From eb3fa9d23f71492a2779b3306b931569947737eb Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sat, 23 Nov 2019 17:25:01 -0600 Subject: [PATCH 001/617] Changed weak target family descriptors to references. - This causes the g_families[] entries to be NULL if the family descriptor is not defined. So the g_families terminator was changed to all Fs and init_families() updated appropriately. - This changed saves quite a bit of .rodata. --- source/target/target_family.c | 76 ++++++++++++++++++----------------- 1 file changed, 39 insertions(+), 37 deletions(-) diff --git a/source/target/target_family.c b/source/target/target_family.c index 1e8096cdb..98fada15f 100644 --- a/source/target/target_family.c +++ b/source/target/target_family.c @@ -43,35 +43,33 @@ const target_family_descriptor_t g_sw_sysresetreq_family = { .soft_reset_type = SYSRESETREQ, }; -//Weakly define family -__attribute__((weak)) -const target_family_descriptor_t g_nxp_kinetis_kseries = {0}; -__attribute__((weak)) -const target_family_descriptor_t g_nxp_kinetis_lseries = {0}; -__attribute__((weak)) -const target_family_descriptor_t g_nxp_kinetis_k32w_series = {0}; -__attribute__((weak)) -const target_family_descriptor_t g_nxp_mimxrt = {0}; -__attribute__((weak)) -const target_family_descriptor_t g_nxp_rapid_iot = {0}; -__attribute__((weak)) -const target_family_descriptor_t g_nordic_nrf51 = {0}; -__attribute__((weak)) -const target_family_descriptor_t g_nordic_nrf52 = {0}; -__attribute__((weak)) -const target_family_descriptor_t g_realtek_rtl8195am = {0}; -__attribute__((weak)) -const target_family_descriptor_t g_ti_family = {0}; -__attribute__((weak)) -const target_family_descriptor_t g_wiznet_family = {0}; -__attribute__((weak)) -const target_family_descriptor_t g_renesas_family = {0}; -__attribute__((weak)) -const target_family_descriptor_t g_toshiba_tz_family = {0}; -__attribute__((weak)) -const target_family_descriptor_t g_ambiq_ama3b1kk = {0}; +// Weak references to family definitions. +extern __WEAK const target_family_descriptor_t g_nxp_kinetis_kseries; +extern __WEAK const target_family_descriptor_t g_nxp_kinetis_lseries; +extern __WEAK const target_family_descriptor_t g_nxp_kinetis_k32w_series; +extern __WEAK const target_family_descriptor_t g_nxp_mimxrt; +extern __WEAK const target_family_descriptor_t g_nxp_rapid_iot; +extern __WEAK const target_family_descriptor_t g_nordic_nrf51; +extern __WEAK const target_family_descriptor_t g_nordic_nrf52; +extern __WEAK const target_family_descriptor_t g_realtek_rtl8195am; +extern __WEAK const target_family_descriptor_t g_ti_family; +extern __WEAK const target_family_descriptor_t g_wiznet_family; +extern __WEAK const target_family_descriptor_t g_renesas_family; +extern __WEAK const target_family_descriptor_t g_toshiba_tz_family; +extern __WEAK const target_family_descriptor_t g_ambiq_ama3b1kk; +//! @brief Terminator value for g_families list. +//! +//! This terminator value is chosen so that weak references to the family descriptors that +//! resolve to NULL at link time do not terminate the list early. +#define FAMILY_LIST_TERMINATOR ((const target_family_descriptor_t *)(0xffffffff)) +//! @brief Default list of family descriptors. +//! +//! init_family() scans this list searching for a family descriptor with an ID that matches +//! the family ID set in the board info or target config structs. Because each of the family +//! descriptors has a weak reference defined above, the entry in this list for a family whose +//! descriptor is not included in the link will resolve to NULL and init_family() can skip it. __attribute__((weak)) const target_family_descriptor_t *g_families[] = { &g_hw_reset_family, @@ -90,7 +88,7 @@ const target_family_descriptor_t *g_families[] = { &g_renesas_family, &g_toshiba_tz_family, &g_ambiq_ama3b1kk, - 0 // list terminator + FAMILY_LIST_TERMINATOR // list terminator }; __attribute__((weak)) @@ -99,21 +97,25 @@ const target_family_descriptor_t *g_target_family = NULL; void init_family(void) { - uint8_t index = 0; - uint16_t family_id = get_family_id(); - if (g_target_family != NULL){ //already set + // Check if the family is already set. + if (g_target_family != NULL) { return; } - while (g_families[index]!=0) { - if (g_families[index]->family_id && (g_families[index]->family_id == family_id)) { + // Scan families table looking for matching family ID. + uint8_t index = 0; + uint16_t family_id = get_family_id(); + + while (g_families[index] != FAMILY_LIST_TERMINATOR) { + if ((g_families[index] != NULL) && (g_families[index]->family_id == family_id)) { g_target_family = g_families[index]; break; } index++; } - if(g_target_family == NULL){ //default family + // Last resort is to use a default family. + if (g_target_family == NULL) { g_target_family = &g_hw_reset_family; } } @@ -137,11 +139,11 @@ uint8_t target_set_state(target_state_t state) swd_set_soft_reset(g_target_family->soft_reset_type); } return swd_set_target_state_sw(state); - }else { + } else { return 1; } } - }else{ + } else { return 0; } } @@ -150,7 +152,7 @@ void swd_set_target_reset(uint8_t asserted) { if (g_target_family && g_target_family->swd_set_target_reset) { g_target_family->swd_set_target_reset(asserted); - }else { + } else { (asserted) ? PIN_nRESET_OUT(0) : PIN_nRESET_OUT(1); } } From 838f1ed05142f9a937de0631181034ed88dea33c Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Mon, 4 Nov 2019 17:04:03 -0600 Subject: [PATCH 002/617] Including cmsis_compiler.h in compiler.h. --- source/daplink/compiler.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/source/daplink/compiler.h b/source/daplink/compiler.h index c4b812892..c9ba3e8f9 100644 --- a/source/daplink/compiler.h +++ b/source/daplink/compiler.h @@ -22,6 +22,8 @@ #ifndef COMPILER_H #define COMPILER_H +#include "cmsis_compiler.h" + #ifdef __cplusplus extern "C" { #endif From 22771bec8da86f01cc9274f539bf05f72486ecf7 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Mon, 4 Nov 2019 17:04:47 -0600 Subject: [PATCH 003/617] Migrated armcc __packed to compiler-independent macros. --- source/usb/usb_cdc.h | 12 ++++++------ source/usb/usb_def.h | 41 +++++++++++++++++++++-------------------- source/usb/usb_hid.h | 4 ++-- source/usb/usb_msc.h | 4 ++-- source/usb/usb_webusb.h | 4 ++-- source/usb/usb_winusb.h | 4 ++-- 6 files changed, 35 insertions(+), 34 deletions(-) diff --git a/source/usb/usb_cdc.h b/source/usb/usb_cdc.h index 570e7b58c..4eb96ec4a 100644 --- a/source/usb/usb_cdc.h +++ b/source/usb/usb_cdc.h @@ -189,7 +189,7 @@ /* Header functional descriptor */ /* (usbcdc11.pdf, 5.2.3.1) */ /* This header must precede any list of class-specific descriptors. */ -typedef __packed struct _CDC_HEADER_DESCRIPTOR { +typedef __PACKED_STRUCT _CDC_HEADER_DESCRIPTOR { U8 bFunctionLength; /* size of this descriptor in bytes */ U8 bDescriptorType; /* CS_INTERFACE descriptor type */ U8 bDescriptorSubtype; /* Header functional descriptor subtype */ @@ -199,7 +199,7 @@ typedef __packed struct _CDC_HEADER_DESCRIPTOR { /* Call management functional descriptor */ /* (usbcdc11.pdf, 5.2.3.2) */ /* Describes the processing of calls for the communication class interface. */ -typedef __packed struct _CDC_CALL_MANAGEMENT_DESCRIPTOR { +typedef __PACKED_STRUCT _CDC_CALL_MANAGEMENT_DESCRIPTOR { U8 bFunctionLength; /* size of this descriptor in bytes */ U8 bDescriptorType; /* CS_INTERFACE descriptor type */ U8 bDescriptorSubtype; /* call management functional descriptor subtype */ @@ -210,7 +210,7 @@ typedef __packed struct _CDC_CALL_MANAGEMENT_DESCRIPTOR { /* Abstract control management functional descriptor */ /* (usbcdc11.pdf, 5.2.3.3) */ /* Describes the command supported by the communication interface class with the Abstract Control Model subclass code. */ -typedef __packed struct _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR { +typedef __PACKED_STRUCT _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR { U8 bFunctionLength; /* size of this descriptor in bytes */ U8 bDescriptorType; /* CS_INTERFACE descriptor type */ U8 bDescriptorSubtype; /* abstract control management functional descriptor subtype */ @@ -220,7 +220,7 @@ typedef __packed struct _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR { /* Union functional descriptors */ /* (usbcdc11.pdf, 5.2.3.8) */ /* Describes the relationship between a group of interfaces that can be considered to form a functional unit. */ -typedef __packed struct _CDC_UNION_DESCRIPTOR { +typedef __PACKED_STRUCT _CDC_UNION_DESCRIPTOR { U8 bFunctionLength; /* size of this descriptor in bytes */ U8 bDescriptorType; /* CS_INTERFACE descriptor type */ U8 bDescriptorSubtype; /* union functional descriptor subtype */ @@ -229,7 +229,7 @@ typedef __packed struct _CDC_UNION_DESCRIPTOR { /* Union functional descriptors with one slave interface */ /* (usbcdc11.pdf, 5.2.3.8) */ -typedef __packed struct _CDC_UNION_1SLAVE_DESCRIPTOR { +typedef __PACKED_STRUCT _CDC_UNION_1SLAVE_DESCRIPTOR { CDC_UNION_DESCRIPTOR sUnion; /* Union functional descriptor */ U8 bSlaveInterfaces[1]; /* Slave interface 0 */ } CDC_UNION_1SLAVE_DESCRIPTOR; @@ -237,7 +237,7 @@ typedef __packed struct _CDC_UNION_1SLAVE_DESCRIPTOR { /* Line coding structure */ /* Format of the data returned when a GetLineCoding request is received */ /* (usbcdc11.pdf, 6.2.13) */ -typedef __packed struct _CDC_LINE_CODING { +typedef __PACKED_STRUCT _CDC_LINE_CODING { U32 dwDTERate; /* Data terminal rate in bits per second */ U8 bCharFormat; /* Number of stop bits */ U8 bParityType; /* Parity bit type */ diff --git a/source/usb/usb_def.h b/source/usb/usb_def.h index 0c9d534ef..f6a5c6b06 100644 --- a/source/usb/usb_def.h +++ b/source/usb/usb_def.h @@ -24,6 +24,7 @@ #pragma anon_unions +#include "compiler.h" #include #include @@ -80,7 +81,7 @@ typedef unsigned int BOOL; #define REQUEST_TO_OTHER 3 /* bmRequestType Definition */ -typedef __packed struct _REQUEST_TYPE { +typedef __PACKED_STRUCT _REQUEST_TYPE { U8 Recipient : 5; /* D4..0: Recipient */ U8 Type : 2; /* D6..5: Type */ U8 Dir : 1; /* D7: Data Phase Txsfer Direction */ @@ -109,19 +110,19 @@ typedef __packed struct _REQUEST_TYPE { #define USB_FEATURE_REMOTE_WAKEUP 1 /* USB Default Control Pipe Setup Packet */ -typedef __packed struct _USB_SETUP_PACKET { +typedef __PACKED_STRUCT _USB_SETUP_PACKET { REQUEST_TYPE bmRequestType; /* bmRequestType */ U8 bRequest; /* bRequest */ - __packed union { + __PACKED_UNION { U16 wValue; /* wValue */ - __packed struct { + __PACKED_STRUCT { U8 wValueL; U8 wValueH; }; }; - __packed union { + __PACKED_UNION { U16 wIndex; /* wIndex */ - __packed struct { + __PACKED_STRUCT { U8 wIndexL; U8 wIndexH; }; @@ -206,7 +207,7 @@ typedef __packed struct _USB_SETUP_PACKET { #define USB_DEVICE_CAPABILITY_WIRELESS_USB_EXT 12 /* USB Standard Device Descriptor */ -typedef __packed struct _USB_DEVICE_DESCRIPTOR { +typedef __PACKED_STRUCT _USB_DEVICE_DESCRIPTOR { U8 bLength; U8 bDescriptorType; U16 bcdUSB; @@ -224,7 +225,7 @@ typedef __packed struct _USB_DEVICE_DESCRIPTOR { } USB_DEVICE_DESCRIPTOR; /* USB 2.0 Device Qualifier Descriptor */ -typedef __packed struct _USB_DEVICE_QUALIFIER_DESCRIPTOR { +typedef __PACKED_STRUCT _USB_DEVICE_QUALIFIER_DESCRIPTOR { U8 bLength; U8 bDescriptorType; U16 bcdUSB; @@ -237,7 +238,7 @@ typedef __packed struct _USB_DEVICE_QUALIFIER_DESCRIPTOR { } USB_DEVICE_QUALIFIER_DESCRIPTOR; /* USB Standard Configuration Descriptor */ -typedef __packed struct _USB_CONFIGURATION_DESCRIPTOR { +typedef __PACKED_STRUCT _USB_CONFIGURATION_DESCRIPTOR { U8 bLength; U8 bDescriptorType; U16 wTotalLength; @@ -249,7 +250,7 @@ typedef __packed struct _USB_CONFIGURATION_DESCRIPTOR { } USB_CONFIGURATION_DESCRIPTOR; /* USB Standard Interface Descriptor */ -typedef __packed struct _USB_INTERFACE_DESCRIPTOR { +typedef __PACKED_STRUCT _USB_INTERFACE_DESCRIPTOR { U8 bLength; U8 bDescriptorType; U8 bInterfaceNumber; @@ -262,7 +263,7 @@ typedef __packed struct _USB_INTERFACE_DESCRIPTOR { } USB_INTERFACE_DESCRIPTOR; /* USB Standard Endpoint Descriptor */ -typedef __packed struct _USB_ENDPOINT_DESCRIPTOR { +typedef __PACKED_STRUCT _USB_ENDPOINT_DESCRIPTOR { U8 bLength; U8 bDescriptorType; U8 bEndpointAddress; @@ -272,20 +273,20 @@ typedef __packed struct _USB_ENDPOINT_DESCRIPTOR { } USB_ENDPOINT_DESCRIPTOR; /* USB String Descriptor */ -typedef __packed struct _USB_STRING_DESCRIPTOR { +typedef __PACKED_STRUCT _USB_STRING_DESCRIPTOR { U8 bLength; U8 bDescriptorType; U16 bString/*[]*/; } USB_STRING_DESCRIPTOR; /* USB Common Descriptor */ -typedef __packed struct _USB_COMMON_DESCRIPTOR { +typedef __PACKED_STRUCT _USB_COMMON_DESCRIPTOR { U8 bLength; U8 bDescriptorType; } USB_COMMON_DESCRIPTOR; /* USB Interface Association Descriptor */ -typedef __packed struct _USB_INTERFACE_ASSOCIATION_DESCRIPTOR { +typedef __PACKED_STRUCT _USB_INTERFACE_ASSOCIATION_DESCRIPTOR { U8 bLength; U8 bDescriptorType; U8 bFirstInterface; @@ -297,15 +298,15 @@ typedef __packed struct _USB_INTERFACE_ASSOCIATION_DESCRIPTOR { } USB_INTERFACE_ASSOCIATION_DESCRIPTOR; /* USB Binary Object Store Descriptor */ -typedef __packed struct _USB_BINARY_OBJECT_STORE_DESCRIPTOR { +typedef __PACKED_STRUCT _USB_BINARY_OBJECT_STORE_DESCRIPTOR { U8 bLength; U8 bDescriptorType; U16 wTotalLength; U8 bNumDeviceCaps; } USB_BINARY_OBJECT_STORE_DESCRIPTOR; -/* Union Functional Descriptor */ -typedef __packed struct _UNION_FUNCTIONAL_DESCRIPTOR { +/* Union Functional Descriptor */ +typedef __PACKED_STRUCT _UNION_FUNCTIONAL_DESCRIPTOR { U8 bLength; U8 bDescriptorType; U8 bDescriptorSubtype; @@ -313,15 +314,15 @@ typedef __packed struct _UNION_FUNCTIONAL_DESCRIPTOR { U8 bSlaveInterface0; } UNION_FUNCTIONAL_DESCRIPTOR; -typedef __packed struct _WINUSB_FUNCTION_SUBSET_HEADER { +typedef __PACKED_STRUCT _WINUSB_FUNCTION_SUBSET_HEADER { U16 wLength; - U16 wDescriptorType; + U16 wDescriptorType; U8 bFirstInterface; U8 bReserved; } WINUSB_FUNCTION_SUBSET_HEADER; /* USB Device Capability Descriptor */ -typedef __packed struct _USB_DEVICE_CAPABILITY_DESCRIPTOR { +typedef __PACKED_STRUCT _USB_DEVICE_CAPABILITY_DESCRIPTOR { U8 bLength; U8 bDescriptorType; U8 bDevCapabilityType; diff --git a/source/usb/usb_hid.h b/source/usb/usb_hid.h index c8150a8dd..4b67dfaff 100644 --- a/source/usb/usb_hid.h +++ b/source/usb/usb_hid.h @@ -42,14 +42,14 @@ /* HID Descriptor */ -typedef __packed struct _HID_DESCRIPTOR { +typedef __PACKED_STRUCT _HID_DESCRIPTOR { U8 bLength; U8 bDescriptorType; U16 bcdHID; U8 bCountryCode; U8 bNumDescriptors; /* Array of one or more descriptors */ - __packed struct _HID_DESCRIPTOR_LIST { + __PACKED_STRUCT _HID_DESCRIPTOR_LIST { U8 bDescriptorType; U16 wDescriptorLength; } DescriptorList[1]; diff --git a/source/usb/usb_msc.h b/source/usb/usb_msc.h index 33658dee5..c3c12090c 100644 --- a/source/usb/usb_msc.h +++ b/source/usb/usb_msc.h @@ -54,7 +54,7 @@ /* Bulk-only Command Block Wrapper */ -typedef __packed struct _MSC_CBW { +typedef __PACKED_STRUCT _MSC_CBW { U32 dSignature; U32 dTag; U32 dDataLength; @@ -65,7 +65,7 @@ typedef __packed struct _MSC_CBW { } MSC_CBW; /* Bulk-only Command Status Wrapper */ -typedef __packed struct _MSC_CSW { +typedef __PACKED_STRUCT _MSC_CSW { U32 dSignature; U32 dTag; U32 dDataResidue; diff --git a/source/usb/usb_webusb.h b/source/usb/usb_webusb.h index 0439f5291..52a3ccafc 100644 --- a/source/usb/usb_webusb.h +++ b/source/usb/usb_webusb.h @@ -29,7 +29,7 @@ #define WEBUSB_URL_TYPE 0x03 /* WebUSB Platform Capability Descriptor */ -typedef __packed struct _WEBUSB_PLATFORM_CAPABILITY_DESCRIPTOR { +typedef __PACKED_STRUCT _WEBUSB_PLATFORM_CAPABILITY_DESCRIPTOR { U8 bLength; U8 bDescriptorType; U8 bDevCapabilityType; @@ -40,7 +40,7 @@ typedef __packed struct _WEBUSB_PLATFORM_CAPABILITY_DESCRIPTOR { U8 iLandingPage; } WEBUSB_PLATFORM_CAPABILITY_DESCRIPTOR; -typedef __packed struct _WEBUSB_URL_DESCRIPTOR { +typedef __PACKED_STRUCT _WEBUSB_URL_DESCRIPTOR { U8 bLength; U8 bDescriptorType; U8 bScheme; diff --git a/source/usb/usb_winusb.h b/source/usb/usb_winusb.h index 9a2b5d43d..5b2dbd3f4 100644 --- a/source/usb/usb_winusb.h +++ b/source/usb/usb_winusb.h @@ -37,7 +37,7 @@ #define WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ 0x07 /* WinUSB Microsoft OS 2.0 descriptor Platform Capability Descriptor */ -typedef __packed struct _WINUSB_PLATFORM_CAPABILITY_DESCRIPTOR { +typedef __PACKED_STRUCT _WINUSB_PLATFORM_CAPABILITY_DESCRIPTOR { U8 bLength; U8 bDescriptorType; U8 bDevCapabilityType; @@ -50,7 +50,7 @@ typedef __packed struct _WINUSB_PLATFORM_CAPABILITY_DESCRIPTOR { } WINUSB_PLATFORM_CAPABILITY_DESCRIPTOR; /* WinUSB Microsoft OS 2.0 descriptor set header */ -typedef __packed struct _WINUSB_DESCRIPTOR_SET_HEADER { +typedef __PACKED_STRUCT _WINUSB_DESCRIPTOR_SET_HEADER { U16 wLength; U16 wDescriptorType; U32 dwWindowsVersion; From 7ace2559c81a22d8f3b65f5878ce349a61a5510b Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Tue, 5 Nov 2019 16:59:30 -0600 Subject: [PATCH 004/617] Convert to __WEAK. - Changed __weak to __WEAK. - Using __WEAK instead of plain attribute. --- source/daplink/cortex_m.c | 5 +- source/daplink/drag-n-drop/flash_intf.c | 11 +- source/daplink/sdk_stub.c | 4 +- source/daplink/util.c | 2 +- source/target/target_board.c | 2 +- source/target/target_family.c | 4 +- source/usb/cdc/usbd_cdc_acm.c | 38 ++-- source/usb/cdc/usbd_core_cdc.c | 4 +- source/usb/hid/usbd_core_hid.c | 6 +- source/usb/hid/usbd_hid.c | 10 +- source/usb/msc/usbd_core_msc.c | 4 +- source/usb/msc/usbd_msc.c | 8 +- source/usb/usb_lib.c | 250 ++++++++++++------------ source/usb/webusb/usbd_core_webusb.c | 2 +- source/usb/winusb/usbd_core_winusb.c | 2 +- 15 files changed, 175 insertions(+), 177 deletions(-) diff --git a/source/daplink/cortex_m.c b/source/daplink/cortex_m.c index de2096f63..a9f0735df 100644 --- a/source/daplink/cortex_m.c +++ b/source/daplink/cortex_m.c @@ -3,7 +3,7 @@ * @brief ARM Cortex-Mx cpu functions * * DAPLink Interface Firmware - * Copyright (c) 2009-2017, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -21,8 +21,7 @@ #include "cortex_m.h" -__attribute__((weak)) -void SystemReset(void) +__WEAK void SystemReset(void) { NVIC_SystemReset(); } diff --git a/source/daplink/drag-n-drop/flash_intf.c b/source/daplink/drag-n-drop/flash_intf.c index 41414c418..807dc3c5f 100644 --- a/source/daplink/drag-n-drop/flash_intf.c +++ b/source/daplink/drag-n-drop/flash_intf.c @@ -20,11 +20,8 @@ */ #include "flash_intf.h" +#include "compiler.h" - -__attribute__((weak)) -const flash_intf_t *const flash_intf_iap_protected = 0; -__attribute__((weak)) -const flash_intf_t *const flash_intf_target = 0; -__attribute__((weak)) -const flash_intf_t *const flash_intf_target_custom = 0; +__WEAK const flash_intf_t *const flash_intf_iap_protected = 0; +__WEAK const flash_intf_t *const flash_intf_target = 0; +__WEAK const flash_intf_t *const flash_intf_target_custom = 0; diff --git a/source/daplink/sdk_stub.c b/source/daplink/sdk_stub.c index ca4f17bdc..e9116a636 100644 --- a/source/daplink/sdk_stub.c +++ b/source/daplink/sdk_stub.c @@ -19,7 +19,9 @@ * limitations under the License. */ -__weak void sdk_init() +#include "device.h" + +__WEAK void sdk_init() { // Do nothing } diff --git a/source/daplink/util.c b/source/daplink/util.c index 8214ff2f0..c29a3088c 100644 --- a/source/daplink/util.c +++ b/source/daplink/util.c @@ -26,7 +26,7 @@ #include "cortex_m.h" //remove dependency from vfs_manager -__attribute__((weak)) void vfs_mngr_fs_remount(void) {} +__WEAK void vfs_mngr_fs_remount(void) {} uint32_t util_write_hex8(char *str, uint8_t value) { diff --git a/source/target/target_board.c b/source/target/target_board.c index 8142af14b..8451f7776 100644 --- a/source/target/target_board.c +++ b/source/target/target_board.c @@ -23,7 +23,7 @@ #include "target_board.h" // Default empty board info. -__attribute__((weak)) +__WEAK const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "0000", diff --git a/source/target/target_family.c b/source/target/target_family.c index 98fada15f..4eb110629 100644 --- a/source/target/target_family.c +++ b/source/target/target_family.c @@ -70,7 +70,7 @@ extern __WEAK const target_family_descriptor_t g_ambiq_ama3b1kk; //! the family ID set in the board info or target config structs. Because each of the family //! descriptors has a weak reference defined above, the entry in this list for a family whose //! descriptor is not included in the link will resolve to NULL and init_family() can skip it. -__attribute__((weak)) +__WEAK const target_family_descriptor_t *g_families[] = { &g_hw_reset_family, &g_sw_vectreset_family, @@ -91,7 +91,7 @@ const target_family_descriptor_t *g_families[] = { FAMILY_LIST_TERMINATOR // list terminator }; -__attribute__((weak)) +__WEAK const target_family_descriptor_t *g_target_family = NULL; diff --git a/source/usb/cdc/usbd_cdc_acm.c b/source/usb/cdc/usbd_cdc_acm.c index 5bf005108..df28107b3 100644 --- a/source/usb/cdc/usbd_cdc_acm.c +++ b/source/usb/cdc/usbd_cdc_acm.c @@ -55,27 +55,27 @@ CDC_LINE_CODING line_coding; /*!< Communication settings */ /* Functions that should be provided by user to use standard Virtual COM port functionality */ -__weak int32_t USBD_CDC_ACM_PortInitialize(void) +__WEAK int32_t USBD_CDC_ACM_PortInitialize(void) { return (0); } -__weak int32_t USBD_CDC_ACM_PortUninitialize(void) +__WEAK int32_t USBD_CDC_ACM_PortUninitialize(void) { return (0); } -__weak int32_t USBD_CDC_ACM_PortReset(void) +__WEAK int32_t USBD_CDC_ACM_PortReset(void) { return (0); } -__weak int32_t USBD_CDC_ACM_PortSetLineCoding(CDC_LINE_CODING *line_coding) +__WEAK int32_t USBD_CDC_ACM_PortSetLineCoding(CDC_LINE_CODING *line_coding) { return (0); } -__weak int32_t USBD_CDC_ACM_PortGetLineCoding(CDC_LINE_CODING *line_coding) +__WEAK int32_t USBD_CDC_ACM_PortGetLineCoding(CDC_LINE_CODING *line_coding) { return (0); } -__weak int32_t USBD_CDC_ACM_PortSetControlLineState(uint16_t ctrl_bmp) +__WEAK int32_t USBD_CDC_ACM_PortSetControlLineState(uint16_t ctrl_bmp) { return (0); } @@ -86,7 +86,7 @@ int32_t USBD_CDC_ACM_DataSend(const uint8_t *buf, int32_t len); int32_t USBD_CDC_ACM_PutChar(const uint8_t ch); int32_t USBD_CDC_ACM_DataRead(uint8_t *buf, int32_t len); int32_t USBD_CDC_ACM_GetChar(void); -__weak int32_t USBD_CDC_ACM_DataReceived(int32_t len) +__WEAK int32_t USBD_CDC_ACM_DataReceived(int32_t len) { return (0); } @@ -95,27 +95,27 @@ int32_t USBD_CDC_ACM_Notify(uint16_t stat); /* Functions handling CDC ACM requests (can be overridden to provide custom handling of CDC ACM requests) */ -__weak int32_t USBD_CDC_ACM_SendEncapsulatedCommand(void) +__WEAK int32_t USBD_CDC_ACM_SendEncapsulatedCommand(void) { return (0); } -__weak int32_t USBD_CDC_ACM_GetEncapsulatedResponse(void) +__WEAK int32_t USBD_CDC_ACM_GetEncapsulatedResponse(void) { return (0); } -__weak int32_t USBD_CDC_ACM_SetCommFeature(uint16_t feat) +__WEAK int32_t USBD_CDC_ACM_SetCommFeature(uint16_t feat) { return (0); } -__weak int32_t USBD_CDC_ACM_GetCommFeature(uint16_t feat) +__WEAK int32_t USBD_CDC_ACM_GetCommFeature(uint16_t feat) { return (0); } -__weak int32_t USBD_CDC_ACM_ClearCommFeature(uint16_t feat) +__WEAK int32_t USBD_CDC_ACM_ClearCommFeature(uint16_t feat) { return (0); } -__weak int32_t USBD_CDC_ACM_SendBreak(uint16_t dur) +__WEAK int32_t USBD_CDC_ACM_SendBreak(uint16_t dur) { return (0); } @@ -137,7 +137,7 @@ static void USBD_CDC_ACM_EP_BULKIN_HandleData(void); \return 1 Function succeeded. */ -__weak int32_t USBD_CDC_ACM_Initialize(void) +__WEAK int32_t USBD_CDC_ACM_Initialize(void) { data_send_access = 0; data_send_active = 0; @@ -170,7 +170,7 @@ __weak int32_t USBD_CDC_ACM_Initialize(void) \return 1 Function succeeded. */ -__weak int32_t USBD_CDC_ACM_Uninitialization(void) +__WEAK int32_t USBD_CDC_ACM_Uninitialization(void) { return (USBD_CDC_ACM_PortUninitialize()); } @@ -188,7 +188,7 @@ __weak int32_t USBD_CDC_ACM_Uninitialization(void) \return 1 Function succeeded. */ -__weak int32_t USBD_CDC_ACM_Reset(void) +__WEAK int32_t USBD_CDC_ACM_Reset(void) { data_send_access = 0; data_send_active = 0; @@ -222,7 +222,7 @@ __weak int32_t USBD_CDC_ACM_Reset(void) \return 1 Function succeeded. */ -__weak int32_t USBD_CDC_ACM_SetLineCoding(void) +__WEAK int32_t USBD_CDC_ACM_SetLineCoding(void) { line_coding.dwDTERate = (USBD_EP0Buf[0] << 0) | (USBD_EP0Buf[1] << 8) | @@ -244,7 +244,7 @@ __weak int32_t USBD_CDC_ACM_SetLineCoding(void) \return 1 Function succeeded. */ -__weak int32_t USBD_CDC_ACM_GetLineCoding(void) +__WEAK int32_t USBD_CDC_ACM_GetLineCoding(void) { if (USBD_CDC_ACM_PortGetLineCoding(&line_coding)) { USBD_EP0Buf[0] = (line_coding.dwDTERate >> 0) & 0xFF; @@ -273,7 +273,7 @@ __weak int32_t USBD_CDC_ACM_GetLineCoding(void) \return 1 Function succeeded. */ -__weak int32_t USBD_CDC_ACM_SetControlLineState(uint16_t ctrl_bmp) +__WEAK int32_t USBD_CDC_ACM_SetControlLineState(uint16_t ctrl_bmp) { control_line_state = ctrl_bmp; return (USBD_CDC_ACM_PortSetControlLineState(ctrl_bmp)); diff --git a/source/usb/cdc/usbd_core_cdc.c b/source/usb/cdc/usbd_core_cdc.c index fd044d66c..11fe2f405 100644 --- a/source/usb/cdc/usbd_core_cdc.c +++ b/source/usb/cdc/usbd_core_cdc.c @@ -31,7 +31,7 @@ * Return Value: TRUE - Setup class request ok, FALSE - Setup class request not supported */ -__weak BOOL USBD_EndPoint0_Setup_CDC_ReqToIF(void) +__WEAK BOOL USBD_EndPoint0_Setup_CDC_ReqToIF(void) { if ((USBD_SetupPacket.wIndexL == usbd_cdc_acm_cif_num) || /* IF number correct? */ (USBD_SetupPacket.wIndexL == usbd_cdc_acm_dif_num)) { @@ -111,7 +111,7 @@ __weak BOOL USBD_EndPoint0_Setup_CDC_ReqToIF(void) * Return Value: TRUE - Out class request ok, FALSE - Out class request not supported */ -__weak BOOL USBD_EndPoint0_Out_CDC_ReqToIF(void) +__WEAK BOOL USBD_EndPoint0_Out_CDC_ReqToIF(void) { if ((USBD_SetupPacket.wIndexL == usbd_cdc_acm_cif_num) || /* IF number correct? */ (USBD_SetupPacket.wIndexL == usbd_cdc_acm_dif_num)) { diff --git a/source/usb/hid/usbd_core_hid.c b/source/usb/hid/usbd_core_hid.c index af948ebac..a77f8fff9 100644 --- a/source/usb/hid/usbd_core_hid.c +++ b/source/usb/hid/usbd_core_hid.c @@ -31,7 +31,7 @@ * Return Value: TRUE - Success, FALSE - Error */ -__weak BOOL USBD_ReqGetDescriptor_HID(U8 **pD, U32 *len) +__WEAK BOOL USBD_ReqGetDescriptor_HID(U8 **pD, U32 *len) { switch (USBD_SetupPacket.wValueH) { case HID_HID_DESCRIPTOR_TYPE: @@ -81,7 +81,7 @@ __weak BOOL USBD_ReqGetDescriptor_HID(U8 **pD, U32 *len) * Return Value: TRUE - Setup class request ok, FALSE - Setup class request not supported */ -__weak BOOL USBD_EndPoint0_Setup_HID_ReqToIF(void) +__WEAK BOOL USBD_EndPoint0_Setup_HID_ReqToIF(void) { if (USBD_SetupPacket.wIndexL == usbd_hid_if_num || USBD_SetupPacket.wIndexL == usbd_webusb_if_num) { @@ -155,7 +155,7 @@ __weak BOOL USBD_EndPoint0_Setup_HID_ReqToIF(void) * Return Value: TRUE - Out class request ok, FALSE - Out class request not supported */ -__weak BOOL USBD_EndPoint0_Out_HID_ReqToIF(void) +__WEAK BOOL USBD_EndPoint0_Out_HID_ReqToIF(void) { if (USBD_SetupPacket.wIndexL == usbd_hid_if_num || USBD_SetupPacket.wIndexL == usbd_webusb_if_num) { diff --git a/source/usb/hid/usbd_hid.c b/source/usb/hid/usbd_hid.c index 218858e2b..980c91003 100644 --- a/source/usb/hid/usbd_hid.c +++ b/source/usb/hid/usbd_hid.c @@ -43,23 +43,23 @@ U16 DataFeatReceLen; /* Dummy Weak Functions that need to be provided by user */ -__weak void usbd_hid_init(void) +__WEAK void usbd_hid_init(void) { } -__weak int usbd_hid_get_report(U8 rtype, U8 rid, U8 *buf, U8 req) +__WEAK int usbd_hid_get_report(U8 rtype, U8 rid, U8 *buf, U8 req) { return (0); }; -__weak void usbd_hid_set_report(U8 rtype, U8 rid, U8 *buf, int len, U8 req) +__WEAK void usbd_hid_set_report(U8 rtype, U8 rid, U8 *buf, int len, U8 req) { } -__weak U8 usbd_hid_get_protocol(void) +__WEAK U8 usbd_hid_get_protocol(void) { return (0); }; -__weak void usbd_hid_set_protocol(U8 protocol) +__WEAK void usbd_hid_set_protocol(U8 protocol) { }; diff --git a/source/usb/msc/usbd_core_msc.c b/source/usb/msc/usbd_core_msc.c index d47ed0745..eec331119 100644 --- a/source/usb/msc/usbd_core_msc.c +++ b/source/usb/msc/usbd_core_msc.c @@ -31,7 +31,7 @@ * Return Value: None */ -__weak void USBD_ReqClrFeature_MSC(U32 EPNum) +__WEAK void USBD_ReqClrFeature_MSC(U32 EPNum) { USBD_MSC_ClrStallEP(EPNum); } @@ -43,7 +43,7 @@ __weak void USBD_ReqClrFeature_MSC(U32 EPNum) * Return Value: TRUE - Setup class request ok, FALSE - Setup class request not supported */ -__weak BOOL USBD_EndPoint0_Setup_MSC_ReqToIF(void) +__WEAK BOOL USBD_EndPoint0_Setup_MSC_ReqToIF(void) { if (USBD_SetupPacket.wIndexL == usbd_msc_if_num) { /* IF number correct? */ switch (USBD_SetupPacket.bRequest) { diff --git a/source/usb/msc/usbd_msc.c b/source/usb/msc/usbd_msc.c index fab86af9c..9d54131d5 100644 --- a/source/usb/msc/usbd_msc.c +++ b/source/usb/msc/usbd_msc.c @@ -48,19 +48,19 @@ U32 BulkLen; /* Bulk In/Out Length */ /* Dummy Weak Functions that need to be provided by user */ -__weak void usbd_msc_init() +__WEAK void usbd_msc_init() { } -__weak void usbd_msc_read_sect(U32 block, U8 *buf, U32 num_of_blocks) +__WEAK void usbd_msc_read_sect(U32 block, U8 *buf, U32 num_of_blocks) { } -__weak void usbd_msc_write_sect(U32 block, U8 *buf, U32 num_of_blocks) +__WEAK void usbd_msc_write_sect(U32 block, U8 *buf, U32 num_of_blocks) { } -__weak void usbd_msc_start_stop(BOOL start) +__WEAK void usbd_msc_start_stop(BOOL start) { } diff --git a/source/usb/usb_lib.c b/source/usb/usb_lib.c index ca177d9f2..3540999c7 100644 --- a/source/usb/usb_lib.c +++ b/source/usb/usb_lib.c @@ -1060,7 +1060,7 @@ void USBD_Reset_Event(void) #endif #if (USBD_MSC_ENABLE) USBD_MSC_Reset_Event(); -#endif +#endif } #endif #endif /* ((USBD_CDC_ACM_ENABLE)) */ @@ -1086,13 +1086,13 @@ void USBD_SOF_Event(void) #endif /* ((USBD_HID_ENABLE) || (USBD_ADC_ENABLE) || (USBD_CDC_ACM_ENABLE) || (USBD_CLS_ENABLE)) */ /* USB Device - Device Events Callback Functions */ -__weak void USBD_Power_Event(BOOL power); -__weak void USBD_Reset_Event(void); -__weak void USBD_Suspend_Event(void); -__weak void USBD_Resume_Event(void); -__weak void USBD_WakeUp_Event(void); -__weak void USBD_SOF_Event(void); -__weak void USBD_Error_Event(U32 error); +__WEAK void USBD_Power_Event(BOOL power); +__WEAK void USBD_Reset_Event(void); +__WEAK void USBD_Suspend_Event(void); +__WEAK void USBD_Resume_Event(void); +__WEAK void USBD_WakeUp_Event(void); +__WEAK void USBD_SOF_Event(void); +__WEAK void USBD_Error_Event(U32 error); /* USB Device - Device Events Callback Pointers */ void (* const USBD_P_Power_Event)(BOOL power) = USBD_Power_Event; @@ -1106,49 +1106,49 @@ void (* const USBD_P_Error_Event)(U32 error) = USBD_Error_Event; /* USB Device - Endpoint Events Callback Functions */ extern void USBD_EndPoint0(U32 event); #ifndef USBD_EndPoint1 -__weak void USBD_EndPoint1(U32 event); +__WEAK void USBD_EndPoint1(U32 event); #endif #ifndef USBD_EndPoint2 -__weak void USBD_EndPoint2(U32 event); +__WEAK void USBD_EndPoint2(U32 event); #endif #ifndef USBD_EndPoint3 -__weak void USBD_EndPoint3(U32 event); +__WEAK void USBD_EndPoint3(U32 event); #endif #ifndef USBD_EndPoint4 -__weak void USBD_EndPoint4(U32 event); +__WEAK void USBD_EndPoint4(U32 event); #endif #ifndef USBD_EndPoint5 -__weak void USBD_EndPoint5(U32 event); +__WEAK void USBD_EndPoint5(U32 event); #endif #ifndef USBD_EndPoint6 -__weak void USBD_EndPoint6(U32 event); +__WEAK void USBD_EndPoint6(U32 event); #endif #ifndef USBD_EndPoint7 -__weak void USBD_EndPoint7(U32 event); +__WEAK void USBD_EndPoint7(U32 event); #endif #ifndef USBD_EndPoint8 -__weak void USBD_EndPoint8(U32 event); +__WEAK void USBD_EndPoint8(U32 event); #endif #ifndef USBD_EndPoint9 -__weak void USBD_EndPoint9(U32 event); +__WEAK void USBD_EndPoint9(U32 event); #endif #ifndef USBD_EndPoint10 -__weak void USBD_EndPoint10(U32 event); +__WEAK void USBD_EndPoint10(U32 event); #endif #ifndef USBD_EndPoint11 -__weak void USBD_EndPoint11(U32 event); +__WEAK void USBD_EndPoint11(U32 event); #endif #ifndef USBD_EndPoint12 -__weak void USBD_EndPoint12(U32 event); +__WEAK void USBD_EndPoint12(U32 event); #endif #ifndef USBD_EndPoint13 -__weak void USBD_EndPoint13(U32 event); +__WEAK void USBD_EndPoint13(U32 event); #endif #ifndef USBD_EndPoint14 -__weak void USBD_EndPoint14(U32 event); +__WEAK void USBD_EndPoint14(U32 event); #endif #ifndef USBD_EndPoint15 -__weak void USBD_EndPoint15(U32 event); +__WEAK void USBD_EndPoint15(U32 event); #endif /* USB Device - Endpoint Events Callback Pointers */ @@ -1172,9 +1172,9 @@ void (* const USBD_P_EP[16])(U32 event) = { }; /* USB Device - Core Events Callback Functions */ -__weak void USBD_Configure_Event(void); -__weak void USBD_Interface_Event(void); -__weak void USBD_Feature_Event(void); +__WEAK void USBD_Configure_Event(void); +__WEAK void USBD_Interface_Event(void); +__WEAK void USBD_Feature_Event(void); /* USB Device - Core Events Callback Pointers */ void (* const USBD_P_Configure_Event)(void) = USBD_Configure_Event; @@ -1185,7 +1185,7 @@ void (* const USBD_P_Feature_Event)(void) = USBD_Feature_Event; const BOOL __rtx = __TRUE; #if ((USBD_HID_ENABLE) || (USBD_ADC_ENABLE) || (USBD_CDC_ACM_ENABLE) || (USBD_CLS_ENABLE)) -__weak void USBD_RTX_Device(void) +__WEAK void USBD_RTX_Device(void) { U16 evt; @@ -1199,7 +1199,7 @@ __weak void USBD_RTX_Device(void) #endif #if (USBD_MSC_ENABLE) USBD_MSC_Reset_Event(); -#endif +#endif } if (evt & USBD_EVT_SOF) { @@ -1219,7 +1219,7 @@ __weak void USBD_RTX_Device(void) } } #else -__weak void USBD_RTX_Device(void); +__WEAK void USBD_RTX_Device(void); #endif /* USB Device - Device Events Callback Pointer */ @@ -1228,53 +1228,53 @@ void (* const USBD_RTX_P_Device)(void) = USBD_RTX_Device; /* USB Device Endpoint Events Callback Functions */ extern void USBD_RTX_EndPoint0(void); #ifndef USBD_RTX_EndPoint1 -__weak void USBD_RTX_EndPoint1(void); +__WEAK void USBD_RTX_EndPoint1(void); #endif #ifndef USBD_RTX_EndPoint2 -__weak void USBD_RTX_EndPoint2(void); +__WEAK void USBD_RTX_EndPoint2(void); #endif #ifndef USBD_RTX_EndPoint3 -__weak void USBD_RTX_EndPoint3(void); +__WEAK void USBD_RTX_EndPoint3(void); #endif #ifndef USBD_RTX_EndPoint4 -__weak void USBD_RTX_EndPoint4(void); +__WEAK void USBD_RTX_EndPoint4(void); #endif #ifndef USBD_RTX_EndPoint5 -__weak void USBD_RTX_EndPoint5(void); +__WEAK void USBD_RTX_EndPoint5(void); #endif #ifndef USBD_RTX_EndPoint6 -__weak void USBD_RTX_EndPoint6(void); +__WEAK void USBD_RTX_EndPoint6(void); #endif #ifndef USBD_RTX_EndPoint7 -__weak void USBD_RTX_EndPoint7(void); +__WEAK void USBD_RTX_EndPoint7(void); #endif #ifndef USBD_RTX_EndPoint8 -__weak void USBD_RTX_EndPoint8(void); +__WEAK void USBD_RTX_EndPoint8(void); #endif #ifndef USBD_RTX_EndPoint9 -__weak void USBD_RTX_EndPoint9(void); +__WEAK void USBD_RTX_EndPoint9(void); #endif #ifndef USBD_RTX_EndPoint10 -__weak void USBD_RTX_EndPoint10(void); +__WEAK void USBD_RTX_EndPoint10(void); #endif #ifndef USBD_RTX_EndPoint11 -__weak void USBD_RTX_EndPoint11(void); +__WEAK void USBD_RTX_EndPoint11(void); #endif #ifndef USBD_RTX_EndPoint12 -__weak void USBD_RTX_EndPoint12(void); +__WEAK void USBD_RTX_EndPoint12(void); #endif #ifndef USBD_RTX_EndPoint13 -__weak void USBD_RTX_EndPoint13(void); +__WEAK void USBD_RTX_EndPoint13(void); #endif #ifndef USBD_RTX_EndPoint14 -__weak void USBD_RTX_EndPoint14(void); +__WEAK void USBD_RTX_EndPoint14(void); #endif #ifndef USBD_RTX_EndPoint15 -__weak void USBD_RTX_EndPoint15(void); +__WEAK void USBD_RTX_EndPoint15(void); #endif #if (USBD_HID_ENABLE) -__weak void USBD_RTX_Core(void) +__WEAK void USBD_RTX_Core(void) { U16 evt; @@ -1288,7 +1288,7 @@ __weak void USBD_RTX_Core(void) } } #else -__weak void USBD_RTX_Core(void); +__WEAK void USBD_RTX_Core(void); #endif /* USB Device - Core Events Callback Pointer */ @@ -1334,7 +1334,7 @@ const BOOL __rtx = __FALSE; void usbd_os_evt_set(U16 event_flags, U32 task) { - + } U16 usbd_os_evt_get(void) { @@ -1587,7 +1587,7 @@ void USBD_RTX_TaskInit(void) #define USBD_HID_DESC_OFS (USB_CONFIGUARTION_DESC_SIZE + USB_INTERFACE_DESC_SIZE + \ USBD_MSC_ENABLE * USBD_MSC_DESC_LEN + USBD_CDC_ACM_ENABLE * USBD_CDC_ACM_DESC_LEN) - + #define USBD_WTOTALLENGTH_MAX (USB_CONFIGUARTION_DESC_SIZE + \ USBD_CDC_ACM_DESC_LEN * USBD_CDC_ACM_ENABLE + \ USBD_HID_DESC_LEN * USBD_HID_ENABLE + \ @@ -1610,7 +1610,7 @@ void USBD_RTX_TaskInit(void) 7 IN7 OUT7 */ -__weak \ +__WEAK \ const U8 USBD_HID_ReportDescriptor[] = { HID_UsagePageVendor(0x00), HID_Usage(0x01), @@ -1642,14 +1642,14 @@ const U8 USBD_HID_ReportDescriptor[] = { HID_EndCollection, }; -__weak \ +__WEAK \ const U16 USBD_HID_ReportDescriptorSize = sizeof(USBD_HID_ReportDescriptor); -__weak \ +__WEAK \ U16 USBD_HID_DescriptorOffset = USBD_HID_DESC_OFS; /* USB Device Standard Descriptor */ -__weak \ +__WEAK \ const U8 USBD_DeviceDescriptor[] = { USB_DEVICE_DESC_SIZE, /* bLength */ USB_DEVICE_DESCRIPTOR_TYPE, /* bDescriptorType */ @@ -1685,7 +1685,7 @@ const U8 USBD_DeviceDescriptor[] = { #if (USBD_HS_ENABLE) /* USB Device Qualifier Descriptor (for Full Speed) */ -__weak \ +__WEAK \ const U8 USBD_DeviceQualifier[] = { USB_DEVICE_QUALI_SIZE, /* bLength */ USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE, /* bDescriptorType */ @@ -1703,7 +1703,7 @@ const U8 USBD_DeviceQualifier[] = { }; /* USB Device Qualifier Descriptor for High Speed */ -__weak \ +__WEAK \ const U8 USBD_DeviceQualifier_HS[] = { USB_DEVICE_QUALI_SIZE, /* bLength */ USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE, /* bDescriptorType */ @@ -1721,11 +1721,11 @@ const U8 USBD_DeviceQualifier_HS[] = { }; #else /* USB Device Qualifier Descriptor (for Full Speed) */ -__weak \ +__WEAK \ const U8 USBD_DeviceQualifier[] = { 0 }; /* USB Device Qualifier Descriptor for High Speed */ -__weak \ +__WEAK \ const U8 USBD_DeviceQualifier_HS[] = { 0 }; #endif @@ -1741,24 +1741,24 @@ U8 USBD_WinUSBDescriptorSetDescriptor[] = { WBVAL(WINUSB_SET_HEADER_DESCRIPTOR_TYPE), /* wDescriptorType */ 0x00, 0x00, 0x03, 0x06, /* >= Win 8.1 */ /* dwWindowsVersion*/ WBVAL(USBD_WINUSB_DESC_SET_LEN), /* wDescriptorSetTotalLength */ -#if (USBD_WEBUSB_ENABLE) - WBVAL(WINUSB_FUNCTION_SUBSET_HEADER_SIZE),// wLength - WBVAL(WINUSB_SUBSET_HEADER_FUNCTION_TYPE),// wDescriptorType +#if (USBD_WEBUSB_ENABLE) + WBVAL(WINUSB_FUNCTION_SUBSET_HEADER_SIZE),// wLength + WBVAL(WINUSB_SUBSET_HEADER_FUNCTION_TYPE),// wDescriptorType 0, // bFirstInterface USBD_WINUSB_IF_NUM - 0, // bReserved - WBVAL(FUNCTION_SUBSET_LEN), // wSubsetLength - WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_SIZE), // wLength - WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_TYPE), // wDescriptorType + 0, // bReserved + WBVAL(FUNCTION_SUBSET_LEN), // wSubsetLength + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_SIZE), // wLength + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_TYPE), // wDescriptorType 'W', 'I', 'N', 'U', 'S', 'B', 0, 0, // CompatibleId 0, 0, 0, 0, 0, 0, 0, 0, // SubCompatibleId - WBVAL(DEVICE_INTERFACE_GUIDS_FEATURE_LEN),// wLength - WBVAL(WINUSB_FEATURE_REG_PROPERTY_TYPE), // wDescriptorType - WBVAL(WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ), // wPropertyDataType - WBVAL(42), // wPropertyNameLength + WBVAL(DEVICE_INTERFACE_GUIDS_FEATURE_LEN),// wLength + WBVAL(WINUSB_FEATURE_REG_PROPERTY_TYPE), // wDescriptorType + WBVAL(WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ), // wPropertyDataType + WBVAL(42), // wPropertyNameLength 'D',0,'e',0,'v',0,'i',0,'c',0,'e',0, 'I',0,'n',0,'t',0,'e',0,'r',0,'f',0,'a',0,'c',0,'e',0, 'G',0,'U',0,'I',0,'D',0,'s',0,0,0, - WBVAL(80), // wPropertyDataLength + WBVAL(80), // wPropertyDataLength '{',0, '9',0,'2',0,'C',0,'E',0,'6',0,'4',0,'6',0,'2',0,'-',0, '9',0,'C',0,'7',0,'7',0,'-',0, @@ -1766,8 +1766,8 @@ U8 USBD_WinUSBDescriptorSetDescriptor[] = { '9',0,'3',0,'3',0,'B',0,'-', 0,'3',0,'1',0,'C',0,'B',0,'9',0,'C',0,'5',0,'A',0,'A',0,'3',0,'B',0,'9',0, '}',0,0,0,0,0, -#endif -#if (USBD_BULK_ENABLE) +#endif +#if (USBD_BULK_ENABLE) WBVAL(WINUSB_FUNCTION_SUBSET_HEADER_SIZE),/* wLength */ WBVAL(WINUSB_SUBSET_HEADER_FUNCTION_TYPE),/* wDescriptorType */ 0, /* bFirstInterface USBD_BULK_IF_NUM*/ @@ -1792,7 +1792,7 @@ U8 USBD_WinUSBDescriptorSetDescriptor[] = { 'A',0,'A',0,'3',0,'6',0,'-', 0,'1',0,'A',0,'A',0,'E',0,'4',0,'6',0,'4',0,'6',0,'3',0,'7',0,'7',0,'6',0, '}',0,0,0,0,0, -#endif +#endif }; #else @@ -1818,7 +1818,7 @@ BOOL USBD_EndPoint0_Setup_WinUSB_ReqToDevice(void) USBD_WEBUSB_DESC_LEN * USBD_WEBUSB_ENABLE + \ USBD_WINUSB_DESC_LEN * USBD_WINUSB_ENABLE) -__weak \ +__WEAK \ const U8 USBD_BinaryObjectStoreDescriptor[] = { USB_BOS_DESC_SIZE, /* bLength */ USB_BINARY_OBJECT_STORE_DESCRIPTOR_TYPE,/* bDescriptorType */ @@ -1854,7 +1854,7 @@ const U8 USBD_BinaryObjectStoreDescriptor[] = { }; #else -__weak \ +__WEAK \ const U8 USBD_BinaryObjectStoreDescriptor[] = { 0 }; #endif @@ -2017,7 +2017,7 @@ const U8 USBD_BinaryObjectStoreDescriptor[] = { 0 }; USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ \ WBVAL(USBD_MSC_HS_WMAXPACKETSIZE), /* wMaxPacketSize */ \ USBD_MSC_HS_BINTERVAL, /* bInterval */ - + #define BULK_DESC \ /* Interface, Alternate Setting 0, MSC Class */ \ USB_INTERFACE_DESC_SIZE, /* bLength */ \ @@ -2045,7 +2045,7 @@ const U8 USBD_BinaryObjectStoreDescriptor[] = { 0 }; USB_ENDPOINT_IN(USBD_BULK_EP_BULKIN), /* bEndpointAddress */ \ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ \ WBVAL(USBD_BULK_WMAXPACKETSIZE), /* wMaxPacketSize */ \ - 0x00, /* bInterval: ignore for Bulk transfer */ + 0x00, /* bInterval: ignore for Bulk transfer */ #define BULK_EP_HS /* MSC Endpoints for Low-speed/Full-speed */ \ /* Endpoint, EP Bulk OUT */ \ @@ -2062,7 +2062,7 @@ const U8 USBD_BinaryObjectStoreDescriptor[] = { 0 }; USB_ENDPOINT_IN(USBD_BULK_EP_BULKIN),/* bEndpointAddress */ \ USB_ENDPOINT_TYPE_BULK, /* bmAttributes */ \ WBVAL(USBD_BULK_HS_WMAXPACKETSIZE), /* wMaxPacketSize */ \ - 0x00, /* bInterval: ignore for Bulk transfer */ + 0x00, /* bInterval: ignore for Bulk transfer */ #define ADC_DESC_IAD(first,num_of_ifs) /* ADC: Interface Association Descriptor */ \ USB_INTERFACE_ASSOC_DESC_SIZE, /* bLength */ \ @@ -2323,16 +2323,16 @@ const U8 USBD_BinaryObjectStoreDescriptor[] = { 0 }; /* USB Device Configuration Descriptor (for Full Speed) */ /* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor) */ -__weak \ +__WEAK \ U8 USBD_ConfigDescriptor[200] = { 0 }; #if (USBD_HS_ENABLE == 0) /* If High-speed not enabled, declare dummy descriptors for High-speed */ -__weak \ +__WEAK \ U8 USBD_ConfigDescriptor_HS[] = { 0 }; #else /* USB Device Configuration Descriptor (for High Speed) */ /* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor) */ -__weak \ +__WEAK \ U8 USBD_ConfigDescriptor_HS[200] = { 0 }; #endif @@ -2348,7 +2348,7 @@ U8 USBD_ConfigDescriptor_HS[200] = { 0 }; #define USBD_STR_VAL(n) \ { sizeof(USBD_##n), USB_STRING_DESCRIPTOR_TYPE, USBD_##n } -__weak \ +__WEAK \ const struct { struct { U8 len; @@ -2445,7 +2445,7 @@ const struct { USBD_##n \ } -__weak \ +__WEAK \ struct { WEBUSB_URL_DEF(WEBUSB_LANDING_URL); WEBUSB_URL_DEF(WEBUSB_ORIGIN_URL); @@ -2471,26 +2471,26 @@ extern uint8_t flash_algo_valid(void); static U16 start_desc_fill(U8 * config_desc, U8 * config_desc_hs, U8 if_num) { U8 * pD = 0; - const U8 start_desc[] = { + const U8 start_desc[] = { /* Configuration 1 */ - USB_CONFIGUARTION_DESC_SIZE, // bLength - USB_CONFIGURATION_DESCRIPTOR_TYPE, // bDescriptorType - WBVAL(USBD_WTOTALLENGTH_MAX), // wTotalLength - USBD_IF_NUM_MAX, // bNumInterfaces - 0x01, // bConfigurationValue: 0x01 is used to select this configuration - 0x00, // iConfiguration: no string to describe this configuration - USBD_CFGDESC_BMATTRIBUTES | // bmAttributes + USB_CONFIGUARTION_DESC_SIZE, // bLength + USB_CONFIGURATION_DESCRIPTOR_TYPE, // bDescriptorType + WBVAL(USBD_WTOTALLENGTH_MAX), // wTotalLength + USBD_IF_NUM_MAX, // bNumInterfaces + 0x01, // bConfigurationValue: 0x01 is used to select this configuration + 0x00, // iConfiguration: no string to describe this configuration + USBD_CFGDESC_BMATTRIBUTES | // bmAttributes (USBD_POWER << 6), - USBD_CFGDESC_BMAXPOWER // bMaxPower, device power consumption + USBD_CFGDESC_BMAXPOWER // bMaxPower, device power consumption }; pD = config_desc; memcpy(pD, start_desc, sizeof(start_desc)); - + #if (USBD_HS_ENABLE == 1) pD = config_desc_hs; memcpy(pD, start_desc, sizeof(start_desc)); #endif - + return sizeof(start_desc); } @@ -2509,7 +2509,7 @@ static U16 hid_desc_fill(U8 * config_desc, U8 * config_desc_hs, U8 if_num) { pD = config_desc; memcpy(pD, hid_desc, sizeof(hid_desc)); ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num; -#if (USBD_HS_ENABLE == 1) +#if (USBD_HS_ENABLE == 1) const U8 hid_desc_hs[] = { HID_DESC #if ((USBD_HID_EP_INTOUT != 0) && (USBD_HID_EP_INTIN != 0)) @@ -2523,7 +2523,7 @@ static U16 hid_desc_fill(U8 * config_desc, U8 * config_desc_hs, U8 if_num) { pD = config_desc_hs; memcpy(pD, hid_desc_hs, sizeof(hid_desc_hs)); ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num; -#endif +#endif return sizeof(hid_desc); } @@ -2544,8 +2544,8 @@ static U16 acm_cdc_desc_fill(U8 * config_desc, U8 * config_desc_hs, U8 if_num) { #if (USBD_MULTI_IF) ((USB_INTERFACE_ASSOCIATION_DESCRIPTOR *)pD)->bFirstInterface = if_num; pD += USB_INTERFACE_ASSOC_DESC_SIZE; -#endif - +#endif + ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num; pD += USB_INTERFACE_DESC_SIZE + CDC_HEADER_SIZE + CDC_CALL_MANAGEMENT_SIZE + CDC_ABSTRACT_CONTROL_MANAGEMENT_SIZE; ((UNION_FUNCTIONAL_DESCRIPTOR*)pD)->bMasterInterface = if_num; @@ -2553,7 +2553,7 @@ static U16 acm_cdc_desc_fill(U8 * config_desc, U8 * config_desc_hs, U8 if_num) { pD += CDC_UNION_SIZE + USB_ENDPOINT_DESC_SIZE; ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num + 1; -#if (USBD_HS_ENABLE == 1) +#if (USBD_HS_ENABLE == 1) const U8 cdc_desc_hs[] = { #if (USBD_MULTI_IF) CDC_ACM_DESC_IAD(0, 2) @@ -2565,35 +2565,35 @@ static U16 acm_cdc_desc_fill(U8 * config_desc, U8 * config_desc_hs, U8 if_num) { }; pD = config_desc_hs; memcpy(pD, cdc_desc_hs, sizeof(cdc_desc_hs)); - + #if (USBD_MULTI_IF) ((USB_INTERFACE_ASSOCIATION_DESCRIPTOR *)pD)->bFirstInterface = if_num; pD += USB_INTERFACE_ASSOC_DESC_SIZE; -#endif - +#endif + ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num; pD += USB_INTERFACE_DESC_SIZE + CDC_HEADER_SIZE + CDC_CALL_MANAGEMENT_SIZE + CDC_ABSTRACT_CONTROL_MANAGEMENT_SIZE; ((UNION_FUNCTIONAL_DESCRIPTOR*)pD)->bMasterInterface = if_num; ((UNION_FUNCTIONAL_DESCRIPTOR*)pD)->bSlaveInterface0 = if_num + 1; pD += CDC_UNION_SIZE + USB_ENDPOINT_DESC_SIZE; ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num +1 ; -#endif //(USBD_HS_ENABLE == 1) +#endif //(USBD_HS_ENABLE == 1) return sizeof(cdc_desc); } static U16 msc_desc_fill(U8 * config_desc, U8 * config_desc_hs, U8 if_num) { U8 * pD = 0; - const U8 msc_desc[] = { + const U8 msc_desc[] = { MSC_DESC MSC_EP }; pD = config_desc; memcpy(pD, msc_desc, sizeof(msc_desc)); - + ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num; -#if (USBD_HS_ENABLE == 1) - const U8 msc_desc_hs[] = { +#if (USBD_HS_ENABLE == 1) + const U8 msc_desc_hs[] = { MSC_DESC MSC_EP_HS }; @@ -2601,7 +2601,7 @@ static U16 msc_desc_fill(U8 * config_desc, U8 * config_desc_hs, U8 if_num) { memcpy(pD, msc_desc_hs, sizeof(msc_desc_hs)); ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num; #endif - + return sizeof(msc_desc); } @@ -2614,36 +2614,36 @@ static U16 webusb_desc_fill(U8 * config_desc, U8 * config_desc_hs, U8 if_num) { pD = config_desc; memcpy(pD, webusb_desc, sizeof(webusb_desc)); ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num; - + #if (USBD_HS_ENABLE == 1) pD = config_desc_hs; memcpy(pD, webusb_desc, sizeof(webusb_desc)); ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num; #endif - + #if (USBD_WINUSB_ENABLE) pD = USBD_WinUSBDescriptorSetDescriptor + WINUSB_DESCRIPTOR_SET_HEADER_SIZE; ((WINUSB_FUNCTION_SUBSET_HEADER*)pD)->bFirstInterface = if_num; #else #error "WEBUSB requires WINUSB!" #endif - - return sizeof(webusb_desc); + + return sizeof(webusb_desc); } #endif #if (USBD_BULK_ENABLE) static U16 bulk_desc_fill(U8 * config_desc, U8 * config_desc_hs, U8 if_num) { U8 * pD = 0; - const U8 bulk_desc[] = { + const U8 bulk_desc[] = { BULK_DESC BULK_EP }; pD = config_desc; memcpy(pD, bulk_desc, sizeof(bulk_desc)); ((USB_INTERFACE_DESCRIPTOR *)pD)->bInterfaceNumber = if_num; -#if (USBD_HS_ENABLE == 1) - const U8 bulk_desc_hs[] = { +#if (USBD_HS_ENABLE == 1) + const U8 bulk_desc_hs[] = { BULK_DESC BULK_EP_HS }; @@ -2661,25 +2661,25 @@ static U16 bulk_desc_fill(U8 * config_desc, U8 * config_desc_hs, U8 if_num) { #else #error "BULK interfaces requires WINUSB!" #endif - + return sizeof(bulk_desc); } #endif void usbd_class_init(void) -{ +{ U8 if_num = 0; U16 desc_ptr = 0; - - desc_ptr += start_desc_fill(&USBD_ConfigDescriptor[desc_ptr], &USBD_ConfigDescriptor_HS[desc_ptr], if_num); - + + desc_ptr += start_desc_fill(&USBD_ConfigDescriptor[desc_ptr], &USBD_ConfigDescriptor_HS[desc_ptr], if_num); + #if (USBD_ADC_ENABLE) usbd_adc_init(); #endif -#if (USBD_MSC_ENABLE) - +#if (USBD_MSC_ENABLE) + #if !(defined(DAPLINK_BL)) && defined(DRAG_N_DROP_SUPPORT) //change descriptors here if (config_ram_get_disable_msd() == 1 || flash_algo_valid()==0 ){ @@ -2695,7 +2695,7 @@ void usbd_class_init(void) usb_conf_desc->bNumInterfaces = usbd_if_num; usb_conf_desc->wTotalLength = usb_wtotal_len; USBD_ConfigDescriptor_HS[usb_wtotal_len] = 0; -#endif +#endif } else #endif { @@ -2704,7 +2704,7 @@ void usbd_class_init(void) usbd_msc_init(); } -#endif //#if (USBD_MSC_ENABLE) +#endif //#if (USBD_MSC_ENABLE) #if (USBD_CDC_ACM_ENABLE) usbd_cdc_acm_cif_num = if_num++; @@ -2713,19 +2713,19 @@ void usbd_class_init(void) USBD_CDC_ACM_Initialize(); #endif -#if (USBD_HID_ENABLE) +#if (USBD_HID_ENABLE) usbd_hid_if_num = if_num++; desc_ptr += hid_desc_fill(&USBD_ConfigDescriptor[desc_ptr], &USBD_ConfigDescriptor_HS[desc_ptr], usbd_hid_if_num); usbd_hid_init(); #endif #if (USBD_WEBUSB_ENABLE) - usbd_webusb_if_num = if_num++; + usbd_webusb_if_num = if_num++; desc_ptr += webusb_desc_fill(&USBD_ConfigDescriptor[desc_ptr], &USBD_ConfigDescriptor_HS[desc_ptr], usbd_webusb_if_num); #endif #if (USBD_BULK_ENABLE) - usbd_bulk_if_num = if_num++; + usbd_bulk_if_num = if_num++; desc_ptr += bulk_desc_fill(&USBD_ConfigDescriptor[desc_ptr], &USBD_ConfigDescriptor_HS[desc_ptr], usbd_bulk_if_num); usbd_bulk_init(); #endif diff --git a/source/usb/webusb/usbd_core_webusb.c b/source/usb/webusb/usbd_core_webusb.c index a2712117b..2a9fb6a3a 100644 --- a/source/usb/webusb/usbd_core_webusb.c +++ b/source/usb/webusb/usbd_core_webusb.c @@ -31,7 +31,7 @@ * Return Value: TRUE - Setup vendor request ok, FALSE - Setup vendor request not supported */ -__weak BOOL USBD_EndPoint0_Setup_WebUSB_ReqToDevice(void) +__WEAK BOOL USBD_EndPoint0_Setup_WebUSB_ReqToDevice(void) { U8 *pD; U32 len, n; diff --git a/source/usb/winusb/usbd_core_winusb.c b/source/usb/winusb/usbd_core_winusb.c index 404ac099d..f8f5fe5fc 100644 --- a/source/usb/winusb/usbd_core_winusb.c +++ b/source/usb/winusb/usbd_core_winusb.c @@ -30,7 +30,7 @@ * Return Value: TRUE - Setup vendor request ok, FALSE - Setup vendor request not supported */ -__weak BOOL USBD_EndPoint0_Setup_WinUSB_ReqToDevice(void) +__WEAK BOOL USBD_EndPoint0_Setup_WinUSB_ReqToDevice(void) { U8 *pD; U32 len; From f1fee11ded5326167019019b1c9b40eff8d70594 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sun, 1 Dec 2019 16:03:41 -0600 Subject: [PATCH 005/617] Include compiler.h in target_board.c. --- source/target/target_board.c | 1 + 1 file changed, 1 insertion(+) diff --git a/source/target/target_board.c b/source/target/target_board.c index 8451f7776..dde63ff42 100644 --- a/source/target/target_board.c +++ b/source/target/target_board.c @@ -21,6 +21,7 @@ #include #include "target_board.h" +#include "compiler.h" // Default empty board info. __WEAK From 78413f09570079b0a5fe37e1cda9cef5c677a0c4 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sun, 5 Jan 2020 15:56:29 -0600 Subject: [PATCH 006/617] Correct board info alignment. - Made board_info_t non-packed. Using canonical alignment for the fields will reduce code size. - Remove aligned(4) on default weak g_board_info. --- source/target/target_board.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/target/target_board.h b/source/target/target_board.h index f6f8a3710..7ae102e0b 100644 --- a/source/target/target_board.h +++ b/source/target/target_board.h @@ -54,7 +54,7 @@ enum _board_info_flags { * The board initialization function pointers allow the board to override the routines defined * by the device family. */ -typedef struct __attribute__((__packed__)) board_info { +typedef struct board_info { uint16_t info_version; /*!< Version number of the board info */ uint16_t family_id; /*!< Use to select or identify target family from defined target family or custom ones */ char board_id[5]; /*!< 4-char board ID plus null terminator */ From ae00002612b1c372887c80ab593ae20bee363c81 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Tue, 5 Nov 2019 17:00:08 -0600 Subject: [PATCH 007/617] Basing RTL types on stdint. --- source/rtos/RTL.h | 20 +++++++++++--------- source/rtos/rt_TypeDef.h | 20 +++++++++++--------- source/usb/usb_def.h | 16 ++++++++-------- 3 files changed, 30 insertions(+), 26 deletions(-) diff --git a/source/rtos/RTL.h b/source/rtos/RTL.h index 575c196be..e6c794cb6 100644 --- a/source/rtos/RTL.h +++ b/source/rtos/RTL.h @@ -1,6 +1,6 @@ /** * @file RTL.h - * @brief + * @brief * * DAPLink Interface Firmware * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved @@ -22,6 +22,8 @@ #ifndef __RTL_H__ #define __RTL_H__ +#include + /* RL-ARM version number. */ #define __RL_ARM_VER 471 @@ -45,14 +47,14 @@ typedef unsigned int size_t; #endif -typedef signed char S8; -typedef unsigned char U8; -typedef short S16; -typedef unsigned short U16; -typedef int S32; -typedef unsigned int U32; -typedef long long S64; -typedef unsigned long long U64; +typedef int8_t S8; +typedef uint8_t U8; +typedef int16_t S16; +typedef uint16_t U16; +typedef int32_t S32; +typedef uint32_t U32; +typedef int64_t S64; +typedef uint64_t U64; typedef unsigned char BIT; typedef unsigned int BOOL; diff --git a/source/rtos/rt_TypeDef.h b/source/rtos/rt_TypeDef.h index 22275c7aa..f042fade1 100644 --- a/source/rtos/rt_TypeDef.h +++ b/source/rtos/rt_TypeDef.h @@ -1,6 +1,6 @@ /** * @file rt_TypeDef.h - * @brief + * @brief * * DAPLink Interface Firmware * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved @@ -19,15 +19,17 @@ * limitations under the License. */ +#include + /* Types */ -typedef char S8; -typedef unsigned char U8; -typedef short S16; -typedef unsigned short U16; -typedef int S32; -typedef unsigned int U32; -typedef long long S64; -typedef unsigned long long U64; +typedef int8_t S8; +typedef uint8_t U8; +typedef int16_t S16; +typedef uint16_t U16; +typedef int32_t S32; +typedef uint32_t U32; +typedef int64_t S64; +typedef uint64_t U64; typedef unsigned char BIT; typedef unsigned int BOOL; typedef void (*FUNCP)(void); diff --git a/source/usb/usb_def.h b/source/usb/usb_def.h index f6a5c6b06..a51900d28 100644 --- a/source/usb/usb_def.h +++ b/source/usb/usb_def.h @@ -45,14 +45,14 @@ typedef unsigned int size_t; #endif -typedef signed char S8; -typedef unsigned char U8; -typedef short S16; -typedef unsigned short U16; -typedef int S32; -typedef unsigned int U32; -typedef long long S64; -typedef unsigned long long U64; +typedef int8_t S8; +typedef uint8_t U8; +typedef int16_t S16; +typedef uint16_t U16; +typedef int32_t S32; +typedef uint32_t U32; +typedef int64_t S64; +typedef uint64_t U64; typedef unsigned char BIT; typedef unsigned int BOOL; From aed7013a14521f25e5c60fdb26d19952d2c5c2a2 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Tue, 5 Nov 2019 17:00:26 -0600 Subject: [PATCH 008/617] Removed RTL version asm function. --- source/usb/usbd_core.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/source/usb/usbd_core.c b/source/usb/usbd_core.c index 4e8ff1568..6415959e3 100644 --- a/source/usb/usbd_core.c +++ b/source/usb/usbd_core.c @@ -44,12 +44,6 @@ OS_TID USBD_RTX_CoreTask; /* USB Core Task ID */ #endif -__asm void $$USBD$$version(void) -{ - /* Export a version number symbol for a version control. */ - EXPORT __RL_USBD_VER -__RL_USBD_VER EQU 0x470 -} /* From 03490b7f3b52ff5040b39003804fe9220d96fa95 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Tue, 5 Nov 2019 17:00:52 -0600 Subject: [PATCH 009/617] Changed U16 to wchar_t in usb_lib.c for string descriptors. --- source/usb/usb_lib.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/source/usb/usb_lib.c b/source/usb/usb_lib.c index 3540999c7..457d21c50 100644 --- a/source/usb/usb_lib.c +++ b/source/usb/usb_lib.c @@ -23,6 +23,7 @@ #include "rl_usb.h" #include "usb.h" #include "settings.h" +#include "compiler.h" #pragma thumb #pragma O3 @@ -2337,12 +2338,15 @@ U8 USBD_ConfigDescriptor_HS[200] = { 0 }; #endif +// Verify that wchar_t is UTF-16. +COMPILER_ASSERT(sizeof(wchar_t) == 2); + /* USB Device Create String Descriptor */ #define USBD_STR_DEF(n) \ struct { \ U8 len; \ U8 type; \ - U16 str[sizeof(USBD_##n)/2-1]; \ + wchar_t str[sizeof(USBD_##n)/2-1]; \ } desc##n #define USBD_STR_VAL(n) \ From a8eb2dca50d3a073aeb5aa1dfa3e523ee29e8f0c Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Tue, 5 Nov 2019 17:01:32 -0600 Subject: [PATCH 010/617] Using CMSIS unaligned read/write macros instead of packed r/w. --- source/hic_hal/freescale/k26f/usbd_MK26F.c | 8 ++++---- source/hic_hal/nxp/lpc11u35/usbd_LPC11Uxx.c | 8 ++++---- source/hic_hal/nxp/lpc4322/usbd_LPC43xx_USB0.c | 10 +++++----- source/hic_hal/stm32/stm32f103xb/usbd_STM32F103.c | 12 ++++++------ source/usb/usbd_core.c | 4 ++-- 5 files changed, 21 insertions(+), 21 deletions(-) diff --git a/source/hic_hal/freescale/k26f/usbd_MK26F.c b/source/hic_hal/freescale/k26f/usbd_MK26F.c index 6c05fd6b2..bdac64e49 100644 --- a/source/hic_hal/freescale/k26f/usbd_MK26F.c +++ b/source/hic_hal/freescale/k26f/usbd_MK26F.c @@ -79,8 +79,8 @@ uint8_t __align(4096) EPBufPool[ USBD_MSC_ENABLE * (HS(USBD_MSC_HS_ENABLE) ? USBD_MSC_HS_WMAXPACKETSIZE : USBD_MSC_WMAXPACKETSIZE) * 2 + USBD_ADC_ENABLE * (HS(USBD_ADC_HS_ENABLE) ? USBD_ADC_HS_WMAXPACKETSIZE : USBD_ADC_WMAXPACKETSIZE) + USBD_CDC_ACM_ENABLE * ((HS(USBD_CDC_ACM_HS_ENABLE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE : USBD_CDC_ACM_WMAXPACKETSIZE) + - (HS(USBD_CDC_ACM_HS_ENABLE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE1 : USBD_CDC_ACM_WMAXPACKETSIZE1) * 2) + - USBD_BULK_ENABLE * (HS(USBD_BULK_HS_ENABLE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) * 2 + (HS(USBD_CDC_ACM_HS_ENABLE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE1 : USBD_CDC_ACM_WMAXPACKETSIZE1) * 2) + + USBD_BULK_ENABLE * (HS(USBD_BULK_HS_ENABLE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) * 2 ]; #endif @@ -582,8 +582,8 @@ uint32_t USBD_ReadEP(uint32_t EPNum, uint8_t *pData, uint32_t size) while (USBHS->EPSETUPSR & 1); do { - *((__packed uint32_t *) pData) = EPQHx[EP_OUT_IDX(0)].setup[0]; - *((__packed uint32_t *)(pData + 4)) = EPQHx[EP_OUT_IDX(0)].setup[1]; + __UNALIGNED_UINT32_WRITE(pData, EPQHx[EP_OUT_IDX(0)].setup[0]); + __UNALIGNED_UINT32_WRITE(pData + 4, EPQHx[EP_OUT_IDX(0)].setup[1]); cnt = 8; USBHS->USBCMD |= (1UL << 13); } while (!(USBHS->USBCMD & (1UL << 13))); diff --git a/source/hic_hal/nxp/lpc11u35/usbd_LPC11Uxx.c b/source/hic_hal/nxp/lpc11u35/usbd_LPC11Uxx.c index c609675f6..61de83cca 100644 --- a/source/hic_hal/nxp/lpc11u35/usbd_LPC11Uxx.c +++ b/source/hic_hal/nxp/lpc11u35/usbd_LPC11Uxx.c @@ -1,6 +1,6 @@ /** * @file usbd_LPC11Uxx.c - * @brief + * @brief * * DAPLink Interface Firmware * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved @@ -552,9 +552,9 @@ U32 USBD_ReadEP(U32 EPNum, U8 *pData, U32 size) cnt = EPBufInfo[EP_OUT_IDX(EPNum)].buf_len - ((*ptr >> 16) & 0x3FF); dataptr = (U8 *)EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr; - while ((timeout-- > 0) && (*ptr & BUF_ACTIVE)); //spin on the hardware until it's done + while ((timeout-- > 0) && (*ptr & BUF_ACTIVE)); //spin on the hardware until it's done util_assert(!(*ptr & BUF_ACTIVE)); //check for timeout - + if (size < cnt) { util_assert(0); cnt = size; @@ -612,7 +612,7 @@ U32 USBD_WriteEP(U32 EPNum, U8 *pData, U32 cnt) dataptr = (U32 *)EPBufInfo[EP_IN_IDX(EPNum)].buf_ptr; for (i = 0; i < (cnt + 3) / 4; i++) { - dataptr[i] = * ((__packed U32 *)pData); + dataptr[i] = __UNALIGNED_UINT32_READ(pData); pData += 4; } diff --git a/source/hic_hal/nxp/lpc4322/usbd_LPC43xx_USB0.c b/source/hic_hal/nxp/lpc4322/usbd_LPC43xx_USB0.c index b9d09f5ae..c3d2e4f81 100644 --- a/source/hic_hal/nxp/lpc4322/usbd_LPC43xx_USB0.c +++ b/source/hic_hal/nxp/lpc4322/usbd_LPC43xx_USB0.c @@ -1,6 +1,6 @@ /** * @file usbd_LPC43xx_USBD0.c - * @brief + * @brief * * DAPLink Interface Firmware * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved @@ -80,8 +80,8 @@ uint8_t __align(4096) EPBufPool[ USBD_MSC_ENABLE * (HS(USBD_MSC_HS_ENABLE) ? USBD_MSC_HS_WMAXPACKETSIZE : USBD_MSC_WMAXPACKETSIZE) * 2 + USBD_ADC_ENABLE * (HS(USBD_ADC_HS_ENABLE) ? USBD_ADC_HS_WMAXPACKETSIZE : USBD_ADC_WMAXPACKETSIZE) + USBD_CDC_ACM_ENABLE * ((HS(USBD_CDC_ACM_HS_ENABLE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE : USBD_CDC_ACM_WMAXPACKETSIZE) + - (HS(USBD_CDC_ACM_HS_ENABLE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE1 : USBD_CDC_ACM_WMAXPACKETSIZE1) * 2) + - USBD_BULK_ENABLE * (HS(USBD_BULK_HS_ENABLE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) * 2 + (HS(USBD_CDC_ACM_HS_ENABLE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE1 : USBD_CDC_ACM_WMAXPACKETSIZE1) * 2) + + USBD_BULK_ENABLE * (HS(USBD_BULK_HS_ENABLE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) * 2 ]; #endif @@ -592,8 +592,8 @@ uint32_t USBD_ReadEP(uint32_t EPNum, uint8_t *pData, U32 size) while (LPC_USBx->ENDPTSETUPSTAT & 1); do { - *((__packed uint32_t *) pData) = EPQHx[EP_OUT_IDX(0)].setup[0]; - *((__packed uint32_t *)(pData + 4)) = EPQHx[EP_OUT_IDX(0)].setup[1]; + __UNALIGNED_UINT32_WRITE(pData, EPQHx[EP_OUT_IDX(0)].setup[0]); + __UNALIGNED_UINT32_WRITE(pData + 4, EPQHx[EP_OUT_IDX(0)].setup[1]); cnt = 8; LPC_USBx->USBCMD_D |= (1UL << 13); } while (!(LPC_USBx->USBCMD_D & (1UL << 13))); diff --git a/source/hic_hal/stm32/stm32f103xb/usbd_STM32F103.c b/source/hic_hal/stm32/stm32f103xb/usbd_STM32F103.c index 319d1166b..806233571 100644 --- a/source/hic_hal/stm32/stm32f103xb/usbd_STM32F103.c +++ b/source/hic_hal/stm32/stm32f103xb/usbd_STM32F103.c @@ -38,7 +38,7 @@ #define USB_ISTR_W0C_MASK (ISTR_PMAOVR | ISTR_ERR | ISTR_WKUP | ISTR_SUSP | ISTR_RESET | ISTR_SOF | ISTR_ESOF) #define VAL_MASK 0xFFFF -#define VAL_SHIFT 16 +#define VAL_SHIFT 16 #define EP_NUM_MASK 0xFFFF #define EP_NUM_SHIFT 0 @@ -490,7 +490,7 @@ U32 USBD_ReadEP(U32 EPNum, U8 *pData, U32 bufsz) } for (n = 0; n < (cnt + 1) / 2; n++) { - *((__packed U16 *)pData) = *pv++; + __UNALIGNED_UINT16_WRITE(pData, *pv++); pData += 2; } @@ -518,7 +518,7 @@ U32 USBD_WriteEP(U32 EPNum, U8 *pData, U32 cnt) pv = (U32 *)(USB_PMA_ADDR + 2 * ((pBUF_DSCR + num)->ADDR_TX)); for (n = 0; n < (cnt + 1) / 2; n++) { - *pv++ = *((__packed U16 *)pData); + *pv++ = __UNALIGNED_UINT16_READ(pData); pData += 2; } @@ -587,13 +587,13 @@ void USB_LP_CAN1_RX0_IRQHandler(void) && (0 == ((pBUF_DSCR + num)->COUNT_RX & EP_COUNT_MASK))) { if (val & EP_CTR_TX) { // Drop the RX event but not TX - stat_enque((((val & VAL_MASK) & ~EP_CTR_RX) << VAL_SHIFT) | + stat_enque((((val & VAL_MASK) & ~EP_CTR_RX) << VAL_SHIFT) | ((num & EP_NUM_MASK) << EP_NUM_SHIFT)); } else { // Drop the event } } else { - stat_enque(((val & VAL_MASK) << VAL_SHIFT) | + stat_enque(((val & VAL_MASK) << VAL_SHIFT) | ((num & EP_NUM_MASK) << EP_NUM_SHIFT)); } @@ -607,7 +607,7 @@ void USB_LP_CAN1_RX0_IRQHandler(void) } } } - + USBD_SignalHandler(); } diff --git a/source/usb/usbd_core.c b/source/usb/usbd_core.c index 6415959e3..f007563f6 100644 --- a/source/usb/usbd_core.c +++ b/source/usb/usbd_core.c @@ -202,7 +202,7 @@ static inline BOOL USBD_ReqGetStatus(void) case REQUEST_TO_INTERFACE: if ((USBD_Configuration != 0) && (USBD_SetupPacket.wIndexL < USBD_NumInterfaces)) { - *((__packed U16 *)USBD_EP0Buf) = 0; + __UNALIGNED_UINT16_WRITE(USBD_EP0Buf, 0); USBD_EP0Data.pData = USBD_EP0Buf; } else { return (__FALSE); @@ -215,7 +215,7 @@ static inline BOOL USBD_ReqGetStatus(void) m = (n & 0x80) ? ((1 << 16) << (n & 0x0F)) : (1 << n); if (((USBD_Configuration != 0) || ((n & 0x0F) == 0)) && (USBD_EndPointMask & m)) { - *((__packed U16 *)USBD_EP0Buf) = (USBD_EndPointHalt & m) ? 1 : 0; + __UNALIGNED_UINT16_WRITE(USBD_EP0Buf, (USBD_EndPointHalt & m) ? 1 : 0); USBD_EP0Data.pData = USBD_EP0Buf; } else { return (__FALSE); From bd49a031bfad757ed725d09b438f77ba47a51e19 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Tue, 5 Nov 2019 17:02:43 -0600 Subject: [PATCH 011/617] Fixed usbd issues. - Using CMSIS __ALIGNED macro. - Corrected some function prototypes that were out of sync. - Changed from __at to __attribute__((at(x))) for LPC11U35 USB buffer placement. --- source/hic_hal/freescale/k26f/usbd_MK26F.c | 14 +++++++------- source/hic_hal/freescale/usbd_kinetis.c | 14 +++++++------- source/hic_hal/nxp/lpc11u35/usbd_LPC11Uxx.c | 6 +++++- source/hic_hal/nxp/lpc4322/usbd_LPC43xx_USB0.c | 14 +++++++------- 4 files changed, 26 insertions(+), 22 deletions(-) diff --git a/source/hic_hal/freescale/k26f/usbd_MK26F.c b/source/hic_hal/freescale/k26f/usbd_MK26F.c index bdac64e49..cb742f798 100644 --- a/source/hic_hal/freescale/k26f/usbd_MK26F.c +++ b/source/hic_hal/freescale/k26f/usbd_MK26F.c @@ -53,8 +53,8 @@ typedef struct __EP { uint32_t maxPacket; } EP; -EPQH __align(2048) EPQHx[(USBD_EP_NUM + 1) * 2]; -dTD __align(32) dTDx[(USBD_EP_NUM + 1) * 2]; +EPQH __ALIGNED(2048) EPQHx[(USBD_EP_NUM + 1) * 2]; +dTD __ALIGNED(32) dTDx[(USBD_EP_NUM + 1) * 2]; EP Ep[(USBD_EP_NUM + 1) * 2]; uint32_t BufUsed; @@ -70,10 +70,10 @@ uint32_t cmpl_pnd; #if USBD_VENDOR_ENABLE /* custom class: user defined buffer size */ #define EP_BUF_POOL_SIZE 0x1000 -uint8_t __align(4096) EPBufPool[EP_BUF_POOL_SIZE] +uint8_t __ALIGNED(4096) EPBufPool[EP_BUF_POOL_SIZE] #else /* supported classes are used */ -uint8_t __align(4096) EPBufPool[ +uint8_t __ALIGNED(4096) EPBufPool[ USBD_MAX_PACKET0 * 2 + USBD_HID_ENABLE * (HS(USBD_HID_HS_ENABLE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) * 2 + USBD_MSC_ENABLE * (HS(USBD_MSC_HS_ENABLE) ? USBD_MSC_HS_WMAXPACKETSIZE : USBD_MSC_WMAXPACKETSIZE) * 2 + @@ -158,7 +158,7 @@ void USBD_Init(void) * Return Value: None */ -void USBD_Connect(uint32_t con) +void USBD_Connect(BOOL con) { if (con) { USBHS->USBCMD |= 1; /* run */ @@ -281,7 +281,7 @@ void USBD_WakeUp(void) * Return Value: None */ -void USBD_WakeUpCfg(uint32_t cfg) +void USBD_WakeUpCfg(BOOL cfg) { /* Not needed */ } @@ -308,7 +308,7 @@ void USBD_SetAddress(uint32_t adr, uint32_t setup) * Return Value: None */ -void USBD_Configure(uint32_t cfg) +void USBD_Configure(BOOL cfg) { uint32_t i; diff --git a/source/hic_hal/freescale/usbd_kinetis.c b/source/hic_hal/freescale/usbd_kinetis.c index 8cfdaf704..4f06f63fd 100644 --- a/source/hic_hal/freescale/usbd_kinetis.c +++ b/source/hic_hal/freescale/usbd_kinetis.c @@ -1,6 +1,6 @@ /** * @file usbd_kinetis.c - * @brief + * @brief * * DAPLink Interface Firmware * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved @@ -36,7 +36,7 @@ typedef struct __BUF_DESC { uint32_t buf_addr; } BUF_DESC; -BUF_DESC __align(512) BD[(USBD_EP_NUM + 1) * 2 * 2]; +BUF_DESC __ALIGNED(512) BD[(USBD_EP_NUM + 1) * 2 * 2]; uint8_t EPBuf[(USBD_EP_NUM + 1) * 2 * 2][64]; uint8_t OutEpSize[USBD_EP_NUM + 1]; uint8_t StatQueue[(USBD_EP_NUM + 1) * 2 * 2 + 1]; @@ -44,7 +44,7 @@ uint32_t StatQueueHead = 0; uint32_t StatQueueTail = 0; uint32_t LastIstat = 0; uint8_t UsbSuspended = 0; -uint8_t Ep0ZlpOut = 0; +uint8_t Ep0ZlpOut = 0; uint32_t Data1 = 0x55555555; @@ -175,7 +175,7 @@ void USBD_Init(void) * Return Value: None */ -void USBD_Connect(uint32_t con) +void USBD_Connect(BOOL con) { if (con) { USB0->CTL |= USB_CTL_USBENSOFEN_MASK; /* enable USB */ @@ -269,7 +269,7 @@ void USBD_WakeUp(void) USB0->CTL |= USB_CTL_RESUME_MASK; while (i--) { - __nop(); + __NOP(); } USB0->CTL &= ~USB_CTL_RESUME_MASK; @@ -283,7 +283,7 @@ void USBD_WakeUp(void) * Return Value: None */ -void USBD_WakeUpCfg(uint32_t cfg) +void USBD_WakeUpCfg(BOOL cfg) { /* Not needed */ } @@ -309,7 +309,7 @@ void USBD_SetAddress(uint32_t adr, uint32_t setup) * Return Value: None */ -void USBD_Configure(uint32_t cfg) +void USBD_Configure(BOOL cfg) { } diff --git a/source/hic_hal/nxp/lpc11u35/usbd_LPC11Uxx.c b/source/hic_hal/nxp/lpc11u35/usbd_LPC11Uxx.c index 61de83cca..1746e26d7 100644 --- a/source/hic_hal/nxp/lpc11u35/usbd_LPC11Uxx.c +++ b/source/hic_hal/nxp/lpc11u35/usbd_LPC11Uxx.c @@ -49,7 +49,11 @@ typedef struct BUF_INFO { } EP_BUF_INFO; EP_BUF_INFO EPBufInfo[(USBD_EP_NUM + 1) * 2]; -volatile U32 EPList[(USBD_EP_NUM + 1) * 2] __at(EP_LIST_BASE); +#if defined ( __CC_ARM ) || defined (__ARMCC_VERSION) +volatile U32 EPList[(USBD_EP_NUM + 1) * 2] __attribute__((at(EP_LIST_BASE))); +#else +#error "Unsupported compiler!" +#endif static U32 addr = 3 * 64 + EP_BUF_BASE; static U32 ctrl_out_next = 0; diff --git a/source/hic_hal/nxp/lpc4322/usbd_LPC43xx_USB0.c b/source/hic_hal/nxp/lpc4322/usbd_LPC43xx_USB0.c index c3d2e4f81..3bc3c66f7 100644 --- a/source/hic_hal/nxp/lpc4322/usbd_LPC43xx_USB0.c +++ b/source/hic_hal/nxp/lpc4322/usbd_LPC43xx_USB0.c @@ -53,8 +53,8 @@ typedef struct __EP { uint32_t maxPacket; } EP; -EPQH __align(2048) EPQHx[(USBD_EP_NUM + 1) * 2]; -dTD __align(32) dTDx[(USBD_EP_NUM + 1) * 2]; +EPQH __ALIGNED(2048) EPQHx[(USBD_EP_NUM + 1) * 2]; +dTD __ALIGNED(32) dTDx[(USBD_EP_NUM + 1) * 2]; EP Ep[(USBD_EP_NUM + 1) * 2]; uint32_t BufUsed; @@ -71,10 +71,10 @@ uint32_t cmpl_pnd; #if USBD_VENDOR_ENABLE /* custom class: user defined buffer size */ #define EP_BUF_POOL_SIZE 0x1000 -uint8_t __align(4096) EPBufPool[EP_BUF_POOL_SIZE] +uint8_t __ALIGNED(4096) EPBufPool[EP_BUF_POOL_SIZE] #else /* supported classes are used */ -uint8_t __align(4096) EPBufPool[ +uint8_t __ALIGNED(4096) EPBufPool[ USBD_MAX_PACKET0 * 2 + USBD_HID_ENABLE * (HS(USBD_HID_HS_ENABLE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) * 2 + USBD_MSC_ENABLE * (HS(USBD_MSC_HS_ENABLE) ? USBD_MSC_HS_WMAXPACKETSIZE : USBD_MSC_WMAXPACKETSIZE) * 2 + @@ -168,7 +168,7 @@ void USBD_Init(void) * Return Value: None */ -void USBD_Connect(uint32_t con) +void USBD_Connect(BOOL con) { if (con) { LPC_USBx->USBCMD_D |= 1; /* run */ @@ -291,7 +291,7 @@ void USBD_WakeUp(void) * Return Value: None */ -void USBD_WakeUpCfg(uint32_t cfg) +void USBD_WakeUpCfg(BOOL cfg) { /* Not needed */ } @@ -318,7 +318,7 @@ void USBD_SetAddress(uint32_t adr, uint32_t setup) * Return Value: None */ -void USBD_Configure(uint32_t cfg) +void USBD_Configure(BOOL cfg) { uint32_t i; From 199a38e33f2dc51f415f41e40d7c2aad68c20e4e Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Wed, 6 Nov 2019 16:46:23 -0600 Subject: [PATCH 012/617] Wrapped some anon_unions pragmas in #if for armcc. --- source/rtos/RTL.h | 4 ++++ source/usb/usb_def.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/source/rtos/RTL.h b/source/rtos/RTL.h index e6c794cb6..2877b4dad 100644 --- a/source/rtos/RTL.h +++ b/source/rtos/RTL.h @@ -565,8 +565,10 @@ typedef struct sockaddr { /* << Generic Socket Address structure >> */ char sa_data[14]; /* Direct address (up to 14 bytes) */ } SOCKADDR; +#if defined ( __CC_ARM) #pragma push #pragma anon_unions +#endif typedef struct in_addr { /* << Generic IPv4 Address structure >> */ union { @@ -579,7 +581,9 @@ typedef struct in_addr { /* << Generic IPv4 Address structure >> */ U32 s_addr; /* IP address in network byte order */ }; } IN_ADDR; +#if defined ( __CC_ARM) #pragma pop +#endif typedef struct sockaddr_in { /* << IPv4 Socket Address structure >> */ S16 sin_family; /* Socket domain */ diff --git a/source/usb/usb_def.h b/source/usb/usb_def.h index a51900d28..66f452053 100644 --- a/source/usb/usb_def.h +++ b/source/usb/usb_def.h @@ -22,7 +22,9 @@ #ifndef __USB_DEF_H__ #define __USB_DEF_H__ +#if defined ( __CC_ARM) #pragma anon_unions +#endif #include "compiler.h" #include From ee5e95e6cbdaa2dfd197cadc4e4f7a20597d7815 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Tue, 5 Nov 2019 17:05:36 -0600 Subject: [PATCH 013/617] Rewrote IRQ utilities in cortex_m.h in terms of CMSIS intrinsics. --- source/daplink/cortex_m.h | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/source/daplink/cortex_m.h b/source/daplink/cortex_m.h index e1a77ca67..b3425ce6c 100644 --- a/source/daplink/cortex_m.h +++ b/source/daplink/cortex_m.h @@ -24,33 +24,28 @@ #include #include - -#include "IO_Config.h" +#include "device.h" #ifdef __cplusplus extern "C" { #endif -typedef int cortex_int_state_t; +typedef uint32_t cortex_int_state_t; -__attribute__((always_inline)) -static cortex_int_state_t cortex_int_get_and_disable(void) +__STATIC_FORCEINLINE cortex_int_state_t cortex_int_get_and_disable(void) { cortex_int_state_t state; - state = __disable_irq(); + state = __get_PRIMASK(); + __disable_irq(); return state; } -__attribute__((always_inline)) -static void cortex_int_restore(cortex_int_state_t state) +__STATIC_FORCEINLINE void cortex_int_restore(cortex_int_state_t state) { - if (!state) { - __enable_irq(); - } + __set_PRIMASK(state); } -__attribute__((always_inline)) -static bool cortex_in_isr(void) +__STATIC_FORCEINLINE bool cortex_in_isr(void) { return (__get_xPSR() & 0x1F) != 0; } From 09e846fb343467863cdc9bbcd9a2d67796aa2bce Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Tue, 12 Nov 2019 14:29:57 -0600 Subject: [PATCH 014/617] Made some util div functions inline, added WORDS macro. --- source/daplink/util.c | 15 --------------- source/daplink/util.h | 21 ++++++++++++++++++--- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/source/daplink/util.c b/source/daplink/util.c index c29a3088c..9caf0fdbb 100644 --- a/source/daplink/util.c +++ b/source/daplink/util.c @@ -110,21 +110,6 @@ uint32_t util_write_string(char *str, const char *data) return pos; } -uint32_t util_div_round_up(uint32_t dividen, uint32_t divisor) -{ - return (dividen + divisor - 1) / divisor; -} - -uint32_t util_div_round_down(uint32_t dividen, uint32_t divisor) -{ - return dividen / divisor; -} - -uint32_t util_div_round(uint32_t dividen, uint32_t divisor) -{ - return (dividen + divisor / 2) / divisor; -} - void _util_assert(bool expression, const char *filename, uint16_t line) { bool assert_set; diff --git a/source/daplink/util.h b/source/daplink/util.h index a220df919..a8e3fc932 100644 --- a/source/daplink/util.h +++ b/source/daplink/util.h @@ -24,10 +24,14 @@ #include #include +#include "compiler.h" // Protect commonly-defined macros with ifdefs, to prevent conflicts if redefined // in imported sources (mostly vendor SDKs). +//! @brief Round up division to nearest number of words. +#define WORDS(s) (((s) + sizeof(uint32_t) - 1) / sizeof(uint32_t)) + #if !defined(ARRAY_SIZE) //! @brief Get number of elements in the array. #define ARRAY_SIZE(array) (sizeof(array) / sizeof(array[0])) @@ -62,9 +66,20 @@ uint32_t util_write_uint32(char *str, uint32_t value); uint32_t util_write_uint32_zp(char *str, uint32_t value, uint16_t total_size); uint32_t util_write_string(char *str, const char *data); -uint32_t util_div_round_up(uint32_t dividen, uint32_t divisor); -uint32_t util_div_round_down(uint32_t dividen, uint32_t divisor); -uint32_t util_div_round(uint32_t dividen, uint32_t divisor); +__STATIC_INLINE uint32_t util_div_round_up(uint32_t dividen, uint32_t divisor) +{ + return (dividen + divisor - 1) / divisor; +} + +__STATIC_INLINE uint32_t util_div_round_down(uint32_t dividen, uint32_t divisor) +{ + return dividen / divisor; +} + +__STATIC_INLINE uint32_t util_div_round(uint32_t dividen, uint32_t divisor) +{ + return (dividen + divisor / 2) / divisor; +} #if !(defined(DAPLINK_NO_ASSERT_FILENAMES) && defined(DAPLINK_BL)) // With the filename enabled. From 55fa1af70b9bbbd4ad2fb7d3e5e60b36a08ec652 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Tue, 5 Nov 2019 17:06:47 -0600 Subject: [PATCH 015/617] Modified HardFault_Handler.c. - Using an asm handler that can get LR for gcc, and a simpler handler for armcc. - Common function with main functionality that uses CMSIS intrinsics to get other core registers. Made _fault_handler symbol global so HardFault_Handler() can see it. Fixed hard fault handler for armcc. --- source/daplink/HardFault_Handler.c | 55 +++++++++++++++++------------- 1 file changed, 32 insertions(+), 23 deletions(-) diff --git a/source/daplink/HardFault_Handler.c b/source/daplink/HardFault_Handler.c index f249ba075..537e1ec2c 100644 --- a/source/daplink/HardFault_Handler.c +++ b/source/daplink/HardFault_Handler.c @@ -3,7 +3,7 @@ * @brief Entry point for interface program logic * * DAPLink Interface Firmware - * Copyright (c) 2009-2018, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -24,18 +24,15 @@ #include "util.h" #include "cortex_m.h" -register unsigned int _psp __asm("psp"); -register unsigned int _msp __asm("msp"); -register unsigned int _lr __asm("lr"); -register unsigned int _control __asm("control"); -void HardFault_Handler() -{ + //hexdump logic on hardfault +__NO_RETURN void _fault_handler(uint32_t _lr) +{ uint32_t stk_ptr; - uint32_t * stack = (uint32_t *)_msp; - + uint32_t * stack = (uint32_t *)__get_MSP(); + if ((_lr & 0xF) == 0xD) { //process stack - stack = (uint32_t *)_psp; + stack = (uint32_t *)__get_PSP(); } //calculate stack ptr before fault @@ -46,33 +43,45 @@ void HardFault_Handler() if ((_lr & 0x10) == 0) { //fp stk_ptr += 0x48; } - + config_ram_add_hexdump(_lr); //EXC_RETURN - config_ram_add_hexdump(_psp); - config_ram_add_hexdump(_msp); - config_ram_add_hexdump(_control); + config_ram_add_hexdump(__get_PSP()); + config_ram_add_hexdump(__get_MSP()); + config_ram_add_hexdump(__get_CONTROL()); config_ram_add_hexdump(stk_ptr); //SP config_ram_add_hexdump(stack[5]); //LR config_ram_add_hexdump(stack[6]); //PC - config_ram_add_hexdump(stack[7]); //xPSR - -#ifndef __CORTEX_M -#error __CORTEX_M not defined!! -#else + config_ram_add_hexdump(stack[7]); //xPSR -#if (__CORTEX_M > 0x00) +#if !defined(__CORTEX_M) +#error "__CORTEX_M not defined!!" +#elif (__CORTEX_M > 0x00) config_ram_add_hexdump(SCB->HFSR); config_ram_add_hexdump(SCB->CFSR); config_ram_add_hexdump(SCB->DFSR); config_ram_add_hexdump(SCB->AFSR); config_ram_add_hexdump(SCB->MMFAR); config_ram_add_hexdump(SCB->BFAR); -#endif - -#endif //#ifndef __CORTEX_M +#endif // __CORTEX_M util_assert(0); SystemReset(); while (1); // Wait for reset } + +#if defined(__CC_ARM) +void HardFault_Handler() +{ + register unsigned int _lr __asm("lr"); + _fault_handler(_lr); +} +#else +void HardFault_Handler() +{ + asm volatile ( + " mov r0, lr \n\t" + " bl _fault_handler \n\t" + ); +} +#endif From 461fd15ace273b8f99c5fef303b713b1515d563b Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sun, 24 Nov 2019 15:29:39 -0600 Subject: [PATCH 016/617] Prevent compiler warning about unaligned pointer in settings.c. --- source/daplink/settings/settings.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/source/daplink/settings/settings.c b/source/daplink/settings/settings.c index 9b82f2f58..bc55327d1 100644 --- a/source/daplink/settings/settings.c +++ b/source/daplink/settings/settings.c @@ -62,6 +62,9 @@ typedef struct __attribute__((__packed__)) cfg_ram { uint8_t page_erase_enable; } cfg_ram_t; +// Ensure hexdump field is word aligned. +COMPILER_ASSERT((offsetof(cfg_ram_t, hexdump) % sizeof(uint32_t)) == 0); + // Configuration RAM static cfg_ram_t config_ram __attribute__((section("cfgram"), zero_init)); // Ram copy of RAM config @@ -218,8 +221,11 @@ uint8_t config_ram_get_hexdumps(uint32_t **hexdumps) return 0; } - //prevent memcopy check alignment - *hexdumps = config_ram.hexdump; + // this hack prevents a gcc compiler warning about possible unaligned word pointer. + // we know in advance that the pointer to the hexdump field is word aligned due to the + // compiler assert at the top of this file. + uint32_t hd_addr = (uint32_t)&config_ram.hexdump; + *hexdumps = (uint32_t *)hd_addr; return config_ram.valid_dumps; } From 799ad73c54782570792756c3bad04623156df5c0 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Tue, 5 Nov 2019 17:02:26 -0600 Subject: [PATCH 017/617] Clean up non-optimized functions. - Added NO_OPTIMIZE_* macros to compiler.h, using instead of explicit pragmas in source files. - Restored optimization for setup_basics() in info.c, and instead made get_board_id() and get_family_id() in target_board.c non-optimized - This reduces code size since setup_basics() is a fairly large function. --- source/daplink/compiler.h | 18 +++++++++- source/daplink/info.c | 32 ++++------------- source/hic_hal/freescale/iap/fsl_flash.c | 2 +- source/target/target_board.c | 46 +++++++++++------------- 4 files changed, 45 insertions(+), 53 deletions(-) diff --git a/source/daplink/compiler.h b/source/daplink/compiler.h index c9ba3e8f9..38d64bc36 100644 --- a/source/daplink/compiler.h +++ b/source/daplink/compiler.h @@ -39,7 +39,23 @@ extern "C" { // conflicts resulting from the same enum being declared multiple times. #define COMPILER_ASSERT(e) enum { COMPILER_CONCAT(compiler_assert_, __COUNTER__) = 1/((e) ? 1 : 0) } -#define __at(_addr) __attribute__ ((at(_addr))) +// Macros to disable optimisation of a function. +#if (defined(__ICCARM__)) +#define NO_OPTIMIZE_PRE _Pragma("optimize = none") +#define NO_OPTIMIZE_INLINE +#define NO_OPTIMIZE_POST +#elif (defined(__CC_ARM)) +#define NO_OPTIMIZE_PRE _Pragma("push") \ + _Pragma("O0") +#define NO_OPTIMIZE_INLINE +#define NO_OPTIMIZE_POST _Pragma("pop") +#elif (defined(__GNUC__)) +#define NO_OPTIMIZE_PRE +#define NO_OPTIMIZE_INLINE __attribute__((optimize("O0"))) +#define NO_OPTIMIZE_POST +#else +#error "Unknown compiler" +#endif #ifdef __cplusplus } diff --git a/source/daplink/info.c b/source/daplink/info.c index ad5b5a625..08c2d12d1 100644 --- a/source/daplink/info.c +++ b/source/daplink/info.c @@ -100,22 +100,8 @@ const char *info_get_unique_id_string_descriptor(void) return usb_desc_unique_id; } -//prevent the compiler to optimize boad and family id -#if (defined(__ICCARM__)) -#pragma optimize = none +//prevent the compiler to optimize board and family id static void setup_basics(void) -#elif (defined(__CC_ARM)) -#pragma push -#pragma O0 -static void setup_basics(void) -#elif (!defined(__GNUC__)) -/* #pragma GCC push_options */ -/* #pragma GCC optimize("O0") */ -static void __attribute__((optimize("O0"))) setup_basics(void) -#else -#error "Unknown compiler" -#endif - { uint8_t i = 0, idx = 0; uint16_t family_id = get_family_id(); @@ -149,22 +135,22 @@ static void __attribute__((optimize("O0"))) setup_basics(void) string_board_id[4] = 0; idx = 0; //Family ID - string_family_id[idx++] = hex_to_ascii(((family_id >> 12) & 0xF)); + string_family_id[idx++] = hex_to_ascii(((family_id >> 12) & 0xF)); string_family_id[idx++] = hex_to_ascii(((family_id >> 8) & 0xF)); -#if !(defined(DAPLINK_BL)) && defined(DRAG_N_DROP_SUPPORT) //need to change the unique id when the msd is disabled +#if !(defined(DAPLINK_BL)) && defined(DRAG_N_DROP_SUPPORT) //need to change the unique id when the msd is disabled #if defined(MSC_ENDPOINT) if (config_ram_get_disable_msd() == 1 || flash_algo_valid()==0){ - string_family_id[idx++] = hex_to_ascii((((family_id >> 4) | 0x08) & 0xF)); + string_family_id[idx++] = hex_to_ascii((((family_id >> 4) | 0x08) & 0xF)); } else { string_family_id[idx++] = hex_to_ascii(((family_id >> 4) & 0xF)); } #else //no msd support always have the most significant bit set for family id 2nd byte - string_family_id[idx++] = hex_to_ascii((((family_id >> 4) | 0x08) & 0xF)); + string_family_id[idx++] = hex_to_ascii((((family_id >> 4) | 0x08) & 0xF)); #endif #else string_family_id[idx++] = hex_to_ascii(((family_id >> 4) & 0xF)); #endif - string_family_id[idx++] = hex_to_ascii(((family_id) & 0xF)); + string_family_id[idx++] = hex_to_ascii(((family_id) & 0xF)); string_family_id[idx++] = 0; // Version idx = 0; @@ -338,9 +324,3 @@ uint32_t info_get_interface_version(void) return info_if->version; } -#if (defined(__CC_ARM)) -#pragma pop -#endif -#if (defined(__GNUC__)) -/* #pragma GCC pop_options */ -#endif diff --git a/source/hic_hal/freescale/iap/fsl_flash.c b/source/hic_hal/freescale/iap/fsl_flash.c index 3572183c2..77b145c78 100644 --- a/source/hic_hal/freescale/iap/fsl_flash.c +++ b/source/hic_hal/freescale/iap/fsl_flash.c @@ -2102,7 +2102,7 @@ void flash_cache_clear(flash_config_t *config) #pragma push #pragma O0 void flash_cache_clear(flash_config_t *config) -#elif (!defined(__GNUC__)) +#elif (defined(__GNUC__)) /* #pragma GCC push_options */ /* #pragma GCC optimize("O0") */ void __attribute__((optimize("O0"))) flash_cache_clear(flash_config_t *config) diff --git a/source/target/target_board.c b/source/target/target_board.c index dde63ff42..520353889 100644 --- a/source/target/target_board.c +++ b/source/target/target_board.c @@ -33,46 +33,42 @@ const board_info_t g_board_info = { .daplink_target_url = "https://mbed.org/device/?code=@U?version=@V?target_id=@T", }; +// Disable optimization of these functions. +// +// This is required because for the "no target" builds, the compiler sees g_board_info fields as +// defined above and will elide entire expressions. However, the board and target info may be +// modified using the post processor script, changing what the code sees at runtime. -const char * get_board_id(void) +NO_OPTIMIZE_PRE +const char * NO_OPTIMIZE_INLINE get_board_id(void) { if (g_board_info.target_cfg && g_board_info.target_cfg->rt_board_id) { return g_board_info.target_cfg->rt_board_id; //flexible board id - }else{ + } else { return g_board_info.board_id; } } +NO_OPTIMIZE_POST -uint16_t get_family_id(void) +NO_OPTIMIZE_PRE +uint16_t NO_OPTIMIZE_INLINE get_family_id(void) { if (g_board_info.target_cfg && g_board_info.target_cfg->rt_family_id) { return g_board_info.target_cfg->rt_family_id; //flexible family id - }else{ + } else { return g_board_info.family_id; } } +NO_OPTIMIZE_POST -#if (defined(__ICCARM__)) -#pragma optimize = none -uint8_t flash_algo_valid(void) -#elif (defined(__CC_ARM)) -#pragma push -#pragma O0 -uint8_t flash_algo_valid(void) -#elif (!defined(__GNUC__)) -/* #pragma GCC push_options */ -/* #pragma GCC optimize("O0") */ -uint8_t __attribute__((optimize("O0"))) flash_algo_valid(void) -#else -#error "Unknown compiler" -#endif +// Disable optimization of this function. +// +// This is required because for the "no target" builds, the compiler sees g_board_info.target_cfg as +// NULL and will elide the entire expression. However, the board and target info may be modified +// using the post processor script, changing what the code sees at runtime. +NO_OPTIMIZE_PRE +uint8_t NO_OPTIMIZE_INLINE flash_algo_valid(void) { return (g_board_info.target_cfg != 0); } - -#if (defined(__CC_ARM)) -#pragma pop -#endif -#if (defined(__GNUC__)) -/* #pragma GCC pop_options */ -#endif +NO_OPTIMIZE_POST From 3dbc4bbdf474e9d081bce92ea6a83acb40da8ccc Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sat, 1 Feb 2020 17:49:06 -0600 Subject: [PATCH 018/617] Fixed warning in SAM3U2C usb_config.c. - Missed this file when standardizing on a single MAX() macro. --- source/hic_hal/atmel/sam3u2c/usb_config.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/source/hic_hal/atmel/sam3u2c/usb_config.c b/source/hic_hal/atmel/sam3u2c/usb_config.c index a1f4b8040..89a5320df 100644 --- a/source/hic_hal/atmel/sam3u2c/usb_config.c +++ b/source/hic_hal/atmel/sam3u2c/usb_config.c @@ -19,6 +19,8 @@ * limitations under the License. */ +#include "util.h" + // USB Device // Enable the USB Device functionality #define USBD_ENABLE 1 @@ -395,7 +397,7 @@ #define USBD_IF_NUM_MAX (USBD_BULK_ENABLE+USBD_WEBUSB_ENABLE+USBD_HID_ENABLE+USBD_MSC_ENABLE+(USBD_ADC_ENABLE*2)+(USBD_CDC_ACM_ENABLE*2)+USBD_CLS_ENABLE) #define USBD_MULTI_IF (USBD_CDC_ACM_ENABLE*(USBD_HID_ENABLE|USBD_MSC_ENABLE|USBD_ADC_ENABLE|USBD_CLS_ENABLE|USBD_WEBUSB_ENABLE|USBD_BULK_ENABLE)) -#define MAX(x, y) (((x) < (y)) ? (y) : (x)) +// #define MAX(x, y) (((x) < (y)) ? (y) : (x)) #define USBD_EP_NUM_CALC0 MAX((USBD_HID_ENABLE *(USBD_HID_EP_INTIN )), (USBD_HID_ENABLE *(USBD_HID_EP_INTOUT!=0)*(USBD_HID_EP_INTOUT))) #define USBD_EP_NUM_CALC1 MAX((USBD_MSC_ENABLE *(USBD_MSC_EP_BULKIN )), (USBD_MSC_ENABLE *(USBD_MSC_EP_BULKOUT))) #define USBD_EP_NUM_CALC2 MAX((USBD_ADC_ENABLE *(USBD_ADC_EP_ISOOUT )), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_INTIN))) From 026a5ea089130e7b6de3e49236615e68a3b476dd Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sat, 5 Dec 2020 14:08:49 -0600 Subject: [PATCH 019/617] Change __weak to __WEAK in DAP.c. --- source/daplink/cmsis-dap/DAP.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/source/daplink/cmsis-dap/DAP.c b/source/daplink/cmsis-dap/DAP.c index 0be0f783d..0dd0de463 100644 --- a/source/daplink/cmsis-dap/DAP.c +++ b/source/daplink/cmsis-dap/DAP.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2013-2017 ARM Limited. All rights reserved. - * Copyright 2019, Cypress Semiconductor Corporation + * Copyright 2019, Cypress Semiconductor Corporation * or a subsidiary of Cypress Semiconductor Corporation. * * SPDX-License-Identifier: Apache-2.0 @@ -1624,7 +1624,7 @@ __WEAK uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *respon // response: pointer to response data // return: number of bytes in response (lower 16 bits) // number of bytes in request (upper 16 bits) -__weak uint32_t DAP_ProcessVendorCommandEx(const uint8_t *request, uint8_t *response) { +__WEAK uint32_t DAP_ProcessVendorCommandEx(const uint8_t *request, uint8_t *response) { *response = ID_DAP_Invalid; return ((1U << 16) | 1U); } @@ -1643,7 +1643,7 @@ uint32_t DAP_ProcessCommand(const uint8_t *request, uint8_t *response) { if ((*request >= ID_DAP_VendorExFirst) && (*request <= ID_DAP_VendorExLast)) { return DAP_ProcessVendorCommandEx(request, response); - } + } *response++ = *request; From 63257796a9de1ec25e4e6f658debac3a46792418 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Thu, 28 Nov 2019 16:33:42 -0600 Subject: [PATCH 020/617] HIC armcc record cleanup. - Made armcc sources tool specific. - Added uvision tool data to make_armcc.yaml. - Move M480 armcc startup.s. - Updated uvision project template. --- records/hic_hal/k20dx.yaml | 19 +++------- records/hic_hal/k26f.yaml | 7 +++- records/hic_hal/kl26z.yaml | 7 +++- records/hic_hal/lpc11u35.yaml | 9 +++-- records/hic_hal/lpc4322.yaml | 9 +++-- records/hic_hal/m48ssidae.yaml | 19 +++------- records/hic_hal/max32620.yaml | 7 +++- records/hic_hal/max32625.yaml | 7 +++- records/hic_hal/sam3u2c.yaml | 9 +++-- records/hic_hal/stm32f103xb.yaml | 19 +++------- records/tools/make_armcc.yaml | 38 +++++++++++++++++-- records/tools/uvision.uvproj.tmpl | 4 +- .../M480/Source/ARM => armcc}/startup_M480.s | 0 13 files changed, 96 insertions(+), 58 deletions(-) rename source/hic_hal/nuvoton/m48ssidae/{Device/Nuvoton/M480/Source/ARM => armcc}/startup_M480.s (100%) diff --git a/records/hic_hal/k20dx.yaml b/records/hic_hal/k20dx.yaml index 5b3aa41b0..ff225f7e8 100644 --- a/records/hic_hal/k20dx.yaml +++ b/records/hic_hal/k20dx.yaml @@ -20,7 +20,6 @@ common: - source/hic_hal/freescale - source/hic_hal/freescale/k20dx - source/hic_hal/freescale/k20dx/MK20D5 - - source/hic_hal/freescale/k20dx/armcc fsl_flash_driver: - source/hic_hal/freescale/iap @@ -29,19 +28,13 @@ tool_specific: misc: ld_flags: - --predefine="-I..\..\..\source\hic_hal\freescale\k20dx" - c_flags: - - --no_unaligned_access - cxx_flags: - - --no_unaligned_access - asm_flags: - - --no_unaligned_access + sources: + hic_hal: + - source/hic_hal/freescale/k20dx/armcc make_armcc: misc: ld_flags: - --predefine="-Isource\hic_hal\freescale\k20dx" - c_flags: - - --no_unaligned_access - cxx_flags: - - --no_unaligned_access - asm_flags: - - --no_unaligned_access + sources: + hic_hal: + - source/hic_hal/freescale/k20dx/armcc diff --git a/records/hic_hal/k26f.yaml b/records/hic_hal/k26f.yaml index 382a6142f..cea0fe681 100644 --- a/records/hic_hal/k26f.yaml +++ b/records/hic_hal/k26f.yaml @@ -19,7 +19,6 @@ common: hic_hal: - source/hic_hal/freescale/k26f - source/hic_hal/freescale/k26f/MK26F18 - - source/hic_hal/freescale/k26f/armcc fsl_flash_driver: - source/hic_hal/freescale/iap @@ -35,6 +34,9 @@ tool_specific: - --no_unaligned_access asm_flags: - --no_unaligned_access + sources: + hic_hal: + - source/hic_hal/freescale/k26f/armcc make_armcc: misc: ld_flags: @@ -46,3 +48,6 @@ tool_specific: - --no_unaligned_access asm_flags: - --no_unaligned_access + sources: + hic_hal: + - source/hic_hal/freescale/k26f/armcc diff --git a/records/hic_hal/kl26z.yaml b/records/hic_hal/kl26z.yaml index eee977a79..05d77702b 100644 --- a/records/hic_hal/kl26z.yaml +++ b/records/hic_hal/kl26z.yaml @@ -20,7 +20,6 @@ common: - source/hic_hal/freescale - source/hic_hal/freescale/kl26z - source/hic_hal/freescale/kl26z/MKL26Z4 - - source/hic_hal/freescale/kl26z/armcc fsl_flash_driver: - source/hic_hal/freescale/iap @@ -29,7 +28,13 @@ tool_specific: misc: ld_flags: - --predefine="-I..\..\..\source\hic_hal\freescale\kl26z" + sources: + hic_hal: + - source/hic_hal/freescale/kl26z/armcc make_armcc: misc: ld_flags: - --predefine="-Isource\hic_hal\freescale\kl26z" + sources: + hic_hal: + - source/hic_hal/freescale/kl26z/armcc diff --git a/records/hic_hal/lpc11u35.yaml b/records/hic_hal/lpc11u35.yaml index c19dc0400..66e4fdb2a 100644 --- a/records/hic_hal/lpc11u35.yaml +++ b/records/hic_hal/lpc11u35.yaml @@ -9,19 +9,22 @@ common: - OS_CLOCK=48000000 includes: - source/hic_hal/nxp/lpc11u35 - - source/hic_hal/nxp/lpc11u35 sources: hic_hal: - source/hic_hal/nxp/lpc11u35 - - source/hic_hal/nxp/lpc11u35/armcc - - source/hic_hal/nxp/lpc11u35 tool_specific: uvision: misc: ld_flags: - --predefine="-I..\..\..\source\hic_hal\nxp\lpc11u35" + sources: + hic_hal: + - source/hic_hal/nxp/lpc11u35/armcc make_armcc: misc: ld_flags: - --predefine="-Isource\hic_hal\nxp\lpc11u35" + sources: + hic_hal: + - source/hic_hal/nxp/lpc11u35/armcc diff --git a/records/hic_hal/lpc4322.yaml b/records/hic_hal/lpc4322.yaml index e094d19b9..f019a96f7 100644 --- a/records/hic_hal/lpc4322.yaml +++ b/records/hic_hal/lpc4322.yaml @@ -11,19 +11,22 @@ common: - OS_CLOCK=96000000 includes: - source/hic_hal/nxp/lpc4322 - - source/hic_hal/nxp/lpc4322 sources: hic_hal: - source/hic_hal/nxp/lpc4322 - - source/hic_hal/nxp/lpc4322/armcc - - source/hic_hal/nxp/lpc4322 tool_specific: uvision: misc: ld_flags: - --predefine="-I..\..\..\source\hic_hal\nxp\lpc4322" + sources: + hic_hal: + - source/hic_hal/nxp/lpc4322/armcc make_armcc: misc: ld_flags: - --predefine="-Isource\hic_hal\nxp\lpc4322" + sources: + hic_hal: + - source/hic_hal/nxp/lpc4322/armcc diff --git a/records/hic_hal/m48ssidae.yaml b/records/hic_hal/m48ssidae.yaml index 16c21c9ac..5c81d7db6 100644 --- a/records/hic_hal/m48ssidae.yaml +++ b/records/hic_hal/m48ssidae.yaml @@ -17,7 +17,6 @@ common: hic_hal: - source/hic_hal/nuvoton/m48ssidae - source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Source - - source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Source/ARM - source/hic_hal/nuvoton/m48ssidae/StdDriver/src tool_specific: @@ -25,19 +24,13 @@ tool_specific: misc: ld_flags: - --predefine="-I..\..\..\source\hic_hal\nuvoton\m48ssidae" - c_flags: - - --no_unaligned_access - cxx_flags: - - --no_unaligned_access - asm_flags: - - --no_unaligned_access + sources: + hic_hal: + - source/hic_hal/nuvoton/m48ssidae/armcc make_armcc: misc: ld_flags: - --predefine="-Isource\hic_hal\nuvoton\m48ssidae" - c_flags: - - --no_unaligned_access - cxx_flags: - - --no_unaligned_access - asm_flags: - - --no_unaligned_access + sources: + hic_hal: + - source/hic_hal/nuvoton/m48ssidae/armcc diff --git a/records/hic_hal/max32620.yaml b/records/hic_hal/max32620.yaml index 388a27656..2bd130c93 100644 --- a/records/hic_hal/max32620.yaml +++ b/records/hic_hal/max32620.yaml @@ -12,14 +12,19 @@ common: sources: hic_hal: - source/hic_hal/maxim/max32620 - - source/hic_hal/maxim/max32620/armcc tool_specific: uvision: misc: ld_flags: - --predefine="-I..\..\..\source\hic_hal\maxim\max32620" + sources: + hic_hal: + - source/hic_hal/maxim/max32620/armcc make_armcc: misc: ld_flags: - --predefine="-Isource\hic_hal\maxim\max32620" + sources: + hic_hal: + - source/hic_hal/maxim/max32620/armcc diff --git a/records/hic_hal/max32625.yaml b/records/hic_hal/max32625.yaml index f6fcf178c..669ded18a 100644 --- a/records/hic_hal/max32625.yaml +++ b/records/hic_hal/max32625.yaml @@ -12,14 +12,19 @@ common: sources: hic_hal: - source/hic_hal/maxim/max32625 - - source/hic_hal/maxim/max32625/armcc tool_specific: uvision: misc: ld_flags: - --predefine="-I..\..\..\source\hic_hal\maxim\max32625" + sources: + hic_hal: + - source/hic_hal/maxim/max32625/armcc make_armcc: misc: ld_flags: - --predefine="-Isource\hic_hal\maxim\max32625" + sources: + hic_hal: + - source/hic_hal/maxim/max32625/armcc diff --git a/records/hic_hal/sam3u2c.yaml b/records/hic_hal/sam3u2c.yaml index e80722a19..b08b7af47 100644 --- a/records/hic_hal/sam3u2c.yaml +++ b/records/hic_hal/sam3u2c.yaml @@ -9,21 +9,24 @@ common: - DAPLINK_HIC_ID=0x97969903 # DAPLINK_HIC_ID_SAM3U2C - OS_CLOCK=96000000 includes: - - source/hic_hal/atmel/sam3u2c - source/hic_hal/atmel/sam3u2c - projectfiles/uvision/sam3u2c_bl/build sources: hic_hal: - source/hic_hal/atmel/sam3u2c - - source/hic_hal/atmel/sam3u2c/armcc - - source/hic_hal/atmel/sam3u2c tool_specific: uvision: misc: ld_flags: - --predefine="-I..\..\..\source\hic_hal\atmel\sam3u2c" + sources: + hic_hal: + - source/hic_hal/atmel/sam3u2c/armcc make_armcc: misc: ld_flags: - --predefine="-Isource\hic_hal\atmel\sam3u2c" + sources: + hic_hal: + - source/hic_hal/atmel/sam3u2c/armcc diff --git a/records/hic_hal/stm32f103xb.yaml b/records/hic_hal/stm32f103xb.yaml index e828d5d5b..58fc80236 100644 --- a/records/hic_hal/stm32f103xb.yaml +++ b/records/hic_hal/stm32f103xb.yaml @@ -20,7 +20,6 @@ common: hic_hal: - source/hic_hal/stm32/stm32f103xb - source/hic_hal/stm32/stm32f103xb/cmsis - - source/hic_hal/stm32/stm32f103xb/armcc - source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src tool_specific: @@ -28,19 +27,13 @@ tool_specific: misc: ld_flags: - --predefine="-I..\..\..\source\hic_hal\stm32\stm32f103xb" - c_flags: - - --no_unaligned_access - cxx_flags: - - --no_unaligned_access - asm_flags: - - --no_unaligned_access + sources: + hic_hal: + - source/hic_hal/stm32/stm32f103xb/armcc make_armcc: misc: ld_flags: - --predefine="-Isource\hic_hal\stm32\stm32f103xb" - c_flags: - - --no_unaligned_access - cxx_flags: - - --no_unaligned_access - asm_flags: - - --no_unaligned_access + sources: + hic_hal: + - source/hic_hal/stm32/stm32f103xb/armcc diff --git a/records/tools/make_armcc.yaml b/records/tools/make_armcc.yaml index 4ad2ca915..60961300f 100644 --- a/records/tools/make_armcc.yaml +++ b/records/tools/make_armcc.yaml @@ -7,18 +7,48 @@ tool_specific: linker_file: - source/daplink/daplink.sct misc: - common_flags: - - -c + asm_flags: + - -g c_flags: - -O2 + - -Ospace - --gnu - --c99 + - --asm - --split_sections - --interleave - linker_options: - - nostartfiles + - -g + ld_flags: + - --bestdebug + - --summary_stderr + - --info summarysizes + - --map + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + - --info sizes + - --info totals + - --info unused + - --info veneers + - --list "$@.map" pre_build_script: - tools/pre_build_script.sh post_build_script: - tools/post_build_script.sh + uvision: + misc: + asm_flags: + - -g + c_flags: + # uvision.uvproj.tmpl specifies: + # - O2, space + # - C99 + # - split sections + - --gnu + - --asm + - --interleave + - -g + ld_flags: + - --bestdebug diff --git a/records/tools/uvision.uvproj.tmpl b/records/tools/uvision.uvproj.tmpl index 003abef4a..6fdaf15d6 100644 --- a/records/tools/uvision.uvproj.tmpl +++ b/records/tools/uvision.uvproj.tmpl @@ -356,10 +356,10 @@ 0 0 0 - 0 + 1 0 - --gnu --c99 + diff --git a/source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Source/ARM/startup_M480.s b/source/hic_hal/nuvoton/m48ssidae/armcc/startup_M480.s similarity index 100% rename from source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Source/ARM/startup_M480.s rename to source/hic_hal/nuvoton/m48ssidae/armcc/startup_M480.s From af2f3661453ae2f424000c1f923b74b073987872 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sun, 10 Nov 2019 16:22:46 -0600 Subject: [PATCH 021/617] Fixes to build bootloader. --- source/daplink/bootloader/main.c | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/source/daplink/bootloader/main.c b/source/daplink/bootloader/main.c index 97bef4224..6bdaf09ec 100644 --- a/source/daplink/bootloader/main.c +++ b/source/daplink/bootloader/main.c @@ -38,11 +38,29 @@ #define MSC_LED_DEF GPIO_LED_ON #endif +#if defined(__CC_ARM) __asm void modify_stack_pointer_and_start_app(uint32_t r0_sp, uint32_t r1_pc) { MOV SP, R0 BX R1 } +#elif defined(__GNUC__) +void modify_stack_pointer_and_start_app(uint32_t r0_sp, uint32_t r1_pc) +{ + uint32_t z = 0; + asm volatile ( "msr control, %[z] \n\t" + "isb \n\t" + "mov sp, %[r0_sp] \n\t" + "bx %[r1_pc]" + : + : [z] "l" (z), + [r0_sp] "l" (r0_sp), + [r1_pc] "l" (r1_pc) + ); +} +#else +#error "Unknown compiler!" +#endif // Event flags for main task // Timers events @@ -136,7 +154,7 @@ void main_task(void * arg) flags = osThreadFlagsWait(FLAGS_MAIN_90MS // 90mS tick | FLAGS_MAIN_30MS // 30mS tick | FLAGS_MAIN_PROC_USB // process usb events - , osFlagsWaitAny, + , osFlagsWaitAny, osWaitForever); if (flags & FLAGS_MAIN_PROC_USB) { @@ -202,12 +220,12 @@ void main_task(void * arg) // 30mS tick used for flashing LED when USB is busy if (flags & FLAGS_MAIN_30MS) { if (msc_led_usb_activity) { - + if ((msc_led_state == MAIN_LED_FLASH) || (msc_led_state == MAIN_LED_FLASH_PERMANENT)) { // Toggle LED value msc_led_value = (GPIO_LED_ON == msc_led_value) ? GPIO_LED_OFF : GPIO_LED_ON; // If in flash mode stop after one cycle but in bootloader LED stays on - if ((MSC_LED_DEF == msc_led_value) && (MAIN_LED_FLASH == msc_led_state)) { + if ((MSC_LED_DEF == msc_led_value) && (MAIN_LED_FLASH == msc_led_state)) { msc_led_usb_activity = 0; msc_led_state = MAIN_LED_DEF; } @@ -236,11 +254,15 @@ int main(void) // check for invalid app image or rst button press. Should be checksum or CRC but NVIC validation is better than nothing. // If the interface has set the hold in bootloader setting don't jump to app - if (!gpio_get_reset_btn() && g_board_info.target_cfg && validate_bin_nvic((uint8_t *)g_board_info.target_cfg->flash_regions[0].start) && !config_ram_get_initial_hold_in_bl()) { + if (!gpio_get_reset_btn() + && g_board_info.target_cfg + && validate_bin_nvic((uint8_t *)g_board_info.target_cfg->flash_regions[0].start) + && !config_ram_get_initial_hold_in_bl()) { // change to the new vector table SCB->VTOR = g_board_info.target_cfg->flash_regions[0].start; //bootloaders should only have one flash region for interface // modify stack pointer and start app - modify_stack_pointer_and_start_app((*(uint32_t *)(g_board_info.target_cfg->flash_regions[0].start)), (*(uint32_t *)(g_board_info.target_cfg->flash_regions[0].start + 4))); + modify_stack_pointer_and_start_app((*(uint32_t *)(g_board_info.target_cfg->flash_regions[0].start)), + (*(uint32_t *)(g_board_info.target_cfg->flash_regions[0].start + 4))); } // config the usb interface descriptor and web auth token before USB connects From 9a4413da2ec80ad8bd4dc2b7274ec434706f358a Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Tue, 5 Nov 2019 17:03:04 -0600 Subject: [PATCH 022/617] Fixed cfgram and cfgrom definitions for gcc. - Using zero_init attribute on cfgrom section only for armcc. - Removed zero_init from cfgram. --- source/daplink/settings/settings.c | 4 ++-- source/daplink/settings/settings_rom.c | 6 +++++- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/source/daplink/settings/settings.c b/source/daplink/settings/settings.c index bc55327d1..c51c85085 100644 --- a/source/daplink/settings/settings.c +++ b/source/daplink/settings/settings.c @@ -3,7 +3,7 @@ * @brief Implementation of settings.h * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2020, ARM Limited, All Rights Reserved * Copyright 2019, Cypress Semiconductor Corporation * or a subsidiary of Cypress Semiconductor Corporation. * SPDX-License-Identifier: Apache-2.0 @@ -66,7 +66,7 @@ typedef struct __attribute__((__packed__)) cfg_ram { COMPILER_ASSERT((offsetof(cfg_ram_t, hexdump) % sizeof(uint32_t)) == 0); // Configuration RAM -static cfg_ram_t config_ram __attribute__((section("cfgram"), zero_init)); +static cfg_ram_t config_ram __attribute__((section("cfgram"))); // Ram copy of RAM config static cfg_ram_t config_ram_copy; diff --git a/source/daplink/settings/settings_rom.c b/source/daplink/settings/settings_rom.c index 52943591d..d0908bd12 100644 --- a/source/daplink/settings/settings_rom.c +++ b/source/daplink/settings/settings_rom.c @@ -61,7 +61,11 @@ COMPILER_ASSERT(sizeof(cfg_setting_t) < SECTOR_BUFFER_SIZE); COMPILER_ASSERT(SECTOR_BUFFER_SIZE % 8 == 0); // Configuration ROM -static volatile const cfg_setting_t config_rom __attribute__((section("cfgrom"), zero_init)); +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +static volatile cfg_setting_t config_rom __attribute__((section("cfgrom"),zero_init)); +#else +static volatile cfg_setting_t config_rom __attribute__((section("cfgrom"))); +#endif // Ram copy of ROM config static cfg_setting_t config_rom_copy; From 33b5607ec9bfa2b1cc3b544a29886e621f8ee5f7 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Wed, 13 Nov 2019 16:49:34 -0600 Subject: [PATCH 023/617] Post build script reports address ranges if there is more than one flash region. --- tools/post_build_script.py | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/tools/post_build_script.py b/tools/post_build_script.py index 63f87c327..b2e637f57 100644 --- a/tools/post_build_script.py +++ b/tools/post_build_script.py @@ -69,8 +69,13 @@ def post_build_script(input_file, output_file, board_id=None, family_id=None, bi addresses.sort() start_end_pairs = list(ranges(addresses)) regions = len(start_end_pairs) - assert regions == 1, ("Error - only 1 region allowed in " - "hex file %i found." % regions) + if regions > 1: + print("Error - only 1 region allowed in hex file %i found." % regions) + print("Regions:") + for i, se in enumerate(start_end_pairs): + s, e = se + print(" %d: 0x%08x - 0x%08x" % (i, s, e)) + exit(1) start, end = start_end_pairs[0] pack_flash_algo = None From 3afef212c91eb30b7ac7c8045f265e95def18cfc Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sat, 23 Nov 2019 17:27:03 -0600 Subject: [PATCH 024/617] Shorted some error strings. --- source/daplink/error.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/source/daplink/error.c b/source/daplink/error.c index ab2174985..736fdb437 100644 --- a/source/daplink/error.c +++ b/source/daplink/error.c @@ -48,21 +48,21 @@ static const char *const error_message[] = { /* Target flash errors */ // ERROR_RESET - "The interface firmware FAILED to reset/halt the target MCU", + "Failed to reset/halt the target MCU", // ERROR_ALGO_DL - "The interface firmware FAILED to download the flash programming algorithms to the target MCU", + "Failed to download flash algorithm to target MCU", //ERROR_ALGO_MISSING - "The flash algo missing for a region", + "Flash algorithm missing for a region", // ERROR_ALGO_DATA_SEQ - "The interface firmware FAILED to download the flash data contents to be programmed", + "Failed to download the flash data contents to be programmed", // ERROR_INIT - "The interface firmware FAILED to initialize the target MCU", + "Failed to initialize the target MCU", // ERROR_UNINIT - "The interface firmware FAILED to uninitialize the target MCU", + "Failed to uninitialize the target MCU", // ERROR_SECURITY_BITS - "The interface firmware ABORTED programming. Image is trying to set security bits", + "Programming aborted: image would lock target MCU", // ERROR_UNLOCK - "The interface firmware FAILED to unlock the target for programming", + "Failed to unlock target MCU for programming", // ERROR_ERASE_SECTOR "Flash algorithm erase sector command FAILURE", // ERROR_ERASE_ALL From fdd9db02fdfd635e7fe4a8656f458a858333f75b Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sat, 23 Nov 2019 17:46:26 -0600 Subject: [PATCH 025/617] Support for disabling inclusion of error message strings. - If DAPLINK_NO_ERROR_MESSAGES is defined then the fail.txt file will include only "Error NN" instead of a descriptive error message. - This is required for the Musca-B1 builds to fit in flash with gcc. --- records/board/musca_b.yaml | 1 + records/board/musca_b_eflash.yaml | 1 + source/daplink/error.c | 22 +++++++++++++++++++--- 3 files changed, 21 insertions(+), 3 deletions(-) diff --git a/records/board/musca_b.yaml b/records/board/musca_b.yaml index 9732b21c0..52eb38bc4 100644 --- a/records/board/musca_b.yaml +++ b/records/board/musca_b.yaml @@ -2,6 +2,7 @@ common: macros: - IO_CONFIG_OVERRIDE - MUSCA_B_BOOT_QSPI_FLASH + - DAPLINK_NO_ERROR_MESSAGES includes: - source/board/override_musca_b - source/family/arm/musca_b diff --git a/records/board/musca_b_eflash.yaml b/records/board/musca_b_eflash.yaml index 26c56cb89..7683fb1d5 100644 --- a/records/board/musca_b_eflash.yaml +++ b/records/board/musca_b_eflash.yaml @@ -2,6 +2,7 @@ common: macros: - IO_CONFIG_OVERRIDE - MUSCA_B_BOOT_EFLASH0 + - DAPLINK_NO_ERROR_MESSAGES includes: - source/board/override_musca_b - source/family/arm/musca_b diff --git a/source/daplink/error.c b/source/daplink/error.c index 736fdb437..965c2dfbd 100644 --- a/source/daplink/error.c +++ b/source/daplink/error.c @@ -3,7 +3,7 @@ * @brief Implementation of error.h * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2020, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -19,10 +19,12 @@ * limitations under the License. */ +#include #include "error.h" #include "util.h" #include "compiler.h" +#if !DAPLINK_NO_ERROR_MESSAGES static const char *const error_message[] = { /* Shared errors */ @@ -123,6 +125,10 @@ static const char *const error_message[] = { }; +COMPILER_ASSERT(ERROR_COUNT == ARRAY_SIZE(error_message)); + +#endif // DAPLINK_NO_ERROR_MESSAGES + static error_type_t error_type[] = { /* These should always stay the same for each error type. */ @@ -222,11 +228,12 @@ static error_type_t error_type[] = { ERROR_TYPE_INTERFACE, }; -COMPILER_ASSERT(ERROR_COUNT == ARRAY_SIZE(error_message)); +COMPILER_ASSERT(ERROR_COUNT == ARRAY_SIZE(error_type)); const char *error_get_string(error_t error) { - const char *msg = 0; +#if !DAPLINK_NO_ERROR_MESSAGES + const char *msg = NULL; if (error < ERROR_COUNT) { msg = error_message[error]; @@ -238,6 +245,15 @@ const char *error_get_string(error_t error) } return msg; +#else // DAPLINK_NO_ERROR_MESSAGES + static char error_num_str[10] = "Error 00"; +#define ERROR_NUM_CHAR_INDEX (6) // offset of first '0' in error_num_str[] + + error_num_str[ERROR_NUM_CHAR_INDEX+0] = '0' + ((int)error / 1000) % 10; + error_num_str[ERROR_NUM_CHAR_INDEX+1] = '0' + ((int)error / 100) % 10; + COMPILER_ASSERT(ERROR_COUNT < 100); // if this assert is hit, add a digit here + error_num_str[ERROR_NUM_CHAR_INDEX+2] = 0; +#endif // DAPLINK_NO_ERROR_MESSAGES } error_type_t error_get_type(error_t error) From d16c7dd1bee673bd85ab9fe2d1351d2543e9d27a Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Mon, 18 Nov 2019 17:30:04 -0600 Subject: [PATCH 026/617] Setting optimization of SW_DP.c for to -O3 with pragma. --- source/daplink/cmsis-dap/SW_DP.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/source/daplink/cmsis-dap/SW_DP.c b/source/daplink/cmsis-dap/SW_DP.c index 803cf421e..932cfceb8 100644 --- a/source/daplink/cmsis-dap/SW_DP.c +++ b/source/daplink/cmsis-dap/SW_DP.c @@ -28,6 +28,14 @@ #include "DAP_config.h" #include "DAP.h" +#if defined(__CC_ARM) +#pragma push +#pragma O3 +#pragma Otime +#elif defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize("O3") +#endif // SW Macros @@ -284,3 +292,10 @@ uint8_t SWD_Transfer(uint32_t request, uint32_t *data) { #endif /* (DAP_SWD != 0) */ + + +#if defined(__CC_ARM) +#pragma pop +#elif defined(__GNUC__) +#pragma GCC pop_options +#endif From 35ecf000fcd2ba5515dfec792ab0acbabdfbfe69 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 5 Dec 2020 17:14:11 -0600 Subject: [PATCH 027/617] Make some python files not interfere with caller when used as libraries --- tools/make_update_yml.py | 3 --- tools/mbedcli_compile.py | 3 ++- tools/package_release_files.py | 35 +++++++++++++++------------------- 3 files changed, 17 insertions(+), 24 deletions(-) diff --git a/tools/make_update_yml.py b/tools/make_update_yml.py index 5b01600bb..9e705d606 100644 --- a/tools/make_update_yml.py +++ b/tools/make_update_yml.py @@ -18,10 +18,7 @@ import logging -logging.basicConfig(format='Line: %(lineno)d %(message)s') logger = logging.getLogger('yaml gen') -logger.setLevel(logging.DEBUG) - class DefaultList(list): def sort(self, *args, **kwargs): diff --git a/tools/mbedcli_compile.py b/tools/mbedcli_compile.py index a26e64da2..2291d6cd3 100755 --- a/tools/mbedcli_compile.py +++ b/tools/mbedcli_compile.py @@ -119,6 +119,7 @@ def main(): shutil.rmtree(release_dir, ignore_errors=True) print("Releasing directory: " + release_dir) toolchain_dir = args.toolchain+"-CUSTOM_PROFILE" - package_release_files(args.build_folder, release_dir, release_version, toolchain_dir) + package_release_files(args.build_folder, release_dir, release_version, toolchain_dir, + info.PROJECT_RELEASE_INFO, info.SUPPORTED_CONFIGURATIONS) main() diff --git a/tools/package_release_files.py b/tools/package_release_files.py index 5d85bb6a8..5ae31cf34 100644 --- a/tools/package_release_files.py +++ b/tools/package_release_files.py @@ -22,21 +22,8 @@ import argparse import yaml import subprocess - -self_path = os.path.abspath(__file__) -tools_dir = os.path.dirname(self_path) -daplink_dir = os.path.dirname(tools_dir) -test_dir = os.path.join(daplink_dir, "test") -sys.path.append(test_dir) - -import info - -from make_update_yml import DefaultList -from make_update_yml import TargetList -from make_update_yml import InstructionsText -from make_update_yml import make_update_yml_file - import zipfile +from make_update_yml import DefaultList, TargetList, InstructionsText, make_update_yml_file def make_bin_zip(dir, name): working_dir = os.getcwd() @@ -48,8 +35,7 @@ def make_bin_zip(dir, name): #go back os.chdir(working_dir) -def package_release_files(source, dest, version, toolchain): - +def package_release_files(source, dest, version, toolchain, release_info, supported_configurations): proj_dir = source output_dir = dest build_number = "%04i" % version @@ -67,7 +53,7 @@ def package_release_files(source, dest, version, toolchain): os.mkdir(output_dir) - for prj_name, legacy, offset, extension in info.PROJECT_RELEASE_INFO: + for prj_name, legacy, offset, extension in release_info: legacy_str = "_legacy" if legacy else "" source_offset_str = "_0x%04x" % offset if legacy else "" source_name = prj_name + "_crc" + legacy_str + source_offset_str + "." + extension @@ -86,7 +72,7 @@ def package_release_files(source, dest, version, toolchain): shutil.copyfile(source_path, dest_path) product_code = 'NOT SUPPORTED' - for board_id, family_id, fimware, bootloader, target in info.SUPPORTED_CONFIGURATIONS: + for board_id, family_id, fimware, bootloader, target in supported_configurations: if fimware == prj_name: product_code = board_id if target is not None: @@ -113,6 +99,14 @@ def package_release_files(source, dest, version, toolchain): make_update_yml_file(os.path.join(output_dir, 'update.yml'), update_yml_entries, explicit_start=True) if __name__ == "__main__": + self_path = os.path.abspath(__file__) + tools_dir = os.path.dirname(self_path) + daplink_dir = os.path.dirname(tools_dir) + test_dir = os.path.join(daplink_dir, "test") + sys.path.append(test_dir) + + import info + parser = argparse.ArgumentParser(description='Package a release for distribution') parser.add_argument('source', help='Release directory to grab files from') parser.add_argument('dest', help='Directory to create and place files in') @@ -120,6 +114,7 @@ def package_release_files(source, dest, version, toolchain): parser.add_argument('--toolchain', type=str, default='', help='Toolchain directory if present') args = parser.parse_args() - print("args",args.source,args.dest,args.version,args.toolchain) + print("args", args.source, args.dest, args.version, args.toolchain) - package_release_files(args.source,args.dest,args.version,args.toolchain) + package_release_files(args.source, args.dest, args.version, args.toolchain, + info.PROJECT_RELEASE_INFO, info.SUPPORTED_CONFIGURATIONS) From ab2baf30edf524aa2e0aec13ba89448dba411b2b Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 5 Dec 2020 17:17:03 -0600 Subject: [PATCH 028/617] Small minor changes --- .gitignore | 1 + test/info.py | 2 +- tools/package_release_files.py | 4 ++-- tools/pre_build_script.sh | 2 +- 4 files changed, 5 insertions(+), 4 deletions(-) diff --git a/.gitignore b/.gitignore index 7b22078b8..5fd84dbbd 100644 --- a/.gitignore +++ b/.gitignore @@ -42,6 +42,7 @@ tmp/ *.axf *.S19 *.bin +*.hex *.dep *.FLM diff --git a/test/info.py b/test/info.py index c8a8a40d6..7b948ca5e 100644 --- a/test/info.py +++ b/test/info.py @@ -59,7 +59,7 @@ ("k20dx_mimxrt1050_evk_hyper_if", True, 0x8000, "bin" ), ("k20dx_mimxrt1050_evk_qspi_if", True, 0x8000, "bin" ), ('k20dx_ep_agora_if', True, 0x0000, "bin" ), - ('k20dx_ep_kairos_if', True, 0x0000, "bin" ), + ('k20dx_ep_kairos_if', True, 0x0000, "bin" ), ("k26f_frdmk32w042_if", False, 0x8000, "bin" ), ("lpc11u35_archble_if", False, 0x0000, "bin" ), ("lpc11u35_archpro_if", False, 0x0000, "bin" ), diff --git a/tools/package_release_files.py b/tools/package_release_files.py index 5ae31cf34..00208ce23 100644 --- a/tools/package_release_files.py +++ b/tools/package_release_files.py @@ -84,7 +84,7 @@ def package_release_files(source, dest, version, toolchain, release_info, suppor for fw_name_key in InstructionsText: if fw_name_key in dest_name.lower(): fw_instuction = InstructionsText[fw_name_key] - break; + break if extension == 'bin': update_yml_entries.append({target_name:TargetList([ @@ -92,7 +92,7 @@ def package_release_files(source, dest, version, toolchain, release_info, suppor ('product_code', "'" + format(product_code, '04x') + "'"), ('fw_name', host_mcu + "_" + base_name + dest_offset_str), ('instructions', fw_instuction) - ])}); + ])}) make_bin_zip(output_dir, build_number + '_release_package_' + subprocess.check_output(['git', 'rev-parse', '--short', 'HEAD']).decode().strip() + '.zip') diff --git a/tools/pre_build_script.sh b/tools/pre_build_script.sh index 7dcc5fa76..bc640a155 100755 --- a/tools/pre_build_script.sh +++ b/tools/pre_build_script.sh @@ -21,7 +21,7 @@ export TOOLS=../../../tools export DIR=../../../source/daplink # Create dsion_git_tmpl.txt ${DIR}\version_git.h -python --version 2> nul +# python --version # Run python script to delete default version_git.h and create the real one python ${TOOLS}/pre_build_script.py From 2fd2a102d2e570dfdd1e984aac316f9fa886b667 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 5 Dec 2020 22:25:47 -0600 Subject: [PATCH 029/617] Update armcc post-build script to use new post_build_script.py --- records/tools/make_armcc.yaml | 2 +- ...uild_script.sh => post_build_script_armcc.sh} | 16 ++++++++++++---- 2 files changed, 13 insertions(+), 5 deletions(-) rename tools/{post_build_script.sh => post_build_script_armcc.sh} (68%) diff --git a/records/tools/make_armcc.yaml b/records/tools/make_armcc.yaml index 60961300f..7104877ca 100644 --- a/records/tools/make_armcc.yaml +++ b/records/tools/make_armcc.yaml @@ -35,7 +35,7 @@ tool_specific: pre_build_script: - tools/pre_build_script.sh post_build_script: - - tools/post_build_script.sh + - tools/post_build_script_armcc.sh uvision: misc: asm_flags: diff --git a/tools/post_build_script.sh b/tools/post_build_script_armcc.sh similarity index 68% rename from tools/post_build_script.sh rename to tools/post_build_script_armcc.sh index 225c999f1..e8e74f96e 100755 --- a/tools/post_build_script.sh +++ b/tools/post_build_script_armcc.sh @@ -17,13 +17,21 @@ ## limitations under the License. ## -export PROJECT_DIR=build -export TOOLS=../../../tools +PROJECT_DIR=build +TOOLS=../../../tools +PROJECT_NAME=$(basename $PWD) -python --version 2> /dev/null +INFILE=${PROJECT_DIR}/${PROJECT_NAME}.hex +OUTBASE=${PROJECT_DIR}/${PROJECT_NAME}_crc +CRCBIN=${OUTBASE}.bin fromelf --bin $PROJECT_DIR/*.axf -o $PROJECT_DIR/firmware.bin fromelf --i32 $PROJECT_DIR/*.axf -o $PROJECT_DIR/firmware.hex -python ${TOOLS}/post_compute_crc.py ${PROJECT_DIR}/firmware.hex ${PROJECT_DIR}/firmware_crc +# Only execute the post build script if the input is newer than output, or the +# output doesn't exist. +if [[ "$INFILE" -nt "$CRCBIN" ]]; then + python "${TOOLS}/post_build_script.py" "$INFILE" "$OUTBASE" +fi + From 24c6d4ad728834d586281b5d5a5ba90b3844cea3 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 5 Dec 2020 22:26:29 -0600 Subject: [PATCH 030/617] Add support for Python 3 to post_build_script.py --- tools/post_build_script.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tools/post_build_script.py b/tools/post_build_script.py index b2e637f57..8c4eacea9 100644 --- a/tools/post_build_script.py +++ b/tools/post_build_script.py @@ -19,6 +19,7 @@ from __future__ import absolute_import from __future__ import print_function +import sys import argparse import itertools import binascii @@ -115,7 +116,9 @@ def post_build_script(input_file, output_file, board_id=None, family_id=None, bi new_hex_file.puts(target_addr_unpack + 2,struct.pack('<1H',int(family_id, 16))) #board_id is in string hex if board_id is not None: - new_hex_file.puts(target_addr_unpack + 4,struct.pack('4s',"%.04X" % int(board_id, 16))) + board_id_str = "%.04X" % int(board_id, 16) + board_id_bytes = bytes(board_id_str) if sys.version_info < (3, 0) else bytes(board_id_str, 'utf8') + new_hex_file.puts(target_addr_unpack + 4, struct.pack('4s', board_id_bytes)) if pack_flash_algo is not None: blob_header = (0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2) stack_size = 0x200 From 20180c2f89e3a04949e7aa3d66d28631acd7fcbb Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 14 Dec 2020 16:18:14 -0600 Subject: [PATCH 031/617] Fix for armclang support --- source/daplink/settings/settings_rom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/daplink/settings/settings_rom.c b/source/daplink/settings/settings_rom.c index d0908bd12..d1481d23e 100644 --- a/source/daplink/settings/settings_rom.c +++ b/source/daplink/settings/settings_rom.c @@ -61,7 +61,7 @@ COMPILER_ASSERT(sizeof(cfg_setting_t) < SECTOR_BUFFER_SIZE); COMPILER_ASSERT(SECTOR_BUFFER_SIZE % 8 == 0); // Configuration ROM -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +#if defined(__CC_ARM) static volatile cfg_setting_t config_rom __attribute__((section("cfgrom"),zero_init)); #else static volatile cfg_setting_t config_rom __attribute__((section("cfgrom"))); From 0c686f25f27043284f1ee0176d5cd517a47e4b58 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 9 Dec 2020 21:30:06 -0600 Subject: [PATCH 032/617] Fix portability issues for armclang --- source/daplink/HardFault_Handler.c | 2 +- source/daplink/bootloader/main.c | 18 +++++++++--------- source/daplink/compiler.h | 6 +++++- source/hic_hal/freescale/iap/fsl_flash.c | 2 ++ source/hic_hal/freescale/k20dx/MK20D5/MK20D5.h | 4 ++-- .../hic_hal/freescale/kl26z/MKL26Z4/MKL26Z4.h | 4 ++-- .../maxim/max32620/armcc/startup_MAX32620.S | 1 - .../maxim/max32625/armcc/startup_MAX32625.S | 1 - source/hic_hal/nxp/lpc4322/LPC43xx.h | 4 ++-- source/usb/usb_lib.c | 2 ++ 10 files changed, 25 insertions(+), 19 deletions(-) diff --git a/source/daplink/HardFault_Handler.c b/source/daplink/HardFault_Handler.c index 537e1ec2c..ff7d9ee84 100644 --- a/source/daplink/HardFault_Handler.c +++ b/source/daplink/HardFault_Handler.c @@ -70,7 +70,7 @@ __NO_RETURN void _fault_handler(uint32_t _lr) while (1); // Wait for reset } -#if defined(__CC_ARM) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) void HardFault_Handler() { register unsigned int _lr __asm("lr"); diff --git a/source/daplink/bootloader/main.c b/source/daplink/bootloader/main.c index 6bdaf09ec..4969e20a6 100644 --- a/source/daplink/bootloader/main.c +++ b/source/daplink/bootloader/main.c @@ -48,15 +48,15 @@ __asm void modify_stack_pointer_and_start_app(uint32_t r0_sp, uint32_t r1_pc) void modify_stack_pointer_and_start_app(uint32_t r0_sp, uint32_t r1_pc) { uint32_t z = 0; - asm volatile ( "msr control, %[z] \n\t" - "isb \n\t" - "mov sp, %[r0_sp] \n\t" - "bx %[r1_pc]" - : - : [z] "l" (z), - [r0_sp] "l" (r0_sp), - [r1_pc] "l" (r1_pc) - ); + __ASM volatile ( "msr control, %[z] \n\t" + "isb \n\t" + "mov sp, %[r0_sp] \n\t" + "bx %[r1_pc]" + : + : [z] "l" (z), + [r0_sp] "l" (r0_sp), + [r1_pc] "l" (r1_pc) + ); } #else #error "Unknown compiler!" diff --git a/source/daplink/compiler.h b/source/daplink/compiler.h index 38d64bc36..0d9e73a65 100644 --- a/source/daplink/compiler.h +++ b/source/daplink/compiler.h @@ -44,11 +44,15 @@ extern "C" { #define NO_OPTIMIZE_PRE _Pragma("optimize = none") #define NO_OPTIMIZE_INLINE #define NO_OPTIMIZE_POST -#elif (defined(__CC_ARM)) +#elif (defined(__CC_ARM)) /* ARMCC */ #define NO_OPTIMIZE_PRE _Pragma("push") \ _Pragma("O0") #define NO_OPTIMIZE_INLINE #define NO_OPTIMIZE_POST _Pragma("pop") +#elif (defined(__ARMCC_VERSION)) /* ARMCLANG */ +#define NO_OPTIMIZE_PRE +#define NO_OPTIMIZE_INLINE +#define NO_OPTIMIZE_POST #elif (defined(__GNUC__)) #define NO_OPTIMIZE_PRE #define NO_OPTIMIZE_INLINE __attribute__((optimize("O0"))) diff --git a/source/hic_hal/freescale/iap/fsl_flash.c b/source/hic_hal/freescale/iap/fsl_flash.c index 77b145c78..b704c2791 100644 --- a/source/hic_hal/freescale/iap/fsl_flash.c +++ b/source/hic_hal/freescale/iap/fsl_flash.c @@ -2102,6 +2102,8 @@ void flash_cache_clear(flash_config_t *config) #pragma push #pragma O0 void flash_cache_clear(flash_config_t *config) +#elif (defined(__ARMCC_VERSION)) +void flash_cache_clear(flash_config_t *config) #elif (defined(__GNUC__)) /* #pragma GCC push_options */ /* #pragma GCC optimize("O0") */ diff --git a/source/hic_hal/freescale/k20dx/MK20D5/MK20D5.h b/source/hic_hal/freescale/k20dx/MK20D5/MK20D5.h index aa8c33d78..a2bab5705 100644 --- a/source/hic_hal/freescale/k20dx/MK20D5/MK20D5.h +++ b/source/hic_hal/freescale/k20dx/MK20D5/MK20D5.h @@ -353,7 +353,7 @@ typedef enum _dma_request_source ** Start of section using anonymous unions */ -#if defined(__ARMCC_VERSION) +#if defined(__CC_ARM) #pragma push #pragma anon_unions #elif defined(__CWCC__) @@ -7664,7 +7664,7 @@ typedef struct { ** End of section using anonymous unions */ -#if defined(__ARMCC_VERSION) +#if defined(__CC_ARM) #pragma pop #elif defined(__CWCC__) #pragma pop diff --git a/source/hic_hal/freescale/kl26z/MKL26Z4/MKL26Z4.h b/source/hic_hal/freescale/kl26z/MKL26Z4/MKL26Z4.h index 6be699344..5ef277acf 100644 --- a/source/hic_hal/freescale/kl26z/MKL26Z4/MKL26Z4.h +++ b/source/hic_hal/freescale/kl26z/MKL26Z4/MKL26Z4.h @@ -314,7 +314,7 @@ typedef enum _dma_request_source ** Start of section using anonymous unions */ -#if defined(__ARMCC_VERSION) +#if defined(__CC_ARM) #pragma push #pragma anon_unions #elif defined(__CWCC__) @@ -5839,7 +5839,7 @@ typedef struct { ** End of section using anonymous unions */ -#if defined(__ARMCC_VERSION) +#if defined(__CC_ARM) #pragma pop #elif defined(__CWCC__) #pragma pop diff --git a/source/hic_hal/maxim/max32620/armcc/startup_MAX32620.S b/source/hic_hal/maxim/max32620/armcc/startup_MAX32620.S index 9839266d9..376ae36ed 100644 --- a/source/hic_hal/maxim/max32620/armcc/startup_MAX32620.S +++ b/source/hic_hal/maxim/max32620/armcc/startup_MAX32620.S @@ -59,7 +59,6 @@ __heap_limit ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY - EXPORT __initial_sp EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size diff --git a/source/hic_hal/maxim/max32625/armcc/startup_MAX32625.S b/source/hic_hal/maxim/max32625/armcc/startup_MAX32625.S index 657df9ccb..f68a64461 100755 --- a/source/hic_hal/maxim/max32625/armcc/startup_MAX32625.S +++ b/source/hic_hal/maxim/max32625/armcc/startup_MAX32625.S @@ -59,7 +59,6 @@ __heap_limit ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY - EXPORT __initial_sp EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size diff --git a/source/hic_hal/nxp/lpc4322/LPC43xx.h b/source/hic_hal/nxp/lpc4322/LPC43xx.h index 9678ccaed..1b0006fac 100644 --- a/source/hic_hal/nxp/lpc4322/LPC43xx.h +++ b/source/hic_hal/nxp/lpc4322/LPC43xx.h @@ -40,7 +40,7 @@ extern "C" { ** Start of section using anonymous unions ** *********************************************/ -#if defined(__ARMCC_VERSION) +#if defined(__CC_ARM) #pragma push #pragma anon_unions #elif defined(__CWCC__) @@ -2161,7 +2161,7 @@ typedef struct { /*!< (@ 0x40101000) SGPIO Structure ** End of section using anonymous unions ** *********************************************/ -#if defined(__ARMCC_VERSION) +#if defined(__CC_ARM) #pragma pop #elif defined(__CWCC__) #pragma pop diff --git a/source/usb/usb_lib.c b/source/usb/usb_lib.c index 457d21c50..12f7b694f 100644 --- a/source/usb/usb_lib.c +++ b/source/usb/usb_lib.c @@ -25,8 +25,10 @@ #include "settings.h" #include "compiler.h" +#if defined(__CC_ARM) #pragma thumb #pragma O3 +#endif /*------------------------------------------------------------------------------ From baeb34457e4b12152b5b1baf5f363e4dae85dd55 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 9 Dec 2020 21:41:11 -0600 Subject: [PATCH 033/617] Minor cleanup --- records/hic_hal/k20dx.yaml | 3 ++- records/hic_hal/k26f.yaml | 3 ++- records/hic_hal/kl26z.yaml | 3 ++- records/hic_hal/sam3u2c.yaml | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/records/hic_hal/k20dx.yaml b/records/hic_hal/k20dx.yaml index ff225f7e8..c274f84b6 100644 --- a/records/hic_hal/k20dx.yaml +++ b/records/hic_hal/k20dx.yaml @@ -14,7 +14,6 @@ common: includes: - source/hic_hal/freescale/k20dx - source/hic_hal/freescale/k20dx/MK20D5 - - projectfiles/uvision/k20dx_bl/build sources: hic_hal: - source/hic_hal/freescale @@ -28,6 +27,8 @@ tool_specific: misc: ld_flags: - --predefine="-I..\..\..\source\hic_hal\freescale\k20dx" + includes: + - projectfiles/uvision/k20dx_bl/build sources: hic_hal: - source/hic_hal/freescale/k20dx/armcc diff --git a/records/hic_hal/k26f.yaml b/records/hic_hal/k26f.yaml index cea0fe681..6d18f23fe 100644 --- a/records/hic_hal/k26f.yaml +++ b/records/hic_hal/k26f.yaml @@ -14,7 +14,6 @@ common: - source/hic_hal/freescale/k26f - source/hic_hal/freescale/k26f/MK26F18 - source/hic_hal/freescale/iap - - projectfiles/uvision/k26f_bl/build sources: hic_hal: - source/hic_hal/freescale/k26f @@ -34,6 +33,8 @@ tool_specific: - --no_unaligned_access asm_flags: - --no_unaligned_access + includes: + - projectfiles/uvision/k26f_bl/build sources: hic_hal: - source/hic_hal/freescale/k26f/armcc diff --git a/records/hic_hal/kl26z.yaml b/records/hic_hal/kl26z.yaml index 05d77702b..98596443e 100644 --- a/records/hic_hal/kl26z.yaml +++ b/records/hic_hal/kl26z.yaml @@ -14,7 +14,6 @@ common: includes: - source/hic_hal/freescale/kl26z - source/hic_hal/freescale/kl26z/MKL26Z4 - - projectfiles/uvision/kl26z_bl/build sources: hic_hal: - source/hic_hal/freescale @@ -28,6 +27,8 @@ tool_specific: misc: ld_flags: - --predefine="-I..\..\..\source\hic_hal\freescale\kl26z" + includes: + - projectfiles/uvision/kl26z_bl/build sources: hic_hal: - source/hic_hal/freescale/kl26z/armcc diff --git a/records/hic_hal/sam3u2c.yaml b/records/hic_hal/sam3u2c.yaml index b08b7af47..6ce1eae72 100644 --- a/records/hic_hal/sam3u2c.yaml +++ b/records/hic_hal/sam3u2c.yaml @@ -10,7 +10,6 @@ common: - OS_CLOCK=96000000 includes: - source/hic_hal/atmel/sam3u2c - - projectfiles/uvision/sam3u2c_bl/build sources: hic_hal: - source/hic_hal/atmel/sam3u2c @@ -20,6 +19,8 @@ tool_specific: misc: ld_flags: - --predefine="-I..\..\..\source\hic_hal\atmel\sam3u2c" + includes: + - projectfiles/uvision/sam3u2c_bl/build sources: hic_hal: - source/hic_hal/atmel/sam3u2c/armcc From 1360dce4bc7985f1bf66a1a8c7548b14e0d5e611 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 17 Dec 2020 22:23:47 -0600 Subject: [PATCH 034/617] Fixes to remove armclang warnings --- source/daplink/cmsis-dap/SW_DP.c | 4 ++-- source/daplink/interface/bootloader_update.c | 2 ++ source/usb/usb_lib.c | 6 +++--- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/source/daplink/cmsis-dap/SW_DP.c b/source/daplink/cmsis-dap/SW_DP.c index 932cfceb8..59d22d934 100644 --- a/source/daplink/cmsis-dap/SW_DP.c +++ b/source/daplink/cmsis-dap/SW_DP.c @@ -32,7 +32,7 @@ #pragma push #pragma O3 #pragma Otime -#elif defined(__GNUC__) +#elif defined(__GNUC__) && !defined(__ARMCC_VERSION) #pragma GCC push_options #pragma GCC optimize("O3") #endif @@ -296,6 +296,6 @@ uint8_t SWD_Transfer(uint32_t request, uint32_t *data) { #if defined(__CC_ARM) #pragma pop -#elif defined(__GNUC__) +#elif defined(__GNUC__) && !defined(__ARMCC_VERSION) #pragma GCC pop_options #endif diff --git a/source/daplink/interface/bootloader_update.c b/source/daplink/interface/bootloader_update.c index c02170670..2af91401b 100644 --- a/source/daplink/interface/bootloader_update.c +++ b/source/daplink/interface/bootloader_update.c @@ -29,9 +29,11 @@ #include "daplink.h" #include "crc.h" +#if defined(__CC_ARM) // Supress the warning 'null argument provided for parameter marked with attribute "nonnull"' // since the vector table is at address 0 #pragma diag_suppress 2748 +#endif #if !defined(DAPLINK_BOOTLOADER_UPDATE) #define DAPLINK_BOOTLOADER_UPDATE 0 diff --git a/source/usb/usb_lib.c b/source/usb/usb_lib.c index 12f7b694f..cbf06ff96 100644 --- a/source/usb/usb_lib.c +++ b/source/usb/usb_lib.c @@ -162,7 +162,7 @@ U8 USBD_Bulk_BulkOutBuf[USBD_BULK_MAX_PACKET]; #if (USBD_HID_ENABLE) #ifndef __RTX -void USBD_Configure_Event(void) +__WEAK void USBD_Configure_Event(void) { USBD_HID_Configure_Event(); } @@ -1056,7 +1056,7 @@ BOOL USBD_EndPoint0_Out_CLS_ReqToEP(void) #if ((USBD_CDC_ACM_ENABLE)) #ifndef __RTX -void USBD_Reset_Event(void) +__WEAK void USBD_Reset_Event(void) { #if (USBD_CDC_ACM_ENABLE) USBD_CDC_ACM_Reset_Event(); @@ -1070,7 +1070,7 @@ void USBD_Reset_Event(void) #if ((USBD_HID_ENABLE) || (USBD_ADC_ENABLE) || (USBD_CDC_ACM_ENABLE) || (USBD_CLS_ENABLE)) #ifndef __RTX -void USBD_SOF_Event(void) +__WEAK void USBD_SOF_Event(void) { #if (USBD_HID_ENABLE) USBD_HID_SOF_Event(); From 4299c5b0073cdf89f7608b06b835a282b89e64fd Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Wed, 16 Dec 2020 17:07:04 -0600 Subject: [PATCH 035/617] Interface: moved bootloader_check_and_update() to after info_init(). This change prevents computing the CRC of the interface twice. --- source/daplink/interface/main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/source/daplink/interface/main.c b/source/daplink/interface/main.c index 42e3d6499..d6229e9de 100644 --- a/source/daplink/interface/main.c +++ b/source/daplink/interface/main.c @@ -198,8 +198,6 @@ void main_task(void * arg) // Initialize settings - required for asserts to work config_init(); - // Update bootloader if it is out of date - bootloader_check_and_update(); // Get a reference to this task main_task_id = osThreadGetId(); // leds @@ -238,6 +236,8 @@ void main_task(void * arg) // Update versions and IDs info_init(); + // Update bootloader if it is out of date + bootloader_check_and_update(); // USB usbd_init(); #ifdef DRAG_N_DROP_SUPPORT From fe9bea168ddbcce02fa932b26fde00d0e931820e Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Thu, 17 Dec 2020 12:03:45 -0600 Subject: [PATCH 036/617] Make main.* file names unique. - Renamed main.{c,h} to main_{bootloader,interface}.{c,h}. - daplink.h defines a DAPLINK_MAIN_HEADER macro with the name of the main app header for the current project. - Updated files that include "main.h" to use the header name macro. --- source/daplink/bootloader/{main.c => main_bootloader.c} | 6 +++--- source/daplink/bootloader/{main.h => main_bootloader.h} | 8 ++++---- source/daplink/cmsis-dap/DAP_vendor.c | 9 +++++---- source/daplink/daplink.h | 9 +++++++++ source/daplink/drag-n-drop/vfs_manager.c | 6 +++--- source/daplink/info.c | 3 +-- source/daplink/interface/{main.c => main_interface.c} | 6 +++--- source/daplink/interface/{main.h => main_interface.h} | 8 ++++---- source/daplink/usb2uart/usbd_user_cdc_acm.c | 5 +++-- source/usb/hid/usbd_user_hid.c | 5 +++-- 10 files changed, 38 insertions(+), 27 deletions(-) rename source/daplink/bootloader/{main.c => main_bootloader.c} (98%) rename source/daplink/bootloader/{main.h => main_bootloader.h} (94%) rename source/daplink/interface/{main.c => main_interface.c} (99%) rename source/daplink/interface/{main.h => main_interface.h} (91%) diff --git a/source/daplink/bootloader/main.c b/source/daplink/bootloader/main_bootloader.c similarity index 98% rename from source/daplink/bootloader/main.c rename to source/daplink/bootloader/main_bootloader.c index 4969e20a6..8879e23ea 100644 --- a/source/daplink/bootloader/main.c +++ b/source/daplink/bootloader/main_bootloader.c @@ -1,9 +1,9 @@ /** - * @file main.c + * @file main_bootloader.c * @brief DAPLink Bootloader application entry point * * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2020 Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -19,7 +19,7 @@ * limitations under the License. */ -#include "main.h" +#include "main_bootloader.h" #include "gpio.h" #include "validation.h" #include "vfs_manager.h" diff --git a/source/daplink/bootloader/main.h b/source/daplink/bootloader/main_bootloader.h similarity index 94% rename from source/daplink/bootloader/main.h rename to source/daplink/bootloader/main_bootloader.h index c52bedd40..cd71a3ce8 100644 --- a/source/daplink/bootloader/main.h +++ b/source/daplink/bootloader/main_bootloader.h @@ -1,9 +1,9 @@ /** - * @file main.h + * @file main_bootloader.h * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2020 Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -19,8 +19,8 @@ * limitations under the License. */ -#ifndef MAIN_H -#define MAIN_H +#ifndef MAIN_BOOTLOADER_H +#define MAIN_BOOTLOADER_H #include diff --git a/source/daplink/cmsis-dap/DAP_vendor.c b/source/daplink/cmsis-dap/DAP_vendor.c index 1a608d679..5a4fd79db 100644 --- a/source/daplink/cmsis-dap/DAP_vendor.c +++ b/source/daplink/cmsis-dap/DAP_vendor.c @@ -1,6 +1,6 @@ /* - * Copyright (c) 2013-2016 ARM Limited. All rights reserved. - * Copyright 2019, Cypress Semiconductor Corporation + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * Copyright 2019, Cypress Semiconductor Corporation * or a subsidiary of Cypress Semiconductor Corporation. * * SPDX-License-Identifier: Apache-2.0 @@ -31,7 +31,8 @@ #include "DAP_config.h" #include "DAP.h" #include "info.h" -#include "main.h" +#include "daplink.h" +#include DAPLINK_MAIN_HEADER #include "uart.h" #include "settings.h" #include "target_family.h" @@ -169,7 +170,7 @@ uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { // 0x00 - Chip Erase // nonzero - Page Erase // RESPONSE(IN Packet) - // BYTE 0 + // BYTE 0 // 0x00 - OK *response = DAP_OK; if (0x00U == *request) { diff --git a/source/daplink/daplink.h b/source/daplink/daplink.h index f0ebd70ad..05ef8e333 100644 --- a/source/daplink/daplink.h +++ b/source/daplink/daplink.h @@ -73,6 +73,15 @@ COMPILER_ASSERT(DAPLINK_RAM_SHARED_START + DAPLINK_RAM_SHARED_SIZE == DAPLINK_RA #define DAPLINK_INFO_OFFSET 0x20 +// Macro with the name of the main application header file. +#if defined(DAPLINK_BL) +#define DAPLINK_MAIN_HEADER "main_bootloader.h" +#elif defined(DAPLINK_IF) +#define DAPLINK_MAIN_HEADER "main_interface.h" +#else +#error "Neither DAPLINK_BL nor DAPLINK_IF are defined!" +#endif + typedef struct { uint32_t build_key; uint32_t hic_id; diff --git a/source/daplink/drag-n-drop/vfs_manager.c b/source/daplink/drag-n-drop/vfs_manager.c index a2941eede..64a90ba94 100644 --- a/source/daplink/drag-n-drop/vfs_manager.c +++ b/source/daplink/drag-n-drop/vfs_manager.c @@ -3,7 +3,7 @@ * @brief Implementation of vfs_manager.h * * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2020 Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -21,7 +21,8 @@ #include -#include "main.h" +#include "daplink.h" +#include DAPLINK_MAIN_HEADER #include "cmsis_os2.h" #include "rl_usb.h" #include "virtual_fs.h" @@ -29,7 +30,6 @@ #include "daplink_debug.h" #include "info.h" #include "settings.h" -#include "daplink.h" #include "util.h" #include "version_git.h" #include "IO_Config.h" diff --git a/source/daplink/info.c b/source/daplink/info.c index 08c2d12d1..c0dd57d25 100644 --- a/source/daplink/info.c +++ b/source/daplink/info.c @@ -3,7 +3,7 @@ * @brief Implementation of info.h * * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2020 Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -20,7 +20,6 @@ */ #include -#include "main.h" #include "info.h" #include "target_config.h" #include "read_uid.h" diff --git a/source/daplink/interface/main.c b/source/daplink/interface/main_interface.c similarity index 99% rename from source/daplink/interface/main.c rename to source/daplink/interface/main_interface.c index d6229e9de..d1743c1ad 100644 --- a/source/daplink/interface/main.c +++ b/source/daplink/interface/main_interface.c @@ -1,9 +1,9 @@ /** - * @file main.c + * @file main_interface.c * @brief Entry point for interface program logic * * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2020 Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -24,7 +24,7 @@ #include "cmsis_os2.h" #include "rl_usb.h" -#include "main.h" +#include "main_interface.h" #include "gpio.h" #include "uart.h" #include "tasks.h" diff --git a/source/daplink/interface/main.h b/source/daplink/interface/main_interface.h similarity index 91% rename from source/daplink/interface/main.h rename to source/daplink/interface/main_interface.h index 665418e43..06d8cdb3d 100644 --- a/source/daplink/interface/main.h +++ b/source/daplink/interface/main_interface.h @@ -1,9 +1,9 @@ /** - * @file main.h + * @file main_interface.h * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2020 Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -19,8 +19,8 @@ * limitations under the License. */ -#ifndef MAIN_H -#define MAIN_H +#ifndef MAIN_INTERFACE_H +#define MAIN_INTERFACE_H #include #include diff --git a/source/daplink/usb2uart/usbd_user_cdc_acm.c b/source/daplink/usb2uart/usbd_user_cdc_acm.c index 1f4e57e23..7201aa044 100644 --- a/source/daplink/usb2uart/usbd_user_cdc_acm.c +++ b/source/daplink/usb2uart/usbd_user_cdc_acm.c @@ -3,7 +3,7 @@ * @brief implementation of USB CDC ACM middleware * * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2020 Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -21,7 +21,8 @@ #include "cmsis_os2.h" #include "rl_usb.h" -#include "main.h" +#include "daplink.h" +#include DAPLINK_MAIN_HEADER #include "uart.h" #ifdef DRAG_N_DROP_SUPPORT #include "flash_intf.h" diff --git a/source/usb/hid/usbd_user_hid.c b/source/usb/hid/usbd_user_hid.c index 2c52fe146..bd2fe107a 100644 --- a/source/usb/hid/usbd_user_hid.c +++ b/source/usb/hid/usbd_user_hid.c @@ -3,7 +3,7 @@ * @brief HID driver for CMSIS-DAP packet processing * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2020 Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -28,7 +28,8 @@ #include "DAP.h" #include "util.h" #include "DAP_queue.h" -#include "main.h" +#include "daplink.h" +#include DAPLINK_MAIN_HEADER #if (USBD_HID_OUTREPORT_MAX_SZ > DAP_PACKET_SIZE) From ecd8ca8edeadca8b2897255941892b1db88aafc3 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Wed, 16 Dec 2020 17:03:15 -0600 Subject: [PATCH 037/617] Corrected spelling of "Arm" in USB vendor name strings. --- source/hic_hal/atmel/sam3u2c/usb_config.c | 2 +- source/hic_hal/freescale/k20dx/usb_config.c | 2 +- source/hic_hal/freescale/k26f/usb_config.c | 2 +- source/hic_hal/freescale/kl26z/usb_config.c | 2 +- source/hic_hal/maxim/max32620/usb_config.c | 2 +- source/hic_hal/maxim/max32625/usb_config.c | 2 +- source/hic_hal/nuvoton/m48ssidae/usb_config.c | 2 +- source/hic_hal/nxp/lpc11u35/usb_config.c | 2 +- source/hic_hal/nxp/lpc4322/usb_config.c | 2 +- source/hic_hal/stm32/stm32f103xb/usb_config.c | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) diff --git a/source/hic_hal/atmel/sam3u2c/usb_config.c b/source/hic_hal/atmel/sam3u2c/usb_config.c index 89a5320df..c748c9adf 100644 --- a/source/hic_hal/atmel/sam3u2c/usb_config.c +++ b/source/hic_hal/atmel/sam3u2c/usb_config.c @@ -86,7 +86,7 @@ // // #define USBD_STRDESC_LANGID 0x0409 -#define USBD_STRDESC_MAN L"ARM" +#define USBD_STRDESC_MAN L"Arm" #ifndef USB_PROD_STR #define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" #else diff --git a/source/hic_hal/freescale/k20dx/usb_config.c b/source/hic_hal/freescale/k20dx/usb_config.c index 5b232ec8e..2f1b37185 100644 --- a/source/hic_hal/freescale/k20dx/usb_config.c +++ b/source/hic_hal/freescale/k20dx/usb_config.c @@ -86,7 +86,7 @@ // // #define USBD_STRDESC_LANGID 0x0409 -#define USBD_STRDESC_MAN L"ARM" +#define USBD_STRDESC_MAN L"Arm" #ifndef USB_PROD_STR #define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" #else diff --git a/source/hic_hal/freescale/k26f/usb_config.c b/source/hic_hal/freescale/k26f/usb_config.c index c2dcd52c1..d30512bba 100644 --- a/source/hic_hal/freescale/k26f/usb_config.c +++ b/source/hic_hal/freescale/k26f/usb_config.c @@ -95,7 +95,7 @@ // // #define USBD_STRDESC_LANGID 0x0409 -#define USBD_STRDESC_MAN L"ARM" +#define USBD_STRDESC_MAN L"Arm" #ifndef USB_PROD_STR #define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" #else diff --git a/source/hic_hal/freescale/kl26z/usb_config.c b/source/hic_hal/freescale/kl26z/usb_config.c index ad35f74d0..a5a325232 100644 --- a/source/hic_hal/freescale/kl26z/usb_config.c +++ b/source/hic_hal/freescale/kl26z/usb_config.c @@ -86,7 +86,7 @@ // // #define USBD_STRDESC_LANGID 0x0409 -#define USBD_STRDESC_MAN L"ARM" +#define USBD_STRDESC_MAN L"Arm" #ifndef USB_PROD_STR #define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" #else diff --git a/source/hic_hal/maxim/max32620/usb_config.c b/source/hic_hal/maxim/max32620/usb_config.c index b9f1a811a..82b8110fe 100644 --- a/source/hic_hal/maxim/max32620/usb_config.c +++ b/source/hic_hal/maxim/max32620/usb_config.c @@ -85,7 +85,7 @@ // // #define USBD_STRDESC_LANGID 0x0409 -#define USBD_STRDESC_MAN L"ARM" +#define USBD_STRDESC_MAN L"Arm" #ifndef USB_PROD_STR #define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" #else diff --git a/source/hic_hal/maxim/max32625/usb_config.c b/source/hic_hal/maxim/max32625/usb_config.c index 44af7e941..190f2f762 100755 --- a/source/hic_hal/maxim/max32625/usb_config.c +++ b/source/hic_hal/maxim/max32625/usb_config.c @@ -85,7 +85,7 @@ // // #define USBD_STRDESC_LANGID 0x0409 -#define USBD_STRDESC_MAN L"ARM" +#define USBD_STRDESC_MAN L"Arm" #ifndef USB_PROD_STR #define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" #else diff --git a/source/hic_hal/nuvoton/m48ssidae/usb_config.c b/source/hic_hal/nuvoton/m48ssidae/usb_config.c index c04d53a3c..5b4b5b92f 100644 --- a/source/hic_hal/nuvoton/m48ssidae/usb_config.c +++ b/source/hic_hal/nuvoton/m48ssidae/usb_config.c @@ -86,7 +86,7 @@ // // #define USBD_STRDESC_LANGID 0x0409 -#define USBD_STRDESC_MAN L"ARM" +#define USBD_STRDESC_MAN L"Arm" #define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" #define USBD_STRDESC_SER_ENABLE 1 #define USBD_STRDESC_SER L"0001A0000000" diff --git a/source/hic_hal/nxp/lpc11u35/usb_config.c b/source/hic_hal/nxp/lpc11u35/usb_config.c index 828b0c761..0153f6de8 100644 --- a/source/hic_hal/nxp/lpc11u35/usb_config.c +++ b/source/hic_hal/nxp/lpc11u35/usb_config.c @@ -86,7 +86,7 @@ // // #define USBD_STRDESC_LANGID 0x0409 -#define USBD_STRDESC_MAN L"ARM" +#define USBD_STRDESC_MAN L"Arm" #ifndef USB_PROD_STR #define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" #else diff --git a/source/hic_hal/nxp/lpc4322/usb_config.c b/source/hic_hal/nxp/lpc4322/usb_config.c index a6886c3b3..04306196f 100644 --- a/source/hic_hal/nxp/lpc4322/usb_config.c +++ b/source/hic_hal/nxp/lpc4322/usb_config.c @@ -86,7 +86,7 @@ // // #define USBD_STRDESC_LANGID 0x0409 -#define USBD_STRDESC_MAN L"ARM" +#define USBD_STRDESC_MAN L"Arm" #ifndef USB_PROD_STR #define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" #else diff --git a/source/hic_hal/stm32/stm32f103xb/usb_config.c b/source/hic_hal/stm32/stm32f103xb/usb_config.c index 646a27810..db2a0bca3 100644 --- a/source/hic_hal/stm32/stm32f103xb/usb_config.c +++ b/source/hic_hal/stm32/stm32f103xb/usb_config.c @@ -86,7 +86,7 @@ // // #define USBD_STRDESC_LANGID 0x0409 -#define USBD_STRDESC_MAN L"ARM" +#define USBD_STRDESC_MAN L"Arm" #define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" #define USBD_STRDESC_SER_ENABLE 1 #define USBD_STRDESC_SER L"0001A0000000" From b170e8d8bfa1adea52154ee68af319ca60a1fbd6 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 21 Dec 2020 16:40:26 -0600 Subject: [PATCH 038/617] Avoid C runtime issue on armclang --- source/daplink/bootloader/main_bootloader.c | 5 +++++ source/daplink/interface/main_interface.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/source/daplink/bootloader/main_bootloader.c b/source/daplink/bootloader/main_bootloader.c index 8879e23ea..c1de1925e 100644 --- a/source/daplink/bootloader/main_bootloader.c +++ b/source/daplink/bootloader/main_bootloader.c @@ -38,6 +38,11 @@ #define MSC_LED_DEF GPIO_LED_ON #endif +/* Avoids the semihosting issue */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +__asm(" .global __ARM_use_no_argv\n"); +#endif + #if defined(__CC_ARM) __asm void modify_stack_pointer_and_start_app(uint32_t r0_sp, uint32_t r1_pc) { diff --git a/source/daplink/interface/main_interface.c b/source/daplink/interface/main_interface.c index d1743c1ad..938d9e3b4 100644 --- a/source/daplink/interface/main_interface.c +++ b/source/daplink/interface/main_interface.c @@ -46,6 +46,11 @@ #include "flash_manager.h" #endif +/* Avoids the semihosting issue */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +__asm(" .global __ARM_use_no_argv\n"); +#endif + // Event flags for main task // Timers events #define FLAGS_MAIN_90MS (1 << 0) From 2a5c4b673c54e25bf546195ead6cb2bbe764fad4 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 5 Dec 2020 17:20:31 -0600 Subject: [PATCH 039/617] Add `progen` equivalent to `mbedcli_compile.py` --- tools/package_release_files.py | 8 +- tools/progen_compile.py | 149 +++++++++++++++++++++++++++++++++ 2 files changed, 155 insertions(+), 2 deletions(-) create mode 100755 tools/progen_compile.py diff --git a/tools/package_release_files.py b/tools/package_release_files.py index 00208ce23..87a51f1e3 100644 --- a/tools/package_release_files.py +++ b/tools/package_release_files.py @@ -57,10 +57,14 @@ def package_release_files(source, dest, version, toolchain, release_info, suppor legacy_str = "_legacy" if legacy else "" source_offset_str = "_0x%04x" % offset if legacy else "" source_name = prj_name + "_crc" + legacy_str + source_offset_str + "." + extension - source_dir_part = os.path.join(proj_dir, prj_name, toolchain).upper() + # The build path hierarchy is different between mbedcli and progen + if toolchain.startswith("projectfiles"): + source_dir_part = os.path.join(toolchain, prj_name, proj_dir) + else: + source_dir_part = os.path.join(proj_dir, prj_name, toolchain).upper() source_path = os.path.join(source_dir_part, source_name) if not os.path.isfile(source_path): - print("Warning %s not added to release" % prj_name) + print("Warning %s not added to release (expected file '%s')" % (prj_name, source_path)) continue items = prj_name.split('_') # "k20dx_frdmk22f_if" -> ("k20dx", "frdmk22f", "if") assert items[-1] == "if", "Unexpected string: %s" % items[2] diff --git a/tools/progen_compile.py b/tools/progen_compile.py new file mode 100755 index 000000000..8313f535f --- /dev/null +++ b/tools/progen_compile.py @@ -0,0 +1,149 @@ +#!/usr/bin/env python +# +# DAPLink Interface Firmware +# Copyright (c) 2009-2020, ARM Limited, All Rights Reserved +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +from package_release_files import package_release_files +from post_build_script import post_build_script +from project_generator import generate +from pre_build_script import generate_version_file +import argparse +import logging +import shutil +import yaml +import sys +import os + +self_path = os.path.abspath(__file__) +tools_dir = os.path.dirname(self_path) +daplink_dir = os.path.dirname(tools_dir) + +PROJECTS_YAML = os.path.join(daplink_dir, "projects.yaml") +VERSION_YAML = os.path.join(daplink_dir, "records", "tools", "version.yaml") + +def load_project_list(path): + project_list = [] + with open(path, 'r') as top_yaml: + try: + topdict = yaml.safe_load(top_yaml) + for dict_key in topdict: + if dict_key == 'projects': + for project in topdict[dict_key]: + project_list.append(project) + break + except yaml.YAMLError as ex: + print("Found yaml parse error", ex) + return project_list + + +def build_projects(file, projects, tool, build=True, clean=False, ignore_errors=True): + generator = generate.Generator(file) + cores = 4 + try: + import multiprocessing + cores = multiprocessing.cpu_count() + except: + pass + + for p_name in projects: + for project in generator.generate(p_name): + failed = False + if hasattr(project, 'workspace_name') and (project.workspace_name is not None): + logger.info("Generating %s for %s in workspace %s", tool, project.name, project.workspace_name) + else: + logger.info("Generating %s for %s", tool, project.name) + if clean: + if project.clean(tool) == -1: + logger.error("Error cleaning project %s", project.name) + failed = True + if not failed and project.generate(tool) == -1: + logger.error("Error generating project %s", project.name) + failed = True + if build and not failed: + if project.build(tool, jobs=cores) == -1: + logger.error("Error building project %s", project.name) + failed = True + if failed and not ignore_errors: + return -1 + +project_list = load_project_list(PROJECTS_YAML) +parser = argparse.ArgumentParser(description='project-generator compile support for DAPLink', + epilog="List of supported projects (%d): %s" % (len(project_list), ", ".join(project_list)), + formatter_class=argparse.RawDescriptionHelpFormatter) +parser.add_argument('projects', help='Selectively compile only the firmware specified otherwise all projects', + nargs='*', type=str, default=[]) +parser.add_argument('--release', dest='release', action='store_true', help='Create a release with the yaml version file') +parser.add_argument('--release-folder', type=str, default='firmware', help='Directory to create and place files in') +parser.add_argument('--toolchain', type=str, default='GCC', help='Toolchain ("GCC" or "ARM", default: %(default)s', + choices=['GCC', 'ARM']) +parser.add_argument('--clean', dest='clean', action='store_true', help='Rebuild or delete build folder before compile') +parser.add_argument('-v', dest='verbosity', action='count', help='Increase verbosity (can be specify multiple times)', default=0) +parser.set_defaults(build=True) +parser.set_defaults(clean=False) +parser.set_defaults(release=False) +args = parser.parse_args() + +toolchain = "make_gcc_arm" if args.toolchain in ['GCC'] else 'make_armcc' +logging_level = logging.DEBUG if args.verbosity >= 2 else (logging.INFO if args.verbosity >= 1 else logging.WARNING) +# logging_level = logging.DEBUG +logging.basicConfig(format="%(asctime)s %(name)020s %(levelname)s\t%(message)s", level=logging_level) +logger = logging.getLogger('progen_build') + +if args.release: + sys.path.append(os.path.join(daplink_dir, "test")) + from info import SUPPORTED_CONFIGURATIONS, PROJECT_RELEASE_INFO + version_git_dir = os.path.join(daplink_dir, "source", "daplink") + generate_version_file(version_git_dir) + +projects = args.projects if len(args.projects) > 0 else project_list +print(projects) +build_projects(PROJECTS_YAML, projects, toolchain, args.build, args.clean) + +if args.release: + id_map = {} + for board_id, family_id, firmware, bootloader, target in SUPPORTED_CONFIGURATIONS: + if firmware in id_map: + id_map[firmware].append((hex(board_id), hex(family_id))) + else: + id_map[firmware] = [(hex(board_id), hex(family_id))] + for project in projects: + output = "projectfiles/%s/%s/build/%s" % (toolchain, project, project) + hex = output + ".hex" + crc = output + "_crc" + post_build_script(hex, crc) + # do a build with board_id and family_id + if project in id_map: + for (boardid, familyid) in id_map[project]: + print(project, boardid, familyid) + post_build_script(hex, crc, boardid, familyid) + +if args.release: + release_version = 0 + with open(VERSION_YAML, 'r') as ver_yaml: + try: + verdict = yaml.safe_load(ver_yaml) + release_version = int(verdict['common']['macros'][0].split('=')[1]) + except yaml.YAMLError as ex: + print("Found yaml parse error", ex) + + release_dir = args.release_folder + "_%04i" % release_version + if os.path.exists(release_dir): + logger.info("Deleting: %s" % release_dir) + shutil.rmtree(release_dir, ignore_errors=True) + logger.info("Releasing directory: %s" % release_dir) + package_release_files("build", release_dir, release_version, "projectfiles/" + toolchain, + PROJECT_RELEASE_INFO, SUPPORTED_CONFIGURATIONS) From f738b56c587945f24fe99902387441eced093b8b Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 5 Dec 2020 18:23:21 -0600 Subject: [PATCH 040/617] Add support for progen to `copy_release_files.py` and run post build scripts even for non-release --- tools/copy_release_files.py | 7 ++++-- tools/progen_compile.py | 46 +++++++++++++++++++++---------------- 2 files changed, 31 insertions(+), 22 deletions(-) diff --git a/tools/copy_release_files.py b/tools/copy_release_files.py index 9a4fef3e3..48f8ad188 100644 --- a/tools/copy_release_files.py +++ b/tools/copy_release_files.py @@ -48,7 +48,9 @@ TOOL_DIR = { 'uvision' : { 'proj_dir': os.path.join('projectfiles', 'uvision') , 'rel_dir' : 'uvision_release', 'build_dir' : 'build' }, - 'mbedcli' : { 'proj_dir': 'BUILD' , 'rel_dir' : 'mbedcli_release', 'build_dir' : 'ARM-CUSTOM_PROFILE' } + 'mbedcli' : { 'proj_dir': 'BUILD' , 'rel_dir' : 'mbedcli_release', 'build_dir' : 'ARM-CUSTOM_PROFILE' }, + 'progen_arm' : { 'proj_dir': 'projectfiles/make_armcc' , 'rel_dir' : 'progen_arm_release', 'build_dir' : 'build' }, + 'progen_gcc' : { 'proj_dir': 'projectfiles/make_gcc_arm' , 'rel_dir' : 'progen_gcc_release', 'build_dir' : 'build' } } def generate_info_files(dir): @@ -95,7 +97,8 @@ def generate_info_files(dir): def main(): """Copy imporant files for the current release""" parser = argparse.ArgumentParser(description='Copy imporant files for the current release') - parser.add_argument('--project-tool', type=str, default='uvision', choices=['uvision', 'mbedcli'], help='Choose from uvision and mbedcli') + parser.add_argument('--project-tool', type=str, default='uvision', choices=['uvision', 'mbedcli', 'progen_arm', 'progen_gcc'], + help='Choose from uvision and mbedcli') args = parser.parse_args() self_path = os.path.abspath(__file__) diff --git a/tools/progen_compile.py b/tools/progen_compile.py index 8313f535f..dab40e510 100755 --- a/tools/progen_compile.py +++ b/tools/progen_compile.py @@ -99,37 +99,43 @@ def build_projects(file, projects, tool, build=True, clean=False, ignore_errors= toolchain = "make_gcc_arm" if args.toolchain in ['GCC'] else 'make_armcc' logging_level = logging.DEBUG if args.verbosity >= 2 else (logging.INFO if args.verbosity >= 1 else logging.WARNING) -# logging_level = logging.DEBUG logging.basicConfig(format="%(asctime)s %(name)020s %(levelname)s\t%(message)s", level=logging_level) logger = logging.getLogger('progen_build') if args.release: - sys.path.append(os.path.join(daplink_dir, "test")) - from info import SUPPORTED_CONFIGURATIONS, PROJECT_RELEASE_INFO + if len(args.projects) > 0: + logger.warning("A release can should only be done on all packages") version_git_dir = os.path.join(daplink_dir, "source", "daplink") generate_version_file(version_git_dir) projects = args.projects if len(args.projects) > 0 else project_list -print(projects) build_projects(PROJECTS_YAML, projects, toolchain, args.build, args.clean) -if args.release: - id_map = {} - for board_id, family_id, firmware, bootloader, target in SUPPORTED_CONFIGURATIONS: - if firmware in id_map: - id_map[firmware].append((hex(board_id), hex(family_id))) - else: - id_map[firmware] = [(hex(board_id), hex(family_id))] - for project in projects: - output = "projectfiles/%s/%s/build/%s" % (toolchain, project, project) - hex = output + ".hex" - crc = output + "_crc" +sys.path.append(os.path.join(daplink_dir, "test")) +from info import SUPPORTED_CONFIGURATIONS, PROJECT_RELEASE_INFO +id_map = {} +for board_id, family_id, firmware, bootloader, target in SUPPORTED_CONFIGURATIONS: + if firmware in id_map: + id_map[firmware].append((hex(board_id), hex(family_id))) + else: + id_map[firmware] = [(hex(board_id), hex(family_id))] +for project in projects: + output = "projectfiles/%s/%s/build/%s" % (toolchain, project, project) + hex = output + ".hex" + crc = output + "_crc" + + # TODO: I think this part is already done as part of the progen build with the call + # to the post_build_script_gcc.sh. Remove the next block if confirmed. + # We use the same check as the shell wrapper guard to run it only if necessary. + if os.path.getmtime(hex) >= os.path.getmtime(crc + '.bin'): + logger.debug("Generating %s" % (crc + '.bin')) post_build_script(hex, crc) - # do a build with board_id and family_id - if project in id_map: - for (boardid, familyid) in id_map[project]: - print(project, boardid, familyid) - post_build_script(hex, crc, boardid, familyid) + + # Do a build with board_id and family_id + if project in id_map: + for (boardid, familyid) in id_map[project]: + logger.debug("Building image for %s (%s, %s)" % (project, boardid, familyid)) + post_build_script(hex, crc, boardid, familyid) if args.release: release_version = 0 From 789bfcebe235dd0d88f9e9862dee4503c6dbb096 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 8 Dec 2020 23:39:02 -0600 Subject: [PATCH 041/617] Improve progen_compile.py --- tools/progen_compile.py | 36 ++++++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/tools/progen_compile.py b/tools/progen_compile.py index dab40e510..6ec648fa2 100755 --- a/tools/progen_compile.py +++ b/tools/progen_compile.py @@ -50,14 +50,16 @@ def load_project_list(path): return project_list -def build_projects(file, projects, tool, build=True, clean=False, ignore_errors=True): +def build_projects(file, projects, tool, build=True, clean=False, parallel=False, ignore_failures=False): generator = generate.Generator(file) - cores = 4 - try: - import multiprocessing - cores = multiprocessing.cpu_count() - except: - pass + cores = 1 + if parallel: + cores = 4 + try: + import multiprocessing + cores = multiprocessing.cpu_count() + except: + pass for p_name in projects: for project in generator.generate(p_name): @@ -77,7 +79,7 @@ def build_projects(file, projects, tool, build=True, clean=False, ignore_errors= if project.build(tool, jobs=cores) == -1: logger.error("Error building project %s", project.name) failed = True - if failed and not ignore_errors: + if failed and not ignore_failures: return -1 project_list = load_project_list(PROJECTS_YAML) @@ -88,16 +90,26 @@ def build_projects(file, projects, tool, build=True, clean=False, ignore_errors= nargs='*', type=str, default=[]) parser.add_argument('--release', dest='release', action='store_true', help='Create a release with the yaml version file') parser.add_argument('--release-folder', type=str, default='firmware', help='Directory to create and place files in') -parser.add_argument('--toolchain', type=str, default='GCC', help='Toolchain ("GCC" or "ARM", default: %(default)s', - choices=['GCC', 'ARM']) +parser.add_argument('--toolchain', type=str, default='GCC', help='Toolchain ("GCC", "ARMCC", "ARMCLANG", default: %(default)s', + choices=['GCC', 'ARMCC', "ARMCLANG"]) parser.add_argument('--clean', dest='clean', action='store_true', help='Rebuild or delete build folder before compile') +parser.add_argument('--ignore-failures', dest='ignore_failures', action='store_true', help='Continue build even in case of failures') +parser.add_argument('--parallel', dest='parallel', action='store_true', help='Build with multiple compilations in parallel') parser.add_argument('-v', dest='verbosity', action='count', help='Increase verbosity (can be specify multiple times)', default=0) parser.set_defaults(build=True) parser.set_defaults(clean=False) +parser.set_defaults(ignore_failures=False) +parser.set_defaults(parallel=False) parser.set_defaults(release=False) args = parser.parse_args() -toolchain = "make_gcc_arm" if args.toolchain in ['GCC'] else 'make_armcc' +toolchains = { + "GCC": "make_gcc_arm", + "ARMCC": "make_armcc", + "ARMCLANG": "make_armclang", +} + +toolchain = toolchains[args.toolchain] if args.toolchain in toolchains.keys() else 'make_gcc_arm' logging_level = logging.DEBUG if args.verbosity >= 2 else (logging.INFO if args.verbosity >= 1 else logging.WARNING) logging.basicConfig(format="%(asctime)s %(name)020s %(levelname)s\t%(message)s", level=logging_level) logger = logging.getLogger('progen_build') @@ -109,7 +121,7 @@ def build_projects(file, projects, tool, build=True, clean=False, ignore_errors= generate_version_file(version_git_dir) projects = args.projects if len(args.projects) > 0 else project_list -build_projects(PROJECTS_YAML, projects, toolchain, args.build, args.clean) +build_projects(PROJECTS_YAML, projects, toolchain, args.build, args.clean, args.parallel, args.ignore_failures) sys.path.append(os.path.join(daplink_dir, "test")) from info import SUPPORTED_CONFIGURATIONS, PROJECT_RELEASE_INFO From 9caebe7787c1647f966a3431702c35dad8801301 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 9 Dec 2020 12:50:09 -0600 Subject: [PATCH 042/617] Extend verbose flag to the build system --- tools/progen_compile.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/tools/progen_compile.py b/tools/progen_compile.py index 6ec648fa2..9c44f88e0 100755 --- a/tools/progen_compile.py +++ b/tools/progen_compile.py @@ -50,7 +50,7 @@ def load_project_list(path): return project_list -def build_projects(file, projects, tool, build=True, clean=False, parallel=False, ignore_failures=False): +def build_projects(file, projects, tool, build=True, clean=False, parallel=False, ignore_failures=False, verbose=False): generator = generate.Generator(file) cores = 1 if parallel: @@ -76,7 +76,7 @@ def build_projects(file, projects, tool, build=True, clean=False, parallel=False logger.error("Error generating project %s", project.name) failed = True if build and not failed: - if project.build(tool, jobs=cores) == -1: + if project.build(tool, jobs=cores, verbose=verbose) == -1: logger.error("Error building project %s", project.name) failed = True if failed and not ignore_failures: @@ -121,7 +121,8 @@ def build_projects(file, projects, tool, build=True, clean=False, parallel=False generate_version_file(version_git_dir) projects = args.projects if len(args.projects) > 0 else project_list -build_projects(PROJECTS_YAML, projects, toolchain, args.build, args.clean, args.parallel, args.ignore_failures) +build_projects(PROJECTS_YAML, projects, toolchain, args.build, args.clean, + args.parallel, args.ignore_failures, args.verbosity > 0) sys.path.append(os.path.join(daplink_dir, "test")) from info import SUPPORTED_CONFIGURATIONS, PROJECT_RELEASE_INFO From 503535798258393e10ca8828a1b0aed31967d12f Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 16 Dec 2020 19:35:38 -0600 Subject: [PATCH 043/617] Better detection and handling of build failures --- tools/progen_compile.py | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/tools/progen_compile.py b/tools/progen_compile.py index 9c44f88e0..874f602a1 100755 --- a/tools/progen_compile.py +++ b/tools/progen_compile.py @@ -137,10 +137,19 @@ def build_projects(file, projects, tool, build=True, clean=False, parallel=False hex = output + ".hex" crc = output + "_crc" + if not os.path.exists(hex): + # Build failed + if args.ignore_failures: + logger.warnig("Missing file %s (build failed)" % (hex)) + continue + else: + logger.error("Missing file %s (build failed)" % (hex)) + exit(-1) + # TODO: I think this part is already done as part of the progen build with the call # to the post_build_script_gcc.sh. Remove the next block if confirmed. # We use the same check as the shell wrapper guard to run it only if necessary. - if os.path.getmtime(hex) >= os.path.getmtime(crc + '.bin'): + if not os.path.exists(crc + '.bin') or os.path.getmtime(hex) >= os.path.getmtime(crc + '.bin'): logger.debug("Generating %s" % (crc + '.bin')) post_build_script(hex, crc) From 62eb3a4120ff5c9c243d6581f670f25bec78644a Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 17 Dec 2020 22:33:19 -0600 Subject: [PATCH 044/617] Use progen toolchain identifiers in progen_compile.py --- tools/progen_compile.py | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) diff --git a/tools/progen_compile.py b/tools/progen_compile.py index 874f602a1..513e94f9a 100755 --- a/tools/progen_compile.py +++ b/tools/progen_compile.py @@ -54,11 +54,11 @@ def build_projects(file, projects, tool, build=True, clean=False, parallel=False generator = generate.Generator(file) cores = 1 if parallel: - cores = 4 try: import multiprocessing cores = multiprocessing.cpu_count() except: + cores = 4 pass for p_name in projects: @@ -90,8 +90,7 @@ def build_projects(file, projects, tool, build=True, clean=False, parallel=False nargs='*', type=str, default=[]) parser.add_argument('--release', dest='release', action='store_true', help='Create a release with the yaml version file') parser.add_argument('--release-folder', type=str, default='firmware', help='Directory to create and place files in') -parser.add_argument('--toolchain', type=str, default='GCC', help='Toolchain ("GCC", "ARMCC", "ARMCLANG", default: %(default)s', - choices=['GCC', 'ARMCC', "ARMCLANG"]) +parser.add_argument('--toolchain', '-t', type=str, help='Toolchain (default: make_gcc_arm)') parser.add_argument('--clean', dest='clean', action='store_true', help='Rebuild or delete build folder before compile') parser.add_argument('--ignore-failures', dest='ignore_failures', action='store_true', help='Continue build even in case of failures') parser.add_argument('--parallel', dest='parallel', action='store_true', help='Build with multiple compilations in parallel') @@ -103,13 +102,15 @@ def build_projects(file, projects, tool, build=True, clean=False, parallel=False parser.set_defaults(release=False) args = parser.parse_args() -toolchains = { - "GCC": "make_gcc_arm", - "ARMCC": "make_armcc", - "ARMCLANG": "make_armclang", -} -toolchain = toolchains[args.toolchain] if args.toolchain in toolchains.keys() else 'make_gcc_arm' +toolchains = ["make_gcc_arm", "make_armcc", "make_armclang", # Make options + "cmake_gcc_arm", "cmake_armclang", # CMake options + "gcc_arm", "armcc", "armclang"] # Aliases for the make options +toolchain = args.toolchain if args.toolchain else 'make_gcc_arm' +if toolchain not in toolchains: + print("Unsupported toolchain '%s' (options: %s)\n" % (toolchain, ", ".join(toolchains))) + exit(-1) + logging_level = logging.DEBUG if args.verbosity >= 2 else (logging.INFO if args.verbosity >= 1 else logging.WARNING) logging.basicConfig(format="%(asctime)s %(name)020s %(levelname)s\t%(message)s", level=logging_level) logger = logging.getLogger('progen_build') @@ -146,13 +147,6 @@ def build_projects(file, projects, tool, build=True, clean=False, parallel=False logger.error("Missing file %s (build failed)" % (hex)) exit(-1) - # TODO: I think this part is already done as part of the progen build with the call - # to the post_build_script_gcc.sh. Remove the next block if confirmed. - # We use the same check as the shell wrapper guard to run it only if necessary. - if not os.path.exists(crc + '.bin') or os.path.getmtime(hex) >= os.path.getmtime(crc + '.bin'): - logger.debug("Generating %s" % (crc + '.bin')) - post_build_script(hex, crc) - # Do a build with board_id and family_id if project in id_map: for (boardid, familyid) in id_map[project]: From da8b7fa13f91d71e0460a85eecd06582302c44ae Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Thu, 24 Dec 2020 15:47:56 -0600 Subject: [PATCH 045/617] Remove unused CRC16, make default CRC32 weak. --- source/daplink/crc.h | 1 - source/daplink/crc16.c | 144 ----------------------------------------- source/daplink/crc32.c | 5 +- 3 files changed, 3 insertions(+), 147 deletions(-) delete mode 100644 source/daplink/crc16.c diff --git a/source/daplink/crc.h b/source/daplink/crc.h index dafb5ae6c..e9d8b8efc 100644 --- a/source/daplink/crc.h +++ b/source/daplink/crc.h @@ -27,7 +27,6 @@ extern "C" { #endif -uint16_t crc16(const void *data, int nBytes); uint32_t crc32(const void *data, int nBytes); uint32_t crc32_continue(uint32_t prev_crc, const void *data, int nBytes); diff --git a/source/daplink/crc16.c b/source/daplink/crc16.c deleted file mode 100644 index 10afc7c0a..000000000 --- a/source/daplink/crc16.c +++ /dev/null @@ -1,144 +0,0 @@ -/********************************************************************** - * - * Filename: crc.c - * - * Description: Slow and fast implementations of the CRC standards. - * - * Notes: The parameters for each supported CRC standard are - * defined in the header file crc.h. The implementations - * here should stand up to further additions to that list. - * - * - * Copyright (c) 2000 by Michael Barr. This software is placed into - * the public domain and may be used for any purpose. However, this - * notice must not be changed or removed and no warranty is either - * expressed or implied by its publication or distribution. - **********************************************************************/ - -/** - * @file crc16.c - * @brief Implementation of crc.h - */ - -#include "crc.h" - -#define FALSE 0 -#define TRUE !FALSE - -typedef unsigned short crc; - -#define CRC_NAME "CRC-16" -#define POLYNOMIAL 0x8005 -#define INITIAL_REMAINDER 0x0000 -#define FINAL_XOR_VALUE 0x0000 -#define REFLECT_DATA TRUE -#define REFLECT_REMAINDER TRUE -#define CHECK_VALUE 0xBB3D - -/* - * Derive parameters from the standard-specific parameters in crc.h. - */ -#define WIDTH (8 * sizeof(crc)) -#define TOPBIT (1 << (WIDTH - 1)) - -#if (REFLECT_DATA == TRUE) -#undef REFLECT_DATA -#define REFLECT_DATA(X) ((unsigned char) reflect((X), 8)) -#else -#undef REFLECT_DATA -#define REFLECT_DATA(X) (X) -#endif - -#if (REFLECT_REMAINDER == TRUE) -#undef REFLECT_REMAINDER -#define REFLECT_REMAINDER(X) ((crc) reflect((X), WIDTH)) -#else -#undef REFLECT_REMAINDER -#define REFLECT_REMAINDER(X) (X) -#endif - - -/********************************************************************* - * - * Function: reflect() - * - * Description: Reorder the bits of a binary sequence, by reflecting - * them about the middle position. - * - * Notes: No checking is done that nBits <= 32. - * - * Returns: The reflection of the original data. - * - *********************************************************************/ -static unsigned long -reflect(unsigned long data, unsigned char nBits) -{ - unsigned long reflection = 0x00000000; - unsigned char bit; - - /* - * Reflect the data about the center bit. - */ - for (bit = 0; bit < nBits; ++bit) { - /* - * If the LSB bit is set, set the reflection of it. - */ - if (data & 0x01) { - reflection |= (1 << ((nBits - 1) - bit)); - } - - data = (data >> 1); - } - - return (reflection); -} /* reflect() */ - - -/********************************************************************* - * - * Function: crcSlow() - * - * Description: Compute the CRC of a given message. - * - * Notes: - * - * Returns: The CRC of the message. - * - *********************************************************************/ -uint16_t -crc16(const void *data, int nBytes) -{ - crc remainder = INITIAL_REMAINDER; - int byte; - unsigned char bit; - unsigned char const *message = data; - - /* - * Perform modulo-2 division, a byte at a time. - */ - for (byte = 0; byte < nBytes; ++byte) { - /* - * Bring the next byte into the remainder. - */ - remainder ^= (REFLECT_DATA(message[byte]) << (WIDTH - 8)); - - /* - * Perform modulo-2 division, a bit at a time. - */ - for (bit = 8; bit > 0; --bit) { - /* - * Try to divide the current data bit. - */ - if (remainder & TOPBIT) { - remainder = (remainder << 1) ^ POLYNOMIAL; - } else { - remainder = (remainder << 1); - } - } - } - - /* - * The final remainder is the CRC result. - */ - return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE); -} /* crcSlow() */ diff --git a/source/daplink/crc32.c b/source/daplink/crc32.c index a4fd5973d..ab1e5a401 100644 --- a/source/daplink/crc32.c +++ b/source/daplink/crc32.c @@ -21,6 +21,7 @@ */ #include "crc.h" +#include "compiler.h" #define FALSE 0 #define TRUE !FALSE @@ -105,7 +106,7 @@ reflect(unsigned long data, unsigned char nBits) * Returns: The CRC of the message. * *********************************************************************/ -uint32_t +__WEAK uint32_t crc32(const void *data, int nBytes) { crc remainder = INITIAL_REMAINDER; @@ -154,7 +155,7 @@ crc32(const void *data, int nBytes) * Returns: The CRC of the message. * *********************************************************************/ -uint32_t +__WEAK uint32_t crc32_continue(uint32_t prev_crc, const void *data, int nBytes) { crc remainder = REFLECT_REMAINDER(prev_crc ^ FINAL_XOR_VALUE); From fa688ec6b2ae244e7977938a93e38a5e32a1aaab Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 2 Jan 2021 22:02:49 -0600 Subject: [PATCH 046/617] Default CRC32 uses __RBIT intrinsic for bit reversal. --- source/daplink/crc32.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/source/daplink/crc32.c b/source/daplink/crc32.c index ab1e5a401..24f7bfd11 100644 --- a/source/daplink/crc32.c +++ b/source/daplink/crc32.c @@ -22,6 +22,7 @@ #include "crc.h" #include "compiler.h" +#include "util.h" #define FALSE 0 #define TRUE !FALSE @@ -74,6 +75,13 @@ typedef unsigned long crc; static unsigned long reflect(unsigned long data, unsigned char nBits) { + // util_assert(nBits <= 32); + if (nBits == 32) { + // Use bit reverse instruction intrinsic. The CMSIS intrinsic also + // provides an implementation for cores that don't have the instruction. + return __RBIT(data); + } + unsigned long reflection = 0x00000000; unsigned char bit; From 9ff4c9014e044f2e95c20134a160b9dcd71b2430 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 24 Dec 2020 00:22:20 -0600 Subject: [PATCH 047/617] Import CMSIS RTOS2 for armclang and GCC --- records/rtos/rtos-cm0.yaml | 102 +- records/rtos/rtos-cm3.yaml | 102 +- records/rtos/rtos-cm4.yaml | 104 +- source/daplink/RTE_Components.h | 22 + source/daplink/bootloader/SVC_Table.s | 38 - .../interface => rtos/ARM}/SVC_Table.s | 0 source/rtos2/Include/cmsis_os2.h | 756 ++++++ source/rtos2/Include/os_tick.h | 71 + source/rtos2/RTX/Config/RTX_Config.c | 64 + source/rtos2/RTX/Config/RTX_Config.h | 580 +++++ source/rtos2/RTX/Config/handlers.c | 158 ++ source/rtos2/RTX/Include/rtx_evr.h | 1974 +++++++++++++++ source/rtos2/RTX/Include/rtx_os.h | 472 ++++ source/rtos2/RTX/Source/ARM/irq_armv8mbl.s | 335 +++ source/rtos2/RTX/Source/ARM/irq_armv8mbl_ns.s | 3 + source/rtos2/RTX/Source/ARM/irq_armv8mml.s | 308 +++ source/rtos2/RTX/Source/ARM/irq_armv8mml_ns.s | 3 + source/rtos2/RTX/Source/ARM/irq_cm0.s | 174 ++ source/rtos2/RTX/Source/ARM/irq_cm3.s | 146 ++ source/rtos2/RTX/Source/ARM/irq_cm4f.s | 162 ++ source/rtos2/RTX/Source/GCC/irq_armv8mbl.S | 325 +++ source/rtos2/RTX/Source/GCC/irq_armv8mml.S | 304 +++ source/rtos2/RTX/Source/GCC/irq_cm0.S | 172 ++ source/rtos2/RTX/Source/GCC/irq_cm3.S | 143 ++ source/rtos2/RTX/Source/GCC/irq_cm4f.S | 160 ++ source/rtos2/RTX/Source/rtx_core_c.h | 49 + source/rtos2/RTX/Source/rtx_core_cm.h | 1215 ++++++++++ source/rtos2/RTX/Source/rtx_delay.c | 101 + source/rtos2/RTX/Source/rtx_evflags.c | 582 +++++ source/rtos2/RTX/Source/rtx_evr.c | 2114 +++++++++++++++++ source/rtos2/RTX/Source/rtx_kernel.c | 680 ++++++ source/rtos2/RTX/Source/rtx_lib.c | 773 ++++++ source/rtos2/RTX/Source/rtx_lib.h | 218 ++ source/rtos2/RTX/Source/rtx_memory.c | 218 ++ source/rtos2/RTX/Source/rtx_mempool.c | 705 ++++++ source/rtos2/RTX/Source/rtx_msgqueue.c | 948 ++++++++ source/rtos2/RTX/Source/rtx_mutex.c | 570 +++++ source/rtos2/RTX/Source/rtx_semaphore.c | 507 ++++ source/rtos2/RTX/Source/rtx_system.c | 213 ++ source/rtos2/RTX/Source/rtx_thread.c | 1901 +++++++++++++++ source/rtos2/RTX/Source/rtx_timer.c | 459 ++++ source/rtos2/Source/os_systick.c | 133 ++ 42 files changed, 17972 insertions(+), 92 deletions(-) create mode 100644 source/daplink/RTE_Components.h delete mode 100644 source/daplink/bootloader/SVC_Table.s rename source/{daplink/interface => rtos/ARM}/SVC_Table.s (100%) create mode 100644 source/rtos2/Include/cmsis_os2.h create mode 100644 source/rtos2/Include/os_tick.h create mode 100644 source/rtos2/RTX/Config/RTX_Config.c create mode 100644 source/rtos2/RTX/Config/RTX_Config.h create mode 100644 source/rtos2/RTX/Config/handlers.c create mode 100644 source/rtos2/RTX/Include/rtx_evr.h create mode 100644 source/rtos2/RTX/Include/rtx_os.h create mode 100644 source/rtos2/RTX/Source/ARM/irq_armv8mbl.s create mode 100644 source/rtos2/RTX/Source/ARM/irq_armv8mbl_ns.s create mode 100644 source/rtos2/RTX/Source/ARM/irq_armv8mml.s create mode 100644 source/rtos2/RTX/Source/ARM/irq_armv8mml_ns.s create mode 100644 source/rtos2/RTX/Source/ARM/irq_cm0.s create mode 100644 source/rtos2/RTX/Source/ARM/irq_cm3.s create mode 100644 source/rtos2/RTX/Source/ARM/irq_cm4f.s create mode 100644 source/rtos2/RTX/Source/GCC/irq_armv8mbl.S create mode 100644 source/rtos2/RTX/Source/GCC/irq_armv8mml.S create mode 100644 source/rtos2/RTX/Source/GCC/irq_cm0.S create mode 100644 source/rtos2/RTX/Source/GCC/irq_cm3.S create mode 100644 source/rtos2/RTX/Source/GCC/irq_cm4f.S create mode 100644 source/rtos2/RTX/Source/rtx_core_c.h create mode 100644 source/rtos2/RTX/Source/rtx_core_cm.h create mode 100644 source/rtos2/RTX/Source/rtx_delay.c create mode 100644 source/rtos2/RTX/Source/rtx_evflags.c create mode 100644 source/rtos2/RTX/Source/rtx_evr.c create mode 100644 source/rtos2/RTX/Source/rtx_kernel.c create mode 100644 source/rtos2/RTX/Source/rtx_lib.c create mode 100644 source/rtos2/RTX/Source/rtx_lib.h create mode 100644 source/rtos2/RTX/Source/rtx_memory.c create mode 100644 source/rtos2/RTX/Source/rtx_mempool.c create mode 100644 source/rtos2/RTX/Source/rtx_msgqueue.c create mode 100644 source/rtos2/RTX/Source/rtx_mutex.c create mode 100644 source/rtos2/RTX/Source/rtx_semaphore.c create mode 100644 source/rtos2/RTX/Source/rtx_system.c create mode 100644 source/rtos2/RTX/Source/rtx_thread.c create mode 100644 source/rtos2/RTX/Source/rtx_timer.c create mode 100644 source/rtos2/Source/os_systick.c diff --git a/records/rtos/rtos-cm0.yaml b/records/rtos/rtos-cm0.yaml index 79b3174f2..2dc842d2e 100644 --- a/records/rtos/rtos-cm0.yaml +++ b/records/rtos/rtos-cm0.yaml @@ -1,21 +1,87 @@ common: macros: - OS_TICK=10000 - includes: - - source/rtos - sources: - rtos: - - source/rtos/cm0 - - source/rtos/rt_Event.c - - source/rtos/rt_List.c - - source/rtos/rt_Mailbox.c - - source/rtos/rt_MemBox.c - - source/rtos/rt_Mutex.c - - source/rtos/rt_Robin.c - - source/rtos/rt_Semaphore.c - - source/rtos/rt_System.c - - source/rtos/rt_Task.c - - source/rtos/rt_Time.c - - source/rtos/rt_Timer.c - - source/rtos/RTX_Config.c - - source/rtos/cmsis_os2_port.c + - __ARM_ARCH_6M__=1 +tool_specific: + uvision: + includes: + - source/rtos + sources: + rtos: + - source/rtos/cm0 + - source/rtos/ARM/SVC_Table.s + - source/rtos/rt_Event.c + - source/rtos/rt_List.c + - source/rtos/rt_Mailbox.c + - source/rtos/rt_MemBox.c + - source/rtos/rt_Mutex.c + - source/rtos/rt_Robin.c + - source/rtos/rt_Semaphore.c + - source/rtos/rt_System.c + - source/rtos/rt_Task.c + - source/rtos/rt_Time.c + - source/rtos/rt_Timer.c + - source/rtos/RTX_Config.c + - source/rtos/cmsis_os2_port.c + make_armcc: + includes: + - source/rtos + sources: + rtos: + - source/rtos/cm0 + - source/rtos/ARM/SVC_Table.s + - source/rtos/rt_Event.c + - source/rtos/rt_List.c + - source/rtos/rt_Mailbox.c + - source/rtos/rt_MemBox.c + - source/rtos/rt_Mutex.c + - source/rtos/rt_Robin.c + - source/rtos/rt_Semaphore.c + - source/rtos/rt_System.c + - source/rtos/rt_Task.c + - source/rtos/rt_Time.c + - source/rtos/rt_Timer.c + - source/rtos/RTX_Config.c + - source/rtos/cmsis_os2_port.c + make_armclang: + includes: + - source/rtos2/Include + - source/rtos2/RTX/Include + - source/rtos2/RTX/Config + sources: + rtos: + - source/rtos2/RTX/Source/ARM/irq_cm0.s + - source/rtos2/RTX/Config/RTX_Config.c + - source/rtos2/RTX/Source/rtx_delay.c + - source/rtos2/RTX/Source/rtx_evr.c + - source/rtos2/RTX/Source/rtx_kernel.c + - source/rtos2/RTX/Source/rtx_lib.c + - source/rtos2/RTX/Source/rtx_memory.c + - source/rtos2/RTX/Source/rtx_mempool.c + - source/rtos2/RTX/Source/rtx_msgqueue.c + - source/rtos2/RTX/Source/rtx_mutex.c + - source/rtos2/RTX/Source/rtx_system.c + - source/rtos2/RTX/Source/rtx_thread.c + - source/rtos2/RTX/Source/rtx_timer.c + - source/rtos2/Source/os_systick.c + make_gcc_arm: + includes: + - source/rtos2/Include + - source/rtos2/RTX/Include + - source/rtos2/RTX/Config + sources: + rtos: + - source/rtos2/RTX/Source/GCC/irq_cm0.S + - source/rtos2/RTX/Config/RTX_Config.c + - source/rtos2/RTX/Source/rtx_delay.c + - source/rtos2/RTX/Source/rtx_evr.c + - source/rtos2/RTX/Source/rtx_kernel.c + - source/rtos2/RTX/Source/rtx_lib.c + - source/rtos2/RTX/Source/rtx_memory.c + - source/rtos2/RTX/Source/rtx_mempool.c + - source/rtos2/RTX/Source/rtx_msgqueue.c + - source/rtos2/RTX/Source/rtx_mutex.c + - source/rtos2/RTX/Source/rtx_system.c + - source/rtos2/RTX/Source/rtx_thread.c + - source/rtos2/RTX/Source/rtx_timer.c + - source/rtos2/Source/os_systick.c diff --git a/records/rtos/rtos-cm3.yaml b/records/rtos/rtos-cm3.yaml index 161f032db..cdf16e7fa 100644 --- a/records/rtos/rtos-cm3.yaml +++ b/records/rtos/rtos-cm3.yaml @@ -1,21 +1,87 @@ common: macros: - OS_TICK=10000 - includes: - - source/rtos - sources: - rtos: - - source/rtos/cm3 - - source/rtos/rt_Event.c - - source/rtos/rt_List.c - - source/rtos/rt_Mailbox.c - - source/rtos/rt_MemBox.c - - source/rtos/rt_Mutex.c - - source/rtos/rt_Robin.c - - source/rtos/rt_Semaphore.c - - source/rtos/rt_System.c - - source/rtos/rt_Task.c - - source/rtos/rt_Time.c - - source/rtos/rt_Timer.c - - source/rtos/RTX_Config.c - - source/rtos/cmsis_os2_port.c + +tool_specific: + uvision: + includes: + - source/rtos + sources: + rtos: + - source/rtos/cm3 + - source/rtos/ARM/SVC_Table.s + - source/rtos/rt_Event.c + - source/rtos/rt_List.c + - source/rtos/rt_Mailbox.c + - source/rtos/rt_MemBox.c + - source/rtos/rt_Mutex.c + - source/rtos/rt_Robin.c + - source/rtos/rt_Semaphore.c + - source/rtos/rt_System.c + - source/rtos/rt_Task.c + - source/rtos/rt_Time.c + - source/rtos/rt_Timer.c + - source/rtos/RTX_Config.c + - source/rtos/cmsis_os2_port.c + make_armcc: + includes: + - source/rtos + sources: + rtos: + - source/rtos/cm3 + - source/rtos/ARM/SVC_Table.s + - source/rtos/rt_Event.c + - source/rtos/rt_List.c + - source/rtos/rt_Mailbox.c + - source/rtos/rt_MemBox.c + - source/rtos/rt_Mutex.c + - source/rtos/rt_Robin.c + - source/rtos/rt_Semaphore.c + - source/rtos/rt_System.c + - source/rtos/rt_Task.c + - source/rtos/rt_Time.c + - source/rtos/rt_Timer.c + - source/rtos/RTX_Config.c + - source/rtos/cmsis_os2_port.c + make_armclang: + includes: + - source/rtos2/Include + - source/rtos2/RTX/Include + - source/rtos2/RTX/Config + sources: + rtos: + - source/rtos2/RTX/Source/ARM/irq_cm3.s + - source/rtos2/RTX/Config/RTX_Config.c + - source/rtos2/RTX/Source/rtx_delay.c + - source/rtos2/RTX/Source/rtx_evr.c + - source/rtos2/RTX/Source/rtx_kernel.c + - source/rtos2/RTX/Source/rtx_lib.c + - source/rtos2/RTX/Source/rtx_memory.c + - source/rtos2/RTX/Source/rtx_mempool.c + - source/rtos2/RTX/Source/rtx_msgqueue.c + - source/rtos2/RTX/Source/rtx_mutex.c + - source/rtos2/RTX/Source/rtx_system.c + - source/rtos2/RTX/Source/rtx_thread.c + - source/rtos2/RTX/Source/rtx_timer.c + - source/rtos2/Source/os_systick.c + make_gcc_arm: + includes: + - source/rtos2/Include + - source/rtos2/RTX/Include + - source/rtos2/RTX/Config + sources: + rtos: + - source/rtos2/RTX/Source/GCC/irq_cm3.S + - source/rtos2/RTX/Config/RTX_Config.c + - source/rtos2/RTX/Source/rtx_delay.c + - source/rtos2/RTX/Source/rtx_evr.c + - source/rtos2/RTX/Source/rtx_kernel.c + - source/rtos2/RTX/Source/rtx_lib.c + - source/rtos2/RTX/Source/rtx_memory.c + - source/rtos2/RTX/Source/rtx_mempool.c + - source/rtos2/RTX/Source/rtx_msgqueue.c + - source/rtos2/RTX/Source/rtx_mutex.c + - source/rtos2/RTX/Source/rtx_system.c + - source/rtos2/RTX/Source/rtx_thread.c + - source/rtos2/RTX/Source/rtx_timer.c + - source/rtos2/Source/os_systick.c diff --git a/records/rtos/rtos-cm4.yaml b/records/rtos/rtos-cm4.yaml index 7e231c5cc..78b83e026 100644 --- a/records/rtos/rtos-cm4.yaml +++ b/records/rtos/rtos-cm4.yaml @@ -1,21 +1,89 @@ common: macros: - OS_TICK=10000 - includes: - - source/rtos - sources: - rtos: - - source/rtos/cm4 - - source/rtos/rt_Event.c - - source/rtos/rt_List.c - - source/rtos/rt_Mailbox.c - - source/rtos/rt_MemBox.c - - source/rtos/rt_Mutex.c - - source/rtos/rt_Robin.c - - source/rtos/rt_Semaphore.c - - source/rtos/rt_System.c - - source/rtos/rt_Task.c - - source/rtos/rt_Time.c - - source/rtos/rt_Timer.c - - source/rtos/RTX_Config.c - - source/rtos/cmsis_os2_port.c + +# Use irq_cm3 instead of irq_cm4f because DAPLink doesn't use float, +# and the k20dx doesn't have the FP extension. +tool_specific: + uvision: + includes: + - source/rtos + sources: + rtos: + - source/rtos/cm3 + - source/rtos/ARM/SVC_Table.s + - source/rtos/rt_Event.c + - source/rtos/rt_List.c + - source/rtos/rt_Mailbox.c + - source/rtos/rt_MemBox.c + - source/rtos/rt_Mutex.c + - source/rtos/rt_Robin.c + - source/rtos/rt_Semaphore.c + - source/rtos/rt_System.c + - source/rtos/rt_Task.c + - source/rtos/rt_Time.c + - source/rtos/rt_Timer.c + - source/rtos/RTX_Config.c + - source/rtos/cmsis_os2_port.c + make_armcc: + includes: + - source/rtos + sources: + rtos: + - source/rtos/cm3 + - source/rtos/ARM/SVC_Table.s + - source/rtos/rt_Event.c + - source/rtos/rt_List.c + - source/rtos/rt_Mailbox.c + - source/rtos/rt_MemBox.c + - source/rtos/rt_Mutex.c + - source/rtos/rt_Robin.c + - source/rtos/rt_Semaphore.c + - source/rtos/rt_System.c + - source/rtos/rt_Task.c + - source/rtos/rt_Time.c + - source/rtos/rt_Timer.c + - source/rtos/RTX_Config.c + - source/rtos/cmsis_os2_port.c + make_armclang: + includes: + - source/rtos2/Include + - source/rtos2/RTX/Include + - source/rtos2/RTX/Config + sources: + rtos: + - source/rtos2/RTX/Source/ARM/irq_cm3.s + - source/rtos2/RTX/Config/RTX_Config.c + - source/rtos2/RTX/Source/rtx_delay.c + - source/rtos2/RTX/Source/rtx_evr.c + - source/rtos2/RTX/Source/rtx_kernel.c + - source/rtos2/RTX/Source/rtx_lib.c + - source/rtos2/RTX/Source/rtx_memory.c + - source/rtos2/RTX/Source/rtx_mempool.c + - source/rtos2/RTX/Source/rtx_msgqueue.c + - source/rtos2/RTX/Source/rtx_mutex.c + - source/rtos2/RTX/Source/rtx_system.c + - source/rtos2/RTX/Source/rtx_thread.c + - source/rtos2/RTX/Source/rtx_timer.c + - source/rtos2/Source/os_systick.c + make_gcc_arm: + includes: + - source/rtos2/Include + - source/rtos2/RTX/Include + - source/rtos2/RTX/Config + sources: + rtos: + - source/rtos2/RTX/Source/GCC/irq_cm3.S + - source/rtos2/RTX/Config/RTX_Config.c + - source/rtos2/RTX/Source/rtx_delay.c + - source/rtos2/RTX/Source/rtx_evr.c + - source/rtos2/RTX/Source/rtx_kernel.c + - source/rtos2/RTX/Source/rtx_lib.c + - source/rtos2/RTX/Source/rtx_memory.c + - source/rtos2/RTX/Source/rtx_mempool.c + - source/rtos2/RTX/Source/rtx_msgqueue.c + - source/rtos2/RTX/Source/rtx_mutex.c + - source/rtos2/RTX/Source/rtx_system.c + - source/rtos2/RTX/Source/rtx_thread.c + - source/rtos2/RTX/Source/rtx_timer.c + - source/rtos2/Source/os_systick.c diff --git a/source/daplink/RTE_Components.h b/source/daplink/RTE_Components.h new file mode 100644 index 000000000..a34cb1118 --- /dev/null +++ b/source/daplink/RTE_Components.h @@ -0,0 +1,22 @@ +/* DAPLink Interface Firmware + * Copyright (c) 2020, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + +#define CMSIS_device_header + +#endif diff --git a/source/daplink/bootloader/SVC_Table.s b/source/daplink/bootloader/SVC_Table.s deleted file mode 100644 index 0d0171037..000000000 --- a/source/daplink/bootloader/SVC_Table.s +++ /dev/null @@ -1,38 +0,0 @@ -;/** -; * @file SVC_Table.s -; * @brief SVC functions -; * -; * DAPLink Interface Firmware -; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the "License"); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - - AREA SVC_TABLE, CODE, READONLY - - EXPORT SVC_Count - -SVC_Cnt EQU (SVC_End-SVC_Table)/4 -SVC_Count DCD SVC_Cnt - -; Import user SVC functions here. - - - EXPORT SVC_Table -SVC_Table -; Insert user SVC functions here. SVC 0 used by RTL Kernel. - -SVC_End - - END diff --git a/source/daplink/interface/SVC_Table.s b/source/rtos/ARM/SVC_Table.s similarity index 100% rename from source/daplink/interface/SVC_Table.s rename to source/rtos/ARM/SVC_Table.s diff --git a/source/rtos2/Include/cmsis_os2.h b/source/rtos2/Include/cmsis_os2.h new file mode 100644 index 000000000..76612e292 --- /dev/null +++ b/source/rtos2/Include/cmsis_os2.h @@ -0,0 +1,756 @@ +/* + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 12. June 2020 + * $Revision: V2.1.3 + * + * Project: CMSIS-RTOS2 API + * Title: cmsis_os2.h header file + * + * Version 2.1.3 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osThreadGetId + * Version 2.1.2 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetInfo, osKernelGetState + * Version 2.1.1 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetTickCount, osKernelGetTickFreq + * Changed Kernel Tick type to uint32_t: + * - updated: osKernelGetTickCount, osDelayUntil + * Version 2.1.0 + * Support for critical and uncritical sections (nesting safe): + * - updated: osKernelLock, osKernelUnlock + * - added: osKernelRestoreLock + * Updated Thread and Event Flags: + * - changed flags parameter and return type from int32_t to uint32_t + * Version 2.0.0 + * Initial Release + *---------------------------------------------------------------------------*/ + +#ifndef CMSIS_OS2_H_ +#define CMSIS_OS2_H_ + +#ifndef __NO_RETURN +#if defined(__CC_ARM) +#define __NO_RETURN __declspec(noreturn) +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __NO_RETURN __attribute__((__noreturn__)) +#elif defined(__GNUC__) +#define __NO_RETURN __attribute__((__noreturn__)) +#elif defined(__ICCARM__) +#define __NO_RETURN __noreturn +#else +#define __NO_RETURN +#endif +#endif + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumerations, structures, defines ==== + +/// Version information. +typedef struct { + uint32_t api; ///< API version (major.minor.rev: mmnnnrrrr dec). + uint32_t kernel; ///< Kernel version (major.minor.rev: mmnnnrrrr dec). +} osVersion_t; + +/// Kernel state. +typedef enum { + osKernelInactive = 0, ///< Inactive. + osKernelReady = 1, ///< Ready. + osKernelRunning = 2, ///< Running. + osKernelLocked = 3, ///< Locked. + osKernelSuspended = 4, ///< Suspended. + osKernelError = -1, ///< Error. + osKernelReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osKernelState_t; + +/// Thread state. +typedef enum { + osThreadInactive = 0, ///< Inactive. + osThreadReady = 1, ///< Ready. + osThreadRunning = 2, ///< Running. + osThreadBlocked = 3, ///< Blocked. + osThreadTerminated = 4, ///< Terminated. + osThreadError = -1, ///< Error. + osThreadReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osThreadState_t; + +/// Priority values. +typedef enum { + osPriorityNone = 0, ///< No priority (not initialized). + osPriorityIdle = 1, ///< Reserved for Idle thread. + osPriorityLow = 8, ///< Priority: low + osPriorityLow1 = 8+1, ///< Priority: low + 1 + osPriorityLow2 = 8+2, ///< Priority: low + 2 + osPriorityLow3 = 8+3, ///< Priority: low + 3 + osPriorityLow4 = 8+4, ///< Priority: low + 4 + osPriorityLow5 = 8+5, ///< Priority: low + 5 + osPriorityLow6 = 8+6, ///< Priority: low + 6 + osPriorityLow7 = 8+7, ///< Priority: low + 7 + osPriorityBelowNormal = 16, ///< Priority: below normal + osPriorityBelowNormal1 = 16+1, ///< Priority: below normal + 1 + osPriorityBelowNormal2 = 16+2, ///< Priority: below normal + 2 + osPriorityBelowNormal3 = 16+3, ///< Priority: below normal + 3 + osPriorityBelowNormal4 = 16+4, ///< Priority: below normal + 4 + osPriorityBelowNormal5 = 16+5, ///< Priority: below normal + 5 + osPriorityBelowNormal6 = 16+6, ///< Priority: below normal + 6 + osPriorityBelowNormal7 = 16+7, ///< Priority: below normal + 7 + osPriorityNormal = 24, ///< Priority: normal + osPriorityNormal1 = 24+1, ///< Priority: normal + 1 + osPriorityNormal2 = 24+2, ///< Priority: normal + 2 + osPriorityNormal3 = 24+3, ///< Priority: normal + 3 + osPriorityNormal4 = 24+4, ///< Priority: normal + 4 + osPriorityNormal5 = 24+5, ///< Priority: normal + 5 + osPriorityNormal6 = 24+6, ///< Priority: normal + 6 + osPriorityNormal7 = 24+7, ///< Priority: normal + 7 + osPriorityAboveNormal = 32, ///< Priority: above normal + osPriorityAboveNormal1 = 32+1, ///< Priority: above normal + 1 + osPriorityAboveNormal2 = 32+2, ///< Priority: above normal + 2 + osPriorityAboveNormal3 = 32+3, ///< Priority: above normal + 3 + osPriorityAboveNormal4 = 32+4, ///< Priority: above normal + 4 + osPriorityAboveNormal5 = 32+5, ///< Priority: above normal + 5 + osPriorityAboveNormal6 = 32+6, ///< Priority: above normal + 6 + osPriorityAboveNormal7 = 32+7, ///< Priority: above normal + 7 + osPriorityHigh = 40, ///< Priority: high + osPriorityHigh1 = 40+1, ///< Priority: high + 1 + osPriorityHigh2 = 40+2, ///< Priority: high + 2 + osPriorityHigh3 = 40+3, ///< Priority: high + 3 + osPriorityHigh4 = 40+4, ///< Priority: high + 4 + osPriorityHigh5 = 40+5, ///< Priority: high + 5 + osPriorityHigh6 = 40+6, ///< Priority: high + 6 + osPriorityHigh7 = 40+7, ///< Priority: high + 7 + osPriorityRealtime = 48, ///< Priority: realtime + osPriorityRealtime1 = 48+1, ///< Priority: realtime + 1 + osPriorityRealtime2 = 48+2, ///< Priority: realtime + 2 + osPriorityRealtime3 = 48+3, ///< Priority: realtime + 3 + osPriorityRealtime4 = 48+4, ///< Priority: realtime + 4 + osPriorityRealtime5 = 48+5, ///< Priority: realtime + 5 + osPriorityRealtime6 = 48+6, ///< Priority: realtime + 6 + osPriorityRealtime7 = 48+7, ///< Priority: realtime + 7 + osPriorityISR = 56, ///< Reserved for ISR deferred thread. + osPriorityError = -1, ///< System cannot determine priority or illegal priority. + osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osPriority_t; + +/// Entry point of a thread. +typedef void (*osThreadFunc_t) (void *argument); + +/// Timer callback function. +typedef void (*osTimerFunc_t) (void *argument); + +/// Timer type. +typedef enum { + osTimerOnce = 0, ///< One-shot timer. + osTimerPeriodic = 1 ///< Repeating timer. +} osTimerType_t; + +// Timeout value. +#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value. + +// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait). +#define osFlagsWaitAny 0x00000000U ///< Wait for any flag (default). +#define osFlagsWaitAll 0x00000001U ///< Wait for all flags. +#define osFlagsNoClear 0x00000002U ///< Do not clear flags which have been specified to wait for. + +// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx). +#define osFlagsError 0x80000000U ///< Error indicator. +#define osFlagsErrorUnknown 0xFFFFFFFFU ///< osError (-1). +#define osFlagsErrorTimeout 0xFFFFFFFEU ///< osErrorTimeout (-2). +#define osFlagsErrorResource 0xFFFFFFFDU ///< osErrorResource (-3). +#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4). +#define osFlagsErrorISR 0xFFFFFFFAU ///< osErrorISR (-6). + +// Thread attributes (attr_bits in \ref osThreadAttr_t). +#define osThreadDetached 0x00000000U ///< Thread created in detached mode (default) +#define osThreadJoinable 0x00000001U ///< Thread created in joinable mode + +// Mutex attributes (attr_bits in \ref osMutexAttr_t). +#define osMutexRecursive 0x00000001U ///< Recursive mutex. +#define osMutexPrioInherit 0x00000002U ///< Priority inherit protocol. +#define osMutexRobust 0x00000008U ///< Robust mutex. + +/// Status code values returned by CMSIS-RTOS functions. +typedef enum { + osOK = 0, ///< Operation completed successfully. + osError = -1, ///< Unspecified RTOS error: run-time error but no other error message fits. + osErrorTimeout = -2, ///< Operation not completed within the timeout period. + osErrorResource = -3, ///< Resource not available. + osErrorParameter = -4, ///< Parameter error. + osErrorNoMemory = -5, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorISR = -6, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines. + osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osStatus_t; + + +/// \details Thread ID identifies the thread. +typedef void *osThreadId_t; + +/// \details Timer ID identifies the timer. +typedef void *osTimerId_t; + +/// \details Event Flags ID identifies the event flags. +typedef void *osEventFlagsId_t; + +/// \details Mutex ID identifies the mutex. +typedef void *osMutexId_t; + +/// \details Semaphore ID identifies the semaphore. +typedef void *osSemaphoreId_t; + +/// \details Memory Pool ID identifies the memory pool. +typedef void *osMemoryPoolId_t; + +/// \details Message Queue ID identifies the message queue. +typedef void *osMessageQueueId_t; + + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + + +/// Attributes structure for thread. +typedef struct { + const char *name; ///< name of the thread + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *stack_mem; ///< memory for stack + uint32_t stack_size; ///< size of stack + osPriority_t priority; ///< initial thread priority (default: osPriorityNormal) + TZ_ModuleId_t tz_module; ///< TrustZone module identifier + uint32_t reserved; ///< reserved (must be 0) +} osThreadAttr_t; + +/// Attributes structure for timer. +typedef struct { + const char *name; ///< name of the timer + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osTimerAttr_t; + +/// Attributes structure for event flags. +typedef struct { + const char *name; ///< name of the event flags + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osEventFlagsAttr_t; + +/// Attributes structure for mutex. +typedef struct { + const char *name; ///< name of the mutex + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osMutexAttr_t; + +/// Attributes structure for semaphore. +typedef struct { + const char *name; ///< name of the semaphore + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osSemaphoreAttr_t; + +/// Attributes structure for memory pool. +typedef struct { + const char *name; ///< name of the memory pool + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *mp_mem; ///< memory for data storage + uint32_t mp_size; ///< size of provided memory for data storage +} osMemoryPoolAttr_t; + +/// Attributes structure for message queue. +typedef struct { + const char *name; ///< name of the message queue + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *mq_mem; ///< memory for data storage + uint32_t mq_size; ///< size of provided memory for data storage +} osMessageQueueAttr_t; + + +// ==== Kernel Management Functions ==== + +/// Initialize the RTOS Kernel. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelInitialize (void); + +/// Get RTOS Kernel Information. +/// \param[out] version pointer to buffer for retrieving version information. +/// \param[out] id_buf pointer to buffer for retrieving kernel identification string. +/// \param[in] id_size size of buffer for kernel identification string. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size); + +/// Get the current RTOS Kernel state. +/// \return current RTOS Kernel state. +osKernelState_t osKernelGetState (void); + +/// Start the RTOS Kernel scheduler. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelStart (void); + +/// Lock the RTOS Kernel scheduler. +/// \return previous lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelLock (void); + +/// Unlock the RTOS Kernel scheduler. +/// \return previous lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelUnlock (void); + +/// Restore the RTOS Kernel scheduler lock state. +/// \param[in] lock lock state obtained by \ref osKernelLock or \ref osKernelUnlock. +/// \return new lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelRestoreLock (int32_t lock); + +/// Suspend the RTOS Kernel scheduler. +/// \return time in ticks, for how long the system can sleep or power-down. +uint32_t osKernelSuspend (void); + +/// Resume the RTOS Kernel scheduler. +/// \param[in] sleep_ticks time in ticks for how long the system was in sleep or power-down mode. +void osKernelResume (uint32_t sleep_ticks); + +/// Get the RTOS kernel tick count. +/// \return RTOS kernel current tick count. +uint32_t osKernelGetTickCount (void); + +/// Get the RTOS kernel tick frequency. +/// \return frequency of the kernel tick in hertz, i.e. kernel ticks per second. +uint32_t osKernelGetTickFreq (void); + +/// Get the RTOS kernel system timer count. +/// \return RTOS kernel current system timer count as 32-bit value. +uint32_t osKernelGetSysTimerCount (void); + +/// Get the RTOS kernel system timer frequency. +/// \return frequency of the system timer in hertz, i.e. timer ticks per second. +uint32_t osKernelGetSysTimerFreq (void); + + +// ==== Thread Management Functions ==== + +/// Create a thread and add it to Active Threads. +/// \param[in] func thread function. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \param[in] attr thread attributes; NULL: default values. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr); + +/// Get name of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return name as null-terminated string. +const char *osThreadGetName (osThreadId_t thread_id); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId_t osThreadGetId (void); + +/// Get current thread state of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return current thread state of the specified thread. +osThreadState_t osThreadGetState (osThreadId_t thread_id); + +/// Get stack size of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return stack size in bytes. +uint32_t osThreadGetStackSize (osThreadId_t thread_id); + +/// Get available stack space of a thread based on stack watermark recording during execution. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return remaining stack space in bytes. +uint32_t osThreadGetStackSpace (osThreadId_t thread_id); + +/// Change priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority); + +/// Get current priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return current priority value of the specified thread. +osPriority_t osThreadGetPriority (osThreadId_t thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadYield (void); + +/// Suspend execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadSuspend (osThreadId_t thread_id); + +/// Resume execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadResume (osThreadId_t thread_id); + +/// Detach a thread (thread storage can be reclaimed when thread terminates). +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadDetach (osThreadId_t thread_id); + +/// Wait for specified thread to terminate. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadJoin (osThreadId_t thread_id); + +/// Terminate execution of current running thread. +__NO_RETURN void osThreadExit (void); + +/// Terminate execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadTerminate (osThreadId_t thread_id); + +/// Get number of active threads. +/// \return number of active threads. +uint32_t osThreadGetCount (void); + +/// Enumerate active threads. +/// \param[out] thread_array pointer to array for retrieving thread IDs. +/// \param[in] array_items maximum number of items in array for retrieving thread IDs. +/// \return number of enumerated threads. +uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items); + + +// ==== Thread Flags Functions ==== + +/// Set the specified Thread Flags of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \param[in] flags specifies the flags of the thread that shall be set. +/// \return thread flags after setting or error code if highest bit set. +uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags); + +/// Clear the specified Thread Flags of current running thread. +/// \param[in] flags specifies the flags of the thread that shall be cleared. +/// \return thread flags before clearing or error code if highest bit set. +uint32_t osThreadFlagsClear (uint32_t flags); + +/// Get the current Thread Flags of current running thread. +/// \return current thread flags. +uint32_t osThreadFlagsGet (void); + +/// Wait for one or more Thread Flags of the current running thread to become signaled. +/// \param[in] flags specifies the flags to wait for. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return thread flags before clearing or error code if highest bit set. +uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value +/// \return status code that indicates the execution status of the function. +osStatus_t osDelay (uint32_t ticks); + +/// Wait until specified time. +/// \param[in] ticks absolute time in ticks +/// \return status code that indicates the execution status of the function. +osStatus_t osDelayUntil (uint32_t ticks); + + +// ==== Timer Management Functions ==== + +/// Create and Initialize a timer. +/// \param[in] func function pointer to callback function. +/// \param[in] type \ref osTimerOnce for one-shot or \ref osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer callback function. +/// \param[in] attr timer attributes; NULL: default values. +/// \return timer ID for reference by other functions or NULL in case of error. +osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr); + +/// Get name of a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return name as null-terminated string. +const char *osTimerGetName (osTimerId_t timer_id); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks); + +/// Stop a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerStop (osTimerId_t timer_id); + +/// Check if a timer is running. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return 0 not running, 1 running. +uint32_t osTimerIsRunning (osTimerId_t timer_id); + +/// Delete a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerDelete (osTimerId_t timer_id); + + +// ==== Event Flags Management Functions ==== + +/// Create and Initialize an Event Flags object. +/// \param[in] attr event flags attributes; NULL: default values. +/// \return event flags ID for reference by other functions or NULL in case of error. +osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr); + +/// Get name of an Event Flags object. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return name as null-terminated string. +const char *osEventFlagsGetName (osEventFlagsId_t ef_id); + +/// Set the specified Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags that shall be set. +/// \return event flags after setting or error code if highest bit set. +uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags); + +/// Clear the specified Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags that shall be cleared. +/// \return event flags before clearing or error code if highest bit set. +uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags); + +/// Get the current Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return current event flags. +uint32_t osEventFlagsGet (osEventFlagsId_t ef_id); + +/// Wait for one or more Event Flags to become signaled. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags to wait for. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event flags before clearing or error code if highest bit set. +uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout); + +/// Delete an Event Flags object. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id); + + +// ==== Mutex Management Functions ==== + +/// Create and Initialize a Mutex object. +/// \param[in] attr mutex attributes; NULL: default values. +/// \return mutex ID for reference by other functions or NULL in case of error. +osMutexId_t osMutexNew (const osMutexAttr_t *attr); + +/// Get name of a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return name as null-terminated string. +const char *osMutexGetName (osMutexId_t mutex_id); + +/// Acquire a Mutex or timeout if it is locked. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout); + +/// Release a Mutex that was acquired by \ref osMutexAcquire. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexRelease (osMutexId_t mutex_id); + +/// Get Thread which owns a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return thread ID of owner thread or NULL when mutex was not acquired. +osThreadId_t osMutexGetOwner (osMutexId_t mutex_id); + +/// Delete a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexDelete (osMutexId_t mutex_id); + + +// ==== Semaphore Management Functions ==== + +/// Create and Initialize a Semaphore object. +/// \param[in] max_count maximum number of available tokens. +/// \param[in] initial_count initial number of available tokens. +/// \param[in] attr semaphore attributes; NULL: default values. +/// \return semaphore ID for reference by other functions or NULL in case of error. +osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr); + +/// Get name of a Semaphore object. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return name as null-terminated string. +const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id); + +/// Acquire a Semaphore token or timeout if no tokens are available. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout); + +/// Release a Semaphore token up to the initial maximum count. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id); + +/// Get current Semaphore token count. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return number of tokens available. +uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id); + +/// Delete a Semaphore object. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id); + + +// ==== Memory Pool Management Functions ==== + +/// Create and Initialize a Memory Pool object. +/// \param[in] block_count maximum number of memory blocks in memory pool. +/// \param[in] block_size memory block size in bytes. +/// \param[in] attr memory pool attributes; NULL: default values. +/// \return memory pool ID for reference by other functions or NULL in case of error. +osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr); + +/// Get name of a Memory Pool object. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return name as null-terminated string. +const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id); + +/// Allocate a memory block from a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return address of the allocated memory block or NULL in case of no memory is available. +void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout); + +/// Return an allocated memory block back to a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \param[in] block address of the allocated memory block to be returned to the memory pool. +/// \return status code that indicates the execution status of the function. +osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block); + +/// Get maximum number of memory blocks in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return maximum number of memory blocks. +uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id); + +/// Get memory block size in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return memory block size in bytes. +uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id); + +/// Get number of memory blocks used in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return number of memory blocks used. +uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id); + +/// Get number of memory blocks available in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return number of memory blocks available. +uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id); + +/// Delete a Memory Pool object. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id); + + +// ==== Message Queue Management Functions ==== + +/// Create and Initialize a Message Queue object. +/// \param[in] msg_count maximum number of messages in queue. +/// \param[in] msg_size maximum message size in bytes. +/// \param[in] attr message queue attributes; NULL: default values. +/// \return message queue ID for reference by other functions or NULL in case of error. +osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr); + +/// Get name of a Message Queue object. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return name as null-terminated string. +const char *osMessageQueueGetName (osMessageQueueId_t mq_id); + +/// Put a Message into a Queue or timeout if Queue is full. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \param[in] msg_ptr pointer to buffer with message to put into a queue. +/// \param[in] msg_prio message priority. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout); + +/// Get a Message from a Queue or timeout if Queue is empty. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \param[out] msg_ptr pointer to buffer for message to get from a queue. +/// \param[out] msg_prio pointer to buffer for message priority or NULL. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout); + +/// Get maximum number of messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return maximum number of messages. +uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id); + +/// Get maximum message size in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return maximum message size in bytes. +uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id); + +/// Get number of queued messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return number of queued messages. +uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id); + +/// Get number of available slots for messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return number of available slots for messages. +uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id); + +/// Reset a Message Queue to initial empty state. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id); + +/// Delete a Message Queue object. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id); + + +#ifdef __cplusplus +} +#endif + +#endif // CMSIS_OS2_H_ diff --git a/source/rtos2/Include/os_tick.h b/source/rtos2/Include/os_tick.h new file mode 100644 index 000000000..8f7cdf667 --- /dev/null +++ b/source/rtos2/Include/os_tick.h @@ -0,0 +1,71 @@ +/**************************************************************************//** + * @file os_tick.h + * @brief CMSIS OS Tick header file + * @version V1.0.1 + * @date 24. November 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef OS_TICK_H +#define OS_TICK_H + +#include + +/// IRQ Handler. +#ifndef IRQHANDLER_T +#define IRQHANDLER_T +typedef void (*IRQHandler_t) (void); +#endif + +/// Setup OS Tick timer to generate periodic RTOS Kernel Ticks +/// \param[in] freq tick frequency in Hz +/// \param[in] handler tick IRQ handler +/// \return 0 on success, -1 on error. +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler); + +/// Enable OS Tick timer interrupt +void OS_Tick_Enable (void); + +/// Disable OS Tick timer interrupt +void OS_Tick_Disable (void); + +/// Acknowledge execution of OS Tick timer interrupt +void OS_Tick_AcknowledgeIRQ (void); + +/// Get OS Tick timer IRQ number +/// \return OS Tick IRQ number +int32_t OS_Tick_GetIRQn (void); + +/// Get OS Tick timer clock frequency +/// \return OS Tick timer clock frequency in Hz +uint32_t OS_Tick_GetClock (void); + +/// Get OS Tick timer interval reload value +/// \return OS Tick timer interval reload value +uint32_t OS_Tick_GetInterval (void); + +/// Get OS Tick timer counter value +/// \return OS Tick timer counter value +uint32_t OS_Tick_GetCount (void); + +/// Get OS Tick timer overflow status +/// \return OS Tick overflow status (1 - overflow, 0 - no overflow). +uint32_t OS_Tick_GetOverflow (void); + +#endif /* OS_TICK_H */ diff --git a/source/rtos2/RTX/Config/RTX_Config.c b/source/rtos2/RTX/Config/RTX_Config.c new file mode 100644 index 000000000..e4871014a --- /dev/null +++ b/source/rtos2/RTX/Config/RTX_Config.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/source/rtos2/RTX/Config/RTX_Config.h b/source/rtos2/RTX/Config/RTX_Config.h new file mode 100644 index 000000000..244ed17e3 --- /dev/null +++ b/source/rtos2/RTX/Config/RTX_Config.h @@ -0,0 +1,580 @@ +/* + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.5.1 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 32768 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 32768 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 3072 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 3072 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 512 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 512 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 512 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 512 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x01U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x01U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x05U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x01U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x01U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x01U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x01U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x01U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x01U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x01U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x01U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#ifndef OS_THREAD_LIBSPACE_NUM +#define OS_THREAD_LIBSPACE_NUM 4 +#endif +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/source/rtos2/RTX/Config/handlers.c b/source/rtos2/RTX/Config/handlers.c new file mode 100644 index 000000000..1cc56d770 --- /dev/null +++ b/source/rtos2/RTX/Config/handlers.c @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Exception handlers (C functions) + * + * ----------------------------------------------------------------------------- + */ +#include "RTE_Components.h" +#include CMSIS_device_header + + +//Fault Status Register (IFSR/DFSR) definitions +#define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup +#define FSR_INSTRUCTION_CACHE_MAINTENANCE 0x04 //DFSR only - async/external +#define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external +#define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external +#define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external +#define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external +#define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal +#define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal +#define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal +#define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal +#define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal +#define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal +#define FSR_PERMISSION_FAULT_FIRST 0x0f //MMU Fault - internal +#define FSR_PERMISSION_FAULT_SECOND 0x0d //MMU Fault - internal +#define FSR_DEBUG_EVENT 0x02 //internal +#define FSR_SYNC_EXT_ABORT 0x08 //sync/external +#define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external +#define FSR_LOCKDOWN 0x14 //internal +#define FSR_COPROCESSOR_ABORT 0x1a //internal +#define FSR_SYNC_PARITY_ERROR 0x19 //sync/external +#define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external +#define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external + +void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) { + uint32_t FS = (DFSR & (1U << 10U)) >> 6U | (DFSR & 0x0FU); //Store Fault Status + (void)DFAR; + (void)LR; + + switch(FS) { + //Synchronous parity errors - retry + case FSR_SYNC_PARITY_ERROR: + case FSR_SYNC_PARITY_TTB_WALK_FIRST: + case FSR_SYNC_PARITY_TTB_WALK_SECOND: + return; + + //Your code here. Value in DFAR is invalid for some fault statuses. + case FSR_ALIGNMENT_FAULT: + case FSR_INSTRUCTION_CACHE_MAINTENANCE: + case FSR_SYNC_EXT_TTB_WALK_FIRST: + case FSR_SYNC_EXT_TTB_WALK_SECOND: + case FSR_TRANSLATION_FAULT_FIRST: + case FSR_TRANSLATION_FAULT_SECOND: + case FSR_ACCESS_FLAG_FAULT_FIRST: + case FSR_ACCESS_FLAG_FAULT_SECOND: + case FSR_DOMAIN_FAULT_FIRST: + case FSR_DOMAIN_FAULT_SECOND: + case FSR_PERMISSION_FAULT_FIRST: + case FSR_PERMISSION_FAULT_SECOND: + case FSR_DEBUG_EVENT: + case FSR_SYNC_EXT_ABORT: + case FSR_TLB_CONFLICT_ABORT: + case FSR_LOCKDOWN: + case FSR_COPROCESSOR_ABORT: + case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid + case FSR_ASYNC_PARITY_ERROR: //DFAR invalid + default: + while(1); + } +} + +void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) { + uint32_t FS = (IFSR & (1U << 10U)) >> 6U | (IFSR & 0x0FU); //Store Fault Status + (void)IFAR; + (void)LR; + + switch(FS) { + //Synchronous parity errors - retry + case FSR_SYNC_PARITY_ERROR: + case FSR_SYNC_PARITY_TTB_WALK_FIRST: + case FSR_SYNC_PARITY_TTB_WALK_SECOND: + return; + + //Your code here. Value in IFAR is invalid for some fault statuses. + case FSR_SYNC_EXT_TTB_WALK_FIRST: + case FSR_SYNC_EXT_TTB_WALK_SECOND: + case FSR_TRANSLATION_FAULT_FIRST: + case FSR_TRANSLATION_FAULT_SECOND: + case FSR_ACCESS_FLAG_FAULT_FIRST: + case FSR_ACCESS_FLAG_FAULT_SECOND: + case FSR_DOMAIN_FAULT_FIRST: + case FSR_DOMAIN_FAULT_SECOND: + case FSR_PERMISSION_FAULT_FIRST: + case FSR_PERMISSION_FAULT_SECOND: + case FSR_DEBUG_EVENT: //IFAR invalid + case FSR_SYNC_EXT_ABORT: + case FSR_TLB_CONFLICT_ABORT: + case FSR_LOCKDOWN: + case FSR_COPROCESSOR_ABORT: + default: + while(1); + } +} + + +//returns amount to decrement lr by +//this will be 0 when we have emulated the instruction and want to execute the next instruction +//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2) +//this will be 4 when we have performed some maintenance and want to retry the instruction in Arm (state == 4) +uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) { + const uint32_t THUMB = 2U; + const uint32_t ARM = 4U; + (void)LR; + //Lazy VFP/NEON initialisation and switching + + // (Arm Architecture Reference Manual section A7.5) VFP data processing instruction? + // (Arm Architecture Reference Manual section A7.6) VFP/NEON register load/store instruction? + // (Arm Architecture Reference Manual section A7.8) VFP/NEON register data transfer instruction? + // (Arm Architecture Reference Manual section A7.9) VFP/NEON 64-bit register data transfer instruction? + if ((state == ARM && ((opcode & 0x0C000000U) >> 26U == 0x03U)) || + (state == THUMB && ((opcode & 0xEC000000U) >> 26U == 0x3BU))) { + if (((opcode & 0x00000E00U) >> 9U) == 5U) { + __FPU_Enable(); + return state; + } + } + + // (Arm Architecture Reference Manual section A7.4) NEON data processing instruction? + if ((state == ARM && ((opcode & 0xFE000000U) >> 24U == 0xF2U)) || + (state == THUMB && ((opcode & 0xEF000000U) >> 24U == 0xEFU)) || + // (Arm Architecture Reference Manual section A7.7) NEON load/store instruction? + (state == ARM && ((opcode >> 24U) == 0xF4U)) || + (state == THUMB && ((opcode >> 24U) == 0xF9U))) { + __FPU_Enable(); + return state; + } + + //Add code here for other Undef cases + while(1); +} diff --git a/source/rtos2/RTX/Include/rtx_evr.h b/source/rtos2/RTX/Include/rtx_evr.h new file mode 100644 index 000000000..1dec30a79 --- /dev/null +++ b/source/rtos2/RTX/Include/rtx_evr.h @@ -0,0 +1,1974 @@ +/* + * Copyright (c) 2013-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: RTX Event Recorder definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_EVR_H_ +#define RTX_EVR_H_ + +#include "cmsis_os2.h" // CMSIS RTOS API +#include "RTX_Config.h" // RTX Configuration +#include "rtx_os.h" // RTX OS definitions + +// Initial Thread configuration covered also Thread Flags and Generic Wait +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS OS_EVR_THREAD +#endif +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT OS_EVR_THREAD +#endif + +#ifdef _RTE_ +#include "RTE_Components.h" +#endif + +#ifdef RTE_Compiler_EventRecorder + +//lint -emacro((835,845),EventID) [MISRA Note 13] + +#include "EventRecorder.h" +#include "EventRecorderConf.h" + +#if ((defined(OS_EVR_INIT) && (OS_EVR_INIT != 0)) || (EVENT_TIMESTAMP_SOURCE == 2)) +#ifndef EVR_RTX_KERNEL_GET_STATE_DISABLE +#define EVR_RTX_KERNEL_GET_STATE_DISABLE +#endif +#endif + +#if (EVENT_TIMESTAMP_SOURCE == 2) +#ifndef EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE +#define EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE +#endif +#ifndef EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE +#define EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE +#endif +#endif + +/// RTOS component number +#define EvtRtxMemoryNo (0xF0U) +#define EvtRtxKernelNo (0xF1U) +#define EvtRtxThreadNo (0xF2U) +#define EvtRtxThreadFlagsNo (0xF4U) +#define EvtRtxWaitNo (0xF3U) +#define EvtRtxTimerNo (0xF6U) +#define EvtRtxEventFlagsNo (0xF5U) +#define EvtRtxMutexNo (0xF7U) +#define EvtRtxSemaphoreNo (0xF8U) +#define EvtRtxMemoryPoolNo (0xF9U) +#define EvtRtxMessageQueueNo (0xFAU) + +#endif // RTE_Compiler_EventRecorder + + +/// Extended Status codes +#define osRtxErrorKernelNotReady (-7) +#define osRtxErrorKernelNotRunning (-8) +#define osRtxErrorInvalidControlBlock (-9) +#define osRtxErrorInvalidDataMemory (-10) +#define osRtxErrorInvalidThreadStack (-11) +#define osRtxErrorInvalidPriority (-12) +#define osRtxErrorThreadNotJoinable (-13) +#define osRtxErrorMutexNotOwned (-14) +#define osRtxErrorMutexNotLocked (-15) +#define osRtxErrorMutexLockLimit (-16) +#define osRtxErrorSemaphoreCountLimit (-17) +#define osRtxErrorTZ_InitContext_S (-18) +#define osRtxErrorTZ_AllocContext_S (-19) +#define osRtxErrorTZ_FreeContext_S (-20) +#define osRtxErrorTZ_LoadContext_S (-21) +#define osRtxErrorTZ_SaveContext_S (-22) + + +// ==== Memory Events ==== + +/** + \brief Event on memory initialization (Op) + \param[in] mem pointer to memory pool. + \param[in] size size of a memory pool in bytes. + \param[in] result execution status: 1 - success, 0 - failure. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_INIT_DISABLE)) +extern void EvrRtxMemoryInit (void *mem, uint32_t size, uint32_t result); +#else +#define EvrRtxMemoryInit(mem, size, result) +#endif + +/** + \brief Event on memory allocate (Op) + \param[in] mem pointer to memory pool. + \param[in] size size of a memory block in bytes. + \param[in] type memory block type: 0 - generic, 1 - control block. + \param[in] block pointer to allocated memory block or NULL in case of no memory is available. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_ALLOC_DISABLE)) +extern void EvrRtxMemoryAlloc (void *mem, uint32_t size, uint32_t type, void *block); +#else +#define EvrRtxMemoryAlloc(mem, size, type, block) +#endif + +/** + \brief Event on memory free (Op) + \param[in] mem pointer to memory pool. + \param[in] block memory block to be returned to the memory pool. + \param[in] result execution status: 1 - success, 0 - failure. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_FREE_DISABLE)) +extern void EvrRtxMemoryFree (void *mem, void *block, uint32_t result); +#else +#define EvrRtxMemoryFree(mem, block, result) +#endif + +/** + \brief Event on memory block initialization (Op) + \param[in] mp_info memory pool info. + \param[in] block_count maximum number of memory blocks in memory pool. + \param[in] block_size size of a memory block in bytes. + \param[in] block_mem pointer to memory for block storage. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_INIT_DISABLE)) +extern void EvrRtxMemoryBlockInit (osRtxMpInfo_t *mp_info, uint32_t block_count, uint32_t block_size, void *block_mem); +#else +#define EvrRtxMemoryBlockInit(mp_info, block_count, block_size, block_mem) +#endif + +/** + \brief Event on memory block alloc (Op) + \param[in] mp_info memory pool info. + \param[in] block address of the allocated memory block or NULL in case of no memory is available. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_ALLOC_DISABLE)) +extern void EvrRtxMemoryBlockAlloc (osRtxMpInfo_t *mp_info, void *block); +#else +#define EvrRtxMemoryBlockAlloc(mp_info, block) +#endif + +/** + \brief Event on memory block free (Op) + \param[in] mp_info memory pool info. + \param[in] block address of the allocated memory block to be returned to the memory pool. + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_FREE_DISABLE)) +extern void EvrRtxMemoryBlockFree (osRtxMpInfo_t *mp_info, void *block, int32_t status); +#else +#define EvrRtxMemoryBlockFree(mp_info, block, status) +#endif + + +// ==== Kernel Events ==== + +/** + \brief Event on RTOS kernel error (Error) + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_ERROR_DISABLE)) +extern void EvrRtxKernelError (int32_t status); +#else +#define EvrRtxKernelError(status) +#endif + +/** + \brief Event on RTOS kernel initialize (API) +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZE_DISABLE)) +extern void EvrRtxKernelInitialize (void); +#else +#define EvrRtxKernelInitialize() +#endif + +/** + \brief Event on successful RTOS kernel initialize (Op) +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZED_DISABLE)) +extern void EvrRtxKernelInitialized (void); +#else +#define EvrRtxKernelInitialized() +#endif + +/** + \brief Event on RTOS kernel information retrieve (API) + \param[in] version pointer to buffer for retrieving version information. + \param[in] id_buf pointer to buffer for retrieving kernel identification string. + \param[in] id_size size of buffer for kernel identification string. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_INFO_DISABLE)) +extern void EvrRtxKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size); +#else +#define EvrRtxKernelGetInfo(version, id_buf, id_size) +#endif + +/** + \brief Event on successful RTOS kernel information retrieve (Op) + \param[in] version pointer to buffer for retrieving version information. + \param[in] id_buf pointer to buffer for retrieving kernel identification string. + \param[in] id_size size of buffer for kernel identification string. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INFO_RETRIEVED_DISABLE)) +extern void EvrRtxKernelInfoRetrieved (const osVersion_t *version, const char *id_buf, uint32_t id_size); +#else +#define EvrRtxKernelInfoRetrieved(version, id_buf, id_size) +#endif + +/** + \brief Event on current RTOS Kernel state retrieve (API) + \param[in] state current RTOS Kernel state. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_STATE_DISABLE)) +extern void EvrRtxKernelGetState (osKernelState_t state); +#else +#define EvrRtxKernelGetState(state) +#endif + +/** + \brief Event on RTOS Kernel scheduler start (API) +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_START_DISABLE)) +extern void EvrRtxKernelStart (void); +#else +#define EvrRtxKernelStart() +#endif + +/** + \brief Event on successful RTOS Kernel scheduler start (Op) +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_STARTED_DISABLE)) +extern void EvrRtxKernelStarted (void); +#else +#define EvrRtxKernelStarted() +#endif + +/** + \brief Event on RTOS Kernel scheduler lock (API) +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCK_DISABLE)) +extern void EvrRtxKernelLock (void); +#else +#define EvrRtxKernelLock() +#endif + +/** + \brief Event on successful RTOS Kernel scheduler lock (Op) + \param[in] lock previous lock state (1 - locked, 0 - not locked). +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCKED_DISABLE)) +extern void EvrRtxKernelLocked (int32_t lock); +#else +#define EvrRtxKernelLocked(lock) +#endif + +/** + \brief Event on RTOS Kernel scheduler unlock (API) +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_UNLOCK_DISABLE)) +extern void EvrRtxKernelUnlock (void); +#else +#define EvrRtxKernelUnlock() +#endif + +/** + \brief Event on successful RTOS Kernel scheduler unlock (Op) + \param[in] lock previous lock state (1 - locked, 0 - not locked). +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_UNLOCKED_DISABLE)) +extern void EvrRtxKernelUnlocked (int32_t lock); +#else +#define EvrRtxKernelUnlocked(lock) +#endif + +/** + \brief Event on RTOS Kernel scheduler lock state restore (API) + \param[in] lock lock state obtained by \ref osKernelLock or \ref osKernelUnlock. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESTORE_LOCK_DISABLE)) +extern void EvrRtxKernelRestoreLock (int32_t lock); +#else +#define EvrRtxKernelRestoreLock(lock) +#endif + +/** + \brief Event on successful RTOS Kernel scheduler lock state restore (Op) + \param[in] lock new lock state (1 - locked, 0 - not locked). +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCK_RESTORED_DISABLE)) +extern void EvrRtxKernelLockRestored (int32_t lock); +#else +#define EvrRtxKernelLockRestored(lock) +#endif + +/** + \brief Event on RTOS Kernel scheduler suspend (API) +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_SUSPEND_DISABLE)) +extern void EvrRtxKernelSuspend (void); +#else +#define EvrRtxKernelSuspend() +#endif + +/** + \brief Event on successful RTOS Kernel scheduler suspend (Op) + \param[in] sleep_ticks time in ticks, for how long the system can sleep or power-down. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_SUSPENDED_DISABLE)) +extern void EvrRtxKernelSuspended (uint32_t sleep_ticks); +#else +#define EvrRtxKernelSuspended(sleep_ticks) +#endif + +/** + \brief Event on RTOS Kernel scheduler resume (API) + \param[in] sleep_ticks time in ticks, for how long the system was in sleep or power-down mode. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESUME_DISABLE)) +extern void EvrRtxKernelResume (uint32_t sleep_ticks); +#else +#define EvrRtxKernelResume(sleep_ticks) +#endif + +/** + \brief Event on successful RTOS Kernel scheduler resume (Op) +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESUMED_DISABLE)) +extern void EvrRtxKernelResumed (void); +#else +#define EvrRtxKernelResumed() +#endif + +/** + \brief Event on RTOS kernel tick count retrieve (API) + \param[in] count RTOS kernel current tick count. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_COUNT_DISABLE)) +extern void EvrRtxKernelGetTickCount (uint32_t count); +#else +#define EvrRtxKernelGetTickCount(count) +#endif + +/** + \brief Event on RTOS kernel tick frequency retrieve (API) + \param[in] freq frequency of the kernel tick. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_FREQ_DISABLE)) +extern void EvrRtxKernelGetTickFreq (uint32_t freq); +#else +#define EvrRtxKernelGetTickFreq(freq) +#endif + +/** + \brief Event on RTOS kernel system timer count retrieve (API) + \param[in] count RTOS kernel current system timer count as 32-bit value. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE)) +extern void EvrRtxKernelGetSysTimerCount (uint32_t count); +#else +#define EvrRtxKernelGetSysTimerCount(count) +#endif + +/** + \brief Event on RTOS kernel system timer frequency retrieve (API) + \param[in] freq frequency of the system timer. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE)) +extern void EvrRtxKernelGetSysTimerFreq (uint32_t freq); +#else +#define EvrRtxKernelGetSysTimerFreq(freq) +#endif + + +// ==== Thread Events ==== + +/** + \brief Event on thread error (Error) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId or NULL when ID is unknown. + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_ERROR_DISABLE)) +extern void EvrRtxThreadError (osThreadId_t thread_id, int32_t status); +#else +#define EvrRtxThreadError(thread_id, status) +#endif + +/** + \brief Event on thread create and intialize (API) + \param[in] func thread function. + \param[in] argument pointer that is passed to the thread function as start argument. + \param[in] attr thread attributes. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_NEW_DISABLE)) +extern void EvrRtxThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr); +#else +#define EvrRtxThreadNew(func, argument, attr) +#endif + +/** + \brief Event on successful thread create (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] thread_addr thread entry address. + \param[in] name pointer to thread object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_CREATED_DISABLE)) +extern void EvrRtxThreadCreated (osThreadId_t thread_id, uint32_t thread_addr, const char *name); +#else +#define EvrRtxThreadCreated(thread_id, thread_addr, name) +#endif + +/** + \brief Event on thread name retrieve (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] name pointer to thread object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_NAME_DISABLE)) +extern void EvrRtxThreadGetName (osThreadId_t thread_id, const char *name); +#else +#define EvrRtxThreadGetName(thread_id, name) +#endif + +/** + \brief Event on current running thread ID retrieve (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_ID_DISABLE)) +extern void EvrRtxThreadGetId (osThreadId_t thread_id); +#else +#define EvrRtxThreadGetId(thread_id) +#endif + +/** + \brief Event on thread state retrieve (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] state current thread state of the specified thread. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STATE_DISABLE)) +extern void EvrRtxThreadGetState (osThreadId_t thread_id, osThreadState_t state); +#else +#define EvrRtxThreadGetState(thread_id, state) +#endif + +/** + \brief Event on thread stack size retrieve (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] stack_size stack size in bytes. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STACK_SIZE_DISABLE)) +extern void EvrRtxThreadGetStackSize (osThreadId_t thread_id, uint32_t stack_size); +#else +#define EvrRtxThreadGetStackSize(thread_id, stack_size) +#endif + +/** + \brief Event on available stack space retrieve (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] stack_space remaining stack space in bytes. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STACK_SPACE_DISABLE)) +extern void EvrRtxThreadGetStackSpace (osThreadId_t thread_id, uint32_t stack_space); +#else +#define EvrRtxThreadGetStackSpace(thread_id, stack_space) +#endif + +/** + \brief Event on thread priority set (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] priority new priority value for the thread function. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SET_PRIORITY_DISABLE)) +extern void EvrRtxThreadSetPriority (osThreadId_t thread_id, osPriority_t priority); +#else +#define EvrRtxThreadSetPriority(thread_id, priority) +#endif + +/** + \brief Event on thread priority updated (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] priority new priority value for the thread function. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PRIORITY_UPDATED_DISABLE)) +extern void EvrRtxThreadPriorityUpdated (osThreadId_t thread_id, osPriority_t priority); +#else +#define EvrRtxThreadPriorityUpdated(thread_id, priority) +#endif + +/** + \brief Event on thread priority retrieve (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] priority current priority value of the specified thread. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_PRIORITY_DISABLE)) +extern void EvrRtxThreadGetPriority (osThreadId_t thread_id, osPriority_t priority); +#else +#define EvrRtxThreadGetPriority(thread_id, priority) +#endif + +/** + \brief Event on thread yield (API) +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_YIELD_DISABLE)) +extern void EvrRtxThreadYield (void); +#else +#define EvrRtxThreadYield() +#endif + +/** + \brief Event on thread suspend (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPEND_DISABLE)) +extern void EvrRtxThreadSuspend (osThreadId_t thread_id); +#else +#define EvrRtxThreadSuspend(thread_id) +#endif + +/** + \brief Event on successful thread suspend (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPENDED_DISABLE)) +extern void EvrRtxThreadSuspended (osThreadId_t thread_id); +#else +#define EvrRtxThreadSuspended(thread_id) +#endif + +/** + \brief Event on thread resume (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUME_DISABLE)) +extern void EvrRtxThreadResume (osThreadId_t thread_id); +#else +#define EvrRtxThreadResume(thread_id) +#endif + +/** + \brief Event on successful thread resume (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUMED_DISABLE)) +extern void EvrRtxThreadResumed (osThreadId_t thread_id); +#else +#define EvrRtxThreadResumed(thread_id) +#endif + +/** + \brief Event on thread detach (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DETACH_DISABLE)) +extern void EvrRtxThreadDetach (osThreadId_t thread_id); +#else +#define EvrRtxThreadDetach(thread_id) +#endif + +/** + \brief Event on successful thread detach (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DETACHED_DISABLE)) +extern void EvrRtxThreadDetached (osThreadId_t thread_id); +#else +#define EvrRtxThreadDetached(thread_id) +#endif + +/** + \brief Event on thread join (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOIN_DISABLE)) +extern void EvrRtxThreadJoin (osThreadId_t thread_id); +#else +#define EvrRtxThreadJoin(thread_id) +#endif + +/** + \brief Event on pending thread join (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOIN_PENDING_DISABLE)) +extern void EvrRtxThreadJoinPending (osThreadId_t thread_id); +#else +#define EvrRtxThreadJoinPending(thread_id) +#endif + +/** + \brief Event on successful thread join (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOINED_DISABLE)) +extern void EvrRtxThreadJoined (osThreadId_t thread_id); +#else +#define EvrRtxThreadJoined(thread_id) +#endif + +/** + \brief Event on thread execution block (Detail) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_BLOCKED_DISABLE)) +extern void EvrRtxThreadBlocked (osThreadId_t thread_id, uint32_t timeout); +#else +#define EvrRtxThreadBlocked(thread_id, timeout) +#endif + +/** + \brief Event on thread execution unblock (Detail) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] ret_val extended execution status of the thread. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_UNBLOCKED_DISABLE)) +extern void EvrRtxThreadUnblocked (osThreadId_t thread_id, uint32_t ret_val); +#else +#define EvrRtxThreadUnblocked(thread_id, ret_val) +#endif + +/** + \brief Event on running thread pre-emption (Detail) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PREEMPTED_DISABLE)) +extern void EvrRtxThreadPreempted (osThreadId_t thread_id); +#else +#define EvrRtxThreadPreempted(thread_id) +#endif + +/** + \brief Event on running thread switch (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SWITCHED_DISABLE)) +extern void EvrRtxThreadSwitched (osThreadId_t thread_id); +#else +#define EvrRtxThreadSwitched(thread_id) +#endif + +/** + \brief Event on thread exit (API) +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_EXIT_DISABLE)) +extern void EvrRtxThreadExit (void); +#else +#define EvrRtxThreadExit() +#endif + +/** + \brief Event on thread terminate (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_TERMINATE_DISABLE)) +extern void EvrRtxThreadTerminate (osThreadId_t thread_id); +#else +#define EvrRtxThreadTerminate(thread_id) +#endif + +/** + \brief Event on successful thread terminate (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DESTROYED_DISABLE)) +extern void EvrRtxThreadDestroyed (osThreadId_t thread_id); +#else +#define EvrRtxThreadDestroyed(thread_id) +#endif + +/** + \brief Event on active thread count retrieve (API) + \param[in] count number of active threads. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_COUNT_DISABLE)) +extern void EvrRtxThreadGetCount (uint32_t count); +#else +#define EvrRtxThreadGetCount(count) +#endif + +/** + \brief Event on active threads enumerate (API) + \param[in] thread_array pointer to array for retrieving thread IDs. + \param[in] array_items maximum number of items in array for retrieving thread IDs. + \param[in] count number of enumerated threads. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_ENUMERATE_DISABLE)) +extern void EvrRtxThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items, uint32_t count); +#else +#define EvrRtxThreadEnumerate(thread_array, array_items, count) +#endif + + +// ==== Thread Flags Events ==== + +/** + \brief Event on thread flags error (Error) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId or NULL when ID is unknown. + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_ERROR_DISABLE)) +extern void EvrRtxThreadFlagsError (osThreadId_t thread_id, int32_t status); +#else +#define EvrRtxThreadFlagsError(thread_id, status) +#endif + +/** + \brief Event on thread flags set (API) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] flags flags of the thread that shall be set. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_SET_DISABLE)) +extern void EvrRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags); +#else +#define EvrRtxThreadFlagsSet(thread_id, flags) +#endif + +/** + \brief Event on successful thread flags set (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. + \param[in] thread_flags thread flags after setting. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_SET_DONE_DISABLE)) +extern void EvrRtxThreadFlagsSetDone (osThreadId_t thread_id, uint32_t thread_flags); +#else +#define EvrRtxThreadFlagsSetDone(thread_id, thread_flags) +#endif + +/** + \brief Event on thread flags clear (API) + \param[in] flags flags of the thread that shall be cleared. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_CLEAR_DISABLE)) +extern void EvrRtxThreadFlagsClear (uint32_t flags); +#else +#define EvrRtxThreadFlagsClear(flags) +#endif + +/** + \brief Event on successful thread flags clear (Op) + \param[in] thread_flags thread flags before clearing. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_CLEAR_DONE_DISABLE)) +extern void EvrRtxThreadFlagsClearDone (uint32_t thread_flags); +#else +#define EvrRtxThreadFlagsClearDone(thread_flags) +#endif + +/** + \brief Event on thread flags retrieve (API) + \param[in] thread_flags current thread flags. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_GET_DISABLE)) +extern void EvrRtxThreadFlagsGet (uint32_t thread_flags); +#else +#define EvrRtxThreadFlagsGet(thread_flags) +#endif + +/** + \brief Event on wait for thread flags (API) + \param[in] flags flags to wait for. + \param[in] options flags options (osFlagsXxxx). + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_DISABLE)) +extern void EvrRtxThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout); +#else +#define EvrRtxThreadFlagsWait(flags, options, timeout) +#endif + +/** + \brief Event on pending wait for thread flags (Op) + \param[in] flags flags to wait for. + \param[in] options flags options (osFlagsXxxx). + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_PENDING_DISABLE)) +extern void EvrRtxThreadFlagsWaitPending (uint32_t flags, uint32_t options, uint32_t timeout); +#else +#define EvrRtxThreadFlagsWaitPending(flags, options, timeout) +#endif + +/** + \brief Event on wait timeout for thread flags (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_TIMEOUT_DISABLE)) +extern void EvrRtxThreadFlagsWaitTimeout (osThreadId_t thread_id); +#else +#define EvrRtxThreadFlagsWaitTimeout(thread_id) +#endif + +/** + \brief Event on successful wait for thread flags (Op) + \param[in] flags flags to wait for. + \param[in] options flags options (osFlagsXxxx). + \param[in] thread_flags thread flags before clearing. + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_COMPLETED_DISABLE)) +extern void EvrRtxThreadFlagsWaitCompleted (uint32_t flags, uint32_t options, uint32_t thread_flags, osThreadId_t thread_id); +#else +#define EvrRtxThreadFlagsWaitCompleted(flags, options, thread_flags, thread_id) +#endif + +/** + \brief Event on unsuccessful wait for thread flags (Op) + \param[in] flags flags to wait for. + \param[in] options flags options (osFlagsXxxx). +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_NOT_COMPLETED_DISABLE)) +extern void EvrRtxThreadFlagsWaitNotCompleted (uint32_t flags, uint32_t options); +#else +#define EvrRtxThreadFlagsWaitNotCompleted(flags, options) +#endif + + +// ==== Generic Wait Events ==== + +/** + \brief Event on delay error (Error) + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_ERROR_DISABLE)) +extern void EvrRtxDelayError (int32_t status); +#else +#define EvrRtxDelayError(status) +#endif + +/** + \brief Event on delay for specified time (API) + \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_DISABLE)) +extern void EvrRtxDelay (uint32_t ticks); +#else +#define EvrRtxDelay(ticks) +#endif + +/** + \brief Event on delay until specified time (API) + \param[in] ticks absolute time in ticks. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_UNTIL_DISABLE)) +extern void EvrRtxDelayUntil (uint32_t ticks); +#else +#define EvrRtxDelayUntil(ticks) +#endif + +/** + \brief Event on delay started (Op) + \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_STARTED_DISABLE)) +extern void EvrRtxDelayStarted (uint32_t ticks); +#else +#define EvrRtxDelayStarted(ticks) +#endif + +/** + \brief Event on delay until specified time started (Op) + \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_UNTIL_STARTED_DISABLE)) +extern void EvrRtxDelayUntilStarted (uint32_t ticks); +#else +#define EvrRtxDelayUntilStarted(ticks) +#endif + +/** + \brief Event on delay completed (Op) + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_COMPLETED_DISABLE)) +extern void EvrRtxDelayCompleted (osThreadId_t thread_id); +#else +#define EvrRtxDelayCompleted(thread_id) +#endif + + +// ==== Timer Events ==== + +/** + \brief Event on timer error (Error) + \param[in] timer_id timer ID obtained by \ref osTimerNew or NULL when ID is unknown. + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_ERROR_DISABLE)) +extern void EvrRtxTimerError (osTimerId_t timer_id, int32_t status); +#else +#define EvrRtxTimerError(timer_id, status) +#endif + +/** + \brief Event on timer callback call (Op) + \param[in] func start address of a timer call back function. + \param[in] argument argument to the timer call back function. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_CALLBACK_DISABLE)) +extern void EvrRtxTimerCallback (osTimerFunc_t func, void *argument); +#else +#define EvrRtxTimerCallback(func, argument) +#endif + +/** + \brief Event on timer create and initialize (API) + \param[in] func start address of a timer call back function. + \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. + \param[in] argument argument to the timer call back function. + \param[in] attr timer attributes. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_NEW_DISABLE)) +extern void EvrRtxTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr); +#else +#define EvrRtxTimerNew(func, type, argument, attr) +#endif + +/** + \brief Event on successful timer create (Op) + \param[in] timer_id timer ID obtained by \ref osTimerNew. + \param[in] name pointer to timer object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_CREATED_DISABLE)) +extern void EvrRtxTimerCreated (osTimerId_t timer_id, const char *name); +#else +#define EvrRtxTimerCreated(timer_id, name) +#endif + +/** + \brief Event on timer name retrieve (API) + \param[in] timer_id timer ID obtained by \ref osTimerNew. + \param[in] name pointer to timer object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_GET_NAME_DISABLE)) +extern void EvrRtxTimerGetName (osTimerId_t timer_id, const char *name); +#else +#define EvrRtxTimerGetName(timer_id, name) +#endif + +/** + \brief Event on timer start (API) + \param[in] timer_id timer ID obtained by \ref osTimerNew. + \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_START_DISABLE)) +extern void EvrRtxTimerStart (osTimerId_t timer_id, uint32_t ticks); +#else +#define EvrRtxTimerStart(timer_id, ticks) +#endif + +/** + \brief Event on successful timer start (Op) + \param[in] timer_id timer ID obtained by \ref osTimerNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STARTED_DISABLE)) +extern void EvrRtxTimerStarted (osTimerId_t timer_id); +#else +#define EvrRtxTimerStarted(timer_id) +#endif + +/** + \brief Event on timer stop (API) + \param[in] timer_id timer ID obtained by \ref osTimerNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOP_DISABLE)) +extern void EvrRtxTimerStop (osTimerId_t timer_id); +#else +#define EvrRtxTimerStop(timer_id) +#endif + +/** + \brief Event on successful timer stop (Op) + \param[in] timer_id timer ID obtained by \ref osTimerNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOPPED_DISABLE)) +extern void EvrRtxTimerStopped (osTimerId_t timer_id); +#else +#define EvrRtxTimerStopped(timer_id) +#endif + +/** + \brief Event on timer running state check (API) + \param[in] timer_id timer ID obtained by \ref osTimerNew. + \param[in] running running state: 0 not running, 1 running. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_IS_RUNNING_DISABLE)) +extern void EvrRtxTimerIsRunning (osTimerId_t timer_id, uint32_t running); +#else +#define EvrRtxTimerIsRunning(timer_id, running) +#endif + +/** + \brief Event on timer delete (API) + \param[in] timer_id timer ID obtained by \ref osTimerNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DELETE_DISABLE)) +extern void EvrRtxTimerDelete (osTimerId_t timer_id); +#else +#define EvrRtxTimerDelete(timer_id) +#endif + +/** + \brief Event on successful timer delete (Op) + \param[in] timer_id timer ID obtained by \ref osTimerNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DESTROYED_DISABLE)) +extern void EvrRtxTimerDestroyed (osTimerId_t timer_id); +#else +#define EvrRtxTimerDestroyed(timer_id) +#endif + + +// ==== Event Flags Events ==== + +/** + \brief Event on event flags error (Error) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew or NULL when ID is unknown. + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_ERROR_DISABLE)) +extern void EvrRtxEventFlagsError (osEventFlagsId_t ef_id, int32_t status); +#else +#define EvrRtxEventFlagsError(ef_id, status) +#endif + +/** + \brief Event on event flags create and initialize (API) + \param[in] attr event flags attributes. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_NEW_DISABLE)) +extern void EvrRtxEventFlagsNew (const osEventFlagsAttr_t *attr); +#else +#define EvrRtxEventFlagsNew(attr) +#endif + +/** + \brief Event on successful event flags create (Op) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] name pointer to event flags object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CREATED_DISABLE)) +extern void EvrRtxEventFlagsCreated (osEventFlagsId_t ef_id, const char *name); +#else +#define EvrRtxEventFlagsCreated(ef_id, name) +#endif + +/** + \brief Event on event flags name retrieve (API) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] name pointer to event flags object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_GET_NAME_DISABLE)) +extern void EvrRtxEventFlagsGetName (osEventFlagsId_t ef_id, const char *name); +#else +#define EvrRtxEventFlagsGetName(ef_id, name) +#endif + +/** + \brief Event on event flags set (API) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] flags flags that shall be set. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_SET_DISABLE)) +extern void EvrRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags); +#else +#define EvrRtxEventFlagsSet(ef_id, flags) +#endif + +/** + \brief Event on successful event flags set (Op) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] event_flags event flags after setting. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_SET_DONE_DISABLE)) +extern void EvrRtxEventFlagsSetDone (osEventFlagsId_t ef_id, uint32_t event_flags); +#else +#define EvrRtxEventFlagsSetDone(ef_id, event_flags) +#endif + +/** + \brief Event on event flags clear (API) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] flags flags that shall be cleared. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CLEAR_DISABLE)) +extern void EvrRtxEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags); +#else +#define EvrRtxEventFlagsClear(ef_id, flags) +#endif + +/** + \brief Event on successful event flags clear (Op) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] event_flags event flags before clearing. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CLEAR_DONE_DISABLE)) +extern void EvrRtxEventFlagsClearDone (osEventFlagsId_t ef_id, uint32_t event_flags); +#else +#define EvrRtxEventFlagsClearDone(ef_id, event_flags) +#endif + +/** + \brief Event on event flags retrieve (API) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] event_flags current event flags. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_GET_DISABLE)) +extern void EvrRtxEventFlagsGet (osEventFlagsId_t ef_id, uint32_t event_flags); +#else +#define EvrRtxEventFlagsGet(ef_id, event_flags) +#endif + +/** + \brief Event on wait for event flags (API) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] flags flags to wait for. + \param[in] options flags options (osFlagsXxxx). + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_DISABLE)) +extern void EvrRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout); +#else +#define EvrRtxEventFlagsWait(ef_id, flags, options, timeout) +#endif + +/** + \brief Event on pending wait for event flags (Op) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] flags flags to wait for. + \param[in] options flags options (osFlagsXxxx). + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_PENDING_DISABLE)) +extern void EvrRtxEventFlagsWaitPending (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout); +#else +#define EvrRtxEventFlagsWaitPending(ef_id, flags, options, timeout) +#endif + +/** + \brief Event on wait timeout for event flags (Op) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_TIMEOUT_DISABLE)) +extern void EvrRtxEventFlagsWaitTimeout (osEventFlagsId_t ef_id); +#else +#define EvrRtxEventFlagsWaitTimeout(ef_id) +#endif + +/** + \brief Event on successful wait for event flags (Op) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] flags flags to wait for. + \param[in] options flags options (osFlagsXxxx). + \param[in] event_flags event flags before clearing or 0 if specified flags have not been set. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_COMPLETED_DISABLE)) +extern void EvrRtxEventFlagsWaitCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t event_flags); +#else +#define EvrRtxEventFlagsWaitCompleted(ef_id, flags, options, event_flags) +#endif + +/** + \brief Event on unsuccessful wait for event flags (Op) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. + \param[in] flags flags to wait for. + \param[in] options flags options (osFlagsXxxx). +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_NOT_COMPLETED_DISABLE)) +extern void EvrRtxEventFlagsWaitNotCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options); +#else +#define EvrRtxEventFlagsWaitNotCompleted(ef_id, flags, options) +#endif + +/** + \brief Event on event flags delete (API) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_DELETE_DISABLE)) +extern void EvrRtxEventFlagsDelete (osEventFlagsId_t ef_id); +#else +#define EvrRtxEventFlagsDelete(ef_id) +#endif + +/** + \brief Event on successful event flags delete (Op) + \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_DESTROYED_DISABLE)) +extern void EvrRtxEventFlagsDestroyed (osEventFlagsId_t ef_id); +#else +#define EvrRtxEventFlagsDestroyed(ef_id) +#endif + + +// ==== Mutex Events ==== + +/** + \brief Event on mutex error (Error) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew or NULL when ID is unknown. + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ERROR_DISABLE)) +extern void EvrRtxMutexError (osMutexId_t mutex_id, int32_t status); +#else +#define EvrRtxMutexError(mutex_id, status) +#endif + +/** + \brief Event on mutex create and initialize (API) + \param[in] attr mutex attributes. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_NEW_DISABLE)) +extern void EvrRtxMutexNew (const osMutexAttr_t *attr); +#else +#define EvrRtxMutexNew(attr) +#endif + +/** + \brief Event on successful mutex create (Op) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. + \param[in] name pointer to mutex object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_CREATED_DISABLE)) +extern void EvrRtxMutexCreated (osMutexId_t mutex_id, const char *name); +#else +#define EvrRtxMutexCreated(mutex_id, name) +#endif + +/** + \brief Event on mutex name retrieve (API) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. + \param[in] name pointer to mutex object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_GET_NAME_DISABLE)) +extern void EvrRtxMutexGetName (osMutexId_t mutex_id, const char *name); +#else +#define EvrRtxMutexGetName(mutex_id, name) +#endif + +/** + \brief Event on mutex acquire (API) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_DISABLE)) +extern void EvrRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout); +#else +#define EvrRtxMutexAcquire(mutex_id, timeout) +#endif + +/** + \brief Event on pending mutex acquire (Op) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_PENDING_DISABLE)) +extern void EvrRtxMutexAcquirePending (osMutexId_t mutex_id, uint32_t timeout); +#else +#define EvrRtxMutexAcquirePending(mutex_id, timeout) +#endif + +/** + \brief Event on mutex acquire timeout (Op) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_TIMEOUT_DISABLE)) +extern void EvrRtxMutexAcquireTimeout (osMutexId_t mutex_id); +#else +#define EvrRtxMutexAcquireTimeout(mutex_id) +#endif + +/** + \brief Event on successful mutex acquire (Op) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. + \param[in] lock current number of times mutex object is locked. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRED_DISABLE)) +extern void EvrRtxMutexAcquired (osMutexId_t mutex_id, uint32_t lock); +#else +#define EvrRtxMutexAcquired(mutex_id, lock) +#endif + +/** + \brief Event on unsuccessful mutex acquire (Op) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_NOT_ACQUIRED_DISABLE)) +extern void EvrRtxMutexNotAcquired (osMutexId_t mutex_id); +#else +#define EvrRtxMutexNotAcquired(mutex_id) +#endif + +/** + \brief Event on mutex release (API) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_RELEASE_DISABLE)) +extern void EvrRtxMutexRelease (osMutexId_t mutex_id); +#else +#define EvrRtxMutexRelease(mutex_id) +#endif + +/** + \brief Event on successful mutex release (Op) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. + \param[in] lock current number of times mutex object is locked. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_RELEASED_DISABLE)) +extern void EvrRtxMutexReleased (osMutexId_t mutex_id, uint32_t lock); +#else +#define EvrRtxMutexReleased(mutex_id, lock) +#endif + +/** + \brief Event on mutex owner retrieve (API) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. + \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_GET_OWNER_DISABLE)) +extern void EvrRtxMutexGetOwner (osMutexId_t mutex_id, osThreadId_t thread_id); +#else +#define EvrRtxMutexGetOwner(mutex_id, thread_id) +#endif + +/** + \brief Event on mutex delete (API) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_DELETE_DISABLE)) +extern void EvrRtxMutexDelete (osMutexId_t mutex_id); +#else +#define EvrRtxMutexDelete(mutex_id) +#endif + +/** + \brief Event on successful mutex delete (Op) + \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_DESTROYED_DISABLE)) +extern void EvrRtxMutexDestroyed (osMutexId_t mutex_id); +#else +#define EvrRtxMutexDestroyed(mutex_id) +#endif + + +// ==== Semaphore Events ==== + +/** + \brief Event on semaphore error (Error) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew or NULL when ID is unknown. + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ERROR_DISABLE)) +extern void EvrRtxSemaphoreError (osSemaphoreId_t semaphore_id, int32_t status); +#else +#define EvrRtxSemaphoreError(semaphore_id, status) +#endif + +/** + \brief Event on semaphore create and initialize (API) + \param[in] max_count maximum number of available tokens. + \param[in] initial_count initial number of available tokens. + \param[in] attr semaphore attributes. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_NEW_DISABLE)) +extern void EvrRtxSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr); +#else +#define EvrRtxSemaphoreNew(max_count, initial_count, attr) +#endif + +/** + \brief Event on successful semaphore create (Op) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. + \param[in] name pointer to semaphore object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_CREATED_DISABLE)) +extern void EvrRtxSemaphoreCreated (osSemaphoreId_t semaphore_id, const char *name); +#else +#define EvrRtxSemaphoreCreated(semaphore_id, name) +#endif + +/** + \brief Event on semaphore name retrieve (API) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. + \param[in] name pointer to semaphore object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_GET_NAME_DISABLE)) +extern void EvrRtxSemaphoreGetName (osSemaphoreId_t semaphore_id, const char *name); +#else +#define EvrRtxSemaphoreGetName(semaphore_id, name) +#endif + +/** + \brief Event on semaphore acquire (API) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_DISABLE)) +extern void EvrRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout); +#else +#define EvrRtxSemaphoreAcquire(semaphore_id, timeout) +#endif + +/** + \brief Event on pending semaphore acquire (Op) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_PENDING_DISABLE)) +extern void EvrRtxSemaphoreAcquirePending (osSemaphoreId_t semaphore_id, uint32_t timeout); +#else +#define EvrRtxSemaphoreAcquirePending(semaphore_id, timeout) +#endif + +/** + \brief Event on semaphore acquire timeout (Op) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_TIMEOUT_DISABLE)) +extern void EvrRtxSemaphoreAcquireTimeout (osSemaphoreId_t semaphore_id); +#else +#define EvrRtxSemaphoreAcquireTimeout(semaphore_id) +#endif + +/** + \brief Event on successful semaphore acquire (Op) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. + \param[in] tokens number of available tokens. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRED_DISABLE)) +extern void EvrRtxSemaphoreAcquired (osSemaphoreId_t semaphore_id, uint32_t tokens); +#else +#define EvrRtxSemaphoreAcquired(semaphore_id, tokens) +#endif + +/** + \brief Event on unsuccessful semaphore acquire (Op) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_NOT_ACQUIRED_DISABLE)) +extern void EvrRtxSemaphoreNotAcquired (osSemaphoreId_t semaphore_id); +#else +#define EvrRtxSemaphoreNotAcquired(semaphore_id) +#endif + +/** + \brief Event on semaphore release (API) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASE_DISABLE)) +extern void EvrRtxSemaphoreRelease (osSemaphoreId_t semaphore_id); +#else +#define EvrRtxSemaphoreRelease(semaphore_id) +#endif + +/** + \brief Event on successful semaphore release (Op) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. + \param[in] tokens number of available tokens. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASED_DISABLE)) +extern void EvrRtxSemaphoreReleased (osSemaphoreId_t semaphore_id, uint32_t tokens); +#else +#define EvrRtxSemaphoreReleased(semaphore_id, tokens) +#endif + +/** + \brief Event on semaphore token count retrieval (API) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. + \param[in] count current number of available tokens. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_GET_COUNT_DISABLE)) +extern void EvrRtxSemaphoreGetCount (osSemaphoreId_t semaphore_id, uint32_t count); +#else +#define EvrRtxSemaphoreGetCount(semaphore_id, count) +#endif + +/** + \brief Event on semaphore delete (API) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_DELETE_DISABLE)) +extern void EvrRtxSemaphoreDelete (osSemaphoreId_t semaphore_id); +#else +#define EvrRtxSemaphoreDelete(semaphore_id) +#endif + +/** + \brief Event on successful semaphore delete (Op) + \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_DESTROYED_DISABLE)) +extern void EvrRtxSemaphoreDestroyed (osSemaphoreId_t semaphore_id); +#else +#define EvrRtxSemaphoreDestroyed(semaphore_id) +#endif + + +// ==== Memory Pool Events ==== + +/** + \brief Event on memory pool error (Error) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew or NULL when ID is unknown. + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ERROR_DISABLE)) +extern void EvrRtxMemoryPoolError (osMemoryPoolId_t mp_id, int32_t status); +#else +#define EvrRtxMemoryPoolError(mp_id, status) +#endif + +/** + \brief Event on memory pool create and initialize (API) + \param[in] block_count maximum number of memory blocks in memory pool. + \param[in] block_size memory block size in bytes. + \param[in] attr memory pool attributes; NULL: default values. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_NEW_DISABLE)) +extern void EvrRtxMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr); +#else +#define EvrRtxMemoryPoolNew(block_count, block_size, attr) +#endif + +/** + \brief Event on successful memory pool create (Op) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] name pointer to memory pool object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_CREATED_DISABLE)) +extern void EvrRtxMemoryPoolCreated (osMemoryPoolId_t mp_id, const char *name); +#else +#define EvrRtxMemoryPoolCreated(mp_id, name) +#endif + +/** + \brief Event on memory pool name retrieve (API) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] name pointer to memory pool object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_NAME_DISABLE)) +extern void EvrRtxMemoryPoolGetName (osMemoryPoolId_t mp_id, const char *name); +#else +#define EvrRtxMemoryPoolGetName(mp_id, name) +#endif + +/** + \brief Event on memory pool allocation (API) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_DISABLE)) +extern void EvrRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout); +#else +#define EvrRtxMemoryPoolAlloc(mp_id, timeout) +#endif + +/** + \brief Event on pending memory pool allocation (Op) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_PENDING_DISABLE)) +extern void EvrRtxMemoryPoolAllocPending (osMemoryPoolId_t mp_id, uint32_t timeout); +#else +#define EvrRtxMemoryPoolAllocPending(mp_id, timeout) +#endif + +/** + \brief Event on memory pool allocation timeout (Op) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_TIMEOUT_DISABLE)) +extern void EvrRtxMemoryPoolAllocTimeout (osMemoryPoolId_t mp_id); +#else +#define EvrRtxMemoryPoolAllocTimeout(mp_id) +#endif + +/** + \brief Event on successful memory pool allocation (Op) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] block address of the allocated memory block. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOCATED_DISABLE)) +extern void EvrRtxMemoryPoolAllocated (osMemoryPoolId_t mp_id, void *block); +#else +#define EvrRtxMemoryPoolAllocated(mp_id, block) +#endif + +/** + \brief Event on unsuccessful memory pool allocation (Op) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_FAILED_DISABLE)) +extern void EvrRtxMemoryPoolAllocFailed (osMemoryPoolId_t mp_id); +#else +#define EvrRtxMemoryPoolAllocFailed(mp_id) +#endif + +/** + \brief Event on memory pool free (API) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] block address of the allocated memory block to be returned to the memory pool. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_FREE_DISABLE)) +extern void EvrRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block); +#else +#define EvrRtxMemoryPoolFree(mp_id, block) +#endif + +/** + \brief Event on successful memory pool free (Op) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] block address of the allocated memory block to be returned to the memory pool. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DEALLOCATED_DISABLE)) +extern void EvrRtxMemoryPoolDeallocated (osMemoryPoolId_t mp_id, void *block); +#else +#define EvrRtxMemoryPoolDeallocated(mp_id, block) +#endif + +/** + \brief Event on unsuccessful memory pool free (Op) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] block address of the allocated memory block to be returned to the memory pool. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_FREE_FAILED_DISABLE)) +extern void EvrRtxMemoryPoolFreeFailed (osMemoryPoolId_t mp_id, void *block); +#else +#define EvrRtxMemoryPoolFreeFailed(mp_id, block) +#endif + +/** + \brief Event on memory pool capacity retrieve (API) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] capacity maximum number of memory blocks. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_CAPACITY_DISABLE)) +extern void EvrRtxMemoryPoolGetCapacity (osMemoryPoolId_t mp_id, uint32_t capacity); +#else +#define EvrRtxMemoryPoolGetCapacity(mp_id, capacity) +#endif + +/** + \brief Event on memory pool block size retrieve (API) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] block_size memory block size in bytes. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_BLOCK_SZIE_DISABLE)) +extern void EvrRtxMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id, uint32_t block_size); +#else +#define EvrRtxMemoryPoolGetBlockSize(mp_id, block_size) +#endif + +/** + \brief Event on used memory pool blocks retrieve (API) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] count number of memory blocks used. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_COUNT_DISABLE)) +extern void EvrRtxMemoryPoolGetCount (osMemoryPoolId_t mp_id, uint32_t count); +#else +#define EvrRtxMemoryPoolGetCount(mp_id, count) +#endif + +/** + \brief Event on available memory pool blocks retrieve (API) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. + \param[in] space number of memory blocks available. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_SPACE_DISABLE)) +extern void EvrRtxMemoryPoolGetSpace (osMemoryPoolId_t mp_id, uint32_t space); +#else +#define EvrRtxMemoryPoolGetSpace(mp_id, space) +#endif + +/** + \brief Event on memory pool delete (API) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DELETE_DISABLE)) +extern void EvrRtxMemoryPoolDelete (osMemoryPoolId_t mp_id); +#else +#define EvrRtxMemoryPoolDelete(mp_id) +#endif + +/** + \brief Event on successful memory pool delete (Op) + \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DESTROYED_DISABLE)) +extern void EvrRtxMemoryPoolDestroyed (osMemoryPoolId_t mp_id); +#else +#define EvrRtxMemoryPoolDestroyed(mp_id) +#endif + + +// ==== Message Queue Events ==== + +/** + \brief Event on message queue error (Error) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew or NULL when ID is unknown. + \param[in] status extended execution status. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_ERROR_DISABLE)) +extern void EvrRtxMessageQueueError (osMessageQueueId_t mq_id, int32_t status); +#else +#define EvrRtxMessageQueueError(mq_id, status) +#endif + +/** + \brief Event on message queue create and initialization (API) + \param[in] msg_count maximum number of messages in queue. + \param[in] msg_size maximum message size in bytes. + \param[in] attr message queue attributes; NULL: default values. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NEW_DISABLE)) +extern void EvrRtxMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr); +#else +#define EvrRtxMessageQueueNew(msg_count, msg_size, attr) +#endif + +/** + \brief Event on successful message queue create (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] name pointer to message queue object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_CREATED_DISABLE)) +extern void EvrRtxMessageQueueCreated (osMessageQueueId_t mq_id, const char *name); +#else +#define EvrRtxMessageQueueCreated(mq_id, name) +#endif + +/** + \brief Event on message queue name retrieve(API) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] name pointer to message queue object name. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_NAME_DISABLE)) +extern void EvrRtxMessageQueueGetName (osMessageQueueId_t mq_id, const char *name); +#else +#define EvrRtxMessageQueueGetName(mq_id, name) +#endif + +/** + \brief Event on message put (API) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] msg_ptr pointer to buffer with message to put into a queue. + \param[in] msg_prio message priority. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_DISABLE)) +extern void EvrRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout); +#else +#define EvrRtxMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout) +#endif + +/** + \brief Event on pending message put (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] msg_ptr pointer to buffer with message to put into a queue. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_PENDING_DISABLE)) +extern void EvrRtxMessageQueuePutPending (osMessageQueueId_t mq_id, const void *msg_ptr, uint32_t timeout); +#else +#define EvrRtxMessageQueuePutPending(mq_id, msg_ptr, timeout) +#endif + +/** + \brief Event on message put timeout (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_TIMEOUT_DISABLE)) +extern void EvrRtxMessageQueuePutTimeout (osMessageQueueId_t mq_id); +#else +#define EvrRtxMessageQueuePutTimeout(mq_id) +#endif + +/** + \brief Event on pending message insert (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] msg_ptr pointer to buffer with message to put into a queue. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_INSERT_PENDING_DISABLE)) +extern void EvrRtxMessageQueueInsertPending (osMessageQueueId_t mq_id, const void *msg_ptr); +#else +#define EvrRtxMessageQueueInsertPending(mq_id, msg_ptr) +#endif + +/** + \brief Event on successful message insert (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] msg_ptr pointer to buffer with message to put into a queue. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_INSERTED_DISABLE)) +extern void EvrRtxMessageQueueInserted (osMessageQueueId_t mq_id, const void *msg_ptr); +#else +#define EvrRtxMessageQueueInserted(mq_id, msg_ptr) +#endif + +/** + \brief Event on unsuccessful message insert (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] msg_ptr pointer to buffer with message to put into a queue. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NOT_INSERTED_DISABLE)) +extern void EvrRtxMessageQueueNotInserted (osMessageQueueId_t mq_id, const void *msg_ptr); +#else +#define EvrRtxMessageQueueNotInserted(mq_id, msg_ptr) +#endif + +/** + \brief Event on message get (API) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] msg_ptr pointer to buffer for message to get from a queue. + \param[in] msg_prio message priority. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_DISABLE)) +extern void EvrRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout); +#else +#define EvrRtxMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout) +#endif + +/** + \brief Event on pending message get (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] msg_ptr pointer to buffer for message to get from a queue. + \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_PENDING_DISABLE)) +extern void EvrRtxMessageQueueGetPending (osMessageQueueId_t mq_id, void *msg_ptr, uint32_t timeout); +#else +#define EvrRtxMessageQueueGetPending(mq_id, msg_ptr, timeout) +#endif + +/** + \brief Event on message get timeout (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_TIMEOUT_DISABLE)) +extern void EvrRtxMessageQueueGetTimeout (osMessageQueueId_t mq_id); +#else +#define EvrRtxMessageQueueGetTimeout(mq_id) +#endif + +/** + \brief Event on successful message get (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] msg_ptr pointer to buffer for message to get from a queue. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RETRIEVED_DISABLE)) +extern void EvrRtxMessageQueueRetrieved (osMessageQueueId_t mq_id, void *msg_ptr); +#else +#define EvrRtxMessageQueueRetrieved(mq_id, msg_ptr) +#endif + +/** + \brief Event on unsuccessful message get (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] msg_ptr pointer to buffer for message to get from a queue. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NOT_RETRIEVED_DISABLE)) +extern void EvrRtxMessageQueueNotRetrieved (osMessageQueueId_t mq_id, void *msg_ptr); +#else +#define EvrRtxMessageQueueNotRetrieved(mq_id, msg_ptr) +#endif + +/** + \brief Event on message queue capacity retrieve (API) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] capacity maximum number of messages. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_CAPACITY_DISABLE)) +extern void EvrRtxMessageQueueGetCapacity (osMessageQueueId_t mq_id, uint32_t capacity); +#else +#define EvrRtxMessageQueueGetCapacity(mq_id, capacity) +#endif + +/** + \brief Event on message queue message size retrieve (API) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] msg_size maximum message size in bytes. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_MSG_SIZE_DISABLE)) +extern void EvrRtxMessageQueueGetMsgSize (osMessageQueueId_t mq_id, uint32_t msg_size); +#else +#define EvrRtxMessageQueueGetMsgSize(mq_id, msg_size) +#endif + +/** + \brief Event on message queue message count retrieve (API) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] count number of queued messages. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_COUNT_DISABLE)) +extern void EvrRtxMessageQueueGetCount (osMessageQueueId_t mq_id, uint32_t count); +#else +#define EvrRtxMessageQueueGetCount(mq_id, count) +#endif + +/** + \brief Event on message queue message slots retrieve (API) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. + \param[in] space number of available slots for messages. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_SPACE_DISABLE)) +extern void EvrRtxMessageQueueGetSpace (osMessageQueueId_t mq_id, uint32_t space); +#else +#define EvrRtxMessageQueueGetSpace(mq_id, space) +#endif + +/** + \brief Event on message queue reset (API) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RESET_DISABLE)) +extern void EvrRtxMessageQueueReset (osMessageQueueId_t mq_id); +#else +#define EvrRtxMessageQueueReset(mq_id) +#endif + +/** + \brief Event on successful message queue reset (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RESET_DONE_DISABLE)) +extern void EvrRtxMessageQueueResetDone (osMessageQueueId_t mq_id); +#else +#define EvrRtxMessageQueueResetDone(mq_id) +#endif + +/** + \brief Event on message queue delete (API) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_DELETE_DISABLE)) +extern void EvrRtxMessageQueueDelete (osMessageQueueId_t mq_id); +#else +#define EvrRtxMessageQueueDelete(mq_id) +#endif + +/** + \brief Event on successful message queue delete (Op) + \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +*/ +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_DESTROYED_DISABLE)) +extern void EvrRtxMessageQueueDestroyed (osMessageQueueId_t mq_id); +#else +#define EvrRtxMessageQueueDestroyed(mq_id) +#endif + + +#endif // RTX_EVR_H_ diff --git a/source/rtos2/RTX/Include/rtx_os.h b/source/rtos2/RTX/Include/rtx_os.h new file mode 100644 index 000000000..c54e2f230 --- /dev/null +++ b/source/rtos2/RTX/Include/rtx_os.h @@ -0,0 +1,472 @@ +/* + * Copyright (c) 2013-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: RTX OS definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_OS_H_ +#define RTX_OS_H_ + +#include +#include +#include "cmsis_os2.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/// Kernel Information +#define osRtxVersionAPI 20010003 ///< API version (2.1.3) +#define osRtxVersionKernel 50050002 ///< Kernel version (5.5.2) +#define osRtxKernelId "RTX V5.5.2" ///< Kernel identification string + + +// ==== Common definitions ==== + +/// Object Identifier definitions +#define osRtxIdInvalid 0x00U +#define osRtxIdThread 0xF1U +#define osRtxIdTimer 0xF2U +#define osRtxIdEventFlags 0xF3U +#define osRtxIdMutex 0xF5U +#define osRtxIdSemaphore 0xF6U +#define osRtxIdMemoryPool 0xF7U +#define osRtxIdMessage 0xF9U +#define osRtxIdMessageQueue 0xFAU + +/// Object Flags definitions +#define osRtxFlagSystemObject 0x01U +#define osRtxFlagSystemMemory 0x02U + + +// ==== Kernel definitions ==== + +/// Kernel State definitions +#define osRtxKernelInactive ((uint8_t)osKernelInactive) +#define osRtxKernelReady ((uint8_t)osKernelReady) +#define osRtxKernelRunning ((uint8_t)osKernelRunning) +#define osRtxKernelLocked ((uint8_t)osKernelLocked) +#define osRtxKernelSuspended ((uint8_t)osKernelSuspended) + + +// ==== Thread definitions ==== + +/// Thread State definitions (extending osThreadState) +#define osRtxThreadStateMask 0x0FU + +#define osRtxThreadInactive ((uint8_t)osThreadInactive) +#define osRtxThreadReady ((uint8_t)osThreadReady) +#define osRtxThreadRunning ((uint8_t)osThreadRunning) +#define osRtxThreadBlocked ((uint8_t)osThreadBlocked) +#define osRtxThreadTerminated ((uint8_t)osThreadTerminated) + +#define osRtxThreadWaitingDelay ((uint8_t)(osRtxThreadBlocked | 0x10U)) +#define osRtxThreadWaitingJoin ((uint8_t)(osRtxThreadBlocked | 0x20U)) +#define osRtxThreadWaitingThreadFlags ((uint8_t)(osRtxThreadBlocked | 0x30U)) +#define osRtxThreadWaitingEventFlags ((uint8_t)(osRtxThreadBlocked | 0x40U)) +#define osRtxThreadWaitingMutex ((uint8_t)(osRtxThreadBlocked | 0x50U)) +#define osRtxThreadWaitingSemaphore ((uint8_t)(osRtxThreadBlocked | 0x60U)) +#define osRtxThreadWaitingMemoryPool ((uint8_t)(osRtxThreadBlocked | 0x70U)) +#define osRtxThreadWaitingMessageGet ((uint8_t)(osRtxThreadBlocked | 0x80U)) +#define osRtxThreadWaitingMessagePut ((uint8_t)(osRtxThreadBlocked | 0x90U)) + +/// Thread Flags definitions +#define osRtxThreadFlagDefStack 0x10U ///< Default Stack flag + +/// Stack Marker definitions +#define osRtxStackMagicWord 0xE25A2EA5U ///< Stack Magic Word (Stack Base) +#define osRtxStackFillPattern 0xCCCCCCCCU ///< Stack Fill Pattern + +/// Thread Control Block +typedef struct osRtxThread_s { + uint8_t id; ///< Object Identifier + uint8_t state; ///< Object State + uint8_t flags; ///< Object Flags + uint8_t attr; ///< Object Attributes + const char *name; ///< Object Name + struct osRtxThread_s *thread_next; ///< Link pointer to next Thread in Object list + struct osRtxThread_s *thread_prev; ///< Link pointer to previous Thread in Object list + struct osRtxThread_s *delay_next; ///< Link pointer to next Thread in Delay list + struct osRtxThread_s *delay_prev; ///< Link pointer to previous Thread in Delay list + struct osRtxThread_s *thread_join; ///< Thread waiting to Join + uint32_t delay; ///< Delay Time + int8_t priority; ///< Thread Priority + int8_t priority_base; ///< Base Priority + uint8_t stack_frame; ///< Stack Frame (EXC_RETURN[7..0]) + uint8_t flags_options; ///< Thread/Event Flags Options + uint32_t wait_flags; ///< Waiting Thread/Event Flags + uint32_t thread_flags; ///< Thread Flags + struct osRtxMutex_s *mutex_list; ///< Link pointer to list of owned Mutexes + void *stack_mem; ///< Stack Memory + uint32_t stack_size; ///< Stack Size + uint32_t sp; ///< Current Stack Pointer + uint32_t thread_addr; ///< Thread entry address + uint32_t tz_memory; ///< TrustZone Memory Identifier +#ifdef RTX_TF_M_EXTENSION + uint32_t tz_module; ///< TrustZone Module Identifier +#endif +} osRtxThread_t; + + +// ==== Timer definitions ==== + +/// Timer State definitions +#define osRtxTimerInactive 0x00U ///< Timer Inactive +#define osRtxTimerStopped 0x01U ///< Timer Stopped +#define osRtxTimerRunning 0x02U ///< Timer Running + +/// Timer Type definitions +#define osRtxTimerPeriodic ((uint8_t)osTimerPeriodic) + +/// Timer Function Information +typedef struct { + osTimerFunc_t func; ///< Function Pointer + void *arg; ///< Function Argument +} osRtxTimerFinfo_t; + +/// Timer Control Block +typedef struct osRtxTimer_s { + uint8_t id; ///< Object Identifier + uint8_t state; ///< Object State + uint8_t flags; ///< Object Flags + uint8_t type; ///< Timer Type (Periodic/One-shot) + const char *name; ///< Object Name + struct osRtxTimer_s *prev; ///< Pointer to previous active Timer + struct osRtxTimer_s *next; ///< Pointer to next active Timer + uint32_t tick; ///< Timer current Tick + uint32_t load; ///< Timer Load value + osRtxTimerFinfo_t finfo; ///< Timer Function Info +} osRtxTimer_t; + + +// ==== Event Flags definitions ==== + +/// Event Flags Control Block +typedef struct { + uint8_t id; ///< Object Identifier + uint8_t reserved_state; ///< Object State (not used) + uint8_t flags; ///< Object Flags + uint8_t reserved; + const char *name; ///< Object Name + osRtxThread_t *thread_list; ///< Waiting Threads List + uint32_t event_flags; ///< Event Flags +} osRtxEventFlags_t; + + +// ==== Mutex definitions ==== + +/// Mutex Control Block +typedef struct osRtxMutex_s { + uint8_t id; ///< Object Identifier + uint8_t reserved_state; ///< Object State (not used) + uint8_t flags; ///< Object Flags + uint8_t attr; ///< Object Attributes + const char *name; ///< Object Name + osRtxThread_t *thread_list; ///< Waiting Threads List + osRtxThread_t *owner_thread; ///< Owner Thread + struct osRtxMutex_s *owner_prev; ///< Pointer to previous owned Mutex + struct osRtxMutex_s *owner_next; ///< Pointer to next owned Mutex + uint8_t lock; ///< Lock counter + uint8_t padding[3]; +} osRtxMutex_t; + + +// ==== Semaphore definitions ==== + +/// Semaphore Control Block +typedef struct { + uint8_t id; ///< Object Identifier + uint8_t reserved_state; ///< Object State (not used) + uint8_t flags; ///< Object Flags + uint8_t reserved; + const char *name; ///< Object Name + osRtxThread_t *thread_list; ///< Waiting Threads List + uint16_t tokens; ///< Current number of tokens + uint16_t max_tokens; ///< Maximum number of tokens +} osRtxSemaphore_t; + + +// ==== Memory Pool definitions ==== + +/// Memory Pool Information +typedef struct { + uint32_t max_blocks; ///< Maximum number of Blocks + uint32_t used_blocks; ///< Number of used Blocks + uint32_t block_size; ///< Block Size + void *block_base; ///< Block Memory Base Address + void *block_lim; ///< Block Memory Limit Address + void *block_free; ///< First free Block Address +} osRtxMpInfo_t; + +/// Memory Pool Control Block +typedef struct { + uint8_t id; ///< Object Identifier + uint8_t reserved_state; ///< Object State (not used) + uint8_t flags; ///< Object Flags + uint8_t reserved; + const char *name; ///< Object Name + osRtxThread_t *thread_list; ///< Waiting Threads List + osRtxMpInfo_t mp_info; ///< Memory Pool Info +} osRtxMemoryPool_t; + + +// ==== Message Queue definitions ==== + +/// Message Control Block +typedef struct osRtxMessage_s { + uint8_t id; ///< Object Identifier + uint8_t reserved_state; ///< Object State (not used) + uint8_t flags; ///< Object Flags + uint8_t priority; ///< Message Priority + struct osRtxMessage_s *prev; ///< Pointer to previous Message + struct osRtxMessage_s *next; ///< Pointer to next Message +} osRtxMessage_t; + +/// Message Queue Control Block +typedef struct { + uint8_t id; ///< Object Identifier + uint8_t reserved_state; ///< Object State (not used) + uint8_t flags; ///< Object Flags + uint8_t reserved; + const char *name; ///< Object Name + osRtxThread_t *thread_list; ///< Waiting Threads List + osRtxMpInfo_t mp_info; ///< Memory Pool Info + uint32_t msg_size; ///< Message Size + uint32_t msg_count; ///< Number of queued Messages + osRtxMessage_t *msg_first; ///< Pointer to first Message + osRtxMessage_t *msg_last; ///< Pointer to last Message +} osRtxMessageQueue_t; + + +// ==== Generic Object definitions ==== + +/// Generic Object Control Block +typedef struct { + uint8_t id; ///< Object Identifier + uint8_t state; ///< Object State + uint8_t flags; ///< Object Flags + uint8_t reserved; + const char *name; ///< Object Name + osRtxThread_t *thread_list; ///< Threads List +} osRtxObject_t; + + +// ==== OS Runtime Information definitions ==== + +/// OS Runtime Information structure +typedef struct { + const char *os_id; ///< OS Identification + uint32_t version; ///< OS Version + struct { ///< Kernel Info + uint8_t state; ///< State + volatile uint8_t blocked; ///< Blocked + uint8_t pendSV; ///< Pending SV + uint8_t reserved; + uint32_t tick; ///< Tick counter + } kernel; + int32_t tick_irqn; ///< Tick Timer IRQ Number + struct { ///< Thread Info + struct { ///< Thread Run Info + osRtxThread_t *curr; ///< Current running Thread + osRtxThread_t *next; ///< Next Thread to Run + } run; + osRtxObject_t ready; ///< Ready List Object + osRtxThread_t *idle; ///< Idle Thread + osRtxThread_t *delay_list; ///< Delay List + osRtxThread_t *wait_list; ///< Wait List (no Timeout) + osRtxThread_t *terminate_list; ///< Terminate Thread List + struct { ///< Thread Round Robin Info + osRtxThread_t *thread; ///< Round Robin Thread + uint32_t tick; ///< Round Robin Time Tick + uint32_t timeout; ///< Round Robin Timeout + } robin; + } thread; + struct { ///< Timer Info + osRtxTimer_t *list; ///< Active Timer List + osRtxThread_t *thread; ///< Timer Thread + osRtxMessageQueue_t *mq; ///< Timer Message Queue + void (*tick)(void); ///< Timer Tick Function + } timer; + struct { ///< ISR Post Processing Queue + uint16_t max; ///< Maximum Items + uint16_t cnt; ///< Item Count + uint16_t in; ///< Incoming Item Index + uint16_t out; ///< Outgoing Item Index + void **data; ///< Queue Data + } isr_queue; + struct { ///< ISR Post Processing functions + void (*thread)(osRtxThread_t*); ///< Thread Post Processing function + void (*event_flags)(osRtxEventFlags_t*); ///< Event Flags Post Processing function + void (*semaphore)(osRtxSemaphore_t*); ///< Semaphore Post Processing function + void (*memory_pool)(osRtxMemoryPool_t*); ///< Memory Pool Post Processing function + void (*message)(osRtxMessage_t*); ///< Message Post Processing function + } post_process; + struct { ///< Memory Pools (Variable Block Size) + void *stack; ///< Stack Memory + void *mp_data; ///< Memory Pool Data Memory + void *mq_data; ///< Message Queue Data Memory + void *common; ///< Common Memory + } mem; + struct { ///< Memory Pools (Fixed Block Size) + osRtxMpInfo_t *stack; ///< Stack for Threads + osRtxMpInfo_t *thread; ///< Thread Control Blocks + osRtxMpInfo_t *timer; ///< Timer Control Blocks + osRtxMpInfo_t *event_flags; ///< Event Flags Control Blocks + osRtxMpInfo_t *mutex; ///< Mutex Control Blocks + osRtxMpInfo_t *semaphore; ///< Semaphore Control Blocks + osRtxMpInfo_t *memory_pool; ///< Memory Pool Control Blocks + osRtxMpInfo_t *message_queue; ///< Message Queue Control Blocks + } mpi; +} osRtxInfo_t; + +extern osRtxInfo_t osRtxInfo; ///< OS Runtime Information + +/// OS Runtime Object Memory Usage structure +typedef struct { + uint32_t cnt_alloc; ///< Counter for alloc + uint32_t cnt_free; ///< Counter for free + uint32_t max_used; ///< Maximum used +} osRtxObjectMemUsage_t; + +/// OS Runtime Object Memory Usage variables +extern osRtxObjectMemUsage_t osRtxThreadMemUsage; +extern osRtxObjectMemUsage_t osRtxTimerMemUsage; +extern osRtxObjectMemUsage_t osRtxEventFlagsMemUsage; +extern osRtxObjectMemUsage_t osRtxMutexMemUsage; +extern osRtxObjectMemUsage_t osRtxSemaphoreMemUsage; +extern osRtxObjectMemUsage_t osRtxMemoryPoolMemUsage; +extern osRtxObjectMemUsage_t osRtxMessageQueueMemUsage; + + +// ==== OS API definitions ==== + +// Object Limits definitions +#define osRtxThreadFlagsLimit 31U ///< number of Thread Flags available per thread +#define osRtxEventFlagsLimit 31U ///< number of Event Flags available per object +#define osRtxMutexLockLimit 255U ///< maximum number of recursive mutex locks +#define osRtxSemaphoreTokenLimit 65535U ///< maximum number of tokens per semaphore + +// Control Block sizes +#define osRtxThreadCbSize sizeof(osRtxThread_t) +#define osRtxTimerCbSize sizeof(osRtxTimer_t) +#define osRtxEventFlagsCbSize sizeof(osRtxEventFlags_t) +#define osRtxMutexCbSize sizeof(osRtxMutex_t) +#define osRtxSemaphoreCbSize sizeof(osRtxSemaphore_t) +#define osRtxMemoryPoolCbSize sizeof(osRtxMemoryPool_t) +#define osRtxMessageQueueCbSize sizeof(osRtxMessageQueue_t) + +/// Memory size in bytes for Memory Pool storage. +/// \param block_count maximum number of memory blocks in memory pool. +/// \param block_size memory block size in bytes. +#define osRtxMemoryPoolMemSize(block_count, block_size) \ + (4*(block_count)*(((block_size)+3)/4)) + +/// Memory size in bytes for Message Queue storage. +/// \param msg_count maximum number of messages in queue. +/// \param msg_size maximum message size in bytes. +#define osRtxMessageQueueMemSize(msg_count, msg_size) \ + (4*(msg_count)*(3+(((msg_size)+3)/4))) + + +// ==== OS External Functions ==== + +// OS Error Codes +#define osRtxErrorStackUnderflow 1U ///< Stack overflow, i.e. stack pointer below its lower memory limit for descending stacks. +#define osRtxErrorISRQueueOverflow 2U ///< ISR Queue overflow detected when inserting object. +#define osRtxErrorTimerQueueOverflow 3U ///< User Timer Callback Queue overflow detected for timer. +#define osRtxErrorClibSpace 4U ///< Standard C/C++ library libspace not available: increase \c OS_THREAD_LIBSPACE_NUM. +#define osRtxErrorClibMutex 5U ///< Standard C/C++ library mutex initialization failed. + +/// OS Error Callback function +extern uint32_t osRtxErrorNotify (uint32_t code, void *object_id); + +/// OS Idle Thread +extern void osRtxIdleThread (void *argument); + +/// OS Exception handlers +extern void SVC_Handler (void); +extern void PendSV_Handler (void); +extern void SysTick_Handler (void); + +/// OS Trusted Firmware M Extension +#ifdef RTX_TF_M_EXTENSION +extern uint32_t osRtxTzGetModuleId (void); +#endif + + +// ==== OS External Configuration ==== + +/// OS Configuration flags +#define osRtxConfigPrivilegedMode (1UL<<0) ///< Threads in Privileged mode +#define osRtxConfigStackCheck (1UL<<1) ///< Stack overrun checking +#define osRtxConfigStackWatermark (1UL<<2) ///< Stack usage Watermark + +/// OS Configuration structure +typedef struct { + uint32_t flags; ///< OS Configuration Flags + uint32_t tick_freq; ///< Kernel Tick Frequency + uint32_t robin_timeout; ///< Round Robin Timeout Tick + struct { ///< ISR Post Processing Queue + void **data; ///< Queue Data + uint16_t max; ///< Maximum Items + uint16_t padding; + } isr_queue; + struct { ///< Memory Pools (Variable Block Size) + void *stack_addr; ///< Stack Memory Address + uint32_t stack_size; ///< Stack Memory Size + void *mp_data_addr; ///< Memory Pool Memory Address + uint32_t mp_data_size; ///< Memory Pool Memory Size + void *mq_data_addr; ///< Message Queue Data Memory Address + uint32_t mq_data_size; ///< Message Queue Data Memory Size + void *common_addr; ///< Common Memory Address + uint32_t common_size; ///< Common Memory Size + } mem; + struct { ///< Memory Pools (Fixed Block Size) + osRtxMpInfo_t *stack; ///< Stack for Threads + osRtxMpInfo_t *thread; ///< Thread Control Blocks + osRtxMpInfo_t *timer; ///< Timer Control Blocks + osRtxMpInfo_t *event_flags; ///< Event Flags Control Blocks + osRtxMpInfo_t *mutex; ///< Mutex Control Blocks + osRtxMpInfo_t *semaphore; ///< Semaphore Control Blocks + osRtxMpInfo_t *memory_pool; ///< Memory Pool Control Blocks + osRtxMpInfo_t *message_queue; ///< Message Queue Control Blocks + } mpi; + uint32_t thread_stack_size; ///< Default Thread Stack Size + const + osThreadAttr_t *idle_thread_attr; ///< Idle Thread Attributes + const + osThreadAttr_t *timer_thread_attr; ///< Timer Thread Attributes + const + osMessageQueueAttr_t *timer_mq_attr; ///< Timer Message Queue Attributes + uint32_t timer_mq_mcnt; ///< Timer Message Queue maximum Messages +} osRtxConfig_t; + +extern const osRtxConfig_t osRtxConfig; ///< OS Configuration + + +#ifdef __cplusplus +} +#endif + +#endif // RTX_OS_H_ diff --git a/source/rtos2/RTX/Source/ARM/irq_armv8mbl.s b/source/rtos2/RTX/Source/ARM/irq_armv8mbl.s new file mode 100644 index 000000000..28f7cb502 --- /dev/null +++ b/source/rtos2/RTX/Source/ARM/irq_armv8mbl.s @@ -0,0 +1,335 @@ +;/* +; * Copyright (c) 2016-2020 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; * ----------------------------------------------------------------------------- +; * +; * Project: CMSIS-RTOS RTX +; * Title: ARMv8M Baseline Exception handlers +; * +; * ----------------------------------------------------------------------------- +; */ + + + IF :LNOT::DEF:DOMAIN_NS +DOMAIN_NS EQU 0 + ENDIF + +I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset +TCB_SM_OFS EQU 48 ; TCB.stack_mem offset +TCB_SP_OFS EQU 56 ; TCB.SP offset +TCB_SF_OFS EQU 34 ; TCB.stack_frame offset +TCB_TZM_OFS EQU 64 ; TCB.tz_memory offset + + + PRESERVE8 + THUMB + + + AREA |.constdata|, DATA, READONLY + EXPORT irqRtxLib +irqRtxLib DCB 0 ; Non weak library reference + + + AREA |.text|, CODE, READONLY + + +SVC_Handler PROC + EXPORT SVC_Handler + IMPORT osRtxUserSVC + IMPORT osRtxInfo + IF :DEF:MPU_LOAD + IMPORT osRtxMpuLoad + ENDIF + IF DOMAIN_NS = 1 + IMPORT TZ_LoadContext_S + IMPORT TZ_StoreContext_S + ENDIF + + MOV R0,LR + LSRS R0,R0,#3 ; Determine return stack from EXC_RETURN bit 2 + BCC SVC_MSP ; Branch if return stack is MSP + MRS R0,PSP ; Get PSP + +SVC_Number + LDR R1,[R0,#24] ; Load saved PC from stack + SUBS R1,R1,#2 ; Point to SVC instruction + LDRB R1,[R1] ; Load SVC number + CMP R1,#0 + BNE SVC_User ; Branch if not SVC 0 + + PUSH {R0,LR} ; Save SP and EXC_RETURN + LDM R0,{R0-R3} ; Load function parameters from stack + BLX R7 ; Call service function + POP {R2,R3} ; Restore SP and EXC_RETURN + STMIA R2!,{R0-R1} ; Store function return values + MOV LR,R3 ; Set EXC_RETURN + +SVC_Context + LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run + LDMIA R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next + CMP R1,R2 ; Check if thread switch is required + BEQ SVC_Exit ; Branch when threads are the same + + CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted + +SVC_ContextSave + IF DOMAIN_NS = 1 + LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier + CBZ R0,SVC_ContextSave1 ; Branch if there is no secure context + PUSH {R1,R2,R3,R7} ; Save registers + MOV R7,LR ; Get EXC_RETURN + BL TZ_StoreContext_S ; Store secure context + MOV LR,R7 ; Set EXC_RETURN + POP {R1,R2,R3,R7} ; Restore registers + ENDIF + +SVC_ContextSave1 + MRS R0,PSP ; Get PSP + SUBS R0,R0,#32 ; Calculate SP + STR R0,[R1,#TCB_SP_OFS] ; Store SP + STMIA R0!,{R4-R7} ; Save R4..R7 + MOV R4,R8 + MOV R5,R9 + MOV R6,R10 + MOV R7,R11 + STMIA R0!,{R4-R7} ; Save R8..R11 + +SVC_ContextSave2 + MOV R0,LR ; Get EXC_RETURN + ADDS R1,R1,#TCB_SF_OFS ; Adjust address + STRB R0,[R1] ; Store stack frame information + +SVC_ContextSwitch + SUBS R3,R3,#8 ; Adjust address + STR R2,[R3] ; osRtxInfo.thread.run: curr = next + + IF :DEF:MPU_LOAD + PUSH {R2,R3} ; Save registers + MOV R0,R2 ; osRtxMpuLoad parameter + BL osRtxMpuLoad ; Load MPU for next thread + POP {R2,R3} ; Restore registers + ENDIF + +SVC_ContextRestore + IF DOMAIN_NS = 1 + LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier + CBZ R0,SVC_ContextRestore1 ; Branch if there is no secure context + PUSH {R2,R3} ; Save registers + BL TZ_LoadContext_S ; Load secure context + POP {R2,R3} ; Restore registers + ENDIF + +SVC_ContextRestore1 + MOV R1,R2 + ADDS R1,R1,#TCB_SF_OFS ; Adjust address + LDRB R0,[R1] ; Load stack frame information + MOVS R1,#0xFF + MVNS R1,R1 ; R1=0xFFFFFF00 + ORRS R0,R1 + MOV LR,R0 ; Set EXC_RETURN + + IF DOMAIN_NS = 1 + LSLS R0,R0,#25 ; Check domain of interrupted thread + BPL SVC_ContextRestore2 ; Branch if non-secure + LDR R0,[R2,#TCB_SP_OFS] ; Load SP + MSR PSP,R0 ; Set PSP + BX LR ; Exit from handler + ELSE + LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base + MSR PSPLIM,R0 ; Set PSPLIM + ENDIF + +SVC_ContextRestore2 + LDR R0,[R2,#TCB_SP_OFS] ; Load SP + ADDS R0,R0,#16 ; Adjust address + LDMIA R0!,{R4-R7} ; Restore R8..R11 + MOV R8,R4 + MOV R9,R5 + MOV R10,R6 + MOV R11,R7 + MSR PSP,R0 ; Set PSP + SUBS R0,R0,#32 ; Adjust address + LDMIA R0!,{R4-R7} ; Restore R4..R7 + +SVC_Exit + BX LR ; Exit from handler + +SVC_MSP + MRS R0,MSP ; Get MSP + B SVC_Number + +SVC_User + LDR R2,=osRtxUserSVC ; Load address of SVC table + LDR R3,[R2] ; Load SVC maximum number + CMP R1,R3 ; Check SVC number range + BHI SVC_Exit ; Branch if out of range + + PUSH {R0,LR} ; Save SP and EXC_RETURN + LSLS R1,R1,#2 + LDR R3,[R2,R1] ; Load address of SVC function + MOV R12,R3 + LDMIA R0,{R0-R3} ; Load function parameters from stack + BLX R12 ; Call service function + POP {R2,R3} ; Restore SP and EXC_RETURN + STR R0,[R2] ; Store function return value + MOV LR,R3 ; Set EXC_RETURN + + BX LR ; Return from handler + + ALIGN + ENDP + + +PendSV_Handler PROC + EXPORT PendSV_Handler + IMPORT osRtxPendSV_Handler + + PUSH {R0,LR} ; Save EXC_RETURN + BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler + POP {R0,R1} ; Restore EXC_RETURN + MOV LR,R1 ; Set EXC_RETURN + B Sys_Context + + ALIGN + ENDP + + +SysTick_Handler PROC + EXPORT SysTick_Handler + IMPORT osRtxTick_Handler + + PUSH {R0,LR} ; Save EXC_RETURN + BL osRtxTick_Handler ; Call osRtxTick_Handler + POP {R0,R1} ; Restore EXC_RETURN + MOV LR,R1 ; Set EXC_RETURN + B Sys_Context + + ALIGN + ENDP + + +Sys_Context PROC + EXPORT Sys_Context + IMPORT osRtxInfo + IF :DEF:MPU_LOAD + IMPORT osRtxMpuLoad + ENDIF + IF DOMAIN_NS = 1 + IMPORT TZ_LoadContext_S + IMPORT TZ_StoreContext_S + ENDIF + + LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run + LDM R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next + CMP R1,R2 ; Check if thread switch is required + BEQ Sys_ContextExit ; Branch when threads are the same + +Sys_ContextSave + IF DOMAIN_NS = 1 + LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier + CBZ R0,Sys_ContextSave1 ; Branch if there is no secure context + PUSH {R1,R2,R3,R7} ; Save registers + MOV R7,LR ; Get EXC_RETURN + BL TZ_StoreContext_S ; Store secure context + MOV LR,R7 ; Set EXC_RETURN + POP {R1,R2,R3,R7} ; Restore registers + +Sys_ContextSave1 + MOV R0,LR ; Get EXC_RETURN + LSLS R0,R0,#25 ; Check domain of interrupted thread + BPL Sys_ContextSave2 ; Branch if non-secure + MRS R0,PSP ; Get PSP + STR R0,[R1,#TCB_SP_OFS] ; Store SP + B Sys_ContextSave3 + ENDIF + +Sys_ContextSave2 + MRS R0,PSP ; Get PSP + SUBS R0,R0,#32 ; Adjust address + STR R0,[R1,#TCB_SP_OFS] ; Store SP + STMIA R0!,{R4-R7} ; Save R4..R7 + MOV R4,R8 + MOV R5,R9 + MOV R6,R10 + MOV R7,R11 + STMIA R0!,{R4-R7} ; Save R8..R11 + +Sys_ContextSave3 + MOV R0,LR ; Get EXC_RETURN + ADDS R1,R1,#TCB_SF_OFS ; Adjust address + STRB R0,[R1] ; Store stack frame information + +Sys_ContextSwitch + SUBS R3,R3,#8 ; Adjust address + STR R2,[R3] ; osRtxInfo.run: curr = next + + IF :DEF:MPU_LOAD + PUSH {R2,R3} ; Save registers + MOV R0,R2 ; osRtxMpuLoad parameter + BL osRtxMpuLoad ; Load MPU for next thread + POP {R2,R3} ; Restore registers + ENDIF + +Sys_ContextRestore + IF DOMAIN_NS = 1 + LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier + CBZ R0,Sys_ContextRestore1 ; Branch if there is no secure context + PUSH {R2,R3} ; Save registers + BL TZ_LoadContext_S ; Load secure context + POP {R2,R3} ; Restore registers + ENDIF + +Sys_ContextRestore1 + MOV R1,R2 + ADDS R1,R1,#TCB_SF_OFS ; Adjust offset + LDRB R0,[R1] ; Load stack frame information + MOVS R1,#0xFF + MVNS R1,R1 ; R1=0xFFFFFF00 + ORRS R0,R1 + MOV LR,R0 ; Set EXC_RETURN + + IF DOMAIN_NS = 1 + LSLS R0,R0,#25 ; Check domain of interrupted thread + BPL Sys_ContextRestore2 ; Branch if non-secure + LDR R0,[R2,#TCB_SP_OFS] ; Load SP + MSR PSP,R0 ; Set PSP + BX LR ; Exit from handler + ELSE + LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base + MSR PSPLIM,R0 ; Set PSPLIM + ENDIF + +Sys_ContextRestore2 + LDR R0,[R2,#TCB_SP_OFS] ; Load SP + ADDS R0,R0,#16 ; Adjust address + LDMIA R0!,{R4-R7} ; Restore R8..R11 + MOV R8,R4 + MOV R9,R5 + MOV R10,R6 + MOV R11,R7 + MSR PSP,R0 ; Set PSP + SUBS R0,R0,#32 ; Adjust address + LDMIA R0!,{R4-R7} ; Restore R4..R7 + +Sys_ContextExit + BX LR ; Exit from handler + + ALIGN + ENDP + + + END diff --git a/source/rtos2/RTX/Source/ARM/irq_armv8mbl_ns.s b/source/rtos2/RTX/Source/ARM/irq_armv8mbl_ns.s new file mode 100644 index 000000000..e94cb56db --- /dev/null +++ b/source/rtos2/RTX/Source/ARM/irq_armv8mbl_ns.s @@ -0,0 +1,3 @@ +DOMAIN_NS EQU 1 + INCLUDE irq_armv8mbl.s + END diff --git a/source/rtos2/RTX/Source/ARM/irq_armv8mml.s b/source/rtos2/RTX/Source/ARM/irq_armv8mml.s new file mode 100644 index 000000000..65cfc4e48 --- /dev/null +++ b/source/rtos2/RTX/Source/ARM/irq_armv8mml.s @@ -0,0 +1,308 @@ +;/* +; * Copyright (c) 2016-2020 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; * ----------------------------------------------------------------------------- +; * +; * Project: CMSIS-RTOS RTX +; * Title: ARMv8M Mainline Exception handlers +; * +; * ----------------------------------------------------------------------------- +; */ + + + IF :LNOT::DEF:DOMAIN_NS +DOMAIN_NS EQU 0 + ENDIF + + IF ({FPU}="FPv5-SP") || ({FPU}="FPv5_D16") +FPU_USED EQU 1 + ELSE +FPU_USED EQU 0 + ENDIF + +I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset +TCB_SM_OFS EQU 48 ; TCB.stack_mem offset +TCB_SP_OFS EQU 56 ; TCB.SP offset +TCB_SF_OFS EQU 34 ; TCB.stack_frame offset +TCB_TZM_OFS EQU 64 ; TCB.tz_memory offset + + + PRESERVE8 + THUMB + + + AREA |.constdata|, DATA, READONLY + EXPORT irqRtxLib +irqRtxLib DCB 0 ; Non weak library reference + + + AREA |.text|, CODE, READONLY + + +SVC_Handler PROC + EXPORT SVC_Handler + IMPORT osRtxUserSVC + IMPORT osRtxInfo + IF :DEF:MPU_LOAD + IMPORT osRtxMpuLoad + ENDIF + IF DOMAIN_NS = 1 + IMPORT TZ_LoadContext_S + IMPORT TZ_StoreContext_S + ENDIF + + TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2 + ITE EQ + MRSEQ R0,MSP ; Get MSP if return stack is MSP + MRSNE R0,PSP ; Get PSP if return stack is PSP + + LDR R1,[R0,#24] ; Load saved PC from stack + LDRB R1,[R1,#-2] ; Load SVC number + CMP R1,#0 + BNE SVC_User ; Branch if not SVC 0 + + PUSH {R0,LR} ; Save SP and EXC_RETURN + LDM R0,{R0-R3,R12} ; Load function parameters and address from stack + BLX R12 ; Call service function + POP {R12,LR} ; Restore SP and EXC_RETURN + STM R12,{R0-R1} ; Store function return values + +SVC_Context + LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run + LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next + CMP R1,R2 ; Check if thread switch is required + IT EQ + BXEQ LR ; Exit when threads are the same + + IF FPU_USED = 1 + CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted + TST LR,#0x10 ; Check if extended stack frame + BNE SVC_ContextSwitch + LDR R1,=0xE000EF34 ; FPCCR Address + LDR R0,[R1] ; Load FPCCR + BIC R0,R0,#1 ; Clear LSPACT (Lazy state) + STR R0,[R1] ; Store FPCCR + B SVC_ContextSwitch + ELSE + CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted + ENDIF + +SVC_ContextSave + IF DOMAIN_NS = 1 + LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier + CBZ R0,SVC_ContextSave1 ; Branch if there is no secure context + PUSH {R1,R2,R3,LR} ; Save registers and EXC_RETURN + BL TZ_StoreContext_S ; Store secure context + POP {R1,R2,R3,LR} ; Restore registers and EXC_RETURN + ENDIF + +SVC_ContextSave1 + MRS R0,PSP ; Get PSP + STMDB R0!,{R4-R11} ; Save R4..R11 + IF FPU_USED = 1 + TST LR,#0x10 ; Check if extended stack frame + IT EQ + VSTMDBEQ R0!,{S16-S31} ; Save VFP S16.S31 + ENDIF + +SVC_ContextSave2 + STR R0,[R1,#TCB_SP_OFS] ; Store SP + STRB LR,[R1,#TCB_SF_OFS] ; Store stack frame information + +SVC_ContextSwitch + STR R2,[R3] ; osRtxInfo.thread.run: curr = next + + IF :DEF:MPU_LOAD + PUSH {R2,R3} ; Save registers + MOV R0,R2 ; osRtxMpuLoad parameter + BL osRtxMpuLoad ; Load MPU for next thread + POP {R2,R3} ; Restore registers + ENDIF + +SVC_ContextRestore + IF DOMAIN_NS = 1 + LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier + CBZ R0,SVC_ContextRestore1 ; Branch if there is no secure context + PUSH {R2,R3} ; Save registers + BL TZ_LoadContext_S ; Load secure context + POP {R2,R3} ; Restore registers + ENDIF + +SVC_ContextRestore1 + LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base + LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information + MSR PSPLIM,R0 ; Set PSPLIM + LDR R0,[R2,#TCB_SP_OFS] ; Load SP + ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN + + IF DOMAIN_NS = 1 + TST LR,#0x40 ; Check domain of interrupted thread + BNE SVC_ContextRestore2 ; Branch if secure + ENDIF + + IF FPU_USED = 1 + TST LR,#0x10 ; Check if extended stack frame + IT EQ + VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 + ENDIF + LDMIA R0!,{R4-R11} ; Restore R4..R11 + +SVC_ContextRestore2 + MSR PSP,R0 ; Set PSP + +SVC_Exit + BX LR ; Exit from handler + +SVC_User + LDR R2,=osRtxUserSVC ; Load address of SVC table + LDR R3,[R2] ; Load SVC maximum number + CMP R1,R3 ; Check SVC number range + BHI SVC_Exit ; Branch if out of range + + PUSH {R0,LR} ; Save SP and EXC_RETURN + LDR R12,[R2,R1,LSL #2] ; Load address of SVC function + LDM R0,{R0-R3} ; Load function parameters from stack + BLX R12 ; Call service function + POP {R12,LR} ; Restore SP and EXC_RETURN + STR R0,[R12] ; Store function return value + + BX LR ; Return from handler + + ALIGN + ENDP + + +PendSV_Handler PROC + EXPORT PendSV_Handler + IMPORT osRtxPendSV_Handler + + PUSH {R0,LR} ; Save EXC_RETURN + BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler + POP {R0,LR} ; Restore EXC_RETURN + B Sys_Context + + ALIGN + ENDP + + +SysTick_Handler PROC + EXPORT SysTick_Handler + IMPORT osRtxTick_Handler + + PUSH {R0,LR} ; Save EXC_RETURN + BL osRtxTick_Handler ; Call osRtxTick_Handler + POP {R0,LR} ; Restore EXC_RETURN + B Sys_Context + + ALIGN + ENDP + + +Sys_Context PROC + EXPORT Sys_Context + IMPORT osRtxInfo + IF :DEF:MPU_LOAD + IMPORT osRtxMpuLoad + ENDIF + IF DOMAIN_NS = 1 + IMPORT TZ_LoadContext_S + IMPORT TZ_StoreContext_S + ENDIF + + LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run + LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next + CMP R1,R2 ; Check if thread switch is required + IT EQ + BXEQ LR ; Exit when threads are the same + +Sys_ContextSave + IF DOMAIN_NS = 1 + LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier + CBZ R0,Sys_ContextSave1 ; Branch if there is no secure context + PUSH {R1,R2,R3,LR} ; Save registers and EXC_RETURN + BL TZ_StoreContext_S ; Store secure context + POP {R1,R2,R3,LR} ; Restore registers and EXC_RETURN + +Sys_ContextSave1 + TST LR,#0x40 ; Check domain of interrupted thread + IT NE + MRSNE R0,PSP ; Get PSP + BNE Sys_ContextSave3 ; Branch if secure + ENDIF + +Sys_ContextSave2 + MRS R0,PSP ; Get PSP + STMDB R0!,{R4-R11} ; Save R4..R11 + IF FPU_USED = 1 + TST LR,#0x10 ; Check if extended stack frame + IT EQ + VSTMDBEQ R0!,{S16-S31} ; Save VFP S16.S31 + ENDIF + +Sys_ContextSave3 + STR R0,[R1,#TCB_SP_OFS] ; Store SP + STRB LR,[R1,#TCB_SF_OFS] ; Store stack frame information + +Sys_ContextSwitch + STR R2,[R3] ; osRtxInfo.run: curr = next + + IF :DEF:MPU_LOAD + PUSH {R2,R3} ; Save registers + MOV R0,R2 ; osRtxMpuLoad parameter + BL osRtxMpuLoad ; Load MPU for next thread + POP {R2,R3} ; Restore registers + ENDIF + +Sys_ContextRestore + IF DOMAIN_NS = 1 + LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier + CBZ R0,Sys_ContextRestore1 ; Branch if there is no secure context + PUSH {R2,R3} ; Save registers + BL TZ_LoadContext_S ; Load secure context + POP {R2,R3} ; Restore registers + ENDIF + +Sys_ContextRestore1 + LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base + LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information + MSR PSPLIM,R0 ; Set PSPLIM + LDR R0,[R2,#TCB_SP_OFS] ; Load SP + ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN + + IF DOMAIN_NS = 1 + TST LR,#0x40 ; Check domain of interrupted thread + BNE Sys_ContextRestore2 ; Branch if secure + ENDIF + + IF FPU_USED = 1 + TST LR,#0x10 ; Check if extended stack frame + IT EQ + VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 + ENDIF + LDMIA R0!,{R4-R11} ; Restore R4..R11 + +Sys_ContextRestore2 + MSR PSP,R0 ; Set PSP + +Sys_ContextExit + BX LR ; Exit from handler + + ALIGN + ENDP + + + END diff --git a/source/rtos2/RTX/Source/ARM/irq_armv8mml_ns.s b/source/rtos2/RTX/Source/ARM/irq_armv8mml_ns.s new file mode 100644 index 000000000..89a1414e2 --- /dev/null +++ b/source/rtos2/RTX/Source/ARM/irq_armv8mml_ns.s @@ -0,0 +1,3 @@ +DOMAIN_NS EQU 1 + INCLUDE irq_armv8mml.s + END diff --git a/source/rtos2/RTX/Source/ARM/irq_cm0.s b/source/rtos2/RTX/Source/ARM/irq_cm0.s new file mode 100644 index 000000000..c5146b3b8 --- /dev/null +++ b/source/rtos2/RTX/Source/ARM/irq_cm0.s @@ -0,0 +1,174 @@ +;/* +; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; * ----------------------------------------------------------------------------- +; * +; * Project: CMSIS-RTOS RTX +; * Title: Cortex-M0 Exception handlers +; * +; * ----------------------------------------------------------------------------- +; */ + + +I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset +TCB_SP_OFS EQU 56 ; TCB.SP offset + + + PRESERVE8 + THUMB + + + AREA |.constdata|, DATA, READONLY + EXPORT irqRtxLib +irqRtxLib DCB 0 ; Non weak library reference + + + AREA |.text|, CODE, READONLY + + +SVC_Handler PROC + EXPORT SVC_Handler + IMPORT osRtxUserSVC + IMPORT osRtxInfo + IF :DEF:MPU_LOAD + IMPORT osRtxMpuLoad + ENDIF + + MOV R0,LR + LSRS R0,R0,#3 ; Determine return stack from EXC_RETURN bit 2 + BCC SVC_MSP ; Branch if return stack is MSP + MRS R0,PSP ; Get PSP + +SVC_Number + LDR R1,[R0,#24] ; Load saved PC from stack + SUBS R1,R1,#2 ; Point to SVC instruction + LDRB R1,[R1] ; Load SVC number + CMP R1,#0 + BNE SVC_User ; Branch if not SVC 0 + + PUSH {R0,LR} ; Save SP and EXC_RETURN + LDMIA R0,{R0-R3} ; Load function parameters from stack + BLX R7 ; Call service function + POP {R2,R3} ; Restore SP and EXC_RETURN + STMIA R2!,{R0-R1} ; Store function return values + MOV LR,R3 ; Set EXC_RETURN + +SVC_Context + LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run + LDMIA R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next + CMP R1,R2 ; Check if thread switch is required + BEQ SVC_Exit ; Branch when threads are the same + + CMP R1,#0 + BEQ SVC_ContextSwitch ; Branch if running thread is deleted + +SVC_ContextSave + MRS R0,PSP ; Get PSP + SUBS R0,R0,#32 ; Calculate SP + STR R0,[R1,#TCB_SP_OFS] ; Store SP + STMIA R0!,{R4-R7} ; Save R4..R7 + MOV R4,R8 + MOV R5,R9 + MOV R6,R10 + MOV R7,R11 + STMIA R0!,{R4-R7} ; Save R8..R11 + +SVC_ContextSwitch + SUBS R3,R3,#8 ; Adjust address + STR R2,[R3] ; osRtxInfo.thread.run: curr = next + + IF :DEF:MPU_LOAD + PUSH {R2,R3} ; Save registers + MOV R0,R2 ; osRtxMpuLoad parameter + BL osRtxMpuLoad ; Load MPU for next thread + POP {R2,R3} ; Restore registers + ENDIF + +SVC_ContextRestore + LDR R0,[R2,#TCB_SP_OFS] ; Load SP + ADDS R0,R0,#16 ; Adjust address + LDMIA R0!,{R4-R7} ; Restore R8..R11 + MOV R8,R4 + MOV R9,R5 + MOV R10,R6 + MOV R11,R7 + MSR PSP,R0 ; Set PSP + SUBS R0,R0,#32 ; Adjust address + LDMIA R0!,{R4-R7} ; Restore R4..R7 + + MOVS R0,#~0xFFFFFFFD + MVNS R0,R0 ; Set EXC_RETURN value + BX R0 ; Exit from handler + +SVC_MSP + MRS R0,MSP ; Get MSP + B SVC_Number + +SVC_Exit + BX LR ; Exit from handler + +SVC_User + LDR R2,=osRtxUserSVC ; Load address of SVC table + LDR R3,[R2] ; Load SVC maximum number + CMP R1,R3 ; Check SVC number range + BHI SVC_Exit ; Branch if out of range + + PUSH {R0,LR} ; Save SP and EXC_RETURN + LSLS R1,R1,#2 + LDR R3,[R2,R1] ; Load address of SVC function + MOV R12,R3 + LDMIA R0,{R0-R3} ; Load function parameters from stack + BLX R12 ; Call service function + POP {R2,R3} ; Restore SP and EXC_RETURN + STR R0,[R2] ; Store function return value + MOV LR,R3 ; Set EXC_RETURN + + BX LR ; Return from handler + + ALIGN + ENDP + + +PendSV_Handler PROC + EXPORT PendSV_Handler + IMPORT osRtxPendSV_Handler + + PUSH {R0,LR} ; Save EXC_RETURN + BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler + POP {R0,R1} ; Restore EXC_RETURN + MOV LR,R1 ; Set EXC_RETURN + B SVC_Context + + ALIGN + ENDP + + +SysTick_Handler PROC + EXPORT SysTick_Handler + IMPORT osRtxTick_Handler + + PUSH {R0,LR} ; Save EXC_RETURN + BL osRtxTick_Handler ; Call osRtxTick_Handler + POP {R0,R1} ; Restore EXC_RETURN + MOV LR,R1 ; Set EXC_RETURN + B SVC_Context + + ALIGN + ENDP + + + END diff --git a/source/rtos2/RTX/Source/ARM/irq_cm3.s b/source/rtos2/RTX/Source/ARM/irq_cm3.s new file mode 100644 index 000000000..0a5ed3458 --- /dev/null +++ b/source/rtos2/RTX/Source/ARM/irq_cm3.s @@ -0,0 +1,146 @@ +;/* +; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; * ----------------------------------------------------------------------------- +; * +; * Project: CMSIS-RTOS RTX +; * Title: Cortex-M3 Exception handlers +; * +; * ----------------------------------------------------------------------------- +; */ + + +I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset +TCB_SP_OFS EQU 56 ; TCB.SP offset + + + PRESERVE8 + THUMB + + + AREA |.constdata|, DATA, READONLY + EXPORT irqRtxLib +irqRtxLib DCB 0 ; Non weak library reference + + + AREA |.text|, CODE, READONLY + + +SVC_Handler PROC + EXPORT SVC_Handler + IMPORT osRtxUserSVC + IMPORT osRtxInfo + IF :DEF:MPU_LOAD + IMPORT osRtxMpuLoad + ENDIF + + TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2 + ITE EQ + MRSEQ R0,MSP ; Get MSP if return stack is MSP + MRSNE R0,PSP ; Get PSP if return stack is PSP + + LDR R1,[R0,#24] ; Load saved PC from stack + LDRB R1,[R1,#-2] ; Load SVC number + CBNZ R1,SVC_User ; Branch if not SVC 0 + + PUSH {R0,LR} ; Save SP and EXC_RETURN + LDM R0,{R0-R3,R12} ; Load function parameters and address from stack + BLX R12 ; Call service function + POP {R12,LR} ; Restore SP and EXC_RETURN + STM R12,{R0-R1} ; Store function return values + +SVC_Context + LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run + LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next + CMP R1,R2 ; Check if thread switch is required + IT EQ + BXEQ LR ; Exit when threads are the same + + CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted + +SVC_ContextSave + STMDB R12!,{R4-R11} ; Save R4..R11 + STR R12,[R1,#TCB_SP_OFS] ; Store SP + +SVC_ContextSwitch + STR R2,[R3] ; osRtxInfo.thread.run: curr = next + + IF :DEF:MPU_LOAD + PUSH {R2,R3} ; Save registers + MOV R0,R2 ; osRtxMpuLoad parameter + BL osRtxMpuLoad ; Load MPU for next thread + POP {R2,R3} ; Restore registers + ENDIF + +SVC_ContextRestore + LDR R0,[R2,#TCB_SP_OFS] ; Load SP + LDMIA R0!,{R4-R11} ; Restore R4..R11 + MSR PSP,R0 ; Set PSP + + MVN LR,#~0xFFFFFFFD ; Set EXC_RETURN value + +SVC_Exit + BX LR ; Exit from handler + +SVC_User + LDR R2,=osRtxUserSVC ; Load address of SVC table + LDR R3,[R2] ; Load SVC maximum number + CMP R1,R3 ; Check SVC number range + BHI SVC_Exit ; Branch if out of range + + PUSH {R0,LR} ; Save SP and EXC_RETURN + LDR R12,[R2,R1,LSL #2] ; Load address of SVC function + LDM R0,{R0-R3} ; Load function parameters from stack + BLX R12 ; Call service function + POP {R12,LR} ; Restore SP and EXC_RETURN + STR R0,[R12] ; Store function return value + + BX LR ; Return from handler + + ALIGN + ENDP + + +PendSV_Handler PROC + EXPORT PendSV_Handler + IMPORT osRtxPendSV_Handler + + PUSH {R0,LR} ; Save EXC_RETURN + BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler + POP {R0,LR} ; Restore EXC_RETURN + MRS R12,PSP + B SVC_Context + + ALIGN + ENDP + + +SysTick_Handler PROC + EXPORT SysTick_Handler + IMPORT osRtxTick_Handler + + PUSH {R0,LR} ; Save EXC_RETURN + BL osRtxTick_Handler ; Call osRtxTick_Handler + POP {R0,LR} ; Restore EXC_RETURN + MRS R12,PSP + B SVC_Context + + ALIGN + ENDP + + + END diff --git a/source/rtos2/RTX/Source/ARM/irq_cm4f.s b/source/rtos2/RTX/Source/ARM/irq_cm4f.s new file mode 100644 index 000000000..7d405b7e4 --- /dev/null +++ b/source/rtos2/RTX/Source/ARM/irq_cm4f.s @@ -0,0 +1,162 @@ +;/* +; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; * ----------------------------------------------------------------------------- +; * +; * Project: CMSIS-RTOS RTX +; * Title: Cortex-M4F Exception handlers +; * +; * ----------------------------------------------------------------------------- +; */ + + +I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset +TCB_SP_OFS EQU 56 ; TCB.SP offset +TCB_SF_OFS EQU 34 ; TCB.stack_frame offset + + + PRESERVE8 + THUMB + + + AREA |.constdata|, DATA, READONLY + EXPORT irqRtxLib +irqRtxLib DCB 0 ; Non weak library reference + + + AREA |.text|, CODE, READONLY + + +SVC_Handler PROC + EXPORT SVC_Handler + IMPORT osRtxUserSVC + IMPORT osRtxInfo + IF :DEF:MPU_LOAD + IMPORT osRtxMpuLoad + ENDIF + + TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2 + ITE EQ + MRSEQ R0,MSP ; Get MSP if return stack is MSP + MRSNE R0,PSP ; Get PSP if return stack is PSP + + LDR R1,[R0,#24] ; Load saved PC from stack + LDRB R1,[R1,#-2] ; Load SVC number + CBNZ R1,SVC_User ; Branch if not SVC 0 + + PUSH {R0,LR} ; Save SP and EXC_RETURN + LDM R0,{R0-R3,R12} ; Load function parameters and address from stack + BLX R12 ; Call service function + POP {R12,LR} ; Restore SP and EXC_RETURN + STM R12,{R0-R1} ; Store function return values + +SVC_Context + LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run + LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next + CMP R1,R2 ; Check if thread switch is required + IT EQ + BXEQ LR ; Exit when threads are the same + + CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted + TST LR,#0x10 ; Check if extended stack frame + BNE SVC_ContextSwitch + LDR R1,=0xE000EF34 ; FPCCR Address + LDR R0,[R1] ; Load FPCCR + BIC R0,R0,#1 ; Clear LSPACT (Lazy state) + STR R0,[R1] ; Store FPCCR + B SVC_ContextSwitch + +SVC_ContextSave + STMDB R12!,{R4-R11} ; Save R4..R11 + TST LR,#0x10 ; Check if extended stack frame + IT EQ + VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31 + STR R12,[R1,#TCB_SP_OFS] ; Store SP + STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information + +SVC_ContextSwitch + STR R2,[R3] ; osRtxInfo.thread.run: curr = next + + IF :DEF:MPU_LOAD + PUSH {R2,R3} ; Save registers + MOV R0,R2 ; osRtxMpuLoad parameter + BL osRtxMpuLoad ; Load MPU for next thread + POP {R2,R3} ; Restore registers + ENDIF + +SVC_ContextRestore + LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information + LDR R0,[R2,#TCB_SP_OFS] ; Load SP + ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN + + TST LR,#0x10 ; Check if extended stack frame + IT EQ + VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 + LDMIA R0!,{R4-R11} ; Restore R4..R11 + MSR PSP,R0 ; Set PSP + +SVC_Exit + BX LR ; Exit from handler + +SVC_User + LDR R2,=osRtxUserSVC ; Load address of SVC table + LDR R3,[R2] ; Load SVC maximum number + CMP R1,R3 ; Check SVC number range + BHI SVC_Exit ; Branch if out of range + + PUSH {R0,LR} ; Save SP and EXC_RETURN + LDR R12,[R2,R1,LSL #2] ; Load address of SVC function + LDM R0,{R0-R3} ; Load function parameters from stack + BLX R12 ; Call service function + POP {R12,LR} ; Restore SP and EXC_RETURN + STR R0,[R12] ; Store function return value + + BX LR ; Return from handler + + ALIGN + ENDP + + +PendSV_Handler PROC + EXPORT PendSV_Handler + IMPORT osRtxPendSV_Handler + + PUSH {R0,LR} ; Save EXC_RETURN + BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler + POP {R0,LR} ; Restore EXC_RETURN + MRS R12,PSP + B SVC_Context + + ALIGN + ENDP + + +SysTick_Handler PROC + EXPORT SysTick_Handler + IMPORT osRtxTick_Handler + + PUSH {R0,LR} ; Save EXC_RETURN + BL osRtxTick_Handler ; Call osRtxTick_Handler + POP {R0,LR} ; Restore EXC_RETURN + MRS R12,PSP + B SVC_Context + + ALIGN + ENDP + + + END diff --git a/source/rtos2/RTX/Source/GCC/irq_armv8mbl.S b/source/rtos2/RTX/Source/GCC/irq_armv8mbl.S new file mode 100644 index 000000000..8f8f0d538 --- /dev/null +++ b/source/rtos2/RTX/Source/GCC/irq_armv8mbl.S @@ -0,0 +1,325 @@ +/* + * Copyright (c) 2016-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: ARMv8M Baseline Exception handlers + * + * ----------------------------------------------------------------------------- + */ + + + .syntax unified + + #ifdef _RTE_ + #include "RTE_Components.h" + #ifdef RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS + #define DOMAIN_NS 1 + #endif + #endif + + #ifndef DOMAIN_NS + #define DOMAIN_NS 0 + #endif + + .equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset + .equ TCB_SM_OFS, 48 // TCB.stack_mem offset + .equ TCB_SP_OFS, 56 // TCB.SP offset + .equ TCB_SF_OFS, 34 // TCB.stack_frame offset + .equ TCB_TZM_OFS, 64 // TCB.tz_memory offset + + .section ".rodata" + .global irqRtxLib // Non weak library reference +irqRtxLib: + .byte 0 + + + .thumb + .section ".text" + .align 2 + + + .thumb_func + .type SVC_Handler, %function + .global SVC_Handler + .fnstart + .cantunwind +SVC_Handler: + + MOV R0,LR + LSRS R0,R0,#3 // Determine return stack from EXC_RETURN bit 2 + BCC SVC_MSP // Branch if return stack is MSP + MRS R0,PSP // Get PSP + +SVC_Number: + LDR R1,[R0,#24] // Load saved PC from stack + SUBS R1,R1,#2 // Point to SVC instruction + LDRB R1,[R1] // Load SVC number + CMP R1,#0 + BNE SVC_User // Branch if not SVC 0 + + PUSH {R0,LR} // Save SP and EXC_RETURN + LDM R0,{R0-R3} // Load function parameters from stack + BLX R7 // Call service function + POP {R2,R3} // Restore SP and EXC_RETURN + STMIA R2!,{R0-R1} // Store function return values + MOV LR,R3 // Set EXC_RETURN + +SVC_Context: + LDR R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run + LDMIA R3!,{R1,R2} // Load osRtxInfo.thread.run: curr & next + CMP R1,R2 // Check if thread switch is required + BEQ SVC_Exit // Branch when threads are the same + + CBZ R1,SVC_ContextSwitch // Branch if running thread is deleted + +SVC_ContextSave: + #if (DOMAIN_NS == 1) + LDR R0,[R1,#TCB_TZM_OFS] // Load TrustZone memory identifier + CBZ R0,SVC_ContextSave1 // Branch if there is no secure context + PUSH {R1,R2,R3,R7} // Save registers + MOV R7,LR // Get EXC_RETURN + BL TZ_StoreContext_S // Store secure context + MOV LR,R7 // Set EXC_RETURN + POP {R1,R2,R3,R7} // Restore registers + #endif + +SVC_ContextSave1: + MRS R0,PSP // Get PSP + SUBS R0,R0,#32 // Calculate SP + STR R0,[R1,#TCB_SP_OFS] // Store SP + STMIA R0!,{R4-R7} // Save R4..R7 + MOV R4,R8 + MOV R5,R9 + MOV R6,R10 + MOV R7,R11 + STMIA R0!,{R4-R7} // Save R8..R11 + +SVC_ContextSave2: + MOV R0,LR // Get EXC_RETURN + ADDS R1,R1,#TCB_SF_OFS // Adjust address + STRB R0,[R1] // Store stack frame information + +SVC_ContextSwitch: + SUBS R3,R3,#8 // Adjust address + STR R2,[R3] // osRtxInfo.thread.run: curr = next + +SVC_ContextRestore: + #if (DOMAIN_NS == 1) + LDR R0,[R2,#TCB_TZM_OFS] // Load TrustZone memory identifier + CBZ R0,SVC_ContextRestore1 // Branch if there is no secure context + PUSH {R2,R3} // Save registers + BL TZ_LoadContext_S // Load secure context + POP {R2,R3} // Restore registers + #endif + +SVC_ContextRestore1: + MOV R1,R2 + ADDS R1,R1,#TCB_SF_OFS // Adjust address + LDRB R0,[R1] // Load stack frame information + MOVS R1,#0xFF + MVNS R1,R1 // R1=0xFFFFFF00 + ORRS R0,R1 + MOV LR,R0 // Set EXC_RETURN + + #if (DOMAIN_NS == 1) + LSLS R0,R0,#25 // Check domain of interrupted thread + BPL SVC_ContextRestore2 // Branch if non-secure + LDR R0,[R2,#TCB_SP_OFS] // Load SP + MSR PSP,R0 // Set PSP + BX LR // Exit from handler + #else + LDR R0,[R2,#TCB_SM_OFS] // Load stack memory base + MSR PSPLIM,R0 // Set PSPLIM + #endif + +SVC_ContextRestore2: + LDR R0,[R2,#TCB_SP_OFS] // Load SP + ADDS R0,R0,#16 // Adjust address + LDMIA R0!,{R4-R7} // Restore R8..R11 + MOV R8,R4 + MOV R9,R5 + MOV R10,R6 + MOV R11,R7 + MSR PSP,R0 // Set PSP + SUBS R0,R0,#32 // Adjust address + LDMIA R0!,{R4-R7} // Restore R4..R7 + +SVC_Exit: + BX LR // Exit from handler + +SVC_MSP: + MRS R0,MSP // Get MSP + B SVC_Number + +SVC_User: + LDR R2,=osRtxUserSVC // Load address of SVC table + LDR R3,[R2] // Load SVC maximum number + CMP R1,R3 // Check SVC number range + BHI SVC_Exit // Branch if out of range + + PUSH {R0,LR} // Save SP and EXC_RETURN + LSLS R1,R1,#2 + LDR R3,[R2,R1] // Load address of SVC function + MOV R12,R3 + LDMIA R0,{R0-R3} // Load function parameters from stack + BLX R12 // Call service function + POP {R2,R3} // Restore SP and EXC_RETURN + STR R0,[R2] // Store function return value + MOV LR,R3 // Set EXC_RETURN + + BX LR // Return from handler + + .fnend + .size SVC_Handler, .-SVC_Handler + + + .thumb_func + .type PendSV_Handler, %function + .global PendSV_Handler + .fnstart + .cantunwind +PendSV_Handler: + + PUSH {R0,LR} // Save EXC_RETURN + BL osRtxPendSV_Handler // Call osRtxPendSV_Handler + POP {R0,R1} // Restore EXC_RETURN + MOV LR,R1 // Set EXC_RETURN + B Sys_Context + + .fnend + .size PendSV_Handler, .-PendSV_Handler + + + .thumb_func + .type SysTick_Handler, %function + .global SysTick_Handler + .fnstart + .cantunwind +SysTick_Handler: + + PUSH {R0,LR} // Save EXC_RETURN + BL osRtxTick_Handler // Call osRtxTick_Handler + POP {R0,R1} // Restore EXC_RETURN + MOV LR,R1 // Set EXC_RETURN + B Sys_Context + + .fnend + .size SysTick_Handler, .-SysTick_Handler + + + .thumb_func + .type Sys_Context, %function + .global Sys_Context + .fnstart + .cantunwind +Sys_Context: + + LDR R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run + LDM R3!,{R1,R2} // Load osRtxInfo.thread.run: curr & next + CMP R1,R2 // Check if thread switch is required + BEQ Sys_ContextExit // Branch when threads are the same + +Sys_ContextSave: + #if (DOMAIN_NS == 1) + LDR R0,[R1,#TCB_TZM_OFS] // Load TrustZone memory identifier + CBZ R0,Sys_ContextSave1 // Branch if there is no secure context + PUSH {R1,R2,R3,R7} // Save registers + MOV R7,LR // Get EXC_RETURN + BL TZ_StoreContext_S // Store secure context + MOV LR,R7 // Set EXC_RETURN + POP {R1,R2,R3,R7} // Restore registers + +Sys_ContextSave1: + MOV R0,LR // Get EXC_RETURN + LSLS R0,R0,#25 // Check domain of interrupted thread + BPL Sys_ContextSave2 // Branch if non-secure + MRS R0,PSP // Get PSP + STR R0,[R1,#TCB_SP_OFS] // Store SP + B Sys_ContextSave3 + #endif + +Sys_ContextSave2: + MRS R0,PSP // Get PSP + SUBS R0,R0,#32 // Adjust address + STR R0,[R1,#TCB_SP_OFS] // Store SP + STMIA R0!,{R4-R7} // Save R4..R7 + MOV R4,R8 + MOV R5,R9 + MOV R6,R10 + MOV R7,R11 + STMIA R0!,{R4-R7} // Save R8..R11 + +Sys_ContextSave3: + MOV R0,LR // Get EXC_RETURN + ADDS R1,R1,#TCB_SF_OFS // Adjust address + STRB R0,[R1] // Store stack frame information + +Sys_ContextSwitch: + SUBS R3,R3,#8 // Adjust address + STR R2,[R3] // osRtxInfo.run: curr = next + +Sys_ContextRestore: + #if (DOMAIN_NS == 1) + LDR R0,[R2,#TCB_TZM_OFS] // Load TrustZone memory identifier + CBZ R0,Sys_ContextRestore1 // Branch if there is no secure context + PUSH {R2,R3} // Save registers + BL TZ_LoadContext_S // Load secure context + POP {R2,R3} // Restore registers + #endif + +Sys_ContextRestore1: + MOV R1,R2 + ADDS R1,R1,#TCB_SF_OFS // Adjust offset + LDRB R0,[R1] // Load stack frame information + MOVS R1,#0xFF + MVNS R1,R1 // R1=0xFFFFFF00 + ORRS R0,R1 + MOV LR,R0 // Set EXC_RETURN + + #if (DOMAIN_NS == 1) + LSLS R0,R0,#25 // Check domain of interrupted thread + BPL Sys_ContextRestore2 // Branch if non-secure + LDR R0,[R2,#TCB_SP_OFS] // Load SP + MSR PSP,R0 // Set PSP + BX LR // Exit from handler + #else + LDR R0,[R2,#TCB_SM_OFS] // Load stack memory base + MSR PSPLIM,R0 // Set PSPLIM + #endif + +Sys_ContextRestore2: + LDR R0,[R2,#TCB_SP_OFS] // Load SP + ADDS R0,R0,#16 // Adjust address + LDMIA R0!,{R4-R7} // Restore R8..R11 + MOV R8,R4 + MOV R9,R5 + MOV R10,R6 + MOV R11,R7 + MSR PSP,R0 // Set PSP + SUBS R0,R0,#32 // Adjust address + LDMIA R0!,{R4-R7} // Restore R4..R7 + +Sys_ContextExit: + BX LR // Exit from handler + + .fnend + .size Sys_Context, .-Sys_Context + + + .end diff --git a/source/rtos2/RTX/Source/GCC/irq_armv8mml.S b/source/rtos2/RTX/Source/GCC/irq_armv8mml.S new file mode 100644 index 000000000..0c7197213 --- /dev/null +++ b/source/rtos2/RTX/Source/GCC/irq_armv8mml.S @@ -0,0 +1,304 @@ +/* + * Copyright (c) 2016-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: ARMv8M Mainline Exception handlers + * + * ----------------------------------------------------------------------------- + */ + + + .syntax unified + + #ifdef _RTE_ + #include "RTE_Components.h" + #ifdef RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS + #define DOMAIN_NS 1 + #endif + #endif + + #ifndef DOMAIN_NS + #define DOMAIN_NS 0 + #endif + + #if (defined(__ARM_FP) && (__ARM_FP > 0)) + .equ FPU_USED, 1 + #else + .equ FPU_USED, 0 + #endif + + #if (defined(__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0)) + .equ MVE_USED, 1 + #else + .equ MVE_USED, 0 + #endif + + .equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset + .equ TCB_SM_OFS, 48 // TCB.stack_mem offset + .equ TCB_SP_OFS, 56 // TCB.SP offset + .equ TCB_SF_OFS, 34 // TCB.stack_frame offset + .equ TCB_TZM_OFS, 64 // TCB.tz_memory offset + + .section ".rodata" + .global irqRtxLib // Non weak library reference +irqRtxLib: + .byte 0 + + + .thumb + .section ".text" + .align 2 + + + .thumb_func + .type SVC_Handler, %function + .global SVC_Handler + .fnstart + .cantunwind +SVC_Handler: + + TST LR,#0x04 // Determine return stack from EXC_RETURN bit 2 + ITE EQ + MRSEQ R0,MSP // Get MSP if return stack is MSP + MRSNE R0,PSP // Get PSP if return stack is PSP + + LDR R1,[R0,#24] // Load saved PC from stack + LDRB R1,[R1,#-2] // Load SVC number + CMP R1,#0 + BNE SVC_User // Branch if not SVC 0 + + PUSH {R0,LR} // Save SP and EXC_RETURN + LDM R0,{R0-R3,R12} // Load function parameters and address from stack + BLX R12 // Call service function + POP {R12,LR} // Restore SP and EXC_RETURN + STM R12,{R0-R1} // Store function return values + +SVC_Context: + LDR R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run + LDM R3,{R1,R2} // Load osRtxInfo.thread.run: curr & next + CMP R1,R2 // Check if thread switch is required + IT EQ + BXEQ LR // Exit when threads are the same + + .if (FPU_USED == 1) || (MVE_USED == 1) + CBNZ R1,SVC_ContextSave // Branch if running thread is not deleted + TST LR,#0x10 // Check if extended stack frame + BNE SVC_ContextSwitch + LDR R1,=0xE000EF34 // FPCCR Address + LDR R0,[R1] // Load FPCCR + BIC R0,R0,#1 // Clear LSPACT (Lazy state) + STR R0,[R1] // Store FPCCR + B SVC_ContextSwitch + .else + CBZ R1,SVC_ContextSwitch // Branch if running thread is deleted + .endif + +SVC_ContextSave: + #if (DOMAIN_NS == 1) + LDR R0,[R1,#TCB_TZM_OFS] // Load TrustZone memory identifier + CBZ R0,SVC_ContextSave1 // Branch if there is no secure context + PUSH {R1,R2,R3,LR} // Save registers and EXC_RETURN + BL TZ_StoreContext_S // Store secure context + POP {R1,R2,R3,LR} // Restore registers and EXC_RETURN + #endif + +SVC_ContextSave1: + MRS R0,PSP // Get PSP + STMDB R0!,{R4-R11} // Save R4..R11 + .if (FPU_USED == 1) || (MVE_USED == 1) + TST LR,#0x10 // Check if extended stack frame + IT EQ + VSTMDBEQ R0!,{S16-S31} // Save VFP S16.S31 + .endif + +SVC_ContextSave2: + STR R0,[R1,#TCB_SP_OFS] // Store SP + STRB LR,[R1,#TCB_SF_OFS] // Store stack frame information + +SVC_ContextSwitch: + STR R2,[R3] // osRtxInfo.thread.run: curr = next + +SVC_ContextRestore: + #if (DOMAIN_NS == 1) + LDR R0,[R2,#TCB_TZM_OFS] // Load TrustZone memory identifier + CBZ R0,SVC_ContextRestore1 // Branch if there is no secure context + PUSH {R2,R3} // Save registers + BL TZ_LoadContext_S // Load secure context + POP {R2,R3} // Restore registers + #endif + +SVC_ContextRestore1: + LDR R0,[R2,#TCB_SM_OFS] // Load stack memory base + LDRB R1,[R2,#TCB_SF_OFS] // Load stack frame information + MSR PSPLIM,R0 // Set PSPLIM + LDR R0,[R2,#TCB_SP_OFS] // Load SP + ORR LR,R1,#0xFFFFFF00 // Set EXC_RETURN + + #if (DOMAIN_NS == 1) + TST LR,#0x40 // Check domain of interrupted thread + BNE SVC_ContextRestore2 // Branch if secure + #endif + + .if (FPU_USED == 1) || (MVE_USED == 1) + TST LR,#0x10 // Check if extended stack frame + IT EQ + VLDMIAEQ R0!,{S16-S31} // Restore VFP S16..S31 + .endif + LDMIA R0!,{R4-R11} // Restore R4..R11 + +SVC_ContextRestore2: + MSR PSP,R0 // Set PSP + +SVC_Exit: + BX LR // Exit from handler + +SVC_User: + LDR R2,=osRtxUserSVC // Load address of SVC table + LDR R3,[R2] // Load SVC maximum number + CMP R1,R3 // Check SVC number range + BHI SVC_Exit // Branch if out of range + + PUSH {R0,LR} // Save SP and EXC_RETURN + LDR R12,[R2,R1,LSL #2] // Load address of SVC function + LDM R0,{R0-R3} // Load function parameters from stack + BLX R12 // Call service function + POP {R12,LR} // Restore SP and EXC_RETURN + STR R0,[R12] // Store function return value + + BX LR // Return from handler + + .fnend + .size SVC_Handler, .-SVC_Handler + + + .thumb_func + .type PendSV_Handler, %function + .global PendSV_Handler + .fnstart + .cantunwind +PendSV_Handler: + + PUSH {R0,LR} // Save EXC_RETURN + BL osRtxPendSV_Handler // Call osRtxPendSV_Handler + POP {R0,LR} // Restore EXC_RETURN + B Sys_Context + + .fnend + .size PendSV_Handler, .-PendSV_Handler + + + .thumb_func + .type SysTick_Handler, %function + .global SysTick_Handler + .fnstart + .cantunwind +SysTick_Handler: + + PUSH {R0,LR} // Save EXC_RETURN + BL osRtxTick_Handler // Call osRtxTick_Handler + POP {R0,LR} // Restore EXC_RETURN + B Sys_Context + + .fnend + .size SysTick_Handler, .-SysTick_Handler + + + .thumb_func + .type Sys_Context, %function + .global Sys_Context + .fnstart + .cantunwind +Sys_Context: + + LDR R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run + LDM R3,{R1,R2} // Load osRtxInfo.thread.run: curr & next + CMP R1,R2 // Check if thread switch is required + IT EQ + BXEQ LR // Exit when threads are the same + +Sys_ContextSave: + #if (DOMAIN_NS == 1) + LDR R0,[R1,#TCB_TZM_OFS] // Load TrustZone memory identifier + CBZ R0,Sys_ContextSave1 // Branch if there is no secure context + PUSH {R1,R2,R3,LR} // Save registers and EXC_RETURN + BL TZ_StoreContext_S // Store secure context + POP {R1,R2,R3,LR} // Restore registers and EXC_RETURN + +Sys_ContextSave1: + TST LR,#0x40 // Check domain of interrupted thread + IT NE + MRSNE R0,PSP // Get PSP + BNE Sys_ContextSave3 // Branch if secure + #endif + +Sys_ContextSave2: + MRS R0,PSP // Get PSP + STMDB R0!,{R4-R11} // Save R4..R11 + .if (FPU_USED == 1) || (MVE_USED == 1) + TST LR,#0x10 // Check if extended stack frame + IT EQ + VSTMDBEQ R0!,{S16-S31} // Save VFP S16.S31 + .endif + +Sys_ContextSave3: + STR R0,[R1,#TCB_SP_OFS] // Store SP + STRB LR,[R1,#TCB_SF_OFS] // Store stack frame information + +Sys_ContextSwitch: + STR R2,[R3] // osRtxInfo.run: curr = next + +Sys_ContextRestore: + #if (DOMAIN_NS == 1) + LDR R0,[R2,#TCB_TZM_OFS] // Load TrustZone memory identifier + CBZ R0,Sys_ContextRestore1 // Branch if there is no secure context + PUSH {R2,R3} // Save registers + BL TZ_LoadContext_S // Load secure context + POP {R2,R3} // Restore registers + #endif + +Sys_ContextRestore1: + LDR R0,[R2,#TCB_SM_OFS] // Load stack memory base + LDRB R1,[R2,#TCB_SF_OFS] // Load stack frame information + MSR PSPLIM,R0 // Set PSPLIM + LDR R0,[R2,#TCB_SP_OFS] // Load SP + ORR LR,R1,#0xFFFFFF00 // Set EXC_RETURN + + #if (DOMAIN_NS == 1) + TST LR,#0x40 // Check domain of interrupted thread + BNE Sys_ContextRestore2 // Branch if secure + #endif + + .if (FPU_USED == 1) || (MVE_USED == 1) + TST LR,#0x10 // Check if extended stack frame + IT EQ + VLDMIAEQ R0!,{S16-S31} // Restore VFP S16..S31 + .endif + LDMIA R0!,{R4-R11} // Restore R4..R11 + +Sys_ContextRestore2: + MSR PSP,R0 // Set PSP + +Sys_ContextExit: + BX LR // Exit from handler + + .fnend + .size Sys_Context, .-Sys_Context + + + .end diff --git a/source/rtos2/RTX/Source/GCC/irq_cm0.S b/source/rtos2/RTX/Source/GCC/irq_cm0.S new file mode 100644 index 000000000..e261cd066 --- /dev/null +++ b/source/rtos2/RTX/Source/GCC/irq_cm0.S @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Cortex-M0 Exception handlers + * + * ----------------------------------------------------------------------------- + */ + + + .syntax unified + + .equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset + .equ TCB_SP_OFS, 56 // TCB.SP offset + + .section ".rodata" + .global irqRtxLib // Non weak library reference +irqRtxLib: + .byte 0 + + + .thumb + .section ".text" + .align 2 + + + .thumb_func + .type SVC_Handler, %function + .global SVC_Handler + .fnstart + .cantunwind +SVC_Handler: + + MOV R0,LR + LSRS R0,R0,#3 // Determine return stack from EXC_RETURN bit 2 + BCC SVC_MSP // Branch if return stack is MSP + MRS R0,PSP // Get PSP + +SVC_Number: + LDR R1,[R0,#24] // Load saved PC from stack + SUBS R1,R1,#2 // Point to SVC instruction + LDRB R1,[R1] // Load SVC number + CMP R1,#0 + BNE SVC_User // Branch if not SVC 0 + + PUSH {R0,LR} // Save SP and EXC_RETURN + LDMIA R0,{R0-R3} // Load function parameters from stack + BLX R7 // Call service function + POP {R2,R3} // Restore SP and EXC_RETURN + STMIA R2!,{R0-R1} // Store function return values + MOV LR,R3 // Set EXC_RETURN + +SVC_Context: + LDR R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run + LDMIA R3!,{R1,R2} // Load osRtxInfo.thread.run: curr & next + CMP R1,R2 // Check if thread switch is required + BEQ SVC_Exit // Branch when threads are the same + + CMP R1,#0 + BEQ SVC_ContextSwitch // Branch if running thread is deleted + +SVC_ContextSave: + MRS R0,PSP // Get PSP + SUBS R0,R0,#32 // Calculate SP + STR R0,[R1,#TCB_SP_OFS] // Store SP + STMIA R0!,{R4-R7} // Save R4..R7 + MOV R4,R8 + MOV R5,R9 + MOV R6,R10 + MOV R7,R11 + STMIA R0!,{R4-R7} // Save R8..R11 + +SVC_ContextSwitch: + SUBS R3,R3,#8 // Adjust address + STR R2,[R3] // osRtxInfo.thread.run: curr = next + +SVC_ContextRestore: + LDR R0,[R2,#TCB_SP_OFS] // Load SP + ADDS R0,R0,#16 // Adjust address + LDMIA R0!,{R4-R7} // Restore R8..R11 + MOV R8,R4 + MOV R9,R5 + MOV R10,R6 + MOV R11,R7 + MSR PSP,R0 // Set PSP + SUBS R0,R0,#32 // Adjust address + LDMIA R0!,{R4-R7} // Restore R4..R7 + + MOVS R0,#~0xFFFFFFFD + MVNS R0,R0 // Set EXC_RETURN value + BX R0 // Exit from handler + +SVC_MSP: + MRS R0,MSP // Get MSP + B SVC_Number + +SVC_Exit: + BX LR // Exit from handler + +SVC_User: + LDR R2,=osRtxUserSVC // Load address of SVC table + LDR R3,[R2] // Load SVC maximum number + CMP R1,R3 // Check SVC number range + BHI SVC_Exit // Branch if out of range + + PUSH {R0,LR} // Save SP and EXC_RETURN + LSLS R1,R1,#2 + LDR R3,[R2,R1] // Load address of SVC function + MOV R12,R3 + LDMIA R0,{R0-R3} // Load function parameters from stack + BLX R12 // Call service function + POP {R2,R3} // Restore SP and EXC_RETURN + STR R0,[R2] // Store function return value + MOV LR,R3 // Set EXC_RETURN + + BX LR // Return from handler + + .fnend + .size SVC_Handler, .-SVC_Handler + + + .thumb_func + .type PendSV_Handler, %function + .global PendSV_Handler + .fnstart + .cantunwind +PendSV_Handler: + + PUSH {R0,LR} // Save EXC_RETURN + BL osRtxPendSV_Handler // Call osRtxPendSV_Handler + POP {R0,R1} // Restore EXC_RETURN + MOV LR,R1 // Set EXC_RETURN + B SVC_Context + + .fnend + .size PendSV_Handler, .-PendSV_Handler + + + .thumb_func + .type SysTick_Handler, %function + .global SysTick_Handler + .fnstart + .cantunwind +SysTick_Handler: + + PUSH {R0,LR} // Save EXC_RETURN + BL osRtxTick_Handler // Call osRtxTick_Handler + POP {R0,R1} // Restore EXC_RETURN + MOV LR,R1 // Set EXC_RETURN + B SVC_Context + + .fnend + .size SysTick_Handler, .-SysTick_Handler + + + .end diff --git a/source/rtos2/RTX/Source/GCC/irq_cm3.S b/source/rtos2/RTX/Source/GCC/irq_cm3.S new file mode 100644 index 000000000..069bc9014 --- /dev/null +++ b/source/rtos2/RTX/Source/GCC/irq_cm3.S @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Cortex-M3 Exception handlers + * + * ----------------------------------------------------------------------------- + */ + + + .syntax unified + + .equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset + .equ TCB_SP_OFS, 56 // TCB.SP offset + + .section ".rodata" + .global irqRtxLib // Non weak library reference +irqRtxLib: + .byte 0 + + + .thumb + .section ".text" + .align 2 + + + .thumb_func + .type SVC_Handler, %function + .global SVC_Handler + .fnstart + .cantunwind +SVC_Handler: + + TST LR,#0x04 // Determine return stack from EXC_RETURN bit 2 + ITE EQ + MRSEQ R0,MSP // Get MSP if return stack is MSP + MRSNE R0,PSP // Get PSP if return stack is PSP + + LDR R1,[R0,#24] // Load saved PC from stack + LDRB R1,[R1,#-2] // Load SVC number + CBNZ R1,SVC_User // Branch if not SVC 0 + + PUSH {R0,LR} // Save SP and EXC_RETURN + LDM R0,{R0-R3,R12} // Load function parameters and address from stack + BLX R12 // Call service function + POP {R12,LR} // Restore SP and EXC_RETURN + STM R12,{R0-R1} // Store function return values + +SVC_Context: + LDR R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run + LDM R3,{R1,R2} // Load osRtxInfo.thread.run: curr & next + CMP R1,R2 // Check if thread switch is required + IT EQ + BXEQ LR // Exit when threads are the same + + CBZ R1,SVC_ContextSwitch // Branch if running thread is deleted + +SVC_ContextSave: + STMDB R12!,{R4-R11} // Save R4..R11 + STR R12,[R1,#TCB_SP_OFS] // Store SP + +SVC_ContextSwitch: + STR R2,[R3] // osRtxInfo.thread.run: curr = next + +SVC_ContextRestore: + LDR R0,[R2,#TCB_SP_OFS] // Load SP + LDMIA R0!,{R4-R11} // Restore R4..R11 + MSR PSP,R0 // Set PSP + MVN LR,#~0xFFFFFFFD // Set EXC_RETURN value + +SVC_Exit: + BX LR // Exit from handler + +SVC_User: + LDR R2,=osRtxUserSVC // Load address of SVC table + LDR R3,[R2] // Load SVC maximum number + CMP R1,R3 // Check SVC number range + BHI SVC_Exit // Branch if out of range + + PUSH {R0,LR} // Save SP and EXC_RETURN + LDR R12,[R2,R1,LSL #2] // Load address of SVC function + LDM R0,{R0-R3} // Load function parameters from stack + BLX R12 // Call service function + POP {R12,LR} // Restore SP and EXC_RETURN + STR R0,[R12] // Store function return value + + BX LR // Return from handler + + .fnend + .size SVC_Handler, .-SVC_Handler + + + .thumb_func + .type PendSV_Handler, %function + .global PendSV_Handler + .fnstart + .cantunwind +PendSV_Handler: + + PUSH {R0,LR} // Save EXC_RETURN + BL osRtxPendSV_Handler // Call osRtxPendSV_Handler + POP {R0,LR} // Restore EXC_RETURN + MRS R12,PSP + B SVC_Context + + .fnend + .size PendSV_Handler, .-PendSV_Handler + + + .thumb_func + .type SysTick_Handler, %function + .global SysTick_Handler + .fnstart + .cantunwind +SysTick_Handler: + + PUSH {R0,LR} // Save EXC_RETURN + BL osRtxTick_Handler // Call osRtxTick_Handler + POP {R0,LR} // Restore EXC_RETURN + MRS R12,PSP + B SVC_Context + + .fnend + .size SysTick_Handler, .-SysTick_Handler + + + .end diff --git a/source/rtos2/RTX/Source/GCC/irq_cm4f.S b/source/rtos2/RTX/Source/GCC/irq_cm4f.S new file mode 100644 index 000000000..e02990956 --- /dev/null +++ b/source/rtos2/RTX/Source/GCC/irq_cm4f.S @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Cortex-M4F Exception handlers + * + * ----------------------------------------------------------------------------- + */ + + + .syntax unified + + .equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset + .equ TCB_SP_OFS, 56 // TCB.SP offset + .equ TCB_SF_OFS, 34 // TCB.stack_frame offset + + .section ".rodata" + .global irqRtxLib // Non weak library reference +irqRtxLib: + .byte 0 + + + .thumb + .section ".text" + .align 2 + + + .thumb_func + .type SVC_Handler, %function + .global SVC_Handler + .fnstart + .cantunwind +SVC_Handler: + + TST LR,#0x04 // Determine return stack from EXC_RETURN bit 2 + ITE EQ + MRSEQ R0,MSP // Get MSP if return stack is MSP + MRSNE R0,PSP // Get PSP if return stack is PSP + + LDR R1,[R0,#24] // Load saved PC from stack + LDRB R1,[R1,#-2] // Load SVC number + CBNZ R1,SVC_User // Branch if not SVC 0 + + PUSH {R0,LR} // Save SP and EXC_RETURN + LDM R0,{R0-R3,R12} // Load function parameters and address from stack + BLX R12 // Call service function + POP {R12,LR} // Restore SP and EXC_RETURN + STM R12,{R0-R1} // Store function return values + +SVC_Context: + LDR R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run + LDM R3,{R1,R2} // Load osRtxInfo.thread.run: curr & next + CMP R1,R2 // Check if thread switch is required + IT EQ + BXEQ LR // Exit when threads are the same + + CBNZ R1,SVC_ContextSave // Branch if running thread is not deleted + TST LR,#0x10 // Check if extended stack frame + BNE SVC_ContextSwitch + LDR R1,=0xE000EF34 // FPCCR Address + LDR R0,[R1] // Load FPCCR + BIC R0,R0,#1 // Clear LSPACT (Lazy state) + STR R0,[R1] // Store FPCCR + B SVC_ContextSwitch + +SVC_ContextSave: + STMDB R12!,{R4-R11} // Save R4..R11 + TST LR,#0x10 // Check if extended stack frame + IT EQ + VSTMDBEQ R12!,{S16-S31} // Save VFP S16.S31 + STR R12,[R1,#TCB_SP_OFS] // Store SP + STRB LR, [R1,#TCB_SF_OFS] // Store stack frame information + +SVC_ContextSwitch: + STR R2,[R3] // osRtxInfo.thread.run: curr = next + +SVC_ContextRestore: + LDRB R1,[R2,#TCB_SF_OFS] // Load stack frame information + LDR R0,[R2,#TCB_SP_OFS] // Load SP + ORR LR,R1,#0xFFFFFF00 // Set EXC_RETURN + + TST LR,#0x10 // Check if extended stack frame + IT EQ + VLDMIAEQ R0!,{S16-S31} // Restore VFP S16..S31 + LDMIA R0!,{R4-R11} // Restore R4..R11 + MSR PSP,R0 // Set PSP + +SVC_Exit: + BX LR // Exit from handler + +SVC_User: + LDR R2,=osRtxUserSVC // Load address of SVC table + LDR R3,[R2] // Load SVC maximum number + CMP R1,R3 // Check SVC number range + BHI SVC_Exit // Branch if out of range + + PUSH {R0,LR} // Save SP and EXC_RETURN + LDR R12,[R2,R1,LSL #2] // Load address of SVC function + LDM R0,{R0-R3} // Load function parameters from stack + BLX R12 // Call service function + POP {R12,LR} // Restore SP and EXC_RETURN + STR R0,[R12] // Store function return value + + BX LR // Return from handler + + .fnend + .size SVC_Handler, .-SVC_Handler + + + .thumb_func + .type PendSV_Handler, %function + .global PendSV_Handler + .fnstart + .cantunwind +PendSV_Handler: + + PUSH {R0,LR} // Save EXC_RETURN + BL osRtxPendSV_Handler // Call osRtxPendSV_Handler + POP {R0,LR} // Restore EXC_RETURN + MRS R12,PSP + B SVC_Context + + .fnend + .size PendSV_Handler, .-PendSV_Handler + + + .thumb_func + .type SysTick_Handler, %function + .global SysTick_Handler + .fnstart + .cantunwind +SysTick_Handler: + + PUSH {R0,LR} // Save EXC_RETURN + BL osRtxTick_Handler // Call osRtxTick_Handler + POP {R0,LR} // Restore EXC_RETURN + MRS R12,PSP + B SVC_Context + + .fnend + .size SysTick_Handler, .-SysTick_Handler + + + .end diff --git a/source/rtos2/RTX/Source/rtx_core_c.h b/source/rtos2/RTX/Source/rtx_core_c.h new file mode 100644 index 000000000..445d393c9 --- /dev/null +++ b/source/rtos2/RTX/Source/rtx_core_c.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Cortex Core definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CORE_C_H_ +#define RTX_CORE_C_H_ + +//lint -emacro((923,9078),SCB) "cast from unsigned long to pointer" [MISRA Note 9] +#include "RTE_Components.h" +#include CMSIS_device_header + +#if ((!defined(__ARM_ARCH_6M__)) && \ + (!defined(__ARM_ARCH_7A__)) && \ + (!defined(__ARM_ARCH_7M__)) && \ + (!defined(__ARM_ARCH_7EM__)) && \ + (!defined(__ARM_ARCH_8M_BASE__)) && \ + (!defined(__ARM_ARCH_8M_MAIN__)) && \ + (!defined(__ARM_ARCH_8_1M_MAIN__))) +#error "Unknown Arm Architecture!" +#endif + +#if (defined(__ARM_ARCH_7A__) && (__ARM_ARCH_7A__ != 0)) +#include "rtx_core_ca.h" +#else +#include "rtx_core_cm.h" +#endif + +#endif // RTX_CORE_C_H_ diff --git a/source/rtos2/RTX/Source/rtx_core_cm.h b/source/rtos2/RTX/Source/rtx_core_cm.h new file mode 100644 index 000000000..9bd0c8867 --- /dev/null +++ b/source/rtos2/RTX/Source/rtx_core_cm.h @@ -0,0 +1,1215 @@ +/* + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Cortex-M Core definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CORE_CM_H_ +#define RTX_CORE_CM_H_ + +#ifndef RTX_CORE_C_H_ +#include "RTE_Components.h" +#include CMSIS_device_header +#endif + +#include +typedef bool bool_t; + +#ifndef FALSE +#define FALSE ((bool_t)0) +#endif + +#ifndef TRUE +#define TRUE ((bool_t)1) +#endif + +#ifdef RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS +#define DOMAIN_NS 1 +#endif + +#ifndef DOMAIN_NS +#define DOMAIN_NS 0 +#endif + +#if (DOMAIN_NS == 1) +#if ((!defined(__ARM_ARCH_8M_BASE__) || (__ARM_ARCH_8M_BASE__ == 0)) && \ + (!defined(__ARM_ARCH_8M_MAIN__) || (__ARM_ARCH_8M_MAIN__ == 0)) && \ + (!defined(__ARM_ARCH_8_1M_MAIN__) || (__ARM_ARCH_8_1M_MAIN__ == 0))) +#error "Non-secure domain requires ARMv8-M Architecture!" +#endif +#endif + +#ifndef EXCLUSIVE_ACCESS +#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0))) +#define EXCLUSIVE_ACCESS 1 +#else +#define EXCLUSIVE_ACCESS 0 +#endif +#endif + +#define OS_TICK_HANDLER SysTick_Handler + +/// xPSR_Initialization Value +/// \param[in] privileged true=privileged, false=unprivileged +/// \param[in] thumb true=Thumb, false=ARM +/// \return xPSR Init Value +__STATIC_INLINE uint32_t xPSR_InitVal (bool_t privileged, bool_t thumb) { + (void)privileged; + (void)thumb; + return (0x01000000U); +} + +// Stack Frame: +// - Extended: S16-S31, R4-R11, R0-R3, R12, LR, PC, xPSR, S0-S15, FPSCR +// - Basic: R4-R11, R0-R3, R12, LR, PC, xPSR + +/// Stack Frame Initialization Value (EXC_RETURN[7..0]) +#if (DOMAIN_NS == 1) +#define STACK_FRAME_INIT_VAL 0xBCU +#else +#define STACK_FRAME_INIT_VAL 0xFDU +#endif + +/// Stack Offset of Register R0 +/// \param[in] stack_frame Stack Frame (EXC_RETURN[7..0]) +/// \return R0 Offset +__STATIC_INLINE uint32_t StackOffsetR0 (uint8_t stack_frame) { +#if ((__FPU_USED == 1U) || \ + (defined(__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) + return (((stack_frame & 0x10U) == 0U) ? ((16U+8U)*4U) : (8U*4U)); +#else + (void)stack_frame; + return (8U*4U); +#endif +} + + +// ==== Core functions ==== + +//lint -sem(__get_CONTROL, pure) +//lint -sem(__get_IPSR, pure) +//lint -sem(__get_PRIMASK, pure) +//lint -sem(__get_BASEPRI, pure) + +/// Check if running Privileged +/// \return true=privileged, false=unprivileged +__STATIC_INLINE bool_t IsPrivileged (void) { + return ((__get_CONTROL() & 1U) == 0U); +} + +/// Check if in IRQ Mode +/// \return true=IRQ, false=thread +__STATIC_INLINE bool_t IsIrqMode (void) { + return (__get_IPSR() != 0U); +} + +/// Check if IRQ is Masked +/// \return true=masked, false=not masked +__STATIC_INLINE bool_t IsIrqMasked (void) { +#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0))) + return ((__get_PRIMASK() != 0U) || (__get_BASEPRI() != 0U)); +#else + return (__get_PRIMASK() != 0U); +#endif +} + + +// ==== Core Peripherals functions ==== + +/// Setup SVC and PendSV System Service Calls +__STATIC_INLINE void SVC_Setup (void) { +#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)) || \ + (defined(__CORTEX_M) && (__CORTEX_M == 7U))) + uint32_t p, n; + + SCB->SHPR[10] = 0xFFU; + n = 32U - (uint32_t)__CLZ(~(SCB->SHPR[10] | 0xFFFFFF00U)); + p = NVIC_GetPriorityGrouping(); + if (p >= n) { + n = p + 1U; + } + SCB->SHPR[7] = (uint8_t)(0xFEU << n); +#elif (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + uint32_t n; + + SCB->SHPR[1] |= 0x00FF0000U; + n = SCB->SHPR[1]; + SCB->SHPR[0] |= (n << (8+1)) & 0xFC000000U; +#elif ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0))) + uint32_t p, n; + + SCB->SHP[10] = 0xFFU; + n = 32U - (uint32_t)__CLZ(~(SCB->SHP[10] | 0xFFFFFF00U)); + p = NVIC_GetPriorityGrouping(); + if (p >= n) { + n = p + 1U; + } + SCB->SHP[7] = (uint8_t)(0xFEU << n); +#elif (defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) + uint32_t n; + + SCB->SHP[1] |= 0x00FF0000U; + n = SCB->SHP[1]; + SCB->SHP[0] |= (n << (8+1)) & 0xFC000000U; +#endif +} + +/// Get Pending SV (Service Call) Flag +/// \return Pending SV Flag +__STATIC_INLINE uint8_t GetPendSV (void) { + return ((uint8_t)((SCB->ICSR & (SCB_ICSR_PENDSVSET_Msk)) >> 24)); +} + +/// Clear Pending SV (Service Call) Flag +__STATIC_INLINE void ClrPendSV (void) { + SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk; +} + +/// Set Pending SV (Service Call) Flag +__STATIC_INLINE void SetPendSV (void) { + SCB->ICSR = SCB_ICSR_PENDSVSET_Msk; +} + + +// ==== Service Calls definitions ==== + +//lint -save -e9023 -e9024 -e9026 "Function-like macros using '#/##'" [MISRA Note 10] + +#if defined(__CC_ARM) + +#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0))) +#define __SVC_INDIRECT(n) __svc_indirect(n) +#elif ((defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))) +#define __SVC_INDIRECT(n) __svc_indirect_r7(n) +#endif + +#define SVC0_0N(f,t) \ +__SVC_INDIRECT(0) t svc##f (t(*)()); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + svc##f(svcRtx##f); \ +} + +#define SVC0_0(f,t) \ +__SVC_INDIRECT(0) t svc##f (t(*)()); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + return svc##f(svcRtx##f); \ +} + +#define SVC0_1N(f,t,t1) \ +__SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + svc##f(svcRtx##f,a1); \ +} + +#define SVC0_1(f,t,t1) \ +__SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + return svc##f(svcRtx##f,a1); \ +} + +#define SVC0_2(f,t,t1,t2) \ +__SVC_INDIRECT(0) t svc##f (t(*)(t1,t2),t1,t2); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \ + return svc##f(svcRtx##f,a1,a2); \ +} + +#define SVC0_3(f,t,t1,t2,t3) \ +__SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3),t1,t2,t3); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \ + return svc##f(svcRtx##f,a1,a2,a3); \ +} + +#define SVC0_4(f,t,t1,t2,t3,t4) \ +__SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ + return svc##f(svcRtx##f,a1,a2,a3,a4); \ +} + +#elif defined(__ICCARM__) + +#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0))) +#define SVC_ArgF(f) \ + __asm( \ + "mov r12,%0\n" \ + :: "r"(&f): "r12" \ + ); +#elif ((defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))) +#define SVC_ArgF(f) \ + __asm( \ + "mov r7,%0\n" \ + :: "r"(&f): "r7" \ + ); +#endif + +#define STRINGIFY(a) #a +#define __SVC_INDIRECT(n) _Pragma(STRINGIFY(swi_number = n)) __swi + +#define SVC0_0N(f,t) \ +__SVC_INDIRECT(0) t svc##f (); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + SVC_ArgF(svcRtx##f); \ + svc##f(); \ +} + +#define SVC0_0(f,t) \ +__SVC_INDIRECT(0) t svc##f (); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + SVC_ArgF(svcRtx##f); \ + return svc##f(); \ +} + +#define SVC0_1N(f,t,t1) \ +__SVC_INDIRECT(0) t svc##f (t1 a1); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + SVC_ArgF(svcRtx##f); \ + svc##f(a1); \ +} + +#define SVC0_1(f,t,t1) \ +__SVC_INDIRECT(0) t svc##f (t1 a1); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + SVC_ArgF(svcRtx##f); \ + return svc##f(a1); \ +} + +#define SVC0_2(f,t,t1,t2) \ +__SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \ + SVC_ArgF(svcRtx##f); \ + return svc##f(a1,a2); \ +} + +#define SVC0_3(f,t,t1,t2,t3) \ +__SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \ + SVC_ArgF(svcRtx##f); \ + return svc##f(a1,a2,a3); \ +} + +#define SVC0_4(f,t,t1,t2,t3,t4) \ +__SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3, t4 a4); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ + SVC_ArgF(svcRtx##f); \ + return svc##f(a1,a2,a3,a4); \ +} + +#else // !(defined(__CC_ARM) || defined(__ICCARM__)) + +//lint -esym(522,__svc*) "Functions '__svc*' are impure (side-effects)" + +#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0))) +#define SVC_RegF "r12" +#elif ((defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))) +#define SVC_RegF "r7" +#endif + +#define SVC_ArgN(n) \ +register uint32_t __r##n __ASM("r"#n) + +#define SVC_ArgR(n,a) \ +register uint32_t __r##n __ASM("r"#n) = (uint32_t)a + +#define SVC_ArgF(f) \ +register uint32_t __rf __ASM(SVC_RegF) = (uint32_t)f + +#define SVC_In0 "r"(__rf) +#define SVC_In1 "r"(__rf),"r"(__r0) +#define SVC_In2 "r"(__rf),"r"(__r0),"r"(__r1) +#define SVC_In3 "r"(__rf),"r"(__r0),"r"(__r1),"r"(__r2) +#define SVC_In4 "r"(__rf),"r"(__r0),"r"(__r1),"r"(__r2),"r"(__r3) + +#define SVC_Out0 +#define SVC_Out1 "=r"(__r0) + +#define SVC_CL0 +#define SVC_CL1 "r1" +#define SVC_CL2 "r0","r1" + +#define SVC_Call0(in, out, cl) \ + __ASM volatile ("svc 0" : out : in : cl) + +#define SVC0_0N(f,t) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In0, SVC_Out0, SVC_CL2); \ +} + +#define SVC0_0(f,t) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + SVC_ArgN(0); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In0, SVC_Out1, SVC_CL1); \ + return (t) __r0; \ +} + +#define SVC0_1N(f,t,t1) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + SVC_ArgR(0,a1); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In1, SVC_Out0, SVC_CL1); \ +} + +#define SVC0_1(f,t,t1) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + SVC_ArgR(0,a1); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In1, SVC_Out1, SVC_CL1); \ + return (t) __r0; \ +} + +#define SVC0_2(f,t,t1,t2) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \ + SVC_ArgR(0,a1); \ + SVC_ArgR(1,a2); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In2, SVC_Out1, SVC_CL0); \ + return (t) __r0; \ +} + +#define SVC0_3(f,t,t1,t2,t3) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \ + SVC_ArgR(0,a1); \ + SVC_ArgR(1,a2); \ + SVC_ArgR(2,a3); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In3, SVC_Out1, SVC_CL0); \ + return (t) __r0; \ +} + +#define SVC0_4(f,t,t1,t2,t3,t4) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ + SVC_ArgR(0,a1); \ + SVC_ArgR(1,a2); \ + SVC_ArgR(2,a3); \ + SVC_ArgR(3,a4); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In4, SVC_Out1, SVC_CL0); \ + return (t) __r0; \ +} + +#endif + +//lint -restore [MISRA Note 10] + + +// ==== Exclusive Access Operation ==== + +#if (EXCLUSIVE_ACCESS == 1) + +//lint ++flb "Library Begin" [MISRA Note 12] + +/// Atomic Access Operation: Write (8-bit) +/// \param[in] mem Memory address +/// \param[in] val Value to write +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) { + mov r2,r0 +1 + ldrexb r0,[r2] + strexb r3,r1,[r2] + cbz r3,%F2 + b %B1 +2 + bx lr +} +#else +__STATIC_INLINE uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint8_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrexb %[ret],[%[mem]]\n\t" + "strexb %[res],%[val],[%[mem]]\n\t" + "cbz %[res],2f\n\t" + "b 1b\n" + "2:" + : [ret] "=&l" (ret), + [res] "=&l" (res) + : [mem] "l" (mem), + [val] "l" (val) + : "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Set bits (32-bit) +/// \param[in] mem Memory address +/// \param[in] bits Bit mask +/// \return New value +#if defined(__CC_ARM) +static __asm uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) { + mov r2,r0 +1 + ldrex r0,[r2] + orr r0,r0,r1 + strex r3,r0,[r2] + cbz r3,%F2 + b %B1 +2 + bx lr +} +#else +__STATIC_INLINE uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[val],[%[mem]]\n\t" +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + "mov %[ret],%[val]\n\t" + "orrs %[ret],%[bits]\n\t" +#else + "orr %[ret],%[val],%[bits]\n\t" +#endif + "strex %[res],%[ret],[%[mem]]\n\t" + "cbz %[res],2f\n\t" + "b 1b\n" + "2:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [bits] "l" (bits) +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + : "memory", "cc" +#else + : "memory" +#endif + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Clear bits (32-bit) +/// \param[in] mem Memory address +/// \param[in] bits Bit mask +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) { + push {r4,lr} + mov r2,r0 +1 + ldrex r0,[r2] + bic r4,r0,r1 + strex r3,r4,[r2] + cbz r3,%F2 + b %B1 +2 + pop {r4,pc} +} +#else +__STATIC_INLINE uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + "mov %[val],%[ret]\n\t" + "bics %[val],%[bits]\n\t" +#else + "bic %[val],%[ret],%[bits]\n\t" +#endif + "strex %[res],%[val],[%[mem]]\n\t" + "cbz %[res],2f\n\t" + "b 1b\n" + "2:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [bits] "l" (bits) +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + : "memory", "cc" +#else + : "memory" +#endif + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Check if all specified bits (32-bit) are active and clear them +/// \param[in] mem Memory address +/// \param[in] bits Bit mask +/// \return Active bits before clearing or 0 if not active +#if defined(__CC_ARM) +static __asm uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) { + push {r4,lr} + mov r2,r0 +1 + ldrex r0,[r2] + and r4,r0,r1 + cmp r4,r1 + beq %F2 + clrex + movs r0,#0 + pop {r4,pc} +2 + bic r4,r0,r1 + strex r3,r4,[r2] + cbz r3,%F3 + b %B1 +3 + pop {r4,pc} +} +#else +__STATIC_INLINE uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + "mov %[val],%[ret]\n\t" + "ands %[val],%[bits]\n\t" +#else + "and %[val],%[ret],%[bits]\n\t" +#endif + "cmp %[val],%[bits]\n\t" + "beq 2f\n\t" + "clrex\n\t" + "movs %[ret],#0\n\t" + "b 3f\n" + "2:\n\t" +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + "mov %[val],%[ret]\n\t" + "bics %[val],%[bits]\n\t" +#else + "bic %[val],%[ret],%[bits]\n\t" +#endif + "strex %[res],%[val],[%[mem]]\n\t" + "cbz %[res],3f\n\t" + "b 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [bits] "l" (bits) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Check if any specified bits (32-bit) are active and clear them +/// \param[in] mem Memory address +/// \param[in] bits Bit mask +/// \return Active bits before clearing or 0 if not active +#if defined(__CC_ARM) +static __asm uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) { + push {r4,lr} + mov r2,r0 +1 + ldrex r0,[r2] + tst r0,r1 + bne %F2 + clrex + movs r0,#0 + pop {r4,pc} +2 + bic r4,r0,r1 + strex r3,r4,[r2] + cbz r3,%F3 + b %B1 +3 + pop {r4,pc} +} +#else +__STATIC_INLINE uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "tst %[ret],%[bits]\n\t" + "bne 2f\n\t" + "clrex\n\t" + "movs %[ret],#0\n\t" + "b 3f\n" + "2:\n\t" +#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + "mov %[val],%[ret]\n\t" + "bics %[val],%[bits]\n\t" +#else + "bic %[val],%[ret],%[bits]\n\t" +#endif + "strex %[res],%[val],[%[mem]]\n\t" + "cbz %[res],3f\n\t" + "b 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [bits] "l" (bits) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Increment (32-bit) +/// \param[in] mem Memory address +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint32_t atomic_inc32 (uint32_t *mem) { + mov r2,r0 +1 + ldrex r0,[r2] + adds r1,r0,#1 + strex r3,r1,[r2] + cbz r3,%F2 + b %B1 +2 + bx lr +} +#else +__STATIC_INLINE uint32_t atomic_inc32 (uint32_t *mem) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "adds %[val],%[ret],#1\n\t" + "strex %[res],%[val],[%[mem]]\n\t" + "cbz %[res],2f\n\t" + "b 1b\n" + "2:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Increment (16-bit) if Less Than +/// \param[in] mem Memory address +/// \param[in] max Maximum value +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) { + push {r4,lr} + mov r2,r0 +1 + ldrexh r0,[r2] + cmp r1,r0 + bhi %F2 + clrex + pop {r4,pc} +2 + adds r4,r0,#1 + strexh r3,r4,[r2] + cbz r3,%F3 + b %B1 +3 + pop {r4,pc} +} +#else +__STATIC_INLINE uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint16_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrexh %[ret],[%[mem]]\n\t" + "cmp %[max],%[ret]\n\t" + "bhi 2f\n\t" + "clrex\n\t" + "b 3f\n" + "2:\n\t" + "adds %[val],%[ret],#1\n\t" + "strexh %[res],%[val],[%[mem]]\n\t" + "cbz %[res],3f\n\t" + "b 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [max] "l" (max) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Increment (16-bit) and clear on Limit +/// \param[in] mem Memory address +/// \param[in] max Maximum value +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) { + push {r4,lr} + mov r2,r0 +1 + ldrexh r0,[r2] + adds r4,r0,#1 + cmp r1,r4 + bhi %F2 + movs r4,#0 +2 + strexh r3,r4,[r2] + cbz r3,%F3 + b %B1 +3 + pop {r4,pc} +} +#else +__STATIC_INLINE uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint16_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrexh %[ret],[%[mem]]\n\t" + "adds %[val],%[ret],#1\n\t" + "cmp %[lim],%[val]\n\t" + "bhi 2f\n\t" + "movs %[val],#0\n" + "2:\n\t" + "strexh %[res],%[val],[%[mem]]\n\t" + "cbz %[res],3f\n\t" + "b 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [lim] "l" (lim) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Decrement (32-bit) +/// \param[in] mem Memory address +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint32_t atomic_dec32 (uint32_t *mem) { + mov r2,r0 +1 + ldrex r0,[r2] + subs r1,r0,#1 + strex r3,r1,[r2] + cbz r3,%F2 + b %B1 +2 + bx lr +} +#else +__STATIC_INLINE uint32_t atomic_dec32 (uint32_t *mem) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "subs %[val],%[ret],#1\n\t" + "strex %[res],%[val],[%[mem]]\n\t" + "cbz %[res],2f\n\t" + "b 1b\n" + "2:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Decrement (32-bit) if Not Zero +/// \param[in] mem Memory address +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint32_t atomic_dec32_nz (uint32_t *mem) { + mov r2,r0 +1 + ldrex r0,[r2] + cbnz r0,%F2 + clrex + bx lr +2 + subs r1,r0,#1 + strex r3,r1,[r2] + cbz r3,%F3 + b %B1 +3 + bx lr +} +#else +__STATIC_INLINE uint32_t atomic_dec32_nz (uint32_t *mem) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "cbnz %[ret],2f\n\t" + "clrex\n\t" + "b 3f\n" + "2:\n\t" + "subs %[val],%[ret],#1\n\t" + "strex %[res],%[val],[%[mem]]\n\t" + "cbz %[res],3f\n\t" + "b 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Decrement (16-bit) if Not Zero +/// \param[in] mem Memory address +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint16_t atomic_dec16_nz (uint16_t *mem) { + mov r2,r0 +1 + ldrexh r0,[r2] + cbnz r0,%F2 + clrex + bx lr +2 + subs r1,r0,#1 + strexh r3,r1,[r2] + cbz r3,%F3 + b %B1 +3 + bx lr +} +#else +__STATIC_INLINE uint16_t atomic_dec16_nz (uint16_t *mem) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint16_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrexh %[ret],[%[mem]]\n\t" + "cbnz %[ret],2f\n\t" + "clrex\n\t" + "b 3f\n" + "2:\n\t" + "subs %[val],%[ret],#1\n\t" + "strexh %[res],%[val],[%[mem]]\n\t" + "cbz %[res],3f\n\t" + "b 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Link Get +/// \param[in] root Root address +/// \return Link +#if defined(__CC_ARM) +static __asm void *atomic_link_get (void **root) { + mov r2,r0 +1 + ldrex r0,[r2] + cbnz r0,%F2 + clrex + bx lr +2 + ldr r1,[r0] + strex r3,r1,[r2] + cbz r3,%F3 + b %B1 +3 + bx lr +} +#else +__STATIC_INLINE void *atomic_link_get (void **root) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register void *ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[root]]\n\t" + "cbnz %[ret],2f\n\t" + "clrex\n\t" + "b 3f\n" + "2:\n\t" + "ldr %[val],[%[ret]]\n\t" + "strex %[res],%[val],[%[root]]\n\t" + "cbz %[res],3f\n\t" + "b 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [root] "l" (root) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Link Put +/// \param[in] root Root address +/// \param[in] lnk Link +#if defined(__CC_ARM) +static __asm void atomic_link_put (void **root, void *link) { +1 + ldr r2,[r0] + str r2,[r1] + dmb + ldrex r2,[r0] + ldr r3,[r1] + cmp r3,r2 + bne %B1 + strex r3,r1,[r0] + cbz r3,%F2 + b %B1 +2 + bx lr +} +#else +__STATIC_INLINE void atomic_link_put (void **root, void *link) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val1, val2, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldr %[val1],[%[root]]\n\t" + "str %[val1],[%[link]]\n\t" + "dmb\n\t" + "ldrex %[val1],[%[root]]\n\t" + "ldr %[val2],[%[link]]\n\t" + "cmp %[val2],%[val1]\n\t" + "bne 1b\n\t" + "strex %[res],%[link],[%[root]]\n\t" + "cbz %[res],2f\n\t" + "b 1b\n" + "2:" + : [val1] "=&l" (val1), + [val2] "=&l" (val2), + [res] "=&l" (res) + : [root] "l" (root), + [link] "l" (link) + : "cc", "memory" + ); +} +#endif + +//lint --flb "Library End" [MISRA Note 12] + +#endif // (EXCLUSIVE_ACCESS == 1) + + +#endif // RTX_CORE_CM_H_ diff --git a/source/rtos2/RTX/Source/rtx_delay.c b/source/rtos2/RTX/Source/rtx_delay.c new file mode 100644 index 000000000..9d0cf414b --- /dev/null +++ b/source/rtos2/RTX/Source/rtx_delay.c @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2013-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Delay functions + * + * ----------------------------------------------------------------------------- + */ + +#include "rtx_lib.h" + + +// ==== Service Calls ==== + +/// Wait for Timeout (Time Delay). +/// \note API identical to osDelay +static osStatus_t svcRtxDelay (uint32_t ticks) { + + if (ticks != 0U) { + if (osRtxThreadWaitEnter(osRtxThreadWaitingDelay, ticks)) { + EvrRtxDelayStarted(ticks); + } else { + EvrRtxDelayCompleted(osRtxThreadGetRunning()); + } + } + + return osOK; +} + +/// Wait until specified time. +/// \note API identical to osDelayUntil +static osStatus_t svcRtxDelayUntil (uint32_t ticks) { + + ticks -= osRtxInfo.kernel.tick; + if ((ticks == 0U) || (ticks > 0x7FFFFFFFU)) { + EvrRtxDelayError((int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + if (osRtxThreadWaitEnter(osRtxThreadWaitingDelay, ticks)) { + EvrRtxDelayUntilStarted(ticks); + } else { + EvrRtxDelayCompleted(osRtxThreadGetRunning()); + } + + return osOK; +} + +// Service Calls definitions +//lint ++flb "Library Begin" [MISRA Note 11] +SVC0_1(Delay, osStatus_t, uint32_t) +SVC0_1(DelayUntil, osStatus_t, uint32_t) +//lint --flb "Library End" + + +// ==== Public API ==== + +/// Wait for Timeout (Time Delay). +osStatus_t osDelay (uint32_t ticks) { + osStatus_t status; + + EvrRtxDelay(ticks); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxDelayError((int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcDelay(ticks); + } + return status; +} + +/// Wait until specified time. +osStatus_t osDelayUntil (uint32_t ticks) { + osStatus_t status; + + EvrRtxDelayUntil(ticks); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxDelayError((int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcDelayUntil(ticks); + } + return status; +} diff --git a/source/rtos2/RTX/Source/rtx_evflags.c b/source/rtos2/RTX/Source/rtx_evflags.c new file mode 100644 index 000000000..f32aec7b8 --- /dev/null +++ b/source/rtos2/RTX/Source/rtx_evflags.c @@ -0,0 +1,582 @@ +/* + * Copyright (c) 2013-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Event Flags functions + * + * ----------------------------------------------------------------------------- + */ + +#include "rtx_lib.h" + + +// OS Runtime Object Memory Usage +#if ((defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0))) +osRtxObjectMemUsage_t osRtxEventFlagsMemUsage \ +__attribute__((section(".data.os.evflags.obj"))) = +{ 0U, 0U, 0U }; +#endif + + +// ==== Helper functions ==== + +/// Set Event Flags. +/// \param[in] ef event flags object. +/// \param[in] flags specifies the flags to set. +/// \return event flags after setting. +static uint32_t EventFlagsSet (os_event_flags_t *ef, uint32_t flags) { +#if (EXCLUSIVE_ACCESS == 0) + uint32_t primask = __get_PRIMASK(); +#endif + uint32_t event_flags; + +#if (EXCLUSIVE_ACCESS == 0) + __disable_irq(); + + ef->event_flags |= flags; + event_flags = ef->event_flags; + + if (primask == 0U) { + __enable_irq(); + } +#else + event_flags = atomic_set32(&ef->event_flags, flags); +#endif + + return event_flags; +} + +/// Clear Event Flags. +/// \param[in] ef event flags object. +/// \param[in] flags specifies the flags to clear. +/// \return event flags before clearing. +static uint32_t EventFlagsClear (os_event_flags_t *ef, uint32_t flags) { +#if (EXCLUSIVE_ACCESS == 0) + uint32_t primask = __get_PRIMASK(); +#endif + uint32_t event_flags; + +#if (EXCLUSIVE_ACCESS == 0) + __disable_irq(); + + event_flags = ef->event_flags; + ef->event_flags &= ~flags; + + if (primask == 0U) { + __enable_irq(); + } +#else + event_flags = atomic_clr32(&ef->event_flags, flags); +#endif + + return event_flags; +} + +/// Check Event Flags. +/// \param[in] ef event flags object. +/// \param[in] flags specifies the flags to check. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \return event flags before clearing or 0 if specified flags have not been set. +static uint32_t EventFlagsCheck (os_event_flags_t *ef, uint32_t flags, uint32_t options) { +#if (EXCLUSIVE_ACCESS == 0) + uint32_t primask; +#endif + uint32_t event_flags; + + if ((options & osFlagsNoClear) == 0U) { +#if (EXCLUSIVE_ACCESS == 0) + primask = __get_PRIMASK(); + __disable_irq(); + + event_flags = ef->event_flags; + if ((((options & osFlagsWaitAll) != 0U) && ((event_flags & flags) != flags)) || + (((options & osFlagsWaitAll) == 0U) && ((event_flags & flags) == 0U))) { + event_flags = 0U; + } else { + ef->event_flags &= ~flags; + } + + if (primask == 0U) { + __enable_irq(); + } +#else + if ((options & osFlagsWaitAll) != 0U) { + event_flags = atomic_chk32_all(&ef->event_flags, flags); + } else { + event_flags = atomic_chk32_any(&ef->event_flags, flags); + } +#endif + } else { + event_flags = ef->event_flags; + if ((((options & osFlagsWaitAll) != 0U) && ((event_flags & flags) != flags)) || + (((options & osFlagsWaitAll) == 0U) && ((event_flags & flags) == 0U))) { + event_flags = 0U; + } + } + + return event_flags; +} + + +// ==== Post ISR processing ==== + +/// Event Flags post ISR processing. +/// \param[in] ef event flags object. +static void osRtxEventFlagsPostProcess (os_event_flags_t *ef) { + os_thread_t *thread; + os_thread_t *thread_next; + uint32_t event_flags; + + // Check if Threads are waiting for Event Flags + thread = ef->thread_list; + while (thread != NULL) { + thread_next = thread->thread_next; + event_flags = EventFlagsCheck(ef, thread->wait_flags, thread->flags_options); + if (event_flags != 0U) { + osRtxThreadListRemove(thread); + osRtxThreadWaitExit(thread, event_flags, FALSE); + EvrRtxEventFlagsWaitCompleted(ef, thread->wait_flags, thread->flags_options, event_flags); + } + thread = thread_next; + } +} + + +// ==== Service Calls ==== + +/// Create and Initialize an Event Flags object. +/// \note API identical to osEventFlagsNew +static osEventFlagsId_t svcRtxEventFlagsNew (const osEventFlagsAttr_t *attr) { + os_event_flags_t *ef; + uint8_t flags; + const char *name; + + // Process attributes + if (attr != NULL) { + name = attr->name; + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6] + ef = attr->cb_mem; + if (ef != NULL) { + //lint -e(923) -e(9078) "cast from pointer to unsigned int" [MISRA Note 7] + if ((((uint32_t)ef & 3U) != 0U) || (attr->cb_size < sizeof(os_event_flags_t))) { + EvrRtxEventFlagsError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + } else { + if (attr->cb_size != 0U) { + EvrRtxEventFlagsError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + } + } else { + name = NULL; + ef = NULL; + } + + // Allocate object memory if not provided + if (ef == NULL) { + if (osRtxInfo.mpi.event_flags != NULL) { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + ef = osRtxMemoryPoolAlloc(osRtxInfo.mpi.event_flags); + } else { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + ef = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_event_flags_t), 1U); + } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + if (ef != NULL) { + uint32_t used; + osRtxEventFlagsMemUsage.cnt_alloc++; + used = osRtxEventFlagsMemUsage.cnt_alloc - osRtxEventFlagsMemUsage.cnt_free; + if (osRtxEventFlagsMemUsage.max_used < used) { + osRtxEventFlagsMemUsage.max_used = used; + } + } +#endif + flags = osRtxFlagSystemObject; + } else { + flags = 0U; + } + + if (ef != NULL) { + // Initialize control block + ef->id = osRtxIdEventFlags; + ef->flags = flags; + ef->name = name; + ef->thread_list = NULL; + ef->event_flags = 0U; + + // Register post ISR processing function + osRtxInfo.post_process.event_flags = osRtxEventFlagsPostProcess; + + EvrRtxEventFlagsCreated(ef, ef->name); + } else { + EvrRtxEventFlagsError(NULL, (int32_t)osErrorNoMemory); + } + + return ef; +} + +/// Get name of an Event Flags object. +/// \note API identical to osEventFlagsGetName +static const char *svcRtxEventFlagsGetName (osEventFlagsId_t ef_id) { + os_event_flags_t *ef = osRtxEventFlagsId(ef_id); + + // Check parameters + if ((ef == NULL) || (ef->id != osRtxIdEventFlags)) { + EvrRtxEventFlagsGetName(ef, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + + EvrRtxEventFlagsGetName(ef, ef->name); + + return ef->name; +} + +/// Set the specified Event Flags. +/// \note API identical to osEventFlagsSet +static uint32_t svcRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) { + os_event_flags_t *ef = osRtxEventFlagsId(ef_id); + os_thread_t *thread; + os_thread_t *thread_next; + uint32_t event_flags; + uint32_t event_flags0; + + // Check parameters + if ((ef == NULL) || (ef->id != osRtxIdEventFlags) || + ((flags & ~(((uint32_t)1U << osRtxEventFlagsLimit) - 1U)) != 0U)) { + EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return ((uint32_t)osErrorParameter); + } + + // Set Event Flags + event_flags = EventFlagsSet(ef, flags); + + // Check if Threads are waiting for Event Flags + thread = ef->thread_list; + while (thread != NULL) { + thread_next = thread->thread_next; + event_flags0 = EventFlagsCheck(ef, thread->wait_flags, thread->flags_options); + if (event_flags0 != 0U) { + if ((thread->flags_options & osFlagsNoClear) == 0U) { + event_flags = event_flags0 & ~thread->wait_flags; + } else { + event_flags = event_flags0; + } + osRtxThreadListRemove(thread); + osRtxThreadWaitExit(thread, event_flags0, FALSE); + EvrRtxEventFlagsWaitCompleted(ef, thread->wait_flags, thread->flags_options, event_flags0); + } + thread = thread_next; + } + osRtxThreadDispatch(NULL); + + EvrRtxEventFlagsSetDone(ef, event_flags); + + return event_flags; +} + +/// Clear the specified Event Flags. +/// \note API identical to osEventFlagsClear +static uint32_t svcRtxEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) { + os_event_flags_t *ef = osRtxEventFlagsId(ef_id); + uint32_t event_flags; + + // Check parameters + if ((ef == NULL) || (ef->id != osRtxIdEventFlags) || + ((flags & ~(((uint32_t)1U << osRtxEventFlagsLimit) - 1U)) != 0U)) { + EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return ((uint32_t)osErrorParameter); + } + + // Clear Event Flags + event_flags = EventFlagsClear(ef, flags); + + EvrRtxEventFlagsClearDone(ef, event_flags); + + return event_flags; +} + +/// Get the current Event Flags. +/// \note API identical to osEventFlagsGet +static uint32_t svcRtxEventFlagsGet (osEventFlagsId_t ef_id) { + os_event_flags_t *ef = osRtxEventFlagsId(ef_id); + + // Check parameters + if ((ef == NULL) || (ef->id != osRtxIdEventFlags)) { + EvrRtxEventFlagsGet(ef, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return 0U; + } + + EvrRtxEventFlagsGet(ef, ef->event_flags); + + return ef->event_flags; +} + +/// Wait for one or more Event Flags to become signaled. +/// \note API identical to osEventFlagsWait +static uint32_t svcRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) { + os_event_flags_t *ef = osRtxEventFlagsId(ef_id); + os_thread_t *thread; + uint32_t event_flags; + + // Check parameters + if ((ef == NULL) || (ef->id != osRtxIdEventFlags) || + ((flags & ~(((uint32_t)1U << osRtxEventFlagsLimit) - 1U)) != 0U)) { + EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return ((uint32_t)osErrorParameter); + } + + // Check Event Flags + event_flags = EventFlagsCheck(ef, flags, options); + if (event_flags != 0U) { + EvrRtxEventFlagsWaitCompleted(ef, flags, options, event_flags); + } else { + // Check if timeout is specified + if (timeout != 0U) { + EvrRtxEventFlagsWaitPending(ef, flags, options, timeout); + // Suspend current Thread + if (osRtxThreadWaitEnter(osRtxThreadWaitingEventFlags, timeout)) { + thread = osRtxThreadGetRunning(); + osRtxThreadListPut(osRtxObject(ef), thread); + // Store waiting flags and options + thread->wait_flags = flags; + thread->flags_options = (uint8_t)options; + } else { + EvrRtxEventFlagsWaitTimeout(ef); + } + event_flags = (uint32_t)osErrorTimeout; + } else { + EvrRtxEventFlagsWaitNotCompleted(ef, flags, options); + event_flags = (uint32_t)osErrorResource; + } + } + + return event_flags; +} + +/// Delete an Event Flags object. +/// \note API identical to osEventFlagsDelete +static osStatus_t svcRtxEventFlagsDelete (osEventFlagsId_t ef_id) { + os_event_flags_t *ef = osRtxEventFlagsId(ef_id); + os_thread_t *thread; + + // Check parameters + if ((ef == NULL) || (ef->id != osRtxIdEventFlags)) { + EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Unblock waiting threads + if (ef->thread_list != NULL) { + do { + thread = osRtxThreadListGet(osRtxObject(ef)); + osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE); + } while (ef->thread_list != NULL); + osRtxThreadDispatch(NULL); + } + + // Mark object as invalid + ef->id = osRtxIdInvalid; + + // Free object memory + if ((ef->flags & osRtxFlagSystemObject) != 0U) { + if (osRtxInfo.mpi.event_flags != NULL) { + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.event_flags, ef); + } else { + (void)osRtxMemoryFree(osRtxInfo.mem.common, ef); + } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxEventFlagsMemUsage.cnt_free++; +#endif + } + + EvrRtxEventFlagsDestroyed(ef); + + return osOK; +} + +// Service Calls definitions +//lint ++flb "Library Begin" [MISRA Note 11] +SVC0_1(EventFlagsNew, osEventFlagsId_t, const osEventFlagsAttr_t *) +SVC0_1(EventFlagsGetName, const char *, osEventFlagsId_t) +SVC0_2(EventFlagsSet, uint32_t, osEventFlagsId_t, uint32_t) +SVC0_2(EventFlagsClear, uint32_t, osEventFlagsId_t, uint32_t) +SVC0_1(EventFlagsGet, uint32_t, osEventFlagsId_t) +SVC0_4(EventFlagsWait, uint32_t, osEventFlagsId_t, uint32_t, uint32_t, uint32_t) +SVC0_1(EventFlagsDelete, osStatus_t, osEventFlagsId_t) +//lint --flb "Library End" + + +// ==== ISR Calls ==== + +/// Set the specified Event Flags. +/// \note API identical to osEventFlagsSet +__STATIC_INLINE +uint32_t isrRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) { + os_event_flags_t *ef = osRtxEventFlagsId(ef_id); + uint32_t event_flags; + + // Check parameters + if ((ef == NULL) || (ef->id != osRtxIdEventFlags) || + ((flags & ~(((uint32_t)1U << osRtxEventFlagsLimit) - 1U)) != 0U)) { + EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return ((uint32_t)osErrorParameter); + } + + // Set Event Flags + event_flags = EventFlagsSet(ef, flags); + + // Register post ISR processing + osRtxPostProcess(osRtxObject(ef)); + + EvrRtxEventFlagsSetDone(ef, event_flags); + + return event_flags; +} + +/// Wait for one or more Event Flags to become signaled. +/// \note API identical to osEventFlagsWait +__STATIC_INLINE +uint32_t isrRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) { + os_event_flags_t *ef = osRtxEventFlagsId(ef_id); + uint32_t event_flags; + + // Check parameters + if ((ef == NULL) || (ef->id != osRtxIdEventFlags) || (timeout != 0U) || + ((flags & ~(((uint32_t)1U << osRtxEventFlagsLimit) - 1U)) != 0U)) { + EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return ((uint32_t)osErrorParameter); + } + + // Check Event Flags + event_flags = EventFlagsCheck(ef, flags, options); + if (event_flags != 0U) { + EvrRtxEventFlagsWaitCompleted(ef, flags, options, event_flags); + } else { + EvrRtxEventFlagsWaitNotCompleted(ef, flags, options); + event_flags = (uint32_t)osErrorResource; + } + + return event_flags; +} + + +// ==== Public API ==== + +/// Create and Initialize an Event Flags object. +osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr) { + osEventFlagsId_t ef_id; + + EvrRtxEventFlagsNew(attr); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxEventFlagsError(NULL, (int32_t)osErrorISR); + ef_id = NULL; + } else { + ef_id = __svcEventFlagsNew(attr); + } + return ef_id; +} + +/// Get name of an Event Flags object. +const char *osEventFlagsGetName (osEventFlagsId_t ef_id) { + const char *name; + + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxEventFlagsGetName(ef_id, NULL); + name = NULL; + } else { + name = __svcEventFlagsGetName(ef_id); + } + return name; +} + +/// Set the specified Event Flags. +uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) { + uint32_t event_flags; + + EvrRtxEventFlagsSet(ef_id, flags); + if (IsIrqMode() || IsIrqMasked()) { + event_flags = isrRtxEventFlagsSet(ef_id, flags); + } else { + event_flags = __svcEventFlagsSet(ef_id, flags); + } + return event_flags; +} + +/// Clear the specified Event Flags. +uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) { + uint32_t event_flags; + + EvrRtxEventFlagsClear(ef_id, flags); + if (IsIrqMode() || IsIrqMasked()) { + event_flags = svcRtxEventFlagsClear(ef_id, flags); + } else { + event_flags = __svcEventFlagsClear(ef_id, flags); + } + return event_flags; +} + +/// Get the current Event Flags. +uint32_t osEventFlagsGet (osEventFlagsId_t ef_id) { + uint32_t event_flags; + + if (IsIrqMode() || IsIrqMasked()) { + event_flags = svcRtxEventFlagsGet(ef_id); + } else { + event_flags = __svcEventFlagsGet(ef_id); + } + return event_flags; +} + +/// Wait for one or more Event Flags to become signaled. +uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) { + uint32_t event_flags; + + EvrRtxEventFlagsWait(ef_id, flags, options, timeout); + if (IsIrqMode() || IsIrqMasked()) { + event_flags = isrRtxEventFlagsWait(ef_id, flags, options, timeout); + } else { + event_flags = __svcEventFlagsWait(ef_id, flags, options, timeout); + } + return event_flags; +} + +/// Delete an Event Flags object. +osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id) { + osStatus_t status; + + EvrRtxEventFlagsDelete(ef_id); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxEventFlagsError(ef_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcEventFlagsDelete(ef_id); + } + return status; +} diff --git a/source/rtos2/RTX/Source/rtx_evr.c b/source/rtos2/RTX/Source/rtx_evr.c new file mode 100644 index 000000000..042d25427 --- /dev/null +++ b/source/rtos2/RTX/Source/rtx_evr.c @@ -0,0 +1,2114 @@ +/* + * Copyright (c) 2013-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: RTX Event Recorder + * + * ----------------------------------------------------------------------------- + */ + +#include +#include "cmsis_compiler.h" +#include "rtx_evr.h" // RTX Event Recorder definitions + +#ifdef RTE_Compiler_EventRecorder + +//lint -e923 -e9074 -e9078 [MISRA Note 13] + +/// Event IDs for "RTX Memory Management" +#define EvtRtxMemoryInit EventID(EventLevelOp, EvtRtxMemoryNo, 0x00U) +#define EvtRtxMemoryAlloc EventID(EventLevelOp, EvtRtxMemoryNo, 0x01U) +#define EvtRtxMemoryFree EventID(EventLevelOp, EvtRtxMemoryNo, 0x02U) +#define EvtRtxMemoryBlockInit EventID(EventLevelOp, EvtRtxMemoryNo, 0x03U) +#define EvtRtxMemoryBlockAlloc EventID(EventLevelOp, EvtRtxMemoryNo, 0x04U) +#define EvtRtxMemoryBlockFree EventID(EventLevelOp, EvtRtxMemoryNo, 0x05U) + +/// Event IDs for "RTX Kernel" +#define EvtRtxKernelError EventID(EventLevelError, EvtRtxKernelNo, 0x00U) +#define EvtRtxKernelInitialize EventID(EventLevelAPI, EvtRtxKernelNo, 0x01U) +#define EvtRtxKernelInitialized EventID(EventLevelOp, EvtRtxKernelNo, 0x02U) +#define EvtRtxKernelGetInfo EventID(EventLevelAPI, EvtRtxKernelNo, 0x03U) +#define EvtRtxKernelInfoRetrieved EventID(EventLevelOp, EvtRtxKernelNo, 0x04U) +#define EvtRtxKernelInfoRetrieved_Detail EventID(EventLevelDetail, EvtRtxKernelNo, 0x05U) +#define EvtRtxKernelGetState EventID(EventLevelAPI, EvtRtxKernelNo, 0x06U) +#define EvtRtxKernelStart EventID(EventLevelAPI, EvtRtxKernelNo, 0x07U) +#define EvtRtxKernelStarted EventID(EventLevelOp, EvtRtxKernelNo, 0x08U) +#define EvtRtxKernelLock EventID(EventLevelAPI, EvtRtxKernelNo, 0x09U) +#define EvtRtxKernelLocked EventID(EventLevelOp, EvtRtxKernelNo, 0x0AU) +#define EvtRtxKernelUnlock EventID(EventLevelAPI, EvtRtxKernelNo, 0x0BU) +#define EvtRtxKernelUnlocked EventID(EventLevelOp, EvtRtxKernelNo, 0x0CU) +#define EvtRtxKernelRestoreLock EventID(EventLevelAPI, EvtRtxKernelNo, 0x0DU) +#define EvtRtxKernelLockRestored EventID(EventLevelOp, EvtRtxKernelNo, 0x0EU) +#define EvtRtxKernelSuspend EventID(EventLevelAPI, EvtRtxKernelNo, 0x0FU) +#define EvtRtxKernelSuspended EventID(EventLevelOp, EvtRtxKernelNo, 0x10U) +#define EvtRtxKernelResume EventID(EventLevelAPI, EvtRtxKernelNo, 0x11U) +#define EvtRtxKernelResumed EventID(EventLevelOp, EvtRtxKernelNo, 0x12U) +#define EvtRtxKernelGetTickCount EventID(EventLevelAPI, EvtRtxKernelNo, 0x13U) +#define EvtRtxKernelGetTickFreq EventID(EventLevelAPI, EvtRtxKernelNo, 0x14U) +#define EvtRtxKernelGetSysTimerCount EventID(EventLevelAPI, EvtRtxKernelNo, 0x15U) +#define EvtRtxKernelGetSysTimerFreq EventID(EventLevelAPI, EvtRtxKernelNo, 0x16U) + +/// Event IDs for "RTX Thread" +#define EvtRtxThreadError EventID(EventLevelError, EvtRtxThreadNo, 0x00U) +#define EvtRtxThreadNew EventID(EventLevelAPI, EvtRtxThreadNo, 0x01U) +#define EvtRtxThreadCreated_Addr EventID(EventLevelOp, EvtRtxThreadNo, 0x03U) +#define EvtRtxThreadCreated_Name EventID(EventLevelOp, EvtRtxThreadNo, 0x2CU) +#define EvtRtxThreadGetName EventID(EventLevelAPI, EvtRtxThreadNo, 0x04U) +#define EvtRtxThreadGetId EventID(EventLevelAPI, EvtRtxThreadNo, 0x06U) +#define EvtRtxThreadGetState EventID(EventLevelAPI, EvtRtxThreadNo, 0x07U) +#define EvtRtxThreadGetStackSize EventID(EventLevelAPI, EvtRtxThreadNo, 0x08U) +#define EvtRtxThreadGetStackSpace EventID(EventLevelAPI, EvtRtxThreadNo, 0x09U) +#define EvtRtxThreadSetPriority EventID(EventLevelAPI, EvtRtxThreadNo, 0x0AU) +#define EvtRtxThreadPriorityUpdated EventID(EventLevelOp, EvtRtxThreadNo, 0x2DU) +#define EvtRtxThreadGetPriority EventID(EventLevelAPI, EvtRtxThreadNo, 0x0BU) +#define EvtRtxThreadYield EventID(EventLevelAPI, EvtRtxThreadNo, 0x0CU) +#define EvtRtxThreadSuspend EventID(EventLevelAPI, EvtRtxThreadNo, 0x0DU) +#define EvtRtxThreadSuspended EventID(EventLevelOp, EvtRtxThreadNo, 0x0EU) +#define EvtRtxThreadResume EventID(EventLevelAPI, EvtRtxThreadNo, 0x0FU) +#define EvtRtxThreadResumed EventID(EventLevelOp, EvtRtxThreadNo, 0x10U) +#define EvtRtxThreadDetach EventID(EventLevelAPI, EvtRtxThreadNo, 0x11U) +#define EvtRtxThreadDetached EventID(EventLevelOp, EvtRtxThreadNo, 0x12U) +#define EvtRtxThreadJoin EventID(EventLevelAPI, EvtRtxThreadNo, 0x13U) +#define EvtRtxThreadJoinPending EventID(EventLevelOp, EvtRtxThreadNo, 0x14U) +#define EvtRtxThreadJoined EventID(EventLevelOp, EvtRtxThreadNo, 0x15U) +#define EvtRtxThreadBlocked EventID(EventLevelDetail, EvtRtxThreadNo, 0x16U) +#define EvtRtxThreadUnblocked EventID(EventLevelDetail, EvtRtxThreadNo, 0x17U) +#define EvtRtxThreadPreempted EventID(EventLevelDetail, EvtRtxThreadNo, 0x18U) +#define EvtRtxThreadSwitched EventID(EventLevelOp, EvtRtxThreadNo, 0x19U) +#define EvtRtxThreadExit EventID(EventLevelAPI, EvtRtxThreadNo, 0x1AU) +#define EvtRtxThreadTerminate EventID(EventLevelAPI, EvtRtxThreadNo, 0x1BU) +#define EvtRtxThreadDestroyed EventID(EventLevelOp, EvtRtxThreadNo, 0x1CU) +#define EvtRtxThreadGetCount EventID(EventLevelAPI, EvtRtxThreadNo, 0x1DU) +#define EvtRtxThreadEnumerate EventID(EventLevelAPI, EvtRtxThreadNo, 0x1EU) + +/// Event IDs for "RTX Thread Flags" +#define EvtRtxThreadFlagsError EventID(EventLevelError, EvtRtxThreadFlagsNo, 0x00U) +#define EvtRtxThreadFlagsSet EventID(EventLevelAPI, EvtRtxThreadFlagsNo, 0x01U) +#define EvtRtxThreadFlagsSetDone EventID(EventLevelOp, EvtRtxThreadFlagsNo, 0x02U) +#define EvtRtxThreadFlagsClear EventID(EventLevelAPI, EvtRtxThreadFlagsNo, 0x03U) +#define EvtRtxThreadFlagsClearDone EventID(EventLevelOp, EvtRtxThreadFlagsNo, 0x04U) +#define EvtRtxThreadFlagsGet EventID(EventLevelAPI, EvtRtxThreadFlagsNo, 0x05U) +#define EvtRtxThreadFlagsWait EventID(EventLevelAPI, EvtRtxThreadFlagsNo, 0x06U) +#define EvtRtxThreadFlagsWaitPending EventID(EventLevelOp, EvtRtxThreadFlagsNo, 0x07U) +#define EvtRtxThreadFlagsWaitTimeout EventID(EventLevelOp, EvtRtxThreadFlagsNo, 0x08U) +#define EvtRtxThreadFlagsWaitCompleted EventID(EventLevelOp, EvtRtxThreadFlagsNo, 0x09U) +#define EvtRtxThreadFlagsWaitNotCompleted EventID(EventLevelOp, EvtRtxThreadFlagsNo, 0x0AU) + +/// Event IDs for "RTX Generic Wait" +#define EvtRtxDelayError EventID(EventLevelError, EvtRtxWaitNo, 0x00U) +#define EvtRtxDelay EventID(EventLevelAPI, EvtRtxWaitNo, 0x01U) +#define EvtRtxDelayUntil EventID(EventLevelAPI, EvtRtxWaitNo, 0x02U) +#define EvtRtxDelayStarted EventID(EventLevelOp, EvtRtxWaitNo, 0x03U) +#define EvtRtxDelayUntilStarted EventID(EventLevelOp, EvtRtxWaitNo, 0x04U) +#define EvtRtxDelayCompleted EventID(EventLevelOp, EvtRtxWaitNo, 0x05U) + +/// Event IDs for "RTX Timer" +#define EvtRtxTimerError EventID(EventLevelError, EvtRtxTimerNo, 0x00U) +#define EvtRtxTimerCallback EventID(EventLevelOp, EvtRtxTimerNo, 0x01U) +#define EvtRtxTimerNew EventID(EventLevelAPI, EvtRtxTimerNo, 0x02U) +#define EvtRtxTimerCreated EventID(EventLevelOp, EvtRtxTimerNo, 0x04U) +#define EvtRtxTimerGetName EventID(EventLevelAPI, EvtRtxTimerNo, 0x05U) +#define EvtRtxTimerStart EventID(EventLevelAPI, EvtRtxTimerNo, 0x07U) +#define EvtRtxTimerStarted EventID(EventLevelOp, EvtRtxTimerNo, 0x08U) +#define EvtRtxTimerStop EventID(EventLevelAPI, EvtRtxTimerNo, 0x09U) +#define EvtRtxTimerStopped EventID(EventLevelOp, EvtRtxTimerNo, 0x0AU) +#define EvtRtxTimerIsRunning EventID(EventLevelAPI, EvtRtxTimerNo, 0x0BU) +#define EvtRtxTimerDelete EventID(EventLevelAPI, EvtRtxTimerNo, 0x0CU) +#define EvtRtxTimerDestroyed EventID(EventLevelOp, EvtRtxTimerNo, 0x0DU) + +/// Event IDs for "RTX Event Flags" +#define EvtRtxEventFlagsError EventID(EventLevelError, EvtRtxEventFlagsNo, 0x00U) +#define EvtRtxEventFlagsNew EventID(EventLevelAPI, EvtRtxEventFlagsNo, 0x01U) +#define EvtRtxEventFlagsCreated EventID(EventLevelOp, EvtRtxEventFlagsNo, 0x03U) +#define EvtRtxEventFlagsGetName EventID(EventLevelAPI, EvtRtxEventFlagsNo, 0x04U) +#define EvtRtxEventFlagsSet EventID(EventLevelAPI, EvtRtxEventFlagsNo, 0x06U) +#define EvtRtxEventFlagsSetDone EventID(EventLevelOp, EvtRtxEventFlagsNo, 0x07U) +#define EvtRtxEventFlagsClear EventID(EventLevelAPI, EvtRtxEventFlagsNo, 0x08U) +#define EvtRtxEventFlagsClearDone EventID(EventLevelOp, EvtRtxEventFlagsNo, 0x09U) +#define EvtRtxEventFlagsGet EventID(EventLevelAPI, EvtRtxEventFlagsNo, 0x0AU) +#define EvtRtxEventFlagsWait EventID(EventLevelAPI, EvtRtxEventFlagsNo, 0x0BU) +#define EvtRtxEventFlagsWaitPending EventID(EventLevelOp, EvtRtxEventFlagsNo, 0x0CU) +#define EvtRtxEventFlagsWaitTimeout EventID(EventLevelOp, EvtRtxEventFlagsNo, 0x0DU) +#define EvtRtxEventFlagsWaitCompleted EventID(EventLevelOp, EvtRtxEventFlagsNo, 0x0EU) +#define EvtRtxEventFlagsWaitNotCompleted EventID(EventLevelOp, EvtRtxEventFlagsNo, 0x0FU) +#define EvtRtxEventFlagsDelete EventID(EventLevelAPI, EvtRtxEventFlagsNo, 0x10U) +#define EvtRtxEventFlagsDestroyed EventID(EventLevelOp, EvtRtxEventFlagsNo, 0x11U) + +/// Event IDs for "RTX Mutex" +#define EvtRtxMutexError EventID(EventLevelError, EvtRtxMutexNo, 0x00U) +#define EvtRtxMutexNew EventID(EventLevelAPI, EvtRtxMutexNo, 0x01U) +#define EvtRtxMutexCreated EventID(EventLevelOp, EvtRtxMutexNo, 0x03U) +#define EvtRtxMutexGetName EventID(EventLevelAPI, EvtRtxMutexNo, 0x04U) +#define EvtRtxMutexAcquire EventID(EventLevelAPI, EvtRtxMutexNo, 0x06U) +#define EvtRtxMutexAcquirePending EventID(EventLevelOp, EvtRtxMutexNo, 0x07U) +#define EvtRtxMutexAcquireTimeout EventID(EventLevelOp, EvtRtxMutexNo, 0x08U) +#define EvtRtxMutexAcquired EventID(EventLevelOp, EvtRtxMutexNo, 0x09U) +#define EvtRtxMutexNotAcquired EventID(EventLevelOp, EvtRtxMutexNo, 0x0AU) +#define EvtRtxMutexRelease EventID(EventLevelAPI, EvtRtxMutexNo, 0x0BU) +#define EvtRtxMutexReleased EventID(EventLevelOp, EvtRtxMutexNo, 0x0CU) +#define EvtRtxMutexGetOwner EventID(EventLevelAPI, EvtRtxMutexNo, 0x0DU) +#define EvtRtxMutexDelete EventID(EventLevelAPI, EvtRtxMutexNo, 0x0EU) +#define EvtRtxMutexDestroyed EventID(EventLevelOp, EvtRtxMutexNo, 0x0FU) + +/// Event IDs for "RTX Semaphore" +#define EvtRtxSemaphoreError EventID(EventLevelError, EvtRtxSemaphoreNo, 0x00U) +#define EvtRtxSemaphoreNew EventID(EventLevelAPI, EvtRtxSemaphoreNo, 0x01U) +#define EvtRtxSemaphoreCreated EventID(EventLevelOp, EvtRtxSemaphoreNo, 0x03U) +#define EvtRtxSemaphoreGetName EventID(EventLevelAPI, EvtRtxSemaphoreNo, 0x04U) +#define EvtRtxSemaphoreAcquire EventID(EventLevelAPI, EvtRtxSemaphoreNo, 0x06U) +#define EvtRtxSemaphoreAcquirePending EventID(EventLevelOp, EvtRtxSemaphoreNo, 0x07U) +#define EvtRtxSemaphoreAcquireTimeout EventID(EventLevelOp, EvtRtxSemaphoreNo, 0x08U) +#define EvtRtxSemaphoreAcquired EventID(EventLevelOp, EvtRtxSemaphoreNo, 0x09U) +#define EvtRtxSemaphoreNotAcquired EventID(EventLevelOp, EvtRtxSemaphoreNo, 0x0AU) +#define EvtRtxSemaphoreRelease EventID(EventLevelAPI, EvtRtxSemaphoreNo, 0x0BU) +#define EvtRtxSemaphoreReleased EventID(EventLevelOp, EvtRtxSemaphoreNo, 0x0CU) +#define EvtRtxSemaphoreGetCount EventID(EventLevelAPI, EvtRtxSemaphoreNo, 0x0DU) +#define EvtRtxSemaphoreDelete EventID(EventLevelAPI, EvtRtxSemaphoreNo, 0x0EU) +#define EvtRtxSemaphoreDestroyed EventID(EventLevelOp, EvtRtxSemaphoreNo, 0x0FU) + +/// Event IDs for "RTX Memory Pool" +#define EvtRtxMemoryPoolError EventID(EventLevelError, EvtRtxMemoryPoolNo, 0x00U) +#define EvtRtxMemoryPoolNew EventID(EventLevelAPI, EvtRtxMemoryPoolNo, 0x01U) +#define EvtRtxMemoryPoolCreated EventID(EventLevelOp, EvtRtxMemoryPoolNo, 0x03U) +#define EvtRtxMemoryPoolGetName EventID(EventLevelAPI, EvtRtxMemoryPoolNo, 0x04U) +#define EvtRtxMemoryPoolAlloc EventID(EventLevelAPI, EvtRtxMemoryPoolNo, 0x06U) +#define EvtRtxMemoryPoolAllocPending EventID(EventLevelOp, EvtRtxMemoryPoolNo, 0x07U) +#define EvtRtxMemoryPoolAllocTimeout EventID(EventLevelOp, EvtRtxMemoryPoolNo, 0x08U) +#define EvtRtxMemoryPoolAllocated EventID(EventLevelOp, EvtRtxMemoryPoolNo, 0x09U) +#define EvtRtxMemoryPoolAllocFailed EventID(EventLevelOp, EvtRtxMemoryPoolNo, 0x0AU) +#define EvtRtxMemoryPoolFree EventID(EventLevelAPI, EvtRtxMemoryPoolNo, 0x0BU) +#define EvtRtxMemoryPoolDeallocated EventID(EventLevelOp, EvtRtxMemoryPoolNo, 0x0CU) +#define EvtRtxMemoryPoolFreeFailed EventID(EventLevelOp, EvtRtxMemoryPoolNo, 0x0DU) +#define EvtRtxMemoryPoolGetCapacity EventID(EventLevelAPI, EvtRtxMemoryPoolNo, 0x0EU) +#define EvtRtxMemoryPoolGetBlockSize EventID(EventLevelAPI, EvtRtxMemoryPoolNo, 0x0FU) +#define EvtRtxMemoryPoolGetCount EventID(EventLevelAPI, EvtRtxMemoryPoolNo, 0x10U) +#define EvtRtxMemoryPoolGetSpace EventID(EventLevelAPI, EvtRtxMemoryPoolNo, 0x11U) +#define EvtRtxMemoryPoolDelete EventID(EventLevelAPI, EvtRtxMemoryPoolNo, 0x12U) +#define EvtRtxMemoryPoolDestroyed EventID(EventLevelOp, EvtRtxMemoryPoolNo, 0x13U) + +/// Event IDs for "RTX Message Queue" +#define EvtRtxMessageQueueError EventID(EventLevelError, EvtRtxMessageQueueNo, 0x00U) +#define EvtRtxMessageQueueNew EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x01U) +#define EvtRtxMessageQueueCreated EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x03U) +#define EvtRtxMessageQueueGetName EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x04U) +#define EvtRtxMessageQueuePut EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x06U) +#define EvtRtxMessageQueuePutPending EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x07U) +#define EvtRtxMessageQueuePutTimeout EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x08U) +#define EvtRtxMessageQueueInsertPending EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x09U) +#define EvtRtxMessageQueueInserted EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x0AU) +#define EvtRtxMessageQueueNotInserted EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x0BU) +#define EvtRtxMessageQueueGet EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x0CU) +#define EvtRtxMessageQueueGetPending EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x0DU) +#define EvtRtxMessageQueueGetTimeout EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x0EU) +#define EvtRtxMessageQueueRetrieved EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x0FU) +#define EvtRtxMessageQueueNotRetrieved EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x10U) +#define EvtRtxMessageQueueGetCapacity EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x11U) +#define EvtRtxMessageQueueGetMsgSize EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x12U) +#define EvtRtxMessageQueueGetCount EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x13U) +#define EvtRtxMessageQueueGetSpace EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x14U) +#define EvtRtxMessageQueueReset EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x15U) +#define EvtRtxMessageQueueResetDone EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x16U) +#define EvtRtxMessageQueueDelete EventID(EventLevelAPI, EvtRtxMessageQueueNo, 0x17U) +#define EvtRtxMessageQueueDestroyed EventID(EventLevelOp, EvtRtxMessageQueueNo, 0x18U) + +#endif // RTE_Compiler_EventRecorder + +//lint -esym(522, EvrRtx*) "Functions 'EvrRtx*' can be overridden (do not lack side-effects)" + + +// ==== Memory Events ==== + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_INIT_DISABLE)) +__WEAK void EvrRtxMemoryInit (void *mem, uint32_t size, uint32_t result) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxMemoryInit, (uint32_t)mem, size, result, 0U); +#else + (void)mem; + (void)size; + (void)result; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_ALLOC_DISABLE)) +__WEAK void EvrRtxMemoryAlloc (void *mem, uint32_t size, uint32_t type, void *block) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxMemoryAlloc, (uint32_t)mem, size, type, (uint32_t)block); +#else + (void)mem; + (void)size; + (void)type; + (void)block; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_FREE_DISABLE)) +__WEAK void EvrRtxMemoryFree (void *mem, void *block, uint32_t result) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxMemoryFree, (uint32_t)mem, (uint32_t)block, result, 0U); +#else + (void)mem; + (void)block; + (void)result; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_INIT_DISABLE)) +__WEAK void EvrRtxMemoryBlockInit (osRtxMpInfo_t *mp_info, uint32_t block_count, uint32_t block_size, void *block_mem) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxMemoryBlockInit, (uint32_t)mp_info, block_count, block_size, (uint32_t)block_mem); +#else + (void)mp_info; + (void)block_count; + (void)block_size; + (void)block_mem; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_ALLOC_DISABLE)) +__WEAK void EvrRtxMemoryBlockAlloc (osRtxMpInfo_t *mp_info, void *block) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMemoryBlockAlloc, (uint32_t)mp_info, (uint32_t)block); +#else + (void)mp_info; + (void)block; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_FREE_DISABLE)) +__WEAK void EvrRtxMemoryBlockFree (osRtxMpInfo_t *mp_info, void *block, int32_t status) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxMemoryBlockFree, (uint32_t)mp_info, (uint32_t)block, (uint32_t)status, 0U); +#else + (void)mp_info; + (void)block; + (void)status; +#endif +} +#endif + + +// ==== Kernel Events ==== + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_ERROR_DISABLE)) +__WEAK void EvrRtxKernelError (int32_t status) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxKernelError, (uint32_t)status, 0U); +#else + (void)status; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZE_DISABLE)) +__WEAK void EvrRtxKernelInitialize (void) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxKernelInitialize, 0U, 0U); +#else +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZED_DISABLE)) +__WEAK void EvrRtxKernelInitialized (void) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxKernelInitialized, 0U, 0U); +#else +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_INFO_DISABLE)) +__WEAK void EvrRtxKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxKernelGetInfo, (uint32_t)version, (uint32_t)id_buf, id_size, 0U); +#else + (void)version; + (void)id_buf; + (void)id_size; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INFO_RETRIEVED_DISABLE)) +__WEAK void EvrRtxKernelInfoRetrieved (const osVersion_t *version, const char *id_buf, uint32_t id_size) { +#if defined(RTE_Compiler_EventRecorder) + if (version != NULL) { + (void)EventRecord2(EvtRtxKernelInfoRetrieved, version->api, version->kernel); + } + if (id_buf != NULL) { + (void)EventRecordData(EvtRtxKernelInfoRetrieved_Detail, id_buf, id_size); + } +#else + (void)version; + (void)id_buf; + (void)id_size; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_STATE_DISABLE)) +__WEAK void EvrRtxKernelGetState (osKernelState_t state) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxKernelGetState, (uint32_t)state, 0U); +#else + (void)state; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_START_DISABLE)) +__WEAK void EvrRtxKernelStart (void) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxKernelStart, 0U, 0U); +#else +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_STARTED_DISABLE)) +__WEAK void EvrRtxKernelStarted (void) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxKernelStarted, 0U, 0U); +#else +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCK_DISABLE)) +__WEAK void EvrRtxKernelLock (void) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxKernelLock, 0U, 0U); +#else +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCKED_DISABLE)) +__WEAK void EvrRtxKernelLocked (int32_t lock) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxKernelLocked, (uint32_t)lock, 0U); +#else + (void)lock; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_UNLOCK_DISABLE)) +__WEAK void EvrRtxKernelUnlock (void) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxKernelUnlock, 0U, 0U); +#else +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_UNLOCKED_DISABLE)) +__WEAK void EvrRtxKernelUnlocked (int32_t lock) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxKernelUnlocked, (uint32_t)lock, 0U); +#else + (void)lock; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESTORE_LOCK_DISABLE)) +__WEAK void EvrRtxKernelRestoreLock (int32_t lock) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxKernelRestoreLock, (uint32_t)lock, 0U); +#else + (void)lock; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCK_RESTORED_DISABLE)) +__WEAK void EvrRtxKernelLockRestored (int32_t lock) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxKernelLockRestored, (uint32_t)lock, 0U); +#else + (void)lock; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_SUSPEND_DISABLE)) +__WEAK void EvrRtxKernelSuspend (void) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxKernelSuspend, 0U, 0U); +#else +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_SUSPENDED_DISABLE)) +__WEAK void EvrRtxKernelSuspended (uint32_t sleep_ticks) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxKernelSuspended, sleep_ticks, 0U); +#else + (void)sleep_ticks; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESUME_DISABLE)) +__WEAK void EvrRtxKernelResume (uint32_t sleep_ticks) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxKernelResume, sleep_ticks, 0U); +#else + (void)sleep_ticks; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESUMED_DISABLE)) +__WEAK void EvrRtxKernelResumed (void) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxKernelResumed, 0U, 0U); +#else +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_COUNT_DISABLE)) +__WEAK void EvrRtxKernelGetTickCount (uint32_t count) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxKernelGetTickCount, count, 0U); +#else + (void)count; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_FREQ_DISABLE)) +__WEAK void EvrRtxKernelGetTickFreq (uint32_t freq) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxKernelGetTickFreq, freq, 0U); +#else + (void)freq; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE)) +__WEAK void EvrRtxKernelGetSysTimerCount (uint32_t count) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxKernelGetSysTimerCount, count, 0U); +#else + (void)count; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE)) +__WEAK void EvrRtxKernelGetSysTimerFreq (uint32_t freq) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxKernelGetSysTimerFreq, freq, 0U); +#else + (void)freq; +#endif +} +#endif + + +// ==== Thread Events ==== + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_ERROR_DISABLE)) +__WEAK void EvrRtxThreadError (osThreadId_t thread_id, int32_t status) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadError, (uint32_t)thread_id, (uint32_t)status); +#else + (void)thread_id; + (void)status; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_NEW_DISABLE)) +__WEAK void EvrRtxThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxThreadNew, (uint32_t)func, (uint32_t)argument, (uint32_t)attr, 0U); +#else + (void)func; + (void)argument; + (void)attr; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_CREATED_DISABLE)) +__WEAK void EvrRtxThreadCreated (osThreadId_t thread_id, uint32_t thread_addr, const char *name) { +#if defined(RTE_Compiler_EventRecorder) + if (name != NULL) { + (void)EventRecord2(EvtRtxThreadCreated_Name, (uint32_t)thread_id, (uint32_t)name); + } else { + (void)EventRecord2(EvtRtxThreadCreated_Addr, (uint32_t)thread_id, thread_addr); + } +#else + (void)thread_id; + (void)thread_addr; + (void)name; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_NAME_DISABLE)) +__WEAK void EvrRtxThreadGetName (osThreadId_t thread_id, const char *name) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadGetName, (uint32_t)thread_id, (uint32_t)name); +#else + (void)thread_id; + (void)name; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_ID_DISABLE)) +__WEAK void EvrRtxThreadGetId (osThreadId_t thread_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadGetId, (uint32_t)thread_id, 0U); +#else + (void)thread_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STATE_DISABLE)) +__WEAK void EvrRtxThreadGetState (osThreadId_t thread_id, osThreadState_t state) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadGetState, (uint32_t)thread_id, (uint32_t)state); +#else + (void)thread_id; + (void)state; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STACK_SIZE_DISABLE)) +__WEAK void EvrRtxThreadGetStackSize (osThreadId_t thread_id, uint32_t stack_size) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadGetStackSize, (uint32_t)thread_id, stack_size); +#else + (void)thread_id; + (void)stack_size; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STACK_SPACE_DISABLE)) +__WEAK void EvrRtxThreadGetStackSpace (osThreadId_t thread_id, uint32_t stack_space) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadGetStackSpace, (uint32_t)thread_id, stack_space); +#else + (void)thread_id; + (void)stack_space; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SET_PRIORITY_DISABLE)) +__WEAK void EvrRtxThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadSetPriority, (uint32_t)thread_id, (uint32_t)priority); +#else + (void)thread_id; + (void)priority; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PRIORITY_UPDATED_DISABLE)) +__WEAK void EvrRtxThreadPriorityUpdated (osThreadId_t thread_id, osPriority_t priority) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadPriorityUpdated, (uint32_t)thread_id, (uint32_t)priority); +#else + (void)thread_id; + (void)priority; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_PRIORITY_DISABLE)) +__WEAK void EvrRtxThreadGetPriority (osThreadId_t thread_id, osPriority_t priority) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadGetPriority, (uint32_t)thread_id, (uint32_t)priority); +#else + (void)thread_id; + (void)priority; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_YIELD_DISABLE)) +__WEAK void EvrRtxThreadYield (void) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadYield, 0U, 0U); +#else +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPEND_DISABLE)) +__WEAK void EvrRtxThreadSuspend (osThreadId_t thread_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadSuspend, (uint32_t)thread_id, 0U); +#else + (void)thread_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPENDED_DISABLE)) +__WEAK void EvrRtxThreadSuspended (osThreadId_t thread_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadSuspended, (uint32_t)thread_id, 0U); +#else + (void)thread_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUME_DISABLE)) +__WEAK void EvrRtxThreadResume (osThreadId_t thread_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadResume, (uint32_t)thread_id, 0U); +#else + (void)thread_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUMED_DISABLE)) +__WEAK void EvrRtxThreadResumed (osThreadId_t thread_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadResumed, (uint32_t)thread_id, 0U); +#else + (void)thread_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DETACH_DISABLE)) +__WEAK void EvrRtxThreadDetach (osThreadId_t thread_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadDetach, (uint32_t)thread_id, 0U); +#else + (void)thread_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DETACHED_DISABLE)) +__WEAK void EvrRtxThreadDetached (osThreadId_t thread_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadDetached, (uint32_t)thread_id, 0U); +#else + (void)thread_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOIN_DISABLE)) +__WEAK void EvrRtxThreadJoin (osThreadId_t thread_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadJoin, (uint32_t)thread_id, 0U); +#else + (void)thread_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOIN_PENDING_DISABLE)) +__WEAK void EvrRtxThreadJoinPending (osThreadId_t thread_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadJoinPending, (uint32_t)thread_id, 0U); +#else + (void)thread_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOINED_DISABLE)) +__WEAK void EvrRtxThreadJoined (osThreadId_t thread_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadJoined, (uint32_t)thread_id, 0U); +#else + (void)thread_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_BLOCKED_DISABLE)) +__WEAK void EvrRtxThreadBlocked (osThreadId_t thread_id, uint32_t timeout) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadBlocked, (uint32_t)thread_id, timeout); +#else + (void)thread_id; + (void)timeout; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_UNBLOCKED_DISABLE)) +__WEAK void EvrRtxThreadUnblocked (osThreadId_t thread_id, uint32_t ret_val) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadUnblocked, (uint32_t)thread_id, ret_val); +#else + (void)thread_id; + (void)ret_val; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PREEMPTED_DISABLE)) +__WEAK void EvrRtxThreadPreempted (osThreadId_t thread_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadPreempted, (uint32_t)thread_id, 0U); +#else + (void)thread_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SWITCHED_DISABLE)) +__WEAK void EvrRtxThreadSwitched (osThreadId_t thread_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadSwitched, (uint32_t)thread_id, 0U); +#else + (void)thread_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_EXIT_DISABLE)) +__WEAK void EvrRtxThreadExit (void) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadExit, 0U, 0U); +#else +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_TERMINATE_DISABLE)) +__WEAK void EvrRtxThreadTerminate (osThreadId_t thread_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadTerminate, (uint32_t)thread_id, 0U); +#else + (void)thread_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DESTROYED_DISABLE)) +__WEAK void EvrRtxThreadDestroyed (osThreadId_t thread_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadDestroyed, (uint32_t)thread_id, 0U); +#else + (void)thread_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_COUNT_DISABLE)) +__WEAK void EvrRtxThreadGetCount (uint32_t count) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadGetCount, count, 0U); +#else + (void)count; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_ENUMERATE_DISABLE)) +__WEAK void EvrRtxThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items, uint32_t count) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxThreadEnumerate, (uint32_t)thread_array, array_items, count, 0U); +#else + (void)thread_array; + (void)array_items; + (void)count; +#endif +} +#endif + + +// ==== Thread Flags Events ==== + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_ERROR_DISABLE)) +__WEAK void EvrRtxThreadFlagsError (osThreadId_t thread_id, int32_t status) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadFlagsError, (uint32_t)thread_id, (uint32_t)status); +#else + (void)thread_id; + (void)status; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_SET_DISABLE)) +__WEAK void EvrRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadFlagsSet, (uint32_t)thread_id, flags); +#else + (void)thread_id; + (void)flags; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_SET_DONE_DISABLE)) +__WEAK void EvrRtxThreadFlagsSetDone (osThreadId_t thread_id, uint32_t thread_flags) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadFlagsSetDone, (uint32_t)thread_id, thread_flags); +#else + (void)thread_id; + (void)thread_flags; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_CLEAR_DISABLE)) +__WEAK void EvrRtxThreadFlagsClear (uint32_t flags) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadFlagsClear, flags, 0U); +#else + (void)flags; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_CLEAR_DONE_DISABLE)) +__WEAK void EvrRtxThreadFlagsClearDone (uint32_t thread_flags) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadFlagsClearDone, thread_flags, 0U); +#else + (void)thread_flags; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_GET_DISABLE)) +__WEAK void EvrRtxThreadFlagsGet (uint32_t thread_flags) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadFlagsGet, thread_flags, 0U); +#else + (void)thread_flags; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_DISABLE)) +__WEAK void EvrRtxThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxThreadFlagsWait, flags, options, timeout, 0U); +#else + (void)flags; + (void)options; + (void)timeout; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_PENDING_DISABLE)) +__WEAK void EvrRtxThreadFlagsWaitPending (uint32_t flags, uint32_t options, uint32_t timeout) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxThreadFlagsWaitPending, flags, options, timeout, 0U); +#else + (void)flags; + (void)options; + (void)timeout; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_TIMEOUT_DISABLE)) +__WEAK void EvrRtxThreadFlagsWaitTimeout (osThreadId_t thread_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadFlagsWaitTimeout, (uint32_t)thread_id, 0U); +#else + (void)thread_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_COMPLETED_DISABLE)) +__WEAK void EvrRtxThreadFlagsWaitCompleted (uint32_t flags, uint32_t options, uint32_t thread_flags, osThreadId_t thread_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxThreadFlagsWaitCompleted, flags, options, thread_flags, (uint32_t)thread_id); +#else + (void)flags; + (void)options; + (void)thread_flags; + (void)thread_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_NOT_COMPLETED_DISABLE)) +__WEAK void EvrRtxThreadFlagsWaitNotCompleted (uint32_t flags, uint32_t options) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxThreadFlagsWaitNotCompleted, flags, options); +#else + (void)flags; + (void)options; +#endif +} +#endif + + +// ==== Generic Wait Events ==== + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_ERROR_DISABLE)) +__WEAK void EvrRtxDelayError (int32_t status) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxDelayError, (uint32_t)status, 0U); +#else + (void)status; +#endif +} +#endif + + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_DISABLE)) +__WEAK void EvrRtxDelay (uint32_t ticks) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxDelay, ticks, 0U); +#else + (void)ticks; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_UNTIL_DISABLE)) +__WEAK void EvrRtxDelayUntil (uint32_t ticks) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxDelayUntil, ticks, 0U); +#else + (void)ticks; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_STARTED_DISABLE)) +__WEAK void EvrRtxDelayStarted (uint32_t ticks) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxDelayStarted, ticks, 0U); +#else + (void)ticks; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_UNTIL_STARTED_DISABLE)) +__WEAK void EvrRtxDelayUntilStarted (uint32_t ticks) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxDelayUntilStarted, ticks, 0U); +#else + (void)ticks; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_COMPLETED_DISABLE)) +__WEAK void EvrRtxDelayCompleted (osThreadId_t thread_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxDelayCompleted, (uint32_t)thread_id, 0U); +#else + (void)thread_id; +#endif +} +#endif + + +// ==== Timer Events ==== + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_ERROR_DISABLE)) +__WEAK void EvrRtxTimerError (osTimerId_t timer_id, int32_t status) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxTimerError, (uint32_t)timer_id, (uint32_t)status); +#else + (void)timer_id; + (void)status; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_CALLBACK_DISABLE)) +__WEAK void EvrRtxTimerCallback (osTimerFunc_t func, void *argument) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxTimerCallback, (uint32_t)func, (uint32_t)argument); +#else + (void)func; + (void)argument; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_NEW_DISABLE)) +__WEAK void EvrRtxTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxTimerNew, (uint32_t)func, (uint32_t)type, (uint32_t)argument, (uint32_t)attr); +#else + (void)func; + (void)type; + (void)argument; + (void)attr; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_CREATED_DISABLE)) +__WEAK void EvrRtxTimerCreated (osTimerId_t timer_id, const char *name) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxTimerCreated, (uint32_t)timer_id, (uint32_t)name); +#else + (void)timer_id; + (void)name; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_GET_NAME_DISABLE)) +__WEAK void EvrRtxTimerGetName (osTimerId_t timer_id, const char *name) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxTimerGetName, (uint32_t)timer_id, (uint32_t)name); +#else + (void)timer_id; + (void)name; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_START_DISABLE)) +__WEAK void EvrRtxTimerStart (osTimerId_t timer_id, uint32_t ticks) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxTimerStart, (uint32_t)timer_id, ticks); +#else + (void)timer_id; + (void)ticks; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STARTED_DISABLE)) +__WEAK void EvrRtxTimerStarted (osTimerId_t timer_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxTimerStarted, (uint32_t)timer_id, 0U); +#else + (void)timer_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOP_DISABLE)) +__WEAK void EvrRtxTimerStop (osTimerId_t timer_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxTimerStop, (uint32_t)timer_id, 0U); +#else + (void)timer_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOPPED_DISABLE)) +__WEAK void EvrRtxTimerStopped (osTimerId_t timer_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxTimerStopped, (uint32_t)timer_id, 0U); +#else + (void)timer_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_IS_RUNNING_DISABLE)) +__WEAK void EvrRtxTimerIsRunning (osTimerId_t timer_id, uint32_t running) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxTimerIsRunning, (uint32_t)timer_id, running); +#else + (void)timer_id; + (void)running; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DELETE_DISABLE)) +__WEAK void EvrRtxTimerDelete (osTimerId_t timer_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxTimerDelete, (uint32_t)timer_id, 0U); +#else + (void)timer_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DESTROYED_DISABLE)) +__WEAK void EvrRtxTimerDestroyed (osTimerId_t timer_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxTimerDestroyed, (uint32_t)timer_id, 0U); +#else + (void)timer_id; +#endif +} +#endif + + +// ==== Event Flags Events ==== + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_ERROR_DISABLE)) +__WEAK void EvrRtxEventFlagsError (osEventFlagsId_t ef_id, int32_t status) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxEventFlagsError, (uint32_t)ef_id, (uint32_t)status); +#else + (void)ef_id; + (void)status; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_NEW_DISABLE)) +__WEAK void EvrRtxEventFlagsNew (const osEventFlagsAttr_t *attr) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxEventFlagsNew, (uint32_t)attr, 0U); +#else + (void)attr; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CREATED_DISABLE)) +__WEAK void EvrRtxEventFlagsCreated (osEventFlagsId_t ef_id, const char *name) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxEventFlagsCreated, (uint32_t)ef_id, (uint32_t)name); +#else + (void)ef_id; + (void)name; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_GET_NAME_DISABLE)) +__WEAK void EvrRtxEventFlagsGetName (osEventFlagsId_t ef_id, const char *name) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxEventFlagsGetName, (uint32_t)ef_id, (uint32_t)name); +#else + (void)ef_id; + (void)name; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_SET_DISABLE)) +__WEAK void EvrRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxEventFlagsSet, (uint32_t)ef_id, flags); +#else + (void)ef_id; + (void)flags; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_SET_DONE_DISABLE)) +__WEAK void EvrRtxEventFlagsSetDone (osEventFlagsId_t ef_id, uint32_t event_flags) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxEventFlagsSetDone, (uint32_t)ef_id, event_flags); +#else + (void)ef_id; + (void)event_flags; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CLEAR_DISABLE)) +__WEAK void EvrRtxEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxEventFlagsClear, (uint32_t)ef_id, flags); +#else + (void)ef_id; + (void)flags; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CLEAR_DONE_DISABLE)) +__WEAK void EvrRtxEventFlagsClearDone (osEventFlagsId_t ef_id, uint32_t event_flags) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxEventFlagsClearDone, (uint32_t)ef_id, event_flags); +#else + (void)ef_id; + (void)event_flags; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_GET_DISABLE)) +__WEAK void EvrRtxEventFlagsGet (osEventFlagsId_t ef_id, uint32_t event_flags) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxEventFlagsGet, (uint32_t)ef_id, event_flags); +#else + (void)ef_id; + (void)event_flags; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_DISABLE)) +__WEAK void EvrRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxEventFlagsWait, (uint32_t)ef_id, flags, options, timeout); +#else + (void)ef_id; + (void)flags; + (void)options; + (void)timeout; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_PENDING_DISABLE)) +__WEAK void EvrRtxEventFlagsWaitPending (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxEventFlagsWaitPending, (uint32_t)ef_id, flags, options, timeout); +#else + (void)ef_id; + (void)flags; + (void)options; + (void)timeout; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_TIMEOUT_DISABLE)) +__WEAK void EvrRtxEventFlagsWaitTimeout (osEventFlagsId_t ef_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxEventFlagsWaitTimeout, (uint32_t)ef_id, 0U); +#else + (void)ef_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_COMPLETED_DISABLE)) +__WEAK void EvrRtxEventFlagsWaitCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t event_flags) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxEventFlagsWaitCompleted, (uint32_t)ef_id, flags, options, event_flags); +#else + (void)ef_id; + (void)flags; + (void)options; + (void)event_flags; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_NOT_COMPLETED_DISABLE)) +__WEAK void EvrRtxEventFlagsWaitNotCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxEventFlagsWaitNotCompleted, (uint32_t)ef_id, flags, options, 0U); +#else + (void)ef_id; + (void)flags; + (void)options; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_DELETE_DISABLE)) +__WEAK void EvrRtxEventFlagsDelete (osEventFlagsId_t ef_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxEventFlagsDelete, (uint32_t)ef_id, 0U); +#else + (void)ef_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_DESTROYED_DISABLE)) +__WEAK void EvrRtxEventFlagsDestroyed (osEventFlagsId_t ef_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxEventFlagsDestroyed, (uint32_t)ef_id, 0U); +#else + (void)ef_id; +#endif +} +#endif + + +// ==== Mutex Events ==== + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ERROR_DISABLE)) +__WEAK void EvrRtxMutexError (osMutexId_t mutex_id, int32_t status) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMutexError, (uint32_t)mutex_id, (uint32_t)status); +#else + (void)mutex_id; + (void)status; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_NEW_DISABLE)) +__WEAK void EvrRtxMutexNew (const osMutexAttr_t *attr) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMutexNew, (uint32_t)attr, 0U); +#else + (void)attr; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_CREATED_DISABLE)) +__WEAK void EvrRtxMutexCreated (osMutexId_t mutex_id, const char *name) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMutexCreated, (uint32_t)mutex_id, (uint32_t)name); +#else + (void)mutex_id; + (void)name; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_GET_NAME_DISABLE)) +__WEAK void EvrRtxMutexGetName (osMutexId_t mutex_id, const char *name) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMutexGetName, (uint32_t)mutex_id, (uint32_t)name); +#else + (void)mutex_id; + (void)name; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_DISABLE)) +__WEAK void EvrRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMutexAcquire, (uint32_t)mutex_id, timeout); +#else + (void)mutex_id; + (void)timeout; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_PENDING_DISABLE)) +__WEAK void EvrRtxMutexAcquirePending (osMutexId_t mutex_id, uint32_t timeout) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMutexAcquirePending, (uint32_t)mutex_id, timeout); +#else + (void)mutex_id; + (void)timeout; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_TIMEOUT_DISABLE)) +__WEAK void EvrRtxMutexAcquireTimeout (osMutexId_t mutex_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMutexAcquireTimeout, (uint32_t)mutex_id, 0U); +#else + (void)mutex_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRED_DISABLE)) +__WEAK void EvrRtxMutexAcquired (osMutexId_t mutex_id, uint32_t lock) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMutexAcquired, (uint32_t)mutex_id, lock); +#else + (void)mutex_id; + (void)lock; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_NOT_ACQUIRED_DISABLE)) +__WEAK void EvrRtxMutexNotAcquired (osMutexId_t mutex_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMutexNotAcquired, (uint32_t)mutex_id, 0U); +#else + (void)mutex_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_RELEASE_DISABLE)) +__WEAK void EvrRtxMutexRelease (osMutexId_t mutex_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMutexRelease, (uint32_t)mutex_id, 0U); +#else + (void)mutex_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_RELEASED_DISABLE)) +__WEAK void EvrRtxMutexReleased (osMutexId_t mutex_id, uint32_t lock) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMutexReleased, (uint32_t)mutex_id, lock); +#else + (void)mutex_id; + (void)lock; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_GET_OWNER_DISABLE)) +__WEAK void EvrRtxMutexGetOwner (osMutexId_t mutex_id, osThreadId_t thread_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMutexGetOwner, (uint32_t)mutex_id, (uint32_t)thread_id); +#else + (void)mutex_id; + (void)thread_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_DELETE_DISABLE)) +__WEAK void EvrRtxMutexDelete (osMutexId_t mutex_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMutexDelete, (uint32_t)mutex_id, 0U); +#else + (void)mutex_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_DESTROYED_DISABLE)) +__WEAK void EvrRtxMutexDestroyed (osMutexId_t mutex_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMutexDestroyed, (uint32_t)mutex_id, 0U); +#else + (void)mutex_id; +#endif +} +#endif + + +// ==== Semaphore Events ==== + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ERROR_DISABLE)) +__WEAK void EvrRtxSemaphoreError (osSemaphoreId_t semaphore_id, int32_t status) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxSemaphoreError, (uint32_t)semaphore_id, (uint32_t)status); +#else + (void)semaphore_id; + (void)status; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_NEW_DISABLE)) +__WEAK void EvrRtxSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxSemaphoreNew, max_count, initial_count, (uint32_t)attr, 0U); +#else + (void)max_count; + (void)initial_count; + (void)attr; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_CREATED_DISABLE)) +__WEAK void EvrRtxSemaphoreCreated (osSemaphoreId_t semaphore_id, const char *name) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxSemaphoreCreated, (uint32_t)semaphore_id, (uint32_t)name); +#else + (void)semaphore_id; + (void)name; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_GET_NAME_DISABLE)) +__WEAK void EvrRtxSemaphoreGetName (osSemaphoreId_t semaphore_id, const char *name) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxSemaphoreGetName, (uint32_t)semaphore_id, (uint32_t)name); +#else +#endif + (void)semaphore_id; + (void)name; +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_DISABLE)) +__WEAK void EvrRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxSemaphoreAcquire, (uint32_t)semaphore_id, timeout); +#else + (void)semaphore_id; + (void)timeout; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_PENDING_DISABLE)) +__WEAK void EvrRtxSemaphoreAcquirePending (osSemaphoreId_t semaphore_id, uint32_t timeout) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxSemaphoreAcquirePending, (uint32_t)semaphore_id, (uint32_t)timeout); +#else + (void)semaphore_id; + (void)timeout; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_TIMEOUT_DISABLE)) +__WEAK void EvrRtxSemaphoreAcquireTimeout (osSemaphoreId_t semaphore_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxSemaphoreAcquireTimeout, (uint32_t)semaphore_id, 0U); +#else + (void)semaphore_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRED_DISABLE)) +__WEAK void EvrRtxSemaphoreAcquired (osSemaphoreId_t semaphore_id, uint32_t tokens) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxSemaphoreAcquired, (uint32_t)semaphore_id, tokens); +#else + (void)semaphore_id; + (void)tokens; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_NOT_ACQUIRED_DISABLE)) +__WEAK void EvrRtxSemaphoreNotAcquired (osSemaphoreId_t semaphore_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxSemaphoreNotAcquired, (uint32_t)semaphore_id, 0U); +#else + (void)semaphore_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASE_DISABLE)) +__WEAK void EvrRtxSemaphoreRelease (osSemaphoreId_t semaphore_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxSemaphoreRelease, (uint32_t)semaphore_id, 0U); +#else + (void)semaphore_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASED_DISABLE)) +__WEAK void EvrRtxSemaphoreReleased (osSemaphoreId_t semaphore_id, uint32_t tokens) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxSemaphoreReleased, (uint32_t)semaphore_id, tokens); +#else + (void)semaphore_id; + (void)tokens; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_GET_COUNT_DISABLE)) +__WEAK void EvrRtxSemaphoreGetCount (osSemaphoreId_t semaphore_id, uint32_t count) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxSemaphoreGetCount, (uint32_t)semaphore_id, count); +#else + (void)semaphore_id; + (void)count; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_DELETE_DISABLE)) +__WEAK void EvrRtxSemaphoreDelete (osSemaphoreId_t semaphore_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxSemaphoreDelete, (uint32_t)semaphore_id, 0U); +#else + (void)semaphore_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_DESTROYED_DISABLE)) +__WEAK void EvrRtxSemaphoreDestroyed (osSemaphoreId_t semaphore_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxSemaphoreDestroyed, (uint32_t)semaphore_id, 0U); +#else + (void)semaphore_id; +#endif +} +#endif + + +// ==== Memory Pool Events ==== + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ERROR_DISABLE)) +__WEAK void EvrRtxMemoryPoolError (osMemoryPoolId_t mp_id, int32_t status) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMemoryPoolError, (uint32_t)mp_id, (uint32_t)status); +#else + (void)mp_id; + (void)status; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_NEW_DISABLE)) +__WEAK void EvrRtxMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxMemoryPoolNew, block_count, block_size, (uint32_t)attr, 0U); +#else + (void)block_count; + (void)block_size; + (void)attr; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_CREATED_DISABLE)) +__WEAK void EvrRtxMemoryPoolCreated (osMemoryPoolId_t mp_id, const char *name) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMemoryPoolCreated, (uint32_t)mp_id, (uint32_t)name); +#else + (void)mp_id; + (void)name; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_NAME_DISABLE)) +__WEAK void EvrRtxMemoryPoolGetName (osMemoryPoolId_t mp_id, const char *name) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMemoryPoolGetName, (uint32_t)mp_id, (uint32_t)name); +#else + (void)mp_id; + (void)name; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_DISABLE)) +__WEAK void EvrRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMemoryPoolAlloc, (uint32_t)mp_id, timeout); +#else + (void)mp_id; + (void)timeout; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_PENDING_DISABLE)) +__WEAK void EvrRtxMemoryPoolAllocPending (osMemoryPoolId_t mp_id, uint32_t timeout) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMemoryPoolAllocPending, (uint32_t)mp_id, timeout); +#else + (void)mp_id; + (void)timeout; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_TIMEOUT_DISABLE)) +__WEAK void EvrRtxMemoryPoolAllocTimeout (osMemoryPoolId_t mp_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMemoryPoolAllocTimeout, (uint32_t)mp_id, 0U); +#else + (void)mp_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOCATED_DISABLE)) +__WEAK void EvrRtxMemoryPoolAllocated (osMemoryPoolId_t mp_id, void *block) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMemoryPoolAllocated, (uint32_t)mp_id, (uint32_t)block); +#else + (void)mp_id; + (void)block; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_FAILED_DISABLE)) +__WEAK void EvrRtxMemoryPoolAllocFailed (osMemoryPoolId_t mp_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMemoryPoolAllocFailed, (uint32_t)mp_id, 0U); +#else + (void)mp_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_FREE_DISABLE)) +__WEAK void EvrRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMemoryPoolFree, (uint32_t)mp_id, (uint32_t)block); +#else + (void)mp_id; + (void)block; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DEALLOCATED_DISABLE)) +__WEAK void EvrRtxMemoryPoolDeallocated (osMemoryPoolId_t mp_id, void *block) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMemoryPoolDeallocated, (uint32_t)mp_id, (uint32_t)block); +#else + (void)mp_id; + (void)block; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_FREE_FAILED_DISABLE)) +__WEAK void EvrRtxMemoryPoolFreeFailed (osMemoryPoolId_t mp_id, void *block) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMemoryPoolFreeFailed, (uint32_t)mp_id, (uint32_t)block); +#else + (void)mp_id; + (void)block; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_CAPACITY_DISABLE)) +__WEAK void EvrRtxMemoryPoolGetCapacity (osMemoryPoolId_t mp_id, uint32_t capacity) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMemoryPoolGetCapacity, (uint32_t)mp_id, capacity); +#else + (void)mp_id; + (void)capacity; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_BLOCK_SZIE_DISABLE)) +__WEAK void EvrRtxMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id, uint32_t block_size) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMemoryPoolGetBlockSize, (uint32_t)mp_id, block_size); +#else + (void)mp_id; + (void)block_size; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_COUNT_DISABLE)) +__WEAK void EvrRtxMemoryPoolGetCount (osMemoryPoolId_t mp_id, uint32_t count) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMemoryPoolGetCount, (uint32_t)mp_id, count); +#else + (void)mp_id; + (void)count; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_SPACE_DISABLE)) +__WEAK void EvrRtxMemoryPoolGetSpace (osMemoryPoolId_t mp_id, uint32_t space) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMemoryPoolGetSpace, (uint32_t)mp_id, space); +#else + (void)mp_id; + (void)space; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DELETE_DISABLE)) +__WEAK void EvrRtxMemoryPoolDelete (osMemoryPoolId_t mp_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMemoryPoolDelete, (uint32_t)mp_id, 0U); +#else + (void)mp_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DESTROYED_DISABLE)) +__WEAK void EvrRtxMemoryPoolDestroyed (osMemoryPoolId_t mp_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMemoryPoolDestroyed, (uint32_t)mp_id, 0U); +#else + (void)mp_id; +#endif +} +#endif + + +// ==== Message Queue Events ==== + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_ERROR_DISABLE)) +__WEAK void EvrRtxMessageQueueError (osMessageQueueId_t mq_id, int32_t status) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2 (EvtRtxMessageQueueError, (uint32_t)mq_id, (uint32_t)status); +#else + (void)mq_id; + (void)status; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NEW_DISABLE)) +__WEAK void EvrRtxMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxMessageQueueNew, msg_count, msg_size, (uint32_t)attr, 0U); +#else + (void)msg_count; + (void)msg_size; + (void)attr; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_CREATED_DISABLE)) +__WEAK void EvrRtxMessageQueueCreated (osMessageQueueId_t mq_id, const char *name) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMessageQueueCreated, (uint32_t)mq_id, (uint32_t)name); +#else + (void)mq_id; + (void)name; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_NAME_DISABLE)) +__WEAK void EvrRtxMessageQueueGetName (osMessageQueueId_t mq_id, const char *name) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMessageQueueGetName, (uint32_t)mq_id, (uint32_t)name); +#else + (void)mq_id; + (void)name; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_DISABLE)) +__WEAK void EvrRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxMessageQueuePut, (uint32_t)mq_id, (uint32_t)msg_ptr, (uint32_t)msg_prio, timeout); +#else + (void)mq_id; + (void)msg_ptr; + (void)msg_prio; + (void)timeout; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_PENDING_DISABLE)) +__WEAK void EvrRtxMessageQueuePutPending (osMessageQueueId_t mq_id, const void *msg_ptr, uint32_t timeout) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxMessageQueuePutPending, (uint32_t)mq_id, (uint32_t)msg_ptr, timeout, 0U); +#else + (void)mq_id; + (void)msg_ptr; + (void)timeout; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_TIMEOUT_DISABLE)) +__WEAK void EvrRtxMessageQueuePutTimeout (osMessageQueueId_t mq_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMessageQueuePutTimeout, (uint32_t)mq_id, 0U); +#else + (void)mq_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_INSERT_PENDING_DISABLE)) +__WEAK void EvrRtxMessageQueueInsertPending (osMessageQueueId_t mq_id, const void *msg_ptr) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMessageQueueInsertPending, (uint32_t)mq_id, (uint32_t)msg_ptr); +#else + (void)mq_id; + (void)msg_ptr; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_INSERTED_DISABLE)) +__WEAK void EvrRtxMessageQueueInserted (osMessageQueueId_t mq_id, const void *msg_ptr) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMessageQueueInserted, (uint32_t)mq_id, (uint32_t)msg_ptr); +#else + (void)mq_id; + (void)msg_ptr; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NOT_INSERTED_DISABLE)) +__WEAK void EvrRtxMessageQueueNotInserted (osMessageQueueId_t mq_id, const void *msg_ptr) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMessageQueueNotInserted, (uint32_t)mq_id, (uint32_t)msg_ptr); +#else + (void)mq_id; + (void)msg_ptr; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_DISABLE)) +__WEAK void EvrRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxMessageQueueGet, (uint32_t)mq_id, (uint32_t)msg_ptr, (uint32_t)msg_prio, timeout); +#else + (void)mq_id; + (void)msg_ptr; + (void)msg_prio; + (void)timeout; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_PENDING_DISABLE)) +__WEAK void EvrRtxMessageQueueGetPending (osMessageQueueId_t mq_id, void *msg_ptr, uint32_t timeout) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord4(EvtRtxMessageQueueGetPending, (uint32_t)mq_id, (uint32_t)msg_ptr, timeout, 0U); +#else + (void)mq_id; + (void)msg_ptr; + (void)timeout; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_TIMEOUT_DISABLE)) +__WEAK void EvrRtxMessageQueueGetTimeout (osMessageQueueId_t mq_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMessageQueueGetTimeout, (uint32_t)mq_id, 0U); +#else + (void)mq_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RETRIEVED_DISABLE)) +__WEAK void EvrRtxMessageQueueRetrieved (osMessageQueueId_t mq_id, void *msg_ptr) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMessageQueueRetrieved, (uint32_t)mq_id, (uint32_t)msg_ptr); +#else + (void)mq_id; + (void)msg_ptr; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NOT_RETRIEVED_DISABLE)) +__WEAK void EvrRtxMessageQueueNotRetrieved (osMessageQueueId_t mq_id, void *msg_ptr) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMessageQueueNotRetrieved, (uint32_t)mq_id, (uint32_t)msg_ptr); +#else + (void)mq_id; + (void)msg_ptr; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_CAPACITY_DISABLE)) +__WEAK void EvrRtxMessageQueueGetCapacity (osMessageQueueId_t mq_id, uint32_t capacity) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMessageQueueGetCapacity, (uint32_t)mq_id, capacity); +#else + (void)mq_id; + (void)capacity; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_MSG_SIZE_DISABLE)) +__WEAK void EvrRtxMessageQueueGetMsgSize (osMessageQueueId_t mq_id, uint32_t msg_size) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMessageQueueGetMsgSize, (uint32_t)mq_id, msg_size); +#else + (void)mq_id; + (void)msg_size; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_COUNT_DISABLE)) +__WEAK void EvrRtxMessageQueueGetCount (osMessageQueueId_t mq_id, uint32_t count) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMessageQueueGetCount, (uint32_t)mq_id, count); +#else + (void)mq_id; + (void)count; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_SPACE_DISABLE)) +__WEAK void EvrRtxMessageQueueGetSpace (osMessageQueueId_t mq_id, uint32_t space) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMessageQueueGetSpace, (uint32_t)mq_id, space); +#else + (void)mq_id; + (void)space; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RESET_DISABLE)) +__WEAK void EvrRtxMessageQueueReset (osMessageQueueId_t mq_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMessageQueueReset, (uint32_t)mq_id, 0U); +#else + (void)mq_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RESET_DONE_DISABLE)) +__WEAK void EvrRtxMessageQueueResetDone (osMessageQueueId_t mq_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMessageQueueResetDone, (uint32_t)mq_id, 0U); +#else + (void)mq_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_DELETE_DISABLE)) +__WEAK void EvrRtxMessageQueueDelete (osMessageQueueId_t mq_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMessageQueueDelete, (uint32_t)mq_id, 0U); +#else + (void)mq_id; +#endif +} +#endif + +#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_DESTROYED_DISABLE)) +__WEAK void EvrRtxMessageQueueDestroyed (osMessageQueueId_t mq_id) { +#if defined(RTE_Compiler_EventRecorder) + (void)EventRecord2(EvtRtxMessageQueueDestroyed, (uint32_t)mq_id, 0U); +#else + (void)mq_id; +#endif +} +#endif diff --git a/source/rtos2/RTX/Source/rtx_kernel.c b/source/rtos2/RTX/Source/rtx_kernel.c new file mode 100644 index 000000000..303fc5442 --- /dev/null +++ b/source/rtos2/RTX/Source/rtx_kernel.c @@ -0,0 +1,680 @@ +/* + * Copyright (c) 2013-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Kernel functions + * + * ----------------------------------------------------------------------------- + */ + +#include "rtx_lib.h" + + +// OS Runtime Information +osRtxInfo_t osRtxInfo __attribute__((section(".data.os"))) = +//lint -e{785} "Initialize only OS ID, OS Version and Kernel State" +{ .os_id = osRtxKernelId, .version = osRtxVersionKernel, .kernel.state = osRtxKernelInactive }; + + +// ==== Helper functions ==== + +/// Block Kernel (disable: thread switching, time tick, post ISR processing). +static void KernelBlock (void) { + + OS_Tick_Disable(); + + osRtxInfo.kernel.blocked = 1U; + __DSB(); + + if (GetPendSV() != 0U) { + ClrPendSV(); + osRtxInfo.kernel.pendSV = 1U; + } +} + +/// Unblock Kernel +static void KernelUnblock (void) { + + osRtxInfo.kernel.blocked = 0U; + __DSB(); + + if (osRtxInfo.kernel.pendSV != 0U) { + osRtxInfo.kernel.pendSV = 0U; + SetPendSV(); + } + + OS_Tick_Enable(); +} + + +// ==== Service Calls ==== + +/// Initialize the RTOS Kernel. +/// \note API identical to osKernelInitialize +static osStatus_t svcRtxKernelInitialize (void) { + + if (osRtxInfo.kernel.state == osRtxKernelReady) { + EvrRtxKernelInitialized(); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osOK; + } + if (osRtxInfo.kernel.state != osRtxKernelInactive) { + EvrRtxKernelError((int32_t)osError); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osError; + } + +#if (DOMAIN_NS == 1) + // Initialize Secure Process Stack + if (TZ_InitContextSystem_S() == 0U) { + EvrRtxKernelError(osRtxErrorTZ_InitContext_S); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osError; + } +#endif + + // Initialize osRtxInfo + memset(&osRtxInfo.kernel, 0, sizeof(osRtxInfo) - offsetof(osRtxInfo_t, kernel)); + + osRtxInfo.isr_queue.data = osRtxConfig.isr_queue.data; + osRtxInfo.isr_queue.max = osRtxConfig.isr_queue.max; + + osRtxInfo.thread.robin.timeout = osRtxConfig.robin_timeout; + + // Initialize Memory Pools (Variable Block Size) + if (osRtxMemoryInit(osRtxConfig.mem.common_addr, osRtxConfig.mem.common_size) != 0U) { + osRtxInfo.mem.common = osRtxConfig.mem.common_addr; + } + if (osRtxMemoryInit(osRtxConfig.mem.stack_addr, osRtxConfig.mem.stack_size) != 0U) { + osRtxInfo.mem.stack = osRtxConfig.mem.stack_addr; + } else { + osRtxInfo.mem.stack = osRtxInfo.mem.common; + } + if (osRtxMemoryInit(osRtxConfig.mem.mp_data_addr, osRtxConfig.mem.mp_data_size) != 0U) { + osRtxInfo.mem.mp_data = osRtxConfig.mem.mp_data_addr; + } else { + osRtxInfo.mem.mp_data = osRtxInfo.mem.common; + } + if (osRtxMemoryInit(osRtxConfig.mem.mq_data_addr, osRtxConfig.mem.mq_data_size) != 0U) { + osRtxInfo.mem.mq_data = osRtxConfig.mem.mq_data_addr; + } else { + osRtxInfo.mem.mq_data = osRtxInfo.mem.common; + } + + // Initialize Memory Pools (Fixed Block Size) + if (osRtxConfig.mpi.stack != NULL) { + (void)osRtxMemoryPoolInit(osRtxConfig.mpi.stack, + osRtxConfig.mpi.stack->max_blocks, + osRtxConfig.mpi.stack->block_size, + osRtxConfig.mpi.stack->block_base); + osRtxInfo.mpi.stack = osRtxConfig.mpi.stack; + } + if (osRtxConfig.mpi.thread != NULL) { + (void)osRtxMemoryPoolInit(osRtxConfig.mpi.thread, + osRtxConfig.mpi.thread->max_blocks, + osRtxConfig.mpi.thread->block_size, + osRtxConfig.mpi.thread->block_base); + osRtxInfo.mpi.thread = osRtxConfig.mpi.thread; + } + if (osRtxConfig.mpi.timer != NULL) { + (void)osRtxMemoryPoolInit(osRtxConfig.mpi.timer, + osRtxConfig.mpi.timer->max_blocks, + osRtxConfig.mpi.timer->block_size, + osRtxConfig.mpi.timer->block_base); + osRtxInfo.mpi.timer = osRtxConfig.mpi.timer; + } + if (osRtxConfig.mpi.event_flags != NULL) { + (void)osRtxMemoryPoolInit(osRtxConfig.mpi.event_flags, + osRtxConfig.mpi.event_flags->max_blocks, + osRtxConfig.mpi.event_flags->block_size, + osRtxConfig.mpi.event_flags->block_base); + osRtxInfo.mpi.event_flags = osRtxConfig.mpi.event_flags; + } + if (osRtxConfig.mpi.mutex != NULL) { + (void)osRtxMemoryPoolInit(osRtxConfig.mpi.mutex, + osRtxConfig.mpi.mutex->max_blocks, + osRtxConfig.mpi.mutex->block_size, + osRtxConfig.mpi.mutex->block_base); + osRtxInfo.mpi.mutex = osRtxConfig.mpi.mutex; + } + if (osRtxConfig.mpi.semaphore != NULL) { + (void)osRtxMemoryPoolInit(osRtxConfig.mpi.semaphore, + osRtxConfig.mpi.semaphore->max_blocks, + osRtxConfig.mpi.semaphore->block_size, + osRtxConfig.mpi.semaphore->block_base); + osRtxInfo.mpi.semaphore = osRtxConfig.mpi.semaphore; + } + if (osRtxConfig.mpi.memory_pool != NULL) { + (void)osRtxMemoryPoolInit(osRtxConfig.mpi.memory_pool, + osRtxConfig.mpi.memory_pool->max_blocks, + osRtxConfig.mpi.memory_pool->block_size, + osRtxConfig.mpi.memory_pool->block_base); + osRtxInfo.mpi.memory_pool = osRtxConfig.mpi.memory_pool; + } + if (osRtxConfig.mpi.message_queue != NULL) { + (void)osRtxMemoryPoolInit(osRtxConfig.mpi.message_queue, + osRtxConfig.mpi.message_queue->max_blocks, + osRtxConfig.mpi.message_queue->block_size, + osRtxConfig.mpi.message_queue->block_base); + osRtxInfo.mpi.message_queue = osRtxConfig.mpi.message_queue; + } + + osRtxInfo.kernel.state = osRtxKernelReady; + + EvrRtxKernelInitialized(); + + return osOK; +} + +/// Get RTOS Kernel Information. +/// \note API identical to osKernelGetInfo +static osStatus_t svcRtxKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) { + uint32_t size; + + if (version != NULL) { + version->api = osRtxVersionAPI; + version->kernel = osRtxVersionKernel; + } + + if ((id_buf != NULL) && (id_size != 0U)) { + if (id_size > sizeof(osRtxKernelId)) { + size = sizeof(osRtxKernelId); + } else { + size = id_size; + } + memcpy(id_buf, osRtxKernelId, size); + } + + EvrRtxKernelInfoRetrieved(version, id_buf, id_size); + + return osOK; +} + +/// Get the current RTOS Kernel state. +/// \note API identical to osKernelGetState +static osKernelState_t svcRtxKernelGetState (void) { + osKernelState_t state = osRtxKernelState(); + EvrRtxKernelGetState(state); + return state; +} + +/// Start the RTOS Kernel scheduler. +/// \note API identical to osKernelStart +static osStatus_t svcRtxKernelStart (void) { + os_thread_t *thread; + + if (osRtxInfo.kernel.state != osRtxKernelReady) { + EvrRtxKernelError(osRtxErrorKernelNotReady); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osError; + } + + // Thread startup (Idle and Timer Thread) + if (!osRtxThreadStartup()) { + EvrRtxKernelError((int32_t)osError); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osError; + } + + // Setup SVC and PendSV System Service Calls + SVC_Setup(); + + // Setup RTOS Tick + if (OS_Tick_Setup(osRtxConfig.tick_freq, OS_TICK_HANDLER) != 0) { + EvrRtxKernelError((int32_t)osError); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osError; + } + osRtxInfo.tick_irqn = OS_Tick_GetIRQn(); + + // Enable RTOS Tick + OS_Tick_Enable(); + + // Switch to Ready Thread with highest Priority + thread = osRtxThreadListGet(&osRtxInfo.thread.ready); + osRtxThreadSwitch(thread); + + if ((osRtxConfig.flags & osRtxConfigPrivilegedMode) != 0U) { + // Privileged Thread mode & PSP + __set_CONTROL(0x02U); + } else { + // Unprivileged Thread mode & PSP + __set_CONTROL(0x03U); + } + + osRtxInfo.kernel.state = osRtxKernelRunning; + + EvrRtxKernelStarted(); + + return osOK; +} + +/// Lock the RTOS Kernel scheduler. +/// \note API identical to osKernelLock +static int32_t svcRtxKernelLock (void) { + int32_t lock; + + switch (osRtxInfo.kernel.state) { + case osRtxKernelRunning: + osRtxInfo.kernel.state = osRtxKernelLocked; + EvrRtxKernelLocked(0); + lock = 0; + break; + case osRtxKernelLocked: + EvrRtxKernelLocked(1); + lock = 1; + break; + default: + EvrRtxKernelError((int32_t)osError); + lock = (int32_t)osError; + break; + } + return lock; +} + +/// Unlock the RTOS Kernel scheduler. +/// \note API identical to osKernelUnlock +static int32_t svcRtxKernelUnlock (void) { + int32_t lock; + + switch (osRtxInfo.kernel.state) { + case osRtxKernelRunning: + EvrRtxKernelUnlocked(0); + lock = 0; + break; + case osRtxKernelLocked: + osRtxInfo.kernel.state = osRtxKernelRunning; + EvrRtxKernelUnlocked(1); + lock = 1; + break; + default: + EvrRtxKernelError((int32_t)osError); + lock = (int32_t)osError; + break; + } + return lock; +} + +/// Restore the RTOS Kernel scheduler lock state. +/// \note API identical to osKernelRestoreLock +static int32_t svcRtxKernelRestoreLock (int32_t lock) { + int32_t lock_new; + + switch (osRtxInfo.kernel.state) { + case osRtxKernelRunning: + case osRtxKernelLocked: + switch (lock) { + case 0: + osRtxInfo.kernel.state = osRtxKernelRunning; + EvrRtxKernelLockRestored(0); + lock_new = 0; + break; + case 1: + osRtxInfo.kernel.state = osRtxKernelLocked; + EvrRtxKernelLockRestored(1); + lock_new = 1; + break; + default: + EvrRtxKernelError((int32_t)osError); + lock_new = (int32_t)osError; + break; + } + break; + default: + EvrRtxKernelError((int32_t)osError); + lock_new = (int32_t)osError; + break; + } + return lock_new; +} + +/// Suspend the RTOS Kernel scheduler. +/// \note API identical to osKernelSuspend +static uint32_t svcRtxKernelSuspend (void) { + const os_thread_t *thread; + const os_timer_t *timer; + uint32_t delay; + + if (osRtxInfo.kernel.state != osRtxKernelRunning) { + EvrRtxKernelError(osRtxErrorKernelNotRunning); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return 0U; + } + + KernelBlock(); + + delay = osWaitForever; + + // Check Thread Delay list + thread = osRtxInfo.thread.delay_list; + if (thread != NULL) { + delay = thread->delay; + } + + // Check Active Timer list + timer = osRtxInfo.timer.list; + if (timer != NULL) { + if (timer->tick < delay) { + delay = timer->tick; + } + } + + osRtxInfo.kernel.state = osRtxKernelSuspended; + + EvrRtxKernelSuspended(delay); + + return delay; +} + +/// Resume the RTOS Kernel scheduler. +/// \note API identical to osKernelResume +static void svcRtxKernelResume (uint32_t sleep_ticks) { + os_thread_t *thread; + os_timer_t *timer; + uint32_t delay; + uint32_t ticks; + + if (osRtxInfo.kernel.state != osRtxKernelSuspended) { + EvrRtxKernelResumed(); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return; + } + + osRtxInfo.kernel.tick += sleep_ticks; + + // Process Thread Delay list + thread = osRtxInfo.thread.delay_list; + if (thread != NULL) { + delay = sleep_ticks; + do { + if (delay >= thread->delay) { + delay -= thread->delay; + thread->delay = 1U; + osRtxThreadDelayTick(); + thread = osRtxInfo.thread.delay_list; + } else { + thread->delay -= delay; + delay = 0U; + } + } while ((thread != NULL) && (delay != 0U)); + } + + // Process Active Timer list + timer = osRtxInfo.timer.list; + if (timer != NULL) { + ticks = sleep_ticks; + do { + if (ticks >= timer->tick) { + ticks -= timer->tick; + timer->tick = 1U; + osRtxInfo.timer.tick(); + timer = osRtxInfo.timer.list; + } else { + timer->tick -= ticks; + ticks = 0U; + } + } while ((timer != NULL) && (ticks != 0U)); + } + + osRtxInfo.kernel.state = osRtxKernelRunning; + + osRtxThreadDispatch(NULL); + + KernelUnblock(); + + EvrRtxKernelResumed(); +} + +/// Get the RTOS kernel tick count. +/// \note API identical to osKernelGetTickCount +static uint32_t svcRtxKernelGetTickCount (void) { + EvrRtxKernelGetTickCount(osRtxInfo.kernel.tick); + return osRtxInfo.kernel.tick; +} + +/// Get the RTOS kernel tick frequency. +/// \note API identical to osKernelGetTickFreq +static uint32_t svcRtxKernelGetTickFreq (void) { + EvrRtxKernelGetTickFreq(osRtxConfig.tick_freq); + return osRtxConfig.tick_freq; +} + +/// Get the RTOS kernel system timer count. +/// \note API identical to osKernelGetSysTimerCount +static uint32_t svcRtxKernelGetSysTimerCount (void) { + uint32_t tick; + uint32_t count; + + tick = (uint32_t)osRtxInfo.kernel.tick; + count = OS_Tick_GetCount(); + if (OS_Tick_GetOverflow() != 0U) { + count = OS_Tick_GetCount(); + tick++; + } + count += tick * OS_Tick_GetInterval(); + EvrRtxKernelGetSysTimerCount(count); + return count; +} + +/// Get the RTOS kernel system timer frequency. +/// \note API identical to osKernelGetSysTimerFreq +static uint32_t svcRtxKernelGetSysTimerFreq (void) { + uint32_t freq = OS_Tick_GetClock(); + EvrRtxKernelGetSysTimerFreq(freq); + return freq; +} + +// Service Calls definitions +//lint ++flb "Library Begin" [MISRA Note 11] +SVC0_0 (KernelInitialize, osStatus_t) +SVC0_3 (KernelGetInfo, osStatus_t, osVersion_t *, char *, uint32_t) +SVC0_0 (KernelStart, osStatus_t) +SVC0_0 (KernelLock, int32_t) +SVC0_0 (KernelUnlock, int32_t) +SVC0_1 (KernelRestoreLock, int32_t, int32_t) +SVC0_0 (KernelSuspend, uint32_t) +SVC0_1N(KernelResume, void, uint32_t) +SVC0_0 (KernelGetState, osKernelState_t) +SVC0_0 (KernelGetTickCount, uint32_t) +SVC0_0 (KernelGetTickFreq, uint32_t) +SVC0_0 (KernelGetSysTimerCount, uint32_t) +SVC0_0 (KernelGetSysTimerFreq, uint32_t) +//lint --flb "Library End" + + +// ==== Library functions ==== + +/// RTOS Kernel Pre-Initialization Hook +//lint -esym(759,osRtxKernelPreInit) "Prototype in header" +//lint -esym(765,osRtxKernelPreInit) "Global scope (can be overridden)" +//lint -esym(522,osRtxKernelPreInit) "Can be overridden (do not lack side-effects)" +__WEAK void osRtxKernelPreInit (void) { +} + + +// ==== Public API ==== + +/// Initialize the RTOS Kernel. +osStatus_t osKernelInitialize (void) { + osStatus_t status; + + osRtxKernelPreInit(); + EvrRtxKernelInitialize(); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxKernelError((int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcKernelInitialize(); + } + return status; +} + +/// Get RTOS Kernel Information. +osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) { + osStatus_t status; + + EvrRtxKernelGetInfo(version, id_buf, id_size); + if (IsIrqMode() || IsIrqMasked() || IsPrivileged()) { + status = svcRtxKernelGetInfo(version, id_buf, id_size); + } else { + status = __svcKernelGetInfo(version, id_buf, id_size); + } + return status; +} + +/// Get the current RTOS Kernel state. +osKernelState_t osKernelGetState (void) { + osKernelState_t state; + + if (IsIrqMode() || IsIrqMasked() || IsPrivileged()) { + state = svcRtxKernelGetState(); + } else { + state = __svcKernelGetState(); + } + return state; +} + +/// Start the RTOS Kernel scheduler. +osStatus_t osKernelStart (void) { + osStatus_t status; + + EvrRtxKernelStart(); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxKernelError((int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcKernelStart(); + } + return status; +} + +/// Lock the RTOS Kernel scheduler. +int32_t osKernelLock (void) { + int32_t lock; + + EvrRtxKernelLock(); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxKernelError((int32_t)osErrorISR); + lock = (int32_t)osErrorISR; + } else { + lock = __svcKernelLock(); + } + return lock; +} + +/// Unlock the RTOS Kernel scheduler. +int32_t osKernelUnlock (void) { + int32_t lock; + + EvrRtxKernelUnlock(); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxKernelError((int32_t)osErrorISR); + lock = (int32_t)osErrorISR; + } else { + lock = __svcKernelUnlock(); + } + return lock; +} + +/// Restore the RTOS Kernel scheduler lock state. +int32_t osKernelRestoreLock (int32_t lock) { + int32_t lock_new; + + EvrRtxKernelRestoreLock(lock); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxKernelError((int32_t)osErrorISR); + lock_new = (int32_t)osErrorISR; + } else { + lock_new = __svcKernelRestoreLock(lock); + } + return lock_new; +} + +/// Suspend the RTOS Kernel scheduler. +uint32_t osKernelSuspend (void) { + uint32_t ticks; + + EvrRtxKernelSuspend(); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxKernelError((int32_t)osErrorISR); + ticks = 0U; + } else { + ticks = __svcKernelSuspend(); + } + return ticks; +} + +/// Resume the RTOS Kernel scheduler. +void osKernelResume (uint32_t sleep_ticks) { + + EvrRtxKernelResume(sleep_ticks); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxKernelError((int32_t)osErrorISR); + } else { + __svcKernelResume(sleep_ticks); + } +} + +/// Get the RTOS kernel tick count. +uint32_t osKernelGetTickCount (void) { + uint32_t count; + + if (IsIrqMode() || IsIrqMasked()) { + count = svcRtxKernelGetTickCount(); + } else { + count = __svcKernelGetTickCount(); + } + return count; +} + +/// Get the RTOS kernel tick frequency. +uint32_t osKernelGetTickFreq (void) { + uint32_t freq; + + if (IsIrqMode() || IsIrqMasked()) { + freq = svcRtxKernelGetTickFreq(); + } else { + freq = __svcKernelGetTickFreq(); + } + return freq; +} + +/// Get the RTOS kernel system timer count. +uint32_t osKernelGetSysTimerCount (void) { + uint32_t count; + + if (IsIrqMode() || IsIrqMasked()) { + count = svcRtxKernelGetSysTimerCount(); + } else { + count = __svcKernelGetSysTimerCount(); + } + return count; +} + +/// Get the RTOS kernel system timer frequency. +uint32_t osKernelGetSysTimerFreq (void) { + uint32_t freq; + + if (IsIrqMode() || IsIrqMasked()) { + freq = svcRtxKernelGetSysTimerFreq(); + } else { + freq = __svcKernelGetSysTimerFreq(); + } + return freq; +} diff --git a/source/rtos2/RTX/Source/rtx_lib.c b/source/rtos2/RTX/Source/rtx_lib.c new file mode 100644 index 000000000..4f1a45665 --- /dev/null +++ b/source/rtos2/RTX/Source/rtx_lib.c @@ -0,0 +1,773 @@ +/* + * Copyright (c) 2013-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: RTX Library Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "RTX_Config.h" +#include "rtx_os.h" + +#ifdef RTE_Compiler_EventRecorder +#include "EventRecorder.h" +#include "EventRecorderConf.h" +#endif +#include "rtx_evr.h" + + +// System Configuration +// ==================== + +// Dynamic Memory +#if (OS_DYNAMIC_MEM_SIZE != 0) +#if ((OS_DYNAMIC_MEM_SIZE % 8) != 0) +#error "Invalid Dynamic Memory size!" +#endif +static uint64_t os_mem[OS_DYNAMIC_MEM_SIZE/8] \ +__attribute__((section(".bss.os"))); +#endif + +// Kernel Tick Frequency +#if (OS_TICK_FREQ < 1) +#error "Invalid Kernel Tick Frequency!" +#endif + +// ISR FIFO Queue +#if (OS_ISR_FIFO_QUEUE < 4) +#error "Invalid ISR FIFO Queue size!" +#endif +static void *os_isr_queue[OS_ISR_FIFO_QUEUE] \ +__attribute__((section(".bss.os"))); + + +// Thread Configuration +// ==================== + +#if (((OS_STACK_SIZE % 8) != 0) || (OS_STACK_SIZE < 72)) +#error "Invalid default Thread Stack size!" +#endif + +#if (((OS_IDLE_THREAD_STACK_SIZE % 8) != 0) || (OS_IDLE_THREAD_STACK_SIZE < 72)) +#error "Invalid Idle Thread Stack size!" +#endif + + +#if (OS_THREAD_OBJ_MEM != 0) + +#if (OS_THREAD_NUM == 0) +#error "Invalid number of user Threads!" +#endif + +#if ((OS_THREAD_USER_STACK_SIZE != 0) && ((OS_THREAD_USER_STACK_SIZE % 8) != 0)) +#error "Invalid total Stack size!" +#endif + +// Thread Control Blocks +static osRtxThread_t os_thread_cb[OS_THREAD_NUM] \ +__attribute__((section(".bss.os.thread.cb"))); + +// Thread Default Stack +#if (OS_THREAD_DEF_STACK_NUM != 0) +static uint64_t os_thread_def_stack[OS_THREAD_DEF_STACK_NUM*(OS_STACK_SIZE/8)] \ +__attribute__((section(".bss.os.thread.stack"))); +#endif + +// Memory Pool for Thread Control Blocks +static osRtxMpInfo_t os_mpi_thread \ +__attribute__((section(".data.os.thread.mpi"))) = +{ (uint32_t)OS_THREAD_NUM, 0U, (uint32_t)osRtxThreadCbSize, &os_thread_cb[0], NULL, NULL }; + +// Memory Pool for Thread Default Stack +#if (OS_THREAD_DEF_STACK_NUM != 0) +static osRtxMpInfo_t os_mpi_def_stack \ +__attribute__((section(".data.os.thread.mpi"))) = +{ (uint32_t)OS_THREAD_DEF_STACK_NUM, 0U, (uint32_t)OS_STACK_SIZE, &os_thread_def_stack[0], NULL, NULL }; +#endif + +// Memory Pool for Thread Stack +#if (OS_THREAD_USER_STACK_SIZE != 0) +static uint64_t os_thread_stack[2 + OS_THREAD_NUM + (OS_THREAD_USER_STACK_SIZE/8)] \ +__attribute__((section(".bss.os.thread.stack"))); +#endif + +#endif // (OS_THREAD_OBJ_MEM != 0) + + +// Stack overrun checking +#if (OS_STACK_CHECK == 0) +// Override library function +extern void osRtxThreadStackCheck (void); + void osRtxThreadStackCheck (void) {} +#endif + + +// Idle Thread Control Block +static osRtxThread_t os_idle_thread_cb \ +__attribute__((section(".bss.os.thread.cb"))); + +// Idle Thread Stack +static uint64_t os_idle_thread_stack[OS_IDLE_THREAD_STACK_SIZE/8] \ +__attribute__((section(".bss.os.thread.stack"))); + +// Idle Thread Attributes +static const osThreadAttr_t os_idle_thread_attr = { +#if defined(OS_IDLE_THREAD_NAME) + OS_IDLE_THREAD_NAME, +#else + NULL, +#endif + osThreadDetached, + &os_idle_thread_cb, + (uint32_t)sizeof(os_idle_thread_cb), + &os_idle_thread_stack[0], + (uint32_t)sizeof(os_idle_thread_stack), + osPriorityIdle, +#if defined(OS_IDLE_THREAD_TZ_MOD_ID) + (uint32_t)OS_IDLE_THREAD_TZ_MOD_ID, +#else + 0U, +#endif + 0U +}; + + +// Timer Configuration +// =================== + +#if (OS_TIMER_OBJ_MEM != 0) + +#if (OS_TIMER_NUM == 0) +#error "Invalid number of Timer objects!" +#endif + +// Timer Control Blocks +static osRtxTimer_t os_timer_cb[OS_TIMER_NUM] \ +__attribute__((section(".bss.os.timer.cb"))); + +// Memory Pool for Timer Control Blocks +static osRtxMpInfo_t os_mpi_timer \ +__attribute__((section(".data.os.timer.mpi"))) = +{ (uint32_t)OS_TIMER_NUM, 0U, (uint32_t)osRtxTimerCbSize, &os_timer_cb[0], NULL, NULL }; + +#endif // (OS_TIMER_OBJ_MEM != 0) + + +#if ((OS_TIMER_THREAD_STACK_SIZE != 0) && (OS_TIMER_CB_QUEUE != 0)) + +#if (((OS_TIMER_THREAD_STACK_SIZE % 8) != 0) || (OS_TIMER_THREAD_STACK_SIZE < 96)) +#error "Invalid Timer Thread Stack size!" +#endif + +// Timer Thread Control Block +static osRtxThread_t os_timer_thread_cb \ +__attribute__((section(".bss.os.thread.cb"))); + +// Timer Thread Stack +static uint64_t os_timer_thread_stack[OS_TIMER_THREAD_STACK_SIZE/8] \ +__attribute__((section(".bss.os.thread.stack"))); + +// Timer Thread Attributes +static const osThreadAttr_t os_timer_thread_attr = { +#if defined(OS_TIMER_THREAD_NAME) + OS_TIMER_THREAD_NAME, +#else + NULL, +#endif + osThreadDetached, + &os_timer_thread_cb, + (uint32_t)sizeof(os_timer_thread_cb), + &os_timer_thread_stack[0], + (uint32_t)sizeof(os_timer_thread_stack), + //lint -e{9030} -e{9034} "cast from signed to enum" + (osPriority_t)OS_TIMER_THREAD_PRIO, +#if defined(OS_TIMER_THREAD_TZ_MOD_ID) + (uint32_t)OS_TIMER_THREAD_TZ_MOD_ID, +#else + 0U, +#endif + 0U +}; + +// Timer Message Queue Control Block +static osRtxMessageQueue_t os_timer_mq_cb \ +__attribute__((section(".bss.os.msgqueue.cb"))); + +// Timer Message Queue Data +static uint32_t os_timer_mq_data[osRtxMessageQueueMemSize(OS_TIMER_CB_QUEUE,8)/4] \ +__attribute__((section(".bss.os.msgqueue.mem"))); + +// Timer Message Queue Attributes +static const osMessageQueueAttr_t os_timer_mq_attr = { + NULL, + 0U, + &os_timer_mq_cb, + (uint32_t)sizeof(os_timer_mq_cb), + &os_timer_mq_data[0], + (uint32_t)sizeof(os_timer_mq_data) +}; + +#else + +extern void osRtxTimerThread (void *argument); + void osRtxTimerThread (void *argument) { (void)argument; } + +#endif // ((OS_TIMER_THREAD_STACK_SIZE != 0) && (OS_TIMER_CB_QUEUE != 0)) + + +// Event Flags Configuration +// ========================= + +#if (OS_EVFLAGS_OBJ_MEM != 0) + +#if (OS_EVFLAGS_NUM == 0) +#error "Invalid number of Event Flags objects!" +#endif + +// Event Flags Control Blocks +static osRtxEventFlags_t os_ef_cb[OS_EVFLAGS_NUM] \ +__attribute__((section(".bss.os.evflags.cb"))); + +// Memory Pool for Event Flags Control Blocks +static osRtxMpInfo_t os_mpi_ef \ +__attribute__((section(".data.os.evflags.mpi"))) = +{ (uint32_t)OS_EVFLAGS_NUM, 0U, (uint32_t)osRtxEventFlagsCbSize, &os_ef_cb[0], NULL, NULL }; + +#endif // (OS_EVFLAGS_OBJ_MEM != 0) + + +// Mutex Configuration +// =================== + +#if (OS_MUTEX_OBJ_MEM != 0) + +#if (OS_MUTEX_NUM == 0) +#error "Invalid number of Mutex objects!" +#endif + +// Mutex Control Blocks +static osRtxMutex_t os_mutex_cb[OS_MUTEX_NUM] \ +__attribute__((section(".bss.os.mutex.cb"))); + +// Memory Pool for Mutex Control Blocks +static osRtxMpInfo_t os_mpi_mutex \ +__attribute__((section(".data.os.mutex.mpi"))) = +{ (uint32_t)OS_MUTEX_NUM, 0U, (uint32_t)osRtxMutexCbSize, &os_mutex_cb[0], NULL, NULL }; + +#endif // (OS_MUTEX_OBJ_MEM != 0) + + +// Semaphore Configuration +// ======================= + +#if (OS_SEMAPHORE_OBJ_MEM != 0) + +#if (OS_SEMAPHORE_NUM == 0) +#error "Invalid number of Semaphore objects!" +#endif + +// Semaphore Control Blocks +static osRtxSemaphore_t os_semaphore_cb[OS_SEMAPHORE_NUM] \ +__attribute__((section(".bss.os.semaphore.cb"))); + +// Memory Pool for Semaphore Control Blocks +static osRtxMpInfo_t os_mpi_semaphore \ +__attribute__((section(".data.os.semaphore.mpi"))) = +{ (uint32_t)OS_SEMAPHORE_NUM, 0U, (uint32_t)osRtxSemaphoreCbSize, &os_semaphore_cb[0], NULL, NULL }; + +#endif // (OS_SEMAPHORE_OBJ_MEM != 0) + + +// Memory Pool Configuration +// ========================= + +#if (OS_MEMPOOL_OBJ_MEM != 0) + +#if (OS_MEMPOOL_NUM == 0) +#error "Invalid number of Memory Pool objects!" +#endif + +// Memory Pool Control Blocks +static osRtxMemoryPool_t os_mp_cb[OS_MEMPOOL_NUM] \ +__attribute__((section(".bss.os.mempool.cb"))); + +// Memory Pool for Memory Pool Control Blocks +static osRtxMpInfo_t os_mpi_mp \ +__attribute__((section(".data.os.mempool.mpi"))) = +{ (uint32_t)OS_MEMPOOL_NUM, 0U, (uint32_t)osRtxMemoryPoolCbSize, &os_mp_cb[0], NULL, NULL }; + +// Memory Pool for Memory Pool Data Storage +#if (OS_MEMPOOL_DATA_SIZE != 0) +#if ((OS_MEMPOOL_DATA_SIZE % 8) != 0) +#error "Invalid Data Memory size for Memory Pools!" +#endif +static uint64_t os_mp_data[2 + OS_MEMPOOL_NUM + (OS_MEMPOOL_DATA_SIZE/8)] \ +__attribute__((section(".bss.os.mempool.mem"))); +#endif + +#endif // (OS_MEMPOOL_OBJ_MEM != 0) + + +// Message Queue Configuration +// =========================== + +#if (OS_MSGQUEUE_OBJ_MEM != 0) + +#if (OS_MSGQUEUE_NUM == 0) +#error "Invalid number of Message Queue objects!" +#endif + +// Message Queue Control Blocks +static osRtxMessageQueue_t os_mq_cb[OS_MSGQUEUE_NUM] \ +__attribute__((section(".bss.os.msgqueue.cb"))); + +// Memory Pool for Message Queue Control Blocks +static osRtxMpInfo_t os_mpi_mq \ +__attribute__((section(".data.os.msgqueue.mpi"))) = +{ (uint32_t)OS_MSGQUEUE_NUM, 0U, (uint32_t)osRtxMessageQueueCbSize, &os_mq_cb[0], NULL, NULL }; + +// Memory Pool for Message Queue Data Storage +#if (OS_MSGQUEUE_DATA_SIZE != 0) +#if ((OS_MSGQUEUE_DATA_SIZE % 8) != 0) +#error "Invalid Data Memory size for Message Queues!" +#endif +static uint64_t os_mq_data[2 + OS_MSGQUEUE_NUM + (OS_MSGQUEUE_DATA_SIZE/8)] \ +__attribute__((section(".bss.os.msgqueue.mem"))); +#endif + +#endif // (OS_MSGQUEUE_OBJ_MEM != 0) + + +// Event Recorder Configuration +// ============================ + +#if (defined(OS_EVR_INIT) && (OS_EVR_INIT != 0)) + +// Initial Thread configuration covered also Thread Flags and Generic Wait +#if defined(OS_EVR_THREAD_FILTER) +#if !defined(OS_EVR_THFLAGS_FILTER) +#define OS_EVR_THFLAGS_FILTER OS_EVR_THREAD_FILTER +#endif +#if !defined(OS_EVR_WAIT_FILTER) +#define OS_EVR_WAIT_FILTER OS_EVR_THREAD_FILTER +#endif +#endif + +// Migrate initial filter configuration +#if defined(OS_EVR_MEMORY_FILTER) +#define OS_EVR_MEMORY_LEVEL (((OS_EVR_MEMORY_FILTER & 0x80U) != 0U) ? (OS_EVR_MEMORY_FILTER & 0x0FU) : 0U) +#endif +#if defined(OS_EVR_KERNEL_FILTER) +#define OS_EVR_KERNEL_LEVEL (((OS_EVR_KERNEL_FILTER & 0x80U) != 0U) ? (OS_EVR_KERNEL_FILTER & 0x0FU) : 0U) +#endif +#if defined(OS_EVR_THREAD_FILTER) +#define OS_EVR_THREAD_LEVEL (((OS_EVR_THREAD_FILTER & 0x80U) != 0U) ? (OS_EVR_THREAD_FILTER & 0x0FU) : 0U) +#endif +#if defined(OS_EVR_WAIT_FILTER) +#define OS_EVR_WAIT_LEVEL (((OS_EVR_WAIT_FILTER & 0x80U) != 0U) ? (OS_EVR_WAIT_FILTER & 0x0FU) : 0U) +#endif +#if defined(OS_EVR_THFLAGS_FILTER) +#define OS_EVR_THFLAGS_LEVEL (((OS_EVR_THFLAGS_FILTER & 0x80U) != 0U) ? (OS_EVR_THFLAGS_FILTER & 0x0FU) : 0U) +#endif +#if defined(OS_EVR_EVFLAGS_FILTER) +#define OS_EVR_EVFLAGS_LEVEL (((OS_EVR_EVFLAGS_FILTER & 0x80U) != 0U) ? (OS_EVR_EVFLAGS_FILTER & 0x0FU) : 0U) +#endif +#if defined(OS_EVR_TIMER_FILTER) +#define OS_EVR_TIMER_LEVEL (((OS_EVR_TIMER_FILTER & 0x80U) != 0U) ? (OS_EVR_TIMER_FILTER & 0x0FU) : 0U) +#endif +#if defined(OS_EVR_MUTEX_FILTER) +#define OS_EVR_MUTEX_LEVEL (((OS_EVR_MUTEX_FILTER & 0x80U) != 0U) ? (OS_EVR_MUTEX_FILTER & 0x0FU) : 0U) +#endif +#if defined(OS_EVR_SEMAPHORE_FILTER) +#define OS_EVR_SEMAPHORE_LEVEL (((OS_EVR_SEMAPHORE_FILTER & 0x80U) != 0U) ? (OS_EVR_SEMAPHORE_FILTER & 0x0FU) : 0U) +#endif +#if defined(OS_EVR_MEMPOOL_FILTER) +#define OS_EVR_MEMPOOL_LEVEL (((OS_EVR_MEMPOOL_FILTER & 0x80U) != 0U) ? (OS_EVR_MEMPOOL_FILTER & 0x0FU) : 0U) +#endif +#if defined(OS_EVR_MSGQUEUE_FILTER) +#define OS_EVR_MSGQUEUE_LEVEL (((OS_EVR_MSGQUEUE_FILTER & 0x80U) != 0U) ? (OS_EVR_MSGQUEUE_FILTER & 0x0FU) : 0U) +#endif + +#if defined(RTE_Compiler_EventRecorder) + +// Event Recorder Initialize +__STATIC_INLINE void evr_initialize (void) { + + (void)EventRecorderInitialize(OS_EVR_LEVEL, (uint32_t)OS_EVR_START); + + (void)EventRecorderEnable(OS_EVR_MEMORY_LEVEL, EvtRtxMemoryNo, EvtRtxMemoryNo); + (void)EventRecorderEnable(OS_EVR_KERNEL_LEVEL, EvtRtxKernelNo, EvtRtxKernelNo); + (void)EventRecorderEnable(OS_EVR_THREAD_LEVEL, EvtRtxThreadNo, EvtRtxThreadNo); + (void)EventRecorderEnable(OS_EVR_WAIT_LEVEL, EvtRtxWaitNo, EvtRtxWaitNo); + (void)EventRecorderEnable(OS_EVR_THFLAGS_LEVEL, EvtRtxThreadFlagsNo, EvtRtxThreadFlagsNo); + (void)EventRecorderEnable(OS_EVR_EVFLAGS_LEVEL, EvtRtxEventFlagsNo, EvtRtxEventFlagsNo); + (void)EventRecorderEnable(OS_EVR_TIMER_LEVEL, EvtRtxTimerNo, EvtRtxTimerNo); + (void)EventRecorderEnable(OS_EVR_MUTEX_LEVEL, EvtRtxMutexNo, EvtRtxMutexNo); + (void)EventRecorderEnable(OS_EVR_SEMAPHORE_LEVEL, EvtRtxSemaphoreNo, EvtRtxSemaphoreNo); + (void)EventRecorderEnable(OS_EVR_MEMPOOL_LEVEL, EvtRtxMemoryPoolNo, EvtRtxMemoryPoolNo); + (void)EventRecorderEnable(OS_EVR_MSGQUEUE_LEVEL, EvtRtxMessageQueueNo, EvtRtxMessageQueueNo); +} + +#else +#warning "Event Recorder cannot be initialized (Event Recorder component is not selected)!" +#define evr_initialize() +#endif + +#endif // (OS_EVR_INIT != 0) + + +// OS Configuration +// ================ + + +const osRtxConfig_t osRtxConfig \ +__USED \ +__attribute__((section(".rodata"))) = +{ + //lint -e{835} "Zero argument to operator" + 0U // Flags +#if (OS_PRIVILEGE_MODE != 0) + | osRtxConfigPrivilegedMode +#endif +#if (OS_STACK_CHECK != 0) + | osRtxConfigStackCheck +#endif +#if (OS_STACK_WATERMARK != 0) + | osRtxConfigStackWatermark +#endif + , + (uint32_t)OS_TICK_FREQ, +#if (OS_ROBIN_ENABLE != 0) + (uint32_t)OS_ROBIN_TIMEOUT, +#else + 0U, +#endif + { &os_isr_queue[0], (uint16_t)(sizeof(os_isr_queue)/sizeof(void *)), 0U }, + { + // Memory Pools (Variable Block Size) +#if ((OS_THREAD_OBJ_MEM != 0) && (OS_THREAD_USER_STACK_SIZE != 0)) + &os_thread_stack[0], sizeof(os_thread_stack), +#else + NULL, 0U, +#endif +#if ((OS_MEMPOOL_OBJ_MEM != 0) && (OS_MEMPOOL_DATA_SIZE != 0)) + &os_mp_data[0], sizeof(os_mp_data), +#else + NULL, 0U, +#endif +#if ((OS_MSGQUEUE_OBJ_MEM != 0) && (OS_MSGQUEUE_DATA_SIZE != 0)) + &os_mq_data[0], sizeof(os_mq_data), +#else + NULL, 0U, +#endif +#if (OS_DYNAMIC_MEM_SIZE != 0) + &os_mem[0], (uint32_t)OS_DYNAMIC_MEM_SIZE, +#else + NULL, 0U +#endif + }, + { + // Memory Pools (Fixed Block Size) +#if (OS_THREAD_OBJ_MEM != 0) +#if (OS_THREAD_DEF_STACK_NUM != 0) + &os_mpi_def_stack, +#else + NULL, +#endif + &os_mpi_thread, +#else + NULL, + NULL, +#endif +#if (OS_TIMER_OBJ_MEM != 0) + &os_mpi_timer, +#else + NULL, +#endif +#if (OS_EVFLAGS_OBJ_MEM != 0) + &os_mpi_ef, +#else + NULL, +#endif +#if (OS_MUTEX_OBJ_MEM != 0) + &os_mpi_mutex, +#else + NULL, +#endif +#if (OS_SEMAPHORE_OBJ_MEM != 0) + &os_mpi_semaphore, +#else + NULL, +#endif +#if (OS_MEMPOOL_OBJ_MEM != 0) + &os_mpi_mp, +#else + NULL, +#endif +#if (OS_MSGQUEUE_OBJ_MEM != 0) + &os_mpi_mq, +#else + NULL, +#endif + }, + (uint32_t)OS_STACK_SIZE, + &os_idle_thread_attr, +#if ((OS_TIMER_THREAD_STACK_SIZE != 0) && (OS_TIMER_CB_QUEUE != 0)) + &os_timer_thread_attr, + &os_timer_mq_attr, + (uint32_t)OS_TIMER_CB_QUEUE +#else + NULL, + NULL, + 0U +#endif +}; + + +// Non weak reference to library irq module +//lint -esym(526,irqRtxLib) "Defined by Exception handlers" +//lint -esym(714,irqRtxLibRef) "Non weak reference" +//lint -esym(765,irqRtxLibRef) "Global scope" +extern uint8_t irqRtxLib; +extern const uint8_t *irqRtxLibRef; + const uint8_t *irqRtxLibRef = &irqRtxLib; + +// Default User SVC Table +//lint -esym(714,osRtxUserSVC) "Referenced by Exception handlers" +//lint -esym(765,osRtxUserSVC) "Global scope" +//lint -e{9067} "extern array declared without size" +extern void * const osRtxUserSVC[]; +__WEAK void * const osRtxUserSVC[1] = { (void *)0 }; + + +// OS Sections +// =========== + +#if defined(__CC_ARM) || \ + (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +static uint32_t __os_thread_cb_start__ __attribute__((weakref(".bss.os.thread.cb$$Base"))); //lint -esym(728,__os_thread_cb_start__) +static uint32_t __os_thread_cb_end__ __attribute__((weakref(".bss.os.thread.cb$$Limit"))); //lint -esym(728,__os_thread_cb_end__) +static uint32_t __os_timer_cb_start__ __attribute__((weakref(".bss.os.timer.cb$$Base"))); //lint -esym(728,__os_timer_cb_start__) +static uint32_t __os_timer_cb_end__ __attribute__((weakref(".bss.os.timer.cb$$Limit"))); //lint -esym(728,__os_timer_cb_end__) +static uint32_t __os_evflags_cb_start__ __attribute__((weakref(".bss.os.evflags.cb$$Base"))); //lint -esym(728,__os_evflags_cb_start__) +static uint32_t __os_evflags_cb_end__ __attribute__((weakref(".bss.os.evflags.cb$$Limit"))); //lint -esym(728,__os_evflags_cb_end__) +static uint32_t __os_mutex_cb_start__ __attribute__((weakref(".bss.os.mutex.cb$$Base"))); //lint -esym(728,__os_mutex_cb_start__) +static uint32_t __os_mutex_cb_end__ __attribute__((weakref(".bss.os.mutex.cb$$Limit"))); //lint -esym(728,__os_mutex_cb_end__) +static uint32_t __os_semaphore_cb_start__ __attribute__((weakref(".bss.os.semaphore.cb$$Base"))); //lint -esym(728,__os_semaphore_cb_start__) +static uint32_t __os_semaphore_cb_end__ __attribute__((weakref(".bss.os.semaphore.cb$$Limit"))); //lint -esym(728,__os_semaphore_cb_end__) +static uint32_t __os_mempool_cb_start__ __attribute__((weakref(".bss.os.mempool.cb$$Base"))); //lint -esym(728,__os_mempool_cb_start__) +static uint32_t __os_mempool_cb_end__ __attribute__((weakref(".bss.os.mempool.cb$$Limit"))); //lint -esym(728,__os_mempool_cb_end__) +static uint32_t __os_msgqueue_cb_start__ __attribute__((weakref(".bss.os.msgqueue.cb$$Base"))); //lint -esym(728,__os_msgqueue_cb_start__) +static uint32_t __os_msgqueue_cb_end__ __attribute__((weakref(".bss.os.msgqueue.cb$$Limit"))); //lint -esym(728,__os_msgqueue_cb_end__) +#else +extern uint32_t __os_thread_cb_start__ __attribute__((weak)); +extern uint32_t __os_thread_cb_end__ __attribute__((weak)); +extern uint32_t __os_timer_cb_start__ __attribute__((weak)); +extern uint32_t __os_timer_cb_end__ __attribute__((weak)); +extern uint32_t __os_evflags_cb_start__ __attribute__((weak)); +extern uint32_t __os_evflags_cb_end__ __attribute__((weak)); +extern uint32_t __os_mutex_cb_start__ __attribute__((weak)); +extern uint32_t __os_mutex_cb_end__ __attribute__((weak)); +extern uint32_t __os_semaphore_cb_start__ __attribute__((weak)); +extern uint32_t __os_semaphore_cb_end__ __attribute__((weak)); +extern uint32_t __os_mempool_cb_start__ __attribute__((weak)); +extern uint32_t __os_mempool_cb_end__ __attribute__((weak)); +extern uint32_t __os_msgqueue_cb_start__ __attribute__((weak)); +extern uint32_t __os_msgqueue_cb_end__ __attribute__((weak)); +#endif + +//lint -e{9067} "extern array declared without size" +extern const uint32_t * const os_cb_sections[]; + +//lint -esym(714,os_cb_sections) "Referenced by debugger" +//lint -esym(765,os_cb_sections) "Global scope" +const uint32_t * const os_cb_sections[] \ +__USED \ +__attribute__((section(".rodata"))) = +{ + &__os_thread_cb_start__, + &__os_thread_cb_end__, + &__os_timer_cb_start__, + &__os_timer_cb_end__, + &__os_evflags_cb_start__, + &__os_evflags_cb_end__, + &__os_mutex_cb_start__, + &__os_mutex_cb_end__, + &__os_semaphore_cb_start__, + &__os_semaphore_cb_end__, + &__os_mempool_cb_start__, + &__os_mempool_cb_end__, + &__os_msgqueue_cb_start__, + &__os_msgqueue_cb_end__ +}; + + +// OS Initialization +// ================= + +#if defined(__CC_ARM) || \ + (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + +#ifndef __MICROLIB +//lint -esym(714,_platform_post_stackheap_init) "Referenced by C library" +//lint -esym(765,_platform_post_stackheap_init) "Global scope" +extern void _platform_post_stackheap_init (void); +__WEAK void _platform_post_stackheap_init (void) { + (void)osKernelInitialize(); +} +#endif + +#elif defined(__GNUC__) + +extern void software_init_hook (void); +__WEAK void software_init_hook (void) { + (void)osKernelInitialize(); +} + +#endif + + +// OS Hooks +// ======== + +// RTOS Kernel Pre-Initialization Hook +#if (defined(OS_EVR_INIT) && (OS_EVR_INIT != 0)) +void osRtxKernelPreInit (void); +void osRtxKernelPreInit (void) { + if (osKernelGetState() == osKernelInactive) { + evr_initialize(); + } +} +#endif + + +// C/C++ Standard Library Multithreading Interface +// =============================================== + +#if ( !defined(RTX_NO_MULTITHREAD_CLIB) && \ + ( defined(__CC_ARM) || \ + (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))) && \ + !defined(__MICROLIB)) + +#define LIBSPACE_SIZE 96 + +//lint -esym(714,__user_perthread_libspace,_mutex_*) "Referenced by C library" +//lint -esym(765,__user_perthread_libspace,_mutex_*) "Global scope" +//lint -esym(9003, os_libspace*) "variables 'os_libspace*' defined at module scope" + +// Memory for libspace +static uint32_t os_libspace[OS_THREAD_LIBSPACE_NUM+1][LIBSPACE_SIZE/4] \ +__attribute__((section(".bss.os.libspace"))); + +// Thread IDs for libspace +static osThreadId_t os_libspace_id[OS_THREAD_LIBSPACE_NUM] \ +__attribute__((section(".bss.os.libspace"))); + +// Check if Kernel has been started +static uint32_t os_kernel_is_active (void) { + static uint8_t os_kernel_active = 0U; + + if (os_kernel_active == 0U) { + if (osKernelGetState() > osKernelReady) { + os_kernel_active = 1U; + } + } + return (uint32_t)os_kernel_active; +} + +// Provide libspace for current thread +void *__user_perthread_libspace (void); +void *__user_perthread_libspace (void) { + osThreadId_t id; + uint32_t n; + + if (os_kernel_is_active() != 0U) { + id = osThreadGetId(); + for (n = 0U; n < (uint32_t)OS_THREAD_LIBSPACE_NUM; n++) { + if (os_libspace_id[n] == NULL) { + os_libspace_id[n] = id; + } + if (os_libspace_id[n] == id) { + break; + } + } + if (n == (uint32_t)OS_THREAD_LIBSPACE_NUM) { + (void)osRtxErrorNotify(osRtxErrorClibSpace, id); + } + } else { + n = OS_THREAD_LIBSPACE_NUM; + } + + //lint -e{9087} "cast between pointers to different object types" + return (void *)&os_libspace[n][0]; +} + +// Mutex identifier +typedef void *mutex; + +//lint -save "Function prototypes defined in C library" +//lint -e970 "Use of 'int' outside of a typedef" +//lint -e818 "Pointer 'm' could be declared as pointing to const" + +// Initialize mutex +__USED +int _mutex_initialize(mutex *m); +int _mutex_initialize(mutex *m) { + int result; + + *m = osMutexNew(NULL); + if (*m != NULL) { + result = 1; + } else { + result = 0; + (void)osRtxErrorNotify(osRtxErrorClibMutex, m); + } + return result; +} + +// Acquire mutex +__USED +void _mutex_acquire(mutex *m); +void _mutex_acquire(mutex *m) { + if (os_kernel_is_active() != 0U) { + (void)osMutexAcquire(*m, osWaitForever); + } +} + +// Release mutex +__USED +void _mutex_release(mutex *m); +void _mutex_release(mutex *m) { + if (os_kernel_is_active() != 0U) { + (void)osMutexRelease(*m); + } +} + +// Free mutex +__USED +void _mutex_free(mutex *m); +void _mutex_free(mutex *m) { + (void)osMutexDelete(*m); +} + +//lint -restore + +#endif diff --git a/source/rtos2/RTX/Source/rtx_lib.h b/source/rtos2/RTX/Source/rtx_lib.h new file mode 100644 index 000000000..2d23625e4 --- /dev/null +++ b/source/rtos2/RTX/Source/rtx_lib.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: RTX Library definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_LIB_H_ +#define RTX_LIB_H_ + +#include +#include "rtx_core_c.h" // Cortex core definitions +#if ((defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0))) +#include "tz_context.h" // TrustZone Context API +#endif +#include "os_tick.h" // CMSIS OS Tick API +#include "cmsis_os2.h" // CMSIS RTOS API +#include "RTX_Config.h" // RTX Configuration +#include "rtx_os.h" // RTX OS definitions +#include "rtx_evr.h" // RTX Event Recorder definitions + + +// ==== Library defines ==== + +#define os_thread_t osRtxThread_t +#define os_timer_t osRtxTimer_t +#define os_timer_finfo_t osRtxTimerFinfo_t +#define os_event_flags_t osRtxEventFlags_t +#define os_mutex_t osRtxMutex_t +#define os_semaphore_t osRtxSemaphore_t +#define os_mp_info_t osRtxMpInfo_t +#define os_memory_pool_t osRtxMemoryPool_t +#define os_message_t osRtxMessage_t +#define os_message_queue_t osRtxMessageQueue_t +#define os_object_t osRtxObject_t + +// ==== Inline functions ==== + +// Thread ID +__STATIC_INLINE os_thread_t *osRtxThreadId (osThreadId_t thread_id) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2] + return ((os_thread_t *)thread_id); +} +// Timer ID +__STATIC_INLINE os_timer_t *osRtxTimerId (osTimerId_t timer_id) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2] + return ((os_timer_t *)timer_id); +} +// Event Flags ID +__STATIC_INLINE os_event_flags_t *osRtxEventFlagsId (osEventFlagsId_t ef_id) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2] + return ((os_event_flags_t *)ef_id); +} +// Mutex ID +__STATIC_INLINE os_mutex_t *osRtxMutexId (osMutexId_t mutex_id) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2] + return ((os_mutex_t *)mutex_id); +} +// Semaphore ID +__STATIC_INLINE os_semaphore_t *osRtxSemaphoreId (osSemaphoreId_t semaphore_id) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2] + return ((os_semaphore_t *)semaphore_id); +} +// Memory Pool ID +__STATIC_INLINE os_memory_pool_t *osRtxMemoryPoolId (osMemoryPoolId_t mp_id) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2] + return ((os_memory_pool_t *)mp_id); +} +// Message Queue ID +__STATIC_INLINE os_message_queue_t *osRtxMessageQueueId (osMessageQueueId_t mq_id) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 2] + return ((os_message_queue_t *)mq_id); +} + +// Generic Object +__STATIC_INLINE os_object_t *osRtxObject (void *object) { + //lint -e{9079} -e{9087} "cast from pointer to void to pointer to object type" [MISRA Note 3] + return ((os_object_t *)object); +} + +// Thread Object +__STATIC_INLINE os_thread_t *osRtxThreadObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_thread_t *)object); +} +// Timer Object +__STATIC_INLINE os_timer_t *osRtxTimerObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_timer_t *)object); +} +// Event Flags Object +__STATIC_INLINE os_event_flags_t *osRtxEventFlagsObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_event_flags_t *)object); +} +// Mutex Object +__STATIC_INLINE os_mutex_t *osRtxMutexObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_mutex_t *)object); +} +// Semaphore Object +__STATIC_INLINE os_semaphore_t *osRtxSemaphoreObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_semaphore_t *)object); +} +// Memory Pool Object +__STATIC_INLINE os_memory_pool_t *osRtxMemoryPoolObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_memory_pool_t *)object); +} +// Message Queue Object +__STATIC_INLINE os_message_queue_t *osRtxMessageQueueObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_message_queue_t *)object); +} +// Message Object +__STATIC_INLINE os_message_t *osRtxMessageObject (os_object_t *object) { + //lint -e{740} -e{826} -e{9087} "cast from pointer to generic object to specific object" [MISRA Note 4] + return ((os_message_t *)object); +} + +// Kernel State +__STATIC_INLINE osKernelState_t osRtxKernelState (void) { + //lint -e{9030} -e{9034} "cast to enum" + return ((osKernelState_t)(osRtxInfo.kernel.state)); +} + +// Thread State +__STATIC_INLINE osThreadState_t osRtxThreadState (const os_thread_t *thread) { + uint8_t state = thread->state & osRtxThreadStateMask; + //lint -e{9030} -e{9034} "cast to enum" + return ((osThreadState_t)state); +} + +// Thread Priority +__STATIC_INLINE osPriority_t osRtxThreadPriority (const os_thread_t *thread) { + //lint -e{9030} -e{9034} "cast to enum" + return ((osPriority_t)thread->priority); +} + +// Kernel Get State +__STATIC_INLINE uint8_t osRtxKernelGetState (void) { + return osRtxInfo.kernel.state; +} + +// Thread Get/Set Running +__STATIC_INLINE os_thread_t *osRtxThreadGetRunning (void) { + return osRtxInfo.thread.run.curr; +} +__STATIC_INLINE void osRtxThreadSetRunning (os_thread_t *thread) { + osRtxInfo.thread.run.curr = thread; +} + + +// ==== Library functions ==== + +// Kernel Library functions +extern void osRtxKernelPreInit (void); + +// Thread Library functions +extern void osRtxThreadListPut (os_object_t *object, os_thread_t *thread); +extern os_thread_t *osRtxThreadListGet (os_object_t *object); +extern void osRtxThreadListSort (os_thread_t *thread); +extern void osRtxThreadListRemove (os_thread_t *thread); +extern void osRtxThreadReadyPut (os_thread_t *thread); +extern void osRtxThreadDelayTick (void); +extern uint32_t *osRtxThreadRegPtr (const os_thread_t *thread); +extern void osRtxThreadSwitch (os_thread_t *thread); +extern void osRtxThreadDispatch (os_thread_t *thread); +extern void osRtxThreadWaitExit (os_thread_t *thread, uint32_t ret_val, bool_t dispatch); +extern bool_t osRtxThreadWaitEnter (uint8_t state, uint32_t timeout); +extern void osRtxThreadStackCheck (void); +extern bool_t osRtxThreadStartup (void); + +// Timer Library functions +extern void osRtxTimerThread (void *argument); + +// Mutex Library functions +extern void osRtxMutexOwnerRelease (os_mutex_t *mutex_list); +extern void osRtxMutexOwnerRestore (const os_mutex_t *mutex, const os_thread_t *thread_wakeup); + +// Memory Heap Library functions +extern uint32_t osRtxMemoryInit (void *mem, uint32_t size); +extern void *osRtxMemoryAlloc(void *mem, uint32_t size, uint32_t type); +extern uint32_t osRtxMemoryFree (void *mem, void *block); + +// Memory Pool Library functions +extern uint32_t osRtxMemoryPoolInit (os_mp_info_t *mp_info, uint32_t block_count, uint32_t block_size, void *block_mem); +extern void *osRtxMemoryPoolAlloc (os_mp_info_t *mp_info); +extern osStatus_t osRtxMemoryPoolFree (os_mp_info_t *mp_info, void *block); + +// System Library functions +extern void osRtxTick_Handler (void); +extern void osRtxPendSV_Handler (void); +extern void osRtxPostProcess (os_object_t *object); + + +#endif // RTX_LIB_H_ diff --git a/source/rtos2/RTX/Source/rtx_memory.c b/source/rtos2/RTX/Source/rtx_memory.c new file mode 100644 index 000000000..b22bfda95 --- /dev/null +++ b/source/rtos2/RTX/Source/rtx_memory.c @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Memory functions + * + * ----------------------------------------------------------------------------- + */ + +#include "rtx_lib.h" + + +// Memory Pool Header structure +typedef struct { + uint32_t size; // Memory Pool size + uint32_t used; // Used Memory +} mem_head_t; + +// Memory Block Header structure +typedef struct mem_block_s { + struct mem_block_s *next; // Next Memory Block in list + uint32_t info; // Block Info or max used Memory (in last block) +} mem_block_t; + +// Memory Block Info: Length = <31:2>:'00', Type = <1:0> +#define MB_INFO_LEN_MASK 0xFFFFFFFCU // Length mask +#define MB_INFO_TYPE_MASK 0x00000003U // Type mask + +// Memory Head Pointer +__STATIC_INLINE mem_head_t *MemHeadPtr (void *mem) { + //lint -e{9079} -e{9087} "conversion from pointer to void to pointer to other type" [MISRA Note 6] + return ((mem_head_t *)mem); +} + +// Memory Block Pointer +__STATIC_INLINE mem_block_t *MemBlockPtr (void *mem, uint32_t offset) { + uint32_t addr; + mem_block_t *ptr; + + //lint --e{923} --e{9078} "cast between pointer and unsigned int" [MISRA Note 8] + addr = (uint32_t)mem + offset; + ptr = (mem_block_t *)addr; + + return ptr; +} + + +// ==== Library functions ==== + +/// Initialize Memory Pool with variable block size. +/// \param[in] mem pointer to memory pool. +/// \param[in] size size of a memory pool in bytes. +/// \return 1 - success, 0 - failure. +__WEAK uint32_t osRtxMemoryInit (void *mem, uint32_t size) { + mem_head_t *head; + mem_block_t *ptr; + + // Check parameters + //lint -e{923} "cast from pointer to unsigned int" [MISRA Note 7] + if ((mem == NULL) || (((uint32_t)mem & 7U) != 0U) || ((size & 7U) != 0U) || + (size < (sizeof(mem_head_t) + (2U*sizeof(mem_block_t))))) { + EvrRtxMemoryInit(mem, size, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return 0U; + } + + // Initialize memory pool header + head = MemHeadPtr(mem); + head->size = size; + head->used = sizeof(mem_head_t) + sizeof(mem_block_t); + + // Initialize first and last block header + ptr = MemBlockPtr(mem, sizeof(mem_head_t)); + ptr->next = MemBlockPtr(mem, size - sizeof(mem_block_t)); + ptr->next->next = NULL; + ptr->next->info = sizeof(mem_head_t) + sizeof(mem_block_t); + ptr->info = 0U; + + EvrRtxMemoryInit(mem, size, 1U); + + return 1U; +} + +/// Allocate a memory block from a Memory Pool. +/// \param[in] mem pointer to memory pool. +/// \param[in] size size of a memory block in bytes. +/// \param[in] type memory block type: 0 - generic, 1 - control block +/// \return allocated memory block or NULL in case of no memory is available. +__WEAK void *osRtxMemoryAlloc (void *mem, uint32_t size, uint32_t type) { + mem_block_t *ptr; + mem_block_t *p, *p_new; + uint32_t block_size; + uint32_t hole_size; + + // Check parameters + if ((mem == NULL) || (size == 0U) || ((type & ~MB_INFO_TYPE_MASK) != 0U)) { + EvrRtxMemoryAlloc(mem, size, type, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + + // Add block header to size + block_size = size + sizeof(mem_block_t); + // Make sure that block is 8-byte aligned + block_size = (block_size + 7U) & ~((uint32_t)7U); + + // Search for hole big enough + p = MemBlockPtr(mem, sizeof(mem_head_t)); + for (;;) { + //lint -e{923} -e{9078} "cast from pointer to unsigned int" + hole_size = (uint32_t)p->next - (uint32_t)p; + hole_size -= p->info & MB_INFO_LEN_MASK; + if (hole_size >= block_size) { + // Hole found + break; + } + p = p->next; + if (p->next == NULL) { + // Failed (end of list) + EvrRtxMemoryAlloc(mem, size, type, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + } + + // Update used memory + (MemHeadPtr(mem))->used += block_size; + + // Update max used memory + p_new = MemBlockPtr(mem, (MemHeadPtr(mem))->size - sizeof(mem_block_t)); + if (p_new->info < (MemHeadPtr(mem))->used) { + p_new->info = (MemHeadPtr(mem))->used; + } + + // Allocate block + if (p->info == 0U) { + // No block allocated, set info of first element + p->info = block_size | type; + ptr = MemBlockPtr(p, sizeof(mem_block_t)); + } else { + // Insert new element into the list + p_new = MemBlockPtr(p, p->info & MB_INFO_LEN_MASK); + p_new->next = p->next; + p_new->info = block_size | type; + p->next = p_new; + ptr = MemBlockPtr(p_new, sizeof(mem_block_t)); + } + + EvrRtxMemoryAlloc(mem, size, type, ptr); + + return ptr; +} + +/// Return an allocated memory block back to a Memory Pool. +/// \param[in] mem pointer to memory pool. +/// \param[in] block memory block to be returned to the memory pool. +/// \return 1 - success, 0 - failure. +__WEAK uint32_t osRtxMemoryFree (void *mem, void *block) { + const mem_block_t *ptr; + mem_block_t *p, *p_prev; + + // Check parameters + if ((mem == NULL) || (block == NULL)) { + EvrRtxMemoryFree(mem, block, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return 0U; + } + + // Memory block header + ptr = MemBlockPtr(block, 0U); + ptr--; + + // Search for block header + p_prev = NULL; + p = MemBlockPtr(mem, sizeof(mem_head_t)); + while (p != ptr) { + p_prev = p; + p = p->next; + if (p == NULL) { + // Not found + EvrRtxMemoryFree(mem, block, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return 0U; + } + } + + // Update used memory + (MemHeadPtr(mem))->used -= p->info & MB_INFO_LEN_MASK; + + // Free block + if (p_prev == NULL) { + // Release first block, only set info to 0 + p->info = 0U; + } else { + // Discard block from chained list + p_prev->next = p->next; + } + + EvrRtxMemoryFree(mem, block, 1U); + + return 1U; +} diff --git a/source/rtos2/RTX/Source/rtx_mempool.c b/source/rtos2/RTX/Source/rtx_mempool.c new file mode 100644 index 000000000..f7a18723d --- /dev/null +++ b/source/rtos2/RTX/Source/rtx_mempool.c @@ -0,0 +1,705 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Memory Pool functions + * + * ----------------------------------------------------------------------------- + */ + +#include "rtx_lib.h" + + +// OS Runtime Object Memory Usage +#if ((defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0))) +osRtxObjectMemUsage_t osRtxMemoryPoolMemUsage \ +__attribute__((section(".data.os.mempool.obj"))) = +{ 0U, 0U, 0U }; +#endif + + +// ==== Library functions ==== + +/// Initialize Memory Pool. +/// \param[in] mp_info memory pool info. +/// \param[in] block_count maximum number of memory blocks in memory pool. +/// \param[in] block_size size of a memory block in bytes. +/// \param[in] block_mem pointer to memory for block storage. +/// \return 1 - success, 0 - failure. +uint32_t osRtxMemoryPoolInit (os_mp_info_t *mp_info, uint32_t block_count, uint32_t block_size, void *block_mem) { + //lint --e{9079} --e{9087} "conversion from pointer to void to pointer to other type" [MISRA Note 6] + void *mem; + void *block; + + // Check parameters + if ((mp_info == NULL) || (block_count == 0U) || (block_size == 0U) || (block_mem == NULL)) { + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return 0U; + } + + // Initialize information structure + mp_info->max_blocks = block_count; + mp_info->used_blocks = 0U; + mp_info->block_size = block_size; + mp_info->block_base = block_mem; + mp_info->block_free = block_mem; + mp_info->block_lim = &(((uint8_t *)block_mem)[block_count * block_size]); + + EvrRtxMemoryBlockInit(mp_info, block_count, block_size, block_mem); + + // Link all free blocks + mem = block_mem; + while (--block_count != 0U) { + block = &((uint8_t *)mem)[block_size]; + *((void **)mem) = block; + mem = block; + } + *((void **)mem) = NULL; + + return 1U; +} + +/// Allocate a memory block from a Memory Pool. +/// \param[in] mp_info memory pool info. +/// \return address of the allocated memory block or NULL in case of no memory is available. +void *osRtxMemoryPoolAlloc (os_mp_info_t *mp_info) { +#if (EXCLUSIVE_ACCESS == 0) + uint32_t primask = __get_PRIMASK(); +#endif + void *block; + + if (mp_info == NULL) { + EvrRtxMemoryBlockAlloc(NULL, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + +#if (EXCLUSIVE_ACCESS == 0) + __disable_irq(); + + block = mp_info->block_free; + if (block != NULL) { + //lint --e{9079} --e{9087} "conversion from pointer to void to pointer to other type" + mp_info->block_free = *((void **)block); + mp_info->used_blocks++; + } + + if (primask == 0U) { + __enable_irq(); + } +#else + block = atomic_link_get(&mp_info->block_free); + if (block != NULL) { + (void)atomic_inc32(&mp_info->used_blocks); + } +#endif + + EvrRtxMemoryBlockAlloc(mp_info, block); + + return block; +} + +/// Return an allocated memory block back to a Memory Pool. +/// \param[in] mp_info memory pool info. +/// \param[in] block address of the allocated memory block to be returned to the memory pool. +/// \return status code that indicates the execution status of the function. +osStatus_t osRtxMemoryPoolFree (os_mp_info_t *mp_info, void *block) { +#if (EXCLUSIVE_ACCESS == 0) + uint32_t primask = __get_PRIMASK(); +#endif + + //lint -e{946} "Relational operator applied to pointers" + if ((mp_info == NULL) || (block < mp_info->block_base) || (block >= mp_info->block_lim)) { + EvrRtxMemoryBlockFree(mp_info, block, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + +#if (EXCLUSIVE_ACCESS == 0) + __disable_irq(); + + //lint --e{9079} --e{9087} "conversion from pointer to void to pointer to other type" + *((void **)block) = mp_info->block_free; + mp_info->block_free = block; + mp_info->used_blocks--; + + if (primask == 0U) { + __enable_irq(); + } +#else + atomic_link_put(&mp_info->block_free, block); + (void)atomic_dec32(&mp_info->used_blocks); +#endif + + EvrRtxMemoryBlockFree(mp_info, block, (int32_t)osOK); + + return osOK; +} + + +// ==== Post ISR processing ==== + +/// Memory Pool post ISR processing. +/// \param[in] mp memory pool object. +static void osRtxMemoryPoolPostProcess (os_memory_pool_t *mp) { + void *block; + os_thread_t *thread; + + // Check if Thread is waiting to allocate memory + if (mp->thread_list != NULL) { + // Allocate memory + block = osRtxMemoryPoolAlloc(&mp->mp_info); + if (block != NULL) { + // Wakeup waiting Thread with highest Priority + thread = osRtxThreadListGet(osRtxObject(mp)); + //lint -e{923} "cast from pointer to unsigned int" + osRtxThreadWaitExit(thread, (uint32_t)block, FALSE); + EvrRtxMemoryPoolAllocated(mp, block); + } + } +} + + +// ==== Service Calls ==== + +/// Create and Initialize a Memory Pool object. +/// \note API identical to osMemoryPoolNew +static osMemoryPoolId_t svcRtxMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) { + os_memory_pool_t *mp; + void *mp_mem; + uint32_t mp_size; + uint32_t b_count; + uint32_t b_size; + uint32_t size; + uint8_t flags; + const char *name; + + // Check parameters + if ((block_count == 0U) || (block_size == 0U)) { + EvrRtxMemoryPoolError(NULL, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + b_count = block_count; + b_size = (block_size + 3U) & ~3UL; + if ((__CLZ(b_count) + __CLZ(b_size)) < 32U) { + EvrRtxMemoryPoolError(NULL, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + + size = b_count * b_size; + + // Process attributes + if (attr != NULL) { + name = attr->name; + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6] + mp = attr->cb_mem; + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6] + mp_mem = attr->mp_mem; + mp_size = attr->mp_size; + if (mp != NULL) { + //lint -e(923) -e(9078) "cast from pointer to unsigned int" [MISRA Note 7] + if ((((uint32_t)mp & 3U) != 0U) || (attr->cb_size < sizeof(os_memory_pool_t))) { + EvrRtxMemoryPoolError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + } else { + if (attr->cb_size != 0U) { + EvrRtxMemoryPoolError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + } + if (mp_mem != NULL) { + //lint -e(923) -e(9078) "cast from pointer to unsigned int" [MISRA Note 7] + if ((((uint32_t)mp_mem & 3U) != 0U) || (mp_size < size)) { + EvrRtxMemoryPoolError(NULL, osRtxErrorInvalidDataMemory); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + } else { + if (mp_size != 0U) { + EvrRtxMemoryPoolError(NULL, osRtxErrorInvalidDataMemory); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + } + } else { + name = NULL; + mp = NULL; + mp_mem = NULL; + } + + // Allocate object memory if not provided + if (mp == NULL) { + if (osRtxInfo.mpi.memory_pool != NULL) { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + mp = osRtxMemoryPoolAlloc(osRtxInfo.mpi.memory_pool); + } else { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + mp = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_memory_pool_t), 1U); + } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + if (mp != NULL) { + uint32_t used; + osRtxMemoryPoolMemUsage.cnt_alloc++; + used = osRtxMemoryPoolMemUsage.cnt_alloc - osRtxMemoryPoolMemUsage.cnt_free; + if (osRtxMemoryPoolMemUsage.max_used < used) { + osRtxMemoryPoolMemUsage.max_used = used; + } + } +#endif + flags = osRtxFlagSystemObject; + } else { + flags = 0U; + } + + // Allocate data memory if not provided + if ((mp != NULL) && (mp_mem == NULL)) { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + mp_mem = osRtxMemoryAlloc(osRtxInfo.mem.mp_data, size, 0U); + if (mp_mem == NULL) { + if ((flags & osRtxFlagSystemObject) != 0U) { + if (osRtxInfo.mpi.memory_pool != NULL) { + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.memory_pool, mp); + } else { + (void)osRtxMemoryFree(osRtxInfo.mem.common, mp); + } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxMemoryPoolMemUsage.cnt_free++; +#endif + } + mp = NULL; + } else { + memset(mp_mem, 0, size); + } + flags |= osRtxFlagSystemMemory; + } + + if (mp != NULL) { + // Initialize control block + mp->id = osRtxIdMemoryPool; + mp->flags = flags; + mp->name = name; + mp->thread_list = NULL; + (void)osRtxMemoryPoolInit(&mp->mp_info, b_count, b_size, mp_mem); + + // Register post ISR processing function + osRtxInfo.post_process.memory_pool = osRtxMemoryPoolPostProcess; + + EvrRtxMemoryPoolCreated(mp, mp->name); + } else { + EvrRtxMemoryPoolError(NULL, (int32_t)osErrorNoMemory); + } + + return mp; +} + +/// Get name of a Memory Pool object. +/// \note API identical to osMemoryPoolGetName +static const char *svcRtxMemoryPoolGetName (osMemoryPoolId_t mp_id) { + os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id); + + // Check parameters + if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) { + EvrRtxMemoryPoolGetName(mp, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + + EvrRtxMemoryPoolGetName(mp, mp->name); + + return mp->name; +} + +/// Allocate a memory block from a Memory Pool. +/// \note API identical to osMemoryPoolAlloc +static void *svcRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) { + os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id); + void *block; + + // Check parameters + if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) { + EvrRtxMemoryPoolError(mp, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + + // Allocate memory + block = osRtxMemoryPoolAlloc(&mp->mp_info); + if (block != NULL) { + EvrRtxMemoryPoolAllocated(mp, block); + } else { + // No memory available + if (timeout != 0U) { + EvrRtxMemoryPoolAllocPending(mp, timeout); + // Suspend current Thread + if (osRtxThreadWaitEnter(osRtxThreadWaitingMemoryPool, timeout)) { + osRtxThreadListPut(osRtxObject(mp), osRtxThreadGetRunning()); + } else { + EvrRtxMemoryPoolAllocTimeout(mp); + } + } else { + EvrRtxMemoryPoolAllocFailed(mp); + } + } + + return block; +} + +/// Return an allocated memory block back to a Memory Pool. +/// \note API identical to osMemoryPoolFree +static osStatus_t svcRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) { + os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id); + void *block0; + os_thread_t *thread; + osStatus_t status; + + // Check parameters + if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) { + EvrRtxMemoryPoolError(mp, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Free memory + status = osRtxMemoryPoolFree(&mp->mp_info, block); + if (status == osOK) { + EvrRtxMemoryPoolDeallocated(mp, block); + // Check if Thread is waiting to allocate memory + if (mp->thread_list != NULL) { + // Allocate memory + block0 = osRtxMemoryPoolAlloc(&mp->mp_info); + if (block0 != NULL) { + // Wakeup waiting Thread with highest Priority + thread = osRtxThreadListGet(osRtxObject(mp)); + //lint -e{923} "cast from pointer to unsigned int" + osRtxThreadWaitExit(thread, (uint32_t)block0, TRUE); + EvrRtxMemoryPoolAllocated(mp, block0); + } + } + } else { + EvrRtxMemoryPoolFreeFailed(mp, block); + } + + return status; +} + +/// Get maximum number of memory blocks in a Memory Pool. +/// \note API identical to osMemoryPoolGetCapacity +static uint32_t svcRtxMemoryPoolGetCapacity (osMemoryPoolId_t mp_id) { + os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id); + + // Check parameters + if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) { + EvrRtxMemoryPoolGetCapacity(mp, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return 0U; + } + + EvrRtxMemoryPoolGetCapacity(mp, mp->mp_info.max_blocks); + + return mp->mp_info.max_blocks; +} + +/// Get memory block size in a Memory Pool. +/// \note API identical to osMemoryPoolGetBlockSize +static uint32_t svcRtxMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id) { + os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id); + + // Check parameters + if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) { + EvrRtxMemoryPoolGetBlockSize(mp, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return 0U; + } + + EvrRtxMemoryPoolGetBlockSize(mp, mp->mp_info.block_size); + + return mp->mp_info.block_size; +} + +/// Get number of memory blocks used in a Memory Pool. +/// \note API identical to osMemoryPoolGetCount +static uint32_t svcRtxMemoryPoolGetCount (osMemoryPoolId_t mp_id) { + os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id); + + // Check parameters + if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) { + EvrRtxMemoryPoolGetCount(mp, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return 0U; + } + + EvrRtxMemoryPoolGetCount(mp, mp->mp_info.used_blocks); + + return mp->mp_info.used_blocks; +} + +/// Get number of memory blocks available in a Memory Pool. +/// \note API identical to osMemoryPoolGetSpace +static uint32_t svcRtxMemoryPoolGetSpace (osMemoryPoolId_t mp_id) { + os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id); + + // Check parameters + if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) { + EvrRtxMemoryPoolGetSpace(mp, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return 0U; + } + + EvrRtxMemoryPoolGetSpace(mp, mp->mp_info.max_blocks - mp->mp_info.used_blocks); + + return (mp->mp_info.max_blocks - mp->mp_info.used_blocks); +} + +/// Delete a Memory Pool object. +/// \note API identical to osMemoryPoolDelete +static osStatus_t svcRtxMemoryPoolDelete (osMemoryPoolId_t mp_id) { + os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id); + os_thread_t *thread; + + // Check parameters + if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) { + EvrRtxMemoryPoolError(mp, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Unblock waiting threads + if (mp->thread_list != NULL) { + do { + thread = osRtxThreadListGet(osRtxObject(mp)); + osRtxThreadWaitExit(thread, 0U, FALSE); + } while (mp->thread_list != NULL); + osRtxThreadDispatch(NULL); + } + + // Mark object as invalid + mp->id = osRtxIdInvalid; + + // Free data memory + if ((mp->flags & osRtxFlagSystemMemory) != 0U) { + (void)osRtxMemoryFree(osRtxInfo.mem.mp_data, mp->mp_info.block_base); + } + + // Free object memory + if ((mp->flags & osRtxFlagSystemObject) != 0U) { + if (osRtxInfo.mpi.memory_pool != NULL) { + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.memory_pool, mp); + } else { + (void)osRtxMemoryFree(osRtxInfo.mem.common, mp); + } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxMemoryPoolMemUsage.cnt_free++; +#endif + } + + EvrRtxMemoryPoolDestroyed(mp); + + return osOK; +} + +// Service Calls definitions +//lint ++flb "Library Begin" [MISRA Note 11] +SVC0_3(MemoryPoolNew, osMemoryPoolId_t, uint32_t, uint32_t, const osMemoryPoolAttr_t *) +SVC0_1(MemoryPoolGetName, const char *, osMemoryPoolId_t) +SVC0_2(MemoryPoolAlloc, void *, osMemoryPoolId_t, uint32_t) +SVC0_2(MemoryPoolFree, osStatus_t, osMemoryPoolId_t, void *) +SVC0_1(MemoryPoolGetCapacity, uint32_t, osMemoryPoolId_t) +SVC0_1(MemoryPoolGetBlockSize, uint32_t, osMemoryPoolId_t) +SVC0_1(MemoryPoolGetCount, uint32_t, osMemoryPoolId_t) +SVC0_1(MemoryPoolGetSpace, uint32_t, osMemoryPoolId_t) +SVC0_1(MemoryPoolDelete, osStatus_t, osMemoryPoolId_t) +//lint --flb "Library End" + + +// ==== ISR Calls ==== + +/// Allocate a memory block from a Memory Pool. +/// \note API identical to osMemoryPoolAlloc +__STATIC_INLINE +void *isrRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) { + os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id); + void *block; + + // Check parameters + if ((mp == NULL) || (mp->id != osRtxIdMemoryPool) || (timeout != 0U)) { + EvrRtxMemoryPoolError(mp, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + + // Allocate memory + block = osRtxMemoryPoolAlloc(&mp->mp_info); + if (block == NULL) { + EvrRtxMemoryPoolAllocFailed(mp); + } else { + EvrRtxMemoryPoolAllocated(mp, block); + } + + return block; +} + +/// Return an allocated memory block back to a Memory Pool. +/// \note API identical to osMemoryPoolFree +__STATIC_INLINE +osStatus_t isrRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) { + os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id); + osStatus_t status; + + // Check parameters + if ((mp == NULL) || (mp->id != osRtxIdMemoryPool)) { + EvrRtxMemoryPoolError(mp, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Free memory + status = osRtxMemoryPoolFree(&mp->mp_info, block); + if (status == osOK) { + // Register post ISR processing + osRtxPostProcess(osRtxObject(mp)); + EvrRtxMemoryPoolDeallocated(mp, block); + } else { + EvrRtxMemoryPoolFreeFailed(mp, block); + } + + return status; +} + + +// ==== Public API ==== + +/// Create and Initialize a Memory Pool object. +osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) { + osMemoryPoolId_t mp_id; + + EvrRtxMemoryPoolNew(block_count, block_size, attr); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMemoryPoolError(NULL, (int32_t)osErrorISR); + mp_id = NULL; + } else { + mp_id = __svcMemoryPoolNew(block_count, block_size, attr); + } + return mp_id; +} + +/// Get name of a Memory Pool object. +const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id) { + const char *name; + + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMemoryPoolGetName(mp_id, NULL); + name = NULL; + } else { + name = __svcMemoryPoolGetName(mp_id); + } + return name; +} + +/// Allocate a memory block from a Memory Pool. +void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) { + void *memory; + + EvrRtxMemoryPoolAlloc(mp_id, timeout); + if (IsIrqMode() || IsIrqMasked()) { + memory = isrRtxMemoryPoolAlloc(mp_id, timeout); + } else { + memory = __svcMemoryPoolAlloc(mp_id, timeout); + } + return memory; +} + +/// Return an allocated memory block back to a Memory Pool. +osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) { + osStatus_t status; + + EvrRtxMemoryPoolFree(mp_id, block); + if (IsIrqMode() || IsIrqMasked()) { + status = isrRtxMemoryPoolFree(mp_id, block); + } else { + status = __svcMemoryPoolFree(mp_id, block); + } + return status; +} + +/// Get maximum number of memory blocks in a Memory Pool. +uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id) { + uint32_t capacity; + + if (IsIrqMode() || IsIrqMasked()) { + capacity = svcRtxMemoryPoolGetCapacity(mp_id); + } else { + capacity = __svcMemoryPoolGetCapacity(mp_id); + } + return capacity; +} + +/// Get memory block size in a Memory Pool. +uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id) { + uint32_t block_size; + + if (IsIrqMode() || IsIrqMasked()) { + block_size = svcRtxMemoryPoolGetBlockSize(mp_id); + } else { + block_size = __svcMemoryPoolGetBlockSize(mp_id); + } + return block_size; +} + +/// Get number of memory blocks used in a Memory Pool. +uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id) { + uint32_t count; + + if (IsIrqMode() || IsIrqMasked()) { + count = svcRtxMemoryPoolGetCount(mp_id); + } else { + count = __svcMemoryPoolGetCount(mp_id); + } + return count; +} + +/// Get number of memory blocks available in a Memory Pool. +uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id) { + uint32_t space; + + if (IsIrqMode() || IsIrqMasked()) { + space = svcRtxMemoryPoolGetSpace(mp_id); + } else { + space = __svcMemoryPoolGetSpace(mp_id); + } + return space; +} + +/// Delete a Memory Pool object. +osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id) { + osStatus_t status; + + EvrRtxMemoryPoolDelete(mp_id); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMemoryPoolError(mp_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcMemoryPoolDelete(mp_id); + } + return status; +} diff --git a/source/rtos2/RTX/Source/rtx_msgqueue.c b/source/rtos2/RTX/Source/rtx_msgqueue.c new file mode 100644 index 000000000..5451998c6 --- /dev/null +++ b/source/rtos2/RTX/Source/rtx_msgqueue.c @@ -0,0 +1,948 @@ +/* + * Copyright (c) 2013-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Message Queue functions + * + * ----------------------------------------------------------------------------- + */ + +#include "rtx_lib.h" + + +// OS Runtime Object Memory Usage +#if ((defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0))) +osRtxObjectMemUsage_t osRtxMessageQueueMemUsage \ +__attribute__((section(".data.os.msgqueue.obj"))) = +{ 0U, 0U, 0U }; +#endif + + +// ==== Helper functions ==== + +/// Put a Message into Queue sorted by Priority (Highest at Head). +/// \param[in] mq message queue object. +/// \param[in] msg message object. +static void MessageQueuePut (os_message_queue_t *mq, os_message_t *msg) { +#if (EXCLUSIVE_ACCESS == 0) + uint32_t primask = __get_PRIMASK(); +#endif + os_message_t *prev, *next; + + if (mq->msg_last != NULL) { + prev = mq->msg_last; + next = NULL; + while ((prev != NULL) && (prev->priority < msg->priority)) { + next = prev; + prev = prev->prev; + } + msg->prev = prev; + msg->next = next; + if (prev != NULL) { + prev->next = msg; + } else { + mq->msg_first = msg; + } + if (next != NULL) { + next->prev = msg; + } else { + mq->msg_last = msg; + } + } else { + msg->prev = NULL; + msg->next = NULL; + mq->msg_first= msg; + mq->msg_last = msg; + } + +#if (EXCLUSIVE_ACCESS == 0) + __disable_irq(); + + mq->msg_count++; + + if (primask == 0U) { + __enable_irq(); + } +#else + (void)atomic_inc32(&mq->msg_count); +#endif +} + +/// Get a Message from Queue with Highest Priority. +/// \param[in] mq message queue object. +/// \return message object or NULL. +static os_message_t *MessageQueueGet (os_message_queue_t *mq) { +#if (EXCLUSIVE_ACCESS == 0) + uint32_t primask = __get_PRIMASK(); +#endif + os_message_t *msg; + uint32_t count; + uint8_t flags; + +#if (EXCLUSIVE_ACCESS == 0) + __disable_irq(); + + count = mq->msg_count; + if (count != 0U) { + mq->msg_count--; + } + + if (primask == 0U) { + __enable_irq(); + } +#else + count = atomic_dec32_nz(&mq->msg_count); +#endif + + if (count != 0U) { + msg = mq->msg_first; + + while (msg != NULL) { +#if (EXCLUSIVE_ACCESS == 0) + __disable_irq(); + + flags = msg->flags; + msg->flags = 1U; + + if (primask == 0U) { + __enable_irq(); + } +#else + flags = atomic_wr8(&msg->flags, 1U); +#endif + if (flags == 0U) { + break; + } + msg = msg->next; + } + } else { + msg = NULL; + } + + return msg; +} + +/// Remove a Message from Queue +/// \param[in] mq message queue object. +/// \param[in] msg message object. +static void MessageQueueRemove (os_message_queue_t *mq, const os_message_t *msg) { + + if (msg->prev != NULL) { + msg->prev->next = msg->next; + } else { + mq->msg_first = msg->next; + } + if (msg->next != NULL) { + msg->next->prev = msg->prev; + } else { + mq->msg_last = msg->prev; + } +} + + +// ==== Post ISR processing ==== + +/// Message Queue post ISR processing. +/// \param[in] msg message object. +static void osRtxMessageQueuePostProcess (os_message_t *msg) { + os_message_queue_t *mq; + os_message_t *msg0; + os_thread_t *thread; + const uint32_t *reg; + const void *ptr_src; + void *ptr_dst; + + if (msg->flags != 0U) { + // Remove Message + //lint -e{9079} -e{9087} "cast between pointers to different object types" + mq = *((os_message_queue_t **)(void *)&msg[1]); + MessageQueueRemove(mq, msg); + // Free memory + msg->id = osRtxIdInvalid; + (void)osRtxMemoryPoolFree(&mq->mp_info, msg); + // Check if Thread is waiting to send a Message + if (mq->thread_list != NULL) { + // Try to allocate memory + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + msg0 = osRtxMemoryPoolAlloc(&mq->mp_info); + if (msg0 != NULL) { + // Wakeup waiting Thread with highest Priority + thread = osRtxThreadListGet(osRtxObject(mq)); + osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE); + // Copy Message (R2: const void *msg_ptr, R3: uint8_t msg_prio) + reg = osRtxThreadRegPtr(thread); + //lint -e{923} "cast from unsigned int to pointer" + ptr_src = (const void *)reg[2]; + memcpy(&msg0[1], ptr_src, mq->msg_size); + // Store Message into Queue + msg0->id = osRtxIdMessage; + msg0->flags = 0U; + msg0->priority = (uint8_t)reg[3]; + MessageQueuePut(mq, msg0); + EvrRtxMessageQueueInserted(mq, ptr_src); + } + } + } else { + // New Message + //lint -e{9079} -e{9087} "cast between pointers to different object types" + mq = (void *)msg->next; + //lint -e{9087} "cast between pointers to different object types" + ptr_src = (const void *)msg->prev; + // Check if Thread is waiting to receive a Message + if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessageGet)) { + EvrRtxMessageQueueInserted(mq, ptr_src); + // Wakeup waiting Thread with highest Priority + thread = osRtxThreadListGet(osRtxObject(mq)); + osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE); + // Copy Message (R2: void *msg_ptr, R3: uint8_t *msg_prio) + reg = osRtxThreadRegPtr(thread); + //lint -e{923} "cast from unsigned int to pointer" + ptr_dst = (void *)reg[2]; + memcpy(ptr_dst, &msg[1], mq->msg_size); + if (reg[3] != 0U) { + //lint -e{923} -e{9078} "cast from unsigned int to pointer" + *((uint8_t *)reg[3]) = msg->priority; + } + EvrRtxMessageQueueRetrieved(mq, ptr_dst); + // Free memory + msg->id = osRtxIdInvalid; + (void)osRtxMemoryPoolFree(&mq->mp_info, msg); + } else { + EvrRtxMessageQueueInserted(mq, ptr_src); + MessageQueuePut(mq, msg); + } + } +} + + +// ==== Service Calls ==== + +/// Create and Initialize a Message Queue object. +/// \note API identical to osMessageQueueNew +static osMessageQueueId_t svcRtxMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { + os_message_queue_t *mq; + void *mq_mem; + uint32_t mq_size; + uint32_t block_size; + uint32_t size; + uint8_t flags; + const char *name; + + // Check parameters + if ((msg_count == 0U) || (msg_size == 0U)) { + EvrRtxMessageQueueError(NULL, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + block_size = ((msg_size + 3U) & ~3UL) + sizeof(os_message_t); + if ((__CLZ(msg_count) + __CLZ(block_size)) < 32U) { + EvrRtxMessageQueueError(NULL, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + + size = msg_count * block_size; + + // Process attributes + if (attr != NULL) { + name = attr->name; + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6] + mq = attr->cb_mem; + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6] + mq_mem = attr->mq_mem; + mq_size = attr->mq_size; + if (mq != NULL) { + //lint -e(923) -e(9078) "cast from pointer to unsigned int" [MISRA Note 7] + if ((((uint32_t)mq & 3U) != 0U) || (attr->cb_size < sizeof(os_message_queue_t))) { + EvrRtxMessageQueueError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + } else { + if (attr->cb_size != 0U) { + EvrRtxMessageQueueError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + } + if (mq_mem != NULL) { + //lint -e(923) -e(9078) "cast from pointer to unsigned int" [MISRA Note 7] + if ((((uint32_t)mq_mem & 3U) != 0U) || (mq_size < size)) { + EvrRtxMessageQueueError(NULL, osRtxErrorInvalidDataMemory); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + } else { + if (mq_size != 0U) { + EvrRtxMessageQueueError(NULL, osRtxErrorInvalidDataMemory); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + } + } else { + name = NULL; + mq = NULL; + mq_mem = NULL; + } + + // Allocate object memory if not provided + if (mq == NULL) { + if (osRtxInfo.mpi.message_queue != NULL) { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + mq = osRtxMemoryPoolAlloc(osRtxInfo.mpi.message_queue); + } else { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + mq = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_message_queue_t), 1U); + } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + if (mq != NULL) { + uint32_t used; + osRtxMessageQueueMemUsage.cnt_alloc++; + used = osRtxMessageQueueMemUsage.cnt_alloc - osRtxMessageQueueMemUsage.cnt_free; + if (osRtxMessageQueueMemUsage.max_used < used) { + osRtxMessageQueueMemUsage.max_used = used; + } + } +#endif + flags = osRtxFlagSystemObject; + } else { + flags = 0U; + } + + // Allocate data memory if not provided + if ((mq != NULL) && (mq_mem == NULL)) { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + mq_mem = osRtxMemoryAlloc(osRtxInfo.mem.mq_data, size, 0U); + if (mq_mem == NULL) { + if ((flags & osRtxFlagSystemObject) != 0U) { + if (osRtxInfo.mpi.message_queue != NULL) { + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.message_queue, mq); + } else { + (void)osRtxMemoryFree(osRtxInfo.mem.common, mq); + } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxMessageQueueMemUsage.cnt_free++; +#endif + } + mq = NULL; + } else { + memset(mq_mem, 0, size); + } + flags |= osRtxFlagSystemMemory; + } + + if (mq != NULL) { + // Initialize control block + mq->id = osRtxIdMessageQueue; + mq->flags = flags; + mq->name = name; + mq->thread_list = NULL; + mq->msg_size = msg_size; + mq->msg_count = 0U; + mq->msg_first = NULL; + mq->msg_last = NULL; + (void)osRtxMemoryPoolInit(&mq->mp_info, msg_count, block_size, mq_mem); + + // Register post ISR processing function + osRtxInfo.post_process.message = osRtxMessageQueuePostProcess; + + EvrRtxMessageQueueCreated(mq, mq->name); + } else { + EvrRtxMessageQueueError(NULL, (int32_t)osErrorNoMemory); + } + + return mq; +} + +/// Get name of a Message Queue object. +/// \note API identical to osMessageQueueGetName +static const char *svcRtxMessageQueueGetName (osMessageQueueId_t mq_id) { + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); + + // Check parameters + if ((mq == NULL) || (mq->id != osRtxIdMessageQueue)) { + EvrRtxMessageQueueGetName(mq, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + + EvrRtxMessageQueueGetName(mq, mq->name); + + return mq->name; +} + +/// Put a Message into a Queue or timeout if Queue is full. +/// \note API identical to osMessageQueuePut +static osStatus_t svcRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); + os_message_t *msg; + os_thread_t *thread; + uint32_t *reg; + void *ptr; + osStatus_t status; + + // Check parameters + if ((mq == NULL) || (mq->id != osRtxIdMessageQueue) || (msg_ptr == NULL)) { + EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Check if Thread is waiting to receive a Message + if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessageGet)) { + EvrRtxMessageQueueInserted(mq, msg_ptr); + // Wakeup waiting Thread with highest Priority + thread = osRtxThreadListGet(osRtxObject(mq)); + osRtxThreadWaitExit(thread, (uint32_t)osOK, TRUE); + // Copy Message (R2: void *msg_ptr, R3: uint8_t *msg_prio) + reg = osRtxThreadRegPtr(thread); + //lint -e{923} "cast from unsigned int to pointer" + ptr = (void *)reg[2]; + memcpy(ptr, msg_ptr, mq->msg_size); + if (reg[3] != 0U) { + //lint -e{923} -e{9078} "cast from unsigned int to pointer" + *((uint8_t *)reg[3]) = msg_prio; + } + EvrRtxMessageQueueRetrieved(mq, ptr); + status = osOK; + } else { + // Try to allocate memory + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + msg = osRtxMemoryPoolAlloc(&mq->mp_info); + if (msg != NULL) { + // Copy Message + memcpy(&msg[1], msg_ptr, mq->msg_size); + // Put Message into Queue + msg->id = osRtxIdMessage; + msg->flags = 0U; + msg->priority = msg_prio; + MessageQueuePut(mq, msg); + EvrRtxMessageQueueInserted(mq, msg_ptr); + status = osOK; + } else { + // No memory available + if (timeout != 0U) { + EvrRtxMessageQueuePutPending(mq, msg_ptr, timeout); + // Suspend current Thread + if (osRtxThreadWaitEnter(osRtxThreadWaitingMessagePut, timeout)) { + osRtxThreadListPut(osRtxObject(mq), osRtxThreadGetRunning()); + // Save arguments (R2: const void *msg_ptr, R3: uint8_t msg_prio) + //lint -e{923} -e{9078} "cast from unsigned int to pointer" + reg = (uint32_t *)(__get_PSP()); + //lint -e{923} -e{9078} "cast from pointer to unsigned int" + reg[2] = (uint32_t)msg_ptr; + //lint -e{923} -e{9078} "cast from pointer to unsigned int" + reg[3] = (uint32_t)msg_prio; + } else { + EvrRtxMessageQueuePutTimeout(mq); + } + status = osErrorTimeout; + } else { + EvrRtxMessageQueueNotInserted(mq, msg_ptr); + status = osErrorResource; + } + } + } + + return status; +} + +/// Get a Message from a Queue or timeout if Queue is empty. +/// \note API identical to osMessageQueueGet +static osStatus_t svcRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); + os_message_t *msg; + os_thread_t *thread; + uint32_t *reg; + const void *ptr; + osStatus_t status; + + // Check parameters + if ((mq == NULL) || (mq->id != osRtxIdMessageQueue) || (msg_ptr == NULL)) { + EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Get Message from Queue + msg = MessageQueueGet(mq); + if (msg != NULL) { + MessageQueueRemove(mq, msg); + // Copy Message + memcpy(msg_ptr, &msg[1], mq->msg_size); + if (msg_prio != NULL) { + *msg_prio = msg->priority; + } + EvrRtxMessageQueueRetrieved(mq, msg_ptr); + // Free memory + msg->id = osRtxIdInvalid; + (void)osRtxMemoryPoolFree(&mq->mp_info, msg); + // Check if Thread is waiting to send a Message + if (mq->thread_list != NULL) { + // Try to allocate memory + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + msg = osRtxMemoryPoolAlloc(&mq->mp_info); + if (msg != NULL) { + // Wakeup waiting Thread with highest Priority + thread = osRtxThreadListGet(osRtxObject(mq)); + osRtxThreadWaitExit(thread, (uint32_t)osOK, TRUE); + // Copy Message (R2: const void *msg_ptr, R3: uint8_t msg_prio) + reg = osRtxThreadRegPtr(thread); + //lint -e{923} "cast from unsigned int to pointer" + ptr = (const void *)reg[2]; + memcpy(&msg[1], ptr, mq->msg_size); + // Store Message into Queue + msg->id = osRtxIdMessage; + msg->flags = 0U; + msg->priority = (uint8_t)reg[3]; + MessageQueuePut(mq, msg); + EvrRtxMessageQueueInserted(mq, ptr); + } + } + status = osOK; + } else { + // No Message available + if (timeout != 0U) { + EvrRtxMessageQueueGetPending(mq, msg_ptr, timeout); + // Suspend current Thread + if (osRtxThreadWaitEnter(osRtxThreadWaitingMessageGet, timeout)) { + osRtxThreadListPut(osRtxObject(mq), osRtxThreadGetRunning()); + // Save arguments (R2: void *msg_ptr, R3: uint8_t *msg_prio) + //lint -e{923} -e{9078} "cast from unsigned int to pointer" + reg = (uint32_t *)(__get_PSP()); + //lint -e{923} -e{9078} "cast from pointer to unsigned int" + reg[2] = (uint32_t)msg_ptr; + //lint -e{923} -e{9078} "cast from pointer to unsigned int" + reg[3] = (uint32_t)msg_prio; + } else { + EvrRtxMessageQueueGetTimeout(mq); + } + status = osErrorTimeout; + } else { + EvrRtxMessageQueueNotRetrieved(mq, msg_ptr); + status = osErrorResource; + } + } + + return status; +} + +/// Get maximum number of messages in a Message Queue. +/// \note API identical to osMessageQueueGetCapacity +static uint32_t svcRtxMessageQueueGetCapacity (osMessageQueueId_t mq_id) { + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); + + // Check parameters + if ((mq == NULL) || (mq->id != osRtxIdMessageQueue)) { + EvrRtxMessageQueueGetCapacity(mq, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return 0U; + } + + EvrRtxMessageQueueGetCapacity(mq, mq->mp_info.max_blocks); + + return mq->mp_info.max_blocks; +} + +/// Get maximum message size in a Memory Pool. +/// \note API identical to osMessageQueueGetMsgSize +static uint32_t svcRtxMessageQueueGetMsgSize (osMessageQueueId_t mq_id) { + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); + + // Check parameters + if ((mq == NULL) || (mq->id != osRtxIdMessageQueue)) { + EvrRtxMessageQueueGetMsgSize(mq, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return 0U; + } + + EvrRtxMessageQueueGetMsgSize(mq, mq->msg_size); + + return mq->msg_size; +} + +/// Get number of queued messages in a Message Queue. +/// \note API identical to osMessageQueueGetCount +static uint32_t svcRtxMessageQueueGetCount (osMessageQueueId_t mq_id) { + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); + + // Check parameters + if ((mq == NULL) || (mq->id != osRtxIdMessageQueue)) { + EvrRtxMessageQueueGetCount(mq, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return 0U; + } + + EvrRtxMessageQueueGetCount(mq, mq->msg_count); + + return mq->msg_count; +} + +/// Get number of available slots for messages in a Message Queue. +/// \note API identical to osMessageQueueGetSpace +static uint32_t svcRtxMessageQueueGetSpace (osMessageQueueId_t mq_id) { + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); + + // Check parameters + if ((mq == NULL) || (mq->id != osRtxIdMessageQueue)) { + EvrRtxMessageQueueGetSpace(mq, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return 0U; + } + + EvrRtxMessageQueueGetSpace(mq, mq->mp_info.max_blocks - mq->msg_count); + + return (mq->mp_info.max_blocks - mq->msg_count); +} + +/// Reset a Message Queue to initial empty state. +/// \note API identical to osMessageQueueReset +static osStatus_t svcRtxMessageQueueReset (osMessageQueueId_t mq_id) { + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); + os_message_t *msg; + os_thread_t *thread; + const uint32_t *reg; + const void *ptr; + + // Check parameters + if ((mq == NULL) || (mq->id != osRtxIdMessageQueue)) { + EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Remove Messages from Queue + for (;;) { + // Get Message from Queue + msg = MessageQueueGet(mq); + if (msg == NULL) { + break; + } + MessageQueueRemove(mq, msg); + EvrRtxMessageQueueRetrieved(mq, NULL); + // Free memory + msg->id = osRtxIdInvalid; + (void)osRtxMemoryPoolFree(&mq->mp_info, msg); + } + + // Check if Threads are waiting to send Messages + if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessagePut)) { + do { + // Try to allocate memory + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + msg = osRtxMemoryPoolAlloc(&mq->mp_info); + if (msg != NULL) { + // Wakeup waiting Thread with highest Priority + thread = osRtxThreadListGet(osRtxObject(mq)); + osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE); + // Copy Message (R2: const void *msg_ptr, R3: uint8_t msg_prio) + reg = osRtxThreadRegPtr(thread); + //lint -e{923} "cast from unsigned int to pointer" + ptr = (const void *)reg[2]; + memcpy(&msg[1], ptr, mq->msg_size); + // Store Message into Queue + msg->id = osRtxIdMessage; + msg->flags = 0U; + msg->priority = (uint8_t)reg[3]; + MessageQueuePut(mq, msg); + EvrRtxMessageQueueInserted(mq, ptr); + } + } while ((msg != NULL) && (mq->thread_list != NULL)); + osRtxThreadDispatch(NULL); + } + + EvrRtxMessageQueueResetDone(mq); + + return osOK; +} + +/// Delete a Message Queue object. +/// \note API identical to osMessageQueueDelete +static osStatus_t svcRtxMessageQueueDelete (osMessageQueueId_t mq_id) { + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); + os_thread_t *thread; + + // Check parameters + if ((mq == NULL) || (mq->id != osRtxIdMessageQueue)) { + EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Unblock waiting threads + if (mq->thread_list != NULL) { + do { + thread = osRtxThreadListGet(osRtxObject(mq)); + osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE); + } while (mq->thread_list != NULL); + osRtxThreadDispatch(NULL); + } + + // Mark object as invalid + mq->id = osRtxIdInvalid; + + // Free data memory + if ((mq->flags & osRtxFlagSystemMemory) != 0U) { + (void)osRtxMemoryFree(osRtxInfo.mem.mq_data, mq->mp_info.block_base); + } + + // Free object memory + if ((mq->flags & osRtxFlagSystemObject) != 0U) { + if (osRtxInfo.mpi.message_queue != NULL) { + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.message_queue, mq); + } else { + (void)osRtxMemoryFree(osRtxInfo.mem.common, mq); + } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxMessageQueueMemUsage.cnt_free++; +#endif + } + + EvrRtxMessageQueueDestroyed(mq); + + return osOK; +} + +// Service Calls definitions +//lint ++flb "Library Begin" [MISRA Note 11] +SVC0_3(MessageQueueNew, osMessageQueueId_t, uint32_t, uint32_t, const osMessageQueueAttr_t *) +SVC0_1(MessageQueueGetName, const char *, osMessageQueueId_t) +SVC0_4(MessageQueuePut, osStatus_t, osMessageQueueId_t, const void *, uint8_t, uint32_t) +SVC0_4(MessageQueueGet, osStatus_t, osMessageQueueId_t, void *, uint8_t *, uint32_t) +SVC0_1(MessageQueueGetCapacity, uint32_t, osMessageQueueId_t) +SVC0_1(MessageQueueGetMsgSize, uint32_t, osMessageQueueId_t) +SVC0_1(MessageQueueGetCount, uint32_t, osMessageQueueId_t) +SVC0_1(MessageQueueGetSpace, uint32_t, osMessageQueueId_t) +SVC0_1(MessageQueueReset, osStatus_t, osMessageQueueId_t) +SVC0_1(MessageQueueDelete, osStatus_t, osMessageQueueId_t) +//lint --flb "Library End" + + +// ==== ISR Calls ==== + +/// Put a Message into a Queue or timeout if Queue is full. +/// \note API identical to osMessageQueuePut +__STATIC_INLINE +osStatus_t isrRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); + os_message_t *msg; + osStatus_t status; + + // Check parameters + if ((mq == NULL) || (mq->id != osRtxIdMessageQueue) || (msg_ptr == NULL) || (timeout != 0U)) { + EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Try to allocate memory + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + msg = osRtxMemoryPoolAlloc(&mq->mp_info); + if (msg != NULL) { + // Copy Message + memcpy(&msg[1], msg_ptr, mq->msg_size); + msg->id = osRtxIdMessage; + msg->flags = 0U; + msg->priority = msg_prio; + // Register post ISR processing + //lint -e{9079} -e{9087} "cast between pointers to different object types" + *((const void **)(void *)&msg->prev) = msg_ptr; + //lint -e{9079} -e{9087} "cast between pointers to different object types" + *( (void **) &msg->next) = mq; + osRtxPostProcess(osRtxObject(msg)); + EvrRtxMessageQueueInsertPending(mq, msg_ptr); + status = osOK; + } else { + // No memory available + EvrRtxMessageQueueNotInserted(mq, msg_ptr); + status = osErrorResource; + } + + return status; +} + +/// Get a Message from a Queue or timeout if Queue is empty. +/// \note API identical to osMessageQueueGet +__STATIC_INLINE +osStatus_t isrRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { + os_message_queue_t *mq = osRtxMessageQueueId(mq_id); + os_message_t *msg; + osStatus_t status; + + // Check parameters + if ((mq == NULL) || (mq->id != osRtxIdMessageQueue) || (msg_ptr == NULL) || (timeout != 0U)) { + EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Get Message from Queue + msg = MessageQueueGet(mq); + if (msg != NULL) { + // Copy Message + memcpy(msg_ptr, &msg[1], mq->msg_size); + if (msg_prio != NULL) { + *msg_prio = msg->priority; + } + // Register post ISR processing + //lint -e{9079} -e{9087} "cast between pointers to different object types" + *((os_message_queue_t **)(void *)&msg[1]) = mq; + osRtxPostProcess(osRtxObject(msg)); + EvrRtxMessageQueueRetrieved(mq, msg_ptr); + status = osOK; + } else { + // No Message available + EvrRtxMessageQueueNotRetrieved(mq, msg_ptr); + status = osErrorResource; + } + + return status; +} + + +// ==== Public API ==== + +/// Create and Initialize a Message Queue object. +osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { + osMessageQueueId_t mq_id; + + EvrRtxMessageQueueNew(msg_count, msg_size, attr); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMessageQueueError(NULL, (int32_t)osErrorISR); + mq_id = NULL; + } else { + mq_id = __svcMessageQueueNew(msg_count, msg_size, attr); + } + return mq_id; +} + +/// Get name of a Message Queue object. +const char *osMessageQueueGetName (osMessageQueueId_t mq_id) { + const char *name; + + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMessageQueueGetName(mq_id, NULL); + name = NULL; + } else { + name = __svcMessageQueueGetName(mq_id); + } + return name; +} + +/// Put a Message into a Queue or timeout if Queue is full. +osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { + osStatus_t status; + + EvrRtxMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout); + if (IsIrqMode() || IsIrqMasked()) { + status = isrRtxMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout); + } else { + status = __svcMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout); + } + return status; +} + +/// Get a Message from a Queue or timeout if Queue is empty. +osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { + osStatus_t status; + + EvrRtxMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout); + if (IsIrqMode() || IsIrqMasked()) { + status = isrRtxMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout); + } else { + status = __svcMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout); + } + return status; +} + +/// Get maximum number of messages in a Message Queue. +uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id) { + uint32_t capacity; + + if (IsIrqMode() || IsIrqMasked()) { + capacity = svcRtxMessageQueueGetCapacity(mq_id); + } else { + capacity = __svcMessageQueueGetCapacity(mq_id); + } + return capacity; +} + +/// Get maximum message size in a Memory Pool. +uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id) { + uint32_t msg_size; + + if (IsIrqMode() || IsIrqMasked()) { + msg_size = svcRtxMessageQueueGetMsgSize(mq_id); + } else { + msg_size = __svcMessageQueueGetMsgSize(mq_id); + } + return msg_size; +} + +/// Get number of queued messages in a Message Queue. +uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id) { + uint32_t count; + + if (IsIrqMode() || IsIrqMasked()) { + count = svcRtxMessageQueueGetCount(mq_id); + } else { + count = __svcMessageQueueGetCount(mq_id); + } + return count; +} + +/// Get number of available slots for messages in a Message Queue. +uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id) { + uint32_t space; + + if (IsIrqMode() || IsIrqMasked()) { + space = svcRtxMessageQueueGetSpace(mq_id); + } else { + space = __svcMessageQueueGetSpace(mq_id); + } + return space; +} + +/// Reset a Message Queue to initial empty state. +osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id) { + osStatus_t status; + + EvrRtxMessageQueueReset(mq_id); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMessageQueueError(mq_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcMessageQueueReset(mq_id); + } + return status; +} + +/// Delete a Message Queue object. +osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id) { + osStatus_t status; + + EvrRtxMessageQueueDelete(mq_id); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMessageQueueError(mq_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcMessageQueueDelete(mq_id); + } + return status; +} diff --git a/source/rtos2/RTX/Source/rtx_mutex.c b/source/rtos2/RTX/Source/rtx_mutex.c new file mode 100644 index 000000000..e97def252 --- /dev/null +++ b/source/rtos2/RTX/Source/rtx_mutex.c @@ -0,0 +1,570 @@ +/* + * Copyright (c) 2013-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Mutex functions + * + * ----------------------------------------------------------------------------- + */ + +#include "rtx_lib.h" + + +// OS Runtime Object Memory Usage +#if ((defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0))) +osRtxObjectMemUsage_t osRtxMutexMemUsage \ +__attribute__((section(".data.os.mutex.obj"))) = +{ 0U, 0U, 0U }; +#endif + + +// ==== Library functions ==== + +/// Release Mutex list when owner Thread terminates. +/// \param[in] mutex_list mutex list. +void osRtxMutexOwnerRelease (os_mutex_t *mutex_list) { + os_mutex_t *mutex; + os_mutex_t *mutex_next; + os_thread_t *thread; + + mutex = mutex_list; + while (mutex != NULL) { + mutex_next = mutex->owner_next; + // Check if Mutex is Robust + if ((mutex->attr & osMutexRobust) != 0U) { + // Clear Lock counter + mutex->lock = 0U; + EvrRtxMutexReleased(mutex, 0U); + // Check if Thread is waiting for a Mutex + if (mutex->thread_list != NULL) { + // Wakeup waiting Thread with highest Priority + thread = osRtxThreadListGet(osRtxObject(mutex)); + osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE); + // Thread is the new Mutex owner + mutex->owner_thread = thread; + mutex->owner_prev = NULL; + mutex->owner_next = thread->mutex_list; + if (thread->mutex_list != NULL) { + thread->mutex_list->owner_prev = mutex; + } + thread->mutex_list = mutex; + mutex->lock = 1U; + EvrRtxMutexAcquired(mutex, 1U); + } + } + mutex = mutex_next; + } +} + +/// Restore Mutex owner Thread priority. +/// \param[in] mutex mutex object. +/// \param[in] thread_wakeup thread wakeup object. +void osRtxMutexOwnerRestore (const os_mutex_t *mutex, const os_thread_t *thread_wakeup) { + const os_mutex_t *mutex0; + os_thread_t *thread; + os_thread_t *thread0; + int8_t priority; + + // Restore owner Thread priority + if ((mutex->attr & osMutexPrioInherit) != 0U) { + thread = mutex->owner_thread; + priority = thread->priority_base; + mutex0 = thread->mutex_list; + // Check Mutexes owned by Thread + do { + // Check Threads waiting for Mutex + thread0 = mutex0->thread_list; + if (thread0 == thread_wakeup) { + // Skip thread that is waken-up + thread0 = thread0->thread_next; + } + if ((thread0 != NULL) && (thread0->priority > priority)) { + // Higher priority Thread is waiting for Mutex + priority = thread0->priority; + } + mutex0 = mutex0->owner_next; + } while (mutex0 != NULL); + if (thread->priority != priority) { + thread->priority = priority; + osRtxThreadListSort(thread); + } + } +} + + +// ==== Service Calls ==== + +/// Create and Initialize a Mutex object. +/// \note API identical to osMutexNew +static osMutexId_t svcRtxMutexNew (const osMutexAttr_t *attr) { + os_mutex_t *mutex; + uint32_t attr_bits; + uint8_t flags; + const char *name; + + // Process attributes + if (attr != NULL) { + name = attr->name; + attr_bits = attr->attr_bits; + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6] + mutex = attr->cb_mem; + if (mutex != NULL) { + //lint -e(923) -e(9078) "cast from pointer to unsigned int" [MISRA Note 7] + if ((((uint32_t)mutex & 3U) != 0U) || (attr->cb_size < sizeof(os_mutex_t))) { + EvrRtxMutexError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + } else { + if (attr->cb_size != 0U) { + EvrRtxMutexError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + } + } else { + name = NULL; + attr_bits = 0U; + mutex = NULL; + } + + // Allocate object memory if not provided + if (mutex == NULL) { + if (osRtxInfo.mpi.mutex != NULL) { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + mutex = osRtxMemoryPoolAlloc(osRtxInfo.mpi.mutex); + } else { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + mutex = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_mutex_t), 1U); + } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + if (mutex != NULL) { + uint32_t used; + osRtxMutexMemUsage.cnt_alloc++; + used = osRtxMutexMemUsage.cnt_alloc - osRtxMutexMemUsage.cnt_free; + if (osRtxMutexMemUsage.max_used < used) { + osRtxMutexMemUsage.max_used = used; + } + } +#endif + flags = osRtxFlagSystemObject; + } else { + flags = 0U; + } + + if (mutex != NULL) { + // Initialize control block + mutex->id = osRtxIdMutex; + mutex->flags = flags; + mutex->attr = (uint8_t)attr_bits; + mutex->name = name; + mutex->thread_list = NULL; + mutex->owner_thread = NULL; + mutex->owner_prev = NULL; + mutex->owner_next = NULL; + mutex->lock = 0U; + + EvrRtxMutexCreated(mutex, mutex->name); + } else { + EvrRtxMutexError(NULL, (int32_t)osErrorNoMemory); + } + + return mutex; +} + +/// Get name of a Mutex object. +/// \note API identical to osMutexGetName +static const char *svcRtxMutexGetName (osMutexId_t mutex_id) { + os_mutex_t *mutex = osRtxMutexId(mutex_id); + + // Check parameters + if ((mutex == NULL) || (mutex->id != osRtxIdMutex)) { + EvrRtxMutexGetName(mutex, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + + EvrRtxMutexGetName(mutex, mutex->name); + + return mutex->name; +} + +/// Acquire a Mutex or timeout if it is locked. +/// \note API identical to osMutexAcquire +static osStatus_t svcRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { + os_mutex_t *mutex = osRtxMutexId(mutex_id); + os_thread_t *thread; + osStatus_t status; + + // Check running thread + thread = osRtxThreadGetRunning(); + if (thread == NULL) { + EvrRtxMutexError(mutex, osRtxErrorKernelNotRunning); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osError; + } + + // Check parameters + if ((mutex == NULL) || (mutex->id != osRtxIdMutex)) { + EvrRtxMutexError(mutex, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Check if Mutex is not locked + if (mutex->lock == 0U) { + // Acquire Mutex + mutex->owner_thread = thread; + mutex->owner_prev = NULL; + mutex->owner_next = thread->mutex_list; + if (thread->mutex_list != NULL) { + thread->mutex_list->owner_prev = mutex; + } + thread->mutex_list = mutex; + mutex->lock = 1U; + EvrRtxMutexAcquired(mutex, mutex->lock); + status = osOK; + } else { + // Check if Mutex is recursive and running Thread is the owner + if (((mutex->attr & osMutexRecursive) != 0U) && (mutex->owner_thread == thread)) { + // Try to increment lock counter + if (mutex->lock == osRtxMutexLockLimit) { + EvrRtxMutexError(mutex, osRtxErrorMutexLockLimit); + status = osErrorResource; + } else { + mutex->lock++; + EvrRtxMutexAcquired(mutex, mutex->lock); + status = osOK; + } + } else { + // Check if timeout is specified + if (timeout != 0U) { + // Check if Priority inheritance protocol is enabled + if ((mutex->attr & osMutexPrioInherit) != 0U) { + // Raise priority of owner Thread if lower than priority of running Thread + if (mutex->owner_thread->priority < thread->priority) { + mutex->owner_thread->priority = thread->priority; + osRtxThreadListSort(mutex->owner_thread); + } + } + EvrRtxMutexAcquirePending(mutex, timeout); + // Suspend current Thread + if (osRtxThreadWaitEnter(osRtxThreadWaitingMutex, timeout)) { + osRtxThreadListPut(osRtxObject(mutex), thread); + } else { + EvrRtxMutexAcquireTimeout(mutex); + } + status = osErrorTimeout; + } else { + EvrRtxMutexNotAcquired(mutex); + status = osErrorResource; + } + } + } + + return status; +} + +/// Release a Mutex that was acquired by osMutexAcquire. +/// \note API identical to osMutexRelease +static osStatus_t svcRtxMutexRelease (osMutexId_t mutex_id) { + os_mutex_t *mutex = osRtxMutexId(mutex_id); + const os_mutex_t *mutex0; + os_thread_t *thread; + int8_t priority; + + // Check running thread + thread = osRtxThreadGetRunning(); + if (thread == NULL) { + EvrRtxMutexError(mutex, osRtxErrorKernelNotRunning); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osError; + } + + // Check parameters + if ((mutex == NULL) || (mutex->id != osRtxIdMutex)) { + EvrRtxMutexError(mutex, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Check if Mutex is not locked + if (mutex->lock == 0U) { + EvrRtxMutexError(mutex, osRtxErrorMutexNotLocked); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorResource; + } + + // Check if running Thread is not the owner + if (mutex->owner_thread != thread) { + EvrRtxMutexError(mutex, osRtxErrorMutexNotOwned); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorResource; + } + + // Decrement Lock counter + mutex->lock--; + EvrRtxMutexReleased(mutex, mutex->lock); + + // Check Lock counter + if (mutex->lock == 0U) { + + // Remove Mutex from Thread owner list + if (mutex->owner_next != NULL) { + mutex->owner_next->owner_prev = mutex->owner_prev; + } + if (mutex->owner_prev != NULL) { + mutex->owner_prev->owner_next = mutex->owner_next; + } else { + thread->mutex_list = mutex->owner_next; + } + + // Restore running Thread priority + if ((mutex->attr & osMutexPrioInherit) != 0U) { + priority = thread->priority_base; + mutex0 = thread->mutex_list; + // Check mutexes owned by running Thread + while (mutex0 != NULL) { + if ((mutex0->thread_list != NULL) && (mutex0->thread_list->priority > priority)) { + // Higher priority Thread is waiting for Mutex + priority = mutex0->thread_list->priority; + } + mutex0 = mutex0->owner_next; + } + thread->priority = priority; + } + + // Check if Thread is waiting for a Mutex + if (mutex->thread_list != NULL) { + // Wakeup waiting Thread with highest Priority + thread = osRtxThreadListGet(osRtxObject(mutex)); + osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE); + // Thread is the new Mutex owner + mutex->owner_thread = thread; + mutex->owner_prev = NULL; + mutex->owner_next = thread->mutex_list; + if (thread->mutex_list != NULL) { + thread->mutex_list->owner_prev = mutex; + } + thread->mutex_list = mutex; + mutex->lock = 1U; + EvrRtxMutexAcquired(mutex, 1U); + } + + osRtxThreadDispatch(NULL); + } + + return osOK; +} + +/// Get Thread which owns a Mutex object. +/// \note API identical to osMutexGetOwner +static osThreadId_t svcRtxMutexGetOwner (osMutexId_t mutex_id) { + os_mutex_t *mutex = osRtxMutexId(mutex_id); + + // Check parameters + if ((mutex == NULL) || (mutex->id != osRtxIdMutex)) { + EvrRtxMutexGetOwner(mutex, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + + // Check if Mutex is not locked + if (mutex->lock == 0U) { + EvrRtxMutexGetOwner(mutex, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + + EvrRtxMutexGetOwner(mutex, mutex->owner_thread); + + return mutex->owner_thread; +} + +/// Delete a Mutex object. +/// \note API identical to osMutexDelete +static osStatus_t svcRtxMutexDelete (osMutexId_t mutex_id) { + os_mutex_t *mutex = osRtxMutexId(mutex_id); + const os_mutex_t *mutex0; + os_thread_t *thread; + int8_t priority; + + // Check parameters + if ((mutex == NULL) || (mutex->id != osRtxIdMutex)) { + EvrRtxMutexError(mutex, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Check if Mutex is locked + if (mutex->lock != 0U) { + + thread = mutex->owner_thread; + + // Remove Mutex from Thread owner list + if (mutex->owner_next != NULL) { + mutex->owner_next->owner_prev = mutex->owner_prev; + } + if (mutex->owner_prev != NULL) { + mutex->owner_prev->owner_next = mutex->owner_next; + } else { + thread->mutex_list = mutex->owner_next; + } + + // Restore owner Thread priority + if ((mutex->attr & osMutexPrioInherit) != 0U) { + priority = thread->priority_base; + mutex0 = thread->mutex_list; + // Check Mutexes owned by Thread + while (mutex0 != NULL) { + if ((mutex0->thread_list != NULL) && (mutex0->thread_list->priority > priority)) { + // Higher priority Thread is waiting for Mutex + priority = mutex0->thread_list->priority; + } + mutex0 = mutex0->owner_next; + } + if (thread->priority != priority) { + thread->priority = priority; + osRtxThreadListSort(thread); + } + } + + // Unblock waiting threads + while (mutex->thread_list != NULL) { + thread = osRtxThreadListGet(osRtxObject(mutex)); + osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE); + } + + osRtxThreadDispatch(NULL); + } + + // Mark object as invalid + mutex->id = osRtxIdInvalid; + + // Free object memory + if ((mutex->flags & osRtxFlagSystemObject) != 0U) { + if (osRtxInfo.mpi.mutex != NULL) { + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.mutex, mutex); + } else { + (void)osRtxMemoryFree(osRtxInfo.mem.common, mutex); + } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxMutexMemUsage.cnt_free++; +#endif + } + + EvrRtxMutexDestroyed(mutex); + + return osOK; +} + +// Service Calls definitions +//lint ++flb "Library Begin" [MISRA Note 11] +SVC0_1(MutexNew, osMutexId_t, const osMutexAttr_t *) +SVC0_1(MutexGetName, const char *, osMutexId_t) +SVC0_2(MutexAcquire, osStatus_t, osMutexId_t, uint32_t) +SVC0_1(MutexRelease, osStatus_t, osMutexId_t) +SVC0_1(MutexGetOwner, osThreadId_t, osMutexId_t) +SVC0_1(MutexDelete, osStatus_t, osMutexId_t) +//lint --flb "Library End" + + +// ==== Public API ==== + +/// Create and Initialize a Mutex object. +osMutexId_t osMutexNew (const osMutexAttr_t *attr) { + osMutexId_t mutex_id; + + EvrRtxMutexNew(attr); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMutexError(NULL, (int32_t)osErrorISR); + mutex_id = NULL; + } else { + mutex_id = __svcMutexNew(attr); + } + return mutex_id; +} + +/// Get name of a Mutex object. +const char *osMutexGetName (osMutexId_t mutex_id) { + const char *name; + + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMutexGetName(mutex_id, NULL); + name = NULL; + } else { + name = __svcMutexGetName(mutex_id); + } + return name; +} + +/// Acquire a Mutex or timeout if it is locked. +osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { + osStatus_t status; + + EvrRtxMutexAcquire(mutex_id, timeout); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMutexError(mutex_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcMutexAcquire(mutex_id, timeout); + } + return status; +} + +/// Release a Mutex that was acquired by \ref osMutexAcquire. +osStatus_t osMutexRelease (osMutexId_t mutex_id) { + osStatus_t status; + + EvrRtxMutexRelease(mutex_id); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMutexError(mutex_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcMutexRelease(mutex_id); + } + return status; +} + +/// Get Thread which owns a Mutex object. +osThreadId_t osMutexGetOwner (osMutexId_t mutex_id) { + osThreadId_t thread; + + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMutexGetOwner(mutex_id, NULL); + thread = NULL; + } else { + thread = __svcMutexGetOwner(mutex_id); + } + return thread; +} + +/// Delete a Mutex object. +osStatus_t osMutexDelete (osMutexId_t mutex_id) { + osStatus_t status; + + EvrRtxMutexDelete(mutex_id); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxMutexError(mutex_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcMutexDelete(mutex_id); + } + return status; +} diff --git a/source/rtos2/RTX/Source/rtx_semaphore.c b/source/rtos2/RTX/Source/rtx_semaphore.c new file mode 100644 index 000000000..ebca85543 --- /dev/null +++ b/source/rtos2/RTX/Source/rtx_semaphore.c @@ -0,0 +1,507 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Semaphore functions + * + * ----------------------------------------------------------------------------- + */ + +#include "rtx_lib.h" + + +// OS Runtime Object Memory Usage +#if ((defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0))) +osRtxObjectMemUsage_t osRtxSemaphoreMemUsage \ +__attribute__((section(".data.os.semaphore.obj"))) = +{ 0U, 0U, 0U }; +#endif + + +// ==== Helper functions ==== + +/// Decrement Semaphore tokens. +/// \param[in] semaphore semaphore object. +/// \return 1 - success, 0 - failure. +static uint32_t SemaphoreTokenDecrement (os_semaphore_t *semaphore) { +#if (EXCLUSIVE_ACCESS == 0) + uint32_t primask = __get_PRIMASK(); +#endif + uint32_t ret; + +#if (EXCLUSIVE_ACCESS == 0) + __disable_irq(); + + if (semaphore->tokens != 0U) { + semaphore->tokens--; + ret = 1U; + } else { + ret = 0U; + } + + if (primask == 0U) { + __enable_irq(); + } +#else + if (atomic_dec16_nz(&semaphore->tokens) != 0U) { + ret = 1U; + } else { + ret = 0U; + } +#endif + + return ret; +} + +/// Increment Semaphore tokens. +/// \param[in] semaphore semaphore object. +/// \return 1 - success, 0 - failure. +static uint32_t SemaphoreTokenIncrement (os_semaphore_t *semaphore) { +#if (EXCLUSIVE_ACCESS == 0) + uint32_t primask = __get_PRIMASK(); +#endif + uint32_t ret; + +#if (EXCLUSIVE_ACCESS == 0) + __disable_irq(); + + if (semaphore->tokens < semaphore->max_tokens) { + semaphore->tokens++; + ret = 1U; + } else { + ret = 0U; + } + + if (primask == 0U) { + __enable_irq(); + } +#else + if (atomic_inc16_lt(&semaphore->tokens, semaphore->max_tokens) < semaphore->max_tokens) { + ret = 1U; + } else { + ret = 0U; + } +#endif + + return ret; +} + + +// ==== Post ISR processing ==== + +/// Semaphore post ISR processing. +/// \param[in] semaphore semaphore object. +static void osRtxSemaphorePostProcess (os_semaphore_t *semaphore) { + os_thread_t *thread; + + // Check if Thread is waiting for a token + if (semaphore->thread_list != NULL) { + // Try to acquire token + if (SemaphoreTokenDecrement(semaphore) != 0U) { + // Wakeup waiting Thread with highest Priority + thread = osRtxThreadListGet(osRtxObject(semaphore)); + osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE); + EvrRtxSemaphoreAcquired(semaphore, semaphore->tokens); + } + } +} + + +// ==== Service Calls ==== + +/// Create and Initialize a Semaphore object. +/// \note API identical to osSemaphoreNew +static osSemaphoreId_t svcRtxSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) { + os_semaphore_t *semaphore; + uint8_t flags; + const char *name; + + // Check parameters + if ((max_count == 0U) || (max_count > osRtxSemaphoreTokenLimit) || (initial_count > max_count)) { + EvrRtxSemaphoreError(NULL, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + + // Process attributes + if (attr != NULL) { + name = attr->name; + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6] + semaphore = attr->cb_mem; + if (semaphore != NULL) { + //lint -e(923) -e(9078) "cast from pointer to unsigned int" [MISRA Note 7] + if ((((uint32_t)semaphore & 3U) != 0U) || (attr->cb_size < sizeof(os_semaphore_t))) { + EvrRtxSemaphoreError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + } else { + if (attr->cb_size != 0U) { + EvrRtxSemaphoreError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + } + } else { + name = NULL; + semaphore = NULL; + } + + // Allocate object memory if not provided + if (semaphore == NULL) { + if (osRtxInfo.mpi.semaphore != NULL) { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + semaphore = osRtxMemoryPoolAlloc(osRtxInfo.mpi.semaphore); + } else { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + semaphore = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_semaphore_t), 1U); + } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + if (semaphore != NULL) { + uint32_t used; + osRtxSemaphoreMemUsage.cnt_alloc++; + used = osRtxSemaphoreMemUsage.cnt_alloc - osRtxSemaphoreMemUsage.cnt_free; + if (osRtxSemaphoreMemUsage.max_used < used) { + osRtxSemaphoreMemUsage.max_used = used; + } + } +#endif + flags = osRtxFlagSystemObject; + } else { + flags = 0U; + } + + if (semaphore != NULL) { + // Initialize control block + semaphore->id = osRtxIdSemaphore; + semaphore->flags = flags; + semaphore->name = name; + semaphore->thread_list = NULL; + semaphore->tokens = (uint16_t)initial_count; + semaphore->max_tokens = (uint16_t)max_count; + + // Register post ISR processing function + osRtxInfo.post_process.semaphore = osRtxSemaphorePostProcess; + + EvrRtxSemaphoreCreated(semaphore, semaphore->name); + } else { + EvrRtxSemaphoreError(NULL,(int32_t)osErrorNoMemory); + } + + return semaphore; +} + +/// Get name of a Semaphore object. +/// \note API identical to osSemaphoreGetName +static const char *svcRtxSemaphoreGetName (osSemaphoreId_t semaphore_id) { + os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id); + + // Check parameters + if ((semaphore == NULL) || (semaphore->id != osRtxIdSemaphore)) { + EvrRtxSemaphoreGetName(semaphore, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + + EvrRtxSemaphoreGetName(semaphore, semaphore->name); + + return semaphore->name; +} + +/// Acquire a Semaphore token or timeout if no tokens are available. +/// \note API identical to osSemaphoreAcquire +static osStatus_t svcRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) { + os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id); + osStatus_t status; + + // Check parameters + if ((semaphore == NULL) || (semaphore->id != osRtxIdSemaphore)) { + EvrRtxSemaphoreError(semaphore, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Try to acquire token + if (SemaphoreTokenDecrement(semaphore) != 0U) { + EvrRtxSemaphoreAcquired(semaphore, semaphore->tokens); + status = osOK; + } else { + // No token available + if (timeout != 0U) { + EvrRtxSemaphoreAcquirePending(semaphore, timeout); + // Suspend current Thread + if (osRtxThreadWaitEnter(osRtxThreadWaitingSemaphore, timeout)) { + osRtxThreadListPut(osRtxObject(semaphore), osRtxThreadGetRunning()); + } else { + EvrRtxSemaphoreAcquireTimeout(semaphore); + } + status = osErrorTimeout; + } else { + EvrRtxSemaphoreNotAcquired(semaphore); + status = osErrorResource; + } + } + + return status; +} + +/// Release a Semaphore token that was acquired by osSemaphoreAcquire. +/// \note API identical to osSemaphoreRelease +static osStatus_t svcRtxSemaphoreRelease (osSemaphoreId_t semaphore_id) { + os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id); + os_thread_t *thread; + osStatus_t status; + + // Check parameters + if ((semaphore == NULL) || (semaphore->id != osRtxIdSemaphore)) { + EvrRtxSemaphoreError(semaphore, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Check if Thread is waiting for a token + if (semaphore->thread_list != NULL) { + EvrRtxSemaphoreReleased(semaphore, semaphore->tokens); + // Wakeup waiting Thread with highest Priority + thread = osRtxThreadListGet(osRtxObject(semaphore)); + osRtxThreadWaitExit(thread, (uint32_t)osOK, TRUE); + EvrRtxSemaphoreAcquired(semaphore, semaphore->tokens); + status = osOK; + } else { + // Try to release token + if (SemaphoreTokenIncrement(semaphore) != 0U) { + EvrRtxSemaphoreReleased(semaphore, semaphore->tokens); + status = osOK; + } else { + EvrRtxSemaphoreError(semaphore, osRtxErrorSemaphoreCountLimit); + status = osErrorResource; + } + } + + return status; +} + +/// Get current Semaphore token count. +/// \note API identical to osSemaphoreGetCount +static uint32_t svcRtxSemaphoreGetCount (osSemaphoreId_t semaphore_id) { + os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id); + + // Check parameters + if ((semaphore == NULL) || (semaphore->id != osRtxIdSemaphore)) { + EvrRtxSemaphoreGetCount(semaphore, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return 0U; + } + + EvrRtxSemaphoreGetCount(semaphore, semaphore->tokens); + + return semaphore->tokens; +} + +/// Delete a Semaphore object. +/// \note API identical to osSemaphoreDelete +static osStatus_t svcRtxSemaphoreDelete (osSemaphoreId_t semaphore_id) { + os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id); + os_thread_t *thread; + + // Check parameters + if ((semaphore == NULL) || (semaphore->id != osRtxIdSemaphore)) { + EvrRtxSemaphoreError(semaphore, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Unblock waiting threads + if (semaphore->thread_list != NULL) { + do { + thread = osRtxThreadListGet(osRtxObject(semaphore)); + osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE); + } while (semaphore->thread_list != NULL); + osRtxThreadDispatch(NULL); + } + + // Mark object as invalid + semaphore->id = osRtxIdInvalid; + + // Free object memory + if ((semaphore->flags & osRtxFlagSystemObject) != 0U) { + if (osRtxInfo.mpi.semaphore != NULL) { + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.semaphore, semaphore); + } else { + (void)osRtxMemoryFree(osRtxInfo.mem.common, semaphore); + } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxSemaphoreMemUsage.cnt_free++; +#endif + } + + EvrRtxSemaphoreDestroyed(semaphore); + + return osOK; +} + +// Service Calls definitions +//lint ++flb "Library Begin" [MISRA Note 11] +SVC0_3(SemaphoreNew, osSemaphoreId_t, uint32_t, uint32_t, const osSemaphoreAttr_t *) +SVC0_1(SemaphoreGetName, const char *, osSemaphoreId_t) +SVC0_2(SemaphoreAcquire, osStatus_t, osSemaphoreId_t, uint32_t) +SVC0_1(SemaphoreRelease, osStatus_t, osSemaphoreId_t) +SVC0_1(SemaphoreGetCount, uint32_t, osSemaphoreId_t) +SVC0_1(SemaphoreDelete, osStatus_t, osSemaphoreId_t) +//lint --flb "Library End" + + +// ==== ISR Calls ==== + +/// Acquire a Semaphore token or timeout if no tokens are available. +/// \note API identical to osSemaphoreAcquire +__STATIC_INLINE +osStatus_t isrRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) { + os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id); + osStatus_t status; + + // Check parameters + if ((semaphore == NULL) || (semaphore->id != osRtxIdSemaphore) || (timeout != 0U)) { + EvrRtxSemaphoreError(semaphore, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Try to acquire token + if (SemaphoreTokenDecrement(semaphore) != 0U) { + EvrRtxSemaphoreAcquired(semaphore, semaphore->tokens); + status = osOK; + } else { + // No token available + EvrRtxSemaphoreNotAcquired(semaphore); + status = osErrorResource; + } + + return status; +} + +/// Release a Semaphore token that was acquired by osSemaphoreAcquire. +/// \note API identical to osSemaphoreRelease +__STATIC_INLINE +osStatus_t isrRtxSemaphoreRelease (osSemaphoreId_t semaphore_id) { + os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id); + osStatus_t status; + + // Check parameters + if ((semaphore == NULL) || (semaphore->id != osRtxIdSemaphore)) { + EvrRtxSemaphoreError(semaphore, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Try to release token + if (SemaphoreTokenIncrement(semaphore) != 0U) { + // Register post ISR processing + osRtxPostProcess(osRtxObject(semaphore)); + EvrRtxSemaphoreReleased(semaphore, semaphore->tokens); + status = osOK; + } else { + EvrRtxSemaphoreError(semaphore, osRtxErrorSemaphoreCountLimit); + status = osErrorResource; + } + + return status; +} + + +// ==== Public API ==== + +/// Create and Initialize a Semaphore object. +osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) { + osSemaphoreId_t semaphore_id; + + EvrRtxSemaphoreNew(max_count, initial_count, attr); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxSemaphoreError(NULL, (int32_t)osErrorISR); + semaphore_id = NULL; + } else { + semaphore_id = __svcSemaphoreNew(max_count, initial_count, attr); + } + return semaphore_id; +} + +/// Get name of a Semaphore object. +const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id) { + const char *name; + + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxSemaphoreGetName(semaphore_id, NULL); + name = NULL; + } else { + name = __svcSemaphoreGetName(semaphore_id); + } + return name; +} + +/// Acquire a Semaphore token or timeout if no tokens are available. +osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) { + osStatus_t status; + + EvrRtxSemaphoreAcquire(semaphore_id, timeout); + if (IsIrqMode() || IsIrqMasked()) { + status = isrRtxSemaphoreAcquire(semaphore_id, timeout); + } else { + status = __svcSemaphoreAcquire(semaphore_id, timeout); + } + return status; +} + +/// Release a Semaphore token that was acquired by osSemaphoreAcquire. +osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id) { + osStatus_t status; + + EvrRtxSemaphoreRelease(semaphore_id); + if (IsIrqMode() || IsIrqMasked()) { + status = isrRtxSemaphoreRelease(semaphore_id); + } else { + status = __svcSemaphoreRelease(semaphore_id); + } + return status; +} + +/// Get current Semaphore token count. +uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id) { + uint32_t count; + + if (IsIrqMode() || IsIrqMasked()) { + count = svcRtxSemaphoreGetCount(semaphore_id); + } else { + count = __svcSemaphoreGetCount(semaphore_id); + } + return count; +} + +/// Delete a Semaphore object. +osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id) { + osStatus_t status; + + EvrRtxSemaphoreDelete(semaphore_id); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxSemaphoreError(semaphore_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcSemaphoreDelete(semaphore_id); + } + return status; +} diff --git a/source/rtos2/RTX/Source/rtx_system.c b/source/rtos2/RTX/Source/rtx_system.c new file mode 100644 index 000000000..a0583495c --- /dev/null +++ b/source/rtos2/RTX/Source/rtx_system.c @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2013-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: System functions + * + * ----------------------------------------------------------------------------- + */ + +#include "rtx_lib.h" + + +// ==== Helper functions ==== + +/// Put Object into ISR Queue. +/// \param[in] object object. +/// \return 1 - success, 0 - failure. +static uint32_t isr_queue_put (os_object_t *object) { +#if (EXCLUSIVE_ACCESS == 0) + uint32_t primask = __get_PRIMASK(); +#else + uint32_t n; +#endif + uint16_t max; + uint32_t ret; + + max = osRtxInfo.isr_queue.max; + +#if (EXCLUSIVE_ACCESS == 0) + __disable_irq(); + + if (osRtxInfo.isr_queue.cnt < max) { + osRtxInfo.isr_queue.cnt++; + osRtxInfo.isr_queue.data[osRtxInfo.isr_queue.in] = object; + if (++osRtxInfo.isr_queue.in == max) { + osRtxInfo.isr_queue.in = 0U; + } + ret = 1U; + } else { + ret = 0U; + } + + if (primask == 0U) { + __enable_irq(); + } +#else + if (atomic_inc16_lt(&osRtxInfo.isr_queue.cnt, max) < max) { + n = atomic_inc16_lim(&osRtxInfo.isr_queue.in, max); + osRtxInfo.isr_queue.data[n] = object; + ret = 1U; + } else { + ret = 0U; + } +#endif + + return ret; +} + +/// Get Object from ISR Queue. +/// \return object or NULL. +static os_object_t *isr_queue_get (void) { +#if (EXCLUSIVE_ACCESS != 0) + uint32_t n; +#endif + uint16_t max; + os_object_t *ret; + + max = osRtxInfo.isr_queue.max; + +#if (EXCLUSIVE_ACCESS == 0) + __disable_irq(); + + if (osRtxInfo.isr_queue.cnt != 0U) { + osRtxInfo.isr_queue.cnt--; + ret = osRtxObject(osRtxInfo.isr_queue.data[osRtxInfo.isr_queue.out]); + if (++osRtxInfo.isr_queue.out == max) { + osRtxInfo.isr_queue.out = 0U; + } + } else { + ret = NULL; + } + + __enable_irq(); +#else + if (atomic_dec16_nz(&osRtxInfo.isr_queue.cnt) != 0U) { + n = atomic_inc16_lim(&osRtxInfo.isr_queue.out, max); + ret = osRtxObject(osRtxInfo.isr_queue.data[n]); + } else { + ret = NULL; + } +#endif + + return ret; +} + + +// ==== Library Functions ==== + +/// Tick Handler. +//lint -esym(714,osRtxTick_Handler) "Referenced by Exception handlers" +//lint -esym(759,osRtxTick_Handler) "Prototype in header" +//lint -esym(765,osRtxTick_Handler) "Global scope" +void osRtxTick_Handler (void) { + os_thread_t *thread; + + OS_Tick_AcknowledgeIRQ(); + osRtxInfo.kernel.tick++; + + // Process Timers + if (osRtxInfo.timer.tick != NULL) { + osRtxInfo.timer.tick(); + } + + // Process Thread Delays + osRtxThreadDelayTick(); + + osRtxThreadDispatch(NULL); + + // Check Round Robin timeout + if (osRtxInfo.thread.robin.timeout != 0U) { + if (osRtxInfo.thread.robin.thread != osRtxInfo.thread.run.next) { + // Reset Round Robin + osRtxInfo.thread.robin.thread = osRtxInfo.thread.run.next; + osRtxInfo.thread.robin.tick = osRtxInfo.thread.robin.timeout; + } else { + if (osRtxInfo.thread.robin.tick != 0U) { + osRtxInfo.thread.robin.tick--; + } + if (osRtxInfo.thread.robin.tick == 0U) { + // Round Robin Timeout + if (osRtxKernelGetState() == osRtxKernelRunning) { + thread = osRtxInfo.thread.ready.thread_list; + if ((thread != NULL) && (thread->priority == osRtxInfo.thread.robin.thread->priority)) { + osRtxThreadListRemove(thread); + osRtxThreadReadyPut(osRtxInfo.thread.robin.thread); + EvrRtxThreadPreempted(osRtxInfo.thread.robin.thread); + osRtxThreadSwitch(thread); + osRtxInfo.thread.robin.thread = thread; + osRtxInfo.thread.robin.tick = osRtxInfo.thread.robin.timeout; + } + } + } + } + } +} + +/// Pending Service Call Handler. +//lint -esym(714,osRtxPendSV_Handler) "Referenced by Exception handlers" +//lint -esym(759,osRtxPendSV_Handler) "Prototype in header" +//lint -esym(765,osRtxPendSV_Handler) "Global scope" +void osRtxPendSV_Handler (void) { + os_object_t *object; + + for (;;) { + object = isr_queue_get(); + if (object == NULL) { + break; + } + switch (object->id) { + case osRtxIdThread: + osRtxInfo.post_process.thread(osRtxThreadObject(object)); + break; + case osRtxIdEventFlags: + osRtxInfo.post_process.event_flags(osRtxEventFlagsObject(object)); + break; + case osRtxIdSemaphore: + osRtxInfo.post_process.semaphore(osRtxSemaphoreObject(object)); + break; + case osRtxIdMemoryPool: + osRtxInfo.post_process.memory_pool(osRtxMemoryPoolObject(object)); + break; + case osRtxIdMessage: + osRtxInfo.post_process.message(osRtxMessageObject(object)); + break; + default: + // Should never come here + break; + } + } + + osRtxThreadDispatch(NULL); +} + +/// Register post ISR processing. +/// \param[in] object generic object. +void osRtxPostProcess (os_object_t *object) { + + if (isr_queue_put(object) != 0U) { + if (osRtxInfo.kernel.blocked == 0U) { + SetPendSV(); + } else { + osRtxInfo.kernel.pendSV = 1U; + } + } else { + (void)osRtxErrorNotify(osRtxErrorISRQueueOverflow, object); + } +} diff --git a/source/rtos2/RTX/Source/rtx_thread.c b/source/rtos2/RTX/Source/rtx_thread.c new file mode 100644 index 000000000..96a1e3196 --- /dev/null +++ b/source/rtos2/RTX/Source/rtx_thread.c @@ -0,0 +1,1901 @@ +/* + * Copyright (c) 2013-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Thread functions + * + * ----------------------------------------------------------------------------- + */ + +#include "rtx_lib.h" + + +// OS Runtime Object Memory Usage +#if ((defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0))) +osRtxObjectMemUsage_t osRtxThreadMemUsage \ +__attribute__((section(".data.os.thread.obj"))) = +{ 0U, 0U, 0U }; +#endif + + +// ==== Helper functions ==== + +/// Set Thread Flags. +/// \param[in] thread thread object. +/// \param[in] flags specifies the flags to set. +/// \return thread flags after setting. +static uint32_t ThreadFlagsSet (os_thread_t *thread, uint32_t flags) { +#if (EXCLUSIVE_ACCESS == 0) + uint32_t primask = __get_PRIMASK(); +#endif + uint32_t thread_flags; + +#if (EXCLUSIVE_ACCESS == 0) + __disable_irq(); + + thread->thread_flags |= flags; + thread_flags = thread->thread_flags; + + if (primask == 0U) { + __enable_irq(); + } +#else + thread_flags = atomic_set32(&thread->thread_flags, flags); +#endif + + return thread_flags; +} + +/// Clear Thread Flags. +/// \param[in] thread thread object. +/// \param[in] flags specifies the flags to clear. +/// \return thread flags before clearing. +static uint32_t ThreadFlagsClear (os_thread_t *thread, uint32_t flags) { +#if (EXCLUSIVE_ACCESS == 0) + uint32_t primask = __get_PRIMASK(); +#endif + uint32_t thread_flags; + +#if (EXCLUSIVE_ACCESS == 0) + __disable_irq(); + + thread_flags = thread->thread_flags; + thread->thread_flags &= ~flags; + + if (primask == 0U) { + __enable_irq(); + } +#else + thread_flags = atomic_clr32(&thread->thread_flags, flags); +#endif + + return thread_flags; +} + +/// Check Thread Flags. +/// \param[in] thread thread object. +/// \param[in] flags specifies the flags to check. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \return thread flags before clearing or 0 if specified flags have not been set. +static uint32_t ThreadFlagsCheck (os_thread_t *thread, uint32_t flags, uint32_t options) { +#if (EXCLUSIVE_ACCESS == 0) + uint32_t primask; +#endif + uint32_t thread_flags; + + if ((options & osFlagsNoClear) == 0U) { +#if (EXCLUSIVE_ACCESS == 0) + primask = __get_PRIMASK(); + __disable_irq(); + + thread_flags = thread->thread_flags; + if ((((options & osFlagsWaitAll) != 0U) && ((thread_flags & flags) != flags)) || + (((options & osFlagsWaitAll) == 0U) && ((thread_flags & flags) == 0U))) { + thread_flags = 0U; + } else { + thread->thread_flags &= ~flags; + } + + if (primask == 0U) { + __enable_irq(); + } +#else + if ((options & osFlagsWaitAll) != 0U) { + thread_flags = atomic_chk32_all(&thread->thread_flags, flags); + } else { + thread_flags = atomic_chk32_any(&thread->thread_flags, flags); + } +#endif + } else { + thread_flags = thread->thread_flags; + if ((((options & osFlagsWaitAll) != 0U) && ((thread_flags & flags) != flags)) || + (((options & osFlagsWaitAll) == 0U) && ((thread_flags & flags) == 0U))) { + thread_flags = 0U; + } + } + + return thread_flags; +} + + +// ==== Library functions ==== + +/// Put a Thread into specified Object list sorted by Priority (Highest at Head). +/// \param[in] object generic object. +/// \param[in] thread thread object. +void osRtxThreadListPut (os_object_t *object, os_thread_t *thread) { + os_thread_t *prev, *next; + int32_t priority; + + priority = thread->priority; + + prev = osRtxThreadObject(object); + next = prev->thread_next; + while ((next != NULL) && (next->priority >= priority)) { + prev = next; + next = next->thread_next; + } + thread->thread_prev = prev; + thread->thread_next = next; + prev->thread_next = thread; + if (next != NULL) { + next->thread_prev = thread; + } +} + +/// Get a Thread with Highest Priority from specified Object list and remove it. +/// \param[in] object generic object. +/// \return thread object. +os_thread_t *osRtxThreadListGet (os_object_t *object) { + os_thread_t *thread; + + thread = object->thread_list; + object->thread_list = thread->thread_next; + if (thread->thread_next != NULL) { + thread->thread_next->thread_prev = osRtxThreadObject(object); + } + thread->thread_prev = NULL; + + return thread; +} + +/// Retrieve Thread list root object. +/// \param[in] thread thread object. +/// \return root object. +static void *osRtxThreadListRoot (os_thread_t *thread) { + os_thread_t *thread0; + + thread0 = thread; + while (thread0->id == osRtxIdThread) { + thread0 = thread0->thread_prev; + } + return thread0; +} + +/// Re-sort a Thread in linked Object list by Priority (Highest at Head). +/// \param[in] thread thread object. +void osRtxThreadListSort (os_thread_t *thread) { + os_object_t *object; + os_thread_t *thread0; + + // Search for object + thread0 = thread; + while ((thread0 != NULL) && (thread0->id == osRtxIdThread)) { + thread0 = thread0->thread_prev; + } + object = osRtxObject(thread0); + + if (object != NULL) { + osRtxThreadListRemove(thread); + osRtxThreadListPut(object, thread); + } +} + +/// Remove a Thread from linked Object list. +/// \param[in] thread thread object. +void osRtxThreadListRemove (os_thread_t *thread) { + + if (thread->thread_prev != NULL) { + thread->thread_prev->thread_next = thread->thread_next; + if (thread->thread_next != NULL) { + thread->thread_next->thread_prev = thread->thread_prev; + } + thread->thread_prev = NULL; + } +} + +/// Unlink a Thread from specified linked list. +/// \param[in] thread thread object. +static void osRtxThreadListUnlink (os_thread_t **thread_list, os_thread_t *thread) { + + if (thread->thread_next != NULL) { + thread->thread_next->thread_prev = thread->thread_prev; + } + if (thread->thread_prev != NULL) { + thread->thread_prev->thread_next = thread->thread_next; + thread->thread_prev = NULL; + } else { + *thread_list = thread->thread_next; + } +} + +/// Mark a Thread as Ready and put it into Ready list (sorted by Priority). +/// \param[in] thread thread object. +void osRtxThreadReadyPut (os_thread_t *thread) { + + thread->state = osRtxThreadReady; + osRtxThreadListPut(&osRtxInfo.thread.ready, thread); +} + +/// Insert a Thread into the Delay list sorted by Delay (Lowest at Head). +/// \param[in] thread thread object. +/// \param[in] delay delay value. +static void osRtxThreadDelayInsert (os_thread_t *thread, uint32_t delay) { + os_thread_t *prev, *next; + + if (delay == osWaitForever) { + prev = NULL; + next = osRtxInfo.thread.wait_list; + while (next != NULL) { + prev = next; + next = next->delay_next; + } + thread->delay = delay; + thread->delay_prev = prev; + thread->delay_next = NULL; + if (prev != NULL) { + prev->delay_next = thread; + } else { + osRtxInfo.thread.wait_list = thread; + } + } else { + prev = NULL; + next = osRtxInfo.thread.delay_list; + while ((next != NULL) && (next->delay <= delay)) { + delay -= next->delay; + prev = next; + next = next->delay_next; + } + thread->delay = delay; + thread->delay_prev = prev; + thread->delay_next = next; + if (prev != NULL) { + prev->delay_next = thread; + } else { + osRtxInfo.thread.delay_list = thread; + } + if (next != NULL) { + next->delay -= delay; + next->delay_prev = thread; + } + } +} + +/// Remove a Thread from the Delay list. +/// \param[in] thread thread object. +static void osRtxThreadDelayRemove (os_thread_t *thread) { + + if (thread->delay == osWaitForever) { + if (thread->delay_next != NULL) { + thread->delay_next->delay_prev = thread->delay_prev; + } + if (thread->delay_prev != NULL) { + thread->delay_prev->delay_next = thread->delay_next; + thread->delay_prev = NULL; + } else { + osRtxInfo.thread.wait_list = thread->delay_next; + } + } else { + if (thread->delay_next != NULL) { + thread->delay_next->delay += thread->delay; + thread->delay_next->delay_prev = thread->delay_prev; + } + if (thread->delay_prev != NULL) { + thread->delay_prev->delay_next = thread->delay_next; + thread->delay_prev = NULL; + } else { + osRtxInfo.thread.delay_list = thread->delay_next; + } + } +} + +/// Process Thread Delay Tick (executed each System Tick). +void osRtxThreadDelayTick (void) { + os_thread_t *thread; + os_object_t *object; + + thread = osRtxInfo.thread.delay_list; + if (thread == NULL) { + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return; + } + + thread->delay--; + + if (thread->delay == 0U) { + do { + switch (thread->state) { + case osRtxThreadWaitingDelay: + EvrRtxDelayCompleted(thread); + break; + case osRtxThreadWaitingThreadFlags: + EvrRtxThreadFlagsWaitTimeout(thread); + break; + case osRtxThreadWaitingEventFlags: + object = osRtxObject(osRtxThreadListRoot(thread)); + EvrRtxEventFlagsWaitTimeout(osRtxEventFlagsObject(object)); + break; + case osRtxThreadWaitingMutex: + object = osRtxObject(osRtxThreadListRoot(thread)); + osRtxMutexOwnerRestore(osRtxMutexObject(object), thread); + EvrRtxMutexAcquireTimeout(osRtxMutexObject(object)); + break; + case osRtxThreadWaitingSemaphore: + object = osRtxObject(osRtxThreadListRoot(thread)); + EvrRtxSemaphoreAcquireTimeout(osRtxSemaphoreObject(object)); + break; + case osRtxThreadWaitingMemoryPool: + object = osRtxObject(osRtxThreadListRoot(thread)); + EvrRtxMemoryPoolAllocTimeout(osRtxMemoryPoolObject(object)); + break; + case osRtxThreadWaitingMessageGet: + object = osRtxObject(osRtxThreadListRoot(thread)); + EvrRtxMessageQueueGetTimeout(osRtxMessageQueueObject(object)); + break; + case osRtxThreadWaitingMessagePut: + object = osRtxObject(osRtxThreadListRoot(thread)); + EvrRtxMessageQueuePutTimeout(osRtxMessageQueueObject(object)); + break; + default: + // Invalid + break; + } + EvrRtxThreadUnblocked(thread, (osRtxThreadRegPtr(thread))[0]); + osRtxThreadListRemove(thread); + osRtxThreadReadyPut(thread); + thread = thread->delay_next; + } while ((thread != NULL) && (thread->delay == 0U)); + if (thread != NULL) { + thread->delay_prev = NULL; + } + osRtxInfo.thread.delay_list = thread; + } +} + +/// Get pointer to Thread registers (R0..R3) +/// \param[in] thread thread object. +/// \return pointer to registers R0-R3. +uint32_t *osRtxThreadRegPtr (const os_thread_t *thread) { + uint32_t addr = thread->sp + StackOffsetR0(thread->stack_frame); + //lint -e{923} -e{9078} "cast from unsigned int to pointer" + return ((uint32_t *)addr); +} + +/// Block running Thread execution and register it as Ready to Run. +/// \param[in] thread running thread object. +static void osRtxThreadBlock (os_thread_t *thread) { + os_thread_t *prev, *next; + int32_t priority; + + thread->state = osRtxThreadReady; + + priority = thread->priority; + + prev = osRtxThreadObject(&osRtxInfo.thread.ready); + next = prev->thread_next; + + while ((next != NULL) && (next->priority > priority)) { + prev = next; + next = next->thread_next; + } + thread->thread_prev = prev; + thread->thread_next = next; + prev->thread_next = thread; + if (next != NULL) { + next->thread_prev = thread; + } + + EvrRtxThreadPreempted(thread); +} + +/// Switch to specified Thread. +/// \param[in] thread thread object. +void osRtxThreadSwitch (os_thread_t *thread) { + + thread->state = osRtxThreadRunning; + osRtxInfo.thread.run.next = thread; + osRtxThreadStackCheck(); + EvrRtxThreadSwitched(thread); +} + +/// Dispatch specified Thread or Ready Thread with Highest Priority. +/// \param[in] thread thread object or NULL. +void osRtxThreadDispatch (os_thread_t *thread) { + uint8_t kernel_state; + os_thread_t *thread_running; + os_thread_t *thread_ready; + + kernel_state = osRtxKernelGetState(); + thread_running = osRtxThreadGetRunning(); + + if (thread == NULL) { + thread_ready = osRtxInfo.thread.ready.thread_list; + if ((kernel_state == osRtxKernelRunning) && + (thread_ready != NULL) && + (thread_ready->priority > thread_running->priority)) { + // Preempt running Thread + osRtxThreadListRemove(thread_ready); + osRtxThreadBlock(thread_running); + osRtxThreadSwitch(thread_ready); + } + } else { + if ((kernel_state == osRtxKernelRunning) && + (thread->priority > thread_running->priority)) { + // Preempt running Thread + osRtxThreadBlock(thread_running); + osRtxThreadSwitch(thread); + } else { + // Put Thread into Ready list + osRtxThreadReadyPut(thread); + } + } +} + +/// Exit Thread wait state. +/// \param[in] thread thread object. +/// \param[in] ret_val return value. +/// \param[in] dispatch dispatch flag. +void osRtxThreadWaitExit (os_thread_t *thread, uint32_t ret_val, bool_t dispatch) { + uint32_t *reg; + + EvrRtxThreadUnblocked(thread, ret_val); + + reg = osRtxThreadRegPtr(thread); + reg[0] = ret_val; + + osRtxThreadDelayRemove(thread); + if (dispatch) { + osRtxThreadDispatch(thread); + } else { + osRtxThreadReadyPut(thread); + } +} + +/// Enter Thread wait state. +/// \param[in] state new thread state. +/// \param[in] timeout timeout. +/// \return true - success, false - failure. +bool_t osRtxThreadWaitEnter (uint8_t state, uint32_t timeout) { + os_thread_t *thread; + + // Check if Kernel is running + if (osRtxKernelGetState() != osRtxKernelRunning) { + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return FALSE; + } + + // Check if any thread is ready + if (osRtxInfo.thread.ready.thread_list == NULL) { + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return FALSE; + } + + // Get running thread + thread = osRtxThreadGetRunning(); + + EvrRtxThreadBlocked(thread, timeout); + + thread->state = state; + osRtxThreadDelayInsert(thread, timeout); + thread = osRtxThreadListGet(&osRtxInfo.thread.ready); + osRtxThreadSwitch(thread); + + return TRUE; +} + +/// Check current running Thread Stack. +//lint -esym(759,osRtxThreadStackCheck) "Prototype in header" +//lint -esym(765,osRtxThreadStackCheck) "Global scope (can be overridden)" +__WEAK void osRtxThreadStackCheck (void) { + os_thread_t *thread; + + thread = osRtxThreadGetRunning(); + if (thread != NULL) { + //lint -e{923} "cast from pointer to unsigned int" + //lint -e{9079} -e{9087} "cast between pointers to different object types" + if ((thread->sp <= (uint32_t)thread->stack_mem) || + (*((uint32_t *)thread->stack_mem) != osRtxStackMagicWord)) { + (void)osRtxErrorNotify(osRtxErrorStackUnderflow, thread); + } + } +} + +#ifdef RTX_TF_M_EXTENSION +/// Get TrustZone Module Identifier of running Thread. +/// \return TrustZone Module Identifier. +uint32_t osRtxTzGetModuleId (void) { + os_thread_t *thread; + uint32_t tz_module; + + thread = osRtxThreadGetRunning(); + if (thread != NULL) { + tz_module = thread->tz_module; + } else { + tz_module = 0U; + } + + return tz_module; +} +#endif + + +// ==== Post ISR processing ==== + +/// Thread post ISR processing. +/// \param[in] thread thread object. +static void osRtxThreadPostProcess (os_thread_t *thread) { + uint32_t thread_flags; + + // Check if Thread is waiting for Thread Flags + if (thread->state == osRtxThreadWaitingThreadFlags) { + thread_flags = ThreadFlagsCheck(thread, thread->wait_flags, thread->flags_options); + if (thread_flags != 0U) { + osRtxThreadWaitExit(thread, thread_flags, FALSE); + EvrRtxThreadFlagsWaitCompleted(thread->wait_flags, thread->flags_options, thread_flags, thread); + } + } +} + + +// ==== Service Calls ==== + +/// Create a thread and add it to Active Threads. +/// \note API identical to osThreadNew +static osThreadId_t svcRtxThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { + os_thread_t *thread; + uint32_t attr_bits; + void *stack_mem; + uint32_t stack_size; + osPriority_t priority; + uint8_t flags; + const char *name; + uint32_t *ptr; + uint32_t n; +#if (DOMAIN_NS == 1) + TZ_ModuleId_t tz_module; + TZ_MemoryId_t tz_memory; +#endif + + // Check parameters + if (func == NULL) { + EvrRtxThreadError(NULL, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + + // Process attributes + if (attr != NULL) { + name = attr->name; + attr_bits = attr->attr_bits; + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6] + thread = attr->cb_mem; + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6] + stack_mem = attr->stack_mem; + stack_size = attr->stack_size; + priority = attr->priority; +#if (DOMAIN_NS == 1) + tz_module = attr->tz_module; +#endif + if (thread != NULL) { + //lint -e(923) -e(9078) "cast from pointer to unsigned int" [MISRA Note 7] + if ((((uint32_t)thread & 3U) != 0U) || (attr->cb_size < sizeof(os_thread_t))) { + EvrRtxThreadError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + } else { + if (attr->cb_size != 0U) { + EvrRtxThreadError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + } + if (stack_mem != NULL) { + //lint -e(923) -e(9078) "cast from pointer to unsigned int" [MISRA Note 7] + if ((((uint32_t)stack_mem & 7U) != 0U) || (stack_size == 0U)) { + EvrRtxThreadError(NULL, osRtxErrorInvalidThreadStack); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + } + if (priority == osPriorityNone) { + priority = osPriorityNormal; + } else { + if ((priority < osPriorityIdle) || (priority > osPriorityISR)) { + EvrRtxThreadError(NULL, osRtxErrorInvalidPriority); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + } + } else { + name = NULL; + attr_bits = 0U; + thread = NULL; + stack_mem = NULL; + stack_size = 0U; + priority = osPriorityNormal; +#if (DOMAIN_NS == 1) + tz_module = 0U; +#endif + } + + // Check stack size + if ((stack_size != 0U) && (((stack_size & 7U) != 0U) || (stack_size < (64U + 8U)))) { + EvrRtxThreadError(NULL, osRtxErrorInvalidThreadStack); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + + // Allocate object memory if not provided + if (thread == NULL) { + if (osRtxInfo.mpi.thread != NULL) { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + thread = osRtxMemoryPoolAlloc(osRtxInfo.mpi.thread); + } else { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + thread = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_thread_t), 1U); + } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + if (thread != NULL) { + uint32_t used; + osRtxThreadMemUsage.cnt_alloc++; + used = osRtxThreadMemUsage.cnt_alloc - osRtxThreadMemUsage.cnt_free; + if (osRtxThreadMemUsage.max_used < used) { + osRtxThreadMemUsage.max_used = used; + } + } +#endif + flags = osRtxFlagSystemObject; + } else { + flags = 0U; + } + + // Allocate stack memory if not provided + if ((thread != NULL) && (stack_mem == NULL)) { + if (stack_size == 0U) { + stack_size = osRtxConfig.thread_stack_size; + if (osRtxInfo.mpi.stack != NULL) { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + stack_mem = osRtxMemoryPoolAlloc(osRtxInfo.mpi.stack); + if (stack_mem != NULL) { + flags |= osRtxThreadFlagDefStack; + } + } else { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + stack_mem = osRtxMemoryAlloc(osRtxInfo.mem.stack, stack_size, 0U); + } + } else { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + stack_mem = osRtxMemoryAlloc(osRtxInfo.mem.stack, stack_size, 0U); + } + if (stack_mem == NULL) { + if ((flags & osRtxFlagSystemObject) != 0U) { + if (osRtxInfo.mpi.thread != NULL) { + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread); + } else { + (void)osRtxMemoryFree(osRtxInfo.mem.common, thread); + } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxThreadMemUsage.cnt_free++; +#endif + } + thread = NULL; + } + flags |= osRtxFlagSystemMemory; + } + +#if (DOMAIN_NS == 1) + // Allocate secure process stack + if ((thread != NULL) && (tz_module != 0U)) { + tz_memory = TZ_AllocModuleContext_S(tz_module); + if (tz_memory == 0U) { + EvrRtxThreadError(NULL, osRtxErrorTZ_AllocContext_S); + if ((flags & osRtxFlagSystemMemory) != 0U) { + if ((flags & osRtxThreadFlagDefStack) != 0U) { + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.stack, thread->stack_mem); + } else { + (void)osRtxMemoryFree(osRtxInfo.mem.stack, thread->stack_mem); + } + } + if ((flags & osRtxFlagSystemObject) != 0U) { + if (osRtxInfo.mpi.thread != NULL) { + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread); + } else { + (void)osRtxMemoryFree(osRtxInfo.mem.common, thread); + } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxThreadMemUsage.cnt_free++; +#endif + } + thread = NULL; + } + } else { + tz_memory = 0U; + } +#endif + + if (thread != NULL) { + // Initialize control block + //lint --e{923} --e{9078} "cast between pointers and unsigned int" + //lint --e{9079} --e{9087} "cast between pointers to different object types" + //lint --e{9074} "conversion between a pointer to function and another type" + thread->id = osRtxIdThread; + thread->state = osRtxThreadReady; + thread->flags = flags; + thread->attr = (uint8_t)attr_bits; + thread->name = name; + thread->thread_next = NULL; + thread->thread_prev = NULL; + thread->delay_next = NULL; + thread->delay_prev = NULL; + thread->thread_join = NULL; + thread->delay = 0U; + thread->priority = (int8_t)priority; + thread->priority_base = (int8_t)priority; + thread->stack_frame = STACK_FRAME_INIT_VAL; + thread->flags_options = 0U; + thread->wait_flags = 0U; + thread->thread_flags = 0U; + thread->mutex_list = NULL; + thread->stack_mem = stack_mem; + thread->stack_size = stack_size; + thread->sp = (uint32_t)stack_mem + stack_size - 64U; + thread->thread_addr = (uint32_t)func; + #if (DOMAIN_NS == 1) + thread->tz_memory = tz_memory; + #ifdef RTX_TF_M_EXTENSION + thread->tz_module = tz_module; + #endif + #endif + + // Initialize stack + //lint --e{613} false detection: "Possible use of null pointer" + ptr = (uint32_t *)stack_mem; + ptr[0] = osRtxStackMagicWord; + if ((osRtxConfig.flags & osRtxConfigStackWatermark) != 0U) { + for (n = (stack_size/4U) - (16U + 1U); n != 0U; n--) { + ptr++; + *ptr = osRtxStackFillPattern; + } + } + ptr = (uint32_t *)thread->sp; + for (n = 0U; n != 13U; n++) { + ptr[n] = 0U; // R4..R11, R0..R3, R12 + } + ptr[13] = (uint32_t)osThreadExit; // LR + ptr[14] = (uint32_t)func; // PC + ptr[15] = xPSR_InitVal( + (bool_t)((osRtxConfig.flags & osRtxConfigPrivilegedMode) != 0U), + (bool_t)(((uint32_t)func & 1U) != 0U) + ); // xPSR + ptr[8] = (uint32_t)argument; // R0 + + // Register post ISR processing function + osRtxInfo.post_process.thread = osRtxThreadPostProcess; + + EvrRtxThreadCreated(thread, thread->thread_addr, thread->name); + } else { + EvrRtxThreadError(NULL, (int32_t)osErrorNoMemory); + } + + if (thread != NULL) { + osRtxThreadDispatch(thread); + } + + return thread; +} + +/// Get name of a thread. +/// \note API identical to osThreadGetName +static const char *svcRtxThreadGetName (osThreadId_t thread_id) { + os_thread_t *thread = osRtxThreadId(thread_id); + + // Check parameters + if ((thread == NULL) || (thread->id != osRtxIdThread)) { + EvrRtxThreadGetName(thread, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + + EvrRtxThreadGetName(thread, thread->name); + + return thread->name; +} + +/// Return the thread ID of the current running thread. +/// \note API identical to osThreadGetId +static osThreadId_t svcRtxThreadGetId (void) { + os_thread_t *thread; + + thread = osRtxThreadGetRunning(); + EvrRtxThreadGetId(thread); + return thread; +} + +/// Get current thread state of a thread. +/// \note API identical to osThreadGetState +static osThreadState_t svcRtxThreadGetState (osThreadId_t thread_id) { + os_thread_t *thread = osRtxThreadId(thread_id); + osThreadState_t state; + + // Check parameters + if ((thread == NULL) || (thread->id != osRtxIdThread)) { + EvrRtxThreadGetState(thread, osThreadError); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osThreadError; + } + + state = osRtxThreadState(thread); + + EvrRtxThreadGetState(thread, state); + + return state; +} + +/// Get stack size of a thread. +/// \note API identical to osThreadGetStackSize +static uint32_t svcRtxThreadGetStackSize (osThreadId_t thread_id) { + os_thread_t *thread = osRtxThreadId(thread_id); + + // Check parameters + if ((thread == NULL) || (thread->id != osRtxIdThread)) { + EvrRtxThreadGetStackSize(thread, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return 0U; + } + + EvrRtxThreadGetStackSize(thread, thread->stack_size); + + return thread->stack_size; +} + +/// Get available stack space of a thread based on stack watermark recording during execution. +/// \note API identical to osThreadGetStackSpace +static uint32_t svcRtxThreadGetStackSpace (osThreadId_t thread_id) { + os_thread_t *thread = osRtxThreadId(thread_id); + const uint32_t *stack; + uint32_t space; + + // Check parameters + if ((thread == NULL) || (thread->id != osRtxIdThread)) { + EvrRtxThreadGetStackSpace(thread, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return 0U; + } + + // Check if stack watermark is not enabled + if ((osRtxConfig.flags & osRtxConfigStackWatermark) == 0U) { + EvrRtxThreadGetStackSpace(thread, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return 0U; + } + + //lint -e{9079} "conversion from pointer to void to pointer to other type" + stack = thread->stack_mem; + if (*stack++ == osRtxStackMagicWord) { + for (space = 4U; space < thread->stack_size; space += 4U) { + if (*stack++ != osRtxStackFillPattern) { + break; + } + } + } else { + space = 0U; + } + + EvrRtxThreadGetStackSpace(thread, space); + + return space; +} + +/// Change priority of a thread. +/// \note API identical to osThreadSetPriority +static osStatus_t svcRtxThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) { + os_thread_t *thread = osRtxThreadId(thread_id); + + // Check parameters + if ((thread == NULL) || (thread->id != osRtxIdThread) || + (priority < osPriorityIdle) || (priority > osPriorityISR)) { + EvrRtxThreadError(thread, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Check object state + if (thread->state == osRtxThreadTerminated) { + EvrRtxThreadError(thread, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorResource; + } + + if (thread->priority != (int8_t)priority) { + thread->priority = (int8_t)priority; + thread->priority_base = (int8_t)priority; + EvrRtxThreadPriorityUpdated(thread, priority); + osRtxThreadListSort(thread); + osRtxThreadDispatch(NULL); + } + + return osOK; +} + +/// Get current priority of a thread. +/// \note API identical to osThreadGetPriority +static osPriority_t svcRtxThreadGetPriority (osThreadId_t thread_id) { + os_thread_t *thread = osRtxThreadId(thread_id); + osPriority_t priority; + + // Check parameters + if ((thread == NULL) || (thread->id != osRtxIdThread)) { + EvrRtxThreadGetPriority(thread, osPriorityError); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osPriorityError; + } + + // Check object state + if (thread->state == osRtxThreadTerminated) { + EvrRtxThreadGetPriority(thread, osPriorityError); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osPriorityError; + } + + priority = osRtxThreadPriority(thread); + + EvrRtxThreadGetPriority(thread, priority); + + return priority; +} + +/// Pass control to next thread that is in state READY. +/// \note API identical to osThreadYield +static osStatus_t svcRtxThreadYield (void) { + os_thread_t *thread_running; + os_thread_t *thread_ready; + + if (osRtxKernelGetState() == osRtxKernelRunning) { + thread_running = osRtxThreadGetRunning(); + thread_ready = osRtxInfo.thread.ready.thread_list; + if ((thread_ready != NULL) && + (thread_ready->priority == thread_running->priority)) { + osRtxThreadListRemove(thread_ready); + osRtxThreadReadyPut(thread_running); + EvrRtxThreadPreempted(thread_running); + osRtxThreadSwitch(thread_ready); + } + } + + return osOK; +} + +/// Suspend execution of a thread. +/// \note API identical to osThreadSuspend +static osStatus_t svcRtxThreadSuspend (osThreadId_t thread_id) { + os_thread_t *thread = osRtxThreadId(thread_id); + osStatus_t status; + + // Check parameters + if ((thread == NULL) || (thread->id != osRtxIdThread)) { + EvrRtxThreadError(thread, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Check object state + switch (thread->state & osRtxThreadStateMask) { + case osRtxThreadRunning: + if ((osRtxKernelGetState() != osRtxKernelRunning) || + (osRtxInfo.thread.ready.thread_list == NULL)) { + EvrRtxThreadError(thread, (int32_t)osErrorResource); + status = osErrorResource; + } else { + status = osOK; + } + break; + case osRtxThreadReady: + osRtxThreadListRemove(thread); + status = osOK; + break; + case osRtxThreadBlocked: + osRtxThreadListRemove(thread); + osRtxThreadDelayRemove(thread); + status = osOK; + break; + case osRtxThreadInactive: + case osRtxThreadTerminated: + default: + EvrRtxThreadError(thread, (int32_t)osErrorResource); + status = osErrorResource; + break; + } + + if (status == osOK) { + EvrRtxThreadSuspended(thread); + + if (thread->state == osRtxThreadRunning) { + osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready)); + } + + // Update Thread State and put it into Delay list + thread->state = osRtxThreadBlocked; + thread->thread_prev = NULL; + thread->thread_next = NULL; + osRtxThreadDelayInsert(thread, osWaitForever); + } + + return status; +} + +/// Resume execution of a thread. +/// \note API identical to osThreadResume +static osStatus_t svcRtxThreadResume (osThreadId_t thread_id) { + os_thread_t *thread = osRtxThreadId(thread_id); + + // Check parameters + if ((thread == NULL) || (thread->id != osRtxIdThread)) { + EvrRtxThreadError(thread, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Check object state + if ((thread->state & osRtxThreadStateMask) != osRtxThreadBlocked) { + EvrRtxThreadError(thread, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorResource; + } + + EvrRtxThreadResumed(thread); + + // Wakeup Thread + osRtxThreadListRemove(thread); + osRtxThreadDelayRemove(thread); + osRtxThreadDispatch(thread); + + return osOK; +} + +/// Free Thread resources. +/// \param[in] thread thread object. +static void osRtxThreadFree (os_thread_t *thread) { + + // Mark object as inactive and invalid + thread->state = osRtxThreadInactive; + thread->id = osRtxIdInvalid; + +#if (DOMAIN_NS == 1) + // Free secure process stack + if (thread->tz_memory != 0U) { + (void)TZ_FreeModuleContext_S(thread->tz_memory); + } +#endif + + // Free stack memory + if ((thread->flags & osRtxFlagSystemMemory) != 0U) { + if ((thread->flags & osRtxThreadFlagDefStack) != 0U) { + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.stack, thread->stack_mem); + } else { + (void)osRtxMemoryFree(osRtxInfo.mem.stack, thread->stack_mem); + } + } + + // Free object memory + if ((thread->flags & osRtxFlagSystemObject) != 0U) { + if (osRtxInfo.mpi.thread != NULL) { + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread); + } else { + (void)osRtxMemoryFree(osRtxInfo.mem.common, thread); + } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxThreadMemUsage.cnt_free++; +#endif + } +} + +/// Detach a thread (thread storage can be reclaimed when thread terminates). +/// \note API identical to osThreadDetach +static osStatus_t svcRtxThreadDetach (osThreadId_t thread_id) { + os_thread_t *thread = osRtxThreadId(thread_id); + + // Check parameters + if ((thread == NULL) || (thread->id != osRtxIdThread)) { + EvrRtxThreadError(thread, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Check object attributes + if ((thread->attr & osThreadJoinable) == 0U) { + EvrRtxThreadError(thread, osRtxErrorThreadNotJoinable); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorResource; + } + + if (thread->state == osRtxThreadTerminated) { + osRtxThreadListUnlink(&osRtxInfo.thread.terminate_list, thread); + osRtxThreadFree(thread); + } else { + thread->attr &= ~osThreadJoinable; + } + + EvrRtxThreadDetached(thread); + + return osOK; +} + +/// Wait for specified thread to terminate. +/// \note API identical to osThreadJoin +static osStatus_t svcRtxThreadJoin (osThreadId_t thread_id) { + os_thread_t *thread = osRtxThreadId(thread_id); + osStatus_t status; + + // Check parameters + if ((thread == NULL) || (thread->id != osRtxIdThread)) { + EvrRtxThreadError(thread, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Check object attributes + if ((thread->attr & osThreadJoinable) == 0U) { + EvrRtxThreadError(thread, osRtxErrorThreadNotJoinable); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorResource; + } + + // Check object state + if (thread->state == osRtxThreadRunning) { + EvrRtxThreadError(thread, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorResource; + } + + if (thread->state == osRtxThreadTerminated) { + osRtxThreadListUnlink(&osRtxInfo.thread.terminate_list, thread); + osRtxThreadFree(thread); + EvrRtxThreadJoined(thread); + status = osOK; + } else { + // Suspend current Thread + if (osRtxThreadWaitEnter(osRtxThreadWaitingJoin, osWaitForever)) { + thread->thread_join = osRtxThreadGetRunning(); + thread->attr &= ~osThreadJoinable; + EvrRtxThreadJoinPending(thread); + } else { + EvrRtxThreadError(thread, (int32_t)osErrorResource); + } + status = osErrorResource; + } + + return status; +} + +/// Terminate execution of current running thread. +/// \note API identical to osThreadExit +static void svcRtxThreadExit (void) { + os_thread_t *thread; + + // Check if switch to next Ready Thread is possible + if ((osRtxKernelGetState() != osRtxKernelRunning) || + (osRtxInfo.thread.ready.thread_list == NULL)) { + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return; + } + + // Get running thread + thread = osRtxThreadGetRunning(); + + // Release owned Mutexes + osRtxMutexOwnerRelease(thread->mutex_list); + + // Wakeup Thread waiting to Join + if (thread->thread_join != NULL) { + osRtxThreadWaitExit(thread->thread_join, (uint32_t)osOK, FALSE); + EvrRtxThreadJoined(thread->thread_join); + } + + // Switch to next Ready Thread + thread->sp = __get_PSP(); + osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready)); + osRtxThreadSetRunning(NULL); + + if ((thread->attr & osThreadJoinable) == 0U) { + osRtxThreadFree(thread); + } else { + // Update Thread State and put it into Terminate Thread list + thread->state = osRtxThreadTerminated; + thread->thread_prev = NULL; + thread->thread_next = osRtxInfo.thread.terminate_list; + if (osRtxInfo.thread.terminate_list != NULL) { + osRtxInfo.thread.terminate_list->thread_prev = thread; + } + osRtxInfo.thread.terminate_list = thread; + } + + EvrRtxThreadDestroyed(thread); +} + +/// Terminate execution of a thread. +/// \note API identical to osThreadTerminate +static osStatus_t svcRtxThreadTerminate (osThreadId_t thread_id) { + os_thread_t *thread = osRtxThreadId(thread_id); + osStatus_t status; + + // Check parameters + if ((thread == NULL) || (thread->id != osRtxIdThread)) { + EvrRtxThreadError(thread, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Check object state + switch (thread->state & osRtxThreadStateMask) { + case osRtxThreadRunning: + if ((osRtxKernelGetState() != osRtxKernelRunning) || + (osRtxInfo.thread.ready.thread_list == NULL)) { + EvrRtxThreadError(thread, (int32_t)osErrorResource); + status = osErrorResource; + } else { + status = osOK; + } + break; + case osRtxThreadReady: + osRtxThreadListRemove(thread); + status = osOK; + break; + case osRtxThreadBlocked: + osRtxThreadListRemove(thread); + osRtxThreadDelayRemove(thread); + status = osOK; + break; + case osRtxThreadInactive: + case osRtxThreadTerminated: + default: + EvrRtxThreadError(thread, (int32_t)osErrorResource); + status = osErrorResource; + break; + } + + if (status == osOK) { + // Release owned Mutexes + osRtxMutexOwnerRelease(thread->mutex_list); + + // Wakeup Thread waiting to Join + if (thread->thread_join != NULL) { + osRtxThreadWaitExit(thread->thread_join, (uint32_t)osOK, FALSE); + EvrRtxThreadJoined(thread->thread_join); + } + + // Switch to next Ready Thread when terminating running Thread + if (thread->state == osRtxThreadRunning) { + thread->sp = __get_PSP(); + osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready)); + osRtxThreadSetRunning(NULL); + } else { + osRtxThreadDispatch(NULL); + } + + if ((thread->attr & osThreadJoinable) == 0U) { + osRtxThreadFree(thread); + } else { + // Update Thread State and put it into Terminate Thread list + thread->state = osRtxThreadTerminated; + thread->thread_prev = NULL; + thread->thread_next = osRtxInfo.thread.terminate_list; + if (osRtxInfo.thread.terminate_list != NULL) { + osRtxInfo.thread.terminate_list->thread_prev = thread; + } + osRtxInfo.thread.terminate_list = thread; + } + + EvrRtxThreadDestroyed(thread); + } + + return status; +} + +/// Get number of active threads. +/// \note API identical to osThreadGetCount +static uint32_t svcRtxThreadGetCount (void) { + const os_thread_t *thread; + uint32_t count; + + // Running Thread + count = 1U; + + // Ready List + for (thread = osRtxInfo.thread.ready.thread_list; + thread != NULL; thread = thread->thread_next) { + count++; + } + + // Delay List + for (thread = osRtxInfo.thread.delay_list; + thread != NULL; thread = thread->delay_next) { + count++; + } + + // Wait List + for (thread = osRtxInfo.thread.wait_list; + thread != NULL; thread = thread->delay_next) { + count++; + } + + EvrRtxThreadGetCount(count); + + return count; +} + +/// Enumerate active threads. +/// \note API identical to osThreadEnumerate +static uint32_t svcRtxThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items) { + os_thread_t *thread; + uint32_t count; + + // Check parameters + if ((thread_array == NULL) || (array_items == 0U)) { + EvrRtxThreadEnumerate(thread_array, array_items, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return 0U; + } + + // Running Thread + *thread_array = osRtxThreadGetRunning(); + thread_array++; + count = 1U; + + // Ready List + for (thread = osRtxInfo.thread.ready.thread_list; + (thread != NULL) && (count < array_items); thread = thread->thread_next) { + *thread_array = thread; + thread_array++; + count++; + } + + // Delay List + for (thread = osRtxInfo.thread.delay_list; + (thread != NULL) && (count < array_items); thread = thread->delay_next) { + *thread_array = thread; + thread_array++; + count++; + } + + // Wait List + for (thread = osRtxInfo.thread.wait_list; + (thread != NULL) && (count < array_items); thread = thread->delay_next) { + *thread_array = thread; + thread_array++; + count++; + } + + EvrRtxThreadEnumerate(thread_array - count, array_items, count); + + return count; +} + +/// Set the specified Thread Flags of a thread. +/// \note API identical to osThreadFlagsSet +static uint32_t svcRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) { + os_thread_t *thread = osRtxThreadId(thread_id); + uint32_t thread_flags; + uint32_t thread_flags0; + + // Check parameters + if ((thread == NULL) || (thread->id != osRtxIdThread) || + ((flags & ~(((uint32_t)1U << osRtxThreadFlagsLimit) - 1U)) != 0U)) { + EvrRtxThreadFlagsError(thread, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return ((uint32_t)osErrorParameter); + } + + // Check object state + if (thread->state == osRtxThreadTerminated) { + EvrRtxThreadFlagsError(thread, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return ((uint32_t)osErrorResource); + } + + // Set Thread Flags + thread_flags = ThreadFlagsSet(thread, flags); + + // Check if Thread is waiting for Thread Flags + if (thread->state == osRtxThreadWaitingThreadFlags) { + thread_flags0 = ThreadFlagsCheck(thread, thread->wait_flags, thread->flags_options); + if (thread_flags0 != 0U) { + if ((thread->flags_options & osFlagsNoClear) == 0U) { + thread_flags = thread_flags0 & ~thread->wait_flags; + } else { + thread_flags = thread_flags0; + } + osRtxThreadWaitExit(thread, thread_flags0, TRUE); + EvrRtxThreadFlagsWaitCompleted(thread->wait_flags, thread->flags_options, thread_flags0, thread); + } + } + + EvrRtxThreadFlagsSetDone(thread, thread_flags); + + return thread_flags; +} + +/// Clear the specified Thread Flags of current running thread. +/// \note API identical to osThreadFlagsClear +static uint32_t svcRtxThreadFlagsClear (uint32_t flags) { + os_thread_t *thread; + uint32_t thread_flags; + + // Check running thread + thread = osRtxThreadGetRunning(); + if (thread == NULL) { + EvrRtxThreadFlagsError(NULL, osRtxErrorKernelNotRunning); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return ((uint32_t)osError); + } + + // Check parameters + if ((flags & ~(((uint32_t)1U << osRtxThreadFlagsLimit) - 1U)) != 0U) { + EvrRtxThreadFlagsError(thread, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return ((uint32_t)osErrorParameter); + } + + // Clear Thread Flags + thread_flags = ThreadFlagsClear(thread, flags); + + EvrRtxThreadFlagsClearDone(thread_flags); + + return thread_flags; +} + +/// Get the current Thread Flags of current running thread. +/// \note API identical to osThreadFlagsGet +static uint32_t svcRtxThreadFlagsGet (void) { + const os_thread_t *thread; + + // Check running thread + thread = osRtxThreadGetRunning(); + if (thread == NULL) { + EvrRtxThreadFlagsGet(0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return 0U; + } + + EvrRtxThreadFlagsGet(thread->thread_flags); + + return thread->thread_flags; +} + +/// Wait for one or more Thread Flags of the current running thread to become signaled. +/// \note API identical to osThreadFlagsWait +static uint32_t svcRtxThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) { + os_thread_t *thread; + uint32_t thread_flags; + + // Check running thread + thread = osRtxThreadGetRunning(); + if (thread == NULL) { + EvrRtxThreadFlagsError(NULL, osRtxErrorKernelNotRunning); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return ((uint32_t)osError); + } + + // Check parameters + if ((flags & ~(((uint32_t)1U << osRtxThreadFlagsLimit) - 1U)) != 0U) { + EvrRtxThreadFlagsError(thread, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return ((uint32_t)osErrorParameter); + } + + // Check Thread Flags + thread_flags = ThreadFlagsCheck(thread, flags, options); + if (thread_flags != 0U) { + EvrRtxThreadFlagsWaitCompleted(flags, options, thread_flags, thread); + } else { + // Check if timeout is specified + if (timeout != 0U) { + // Store waiting flags and options + EvrRtxThreadFlagsWaitPending(flags, options, timeout); + thread->wait_flags = flags; + thread->flags_options = (uint8_t)options; + // Suspend current Thread + if (!osRtxThreadWaitEnter(osRtxThreadWaitingThreadFlags, timeout)) { + EvrRtxThreadFlagsWaitTimeout(thread); + } + thread_flags = (uint32_t)osErrorTimeout; + } else { + EvrRtxThreadFlagsWaitNotCompleted(flags, options); + thread_flags = (uint32_t)osErrorResource; + } + } + return thread_flags; +} + +// Service Calls definitions +//lint ++flb "Library Begin" [MISRA Note 11] +SVC0_3 (ThreadNew, osThreadId_t, osThreadFunc_t, void *, const osThreadAttr_t *) +SVC0_1 (ThreadGetName, const char *, osThreadId_t) +SVC0_0 (ThreadGetId, osThreadId_t) +SVC0_1 (ThreadGetState, osThreadState_t, osThreadId_t) +SVC0_1 (ThreadGetStackSize, uint32_t, osThreadId_t) +SVC0_1 (ThreadGetStackSpace, uint32_t, osThreadId_t) +SVC0_2 (ThreadSetPriority, osStatus_t, osThreadId_t, osPriority_t) +SVC0_1 (ThreadGetPriority, osPriority_t, osThreadId_t) +SVC0_0 (ThreadYield, osStatus_t) +SVC0_1 (ThreadSuspend, osStatus_t, osThreadId_t) +SVC0_1 (ThreadResume, osStatus_t, osThreadId_t) +SVC0_1 (ThreadDetach, osStatus_t, osThreadId_t) +SVC0_1 (ThreadJoin, osStatus_t, osThreadId_t) +SVC0_0N(ThreadExit, void) +SVC0_1 (ThreadTerminate, osStatus_t, osThreadId_t) +SVC0_0 (ThreadGetCount, uint32_t) +SVC0_2 (ThreadEnumerate, uint32_t, osThreadId_t *, uint32_t) +SVC0_2 (ThreadFlagsSet, uint32_t, osThreadId_t, uint32_t) +SVC0_1 (ThreadFlagsClear, uint32_t, uint32_t) +SVC0_0 (ThreadFlagsGet, uint32_t) +SVC0_3 (ThreadFlagsWait, uint32_t, uint32_t, uint32_t, uint32_t) +//lint --flb "Library End" + + +// ==== ISR Calls ==== + +/// Set the specified Thread Flags of a thread. +/// \note API identical to osThreadFlagsSet +__STATIC_INLINE +uint32_t isrRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) { + os_thread_t *thread = osRtxThreadId(thread_id); + uint32_t thread_flags; + + // Check parameters + if ((thread == NULL) || (thread->id != osRtxIdThread) || + ((flags & ~(((uint32_t)1U << osRtxThreadFlagsLimit) - 1U)) != 0U)) { + EvrRtxThreadFlagsError(thread, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return ((uint32_t)osErrorParameter); + } + + // Check object state + if (thread->state == osRtxThreadTerminated) { + EvrRtxThreadFlagsError(thread, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return ((uint32_t)osErrorResource); + } + + // Set Thread Flags + thread_flags = ThreadFlagsSet(thread, flags); + + // Register post ISR processing + osRtxPostProcess(osRtxObject(thread)); + + EvrRtxThreadFlagsSetDone(thread, thread_flags); + + return thread_flags; +} + + +// ==== Library functions ==== + +/// Thread startup (Idle and Timer Thread). +/// \return true - success, false - failure. +bool_t osRtxThreadStartup (void) { + bool_t ret = TRUE; + + // Create Idle Thread + osRtxInfo.thread.idle = osRtxThreadId( + svcRtxThreadNew(osRtxIdleThread, NULL, osRtxConfig.idle_thread_attr) + ); + + // Create Timer Thread + if (osRtxConfig.timer_mq_mcnt != 0U) { + osRtxInfo.timer.thread = osRtxThreadId( + svcRtxThreadNew(osRtxTimerThread, NULL, osRtxConfig.timer_thread_attr) + ); + if (osRtxInfo.timer.thread == NULL) { + ret = FALSE; + } + } + + return ret; +} + + +// ==== Public API ==== + +/// Create a thread and add it to Active Threads. +osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { + osThreadId_t thread_id; + + EvrRtxThreadNew(func, argument, attr); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadError(NULL, (int32_t)osErrorISR); + thread_id = NULL; + } else { + thread_id = __svcThreadNew(func, argument, attr); + } + return thread_id; +} + +/// Get name of a thread. +const char *osThreadGetName (osThreadId_t thread_id) { + const char *name; + + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadGetName(thread_id, NULL); + name = NULL; + } else { + name = __svcThreadGetName(thread_id); + } + return name; +} + +/// Return the thread ID of the current running thread. +osThreadId_t osThreadGetId (void) { + osThreadId_t thread_id; + + if (IsIrqMode() || IsIrqMasked()) { + thread_id = svcRtxThreadGetId(); + } else { + thread_id = __svcThreadGetId(); + } + return thread_id; +} + +/// Get current thread state of a thread. +osThreadState_t osThreadGetState (osThreadId_t thread_id) { + osThreadState_t state; + + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadGetState(thread_id, osThreadError); + state = osThreadError; + } else { + state = __svcThreadGetState(thread_id); + } + return state; +} + +/// Get stack size of a thread. +uint32_t osThreadGetStackSize (osThreadId_t thread_id) { + uint32_t stack_size; + + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadGetStackSize(thread_id, 0U); + stack_size = 0U; + } else { + stack_size = __svcThreadGetStackSize(thread_id); + } + return stack_size; +} + +/// Get available stack space of a thread based on stack watermark recording during execution. +uint32_t osThreadGetStackSpace (osThreadId_t thread_id) { + uint32_t stack_space; + + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadGetStackSpace(thread_id, 0U); + stack_space = 0U; + } else { + stack_space = __svcThreadGetStackSpace(thread_id); + } + return stack_space; +} + +/// Change priority of a thread. +osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) { + osStatus_t status; + + EvrRtxThreadSetPriority(thread_id, priority); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadError(thread_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcThreadSetPriority(thread_id, priority); + } + return status; +} + +/// Get current priority of a thread. +osPriority_t osThreadGetPriority (osThreadId_t thread_id) { + osPriority_t priority; + + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadGetPriority(thread_id, osPriorityError); + priority = osPriorityError; + } else { + priority = __svcThreadGetPriority(thread_id); + } + return priority; +} + +/// Pass control to next thread that is in state READY. +osStatus_t osThreadYield (void) { + osStatus_t status; + + EvrRtxThreadYield(); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadError(NULL, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcThreadYield(); + } + return status; +} + +/// Suspend execution of a thread. +osStatus_t osThreadSuspend (osThreadId_t thread_id) { + osStatus_t status; + + EvrRtxThreadSuspend(thread_id); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadError(thread_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcThreadSuspend(thread_id); + } + return status; +} + +/// Resume execution of a thread. +osStatus_t osThreadResume (osThreadId_t thread_id) { + osStatus_t status; + + EvrRtxThreadResume(thread_id); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadError(thread_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcThreadResume(thread_id); + } + return status; +} + +/// Detach a thread (thread storage can be reclaimed when thread terminates). +osStatus_t osThreadDetach (osThreadId_t thread_id) { + osStatus_t status; + + EvrRtxThreadDetach(thread_id); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadError(thread_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcThreadDetach(thread_id); + } + return status; +} + +/// Wait for specified thread to terminate. +osStatus_t osThreadJoin (osThreadId_t thread_id) { + osStatus_t status; + + EvrRtxThreadJoin(thread_id); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadError(thread_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcThreadJoin(thread_id); + } + return status; +} + +/// Terminate execution of current running thread. +__NO_RETURN void osThreadExit (void) { + EvrRtxThreadExit(); + __svcThreadExit(); + EvrRtxThreadError(NULL, (int32_t)osError); + for (;;) {} +} + +/// Terminate execution of a thread. +osStatus_t osThreadTerminate (osThreadId_t thread_id) { + osStatus_t status; + + EvrRtxThreadTerminate(thread_id); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadError(thread_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcThreadTerminate(thread_id); + } + return status; +} + +/// Get number of active threads. +uint32_t osThreadGetCount (void) { + uint32_t count; + + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadGetCount(0U); + count = 0U; + } else { + count = __svcThreadGetCount(); + } + return count; +} + +/// Enumerate active threads. +uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items) { + uint32_t count; + + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadEnumerate(thread_array, array_items, 0U); + count = 0U; + } else { + count = __svcThreadEnumerate(thread_array, array_items); + } + return count; +} + +/// Set the specified Thread Flags of a thread. +uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) { + uint32_t thread_flags; + + EvrRtxThreadFlagsSet(thread_id, flags); + if (IsIrqMode() || IsIrqMasked()) { + thread_flags = isrRtxThreadFlagsSet(thread_id, flags); + } else { + thread_flags = __svcThreadFlagsSet(thread_id, flags); + } + return thread_flags; +} + +/// Clear the specified Thread Flags of current running thread. +uint32_t osThreadFlagsClear (uint32_t flags) { + uint32_t thread_flags; + + EvrRtxThreadFlagsClear(flags); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadFlagsError(NULL, (int32_t)osErrorISR); + thread_flags = (uint32_t)osErrorISR; + } else { + thread_flags = __svcThreadFlagsClear(flags); + } + return thread_flags; +} + +/// Get the current Thread Flags of current running thread. +uint32_t osThreadFlagsGet (void) { + uint32_t thread_flags; + + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadFlagsGet(0U); + thread_flags = 0U; + } else { + thread_flags = __svcThreadFlagsGet(); + } + return thread_flags; +} + +/// Wait for one or more Thread Flags of the current running thread to become signaled. +uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) { + uint32_t thread_flags; + + EvrRtxThreadFlagsWait(flags, options, timeout); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxThreadFlagsError(NULL, (int32_t)osErrorISR); + thread_flags = (uint32_t)osErrorISR; + } else { + thread_flags = __svcThreadFlagsWait(flags, options, timeout); + } + return thread_flags; +} diff --git a/source/rtos2/RTX/Source/rtx_timer.c b/source/rtos2/RTX/Source/rtx_timer.c new file mode 100644 index 000000000..de3c98712 --- /dev/null +++ b/source/rtos2/RTX/Source/rtx_timer.c @@ -0,0 +1,459 @@ +/* + * Copyright (c) 2013-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Timer functions + * + * ----------------------------------------------------------------------------- + */ + +#include "rtx_lib.h" + + +// OS Runtime Object Memory Usage +#if ((defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0))) +osRtxObjectMemUsage_t osRtxTimerMemUsage \ +__attribute__((section(".data.os.timer.obj"))) = +{ 0U, 0U, 0U }; +#endif + + +// ==== Helper functions ==== + +/// Insert Timer into the Timer List sorted by Time. +/// \param[in] timer timer object. +/// \param[in] tick timer tick. +static void TimerInsert (os_timer_t *timer, uint32_t tick) { + os_timer_t *prev, *next; + + prev = NULL; + next = osRtxInfo.timer.list; + while ((next != NULL) && (next->tick <= tick)) { + tick -= next->tick; + prev = next; + next = next->next; + } + timer->tick = tick; + timer->prev = prev; + timer->next = next; + if (next != NULL) { + next->tick -= timer->tick; + next->prev = timer; + } + if (prev != NULL) { + prev->next = timer; + } else { + osRtxInfo.timer.list = timer; + } +} + +/// Remove Timer from the Timer List. +/// \param[in] timer timer object. +static void TimerRemove (const os_timer_t *timer) { + + if (timer->next != NULL) { + timer->next->tick += timer->tick; + timer->next->prev = timer->prev; + } + if (timer->prev != NULL) { + timer->prev->next = timer->next; + } else { + osRtxInfo.timer.list = timer->next; + } +} + +/// Unlink Timer from the Timer List Head. +/// \param[in] timer timer object. +static void TimerUnlink (const os_timer_t *timer) { + + if (timer->next != NULL) { + timer->next->prev = timer->prev; + } + osRtxInfo.timer.list = timer->next; +} + + +// ==== Library functions ==== + +/// Timer Tick (called each SysTick). +static void osRtxTimerTick (void) { + os_timer_t *timer; + osStatus_t status; + + timer = osRtxInfo.timer.list; + if (timer == NULL) { + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return; + } + + timer->tick--; + while ((timer != NULL) && (timer->tick == 0U)) { + TimerUnlink(timer); + status = osMessageQueuePut(osRtxInfo.timer.mq, &timer->finfo, 0U, 0U); + if (status != osOK) { + (void)osRtxErrorNotify(osRtxErrorTimerQueueOverflow, timer); + } + if (timer->type == osRtxTimerPeriodic) { + TimerInsert(timer, timer->load); + } else { + timer->state = osRtxTimerStopped; + } + timer = osRtxInfo.timer.list; + } +} + +/// Timer Thread +__WEAK __NO_RETURN void osRtxTimerThread (void *argument) { + os_timer_finfo_t finfo; + osStatus_t status; + (void) argument; + + osRtxInfo.timer.mq = osRtxMessageQueueId( + osMessageQueueNew(osRtxConfig.timer_mq_mcnt, sizeof(os_timer_finfo_t), osRtxConfig.timer_mq_attr) + ); + osRtxInfo.timer.tick = osRtxTimerTick; + + for (;;) { + //lint -e{934} "Taking address of near auto variable" + status = osMessageQueueGet(osRtxInfo.timer.mq, &finfo, NULL, osWaitForever); + if (status == osOK) { + EvrRtxTimerCallback(finfo.func, finfo.arg); + (finfo.func)(finfo.arg); + } + } +} + +// ==== Service Calls ==== + +/// Create and Initialize a timer. +/// \note API identical to osTimerNew +static osTimerId_t svcRtxTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) { + os_timer_t *timer; + uint8_t flags; + const char *name; + + // Check parameters + if ((func == NULL) || ((type != osTimerOnce) && (type != osTimerPeriodic))) { + EvrRtxTimerError(NULL, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + + // Process attributes + if (attr != NULL) { + name = attr->name; + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 6] + timer = attr->cb_mem; + if (timer != NULL) { + //lint -e(923) -e(9078) "cast from pointer to unsigned int" [MISRA Note 7] + if ((((uint32_t)timer & 3U) != 0U) || (attr->cb_size < sizeof(os_timer_t))) { + EvrRtxTimerError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + } else { + if (attr->cb_size != 0U) { + EvrRtxTimerError(NULL, osRtxErrorInvalidControlBlock); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + } + } else { + name = NULL; + timer = NULL; + } + + // Allocate object memory if not provided + if (timer == NULL) { + if (osRtxInfo.mpi.timer != NULL) { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + timer = osRtxMemoryPoolAlloc(osRtxInfo.mpi.timer); + } else { + //lint -e{9079} "conversion from pointer to void to pointer to other type" [MISRA Note 5] + timer = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_timer_t), 1U); + } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + if (timer != NULL) { + uint32_t used; + osRtxTimerMemUsage.cnt_alloc++; + used = osRtxTimerMemUsage.cnt_alloc - osRtxTimerMemUsage.cnt_free; + if (osRtxTimerMemUsage.max_used < used) { + osRtxTimerMemUsage.max_used = used; + } + } +#endif + flags = osRtxFlagSystemObject; + } else { + flags = 0U; + } + + if (timer != NULL) { + // Initialize control block + timer->id = osRtxIdTimer; + timer->state = osRtxTimerStopped; + timer->flags = flags; + timer->type = (uint8_t)type; + timer->name = name; + timer->prev = NULL; + timer->next = NULL; + timer->tick = 0U; + timer->load = 0U; + timer->finfo.func = func; + timer->finfo.arg = argument; + + EvrRtxTimerCreated(timer, timer->name); + } else { + EvrRtxTimerError(NULL, (int32_t)osErrorNoMemory); + } + + return timer; +} + +/// Get name of a timer. +/// \note API identical to osTimerGetName +static const char *svcRtxTimerGetName (osTimerId_t timer_id) { + os_timer_t *timer = osRtxTimerId(timer_id); + + // Check parameters + if ((timer == NULL) || (timer->id != osRtxIdTimer)) { + EvrRtxTimerGetName(timer, NULL); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return NULL; + } + + EvrRtxTimerGetName(timer, timer->name); + + return timer->name; +} + +/// Start or restart a timer. +/// \note API identical to osTimerStart +static osStatus_t svcRtxTimerStart (osTimerId_t timer_id, uint32_t ticks) { + os_timer_t *timer = osRtxTimerId(timer_id); + + // Check parameters + if ((timer == NULL) || (timer->id != osRtxIdTimer) || (ticks == 0U)) { + EvrRtxTimerError(timer, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + if (timer->state == osRtxTimerRunning) { + TimerRemove(timer); + } else { + if (osRtxInfo.timer.tick == NULL) { + EvrRtxTimerError(timer, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorResource; + } else { + timer->state = osRtxTimerRunning; + timer->load = ticks; + } + } + + TimerInsert(timer, ticks); + + EvrRtxTimerStarted(timer); + + return osOK; +} + +/// Stop a timer. +/// \note API identical to osTimerStop +static osStatus_t svcRtxTimerStop (osTimerId_t timer_id) { + os_timer_t *timer = osRtxTimerId(timer_id); + + // Check parameters + if ((timer == NULL) || (timer->id != osRtxIdTimer)) { + EvrRtxTimerError(timer, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + // Check object state + if (timer->state != osRtxTimerRunning) { + EvrRtxTimerError(timer, (int32_t)osErrorResource); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorResource; + } + + timer->state = osRtxTimerStopped; + + TimerRemove(timer); + + EvrRtxTimerStopped(timer); + + return osOK; +} + +/// Check if a timer is running. +/// \note API identical to osTimerIsRunning +static uint32_t svcRtxTimerIsRunning (osTimerId_t timer_id) { + os_timer_t *timer = osRtxTimerId(timer_id); + uint32_t is_running; + + // Check parameters + if ((timer == NULL) || (timer->id != osRtxIdTimer)) { + EvrRtxTimerIsRunning(timer, 0U); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return 0U; + } + + if (timer->state == osRtxTimerRunning) { + EvrRtxTimerIsRunning(timer, 1U); + is_running = 1U; + } else { + EvrRtxTimerIsRunning(timer, 0U); + is_running = 0; + } + + return is_running; +} + +/// Delete a timer. +/// \note API identical to osTimerDelete +static osStatus_t svcRtxTimerDelete (osTimerId_t timer_id) { + os_timer_t *timer = osRtxTimerId(timer_id); + + // Check parameters + if ((timer == NULL) || (timer->id != osRtxIdTimer)) { + EvrRtxTimerError(timer, (int32_t)osErrorParameter); + //lint -e{904} "Return statement before end of function" [MISRA Note 1] + return osErrorParameter; + } + + if (timer->state == osRtxTimerRunning) { + TimerRemove(timer); + } + + // Mark object as inactive and invalid + timer->state = osRtxTimerInactive; + timer->id = osRtxIdInvalid; + + // Free object memory + if ((timer->flags & osRtxFlagSystemObject) != 0U) { + if (osRtxInfo.mpi.timer != NULL) { + (void)osRtxMemoryPoolFree(osRtxInfo.mpi.timer, timer); + } else { + (void)osRtxMemoryFree(osRtxInfo.mem.common, timer); + } +#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0)) + osRtxTimerMemUsage.cnt_free++; +#endif + } + + EvrRtxTimerDestroyed(timer); + + return osOK; +} + +// Service Calls definitions +//lint ++flb "Library Begin" [MISRA Note 11] +SVC0_4(TimerNew, osTimerId_t, osTimerFunc_t, osTimerType_t, void *, const osTimerAttr_t *) +SVC0_1(TimerGetName, const char *, osTimerId_t) +SVC0_2(TimerStart, osStatus_t, osTimerId_t, uint32_t) +SVC0_1(TimerStop, osStatus_t, osTimerId_t) +SVC0_1(TimerIsRunning, uint32_t, osTimerId_t) +SVC0_1(TimerDelete, osStatus_t, osTimerId_t) +//lint --flb "Library End" + + +// ==== Public API ==== + +/// Create and Initialize a timer. +osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) { + osTimerId_t timer_id; + + EvrRtxTimerNew(func, type, argument, attr); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxTimerError(NULL, (int32_t)osErrorISR); + timer_id = NULL; + } else { + timer_id = __svcTimerNew(func, type, argument, attr); + } + return timer_id; +} + +/// Get name of a timer. +const char *osTimerGetName (osTimerId_t timer_id) { + const char *name; + + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxTimerGetName(timer_id, NULL); + name = NULL; + } else { + name = __svcTimerGetName(timer_id); + } + return name; +} + +/// Start or restart a timer. +osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) { + osStatus_t status; + + EvrRtxTimerStart(timer_id, ticks); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxTimerError(timer_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcTimerStart(timer_id, ticks); + } + return status; +} + +/// Stop a timer. +osStatus_t osTimerStop (osTimerId_t timer_id) { + osStatus_t status; + + EvrRtxTimerStop(timer_id); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxTimerError(timer_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcTimerStop(timer_id); + } + return status; +} + +/// Check if a timer is running. +uint32_t osTimerIsRunning (osTimerId_t timer_id) { + uint32_t is_running; + + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxTimerIsRunning(timer_id, 0U); + is_running = 0U; + } else { + is_running = __svcTimerIsRunning(timer_id); + } + return is_running; +} + +/// Delete a timer. +osStatus_t osTimerDelete (osTimerId_t timer_id) { + osStatus_t status; + + EvrRtxTimerDelete(timer_id); + if (IsIrqMode() || IsIrqMasked()) { + EvrRtxTimerError(timer_id, (int32_t)osErrorISR); + status = osErrorISR; + } else { + status = __svcTimerDelete(timer_id); + } + return status; +} diff --git a/source/rtos2/Source/os_systick.c b/source/rtos2/Source/os_systick.c new file mode 100644 index 000000000..b7c3e3e0b --- /dev/null +++ b/source/rtos2/Source/os_systick.c @@ -0,0 +1,133 @@ +/**************************************************************************//** + * @file os_systick.c + * @brief CMSIS OS Tick SysTick implementation + * @version V1.0.2 + * @date 6. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "os_tick.h" + +//lint -emacro((923,9078),SCB,SysTick) "cast from unsigned long to pointer" +#include "RTE_Components.h" +#include CMSIS_device_header + +#ifdef SysTick + +#ifndef SYSTICK_IRQ_PRIORITY +#define SYSTICK_IRQ_PRIORITY 0xFFU +#endif + +static uint8_t PendST; + +// Setup OS Tick. +__WEAK int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { + uint32_t load; + (void)handler; + + if (freq == 0U) { + //lint -e{904} "Return statement before end of function" + return (-1); + } + + load = (SystemCoreClock / freq) - 1U; + if (load > 0x00FFFFFFU) { + //lint -e{904} "Return statement before end of function" + return (-1); + } + + // Set SysTick Interrupt Priority +#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)) || \ + (defined(__CORTEX_M) && (__CORTEX_M == 7U))) + SCB->SHPR[11] = SYSTICK_IRQ_PRIORITY; +#elif (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + SCB->SHPR[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24); +#elif ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0))) + SCB->SHP[11] = SYSTICK_IRQ_PRIORITY; +#elif (defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) + SCB->SHP[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24); +#else +#error "Unknown ARM Core!" +#endif + + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk; + SysTick->LOAD = load; + SysTick->VAL = 0U; + + PendST = 0U; + + return (0); +} + +/// Enable OS Tick. +__WEAK void OS_Tick_Enable (void) { + + if (PendST != 0U) { + PendST = 0U; + SCB->ICSR = SCB_ICSR_PENDSTSET_Msk; + } + + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; +} + +/// Disable OS Tick. +__WEAK void OS_Tick_Disable (void) { + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + + if ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0U) { + SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk; + PendST = 1U; + } +} + +// Acknowledge OS Tick IRQ. +__WEAK void OS_Tick_AcknowledgeIRQ (void) { + (void)SysTick->CTRL; +} + +// Get OS Tick IRQ number. +__WEAK int32_t OS_Tick_GetIRQn (void) { + return ((int32_t)SysTick_IRQn); +} + +// Get OS Tick clock. +__WEAK uint32_t OS_Tick_GetClock (void) { + return (SystemCoreClock); +} + +// Get OS Tick interval. +__WEAK uint32_t OS_Tick_GetInterval (void) { + return (SysTick->LOAD + 1U); +} + +// Get OS Tick count value. +__WEAK uint32_t OS_Tick_GetCount (void) { + uint32_t load = SysTick->LOAD; + return (load - SysTick->VAL); +} + +// Get OS Tick overflow status. +__WEAK uint32_t OS_Tick_GetOverflow (void) { + return ((SysTick->CTRL >> 16) & 1U); +} + +#endif // SysTick From 70fe7893983d245dd14c44ce309818e0ae80d52e Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 24 Dec 2020 00:22:58 -0600 Subject: [PATCH 048/617] Customize CMSIS RTOS2 configuration for DAPLink --- source/rtos2/RTX/Config/RTX_Config.h | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/source/rtos2/RTX/Config/RTX_Config.h b/source/rtos2/RTX/Config/RTX_Config.h index 244ed17e3..4f3e14211 100644 --- a/source/rtos2/RTX/Config/RTX_Config.h +++ b/source/rtos2/RTX/Config/RTX_Config.h @@ -44,20 +44,20 @@ // Defines the combined global dynamic memory size. // Default: 32768 #ifndef OS_DYNAMIC_MEM_SIZE -#define OS_DYNAMIC_MEM_SIZE 32768 +#define OS_DYNAMIC_MEM_SIZE 0 // DAPLINK. Default was: 32768 #endif // Kernel Tick Frequency [Hz] <1-1000000> // Defines base time unit for delays and timeouts. // Default: 1000 (1ms tick) #ifndef OS_TICK_FREQ -#define OS_TICK_FREQ 1000 +#define OS_TICK_FREQ 10000 // DAPLINK. Default was: 1000 #endif // Round-Robin Thread switching // Enables Round-Robin Thread switching. #ifndef OS_ROBIN_ENABLE -#define OS_ROBIN_ENABLE 1 +#define OS_ROBIN_ENABLE 0 // DAPLINK. Default was: 1 #endif // Round-Robin Timeout <1-1000> @@ -76,7 +76,7 @@ // RTOS Functions called from ISR store requests to this buffer. // Default: 16 entries #ifndef OS_ISR_FIFO_QUEUE -#define OS_ISR_FIFO_QUEUE 16 +#define OS_ISR_FIFO_QUEUE 4 // DAPLINK. Default was: 16 #endif // Object Memory usage counters @@ -100,7 +100,7 @@ // Defines maximum number of user threads that can be active at the same time. // Applies to user threads with system provided memory for control blocks. #ifndef OS_THREAD_NUM -#define OS_THREAD_NUM 1 +#define OS_THREAD_NUM 0 // DAPLINK. Default was: 1 #endif // Number of user Threads with default Stack size <0-1000> @@ -124,14 +124,14 @@ // Defines stack size for threads with zero stack size specified. // Default: 3072 #ifndef OS_STACK_SIZE -#define OS_STACK_SIZE 3072 +#define OS_STACK_SIZE 72 // DAPLINK. Default was: 3072 #endif // Idle Thread Stack size [bytes] <72-1073741824:8> // Defines stack size for Idle thread. // Default: 512 #ifndef OS_IDLE_THREAD_STACK_SIZE -#define OS_IDLE_THREAD_STACK_SIZE 512 +#define OS_IDLE_THREAD_STACK_SIZE 72 // DAPLINK. Default was: 512 #endif // Idle Thread TrustZone Module Identifier @@ -179,7 +179,7 @@ // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_TIMER_NUM -#define OS_TIMER_NUM 1 +#define OS_TIMER_NUM 0 // DAPLINK. Default was: 1 #endif // @@ -200,7 +200,7 @@ // May be set to 0 when timers are not used. // Default: 512 #ifndef OS_TIMER_THREAD_STACK_SIZE -#define OS_TIMER_THREAD_STACK_SIZE 512 +#define OS_TIMER_THREAD_STACK_SIZE 128 // 512 #endif // Timer Thread TrustZone Module Identifier @@ -274,7 +274,7 @@ // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_SEMAPHORE_NUM -#define OS_SEMAPHORE_NUM 1 +#define OS_SEMAPHORE_NUM 0 // DAPLINK. Default was: 1 #endif // @@ -294,7 +294,7 @@ // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_MEMPOOL_NUM -#define OS_MEMPOOL_NUM 1 +#define OS_MEMPOOL_NUM 0 // DAPLINK. Default was: 1 #endif // Data Storage Memory size [bytes] <0-1073741824:8> @@ -322,7 +322,7 @@ // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_MSGQUEUE_NUM -#define OS_MSGQUEUE_NUM 1 +#define OS_MSGQUEUE_NUM 0 // DAPLINK. Default was: 1 #endif // Data Storage Memory size [bytes] <0-1073741824:8> @@ -349,7 +349,7 @@ // Start recording // Start event recording after initialization. #ifndef OS_EVR_START -#define OS_EVR_START 1 +#define OS_EVR_START 0 // DAPLINK. Default was: 1 #endif // Global Event Filter Setup From 89eeb153a849d5978a3bf8a3239a20993f3a3343 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Mon, 28 Oct 2019 16:35:21 -0500 Subject: [PATCH 049/617] Move RTX_Config.h to Include directory --- records/rtos/rtos-cm0.yaml | 2 -- records/rtos/rtos-cm3.yaml | 2 -- records/rtos/rtos-cm4.yaml | 2 -- source/rtos2/{RTX/Config => Include}/RTX_Config.h | 0 4 files changed, 6 deletions(-) rename source/rtos2/{RTX/Config => Include}/RTX_Config.h (100%) diff --git a/records/rtos/rtos-cm0.yaml b/records/rtos/rtos-cm0.yaml index 2dc842d2e..6713abdd3 100644 --- a/records/rtos/rtos-cm0.yaml +++ b/records/rtos/rtos-cm0.yaml @@ -47,7 +47,6 @@ tool_specific: includes: - source/rtos2/Include - source/rtos2/RTX/Include - - source/rtos2/RTX/Config sources: rtos: - source/rtos2/RTX/Source/ARM/irq_cm0.s @@ -68,7 +67,6 @@ tool_specific: includes: - source/rtos2/Include - source/rtos2/RTX/Include - - source/rtos2/RTX/Config sources: rtos: - source/rtos2/RTX/Source/GCC/irq_cm0.S diff --git a/records/rtos/rtos-cm3.yaml b/records/rtos/rtos-cm3.yaml index cdf16e7fa..360afacfa 100644 --- a/records/rtos/rtos-cm3.yaml +++ b/records/rtos/rtos-cm3.yaml @@ -47,7 +47,6 @@ tool_specific: includes: - source/rtos2/Include - source/rtos2/RTX/Include - - source/rtos2/RTX/Config sources: rtos: - source/rtos2/RTX/Source/ARM/irq_cm3.s @@ -68,7 +67,6 @@ tool_specific: includes: - source/rtos2/Include - source/rtos2/RTX/Include - - source/rtos2/RTX/Config sources: rtos: - source/rtos2/RTX/Source/GCC/irq_cm3.S diff --git a/records/rtos/rtos-cm4.yaml b/records/rtos/rtos-cm4.yaml index 78b83e026..9bf527ee7 100644 --- a/records/rtos/rtos-cm4.yaml +++ b/records/rtos/rtos-cm4.yaml @@ -49,7 +49,6 @@ tool_specific: includes: - source/rtos2/Include - source/rtos2/RTX/Include - - source/rtos2/RTX/Config sources: rtos: - source/rtos2/RTX/Source/ARM/irq_cm3.s @@ -70,7 +69,6 @@ tool_specific: includes: - source/rtos2/Include - source/rtos2/RTX/Include - - source/rtos2/RTX/Config sources: rtos: - source/rtos2/RTX/Source/GCC/irq_cm3.S diff --git a/source/rtos2/RTX/Config/RTX_Config.h b/source/rtos2/Include/RTX_Config.h similarity index 100% rename from source/rtos2/RTX/Config/RTX_Config.h rename to source/rtos2/Include/RTX_Config.h From 1392198a3545b60df49ac5b966fa6c12d168bedf Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Thu, 28 Nov 2019 17:04:33 -0600 Subject: [PATCH 050/617] Common daplink.ld gcc linker script. --- source/daplink/daplink.ld | 223 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 223 insertions(+) create mode 100644 source/daplink/daplink.ld diff --git a/source/daplink/daplink.ld b/source/daplink/daplink.ld new file mode 100644 index 000000000..b45e3851e --- /dev/null +++ b/source/daplink/daplink.ld @@ -0,0 +1,223 @@ +/** + * @file daplink.ld + * @brief + * + * DAPLink Interface Firmware + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * Copyright (c) 2019, ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "daplink_addr.h" + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = DAPLINK_ROM_APP_START, LENGTH = 0x400 + m_text (RX) : ORIGIN = DAPLINK_ROM_APP_START + 0x400, LENGTH = DAPLINK_ROM_APP_SIZE - 0x400 + m_cfgrom (RW) : ORIGIN = DAPLINK_ROM_CONFIG_USER_START, LENGTH = DAPLINK_ROM_CONFIG_USER_SIZE + m_data (RW) : ORIGIN = DAPLINK_RAM_APP_START, LENGTH = DAPLINK_RAM_APP_SIZE + m_cfgram (RW) : ORIGIN = DAPLINK_RAM_SHARED_START, LENGTH = DAPLINK_RAM_SHARED_SIZE +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + FILL(0xffffffff) + . = ALIGN(4); + . += LENGTH(m_interrupts) - (. - ORIGIN(m_interrupts)); /* pad out to end of m_interrupts */ + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + + /* fill .text out to the end of the app */ + .fill __DATA_END : + { + FILL(0xffffffff) + . = ALIGN(4); + . += DAPLINK_ROM_APP_START + DAPLINK_ROM_APP_SIZE - __DATA_END - 4; + /* Need some contents in this section or it won't be copied to bin or hex. The CRC will + * be placed here by post_build_script.py. */ + LONG(0x55555555) + } > m_text + + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + .cfgrom (NOLOAD) : + { + *(cfgrom) + } > m_cfgrom + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + .cfgram (NOLOAD) : + { + *(cfgram) + } > m_cfgram + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region overflowed with stack and heap") +} + From 7eb6c8052baa5a661e4217e275dbe02b5060b9eb Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Thu, 28 Nov 2019 17:05:13 -0600 Subject: [PATCH 051/617] Initial gcc support in k20dx. --- records/hic_hal/k20dx.yaml | 8 + records/tools/make_gcc_arm.yaml | 34 +- .../freescale/k20dx/gcc/startup_MK20D5.S | 342 ++++++++++++++++++ source/hic_hal/freescale/kinetis.ld | 231 ++++++++++++ 4 files changed, 607 insertions(+), 8 deletions(-) create mode 100644 source/hic_hal/freescale/k20dx/gcc/startup_MK20D5.S create mode 100644 source/hic_hal/freescale/kinetis.ld diff --git a/records/hic_hal/k20dx.yaml b/records/hic_hal/k20dx.yaml index c274f84b6..2b12e7dff 100644 --- a/records/hic_hal/k20dx.yaml +++ b/records/hic_hal/k20dx.yaml @@ -39,3 +39,11 @@ tool_specific: sources: hic_hal: - source/hic_hal/freescale/k20dx/armcc + make_gcc_arm: + linker_file: + - source/hic_hal/freescale/kinetis.ld + includes: + - source/hic_hal/freescale/k20dx/gcc + sources: + hic_hal: + - source/hic_hal/freescale/k20dx/gcc diff --git a/records/tools/make_gcc_arm.yaml b/records/tools/make_gcc_arm.yaml index ddc968794..25e9333b7 100644 --- a/records/tools/make_gcc_arm.yaml +++ b/records/tools/make_gcc_arm.yaml @@ -4,19 +4,37 @@ tool_specific: - cortex-m0 macros: - + linker_file: + - source/daplink/daplink.ld misc: libraries: - m - gcc - c - nosys - optimization: - - O3 - compiler_options: - - Wall - - ffunction-sections - - fdata-sections - linker_options: - - nostartfiles + common_flags: + - -Os + - -g3 +# - -Wall + - -ffunction-sections + - -fdata-sections + - -std=gnu99 + - -fshort-wchar + - -fno-common + - -ffreestanding + - -Wa,-adln=$@.lst + - -fverbose-asm + - -mno-unaligned-access + ld_flags: + - -Wl,--no-wchar-size-warning + - --specs=nano.specs + - --specs=nosys.specs + - -Wl,--gc-sections + - -Wl,--defsym=__stack_size__=0x200 + - -Wl,--defsym=__heap_size__=0x0 + pre_build_script: + - tools/pre_build_script.sh + post_build_script: + - tools/post_build_script.sh diff --git a/source/hic_hal/freescale/k20dx/gcc/startup_MK20D5.S b/source/hic_hal/freescale/k20dx/gcc/startup_MK20D5.S new file mode 100644 index 000000000..cbf89d9f0 --- /dev/null +++ b/source/hic_hal/freescale/k20dx/gcc/startup_MK20D5.S @@ -0,0 +1,342 @@ +/** + * @file startup_MK20D5.s + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long 0 /* Reserved*/ + .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ + .long DAPLINK_HIC_ID /* Compatibility*/ + .long DAPLINK_VERSION /* Version*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long g_board_info /* Ptr to Board info, family info other target details*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long DMA0_IRQHandler /* DMA channel 0 transfer complete*/ + .long DMA1_IRQHandler /* DMA channel 1 transfer complete*/ + .long DMA2_IRQHandler /* DMA channel 2 transfer complete*/ + .long DMA3_IRQHandler /* DMA channel 3 transfer complete*/ + .long DMA_Error_IRQHandler /* DMA channel 0 - 15 error*/ + .long Reserved21_IRQHandler /* Reserved interrupt 21 */ + .long FTFL_IRQHandler /* FTFL interrupt */ + .long Read_Collision_IRQHandler /* Read collision interrupt */ + .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning */ + .long LLW_IRQHandler /* Low Leakage Wakeup */ + .long Watchdog_IRQHandler /* WDOG interrupt */ + .long I2C0_IRQHandler /* I2C0 interrupt */ + .long SPI0_IRQHandler /* SPI0 interrupt */ + .long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt */ + .long I2S0_Rx_IRQHandler /* I2S0 receive interrupt */ + .long UART0_LON_IRQHandler /* UART0 LON interrupt */ + .long UART0_RX_TX_IRQHandler /* UART0 receive/transmit interrupt */ + .long UART0_ERR_IRQHandler /* UART0 error interrupt */ + .long UART1_RX_TX_IRQHandler /* UART1 receive/transmit interrupt */ + .long UART1_ERR_IRQHandler /* UART1 error interrupt */ + .long UART2_RX_TX_IRQHandler /* UART2 receive/transmit interrupt */ + .long UART2_ERR_IRQHandler /* UART2 error interrupt */ + .long ADC0_IRQHandler /* ADC0 interrupt */ + .long CMP0_IRQHandler /* CMP0 interrupt */ + .long CMP1_IRQHandler /* CMP1 interrupt */ + .long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt */ + .long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt */ + .long CMT_IRQHandler /* CMT interrupt */ + .long RTC_IRQHandler /* RTC interrupt */ + .long RTC_Seconds_IRQHandler /* RTC seconds interrupt */ + .long PIT0_IRQHandler /* PIT timer channel 0 interrupt */ + .long PIT1_IRQHandler /* PIT timer channel 1 interrupt */ + .long PIT2_IRQHandler /* PIT timer channel 2 interrupt */ + .long PIT3_IRQHandler /* PIT timer channel 3 interrupt */ + .long PDB0_IRQHandler /* PDB0 interrupt */ + .long USB0_IRQHandler /* USB0 interrupt */ + .long USBDCD_IRQHandler /* USBDCD interrupt */ + .long TSI0_IRQHandler /* TSI0 interrupt */ + .long MCG_IRQHandler /* MCG interrupt */ + .long LPTimer_IRQHandler /* LPTimer interrupt */ + .long PORTA_IRQHandler /* Port A interrupt */ + .long PORTB_IRQHandler /* Port B interrupt */ + .long PORTC_IRQHandler /* Port C interrupt */ + .long PORTD_IRQHandler /* Port D interrupt */ + .long PORTE_IRQHandler /* Port E interrupt */ + .long SWI_IRQHandler /* Software interrupt */ + + .size __isr_vector, . - __isr_vector + +/* Flash Configuration */ + .section .FlashConfig, "a" + .long 0xFFFFFFFF + .long 0xFFFFFFFF + .long 0xFFFFFFFF + .long 0xFFFFFFFE + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__isr_vector + str r1, [r0] + ldr r2, [r1] + msr msp, r2 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + + cpsie i /* Unmask interrupts */ +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + ldr r0,=MemManage_Handler + bx r0 + .size MemManage_Handler, . - MemManage_Handler + + .align 1 + .thumb_func + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + ldr r0,=BusFault_Handler + bx r0 + .size BusFault_Handler, . - BusFault_Handler + + .align 1 + .thumb_func + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + ldr r0,=UsageFault_Handler + bx r0 + .size UsageFault_Handler, . - UsageFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + ldr r0,=DebugMon_Handler + bx r0 + .size DebugMon_Handler, . - DebugMon_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler DMA0_IRQHandler + def_irq_handler DMA1_IRQHandler + def_irq_handler DMA2_IRQHandler + def_irq_handler DMA3_IRQHandler + def_irq_handler DMA_Error_IRQHandler + def_irq_handler Reserved21_IRQHandler + def_irq_handler FTFL_IRQHandler + def_irq_handler Read_Collision_IRQHandler + def_irq_handler LVD_LVW_IRQHandler + def_irq_handler LLW_IRQHandler + def_irq_handler Watchdog_IRQHandler + def_irq_handler I2C0_IRQHandler + def_irq_handler SPI0_IRQHandler + def_irq_handler I2S0_Tx_IRQHandler + def_irq_handler I2S0_Rx_IRQHandler + def_irq_handler UART0_LON_IRQHandler + def_irq_handler UART0_RX_TX_IRQHandler + def_irq_handler UART0_ERR_IRQHandler + def_irq_handler UART1_RX_TX_IRQHandler + def_irq_handler UART1_ERR_IRQHandler + def_irq_handler UART2_RX_TX_IRQHandler + def_irq_handler UART2_ERR_IRQHandler + def_irq_handler ADC0_IRQHandler + def_irq_handler CMP0_IRQHandler + def_irq_handler CMP1_IRQHandler + def_irq_handler FTM0_IRQHandler + def_irq_handler FTM1_IRQHandler + def_irq_handler CMT_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler RTC_Seconds_IRQHandler + def_irq_handler PIT0_IRQHandler + def_irq_handler PIT1_IRQHandler + def_irq_handler PIT2_IRQHandler + def_irq_handler PIT3_IRQHandler + def_irq_handler PDB0_IRQHandler + def_irq_handler USB0_IRQHandler + def_irq_handler USBDCD_IRQHandler + def_irq_handler TSI0_IRQHandler + def_irq_handler MCG_IRQHandler + def_irq_handler LPTimer_IRQHandler + def_irq_handler PORTA_IRQHandler + def_irq_handler PORTB_IRQHandler + def_irq_handler PORTC_IRQHandler + def_irq_handler PORTD_IRQHandler + def_irq_handler PORTE_IRQHandler + def_irq_handler SWI_IRQHandler + + .end diff --git a/source/hic_hal/freescale/kinetis.ld b/source/hic_hal/freescale/kinetis.ld new file mode 100644 index 000000000..b75bc6a48 --- /dev/null +++ b/source/hic_hal/freescale/kinetis.ld @@ -0,0 +1,231 @@ +/** + * @file daplink.ld + * @brief + * + * DAPLink Interface Firmware + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * Copyright (c) 2019, ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "daplink_addr.h" + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = DAPLINK_ROM_APP_START, LENGTH = 0x400 + m_flash_config (RX) : ORIGIN = DAPLINK_ROM_APP_START + 0x400, LENGTH = 0x10 + m_text (RX) : ORIGIN = DAPLINK_ROM_APP_START + 0x410, LENGTH = DAPLINK_ROM_APP_SIZE - 0x410 + m_cfgrom (RW) : ORIGIN = DAPLINK_ROM_CONFIG_USER_START, LENGTH = DAPLINK_ROM_CONFIG_USER_SIZE + m_data (RW) : ORIGIN = DAPLINK_RAM_APP_START, LENGTH = DAPLINK_RAM_APP_SIZE + m_cfgram (RW) : ORIGIN = DAPLINK_RAM_SHARED_START, LENGTH = DAPLINK_RAM_SHARED_SIZE +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + FILL(0xffffffff) + . = ALIGN(4); + . += LENGTH(m_interrupts) - (. - ORIGIN(m_interrupts)); /* pad out to end of m_interrupts */ + } > m_interrupts + + .flash_config : + { + . = ALIGN(4); + KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_flash_config + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + + /* fill .text out to the end of the interface */ + .fill __DATA_END : + { + FILL(0xffffffff) + . = ALIGN(4); + . += DAPLINK_ROM_APP_START + DAPLINK_ROM_APP_SIZE - __DATA_END - 4; + /* Need some contents in this section or it won't be copied to bin or hex. The CRC will + * be placed here by post_build_script.py. */ + LONG(0x55555555) + } > m_text + + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + .cfgrom (NOLOAD) : + { + *(cfgrom) + } > m_cfgrom + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + .cfgram (NOLOAD) : + { + *(cfgram) + } > m_cfgram + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region overflowed with stack and heap") +} + From 72482e037da078024f5c35c44b9ae353bcee15b7 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sat, 9 Nov 2019 17:01:06 -0600 Subject: [PATCH 052/617] Updated pre and post build scripts for gcc. --- records/tools/make_gcc_arm.yaml | 2 +- tools/post_build_script_gcc.sh | 35 +++++++++++++++++++++++++++++++++ tools/pre_build_script.sh | 9 ++++----- 3 files changed, 40 insertions(+), 6 deletions(-) create mode 100755 tools/post_build_script_gcc.sh diff --git a/records/tools/make_gcc_arm.yaml b/records/tools/make_gcc_arm.yaml index 25e9333b7..afbbaede1 100644 --- a/records/tools/make_gcc_arm.yaml +++ b/records/tools/make_gcc_arm.yaml @@ -35,6 +35,6 @@ tool_specific: pre_build_script: - tools/pre_build_script.sh post_build_script: - - tools/post_build_script.sh + - tools/post_build_script_gcc.sh diff --git a/tools/post_build_script_gcc.sh b/tools/post_build_script_gcc.sh new file mode 100755 index 000000000..099a1e0fb --- /dev/null +++ b/tools/post_build_script_gcc.sh @@ -0,0 +1,35 @@ +#!/bin/bash -e +## +## DAPLink Interface Firmware +## Copyright (c) 2009-2019, ARM Limited, All Rights Reserved +## SPDX-License-Identifier: Apache-2.0 +## +## Licensed under the Apache License, Version 2.0 (the "License"); you may +## not use this file except in compliance with the License. +## You may obtain a copy of the License at +## +## http://www.apache.org/licenses/LICENSE-2.0 +## +## Unless required by applicable law or agreed to in writing, software +## distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +## WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +## See the License for the specific language governing permissions and +## limitations under the License. +## + +PROJECT_DIR=build +TOOLS=../../../tools +PROJECT_NAME=$(basename $PWD) + +INFILE=${PROJECT_DIR}/${PROJECT_NAME}.hex +OUTBASE=${PROJECT_DIR}/${PROJECT_NAME}_crc +CRCBIN=${OUTBASE}.bin + +# The makefile generated by progen already converts output to both bin and hex. + +# Only execute the post build script if the input is newer than output, or the +# output doesn't exist. +if [[ "$INFILE" -nt "$CRCBIN" ]]; then + python "${TOOLS}/post_build_script.py" "$INFILE" "$OUTBASE" +fi + diff --git a/tools/pre_build_script.sh b/tools/pre_build_script.sh index bc640a155..5236a639a 100755 --- a/tools/pre_build_script.sh +++ b/tools/pre_build_script.sh @@ -1,7 +1,7 @@ #!/bin/bash -e # # DAPLink Interface Firmware -# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved +# Copyright (c) 2009-2019, ARM Limited, All Rights Reserved # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -17,11 +17,10 @@ # limitations under the License. # -export TOOLS=../../../tools -export DIR=../../../source/daplink -# Create dsion_git_tmpl.txt ${DIR}\version_git.h +TOOLS=../../../tools +DIR=../../../source/daplink # python --version # Run python script to delete default version_git.h and create the real one -python ${TOOLS}/pre_build_script.py +python ${TOOLS}/pre_build_script.py --version_git_dir=${DIR} From 968544a55679c12a9996327f0367a2ab6b9f8805 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Thu, 28 Nov 2019 16:38:29 -0600 Subject: [PATCH 053/617] lpc11u35 gcc support. --- records/hic_hal/lpc11u35.yaml | 8 + source/hic_hal/nxp/lpc11u35/daplink_addr.h | 6 +- source/hic_hal/nxp/lpc11u35/gcc/lpc11u35.ld | 235 +++++++++++++++ .../nxp/lpc11u35/gcc/startup_LPC11Uxx.S | 284 ++++++++++++++++++ source/hic_hal/nxp/lpc11u35/usbd_LPC11Uxx.c | 13 +- 5 files changed, 541 insertions(+), 5 deletions(-) create mode 100644 source/hic_hal/nxp/lpc11u35/gcc/lpc11u35.ld create mode 100644 source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11Uxx.S diff --git a/records/hic_hal/lpc11u35.yaml b/records/hic_hal/lpc11u35.yaml index 66e4fdb2a..4286ffa1a 100644 --- a/records/hic_hal/lpc11u35.yaml +++ b/records/hic_hal/lpc11u35.yaml @@ -28,3 +28,11 @@ tool_specific: sources: hic_hal: - source/hic_hal/nxp/lpc11u35/armcc + make_gcc_arm: + linker_file: + - source/hic_hal/nxp/lpc11u35/gcc/lpc11u35.ld + includes: + - source/hic_hal/nxp/lpc11u35/gcc + sources: + hic_hal: + - source/hic_hal/nxp/lpc11u35/gcc diff --git a/source/hic_hal/nxp/lpc11u35/daplink_addr.h b/source/hic_hal/nxp/lpc11u35/daplink_addr.h index 0b4b965dd..6db79e769 100644 --- a/source/hic_hal/nxp/lpc11u35/daplink_addr.h +++ b/source/hic_hal/nxp/lpc11u35/daplink_addr.h @@ -1,6 +1,6 @@ /** * @file daplink_addr.h - * @brief + * @brief * * DAPLink Interface Firmware * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved @@ -63,6 +63,10 @@ #define DAPLINK_SECTOR_SIZE 0x00000100 #define DAPLINK_MIN_WRITE_SIZE 0x00000100 +/* USB RAM */ +#define DAPLINK_USB_RAM_START 0x20004000 +#define DAPLINK_USB_RAM_SIZE 0x00000800 + /* Current build */ #if defined(DAPLINK_BL) diff --git a/source/hic_hal/nxp/lpc11u35/gcc/lpc11u35.ld b/source/hic_hal/nxp/lpc11u35/gcc/lpc11u35.ld new file mode 100644 index 000000000..7922d37e8 --- /dev/null +++ b/source/hic_hal/nxp/lpc11u35/gcc/lpc11u35.ld @@ -0,0 +1,235 @@ +/** + * @file daplink.ld + * @brief + * + * DAPLink Interface Firmware + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * Copyright (c) 2019, ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "daplink_addr.h" + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = DAPLINK_ROM_APP_START, LENGTH = 0x400 + m_text (RX) : ORIGIN = DAPLINK_ROM_APP_START + 0x400, LENGTH = DAPLINK_ROM_APP_SIZE - 0x400 + m_cfgrom (RW) : ORIGIN = DAPLINK_ROM_CONFIG_USER_START, LENGTH = DAPLINK_ROM_CONFIG_USER_SIZE + m_data (RW) : ORIGIN = DAPLINK_RAM_APP_START, LENGTH = DAPLINK_RAM_APP_SIZE + m_cfgram (RW) : ORIGIN = DAPLINK_RAM_SHARED_START, LENGTH = DAPLINK_RAM_SHARED_SIZE + m_data_2 (RW) : ORIGIN = DAPLINK_RAM_APP2_START, LENGTH = DAPLINK_RAM_APP2_SIZE + m_usb_ram (RW) : ORIGIN = DAPLINK_USB_RAM_START, LENGTH = DAPLINK_USB_RAM_SIZE +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + FILL(0xffffffff) + . = ALIGN(4); + . += LENGTH(m_interrupts) - (. - ORIGIN(m_interrupts)); /* pad out to end of m_interrupts */ + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(RAM1) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + + /* unlike the other HICs, the LPC11U35 doesn't need to have the firmware image filled + * out to the end of memory since it doesn't use the DAPLink bootloader */ + + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + .cfgrom (NOLOAD) : + { + *(cfgrom) + } > m_cfgrom + + /* Uninitialized data section */ + + /* build .bss_2 first so we don't have to exclude any sections put in here from .bss */ + .bss_2 : + { + . = ALIGN(4); + *(.bss.dir_current) + *(.bss.mbr) + . = ALIGN(4); + } > m_data_2 + + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data_2 + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data_2 + + .cfgram (NOLOAD) : + { + *(cfgram) + } > m_cfgram + + .usbram (NOLOAD) : + { + . = ALIGN(4); + *(.usbram) + . = ALIGN(4); + } > m_usb_ram + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region overflowed with stack and heap") +} + diff --git a/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11Uxx.S b/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11Uxx.S new file mode 100644 index 000000000..0a3218338 --- /dev/null +++ b/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11Uxx.S @@ -0,0 +1,284 @@ +/** + * @file startup_LPC11Uxx.S + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long 0 + .long 0 + .long 0 + .long 0 /* Reserved*/ + .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ + .long DAPLINK_HIC_ID /* Compatibility*/ + .long DAPLINK_VERSION /* Version*/ + .long SVC_Handler /* SVCall Handler*/ + .long 0 + .long g_board_info /* Ptr to Board info, family info other target details*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* 32 External Interrupts*/ + .long FLEX_INT0_IRQHandler /* All GPIO pin can be routed to FLEX_INTx */ + .long FLEX_INT1_IRQHandler + .long FLEX_INT2_IRQHandler + .long FLEX_INT3_IRQHandler + .long FLEX_INT4_IRQHandler + .long FLEX_INT5_IRQHandler + .long FLEX_INT6_IRQHandler + .long FLEX_INT7_IRQHandler + .long GINT0_IRQHandler + .long GINT1_IRQHandler /* PIO0 (0:7) */ + .long Reserved1_IRQHandler /* Reserved */ + .long Reserved2_IRQHandler + .long Reserved3_IRQHandler + .long Reserved4_IRQHandler + .long SSP1_IRQHandler /* SSP1 */ + .long I2C_IRQHandler /* I2C */ + .long TIMER16_0_IRQHandler /* 16-bit Timer0 */ + .long TIMER16_1_IRQHandler /* 16-bit Timer1 */ + .long TIMER32_0_IRQHandler /* 32-bit Timer0 */ + .long TIMER32_1_IRQHandler /* 32-bit Timer1 */ + .long SSP0_IRQHandler /* SSP0 */ + .long UART_IRQHandler /* UART */ + .long USB_IRQHandler /* USB IRQ */ + .long USB_FIQHandler /* USB FIQ */ + .long ADC_IRQHandler /* A/D Converter */ + .long WDT_IRQHandler /* Watchdog timer */ + .long BOD_IRQHandler /* Brown Out Detect */ + .long FMC_IRQHandler /* IP2111 Flash Memory Controller */ + .long Reserved5_IRQHandler /* Reserved */ + .long Reserved6_IRQHandler /* Reserved */ + .long USBWakeup_IRQHandler /* USB wake up */ + .long Reserved7_IRQHandler /* Reserved */ + +#if defined(MBED_BOOTLOADER) + +// Set the CRP (Code Read Protection) configuration word at address 0x2FC to ensure that +// CRP is disabled. +#define CRP_KEY_ADDR (0x000002FC) +#define CRP_DISABLED (0xFFFFFFFF) + +1: // Fill up to CRP config word address. + .dcb.l ((CRP_KEY_ADDR - (1b - __isr_vector)) / 4) + +CRP_Key: + .long CRP_DISABLED + +#endif // MBED_BOOTLOADER + + .size __isr_vector, . - __isr_vector + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__isr_vector + str r1, [r0] + ldr r2, [r1] + msr msp, r2 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + + cpsie i /* Unmask interrupts */ +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler FLEX_INT0_IRQHandler /* All GPIO pin can be routed to FLEX_INTx */ + def_irq_handler FLEX_INT1_IRQHandler + def_irq_handler FLEX_INT2_IRQHandler + def_irq_handler FLEX_INT3_IRQHandler + def_irq_handler FLEX_INT4_IRQHandler + def_irq_handler FLEX_INT5_IRQHandler + def_irq_handler FLEX_INT6_IRQHandler + def_irq_handler FLEX_INT7_IRQHandler + def_irq_handler GINT0_IRQHandler + def_irq_handler GINT1_IRQHandler /* PIO0 (0:7) */ + def_irq_handler Reserved1_IRQHandler /* Reserved */ + def_irq_handler Reserved2_IRQHandler + def_irq_handler Reserved3_IRQHandler + def_irq_handler Reserved4_IRQHandler + def_irq_handler SSP1_IRQHandler /* SSP1 */ + def_irq_handler I2C_IRQHandler /* I2C */ + def_irq_handler TIMER16_0_IRQHandler /* 16-bit Timer0 */ + def_irq_handler TIMER16_1_IRQHandler /* 16-bit Timer1 */ + def_irq_handler TIMER32_0_IRQHandler /* 32-bit Timer0 */ + def_irq_handler TIMER32_1_IRQHandler /* 32-bit Timer1 */ + def_irq_handler SSP0_IRQHandler /* SSP0 */ + def_irq_handler UART_IRQHandler /* UART */ + def_irq_handler USB_IRQHandler /* USB IRQ */ + def_irq_handler USB_FIQHandler /* USB FIQ */ + def_irq_handler ADC_IRQHandler /* A/D Converter */ + def_irq_handler WDT_IRQHandler /* Watchdog timer */ + def_irq_handler BOD_IRQHandler /* Brown Out Detect */ + def_irq_handler FMC_IRQHandler /* IP2111 Flash Memory Controller */ + def_irq_handler Reserved5_IRQHandler /* Reserved */ + def_irq_handler Reserved6_IRQHandler /* Reserved */ + def_irq_handler USBWakeup_IRQHandler /* USB wake up */ + def_irq_handler Reserved7_IRQHandler /* Reserved */ + + .end diff --git a/source/hic_hal/nxp/lpc11u35/usbd_LPC11Uxx.c b/source/hic_hal/nxp/lpc11u35/usbd_LPC11Uxx.c index 1746e26d7..4ba78544b 100644 --- a/source/hic_hal/nxp/lpc11u35/usbd_LPC11Uxx.c +++ b/source/hic_hal/nxp/lpc11u35/usbd_LPC11Uxx.c @@ -50,7 +50,9 @@ typedef struct BUF_INFO { EP_BUF_INFO EPBufInfo[(USBD_EP_NUM + 1) * 2]; #if defined ( __CC_ARM ) || defined (__ARMCC_VERSION) -volatile U32 EPList[(USBD_EP_NUM + 1) * 2] __attribute__((at(EP_LIST_BASE))); +volatile U32 EPList[(USBD_EP_NUM + 1) * 2] __attribute__((at(EP_LIST_BASE))); +#elif defined ( __GNUC__ ) +volatile U32 EPList[(USBD_EP_NUM + 1) * 2] __attribute__((section(".usbram"))); #else #error "Unsupported compiler!" #endif @@ -143,13 +145,16 @@ void USBD_Connect(BOOL con) } +// Disable optimization of this function. It gets a "iteration 8 invokes undefined behavior +// [-Waggressive-loop-optimizations]" warning in gcc if optimisation is enabled, for the first +// loop where EPList[i] is written to disable EPs. +NO_OPTIMIZE_PRE /* * USB Device Reset Function * Called automatically on USB Device Reset * Return Value: None */ - -void USBD_Reset(void) +void NO_OPTIMIZE_INLINE USBD_Reset(void) { U32 i; U32 *ptr; @@ -177,7 +182,7 @@ void USBD_Reset(void) (1UL << 1) | /* EP0 IN intr enable */ (1UL << 31)); /* stat change int en */ } - +NO_OPTIMIZE_POST /* * USB Device Suspend Function From e04bd2bc5f6204db6d5d3f91fe1bafb70bd8dd89 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Mon, 18 Nov 2019 11:49:52 -0600 Subject: [PATCH 054/617] Updated remaining HICs for gcc. --- records/hic_hal/k26f.yaml | 8 + records/hic_hal/kl26z.yaml | 8 + records/hic_hal/lpc4322.yaml | 6 + records/hic_hal/m48ssidae.yaml | 6 + records/hic_hal/max32620.yaml | 6 + records/hic_hal/max32625.yaml | 6 + records/hic_hal/sam3u2c.yaml | 6 + records/hic_hal/stm32f103xb.yaml | 6 + .../hic_hal/atmel/sam3u2c/gcc/startup_SAM3U.S | 303 ++++++++++++ .../freescale/k26f/gcc/startup_MK26F18.S | 440 +++++++++++++++++ .../freescale/kl26z/gcc/startup_MKL26Z4.S | 288 +++++++++++ .../maxim/max32620/gcc/startup_MAX32620.S | 341 +++++++++++++ .../maxim/max32625/gcc/startup_MAX32625.S | 347 +++++++++++++ .../m48ssidae/StdDriver/src/m480_rtc.c | 4 +- .../nuvoton/m48ssidae/gcc/startup_M480.S | 461 ++++++++++++++++++ .../hic_hal/nxp/lpc4322/gcc/startup_LPC43xx.S | 363 ++++++++++++++ source/hic_hal/nxp/lpc4322/system_LPC43xx.c | 3 - .../stm32f103xb/gcc/startup_stm32f103xb.S | 329 +++++++++++++ 18 files changed, 2926 insertions(+), 5 deletions(-) create mode 100644 source/hic_hal/atmel/sam3u2c/gcc/startup_SAM3U.S create mode 100644 source/hic_hal/freescale/k26f/gcc/startup_MK26F18.S create mode 100644 source/hic_hal/freescale/kl26z/gcc/startup_MKL26Z4.S create mode 100644 source/hic_hal/maxim/max32620/gcc/startup_MAX32620.S create mode 100644 source/hic_hal/maxim/max32625/gcc/startup_MAX32625.S create mode 100644 source/hic_hal/nuvoton/m48ssidae/gcc/startup_M480.S create mode 100644 source/hic_hal/nxp/lpc4322/gcc/startup_LPC43xx.S create mode 100644 source/hic_hal/stm32/stm32f103xb/gcc/startup_stm32f103xb.S diff --git a/records/hic_hal/k26f.yaml b/records/hic_hal/k26f.yaml index 6d18f23fe..100c715dd 100644 --- a/records/hic_hal/k26f.yaml +++ b/records/hic_hal/k26f.yaml @@ -52,3 +52,11 @@ tool_specific: sources: hic_hal: - source/hic_hal/freescale/k26f/armcc + make_gcc_arm: + linker_file: + - source/hic_hal/freescale/kinetis.ld + includes: + - source/hic_hal/freescale/k26f/gcc + sources: + hic_hal: + - source/hic_hal/freescale/k26f/gcc diff --git a/records/hic_hal/kl26z.yaml b/records/hic_hal/kl26z.yaml index 98596443e..41fa67b96 100644 --- a/records/hic_hal/kl26z.yaml +++ b/records/hic_hal/kl26z.yaml @@ -39,3 +39,11 @@ tool_specific: sources: hic_hal: - source/hic_hal/freescale/kl26z/armcc + make_gcc_arm: + linker_file: + - source/hic_hal/freescale/kinetis.ld + includes: + - source/hic_hal/freescale/kl26z/gcc + sources: + hic_hal: + - source/hic_hal/freescale/kl26z/gcc diff --git a/records/hic_hal/lpc4322.yaml b/records/hic_hal/lpc4322.yaml index f019a96f7..d3ce8ffc7 100644 --- a/records/hic_hal/lpc4322.yaml +++ b/records/hic_hal/lpc4322.yaml @@ -30,3 +30,9 @@ tool_specific: sources: hic_hal: - source/hic_hal/nxp/lpc4322/armcc + make_gcc_arm: + includes: + - source/hic_hal/nxp/lpc4322/gcc + sources: + hic_hal: + - source/hic_hal/nxp/lpc4322/gcc diff --git a/records/hic_hal/m48ssidae.yaml b/records/hic_hal/m48ssidae.yaml index 5c81d7db6..c21fc8c36 100644 --- a/records/hic_hal/m48ssidae.yaml +++ b/records/hic_hal/m48ssidae.yaml @@ -34,3 +34,9 @@ tool_specific: sources: hic_hal: - source/hic_hal/nuvoton/m48ssidae/armcc + make_gcc_arm: + includes: + - source/hic_hal/nuvoton/m48ssidae/gcc + sources: + hic_hal: + - source/hic_hal/nuvoton/m48ssidae/gcc diff --git a/records/hic_hal/max32620.yaml b/records/hic_hal/max32620.yaml index 2bd130c93..b24e1149d 100644 --- a/records/hic_hal/max32620.yaml +++ b/records/hic_hal/max32620.yaml @@ -28,3 +28,9 @@ tool_specific: sources: hic_hal: - source/hic_hal/maxim/max32620/armcc + make_gcc_arm: + includes: + - source/hic_hal/maxim/max32620/gcc + sources: + hic_hal: + - source/hic_hal/maxim/max32620/gcc diff --git a/records/hic_hal/max32625.yaml b/records/hic_hal/max32625.yaml index 669ded18a..b4d806364 100644 --- a/records/hic_hal/max32625.yaml +++ b/records/hic_hal/max32625.yaml @@ -28,3 +28,9 @@ tool_specific: sources: hic_hal: - source/hic_hal/maxim/max32625/armcc + make_gcc_arm: + includes: + - source/hic_hal/maxim/max32625/gcc + sources: + hic_hal: + - source/hic_hal/maxim/max32625/gcc diff --git a/records/hic_hal/sam3u2c.yaml b/records/hic_hal/sam3u2c.yaml index 6ce1eae72..f726b4188 100644 --- a/records/hic_hal/sam3u2c.yaml +++ b/records/hic_hal/sam3u2c.yaml @@ -31,3 +31,9 @@ tool_specific: sources: hic_hal: - source/hic_hal/atmel/sam3u2c/armcc + make_gcc_arm: + includes: + - source/hic_hal/atmel/sam3u2c/gcc + sources: + hic_hal: + - source/hic_hal/atmel/sam3u2c/gcc diff --git a/records/hic_hal/stm32f103xb.yaml b/records/hic_hal/stm32f103xb.yaml index 58fc80236..991c5ce98 100644 --- a/records/hic_hal/stm32f103xb.yaml +++ b/records/hic_hal/stm32f103xb.yaml @@ -37,3 +37,9 @@ tool_specific: sources: hic_hal: - source/hic_hal/stm32/stm32f103xb/armcc + make_gcc_arm: + includes: + - source/hic_hal/stm32/stm32f103xb/gcc + sources: + hic_hal: + - source/hic_hal/stm32/stm32f103xb/gcc diff --git a/source/hic_hal/atmel/sam3u2c/gcc/startup_SAM3U.S b/source/hic_hal/atmel/sam3u2c/gcc/startup_SAM3U.S new file mode 100644 index 000000000..54afeb91a --- /dev/null +++ b/source/hic_hal/atmel/sam3u2c/gcc/startup_SAM3U.S @@ -0,0 +1,303 @@ +/** + * @file startup_MK20D5.s + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long 0 /* Reserved*/ + .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ + .long DAPLINK_HIC_ID /* Compatibility*/ + .long DAPLINK_VERSION /* Version*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long g_board_info /* Ptr to Board info, family info other target details*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long SUPC_IRQHandler /* 0: Supply Controller */ + .long RSTC_IRQHandler /* 1: Reset Controller */ + .long RTC_IRQHandler /* 2: Real Time Clock */ + .long RTT_IRQHandler /* 3: Real Time Timer */ + .long WDT_IRQHandler /* 4: Watchdog Timer */ + .long PMC_IRQHandler /* 5: Power Management Controller */ + .long EEFC0_IRQHandler /* 6: Enhanced Embedded Flash Controller 0 */ + .long EEFC1_IRQHandler /* 7: Enhanced Embedded Flash Controller 1 */ + .long UART_IRQHandler /* 8: UART */ + .long SMC_IRQHandler /* 9: Static Memory Controller */ + .long PIOA_IRQHandler /* 10: Parallel I/O Controller A */ + .long PIOB_IRQHandler /* 11: Parallel I/O Controller B */ + .long PIOC_IRQHandler /* 12: Parallel I/O Controller C */ + .long USART0_IRQHandler /* 13: USART 0 */ + .long USART1_IRQHandler /* 14: USART 1 */ + .long USART2_IRQHandler /* 15: USART 2 */ + .long USART3_IRQHandler /* 16: USART 3 */ + .long HSMCI_IRQHandler /* 17: High Speed Multimedia Card Interface */ + .long TWI0_IRQHandler /* 18: Two-wire Interface 0 */ + .long TWI1_IRQHandler /* 19: Two-wire Interface 1 */ + .long SPI_IRQHandler /* 20: Synchronous Peripheral Interface */ + .long SSC_IRQHandler /* 21: Synchronous Serial Controller */ + .long TC0_IRQHandler /* 22: Timer Counter 0 */ + .long TC1_IRQHandler /* 23: Timer Counter 1 */ + .long TC2_IRQHandler /* 24: Timer Counter 2 */ + .long PWM_IRQHandler /* 25: Pulse Width Modulation Controller */ + .long ADC12B_IRQHandler /* 26: 12-bit ADC Controller */ + .long ADC_IRQHandler /* 27: 10-bit ADC Controller */ + .long DMAC_IRQHandler /* 28: DMA Controller */ + .long UDPHS_IRQHandler /* 29: USB Device High Speed */ + + .size __isr_vector, . - __isr_vector + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__isr_vector + str r1, [r0] + ldr r2, [r1] + msr msp, r2 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + + cpsie i /* Unmask interrupts */ +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + ldr r0,=MemManage_Handler + bx r0 + .size MemManage_Handler, . - MemManage_Handler + + .align 1 + .thumb_func + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + ldr r0,=BusFault_Handler + bx r0 + .size BusFault_Handler, . - BusFault_Handler + + .align 1 + .thumb_func + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + ldr r0,=UsageFault_Handler + bx r0 + .size UsageFault_Handler, . - UsageFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + ldr r0,=DebugMon_Handler + bx r0 + .size DebugMon_Handler, . - DebugMon_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler SUPC_IRQHandler /* 0: Supply Controller */ + def_irq_handler RSTC_IRQHandler /* 1: Reset Controller */ + def_irq_handler RTC_IRQHandler /* 2: Real Time Clock */ + def_irq_handler RTT_IRQHandler /* 3: Real Time Timer */ + def_irq_handler WDT_IRQHandler /* 4: Watchdog Timer */ + def_irq_handler PMC_IRQHandler /* 5: Power Management Controller */ + def_irq_handler EEFC0_IRQHandler /* 6: Enhanced Embedded Flash Controller 0 */ + def_irq_handler EEFC1_IRQHandler /* 7: Enhanced Embedded Flash Controller 1 */ + def_irq_handler UART_IRQHandler /* 8: UART */ + def_irq_handler SMC_IRQHandler /* 9: Static Memory Controller */ + def_irq_handler PIOA_IRQHandler /* 10: Parallel I/O Controller A */ + def_irq_handler PIOB_IRQHandler /* 11: Parallel I/O Controller B */ + def_irq_handler PIOC_IRQHandler /* 12: Parallel I/O Controller C */ + def_irq_handler USART0_IRQHandler /* 13: USART 0 */ + def_irq_handler USART1_IRQHandler /* 14: USART 1 */ + def_irq_handler USART2_IRQHandler /* 15: USART 2 */ + def_irq_handler USART3_IRQHandler /* 16: USART 3 */ + def_irq_handler HSMCI_IRQHandler /* 17: High Speed Multimedia Card Interface */ + def_irq_handler TWI0_IRQHandler /* 18: Two-wire Interface 0 */ + def_irq_handler TWI1_IRQHandler /* 19: Two-wire Interface 1 */ + def_irq_handler SPI_IRQHandler /* 20: Synchronous Peripheral Interface */ + def_irq_handler SSC_IRQHandler /* 21: Synchronous Serial Controller */ + def_irq_handler TC0_IRQHandler /* 22: Timer Counter 0 */ + def_irq_handler TC1_IRQHandler /* 23: Timer Counter 1 */ + def_irq_handler TC2_IRQHandler /* 24: Timer Counter 2 */ + def_irq_handler PWM_IRQHandler /* 25: Pulse Width Modulation Controller */ + def_irq_handler ADC12B_IRQHandler /* 26: 12-bit ADC Controller */ + def_irq_handler ADC_IRQHandler /* 27: 10-bit ADC Controller */ + def_irq_handler DMAC_IRQHandler /* 28: DMA Controller */ + def_irq_handler UDPHS_IRQHandler /* 29: USB Device High Speed */ + + .end diff --git a/source/hic_hal/freescale/k26f/gcc/startup_MK26F18.S b/source/hic_hal/freescale/k26f/gcc/startup_MK26F18.S new file mode 100644 index 000000000..d3cca0fc9 --- /dev/null +++ b/source/hic_hal/freescale/k26f/gcc/startup_MK26F18.S @@ -0,0 +1,440 @@ +/* ------------------------------------------------------------------------- */ +/* @file: startup_MK26F18.s */ +/* @purpose: CMSIS Cortex-M4 Core Device Startup File */ +/* MK26F18 */ +/* @version: 2.0 */ +/* @date: 2015-3-25 */ +/* @build: b180801 */ +/* ------------------------------------------------------------------------- */ +/* */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2018 NXP */ +/* */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long 0 /* Reserved*/ + .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ + .long DAPLINK_HIC_ID /* Compatibility*/ + .long DAPLINK_VERSION /* Version*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long g_board_info /* Ptr to Board info, family info other target details*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long DMA0_DMA16_IRQHandler /* DMA Channel 0, 16 Transfer Complete*/ + .long DMA1_DMA17_IRQHandler /* DMA Channel 1, 17 Transfer Complete*/ + .long DMA2_DMA18_IRQHandler /* DMA Channel 2, 18 Transfer Complete*/ + .long DMA3_DMA19_IRQHandler /* DMA Channel 3, 19 Transfer Complete*/ + .long DMA4_DMA20_IRQHandler /* DMA Channel 4, 20 Transfer Complete*/ + .long DMA5_DMA21_IRQHandler /* DMA Channel 5, 21 Transfer Complete*/ + .long DMA6_DMA22_IRQHandler /* DMA Channel 6, 22 Transfer Complete*/ + .long DMA7_DMA23_IRQHandler /* DMA Channel 7, 23 Transfer Complete*/ + .long DMA8_DMA24_IRQHandler /* DMA Channel 8, 24 Transfer Complete*/ + .long DMA9_DMA25_IRQHandler /* DMA Channel 9, 25 Transfer Complete*/ + .long DMA10_DMA26_IRQHandler /* DMA Channel 10, 26 Transfer Complete*/ + .long DMA11_DMA27_IRQHandler /* DMA Channel 11, 27 Transfer Complete*/ + .long DMA12_DMA28_IRQHandler /* DMA Channel 12, 28 Transfer Complete*/ + .long DMA13_DMA29_IRQHandler /* DMA Channel 13, 29 Transfer Complete*/ + .long DMA14_DMA30_IRQHandler /* DMA Channel 14, 30 Transfer Complete*/ + .long DMA15_DMA31_IRQHandler /* DMA Channel 15, 31 Transfer Complete*/ + .long DMA_Error_IRQHandler /* DMA Error Interrupt*/ + .long MCM_IRQHandler /* Normal Interrupt*/ + .long FTFE_IRQHandler /* FTFE Command complete interrupt*/ + .long Read_Collision_IRQHandler /* Read Collision Interrupt*/ + .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning*/ + .long LLWU_IRQHandler /* Low Leakage Wakeup Unit*/ + .long WDOG_EWM_IRQHandler /* WDOG Interrupt*/ + .long RNG_IRQHandler /* RNG Interrupt*/ + .long I2C0_IRQHandler /* I2C0 interrupt*/ + .long I2C1_IRQHandler /* I2C1 interrupt*/ + .long SPI0_IRQHandler /* SPI0 Interrupt*/ + .long SPI1_IRQHandler /* SPI1 Interrupt*/ + .long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt*/ + .long I2S0_Rx_IRQHandler /* I2S0 receive interrupt*/ + .long Reserved46_IRQHandler /* Reserved interrupt 46*/ + .long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt*/ + .long UART0_ERR_IRQHandler /* UART0 Error interrupt*/ + .long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt*/ + .long UART1_ERR_IRQHandler /* UART1 Error interrupt*/ + .long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt*/ + .long UART2_ERR_IRQHandler /* UART2 Error interrupt*/ + .long UART3_RX_TX_IRQHandler /* UART3 Receive/Transmit interrupt*/ + .long UART3_ERR_IRQHandler /* UART3 Error interrupt*/ + .long ADC0_IRQHandler /* ADC0 interrupt*/ + .long CMP0_IRQHandler /* CMP0 interrupt*/ + .long CMP1_IRQHandler /* CMP1 interrupt*/ + .long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt*/ + .long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt*/ + .long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt*/ + .long CMT_IRQHandler /* CMT interrupt*/ + .long RTC_IRQHandler /* RTC interrupt*/ + .long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/ + .long PIT0_IRQHandler /* PIT timer channel 0 interrupt*/ + .long PIT1_IRQHandler /* PIT timer channel 1 interrupt*/ + .long PIT2_IRQHandler /* PIT timer channel 2 interrupt*/ + .long PIT3_IRQHandler /* PIT timer channel 3 interrupt*/ + .long PDB0_IRQHandler /* PDB0 Interrupt*/ + .long USB0_IRQHandler /* USB0 interrupt*/ + .long USBDCD_IRQHandler /* USBDCD Interrupt*/ + .long Reserved71_IRQHandler /* Reserved interrupt 71*/ + .long DAC0_IRQHandler /* DAC0 interrupt*/ + .long MCG_IRQHandler /* MCG Interrupt*/ + .long LPTMR0_IRQHandler /* LPTimer interrupt*/ + .long PORTA_IRQHandler /* Port A interrupt*/ + .long PORTB_IRQHandler /* Port B interrupt*/ + .long PORTC_IRQHandler /* Port C interrupt*/ + .long PORTD_IRQHandler /* Port D interrupt*/ + .long PORTE_IRQHandler /* Port E interrupt*/ + .long SWI_IRQHandler /* Software interrupt*/ + .long SPI2_IRQHandler /* SPI2 Interrupt*/ + .long UART4_RX_TX_IRQHandler /* UART4 Receive/Transmit interrupt*/ + .long UART4_ERR_IRQHandler /* UART4 Error interrupt*/ + .long Reserved84_IRQHandler /* Reserved interrupt 84*/ + .long Reserved85_IRQHandler /* Reserved interrupt 85*/ + .long CMP2_IRQHandler /* CMP2 interrupt*/ + .long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt*/ + .long DAC1_IRQHandler /* DAC1 interrupt*/ + .long ADC1_IRQHandler /* ADC1 interrupt*/ + .long I2C2_IRQHandler /* I2C2 interrupt*/ + .long CAN0_ORed_Message_buffer_IRQHandler /* CAN0 OR'd message buffers interrupt*/ + .long CAN0_Bus_Off_IRQHandler /* CAN0 bus off interrupt*/ + .long CAN0_Error_IRQHandler /* CAN0 error interrupt*/ + .long CAN0_Tx_Warning_IRQHandler /* CAN0 Tx warning interrupt*/ + .long CAN0_Rx_Warning_IRQHandler /* CAN0 Rx warning interrupt*/ + .long CAN0_Wake_Up_IRQHandler /* CAN0 wake up interrupt*/ + .long SDHC_IRQHandler /* SDHC interrupt*/ + .long Reserved98_IRQHandler /* Reserved Interrupt 98*/ + .long Reserved99_IRQHandler /* Reserved Interrupt 99*/ + .long Reserved100_IRQHandler /* Reserved Interrupt 100*/ + .long Reserved101_IRQHandler /* Reserved Interrupt 101*/ + .long LPUART0_IRQHandler /* LPUART0 status/error interrupt*/ + .long TSI0_IRQHandler /* TSI0 interrupt*/ + .long TPM1_IRQHandler /* TPM1 fault, overflow and channels interrupt*/ + .long TPM2_IRQHandler /* TPM2 fault, overflow and channels interrupt*/ + .long USBHSDCD_IRQHandler /* USBHSDCD, USBHS Phy Interrupt*/ + .long I2C3_IRQHandler /* I2C3 interrupt*/ + .long CMP3_IRQHandler /* CMP3 interrupt*/ + .long USBHS_IRQHandler /* USB high speed OTG interrupt*/ + .long CAN1_ORed_Message_buffer_IRQHandler /* CAN1 OR'd message buffers interrupt*/ + .long CAN1_Bus_Off_IRQHandler /* CAN1 bus off interrupt*/ + .long CAN1_Error_IRQHandler /* CAN1 error interrupt*/ + .long CAN1_Tx_Warning_IRQHandler /* CAN1 Tx warning interrupt*/ + .long CAN1_Rx_Warning_IRQHandler /* CAN1 Rx warning interrupt*/ + .long CAN1_Wake_Up_IRQHandler /* CAN1 wake up interrupt*/ + + .size __isr_vector, . - __isr_vector + +/* Flash Configuration */ + .section .FlashConfig, "a" + .long 0xFFFFFFFF + .long 0xFFFFFFFF + .long 0xFFFFFFFF + .long 0xFFFFFFFE + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__isr_vector + str r1, [r0] + ldr r2, [r1] + msr msp, r2 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * __noncachedata_start__/__noncachedata_end__ : none cachable region + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif +#ifdef __STARTUP_INITIALIZE_NONCACHEDATA + ldr r2, =__noncachedata_start__ + ldr r3, =__noncachedata_init_end__ +#if 1 +.LC2: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC2 +#else + subs r3, r2 + ble .LC3 +.LC2: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC2 +.LC3: +#endif +/* zero inited ncache section initialization */ + ldr r3, =__noncachedata_end__ + movs r0,0 +.LC4: + cmp r2,r3 + itt lt + strlt r0,[r2],#4 + blt .LC4 +#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */ + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC5: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC5 +#endif /* __STARTUP_CLEAR_BSS */ + + cpsie i /* Unmask interrupts */ +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler DMA0_DMA16_IRQHandler + def_irq_handler DMA1_DMA17_IRQHandler + def_irq_handler DMA2_DMA18_IRQHandler + def_irq_handler DMA3_DMA19_IRQHandler + def_irq_handler DMA4_DMA20_IRQHandler + def_irq_handler DMA5_DMA21_IRQHandler + def_irq_handler DMA6_DMA22_IRQHandler + def_irq_handler DMA7_DMA23_IRQHandler + def_irq_handler DMA8_DMA24_IRQHandler + def_irq_handler DMA9_DMA25_IRQHandler + def_irq_handler DMA10_DMA26_IRQHandler + def_irq_handler DMA11_DMA27_IRQHandler + def_irq_handler DMA12_DMA28_IRQHandler + def_irq_handler DMA13_DMA29_IRQHandler + def_irq_handler DMA14_DMA30_IRQHandler + def_irq_handler DMA15_DMA31_IRQHandler + def_irq_handler DMA_Error_IRQHandler + def_irq_handler MCM_IRQHandler + def_irq_handler FTFE_IRQHandler + def_irq_handler Read_Collision_IRQHandler + def_irq_handler LVD_LVW_IRQHandler + def_irq_handler LLWU_IRQHandler + def_irq_handler WDOG_EWM_IRQHandler + def_irq_handler RNG_IRQHandler + def_irq_handler I2C0_IRQHandler + def_irq_handler I2C1_IRQHandler + def_irq_handler SPI0_IRQHandler + def_irq_handler SPI1_IRQHandler + def_irq_handler I2S0_Tx_IRQHandler + def_irq_handler I2S0_Rx_IRQHandler + def_irq_handler Reserved46_IRQHandler + def_irq_handler UART0_RX_TX_IRQHandler + def_irq_handler UART0_ERR_IRQHandler + def_irq_handler UART1_RX_TX_IRQHandler + def_irq_handler UART1_ERR_IRQHandler + def_irq_handler UART2_RX_TX_IRQHandler + def_irq_handler UART2_ERR_IRQHandler + def_irq_handler UART3_RX_TX_IRQHandler + def_irq_handler UART3_ERR_IRQHandler + def_irq_handler ADC0_IRQHandler + def_irq_handler CMP0_IRQHandler + def_irq_handler CMP1_IRQHandler + def_irq_handler FTM0_IRQHandler + def_irq_handler FTM1_IRQHandler + def_irq_handler FTM2_IRQHandler + def_irq_handler CMT_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler RTC_Seconds_IRQHandler + def_irq_handler PIT0_IRQHandler + def_irq_handler PIT1_IRQHandler + def_irq_handler PIT2_IRQHandler + def_irq_handler PIT3_IRQHandler + def_irq_handler PDB0_IRQHandler + def_irq_handler USB0_IRQHandler + def_irq_handler USBDCD_IRQHandler + def_irq_handler Reserved71_IRQHandler + def_irq_handler DAC0_IRQHandler + def_irq_handler MCG_IRQHandler + def_irq_handler LPTMR0_IRQHandler + def_irq_handler PORTA_IRQHandler + def_irq_handler PORTB_IRQHandler + def_irq_handler PORTC_IRQHandler + def_irq_handler PORTD_IRQHandler + def_irq_handler PORTE_IRQHandler + def_irq_handler SWI_IRQHandler + def_irq_handler SPI2_IRQHandler + def_irq_handler UART4_RX_TX_IRQHandler + def_irq_handler UART4_ERR_IRQHandler + def_irq_handler Reserved84_IRQHandler + def_irq_handler Reserved85_IRQHandler + def_irq_handler CMP2_IRQHandler + def_irq_handler FTM3_IRQHandler + def_irq_handler DAC1_IRQHandler + def_irq_handler ADC1_IRQHandler + def_irq_handler I2C2_IRQHandler + def_irq_handler CAN0_ORed_Message_buffer_IRQHandler + def_irq_handler CAN0_Bus_Off_IRQHandler + def_irq_handler CAN0_Error_IRQHandler + def_irq_handler CAN0_Tx_Warning_IRQHandler + def_irq_handler CAN0_Rx_Warning_IRQHandler + def_irq_handler CAN0_Wake_Up_IRQHandler + def_irq_handler SDHC_IRQHandler + def_irq_handler Reserved98_IRQHandler + def_irq_handler Reserved99_IRQHandler + def_irq_handler Reserved100_IRQHandler + def_irq_handler Reserved101_IRQHandler + def_irq_handler LPUART0_IRQHandler + def_irq_handler TSI0_IRQHandler + def_irq_handler TPM1_IRQHandler + def_irq_handler TPM2_IRQHandler + def_irq_handler USBHSDCD_IRQHandler + def_irq_handler I2C3_IRQHandler + def_irq_handler CMP3_IRQHandler + def_irq_handler USBHS_IRQHandler + def_irq_handler CAN1_ORed_Message_buffer_IRQHandler + def_irq_handler CAN1_Bus_Off_IRQHandler + def_irq_handler CAN1_Error_IRQHandler + def_irq_handler CAN1_Tx_Warning_IRQHandler + def_irq_handler CAN1_Rx_Warning_IRQHandler + def_irq_handler CAN1_Wake_Up_IRQHandler + + .end diff --git a/source/hic_hal/freescale/kl26z/gcc/startup_MKL26Z4.S b/source/hic_hal/freescale/kl26z/gcc/startup_MKL26Z4.S new file mode 100644 index 000000000..1cac80a0d --- /dev/null +++ b/source/hic_hal/freescale/kl26z/gcc/startup_MKL26Z4.S @@ -0,0 +1,288 @@ +/* ------------------------------------------------------------------------- */ +/* @file: startup_MKL26Z4.s */ +/* @purpose: CMSIS Cortex-M0P Core Device Startup File */ +/* MKL26Z4 */ +/* @version: 1.8 */ +/* @date: 2015-7-29 */ +/* @build: b171205 */ +/* ------------------------------------------------------------------------- */ +/* */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2017 NXP */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted (subject to the limitations in the */ +/* disclaimer below) provided that the following conditions are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of the copyright holder nor the names of its */ +/* contributors may be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT */ +/* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED */ +/* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ +/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE */ +/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */ +/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */ +/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */ +/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE */ +/* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN */ +/* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv6-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ + .long DAPLINK_HIC_ID /* Compatibility*/ + .long DAPLINK_VERSION /* Version*/ + .long SVC_Handler /* SVCall Handler*/ + .long 0 /* Reserved*/ + .long g_board_info /* Ptr to Board info, family info other target details*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long DMA0_IRQHandler /* DMA channel 0 transfer complete and error interrupt*/ + .long DMA1_IRQHandler /* DMA channel 1 transfer complete and error interrupt*/ + .long DMA2_IRQHandler /* DMA channel 2 transfer complete and error interrupt*/ + .long DMA3_IRQHandler /* DMA channel 3 transfer complete and error interrupt*/ + .long Reserved20_IRQHandler /* Reserved interrupt*/ + .long FTFA_IRQHandler /* FTFA command complete and read collision*/ + .long LVD_LVW_IRQHandler /* Low-voltage detect, low-voltage warning*/ + .long LLWU_IRQHandler /* Low Leakage Wakeup*/ + .long I2C0_IRQHandler /* I2C0 interrupt*/ + .long I2C1_IRQHandler /* I2C1 interrupt*/ + .long SPI0_IRQHandler /* SPI0 single interrupt vector for all sources*/ + .long SPI1_IRQHandler /* SPI1 single interrupt vector for all sources*/ + .long UART0_IRQHandler /* UART0 status and error*/ + .long UART1_IRQHandler /* UART1 status and error*/ + .long UART2_IRQHandler /* UART2 status and error*/ + .long ADC0_IRQHandler /* ADC0 interrupt*/ + .long CMP0_IRQHandler /* CMP0 interrupt*/ + .long TPM0_IRQHandler /* TPM0 single interrupt vector for all sources*/ + .long TPM1_IRQHandler /* TPM1 single interrupt vector for all sources*/ + .long TPM2_IRQHandler /* TPM2 single interrupt vector for all sources*/ + .long RTC_IRQHandler /* RTC alarm interrupt*/ + .long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/ + .long PIT_IRQHandler /* PIT single interrupt vector for all channels*/ + .long I2S0_IRQHandler /* I2S0 Single interrupt vector for all sources*/ + .long USB0_IRQHandler /* USB0 OTG*/ + .long DAC0_IRQHandler /* DAC0 interrupt*/ + .long TSI0_IRQHandler /* TSI0 interrupt*/ + .long MCG_IRQHandler /* MCG interrupt*/ + .long LPTMR0_IRQHandler /* LPTMR0 interrupt*/ + .long Reserved45_IRQHandler /* Reserved interrupt*/ + .long PORTA_IRQHandler /* PORTA pin detect*/ + .long PORTC_PORTD_IRQHandler /* Single interrupt vector for PORTC and PORTD pin detect*/ + + .size __isr_vector, . - __isr_vector + +/* Flash Configuration */ + .section .FlashConfig, "a" + .long 0xFFFFFFFF + .long 0xFFFFFFFF + .long 0xFFFFFFFF + .long 0xFFFFFFFE + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__isr_vector + str r1, [r0] + ldr r2, [r1] + msr msp, r2 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .LC0 + +.LC1: + subs r3, 4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .LC1 +.LC0: + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + subs r2, r1 + ble .LC3 + + movs r0, 0 +.LC2: + str r0, [r1, r2] + subs r2, 4 + bge .LC2 +.LC3: +#endif + cpsie i /* Unmask interrupts */ +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + ldr r0, =DefaultISR + bx r0 + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler DMA0_IRQHandler + def_irq_handler DMA1_IRQHandler + def_irq_handler DMA2_IRQHandler + def_irq_handler DMA3_IRQHandler + def_irq_handler Reserved20_IRQHandler + def_irq_handler FTFA_IRQHandler + def_irq_handler LVD_LVW_IRQHandler + def_irq_handler LLWU_IRQHandler + def_irq_handler I2C0_IRQHandler + def_irq_handler I2C1_IRQHandler + def_irq_handler SPI0_IRQHandler + def_irq_handler SPI1_IRQHandler + def_irq_handler UART0_IRQHandler + def_irq_handler UART1_IRQHandler + def_irq_handler UART2_IRQHandler + def_irq_handler ADC0_IRQHandler + def_irq_handler CMP0_IRQHandler + def_irq_handler TPM0_IRQHandler + def_irq_handler TPM1_IRQHandler + def_irq_handler TPM2_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler RTC_Seconds_IRQHandler + def_irq_handler PIT_IRQHandler + def_irq_handler I2S0_IRQHandler + def_irq_handler USB0_IRQHandler + def_irq_handler DAC0_IRQHandler + def_irq_handler TSI0_IRQHandler + def_irq_handler MCG_IRQHandler + def_irq_handler LPTMR0_IRQHandler + def_irq_handler Reserved45_IRQHandler + def_irq_handler PORTA_IRQHandler + def_irq_handler PORTC_PORTD_IRQHandler + + .end diff --git a/source/hic_hal/maxim/max32620/gcc/startup_MAX32620.S b/source/hic_hal/maxim/max32620/gcc/startup_MAX32620.S new file mode 100644 index 000000000..ee1fc680b --- /dev/null +++ b/source/hic_hal/maxim/max32620/gcc/startup_MAX32620.S @@ -0,0 +1,341 @@ +/** + * @file startup_MK20D5.s + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long 0 /* Reserved*/ + .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ + .long DAPLINK_HIC_ID /* Compatibility*/ + .long DAPLINK_VERSION /* Version*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long g_board_info /* Ptr to Board info, family info other target details*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long CLKMAN_IRQHandler /* 16:01 CLKMAN */ + .long PWRMAN_IRQHandler /* 17:02 PWRMAN */ + .long FLC_IRQHandler /* 18:03 Flash Controller */ + .long RTC0_IRQHandler /* 19:04 RTC INT0 */ + .long RTC1_IRQHandler /* 20:05 RTC INT1 */ + .long RTC2_IRQHandler /* 21:06 RTC INT2 */ + .long RTC3_IRQHandler /* 22:07 RTC INT3 */ + .long PMU_IRQHandler /* 23:08 PMU */ + .long USB_IRQHandler /* 24:09 USB */ + .long AES_IRQHandler /* 25:10 AES */ + .long MAA_IRQHandler /* 26:11 MAA */ + .long WDT0_IRQHandler /* 27:12 WATCHDOG0 */ + .long WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */ + .long WDT1_IRQHandler /* 29:14 WATCHDOG1 */ + .long WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */ + .long GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */ + .long GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */ + .long GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */ + .long GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */ + .long GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */ + .long GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */ + .long GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */ + .long TMR0_IRQHandler /* 38:23 Timer32-0 */ + .long TMR16_0_IRQHandler /* 39:24 Timer16-s0 */ + .long TMR1_IRQHandler /* 40:25 Timer32-1 */ + .long TMR16_1_IRQHandler /* 41:26 Timer16-s1 */ + .long TMR2_IRQHandler /* 42:27 Timer32-2 */ + .long TMR16_2_IRQHandler /* 43:28 Timer16-s2 */ + .long TMR3_IRQHandler /* 44:29 Timer32-3 */ + .long TMR16_3_IRQHandler /* 45:30 Timer16-s3 */ + .long TMR4_IRQHandler /* 46:31 Timer32-4 */ + .long TMR16_4_IRQHandler /* 47:32 Timer16-s4 */ + .long TMR5_IRQHandler /* 48:33 Timer32-5 */ + .long TMR16_5_IRQHandler /* 49:34 Timer16-s5 */ + .long UART0_IRQHandler /* 50:35 UART0 */ + .long UART1_IRQHandler /* 51:36 UART1 */ + .long UART2_IRQHandler /* 52:37 UART0 */ + .long UART3_IRQHandler /* 53:38 UART1 */ + .long PT_IRQHandler /* 54:39 PT */ + .long I2CM0_IRQHandler /* 55:40 I2C Master 0 */ + .long I2CM1_IRQHandler /* 56:41 I2C Master 1 */ + .long I2CM2_IRQHandler /* 57:42 I2C Master 2 */ + .long I2CS_IRQHandler /* 58:43 I2C Slave */ + .long SPI0_IRQHandler /* 59:44 SPI0 */ + .long SPI1_IRQHandler /* 60:45 SPI1 */ + .long SPI2_IRQHandler /* 61:46 SPI2 */ + .long SPIB_IRQHandler /* 62:47 SPI Bridge */ + .long OWM_IRQHandler /* 63:48 1-Wire Master */ + .long AFE_IRQHandler /* 64:49 AFE */ + + .size __isr_vector, . - __isr_vector + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__isr_vector + str r1, [r0] + ldr r2, [r1] + msr msp, r2 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + + cpsie i /* Unmask interrupts */ +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + ldr r0,=MemManage_Handler + bx r0 + .size MemManage_Handler, . - MemManage_Handler + + .align 1 + .thumb_func + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + ldr r0,=BusFault_Handler + bx r0 + .size BusFault_Handler, . - BusFault_Handler + + .align 1 + .thumb_func + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + ldr r0,=UsageFault_Handler + bx r0 + .size UsageFault_Handler, . - UsageFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + ldr r0,=DebugMon_Handler + bx r0 + .size DebugMon_Handler, . - DebugMon_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler CLKMAN_IRQHandler /* 16:01 CLKMAN */ + def_irq_handler PWRMAN_IRQHandler /* 17:02 PWRMAN */ + def_irq_handler FLC_IRQHandler /* 18:03 Flash Controller */ + def_irq_handler RTC0_IRQHandler /* 19:04 RTC INT0 */ + def_irq_handler RTC1_IRQHandler /* 20:05 RTC INT1 */ + def_irq_handler RTC2_IRQHandler /* 21:06 RTC INT2 */ + def_irq_handler RTC3_IRQHandler /* 22:07 RTC INT3 */ + def_irq_handler PMU_IRQHandler /* 23:08 PMU */ + def_irq_handler USB_IRQHandler /* 24:09 USB */ + def_irq_handler AES_IRQHandler /* 25:10 AES */ + def_irq_handler MAA_IRQHandler /* 26:11 MAA */ + def_irq_handler WDT0_IRQHandler /* 27:12 WATCHDOG0 */ + def_irq_handler WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */ + def_irq_handler WDT1_IRQHandler /* 29:14 WATCHDOG1 */ + def_irq_handler WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */ + def_irq_handler GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */ + def_irq_handler GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */ + def_irq_handler GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */ + def_irq_handler GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */ + def_irq_handler GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */ + def_irq_handler GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */ + def_irq_handler GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */ + def_irq_handler TMR0_IRQHandler /* 38:23 Timer32-0 */ + def_irq_handler TMR16_0_IRQHandler /* 39:24 Timer16-s0 */ + def_irq_handler TMR1_IRQHandler /* 40:25 Timer32-1 */ + def_irq_handler TMR16_1_IRQHandler /* 41:26 Timer16-s1 */ + def_irq_handler TMR2_IRQHandler /* 42:27 Timer32-2 */ + def_irq_handler TMR16_2_IRQHandler /* 43:28 Timer16-s2 */ + def_irq_handler TMR3_IRQHandler /* 44:29 Timer32-3 */ + def_irq_handler TMR16_3_IRQHandler /* 45:30 Timer16-s3 */ + def_irq_handler TMR4_IRQHandler /* 46:31 Timer32-4 */ + def_irq_handler TMR16_4_IRQHandler /* 47:32 Timer16-s4 */ + def_irq_handler TMR5_IRQHandler /* 48:33 Timer32-5 */ + def_irq_handler TMR16_5_IRQHandler /* 49:34 Timer16-s5 */ + def_irq_handler UART0_IRQHandler /* 50:35 UART0 */ + def_irq_handler UART1_IRQHandler /* 51:36 UART1 */ + def_irq_handler UART2_IRQHandler /* 52:37 UART0 */ + def_irq_handler UART3_IRQHandler /* 53:38 UART1 */ + def_irq_handler PT_IRQHandler /* 54:39 PT */ + def_irq_handler I2CM0_IRQHandler /* 55:40 I2C Master 0 */ + def_irq_handler I2CM1_IRQHandler /* 56:41 I2C Master 1 */ + def_irq_handler I2CM2_IRQHandler /* 57:42 I2C Master 2 */ + def_irq_handler I2CS_IRQHandler /* 58:43 I2C Slave */ + def_irq_handler SPI0_IRQHandler /* 59:44 SPI0 */ + def_irq_handler SPI1_IRQHandler /* 60:45 SPI1 */ + def_irq_handler SPI2_IRQHandler /* 61:46 SPI2 */ + def_irq_handler SPIB_IRQHandler /* 62:47 SPI Bridge */ + def_irq_handler OWM_IRQHandler /* 63:48 1-Wire Master */ + def_irq_handler AFE_IRQHandler /* 64:49 AFE */ + + .end diff --git a/source/hic_hal/maxim/max32625/gcc/startup_MAX32625.S b/source/hic_hal/maxim/max32625/gcc/startup_MAX32625.S new file mode 100644 index 000000000..6c672c176 --- /dev/null +++ b/source/hic_hal/maxim/max32625/gcc/startup_MAX32625.S @@ -0,0 +1,347 @@ +/** + * @file startup_MK20D5.s + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long 0 /* Reserved*/ + .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ + .long DAPLINK_HIC_ID /* Compatibility*/ + .long DAPLINK_VERSION /* Version*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long g_board_info /* Ptr to Board info, family info other target details*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long CLKMAN_IRQHandler /* 16:01 CLKMAN */ + .long PWRMAN_IRQHandler /* 17:02 PWRMAN */ + .long FLC_IRQHandler /* 18:03 Flash Controller */ + .long RTC0_IRQHandler /* 19:04 RTC INT0 */ + .long RTC1_IRQHandler /* 20:05 RTC INT1 */ + .long RTC2_IRQHandler /* 21:06 RTC INT2 */ + .long RTC3_IRQHandler /* 22:07 RTC INT3 */ + .long PMU_IRQHandler /* 23:08 PMU */ + .long USB_IRQHandler /* 24:09 USB */ + .long AES_IRQHandler /* 25:10 AES */ + .long MAA_IRQHandler /* 26:11 MAA */ + .long WDT0_IRQHandler /* 27:12 WATCHDOG0 */ + .long WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */ + .long WDT1_IRQHandler /* 29:14 WATCHDOG1 */ + .long WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */ + .long GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */ + .long GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */ + .long GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */ + .long GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */ + .long GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */ + .long GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */ + .long GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */ + .long TMR0_IRQHandler /* 38:23 Timer32-0 */ + .long TMR16_0_IRQHandler /* 39:24 Timer16-s0 */ + .long TMR1_IRQHandler /* 40:25 Timer32-1 */ + .long TMR16_1_IRQHandler /* 41:26 Timer16-s1 */ + .long TMR2_IRQHandler /* 42:27 Timer32-2 */ + .long TMR16_2_IRQHandler /* 43:28 Timer16-s2 */ + .long TMR3_IRQHandler /* 44:29 Timer32-3 */ + .long TMR16_3_IRQHandler /* 45:30 Timer16-s3 */ + .long TMR4_IRQHandler /* 46:31 Timer32-4 */ + .long TMR16_4_IRQHandler /* 47:32 Timer16-s4 */ + .long TMR5_IRQHandler /* 48:33 Timer32-5 */ + .long TMR16_5_IRQHandler /* 49:34 Timer16-s5 */ + .long UART0_IRQHandler /* 50:35 UART0 */ + .long UART1_IRQHandler /* 51:36 UART1 */ + .long UART2_IRQHandler /* 52:37 UART0 */ + .long UART3_IRQHandler /* 53:38 UART1 */ + .long PT_IRQHandler /* 54:39 PT */ + .long I2CM0_IRQHandler /* 55:40 I2C Master 0 */ + .long I2CM1_IRQHandler /* 56:41 I2C Master 1 */ + .long I2CM2_IRQHandler /* 57:42 I2C Master 2 */ + .long I2CS_IRQHandler /* 58:43 I2C Slave */ + .long SPI0_IRQHandler /* 59:44 SPI0 */ + .long SPI1_IRQHandler /* 60:45 SPI1 */ + .long SPI2_IRQHandler /* 61:46 SPI2 */ + .long SPIB_IRQHandler /* 62:47 SPI Bridge */ + .long OWM_IRQHandler /* 63:48 1-Wire Master */ + .long AFE_IRQHandler /* 64:49 AFE */ + .long SPIS_IRQHandler /* 65:50 SPI Slave */ + .long GPIO_P7_IRQHandler /* 66:51 GPIO Port 7 */ + .long GPIO_P8_IRQHandler /* 67:52 GPIO Port 8 */ + + .size __isr_vector, . - __isr_vector + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__isr_vector + str r1, [r0] + ldr r2, [r1] + msr msp, r2 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + + cpsie i /* Unmask interrupts */ +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + ldr r0,=MemManage_Handler + bx r0 + .size MemManage_Handler, . - MemManage_Handler + + .align 1 + .thumb_func + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + ldr r0,=BusFault_Handler + bx r0 + .size BusFault_Handler, . - BusFault_Handler + + .align 1 + .thumb_func + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + ldr r0,=UsageFault_Handler + bx r0 + .size UsageFault_Handler, . - UsageFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + ldr r0,=DebugMon_Handler + bx r0 + .size DebugMon_Handler, . - DebugMon_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler CLKMAN_IRQHandler /* 16:01 CLKMAN */ + def_irq_handler PWRMAN_IRQHandler /* 17:02 PWRMAN */ + def_irq_handler FLC_IRQHandler /* 18:03 Flash Controller */ + def_irq_handler RTC0_IRQHandler /* 19:04 RTC INT0 */ + def_irq_handler RTC1_IRQHandler /* 20:05 RTC INT1 */ + def_irq_handler RTC2_IRQHandler /* 21:06 RTC INT2 */ + def_irq_handler RTC3_IRQHandler /* 22:07 RTC INT3 */ + def_irq_handler PMU_IRQHandler /* 23:08 PMU */ + def_irq_handler USB_IRQHandler /* 24:09 USB */ + def_irq_handler AES_IRQHandler /* 25:10 AES */ + def_irq_handler MAA_IRQHandler /* 26:11 MAA */ + def_irq_handler WDT0_IRQHandler /* 27:12 WATCHDOG0 */ + def_irq_handler WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */ + def_irq_handler WDT1_IRQHandler /* 29:14 WATCHDOG1 */ + def_irq_handler WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */ + def_irq_handler GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */ + def_irq_handler GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */ + def_irq_handler GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */ + def_irq_handler GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */ + def_irq_handler GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */ + def_irq_handler GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */ + def_irq_handler GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */ + def_irq_handler TMR0_IRQHandler /* 38:23 Timer32-0 */ + def_irq_handler TMR16_0_IRQHandler /* 39:24 Timer16-s0 */ + def_irq_handler TMR1_IRQHandler /* 40:25 Timer32-1 */ + def_irq_handler TMR16_1_IRQHandler /* 41:26 Timer16-s1 */ + def_irq_handler TMR2_IRQHandler /* 42:27 Timer32-2 */ + def_irq_handler TMR16_2_IRQHandler /* 43:28 Timer16-s2 */ + def_irq_handler TMR3_IRQHandler /* 44:29 Timer32-3 */ + def_irq_handler TMR16_3_IRQHandler /* 45:30 Timer16-s3 */ + def_irq_handler TMR4_IRQHandler /* 46:31 Timer32-4 */ + def_irq_handler TMR16_4_IRQHandler /* 47:32 Timer16-s4 */ + def_irq_handler TMR5_IRQHandler /* 48:33 Timer32-5 */ + def_irq_handler TMR16_5_IRQHandler /* 49:34 Timer16-s5 */ + def_irq_handler UART0_IRQHandler /* 50:35 UART0 */ + def_irq_handler UART1_IRQHandler /* 51:36 UART1 */ + def_irq_handler UART2_IRQHandler /* 52:37 UART0 */ + def_irq_handler UART3_IRQHandler /* 53:38 UART1 */ + def_irq_handler PT_IRQHandler /* 54:39 PT */ + def_irq_handler I2CM0_IRQHandler /* 55:40 I2C Master 0 */ + def_irq_handler I2CM1_IRQHandler /* 56:41 I2C Master 1 */ + def_irq_handler I2CM2_IRQHandler /* 57:42 I2C Master 2 */ + def_irq_handler I2CS_IRQHandler /* 58:43 I2C Slave */ + def_irq_handler SPI0_IRQHandler /* 59:44 SPI0 */ + def_irq_handler SPI1_IRQHandler /* 60:45 SPI1 */ + def_irq_handler SPI2_IRQHandler /* 61:46 SPI2 */ + def_irq_handler SPIB_IRQHandler /* 62:47 SPI Bridge */ + def_irq_handler OWM_IRQHandler /* 63:48 1-Wire Master */ + def_irq_handler AFE_IRQHandler /* 64:49 AFE */ + def_irq_handler SPIS_IRQHandler /* 65:50 SPI Slave */ + def_irq_handler GPIO_P7_IRQHandler /* 66:51 GPIO Port 7 */ + def_irq_handler GPIO_P8_IRQHandler /* 67:52 GPIO Port 8 */ + + .end diff --git a/source/hic_hal/nuvoton/m48ssidae/StdDriver/src/m480_rtc.c b/source/hic_hal/nuvoton/m48ssidae/StdDriver/src/m480_rtc.c index b820a1719..392ee771f 100644 --- a/source/hic_hal/nuvoton/m48ssidae/StdDriver/src/m480_rtc.c +++ b/source/hic_hal/nuvoton/m48ssidae/StdDriver/src/m480_rtc.c @@ -15,7 +15,7 @@ * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -324,7 +324,7 @@ void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt) { uint32_t u32RegCAL, u32RegTIME; - if (sPt == 0ul) { + if (!sPt) { } else { /*-----------------------------------------------------------------------------------------------------*/ /* Set RTC 24/12 hour setting and Day of the Week */ diff --git a/source/hic_hal/nuvoton/m48ssidae/gcc/startup_M480.S b/source/hic_hal/nuvoton/m48ssidae/gcc/startup_M480.S new file mode 100644 index 000000000..1c06187ca --- /dev/null +++ b/source/hic_hal/nuvoton/m48ssidae/gcc/startup_M480.S @@ -0,0 +1,461 @@ +/** + * @file startup_MK20D5.s + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long 0 /* Reserved*/ + .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ + .long DAPLINK_HIC_ID /* Compatibility*/ + .long DAPLINK_VERSION /* Version*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long g_board_info /* Ptr to Board info, family info other target details*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long BOD_IRQHandler /* 0: Brown Out detection */ + .long IRC_IRQHandler /* 1: Internal RC */ + .long PWRWU_IRQHandler /* 2: Power down wake up */ + .long RAMPE_IRQHandler /* 3: RAM parity error */ + .long CKFAIL_IRQHandler /* 4: Clock detection fail */ + .long Reserved0_Handler /* 5: Reserved */ + .long RTC_IRQHandler /* 6: Real Time Clock */ + .long TAMPER_IRQHandler /* 7: Tamper detection */ + .long WDT_IRQHandler /* 8: Watchdog timer */ + .long WWDT_IRQHandler /* 9: Window watchdog timer */ + .long EINT0_IRQHandler /* 10: External Input 0 */ + .long EINT1_IRQHandler /* 11: External Input 1 */ + .long EINT2_IRQHandler /* 12: External Input 2 */ + .long EINT3_IRQHandler /* 13: External Input 3 */ + .long EINT4_IRQHandler /* 14: External Input 4 */ + .long EINT5_IRQHandler /* 15: External Input 5 */ + .long GPA_IRQHandler /* 16: GPIO Port A */ + .long GPB_IRQHandler /* 17: GPIO Port B */ + .long GPC_IRQHandler /* 18: GPIO Port C */ + .long GPD_IRQHandler /* 19: GPIO Port D */ + .long GPE_IRQHandler /* 20: GPIO Port E */ + .long GPF_IRQHandler /* 21: GPIO Port F */ + .long QSPI0_IRQHandler /* 22: QSPI0 */ + .long SPI0_IRQHandler /* 23: SPI0 */ + .long BRAKE0_IRQHandler /* 24: */ + .long EPWM0P0_IRQHandler /* 25: */ + .long EPWM0P1_IRQHandler /* 26: */ + .long EPWM0P2_IRQHandler /* 27: */ + .long BRAKE1_IRQHandler /* 28: */ + .long EPWM1P0_IRQHandler /* 29: */ + .long EPWM1P1_IRQHandler /* 30: */ + .long EPWM1P2_IRQHandler /* 31: */ + .long TMR0_IRQHandler /* 32: Timer 0 */ + .long TMR1_IRQHandler /* 33: Timer 1 */ + .long TMR2_IRQHandler /* 34: Timer 2 */ + .long TMR3_IRQHandler /* 35: Timer 3 */ + .long UART0_IRQHandler /* 36: UART0 */ + .long UART1_IRQHandler /* 37: UART1 */ + .long I2C0_IRQHandler /* 38: I2C0 */ + .long I2C1_IRQHandler /* 39: I2C1 */ + .long PDMA_IRQHandler /* 40: Peripheral DMA */ + .long DAC_IRQHandler /* 41: DAC */ + .long ADC00_IRQHandler /* 42: ADC0 interrupt source 0 */ + .long ADC01_IRQHandler /* 43: ADC0 interrupt source 1 */ + .long ACMP01_IRQHandler /* 44: ACMP0 and ACMP1 */ + .long Reserved1_Handler /* 45: Reserved */ + .long ADC02_IRQHandler /* 46: ADC0 interrupt source 2 */ + .long ADC03_IRQHandler /* 47: ADC0 interrupt source 3 */ + .long UART2_IRQHandler /* 48: UART2 */ + .long UART3_IRQHandler /* 49: UART3 */ + .long Reserved2_Handler /* 50: Reserved */ + .long SPI1_IRQHandler /* 51: SPI1 */ + .long SPI2_IRQHandler /* 52: SPI2 */ + .long USBD_IRQHandler /* 53: USB device */ + .long OHCI_IRQHandler /* 54: OHCI */ + .long USBOTG_IRQHandler /* 55: USB OTG */ + .long CAN0_IRQHandler /* 56: CAN0 */ + .long CAN1_IRQHandler /* 57: CAN1 */ + .long SC0_IRQHandler /* 58: */ + .long SC1_IRQHandler /* 59: */ + .long SC2_IRQHandler /* 60: */ + .long Reserved3_Handler /* 61: */ + .long SPI3_IRQHandler /* 62: SPI3 */ + .long Reserved4_Handler /* 63: */ + .long SDH0_IRQHandler /* 64: SDH0 */ + .long USBD20_IRQHandler /* 65: USBD20 */ + .long EMAC_TX_IRQHandler /* 66: EMAC_TX */ + .long EMAC_RX_IRQHandler /* 67: EMAX_RX */ + .long I2S0_IRQHandler /* 68: I2S0 */ + .long Reserved5_Handler /* 69: ToDo: Add description to this Interrupt */ + .long OPA0_IRQHandler /* 70: OPA0 */ + .long CRYPTO_IRQHandler /* 71: CRYPTO */ + .long GPG_IRQHandler /* 72: */ + .long EINT6_IRQHandler /* 73: */ + .long UART4_IRQHandler /* 74: UART4 */ + .long UART5_IRQHandler /* 75: UART5 */ + .long USCI0_IRQHandler /* 76: USCI0 */ + .long USCI1_IRQHandler /* 77: USCI1 */ + .long BPWM0_IRQHandler /* 78: BPWM0 */ + .long BPWM1_IRQHandler /* 79: BPWM1 */ + .long SPIM_IRQHandler /* 80: SPIM */ + .long Reserved6_Handler /* 81: ToDo: Add description to this Interrupt */ + .long I2C2_IRQHandler /* 82: I2C2 */ + .long Reserved7_Handler /* 83: */ + .long QEI0_IRQHandler /* 84: QEI0 */ + .long QEI1_IRQHandler /* 85: QEI1 */ + .long ECAP0_IRQHandler /* 86: ECAP0 */ + .long ECAP1_IRQHandler /* 87: ECAP1 */ + .long GPH_IRQHandler /* 88: */ + .long EINT7_IRQHandler /* 89: */ + .long SDH1_IRQHandler /* 90: SDH1 */ + .long Reserved8_Handler /* 91: */ + .long EHCI_IRQHandler /* 92: EHCI */ + .long USBOTG20_IRQHandler /* 93: */ + + .size __isr_vector, . - __isr_vector + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__isr_vector + str r1, [r0] + ldr r2, [r1] + msr msp, r2 + + /* Unlock Register */ + ldr r0, =0x40000100 + ldr r1, =0x59 + str r1, [r0] + ldr r1, =0x16 + str r1, [r0] + ldr r1, =0x88 + str r1, [r0] + +#if !defined(ENABLE_SPIM_CACHE) + ldr r0, =0x40000200 /* R0 = Clock Controller Register Base Address */ + ldr r1, [r0,#0x4] /* R1 = 0x40000204 (AHBCLK) */ + orr r1, r1, #0x4000 + str r1, [r0,#0x4] /* CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk; */ + + ldr r0, =0x40007000 /* R0 = SPIM Register Base Address */ + ldr r1, [r0,#4] /* R1 = SPIM->CTL1 */ + orr r1, r1,#2 /* R1 |= SPIM_CTL1_CACHEOFF_Msk */ + str r1, [r0,#4] /* _SPIM_DISABLE_CACHE() */ + ldr r1, [r0,#4] /* R1 = SPIM->CTL1 */ + orr r1, r1, #4 /* R1 |= SPIM_CTL1_CCMEN_Msk */ + str r1, [r0,#4] /* _SPIM_ENABLE_CCM() */ +#endif + +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + + /* Lock */ + ldr r0, =0x40000100 + ldr r1, =0 + str r1, [r0] + + cpsie i /* Unmask interrupts */ +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + ldr r0,=MemManage_Handler + bx r0 + .size MemManage_Handler, . - MemManage_Handler + + .align 1 + .thumb_func + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + ldr r0,=BusFault_Handler + bx r0 + .size BusFault_Handler, . - BusFault_Handler + + .align 1 + .thumb_func + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + ldr r0,=UsageFault_Handler + bx r0 + .size UsageFault_Handler, . - UsageFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + ldr r0,=DebugMon_Handler + bx r0 + .size DebugMon_Handler, . - DebugMon_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler BOD_IRQHandler /* 0: Brown Out detection */ + def_irq_handler IRC_IRQHandler /* 1: Internal RC */ + def_irq_handler PWRWU_IRQHandler /* 2: Power down wake up */ + def_irq_handler RAMPE_IRQHandler /* 3: RAM parity error */ + def_irq_handler CKFAIL_IRQHandler /* 4: Clock detection fail */ + def_irq_handler Reserved0_Handler /* 5: Reserved */ + def_irq_handler RTC_IRQHandler /* 6: Real Time Clock */ + def_irq_handler TAMPER_IRQHandler /* 7: Tamper detection */ + def_irq_handler WDT_IRQHandler /* 8: Watchdog timer */ + def_irq_handler WWDT_IRQHandler /* 9: Window watchdog timer */ + def_irq_handler EINT0_IRQHandler /* 10: External Input 0 */ + def_irq_handler EINT1_IRQHandler /* 11: External Input 1 */ + def_irq_handler EINT2_IRQHandler /* 12: External Input 2 */ + def_irq_handler EINT3_IRQHandler /* 13: External Input 3 */ + def_irq_handler EINT4_IRQHandler /* 14: External Input 4 */ + def_irq_handler EINT5_IRQHandler /* 15: External Input 5 */ + def_irq_handler GPA_IRQHandler /* 16: GPIO Port A */ + def_irq_handler GPB_IRQHandler /* 17: GPIO Port B */ + def_irq_handler GPC_IRQHandler /* 18: GPIO Port C */ + def_irq_handler GPD_IRQHandler /* 19: GPIO Port D */ + def_irq_handler GPE_IRQHandler /* 20: GPIO Port E */ + def_irq_handler GPF_IRQHandler /* 21: GPIO Port F */ + def_irq_handler QSPI0_IRQHandler /* 22: QSPI0 */ + def_irq_handler SPI0_IRQHandler /* 23: SPI0 */ + def_irq_handler BRAKE0_IRQHandler /* 24: */ + def_irq_handler EPWM0P0_IRQHandler /* 25: */ + def_irq_handler EPWM0P1_IRQHandler /* 26: */ + def_irq_handler EPWM0P2_IRQHandler /* 27: */ + def_irq_handler BRAKE1_IRQHandler /* 28: */ + def_irq_handler EPWM1P0_IRQHandler /* 29: */ + def_irq_handler EPWM1P1_IRQHandler /* 30: */ + def_irq_handler EPWM1P2_IRQHandler /* 31: */ + def_irq_handler TMR0_IRQHandler /* 32: Timer 0 */ + def_irq_handler TMR1_IRQHandler /* 33: Timer 1 */ + def_irq_handler TMR2_IRQHandler /* 34: Timer 2 */ + def_irq_handler TMR3_IRQHandler /* 35: Timer 3 */ + def_irq_handler UART0_IRQHandler /* 36: UART0 */ + def_irq_handler UART1_IRQHandler /* 37: UART1 */ + def_irq_handler I2C0_IRQHandler /* 38: I2C0 */ + def_irq_handler I2C1_IRQHandler /* 39: I2C1 */ + def_irq_handler PDMA_IRQHandler /* 40: Peripheral DMA */ + def_irq_handler DAC_IRQHandler /* 41: DAC */ + def_irq_handler ADC00_IRQHandler /* 42: ADC0 interrupt source 0 */ + def_irq_handler ADC01_IRQHandler /* 43: ADC0 interrupt source 1 */ + def_irq_handler ACMP01_IRQHandler /* 44: ACMP0 and ACMP1 */ + def_irq_handler Reserved1_Handler /* 45: Reserved */ + def_irq_handler ADC02_IRQHandler /* 46: ADC0 interrupt source 2 */ + def_irq_handler ADC03_IRQHandler /* 47: ADC0 interrupt source 3 */ + def_irq_handler UART2_IRQHandler /* 48: UART2 */ + def_irq_handler UART3_IRQHandler /* 49: UART3 */ + def_irq_handler Reserved2_Handler /* 50: Reserved */ + def_irq_handler SPI1_IRQHandler /* 51: SPI1 */ + def_irq_handler SPI2_IRQHandler /* 52: SPI2 */ + def_irq_handler USBD_IRQHandler /* 53: USB device */ + def_irq_handler OHCI_IRQHandler /* 54: OHCI */ + def_irq_handler USBOTG_IRQHandler /* 55: USB OTG */ + def_irq_handler CAN0_IRQHandler /* 56: CAN0 */ + def_irq_handler CAN1_IRQHandler /* 57: CAN1 */ + def_irq_handler SC0_IRQHandler /* 58: */ + def_irq_handler SC1_IRQHandler /* 59: */ + def_irq_handler SC2_IRQHandler /* 60: */ + def_irq_handler Reserved3_Handler /* 61: */ + def_irq_handler SPI3_IRQHandler /* 62: SPI3 */ + def_irq_handler Reserved4_Handler /* 63: */ + def_irq_handler SDH0_IRQHandler /* 64: SDH0 */ + def_irq_handler USBD20_IRQHandler /* 65: USBD20 */ + def_irq_handler EMAC_TX_IRQHandler /* 66: EMAC_TX */ + def_irq_handler EMAC_RX_IRQHandler /* 67: EMAX_RX */ + def_irq_handler I2S0_IRQHandler /* 68: I2S0 */ + def_irq_handler Reserved5_Handler /* 69: ToDo: Add description to this Interrupt */ + def_irq_handler OPA0_IRQHandler /* 70: OPA0 */ + def_irq_handler CRYPTO_IRQHandler /* 71: CRYPTO */ + def_irq_handler GPG_IRQHandler /* 72: */ + def_irq_handler EINT6_IRQHandler /* 73: */ + def_irq_handler UART4_IRQHandler /* 74: UART4 */ + def_irq_handler UART5_IRQHandler /* 75: UART5 */ + def_irq_handler USCI0_IRQHandler /* 76: USCI0 */ + def_irq_handler USCI1_IRQHandler /* 77: USCI1 */ + def_irq_handler BPWM0_IRQHandler /* 78: BPWM0 */ + def_irq_handler BPWM1_IRQHandler /* 79: BPWM1 */ + def_irq_handler SPIM_IRQHandler /* 80: SPIM */ + def_irq_handler Reserved6_Handler /* 81: ToDo: Add description to this Interrupt */ + def_irq_handler I2C2_IRQHandler /* 82: I2C2 */ + def_irq_handler Reserved7_Handler /* 83: */ + def_irq_handler QEI0_IRQHandler /* 84: QEI0 */ + def_irq_handler QEI1_IRQHandler /* 85: QEI1 */ + def_irq_handler ECAP0_IRQHandler /* 86: ECAP0 */ + def_irq_handler ECAP1_IRQHandler /* 87: ECAP1 */ + def_irq_handler GPH_IRQHandler /* 88: */ + def_irq_handler EINT7_IRQHandler /* 89: */ + def_irq_handler SDH1_IRQHandler /* 90: SDH1 */ + def_irq_handler Reserved8_Handler /* 91: */ + def_irq_handler EHCI_IRQHandler /* 92: EHCI */ + def_irq_handler USBOTG20_IRQHandler /* 93: */ + + .end diff --git a/source/hic_hal/nxp/lpc4322/gcc/startup_LPC43xx.S b/source/hic_hal/nxp/lpc4322/gcc/startup_LPC43xx.S new file mode 100644 index 000000000..51ff0d917 --- /dev/null +++ b/source/hic_hal/nxp/lpc4322/gcc/startup_LPC43xx.S @@ -0,0 +1,363 @@ +/** + * @file startup_MK20D5.s + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long 0x5A5A5A5A /* Reserved*/ + .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ + .long DAPLINK_HIC_ID /* Compatibility*/ + .long DAPLINK_VERSION /* Version*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long g_board_info /* Ptr to Board info, family info other target details*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long DAC_IRQHandler /* 16 D/A Converter */ + .long M0CORE_IRQHandler /* 17 M0 Core */ + .long DMA_IRQHandler /* 18 General Purpose DMA */ + .long EZH_IRQHandler /* 19 EZH/EDM */ + .long FLASH_EEPROM_IRQHandler /* 20 Reserved for Typhoon */ + .long ETH_IRQHandler /* 21 Ethernet */ + .long SDIO_IRQHandler /* 22 SD/MMC */ + .long LCD_IRQHandler /* 23 LCD */ + .long USB0_IRQHandler /* 24 USB0 */ + .long USB1_IRQHandler /* 25 USB1 */ + .long SCT_IRQHandler /* 26 State Configurable Timer */ + .long RIT_IRQHandler /* 27 Repetitive Interrupt Timer */ + .long TIMER0_IRQHandler /* 28 Timer0 */ + .long TIMER1_IRQHandler /* 29 Timer1 */ + .long TIMER2_IRQHandler /* 30 Timer2 */ + .long TIMER3_IRQHandler /* 31 Timer3 */ + .long MCPWM_IRQHandler /* 32 Motor Control PWM */ + .long ADC0_IRQHandler /* 33 A/D Converter 0 */ + .long I2C0_IRQHandler /* 34 I2C0 */ + .long I2C1_IRQHandler /* 35 I2C1 */ + .long SPI_IRQHandler /* 36 SPI */ + .long ADC1_IRQHandler /* 37 A/D Converter 1 */ + .long SSP0_IRQHandler /* 38 SSP0 */ + .long SSP1_IRQHandler /* 39 SSP1 */ + .long UART0_IRQHandler /* 40 UART0 */ + .long UART1_IRQHandler /* 41 UART1 */ + .long UART2_IRQHandler /* 42 UART2 */ + .long UART3_IRQHandler /* 43 UART3 */ + .long I2S0_IRQHandler /* 44 I2S0 */ + .long I2S1_IRQHandler /* 45 I2S1 */ + .long SPIFI_IRQHandler /* 46 SPI Flash Interface */ + .long SGPIO_IRQHandler /* 47 SGPIO */ + .long GPIO0_IRQHandler /* 48 GPIO0 */ + .long GPIO1_IRQHandler /* 49 GPIO1 */ + .long GPIO2_IRQHandler /* 50 GPIO2 */ + .long GPIO3_IRQHandler /* 51 GPIO3 */ + .long GPIO4_IRQHandler /* 52 GPIO4 */ + .long GPIO5_IRQHandler /* 53 GPIO5 */ + .long GPIO6_IRQHandler /* 54 GPIO6 */ + .long GPIO7_IRQHandler /* 55 GPIO7 */ + .long GINT0_IRQHandler /* 56 GINT0 */ + .long GINT1_IRQHandler /* 57 GINT1 */ + .long EVRT_IRQHandler /* 58 Event Router */ + .long CAN1_IRQHandler /* 59 C_CAN1 */ + .long 0 /* 60 Reserved */ + .long VADC_IRQHandler /* 61 VADC */ + .long ATIMER_IRQHandler /* 62 ATIMER */ + .long RTC_IRQHandler /* 63 RTC */ + .long 0 /* 64 Reserved */ + .long WDT_IRQHandler /* 65 WDT */ + .long M0s_IRQHandler /* 66 M0s */ + .long CAN0_IRQHandler /* 67 C_CAN0 */ + .long QEI_IRQHandler /* 68 QEI */ + +#if defined(MBED_BOOTLOADER) + +// Set the CRP (Code Read Protection) configuration word at address 0x2FC to ensure that +// CRP is disabled. +#define CRP_KEY_ADDR (0x000002FC) +#define CRP_DISABLED (0xFFFFFFFF) + +1: // Fill up to CRP config word address. + .dcb.l ((CRP_KEY_ADDR - (1b - __isr_vector)) / 4) + +CRP_Key: + .long CRP_DISABLED + +#endif // MBED_BOOTLOADER + + + .size __isr_vector, . - __isr_vector + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__isr_vector + str r1, [r0] + ldr r2, [r1] + msr msp, r2 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + + cpsie i /* Unmask interrupts */ +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + ldr r0,=MemManage_Handler + bx r0 + .size MemManage_Handler, . - MemManage_Handler + + .align 1 + .thumb_func + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + ldr r0,=BusFault_Handler + bx r0 + .size BusFault_Handler, . - BusFault_Handler + + .align 1 + .thumb_func + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + ldr r0,=UsageFault_Handler + bx r0 + .size UsageFault_Handler, . - UsageFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + ldr r0,=DebugMon_Handler + bx r0 + .size DebugMon_Handler, . - DebugMon_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler DAC_IRQHandler /* 16 D/A Converter */ + def_irq_handler M0CORE_IRQHandler /* 17 M0 Core */ + def_irq_handler DMA_IRQHandler /* 18 General Purpose DMA */ + def_irq_handler EZH_IRQHandler /* 19 EZH/EDM */ + def_irq_handler FLASH_EEPROM_IRQHandler /* 20 Reserved for Typhoon */ + def_irq_handler ETH_IRQHandler /* 21 Ethernet */ + def_irq_handler SDIO_IRQHandler /* 22 SD/MMC */ + def_irq_handler LCD_IRQHandler /* 23 LCD */ + def_irq_handler USB0_IRQHandler /* 24 USB0 */ + def_irq_handler USB1_IRQHandler /* 25 USB1 */ + def_irq_handler SCT_IRQHandler /* 26 State Configurable Timer */ + def_irq_handler RIT_IRQHandler /* 27 Repetitive Interrupt Timer */ + def_irq_handler TIMER0_IRQHandler /* 28 Timer0 */ + def_irq_handler TIMER1_IRQHandler /* 29 Timer1 */ + def_irq_handler TIMER2_IRQHandler /* 30 Timer2 */ + def_irq_handler TIMER3_IRQHandler /* 31 Timer3 */ + def_irq_handler MCPWM_IRQHandler /* 32 Motor Control PWM */ + def_irq_handler ADC0_IRQHandler /* 33 A/D Converter 0 */ + def_irq_handler I2C0_IRQHandler /* 34 I2C0 */ + def_irq_handler I2C1_IRQHandler /* 35 I2C1 */ + def_irq_handler SPI_IRQHandler /* 36 SPI */ + def_irq_handler ADC1_IRQHandler /* 37 A/D Converter 1 */ + def_irq_handler SSP0_IRQHandler /* 38 SSP0 */ + def_irq_handler SSP1_IRQHandler /* 39 SSP1 */ + def_irq_handler UART0_IRQHandler /* 40 UART0 */ + def_irq_handler UART1_IRQHandler /* 41 UART1 */ + def_irq_handler UART2_IRQHandler /* 42 UART2 */ + def_irq_handler UART3_IRQHandler /* 43 UART3 */ + def_irq_handler I2S0_IRQHandler /* 44 I2S0 */ + def_irq_handler I2S1_IRQHandler /* 45 I2S1 */ + def_irq_handler SPIFI_IRQHandler /* 46 SPI Flash Interface */ + def_irq_handler SGPIO_IRQHandler /* 47 SGPIO */ + def_irq_handler GPIO0_IRQHandler /* 48 GPIO0 */ + def_irq_handler GPIO1_IRQHandler /* 49 GPIO1 */ + def_irq_handler GPIO2_IRQHandler /* 50 GPIO2 */ + def_irq_handler GPIO3_IRQHandler /* 51 GPIO3 */ + def_irq_handler GPIO4_IRQHandler /* 52 GPIO4 */ + def_irq_handler GPIO5_IRQHandler /* 53 GPIO5 */ + def_irq_handler GPIO6_IRQHandler /* 54 GPIO6 */ + def_irq_handler GPIO7_IRQHandler /* 55 GPIO7 */ + def_irq_handler GINT0_IRQHandler /* 56 GINT0 */ + def_irq_handler GINT1_IRQHandler /* 57 GINT1 */ + def_irq_handler EVRT_IRQHandler /* 58 Event Router */ + def_irq_handler CAN1_IRQHandler /* 59 C_CAN1 */ + def_irq_handler VADC_IRQHandler /* 61 VADC */ + def_irq_handler ATIMER_IRQHandler /* 62 ATIMER */ + def_irq_handler RTC_IRQHandler /* 63 RTC */ + def_irq_handler WDT_IRQHandler /* 65 WDT */ + def_irq_handler M0s_IRQHandler /* 66 M0s */ + def_irq_handler CAN0_IRQHandler /* 67 C_CAN0 */ + def_irq_handler QEI_IRQHandler /* 68 QEI */ + + .end diff --git a/source/hic_hal/nxp/lpc4322/system_LPC43xx.c b/source/hic_hal/nxp/lpc4322/system_LPC43xx.c index 87cd44d55..405cf5aea 100644 --- a/source/hic_hal/nxp/lpc4322/system_LPC43xx.c +++ b/source/hic_hal/nxp/lpc4322/system_LPC43xx.c @@ -55,9 +55,6 @@ extern uint32_t __Vectors; */ void SystemInit(void) { - // Set up Cortex_M3 or M4 VTOR register to point to vector table - SCB->VTOR = (unsigned int)&__Vectors; - fpuEnable(); // In case we are running from internal flash, we configure the flash diff --git a/source/hic_hal/stm32/stm32f103xb/gcc/startup_stm32f103xb.S b/source/hic_hal/stm32/stm32f103xb/gcc/startup_stm32f103xb.S new file mode 100644 index 000000000..ddc406b7c --- /dev/null +++ b/source/hic_hal/stm32/stm32f103xb/gcc/startup_stm32f103xb.S @@ -0,0 +1,329 @@ +/** + * @file startup_MK20D5.s + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long 0 /* Reserved*/ + .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ + .long DAPLINK_HIC_ID /* Compatibility*/ + .long DAPLINK_VERSION /* Version*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long g_board_info /* Ptr to Board info, family info other target details*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long WWDG_IRQHandler /* Window Watchdog */ + .long PVD_IRQHandler /* PVD through EXTI Line detect */ + .long TAMPER_IRQHandler /* Tamper */ + .long RTC_IRQHandler /* RTC */ + .long FLASH_IRQHandler /* Flash */ + .long RCC_IRQHandler /* RCC */ + .long EXTI0_IRQHandler /* EXTI Line 0 */ + .long EXTI1_IRQHandler /* EXTI Line 1 */ + .long EXTI2_IRQHandler /* EXTI Line 2 */ + .long EXTI3_IRQHandler /* EXTI Line 3 */ + .long EXTI4_IRQHandler /* EXTI Line 4 */ + .long DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .long DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .long DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .long DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .long DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .long DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .long DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .long ADC1_2_IRQHandler /* ADC1_2 */ + .long USB_HP_CAN1_TX_IRQHandler /* USB High Priority or CAN1 TX */ + .long USB_LP_CAN1_RX0_IRQHandler /* USB Low Priority or CAN1 RX0 */ + .long CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .long CAN1_SCE_IRQHandler /* CAN1 SCE */ + .long EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .long TIM1_BRK_IRQHandler /* TIM1 Break */ + .long TIM1_UP_IRQHandler /* TIM1 Update */ + .long TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .long TIM2_IRQHandler /* TIM2 */ + .long TIM3_IRQHandler /* TIM3 */ + .long TIM4_IRQHandler /* TIM4 */ + .long I2C1_EV_IRQHandler /* I2C1 Event */ + .long I2C1_ER_IRQHandler /* I2C1 Error */ + .long I2C2_EV_IRQHandler /* I2C2 Event */ + .long I2C2_ER_IRQHandler /* I2C2 Error */ + .long SPI1_IRQHandler /* SPI1 */ + .long SPI2_IRQHandler /* SPI2 */ + .long USART1_IRQHandler /* USART1 */ + .long USART2_IRQHandler /* USART2 */ + .long USART3_IRQHandler /* USART3 */ + .long EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .long RTC_Alarm_IRQHandler /* RTC Alarm through EXTI Line */ + .long USBWakeUp_IRQHandler /* USB Wakeup from suspend */ + + .size __isr_vector, . - __isr_vector + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__isr_vector + str r1, [r0] + ldr r2, [r1] + msr msp, r2 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + + cpsie i /* Unmask interrupts */ +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + ldr r0,=MemManage_Handler + bx r0 + .size MemManage_Handler, . - MemManage_Handler + + .align 1 + .thumb_func + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + ldr r0,=BusFault_Handler + bx r0 + .size BusFault_Handler, . - BusFault_Handler + + .align 1 + .thumb_func + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + ldr r0,=UsageFault_Handler + bx r0 + .size UsageFault_Handler, . - UsageFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + ldr r0,=DebugMon_Handler + bx r0 + .size DebugMon_Handler, . - DebugMon_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler WWDG_IRQHandler /* Window Watchdog */ + def_irq_handler PVD_IRQHandler /* PVD through EXTI Line detect */ + def_irq_handler TAMPER_IRQHandler /* Tamper */ + def_irq_handler RTC_IRQHandler /* RTC */ + def_irq_handler FLASH_IRQHandler /* Flash */ + def_irq_handler RCC_IRQHandler /* RCC */ + def_irq_handler EXTI0_IRQHandler /* EXTI Line 0 */ + def_irq_handler EXTI1_IRQHandler /* EXTI Line 1 */ + def_irq_handler EXTI2_IRQHandler /* EXTI Line 2 */ + def_irq_handler EXTI3_IRQHandler /* EXTI Line 3 */ + def_irq_handler EXTI4_IRQHandler /* EXTI Line 4 */ + def_irq_handler DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + def_irq_handler DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + def_irq_handler DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + def_irq_handler DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + def_irq_handler DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + def_irq_handler DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + def_irq_handler DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + def_irq_handler ADC1_2_IRQHandler /* ADC1_2 */ + def_irq_handler USB_HP_CAN1_TX_IRQHandler /* USB High Priority or CAN1 TX */ + def_irq_handler USB_LP_CAN1_RX0_IRQHandler /* USB Low Priority or CAN1 RX0 */ + def_irq_handler CAN1_RX1_IRQHandler /* CAN1 RX1 */ + def_irq_handler CAN1_SCE_IRQHandler /* CAN1 SCE */ + def_irq_handler EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + def_irq_handler TIM1_BRK_IRQHandler /* TIM1 Break */ + def_irq_handler TIM1_UP_IRQHandler /* TIM1 Update */ + def_irq_handler TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + def_irq_handler TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + def_irq_handler TIM2_IRQHandler /* TIM2 */ + def_irq_handler TIM3_IRQHandler /* TIM3 */ + def_irq_handler TIM4_IRQHandler /* TIM4 */ + def_irq_handler I2C1_EV_IRQHandler /* I2C1 Event */ + def_irq_handler I2C1_ER_IRQHandler /* I2C1 Error */ + def_irq_handler I2C2_EV_IRQHandler /* I2C2 Event */ + def_irq_handler I2C2_ER_IRQHandler /* I2C2 Error */ + def_irq_handler SPI1_IRQHandler /* SPI1 */ + def_irq_handler SPI2_IRQHandler /* SPI2 */ + def_irq_handler USART1_IRQHandler /* USART1 */ + def_irq_handler USART2_IRQHandler /* USART2 */ + def_irq_handler USART3_IRQHandler /* USART3 */ + def_irq_handler EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + def_irq_handler RTC_Alarm_IRQHandler /* RTC Alarm through EXTI Line */ + def_irq_handler USBWakeUp_IRQHandler /* USB Wakeup from suspend */ + + .end From 41e6727dc97bb12d5d15387b29d78a8a0106f5b5 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sun, 24 Nov 2019 15:38:09 -0600 Subject: [PATCH 055/617] Turned on -Werror for gcc. --- records/tools/make_gcc_arm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/records/tools/make_gcc_arm.yaml b/records/tools/make_gcc_arm.yaml index afbbaede1..24c45ae0d 100644 --- a/records/tools/make_gcc_arm.yaml +++ b/records/tools/make_gcc_arm.yaml @@ -16,6 +16,7 @@ tool_specific: - -Os - -g3 # - -Wall + - -Werror - -ffunction-sections - -fdata-sections - -std=gnu99 From 93531964e70fe1e78eacc204d0bb9fffd43931db Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 9 Dec 2020 13:32:41 -0600 Subject: [PATCH 056/617] Additional gcc compilation flags --- records/tools/make_gcc_arm.yaml | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/records/tools/make_gcc_arm.yaml b/records/tools/make_gcc_arm.yaml index 24c45ae0d..afeabf242 100644 --- a/records/tools/make_gcc_arm.yaml +++ b/records/tools/make_gcc_arm.yaml @@ -27,15 +27,16 @@ tool_specific: - -fverbose-asm - -mno-unaligned-access ld_flags: - - -Wl,--no-wchar-size-warning - --specs=nano.specs - --specs=nosys.specs - - -Wl,--gc-sections + - -Wl,-check-sections - -Wl,--defsym=__stack_size__=0x200 - -Wl,--defsym=__heap_size__=0x0 + - -Wl,-fatal-warnings + - -Wl,--gc-sections + - -Wl,--no-wchar-size-warning + - -Wl,--print-memory-usage pre_build_script: - tools/pre_build_script.sh post_build_script: - tools/post_build_script_gcc.sh - - From c67a2ebdcdfbf2e08f551f70618ba5cf95a2a438 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 9 Dec 2020 21:40:44 -0600 Subject: [PATCH 057/617] Add support for make_armclang tool --- projects.yaml | 1 + records/daplink/bootloader.yaml | 3 ++ records/daplink/interface.yaml | 3 ++ records/hic_hal/k20dx.yaml | 4 ++ records/hic_hal/k26f.yaml | 11 ++++++ records/hic_hal/kl26z.yaml | 4 ++ records/hic_hal/lpc11u35.yaml | 4 ++ records/hic_hal/lpc4322.yaml | 4 ++ records/hic_hal/m48ssidae.yaml | 4 ++ records/hic_hal/max32620.yaml | 4 ++ records/hic_hal/max32625.yaml | 4 ++ records/hic_hal/sam3u2c.yaml | 4 ++ records/hic_hal/stm32f103xb.yaml | 9 +++++ records/tools/make_armclang.yaml | 43 +++++++++++++++++++++ source/daplink/daplink.ac6.sct | 60 +++++++++++++++++++++++++++++ tools/post_build_script_armclang.sh | 36 +++++++++++++++++ 16 files changed, 198 insertions(+) create mode 100644 records/tools/make_armclang.yaml create mode 100644 source/daplink/daplink.ac6.sct create mode 100755 tools/post_build_script_armclang.sh diff --git a/projects.yaml b/projects.yaml index b5a97d0e6..9f183b4b2 100644 --- a/projects.yaml +++ b/projects.yaml @@ -10,6 +10,7 @@ module: tools: &module_tools - records/tools/make_gcc_arm.yaml - records/tools/make_armcc.yaml + - records/tools/make_armclang.yaml - records/tools/version.yaml bl: &module_bl - *module_tools diff --git a/records/daplink/bootloader.yaml b/records/daplink/bootloader.yaml index 8172074e9..1bc9a5b48 100644 --- a/records/daplink/bootloader.yaml +++ b/records/daplink/bootloader.yaml @@ -25,3 +25,6 @@ tool_specific: misc: ld_flags: - --predefine="-DDAPLINK_BL" + make_armclang: + linker_file: + - source/daplink/daplink.ac6.sct diff --git a/records/daplink/interface.yaml b/records/daplink/interface.yaml index 2584d5699..3dac19046 100644 --- a/records/daplink/interface.yaml +++ b/records/daplink/interface.yaml @@ -25,3 +25,6 @@ tool_specific: misc: ld_flags: - --predefine="-DDAPLINK_IF" + make_armclang: + linker_file: + - source/daplink/daplink.ac6.sct diff --git a/records/hic_hal/k20dx.yaml b/records/hic_hal/k20dx.yaml index 2b12e7dff..12a28104f 100644 --- a/records/hic_hal/k20dx.yaml +++ b/records/hic_hal/k20dx.yaml @@ -39,6 +39,10 @@ tool_specific: sources: hic_hal: - source/hic_hal/freescale/k20dx/armcc + make_armclang: + sources: + hic_hal: + - source/hic_hal/freescale/k20dx/armcc make_gcc_arm: linker_file: - source/hic_hal/freescale/kinetis.ld diff --git a/records/hic_hal/k26f.yaml b/records/hic_hal/k26f.yaml index 100c715dd..ae122fb78 100644 --- a/records/hic_hal/k26f.yaml +++ b/records/hic_hal/k26f.yaml @@ -52,6 +52,17 @@ tool_specific: sources: hic_hal: - source/hic_hal/freescale/k26f/armcc + make_armclang: + misc: + c_flags: + - -mno-unaligned-access + cxx_flags: + - -mno-unaligned-access + asm_flags: + - -Wa,armasm,--no_unaligned_access + sources: + hic_hal: + - source/hic_hal/freescale/k26f/armcc make_gcc_arm: linker_file: - source/hic_hal/freescale/kinetis.ld diff --git a/records/hic_hal/kl26z.yaml b/records/hic_hal/kl26z.yaml index 41fa67b96..09e87f67b 100644 --- a/records/hic_hal/kl26z.yaml +++ b/records/hic_hal/kl26z.yaml @@ -39,6 +39,10 @@ tool_specific: sources: hic_hal: - source/hic_hal/freescale/kl26z/armcc + make_armclang: + sources: + hic_hal: + - source/hic_hal/freescale/kl26z/armcc make_gcc_arm: linker_file: - source/hic_hal/freescale/kinetis.ld diff --git a/records/hic_hal/lpc11u35.yaml b/records/hic_hal/lpc11u35.yaml index 4286ffa1a..ad1bebaa1 100644 --- a/records/hic_hal/lpc11u35.yaml +++ b/records/hic_hal/lpc11u35.yaml @@ -28,6 +28,10 @@ tool_specific: sources: hic_hal: - source/hic_hal/nxp/lpc11u35/armcc + make_armclang: + sources: + hic_hal: + - source/hic_hal/nxp/lpc11u35/armcc make_gcc_arm: linker_file: - source/hic_hal/nxp/lpc11u35/gcc/lpc11u35.ld diff --git a/records/hic_hal/lpc4322.yaml b/records/hic_hal/lpc4322.yaml index d3ce8ffc7..51d5b15a2 100644 --- a/records/hic_hal/lpc4322.yaml +++ b/records/hic_hal/lpc4322.yaml @@ -30,6 +30,10 @@ tool_specific: sources: hic_hal: - source/hic_hal/nxp/lpc4322/armcc + make_armclang: + sources: + hic_hal: + - source/hic_hal/nxp/lpc4322/armcc make_gcc_arm: includes: - source/hic_hal/nxp/lpc4322/gcc diff --git a/records/hic_hal/m48ssidae.yaml b/records/hic_hal/m48ssidae.yaml index c21fc8c36..5ce69317d 100644 --- a/records/hic_hal/m48ssidae.yaml +++ b/records/hic_hal/m48ssidae.yaml @@ -34,6 +34,10 @@ tool_specific: sources: hic_hal: - source/hic_hal/nuvoton/m48ssidae/armcc + make_armclang: + sources: + hic_hal: + - source/hic_hal/nuvoton/m48ssidae/armcc make_gcc_arm: includes: - source/hic_hal/nuvoton/m48ssidae/gcc diff --git a/records/hic_hal/max32620.yaml b/records/hic_hal/max32620.yaml index b24e1149d..041018657 100644 --- a/records/hic_hal/max32620.yaml +++ b/records/hic_hal/max32620.yaml @@ -28,6 +28,10 @@ tool_specific: sources: hic_hal: - source/hic_hal/maxim/max32620/armcc + make_armclang: + sources: + hic_hal: + - source/hic_hal/maxim/max32620/armcc make_gcc_arm: includes: - source/hic_hal/maxim/max32620/gcc diff --git a/records/hic_hal/max32625.yaml b/records/hic_hal/max32625.yaml index b4d806364..dc99e6bbd 100644 --- a/records/hic_hal/max32625.yaml +++ b/records/hic_hal/max32625.yaml @@ -28,6 +28,10 @@ tool_specific: sources: hic_hal: - source/hic_hal/maxim/max32625/armcc + make_armclang: + sources: + hic_hal: + - source/hic_hal/maxim/max32625/armcc make_gcc_arm: includes: - source/hic_hal/maxim/max32625/gcc diff --git a/records/hic_hal/sam3u2c.yaml b/records/hic_hal/sam3u2c.yaml index f726b4188..d127dd665 100644 --- a/records/hic_hal/sam3u2c.yaml +++ b/records/hic_hal/sam3u2c.yaml @@ -31,6 +31,10 @@ tool_specific: sources: hic_hal: - source/hic_hal/atmel/sam3u2c/armcc + make_armclang: + sources: + hic_hal: + - source/hic_hal/atmel/sam3u2c/armcc make_gcc_arm: includes: - source/hic_hal/atmel/sam3u2c/gcc diff --git a/records/hic_hal/stm32f103xb.yaml b/records/hic_hal/stm32f103xb.yaml index 991c5ce98..c25777fbe 100644 --- a/records/hic_hal/stm32f103xb.yaml +++ b/records/hic_hal/stm32f103xb.yaml @@ -37,6 +37,15 @@ tool_specific: sources: hic_hal: - source/hic_hal/stm32/stm32f103xb/armcc + make_armclang: + misc: + c_flags: + - -mcpu=cortex-m3 + asm_flags: + - -mcpu=cortex-m3 + sources: + hic_hal: + - source/hic_hal/stm32/stm32f103xb/armcc make_gcc_arm: includes: - source/hic_hal/stm32/stm32f103xb/gcc diff --git a/records/tools/make_armclang.yaml b/records/tools/make_armclang.yaml new file mode 100644 index 000000000..20157e3c8 --- /dev/null +++ b/records/tools/make_armclang.yaml @@ -0,0 +1,43 @@ +tool_specific: + make_armclang: + mcu: + - cortex-m0 + macros: + - + linker_file: + - source/daplink/daplink.sct + misc: + asm_flags: + - -g + cpp_flags: + - --target=arm-arm-none-eabi + c_flags: + - --target=arm-arm-none-eabi + - -Oz + - -g + - --std=c99 + - -fdata-sections + - -ffunction-sections + - -fno-builtin + - -fshort-enums + - -fshort-wchar + - -funsigned-char + - -masm=auto + - -nostdlib + - -Wall + - -Wno-error=cpp + - -Warmcc-pragma-thumb + - -Wno-ignored-optimization-argument + - -Wno-unused-command-line-argument + ld_flags: + - --bestdebug + - --summary_stderr + - --info=summarysizes,sizes,totals,unused,veneers + - --load_addr_map_info + - --xref + - --callgraph + - --symbols + pre_build_script: + - tools/pre_build_script.sh + post_build_script: + - tools/post_build_script_armclang.sh diff --git a/source/daplink/daplink.ac6.sct b/source/daplink/daplink.ac6.sct new file mode 100644 index 000000000..34bf02cd4 --- /dev/null +++ b/source/daplink/daplink.ac6.sct @@ -0,0 +1,60 @@ +;/** +; * @file daplink.sct +; * @brief Memory layout for DAPLink Interface Firmware +; * +; * DAPLink Interface Firmware +; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +#include "daplink_addr.h" + +LR_IROM1 DAPLINK_ROM_APP_START DAPLINK_ROM_APP_SIZE { + + ER_IROM1 DAPLINK_ROM_APP_START DAPLINK_ROM_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 DAPLINK_RAM_APP_START DAPLINK_RAM_APP_SIZE { ; RW data + .ANY (ram_func) + .ANY (+RW +ZI) + main.o (+RW +ZI) + startup_*.o (+RW +ZI) + .ANY (RAM1) + } + + #if defined(DAPLINK_RAM_APP2_START) + RW_IRAM2 DAPLINK_RAM_APP2_START DAPLINK_RAM_APP2_SIZE { ; RW data + .ANY (+RW +ZI) + .ANY (RAM2) + } + #endif + + RW_CONFIG DAPLINK_RAM_SHARED_START UNINIT DAPLINK_RAM_SHARED_SIZE { + .ANY (cfgram) + } + + ER_IROM1_CRC (DAPLINK_ROM_APP_START + DAPLINK_ROM_APP_SIZE - 4) FIXED FILL 0xFFFFFFFF 4 { + ; reserve space for the CRC + } +} + +LR_CONFIG DAPLINK_ROM_CONFIG_USER_START DAPLINK_ROM_CONFIG_USER_SIZE { ; reserve last sector for config data + ER_CONFIG DAPLINK_ROM_CONFIG_USER_START UNINIT DAPLINK_ROM_CONFIG_USER_SIZE { + .ANY (cfgrom) + } +} diff --git a/tools/post_build_script_armclang.sh b/tools/post_build_script_armclang.sh new file mode 100755 index 000000000..c8fd0fce6 --- /dev/null +++ b/tools/post_build_script_armclang.sh @@ -0,0 +1,36 @@ +#!/bin/bash -e +## +## DAPLink Interface Firmware +## Copyright (c) 2009-2016, ARM Limited, All Rights Reserved +## SPDX-License-Identifier: Apache-2.0 +## +## Licensed under the Apache License, Version 2.0 (the "License"); you may +## not use this file except in compliance with the License. +## You may obtain a copy of the License at +## +## http://www.apache.org/licenses/LICENSE-2.0 +## +## Unless required by applicable law or agreed to in writing, software +## distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +## WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +## See the License for the specific language governing permissions and +## limitations under the License. +## + +PROJECT_DIR=build +TOOLS=../../../tools +PROJECT_NAME=$(basename $PWD) + +INFILE=${PROJECT_DIR}/${PROJECT_NAME}.hex +OUTBASE=${PROJECT_DIR}/${PROJECT_NAME}_crc +CRCBIN=${OUTBASE}.bin + +fromelf --bincombined $PROJECT_DIR/${PROJECT_NAME}.axf --output=$PROJECT_DIR/firmware.bin + +fromelf --i32combined $PROJECT_DIR/${PROJECT_NAME}.axf --output=$PROJECT_DIR/firmware.hex + +# Only execute the post build script if the input is newer than output, or the +# output doesn't exist. +if [[ "$INFILE" -nt "$CRCBIN" ]]; then + python "${TOOLS}/post_build_script.py" "$INFILE" "$OUTBASE" +fi From 3c096cc4465b8ba7c1edd85dad96287f662ff4e2 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 14 Dec 2020 16:32:37 -0600 Subject: [PATCH 058/617] The settings are compiler-specific not build tool-specific --- projects.yaml | 6 +++--- records/daplink/bootloader.yaml | 4 ++-- records/daplink/interface.yaml | 4 ++-- records/hic_hal/k20dx.yaml | 6 +++--- records/hic_hal/k26f.yaml | 6 +++--- records/hic_hal/kl26z.yaml | 6 +++--- records/hic_hal/lpc11u35.yaml | 6 +++--- records/hic_hal/lpc4322.yaml | 6 +++--- records/hic_hal/m48ssidae.yaml | 6 +++--- records/hic_hal/max32620.yaml | 6 +++--- records/hic_hal/max32625.yaml | 6 +++--- records/hic_hal/sam3u2c.yaml | 6 +++--- records/hic_hal/stm32f103xb.yaml | 6 +++--- records/rtos/rtos-cm0.yaml | 6 +++--- records/rtos/rtos-cm3.yaml | 6 +++--- records/rtos/rtos-cm4.yaml | 6 +++--- records/tools/{make_armcc.yaml => armcc.yaml} | 2 +- records/tools/{make_armclang.yaml => armclang.yaml} | 2 +- records/tools/{make_gcc_arm.yaml => gcc_arm.yaml} | 2 +- 19 files changed, 49 insertions(+), 49 deletions(-) rename records/tools/{make_armcc.yaml => armcc.yaml} (98%) rename records/tools/{make_armclang.yaml => armclang.yaml} (98%) rename records/tools/{make_gcc_arm.yaml => gcc_arm.yaml} (98%) diff --git a/projects.yaml b/projects.yaml index 9f183b4b2..880b52457 100644 --- a/projects.yaml +++ b/projects.yaml @@ -8,9 +8,9 @@ settings: module: tools: &module_tools - - records/tools/make_gcc_arm.yaml - - records/tools/make_armcc.yaml - - records/tools/make_armclang.yaml + - records/tools/gcc_arm.yaml + - records/tools/armcc.yaml + - records/tools/armclang.yaml - records/tools/version.yaml bl: &module_bl - *module_tools diff --git a/records/daplink/bootloader.yaml b/records/daplink/bootloader.yaml index 1bc9a5b48..e390e4d9f 100644 --- a/records/daplink/bootloader.yaml +++ b/records/daplink/bootloader.yaml @@ -19,12 +19,12 @@ tool_specific: misc: ld_flags: - --predefine="-DDAPLINK_BL" - make_armcc: + armcc: linker_file: - source/daplink/daplink.sct misc: ld_flags: - --predefine="-DDAPLINK_BL" - make_armclang: + armclang: linker_file: - source/daplink/daplink.ac6.sct diff --git a/records/daplink/interface.yaml b/records/daplink/interface.yaml index 3dac19046..f3d517259 100644 --- a/records/daplink/interface.yaml +++ b/records/daplink/interface.yaml @@ -19,12 +19,12 @@ tool_specific: misc: ld_flags: - --predefine="-DDAPLINK_IF" - make_armcc: + armcc: linker_file: - source/daplink/daplink.sct misc: ld_flags: - --predefine="-DDAPLINK_IF" - make_armclang: + armclang: linker_file: - source/daplink/daplink.ac6.sct diff --git a/records/hic_hal/k20dx.yaml b/records/hic_hal/k20dx.yaml index 12a28104f..9448dd79d 100644 --- a/records/hic_hal/k20dx.yaml +++ b/records/hic_hal/k20dx.yaml @@ -32,18 +32,18 @@ tool_specific: sources: hic_hal: - source/hic_hal/freescale/k20dx/armcc - make_armcc: + armcc: misc: ld_flags: - --predefine="-Isource\hic_hal\freescale\k20dx" sources: hic_hal: - source/hic_hal/freescale/k20dx/armcc - make_armclang: + armclang: sources: hic_hal: - source/hic_hal/freescale/k20dx/armcc - make_gcc_arm: + gcc_arm: linker_file: - source/hic_hal/freescale/kinetis.ld includes: diff --git a/records/hic_hal/k26f.yaml b/records/hic_hal/k26f.yaml index ae122fb78..b3880d64a 100644 --- a/records/hic_hal/k26f.yaml +++ b/records/hic_hal/k26f.yaml @@ -38,7 +38,7 @@ tool_specific: sources: hic_hal: - source/hic_hal/freescale/k26f/armcc - make_armcc: + armcc: misc: ld_flags: - --predefine="-Isource\hic_hal\freescale\k26f" @@ -52,7 +52,7 @@ tool_specific: sources: hic_hal: - source/hic_hal/freescale/k26f/armcc - make_armclang: + armclang: misc: c_flags: - -mno-unaligned-access @@ -63,7 +63,7 @@ tool_specific: sources: hic_hal: - source/hic_hal/freescale/k26f/armcc - make_gcc_arm: + gcc_arm: linker_file: - source/hic_hal/freescale/kinetis.ld includes: diff --git a/records/hic_hal/kl26z.yaml b/records/hic_hal/kl26z.yaml index 09e87f67b..7e578f2ca 100644 --- a/records/hic_hal/kl26z.yaml +++ b/records/hic_hal/kl26z.yaml @@ -32,18 +32,18 @@ tool_specific: sources: hic_hal: - source/hic_hal/freescale/kl26z/armcc - make_armcc: + armcc: misc: ld_flags: - --predefine="-Isource\hic_hal\freescale\kl26z" sources: hic_hal: - source/hic_hal/freescale/kl26z/armcc - make_armclang: + armclang: sources: hic_hal: - source/hic_hal/freescale/kl26z/armcc - make_gcc_arm: + gcc_arm: linker_file: - source/hic_hal/freescale/kinetis.ld includes: diff --git a/records/hic_hal/lpc11u35.yaml b/records/hic_hal/lpc11u35.yaml index ad1bebaa1..1d8861c1e 100644 --- a/records/hic_hal/lpc11u35.yaml +++ b/records/hic_hal/lpc11u35.yaml @@ -21,18 +21,18 @@ tool_specific: sources: hic_hal: - source/hic_hal/nxp/lpc11u35/armcc - make_armcc: + armcc: misc: ld_flags: - --predefine="-Isource\hic_hal\nxp\lpc11u35" sources: hic_hal: - source/hic_hal/nxp/lpc11u35/armcc - make_armclang: + armclang: sources: hic_hal: - source/hic_hal/nxp/lpc11u35/armcc - make_gcc_arm: + gcc_arm: linker_file: - source/hic_hal/nxp/lpc11u35/gcc/lpc11u35.ld includes: diff --git a/records/hic_hal/lpc4322.yaml b/records/hic_hal/lpc4322.yaml index 51d5b15a2..30b895561 100644 --- a/records/hic_hal/lpc4322.yaml +++ b/records/hic_hal/lpc4322.yaml @@ -23,18 +23,18 @@ tool_specific: sources: hic_hal: - source/hic_hal/nxp/lpc4322/armcc - make_armcc: + armcc: misc: ld_flags: - --predefine="-Isource\hic_hal\nxp\lpc4322" sources: hic_hal: - source/hic_hal/nxp/lpc4322/armcc - make_armclang: + armclang: sources: hic_hal: - source/hic_hal/nxp/lpc4322/armcc - make_gcc_arm: + gcc_arm: includes: - source/hic_hal/nxp/lpc4322/gcc sources: diff --git a/records/hic_hal/m48ssidae.yaml b/records/hic_hal/m48ssidae.yaml index 5ce69317d..25a6d4d9c 100644 --- a/records/hic_hal/m48ssidae.yaml +++ b/records/hic_hal/m48ssidae.yaml @@ -27,18 +27,18 @@ tool_specific: sources: hic_hal: - source/hic_hal/nuvoton/m48ssidae/armcc - make_armcc: + armcc: misc: ld_flags: - --predefine="-Isource\hic_hal\nuvoton\m48ssidae" sources: hic_hal: - source/hic_hal/nuvoton/m48ssidae/armcc - make_armclang: + armclang: sources: hic_hal: - source/hic_hal/nuvoton/m48ssidae/armcc - make_gcc_arm: + gcc_arm: includes: - source/hic_hal/nuvoton/m48ssidae/gcc sources: diff --git a/records/hic_hal/max32620.yaml b/records/hic_hal/max32620.yaml index 041018657..25638ea6b 100644 --- a/records/hic_hal/max32620.yaml +++ b/records/hic_hal/max32620.yaml @@ -21,18 +21,18 @@ tool_specific: sources: hic_hal: - source/hic_hal/maxim/max32620/armcc - make_armcc: + armcc: misc: ld_flags: - --predefine="-Isource\hic_hal\maxim\max32620" sources: hic_hal: - source/hic_hal/maxim/max32620/armcc - make_armclang: + armclang: sources: hic_hal: - source/hic_hal/maxim/max32620/armcc - make_gcc_arm: + gcc_arm: includes: - source/hic_hal/maxim/max32620/gcc sources: diff --git a/records/hic_hal/max32625.yaml b/records/hic_hal/max32625.yaml index dc99e6bbd..0cb34defa 100644 --- a/records/hic_hal/max32625.yaml +++ b/records/hic_hal/max32625.yaml @@ -21,18 +21,18 @@ tool_specific: sources: hic_hal: - source/hic_hal/maxim/max32625/armcc - make_armcc: + armcc: misc: ld_flags: - --predefine="-Isource\hic_hal\maxim\max32625" sources: hic_hal: - source/hic_hal/maxim/max32625/armcc - make_armclang: + armclang: sources: hic_hal: - source/hic_hal/maxim/max32625/armcc - make_gcc_arm: + gcc_arm: includes: - source/hic_hal/maxim/max32625/gcc sources: diff --git a/records/hic_hal/sam3u2c.yaml b/records/hic_hal/sam3u2c.yaml index d127dd665..1d5645e37 100644 --- a/records/hic_hal/sam3u2c.yaml +++ b/records/hic_hal/sam3u2c.yaml @@ -24,18 +24,18 @@ tool_specific: sources: hic_hal: - source/hic_hal/atmel/sam3u2c/armcc - make_armcc: + armcc: misc: ld_flags: - --predefine="-Isource\hic_hal\atmel\sam3u2c" sources: hic_hal: - source/hic_hal/atmel/sam3u2c/armcc - make_armclang: + armclang: sources: hic_hal: - source/hic_hal/atmel/sam3u2c/armcc - make_gcc_arm: + gcc_arm: includes: - source/hic_hal/atmel/sam3u2c/gcc sources: diff --git a/records/hic_hal/stm32f103xb.yaml b/records/hic_hal/stm32f103xb.yaml index c25777fbe..9fb26f90c 100644 --- a/records/hic_hal/stm32f103xb.yaml +++ b/records/hic_hal/stm32f103xb.yaml @@ -30,14 +30,14 @@ tool_specific: sources: hic_hal: - source/hic_hal/stm32/stm32f103xb/armcc - make_armcc: + armcc: misc: ld_flags: - --predefine="-Isource\hic_hal\stm32\stm32f103xb" sources: hic_hal: - source/hic_hal/stm32/stm32f103xb/armcc - make_armclang: + armclang: misc: c_flags: - -mcpu=cortex-m3 @@ -46,7 +46,7 @@ tool_specific: sources: hic_hal: - source/hic_hal/stm32/stm32f103xb/armcc - make_gcc_arm: + gcc_arm: includes: - source/hic_hal/stm32/stm32f103xb/gcc sources: diff --git a/records/rtos/rtos-cm0.yaml b/records/rtos/rtos-cm0.yaml index 6713abdd3..76b8de45a 100644 --- a/records/rtos/rtos-cm0.yaml +++ b/records/rtos/rtos-cm0.yaml @@ -23,7 +23,7 @@ tool_specific: - source/rtos/rt_Timer.c - source/rtos/RTX_Config.c - source/rtos/cmsis_os2_port.c - make_armcc: + armcc: includes: - source/rtos sources: @@ -43,7 +43,7 @@ tool_specific: - source/rtos/rt_Timer.c - source/rtos/RTX_Config.c - source/rtos/cmsis_os2_port.c - make_armclang: + armclang: includes: - source/rtos2/Include - source/rtos2/RTX/Include @@ -63,7 +63,7 @@ tool_specific: - source/rtos2/RTX/Source/rtx_thread.c - source/rtos2/RTX/Source/rtx_timer.c - source/rtos2/Source/os_systick.c - make_gcc_arm: + gcc_arm: includes: - source/rtos2/Include - source/rtos2/RTX/Include diff --git a/records/rtos/rtos-cm3.yaml b/records/rtos/rtos-cm3.yaml index 360afacfa..2fac4704b 100644 --- a/records/rtos/rtos-cm3.yaml +++ b/records/rtos/rtos-cm3.yaml @@ -23,7 +23,7 @@ tool_specific: - source/rtos/rt_Timer.c - source/rtos/RTX_Config.c - source/rtos/cmsis_os2_port.c - make_armcc: + armcc: includes: - source/rtos sources: @@ -43,7 +43,7 @@ tool_specific: - source/rtos/rt_Timer.c - source/rtos/RTX_Config.c - source/rtos/cmsis_os2_port.c - make_armclang: + armclang: includes: - source/rtos2/Include - source/rtos2/RTX/Include @@ -63,7 +63,7 @@ tool_specific: - source/rtos2/RTX/Source/rtx_thread.c - source/rtos2/RTX/Source/rtx_timer.c - source/rtos2/Source/os_systick.c - make_gcc_arm: + gcc_arm: includes: - source/rtos2/Include - source/rtos2/RTX/Include diff --git a/records/rtos/rtos-cm4.yaml b/records/rtos/rtos-cm4.yaml index 9bf527ee7..18d6c5bb8 100644 --- a/records/rtos/rtos-cm4.yaml +++ b/records/rtos/rtos-cm4.yaml @@ -25,7 +25,7 @@ tool_specific: - source/rtos/rt_Timer.c - source/rtos/RTX_Config.c - source/rtos/cmsis_os2_port.c - make_armcc: + armcc: includes: - source/rtos sources: @@ -45,7 +45,7 @@ tool_specific: - source/rtos/rt_Timer.c - source/rtos/RTX_Config.c - source/rtos/cmsis_os2_port.c - make_armclang: + armclang: includes: - source/rtos2/Include - source/rtos2/RTX/Include @@ -65,7 +65,7 @@ tool_specific: - source/rtos2/RTX/Source/rtx_thread.c - source/rtos2/RTX/Source/rtx_timer.c - source/rtos2/Source/os_systick.c - make_gcc_arm: + gcc_arm: includes: - source/rtos2/Include - source/rtos2/RTX/Include diff --git a/records/tools/make_armcc.yaml b/records/tools/armcc.yaml similarity index 98% rename from records/tools/make_armcc.yaml rename to records/tools/armcc.yaml index 7104877ca..6e01229c2 100644 --- a/records/tools/make_armcc.yaml +++ b/records/tools/armcc.yaml @@ -1,5 +1,5 @@ tool_specific: - make_armcc: + armcc: mcu: - cortex-m0 macros: diff --git a/records/tools/make_armclang.yaml b/records/tools/armclang.yaml similarity index 98% rename from records/tools/make_armclang.yaml rename to records/tools/armclang.yaml index 20157e3c8..0d8d2f457 100644 --- a/records/tools/make_armclang.yaml +++ b/records/tools/armclang.yaml @@ -1,5 +1,5 @@ tool_specific: - make_armclang: + armclang: mcu: - cortex-m0 macros: diff --git a/records/tools/make_gcc_arm.yaml b/records/tools/gcc_arm.yaml similarity index 98% rename from records/tools/make_gcc_arm.yaml rename to records/tools/gcc_arm.yaml index afeabf242..3d3424290 100644 --- a/records/tools/make_gcc_arm.yaml +++ b/records/tools/gcc_arm.yaml @@ -1,5 +1,5 @@ tool_specific: - make_gcc_arm: + gcc_arm: mcu: - cortex-m0 macros: From f97da71879934a9019b11c88dc9d4f6bfb429201 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 14 Dec 2020 17:55:52 -0600 Subject: [PATCH 059/617] Align armclang flags with project-generator changes --- records/tools/armclang.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/records/tools/armclang.yaml b/records/tools/armclang.yaml index 0d8d2f457..a3a80b8c9 100644 --- a/records/tools/armclang.yaml +++ b/records/tools/armclang.yaml @@ -9,6 +9,8 @@ tool_specific: misc: asm_flags: - -g + - -x assembler-with-cpp + - -masm=auto cpp_flags: - --target=arm-arm-none-eabi c_flags: From 96d4ad59670d683cc5bff13766c09fe339a2d7e1 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 16 Dec 2020 19:36:42 -0600 Subject: [PATCH 060/617] Add LTO for Musca targets with GCC (code size too large) --- projects.yaml | 3 +++ records/tools/gcc_arm_lto.yaml | 9 +++++++++ 2 files changed, 12 insertions(+) create mode 100644 records/tools/gcc_arm_lto.yaml diff --git a/projects.yaml b/projects.yaml index 880b52457..ffde11799 100644 --- a/projects.yaml +++ b/projects.yaml @@ -627,14 +627,17 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/musca_a.yaml + - records/tools/gcc_arm_lto.yaml lpc11u35_musca_b_if: - *module_if - *module_hic_lpc11u35 - records/board/musca_b.yaml + - records/tools/gcc_arm_lto.yaml lpc11u35_musca_b_eflash_if: - *module_if - *module_hic_lpc11u35 - records/board/musca_b_eflash.yaml + - records/tools/gcc_arm_lto.yaml max32620_max32625mbed_if: - *module_if - *module_hic_max32620 diff --git a/records/tools/gcc_arm_lto.yaml b/records/tools/gcc_arm_lto.yaml new file mode 100644 index 000000000..cfedab4cc --- /dev/null +++ b/records/tools/gcc_arm_lto.yaml @@ -0,0 +1,9 @@ +tool_specific: + gcc_arm: + misc: + common_flags: + - -flto + ld_flags: + - -flto + - -flto-partition=none + - -fuse-linker-plugin From a109e26868157b93b6d59334a14da0591fb905c3 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 16 Dec 2020 19:38:16 -0600 Subject: [PATCH 061/617] The $@ trick only works with make --- records/tools/gcc_arm.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/records/tools/gcc_arm.yaml b/records/tools/gcc_arm.yaml index 3d3424290..f2befd94b 100644 --- a/records/tools/gcc_arm.yaml +++ b/records/tools/gcc_arm.yaml @@ -23,7 +23,6 @@ tool_specific: - -fshort-wchar - -fno-common - -ffreestanding - - -Wa,-adln=$@.lst - -fverbose-asm - -mno-unaligned-access ld_flags: @@ -40,3 +39,7 @@ tool_specific: - tools/pre_build_script.sh post_build_script: - tools/post_build_script_gcc.sh + make_gcc_arm: + misc: + common_flags: + - -Wa,-adln=$@.lst From c9975cb84b43c120c3f01555e743264e041243f9 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 17 Dec 2020 22:37:27 -0600 Subject: [PATCH 062/617] Convert pre/post-build shell script to python --- records/tools/armcc.yaml | 4 +-- records/tools/armclang.yaml | 4 +-- records/tools/gcc_arm.yaml | 4 +-- tools/post_build_script.py | 0 tools/post_build_script_armcc.py | 49 +++++++++++++++++++++++++++++ tools/post_build_script_armclang.py | 49 +++++++++++++++++++++++++++++ tools/post_build_script_gcc.py | 43 +++++++++++++++++++++++++ tools/pre_build_script.py | 2 +- 8 files changed, 148 insertions(+), 7 deletions(-) mode change 100644 => 100755 tools/post_build_script.py create mode 100755 tools/post_build_script_armcc.py create mode 100755 tools/post_build_script_armclang.py create mode 100755 tools/post_build_script_gcc.py mode change 100644 => 100755 tools/pre_build_script.py diff --git a/records/tools/armcc.yaml b/records/tools/armcc.yaml index 6e01229c2..95c5880fa 100644 --- a/records/tools/armcc.yaml +++ b/records/tools/armcc.yaml @@ -33,9 +33,9 @@ tool_specific: - --info veneers - --list "$@.map" pre_build_script: - - tools/pre_build_script.sh + - tools/pre_build_script.py post_build_script: - - tools/post_build_script_armcc.sh + - tools/post_build_script_armcc.py uvision: misc: asm_flags: diff --git a/records/tools/armclang.yaml b/records/tools/armclang.yaml index a3a80b8c9..530258a93 100644 --- a/records/tools/armclang.yaml +++ b/records/tools/armclang.yaml @@ -40,6 +40,6 @@ tool_specific: - --callgraph - --symbols pre_build_script: - - tools/pre_build_script.sh + - tools/pre_build_script.py post_build_script: - - tools/post_build_script_armclang.sh + - tools/post_build_script_armclang.py diff --git a/records/tools/gcc_arm.yaml b/records/tools/gcc_arm.yaml index f2befd94b..acdb135b8 100644 --- a/records/tools/gcc_arm.yaml +++ b/records/tools/gcc_arm.yaml @@ -36,9 +36,9 @@ tool_specific: - -Wl,--no-wchar-size-warning - -Wl,--print-memory-usage pre_build_script: - - tools/pre_build_script.sh + - tools/pre_build_script.py post_build_script: - - tools/post_build_script_gcc.sh + - tools/post_build_script_gcc.py make_gcc_arm: misc: common_flags: diff --git a/tools/post_build_script.py b/tools/post_build_script.py old mode 100644 new mode 100755 diff --git a/tools/post_build_script_armcc.py b/tools/post_build_script_armcc.py new file mode 100755 index 000000000..f2c017733 --- /dev/null +++ b/tools/post_build_script_armcc.py @@ -0,0 +1,49 @@ +#!/usr/bin/env python +# +# DAPLink Interface Firmware +# Copyright (c) 2009-2020, ARM Limited, All Rights Reserved +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +import os +import subprocess +from post_build_script import post_build_script + +project_dir = 'build' +# project_dir = os.path.join(os.getcwd(), 'build') +project_name = os.path.basename(os.getcwd()) +infile = os.path.join(project_dir, project_name + '.hex') +outbase = os.path.join(project_dir, project_name + '_crc') + +subprocess.call(['fromelf', '--bin', os.path.join(project_dir, project_name + '.axf'), + '--output', os.path.join(project_dir, 'firmware.bin')]) +subprocess.call(['fromelf', '--i32', os.path.join(project_dir, project_name + '.axf'), + '--output', os.path.join(project_dir, 'firmware.hex')]) + +if not os.path.exists(infile): + print("File '%s' is missing" % infile) + exit(-1) + +run = False +if not os.path.exists(outbase + '.bin'): + run = True +elif os.path.getmtime(infile) >= os.path.getmtime(outbase + '.bin'): + run = True +# else: +# print("%s already up-to-date" % outbase) + +if run: + # print("%s -> %s" % (infile, outbase)) + post_build_script(infile, outbase) diff --git a/tools/post_build_script_armclang.py b/tools/post_build_script_armclang.py new file mode 100755 index 000000000..9ff40f452 --- /dev/null +++ b/tools/post_build_script_armclang.py @@ -0,0 +1,49 @@ +#!/usr/bin/env python +# +# DAPLink Interface Firmware +# Copyright (c) 2009-2020, ARM Limited, All Rights Reserved +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +import os +import subprocess +from post_build_script import post_build_script + +project_dir = 'build' +# project_dir = os.path.join(os.getcwd(), 'build') +project_name = os.path.basename(os.getcwd()) +infile = os.path.join(project_dir, project_name + '.hex') +outbase = os.path.join(project_dir, project_name + '_crc') + +subprocess.call(['fromelf', '--bincombined', os.path.join(project_dir, project_name + '.axf'), + '--output', os.path.join(project_dir, 'firmware.bin')]) +subprocess.call(['fromelf', '--i32combined', os.path.join(project_dir, project_name + '.axf'), + '--output', os.path.join(project_dir, 'firmware.hex')]) + +if not os.path.exists(infile): + print("File '%s' is missing" % infile) + exit(-1) + +run = False +if not os.path.exists(outbase + '.bin'): + run = True +elif os.path.getmtime(infile) >= os.path.getmtime(outbase + '.bin'): + run = True +# else: +# print("%s already up-to-date" % outbase) + +if run: + # print("%s -> %s" % (infile, outbase)) + post_build_script(infile, outbase) diff --git a/tools/post_build_script_gcc.py b/tools/post_build_script_gcc.py new file mode 100755 index 000000000..9b0101885 --- /dev/null +++ b/tools/post_build_script_gcc.py @@ -0,0 +1,43 @@ +#!/usr/bin/env python +# +# DAPLink Interface Firmware +# Copyright (c) 2009-2020, ARM Limited, All Rights Reserved +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +import os +from post_build_script import post_build_script + +project_dir = 'build' +# project_dir = os.path.join(os.getcwd(), 'build') +project_name = os.path.basename(os.getcwd()) +infile = os.path.join(project_dir, project_name + '.hex') +outbase = os.path.join(project_dir, project_name + '_crc') + +if not os.path.exists(infile): + print("File '%s' is missing" % infile) + exit(-1) + +run = False +if not os.path.exists(outbase + '.bin'): + run = True +elif os.path.getmtime(infile) >= os.path.getmtime(outbase + '.bin'): + run = True +# else: +# print("%s already up-to-date" % outbase) + +if run: + # print("%s -> %s" % (infile, outbase)) + post_build_script(infile, outbase) diff --git a/tools/pre_build_script.py b/tools/pre_build_script.py old mode 100644 new mode 100755 index b9639653d..2046a6e08 --- a/tools/pre_build_script.py +++ b/tools/pre_build_script.py @@ -1,4 +1,4 @@ -# +#!/usr/bin/env python # DAPLink Interface Firmware # Copyright (c) 2009-2019, ARM Limited, All Rights Reserved # SPDX-License-Identifier: Apache-2.0 From c6770ce57beea3b7bebe6a1eb7d1f2e0e1fc0847 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 18 Dec 2020 18:16:32 -0600 Subject: [PATCH 063/617] Suprefluous quote, use '/' path separator for armcc, map file in progen --- records/daplink/bootloader.yaml | 4 ++-- records/daplink/interface.yaml | 4 ++-- records/hic_hal/k20dx.yaml | 2 +- records/hic_hal/k26f.yaml | 2 +- records/hic_hal/kl26z.yaml | 2 +- records/hic_hal/lpc11u35.yaml | 2 +- records/hic_hal/lpc4322.yaml | 2 +- records/hic_hal/m48ssidae.yaml | 2 +- records/hic_hal/max32620.yaml | 2 +- records/hic_hal/max32625.yaml | 2 +- records/hic_hal/sam3u2c.yaml | 2 +- records/hic_hal/stm32f103xb.yaml | 2 +- records/tools/armcc.yaml | 8 +------- 13 files changed, 15 insertions(+), 21 deletions(-) diff --git a/records/daplink/bootloader.yaml b/records/daplink/bootloader.yaml index e390e4d9f..11e1d7644 100644 --- a/records/daplink/bootloader.yaml +++ b/records/daplink/bootloader.yaml @@ -18,13 +18,13 @@ tool_specific: - source/daplink/daplink.sct misc: ld_flags: - - --predefine="-DDAPLINK_BL" + - --predefine=-DDAPLINK_BL armcc: linker_file: - source/daplink/daplink.sct misc: ld_flags: - - --predefine="-DDAPLINK_BL" + - --predefine=-DDAPLINK_BL armclang: linker_file: - source/daplink/daplink.ac6.sct diff --git a/records/daplink/interface.yaml b/records/daplink/interface.yaml index f3d517259..583a2ff4e 100644 --- a/records/daplink/interface.yaml +++ b/records/daplink/interface.yaml @@ -18,13 +18,13 @@ tool_specific: - source/daplink/daplink.sct misc: ld_flags: - - --predefine="-DDAPLINK_IF" + - --predefine=-DDAPLINK_IF armcc: linker_file: - source/daplink/daplink.sct misc: ld_flags: - - --predefine="-DDAPLINK_IF" + - --predefine=-DDAPLINK_IF armclang: linker_file: - source/daplink/daplink.ac6.sct diff --git a/records/hic_hal/k20dx.yaml b/records/hic_hal/k20dx.yaml index 9448dd79d..e29b96cab 100644 --- a/records/hic_hal/k20dx.yaml +++ b/records/hic_hal/k20dx.yaml @@ -35,7 +35,7 @@ tool_specific: armcc: misc: ld_flags: - - --predefine="-Isource\hic_hal\freescale\k20dx" + - --predefine="-Isource/hic_hal/freescale/k20dx" sources: hic_hal: - source/hic_hal/freescale/k20dx/armcc diff --git a/records/hic_hal/k26f.yaml b/records/hic_hal/k26f.yaml index b3880d64a..831113647 100644 --- a/records/hic_hal/k26f.yaml +++ b/records/hic_hal/k26f.yaml @@ -41,7 +41,7 @@ tool_specific: armcc: misc: ld_flags: - - --predefine="-Isource\hic_hal\freescale\k26f" + - --predefine="-Isource/hic_hal/freescale/k26f" c_flags: - --no_unaligned_access - --diag_suppress=66 # disable warning about enums not fitting in signed 32-bit diff --git a/records/hic_hal/kl26z.yaml b/records/hic_hal/kl26z.yaml index 7e578f2ca..c6bf46995 100644 --- a/records/hic_hal/kl26z.yaml +++ b/records/hic_hal/kl26z.yaml @@ -35,7 +35,7 @@ tool_specific: armcc: misc: ld_flags: - - --predefine="-Isource\hic_hal\freescale\kl26z" + - --predefine="-Isource/hic_hal/freescale/kl26z" sources: hic_hal: - source/hic_hal/freescale/kl26z/armcc diff --git a/records/hic_hal/lpc11u35.yaml b/records/hic_hal/lpc11u35.yaml index 1d8861c1e..01a9db526 100644 --- a/records/hic_hal/lpc11u35.yaml +++ b/records/hic_hal/lpc11u35.yaml @@ -24,7 +24,7 @@ tool_specific: armcc: misc: ld_flags: - - --predefine="-Isource\hic_hal\nxp\lpc11u35" + - --predefine="-Isource/hic_hal/nxp/lpc11u35" sources: hic_hal: - source/hic_hal/nxp/lpc11u35/armcc diff --git a/records/hic_hal/lpc4322.yaml b/records/hic_hal/lpc4322.yaml index 30b895561..d2c64ca76 100644 --- a/records/hic_hal/lpc4322.yaml +++ b/records/hic_hal/lpc4322.yaml @@ -26,7 +26,7 @@ tool_specific: armcc: misc: ld_flags: - - --predefine="-Isource\hic_hal\nxp\lpc4322" + - --predefine="-Isource/hic_hal/nxp/lpc4322" sources: hic_hal: - source/hic_hal/nxp/lpc4322/armcc diff --git a/records/hic_hal/m48ssidae.yaml b/records/hic_hal/m48ssidae.yaml index 25a6d4d9c..819bee598 100644 --- a/records/hic_hal/m48ssidae.yaml +++ b/records/hic_hal/m48ssidae.yaml @@ -30,7 +30,7 @@ tool_specific: armcc: misc: ld_flags: - - --predefine="-Isource\hic_hal\nuvoton\m48ssidae" + - --predefine="-Isource/hic_hal/nuvoton/m48ssidae" sources: hic_hal: - source/hic_hal/nuvoton/m48ssidae/armcc diff --git a/records/hic_hal/max32620.yaml b/records/hic_hal/max32620.yaml index 25638ea6b..a348320ec 100644 --- a/records/hic_hal/max32620.yaml +++ b/records/hic_hal/max32620.yaml @@ -24,7 +24,7 @@ tool_specific: armcc: misc: ld_flags: - - --predefine="-Isource\hic_hal\maxim\max32620" + - --predefine="-Isource/hic_hal/maxim/max32620" sources: hic_hal: - source/hic_hal/maxim/max32620/armcc diff --git a/records/hic_hal/max32625.yaml b/records/hic_hal/max32625.yaml index 0cb34defa..47e3a9353 100644 --- a/records/hic_hal/max32625.yaml +++ b/records/hic_hal/max32625.yaml @@ -24,7 +24,7 @@ tool_specific: armcc: misc: ld_flags: - - --predefine="-Isource\hic_hal\maxim\max32625" + - --predefine="-Isource/hic_hal/maxim/max32625" sources: hic_hal: - source/hic_hal/maxim/max32625/armcc diff --git a/records/hic_hal/sam3u2c.yaml b/records/hic_hal/sam3u2c.yaml index 1d5645e37..5807849ca 100644 --- a/records/hic_hal/sam3u2c.yaml +++ b/records/hic_hal/sam3u2c.yaml @@ -27,7 +27,7 @@ tool_specific: armcc: misc: ld_flags: - - --predefine="-Isource\hic_hal\atmel\sam3u2c" + - --predefine="-Isource/hic_hal/atmel/sam3u2c" sources: hic_hal: - source/hic_hal/atmel/sam3u2c/armcc diff --git a/records/hic_hal/stm32f103xb.yaml b/records/hic_hal/stm32f103xb.yaml index 9fb26f90c..361842bb0 100644 --- a/records/hic_hal/stm32f103xb.yaml +++ b/records/hic_hal/stm32f103xb.yaml @@ -33,7 +33,7 @@ tool_specific: armcc: misc: ld_flags: - - --predefine="-Isource\hic_hal\stm32\stm32f103xb" + - --predefine="-Isource/hic_hal/stm32/stm32f103xb" sources: hic_hal: - source/hic_hal/stm32/stm32f103xb/armcc diff --git a/records/tools/armcc.yaml b/records/tools/armcc.yaml index 95c5880fa..06e469274 100644 --- a/records/tools/armcc.yaml +++ b/records/tools/armcc.yaml @@ -21,17 +21,11 @@ tool_specific: ld_flags: - --bestdebug - --summary_stderr - - --info summarysizes - - --map - --load_addr_map_info - --xref - --callgraph - --symbols - - --info sizes - - --info totals - - --info unused - - --info veneers - - --list "$@.map" + - --info summarysizes,sizes,totals,unused,veneers pre_build_script: - tools/pre_build_script.py post_build_script: From 42636d6789fdf0a8fd190f3b4ca574442569a556 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 21 Dec 2020 17:11:10 -0600 Subject: [PATCH 064/617] Fix .sct file for main.c renames --- source/daplink/daplink.ac6.sct | 2 +- source/daplink/daplink.sct | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/source/daplink/daplink.ac6.sct b/source/daplink/daplink.ac6.sct index 34bf02cd4..c6bbe86c3 100644 --- a/source/daplink/daplink.ac6.sct +++ b/source/daplink/daplink.ac6.sct @@ -32,7 +32,7 @@ LR_IROM1 DAPLINK_ROM_APP_START DAPLINK_ROM_APP_SIZE { RW_IRAM1 DAPLINK_RAM_APP_START DAPLINK_RAM_APP_SIZE { ; RW data .ANY (ram_func) .ANY (+RW +ZI) - main.o (+RW +ZI) + main_*.o (+RW +ZI) startup_*.o (+RW +ZI) .ANY (RAM1) } diff --git a/source/daplink/daplink.sct b/source/daplink/daplink.sct index d27de99c2..2882529fe 100644 --- a/source/daplink/daplink.sct +++ b/source/daplink/daplink.sct @@ -33,7 +33,7 @@ LR_IROM1 DAPLINK_ROM_APP_START DAPLINK_ROM_APP_SIZE { RW_IRAM1 DAPLINK_RAM_APP_START DAPLINK_RAM_APP_SIZE { ; RW data .ANY (ram_func) .ANY (+RW +ZI) - main.o (+RW +ZI) + main_*.o (+RW +ZI) startup_*.o (+RW +ZI) .ANY (RAM1) } From d363fadafcdbe392699462f81b5382de53dc03be Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 22 Dec 2020 08:48:29 -0600 Subject: [PATCH 065/617] Fixes related to RTX and GCC early start --- source/daplink/bootloader/main_bootloader.c | 11 +++++++++++ source/daplink/interface/main_interface.c | 12 ++++++++++++ 2 files changed, 23 insertions(+) diff --git a/source/daplink/bootloader/main_bootloader.c b/source/daplink/bootloader/main_bootloader.c index c1de1925e..95f382068 100644 --- a/source/daplink/bootloader/main_bootloader.c +++ b/source/daplink/bootloader/main_bootloader.c @@ -43,6 +43,17 @@ __asm(" .global __ARM_use_no_argv\n"); #endif +#if defined(__CC_ARM) || \ + (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +#ifndef __MICROLIB +void _platform_post_stackheap_init (void) { +} +#endif +#elif defined(__GNUC__) +void software_init_hook (void) { +} +#endif + #if defined(__CC_ARM) __asm void modify_stack_pointer_and_start_app(uint32_t r0_sp, uint32_t r1_pc) { diff --git a/source/daplink/interface/main_interface.c b/source/daplink/interface/main_interface.c index 938d9e3b4..6d8bfb395 100644 --- a/source/daplink/interface/main_interface.c +++ b/source/daplink/interface/main_interface.c @@ -51,6 +51,18 @@ __asm(" .global __ARM_use_no_argv\n"); #endif +#if defined(__CC_ARM) || \ + (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +#ifndef __MICROLIB +/* Avoids early implicit call to osKernelInitialize() */ +void _platform_post_stackheap_init (void) {} +#endif +#elif defined(__GNUC__) +/* Avoids early implicit call to osKernelInitialize() */ +void software_init_hook (void) {} +void __libc_init_array (void) {} +#endif + // Event flags for main task // Timers events #define FLAGS_MAIN_90MS (1 << 0) From c64e4792caaca4f9cbfc59207812f0d8acb20875 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 23 Dec 2020 00:24:14 -0600 Subject: [PATCH 066/617] Fix LPC11U35 GCC support --- .../nxp/lpc11u35/gcc/startup_LPC11Uxx.S | 284 -------- .../nxp/lpc11u35/gcc/startup_LPC11xx.S | 185 +++++ source/hic_hal/nxp/lpc11u35/system_LPC11Uxx.c | 634 ++++++++++-------- 3 files changed, 545 insertions(+), 558 deletions(-) delete mode 100644 source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11Uxx.S create mode 100644 source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11xx.S diff --git a/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11Uxx.S b/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11Uxx.S deleted file mode 100644 index 0a3218338..000000000 --- a/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11Uxx.S +++ /dev/null @@ -1,284 +0,0 @@ -/** - * @file startup_LPC11Uxx.S - * @brief - * - * DAPLink Interface Firmware - * Copyright (c) 2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - .syntax unified - .arch armv7-m - - .section .isr_vector, "a" - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long 0 - .long 0 - .long 0 - .long 0 /* Reserved*/ - .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ - .long DAPLINK_HIC_ID /* Compatibility*/ - .long DAPLINK_VERSION /* Version*/ - .long SVC_Handler /* SVCall Handler*/ - .long 0 - .long g_board_info /* Ptr to Board info, family info other target details*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* 32 External Interrupts*/ - .long FLEX_INT0_IRQHandler /* All GPIO pin can be routed to FLEX_INTx */ - .long FLEX_INT1_IRQHandler - .long FLEX_INT2_IRQHandler - .long FLEX_INT3_IRQHandler - .long FLEX_INT4_IRQHandler - .long FLEX_INT5_IRQHandler - .long FLEX_INT6_IRQHandler - .long FLEX_INT7_IRQHandler - .long GINT0_IRQHandler - .long GINT1_IRQHandler /* PIO0 (0:7) */ - .long Reserved1_IRQHandler /* Reserved */ - .long Reserved2_IRQHandler - .long Reserved3_IRQHandler - .long Reserved4_IRQHandler - .long SSP1_IRQHandler /* SSP1 */ - .long I2C_IRQHandler /* I2C */ - .long TIMER16_0_IRQHandler /* 16-bit Timer0 */ - .long TIMER16_1_IRQHandler /* 16-bit Timer1 */ - .long TIMER32_0_IRQHandler /* 32-bit Timer0 */ - .long TIMER32_1_IRQHandler /* 32-bit Timer1 */ - .long SSP0_IRQHandler /* SSP0 */ - .long UART_IRQHandler /* UART */ - .long USB_IRQHandler /* USB IRQ */ - .long USB_FIQHandler /* USB FIQ */ - .long ADC_IRQHandler /* A/D Converter */ - .long WDT_IRQHandler /* Watchdog timer */ - .long BOD_IRQHandler /* Brown Out Detect */ - .long FMC_IRQHandler /* IP2111 Flash Memory Controller */ - .long Reserved5_IRQHandler /* Reserved */ - .long Reserved6_IRQHandler /* Reserved */ - .long USBWakeup_IRQHandler /* USB wake up */ - .long Reserved7_IRQHandler /* Reserved */ - -#if defined(MBED_BOOTLOADER) - -// Set the CRP (Code Read Protection) configuration word at address 0x2FC to ensure that -// CRP is disabled. -#define CRP_KEY_ADDR (0x000002FC) -#define CRP_DISABLED (0xFFFFFFFF) - -1: // Fill up to CRP config word address. - .dcb.l ((CRP_KEY_ADDR - (1b - __isr_vector)) / 4) - -CRP_Key: - .long CRP_DISABLED - -#endif // MBED_BOOTLOADER - - .size __isr_vector, . - __isr_vector - - .text - .thumb - -/* Reset Handler */ - - .thumb_func - .align 2 - .globl Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - cpsid i /* Mask interrupts */ - .equ VTOR, 0xE000ED08 - ldr r0, =VTOR - ldr r1, =__isr_vector - str r1, [r0] - ldr r2, [r1] - msr msp, r2 -#ifndef __NO_SYSTEM_INIT - ldr r0,=SystemInit - blx r0 -#endif -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -#if 1 -/* Here are two copies of loop implemenations. First one favors code size - * and the second one favors performance. Default uses the first one. - * Change to "#if 0" to use the second one */ -.LC0: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .LC0 -#else - subs r3, r2 - ble .LC1 -.LC0: - subs r3, #4 - ldr r0, [r1, r3] - str r0, [r2, r3] - bgt .LC0 -.LC1: -#endif - -#ifdef __STARTUP_CLEAR_BSS -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * Loop to zero out BSS section, which uses following symbols - * in linker script: - * __bss_start__: start of BSS section. Must align to 4 - * __bss_end__: end of BSS section. Must align to 4 - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.LC2: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC2 -#endif /* __STARTUP_CLEAR_BSS */ - - cpsie i /* Unmask interrupts */ -#ifndef __START -#define __START _start -#endif -#ifndef __ATOLLIC__ - ldr r0,=__START - blx r0 -#else - ldr r0,=__libc_init_array - blx r0 - ldr r0,=main - bx r0 -#endif - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm - -/* Exception Handlers */ - def_irq_handler FLEX_INT0_IRQHandler /* All GPIO pin can be routed to FLEX_INTx */ - def_irq_handler FLEX_INT1_IRQHandler - def_irq_handler FLEX_INT2_IRQHandler - def_irq_handler FLEX_INT3_IRQHandler - def_irq_handler FLEX_INT4_IRQHandler - def_irq_handler FLEX_INT5_IRQHandler - def_irq_handler FLEX_INT6_IRQHandler - def_irq_handler FLEX_INT7_IRQHandler - def_irq_handler GINT0_IRQHandler - def_irq_handler GINT1_IRQHandler /* PIO0 (0:7) */ - def_irq_handler Reserved1_IRQHandler /* Reserved */ - def_irq_handler Reserved2_IRQHandler - def_irq_handler Reserved3_IRQHandler - def_irq_handler Reserved4_IRQHandler - def_irq_handler SSP1_IRQHandler /* SSP1 */ - def_irq_handler I2C_IRQHandler /* I2C */ - def_irq_handler TIMER16_0_IRQHandler /* 16-bit Timer0 */ - def_irq_handler TIMER16_1_IRQHandler /* 16-bit Timer1 */ - def_irq_handler TIMER32_0_IRQHandler /* 32-bit Timer0 */ - def_irq_handler TIMER32_1_IRQHandler /* 32-bit Timer1 */ - def_irq_handler SSP0_IRQHandler /* SSP0 */ - def_irq_handler UART_IRQHandler /* UART */ - def_irq_handler USB_IRQHandler /* USB IRQ */ - def_irq_handler USB_FIQHandler /* USB FIQ */ - def_irq_handler ADC_IRQHandler /* A/D Converter */ - def_irq_handler WDT_IRQHandler /* Watchdog timer */ - def_irq_handler BOD_IRQHandler /* Brown Out Detect */ - def_irq_handler FMC_IRQHandler /* IP2111 Flash Memory Controller */ - def_irq_handler Reserved5_IRQHandler /* Reserved */ - def_irq_handler Reserved6_IRQHandler /* Reserved */ - def_irq_handler USBWakeup_IRQHandler /* USB wake up */ - def_irq_handler Reserved7_IRQHandler /* Reserved */ - - .end diff --git a/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11xx.S b/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11xx.S new file mode 100644 index 000000000..5bb7f4269 --- /dev/null +++ b/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11xx.S @@ -0,0 +1,185 @@ +/* File: startup_ARMCM0.S + * Purpose: startup file for Cortex-M0 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.2 + * Date: 15 Nov 2011 + * + * Copyright (c) 2011, ARM Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the ARM Limited nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + .syntax unified + .arch armv6-m + +/* Memory Model + The HEAP starts at the end of the DATA section and grows upward. + + The STACK starts at the end of the RAM and grows downward. + + The HEAP and stack STACK are only checked at compile time: + (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE + + This is just a check for the bare minimum for the Heap+Stack area before + aborting compilation, it is not the run time limit: + Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 + */ + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ + .long DAPLINK_HIC_ID /* Compatibility*/ + .long DAPLINK_VERSION /* Version*/ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + +/* LPC11xx interrupts */ + .long WAKEUP_IRQHandler /* 16 0 Wake-up on pin PIO0_0 */ + .long WAKEUP_IRQHandler /* 17 1 Wake-up on pin PIO0_1 */ + .long WAKEUP_IRQHandler /* 18 2 Wake-up on pin PIO0_2 */ + .long WAKEUP_IRQHandler /* 19 3 Wake-up on pin PIO0_3 */ + .long WAKEUP_IRQHandler /* 20 4 Wake-up on pin PIO0_4 */ + .long WAKEUP_IRQHandler /* 21 5 Wake-up on pin PIO0_5 */ + .long WAKEUP_IRQHandler /* 22 6 Wake-up on pin PIO0_6 */ + .long WAKEUP_IRQHandler /* 23 7 Wake-up on pin PIO0_7 */ + .long WAKEUP_IRQHandler /* 24 8 Wake-up on pin PIO0_8 */ + .long WAKEUP_IRQHandler /* 25 9 Wake-up on pin PIO0_9 */ + .long WAKEUP_IRQHandler /* 26 10 Wake-up on pin PIO0_10 */ + .long WAKEUP_IRQHandler /* 27 11 Wake-up on pin PIO0_11 */ + .long WAKEUP_IRQHandler /* 28 12 Wake-up on pin PIO1_0 */ + .long Default_Handler /* 29 13 */ + .long SSP1_IRQHandler /* 30 14 SSP1 */ + .long I2C_IRQHandler /* 31 15 I2C0 SI (state change) */ + .long TIMER16_0_IRQHandler /* 32 16 CT16B0 16 bit timer 0 */ + .long TIMER16_1_IRQHandler /* 33 17 CT16B1 16 bit timer 1 */ + .long TIMER32_0_IRQHandler /* 34 18 CT32B0 32 bit timer 0 */ + .long TIMER32_1_IRQHandler /* 35 19 CT32B1 32 bit timer 1 */ + .long SSP0_IRQHandler /* 36 20 SSP */ + .long UART_IRQHandler /* 37 21 UART */ + .long Default_Handler /* 38 22 */ + .long Default_Handler /* 39 23 */ + .long ADC_IRQHandler /* 40 24 ADC end of conversion */ + .long WDT_IRQHandler /* 41 25 Watchdog interrupt (WDINT) */ + .long BOD_IRQHandler /* 42 26 BOD Brown-out detect */ + .long Default_Handler /* 43 27 */ + .long PIOINT3_IRQHandler /* 44 28 PIO_3 GPIO interrupt status of port 3 */ + .long PIOINT2_IRQHandler /* 45 29 PIO_2 GPIO interrupt status of port 2 */ + .long PIOINT1_IRQHandler /* 46 30 PIO_1 GPIO interrupt status of port 1 */ + .long PIOINT0_IRQHandler /* 47 31 PIO_0 GPIO interrupt status of port 0 */ + + .size __isr_vector, . - __isr_vector + + .section .text.Reset_Handler + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .Lflash_to_ram_loop_end + + movs r4, 0 +.Lflash_to_ram_loop: + ldr r0, [r1,r4] + str r0, [r2,r4] + adds r4, 4 + cmp r4, r3 + blt .Lflash_to_ram_loop +.Lflash_to_ram_loop_end: + + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler SVC_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_default_handler WAKEUP_IRQHandler + def_irq_default_handler SSP1_IRQHandler + def_irq_default_handler I2C_IRQHandler + def_irq_default_handler TIMER16_0_IRQHandler + def_irq_default_handler TIMER16_1_IRQHandler + def_irq_default_handler TIMER32_0_IRQHandler + def_irq_default_handler TIMER32_1_IRQHandler + def_irq_default_handler SSP0_IRQHandler + def_irq_default_handler UART_IRQHandler + def_irq_default_handler ADC_IRQHandler + def_irq_default_handler WDT_IRQHandler + def_irq_default_handler BOD_IRQHandler + def_irq_default_handler PIOINT3_IRQHandler + def_irq_default_handler PIOINT2_IRQHandler + def_irq_default_handler PIOINT1_IRQHandler + def_irq_default_handler PIOINT0_IRQHandler + + .end diff --git a/source/hic_hal/nxp/lpc11u35/system_LPC11Uxx.c b/source/hic_hal/nxp/lpc11u35/system_LPC11Uxx.c index 419336506..e0a8a2eba 100644 --- a/source/hic_hal/nxp/lpc11u35/system_LPC11Uxx.c +++ b/source/hic_hal/nxp/lpc11u35/system_LPC11Uxx.c @@ -1,17 +1,17 @@ -/****************************************************************************** +/**************************************************************************//** * @file system_LPC11Uxx.c - * @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File - * for the NXP LPC13xx Device Series - * @version V1.10 - * @date 24. November 2010 + * @brief CMSIS Device System Source File for + * NXP LPC11Uxx Device Series + * @version V1.20 + * @date 10. October 2012 * * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * Copyright (C) 2012 ARM Limited. All rights reserved. * * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. * * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED @@ -22,149 +22,163 @@ * ******************************************************************************/ - -#include "stdint.h" +#include #include "LPC11Uxx.h" /* //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ */ -/*--------------------- Clock Configuration ---------------------------------- +/*- SystemCoreClock Configuration -------------------------------------------*/ +// SystemCoreClock Configuration +#define CLOCK_SETUP 1 // -// Clock Configuration -// System Oscillator Control Register (SYSOSCCTRL) -// BYPASS: System Oscillator Bypass Enable +// System Oscillator Control (SYSOSCCTRL) +// BYPASS: System Oscillator Bypass Enable // If enabled then PLL input (sys_osc_clk) is fed // directly from XTALIN and XTALOUT pins. -// FREQRANGE: System Oscillator Frequency Range +// FREQRANGE: System Oscillator Frequency Range // Determines frequency range for Low-power oscillator. // <0=> 1 - 20 MHz // <1=> 15 - 25 MHz // +#define SYSOSCCTRL_Val 0x00000000 // Reset value: 0x000 // -// Watchdog Oscillator Control Register (WDTOSCCTRL) -// DIVSEL: Select Divider for Fclkana -// wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL)) -// <0-31> -// FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana) -// <0=> Undefined -// <1=> 0.5 MHz -// <2=> 0.8 MHz -// <3=> 1.1 MHz -// <4=> 1.4 MHz -// <5=> 1.6 MHz -// <6=> 1.8 MHz -// <7=> 2.0 MHz -// <8=> 2.2 MHz -// <9=> 2.4 MHz -// <10=> 2.6 MHz -// <11=> 2.7 MHz -// <12=> 2.9 MHz -// <13=> 3.1 MHz -// <14=> 3.2 MHz -// <15=> 3.4 MHz -// +// System PLL Clock Source Select (SYSPLLCLKSEL) +// <0=> IRC Oscillator +// <1=> Crystal Oscillator (XTAL) +#define SYSPLLCLKSEL_Val 0x00000001 // Reset value: 0x000 // -// System PLL Control Register (SYSPLLCTRL) -// F_clkout = M * F_clkin = F_CCO / (2 * P) -// F_clkin must be in the range of 10 MHz to 25 MHz -// F_CCO must be in the range of 156 MHz to 320 MHz -// MSEL: Feedback Divider Selection -// M = MSEL + 1 -// <0-31> -// PSEL: Post Divider Selection -// <0=> P = 1 -// <1=> P = 2 -// <2=> P = 4 -// <3=> P = 8 -// +// Clock Configuration (Manual) +#define CLOCK_SETUP_REG 1 // -// System PLL Clock Source Select Register (SYSPLLCLKSEL) -// SEL: System PLL Clock Source -// <0=> IRC Oscillator -// <1=> System Oscillator -// <2=> Reserved -// <3=> Reserved -// +// WD Oscillator Setting (WDTOSCCTRL) +// DIVSEL: Select Divider for Fclkana +// wd_osc_clk = Fclkana / (2 � (1 + DIVSEL)) +// <0-31> +// FREQSEL: Select WD Oscillator Analog Output Frequency (Fclkana) +// <1=> 0.5 MHz +// <2=> 0.8 MHz +// <3=> 1.1 MHz +// <4=> 1.4 MHz +// <5=> 1.6 MHz +// <6=> 1.8 MHz +// <7=> 2.0 MHz +// <8=> 2.2 MHz +// <9=> 2.4 MHz +// <10=> 2.6 MHz +// <11=> 2.7 MHz +// <12=> 2.9 MHz +// <13=> 3.1 MHz +// <14=> 3.2 MHz +// <15=> 3.4 MHz +// +#define WDTOSCCTRL_Val 0x000000A0 // Reset value: 0x0A0 // -// Main Clock Source Select Register (MAINCLKSEL) -// SEL: Clock Source for Main Clock -// <0=> IRC Oscillator -// <1=> Input Clock to System PLL -// <2=> WDT Oscillator -// <3=> System PLL Clock Out -// +// System PLL Setting (SYSPLLCTRL) +// F_clkout = M * F_clkin = F_CCO / (2 * P) +// F_clkin must be in the range of 10 MHz to 25 MHz +// F_CCO must be in the range of 156 MHz to 320 MHz +// MSEL: Feedback Divider Selection +// M = MSEL + 1 +// <0-31> +// PSEL: Post Divider Selection +// Post divider ratio P. Division ratio is 2 * P +// <0=> P = 1 +// <1=> P = 2 +// <2=> P = 4 +// <3=> P = 8 +// +#define SYSPLLCTRL_Val 0x00000023 // Reset value: 0x000 // -// System AHB Clock Divider Register (SYSAHBCLKDIV) -// DIV: System AHB Clock Divider -// Divides main clock to provide system clock to core, memories, and peripherals. -// 0 = is disabled -// <0-255> -// +// Main Clock Source Select (MAINCLKSEL) +// <0=> IRC Oscillator +// <1=> PLL Input +// <2=> WD Oscillator +// <3=> PLL Output +#define MAINCLKSEL_Val 0x00000003 // Reset value: 0x000 // -// USB PLL Control Register (USBPLLCTRL) -// F_clkout = M * F_clkin = F_CCO / (2 * P) -// F_clkin must be in the range of 10 MHz to 25 MHz -// F_CCO must be in the range of 156 MHz to 320 MHz -// MSEL: Feedback Divider Selection -// M = MSEL + 1 -// <0-31> -// PSEL: Post Divider Selection -// <0=> P = 1 -// <1=> P = 2 -// <2=> P = 4 -// <3=> P = 8 -// +// System AHB Clock Divider (SYSAHBCLKDIV.DIV) +// Divides main clock to provide system clock to core, memories, and peripherals. +// 0 = is disabled +// <0-255> +#define SYSAHBCLKDIV_Val 0x00000001 // Reset value: 0x001 +// +// +// Clock Configuration (via ROM PLL API) +#define CLOCK_SETUP_API 0 +// +// PLL API Mode Select +// <0=> Exact +// <1=> Less than or equal +// <2=> Greater than or equal +// <3=> As close as possible +#define PLL_API_MODE_Val 0 +// +// CPU Frequency [Hz] <1000000-50000000:1000> +#define PLL_API_FREQ_Val 48000000 +// // -// USB PLL Clock Source Select Register (USBPLLCLKSEL) -// SEL: USB PLL Clock Source +// USB Clock Configuration +#define USB_CLOCK_SETUP 0 +// USB PLL Control (USBPLLCTRL) +// F_clkout = M * F_clkin = F_CCO / (2 * P) +// F_clkin must be in the range of 10 MHz to 25 MHz +// F_CCO must be in the range of 156 MHz to 320 MHz +// MSEL: Feedback Divider Selection +// M = MSEL + 1 +// <0-31> +// PSEL: Post Divider Selection +// Post divider ratio P. Division ratio is 2 * P +// <0=> P = 1 +// <1=> P = 2 +// <2=> P = 4 +// <3=> P = 8 +// +#define USBPLLCTRL_Val 0x00000023 // Reset value: 0x000 +// +// USB PLL Clock Source Select (USBPLLCLKSEL.SEL) // USB PLL clock source must be switched to System Oscillator for correct USB operation // <0=> IRC Oscillator // <1=> System Oscillator -// <2=> Reserved -// <3=> Reserved -// +#define USBPLLCLKSEL_Val 0x00000001 // Reset value: 0x000 // -// USB Clock Source Select Register (USBCLKSEL) -// SEL: System PLL Clock Source +// USB Clock Source Select (USBCLKSEL.SEL) // <0=> USB PLL out // <1=> Main clock -// <2=> Reserved -// <3=> Reserved -// +#define USBCLKSEL_Val 0x00000000 // Reset value: 0x000 // -// USB Clock Divider Register (USBCLKDIV) -// DIV: USB Clock Divider +// USB Clock Divider (USBCLKDIV.DIV) // Divides USB clock to 48 MHz. // 0 = is disabled // <0-255> -// +#define USBCLKDIV_Val 0x00000001 // Reset Value: 0x001 +// +// // -*/ -#define CLOCK_SETUP 1 -#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 -#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 -#define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000 -#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 -#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 -#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 -#define USBPLLCTRL_Val 0x00000023 // Reset: 0x000 -#define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000 -#define USBCLKSEL_Val 0x00000000 // Reset: 0x000 -#define USBCLKDIV_Val 0x00000001 // Reset: 0x001 +// +// System Oscillator (XTAL) Frequency [Hz] <1000000-25000000> +// XTAL frequency must be in the range of 1 MHz to 25 MHz +// +#define XTAL_CLK_Val 12000000 /* //-------- <<< end of configuration section >>> ------------------------------ */ +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __XTAL_CLK ( XTAL_CLK_Val) /* Oscillator freq */ +#define __SYS_OSC_CLK ( __XTAL_CLK) /* System oscillator freq */ +#define __IRC_OSC_CLK ( 12000000UL) /* Internal RC oscillator freq */ + /*---------------------------------------------------------------------------- Check the register settings *----------------------------------------------------------------------------*/ #define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) #define CHECK_RSVD(val, mask) (val & mask) -/* Clock Configuration -------------------------------------------------------*/ #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003)) #error "SYSOSCCTRL: Invalid values of reserved bits!" #endif @@ -173,11 +187,11 @@ #error "WDTOSCCTRL: Invalid values of reserved bits!" #endif -#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2)) +#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 1)) #error "SYSPLLCLKSEL: Value out of range!" #endif -#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF)) +#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x0000007F)) #error "SYSPLLCTRL: Invalid values of reserved bits!" #endif @@ -189,11 +203,15 @@ #error "SYSAHBCLKDIV: Value out of range!" #endif +#if ( CLOCK_SETUP_REG == CLOCK_SETUP_API ) + #error "You must select either manual or API based Clock Configuration!" +#endif + #if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1)) #error "USBPLLCLKSEL: Value out of range!" #endif -#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF)) +#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000007F)) #error "USBPLLCTRL: Invalid values of reserved bits!" #endif @@ -205,56 +223,24 @@ #error "USBCLKDIV: Value out of range!" #endif +#if (CHECK_RANGE(XTAL_CLK_Val, 1000000, 25000000)) + #error "XTAL frequency is out of bounds" +#endif + +#if (CHECK_RANGE(PLL_API_MODE_Val, 0, 3)) + #error "PLL API Mode Select not valid" +#endif + +#if (CHECK_RANGE(PLL_API_FREQ_Val, 1000000, 50000000)) + #error "CPU Frequency (API mode) not valid" +#endif + + /*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - Define clocks + Calculate system core clock *----------------------------------------------------------------------------*/ -#define __XTAL (12000000UL) /* Oscillator frequency */ -#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */ -#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */ - - -#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F) -#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2) - -#if (CLOCK_SETUP) /* Clock Setup */ - #if (__FREQSEL == 0) - #define __WDT_OSC_CLK ( 0) /* undefined */ - #elif (__FREQSEL == 1) - #define __WDT_OSC_CLK ( 500000 / __DIVSEL) - #elif (__FREQSEL == 2) - #define __WDT_OSC_CLK ( 800000 / __DIVSEL) - #elif (__FREQSEL == 3) - #define __WDT_OSC_CLK (1100000 / __DIVSEL) - #elif (__FREQSEL == 4) - #define __WDT_OSC_CLK (1400000 / __DIVSEL) - #elif (__FREQSEL == 5) - #define __WDT_OSC_CLK (1600000 / __DIVSEL) - #elif (__FREQSEL == 6) - #define __WDT_OSC_CLK (1800000 / __DIVSEL) - #elif (__FREQSEL == 7) - #define __WDT_OSC_CLK (2000000 / __DIVSEL) - #elif (__FREQSEL == 8) - #define __WDT_OSC_CLK (2200000 / __DIVSEL) - #elif (__FREQSEL == 9) - #define __WDT_OSC_CLK (2400000 / __DIVSEL) - #elif (__FREQSEL == 10) - #define __WDT_OSC_CLK (2600000 / __DIVSEL) - #elif (__FREQSEL == 11) - #define __WDT_OSC_CLK (2700000 / __DIVSEL) - #elif (__FREQSEL == 12) - #define __WDT_OSC_CLK (2900000 / __DIVSEL) - #elif (__FREQSEL == 13) - #define __WDT_OSC_CLK (3100000 / __DIVSEL) - #elif (__FREQSEL == 14) - #define __WDT_OSC_CLK (3200000 / __DIVSEL) - #else - #define __WDT_OSC_CLK (3400000 / __DIVSEL) - #endif +#if (CLOCK_SETUP) /* Clock Setup */ /* sys_pllclkin calculation */ #if ((SYSPLLCLKSEL_Val & 0x03) == 0) @@ -262,115 +248,194 @@ #elif ((SYSPLLCLKSEL_Val & 0x03) == 1) #define __SYS_PLLCLKIN (__SYS_OSC_CLK) #else - #define __SYS_PLLCLKIN (0) + #error "Oops" #endif - #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1)) + #if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */ + + #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F) + #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2) + + #if (__FREQSEL == 0) + #error "WDTOSCCTRL.FREQSEL undefined!" + #elif (__FREQSEL == 1) + #define __OSC_CLK ( 500000 / __DIVSEL) + #elif (__FREQSEL == 2) + #define __OSC_CLK ( 800000 / __DIVSEL) + #elif (__FREQSEL == 3) + #define __OSC_CLK (1100000 / __DIVSEL) + #elif (__FREQSEL == 4) + #define __OSC_CLK (1400000 / __DIVSEL) + #elif (__FREQSEL == 5) + #define __OSC_CLK (1600000 / __DIVSEL) + #elif (__FREQSEL == 6) + #define __OSC_CLK (1800000 / __DIVSEL) + #elif (__FREQSEL == 7) + #define __OSC_CLK (2000000 / __DIVSEL) + #elif (__FREQSEL == 8) + #define __OSC_CLK (2200000 / __DIVSEL) + #elif (__FREQSEL == 9) + #define __OSC_CLK (2400000 / __DIVSEL) + #elif (__FREQSEL == 10) + #define __OSC_CLK (2600000 / __DIVSEL) + #elif (__FREQSEL == 11) + #define __OSC_CLK (2700000 / __DIVSEL) + #elif (__FREQSEL == 12) + #define __OSC_CLK (2900000 / __DIVSEL) + #elif (__FREQSEL == 13) + #define __OSC_CLK (3100000 / __DIVSEL) + #elif (__FREQSEL == 14) + #define __OSC_CLK (3200000 / __DIVSEL) + #else + #define __OSC_CLK (3400000 / __DIVSEL) + #endif - /* main clock calculation */ - #if ((MAINCLKSEL_Val & 0x03) == 0) - #define __MAIN_CLOCK (__IRC_OSC_CLK) - #elif ((MAINCLKSEL_Val & 0x03) == 1) - #define __MAIN_CLOCK (__SYS_PLLCLKIN) - #elif ((MAINCLKSEL_Val & 0x03) == 2) - #if (__FREQSEL == 0) - #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!" + #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1)) + + /* main clock calculation */ + #if ((MAINCLKSEL_Val & 0x03) == 0) + #define __MAIN_CLOCK (__IRC_OSC_CLK) + #elif ((MAINCLKSEL_Val & 0x03) == 1) + #define __MAIN_CLOCK (__SYS_PLLCLKIN) + #elif ((MAINCLKSEL_Val & 0x03) == 2) + #define __MAIN_CLOCK (__OSC_CLK) + #elif ((MAINCLKSEL_Val & 0x03) == 3) + #define __MAIN_CLOCK (__SYS_PLLCLKOUT) #else - #define __MAIN_CLOCK (__WDT_OSC_CLK) + #error "Oops" #endif - #elif ((MAINCLKSEL_Val & 0x03) == 3) - #define __MAIN_CLOCK (__SYS_PLLCLKOUT) - #else - #define __MAIN_CLOCK (0) - #endif - #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val) + #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val) + #endif /* Clock Setup via Register */ + + #if (CLOCK_SETUP_API == 1) /* Clock Setup via ROM API */ + #define __SYSTEM_CLOCK (PLL_API_FREQ_Val) + #endif /* Clock Setup via PLL API */ #else #define __SYSTEM_CLOCK (__IRC_OSC_CLK) -#endif // CLOCK_SETUP +#endif /* CLOCK_SETUP */ + + + +#if ((CLOCK_SETUP == 1) && (CLOCK_SETUP_API == 1)) /* PLL Setup via PLL API */ +#include "power_api.h" + +typedef struct _ROM { + const unsigned p_usbd; + const unsigned p_clib; + const unsigned p_cand; + const PWRD * pPWRD; /* ROM Power Management API */ + const unsigned p_dev1; + const unsigned p_dev2; + const unsigned p_dev3; + const unsigned p_dev4; +} ROM; + +/*---------------------------------------------------------------------------- + PLL API Function + *----------------------------------------------------------------------------*/ +static void setPLL(const uint32_t pllMode, const uint32_t pllInFreq, const uint32_t reqCpuFreq) +{ + uint32_t cmd[5], res[5]; + ROM ** rom = (ROM **) 0x1FFF1FF8; /* pointer to power API calls */ + + cmd[0] = pllInFreq; /* PLL's input freq in KHz */ + cmd[1] = reqCpuFreq; /* requested CPU freq in KHz */ + cmd[2] = pllMode; + cmd[3] = 0; /* no timeout for PLL to lock */ + + /* Execute API call */ + (*rom)->pPWRD->set_pll(cmd ,res); /* call API function */ + if ((res[0] != PLL_CMD_SUCCESS)){ /* in case of an error ... */ + while(1); /* ... stay here */ + } +} +#endif + + /*---------------------------------------------------------------------------- Clock Variable definitions *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /* System Clock Frequency */ /*---------------------------------------------------------------------------- Clock functions *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ { - uint32_t wdt_osc = 0; + uint32_t oscClk = 0; /* Determine clock frequency according to clock register values */ switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) { - case 0: wdt_osc = 0; break; - case 1: wdt_osc = 500000; break; - case 2: wdt_osc = 800000; break; - case 3: wdt_osc = 1100000; break; - case 4: wdt_osc = 1400000; break; - case 5: wdt_osc = 1600000; break; - case 6: wdt_osc = 1800000; break; - case 7: wdt_osc = 2000000; break; - case 8: wdt_osc = 2200000; break; - case 9: wdt_osc = 2400000; break; - case 10: wdt_osc = 2600000; break; - case 11: wdt_osc = 2700000; break; - case 12: wdt_osc = 2900000; break; - case 13: wdt_osc = 3100000; break; - case 14: wdt_osc = 3200000; break; - case 15: wdt_osc = 3400000; break; + case 0: oscClk = 0; break; + case 1: oscClk = 500000; break; + case 2: oscClk = 800000; break; + case 3: oscClk = 1100000; break; + case 4: oscClk = 1400000; break; + case 5: oscClk = 1600000; break; + case 6: oscClk = 1800000; break; + case 7: oscClk = 2000000; break; + case 8: oscClk = 2200000; break; + case 9: oscClk = 2400000; break; + case 10: oscClk = 2600000; break; + case 11: oscClk = 2700000; break; + case 12: oscClk = 2900000; break; + case 13: oscClk = 3100000; break; + case 14: oscClk = 3200000; break; + case 15: oscClk = 3400000; break; } - wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2; - + oscClk /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2; + switch (LPC_SYSCON->MAINCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ + case 0: /* Internal RC oscillator */ SystemCoreClock = __IRC_OSC_CLK; break; - case 1: /* Input Clock to System PLL */ + case 1: /* Input Clock to System PLL */ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK; - break; - case 1: /* System oscillator */ - SystemCoreClock = __SYS_OSC_CLK; - break; - case 2: /* Reserved */ - case 3: /* Reserved */ - SystemCoreClock = 0; - break; + case 0: /* Internal RC oscillator */ + SystemCoreClock = __IRC_OSC_CLK; + break; + case 1: /* System oscillator */ + SystemCoreClock = __SYS_OSC_CLK; + break; + case 2: /* Reserved */ + case 3: /* Reserved */ + SystemCoreClock = 0; + break; } break; - case 2: /* WDT Oscillator */ - SystemCoreClock = wdt_osc; + case 2: /* WDT Oscillator */ + SystemCoreClock = oscClk; break; - case 3: /* System PLL Clock Out */ + case 3: /* System PLL Clock Out */ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - if (LPC_SYSCON->SYSPLLCTRL & 0x180) { - SystemCoreClock = __IRC_OSC_CLK; - } else { - SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - } - break; - case 1: /* System oscillator */ - if (LPC_SYSCON->SYSPLLCTRL & 0x180) { - SystemCoreClock = __SYS_OSC_CLK; - } else { - SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - } - break; - case 2: /* Reserved */ - case 3: /* Reserved */ - SystemCoreClock = 0; - break; + case 0: /* Internal RC oscillator */ + if (LPC_SYSCON->SYSPLLCTRL & 0x180) { + SystemCoreClock = __IRC_OSC_CLK; + } else { + SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + } + break; + case 1: /* System oscillator */ + if (LPC_SYSCON->SYSPLLCTRL & 0x180) { + SystemCoreClock = __SYS_OSC_CLK; + } else { + SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + } + break; + case 2: /* Reserved */ + case 3: /* Reserved */ + SystemCoreClock = 0; + break; } break; } - SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; + SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; } @@ -381,74 +446,95 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ * @return none * * @brief Setup the microcontroller system. - * Initialize the System. */ void SystemInit (void) { - volatile uint32_t i; - - // Enable USBRAM and SRAM1 - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 26) | (1 << 27); +#if (CLOCK_SETUP) + uint32_t i; +#endif -#if (CLOCK_SETUP) /* Clock Setup */ +#if (CLOCK_SETUP) /* Clock Setup */ #if ((SYSPLLCLKSEL_Val & 0x03) == 1) - LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */ LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val; - for (i = 0; i < 200; i++) __NOP(); + LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up sysosc */ + for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */ #endif - LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */ - LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */ - LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */ + LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */ + LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */ + LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */ LPC_SYSCON->SYSPLLCLKUEN = 0x01; - while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */ -#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */ - LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val; - LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */ - while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */ -#endif + while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */ + +#if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */ #if (((MAINCLKSEL_Val & 0x03) == 2) ) LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val; - LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */ - for (i = 0; i < 200; i++) __NOP(); + LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */ + for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */ #endif - LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */ - LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */ - LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */ +#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */ + LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val; + LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */ + while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */ +#endif + + LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select Clock Source */ + LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */ + LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */ LPC_SYSCON->MAINCLKUEN = 0x01; - while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */ + while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */ LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val; +#endif /* Clock Setup via Register */ + +#if (CLOCK_SETUP_API == 1) /* Clock Setup via PLL API */ +// LPC_SYSCON->SYSPLLCLKSEL = 0x00; /* Use IRC */ +// LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */ +// LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */ +// LPC_SYSCON->SYSPLLCLKUEN = 0x01; +// while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */ + + LPC_SYSCON->MAINCLKSEL = SYSPLLCLKSEL_Val; /* Select same as SYSPLL */ + LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */ + LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */ + LPC_SYSCON->MAINCLKUEN = 0x01; + while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */ + + LPC_SYSCON->SYSAHBCLKDIV = 1; -#if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */ - LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */ + setPLL(PLL_API_MODE_Val, __SYS_PLLCLKIN / 1000, PLL_API_FREQ_Val / 1000); +#endif /* Clock Setup via PLL API */ -#if ((USBCLKSEL_Val & 0x003) == 0) /* USB clock is USB PLL out */ - LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */ - LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */ - LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */ - LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */ +#if (USB_CLOCK_SETUP == 1) /* USB clock is used */ + LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */ + +#if ((USBCLKSEL_Val & 0x003) == 0) /* USB clock is USB PLL out */ + LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */ + LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */ + LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */ + LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */ LPC_SYSCON->USBPLLCLKUEN = 0x01; - while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */ + while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */ + LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val; - while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */ - LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */ + while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */ + + LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */ #endif - LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */ - LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */ + LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */ + LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */ -#else /* USB clock is not used */ - LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */ - LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */ +#else /* USB clock is not used */ + LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */ + LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */ #endif -#endif +#endif /* Clock Setup */ /* System clock to the IOCON needs to be enabled or - most of the I/O related peripherals won't work. */ + most of the I/O related peripherals won't work. */ LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16); - } From ec00edbc0de10e193580bd77ab1bc9afff10fd7a Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 24 Dec 2020 00:24:40 -0600 Subject: [PATCH 067/617] Still working on startup_LPC11xx.S --- .../nxp/lpc11u35/gcc/startup_LPC11xx.S | 79 +++++++++++-------- 1 file changed, 47 insertions(+), 32 deletions(-) diff --git a/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11xx.S b/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11xx.S index 5bb7f4269..991618440 100644 --- a/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11xx.S +++ b/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11xx.S @@ -57,30 +57,30 @@ __isr_vector: .long 0 /* Reserved */ .long 0 /* Reserved */ .long 0 /* Reserved */ - .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ - .long DAPLINK_HIC_ID /* Compatibility*/ - .long DAPLINK_VERSION /* Version*/ + .long DAPLINK_BUILD_KEY /* Build type - BL/IF */ + .long DAPLINK_HIC_ID /* Compatibility */ + .long DAPLINK_VERSION /* Version */ .long SVC_Handler /* SVCall Handler */ .long 0 /* Reserved */ - .long 0 /* Reserved */ + .long g_board_info /* Ptr to Board info, family info other target details */ .long PendSV_Handler /* PendSV Handler */ .long SysTick_Handler /* SysTick Handler */ /* LPC11xx interrupts */ - .long WAKEUP_IRQHandler /* 16 0 Wake-up on pin PIO0_0 */ - .long WAKEUP_IRQHandler /* 17 1 Wake-up on pin PIO0_1 */ - .long WAKEUP_IRQHandler /* 18 2 Wake-up on pin PIO0_2 */ - .long WAKEUP_IRQHandler /* 19 3 Wake-up on pin PIO0_3 */ - .long WAKEUP_IRQHandler /* 20 4 Wake-up on pin PIO0_4 */ - .long WAKEUP_IRQHandler /* 21 5 Wake-up on pin PIO0_5 */ - .long WAKEUP_IRQHandler /* 22 6 Wake-up on pin PIO0_6 */ - .long WAKEUP_IRQHandler /* 23 7 Wake-up on pin PIO0_7 */ - .long WAKEUP_IRQHandler /* 24 8 Wake-up on pin PIO0_8 */ - .long WAKEUP_IRQHandler /* 25 9 Wake-up on pin PIO0_9 */ - .long WAKEUP_IRQHandler /* 26 10 Wake-up on pin PIO0_10 */ - .long WAKEUP_IRQHandler /* 27 11 Wake-up on pin PIO0_11 */ - .long WAKEUP_IRQHandler /* 28 12 Wake-up on pin PIO1_0 */ - .long Default_Handler /* 29 13 */ + .long FLEX_INT0_IRQHandler /* 16 0 Wake-up on pin PIO0_0 */ + .long FLEX_INT1_IRQHandler /* 17 1 Wake-up on pin PIO0_1 */ + .long FLEX_INT2_IRQHandler /* 18 2 Wake-up on pin PIO0_2 */ + .long FLEX_INT3_IRQHandler /* 19 3 Wake-up on pin PIO0_3 */ + .long FLEX_INT4_IRQHandler /* 20 4 Wake-up on pin PIO0_4 */ + .long FLEX_INT5_IRQHandler /* 21 5 Wake-up on pin PIO0_5 */ + .long FLEX_INT6_IRQHandler /* 22 6 Wake-up on pin PIO0_6 */ + .long FLEX_INT7_IRQHandler /* 23 7 Wake-up on pin PIO0_7 */ + .long GINT0_IRQHandler /* 24 8 Wake-up on pin PIO0_8 */ + .long GINT1_IRQHandler /* 25 9 Wake-up on pin PIO0_9 */ + .long Reserved_IRQHandler /* 26 10 Reserved */ + .long Reserved_IRQHandler /* 27 11 Reserved */ + .long Reserved_IRQHandler /* 28 12 Reserved */ + .long Reserved_IRQHandler /* 29 13 Reserved */ .long SSP1_IRQHandler /* 30 14 SSP1 */ .long I2C_IRQHandler /* 31 15 I2C0 SI (state change) */ .long TIMER16_0_IRQHandler /* 32 16 CT16B0 16 bit timer 0 */ @@ -89,17 +89,17 @@ __isr_vector: .long TIMER32_1_IRQHandler /* 35 19 CT32B1 32 bit timer 1 */ .long SSP0_IRQHandler /* 36 20 SSP */ .long UART_IRQHandler /* 37 21 UART */ - .long Default_Handler /* 38 22 */ - .long Default_Handler /* 39 23 */ + .long USB_IRQHandler /* 38 22 USB IRQ */ + .long USB_FIQHandler /* 39 23 USB IRQ */ .long ADC_IRQHandler /* 40 24 ADC end of conversion */ .long WDT_IRQHandler /* 41 25 Watchdog interrupt (WDINT) */ .long BOD_IRQHandler /* 42 26 BOD Brown-out detect */ - .long Default_Handler /* 43 27 */ - .long PIOINT3_IRQHandler /* 44 28 PIO_3 GPIO interrupt status of port 3 */ - .long PIOINT2_IRQHandler /* 45 29 PIO_2 GPIO interrupt status of port 2 */ - .long PIOINT1_IRQHandler /* 46 30 PIO_1 GPIO interrupt status of port 1 */ - .long PIOINT0_IRQHandler /* 47 31 PIO_0 GPIO interrupt status of port 0 */ - + .long FMC_IRQHandler /* 43 27 IP2111 Flash Memory Controller */ + .long Reserved_IRQHandler /* 44 28 Reserved */ + .long Reserved_IRQHandler /* 45 29 Reserved */ + .long USBWakeup_IRQHandler /* 46 30 USB wake up */ + .long Reserved_IRQHandler /* 47 31 Reserved */ + .size __isr_vector, . - __isr_vector .section .text.Reset_Handler @@ -132,6 +132,11 @@ Reset_Handler: blt .Lflash_to_ram_loop .Lflash_to_ram_loop_end: + /* Power on RAM1 and USBRAM area */ + ldr r0, =0x40048080 /* System clock control */ + ldr r1, =0x0C00485F /* boot default + RAM1, USBRAM */ + str r1, [r0] + ldr r0, =SystemInit blx r0 ldr r0, =_start @@ -159,13 +164,23 @@ Reset_Handler: def_default_handler PendSV_Handler def_default_handler SysTick_Handler def_default_handler Default_Handler + def_default_handler Reserved_IRQHandler .macro def_irq_default_handler handler_name .weak \handler_name .set \handler_name, Default_Handler .endm - - def_irq_default_handler WAKEUP_IRQHandler + + def_irq_default_handler FLEX_INT0_IRQHandler + def_irq_default_handler FLEX_INT1_IRQHandler + def_irq_default_handler FLEX_INT2_IRQHandler + def_irq_default_handler FLEX_INT3_IRQHandler + def_irq_default_handler FLEX_INT4_IRQHandler + def_irq_default_handler FLEX_INT5_IRQHandler + def_irq_default_handler FLEX_INT6_IRQHandler + def_irq_default_handler FLEX_INT7_IRQHandler + def_irq_default_handler GINT0_IRQHandler + def_irq_default_handler GINT1_IRQHandler def_irq_default_handler SSP1_IRQHandler def_irq_default_handler I2C_IRQHandler def_irq_default_handler TIMER16_0_IRQHandler @@ -174,12 +189,12 @@ Reset_Handler: def_irq_default_handler TIMER32_1_IRQHandler def_irq_default_handler SSP0_IRQHandler def_irq_default_handler UART_IRQHandler + def_irq_default_handler USB_IRQHandler + def_irq_default_handler USB_FIQHandler def_irq_default_handler ADC_IRQHandler def_irq_default_handler WDT_IRQHandler def_irq_default_handler BOD_IRQHandler - def_irq_default_handler PIOINT3_IRQHandler - def_irq_default_handler PIOINT2_IRQHandler - def_irq_default_handler PIOINT1_IRQHandler - def_irq_default_handler PIOINT0_IRQHandler + def_irq_default_handler FMC_IRQHandler + def_irq_default_handler USBWakeup_IRQHandler .end From d9eba1efd7315fc98c470c0b64588f3bb1321339 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 24 Dec 2020 11:28:58 -0600 Subject: [PATCH 068/617] Still working on startup_LPC11Uxx.S --- .../nxp/lpc11u35/gcc/startup_LPC11Uxx.S | 205 ++++++++++++++++++ .../nxp/lpc11u35/gcc/startup_LPC11xx.S | 200 ----------------- 2 files changed, 205 insertions(+), 200 deletions(-) create mode 100644 source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11Uxx.S delete mode 100644 source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11xx.S diff --git a/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11Uxx.S b/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11Uxx.S new file mode 100644 index 000000000..ba844a58e --- /dev/null +++ b/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11Uxx.S @@ -0,0 +1,205 @@ +/** + * @file startup_LPC11Uxx.s + * @brief CMSIS Cortex-M0 Core Device Startup File for + * NXP LPC11Uxx Device Series + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2020, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + .syntax unified + .arch armv6-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long DAPLINK_BUILD_KEY /* Build type - BL/IF */ + .long DAPLINK_HIC_ID /* Compatibility */ + .long DAPLINK_VERSION /* Version */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long g_board_info /* Ptr to Board info, family info other target details */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + +/* LPC11xx interrupts */ + .long FLEX_INT0_IRQHandler /* 16+ 0 All GPIO pin can be routed to FLEX_INTx */ + .long FLEX_INT1_IRQHandler /* 16+ 1 Pin interrupt */ + .long FLEX_INT2_IRQHandler /* 16+ 2 Pin interrupt */ + .long FLEX_INT3_IRQHandler /* 16+ 3 Pin interrupt */ + .long FLEX_INT4_IRQHandler /* 16+ 4 Pin interrupt */ + .long FLEX_INT5_IRQHandler /* 16+ 5 Pin interrupt */ + .long FLEX_INT6_IRQHandler /* 16+ 6 Pin interrupt */ + .long FLEX_INT7_IRQHandler /* 16+ 7 Pin interrupt */ + .long GINT0_IRQHandler /* 16+ 8 Port interrupt */ + .long GINT1_IRQHandler /* 16+ 9 Port interrupt */ + .long Reserved_IRQHandler /* 16+10 Reserved */ + .long Reserved_IRQHandler /* 16+11 Reserved */ + .long Reserved_IRQHandler /* 16+12 Reserved */ + .long Reserved_IRQHandler /* 16+13 Reserved */ + .long SSP1_IRQHandler /* 16+14 SSP1 */ + .long I2C_IRQHandler /* 16+15 I2C */ + .long TIMER16_0_IRQHandler /* 16+16 16-bit Timer0 */ + .long TIMER16_1_IRQHandler /* 16+17 16-bit Timer1 */ + .long TIMER32_0_IRQHandler /* 16+18 32-bit Timer0 */ + .long TIMER32_1_IRQHandler /* 16+19 32-bit Timer1 */ + .long SSP0_IRQHandler /* 16+20 SSP0 */ + .long UART_IRQHandler /* 16+21 UART */ + .long USB_IRQHandler /* 16+22 USB IRQ */ + .long USB_FIQHandler /* 16+23 USB IRQ */ + .long ADC_IRQHandler /* 16+24 A/D Converter */ + .long WDT_IRQHandler /* 16+25 Watchdog Timer */ + .long BOD_IRQHandler /* 16+26 Brown Out Detect */ + .long FMC_IRQHandler /* 16+27 IP2111 Flash Memory Controller */ + .long Reserved_IRQHandler /* 16+28 Reserved */ + .long Reserved_IRQHandler /* 16+29 Reserved */ + .long USBWakeup_IRQHandler /* 16+30 USB wake up */ + .long IOH_IRQHandler /* 16+31 I/O Handler */ + +/* Set the CRP (Code Read Protection) configuration word + * at address 0x2FC to ensure that CRP is disabled. + * - 0xFFFFFFFF => CRP Disabled + * - 0x12345678 => CRP Level 1 + * - 0x87654321 => CRP Level 2 + * - 0x43218765 => CRP Level 3 (ARE YOU SURE?) + * - 0x4E697370 => NO ISP (ARE YOU SURE?) + */ +#define CRP_KEY_ADDR (0x000002FC) +#define CRP_DISABLED (0xFFFFFFFF) +1: /* Fill up to CRP config word address. */ + .dcb.l ((CRP_KEY_ADDR - (1b - __isr_vector)) / 4) +CRP_Key: + .long CRP_DISABLED + + .size __isr_vector, . - __isr_vector + + .text + .thumb + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__isr_vector + str r1, [r0] + ldr r2, [r1] + msr msp, r2 + + /* Power on RAM1 and USBRAM area */ + ldr r0, =0x40048080 /* System clock control */ + ldr r1, =0x0C00485F /* boot default + RAM1, USBRAM */ + str r1, [r0] + + ldr r0, =SystemInit + blx r0 + +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .LC1 + + movs r4, 0 +.LC0: + ldr r0, [r1,r4] + str r0, [r2,r4] + adds r4, 4 + cmp r4, r3 + blt .LC0 +.LC1: + + cpsie i /* Unmask interrupts */ + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler SVC_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + def_default_handler Reserved_IRQHandler + + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler FLEX_INT0_IRQHandler + def_irq_handler FLEX_INT1_IRQHandler + def_irq_handler FLEX_INT2_IRQHandler + def_irq_handler FLEX_INT3_IRQHandler + def_irq_handler FLEX_INT4_IRQHandler + def_irq_handler FLEX_INT5_IRQHandler + def_irq_handler FLEX_INT6_IRQHandler + def_irq_handler FLEX_INT7_IRQHandler + def_irq_handler GINT0_IRQHandler + def_irq_handler GINT1_IRQHandler + def_irq_handler SSP1_IRQHandler + def_irq_handler I2C_IRQHandler + def_irq_handler TIMER16_0_IRQHandler + def_irq_handler TIMER16_1_IRQHandler + def_irq_handler TIMER32_0_IRQHandler + def_irq_handler TIMER32_1_IRQHandler + def_irq_handler SSP0_IRQHandler + def_irq_handler UART_IRQHandler + def_irq_handler USB_IRQHandler + def_irq_handler USB_FIQHandler + def_irq_handler ADC_IRQHandler + def_irq_handler WDT_IRQHandler + def_irq_handler BOD_IRQHandler + def_irq_handler FMC_IRQHandler + def_irq_handler USBWakeup_IRQHandler + def_irq_handler IOH_IRQHandler + + .end diff --git a/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11xx.S b/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11xx.S deleted file mode 100644 index 991618440..000000000 --- a/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11xx.S +++ /dev/null @@ -1,200 +0,0 @@ -/* File: startup_ARMCM0.S - * Purpose: startup file for Cortex-M0 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V1.2 - * Date: 15 Nov 2011 - * - * Copyright (c) 2011, ARM Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of the ARM Limited nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - .syntax unified - .arch armv6-m - -/* Memory Model - The HEAP starts at the end of the DATA section and grows upward. - - The STACK starts at the end of the RAM and grows downward. - - The HEAP and stack STACK are only checked at compile time: - (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE - - This is just a check for the bare minimum for the Heap+Stack area before - aborting compilation, it is not the run time limit: - Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 - */ - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long DAPLINK_BUILD_KEY /* Build type - BL/IF */ - .long DAPLINK_HIC_ID /* Compatibility */ - .long DAPLINK_VERSION /* Version */ - .long SVC_Handler /* SVCall Handler */ - .long 0 /* Reserved */ - .long g_board_info /* Ptr to Board info, family info other target details */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - -/* LPC11xx interrupts */ - .long FLEX_INT0_IRQHandler /* 16 0 Wake-up on pin PIO0_0 */ - .long FLEX_INT1_IRQHandler /* 17 1 Wake-up on pin PIO0_1 */ - .long FLEX_INT2_IRQHandler /* 18 2 Wake-up on pin PIO0_2 */ - .long FLEX_INT3_IRQHandler /* 19 3 Wake-up on pin PIO0_3 */ - .long FLEX_INT4_IRQHandler /* 20 4 Wake-up on pin PIO0_4 */ - .long FLEX_INT5_IRQHandler /* 21 5 Wake-up on pin PIO0_5 */ - .long FLEX_INT6_IRQHandler /* 22 6 Wake-up on pin PIO0_6 */ - .long FLEX_INT7_IRQHandler /* 23 7 Wake-up on pin PIO0_7 */ - .long GINT0_IRQHandler /* 24 8 Wake-up on pin PIO0_8 */ - .long GINT1_IRQHandler /* 25 9 Wake-up on pin PIO0_9 */ - .long Reserved_IRQHandler /* 26 10 Reserved */ - .long Reserved_IRQHandler /* 27 11 Reserved */ - .long Reserved_IRQHandler /* 28 12 Reserved */ - .long Reserved_IRQHandler /* 29 13 Reserved */ - .long SSP1_IRQHandler /* 30 14 SSP1 */ - .long I2C_IRQHandler /* 31 15 I2C0 SI (state change) */ - .long TIMER16_0_IRQHandler /* 32 16 CT16B0 16 bit timer 0 */ - .long TIMER16_1_IRQHandler /* 33 17 CT16B1 16 bit timer 1 */ - .long TIMER32_0_IRQHandler /* 34 18 CT32B0 32 bit timer 0 */ - .long TIMER32_1_IRQHandler /* 35 19 CT32B1 32 bit timer 1 */ - .long SSP0_IRQHandler /* 36 20 SSP */ - .long UART_IRQHandler /* 37 21 UART */ - .long USB_IRQHandler /* 38 22 USB IRQ */ - .long USB_FIQHandler /* 39 23 USB IRQ */ - .long ADC_IRQHandler /* 40 24 ADC end of conversion */ - .long WDT_IRQHandler /* 41 25 Watchdog interrupt (WDINT) */ - .long BOD_IRQHandler /* 42 26 BOD Brown-out detect */ - .long FMC_IRQHandler /* 43 27 IP2111 Flash Memory Controller */ - .long Reserved_IRQHandler /* 44 28 Reserved */ - .long Reserved_IRQHandler /* 45 29 Reserved */ - .long USBWakeup_IRQHandler /* 46 30 USB wake up */ - .long Reserved_IRQHandler /* 47 31 Reserved */ - - .size __isr_vector, . - __isr_vector - - .section .text.Reset_Handler - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .Lflash_to_ram_loop_end - - movs r4, 0 -.Lflash_to_ram_loop: - ldr r0, [r1,r4] - str r0, [r2,r4] - adds r4, 4 - cmp r4, r3 - blt .Lflash_to_ram_loop -.Lflash_to_ram_loop_end: - - /* Power on RAM1 and USBRAM area */ - ldr r0, =0x40048080 /* System clock control */ - ldr r1, =0x0C00485F /* boot default + RAM1, USBRAM */ - str r1, [r0] - - ldr r0, =SystemInit - blx r0 - ldr r0, =_start - bx r0 - .pool - .size Reset_Handler, . - Reset_Handler - - .text -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler SVC_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - def_default_handler Default_Handler - def_default_handler Reserved_IRQHandler - - .macro def_irq_default_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_default_handler FLEX_INT0_IRQHandler - def_irq_default_handler FLEX_INT1_IRQHandler - def_irq_default_handler FLEX_INT2_IRQHandler - def_irq_default_handler FLEX_INT3_IRQHandler - def_irq_default_handler FLEX_INT4_IRQHandler - def_irq_default_handler FLEX_INT5_IRQHandler - def_irq_default_handler FLEX_INT6_IRQHandler - def_irq_default_handler FLEX_INT7_IRQHandler - def_irq_default_handler GINT0_IRQHandler - def_irq_default_handler GINT1_IRQHandler - def_irq_default_handler SSP1_IRQHandler - def_irq_default_handler I2C_IRQHandler - def_irq_default_handler TIMER16_0_IRQHandler - def_irq_default_handler TIMER16_1_IRQHandler - def_irq_default_handler TIMER32_0_IRQHandler - def_irq_default_handler TIMER32_1_IRQHandler - def_irq_default_handler SSP0_IRQHandler - def_irq_default_handler UART_IRQHandler - def_irq_default_handler USB_IRQHandler - def_irq_default_handler USB_FIQHandler - def_irq_default_handler ADC_IRQHandler - def_irq_default_handler WDT_IRQHandler - def_irq_default_handler BOD_IRQHandler - def_irq_default_handler FMC_IRQHandler - def_irq_default_handler USBWakeup_IRQHandler - - .end From cd50465723430068c7768be99f82bab76bdeb842 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 24 Dec 2020 12:23:28 -0600 Subject: [PATCH 069/617] Enable USB clock in system_LPC11Uxx.c --- source/hic_hal/nxp/lpc11u35/system_LPC11Uxx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/source/hic_hal/nxp/lpc11u35/system_LPC11Uxx.c b/source/hic_hal/nxp/lpc11u35/system_LPC11Uxx.c index e0a8a2eba..e1b042be7 100644 --- a/source/hic_hal/nxp/lpc11u35/system_LPC11Uxx.c +++ b/source/hic_hal/nxp/lpc11u35/system_LPC11Uxx.c @@ -54,7 +54,7 @@ // // WD Oscillator Setting (WDTOSCCTRL) // DIVSEL: Select Divider for Fclkana -// wd_osc_clk = Fclkana / (2 � (1 + DIVSEL)) +// wd_osc_clk = Fclkana / (2 * (1 + DIVSEL)) // <0-31> // FREQSEL: Select WD Oscillator Analog Output Frequency (Fclkana) // <1=> 0.5 MHz @@ -120,7 +120,7 @@ // // // USB Clock Configuration -#define USB_CLOCK_SETUP 0 +#define USB_CLOCK_SETUP 1 // USB PLL Control (USBPLLCTRL) // F_clkout = M * F_clkin = F_CCO / (2 * P) // F_clkin must be in the range of 10 MHz to 25 MHz From 1aee1de5a17b1490ffd3988998b484a26320c6ce Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 21 Dec 2020 15:31:15 -0600 Subject: [PATCH 070/617] Add gcc support to kl27z HIC --- records/hic_hal/kl27z.yaml | 13 +- .../freescale/kl27z/gcc/startup_MKL27Z4.S | 373 ++++++++++++++++++ 2 files changed, 384 insertions(+), 2 deletions(-) create mode 100644 source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S diff --git a/records/hic_hal/kl27z.yaml b/records/hic_hal/kl27z.yaml index 42bd46d8e..faa34e979 100644 --- a/records/hic_hal/kl27z.yaml +++ b/records/hic_hal/kl27z.yaml @@ -21,7 +21,6 @@ common: - source/hic_hal/freescale - source/hic_hal/freescale/kl27z - source/hic_hal/freescale/kl27z/MKL27Z4 - - source/hic_hal/freescale/kl27z/armcc fsl_flash_driver: - source/hic_hal/freescale/iap @@ -30,7 +29,17 @@ tool_specific: misc: ld_flags: - --predefine="-I..\..\..\source\hic_hal\freescale\kl27z" - make_armcc: + sources: + - source/hic_hal/freescale/kl27z/armcc + armcc: misc: ld_flags: - --predefine="-Isource\hic_hal\freescale\kl27z" + sources: + - source/hic_hal/freescale/kl27z/armcc + armclang: + sources: + - source/hic_hal/freescale/kl27z/armcc + gcc_arm: + sources: + - source/hic_hal/freescale/kl27z/gcc diff --git a/source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S b/source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S new file mode 100644 index 000000000..10059050d --- /dev/null +++ b/source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S @@ -0,0 +1,373 @@ +/* ------------------------------------------------------------------------- */ +/* @file: startup_MKL27Z4.s */ +/* @purpose: CMSIS Cortex-M0P Core Device Startup File */ +/* MKL27Z4 */ +/* @version: 1.8 */ +/* @date: 2016-6-24 */ +/* @build: b190918 */ +/* ------------------------------------------------------------------------- */ +/* */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2019 NXP */ +/* All rights reserved. */ +/* */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv6-m + .eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */ + + .section .isr_vector, "a" + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ + .long DAPLINK_HIC_ID /* Compatibility*/ + .long DAPLINK_VERSION /* Version*/ + .long SVC_Handler /* SVCall Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long DMA0_IRQHandler /* DMA channel 0 transfer complete*/ + .long DMA1_IRQHandler /* DMA channel 1 transfer complete*/ + .long DMA2_IRQHandler /* DMA channel 2 transfer complete*/ + .long DMA3_IRQHandler /* DMA channel 3 transfer complete*/ + .long Reserved20_IRQHandler /* Reserved interrupt*/ + .long FTFA_IRQHandler /* Command complete and read collision*/ + .long PMC_IRQHandler /* Low-voltage detect, low-voltage warning*/ + .long LLWU_IRQHandler /* Low leakage wakeup*/ + .long I2C0_IRQHandler /* I2C0 interrupt*/ + .long I2C1_IRQHandler /* I2C1 interrupt*/ + .long SPI0_IRQHandler /* SPI0 single interrupt vector for all sources*/ + .long SPI1_IRQHandler /* SPI1 single interrupt vector for all sources*/ + .long LPUART0_IRQHandler /* LPUART0 status and error*/ + .long LPUART1_IRQHandler /* LPUART1 status and error*/ + .long UART2_FLEXIO_IRQHandler /* UART2 or FLEXIO*/ + .long ADC0_IRQHandler /* ADC0 interrupt*/ + .long CMP0_IRQHandler /* CMP0 interrupt*/ + .long TPM0_IRQHandler /* TPM0 single interrupt vector for all sources*/ + .long TPM1_IRQHandler /* TPM1 single interrupt vector for all sources*/ + .long TPM2_IRQHandler /* TPM2 single interrupt vector for all sources*/ + .long RTC_IRQHandler /* RTC alarm*/ + .long RTC_Seconds_IRQHandler /* RTC seconds*/ + .long PIT_IRQHandler /* PIT interrupt*/ + .long I2S0_IRQHandler /* I2S0 interrupt*/ + .long USB0_IRQHandler /* USB0 interrupt*/ + .long DAC0_IRQHandler /* DAC0 interrupt*/ + .long Reserved42_IRQHandler /* Reserved interrupt*/ + .long Reserved43_IRQHandler /* Reserved interrupt*/ + .long LPTMR0_IRQHandler /* LPTMR0 interrupt*/ + .long Reserved45_IRQHandler /* Reserved interrupt*/ + .long PORTA_IRQHandler /* PORTA Pin detect*/ + .long PORTC_PORTD_IRQHandler /* Single interrupt vector for PORTC; PORTD Pin detect*/ + + .size __Vectors, . - __Vectors + +/* Flash Configuration */ + .section .FlashConfig, "a" + .long 0xFFFFFFFF + .long 0xFFFFFFFF + .long 0xFFFFFFFF + .long 0xFFFF3FFE + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__Vectors + str r1, [r0] + ldr r2, [r1] + msr msp, r2 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .LC0 + +.LC1: + subs r3, 4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .LC1 +.LC0: + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + subs r2, r1 + ble .LC3 + + movs r0, 0 +.LC2: + str r0, [r1, r2] + subs r2, 4 + bge .LC2 +.LC3: +#endif + cpsie i /* Unmask interrupts */ +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + ldr r0, =DefaultISR + bx r0 + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak DMA0_IRQHandler + .type DMA0_IRQHandler, %function +DMA0_IRQHandler: + ldr r0,=DMA0_DriverIRQHandler + bx r0 + .size DMA0_IRQHandler, . - DMA0_IRQHandler + + .align 1 + .thumb_func + .weak DMA1_IRQHandler + .type DMA1_IRQHandler, %function +DMA1_IRQHandler: + ldr r0,=DMA1_DriverIRQHandler + bx r0 + .size DMA1_IRQHandler, . - DMA1_IRQHandler + + .align 1 + .thumb_func + .weak DMA2_IRQHandler + .type DMA2_IRQHandler, %function +DMA2_IRQHandler: + ldr r0,=DMA2_DriverIRQHandler + bx r0 + .size DMA2_IRQHandler, . - DMA2_IRQHandler + + .align 1 + .thumb_func + .weak DMA3_IRQHandler + .type DMA3_IRQHandler, %function +DMA3_IRQHandler: + ldr r0,=DMA3_DriverIRQHandler + bx r0 + .size DMA3_IRQHandler, . - DMA3_IRQHandler + + .align 1 + .thumb_func + .weak I2C0_IRQHandler + .type I2C0_IRQHandler, %function +I2C0_IRQHandler: + ldr r0,=I2C0_DriverIRQHandler + bx r0 + .size I2C0_IRQHandler, . - I2C0_IRQHandler + + .align 1 + .thumb_func + .weak I2C1_IRQHandler + .type I2C1_IRQHandler, %function +I2C1_IRQHandler: + ldr r0,=I2C1_DriverIRQHandler + bx r0 + .size I2C1_IRQHandler, . - I2C1_IRQHandler + + .align 1 + .thumb_func + .weak SPI0_IRQHandler + .type SPI0_IRQHandler, %function +SPI0_IRQHandler: + ldr r0,=SPI0_DriverIRQHandler + bx r0 + .size SPI0_IRQHandler, . - SPI0_IRQHandler + + .align 1 + .thumb_func + .weak SPI1_IRQHandler + .type SPI1_IRQHandler, %function +SPI1_IRQHandler: + ldr r0,=SPI1_DriverIRQHandler + bx r0 + .size SPI1_IRQHandler, . - SPI1_IRQHandler + + .align 1 + .thumb_func + .weak LPUART0_IRQHandler + .type LPUART0_IRQHandler, %function +LPUART0_IRQHandler: + ldr r0,=LPUART0_DriverIRQHandler + bx r0 + .size LPUART0_IRQHandler, . - LPUART0_IRQHandler + + .align 1 + .thumb_func + .weak LPUART1_IRQHandler + .type LPUART1_IRQHandler, %function +LPUART1_IRQHandler: + ldr r0,=LPUART1_DriverIRQHandler + bx r0 + .size LPUART1_IRQHandler, . - LPUART1_IRQHandler + + .align 1 + .thumb_func + .weak UART2_FLEXIO_IRQHandler + .type UART2_FLEXIO_IRQHandler, %function +UART2_FLEXIO_IRQHandler: + ldr r0,=UART2_FLEXIO_DriverIRQHandler + bx r0 + .size UART2_FLEXIO_IRQHandler, . - UART2_FLEXIO_IRQHandler + + .align 1 + .thumb_func + .weak I2S0_IRQHandler + .type I2S0_IRQHandler, %function +I2S0_IRQHandler: + ldr r0,=I2S0_DriverIRQHandler + bx r0 + .size I2S0_IRQHandler, . - I2S0_IRQHandler + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler DMA0_DriverIRQHandler + def_irq_handler DMA1_DriverIRQHandler + def_irq_handler DMA2_DriverIRQHandler + def_irq_handler DMA3_DriverIRQHandler + def_irq_handler Reserved20_IRQHandler + def_irq_handler FTFA_IRQHandler + def_irq_handler PMC_IRQHandler + def_irq_handler LLWU_IRQHandler + def_irq_handler I2C0_DriverIRQHandler + def_irq_handler I2C1_DriverIRQHandler + def_irq_handler SPI0_DriverIRQHandler + def_irq_handler SPI1_DriverIRQHandler + def_irq_handler LPUART0_DriverIRQHandler + def_irq_handler LPUART1_DriverIRQHandler + def_irq_handler UART2_FLEXIO_DriverIRQHandler + def_irq_handler ADC0_IRQHandler + def_irq_handler CMP0_IRQHandler + def_irq_handler TPM0_IRQHandler + def_irq_handler TPM1_IRQHandler + def_irq_handler TPM2_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler RTC_Seconds_IRQHandler + def_irq_handler PIT_IRQHandler + def_irq_handler I2S0_DriverIRQHandler + def_irq_handler USB0_IRQHandler + def_irq_handler DAC0_IRQHandler + def_irq_handler Reserved42_IRQHandler + def_irq_handler Reserved43_IRQHandler + def_irq_handler LPTMR0_IRQHandler + def_irq_handler Reserved45_IRQHandler + def_irq_handler PORTA_IRQHandler + def_irq_handler PORTC_PORTD_IRQHandler + + .end From 73e634b28aac9570ee77174acaa797c5c98de24b Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 21 Dec 2020 15:46:29 -0600 Subject: [PATCH 071/617] Add armclang compilation fix for kl27z --- source/hic_hal/freescale/kl27z/MKL27Z4/MKL27Z4.h | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/source/hic_hal/freescale/kl27z/MKL27Z4/MKL27Z4.h b/source/hic_hal/freescale/kl27z/MKL27Z4/MKL27Z4.h index 3179755e5..77be36146 100644 --- a/source/hic_hal/freescale/kl27z/MKL27Z4/MKL27Z4.h +++ b/source/hic_hal/freescale/kl27z/MKL27Z4/MKL27Z4.h @@ -318,8 +318,12 @@ typedef enum _dma_request_source */ #if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif #elif defined(__CWCC__) #pragma push #pragma cpp_extensions on @@ -6249,7 +6253,11 @@ typedef struct { */ #if defined(__ARMCC_VERSION) - #pragma pop + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif #elif defined(__CWCC__) #pragma pop #elif defined(__GNUC__) From 2dc0df448bba1d52455c10995568cf093fcc38af Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 1 Jan 2021 23:25:39 -0600 Subject: [PATCH 072/617] Fix end-of-line style --- records/board/nina_b1.yaml | 22 +++++++++++----------- records/board/vbluno51.yaml | 22 +++++++++++----------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/records/board/nina_b1.yaml b/records/board/nina_b1.yaml index 5b9869589..224ed6283 100644 --- a/records/board/nina_b1.yaml +++ b/records/board/nina_b1.yaml @@ -1,11 +1,11 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_mkl26z_reset - sources: - board: - - source/board/nina_b1.c - family: - - source/family/nordic/nrf5x/target.c - - source/family/nordic/target_reset_nrf51.c +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mkl26z_reset + sources: + board: + - source/board/nina_b1.c + family: + - source/family/nordic/nrf5x/target.c + - source/family/nordic/target_reset_nrf51.c diff --git a/records/board/vbluno51.yaml b/records/board/vbluno51.yaml index 3276f988b..5a0d862b0 100644 --- a/records/board/vbluno51.yaml +++ b/records/board/vbluno51.yaml @@ -1,11 +1,11 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_vbluno51 - sources: - board: - - source/board/vbluno51.c - family: - - source/family/nordic/nrf51822/target_32.c - - source/family/nordic/target_reset_nrf51.c +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_vbluno51 + sources: + board: + - source/board/vbluno51.c + family: + - source/family/nordic/nrf51822/target_32.c + - source/family/nordic/target_reset_nrf51.c From f2552b434ec0f2cb566e62ada93a8fe54c60d2fe Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 1 Jan 2021 23:26:03 -0600 Subject: [PATCH 073/617] Fix typo --- tools/progen_compile.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/progen_compile.py b/tools/progen_compile.py index 513e94f9a..ccd249418 100755 --- a/tools/progen_compile.py +++ b/tools/progen_compile.py @@ -141,7 +141,7 @@ def build_projects(file, projects, tool, build=True, clean=False, parallel=False if not os.path.exists(hex): # Build failed if args.ignore_failures: - logger.warnig("Missing file %s (build failed)" % (hex)) + logger.warning("Missing file %s (build failed)" % (hex)) continue else: logger.error("Missing file %s (build failed)" % (hex)) From e2c23f786f819aa6a73be1dd4bba179e3eaae1c2 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sat, 2 Jan 2021 13:10:30 -0600 Subject: [PATCH 074/617] Completely disable EVR in RTX_Config.h. --- source/rtos2/Include/RTX_Config.h | 223 +++++++++++++++--------------- 1 file changed, 113 insertions(+), 110 deletions(-) diff --git a/source/rtos2/Include/RTX_Config.h b/source/rtos2/Include/RTX_Config.h index 4f3e14211..497e8f74a 100644 --- a/source/rtos2/Include/RTX_Config.h +++ b/source/rtos2/Include/RTX_Config.h @@ -24,52 +24,52 @@ * * ----------------------------------------------------------------------------- */ - + #ifndef RTX_CONFIG_H_ #define RTX_CONFIG_H_ - + #ifdef _RTE_ #include "RTE_Components.h" #ifdef RTE_RTX_CONFIG_H #include RTE_RTX_CONFIG_H #endif #endif - + //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - + // System Configuration // ======================= - + // Global Dynamic Memory size [bytes] <0-1073741824:8> // Defines the combined global dynamic memory size. // Default: 32768 #ifndef OS_DYNAMIC_MEM_SIZE #define OS_DYNAMIC_MEM_SIZE 0 // DAPLINK. Default was: 32768 #endif - + // Kernel Tick Frequency [Hz] <1-1000000> // Defines base time unit for delays and timeouts. // Default: 1000 (1ms tick) #ifndef OS_TICK_FREQ #define OS_TICK_FREQ 10000 // DAPLINK. Default was: 1000 #endif - + // Round-Robin Thread switching // Enables Round-Robin Thread switching. #ifndef OS_ROBIN_ENABLE #define OS_ROBIN_ENABLE 0 // DAPLINK. Default was: 1 #endif - + // Round-Robin Timeout <1-1000> // Defines how many ticks a thread will execute before a thread switch. // Default: 5 #ifndef OS_ROBIN_TIMEOUT #define OS_ROBIN_TIMEOUT 5 #endif - + // - -// ISR FIFO Queue + +// ISR FIFO Queue // <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries // <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries // <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries @@ -78,38 +78,38 @@ #ifndef OS_ISR_FIFO_QUEUE #define OS_ISR_FIFO_QUEUE 4 // DAPLINK. Default was: 16 #endif - + // Object Memory usage counters // Enables object memory usage counters (requires RTX source variant). #ifndef OS_OBJ_MEM_USAGE #define OS_OBJ_MEM_USAGE 0 #endif - + // - + // Thread Configuration // ======================= - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_THREAD_OBJ_MEM #define OS_THREAD_OBJ_MEM 0 #endif - + // Number of user Threads <1-1000> // Defines maximum number of user threads that can be active at the same time. // Applies to user threads with system provided memory for control blocks. #ifndef OS_THREAD_NUM #define OS_THREAD_NUM 0 // DAPLINK. Default was: 1 #endif - + // Number of user Threads with default Stack size <0-1000> // Defines maximum number of user threads with default stack size. // Applies to user threads with zero stack size specified. #ifndef OS_THREAD_DEF_STACK_NUM #define OS_THREAD_DEF_STACK_NUM 0 #endif - + // Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> // Defines the combined stack size for user threads with user-provided stack size. // Applies to user threads with user-provided stack size and system provided memory for stack. @@ -117,23 +117,23 @@ #ifndef OS_THREAD_USER_STACK_SIZE #define OS_THREAD_USER_STACK_SIZE 0 #endif - + // - + // Default Thread Stack size [bytes] <96-1073741824:8> // Defines stack size for threads with zero stack size specified. // Default: 3072 #ifndef OS_STACK_SIZE #define OS_STACK_SIZE 72 // DAPLINK. Default was: 3072 #endif - + // Idle Thread Stack size [bytes] <72-1073741824:8> // Defines stack size for Idle thread. // Default: 512 #ifndef OS_IDLE_THREAD_STACK_SIZE #define OS_IDLE_THREAD_STACK_SIZE 72 // DAPLINK. Default was: 512 #endif - + // Idle Thread TrustZone Module Identifier // Defines TrustZone Thread Context Management Identifier. // Applies only to cores with TrustZone technology. @@ -141,49 +141,49 @@ #ifndef OS_IDLE_THREAD_TZ_MOD_ID #define OS_IDLE_THREAD_TZ_MOD_ID 0 #endif - + // Stack overrun checking // Enables stack overrun check at thread switch. // Enabling this option increases slightly the execution time of a thread switch. #ifndef OS_STACK_CHECK #define OS_STACK_CHECK 1 #endif - + // Stack usage watermark // Initializes thread stack with watermark pattern for analyzing stack usage. // Enabling this option increases significantly the execution time of thread creation. #ifndef OS_STACK_WATERMARK #define OS_STACK_WATERMARK 0 #endif - -// Processor mode for Thread execution -// <0=> Unprivileged mode + +// Processor mode for Thread execution +// <0=> Unprivileged mode // <1=> Privileged mode // Default: Privileged mode #ifndef OS_PRIVILEGE_MODE #define OS_PRIVILEGE_MODE 1 #endif - + // - + // Timer Configuration // ====================== - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_TIMER_OBJ_MEM #define OS_TIMER_OBJ_MEM 0 #endif - + // Number of Timer objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_TIMER_NUM #define OS_TIMER_NUM 0 // DAPLINK. Default was: 1 #endif - + // - + // Timer Thread Priority // <8=> Low // <16=> Below Normal <24=> Normal <32=> Above Normal @@ -194,7 +194,7 @@ #ifndef OS_TIMER_THREAD_PRIO #define OS_TIMER_THREAD_PRIO 40 #endif - + // Timer Thread Stack size [bytes] <0-1073741824:8> // Defines stack size for Timer thread. // May be set to 0 when timers are not used. @@ -202,7 +202,7 @@ #ifndef OS_TIMER_THREAD_STACK_SIZE #define OS_TIMER_THREAD_STACK_SIZE 128 // 512 #endif - + // Timer Thread TrustZone Module Identifier // Defines TrustZone Thread Context Management Identifier. // Applies only to cores with TrustZone technology. @@ -210,7 +210,7 @@ #ifndef OS_TIMER_THREAD_TZ_MOD_ID #define OS_TIMER_THREAD_TZ_MOD_ID 0 #endif - + // Timer Callback Queue entries <0-256> // Number of concurrent active timer callback functions. // May be set to 0 when timers are not used. @@ -218,85 +218,85 @@ #ifndef OS_TIMER_CB_QUEUE #define OS_TIMER_CB_QUEUE 4 #endif - + // - + // Event Flags Configuration // ============================ - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_EVFLAGS_OBJ_MEM #define OS_EVFLAGS_OBJ_MEM 0 #endif - + // Number of Event Flags objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_EVFLAGS_NUM #define OS_EVFLAGS_NUM 1 #endif - + // - + // - + // Mutex Configuration // ====================== - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_MUTEX_OBJ_MEM #define OS_MUTEX_OBJ_MEM 0 #endif - + // Number of Mutex objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_MUTEX_NUM #define OS_MUTEX_NUM 1 #endif - + // - + // - + // Semaphore Configuration // ========================== - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_SEMAPHORE_OBJ_MEM #define OS_SEMAPHORE_OBJ_MEM 0 #endif - + // Number of Semaphore objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_SEMAPHORE_NUM #define OS_SEMAPHORE_NUM 0 // DAPLINK. Default was: 1 #endif - + // - + // - + // Memory Pool Configuration // ============================ - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_MEMPOOL_OBJ_MEM #define OS_MEMPOOL_OBJ_MEM 0 #endif - + // Number of Memory Pool objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_MEMPOOL_NUM #define OS_MEMPOOL_NUM 0 // DAPLINK. Default was: 1 #endif - + // Data Storage Memory size [bytes] <0-1073741824:8> // Defines the combined data storage memory size. // Applies to objects with system provided memory for data storage. @@ -304,27 +304,27 @@ #ifndef OS_MEMPOOL_DATA_SIZE #define OS_MEMPOOL_DATA_SIZE 0 #endif - + // - + // - + // Message Queue Configuration // ============================== - + // Object specific Memory allocation // Enables object specific memory allocation. #ifndef OS_MSGQUEUE_OBJ_MEM #define OS_MSGQUEUE_OBJ_MEM 0 #endif - + // Number of Message Queue objects <1-1000> // Defines maximum number of objects that can be active at the same time. // Applies to objects with system provided memory for control blocks. #ifndef OS_MSGQUEUE_NUM #define OS_MSGQUEUE_NUM 0 // DAPLINK. Default was: 1 #endif - + // Data Storage Memory size [bytes] <0-1073741824:8> // Defines the combined data storage memory size. // Applies to objects with system provided memory for data storage. @@ -332,26 +332,29 @@ #ifndef OS_MSGQUEUE_DATA_SIZE #define OS_MSGQUEUE_DATA_SIZE 0 #endif - + // - + // - + // Event Recorder Configuration // =============================== - + +// Completely disable the event recorder. +#define EVR_RTX_DISABLE 1 // DAPLINK. Default was undefined + // Global Initialization // Initialize Event Recorder during 'osKernelInitialize'. #ifndef OS_EVR_INIT #define OS_EVR_INIT 0 #endif - + // Start recording // Start event recording after initialization. #ifndef OS_EVR_START #define OS_EVR_START 0 // DAPLINK. Default was: 1 #endif - + // Global Event Filter Setup // Initial recording level applied to all components. // Error events @@ -362,11 +365,11 @@ #ifndef OS_EVR_LEVEL #define OS_EVR_LEVEL 0x00U #endif - + // RTOS Event Filter Setup // Recording levels for RTX components. // Only applicable if events for the respective component are generated. - + // Memory Management // Recording level for Memory Management events. // Error events @@ -374,10 +377,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_MEMORY_LEVEL +#ifndef OS_EVR_MEMORY_LEVEL #define OS_EVR_MEMORY_LEVEL 0x01U #endif - + // Kernel // Recording level for Kernel events. // Error events @@ -385,10 +388,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_KERNEL_LEVEL +#ifndef OS_EVR_KERNEL_LEVEL #define OS_EVR_KERNEL_LEVEL 0x01U #endif - + // Thread // Recording level for Thread events. // Error events @@ -396,10 +399,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_THREAD_LEVEL +#ifndef OS_EVR_THREAD_LEVEL #define OS_EVR_THREAD_LEVEL 0x05U #endif - + // Generic Wait // Recording level for Generic Wait events. // Error events @@ -407,10 +410,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_WAIT_LEVEL +#ifndef OS_EVR_WAIT_LEVEL #define OS_EVR_WAIT_LEVEL 0x01U #endif - + // Thread Flags // Recording level for Thread Flags events. // Error events @@ -418,10 +421,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_THFLAGS_LEVEL +#ifndef OS_EVR_THFLAGS_LEVEL #define OS_EVR_THFLAGS_LEVEL 0x01U #endif - + // Event Flags // Recording level for Event Flags events. // Error events @@ -429,10 +432,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_EVFLAGS_LEVEL +#ifndef OS_EVR_EVFLAGS_LEVEL #define OS_EVR_EVFLAGS_LEVEL 0x01U #endif - + // Timer // Recording level for Timer events. // Error events @@ -440,10 +443,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_TIMER_LEVEL +#ifndef OS_EVR_TIMER_LEVEL #define OS_EVR_TIMER_LEVEL 0x01U #endif - + // Mutex // Recording level for Mutex events. // Error events @@ -451,10 +454,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_MUTEX_LEVEL +#ifndef OS_EVR_MUTEX_LEVEL #define OS_EVR_MUTEX_LEVEL 0x01U #endif - + // Semaphore // Recording level for Semaphore events. // Error events @@ -462,10 +465,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_SEMAPHORE_LEVEL +#ifndef OS_EVR_SEMAPHORE_LEVEL #define OS_EVR_SEMAPHORE_LEVEL 0x01U #endif - + // Memory Pool // Recording level for Memory Pool events. // Error events @@ -473,10 +476,10 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_MEMPOOL_LEVEL +#ifndef OS_EVR_MEMPOOL_LEVEL #define OS_EVR_MEMPOOL_LEVEL 0x01U #endif - + // Message Queue // Recording level for Message Queue events. // Error events @@ -484,87 +487,87 @@ // Operation events // Detailed operation events // -#ifndef OS_EVR_MSGQUEUE_LEVEL +#ifndef OS_EVR_MSGQUEUE_LEVEL #define OS_EVR_MSGQUEUE_LEVEL 0x01U #endif - + // - + // - + // RTOS Event Generation // Enables event generation for RTX components (requires RTX source variant). - + // Memory Management // Enables Memory Management event generation. #ifndef OS_EVR_MEMORY #define OS_EVR_MEMORY 1 #endif - + // Kernel // Enables Kernel event generation. #ifndef OS_EVR_KERNEL #define OS_EVR_KERNEL 1 #endif - + // Thread // Enables Thread event generation. #ifndef OS_EVR_THREAD #define OS_EVR_THREAD 1 #endif - + // Generic Wait // Enables Generic Wait event generation. #ifndef OS_EVR_WAIT #define OS_EVR_WAIT 1 #endif - + // Thread Flags // Enables Thread Flags event generation. #ifndef OS_EVR_THFLAGS #define OS_EVR_THFLAGS 1 #endif - + // Event Flags // Enables Event Flags event generation. #ifndef OS_EVR_EVFLAGS #define OS_EVR_EVFLAGS 1 #endif - + // Timer // Enables Timer event generation. #ifndef OS_EVR_TIMER #define OS_EVR_TIMER 1 #endif - + // Mutex // Enables Mutex event generation. #ifndef OS_EVR_MUTEX #define OS_EVR_MUTEX 1 #endif - + // Semaphore // Enables Semaphore event generation. #ifndef OS_EVR_SEMAPHORE #define OS_EVR_SEMAPHORE 1 #endif - + // Memory Pool // Enables Memory Pool event generation. #ifndef OS_EVR_MEMPOOL #define OS_EVR_MEMPOOL 1 #endif - + // Message Queue // Enables Message Queue event generation. #ifndef OS_EVR_MSGQUEUE #define OS_EVR_MSGQUEUE 1 #endif - + // - + // - + // Number of Threads which use standard C/C++ library libspace // (when thread specific memory allocation is not used). #if (OS_THREAD_OBJ_MEM == 0) @@ -574,7 +577,7 @@ #else #define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM #endif - + //------------- <<< end of configuration section >>> --------------------------- - + #endif // RTX_CONFIG_H_ From 70671a02fc007f5c1868190ea74428c3faa7f0c1 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sat, 2 Jan 2021 16:58:20 -0600 Subject: [PATCH 075/617] Interface: fix RTOS setup in main_interface.c. --- records/rtos/rtos-cm0.yaml | 4 ++ records/rtos/rtos-cm3.yaml | 4 ++ records/rtos/rtos-cm4.yaml | 4 ++ source/daplink/HardFault_Handler.c | 4 +- source/daplink/bootloader/main_bootloader.c | 14 ++---- source/daplink/interface/main_interface.c | 56 ++++++++++++++++++--- source/daplink/interface/tasks.h | 21 +------- 7 files changed, 67 insertions(+), 40 deletions(-) diff --git a/records/rtos/rtos-cm0.yaml b/records/rtos/rtos-cm0.yaml index 76b8de45a..5c67e7444 100644 --- a/records/rtos/rtos-cm0.yaml +++ b/records/rtos/rtos-cm0.yaml @@ -44,6 +44,8 @@ tool_specific: - source/rtos/RTX_Config.c - source/rtos/cmsis_os2_port.c armclang: + macros: + - USE_CMSIS_RTOS2 includes: - source/rtos2/Include - source/rtos2/RTX/Include @@ -64,6 +66,8 @@ tool_specific: - source/rtos2/RTX/Source/rtx_timer.c - source/rtos2/Source/os_systick.c gcc_arm: + macros: + - USE_CMSIS_RTOS2 includes: - source/rtos2/Include - source/rtos2/RTX/Include diff --git a/records/rtos/rtos-cm3.yaml b/records/rtos/rtos-cm3.yaml index 2fac4704b..c8842f922 100644 --- a/records/rtos/rtos-cm3.yaml +++ b/records/rtos/rtos-cm3.yaml @@ -44,6 +44,8 @@ tool_specific: - source/rtos/RTX_Config.c - source/rtos/cmsis_os2_port.c armclang: + macros: + - USE_CMSIS_RTOS2 includes: - source/rtos2/Include - source/rtos2/RTX/Include @@ -64,6 +66,8 @@ tool_specific: - source/rtos2/RTX/Source/rtx_timer.c - source/rtos2/Source/os_systick.c gcc_arm: + macros: + - USE_CMSIS_RTOS2 includes: - source/rtos2/Include - source/rtos2/RTX/Include diff --git a/records/rtos/rtos-cm4.yaml b/records/rtos/rtos-cm4.yaml index 18d6c5bb8..16e11993f 100644 --- a/records/rtos/rtos-cm4.yaml +++ b/records/rtos/rtos-cm4.yaml @@ -46,6 +46,8 @@ tool_specific: - source/rtos/RTX_Config.c - source/rtos/cmsis_os2_port.c armclang: + macros: + - USE_CMSIS_RTOS2 includes: - source/rtos2/Include - source/rtos2/RTX/Include @@ -66,6 +68,8 @@ tool_specific: - source/rtos2/RTX/Source/rtx_timer.c - source/rtos2/Source/os_systick.c gcc_arm: + macros: + - USE_CMSIS_RTOS2 includes: - source/rtos2/Include - source/rtos2/RTX/Include diff --git a/source/daplink/HardFault_Handler.c b/source/daplink/HardFault_Handler.c index ff7d9ee84..7c2083e44 100644 --- a/source/daplink/HardFault_Handler.c +++ b/source/daplink/HardFault_Handler.c @@ -70,13 +70,13 @@ __NO_RETURN void _fault_handler(uint32_t _lr) while (1); // Wait for reset } -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +#if defined(__CC_ARM) // armcc void HardFault_Handler() { register unsigned int _lr __asm("lr"); _fault_handler(_lr); } -#else +#else // gcc and armclang void HardFault_Handler() { asm volatile ( diff --git a/source/daplink/bootloader/main_bootloader.c b/source/daplink/bootloader/main_bootloader.c index 95f382068..f4b9541cd 100644 --- a/source/daplink/bootloader/main_bootloader.c +++ b/source/daplink/bootloader/main_bootloader.c @@ -38,20 +38,12 @@ #define MSC_LED_DEF GPIO_LED_ON #endif -/* Avoids the semihosting issue */ #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +/* Avoids the semihosting issue */ __asm(" .global __ARM_use_no_argv\n"); -#endif - -#if defined(__CC_ARM) || \ - (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -#ifndef __MICROLIB -void _platform_post_stackheap_init (void) { -} -#endif #elif defined(__GNUC__) -void software_init_hook (void) { -} +/* Disables part of C/C++ runtime startup/teardown */ +void __libc_init_array (void) {} #endif #if defined(__CC_ARM) diff --git a/source/daplink/interface/main_interface.c b/source/daplink/interface/main_interface.c index 6d8bfb395..b0e2c0b73 100644 --- a/source/daplink/interface/main_interface.c +++ b/source/daplink/interface/main_interface.c @@ -46,20 +46,23 @@ #include "flash_manager.h" #endif -/* Avoids the semihosting issue */ -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -__asm(" .global __ARM_use_no_argv\n"); +#ifdef USE_CMSIS_RTOS2 +#include "rtx_os.h" #endif -#if defined(__CC_ARM) || \ - (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) #ifndef __MICROLIB /* Avoids early implicit call to osKernelInitialize() */ void _platform_post_stackheap_init (void) {} #endif +#if (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +/* Avoids the semihosting issue */ +__asm(" .global __ARM_use_no_argv\n"); +#endif #elif defined(__GNUC__) /* Avoids early implicit call to osKernelInitialize() */ void software_init_hook (void) {} +/* Disables part of C/C++ runtime startup/teardown */ void __libc_init_array (void) {} #endif @@ -108,6 +111,25 @@ void __libc_init_array (void) {} // Reference to our main task osThreadId_t main_task_id; +#ifdef USE_CMSIS_RTOS2 +static uint32_t s_main_thread_cb[WORDS(sizeof(osRtxThread_t))]; +static uint64_t s_main_task_stack[MAIN_TASK_STACK / sizeof(uint64_t)]; +static const osThreadAttr_t k_main_thread_attr = { + .name = "main", + .cb_mem = s_main_thread_cb, + .cb_size = sizeof(s_main_thread_cb), + .stack_mem = s_main_task_stack, + .stack_size = sizeof(s_main_task_stack), + .priority = MAIN_TASK_PRIORITY, + }; + +static uint32_t s_timer_30ms_cb[WORDS(sizeof(osRtxTimer_t))]; +static const osTimerAttr_t k_timer_30ms_attr = { + .name = "30ms", + .cb_mem = s_timer_30ms_cb, + .cb_size = sizeof(s_timer_30ms_cb), + }; +#endif // USB busy LED state; when TRUE the LED will flash once using 30mS clock tick static uint8_t hid_led_usb_activity = 0; @@ -215,8 +237,11 @@ void main_task(void * arg) // Initialize settings - required for asserts to work config_init(); + +#ifndef USE_CMSIS_RTOS2 // Get a reference to this task main_task_id = osThreadGetId(); +#endif // leds gpio_init(); // Turn to LED default settings @@ -265,7 +290,11 @@ void main_task(void * arg) usb_state_count = USB_CONNECT_DELAY; // Start timer tasks +#ifdef USE_CMSIS_RTOS2 + osTimerId_t tmr_id = osTimerNew(timer_task_30mS, osTimerPeriodic, NULL, &k_timer_30ms_attr); +#else osTimerId_t tmr_id = osTimerNew(timer_task_30mS, osTimerPeriodic, NULL, NULL); +#endif osTimerStart(tmr_id, 3); while (1) { flags = osThreadFlagsWait(FLAGS_MAIN_RESET // Put target in reset state @@ -485,8 +514,19 @@ int main(void) // initialize vendor sdk sdk_init(); - osKernelInitialize(); // Initialize CMSIS-RTOS - osThreadNew(main_task, NULL, NULL); // Create application main thread - osKernelStart(); // Start thread execution + // Initialize CMSIS-RTOS + osKernelInitialize(); + + // Create application main thread +#ifdef USE_CMSIS_RTOS2 + main_task_id = osThreadNew(main_task, NULL, &k_main_thread_attr); +#else + osThreadNew(main_task, NULL, NULL); +#endif + + // Start thread execution + osKernelStart(); + + // Should never reach here! for (;;) {} } diff --git a/source/daplink/interface/tasks.h b/source/daplink/interface/tasks.h index 1c6ca2243..f0274440f 100644 --- a/source/daplink/interface/tasks.h +++ b/source/daplink/interface/tasks.h @@ -3,7 +3,7 @@ * @brief Macros for configuring the run time tasks * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2020, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -22,27 +22,10 @@ #ifndef TASK_H #define TASK_H -#ifdef __cplusplus -extern "C" { -#endif - -#define NO_TIMEOUT (0xffff) - -#define LOWEST_PRIORITY (1) /* Priority 0 is reserved for the RTX idle task */ -#define HIGHEST_PRIORITY (254) /* Priority 255 is reserved by RTX */ - -#define MAIN_TASK_PRIORITY (10) -#define TIMER_TASK_PRIORITY (11) -#define TIMER_TASK_30_PRIORITY (TIMER_TASK_PRIORITY) - // trouble here is that reset for different targets is implemented differently so all targets // have to use the largest stack or these have to be defined in multiple places... Not ideal // may want to move away from threads for some of these behaviours to optimize mempory usage (RAM) -#define TIMER_TASK_30_STACK (136) #define MAIN_TASK_STACK (800) - -#ifdef __cplusplus -} -#endif +#define MAIN_TASK_PRIORITY (osPriorityNormal) #endif From 14fd23d7074ecb46fa584eafe8c11652b69b8200 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 2 Jan 2021 19:33:23 -0600 Subject: [PATCH 076/617] Fix core for stm32f103xb HIC --- records/hic_hal/stm32f103xb.yaml | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/records/hic_hal/stm32f103xb.yaml b/records/hic_hal/stm32f103xb.yaml index 361842bb0..01e648bfa 100644 --- a/records/hic_hal/stm32f103xb.yaml +++ b/records/hic_hal/stm32f103xb.yaml @@ -1,6 +1,6 @@ common: target: - - stm32f103xb + - Cortex-M3 core: - Cortex-M3 macros: @@ -38,17 +38,10 @@ tool_specific: hic_hal: - source/hic_hal/stm32/stm32f103xb/armcc armclang: - misc: - c_flags: - - -mcpu=cortex-m3 - asm_flags: - - -mcpu=cortex-m3 sources: hic_hal: - source/hic_hal/stm32/stm32f103xb/armcc gcc_arm: - includes: - - source/hic_hal/stm32/stm32f103xb/gcc sources: hic_hal: - source/hic_hal/stm32/stm32f103xb/gcc From 020d652bebab00e32c19cc30bd55c20701ea4d72 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 2 Jan 2021 22:06:01 -0600 Subject: [PATCH 077/617] Use gcc Hardfault_Handler for armclang --- source/daplink/HardFault_Handler.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/daplink/HardFault_Handler.c b/source/daplink/HardFault_Handler.c index 7c2083e44..73fc3d177 100644 --- a/source/daplink/HardFault_Handler.c +++ b/source/daplink/HardFault_Handler.c @@ -79,7 +79,7 @@ void HardFault_Handler() #else // gcc and armclang void HardFault_Handler() { - asm volatile ( + __ASM volatile ( " mov r0, lr \n\t" " bl _fault_handler \n\t" ); From 243837343a819367106938b6bba21694b10538d9 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sun, 3 Jan 2021 08:45:37 -0600 Subject: [PATCH 078/617] Set heap and stack size through defines, increase bootloader stack size --- records/tools/gcc_arm.yaml | 2 -- source/daplink/daplink.ld | 9 ++--- source/daplink/daplink_defaults.h | 37 +++++++++++++++++++++ source/hic_hal/freescale/kinetis.ld | 11 +++--- source/hic_hal/nxp/lpc11u35/gcc/lpc11u35.ld | 11 +++--- 5 files changed, 54 insertions(+), 16 deletions(-) create mode 100644 source/daplink/daplink_defaults.h diff --git a/records/tools/gcc_arm.yaml b/records/tools/gcc_arm.yaml index acdb135b8..922aa0dba 100644 --- a/records/tools/gcc_arm.yaml +++ b/records/tools/gcc_arm.yaml @@ -29,8 +29,6 @@ tool_specific: - --specs=nano.specs - --specs=nosys.specs - -Wl,-check-sections - - -Wl,--defsym=__stack_size__=0x200 - - -Wl,--defsym=__heap_size__=0x0 - -Wl,-fatal-warnings - -Wl,--gc-sections - -Wl,--no-wchar-size-warning diff --git a/source/daplink/daplink.ld b/source/daplink/daplink.ld index b45e3851e..375fb378e 100644 --- a/source/daplink/daplink.ld +++ b/source/daplink/daplink.ld @@ -1,11 +1,11 @@ /** * @file daplink.ld - * @brief + * @brief default gcc linker script * * DAPLink Interface Firmware * Copyright 2016 Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * Copyright (c) 2019, ARM Limited + * Copyright (c) 2021, Arm Limited * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -22,12 +22,13 @@ */ #include "daplink_addr.h" +#include "daplink_defaults.h" /* Entry Point */ ENTRY(Reset_Handler) -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : DAPLINK_HEAP_SIZE; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : DAPLINK_STACK_SIZE; /* Specify the memory areas */ MEMORY diff --git a/source/daplink/daplink_defaults.h b/source/daplink/daplink_defaults.h new file mode 100644 index 000000000..4a65f8a9a --- /dev/null +++ b/source/daplink/daplink_defaults.h @@ -0,0 +1,37 @@ +/** + * @file daplink_defaults.h + * @brief Default settings + * + * DAPLink Interface Firmware + * Copyright (c) 2021, Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DAPLINK_DEFAULTS_H +#define DAPLINK_DEFAULTS_H + +#ifndef DAPLINK_HEAP_SIZE +#define DAPLINK_HEAP_SIZE 0x0 +#endif + +#ifndef DAPLINK_STACK_SIZE +#if defined(DAPLINK_BL) +#define DAPLINK_STACK_SIZE 0x800 +#elif defined(DAPLINK_IF) +#define DAPLINK_STACK_SIZE 0x200 +#endif +#endif + +#endif diff --git a/source/hic_hal/freescale/kinetis.ld b/source/hic_hal/freescale/kinetis.ld index b75bc6a48..4572b23d3 100644 --- a/source/hic_hal/freescale/kinetis.ld +++ b/source/hic_hal/freescale/kinetis.ld @@ -1,11 +1,11 @@ /** - * @file daplink.ld - * @brief + * @file kinetis.ld + * @brief Kinetis linker script * * DAPLink Interface Firmware * Copyright 2016 Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * Copyright (c) 2019, ARM Limited + * Copyright (c) 2021, Arm Limited * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -22,12 +22,13 @@ */ #include "daplink_addr.h" +#include "daplink_defaults.h" /* Entry Point */ ENTRY(Reset_Handler) -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : DAPLINK_HEAP_SIZE; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : DAPLINK_STACK_SIZE; /* Specify the memory areas */ MEMORY diff --git a/source/hic_hal/nxp/lpc11u35/gcc/lpc11u35.ld b/source/hic_hal/nxp/lpc11u35/gcc/lpc11u35.ld index 7922d37e8..dd49c146d 100644 --- a/source/hic_hal/nxp/lpc11u35/gcc/lpc11u35.ld +++ b/source/hic_hal/nxp/lpc11u35/gcc/lpc11u35.ld @@ -1,11 +1,11 @@ /** - * @file daplink.ld - * @brief + * @file lpc11u35.ld + * @brief LPC11U35 linker script * * DAPLink Interface Firmware * Copyright 2016 Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP - * Copyright (c) 2019, ARM Limited + * Copyright (c) 2021, Arm Limited * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -22,12 +22,13 @@ */ #include "daplink_addr.h" +#include "daplink_defaults.h" /* Entry Point */ ENTRY(Reset_Handler) -HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; -STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : DAPLINK_HEAP_SIZE; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : DAPLINK_STACK_SIZE; /* Specify the memory areas */ MEMORY From 26ecf80574a4745d131318237b8cbf3c4b5a7330 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sun, 3 Jan 2021 20:37:01 -0600 Subject: [PATCH 079/617] Simplify HIC records + armcc fix - Remove superfluous compilation directives - Disable unaligned accesses at the toolchain level for all HICs - Fix for armcc compilation --- records/hic_hal/k20dx.yaml | 5 ----- records/hic_hal/k26f.yaml | 16 ---------------- records/hic_hal/kl26z.yaml | 5 ----- records/hic_hal/kl27z.yaml | 5 ++--- records/hic_hal/lpc11u35.yaml | 5 ----- records/hic_hal/lpc4322.yaml | 5 ----- records/hic_hal/m48ssidae.yaml | 5 ----- records/hic_hal/max32620.yaml | 5 ----- records/hic_hal/max32625.yaml | 5 ----- records/hic_hal/sam3u2c.yaml | 5 ----- records/hic_hal/stm32f103xb.yaml | 3 --- records/tools/armcc.yaml | 2 ++ records/tools/armclang.yaml | 2 ++ records/tools/gcc_arm.yaml | 2 +- 14 files changed, 7 insertions(+), 63 deletions(-) diff --git a/records/hic_hal/k20dx.yaml b/records/hic_hal/k20dx.yaml index e29b96cab..85f981e0e 100644 --- a/records/hic_hal/k20dx.yaml +++ b/records/hic_hal/k20dx.yaml @@ -33,9 +33,6 @@ tool_specific: hic_hal: - source/hic_hal/freescale/k20dx/armcc armcc: - misc: - ld_flags: - - --predefine="-Isource/hic_hal/freescale/k20dx" sources: hic_hal: - source/hic_hal/freescale/k20dx/armcc @@ -46,8 +43,6 @@ tool_specific: gcc_arm: linker_file: - source/hic_hal/freescale/kinetis.ld - includes: - - source/hic_hal/freescale/k20dx/gcc sources: hic_hal: - source/hic_hal/freescale/k20dx/gcc diff --git a/records/hic_hal/k26f.yaml b/records/hic_hal/k26f.yaml index 831113647..d7cd05516 100644 --- a/records/hic_hal/k26f.yaml +++ b/records/hic_hal/k26f.yaml @@ -40,34 +40,18 @@ tool_specific: - source/hic_hal/freescale/k26f/armcc armcc: misc: - ld_flags: - - --predefine="-Isource/hic_hal/freescale/k26f" c_flags: - - --no_unaligned_access - --diag_suppress=66 # disable warning about enums not fitting in signed 32-bit - cxx_flags: - - --no_unaligned_access - asm_flags: - - --no_unaligned_access sources: hic_hal: - source/hic_hal/freescale/k26f/armcc armclang: - misc: - c_flags: - - -mno-unaligned-access - cxx_flags: - - -mno-unaligned-access - asm_flags: - - -Wa,armasm,--no_unaligned_access sources: hic_hal: - source/hic_hal/freescale/k26f/armcc gcc_arm: linker_file: - source/hic_hal/freescale/kinetis.ld - includes: - - source/hic_hal/freescale/k26f/gcc sources: hic_hal: - source/hic_hal/freescale/k26f/gcc diff --git a/records/hic_hal/kl26z.yaml b/records/hic_hal/kl26z.yaml index c6bf46995..d60f912d1 100644 --- a/records/hic_hal/kl26z.yaml +++ b/records/hic_hal/kl26z.yaml @@ -33,9 +33,6 @@ tool_specific: hic_hal: - source/hic_hal/freescale/kl26z/armcc armcc: - misc: - ld_flags: - - --predefine="-Isource/hic_hal/freescale/kl26z" sources: hic_hal: - source/hic_hal/freescale/kl26z/armcc @@ -46,8 +43,6 @@ tool_specific: gcc_arm: linker_file: - source/hic_hal/freescale/kinetis.ld - includes: - - source/hic_hal/freescale/kl26z/gcc sources: hic_hal: - source/hic_hal/freescale/kl26z/gcc diff --git a/records/hic_hal/kl27z.yaml b/records/hic_hal/kl27z.yaml index faa34e979..1e887bf87 100644 --- a/records/hic_hal/kl27z.yaml +++ b/records/hic_hal/kl27z.yaml @@ -32,14 +32,13 @@ tool_specific: sources: - source/hic_hal/freescale/kl27z/armcc armcc: - misc: - ld_flags: - - --predefine="-Isource\hic_hal\freescale\kl27z" sources: - source/hic_hal/freescale/kl27z/armcc armclang: sources: - source/hic_hal/freescale/kl27z/armcc gcc_arm: + linker_file: + - source/hic_hal/freescale/kinetis.ld sources: - source/hic_hal/freescale/kl27z/gcc diff --git a/records/hic_hal/lpc11u35.yaml b/records/hic_hal/lpc11u35.yaml index 01a9db526..7251d3cd3 100644 --- a/records/hic_hal/lpc11u35.yaml +++ b/records/hic_hal/lpc11u35.yaml @@ -22,9 +22,6 @@ tool_specific: hic_hal: - source/hic_hal/nxp/lpc11u35/armcc armcc: - misc: - ld_flags: - - --predefine="-Isource/hic_hal/nxp/lpc11u35" sources: hic_hal: - source/hic_hal/nxp/lpc11u35/armcc @@ -35,8 +32,6 @@ tool_specific: gcc_arm: linker_file: - source/hic_hal/nxp/lpc11u35/gcc/lpc11u35.ld - includes: - - source/hic_hal/nxp/lpc11u35/gcc sources: hic_hal: - source/hic_hal/nxp/lpc11u35/gcc diff --git a/records/hic_hal/lpc4322.yaml b/records/hic_hal/lpc4322.yaml index d2c64ca76..651fb18d2 100644 --- a/records/hic_hal/lpc4322.yaml +++ b/records/hic_hal/lpc4322.yaml @@ -24,9 +24,6 @@ tool_specific: hic_hal: - source/hic_hal/nxp/lpc4322/armcc armcc: - misc: - ld_flags: - - --predefine="-Isource/hic_hal/nxp/lpc4322" sources: hic_hal: - source/hic_hal/nxp/lpc4322/armcc @@ -35,8 +32,6 @@ tool_specific: hic_hal: - source/hic_hal/nxp/lpc4322/armcc gcc_arm: - includes: - - source/hic_hal/nxp/lpc4322/gcc sources: hic_hal: - source/hic_hal/nxp/lpc4322/gcc diff --git a/records/hic_hal/m48ssidae.yaml b/records/hic_hal/m48ssidae.yaml index 819bee598..eb7159d1c 100644 --- a/records/hic_hal/m48ssidae.yaml +++ b/records/hic_hal/m48ssidae.yaml @@ -28,9 +28,6 @@ tool_specific: hic_hal: - source/hic_hal/nuvoton/m48ssidae/armcc armcc: - misc: - ld_flags: - - --predefine="-Isource/hic_hal/nuvoton/m48ssidae" sources: hic_hal: - source/hic_hal/nuvoton/m48ssidae/armcc @@ -39,8 +36,6 @@ tool_specific: hic_hal: - source/hic_hal/nuvoton/m48ssidae/armcc gcc_arm: - includes: - - source/hic_hal/nuvoton/m48ssidae/gcc sources: hic_hal: - source/hic_hal/nuvoton/m48ssidae/gcc diff --git a/records/hic_hal/max32620.yaml b/records/hic_hal/max32620.yaml index a348320ec..d302903fc 100644 --- a/records/hic_hal/max32620.yaml +++ b/records/hic_hal/max32620.yaml @@ -22,9 +22,6 @@ tool_specific: hic_hal: - source/hic_hal/maxim/max32620/armcc armcc: - misc: - ld_flags: - - --predefine="-Isource/hic_hal/maxim/max32620" sources: hic_hal: - source/hic_hal/maxim/max32620/armcc @@ -33,8 +30,6 @@ tool_specific: hic_hal: - source/hic_hal/maxim/max32620/armcc gcc_arm: - includes: - - source/hic_hal/maxim/max32620/gcc sources: hic_hal: - source/hic_hal/maxim/max32620/gcc diff --git a/records/hic_hal/max32625.yaml b/records/hic_hal/max32625.yaml index 47e3a9353..c7140bf22 100644 --- a/records/hic_hal/max32625.yaml +++ b/records/hic_hal/max32625.yaml @@ -22,9 +22,6 @@ tool_specific: hic_hal: - source/hic_hal/maxim/max32625/armcc armcc: - misc: - ld_flags: - - --predefine="-Isource/hic_hal/maxim/max32625" sources: hic_hal: - source/hic_hal/maxim/max32625/armcc @@ -33,8 +30,6 @@ tool_specific: hic_hal: - source/hic_hal/maxim/max32625/armcc gcc_arm: - includes: - - source/hic_hal/maxim/max32625/gcc sources: hic_hal: - source/hic_hal/maxim/max32625/gcc diff --git a/records/hic_hal/sam3u2c.yaml b/records/hic_hal/sam3u2c.yaml index 5807849ca..1ffd1b34a 100644 --- a/records/hic_hal/sam3u2c.yaml +++ b/records/hic_hal/sam3u2c.yaml @@ -25,9 +25,6 @@ tool_specific: hic_hal: - source/hic_hal/atmel/sam3u2c/armcc armcc: - misc: - ld_flags: - - --predefine="-Isource/hic_hal/atmel/sam3u2c" sources: hic_hal: - source/hic_hal/atmel/sam3u2c/armcc @@ -36,8 +33,6 @@ tool_specific: hic_hal: - source/hic_hal/atmel/sam3u2c/armcc gcc_arm: - includes: - - source/hic_hal/atmel/sam3u2c/gcc sources: hic_hal: - source/hic_hal/atmel/sam3u2c/gcc diff --git a/records/hic_hal/stm32f103xb.yaml b/records/hic_hal/stm32f103xb.yaml index 01e648bfa..b1ff0351b 100644 --- a/records/hic_hal/stm32f103xb.yaml +++ b/records/hic_hal/stm32f103xb.yaml @@ -31,9 +31,6 @@ tool_specific: hic_hal: - source/hic_hal/stm32/stm32f103xb/armcc armcc: - misc: - ld_flags: - - --predefine="-Isource/hic_hal/stm32/stm32f103xb" sources: hic_hal: - source/hic_hal/stm32/stm32f103xb/armcc diff --git a/records/tools/armcc.yaml b/records/tools/armcc.yaml index 06e469274..6b055f438 100644 --- a/records/tools/armcc.yaml +++ b/records/tools/armcc.yaml @@ -9,6 +9,7 @@ tool_specific: misc: asm_flags: - -g + - --no_unaligned_access c_flags: - -O2 - -Ospace @@ -18,6 +19,7 @@ tool_specific: - --split_sections - --interleave - -g + - --no_unaligned_access ld_flags: - --bestdebug - --summary_stderr diff --git a/records/tools/armclang.yaml b/records/tools/armclang.yaml index 530258a93..e8b4968ca 100644 --- a/records/tools/armclang.yaml +++ b/records/tools/armclang.yaml @@ -11,6 +11,7 @@ tool_specific: - -g - -x assembler-with-cpp - -masm=auto + - -Wa,armasm,--no_unaligned_access cpp_flags: - --target=arm-arm-none-eabi c_flags: @@ -31,6 +32,7 @@ tool_specific: - -Warmcc-pragma-thumb - -Wno-ignored-optimization-argument - -Wno-unused-command-line-argument + - -mno-unaligned-access ld_flags: - --bestdebug - --summary_stderr diff --git a/records/tools/gcc_arm.yaml b/records/tools/gcc_arm.yaml index 922aa0dba..cdc189fc9 100644 --- a/records/tools/gcc_arm.yaml +++ b/records/tools/gcc_arm.yaml @@ -15,7 +15,7 @@ tool_specific: common_flags: - -Os - -g3 -# - -Wall + # - -Wall - -Werror - -ffunction-sections - -fdata-sections From 79bcae7d2aefea72723869e517d09af054c051da Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sun, 3 Jan 2021 10:00:39 -0600 Subject: [PATCH 080/617] Add support for CMake generators from command line --- tools/progen_compile.py | 122 ++++++++++++++++++++-------------------- 1 file changed, 62 insertions(+), 60 deletions(-) diff --git a/tools/progen_compile.py b/tools/progen_compile.py index ccd249418..068f6ec21 100755 --- a/tools/progen_compile.py +++ b/tools/progen_compile.py @@ -49,38 +49,12 @@ def load_project_list(path): print("Found yaml parse error", ex) return project_list - -def build_projects(file, projects, tool, build=True, clean=False, parallel=False, ignore_failures=False, verbose=False): - generator = generate.Generator(file) - cores = 1 - if parallel: - try: - import multiprocessing - cores = multiprocessing.cpu_count() - except: - cores = 4 - pass - - for p_name in projects: - for project in generator.generate(p_name): - failed = False - if hasattr(project, 'workspace_name') and (project.workspace_name is not None): - logger.info("Generating %s for %s in workspace %s", tool, project.name, project.workspace_name) - else: - logger.info("Generating %s for %s", tool, project.name) - if clean: - if project.clean(tool) == -1: - logger.error("Error cleaning project %s", project.name) - failed = True - if not failed and project.generate(tool) == -1: - logger.error("Error generating project %s", project.name) - failed = True - if build and not failed: - if project.build(tool, jobs=cores, verbose=verbose) == -1: - logger.error("Error building project %s", project.name) - failed = True - if failed and not ignore_failures: - return -1 +def get_core_count(): + try: + import multiprocessing + return multiprocessing.cpu_count() + except: + return 4 project_list = load_project_list(PROJECTS_YAML) parser = argparse.ArgumentParser(description='project-generator compile support for DAPLink', @@ -90,7 +64,9 @@ def build_projects(file, projects, tool, build=True, clean=False, parallel=False nargs='*', type=str, default=[]) parser.add_argument('--release', dest='release', action='store_true', help='Create a release with the yaml version file') parser.add_argument('--release-folder', type=str, default='firmware', help='Directory to create and place files in') +parser.add_argument('--supported', dest='supported', action='store_true', help='Generate the images with official identifiers') parser.add_argument('--toolchain', '-t', type=str, help='Toolchain (default: make_gcc_arm)') +parser.add_argument('--generator', '-g', type=str, help='CMake Toolchain Generator (default: make)') parser.add_argument('--clean', dest='clean', action='store_true', help='Rebuild or delete build folder before compile') parser.add_argument('--ignore-failures', dest='ignore_failures', action='store_true', help='Continue build even in case of failures') parser.add_argument('--parallel', dest='parallel', action='store_true', help='Build with multiple compilations in parallel') @@ -99,18 +75,20 @@ def build_projects(file, projects, tool, build=True, clean=False, parallel=False parser.set_defaults(clean=False) parser.set_defaults(ignore_failures=False) parser.set_defaults(parallel=False) +parser.set_defaults(supported=False) parser.set_defaults(release=False) args = parser.parse_args() toolchains = ["make_gcc_arm", "make_armcc", "make_armclang", # Make options - "cmake_gcc_arm", "cmake_armclang", # CMake options + "cmake_gcc_arm", "cmake_armcc", "cmake_armclang", # CMake options "gcc_arm", "armcc", "armclang"] # Aliases for the make options toolchain = args.toolchain if args.toolchain else 'make_gcc_arm' if toolchain not in toolchains: print("Unsupported toolchain '%s' (options: %s)\n" % (toolchain, ", ".join(toolchains))) exit(-1) + logging_level = logging.DEBUG if args.verbosity >= 2 else (logging.INFO if args.verbosity >= 1 else logging.WARNING) logging.basicConfig(format="%(asctime)s %(name)020s %(levelname)s\t%(message)s", level=logging_level) logger = logging.getLogger('progen_build') @@ -121,38 +99,62 @@ def build_projects(file, projects, tool, build=True, clean=False, parallel=False version_git_dir = os.path.join(daplink_dir, "source", "daplink") generate_version_file(version_git_dir) +# Build the project(s) +cores = get_core_count() if args.parallel else 1 projects = args.projects if len(args.projects) > 0 else project_list -build_projects(PROJECTS_YAML, projects, toolchain, args.build, args.clean, - args.parallel, args.ignore_failures, args.verbosity > 0) - -sys.path.append(os.path.join(daplink_dir, "test")) -from info import SUPPORTED_CONFIGURATIONS, PROJECT_RELEASE_INFO -id_map = {} -for board_id, family_id, firmware, bootloader, target in SUPPORTED_CONFIGURATIONS: - if firmware in id_map: - id_map[firmware].append((hex(board_id), hex(family_id))) - else: - id_map[firmware] = [(hex(board_id), hex(family_id))] -for project in projects: - output = "projectfiles/%s/%s/build/%s" % (toolchain, project, project) - hex = output + ".hex" - crc = output + "_crc" - - if not os.path.exists(hex): - # Build failed - if args.ignore_failures: - logger.warning("Missing file %s (build failed)" % (hex)) - continue +generator = generate.Generator(PROJECTS_YAML) +for p_name in projects: + for project in generator.generate(p_name): + failed = False + if hasattr(project, 'workspace_name') and (project.workspace_name is not None): + logger.info("Generating %s for %s in workspace %s", toolchain, project.name, project.workspace_name) else: - logger.error("Missing file %s (build failed)" % (hex)) + logger.info("Generating %s for %s", toolchain, project.name) + if args.clean: + if project.clean(toolchain) == -1: + logger.error("Error cleaning project %s", project.name) + failed = True + if not failed and project.generate(toolchain) == -1: + logger.error("Error generating project %s", project.name) + failed = True + if not failed: + if project.build(toolchain, jobs=cores, verbose=(args.verbosity > 0), generator=args.generator) == -1: + logger.error("Error building project %s", project.name) + failed = True + if failed and not args.ignore_failures: exit(-1) - # Do a build with board_id and family_id - if project in id_map: - for (boardid, familyid) in id_map[project]: - logger.debug("Building image for %s (%s, %s)" % (project, boardid, familyid)) - post_build_script(hex, crc, boardid, familyid) +# Generate images with boardid / familyid for supported configurations +if args.release or args.supported: + sys.path.append(os.path.join(daplink_dir, "test")) + from info import SUPPORTED_CONFIGURATIONS, PROJECT_RELEASE_INFO + id_map = {} + for board_id, family_id, firmware, bootloader, target in SUPPORTED_CONFIGURATIONS: + if firmware in id_map: + id_map[firmware].append((hex(board_id), hex(family_id))) + else: + id_map[firmware] = [(hex(board_id), hex(family_id))] + for project in projects: + output = "projectfiles/%s/%s/build/%s" % (toolchain, project, project) + hex = output + ".hex" + crc = output + "_crc" + + if not os.path.exists(hex): + # Build failed + if args.ignore_failures: + logger.warning("Missing file %s (build failed)" % (hex)) + continue + else: + logger.error("Missing file %s (build failed)" % (hex)) + exit(-1) + + # Do a build with board_id and family_id + if project in id_map: + for (boardid, familyid) in id_map[project]: + logger.debug("Building image for %s (%s, %s)" % (project, boardid, familyid)) + post_build_script(hex, crc, boardid, familyid) +# Build release package if args.release: release_version = 0 with open(VERSION_YAML, 'r') as ver_yaml: From b4d967a9efd81553d5a5e7535c9fbbfa826e90fe Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 4 Jan 2021 23:46:08 -0600 Subject: [PATCH 081/617] Make CMSIS-RTOS2 the default --- records/rtos/rtos-cm0.yaml | 8 ++++---- records/rtos/rtos-cm3.yaml | 8 ++++---- records/rtos/rtos-cm4.yaml | 8 ++++---- source/daplink/interface/main_interface.c | 10 +++++----- 4 files changed, 17 insertions(+), 17 deletions(-) diff --git a/records/rtos/rtos-cm0.yaml b/records/rtos/rtos-cm0.yaml index 5c67e7444..9f64681cd 100644 --- a/records/rtos/rtos-cm0.yaml +++ b/records/rtos/rtos-cm0.yaml @@ -4,6 +4,8 @@ common: - __ARM_ARCH_6M__=1 tool_specific: uvision: + macros: + - USE_LEGACY_CMSIS_RTOS includes: - source/rtos sources: @@ -24,6 +26,8 @@ tool_specific: - source/rtos/RTX_Config.c - source/rtos/cmsis_os2_port.c armcc: + macros: + - USE_LEGACY_CMSIS_RTOS includes: - source/rtos sources: @@ -44,8 +48,6 @@ tool_specific: - source/rtos/RTX_Config.c - source/rtos/cmsis_os2_port.c armclang: - macros: - - USE_CMSIS_RTOS2 includes: - source/rtos2/Include - source/rtos2/RTX/Include @@ -66,8 +68,6 @@ tool_specific: - source/rtos2/RTX/Source/rtx_timer.c - source/rtos2/Source/os_systick.c gcc_arm: - macros: - - USE_CMSIS_RTOS2 includes: - source/rtos2/Include - source/rtos2/RTX/Include diff --git a/records/rtos/rtos-cm3.yaml b/records/rtos/rtos-cm3.yaml index c8842f922..4ac78d7d2 100644 --- a/records/rtos/rtos-cm3.yaml +++ b/records/rtos/rtos-cm3.yaml @@ -4,6 +4,8 @@ common: tool_specific: uvision: + macros: + - USE_LEGACY_CMSIS_RTOS includes: - source/rtos sources: @@ -24,6 +26,8 @@ tool_specific: - source/rtos/RTX_Config.c - source/rtos/cmsis_os2_port.c armcc: + macros: + - USE_LEGACY_CMSIS_RTOS includes: - source/rtos sources: @@ -44,8 +48,6 @@ tool_specific: - source/rtos/RTX_Config.c - source/rtos/cmsis_os2_port.c armclang: - macros: - - USE_CMSIS_RTOS2 includes: - source/rtos2/Include - source/rtos2/RTX/Include @@ -66,8 +68,6 @@ tool_specific: - source/rtos2/RTX/Source/rtx_timer.c - source/rtos2/Source/os_systick.c gcc_arm: - macros: - - USE_CMSIS_RTOS2 includes: - source/rtos2/Include - source/rtos2/RTX/Include diff --git a/records/rtos/rtos-cm4.yaml b/records/rtos/rtos-cm4.yaml index 16e11993f..08fa4e098 100644 --- a/records/rtos/rtos-cm4.yaml +++ b/records/rtos/rtos-cm4.yaml @@ -6,6 +6,8 @@ common: # and the k20dx doesn't have the FP extension. tool_specific: uvision: + macros: + - USE_LEGACY_CMSIS_RTOS includes: - source/rtos sources: @@ -26,6 +28,8 @@ tool_specific: - source/rtos/RTX_Config.c - source/rtos/cmsis_os2_port.c armcc: + macros: + - USE_LEGACY_CMSIS_RTOS includes: - source/rtos sources: @@ -46,8 +50,6 @@ tool_specific: - source/rtos/RTX_Config.c - source/rtos/cmsis_os2_port.c armclang: - macros: - - USE_CMSIS_RTOS2 includes: - source/rtos2/Include - source/rtos2/RTX/Include @@ -68,8 +70,6 @@ tool_specific: - source/rtos2/RTX/Source/rtx_timer.c - source/rtos2/Source/os_systick.c gcc_arm: - macros: - - USE_CMSIS_RTOS2 includes: - source/rtos2/Include - source/rtos2/RTX/Include diff --git a/source/daplink/interface/main_interface.c b/source/daplink/interface/main_interface.c index b0e2c0b73..24f9678e7 100644 --- a/source/daplink/interface/main_interface.c +++ b/source/daplink/interface/main_interface.c @@ -46,7 +46,7 @@ #include "flash_manager.h" #endif -#ifdef USE_CMSIS_RTOS2 +#ifndef USE_LEGACY_CMSIS_RTOS #include "rtx_os.h" #endif @@ -111,7 +111,7 @@ void __libc_init_array (void) {} // Reference to our main task osThreadId_t main_task_id; -#ifdef USE_CMSIS_RTOS2 +#ifndef USE_LEGACY_CMSIS_RTOS static uint32_t s_main_thread_cb[WORDS(sizeof(osRtxThread_t))]; static uint64_t s_main_task_stack[MAIN_TASK_STACK / sizeof(uint64_t)]; static const osThreadAttr_t k_main_thread_attr = { @@ -238,7 +238,7 @@ void main_task(void * arg) // Initialize settings - required for asserts to work config_init(); -#ifndef USE_CMSIS_RTOS2 +#ifdef USE_LEGACY_CMSIS_RTOS // Get a reference to this task main_task_id = osThreadGetId(); #endif @@ -290,7 +290,7 @@ void main_task(void * arg) usb_state_count = USB_CONNECT_DELAY; // Start timer tasks -#ifdef USE_CMSIS_RTOS2 +#ifndef USE_LEGACY_CMSIS_RTOS osTimerId_t tmr_id = osTimerNew(timer_task_30mS, osTimerPeriodic, NULL, &k_timer_30ms_attr); #else osTimerId_t tmr_id = osTimerNew(timer_task_30mS, osTimerPeriodic, NULL, NULL); @@ -518,7 +518,7 @@ int main(void) osKernelInitialize(); // Create application main thread -#ifdef USE_CMSIS_RTOS2 +#ifndef USE_LEGACY_CMSIS_RTOS main_task_id = osThreadNew(main_task, NULL, &k_main_thread_attr); #else osThreadNew(main_task, NULL, NULL); From 8c0d17598a0c163db11d6e6c9528793509704ab7 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 25 Jan 2021 23:35:46 -0600 Subject: [PATCH 082/617] Update project-generator and add documentation for experimental branch --- README.md | 94 ++++++++++++++++++++++++++++++++++++++++++++++++ requirements.txt | 2 +- 2 files changed, 95 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index d45a54091..3c29b979d 100644 --- a/README.md +++ b/README.md @@ -1,3 +1,97 @@ +# Warning: Experimental branch + +This is is an experimental branch: +- It adds support for the GCC (`gcc_arm`) and ARMC6 (`armclang`) compilers. +- It focuses on `progen` support using `make` and `cmake`. +- It will be frequently rebased. + +## Setup + +DAPLink sources are compiled using `progen` (from [project-generator](https://github.com/project-generator/project_generator)) which can be run on Linux, MacOS and Windows. + +Install the necessary tools listed below. Skip any step where a compatible tool already exists. + +* Install [Python 3](https://www.python.org/downloads/) . Add to PATH. +* Install [Git](https://git-scm.com/downloads) . Add to PATH. +* Install a compiler: + * [GNU Arm Embedded Toolchain](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads) . This compiler will be identified as `gcc_arm`. + * [Arm Compiler 6](https://developer.arm.com/tools-and-software/embedded/arm-compiler) . This compiler will be identified as `armclang`. Only supported on Linux and Windows. + * [Keil MDK](https://developer.arm.com/tools-and-software/embedded/keil-mdk) or [Arm Compiler 5](https://developer.arm.com/tools-and-software/embedded/arm-compiler/downloads/legacy-compilers#arm-compiler-5). This compiler will be identified as `armcc`. Only supported on Linux and Windows. +* Install `make` (tested with [GNU Make](https://www.gnu.org/software/make)). [CMake](https://cmake.org) can alternatively be used in conjunction with different implementations of `make` as well as [ninja](https://ninja-build.org). +* Install virtualenv in your global Python installation eg: `pip install virtualenv`. + +**Step 1.** Initial setup. + +Get the sources and create a virtual environment + +``` +$ git clone https://github.com/ARMmbed/DAPLink +$ cd DAPLink +$ git checkout experimental_compilers +$ virtualenv venv +``` + +## Activate virtual environment +**Step 2.** Activate the virtual environment and update requirements. This is necessary when you open a new shell. **This should be done every time you pull new changes** + +``` +$ venv/Scripts/activate (For Linux) +$ venv/Scripts/activate.bat (For Windows) +(venv) $ pip install -r requirements.txt +``` + +## Build +**This should be done every time you pull new changes** + +You can use the `progen` command-line tool from project-generator or the `tools/progen_compile.py` wrapper tool. + +**Step 4.1.** Using `progen_compile.py` + +``` +(venv) $ python tools/progen_compile.py [-t ] [--clean] [-v] [--parallel] [ [ ...]] +``` + +* `-t `: choose the toolchain to build. The default is `make_gcc_arm`. Other options tested are `make_gcc_arm`, `make_armclang`, `make_armcc`, `cmake_gcc_arm`, `cmake_armclang`, `cmake_armcc`. +* `--clean`: will clear existing compilation products and force recompilation of all files. +* `-v`: will make compilation process more verbose (typically listing all commands with their arguments) +* `--parallel`: enable parallel compilation within a project (projects are compiled sequentially). +* ``: target project to compile (e.g. `stm32f103xb_bl`, `lpc11u35_if`), if none is specified all (140 to 150) projects will be compiled. + +**Step 4.2.** Using `progen` with `make` + +The following command combines generation and compilation: + +``` +(venv) $ progen generate -t make_gcc_arm -p -b +``` + +Alternatively one can separate those task: +``` +(venv) $ progen generate -t make_gcc_arm -p +(venv) $ make -C projectfiles/make_gcc_arm/ [] [VERBOSE=1] +``` +Where: +* ``: target project to compile (e.g. `stm32f103xb_bl`, `lpc11u35_if`). +* ``: build target, can be `all`, `clean` or `help`. +* `VERBOSE=1`: display additional compilation information. + +**Step 4.3.** Using `progen` with `cmake` + +The following command combines generation and compilation: + +``` +(venv) $ progen generate -t cmake_gcc_arm -o generator= -p -b +``` +* ``: use `CMake` generators among the following options: + * `make` (`Unix Makefiles`) + * `mingw-make` (`MinGW Makefiles`) + * `msys-make` (`MSYS Makefiles`, untested) + * `ninja` (`Ninja`) + * `nmake` (`NMake Makefiles`, untested) +* ``: target project to compile (e.g. `stm32f103xb_bl`, `lpc11u35_if`). + +# End of warning + [![DAPLink](/docs/images/daplink-website-logo-link.png)](https://armmbed.github.io/DAPLink/) Arm Mbed DAPLink is an open-source software project that enables programming and debugging application software running on Arm Cortex CPUs. Commonly referred to as interface firmware, DAPLink runs on a secondary MCU that is attached to the SWD or JTAG port of the application MCU. This configuration is found on nearly all development boards. Enumerating as a USB composite device, it creates a bridge between your development computer and the CPU debug access port. DAPLink enables developers with: diff --git a/requirements.txt b/requirements.txt index bcb592519..e110dcd14 100644 --- a/requirements.txt +++ b/requirements.txt @@ -1,4 +1,4 @@ -project_generator==0.10.* +project_generator==0.11.* mbed-ls==1.6.2 pyserial pyOCD==0.28.* From db3c164cd0e3aee5a1c1d21fbeccefbe3030fbeb Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 1 Feb 2021 22:08:13 -0600 Subject: [PATCH 083/617] Update startup and system files for max32625 Use pack-provided gcc version --- .../maxim/max32625/armcc/startup_MAX32625.S | 334 ---------------- .../maxim/max32625/armcc/startup_max32625.S | 364 ++++++++++++++++++ .../maxim/max32625/gcc/startup_MAX32625.S | 347 ----------------- .../maxim/max32625/gcc/startup_max32625.S | 274 +++++++++++++ .../hic_hal/maxim/max32625/system_max32625.c | 48 ++- 5 files changed, 671 insertions(+), 696 deletions(-) delete mode 100755 source/hic_hal/maxim/max32625/armcc/startup_MAX32625.S create mode 100755 source/hic_hal/maxim/max32625/armcc/startup_max32625.S delete mode 100644 source/hic_hal/maxim/max32625/gcc/startup_MAX32625.S create mode 100644 source/hic_hal/maxim/max32625/gcc/startup_max32625.S diff --git a/source/hic_hal/maxim/max32625/armcc/startup_MAX32625.S b/source/hic_hal/maxim/max32625/armcc/startup_MAX32625.S deleted file mode 100755 index f68a64461..000000000 --- a/source/hic_hal/maxim/max32625/armcc/startup_MAX32625.S +++ /dev/null @@ -1,334 +0,0 @@ -;******************************************************************************* -; Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. -; -; Permission is hereby granted, free of charge, to any person obtaining a -; copy of this software and associated documentation files (the "Software"), -; to deal in the Software without restriction, including without limitation -; the rights to use, copy, modify, merge, publish, distribute, sublicense, -; and/or sell copies of the Software, and to permit persons to whom the -; Software is furnished to do so, subject to the following conditions: -; -; The above copyright notice and this permission notice shall be included -; in all copies or substantial portions of the Software. -; -; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS -; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES -; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -; OTHER DEALINGS IN THE SOFTWARE. -; -; Except as contained in this notice, the name of Maxim Integrated -; Products, Inc. shall not be used except as stated in the Maxim Integrated -; Products, Inc. Branding Policy. -; -; The mere transfer of this software does not imply any licenses -; of trade secrets, proprietary technology, copyrights, patents, -; trademarks, maskwork rights, or any other form of intellectual -; property whatsoever. Maxim Integrated Products, Inc. retains all -; ownership rights. -;******************************************************************************* - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT g_board_info -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD DAPLINK_BUILD_KEY ; Reserved - DCD DAPLINK_HIC_ID ; Reserved - DCD DAPLINK_VERSION ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD g_board_info ; Ptr to Board info, family info other target details - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; Maxim 32625 Externals interrupts - DCD CLKMAN_IRQHandler /* 16:01 CLKMAN */ - DCD PWRMAN_IRQHandler /* 17:02 PWRMAN */ - DCD FLC_IRQHandler /* 18:03 Flash Controller */ - DCD RTC0_IRQHandler /* 19:04 RTC INT0 */ - DCD RTC1_IRQHandler /* 20:05 RTC INT1 */ - DCD RTC2_IRQHandler /* 21:06 RTC INT2 */ - DCD RTC3_IRQHandler /* 22:07 RTC INT3 */ - DCD PMU_IRQHandler /* 23:08 PMU */ - DCD USB_IRQHandler /* 24:09 USB */ - DCD AES_IRQHandler /* 25:10 AES */ - DCD MAA_IRQHandler /* 26:11 MAA */ - DCD WDT0_IRQHandler /* 27:12 WATCHDOG0 */ - DCD WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */ - DCD WDT1_IRQHandler /* 29:14 WATCHDOG1 */ - DCD WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */ - DCD GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */ - DCD GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */ - DCD GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */ - DCD GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */ - DCD GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */ - DCD GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */ - DCD GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */ - DCD TMR0_IRQHandler /* 38:23 Timer32-0 */ - DCD TMR16_0_IRQHandler /* 39:24 Timer16-s0 */ - DCD TMR1_IRQHandler /* 40:25 Timer32-1 */ - DCD TMR16_1_IRQHandler /* 41:26 Timer16-s1 */ - DCD TMR2_IRQHandler /* 42:27 Timer32-2 */ - DCD TMR16_2_IRQHandler /* 43:28 Timer16-s2 */ - DCD TMR3_IRQHandler /* 44:29 Timer32-3 */ - DCD TMR16_3_IRQHandler /* 45:30 Timer16-s3 */ - DCD TMR4_IRQHandler /* 46:31 Timer32-4 */ - DCD TMR16_4_IRQHandler /* 47:32 Timer16-s4 */ - DCD TMR5_IRQHandler /* 48:33 Timer32-5 */ - DCD TMR16_5_IRQHandler /* 49:34 Timer16-s5 */ - DCD UART0_IRQHandler /* 50:35 UART0 */ - DCD UART1_IRQHandler /* 51:36 UART1 */ - DCD UART2_IRQHandler /* 52:37 UART0 */ - DCD UART3_IRQHandler /* 53:38 UART1 */ - DCD PT_IRQHandler /* 54:39 PT */ - DCD I2CM0_IRQHandler /* 55:40 I2C Master 0 */ - DCD I2CM1_IRQHandler /* 56:41 I2C Master 1 */ - DCD I2CM2_IRQHandler /* 57:42 I2C Master 2 */ - DCD I2CS_IRQHandler /* 58:43 I2C Slave */ - DCD SPI0_IRQHandler /* 59:44 SPI0 */ - DCD SPI1_IRQHandler /* 60:45 SPI1 */ - DCD SPI2_IRQHandler /* 61:46 SPI2 */ - DCD SPIB_IRQHandler /* 62:47 SPI Bridge */ - DCD OWM_IRQHandler /* 63:48 1-Wire Master */ - DCD AFE_IRQHandler /* 64:49 AFE */ - DCD SPIS_IRQHandler ; 65:50 SPI Slave - DCD GPIO_P7_IRQHandler ; 66:51 GPIO Port 7 - DCD GPIO_P8_IRQHandler ; 67:52 GPIO Port 8 -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT PreInit - IMPORT SystemInit - IMPORT __main - LDR R0, =PreInit - BLX R0 - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP - -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP - -MemManage_Handler PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP - -BusFault_Handler PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP - -UsageFault_Handler PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -DefaultIRQ_Handler PROC - EXPORT CLKMAN_IRQHandler [WEAK] - EXPORT PWRMAN_IRQHandler [WEAK] - EXPORT FLC_IRQHandler [WEAK] - EXPORT RTC0_IRQHandler [WEAK] - EXPORT RTC1_IRQHandler [WEAK] - EXPORT RTC2_IRQHandler [WEAK] - EXPORT RTC3_IRQHandler [WEAK] - EXPORT PMU_IRQHandler [WEAK] - EXPORT USB_IRQHandler [WEAK] - EXPORT AES_IRQHandler [WEAK] - EXPORT MAA_IRQHandler [WEAK] - EXPORT WDT0_IRQHandler [WEAK] - EXPORT WDT0_P_IRQHandler [WEAK] - EXPORT WDT1_IRQHandler [WEAK] - EXPORT WDT1_P_IRQHandler [WEAK] - EXPORT GPIO_P0_IRQHandler [WEAK] - EXPORT GPIO_P1_IRQHandler [WEAK] - EXPORT GPIO_P2_IRQHandler [WEAK] - EXPORT GPIO_P3_IRQHandler [WEAK] - EXPORT GPIO_P4_IRQHandler [WEAK] - EXPORT GPIO_P5_IRQHandler [WEAK] - EXPORT GPIO_P6_IRQHandler [WEAK] - EXPORT TMR0_IRQHandler [WEAK] - EXPORT TMR16_0_IRQHandler [WEAK] - EXPORT TMR1_IRQHandler [WEAK] - EXPORT TMR16_1_IRQHandler [WEAK] - EXPORT TMR2_IRQHandler [WEAK] - EXPORT TMR16_2_IRQHandler [WEAK] - EXPORT TMR3_IRQHandler [WEAK] - EXPORT TMR16_3_IRQHandler [WEAK] - EXPORT TMR4_IRQHandler [WEAK] - EXPORT TMR16_4_IRQHandler [WEAK] - EXPORT TMR5_IRQHandler [WEAK] - EXPORT TMR16_5_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT PT_IRQHandler [WEAK] - EXPORT I2CM0_IRQHandler [WEAK] - EXPORT I2CM1_IRQHandler [WEAK] - EXPORT I2CM2_IRQHandler [WEAK] - EXPORT I2CS_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT SPIB_IRQHandler [WEAK] - EXPORT OWM_IRQHandler [WEAK] - EXPORT AFE_IRQHandler [WEAK] - EXPORT SPIS_IRQHandler [WEAK] - EXPORT GPIO_P7_IRQHandler [WEAK] - EXPORT GPIO_P8_IRQHandler [WEAK] -CLKMAN_IRQHandler -PWRMAN_IRQHandler -FLC_IRQHandler -RTC0_IRQHandler -RTC1_IRQHandler -RTC2_IRQHandler -RTC3_IRQHandler -PMU_IRQHandler -USB_IRQHandler -AES_IRQHandler -MAA_IRQHandler -WDT0_IRQHandler -WDT0_P_IRQHandler -WDT1_IRQHandler -WDT1_P_IRQHandler -GPIO_P0_IRQHandler -GPIO_P1_IRQHandler -GPIO_P2_IRQHandler -GPIO_P3_IRQHandler -GPIO_P4_IRQHandler -GPIO_P5_IRQHandler -GPIO_P6_IRQHandler -TMR0_IRQHandler -TMR16_0_IRQHandler -TMR1_IRQHandler -TMR16_1_IRQHandler -TMR2_IRQHandler -TMR16_2_IRQHandler -TMR3_IRQHandler -TMR16_3_IRQHandler -TMR4_IRQHandler -TMR16_4_IRQHandler -TMR5_IRQHandler -TMR16_5_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -UART3_IRQHandler -PT_IRQHandler -I2CM0_IRQHandler -I2CM1_IRQHandler -I2CM2_IRQHandler -I2CS_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -SPIB_IRQHandler -OWM_IRQHandler -AFE_IRQHandler -SPIS_IRQHandler -GPIO_P7_IRQHandler -GPIO_P8_IRQHandler - - B . - ENDP - ALIGN - - ; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, = (Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - END diff --git a/source/hic_hal/maxim/max32625/armcc/startup_max32625.S b/source/hic_hal/maxim/max32625/armcc/startup_max32625.S new file mode 100755 index 000000000..e1e006033 --- /dev/null +++ b/source/hic_hal/maxim/max32625/armcc/startup_max32625.S @@ -0,0 +1,364 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved. + ; + ; Permission is hereby granted, free of charge, to any person obtaining a + ; copy of this software and associated documentation files (the "Software"), + ; to deal in the Software without restriction, including without limitation + ; the rights to use, copy, modify, merge, publish, distribute, sublicense, + ; and/or sell copies of the Software, and to permit persons to whom the + ; Software is furnished to do so, subject to the following conditions: + ; + ; The above copyright notice and this permission notice shall be included + ; in all copies or substantial portions of the Software. + ; + ; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + ; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + ; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + ; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + ; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + ; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + ; OTHER DEALINGS IN THE SOFTWARE. + ; + ; Except as contained in this notice, the name of Maxim Integrated + ; Products, Inc. shall not be used except as stated in the Maxim Integrated + ; Products, Inc. Branding Policy. + ; + ; The mere transfer of this software does not imply any licenses + ; of trade secrets, proprietary technology, copyrights, patents, + ; trademarks, maskwork rights, or any other form of intellectual + ; property whatsoever. Maxim Integrated Products, Inc. retains all + ; ownership rights. + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +#include "daplink_defaults.h" + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU DAPLINK_STACK_SIZE + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp ; ARMCC: name is set to work with MicroLib + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU DAPLINK_HEAP_SIZE + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + EXPORT __isr_vector + IMPORT g_board_info + + ; Core Level - CM4 ; Most names are to help the FreeRTOS port. +__isr_vector +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD DAPLINK_BUILD_KEY ; Build type - BL/IF + DCD DAPLINK_HIC_ID ; Compatibility + DCD DAPLINK_VERSION ; Version + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD g_board_info ; Ptr to Board info, family info other target details + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Maxim 3263X Externals interrupts + DCD CLKMAN_IRQHandler ; 16:00 CLKMAN + DCD PWRMAN_IRQHandler ; 17:01 PWRMAN + DCD FLC_IRQHandler ; 18:02 Flash Controller + DCD RTC0_IRQHandler ; 19:03 RTC INT0 + DCD RTC1_IRQHandler ; 20:04 RTC INT1 + DCD RTC2_IRQHandler ; 21:05 RTC INT2 + DCD RTC3_IRQHandler ; 22:06 RTC INT3 + DCD PMU_IRQHandler ; 23:07 PMU + DCD USB_IRQHandler ; 24:08 USB + DCD AES_IRQHandler ; 25:09 AES + DCD MAA_IRQHandler ; 26:10 MAA + DCD WDT0_IRQHandler ; 27:11 WATCHDOG0 + DCD WDT0_P_IRQHandler ; 28:12 WATCHDOG0 PRE-WINDOW + DCD WDT1_IRQHandler ; 29:13 WATCHDOG1 + DCD WDT1_P_IRQHandler ; 30:14 WATCHDOG1 PRE-WINDOW + DCD GPIO_P0_IRQHandler ; 31:15 GPIO Port 0 + DCD GPIO_P1_IRQHandler ; 32:16 GPIO Port 1 + DCD GPIO_P2_IRQHandler ; 33:17 GPIO Port 2 + DCD GPIO_P3_IRQHandler ; 34:18 GPIO Port 3 + DCD GPIO_P4_IRQHandler ; 35:19 GPIO Port 4 + DCD GPIO_P5_IRQHandler ; 36:20 GPIO Port 5 + DCD GPIO_P6_IRQHandler ; 37:21 GPIO Port 6 + DCD TMR0_IRQHandler ; 38:22 Timer32-0 + DCD TMR16_0_IRQHandler ; 39:23 Timer16-s0 + DCD TMR1_IRQHandler ; 40:24 Timer32-1 + DCD TMR16_1_IRQHandler ; 41:25 Timer16-s1 + DCD TMR2_IRQHandler ; 42:26 Timer32-2 + DCD TMR16_2_IRQHandler ; 43:27 Timer16-s2 + DCD TMR3_IRQHandler ; 44:28 Timer32-3 + DCD TMR16_3_IRQHandler ; 45:29 Timer16-s3 + DCD TMR4_IRQHandler ; 46:30 Timer32-4 + DCD TMR16_4_IRQHandler ; 47:31 Timer16-s4 + DCD TMR5_IRQHandler ; 48:32 Timer32-5 + DCD TMR16_5_IRQHandler ; 49:33 Timer16-s5 + DCD UART0_IRQHandler ; 50:34 UART0 + DCD UART1_IRQHandler ; 51:35 UART1 + DCD UART2_IRQHandler ; 52:36 UART2 + DCD UART3_IRQHandler ; 53:37 UART3 + DCD PT_IRQHandler ; 54:38 PT + DCD I2CM0_IRQHandler ; 55:39 I2C Master 0 + DCD I2CM1_IRQHandler ; 56:40 I2C Master 1 + DCD I2CM2_IRQHandler ; 57:41 I2C Master 2 + DCD I2CS_IRQHandler ; 58:42 I2C Slave + DCD SPIM0_IRQHandler ; 59:43 SPIM0 + DCD SPIM1_IRQHandler ; 60:44 SPIM1 + DCD SPIM2_IRQHandler ; 61:45 SPIM2 + DCD SPIB_IRQHandler ; 62:46 SPI Bridge + DCD OWM_IRQHandler ; 63:47 OWM Master + DCD AFE_IRQHandler ; 64:48 AFE + DCD SPIS_IRQHandler ; 65:49 SPI Slave + DCD GPIO_P7_IRQHandler ; 66:50 GPIO Port 7 + DCD GPIO_P8_IRQHandler ; 67:51 GPIO Port 8 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT PreInit + IMPORT SystemInit + IMPORT __main + + LDR R0, =PreInit + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 +__SPIN + WFI + BL __SPIN + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B NMI_Handler + ENDP + +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler\ + PROC + ; MAX32625 Interrupts + EXPORT CLKMAN_IRQHandler [WEAK] ; 16:00 CLKMAN + EXPORT PWRMAN_IRQHandler [WEAK] ; 17:01 PWRMAN + EXPORT FLC_IRQHandler [WEAK] ; 18:02 Flash Controller + EXPORT RTC0_IRQHandler [WEAK] ; 19:03 RTC INT0 + EXPORT RTC1_IRQHandler [WEAK] ; 20:04 RTC INT1 + EXPORT RTC2_IRQHandler [WEAK] ; 21:05 RTC INT2 + EXPORT RTC3_IRQHandler [WEAK] ; 22:06 RTC INT3 + EXPORT PMU_IRQHandler [WEAK] ; 23:07 PMU + EXPORT USB_IRQHandler [WEAK] ; 24:08 USB + EXPORT AES_IRQHandler [WEAK] ; 25:09 AES + EXPORT MAA_IRQHandler [WEAK] ; 26:10 MAA + EXPORT WDT0_IRQHandler [WEAK] ; 27:11 WATCHDOG0 + EXPORT WDT0_P_IRQHandler [WEAK] ; 28:12 WATCHDOG0 PRE-WINDOW + EXPORT WDT1_IRQHandler [WEAK] ; 29:13 WATCHDOG1 + EXPORT WDT1_P_IRQHandler [WEAK] ; 30:14 WATCHDOG1 PRE-WINDOW + EXPORT GPIO_P0_IRQHandler [WEAK] ; 31:15 GPIO Port 0 + EXPORT GPIO_P1_IRQHandler [WEAK] ; 32:16 GPIO Port 1 + EXPORT GPIO_P2_IRQHandler [WEAK] ; 33:17 GPIO Port 2 + EXPORT GPIO_P3_IRQHandler [WEAK] ; 34:18 GPIO Port 3 + EXPORT GPIO_P4_IRQHandler [WEAK] ; 35:19 GPIO Port 4 + EXPORT GPIO_P5_IRQHandler [WEAK] ; 36:20 GPIO Port 5 + EXPORT GPIO_P6_IRQHandler [WEAK] ; 37:21 GPIO Port 6 + EXPORT TMR0_IRQHandler [WEAK] ; 38:22 Timer32-0 + EXPORT TMR16_0_IRQHandler [WEAK] ; 39:23 Timer16-s0 + EXPORT TMR1_IRQHandler [WEAK] ; 40:24 Timer32-1 + EXPORT TMR16_1_IRQHandler [WEAK] ; 41:25 Timer16-s1 + EXPORT TMR2_IRQHandler [WEAK] ; 42:26 Timer32-2 + EXPORT TMR16_2_IRQHandler [WEAK] ; 43:27 Timer16-s2 + EXPORT TMR3_IRQHandler [WEAK] ; 44:28 Timer32-3 + EXPORT TMR16_3_IRQHandler [WEAK] ; 45:29 Timer16-s3 + EXPORT TMR4_IRQHandler [WEAK] ; 46:30 Timer32-4 + EXPORT TMR16_4_IRQHandler [WEAK] ; 47:31 Timer16-s4 + EXPORT TMR5_IRQHandler [WEAK] ; 48:32 Timer32-5 + EXPORT TMR16_5_IRQHandler [WEAK] ; 49:33 Timer16-s5 + EXPORT UART0_IRQHandler [WEAK] ; 50:34 UART0 + EXPORT UART1_IRQHandler [WEAK] ; 51:35 UART1 + EXPORT UART2_IRQHandler [WEAK] ; 52:36 UART2 + EXPORT UART3_IRQHandler [WEAK] ; 53:37 UART3 + EXPORT PT_IRQHandler [WEAK] ; 54:38 PT + EXPORT I2CM0_IRQHandler [WEAK] ; 55:39 I2C Master 0 + EXPORT I2CM1_IRQHandler [WEAK] ; 56:40 I2C Master 1 + EXPORT I2CM2_IRQHandler [WEAK] ; 57:41 I2C Master 2 + EXPORT I2CS_IRQHandler [WEAK] ; 58:42 I2C Slave + EXPORT SPIM0_IRQHandler [WEAK] ; 59:43 SPIM0 + EXPORT SPIM1_IRQHandler [WEAK] ; 60:44 SPIM1 + EXPORT SPIM2_IRQHandler [WEAK] ; 61:45 SPIM2 + EXPORT SPIB_IRQHandler [WEAK] ; 62:46 SPI Bridge + EXPORT OWM_IRQHandler [WEAK] ; 63:47 SPI Bridge + EXPORT AFE_IRQHandler [WEAK] ; 64:48 AFE + EXPORT SPIS_IRQHandler [WEAK] ; 65:49 SPI Slave + EXPORT GPIO_P7_IRQHandler [WEAK] ; 66:50 GPIO Port 7 + EXPORT GPIO_P8_IRQHandler [WEAK] ; 67:51 GPIO Port 8 + +CLKMAN_IRQHandler +PWRMAN_IRQHandler +FLC_IRQHandler +RTC0_IRQHandler +RTC1_IRQHandler +RTC2_IRQHandler +RTC3_IRQHandler +PMU_IRQHandler +USB_IRQHandler +AES_IRQHandler +MAA_IRQHandler +WDT0_IRQHandler +WDT0_P_IRQHandler +WDT1_IRQHandler +WDT1_P_IRQHandler +GPIO_P0_IRQHandler +GPIO_P1_IRQHandler +GPIO_P2_IRQHandler +GPIO_P3_IRQHandler +GPIO_P4_IRQHandler +GPIO_P5_IRQHandler +GPIO_P6_IRQHandler +TMR0_IRQHandler +TMR16_0_IRQHandler +TMR1_IRQHandler +TMR16_1_IRQHandler +TMR2_IRQHandler +TMR16_2_IRQHandler +TMR3_IRQHandler +TMR16_3_IRQHandler +TMR4_IRQHandler +TMR16_4_IRQHandler +TMR5_IRQHandler +TMR16_5_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +PT_IRQHandler +I2CM0_IRQHandler +I2CM1_IRQHandler +I2CM2_IRQHandler +I2CS_IRQHandler +SPIM0_IRQHandler +SPIM1_IRQHandler +SPIM2_IRQHandler +SPIB_IRQHandler +OWM_IRQHandler +AFE_IRQHandler +SPIS_IRQHandler +GPIO_P7_IRQHandler +GPIO_P8_IRQHandler + + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap\ + PROC + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END + +;;;;;;;;;;;;;;;;;;;;;;;;; +;; End of file. +;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/source/hic_hal/maxim/max32625/gcc/startup_MAX32625.S b/source/hic_hal/maxim/max32625/gcc/startup_MAX32625.S deleted file mode 100644 index 6c672c176..000000000 --- a/source/hic_hal/maxim/max32625/gcc/startup_MAX32625.S +++ /dev/null @@ -1,347 +0,0 @@ -/** - * @file startup_MK20D5.s - * @brief - * - * DAPLink Interface Firmware - * Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc. - * Copyright 2016 - 2017 NXP - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - .syntax unified - .arch armv7-m - - .section .isr_vector, "a" - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long MemManage_Handler /* MPU Fault Handler*/ - .long BusFault_Handler /* Bus Fault Handler*/ - .long UsageFault_Handler /* Usage Fault Handler*/ - .long 0 /* Reserved*/ - .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ - .long DAPLINK_HIC_ID /* Compatibility*/ - .long DAPLINK_VERSION /* Version*/ - .long SVC_Handler /* SVCall Handler*/ - .long DebugMon_Handler /* Debug Monitor Handler*/ - .long g_board_info /* Ptr to Board info, family info other target details*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ - - /* External Interrupts*/ - .long CLKMAN_IRQHandler /* 16:01 CLKMAN */ - .long PWRMAN_IRQHandler /* 17:02 PWRMAN */ - .long FLC_IRQHandler /* 18:03 Flash Controller */ - .long RTC0_IRQHandler /* 19:04 RTC INT0 */ - .long RTC1_IRQHandler /* 20:05 RTC INT1 */ - .long RTC2_IRQHandler /* 21:06 RTC INT2 */ - .long RTC3_IRQHandler /* 22:07 RTC INT3 */ - .long PMU_IRQHandler /* 23:08 PMU */ - .long USB_IRQHandler /* 24:09 USB */ - .long AES_IRQHandler /* 25:10 AES */ - .long MAA_IRQHandler /* 26:11 MAA */ - .long WDT0_IRQHandler /* 27:12 WATCHDOG0 */ - .long WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */ - .long WDT1_IRQHandler /* 29:14 WATCHDOG1 */ - .long WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */ - .long GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */ - .long GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */ - .long GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */ - .long GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */ - .long GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */ - .long GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */ - .long GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */ - .long TMR0_IRQHandler /* 38:23 Timer32-0 */ - .long TMR16_0_IRQHandler /* 39:24 Timer16-s0 */ - .long TMR1_IRQHandler /* 40:25 Timer32-1 */ - .long TMR16_1_IRQHandler /* 41:26 Timer16-s1 */ - .long TMR2_IRQHandler /* 42:27 Timer32-2 */ - .long TMR16_2_IRQHandler /* 43:28 Timer16-s2 */ - .long TMR3_IRQHandler /* 44:29 Timer32-3 */ - .long TMR16_3_IRQHandler /* 45:30 Timer16-s3 */ - .long TMR4_IRQHandler /* 46:31 Timer32-4 */ - .long TMR16_4_IRQHandler /* 47:32 Timer16-s4 */ - .long TMR5_IRQHandler /* 48:33 Timer32-5 */ - .long TMR16_5_IRQHandler /* 49:34 Timer16-s5 */ - .long UART0_IRQHandler /* 50:35 UART0 */ - .long UART1_IRQHandler /* 51:36 UART1 */ - .long UART2_IRQHandler /* 52:37 UART0 */ - .long UART3_IRQHandler /* 53:38 UART1 */ - .long PT_IRQHandler /* 54:39 PT */ - .long I2CM0_IRQHandler /* 55:40 I2C Master 0 */ - .long I2CM1_IRQHandler /* 56:41 I2C Master 1 */ - .long I2CM2_IRQHandler /* 57:42 I2C Master 2 */ - .long I2CS_IRQHandler /* 58:43 I2C Slave */ - .long SPI0_IRQHandler /* 59:44 SPI0 */ - .long SPI1_IRQHandler /* 60:45 SPI1 */ - .long SPI2_IRQHandler /* 61:46 SPI2 */ - .long SPIB_IRQHandler /* 62:47 SPI Bridge */ - .long OWM_IRQHandler /* 63:48 1-Wire Master */ - .long AFE_IRQHandler /* 64:49 AFE */ - .long SPIS_IRQHandler /* 65:50 SPI Slave */ - .long GPIO_P7_IRQHandler /* 66:51 GPIO Port 7 */ - .long GPIO_P8_IRQHandler /* 67:52 GPIO Port 8 */ - - .size __isr_vector, . - __isr_vector - - .text - .thumb - -/* Reset Handler */ - - .thumb_func - .align 2 - .globl Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - cpsid i /* Mask interrupts */ - .equ VTOR, 0xE000ED08 - ldr r0, =VTOR - ldr r1, =__isr_vector - str r1, [r0] - ldr r2, [r1] - msr msp, r2 -#ifndef __NO_SYSTEM_INIT - ldr r0,=SystemInit - blx r0 -#endif -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -#if 1 -/* Here are two copies of loop implemenations. First one favors code size - * and the second one favors performance. Default uses the first one. - * Change to "#if 0" to use the second one */ -.LC0: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .LC0 -#else - subs r3, r2 - ble .LC1 -.LC0: - subs r3, #4 - ldr r0, [r1, r3] - str r0, [r2, r3] - bgt .LC0 -.LC1: -#endif - -#ifdef __STARTUP_CLEAR_BSS -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * Loop to zero out BSS section, which uses following symbols - * in linker script: - * __bss_start__: start of BSS section. Must align to 4 - * __bss_end__: end of BSS section. Must align to 4 - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.LC2: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC2 -#endif /* __STARTUP_CLEAR_BSS */ - - cpsie i /* Unmask interrupts */ -#ifndef __START -#define __START _start -#endif -#ifndef __ATOLLIC__ - ldr r0,=__START - blx r0 -#else - ldr r0,=__libc_init_array - blx r0 - ldr r0,=main - bx r0 -#endif - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak MemManage_Handler - .type MemManage_Handler, %function -MemManage_Handler: - ldr r0,=MemManage_Handler - bx r0 - .size MemManage_Handler, . - MemManage_Handler - - .align 1 - .thumb_func - .weak BusFault_Handler - .type BusFault_Handler, %function -BusFault_Handler: - ldr r0,=BusFault_Handler - bx r0 - .size BusFault_Handler, . - BusFault_Handler - - .align 1 - .thumb_func - .weak UsageFault_Handler - .type UsageFault_Handler, %function -UsageFault_Handler: - ldr r0,=UsageFault_Handler - bx r0 - .size UsageFault_Handler, . - UsageFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak DebugMon_Handler - .type DebugMon_Handler, %function -DebugMon_Handler: - ldr r0,=DebugMon_Handler - bx r0 - .size DebugMon_Handler, . - DebugMon_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm - -/* Exception Handlers */ - def_irq_handler CLKMAN_IRQHandler /* 16:01 CLKMAN */ - def_irq_handler PWRMAN_IRQHandler /* 17:02 PWRMAN */ - def_irq_handler FLC_IRQHandler /* 18:03 Flash Controller */ - def_irq_handler RTC0_IRQHandler /* 19:04 RTC INT0 */ - def_irq_handler RTC1_IRQHandler /* 20:05 RTC INT1 */ - def_irq_handler RTC2_IRQHandler /* 21:06 RTC INT2 */ - def_irq_handler RTC3_IRQHandler /* 22:07 RTC INT3 */ - def_irq_handler PMU_IRQHandler /* 23:08 PMU */ - def_irq_handler USB_IRQHandler /* 24:09 USB */ - def_irq_handler AES_IRQHandler /* 25:10 AES */ - def_irq_handler MAA_IRQHandler /* 26:11 MAA */ - def_irq_handler WDT0_IRQHandler /* 27:12 WATCHDOG0 */ - def_irq_handler WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */ - def_irq_handler WDT1_IRQHandler /* 29:14 WATCHDOG1 */ - def_irq_handler WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */ - def_irq_handler GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */ - def_irq_handler GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */ - def_irq_handler GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */ - def_irq_handler GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */ - def_irq_handler GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */ - def_irq_handler GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */ - def_irq_handler GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */ - def_irq_handler TMR0_IRQHandler /* 38:23 Timer32-0 */ - def_irq_handler TMR16_0_IRQHandler /* 39:24 Timer16-s0 */ - def_irq_handler TMR1_IRQHandler /* 40:25 Timer32-1 */ - def_irq_handler TMR16_1_IRQHandler /* 41:26 Timer16-s1 */ - def_irq_handler TMR2_IRQHandler /* 42:27 Timer32-2 */ - def_irq_handler TMR16_2_IRQHandler /* 43:28 Timer16-s2 */ - def_irq_handler TMR3_IRQHandler /* 44:29 Timer32-3 */ - def_irq_handler TMR16_3_IRQHandler /* 45:30 Timer16-s3 */ - def_irq_handler TMR4_IRQHandler /* 46:31 Timer32-4 */ - def_irq_handler TMR16_4_IRQHandler /* 47:32 Timer16-s4 */ - def_irq_handler TMR5_IRQHandler /* 48:33 Timer32-5 */ - def_irq_handler TMR16_5_IRQHandler /* 49:34 Timer16-s5 */ - def_irq_handler UART0_IRQHandler /* 50:35 UART0 */ - def_irq_handler UART1_IRQHandler /* 51:36 UART1 */ - def_irq_handler UART2_IRQHandler /* 52:37 UART0 */ - def_irq_handler UART3_IRQHandler /* 53:38 UART1 */ - def_irq_handler PT_IRQHandler /* 54:39 PT */ - def_irq_handler I2CM0_IRQHandler /* 55:40 I2C Master 0 */ - def_irq_handler I2CM1_IRQHandler /* 56:41 I2C Master 1 */ - def_irq_handler I2CM2_IRQHandler /* 57:42 I2C Master 2 */ - def_irq_handler I2CS_IRQHandler /* 58:43 I2C Slave */ - def_irq_handler SPI0_IRQHandler /* 59:44 SPI0 */ - def_irq_handler SPI1_IRQHandler /* 60:45 SPI1 */ - def_irq_handler SPI2_IRQHandler /* 61:46 SPI2 */ - def_irq_handler SPIB_IRQHandler /* 62:47 SPI Bridge */ - def_irq_handler OWM_IRQHandler /* 63:48 1-Wire Master */ - def_irq_handler AFE_IRQHandler /* 64:49 AFE */ - def_irq_handler SPIS_IRQHandler /* 65:50 SPI Slave */ - def_irq_handler GPIO_P7_IRQHandler /* 66:51 GPIO Port 7 */ - def_irq_handler GPIO_P8_IRQHandler /* 67:52 GPIO Port 8 */ - - .end diff --git a/source/hic_hal/maxim/max32625/gcc/startup_max32625.S b/source/hic_hal/maxim/max32625/gcc/startup_max32625.S new file mode 100644 index 000000000..9df241d1d --- /dev/null +++ b/source/hic_hal/maxim/max32625/gcc/startup_max32625.S @@ -0,0 +1,274 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long DAPLINK_BUILD_KEY /* Build type - BL/IF */ + .long DAPLINK_HIC_ID /* Compatibility */ + .long DAPLINK_VERSION /* Version */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long g_board_info /* Ptr to Board info, family info other target details */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* MAX32625 Interrupts */ + .long CLKMAN_IRQHandler /* 16:01 CLKMAN */ + .long PWRMAN_IRQHandler /* 17:02 PWRMAN */ + .long FLC_IRQHandler /* 18:03 Flash Controller */ + .long RTC0_IRQHandler /* 19:04 RTC INT0 */ + .long RTC1_IRQHandler /* 20:05 RTC INT1 */ + .long RTC2_IRQHandler /* 21:06 RTC INT2 */ + .long RTC3_IRQHandler /* 22:07 RTC INT3 */ + .long PMU_IRQHandler /* 23:08 PMU */ + .long USB_IRQHandler /* 24:09 USB */ + .long AES_IRQHandler /* 25:10 AES */ + .long MAA_IRQHandler /* 26:11 MAA */ + .long WDT0_IRQHandler /* 27:12 WATCHDOG0 */ + .long WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */ + .long WDT1_IRQHandler /* 29:14 WATCHDOG1 */ + .long WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */ + .long GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */ + .long GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */ + .long GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */ + .long GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */ + .long GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */ + .long GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */ + .long GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */ + .long TMR0_IRQHandler /* 38:23 Timer32-0 */ + .long TMR16_0_IRQHandler /* 39:24 Timer16-s0 */ + .long TMR1_IRQHandler /* 40:25 Timer32-1 */ + .long TMR16_1_IRQHandler /* 41:26 Timer16-s1 */ + .long TMR2_IRQHandler /* 42:27 Timer32-2 */ + .long TMR16_2_IRQHandler /* 43:28 Timer16-s2 */ + .long TMR3_IRQHandler /* 44:29 Timer32-3 */ + .long TMR16_3_IRQHandler /* 45:30 Timer16-s3 */ + .long TMR4_IRQHandler /* 46:31 Timer32-4 */ + .long TMR16_4_IRQHandler /* 47:32 Timer16-s4 */ + .long TMR5_IRQHandler /* 48:33 Timer32-5 */ + .long TMR16_5_IRQHandler /* 49:34 Timer16-s5 */ + .long UART0_IRQHandler /* 50:35 UART0 */ + .long UART1_IRQHandler /* 51:36 UART1 */ + .long UART2_IRQHandler /* 52:37 UART2 */ + .long UART3_IRQHandler /* 53:38 UART3 */ + .long PT_IRQHandler /* 54:39 PT */ + .long I2CM0_IRQHandler /* 55:40 I2C Master 0 */ + .long I2CM1_IRQHandler /* 56:41 I2C Master 1 */ + .long I2CM2_IRQHandler /* 57:42 I2C Master 2 */ + .long I2CS_IRQHandler /* 58:43 I2C Slave */ + .long SPIM0_IRQHandler /* 59:44 SPIM0 */ + .long SPIM1_IRQHandler /* 60:45 SPIM1 */ + .long SPIM2_IRQHandler /* 61:46 SPIM2 */ + .long SPIB_IRQHandler /* 62:47 SPI Bridge */ + .long OWM_IRQHandler /* 63:48 1-Wire Master */ + .long AFE_IRQHandler /* 64:49 AFE */ + .long SPIS_IRQHandler /* 65:50 SPI Slave */ + .long GPIO_P7_IRQHandler /* 66:51 GPIO Port 7 */ + .long GPIO_P8_IRQHandler /* 67:52 GPIO Port 8 */ + + .size __isr_vector, . - __isr_vector + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =__StackTop + mov sp, r0 + + ldr r0, =PreInit + blx r0 + cbnz r0, .SKIPRAMINIT + +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + +.SKIPRAMINIT: + + ldr r0, =SystemInit + blx r0 + + ldr r0, =_start + blx r0 + +.SPIN: + /* Enter LP2 if main() ever returns. */ + wfi + bl .SPIN + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + def_irq_handler Default_Handler + + /* MAX32625 Interrupts */ + def_irq_handler CLKMAN_IRQHandler /* 16:01 CLKMAN */ + def_irq_handler PWRMAN_IRQHandler /* 17:02 PWRMAN */ + def_irq_handler FLC_IRQHandler /* 18:03 Flash Controller */ + def_irq_handler RTC0_IRQHandler /* 19:04 RTC INT0 */ + def_irq_handler RTC1_IRQHandler /* 20:05 RTC INT1 */ + def_irq_handler RTC2_IRQHandler /* 21:06 RTC INT2 */ + def_irq_handler RTC3_IRQHandler /* 22:07 RTC INT3 */ + def_irq_handler PMU_IRQHandler /* 23:08 PMU */ + def_irq_handler USB_IRQHandler /* 24:09 USB */ + def_irq_handler AES_IRQHandler /* 25:10 AES */ + def_irq_handler MAA_IRQHandler /* 26:11 MAA */ + def_irq_handler WDT0_IRQHandler /* 27:12 WATCHDOG0 */ + def_irq_handler WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */ + def_irq_handler WDT1_IRQHandler /* 29:14 WATCHDOG1 */ + def_irq_handler WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */ + def_irq_handler GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */ + def_irq_handler GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */ + def_irq_handler GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */ + def_irq_handler GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */ + def_irq_handler GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */ + def_irq_handler GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */ + def_irq_handler GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */ + def_irq_handler TMR0_IRQHandler /* 38:23 Timer32-0 */ + def_irq_handler TMR16_0_IRQHandler /* 39:24 Timer16-s0 */ + def_irq_handler TMR1_IRQHandler /* 40:25 Timer32-1 */ + def_irq_handler TMR16_1_IRQHandler /* 41:26 Timer16-s1 */ + def_irq_handler TMR2_IRQHandler /* 42:27 Timer32-2 */ + def_irq_handler TMR16_2_IRQHandler /* 43:28 Timer16-s2 */ + def_irq_handler TMR3_IRQHandler /* 44:29 Timer32-3 */ + def_irq_handler TMR16_3_IRQHandler /* 45:30 Timer16-s3 */ + def_irq_handler TMR4_IRQHandler /* 46:31 Timer32-4 */ + def_irq_handler TMR16_4_IRQHandler /* 47:32 Timer16-s4 */ + def_irq_handler TMR5_IRQHandler /* 48:33 Timer32-5 */ + def_irq_handler TMR16_5_IRQHandler /* 49:34 Timer16-s5 */ + def_irq_handler PT_IRQHandler /* 50:35 PT */ + def_irq_handler UART0_IRQHandler /* 51:36 UART0 */ + def_irq_handler UART1_IRQHandler /* 52:37 UART1 */ + def_irq_handler UART2_IRQHandler /* 53:38 UART0 */ + def_irq_handler UART3_IRQHandler /* 54:39 UART1 */ + def_irq_handler I2CM0_IRQHandler /* 55:40 I2C Master 0 */ + def_irq_handler I2CM1_IRQHandler /* 56:41 I2C Master 1 */ + def_irq_handler I2CM2_IRQHandler /* 57:42 I2C Master 2 */ + def_irq_handler I2CS_IRQHandler /* 58:43 I2C Slave */ + def_irq_handler SPIM0_IRQHandler /* 59:44 SPIM0 */ + def_irq_handler SPIM1_IRQHandler /* 60:45 SPIM1 */ + def_irq_handler SPIM2_IRQHandler /* 61:46 SPIM2 */ + def_irq_handler SPIB_IRQHandler /* 62:47 SPI Bridge */ + def_irq_handler OWM_IRQHandler /* 63:48 1-Wire Master */ + def_irq_handler AFE_IRQHandler /* 64:49 AFE */ + def_irq_handler SPIS_IRQHandler /* 65:50 SPI Slave */ + def_irq_handler GPIO_P7_IRQHandler /* 66:51 GPIO Port 7 */ + def_irq_handler GPIO_P8_IRQHandler /* 67:52 GPIO Port 8 */ + .end diff --git a/source/hic_hal/maxim/max32625/system_max32625.c b/source/hic_hal/maxim/max32625/system_max32625.c index 43c7e322d..1657a0f21 100755 --- a/source/hic_hal/maxim/max32625/system_max32625.c +++ b/source/hic_hal/maxim/max32625/system_max32625.c @@ -52,18 +52,17 @@ #define LP0_POST_HOOK #endif -/* -* Note: When compiling on ARM Keil Toolchain only. -* If the SystemCoreClock is left uninitialized, post Scatter load -* the clock will default to system reset value(48MHz) -*/ -uint32_t SystemCoreClock = RO_FREQ; +extern void (* const __isr_vector[])(void); +uint32_t SystemCoreClock = RO_FREQ/2; void SystemCoreClockUpdate(void) { - if (MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN) { +#ifdef EMULATOR + SystemCoreClock = RO_FREQ; +#else /* real hardware */ + if(MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN) { /* 4 MHz source */ - if (MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RC_DIV) { + if(MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RC_DIV) { SystemCoreClock = (4000000 / (0x1 << ((MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RC_DIV) >> MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS))); } else { @@ -71,13 +70,14 @@ void SystemCoreClockUpdate(void) } } else { /* 96 MHz source */ - if (MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RO_DIV) { + if(MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RO_DIV) { SystemCoreClock = (RO_FREQ / (0x1 << ((MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RO_DIV) >> MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS))); } else { SystemCoreClock = RO_FREQ; } } +#endif } void CLKMAN_TrimRO(void) @@ -174,11 +174,6 @@ __weak int PreInit(void) return 0; } -/* -* Note: When compiling on ARM Keil Toolchain only. -* If any global variable is modified in this function, post Scatter load -* it will default to its original value(E.g.: SystemCoreClock) -*/ /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -194,6 +189,15 @@ __weak int Board_Init(void) */ __weak void SystemInit(void) { + /* Configure the interrupt controller to use the application vector table in */ + /* the application space */ +#if defined ( __GNUC__ ) + /* IAR sets the VTOR pointer prior to SystemInit and causes stack corruption to change it here. */ + __disable_irq(); /* Disable interrupts */ + SCB->VTOR = (uint32_t)__isr_vector; /* set the Vector Table to point at our ISR table */ + __DSB(); /* bus sync */ + __enable_irq(); /* enable interrupts */ +#endif /* __GNUC__ */ /* Copy trim information from shadow registers into power manager registers */ /* NOTE: Checks have been added to prevent bad/missing trim values from being loaded */ if ((MXC_FLC->ctrl & MXC_F_FLC_CTRL_INFO_BLOCK_VALID) && @@ -247,7 +251,6 @@ __weak void SystemInit(void) MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH); MXC_PWRSEQ->retn_ctrl0 &= ~(MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK); - /* Set retention controller TWake cycle count to 1us to minimize the wake-up time */ /* NOTE: flash polling (...PWRSEQ_RETN_CTRL0_RC_POLL_FLASH) must be enabled before changing POR default! */ MXC_PWRSEQ->retn_ctrl1 = (MXC_PWRSEQ->retn_ctrl1 & ~MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK) | @@ -275,7 +278,22 @@ __weak void SystemInit(void) /* Perform an initial trim of the internal ring oscillator */ CLKMAN_TrimRO(); +#if !defined (__CC_ARM) // Prevent Keil tools from calling these functions until post scatter load SystemCoreClockUpdate(); Board_Init(); +#endif /* ! __CC_ARM */ + +} +#if defined ( __CC_ARM ) +/* Function called post memory initialization in the Keil Toolchain, which + * we are using to call the system core clock upddate and board initialization + * to prevent data corruption if they are called from SystemInit. */ +extern void $Super$$__main_after_scatterload(void); +void $Sub$$__main_after_scatterload(void) +{ + SystemCoreClockUpdate(); + Board_Init(); + $Super$$__main_after_scatterload(); } +#endif /* __CC_ARM */ From db971bb96e31a25b12c45f156fd560cc3d42b018 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 1 Feb 2021 22:09:21 -0600 Subject: [PATCH 084/617] Get default values for stack and heap for sam3u2c --- source/hic_hal/atmel/sam3u2c/armcc/startup_SAM3U.s | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/source/hic_hal/atmel/sam3u2c/armcc/startup_SAM3U.s b/source/hic_hal/atmel/sam3u2c/armcc/startup_SAM3U.s index bf5312427..077762c99 100644 --- a/source/hic_hal/atmel/sam3u2c/armcc/startup_SAM3U.s +++ b/source/hic_hal/atmel/sam3u2c/armcc/startup_SAM3U.s @@ -19,12 +19,13 @@ ; * ; *****************************************************************************/ +#include "daplink_defaults.h" ; Stack Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Stack_Size EQU 0x00000200 +Stack_Size EQU DAPLINK_STACK_SIZE AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size @@ -35,7 +36,7 @@ __initial_sp ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Heap_Size EQU 0x00000000 +Heap_Size EQU DAPLINK_HEAP_SIZE AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base From 68eeee4dadb46d312fc13b23e0851dcec9cc9b49 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 9 Feb 2021 18:48:55 -0600 Subject: [PATCH 085/617] Fix for RTOS2 configuration (problem spotted by @gerargz) --- records/rtos/rtos-cm0.yaml | 4 +++- records/rtos/rtos-cm3.yaml | 4 +++- records/rtos/rtos-cm4.yaml | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/records/rtos/rtos-cm0.yaml b/records/rtos/rtos-cm0.yaml index 9f64681cd..bff9ff5a3 100644 --- a/records/rtos/rtos-cm0.yaml +++ b/records/rtos/rtos-cm0.yaml @@ -1,11 +1,12 @@ common: macros: - - OS_TICK=10000 + - OS_TICK_FREQ=100 - __ARM_ARCH_6M__=1 tool_specific: uvision: macros: - USE_LEGACY_CMSIS_RTOS + - OS_TICK=10000 includes: - source/rtos sources: @@ -28,6 +29,7 @@ tool_specific: armcc: macros: - USE_LEGACY_CMSIS_RTOS + - OS_TICK=10000 includes: - source/rtos sources: diff --git a/records/rtos/rtos-cm3.yaml b/records/rtos/rtos-cm3.yaml index 4ac78d7d2..0093be97c 100644 --- a/records/rtos/rtos-cm3.yaml +++ b/records/rtos/rtos-cm3.yaml @@ -1,11 +1,12 @@ common: macros: - - OS_TICK=10000 + - OS_TICK_FREQ=100 tool_specific: uvision: macros: - USE_LEGACY_CMSIS_RTOS + - OS_TICK=10000 includes: - source/rtos sources: @@ -28,6 +29,7 @@ tool_specific: armcc: macros: - USE_LEGACY_CMSIS_RTOS + - OS_TICK=10000 includes: - source/rtos sources: diff --git a/records/rtos/rtos-cm4.yaml b/records/rtos/rtos-cm4.yaml index 08fa4e098..d52822246 100644 --- a/records/rtos/rtos-cm4.yaml +++ b/records/rtos/rtos-cm4.yaml @@ -1,6 +1,6 @@ common: macros: - - OS_TICK=10000 + - OS_TICK_FREQ=100 # Use irq_cm3 instead of irq_cm4f because DAPLink doesn't use float, # and the k20dx doesn't have the FP extension. @@ -8,6 +8,7 @@ tool_specific: uvision: macros: - USE_LEGACY_CMSIS_RTOS + - OS_TICK=10000 includes: - source/rtos sources: @@ -30,6 +31,7 @@ tool_specific: armcc: macros: - USE_LEGACY_CMSIS_RTOS + - OS_TICK=10000 includes: - source/rtos sources: From f5c6a4b83ef286351759310a2e3bb08308ce14d2 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 9 Feb 2021 18:51:19 -0600 Subject: [PATCH 086/617] Add compiler information in DETAILS.TXT --- source/daplink/drag-n-drop/vfs_user.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/source/daplink/drag-n-drop/vfs_user.c b/source/daplink/drag-n-drop/vfs_user.c index cd6cea7e4..20743336c 100644 --- a/source/daplink/drag-n-drop/vfs_user.c +++ b/source/daplink/drag-n-drop/vfs_user.c @@ -517,6 +517,14 @@ static uint32_t update_details_txt_file(uint8_t *data, uint32_t datasize) pos += util_write_string(buf + pos, "\r\n"); } +#if defined(__CC_ARM) + pos += util_write_string(buf + pos, "Compiler: armcc\r\n"); +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + pos += util_write_string(buf + pos, "Compiler: armclang\r\n"); +#elif defined(__GNUC__) + pos += util_write_string(buf + pos, "Compiler: gcc\r\n"); +#endif + // GIT sha pos += util_write_string(buf + pos, "Git SHA: "); pos += util_write_string(buf + pos, GIT_COMMIT_SHA); From 3dd090ee052ba1a9c43ca1c5be0b502bd826c9a4 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 10 Feb 2021 18:00:04 -0600 Subject: [PATCH 087/617] Need to mark __USED for GCC 10 LTO --- source/daplink/HardFault_Handler.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/daplink/HardFault_Handler.c b/source/daplink/HardFault_Handler.c index 73fc3d177..5575135df 100644 --- a/source/daplink/HardFault_Handler.c +++ b/source/daplink/HardFault_Handler.c @@ -26,7 +26,7 @@ //hexdump logic on hardfault -__NO_RETURN void _fault_handler(uint32_t _lr) +__USED __NO_RETURN void _fault_handler(uint32_t _lr) { uint32_t stk_ptr; uint32_t * stack = (uint32_t *)__get_MSP(); From d5d9be77268a1eee48339c826d51179c53b5cba2 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 10 Feb 2021 18:01:56 -0600 Subject: [PATCH 088/617] Partial revert of [db3c164c]: changes break armcc build --- .../hic_hal/maxim/max32625/system_max32625.c | 22 +++++-------------- 1 file changed, 6 insertions(+), 16 deletions(-) diff --git a/source/hic_hal/maxim/max32625/system_max32625.c b/source/hic_hal/maxim/max32625/system_max32625.c index 1657a0f21..f7433db58 100755 --- a/source/hic_hal/maxim/max32625/system_max32625.c +++ b/source/hic_hal/maxim/max32625/system_max32625.c @@ -53,6 +53,12 @@ #endif extern void (* const __isr_vector[])(void); + +/* +* Note: When compiling on ARM Keil Toolchain only. +* If the SystemCoreClock is left uninitialized, post Scatter load +* the clock will default to system reset value(48MHz) +*/ uint32_t SystemCoreClock = RO_FREQ/2; void SystemCoreClockUpdate(void) @@ -278,22 +284,6 @@ __weak void SystemInit(void) /* Perform an initial trim of the internal ring oscillator */ CLKMAN_TrimRO(); -#if !defined (__CC_ARM) // Prevent Keil tools from calling these functions until post scatter load - SystemCoreClockUpdate(); - Board_Init(); -#endif /* ! __CC_ARM */ - -} - -#if defined ( __CC_ARM ) -/* Function called post memory initialization in the Keil Toolchain, which - * we are using to call the system core clock upddate and board initialization - * to prevent data corruption if they are called from SystemInit. */ -extern void $Super$$__main_after_scatterload(void); -void $Sub$$__main_after_scatterload(void) -{ SystemCoreClockUpdate(); Board_Init(); - $Super$$__main_after_scatterload(); } -#endif /* __CC_ARM */ From f68eb124cef8befcb6a0c545f24d75cb024a6101 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Fri, 19 Feb 2021 13:13:36 -0600 Subject: [PATCH 089/617] Update readme. - Add note about gcc support on experimental_compilers branch. - Mention CMSIS-DAPv2 in interfaces list. - Update copyright year. --- README.md | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 3c29b979d..e6572d542 100644 --- a/README.md +++ b/README.md @@ -94,11 +94,20 @@ The following command combines generation and compilation: [![DAPLink](/docs/images/daplink-website-logo-link.png)](https://armmbed.github.io/DAPLink/) +**Note:** The master branch requires an Arm Compiler 5 or Keil MDK license to build. See the +[experimental_compilers](https://github.com/ARMmbed/DAPLink/tree/experimental_compilers) branch for gcc and Arm +Compiler 6 support. As soon as testing is complete, gcc will become the default compiler and AC5 support will be +dropped. + +---- + Arm Mbed DAPLink is an open-source software project that enables programming and debugging application software running on Arm Cortex CPUs. Commonly referred to as interface firmware, DAPLink runs on a secondary MCU that is attached to the SWD or JTAG port of the application MCU. This configuration is found on nearly all development boards. Enumerating as a USB composite device, it creates a bridge between your development computer and the CPU debug access port. DAPLink enables developers with: + * MSC - drag-n-drop programming flash memory * CDC - virtual com port for log, trace and terminal emulation -* HID - CMSIS-DAP compliant debug channel -* WEBUSB HID - CMSIS-DAP compliant debug channel +* CMSIS-DAPv2 WinUSB (driver-less vendor-specific bulk) - CMSIS compliant debug channel +* CMSIS-DAPv1 HID - CMSIS compliant debug channel +* WebUSB CMSIS-DAP HID - CMSIS compliant debug channel More features are planned and will show up gradually over time. The project is constantly under heavy development by Arm, its partners, numerous hardware vendors and the open-source community around the world. DAPLink has superseded the mbed CMSIS-DAP interface firmware project. You are free to use and contribute. Enjoy! @@ -132,4 +141,4 @@ Information for setting up a development environment, running the tests or creat DAPLink is licensed with the permissive Apache 2.0 license. See the [LICENSE](LICENSE) file for the full text of the license. -Copyright © 2006-2019 Arm Ltd +Copyright © 2006-2021 Arm Ltd From fc5bfbb5e93f46413df8dc2114993e3bbd79c8ee Mon Sep 17 00:00:00 2001 From: Ein Terakawa Date: Sat, 13 Feb 2021 12:48:57 +0900 Subject: [PATCH 090/617] Fix flash_algo.py to properly support both Python2 and Python3 --- requirements.txt | 1 - tools/flash_algo.py | 19 +++++++++---------- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/requirements.txt b/requirements.txt index e110dcd14..11f348055 100644 --- a/requirements.txt +++ b/requirements.txt @@ -4,7 +4,6 @@ pyserial pyOCD==0.28.* requests intelhex -six enum34 pyusb mbed-cli==1.8.2 diff --git a/tools/flash_algo.py b/tools/flash_algo.py index 6c8878c66..aea28a947 100644 --- a/tools/flash_algo.py +++ b/tools/flash_algo.py @@ -22,12 +22,11 @@ import binascii import argparse import logging -from six.moves import StringIO +from io import BytesIO import jinja2 from collections import namedtuple from itertools import count -from elftools.common.py3compat import bytes2str from elftools.elf.elffile import ELFFile from elftools.elf.sections import SymbolTableSection @@ -130,8 +129,8 @@ def format_algo_data(self, spaces, group_size, fmt): elif fmt == "c": blob = self.algo_data[:] pad_size = 0 if len(blob) % 4 == 0 else 4 - len(blob) % 4 - blob = blob + "\x00" * pad_size - integer_list = struct.unpack("<" + "L" * (len(blob) / 4), blob) + blob = blob + b"\x00" * pad_size + integer_list = struct.unpack("<" + "L" * int(len(blob) / 4), blob) line_list = [] for pos in range(0, len(integer_list), group_size): group = ["0x%08x" % value for value in @@ -166,7 +165,7 @@ def process_template(self, template_path, output_path, data_dict=None): template = jinja2.Template(template_text) target_text = template.render(data_dict) - with open(output_path, "wb") as file_handle: + with open(output_path, "w") as file_handle: file_handle.write(target_text) @@ -187,7 +186,7 @@ def _find_sections(elf, name_type_pairs): """Return a list of sections the same length and order of the input list""" sections = [None] * len(name_type_pairs) for section in elf.iter_sections(): - section_name = bytes2str(section.name) + section_name = section.name section_type = section["sh_type"] for i, name_and_type in enumerate(name_type_pairs): if name_and_type != (section_name, section_type): @@ -261,7 +260,7 @@ def __init__(self, elf_simple): values = struct.unpack(self.FLASH_DEVICE_STRUCT, data) self.version = values[0] - self.name = values[1].strip("\x00") + self.name = values[1].strip(b"\x00") self.type = values[2] self.start = values[3] self.size = values[4] @@ -311,12 +310,12 @@ class ElfFileSimple(ELFFile): def __init__(self, data): """Construct a ElfFileSimple from bytes or a bytearray""" - super(ElfFileSimple, self).__init__(StringIO.StringIO(data)) + super(ElfFileSimple, self).__init__(BytesIO(data)) self.symbols = self._read_symbol_table() def _read_symbol_table(self): """Read the symbol table into the field "symbols" for easy use""" - section = self.get_section_by_name(b".symtab") + section = self.get_section_by_name(".symtab") if not section: raise Exception("Missing symbol table") @@ -325,7 +324,7 @@ def _read_symbol_table(self): symbols = {} for symbol in section.iter_symbols(): - name_str = bytes2str(symbol.name) + name_str = symbol.name if name_str in symbols: logging.debug("Duplicate symbol %s", name_str) symbols[name_str] = SymbolSimple(name_str, symbol["st_value"], From 97ed18d607bb7b5cf7788662066683e1e2d19c84 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Mon, 27 Jul 2020 11:45:23 -0500 Subject: [PATCH 091/617] CMSIS-DAP: support for DAP_ID_PRODUCT_FW_VER. - Merged in proposed CMSIS-DAP extension for DAP_ID_PRODUCT_FW_VER. - Reverted DAP_ID_FW_VER (now DAP_ID_CMSIS_DAP_VER) to report the CMSIS-DAP protocol version. - Reporting the DAPLink version via the new DAP_ID_PRODUCT_FW_VER. --- source/daplink/cmsis-dap/DAP.c | 18 ++++++++---------- source/daplink/cmsis-dap/DAP.h | 8 +++++--- source/daplink/cmsis-dap/dap_strings.h | 2 +- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/source/daplink/cmsis-dap/DAP.c b/source/daplink/cmsis-dap/DAP.c index 0dd0de463..27dd62419 100644 --- a/source/daplink/cmsis-dap/DAP.c +++ b/source/daplink/cmsis-dap/DAP.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2020 ARM Limited. All rights reserved. * Copyright 2019, Cypress Semiconductor Corporation * or a subsidiary of Cypress Semiconductor Corporation. * @@ -64,7 +64,7 @@ volatile uint8_t DAP_TransferAbort; // Transfer Abort Flag -// static const char DAP_FW_Ver [] = DAP_FW_VER; +static const char DAP_FW_Ver [] = DAP_FW_VER; #if TARGET_DEVICE_FIXED static const char TargetDeviceVendor [] = TARGET_DEVICE_VENDOR; @@ -89,15 +89,10 @@ static uint8_t DAP_Info(uint8_t id, uint8_t *info) { case DAP_ID_SER_NUM: length = DAP_GetSerNumString((char *)info); break; - case DAP_ID_FW_VER: { -// --- begin DAPLink change --- - length = DAP_GetFirmwareVersionString((char *)info); -// Original: -// memcpy(info, DAP_FW_Ver, sizeof(DAP_FW_Ver)); -// length = (uint8_t)sizeof(DAP_FW_Ver); -// --- end DAPLink change --- + case DAP_ID_CMSIS_DAP_VER: + length = (uint8_t)sizeof(DAP_FW_Ver); + memcpy(info, DAP_FW_Ver, length); break; - } case DAP_ID_DEVICE_VENDOR: #if TARGET_DEVICE_FIXED length = (uint8_t)sizeof(TargetDeviceVendor); @@ -110,6 +105,9 @@ static uint8_t DAP_Info(uint8_t id, uint8_t *info) { memcpy(info, TargetDeviceName, length); #endif break; + case DAP_ID_PRODUCT_FW_VER: + length = DAP_ProductFirmwareVerString((char *)info); + break; case DAP_ID_CAPABILITIES: info[0] = ((DAP_SWD != 0) ? (1U << 0) : 0U) | ((DAP_JTAG != 0) ? (1U << 1) : 0U) | diff --git a/source/daplink/cmsis-dap/DAP.h b/source/daplink/cmsis-dap/DAP.h index edf300a21..7f646f170 100644 --- a/source/daplink/cmsis-dap/DAP.h +++ b/source/daplink/cmsis-dap/DAP.h @@ -1,6 +1,6 @@ /* - * Copyright (c) 2013-2019 ARM Limited. All rights reserved. - * Copyright 2019, Cypress Semiconductor Corporation + * Copyright (c) 2013-2020 ARM Limited. All rights reserved. + * Copyright 2019, Cypress Semiconductor Corporation * or a subsidiary of Cypress Semiconductor Corporation. * * SPDX-License-Identifier: Apache-2.0 @@ -118,9 +118,11 @@ #define DAP_ID_VENDOR 1U #define DAP_ID_PRODUCT 2U #define DAP_ID_SER_NUM 3U -#define DAP_ID_FW_VER 4U +#define DAP_ID_CMSIS_DAP_VER 4U +#define DAP_ID_FW_VER 4U // Deprecated alias of DAP_ID_CMSIS_DAP_VER for backwards compatibility. #define DAP_ID_DEVICE_VENDOR 5U #define DAP_ID_DEVICE_NAME 6U +#define DAP_ID_PRODUCT_FW_VER 7U #define DAP_ID_CAPABILITIES 0xF0U #define DAP_ID_TIMESTAMP_CLOCK 0xF1U #define DAP_ID_SWO_BUFFER_SIZE 0xFDU diff --git a/source/daplink/cmsis-dap/dap_strings.h b/source/daplink/cmsis-dap/dap_strings.h index 786065b64..cb7f73bb1 100644 --- a/source/daplink/cmsis-dap/dap_strings.h +++ b/source/daplink/cmsis-dap/dap_strings.h @@ -54,7 +54,7 @@ __STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) { \param str Pointer to buffer to store the string. \return String length. */ -__STATIC_INLINE uint8_t DAP_GetFirmwareVersionString (char *str) { +__STATIC_INLINE uint8_t DAP_ProductFirmwareVerString (char *str) { const char * data = info_get_version(); uint8_t length = (uint8_t)strlen(data) + 1; memcpy(str, data, length); From b056a5e44897e3c04337bc50c2308b138a5e3864 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 19 Dec 2020 00:03:04 -0600 Subject: [PATCH 092/617] Initial Github Actions file (cherry picked from commit d099c1f3bf56623b634963bce9e51edba805395f) --- .github/workflows/build.yml | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 .github/workflows/build.yml diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml new file mode 100644 index 000000000..d9099b924 --- /dev/null +++ b/.github/workflows/build.yml @@ -0,0 +1,30 @@ +name: Build DAPLink + +on: + push: + branches: [ development ] + + pull_request: + branches: [ development ] + +jobs: + build: + runs-on: ubuntu-20.04 + + steps: + - name: Cache Embedded Arm Toolchain + id: cache-arm-gcc + uses: actions/cache@v2 + env: + cache-name: cache-arm-gcc-9-2020-q2 + with: + path: ${{ runner.temp }}/arm-gcc + key: ${{ runner.os }}-build-${{ env.cache-name }} + restore-keys: ${{ runner.os }}-build-${{ env.cache-name }} + + - name: Install Embedded Arm Toolchain + if: steps.cache-arm-none-eabi-gcc.outputs.cache-hit != 'true' + uses: fiam/arm-none-eabi-gcc@v1.0.2 + with: + release: 9-2020-q2 + directory: ${{ runner.temp }}/arm-gcc From 6d18fe7397d3ab002e4f8ff16b18deb4c6dee26d Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 19 Dec 2020 00:26:36 -0600 Subject: [PATCH 093/617] Manual installation of arm-none-eabi-gcc (cherry picked from commit c21f89406a881c3d2036333e9cdc780569a25cf5) --- .github/workflows/build.yml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index d9099b924..730f230a7 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -16,15 +16,15 @@ jobs: id: cache-arm-gcc uses: actions/cache@v2 env: - cache-name: cache-arm-gcc-9-2020-q2 + cache-name: arm-gcc-9-2020-q2 with: path: ${{ runner.temp }}/arm-gcc - key: ${{ runner.os }}-build-${{ env.cache-name }} - restore-keys: ${{ runner.os }}-build-${{ env.cache-name }} + key: ${{ runner.os }}-${{ env.cache-name }} + restore-keys: ${{ runner.os }}-${{ env.cache-name }} - name: Install Embedded Arm Toolchain - if: steps.cache-arm-none-eabi-gcc.outputs.cache-hit != 'true' - uses: fiam/arm-none-eabi-gcc@v1.0.2 - with: - release: 9-2020-q2 - directory: ${{ runner.temp }}/arm-gcc + if: steps.cache-arm-gcc.outputs.cache-hit != 'true' + run: | + curl -O -S https://developer.arm.com/-/media/Files/downloads/gnu-rm/9-2020q2/gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 + mkdir -p ${{ runner.temp }}/arm-gcc + tar jvxf gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 -C ${{ runner.temp }}/arm-gcc --strip-components 1 From 8f8ed9d2d8eeb58493ccc6ab42f59a81b104b77c Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 19 Dec 2020 00:35:41 -0600 Subject: [PATCH 094/617] Additional build configuration (cherry picked from commit a76bd95a52d4d6494ec81ab8e441f73adde02f3e) --- .github/workflows/build.yml | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 730f230a7..281293e6c 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -22,9 +22,31 @@ jobs: key: ${{ runner.os }}-${{ env.cache-name }} restore-keys: ${{ runner.os }}-${{ env.cache-name }} + - name: Cache Python modules + uses: actions/cache@v2 + with: + path: ~/.cache/pip + key: ${{ runner.os }}-pip-${{ hashFiles('**/requirements.txt') }} + restore-keys: | + ${{ runner.os }}-pip- + + - name: Checkout source files + uses: actions/checkout@v2 + + - name: Install Python module + run: | + pip3 install --user -r requirements.txt + pip3 install --user git+https://github.com/mbrossard/project_generator.git@development + + - name: Install dependencies + run: | + sudo apt install ccache ninja + - name: Install Embedded Arm Toolchain if: steps.cache-arm-gcc.outputs.cache-hit != 'true' run: | curl -O -S https://developer.arm.com/-/media/Files/downloads/gnu-rm/9-2020q2/gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 + md5sum gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 mkdir -p ${{ runner.temp }}/arm-gcc tar jvxf gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 -C ${{ runner.temp }}/arm-gcc --strip-components 1 + From 6a63e39d5b9fc5421fbf9fa21ff5ba205169dfdd Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 19 Dec 2020 01:00:15 -0600 Subject: [PATCH 095/617] Caching ccache cache (cherry picked from commit e472ae5082383dd2fe966a0bdc540d37d1df5b3b) --- .github/workflows/build.yml | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 281293e6c..46134a215 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -22,6 +22,14 @@ jobs: key: ${{ runner.os }}-${{ env.cache-name }} restore-keys: ${{ runner.os }}-${{ env.cache-name }} + - name: Cache CCache + id: ccache + uses: actions/cache@v2 + with: + path: ~/.ccache + key: ${{ runner.os }}-ccache-${{ hashFiles('log.txt') }} + restore-keys: ${{ runner.os }}-ccache- + - name: Cache Python modules uses: actions/cache@v2 with: @@ -38,15 +46,11 @@ jobs: pip3 install --user -r requirements.txt pip3 install --user git+https://github.com/mbrossard/project_generator.git@development - - name: Install dependencies - run: | - sudo apt install ccache ninja - - name: Install Embedded Arm Toolchain if: steps.cache-arm-gcc.outputs.cache-hit != 'true' run: | - curl -O -S https://developer.arm.com/-/media/Files/downloads/gnu-rm/9-2020q2/gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 + curl -O -L https://developer.arm.com/-/media/Files/downloads/gnu-rm/9-2020q2/gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 md5sum gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 + echo Installing $gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux in {{ runner.temp }}/arm-gcc mkdir -p ${{ runner.temp }}/arm-gcc tar jvxf gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 -C ${{ runner.temp }}/arm-gcc --strip-components 1 - From 060641946645522ee00ded3608c97cb7ba0d4b0d Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 19 Dec 2020 01:04:18 -0600 Subject: [PATCH 096/617] Add compilation steps (cherry picked from commit 1452f1b60d728e859a03f9690464e93ed97833e2) --- .github/workflows/build.yml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 46134a215..6c668627b 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -54,3 +54,18 @@ jobs: echo Installing $gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux in {{ runner.temp }}/arm-gcc mkdir -p ${{ runner.temp }}/arm-gcc tar jvxf gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 -C ${{ runner.temp }}/arm-gcc --strip-components 1 + + - name: Install dependencies + run: | + sudo apt install ccache ninja-build + for i in ${{ runner.temp }}/arm-gcc/bin/* ; ln -s /usr/bin/ccache /usr/lib/ccache/$(basename $i); done + ccache -M 1Ti + + - name: Compile + run: | + export PATH=/usr/lib/ccache:${{ runner.temp }}/arm-gcc/bin/:$PATH + python tools/progen_compile.py + + - name: Display results + run: | + - (find projectfiles -name *.elf | xargs ls -l; ccache -s) | tee log.txt From c4c588d318f4c255a5cd0fff437a98d8bec8c919 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 19 Dec 2020 01:14:18 -0600 Subject: [PATCH 097/617] Build release and leverage all cores (cherry picked from commit b6d049dc6be90fca733adcf6bfecc38372443797) --- .github/workflows/build.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 6c668627b..55f337ad7 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -58,14 +58,14 @@ jobs: - name: Install dependencies run: | sudo apt install ccache ninja-build - for i in ${{ runner.temp }}/arm-gcc/bin/* ; ln -s /usr/bin/ccache /usr/lib/ccache/$(basename $i); done + for i in ${{ runner.temp }}/arm-gcc/bin/* ; do ln -s /usr/bin/ccache /usr/lib/ccache/$(basename $i); done ccache -M 1Ti - name: Compile run: | export PATH=/usr/lib/ccache:${{ runner.temp }}/arm-gcc/bin/:$PATH - python tools/progen_compile.py + python tools/progen_compile.py --release --parallel - name: Display results run: | - - (find projectfiles -name *.elf | xargs ls -l; ccache -s) | tee log.txt + - (ls -lR firmware_*; ccache -s) | tee log.txt From ccef680c492c8793749ce0020158bae0ca20cd8f Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 19 Dec 2020 01:24:20 -0600 Subject: [PATCH 098/617] Fix symbolic link and add artifacts upload (cherry picked from commit 4d275cf7669f2bfce02096aeb855ea132fa17a8d) --- .github/workflows/build.yml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 55f337ad7..ea7cf751b 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -58,7 +58,7 @@ jobs: - name: Install dependencies run: | sudo apt install ccache ninja-build - for i in ${{ runner.temp }}/arm-gcc/bin/* ; do ln -s /usr/bin/ccache /usr/lib/ccache/$(basename $i); done + for i in ${{ runner.temp }}/arm-gcc/bin/* ; do sudo ln -s /usr/bin/ccache /usr/lib/ccache/$(basename $i); done ccache -M 1Ti - name: Compile @@ -69,3 +69,10 @@ jobs: - name: Display results run: | - (ls -lR firmware_*; ccache -s) | tee log.txt + + - name: Upload test artifacts + uses: actions/upload-artifact@v2 + with: + name: firmware-package + path: | + firmware*/*.zip From d39a3fd1ed9c9392f300279c8bf409ff7e927a11 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 19 Dec 2020 01:32:22 -0600 Subject: [PATCH 099/617] Fix installation of development version project-generator (cherry picked from commit d5592019f1ee301d049d5b38dc9c5f7377108ffc) --- .github/workflows/build.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index ea7cf751b..18c9bb749 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -44,6 +44,7 @@ jobs: - name: Install Python module run: | pip3 install --user -r requirements.txt + pip3 uninstall --user -y project-generator pip3 install --user git+https://github.com/mbrossard/project_generator.git@development - name: Install Embedded Arm Toolchain @@ -63,7 +64,7 @@ jobs: - name: Compile run: | - export PATH=/usr/lib/ccache:${{ runner.temp }}/arm-gcc/bin/:$PATH + export PATH=/usr/lib/ccache:${{ runner.temp }}/arm-gcc/bin/:/home/runner/.local/bin:$PATH python tools/progen_compile.py --release --parallel - name: Display results From a806e3d49e185906c5b24217ed8a9151f2800ede Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 19 Dec 2020 07:51:47 -0600 Subject: [PATCH 100/617] More verbose output and ignore failure for now (cherry picked from commit 13882600850e4846d96e0326203a596c7e817fa0) --- .github/workflows/build.yml | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 18c9bb749..70d51f3d9 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -61,15 +61,14 @@ jobs: sudo apt install ccache ninja-build for i in ${{ runner.temp }}/arm-gcc/bin/* ; do sudo ln -s /usr/bin/ccache /usr/lib/ccache/$(basename $i); done ccache -M 1Ti - - - name: Compile - run: | export PATH=/usr/lib/ccache:${{ runner.temp }}/arm-gcc/bin/:/home/runner/.local/bin:$PATH - python tools/progen_compile.py --release --parallel + arm-none-eabi-gcc -v - - name: Display results + - name: Compile run: | - - (ls -lR firmware_*; ccache -s) | tee log.txt + export PATH="/usr/lib/ccache:${{ runner.temp }}/arm-gcc/bin/:/home/runner/.local/bin:$PATH" + python tools/progen_compile.py --release --parallel -v -v --ignore-failures + (ls -lR firmware_*; ccache -s; arm-none-eabi-gcc -v) | tee log.txt - name: Upload test artifacts uses: actions/upload-artifact@v2 From 7d83285de25d3374ecabd3db40e5221b85afa07d Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 19 Dec 2020 07:57:23 -0600 Subject: [PATCH 101/617] Fix pip3 asymmetry (cherry picked from commit 4b58f741c06a145156e224c95ae985f044ecee78) --- .github/workflows/build.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 70d51f3d9..55da5d01b 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -44,7 +44,7 @@ jobs: - name: Install Python module run: | pip3 install --user -r requirements.txt - pip3 uninstall --user -y project-generator + pip3 uninstall -y project-generator pip3 install --user git+https://github.com/mbrossard/project_generator.git@development - name: Install Embedded Arm Toolchain From a80c8b39ecdbe64d8c2026124f52c600ae889a48 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 19 Dec 2020 08:22:38 -0600 Subject: [PATCH 102/617] Invalidate ccache cache key (cherry picked from commit e07517ee1b913e32bfeda57e66668a7477dcc92e) --- .github/workflows/build.yml | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 55da5d01b..bab881e29 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -22,14 +22,6 @@ jobs: key: ${{ runner.os }}-${{ env.cache-name }} restore-keys: ${{ runner.os }}-${{ env.cache-name }} - - name: Cache CCache - id: ccache - uses: actions/cache@v2 - with: - path: ~/.ccache - key: ${{ runner.os }}-ccache-${{ hashFiles('log.txt') }} - restore-keys: ${{ runner.os }}-ccache- - - name: Cache Python modules uses: actions/cache@v2 with: @@ -62,7 +54,16 @@ jobs: for i in ${{ runner.temp }}/arm-gcc/bin/* ; do sudo ln -s /usr/bin/ccache /usr/lib/ccache/$(basename $i); done ccache -M 1Ti export PATH=/usr/lib/ccache:${{ runner.temp }}/arm-gcc/bin/:/home/runner/.local/bin:$PATH - arm-none-eabi-gcc -v + arm-none-eabi-gcc -v | tee log.txt + (git status; git log -1 )>> log.txt + + - name: Cache CCache + id: ccache + uses: actions/cache@v2 + with: + path: ~/.ccache + key: ${{ runner.os }}-ccache-${{ hashFiles('log.txt') }} + restore-keys: ${{ runner.os }}-ccache- - name: Compile run: | From 925144e367057b15fdc3eec6ef6be32c202fb3c2 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 19 Dec 2020 09:12:04 -0600 Subject: [PATCH 103/617] Build artifact differently (cherry picked from commit 2f40e37d39769b1a980873e07e9a6527c2c9656c) --- .github/workflows/build.yml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index bab881e29..4ff9948df 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -74,6 +74,7 @@ jobs: - name: Upload test artifacts uses: actions/upload-artifact@v2 with: - name: firmware-package + name: firmware-dev-{{github.run_number}} path: | - firmware*/*.zip + firmware*/* + !firmware*/*.zip From 48f6b92e5a815c6fa75479512bdb90be9cb407ad Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 19 Dec 2020 09:44:00 -0600 Subject: [PATCH 104/617] Try to fix ccache path (cherry picked from commit db05a4e7cfe8f8540c9c1d44dd34d932a7f6a82c) --- .github/workflows/build.yml | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 4ff9948df..a994149fd 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -50,10 +50,13 @@ jobs: - name: Install dependencies run: | - sudo apt install ccache ninja-build - for i in ${{ runner.temp }}/arm-gcc/bin/* ; do sudo ln -s /usr/bin/ccache /usr/lib/ccache/$(basename $i); done - ccache -M 1Ti + sudo apt install -y ccache ninja-build export PATH=/usr/lib/ccache:${{ runner.temp }}/arm-gcc/bin/:/home/runner/.local/bin:$PATH + for i in ${{ runner.temp }}/arm-gcc/bin/* ; do sudo ln -s /usr/bin/ccache /usr/lib/ccache/$(basename $i); done + ccache --set-config=cache_dir="$GITHUB_WORKSPACE" + ccache --set-config=cache_dir="$GITHUB_WORKSPACE/.ccache" + ccache --set-config=max_size=2Ti + ccache -z -s arm-none-eabi-gcc -v | tee log.txt (git status; git log -1 )>> log.txt @@ -61,7 +64,7 @@ jobs: id: ccache uses: actions/cache@v2 with: - path: ~/.ccache + path: .ccache key: ${{ runner.os }}-ccache-${{ hashFiles('log.txt') }} restore-keys: ${{ runner.os }}-ccache- From 81b6e7b41bf421c8ec63273291b3a64179087e90 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 22 Dec 2020 13:43:54 -0600 Subject: [PATCH 105/617] Fix typo in artifact file name (cherry picked from commit a159a460c406e648e809d9a3a7c98e1b55b9aac9) --- .github/workflows/build.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index a994149fd..f4bd000ca 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -77,7 +77,7 @@ jobs: - name: Upload test artifacts uses: actions/upload-artifact@v2 with: - name: firmware-dev-{{github.run_number}} + name: firmware-dev-${{github.run_number}} path: | firmware*/* !firmware*/*.zip From f3ef32206760c53f13b8f03d3605b8cb82be046e Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 22 Dec 2020 13:54:19 -0600 Subject: [PATCH 106/617] Run github actions manually --- .github/workflows/build.yml | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index f4bd000ca..5453b39bb 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -1,11 +1,9 @@ name: Build DAPLink - on: - push: - branches: [ development ] - - pull_request: - branches: [ development ] + workflow_dispatch: + inputs: + version: + required: true jobs: build: From 8af75c5389f2671cee4bb9b678584e1a5fdbae18 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 1 Jan 2021 14:14:50 -0600 Subject: [PATCH 107/617] Adding initial Windows build action --- .github/workflows/{build.yml => linux.yml} | 4 +- .github/workflows/windows.yml | 63 ++++++++++++++++++++++ 2 files changed, 65 insertions(+), 2 deletions(-) rename .github/workflows/{build.yml => linux.yml} (95%) create mode 100644 .github/workflows/windows.yml diff --git a/.github/workflows/build.yml b/.github/workflows/linux.yml similarity index 95% rename from .github/workflows/build.yml rename to .github/workflows/linux.yml index 5453b39bb..b12a20d30 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/linux.yml @@ -1,4 +1,4 @@ -name: Build DAPLink +name: Build DAPLink (Linux) on: workflow_dispatch: inputs: @@ -42,7 +42,7 @@ jobs: run: | curl -O -L https://developer.arm.com/-/media/Files/downloads/gnu-rm/9-2020q2/gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 md5sum gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 - echo Installing $gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux in {{ runner.temp }}/arm-gcc + echo Installing gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux in ${{ runner.temp }}/arm-gcc mkdir -p ${{ runner.temp }}/arm-gcc tar jvxf gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 -C ${{ runner.temp }}/arm-gcc --strip-components 1 diff --git a/.github/workflows/windows.yml b/.github/workflows/windows.yml new file mode 100644 index 000000000..38a44bd92 --- /dev/null +++ b/.github/workflows/windows.yml @@ -0,0 +1,63 @@ +name: Build DAPLink (Windows) +on: + workflow_dispatch: + inputs: + version: + required: true + +jobs: + build: + runs-on: windows-2019 + + steps: + - name: Cache Embedded Arm Toolchain + id: cache-arm-gcc + uses: actions/cache@v2 + env: + cache-name: arm-gcc-9-2020-q2 + with: + path: ${{ runner.temp }}/arm-gcc + key: ${{ runner.os }}-${{ env.cache-name }} + restore-keys: ${{ runner.os }}-${{ env.cache-name }} + + - name: Cache Python modules + uses: actions/cache@v2 + with: + path: ~\AppData\Local\pip\Cache + key: ${{ runner.os }}-pip-${{ hashFiles('**/requirements.txt') }} + restore-keys: | + ${{ runner.os }}-pip- + + - name: Checkout source files + uses: actions/checkout@v2 + + - name: Install Embedded Arm Toolchain + if: steps.cache-arm-gcc.outputs.cache-hit != 'true' + run: | + (New-Object System.Net.WebClient).DownloadFile("https://developer.arm.com/-/media/Files/downloads/gnu-rm/9-2020q2/gcc-arm-none-eabi-9-2020-q2-update-win32.zip","gcc-arm-none-eabi-9-2020-q2-update-win32.zip"); + echo "Installing gcc-arm-none-eabi-9-2020-q2-update-win32 in ${{ runner.temp }}\arm-gcc" + Expand-Archive -Path .\gcc-arm-none-eabi-9-2020-q2-update-win32.zip -DestinationPath ${{ runner.temp }}\arm-gcc -PassThru; + + - name: Check Embedded Arm Toolchain + run: | + echo ${{ runner.temp }}\arm-gcc\bin | Out-File -FilePath $env:GITHUB_PATH -Encoding utf8 -Append + ${{ runner.temp }}\arm-gcc\bin\arm-none-eabi-gcc -v + + - name: Install Python module + run: | + pip install -r requirements.txt + pip uninstall -y project-generator + pip install -U git+https://github.com/mbrossard/project_generator.git@development + + - name: Compile + run: | + python tools/progen_compile.py --release --parallel -v --ignore- + shell: cmd + + - name: Upload test artifacts + uses: actions/upload-artifact@v2 + with: + name: firmware-dev-${{github.run_number}} + path: | + firmware*/* + !firmware*/*.zip From 4605bd2a8f67de5a74d647dde82dd0b548c000b6 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sun, 3 Jan 2021 10:04:32 -0600 Subject: [PATCH 108/617] Use CMake for Windows --- .github/workflows/windows.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/windows.yml b/.github/workflows/windows.yml index 38a44bd92..0c5ebf64d 100644 --- a/.github/workflows/windows.yml +++ b/.github/workflows/windows.yml @@ -51,7 +51,7 @@ jobs: - name: Compile run: | - python tools/progen_compile.py --release --parallel -v --ignore- + python tools/progen_compile.py -t cmake_gcc_arm -g mingw-make --release --parallel -v --ignore-failures shell: cmd - name: Upload test artifacts From 1ffcf73fc810909d0177ff07c453bf989a2c7eda Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 25 Jan 2021 23:42:43 -0600 Subject: [PATCH 109/617] Switch to project-generator 0.11 --- .github/workflows/linux.yml | 2 -- .github/workflows/windows.yml | 2 -- 2 files changed, 4 deletions(-) diff --git a/.github/workflows/linux.yml b/.github/workflows/linux.yml index b12a20d30..1154d47bf 100644 --- a/.github/workflows/linux.yml +++ b/.github/workflows/linux.yml @@ -34,8 +34,6 @@ jobs: - name: Install Python module run: | pip3 install --user -r requirements.txt - pip3 uninstall -y project-generator - pip3 install --user git+https://github.com/mbrossard/project_generator.git@development - name: Install Embedded Arm Toolchain if: steps.cache-arm-gcc.outputs.cache-hit != 'true' diff --git a/.github/workflows/windows.yml b/.github/workflows/windows.yml index 0c5ebf64d..a78be17c7 100644 --- a/.github/workflows/windows.yml +++ b/.github/workflows/windows.yml @@ -46,8 +46,6 @@ jobs: - name: Install Python module run: | pip install -r requirements.txt - pip uninstall -y project-generator - pip install -U git+https://github.com/mbrossard/project_generator.git@development - name: Compile run: | From bc99dfa02f010394da9fc76ec9c40eefcddb0061 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 26 Jan 2021 18:06:51 -0600 Subject: [PATCH 110/617] Update arm-none-eabi-gcc version and change GitHub Action triggers --- .github/workflows/linux.yml | 17 +++++++++-------- .github/workflows/windows.yml | 15 ++++++++------- 2 files changed, 17 insertions(+), 15 deletions(-) diff --git a/.github/workflows/linux.yml b/.github/workflows/linux.yml index 1154d47bf..4d4c800f0 100644 --- a/.github/workflows/linux.yml +++ b/.github/workflows/linux.yml @@ -1,9 +1,10 @@ name: Build DAPLink (Linux) on: + push: + branches: + - development + - compilers_experimental workflow_dispatch: - inputs: - version: - required: true jobs: build: @@ -14,7 +15,7 @@ jobs: id: cache-arm-gcc uses: actions/cache@v2 env: - cache-name: arm-gcc-9-2020-q2 + cache-name: arm-gcc-10-2020-q4 with: path: ${{ runner.temp }}/arm-gcc key: ${{ runner.os }}-${{ env.cache-name }} @@ -38,11 +39,11 @@ jobs: - name: Install Embedded Arm Toolchain if: steps.cache-arm-gcc.outputs.cache-hit != 'true' run: | - curl -O -L https://developer.arm.com/-/media/Files/downloads/gnu-rm/9-2020q2/gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 - md5sum gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 - echo Installing gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux in ${{ runner.temp }}/arm-gcc + curl -O -L https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2 + md5sum gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2 + echo Installing in ${{ runner.temp }}/arm-gcc mkdir -p ${{ runner.temp }}/arm-gcc - tar jvxf gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 -C ${{ runner.temp }}/arm-gcc --strip-components 1 + tar jvxf gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2 -C ${{ runner.temp }}/arm-gcc --strip-components 1 - name: Install dependencies run: | diff --git a/.github/workflows/windows.yml b/.github/workflows/windows.yml index a78be17c7..a583439e1 100644 --- a/.github/workflows/windows.yml +++ b/.github/workflows/windows.yml @@ -1,9 +1,10 @@ name: Build DAPLink (Windows) on: + push: + branches: + - development + - compilers_experimental workflow_dispatch: - inputs: - version: - required: true jobs: build: @@ -14,7 +15,7 @@ jobs: id: cache-arm-gcc uses: actions/cache@v2 env: - cache-name: arm-gcc-9-2020-q2 + cache-name: arm-gcc-10-2020-q4 with: path: ${{ runner.temp }}/arm-gcc key: ${{ runner.os }}-${{ env.cache-name }} @@ -34,9 +35,9 @@ jobs: - name: Install Embedded Arm Toolchain if: steps.cache-arm-gcc.outputs.cache-hit != 'true' run: | - (New-Object System.Net.WebClient).DownloadFile("https://developer.arm.com/-/media/Files/downloads/gnu-rm/9-2020q2/gcc-arm-none-eabi-9-2020-q2-update-win32.zip","gcc-arm-none-eabi-9-2020-q2-update-win32.zip"); - echo "Installing gcc-arm-none-eabi-9-2020-q2-update-win32 in ${{ runner.temp }}\arm-gcc" - Expand-Archive -Path .\gcc-arm-none-eabi-9-2020-q2-update-win32.zip -DestinationPath ${{ runner.temp }}\arm-gcc -PassThru; + (New-Object System.Net.WebClient).DownloadFile("https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-win32.zip","gcc-arm-none-eabi-10-2020-q4-major-win32.zip"); + echo "Installing gcc-arm-none-eabi-10-2020-q4-major-win32 in ${{ runner.temp }}\arm-gcc" + Expand-Archive -Path .\gcc-arm-none-eabi-10-2020-q4-major-win32.zip -DestinationPath ${{ runner.temp }}\arm-gcc -PassThru; - name: Check Embedded Arm Toolchain run: | From 48a849162c3b57222ce60c948cfae02d4e884fe1 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 26 Jan 2021 18:56:20 -0600 Subject: [PATCH 111/617] Support arm-none-eabi-gcc archive path --- .github/workflows/windows.yml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/.github/workflows/windows.yml b/.github/workflows/windows.yml index a583439e1..50444dd58 100644 --- a/.github/workflows/windows.yml +++ b/.github/workflows/windows.yml @@ -36,8 +36,9 @@ jobs: if: steps.cache-arm-gcc.outputs.cache-hit != 'true' run: | (New-Object System.Net.WebClient).DownloadFile("https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-win32.zip","gcc-arm-none-eabi-10-2020-q4-major-win32.zip"); - echo "Installing gcc-arm-none-eabi-10-2020-q4-major-win32 in ${{ runner.temp }}\arm-gcc" - Expand-Archive -Path .\gcc-arm-none-eabi-10-2020-q4-major-win32.zip -DestinationPath ${{ runner.temp }}\arm-gcc -PassThru; + echo "Installing gcc-arm-none-eabi-10-2020-q4-major-win32 in ${{ runner.temp }}\arm-gcc"; + Expand-Archive -Path .\gcc-arm-none-eabi-10-2020-q4-major-win32.zip -DestinationPath ${{ runner.temp }} -PassThru; + Rename-Item ${{ runner.temp }}\gcc-arm-none-eabi-10-2020-q4-major ${{ runner.temp }}\arm-gcc; - name: Check Embedded Arm Toolchain run: | From 290cbdc76e422019bb24e1cc9d295e22e877ef36 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 26 Jan 2021 20:26:28 -0600 Subject: [PATCH 112/617] Disable automatic trigger for Windows Linux workflow is much faster (in part because it supports ccache) --- .github/workflows/linux.yml | 1 - .github/workflows/windows.yml | 4 ---- 2 files changed, 5 deletions(-) diff --git a/.github/workflows/linux.yml b/.github/workflows/linux.yml index 4d4c800f0..80ec2ddb8 100644 --- a/.github/workflows/linux.yml +++ b/.github/workflows/linux.yml @@ -2,7 +2,6 @@ name: Build DAPLink (Linux) on: push: branches: - - development - compilers_experimental workflow_dispatch: diff --git a/.github/workflows/windows.yml b/.github/workflows/windows.yml index 50444dd58..affd401c7 100644 --- a/.github/workflows/windows.yml +++ b/.github/workflows/windows.yml @@ -1,9 +1,5 @@ name: Build DAPLink (Windows) on: - push: - branches: - - development - - compilers_experimental workflow_dispatch: jobs: From 9e967e9b33cf8cccc68b784a355d07801a8c8dfe Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 17 Apr 2021 14:41:07 -0500 Subject: [PATCH 113/617] Revert to GCC 9 --- .github/workflows/linux.yml | 10 +++++----- .github/workflows/windows.yml | 9 ++++----- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/.github/workflows/linux.yml b/.github/workflows/linux.yml index 80ec2ddb8..842cb92c7 100644 --- a/.github/workflows/linux.yml +++ b/.github/workflows/linux.yml @@ -14,7 +14,7 @@ jobs: id: cache-arm-gcc uses: actions/cache@v2 env: - cache-name: arm-gcc-10-2020-q4 + cache-name: arm-gcc-9-2020-q2 with: path: ${{ runner.temp }}/arm-gcc key: ${{ runner.os }}-${{ env.cache-name }} @@ -38,11 +38,11 @@ jobs: - name: Install Embedded Arm Toolchain if: steps.cache-arm-gcc.outputs.cache-hit != 'true' run: | - curl -O -L https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2 - md5sum gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2 + curl -O -L https://developer.arm.com/-/media/Files/downloads/gnu-rm/9-2020q2/gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 + md5sum gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 echo Installing in ${{ runner.temp }}/arm-gcc mkdir -p ${{ runner.temp }}/arm-gcc - tar jvxf gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2 -C ${{ runner.temp }}/arm-gcc --strip-components 1 + tar jvxf gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 -C ${{ runner.temp }}/arm-gcc --strip-components 1 - name: Install dependencies run: | @@ -51,7 +51,7 @@ jobs: for i in ${{ runner.temp }}/arm-gcc/bin/* ; do sudo ln -s /usr/bin/ccache /usr/lib/ccache/$(basename $i); done ccache --set-config=cache_dir="$GITHUB_WORKSPACE" ccache --set-config=cache_dir="$GITHUB_WORKSPACE/.ccache" - ccache --set-config=max_size=2Ti + ccache --set-config=max_size=2Gi ccache -z -s arm-none-eabi-gcc -v | tee log.txt (git status; git log -1 )>> log.txt diff --git a/.github/workflows/windows.yml b/.github/workflows/windows.yml index affd401c7..dec6e6fc8 100644 --- a/.github/workflows/windows.yml +++ b/.github/workflows/windows.yml @@ -11,7 +11,7 @@ jobs: id: cache-arm-gcc uses: actions/cache@v2 env: - cache-name: arm-gcc-10-2020-q4 + cache-name: arm-gcc-9-2020-q2 with: path: ${{ runner.temp }}/arm-gcc key: ${{ runner.os }}-${{ env.cache-name }} @@ -31,10 +31,9 @@ jobs: - name: Install Embedded Arm Toolchain if: steps.cache-arm-gcc.outputs.cache-hit != 'true' run: | - (New-Object System.Net.WebClient).DownloadFile("https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-win32.zip","gcc-arm-none-eabi-10-2020-q4-major-win32.zip"); - echo "Installing gcc-arm-none-eabi-10-2020-q4-major-win32 in ${{ runner.temp }}\arm-gcc"; - Expand-Archive -Path .\gcc-arm-none-eabi-10-2020-q4-major-win32.zip -DestinationPath ${{ runner.temp }} -PassThru; - Rename-Item ${{ runner.temp }}\gcc-arm-none-eabi-10-2020-q4-major ${{ runner.temp }}\arm-gcc; + (New-Object System.Net.WebClient).DownloadFile("https://developer.arm.com/-/media/Files/downloads/gnu-rm/9-2020q2/gcc-arm-none-eabi-9-2020-q2-update-win32.zip","gcc-arm-none-eabi-9-2020-q2-update-win32.zip"); + echo "Installing gcc-arm-none-eabi-9-2020-q2-update-win32 in ${{ runner.temp }}\arm-gcc"; + Expand-Archive -Path .\gcc-arm-none-eabi-9-2020-q2-update-win32.zip -DestinationPath ${{ runner.temp }}\arm-gcc -PassThru; - name: Check Embedded Arm Toolchain run: | From a27ebdec7dfc23682c54f980242820546d910412 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 21 Apr 2021 15:08:06 -0500 Subject: [PATCH 114/617] Fix typo in branch name --- .github/workflows/linux.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/linux.yml b/.github/workflows/linux.yml index 842cb92c7..83a38c775 100644 --- a/.github/workflows/linux.yml +++ b/.github/workflows/linux.yml @@ -2,7 +2,7 @@ name: Build DAPLink (Linux) on: push: branches: - - compilers_experimental + - experimental_compilers workflow_dispatch: jobs: From bd08c8060151b07b8f7951c4d1991c9e1b6215d9 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Thu, 7 Jan 2021 13:14:45 -0600 Subject: [PATCH 115/617] Add shebang to python scripts under ./tools that were missing it. --- tools/copy_release_files.py | 5 +++-- tools/generate_config.py | 1 + tools/make_update_yml.py | 19 ++++++++++--------- tools/offset_update.py | 1 + tools/package_release_files.py | 3 ++- tools/post_build_script.py | 1 + tools/update_yml.py | 3 ++- 7 files changed, 20 insertions(+), 13 deletions(-) mode change 100644 => 100755 tools/copy_release_files.py mode change 100644 => 100755 tools/generate_config.py mode change 100644 => 100755 tools/offset_update.py mode change 100644 => 100755 tools/package_release_files.py mode change 100644 => 100755 tools/update_yml.py diff --git a/tools/copy_release_files.py b/tools/copy_release_files.py old mode 100644 new mode 100755 index 48f8ad188..8e783d144 --- a/tools/copy_release_files.py +++ b/tools/copy_release_files.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python # # DAPLink Interface Firmware # Copyright (c) 2009-2016, ARM Limited, All Rights Reserved @@ -46,7 +47,7 @@ "%s_map.html", ] -TOOL_DIR = { +TOOL_DIR = { 'uvision' : { 'proj_dir': os.path.join('projectfiles', 'uvision') , 'rel_dir' : 'uvision_release', 'build_dir' : 'build' }, 'mbedcli' : { 'proj_dir': 'BUILD' , 'rel_dir' : 'mbedcli_release', 'build_dir' : 'ARM-CUSTOM_PROFILE' }, 'progen_arm' : { 'proj_dir': 'projectfiles/make_armcc' , 'rel_dir' : 'progen_arm_release', 'build_dir' : 'build' }, @@ -124,7 +125,7 @@ def main(): os.mkdir(rel_dir) generate_info_files(rel_dir) - + project_list = os.listdir(proj_dir) for project in project_list: src_dir = os.path.join(proj_dir, project, build_dir) diff --git a/tools/generate_config.py b/tools/generate_config.py old mode 100644 new mode 100755 index deee5b5ff..e13424192 --- a/tools/generate_config.py +++ b/tools/generate_config.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python # # DAPLink Interface Firmware # Copyright (c) 2009-2016, ARM Limited, All Rights Reserved diff --git a/tools/make_update_yml.py b/tools/make_update_yml.py index 9e705d606..bbc2e93a1 100644 --- a/tools/make_update_yml.py +++ b/tools/make_update_yml.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python # # DAPLink Interface Firmware # Copyright (c) 2009-2018, ARM Limited, All Rights Reserved @@ -28,7 +29,7 @@ class TargetList(list): def sort(self, *args, **kwargs): pass -class InstructionList(list): +class InstructionList(list): def sort(self, *args, **kwargs): pass @@ -117,11 +118,11 @@ def yml_object_parser(f, entry, level, tabs): else: f.write('\n') yml_object_parser(f, entry[key], level + 1, tabs); - - elif type(entry) is DefaultList: + + elif type(entry) is DefaultList: for target in entry: - if type(target) is tuple: + if type(target) is tuple: #print target f.write(" " * level * tabs + string_writer(target[0]) + ": "); value = string_writer(target[1]) @@ -134,10 +135,10 @@ def yml_object_parser(f, entry, level, tabs): else: logger.error("Not expecting input type %s %s " % (type(target), str(target))) - elif type(entry) is TargetList: + elif type(entry) is TargetList: #print "found TargetList" for target in entry: - if type(target) is tuple: + if type(target) is tuple: #print target f.write(" " * (level-1) * tabs + string_writer(target[0]) + ": "); value = string_writer(target[1]) @@ -150,10 +151,10 @@ def yml_object_parser(f, entry, level, tabs): else: logger.error("Not expecting input type %s %s " % (type(target), str(target))) - elif type(entry) is InstructionList: - #print "found InstructionList" + elif type(entry) is InstructionList: + #print "found InstructionList" for target in entry: - if type(target) is tuple: + if type(target) is tuple: f.write(" " * level * tabs + string_writer(target[0]) + ": |\n") if type(target[1]) is list: for texts in target[1]: diff --git a/tools/offset_update.py b/tools/offset_update.py old mode 100644 new mode 100755 index 734be1461..cbc3d6037 --- a/tools/offset_update.py +++ b/tools/offset_update.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python # # DAPLink Interface Firmware # Copyright (c) 2009-2016, ARM Limited, All Rights Reserved diff --git a/tools/package_release_files.py b/tools/package_release_files.py old mode 100644 new mode 100755 index 87a51f1e3..7365de0aa --- a/tools/package_release_files.py +++ b/tools/package_release_files.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python # # DAPLink Interface Firmware # Copyright (c) 2009-2016, ARM Limited, All Rights Reserved @@ -119,6 +120,6 @@ def package_release_files(source, dest, version, toolchain, release_info, suppor args = parser.parse_args() print("args", args.source, args.dest, args.version, args.toolchain) - + package_release_files(args.source, args.dest, args.version, args.toolchain, info.PROJECT_RELEASE_INFO, info.SUPPORTED_CONFIGURATIONS) diff --git a/tools/post_build_script.py b/tools/post_build_script.py index 8c4eacea9..96dd6c967 100755 --- a/tools/post_build_script.py +++ b/tools/post_build_script.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python # # DAPLink Interface Firmware # Copyright (c) 2009-2019, ARM Limited, All Rights Reserved diff --git a/tools/update_yml.py b/tools/update_yml.py old mode 100644 new mode 100755 index f136cc83b..eea220ef8 --- a/tools/update_yml.py +++ b/tools/update_yml.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python # # DAPLink Interface Firmware # Copyright (c) 2009-2018, ARM Limited, All Rights Reserved @@ -23,7 +24,7 @@ class TargetList(list): def sort(self, *args, **kwargs): pass -class InstructionList(unicode): +class InstructionList(unicode): def sort(self, *args, **kwargs): pass From a3860b1ff9bae0115521b5e67d204311d62bb527 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 21 Apr 2021 23:58:25 -0500 Subject: [PATCH 116/617] Add bootloader firmwares to build artifacts --- .github/workflows/linux.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.github/workflows/linux.yml b/.github/workflows/linux.yml index 83a38c775..6eb6d9b1e 100644 --- a/.github/workflows/linux.yml +++ b/.github/workflows/linux.yml @@ -69,11 +69,14 @@ jobs: export PATH="/usr/lib/ccache:${{ runner.temp }}/arm-gcc/bin/:/home/runner/.local/bin:$PATH" python tools/progen_compile.py --release --parallel -v -v --ignore-failures (ls -lR firmware_*; ccache -s; arm-none-eabi-gcc -v) | tee log.txt + mkdir bootloaders + cp projectfiles/make_gcc_arm/*_bl/build/*_crc.bin bootloaders - name: Upload test artifacts uses: actions/upload-artifact@v2 with: name: firmware-dev-${{github.run_number}} path: | + bootloaders/* firmware*/* !firmware*/*.zip From 2ec5a958d3bd14d3e4a35d08fc5317a0de8a39b7 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Fri, 11 Dec 2020 17:51:16 -0600 Subject: [PATCH 117/617] Define flash HAL API for testing if flash is readable before accessing. - Add weak flash_is_readable() to flash_hal.*. The default implementation just checks if the address is valid. - Use the new API in info.c to verify the flash pages containing the bootloader/interface info fields are accessible. - bootloader_update.c checks readability. - The cfgrom support checks readability. Plus changed to use the flash HAL API. --- source/daplink/flash_hal.c | 11 ++++- source/daplink/info.c | 43 ++++++++++++-------- source/daplink/interface/bootloader_update.c | 14 ++++--- source/daplink/settings/settings_rom.c | 40 +++++++++--------- source/hic_hal/flash_hal.h | 16 +++++++- 5 files changed, 81 insertions(+), 43 deletions(-) diff --git a/source/daplink/flash_hal.c b/source/daplink/flash_hal.c index b18434380..35e3b76ae 100644 --- a/source/daplink/flash_hal.c +++ b/source/daplink/flash_hal.c @@ -3,7 +3,7 @@ * @brief Implementation of flash_hal.h * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2020, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -21,6 +21,7 @@ #include "flash_hal.h" #include "cortex_m.h" +#include "daplink_addr.h" uint32_t flash_erase_sector(uint32_t addr) { @@ -41,3 +42,11 @@ uint32_t flash_program_page(uint32_t adr, uint32_t sz, uint8_t *buf) cortex_int_restore(state); return retval; } + +// Default implementation. May be overridden by HIC support. +__WEAK bool flash_is_readable(uint32_t addr, uint32_t length) +{ + uint32_t end_addr = addr + length - 1; + return (addr >= DAPLINK_ROM_START && addr < (DAPLINK_ROM_START + DAPLINK_ROM_SIZE)) + && (end_addr >= DAPLINK_ROM_START && end_addr < (DAPLINK_ROM_START + DAPLINK_ROM_SIZE)); +} diff --git a/source/daplink/info.c b/source/daplink/info.c index c0dd57d25..5be10d8e7 100644 --- a/source/daplink/info.c +++ b/source/daplink/info.c @@ -28,6 +28,7 @@ #include "daplink.h" #include "settings.h" #include "target_board.h" +#include "flash_hal.h" static char hex_to_ascii(uint8_t x) { @@ -209,40 +210,46 @@ void info_set_uuid_target(uint32_t *uuid_data) bool info_get_bootloader_present(void) { - bool present = true; - if (0 == DAPLINK_ROM_BL_SIZE) { - present = false; + return false; + } + + // Check whether we can read the bootloader info. + if (!flash_is_readable((uint32_t)info_bl, sizeof(daplink_info_t))) { + return false; } if (DAPLINK_BUILD_KEY_BL != info_bl->build_key) { - present = false; + return false; } if (DAPLINK_HIC_ID != info_bl->hic_id) { - present = false; + return false; } - return present; + return true; } bool info_get_interface_present(void) { - bool present = true; - if (0 == DAPLINK_ROM_IF_SIZE) { - present = false; + return false; + } + + // Check whether we can read the interface info. + if (!flash_is_readable((uint32_t)info_if, sizeof(daplink_info_t))) { + return false; } if (DAPLINK_BUILD_KEY_IF != info_if->build_key) { - present = false; + return false; } if (DAPLINK_HIC_ID != info_if->hic_id) { - present = false; + return false; } - return present; + return true; } bool info_get_config_admin_present(void) @@ -285,19 +292,23 @@ void info_crc_compute() crc_config_user = 0; // Compute the CRCs of regions that exist - if (DAPLINK_ROM_BL_SIZE > 0) { + if ((DAPLINK_ROM_BL_SIZE > 0) + && flash_is_readable(DAPLINK_ROM_BL_START, DAPLINK_ROM_BL_SIZE - 4)) { crc_bootloader = crc32((void *)DAPLINK_ROM_BL_START, DAPLINK_ROM_BL_SIZE - 4); } - if (DAPLINK_ROM_IF_SIZE > 0) { + if ((DAPLINK_ROM_IF_SIZE > 0) + && flash_is_readable(DAPLINK_ROM_IF_START, DAPLINK_ROM_IF_SIZE - 4)) { crc_interface = crc32((void *)DAPLINK_ROM_IF_START, DAPLINK_ROM_IF_SIZE - 4); } - if (DAPLINK_ROM_CONFIG_ADMIN_SIZE > 0) { + if ((DAPLINK_ROM_CONFIG_ADMIN_SIZE > 0) + && flash_is_readable(DAPLINK_ROM_CONFIG_ADMIN_START, DAPLINK_ROM_CONFIG_ADMIN_SIZE)) { crc_config_admin = crc32((void *)DAPLINK_ROM_CONFIG_ADMIN_START, DAPLINK_ROM_CONFIG_ADMIN_SIZE); } - if (DAPLINK_ROM_CONFIG_USER_SIZE > 0) { + if ((DAPLINK_ROM_CONFIG_USER_SIZE > 0) + && flash_is_readable(DAPLINK_ROM_CONFIG_USER_START, DAPLINK_ROM_CONFIG_USER_SIZE)) { crc_config_user = crc32((void *)DAPLINK_ROM_CONFIG_USER_START, DAPLINK_ROM_CONFIG_USER_SIZE); } } diff --git a/source/daplink/interface/bootloader_update.c b/source/daplink/interface/bootloader_update.c index 2af91401b..66355f94c 100644 --- a/source/daplink/interface/bootloader_update.c +++ b/source/daplink/interface/bootloader_update.c @@ -3,7 +3,7 @@ * @brief Logic to perform a bootloader update when enabled * * DAPLink Interface Firmware - * Copyright (c) 2016-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2016-2020 Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -28,6 +28,7 @@ #include "info.h" #include "daplink.h" #include "crc.h" +#include "flash_hal.h" #if defined(__CC_ARM) // Supress the warning 'null argument provided for parameter marked with attribute "nonnull"' @@ -50,11 +51,14 @@ static bool interface_image_valid() { - uint32_t stored_crc; + uint32_t stored_crc = 0; uint32_t computed_crc; - - stored_crc = *(uint32_t *)(DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE - 4); - computed_crc = crc32((void *)DAPLINK_ROM_IF_START, DAPLINK_ROM_IF_SIZE - 4); + + if (flash_is_readable(DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE - 4, 4)) { + stored_crc = *(uint32_t *)(DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE - 4); + } + + computed_crc = info_get_crc_interface(); return computed_crc == stored_crc; } diff --git a/source/daplink/settings/settings_rom.c b/source/daplink/settings/settings_rom.c index d1481d23e..be01a5ba9 100644 --- a/source/daplink/settings/settings_rom.c +++ b/source/daplink/settings/settings_rom.c @@ -3,7 +3,7 @@ * @brief Implementation of settings.h * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2020 Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -25,7 +25,7 @@ #include "target_config.h" #include "compiler.h" #include "cortex_m.h" -#include "FlashPrg.h" +#include "flash_hal.h" // 'kvld' in hex - key valid #define CFG_KEY 0x6b766c64 @@ -76,12 +76,14 @@ static const cfg_setting_t config_default = { .overflow_detect = 1, }; -// Buffer for data to flash -static uint32_t write_buffer[SECTOR_BUFFER_SIZE / 4]; - // Check if the configuration in flash needs to be updated static bool config_needs_update() { + // Update if cfgrom cannot be read (needs to be programmed). + if (!flash_is_readable((uint32_t)&config_rom, sizeof(config_rom))) { + return true; + } + // Update if the key is invalid if (CFG_KEY != config_rom.key) { return true; @@ -103,23 +105,20 @@ static void program_cfg(cfg_setting_t *new_cfg) { uint32_t status; uint32_t addr; - cortex_int_state_t state; - addr = (uint32_t)&config_rom; - state = cortex_int_get_and_disable(); - status = EraseSector(addr); - cortex_int_restore(state); + addr = (uint32_t)&config_rom; + status = flash_erase_sector(addr); if (status != 0) { return; } + // Buffer for data to flash + uint8_t write_buffer[SECTOR_BUFFER_SIZE] __ALIGNED(4); + memset(write_buffer, 0xFF, sizeof(write_buffer)); memcpy(write_buffer, new_cfg, sizeof(cfg_setting_t)); - state = cortex_int_get_and_disable(); - status = ProgramPage(addr, sizeof(write_buffer), write_buffer); - cortex_int_restore(state); - - if (0 != status) { + status = flash_program_page(addr, sizeof(write_buffer), write_buffer); + if (status != 0) { return; } } @@ -127,13 +126,16 @@ static void program_cfg(cfg_setting_t *new_cfg) void config_rom_init() { Init(0, 0, 0); + // Fill in the ram copy with the defaults memcpy(&config_rom_copy, &config_default, sizeof(config_rom_copy)); - // Read settings from flash if the key is valid - if (CFG_KEY == config_rom.key) { - uint32_t size = MIN(config_rom.size, sizeof(config_rom)); - memcpy(&config_rom_copy, (void *)&config_rom, size); + if (flash_is_readable((uint32_t)&config_rom, sizeof(config_rom))) { + // Read settings from flash if the key is valid + if (CFG_KEY == config_rom.key) { + uint32_t size = MIN(config_rom.size, sizeof(config_rom)); + memcpy(&config_rom_copy, (void *)&config_rom, size); + } } // Fill in special values diff --git a/source/hic_hal/flash_hal.h b/source/hic_hal/flash_hal.h index 50d42ec3e..f4fc5949a 100644 --- a/source/hic_hal/flash_hal.h +++ b/source/hic_hal/flash_hal.h @@ -1,9 +1,9 @@ /** * @file flash_hal.h - * @brief + * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2020, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -22,6 +22,7 @@ #ifndef FLASH_HAL_H #define FLASH_HAL_H +#include #include "FlashPrg.h" #ifdef __cplusplus @@ -31,6 +32,17 @@ extern "C" { uint32_t flash_program_page(uint32_t adr, uint32_t sz, uint8_t *buf); uint32_t flash_erase_sector(uint32_t addr); +/*! + * @brief Test whether the specified flash address range can be read from. + * + * The default implementation returns true if the given address range is within the bounds + * of the HIC's internal flash memory (defined by DAPLINK_ROM_START and DAPLINK_ROM_SIZE). + * + * @retval true All pages within the specified range are readble. + * @retval false At least one page within the specified range cannot be read. + */ +bool flash_is_readable(uint32_t addr, uint32_t length); + #ifdef __cplusplus } #endif From 5aaa46494d4c4516554a4355f3274724c8fdf2da Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sun, 20 Dec 2020 16:02:06 -0600 Subject: [PATCH 118/617] CMSIS-DAP: prepare for custom SWD implementation. - Saving nominal requested clock frequency in DAP_Data. - Made SWD bit banging functions weak. --- source/daplink/cmsis-dap/DAP.c | 3 +++ source/daplink/cmsis-dap/DAP.h | 1 + source/daplink/cmsis-dap/SW_DP.c | 6 +++--- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/source/daplink/cmsis-dap/DAP.c b/source/daplink/cmsis-dap/DAP.c index 27dd62419..d94bcd201 100644 --- a/source/daplink/cmsis-dap/DAP.c +++ b/source/daplink/cmsis-dap/DAP.c @@ -388,6 +388,8 @@ static uint32_t DAP_SWJ_Clock(const uint8_t *request, uint8_t *response) { return ((4U << 16) | 1U); } + DAP_Data.nominal_clock = clock; + if (clock >= MAX_SWJ_CLOCK(DELAY_FAST_CYCLES)) { DAP_Data.fast_clock = 1U; DAP_Data.clock_delay = 1U; @@ -1777,6 +1779,7 @@ void DAP_Setup(void) { DAP_Data.debug_port = 0U; DAP_Data.fast_clock = 0U; DAP_Data.clock_delay = CLOCK_DELAY(DAP_DEFAULT_SWJ_CLOCK); + DAP_Data.nominal_clock = DAP_DEFAULT_SWJ_CLOCK; DAP_Data.transfer.idle_cycles = 0U; DAP_Data.transfer.retry_count = 100U; DAP_Data.transfer.match_retry = 0U; diff --git a/source/daplink/cmsis-dap/DAP.h b/source/daplink/cmsis-dap/DAP.h index 7f646f170..02a38ca3d 100644 --- a/source/daplink/cmsis-dap/DAP.h +++ b/source/daplink/cmsis-dap/DAP.h @@ -211,6 +211,7 @@ typedef struct { uint8_t fast_clock; // Fast Clock Flag uint8_t padding[2]; uint32_t clock_delay; // Clock Delay + uint32_t nominal_clock; // Nominal requested clock frequency in Hertz. uint32_t timestamp; // Last captured Timestamp struct { // Transfer Configuration uint8_t idle_cycles; // Idle cycles after transfer diff --git a/source/daplink/cmsis-dap/SW_DP.c b/source/daplink/cmsis-dap/SW_DP.c index 59d22d934..7ac13da19 100644 --- a/source/daplink/cmsis-dap/SW_DP.c +++ b/source/daplink/cmsis-dap/SW_DP.c @@ -70,7 +70,7 @@ // data: pointer to sequence bit data // return: none #if ((DAP_SWD != 0) || (DAP_JTAG != 0)) -void SWJ_Sequence (uint32_t count, const uint8_t *data) { +__WEAK void SWJ_Sequence (uint32_t count, const uint8_t *data) { uint32_t val; uint32_t n; @@ -100,7 +100,7 @@ void SWJ_Sequence (uint32_t count, const uint8_t *data) { // swdi: pointer to SWDIO captured data // return: none #if (DAP_SWD != 0) -void SWD_Sequence (uint32_t info, const uint8_t *swdo, uint8_t *swdi) { +__WEAK void SWD_Sequence (uint32_t info, const uint8_t *swdo, uint8_t *swdi) { uint32_t val; uint32_t bit; uint32_t n, k; @@ -282,7 +282,7 @@ SWD_TransferFunction(Slow) // request: A[3:2] RnW APnDP // data: DATA[31:0] // return: ACK[2:0] -uint8_t SWD_Transfer(uint32_t request, uint32_t *data) { +__WEAK uint8_t SWD_Transfer(uint32_t request, uint32_t *data) { if (DAP_Data.fast_clock) { return SWD_TransferFast(request, data); } else { From 985bfe7482bb8deb86acdd3388be150fab5345e0 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Mon, 6 Jan 2020 16:04:35 -0600 Subject: [PATCH 119/617] Add LPC55xx family ID. --- source/board/hani_iot.c | 2 +- source/board/lpc55S69xpresso.c | 2 +- source/family/nxp/lpc55S6X/target_reset.c | 2 +- source/target/target_family.c | 2 ++ source/target/target_family.h | 1 + 5 files changed, 6 insertions(+), 3 deletions(-) diff --git a/source/board/hani_iot.c b/source/board/hani_iot.c index 83bfe5132..d353d18a3 100644 --- a/source/board/hani_iot.c +++ b/source/board/hani_iot.c @@ -25,7 +25,7 @@ const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "0360", - .family_id = VENDOR_TO_FAMILY(kNXP_VendorID, 0), //ID not maching the predefined family ids + .family_id = kNXP_LPC55xx_FamilyID, //ID not maching the predefined family ids .flags = kEnablePageErase, .daplink_url_name = "PRODINFOHTM", .daplink_drive_name = "HANI_IOT", diff --git a/source/board/lpc55S69xpresso.c b/source/board/lpc55S69xpresso.c index b9a589064..a743721e6 100644 --- a/source/board/lpc55S69xpresso.c +++ b/source/board/lpc55S69xpresso.c @@ -25,7 +25,7 @@ const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "0236", - .family_id = VENDOR_TO_FAMILY(kNXP_VendorID, 0), //ID not maching the predefined family ids + .family_id = kNXP_LPC55xx_FamilyID, .flags = kEnablePageErase, .daplink_url_name = "PRODINFOHTM", .daplink_drive_name = "LPC55S69", diff --git a/source/family/nxp/lpc55S6X/target_reset.c b/source/family/nxp/lpc55S6X/target_reset.c index fe0ebe94e..fb77aa1a5 100644 --- a/source/family/nxp/lpc55S6X/target_reset.c +++ b/source/family/nxp/lpc55S6X/target_reset.c @@ -106,7 +106,7 @@ static uint8_t lpc55s6x_target_set_state(target_state_t state) } const target_family_descriptor_t g_target_family_lpc55S6X = { - .family_id = VENDOR_TO_FAMILY(kNXP_VendorID, 0), //ID not maching the predefined family ids + .family_id = kNXP_LPC55xx_FamilyID, //ID not maching the predefined family ids .target_set_state = lpc55s6x_target_set_state, }; diff --git a/source/target/target_family.c b/source/target/target_family.c index 4eb110629..54c919642 100644 --- a/source/target/target_family.c +++ b/source/target/target_family.c @@ -49,6 +49,7 @@ extern __WEAK const target_family_descriptor_t g_nxp_kinetis_lseries; extern __WEAK const target_family_descriptor_t g_nxp_kinetis_k32w_series; extern __WEAK const target_family_descriptor_t g_nxp_mimxrt; extern __WEAK const target_family_descriptor_t g_nxp_rapid_iot; +extern __WEAK const target_family_descriptor_t g_nxp_lpc55xx_series; extern __WEAK const target_family_descriptor_t g_nordic_nrf51; extern __WEAK const target_family_descriptor_t g_nordic_nrf52; extern __WEAK const target_family_descriptor_t g_realtek_rtl8195am; @@ -78,6 +79,7 @@ const target_family_descriptor_t *g_families[] = { &g_nxp_kinetis_kseries, &g_nxp_kinetis_lseries, &g_nxp_kinetis_k32w_series, + &g_nxp_lpc55xx_series, &g_nxp_mimxrt, &g_nxp_rapid_iot, &g_nordic_nrf51, diff --git a/source/target/target_family.h b/source/target/target_family.h index 80b47b265..c780c63a2 100644 --- a/source/target/target_family.h +++ b/source/target/target_family.h @@ -96,6 +96,7 @@ typedef enum _family_id { kNXP_Mimxrt_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 3), kNXP_RapidIot_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 4), kNXP_KinetisK32W_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 5), + kNXP_LPC55xx_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 6), kNordic_Nrf51_FamilyID = VENDOR_TO_FAMILY(kNordic_VendorID, 1), kNordic_Nrf52_FamilyID = VENDOR_TO_FAMILY(kNordic_VendorID, 2), kRealtek_Rtl8195am_FamilyID = VENDOR_TO_FAMILY(kRealtek_VendorID, 1), From b253a38b40ff4e9221a3fecf169b7e8e1330d01a Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Mon, 28 Oct 2019 16:35:21 -0500 Subject: [PATCH 120/617] LPC55xx: started adding HIC files. --- projects.yaml | 12 + records/board/lpc55s69_bl.yaml | 4 + records/hic_hal/lpc55s69.yaml | 72 + records/tools/gcc_arm.yaml | 2 - source/board/lpc55s69_bl.c | 64 + source/daplink/daplink.h | 2 +- source/hic_hal/nxp/lpc55xx/DAP_config.h | 519 + source/hic_hal/nxp/lpc55xx/Driver_Common.h | 69 + source/hic_hal/nxp/lpc55xx/Driver_USART.h | 341 + source/hic_hal/nxp/lpc55xx/FlashPrg.c | 156 + source/hic_hal/nxp/lpc55xx/IO_Config.h | 207 + .../lpc55xx/LPC55S69/LPC55S69_cm33_core0.h | 23602 ++++++++++++++++ .../LPC55S69/LPC55S69_cm33_core0_features.h | 388 + .../nxp/lpc55xx/LPC55S69/drivers/fsl_clock.c | 2031 ++ .../nxp/lpc55xx/LPC55S69/drivers/fsl_clock.h | 1240 + .../nxp/lpc55xx/LPC55S69/drivers/fsl_common.c | 280 + .../nxp/lpc55xx/LPC55S69/drivers/fsl_common.h | 672 + .../lpc55xx/LPC55S69/drivers/fsl_flexcomm.c | 339 + .../lpc55xx/LPC55S69/drivers/fsl_flexcomm.h | 64 + .../nxp/lpc55xx/LPC55S69/drivers/fsl_gpio.c | 302 + .../nxp/lpc55xx/LPC55S69/drivers/fsl_gpio.h | 364 + .../nxp/lpc55xx/LPC55S69/drivers/fsl_iap.c | 600 + .../nxp/lpc55xx/LPC55S69/drivers/fsl_iap.h | 528 + .../lpc55xx/LPC55S69/drivers/fsl_iap_ffr.h | 388 + .../lpc55xx/LPC55S69/drivers/fsl_iap_kbp.h | 219 + .../drivers/fsl_iap_skboot_authenticate.h | 73 + .../nxp/lpc55xx/LPC55S69/drivers/fsl_iocon.h | 288 + .../nxp/lpc55xx/LPC55S69/drivers/fsl_power.c | 19 + .../nxp/lpc55xx/LPC55S69/drivers/fsl_power.h | 562 + .../nxp/lpc55xx/LPC55S69/drivers/fsl_reset.c | 99 + .../nxp/lpc55xx/LPC55S69/drivers/fsl_reset.h | 281 + .../nxp/lpc55xx/LPC55S69/drivers/fsl_usart.c | 1099 + .../nxp/lpc55xx/LPC55S69/drivers/fsl_usart.h | 750 + .../lpc55xx/LPC55S69/fsl_device_registers.h | 44 + .../LPC55S69/system_LPC55S69_cm33_core0.c | 379 + .../LPC55S69/system_LPC55S69_cm33_core0.h | 112 + source/hic_hal/nxp/lpc55xx/RTE_Device.h | 32 + .../armcc/keil_lib_power_cm33_core0.lib | Bin 0 -> 10560 bytes source/hic_hal/nxp/lpc55xx/daplink_addr.h | 82 + source/hic_hal/nxp/lpc55xx/fsl_usb.h | 134 + .../nxp/lpc55xx/gcc/libpower_hardabi.a | Bin 0 -> 62336 bytes source/hic_hal/nxp/lpc55xx/gcc/lpc55xx.ld | 231 + .../lpc55xx/gcc/startup_LPC55S69_cm33_core0.S | 888 + source/hic_hal/nxp/lpc55xx/gpio.c | 159 + source/hic_hal/nxp/lpc55xx/hic_init.c | 163 + source/hic_hal/nxp/lpc55xx/hic_init.h | 35 + source/hic_hal/nxp/lpc55xx/read_uid.c | 38 + source/hic_hal/nxp/lpc55xx/uart.c | 257 + source/hic_hal/nxp/lpc55xx/usb_buf.h | 29 + source/hic_hal/nxp/lpc55xx/usb_config.c | 561 + source/hic_hal/nxp/lpc55xx/usb_misc.h | 496 + source/hic_hal/nxp/lpc55xx/usb_phy.c | 278 + source/hic_hal/nxp/lpc55xx/usb_phy.h | 105 + source/hic_hal/nxp/lpc55xx/usb_spec.h | 299 + source/hic_hal/nxp/lpc55xx/usbd_LPC55xx.c | 873 + 55 files changed, 40828 insertions(+), 3 deletions(-) create mode 100644 records/board/lpc55s69_bl.yaml create mode 100644 records/hic_hal/lpc55s69.yaml create mode 100644 source/board/lpc55s69_bl.c create mode 100644 source/hic_hal/nxp/lpc55xx/DAP_config.h create mode 100644 source/hic_hal/nxp/lpc55xx/Driver_Common.h create mode 100644 source/hic_hal/nxp/lpc55xx/Driver_USART.h create mode 100644 source/hic_hal/nxp/lpc55xx/FlashPrg.c create mode 100644 source/hic_hal/nxp/lpc55xx/IO_Config.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/LPC55S69_cm33_core0.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/LPC55S69_cm33_core0_features.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_clock.c create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_clock.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_common.c create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_common.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_flexcomm.c create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_flexcomm.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_gpio.c create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_gpio.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iap.c create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iap.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iap_ffr.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iap_kbp.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iap_skboot_authenticate.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iocon.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_power.c create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_power.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_reset.c create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_reset.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart.c create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/fsl_device_registers.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/system_LPC55S69_cm33_core0.c create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/system_LPC55S69_cm33_core0.h create mode 100644 source/hic_hal/nxp/lpc55xx/RTE_Device.h create mode 100644 source/hic_hal/nxp/lpc55xx/armcc/keil_lib_power_cm33_core0.lib create mode 100644 source/hic_hal/nxp/lpc55xx/daplink_addr.h create mode 100644 source/hic_hal/nxp/lpc55xx/fsl_usb.h create mode 100644 source/hic_hal/nxp/lpc55xx/gcc/libpower_hardabi.a create mode 100644 source/hic_hal/nxp/lpc55xx/gcc/lpc55xx.ld create mode 100644 source/hic_hal/nxp/lpc55xx/gcc/startup_LPC55S69_cm33_core0.S create mode 100644 source/hic_hal/nxp/lpc55xx/gpio.c create mode 100644 source/hic_hal/nxp/lpc55xx/hic_init.c create mode 100644 source/hic_hal/nxp/lpc55xx/hic_init.h create mode 100644 source/hic_hal/nxp/lpc55xx/read_uid.c create mode 100644 source/hic_hal/nxp/lpc55xx/uart.c create mode 100644 source/hic_hal/nxp/lpc55xx/usb_buf.h create mode 100644 source/hic_hal/nxp/lpc55xx/usb_config.c create mode 100644 source/hic_hal/nxp/lpc55xx/usb_misc.h create mode 100644 source/hic_hal/nxp/lpc55xx/usb_phy.c create mode 100644 source/hic_hal/nxp/lpc55xx/usb_phy.h create mode 100644 source/hic_hal/nxp/lpc55xx/usb_spec.h create mode 100644 source/hic_hal/nxp/lpc55xx/usbd_LPC55xx.c diff --git a/projects.yaml b/projects.yaml index ffde11799..2d49fad2f 100644 --- a/projects.yaml +++ b/projects.yaml @@ -62,6 +62,10 @@ module: - records/rtos/rtos-cm3.yaml - records/hic_hal/lpc4322.yaml - records/usb/usb-bulk.yaml + hic_lpc55s69: &module_hic_lpc55s69 + - records/rtos/rtos-cm3.yaml + - records/hic_hal/lpc55s69.yaml + - records/usb/usb-bulk.yaml hic_sam3u2c: &module_hic_sam3u2c - records/rtos/rtos-cm3.yaml - records/hic_hal/sam3u2c.yaml @@ -124,6 +128,14 @@ projects: - *module_if - *module_hic_lpc4322 - records/family/all_family.yaml + lpc55s69_bl: + - *module_bl + - records/hic_hal/lpc55s69.yaml + - records/board/lpc55s69_bl.yaml + lpc55s69_if: + - *module_if + - *module_hic_lpc55s69 + - records/family/all_family.yaml max32620_bl: - *module_bl - records/hic_hal/max32620.yaml diff --git a/records/board/lpc55s69_bl.yaml b/records/board/lpc55s69_bl.yaml new file mode 100644 index 000000000..c32f125ea --- /dev/null +++ b/records/board/lpc55s69_bl.yaml @@ -0,0 +1,4 @@ +common: + sources: + board: + - source/board/lpc55s69_bl.c diff --git a/records/hic_hal/lpc55s69.yaml b/records/hic_hal/lpc55s69.yaml new file mode 100644 index 000000000..e0922a78d --- /dev/null +++ b/records/hic_hal/lpc55s69.yaml @@ -0,0 +1,72 @@ +common: + target: + - cortex-m33 + core: + - Cortex-M33 + macros: + - INTERFACE_LPC55XX + - CPU_LPC55S69JBD64_cm33_core0 + - DAPLINK_HIC_ID=0x4C504355 # DAPLINK_HIC_ID_LPC55XX + - OS_CLOCK=150000000 + includes: + - source/hic_hal/nxp/lpc55xx + - source/hic_hal/nxp/lpc55xx/LPC55S69 + - source/hic_hal/nxp/lpc55xx/LPC55S69/drivers + - projectfiles/uvision/lpc55xx_bl/build + sources: + hic_hal: + - source/hic_hal/nxp/lpc55xx + - source/hic_hal/nxp/lpc55xx/LPC55S69 + - source/hic_hal/nxp/lpc55xx/LPC55S69/drivers + +tool_specific: + uvision: + misc: + ld_flags: + - --predefine="-I../../../source/hic_hal/nxp/lpc55xx" + c_flags: + - --no_unaligned_access + - --diag_suppress=66 # disable warning about enums not fitting in signed 32-bit + cxx_flags: + - --no_unaligned_access + asm_flags: + - --no_unaligned_access + sources: + hic_hal: + - source/hic_hal/nxp/lpc55xx/armcc + - source/hic_hal/nxp/lpc55xx/LPC55S69/armcc/keil_lib_power_cm33_core0.lib + make_armcc: + misc: + ld_flags: + - --predefine="-Isource/hic_hal/nxp/lpc55xx" + c_flags: + - --no_unaligned_access + - --diag_suppress=66 # disable warning about enums not fitting in signed 32-bit + cxx_flags: + - --no_unaligned_access + asm_flags: + - --no_unaligned_access + includes: + - projectfiles/make_armcc/lpc55xx_bl/build + sources: + hic_hal: + - source/hic_hal/nxp/lpc55xx/armcc + - source/hic_hal/nxp/lpc55xx/LPC55S69/armcc/keil_lib_power_cm33_core0.lib + make_gcc_arm: + misc: + c_flags: + - -march=armv8-m.main+fp+dsp + - -mfloat-abi=hard + - -mfpu=fpv5-sp-d16 + ld_flags: + - -march=armv8-m.main+fp+dsp + - -mfloat-abi=hard + - -mfpu=fpv5-sp-d16 + linker_file: + - source/hic_hal/nxp/lpc55xx/gcc/lpc55xx.ld + includes: + - source/hic_hal/nxp/lpc55xx/gcc + sources: + hic_hal: + - source/hic_hal/nxp/lpc55xx/gcc + - source/hic_hal/nxp/lpc55xx/LPC55S69/gcc/libpower_hardabi.a diff --git a/records/tools/gcc_arm.yaml b/records/tools/gcc_arm.yaml index cdc189fc9..845767e52 100644 --- a/records/tools/gcc_arm.yaml +++ b/records/tools/gcc_arm.yaml @@ -1,7 +1,5 @@ tool_specific: gcc_arm: - mcu: - - cortex-m0 macros: - linker_file: diff --git a/source/board/lpc55s69_bl.c b/source/board/lpc55s69_bl.c new file mode 100644 index 000000000..7e474424c --- /dev/null +++ b/source/board/lpc55s69_bl.c @@ -0,0 +1,64 @@ +/** + * @file lpc55s69_bl.c + * @brief board ID and meta-data for the hardware interface circuit (HIC) based on the NXP LPC55S69 + * + * DAPLink Interface Firmware + * Copyright (c) 2019-2020, Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_config.h" +#include "daplink_addr.h" +#include "compiler.h" +#include "target_board.h" +#include "target_family.h" + +// Warning - changing the interface start will break backwards compatibility +COMPILER_ASSERT(DAPLINK_ROM_IF_START == (DAPLINK_ROM_START + KB(64))); + +/** +* List of start and size for each size of flash sector +* The size will apply to all sectors between the listed address and the next address +* in the list. +* The last pair in the list will have sectors starting at that address and ending +* at address start + size. +*/ +static const sector_info_t sectors_info[] = { + {DAPLINK_ROM_IF_START, DAPLINK_SECTOR_SIZE}, + }; + +// lpc55s69 target information +target_cfg_t target_device = { + .sectors_info = sectors_info, + .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), + .flash_regions[0].start = DAPLINK_ROM_IF_START, + .flash_regions[0].end = DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE, + .flash_regions[0].flags = kRegionIsDefault, + .ram_regions[0].start = 0x30000000, + .ram_regions[0].end = 0x30040000, + /* .flash_algo not needed for bootloader */ +}; + +//bootloader has no family +const target_family_descriptor_t *g_target_family = NULL; + +const board_info_t g_board_info = { + .info_version = kBoardInfoVersion, + .board_id = "0000", + .daplink_url_name = "HELP_FAQHTM", + .daplink_drive_name = "BOOTLOADER", + .daplink_target_url = "https://mbed.com/daplink", + .target_cfg = &target_device, +}; diff --git a/source/daplink/daplink.h b/source/daplink/daplink.h index 05ef8e333..daf330a0d 100644 --- a/source/daplink/daplink.h +++ b/source/daplink/daplink.h @@ -66,7 +66,7 @@ COMPILER_ASSERT(DAPLINK_RAM_SHARED_START + DAPLINK_RAM_SHARED_SIZE == DAPLINK_RA #define DAPLINK_HIC_ID_KL27Z 0x9796990B #define DAPLINK_HIC_ID_LPC54606 0x9796990C // reserving for future use #define DAPLINK_HIC_ID_STM32F723IE 0x9796990D // reserving for future use -#define DAPLINK_HIC_ID_LPC55S69 0x97969920 // reserving for future use +#define DAPLINK_HIC_ID_LPC55XX 0x4C504355 // 'LPC\x55' #define DAPLINK_HIC_ID_M48SSIDAE 0x97969921 #define DAPLINK_HIC_ID_PSOC5 0x2E127069 //@} diff --git a/source/hic_hal/nxp/lpc55xx/DAP_config.h b/source/hic_hal/nxp/lpc55xx/DAP_config.h new file mode 100644 index 000000000..24a5511f3 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/DAP_config.h @@ -0,0 +1,519 @@ +/** + * @file DAP_config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2020 Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DAP_CONFIG_H__ +#define __DAP_CONFIG_H__ + +#include "IO_Config.h" + +//************************************************************************************************** +/** +\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information +\ingroup DAP_ConfigIO_gr +@{ +Provides definitions about the hardware and configuration of the Debug Unit. + +This information includes: + - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. + - Debug Unit communication packet size. + - Debug Access Port communication mode (JTAG or SWD). + - Optional information about a connected Target Device (for Evaluation Boards). +*/ + +#include "device.h" // Debug Unit Cortex-M Processor Header File + +/// Processor Clock of the Cortex-M MCU used in the Debug Unit. +/// This value is used to calculate the SWD/JTAG clock speed. +#define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz + +/// Number of processor cycles for I/O Port write operations. +/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O +/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors +/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses +/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be +/// required. +#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0 + +/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available + +/// Indicate that JTAG communication mode is available at the Debug Port. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available. + +/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port. +/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255. +#define DAP_JTAG_DEV_CNT 4 ///< Maximum number of JTAG devices on scan chain + +/// Default communication mode on the Debug Access Port. +/// Used for the command \ref DAP_Connect when Port Default mode is selected. +#define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG. + +/// Default communication speed on the Debug Access Port for SWD and JTAG mode. +/// Used to initialize the default SWD/JTAG clock frequency. +/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting. +#define DAP_DEFAULT_SWJ_CLOCK 4000000U ///< Default SWD/JTAG clock frequency in Hz. + +/// Maximum Package Size for Command and Response data. +/// This configuration settings is used to optimized the communication performance with the +/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB. +#ifndef HID_ENDPOINT //HID end points currently set limits to 64 +#define DAP_PACKET_SIZE 512 ///< USB: 64 = Full-Speed, 512 = High-Speed. +#else +#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 512 = High-Speed. +#endif + +/// Maximum Package Buffers for Command and Response data. +/// This configuration settings is used to optimized the communication performance with the +/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the +/// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB. +#define DAP_PACKET_COUNT 4U ///< Buffers: 64 = Full-Speed, 4 = High-Speed. + +/// Indicate that UART Serial Wire Output (SWO) trace is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available + +/// Maximum SWO UART Baudrate +#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz + +/// Indicate that Manchester Serial Wire Output (SWO) trace is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available + +/// SWO Trace Buffer Size. +#define SWO_BUFFER_SIZE 8192U ///< SWO Trace Buffer Size in bytes (must be 2^n) + +/// SWO Streaming Trace. +#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available. + +/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. +#define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported). + +#define SWO_USART_PORT 3 ///< FC3 is used for the SWO UART. + + +/// Debug Unit is connected to fixed Target Device. +/// The Debug Unit may be part of an evaluation board and always connected to a fixed +/// known device. In this case a Device Vendor and Device Name string is stored which +/// may be used by the debugger or IDE to configure device parameters. +#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown; + +#if TARGET_DEVICE_FIXED +#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor +#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device +#endif + +///@} + +//************************************************************************************************** +/** +\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access +\ingroup DAP_ConfigIO_gr +@{ + +Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode +and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug +interface of a device. The following I/O Pins are provided: + +JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode +---------------------------- | -------------------- | --------------------------------------------- +TCK: Test Clock | SWCLK: Clock | Output Push/Pull +TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data) +TDI: Test Data Input | | Output Push/Pull +TDO: Test Data Output | | Input +nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor +nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor + + +DAP Hardware I/O Pin Access Functions +------------------------------------- +The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to +these I/O Pins. + +For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only. +This functions are provided to achieve faster I/O that is possible with some advanced GPIO +peripherals that can independently write/read a single I/O pin without affecting any other pins +of the same I/O port. The following SWDIO I/O Pin functions are provided: + - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware. + - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware. + - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed. + - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed. +*/ + + +// Configure DAP I/O pins ------------------------------ + +/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET. +Configures the DAP Hardware I/O pins for JTAG mode: + - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level. + - TDO to input mode. +*/ +__STATIC_INLINE void PORT_JTAG_SETUP(void) +{ +} + +/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET. +Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: + - SWCLK, SWDIO, nRESET to output mode and set to default high level. + - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode). +*/ +__STATIC_INLINE void PORT_SWD_SETUP(void) +{ +// PIN_SWCLK_GPIO->PSOR = 1 << PIN_SWCLK_BIT; +// PIN_SWDIO_OUT_GPIO->PSOR = 1 << PIN_SWDIO_OUT_BIT; +// PIN_SWDIO_OE_GPIO->PSOR = 1 << PIN_SWDIO_OE_BIT; +// PIN_SWD_OE_GPIO->PSOR = 1 << PIN_SWD_OE_BIT; +// PIN_nRESET_GPIO->PSOR = 1 << PIN_nRESET_BIT; +// PIN_SWD_OE_GPIO->PDDR = PIN_SWD_OE_GPIO->PDDR | (1 << PIN_SWD_OE_BIT); +// PIN_nRESET_GPIO->PSOR = PIN_nRESET; +// PIN_nRESET_GPIO->PDDR |= PIN_nRESET; //output +// PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_MUX(1); +} + +/** Disable JTAG/SWD I/O Pins. +Disables the DAP Hardware I/O pins which configures: + - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode. +*/ +__STATIC_INLINE void PORT_OFF(void) +{ +// PIN_SWDIO_OE_GPIO->PCOR = 1 << PIN_SWDIO_OE_BIT; +// PIN_SWD_OE_GPIO->PCOR = 1 << PIN_SWD_OE_BIT; +// PIN_nRESET_GPIO->PSOR = 1 << PIN_nRESET_BIT; +// PIN_nRESET_GPIO->PDDR &= ~PIN_nRESET; //input +// PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] |= PORT_PCR_ISF_MASK; +// PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_MUX(1); +} + + +// SWCLK/TCK I/O pin ------------------------------------- + +/** SWCLK/TCK I/O pin: Get Input. +\return Current status of the SWCLK/TCK DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void) +{ + return (0); // Not available +} + +/** SWCLK/TCK I/O pin: Set Output to High. +Set the SWCLK/TCK DAP hardware I/O pin to high level. +*/ +__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void) +{ +// PIN_SWCLK_GPIO->PSOR = 1 << PIN_SWCLK_BIT; +} + +/** SWCLK/TCK I/O pin: Set Output to Low. +Set the SWCLK/TCK DAP hardware I/O pin to low level. +*/ +__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void) +{ +// PIN_SWCLK_GPIO->PCOR = 1 << PIN_SWCLK_BIT; +} + + +// SWDIO/TMS Pin I/O -------------------------------------- + +/** SWDIO/TMS I/O pin: Get Input. +\return Current status of the SWDIO/TMS DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void) +{ + return 0; // ((PIN_SWDIO_IN_GPIO->PDIR >> PIN_SWDIO_IN_BIT) & 1); +} + +/** SWDIO/TMS I/O pin: Set Output to High. +Set the SWDIO/TMS DAP hardware I/O pin to high level. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void) +{ +// PIN_SWDIO_OUT_GPIO->PSOR = 1 << PIN_SWDIO_OUT_BIT; +} + +/** SWDIO/TMS I/O pin: Set Output to Low. +Set the SWDIO/TMS DAP hardware I/O pin to low level. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void) +{ +// PIN_SWDIO_OUT_GPIO->PCOR = 1 << PIN_SWDIO_OUT_BIT; +} + +/** SWDIO I/O pin: Get Input (used in SWD mode only). +\return Current status of the SWDIO DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void) +{ + return 0; // (BITBAND_REG(PIN_SWDIO_IN_GPIO->PDIR, PIN_SWDIO_IN_BIT)); +} + +/** SWDIO I/O pin: Set Output (used in SWD mode only). +\param bit Output value for the SWDIO DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit) +{ +// BITBAND_REG(PIN_SWDIO_OUT_GPIO->PDOR, PIN_SWDIO_OUT_BIT) = bit; +} + +/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only). +Configure the SWDIO DAP hardware I/O pin to output mode. This function is +called prior \ref PIN_SWDIO_OUT function calls. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void) +{ +// PIN_SWDIO_OE_GPIO->PSOR = 1 << PIN_SWDIO_OE_BIT; +} + +/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). +Configure the SWDIO DAP hardware I/O pin to input mode. This function is +called prior \ref PIN_SWDIO_IN function calls. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void) +{ +// PIN_SWDIO_OE_GPIO->PCOR = 1 << PIN_SWDIO_OE_BIT; +} + + +// TDI Pin I/O --------------------------------------------- + +/** TDI I/O pin: Get Input. +\return Current status of the TDI DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void) +{ + return (0); // Not available +} + +/** TDI I/O pin: Set Output. +\param bit Output value for the TDI DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit) +{ + ; // Not available +} + + +// TDO Pin I/O --------------------------------------------- + +/** TDO I/O pin: Get Input. +\return Current status of the TDO DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void) +{ + return (0); // Not available +} + + +// nTRST Pin I/O ------------------------------------------- + +/** nTRST I/O pin: Get Input. +\return Current status of the nTRST DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void) +{ + return (0); // Not available +} + +/** nTRST I/O pin: Set Output. +\param bit JTAG TRST Test Reset pin status: + - 0: issue a JTAG TRST Test Reset. + - 1: release JTAG TRST Test Reset. +*/ +__STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit) +{ + ; // Not available +} + +// nRESET Pin I/O------------------------------------------ + +/** nRESET I/O pin: Get Input. +\return Current status of the nRESET DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void) +{ + return 0; //((PIN_nRESET_GPIO->PDIR >> PIN_nRESET_BIT) & 1); +} + +/** nRESET I/O pin: Set Output. +\param bit target device hardware reset pin status: + - 0: issue a device hardware reset. + - 1: release device hardware reset. +*/ +__STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit) +{ +// BITBAND_REG(PIN_nRESET_GPIO->PDOR, PIN_nRESET_BIT) = bit; +} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs +\ingroup DAP_ConfigIO_gr +@{ + +CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit. + +It is recommended to provide the following LEDs for status indication: + - Connect LED: is active when the DAP hardware is connected to a debugger. + - Running LED: is active when the debugger has put the target device into running state. +*/ + +/** Debug Unit: Set status of Connected LED. +\param bit status of the Connect LED. + - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit. + - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit. +*/ +__STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit) +{ +// BITBAND_REG(LED_CONNECTED_GPIO->PDOR, LED_CONNECTED_BIT) = ~bit; +} + +/** Debug Unit: Set status Target Running LED. +\param bit status of the Target Running LED. + - 1: Target Running LED ON: program execution in target started. + - 0: Target Running LED OFF: program execution in target stopped. +*/ +__STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit) +{ + ; // Not available +} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp +\ingroup DAP_ConfigIO_gr +@{ +Access function for Test Domain Timer. + +The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By +default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK. + +*/ + +/** Get timestamp of Test Domain Timer. +\return Current timestamp value. +*/ +__STATIC_INLINE uint32_t TIMESTAMP_GET (void) { + return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK); +} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization +\ingroup DAP_ConfigIO_gr +@{ + +CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP. +*/ + +/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized). +This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the +Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set: + - I/O clock system enabled. + - all I/O pins: input buffer enabled, output pins are set to HighZ mode. + - for nTRST, nRESET a weak pull-up (if available) is enabled. + - LED output pins are enabled and LEDs are turned off. +*/ +__STATIC_INLINE void DAP_SETUP(void) +{ +// SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK | /* Enable Port A Clock */ +// SIM_SCGC5_PORTB_MASK | /* Enable Port B Clock */ +// SIM_SCGC5_PORTC_MASK | /* Enable Port C Clock */ +// SIM_SCGC5_PORTD_MASK; /* Enable Port D Clock */ +// /* Configure I/O pin SWCLK */ +// PIN_SWCLK_PORT->PCR[PIN_SWCLK_BIT] = PORT_PCR_MUX(1) | /* GPIO */ +// PORT_PCR_DSE_MASK; /* High drive strength */ +// PIN_SWCLK_GPIO->PSOR = 1 << PIN_SWCLK_BIT; /* High level */ +// PIN_SWCLK_GPIO->PDDR |= 1 << PIN_SWCLK_BIT; /* Output */ +// /* Configure I/O pin SWDIO_OUT */ +// PIN_SWDIO_OUT_PORT->PCR[PIN_SWDIO_OUT_BIT] = PORT_PCR_MUX(1) | /* GPIO */ +// PORT_PCR_DSE_MASK; /* High drive strength */ +// PIN_SWDIO_OUT_GPIO->PSOR = 1 << PIN_SWDIO_OUT_BIT; /* High level */ +// PIN_SWDIO_OUT_GPIO->PDDR |= 1 << PIN_SWDIO_OUT_BIT; /* Output */ +// /* Configure I/O pin SWDIO_IN */ +// PIN_SWDIO_IN_PORT->PCR[PIN_SWDIO_IN_BIT] = PORT_PCR_MUX(1) | /* GPIO */ +// PORT_PCR_PE_MASK | /* Pull enable */ +// PORT_PCR_PS_MASK; /* Pull-up */ +// PIN_SWDIO_IN_GPIO->PDDR &= ~(1 << PIN_SWDIO_IN_BIT); /* Input */ +// /* Configure I/O pin SWDIO_OE */ +// PIN_SWDIO_OE_PORT->PCR[PIN_SWDIO_OE_BIT] = PORT_PCR_MUX(1) | /* GPIO */ +// PORT_PCR_DSE_MASK; /* High drive strength */ +// PIN_SWDIO_OE_GPIO->PCOR = 1 << PIN_SWDIO_OE_BIT; /* Low level */ +// PIN_SWDIO_OE_GPIO->PDDR |= 1 << PIN_SWDIO_OE_BIT; /* Output */ +// /* Configure I/O pin SWD_OE */ +// PIN_SWD_OE_PORT->PCR[PIN_SWD_OE_BIT] = PORT_PCR_MUX(1) | /* GPIO */ +// PORT_PCR_DSE_MASK; /* High drive strength */ +// PIN_SWD_OE_GPIO->PCOR = 1 << PIN_SWD_OE_BIT; /* Low level */ +// PIN_SWD_OE_GPIO->PDDR |= 1 << PIN_SWD_OE_BIT; /* Output */ +// /* Configure I/O pin nRESET */ +// PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_MUX(1) | /* GPIO */ +// PORT_PCR_PE_MASK | /* Pull enable */ +// PORT_PCR_PS_MASK | /* Pull-up */ +// PORT_PCR_ODE_MASK; /* Open-drain */ +// PIN_nRESET_GPIO->PSOR = 1 << PIN_nRESET_BIT; /* High level */ +// PIN_nRESET_GPIO->PDDR &= ~(1 << PIN_nRESET_BIT); /* Input */ +// // Configure I/O pin LVLRST_EN +// // The nRESET level translator is enabled by default. The translator is auto- +// // direction sensing. So as long as we don't drive nRESET from our side, we won't +// // interfere with another debug probe connected to the target SWD header. +// PIN_nRESET_EN_PORT->PCR[PIN_nRESET_EN_BIT] = PORT_PCR_MUX(1) | /* GPIO */ +// PORT_PCR_ODE_MASK; /* Open-drain */ +// PIN_nRESET_EN_GPIO->PSOR = PIN_nRESET_EN; /* High level */ +// PIN_nRESET_EN_GPIO->PDDR |= PIN_nRESET_EN; /* Output */ +// /* Configure LED */ +// LED_CONNECTED_PORT->PCR[LED_CONNECTED_BIT] = PORT_PCR_MUX(1) | /* GPIO */ +// PORT_PCR_ODE_MASK; /* Open-drain */ +// LED_CONNECTED_GPIO->PCOR = 1 << LED_CONNECTED_BIT; /* Turned on */ +// LED_CONNECTED_GPIO->PDDR |= 1 << LED_CONNECTED_BIT; /* Output */ + + + // Enable clocks. + SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_IOCON_MASK + | SYSCON_AHBCLKCTRL0_GPIO0_MASK; + + + +} + +/** Reset Target Device with custom specific I/O pin or command sequence. +This function allows the optional implementation of a device specific reset sequence. +It is called when the command \ref DAP_ResetTarget and is for example required +when a device needs a time-critical unlock sequence that enables the debug port. +\return 0 = no device specific reset sequence is implemented.\n + 1 = a device specific reset sequence is implemented. +*/ +__STATIC_INLINE uint32_t RESET_TARGET(void) +{ + return (0); // change to '1' when a device reset sequence is implemented +} + +///@} + + +#endif /* __DAP_CONFIG_H__ */ diff --git a/source/hic_hal/nxp/lpc55xx/Driver_Common.h b/source/hic_hal/nxp/lpc55xx/Driver_Common.h new file mode 100644 index 000000000..59d5b759c --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/Driver_Common.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 2. Feb 2017 + * $Revision: V2.0 + * + * Project: Common Driver definitions + */ + +/* History: + * Version 2.0 + * Changed prefix ARM_DRV -> ARM_DRIVER + * Added General return codes definitions + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.00 + * Initial release + */ + +#ifndef DRIVER_COMMON_H_ +#define DRIVER_COMMON_H_ + +#include +#include +#include + +#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor)) + +/** +\brief Driver Version +*/ +typedef struct _ARM_DRIVER_VERSION { + uint16_t api; ///< API version + uint16_t drv; ///< Driver version +} ARM_DRIVER_VERSION; + +/* General return codes */ +#define ARM_DRIVER_OK 0 ///< Operation succeeded +#define ARM_DRIVER_ERROR -1 ///< Unspecified error +#define ARM_DRIVER_ERROR_BUSY -2 ///< Driver is busy +#define ARM_DRIVER_ERROR_TIMEOUT -3 ///< Timeout occurred +#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported +#define ARM_DRIVER_ERROR_PARAMETER -5 ///< Parameter error +#define ARM_DRIVER_ERROR_SPECIFIC -6 ///< Start of driver specific errors + +/** +\brief General power states +*/ +typedef enum _ARM_POWER_STATE { + ARM_POWER_OFF, ///< Power off: no operation possible + ARM_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events + ARM_POWER_FULL ///< Power on: full operation at maximum performance +} ARM_POWER_STATE; + +#endif /* DRIVER_COMMON_H_ */ diff --git a/source/hic_hal/nxp/lpc55xx/Driver_USART.h b/source/hic_hal/nxp/lpc55xx/Driver_USART.h new file mode 100644 index 000000000..e60bf51a3 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/Driver_USART.h @@ -0,0 +1,341 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 2. Feb 2017 + * $Revision: V2.3 + * + * Project: USART (Universal Synchronous Asynchronous Receiver Transmitter) + * Driver definitions + */ + +/* History: + * Version 2.3 + * ARM_USART_STATUS and ARM_USART_MODEM_STATUS made volatile + * Version 2.2 + * Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions + * Version 2.1 + * Removed optional argument parameter from Signal Event + * Version 2.0 + * New simplified driver: + * complexity moved to upper layer (especially data handling) + * more unified API for different communication interfaces + * renamed driver UART -> USART (Asynchronous & Synchronous) + * Added modes: + * Synchronous + * Single-wire + * IrDA + * Smart Card + * Changed prefix ARM_DRV -> ARM_DRIVER + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.01 + * Added events: + * ARM_UART_EVENT_TX_EMPTY, ARM_UART_EVENT_RX_TIMEOUT + * ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD + * Added functions: SetTxThreshold, SetRxThreshold + * Added "rx_timeout_event" to capabilities + * Version 1.00 + * Initial release + */ + +#ifndef DRIVER_USART_H_ +#define DRIVER_USART_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "Driver_Common.h" + +#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */ + + +/****** USART Control Codes *****/ + +#define ARM_USART_CONTROL_Pos 0 +#define ARM_USART_CONTROL_Msk (0xFFUL << ARM_USART_CONTROL_Pos) + +/*----- USART Control Codes: Mode -----*/ +#define ARM_USART_MODE_ASYNCHRONOUS (0x01UL << ARM_USART_CONTROL_Pos) ///< UART (Asynchronous); arg = Baudrate +#define ARM_USART_MODE_SYNCHRONOUS_MASTER (0x02UL << ARM_USART_CONTROL_Pos) ///< Synchronous Master (generates clock signal); arg = Baudrate +#define ARM_USART_MODE_SYNCHRONOUS_SLAVE (0x03UL << ARM_USART_CONTROL_Pos) ///< Synchronous Slave (external clock signal) +#define ARM_USART_MODE_SINGLE_WIRE (0x04UL << ARM_USART_CONTROL_Pos) ///< UART Single-wire (half-duplex); arg = Baudrate +#define ARM_USART_MODE_IRDA (0x05UL << ARM_USART_CONTROL_Pos) ///< UART IrDA; arg = Baudrate +#define ARM_USART_MODE_SMART_CARD (0x06UL << ARM_USART_CONTROL_Pos) ///< UART Smart Card; arg = Baudrate + +/*----- USART Control Codes: Mode Parameters: Data Bits -----*/ +#define ARM_USART_DATA_BITS_Pos 8 +#define ARM_USART_DATA_BITS_Msk (7UL << ARM_USART_DATA_BITS_Pos) +#define ARM_USART_DATA_BITS_5 (5UL << ARM_USART_DATA_BITS_Pos) ///< 5 Data bits +#define ARM_USART_DATA_BITS_6 (6UL << ARM_USART_DATA_BITS_Pos) ///< 6 Data bit +#define ARM_USART_DATA_BITS_7 (7UL << ARM_USART_DATA_BITS_Pos) ///< 7 Data bits +#define ARM_USART_DATA_BITS_8 (0UL << ARM_USART_DATA_BITS_Pos) ///< 8 Data bits (default) +#define ARM_USART_DATA_BITS_9 (1UL << ARM_USART_DATA_BITS_Pos) ///< 9 Data bits + +/*----- USART Control Codes: Mode Parameters: Parity -----*/ +#define ARM_USART_PARITY_Pos 12 +#define ARM_USART_PARITY_Msk (3UL << ARM_USART_PARITY_Pos) +#define ARM_USART_PARITY_NONE (0UL << ARM_USART_PARITY_Pos) ///< No Parity (default) +#define ARM_USART_PARITY_EVEN (1UL << ARM_USART_PARITY_Pos) ///< Even Parity +#define ARM_USART_PARITY_ODD (2UL << ARM_USART_PARITY_Pos) ///< Odd Parity + +/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/ +#define ARM_USART_STOP_BITS_Pos 14 +#define ARM_USART_STOP_BITS_Msk (3UL << ARM_USART_STOP_BITS_Pos) +#define ARM_USART_STOP_BITS_1 (0UL << ARM_USART_STOP_BITS_Pos) ///< 1 Stop bit (default) +#define ARM_USART_STOP_BITS_2 (1UL << ARM_USART_STOP_BITS_Pos) ///< 2 Stop bits +#define ARM_USART_STOP_BITS_1_5 (2UL << ARM_USART_STOP_BITS_Pos) ///< 1.5 Stop bits +#define ARM_USART_STOP_BITS_0_5 (3UL << ARM_USART_STOP_BITS_Pos) ///< 0.5 Stop bits + +/*----- USART Control Codes: Mode Parameters: Flow Control -----*/ +#define ARM_USART_FLOW_CONTROL_Pos 16 +#define ARM_USART_FLOW_CONTROL_Msk (3UL << ARM_USART_FLOW_CONTROL_Pos) +#define ARM_USART_FLOW_CONTROL_NONE (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default) +#define ARM_USART_FLOW_CONTROL_RTS (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control +#define ARM_USART_FLOW_CONTROL_CTS (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control +#define ARM_USART_FLOW_CONTROL_RTS_CTS (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control + +/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/ +#define ARM_USART_CPOL_Pos 18 +#define ARM_USART_CPOL_Msk (1UL << ARM_USART_CPOL_Pos) +#define ARM_USART_CPOL0 (0UL << ARM_USART_CPOL_Pos) ///< CPOL = 0 (default) +#define ARM_USART_CPOL1 (1UL << ARM_USART_CPOL_Pos) ///< CPOL = 1 + +/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/ +#define ARM_USART_CPHA_Pos 19 +#define ARM_USART_CPHA_Msk (1UL << ARM_USART_CPHA_Pos) +#define ARM_USART_CPHA0 (0UL << ARM_USART_CPHA_Pos) ///< CPHA = 0 (default) +#define ARM_USART_CPHA1 (1UL << ARM_USART_CPHA_Pos) ///< CPHA = 1 + + +/*----- USART Control Codes: Miscellaneous Controls -----*/ +#define ARM_USART_SET_DEFAULT_TX_VALUE (0x10UL << ARM_USART_CONTROL_Pos) ///< Set default Transmit value (Synchronous Receive only); arg = value +#define ARM_USART_SET_IRDA_PULSE (0x11UL << ARM_USART_CONTROL_Pos) ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period +#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Guard Time; arg = number of bit periods +#define ARM_USART_SET_SMART_CARD_CLOCK (0x13UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated +#define ARM_USART_CONTROL_SMART_CARD_NACK (0x14UL << ARM_USART_CONTROL_Pos) ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled +#define ARM_USART_CONTROL_TX (0x15UL << ARM_USART_CONTROL_Pos) ///< Transmitter; arg: 0=disabled, 1=enabled +#define ARM_USART_CONTROL_RX (0x16UL << ARM_USART_CONTROL_Pos) ///< Receiver; arg: 0=disabled, 1=enabled +#define ARM_USART_CONTROL_BREAK (0x17UL << ARM_USART_CONTROL_Pos) ///< Continuous Break transmission; arg: 0=disabled, 1=enabled +#define ARM_USART_ABORT_SEND (0x18UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Send +#define ARM_USART_ABORT_RECEIVE (0x19UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Receive +#define ARM_USART_ABORT_TRANSFER (0x1AUL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Transfer + + + +/****** USART specific error codes *****/ +#define ARM_USART_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported +#define ARM_USART_ERROR_BAUDRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified baudrate not supported +#define ARM_USART_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported +#define ARM_USART_ERROR_PARITY (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Parity not supported +#define ARM_USART_ERROR_STOP_BITS (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified number of Stop bits not supported +#define ARM_USART_ERROR_FLOW_CONTROL (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Flow Control not supported +#define ARM_USART_ERROR_CPOL (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock Polarity not supported +#define ARM_USART_ERROR_CPHA (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Clock Phase not supported + + +/** +\brief USART Status +*/ +typedef volatile struct _ARM_USART_STATUS { + uint32_t tx_busy : 1; ///< Transmitter busy flag + uint32_t rx_busy : 1; ///< Receiver busy flag + uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation) + uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation) + uint32_t rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation) + uint32_t rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation) + uint32_t rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation) + uint32_t reserved : 25; +} ARM_USART_STATUS; + +/** +\brief USART Modem Control +*/ +typedef enum _ARM_USART_MODEM_CONTROL { + ARM_USART_RTS_CLEAR, ///< Deactivate RTS + ARM_USART_RTS_SET, ///< Activate RTS + ARM_USART_DTR_CLEAR, ///< Deactivate DTR + ARM_USART_DTR_SET ///< Activate DTR +} ARM_USART_MODEM_CONTROL; + +/** +\brief USART Modem Status +*/ +typedef volatile struct _ARM_USART_MODEM_STATUS { + uint32_t cts : 1; ///< CTS state: 1=Active, 0=Inactive + uint32_t dsr : 1; ///< DSR state: 1=Active, 0=Inactive + uint32_t dcd : 1; ///< DCD state: 1=Active, 0=Inactive + uint32_t ri : 1; ///< RI state: 1=Active, 0=Inactive + uint32_t reserved : 28; +} ARM_USART_MODEM_STATUS; + + +/****** USART Event *****/ +#define ARM_USART_EVENT_SEND_COMPLETE (1UL << 0) ///< Send completed; however USART may still transmit data +#define ARM_USART_EVENT_RECEIVE_COMPLETE (1UL << 1) ///< Receive completed +#define ARM_USART_EVENT_TRANSFER_COMPLETE (1UL << 2) ///< Transfer completed +#define ARM_USART_EVENT_TX_COMPLETE (1UL << 3) ///< Transmit completed (optional) +#define ARM_USART_EVENT_TX_UNDERFLOW (1UL << 4) ///< Transmit data not available (Synchronous Slave) +#define ARM_USART_EVENT_RX_OVERFLOW (1UL << 5) ///< Receive data overflow +#define ARM_USART_EVENT_RX_TIMEOUT (1UL << 6) ///< Receive character timeout (optional) +#define ARM_USART_EVENT_RX_BREAK (1UL << 7) ///< Break detected on receive +#define ARM_USART_EVENT_RX_FRAMING_ERROR (1UL << 8) ///< Framing error detected on receive +#define ARM_USART_EVENT_RX_PARITY_ERROR (1UL << 9) ///< Parity error detected on receive +#define ARM_USART_EVENT_CTS (1UL << 10) ///< CTS state changed (optional) +#define ARM_USART_EVENT_DSR (1UL << 11) ///< DSR state changed (optional) +#define ARM_USART_EVENT_DCD (1UL << 12) ///< DCD state changed (optional) +#define ARM_USART_EVENT_RI (1UL << 13) ///< RI state changed (optional) + + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_USART_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION + + \fn ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void) + \brief Get driver capabilities + \return \ref ARM_USART_CAPABILITIES + + \fn int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event) + \brief Initialize USART Interface. + \param[in] cb_event Pointer to \ref ARM_USART_SignalEvent + \return \ref execution_status + + \fn int32_t ARM_USART_Uninitialize (void) + \brief De-initialize USART Interface. + \return \ref execution_status + + \fn int32_t ARM_USART_PowerControl (ARM_POWER_STATE state) + \brief Control USART Interface Power. + \param[in] state Power state + \return \ref execution_status + + \fn int32_t ARM_USART_Send (const void *data, uint32_t num) + \brief Start sending data to USART transmitter. + \param[in] data Pointer to buffer with data to send to USART transmitter + \param[in] num Number of data items to send + \return \ref execution_status + + \fn int32_t ARM_USART_Receive (void *data, uint32_t num) + \brief Start receiving data from USART receiver. + \param[out] data Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to receive + \return \ref execution_status + + \fn int32_t ARM_USART_Transfer (const void *data_out, + void *data_in, + uint32_t num) + \brief Start sending/receiving data to/from USART transmitter/receiver. + \param[in] data_out Pointer to buffer with data to send to USART transmitter + \param[out] data_in Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to transfer + \return \ref execution_status + + \fn uint32_t ARM_USART_GetTxCount (void) + \brief Get transmitted data count. + \return number of data items transmitted + + \fn uint32_t ARM_USART_GetRxCount (void) + \brief Get received data count. + \return number of data items received + + \fn int32_t ARM_USART_Control (uint32_t control, uint32_t arg) + \brief Control USART Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \return common \ref execution_status and driver specific \ref usart_execution_status + + \fn ARM_USART_STATUS ARM_USART_GetStatus (void) + \brief Get USART status. + \return USART status \ref ARM_USART_STATUS + + \fn int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control) + \brief Set USART Modem Control line state. + \param[in] control \ref ARM_USART_MODEM_CONTROL + \return \ref execution_status + + \fn ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void) + \brief Get USART Modem Status lines state. + \return modem status \ref ARM_USART_MODEM_STATUS + + \fn void ARM_USART_SignalEvent (uint32_t event) + \brief Signal USART Events. + \param[in] event \ref USART_events notification mask + \return none +*/ + +typedef void (*ARM_USART_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event. + + +/** +\brief USART Device Driver Capabilities. +*/ +typedef struct _ARM_USART_CAPABILITIES { + uint32_t asynchronous : 1; ///< supports UART (Asynchronous) mode + uint32_t synchronous_master : 1; ///< supports Synchronous Master mode + uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode + uint32_t single_wire : 1; ///< supports UART Single-wire mode + uint32_t irda : 1; ///< supports UART IrDA mode + uint32_t smart_card : 1; ///< supports UART Smart Card mode + uint32_t smart_card_clock : 1; ///< Smart Card Clock generator available + uint32_t flow_control_rts : 1; ///< RTS Flow Control available + uint32_t flow_control_cts : 1; ///< CTS Flow Control available + uint32_t event_tx_complete : 1; ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE + uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT + uint32_t rts : 1; ///< RTS Line: 0=not available, 1=available + uint32_t cts : 1; ///< CTS Line: 0=not available, 1=available + uint32_t dtr : 1; ///< DTR Line: 0=not available, 1=available + uint32_t dsr : 1; ///< DSR Line: 0=not available, 1=available + uint32_t dcd : 1; ///< DCD Line: 0=not available, 1=available + uint32_t ri : 1; ///< RI Line: 0=not available, 1=available + uint32_t event_cts : 1; ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS + uint32_t event_dsr : 1; ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR + uint32_t event_dcd : 1; ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD + uint32_t event_ri : 1; ///< Signal RI change event: \ref ARM_USART_EVENT_RI + uint32_t reserved : 11; ///< Reserved (must be zero) +} ARM_USART_CAPABILITIES; + + +/** +\brief Access structure of the USART Driver. +*/ +typedef struct _ARM_DRIVER_USART { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USART_GetVersion : Get driver version. + ARM_USART_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_USART_SignalEvent_t cb_event); ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power. + int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter. + int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver. + int32_t (*Transfer) (const void *data_out, + void *data_in, + uint32_t num); ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART. + uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count. + uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count. + int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_USART_Control : Control USART Interface. + ARM_USART_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_USART_GetStatus : Get USART status. + int32_t (*SetModemControl) (ARM_USART_MODEM_CONTROL control); ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state. + ARM_USART_MODEM_STATUS (*GetModemStatus) (void); ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state. +} const ARM_DRIVER_USART; + +#ifdef __cplusplus +} +#endif + +#endif /* DRIVER_USART_H_ */ diff --git a/source/hic_hal/nxp/lpc55xx/FlashPrg.c b/source/hic_hal/nxp/lpc55xx/FlashPrg.c new file mode 100644 index 000000000..441671406 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/FlashPrg.c @@ -0,0 +1,156 @@ +/** + * @file FlashPrg.c + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "FlashOS.h" // FlashOS Structures +#include "fsl_flash.h" +#include "string.h" +#include "cortex_m.h" + +flash_config_t g_flash; //!< Storage for flash driver. + +uint32_t Init(uint32_t adr, uint32_t clk, uint32_t fnc) +{ + cortex_int_state_t state = cortex_int_get_and_disable(); +#if defined (WDOG) + /* Write 0xC520 to the unlock register */ + WDOG->UNLOCK = 0xC520; + /* Followed by 0xD928 to complete the unlock */ + WDOG->UNLOCK = 0xD928; + /* Clear the WDOGEN bit to disable the watchdog */ + WDOG->STCTRLH &= ~WDOG_STCTRLH_WDOGEN_MASK; +#else +#ifdef LPC55_FIXME + /* FIXME: Commenting out next line which seems to disable the watchdog? + source/hic_hal/freescale/kl26z/MKL26Z4/system_MKL26Z4.c:SystemInit.c + */ + SIM->COPC = 0x00u; +#endif +#endif + cortex_int_restore(state); + + return (FLASH_Init(&g_flash) != kStatus_Success); +} + + +/* + * De-Initialize Flash Programming Functions + * Parameter: fnc: Function Code (1 - Erase, 2 - Program, 3 - Verify) + * Return Value: 0 - OK, 1 - Failed + */ + +uint32_t UnInit(uint32_t fnc) +{ + return (0); +} + + +/* Blank Check Block in Flash Memory + * Parameter: adr: Block Start Address + * sz: Block Size (in bytes) + * pat: Block Pattern + * Return Value: 0 - OK, 1 - Failed + */ + +// int BlankCheck (unsigned long adr, unsigned long sz, unsigned char pat) +// { +// return (flash_verify_erase(&g_flash, adr, sz, kFlashMargin_Normal) != kStatus_Success); +// } +// +// /* +// * Verify Flash Contents +// * Parameter: adr: Start Address +// * sz: Size (in bytes) +// * buf: Data +// * Return Value: (adr+sz) - OK, Failed Address +// */ +// unsigned long Verify (unsigned long adr, unsigned long sz, unsigned char *buf) +// { +// uint32_t failedAddress; +// status_t status = flash_verify_program(&g_flash, adr, sz, +// (const uint8_t *)buf, kFlashMargin_Normal, +// &failedAddress, NULL); +// +// if (status == kStatus_Success) +// { +// // Finished without Errors +// return (adr+sz); +// } +// else +// { +// return failedAddress; +// } +// } + +/* + * Erase complete Flash Memory + * Return Value: 0 - OK, 1 - Failed + */ +uint32_t EraseChip(void) +{ + cortex_int_state_t state = cortex_int_get_and_disable(); + int status = FLASH_EraseAll(&g_flash, kFLASH_apiEraseKey); + if (status == kStatus_Success) + { + status = FLASH_VerifyEraseAll(&g_flash, kFLASH_marginValueNormal); + } + cortex_int_restore(state); + return status; +} + +/* + * Erase Sector in Flash Memory + * Parameter: adr: Sector Address + * Return Value: 0 - OK, 1 - Failed + */ +uint32_t EraseSector(uint32_t adr) +{ + cortex_int_state_t state = cortex_int_get_and_disable(); + int status = FLASH_Erase(&g_flash, adr, g_flash.PFlashSectorSize, kFLASH_apiEraseKey); + if (status == kStatus_Success) + { + status = FLASH_VerifyErase(&g_flash, adr, g_flash.PFlashSectorSize, kFLASH_marginValueNormal); + } + cortex_int_restore(state); + return status; +} + +/* + * Program Page in Flash Memory + * Parameter: adr: Page Start Address + * sz: Page Size + * buf: Page Data + * Return Value: 0 - OK, 1 - Failed + */ +uint32_t ProgramPage(uint32_t adr, uint32_t sz, uint32_t *buf) +{ + cortex_int_state_t state = cortex_int_get_and_disable(); + int status = FLASH_Program(&g_flash, adr, buf, sz); + if (status == kStatus_Success) + { + // Must use kFlashMargin_User, or kFlashMargin_Factory for verify program + status = FLASH_VerifyProgram(&g_flash, adr, sz, + buf, kFLASH_marginValueUser, + NULL, NULL); + } + cortex_int_restore(state); + return status; +} + diff --git a/source/hic_hal/nxp/lpc55xx/IO_Config.h b/source/hic_hal/nxp/lpc55xx/IO_Config.h new file mode 100644 index 000000000..b3d1965b2 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/IO_Config.h @@ -0,0 +1,207 @@ +/** + * @file IO_Config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "fsl_device_registers.h" +#include "compiler.h" +#include "daplink.h" + +// This GPIO configuration is only valid for the K26F HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_K26F); + + +// Debug Port I/O Pins + +// SWCLK Pin PTC5 +// (SDA_SWD_SCK on schematic) +#define PIN_SWCLK_PORT PORTC +#define PIN_SWCLK_GPIO PTC +#define PIN_SWCLK_BIT 5 + +// SWDIO Out Pin PTC6 +// (SDA_SWD_DOUT on schematic) +#define PIN_SWDIO_OUT_PORT PORTC +#define PIN_SWDIO_OUT_GPIO PTC +#define PIN_SWDIO_OUT_BIT 6 + +// SWDIO In Pin PTC7 +// (SDA_SWD_DIN on schematic) +#define PIN_SWDIO_IN_PORT PORTC +#define PIN_SWDIO_IN_GPIO PTC +#define PIN_SWDIO_IN_BIT 7 + +// SWDIO Output Enable Pin PTA5 +// (SDA_SWD_OE on schematic) +#define PIN_SWDIO_OE_PORT PORTA +#define PIN_SWDIO_OE_GPIO PTA +#define PIN_SWDIO_OE_BIT 5 + +// SWD Enable Pin PTA4 +// (SDA_SWD_EN on schematic) +#define PIN_SWD_OE_PORT PORTA +#define PIN_SWD_OE_GPIO PTA +#define PIN_SWD_OE_BIT 9 + +// SWO Input Pin PTC3 +// (SDA_SWD_SWO on schematic) +#define PIN_SWO_RX_PORT PORTC +#define PIN_SWO_RX_GPIO PTC +#define PIN_SWO_RX_BIT 3 + +// nRESET Pin PTA7 +#define PIN_nRESET_PORT PORTA +#define PIN_nRESET_GPIO PTA +#define PIN_nRESET_BIT 7 +#define PIN_nRESET (1 << PIN_nRESET_BIT) + +// nRESET Pin Level Shifter Enable PTA6 +// (SDA_LVLRST_EN on schematic) +#define PIN_nRESET_EN_PORT PORTA +#define PIN_nRESET_EN_GPIO PTA +#define PIN_nRESET_EN_BIT 6 +#define PIN_nRESET_EN (1 << PIN_nRESET_EN_BIT) + +// SWD Detect Pin PTA8 +// (x_SWD_DETECT on schematic) +#define PIN_SWD_DETECT_PORT PORTA +#define PIN_SWD_DETECTGPIO PTA +#define PIN_SWD_DETECT_BIT 8 +#define PIN_SWD_DETECT (1 << PIN_SWD_DETECT_BIT) + + +// Power monitor + +// SDA_G1 Pin PTE17 +#define PIN_G1_PORT PORTE +#define PIN_G1_GPIO PTE +#define PIN_G1_BIT 17 +#define PIN_G1 (1 << PIN_G1_BIT) + +// SDA_G2 Pin PTE18 +#define PIN_G2_PORT PORTE +#define PIN_G2_GPIO PTE +#define PIN_G2_BIT 18 +#define PIN_G2 (1 << PIN_G2_BIT) + +// SDA_LOW_RANGE_EN Pin PTE19 +#define PIN_LOW_RANGE_EN_PORT PORTE +#define PIN_LOW_RANGE_EN_GPIO PTE +#define PIN_LOW_RANGE_EN_BIT 19 +#define PIN_LOW_RANGE_EN (1 << PIN_LOW_RANGE_EN_BIT) + +// SDA_CAL_EN Pin PTE24 +#define PIN_CAL_EN_PORT PORTE +#define PIN_CAL_EN_GPIO PTE +#define PIN_CAL_EN_BIT 24 +#define PIN_CAL_EN (1 << PIN_CAL_EN_BIT) + +// SDA_CTRL0 Pin PTE25 +#define PIN_CTRL0_PORT PORTE +#define PIN_CTRL0_GPIO PTE +#define PIN_CTRL0_BIT 25 +#define PIN_CTRL0 (1 << PIN_CTRL0_BIT) + +// SDA_CTRL1 Pin PTE26 +#define PIN_CTRL1_PORT PORTE +#define PIN_CTRL1_GPIO PTE +#define PIN_CTRL1_BIT 26 +#define PIN_CTRL1 (1 << PIN_CTRL1_BIT) + +// SDA_CTRL2 Pin PTE27 +#define PIN_CTRL2_PORT PORTE +#define PIN_CTRL2_GPIO PTE +#define PIN_CTRL2_BIT 27 +#define PIN_CTRL2 (1 << PIN_CTRL2_BIT) + +// SDA_CTRL3 Pin PTE28 +#define PIN_CTRL3_PORT PORTE +#define PIN_CTRL3_GPIO PTE +#define PIN_CTRL3_BIT 28 +#define PIN_CTRL3 (1 << PIN_CTRL3_BIT) + + +// Misc target connections + +// SDA_GPIO0_B Pin PTB22 +#define PIN_GPIO0_B_PORT PORTB +#define PIN_GPIO0_B_GPIO PTB +#define PIN_GPIO0_B_BIT 22 +#define PIN_GPIO0_B (1 < PIN_GPIO0_B_BIT) + +// SDA_CLKOUT_B Pin PTC +#define PIN_CLKOUT_B_PORT PORTC +#define PIN_CLKOUT_B_GPIO PTC +#define PIN_CLKOUT_B_BIT 3 +#define PIN_CLKOUT_B (1 << PIN_CLKOUT_B_BIT) + + +// Power and fault detection + +// PWR_REG_EN PTE12 +#define PIN_POWER_EN_PORT PORTE +#define PIN_POWER_EN_GPIO PTE +#define PIN_POWER_EN_BIT 12 +#define PIN_POWER_EN (1 << PIN_POWER_EN_BIT) + +// VTRG_FAULT_B PTE11 +#define PIN_VTRG_FAULT_B_PORT PORTE +#define PIN_VTRG_FAULT_B_GPIO PTE +#define PIN_VTRG_FAULT_B_BIT 11 + +// Debug Unit LEDs + +// Connected LED PTD4 +#define LED_CONNECTED_PORT PORTD +#define LED_CONNECTED_GPIO PTD +#define LED_CONNECTED_BIT 4 +#define LED_CONNECTED (1 << LED_CONNECTED_BIT) + +// Target Running LED Not available + +// Debug Unit LEDs + +// HID_LED PTD4 +#define PIN_HID_LED_PORT PORTD +#define PIN_HID_LED_GPIO PTD +#define PIN_HID_LED_BIT (4) +#define PIN_HID_LED (1<= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ + __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ + __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ + __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ + __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ + uint8_t RESERVED_1[12]; + __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ + __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ + uint8_t RESERVED_2[4]; + __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ + uint8_t RESERVED_3[92]; + __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ + __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_4[8]; + __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ + __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ + } CMD[15]; + uint8_t RESERVED_5[136]; + __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_6[240]; + __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_7[248]; + __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_8[124]; + __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */ + uint8_t RESERVED_9[2680]; + __IO uint32_t TST; /**< ADC Test Register, offset: 0xFFC */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define ADC_VERID_RES_MASK (0x1U) +#define ADC_VERID_RES_SHIFT (0U) +/*! RES - Resolution + * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. + * 0b1..Up to 16-bit differential/16-bit single ended resolution supported. + */ +#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) +#define ADC_VERID_DIFFEN_MASK (0x2U) +#define ADC_VERID_DIFFEN_SHIFT (1U) +/*! DIFFEN - Differential Supported + * 0b0..Differential operation not supported. + * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented. + */ +#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) +#define ADC_VERID_MVI_MASK (0x8U) +#define ADC_VERID_MVI_SHIFT (3U) +/*! MVI - Multi Vref Implemented + * 0b0..Single voltage reference high (VREFH) input supported. + * 0b1..Multiple voltage reference high (VREFH) inputs supported. + */ +#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) +#define ADC_VERID_CSW_MASK (0x70U) +#define ADC_VERID_CSW_SHIFT (4U) +/*! CSW - Channel Scale Width + * 0b000..Channel scaling not supported. + * 0b001..Channel scaling supported. 1-bit CSCALE control field. + * 0b110..Channel scaling supported. 6-bit CSCALE control field. + */ +#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) +#define ADC_VERID_VR1RNGI_MASK (0x100U) +#define ADC_VERID_VR1RNGI_SHIFT (8U) +/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented + * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. + * 0b1..Range control required. CFG[VREF1RNG] is implemented. + */ +#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) +#define ADC_VERID_IADCKI_MASK (0x200U) +#define ADC_VERID_IADCKI_SHIFT (9U) +/*! IADCKI - Internal ADC Clock implemented + * 0b0..Internal clock source not implemented. + * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. + */ +#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) +#define ADC_VERID_CALOFSI_MASK (0x400U) +#define ADC_VERID_CALOFSI_SHIFT (10U) +/*! CALOFSI - Calibration Function Implemented + * 0b0..Calibration Not Implemented. + * 0b1..Calibration Implemented. + */ +#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) +#define ADC_VERID_NUM_SEC_MASK (0x800U) +#define ADC_VERID_NUM_SEC_SHIFT (11U) +/*! NUM_SEC - Number of Single Ended Outputs Supported + * 0b0..This design supports one single ended conversion at a time. + * 0b1..This design supports two simultanious single ended conversions. + */ +#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) +#define ADC_VERID_NUM_FIFO_MASK (0x7000U) +#define ADC_VERID_NUM_FIFO_SHIFT (12U) +/*! NUM_FIFO - Number of FIFOs + * 0b000..N/A + * 0b001..This design supports one result FIFO. + * 0b010..This design supports two result FIFOs. + * 0b011..This design supports three result FIFOs. + * 0b100..This design supports four result FIFOs. + */ +#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) +#define ADC_VERID_MINOR_MASK (0xFF0000U) +#define ADC_VERID_MINOR_SHIFT (16U) +#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) +#define ADC_VERID_MAJOR_MASK (0xFF000000U) +#define ADC_VERID_MAJOR_SHIFT (24U) +#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) +#define ADC_PARAM_TRIG_NUM_SHIFT (0U) +#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) +#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) +#define ADC_PARAM_FIFOSIZE_SHIFT (8U) +/*! FIFOSIZE - Result FIFO Depth + * 0b00000001..Result FIFO depth = 1 dataword. + * 0b00000100..Result FIFO depth = 4 datawords. + * 0b00001000..Result FIFO depth = 8 datawords. + * 0b00010000..Result FIFO depth = 16 datawords. + * 0b00100000..Result FIFO depth = 32 datawords. + * 0b01000000..Result FIFO depth = 64 datawords. + */ +#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) +#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) +#define ADC_PARAM_CV_NUM_SHIFT (16U) +#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) +#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) +#define ADC_PARAM_CMD_NUM_SHIFT (24U) +#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) +/*! @} */ + +/*! @name CTRL - ADC Control Register */ +/*! @{ */ +#define ADC_CTRL_ADCEN_MASK (0x1U) +#define ADC_CTRL_ADCEN_SHIFT (0U) +/*! ADCEN - ADC Enable + * 0b0..ADC is disabled. + * 0b1..ADC is enabled. + */ +#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) +#define ADC_CTRL_RST_MASK (0x2U) +#define ADC_CTRL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..ADC logic is not reset. + * 0b1..ADC logic is reset. + */ +#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) +#define ADC_CTRL_DOZEN_MASK (0x4U) +#define ADC_CTRL_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Enable + * 0b0..ADC is enabled in Doze mode. + * 0b1..ADC is disabled in Doze mode. + */ +#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) +#define ADC_CTRL_CAL_REQ_MASK (0x8U) +#define ADC_CTRL_CAL_REQ_SHIFT (3U) +/*! CAL_REQ - Auto-Calibration Request + * 0b0..No request for auto-calibration has been made. + * 0b1..A request for auto-calibration has been made + */ +#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) +#define ADC_CTRL_CALOFS_MASK (0x10U) +#define ADC_CTRL_CALOFS_SHIFT (4U) +/*! CALOFS - Configure for offset calibration function + * 0b0..Calibration function disabled + * 0b1..Request for offset calibration function + */ +#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) +#define ADC_CTRL_RSTFIFO0_MASK (0x100U) +#define ADC_CTRL_RSTFIFO0_SHIFT (8U) +/*! RSTFIFO0 - Reset FIFO 0 + * 0b0..No effect. + * 0b1..FIFO 0 is reset. + */ +#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) +#define ADC_CTRL_RSTFIFO1_MASK (0x200U) +#define ADC_CTRL_RSTFIFO1_SHIFT (9U) +/*! RSTFIFO1 - Reset FIFO 1 + * 0b0..No effect. + * 0b1..FIFO 1 is reset. + */ +#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) +#define ADC_CTRL_CAL_AVGS_MASK (0x70000U) +#define ADC_CTRL_CAL_AVGS_SHIFT (16U) +/*! CAL_AVGS - Auto-Calibration Averages + * 0b000..Single conversion. + * 0b001..2 conversions averaged. + * 0b010..4 conversions averaged. + * 0b011..8 conversions averaged. + * 0b100..16 conversions averaged. + * 0b101..32 conversions averaged. + * 0b110..64 conversions averaged. + * 0b111..128 conversions averaged. + */ +#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) +/*! @} */ + +/*! @name STAT - ADC Status Register */ +/*! @{ */ +#define ADC_STAT_RDY0_MASK (0x1U) +#define ADC_STAT_RDY0_SHIFT (0U) +/*! RDY0 - Result FIFO 0 Ready Flag + * 0b0..Result FIFO 0 data level not above watermark level. + * 0b1..Result FIFO 0 holding data above watermark level. + */ +#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) +#define ADC_STAT_FOF0_MASK (0x2U) +#define ADC_STAT_FOF0_SHIFT (1U) +/*! FOF0 - Result FIFO 0 Overflow Flag + * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) +#define ADC_STAT_RDY1_MASK (0x4U) +#define ADC_STAT_RDY1_SHIFT (2U) +/*! RDY1 - Result FIFO1 Ready Flag + * 0b0..Result FIFO1 data level not above watermark level. + * 0b1..Result FIFO1 holding data above watermark level. + */ +#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) +#define ADC_STAT_FOF1_MASK (0x8U) +#define ADC_STAT_FOF1_SHIFT (3U) +/*! FOF1 - Result FIFO1 Overflow Flag + * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) +#define ADC_STAT_TEXC_INT_MASK (0x100U) +#define ADC_STAT_TEXC_INT_SHIFT (8U) +/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception + * 0b0..No trigger exceptions have occurred. + * 0b1..A trigger exception has occurred and is pending acknowledgement. + */ +#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) +#define ADC_STAT_TCOMP_INT_MASK (0x200U) +#define ADC_STAT_TCOMP_INT_SHIFT (9U) +/*! TCOMP_INT - Interrupt Flag For Trigger Completion + * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. + * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. + */ +#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) +#define ADC_STAT_CAL_RDY_MASK (0x400U) +#define ADC_STAT_CAL_RDY_SHIFT (10U) +/*! CAL_RDY - Calibration Ready + * 0b0..Calibration is incomplete or hasn't been ran. + * 0b1..The ADC is calibrated. + */ +#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) +#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) +#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) +/*! ADC_ACTIVE - ADC Active + * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. + * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. + */ +#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) +#define ADC_STAT_TRGACT_MASK (0xF0000U) +#define ADC_STAT_TRGACT_SHIFT (16U) +/*! TRGACT - Trigger Active + * 0b0000..Command (sequence) associated with Trigger 0 currently being executed. + * 0b0001..Command (sequence) associated with Trigger 1 currently being executed. + * 0b0010..Command (sequence) associated with Trigger 2 currently being executed. + * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed. + */ +#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) +#define ADC_STAT_CMDACT_MASK (0xF000000U) +#define ADC_STAT_CMDACT_SHIFT (24U) +/*! CMDACT - Command Active + * 0b0000..No command is currently in progress. + * 0b0001..Command 1 currently being executed. + * 0b0010..Command 2 currently being executed. + * 0b0011-0b1111..Associated command number is currently being executed. + */ +#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) +/*! @} */ + +/*! @name IE - Interrupt Enable Register */ +/*! @{ */ +#define ADC_IE_FWMIE0_MASK (0x1U) +#define ADC_IE_FWMIE0_SHIFT (0U) +/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable + * 0b0..FIFO 0 watermark interrupts are not enabled. + * 0b1..FIFO 0 watermark interrupts are enabled. + */ +#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) +#define ADC_IE_FOFIE0_MASK (0x2U) +#define ADC_IE_FOFIE0_SHIFT (1U) +/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable + * 0b0..FIFO 0 overflow interrupts are not enabled. + * 0b1..FIFO 0 overflow interrupts are enabled. + */ +#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) +#define ADC_IE_FWMIE1_MASK (0x4U) +#define ADC_IE_FWMIE1_SHIFT (2U) +/*! FWMIE1 - FIFO1 Watermark Interrupt Enable + * 0b0..FIFO1 watermark interrupts are not enabled. + * 0b1..FIFO1 watermark interrupts are enabled. + */ +#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) +#define ADC_IE_FOFIE1_MASK (0x8U) +#define ADC_IE_FOFIE1_SHIFT (3U) +/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable + * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) +#define ADC_IE_TEXC_IE_MASK (0x100U) +#define ADC_IE_TEXC_IE_SHIFT (8U) +/*! TEXC_IE - Trigger Exception Interrupt Enable + * 0b0..Trigger exception interrupts are disabled. + * 0b1..Trigger exception interrupts are enabled. + */ +#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) +#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U) +#define ADC_IE_TCOMP_IE_SHIFT (16U) +/*! TCOMP_IE - Trigger Completion Interrupt Enable + * 0b0000000000000000..Trigger completion interrupts are disabled. + * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only. + * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only. + * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled. + * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source. + */ +#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) +/*! @} */ + +/*! @name DE - DMA Enable Register */ +/*! @{ */ +#define ADC_DE_FWMDE0_MASK (0x1U) +#define ADC_DE_FWMDE0_SHIFT (0U) +/*! FWMDE0 - FIFO 0 Watermark DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) +#define ADC_DE_FWMDE1_MASK (0x2U) +#define ADC_DE_FWMDE1_SHIFT (1U) +/*! FWMDE1 - FIFO1 Watermark DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) +/*! @} */ + +/*! @name CFG - ADC Configuration Register */ +/*! @{ */ +#define ADC_CFG_TPRICTRL_MASK (0x3U) +#define ADC_CFG_TPRICTRL_SHIFT (0U) +/*! TPRICTRL - ADC trigger priority control + * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted + * and the new command specified by the trigger is started. + * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after + * after completing the current conversion. If averaging is enabled, the averaging loop will be completed. + * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. + * 0b10..If a higher priority trigger is received during command processing, the current command will be + * completed (averaging, looping, compare) before servicing the higher priority trigger. + * 0b11..RESERVED + */ +#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) +#define ADC_CFG_PWRSEL_MASK (0x30U) +#define ADC_CFG_PWRSEL_SHIFT (4U) +/*! PWRSEL - Power Configuration Select + * 0b00..Lowest power setting. + * 0b01..Higher power setting than 0b0. + * 0b10..Higher power setting than 0b1. + * 0b11..Highest power setting. + */ +#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) +#define ADC_CFG_REFSEL_MASK (0xC0U) +#define ADC_CFG_REFSEL_SHIFT (6U) +/*! REFSEL - Voltage Reference Selection + * 0b00..(Default) Option 1 setting. + * 0b01..Option 2 setting. + * 0b10..Option 3 setting. + * 0b11..Reserved + */ +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) +#define ADC_CFG_TRES_MASK (0x100U) +#define ADC_CFG_TRES_SHIFT (8U) +/*! TRES - Trigger Resume Enable + * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. + */ +#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) +#define ADC_CFG_TCMDRES_MASK (0x200U) +#define ADC_CFG_TCMDRES_SHIFT (9U) +/*! TCMDRES - Trigger Command Resume + * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. + */ +#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) +#define ADC_CFG_HPT_EXDI_MASK (0x400U) +#define ADC_CFG_HPT_EXDI_SHIFT (10U) +/*! HPT_EXDI - High Priority Trigger Exception Disable + * 0b0..High priority trigger exceptions are enabled. + * 0b1..High priority trigger exceptions are disabled. + */ +#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) +#define ADC_CFG_PUDLY_MASK (0xFF0000U) +#define ADC_CFG_PUDLY_SHIFT (16U) +#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) +#define ADC_CFG_PWREN_MASK (0x10000000U) +#define ADC_CFG_PWREN_SHIFT (28U) +/*! PWREN - ADC Analog Pre-Enable + * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. + * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost + * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN + * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. + * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be + * executed. + */ +#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) +/*! @} */ + +/*! @name PAUSE - ADC Pause Register */ +/*! @{ */ +#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) +#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) +#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) +#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) +#define ADC_PAUSE_PAUSEEN_SHIFT (31U) +/*! PAUSEEN - PAUSE Option Enable + * 0b0..Pause operation disabled + * 0b1..Pause operation enabled + */ +#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) +/*! @} */ + +/*! @name SWTRIG - Software Trigger Register */ +/*! @{ */ +#define ADC_SWTRIG_SWT0_MASK (0x1U) +#define ADC_SWTRIG_SWT0_SHIFT (0U) +/*! SWT0 - Software trigger 0 event + * 0b0..No trigger 0 event generated. + * 0b1..Trigger 0 event generated. + */ +#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) +#define ADC_SWTRIG_SWT1_MASK (0x2U) +#define ADC_SWTRIG_SWT1_SHIFT (1U) +/*! SWT1 - Software trigger 1 event + * 0b0..No trigger 1 event generated. + * 0b1..Trigger 1 event generated. + */ +#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) +#define ADC_SWTRIG_SWT2_MASK (0x4U) +#define ADC_SWTRIG_SWT2_SHIFT (2U) +/*! SWT2 - Software trigger 2 event + * 0b0..No trigger 2 event generated. + * 0b1..Trigger 2 event generated. + */ +#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) +#define ADC_SWTRIG_SWT3_MASK (0x8U) +#define ADC_SWTRIG_SWT3_SHIFT (3U) +/*! SWT3 - Software trigger 3 event + * 0b0..No trigger 3 event generated. + * 0b1..Trigger 3 event generated. + */ +#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) +#define ADC_SWTRIG_SWT4_MASK (0x10U) +#define ADC_SWTRIG_SWT4_SHIFT (4U) +/*! SWT4 - Software trigger 4 event + * 0b0..No trigger 4 event generated. + * 0b1..Trigger 4 event generated. + */ +#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) +#define ADC_SWTRIG_SWT5_MASK (0x20U) +#define ADC_SWTRIG_SWT5_SHIFT (5U) +/*! SWT5 - Software trigger 5 event + * 0b0..No trigger 5 event generated. + * 0b1..Trigger 5 event generated. + */ +#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) +#define ADC_SWTRIG_SWT6_MASK (0x40U) +#define ADC_SWTRIG_SWT6_SHIFT (6U) +/*! SWT6 - Software trigger 6 event + * 0b0..No trigger 6 event generated. + * 0b1..Trigger 6 event generated. + */ +#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) +#define ADC_SWTRIG_SWT7_MASK (0x80U) +#define ADC_SWTRIG_SWT7_SHIFT (7U) +/*! SWT7 - Software trigger 7 event + * 0b0..No trigger 7 event generated. + * 0b1..Trigger 7 event generated. + */ +#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) +#define ADC_SWTRIG_SWT8_MASK (0x100U) +#define ADC_SWTRIG_SWT8_SHIFT (8U) +/*! SWT8 - Software trigger 8 event + * 0b0..No trigger 8 event generated. + * 0b1..Trigger 8 event generated. + */ +#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK) +#define ADC_SWTRIG_SWT9_MASK (0x200U) +#define ADC_SWTRIG_SWT9_SHIFT (9U) +/*! SWT9 - Software trigger 9 event + * 0b0..No trigger 9 event generated. + * 0b1..Trigger 9 event generated. + */ +#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK) +#define ADC_SWTRIG_SWT10_MASK (0x400U) +#define ADC_SWTRIG_SWT10_SHIFT (10U) +/*! SWT10 - Software trigger 10 event + * 0b0..No trigger 10 event generated. + * 0b1..Trigger 10 event generated. + */ +#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK) +#define ADC_SWTRIG_SWT11_MASK (0x800U) +#define ADC_SWTRIG_SWT11_SHIFT (11U) +/*! SWT11 - Software trigger 11 event + * 0b0..No trigger 11 event generated. + * 0b1..Trigger 11 event generated. + */ +#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK) +#define ADC_SWTRIG_SWT12_MASK (0x1000U) +#define ADC_SWTRIG_SWT12_SHIFT (12U) +/*! SWT12 - Software trigger 12 event + * 0b0..No trigger 12 event generated. + * 0b1..Trigger 12 event generated. + */ +#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK) +#define ADC_SWTRIG_SWT13_MASK (0x2000U) +#define ADC_SWTRIG_SWT13_SHIFT (13U) +/*! SWT13 - Software trigger 13 event + * 0b0..No trigger 13 event generated. + * 0b1..Trigger 13 event generated. + */ +#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK) +#define ADC_SWTRIG_SWT14_MASK (0x4000U) +#define ADC_SWTRIG_SWT14_SHIFT (14U) +/*! SWT14 - Software trigger 14 event + * 0b0..No trigger 14 event generated. + * 0b1..Trigger 14 event generated. + */ +#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK) +#define ADC_SWTRIG_SWT15_MASK (0x8000U) +#define ADC_SWTRIG_SWT15_SHIFT (15U) +/*! SWT15 - Software trigger 15 event + * 0b0..No trigger 15 event generated. + * 0b1..Trigger 15 event generated. + */ +#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK) +/*! @} */ + +/*! @name TSTAT - Trigger Status Register */ +/*! @{ */ +#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU) +#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) +/*! TEXC_NUM - Trigger Exception Number + * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. + * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception. + * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception. + * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception. + * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception. + */ +#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) +#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U) +#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) +/*! TCOMP_FLAG - Trigger Completion Flag + * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled. + * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts. + * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts. + * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts. + * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. + */ +#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) +/*! @} */ + +/*! @name OFSTRIM - ADC Offset Trim Register */ +/*! @{ */ +#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) +#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) +#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) +#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) +#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) +#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) +/*! @} */ + +/*! @name TCTRL - Trigger Control Register */ +/*! @{ */ +#define ADC_TCTRL_HTEN_MASK (0x1U) +#define ADC_TCTRL_HTEN_SHIFT (0U) +/*! HTEN - Trigger enable + * 0b0..Hardware trigger source disabled + * 0b1..Hardware trigger source enabled + */ +#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) +#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) +#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) +/*! FIFO_SEL_A - SAR Result Destination For Channel A + * 0b0..Result written to FIFO 0 + * 0b1..Result written to FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) +#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) +#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) +/*! FIFO_SEL_B - SAR Result Destination For Channel B + * 0b0..Result written to FIFO 0 + * 0b1..Result written to FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) +#define ADC_TCTRL_TPRI_MASK (0xF00U) +#define ADC_TCTRL_TPRI_SHIFT (8U) +/*! TPRI - Trigger priority setting + * 0b0000..Set to highest priority, Level 1 + * 0b0001-0b1110..Set to corresponding priority level + * 0b1111..Set to lowest priority, Level 16 + */ +#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) +#define ADC_TCTRL_RSYNC_MASK (0x8000U) +#define ADC_TCTRL_RSYNC_SHIFT (15U) +#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) +#define ADC_TCTRL_TDLY_MASK (0xF0000U) +#define ADC_TCTRL_TDLY_SHIFT (16U) +#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) +#define ADC_TCTRL_TCMD_MASK (0xF000000U) +#define ADC_TCTRL_TCMD_SHIFT (24U) +/*! TCMD - Trigger command select + * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b0001..CMD1 is executed + * 0b0010-0b1110..Corresponding CMD is executed + * 0b1111..CMD15 is executed + */ +#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) +/*! @} */ + +/* The count of ADC_TCTRL */ +#define ADC_TCTRL_COUNT (16U) + +/*! @name FCTRL - FIFO Control Register */ +/*! @{ */ +#define ADC_FCTRL_FCOUNT_MASK (0x1FU) +#define ADC_FCTRL_FCOUNT_SHIFT (0U) +#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) +#define ADC_FCTRL_FWMARK_MASK (0xF0000U) +#define ADC_FCTRL_FWMARK_SHIFT (16U) +#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) +/*! @} */ + +/* The count of ADC_FCTRL */ +#define ADC_FCTRL_COUNT (2U) + +/*! @name GCC - Gain Calibration Control */ +/*! @{ */ +#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) +#define ADC_GCC_GAIN_CAL_SHIFT (0U) +#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) +#define ADC_GCC_RDY_MASK (0x1000000U) +#define ADC_GCC_RDY_SHIFT (24U) +/*! RDY - Gain Calibration Value Valid + * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. + * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. + */ +#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCC */ +#define ADC_GCC_COUNT (2U) + +/*! @name GCR - Gain Calculation Result */ +/*! @{ */ +#define ADC_GCR_GCALR_MASK (0xFFFFU) +#define ADC_GCR_GCALR_SHIFT (0U) +#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) +#define ADC_GCR_RDY_MASK (0x1000000U) +#define ADC_GCR_RDY_SHIFT (24U) +/*! RDY - Gain Calculation Ready + * 0b0..The gain offset calculation value is invalid. + * 0b1..The gain calibration value is valid. + */ +#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCR */ +#define ADC_GCR_COUNT (2U) + +/*! @name CMDL - ADC Command Low Buffer Register */ +/*! @{ */ +#define ADC_CMDL_ADCH_MASK (0x1FU) +#define ADC_CMDL_ADCH_SHIFT (0U) +/*! ADCH - Input channel select + * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. + * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. + * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. + * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. + * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. + * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. + */ +#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) +#define ADC_CMDL_CTYPE_MASK (0x60U) +#define ADC_CMDL_CTYPE_SHIFT (5U) +/*! CTYPE - Conversion Type + * 0b00..Single-Ended Mode. Only A side channel is converted. + * 0b01..Single-Ended Mode. Only B side channel is converted. + * 0b10..Differential Mode. A-B. + * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + */ +#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) +#define ADC_CMDL_MODE_MASK (0x80U) +#define ADC_CMDL_MODE_SHIFT (7U) +/*! MODE - Select resolution of conversions + * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + */ +#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) +/*! @} */ + +/* The count of ADC_CMDL */ +#define ADC_CMDL_COUNT (15U) + +/*! @name CMDH - ADC Command High Buffer Register */ +/*! @{ */ +#define ADC_CMDH_CMPEN_MASK (0x3U) +#define ADC_CMDH_CMPEN_SHIFT (0U) +/*! CMPEN - Compare Function Enable + * 0b00..Compare disabled. + * 0b01..Reserved + * 0b10..Compare enabled. Store on true. + * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + */ +#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) +#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) +#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) +/*! WAIT_TRIG - Wait for trigger assertion before execution. + * 0b0..This command will be automatically executed. + * 0b1..The active trigger must be asserted again before executing this command. + */ +#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) +#define ADC_CMDH_LWI_MASK (0x80U) +#define ADC_CMDH_LWI_SHIFT (7U) +/*! LWI - Loop with Increment + * 0b0..Auto channel increment disabled + * 0b1..Auto channel increment enabled + */ +#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) +#define ADC_CMDH_STS_MASK (0x700U) +#define ADC_CMDH_STS_SHIFT (8U) +/*! STS - Sample Time Select + * 0b000..Minimum sample time of 3 ADCK cycles. + * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + */ +#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) +#define ADC_CMDH_AVGS_MASK (0x7000U) +#define ADC_CMDH_AVGS_SHIFT (12U) +/*! AVGS - Hardware Average Select + * 0b000..Single conversion. + * 0b001..2 conversions averaged. + * 0b010..4 conversions averaged. + * 0b011..8 conversions averaged. + * 0b100..16 conversions averaged. + * 0b101..32 conversions averaged. + * 0b110..64 conversions averaged. + * 0b111..128 conversions averaged. + */ +#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) +#define ADC_CMDH_LOOP_MASK (0xF0000U) +#define ADC_CMDH_LOOP_SHIFT (16U) +/*! LOOP - Loop Count Select + * 0b0000..Looping not enabled. Command executes 1 time. + * 0b0001..Loop 1 time. Command executes 2 times. + * 0b0010..Loop 2 times. Command executes 3 times. + * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. + * 0b1111..Loop 15 times. Command executes 16 times. + */ +#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) +#define ADC_CMDH_NEXT_MASK (0xF000000U) +#define ADC_CMDH_NEXT_SHIFT (24U) +/*! NEXT - Next Command Select + * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority + * trigger pending, begin command associated with lower priority trigger. + * 0b0001..Select CMD1 command buffer register as next command. + * 0b0010-0b1110..Select corresponding CMD command buffer register as next command + * 0b1111..Select CMD15 command buffer register as next command. + */ +#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) +/*! @} */ + +/* The count of ADC_CMDH */ +#define ADC_CMDH_COUNT (15U) + +/*! @name CV - Compare Value Register */ +/*! @{ */ +#define ADC_CV_CVL_MASK (0xFFFFU) +#define ADC_CV_CVL_SHIFT (0U) +#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) +#define ADC_CV_CVH_MASK (0xFFFF0000U) +#define ADC_CV_CVH_SHIFT (16U) +#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) +/*! @} */ + +/* The count of ADC_CV */ +#define ADC_CV_COUNT (4U) + +/*! @name RESFIFO - ADC Data Result FIFO Register */ +/*! @{ */ +#define ADC_RESFIFO_D_MASK (0xFFFFU) +#define ADC_RESFIFO_D_SHIFT (0U) +#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) +#define ADC_RESFIFO_TSRC_MASK (0xF0000U) +#define ADC_RESFIFO_TSRC_SHIFT (16U) +/*! TSRC - Trigger Source + * 0b0000..Trigger source 0 initiated this conversion. + * 0b0001..Trigger source 1 initiated this conversion. + * 0b0010-0b1110..Corresponding trigger source initiated this conversion. + * 0b1111..Trigger source 15 initiated this conversion. + */ +#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) +#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) +#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) +/*! LOOPCNT - Loop count value + * 0b0000..Result is from initial conversion in command. + * 0b0001..Result is from second conversion in command. + * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. + * 0b1111..Result is from 16th conversion in command. + */ +#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) +#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) +#define ADC_RESFIFO_CMDSRC_SHIFT (24U) +/*! CMDSRC - Command Buffer Source + * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state + * prior to an ADC conversion result dataword being stored to a RESFIFO buffer. + * 0b0001..CMD1 buffer used as control settings for this conversion. + * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. + * 0b1111..CMD15 buffer used as control settings for this conversion. + */ +#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) +#define ADC_RESFIFO_VALID_MASK (0x80000000U) +#define ADC_RESFIFO_VALID_SHIFT (31U) +/*! VALID - FIFO entry is valid + * 0b0..FIFO is empty. Discard any read from RESFIFO. + * 0b1..FIFO record read from RESFIFO is valid. + */ +#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) +/*! @} */ + +/* The count of ADC_RESFIFO */ +#define ADC_RESFIFO_COUNT (2U) + +/*! @name CAL_GAR - Calibration General A-Side Registers */ +/*! @{ */ +#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) +#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) +/*! @} */ + +/* The count of ADC_CAL_GAR */ +#define ADC_CAL_GAR_COUNT (33U) + +/*! @name CAL_GBR - Calibration General B-Side Registers */ +/*! @{ */ +#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) +#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) +/*! @} */ + +/* The count of ADC_CAL_GBR */ +#define ADC_CAL_GBR_COUNT (33U) + +/*! @name TST - ADC Test Register */ +/*! @{ */ +#define ADC_TST_CST_LONG_MASK (0x1U) +#define ADC_TST_CST_LONG_SHIFT (0U) +/*! CST_LONG - Calibration Sample Time Long + * 0b0..Normal sample time. Minimum sample time of 3 ADCK cycles. + * 0b1..Increased sample time. 67 ADCK cycles total sample time. + */ +#define ADC_TST_CST_LONG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_CST_LONG_SHIFT)) & ADC_TST_CST_LONG_MASK) +#define ADC_TST_FOFFM_MASK (0x100U) +#define ADC_TST_FOFFM_SHIFT (8U) +/*! FOFFM - Force M-side positive offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced positive offset on MDAC. + */ +#define ADC_TST_FOFFM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK) +#define ADC_TST_FOFFP_MASK (0x200U) +#define ADC_TST_FOFFP_SHIFT (9U) +/*! FOFFP - Force P-side positive offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced positive offset on PDAC. + */ +#define ADC_TST_FOFFP(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK) +#define ADC_TST_FOFFM2_MASK (0x400U) +#define ADC_TST_FOFFM2_SHIFT (10U) +/*! FOFFM2 - Force M-side negative offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced negative offset on MDAC. + */ +#define ADC_TST_FOFFM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM2_SHIFT)) & ADC_TST_FOFFM2_MASK) +#define ADC_TST_FOFFP2_MASK (0x800U) +#define ADC_TST_FOFFP2_SHIFT (11U) +/*! FOFFP2 - Force P-side negative offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced negative offset on PDAC. + */ +#define ADC_TST_FOFFP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP2_SHIFT)) & ADC_TST_FOFFP2_MASK) +#define ADC_TST_TESTEN_MASK (0x800000U) +#define ADC_TST_TESTEN_SHIFT (23U) +/*! TESTEN - Enable test configuration + * 0b0..Normal operation. Test configuration not enabled. + * 0b1..Hardware BIST Test in progress. + */ +#define ADC_TST_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_TESTEN_SHIFT)) & ADC_TST_TESTEN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x500A0000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x400A0000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x400A0000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AHB_SECURE_CTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer + * @{ + */ + +/** AHB_SECURE_CTRL - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x30 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[3]; /**< Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */ + } SEC_CTRL_FLASH_ROM[1]; + struct { /* offset: 0x30, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAMX slaves., array offset: 0x40, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_RAMX[1]; + uint8_t RESERVED_0[12]; + struct { /* offset: 0x50, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM0 slaves., array offset: 0x60, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM0[1]; + uint8_t RESERVED_1[8]; + struct { /* offset: 0x70, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM1 slaves., array offset: 0x80, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM1[1]; + uint8_t RESERVED_2[8]; + struct { /* offset: 0x90, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM2[1]; + uint8_t RESERVED_3[8]; + struct { /* offset: 0xB0, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM3 slaves., array offset: 0xB0, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM3 slaves., array offset: 0xC0, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM3[1]; + uint8_t RESERVED_4[8]; + struct { /* offset: 0xD0, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM4 slaves., array offset: 0xD0, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM4 slaves., array offset: 0xE0, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_RAM4[1]; + uint8_t RESERVED_5[12]; + struct { /* offset: 0xF0, array step: 0x30 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for both APB Bridges slaves., array offset: 0xF0, array step: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x100, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x104, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x108, array step: 0x30 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x110, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x114, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x118, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x11C, array step: 0x30 */ + } SEC_CTRL_APB_BRIDGE[1]; + __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */ + __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */ + uint8_t RESERVED_6[8]; + __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */ + __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */ + uint8_t RESERVED_7[8]; + struct { /* offset: 0x140, array step: 0x14 */ + __IO uint32_t SLAVE0_RULE; /**< Security access rules for AHB peripherals., array offset: 0x140, array step: 0x14 */ + __IO uint32_t SLAVE1_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */ + uint8_t RESERVED_0[8]; + __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x150, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_AHB_PORT10[1]; + uint8_t RESERVED_8[12]; + struct { /* offset: 0x160, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0x160, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM_USB_HS., array offset: 0x170, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_USB_HS[1]; + uint8_t RESERVED_9[3212]; + __I uint32_t SEC_VIO_ADDR[12]; /**< most recent security violation address for AHB port n, array offset: 0xE00, array step: 0x4 */ + uint8_t RESERVED_10[80]; + __I uint32_t SEC_VIO_MISC_INFO[12]; /**< most recent security violation miscellaneous information for AHB port n, array offset: 0xE80, array step: 0x4 */ + uint8_t RESERVED_11[80]; + __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */ + uint8_t RESERVED_12[124]; + __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */ + __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */ + uint8_t RESERVED_13[8]; + __IO uint32_t SEC_CPU_INT_MASK0; /**< Secure Interrupt mask for CPU1, offset: 0xF90 */ + __IO uint32_t SEC_CPU_INT_MASK1; /**< Secure Interrupt mask for CPU1, offset: 0xF94 */ + uint8_t RESERVED_14[36]; + __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */ + uint8_t RESERVED_15[16]; + __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */ + __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */ + uint8_t RESERVED_16[20]; + __IO uint32_t CPU0_LOCK_REG; /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */ + __IO uint32_t CPU1_LOCK_REG; /**< Miscalleneous control signals for in micro-Cortex M33 (CPU1), offset: 0xFF0 */ + uint8_t RESERVED_17[4]; + __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */ + __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */ +} AHB_SECURE_CTRL_Type; + +/* ---------------------------------------------------------------------------- + -- AHB_SECURE_CTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks + * @{ + */ + +/*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U) +/*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U) +/*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U) + +/*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U) + +/*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U) +/*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAMX_MEM_RULE - Security access rules for RAMX slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U) +/*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM0_MEM_RULE - Security access rules for RAM0 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT (0U) +/*! RAM1_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM1_MEM_RULE - Security access rules for RAM1 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U) +/*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM2_MEM_RULE - Security access rules for RAM2 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT (0U) +/*! RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM3_MEM_RULE - Security access rules for RAM3 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT (0U) +/*! RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM4_MEM_RULE - Security access rules for RAM4 slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U) +/*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U) +/*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U) +/*! SYSCON_RULE - System Configuration + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U) +/*! IOCON_RULE - I/O Configuration + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U) +/*! GINT0_RULE - GPIO input Interrupt 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U) +/*! GINT1_RULE - GPIO input Interrupt 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U) +/*! PINT_RULE - Pin Interrupt and Pattern match + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U) +/*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT (24U) +/*! INPUTMUX_RULE - Peripheral input multiplexing + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U) +/*! CTIMER0_RULE - Standard counter/Timer 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U) +/*! CTIMER1_RULE - Standard counter/Timer 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U) +/*! WWDT_RULE - Windiwed wtachdog Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U) +/*! MRT_RULE - Multi-rate Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U) +/*! UTICK_RULE - Micro-Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U) +/*! ANACTRL_RULE - Analog Modules controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U) +/*! PMC_RULE - Power Management Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U) +/*! SYSCTRL_RULE - System Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U) +/*! CTIMER2_RULE - Standard counter/Timer 2 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U) +/*! CTIMER3_RULE - Standard counter/Timer 3 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U) +/*! CTIMER4_RULE - Standard counter/Timer 4 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U) +/*! RTC_RULE - Real Time Counter + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U) +/*! OSEVENT_RULE - OS Event Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U) +/*! FLASH_CTRL_RULE - Flash Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U) +/*! PRINCE_RULE - Prince + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U) +/*! USBHPHY_RULE - USB High Speed Phy controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U) +/*! RNG_RULE - True Random Number Generator + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT (12U) +/*! PUF_RULE - PUF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U) +/*! PLU_RULE - Programmable Look-Up logic + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U) + +/*! @name SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT (8U) +/*! DMA0_RULE - DMA Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT (16U) +/*! FS_USB_DEV_RULE - USB Full-speed device + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT (20U) +/*! SCT_RULE - SCTimer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT (24U) +/*! FLEXCOMM0_RULE - Flexcomm interface 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT (28U) +/*! FLEXCOMM1_RULE - Flexcomm interface 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT (0U) +/*! FLEXCOMM2_RULE - Flexcomm interface 2 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT (4U) +/*! FLEXCOMM3_RULE - Flexcomm interface 3 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT (8U) +/*! FLEXCOMM4_RULE - Flexcomm interface 4 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT (12U) +/*! MAILBOX_RULE - Inter CPU communication Mailbox + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT (16U) +/*! GPIO0_RULE - High Speed GPIO + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT (16U) +/*! USB_HS_DEV_RULE - USB high Speed device registers + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT (20U) +/*! CRC_RULE - CRC engine + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT (24U) +/*! FLEXCOMM5_RULE - Flexcomm interface 5 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT (28U) +/*! FLEXCOMM6_RULE - Flexcomm interface 6 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT (0U) +/*! FLEXCOMM7_RULE - Flexcomm interface 7 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT (12U) +/*! SDIO_RULE - SDMMC card interface + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT (16U) +/*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT (28U) +/*! HS_LSPI_RULE - High Speed SPI + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB_PORT10_SLAVE0_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT (0U) +/*! ADC_RULE - ADC + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT (8U) +/*! USB_FS_HOST_RULE - USB Full Speed Host registers. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT (12U) +/*! USB_HS_HOST_RULE - USB High speed host registers + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT (16U) +/*! HASH_RULE - SHA-2 crypto registers + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT (20U) +/*! CASPER_RULE - RSA/ECC crypto accelerator + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT (24U) +/*! PQ_RULE - Power Quad (CPU0 processor hardware accelerator) + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT (28U) +/*! DMA1_RULE - DMA Controller (Secure) + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_COUNT (1U) + +/*! @name SEC_CTRL_AHB_PORT10_SLAVE1_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT (0U) +/*! GPIO1_RULE - Secure High Speed GPIO + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U) +/*! AHB_SEC_CTRL_RULE - AHB Secure Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_COUNT (1U) + +/*! @name SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U) +/*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U) +/*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U) +/*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U) +/*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U) +/*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U) +/*! SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U) +/*! SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U) +/*! SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U) +/*! SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_VIO_ADDR - most recent security violation address for AHB port n */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */ +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (12U) + +/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB port n */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) +/*! SEC_VIO_INFO_WRITE - security violation access read/write indicator. + * 0b0..Read access. + * 0b1..Write access. + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) +/*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator. + * 0b0..Code access. + * 0b1..Data access. + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) +/*! SEC_VIO_INFO_MASTER - security violation master number + * 0b0000..CPU0 Code. + * 0b0001..CPU0 System. + * 0b0010..CPU1 Data. + * 0b0011..CPU1 System. + * 0b0100..USB-HS Device. + * 0b0101..SDMA0. + * 0b1000..SDIO. + * 0b1001..PowerQuad. + * 0b1010..HASH. + * 0b1011..USB-FS Host. + * 0b1100..SDMA1. + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (12U) + +/*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) +/*! VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) +/*! VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) +/*! VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) +/*! VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) +/*! VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) +/*! VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) +/*! VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) +/*! VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) +/*! VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) +/*! VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U) +/*! VIO_INFO_VALID10 - violation information valid flag for AHB port 10. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U) +/*! VIO_INFO_VALID11 - violation information valid flag for AHB port 11. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK) +/*! @} */ + +/*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK) +/*! @} */ + +/*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK) +/*! @} */ + +/*! @name SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT (0U) +/*! SYS_IRQ - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT (1U) +/*! SDMA0_IRQ - System DMA 0 (non-secure) interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT (2U) +/*! GPIO_GLOBALINT0_IRQ - GPIO Group 0 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT (3U) +/*! GPIO_GLOBALINT1_IRQ - GPIO Group 1 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT (4U) +/*! GPIO_INT0_IRQ0 - Pin interrupt 0 or pattern match engine slice 0 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT (5U) +/*! GPIO_INT0_IRQ1 - Pin interrupt 1 or pattern match engine slice 1 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT (6U) +/*! GPIO_INT0_IRQ2 - Pin interrupt 2 or pattern match engine slice 2 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT (7U) +/*! GPIO_INT0_IRQ3 - Pin interrupt 3 or pattern match engine slice 3 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT (8U) +/*! UTICK_IRQ - Micro Tick Timer interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT (9U) +/*! MRT_IRQ - Multi-Rate Timer interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT (10U) +/*! CTIMER0_IRQ - Standard counter/timer 0 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT (11U) +/*! CTIMER1_IRQ - Standard counter/timer 1 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT (12U) +/*! SCT_IRQ - SCTimer/PWM interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT (13U) +/*! CTIMER3_IRQ - Standard counter/timer 3 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT (14U) +/*! FLEXCOMM0_IRQ - Flexcomm 0 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT (15U) +/*! FLEXCOMM1_IRQ - Flexcomm 1 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT (16U) +/*! FLEXCOMM2_IRQ - Flexcomm 2 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT (17U) +/*! FLEXCOMM3_IRQ - Flexcomm 3 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT (18U) +/*! FLEXCOMM4_IRQ - Flexcomm 4 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT (19U) +/*! FLEXCOMM5_IRQ - Flexcomm 5 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT (20U) +/*! FLEXCOMM6_IRQ - Flexcomm 6 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT (21U) +/*! FLEXCOMM7_IRQ - Flexcomm 7 interrupt (USART, SPI, I2C, I2S). + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT (22U) +/*! ADC_IRQ - General Purpose ADC interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT (23U) +/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT (24U) +/*! ACMP_IRQ - Analog Comparator interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT (25U) +/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT (26U) +/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT (27U) +/*! USB0_NEEDCLK - USB Full Speed Controller Clock request interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK (0x10000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT (28U) +/*! USB0_IRQ - USB Full Speed Controller interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK (0x20000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT (29U) +/*! RTC_IRQ - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK (0x40000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT (30U) +/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK (0x80000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT (31U) +/*! MAILBOX_IRQ - Mailbox interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK) +/*! @} */ + +/*! @name SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT (0U) +/*! GPIO_INT0_IRQ4 - Pin interrupt 4 or pattern match engine slice 4 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT (1U) +/*! GPIO_INT0_IRQ5 - Pin interrupt 5 or pattern match engine slice 5 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT (2U) +/*! GPIO_INT0_IRQ6 - Pin interrupt 6 or pattern match engine slice 6 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT (3U) +/*! GPIO_INT0_IRQ7 - Pin interrupt 7 or pattern match engine slice 7 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT (4U) +/*! CTIMER2_IRQ - Standard counter/timer 2 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT (5U) +/*! CTIMER4_IRQ - Standard counter/timer 4 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT (6U) +/*! OS_EVENT_TIMER_IRQ - OS Event Timer and OS Event Timer Wakeup interrupts + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT (7U) +/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT (8U) +/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT (9U) +/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT (10U) +/*! SDIO_IRQ - SDIO Controller interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT (11U) +/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT (12U) +/*! RESERVED4 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT (13U) +/*! RESERVED5 - Reserved. Read value is undefined, only zero should be written. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT (14U) +/*! USB1_PHY_IRQ - USB High Speed PHY Controller interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT (15U) +/*! USB1_IRQ - USB High Speed Controller interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT (16U) +/*! USB1_NEEDCLK - USB High Speed Controller Clock request interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT (17U) +/*! SEC_HYPERVISOR_CALL_IRQ - Secure fault Hyper Visor call interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT (18U) +/*! SEC_GPIO_INT0_IRQ0 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT (19U) +/*! SEC_GPIO_INT0_IRQ1 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT (20U) +/*! PLU_IRQ - Programmable Look-Up Controller interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT (21U) +/*! SEC_VIO_IRQ - Security Violation interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT (22U) +/*! SHA_IRQ - HASH-AES interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT (23U) +/*! CASPER_IRQ - CASPER interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT (24U) +/*! PUFKEY_IRQ - PUF interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT (25U) +/*! PQ_IRQ - Power Quad interrupt. + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT (26U) +/*! SDMA1_IRQ - System DMA 1 (Secure) interrupt + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT (27U) +/*! LSPI_HS_IRQ - High Speed SPI interrupt + * 0b0.. + * 0b1.. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK) +/*! @} */ + +/*! @name SEC_MASK_LOCK - Security General Purpose register access control. */ +/*! @{ */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) +/*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) +/*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (8U) +/*! SEC_CPU1_INT_MASK0_LOCK - SEC_CPU_INT_MASK0 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC00U) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (10U) +/*! SEC_CPU1_INT_MASK1_LOCK - SEC_CPU_INT_MASK1 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK) +/*! @} */ + +/*! @name MASTER_SEC_LEVEL - master secure level register */ +/*! @{ */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK (0x30U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT (4U) +/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK (0xC0U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT (6U) +/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U) +/*! USBFSD - USB Full Speed Device. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U) +/*! SDMA0 - System DMA 0. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK (0x30000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT (16U) +/*! SDIO - SDIO. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK (0xC0000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT (18U) +/*! PQ - Power Quad. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U) +/*! HASH - Hash. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U) +/*! USBFSH - USB Full speed Host. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U) +/*! SDMA1 - System DMA 1 security level. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) +/*! @} */ + +/*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */ +/*! @{ */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK (0x30U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT (4U) +/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK (0xC0U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT (6U) +/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U) +/*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U) +/*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK (0x30000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT (16U) +/*! SDIO - SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0xC0000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (18U) +/*! PQ - Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U) +/*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U) +/*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U) +/*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) +/*! @} */ + +/*! @name CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) */ +/*! @{ */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) +/*! LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) +/*! LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) +/*! LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U) +/*! LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U) +/*! LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT (30U) +/*! CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK) +/*! @} */ + +/*! @name CPU1_LOCK_REG - Miscalleneous control signals for in micro-Cortex M33 (CPU1) */ +/*! @{ */ +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) +/*! LOCK_NS_VTOR - micro-Cortex M33 (CPU1) VTOR_NS register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) +/*! LOCK_NS_MPU - micro-Cortex M33 (CPU1) non-secure MPU register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT (30U) +/*! CPU1_LOCK_REG_LOCK - CPU1_LOCK_REG write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK) +/*! @} */ + +/*! @name MISC_CTRL_DP_REG - secure control duplicate register */ +/*! @{ */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - Write lock. + * 0b10..Secure control registers can be written. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. + * 0b10..Enable abort fort secure checker. + * 0b01..Disable abort fort secure checker. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) +/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. + * 0b10..Simple master in strict mode. + * 0b01..Simple master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) +/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. + * 0b10..Smart master in strict mode. + * 0b01..Smart master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - Disable IDAU. + * 0b10..IDAU is enabled. + * 0b01..IDAU is disable. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) +/*! @} */ + +/*! @name MISC_CTRL_REG - secure control register */ +/*! @{ */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - Write lock. + * 0b10..Secure control registers can be written. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. + * 0b10..Enable abort fort secure checker. + * 0b01..Disable abort fort secure checker. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) +/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. + * 0b10..Simple master in strict mode. + * 0b01..Simple master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) +/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. + * 0b10..Smart master in strict mode. + * 0b01..Smart master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - Disable IDAU. + * 0b10..IDAU is enabled. + * 0b01..IDAU is disable. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group AHB_SECURE_CTRL_Register_Masks */ + + +/* AHB_SECURE_CTRL - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE (0x500AC000u) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS) + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS } +#else + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE (0x400AC000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } +#endif + +/*! + * @} + */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ANACTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer + * @{ + */ + +/** ANACTRL - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */ + __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */ + __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */ + uint8_t RESERVED_2[8]; + __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */ + __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status register, offset: 0x24 */ + uint8_t RESERVED_3[8]; + __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */ + __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */ + uint8_t RESERVED_4[8]; + __IO uint32_t RINGO0_CTRL; /**< First Ring Oscillator module control register., offset: 0x40 */ + __IO uint32_t RINGO1_CTRL; /**< Second Ring Oscillator module control register., offset: 0x44 */ + __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */ + uint8_t RESERVED_5[180]; + __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */ +} ANACTRL_Type; + +/* ---------------------------------------------------------------------------- + -- ANACTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks + * @{ + */ + +/*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */ +/*! @{ */ +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U) +/*! FLASH_PWRDWN - Flash Power Down status. + * 0b0..Flash is not in power down mode. + * 0b1..Flash is in power down mode. + */ +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U) +/*! FLASH_INIT_ERROR - Flash initialization error status. + * 0b0..No error. + * 0b1..At least one error occured during flash initialization.. + */ +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK) +/*! @} */ + +/*! @name FREQ_ME_CTRL - Frequency Measure function control register */ +/*! @{ */ +#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU) +#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U) +#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK) +#define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U) +#define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U) +#define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK) +/*! @} */ + +/*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */ +/*! @{ */ +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U) +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U) +/*! ENA_12MHZCLK - 12 MHz clock control. + * 0b0..12 MHz clock is disabled. + * 0b1..12 MHz clock is enabled. + */ +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) +#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK (0x8000U) +#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT (15U) +/*! ENA_48MHZCLK - 48 MHz clock control. + * 0b0..Reserved. + * 0b1..48 MHz clock is enabled. + */ +#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK) +#define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U) +#define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U) +#define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK) +#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U) +#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U) +#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK) +#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U) +#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U) +#define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK) +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U) +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U) +/*! ENA_96MHZCLK - 96 MHz clock control. + * 0b0..96 MHz clock is disabled. + * 0b1..96 MHz clock is enabled. + */ +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) +/*! @} */ + +/*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */ +/*! @{ */ +#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U) +#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U) +/*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. + * 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). + * 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by + * FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). + */ +#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK) +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U) +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U) +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK) +/*! @} */ + +/*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */ +/*! @{ */ +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U) +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U) +/*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. + * 0b0..XO AC buffer bypass is disabled. + * 0b1..XO AC buffer bypass is enabled. + */ +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK) +#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U) +#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U) +/*! ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL. + * 0b0..High speed Crystal oscillator output to USB HS PLL is disabled. + * 0b1..High speed Crystal oscillator output to USB HS PLL is enabled. + */ +#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U) +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U) +/*! ENABLE_SYSTEM_CLK_OUT - Enable XO 32 MHz output to CPU system. + * 0b0..High speed Crystal oscillator output to CPU system is disabled. + * 0b1..High speed Crystal oscillator output to CPU system is enabled. + */ +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) +/*! @} */ + +/*! @name XO32M_STATUS - High speed Crystal Oscillator Status register */ +/*! @{ */ +#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U) +#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U) +/*! XO_READY - Indicates XO out frequency statibilty. + * 0b0..XO output frequency is not yet stable. + * 0b1..XO output frequency is stable. + */ +#define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK) +/*! @} */ + +/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */ +/*! @{ */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U) +/*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control. + * 0b0..BOD VBAT interrupt is disabled. + * 0b1..BOD VBAT interrupt is enabled. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U) +/*! BODCORE_INT_ENABLE - BOD CORE interrupt control. + * 0b0..BOD CORE interrupt is disabled. + * 0b1..BOD CORE interrupt is enabled. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U) +/*! DCDC_INT_ENABLE - DCDC interrupt control. + * 0b0..DCDC interrupt is disabled. + * 0b1..DCDC interrupt is enabled. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK) +/*! @} */ + +/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */ +/*! @{ */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U) +/*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U) +/*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U) +/*! BODVBAT_VAL - Current value of BOD VBAT power status output. + * 0b0..VBAT voltage level is below the threshold. + * 0b1..VBAT voltage level is above the threshold. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U) +/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U) +/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U) +/*! BODCORE_VAL - Current value of BOD CORE power status output. + * 0b0..CORE voltage level is below the threshold. + * 0b1..CORE voltage level is above the threshold. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U) +/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U) +/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U) +/*! DCDC_VAL - Current value of DCDC power status output. + * 0b0..DCDC output Voltage is below the targeted regulation level. + * 0b1..DCDC output Voltage is above the targeted regulation level. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK) +/*! @} */ + +/*! @name RINGO0_CTRL - First Ring Oscillator module control register. */ +/*! @{ */ +#define ANACTRL_RINGO0_CTRL_SL_MASK (0x1U) +#define ANACTRL_RINGO0_CTRL_SL_SHIFT (0U) +/*! SL - Select short or long ringo (for all ringos types). + * 0b0..Select short ringo (few elements). + * 0b1..Select long ringo (many elements). + */ +#define ANACTRL_RINGO0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK) +#define ANACTRL_RINGO0_CTRL_FS_MASK (0x2U) +#define ANACTRL_RINGO0_CTRL_FS_SHIFT (1U) +/*! FS - Ringo frequency output divider. + * 0b0..High frequency output (frequency lower than 100 MHz). + * 0b1..Low frequency output (frequency lower than 10 MHz). + */ +#define ANACTRL_RINGO0_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK) +#define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK (0xCU) +#define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT (2U) +/*! SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control. + * 0b00..Normal mode. + * 0b01..P-Monitor mode. Measure with weak P transistor. + * 0b10..P-Monitor mode. Measure with weak N transistor. + * 0b11..Don't use. + */ +#define ANACTRL_RINGO0_CTRL_SWN_SWP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK) +#define ANACTRL_RINGO0_CTRL_PD_MASK (0x10U) +#define ANACTRL_RINGO0_CTRL_PD_SHIFT (4U) +/*! PD - Ringo module Power control. + * 0b0..The Ringo module is enabled. + * 0b1..The Ringo module is disabled. + */ +#define ANACTRL_RINGO0_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK) +#define ANACTRL_RINGO0_CTRL_E_ND0_MASK (0x20U) +#define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT (5U) +/*! E_ND0 - First NAND2-based ringo control. + * 0b0..First NAND2-based ringo is disabled. + * 0b1..First NAND2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_ND0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK) +#define ANACTRL_RINGO0_CTRL_E_ND1_MASK (0x40U) +#define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT (6U) +/*! E_ND1 - Second NAND2-based ringo control. + * 0b0..Second NAND2-based ringo is disabled. + * 0b1..Second NAND2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_ND1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK) +#define ANACTRL_RINGO0_CTRL_E_NR0_MASK (0x80U) +#define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT (7U) +/*! E_NR0 - First NOR2-based ringo control. + * 0b0..First NOR2-based ringo is disabled. + * 0b1..First NOR2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_NR0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK) +#define ANACTRL_RINGO0_CTRL_E_NR1_MASK (0x100U) +#define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT (8U) +/*! E_NR1 - Second NOR2-based ringo control. + * 0b0..Second NORD2-based ringo is disabled. + * 0b1..Second NORD2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_NR1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK) +#define ANACTRL_RINGO0_CTRL_E_IV0_MASK (0x200U) +#define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT (9U) +/*! E_IV0 - First Inverter-based ringo control. + * 0b0..First INV-based ringo is disabled. + * 0b1..First INV-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_IV0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK) +#define ANACTRL_RINGO0_CTRL_E_IV1_MASK (0x400U) +#define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT (10U) +/*! E_IV1 - Second Inverter-based ringo control. + * 0b0..Second INV-based ringo is disabled. + * 0b1..Second INV-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_IV1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK) +#define ANACTRL_RINGO0_CTRL_E_PN0_MASK (0x800U) +#define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT (11U) +/*! E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control. + * 0b0..First PN-based ringo is disabled. + * 0b1..First PN-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_PN0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK) +#define ANACTRL_RINGO0_CTRL_E_PN1_MASK (0x1000U) +#define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT (12U) +/*! E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control. + * 0b0..Second PN-based ringo is disabled. + * 0b1..Second PN-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_PN1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK) +#define ANACTRL_RINGO0_CTRL_DIVISOR_MASK (0xF0000U) +#define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT (16U) +#define ANACTRL_RINGO0_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK) +#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) +#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK) +/*! @} */ + +/*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */ +/*! @{ */ +#define ANACTRL_RINGO1_CTRL_S_MASK (0x1U) +#define ANACTRL_RINGO1_CTRL_S_SHIFT (0U) +/*! S - Select short or long ringo (for all ringos types). + * 0b0..Select short ringo (few elements). + * 0b1..Select long ringo (many elements). + */ +#define ANACTRL_RINGO1_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK) +#define ANACTRL_RINGO1_CTRL_FS_MASK (0x2U) +#define ANACTRL_RINGO1_CTRL_FS_SHIFT (1U) +/*! FS - Ringo frequency output divider. + * 0b0..High frequency output (frequency lower than 100 MHz). + * 0b1..Low frequency output (frequency lower than 10 MHz). + */ +#define ANACTRL_RINGO1_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK) +#define ANACTRL_RINGO1_CTRL_PD_MASK (0x4U) +#define ANACTRL_RINGO1_CTRL_PD_SHIFT (2U) +/*! PD - Ringo module Power control. + * 0b0..The Ringo module is enabled. + * 0b1..The Ringo module is disabled. + */ +#define ANACTRL_RINGO1_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK) +#define ANACTRL_RINGO1_CTRL_E_R24_MASK (0x8U) +#define ANACTRL_RINGO1_CTRL_E_R24_SHIFT (3U) +/*! E_R24 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK) +#define ANACTRL_RINGO1_CTRL_E_R35_MASK (0x10U) +#define ANACTRL_RINGO1_CTRL_E_R35_SHIFT (4U) +/*! E_R35 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK) +#define ANACTRL_RINGO1_CTRL_E_M2_MASK (0x20U) +#define ANACTRL_RINGO1_CTRL_E_M2_SHIFT (5U) +/*! E_M2 - Metal 2 (M2) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK) +#define ANACTRL_RINGO1_CTRL_E_M3_MASK (0x40U) +#define ANACTRL_RINGO1_CTRL_E_M3_SHIFT (6U) +/*! E_M3 - Metal 3 (M3) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK) +#define ANACTRL_RINGO1_CTRL_E_M4_MASK (0x80U) +#define ANACTRL_RINGO1_CTRL_E_M4_SHIFT (7U) +/*! E_M4 - Metal 4 (M4) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK) +#define ANACTRL_RINGO1_CTRL_E_M5_MASK (0x100U) +#define ANACTRL_RINGO1_CTRL_E_M5_SHIFT (8U) +/*! E_M5 - Metal 5 (M5) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK) +#define ANACTRL_RINGO1_CTRL_DIVISOR_MASK (0xF0000U) +#define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT (16U) +#define ANACTRL_RINGO1_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK) +#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) +#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK) +/*! @} */ + +/*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */ +/*! @{ */ +#define ANACTRL_RINGO2_CTRL_S_MASK (0x1U) +#define ANACTRL_RINGO2_CTRL_S_SHIFT (0U) +/*! S - Select short or long ringo (for all ringos types). + * 0b0..Select short ringo (few elements). + * 0b1..Select long ringo (many elements). + */ +#define ANACTRL_RINGO2_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK) +#define ANACTRL_RINGO2_CTRL_FS_MASK (0x2U) +#define ANACTRL_RINGO2_CTRL_FS_SHIFT (1U) +/*! FS - Ringo frequency output divider. + * 0b0..High frequency output (frequency lower than 100 MHz). + * 0b1..Low frequency output (frequency lower than 10 MHz). + */ +#define ANACTRL_RINGO2_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK) +#define ANACTRL_RINGO2_CTRL_PD_MASK (0x4U) +#define ANACTRL_RINGO2_CTRL_PD_SHIFT (2U) +/*! PD - Ringo module Power control. + * 0b0..The Ringo module is enabled. + * 0b1..The Ringo module is disabled. + */ +#define ANACTRL_RINGO2_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK) +#define ANACTRL_RINGO2_CTRL_E_R24_MASK (0x8U) +#define ANACTRL_RINGO2_CTRL_E_R24_SHIFT (3U) +/*! E_R24 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK) +#define ANACTRL_RINGO2_CTRL_E_R35_MASK (0x10U) +#define ANACTRL_RINGO2_CTRL_E_R35_SHIFT (4U) +/*! E_R35 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK) +#define ANACTRL_RINGO2_CTRL_E_M2_MASK (0x20U) +#define ANACTRL_RINGO2_CTRL_E_M2_SHIFT (5U) +/*! E_M2 - Metal 2 (M2) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK) +#define ANACTRL_RINGO2_CTRL_E_M3_MASK (0x40U) +#define ANACTRL_RINGO2_CTRL_E_M3_SHIFT (6U) +/*! E_M3 - Metal 3 (M3) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK) +#define ANACTRL_RINGO2_CTRL_E_M4_MASK (0x80U) +#define ANACTRL_RINGO2_CTRL_E_M4_SHIFT (7U) +/*! E_M4 - Metal 4 (M4) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK) +#define ANACTRL_RINGO2_CTRL_E_M5_MASK (0x100U) +#define ANACTRL_RINGO2_CTRL_E_M5_SHIFT (8U) +/*! E_M5 - Metal 5 (M5) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK) +#define ANACTRL_RINGO2_CTRL_DIVISOR_MASK (0xF0000U) +#define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT (16U) +#define ANACTRL_RINGO2_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK) +#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) +#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK) +/*! @} */ + +/*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */ +/*! @{ */ +#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK (0x1U) +#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT (0U) +#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK) +#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK (0x2U) +#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT (1U) +#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK) +#define ANACTRL_USBHS_PHY_CTRL_iso_atx_MASK (0x8U) +#define ANACTRL_USBHS_PHY_CTRL_iso_atx_SHIFT (3U) +#define ANACTRL_USBHS_PHY_CTRL_iso_atx(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_iso_atx_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_iso_atx_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ANACTRL_Register_Masks */ + + +/* ANACTRL - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE (0x50013000u) + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE_NS (0x40013000u) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS) + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS { ANACTRL } + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS } +#else + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE (0x40013000u) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS { ANACTRL } +#endif + +/*! + * @} + */ /* end of group ANACTRL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CASPER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CASPER_Peripheral_Access_Layer CASPER Peripheral Access Layer + * @{ + */ + +/** CASPER - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL0; /**< Contains the offsets of AB and CD in the RAM., offset: 0x0 */ + __IO uint32_t CTRL1; /**< Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR., offset: 0x4 */ + __IO uint32_t LOADER; /**< Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations., offset: 0x8 */ + __IO uint32_t STATUS; /**< Indicates operational status and would contain the carry bit if used., offset: 0xC */ + __IO uint32_t INTENSET; /**< Sets interrupts, offset: 0x10 */ + __IO uint32_t INTENCLR; /**< Clears interrupts, offset: 0x14 */ + __I uint32_t INTSTAT; /**< Interrupt status bits (mask of INTENSET and STATUS), offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t AREG; /**< A register, offset: 0x20 */ + __IO uint32_t BREG; /**< B register, offset: 0x24 */ + __IO uint32_t CREG; /**< C register, offset: 0x28 */ + __IO uint32_t DREG; /**< D register, offset: 0x2C */ + __IO uint32_t RES0; /**< Result register 0, offset: 0x30 */ + __IO uint32_t RES1; /**< Result register 1, offset: 0x34 */ + __IO uint32_t RES2; /**< Result register 2, offset: 0x38 */ + __IO uint32_t RES3; /**< Result register 3, offset: 0x3C */ + uint8_t RESERVED_1[32]; + __IO uint32_t MASK; /**< Optional mask register, offset: 0x60 */ + __IO uint32_t REMASK; /**< Optional re-mask register, offset: 0x64 */ + uint8_t RESERVED_2[24]; + __IO uint32_t LOCK; /**< Security lock register, offset: 0x80 */ +} CASPER_Type; + +/* ---------------------------------------------------------------------------- + -- CASPER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CASPER_Register_Masks CASPER Register Masks + * @{ + */ + +/*! @name CTRL0 - Contains the offsets of AB and CD in the RAM. */ +/*! @{ */ +#define CASPER_CTRL0_ABBPAIR_MASK (0x1U) +#define CASPER_CTRL0_ABBPAIR_SHIFT (0U) +/*! ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_CTRL0_ABBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK) +#define CASPER_CTRL0_ABOFF_MASK (0x4U) +#define CASPER_CTRL0_ABOFF_SHIFT (2U) +#define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK) +#define CASPER_CTRL0_CDBPAIR_MASK (0x10000U) +#define CASPER_CTRL0_CDBPAIR_SHIFT (16U) +/*! CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_CTRL0_CDBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK) +#define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U) +#define CASPER_CTRL0_CDOFF_SHIFT (18U) +#define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK) +/*! @} */ + +/*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */ +/*! @{ */ +#define CASPER_CTRL1_ITER_MASK (0xFFU) +#define CASPER_CTRL1_ITER_SHIFT (0U) +#define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK) +#define CASPER_CTRL1_MODE_MASK (0xFF00U) +#define CASPER_CTRL1_MODE_SHIFT (8U) +#define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK) +#define CASPER_CTRL1_RESBPAIR_MASK (0x10000U) +#define CASPER_CTRL1_RESBPAIR_SHIFT (16U) +/*! RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally + * this is not the same bank as ABBPAIR (when 4-up supported) + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_CTRL1_RESBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK) +#define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U) +#define CASPER_CTRL1_RESOFF_SHIFT (18U) +#define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK) +#define CASPER_CTRL1_CSKIP_MASK (0xC0000000U) +#define CASPER_CTRL1_CSKIP_SHIFT (30U) +/*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: + * 0b00..No Skip + * 0b01..Skip if Carry is 1 + * 0b10..Skip if Carry is 0 + * 0b11..Set CTRLOFF to CDOFF and Skip + */ +#define CASPER_CTRL1_CSKIP(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK) +/*! @} */ + +/*! @name LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. */ +/*! @{ */ +#define CASPER_LOADER_COUNT_MASK (0xFFU) +#define CASPER_LOADER_COUNT_SHIFT (0U) +#define CASPER_LOADER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK) +#define CASPER_LOADER_CTRLBPAIR_MASK (0x10000U) +#define CASPER_LOADER_CTRLBPAIR_SHIFT (16U) +/*! CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not + * matter which bank is used as this is loaded when not performing an operation. + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_LOADER_CTRLBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK) +#define CASPER_LOADER_CTRLOFF_MASK (0x1FFC0000U) +#define CASPER_LOADER_CTRLOFF_SHIFT (18U) +#define CASPER_LOADER_CTRLOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK) +/*! @} */ + +/*! @name STATUS - Indicates operational status and would contain the carry bit if used. */ +/*! @{ */ +#define CASPER_STATUS_DONE_MASK (0x1U) +#define CASPER_STATUS_DONE_SHIFT (0U) +/*! DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. + * 0b0..Busy or just cleared + * 0b1..Completed last operation + */ +#define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK) +#define CASPER_STATUS_CARRY_MASK (0x10U) +#define CASPER_STATUS_CARRY_SHIFT (4U) +/*! CARRY - Last carry value if operation produced a carry bit + * 0b0..Carry was 0 or no carry + * 0b1..Carry was 1 + */ +#define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK) +#define CASPER_STATUS_BUSY_MASK (0x20U) +#define CASPER_STATUS_BUSY_SHIFT (5U) +/*! BUSY - Indicates if the accelerator is busy performing an operation + * 0b0..Not busy - is idle + * 0b1..Is busy + */ +#define CASPER_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK) +/*! @} */ + +/*! @name INTENSET - Sets interrupts */ +/*! @{ */ +#define CASPER_INTENSET_DONE_MASK (0x1U) +#define CASPER_INTENSET_DONE_SHIFT (0U) +/*! DONE - Set if the accelerator should interrupt when done. + * 0b0..Do not interrupt when done + * 0b1..Interrupt when done + */ +#define CASPER_INTENSET_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK) +/*! @} */ + +/*! @name INTENCLR - Clears interrupts */ +/*! @{ */ +#define CASPER_INTENCLR_DONE_MASK (0x1U) +#define CASPER_INTENCLR_DONE_SHIFT (0U) +/*! DONE - Written to clear an interrupt set with INTENSET. + * 0b0..If written 0, ignored + * 0b1..If written 1, do not Interrupt when done + */ +#define CASPER_INTENCLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) */ +/*! @{ */ +#define CASPER_INTSTAT_DONE_MASK (0x1U) +#define CASPER_INTSTAT_DONE_SHIFT (0U) +/*! DONE - If set, interrupt is caused by accelerator being done. + * 0b0..Not caused by accelerator being done + * 0b1..Caused by accelerator being done + */ +#define CASPER_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK) +/*! @} */ + +/*! @name AREG - A register */ +/*! @{ */ +#define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_AREG_REG_VALUE_SHIFT (0U) +#define CASPER_AREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name BREG - B register */ +/*! @{ */ +#define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_BREG_REG_VALUE_SHIFT (0U) +#define CASPER_BREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name CREG - C register */ +/*! @{ */ +#define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_CREG_REG_VALUE_SHIFT (0U) +#define CASPER_CREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name DREG - D register */ +/*! @{ */ +#define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_DREG_REG_VALUE_SHIFT (0U) +#define CASPER_DREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES0 - Result register 0 */ +/*! @{ */ +#define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES0_REG_VALUE_SHIFT (0U) +#define CASPER_RES0_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES1 - Result register 1 */ +/*! @{ */ +#define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES1_REG_VALUE_SHIFT (0U) +#define CASPER_RES1_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES2 - Result register 2 */ +/*! @{ */ +#define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES2_REG_VALUE_SHIFT (0U) +#define CASPER_RES2_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES3 - Result register 3 */ +/*! @{ */ +#define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES3_REG_VALUE_SHIFT (0U) +#define CASPER_RES3_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK) +/*! @} */ + +/*! @name MASK - Optional mask register */ +/*! @{ */ +#define CASPER_MASK_MASK_MASK (0xFFFFFFFFU) +#define CASPER_MASK_MASK_SHIFT (0U) +#define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK) +/*! @} */ + +/*! @name REMASK - Optional re-mask register */ +/*! @{ */ +#define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU) +#define CASPER_REMASK_MASK_SHIFT (0U) +#define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK) +/*! @} */ + +/*! @name LOCK - Security lock register */ +/*! @{ */ +#define CASPER_LOCK_LOCK_MASK (0x1U) +#define CASPER_LOCK_LOCK_SHIFT (0U) +/*! LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. + * 0b0..unlock + * 0b1..Lock to current security level + */ +#define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK) +#define CASPER_LOCK_KEY_MASK (0x1FFF0U) +#define CASPER_LOCK_KEY_SHIFT (4U) +/*! KEY - Must be written as 0x73D to change the register. + * 0b0011100111101..If set during write, will allow lock or unlock + */ +#define CASPER_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CASPER_Register_Masks */ + + +/* CASPER - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral CASPER base address */ + #define CASPER_BASE (0x500A5000u) + /** Peripheral CASPER base address */ + #define CASPER_BASE_NS (0x400A5000u) + /** Peripheral CASPER base pointer */ + #define CASPER ((CASPER_Type *)CASPER_BASE) + /** Peripheral CASPER base pointer */ + #define CASPER_NS ((CASPER_Type *)CASPER_BASE_NS) + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS { CASPER_BASE } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS { CASPER } + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS_NS { CASPER_BASE_NS } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS_NS { CASPER_NS } +#else + /** Peripheral CASPER base address */ + #define CASPER_BASE (0x400A5000u) + /** Peripheral CASPER base pointer */ + #define CASPER ((CASPER_Type *)CASPER_BASE) + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS { CASPER_BASE } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS { CASPER } +#endif + +/*! + * @} + */ /* end of group CASPER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ + __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ + union { /* offset: 0x8 */ + __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ + __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name MODE - CRC mode register */ +/*! @{ */ +#define CRC_MODE_CRC_POLY_MASK (0x3U) +#define CRC_MODE_CRC_POLY_SHIFT (0U) +#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) +#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) +#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) +#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) +#define CRC_MODE_CMPL_WR_MASK (0x8U) +#define CRC_MODE_CMPL_WR_SHIFT (3U) +#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) +#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) +#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) +#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) +#define CRC_MODE_CMPL_SUM_MASK (0x20U) +#define CRC_MODE_CMPL_SUM_SHIFT (5U) +#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) +/*! @} */ + +/*! @name SEED - CRC seed register */ +/*! @{ */ +#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) +#define CRC_SEED_CRC_SEED_SHIFT (0U) +#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) +/*! @} */ + +/*! @name SUM - CRC checksum register */ +/*! @{ */ +#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) +#define CRC_SUM_CRC_SUM_SHIFT (0U) +#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) +/*! @} */ + +/*! @name WR_DATA - CRC data register */ +/*! @{ */ +#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) +#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) +#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/* CRC - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE (0x50095000u) + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE_NS (0x40095000u) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC_ENGINE } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS } +#else + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE (0x40095000u) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC_ENGINE } +#endif + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer + * @{ + */ + +/** CTIMER - Register Layout Typedef */ +typedef struct { + __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ + __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ + __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ + __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ + __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ + __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ + __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ + __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ + __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ + __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ + uint8_t RESERVED_0[48]; + __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ + __IO uint32_t PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */ + __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ +} CTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- CTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Register_Masks CTIMER Register Masks + * @{ + */ + +/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ +/*! @{ */ +#define CTIMER_IR_MR0INT_MASK (0x1U) +#define CTIMER_IR_MR0INT_SHIFT (0U) +#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) +#define CTIMER_IR_MR1INT_MASK (0x2U) +#define CTIMER_IR_MR1INT_SHIFT (1U) +#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) +#define CTIMER_IR_MR2INT_MASK (0x4U) +#define CTIMER_IR_MR2INT_SHIFT (2U) +#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) +#define CTIMER_IR_MR3INT_MASK (0x8U) +#define CTIMER_IR_MR3INT_SHIFT (3U) +#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) +#define CTIMER_IR_CR0INT_MASK (0x10U) +#define CTIMER_IR_CR0INT_SHIFT (4U) +#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) +#define CTIMER_IR_CR1INT_MASK (0x20U) +#define CTIMER_IR_CR1INT_SHIFT (5U) +#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) +#define CTIMER_IR_CR2INT_MASK (0x40U) +#define CTIMER_IR_CR2INT_SHIFT (6U) +#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) +#define CTIMER_IR_CR3INT_MASK (0x80U) +#define CTIMER_IR_CR3INT_SHIFT (7U) +#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) +/*! @} */ + +/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ +/*! @{ */ +#define CTIMER_TCR_CEN_MASK (0x1U) +#define CTIMER_TCR_CEN_SHIFT (0U) +/*! CEN - Counter enable. + * 0b0..Disabled.The counters are disabled. + * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. + */ +#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) +#define CTIMER_TCR_CRST_MASK (0x2U) +#define CTIMER_TCR_CRST_SHIFT (1U) +/*! CRST - Counter reset. + * 0b0..Disabled. Do nothing. + * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of + * the APB bus clock. The counters remain reset until TCR[1] is returned to zero. + */ +#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) +/*! @} */ + +/*! @name TC - Timer Counter */ +/*! @{ */ +#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_TC_TCVAL_SHIFT (0U) +#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) +/*! @} */ + +/*! @name PR - Prescale Register */ +/*! @{ */ +#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PR_PRVAL_SHIFT (0U) +#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) +/*! @} */ + +/*! @name PC - Prescale Counter */ +/*! @{ */ +#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PC_PCVAL_SHIFT (0U) +#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) +/*! @} */ + +/*! @name MCR - Match Control Register */ +/*! @{ */ +#define CTIMER_MCR_MR0I_MASK (0x1U) +#define CTIMER_MCR_MR0I_SHIFT (0U) +#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) +#define CTIMER_MCR_MR0R_MASK (0x2U) +#define CTIMER_MCR_MR0R_SHIFT (1U) +#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) +#define CTIMER_MCR_MR0S_MASK (0x4U) +#define CTIMER_MCR_MR0S_SHIFT (2U) +#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) +#define CTIMER_MCR_MR1I_MASK (0x8U) +#define CTIMER_MCR_MR1I_SHIFT (3U) +#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) +#define CTIMER_MCR_MR1R_MASK (0x10U) +#define CTIMER_MCR_MR1R_SHIFT (4U) +#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) +#define CTIMER_MCR_MR1S_MASK (0x20U) +#define CTIMER_MCR_MR1S_SHIFT (5U) +#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) +#define CTIMER_MCR_MR2I_MASK (0x40U) +#define CTIMER_MCR_MR2I_SHIFT (6U) +#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) +#define CTIMER_MCR_MR2R_MASK (0x80U) +#define CTIMER_MCR_MR2R_SHIFT (7U) +#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) +#define CTIMER_MCR_MR2S_MASK (0x100U) +#define CTIMER_MCR_MR2S_SHIFT (8U) +#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) +#define CTIMER_MCR_MR3I_MASK (0x200U) +#define CTIMER_MCR_MR3I_SHIFT (9U) +#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) +#define CTIMER_MCR_MR3R_MASK (0x400U) +#define CTIMER_MCR_MR3R_SHIFT (10U) +#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) +#define CTIMER_MCR_MR3S_MASK (0x800U) +#define CTIMER_MCR_MR3S_SHIFT (11U) +#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) +#define CTIMER_MCR_MR0RL_MASK (0x1000000U) +#define CTIMER_MCR_MR0RL_SHIFT (24U) +#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) +#define CTIMER_MCR_MR1RL_MASK (0x2000000U) +#define CTIMER_MCR_MR1RL_SHIFT (25U) +#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) +#define CTIMER_MCR_MR2RL_MASK (0x4000000U) +#define CTIMER_MCR_MR2RL_SHIFT (26U) +#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) +#define CTIMER_MCR_MR3RL_MASK (0x8000000U) +#define CTIMER_MCR_MR3RL_SHIFT (27U) +#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) +/*! @} */ + +/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ +/*! @{ */ +#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) +#define CTIMER_MR_MATCH_SHIFT (0U) +#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) +/*! @} */ + +/* The count of CTIMER_MR */ +#define CTIMER_MR_COUNT (4U) + +/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ +/*! @{ */ +#define CTIMER_CCR_CAP0RE_MASK (0x1U) +#define CTIMER_CCR_CAP0RE_SHIFT (0U) +#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) +#define CTIMER_CCR_CAP0FE_MASK (0x2U) +#define CTIMER_CCR_CAP0FE_SHIFT (1U) +#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) +#define CTIMER_CCR_CAP0I_MASK (0x4U) +#define CTIMER_CCR_CAP0I_SHIFT (2U) +#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) +#define CTIMER_CCR_CAP1RE_MASK (0x8U) +#define CTIMER_CCR_CAP1RE_SHIFT (3U) +#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) +#define CTIMER_CCR_CAP1FE_MASK (0x10U) +#define CTIMER_CCR_CAP1FE_SHIFT (4U) +#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) +#define CTIMER_CCR_CAP1I_MASK (0x20U) +#define CTIMER_CCR_CAP1I_SHIFT (5U) +#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) +#define CTIMER_CCR_CAP2RE_MASK (0x40U) +#define CTIMER_CCR_CAP2RE_SHIFT (6U) +#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) +#define CTIMER_CCR_CAP2FE_MASK (0x80U) +#define CTIMER_CCR_CAP2FE_SHIFT (7U) +#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) +#define CTIMER_CCR_CAP2I_MASK (0x100U) +#define CTIMER_CCR_CAP2I_SHIFT (8U) +#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) +#define CTIMER_CCR_CAP3RE_MASK (0x200U) +#define CTIMER_CCR_CAP3RE_SHIFT (9U) +#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) +#define CTIMER_CCR_CAP3FE_MASK (0x400U) +#define CTIMER_CCR_CAP3FE_SHIFT (10U) +#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) +#define CTIMER_CCR_CAP3I_MASK (0x800U) +#define CTIMER_CCR_CAP3I_SHIFT (11U) +#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) +/*! @} */ + +/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ +/*! @{ */ +#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) +#define CTIMER_CR_CAP_SHIFT (0U) +#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) +/*! @} */ + +/* The count of CTIMER_CR */ +#define CTIMER_CR_COUNT (4U) + +/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ +/*! @{ */ +#define CTIMER_EMR_EM0_MASK (0x1U) +#define CTIMER_EMR_EM0_SHIFT (0U) +#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) +#define CTIMER_EMR_EM1_MASK (0x2U) +#define CTIMER_EMR_EM1_SHIFT (1U) +#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) +#define CTIMER_EMR_EM2_MASK (0x4U) +#define CTIMER_EMR_EM2_SHIFT (2U) +#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) +#define CTIMER_EMR_EM3_MASK (0x8U) +#define CTIMER_EMR_EM3_SHIFT (3U) +#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) +#define CTIMER_EMR_EMC0_MASK (0x30U) +#define CTIMER_EMR_EMC0_SHIFT (4U) +/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) +#define CTIMER_EMR_EMC1_MASK (0xC0U) +#define CTIMER_EMR_EMC1_SHIFT (6U) +/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) +#define CTIMER_EMR_EMC2_MASK (0x300U) +#define CTIMER_EMR_EMC2_SHIFT (8U) +/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) +#define CTIMER_EMR_EMC3_MASK (0xC00U) +#define CTIMER_EMR_EMC3_SHIFT (10U) +/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) +/*! @} */ + +/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ +/*! @{ */ +#define CTIMER_CTCR_CTMODE_MASK (0x3U) +#define CTIMER_CTCR_CTMODE_SHIFT (0U) +/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment + * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC + * is incremented when the Prescale Counter matches the Prescale Register. + * 0b00..Timer Mode. Incremented every rising APB bus clock edge. + * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. + * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. + * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. + */ +#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) +#define CTIMER_CTCR_CINSEL_MASK (0xCU) +#define CTIMER_CTCR_CINSEL_SHIFT (2U) +/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which + * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input + * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be + * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the + * same timer. + * 0b00..Channel 0. CAPn.0 for CTIMERn + * 0b01..Channel 1. CAPn.1 for CTIMERn + * 0b10..Channel 2. CAPn.2 for CTIMERn + * 0b11..Channel 3. CAPn.3 for CTIMERn + */ +#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) +#define CTIMER_CTCR_ENCC_MASK (0x10U) +#define CTIMER_CTCR_ENCC_SHIFT (4U) +#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) +#define CTIMER_CTCR_SELCC_MASK (0xE0U) +#define CTIMER_CTCR_SELCC_SHIFT (5U) +/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the + * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to + * 0x3 and 0x6 to 0x7 are reserved. + * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + */ +#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) +/*! @} */ + +/*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */ +/*! @{ */ +#define CTIMER_PWMC_PWMEN0_MASK (0x1U) +#define CTIMER_PWMC_PWMEN0_SHIFT (0U) +/*! PWMEN0 - PWM mode enable for channel0. + * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. + */ +#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) +#define CTIMER_PWMC_PWMEN1_MASK (0x2U) +#define CTIMER_PWMC_PWMEN1_SHIFT (1U) +/*! PWMEN1 - PWM mode enable for channel1. + * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. + */ +#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) +#define CTIMER_PWMC_PWMEN2_MASK (0x4U) +#define CTIMER_PWMC_PWMEN2_SHIFT (2U) +/*! PWMEN2 - PWM mode enable for channel2. + * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. + */ +#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) +#define CTIMER_PWMC_PWMEN3_MASK (0x8U) +#define CTIMER_PWMC_PWMEN3_SHIFT (3U) +/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. + * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. + * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. + */ +#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) +/*! @} */ + +/*! @name MSR - Match Shadow Register */ +/*! @{ */ +#define CTIMER_MSR_SHADOW_MASK (0xFFFFFFFFU) +#define CTIMER_MSR_SHADOW_SHIFT (0U) +#define CTIMER_MSR_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOW_SHIFT)) & CTIMER_MSR_SHADOW_MASK) +/*! @} */ + +/* The count of CTIMER_MSR */ +#define CTIMER_MSR_COUNT (4U) + + +/*! + * @} + */ /* end of group CTIMER_Register_Masks */ + + +/* CTIMER - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x50008000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x40008000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x50009000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x40009000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x50028000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x40028000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x50029000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x40029000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x5002A000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x4002A000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x40008000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x40009000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x40028000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x40029000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x4002A000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/*! + * @} + */ /* end of group CTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DBGMAILBOX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DBGMAILBOX_Peripheral_Access_Layer DBGMAILBOX Peripheral Access Layer + * @{ + */ + +/** DBGMAILBOX - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */ + __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */ + __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */ + uint8_t RESERVED_0[240]; + __I uint32_t ID; /**< Identification register, offset: 0xFC */ +} DBGMAILBOX_Type; + +/* ---------------------------------------------------------------------------- + -- DBGMAILBOX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DBGMAILBOX_Register_Masks DBGMAILBOX Register Masks + * @{ + */ + +/*! @name CSW - CRC mode register */ +/*! @{ */ +#define DBGMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) +#define DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) +#define DBGMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DBGMAILBOX_CSW_RESYNCH_REQ_MASK) +#define DBGMAILBOX_CSW_REQ_PENDING_MASK (0x2U) +#define DBGMAILBOX_CSW_REQ_PENDING_SHIFT (1U) +#define DBGMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DBGMAILBOX_CSW_REQ_PENDING_MASK) +#define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) +#define DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) +#define DBGMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK) +#define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) +#define DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) +#define DBGMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK) +#define DBGMAILBOX_CSW_SOFT_RESET_MASK (0x10U) +#define DBGMAILBOX_CSW_SOFT_RESET_SHIFT (4U) +#define DBGMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DBGMAILBOX_CSW_SOFT_RESET_MASK) +#define DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) +#define DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) +#define DBGMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK) +/*! @} */ + +/*! @name REQUEST - CRC seed register */ +/*! @{ */ +#define DBGMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU) +#define DBGMAILBOX_REQUEST_REQ_SHIFT (0U) +#define DBGMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_REQUEST_REQ_SHIFT)) & DBGMAILBOX_REQUEST_REQ_MASK) +/*! @} */ + +/*! @name RETURN - Return value from ROM. */ +/*! @{ */ +#define DBGMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) +#define DBGMAILBOX_RETURN_RET_SHIFT (0U) +#define DBGMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_RETURN_RET_SHIFT)) & DBGMAILBOX_RETURN_RET_MASK) +/*! @} */ + +/*! @name ID - Identification register */ +/*! @{ */ +#define DBGMAILBOX_ID_ID_MASK (0xFFFFFFFFU) +#define DBGMAILBOX_ID_ID_SHIFT (0U) +#define DBGMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_ID_ID_SHIFT)) & DBGMAILBOX_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DBGMAILBOX_Register_Masks */ + + +/* DBGMAILBOX - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE (0x5009C000u) + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE_NS (0x4009C000u) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX_NS ((DBGMAILBOX_Type *)DBGMAILBOX_BASE_NS) + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS_NS { DBGMAILBOX_BASE_NS } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS_NS { DBGMAILBOX_NS } +#else + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE (0x4009C000u) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } +#endif + +/*! + * @} + */ /* end of group DBGMAILBOX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ + __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ + __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ + uint8_t RESERVED_0[20]; + struct { /* offset: 0x20, array step: 0x5C */ + __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ + uint8_t RESERVED_0[4]; + __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ + uint8_t RESERVED_1[4]; + __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ + uint8_t RESERVED_2[4]; + __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ + uint8_t RESERVED_4[4]; + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ + uint8_t RESERVED_5[4]; + __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ + uint8_t RESERVED_6[4]; + __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ + uint8_t RESERVED_7[4]; + __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ + uint8_t RESERVED_8[4]; + __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ + uint8_t RESERVED_9[4]; + __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ + uint8_t RESERVED_10[4]; + __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ + } COMMON[1]; + uint8_t RESERVED_1[900]; + struct { /* offset: 0x400, array step: 0x10 */ + __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ + __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ + __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } CHANNEL[23]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name CTRL - DMA control. */ +/*! @{ */ +#define DMA_CTRL_ENABLE_MASK (0x1U) +#define DMA_CTRL_ENABLE_SHIFT (0U) +/*! ENABLE - DMA controller master enable. + * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when + * disabled, but does not prevent re-triggering when the DMA controller is re-enabled. + * 0b1..Enabled. The DMA controller is enabled. + */ +#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status. */ +/*! @{ */ +#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) +#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) +/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. + * 0b0..Not pending. No enabled interrupts are pending. + * 0b1..Pending. At least one enabled interrupt is pending. + */ +#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) +#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) +#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) +/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. + * 0b0..Not pending. No error interrupts are pending. + * 0b1..Pending. At least one error interrupt is pending. + */ +#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) +/*! @} */ + +/*! @name SRAMBASE - SRAM address of the channel configuration table. */ +/*! @{ */ +#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) +#define DMA_SRAMBASE_OFFSET_SHIFT (9U) +#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) +/*! @} */ + +/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) +#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLESET */ +#define DMA_COMMON_ENABLESET_COUNT (1U) + +/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) +#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLECLR */ +#define DMA_COMMON_ENABLECLR_COUNT (1U) + +/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) +#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ACTIVE */ +#define DMA_COMMON_ACTIVE_COUNT (1U) + +/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) +#define DMA_COMMON_BUSY_BSY_SHIFT (0U) +#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) +/*! @} */ + +/* The count of DMA_COMMON_BUSY */ +#define DMA_COMMON_BUSY_COUNT (1U) + +/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) +#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ERRINT */ +#define DMA_COMMON_ERRINT_COUNT (1U) + +/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) +#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENSET */ +#define DMA_COMMON_INTENSET_COUNT (1U) + +/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) +#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENCLR */ +#define DMA_COMMON_INTENCLR_COUNT (1U) + +/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTA_IA_SHIFT (0U) +#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTA */ +#define DMA_COMMON_INTA_COUNT (1U) + +/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTB_IB_SHIFT (0U) +#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTB */ +#define DMA_COMMON_INTB_COUNT (1U) + +/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETVALID_SV_SHIFT (0U) +#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETVALID */ +#define DMA_COMMON_SETVALID_COUNT (1U) + +/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) +#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETTRIG */ +#define DMA_COMMON_SETTRIG_COUNT (1U) + +/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) +#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ABORT */ +#define DMA_COMMON_ABORT_COUNT (1U) + +/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ +/*! @{ */ +#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) +#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) +/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory + * move, any peripheral DMA request associated with that channel can be disabled to prevent any + * interaction between the peripheral and the DMA controller. + * 0b0..Disabled. Peripheral DMA requests are disabled. + * 0b1..Enabled. Peripheral DMA requests are enabled. + */ +#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) +#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) +#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) +/*! HWTRIGEN - Hardware Triggering Enable for this channel. + * 0b0..Disabled. Hardware triggering is not used. + * 0b1..Enabled. Use hardware triggering. + */ +#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) +#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) +#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) +/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. + * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. + * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. + */ +#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) +#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) +#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) +/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. + * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. + * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = + * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the + * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger + * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the + * current BURSTPOWER length are completed. + */ +#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) +#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) +#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) +/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. + * 0b0..Single transfer. Hardware trigger causes a single transfer. + * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a + * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a + * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is + * complete. + */ +#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) +#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) +#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) +#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) +/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is + * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this + * could be used to read several sequential registers from a peripheral for each DMA burst, + * reading the same registers again for each burst. + * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. + * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. + */ +#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) +/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is + * 'wrapped', meaning that the destination address range for each burst will be the same. As an + * example, this could be used to write several sequential registers to a peripheral for each DMA + * burst, writing the same registers again for each burst. + * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. + * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. + */ +#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) +#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) +#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) +#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CFG */ +#define DMA_CHANNEL_CFG_COUNT (23U) + +/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ +/*! @{ */ +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) +/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the + * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. + * 0b0..No effect. No effect on DMA operation. + * 0b1..Valid pending. + */ +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) +#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) +#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) +/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is + * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. + * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. + * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. + */ +#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CTLSTAT */ +#define DMA_CHANNEL_CTLSTAT_COUNT (23U) + +/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ +/*! @{ */ +#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) +#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) +/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor + * is valid and can potentially be acted upon, if all other activation criteria are fulfilled. + * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. + * 0b1..Valid. The current channel descriptor is considered valid. + */ +#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) +#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) +#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) +/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current + * descriptor is exhausted. Reloading allows ping-pong and linked transfers. + * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. + * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) +#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) +#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) +/*! SWTRIG - Software Trigger. + * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by + * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. + * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not + * be used with level triggering when TRIGBURST = 0. + */ +#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) +#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) +#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) +/*! CLRTRIG - Clear Trigger. + * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. + * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted + */ +#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) +#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) +#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) +/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between + * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By + * convention, interrupt A may be used when only one interrupt flag is needed. + * 0b0..No effect. + * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) +#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) +#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) +/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between + * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By + * convention, interrupt A may be used when only one interrupt flag is needed. + * 0b0..No effect. + * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) +#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) +#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) +/*! WIDTH - Transfer width used for this DMA channel. + * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). + * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). + * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). + * 0b11..Reserved. Reserved setting, do not use. + */ +#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) +#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) +#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) +/*! SRCINC - Determines whether the source address is incremented for each DMA transfer. + * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. + * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is + * the usual case when the source is memory. + * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. + * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. + */ +#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) +#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) +#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) +/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. + * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when + * the destination is a peripheral device. + * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. + * This is the usual case when the destination is memory. + * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. + * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. + */ +#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_XFERCFG */ +#define DMA_CHANNEL_XFERCFG_COUNT (23U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50082000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40082000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A7000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A7000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40082000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A7000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { DMA0_IRQn, DMA1_IRQn } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer + * @{ + */ + +/** FLASH - Register Layout Typedef */ +typedef struct { + __O uint32_t CMD; /**< command register, offset: 0x0 */ + __O uint32_t EVENT; /**< event register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */ + __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */ + uint8_t RESERVED_1[104]; + __IO uint32_t DATAW[4]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_2[3912]; + __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */ + __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */ + __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ + __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ + __O uint32_t INT_CLR_STATUS; /**< Clear interrupt status bits, offset: 0xFE8 */ + __O uint32_t INT_SET_STATUS; /**< Set interrupt status bits, offset: 0xFEC */ + uint8_t RESERVED_3[12]; + __I uint32_t MODULE_ID; /**< Controller+Memory module identification, offset: 0xFFC */ +} FLASH_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_Register_Masks FLASH Register Masks + * @{ + */ + +/*! @name CMD - command register */ +/*! @{ */ +#define FLASH_CMD_CMD_MASK (0xFFFFFFFFU) +#define FLASH_CMD_CMD_SHIFT (0U) +#define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK) +/*! @} */ + +/*! @name EVENT - event register */ +/*! @{ */ +#define FLASH_EVENT_RST_MASK (0x1U) +#define FLASH_EVENT_RST_SHIFT (0U) +#define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK) +#define FLASH_EVENT_WAKEUP_MASK (0x2U) +#define FLASH_EVENT_WAKEUP_SHIFT (1U) +#define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK) +#define FLASH_EVENT_ABORT_MASK (0x4U) +#define FLASH_EVENT_ABORT_SHIFT (2U) +#define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK) +/*! @} */ + +/*! @name STARTA - start (or only) address for next flash command */ +/*! @{ */ +#define FLASH_STARTA_STARTA_MASK (0x3FFFFU) +#define FLASH_STARTA_STARTA_SHIFT (0U) +#define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK) +/*! @} */ + +/*! @name STOPA - end address for next flash command, if command operates on address ranges */ +/*! @{ */ +#define FLASH_STOPA_STOPA_MASK (0x3FFFFU) +#define FLASH_STOPA_STOPA_SHIFT (0U) +#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK) +/*! @} */ + +/*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */ +/*! @{ */ +#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU) +#define FLASH_DATAW_DATAW_SHIFT (0U) +#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK) +/*! @} */ + +/* The count of FLASH_DATAW */ +#define FLASH_DATAW_COUNT (4U) + +/*! @name INT_CLR_ENABLE - Clear interrupt enable bits */ +/*! @{ */ +#define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U) +#define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U) +#define FLASH_INT_CLR_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK) +#define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U) +#define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U) +#define FLASH_INT_CLR_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK) +#define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U) +#define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U) +#define FLASH_INT_CLR_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK) +#define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U) +#define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U) +#define FLASH_INT_CLR_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_SET_ENABLE - Set interrupt enable bits */ +/*! @{ */ +#define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U) +#define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U) +#define FLASH_INT_SET_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK) +#define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U) +#define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U) +#define FLASH_INT_SET_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK) +#define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U) +#define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U) +#define FLASH_INT_SET_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK) +#define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U) +#define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U) +#define FLASH_INT_SET_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt status bits */ +/*! @{ */ +#define FLASH_INT_STATUS_FAIL_MASK (0x1U) +#define FLASH_INT_STATUS_FAIL_SHIFT (0U) +#define FLASH_INT_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK) +#define FLASH_INT_STATUS_ERR_MASK (0x2U) +#define FLASH_INT_STATUS_ERR_SHIFT (1U) +#define FLASH_INT_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK) +#define FLASH_INT_STATUS_DONE_MASK (0x4U) +#define FLASH_INT_STATUS_DONE_SHIFT (2U) +#define FLASH_INT_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK) +#define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U) +#define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U) +#define FLASH_INT_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_ENABLE - Interrupt enable bits */ +/*! @{ */ +#define FLASH_INT_ENABLE_FAIL_MASK (0x1U) +#define FLASH_INT_ENABLE_FAIL_SHIFT (0U) +#define FLASH_INT_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK) +#define FLASH_INT_ENABLE_ERR_MASK (0x2U) +#define FLASH_INT_ENABLE_ERR_SHIFT (1U) +#define FLASH_INT_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK) +#define FLASH_INT_ENABLE_DONE_MASK (0x4U) +#define FLASH_INT_ENABLE_DONE_SHIFT (2U) +#define FLASH_INT_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK) +#define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U) +#define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U) +#define FLASH_INT_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_CLR_STATUS - Clear interrupt status bits */ +/*! @{ */ +#define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U) +#define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U) +#define FLASH_INT_CLR_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK) +#define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U) +#define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U) +#define FLASH_INT_CLR_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK) +#define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U) +#define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U) +#define FLASH_INT_CLR_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK) +#define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U) +#define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U) +#define FLASH_INT_CLR_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_SET_STATUS - Set interrupt status bits */ +/*! @{ */ +#define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U) +#define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U) +#define FLASH_INT_SET_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK) +#define FLASH_INT_SET_STATUS_ERR_MASK (0x2U) +#define FLASH_INT_SET_STATUS_ERR_SHIFT (1U) +#define FLASH_INT_SET_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK) +#define FLASH_INT_SET_STATUS_DONE_MASK (0x4U) +#define FLASH_INT_SET_STATUS_DONE_SHIFT (2U) +#define FLASH_INT_SET_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK) +#define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U) +#define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U) +#define FLASH_INT_SET_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK) +/*! @} */ + +/*! @name MODULE_ID - Controller+Memory module identification */ +/*! @{ */ +#define FLASH_MODULE_ID_APERTURE_MASK (0xFFU) +#define FLASH_MODULE_ID_APERTURE_SHIFT (0U) +#define FLASH_MODULE_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK) +#define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U) +#define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U) +#define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK) +#define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U) +#define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U) +#define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK) +#define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U) +#define FLASH_MODULE_ID_ID_SHIFT (16U) +#define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLASH_Register_Masks */ + + +/* FLASH - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral FLASH base address */ + #define FLASH_BASE (0x50034000u) + /** Peripheral FLASH base address */ + #define FLASH_BASE_NS (0x40034000u) + /** Peripheral FLASH base pointer */ + #define FLASH ((FLASH_Type *)FLASH_BASE) + /** Peripheral FLASH base pointer */ + #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS) + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS { FLASH_BASE } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS { FLASH } + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS_NS { FLASH_NS } +#else + /** Peripheral FLASH base address */ + #define FLASH_BASE (0x40034000u) + /** Peripheral FLASH base pointer */ + #define FLASH ((FLASH_Type *)FLASH_BASE) + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS { FLASH_BASE } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS { FLASH } +#endif + +/*! + * @} + */ /* end of group FLASH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH_CFPA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CFPA_Peripheral_Access_Layer FLASH_CFPA Peripheral Access Layer + * @{ + */ + +/** FLASH_CFPA - Register Layout Typedef */ +typedef struct { + __IO uint32_t HEADER; /**< ., offset: 0x0 */ + __IO uint32_t VERSION; /**< ., offset: 0x4 */ + __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */ + __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */ + __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ROTKH_REVOKE; /**< ., offset: 0x18 */ + __IO uint32_t VENDOR_USAGE; /**< ., offset: 0x1C */ + __IO uint32_t DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */ + __IO uint32_t DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */ + __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */ + __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */ + union { /* offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< ., array offset: 0x30, array step: 0x4 */ + struct { /* offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< ., offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< ., offset: 0x34 */ + __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< ., array offset: 0x38, array step: 0x4 */ + } PRINCE_REGION0_IV_CODE_CORE; + }; + union { /* offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< ., array offset: 0x68, array step: 0x4 */ + struct { /* offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< ., offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< ., offset: 0x6C */ + __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< ., array offset: 0x70, array step: 0x4 */ + } PRINCE_REGION1_IV_CODE_CORE; + }; + union { /* offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< ., array offset: 0xA0, array step: 0x4 */ + struct { /* offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< ., offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< ., offset: 0xA4 */ + __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< ., array offset: 0xA8, array step: 0x4 */ + } PRINCE_REGION2_IV_CODE_CORE; + }; + uint8_t RESERVED_1[40]; + __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ + __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ +} FLASH_CFPA_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_CFPA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CFPA_Register_Masks FLASH_CFPA Register Masks + * @{ + */ + +/*! @name HEADER - . */ +/*! @{ */ +#define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_HEADER_FIELD_SHIFT (0U) +#define FLASH_CFPA_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK) +/*! @} */ + +/*! @name VERSION - . */ +/*! @{ */ +#define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_VERSION_FIELD_SHIFT (0U) +#define FLASH_CFPA_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK) +/*! @} */ + +/*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */ +/*! @{ */ +#define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U) +#define FLASH_CFPA_S_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK) +/*! @} */ + +/*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */ +/*! @{ */ +#define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U) +#define FLASH_CFPA_NS_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK) +/*! @} */ + +/*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */ +/*! @{ */ +#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U) +#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK) +/*! @} */ + +/*! @name ROTKH_REVOKE - . */ +/*! @{ */ +#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK) +/*! @} */ + +/*! @name VENDOR_USAGE - . */ +/*! @{ */ +#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU) +#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U) +#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK) +#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U) +#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ +/*! @{ */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) +/*! ME_CMD_EN - Flash Mass Erase Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ +/*! @{ */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) +/*! ME_CMD_EN - Flash Mass Erase Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */ +/*! @{ */ +#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK) +/*! @} */ + +/*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */ +/*! @{ */ +#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U) +#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_IV_CODE - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */ +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U) + +/*! @name PRINCE_REGION0_IV_HEADER0 - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_IV_HEADER1 - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_IV_BODY - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */ +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U) + +/*! @name PRINCE_REGION1_IV_CODE - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */ +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U) + +/*! @name PRINCE_REGION1_IV_HEADER0 - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_IV_HEADER1 - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_IV_BODY - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */ +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U) + +/*! @name PRINCE_REGION2_IV_CODE - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */ +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U) + +/*! @name PRINCE_REGION2_IV_HEADER0 - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_IV_HEADER1 - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_IV_BODY - . */ +/*! @{ */ +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION2_IV_BODY */ +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_COUNT (12U) + +/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ +/*! @{ */ +#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) +#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_CUSTOMER_DEFINED */ +#define FLASH_CFPA_CUSTOMER_DEFINED_COUNT (56U) + +/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */ +/*! @{ */ +#define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U) +#define FLASH_CFPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_SHA256_DIGEST */ +#define FLASH_CFPA_SHA256_DIGEST_COUNT (8U) + + +/*! + * @} + */ /* end of group FLASH_CFPA_Register_Masks */ + + +/* FLASH_CFPA - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE (0x1009E000u) + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE_NS (0x9E000u) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0_NS ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE (0x1009E200u) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE_NS (0x9E200u) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1_NS ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE (0x1009DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE_NS (0x9DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH_NS ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS) + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS_NS { FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS_NS { FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS } +#else + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE (0x9E000u) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE (0x9E200u) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE (0x9DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } +#endif + +/*! + * @} + */ /* end of group FLASH_CFPA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH_CMPA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CMPA_Peripheral_Access_Layer FLASH_CMPA Peripheral Access Layer + * @{ + */ + +/** FLASH_CMPA - Register Layout Typedef */ +typedef struct { + __IO uint32_t BOOT_CFG; /**< ., offset: 0x0 */ + __IO uint32_t SPI_FLASH_CFG; /**< ., offset: 0x4 */ + __IO uint32_t USB_ID; /**< ., offset: 0x8 */ + __IO uint32_t SDIO_CFG; /**< ., offset: 0xC */ + __IO uint32_t CC_SOCU_PIN; /**< ., offset: 0x10 */ + __IO uint32_t CC_SOCU_DFLT; /**< ., offset: 0x14 */ + __IO uint32_t VENDOR_USAGE; /**< ., offset: 0x18 */ + __IO uint32_t SECURE_BOOT_CFG; /**< ., offset: 0x1C */ + __IO uint32_t PRINCE_BASE_ADDR; /**< ., offset: 0x20 */ + __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */ + __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */ + __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */ + __IO uint32_t XTAL_32KHZ_CAPABANK_TRIM; /**< Xtal 32kHz capabank triming., offset: 0x30 */ + __IO uint32_t XTAL_16MHZ_CAPABANK_TRIM; /**< Xtal 16MHz capabank triming., offset: 0x34 */ + uint8_t RESERVED_0[24]; + __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */ + uint8_t RESERVED_1[144]; + __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ + __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ +} FLASH_CMPA_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_CMPA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CMPA_Register_Masks FLASH_CMPA Register Masks + * @{ + */ + +/*! @name BOOT_CFG - . */ +/*! @{ */ +#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U) +#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U) +/*! DEFAULT_ISP_MODE - Default ISP mode: + * 0b000..Auto ISP + * 0b001..USB_HID_MSC + * 0b010..SPI Slave ISP + * 0b011..I2C Slave ISP + * 0b111..Disable ISP fall through + */ +#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK) +#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U) +#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U) +/*! BOOT_SPEED - Core clock: + * 0b00..Defined by NMPA.SYSTEM_SPEED_CODE + * 0b01..48MHz FRO + * 0b10..96MHz FRO + */ +#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK) +#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U) +#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U) +#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK) +/*! @} */ + +/*! @name SPI_FLASH_CFG - . */ +/*! @{ */ +#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK (0x1FU) +#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT (0U) +#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK) +/*! @} */ + +/*! @name USB_ID - . */ +/*! @{ */ +#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU) +#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U) +#define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK) +#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U) +#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U) +#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK) +/*! @} */ + +/*! @name SDIO_CFG - . */ +/*! @{ */ +#define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U) +#define FLASH_CMPA_SDIO_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK) +/*! @} */ + +/*! @name CC_SOCU_PIN - . */ +/*! @{ */ +#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK (0x1U) +#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK) +#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK (0x2U) +#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK) +#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) +#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK) +#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK (0x8U) +#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK) +#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK (0x10U) +#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK) +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK) +#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK) +#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) +#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK) +#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) +#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) +/*! ME_CMD_EN - Flash Mass Erase Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK) +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK) +#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) +#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) +#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK) +#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) +#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name CC_SOCU_DFLT - . */ +/*! @{ */ +#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK (0x1U) +#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK) +#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK (0x2U) +#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK) +#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) +#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK) +#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) +#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK) +#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK (0x10U) +#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK) +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK) +#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK) +#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) +#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK) +#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) +#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) +/*! ME_CMD_EN - Flash Mass Erase Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK) +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK) +#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) +#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name VENDOR_USAGE - . */ +/*! @{ */ +#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK (0xFFFF0000U) +#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT (16U) +#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK) +/*! @} */ + +/*! @name SECURE_BOOT_CFG - . */ +/*! @{ */ +#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U) +#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U) +#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK (0xCU) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT (2U) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U) +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U) +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U) +#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U) +#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK (0xC000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT (14U) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK) +#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U) +#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK) +/*! @} */ + +/*! @name PRINCE_BASE_ADDR - . */ +/*! @{ */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0x30000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (16U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0xC0000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (18U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK (0x300000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT (20U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK) +/*! @} */ + +/*! @name PRINCE_SR_0 - Region 0, sub-region enable */ +/*! @{ */ +#define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U) +#define FLASH_CMPA_PRINCE_SR_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_SR_1 - Region 1, sub-region enable */ +/*! @{ */ +#define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U) +#define FLASH_CMPA_PRINCE_SR_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_SR_2 - Region 2, sub-region enable */ +/*! @{ */ +#define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U) +#define FLASH_CMPA_PRINCE_SR_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK) +/*! @} */ + +/*! @name XTAL_32KHZ_CAPABANK_TRIM - Xtal 32kHz capabank triming. */ +/*! @{ */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) +/*! @} */ + +/*! @name XTAL_16MHZ_CAPABANK_TRIM - Xtal 16MHz capabank triming. */ +/*! @{ */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) +/*! @} */ + +/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0] */ +/*! @{ */ +#define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U) +#define FLASH_CMPA_ROTKH_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CMPA_ROTKH */ +#define FLASH_CMPA_ROTKH_COUNT (8U) + +/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ +/*! @{ */ +#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) +#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CMPA_CUSTOMER_DEFINED */ +#define FLASH_CMPA_CUSTOMER_DEFINED_COUNT (56U) + +/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */ +/*! @{ */ +#define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U) +#define FLASH_CMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CMPA_SHA256_DIGEST */ +#define FLASH_CMPA_SHA256_DIGEST_COUNT (8U) + + +/*! + * @} + */ /* end of group FLASH_CMPA_Register_Masks */ + + +/* FLASH_CMPA - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE (0x1009E400u) + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE_NS (0x9E400u) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA_NS ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS) + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS_NS { FLASH_CMPA_BASE_NS } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS_NS { FLASH_CMPA_NS } +#else + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE (0x9E400u) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } +#endif + +/*! + * @} + */ /* end of group FLASH_CMPA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH_KEY_STORE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_KEY_STORE_Peripheral_Access_Layer FLASH_KEY_STORE Peripheral Access Layer + * @{ + */ + +/** FLASH_KEY_STORE - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0 */ + __IO uint32_t HEADER; /**< Valid Key Sore Header : 0x95959595, offset: 0x0 */ + __IO uint32_t PUF_DISCHARGE_TIME_IN_MS; /**< puf discharge time in ms., offset: 0x4 */ + } KEY_STORE_HEADER; + __IO uint32_t ACTIVATION_CODE[298]; /**< ., array offset: 0x8, array step: 0x4 */ + union { /* offset: 0x4B0 */ + __IO uint32_t SBKEY_KEY_CODE[14]; /**< ., array offset: 0x4B0, array step: 0x4 */ + struct { /* offset: 0x4B0 */ + __IO uint32_t SBKEY_HEADER0; /**< ., offset: 0x4B0 */ + __IO uint32_t SBKEY_HEADER1; /**< ., offset: 0x4B4 */ + __IO uint32_t SBKEY_BODY[12]; /**< ., array offset: 0x4B8, array step: 0x4 */ + } SBKEY_KEY_CODE_CORE; + }; + union { /* offset: 0x4E8 */ + __IO uint32_t USER_KEK_KEY_CODE[14]; /**< ., array offset: 0x4E8, array step: 0x4 */ + struct { /* offset: 0x4E8 */ + __IO uint32_t USER_KEK_HEADER0; /**< ., offset: 0x4E8 */ + __IO uint32_t USER_KEK_HEADER1; /**< ., offset: 0x4EC */ + __IO uint32_t USER_KEK_BODY[12]; /**< ., array offset: 0x4F0, array step: 0x4 */ + } USER_KEK_KEY_CODE_CORE; + }; + union { /* offset: 0x520 */ + __IO uint32_t UDS_KEY_CODE[14]; /**< ., array offset: 0x520, array step: 0x4 */ + struct { /* offset: 0x520 */ + __IO uint32_t UDS_HEADER0; /**< ., offset: 0x520 */ + __IO uint32_t UDS_HEADER1; /**< ., offset: 0x524 */ + __IO uint32_t UDS_BODY[12]; /**< ., array offset: 0x528, array step: 0x4 */ + } UDS_KEY_CODE_CORE; + }; + union { /* offset: 0x558 */ + __IO uint32_t PRINCE_REGION0_KEY_CODE[14]; /**< ., array offset: 0x558, array step: 0x4 */ + struct { /* offset: 0x558 */ + __IO uint32_t PRINCE_REGION0_HEADER0; /**< ., offset: 0x558 */ + __IO uint32_t PRINCE_REGION0_HEADER1; /**< ., offset: 0x55C */ + __IO uint32_t PRINCE_REGION0_BODY[12]; /**< ., array offset: 0x560, array step: 0x4 */ + } PRINCE_REGION0_KEY_CODE_CORE; + }; + union { /* offset: 0x590 */ + __IO uint32_t PRINCE_REGION1_KEY_CODE[14]; /**< ., array offset: 0x590, array step: 0x4 */ + struct { /* offset: 0x590 */ + __IO uint32_t PRINCE_REGION1_HEADER0; /**< ., offset: 0x590 */ + __IO uint32_t PRINCE_REGION1_HEADER1; /**< ., offset: 0x594 */ + __IO uint32_t PRINCE_REGION1_BODY[12]; /**< ., array offset: 0x598, array step: 0x4 */ + } PRINCE_REGION1_KEY_CODE_CORE; + }; + union { /* offset: 0x5C8 */ + __IO uint32_t PRINCE_REGION2_KEY_CODE[14]; /**< ., array offset: 0x5C8, array step: 0x4 */ + struct { /* offset: 0x5C8 */ + __IO uint32_t PRINCE_REGION2_HEADER0; /**< ., offset: 0x5C8 */ + __IO uint32_t PRINCE_REGION2_HEADER1; /**< ., offset: 0x5CC */ + __IO uint32_t PRINCE_REGION2_BODY[12]; /**< ., array offset: 0x5D0, array step: 0x4 */ + } PRINCE_REGION2_KEY_CODE_CORE; + }; +} FLASH_KEY_STORE_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_KEY_STORE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_KEY_STORE_Register_Masks FLASH_KEY_STORE Register Masks + * @{ + */ + +/*! @name HEADER - Valid Key Sore Header : 0x95959595 */ +/*! @{ */ +#define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK) +/*! @} */ + +/*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */ +/*! @{ */ +#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK) +/*! @} */ + +/*! @name ACTIVATION_CODE - . */ +/*! @{ */ +#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_ACTIVATION_CODE */ +#define FLASH_KEY_STORE_ACTIVATION_CODE_COUNT (298U) + +/*! @name SBKEY_KEY_CODE - . */ +/*! @{ */ +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_SBKEY_KEY_CODE */ +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_COUNT (14U) + +/*! @name SBKEY_HEADER0 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name SBKEY_HEADER1 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK) +#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK) +#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name SBKEY_BODY - . */ +/*! @{ */ +#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_SBKEY_BODY */ +#define FLASH_KEY_STORE_SBKEY_BODY_COUNT (12U) + +/*! @name USER_KEK_KEY_CODE - . */ +/*! @{ */ +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_USER_KEK_KEY_CODE */ +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_COUNT (14U) + +/*! @name USER_KEK_HEADER0 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name USER_KEK_HEADER1 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name USER_KEK_BODY - . */ +/*! @{ */ +#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_USER_KEK_BODY */ +#define FLASH_KEY_STORE_USER_KEK_BODY_COUNT (12U) + +/*! @name UDS_KEY_CODE - . */ +/*! @{ */ +#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_UDS_KEY_CODE */ +#define FLASH_KEY_STORE_UDS_KEY_CODE_COUNT (14U) + +/*! @name UDS_HEADER0 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name UDS_HEADER1 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U) +#define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK) +#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U) +#define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK) +#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U) +#define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name UDS_BODY - . */ +/*! @{ */ +#define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_UDS_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_UDS_BODY */ +#define FLASH_KEY_STORE_UDS_BODY_COUNT (12U) + +/*! @name PRINCE_REGION0_KEY_CODE - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE */ +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_COUNT (14U) + +/*! @name PRINCE_REGION0_HEADER0 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_HEADER1 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_BODY - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION0_BODY */ +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_COUNT (12U) + +/*! @name PRINCE_REGION1_KEY_CODE - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE */ +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_COUNT (14U) + +/*! @name PRINCE_REGION1_HEADER0 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_HEADER1 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_BODY - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION1_BODY */ +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_COUNT (12U) + +/*! @name PRINCE_REGION2_KEY_CODE - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE */ +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_COUNT (14U) + +/*! @name PRINCE_REGION2_HEADER0 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_HEADER1 - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_BODY - . */ +/*! @{ */ +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U) +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION2_BODY */ +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_COUNT (12U) + + +/*! + * @} + */ /* end of group FLASH_KEY_STORE_Register_Masks */ + + +/* FLASH_KEY_STORE - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE (0x1009E600u) + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE_NS (0x9E600u) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE_NS ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS) + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS_NS { FLASH_KEY_STORE_BASE_NS } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS_NS { FLASH_KEY_STORE_NS } +#else + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE (0x9E600u) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } +#endif + +/*! + * @} + */ /* end of group FLASH_KEY_STORE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer + * @{ + */ + +/** FLEXCOMM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4088]; + __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ + __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ +} FLEXCOMM_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks + * @{ + */ + +/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ +/*! @{ */ +#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) +#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) +/*! PERSEL - Peripheral Select. This field is writable by software. + * 0b000..No peripheral selected. + * 0b001..USART function selected. + * 0b010..SPI function selected. + * 0b011..I2C function selected. + * 0b100..I2S transmit function selected. + * 0b101..I2S receive function selected. + * 0b110..Reserved + * 0b111..Reserved + */ +#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) +#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) +#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) +/*! LOCK - Lock the peripheral select. This field is writable by software. + * 0b0..Peripheral select can be changed by software. + * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. + */ +#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) +#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) +#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) +/*! USARTPRESENT - USART present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the USART function. + * 0b1..This Flexcomm includes the USART function. + */ +#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) +#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) +#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) +/*! SPIPRESENT - SPI present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the SPI function. + * 0b1..This Flexcomm includes the SPI function. + */ +#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) +#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) +#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) +/*! I2CPRESENT - I2C present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the I2C function. + * 0b1..This Flexcomm includes the I2C function. + */ +#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) +#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) +#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) +/*! I2SPRESENT - I 2S present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the I2S function. + * 0b1..This Flexcomm includes the I2S function. + */ +#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) +#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) +#define FLEXCOMM_PSELID_ID_SHIFT (12U) +#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) +/*! @} */ + +/*! @name PID - Peripheral identification register. */ +/*! @{ */ +#define FLEXCOMM_PID_APERTURE_MASK (0xFFU) +#define FLEXCOMM_PID_APERTURE_SHIFT (0U) +#define FLEXCOMM_PID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_APERTURE_SHIFT)) & FLEXCOMM_PID_APERTURE_MASK) +#define FLEXCOMM_PID_MINOR_REV_MASK (0xF00U) +#define FLEXCOMM_PID_MINOR_REV_SHIFT (8U) +#define FLEXCOMM_PID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MINOR_REV_SHIFT)) & FLEXCOMM_PID_MINOR_REV_MASK) +#define FLEXCOMM_PID_MAJOR_REV_MASK (0xF000U) +#define FLEXCOMM_PID_MAJOR_REV_SHIFT (12U) +#define FLEXCOMM_PID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MAJOR_REV_SHIFT)) & FLEXCOMM_PID_MAJOR_REV_MASK) +#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) +#define FLEXCOMM_PID_ID_SHIFT (16U) +#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLEXCOMM_Register_Masks */ + + +/* FLEXCOMM - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE (0x50086000u) + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE_NS (0x40086000u) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE (0x50087000u) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE_NS (0x40087000u) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE (0x50088000u) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE_NS (0x40088000u) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE (0x50089000u) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE_NS (0x40089000u) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE (0x5008A000u) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE_NS (0x4008A000u) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE (0x50096000u) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE_NS (0x40096000u) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE (0x50097000u) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE_NS (0x40097000u) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE (0x50098000u) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE_NS (0x40098000u) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE (0x5009F000u) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE_NS (0x4009F000u) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS) + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS_NS { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS_NS { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS } +#else + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE (0x40086000u) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE (0x40087000u) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE (0x40088000u) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE (0x40089000u) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE (0x4008A000u) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE (0x40096000u) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE (0x40097000u) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE (0x40098000u) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE (0x4009F000u) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } +#endif +/** Interrupt vectors for the FLEXCOMM peripheral type */ +#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } + +/*! + * @} + */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer + * @{ + */ + +/** GINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ + uint8_t RESERVED_0[28]; + __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[24]; + __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ +} GINT_Type; + +/* ---------------------------------------------------------------------------- + -- GINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Register_Masks GINT Register Masks + * @{ + */ + +/*! @name CTRL - GPIO grouped interrupt control register */ +/*! @{ */ +#define GINT_CTRL_INT_MASK (0x1U) +#define GINT_CTRL_INT_SHIFT (0U) +/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. + * 0b0..No request. No interrupt request is pending. + * 0b1..Request active. Interrupt request is active. + */ +#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) +#define GINT_CTRL_COMB_MASK (0x2U) +#define GINT_CTRL_COMB_SHIFT (1U) +/*! COMB - Combine enabled inputs for group interrupt + * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). + * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). + */ +#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) +#define GINT_CTRL_TRIG_MASK (0x4U) +#define GINT_CTRL_TRIG_SHIFT (2U) +/*! TRIG - Group interrupt trigger + * 0b0..Edge-triggered. + * 0b1..Level-triggered. + */ +#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) +/*! @} */ + +/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ +/*! @{ */ +#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) +#define GINT_PORT_POL_POL_SHIFT (0U) +#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) +/*! @} */ + +/* The count of GINT_PORT_POL */ +#define GINT_PORT_POL_COUNT (2U) + +/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ +/*! @{ */ +#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) +#define GINT_PORT_ENA_ENA_SHIFT (0U) +#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) +/*! @} */ + +/* The count of GINT_PORT_ENA */ +#define GINT_PORT_ENA_COUNT (2U) + + +/*! + * @} + */ /* end of group GINT_Register_Masks */ + + +/* GINT - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral GINT0 base address */ + #define GINT0_BASE (0x50002000u) + /** Peripheral GINT0 base address */ + #define GINT0_BASE_NS (0x40002000u) + /** Peripheral GINT0 base pointer */ + #define GINT0 ((GINT_Type *)GINT0_BASE) + /** Peripheral GINT0 base pointer */ + #define GINT0_NS ((GINT_Type *)GINT0_BASE_NS) + /** Peripheral GINT1 base address */ + #define GINT1_BASE (0x50003000u) + /** Peripheral GINT1 base address */ + #define GINT1_BASE_NS (0x40003000u) + /** Peripheral GINT1 base pointer */ + #define GINT1 ((GINT_Type *)GINT1_BASE) + /** Peripheral GINT1 base pointer */ + #define GINT1_NS ((GINT_Type *)GINT1_BASE_NS) + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS { GINT0, GINT1 } + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS_NS { GINT0_BASE_NS, GINT1_BASE_NS } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS_NS { GINT0_NS, GINT1_NS } +#else + /** Peripheral GINT0 base address */ + #define GINT0_BASE (0x40002000u) + /** Peripheral GINT0 base pointer */ + #define GINT0 ((GINT_Type *)GINT0_BASE) + /** Peripheral GINT1 base address */ + #define GINT1_BASE (0x40003000u) + /** Peripheral GINT1 base pointer */ + #define GINT1 ((GINT_Type *)GINT1_BASE) + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS { GINT0, GINT1 } +#endif +/** Interrupt vectors for the GINT peripheral type */ +#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } + +/*! + * @} + */ /* end of group GINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint8_t B[2][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ + uint8_t RESERVED_0[4032]; + __IO uint32_t W[2][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ + uint8_t RESERVED_1[3840]; + __IO uint32_t DIR[2]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */ + uint8_t RESERVED_2[120]; + __IO uint32_t MASK[2]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */ + uint8_t RESERVED_3[120]; + __IO uint32_t PIN[2]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */ + uint8_t RESERVED_4[120]; + __IO uint32_t MPIN[2]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */ + uint8_t RESERVED_5[120]; + __IO uint32_t SET[2]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */ + uint8_t RESERVED_6[120]; + __O uint32_t CLR[2]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */ + uint8_t RESERVED_7[120]; + __O uint32_t NOT[2]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */ + uint8_t RESERVED_8[120]; + __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ + uint8_t RESERVED_9[120]; + __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ + uint8_t RESERVED_10[120]; + __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name B - Byte pin registers for all port GPIO pins */ +/*! @{ */ +#define GPIO_B_PBYTE_MASK (0x1U) +#define GPIO_B_PBYTE_SHIFT (0U) +#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) +/*! @} */ + +/* The count of GPIO_B */ +#define GPIO_B_COUNT (2U) + +/* The count of GPIO_B */ +#define GPIO_B_COUNT2 (32U) + +/*! @name W - Word pin registers for all port GPIO pins */ +/*! @{ */ +#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) +#define GPIO_W_PWORD_SHIFT (0U) +#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) +/*! @} */ + +/* The count of GPIO_W */ +#define GPIO_W_COUNT (2U) + +/* The count of GPIO_W */ +#define GPIO_W_COUNT2 (32U) + +/*! @name DIR - Direction registers for all port GPIO pins */ +/*! @{ */ +#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) +#define GPIO_DIR_DIRP_SHIFT (0U) +#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) +/*! @} */ + +/* The count of GPIO_DIR */ +#define GPIO_DIR_COUNT (2U) + +/*! @name MASK - Mask register for all port GPIO pins */ +/*! @{ */ +#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) +#define GPIO_MASK_MASKP_SHIFT (0U) +#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) +/*! @} */ + +/* The count of GPIO_MASK */ +#define GPIO_MASK_COUNT (2U) + +/*! @name PIN - Port pin register for all port GPIO pins */ +/*! @{ */ +#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) +#define GPIO_PIN_PORT_SHIFT (0U) +#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) +/*! @} */ + +/* The count of GPIO_PIN */ +#define GPIO_PIN_COUNT (2U) + +/*! @name MPIN - Masked port register for all port GPIO pins */ +/*! @{ */ +#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) +#define GPIO_MPIN_MPORTP_SHIFT (0U) +#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) +/*! @} */ + +/* The count of GPIO_MPIN */ +#define GPIO_MPIN_COUNT (2U) + +/*! @name SET - Write: Set register for port. Read: output bits for port */ +/*! @{ */ +#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) +#define GPIO_SET_SETP_SHIFT (0U) +#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) +/*! @} */ + +/* The count of GPIO_SET */ +#define GPIO_SET_COUNT (2U) + +/*! @name CLR - Clear port for all port GPIO pins */ +/*! @{ */ +#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) +#define GPIO_CLR_CLRP_SHIFT (0U) +#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) +/*! @} */ + +/* The count of GPIO_CLR */ +#define GPIO_CLR_COUNT (2U) + +/*! @name NOT - Toggle port for all port GPIO pins */ +/*! @{ */ +#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) +#define GPIO_NOT_NOTP_SHIFT (0U) +#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) +/*! @} */ + +/* The count of GPIO_NOT */ +#define GPIO_NOT_COUNT (2U) + +/*! @name DIRSET - Set pin direction bits for port */ +/*! @{ */ +#define GPIO_DIRSET_DIRSETP_MASK (0xFFFFFFFFU) +#define GPIO_DIRSET_DIRSETP_SHIFT (0U) +#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) +/*! @} */ + +/* The count of GPIO_DIRSET */ +#define GPIO_DIRSET_COUNT (2U) + +/*! @name DIRCLR - Clear pin direction bits for port */ +/*! @{ */ +#define GPIO_DIRCLR_DIRCLRP_MASK (0xFFFFFFFFU) +#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) +#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) +/*! @} */ + +/* The count of GPIO_DIRCLR */ +#define GPIO_DIRCLR_COUNT (2U) + +/*! @name DIRNOT - Toggle pin direction bits for port */ +/*! @{ */ +#define GPIO_DIRNOT_DIRNOTP_MASK (0xFFFFFFFFU) +#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) +#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) +/*! @} */ + +/* The count of GPIO_DIRNOT */ +#define GPIO_DIRNOT_COUNT (2U) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral GPIO base address */ + #define GPIO_BASE (0x5008C000u) + /** Peripheral GPIO base address */ + #define GPIO_BASE_NS (0x4008C000u) + /** Peripheral GPIO base pointer */ + #define GPIO ((GPIO_Type *)GPIO_BASE) + /** Peripheral GPIO base pointer */ + #define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE (0x500A8000u) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE_NS (0x400A8000u) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO, SECGPIO } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO_BASE_NS, SECGPIO_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO_NS, SECGPIO_NS } +#else + /** Peripheral GPIO base address */ + #define GPIO_BASE (0x4008C000u) + /** Peripheral GPIO base pointer */ + #define GPIO ((GPIO_Type *)GPIO_BASE) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE (0x400A8000u) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO, SECGPIO } +#endif + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- HASHCRYPT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup HASHCRYPT_Peripheral_Access_Layer HASHCRYPT Peripheral Access Layer + * @{ + */ + +/** HASHCRYPT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register to enable and operate Hash and Crypto, offset: 0x0 */ + __IO uint32_t STATUS; /**< Indicates status of Hash peripheral., offset: 0x4 */ + __IO uint32_t INTENSET; /**< Write 1 to enable interrupts; reads back with which are set., offset: 0x8 */ + __IO uint32_t INTENCLR; /**< Write 1 to clear interrupts., offset: 0xC */ + __IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available), offset: 0x10 */ + __IO uint32_t MEMADDR; /**< Address to start memory access from (if available)., offset: 0x14 */ + uint8_t RESERVED_0[8]; + __O uint32_t INDATA; /**< Input of 16 words at a time to load up buffer., offset: 0x20 */ + __O uint32_t ALIAS[7]; /**< , array offset: 0x24, array step: 0x4 */ + __I uint32_t DIGEST0[8]; /**< , array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[32]; + __IO uint32_t CRYPTCFG; /**< Crypto settings for AES and Salsa and ChaCha, offset: 0x80 */ + __I uint32_t CONFIG; /**< Returns the configuration of this block in this chip - indicates what services are available., offset: 0x84 */ + uint8_t RESERVED_2[4]; + __IO uint32_t LOCK; /**< Lock register allows locking to the current security level or unlocking by the lock holding level., offset: 0x8C */ + __O uint32_t MASK[4]; /**< , array offset: 0x90, array step: 0x4 */ +} HASHCRYPT_Type; + +/* ---------------------------------------------------------------------------- + -- HASHCRYPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup HASHCRYPT_Register_Masks HASHCRYPT Register Masks + * @{ + */ + +/*! @name CTRL - Control register to enable and operate Hash and Crypto */ +/*! @{ */ +#define HASHCRYPT_CTRL_MODE_MASK (0x7U) +#define HASHCRYPT_CTRL_MODE_SHIFT (0U) +/*! Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if + * specific modes beyond SHA1 and SHA2-256 are available. + * 0b000..Disabled + * 0b001..SHA1 is enabled + * 0b010..SHA2-256 is enabled + * 0b100..AES if available (see also CRYPTCFG register for more controls) + * 0b101..ICB-AES if available (see also CRYPTCFG register for more controls) + */ +#define HASHCRYPT_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK) +#define HASHCRYPT_CTRL_NEW_HASH_MASK (0x10U) +#define HASHCRYPT_CTRL_NEW_HASH_SHIFT (4U) +/*! New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING + * Status bit will clear for a cycle during the initialization from New=1. + * 0b1..Starts a new Hash/Crypto and initializes the Digest/Result. + */ +#define HASHCRYPT_CTRL_NEW_HASH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK) +#define HASHCRYPT_CTRL_DMA_I_MASK (0x100U) +#define HASHCRYPT_CTRL_DMA_I_SHIFT (8U) +/*! DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words + * and then will process the Hash. If Cryptographic, it will load as many words as needed, + * including key if not already loaded. It will then request again. Normal model is that the DMA + * interrupts the processor when its length expires. Note that if the processor will write the key and + * optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be + * expected to load those for the 1st block (when needed). + * 0b0..DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used. + * 0b1..DMA will push in the data. + */ +#define HASHCRYPT_CTRL_DMA_I(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK) +#define HASHCRYPT_CTRL_DMA_O_MASK (0x200U) +#define HASHCRYPT_CTRL_DMA_O_SHIFT (9U) +/*! DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the + * DMA has to know to switch direction and the locations. This can be used for crypto uses. + * 0b0..DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. + */ +#define HASHCRYPT_CTRL_DMA_O(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK) +#define HASHCRYPT_CTRL_HASHSWPB_MASK (0x1000U) +#define HASHCRYPT_CTRL_HASHSWPB_SHIFT (12U) +#define HASHCRYPT_CTRL_HASHSWPB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK) +/*! @} */ + +/*! @name STATUS - Indicates status of Hash peripheral. */ +/*! @{ */ +#define HASHCRYPT_STATUS_WAITING_MASK (0x1U) +#define HASHCRYPT_STATUS_WAITING_SHIFT (0U) +/*! WAITING - If 1, the block is waiting for more data to process. + * 0b0..Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set + * if IsLast is set nor will it set until at least 1 word is read of the output. + * 0b1..Waiting for data to be written in (16 words) + */ +#define HASHCRYPT_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK) +#define HASHCRYPT_STATUS_DIGEST_MASK (0x2U) +#define HASHCRYPT_STATUS_DIGEST_SHIFT (1U) +/*! DIGEST - For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block + * already started. For Cryptographic uses, this will be set for each block processed, indicating + * OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared + * when any data is written, when New is written, for Cryptographic uses when the last word is read + * out, or when the block is disabled. + * 0b0..No Digest is ready + * 0b1..Digest is ready. Application may read it or may write more data + */ +#define HASHCRYPT_STATUS_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_SHIFT)) & HASHCRYPT_STATUS_DIGEST_MASK) +#define HASHCRYPT_STATUS_ERROR_MASK (0x4U) +#define HASHCRYPT_STATUS_ERROR_SHIFT (2U) +/*! ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA + * was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT + * field will indicate which block it was on. + * 0b0..No error. + * 0b1..An error occurred since last cleared (written 1 to clear). + */ +#define HASHCRYPT_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK) +#define HASHCRYPT_STATUS_NEEDKEY_MASK (0x10U) +#define HASHCRYPT_STATUS_NEEDKEY_SHIFT (4U) +/*! NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING) + * 0b0..No Key is needed and writes will not be treated as Key + * 0b1..Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. + */ +#define HASHCRYPT_STATUS_NEEDKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK) +#define HASHCRYPT_STATUS_NEEDIV_MASK (0x20U) +#define HASHCRYPT_STATUS_NEEDIV_SHIFT (5U) +/*! NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING) + * 0b0..No IV/Nonce is needed, either because written already or because not needed. + * 0b1..IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. + */ +#define HASHCRYPT_STATUS_NEEDIV(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK) +#define HASHCRYPT_STATUS_ICBIDX_MASK (0x3F0000U) +#define HASHCRYPT_STATUS_ICBIDX_SHIFT (16U) +#define HASHCRYPT_STATUS_ICBIDX(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ICBIDX_SHIFT)) & HASHCRYPT_STATUS_ICBIDX_MASK) +/*! @} */ + +/*! @name INTENSET - Write 1 to enable interrupts; reads back with which are set. */ +/*! @{ */ +#define HASHCRYPT_INTENSET_WAITING_MASK (0x1U) +#define HASHCRYPT_INTENSET_WAITING_SHIFT (0U) +/*! WAITING - Indicates if should interrupt when waiting for data input. + * 0b0..Will not interrupt when waiting. + * 0b1..Will interrupt when waiting + */ +#define HASHCRYPT_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK) +#define HASHCRYPT_INTENSET_DIGEST_MASK (0x2U) +#define HASHCRYPT_INTENSET_DIGEST_SHIFT (1U) +/*! DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). + * 0b0..Will not interrupt when Digest is ready + * 0b1..Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). + */ +#define HASHCRYPT_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK) +#define HASHCRYPT_INTENSET_ERROR_MASK (0x4U) +#define HASHCRYPT_INTENSET_ERROR_SHIFT (2U) +/*! ERROR - Indicates if should interrupt on an ERROR (as defined in Status) + * 0b0..Will not interrupt on Error. + * 0b1..Will interrupt on Error (until cleared). + */ +#define HASHCRYPT_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_ERROR_SHIFT)) & HASHCRYPT_INTENSET_ERROR_MASK) +/*! @} */ + +/*! @name INTENCLR - Write 1 to clear interrupts. */ +/*! @{ */ +#define HASHCRYPT_INTENCLR_WAITING_MASK (0x1U) +#define HASHCRYPT_INTENCLR_WAITING_SHIFT (0U) +#define HASHCRYPT_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK) +#define HASHCRYPT_INTENCLR_DIGEST_MASK (0x2U) +#define HASHCRYPT_INTENCLR_DIGEST_SHIFT (1U) +#define HASHCRYPT_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK) +#define HASHCRYPT_INTENCLR_ERROR_MASK (0x4U) +#define HASHCRYPT_INTENCLR_ERROR_SHIFT (2U) +#define HASHCRYPT_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK) +/*! @} */ + +/*! @name MEMCTRL - Setup Master to access memory (if available) */ +/*! @{ */ +#define HASHCRYPT_MEMCTRL_MASTER_MASK (0x1U) +#define HASHCRYPT_MEMCTRL_MASTER_SHIFT (0U) +/*! MASTER - Enables mastering. + * 0b0..Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. + * 0b1..Mastering is enabled and DMA and INDATA should not be used. + */ +#define HASHCRYPT_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK) +#define HASHCRYPT_MEMCTRL_COUNT_MASK (0x7FF0000U) +#define HASHCRYPT_MEMCTRL_COUNT_SHIFT (16U) +#define HASHCRYPT_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK) +/*! @} */ + +/*! @name MEMADDR - Address to start memory access from (if available). */ +/*! @{ */ +#define HASHCRYPT_MEMADDR_BASE_MASK (0xFFFFFFFFU) +#define HASHCRYPT_MEMADDR_BASE_SHIFT (0U) +#define HASHCRYPT_MEMADDR_BASE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK) +/*! @} */ + +/*! @name INDATA - Input of 16 words at a time to load up buffer. */ +/*! @{ */ +#define HASHCRYPT_INDATA_DATA_MASK (0xFFFFFFFFU) +#define HASHCRYPT_INDATA_DATA_SHIFT (0U) +#define HASHCRYPT_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK) +/*! @} */ + +/*! @name ALIAS - */ +/*! @{ */ +#define HASHCRYPT_ALIAS_DATA_MASK (0xFFFFFFFFU) +#define HASHCRYPT_ALIAS_DATA_SHIFT (0U) +#define HASHCRYPT_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK) +/*! @} */ + +/* The count of HASHCRYPT_ALIAS */ +#define HASHCRYPT_ALIAS_COUNT (7U) + +/*! @name DIGEST0 - */ +/*! @{ */ +#define HASHCRYPT_DIGEST0_DIGEST_MASK (0xFFFFFFFFU) +#define HASHCRYPT_DIGEST0_DIGEST_SHIFT (0U) +#define HASHCRYPT_DIGEST0_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_DIGEST0_DIGEST_SHIFT)) & HASHCRYPT_DIGEST0_DIGEST_MASK) +/*! @} */ + +/* The count of HASHCRYPT_DIGEST0 */ +#define HASHCRYPT_DIGEST0_COUNT (8U) + +/*! @name CRYPTCFG - Crypto settings for AES and Salsa and ChaCha */ +/*! @{ */ +#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK (0x1U) +#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT (0U) +#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK) +#define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK (0x2U) +#define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT (1U) +#define HASHCRYPT_CRYPTCFG_SWAPKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK) +#define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK (0x4U) +#define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT (2U) +#define HASHCRYPT_CRYPTCFG_SWAPDAT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK) +#define HASHCRYPT_CRYPTCFG_MSW1ST_MASK (0x8U) +#define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT (3U) +#define HASHCRYPT_CRYPTCFG_MSW1ST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK) +#define HASHCRYPT_CRYPTCFG_AESMODE_MASK (0x30U) +#define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT (4U) +/*! AESMODE - AES Cipher mode to use if plain AES + * 0b00..ECB - used as is + * 0b01..CBC mode (see details on IV/nonce) + * 0b10..CTR mode (see details on IV/nonce). See also AESCTRPOS. + * 0b11..reserved + */ +#define HASHCRYPT_CRYPTCFG_AESMODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK) +#define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK (0x40U) +#define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT (6U) +/*! AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB + * 0b0..Encrypt + * 0b1..Decrypt + */ +#define HASHCRYPT_CRYPTCFG_AESDECRYPT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK) +#define HASHCRYPT_CRYPTCFG_AESSECRET_MASK (0x80U) +#define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT (7U) +/*! AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are + * used, only the highest level is permitted to select this. + * 0b0..User key provided in normal way + * 0b1..Secret key provided in hidden way by HW + */ +#define HASHCRYPT_CRYPTCFG_AESSECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK) +#define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK (0x300U) +#define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT (8U) +/*! AESKEYSZ - Sets the AES key size + * 0b00..128 bit key + * 0b01..192 bit key + * 0b10..256 bit key + * 0b11..reserved + */ +#define HASHCRYPT_CRYPTCFG_AESKEYSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK) +#define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK (0x1C00U) +#define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT (10U) +#define HASHCRYPT_CRYPTCFG_AESCTRPOS(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK) +#define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK (0x10000U) +#define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT (16U) +#define HASHCRYPT_CRYPTCFG_STREAMLAST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK) +#define HASHCRYPT_CRYPTCFG_ICBSZ_MASK (0x300000U) +#define HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT (20U) +/*! ICBSZ - This sets the ICB size between 32 and 128 bits, using the following rules. Note that the + * counter is assumed to occupy the low order bits of the IV. + * 0b00..32 bits of the IV/ctr are used (from 127:96) + * 0b01..64 bits of the IV/ctr are used (from 127:64) + * 0b10..96 bits of the IV/ctr are used (from 127:32) + * 0b11..All 128 bits of the IV/ctr are used + */ +#define HASHCRYPT_CRYPTCFG_ICBSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSZ_MASK) +#define HASHCRYPT_CRYPTCFG_ICBSTRM_MASK (0xC00000U) +#define HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT (22U) +/*! ICBSTRM - The size of the ICB-AES stream that can be pushed before needing to compute a new + * IV/ctr (counter start). This optimizes the performance of the stream of blocks after the 1st. + * 0b00..8 blocks + * 0b01..16 blocks + * 0b10..32 blocks + * 0b11..64 blocks + */ +#define HASHCRYPT_CRYPTCFG_ICBSTRM(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSTRM_MASK) +/*! @} */ + +/*! @name CONFIG - Returns the configuration of this block in this chip - indicates what services are available. */ +/*! @{ */ +#define HASHCRYPT_CONFIG_DUAL_MASK (0x1U) +#define HASHCRYPT_CONFIG_DUAL_SHIFT (0U) +#define HASHCRYPT_CONFIG_DUAL(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK) +#define HASHCRYPT_CONFIG_DMA_MASK (0x2U) +#define HASHCRYPT_CONFIG_DMA_SHIFT (1U) +#define HASHCRYPT_CONFIG_DMA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK) +#define HASHCRYPT_CONFIG_AHB_MASK (0x8U) +#define HASHCRYPT_CONFIG_AHB_SHIFT (3U) +#define HASHCRYPT_CONFIG_AHB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK) +#define HASHCRYPT_CONFIG_AES_MASK (0x40U) +#define HASHCRYPT_CONFIG_AES_SHIFT (6U) +#define HASHCRYPT_CONFIG_AES(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK) +#define HASHCRYPT_CONFIG_AESKEY_MASK (0x80U) +#define HASHCRYPT_CONFIG_AESKEY_SHIFT (7U) +#define HASHCRYPT_CONFIG_AESKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK) +#define HASHCRYPT_CONFIG_SECRET_MASK (0x100U) +#define HASHCRYPT_CONFIG_SECRET_SHIFT (8U) +#define HASHCRYPT_CONFIG_SECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK) +#define HASHCRYPT_CONFIG_ICB_MASK (0x800U) +#define HASHCRYPT_CONFIG_ICB_SHIFT (11U) +#define HASHCRYPT_CONFIG_ICB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_ICB_SHIFT)) & HASHCRYPT_CONFIG_ICB_MASK) +/*! @} */ + +/*! @name LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. */ +/*! @{ */ +#define HASHCRYPT_LOCK_SECLOCK_MASK (0x3U) +#define HASHCRYPT_LOCK_SECLOCK_SHIFT (0U) +/*! SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. + * If locked already, may only write if at same or higher security level as lock. Reads as: 0 if + * unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the + * only readable registers if locked and current state is lower than lock level. + * 0b00..Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests. + * 0b01..Locks to the current security level. AHB Master will issue requests at this level. + */ +#define HASHCRYPT_LOCK_SECLOCK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK) +#define HASHCRYPT_LOCK_PATTERN_MASK (0xFFF0U) +#define HASHCRYPT_LOCK_PATTERN_SHIFT (4U) +#define HASHCRYPT_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK) +/*! @} */ + +/*! @name MASK - */ +/*! @{ */ +#define HASHCRYPT_MASK_MASK_MASK (0xFFFFFFFFU) +#define HASHCRYPT_MASK_MASK_SHIFT (0U) +#define HASHCRYPT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK) +/*! @} */ + +/* The count of HASHCRYPT_MASK */ +#define HASHCRYPT_MASK_COUNT (4U) + + +/*! + * @} + */ /* end of group HASHCRYPT_Register_Masks */ + + +/* HASHCRYPT - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE (0x500A4000u) + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE_NS (0x400A4000u) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT_NS ((HASHCRYPT_Type *)HASHCRYPT_BASE_NS) + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS { HASHCRYPT } + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS_NS { HASHCRYPT_BASE_NS } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS_NS { HASHCRYPT_NS } +#else + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE (0x400A4000u) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS { HASHCRYPT } +#endif + +/*! + * @} + */ /* end of group HASHCRYPT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2048]; + __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ + __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ + __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ + __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ + __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ + __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ + uint8_t RESERVED_1[4]; + __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ + __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ + __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ + uint8_t RESERVED_2[20]; + __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ + __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ + __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ + __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ + uint8_t RESERVED_3[36]; + __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ + uint8_t RESERVED_4[1912]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/*! @name CFG - Configuration for shared functions. */ +/*! @{ */ +#define I2C_CFG_MSTEN_MASK (0x1U) +#define I2C_CFG_MSTEN_SHIFT (0U) +/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not + * changed, but the Master function is internally reset. + * 0b0..Disabled. The I2C Master function is disabled. + * 0b1..Enabled. The I2C Master function is enabled. + */ +#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) +#define I2C_CFG_SLVEN_MASK (0x2U) +#define I2C_CFG_SLVEN_SHIFT (1U) +/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not + * changed, but the Slave function is internally reset. + * 0b0..Disabled. The I2C slave function is disabled. + * 0b1..Enabled. The I2C slave function is enabled. + */ +#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) +#define I2C_CFG_MONEN_MASK (0x4U) +#define I2C_CFG_MONEN_SHIFT (2U) +/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not + * changed, but the Monitor function is internally reset. + * 0b0..Disabled. The I2C Monitor function is disabled. + * 0b1..Enabled. The I2C Monitor function is enabled. + */ +#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) +#define I2C_CFG_TIMEOUTEN_MASK (0x8U) +#define I2C_CFG_TIMEOUTEN_SHIFT (3U) +/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. + * 0b0..Disabled. Time-out function is disabled. + * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause + * interrupts if they are enabled. Typically, only one time-out will be used in a system. + */ +#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) +#define I2C_CFG_MONCLKSTR_MASK (0x10U) +#define I2C_CFG_MONCLKSTR_SHIFT (4U) +/*! MONCLKSTR - Monitor function Clock Stretching. + * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able + * to read data provided by the Monitor function before it is overwritten. This mode may be used when + * non-invasive monitoring is critical. + * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can + * read all incoming data supplied by the Monitor function. + */ +#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) +#define I2C_CFG_HSCAPABLE_MASK (0x20U) +#define I2C_CFG_HSCAPABLE_SHIFT (5U) +/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive + * and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies + * to all functions: Master, Slave, and Monitor. + * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the + * extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, + * such as changing the drive strength or filtering, must be made by software via the IOCON register associated + * with each I2C pin, + * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support + * High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more + * information. + */ +#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) +/*! @} */ + +/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ +#define I2C_STAT_MSTPENDING_MASK (0x1U) +#define I2C_STAT_MSTPENDING_SHIFT (0U) +/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on + * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what + * type of software service if any the master expects. This flag will cause an interrupt when set + * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling + * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle + * state, and no communication is needed, mask this interrupt. + * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. + * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the + * idle state, it is waiting to receive or transmit data or the NACK bit. + */ +#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) +#define I2C_STAT_MSTSTATE_MASK (0xEU) +#define I2C_STAT_MSTSTATE_SHIFT (1U) +/*! MSTSTATE - Master State code. The master state code reflects the master state when the + * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field + * indicates a specific required service for the Master function. All other values are reserved. See + * Table 400 for details of state values and appropriate responses. + * 0b000..Idle. The Master function is available to be used for a new transaction. + * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. + * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. + * 0b011..NACK Address. Slave NACKed address. + * 0b100..NACK Data. Slave NACKed transmitted data. + */ +#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) +#define I2C_STAT_MSTARBLOSS_MASK (0x10U) +#define I2C_STAT_MSTARBLOSS_SHIFT (4U) +/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to + * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + * 0b0..No Arbitration Loss has occurred. + * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master + * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, + * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. + */ +#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) +#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) +/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to + * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + * 0b0..No Start/Stop Error has occurred. + * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is + * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an + * idle state, no action is required. A request for a Start could be made, or software could attempt to insure + * that the bus has not stalled. + */ +#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) +#define I2C_STAT_SLVPENDING_MASK (0x100U) +#define I2C_STAT_SLVPENDING_SHIFT (8U) +/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue + * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if + * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the + * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is + * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time + * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section + * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are + * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must + * also be detected automatically, since the address must be acknowledged before the clock can be + * stretched. + * 0b0..In progress. The Slave function does not currently need service. + * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. + */ +#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) +#define I2C_STAT_SLVSTATE_MASK (0x600U) +#define I2C_STAT_SLVSTATE_SHIFT (9U) +/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for + * the Slave function. All other values are reserved. See Table 401 for state values and actions. + * note that the occurrence of some states and how they are handled are affected by DMA mode and + * Automatic Operation modes. + * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. + * 0b01..Slave receive. Received data is available (Slave Receiver mode). + * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). + */ +#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) +#define I2C_STAT_SLVNOTSTR_MASK (0x800U) +#define I2C_STAT_SLVNOTSTR_SHIFT (11U) +/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. + * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave + * operation. This read-only flag reflects the slave function status in real time. + * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. + * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or + * Power-down mode could be entered at this time. + */ +#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) +#define I2C_STAT_SLVIDX_MASK (0x3000U) +#define I2C_STAT_SLVIDX_SHIFT (12U) +/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been + * selected by receiving an address that matches one of the slave addresses defined by any enabled + * slave address registers, and provides an identification of the address that was matched. It is + * possible that more than one address could be matched, but only one match can be reported here. + * 0b00..Address 0. Slave address 0 was matched. + * 0b01..Address 1. Slave address 1 was matched. + * 0b10..Address 2. Slave address 2 was matched. + * 0b11..Address 3. Slave address 3 was matched. + */ +#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) +#define I2C_STAT_SLVSEL_MASK (0x4000U) +#define I2C_STAT_SLVSEL_SHIFT (14U) +/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave + * function to acknowledge the address, or when the address has been automatically acknowledged. + * It is cleared when another address cycle presents an address that does not match an enabled + * address on the Slave function, when slave software decides to NACK a matched address, when + * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of + * Automatic Operation. SLVSEL is not cleared if software NACKs data. + * 0b0..Not selected. The Slave function is not currently selected. + * 0b1..Selected. The Slave function is currently selected. + */ +#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) +#define I2C_STAT_SLVDESEL_MASK (0x8000U) +#define I2C_STAT_SLVDESEL_SHIFT (15U) +/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via + * INTENSET. This flag can be cleared by writing a 1 to this bit. + * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently + * selected. That information can be found in the SLVSEL flag. + * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag + * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. + */ +#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) +#define I2C_STAT_MONRDY_MASK (0x10000U) +#define I2C_STAT_MONRDY_SHIFT (16U) +/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. + * 0b0..No data. The Monitor function does not currently have data available. + * 0b1..Data waiting. The Monitor function has data waiting to be read. + */ +#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) +#define I2C_STAT_MONOV_MASK (0x20000U) +#define I2C_STAT_MONOV_SHIFT (17U) +/*! MONOV - Monitor Overflow flag. + * 0b0..No overrun. Monitor data has not overrun. + * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not + * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. + */ +#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) +#define I2C_STAT_MONACTIVE_MASK (0x40000U) +#define I2C_STAT_MONACTIVE_SHIFT (18U) +/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to + * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred + * more recently than a bus Stop. + * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. + * 0b1..Active. The Monitor function considers the I2C bus to be active. + */ +#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) +#define I2C_STAT_MONIDLE_MASK (0x80000U) +#define I2C_STAT_MONIDLE_SHIFT (19U) +/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change + * from active to inactive. This can be used by software to decide when to process data + * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the + * INTENSET register. The flag can be cleared by writing a 1 to this bit. + * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. + * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. + */ +#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) +#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) +/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been + * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock + * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus + * is idle. + * 0b0..No time-out. I2C bus events have not caused a time-out. + * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. + */ +#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) +#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) +/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the + * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. + * 0b0..No time-out. SCL low time has not caused a time-out. + * 0b1..Time-out. SCL low time has caused a time-out. + */ +#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable Set and read register. */ +/*! @{ */ +#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) +#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) +/*! MSTPENDINGEN - Master Pending interrupt Enable. + * 0b0..Disabled. The MstPending interrupt is disabled. + * 0b1..Enabled. The MstPending interrupt is enabled. + */ +#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) +#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) +#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) +/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. + * 0b0..Disabled. The MstArbLoss interrupt is disabled. + * 0b1..Enabled. The MstArbLoss interrupt is enabled. + */ +#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) +#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) +#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) +/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. + * 0b0..Disabled. The MstStStpErr interrupt is disabled. + * 0b1..Enabled. The MstStStpErr interrupt is enabled. + */ +#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) +#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) +#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) +/*! SLVPENDINGEN - Slave Pending interrupt Enable. + * 0b0..Disabled. The SlvPending interrupt is disabled. + * 0b1..Enabled. The SlvPending interrupt is enabled. + */ +#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) +#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) +#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) +/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. + * 0b0..Disabled. The SlvNotStr interrupt is disabled. + * 0b1..Enabled. The SlvNotStr interrupt is enabled. + */ +#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) +#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) +#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) +/*! SLVDESELEN - Slave Deselect interrupt Enable. + * 0b0..Disabled. The SlvDeSel interrupt is disabled. + * 0b1..Enabled. The SlvDeSel interrupt is enabled. + */ +#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) +#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) +#define I2C_INTENSET_MONRDYEN_SHIFT (16U) +/*! MONRDYEN - Monitor data Ready interrupt Enable. + * 0b0..Disabled. The MonRdy interrupt is disabled. + * 0b1..Enabled. The MonRdy interrupt is enabled. + */ +#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) +#define I2C_INTENSET_MONOVEN_MASK (0x20000U) +#define I2C_INTENSET_MONOVEN_SHIFT (17U) +/*! MONOVEN - Monitor Overrun interrupt Enable. + * 0b0..Disabled. The MonOv interrupt is disabled. + * 0b1..Enabled. The MonOv interrupt is enabled. + */ +#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) +#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) +#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) +/*! MONIDLEEN - Monitor Idle interrupt Enable. + * 0b0..Disabled. The MonIdle interrupt is disabled. + * 0b1..Enabled. The MonIdle interrupt is enabled. + */ +#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) +#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) +#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) +/*! EVENTTIMEOUTEN - Event time-out interrupt Enable. + * 0b0..Disabled. The Event time-out interrupt is disabled. + * 0b1..Enabled. The Event time-out interrupt is enabled. + */ +#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) +#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) +#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) +/*! SCLTIMEOUTEN - SCL time-out interrupt Enable. + * 0b0..Disabled. The SCL time-out interrupt is disabled. + * 0b1..Enabled. The SCL time-out interrupt is enabled. + */ +#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear register. */ +/*! @{ */ +#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) +#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) +#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) +#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) +#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) +#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) +#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) +#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) +#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) +#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) +#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) +#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) +#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) +#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) +#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) +#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) +#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) +#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) +#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) +#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) +#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) +#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) +#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) +#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) +#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) +#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) +#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) +#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) +#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) +#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) +#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) +#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) +#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) +/*! @} */ + +/*! @name TIMEOUT - Time-out value register. */ +/*! @{ */ +#define I2C_TIMEOUT_TOMIN_MASK (0xFU) +#define I2C_TIMEOUT_TOMIN_SHIFT (0U) +#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) +#define I2C_TIMEOUT_TO_MASK (0xFFF0U) +#define I2C_TIMEOUT_TO_SHIFT (4U) +#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) +/*! @} */ + +/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ +/*! @{ */ +#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) +#define I2C_CLKDIV_DIVVAL_SHIFT (0U) +#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ +#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) +#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) +#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) +#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) +#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) +#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) +#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) +#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) +#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) +#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) +#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) +#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) +#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) +#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) +#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) +#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) +#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) +#define I2C_INTSTAT_MONRDY_MASK (0x10000U) +#define I2C_INTSTAT_MONRDY_SHIFT (16U) +#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) +#define I2C_INTSTAT_MONOV_MASK (0x20000U) +#define I2C_INTSTAT_MONOV_SHIFT (17U) +#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) +#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) +#define I2C_INTSTAT_MONIDLE_SHIFT (19U) +#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) +#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) +#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) +#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) +#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name MSTCTL - Master control register. */ +/*! @{ */ +#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) +#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) +/*! MSTCONTINUE - Master Continue. This bit is write-only. + * 0b0..No effect. + * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing + * transmit data, reading received data, or any other housekeeping related to the next bus operation. + */ +#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) +#define I2C_MSTCTL_MSTSTART_MASK (0x2U) +#define I2C_MSTCTL_MSTSTART_SHIFT (1U) +/*! MSTSTART - Master Start control. This bit is write-only. + * 0b0..No effect. + * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. + */ +#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) +#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) +#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) +/*! MSTSTOP - Master Stop control. This bit is write-only. + * 0b0..No effect. + * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave + * if the master is receiving data from the slave (Master Receiver mode). + */ +#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) +#define I2C_MSTCTL_MSTDMA_MASK (0x8U) +#define I2C_MSTCTL_MSTDMA_SHIFT (3U) +/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type + * operations such as Start, address, Stop, and address match must always be done with software, + * typically via an interrupt. Address acknowledgement must also be done by software except when + * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by + * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA + * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is + * read/write. + * 0b0..Disable. No DMA requests are generated for master operation. + * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating + * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. + */ +#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) +/*! @} */ + +/*! @name MSTTIME - Master timing configuration. */ +/*! @{ */ +#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) +#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) +/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this + * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This + * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters + * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. + * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. + * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. + * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. + * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. + * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. + * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. + * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. + * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. + */ +#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) +#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) +#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) +/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this + * master on SCL. Other masters in a multi-master system could shorten this time. This + * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters + * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. + * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. + * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . + * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. + * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. + * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. + * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. + * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. + * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. + */ +#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) +/*! @} */ + +/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ +/*! @{ */ +#define I2C_MSTDAT_DATA_MASK (0xFFU) +#define I2C_MSTDAT_DATA_SHIFT (0U) +#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVCTL - Slave control register. */ +/*! @{ */ +#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) +#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) +/*! SLVCONTINUE - Slave Continue. + * 0b0..No effect. + * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag + * in the STAT register. This must be done after writing transmit data, reading received data, or any other + * housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE + * should not be set unless SLVPENDING = 1. + */ +#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) +#define I2C_SLVCTL_SLVNACK_MASK (0x2U) +#define I2C_SLVCTL_SLVNACK_SHIFT (1U) +/*! SLVNACK - Slave NACK. + * 0b0..No effect. + * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). + */ +#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) +#define I2C_SLVCTL_SLVDMA_MASK (0x8U) +#define I2C_SLVCTL_SLVDMA_SHIFT (3U) +/*! SLVDMA - Slave DMA enable. + * 0b0..Disabled. No DMA requests are issued for Slave mode operation. + * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. + */ +#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) +#define I2C_SLVCTL_AUTOACK_MASK (0x100U) +#define I2C_SLVCTL_AUTOACK_SHIFT (8U) +/*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches + * SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA + * to allow processing of the data without intervention. If this bit is clear and a header + * matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or + * interrupt. + * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching + * address is received. If AUTONACK = 1, received addresses are NACKed (ignored). + * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, + * allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does + * not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK + * is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. + */ +#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) +#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) +#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) +/*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write + * request on the next header with an address matching SLVADR0. Since DMA needs to be configured to + * match the transfer direction, the direction needs to be specified. This bit allows a direction to + * be chosen for the next operation. + * 0b0..The expected next operation in Automatic Mode is an I2C write. + * 0b1..The expected next operation in Automatic Mode is an I2C read. + */ +#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) +/*! @} */ + +/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ +/*! @{ */ +#define I2C_SLVDAT_DATA_MASK (0xFFU) +#define I2C_SLVDAT_DATA_SHIFT (0U) +#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVADR - Slave address register. */ +/*! @{ */ +#define I2C_SLVADR_SADISABLE_MASK (0x1U) +#define I2C_SLVADR_SADISABLE_SHIFT (0U) +/*! SADISABLE - Slave Address n Disable. + * 0b0..Enabled. Slave Address n is enabled. + * 0b1..Ignored Slave Address n is ignored. + */ +#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) +#define I2C_SLVADR_SLVADR_MASK (0xFEU) +#define I2C_SLVADR_SLVADR_SHIFT (1U) +#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) +#define I2C_SLVADR_AUTONACK_MASK (0x8000U) +#define I2C_SLVADR_AUTONACK_SHIFT (15U) +/*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows + * software to ignore I2C traffic while handling previous I2C data or other operations. + * 0b0..Normal operation, matching I2C addresses are not ignored. + * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches + * SLVADRn, and AUTOMATCHREAD matches the direction. + */ +#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) +/*! @} */ + +/* The count of I2C_SLVADR */ +#define I2C_SLVADR_COUNT (4U) + +/*! @name SLVQUAL0 - Slave Qualification for address 0. */ +/*! @{ */ +#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) +#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) +/*! QUALMODE0 - Qualify mode for slave address 0. + * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. + * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. + */ +#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) +#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) +#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) +#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) +/*! @} */ + +/*! @name MONRXDAT - Monitor receiver data register. */ +/*! @{ */ +#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) +#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) +#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) +#define I2C_MONRXDAT_MONSTART_MASK (0x100U) +#define I2C_MONRXDAT_MONSTART_SHIFT (8U) +/*! MONSTART - Monitor Received Start. + * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. + * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. + */ +#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) +#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) +#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) +/*! MONRESTART - Monitor Received Repeated Start. + * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. + * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. + */ +#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) +#define I2C_MONRXDAT_MONNACK_MASK (0x400U) +#define I2C_MONRXDAT_MONNACK_SHIFT (10U) +/*! MONNACK - Monitor Received NACK. + * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. + * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. + */ +#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ +#define I2C_ID_APERTURE_MASK (0xFFU) +#define I2C_ID_APERTURE_SHIFT (0U) +#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) +#define I2C_ID_MINOR_REV_MASK (0xF00U) +#define I2C_ID_MINOR_REV_SHIFT (8U) +#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) +#define I2C_ID_MAJOR_REV_MASK (0xF000U) +#define I2C_ID_MAJOR_REV_SHIFT (12U) +#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) +#define I2C_ID_ID_MASK (0xFFFF0000U) +#define I2C_ID_ID_SHIFT (16U) +#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral I2C0 base address */ + #define I2C0_BASE (0x50086000u) + /** Peripheral I2C0 base address */ + #define I2C0_BASE_NS (0x40086000u) + /** Peripheral I2C0 base pointer */ + #define I2C0 ((I2C_Type *)I2C0_BASE) + /** Peripheral I2C0 base pointer */ + #define I2C0_NS ((I2C_Type *)I2C0_BASE_NS) + /** Peripheral I2C1 base address */ + #define I2C1_BASE (0x50087000u) + /** Peripheral I2C1 base address */ + #define I2C1_BASE_NS (0x40087000u) + /** Peripheral I2C1 base pointer */ + #define I2C1 ((I2C_Type *)I2C1_BASE) + /** Peripheral I2C1 base pointer */ + #define I2C1_NS ((I2C_Type *)I2C1_BASE_NS) + /** Peripheral I2C2 base address */ + #define I2C2_BASE (0x50088000u) + /** Peripheral I2C2 base address */ + #define I2C2_BASE_NS (0x40088000u) + /** Peripheral I2C2 base pointer */ + #define I2C2 ((I2C_Type *)I2C2_BASE) + /** Peripheral I2C2 base pointer */ + #define I2C2_NS ((I2C_Type *)I2C2_BASE_NS) + /** Peripheral I2C3 base address */ + #define I2C3_BASE (0x50089000u) + /** Peripheral I2C3 base address */ + #define I2C3_BASE_NS (0x40089000u) + /** Peripheral I2C3 base pointer */ + #define I2C3 ((I2C_Type *)I2C3_BASE) + /** Peripheral I2C3 base pointer */ + #define I2C3_NS ((I2C_Type *)I2C3_BASE_NS) + /** Peripheral I2C4 base address */ + #define I2C4_BASE (0x5008A000u) + /** Peripheral I2C4 base address */ + #define I2C4_BASE_NS (0x4008A000u) + /** Peripheral I2C4 base pointer */ + #define I2C4 ((I2C_Type *)I2C4_BASE) + /** Peripheral I2C4 base pointer */ + #define I2C4_NS ((I2C_Type *)I2C4_BASE_NS) + /** Peripheral I2C5 base address */ + #define I2C5_BASE (0x50096000u) + /** Peripheral I2C5 base address */ + #define I2C5_BASE_NS (0x40096000u) + /** Peripheral I2C5 base pointer */ + #define I2C5 ((I2C_Type *)I2C5_BASE) + /** Peripheral I2C5 base pointer */ + #define I2C5_NS ((I2C_Type *)I2C5_BASE_NS) + /** Peripheral I2C6 base address */ + #define I2C6_BASE (0x50097000u) + /** Peripheral I2C6 base address */ + #define I2C6_BASE_NS (0x40097000u) + /** Peripheral I2C6 base pointer */ + #define I2C6 ((I2C_Type *)I2C6_BASE) + /** Peripheral I2C6 base pointer */ + #define I2C6_NS ((I2C_Type *)I2C6_BASE_NS) + /** Peripheral I2C7 base address */ + #define I2C7_BASE (0x50098000u) + /** Peripheral I2C7 base address */ + #define I2C7_BASE_NS (0x40098000u) + /** Peripheral I2C7 base pointer */ + #define I2C7 ((I2C_Type *)I2C7_BASE) + /** Peripheral I2C7 base pointer */ + #define I2C7_NS ((I2C_Type *)I2C7_BASE_NS) + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS_NS { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS_NS { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS } +#else + /** Peripheral I2C0 base address */ + #define I2C0_BASE (0x40086000u) + /** Peripheral I2C0 base pointer */ + #define I2C0 ((I2C_Type *)I2C0_BASE) + /** Peripheral I2C1 base address */ + #define I2C1_BASE (0x40087000u) + /** Peripheral I2C1 base pointer */ + #define I2C1 ((I2C_Type *)I2C1_BASE) + /** Peripheral I2C2 base address */ + #define I2C2_BASE (0x40088000u) + /** Peripheral I2C2 base pointer */ + #define I2C2 ((I2C_Type *)I2C2_BASE) + /** Peripheral I2C3 base address */ + #define I2C3_BASE (0x40089000u) + /** Peripheral I2C3 base pointer */ + #define I2C3 ((I2C_Type *)I2C3_BASE) + /** Peripheral I2C4 base address */ + #define I2C4_BASE (0x4008A000u) + /** Peripheral I2C4 base pointer */ + #define I2C4 ((I2C_Type *)I2C4_BASE) + /** Peripheral I2C5 base address */ + #define I2C5_BASE (0x40096000u) + /** Peripheral I2C5 base pointer */ + #define I2C5 ((I2C_Type *)I2C5_BASE) + /** Peripheral I2C6 base address */ + #define I2C6_BASE (0x40097000u) + /** Peripheral I2C6 base pointer */ + #define I2C6 ((I2C_Type *)I2C6_BASE) + /** Peripheral I2C7 base address */ + #define I2C7_BASE (0x40098000u) + /** Peripheral I2C7 base pointer */ + #define I2C7 ((I2C_Type *)I2C7_BASE) + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } +#endif +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[3072]; + __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ + __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ + __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ + uint8_t RESERVED_2[480]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ + uint8_t RESERVED_5[8]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ + uint8_t RESERVED_6[8]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ + uint8_t RESERVED_7[436]; + __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ +/*! @{ */ +#define I2S_CFG1_MAINENABLE_MASK (0x1U) +#define I2S_CFG1_MAINENABLE_SHIFT (0U) +/*! MAINENABLE - Main enable for I 2S function in this Flexcomm + * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags + * are reset. No other channel pairs can be enabled. + * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. + */ +#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) +#define I2S_CFG1_DATAPAUSE_MASK (0x2U) +#define I2S_CFG1_DATAPAUSE_SHIFT (1U) +/*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer + * and the FIFO. This could be done in order to change streams, or while restarting after a data + * underflow or overflow. When paused, FIFO operations can be done without corrupting data that is + * in the process of being sent or received. Once a data pause has been requested, the interface + * may need to complete sending data that was in progress before interrupting the flow of data. + * Software must check that the pause is actually in effect before taking action. This is done by + * monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer + * will resume at the beginning of the next frame. + * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. + * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. + */ +#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) +#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) +#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) +/*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field + * whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this + * Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs + * in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. + * 0b00..1 I2S channel pairs in this flexcomm + * 0b01..2 I2S channel pairs in this flexcomm + * 0b10..3 I2S channel pairs in this flexcomm + * 0b11..4 I2S channel pairs in this flexcomm + */ +#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) +#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) +#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) +/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. + * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. + * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of + * SCK, when divided from the Flexcomm function clock. + * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. + * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. + */ +#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) +#define I2S_CFG1_MODE_MASK (0xC0U) +#define I2S_CFG1_MODE_SHIFT (6U) +/*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all + * supported cases. See Formats and modes for examples. + * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece + * of left channel data occurring during the first phase, and one pieces of right channel data occurring + * during the second phase. In this mode, the data region begins one clock after the leading WS edge for the + * frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If + * FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. + * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0. + * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame. + * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame. + */ +#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) +#define I2S_CFG1_RIGHTLOW_MASK (0x100U) +#define I2S_CFG1_RIGHTLOW_SHIFT (8U) +/*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left + * and right channel data as it is transferred to or from the FIFO. This bit is not used if the + * data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 + * of this register) = 1, the one channel to be used is the nominally the left channel. POSITION + * can still place that data in the frame where right channel data is normally located. if all + * enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. + * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO + * bits 31:16 are used for the right channel. + * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO + * bits 15:0 are used for the right channel. + */ +#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) +#define I2S_CFG1_LEFTJUST_MASK (0x200U) +#define I2S_CFG1_LEFTJUST_SHIFT (9U) +/*! LEFTJUST - Left Justify data. + * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting + * from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data + * in the stream on the data bus. + * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting + * from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would + * correspond to left justified data in the stream on the data bus. + */ +#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) +#define I2S_CFG1_ONECHANNEL_MASK (0x400U) +#define I2S_CFG1_ONECHANNEL_SHIFT (10U) +/*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit + * applies only to the first I2S channel pair. Other channel pairs may select this mode + * independently in their separate CFG1 registers. + * 0b0..I2S data for this channel pair is treated as left and right channels. + * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this + * pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a + * clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel + * of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side + * (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data + * for the single channel of data is placed at the clock defined by POSITION. + */ +#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) +#define I2S_CFG1_SCK_POL_MASK (0x1000U) +#define I2S_CFG1_SCK_POL_SHIFT (12U) +/*! SCK_POL - SCK polarity. + * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). + * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges. + */ +#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) +#define I2S_CFG1_WS_POL_MASK (0x2000U) +#define I2S_CFG1_WS_POL_SHIFT (13U) +/*! WS_POL - WS polarity. + * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S). + * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). + */ +#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) +#define I2S_CFG1_DATALEN_MASK (0x1F0000U) +#define I2S_CFG1_DATALEN_SHIFT (16U) +#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) +/*! @} */ + +/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ +/*! @{ */ +#define I2S_CFG2_FRAMELEN_MASK (0x1FFU) +#define I2S_CFG2_FRAMELEN_SHIFT (0U) +#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) +#define I2S_CFG2_POSITION_MASK (0x1FF0000U) +#define I2S_CFG2_POSITION_SHIFT (16U) +#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) +/*! @} */ + +/*! @name STAT - Status register for the primary channel pair. */ +/*! @{ */ +#define I2S_STAT_BUSY_MASK (0x1U) +#define I2S_STAT_BUSY_SHIFT (0U) +/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. + * 0b0..The transmitter/receiver for channel pair is currently idle. + * 0b1..The transmitter/receiver for channel pair is currently processing data. + */ +#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) +#define I2S_STAT_SLVFRMERR_MASK (0x2U) +#define I2S_STAT_SLVFRMERR_SHIFT (1U) +/*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as + * a slave. An error indicates that the incoming WS signal did not transition as expected due to + * a mismatch between FRAMELEN and the actual incoming I2S stream. + * 0b0..No error has been recorded. + * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. + */ +#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) +#define I2S_STAT_LR_MASK (0x4U) +#define I2S_STAT_LR_SHIFT (2U) +/*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to + * be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data + * being processed for the currently busy channel pair. + * 0b0..Left channel. + * 0b1..Right channel. + */ +#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) +#define I2S_STAT_DATAPAUSED_MASK (0x8U) +#define I2S_STAT_DATAPAUSED_SHIFT (3U) +/*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels + * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for + * an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. + * 0b1..A data pause has been requested and is now in force. + */ +#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) +/*! @} */ + +/*! @name DIV - Clock divider, used by all channel pairs. */ +/*! @{ */ +#define I2S_DIV_DIV_MASK (0xFFFU) +#define I2S_DIV_DIV_SHIFT (0U) +#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ +#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) +#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) +#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) +#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) +#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) +#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) +/*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX + * FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is + * cleared, new data is provided, and the I2S is un-paused. + * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 + * bits or less, or when MONO = 1 for this channel pair. + * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. + */ +#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) +#define I2S_FIFOCFG_PACK48_MASK (0x8U) +#define I2S_FIFOCFG_PACK48_SHIFT (3U) +/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. + * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values. + * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. + */ +#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) +#define I2S_FIFOCFG_SIZE_MASK (0x30U) +#define I2S_FIFOCFG_SIZE_SHIFT (4U) +#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) +#define I2S_FIFOCFG_DMATX_MASK (0x1000U) +#define I2S_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) +#define I2S_FIFOCFG_DMARX_MASK (0x2000U) +#define I2S_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) +#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) +#define I2S_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) +#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) +#define I2S_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in + * FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) +#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) +#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) +#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) +#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ +#define I2S_FIFOSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOSTAT_TXERR_SHIFT (0U) +#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) +#define I2S_FIFOSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOSTAT_RXERR_SHIFT (1U) +#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) +#define I2S_FIFOSTAT_PERINT_MASK (0x8U) +#define I2S_FIFOSTAT_PERINT_SHIFT (3U) +#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) +#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) +#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) +#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) +#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) +#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) +#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) +#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) +#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) +#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) +#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) +#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) +#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ +#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) +#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) +#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) +#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) +#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) +#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) +#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ +#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) +#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) +#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) +#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) +#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases + * to the level specified by TXLVL in the FIFOTRIG register. + */ +#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) +#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level + * increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ +#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) +#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) +#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) +#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) +#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) +#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) +#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) +#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) +#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) +#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ +#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) +#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) +#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) +#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) +#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) +#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) +#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) +#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) +#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) +#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) +#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ +#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFOWR_TXDATA_SHIFT (0U) +#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ +#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) +#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) +#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ +#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORD_RXDATA_SHIFT (0U) +#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ +#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48H_RXDATA_SHIFT (0U) +#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ +#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) +#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ +#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) +#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) +/*! @} */ + +/*! @name ID - I2S Module identification */ +/*! @{ */ +#define I2S_ID_APERTURE_MASK (0xFFU) +#define I2S_ID_APERTURE_SHIFT (0U) +#define I2S_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_APERTURE_SHIFT)) & I2S_ID_APERTURE_MASK) +#define I2S_ID_MINOR_REV_MASK (0xF00U) +#define I2S_ID_MINOR_REV_SHIFT (8U) +#define I2S_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK) +#define I2S_ID_MAJOR_REV_MASK (0xF000U) +#define I2S_ID_MAJOR_REV_SHIFT (12U) +#define I2S_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK) +#define I2S_ID_ID_MASK (0xFFFF0000U) +#define I2S_ID_ID_SHIFT (16U) +#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral I2S0 base address */ + #define I2S0_BASE (0x50086000u) + /** Peripheral I2S0 base address */ + #define I2S0_BASE_NS (0x40086000u) + /** Peripheral I2S0 base pointer */ + #define I2S0 ((I2S_Type *)I2S0_BASE) + /** Peripheral I2S0 base pointer */ + #define I2S0_NS ((I2S_Type *)I2S0_BASE_NS) + /** Peripheral I2S1 base address */ + #define I2S1_BASE (0x50087000u) + /** Peripheral I2S1 base address */ + #define I2S1_BASE_NS (0x40087000u) + /** Peripheral I2S1 base pointer */ + #define I2S1 ((I2S_Type *)I2S1_BASE) + /** Peripheral I2S1 base pointer */ + #define I2S1_NS ((I2S_Type *)I2S1_BASE_NS) + /** Peripheral I2S2 base address */ + #define I2S2_BASE (0x50088000u) + /** Peripheral I2S2 base address */ + #define I2S2_BASE_NS (0x40088000u) + /** Peripheral I2S2 base pointer */ + #define I2S2 ((I2S_Type *)I2S2_BASE) + /** Peripheral I2S2 base pointer */ + #define I2S2_NS ((I2S_Type *)I2S2_BASE_NS) + /** Peripheral I2S3 base address */ + #define I2S3_BASE (0x50089000u) + /** Peripheral I2S3 base address */ + #define I2S3_BASE_NS (0x40089000u) + /** Peripheral I2S3 base pointer */ + #define I2S3 ((I2S_Type *)I2S3_BASE) + /** Peripheral I2S3 base pointer */ + #define I2S3_NS ((I2S_Type *)I2S3_BASE_NS) + /** Peripheral I2S4 base address */ + #define I2S4_BASE (0x5008A000u) + /** Peripheral I2S4 base address */ + #define I2S4_BASE_NS (0x4008A000u) + /** Peripheral I2S4 base pointer */ + #define I2S4 ((I2S_Type *)I2S4_BASE) + /** Peripheral I2S4 base pointer */ + #define I2S4_NS ((I2S_Type *)I2S4_BASE_NS) + /** Peripheral I2S5 base address */ + #define I2S5_BASE (0x50096000u) + /** Peripheral I2S5 base address */ + #define I2S5_BASE_NS (0x40096000u) + /** Peripheral I2S5 base pointer */ + #define I2S5 ((I2S_Type *)I2S5_BASE) + /** Peripheral I2S5 base pointer */ + #define I2S5_NS ((I2S_Type *)I2S5_BASE_NS) + /** Peripheral I2S6 base address */ + #define I2S6_BASE (0x50097000u) + /** Peripheral I2S6 base address */ + #define I2S6_BASE_NS (0x40097000u) + /** Peripheral I2S6 base pointer */ + #define I2S6 ((I2S_Type *)I2S6_BASE) + /** Peripheral I2S6 base pointer */ + #define I2S6_NS ((I2S_Type *)I2S6_BASE_NS) + /** Peripheral I2S7 base address */ + #define I2S7_BASE (0x50098000u) + /** Peripheral I2S7 base address */ + #define I2S7_BASE_NS (0x40098000u) + /** Peripheral I2S7 base pointer */ + #define I2S7 ((I2S_Type *)I2S7_BASE) + /** Peripheral I2S7 base pointer */ + #define I2S7_NS ((I2S_Type *)I2S7_BASE_NS) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS_NS { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS_NS { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS } +#else + /** Peripheral I2S0 base address */ + #define I2S0_BASE (0x40086000u) + /** Peripheral I2S0 base pointer */ + #define I2S0 ((I2S_Type *)I2S0_BASE) + /** Peripheral I2S1 base address */ + #define I2S1_BASE (0x40087000u) + /** Peripheral I2S1 base pointer */ + #define I2S1 ((I2S_Type *)I2S1_BASE) + /** Peripheral I2S2 base address */ + #define I2S2_BASE (0x40088000u) + /** Peripheral I2S2 base pointer */ + #define I2S2 ((I2S_Type *)I2S2_BASE) + /** Peripheral I2S3 base address */ + #define I2S3_BASE (0x40089000u) + /** Peripheral I2S3 base pointer */ + #define I2S3 ((I2S_Type *)I2S3_BASE) + /** Peripheral I2S4 base address */ + #define I2S4_BASE (0x4008A000u) + /** Peripheral I2S4 base pointer */ + #define I2S4 ((I2S_Type *)I2S4_BASE) + /** Peripheral I2S5 base address */ + #define I2S5_BASE (0x40096000u) + /** Peripheral I2S5 base pointer */ + #define I2S5 ((I2S_Type *)I2S5_BASE) + /** Peripheral I2S6 base address */ + #define I2S6_BASE (0x40097000u) + /** Peripheral I2S6 base pointer */ + #define I2S6 ((I2S_Type *)I2S6_BASE) + /** Peripheral I2S7 base address */ + #define I2S7_BASE (0x40098000u) + /** Peripheral I2S7 base pointer */ + #define I2S7 ((I2S_Type *)I2S7_BASE) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } +#endif +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer + * @{ + */ + +/** INPUTMUX - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCT0_INMUX[7]; /**< Input mux register for SCT0 input, array offset: 0x0, array step: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t TIMER0CAPTSEL[4]; /**< Capture select registers for TIMER0 inputs, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[16]; + __IO uint32_t TIMER1CAPTSEL[4]; /**< Capture select registers for TIMER1 inputs, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_2[16]; + __IO uint32_t TIMER2CAPTSEL[4]; /**< Capture select registers for TIMER2 inputs, array offset: 0x60, array step: 0x4 */ + uint8_t RESERVED_3[80]; + __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DMA0_ITRIG_INMUX[23]; /**< Trigger select register for DMA0 channel, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_4[36]; + __IO uint32_t DMA0_OTRIG_INMUX[4]; /**< DMA0 output trigger selection to become DMA0 trigger, array offset: 0x160, array step: 0x4 */ + uint8_t RESERVED_5[16]; + __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ + __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ + uint8_t RESERVED_6[24]; + __IO uint32_t TIMER3CAPTSEL[4]; /**< Capture select registers for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */ + uint8_t RESERVED_7[16]; + __IO uint32_t TIMER4CAPTSEL[4]; /**< Capture select registers for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */ + uint8_t RESERVED_8[16]; + __IO uint32_t PINTSECSEL[2]; /**< Pin interrupt secure select register, array offset: 0x1E0, array step: 0x4 */ + uint8_t RESERVED_9[24]; + __IO uint32_t DMA1_ITRIG_INMUX[10]; /**< Trigger select register for DMA1 channel, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_10[24]; + __IO uint32_t DMA1_OTRIG_INMUX[4]; /**< DMA1 output trigger selection to become DMA1 trigger, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_11[1264]; + __IO uint32_t DMA0_REQ_ENA; /**< Enable DMA0 requests, offset: 0x740 */ + uint8_t RESERVED_12[4]; + __O uint32_t DMA0_REQ_ENA_SET; /**< Set one or several bits in DMA0_REQ_ENA register, offset: 0x748 */ + uint8_t RESERVED_13[4]; + __O uint32_t DMA0_REQ_ENA_CLR; /**< Clear one or several bits in DMA0_REQ_ENA register, offset: 0x750 */ + uint8_t RESERVED_14[12]; + __IO uint32_t DMA1_REQ_ENA; /**< Enable DMA1 requests, offset: 0x760 */ + uint8_t RESERVED_15[4]; + __O uint32_t DMA1_REQ_ENA_SET; /**< Set one or several bits in DMA1_REQ_ENA register, offset: 0x768 */ + uint8_t RESERVED_16[4]; + __O uint32_t DMA1_REQ_ENA_CLR; /**< Clear one or several bits in DMA1_REQ_ENA register, offset: 0x770 */ + uint8_t RESERVED_17[12]; + __IO uint32_t DMA0_ITRIG_ENA; /**< Enable DMA0 triggers, offset: 0x780 */ + uint8_t RESERVED_18[4]; + __O uint32_t DMA0_ITRIG_ENA_SET; /**< Set one or several bits in DMA0_ITRIG_ENA register, offset: 0x788 */ + uint8_t RESERVED_19[4]; + __O uint32_t DMA0_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA0_ITRIG_ENA register, offset: 0x790 */ + uint8_t RESERVED_20[12]; + __IO uint32_t DMA1_ITRIG_ENA; /**< Enable DMA1 triggers, offset: 0x7A0 */ + uint8_t RESERVED_21[4]; + __O uint32_t DMA1_ITRIG_ENA_SET; /**< Set one or several bits in DMA1_ITRIG_ENA register, offset: 0x7A8 */ + uint8_t RESERVED_22[4]; + __O uint32_t DMA1_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA1_ITRIG_ENA register, offset: 0x7B0 */ +} INPUTMUX_Type; + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks + * @{ + */ + +/*! @name SCT0_INMUX - Input mux register for SCT0 input */ +/*! @{ */ +#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU) +#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) +/*! INP_N - Input number to SCT0 inputs 0 to 6.. + * 0b00000..SCT_GPI0 function selected from IOCON register + * 0b00001..SCT_GPI1 function selected from IOCON register + * 0b00010..SCT_GPI2 function selected from IOCON register + * 0b00011..SCT_GPI3 function selected from IOCON register + * 0b00100..SCT_GPI4 function selected from IOCON register + * 0b00101..SCT_GPI5 function selected from IOCON register + * 0b00110..SCT_GPI6 function selected from IOCON register + * 0b00111..SCT_GPI7 function selected from IOCON register + * 0b01000..T0_OUT0 ctimer 0 match[0] output + * 0b01001..T1_OUT0 ctimer 1 match[0] output + * 0b01010..T2_OUT0 ctimer 2 match[0] output + * 0b01011..T3_OUT0 ctimer 3 match[0] output + * 0b01100..T4_OUT0 ctimer 4 match[0] output + * 0b01101..ADC_IRQ interrupt request from ADC + * 0b01110..GPIOINT_BMATCH + * 0b01111..USB0_FRAME_TOGGLE + * 0b10000..USB1_FRAME_TOGGLE + * 0b10001..COMP_OUTPUT output from analog comparator + * 0b10010..I2S_SHARED_SCK[0] output from I2S pin sharing + * 0b10011..I2S_SHARED_SCK[1] output from I2S pin sharing + * 0b10100..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b10101..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b10110..ARM_TXEV interrupt event from cpu0 or cpu1 + * 0b10111..DEBUG_HALTED from cpu0 or cpu1 + * 0b11000-0b11111..None + */ +#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK) +/*! @} */ + +/* The count of INPUTMUX_SCT0_INMUX */ +#define INPUTMUX_SCT0_INMUX_COUNT (7U) + +/*! @name TIMER0CAPTSEL - Capture select registers for TIMER0 inputs */ +/*! @{ */ +#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER0CAPTSEL */ +#define INPUTMUX_TIMER0CAPTSEL_COUNT (4U) + +/*! @name TIMER1CAPTSEL - Capture select registers for TIMER1 inputs */ +/*! @{ */ +#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER1CAPTSEL */ +#define INPUTMUX_TIMER1CAPTSEL_COUNT (4U) + +/*! @name TIMER2CAPTSEL - Capture select registers for TIMER2 inputs */ +/*! @{ */ +#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER2CAPTSEL */ +#define INPUTMUX_TIMER2CAPTSEL_COUNT (4U) + +/*! @name PINTSEL - Pin interrupt select register */ +/*! @{ */ +#define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU) +#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) +#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PINTSEL */ +#define INPUTMUX_PINTSEL_COUNT (8U) + +/*! @name DMA0_ITRIG_INMUX - Trigger select register for DMA0 channel */ +/*! @{ */ +#define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U) +/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22). + * 0b00000..Pin interrupt 0 + * 0b00001..Pin interrupt 1 + * 0b00010..Pin interrupt 2 + * 0b00011..Pin interrupt 3 + * 0b00100..Timer CTIMER0 Match 0 + * 0b00101..Timer CTIMER0 Match 1 + * 0b00110..Timer CTIMER1 Match 0 + * 0b00111..Timer CTIMER1 Match 1 + * 0b01000..Timer CTIMER2 Match 0 + * 0b01001..Timer CTIMER2 Match 1 + * 0b01010..Timer CTIMER3 Match 0 + * 0b01011..Timer CTIMER3 Match 1 + * 0b01100..Timer CTIMER4 Match 0 + * 0b01101..Timer CTIMER4 Match 1 + * 0b01110..COMP_OUTPUT + * 0b01111..DMA0 output trigger mux 0 + * 0b10000..DMA0 output trigger mux 1 + * 0b10001..DMA0 output trigger mux 1 + * 0b10010..DMA0 output trigger mux 3 + * 0b10011..SCT0 DMA request 0 + * 0b10100..SCT0 DMA request 1 + * 0b10101..HASH DMA RX trigger + * 0b10110-0b11111..None + */ +#define INPUTMUX_DMA0_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA0_ITRIG_INMUX */ +#define INPUTMUX_DMA0_ITRIG_INMUX_COUNT (23U) + +/*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection to become DMA0 trigger */ +/*! @{ */ +#define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U) +#define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA0_OTRIG_INMUX */ +#define INPUTMUX_DMA0_OTRIG_INMUX_COUNT (4U) + +/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ +/*! @{ */ +#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) +#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) +/*! @} */ + +/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ +/*! @{ */ +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) +#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) +/*! @} */ + +/*! @name TIMER3CAPTSEL - Capture select registers for TIMER3 inputs */ +/*! @{ */ +#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..CT_INP17 function selected from IOCON register + * 0b10010..CT_INP18 function selected from IOCON register + * 0b10011..CT_INP19 function selected from IOCON register + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER3CAPTSEL */ +#define INPUTMUX_TIMER3CAPTSEL_COUNT (4U) + +/*! @name TIMER4CAPTSEL - Capture select registers for TIMER4 inputs */ +/*! @{ */ +#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..CT_INP17 function selected from IOCON register + * 0b10010..CT_INP18 function selected from IOCON register + * 0b10011..CT_INP19 function selected from IOCON register + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER4CAPTSEL */ +#define INPUTMUX_TIMER4CAPTSEL_COUNT (4U) + +/*! @name PINTSECSEL - Pin interrupt secure select register */ +/*! @{ */ +#define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU) +#define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U) +#define INPUTMUX_PINTSECSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PINTSECSEL */ +#define INPUTMUX_PINTSECSEL_COUNT (2U) + +/*! @name DMA1_ITRIG_INMUX - Trigger select register for DMA1 channel */ +/*! @{ */ +#define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0xFU) +#define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U) +/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9). + * 0b0000..Pin interrupt 0 + * 0b0001..Pin interrupt 1 + * 0b0010..Pin interrupt 2 + * 0b0011..Pin interrupt 3 + * 0b0100..Timer CTIMER0 Match 0 + * 0b0101..Timer CTIMER0 Match 1 + * 0b0110..Timer CTIMER2 Match 0 + * 0b0111..Timer CTIMER4 Match 0 + * 0b1000..DMA1 output trigger mux 0 + * 0b1001..DMA1 output trigger mux 1 + * 0b1010..DMA1 output trigger mux 2 + * 0b1011..DMA1 output trigger mux 3 + * 0b1100..SCT0 DMA request 0 + * 0b1101..SCT0 DMA request 1 + * 0b1110..HASH DMA RX trigger + * 0b1111..None + */ +#define INPUTMUX_DMA1_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA1_ITRIG_INMUX */ +#define INPUTMUX_DMA1_ITRIG_INMUX_COUNT (10U) + +/*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection to become DMA1 trigger */ +/*! @{ */ +#define INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK (0xFU) +#define INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT (0U) +#define INPUTMUX_DMA1_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA1_OTRIG_INMUX */ +#define INPUTMUX_DMA1_OTRIG_INMUX_COUNT (4U) + +/*! @name DMA0_REQ_ENA - Enable DMA0 requests */ +/*! @{ */ +#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK (0x7FFFFFU) +#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT (0U) +#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK (0x7FFFFFU) +#define INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT (0U) +#define INPUTMUX_DMA0_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK (0x7FFFFFU) +#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT (0U) +#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENA - Enable DMA1 requests */ +/*! @{ */ +#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK (0x3FFU) +#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT (0U) +#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK (0x3FFU) +#define INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT (0U) +#define INPUTMUX_DMA1_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK (0x3FFU) +#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT (0U) +#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_ENA - Enable DMA0 triggers */ +/*! @{ */ +#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK (0x3FFFFFU) +#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) +#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK (0x3FFFFFU) +#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT (0U) +#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK (0x3FFFFFU) +#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT (0U) +#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_ENA - Enable DMA1 triggers */ +/*! @{ */ +#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK (0x7FFFU) +#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) +#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK (0x7FFFU) +#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT (0U) +#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register */ +/*! @{ */ +#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK (0x7FFFU) +#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT (0U) +#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group INPUTMUX_Register_Masks */ + + +/* INPUTMUX - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE (0x50006000u) + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX_NS } +#else + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE (0x40006000u) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX } +#endif + +/*! + * @} + */ /* end of group INPUTMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer + * @{ + */ + +/** IOCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ +} IOCON_Type; + +/* ---------------------------------------------------------------------------- + -- IOCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Register_Masks IOCON Register Masks + * @{ + */ + +/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ +/*! @{ */ +#define IOCON_PIO_FUNC_MASK (0xFU) +#define IOCON_PIO_FUNC_SHIFT (0U) +/*! FUNC - Selects pin function. + * 0b0000..Alternative connection 0. + * 0b0001..Alternative connection 1. + * 0b0010..Alternative connection 2. + * 0b0011..Alternative connection 3. + * 0b0100..Alternative connection 4. + * 0b0101..Alternative connection 5. + * 0b0110..Alternative connection 6. + * 0b0111..Alternative connection 7. + */ +#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) +#define IOCON_PIO_MODE_MASK (0x30U) +#define IOCON_PIO_MODE_SHIFT (4U) +/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). + * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). + * 0b01..Pull-down. Pull-down resistor enabled. + * 0b10..Pull-up. Pull-up resistor enabled. + * 0b11..Repeater. Repeater mode. + */ +#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) +#define IOCON_PIO_SLEW_MASK (0x40U) +#define IOCON_PIO_SLEW_SHIFT (6U) +/*! SLEW - Driver slew rate. + * 0b0..Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + * 0b1..Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + */ +#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) +#define IOCON_PIO_INVERT_MASK (0x80U) +#define IOCON_PIO_INVERT_SHIFT (7U) +/*! INVERT - Input polarity. + * 0b0..Disabled. Input function is not inverted. + * 0b1..Enabled. Input is function inverted. + */ +#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) +#define IOCON_PIO_DIGIMODE_MASK (0x100U) +#define IOCON_PIO_DIGIMODE_SHIFT (8U) +/*! DIGIMODE - Select Digital mode. + * 0b0..Disable digital mode. Digital input set to 0. + * 0b1..Enable Digital mode. Digital input is enabled. + */ +#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) +#define IOCON_PIO_OD_MASK (0x200U) +#define IOCON_PIO_OD_SHIFT (9U) +/*! OD - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). + * 0b0..Normal. Normal push-pull output + * 0b1..Open-drain. Simulated open-drain output (high drive disabled). + */ +#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) +#define IOCON_PIO_ASW_MASK (0x400U) +#define IOCON_PIO_ASW_SHIFT (10U) +/*! ASW - Analog switch input control. + * 0b0..For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed + * (enabled). For the other pins, analog switch is open (disabled). + * 0b1..For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) + */ +#define IOCON_PIO_ASW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW_SHIFT)) & IOCON_PIO_ASW_MASK) +#define IOCON_PIO_SSEL_MASK (0x800U) +#define IOCON_PIO_SSEL_SHIFT (11U) +/*! SSEL - Supply Selection bit. + * 0b0..3V3 Signaling in I2C Mode. + * 0b1..1V8 Signaling in I2C Mode. + */ +#define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK) +#define IOCON_PIO_FILTEROFF_MASK (0x1000U) +#define IOCON_PIO_FILTEROFF_SHIFT (12U) +/*! FILTEROFF - Controls input glitch filter. + * 0b0..Filter enabled. + * 0b1..Filter disabled. + */ +#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) +#define IOCON_PIO_ECS_MASK (0x2000U) +#define IOCON_PIO_ECS_SHIFT (13U) +/*! ECS - Pull-up current source enable in I2C mode. + * 0b1..Enabled. Pull resistor is conencted. + * 0b0..Disabled. IO is in open drain cell. + */ +#define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK) +#define IOCON_PIO_EGP_MASK (0x4000U) +#define IOCON_PIO_EGP_SHIFT (14U) +/*! EGP - Switch between GPIO mode and I2C mode. + * 0b0..I2C mode. + * 0b1..GPIO mode. + */ +#define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK) +#define IOCON_PIO_I2CFILTER_MASK (0x8000U) +#define IOCON_PIO_I2CFILTER_SHIFT (15U) +/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. + * 0b0..I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. + * 0b1..I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. + */ +#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) +/*! @} */ + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT (2U) + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT2 (32U) + + +/*! + * @} + */ /* end of group IOCON_Register_Masks */ + + +/* IOCON - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral IOCON base address */ + #define IOCON_BASE (0x50001000u) + /** Peripheral IOCON base address */ + #define IOCON_BASE_NS (0x40001000u) + /** Peripheral IOCON base pointer */ + #define IOCON ((IOCON_Type *)IOCON_BASE) + /** Peripheral IOCON base pointer */ + #define IOCON_NS ((IOCON_Type *)IOCON_BASE_NS) + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS { IOCON_BASE } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS { IOCON } + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS_NS { IOCON_BASE_NS } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS_NS { IOCON_NS } +#else + /** Peripheral IOCON base address */ + #define IOCON_BASE (0x40001000u) + /** Peripheral IOCON base pointer */ + #define IOCON ((IOCON_Type *)IOCON_BASE) + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS { IOCON_BASE } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS { IOCON } +#endif + +/*! + * @} + */ /* end of group IOCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MAILBOX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer + * @{ + */ + +/** MAILBOX - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */ + __O uint32_t IRQSET; /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */ + __O uint32_t IRQCLR; /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } MBOXIRQ[2]; + uint8_t RESERVED_0[216]; + __IO uint32_t MUTEX; /**< Mutual exclusion register[1], offset: 0xF8 */ +} MAILBOX_Type; + +/* ---------------------------------------------------------------------------- + -- MAILBOX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks + * @{ + */ + +/*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */ +/*! @{ */ +#define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U) +#define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQ */ +#define MAILBOX_MBOXIRQ_IRQ_COUNT (2U) + +/*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */ +/*! @{ */ +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U) +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQSET */ +#define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U) + +/*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */ +/*! @{ */ +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U) +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQCLR */ +#define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U) + +/*! @name MUTEX - Mutual exclusion register[1] */ +/*! @{ */ +#define MAILBOX_MUTEX_EX_MASK (0x1U) +#define MAILBOX_MUTEX_EX_SHIFT (0U) +#define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MAILBOX_Register_Masks */ + + +/* MAILBOX - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x5008B000u) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE_NS (0x4008B000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } +#else + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x4008B000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } +#endif +/** Interrupt vectors for the MAILBOX peripheral type */ +#define MAILBOX_IRQS { MAILBOX_IRQn } + +/*! + * @} + */ /* end of group MAILBOX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MRT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer + * @{ + */ + +/** MRT - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ + __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ + __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ + __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ + } CHANNEL[4]; + uint8_t RESERVED_0[176]; + __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ + __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ + __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ +} MRT_Type; + +/* ---------------------------------------------------------------------------- + -- MRT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Register_Masks MRT Register Masks + * @{ + */ + +/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ +/*! @{ */ +#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) +#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) +#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) +#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) +/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. + * This bit is write-only. Reading this bit always returns 0. + * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the + * time interval if the repeat mode is selected. + * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. + */ +#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_INTVAL */ +#define MRT_CHANNEL_INTVAL_COUNT (4U) + +/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ +/*! @{ */ +#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) +#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_TIMER */ +#define MRT_CHANNEL_TIMER_COUNT (4U) + +/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ +/*! @{ */ +#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) +#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) +/*! INTEN - Enable the TIMERn interrupt. + * 0b0..Disabled. TIMERn interrupt is disabled. + * 0b1..Enabled. TIMERn interrupt is enabled. + */ +#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) +#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) +#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) +/*! MODE - Selects timer mode. + * 0b00..Repeat interrupt mode. + * 0b01..One-shot interrupt mode. + * 0b10..One-shot stall mode. + * 0b11..Reserved. + */ +#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_CTRL */ +#define MRT_CHANNEL_CTRL_COUNT (4U) + +/*! @name CHANNEL_STAT - MRT Status register. */ +/*! @{ */ +#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) +#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) +/*! INTFLAG - Monitors the interrupt flag. + * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. + * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If + * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt + * are raised. Writing a 1 to this bit clears the interrupt request. + */ +#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) +#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) +#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) +/*! RUN - Indicates the state of TIMERn. This bit is read-only. + * 0b0..Idle state. TIMERn is stopped. + * 0b1..Running. TIMERn is running. + */ +#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) +#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) +#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) +/*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG + * register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating + * modes. + * 0b0..This channel is not in use. + * 0b1..This channel is in use. + */ +#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_STAT */ +#define MRT_CHANNEL_STAT_COUNT (4U) + +/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ +/*! @{ */ +#define MRT_MODCFG_NOC_MASK (0xFU) +#define MRT_MODCFG_NOC_SHIFT (0U) +#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) +#define MRT_MODCFG_NOB_MASK (0x1F0U) +#define MRT_MODCFG_NOB_SHIFT (4U) +#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) +#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) +#define MRT_MODCFG_MULTITASK_SHIFT (31U) +/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. + * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. + * 0b1..Multi-task mode. + */ +#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) +/*! @} */ + +/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ +/*! @{ */ +#define MRT_IDLE_CH_CHAN_MASK (0xF0U) +#define MRT_IDLE_CH_CHAN_SHIFT (4U) +#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) +/*! @} */ + +/*! @name IRQ_FLAG - Global interrupt flag register */ +/*! @{ */ +#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) +#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) +/*! GFLAG0 - Monitors the interrupt flag of TIMER0. + * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. + * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If + * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global + * interrupt are raised. Writing a 1 to this bit clears the interrupt request. + */ +#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) +#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) +#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) +#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) +#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) +#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) +#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) +#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) +#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) +#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MRT_Register_Masks */ + + +/* MRT - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x5000D000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x4000D000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x4000D000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/*! + * @} + */ /* end of group MRT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OSTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer + * @{ + */ + +/** OSTIMER - Register Layout Typedef */ +typedef struct { + __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */ + __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */ + __I uint32_t CAPTUREN_L; /**< Local Capture Low Register for CPUn, offset: 0x8 */ + __I uint32_t CAPTUREN_H; /**< Local Capture High Register for CPUn, offset: 0xC */ + __IO uint32_t MATCHN_L; /**< Local Match Low Register for CPUn, offset: 0x10 */ + __IO uint32_t MATCHN_H; /**< Match High Register for CPUn, offset: 0x14 */ + uint8_t RESERVED_0[4]; + __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register for CPUn, offset: 0x1C */ +} OSTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- OSTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks + * @{ + */ + +/*! @name EVTIMERL - EVTIMER Low Register */ +/*! @{ */ +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name EVTIMERH - EVTIMER High Register */ +/*! @{ */ +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU) +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name CAPTUREN_L - Local Capture Low Register for CPUn */ +/*! @{ */ +#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_SHIFT (0U) +#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_SHIFT)) & OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_MASK) +/*! @} */ + +/*! @name CAPTUREN_H - Local Capture High Register for CPUn */ +/*! @{ */ +#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_MASK (0x3FFU) +#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_SHIFT (0U) +#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_SHIFT)) & OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_MASK) +/*! @} */ + +/*! @name MATCHN_L - Local Match Low Register for CPUn */ +/*! @{ */ +#define OSTIMER_MATCHN_L_MATCHn_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_MATCHN_L_MATCHn_VALUE_SHIFT (0U) +#define OSTIMER_MATCHN_L_MATCHn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCHN_L_MATCHn_VALUE_SHIFT)) & OSTIMER_MATCHN_L_MATCHn_VALUE_MASK) +/*! @} */ + +/*! @name MATCHN_H - Match High Register for CPUn */ +/*! @{ */ +#define OSTIMER_MATCHN_H_MATCHn_VALUE_MASK (0x3FFU) +#define OSTIMER_MATCHN_H_MATCHn_VALUE_SHIFT (0U) +#define OSTIMER_MATCHN_H_MATCHn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCHN_H_MATCHn_VALUE_SHIFT)) & OSTIMER_MATCHN_H_MATCHn_VALUE_MASK) +/*! @} */ + +/*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register for CPUn */ +/*! @{ */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OSTIMER_Register_Masks */ + + +/* OSTIMER - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE (0x5002D000u) + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE_NS (0x4002D000u) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER_NS ((OSTIMER_Type *)OSTIMER_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER_NS } +#else + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE (0x4002D000u) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/*! + * @} + */ /* end of group OSTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer + * @{ + */ + +/** PINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ + __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ + __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ + __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ + __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ + __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ + __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ + __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ + __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ + __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ + __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ + __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ + __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ +} PINT_Type; + +/* ---------------------------------------------------------------------------- + -- PINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Register_Masks PINT Register Masks + * @{ + */ + +/*! @name ISEL - Pin Interrupt Mode register */ +/*! @{ */ +#define PINT_ISEL_PMODE_MASK (0xFFU) +#define PINT_ISEL_PMODE_SHIFT (0U) +#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) +/*! @} */ + +/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ +/*! @{ */ +#define PINT_IENR_ENRL_MASK (0xFFU) +#define PINT_IENR_ENRL_SHIFT (0U) +#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) +/*! @} */ + +/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ +/*! @{ */ +#define PINT_SIENR_SETENRL_MASK (0xFFU) +#define PINT_SIENR_SETENRL_SHIFT (0U) +#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) +/*! @} */ + +/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ +/*! @{ */ +#define PINT_CIENR_CENRL_MASK (0xFFU) +#define PINT_CIENR_CENRL_SHIFT (0U) +#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) +/*! @} */ + +/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ +/*! @{ */ +#define PINT_IENF_ENAF_MASK (0xFFU) +#define PINT_IENF_ENAF_SHIFT (0U) +#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) +/*! @} */ + +/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ +/*! @{ */ +#define PINT_SIENF_SETENAF_MASK (0xFFU) +#define PINT_SIENF_SETENAF_SHIFT (0U) +#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) +/*! @} */ + +/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ +/*! @{ */ +#define PINT_CIENF_CENAF_MASK (0xFFU) +#define PINT_CIENF_CENAF_SHIFT (0U) +#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) +/*! @} */ + +/*! @name RISE - Pin interrupt rising edge register */ +/*! @{ */ +#define PINT_RISE_RDET_MASK (0xFFU) +#define PINT_RISE_RDET_SHIFT (0U) +#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) +/*! @} */ + +/*! @name FALL - Pin interrupt falling edge register */ +/*! @{ */ +#define PINT_FALL_FDET_MASK (0xFFU) +#define PINT_FALL_FDET_SHIFT (0U) +#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) +/*! @} */ + +/*! @name IST - Pin interrupt status register */ +/*! @{ */ +#define PINT_IST_PSTAT_MASK (0xFFU) +#define PINT_IST_PSTAT_SHIFT (0U) +#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) +/*! @} */ + +/*! @name PMCTRL - Pattern match interrupt control register */ +/*! @{ */ +#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) +#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) +/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. + * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. + * 0b1..Pattern match. Interrupts are driven in response to pattern matches. + */ +#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) +#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) +#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) +/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. + * 0b0..Disabled. RXEV output to the CPU is disabled. + * 0b1..Enabled. RXEV output to the CPU is enabled. + */ +#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) +#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) +#define PINT_PMCTRL_PMAT_SHIFT (24U) +#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) +/*! @} */ + +/*! @name PMSRC - Pattern match interrupt bit-slice source register */ +/*! @{ */ +#define PINT_PMSRC_SRC0_MASK (0x700U) +#define PINT_PMSRC_SRC0_SHIFT (8U) +/*! SRC0 - Selects the input source for bit slice 0 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. + */ +#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) +#define PINT_PMSRC_SRC1_MASK (0x3800U) +#define PINT_PMSRC_SRC1_SHIFT (11U) +/*! SRC1 - Selects the input source for bit slice 1 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. + */ +#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) +#define PINT_PMSRC_SRC2_MASK (0x1C000U) +#define PINT_PMSRC_SRC2_SHIFT (14U) +/*! SRC2 - Selects the input source for bit slice 2 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. + */ +#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) +#define PINT_PMSRC_SRC3_MASK (0xE0000U) +#define PINT_PMSRC_SRC3_SHIFT (17U) +/*! SRC3 - Selects the input source for bit slice 3 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. + */ +#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) +#define PINT_PMSRC_SRC4_MASK (0x700000U) +#define PINT_PMSRC_SRC4_SHIFT (20U) +/*! SRC4 - Selects the input source for bit slice 4 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. + */ +#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) +#define PINT_PMSRC_SRC5_MASK (0x3800000U) +#define PINT_PMSRC_SRC5_SHIFT (23U) +/*! SRC5 - Selects the input source for bit slice 5 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. + */ +#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) +#define PINT_PMSRC_SRC6_MASK (0x1C000000U) +#define PINT_PMSRC_SRC6_SHIFT (26U) +/*! SRC6 - Selects the input source for bit slice 6 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. + */ +#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) +#define PINT_PMSRC_SRC7_MASK (0xE0000000U) +#define PINT_PMSRC_SRC7_SHIFT (29U) +/*! SRC7 - Selects the input source for bit slice 7 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. + */ +#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) +/*! @} */ + +/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ +/*! @{ */ +#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) +#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) +/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. + * 0b0..No effect. Slice 0 is not an endpoint. + * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) +#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) +#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) +/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. + * 0b0..No effect. Slice 1 is not an endpoint. + * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) +#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) +#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) +/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. + * 0b0..No effect. Slice 2 is not an endpoint. + * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) +#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) +#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) +/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. + * 0b0..No effect. Slice 3 is not an endpoint. + * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) +#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) +#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) +/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. + * 0b0..No effect. Slice 4 is not an endpoint. + * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) +#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) +#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) +/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. + * 0b0..No effect. Slice 5 is not an endpoint. + * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) +#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) +#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) +/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. + * 0b0..No effect. Slice 6 is not an endpoint. + * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) +#define PINT_PMCFG_CFG0_MASK (0x700U) +#define PINT_PMCFG_CFG0_SHIFT (8U) +/*! CFG0 - Specifies the match contribution condition for bit slice 0. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) +#define PINT_PMCFG_CFG1_MASK (0x3800U) +#define PINT_PMCFG_CFG1_SHIFT (11U) +/*! CFG1 - Specifies the match contribution condition for bit slice 1. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) +#define PINT_PMCFG_CFG2_MASK (0x1C000U) +#define PINT_PMCFG_CFG2_SHIFT (14U) +/*! CFG2 - Specifies the match contribution condition for bit slice 2. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) +#define PINT_PMCFG_CFG3_MASK (0xE0000U) +#define PINT_PMCFG_CFG3_SHIFT (17U) +/*! CFG3 - Specifies the match contribution condition for bit slice 3. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) +#define PINT_PMCFG_CFG4_MASK (0x700000U) +#define PINT_PMCFG_CFG4_SHIFT (20U) +/*! CFG4 - Specifies the match contribution condition for bit slice 4. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) +#define PINT_PMCFG_CFG5_MASK (0x3800000U) +#define PINT_PMCFG_CFG5_SHIFT (23U) +/*! CFG5 - Specifies the match contribution condition for bit slice 5. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) +#define PINT_PMCFG_CFG6_MASK (0x1C000000U) +#define PINT_PMCFG_CFG6_SHIFT (26U) +/*! CFG6 - Specifies the match contribution condition for bit slice 6. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) +#define PINT_PMCFG_CFG7_MASK (0xE0000000U) +#define PINT_PMCFG_CFG7_SHIFT (29U) +/*! CFG7 - Specifies the match contribution condition for bit slice 7. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PINT_Register_Masks */ + + +/* PINT - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral PINT base address */ + #define PINT_BASE (0x50004000u) + /** Peripheral PINT base address */ + #define PINT_BASE_NS (0x40004000u) + /** Peripheral PINT base pointer */ + #define PINT ((PINT_Type *)PINT_BASE) + /** Peripheral PINT base pointer */ + #define PINT_NS ((PINT_Type *)PINT_BASE_NS) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE (0x50005000u) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE_NS (0x40005000u) + /** Peripheral SECPINT base pointer */ + #define SECPINT ((PINT_Type *)SECPINT_BASE) + /** Peripheral SECPINT base pointer */ + #define SECPINT_NS ((PINT_Type *)SECPINT_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT, SECPINT } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT_BASE_NS, SECPINT_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT_NS, SECPINT_NS } +#else + /** Peripheral PINT base address */ + #define PINT_BASE (0x40004000u) + /** Peripheral PINT base pointer */ + #define PINT ((PINT_Type *)PINT_BASE) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE (0x40005000u) + /** Peripheral SECPINT base pointer */ + #define SECPINT ((PINT_Type *)SECPINT_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT, SECPINT } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn } + +/*! + * @} + */ /* end of group PINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PLU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PLU_Peripheral_Access_Layer PLU Peripheral Access Layer + * @{ + */ + +/** PLU - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x20 */ + __IO uint32_t INP_MUX[5]; /**< LUTn input x MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */ + uint8_t RESERVED_0[12]; + } LUT[26]; + uint8_t RESERVED_0[1216]; + __IO uint32_t LUT_TRUTH[26]; /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25, array offset: 0x800, array step: 0x4 */ + uint8_t RESERVED_1[152]; + __I uint32_t OUTPUTS; /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */ + __IO uint32_t WAKEINT_CTRL; /**< Wakeup interrupt control for PLU, offset: 0x904 */ + uint8_t RESERVED_2[760]; + __IO uint32_t OUTPUT_MUX[8]; /**< Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */ +} PLU_Type; + +/* ---------------------------------------------------------------------------- + -- PLU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PLU_Register_Masks PLU Register Masks + * @{ + */ + +/*! @name LUT_INP_MUX - LUTn input x MUX */ +/*! @{ */ +#define PLU_LUT_INP_MUX_LUTn_INPx_MASK (0x3FU) +#define PLU_LUT_INP_MUX_LUTn_INPx_SHIFT (0U) +/*! LUTn_INPx - Selects the input source to be connected to LUT25 input4. For each LUT, the slot + * associated with the output from LUTn itself is tied low. + * 0b000000..The PLU primary inputs 0. + * 0b000001..The PLU primary inputs 1. + * 0b000010..The PLU primary inputs 2. + * 0b000011..The PLU primary inputs 3. + * 0b000100..The PLU primary inputs 4. + * 0b000101..The PLU primary inputs 5. + * 0b000110..The output of LUT0. + * 0b000111..The output of LUT1. + * 0b001000..The output of LUT2. + * 0b001001..The output of LUT3. + * 0b001010..The output of LUT4. + * 0b001011..The output of LUT5. + * 0b001100..The output of LUT6. + * 0b001101..The output of LUT7. + * 0b001110..The output of LUT8. + * 0b001111..The output of LUT9. + * 0b010000..The output of LUT10. + * 0b010001..The output of LUT11. + * 0b010010..The output of LUT12. + * 0b010011..The output of LUT13. + * 0b010100..The output of LUT14. + * 0b010101..The output of LUT15. + * 0b010110..The output of LUT16. + * 0b010111..The output of LUT17. + * 0b011000..The output of LUT18. + * 0b011001..The output of LUT19. + * 0b011010..The output of LUT20. + * 0b011011..The output of LUT21. + * 0b011100..The output of LUT22. + * 0b011101..The output of LUT23. + * 0b011110..The output of LUT24. + * 0b011111..The output of LUT25. + * 0b100000..state(0). + * 0b100001..state(1). + * 0b100010..state(2). + * 0b100011..state(3). + */ +#define PLU_LUT_INP_MUX_LUTn_INPx(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_MUX_LUTn_INPx_SHIFT)) & PLU_LUT_INP_MUX_LUTn_INPx_MASK) +/*! @} */ + +/* The count of PLU_LUT_INP_MUX */ +#define PLU_LUT_INP_MUX_COUNT (26U) + +/* The count of PLU_LUT_INP_MUX */ +#define PLU_LUT_INP_MUX_COUNT2 (5U) + +/*! @name LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */ +/*! @{ */ +#define PLU_LUT_TRUTH_LUTn_TRUTH_MASK (0xFFFFFFFFU) +#define PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT (0U) +#define PLU_LUT_TRUTH_LUTn_TRUTH(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT)) & PLU_LUT_TRUTH_LUTn_TRUTH_MASK) +/*! @} */ + +/* The count of PLU_LUT_TRUTH */ +#define PLU_LUT_TRUTH_COUNT (26U) + +/*! @name OUTPUTS - Provides the current state of the 8 designated PLU Outputs. */ +/*! @{ */ +#define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU) +#define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U) +#define PLU_OUTPUTS_OUTPUT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK) +/*! @} */ + +/*! @name WAKEINT_CTRL - Wakeup interrupt control for PLU */ +/*! @{ */ +#define PLU_WAKEINT_CTRL_MASK_MASK (0xFFU) +#define PLU_WAKEINT_CTRL_MASK_SHIFT (0U) +#define PLU_WAKEINT_CTRL_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_MASK_SHIFT)) & PLU_WAKEINT_CTRL_MASK_MASK) +#define PLU_WAKEINT_CTRL_FILTER_MODE_MASK (0x300U) +#define PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT (8U) +/*! FILTER_MODE - control input of the PLU, add filtering for glitch. + * 0b00..Bypass mode. + * 0b01..Filter 1 clock period. + * 0b10..Filter 2 clock period. + * 0b11..Filter 3 clock period. + */ +#define PLU_WAKEINT_CTRL_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_MODE_MASK) +#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK (0xC00U) +#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT (10U) +/*! FILTER_CLKSEL - hclk is divided by 2**filter_clksel. + * 0b00..Selects the 1 MHz low-power oscillator as the filter clock. + * 0b01..Selects the 12 Mhz FRO as the filter clock. + * 0b10..Selects a third filter clock source, if provided. + * 0b11..Reserved. + */ +#define PLU_WAKEINT_CTRL_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK) +#define PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK (0x1000U) +#define PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT (12U) +#define PLU_WAKEINT_CTRL_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK) +#define PLU_WAKEINT_CTRL_INTR_CLEAR_MASK (0x2000U) +#define PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT (13U) +#define PLU_WAKEINT_CTRL_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK) +/*! @} */ + +/*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7 */ +/*! @{ */ +#define PLU_OUTPUT_MUX_OUTPUTn_MASK (0x1FU) +#define PLU_OUTPUT_MUX_OUTPUTn_SHIFT (0U) +/*! OUTPUTn - Selects the source to be connected to PLU Output 7. + * 0b00000..The PLU output 0. + * 0b00001..The PLU output 1. + * 0b00010..The PLU output 2. + * 0b00011..The PLU output 3. + * 0b00100..The PLU output 4. + * 0b00101..The PLU output 5. + * 0b00110..The PLU output 6. + * 0b00111..The PLU output 7. + * 0b01000..The PLU output 8. + * 0b01001..The PLU output 9. + * 0b01010..The PLU output 10. + * 0b01011..The PLU output 11. + * 0b01100..The PLU output 12. + * 0b01101..The PLU output 13. + * 0b01110..The PLU output 14. + * 0b01111..The PLU output 15. + * 0b10000..The PLU output 16. + * 0b10001..The PLU output 17. + * 0b10010..The PLU output 18. + * 0b10011..The PLU output 19. + * 0b10100..The PLU output 20. + * 0b10101..The PLU output 21. + * 0b10110..The PLU output 22. + * 0b10111..The PLU output 23. + * 0b11000..The PLU output 24. + * 0b11001..The PLU output 25. + * 0b11010..state(0). + * 0b11011..state(1). + * 0b11100..state(2). + * 0b11101..state(3). + */ +#define PLU_OUTPUT_MUX_OUTPUTn(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUTn_SHIFT)) & PLU_OUTPUT_MUX_OUTPUTn_MASK) +/*! @} */ + +/* The count of PLU_OUTPUT_MUX */ +#define PLU_OUTPUT_MUX_COUNT (8U) + + +/*! + * @} + */ /* end of group PLU_Register_Masks */ + + +/* PLU - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral PLU base address */ + #define PLU_BASE (0x5003D000u) + /** Peripheral PLU base address */ + #define PLU_BASE_NS (0x4003D000u) + /** Peripheral PLU base pointer */ + #define PLU ((PLU_Type *)PLU_BASE) + /** Peripheral PLU base pointer */ + #define PLU_NS ((PLU_Type *)PLU_BASE_NS) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU } + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS_NS { PLU_BASE_NS } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS_NS { PLU_NS } +#else + /** Peripheral PLU base address */ + #define PLU_BASE (0x4003D000u) + /** Peripheral PLU base pointer */ + #define PLU ((PLU_Type *)PLU_BASE) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU } +#endif + +/*! + * @} + */ /* end of group PLU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer + * @{ + */ + +/** PMC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[8]; + __IO uint32_t RESETCTRL; /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x8 */ + uint8_t RESERVED_1[36]; + __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */ + uint8_t RESERVED_2[28]; + __IO uint32_t COMP; /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x50 */ + uint8_t RESERVED_3[20]; + __IO uint32_t WAKEIOCAUSE; /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */ + uint8_t RESERVED_4[8]; + __IO uint32_t STATUSCLK; /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */ + uint8_t RESERVED_5[12]; + __IO uint32_t AOREG1; /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset], offset: 0x84 */ + uint8_t RESERVED_6[16]; + __IO uint32_t RTCOSC32K; /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x98 */ + __IO uint32_t OSTIMERr; /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C */ + uint8_t RESERVED_7[24]; + __IO uint32_t PDRUNCFG0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */ + uint8_t RESERVED_8[4]; + __O uint32_t PDRUNCFGSET0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */ + uint8_t RESERVED_9[4]; + __O uint32_t PDRUNCFGCLR0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */ +} PMC_Type; + +/* ---------------------------------------------------------------------------- + -- PMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Register_Masks PMC Register Masks + * @{ + */ + +/*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U) +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U) +/*! DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). + * 0b0..Reset event from DEEP POWER DOWN mode is disable. + * 0b1..Reset event from DEEP POWER DOWN mode is enable. + */ +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK) +#define PMC_RESETCTRL_BODVBATRESETENABLE_MASK (0x2U) +#define PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT (1U) +/*! BODVBATRESETENABLE - BOD VBAT reset enable. + * 0b0..BOD VBAT reset is disable. + * 0b1..BOD VBAT reset is enable. + */ +#define PMC_RESETCTRL_BODVBATRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENABLE_MASK) +#define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U) +#define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U) +/*! SWRRESETENABLE - Software reset enable. + * 0b0..Software reset is disable. + * 0b1..Software reset is enable. + */ +#define PMC_RESETCTRL_SWRRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK) +/*! @} */ + +/*! @name BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] */ +/*! @{ */ +#define PMC_BODVBAT_TRIGLVL_MASK (0x1FU) +#define PMC_BODVBAT_TRIGLVL_SHIFT (0U) +/*! TRIGLVL - BoD trigger level. + * 0b00000..1.00 V. + * 0b00001..1.10 V. + * 0b00010..1.20 V. + * 0b00011..1.30 V. + * 0b00100..1.40 V. + * 0b00101..1.50 V. + * 0b00110..1.60 V. + * 0b00111..1.65 V. + * 0b01000..1.70 V. + * 0b01001..1.75 V. + * 0b01010..1.80 V. + * 0b01011..1.90 V. + * 0b01100..2.00 V. + * 0b01101..2.10 V. + * 0b01110..2.20 V. + * 0b01111..2.30 V. + * 0b10000..2.40 V. + * 0b10001..2.50 V. + * 0b10010..2.60 V. + * 0b10011..2.70 V. + * 0b10100..2.806 V. + * 0b10101..2.90 V. + * 0b10110..3.00 V. + * 0b10111..3.10 V. + * 0b11000..3.20 V. + * 0b11001..3.30 V. + * 0b11010..3.30 V. + * 0b11011..3.30 V. + * 0b11100..3.30 V. + * 0b11101..3.30 V. + * 0b11110..3.30 V. + * 0b11111..3.30 V. + */ +#define PMC_BODVBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_TRIGLVL_SHIFT)) & PMC_BODVBAT_TRIGLVL_MASK) +#define PMC_BODVBAT_HYST_MASK (0x60U) +#define PMC_BODVBAT_HYST_SHIFT (5U) +/*! HYST - BoD Hysteresis control. + * 0b00..25 mV. + * 0b01..50 mV. + * 0b10..75 mV. + * 0b11..100 mV. + */ +#define PMC_BODVBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK) +/*! @} */ + +/*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ +#define PMC_COMP_HYST_MASK (0x2U) +#define PMC_COMP_HYST_SHIFT (1U) +/*! HYST - Hysteris when hyst = '1'. + * 0b0..Hysteresis is disable. + * 0b1..Hysteresis is enable. + */ +#define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK) +#define PMC_COMP_VREFINPUT_MASK (0x4U) +#define PMC_COMP_VREFINPUT_SHIFT (2U) +/*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). + * 0b0..Select internal VREF. + * 0b1..Select VDDA. + */ +#define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK) +#define PMC_COMP_LOWPOWER_MASK (0x8U) +#define PMC_COMP_LOWPOWER_SHIFT (3U) +/*! LOWPOWER - Low power mode. + * 0b0..High speed mode. + * 0b1..Low power mode (Low speed). + */ +#define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK) +#define PMC_COMP_PMUX_MASK (0x70U) +#define PMC_COMP_PMUX_SHIFT (4U) +/*! PMUX - Control word for P multiplexer:. + * 0b000..VREF (See fiedl VREFINPUT). + * 0b001..Pin P0_0. + * 0b010..Pin P0_9. + * 0b011..Pin P0_18. + * 0b100..Pin P1_14. + * 0b101..Pin P2_23. + */ +#define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK) +#define PMC_COMP_NMUX_MASK (0x380U) +#define PMC_COMP_NMUX_SHIFT (7U) +/*! NMUX - Control word for N multiplexer:. + * 0b000..VREF (See field VREFINPUT). + * 0b001..Pin P0_0. + * 0b010..Pin P0_9. + * 0b011..Pin P0_18. + * 0b100..Pin P1_14. + * 0b101..Pin P2_23. + */ +#define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK) +#define PMC_COMP_VREF_MASK (0x7C00U) +#define PMC_COMP_VREF_SHIFT (10U) +#define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK) +#define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U) +#define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U) +#define PMC_COMP_FILTERCGF_SAMPLEMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK) +#define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U) +#define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U) +#define PMC_COMP_FILTERCGF_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK) +/*! @} */ + +/*! @name WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode */ +/*! @{ */ +#define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U) +#define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U) +/*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0. + */ +#define PMC_WAKEIOCAUSE_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK) +#define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U) +#define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U) +/*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1. + */ +#define PMC_WAKEIOCAUSE_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK) +#define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U) +#define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U) +/*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2. + */ +#define PMC_WAKEIOCAUSE_WAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK) +#define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U) +#define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U) +/*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 3. + */ +#define PMC_WAKEIOCAUSE_WAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK) +/*! @} */ + +/*! @name STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ +#define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U) +#define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U) +#define PMC_STATUSCLK_XTAL32KOK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK) +#define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U) +#define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U) +/*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. + * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared.. + * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared.. + */ +#define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK) +/*! @} */ + +/*! @name AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ +#define PMC_AOREG1_POR_MASK (0x10U) +#define PMC_AOREG1_POR_SHIFT (4U) +#define PMC_AOREG1_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_POR_SHIFT)) & PMC_AOREG1_POR_MASK) +#define PMC_AOREG1_PADRESET_MASK (0x20U) +#define PMC_AOREG1_PADRESET_SHIFT (5U) +#define PMC_AOREG1_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_PADRESET_SHIFT)) & PMC_AOREG1_PADRESET_MASK) +#define PMC_AOREG1_BODRESET_MASK (0x40U) +#define PMC_AOREG1_BODRESET_SHIFT (6U) +#define PMC_AOREG1_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BODRESET_SHIFT)) & PMC_AOREG1_BODRESET_MASK) +#define PMC_AOREG1_SYSTEMRESET_MASK (0x80U) +#define PMC_AOREG1_SYSTEMRESET_SHIFT (7U) +#define PMC_AOREG1_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SYSTEMRESET_SHIFT)) & PMC_AOREG1_SYSTEMRESET_MASK) +#define PMC_AOREG1_WDTRESET_MASK (0x100U) +#define PMC_AOREG1_WDTRESET_SHIFT (8U) +#define PMC_AOREG1_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_WDTRESET_SHIFT)) & PMC_AOREG1_WDTRESET_MASK) +#define PMC_AOREG1_SWRRESET_MASK (0x200U) +#define PMC_AOREG1_SWRRESET_SHIFT (9U) +#define PMC_AOREG1_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SWRRESET_SHIFT)) & PMC_AOREG1_SWRRESET_MASK) +#define PMC_AOREG1_DPDRESET_WAKEUPIO_MASK (0x400U) +#define PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT (10U) +#define PMC_AOREG1_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT)) & PMC_AOREG1_DPDRESET_WAKEUPIO_MASK) +#define PMC_AOREG1_DPDRESET_RTC_MASK (0x800U) +#define PMC_AOREG1_DPDRESET_RTC_SHIFT (11U) +#define PMC_AOREG1_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_RTC_SHIFT)) & PMC_AOREG1_DPDRESET_RTC_MASK) +#define PMC_AOREG1_DPDRESET_OSTIMER_MASK (0x1000U) +#define PMC_AOREG1_DPDRESET_OSTIMER_SHIFT (12U) +#define PMC_AOREG1_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_OSTIMER_SHIFT)) & PMC_AOREG1_DPDRESET_OSTIMER_MASK) +#define PMC_AOREG1_BOOTERRORCOUNTER_MASK (0xF0000U) +#define PMC_AOREG1_BOOTERRORCOUNTER_SHIFT (16U) +#define PMC_AOREG1_BOOTERRORCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BOOTERRORCOUNTER_SHIFT)) & PMC_AOREG1_BOOTERRORCOUNTER_MASK) +/*! @} */ + +/*! @name RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ +#define PMC_RTCOSC32K_SEL_MASK (0x1U) +#define PMC_RTCOSC32K_SEL_SHIFT (0U) +/*! SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . + * 0b0..FRO 32 KHz. + * 0b1..XTAL 32KHz. + */ +#define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK) +#define PMC_RTCOSC32K_CLK1KHZDIV_MASK (0xEU) +#define PMC_RTCOSC32K_CLK1KHZDIV_SHIFT (1U) +#define PMC_RTCOSC32K_CLK1KHZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIV_MASK) +#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK (0x8000U) +#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT (15U) +#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK) +#define PMC_RTCOSC32K_CLK1HZDIV_MASK (0x7FF0000U) +#define PMC_RTCOSC32K_CLK1HZDIV_SHIFT (16U) +#define PMC_RTCOSC32K_CLK1HZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIV_MASK) +#define PMC_RTCOSC32K_CLK1HZDIVHALT_MASK (0x40000000U) +#define PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT (30U) +#define PMC_RTCOSC32K_CLK1HZDIVHALT(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVHALT_MASK) +#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK (0x80000000U) +#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT (31U) +#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK) +/*! @} */ + +/*! @name OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ +#define PMC_OSTIMER_SOFTRESET_MASK (0x1U) +#define PMC_OSTIMER_SOFTRESET_SHIFT (0U) +#define PMC_OSTIMER_SOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_SOFTRESET_SHIFT)) & PMC_OSTIMER_SOFTRESET_MASK) +#define PMC_OSTIMER_CLOCKENABLE_MASK (0x2U) +#define PMC_OSTIMER_CLOCKENABLE_SHIFT (1U) +#define PMC_OSTIMER_CLOCKENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_CLOCKENABLE_SHIFT)) & PMC_OSTIMER_CLOCKENABLE_MASK) +#define PMC_OSTIMER_DPDWAKEUPENABLE_MASK (0x4U) +#define PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT (2U) +#define PMC_OSTIMER_DPDWAKEUPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSTIMER_DPDWAKEUPENABLE_MASK) +#define PMC_OSTIMER_OSC32KPD_MASK (0x8U) +#define PMC_OSTIMER_OSC32KPD_SHIFT (3U) +#define PMC_OSTIMER_OSC32KPD(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSC32KPD_SHIFT)) & PMC_OSTIMER_OSC32KPD_MASK) +/*! @} */ + +/*! @name PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ +#define PMC_PDRUNCFG0_PDEN_BODVBAT_MASK (0x8U) +#define PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT (3U) +/*! PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD). + * 0b0..BOD VBAT is powered. + * 0b1..BOD VBAT is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVBAT_MASK) +#define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U) +#define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U) +/*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. + * 0b0..FRO32KHz is powered. + * 0b1..FRO32KHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK) +#define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U) +#define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U) +/*! PDEN_XTAL32K - Controls power to crystal 32 KHz. + * 0b0..Crystal 32KHz is powered. + * 0b1..Crystal 32KHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK) +#define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK (0x100U) +#define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT (8U) +/*! PDEN_XTAL32M - Controls power to crystal 32 MHz. + * 0b0..Crystal 32MHz is powered. + * 0b1..Crystal 32MHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK) +#define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U) +#define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U) +/*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). + * 0b0..PLL0 is powered. + * 0b1..PLL0 is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK) +#define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U) +#define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U) +/*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1). + * 0b0..PLL1 is powered. + * 0b1..PLL1 is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK) +#define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK (0x800U) +#define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT (11U) +/*! PDEN_USBFSPHY - Controls power to USB Full Speed phy. + * 0b0..USB Full Speed phy is powered. + * 0b1..USB Full Speed phy is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK) +#define PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK (0x1000U) +#define PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT (12U) +/*! PDEN_USBHSPHY - Controls power to USB High Speed Phy. + * 0b0..USB HS phy is powered. + * 0b1..USB HS phy is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK) +#define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U) +#define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U) +/*! PDEN_COMP - Controls power to Analog Comparator. + * 0b0..Analog Comparator is powered. + * 0b1..Analog Comparator is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK) +#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK (0x40000U) +#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT (18U) +/*! PDEN_LDOUSBHS - Controls power to USB high speed LDO. + * 0b0..USB high speed LDO is powered. + * 0b1..USB high speed LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK) +#define PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK (0x80000U) +#define PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT (19U) +/*! PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS) + * 0b0..auxiliary biasing is powered. + * 0b1..auxiliary biasing is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK) +#define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK (0x100000U) +#define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT (20U) +/*! PDEN_LDOXO32M - Controls power to crystal 32 MHz LDO. + * 0b0..crystal 32 MHz LDO is powered. + * 0b1..crystal 32 MHz LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK) +#define PMC_PDRUNCFG0_PDEN_RNG_MASK (0x400000U) +#define PMC_PDRUNCFG0_PDEN_RNG_SHIFT (22U) +/*! PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources. + * 0b0..TRNG clocks are powered. + * 0b1..TRNG clocks are powered down. + */ +#define PMC_PDRUNCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_RNG_SHIFT)) & PMC_PDRUNCFG0_PDEN_RNG_MASK) +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U) +/*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. + * 0b0..PLL0 Sread spectrum module is powered. + * 0b1..PLL0 Sread spectrum module is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) +/*! @} */ + +/*! @name PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU) +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U) +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK) +/*! @} */ + +/*! @name PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU) +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U) +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PMC_Register_Masks */ + + +/* PMC - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral PMC base address */ + #define PMC_BASE (0x50020000u) + /** Peripheral PMC base address */ + #define PMC_BASE_NS (0x40020000u) + /** Peripheral PMC base pointer */ + #define PMC ((PMC_Type *)PMC_BASE) + /** Peripheral PMC base pointer */ + #define PMC_NS ((PMC_Type *)PMC_BASE_NS) + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS { PMC_BASE } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS { PMC } + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS_NS { PMC_BASE_NS } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS_NS { PMC_NS } +#else + /** Peripheral PMC base address */ + #define PMC_BASE (0x40020000u) + /** Peripheral PMC base pointer */ + #define PMC ((PMC_Type *)PMC_BASE) + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS { PMC_BASE } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS { PMC } +#endif + +/*! + * @} + */ /* end of group PMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- POWERQUAD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup POWERQUAD_Peripheral_Access_Layer POWERQUAD Peripheral Access Layer + * @{ + */ + +/** POWERQUAD - Register Layout Typedef */ +typedef struct { + __IO uint32_t OUTBASE; /**< Base address register for output region, offset: 0x0 */ + __IO uint32_t OUTFORMAT; /**< Output format, offset: 0x4 */ + __IO uint32_t TMPBASE; /**< Base address register for temp region, offset: 0x8 */ + __IO uint32_t TMPFORMAT; /**< Temp format, offset: 0xC */ + __IO uint32_t INABASE; /**< Base address register for input A region, offset: 0x10 */ + __IO uint32_t INAFORMAT; /**< Input A format, offset: 0x14 */ + __IO uint32_t INBBASE; /**< Base address register for input B region, offset: 0x18 */ + __IO uint32_t INBFORMAT; /**< Input B format, offset: 0x1C */ + uint8_t RESERVED_0[224]; + __IO uint32_t CONTROL; /**< PowerQuad Control register, offset: 0x100 */ + __IO uint32_t LENGTH; /**< Length register, offset: 0x104 */ + __IO uint32_t CPPRE; /**< Pre-scale register, offset: 0x108 */ + __IO uint32_t MISC; /**< Misc register, offset: 0x10C */ + __IO uint32_t CURSORY; /**< Cursory register, offset: 0x110 */ + uint8_t RESERVED_1[108]; + __IO uint32_t CORDIC_X; /**< Cordic input X register, offset: 0x180 */ + __IO uint32_t CORDIC_Y; /**< Cordic input Y register, offset: 0x184 */ + __IO uint32_t CORDIC_Z; /**< Cordic input Z register, offset: 0x188 */ + __IO uint32_t ERRSTAT; /**< Read/Write register where error statuses are captured (sticky), offset: 0x18C */ + __IO uint32_t INTREN; /**< INTERRUPT enable register, offset: 0x190 */ + __IO uint32_t EVENTEN; /**< Event Enable register, offset: 0x194 */ + __IO uint32_t INTRSTAT; /**< INTERRUPT STATUS register, offset: 0x198 */ + uint8_t RESERVED_2[100]; + __IO uint32_t GPREG[16]; /**< General purpose register bank N., array offset: 0x200, array step: 0x4 */ + __IO uint32_t COMPREG[8]; /**< Compute register bank, array offset: 0x240, array step: 0x4 */ +} POWERQUAD_Type; + +/* ---------------------------------------------------------------------------- + -- POWERQUAD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup POWERQUAD_Register_Masks POWERQUAD Register Masks + * @{ + */ + +/*! @name OUTBASE - Base address register for output region */ +/*! @{ */ +#define POWERQUAD_OUTBASE_OUTBASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_OUTBASE_OUTBASE_SHIFT (0U) +#define POWERQUAD_OUTBASE_OUTBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK) +/*! @} */ + +/*! @name OUTFORMAT - Output format */ +/*! @{ */ +#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK (0x3U) +#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT (0U) +#define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK) +#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK (0x30U) +#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT (4U) +#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK) +#define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK (0xFF00U) +#define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT (8U) +#define POWERQUAD_OUTFORMAT_OUT_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK) +/*! @} */ + +/*! @name TMPBASE - Base address register for temp region */ +/*! @{ */ +#define POWERQUAD_TMPBASE_TMPBASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_TMPBASE_TMPBASE_SHIFT (0U) +#define POWERQUAD_TMPBASE_TMPBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK) +/*! @} */ + +/*! @name TMPFORMAT - Temp format */ +/*! @{ */ +#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK (0x3U) +#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT (0U) +#define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK) +#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK (0x30U) +#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT (4U) +#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK) +#define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK (0xFF00U) +#define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT (8U) +#define POWERQUAD_TMPFORMAT_TMP_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK) +/*! @} */ + +/*! @name INABASE - Base address register for input A region */ +/*! @{ */ +#define POWERQUAD_INABASE_INABASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_INABASE_INABASE_SHIFT (0U) +#define POWERQUAD_INABASE_INABASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK) +/*! @} */ + +/*! @name INAFORMAT - Input A format */ +/*! @{ */ +#define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK (0x3U) +#define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT (0U) +#define POWERQUAD_INAFORMAT_INA_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK) +#define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK (0x30U) +#define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT (4U) +#define POWERQUAD_INAFORMAT_INA_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK) +#define POWERQUAD_INAFORMAT_INA_SCALER_MASK (0xFF00U) +#define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT (8U) +#define POWERQUAD_INAFORMAT_INA_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK) +/*! @} */ + +/*! @name INBBASE - Base address register for input B region */ +/*! @{ */ +#define POWERQUAD_INBBASE_INBBASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_INBBASE_INBBASE_SHIFT (0U) +#define POWERQUAD_INBBASE_INBBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK) +/*! @} */ + +/*! @name INBFORMAT - Input B format */ +/*! @{ */ +#define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK (0x3U) +#define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT (0U) +#define POWERQUAD_INBFORMAT_INB_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK) +#define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK (0x30U) +#define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT (4U) +#define POWERQUAD_INBFORMAT_INB_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK) +#define POWERQUAD_INBFORMAT_INB_SCALER_MASK (0xFF00U) +#define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT (8U) +#define POWERQUAD_INBFORMAT_INB_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK) +/*! @} */ + +/*! @name CONTROL - PowerQuad Control register */ +/*! @{ */ +#define POWERQUAD_CONTROL_DECODE_OPCODE_MASK (0xFU) +#define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT (0U) +#define POWERQUAD_CONTROL_DECODE_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK) +#define POWERQUAD_CONTROL_DECODE_MACHINE_MASK (0xF0U) +#define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT (4U) +#define POWERQUAD_CONTROL_DECODE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK) +#define POWERQUAD_CONTROL_INST_BUSY_MASK (0x80000000U) +#define POWERQUAD_CONTROL_INST_BUSY_SHIFT (31U) +#define POWERQUAD_CONTROL_INST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK) +/*! @} */ + +/*! @name LENGTH - Length register */ +/*! @{ */ +#define POWERQUAD_LENGTH_INST_LENGTH_MASK (0xFFFFFFFFU) +#define POWERQUAD_LENGTH_INST_LENGTH_SHIFT (0U) +#define POWERQUAD_LENGTH_INST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK) +/*! @} */ + +/*! @name CPPRE - Pre-scale register */ +/*! @{ */ +#define POWERQUAD_CPPRE_CPPRE_IN_MASK (0xFFU) +#define POWERQUAD_CPPRE_CPPRE_IN_SHIFT (0U) +#define POWERQUAD_CPPRE_CPPRE_IN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK) +#define POWERQUAD_CPPRE_CPPRE_OUT_MASK (0xFF00U) +#define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT (8U) +#define POWERQUAD_CPPRE_CPPRE_OUT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK) +#define POWERQUAD_CPPRE_CPPRE_SAT_MASK (0x10000U) +#define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT (16U) +#define POWERQUAD_CPPRE_CPPRE_SAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK) +#define POWERQUAD_CPPRE_CPPRE_SAT8_MASK (0x20000U) +#define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT (17U) +#define POWERQUAD_CPPRE_CPPRE_SAT8(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK) +/*! @} */ + +/*! @name MISC - Misc register */ +/*! @{ */ +#define POWERQUAD_MISC_INST_MISC_MASK (0xFFFFFFFFU) +#define POWERQUAD_MISC_INST_MISC_SHIFT (0U) +#define POWERQUAD_MISC_INST_MISC(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK) +/*! @} */ + +/*! @name CURSORY - Cursory register */ +/*! @{ */ +#define POWERQUAD_CURSORY_CURSORY_MASK (0x1U) +#define POWERQUAD_CURSORY_CURSORY_SHIFT (0U) +#define POWERQUAD_CURSORY_CURSORY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK) +/*! @} */ + +/*! @name CORDIC_X - Cordic input X register */ +/*! @{ */ +#define POWERQUAD_CORDIC_X_CORDIC_X_MASK (0xFFFFFFFFU) +#define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT (0U) +#define POWERQUAD_CORDIC_X_CORDIC_X(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK) +/*! @} */ + +/*! @name CORDIC_Y - Cordic input Y register */ +/*! @{ */ +#define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK (0xFFFFFFFFU) +#define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT (0U) +#define POWERQUAD_CORDIC_Y_CORDIC_Y(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK) +/*! @} */ + +/*! @name CORDIC_Z - Cordic input Z register */ +/*! @{ */ +#define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK (0xFFFFFFFFU) +#define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT (0U) +#define POWERQUAD_CORDIC_Z_CORDIC_Z(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK) +/*! @} */ + +/*! @name ERRSTAT - Read/Write register where error statuses are captured (sticky) */ +/*! @{ */ +#define POWERQUAD_ERRSTAT_OVERFLOW_MASK (0x1U) +#define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT (0U) +#define POWERQUAD_ERRSTAT_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK) +#define POWERQUAD_ERRSTAT_NAN_MASK (0x2U) +#define POWERQUAD_ERRSTAT_NAN_SHIFT (1U) +#define POWERQUAD_ERRSTAT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK) +#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK (0x4U) +#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT (2U) +#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK) +#define POWERQUAD_ERRSTAT_UNDERFLOW_MASK (0x8U) +#define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT (3U) +#define POWERQUAD_ERRSTAT_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK) +#define POWERQUAD_ERRSTAT_BUSERROR_MASK (0x10U) +#define POWERQUAD_ERRSTAT_BUSERROR_SHIFT (4U) +#define POWERQUAD_ERRSTAT_BUSERROR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK) +/*! @} */ + +/*! @name INTREN - INTERRUPT enable register */ +/*! @{ */ +#define POWERQUAD_INTREN_INTR_OFLOW_MASK (0x1U) +#define POWERQUAD_INTREN_INTR_OFLOW_SHIFT (0U) +#define POWERQUAD_INTREN_INTR_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK) +#define POWERQUAD_INTREN_INTR_NAN_MASK (0x2U) +#define POWERQUAD_INTREN_INTR_NAN_SHIFT (1U) +#define POWERQUAD_INTREN_INTR_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK) +#define POWERQUAD_INTREN_INTR_FIXED_MASK (0x4U) +#define POWERQUAD_INTREN_INTR_FIXED_SHIFT (2U) +#define POWERQUAD_INTREN_INTR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK) +#define POWERQUAD_INTREN_INTR_UFLOW_MASK (0x8U) +#define POWERQUAD_INTREN_INTR_UFLOW_SHIFT (3U) +#define POWERQUAD_INTREN_INTR_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK) +#define POWERQUAD_INTREN_INTR_BERR_MASK (0x10U) +#define POWERQUAD_INTREN_INTR_BERR_SHIFT (4U) +#define POWERQUAD_INTREN_INTR_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK) +#define POWERQUAD_INTREN_INTR_COMP_MASK (0x80U) +#define POWERQUAD_INTREN_INTR_COMP_SHIFT (7U) +#define POWERQUAD_INTREN_INTR_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK) +/*! @} */ + +/*! @name EVENTEN - Event Enable register */ +/*! @{ */ +#define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK (0x1U) +#define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT (0U) +#define POWERQUAD_EVENTEN_EVENT_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK) +#define POWERQUAD_EVENTEN_EVENT_NAN_MASK (0x2U) +#define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT (1U) +#define POWERQUAD_EVENTEN_EVENT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK) +#define POWERQUAD_EVENTEN_EVENT_FIXED_MASK (0x4U) +#define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT (2U) +#define POWERQUAD_EVENTEN_EVENT_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK) +#define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK (0x8U) +#define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT (3U) +#define POWERQUAD_EVENTEN_EVENT_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK) +#define POWERQUAD_EVENTEN_EVENT_BERR_MASK (0x10U) +#define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT (4U) +#define POWERQUAD_EVENTEN_EVENT_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK) +#define POWERQUAD_EVENTEN_EVENT_COMP_MASK (0x80U) +#define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT (7U) +#define POWERQUAD_EVENTEN_EVENT_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK) +/*! @} */ + +/*! @name INTRSTAT - INTERRUPT STATUS register */ +/*! @{ */ +#define POWERQUAD_INTRSTAT_INTR_STAT_MASK (0x1U) +#define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT (0U) +#define POWERQUAD_INTRSTAT_INTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK) +/*! @} */ + +/*! @name GPREG - General purpose register bank N. */ +/*! @{ */ +#define POWERQUAD_GPREG_GPREG_MASK (0xFFFFFFFFU) +#define POWERQUAD_GPREG_GPREG_SHIFT (0U) +#define POWERQUAD_GPREG_GPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK) +/*! @} */ + +/* The count of POWERQUAD_GPREG */ +#define POWERQUAD_GPREG_COUNT (16U) + +/*! @name COMPREGS_COMPREG - Compute register bank */ +/*! @{ */ +#define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK (0xFFFFFFFFU) +#define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U) +#define POWERQUAD_COMPREGS_COMPREG_COMPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK) +/*! @} */ + +/* The count of POWERQUAD_COMPREGS_COMPREG */ +#define POWERQUAD_COMPREGS_COMPREG_COUNT (8U) + + +/*! + * @} + */ /* end of group POWERQUAD_Register_Masks */ + + +/* POWERQUAD - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x500A6000u) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE_NS (0x400A6000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } +#else + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x400A6000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } +#endif + +/*! + * @} + */ /* end of group POWERQUAD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PRINCE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PRINCE_Peripheral_Access_Layer PRINCE Peripheral Access Layer + * @{ + */ + +/** PRINCE - Register Layout Typedef */ +typedef struct { + __IO uint32_t ENC_ENABLE; /**< Encryption Enable register, offset: 0x0 */ + __O uint32_t MASK_LSB; /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */ + __O uint32_t MASK_MSB; /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */ + __IO uint32_t LOCK; /**< Lock register, offset: 0xC */ + __O uint32_t IV_LSB0; /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */ + __O uint32_t IV_MSB0; /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */ + __IO uint32_t BASE_ADDR0; /**< Base Address for region 0 register, offset: 0x18 */ + __IO uint32_t SR_ENABLE0; /**< Sub-Region Enable register for region 0, offset: 0x1C */ + __O uint32_t IV_LSB1; /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */ + __O uint32_t IV_MSB1; /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */ + __IO uint32_t BASE_ADDR1; /**< Base Address for region 1 register, offset: 0x28 */ + __IO uint32_t SR_ENABLE1; /**< Sub-Region Enable register for region 1, offset: 0x2C */ + __O uint32_t IV_LSB2; /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */ + __O uint32_t IV_MSB2; /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */ + __IO uint32_t BASE_ADDR2; /**< Base Address for region 2 register, offset: 0x38 */ + __IO uint32_t SR_ENABLE2; /**< Sub-Region Enable register for region 2, offset: 0x3C */ +} PRINCE_Type; + +/* ---------------------------------------------------------------------------- + -- PRINCE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PRINCE_Register_Masks PRINCE Register Masks + * @{ + */ + +/*! @name ENC_ENABLE - Encryption Enable register */ +/*! @{ */ +#define PRINCE_ENC_ENABLE_EN_MASK (0x1U) +#define PRINCE_ENC_ENABLE_EN_SHIFT (0U) +/*! EN - Encryption Enable. + * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled. + * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled. + */ +#define PRINCE_ENC_ENABLE_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK) +/*! @} */ + +/*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */ +/*! @{ */ +#define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU) +#define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U) +#define PRINCE_MASK_LSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK) +/*! @} */ + +/*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */ +/*! @{ */ +#define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU) +#define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U) +#define PRINCE_MASK_MSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK) +/*! @} */ + +/*! @name LOCK - Lock register */ +/*! @{ */ +#define PRINCE_LOCK_LOCKREG0_MASK (0x1U) +#define PRINCE_LOCK_LOCKREG0_SHIFT (0U) +/*! LOCKREG0 - Lock Region 0 registers. + * 0b0..Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. + * 0b1..Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. + */ +#define PRINCE_LOCK_LOCKREG0(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK) +#define PRINCE_LOCK_LOCKREG1_MASK (0x2U) +#define PRINCE_LOCK_LOCKREG1_SHIFT (1U) +/*! LOCKREG1 - Lock Region 1 registers. + * 0b0..Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. + * 0b1..Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. + */ +#define PRINCE_LOCK_LOCKREG1(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK) +#define PRINCE_LOCK_LOCKREG2_MASK (0x4U) +#define PRINCE_LOCK_LOCKREG2_SHIFT (2U) +/*! LOCKREG2 - Lock Region 2 registers. + * 0b0..Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. + * 0b1..Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. + */ +#define PRINCE_LOCK_LOCKREG2(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK) +#define PRINCE_LOCK_LOCKMASK_MASK (0x100U) +#define PRINCE_LOCK_LOCKMASK_SHIFT (8U) +/*! LOCKMASK - Lock the Mask registers. + * 0b0..Disabled. MASK_LSB, and MASK_MSB are writable.. + * 0b1..Enabled. MASK_LSB, and MASK_MSB are not writable.. + */ +#define PRINCE_LOCK_LOCKMASK(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK) +/*! @} */ + +/*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */ +/*! @{ */ +#define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB0_IVVAL_SHIFT (0U) +#define PRINCE_IV_LSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */ +/*! @{ */ +#define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB0_IVVAL_SHIFT (0U) +#define PRINCE_IV_MSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR0 - Base Address for region 0 register */ +/*! @{ */ +#define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U) +#define PRINCE_BASE_ADDR0_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK) +#define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U) +#define PRINCE_BASE_ADDR0_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */ +/*! @{ */ +#define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE0_EN_SHIFT (0U) +#define PRINCE_SR_ENABLE0_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK) +/*! @} */ + +/*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */ +/*! @{ */ +#define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB1_IVVAL_SHIFT (0U) +#define PRINCE_IV_LSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */ +/*! @{ */ +#define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB1_IVVAL_SHIFT (0U) +#define PRINCE_IV_MSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR1 - Base Address for region 1 register */ +/*! @{ */ +#define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U) +#define PRINCE_BASE_ADDR1_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK) +#define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U) +#define PRINCE_BASE_ADDR1_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */ +/*! @{ */ +#define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE1_EN_SHIFT (0U) +#define PRINCE_SR_ENABLE1_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK) +/*! @} */ + +/*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */ +/*! @{ */ +#define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB2_IVVAL_SHIFT (0U) +#define PRINCE_IV_LSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */ +/*! @{ */ +#define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB2_IVVAL_SHIFT (0U) +#define PRINCE_IV_MSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR2 - Base Address for region 2 register */ +/*! @{ */ +#define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U) +#define PRINCE_BASE_ADDR2_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK) +#define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U) +#define PRINCE_BASE_ADDR2_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */ +/*! @{ */ +#define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE2_EN_SHIFT (0U) +#define PRINCE_SR_ENABLE2_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PRINCE_Register_Masks */ + + +/* PRINCE - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral PRINCE base address */ + #define PRINCE_BASE (0x50035000u) + /** Peripheral PRINCE base address */ + #define PRINCE_BASE_NS (0x40035000u) + /** Peripheral PRINCE base pointer */ + #define PRINCE ((PRINCE_Type *)PRINCE_BASE) + /** Peripheral PRINCE base pointer */ + #define PRINCE_NS ((PRINCE_Type *)PRINCE_BASE_NS) + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS { PRINCE_BASE } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS { PRINCE } + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS_NS { PRINCE_BASE_NS } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS_NS { PRINCE_NS } +#else + /** Peripheral PRINCE base address */ + #define PRINCE_BASE (0x40035000u) + /** Peripheral PRINCE base pointer */ + #define PRINCE ((PRINCE_Type *)PRINCE_BASE) + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS { PRINCE_BASE } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS { PRINCE } +#endif + +/*! + * @} + */ /* end of group PRINCE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PUF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer + * @{ + */ + +/** PUF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< PUF Control register, offset: 0x0 */ + __IO uint32_t KEYINDEX; /**< PUF Key Index register, offset: 0x4 */ + __IO uint32_t KEYSIZE; /**< PUF Key Size register, offset: 0x8 */ + uint8_t RESERVED_0[20]; + __I uint32_t STAT; /**< PUF Status register, offset: 0x20 */ + uint8_t RESERVED_1[4]; + __I uint32_t ALLOW; /**< PUF Allow register, offset: 0x28 */ + uint8_t RESERVED_2[20]; + __O uint32_t KEYINPUT; /**< PUF Key Input register, offset: 0x40 */ + __O uint32_t CODEINPUT; /**< PUF Code Input register, offset: 0x44 */ + __I uint32_t CODEOUTPUT; /**< PUF Code Output register, offset: 0x48 */ + uint8_t RESERVED_3[20]; + __I uint32_t KEYOUTINDEX; /**< PUF Key Output Index register, offset: 0x60 */ + __I uint32_t KEYOUTPUT; /**< PUF Key Output register, offset: 0x64 */ + uint8_t RESERVED_4[116]; + __IO uint32_t IFSTAT; /**< PUF Interface Status and clear register, offset: 0xDC */ + uint8_t RESERVED_5[28]; + __I uint32_t VERSION; /**< PUF version register., offset: 0xFC */ + __IO uint32_t INTEN; /**< PUF Interrupt Enable, offset: 0x100 */ + __IO uint32_t INTSTAT; /**< PUF interrupt status, offset: 0x104 */ + __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */ + __IO uint32_t CFG; /**< PUF config register for block bits, offset: 0x10C */ + uint8_t RESERVED_6[240]; + __IO uint32_t KEYLOCK; /**< Only reset in case of full IC reset, offset: 0x200 */ + __IO uint32_t KEYENABLE; /**< , offset: 0x204 */ + __O uint32_t KEYRESET; /**< Reinitialize Keys shift registers counters, offset: 0x208 */ + __IO uint32_t IDXBLK_L; /**< , offset: 0x20C */ + __IO uint32_t IDXBLK_H_DP; /**< , offset: 0x210 */ + __O uint32_t KEYMASK[4]; /**< Only reset in case of full IC reset, array offset: 0x214, array step: 0x4 */ + uint8_t RESERVED_7[48]; + __IO uint32_t IDXBLK_H; /**< , offset: 0x254 */ + __IO uint32_t IDXBLK_L_DP; /**< , offset: 0x258 */ + __I uint32_t SHIFT_STATUS; /**< , offset: 0x25C */ +} PUF_Type; + +/* ---------------------------------------------------------------------------- + -- PUF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Register_Masks PUF Register Masks + * @{ + */ + +/*! @name CTRL - PUF Control register */ +/*! @{ */ +#define PUF_CTRL_ZEROIZE_MASK (0x1U) +#define PUF_CTRL_ZEROIZE_SHIFT (0U) +#define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK) +#define PUF_CTRL_ENROLL_MASK (0x2U) +#define PUF_CTRL_ENROLL_SHIFT (1U) +#define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK) +#define PUF_CTRL_START_MASK (0x4U) +#define PUF_CTRL_START_SHIFT (2U) +#define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK) +#define PUF_CTRL_GENERATEKEY_MASK (0x8U) +#define PUF_CTRL_GENERATEKEY_SHIFT (3U) +#define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK) +#define PUF_CTRL_SETKEY_MASK (0x10U) +#define PUF_CTRL_SETKEY_SHIFT (4U) +#define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK) +#define PUF_CTRL_GETKEY_MASK (0x40U) +#define PUF_CTRL_GETKEY_SHIFT (6U) +#define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK) +/*! @} */ + +/*! @name KEYINDEX - PUF Key Index register */ +/*! @{ */ +#define PUF_KEYINDEX_KEYIDX_MASK (0xFU) +#define PUF_KEYINDEX_KEYIDX_SHIFT (0U) +#define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK) +/*! @} */ + +/*! @name KEYSIZE - PUF Key Size register */ +/*! @{ */ +#define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU) +#define PUF_KEYSIZE_KEYSIZE_SHIFT (0U) +#define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK) +/*! @} */ + +/*! @name STAT - PUF Status register */ +/*! @{ */ +#define PUF_STAT_BUSY_MASK (0x1U) +#define PUF_STAT_BUSY_SHIFT (0U) +#define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK) +#define PUF_STAT_SUCCESS_MASK (0x2U) +#define PUF_STAT_SUCCESS_SHIFT (1U) +#define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK) +#define PUF_STAT_ERROR_MASK (0x4U) +#define PUF_STAT_ERROR_SHIFT (2U) +#define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK) +#define PUF_STAT_KEYINREQ_MASK (0x10U) +#define PUF_STAT_KEYINREQ_SHIFT (4U) +#define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK) +#define PUF_STAT_KEYOUTAVAIL_MASK (0x20U) +#define PUF_STAT_KEYOUTAVAIL_SHIFT (5U) +#define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK) +#define PUF_STAT_CODEINREQ_MASK (0x40U) +#define PUF_STAT_CODEINREQ_SHIFT (6U) +#define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK) +#define PUF_STAT_CODEOUTAVAIL_MASK (0x80U) +#define PUF_STAT_CODEOUTAVAIL_SHIFT (7U) +#define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK) +/*! @} */ + +/*! @name ALLOW - PUF Allow register */ +/*! @{ */ +#define PUF_ALLOW_ALLOWENROLL_MASK (0x1U) +#define PUF_ALLOW_ALLOWENROLL_SHIFT (0U) +#define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK) +#define PUF_ALLOW_ALLOWSTART_MASK (0x2U) +#define PUF_ALLOW_ALLOWSTART_SHIFT (1U) +#define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK) +#define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U) +#define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U) +#define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK) +#define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U) +#define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U) +#define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK) +/*! @} */ + +/*! @name KEYINPUT - PUF Key Input register */ +/*! @{ */ +#define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU) +#define PUF_KEYINPUT_KEYIN_SHIFT (0U) +#define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK) +/*! @} */ + +/*! @name CODEINPUT - PUF Code Input register */ +/*! @{ */ +#define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU) +#define PUF_CODEINPUT_CODEIN_SHIFT (0U) +#define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK) +/*! @} */ + +/*! @name CODEOUTPUT - PUF Code Output register */ +/*! @{ */ +#define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU) +#define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U) +#define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK) +/*! @} */ + +/*! @name KEYOUTINDEX - PUF Key Output Index register */ +/*! @{ */ +#define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFU) +#define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U) +#define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK) +/*! @} */ + +/*! @name KEYOUTPUT - PUF Key Output register */ +/*! @{ */ +#define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU) +#define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U) +#define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK) +/*! @} */ + +/*! @name IFSTAT - PUF Interface Status and clear register */ +/*! @{ */ +#define PUF_IFSTAT_ERROR_MASK (0x1U) +#define PUF_IFSTAT_ERROR_SHIFT (0U) +#define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK) +/*! @} */ + +/*! @name VERSION - PUF version register. */ +/*! @{ */ +#define PUF_VERSION_VERSION_MASK (0xFFFFFFFFU) +#define PUF_VERSION_VERSION_SHIFT (0U) +#define PUF_VERSION_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_VERSION_SHIFT)) & PUF_VERSION_VERSION_MASK) +/*! @} */ + +/*! @name INTEN - PUF Interrupt Enable */ +/*! @{ */ +#define PUF_INTEN_READYEN_MASK (0x1U) +#define PUF_INTEN_READYEN_SHIFT (0U) +#define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK) +#define PUF_INTEN_SUCCESEN_MASK (0x2U) +#define PUF_INTEN_SUCCESEN_SHIFT (1U) +#define PUF_INTEN_SUCCESEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK) +#define PUF_INTEN_ERROREN_MASK (0x4U) +#define PUF_INTEN_ERROREN_SHIFT (2U) +#define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK) +#define PUF_INTEN_KEYINREQEN_MASK (0x10U) +#define PUF_INTEN_KEYINREQEN_SHIFT (4U) +#define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK) +#define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U) +#define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U) +#define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK) +#define PUF_INTEN_CODEINREQEN_MASK (0x40U) +#define PUF_INTEN_CODEINREQEN_SHIFT (6U) +#define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK) +#define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U) +#define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U) +#define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK) +/*! @} */ + +/*! @name INTSTAT - PUF interrupt status */ +/*! @{ */ +#define PUF_INTSTAT_READY_MASK (0x1U) +#define PUF_INTSTAT_READY_SHIFT (0U) +#define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK) +#define PUF_INTSTAT_SUCCESS_MASK (0x2U) +#define PUF_INTSTAT_SUCCESS_SHIFT (1U) +#define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK) +#define PUF_INTSTAT_ERROR_MASK (0x4U) +#define PUF_INTSTAT_ERROR_SHIFT (2U) +#define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK) +#define PUF_INTSTAT_KEYINREQ_MASK (0x10U) +#define PUF_INTSTAT_KEYINREQ_SHIFT (4U) +#define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK) +#define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U) +#define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U) +#define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK) +#define PUF_INTSTAT_CODEINREQ_MASK (0x40U) +#define PUF_INTSTAT_CODEINREQ_SHIFT (6U) +#define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK) +#define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U) +#define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U) +#define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK) +/*! @} */ + +/*! @name PWRCTRL - PUF RAM Power Control */ +/*! @{ */ +#define PUF_PWRCTRL_RAMON_MASK (0x1U) +#define PUF_PWRCTRL_RAMON_SHIFT (0U) +#define PUF_PWRCTRL_RAMON(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMON_SHIFT)) & PUF_PWRCTRL_RAMON_MASK) +#define PUF_PWRCTRL_RAMSTAT_MASK (0x2U) +#define PUF_PWRCTRL_RAMSTAT_SHIFT (1U) +#define PUF_PWRCTRL_RAMSTAT(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMSTAT_SHIFT)) & PUF_PWRCTRL_RAMSTAT_MASK) +/*! @} */ + +/*! @name CFG - PUF config register for block bits */ +/*! @{ */ +#define PUF_CFG_BLOCKENROLL_SETKEY_MASK (0x1U) +#define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT (0U) +#define PUF_CFG_BLOCKENROLL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK) +#define PUF_CFG_BLOCKKEYOUTPUT_MASK (0x2U) +#define PUF_CFG_BLOCKKEYOUTPUT_SHIFT (1U) +#define PUF_CFG_BLOCKKEYOUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK) +/*! @} */ + +/*! @name KEYLOCK - Only reset in case of full IC reset */ +/*! @{ */ +#define PUF_KEYLOCK_KEY0_MASK (0x3U) +#define PUF_KEYLOCK_KEY0_SHIFT (0U) +#define PUF_KEYLOCK_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK) +#define PUF_KEYLOCK_KEY1_MASK (0xCU) +#define PUF_KEYLOCK_KEY1_SHIFT (2U) +#define PUF_KEYLOCK_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK) +#define PUF_KEYLOCK_KEY2_MASK (0x30U) +#define PUF_KEYLOCK_KEY2_SHIFT (4U) +#define PUF_KEYLOCK_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK) +#define PUF_KEYLOCK_KEY3_MASK (0xC0U) +#define PUF_KEYLOCK_KEY3_SHIFT (6U) +#define PUF_KEYLOCK_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK) +/*! @} */ + +/*! @name KEYENABLE - */ +/*! @{ */ +#define PUF_KEYENABLE_KEY0_MASK (0x3U) +#define PUF_KEYENABLE_KEY0_SHIFT (0U) +#define PUF_KEYENABLE_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK) +#define PUF_KEYENABLE_KEY1_MASK (0xCU) +#define PUF_KEYENABLE_KEY1_SHIFT (2U) +#define PUF_KEYENABLE_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK) +#define PUF_KEYENABLE_KEY2_MASK (0x30U) +#define PUF_KEYENABLE_KEY2_SHIFT (4U) +#define PUF_KEYENABLE_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK) +#define PUF_KEYENABLE_KEY3_MASK (0xC0U) +#define PUF_KEYENABLE_KEY3_SHIFT (6U) +#define PUF_KEYENABLE_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK) +/*! @} */ + +/*! @name KEYRESET - Reinitialize Keys shift registers counters */ +/*! @{ */ +#define PUF_KEYRESET_KEY0_MASK (0x3U) +#define PUF_KEYRESET_KEY0_SHIFT (0U) +#define PUF_KEYRESET_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK) +#define PUF_KEYRESET_KEY1_MASK (0xCU) +#define PUF_KEYRESET_KEY1_SHIFT (2U) +#define PUF_KEYRESET_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK) +#define PUF_KEYRESET_KEY2_MASK (0x30U) +#define PUF_KEYRESET_KEY2_SHIFT (4U) +#define PUF_KEYRESET_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK) +#define PUF_KEYRESET_KEY3_MASK (0xC0U) +#define PUF_KEYRESET_KEY3_SHIFT (6U) +#define PUF_KEYRESET_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK) +/*! @} */ + +/*! @name IDXBLK_L - */ +/*! @{ */ +#define PUF_IDXBLK_L_IDX1_MASK (0xCU) +#define PUF_IDXBLK_L_IDX1_SHIFT (2U) +#define PUF_IDXBLK_L_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX1_SHIFT)) & PUF_IDXBLK_L_IDX1_MASK) +#define PUF_IDXBLK_L_IDX2_MASK (0x30U) +#define PUF_IDXBLK_L_IDX2_SHIFT (4U) +#define PUF_IDXBLK_L_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX2_SHIFT)) & PUF_IDXBLK_L_IDX2_MASK) +#define PUF_IDXBLK_L_IDX3_MASK (0xC0U) +#define PUF_IDXBLK_L_IDX3_SHIFT (6U) +#define PUF_IDXBLK_L_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX3_SHIFT)) & PUF_IDXBLK_L_IDX3_MASK) +#define PUF_IDXBLK_L_IDX4_MASK (0x300U) +#define PUF_IDXBLK_L_IDX4_SHIFT (8U) +#define PUF_IDXBLK_L_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX4_SHIFT)) & PUF_IDXBLK_L_IDX4_MASK) +#define PUF_IDXBLK_L_IDX5_MASK (0xC00U) +#define PUF_IDXBLK_L_IDX5_SHIFT (10U) +#define PUF_IDXBLK_L_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX5_SHIFT)) & PUF_IDXBLK_L_IDX5_MASK) +#define PUF_IDXBLK_L_IDX6_MASK (0x3000U) +#define PUF_IDXBLK_L_IDX6_SHIFT (12U) +#define PUF_IDXBLK_L_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX6_SHIFT)) & PUF_IDXBLK_L_IDX6_MASK) +#define PUF_IDXBLK_L_IDX7_MASK (0xC000U) +#define PUF_IDXBLK_L_IDX7_SHIFT (14U) +#define PUF_IDXBLK_L_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX7_SHIFT)) & PUF_IDXBLK_L_IDX7_MASK) +#define PUF_IDXBLK_L_LOCK_IDX_MASK (0xC0000000U) +#define PUF_IDXBLK_L_LOCK_IDX_SHIFT (30U) +#define PUF_IDXBLK_L_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_LOCK_IDX_SHIFT)) & PUF_IDXBLK_L_LOCK_IDX_MASK) +/*! @} */ + +/*! @name IDXBLK_H_DP - */ +/*! @{ */ +#define PUF_IDXBLK_H_DP_IDX8_MASK (0x3U) +#define PUF_IDXBLK_H_DP_IDX8_SHIFT (0U) +#define PUF_IDXBLK_H_DP_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX8_SHIFT)) & PUF_IDXBLK_H_DP_IDX8_MASK) +#define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) +#define PUF_IDXBLK_H_DP_IDX9_SHIFT (2U) +#define PUF_IDXBLK_H_DP_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK) +#define PUF_IDXBLK_H_DP_IDX10_MASK (0x30U) +#define PUF_IDXBLK_H_DP_IDX10_SHIFT (4U) +#define PUF_IDXBLK_H_DP_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX10_SHIFT)) & PUF_IDXBLK_H_DP_IDX10_MASK) +#define PUF_IDXBLK_H_DP_IDX11_MASK (0xC0U) +#define PUF_IDXBLK_H_DP_IDX11_SHIFT (6U) +#define PUF_IDXBLK_H_DP_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX11_SHIFT)) & PUF_IDXBLK_H_DP_IDX11_MASK) +#define PUF_IDXBLK_H_DP_IDX12_MASK (0x300U) +#define PUF_IDXBLK_H_DP_IDX12_SHIFT (8U) +#define PUF_IDXBLK_H_DP_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX12_SHIFT)) & PUF_IDXBLK_H_DP_IDX12_MASK) +#define PUF_IDXBLK_H_DP_IDX13_MASK (0xC00U) +#define PUF_IDXBLK_H_DP_IDX13_SHIFT (10U) +#define PUF_IDXBLK_H_DP_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX13_SHIFT)) & PUF_IDXBLK_H_DP_IDX13_MASK) +#define PUF_IDXBLK_H_DP_IDX14_MASK (0x3000U) +#define PUF_IDXBLK_H_DP_IDX14_SHIFT (12U) +#define PUF_IDXBLK_H_DP_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX14_SHIFT)) & PUF_IDXBLK_H_DP_IDX14_MASK) +#define PUF_IDXBLK_H_DP_IDX15_MASK (0xC000U) +#define PUF_IDXBLK_H_DP_IDX15_SHIFT (14U) +#define PUF_IDXBLK_H_DP_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX15_SHIFT)) & PUF_IDXBLK_H_DP_IDX15_MASK) +/*! @} */ + +/*! @name KEYMASK - Only reset in case of full IC reset */ +/*! @{ */ +#define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU) +#define PUF_KEYMASK_KEYMASK_SHIFT (0U) +#define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK) +/*! @} */ + +/* The count of PUF_KEYMASK */ +#define PUF_KEYMASK_COUNT (4U) + +/*! @name IDXBLK_H - */ +/*! @{ */ +#define PUF_IDXBLK_H_IDX8_MASK (0x3U) +#define PUF_IDXBLK_H_IDX8_SHIFT (0U) +#define PUF_IDXBLK_H_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX8_SHIFT)) & PUF_IDXBLK_H_IDX8_MASK) +#define PUF_IDXBLK_H_IDX9_MASK (0xCU) +#define PUF_IDXBLK_H_IDX9_SHIFT (2U) +#define PUF_IDXBLK_H_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX9_SHIFT)) & PUF_IDXBLK_H_IDX9_MASK) +#define PUF_IDXBLK_H_IDX10_MASK (0x30U) +#define PUF_IDXBLK_H_IDX10_SHIFT (4U) +#define PUF_IDXBLK_H_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX10_SHIFT)) & PUF_IDXBLK_H_IDX10_MASK) +#define PUF_IDXBLK_H_IDX11_MASK (0xC0U) +#define PUF_IDXBLK_H_IDX11_SHIFT (6U) +#define PUF_IDXBLK_H_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX11_SHIFT)) & PUF_IDXBLK_H_IDX11_MASK) +#define PUF_IDXBLK_H_IDX12_MASK (0x300U) +#define PUF_IDXBLK_H_IDX12_SHIFT (8U) +#define PUF_IDXBLK_H_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX12_SHIFT)) & PUF_IDXBLK_H_IDX12_MASK) +#define PUF_IDXBLK_H_IDX13_MASK (0xC00U) +#define PUF_IDXBLK_H_IDX13_SHIFT (10U) +#define PUF_IDXBLK_H_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX13_SHIFT)) & PUF_IDXBLK_H_IDX13_MASK) +#define PUF_IDXBLK_H_IDX14_MASK (0x3000U) +#define PUF_IDXBLK_H_IDX14_SHIFT (12U) +#define PUF_IDXBLK_H_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX14_SHIFT)) & PUF_IDXBLK_H_IDX14_MASK) +#define PUF_IDXBLK_H_IDX15_MASK (0xC000U) +#define PUF_IDXBLK_H_IDX15_SHIFT (14U) +#define PUF_IDXBLK_H_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX15_SHIFT)) & PUF_IDXBLK_H_IDX15_MASK) +#define PUF_IDXBLK_H_LOCK_IDX_MASK (0xC0000000U) +#define PUF_IDXBLK_H_LOCK_IDX_SHIFT (30U) +#define PUF_IDXBLK_H_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_LOCK_IDX_SHIFT)) & PUF_IDXBLK_H_LOCK_IDX_MASK) +/*! @} */ + +/*! @name IDXBLK_L_DP - */ +/*! @{ */ +#define PUF_IDXBLK_L_DP_IDX1_MASK (0xCU) +#define PUF_IDXBLK_L_DP_IDX1_SHIFT (2U) +#define PUF_IDXBLK_L_DP_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX1_SHIFT)) & PUF_IDXBLK_L_DP_IDX1_MASK) +#define PUF_IDXBLK_L_DP_IDX2_MASK (0x30U) +#define PUF_IDXBLK_L_DP_IDX2_SHIFT (4U) +#define PUF_IDXBLK_L_DP_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX2_SHIFT)) & PUF_IDXBLK_L_DP_IDX2_MASK) +#define PUF_IDXBLK_L_DP_IDX3_MASK (0xC0U) +#define PUF_IDXBLK_L_DP_IDX3_SHIFT (6U) +#define PUF_IDXBLK_L_DP_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX3_SHIFT)) & PUF_IDXBLK_L_DP_IDX3_MASK) +#define PUF_IDXBLK_L_DP_IDX4_MASK (0x300U) +#define PUF_IDXBLK_L_DP_IDX4_SHIFT (8U) +#define PUF_IDXBLK_L_DP_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX4_SHIFT)) & PUF_IDXBLK_L_DP_IDX4_MASK) +#define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) +#define PUF_IDXBLK_L_DP_IDX5_SHIFT (10U) +#define PUF_IDXBLK_L_DP_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK) +#define PUF_IDXBLK_L_DP_IDX6_MASK (0x3000U) +#define PUF_IDXBLK_L_DP_IDX6_SHIFT (12U) +#define PUF_IDXBLK_L_DP_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX6_SHIFT)) & PUF_IDXBLK_L_DP_IDX6_MASK) +#define PUF_IDXBLK_L_DP_IDX7_MASK (0xC000U) +#define PUF_IDXBLK_L_DP_IDX7_SHIFT (14U) +#define PUF_IDXBLK_L_DP_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX7_SHIFT)) & PUF_IDXBLK_L_DP_IDX7_MASK) +/*! @} */ + +/*! @name SHIFT_STATUS - */ +/*! @{ */ +#define PUF_SHIFT_STATUS_KEY0_MASK (0xFU) +#define PUF_SHIFT_STATUS_KEY0_SHIFT (0U) +#define PUF_SHIFT_STATUS_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY0_SHIFT)) & PUF_SHIFT_STATUS_KEY0_MASK) +#define PUF_SHIFT_STATUS_KEY1_MASK (0xF0U) +#define PUF_SHIFT_STATUS_KEY1_SHIFT (4U) +#define PUF_SHIFT_STATUS_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY1_SHIFT)) & PUF_SHIFT_STATUS_KEY1_MASK) +#define PUF_SHIFT_STATUS_KEY2_MASK (0xF00U) +#define PUF_SHIFT_STATUS_KEY2_SHIFT (8U) +#define PUF_SHIFT_STATUS_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY2_SHIFT)) & PUF_SHIFT_STATUS_KEY2_MASK) +#define PUF_SHIFT_STATUS_KEY3_MASK (0xF000U) +#define PUF_SHIFT_STATUS_KEY3_SHIFT (12U) +#define PUF_SHIFT_STATUS_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY3_SHIFT)) & PUF_SHIFT_STATUS_KEY3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PUF_Register_Masks */ + + +/* PUF - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5003B000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4003B000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4003B000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF } +#endif +/** Interrupt vectors for the PUF peripheral type */ +#define PUF_IRQS { PUF_IRQn } + +/*! + * @} + */ /* end of group PUF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RNG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer + * @{ + */ + +/** RNG - Register Layout Typedef */ +typedef struct { + __I uint32_t RANDOM_NUMBER; /**< This register contains a random 32 bit number which is computed on demand, at each time it is read, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __I uint32_t COUNTER_VAL; /**< , offset: 0x8 */ + __IO uint32_t COUNTER_CFG; /**< , offset: 0xC */ + __IO uint32_t ONLINE_TEST_CFG; /**< , offset: 0x10 */ + __I uint32_t ONLINE_TEST_VAL; /**< , offset: 0x14 */ + uint8_t RESERVED_1[4068]; + __I uint32_t MODULEID; /**< IP identifier, offset: 0xFFC */ +} RNG_Type; + +/* ---------------------------------------------------------------------------- + -- RNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Register_Masks RNG Register Masks + * @{ + */ + +/*! @name RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read */ +/*! @{ */ +#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK (0xFFFFFFFFU) +#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT (0U) +#define RNG_RANDOM_NUMBER_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT)) & RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK) +/*! @} */ + +/*! @name COUNTER_VAL - */ +/*! @{ */ +#define RNG_COUNTER_VAL_CLK_RATIO_MASK (0xFFU) +#define RNG_COUNTER_VAL_CLK_RATIO_SHIFT (0U) +#define RNG_COUNTER_VAL_CLK_RATIO(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_CLK_RATIO_SHIFT)) & RNG_COUNTER_VAL_CLK_RATIO_MASK) +#define RNG_COUNTER_VAL_REFRESH_CNT_MASK (0x1F00U) +#define RNG_COUNTER_VAL_REFRESH_CNT_SHIFT (8U) +#define RNG_COUNTER_VAL_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_REFRESH_CNT_SHIFT)) & RNG_COUNTER_VAL_REFRESH_CNT_MASK) +/*! @} */ + +/*! @name COUNTER_CFG - */ +/*! @{ */ +#define RNG_COUNTER_CFG_MODE_MASK (0x3U) +#define RNG_COUNTER_CFG_MODE_SHIFT (0U) +#define RNG_COUNTER_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_MODE_SHIFT)) & RNG_COUNTER_CFG_MODE_MASK) +#define RNG_COUNTER_CFG_CLOCK_SEL_MASK (0x1CU) +#define RNG_COUNTER_CFG_CLOCK_SEL_SHIFT (2U) +#define RNG_COUNTER_CFG_CLOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_CLOCK_SEL_SHIFT)) & RNG_COUNTER_CFG_CLOCK_SEL_MASK) +#define RNG_COUNTER_CFG_SHIFT4X_MASK (0xE0U) +#define RNG_COUNTER_CFG_SHIFT4X_SHIFT (5U) +#define RNG_COUNTER_CFG_SHIFT4X(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_SHIFT4X_SHIFT)) & RNG_COUNTER_CFG_SHIFT4X_MASK) +/*! @} */ + +/*! @name ONLINE_TEST_CFG - */ +/*! @{ */ +#define RNG_ONLINE_TEST_CFG_ACTIVATE_MASK (0x1U) +#define RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT (0U) +#define RNG_ONLINE_TEST_CFG_ACTIVATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT)) & RNG_ONLINE_TEST_CFG_ACTIVATE_MASK) +#define RNG_ONLINE_TEST_CFG_DATA_SEL_MASK (0x6U) +#define RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT (1U) +#define RNG_ONLINE_TEST_CFG_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT)) & RNG_ONLINE_TEST_CFG_DATA_SEL_MASK) +/*! @} */ + +/*! @name ONLINE_TEST_VAL - */ +/*! @{ */ +#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK (0xFU) +#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT (0U) +#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK) +#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK (0xF0U) +#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT (4U) +#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) +#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK (0xF00U) +#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT (8U) +#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) +/*! @} */ + +/*! @name MODULEID - IP identifier */ +/*! @{ */ +#define RNG_MODULEID_APERTURE_MASK (0xFFU) +#define RNG_MODULEID_APERTURE_SHIFT (0U) +#define RNG_MODULEID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_APERTURE_SHIFT)) & RNG_MODULEID_APERTURE_MASK) +#define RNG_MODULEID_MIN_REV_MASK (0xF00U) +#define RNG_MODULEID_MIN_REV_SHIFT (8U) +#define RNG_MODULEID_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MIN_REV_SHIFT)) & RNG_MODULEID_MIN_REV_MASK) +#define RNG_MODULEID_MAJ_REV_MASK (0xF000U) +#define RNG_MODULEID_MAJ_REV_SHIFT (12U) +#define RNG_MODULEID_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MAJ_REV_SHIFT)) & RNG_MODULEID_MAJ_REV_MASK) +#define RNG_MODULEID_ID_MASK (0xFFFF0000U) +#define RNG_MODULEID_ID_SHIFT (16U) +#define RNG_MODULEID_ID(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_ID_SHIFT)) & RNG_MODULEID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RNG_Register_Masks */ + + +/* RNG - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral RNG base address */ + #define RNG_BASE (0x5003A000u) + /** Peripheral RNG base address */ + #define RNG_BASE_NS (0x4003A000u) + /** Peripheral RNG base pointer */ + #define RNG ((RNG_Type *)RNG_BASE) + /** Peripheral RNG base pointer */ + #define RNG_NS ((RNG_Type *)RNG_BASE_NS) + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS { RNG_BASE } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS { RNG } + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS_NS { RNG_BASE_NS } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS_NS { RNG_NS } +#else + /** Peripheral RNG base address */ + #define RNG_BASE (0x4003A000u) + /** Peripheral RNG base pointer */ + #define RNG ((RNG_Type *)RNG_BASE) + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS { RNG_BASE } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS { RNG } +#endif + +/*! + * @} + */ /* end of group RNG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ + __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ + __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ + __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ + __I uint32_t SUBSEC; /**< Sub-second counter register, offset: 0x10 */ + uint8_t RESERVED_0[44]; + __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/*! @name CTRL - RTC control register */ +/*! @{ */ +#define RTC_CTRL_SWRESET_MASK (0x1U) +#define RTC_CTRL_SWRESET_SHIFT (0U) +/*! SWRESET - Software reset control + * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. + * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value + * except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes + * to set any of the other bits within this register. Do not attempt to write to any bits of this register at + * the same time that the reset bit is being cleared. + */ +#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) +#define RTC_CTRL_ALARM1HZ_MASK (0x4U) +#define RTC_CTRL_ALARM1HZ_SHIFT (2U) +/*! ALARM1HZ - RTC 1 Hz timer alarm flag status. + * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. + * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt + * request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. + */ +#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) +#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) +#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) +/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status. + * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. + * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up + * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. + */ +#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) +#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) +#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) +/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. + * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. + */ +#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) +#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) +#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) +/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. + * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. + */ +#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) +#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) +#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) +/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz + * timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). + * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. The 1 kHz RTC timer is enabled. + */ +#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) +#define RTC_CTRL_RTC_EN_MASK (0x80U) +#define RTC_CTRL_RTC_EN_SHIFT (7U) +/*! RTC_EN - RTC enable. + * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should + * be 0 when writing to load a value in the RTC counter register. + * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate + * operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the + * high-resolution, 1 kHz clock, set bit 6 in this register. + */ +#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) +#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) +#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) +/*! RTC_OSC_PD - RTC oscillator power-down control. + * 0b0..See RTC_OSC_BYPASS + * 0b1..RTC oscillator is powered-down. + */ +#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) +#define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) +#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) +/*! RTC_OSC_BYPASS - RTC oscillator bypass control. + * 0b0..The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. + * 0b1..The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. + */ +#define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) +#define RTC_CTRL_RTC_SUBSEC_ENA_MASK (0x400U) +#define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT (10U) +/*! RTC_SUBSEC_ENA - RTC Sub-second counter control. + * 0b0..The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD + * reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second + * counter, this bit will always read-back as a '0'. + * 0b1..The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first + * one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is + * set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip + * exits deep power-down mode. + */ +#define RTC_CTRL_RTC_SUBSEC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK) +/*! @} */ + +/*! @name MATCH - RTC match register */ +/*! @{ */ +#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) +#define RTC_MATCH_MATVAL_SHIFT (0U) +#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) +/*! @} */ + +/*! @name COUNT - RTC counter register */ +/*! @{ */ +#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) +#define RTC_COUNT_VAL_SHIFT (0U) +#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) +/*! @} */ + +/*! @name WAKE - High-resolution/wake-up timer control register */ +/*! @{ */ +#define RTC_WAKE_VAL_MASK (0xFFFFU) +#define RTC_WAKE_VAL_SHIFT (0U) +#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) +/*! @} */ + +/*! @name SUBSEC - Sub-second counter register */ +/*! @{ */ +#define RTC_SUBSEC_SUBSEC_MASK (0x7FFFU) +#define RTC_SUBSEC_SUBSEC_SHIFT (0U) +#define RTC_SUBSEC_SUBSEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_SUBSEC_SHIFT)) & RTC_SUBSEC_SUBSEC_MASK) +/*! @} */ + +/*! @name GPREG - General Purpose register */ +/*! @{ */ +#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU) +#define RTC_GPREG_GPDATA_SHIFT (0U) +#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK) +/*! @} */ + +/* The count of RTC_GPREG */ +#define RTC_GPREG_COUNT (8U) + + +/*! + * @} + */ /* end of group RTC_Register_Masks */ + + +/* RTC - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral RTC base address */ + #define RTC_BASE (0x5002C000u) + /** Peripheral RTC base address */ + #define RTC_BASE_NS (0x4002C000u) + /** Peripheral RTC base pointer */ + #define RTC ((RTC_Type *)RTC_BASE) + /** Peripheral RTC base pointer */ + #define RTC_NS ((RTC_Type *)RTC_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC_NS } +#else + /** Peripheral RTC base address */ + #define RTC_BASE (0x4002C000u) + /** Peripheral RTC base pointer */ + #define RTC ((RTC_Type *)RTC_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SCT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer + * @{ + */ + +/** SCT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ + __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ + __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ + __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ + __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ + __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ + uint8_t RESERVED_0[40]; + __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ + __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ + __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ + __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ + __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ + __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ + __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ + __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */ + __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */ + uint8_t RESERVED_1[140]; + __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ + __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ + __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ + __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ + union { /* offset: 0x100 */ + __IO uint32_t CAP[16]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ + __IO uint32_t MATCH[16]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ + }; + uint8_t RESERVED_2[192]; + union { /* offset: 0x200 */ + __IO uint32_t CAPCTRL[16]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ + __IO uint32_t MATCHREL[16]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ + }; + uint8_t RESERVED_3[192]; + struct { /* offset: 0x300, array step: 0x8 */ + __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ + __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ + } EV[16]; + uint8_t RESERVED_4[384]; + struct { /* offset: 0x500, array step: 0x8 */ + __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ + __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ + } OUT[10]; +} SCT_Type; + +/* ---------------------------------------------------------------------------- + -- SCT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Register_Masks SCT Register Masks + * @{ + */ + +/*! @name CONFIG - SCT configuration register */ +/*! @{ */ +#define SCT_CONFIG_UNIFY_MASK (0x1U) +#define SCT_CONFIG_UNIFY_SHIFT (0U) +/*! UNIFY - SCT operation + * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. + * 0b1..The SCT operates as a unified 32-bit counter. + */ +#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) +#define SCT_CONFIG_CLKMODE_MASK (0x6U) +#define SCT_CONFIG_CLKMODE_SHIFT (1U) +/*! CLKMODE - SCT clock mode + * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. + * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are + * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The + * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the + * high-performance, sampled-clock mode. + * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the + * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the + * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. + * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL + * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system + * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than + * the system clock. + */ +#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) +#define SCT_CONFIG_CKSEL_MASK (0x78U) +#define SCT_CONFIG_CKSEL_SHIFT (3U) +/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent + * on the CLKMODE bit selection in this register. + * 0b0000..Rising edges on input 0. + * 0b0001..Falling edges on input 0. + * 0b0010..Rising edges on input 1. + * 0b0011..Falling edges on input 1. + * 0b0100..Rising edges on input 2. + * 0b0101..Falling edges on input 2. + * 0b0110..Rising edges on input 3. + * 0b0111..Falling edges on input 3. + * 0b1000..Rising edges on input 4. + * 0b1001..Falling edges on input 4. + * 0b1010..Rising edges on input 5. + * 0b1011..Falling edges on input 5. + * 0b1100..Rising edges on input 6. + * 0b1101..Falling edges on input 6. + * 0b1110..Rising edges on input 7. + * 0b1111..Falling edges on input 7. + */ +#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) +#define SCT_CONFIG_NORELOAD_L_MASK (0x80U) +#define SCT_CONFIG_NORELOAD_L_SHIFT (7U) +#define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK) +#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) +#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) +#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) +#define SCT_CONFIG_INSYNC_MASK (0x1E00U) +#define SCT_CONFIG_INSYNC_SHIFT (9U) +#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) +#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) +#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) +#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) +#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) +#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) +#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) +/*! @} */ + +/*! @name CTRL - SCT control register */ +/*! @{ */ +#define SCT_CTRL_DOWN_L_MASK (0x1U) +#define SCT_CTRL_DOWN_L_SHIFT (0U) +#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) +#define SCT_CTRL_STOP_L_MASK (0x2U) +#define SCT_CTRL_STOP_L_SHIFT (1U) +#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) +#define SCT_CTRL_HALT_L_MASK (0x4U) +#define SCT_CTRL_HALT_L_SHIFT (2U) +#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) +#define SCT_CTRL_CLRCTR_L_MASK (0x8U) +#define SCT_CTRL_CLRCTR_L_SHIFT (3U) +#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) +#define SCT_CTRL_BIDIR_L_MASK (0x10U) +#define SCT_CTRL_BIDIR_L_SHIFT (4U) +/*! BIDIR_L - L or unified counter direction select + * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. + * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) +#define SCT_CTRL_PRE_L_MASK (0x1FE0U) +#define SCT_CTRL_PRE_L_SHIFT (5U) +#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) +#define SCT_CTRL_DOWN_H_MASK (0x10000U) +#define SCT_CTRL_DOWN_H_SHIFT (16U) +#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) +#define SCT_CTRL_STOP_H_MASK (0x20000U) +#define SCT_CTRL_STOP_H_SHIFT (17U) +#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) +#define SCT_CTRL_HALT_H_MASK (0x40000U) +#define SCT_CTRL_HALT_H_SHIFT (18U) +#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) +#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) +#define SCT_CTRL_CLRCTR_H_SHIFT (19U) +#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) +#define SCT_CTRL_BIDIR_H_MASK (0x100000U) +#define SCT_CTRL_BIDIR_H_SHIFT (20U) +/*! BIDIR_H - Direction select + * 0b0..The H counter counts up to its limit condition, then is cleared to zero. + * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) +#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) +#define SCT_CTRL_PRE_H_SHIFT (21U) +#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) +/*! @} */ + +/*! @name LIMIT - SCT limit event select register */ +/*! @{ */ +#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) +#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) +#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) +#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) +#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) +#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) +/*! @} */ + +/*! @name HALT - SCT halt event select register */ +/*! @{ */ +#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) +#define SCT_HALT_HALTMSK_L_SHIFT (0U) +#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) +#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) +#define SCT_HALT_HALTMSK_H_SHIFT (16U) +#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) +/*! @} */ + +/*! @name STOP - SCT stop event select register */ +/*! @{ */ +#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) +#define SCT_STOP_STOPMSK_L_SHIFT (0U) +#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) +#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) +#define SCT_STOP_STOPMSK_H_SHIFT (16U) +#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) +/*! @} */ + +/*! @name START - SCT start event select register */ +/*! @{ */ +#define SCT_START_STARTMSK_L_MASK (0xFFFFU) +#define SCT_START_STARTMSK_L_SHIFT (0U) +#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) +#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) +#define SCT_START_STARTMSK_H_SHIFT (16U) +#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) +/*! @} */ + +/*! @name COUNT - SCT counter register */ +/*! @{ */ +#define SCT_COUNT_CTR_L_MASK (0xFFFFU) +#define SCT_COUNT_CTR_L_SHIFT (0U) +#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) +#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) +#define SCT_COUNT_CTR_H_SHIFT (16U) +#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) +/*! @} */ + +/*! @name STATE - SCT state register */ +/*! @{ */ +#define SCT_STATE_STATE_L_MASK (0x1FU) +#define SCT_STATE_STATE_L_SHIFT (0U) +#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) +#define SCT_STATE_STATE_H_MASK (0x1F0000U) +#define SCT_STATE_STATE_H_SHIFT (16U) +#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) +/*! @} */ + +/*! @name INPUT - SCT input register */ +/*! @{ */ +#define SCT_INPUT_AIN0_MASK (0x1U) +#define SCT_INPUT_AIN0_SHIFT (0U) +#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) +#define SCT_INPUT_AIN1_MASK (0x2U) +#define SCT_INPUT_AIN1_SHIFT (1U) +#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) +#define SCT_INPUT_AIN2_MASK (0x4U) +#define SCT_INPUT_AIN2_SHIFT (2U) +#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) +#define SCT_INPUT_AIN3_MASK (0x8U) +#define SCT_INPUT_AIN3_SHIFT (3U) +#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) +#define SCT_INPUT_AIN4_MASK (0x10U) +#define SCT_INPUT_AIN4_SHIFT (4U) +#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) +#define SCT_INPUT_AIN5_MASK (0x20U) +#define SCT_INPUT_AIN5_SHIFT (5U) +#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) +#define SCT_INPUT_AIN6_MASK (0x40U) +#define SCT_INPUT_AIN6_SHIFT (6U) +#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) +#define SCT_INPUT_AIN7_MASK (0x80U) +#define SCT_INPUT_AIN7_SHIFT (7U) +#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) +#define SCT_INPUT_AIN8_MASK (0x100U) +#define SCT_INPUT_AIN8_SHIFT (8U) +#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) +#define SCT_INPUT_AIN9_MASK (0x200U) +#define SCT_INPUT_AIN9_SHIFT (9U) +#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) +#define SCT_INPUT_AIN10_MASK (0x400U) +#define SCT_INPUT_AIN10_SHIFT (10U) +#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) +#define SCT_INPUT_AIN11_MASK (0x800U) +#define SCT_INPUT_AIN11_SHIFT (11U) +#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) +#define SCT_INPUT_AIN12_MASK (0x1000U) +#define SCT_INPUT_AIN12_SHIFT (12U) +#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) +#define SCT_INPUT_AIN13_MASK (0x2000U) +#define SCT_INPUT_AIN13_SHIFT (13U) +#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) +#define SCT_INPUT_AIN14_MASK (0x4000U) +#define SCT_INPUT_AIN14_SHIFT (14U) +#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) +#define SCT_INPUT_AIN15_MASK (0x8000U) +#define SCT_INPUT_AIN15_SHIFT (15U) +#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) +#define SCT_INPUT_SIN0_MASK (0x10000U) +#define SCT_INPUT_SIN0_SHIFT (16U) +#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) +#define SCT_INPUT_SIN1_MASK (0x20000U) +#define SCT_INPUT_SIN1_SHIFT (17U) +#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) +#define SCT_INPUT_SIN2_MASK (0x40000U) +#define SCT_INPUT_SIN2_SHIFT (18U) +#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) +#define SCT_INPUT_SIN3_MASK (0x80000U) +#define SCT_INPUT_SIN3_SHIFT (19U) +#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) +#define SCT_INPUT_SIN4_MASK (0x100000U) +#define SCT_INPUT_SIN4_SHIFT (20U) +#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) +#define SCT_INPUT_SIN5_MASK (0x200000U) +#define SCT_INPUT_SIN5_SHIFT (21U) +#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) +#define SCT_INPUT_SIN6_MASK (0x400000U) +#define SCT_INPUT_SIN6_SHIFT (22U) +#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) +#define SCT_INPUT_SIN7_MASK (0x800000U) +#define SCT_INPUT_SIN7_SHIFT (23U) +#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) +#define SCT_INPUT_SIN8_MASK (0x1000000U) +#define SCT_INPUT_SIN8_SHIFT (24U) +#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) +#define SCT_INPUT_SIN9_MASK (0x2000000U) +#define SCT_INPUT_SIN9_SHIFT (25U) +#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) +#define SCT_INPUT_SIN10_MASK (0x4000000U) +#define SCT_INPUT_SIN10_SHIFT (26U) +#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) +#define SCT_INPUT_SIN11_MASK (0x8000000U) +#define SCT_INPUT_SIN11_SHIFT (27U) +#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) +#define SCT_INPUT_SIN12_MASK (0x10000000U) +#define SCT_INPUT_SIN12_SHIFT (28U) +#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) +#define SCT_INPUT_SIN13_MASK (0x20000000U) +#define SCT_INPUT_SIN13_SHIFT (29U) +#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) +#define SCT_INPUT_SIN14_MASK (0x40000000U) +#define SCT_INPUT_SIN14_SHIFT (30U) +#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) +#define SCT_INPUT_SIN15_MASK (0x80000000U) +#define SCT_INPUT_SIN15_SHIFT (31U) +#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) +/*! @} */ + +/*! @name REGMODE - SCT match/capture mode register */ +/*! @{ */ +#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) +#define SCT_REGMODE_REGMOD_L_SHIFT (0U) +#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) +#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) +#define SCT_REGMODE_REGMOD_H_SHIFT (16U) +#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) +/*! @} */ + +/*! @name OUTPUT - SCT output register */ +/*! @{ */ +#define SCT_OUTPUT_OUT_MASK (0xFFFFU) +#define SCT_OUTPUT_OUT_SHIFT (0U) +#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) +/*! @} */ + +/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ +/*! @{ */ +#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) +#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) +/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) +#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) +/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) +#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) +/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) +#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) +/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) +#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) +/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) +#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) +/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) +#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) +/*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) +#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) +/*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) +#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) +/*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) +#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) +/*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) +#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) +/*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) +#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) +/*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) +/*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) +/*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) +/*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) +/*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) +/*! @} */ + +/*! @name RES - SCT conflict resolution register */ +/*! @{ */ +#define SCT_RES_O0RES_MASK (0x3U) +#define SCT_RES_O0RES_SHIFT (0U) +/*! O0RES - Effect of simultaneous set and clear on output 0. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR0 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) +#define SCT_RES_O1RES_MASK (0xCU) +#define SCT_RES_O1RES_SHIFT (2U) +/*! O1RES - Effect of simultaneous set and clear on output 1. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR1 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) +#define SCT_RES_O2RES_MASK (0x30U) +#define SCT_RES_O2RES_SHIFT (4U) +/*! O2RES - Effect of simultaneous set and clear on output 2. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output n (or set based on the SETCLR2 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) +#define SCT_RES_O3RES_MASK (0xC0U) +#define SCT_RES_O3RES_SHIFT (6U) +/*! O3RES - Effect of simultaneous set and clear on output 3. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR3 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) +#define SCT_RES_O4RES_MASK (0x300U) +#define SCT_RES_O4RES_SHIFT (8U) +/*! O4RES - Effect of simultaneous set and clear on output 4. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR4 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) +#define SCT_RES_O5RES_MASK (0xC00U) +#define SCT_RES_O5RES_SHIFT (10U) +/*! O5RES - Effect of simultaneous set and clear on output 5. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR5 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) +#define SCT_RES_O6RES_MASK (0x3000U) +#define SCT_RES_O6RES_SHIFT (12U) +/*! O6RES - Effect of simultaneous set and clear on output 6. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR6 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) +#define SCT_RES_O7RES_MASK (0xC000U) +#define SCT_RES_O7RES_SHIFT (14U) +/*! O7RES - Effect of simultaneous set and clear on output 7. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output n (or set based on the SETCLR7 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) +#define SCT_RES_O8RES_MASK (0x30000U) +#define SCT_RES_O8RES_SHIFT (16U) +/*! O8RES - Effect of simultaneous set and clear on output 8. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR8 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) +#define SCT_RES_O9RES_MASK (0xC0000U) +#define SCT_RES_O9RES_SHIFT (18U) +/*! O9RES - Effect of simultaneous set and clear on output 9. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR9 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) +#define SCT_RES_O10RES_MASK (0x300000U) +#define SCT_RES_O10RES_SHIFT (20U) +/*! O10RES - Effect of simultaneous set and clear on output 10. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR10 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) +#define SCT_RES_O11RES_MASK (0xC00000U) +#define SCT_RES_O11RES_SHIFT (22U) +/*! O11RES - Effect of simultaneous set and clear on output 11. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR11 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) +#define SCT_RES_O12RES_MASK (0x3000000U) +#define SCT_RES_O12RES_SHIFT (24U) +/*! O12RES - Effect of simultaneous set and clear on output 12. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR12 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) +#define SCT_RES_O13RES_MASK (0xC000000U) +#define SCT_RES_O13RES_SHIFT (26U) +/*! O13RES - Effect of simultaneous set and clear on output 13. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR13 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) +#define SCT_RES_O14RES_MASK (0x30000000U) +#define SCT_RES_O14RES_SHIFT (28U) +/*! O14RES - Effect of simultaneous set and clear on output 14. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR14 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) +#define SCT_RES_O15RES_MASK (0xC0000000U) +#define SCT_RES_O15RES_SHIFT (30U) +/*! O15RES - Effect of simultaneous set and clear on output 15. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR15 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) +/*! @} */ + +/*! @name DMAREQ0 - SCT DMA request 0 register */ +/*! @{ */ +#define SCT_DMAREQ0_DEV_0_MASK (0xFFFFU) +#define SCT_DMAREQ0_DEV_0_SHIFT (0U) +#define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK) +#define SCT_DMAREQ0_DRL0_MASK (0x40000000U) +#define SCT_DMAREQ0_DRL0_SHIFT (30U) +#define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK) +#define SCT_DMAREQ0_DRQ0_MASK (0x80000000U) +#define SCT_DMAREQ0_DRQ0_SHIFT (31U) +#define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK) +/*! @} */ + +/*! @name DMAREQ1 - SCT DMA request 1 register */ +/*! @{ */ +#define SCT_DMAREQ1_DEV_1_MASK (0xFFFFU) +#define SCT_DMAREQ1_DEV_1_SHIFT (0U) +#define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK) +#define SCT_DMAREQ1_DRL1_MASK (0x40000000U) +#define SCT_DMAREQ1_DRL1_SHIFT (30U) +#define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK) +#define SCT_DMAREQ1_DRQ1_MASK (0x80000000U) +#define SCT_DMAREQ1_DRQ1_SHIFT (31U) +#define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK) +/*! @} */ + +/*! @name EVEN - SCT event interrupt enable register */ +/*! @{ */ +#define SCT_EVEN_IEN_MASK (0xFFFFU) +#define SCT_EVEN_IEN_SHIFT (0U) +#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) +/*! @} */ + +/*! @name EVFLAG - SCT event flag register */ +/*! @{ */ +#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) +#define SCT_EVFLAG_FLAG_SHIFT (0U) +#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) +/*! @} */ + +/*! @name CONEN - SCT conflict interrupt enable register */ +/*! @{ */ +#define SCT_CONEN_NCEN_MASK (0xFFFFU) +#define SCT_CONEN_NCEN_SHIFT (0U) +#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) +/*! @} */ + +/*! @name CONFLAG - SCT conflict flag register */ +/*! @{ */ +#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) +#define SCT_CONFLAG_NCFLAG_SHIFT (0U) +#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) +#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) +#define SCT_CONFLAG_BUSERRL_SHIFT (30U) +#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) +#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) +#define SCT_CONFLAG_BUSERRH_SHIFT (31U) +#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) +/*! @} */ + +/*! @name CAP - SCT capture register of capture channel */ +/*! @{ */ +#define SCT_CAP_CAPn_L_MASK (0xFFFFU) +#define SCT_CAP_CAPn_L_SHIFT (0U) +#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK) +#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U) +#define SCT_CAP_CAPn_H_SHIFT (16U) +#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK) +/*! @} */ + +/* The count of SCT_CAP */ +#define SCT_CAP_COUNT (16U) + +/*! @name MATCH - SCT match value register of match channels */ +/*! @{ */ +#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU) +#define SCT_MATCH_MATCHn_L_SHIFT (0U) +#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK) +#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U) +#define SCT_MATCH_MATCHn_H_SHIFT (16U) +#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK) +/*! @} */ + +/* The count of SCT_MATCH */ +#define SCT_MATCH_COUNT (16U) + +/*! @name CAPCTRL - SCT capture control register */ +/*! @{ */ +#define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU) +#define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U) +#define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK) +#define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) +#define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U) +#define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK) +/*! @} */ + +/* The count of SCT_CAPCTRL */ +#define SCT_CAPCTRL_COUNT (16U) + +/*! @name MATCHREL - SCT match reload value register */ +/*! @{ */ +#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU) +#define SCT_MATCHREL_RELOADn_L_SHIFT (0U) +#define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK) +#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U) +#define SCT_MATCHREL_RELOADn_H_SHIFT (16U) +#define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK) +/*! @} */ + +/* The count of SCT_MATCHREL */ +#define SCT_MATCHREL_COUNT (16U) + +/*! @name EV_STATE - SCT event state register 0 */ +/*! @{ */ +#define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFU) +#define SCT_EV_STATE_STATEMSKn_SHIFT (0U) +#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK) +/*! @} */ + +/* The count of SCT_EV_STATE */ +#define SCT_EV_STATE_COUNT (16U) + +/*! @name EV_CTRL - SCT event control register 0 */ +/*! @{ */ +#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU) +#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U) +#define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK) +#define SCT_EV_CTRL_HEVENT_MASK (0x10U) +#define SCT_EV_CTRL_HEVENT_SHIFT (4U) +/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. + * 0b0..Selects the L state and the L match register selected by MATCHSEL. + * 0b1..Selects the H state and the H match register selected by MATCHSEL. + */ +#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK) +#define SCT_EV_CTRL_OUTSEL_MASK (0x20U) +#define SCT_EV_CTRL_OUTSEL_SHIFT (5U) +/*! OUTSEL - Input/output select + * 0b0..Selects the inputs selected by IOSEL. + * 0b1..Selects the outputs selected by IOSEL. + */ +#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK) +#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U) +#define SCT_EV_CTRL_IOSEL_SHIFT (6U) +#define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK) +#define SCT_EV_CTRL_IOCOND_MASK (0xC00U) +#define SCT_EV_CTRL_IOCOND_SHIFT (10U) +/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the + * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state + * detection, an input must have a minimum pulse width of at least one SCT clock period . + * 0b00..LOW + * 0b01..Rise + * 0b10..Fall + * 0b11..HIGH + */ +#define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK) +#define SCT_EV_CTRL_COMBMODE_MASK (0x3000U) +#define SCT_EV_CTRL_COMBMODE_SHIFT (12U) +/*! COMBMODE - Selects how the specified match and I/O condition are used and combined. + * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. + * 0b01..MATCH. Uses the specified match only. + * 0b10..IO. Uses the specified I/O condition only. + * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. + */ +#define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK) +#define SCT_EV_CTRL_STATELD_MASK (0x4000U) +#define SCT_EV_CTRL_STATELD_SHIFT (14U) +/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this + * event is the highest-numbered event occurring for that state. + * 0b0..STATEV value is added into STATE (the carry-out is ignored). + * 0b1..STATEV value is loaded into STATE. + */ +#define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK) +#define SCT_EV_CTRL_STATEV_MASK (0xF8000U) +#define SCT_EV_CTRL_STATEV_SHIFT (15U) +#define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK) +#define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U) +#define SCT_EV_CTRL_MATCHMEM_SHIFT (20U) +#define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK) +#define SCT_EV_CTRL_DIRECTION_MASK (0x600000U) +#define SCT_EV_CTRL_DIRECTION_SHIFT (21U) +/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters + * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. + * 0b00..Direction independent. This event is triggered regardless of the count direction. + * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. + * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. + */ +#define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK) +/*! @} */ + +/* The count of SCT_EV_CTRL */ +#define SCT_EV_CTRL_COUNT (16U) + +/*! @name OUT_SET - SCT output 0 set register */ +/*! @{ */ +#define SCT_OUT_SET_SET_MASK (0xFFFFU) +#define SCT_OUT_SET_SET_SHIFT (0U) +#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) +/*! @} */ + +/* The count of SCT_OUT_SET */ +#define SCT_OUT_SET_COUNT (10U) + +/*! @name OUT_CLR - SCT output 0 clear register */ +/*! @{ */ +#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) +#define SCT_OUT_CLR_CLR_SHIFT (0U) +#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) +/*! @} */ + +/* The count of SCT_OUT_CLR */ +#define SCT_OUT_CLR_COUNT (10U) + + +/*! + * @} + */ /* end of group SCT_Register_Masks */ + + +/* SCT - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x50085000u) + /** Peripheral SCT0 base address */ + #define SCT0_BASE_NS (0x40085000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Peripheral SCT0 base pointer */ + #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS_NS { SCT0_NS } +#else + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x40085000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } +#endif +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/*! + * @} + */ /* end of group SCT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer + * @{ + */ + +/** SDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register, offset: 0x0 */ + __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */ + __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */ + __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */ + __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */ + __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */ + __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */ + __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */ + __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */ + __IO uint32_t CMD; /**< Command register, offset: 0x2C */ + __IO uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */ + __IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */ + __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */ + __IO uint32_t STATUS; /**< Status register, offset: 0x48 */ + __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */ + __IO uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */ + __IO uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */ + uint8_t RESERVED_1[4]; + __IO uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */ + __IO uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */ + __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */ + uint8_t RESERVED_2[16]; + __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */ + uint8_t RESERVED_3[4]; + __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */ + __IO uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */ + __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */ + __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */ + __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */ + __IO uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */ + __IO uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */ + uint8_t RESERVED_4[100]; + __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */ + __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */ + uint8_t RESERVED_5[248]; + __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */ +} SDIF_Type; + +/* ---------------------------------------------------------------------------- + -- SDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDIF_Register_Masks SDIF Register Masks + * @{ + */ + +/*! @name CTRL - Control register */ +/*! @{ */ +#define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U) +#define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U) +#define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK) +#define SDIF_CTRL_FIFO_RESET_MASK (0x2U) +#define SDIF_CTRL_FIFO_RESET_SHIFT (1U) +#define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK) +#define SDIF_CTRL_DMA_RESET_MASK (0x4U) +#define SDIF_CTRL_DMA_RESET_SHIFT (2U) +#define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK) +#define SDIF_CTRL_INT_ENABLE_MASK (0x10U) +#define SDIF_CTRL_INT_ENABLE_SHIFT (4U) +#define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK) +#define SDIF_CTRL_READ_WAIT_MASK (0x40U) +#define SDIF_CTRL_READ_WAIT_SHIFT (6U) +#define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK) +#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U) +#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U) +#define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK) +#define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U) +#define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U) +#define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK) +#define SDIF_CTRL_SEND_CCSD_MASK (0x200U) +#define SDIF_CTRL_SEND_CCSD_SHIFT (9U) +#define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK) +#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U) +#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U) +#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK) +#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U) +#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U) +#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK) +#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U) +#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U) +#define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK) +#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U) +#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U) +#define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK) +#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U) +#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U) +#define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK) +#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U) +#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U) +#define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) +/*! @} */ + +/*! @name PWREN - Power Enable register */ +/*! @{ */ +#define SDIF_PWREN_POWER_ENABLE0_MASK (0x1U) +#define SDIF_PWREN_POWER_ENABLE0_SHIFT (0U) +#define SDIF_PWREN_POWER_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE0_SHIFT)) & SDIF_PWREN_POWER_ENABLE0_MASK) +#define SDIF_PWREN_POWER_ENABLE1_MASK (0x2U) +#define SDIF_PWREN_POWER_ENABLE1_SHIFT (1U) +#define SDIF_PWREN_POWER_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE1_SHIFT)) & SDIF_PWREN_POWER_ENABLE1_MASK) +/*! @} */ + +/*! @name CLKDIV - Clock Divider register */ +/*! @{ */ +#define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU) +#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U) +#define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK) +/*! @} */ + +/*! @name CLKENA - Clock Enable register */ +/*! @{ */ +#define SDIF_CLKENA_CCLK0_ENABLE_MASK (0x1U) +#define SDIF_CLKENA_CCLK0_ENABLE_SHIFT (0U) +#define SDIF_CLKENA_CCLK0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK0_ENABLE_MASK) +#define SDIF_CLKENA_CCLK1_ENABLE_MASK (0x2U) +#define SDIF_CLKENA_CCLK1_ENABLE_SHIFT (1U) +#define SDIF_CLKENA_CCLK1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK1_ENABLE_MASK) +#define SDIF_CLKENA_CCLK0_LOW_POWER_MASK (0x10000U) +#define SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT (16U) +#define SDIF_CLKENA_CCLK0_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK0_LOW_POWER_MASK) +#define SDIF_CLKENA_CCLK1_LOW_POWER_MASK (0x20000U) +#define SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT (17U) +#define SDIF_CLKENA_CCLK1_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK1_LOW_POWER_MASK) +/*! @} */ + +/*! @name TMOUT - Time-out register */ +/*! @{ */ +#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU) +#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U) +#define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK) +#define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U) +#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U) +#define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK) +/*! @} */ + +/*! @name CTYPE - Card Type register */ +/*! @{ */ +#define SDIF_CTYPE_CARD0_WIDTH0_MASK (0x1U) +#define SDIF_CTYPE_CARD0_WIDTH0_SHIFT (0U) +#define SDIF_CTYPE_CARD0_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH0_MASK) +#define SDIF_CTYPE_CARD1_WIDTH0_MASK (0x2U) +#define SDIF_CTYPE_CARD1_WIDTH0_SHIFT (1U) +#define SDIF_CTYPE_CARD1_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH0_MASK) +#define SDIF_CTYPE_CARD0_WIDTH1_MASK (0x10000U) +#define SDIF_CTYPE_CARD0_WIDTH1_SHIFT (16U) +#define SDIF_CTYPE_CARD0_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH1_MASK) +#define SDIF_CTYPE_CARD1_WIDTH1_MASK (0x20000U) +#define SDIF_CTYPE_CARD1_WIDTH1_SHIFT (17U) +#define SDIF_CTYPE_CARD1_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH1_MASK) +/*! @} */ + +/*! @name BLKSIZ - Block Size register */ +/*! @{ */ +#define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU) +#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U) +#define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK) +/*! @} */ + +/*! @name BYTCNT - Byte Count register */ +/*! @{ */ +#define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU) +#define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U) +#define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK) +/*! @} */ + +/*! @name INTMASK - Interrupt Mask register */ +/*! @{ */ +#define SDIF_INTMASK_CDET_MASK (0x1U) +#define SDIF_INTMASK_CDET_SHIFT (0U) +#define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK) +#define SDIF_INTMASK_RE_MASK (0x2U) +#define SDIF_INTMASK_RE_SHIFT (1U) +#define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK) +#define SDIF_INTMASK_CDONE_MASK (0x4U) +#define SDIF_INTMASK_CDONE_SHIFT (2U) +#define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK) +#define SDIF_INTMASK_DTO_MASK (0x8U) +#define SDIF_INTMASK_DTO_SHIFT (3U) +#define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK) +#define SDIF_INTMASK_TXDR_MASK (0x10U) +#define SDIF_INTMASK_TXDR_SHIFT (4U) +#define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK) +#define SDIF_INTMASK_RXDR_MASK (0x20U) +#define SDIF_INTMASK_RXDR_SHIFT (5U) +#define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK) +#define SDIF_INTMASK_RCRC_MASK (0x40U) +#define SDIF_INTMASK_RCRC_SHIFT (6U) +#define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK) +#define SDIF_INTMASK_DCRC_MASK (0x80U) +#define SDIF_INTMASK_DCRC_SHIFT (7U) +#define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK) +#define SDIF_INTMASK_RTO_MASK (0x100U) +#define SDIF_INTMASK_RTO_SHIFT (8U) +#define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK) +#define SDIF_INTMASK_DRTO_MASK (0x200U) +#define SDIF_INTMASK_DRTO_SHIFT (9U) +#define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK) +#define SDIF_INTMASK_HTO_MASK (0x400U) +#define SDIF_INTMASK_HTO_SHIFT (10U) +#define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK) +#define SDIF_INTMASK_FRUN_MASK (0x800U) +#define SDIF_INTMASK_FRUN_SHIFT (11U) +#define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK) +#define SDIF_INTMASK_HLE_MASK (0x1000U) +#define SDIF_INTMASK_HLE_SHIFT (12U) +#define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK) +#define SDIF_INTMASK_SBE_MASK (0x2000U) +#define SDIF_INTMASK_SBE_SHIFT (13U) +#define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK) +#define SDIF_INTMASK_ACD_MASK (0x4000U) +#define SDIF_INTMASK_ACD_SHIFT (14U) +#define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK) +#define SDIF_INTMASK_EBE_MASK (0x8000U) +#define SDIF_INTMASK_EBE_SHIFT (15U) +#define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK) +#define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U) +#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U) +#define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK) +/*! @} */ + +/*! @name CMDARG - Command Argument register */ +/*! @{ */ +#define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU) +#define SDIF_CMDARG_CMD_ARG_SHIFT (0U) +#define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK) +/*! @} */ + +/*! @name CMD - Command register */ +/*! @{ */ +#define SDIF_CMD_CMD_INDEX_MASK (0x3FU) +#define SDIF_CMD_CMD_INDEX_SHIFT (0U) +#define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK) +#define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U) +#define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U) +#define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK) +#define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U) +#define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U) +#define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK) +#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U) +#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U) +#define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK) +#define SDIF_CMD_DATA_EXPECTED_MASK (0x200U) +#define SDIF_CMD_DATA_EXPECTED_SHIFT (9U) +#define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK) +#define SDIF_CMD_READ_WRITE_MASK (0x400U) +#define SDIF_CMD_READ_WRITE_SHIFT (10U) +#define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK) +#define SDIF_CMD_TRANSFER_MODE_MASK (0x800U) +#define SDIF_CMD_TRANSFER_MODE_SHIFT (11U) +#define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK) +#define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U) +#define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U) +#define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK) +#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U) +#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U) +#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK) +#define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U) +#define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U) +#define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK) +#define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U) +#define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U) +#define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK) +#define SDIF_CMD_CARD_NUMBER_MASK (0x1F0000U) +#define SDIF_CMD_CARD_NUMBER_SHIFT (16U) +/*! CARD_NUMBER - Specifies the card number of SDCARD for which the current Command is being executed + * 0b00000..Command will be execute on SDCARD 0 + * 0b00001..Command will be execute on SDCARD 1 + */ +#define SDIF_CMD_CARD_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CARD_NUMBER_SHIFT)) & SDIF_CMD_CARD_NUMBER_MASK) +#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U) +#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U) +#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK) +#define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U) +#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U) +#define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK) +#define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U) +#define SDIF_CMD_CCS_EXPECTED_SHIFT (23U) +#define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK) +#define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U) +#define SDIF_CMD_ENABLE_BOOT_SHIFT (24U) +#define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK) +#define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U) +#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U) +#define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK) +#define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U) +#define SDIF_CMD_DISABLE_BOOT_SHIFT (26U) +#define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK) +#define SDIF_CMD_BOOT_MODE_MASK (0x8000000U) +#define SDIF_CMD_BOOT_MODE_SHIFT (27U) +#define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK) +#define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U) +#define SDIF_CMD_VOLT_SWITCH_SHIFT (28U) +#define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK) +#define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U) +#define SDIF_CMD_USE_HOLD_REG_SHIFT (29U) +#define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK) +#define SDIF_CMD_START_CMD_MASK (0x80000000U) +#define SDIF_CMD_START_CMD_SHIFT (31U) +#define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK) +/*! @} */ + +/*! @name RESP - Response register */ +/*! @{ */ +#define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU) +#define SDIF_RESP_RESPONSE_SHIFT (0U) +#define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK) +/*! @} */ + +/* The count of SDIF_RESP */ +#define SDIF_RESP_COUNT (4U) + +/*! @name MINTSTS - Masked Interrupt Status register */ +/*! @{ */ +#define SDIF_MINTSTS_CDET_MASK (0x1U) +#define SDIF_MINTSTS_CDET_SHIFT (0U) +#define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK) +#define SDIF_MINTSTS_RE_MASK (0x2U) +#define SDIF_MINTSTS_RE_SHIFT (1U) +#define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK) +#define SDIF_MINTSTS_CDONE_MASK (0x4U) +#define SDIF_MINTSTS_CDONE_SHIFT (2U) +#define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK) +#define SDIF_MINTSTS_DTO_MASK (0x8U) +#define SDIF_MINTSTS_DTO_SHIFT (3U) +#define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK) +#define SDIF_MINTSTS_TXDR_MASK (0x10U) +#define SDIF_MINTSTS_TXDR_SHIFT (4U) +#define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK) +#define SDIF_MINTSTS_RXDR_MASK (0x20U) +#define SDIF_MINTSTS_RXDR_SHIFT (5U) +#define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK) +#define SDIF_MINTSTS_RCRC_MASK (0x40U) +#define SDIF_MINTSTS_RCRC_SHIFT (6U) +#define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK) +#define SDIF_MINTSTS_DCRC_MASK (0x80U) +#define SDIF_MINTSTS_DCRC_SHIFT (7U) +#define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK) +#define SDIF_MINTSTS_RTO_MASK (0x100U) +#define SDIF_MINTSTS_RTO_SHIFT (8U) +#define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK) +#define SDIF_MINTSTS_DRTO_MASK (0x200U) +#define SDIF_MINTSTS_DRTO_SHIFT (9U) +#define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK) +#define SDIF_MINTSTS_HTO_MASK (0x400U) +#define SDIF_MINTSTS_HTO_SHIFT (10U) +#define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK) +#define SDIF_MINTSTS_FRUN_MASK (0x800U) +#define SDIF_MINTSTS_FRUN_SHIFT (11U) +#define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK) +#define SDIF_MINTSTS_HLE_MASK (0x1000U) +#define SDIF_MINTSTS_HLE_SHIFT (12U) +#define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK) +#define SDIF_MINTSTS_SBE_MASK (0x2000U) +#define SDIF_MINTSTS_SBE_SHIFT (13U) +#define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK) +#define SDIF_MINTSTS_ACD_MASK (0x4000U) +#define SDIF_MINTSTS_ACD_SHIFT (14U) +#define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK) +#define SDIF_MINTSTS_EBE_MASK (0x8000U) +#define SDIF_MINTSTS_EBE_SHIFT (15U) +#define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK) +#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U) +#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U) +#define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK) +/*! @} */ + +/*! @name RINTSTS - Raw Interrupt Status register */ +/*! @{ */ +#define SDIF_RINTSTS_CDET_MASK (0x1U) +#define SDIF_RINTSTS_CDET_SHIFT (0U) +#define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK) +#define SDIF_RINTSTS_RE_MASK (0x2U) +#define SDIF_RINTSTS_RE_SHIFT (1U) +#define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK) +#define SDIF_RINTSTS_CDONE_MASK (0x4U) +#define SDIF_RINTSTS_CDONE_SHIFT (2U) +#define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK) +#define SDIF_RINTSTS_DTO_MASK (0x8U) +#define SDIF_RINTSTS_DTO_SHIFT (3U) +#define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK) +#define SDIF_RINTSTS_TXDR_MASK (0x10U) +#define SDIF_RINTSTS_TXDR_SHIFT (4U) +#define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK) +#define SDIF_RINTSTS_RXDR_MASK (0x20U) +#define SDIF_RINTSTS_RXDR_SHIFT (5U) +#define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK) +#define SDIF_RINTSTS_RCRC_MASK (0x40U) +#define SDIF_RINTSTS_RCRC_SHIFT (6U) +#define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK) +#define SDIF_RINTSTS_DCRC_MASK (0x80U) +#define SDIF_RINTSTS_DCRC_SHIFT (7U) +#define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK) +#define SDIF_RINTSTS_RTO_BAR_MASK (0x100U) +#define SDIF_RINTSTS_RTO_BAR_SHIFT (8U) +#define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK) +#define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U) +#define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U) +#define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK) +#define SDIF_RINTSTS_HTO_MASK (0x400U) +#define SDIF_RINTSTS_HTO_SHIFT (10U) +#define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK) +#define SDIF_RINTSTS_FRUN_MASK (0x800U) +#define SDIF_RINTSTS_FRUN_SHIFT (11U) +#define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK) +#define SDIF_RINTSTS_HLE_MASK (0x1000U) +#define SDIF_RINTSTS_HLE_SHIFT (12U) +#define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK) +#define SDIF_RINTSTS_SBE_MASK (0x2000U) +#define SDIF_RINTSTS_SBE_SHIFT (13U) +#define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK) +#define SDIF_RINTSTS_ACD_MASK (0x4000U) +#define SDIF_RINTSTS_ACD_SHIFT (14U) +#define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK) +#define SDIF_RINTSTS_EBE_MASK (0x8000U) +#define SDIF_RINTSTS_EBE_SHIFT (15U) +#define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK) +#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U) +#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U) +#define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK) +/*! @} */ + +/*! @name STATUS - Status register */ +/*! @{ */ +#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U) +#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U) +#define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK) +#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U) +#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U) +#define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK) +#define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U) +#define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U) +#define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK) +#define SDIF_STATUS_FIFO_FULL_MASK (0x8U) +#define SDIF_STATUS_FIFO_FULL_SHIFT (3U) +#define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK) +#define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U) +#define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U) +#define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK) +#define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U) +#define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U) +#define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK) +#define SDIF_STATUS_DATA_BUSY_MASK (0x200U) +#define SDIF_STATUS_DATA_BUSY_SHIFT (9U) +#define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK) +#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U) +#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U) +#define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK) +#define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) +#define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U) +#define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK) +#define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U) +#define SDIF_STATUS_FIFO_COUNT_SHIFT (17U) +#define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK) +#define SDIF_STATUS_DMA_ACK_MASK (0x40000000U) +#define SDIF_STATUS_DMA_ACK_SHIFT (30U) +#define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK) +#define SDIF_STATUS_DMA_REQ_MASK (0x80000000U) +#define SDIF_STATUS_DMA_REQ_SHIFT (31U) +#define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK) +/*! @} */ + +/*! @name FIFOTH - FIFO Threshold Watermark register */ +/*! @{ */ +#define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU) +#define SDIF_FIFOTH_TX_WMARK_SHIFT (0U) +#define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK) +#define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U) +#define SDIF_FIFOTH_RX_WMARK_SHIFT (16U) +#define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK) +#define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U) +#define SDIF_FIFOTH_DMA_MTS_SHIFT (28U) +#define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK) +/*! @} */ + +/*! @name CDETECT - Card Detect register */ +/*! @{ */ +#define SDIF_CDETECT_CARD0_DETECT_MASK (0x1U) +#define SDIF_CDETECT_CARD0_DETECT_SHIFT (0U) +#define SDIF_CDETECT_CARD0_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD0_DETECT_SHIFT)) & SDIF_CDETECT_CARD0_DETECT_MASK) +#define SDIF_CDETECT_CARD1_DETECT_MASK (0x2U) +#define SDIF_CDETECT_CARD1_DETECT_SHIFT (1U) +#define SDIF_CDETECT_CARD1_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD1_DETECT_SHIFT)) & SDIF_CDETECT_CARD1_DETECT_MASK) +/*! @} */ + +/*! @name WRTPRT - Write Protect register */ +/*! @{ */ +#define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U) +#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U) +#define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK) +/*! @} */ + +/*! @name TCBCNT - Transferred CIU Card Byte Count register */ +/*! @{ */ +#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU) +#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U) +#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK) +/*! @} */ + +/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */ +/*! @{ */ +#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU) +#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U) +#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK) +/*! @} */ + +/*! @name DEBNCE - Debounce Count register */ +/*! @{ */ +#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU) +#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U) +#define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK) +/*! @} */ + +/*! @name RST_N - Hardware Reset */ +/*! @{ */ +#define SDIF_RST_N_CARD_RESET_MASK (0x1U) +#define SDIF_RST_N_CARD_RESET_SHIFT (0U) +#define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK) +/*! @} */ + +/*! @name BMOD - Bus Mode register */ +/*! @{ */ +#define SDIF_BMOD_SWR_MASK (0x1U) +#define SDIF_BMOD_SWR_SHIFT (0U) +#define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK) +#define SDIF_BMOD_FB_MASK (0x2U) +#define SDIF_BMOD_FB_SHIFT (1U) +#define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK) +#define SDIF_BMOD_DSL_MASK (0x7CU) +#define SDIF_BMOD_DSL_SHIFT (2U) +#define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK) +#define SDIF_BMOD_DE_MASK (0x80U) +#define SDIF_BMOD_DE_SHIFT (7U) +#define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK) +#define SDIF_BMOD_PBL_MASK (0x700U) +#define SDIF_BMOD_PBL_SHIFT (8U) +#define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK) +/*! @} */ + +/*! @name PLDMND - Poll Demand register */ +/*! @{ */ +#define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU) +#define SDIF_PLDMND_PD_SHIFT (0U) +#define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK) +/*! @} */ + +/*! @name DBADDR - Descriptor List Base Address register */ +/*! @{ */ +#define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU) +#define SDIF_DBADDR_SDL_SHIFT (0U) +#define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK) +/*! @} */ + +/*! @name IDSTS - Internal DMAC Status register */ +/*! @{ */ +#define SDIF_IDSTS_TI_MASK (0x1U) +#define SDIF_IDSTS_TI_SHIFT (0U) +#define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK) +#define SDIF_IDSTS_RI_MASK (0x2U) +#define SDIF_IDSTS_RI_SHIFT (1U) +#define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK) +#define SDIF_IDSTS_FBE_MASK (0x4U) +#define SDIF_IDSTS_FBE_SHIFT (2U) +#define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK) +#define SDIF_IDSTS_DU_MASK (0x10U) +#define SDIF_IDSTS_DU_SHIFT (4U) +#define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK) +#define SDIF_IDSTS_CES_MASK (0x20U) +#define SDIF_IDSTS_CES_SHIFT (5U) +#define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK) +#define SDIF_IDSTS_NIS_MASK (0x100U) +#define SDIF_IDSTS_NIS_SHIFT (8U) +#define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK) +#define SDIF_IDSTS_AIS_MASK (0x200U) +#define SDIF_IDSTS_AIS_SHIFT (9U) +#define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK) +#define SDIF_IDSTS_EB_MASK (0x1C00U) +#define SDIF_IDSTS_EB_SHIFT (10U) +#define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK) +#define SDIF_IDSTS_FSM_MASK (0x1E000U) +#define SDIF_IDSTS_FSM_SHIFT (13U) +#define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK) +/*! @} */ + +/*! @name IDINTEN - Internal DMAC Interrupt Enable register */ +/*! @{ */ +#define SDIF_IDINTEN_TI_MASK (0x1U) +#define SDIF_IDINTEN_TI_SHIFT (0U) +#define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK) +#define SDIF_IDINTEN_RI_MASK (0x2U) +#define SDIF_IDINTEN_RI_SHIFT (1U) +#define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK) +#define SDIF_IDINTEN_FBE_MASK (0x4U) +#define SDIF_IDINTEN_FBE_SHIFT (2U) +#define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK) +#define SDIF_IDINTEN_DU_MASK (0x10U) +#define SDIF_IDINTEN_DU_SHIFT (4U) +#define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK) +#define SDIF_IDINTEN_CES_MASK (0x20U) +#define SDIF_IDINTEN_CES_SHIFT (5U) +#define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK) +#define SDIF_IDINTEN_NIS_MASK (0x100U) +#define SDIF_IDINTEN_NIS_SHIFT (8U) +#define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK) +#define SDIF_IDINTEN_AIS_MASK (0x200U) +#define SDIF_IDINTEN_AIS_SHIFT (9U) +#define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK) +/*! @} */ + +/*! @name DSCADDR - Current Host Descriptor Address register */ +/*! @{ */ +#define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU) +#define SDIF_DSCADDR_HDA_SHIFT (0U) +#define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK) +/*! @} */ + +/*! @name BUFADDR - Current Buffer Descriptor Address register */ +/*! @{ */ +#define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU) +#define SDIF_BUFADDR_HBA_SHIFT (0U) +#define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK) +/*! @} */ + +/*! @name CARDTHRCTL - Card Threshold Control */ +/*! @{ */ +#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U) +#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U) +#define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK) +#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U) +#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U) +#define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK) +#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U) +#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U) +#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK) +/*! @} */ + +/*! @name BACKENDPWR - Power control */ +/*! @{ */ +#define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U) +#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U) +#define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK) +/*! @} */ + +/*! @name FIFO - SDIF FIFO */ +/*! @{ */ +#define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU) +#define SDIF_FIFO_DATA_SHIFT (0U) +#define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK) +/*! @} */ + +/* The count of SDIF_FIFO */ +#define SDIF_FIFO_COUNT (64U) + + +/*! + * @} + */ /* end of group SDIF_Register_Masks */ + + +/* SDIF - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral SDIF base address */ + #define SDIF_BASE (0x5009B000u) + /** Peripheral SDIF base address */ + #define SDIF_BASE_NS (0x4009B000u) + /** Peripheral SDIF base pointer */ + #define SDIF ((SDIF_Type *)SDIF_BASE) + /** Peripheral SDIF base pointer */ + #define SDIF_NS ((SDIF_Type *)SDIF_BASE_NS) + /** Array initializer of SDIF peripheral base addresses */ + #define SDIF_BASE_ADDRS { SDIF_BASE } + /** Array initializer of SDIF peripheral base pointers */ + #define SDIF_BASE_PTRS { SDIF } + /** Array initializer of SDIF peripheral base addresses */ + #define SDIF_BASE_ADDRS_NS { SDIF_BASE_NS } + /** Array initializer of SDIF peripheral base pointers */ + #define SDIF_BASE_PTRS_NS { SDIF_NS } +#else + /** Peripheral SDIF base address */ + #define SDIF_BASE (0x4009B000u) + /** Peripheral SDIF base pointer */ + #define SDIF ((SDIF_Type *)SDIF_BASE) + /** Array initializer of SDIF peripheral base addresses */ + #define SDIF_BASE_ADDRS { SDIF_BASE } + /** Array initializer of SDIF peripheral base pointers */ + #define SDIF_BASE_PTRS { SDIF } +#endif +/** Interrupt vectors for the SDIF peripheral type */ +#define SDIF_IRQS { SDIO_IRQn } + +/*! + * @} + */ /* end of group SDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer + * @{ + */ + +/** SPI - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[1024]; + __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ + __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ + __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ + __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ + __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ + __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ + uint8_t RESERVED_2[2516]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_6[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + uint8_t RESERVED_7[440]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} SPI_Type; + +/* ---------------------------------------------------------------------------- + -- SPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Register_Masks SPI Register Masks + * @{ + */ + +/*! @name CFG - SPI Configuration register */ +/*! @{ */ +#define SPI_CFG_ENABLE_MASK (0x1U) +#define SPI_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - SPI enable. + * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. + * 0b1..Enabled. The SPI is enabled for operation. + */ +#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) +#define SPI_CFG_MASTER_MASK (0x4U) +#define SPI_CFG_MASTER_SHIFT (2U) +/*! MASTER - Master mode select. + * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. + * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. + */ +#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) +#define SPI_CFG_LSBF_MASK (0x8U) +#define SPI_CFG_LSBF_SHIFT (3U) +/*! LSBF - LSB First mode enable. + * 0b0..Standard. Data is transmitted and received in standard MSB first order. + * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). + */ +#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) +#define SPI_CFG_CPHA_MASK (0x10U) +#define SPI_CFG_CPHA_SHIFT (4U) +/*! CPHA - Clock Phase select. + * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock + * changes away from the rest state). Data is changed on the following edge. + * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock + * changes away from the rest state). Data is captured on the following edge. + */ +#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) +#define SPI_CFG_CPOL_MASK (0x20U) +#define SPI_CFG_CPOL_SHIFT (5U) +/*! CPOL - Clock Polarity select. + * 0b0..Low. The rest state of the clock (between transfers) is low. + * 0b1..High. The rest state of the clock (between transfers) is high. + */ +#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) +#define SPI_CFG_LOOP_MASK (0x80U) +#define SPI_CFG_LOOP_SHIFT (7U) +/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit + * and receive data connected together to allow simple software testing. + * 0b0..Disabled. + * 0b1..Enabled. + */ +#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) +#define SPI_CFG_SPOL0_MASK (0x100U) +#define SPI_CFG_SPOL0_SHIFT (8U) +/*! SPOL0 - SSEL0 Polarity select. + * 0b0..Low. The SSEL0 pin is active low. + * 0b1..High. The SSEL0 pin is active high. + */ +#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) +#define SPI_CFG_SPOL1_MASK (0x200U) +#define SPI_CFG_SPOL1_SHIFT (9U) +/*! SPOL1 - SSEL1 Polarity select. + * 0b0..Low. The SSEL1 pin is active low. + * 0b1..High. The SSEL1 pin is active high. + */ +#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) +#define SPI_CFG_SPOL2_MASK (0x400U) +#define SPI_CFG_SPOL2_SHIFT (10U) +/*! SPOL2 - SSEL2 Polarity select. + * 0b0..Low. The SSEL2 pin is active low. + * 0b1..High. The SSEL2 pin is active high. + */ +#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) +#define SPI_CFG_SPOL3_MASK (0x800U) +#define SPI_CFG_SPOL3_SHIFT (11U) +/*! SPOL3 - SSEL3 Polarity select. + * 0b0..Low. The SSEL3 pin is active low. + * 0b1..High. The SSEL3 pin is active high. + */ +#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) +/*! @} */ + +/*! @name DLY - SPI Delay register */ +/*! @{ */ +#define SPI_DLY_PRE_DELAY_MASK (0xFU) +#define SPI_DLY_PRE_DELAY_SHIFT (0U) +#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) +#define SPI_DLY_POST_DELAY_MASK (0xF0U) +#define SPI_DLY_POST_DELAY_SHIFT (4U) +#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) +#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) +#define SPI_DLY_FRAME_DELAY_SHIFT (8U) +#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) +#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) +#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) +#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) +/*! @} */ + +/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ +/*! @{ */ +#define SPI_STAT_SSA_MASK (0x10U) +#define SPI_STAT_SSA_SHIFT (4U) +#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) +#define SPI_STAT_SSD_MASK (0x20U) +#define SPI_STAT_SSD_SHIFT (5U) +#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) +#define SPI_STAT_STALLED_MASK (0x40U) +#define SPI_STAT_STALLED_SHIFT (6U) +#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) +#define SPI_STAT_ENDTRANSFER_MASK (0x80U) +#define SPI_STAT_ENDTRANSFER_SHIFT (7U) +#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) +#define SPI_STAT_MSTIDLE_MASK (0x100U) +#define SPI_STAT_MSTIDLE_SHIFT (8U) +#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ +#define SPI_INTENSET_SSAEN_MASK (0x10U) +#define SPI_INTENSET_SSAEN_SHIFT (4U) +/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. + * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. + * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. + */ +#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) +#define SPI_INTENSET_SSDEN_MASK (0x20U) +#define SPI_INTENSET_SSDEN_SHIFT (5U) +/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. + * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. + * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. + */ +#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) +#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) +#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) +/*! MSTIDLEEN - Master idle interrupt enable. + * 0b0..No interrupt will be generated when the SPI master function is idle. + * 0b1..An interrupt will be generated when the SPI master function is fully idle. + */ +#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) +/*! @} */ + +/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ +/*! @{ */ +#define SPI_INTENCLR_SSAEN_MASK (0x10U) +#define SPI_INTENCLR_SSAEN_SHIFT (4U) +#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) +#define SPI_INTENCLR_SSDEN_MASK (0x20U) +#define SPI_INTENCLR_SSDEN_SHIFT (5U) +#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) +#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) +#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) +#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) +/*! @} */ + +/*! @name DIV - SPI clock Divider */ +/*! @{ */ +#define SPI_DIV_DIVVAL_MASK (0xFFFFU) +#define SPI_DIV_DIVVAL_SHIFT (0U) +#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - SPI Interrupt Status */ +/*! @{ */ +#define SPI_INTSTAT_SSA_MASK (0x10U) +#define SPI_INTSTAT_SSA_SHIFT (4U) +#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) +#define SPI_INTSTAT_SSD_MASK (0x20U) +#define SPI_INTSTAT_SSD_SHIFT (5U) +#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) +#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) +#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) +#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ +#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) +#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) +#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) +#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) +#define SPI_FIFOCFG_SIZE_MASK (0x30U) +#define SPI_FIFOCFG_SIZE_SHIFT (4U) +#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) +#define SPI_FIFOCFG_DMATX_MASK (0x1000U) +#define SPI_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) +#define SPI_FIFOCFG_DMARX_MASK (0x2000U) +#define SPI_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) +#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) +#define SPI_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) +#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) +#define SPI_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in + * FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) +#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) +#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) +#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) +#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ +#define SPI_FIFOSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOSTAT_TXERR_SHIFT (0U) +#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) +#define SPI_FIFOSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOSTAT_RXERR_SHIFT (1U) +#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) +#define SPI_FIFOSTAT_PERINT_MASK (0x8U) +#define SPI_FIFOSTAT_PERINT_SHIFT (3U) +#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) +#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) +#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) +#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) +#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) +#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) +#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) +#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) +#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) +#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) +#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) +#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) +#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ +#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) +#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) +#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) +#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) +#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) +#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) +#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ +#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) +#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) +#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) +#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) +#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases + * to the level specified by TXLVL in the FIFOTRIG register. + */ +#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) +#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level + * increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ +#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) +#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) +#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) +#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) +#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) +#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) +#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) +#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) +#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) +#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ +#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) +#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) +#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) +#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) +#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) +#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) +#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) +#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) +#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) +#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) +#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ +#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) +#define SPI_FIFOWR_TXDATA_SHIFT (0U) +#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) +#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) +#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) +/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL0 asserted. + * 0b1..SSEL0 not asserted. + */ +#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) +#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) +#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) +/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL1 asserted. + * 0b1..SSEL1 not asserted. + */ +#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) +#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) +#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) +/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL2 asserted. + * 0b1..SSEL2 not asserted. + */ +#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) +#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) +#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) +/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL3 asserted. + * 0b1..SSEL3 not asserted. + */ +#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) +#define SPI_FIFOWR_EOT_MASK (0x100000U) +#define SPI_FIFOWR_EOT_SHIFT (20U) +/*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain + * so far at least the time specified by the Transfer_delay value in the DLY register. + * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. + * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. + */ +#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) +#define SPI_FIFOWR_EOF_MASK (0x200000U) +#define SPI_FIFOWR_EOF_SHIFT (21U) +/*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value + * in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay + * value = 0. This control can be used as part of the support for frame lengths greater than 16 + * bits. + * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame. + * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be + * inserted before subsequent data is transmitted. + */ +#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) +#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) +#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) +/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to + * read unneeded data from the receiver. Setting this bit simplifies the transmit process and can + * be used with the DMA. + * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit + * will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data + * is not read before new data is received. + * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received + * data. No receiver flags are generated. + */ +#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) +#define SPI_FIFOWR_LEN_MASK (0xF000000U) +#define SPI_FIFOWR_LEN_SHIFT (24U) +#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ +#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORD_RXDATA_SHIFT (0U) +#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) +#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) +#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) +#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) +#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) +#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) +#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) +#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) +#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) +#define SPI_FIFORD_SOT_MASK (0x100000U) +#define SPI_FIFORD_SOT_SHIFT (20U) +#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ +#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) +#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) +#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) +#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) +#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) +#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) +#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) +#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) +#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) +#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) +#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) +#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) +#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ +#define SPI_ID_APERTURE_MASK (0xFFU) +#define SPI_ID_APERTURE_SHIFT (0U) +#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) +#define SPI_ID_MINOR_REV_MASK (0xF00U) +#define SPI_ID_MINOR_REV_SHIFT (8U) +#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) +#define SPI_ID_MAJOR_REV_MASK (0xF000U) +#define SPI_ID_MAJOR_REV_SHIFT (12U) +#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) +#define SPI_ID_ID_MASK (0xFFFF0000U) +#define SPI_ID_ID_SHIFT (16U) +#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPI_Register_Masks */ + + +/* SPI - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral SPI0 base address */ + #define SPI0_BASE (0x50086000u) + /** Peripheral SPI0 base address */ + #define SPI0_BASE_NS (0x40086000u) + /** Peripheral SPI0 base pointer */ + #define SPI0 ((SPI_Type *)SPI0_BASE) + /** Peripheral SPI0 base pointer */ + #define SPI0_NS ((SPI_Type *)SPI0_BASE_NS) + /** Peripheral SPI1 base address */ + #define SPI1_BASE (0x50087000u) + /** Peripheral SPI1 base address */ + #define SPI1_BASE_NS (0x40087000u) + /** Peripheral SPI1 base pointer */ + #define SPI1 ((SPI_Type *)SPI1_BASE) + /** Peripheral SPI1 base pointer */ + #define SPI1_NS ((SPI_Type *)SPI1_BASE_NS) + /** Peripheral SPI2 base address */ + #define SPI2_BASE (0x50088000u) + /** Peripheral SPI2 base address */ + #define SPI2_BASE_NS (0x40088000u) + /** Peripheral SPI2 base pointer */ + #define SPI2 ((SPI_Type *)SPI2_BASE) + /** Peripheral SPI2 base pointer */ + #define SPI2_NS ((SPI_Type *)SPI2_BASE_NS) + /** Peripheral SPI3 base address */ + #define SPI3_BASE (0x50089000u) + /** Peripheral SPI3 base address */ + #define SPI3_BASE_NS (0x40089000u) + /** Peripheral SPI3 base pointer */ + #define SPI3 ((SPI_Type *)SPI3_BASE) + /** Peripheral SPI3 base pointer */ + #define SPI3_NS ((SPI_Type *)SPI3_BASE_NS) + /** Peripheral SPI4 base address */ + #define SPI4_BASE (0x5008A000u) + /** Peripheral SPI4 base address */ + #define SPI4_BASE_NS (0x4008A000u) + /** Peripheral SPI4 base pointer */ + #define SPI4 ((SPI_Type *)SPI4_BASE) + /** Peripheral SPI4 base pointer */ + #define SPI4_NS ((SPI_Type *)SPI4_BASE_NS) + /** Peripheral SPI5 base address */ + #define SPI5_BASE (0x50096000u) + /** Peripheral SPI5 base address */ + #define SPI5_BASE_NS (0x40096000u) + /** Peripheral SPI5 base pointer */ + #define SPI5 ((SPI_Type *)SPI5_BASE) + /** Peripheral SPI5 base pointer */ + #define SPI5_NS ((SPI_Type *)SPI5_BASE_NS) + /** Peripheral SPI6 base address */ + #define SPI6_BASE (0x50097000u) + /** Peripheral SPI6 base address */ + #define SPI6_BASE_NS (0x40097000u) + /** Peripheral SPI6 base pointer */ + #define SPI6 ((SPI_Type *)SPI6_BASE) + /** Peripheral SPI6 base pointer */ + #define SPI6_NS ((SPI_Type *)SPI6_BASE_NS) + /** Peripheral SPI7 base address */ + #define SPI7_BASE (0x50098000u) + /** Peripheral SPI7 base address */ + #define SPI7_BASE_NS (0x40098000u) + /** Peripheral SPI7 base pointer */ + #define SPI7 ((SPI_Type *)SPI7_BASE) + /** Peripheral SPI7 base pointer */ + #define SPI7_NS ((SPI_Type *)SPI7_BASE_NS) + /** Peripheral SPI8 base address */ + #define SPI8_BASE (0x5009F000u) + /** Peripheral SPI8 base address */ + #define SPI8_BASE_NS (0x4009F000u) + /** Peripheral SPI8 base pointer */ + #define SPI8 ((SPI_Type *)SPI8_BASE) + /** Peripheral SPI8 base pointer */ + #define SPI8_NS ((SPI_Type *)SPI8_BASE_NS) + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS_NS { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS_NS { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS } +#else + /** Peripheral SPI0 base address */ + #define SPI0_BASE (0x40086000u) + /** Peripheral SPI0 base pointer */ + #define SPI0 ((SPI_Type *)SPI0_BASE) + /** Peripheral SPI1 base address */ + #define SPI1_BASE (0x40087000u) + /** Peripheral SPI1 base pointer */ + #define SPI1 ((SPI_Type *)SPI1_BASE) + /** Peripheral SPI2 base address */ + #define SPI2_BASE (0x40088000u) + /** Peripheral SPI2 base pointer */ + #define SPI2 ((SPI_Type *)SPI2_BASE) + /** Peripheral SPI3 base address */ + #define SPI3_BASE (0x40089000u) + /** Peripheral SPI3 base pointer */ + #define SPI3 ((SPI_Type *)SPI3_BASE) + /** Peripheral SPI4 base address */ + #define SPI4_BASE (0x4008A000u) + /** Peripheral SPI4 base pointer */ + #define SPI4 ((SPI_Type *)SPI4_BASE) + /** Peripheral SPI5 base address */ + #define SPI5_BASE (0x40096000u) + /** Peripheral SPI5 base pointer */ + #define SPI5 ((SPI_Type *)SPI5_BASE) + /** Peripheral SPI6 base address */ + #define SPI6_BASE (0x40097000u) + /** Peripheral SPI6 base pointer */ + #define SPI6 ((SPI_Type *)SPI6_BASE) + /** Peripheral SPI7 base address */ + #define SPI7_BASE (0x40098000u) + /** Peripheral SPI7 base pointer */ + #define SPI7 ((SPI_Type *)SPI7_BASE) + /** Peripheral SPI8 base address */ + #define SPI8_BASE (0x4009F000u) + /** Peripheral SPI8 base pointer */ + #define SPI8 ((SPI_Type *)SPI8_BASE) + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } +#endif +/** Interrupt vectors for the SPI peripheral type */ +#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } + +/*! + * @} + */ /* end of group SPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer + * @{ + */ + +/** SYSCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t MEMORYREMAP; /**< Memory Remap control register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t AHBMATPRIO; /**< AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest, offset: 0x10 */ + uint8_t RESERVED_1[36]; + __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */ + __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */ + __IO uint32_t CPU1STCKCAL; /**< System tick calibration for CPU1, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ + uint8_t RESERVED_3[180]; + union { /* offset: 0x100 */ + struct { /* offset: 0x100 */ + __IO uint32_t PRESETCTRL0; /**< Peripheral reset control 0, offset: 0x100 */ + __IO uint32_t PRESETCTRL1; /**< Peripheral reset control 1, offset: 0x104 */ + __IO uint32_t PRESETCTRL2; /**< Peripheral reset control 2, offset: 0x108 */ + } PRESETCTRL; + __IO uint32_t PRESETCTRLX[3]; /**< Peripheral reset control register, array offset: 0x100, array step: 0x4 */ + }; + uint8_t RESERVED_4[20]; + __IO uint32_t PRESETCTRLSET[3]; /**< Peripheral reset control set register, array offset: 0x120, array step: 0x4 */ + uint8_t RESERVED_5[20]; + __IO uint32_t PRESETCTRLCLR[3]; /**< Peripheral reset control clear register, array offset: 0x140, array step: 0x4 */ + uint8_t RESERVED_6[20]; + __O uint32_t SWR_RESET; /**< generate a software_reset, offset: 0x160 */ + uint8_t RESERVED_7[156]; + union { /* offset: 0x200 */ + struct { /* offset: 0x200 */ + __IO uint32_t AHBCLKCTRL0; /**< AHB Clock control 0, offset: 0x200 */ + __IO uint32_t AHBCLKCTRL1; /**< AHB Clock control 1, offset: 0x204 */ + __IO uint32_t AHBCLKCTRL2; /**< AHB Clock control 2, offset: 0x208 */ + } AHBCLKCTRL; + __IO uint32_t AHBCLKCTRLX[3]; /**< Peripheral reset control register, array offset: 0x200, array step: 0x4 */ + }; + uint8_t RESERVED_8[20]; + __IO uint32_t AHBCLKCTRLSET[3]; /**< Peripheral reset control register, array offset: 0x220, array step: 0x4 */ + uint8_t RESERVED_9[20]; + __IO uint32_t AHBCLKCTRLCLR[3]; /**< Peripheral reset control register, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_10[20]; + union { /* offset: 0x260 */ + struct { /* offset: 0x260 */ + __IO uint32_t SYSTICKCLKSEL0; /**< System Tick Timer for CPU0 source select, offset: 0x260 */ + __IO uint32_t SYSTICKCLKSEL1; /**< System Tick Timer for CPU1 source select, offset: 0x264 */ + } SYSTICKCLKSEL; + __IO uint32_t SYSTICKCLKSELX[2]; /**< Peripheral reset control register, array offset: 0x260, array step: 0x4 */ + }; + __IO uint32_t TRACECLKSEL; /**< Trace clock source select, offset: 0x268 */ + union { /* offset: 0x26C */ + struct { /* offset: 0x26C */ + __IO uint32_t CTIMERCLKSEL0; /**< CTimer 0 clock source select, offset: 0x26C */ + __IO uint32_t CTIMERCLKSEL1; /**< CTimer 1 clock source select, offset: 0x270 */ + __IO uint32_t CTIMERCLKSEL2; /**< CTimer 2 clock source select, offset: 0x274 */ + __IO uint32_t CTIMERCLKSEL3; /**< CTimer 3 clock source select, offset: 0x278 */ + __IO uint32_t CTIMERCLKSEL4; /**< CTimer 4 clock source select, offset: 0x27C */ + } CTIMERCLKSEL; + __IO uint32_t CTIMERCLKSELX[5]; /**< Peripheral reset control register, array offset: 0x26C, array step: 0x4 */ + }; + __IO uint32_t MAINCLKSELA; /**< Main clock A source select, offset: 0x280 */ + __IO uint32_t MAINCLKSELB; /**< Main clock source select, offset: 0x284 */ + __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0x288 */ + uint8_t RESERVED_11[4]; + __IO uint32_t PLL0CLKSEL; /**< PLL0 clock source select, offset: 0x290 */ + __IO uint32_t PLL1CLKSEL; /**< PLL1 clock source select, offset: 0x294 */ + uint8_t RESERVED_12[12]; + __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ + __IO uint32_t USB0CLKSEL; /**< FS USB clock source select, offset: 0x2A8 */ + uint8_t RESERVED_13[4]; + union { /* offset: 0x2B0 */ + struct { /* offset: 0x2B0 */ + __IO uint32_t FCCLKSEL0; /**< Flexcomm Interface 0 clock source select for Fractional Rate Divider, offset: 0x2B0 */ + __IO uint32_t FCCLKSEL1; /**< Flexcomm Interface 1 clock source select for Fractional Rate Divider, offset: 0x2B4 */ + __IO uint32_t FCCLKSEL2; /**< Flexcomm Interface 2 clock source select for Fractional Rate Divider, offset: 0x2B8 */ + __IO uint32_t FCCLKSEL3; /**< Flexcomm Interface 3 clock source select for Fractional Rate Divider, offset: 0x2BC */ + __IO uint32_t FCCLKSEL4; /**< Flexcomm Interface 4 clock source select for Fractional Rate Divider, offset: 0x2C0 */ + __IO uint32_t FCCLKSEL5; /**< Flexcomm Interface 5 clock source select for Fractional Rate Divider, offset: 0x2C4 */ + __IO uint32_t FCCLKSEL6; /**< Flexcomm Interface 6 clock source select for Fractional Rate Divider, offset: 0x2C8 */ + __IO uint32_t FCCLKSEL7; /**< Flexcomm Interface 7 clock source select for Fractional Rate Divider, offset: 0x2CC */ + } FCCLKSEL; + __IO uint32_t FCCLKSELX[8]; /**< Peripheral reset control register, array offset: 0x2B0, array step: 0x4 */ + }; + __IO uint32_t HSLSPICLKSEL; /**< HS LSPI clock source select, offset: 0x2D0 */ + uint8_t RESERVED_14[12]; + __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ + uint8_t RESERVED_15[12]; + __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ + uint8_t RESERVED_16[4]; + __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */ + uint8_t RESERVED_17[4]; + __IO uint32_t SYSTICKCLKDIV0; /**< System Tick Timer divider for CPU0, offset: 0x300 */ + __IO uint32_t SYSTICKCLKDIV1; /**< System Tick Timer divider for CPU1, offset: 0x304 */ + __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */ + uint8_t RESERVED_18[20]; + union { /* offset: 0x320 */ + struct { /* offset: 0x320 */ + __IO uint32_t FLEXFRG0CTRL; /**< Fractional rate divider for flexcomm 0, offset: 0x320 */ + __IO uint32_t FLEXFRG1CTRL; /**< Fractional rate divider for flexcomm 1, offset: 0x324 */ + __IO uint32_t FLEXFRG2CTRL; /**< Fractional rate divider for flexcomm 2, offset: 0x328 */ + __IO uint32_t FLEXFRG3CTRL; /**< Fractional rate divider for flexcomm 3, offset: 0x32C */ + __IO uint32_t FLEXFRG4CTRL; /**< Fractional rate divider for flexcomm 4, offset: 0x330 */ + __IO uint32_t FLEXFRG5CTRL; /**< Fractional rate divider for flexcomm 5, offset: 0x334 */ + __IO uint32_t FLEXFRG6CTRL; /**< Fractional rate divider for flexcomm 6, offset: 0x338 */ + __IO uint32_t FLEXFRG7CTRL; /**< Fractional rate divider for flexcomm 7, offset: 0x33C */ + } FLEXFRGCTRL; + __IO uint32_t FLEXFRGXCTRL[8]; /**< Peripheral reset control register, array offset: 0x320, array step: 0x4 */ + }; + uint8_t RESERVED_19[64]; + __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */ + __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ + __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */ + __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */ + uint8_t RESERVED_20[4]; + __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ + __IO uint32_t USB0CLKDIV; /**< USB0 Clock divider, offset: 0x398 */ + uint8_t RESERVED_21[16]; + __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ + uint8_t RESERVED_22[4]; + __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ + uint8_t RESERVED_23[4]; + __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */ + uint8_t RESERVED_24[4]; + __IO uint32_t PLL0CLKDIV; /**< PLL0 clock divider, offset: 0x3C4 */ + uint8_t RESERVED_25[52]; + __IO uint32_t CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */ + __IO uint32_t FMCCR; /**< FMC configuration register, offset: 0x400 */ + uint8_t RESERVED_26[8]; + __IO uint32_t USB0NEEDCLKCTRL; /**< USB0 need clock control, offset: 0x40C */ + __I uint32_t USB0NEEDCLKSTAT; /**< USB0 need clock status, offset: 0x410 */ + uint8_t RESERVED_27[8]; + __O uint32_t FMCFLUSH; /**< FMCflush control, offset: 0x41C */ + __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */ + __IO uint32_t USB1NEEDCLKCTRL; /**< USB1 need clock control, offset: 0x424 */ + __I uint32_t USB1NEEDCLKSTAT; /**< USB1 need clock status, offset: 0x428 */ + uint8_t RESERVED_28[52]; + __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */ + uint8_t RESERVED_29[252]; + __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */ + __I uint32_t PLL1STAT; /**< PLL1 550m status, offset: 0x564 */ + __IO uint32_t PLL1NDEC; /**< PLL1 550m N divider, offset: 0x568 */ + __IO uint32_t PLL1MDEC; /**< PLL1 550m M divider, offset: 0x56C */ + __IO uint32_t PLL1PDEC; /**< PLL1 550m P divider, offset: 0x570 */ + uint8_t RESERVED_30[12]; + __IO uint32_t PLL0CTRL; /**< PLL0 550m control, offset: 0x580 */ + __I uint32_t PLL0STAT; /**< PLL0 550m status, offset: 0x584 */ + __IO uint32_t PLL0NDEC; /**< PLL0 550m N divider, offset: 0x588 */ + __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */ + __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */ + __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */ + uint8_t RESERVED_31[616]; + __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ + __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ + uint8_t RESERVED_32[4]; + __I uint32_t CPSTAT; /**< CPU Status, offset: 0x80C */ + uint8_t RESERVED_33[520]; + __IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures, offset: 0xA18 */ + uint8_t RESERVED_34[244]; + __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */ + __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */ + uint8_t RESERVED_35[748]; + __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */ + __IO uint32_t GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */ + uint8_t RESERVED_36[404]; + __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers., offset: 0xFA0 */ + __IO uint32_t DEBUG_FEATURES; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control., offset: 0xFA4 */ + __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register., offset: 0xFA8 */ + uint8_t RESERVED_37[16]; + __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index., offset: 0xFBC */ + __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug authentication BEACON register, offset: 0xFC0 */ + uint8_t RESERVED_38[16]; + __IO uint32_t CPUCFG; /**< CPUs configuration register, offset: 0xFD4 */ + uint8_t RESERVED_39[32]; + __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ + __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */ +} SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Register_Masks SYSCON Register Masks + * @{ + */ + +/*! @name MEMORYREMAP - Memory Remap control register */ +/*! @{ */ +#define SYSCON_MEMORYREMAP_MAP_MASK (0x3U) +#define SYSCON_MEMORYREMAP_MAP_SHIFT (0U) +/*! MAP - Select the location of the vector table :. + * 0b00..Vector Table in ROM. + * 0b01..Vector Table in RAM. + * 0b10..Vector Table in Flash. + * 0b11..Vector Table in Flash. + */ +#define SYSCON_MEMORYREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK) +/*! @} */ + +/*! @name AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest */ +/*! @{ */ +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK (0x3U) +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT (0U) +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK) +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK (0xCU) +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT (2U) +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK) +#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK (0x30U) +#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT (4U) +#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK) +#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK (0xC0U) +#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT (6U) +#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK) +#define SYSCON_AHBMATPRIO_PRI_USB_FS_MASK (0x300U) +#define SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT (8U) +#define SYSCON_AHBMATPRIO_PRI_USB_FS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_MASK) +#define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0xC00U) +#define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (10U) +#define SYSCON_AHBMATPRIO_PRI_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK) +#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0x30000U) +#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (16U) +#define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK) +#define SYSCON_AHBMATPRIO_PRI_PQ_MASK (0xC0000U) +#define SYSCON_AHBMATPRIO_PRI_PQ_SHIFT (18U) +#define SYSCON_AHBMATPRIO_PRI_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PQ_MASK) +#define SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK (0x300000U) +#define SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT (20U) +#define SYSCON_AHBMATPRIO_PRI_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT)) & SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK) +#define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK (0xC00000U) +#define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT (22U) +#define SYSCON_AHBMATPRIO_PRI_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK) +#define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0x3000000U) +#define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (24U) +#define SYSCON_AHBMATPRIO_PRI_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK) +/*! @} */ + +/*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */ +/*! @{ */ +#define SYSCON_CPU0STCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0STCKCAL_TENMS_SHIFT (0U) +#define SYSCON_CPU0STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK) +#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) +#define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) +#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) +#define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */ +/*! @{ */ +#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) +#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) +#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) +#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) +#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) +#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name CPU1STCKCAL - System tick calibration for CPU1 */ +/*! @{ */ +#define SYSCON_CPU1STCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU1STCKCAL_TENMS_SHIFT (0U) +#define SYSCON_CPU1STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_TENMS_SHIFT)) & SYSCON_CPU1STCKCAL_TENMS_MASK) +#define SYSCON_CPU1STCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU1STCKCAL_SKEW_SHIFT (24U) +#define SYSCON_CPU1STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_SKEW_SHIFT)) & SYSCON_CPU1STCKCAL_SKEW_MASK) +#define SYSCON_CPU1STCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU1STCKCAL_NOREF_SHIFT (25U) +#define SYSCON_CPU1STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_NOREF_SHIFT)) & SYSCON_CPU1STCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name NMISRC - NMI Source Select */ +/*! @{ */ +#define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU) +#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) +#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) +#define SYSCON_NMISRC_IRQCPU1_MASK (0x3F00U) +#define SYSCON_NMISRC_IRQCPU1_SHIFT (8U) +#define SYSCON_NMISRC_IRQCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU1_SHIFT)) & SYSCON_NMISRC_IRQCPU1_MASK) +#define SYSCON_NMISRC_NMIENCPU1_MASK (0x40000000U) +#define SYSCON_NMISRC_NMIENCPU1_SHIFT (30U) +#define SYSCON_NMISRC_NMIENCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU1_SHIFT)) & SYSCON_NMISRC_NMIENCPU1_MASK) +#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) +#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) +#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) +/*! @} */ + +/*! @name PRESETCTRL0 - Peripheral reset control 0 */ +/*! @{ */ +#define SYSCON_PRESETCTRL0_ROM_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL0_ROM_RST_SHIFT (1U) +/*! ROM_RST - ROM reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_ROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ROM_RST_SHIFT)) & SYSCON_PRESETCTRL0_ROM_RST_MASK) +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U) +/*! SRAM_CTRL1_RST - SRAM Controller 1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK) +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U) +/*! SRAM_CTRL2_RST - SRAM Controller 2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK) +#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT (5U) +/*! SRAM_CTRL3_RST - SRAM Controller 3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK) +#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT (6U) +/*! SRAM_CTRL4_RST - SRAM Controller 4 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK) +#define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U) +/*! FLASH_RST - Flash controller reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK) +#define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U) +/*! FMC_RST - FMC controller reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK) +#define SYSCON_PRESETCTRL0_MUX_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL0_MUX_RST_SHIFT (11U) +/*! MUX_RST - Input Mux reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK) +#define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U) +/*! IOCON_RST - I/O controller reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK) +#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U) +/*! GPIO0_RST - GPIO0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) +#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U) +/*! GPIO1_RST - GPIO1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) +#define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (16U) +/*! GPIO2_RST - GPIO2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK) +#define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (17U) +/*! GPIO3_RST - GPIO3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK) +#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U) +/*! PINT_RST - Pin interrupt (PINT) reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) +#define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U) +/*! GINT_RST - Group interrupt (GINT) reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK) +#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U) +/*! DMA0_RST - DMA0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) +#define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U) +/*! CRCGEN_RST - CRCGEN reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_CRCGEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK) +#define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U) +/*! WWDT_RST - Watchdog Timer reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK) +#define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U) +/*! RTC_RST - Real Time Clock (RTC) reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK) +#define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U) +/*! MAILBOX_RST - Inter CPU communication Mailbox reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK) +#define SYSCON_PRESETCTRL0_ADC_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL0_ADC_RST_SHIFT (27U) +/*! ADC_RST - ADC reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_ADC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL1 - Peripheral reset control 1 */ +/*! @{ */ +#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) +#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) +/*! MRT_RST - MRT reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) +#define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT (1U) +/*! OSTIMER_RST - OS Event Timer reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_OSTIMER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK) +#define SYSCON_PRESETCTRL1_SCT_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL1_SCT_RST_SHIFT (2U) +/*! SCT_RST - SCT reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_SCT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT_RST_MASK) +#define SYSCON_PRESETCTRL1_SCTIPU_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT (6U) +/*! SCTIPU_RST - SCTIPU reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_SCTIPU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCTIPU_RST_MASK) +#define SYSCON_PRESETCTRL1_UTICK_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT (10U) +/*! UTICK_RST - UTICK reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK) +#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) +/*! FC0_RST - FC0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) +#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) +/*! FC1_RST - FC1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) +#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) +/*! FC2_RST - FC2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) +#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) +/*! FC3_RST - FC3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) +#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) +/*! FC4_RST - FC4 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) +#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) +/*! FC5_RST - FC5 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) +#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) +/*! FC6_RST - FC6 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) +#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) +/*! FC7_RST - FC7 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) +#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) +/*! TIMER2_RST - Timer 2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) +#define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK (0x2000000U) +#define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT (25U) +/*! USB0_DEV_RST - USB0 DEV reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_USB0_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK) +#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) +/*! TIMER0_RST - Timer 0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) +#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) +/*! TIMER1_RST - Timer 1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL2 - Peripheral reset control 2 */ +/*! @{ */ +#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) +/*! DMA1_RST - DMA1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) +#define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U) +/*! COMP_RST - Comparator reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_COMP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK) +#define SYSCON_PRESETCTRL2_SDIO_RST_MASK (0x8U) +#define SYSCON_PRESETCTRL2_SDIO_RST_SHIFT (3U) +/*! SDIO_RST - SDIO reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_SDIO_RST_MASK) +#define SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT (4U) +/*! USB1_HOST_RST - USB1 Host reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_HOST_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK) +#define SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT (5U) +/*! USB1_DEV_RST - USB1 dev reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK) +#define SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT (6U) +/*! USB1_RAM_RST - USB1 RAM reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK) +#define SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT (7U) +/*! USB1_PHY_RST - USB1 PHY reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK) +#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) +/*! FREQME_RST - Frequency meter reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) +#define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U) +/*! RNG_RST - RNG reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK) +#define SYSCON_PRESETCTRL2_SYSCTL_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT (15U) +/*! SYSCTL_RST - SYSCTL Block reset. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_SYSCTL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT)) & SYSCON_PRESETCTRL2_SYSCTL_RST_MASK) +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT (16U) +/*! USB0_HOSTM_RST - USB0 Host Master reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK) +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT (17U) +/*! USB0_HOSTS_RST - USB0 Host Slave reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK) +#define SYSCON_PRESETCTRL2_HASH_AES_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT (18U) +/*! HASH_AES_RST - HASH_AES reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_HASH_AES_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH_AES_RST_MASK) +#define SYSCON_PRESETCTRL2_PQ_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL2_PQ_RST_SHIFT (19U) +/*! PQ_RST - Power Quad reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_PQ_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK) +#define SYSCON_PRESETCTRL2_PLULUT_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT (20U) +/*! PLULUT_RST - PLU LUT reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_PLULUT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLULUT_RST_MASK) +#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) +/*! TIMER3_RST - Timer 3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) +#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) +/*! TIMER4_RST - Timer 4 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) +#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) +/*! PUF_RST - PUF reset control reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) +#define SYSCON_PRESETCTRL2_CASPER_RST_MASK (0x1000000U) +#define SYSCON_PRESETCTRL2_CASPER_RST_SHIFT (24U) +/*! CASPER_RST - Casper reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_CASPER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CASPER_RST_SHIFT)) & SYSCON_PRESETCTRL2_CASPER_RST_MASK) +#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT (27U) +/*! ANALOG_CTRL_RST - analog control reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK) +#define SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK (0x10000000U) +#define SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT (28U) +/*! HS_LSPI_RST - HS LSPI reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_HS_LSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK) +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U) +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U) +/*! GPIO_SEC_RST - GPIO secure reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK) +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U) +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U) +/*! GPIO_SEC_INT_RST - GPIO secure int reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRLX - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_PRESETCTRLX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLX_DATA_SHIFT (0U) +#define SYSCON_PRESETCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLX_DATA_SHIFT)) & SYSCON_PRESETCTRLX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLX */ +#define SYSCON_PRESETCTRLX_COUNT (3U) + +/*! @name PRESETCTRLSET - Peripheral reset control set register */ +/*! @{ */ +#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) +#define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLSET */ +#define SYSCON_PRESETCTRLSET_COUNT (3U) + +/*! @name PRESETCTRLCLR - Peripheral reset control clear register */ +/*! @{ */ +#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) +#define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLCLR */ +#define SYSCON_PRESETCTRLCLR_COUNT (3U) + +/*! @name SWR_RESET - generate a software_reset */ +/*! @{ */ +#define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU) +#define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U) +/*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset. + * 0b01011010000000000000000000000001..Generate a software reset. + * 0b00000000000000000000000000000000..Bloc is not reset. + */ +#define SYSCON_SWR_RESET_SWR_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL0 - AHB Clock control 0 */ +/*! @{ */ +#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) +#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) +/*! ROM - Enables the clock for the ROM. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U) +/*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U) +/*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK (0x20U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT (5U) +/*! SRAM_CTRL3 - Enables the clock for the SRAM Controller 3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK (0x40U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT (6U) +/*! SRAM_CTRL4 - Enables the clock for the SRAM Controller 4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK) +#define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U) +#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U) +/*! FLASH - Enables the clock for the Flash controller. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK) +#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U) +#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U) +/*! FMC - Enables the clock for the FMC controller. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) +#define SYSCON_AHBCLKCTRL0_MUX_MASK (0x800U) +#define SYSCON_AHBCLKCTRL0_MUX_SHIFT (11U) +/*! MUX - Enables the clock for the Input Mux. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_MUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK) +#define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U) +/*! IOCON - Enables the clock for the I/O controller. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK) +#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U) +/*! GPIO0 - Enables the clock for the GPIO0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) +#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U) +/*! GPIO1 - Enables the clock for the GPIO1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) +#define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (16U) +/*! GPIO2 - Enables the clock for the GPIO2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK) +#define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (17U) +/*! GPIO3 - Enables the clock for the GPIO3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK) +#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U) +/*! PINT - Enables the clock for the Pin interrupt (PINT). + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) +#define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U) +/*! GINT - Enables the clock for the Group interrupt (GINT). + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK) +#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U) +/*! DMA0 - Enables the clock for the DMA0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) +#define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U) +/*! CRCGEN - Enables the clock for the CRCGEN. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK) +#define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U) +/*! WWDT - Enables the clock for the Watchdog Timer. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK) +#define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U) +/*! RTC - Enables the clock for the Real Time Clock (RTC). + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK) +#define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U) +/*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK) +#define SYSCON_AHBCLKCTRL0_ADC_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL0_ADC_SHIFT (27U) +/*! ADC - Enables the clock for the ADC. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL1 - AHB Clock control 1 */ +/*! @{ */ +#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) +#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) +/*! MRT - Enables the clock for the MRT. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) +#define SYSCON_AHBCLKCTRL1_OSTIMER_MASK (0x2U) +#define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT (1U) +/*! OSTIMER - Enables the clock for the OS Event Timer. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK) +#define SYSCON_AHBCLKCTRL1_SCT_MASK (0x4U) +#define SYSCON_AHBCLKCTRL1_SCT_SHIFT (2U) +/*! SCT - Enables the clock for the SCT. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_SCT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT_MASK) +#define SYSCON_AHBCLKCTRL1_UTICK_MASK (0x400U) +#define SYSCON_AHBCLKCTRL1_UTICK_SHIFT (10U) +/*! UTICK - Enables the clock for the UTICK. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK) +#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) +#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) +/*! FC0 - Enables the clock for the FC0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) +#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) +/*! FC1 - Enables the clock for the FC1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) +#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) +/*! FC2 - Enables the clock for the FC2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) +#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) +/*! FC3 - Enables the clock for the FC3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) +#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) +/*! FC4 - Enables the clock for the FC4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) +#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) +/*! FC5 - Enables the clock for the FC5. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) +#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) +/*! FC6 - Enables the clock for the FC6. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) +#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) +/*! FC7 - Enables the clock for the FC7. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) +#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) +/*! TIMER2 - Enables the clock for the Timer 2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) +#define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK (0x2000000U) +#define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT (25U) +/*! USB0_DEV - Enables the clock for the USB0 DEV. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_USB0_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK) +#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) +/*! TIMER0 - Enables the clock for the Timer 0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) +#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) +/*! TIMER1 - Enables the clock for the Timer 1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL2 - AHB Clock control 2 */ +/*! @{ */ +#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) +#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) +/*! DMA1 - Enables the clock for the DMA1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) +#define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U) +#define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U) +/*! COMP - Enables the clock for the Comparator. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK) +#define SYSCON_AHBCLKCTRL2_SDIO_MASK (0x8U) +#define SYSCON_AHBCLKCTRL2_SDIO_SHIFT (3U) +/*! SDIO - Enables the clock for the SDIO. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL2_SDIO_MASK) +#define SYSCON_AHBCLKCTRL2_USB1_HOST_MASK (0x10U) +#define SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT (4U) +/*! USB1_HOST - Enables the clock for the USB1 Host. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_HOST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_HOST_MASK) +#define SYSCON_AHBCLKCTRL2_USB1_DEV_MASK (0x20U) +#define SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT (5U) +/*! USB1_DEV - Enables the clock for the USB1 dev. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_DEV_MASK) +#define SYSCON_AHBCLKCTRL2_USB1_RAM_MASK (0x40U) +#define SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT (6U) +/*! USB1_RAM - Enables the clock for the USB1 RAM. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_RAM_MASK) +#define SYSCON_AHBCLKCTRL2_USB1_PHY_MASK (0x80U) +#define SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT (7U) +/*! USB1_PHY - Enables the clock for the USB1 PHY. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_PHY_MASK) +#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) +#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) +/*! FREQME - Enables the clock for the Frequency meter. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) +#define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U) +/*! RNG - Enables the clock for the RNG. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK) +#define SYSCON_AHBCLKCTRL2_SYSCTL_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT (15U) +/*! SYSCTL - SYSCTL block clock. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_SYSCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT)) & SYSCON_AHBCLKCTRL2_SYSCTL_MASK) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT (16U) +/*! USB0_HOSTM - Enables the clock for the USB0 Host Master. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT (17U) +/*! USB0_HOSTS - Enables the clock for the USB0 Host Slave. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK) +#define SYSCON_AHBCLKCTRL2_HASH_AES_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT (18U) +/*! HASH_AES - Enables the clock for the HASH_AES. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH_AES_MASK) +#define SYSCON_AHBCLKCTRL2_PQ_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL2_PQ_SHIFT (19U) +/*! PQ - Enables the clock for the Power Quad. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK) +#define SYSCON_AHBCLKCTRL2_PLULUT_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL2_PLULUT_SHIFT (20U) +/*! PLULUT - Enables the clock for the PLU LUT. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PLULUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLULUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLULUT_MASK) +#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) +/*! TIMER3 - Enables the clock for the Timer 3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) +#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) +/*! TIMER4 - Enables the clock for the Timer 4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) +#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) +/*! PUF - Enables the clock for the PUF reset control. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) +#define SYSCON_AHBCLKCTRL2_CASPER_MASK (0x1000000U) +#define SYSCON_AHBCLKCTRL2_CASPER_SHIFT (24U) +/*! CASPER - Enables the clock for the Casper. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CASPER_SHIFT)) & SYSCON_AHBCLKCTRL2_CASPER_MASK) +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U) +/*! ANALOG_CTRL - Enables the clock for the analog control. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK) +#define SYSCON_AHBCLKCTRL2_HS_LSPI_MASK (0x10000000U) +#define SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT (28U) +/*! HS_LSPI - Enables the clock for the HS LSPI. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_LSPI_MASK) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U) +/*! GPIO_SEC - Enables the clock for the GPIO secure. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U) +/*! GPIO_SEC_INT - Enables the clock for the GPIO secure int. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK) +/*! @} */ + +/*! @name AHBCLKCTRLX - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_AHBCLKCTRLX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLX_DATA_SHIFT (0U) +#define SYSCON_AHBCLKCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLX_DATA_SHIFT)) & SYSCON_AHBCLKCTRLX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLX */ +#define SYSCON_AHBCLKCTRLX_COUNT (3U) + +/*! @name AHBCLKCTRLSET - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) +#define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLSET */ +#define SYSCON_AHBCLKCTRLSET_COUNT (3U) + +/*! @name AHBCLKCTRLCLR - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) +#define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLCLR */ +#define SYSCON_AHBCLKCTRLCLR_COUNT (3U) + +/*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */ +/*! @{ */ +#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) +/*! SEL - System Tick Timer for CPU0 source select. + * 0b000..System Tick 0 divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKSEL1 - System Tick Timer for CPU1 source select */ +/*! @{ */ +#define SYSCON_SYSTICKCLKSEL1_SEL_MASK (0x7U) +#define SYSCON_SYSTICKCLKSEL1_SEL_SHIFT (0U) +/*! SEL - System Tick Timer for CPU1 source select. + * 0b000..System Tick 1 divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SYSTICKCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL1_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL1_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKSELX - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_SYSTICKCLKSELX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_SYSTICKCLKSELX_DATA_SHIFT (0U) +#define SYSCON_SYSTICKCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSELX_DATA_SHIFT)) & SYSCON_SYSTICKCLKSELX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_SYSTICKCLKSELX */ +#define SYSCON_SYSTICKCLKSELX_COUNT (2U) + +/*! @name TRACECLKSEL - Trace clock source select */ +/*! @{ */ +#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) +#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) +/*! SEL - Trace clock source select. + * 0b000..Trace divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL0 - CTimer 0 clock source select */ +/*! @{ */ +#define SYSCON_CTIMERCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL0_SEL_SHIFT (0U) +/*! SEL - CTimer 0 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL0_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL1 - CTimer 1 clock source select */ +/*! @{ */ +#define SYSCON_CTIMERCLKSEL1_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL1_SEL_SHIFT (0U) +/*! SEL - CTimer 1 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL1_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL1_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL2 - CTimer 2 clock source select */ +/*! @{ */ +#define SYSCON_CTIMERCLKSEL2_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL2_SEL_SHIFT (0U) +/*! SEL - CTimer 2 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL2_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL2_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL3 - CTimer 3 clock source select */ +/*! @{ */ +#define SYSCON_CTIMERCLKSEL3_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL3_SEL_SHIFT (0U) +/*! SEL - CTimer 3 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL3_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL3_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL4 - CTimer 4 clock source select */ +/*! @{ */ +#define SYSCON_CTIMERCLKSEL4_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL4_SEL_SHIFT (0U) +/*! SEL - CTimer 4 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL4_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL4_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSELX - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_CTIMERCLKSELX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_CTIMERCLKSELX_DATA_SHIFT (0U) +#define SYSCON_CTIMERCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSELX_DATA_SHIFT)) & SYSCON_CTIMERCLKSELX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_CTIMERCLKSELX */ +#define SYSCON_CTIMERCLKSELX_COUNT (5U) + +/*! @name MAINCLKSELA - Main clock A source select */ +/*! @{ */ +#define SYSCON_MAINCLKSELA_SEL_MASK (0x7U) +#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) +/*! SEL - Main clock A source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + * 0b111..Reserved. + */ +#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) +/*! @} */ + +/*! @name MAINCLKSELB - Main clock source select */ +/*! @{ */ +#define SYSCON_MAINCLKSELB_SEL_MASK (0x7U) +#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) +/*! SEL - Main clock source select. + * 0b000..Main Clock A. + * 0b001..PLL0 clock. + * 0b010..PLL1 clock. + * 0b011..Oscillator 32 kHz clock. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + * 0b111..Reserved. + */ +#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) +/*! @} */ + +/*! @name CLKOUTSEL - CLKOUT clock source select */ +/*! @{ */ +#define SYSCON_CLKOUTSEL_SEL_MASK (0x7U) +#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) +/*! SEL - CLKOUT clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..CLKIN clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..PLL1 clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) +/*! @} */ + +/*! @name PLL0CLKSEL - PLL0 clock source select */ +/*! @{ */ +#define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U) +/*! SEL - PLL0 clock source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..Oscillator 32kHz clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_PLL0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name PLL1CLKSEL - PLL1 clock source select */ +/*! @{ */ +#define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U) +#define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U) +/*! SEL - PLL1 clock source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..Oscillator 32kHz clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_PLL1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name ADCCLKSEL - ADC clock source select */ +/*! @{ */ +#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) +#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) +/*! SEL - ADC clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..FRO 96 MHz clock. + * 0b011..Reserved. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name USB0CLKSEL - FS USB clock source select */ +/*! @{ */ +#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) +/*! SEL - FS USB clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..PLL1 clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL0_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL0_SEL_SHIFT)) & SYSCON_FCCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL1_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL1_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL1_SEL_SHIFT)) & SYSCON_FCCLKSEL1_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL2_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL2_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL2_SEL_SHIFT)) & SYSCON_FCCLKSEL2_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL3_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL3_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL3_SEL_SHIFT)) & SYSCON_FCCLKSEL3_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL4_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL4_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL4_SEL_SHIFT)) & SYSCON_FCCLKSEL4_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL5_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL5_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL5_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL5_SEL_SHIFT)) & SYSCON_FCCLKSEL5_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL6_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL6_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL6_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL6_SEL_SHIFT)) & SYSCON_FCCLKSEL6_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider */ +/*! @{ */ +#define SYSCON_FCCLKSEL7_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL7_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL7_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL7_SEL_SHIFT)) & SYSCON_FCCLKSEL7_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSELX - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_FCCLKSELX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_FCCLKSELX_DATA_SHIFT (0U) +#define SYSCON_FCCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSELX_DATA_SHIFT)) & SYSCON_FCCLKSELX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_FCCLKSELX */ +#define SYSCON_FCCLKSELX_COUNT (8U) + +/*! @name HSLSPICLKSEL - HS LSPI clock source select */ +/*! @{ */ +#define SYSCON_HSLSPICLKSEL_SEL_MASK (0x7U) +#define SYSCON_HSLSPICLKSEL_SEL_SHIFT (0U) +/*! SEL - HS LSPI clock source select. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..No clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_HSLSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HSLSPICLKSEL_SEL_SHIFT)) & SYSCON_HSLSPICLKSEL_SEL_MASK) +/*! @} */ + +/*! @name MCLKCLKSEL - MCLK clock source select */ +/*! @{ */ +#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) +#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) +/*! SEL - MCLK clock source select. + * 0b000..FRO 96 MHz clock. + * 0b001..PLL0 clock. + * 0b010..Reserved. + * 0b011..Reserved. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SCTCLKSEL - SCTimer/PWM clock source select */ +/*! @{ */ +#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) +#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) +/*! SEL - SCTimer/PWM clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..CLKIN clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..MCLK clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SDIOCLKSEL - SDIO clock source select */ +/*! @{ */ +#define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U) +#define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U) +/*! SEL - SDIO clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..PLL1 clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 */ +/*! @{ */ +#define SYSCON_SYSTICKCLKDIV0_DIV_MASK (0xFFU) +#define SYSCON_SYSTICKCLKDIV0_DIV_SHIFT (0U) +#define SYSCON_SYSTICKCLKDIV0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV0_DIV_MASK) +#define SYSCON_SYSTICKCLKDIV0_RESET_MASK (0x20000000U) +#define SYSCON_SYSTICKCLKDIV0_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SYSTICKCLKDIV0_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV0_RESET_MASK) +#define SYSCON_SYSTICKCLKDIV0_HALT_MASK (0x40000000U) +#define SYSCON_SYSTICKCLKDIV0_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SYSTICKCLKDIV0_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV0_HALT_MASK) +#define SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK (0x80000000U) +#define SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SYSTICKCLKDIV0_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK) +/*! @} */ + +/*! @name SYSTICKCLKDIV1 - System Tick Timer divider for CPU1 */ +/*! @{ */ +#define SYSCON_SYSTICKCLKDIV1_DIV_MASK (0xFFU) +#define SYSCON_SYSTICKCLKDIV1_DIV_SHIFT (0U) +#define SYSCON_SYSTICKCLKDIV1_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV1_DIV_MASK) +#define SYSCON_SYSTICKCLKDIV1_RESET_MASK (0x20000000U) +#define SYSCON_SYSTICKCLKDIV1_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SYSTICKCLKDIV1_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV1_RESET_MASK) +#define SYSCON_SYSTICKCLKDIV1_HALT_MASK (0x40000000U) +#define SYSCON_SYSTICKCLKDIV1_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SYSTICKCLKDIV1_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV1_HALT_MASK) +#define SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK (0x80000000U) +#define SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SYSTICKCLKDIV1_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK) +/*! @} */ + +/*! @name TRACECLKDIV - TRACE clock divider */ +/*! @{ */ +#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) +#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) +#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) +#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) +#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) +#define SYSCON_TRACECLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_TRACECLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_TRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_TRACECLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 */ +/*! @{ */ +#define SYSCON_FLEXFRG0CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG0CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG0CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG0CTRL_DIV_MASK) +#define SYSCON_FLEXFRG0CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG0CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG0CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG0CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 */ +/*! @{ */ +#define SYSCON_FLEXFRG1CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG1CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG1CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG1CTRL_DIV_MASK) +#define SYSCON_FLEXFRG1CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG1CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG1CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG1CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 */ +/*! @{ */ +#define SYSCON_FLEXFRG2CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG2CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG2CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG2CTRL_DIV_MASK) +#define SYSCON_FLEXFRG2CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG2CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG2CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG2CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 */ +/*! @{ */ +#define SYSCON_FLEXFRG3CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG3CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG3CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG3CTRL_DIV_MASK) +#define SYSCON_FLEXFRG3CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG3CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG3CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG3CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 */ +/*! @{ */ +#define SYSCON_FLEXFRG4CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG4CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG4CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG4CTRL_DIV_MASK) +#define SYSCON_FLEXFRG4CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG4CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG4CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG4CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 */ +/*! @{ */ +#define SYSCON_FLEXFRG5CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG5CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG5CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG5CTRL_DIV_MASK) +#define SYSCON_FLEXFRG5CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG5CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG5CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG5CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 */ +/*! @{ */ +#define SYSCON_FLEXFRG6CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG6CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG6CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG6CTRL_DIV_MASK) +#define SYSCON_FLEXFRG6CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG6CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG6CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG6CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 */ +/*! @{ */ +#define SYSCON_FLEXFRG7CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG7CTRL_DIV_SHIFT (0U) +#define SYSCON_FLEXFRG7CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG7CTRL_DIV_MASK) +#define SYSCON_FLEXFRG7CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG7CTRL_MULT_SHIFT (8U) +#define SYSCON_FLEXFRG7CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG7CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRGXCTRL - Peripheral reset control register */ +/*! @{ */ +#define SYSCON_FLEXFRGXCTRL_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_FLEXFRGXCTRL_DATA_SHIFT (0U) +#define SYSCON_FLEXFRGXCTRL_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRGXCTRL_DATA_SHIFT)) & SYSCON_FLEXFRGXCTRL_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_FLEXFRGXCTRL */ +#define SYSCON_FLEXFRGXCTRL_COUNT (8U) + +/*! @name AHBCLKDIV - System clock divider */ +/*! @{ */ +#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) +#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) +#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) +#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) +#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name CLKOUTDIV - CLKOUT clock divider */ +/*! @{ */ +#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) +#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) +#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) +#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) +#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) +#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) +#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) +#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name FROHFDIV - FRO_HF (96MHz) clock divider */ +/*! @{ */ +#define SYSCON_FROHFDIV_DIV_MASK (0xFFU) +#define SYSCON_FROHFDIV_DIV_SHIFT (0U) +#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) +#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U) +#define SYSCON_FROHFDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK) +#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) +#define SYSCON_FROHFDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) +#define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_FROHFDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name WDTCLKDIV - WDT clock divider */ +/*! @{ */ +#define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU) +#define SYSCON_WDTCLKDIV_DIV_SHIFT (0U) +#define SYSCON_WDTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK) +#define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_WDTCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_WDTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK) +#define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_WDTCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_WDTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK) +#define SYSCON_WDTCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_WDTCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_WDTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_REQFLAG_SHIFT)) & SYSCON_WDTCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name ADCCLKDIV - ADC clock divider */ +/*! @{ */ +#define SYSCON_ADCCLKDIV_DIV_MASK (0x7U) +#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) +#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) +#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) +#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) +#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name USB0CLKDIV - USB0 Clock divider */ +/*! @{ */ +#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) +#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) +#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) +#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) +#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name MCLKDIV - I2S MCLK clock divider */ +/*! @{ */ +#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_MCLKDIV_DIV_SHIFT (0U) +#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) +#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_MCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) +#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_MCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) +#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name SCTCLKDIV - SCT/PWM clock divider */ +/*! @{ */ +#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) +#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) +#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) +#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) +#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name SDIOCLKDIV - SDIO clock divider */ +/*! @{ */ +#define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U) +#define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK) +#define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK) +#define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK) +#define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name PLL0CLKDIV - PLL0 clock divider */ +/*! @{ */ +#define SYSCON_PLL0CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_PLL0CLKDIV_DIV_SHIFT (0U) +#define SYSCON_PLL0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_DIV_SHIFT)) & SYSCON_PLL0CLKDIV_DIV_MASK) +#define SYSCON_PLL0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_PLL0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_PLL0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_RESET_SHIFT)) & SYSCON_PLL0CLKDIV_RESET_MASK) +#define SYSCON_PLL0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_PLL0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_PLL0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_HALT_SHIFT)) & SYSCON_PLL0CLKDIV_HALT_MASK) +#define SYSCON_PLL0CLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_PLL0CLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_PLL0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_REQFLAG_SHIFT)) & SYSCON_PLL0CLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) */ +/*! @{ */ +#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK (0xFFFFFFFFU) +#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT (0U) +/*! CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL). + * 0b00000000000000000000000000000001..update all clock configuration. + * 0b00000000000000000000000000000000..all hardware clock configruration are freeze. + */ +#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK) +/*! @} */ + +/*! @name FMCCR - FMC configuration register */ +/*! @{ */ +#define SYSCON_FMCCR_FLASHTIM_MASK (0xF000U) +#define SYSCON_FMCCR_FLASHTIM_SHIFT (12U) +/*! FLASHTIM - Flash memory access time. + * 0b0000..1 system clock flash access time (for system clock rates up to 11 MHz). + * 0b0001..2 system clocks flash access time (for system clock rates up to 22 MHz). + * 0b0010..3 system clocks flash access time (for system clock rates up to 33 MHz). + * 0b0011..4 system clocks flash access time (for system clock rates up to 44 MHz). + * 0b0100..5 system clocks flash access time (for system clock rates up to 55 MHz). + * 0b0101..6 system clocks flash access time (for system clock rates up to 66 MHz). + * 0b0110..7 system clocks flash access time (for system clock rates up to 77 MHz). + * 0b0111..8 system clocks flash access time (for system clock rates up to 88 MHz). + * 0b1000..9 system clocks flash access time (for system clock rates up to 100 MHz). + */ +#define SYSCON_FMCCR_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FLASHTIM_SHIFT)) & SYSCON_FMCCR_FLASHTIM_MASK) +/*! @} */ + +/*! @name USB0NEEDCLKCTRL - USB0 need clock control */ +/*! @{ */ +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT (0U) +/*! AP_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal control:. + * 0b0..Under hardware control. + * 0b1..Forced high. + */ +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK) +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK (0x2U) +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT (1U) +/*! POL_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. + * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. + * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK) +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK (0x4U) +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT (2U) +/*! AP_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal control:. + * 0b0..Under hardware control. + * 0b1..Forced high. + */ +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK) +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK (0x8U) +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT (3U) +/*! POL_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. + * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. + * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK) +/*! @} */ + +/*! @name USB0NEEDCLKSTAT - USB0 need clock status */ +/*! @{ */ +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) +/*! DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal status:. + * 0b1..USB0 Device clock is high. + * 0b0..USB0 Device clock is low. + */ +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK) +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) +/*! HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal status:. + * 0b1..USB0 Host clock is high. + * 0b0..USB0 Host clock is low. + */ +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK) +/*! @} */ + +/*! @name FMCFLUSH - FMCflush control */ +/*! @{ */ +#define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U) +#define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U) +/*! FLUSH - Flush control + * 0b1..Flush the FMC buffer contents. + * 0b0..No action is performed. + */ +#define SYSCON_FMCFLUSH_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK) +/*! @} */ + +/*! @name MCLKIO - MCLK control */ +/*! @{ */ +#define SYSCON_MCLKIO_MCLKIO_MASK (0xFFFFFFFFU) +#define SYSCON_MCLKIO_MCLKIO_SHIFT (0U) +/*! MCLKIO - MCLK control. + * 0b00000000000000000000000000000000..input mode. + * 0b00000000000000000000000000000001..output mode. + */ +#define SYSCON_MCLKIO_MCLKIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK) +/*! @} */ + +/*! @name USB1NEEDCLKCTRL - USB1 need clock control */ +/*! @{ */ +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT (0U) +/*! AP_HS_DEV_NEEDCLK - USB1 Device need_clock signal control: + * 0b0..HOST_NEEDCLK is under hardware control. + * 0b1..HOST_NEEDCLK is forced high. + */ +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK) +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK (0x2U) +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT (1U) +/*! POL_HS_DEV_NEEDCLK - USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt: + * 0b0..Falling edge of DEV_NEEDCLK triggers wake-up. + * 0b1..Rising edge of DEV_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK) +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK (0x4U) +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT (2U) +/*! AP_HS_HOST_NEEDCLK - USB1 Host need clock signal control: + * 0b0..HOST_NEEDCLK is under hardware control. + * 0b1..HOST_NEEDCLK is forced high. + */ +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK) +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK (0x8U) +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT (3U) +/*! POL_HS_HOST_NEEDCLK - USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. + * 0b0..Falling edge of HOST_NEEDCLK triggers wake-up. + * 0b1..Rising edge of HOST_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK) +#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U) +#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U) +/*! HS_DEV_WAKEUP_N - Software override of device controller PHY wake up logic. + * 0b0..Forces USB1_PHY to wake-up. + * 0b1..Normal USB1_PHY behavior. + */ +#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK) +/*! @} */ + +/*! @name USB1NEEDCLKSTAT - USB1 need clock status */ +/*! @{ */ +#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) +/*! DEV_NEEDCLK - USB1 Device need_clock signal status:. + * 0b1..DEV_NEEDCLK is high. + * 0b0..DEV_NEEDCLK is low. + */ +#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK) +#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) +#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) +/*! HOST_NEEDCLK - USB1 Host need_clock signal status:. + * 0b1..HOST_NEEDCLK is high. + * 0b0..HOST_NEEDCLK is low. + */ +#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK) +/*! @} */ + +/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */ +/*! @{ */ +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U) +/*! CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in. + * 0b00..0 degree shift. + * 0b01..90 degree shift. + * 0b10..180 degree shift. + * 0b11..270 degree shift. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U) +/*! CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. + * 0b00..0 degree shift. + * 0b01..90 degree shift. + * 0b10..180 degree shift. + * 0b11..270 degree shift. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK) +#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) +#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U) +/*! PHASE_ACTIVE - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE. + * 0b0..Bypassed. + * 0b1..Activates phase shift logic. When active, the clock divider is active and phase delays are enabled. + */ +#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U) +/*! CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field. + * 0b1..Enable drive delay. + * 0b0..Disable drive delay. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U) +/*! CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. + * 0b1..Enables sample delay. + * 0b0..Disables sample delay. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK) +/*! @} */ + +/*! @name PLL1CTRL - PLL1 550m control */ +/*! @{ */ +#define SYSCON_PLL1CTRL_SELR_MASK (0xFU) +#define SYSCON_PLL1CTRL_SELR_SHIFT (0U) +#define SYSCON_PLL1CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK) +#define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U) +#define SYSCON_PLL1CTRL_SELI_SHIFT (4U) +#define SYSCON_PLL1CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK) +#define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U) +#define SYSCON_PLL1CTRL_SELP_SHIFT (10U) +#define SYSCON_PLL1CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK) +#define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U) +#define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U) +/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). + * 0b1..PLL input clock is sent directly to the PLL output. + * 0b0..use PLL. + */ +#define SYSCON_PLL1CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. + * 0b1..bypass of the divide-by-2 divider in the post-divider. + * 0b0..use the divide-by-2 divider in the post-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) +#define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U) +#define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U) +#define SYSCON_PLL1CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK) +#define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U) +#define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U) +/*! BWDIRECT - control of the bandwidth of the PLL. + * 0b1..modify the bandwidth of the PLL directly. + * 0b0..the bandwidth is changed synchronously with the feedback-divider. + */ +#define SYSCON_PLL1CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK) +#define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U) +#define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - bypass of the pre-divider. + * 0b1..bypass of the pre-divider. + * 0b0..use the pre-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - bypass of the post-divider. + * 0b1..bypass of the post-divider. + * 0b0..use the post-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) +#define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U) +#define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U) +/*! CLKEN - enable the output clock. + * 0b1..Enable the output clock. + * 0b0..Disable the output clock. + */ +#define SYSCON_PLL1CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK) +#define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U) +#define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U) +#define SYSCON_PLL1CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK) +#define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U) +#define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U) +#define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK) +#define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U) +#define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U) +/*! SKEWEN - Skew mode. + * 0b1..skewmode is enable. + * 0b0..skewmode is disable. + */ +#define SYSCON_PLL1CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK) +/*! @} */ + +/*! @name PLL1STAT - PLL1 550m status */ +/*! @{ */ +#define SYSCON_PLL1STAT_LOCK_MASK (0x1U) +#define SYSCON_PLL1STAT_LOCK_SHIFT (0U) +#define SYSCON_PLL1STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK) +#define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U) +#define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U) +#define SYSCON_PLL1STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK) +#define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U) +#define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U) +#define SYSCON_PLL1STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK) +#define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U) +#define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U) +#define SYSCON_PLL1STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK) +#define SYSCON_PLL1STAT_FRMDET_MASK (0x10U) +#define SYSCON_PLL1STAT_FRMDET_SHIFT (4U) +#define SYSCON_PLL1STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK) +/*! @} */ + +/*! @name PLL1NDEC - PLL1 550m N divider */ +/*! @{ */ +#define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU) +#define SYSCON_PLL1NDEC_NDIV_SHIFT (0U) +#define SYSCON_PLL1NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK) +#define SYSCON_PLL1NDEC_NREQ_MASK (0x100U) +#define SYSCON_PLL1NDEC_NREQ_SHIFT (8U) +#define SYSCON_PLL1NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK) +/*! @} */ + +/*! @name PLL1MDEC - PLL1 550m M divider */ +/*! @{ */ +#define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU) +#define SYSCON_PLL1MDEC_MDIV_SHIFT (0U) +#define SYSCON_PLL1MDEC_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK) +#define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U) +#define SYSCON_PLL1MDEC_MREQ_SHIFT (16U) +#define SYSCON_PLL1MDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK) +/*! @} */ + +/*! @name PLL1PDEC - PLL1 550m P divider */ +/*! @{ */ +#define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU) +#define SYSCON_PLL1PDEC_PDIV_SHIFT (0U) +#define SYSCON_PLL1PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK) +#define SYSCON_PLL1PDEC_PREQ_MASK (0x20U) +#define SYSCON_PLL1PDEC_PREQ_SHIFT (5U) +#define SYSCON_PLL1PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK) +/*! @} */ + +/*! @name PLL0CTRL - PLL0 550m control */ +/*! @{ */ +#define SYSCON_PLL0CTRL_SELR_MASK (0xFU) +#define SYSCON_PLL0CTRL_SELR_SHIFT (0U) +#define SYSCON_PLL0CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK) +#define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U) +#define SYSCON_PLL0CTRL_SELI_SHIFT (4U) +#define SYSCON_PLL0CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK) +#define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U) +#define SYSCON_PLL0CTRL_SELP_SHIFT (10U) +#define SYSCON_PLL0CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK) +#define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U) +#define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U) +/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). + * 0b1..Bypass PLL input clock is sent directly to the PLL output. + * 0b0..use PLL. + */ +#define SYSCON_PLL0CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. + * 0b1..bypass of the divide-by-2 divider in the post-divider. + * 0b0..use the divide-by-2 divider in the post-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) +#define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U) +#define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U) +#define SYSCON_PLL0CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK) +#define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U) +#define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U) +/*! BWDIRECT - Control of the bandwidth of the PLL. + * 0b1..modify the bandwidth of the PLL directly. + * 0b0..the bandwidth is changed synchronously with the feedback-divider. + */ +#define SYSCON_PLL0CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK) +#define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U) +#define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - bypass of the pre-divider. + * 0b1..bypass of the pre-divider. + * 0b0..use the pre-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - bypass of the post-divider. + * 0b1..bypass of the post-divider. + * 0b0..use the post-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) +#define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U) +#define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U) +/*! CLKEN - enable the output clock. + * 0b1..enable the output clock. + * 0b0..disable the output clock. + */ +#define SYSCON_PLL0CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK) +#define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U) +#define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U) +/*! FRMEN - free running mode. + * 0b1..free running mode is enable. + * 0b0..free running mode is disable. + */ +#define SYSCON_PLL0CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK) +#define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U) +#define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U) +#define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK) +#define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U) +#define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U) +/*! SKEWEN - skew mode. + * 0b1..skew mode is enable. + * 0b0..skew mode is disable. + */ +#define SYSCON_PLL0CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK) +/*! @} */ + +/*! @name PLL0STAT - PLL0 550m status */ +/*! @{ */ +#define SYSCON_PLL0STAT_LOCK_MASK (0x1U) +#define SYSCON_PLL0STAT_LOCK_SHIFT (0U) +#define SYSCON_PLL0STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK) +#define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U) +#define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U) +#define SYSCON_PLL0STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK) +#define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U) +#define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U) +#define SYSCON_PLL0STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK) +#define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U) +#define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U) +#define SYSCON_PLL0STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK) +#define SYSCON_PLL0STAT_FRMDET_MASK (0x10U) +#define SYSCON_PLL0STAT_FRMDET_SHIFT (4U) +#define SYSCON_PLL0STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK) +/*! @} */ + +/*! @name PLL0NDEC - PLL0 550m N divider */ +/*! @{ */ +#define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU) +#define SYSCON_PLL0NDEC_NDIV_SHIFT (0U) +#define SYSCON_PLL0NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK) +#define SYSCON_PLL0NDEC_NREQ_MASK (0x100U) +#define SYSCON_PLL0NDEC_NREQ_SHIFT (8U) +#define SYSCON_PLL0NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK) +/*! @} */ + +/*! @name PLL0PDEC - PLL0 550m P divider */ +/*! @{ */ +#define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU) +#define SYSCON_PLL0PDEC_PDIV_SHIFT (0U) +#define SYSCON_PLL0PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK) +#define SYSCON_PLL0PDEC_PREQ_MASK (0x20U) +#define SYSCON_PLL0PDEC_PREQ_SHIFT (5U) +#define SYSCON_PLL0PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK) +/*! @} */ + +/*! @name PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 */ +/*! @{ */ +#define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU) +#define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U) +#define SYSCON_PLL0SSCG0_MD_LBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK) +/*! @} */ + +/*! @name PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 */ +/*! @{ */ +#define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U) +#define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U) +#define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK) +#define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U) +#define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U) +#define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK) +#define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) +#define SYSCON_PLL0SSCG1_MF_SHIFT (2U) +#define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK) +#define SYSCON_PLL0SSCG1_MR_MASK (0xE0U) +#define SYSCON_PLL0SSCG1_MR_SHIFT (5U) +#define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK) +#define SYSCON_PLL0SSCG1_MC_MASK (0x300U) +#define SYSCON_PLL0SSCG1_MC_SHIFT (8U) +#define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK) +#define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U) +#define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U) +#define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) +#define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U) +#define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U) +#define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK) +#define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U) +#define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U) +#define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK) +#define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U) +#define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U) +#define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK) +/*! @} */ + +/*! @name CPUCTRL - CPU Control for multiple processors */ +/*! @{ */ +#define SYSCON_CPUCTRL_CPU1CLKEN_MASK (0x8U) +#define SYSCON_CPUCTRL_CPU1CLKEN_SHIFT (3U) +/*! CPU1CLKEN - CPU1 clock enable. + * 0b1..The CPU1 clock is enabled. + * 0b0..The CPU1 clock is not enabled. + */ +#define SYSCON_CPUCTRL_CPU1CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1CLKEN_SHIFT)) & SYSCON_CPUCTRL_CPU1CLKEN_MASK) +#define SYSCON_CPUCTRL_CPU1RSTEN_MASK (0x20U) +#define SYSCON_CPUCTRL_CPU1RSTEN_SHIFT (5U) +/*! CPU1RSTEN - CPU1 reset. + * 0b1..The CPU1 is being reset. + * 0b0..The CPU1 is not being reset. + */ +#define SYSCON_CPUCTRL_CPU1RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1RSTEN_SHIFT)) & SYSCON_CPUCTRL_CPU1RSTEN_MASK) +/*! @} */ + +/*! @name CPBOOT - Coprocessor Boot Address */ +/*! @{ */ +#define SYSCON_CPBOOT_CPBOOT_MASK (0xFFFFFFFFU) +#define SYSCON_CPBOOT_CPBOOT_SHIFT (0U) +#define SYSCON_CPBOOT_CPBOOT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_CPBOOT_SHIFT)) & SYSCON_CPBOOT_CPBOOT_MASK) +/*! @} */ + +/*! @name CPSTAT - CPU Status */ +/*! @{ */ +#define SYSCON_CPSTAT_CPU0SLEEPING_MASK (0x1U) +#define SYSCON_CPSTAT_CPU0SLEEPING_SHIFT (0U) +/*! CPU0SLEEPING - The CPU0 sleeping state. + * 0b1..the CPU is sleeping. + * 0b0..the CPU is not sleeping. + */ +#define SYSCON_CPSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU0SLEEPING_MASK) +#define SYSCON_CPSTAT_CPU1SLEEPING_MASK (0x2U) +#define SYSCON_CPSTAT_CPU1SLEEPING_SHIFT (1U) +/*! CPU1SLEEPING - The CPU1 sleeping state. + * 0b1..the CPU is sleeping. + * 0b0..the CPU is not sleeping. + */ +#define SYSCON_CPSTAT_CPU1SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU1SLEEPING_MASK) +#define SYSCON_CPSTAT_CPU0LOCKUP_MASK (0x4U) +#define SYSCON_CPSTAT_CPU0LOCKUP_SHIFT (2U) +/*! CPU0LOCKUP - The CPU0 lockup state. + * 0b1..the CPU is in lockup. + * 0b0..the CPU is not in lockup. + */ +#define SYSCON_CPSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU0LOCKUP_MASK) +#define SYSCON_CPSTAT_CPU1LOCKUP_MASK (0x8U) +#define SYSCON_CPSTAT_CPU1LOCKUP_SHIFT (3U) +/*! CPU1LOCKUP - The CPU1 lockup state. + * 0b1..the CPU is in lockup. + * 0b0..the CPU is not in lockup. + */ +#define SYSCON_CPSTAT_CPU1LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU1LOCKUP_MASK) +/*! @} */ + +/*! @name CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures */ +/*! @{ */ +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U) +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U) +/*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U) +/*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK) +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U) +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U) +/*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK) +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U) +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U) +/*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK) +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) +/*! CLKIN_ENA - Enable clock_in clock for clock module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) +/*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U) +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U) +/*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK) +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U) +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U) +/*! XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK) +#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U) +#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U) +/*! PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK) +/*! @} */ + +/*! @name COMP_INT_CTRL - Comparator Interrupt control */ +/*! @{ */ +#define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U) +#define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U) +/*! INT_ENABLE - Analog Comparator interrupt enable control:. + * 0b1..interrupt enable. + * 0b0..interrupt disable. + */ +#define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK) +#define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U) +#define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U) +/*! INT_CLEAR - Analog Comparator interrupt clear. + * 0b0..No effect. + * 0b1..Clear the interrupt. Self-cleared bit. + */ +#define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK) +#define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU) +#define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U) +/*! INT_CTRL - Comparator interrupt type selector:. + * 0b000..The analog comparator interrupt edge sensitive is disabled. + * 0b010..analog comparator interrupt is rising edge sensitive. + * 0b100..analog comparator interrupt is falling edge sensitive. + * 0b110..analog comparator interrupt is rising and falling edge sensitive. + * 0b001..The analog comparator interrupt level sensitive is disabled. + * 0b011..Analog Comparator interrupt is high level sensitive. + * 0b101..Analog Comparator interrupt is low level sensitive. + * 0b111..The analog comparator interrupt level sensitive is disabled. + */ +#define SYSCON_COMP_INT_CTRL_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK) +#define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U) +#define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U) +/*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. + * 0b0..Select Analog Comparator filtered output as input for interrupt detection. + * 0b1..Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when + * Analog comparator is used as wake up source in Power down mode. + */ +#define SYSCON_COMP_INT_CTRL_INT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK) +/*! @} */ + +/*! @name COMP_INT_STATUS - Comparator Interrupt status */ +/*! @{ */ +#define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U) +#define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U) +/*! STATUS - Interrupt status BEFORE Interrupt Enable. + * 0b0..no interrupt pending. + * 0b1..interrupt pending. + */ +#define SYSCON_COMP_INT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK) +#define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U) +#define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U) +/*! INT_STATUS - Interrupt status AFTER Interrupt Enable. + * 0b0..no interrupt pending. + * 0b1..interrupt pending. + */ +#define SYSCON_COMP_INT_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) +#define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U) +#define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U) +/*! VAL - comparator analog output. + * 0b1..P+ is greater than P-. + * 0b0..P+ is smaller than P-. + */ +#define SYSCON_COMP_INT_STATUS_VAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK) +/*! @} */ + +/*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */ +/*! @{ */ +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U) +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U) +/*! ROM - Control automatic clock gating of ROM controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK (0x2U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT (1U) +/*! RAMX_CTRL - Control automatic clock gating of RAMX controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK (0x4U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT (2U) +/*! RAM0_CTRL - Control automatic clock gating of RAM0 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK (0x8U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT (3U) +/*! RAM1_CTRL - Control automatic clock gating of RAM1 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK (0x10U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT (4U) +/*! RAM2_CTRL - Control automatic clock gating of RAM2 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK (0x20U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT (5U) +/*! RAM3_CTRL - Control automatic clock gating of RAM3 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK (0x40U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT (6U) +/*! RAM4_CTRL - Control automatic clock gating of RAM4 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U) +/*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U) +/*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U) +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U) +/*! CRCGEN - Control automatic clock gating of CRCGEN controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U) +/*! SDMA0 - Control automatic clock gating of DMA0 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U) +/*! SDMA1 - Control automatic clock gating of DMA1 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK (0x4000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT (14U) +/*! USB0 - Control automatic clock gating of USB controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U) +/*! SYSCON - Control automatic clock gating of synchronous system controller registers bank. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U) +/*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. + * 0b1100000011011110..Bit Fields 0 - 15 of this register are updated + * 0b0000000000000000..Bit Fields 0 - 15 of this register are not updated + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK) +/*! @} */ + +/*! @name GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module */ +/*! @{ */ +#define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U) +#define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U) +/*! PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module. + * 0b1..bypass of the first stage of synchonization inside GPIO_INT module. + * 0b0..use the first stage of synchonization inside GPIO_INT module. + */ +#define SYSCON_GPIOPSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK) +/*! @} */ + +/*! @name DEBUG_LOCK_EN - Control write access to security registers. */ +/*! @{ */ +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) +/*! LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, + * CODESECURITYPROTCPU1, CPU0_DEBUG_FEATURES, CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. + * 0b1010..1010: Enable write access to all 6 registers. + * 0b0000..Any other value than b1010: disable write access to all 6 registers. + */ +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control. */ +/*! @{ */ +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK (0x300U) +#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT (8U) +/*! CPU1_DBGEN - CPU1 Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK) +#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK (0xC00U) +#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT (10U) +/*! CPU1_NIDEN - CPU1 Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register. */ +/*! @{ */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 (CPU0) Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK (0x300U) +#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT (8U) +/*! CPU1_DBGEN - CPU1 Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK) +#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK (0xC00U) +#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT (10U) +/*! CPU1_NIDEN - CPU1 Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK) +/*! @} */ + +/*! @name KEY_BLOCK - block quiddikey/PUF all index. */ +/*! @{ */ +#define SYSCON_KEY_BLOCK_KEY_BLOCK_MASK (0xFFFFFFFFU) +#define SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT (0U) +#define SYSCON_KEY_BLOCK_KEY_BLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCON_KEY_BLOCK_KEY_BLOCK_MASK) +/*! @} */ + +/*! @name DEBUG_AUTH_BEACON - Debug authentication BEACON register */ +/*! @{ */ +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) +#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) +/*! @} */ + +/*! @name CPUCFG - CPUs configuration register */ +/*! @{ */ +#define SYSCON_CPUCFG_CPU1ENABLE_MASK (0x4U) +#define SYSCON_CPUCFG_CPU1ENABLE_SHIFT (2U) +/*! CPU1ENABLE - Enable CPU1. + * 0b0..CPU1 is disable (Processor in reset). + * 0b1..CPU1 is enable. + */ +#define SYSCON_CPUCFG_CPU1ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCFG_CPU1ENABLE_SHIFT)) & SYSCON_CPUCFG_CPU1ENABLE_MASK) +/*! @} */ + +/*! @name DEVICE_ID0 - Device ID */ +/*! @{ */ +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) +/*! @} */ + +/*! @name DIEID - Chip revision ID and Number */ +/*! @{ */ +#define SYSCON_DIEID_REV_ID_MASK (0xFU) +#define SYSCON_DIEID_REV_ID_SHIFT (0U) +#define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK) +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U) +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U) +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCON_Register_Masks */ + + +/* SYSCON - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral SYSCON base address */ + #define SYSCON_BASE (0x50000000u) + /** Peripheral SYSCON base address */ + #define SYSCON_BASE_NS (0x40000000u) + /** Peripheral SYSCON base pointer */ + #define SYSCON ((SYSCON_Type *)SYSCON_BASE) + /** Peripheral SYSCON base pointer */ + #define SYSCON_NS ((SYSCON_Type *)SYSCON_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON_NS } +#else + /** Peripheral SYSCON base address */ + #define SYSCON_BASE (0x40000000u) + /** Peripheral SYSCON base pointer */ + #define SYSCON ((SYSCON_Type *)SYSCON_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON } +#endif + +/*! + * @} + */ /* end of group SYSCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCTL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCTL_Peripheral_Access_Layer SYSCTL Peripheral Access Layer + * @{ + */ + +/** SYSCTL - Register Layout Typedef */ +typedef struct { + __IO uint32_t UPDATELCKOUT; /**< update lock out control, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t FCCTRLSEL[8]; /**< Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[32]; + __IO uint32_t SHAREDCTRLSET[2]; /**< Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1., array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_2[120]; + __I uint32_t USB_HS_STATUS; /**< Status register for USB HS, offset: 0x100 */ +} SYSCTL_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCTL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCTL_Register_Masks SYSCTL Register Masks + * @{ + */ + +/*! @name UPDATELCKOUT - update lock out control */ +/*! @{ */ +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U) +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U) +/*! UPDATELCKOUT - All Registers + * 0b0..Normal Mode. Can be written to. + * 0b1..Protected Mode. Cannot be written to. + */ +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK) +/*! @} */ + +/*! @name FCCTRLSEL - Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7 */ +/*! @{ */ +#define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U) +#define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U) +/*! SCKINSEL - Selects the source for SCK going into this Flexcomm. + * 0b00..Selects the dedicated FCn_SCK function for this Flexcomm. + * 0b01..SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK) +#define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U) +#define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U) +/*! WSINSEL - Selects the source for WS going into this Flexcomm. + * 0b00..Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. + * 0b01..WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK) +#define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U) +#define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U) +/*! DATAINSEL - Selects the source for DATA input to this Flexcomm. + * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. + * 0b01..Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK) +#define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U) +#define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U) +/*! DATAOUTSEL - Selects the source for DATA output from this Flexcomm. + * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. + * 0b01..Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_DATAOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK) +/*! @} */ + +/* The count of SYSCTL_FCCTRLSEL */ +#define SYSCTL_FCCTRLSEL_COUNT (8U) + +/*! @name SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */ +/*! @{ */ +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U) +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U) +/*! SHAREDSCKSEL - Selects the source for SCK of this shared signal set. + * 0b000..SCK for this shared signal set comes from Flexcomm 0. + * 0b001..SCK for this shared signal set comes from Flexcomm 1. + * 0b010..SCK for this shared signal set comes from Flexcomm 2. + * 0b011..SCK for this shared signal set comes from Flexcomm 3. + * 0b100..SCK for this shared signal set comes from Flexcomm 4. + * 0b101..SCK for this shared signal set comes from Flexcomm 5. + * 0b110..SCK for this shared signal set comes from Flexcomm 6. + * 0b111..SCK for this shared signal set comes from Flexcomm 7. + */ +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK) +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U) +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U) +/*! SHAREDWSSEL - Selects the source for WS of this shared signal set. + * 0b000..WS for this shared signal set comes from Flexcomm 0. + * 0b001..WS for this shared signal set comes from Flexcomm 1. + * 0b010..WS for this shared signal set comes from Flexcomm 2. + * 0b011..WS for this shared signal set comes from Flexcomm 3. + * 0b100..WS for this shared signal set comes from Flexcomm 4. + * 0b101..WS for this shared signal set comes from Flexcomm 5. + * 0b110..WS for this shared signal set comes from Flexcomm 6. + * 0b111..WS for this shared signal set comes from Flexcomm 7. + */ +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK) +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U) +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U) +/*! SHAREDDATASEL - Selects the source for DATA input for this shared signal set. + * 0b000..DATA input for this shared signal set comes from Flexcomm 0. + * 0b001..DATA input for this shared signal set comes from Flexcomm 1. + * 0b010..DATA input for this shared signal set comes from Flexcomm 2. + * 0b011..DATA input for this shared signal set comes from Flexcomm 3. + * 0b100..DATA input for this shared signal set comes from Flexcomm 4. + * 0b101..DATA input for this shared signal set comes from Flexcomm 5. + * 0b110..DATA input for this shared signal set comes from Flexcomm 6. + * 0b111..DATA input for this shared signal set comes from Flexcomm 7. + */ +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK) +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U) +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U) +/*! FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC0 does not contribute to this shared set. + * 0b1..Data output from FC0 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK) +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U) +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U) +/*! FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC1 does not contribute to this shared set. + * 0b1..Data output from FC1 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK) +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK (0x40000U) +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT (18U) +/*! FC2DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC2 does not contribute to this shared set. + * 0b1..Data output from FC2 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK) +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U) +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U) +/*! FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC4 does not contribute to this shared set. + * 0b1..Data output from FC4 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK) +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U) +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U) +/*! FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC5 does not contribute to this shared set. + * 0b1..Data output from FC5 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK) +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U) +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U) +/*! FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC6 does not contribute to this shared set. + * 0b1..Data output from FC6 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK) +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U) +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U) +/*! FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC7 does not contribute to this shared set. + * 0b1..Data output from FC7 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK) +/*! @} */ + +/* The count of SYSCTL_SHAREDCTRLSET */ +#define SYSCTL_SHAREDCTRLSET_COUNT (2U) + +/*! @name USB_HS_STATUS - Status register for USB HS */ +/*! @{ */ +#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK (0x1U) +#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT (0U) +/*! USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply. + * 0b0..3v3 supply is good. + * 0b1..3v3 supply is too low. + */ +#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT)) & SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCTL_Register_Masks */ + + +/* SYSCTL - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE (0x50023000u) + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE_NS (0x40023000u) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL_NS ((SYSCTL_Type *)SYSCTL_BASE_NS) + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS { SYSCTL } + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS_NS { SYSCTL_BASE_NS } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS_NS { SYSCTL_NS } +#else + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE (0x40023000u) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS { SYSCTL } +#endif + +/*! + * @} + */ /* end of group SYSCTL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer + * @{ + */ + +/** USART - Register Layout Typedef */ +typedef struct { + __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ + __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ + __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ + __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ + __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ + __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ + uint8_t RESERVED_1[3536]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_3[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_4[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + uint8_t RESERVED_6[440]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} USART_Type; + +/* ---------------------------------------------------------------------------- + -- USART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Register_Masks USART Register Masks + * @{ + */ + +/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ +/*! @{ */ +#define USART_CFG_ENABLE_MASK (0x1U) +#define USART_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - USART Enable. + * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, + * all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control + * bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the + * transmitter has been reset and is therefore available. + * 0b1..Enabled. The USART is enabled for operation. + */ +#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) +#define USART_CFG_DATALEN_MASK (0xCU) +#define USART_CFG_DATALEN_SHIFT (2U) +/*! DATALEN - Selects the data size for the USART. + * 0b00..7 bit Data length. + * 0b01..8 bit Data length. + * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. + * 0b11..Reserved. + */ +#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) +#define USART_CFG_PARITYSEL_MASK (0x30U) +#define USART_CFG_PARITYSEL_SHIFT (4U) +/*! PARITYSEL - Selects what type of parity is used by the USART. + * 0b00..No parity. + * 0b01..Reserved. + * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, + * and the number of 1s in a received character is expected to be even. + * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, + * and the number of 1s in a received character is expected to be odd. + */ +#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) +#define USART_CFG_STOPLEN_MASK (0x40U) +#define USART_CFG_STOPLEN_SHIFT (6U) +/*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. + * 0b0..1 stop bit. + * 0b1..2 stop bits. This setting should only be used for asynchronous communication. + */ +#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) +#define USART_CFG_MODE32K_MASK (0x80U) +#define USART_CFG_MODE32K_SHIFT (7U) +/*! MODE32K - Selects standard or 32 kHz clocking mode. + * 0b0..Disabled. USART uses standard clocking. + * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. + */ +#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) +#define USART_CFG_LINMODE_MASK (0x100U) +#define USART_CFG_LINMODE_SHIFT (8U) +/*! LINMODE - LIN break mode enable. + * 0b0..Disabled. Break detect and generate is configured for normal operation. + * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. + */ +#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) +#define USART_CFG_CTSEN_MASK (0x200U) +#define USART_CFG_CTSEN_SHIFT (9U) +/*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input + * pin, or from the USART's own RTS if loopback mode is enabled. + * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. + * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. + */ +#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) +#define USART_CFG_SYNCEN_MASK (0x800U) +#define USART_CFG_SYNCEN_SHIFT (11U) +/*! SYNCEN - Selects synchronous or asynchronous operation. + * 0b0..Asynchronous mode. + * 0b1..Synchronous mode. + */ +#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) +#define USART_CFG_CLKPOL_MASK (0x1000U) +#define USART_CFG_CLKPOL_SHIFT (12U) +/*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. + * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK. + * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. + */ +#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) +#define USART_CFG_SYNCMST_MASK (0x4000U) +#define USART_CFG_SYNCMST_SHIFT (14U) +/*! SYNCMST - Synchronous mode Master select. + * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. + * 0b1..Master. When synchronous mode is enabled, the USART is a master. + */ +#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) +#define USART_CFG_LOOP_MASK (0x8000U) +#define USART_CFG_LOOP_SHIFT (15U) +/*! LOOP - Selects data loopback mode. + * 0b0..Normal operation. + * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial + * data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD + * and Un_RTS activity will also appear on external pins if these functions are configured to appear on device + * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. + */ +#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) +#define USART_CFG_OETA_MASK (0x40000U) +#define USART_CFG_OETA_SHIFT (18U) +/*! OETA - Output Enable Turnaround time enable for RS-485 operation. + * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. + * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the + * end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins + * before it is deasserted. + */ +#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) +#define USART_CFG_AUTOADDR_MASK (0x80000U) +#define USART_CFG_AUTOADDR_SHIFT (19U) +/*! AUTOADDR - Automatic Address matching enable. + * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the + * possibility of versatile addressing (e.g. respond to more than one address). + * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in + * the ADDR register as the address to match. + */ +#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) +#define USART_CFG_OESEL_MASK (0x100000U) +#define USART_CFG_OESEL_SHIFT (20U) +/*! OESEL - Output Enable Select. + * 0b0..Standard. The RTS signal is used as the standard flow control function. + * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. + */ +#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) +#define USART_CFG_OEPOL_MASK (0x200000U) +#define USART_CFG_OEPOL_SHIFT (21U) +/*! OEPOL - Output Enable Polarity. + * 0b0..Low. If selected by OESEL, the output enable is active low. + * 0b1..High. If selected by OESEL, the output enable is active high. + */ +#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) +#define USART_CFG_RXPOL_MASK (0x400000U) +#define USART_CFG_RXPOL_SHIFT (22U) +/*! RXPOL - Receive data polarity. + * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start + * bit is 0, data is not inverted, and the stop bit is 1. + * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is + * 0, start bit is 1, data is inverted, and the stop bit is 0. + */ +#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) +#define USART_CFG_TXPOL_MASK (0x800000U) +#define USART_CFG_TXPOL_SHIFT (23U) +/*! TXPOL - Transmit data polarity. + * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is + * 0, data is not inverted, and the stop bit is 1. + * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value + * is 0, start bit is 1, data is inverted, and the stop bit is 0. + */ +#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) +/*! @} */ + +/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ +/*! @{ */ +#define USART_CTL_TXBRKEN_MASK (0x2U) +#define USART_CTL_TXBRKEN_SHIFT (1U) +/*! TXBRKEN - Break Enable. + * 0b0..Normal operation. + * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit + * is cleared. A break may be sent without danger of corrupting any currently transmitting character if the + * transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled + * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. + */ +#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) +#define USART_CTL_ADDRDET_MASK (0x4U) +#define USART_CTL_ADDRDET_SHIFT (2U) +/*! ADDRDET - Enable address detect mode. + * 0b0..Disabled. The USART presents all incoming data. + * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data + * (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, + * generating a received data interrupt. Software can then check the data to see if this is an address that + * should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled + * normally. + */ +#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) +#define USART_CTL_TXDIS_MASK (0x40U) +#define USART_CTL_TXDIS_SHIFT (6U) +/*! TXDIS - Transmit Disable. + * 0b0..Not disabled. USART transmitter is not disabled. + * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This + * feature can be used to facilitate software flow control. + */ +#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) +#define USART_CTL_CC_MASK (0x100U) +#define USART_CTL_CC_SHIFT (8U) +/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. + * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to + * complete a character that is being received. + * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on + * Un_RxD independently from transmission on Un_TXD). + */ +#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) +#define USART_CTL_CLRCCONRX_MASK (0x200U) +#define USART_CTL_CLRCCONRX_SHIFT (9U) +/*! CLRCCONRX - Clear Continuous Clock. + * 0b0..No effect. No effect on the CC bit. + * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. + */ +#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) +#define USART_CTL_AUTOBAUD_MASK (0x10000U) +#define USART_CTL_AUTOBAUD_SHIFT (16U) +/*! AUTOBAUD - Autobaud enable. + * 0b0..Disabled. USART is in normal operating mode. + * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The + * first start bit of RX is measured and used the update the BRG register to match the received data rate. + * AUTOBAUD is cleared once this process is complete, or if there is an AERR. + */ +#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) +/*! @} */ + +/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ +/*! @{ */ +#define USART_STAT_RXIDLE_MASK (0x2U) +#define USART_STAT_RXIDLE_SHIFT (1U) +#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) +#define USART_STAT_TXIDLE_MASK (0x8U) +#define USART_STAT_TXIDLE_SHIFT (3U) +#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) +#define USART_STAT_CTS_MASK (0x10U) +#define USART_STAT_CTS_SHIFT (4U) +#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) +#define USART_STAT_DELTACTS_MASK (0x20U) +#define USART_STAT_DELTACTS_SHIFT (5U) +#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) +#define USART_STAT_TXDISSTAT_MASK (0x40U) +#define USART_STAT_TXDISSTAT_SHIFT (6U) +#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) +#define USART_STAT_RXBRK_MASK (0x400U) +#define USART_STAT_RXBRK_SHIFT (10U) +#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) +#define USART_STAT_DELTARXBRK_MASK (0x800U) +#define USART_STAT_DELTARXBRK_SHIFT (11U) +#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) +#define USART_STAT_START_MASK (0x1000U) +#define USART_STAT_START_SHIFT (12U) +#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) +#define USART_STAT_FRAMERRINT_MASK (0x2000U) +#define USART_STAT_FRAMERRINT_SHIFT (13U) +#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) +#define USART_STAT_PARITYERRINT_MASK (0x4000U) +#define USART_STAT_PARITYERRINT_SHIFT (14U) +#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) +#define USART_STAT_RXNOISEINT_MASK (0x8000U) +#define USART_STAT_RXNOISEINT_SHIFT (15U) +#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) +#define USART_STAT_ABERR_MASK (0x10000U) +#define USART_STAT_ABERR_SHIFT (16U) +#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ +#define USART_INTENSET_TXIDLEEN_MASK (0x8U) +#define USART_INTENSET_TXIDLEEN_SHIFT (3U) +#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) +#define USART_INTENSET_DELTACTSEN_MASK (0x20U) +#define USART_INTENSET_DELTACTSEN_SHIFT (5U) +#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) +#define USART_INTENSET_TXDISEN_MASK (0x40U) +#define USART_INTENSET_TXDISEN_SHIFT (6U) +#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) +#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) +#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) +#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) +#define USART_INTENSET_STARTEN_MASK (0x1000U) +#define USART_INTENSET_STARTEN_SHIFT (12U) +#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) +#define USART_INTENSET_FRAMERREN_MASK (0x2000U) +#define USART_INTENSET_FRAMERREN_SHIFT (13U) +#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) +#define USART_INTENSET_PARITYERREN_MASK (0x4000U) +#define USART_INTENSET_PARITYERREN_SHIFT (14U) +#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) +#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) +#define USART_INTENSET_RXNOISEEN_SHIFT (15U) +#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) +#define USART_INTENSET_ABERREN_MASK (0x10000U) +#define USART_INTENSET_ABERREN_SHIFT (16U) +#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ +/*! @{ */ +#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) +#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) +#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) +#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) +#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) +#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) +#define USART_INTENCLR_TXDISCLR_MASK (0x40U) +#define USART_INTENCLR_TXDISCLR_SHIFT (6U) +#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) +#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) +#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) +#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) +#define USART_INTENCLR_STARTCLR_MASK (0x1000U) +#define USART_INTENCLR_STARTCLR_SHIFT (12U) +#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) +#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) +#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) +#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) +#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) +#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) +#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) +#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) +#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) +#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) +#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) +#define USART_INTENCLR_ABERRCLR_SHIFT (16U) +#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) +/*! @} */ + +/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ +/*! @{ */ +#define USART_BRG_BRGVAL_MASK (0xFFFFU) +#define USART_BRG_BRGVAL_SHIFT (0U) +#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ +/*! @{ */ +#define USART_INTSTAT_TXIDLE_MASK (0x8U) +#define USART_INTSTAT_TXIDLE_SHIFT (3U) +#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) +#define USART_INTSTAT_DELTACTS_MASK (0x20U) +#define USART_INTSTAT_DELTACTS_SHIFT (5U) +#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) +#define USART_INTSTAT_TXDISINT_MASK (0x40U) +#define USART_INTSTAT_TXDISINT_SHIFT (6U) +#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) +#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) +#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) +#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) +#define USART_INTSTAT_START_MASK (0x1000U) +#define USART_INTSTAT_START_SHIFT (12U) +#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) +#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) +#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) +#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) +#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) +#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) +#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) +#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) +#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) +#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) +#define USART_INTSTAT_ABERRINT_MASK (0x10000U) +#define USART_INTSTAT_ABERRINT_SHIFT (16U) +#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) +/*! @} */ + +/*! @name OSR - Oversample selection register for asynchronous communication. */ +/*! @{ */ +#define USART_OSR_OSRVAL_MASK (0xFU) +#define USART_OSR_OSRVAL_SHIFT (0U) +#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) +/*! @} */ + +/*! @name ADDR - Address register for automatic address matching. */ +/*! @{ */ +#define USART_ADDR_ADDRESS_MASK (0xFFU) +#define USART_ADDR_ADDRESS_SHIFT (0U) +#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ +#define USART_FIFOCFG_ENABLETX_MASK (0x1U) +#define USART_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) +#define USART_FIFOCFG_ENABLERX_MASK (0x2U) +#define USART_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) +#define USART_FIFOCFG_SIZE_MASK (0x30U) +#define USART_FIFOCFG_SIZE_SHIFT (4U) +#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) +#define USART_FIFOCFG_DMATX_MASK (0x1000U) +#define USART_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) +#define USART_FIFOCFG_DMARX_MASK (0x2000U) +#define USART_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) +#define USART_FIFOCFG_WAKETX_MASK (0x4000U) +#define USART_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) +#define USART_FIFOCFG_WAKERX_MASK (0x8000U) +#define USART_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in + * FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) +#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) +#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) +#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) +#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ +#define USART_FIFOSTAT_TXERR_MASK (0x1U) +#define USART_FIFOSTAT_TXERR_SHIFT (0U) +#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) +#define USART_FIFOSTAT_RXERR_MASK (0x2U) +#define USART_FIFOSTAT_RXERR_SHIFT (1U) +#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) +#define USART_FIFOSTAT_PERINT_MASK (0x8U) +#define USART_FIFOSTAT_PERINT_SHIFT (3U) +#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) +#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) +#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) +#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) +#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) +#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) +#define USART_FIFOSTAT_RXFULL_MASK (0x80U) +#define USART_FIFOSTAT_RXFULL_SHIFT (7U) +#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) +#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define USART_FIFOSTAT_TXLVL_SHIFT (8U) +#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) +#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define USART_FIFOSTAT_RXLVL_SHIFT (16U) +#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ +#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) +#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) +#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) +#define USART_FIFOTRIG_TXLVL_SHIFT (8U) +#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) +#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define USART_FIFOTRIG_RXLVL_SHIFT (16U) +#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ +#define USART_FIFOINTENSET_TXERR_MASK (0x1U) +#define USART_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) +#define USART_FIFOINTENSET_RXERR_MASK (0x2U) +#define USART_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) +#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) +#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases + * to the level specified by TXLVL in the FIFOTRIG register. + */ +#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) +#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) +#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level + * increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ +#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) +#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) +#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) +#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) +#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) +#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) +#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) +#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) +#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) +#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ +#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) +#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) +#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) +#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) +#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) +#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) +#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) +#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) +#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) +#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) +#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) +#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) +#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ +#define USART_FIFOWR_TXDATA_MASK (0x1FFU) +#define USART_FIFOWR_TXDATA_SHIFT (0U) +#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ +#define USART_FIFORD_RXDATA_MASK (0x1FFU) +#define USART_FIFORD_RXDATA_SHIFT (0U) +#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) +#define USART_FIFORD_FRAMERR_MASK (0x2000U) +#define USART_FIFORD_FRAMERR_SHIFT (13U) +#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) +#define USART_FIFORD_PARITYERR_MASK (0x4000U) +#define USART_FIFORD_PARITYERR_SHIFT (14U) +#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) +#define USART_FIFORD_RXNOISE_MASK (0x8000U) +#define USART_FIFORD_RXNOISE_SHIFT (15U) +#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ +#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) +#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) +#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) +#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) +#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) +#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) +#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) +#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) +#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) +#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) +#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) +#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ +#define USART_ID_APERTURE_MASK (0xFFU) +#define USART_ID_APERTURE_SHIFT (0U) +#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) +#define USART_ID_MINOR_REV_MASK (0xF00U) +#define USART_ID_MINOR_REV_SHIFT (8U) +#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) +#define USART_ID_MAJOR_REV_MASK (0xF000U) +#define USART_ID_MAJOR_REV_SHIFT (12U) +#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) +#define USART_ID_ID_MASK (0xFFFF0000U) +#define USART_ID_ID_SHIFT (16U) +#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USART_Register_Masks */ + + +/* USART - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral USART0 base address */ + #define USART0_BASE (0x50086000u) + /** Peripheral USART0 base address */ + #define USART0_BASE_NS (0x40086000u) + /** Peripheral USART0 base pointer */ + #define USART0 ((USART_Type *)USART0_BASE) + /** Peripheral USART0 base pointer */ + #define USART0_NS ((USART_Type *)USART0_BASE_NS) + /** Peripheral USART1 base address */ + #define USART1_BASE (0x50087000u) + /** Peripheral USART1 base address */ + #define USART1_BASE_NS (0x40087000u) + /** Peripheral USART1 base pointer */ + #define USART1 ((USART_Type *)USART1_BASE) + /** Peripheral USART1 base pointer */ + #define USART1_NS ((USART_Type *)USART1_BASE_NS) + /** Peripheral USART2 base address */ + #define USART2_BASE (0x50088000u) + /** Peripheral USART2 base address */ + #define USART2_BASE_NS (0x40088000u) + /** Peripheral USART2 base pointer */ + #define USART2 ((USART_Type *)USART2_BASE) + /** Peripheral USART2 base pointer */ + #define USART2_NS ((USART_Type *)USART2_BASE_NS) + /** Peripheral USART3 base address */ + #define USART3_BASE (0x50089000u) + /** Peripheral USART3 base address */ + #define USART3_BASE_NS (0x40089000u) + /** Peripheral USART3 base pointer */ + #define USART3 ((USART_Type *)USART3_BASE) + /** Peripheral USART3 base pointer */ + #define USART3_NS ((USART_Type *)USART3_BASE_NS) + /** Peripheral USART4 base address */ + #define USART4_BASE (0x5008A000u) + /** Peripheral USART4 base address */ + #define USART4_BASE_NS (0x4008A000u) + /** Peripheral USART4 base pointer */ + #define USART4 ((USART_Type *)USART4_BASE) + /** Peripheral USART4 base pointer */ + #define USART4_NS ((USART_Type *)USART4_BASE_NS) + /** Peripheral USART5 base address */ + #define USART5_BASE (0x50096000u) + /** Peripheral USART5 base address */ + #define USART5_BASE_NS (0x40096000u) + /** Peripheral USART5 base pointer */ + #define USART5 ((USART_Type *)USART5_BASE) + /** Peripheral USART5 base pointer */ + #define USART5_NS ((USART_Type *)USART5_BASE_NS) + /** Peripheral USART6 base address */ + #define USART6_BASE (0x50097000u) + /** Peripheral USART6 base address */ + #define USART6_BASE_NS (0x40097000u) + /** Peripheral USART6 base pointer */ + #define USART6 ((USART_Type *)USART6_BASE) + /** Peripheral USART6 base pointer */ + #define USART6_NS ((USART_Type *)USART6_BASE_NS) + /** Peripheral USART7 base address */ + #define USART7_BASE (0x50098000u) + /** Peripheral USART7 base address */ + #define USART7_BASE_NS (0x40098000u) + /** Peripheral USART7 base pointer */ + #define USART7 ((USART_Type *)USART7_BASE) + /** Peripheral USART7 base pointer */ + #define USART7_NS ((USART_Type *)USART7_BASE_NS) + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS_NS { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS_NS { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS } +#else + /** Peripheral USART0 base address */ + #define USART0_BASE (0x40086000u) + /** Peripheral USART0 base pointer */ + #define USART0 ((USART_Type *)USART0_BASE) + /** Peripheral USART1 base address */ + #define USART1_BASE (0x40087000u) + /** Peripheral USART1 base pointer */ + #define USART1 ((USART_Type *)USART1_BASE) + /** Peripheral USART2 base address */ + #define USART2_BASE (0x40088000u) + /** Peripheral USART2 base pointer */ + #define USART2 ((USART_Type *)USART2_BASE) + /** Peripheral USART3 base address */ + #define USART3_BASE (0x40089000u) + /** Peripheral USART3 base pointer */ + #define USART3 ((USART_Type *)USART3_BASE) + /** Peripheral USART4 base address */ + #define USART4_BASE (0x4008A000u) + /** Peripheral USART4 base pointer */ + #define USART4 ((USART_Type *)USART4_BASE) + /** Peripheral USART5 base address */ + #define USART5_BASE (0x40096000u) + /** Peripheral USART5 base pointer */ + #define USART5 ((USART_Type *)USART5_BASE) + /** Peripheral USART6 base address */ + #define USART6_BASE (0x40097000u) + /** Peripheral USART6 base pointer */ + #define USART6 ((USART_Type *)USART6_BASE) + /** Peripheral USART7 base address */ + #define USART7_BASE (0x40098000u) + /** Peripheral USART7 base pointer */ + #define USART7 ((USART_Type *)USART7_BASE) + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } +#endif +/** Interrupt vectors for the USART peripheral type */ +#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group USART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ + __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ + __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ + __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ + __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ + __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ + __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ + __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ + __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ + __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ + __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ + uint8_t RESERVED_0[8]; + __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name DEVCMDSTAT - USB Device Command/Status register */ +/*! @{ */ +#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) +#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) +#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) +#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) +#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) +#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) +#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) +#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: + * 0b0..USB_NEEDCLK has normal function. + * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. + */ +#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) +#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) +#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +/*! LPM_SUP - LPM Supported: + * 0b0..LPM not supported. + * 0b1..LPM supported. + */ +#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) +#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) +#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) +#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) +#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) +#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) +#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +/*! INTONNAK_CO - Interrupt on NAK for control OUT EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) +#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) +#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +/*! INTONNAK_CI - Interrupt on NAK for control IN EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) +#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) +#define USB_DEVCMDSTAT_DCON_SHIFT (16U) +#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) +#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) +#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) +#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) +#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) +#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) +#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) +#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) +#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) +#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) +#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) +#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) +#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) +#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) +#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) +#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) +#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) +/*! @} */ + +/*! @name INFO - USB Info register */ +/*! @{ */ +#define USB_INFO_FRAME_NR_MASK (0x7FFU) +#define USB_INFO_FRAME_NR_SHIFT (0U) +#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) +#define USB_INFO_ERR_CODE_MASK (0x7800U) +#define USB_INFO_ERR_CODE_SHIFT (11U) +/*! ERR_CODE - The error code which last occurred: + * 0b0000..No error + * 0b0001..PID encoding error + * 0b0010..PID unknown + * 0b0011..Packet unexpected + * 0b0100..Token CRC error + * 0b0101..Data CRC error + * 0b0110..Time out + * 0b0111..Babble + * 0b1000..Truncated EOP + * 0b1001..Sent/Received NAK + * 0b1010..Sent Stall + * 0b1011..Overrun + * 0b1100..Sent empty packet + * 0b1101..Bitstuff error + * 0b1110..Sync error + * 0b1111..Wrong data toggle + */ +#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) +#define USB_INFO_MINREV_MASK (0xFF0000U) +#define USB_INFO_MINREV_SHIFT (16U) +#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK) +#define USB_INFO_MAJREV_MASK (0xFF000000U) +#define USB_INFO_MAJREV_SHIFT (24U) +#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK) +/*! @} */ + +/*! @name EPLISTSTART - USB EP Command/Status List start address */ +/*! @{ */ +#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) +#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) +#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) +/*! @} */ + +/*! @name DATABUFSTART - USB Data buffer start address */ +/*! @{ */ +#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) +#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) +#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) +/*! @} */ + +/*! @name LPM - USB Link Power Management register */ +/*! @{ */ +#define USB_LPM_HIRD_HW_MASK (0xFU) +#define USB_LPM_HIRD_HW_SHIFT (0U) +#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) +#define USB_LPM_HIRD_SW_MASK (0xF0U) +#define USB_LPM_HIRD_SW_SHIFT (4U) +#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) +#define USB_LPM_DATA_PENDING_MASK (0x100U) +#define USB_LPM_DATA_PENDING_SHIFT (8U) +#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) +/*! @} */ + +/*! @name EPSKIP - USB Endpoint skip */ +/*! @{ */ +#define USB_EPSKIP_SKIP_MASK (0x3FFU) +#define USB_EPSKIP_SKIP_SHIFT (0U) +#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) +/*! @} */ + +/*! @name EPINUSE - USB Endpoint Buffer in use */ +/*! @{ */ +#define USB_EPINUSE_BUF_MASK (0x3FCU) +#define USB_EPINUSE_BUF_SHIFT (2U) +#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) +/*! @} */ + +/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ +/*! @{ */ +#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) +#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) +#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) +/*! @} */ + +/*! @name INTSTAT - USB interrupt status register */ +/*! @{ */ +#define USB_INTSTAT_EP0OUT_MASK (0x1U) +#define USB_INTSTAT_EP0OUT_SHIFT (0U) +#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) +#define USB_INTSTAT_EP0IN_MASK (0x2U) +#define USB_INTSTAT_EP0IN_SHIFT (1U) +#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) +#define USB_INTSTAT_EP1OUT_MASK (0x4U) +#define USB_INTSTAT_EP1OUT_SHIFT (2U) +#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) +#define USB_INTSTAT_EP1IN_MASK (0x8U) +#define USB_INTSTAT_EP1IN_SHIFT (3U) +#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) +#define USB_INTSTAT_EP2OUT_MASK (0x10U) +#define USB_INTSTAT_EP2OUT_SHIFT (4U) +#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) +#define USB_INTSTAT_EP2IN_MASK (0x20U) +#define USB_INTSTAT_EP2IN_SHIFT (5U) +#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) +#define USB_INTSTAT_EP3OUT_MASK (0x40U) +#define USB_INTSTAT_EP3OUT_SHIFT (6U) +#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) +#define USB_INTSTAT_EP3IN_MASK (0x80U) +#define USB_INTSTAT_EP3IN_SHIFT (7U) +#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) +#define USB_INTSTAT_EP4OUT_MASK (0x100U) +#define USB_INTSTAT_EP4OUT_SHIFT (8U) +#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) +#define USB_INTSTAT_EP4IN_MASK (0x200U) +#define USB_INTSTAT_EP4IN_SHIFT (9U) +#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) +#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) +#define USB_INTSTAT_FRAME_INT_SHIFT (30U) +#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) +#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) +#define USB_INTSTAT_DEV_INT_SHIFT (31U) +#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) +/*! @} */ + +/*! @name INTEN - USB interrupt enable register */ +/*! @{ */ +#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) +#define USB_INTEN_EP_INT_EN_SHIFT (0U) +#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) +#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) +#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) +#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) +#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) +#define USB_INTEN_DEV_INT_EN_SHIFT (31U) +#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) +/*! @} */ + +/*! @name INTSETSTAT - USB set interrupt status register */ +/*! @{ */ +#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) +#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) +#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) +#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) +#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) +#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) +#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) +/*! @} */ + +/*! @name EPTOGGLE - USB Endpoint toggle register */ +/*! @{ */ +#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) +#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) +#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral USB0 base address */ + #define USB0_BASE (0x50084000u) + /** Peripheral USB0 base address */ + #define USB0_BASE_NS (0x40084000u) + /** Peripheral USB0 base pointer */ + #define USB0 ((USB_Type *)USB0_BASE) + /** Peripheral USB0 base pointer */ + #define USB0_NS ((USB_Type *)USB0_BASE_NS) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USB0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USB0 } + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS_NS { USB0_BASE_NS } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS_NS { USB0_NS } +#else + /** Peripheral USB0 base address */ + #define USB0_BASE (0x40084000u) + /** Peripheral USB0 base pointer */ + #define USB0 ((USB_Type *)USB0_BASE) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USB0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USB0 } +#endif +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } +#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBFSH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer + * @{ + */ + +/** USBFSH - Register Layout Typedef */ +typedef struct { + __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */ + __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */ + __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */ + __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */ + __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */ + __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */ + __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */ + __I uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */ + __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */ + __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */ + __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */ + __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */ + __I uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */ + __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */ + __I uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */ + __I uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */ + __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */ + __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */ + __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */ + __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */ + __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */ + __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */ + uint8_t RESERVED_0[4]; + __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */ +} USBFSH_Type; + +/* ---------------------------------------------------------------------------- + -- USBFSH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBFSH_Register_Masks USBFSH Register Masks + * @{ + */ + +/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */ +/*! @{ */ +#define USBFSH_HCREVISION_REV_MASK (0xFFU) +#define USBFSH_HCREVISION_REV_SHIFT (0U) +#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK) +/*! @} */ + +/*! @name HCCONTROL - Defines the operating modes of the HC */ +/*! @{ */ +#define USBFSH_HCCONTROL_CBSR_MASK (0x3U) +#define USBFSH_HCCONTROL_CBSR_SHIFT (0U) +#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK) +#define USBFSH_HCCONTROL_PLE_MASK (0x4U) +#define USBFSH_HCCONTROL_PLE_SHIFT (2U) +#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK) +#define USBFSH_HCCONTROL_IE_MASK (0x8U) +#define USBFSH_HCCONTROL_IE_SHIFT (3U) +#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK) +#define USBFSH_HCCONTROL_CLE_MASK (0x10U) +#define USBFSH_HCCONTROL_CLE_SHIFT (4U) +#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK) +#define USBFSH_HCCONTROL_BLE_MASK (0x20U) +#define USBFSH_HCCONTROL_BLE_SHIFT (5U) +#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK) +#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U) +#define USBFSH_HCCONTROL_HCFS_SHIFT (6U) +#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK) +#define USBFSH_HCCONTROL_IR_MASK (0x100U) +#define USBFSH_HCCONTROL_IR_SHIFT (8U) +#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK) +#define USBFSH_HCCONTROL_RWC_MASK (0x200U) +#define USBFSH_HCCONTROL_RWC_SHIFT (9U) +#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK) +#define USBFSH_HCCONTROL_RWE_MASK (0x400U) +#define USBFSH_HCCONTROL_RWE_SHIFT (10U) +#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK) +/*! @} */ + +/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */ +/*! @{ */ +#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U) +#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U) +#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK) +#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U) +#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U) +#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK) +#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U) +#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U) +#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK) +#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U) +#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U) +#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK) +#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U) +#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U) +#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK) +/*! @} */ + +/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */ +/*! @{ */ +#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U) +#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK) +#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U) +#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK) +#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U) +#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK) +#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U) +#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK) +#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U) +#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK) +#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U) +#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK) +#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U) +#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK) +#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U) +#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U) +#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK) +/*! @} */ + +/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */ +/*! @{ */ +#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U) +#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK) +#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U) +#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK) +#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U) +#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK) +#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U) +#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK) +#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U) +#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK) +#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U) +#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK) +#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U) +#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK) +#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U) +#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U) +#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK) +#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U) +#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U) +#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK) +/*! @} */ + +/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */ +/*! @{ */ +#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U) +#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK) +#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U) +#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK) +#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U) +#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK) +#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U) +#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK) +#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U) +#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK) +#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U) +#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK) +#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U) +#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK) +#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U) +#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U) +#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK) +#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U) +#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U) +#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK) +/*! @} */ + +/*! @name HCHCCA - Contains the physical address of the host controller communication area */ +/*! @{ */ +#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U) +#define USBFSH_HCHCCA_HCCA_SHIFT (8U) +#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK) +/*! @} */ + +/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */ +/*! @{ */ +#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U) +#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK) +/*! @} */ + +/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */ +/*! @{ */ +#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U) +#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U) +#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK) +/*! @} */ + +/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */ +/*! @{ */ +#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U) +#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK) +/*! @} */ + +/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */ +/*! @{ */ +#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U) +#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U) +#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK) +/*! @} */ + +/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */ +/*! @{ */ +#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U) +#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK) +/*! @} */ + +/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */ +/*! @{ */ +#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U) +#define USBFSH_HCDONEHEAD_DH_SHIFT (4U) +#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK) +/*! @} */ + +/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */ +/*! @{ */ +#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU) +#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U) +#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK) +#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U) +#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U) +#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK) +#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U) +#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U) +#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK) +/*! @} */ + +/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */ +/*! @{ */ +#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU) +#define USBFSH_HCFMREMAINING_FR_SHIFT (0U) +#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK) +#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U) +#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U) +#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK) +/*! @} */ + +/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */ +/*! @{ */ +#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU) +#define USBFSH_HCFMNUMBER_FN_SHIFT (0U) +#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK) +/*! @} */ + +/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */ +/*! @{ */ +#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU) +#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U) +#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK) +/*! @} */ + +/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */ +/*! @{ */ +#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU) +#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U) +#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK) +/*! @} */ + +/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */ +/*! @{ */ +#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU) +#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U) +#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK) +#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U) +#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U) +#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK) +#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U) +#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U) +#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK) +#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U) +#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U) +#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK) +#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U) +#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U) +#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK) +#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U) +#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U) +#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK) +#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U) +#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U) +#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK) +/*! @} */ + +/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */ +/*! @{ */ +#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU) +#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U) +#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK) +#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U) +#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U) +#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK) +/*! @} */ + +/*! @name HCRHSTATUS - This register is divided into two parts */ +/*! @{ */ +#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U) +#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U) +#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK) +#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U) +#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U) +#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK) +#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U) +#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U) +#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK) +#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U) +#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U) +#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK) +#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U) +#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U) +#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK) +#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U) +#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U) +#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK) +/*! @} */ + +/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */ +/*! @{ */ +#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U) +#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U) +#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK) +#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U) +#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U) +#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK) +#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U) +#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U) +#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK) +#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U) +#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U) +#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK) +#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U) +#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U) +#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK) +#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U) +#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U) +#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK) +#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U) +#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U) +#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK) +#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U) +#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U) +#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK) +#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U) +#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U) +#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK) +#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U) +#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U) +#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK) +#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U) +#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U) +#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK) +#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U) +#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U) +#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK) +/*! @} */ + +/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ +/*! @{ */ +#define USBFSH_PORTMODE_ID_MASK (0x1U) +#define USBFSH_PORTMODE_ID_SHIFT (0U) +#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK) +#define USBFSH_PORTMODE_ID_EN_MASK (0x100U) +#define USBFSH_PORTMODE_ID_EN_SHIFT (8U) +#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK) +#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) +#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U) +#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBFSH_Register_Masks */ + + +/* USBFSH - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral USBFSH base address */ + #define USBFSH_BASE (0x500A2000u) + /** Peripheral USBFSH base address */ + #define USBFSH_BASE_NS (0x400A2000u) + /** Peripheral USBFSH base pointer */ + #define USBFSH ((USBFSH_Type *)USBFSH_BASE) + /** Peripheral USBFSH base pointer */ + #define USBFSH_NS ((USBFSH_Type *)USBFSH_BASE_NS) + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS { USBFSH_BASE } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS { USBFSH } + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS_NS { USBFSH_BASE_NS } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS_NS { USBFSH_NS } +#else + /** Peripheral USBFSH base address */ + #define USBFSH_BASE (0x400A2000u) + /** Peripheral USBFSH base pointer */ + #define USBFSH ((USBFSH_Type *)USBFSH_BASE) + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS { USBFSH_BASE } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS { USBFSH } +#endif +/** Interrupt vectors for the USBFSH peripheral type */ +#define USBFSH_IRQS { USB0_IRQn } +#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBFSH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBHSD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer + * @{ + */ + +/** USBHSD - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ + __I uint32_t INFO; /**< USB Info register, offset: 0x4 */ + __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ + __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ + __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ + __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ + __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ + __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ + __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ + __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ + __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ + uint8_t RESERVED_0[8]; + __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ +} USBHSD_Type; + +/* ---------------------------------------------------------------------------- + -- USBHSD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSD_Register_Masks USBHSD Register Masks + * @{ + */ + +/*! @name DEVCMDSTAT - USB Device Command/Status register */ +/*! @{ */ +#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) +#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK) +#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U) +#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U) +#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK) +#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U) +#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U) +#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK) +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK) +#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U) +#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK) +#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK) +#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK) +#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK) +#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK) +#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U) +#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U) +#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK) +#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U) +#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U) +#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK) +#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) +#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK) +#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) +#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK) +#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U) +#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U) +#define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK) +#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U) +#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U) +#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK) +#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) +#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U) +#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK) +#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U) +#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U) +#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK) +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U) +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U) +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK) +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U) +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U) +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK) +/*! @} */ + +/*! @name INFO - USB Info register */ +/*! @{ */ +#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU) +#define USBHSD_INFO_FRAME_NR_SHIFT (0U) +#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK) +#define USBHSD_INFO_ERR_CODE_MASK (0x7800U) +#define USBHSD_INFO_ERR_CODE_SHIFT (11U) +#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK) +#define USBHSD_INFO_MINREV_MASK (0xFF0000U) +#define USBHSD_INFO_MINREV_SHIFT (16U) +#define USBHSD_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MINREV_SHIFT)) & USBHSD_INFO_MINREV_MASK) +#define USBHSD_INFO_MAJREV_MASK (0xFF000000U) +#define USBHSD_INFO_MAJREV_SHIFT (24U) +#define USBHSD_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MAJREV_SHIFT)) & USBHSD_INFO_MAJREV_MASK) +/*! @} */ + +/*! @name EPLISTSTART - USB EP Command/Status List start address */ +/*! @{ */ +#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U) +#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U) +#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK) +#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U) +#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U) +#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK) +/*! @} */ + +/*! @name DATABUFSTART - USB Data buffer start address */ +/*! @{ */ +#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU) +#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U) +#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK) +/*! @} */ + +/*! @name LPM - USB Link Power Management register */ +/*! @{ */ +#define USBHSD_LPM_HIRD_HW_MASK (0xFU) +#define USBHSD_LPM_HIRD_HW_SHIFT (0U) +#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK) +#define USBHSD_LPM_HIRD_SW_MASK (0xF0U) +#define USBHSD_LPM_HIRD_SW_SHIFT (4U) +#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK) +#define USBHSD_LPM_DATA_PENDING_MASK (0x100U) +#define USBHSD_LPM_DATA_PENDING_SHIFT (8U) +#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK) +/*! @} */ + +/*! @name EPSKIP - USB Endpoint skip */ +/*! @{ */ +#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU) +#define USBHSD_EPSKIP_SKIP_SHIFT (0U) +#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK) +/*! @} */ + +/*! @name EPINUSE - USB Endpoint Buffer in use */ +/*! @{ */ +#define USBHSD_EPINUSE_BUF_MASK (0xFFCU) +#define USBHSD_EPINUSE_BUF_SHIFT (2U) +#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK) +/*! @} */ + +/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ +/*! @{ */ +#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU) +#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U) +#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK) +/*! @} */ + +/*! @name INTSTAT - USB interrupt status register */ +/*! @{ */ +#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U) +#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U) +#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK) +#define USBHSD_INTSTAT_EP0IN_MASK (0x2U) +#define USBHSD_INTSTAT_EP0IN_SHIFT (1U) +#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK) +#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U) +#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U) +#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK) +#define USBHSD_INTSTAT_EP1IN_MASK (0x8U) +#define USBHSD_INTSTAT_EP1IN_SHIFT (3U) +#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK) +#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U) +#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U) +#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK) +#define USBHSD_INTSTAT_EP2IN_MASK (0x20U) +#define USBHSD_INTSTAT_EP2IN_SHIFT (5U) +#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK) +#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U) +#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U) +#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK) +#define USBHSD_INTSTAT_EP3IN_MASK (0x80U) +#define USBHSD_INTSTAT_EP3IN_SHIFT (7U) +#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK) +#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U) +#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U) +#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK) +#define USBHSD_INTSTAT_EP4IN_MASK (0x200U) +#define USBHSD_INTSTAT_EP4IN_SHIFT (9U) +#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK) +#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U) +#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U) +#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK) +#define USBHSD_INTSTAT_EP5IN_MASK (0x800U) +#define USBHSD_INTSTAT_EP5IN_SHIFT (11U) +#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK) +#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U) +#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U) +#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK) +#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U) +#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U) +#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK) +/*! @} */ + +/*! @name INTEN - USB interrupt enable register */ +/*! @{ */ +#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU) +#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U) +#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK) +#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U) +#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U) +#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK) +#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U) +#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U) +#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK) +/*! @} */ + +/*! @name INTSETSTAT - USB set interrupt status register */ +/*! @{ */ +#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU) +#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U) +#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK) +#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) +#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK) +#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) +#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK) +/*! @} */ + +/*! @name EPTOGGLE - USB Endpoint toggle register */ +/*! @{ */ +#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU) +#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U) +#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBHSD_Register_Masks */ + + +/* USBHSD - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral USBHSD base address */ + #define USBHSD_BASE (0x50094000u) + /** Peripheral USBHSD base address */ + #define USBHSD_BASE_NS (0x40094000u) + /** Peripheral USBHSD base pointer */ + #define USBHSD ((USBHSD_Type *)USBHSD_BASE) + /** Peripheral USBHSD base pointer */ + #define USBHSD_NS ((USBHSD_Type *)USBHSD_BASE_NS) + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS { USBHSD_BASE } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS { USBHSD } + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS_NS { USBHSD_BASE_NS } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS_NS { USBHSD_NS } +#else + /** Peripheral USBHSD base address */ + #define USBHSD_BASE (0x40094000u) + /** Peripheral USBHSD base pointer */ + #define USBHSD ((USBHSD_Type *)USBHSD_BASE) + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS { USBHSD_BASE } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS { USBHSD } +#endif +/** Interrupt vectors for the USBHSD peripheral type */ +#define USBHSD_IRQS { USB1_IRQn } +#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBHSD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBHSH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer + * @{ + */ + +/** USBHSH - Register Layout Typedef */ +typedef struct { + __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */ + __IO uint32_t ATLPTD; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */ + __IO uint32_t ISOPTD; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */ + __IO uint32_t INTPTD; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */ + __IO uint32_t DATAPAYLOAD; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */ + __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */ + __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */ + __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */ + __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */ + __IO uint32_t ATLPTDD; /**< Done map for each ATL PTD, offset: 0x30 */ + __IO uint32_t ATLPTDS; /**< Skip map for each ATL PTD, offset: 0x34 */ + __IO uint32_t ISOPTDD; /**< Done map for each ISO PTD, offset: 0x38 */ + __IO uint32_t ISOPTDS; /**< Skip map for each ISO PTD, offset: 0x3C */ + __IO uint32_t INTPTDD; /**< Done map for each INT PTD, offset: 0x40 */ + __IO uint32_t INTPTDS; /**< Skip map for each INT PTD, offset: 0x44 */ + __IO uint32_t LASTPTD; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */ + uint8_t RESERVED_1[4]; + __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */ +} USBHSH_Type; + +/* ---------------------------------------------------------------------------- + -- USBHSH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSH_Register_Masks USBHSH Register Masks + * @{ + */ + +/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */ +/*! @{ */ +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU) +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U) +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK) +#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U) +#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U) +#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK) +/*! @} */ + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +/*! @{ */ +#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U) +#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK) +#define USBHSH_HCSPARAMS_PPC_MASK (0x10U) +#define USBHSH_HCSPARAMS_PPC_SHIFT (4U) +#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK) +#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U) +#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U) +#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK) +/*! @} */ + +/*! @name FLADJ_FRINDEX - Frame Length Adjustment */ +/*! @{ */ +#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU) +#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U) +#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK) +#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U) +#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U) +#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) +/*! @} */ + +/*! @name ATLPTD - Memory base address where ATL PTD0 is stored */ +/*! @{ */ +#define USBHSH_ATLPTD_ATL_CUR_MASK (0x1F0U) +#define USBHSH_ATLPTD_ATL_CUR_SHIFT (4U) +#define USBHSH_ATLPTD_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_CUR_SHIFT)) & USBHSH_ATLPTD_ATL_CUR_MASK) +#define USBHSH_ATLPTD_ATL_BASE_MASK (0xFFFFFE00U) +#define USBHSH_ATLPTD_ATL_BASE_SHIFT (9U) +#define USBHSH_ATLPTD_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_BASE_SHIFT)) & USBHSH_ATLPTD_ATL_BASE_MASK) +/*! @} */ + +/*! @name ISOPTD - Memory base address where ISO PTD0 is stored */ +/*! @{ */ +#define USBHSH_ISOPTD_ISO_FIRST_MASK (0x3E0U) +#define USBHSH_ISOPTD_ISO_FIRST_SHIFT (5U) +#define USBHSH_ISOPTD_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_FIRST_SHIFT)) & USBHSH_ISOPTD_ISO_FIRST_MASK) +#define USBHSH_ISOPTD_ISO_BASE_MASK (0xFFFFFC00U) +#define USBHSH_ISOPTD_ISO_BASE_SHIFT (10U) +#define USBHSH_ISOPTD_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_BASE_SHIFT)) & USBHSH_ISOPTD_ISO_BASE_MASK) +/*! @} */ + +/*! @name INTPTD - Memory base address where INT PTD0 is stored */ +/*! @{ */ +#define USBHSH_INTPTD_INT_FIRST_MASK (0x3E0U) +#define USBHSH_INTPTD_INT_FIRST_SHIFT (5U) +#define USBHSH_INTPTD_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_FIRST_SHIFT)) & USBHSH_INTPTD_INT_FIRST_MASK) +#define USBHSH_INTPTD_INT_BASE_MASK (0xFFFFFC00U) +#define USBHSH_INTPTD_INT_BASE_SHIFT (10U) +#define USBHSH_INTPTD_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_BASE_SHIFT)) & USBHSH_INTPTD_INT_BASE_MASK) +/*! @} */ + +/*! @name DATAPAYLOAD - Memory base address that indicates the start of the data payload buffers */ +/*! @{ */ +#define USBHSH_DATAPAYLOAD_DAT_BASE_MASK (0xFFFF0000U) +#define USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT (16U) +#define USBHSH_DATAPAYLOAD_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT)) & USBHSH_DATAPAYLOAD_DAT_BASE_MASK) +/*! @} */ + +/*! @name USBCMD - USB Command register */ +/*! @{ */ +#define USBHSH_USBCMD_RS_MASK (0x1U) +#define USBHSH_USBCMD_RS_SHIFT (0U) +#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK) +#define USBHSH_USBCMD_HCRESET_MASK (0x2U) +#define USBHSH_USBCMD_HCRESET_SHIFT (1U) +#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK) +#define USBHSH_USBCMD_FLS_MASK (0xCU) +#define USBHSH_USBCMD_FLS_SHIFT (2U) +#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK) +#define USBHSH_USBCMD_LHCR_MASK (0x80U) +#define USBHSH_USBCMD_LHCR_SHIFT (7U) +#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK) +#define USBHSH_USBCMD_ATL_EN_MASK (0x100U) +#define USBHSH_USBCMD_ATL_EN_SHIFT (8U) +#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK) +#define USBHSH_USBCMD_ISO_EN_MASK (0x200U) +#define USBHSH_USBCMD_ISO_EN_SHIFT (9U) +#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK) +#define USBHSH_USBCMD_INT_EN_MASK (0x400U) +#define USBHSH_USBCMD_INT_EN_SHIFT (10U) +#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK) +/*! @} */ + +/*! @name USBSTS - USB Interrupt Status register */ +/*! @{ */ +#define USBHSH_USBSTS_PCD_MASK (0x4U) +#define USBHSH_USBSTS_PCD_SHIFT (2U) +#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK) +#define USBHSH_USBSTS_FLR_MASK (0x8U) +#define USBHSH_USBSTS_FLR_SHIFT (3U) +#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK) +#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U) +#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U) +#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK) +#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U) +#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U) +#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK) +#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U) +#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U) +#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK) +#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U) +#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U) +#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK) +/*! @} */ + +/*! @name USBINTR - USB Interrupt Enable register */ +/*! @{ */ +#define USBHSH_USBINTR_PCDE_MASK (0x4U) +#define USBHSH_USBINTR_PCDE_SHIFT (2U) +#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK) +#define USBHSH_USBINTR_FLRE_MASK (0x8U) +#define USBHSH_USBINTR_FLRE_SHIFT (3U) +#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK) +#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U) +#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U) +#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK) +#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U) +#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U) +#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK) +#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U) +#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U) +#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK) +#define USBHSH_USBINTR_SOF_E_MASK (0x80000U) +#define USBHSH_USBINTR_SOF_E_SHIFT (19U) +#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK) +/*! @} */ + +/*! @name PORTSC1 - Port Status and Control register */ +/*! @{ */ +#define USBHSH_PORTSC1_CCS_MASK (0x1U) +#define USBHSH_PORTSC1_CCS_SHIFT (0U) +#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK) +#define USBHSH_PORTSC1_CSC_MASK (0x2U) +#define USBHSH_PORTSC1_CSC_SHIFT (1U) +#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK) +#define USBHSH_PORTSC1_PED_MASK (0x4U) +#define USBHSH_PORTSC1_PED_SHIFT (2U) +#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK) +#define USBHSH_PORTSC1_PEDC_MASK (0x8U) +#define USBHSH_PORTSC1_PEDC_SHIFT (3U) +#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK) +#define USBHSH_PORTSC1_OCA_MASK (0x10U) +#define USBHSH_PORTSC1_OCA_SHIFT (4U) +#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK) +#define USBHSH_PORTSC1_OCC_MASK (0x20U) +#define USBHSH_PORTSC1_OCC_SHIFT (5U) +#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK) +#define USBHSH_PORTSC1_FPR_MASK (0x40U) +#define USBHSH_PORTSC1_FPR_SHIFT (6U) +#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK) +#define USBHSH_PORTSC1_SUSP_MASK (0x80U) +#define USBHSH_PORTSC1_SUSP_SHIFT (7U) +#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK) +#define USBHSH_PORTSC1_PR_MASK (0x100U) +#define USBHSH_PORTSC1_PR_SHIFT (8U) +#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK) +#define USBHSH_PORTSC1_LS_MASK (0xC00U) +#define USBHSH_PORTSC1_LS_SHIFT (10U) +#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK) +#define USBHSH_PORTSC1_PP_MASK (0x1000U) +#define USBHSH_PORTSC1_PP_SHIFT (12U) +#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK) +#define USBHSH_PORTSC1_PIC_MASK (0xC000U) +#define USBHSH_PORTSC1_PIC_SHIFT (14U) +#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK) +#define USBHSH_PORTSC1_PTC_MASK (0xF0000U) +#define USBHSH_PORTSC1_PTC_SHIFT (16U) +#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK) +#define USBHSH_PORTSC1_PSPD_MASK (0x300000U) +#define USBHSH_PORTSC1_PSPD_SHIFT (20U) +#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK) +#define USBHSH_PORTSC1_WOO_MASK (0x400000U) +#define USBHSH_PORTSC1_WOO_SHIFT (22U) +#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK) +/*! @} */ + +/*! @name ATLPTDD - Done map for each ATL PTD */ +/*! @{ */ +#define USBHSH_ATLPTDD_ATL_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_ATLPTDD_ATL_DONE_SHIFT (0U) +#define USBHSH_ATLPTDD_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDD_ATL_DONE_SHIFT)) & USBHSH_ATLPTDD_ATL_DONE_MASK) +/*! @} */ + +/*! @name ATLPTDS - Skip map for each ATL PTD */ +/*! @{ */ +#define USBHSH_ATLPTDS_ATL_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_ATLPTDS_ATL_SKIP_SHIFT (0U) +#define USBHSH_ATLPTDS_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDS_ATL_SKIP_SHIFT)) & USBHSH_ATLPTDS_ATL_SKIP_MASK) +/*! @} */ + +/*! @name ISOPTDD - Done map for each ISO PTD */ +/*! @{ */ +#define USBHSH_ISOPTDD_ISO_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_ISOPTDD_ISO_DONE_SHIFT (0U) +#define USBHSH_ISOPTDD_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDD_ISO_DONE_SHIFT)) & USBHSH_ISOPTDD_ISO_DONE_MASK) +/*! @} */ + +/*! @name ISOPTDS - Skip map for each ISO PTD */ +/*! @{ */ +#define USBHSH_ISOPTDS_ISO_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_ISOPTDS_ISO_SKIP_SHIFT (0U) +#define USBHSH_ISOPTDS_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDS_ISO_SKIP_SHIFT)) & USBHSH_ISOPTDS_ISO_SKIP_MASK) +/*! @} */ + +/*! @name INTPTDD - Done map for each INT PTD */ +/*! @{ */ +#define USBHSH_INTPTDD_INT_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_INTPTDD_INT_DONE_SHIFT (0U) +#define USBHSH_INTPTDD_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDD_INT_DONE_SHIFT)) & USBHSH_INTPTDD_INT_DONE_MASK) +/*! @} */ + +/*! @name INTPTDS - Skip map for each INT PTD */ +/*! @{ */ +#define USBHSH_INTPTDS_INT_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_INTPTDS_INT_SKIP_SHIFT (0U) +#define USBHSH_INTPTDS_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDS_INT_SKIP_SHIFT)) & USBHSH_INTPTDS_INT_SKIP_MASK) +/*! @} */ + +/*! @name LASTPTD - Marks the last PTD in the list for ISO, INT and ATL */ +/*! @{ */ +#define USBHSH_LASTPTD_ATL_LAST_MASK (0x1FU) +#define USBHSH_LASTPTD_ATL_LAST_SHIFT (0U) +#define USBHSH_LASTPTD_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ATL_LAST_SHIFT)) & USBHSH_LASTPTD_ATL_LAST_MASK) +#define USBHSH_LASTPTD_ISO_LAST_MASK (0x1F00U) +#define USBHSH_LASTPTD_ISO_LAST_SHIFT (8U) +#define USBHSH_LASTPTD_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ISO_LAST_SHIFT)) & USBHSH_LASTPTD_ISO_LAST_MASK) +#define USBHSH_LASTPTD_INT_LAST_MASK (0x1F0000U) +#define USBHSH_LASTPTD_INT_LAST_SHIFT (16U) +#define USBHSH_LASTPTD_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_INT_LAST_SHIFT)) & USBHSH_LASTPTD_INT_LAST_MASK) +/*! @} */ + +/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ +/*! @{ */ +#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) +#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U) +#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK) +#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U) +#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U) +#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK) +#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U) +#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U) +#define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBHSH_Register_Masks */ + + +/* USBHSH - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral USBHSH base address */ + #define USBHSH_BASE (0x500A3000u) + /** Peripheral USBHSH base address */ + #define USBHSH_BASE_NS (0x400A3000u) + /** Peripheral USBHSH base pointer */ + #define USBHSH ((USBHSH_Type *)USBHSH_BASE) + /** Peripheral USBHSH base pointer */ + #define USBHSH_NS ((USBHSH_Type *)USBHSH_BASE_NS) + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS { USBHSH_BASE } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS { USBHSH } + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS_NS { USBHSH_BASE_NS } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS_NS { USBHSH_NS } +#else + /** Peripheral USBHSH base address */ + #define USBHSH_BASE (0x400A3000u) + /** Peripheral USBHSH base pointer */ + #define USBHSH ((USBHSH_Type *)USBHSH_BASE) + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS { USBHSH_BASE } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS { USBHSH } +#endif +/** Interrupt vectors for the USBHSH peripheral type */ +#define USBHSH_IRQS { USB1_IRQn } +#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBHSH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBPHY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer + * @{ + */ + +/** USBPHY - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ + __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ + __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ + __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ + __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ + __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ + __I uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ + uint8_t RESERVED_0[92]; + __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */ + __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */ + __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */ + __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */ + uint8_t RESERVED_1[16]; + __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */ + __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */ + __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */ + __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */ + uint8_t RESERVED_2[48]; + __IO uint32_t ANACTRLr; /**< USB PHY Analog Control Register, offset: 0x100 */ + __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */ + __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */ + __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */ +} USBPHY_Type; + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/*! @name PWD - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) +#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) +#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) +#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) +#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) +#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_SET - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) +#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) +#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) +#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) +#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) +#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) +#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_CLR - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) +#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) +#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) +#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) +#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) +#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) +#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_TOG - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) +#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) +#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) +#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) +#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) +#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) +/*! @} */ + +/*! @name TX - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_D_CAL_MASK (0xFU) +#define USBPHY_TX_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) +#define USBPHY_TX_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK) +#define USBPHY_TX_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DN_SHIFT)) & USBPHY_TX_TXENCAL45DN_MASK) +#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) +#define USBPHY_TX_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name TX_SET - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_SET_D_CAL_MASK (0xFU) +#define USBPHY_TX_SET_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) +#define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK) +#define USBPHY_TX_SET_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_SET_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_SET_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DN_SHIFT)) & USBPHY_TX_SET_TXENCAL45DN_MASK) +#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) +#define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_SET_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name TX_CLR - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) +#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) +#define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK) +#define USBPHY_TX_CLR_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_CLR_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_CLR_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DN_MASK) +#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) +#define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_CLR_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name TX_TOG - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) +#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) +#define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK) +#define USBPHY_TX_TOG_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_TOG_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_TOG_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DN_MASK) +#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) +#define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_TOG_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name RX - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_ENVADJ_MASK (0x7U) +#define USBPHY_RX_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) +#define USBPHY_RX_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) +#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) +/*! @} */ + +/*! @name RX_SET - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) +#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) +#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) +#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) +/*! @} */ + +/*! @name RX_CLR - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) +#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) +#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) +#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) +/*! @} */ + +/*! @name RX_TOG - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) +#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) +#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) +#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) +/*! @} */ + +/*! @name CTRL - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK) +#define USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) +#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK) +#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) +#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK) +#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK) +#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name STATUS - USB PHY Status Register */ +/*! @{ */ +#define USBPHY_STATUS_OK_STATUS_3V_MASK (0x1U) +#define USBPHY_STATUS_OK_STATUS_3V_SHIFT (0U) +#define USBPHY_STATUS_OK_STATUS_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OK_STATUS_3V_SHIFT)) & USBPHY_STATUS_OK_STATUS_3V_MASK) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) +/*! HOSTDISCONDETECT_STATUS + * 0b0..USB cable disconnect has not been detected at the local host + * 0b1..USB cable disconnect has been detected at the local host + */ +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) +/*! DEVPLUGIN_STATUS + * 0b0..No attachment to a USB host is detected + * 0b1..Cable attachment to a USB host is detected + */ +#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) +#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) +#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) +#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) +/*! @} */ + +/*! @name PLL_SIC - USB PHY PLL Control/Status Register */ +/*! @{ */ +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) +#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) +#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) +#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) +#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) +#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) +#define USBPHY_PLL_SIC_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_PREDIV_MASK) +#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */ +/*! @{ */ +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) +#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) +#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) +#define USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_SET_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK) +#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */ +/*! @{ */ +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) +#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) +#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_CLR_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK) +#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */ +/*! @{ */ +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) +#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) +#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_TOG_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK) +#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */ +/*! @{ */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK) +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK) +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */ +/*! @{ */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK) +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */ +/*! @{ */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK) +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */ +/*! @{ */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK) +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name ANACTRL - USB PHY Analog Control Register */ +/*! @{ */ +#define USBPHY_ANACTRL_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_LVI_EN_SHIFT)) & USBPHY_ANACTRL_LVI_EN_MASK) +#define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) +#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_SET - USB PHY Analog Control Register */ +/*! @{ */ +#define USBPHY_ANACTRL_SET_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_SET_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_SET_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_LVI_EN_SHIFT)) & USBPHY_ANACTRL_SET_LVI_EN_MASK) +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK) +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_CLR - USB PHY Analog Control Register */ +/*! @{ */ +#define USBPHY_ANACTRL_CLR_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_CLR_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_CLR_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_LVI_EN_SHIFT)) & USBPHY_ANACTRL_CLR_LVI_EN_MASK) +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK) +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_TOG - USB PHY Analog Control Register */ +/*! @{ */ +#define USBPHY_ANACTRL_TOG_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_TOG_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_TOG_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_LVI_EN_SHIFT)) & USBPHY_ANACTRL_TOG_LVI_EN_MASK) +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK) +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBPHY_Register_Masks */ + + +/* USBPHY - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x50038000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x40038000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x40038000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_PHY_IRQn } + +/*! + * @} + */ /* end of group USBPHY_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UTICK Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer + * @{ + */ + +/** UTICK - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ + __IO uint32_t STAT; /**< Status register., offset: 0x4 */ + __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ + __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ + __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ +} UTICK_Type; + +/* ---------------------------------------------------------------------------- + -- UTICK Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Register_Masks UTICK Register Masks + * @{ + */ + +/*! @name CTRL - Control register. */ +/*! @{ */ +#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) +#define UTICK_CTRL_DELAYVAL_SHIFT (0U) +#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) +#define UTICK_CTRL_REPEAT_MASK (0x80000000U) +#define UTICK_CTRL_REPEAT_SHIFT (31U) +#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) +/*! @} */ + +/*! @name STAT - Status register. */ +/*! @{ */ +#define UTICK_STAT_INTR_MASK (0x1U) +#define UTICK_STAT_INTR_SHIFT (0U) +#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) +#define UTICK_STAT_ACTIVE_MASK (0x2U) +#define UTICK_STAT_ACTIVE_SHIFT (1U) +#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) +/*! @} */ + +/*! @name CFG - Capture configuration register. */ +/*! @{ */ +#define UTICK_CFG_CAPEN0_MASK (0x1U) +#define UTICK_CFG_CAPEN0_SHIFT (0U) +#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) +#define UTICK_CFG_CAPEN1_MASK (0x2U) +#define UTICK_CFG_CAPEN1_SHIFT (1U) +#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) +#define UTICK_CFG_CAPEN2_MASK (0x4U) +#define UTICK_CFG_CAPEN2_SHIFT (2U) +#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) +#define UTICK_CFG_CAPEN3_MASK (0x8U) +#define UTICK_CFG_CAPEN3_SHIFT (3U) +#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) +#define UTICK_CFG_CAPPOL0_MASK (0x100U) +#define UTICK_CFG_CAPPOL0_SHIFT (8U) +#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) +#define UTICK_CFG_CAPPOL1_MASK (0x200U) +#define UTICK_CFG_CAPPOL1_SHIFT (9U) +#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) +#define UTICK_CFG_CAPPOL2_MASK (0x400U) +#define UTICK_CFG_CAPPOL2_SHIFT (10U) +#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) +#define UTICK_CFG_CAPPOL3_MASK (0x800U) +#define UTICK_CFG_CAPPOL3_SHIFT (11U) +#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) +/*! @} */ + +/*! @name CAPCLR - Capture clear register. */ +/*! @{ */ +#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) +#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) +#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) +#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) +#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) +#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) +#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) +#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) +#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) +#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) +#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) +#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) +/*! @} */ + +/*! @name CAP - Capture register . */ +/*! @{ */ +#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) +#define UTICK_CAP_CAP_VALUE_SHIFT (0U) +#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) +#define UTICK_CAP_VALID_MASK (0x80000000U) +#define UTICK_CAP_VALID_SHIFT (31U) +#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) +/*! @} */ + +/* The count of UTICK_CAP */ +#define UTICK_CAP_COUNT (4U) + + +/*! + * @} + */ /* end of group UTICK_Register_Masks */ + + +/* UTICK - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x5000E000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x4000E000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x4000E000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/*! + * @} + */ /* end of group UTICK_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WWDT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer + * @{ + */ + +/** WWDT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ + __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ + __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ + __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ + uint8_t RESERVED_0[4]; + __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ + __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ +} WWDT_Type; + +/* ---------------------------------------------------------------------------- + -- WWDT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Register_Masks WWDT Register Masks + * @{ + */ + +/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ +/*! @{ */ +#define WWDT_MOD_WDEN_MASK (0x1U) +#define WWDT_MOD_WDEN_SHIFT (0U) +/*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the + * watchdog timer will run permanently. + * 0b0..Stop. The watchdog timer is stopped. + * 0b1..Run. The watchdog timer is running. + */ +#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) +#define WWDT_MOD_WDRESET_MASK (0x2U) +#define WWDT_MOD_WDRESET_SHIFT (1U) +/*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. + * 0b0..Interrupt. A watchdog time-out will not cause a chip reset. + * 0b1..Reset. A watchdog time-out will cause a chip reset. + */ +#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) +#define WWDT_MOD_WDTOF_MASK (0x4U) +#define WWDT_MOD_WDTOF_SHIFT (2U) +#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) +#define WWDT_MOD_WDINT_MASK (0x8U) +#define WWDT_MOD_WDINT_SHIFT (3U) +#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) +#define WWDT_MOD_WDPROTECT_MASK (0x10U) +#define WWDT_MOD_WDPROTECT_SHIFT (4U) +/*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. + * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time. + * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. + */ +#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) +/*! @} */ + +/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ +/*! @{ */ +#define WWDT_TC_COUNT_MASK (0xFFFFFFU) +#define WWDT_TC_COUNT_SHIFT (0U) +#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) +/*! @} */ + +/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ +/*! @{ */ +#define WWDT_FEED_FEED_MASK (0xFFU) +#define WWDT_FEED_FEED_SHIFT (0U) +#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) +/*! @} */ + +/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ +/*! @{ */ +#define WWDT_TV_COUNT_MASK (0xFFFFFFU) +#define WWDT_TV_COUNT_SHIFT (0U) +#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) +/*! @} */ + +/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ +/*! @{ */ +#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) +#define WWDT_WARNINT_WARNINT_SHIFT (0U) +#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) +/*! @} */ + +/*! @name WINDOW - Watchdog Window compare value. */ +/*! @{ */ +#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) +#define WWDT_WINDOW_WINDOW_SHIFT (0U) +#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WWDT_Register_Masks */ + + +/* WWDT - Peripheral instance base addresses */ +#if (__ARM_FEATURE_CMSE & 0x2) + /** Peripheral WWDT base address */ + #define WWDT_BASE (0x5000C000u) + /** Peripheral WWDT base address */ + #define WWDT_BASE_NS (0x4000C000u) + /** Peripheral WWDT base pointer */ + #define WWDT ((WWDT_Type *)WWDT_BASE) + /** Peripheral WWDT base pointer */ + #define WWDT_NS ((WWDT_Type *)WWDT_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT_NS } +#else + /** Peripheral WWDT base address */ + #define WWDT_BASE (0x4000C000u) + /** Peripheral WWDT base pointer */ + #define WWDT ((WWDT_Type *)WWDT_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WDT_BOD_IRQn } + +/*! + * @} + */ /* end of group WWDT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/** High Speed SPI (Flexcomm 8) interrupt name */ +#define LSPI_HS_IRQn FLEXCOMM8_IRQn + +/*! + * @brief Get the chip value. + * + * @return chip version, 0x0: A0 version chip, 0x1: A1 version chip, 0xFF: invalid version. + */ +static inline uint32_t Chip_GetVersion() +{ + uint32_t deviceRevision; + + deviceRevision = SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK; + + if(0 == deviceRevision) /* A0 device revision is 0 */ + { + return 0x0; + } + else if(1 == deviceRevision) /* A1 device revision is 1 */ + { + return 0x1; + } + else + { + return 0xFF; + } +} + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _LPC55S69_CM33_CORE0_H_ */ + diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/LPC55S69_cm33_core0_features.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/LPC55S69_cm33_core0_features.h new file mode 100644 index 000000000..d170e2c98 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/LPC55S69_cm33_core0_features.h @@ -0,0 +1,388 @@ +/* +** ################################################################### +** Version: rev. 1.1, 2019-05-16 +** Build: b190719 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** +** ################################################################### +*/ + +#ifndef _LPC55S69_cm33_core0_FEATURES_H_ +#define _LPC55S69_cm33_core0_FEATURES_H_ + +/* SOC module features */ + +/* @brief CASPER availability on the SoC. */ +#define FSL_FEATURE_SOC_CASPER_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (2) +/* @brief FLASH availability on the SoC. */ +#define FSL_FEATURE_SOC_FLASH_COUNT (1) +/* @brief FLEXCOMM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) +/* @brief GINT availability on the SoC. */ +#define FSL_FEATURE_SOC_GINT_COUNT (2) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (1) +/* @brief SECGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_SECGPIO_COUNT (1) +/* @brief HASHCRYPT availability on the SoC. */ +#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (8) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (8) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief IOCON availability on the SoC. */ +#define FSL_FEATURE_SOC_IOCON_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (1) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief SECPINT availability on the SoC. */ +#define FSL_FEATURE_SOC_SECPINT_COUNT (1) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (1) +/* @brief POWERQUAD availability on the SoC. */ +#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (1) +/* @brief RNG1 availability on the SoC. */ +#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SDIF_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (9) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSCTL1 availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) +/* @brief USART availability on the SoC. */ +#define FSL_FEATURE_SOC_USART_COUNT (8) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBFSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBFSH_COUNT (1) +/* @brief USBHSD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSD_COUNT (1) +/* @brief USBHSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSH_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (744.6f) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (313.7f) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.5f) + +/* CASPER module features */ + +/* @brief Base address of the CASPER dedicated RAM */ +#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) +/* @brief Interleaving of the CASPER dedicated RAM */ +#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1) + +/* DMA module features */ + +/* @brief Number of channels */ +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23) +/* @brief Align size of DMA descriptor */ +#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) +/* @brief DMA head link descriptor table align size */ +#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) + +/* FLEXCOMM module features */ + +/* @brief FLEXCOMM0 USART INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) +/* @brief FLEXCOMM0 SPI INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) +/* @brief FLEXCOMM0 I2C INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) +/* @brief FLEXCOMM0 I2S INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) +/* @brief FLEXCOMM1 USART INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) +/* @brief FLEXCOMM1 SPI INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) +/* @brief FLEXCOMM1 I2C INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) +/* @brief FLEXCOMM1 I2S INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) +/* @brief FLEXCOMM2 USART INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) +/* @brief FLEXCOMM2 SPI INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) +/* @brief FLEXCOMM2 I2C INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) +/* @brief FLEXCOMM2 I2S INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) +/* @brief FLEXCOMM3 USART INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) +/* @brief FLEXCOMM3 SPI INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) +/* @brief FLEXCOMM3 I2C INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) +/* @brief FLEXCOMM3 I2S INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) +/* @brief FLEXCOMM4 USART INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) +/* @brief FLEXCOMM4 SPI INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) +/* @brief FLEXCOMM4 I2C INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) +/* @brief FLEXCOMM4 I2S INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) +/* @brief FLEXCOMM5 USART INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) +/* @brief FLEXCOMM5 SPI INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) +/* @brief FLEXCOMM5 I2C INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) +/* @brief FLEXCOMM5 I2S INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) +/* @brief FLEXCOMM6 USART INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) +/* @brief FLEXCOMM6 SPI INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) +/* @brief FLEXCOMM6 I2C INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) +/* @brief FLEXCOMM6 I2S INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) +/* @brief FLEXCOMM7 USART INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) +/* @brief FLEXCOMM7 SPI INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) +/* @brief FLEXCOMM7 I2C INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) +/* @brief FLEXCOMM7 I2S INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) +/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ +#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) + +/* HASHCRYPT module features */ + +/* @brief the address of alias offset */ +#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000) + +/* I2S module features */ + +/* @brief I2S support dual channel transfer. */ +#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0) +/* @brief I2S has DMIC interconnection. */ +#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) + +/* IOCON module features */ + +/* @brief Func bit field width */ +#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core */ +#define FSL_FEATURE_MAILBOX_SIDE_A (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) + +/* PLU module features */ + +/* @brief Has WAKEINT_CTRL register. */ +#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) + +/* POWERLIB module features */ + +/* @brief Powerlib API is different with other LPC series devices. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) + +/* POWERQUAD module features */ + +/* @brief Sine and Cossine fix errata */ +#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1) + +/* PUF module features */ + +/* @brief Number of PUF key slots available on device. */ +#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4) +/* @brief the shift status value */ +#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) + +/* SDIF module features */ + +/* @brief FIFO depth, every location is a WORD */ +#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) +/* @brief Max DMA buffer size */ +#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) +/* @brief Max source clock in HZ */ +#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) +/* @brief support 2 cards */ +#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1) + +/* SECPINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) + +/* SYSCON module features */ + +/* @brief Pointer to ROM IAP entry functions */ +#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205) +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592) +/* @brief Has Power Down mode */ +#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) +/* @brief CCM_ANALOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) + +/* USB module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USB version */ +#define FSL_FEATURE_USB_VERSION (200) +/* @brief Number of the endpoint in USB FS */ +#define FSL_FEATURE_USB_EP_NUM (5) + +/* USBFSH module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBFSH version */ +#define FSL_FEATURE_USBFSH_VERSION (200) + +/* USBHSD module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBHSD version */ +#define FSL_FEATURE_USBHSD_VERSION (300) +/* @brief Number of the endpoint in USB HS */ +#define FSL_FEATURE_USBHSD_EP_NUM (6) + +/* USBHSH module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBHSH version */ +#define FSL_FEATURE_USBHSH_VERSION (300) + +/* UTICK module features */ + +/* @brief UTICK does not support PD configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* WWDT module features */ + +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) +/* @brief WWDT does not support power down configure */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) + +#endif /* _LPC55S69_cm33_core0_FEATURES_H_ */ + diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_clock.c b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_clock.c new file mode 100644 index 000000000..63d8ceb55 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_clock.c @@ -0,0 +1,2031 @@ +/* + * Copyright 2017 - 2020 , NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_clock.h" +#include "fsl_power.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif +#define NVALMAX (0x100U) +#define PVALMAX (0x20U) +#define MVALMAX (0x10000U) + +#define PLL_MAX_N_DIV 0x100U + +/*-------------------------------------------------------------------------- +!!! If required these #defines can be moved to chip library file +----------------------------------------------------------------------------*/ + +#define PLL_SSCG1_MDEC_VAL_P (10U) /* MDEC is in bits 25 downto 10 */ +#define PLL_SSCG1_MDEC_VAL_M (0xFFFFULL << PLL_SSCG1_MDEC_VAL_P) +#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */ +#define PLL_NDEC_VAL_M (0xFFUL << PLL_NDEC_VAL_P) +#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */ +#define PLL_PDEC_VAL_M (0x1FUL << PLL_PDEC_VAL_P) + +#define PLL_MIN_CCO_FREQ_MHZ (275000000U) +#define PLL_MAX_CCO_FREQ_MHZ (550000000U) +#define PLL_LOWER_IN_LIMIT (2000U) /*!< Minimum PLL input rate */ +#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */ +#define PLL_MIN_IN_SSMODE (3000000U) +#define PLL_MAX_IN_SSMODE \ + (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */ + +/* PLL NDEC reg */ +#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) +/* PLL PDEC reg */ +#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M) +/* SSCG control1 */ +#define PLL_SSCG1_MDEC_VAL_SET(value) (((uint64_t)(value) << PLL_SSCG1_MDEC_VAL_P) & PLL_SSCG1_MDEC_VAL_M) + +/* PLL0 SSCG control1 */ +#define PLL0_SSCG_MD_FRACT_P 0U +#define PLL0_SSCG_MD_INT_P 25U +#define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) +#define PLL0_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL0_SSCG_MD_INT_P) + +#define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_FRACT_M) +#define PLL0_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_INT_P) & PLL0_SSCG_MD_INT_M) + +/* Saved value of PLL output rate, computed whenever needed to save run-time + computation on each call to retrive the PLL rate. */ +static uint32_t s_Pll0_Freq; +static uint32_t s_Pll1_Freq; + +/** External clock rate on the CLKIN pin in Hz. If not used, + set this to 0. Otherwise, set it to the exact rate in Hz this pin is + being driven at. */ +static uint32_t s_Ext_Clk_Freq = 16000000U; +static uint32_t s_I2S_Mclk_Freq = 0U; +static uint32_t s_PLU_ClkIn_Freq = 0U; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); +/* Get predivider (N) from PLL0 NDEC setting */ +static uint32_t findPll0PreDiv(void); +/* Get predivider (N) from PLL1 NDEC setting */ +static uint32_t findPll1PreDiv(void); +/* Get postdivider (P) from PLL0 PDEC setting */ +static uint32_t findPll0PostDiv(void); +/* Get multiplier (M) from PLL0 MDEC and SSCG settings */ +static float findPll0MMult(void); +/* Get the greatest common divisor */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); +/* Set PLL output based on desired output rate */ +static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS); +/* Update local PLL rate variable */ +static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup); + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Clock Selection for IP */ +/** + * brief Configure the clock selection muxes. + * param connection : Clock to be configured. + * return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection) +{ + uint8_t mux; + uint8_t sel; + uint16_t item; + uint32_t tmp32 = (uint32_t)connection; + uint32_t i; + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->SYSTICKCLKSELX[0]); + + if (kNONE_to_NONE != connection) + { + for (i = 0U; i < 2U; i++) + { + if (tmp32 == 0U) + { + break; + } + item = (uint16_t)GET_ID_ITEM(tmp32); + if (item != 0U) + { + mux = GET_ID_ITEM_MUX(item); + sel = GET_ID_ITEM_SEL(item); + if (mux == CM_RTCOSC32KCLKSEL) + { + PMC->RTCOSC32K |= sel; + } + else + { + pClkSel[mux] = sel; + } + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */ + } + } +} + +/* Return the actual clock attach id */ +/** + * brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * param attachId : Clock attach id to get. + * return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId) +{ + uint8_t mux; + uint8_t actualSel; + uint32_t tmp32 = (uint32_t)attachId; + uint32_t i; + uint32_t actualAttachId = 0U; + uint32_t selector = GET_ID_SELECTOR(tmp32); + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->SYSTICKCLKSELX[0]); + + if (kNONE_to_NONE == attachId) + { + return kNONE_to_NONE; + } + + for (i = 0U; i < 2U; i++) + { + mux = GET_ID_ITEM_MUX(tmp32); + if (tmp32 != 0UL) + { + if (mux == CM_RTCOSC32KCLKSEL) + { + actualSel = (uint8_t)(PMC->RTCOSC32K); + } + else + { + actualSel = (uint8_t)(pClkSel[mux]); + } + + /* Consider the combination of two registers */ + actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i); + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */ + } + + actualAttachId |= selector; + + return (clock_attach_id_t)actualAttachId; +} + +/* Set IP Clock Divider */ +/** + * brief Setup peripheral clock dividers. + * param div_name : Clock divider name + * param divided_by_value: Value to be divided + * param reset : Whether to reset the divider counter. + * return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) +{ + volatile uint32_t *pClkDiv; + + pClkDiv = &(SYSCON->SYSTICKCLKDIV0); + if (reset) + { + pClkDiv[(uint8_t)div_name] = 1UL << 29U; + } + if (divided_by_value == 0U) /*!< halt */ + { + pClkDiv[(uint8_t)div_name] = 1UL << 30U; + } + else + { + pClkDiv[(uint8_t)div_name] = (divided_by_value - 1U); + } +} + +/* Set RTC 1KHz Clock Divider */ +/** + * brief Setup rtc 1khz clock divider. + * param divided_by_value: Value to be divided + * return Nothing + */ +void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value) +{ + PMC->RTCOSC32K |= (((divided_by_value - 28U) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT) | PMC_RTCOSC32K_CLK1KHZDIV_MASK); +} + +/* Set RTC 1KHz Clock Divider */ +/** + * brief Setup rtc 1hz clock divider. + * param divided_by_value: Value to be divided + * return Nothing + */ +void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value) +{ + if (divided_by_value == 0U) /*!< halt */ + { + PMC->RTCOSC32K |= (1UL << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT); + } + else + { + PMC->RTCOSC32K |= + (((divided_by_value - 31744U) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT) | PMC_RTCOSC32K_CLK1HZDIV_MASK); + } +} + +/* Set FRO Clocking */ +/** + * brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). + * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is + * enabled. + * param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ) + * return returns success or fail status. + */ +status_t CLOCK_SetupFROClocking(uint32_t iFreq) +{ + if ((iFreq != 12000000U) && (iFreq != 48000000U) && (iFreq != 96000000U)) + { + return kStatus_Fail; + } + /* Enable Analog Control module */ + SYSCON->PRESETCTRLCLR[2] = (1UL << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT); + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK; + /* Power up the FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); + + if (iFreq == 96000000U) + { + ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(1); + } + /* always enable + else if (iFreq == 48000000U) + { + ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(1); + }*/ + else + { + ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(1); + } + return kStatus_Success; +} + +/* Set the FLASH wait states for the passed frequency */ +/** + * brief Set the flash wait states for the input freuqency. + * param iFreq: Input frequency + * return Nothing + */ +void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq) +{ + uint32_t num_wait_states; /* Flash Controller & FMC internal number of Wait States (minus 1) */ + + if (iFreq <= 11000000UL) + { + /* [0 - 11 MHz] */ + num_wait_states = 0UL; + } + else if (iFreq <= 22000000UL) + { + /* [11 MHz - 22 MHz] */ + num_wait_states = 1UL; + } + else if (iFreq <= 33000000UL) + { + /* [22 MHz - 33 MHz] */ + num_wait_states = 2UL; + } + else if (iFreq <= 44000000UL) + { + /* [33 MHz - 44 MHz] */ + num_wait_states = 3UL; + } + else if (iFreq <= 55000000UL) + { + /* [44 MHz - 55 MHz] */ + num_wait_states = 4UL; + } + else if (iFreq <= 66000000UL) + { + /* [55 MHz - 662 MHz] */ + num_wait_states = 5UL; + } + else if (iFreq <= 77000000UL) + { + /* [66 MHz - 77 MHz] */ + num_wait_states = 6UL; + } + else if (iFreq <= 88000000UL) + { + /* [77 MHz - 88 MHz] */ + num_wait_states = 7UL; + } + else if (iFreq <= 100000000UL) + { + /* [88 MHz - 100 MHz] */ + num_wait_states = 8UL; + } + else if (iFreq <= 115000000UL) + { + /* [100 MHz - 115 MHz] */ + num_wait_states = 9UL; + } + else if (iFreq <= 130000000UL) + { + /* [115 MHz - 130 MHz] */ + num_wait_states = 10UL; + } + else if (iFreq <= 150000000UL) + { + /* [130 MHz - 150 MHz] */ + num_wait_states = 11UL; + } + else + { + /* Above 150 MHz */ + num_wait_states = 12UL; + } + + FLASH->INT_CLR_STATUS = 0x1FUL; /* Clear all status flags */ + + FLASH->DATAW[0] = (FLASH->DATAW[0] & 0xFFFFFFF0UL) | + (num_wait_states & (SYSCON_FMCCR_FLASHTIM_MASK >> SYSCON_FMCCR_FLASHTIM_SHIFT)); + + FLASH->CMD = 0x2; /* CMD_SET_READ_MODE */ + + /* Wait until the cmd is completed (without error) */ + while (0UL == (FLASH->INT_STATUS & FLASH_INT_STATUS_DONE_MASK)) + { + ; + } + + /* Adjust FMC waiting time cycles (num_wait_states) */ + SYSCON->FMCCR = (SYSCON->FMCCR & ~SYSCON_FMCCR_FLASHTIM_MASK) | + ((num_wait_states << SYSCON_FMCCR_FLASHTIM_SHIFT) & SYSCON_FMCCR_FLASHTIM_MASK); +} + +/* Set EXT OSC Clk */ +/** + * brief Initialize the external osc clock to given frequency. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq) +{ + if (iFreq >= 32000000U) + { + return kStatus_Fail; + } + /* Turn on power for crystal 32 MHz */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); + /* Enable clock_in clock for clock module. */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; + + s_Ext_Clk_Freq = iFreq; + return kStatus_Success; +} + +/* Set I2S MCLK Clk */ +/** + * brief Initialize the I2S MCLK clock to given frequency. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq) +{ + s_I2S_Mclk_Freq = iFreq; + return kStatus_Success; +} + +/* Set PLU CLKIN Clk */ +/** + * brief Initialize the PLU CLKIN clock to given frequency. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq) +{ + s_PLU_ClkIn_Freq = iFreq; + return kStatus_Success; +} + +/* Get CLOCK OUT Clk */ +/*! brief Return Frequency of ClockOut + * return Frequency of ClockOut + */ +uint32_t CLOCK_GetClockOutClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->CLKOUTSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + + case 5U: + freq = CLOCK_GetPll1OutFreq(); + break; + + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U); +} + +/* Get ADC Clk */ +/*! brief Return Frequency of Adc Clock + * return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->ADCCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + + return freq / ((SYSCON->ADCCLKDIV & SYSCON_ADCCLKDIV_DIV_MASK) + 1U); +} + +/* Get USB0 Clk */ +/*! brief Return Frequency of Usb0 Clock + * return Frequency of Usb0 Clock. + */ +uint32_t CLOCK_GetUsb0ClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->USB0CLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + + return freq / ((SYSCON->USB0CLKDIV & 0xffU) + 1U); +} + +/* Get USB1 Clk */ +/*! brief Return Frequency of Usb1 Clock + * return Frequency of Usb1 Clock. + */ +uint32_t CLOCK_GetUsb1ClkFreq(void) +{ + return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; +} + +/* Get MCLK Clk */ +/*! brief Return Frequency of MClk Clock + * return Frequency of MClk Clock. + */ +uint32_t CLOCK_GetMclkClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->MCLKCLKSEL) + { + case 0U: + freq = CLOCK_GetFroHfFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + + return freq / ((SYSCON->MCLKDIV & 0xffU) + 1U); +} + +/* Get SCTIMER Clk */ +/*! brief Return Frequency of SCTimer Clock + * return Frequency of SCTimer Clock. + */ +uint32_t CLOCK_GetSctClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->SCTCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 5U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + + return freq / ((SYSCON->SCTCLKDIV & 0xffU) + 1U); +} + +/* Get SDIO Clk */ +/*! brief Return Frequency of SDIO Clock + * return Frequency of SDIO Clock. + */ +uint32_t CLOCK_GetSdioClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->SDIOCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq(); + break; + case 7U: + freq = 0U; + break; + default: + assert(false); + break; + } + + return freq / ((SYSCON->SDIOCLKDIV & 0xffU) + 1U); +} + +/* Get FRO 12M Clk */ +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ +uint32_t CLOCK_GetFro12MFreq(void) +{ + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; +} + +/* Get FRO 1M Clk */ +/*! brief Return Frequency of FRO 1MHz + * return Frequency of FRO 1MHz + */ +uint32_t CLOCK_GetFro1MFreq(void) +{ + return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; +} + +/* Get EXT OSC Clk */ +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ +uint32_t CLOCK_GetExtClkFreq(void) +{ + return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; +} + +/* Get WATCH DOG Clk */ +/*! brief Return Frequency of Watchdog + * return Frequency of Watchdog + */ +uint32_t CLOCK_GetWdtClkFreq(void) +{ + return CLOCK_GetFro1MFreq() / ((SYSCON->WDTCLKDIV & SYSCON_WDTCLKDIV_DIV_MASK) + 1U); +} + +/* Get HF FRO Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +uint32_t CLOCK_GetFroHfFreq(void) +{ + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; +} + +/* Get SYSTEM PLL Clk */ +/*! brief Return Frequency of PLL + * return Frequency of PLL + */ +uint32_t CLOCK_GetPll0OutFreq(void) +{ + return s_Pll0_Freq; +} + +/* Get USB PLL Clk */ +/*! brief Return Frequency of USB PLL + * return Frequency of PLL + */ +uint32_t CLOCK_GetPll1OutFreq(void) +{ + return s_Pll1_Freq; +} + +/* Get RTC OSC Clk */ +/*! brief Return Frequency of 32kHz osc + * return Frequency of 32kHz osc + */ +uint32_t CLOCK_GetOsc32KFreq(void) +{ + return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && + (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? + CLK_RTC_32K_CLK : + ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && + (0UL != (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? + CLK_RTC_32K_CLK : + 0U; +} + +/* Get MAIN Clk */ +/*! brief Return Frequency of Core System + * return Frequency of Core System + */ +uint32_t CLOCK_GetCoreSysClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->MAINCLKSELB) + { + case 0U: + if (SYSCON->MAINCLKSELA == 0U) + { + freq = CLOCK_GetFro12MFreq(); + } + else if (SYSCON->MAINCLKSELA == 1U) + { + freq = CLOCK_GetExtClkFreq(); + } + else if (SYSCON->MAINCLKSELA == 2U) + { + freq = CLOCK_GetFro1MFreq(); + } + else if (SYSCON->MAINCLKSELA == 3U) + { + freq = CLOCK_GetFroHfFreq(); + } + else + { + /* Add comments to prevent the case of MISRA C-2012 rule 15.7. */ + } + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetPll1OutFreq(); + break; + + case 3U: + freq = CLOCK_GetOsc32KFreq(); + break; + + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get I2S MCLK Clk */ +/*! brief Return Frequency of I2S MCLK Clock + * return Frequency of I2S MCLK Clock + */ +uint32_t CLOCK_GetI2SMClkFreq(void) +{ + return s_I2S_Mclk_Freq; +} + +/* Get PLU CLKIN Clk */ +/*! brief Return Frequency of PLU CLKIN Clock + * return Frequency of PLU CLKIN Clock + */ +uint32_t CLOCK_GetPLUClkInFreq(void) +{ + return s_PLU_ClkIn_Freq; +} + +/* Get FLEXCOMM input clock */ +/*! brief Return Frequency of flexcomm input clock + * param id : flexcomm instance id + * return Frequency value + */ +uint32_t CLOCK_GetFlexCommInputClock(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->FCCLKSELX[id]) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); + break; + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + case 5U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + + return freq; +} + +/* Get FLEXCOMM Clk */ +uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t temp; + + freq = CLOCK_GetFlexCommInputClock(id); + temp = SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_MULT_MASK; + return freq / (1U + (temp) / ((SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_DIV_MASK) + 1U)); +} + +/* Get HS_LPSI Clk */ +uint32_t CLOCK_GetHsLspiClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->HSLSPICLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); + break; + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + + return freq; +} + +/* Get CTimer Clk */ +/*! brief Return Frequency of CTimer functional Clock + * return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->CTIMERCLKSELX[id]) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + case 5U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + + return freq; +} + +/* Get Systick Clk */ +/*! brief Return Frequency of SystickClock + * return Frequency of Systick Clock + */ +uint32_t CLOCK_GetSystickClkFreq(uint32_t id) +{ + volatile uint32_t *pSystickClkDiv; + pSystickClkDiv = &(SYSCON->SYSTICKCLKDIV0); + uint32_t freq = 0U; + + switch (SYSCON->SYSTICKCLKSELX[id]) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq() / ((pSystickClkDiv[id] & 0xffU) + 1U); + break; + case 1U: + freq = CLOCK_GetFro1MFreq(); + break; + case 2U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + + return freq; +} + +/* Set FlexComm Clock */ +/** + * brief Set the flexcomm output frequency. + * param id : flexcomm instance id + * freq : output frequency + * return 0 : the frequency range is out of range. + * 1 : switch successfully. + */ +uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq) +{ + uint32_t input = CLOCK_GetFlexCommClkFreq(id); + uint32_t mul; + + if ((freq > 48000000UL) || (freq > input) || (input / freq >= 2UL)) + { + /* FRG output frequency should be less than equal to 48MHz */ + return 0UL; + } + else + { + mul = (uint32_t)((((uint64_t)input - freq) * 256ULL) / ((uint64_t)freq)); + SYSCON->FLEXFRGXCTRL[id] = (mul << 8U) | 0xFFU; + return 1UL; + } +} + +/* Get IP Clk */ +/*! brief Return Frequency of selected clock + * return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName) +{ + uint32_t freq; + switch (clockName) + { + case kCLOCK_CoreSysClk: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_BusClk: + freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); + break; + case kCLOCK_ClockOut: + freq = CLOCK_GetClockOutClkFreq(); + break; + case kCLOCK_Pll1Out: + freq = CLOCK_GetPll1OutFreq(); + break; + case kCLOCK_Mclk: + freq = CLOCK_GetMclkClkFreq(); + break; + case kCLOCK_FroHf: + freq = CLOCK_GetFroHfFreq(); + break; + case kCLOCK_Fro12M: + freq = CLOCK_GetFro12MFreq(); + break; + case kCLOCK_ExtClk: + freq = CLOCK_GetExtClkFreq(); + break; + case kCLOCK_Pll0Out: + freq = CLOCK_GetPll0OutFreq(); + break; + case kCLOCK_FlexI2S: + freq = CLOCK_GetI2SMClkFreq(); + break; + default: + freq = 0U; + break; + } + return freq; +} + +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) +{ + uint32_t seli, selp; + /* bandwidth: compute selP from Multiplier */ + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ + { + selp = (M >> 2U) + 1U; + if (selp >= 31U) + { + selp = 31U; + } + *pSelP = selp; + + if (M >= 8000UL) + { + seli = 1UL; + } + else if (M >= 122UL) + { + seli = (uint32_t)(8000UL / M); /*floor(8000/M) */ + } + else + { + seli = 2UL * ((uint32_t)(M / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ + } + + if (seli >= 63UL) + { + seli = 63UL; + } + *pSelI = seli; + + *pSelR = 0U; + } + else + { + /* Note: If the spread spectrum mode, choose N to ensure 3 MHz < Fin/N < 5 MHz */ + *pSelP = 3U; + *pSelI = 4U; + *pSelR = 4U; + } +} + +/* Get predivider (N) from PLL0 NDEC setting */ +static uint32_t findPll0PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get predivider (N) from PLL1 NDEC setting */ +static uint32_t findPll1PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL0 PDEC setting */ +static uint32_t findPll0PostDiv(void) +{ + uint32_t postDiv = 1UL; + + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; + } + else + { + postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + return postDiv; +} + +/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ +static float findPll0MMult(void) +{ + float mMult = 1.0F; + float mMult_fract; + uint32_t mMult_int; + + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) + { + mMult = + (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); + } + else + { + mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); + mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL0_SSCG_MD_INT_P); + mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL0_SSCG_MD_FRACT_M) / + (float)(uint32_t)(1UL << PLL0_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (mMult == 0.0F) + { + mMult = 1.0F; + } + return mMult; +} + +/* Find greatest common divisor between m and n */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) +{ + uint32_t tmp; + + while (n != 0U) + { + tmp = n; + n = m % n; + m = tmp; + } + + return m; +} + +/* + * Set PLL0 output based on desired output rate. + * In this function, the it calculates the PLL0 setting for output frequency from input clock + * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. + * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. + */ +static pll_error_t CLOCK_GetPll0ConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) +{ + uint32_t nDivOutHz, fccoHz; + uint32_t pllPreDivider, pllMultiplier, pllPostDivider; + uint32_t pllDirectInput, pllDirectOutput; + uint32_t pllSelP, pllSelI, pllSelR, uplimoff; + + /* Baseline parameters (no input or output dividers) */ + pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ + pllPostDivider = 1U; /* 1 implies post-divider will be disabled */ + pllDirectOutput = 1U; + + /* Verify output rate parameter */ + if (foutHz > PLL_MAX_CCO_FREQ_MHZ) + { + /* Maximum PLL output with post divider=1 cannot go above this frequency */ + return kStatus_PLL_OutputTooHigh; + } + if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) + { + /* Minmum PLL output with maximum post divider cannot go below this frequency */ + return kStatus_PLL_OutputTooLow; + } + + /* If using SS mode, input clock needs to be between 3MHz and 20MHz */ + if (useSS) + { + /* Verify input rate parameter */ + if (finHz < PLL_MIN_IN_SSMODE) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + /* PLL input in SS mode must be under 20MHz */ + if (finHz > (PLL_MAX_IN_SSMODE * NVALMAX)) + { + return kStatus_PLL_InputTooHigh; + } + } + else + { + /* Verify input rate parameter */ + if (finHz < PLL_LOWER_IN_LIMIT) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + if (finHz > PLL_HIGHER_IN_LIMIT) + { + /* Input clock into the PLL cannot be higher than this */ + return kStatus_PLL_InputTooHigh; + } + } + + /* Find the optimal CCO frequency for the output and input that + will keep it inside the PLL CCO range. This may require + tweaking the post-divider for the PLL. */ + fccoHz = foutHz; + while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) + { + /* CCO output is less than minimum CCO range, so the CCO output + needs to be bumped up and the post-divider is used to bring + the PLL output back down. */ + pllPostDivider++; + if (pllPostDivider > PVALMAX) + { + return kStatus_PLL_OutsideIntLimit; + } + + /* Target CCO goes up, PLL output goes down */ + /* divide-by-2 divider in the post-divider is always work*/ + fccoHz = foutHz * (pllPostDivider * 2U); + pllDirectOutput = 0U; + } + + /* Determine if a pre-divider is needed to get the best frequency */ + if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) + { + uint32_t a = FindGreatestCommonDivisor(fccoHz, finHz); + + if (a > PLL_LOWER_IN_LIMIT) + { + a = finHz / a; + if ((a != 0U) && (a < PLL_MAX_N_DIV)) + { + pllPreDivider = a; + } + } + } + + /* Bypass pre-divider hardware if pre-divider is 1 */ + if (pllPreDivider > 1U) + { + pllDirectInput = 0U; + } + else + { + pllDirectInput = 1U; + } + + /* Determine PLL multipler */ + nDivOutHz = (finHz / pllPreDivider); + pllMultiplier = (fccoHz / nDivOutHz); + + /* Find optimal values for filter */ + if (useSS == false) + { + /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ + if ((nDivOutHz * ((pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) + { + pllMultiplier++; + } + + /* Setup filtering */ + pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR); + uplimoff = 0U; + + /* Get encoded value for M (mult) and use manual filter, disable SS mode */ + pSetup->pllsscg[1] = + (uint32_t)((PLL_SSCG1_MDEC_VAL_SET(pllMultiplier)) | (1UL << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)); + } + else + { + uint64_t fc; + + /* Filtering will be handled by SSC */ + pllSelR = 0U; + pllSelI = 0U; + pllSelP = 0U; + uplimoff = 1U; + + /* The PLL multiplier will get very close and slightly under the + desired target frequency. A small fractional component can be + added to fine tune the frequency upwards to the target. */ + fc = (((uint64_t)fccoHz % (uint64_t)nDivOutHz) << 25U) / nDivOutHz; + + /* Set multiplier */ + pSetup->pllsscg[0] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) | PLL0_SSCG_MD_FRACT_SET((uint32_t)fc)); + pSetup->pllsscg[1] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) >> 32U); + } + + /* Get encoded values for N (prediv) and P (postdiv) */ + pSetup->pllndec = PLL_NDEC_VAL_SET(pllPreDivider); + pSetup->pllpdec = PLL_PDEC_VAL_SET(pllPostDivider); + + /* PLL control */ + pSetup->pllctrl = (pllSelR << SYSCON_PLL0CTRL_SELR_SHIFT) | /* Filter coefficient */ + (pllSelI << SYSCON_PLL0CTRL_SELI_SHIFT) | /* Filter coefficient */ + (pllSelP << SYSCON_PLL0CTRL_SELP_SHIFT) | /* Filter coefficient */ + (0UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT) | /* PLL bypass mode disabled */ + (uplimoff << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */ + (pllDirectInput << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */ + (pllDirectOutput << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT) | /* Bypass post-divider? */ + (1UL << SYSCON_PLL0CTRL_CLKEN_SHIFT); /* Ensure the PLL clock output */ + + return kStatus_PLL_Success; +} + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) +/* Alloct the static buffer for cache. */ +static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; +static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; +static uint32_t s_PllSetupCacheIdx = 0U; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + +/* + * Calculate the PLL setting values from input clock freq to output freq. + */ +static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) +{ + pll_error_t retErr; +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + uint32_t i; + + for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) + { + if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && (useSS == s_UseSSCache[i])) + { + /* Hit the target in cache buffer. */ + pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl; + pSetup->pllndec = s_PllSetupCacheStruct[i].pllndec; + pSetup->pllpdec = s_PllSetupCacheStruct[i].pllpdec; + pSetup->pllsscg[0] = s_PllSetupCacheStruct[i].pllsscg[0]; + pSetup->pllsscg[1] = s_PllSetupCacheStruct[i].pllsscg[1]; + retErr = kStatus_PLL_Success; + break; + } + } + + if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + { + return retErr; + } +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + retErr = CLOCK_GetPll0ConfigInternal(finHz, foutHz, pSetup, useSS); + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + /* Cache the most recent calulation result into buffer. */ + s_FinHzCache[s_PllSetupCacheIdx] = finHz; + s_FoutHzCache[s_PllSetupCacheIdx] = foutHz; + s_UseSSCache[s_PllSetupCacheIdx] = useSS; + + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndec = pSetup->pllndec; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdec = pSetup->pllpdec; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[0] = pSetup->pllsscg[0]; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[1] = pSetup->pllsscg[1]; + /* Update the index for next available buffer. */ + s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + return retErr; +} + +/* Update local PLL rate variable */ +static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup) +{ + s_Pll0_Freq = CLOCK_GetPLL0OutFromSetup(pSetup); +} + +/* Return System PLL input clock rate */ +/*! brief Return PLL0 input clock rate + * return PLL0 input clock rate + */ +uint32_t CLOCK_GetPLL0InClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK)) + { + case 0x00U: + clkRate = CLK_FRO_12MHZ; + break; + + case 0x01U: + clkRate = CLOCK_GetExtClkFreq(); + break; + + case 0x02U: + clkRate = CLOCK_GetFro1MFreq(); + break; + + case 0x03U: + clkRate = CLOCK_GetOsc32KFreq(); + break; + + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return PLL1 input clock rate */ +uint32_t CLOCK_GetPLL1InClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK)) + { + case 0x00U: + clkRate = CLK_FRO_12MHZ; + break; + + case 0x01U: + clkRate = CLOCK_GetExtClkFreq(); + break; + + case 0x02U: + clkRate = CLOCK_GetFro1MFreq(); + break; + + case 0x03U: + clkRate = CLOCK_GetOsc32KFreq(); + break; + + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return PLL0 output clock rate from setup structure */ +/*! brief Return PLL0 output clock rate from setup structure + * param pSetup : Pointer to a PLL setup structure + * return PLL0 output clock rate the setup structure will generate + */ +uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup) +{ + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + float workRate = 0.0F; + + /* Get the input clock frequency of PLL. */ + clkRate = CLOCK_GetPLL0InClockRate(); + + if (((pSetup->pllctrl & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && + ((pSetup->pllctrl & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && + ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && + ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) + { + prediv = findPll0PreDiv(); + postdiv = findPll0PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (float)clkRate * (float)findPll0MMult(); + workRate /= (float)postdiv; + } + + return (uint32_t)workRate; +} + +/* Set the current PLL0 Rate */ +/*! brief Store the current PLL rate + * param rate: Current rate of the PLL + * return Nothing + **/ +void CLOCK_SetStoredPLL0ClockRate(uint32_t rate) +{ + s_Pll0_Freq = rate; +} + +/* Return PLL0 output clock rate */ +/*! brief Return PLL0 output clock rate + * param recompute : Forces a PLL rate recomputation if true + * return PLL0 output clock rate + * note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetPLL0OutClockRate(bool recompute) +{ + pll_setup_t Setup; + uint32_t rate; + + if ((recompute) || (s_Pll0_Freq == 0U)) + { + Setup.pllctrl = SYSCON->PLL0CTRL; + Setup.pllndec = SYSCON->PLL0NDEC; + Setup.pllpdec = SYSCON->PLL0PDEC; + Setup.pllsscg[0] = SYSCON->PLL0SSCG0; + Setup.pllsscg[1] = SYSCON->PLL0SSCG1; + + CLOCK_GetPLL0OutFromSetupUpdate(&Setup); + } + + rate = s_Pll0_Freq; + + return rate; +} + +/* Set PLL0 output based on the passed PLL setup data */ +/*! brief Set PLL output based on the passed PLL setup data + * param pControl : Pointer to populated PLL control structure to generate setup with + * param pSetup : Pointer to PLL setup structure to be filled + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ +pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup) +{ + uint32_t inRate; + bool useSS = ((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0U); + + pll_error_t pllError; + + /* Determine input rate for the PLL */ + if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U) + { + inRate = pControl->inputRate; + } + else + { + inRate = CLOCK_GetPLL0InClockRate(); + } + + /* PLL flag options */ + pllError = CLOCK_GetPll0Config(inRate, pControl->desiredRate, pSetup, useSS); + if ((useSS) && (pllError == kStatus_PLL_Success)) + { + /* If using SS mode, then some tweaks are made to the generated setup */ + pSetup->pllsscg[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc; + if (pControl->mfDither) + { + pSetup->pllsscg[1] |= (1UL << SYSCON_PLL0SSCG1_DITHER_SHIFT); + } + } + + return pllError; +} + +/* Set PLL0 output from PLL setup structure */ +/*! brief Set PLL output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * param flagcfg : Flag configuration for PLL config structure + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg) +{ + uint32_t inRate, clkRate, prediv; + + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_PLL0); + POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); + + pSetup->flags = flagcfg; + + /* Write PLL setup data */ + SYSCON->PLL0CTRL = pSetup->pllctrl; + SYSCON->PLL0NDEC = pSetup->pllndec; + SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ + SYSCON->PLL0PDEC = pSetup->pllpdec; + SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ + SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; + SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; + SYSCON->PLL0SSCG1 = + pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT); /* latch */ + + POWER_DisablePD(kPDRUNCFG_PD_PLL0); + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ + { + inRate = CLOCK_GetPLL0InClockRate(); + prediv = findPll0PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ + if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) + { + while (CLOCK_IsPLL0Locked() == false) + { + } + } + else + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval + to insure the PLL will be stable */ + } + } + else /* spread spectrum mode */ + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to + insure the PLL will be stable */ + } + } + + /* Update current programmed PLL rate var */ + CLOCK_GetPLL0OutFromSetupUpdate(pSetup); + + /* System voltage adjustment, occurs prior to setting main system clock */ + if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U) + { + POWER_SetVoltageForFreq(s_Pll0_Freq); + } + + return kStatus_PLL_Success; +} + +/* Setup PLL Frequency from pre-calculated value */ +/** + * brief Set PLL0 output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup) +{ + uint32_t inRate, clkRate, prediv; + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_PLL0); + POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); + + /* Write PLL setup data */ + SYSCON->PLL0CTRL = pSetup->pllctrl; + SYSCON->PLL0NDEC = pSetup->pllndec; + SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ + SYSCON->PLL0PDEC = pSetup->pllpdec; + SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ + SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; + SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; + SYSCON->PLL0SSCG1 = + pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* latch */ + + POWER_DisablePD(kPDRUNCFG_PD_PLL0); + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ + { + inRate = CLOCK_GetPLL0InClockRate(); + prediv = findPll0PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ + if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) + { + while (CLOCK_IsPLL0Locked() == false) + { + } + } + else + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval + to insure the PLL will be stable */ + } + } + else /* spread spectrum mode */ + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to + insure the PLL will be stable */ + } + } + + /* Update current programmed PLL rate var */ + s_Pll0_Freq = pSetup->pllRate; + + return kStatus_PLL_Success; +} + +/* Setup PLL1 Frequency from pre-calculated value */ +/** + * brief Set PLL1 output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup) +{ + uint32_t inRate, clkRate, prediv; + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_PLL1); + + /* Write PLL setup data */ + SYSCON->PLL1CTRL = pSetup->pllctrl; + SYSCON->PLL1NDEC = pSetup->pllndec; + SYSCON->PLL1NDEC = pSetup->pllndec | (1UL << SYSCON_PLL1NDEC_NREQ_SHIFT); /* latch */ + SYSCON->PLL1PDEC = pSetup->pllpdec; + SYSCON->PLL1PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL1PDEC_PREQ_SHIFT); /* latch */ + SYSCON->PLL1MDEC = pSetup->pllmdec; + SYSCON->PLL1MDEC = pSetup->pllmdec | (1UL << SYSCON_PLL1MDEC_MREQ_SHIFT); /* latch */ + + POWER_DisablePD(kPDRUNCFG_PD_PLL1); + + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + inRate = CLOCK_GetPLL1InClockRate(); + prediv = findPll1PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ + if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) + { + while (CLOCK_IsPLL1Locked() == false) + { + } + } + else + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to + insure the PLL will be stable */ + } + } + + /* Update current programmed PLL rate var */ + s_Pll0_Freq = pSetup->pllRate; + + return kStatus_PLL_Success; +} + +/* Set PLL0 clock based on the input frequency and multiplier */ +/*! brief Set PLL0 output based on the multiplier and input frequency + * param multiply_by : multiplier + * param input_freq : Clock input frequency of the PLL + * return Nothing + * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this + * function does not disable or enable PLL power, wait for PLL lock, + * or adjust system voltages. These must be done in the application. + * The function will not alter any source clocks (ie, main systen clock) + * that may use the PLL, so these should be setup prior to and after + * exiting the function. + */ +void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq) +{ + uint32_t cco_freq = input_freq * multiply_by; + uint32_t pdec = 1U; + uint32_t selr; + uint32_t seli; + uint32_t selp; + uint32_t mdec, ndec; + + while (cco_freq < 275000000U) + { + multiply_by <<= 1U; /* double value in each iteration */ + pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */ + cco_freq = input_freq * multiply_by; + } + + selr = 0U; + + if (multiply_by >= 8000UL) + { + seli = 1UL; + } + else if (multiply_by >= 122UL) + { + seli = (uint32_t)(8000UL / multiply_by); /*floor(8000/M) */ + } + else + { + seli = 2UL * ((uint32_t)(multiply_by / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ + } + + if (seli >= 63U) + { + seli = 63U; + } + + { + selp = 31U; + } + + if (pdec > 1U) + { + pdec = pdec / 2U; /* Account for minus 1 encoding */ + /* Translate P value */ + } + + mdec = (uint32_t)PLL_SSCG1_MDEC_VAL_SET(multiply_by); + ndec = 0x1U; /* pre divide by 1 (hardcoded) */ + + SYSCON->PLL0CTRL = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_BYPASSPOSTDIV(0) | + SYSCON_PLL0CTRL_BYPASSPOSTDIV2(0) | (selr << SYSCON_PLL0CTRL_SELR_SHIFT) | + (seli << SYSCON_PLL0CTRL_SELI_SHIFT) | (selp << SYSCON_PLL0CTRL_SELP_SHIFT); + SYSCON->PLL0PDEC = pdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* set Pdec value and assert preq */ + SYSCON->PLL0NDEC = ndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* set Pdec value and assert preq */ + SYSCON->PLL0SSCG1 = + mdec | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* select non sscg MDEC value, assert mreq and select mdec value */ +} + +/* Enable USB DEVICE FULL SPEED clock */ +/*! brief Enable USB Device FS clock. + * param src : clock source + * param freq: clock frequency + * Enable USB Device Full Speed clock. + */ +bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq) +{ + bool ret = true; + + CLOCK_DisableClock(kCLOCK_Usbd0); + + if (kCLOCK_UsbfsSrcFro == src) + { + switch (freq) + { + case 96000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ + break; + + default: + ret = false; + break; + } + /* Turn ON FRO HF */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); + /* Enable FRO 96MHz output */ + ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; + /* Select FRO 96 or 48 MHz */ + CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); + } + else + { + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + /*!< Set up PLL1 */ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U), + .pllndec = SYSCON_PLL1NDEC_NDIV(1U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(5U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(30U), + .pllRate = 48000000U, + .flags = PLL_SETUPFLAG_WAITLOCK}; + (void)CLOCK_SetPLL1Freq(&pll1Setup); + + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); + CLOCK_AttachClk(kPLL1_to_USB0_CLK); + SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + CLOCK_EnableClock(kCLOCK_Usbd0); + CLOCK_EnableClock(kCLOCK_UsbRam1); + + return ret; +} + +/* Enable USB HOST FULL SPEED clock */ +/*! brief Enable USB HOST FS clock. + * param src : clock source + * param freq: clock frequency + * Enable USB HOST Full Speed clock. + */ +bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq) +{ + bool ret = true; + + CLOCK_DisableClock(kCLOCK_Usbhmr0); + CLOCK_DisableClock(kCLOCK_Usbhsl0); + + if (kCLOCK_UsbfsSrcFro == src) + { + switch (freq) + { + case 96000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ + break; + + default: + ret = false; + break; + } + /* Turn ON FRO HF */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); + /* Enable FRO 96MHz output */ + ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; + /* Select FRO 96 MHz */ + CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); + } + else + { + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + /*!< Set up PLL1 */ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U), + .pllndec = SYSCON_PLL1NDEC_NDIV(1U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(5U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(30U), + .pllRate = 48000000U, + .flags = PLL_SETUPFLAG_WAITLOCK}; + (void)CLOCK_SetPLL1Freq(&pll1Setup); + + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); + CLOCK_AttachClk(kPLL1_to_USB0_CLK); + SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + CLOCK_EnableClock(kCLOCK_Usbhmr0); + CLOCK_EnableClock(kCLOCK_Usbhsl0); + CLOCK_EnableClock(kCLOCK_UsbRam1); + + return ret; +} + +/* Enable USB PHY clock */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + volatile uint32_t i; + + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); + POWER_DisablePD(kPDRUNCFG_PD_FRO32K); /*!< Ensure FRO32k is on */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32K); /*!< Ensure xtal32k is on */ + POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /*!< Ensure xtal32k is on */ + POWER_DisablePD(kPDRUNCFG_PD_LDOUSBHS); /*!< Ensure xtal32k is on */ + + /* wait to make sure PHY power is fully up */ + i = 100000U; + while ((i--) != 0U) + { + __ASM("nop"); + } + + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL(1); + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_PHY(1); + + USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; + USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | USBPHY_PLL_SIC_PLL_DIV_SEL(0x06); + USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK; + USBPHY->PLL_SIC_CLR = (1UL << 16U); // Reserved. User must set this bit to 0x0 + USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_POWER_MASK; + USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK; + + USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; + USBPHY->PWD_SET = 0x0; + + return true; +} + +/* Enable USB DEVICE HIGH SPEED clock */ +bool CLOCK_EnableUsbhs0DeviceClock(clock_usbhs_src_t src, uint32_t freq) +{ + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1); + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_DEV(1); + + /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1); + return true; +} + +/* Enable USB HOST HIGH SPEED clock */ +bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq) +{ + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1); + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_HOST(1); + + /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1); + + return true; +} diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_clock.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_clock.h new file mode 100644 index 000000000..b03ce4621 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_clock.h @@ -0,0 +1,1240 @@ +/* + * Copyright 2017 - 2020, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.3.2. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 2)) +/*@}*/ + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could control the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 +#endif + +/*! + * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. + * + * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function + * would cache the recent calulation and accelerate the execution to get the + * right settings. + */ +#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT +#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U +#endif + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (150000000UL) +#endif + +/*! @brief Clock ip name array for ROM. */ +#define ROM_CLOCKS \ + { \ + kCLOCK_Rom \ + } +/*! @brief Clock ip name array for SRAM. */ +#define SRAM_CLOCKS \ + { \ + kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3, kCLOCK_Sram4 \ + } +/*! @brief Clock ip name array for FLASH. */ +#define FLASH_CLOCKS \ + { \ + kCLOCK_Flash \ + } +/*! @brief Clock ip name array for FMC. */ +#define FMC_CLOCKS \ + { \ + kCLOCK_Fmc \ + } +/*! @brief Clock ip name array for INPUTMUX. */ +#define INPUTMUX_CLOCKS \ + { \ + kCLOCK_InputMux0 \ + } +/*! @brief Clock ip name array for IOCON. */ +#define IOCON_CLOCKS \ + { \ + kCLOCK_Iocon \ + } +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3 \ + } +/*! @brief Clock ip name array for PINT. */ +#define PINT_CLOCKS \ + { \ + kCLOCK_Pint \ + } +/*! @brief Clock ip name array for GINT. */ +#define GINT_CLOCKS \ + { \ + kCLOCK_Gint, kCLOCK_Gint \ + } +/*! @brief Clock ip name array for DMA. */ +#define DMA_CLOCKS \ + { \ + kCLOCK_Dma0, kCLOCK_Dma1 \ + } +/*! @brief Clock ip name array for CRC. */ +#define CRC_CLOCKS \ + { \ + kCLOCK_Crc \ + } +/*! @brief Clock ip name array for WWDT. */ +#define WWDT_CLOCKS \ + { \ + kCLOCK_Wwdt \ + } +/*! @brief Clock ip name array for RTC. */ +#define RTC_CLOCKS \ + { \ + kCLOCK_Rtc \ + } +/*! @brief Clock ip name array for Mailbox. */ +#define MAILBOX_CLOCKS \ + { \ + kCLOCK_Mailbox \ + } +/*! @brief Clock ip name array for LPADC. */ +#define LPADC_CLOCKS \ + { \ + kCLOCK_Adc0 \ + } +/*! @brief Clock ip name array for MRT. */ +#define MRT_CLOCKS \ + { \ + kCLOCK_Mrt \ + } +/*! @brief Clock ip name array for OSTIMER. */ +#define OSTIMER_CLOCKS \ + { \ + kCLOCK_OsTimer0 \ + } +/*! @brief Clock ip name array for SCT0. */ +#define SCT_CLOCKS \ + { \ + kCLOCK_Sct0 \ + } +/*! @brief Clock ip name array for UTICK. */ +#define UTICK_CLOCKS \ + { \ + kCLOCK_Utick0 \ + } +/*! @brief Clock ip name array for FLEXCOMM. */ +#define FLEXCOMM_CLOCKS \ + { \ + kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \ + kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi \ + } +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \ + kCLOCK_MinUart6, kCLOCK_MinUart7 \ + } + +/*! @brief Clock ip name array for BI2C. */ +#define BI2C_CLOCKS \ + { \ + kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \ + } +/*! @brief Clock ip name array for LSPI. */ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \ + } +/*! @brief Clock ip name array for FLEXI2S. */ +#define FLEXI2S_CLOCKS \ + { \ + kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \ + kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \ + } +/*! @brief Clock ip name array for CTIMER. */ +#define CTIMER_CLOCKS \ + { \ + kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ + } +/*! @brief Clock ip name array for COMP */ +#define COMP_CLOCKS \ + { \ + kCLOCK_Comp \ + } +/*! @brief Clock ip name array for SDIO. */ +#define SDIO_CLOCKS \ + { \ + kCLOCK_Sdio \ + } +/*! @brief Clock ip name array for USB1CLK. */ +#define USB1CLK_CLOCKS \ + { \ + kCLOCK_Usb1Clk \ + } +/*! @brief Clock ip name array for FREQME. */ +#define FREQME_CLOCKS \ + { \ + kCLOCK_Freqme \ + } +/*! @brief Clock ip name array for USBRAM. */ +#define USBRAM_CLOCKS \ + { \ + kCLOCK_UsbRam1 \ + } +/*! @brief Clock ip name array for RNG. */ +#define RNG_CLOCKS \ + { \ + kCLOCK_Rng \ + } +/*! @brief Clock ip name array for USBHMR0. */ +#define USBHMR0_CLOCKS \ + { \ + kCLOCK_Usbhmr0 \ + } +/*! @brief Clock ip name array for USBHSL0. */ +#define USBHSL0_CLOCKS \ + { \ + kCLOCK_Usbhsl0 \ + } +/*! @brief Clock ip name array for HashCrypt. */ +#define HASHCRYPT_CLOCKS \ + { \ + kCLOCK_HashCrypt \ + } +/*! @brief Clock ip name array for PowerQuad. */ +#define POWERQUAD_CLOCKS \ + { \ + kCLOCK_PowerQuad \ + } +/*! @brief Clock ip name array for PLULUT. */ +#define PLULUT_CLOCKS \ + { \ + kCLOCK_PluLut \ + } +/*! @brief Clock ip name array for PUF. */ +#define PUF_CLOCKS \ + { \ + kCLOCK_Puf \ + } +/*! @brief Clock ip name array for CASPER. */ +#define CASPER_CLOCKS \ + { \ + kCLOCK_Casper \ + } +/*! @brief Clock ip name array for ANALOGCTRL. */ +#define ANALOGCTRL_CLOCKS \ + { \ + kCLOCK_AnalogCtrl \ + } +/*! @brief Clock ip name array for HS_LSPI. */ +#define HS_LSPI_CLOCKS \ + { \ + kCLOCK_Hs_Lspi \ + } +/*! @brief Clock ip name array for GPIO_SEC. */ +#define GPIO_SEC_CLOCKS \ + { \ + kCLOCK_Gpio_Sec \ + } +/*! @brief Clock ip name array for GPIO_SEC_INT. */ +#define GPIO_SEC_INT_CLOCKS \ + { \ + kCLOCK_Gpio_Sec_Int \ + } +/*! @brief Clock ip name array for USBD. */ +#define USBD_CLOCKS \ + { \ + kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \ + } +/*! @brief Clock ip name array for USBH. */ +#define USBH_CLOCKS \ + { \ + kCLOCK_Usbh1 \ + } +#define PLU_CLOCKS \ + { \ + kCLOCK_PluLut \ + } +#define SYSCTL_CLOCKS \ + { \ + kCLOCK_Sysctl \ + } +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +/*------------------------------------------------------------------------------ + clock_ip_name_t definition: +------------------------------------------------------------------------------*/ + +#define CLK_GATE_REG_OFFSET_SHIFT 8U +#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U +#define CLK_GATE_BIT_SHIFT_SHIFT 0U +#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU + +#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ + ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ + (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) + +#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) +#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) + +#define AHB_CLK_CTRL0 0 +#define AHB_CLK_CTRL1 1 +#define AHB_CLK_CTRL2 2 + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = 0U, + kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), + kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), + kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), + kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), + kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), + kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), + kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), + kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), + kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), + kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), + kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), + kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), + kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), + kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), + kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), + kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), + kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), + kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), + kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), + kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), + kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), + kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), + kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), + kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), + kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), + kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), + kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), + kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), + kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), + kCLOCK_Pvt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28), + kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30), + kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), + kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), + kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), + kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3), + kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), + kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), + kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), + kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), + kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), + kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), + kCLOCK_InputMux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), + kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), + kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), + kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), + kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), + kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19), + kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), + kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), + kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), + kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), + kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), + kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27), + kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28), + kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), + kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30) +} clock_ip_name_t; + +/*! @brief Peripherals clock source definition. */ +#define BUS_CLK kCLOCK_BusClk + +#define I2C0_CLK_SRC BUS_CLK + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ + kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ + kCLOCK_ClockOut, /*!< CLOCKOUT */ + kCLOCK_FroHf, /*!< FRO48/96 */ + kCLOCK_Pll1Out, /*!< PLL1 Output */ + kCLOCK_Mclk, /*!< MCLK */ + kCLOCK_Fro12M, /*!< FRO12M */ + kCLOCK_ExtClk, /*!< External Clock */ + kCLOCK_Pll0Out, /*!< PLL0 Output */ + kCLOCK_FlexI2S, /*!< FlexI2S clock */ + +} clock_name_t; + +/*! @brief Clock Mux Switches + * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable + * starting from LSB upwards + * + * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* + * + */ + +#define CLK_ATTACH_ID(mux, sel, pos) \ + ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((uint32_t)(pos)*12U)) +#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U) +#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U)) + +#define GET_ID_ITEM(connection) ((connection)&0xFFFU) +#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U) +#define GET_ID_ITEM_MUX(connection) (((uint8_t)connection) & 0xFFU) +#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF00U) >> 8U) - 1U)) +#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) + +#define CM_SYSTICKCLKSEL0 0U +#define CM_SYSTICKCLKSEL1 1U +#define CM_TRACECLKSEL 2U +#define CM_CTIMERCLKSEL0 3U +#define CM_CTIMERCLKSEL1 4U +#define CM_CTIMERCLKSEL2 5U +#define CM_CTIMERCLKSEL3 6U +#define CM_CTIMERCLKSEL4 7U +#define CM_MAINCLKSELA 8U +#define CM_MAINCLKSELB 9U +#define CM_CLKOUTCLKSEL 10U +#define CM_PLL0CLKSEL 12U +#define CM_PLL1CLKSEL 13U +#define CM_ADCASYNCCLKSEL 17U +#define CM_USB0CLKSEL 18U +#define CM_FXCOMCLKSEL0 20U +#define CM_FXCOMCLKSEL1 21U +#define CM_FXCOMCLKSEL2 22U +#define CM_FXCOMCLKSEL3 23U +#define CM_FXCOMCLKSEL4 24U +#define CM_FXCOMCLKSEL5 25U +#define CM_FXCOMCLKSEL6 26U +#define CM_FXCOMCLKSEL7 27U +#define CM_HSLSPICLKSEL 28U +#define CM_MCLKCLKSEL 32U +#define CM_SCTCLKSEL 36U +#define CM_SDIOCLKSEL 38U + +#define CM_RTCOSC32KCLKSEL 63U + +typedef enum _clock_attach_id +{ + + kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), + kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), + kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), + kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), + kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0), + kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), + kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), + + kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), + kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), + kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), + kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), + kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), + kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), + kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), + kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), + + kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0), + kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1), + kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2), + kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3), + kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7), + + kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), + kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), + kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), + kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), + + kMAIN_CLK_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0), + kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1), + kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3), + kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5), + kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7), + + kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), + kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), + kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), + kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), + kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), + kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5), + kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6), + kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), + + kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), + kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), + kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), + kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), + kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), + kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5), + kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6), + kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), + + kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), + kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), + kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), + kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), + kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), + kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5), + kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6), + kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), + + kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), + kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), + kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), + kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), + kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), + kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5), + kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6), + kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), + + kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), + kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), + kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), + kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), + kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), + kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5), + kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6), + kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), + + kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), + kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), + kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), + kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), + kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), + kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5), + kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6), + kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), + + kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), + kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), + kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), + kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), + kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), + kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5), + kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6), + kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), + + kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), + kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), + kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), + kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), + kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), + kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5), + kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6), + kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), + + kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0), + kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1), + kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2), + kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3), + kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4), + kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6), + kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7), + + kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), + kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), + kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), + + kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), + kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), + kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), + kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), + kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5), + kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), + + kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0), + kPLL0_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1), + kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3), + kPLL1_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 5), + kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7), + + kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0), + kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1), + + kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), + kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), + kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), + kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), + + kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), + kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), + kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), + kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), + + kSYSTICK_DIV1_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 0), + kFRO1M_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 1), + kOSC32K_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 2), + kNONE_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 7), + + kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0), + kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1), + kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2), + kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3), + kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7), + + kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), + kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), + kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), + kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), + kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), + kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), + kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7), + + kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), + kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), + kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), + kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), + kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), + kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), + kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7), + + kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), + kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), + kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), + kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), + kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), + kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), + kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7), + + kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), + kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), + kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), + kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), + kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), + kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), + kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7), + + kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), + kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), + kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), + kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), + kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), + kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), + kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7), + kNONE_to_NONE = (int)0x80000000U, +} clock_attach_id_t; + +/* Clock dividers */ +typedef enum _clock_div_name +{ + kCLOCK_DivSystickClk0 = 0, + kCLOCK_DivSystickClk1 = 1, + kCLOCK_DivArmTrClkDiv = 2, + kCLOCK_DivFlexFrg0 = 8, + kCLOCK_DivFlexFrg1 = 9, + kCLOCK_DivFlexFrg2 = 10, + kCLOCK_DivFlexFrg3 = 11, + kCLOCK_DivFlexFrg4 = 12, + kCLOCK_DivFlexFrg5 = 13, + kCLOCK_DivFlexFrg6 = 14, + kCLOCK_DivFlexFrg7 = 15, + kCLOCK_DivAhbClk = 32, + kCLOCK_DivClkOut = 33, + kCLOCK_DivFrohfClk = 34, + kCLOCK_DivWdtClk = 35, + kCLOCK_DivAdcAsyncClk = 37, + kCLOCK_DivUsb0Clk = 38, + kCLOCK_DivMClk = 43, + kCLOCK_DivSctClk = 45, + kCLOCK_DivSdioClk = 47, + kCLOCK_DivPll0Clk = 49 +} clock_div_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Enable the clock for specific IP. + * @param clk : Clock to be enabled. + * @return Nothing + */ +static inline void CLOCK_EnableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); +} +/** + * @brief Disable the clock for specific IP. + * @param clk : Clock to be Disabled. + * @return Nothing + */ +static inline void CLOCK_DisableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); +} +/** + * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). + * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is + * enabled. + * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ) + * @return returns success or fail status. + */ +status_t CLOCK_SetupFROClocking(uint32_t iFreq); +/** + * @brief Set the flash wait states for the input freuqency. + * @param iFreq : Input frequency + * @return Nothing + */ +void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq); +/** + * @brief Initialize the external osc clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq); +/** + * @brief Initialize the I2S MCLK clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq); +/** + * @brief Initialize the PLU CLKIN clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq); +/** + * @brief Configure the clock selection muxes. + * @param connection : Clock to be configured. + * @return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection); +/** + * @brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * @param attachId : Clock attach id to get. + * @return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId); +/** + * @brief Setup peripheral clock dividers. + * @param div_name : Clock divider name + * @param divided_by_value: Value to be divided + * @param reset : Whether to reset the divider counter. + * @return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset); +/** + * @brief Setup rtc 1khz clock divider. + * @param divided_by_value: Value to be divided + * @return Nothing + */ +void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value); +/** + * @brief Setup rtc 1hz clock divider. + * @param divided_by_value: Value to be divided + * @return Nothing + */ +void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value); + +/** + * @brief Set the flexcomm output frequency. + * @param id : flexcomm instance id + * @param freq : output frequency + * @return 0 : the frequency range is out of range. + * 1 : switch successfully. + */ +uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq); + +/*! @brief Return Frequency of flexcomm input clock + * @param id : flexcomm instance id + * @return Frequency value + */ +uint32_t CLOCK_GetFlexCommInputClock(uint32_t id); + +/*! @brief Return Frequency of selected clock + * @return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); +/*! @brief Return Frequency of FRO 12MHz + * @return Frequency of FRO 12MHz + */ +uint32_t CLOCK_GetFro12MFreq(void); +/*! @brief Return Frequency of FRO 1MHz + * @return Frequency of FRO 1MHz + */ +uint32_t CLOCK_GetFro1MFreq(void); +/*! @brief Return Frequency of ClockOut + * @return Frequency of ClockOut + */ +uint32_t CLOCK_GetClockOutClkFreq(void); +/*! @brief Return Frequency of Adc Clock + * @return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(void); +/*! @brief Return Frequency of Usb0 Clock + * @return Frequency of Usb0 Clock. + */ +uint32_t CLOCK_GetUsb0ClkFreq(void); +/*! @brief Return Frequency of Usb1 Clock + * @return Frequency of Usb1 Clock. + */ +uint32_t CLOCK_GetUsb1ClkFreq(void); +/*! @brief Return Frequency of MClk Clock + * @return Frequency of MClk Clock. + */ +uint32_t CLOCK_GetMclkClkFreq(void); +/*! @brief Return Frequency of SCTimer Clock + * @return Frequency of SCTimer Clock. + */ +uint32_t CLOCK_GetSctClkFreq(void); +/*! @brief Return Frequency of SDIO Clock + * @return Frequency of SDIO Clock. + */ +uint32_t CLOCK_GetSdioClkFreq(void); +/*! @brief Return Frequency of External Clock + * @return Frequency of External Clock. If no external clock is used returns 0. + */ +uint32_t CLOCK_GetExtClkFreq(void); +/*! @brief Return Frequency of Watchdog + * @return Frequency of Watchdog + */ +uint32_t CLOCK_GetWdtClkFreq(void); +/*! @brief Return Frequency of High-Freq output of FRO + * @return Frequency of High-Freq output of FRO + */ +uint32_t CLOCK_GetFroHfFreq(void); +/*! @brief Return Frequency of PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetPll0OutFreq(void); +/*! @brief Return Frequency of USB PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetPll1OutFreq(void); +/*! @brief Return Frequency of 32kHz osc + * @return Frequency of 32kHz osc + */ +uint32_t CLOCK_GetOsc32KFreq(void); +/*! @brief Return Frequency of Core System + * @return Frequency of Core System + */ +uint32_t CLOCK_GetCoreSysClkFreq(void); +/*! @brief Return Frequency of I2S MCLK Clock + * @return Frequency of I2S MCLK Clock + */ +uint32_t CLOCK_GetI2SMClkFreq(void); +/*! @brief Return Frequency of PLU CLKIN Clock + * @return Frequency of PLU CLKIN Clock + */ +uint32_t CLOCK_GetPLUClkInFreq(void); +/*! @brief Return Frequency of FlexComm Clock + * @return Frequency of FlexComm Clock + */ +uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id); +/*! @brief Return Frequency of High speed SPI Clock + * @return Frequency of High speed SPI Clock + */ +uint32_t CLOCK_GetHsLspiClkFreq(void); +/*! @brief Return Frequency of CTimer functional Clock + * @return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id); +/*! @brief Return Frequency of SystickClock + * @return Frequency of Systick Clock + */ +uint32_t CLOCK_GetSystickClkFreq(uint32_t id); + +/*! @brief Return PLL0 input clock rate + * @return PLL0 input clock rate + */ +uint32_t CLOCK_GetPLL0InClockRate(void); + +/*! @brief Return PLL1 input clock rate + * @return PLL1 input clock rate + */ +uint32_t CLOCK_GetPLL1InClockRate(void); + +/*! @brief Return PLL0 output clock rate + * @param recompute : Forces a PLL rate recomputation if true + * @return PLL0 output clock rate + * @note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetPLL0OutClockRate(bool recompute); + +/*! @brief Enables and disables PLL0 bypass mode + * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass + * @return PLL0 output clock rate + */ +__STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass) +{ + if (bypass) + { + SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); + } + else + { + SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); + } +} + +/*! @brief Enables and disables PLL1 bypass mode + * @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass + * @return PLL1 output clock rate + */ +__STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass) +{ + if (bypass) + { + SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); + } + else + { + SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); + } +} + +/*! @brief Check if PLL is locked or not + * @return true if the PLL is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsPLL0Locked(void) +{ + return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0UL); +} + +/*! @brief Check if PLL1 is locked or not + * @return true if the PLL1 is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsPLL1Locked(void) +{ + return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0UL); +} + +/*! @brief Store the current PLL0 rate + * @param rate: Current rate of the PLL0 + * @return Nothing + **/ +void CLOCK_SetStoredPLL0ClockRate(uint32_t rate); + +/*! @brief PLL configuration structure flags for 'flags' field + * These flags control how the PLL configuration function sets up the PLL setup structure.
+ * + * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the + * configuration structure must be assigned with the expected PLL frequency. If the + * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration + * function and the driver will determine the PLL rate from the currently selected + * PLL source. This flag might be used to configure the PLL input clock more accurately + * when using the WDT oscillator or a more dyanmic CLKIN source.
+ * + * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the + * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider + * are not used.
+ */ +#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */ +#define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U) +/*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */ + +/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency + * See (MF) field in the PLL0SSCG1 register in the UM. + */ +typedef enum _ss_progmodfm +{ + kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */ + kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */ + kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */ + kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */ + kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */ + kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */ + kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */ + kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */ +} ss_progmodfm_t; + +/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth + * See (MR) field in the PLL0SSCG1 register in the UM. + */ +typedef enum _ss_progmoddp +{ + kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */ + kSS_MR_K1 = (1 << 23), /*!< k = 1 */ + kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */ + kSS_MR_K2 = (3 << 23), /*!< k = 2 */ + kSS_MR_K3 = (4 << 23), /*!< k = 3 */ + kSS_MR_K4 = (5 << 23), /*!< k = 4 */ + kSS_MR_K6 = (6 << 23), /*!< k = 6 */ + kSS_MR_K8 = (7 << 23) /*!< k = 8 */ +} ss_progmoddp_t; + +/*! @brief PLL Spread Spectrum (SS) Modulation waveform control + * See (MC) field in the PLL0SSCG1 register in the UM.
+ * Compensation for low pass filtering of the PLL to get a triangular + * modulation at the output of the PLL, giving a flat frequency spectrum. + */ +typedef enum _ss_modwvctrl +{ + kSS_MC_NOC = (0 << 26), /*!< no compensation */ + kSS_MC_RECC = (2 << 26), /*!< recommended setting */ + kSS_MC_MAXC = (3 << 26), /*!< max. compensation */ +} ss_modwvctrl_t; + +/*! @brief PLL configuration structure + * + * This structure can be used to configure the settings for a PLL + * setup structure. Fill in the desired configuration for the PLL + * and call the PLL setup function to fill in a PLL setup structure. + */ +typedef struct _pll_config +{ + uint32_t desiredRate; /*!< Desired PLL rate in Hz */ + uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */ + uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ + ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_modwvctrl_t + ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ + bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + +} pll_config_t; + +/*! @brief PLL setup structure flags for 'flags' field + * These flags control how the PLL setup function sets up the PLL + */ +#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */ +#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ +#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */ +#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */ + +/*! @brief PLL0 setup structure + * This structure can be used to pre-build a PLL setup configuration + * at run-time and quickly set the PLL to the configuration. It can be + * populated with the PLL setup function. If powering up or waiting + * for PLL lock, the PLL input clock source should be configured prior + * to PLL setup. + */ +typedef struct _pll_setup +{ + uint32_t pllctrl; /*!< PLL control register PLL0CTRL */ + uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */ + uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */ + uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */ + uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/ + uint32_t pllRate; /*!< Acutal PLL rate */ + uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ +} pll_setup_t; + +/*! @brief PLL status definitions + */ +typedef enum _pll_error +{ + kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ + kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ + kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ + kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ + kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ + kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */ + kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */ + kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */ +} pll_error_t; + +/*! @brief USB FS clock source definition. */ +typedef enum _clock_usbfs_src +{ + kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 MHz. */ + kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, /*!< Use PLL0 output. */ + kCLOCK_UsbfsSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */ + kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, /*!< Use PLL1 clock. */ + + kCLOCK_UsbfsSrcNone = + SYSCON_USB0CLKSEL_SEL(7) /*!VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + ret = __VECTOR_RAM[irq + 16]; + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[irq + 16] = irqHandler; + + EnableGlobalIRQ(irqMaskValue); + SDK_ISR_EXIT_BARRIER; + + return ret; +} +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#endif /* __GIC_PRIO_BITS. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) +#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) + +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERSET[index] = 1u << intNumber; + EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERCLR[index] = 1u << intNumber; +} +#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +void *SDK_Malloc(size_t size, size_t alignbytes) +{ + mem_align_cb_t *p_cb = NULL; + uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t); + union + { + void *pointer_value; + uint32_t unsigned_value; + } p_align_addr, p_addr; + + p_addr.pointer_value = malloc(alignedsize); + + if (p_addr.pointer_value == NULL) + { + return NULL; + } + + p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes); + + p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U); + p_cb->identifier = SDK_MEM_MAGIC_NUMBER; + p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value); + + return p_align_addr.pointer_value; +} + +void SDK_Free(void *ptr) +{ + union + { + void *pointer_value; + uint32_t unsigned_value; + } p_free; + p_free.pointer_value = ptr; + mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U); + + if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) + { + return; + } + + p_free.unsigned_value = p_free.unsigned_value - p_cb->offset; + + free(p_free.pointer_value); +} + +/*! + * @brief Delay function bases on while loop, every loop includes three instructions. + * + * @param count Counts of loop needed for dalay. + */ +#if defined(SDK_DELAY_USE_DWT) && defined(DWT) +void enableCpuCycleCounter(void) +{ + /* Make sure the DWT trace fucntion is enabled. */ + if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) + { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } + + /* CYCCNT not supported on this device. */ + assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); + + /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */ + if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) + { + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; + } +} + +uint32_t getCpuCycleCount(void) +{ + return DWT->CYCCNT; +} +#elif defined __XCC__ +extern uint32_t xthal_get_ccount(void); +void enableCpuCycleCounter(void) +{ + /* do nothing */ +} + +uint32_t getCpuCycleCount(void) +{ + return xthal_get_ccount(); +} +#endif + +#ifndef __XCC__ +#if (!defined(SDK_DELAY_USE_DWT)) || (!defined(DWT)) +#if defined(__CC_ARM) /* This macro is arm v5 specific */ +/* clang-format off */ +__ASM static void DelayLoop(uint32_t count) +{ +loop + SUBS R0, R0, #1 + CMP R0, #0 + BNE loop + BX LR +} +/* clang-format on */ +#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__) +/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler, + * use SUB and CMP here for compatibility */ +static void DelayLoop(uint32_t count) +{ + __ASM volatile(" MOV R0, %0" : : "r"(count)); + __ASM volatile( + "loop: \n" +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + " SUB R0, R0, #1 \n" +#else + " SUBS R0, R0, #1 \n" +#endif + " CMP R0, #0 \n" + + " BNE loop \n"); +} +#endif /* defined(__CC_ARM) */ +#endif /* (!defined(SDK_DELAY_USE_DWT)) || (!defined(DWT)) */ +#endif /* __XCC__ */ +/*! + * @brief Delay at least for some time. + * Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have + * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delay_us and + * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delay_us only supports + * up to 4294967 in current code. If long time delay is needed, please implement a new delay function. + * + * @param delay_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz) +{ + assert(0U != delay_us); + uint64_t count = USEC_TO_COUNT(delay_us, coreClock_Hz); + assert(count <= UINT32_MAX); + +#if defined(SDK_DELAY_USE_DWT) && defined(DWT) || (defined __XCC__) /* Use DWT for better accuracy */ + + enableCpuCycleCounter(); + /* Calculate the count ticks. */ + count += getCpuCycleCount(); + + if (count > UINT32_MAX) + { + count -= UINT32_MAX; + /* Wait for cyccnt overflow. */ + while (count < getCpuCycleCount()) + { + } + } + + /* Wait for cyccnt reach count value. */ + while (count > getCpuCycleCount()) + { + } +#else + /* Divide value may be different in various environment to ensure delay is precise. + * Every loop count includes three instructions, due to Cortex-M7 sometimes executes + * two instructions in one period, through test here set divide 1.5. Other M cores use + * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does + * not matter because other instructions outside while loop is enough to fill the time. + */ +#if (__CORTEX_M == 7) + count = count / 3U * 2U; +#else + count = count / 4U; +#endif + DelayLoop((uint32_t)count); +#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) || (defined __XCC__) */ +} diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_common.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_common.h new file mode 100644 index 000000000..358f973b9 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_common.h @@ -0,0 +1,672 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_COMMON_H_ +#define _FSL_COMMON_H_ + +#include +#include +#include +#include +#include + +#if defined(__ICCARM__) +#include +#endif + +/* + * For CMSIS pack RTE. + * CMSIS pack RTE generates "RTC_Components.h" which contains the statements + * of the related element for all selected software components. + */ +#ifdef _RTE_ +#include "RTE_Components.h" +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/*! @brief Construct the version number for drivers. */ +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/*! @name Driver version */ +/*@{*/ +/*! @brief common driver version 2.2.4. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 2, 4)) +/*@}*/ + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ + kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ + kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ + kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/ + kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */ + kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */ + + kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ + kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ + kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ + kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ + kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ + kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ + kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ + kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ + kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ + kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ + kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ + kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ + kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ + kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ + kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ + kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ + kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ + kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ + kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ + kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ + kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ + kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ + kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */ + kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */ + kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */ + +}; + +/*! \public + * @brief Generic status return codes. + */ +enum +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */ + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */ + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */ + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */ + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */ + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */ + kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */ +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/* + * Macro guard for whether to use default weak IRQ implementation in drivers + */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + +/*! @name Min/max macros */ +/* @{ */ +#if !defined(MIN) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +/* @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/*! @name UINT16_MAX/UINT32_MAX value */ +/* @{ */ +#if !defined(UINT16_MAX) +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +#define UINT32_MAX ((uint32_t)-1) +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000000U / (clockFreqInHz)) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000U / (clockFreqInHz)) +/* @} */ + +/*! @name ISR exit barrier + * @{ + * + * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + * exception return operation might vector to incorrect interrupt. + * For Cortex-M7, if core speed much faster than peripheral register write speed, + * the peripheral interrupt flags may be still set after exiting ISR, this results to + * the same error similar with errata 83869. + */ +#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U)) +#define SDK_ISR_EXIT_BARRIER __DSB() +#else +#define SDK_ISR_EXIT_BARRIER +#endif + +/* @} */ + +/*! @name Alignment variable definition macros */ +/* @{ */ +#if (defined(__ICCARM__)) +/** + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http:/ /supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var +#endif +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var +#endif +#elif defined(__GNUC__) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) +#endif +#else +#error Toolchain not supported +#define SDK_ALIGN(var, alignbytes) var +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var +#endif +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var +#endif +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) +/* @} */ + +/*! @name Non-cacheable region definition macros */ +/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, + * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables + * will be initialized to zero in system startup. + */ +/* @{ */ +#if (defined(__ICCARM__)) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#endif +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var +#if(defined(__CC_ARM)) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var +#else +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var +#endif +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var +#endif +#elif(defined(__XCC__)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes))) +#elif(defined(__GNUC__)) +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes))) +#endif +#else +#error Toolchain not supported. +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var +#endif +/* @} */ + +/*! @name Time sensitive region */ +/* @{ */ +#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +#else +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#else +#error Toolchain not supported. +#endif +#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ +/* @} */ + +/*! @name Ram Function */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif(defined(__GNUC__)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/* @} */ + +/*! @name Suppress fallthrough warning macro */ +/* For switch case code block, if case section ends without "break;" statement, there wil be + fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. + To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each + case section which misses "break;"statement. + */ +/* @{ */ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__ ((fallthrough)) +#else +#define SUPPRESS_FALL_THROUGH_WARNING() +#endif +/* @} */ + +#if defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) +void DefaultISR(void); +#endif +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) + extern "C" +{ +#endif + + /*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ + static inline status_t EnableIRQ(IRQn_Type interrupt) + { + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if ((uint32_t)interrupt >= (uint32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ + static inline status_t DisableIRQ(IRQn_Type interrupt) + { + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if ((uint32_t)interrupt >= (uint32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ + static inline uint32_t DisableGlobalIRQ(void) + { +#if defined (__XCC__) + return 0; +#else +#if defined(CPSR_I_Msk) + uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; + + __disable_irq(); + + return cpsr; +#else + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +#endif +#endif + } + + /*! + * @brief Enable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ + static inline void EnableGlobalIRQ(uint32_t primask) + { +#if defined (__XCC__) +#else +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#else + __set_PRIMASK(primask); +#endif +#endif + } + +#if defined(ENABLE_RAM_VECTOR_TABLE) + /*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ + uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + /*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ + void EnableDeepSleepIRQ(IRQn_Type interrupt); + + /*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ + void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + + /*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ + void *SDK_Malloc(size_t size, size_t alignbytes); + + /*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ + void SDK_Free(void *ptr); + + /*! + * @brief Delay at least for some time. + * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, + * if precise delay count was needed, please implement a new delay function with hardware timer. + * + * @param delay_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ + void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_COMMON_H_ */ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_flexcomm.c b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_flexcomm.c new file mode 100644 index 000000000..902ebef52 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_flexcomm.c @@ -0,0 +1,339 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm" +#endif + +/*! + * @brief Used for conversion between `void*` and `uint32_t`. + */ +typedef union pvoid_to_u32 +{ + void *pvoid; + uint32_t u32; +} pvoid_to_u32_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! @brief Set the FLEXCOMM mode . */ +static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock); + +/*! @brief check whether flexcomm supports peripheral type */ +static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ +static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT]; + +/*! @brief Pointers to handles for each instance to provide context to interrupt routines */ +static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT]; + +/*! @brief Array to map FLEXCOMM instance number to IRQ number. */ +IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS; + +/*! @brief Array to map FLEXCOMM instance number to base address. */ +static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief IDs of clock for each FLEXCOMM module */ +static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) +/*! @brief Pointers to FLEXCOMM resets for each instance. */ +static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* check whether flexcomm supports peripheral type */ +static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph) +{ + if (periph == FLEXCOMM_PERIPH_NONE) + { + return true; + } + else if (periph <= FLEXCOMM_PERIPH_I2S_TX) + { + return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false; + } + else if (periph == FLEXCOMM_PERIPH_I2S_RX) + { + return (base->PSELID & (1U << 7U)) > (uint32_t)0U ? true : false; + } + else + { + return false; + } +} + +/* Get the index corresponding to the FLEXCOMM */ +/*! brief Returns instance number for FLEXCOMM module with given base address. */ +uint32_t FLEXCOMM_GetInstance(void *base) +{ + uint32_t i; + pvoid_to_u32_t BaseAddr; + BaseAddr.pvoid = base; + + for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++) + { + if (BaseAddr.u32 == s_flexcommBaseAddrs[i]) + { + break; + } + } + + assert(i < FSL_FEATURE_SOC_FLEXCOMM_COUNT); + return i; +} + +/* Changes FLEXCOMM mode */ +static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock) +{ + /* Check whether peripheral type is present */ + if (!FLEXCOMM_PeripheralIsPresent(base, periph)) + { + return kStatus_OutOfRange; + } + + /* Flexcomm is locked to different peripheral type than expected */ + if (((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) != 0U) && + ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph)) + { + return kStatus_Fail; + } + + /* Check if we are asked to lock */ + if (lock != 0) + { + base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK; + } + else + { + base->PSELID = (uint32_t)periph; + } + + return kStatus_Success; +} + +/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ +status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) +{ + uint32_t idx = FLEXCOMM_GetInstance(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the peripheral clock */ + CLOCK_EnableClock(s_flexcommClocks[idx]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) + /* Reset the FLEXCOMM module */ + RESET_PeripheralReset(s_flexcommResets[idx]); +#endif + + /* Set the FLEXCOMM to given peripheral */ + return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0); +} + +/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM + * mode */ +void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(base); + + /* Clear handler first to avoid execution of the handler with wrong handle */ + s_flexcommIrqHandler[instance] = NULL; + s_flexcommHandle[instance] = handle; + s_flexcommIrqHandler[instance] = handler; + SDK_ISR_EXIT_BARRIER; +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(FLEXCOMM0) +void FLEXCOMM0_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[0]); + s_flexcommIrqHandler[0]((uint32_t *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM1) +void FLEXCOMM1_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[1]); + s_flexcommIrqHandler[1]((uint32_t *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM2) +void FLEXCOMM2_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[2]); + s_flexcommIrqHandler[2]((uint32_t *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM3) +void FLEXCOMM3_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[3]); + s_flexcommIrqHandler[3]((uint32_t *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM4) +void FLEXCOMM4_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[4]); + s_flexcommIrqHandler[4]((uint32_t *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]); + SDK_ISR_EXIT_BARRIER; +} + +#endif + +#if defined(FLEXCOMM5) +void FLEXCOMM5_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[5]); + s_flexcommIrqHandler[5]((uint32_t *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM6) +void FLEXCOMM6_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[6]); + s_flexcommIrqHandler[6]((uint32_t *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM7) +void FLEXCOMM7_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[7]); + s_flexcommIrqHandler[7]((uint32_t *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM8) +void FLEXCOMM8_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[8]); + s_flexcommIrqHandler[8]((uint32_t *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM9) +void FLEXCOMM9_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[9]); + s_flexcommIrqHandler[9]((uint32_t *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM10) +void FLEXCOMM10_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[10]); + s_flexcommIrqHandler[10]((uint32_t *)s_flexcommBaseAddrs[10], s_flexcommHandle[10]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM11) +void FLEXCOMM11_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[11]); + s_flexcommIrqHandler[11]((uint32_t *)s_flexcommBaseAddrs[11], s_flexcommHandle[11]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM12) +void FLEXCOMM12_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[12]); + s_flexcommIrqHandler[12]((uint32_t *)s_flexcommBaseAddrs[12], s_flexcommHandle[12]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM13) +void FLEXCOMM13_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[13]); + s_flexcommIrqHandler[13]((uint32_t *)s_flexcommBaseAddrs[13], s_flexcommHandle[13]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM14) +void FLEXCOMM14_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM14); + assert(s_flexcommIrqHandler[instance]); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM15) +void FLEXCOMM15_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM15); + assert(s_flexcommIrqHandler[instance]); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM16) +void FLEXCOMM16_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM16); + assert(s_flexcommIrqHandler[instance]); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_flexcomm.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_flexcomm.h new file mode 100644 index 000000000..cf5b6ef99 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_flexcomm.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_FLEXCOMM_H_ +#define _FSL_FLEXCOMM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexcomm_driver + * @{ + */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexCOMM driver version 2.0.2. */ +#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! @brief FLEXCOMM peripheral modes. */ +typedef enum +{ + FLEXCOMM_PERIPH_NONE, /*!< No peripheral */ + FLEXCOMM_PERIPH_USART, /*!< USART peripheral */ + FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */ + FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */ + FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */ + FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */ +} FLEXCOMM_PERIPH_T; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*flexcomm_irq_handler_t)(void *base, void *handle); + +/*! @brief Array with IRQ number for each FLEXCOMM module. */ +extern IRQn_Type const kFlexcommIrqs[]; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @brief Returns instance number for FLEXCOMM module with given base address. */ +uint32_t FLEXCOMM_GetInstance(void *base); + +/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ +status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph); + +/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM + * mode */ +void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle); + +#if defined(__cplusplus) +} +#endif + +/*@}*/ + +#endif /* _FSL_FLEXCOMM_H_*/ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_gpio.c b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_gpio.c new file mode 100644 index 000000000..3d9a7a277 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_gpio.c @@ -0,0 +1,302 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_gpio.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map FGPIO instance number to clock name. */ +static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) +/*! @brief Pointers to GPIO resets for each instance. */ +static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N; +#endif +/******************************************************************************* + * Prototypes + ************ ******************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * param base GPIO peripheral base pointer. + * param port GPIO port number. + */ +void GPIO_PortInit(GPIO_Type *base, uint32_t port) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + assert(port < ARRAY_SIZE(s_gpioClockName)); + + /* Upgate the GPIO clock */ + CLOCK_EnableClock(s_gpioClockName[port]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) + /* Reset the GPIO module */ + RESET_PeripheralReset(s_gpioResets[port]); +#endif +} + +/*! + * brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base GPIO peripheral base pointer(Typically GPIO) + * param port GPIO port number + * param pin GPIO pin number + * param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) +{ + if (config->pinDirection == kGPIO_DigitalInput) + { +#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) + base->DIRCLR[port] = 1UL << pin; +#else + base->DIR[port] &= ~(1UL << pin); +#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ + } + else + { + /* Set default output value */ + if (config->outputLogic == 0U) + { + base->CLR[port] = (1UL << pin); + } + else + { + base->SET[port] = (1UL << pin); + } +/* Set pin direction */ +#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) + base->DIRSET[port] = 1UL << pin; +#else + base->DIR[port] |= 1UL << pin; +#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ + } +} + +#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT +/*! + * @brief Set the configuration of pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param pin GPIO pin number. + * @param config GPIO pin interrupt configuration.. + */ +void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config) +{ + base->INTEDG[port] = (base->INTEDG[port] & ~(1UL << pin)) | ((uint32_t)config->mode << pin); + + base->INTPOL[port] = (base->INTPOL[port] & ~(1UL << pin)) | ((uint32_t)config->polarity << pin); +} + +/*! + * @brief Enables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] | mask; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] | mask; + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Disables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] & ~mask; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] & ~mask; + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Clears multiple pins interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTSTATA[port] = mask; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTSTATB[port] = mask; + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @ Read port interrupt status. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param index GPIO interrupt number. + * @retval masked GPIO status value + */ +uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index) +{ + uint32_t status = 0U; + + if ((uint32_t)kGPIO_InterruptA == index) + { + status = base->INTSTATA[port]; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + status = base->INTSTATB[port]; + } + else + { + /*Should not enter here*/ + } + return status; +} + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] | (1UL << pin); + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] | (1UL << pin); + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] & ~(1UL << pin); + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] & ~(1UL << pin); + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Clears the specific pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTSTATA[port] = 1UL << pin; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTSTATB[port] = 1UL << pin; + } + else + { + /*Should not enter here*/ + } +} +#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_gpio.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_gpio.h new file mode 100644 index 000000000..89b0906b6 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_gpio.h @@ -0,0 +1,364 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _LPC_GPIO_H_ +#define _LPC_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_gpio + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPC GPIO driver version. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 6)) +/*@}*/ + +/*! @brief LPC GPIO direction definition */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} gpio_pin_direction_t; + +/*! + * @brief The GPIO pin configuration structure. + * + * Every pin can only be configured as either output pin or input pin at a time. + * If configured as a input pin, then leave the outputConfig unused. + */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ + /* Output configurations, please ignore if configured as a input one */ + uint8_t outputLogic; /*!< Set default output logic, no use in input */ +} gpio_pin_config_t; + +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT) +#define GPIO_PIN_INT_LEVEL 0x00U +#define GPIO_PIN_INT_EDGE 0x01U + +#define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U +#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U + +/*! @brief GPIO Pin Interrupt enable mode */ +typedef enum _gpio_pin_enable_mode +{ + kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */ + kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE /*!< Generate Pin Interrupt on edge mode */ +} gpio_pin_enable_mode_t; + +/*! @brief GPIO Pin Interrupt enable polarity */ +typedef enum _gpio_pin_enable_polarity +{ + kGPIO_PinIntEnableHighOrRise = + PINT_PIN_INT_HIGH_OR_RISE_TRIGGER, /*!< Generate Pin Interrupt on high level or rising edge */ + kGPIO_PinIntEnableLowOrFall = + PINT_PIN_INT_LOW_OR_FALL_TRIGGER /*!< Generate Pin Interrupt on low level or falling edge */ +} gpio_pin_enable_polarity_t; + +/*! @brief LPC GPIO interrupt index definition */ +typedef enum _gpio_interrupt_index +{ + kGPIO_InterruptA = 0U, /*!< Set current pin as interrupt A*/ + kGPIO_InterruptB = 1U, /*!< Set current pin as interrupt B*/ +} gpio_interrupt_index_t; + +/*! @brief Configures the interrupt generation condition. */ +typedef struct _gpio_interrupt_config +{ + uint8_t mode; /* The trigger mode of GPIO interrupts */ + uint8_t polarity; /* The polarity of GPIO interrupts */ +} gpio_interrupt_config_t; +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @name GPIO Configuration */ +/*@{*/ + +/*! + * @brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * @param base GPIO peripheral base pointer. + * @param port GPIO port number. + */ +void GPIO_PortInit(GPIO_Type *base, uint32_t port); + +/*! + * @brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * @code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config); + +/*@}*/ + +/*! @name GPIO Output Operations */ +/*@{*/ + +/*! + * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @param output GPIO pin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) +{ + base->B[port][pin] = output; +} + +/*@}*/ +/*! @name GPIO Input Operations */ +/*@{*/ + +/*! + * @brief Reads the current input value of the GPIO PIN. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @retval GPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) +{ + return (uint32_t)base->B[port][pin]; +} + +/*@}*/ + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->SET[port] = mask; +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->CLR[port] = mask; +} + +/*! + * @brief Reverses current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->NOT[port] = mask; +} + +/*@}*/ + +/*! + * @brief Reads the current input value of the whole GPIO port. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + */ +static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port) +{ + return (uint32_t)base->PIN[port]; +} + +/*@}*/ +/*! @name GPIO Mask Operations */ +/*@{*/ + +/*! + * @brief Sets port mask, 0 - enable pin, 1 - disable pin. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->MASK[port] = mask; +} + +/*! + * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param output GPIO port output value. + */ +static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output) +{ + base->MPIN[port] = output; +} + +/*! + * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be + * affected. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @retval masked GPIO port value + */ +static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) +{ + return (uint32_t)base->MPIN[port]; +} + +#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT +/*! + * @brief Set the configuration of pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param pin GPIO pin number. + * @param config GPIO pin interrupt configuration.. + */ +void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config); + +/*! + * @brief Enables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); + +/*! + * @brief Disables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); + +/*! + * @brief Clears pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); + +/*! + * @ Read port interrupt status. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param index GPIO interrupt number. + * @retval masked GPIO status value + */ +uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index); + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); + +/*! + * @brief Clears the specific pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); + +#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _LPC_GPIO_H_*/ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iap.c b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iap.c new file mode 100644 index 000000000..1179f24f0 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iap.c @@ -0,0 +1,600 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "fsl_iap.h" +#include "fsl_iap_ffr.h" +#include "fsl_iap_kbp.h" +#include "fsl_iap_skboot_authenticate.h" +#include "fsl_device_registers.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iap1" +#endif + +#if (defined(LPC5512_SERIES) || defined(LPC5514_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ + defined(LPC55S16_SERIES) || defined(LPC5524_SERIES)) + +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1301fe00U) + +#elif (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || defined(LPC5526_SERIES) || \ + defined(LPC55S26_SERIES) || defined(LPC5528_SERIES) || defined(LPC55S28_SERIES) || \ + defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES)) + +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x130010f0U) + +#else +#error "No valid CPU defined!" + +#endif + +/*! + * @name flash and ffr Structure + * @{ + */ + +typedef union functionCommandOption +{ + uint32_t commandAddr; + status_t (*eraseCommand)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*programCommand)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + status_t (*verifyProgramCommand)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + status_t (*flashReadCommand)(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); +} function_command_option_t; + +/* + *!@brief Structure of version property. + * + *!@ingroup bl_core + */ +typedef union StandardVersion +{ + struct + { + uint32_t bugfix : 8; /*!< bugfix version [7:0] */ + uint32_t minor : 8; /*!< minor version [15:8] */ + uint32_t major : 8; /*!< major version [23:16] */ + uint32_t name : 8; /*!< name [31:24] */ + }; + uint32_t version; /*!< combined version numbers. */ +#if defined(__cplusplus) + StandardVersion() : version(0) + { + } + StandardVersion(uint32_t version) : version(version) + { + } +#endif +} standard_version_t; + +/*! @brief Interface for the flash driver.*/ +typedef struct version1FlashDriverInterface +{ + standard_version_t version; /*!< flash driver API version number.*/ + + /*!< Flash driver.*/ + status_t (*flash_init)(flash_config_t *config); + status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + status_t (*flash_verify_program)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + uint32_t reserved[3]; /*! Reserved for future use */ + /*!< Flash FFR driver*/ + status_t (*ffr_init)(flash_config_t *config); + status_t (*ffr_lock_all)(flash_config_t *config); + status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); + status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); + status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); + status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode); + status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); + status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); +} version1_flash_driver_interface_t; + +/*! @brief Interface for the flash driver.*/ +typedef struct version0FlashDriverInterface +{ + standard_version_t version; /*!< flash driver API version number.*/ + + /*!< Flash driver.*/ + status_t (*flash_init)(flash_config_t *config); + status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + status_t (*flash_verify_program)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + + /*!< Flash FFR driver*/ + status_t (*ffr_init)(flash_config_t *config); + status_t (*ffr_lock_all)(flash_config_t *config); + status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); + status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); + status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); + status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode); + status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); + status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); +} version0_flash_driver_interface_t; + +typedef union flashDriverInterface +{ + const version1_flash_driver_interface_t *version1FlashDriver; + const version0_flash_driver_interface_t *version0FlashDriver; +} flash_driver_interface_t; + +/*! @}*/ + +/*! + * @name Bootloader API and image authentication Structure + * @{ + */ + +/*! @brief Interface for Bootloader API functions. */ +typedef struct _kb_interface +{ + /*!< Initialize the API. */ + status_t (*kb_init_function)(kb_session_ref_t **session, const kb_options_t *options); + status_t (*kb_deinit_function)(kb_session_ref_t *session); + status_t (*kb_execute_function)(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength); +} kb_interface_t; + +//! @brief Interface for image authentication API +typedef struct _skboot_authenticate_interface +{ + skboot_status_t (*skboot_authenticate_function)(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified); + void (*skboot_hashcrypt_irq_handler)(void); +} skboot_authenticate_interface_t; +/*! @}*/ + +/*! + * @brief Root of the bootloader API tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + * @note The order of existing fields must not be changed. + */ +typedef struct BootloaderTree +{ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing. */ + standard_version_t bootloader_version; /*!< Bootloader version number. */ + const char *copyright; /*!< Copyright string. */ + const uint32_t reserved0; /*!< Do NOT use. */ + flash_driver_interface_t flashDriver; + const kb_interface_t *kbApi; /*!< Bootloader API. */ + const uint32_t reserved1[4]; /*!< Do NOT use. */ + const skboot_authenticate_interface_t *skbootAuthenticate; /*!< Image authentication API. */ +} bootloader_tree_t; + +/******************************************************************************* + * Prototype + ******************************************************************************/ +static uint32_t get_rom_api_version(void); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! Get pointer to flash driver API table in ROM. */ +#define VERSION1_FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver.version1FlashDriver +#define VERSION0_FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver.version0FlashDriver +#define LPC55S69_REV0_FLASH_READ_ADDR (0x130043a3U) +#define LPC55S69_REV1_FLASH_READ_ADDR (0x13007539U) +#define LPC55S16_REV0_FLASH_READ_ADDR (0x1300ade5U) + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t get_rom_api_version(void) +{ + if (BOOTLOADER_API_TREE_POINTER->bootloader_version.major == 3u) + { + return 1u; + } + else + { + return 0u; + } +} + +/*! + * @brief Initializes the global flash properties structure members. + * + * This function checks and initializes the Flash module for the other Flash APIs. + */ +status_t FLASH_Init(flash_config_t *config) +{ + /* Initialize the clock to 96MHz */ + config->modeConfig.sysFreqInMHz = (uint32_t)kSysToFlashFreq_defaultInMHz; + if (get_rom_api_version() == 1u) + { + return VERSION1_FLASH_API_TREE->flash_init(config); + } + else + { + return VERSION0_FLASH_API_TREE->flash_init(config); + } +} + +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + */ +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + if (get_rom_api_version() == 0u) + { + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = 0x1300413bU; /*!< get the flash erase api location adress in rom */ + return runCmdFuncOption.eraseCommand(config, start, lengthInBytes, key); + } + else + { + return VERSION1_FLASH_API_TREE->flash_erase(config, start, lengthInBytes, key); + } +} + +/*! See fsl_iap.h for documentation of this function. */ +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + if (get_rom_api_version() == 0u) + { + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = 0x1300419dU; /*!< get the flash program api location adress in rom*/ + return runCmdFuncOption.programCommand(config, start, src, lengthInBytes); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->flash_program(config, start, src, lengthInBytes); + } +} + +/*! See fsl_iap.h for documentation of this function. */ +status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes) +{ + if (get_rom_api_version() == 0u) + { + /*!< get the flash read api location adress in rom*/ + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = LPC55S69_REV0_FLASH_READ_ADDR; + return runCmdFuncOption.flashReadCommand(config, start, dest, lengthInBytes); + } + else + { + /*!< get the flash read api location adress in rom*/ + function_command_option_t runCmdFuncOption; + if ((SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK) != 0u) + { + runCmdFuncOption.commandAddr = LPC55S69_REV1_FLASH_READ_ADDR; + } + else + { + runCmdFuncOption.commandAddr = LPC55S16_REV0_FLASH_READ_ADDR; + } + return runCmdFuncOption.flashReadCommand(config, start, dest, lengthInBytes); + } +} + +/*! See fsl_iap.h for documentation of this function. */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) +{ + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->flash_verify_erase(config, start, lengthInBytes); +} + +/*! + * @brief Verifies programming of the desired flash area at a specified margin level. + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it to the expected data for a given + * flash area as determined by the start address and length. + */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData) +{ + if (get_rom_api_version() == 0u) + { + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = 0x1300427dU; /*!< get the flash verify program api location adress in rom*/ + return runCmdFuncOption.verifyProgramCommand(config, start, lengthInBytes, expectedData, failedAddress, + failedData); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->flash_verify_program(config, start, lengthInBytes, expectedData, failedAddress, + failedData); + } +} + +/*! + * @brief Returns the desired flash property. + */ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) +{ + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->flash_get_property(config, whichProperty, value); +} +/******************************************************************************** + * fsl iap ffr CODE + *******************************************************************************/ + +/*! + * Initializes the global FFR properties structure members. + */ +status_t FFR_Init(flash_config_t *config) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_init(config); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_init(config); + } +} + +/*! + * Enable firewall for all flash banks. + */ +status_t FFR_Lock_All(flash_config_t *config) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_lock_all(config); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_lock_all(config); + } +} + +/*! + * APIs to access CMPA pages; + * This routine will erase "customer factory page" and program the page with passed data. + */ +status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part); + } +} + +/*! + * See fsl_iap_ffr.h for documentation of this function. + */ +status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_get_uuid(config, uuid); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_get_uuid(config, uuid); + } +} + +/*! + * APIs to access CMPA pages + * Read data stored in 'Customer Factory CFG Page'. + */ +status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len); + } +} + +/*! + * This routine writes the 3 pages allocated for Key store data, + * Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state. + */ +status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_keystore_write(config, pKeyStore); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_keystore_write(config, pKeyStore); + } +} + +/*! See fsl_iap_ffr.h for documentation of this function. */ +status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode); + } +} + +/*! See fsl_iap_ffr.h for documentation of this function. */ +status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex); + } +} + +/*! + * APIs to access CFPA pages + * This routine will erase CFPA and program the CFPA page with passed data. + */ +status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len); + } +} + +/*! + * APIs to access CFPA pages + * Generic read function, used by customer to read data stored in 'Customer In-field Page'. + */ +status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len); + } +} + +/******************************************************************************** + * Bootloader API + *******************************************************************************/ +/*! + * @brief Initialize ROM API for a given operation. + * + * Inits the ROM API based on the options provided by the application in the second + * argument. Every call to rom_init() should be paired with a call to rom_deinit(). + */ +status_t kb_init(kb_session_ref_t **session, const kb_options_t *options) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->kbApi->kb_init_function(session, options); +} + +/*! + * @brief Cleans up the ROM API context. + * + * After this call, the @a context parameter can be reused for another operation + * by calling rom_init() again. + */ +status_t kb_deinit(kb_session_ref_t *session) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->kbApi->kb_deinit_function(session); +} + +/*! + * Perform the operation configured during init. + * + * This application must call this API repeatedly, passing in sequential chunks of + * data from the boot image (SB file) that is to be processed. The ROM will perform + * the selected operation on this data and return. The application may call this + * function with as much or as little data as it wishes, which can be used to select + * the granularity of time given to the application in between executing the operation. + * + * @param context Current ROM context pointer. + * @param data Buffer of boot image data provided to the ROM by the application. + * @param dataLength Length in bytes of the data in the buffer provided to the ROM. + * + * @retval #kStatus_Success The operation has completed successfully. + * @retval #kStatus_Fail An error occurred while executing the operation. + * @retval #kStatus_RomApiNeedMoreData No error occurred, but the ROM needs more data to + * continue processing the boot image. + */ +status_t kb_execute(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->kbApi->kb_execute_function(session, data, dataLength); +} + +/******************************************************************************** + * Image authentication API + *******************************************************************************/ + +/*! + * @brief Authenticate entry function with ARENA allocator init + * + * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface + */ +skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->skbootAuthenticate->skboot_authenticate_function(imageStartAddr, + isSignVerified); +} + +/*! + * @brief Interface for image authentication API + */ +void HASH_IRQHandler(void) +{ + assert(BOOTLOADER_API_TREE_POINTER); + BOOTLOADER_API_TREE_POINTER->skbootAuthenticate->skboot_hashcrypt_irq_handler(); +} +/******************************************************************************** + * EOF + *******************************************************************************/ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iap.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iap.h new file mode 100644 index 000000000..a251f2ceb --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iap.h @@ -0,0 +1,528 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_IAP_H_ +#define __FSL_IAP_H_ + +#include "fsl_common.h" +/*! + * @addtogroup flash_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! + * @name Flash version + * @{ + */ +/*! @brief Constructs the version number for drivers. */ +#if !defined(MAKE_VERSION) +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) +#endif + +/*! @brief Flash driver version for SDK*/ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ + +/*! @brief Flash driver version for ROM*/ +enum _flash_driver_version_constants +{ + kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ + kFLASH_DriverVersionMajor = 2, /*!< Major flash driver version.*/ + kFLASH_DriverVersionMinor = 1, /*!< Minor flash driver version.*/ + kFLASH_DriverVersionBugfix = 0 /*!< Bugfix for flash driver version.*/ +}; + +/*@}*/ + +/*! + * @name Flash configuration + * @{ + */ +/*! @brief Flash IP Type. */ +#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC) +#define FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC (1) +#endif +#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_FC) +#define FSL_FEATURE_FLASH_IP_IS_C040HD_FC (0) +#endif + +/*! + * @name Flash status + * @{ + */ +/*! @brief Flash driver status group. */ +#if defined(kStatusGroup_FlashDriver) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FlashDriver +#elif defined(kStatusGroup_FLASHIAP) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FLASH +#else +#define kStatusGroupGeneric 0 +#define kStatusGroupFlashDriver 1 +#endif + +/*! @brief Constructs a status code value from a group and a code number. */ +#if !defined(MAKE_STATUS) +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) +#endif + +/*! + * @brief Flash driver status codes. + */ +enum _flash_status +{ + kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ + kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ + kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ + kStatus_FLASH_AlignmentError = + MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ + kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ + kStatus_FLASH_AccessError = + MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ + kStatus_FLASH_ProtectionViolation = MAKE_STATUS( + kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ + kStatus_FLASH_CommandFailure = + MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ + kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ + kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/ + kStatus_FLASH_RegionExecuteOnly = + MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/ + kStatus_FLASH_ExecuteInRamFunctionNotReady = + MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/ + + kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Flash API is not supported.*/ + kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< The flash property is read-only.*/ + kStatus_FLASH_InvalidPropertyValue = + MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< The flash property value is out of range.*/ + kStatus_FLASH_InvalidSpeculationOption = + MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< The option of flash prefetch speculation is invalid.*/ + kStatus_FLASH_EccError = MAKE_STATUS(kStatusGroupFlashDriver, + 0x10), /*!< A correctable or uncorrectable error during command execution. */ + kStatus_FLASH_CompareError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x11), /*!< Destination and source memory contents do not match. */ + kStatus_FLASH_RegulationLoss = MAKE_STATUS(kStatusGroupFlashDriver, 0x12), /*!< A loss of regulation during read. */ + kStatus_FLASH_InvalidWaitStateCycles = + MAKE_STATUS(kStatusGroupFlashDriver, 0x13), /*!< The wait state cycle set to r/w mode is invalid. */ + + kStatus_FLASH_OutOfDateCfpaPage = + MAKE_STATUS(kStatusGroupFlashDriver, 0x20), /*!< CFPA page version is out of date. */ + kStatus_FLASH_BlankIfrPageData = MAKE_STATUS(kStatusGroupFlashDriver, 0x21), /*!< Blank page cannnot be read. */ + kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce = + MAKE_STATUS(kStatusGroupFlashDriver, 0x22), /*!< Encrypted flash subregions are not erased at once. */ + kStatus_FLASH_ProgramVerificationNotAllowed = MAKE_STATUS( + kStatusGroupFlashDriver, 0x23), /*!< Program verification is not allowed when the encryption is enabled. */ + kStatus_FLASH_HashCheckError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x24), /*!< Hash check of page data is failed. */ + kStatus_FLASH_SealedFfrRegion = MAKE_STATUS(kStatusGroupFlashDriver, 0x25), /*!< The FFR region is sealed. */ + kStatus_FLASH_FfrRegionWriteBroken = MAKE_STATUS( + kStatusGroupFlashDriver, 0x26), /*!< The FFR Spec region is not allowed to be written discontinuously. */ + kStatus_FLASH_NmpaAccessNotAllowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x27), /*!< The NMPA region is not allowed to be read/written/erased. */ + kStatus_FLASH_CmpaCfgDirectEraseNotAllowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x28), /*!< The CMPA Cfg region is not allowed to be erased directly. */ + kStatus_FLASH_FfrBankIsLocked = MAKE_STATUS(kStatusGroupFlashDriver, 0x29), /*!< The FFR bank region is locked. */ +}; +/*@}*/ + +/*! + * @name Flash API key + * @{ + */ +/*! @brief Constructs the four character code for the Flash driver API key. */ +#if !defined(FOUR_CHAR_CODE) +#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) +#endif + +/*! + * @brief Enumeration for Flash driver API keys. + * + * @note The resulting value is built with a byte order such that the string + * being readable in expected order when viewed in a hex editor, if the value + * is treated as a 32-bit little endian value. + */ +enum _flash_driver_api_keys +{ + kFLASH_ApiEraseKey = FOUR_CHAR_CODE('l', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ +}; +/*@}*/ + +/*! + * @brief Enumeration for various flash properties. + */ +typedef enum _flash_property_tag +{ + kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ + kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ + kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ + kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ + kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ + + kFLASH_PropertyPflashPageSize = 0x30U, /*!< Pflash page size property.*/ + kFLASH_PropertyPflashSystemFreq = 0x31U, /*!< System Frequency System Frequency.*/ + + kFLASH_PropertyFfrSectorSize = 0x40U, /*!< FFR sector size property.*/ + kFLASH_PropertyFfrTotalSize = 0x41U, /*!< FFR total size property.*/ + kFLASH_PropertyFfrBlockBaseAddr = 0x42U, /*!< FFR block base address property.*/ + kFLASH_PropertyFfrPageSize = 0x43U, /*!< FFR page size property.*/ +} flash_property_tag_t; + +/*! + * @brief Enumeration for flash max pages to erase. + */ +enum _flash_max_erase_page_value +{ + kFLASH_MaxPagesToErase = 100U /*!< The max value in pages to erase. */ +}; + +/*! + * @brief Enumeration for flash alignment property. + */ +enum _flash_alignment_property +{ + kFLASH_AlignementUnitVerifyErase = 4, /*!< The alignment unit in bytes used for verify erase operation.*/ + kFLASH_AlignementUnitProgram = 512, /*!< The alignment unit in bytes used for program operation.*/ + /*kFLASH_AlignementUnitVerifyProgram = 4,*/ /*!< The alignment unit in bytes used for verify program operation.*/ + kFLASH_AlignementUnitSingleWordRead = 16 /*!< The alignment unit in bytes used for SingleWordRead command.*/ +}; + +/*! + * @brief Enumeration for flash read ecc option + */ +enum _flash_read_ecc_option +{ + kFLASH_ReadWithEccOn = 0, /*! ECC is on */ + kFLASH_ReadWithEccOff = 1, /*! ECC is off */ +}; + +/* set flash Controller timing before flash init */ +enum _flash_freq_tag +{ + kSysToFlashFreq_lowInMHz = 12u, + kSysToFlashFreq_defaultInMHz = 96u, +}; + +/*! + * @brief Enumeration for flash read margin option + */ +enum _flash_read_margin_option +{ + kFLASH_ReadMarginNormal = 0, /*!< Normal read */ + kFLASH_ReadMarginVsProgram = 1, /*!< Margin vs. program */ + kFLASH_ReadMarginVsErase = 2, /*!< Margin vs. erase */ + kFLASH_ReadMarginIllegalBitCombination = 3 /*!< Illegal bit combination */ +}; + +/*! + * @brief Enumeration for flash read dmacc option + */ +enum _flash_read_dmacc_option +{ + kFLASH_ReadDmaccDisabled = 0, /*!< Memory word */ + kFLASH_ReadDmaccEnabled = 1, /*!< DMACC word */ +}; + +/*! + * @brief Enumeration for flash ramp control option + */ +enum _flash_ramp_control_option +{ + kFLASH_RampControlDivisionFactorReserved = 0, /*!< Reserved */ + kFLASH_RampControlDivisionFactor256 = 1, /*!< clk48mhz / 256 = 187.5KHz */ + kFLASH_RampControlDivisionFactor128 = 2, /*!< clk48mhz / 128 = 375KHz */ + kFLASH_RampControlDivisionFactor64 = 3 /*!< clk48mhz / 64 = 750KHz */ +}; + +/*! @brief Flash ECC log info. */ +typedef struct _flash_ecc_log +{ + uint32_t firstEccEventAddress; + uint32_t eccErrorCount; + uint32_t eccCorrectionCount; + uint32_t reserved; +} flash_ecc_log_t; + +/*! @brief Flash controller paramter config. */ +typedef struct _flash_mode_config +{ + uint32_t sysFreqInMHz; + /* ReadSingleWord parameter. */ + struct + { + uint8_t readWithEccOff : 1; + uint8_t readMarginLevel : 2; + uint8_t readDmaccWord : 1; + uint8_t reserved0 : 4; + uint8_t reserved1[3]; + } readSingleWord; + /* SetWriteMode parameter. */ + struct + { + uint8_t programRampControl; + uint8_t eraseRampControl; + uint8_t reserved[2]; + } setWriteMode; + /* SetReadMode parameter. */ + struct + { + uint16_t readInterfaceTimingTrim; + uint16_t readControllerTimingTrim; + uint8_t readWaitStates; + uint8_t reserved[3]; + } setReadMode; +} flash_mode_config_t; + +/*! @brief Flash controller paramter config. */ +typedef struct _flash_ffr_config +{ + uint32_t ffrBlockBase; + uint32_t ffrTotalSize; + uint32_t ffrPageSize; + uint32_t cfpaPageVersion; + uint32_t cfpaPageOffset; +} flash_ffr_config_t; + +/*! @brief Flash driver state information. + * + * An instance of this structure is allocated by the user of the flash driver and + * passed into each of the driver APIs. + */ +typedef struct _flash_config +{ + uint32_t PFlashBlockBase; /*!< A base address of the first PFlash block */ + uint32_t PFlashTotalSize; /*!< The size of the combined PFlash block. */ + uint32_t PFlashBlockCount; /*!< A number of PFlash blocks. */ + uint32_t PFlashPageSize; /*!< The size in bytes of a page of PFlash. */ + uint32_t PFlashSectorSize; /*!< The size in bytes of a sector of PFlash. */ + flash_ffr_config_t ffrConfig; + flash_mode_config_t modeConfig; +} flash_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the global flash properties structure members. + * + * This function checks and initializes the Flash module for the other Flash APIs. + * + * @param config Pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Init(flash_config_t *config); + +/*@}*/ + +/*! + * @name Erasing + * @{ + */ + +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + * + * @param config The pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be erased. + * The start address need to be 512bytes-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be erased. Must be 512bytes-aligned. + * @param key The value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success API was executed successfully; + * the appropriate number of flash sectors based on the desired + * start address and length were erased successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError The address is out of range. + * @retval #kStatus_FLASH_EraseKeyError The API erase key is invalid. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + +/*@}*/ + +/*! + * @name Programming + * @{ + */ + +/*! + * @brief Programs flash with data at locations passed in through parameters. + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * 512bytes-aligned. + * @param src A pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be programmed. Must be 512bytes-aligned. + * + * @retval #kStatus_FLASH_Success API was executed successfully; the desired data were programed successfully + * into flash based on desired start address and length. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + +/*@}*/ + +/*! + * @brief Reads flash at locations passed in through parameters. + * + * This function read the flash memory from a given flash area as determined + * by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be read. + * @param dest A pointer to the dest buffer of data that is to be read + * from the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be read. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); + +/*! + * @name Verification + * @{ + */ + +/*! + * @brief Verifies an erasure of the desired flash area at a specified margin level. + * + * This function checks the appropriate number of flash sectors based on + * the desired start address and length to check whether the flash is erased + * to the specified read margin level. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. + * The start address need to be 512bytes-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be 512bytes-aligned. + * + * @retval #kStatus_FLASH_Success API was executed successfully; the specified FLASH region has been erased. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + +/*! + * @brief Verifies programming of the desired flash area at a specified margin level. + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it to the expected data for a given + * flash area as determined by the start address and length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. need be 512bytes-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. need be 512bytes-aligned. + * @param expectedData A pointer to the expected data that is to be + * verified against. + * @param failedAddress A pointer to the returned failing address. + * @param failedData A pointer to the returned failing data. Some derivatives do + * not include failed data as part of the FCCOBx registers. In this + * case, zeros are returned upon failure. + * + * @retval #kStatus_FLASH_Success API was executed successfully; + * the desired data have been successfully programed into specified FLASH region. + * + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + +/*@}*/ + +/*! + * @name Properties + * @{ + */ + +/*! + * @brief Returns the desired flash property. + * + * @param config A pointer to the storage for the driver runtime state. + * @param whichProperty The desired property from the list of properties in + * enum flash_property_tag_t + * @param value A pointer to the value returned for the desired flash property. + * + * @retval #kStatus_FLASH_Success API was executed successfully; the flash property was stored to value. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_UnknownProperty An unknown property tag. + */ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + +/*@}*/ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* __FLASH_FLASH_H_ */ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iap_ffr.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iap_ffr.h new file mode 100644 index 000000000..9481e07af --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iap_ffr.h @@ -0,0 +1,388 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_IAP_FFR_H_ +#define __FSL_IAP_FFR_H_ + +#include "fsl_iap.h" + +/*! + * @addtogroup flash_ifr_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! + * @name Flash IFR version + * @{ + */ +/*! @brief Flash IFR driver version for SDK*/ +#define FSL_FLASH_IFR_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ +/*@}*/ + +/*! @brief Alignment(down) utility. */ +#if !defined(ALIGN_DOWN) +#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) +#endif + +/*! @brief Alignment(up) utility. */ +#if !defined(ALIGN_UP) +#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) +#endif + +#define FLASH_FFR_MAX_PAGE_SIZE (512u) +#define FLASH_FFR_HASH_DIGEST_SIZE (32u) +#define FLASH_FFR_IV_CODE_SIZE (52u) + +/*! @brief flash ffr page offset. */ +enum _flash_ffr_page_offset +{ + kFfrPageOffset_CFPA = 0, /*!< Customer In-Field programmed area*/ + kFfrPageOffset_CFPA_Scratch = 0, /*!< CFPA Scratch page */ + kFfrPageOffset_CFPA_Cfg = 1, /*!< CFPA Configuration area (Ping page)*/ + kFfrPageOffset_CFPA_CfgPong = 2, /*!< Same as CFPA page (Pong page)*/ + + kFfrPageOffset_CMPA = 3, /*!< Customer Manufacturing programmed area*/ + kFfrPageOffset_CMPA_Cfg = 3, /*!< CMPA Configuration area (Part of CMPA)*/ + kFfrPageOffset_CMPA_Key = 4, /*!< Key Store area (Part of CMPA)*/ + + kFfrPageOffset_NMPA = 7, /*!< NXP Manufacturing programmed area*/ + kFfrPageOffset_NMPA_Romcp = 7, /*!< ROM patch area (Part of NMPA)*/ + kFfrPageOffset_NMPA_Repair = 9, /*!< Repair area (Part of NMPA)*/ + kFfrPageOffset_NMPA_Cfg = 15, /*!< NMPA configuration area (Part of NMPA)*/ + kFfrPageOffset_NMPA_End = 16, /*!< Reserved (Part of NMPA)*/ +}; + +/*! @brief flash ffr page number. */ +enum _flash_ffr_page_num +{ + kFfrPageNum_CFPA = 3, /*!< Customer In-Field programmed area*/ + kFfrPageNum_CMPA = 4, /*!< Customer Manufacturing programmed area*/ + kFfrPageNum_NMPA = 10, /*!< NXP Manufacturing programmed area*/ + + kFfrPageNum_CMPA_Cfg = 1, + kFfrPageNum_CMPA_Key = 3, + kFfrPageNum_NMPA_Romcp = 2, + + kFfrPageNum_SpecArea = kFfrPageNum_CFPA + kFfrPageNum_CMPA, + kFfrPageNum_Total = (kFfrPageNum_CFPA + kFfrPageNum_CMPA + kFfrPageNum_NMPA), +}; + +enum _flash_ffr_block_size +{ + kFfrBlockSize_Key = 52u, + kFfrBlockSize_ActivationCode = 1192u, +}; + +typedef enum _cfpa_cfg_cmpa_prog_process +{ + kFfrCmpaProgProcess_Pre = 0x0u, + kFfrCmpaProgProcess_Post = 0xFFFFFFFFu, +} cmpa_prog_process_t; + +typedef struct _cfpa_cfg_iv_code +{ + uint32_t keycodeHeader; + uint8_t reserved[FLASH_FFR_IV_CODE_SIZE]; +} cfpa_cfg_iv_code_t; + +typedef struct _cfpa_cfg_info +{ + uint32_t header; /*!< [0x000-0x003] */ + uint32_t version; /*!< [0x004-0x007 */ + uint32_t secureFwVersion; /*!< [0x008-0x00b */ + uint32_t nsFwVersion; /*!< [0x00c-0x00f] */ + uint32_t imageKeyRevoke; /*!< [0x010-0x013] */ + uint8_t reserved0[4]; /*!< [0x014-0x017] */ + uint32_t rotkhRevoke; /*!< [0x018-0x01b] */ + uint32_t vendorUsage; /*!< [0x01c-0x01f] */ + uint32_t dcfgNsPin; /*!< [0x020-0x013] */ + uint32_t dcfgNsDflt; /*!< [0x024-0x017] */ + uint32_t enableFaMode; /*!< [0x028-0x02b] */ + uint8_t reserved1[4]; /*!< [0x02c-0x02f] */ + cfpa_cfg_iv_code_t ivCodePrinceRegion[3]; /*!< [0x030-0x0d7] */ + uint8_t reserved2[264]; /*!< [0x0d8-0x1df] */ + uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */ +} cfpa_cfg_info_t; + +#define FFR_BOOTCFG_BOOTSPEED_MASK (0x18U) +#define FFR_BOOTCFG_BOOTSPEED_SHIFT (7U) +#define FFR_BOOTCFG_BOOTSPEED_48MHZ (0x0U) +#define FFR_BOOTCFG_BOOTSPEED_96MHZ (0x1U) + +#define FFR_USBID_VENDORID_MASK (0xFFFFU) +#define FFR_USBID_VENDORID_SHIFT (0U) +#define FFR_USBID_PRODUCTID_MASK (0xFFFF0000U) +#define FFR_USBID_PRODUCTID_SHIFT (16U) + +typedef struct _cmpa_cfg_info +{ + uint32_t bootCfg; /*!< [0x000-0x003] */ + uint32_t spiFlashCfg; /*!< [0x004-0x007] */ + struct + { + uint16_t vid; + uint16_t pid; + } usbId; /*!< [0x008-0x00b] */ + uint32_t sdioCfg; /*!< [0x00c-0x00f] */ + uint32_t dcfgPin; /*!< [0x010-0x013] */ + uint32_t dcfgDflt; /*!< [0x014-0x017] */ + uint32_t dapVendorUsage; /*!< [0x018-0x01b] */ + uint32_t secureBootCfg; /*!< [0x01c-0x01f] */ + uint32_t princeBaseAddr; /*!< [0x020-0x023] */ + uint32_t princeSr[3]; /*!< [0x024-0x02f] */ + uint8_t reserved0[32]; /*!< [0x030-0x04f] */ + uint32_t rotkh[8]; /*!< [0x050-0x06f] */ + uint8_t reserved1[368]; /*!< [0x070-0x1df] */ + uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */ +} cmpa_cfg_info_t; + +typedef struct _cmpa_key_store_header +{ + uint32_t header; + uint8_t reserved[4]; +} cmpa_key_store_header_t; + +#define FFR_SYSTEM_SPEED_CODE_MASK (0x3U) +#define FFR_SYSTEM_SPEED_CODE_SHIFT (0U) +#define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ (0x0U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_24MHZ (0x1U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_48MHZ (0x2U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_96MHZ (0x3U) + +#define FFR_PERIPHERALCFG_PERI_MASK (0x7FFFFFFFU) +#define FFR_PERIPHERALCFG_PERI_SHIFT (0U) +#define FFR_PERIPHERALCFG_COREEN_MASK (0x10000000U) +#define FFR_PERIPHERALCFG_COREEN_SHIFT (31U) + +typedef struct _nmpa_cfg_info +{ + uint16_t fro32kCfg; /*!< [0x000-0x001] */ + uint8_t reserved0[6]; /*!< [0x002-0x007] */ + uint8_t sysCfg; /*!< [0x008-0x008] */ + uint8_t reserved1[7]; /*!< [0x009-0x00f] */ + struct + { + uint32_t data; + uint32_t reserved[3]; + } GpoInitData[3]; /*!< [0x010-0x03f] */ + uint32_t GpoDataChecksum[4]; /*!< [0x040-0x04f] */ + uint32_t finalTestBatchId[4]; /*!< [0x050-0x05f] */ + uint32_t deviceType; /*!< [0x060-0x063] */ + uint32_t finalTestProgVersion; /*!< [0x064-0x067] */ + uint32_t finalTestDate; /*!< [0x068-0x06b] */ + uint32_t finalTestTime; /*!< [0x06c-0x06f] */ + uint32_t uuid[4]; /*!< [0x070-0x07f] */ + uint8_t reserved2[32]; /*!< [0x080-0x09f] */ + uint32_t peripheralCfg; /*!< [0x0a0-0x0a3] */ + uint32_t ramSizeCfg; /*!< [0x0a4-0x0a7] */ + uint32_t flashSizeCfg; /*!< [0x0a8-0x0ab] */ + uint8_t reserved3[36]; /*!< [0x0ac-0x0cf] */ + uint8_t fro1mCfg; /*!< [0x0d0-0x0d0] */ + uint8_t reserved4[15]; /*!< [0x0d1-0x0df] */ + uint32_t dcdc[4]; /*!< [0x0e0-0x0ef] */ + uint32_t bod; /*!< [0x0f0-0x0f3] */ + uint8_t reserved5[12]; /*!< [0x0f4-0x0ff] */ + uint8_t calcHashReserved[192]; /*!< [0x100-0x1bf] */ + uint8_t sha256[32]; /*!< [0x1c0-0x1df] */ + uint32_t ecidBackup[4]; /*!< [0x1e0-0x1ef] */ + uint32_t pageChecksum[4]; /*!< [0x1f0-0x1ff] */ +} nmpa_cfg_info_t; + +typedef struct _ffr_key_store +{ + uint8_t reserved[3][FLASH_FFR_MAX_PAGE_SIZE]; +} ffr_key_store_t; + +typedef enum _ffr_key_type +{ + kFFR_KeyTypeSbkek = 0x00U, + kFFR_KeyTypeUser = 0x01U, + kFFR_KeyTypeUds = 0x02U, + kFFR_KeyTypePrinceRegion0 = 0x03U, + kFFR_KeyTypePrinceRegion1 = 0x04U, + kFFR_KeyTypePrinceRegion2 = 0x05U, +} ffr_key_type_t; + +typedef enum _ffr_bank_type +{ + kFFR_BankTypeBank0_NMPA = 0x00U, + kFFR_BankTypeBank1_CMPA = 0x01U, + kFFR_BankTypeBank2_CFPA = 0x02U +} ffr_bank_type_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name FFR APIs + * @{ + */ + +/*! + * @brief Initializes the global FFR properties structure members. + * + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + */ +status_t FFR_Init(flash_config_t *config); + +/*! + * @brief Enable firewall for all flash banks. + * + * CFPA, CMPA, and NMPA flash areas region will be locked, After this function executed; + * Unless the board is reset again. + * + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success An invalid argument is provided. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + */ +status_t FFR_Lock_All(flash_config_t *config); + +/*! + * @brief APIs to access CFPA pages + * + * This routine will erase CFPA and program the CFPA page with passed data. + * + * @param config A pointer to the storage for the driver runtime state. + * @param page_data A pointer to the source buffer of data that is to be programmed + * into the CFPA. + * @param valid_len The length, given in bytes, to be programmed. + * + * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CFPA. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_FfrBankIsLocked The CFPA was locked. + * @retval #kStatus_FLASH_OutOfDateCfpaPage It is not newest CFPA page. + */ +status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + +/*! + * @brief APIs to access CFPA pages + * + * Generic read function, used by customer to read data stored in 'Customer In-field Page'. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read from 'Customer In-field Page'. + * @param offset An offset from the 'Customer In-field Page' start address. + * @param len The length, given in bytes, to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer In-field Page'. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + */ +status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief APIs to access CMPA pages + * + * This routine will erase "customer factory page" and program the page with passed data. + * If 'seal_part' parameter is TRUE then the routine will compute SHA256 hash of + * the page contents and then programs the pages. + * 1.During development customer code uses this API with 'seal_part' set to FALSE. + * 2.During manufacturing this parameter should be set to TRUE to seal the part + * from further modifications + * 3.This routine checks if the page is sealed or not. A page is said to be sealed if + * the SHA256 value in the page has non-zero value. On boot ROM locks the firewall for + * the region if hash is programmed anyways. So, write/erase commands will fail eventually. + * + * @param config A pointer to the storage for the driver runtime state. + * @param page_data A pointer to the source buffer of data that is to be programmed + * into the "customer factory page". + * @param seal_part Set fasle for During development customer code. + * + * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CMPA. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + */ +status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part); + +/*! + * @brief APIs to access CMPA page + * + * Read data stored in 'Customer Factory CFG Page'. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read + * from the Customer Factory CFG Page. + * @param offset Address offset relative to the CMPA area. + * @param len The length, given in bytes to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + */ +status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief APIs to access CMPA page + * + * 1.SW should use this API routine to get the UUID of the chip. + * 2.Calling routine should pass a pointer to buffer which can hold 128-bit value. + */ +status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid); + +/*! + * @brief This routine writes the 3 pages allocated for Key store data, + * + * 1.Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state. + * 2.Optional routines to set individual data members (activation code, key codes etc) to construct + * the key store structure in RAM before committing it to IFR/FFR. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pKeyStore A Pointer to the 3 pages allocated for Key store data. + * that will be written to 'customer factory page'. + * + * @retval #kStatus_FLASH_Success The key were programed successfully into FFR. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + */ +status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore); + +/*! + * @brief Get/Read Key store code routines + * + * 1. Calling code should pass buffer pointer which can hold activation code 1192 bytes. + * 2. Check if flash aperture is small or regular and read the data appropriately. + */ +status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode); + +/*! + * @brief Get/Read Key store code routines + * + * 1. Calling code should pass buffer pointer which can hold key code 52 bytes. + * 2. Check if flash aperture is small or regular and read the data appropriately. + * 3. keyIndex specifies which key code is read. + */ +status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); + +/*@}*/ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /*! __FSL_FLASH_FFR_H_ */ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iap_kbp.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iap_kbp.h new file mode 100644 index 000000000..f5c436ea0 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iap_kbp.h @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2020, Freescale Semiconductor, Inc. + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_IAP_KBP_H_ +#define _FSL_IAP_KBP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup kb_driver + * @{ + */ +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! + * @brief Details of the operation to be performed by the ROM. + * + * The #kRomAuthenticateImage operation requires the entire signed image to be + * available to the application. + */ +typedef enum _kb_operation +{ + kRomAuthenticateImage = 1, /*!< Authenticate a signed image.*/ + kRomLoadImage = 2, /*!< Load SB file.*/ + kRomOperationCount = 3, +} kb_operation_t; + +/*! + * @brief Security constraint flags, Security profile flags. + */ +enum _kb_security_profile +{ + kKbootMinRSA4096 = (1 << 16), +}; + +/*! + * @brief Memory region definition. + */ +typedef struct _kb_region +{ + uint32_t address; + uint32_t length; +} kb_region_t; + +/*! + * @brief User-provided options passed into kb_init(). + * + * The buffer field is a pointer to memory provided by the caller for use by + * Kboot during execution of the operation. Minimum size is the size of each + * certificate in the chain plus 432 bytes additional per certificate. + * + * The profile field is a mask that specifies which features are required in + * the SB file or image being processed. This includes the minimum AES and RSA + * key sizes. See the _kb_security_profile enum for profile mask constants. + * The image being loaded or authenticated must match the profile or an error will + * be returned. + * + * minBuildNumber is an optional field that can be used to prevent version + * rollback. The API will check the build number of the image, and if it is less + * than minBuildNumber will fail with an error. + * + * maxImageLength is used to verify the offsetToCertificateBlockHeaderInBytes + * value at the beginning of a signed image. It should be set to the length of + * the SB file. If verifying an image in flash, it can be set to the internal + * flash size or a large number like 0x10000000. + * + * userRHK can optionally be used by the user to override the RHK in IFR. If + * userRHK is not NULL, it points to a 32-byte array containing the SHA-256 of + * the root certificate's RSA public key. + * + * The regions field points to an array of memory regions that the SB file being + * loaded is allowed to access. If regions is NULL, then all memory is + * accessible by the SB file. This feature is required to prevent a malicious + * image from erasing good code or RAM contents while it is being loaded, only + * for us to find that the image is inauthentic when we hit the end of the + * section. + * + * overrideSBBootSectionID lets the caller override the default section of the + * SB file that is processed during a kKbootLoadSB operation. By default, + * the section specified in the firstBootableSectionID field of the SB header + * is loaded. If overrideSBBootSectionID is non-zero, then the section with + * the given ID will be loaded instead. + * + * The userSBKEK field lets a user provide their own AES-256 key for unwrapping + * keys in an SB file during the kKbootLoadSB operation. userSBKEK should point + * to a 32-byte AES-256 key. If userSBKEK is NULL then the IFR SBKEK will be used. + * After kb_init() returns, the caller should zero out the data pointed to by + * userSBKEK, as the API will have installed the key in the CAU3. + */ + +typedef struct _kb_load_sb +{ + uint32_t profile; + uint32_t minBuildNumber; + uint32_t overrideSBBootSectionID; + uint32_t *userSBKEK; + uint32_t regionCount; + const kb_region_t *regions; +} kb_load_sb_t; + +typedef struct _kb_authenticate +{ + uint32_t profile; + uint32_t minBuildNumber; + uint32_t maxImageLength; + uint32_t *userRHK; +} kb_authenticate_t; + +typedef struct _kb_options +{ + uint32_t version; /*!< Should be set to kKbootApiVersion.*/ + uint8_t *buffer; /*!< Caller-provided buffer used by Kboot.*/ + uint32_t bufferLength; + kb_operation_t op; + union + { + kb_authenticate_t authenticate; /*! Settings for kKbootAuthenticate operation.*/ + kb_load_sb_t loadSB; /*! Settings for kKbootLoadSB operation.*/ + }; +} kb_options_t; + +/*! + * @brief Interface to memory operations for one region of memory. + */ +typedef struct _memory_region_interface +{ + status_t (*init)(void); + status_t (*read)(uint32_t address, uint32_t length, uint8_t *buffer); + status_t (*write)(uint32_t address, uint32_t length, const uint8_t *buffer); + status_t (*fill)(uint32_t address, uint32_t length, uint32_t pattern); + status_t (*flush)(void); + status_t (*erase)(uint32_t address, uint32_t length); + status_t (*config)(uint32_t *buffer); + status_t (*erase_all)(void); +} memory_region_interface_t; + +/*! + * @brief Structure of a memory map entry. + */ +typedef struct _memory_map_entry +{ + uint32_t startAddress; + uint32_t endAddress; + uint32_t memoryProperty; + uint32_t memoryId; + const memory_region_interface_t *memoryInterface; +} memory_map_entry_t; + +typedef struct _kb_opaque_session_ref +{ + kb_options_t context; + bool cau3Initialized; + memory_map_entry_t *memoryMap; +} kb_session_ref_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize ROM API for a given operation. + * + * Inits the ROM API based on the options provided by the application in the second + * argument. Every call to rom_init() should be paired with a call to rom_deinit(). + */ +status_t kb_init(kb_session_ref_t **session, const kb_options_t *options); + +/*! + * @brief Cleans up the ROM API context. + * + * After this call, the context parameter can be reused for another operation + * by calling rom_init() again. + */ +status_t kb_deinit(kb_session_ref_t *session); + +/*! + * Perform the operation configured during init. + * + * This application must call this API repeatedly, passing in sequential chunks of + * data from the boot image (SB file) that is to be processed. The ROM will perform + * the selected operation on this data and return. The application may call this + * function with as much or as little data as it wishes, which can be used to select + * the granularity of time given to the application in between executing the operation. + * + * @param session Current ROM context pointer. + * @param data Buffer of boot image data provided to the ROM by the application. + * @param dataLength Length in bytes of the data in the buffer provided to the ROM. + * + * @retval kStatus_RomApiExecuteSuccess ROM successfully process the part of sb file/boot image. + * @retval kStatus_RomApiExecuteCompleted ROM successfully process the whole sb file/boot image. + * @retval kStatus_Fail An error occurred while executing the operation. + * @retval kStatus_RomApiNeedMoreData No error occurred, but the ROM needs more data to + * continue processing the boot image. + * @retval kStatus_RomApiBufferSizeNotEnough user buffer is not enough for + * use by Kboot during execution of the operation. + * @retval kStatus_RomApiBufferNotOkForArena user buffer does't meet the requirement + * of arena memory. + */ +status_t kb_execute(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength); + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* _FSL_IAP_KBP_H_ */ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iap_skboot_authenticate.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iap_skboot_authenticate.h new file mode 100644 index 000000000..0f8a21f9d --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iap_skboot_authenticate.h @@ -0,0 +1,73 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FSL_IAP_SKBOOT_AUTHENTICATE_H_ +#define _FSL_IAP_SKBOOT_AUTHENTICATE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup skboot_authenticate + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +typedef enum _skboot_status +{ + kStatus_SKBOOT_Success = 0x5ac3c35au, + kStatus_SKBOOT_Fail = 0xc35ac35au, + kStatus_SKBOOT_InvalidArgument = 0xc35a5ac3u, + kStatus_SKBOOT_KeyStoreMarkerInvalid = 0xc3c35a5au, + kStatus_SKBOOT_HashcryptFinishedWithStatusSuccess = 0xc15a5ac3, + kStatus_SKBOOT_HashcryptFinishedWithStatusFail = 0xc15a5acb, +} skboot_status_t; + +typedef enum _secure_bool +{ + kSECURE_TRUE = 0xc33cc33cU, + kSECURE_FALSE = 0x5aa55aa5U, + kSECURE_CALLPROTECT_SECURITY_FLAGS = 0xc33c5aa5U, + kSECURE_CALLPROTECT_IS_APP_READY = 0x5aa5c33cU, + kSECURE_TRACKER_VERIFIED = 0x55aacc33U, +} secure_bool_t; + +/******************************************************************************* + * Externs + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Authenticate entry function with ARENA allocator init + * + * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface + */ +skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified); + +/*! + * @brief Interface for image authentication API + */ +void HASH_IRQHandler(void); + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* _FSL_IAP_SKBOOT_AUTHENTICATE_H_ */ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iocon.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iocon.h new file mode 100644 index 000000000..221080fd6 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iocon.h @@ -0,0 +1,288 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_IOCON_H_ +#define _FSL_IOCON_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_iocon + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOCON driver version 2.1.1. */ +#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*@}*/ + +/** + * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format + */ +typedef struct _iocon_group +{ + uint32_t port : 8; /* Pin port */ + uint32_t pin : 8; /* Pin number */ + uint32_t ionumber : 8; /* IO number */ + uint32_t modefunc : 16; /* Function and mode */ +} iocon_group_t; + +/** + * @brief IOCON function and mode selection definitions + * @note See the User Manual for specific modes and functions supported by the various pins. + */ +#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) +#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ +#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ +#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ +#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ +#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ +#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ +#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ +#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ +#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ +#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ +#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ +#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ +#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ +#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ +#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ +#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ +#if defined(IOCON_PIO_MODE_SHIFT) +#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ +#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ +#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ +#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ +#endif + +#if defined(IOCON_PIO_I2CSLEW_SHIFT) +#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ +#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ +#endif + +#if defined(IOCON_PIO_EGP_SHIFT) +#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ +#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ +#endif + +#if defined(IOCON_PIO_SLEW_SHIFT) +#define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ +#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ +#endif + +#if defined(IOCON_PIO_INVERT_SHIFT) +#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */ +#endif + +#if defined(IOCON_PIO_DIGIMODE_SHIFT) +#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */ +#define IOCON_DIGITAL_EN \ + (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */ +#endif + +#if defined(IOCON_PIO_FILTEROFF_SHIFT) +#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ +#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ +#endif + +#if defined(IOCON_PIO_I2CDRIVE_SHIFT) +#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ +#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ +#endif + +#if defined(IOCON_PIO_OD_SHIFT) +#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */ +#endif + +#if defined(IOCON_PIO_I2CFILTER_SHIFT) +#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ +#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */ +#endif + +#if defined(IOCON_PIO_ASW_SHIFT) +#define IOCON_AWS_EN (0x1 << IOCON_PIO_ASW_SHIFT) /*!< Enables analog switch function */ +#endif + +#if defined(IOCON_PIO_SSEL_SHIFT) +#define IOCON_SSEL_3V3 (0x0 << IOCON_PIO_SSEL_SHIFT) /*!< 3V3 signaling in I2C mode */ +#define IOCON_SSEL_1V8 (0x1 << IOCON_PIO_SSEL_SHIFT) /*!< 1V8 signaling in I2C mode */ +#endif + +#if defined(IOCON_PIO_ECS_SHIFT) +#define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */ +#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */ +#endif + +#if defined(IOCON_PIO_S_MODE_SHIFT) +#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ +#define IOCON_S_MODE_1CLK \ + (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE_2CLK \ + (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE_3CLK \ + (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ +#endif + +#if defined(IOCON_PIO_CLK_DIV_SHIFT) +#define IOCON_CLKDIV(div) \ + ((div) \ + << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ +#endif + +#else +#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ +#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ +#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ +#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ +#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ +#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ +#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ +#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ + +#if defined(IOCON_PIO_MODE_SHIFT) +#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ +#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ +#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ +#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ +#endif + +#if defined(IOCON_PIO_I2CSLEW_SHIFT) +#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ +#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ +#endif + +#if defined(IOCON_PIO_EGP_SHIFT) +#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ +#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ +#endif + +#if defined(IOCON_PIO_INVERT_SHIFT) +#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */ +#endif + +#if defined(IOCON_PIO_DIGIMODE_SHIFT) +#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */ +#define IOCON_DIGITAL_EN \ + (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */ +#endif + +#if defined(IOCON_PIO_FILTEROFF_SHIFT) +#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ +#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ +#endif + +#if defined(IOCON_PIO_I2CDRIVE_SHIFT) +#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ +#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ +#endif + +#if defined(IOCON_PIO_OD_SHIFT) +#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */ +#endif + +#if defined(IOCON_PIO_I2CFILTER_SHIFT) +#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ +#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled */ +#endif + +#if defined(IOCON_PIO_S_MODE_SHIFT) +#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ +#define IOCON_S_MODE_1CLK \ + (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE_2CLK \ + (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE_3CLK \ + (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ +#endif + +#if defined(IOCON_PIO_CLK_DIV_SHIFT) +#define IOCON_CLKDIV(div) \ + ((div) \ + << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ +#endif + +#endif +#if defined(__cplusplus) +extern "C" { +#endif + +#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) +/** + * @brief Sets I/O Control pin mux + * @param base : The base of IOCON peripheral on the chip + * @param ionumber : GPIO number to mux + * @param modefunc : OR'ed values of type IOCON_* + * @return Nothing + */ +__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc) +{ + base->PIO[ionumber] = modefunc; +} +#else +/** + * @brief Sets I/O Control pin mux + * @param base : The base of IOCON peripheral on the chip + * @param port : GPIO port to mux + * @param pin : GPIO pin to mux + * @param modefunc : OR'ed values of type IOCON_* + * @return Nothing + */ +__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc) +{ + base->PIO[port][pin] = modefunc; +} +#endif + +/** + * @brief Set all I/O Control pin muxing + * @param base : The base of IOCON peripheral on the chip + * @param pinArray : Pointer to array of pin mux selections + * @param arrayLength : Number of entries in pinArray + * @return Nothing + */ +__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength) +{ + uint32_t i; + + for (i = 0; i < arrayLength; i++) + { +#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) + IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc); +#else + IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc); +#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */ + } +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_IOCON_H_ */ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_power.c b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_power.c new file mode 100644 index 000000000..a0b833175 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_power.c @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_common.h" +#include "fsl_power.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.power" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Empty file since implementation is in header file and power library */ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_power.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_power.h new file mode 100644 index 000000000..64fd83543 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_power.h @@ -0,0 +1,562 @@ +/* + * Copyright 2017, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_POWER_H_ +#define _FSL_POWER_H_ + +#include "fsl_common.h" +#include "fsl_device_registers.h" +#include + +/*! + * @addtogroup power + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief power driver version 1.0.0. */ +#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*@}*/ + +/* Power mode configuration API parameter */ +typedef enum _power_mode_config +{ + kPmu_Sleep = 0U, + kPmu_Deep_Sleep = 1U, + kPmu_PowerDown = 2U, + kPmu_Deep_PowerDown = 3U, +} power_mode_cfg_t; + +/** + * @brief Analog components power modes control during low power modes + */ +typedef enum pd_bits +{ + kPDRUNCFG_PD_DCDC = (1UL << 0), + kPDRUNCFG_PD_BIAS = (1UL << 1), + kPDRUNCFG_PD_BODCORE = (1UL << 2), + kPDRUNCFG_PD_BODVBAT = (1UL << 3), + kPDRUNCFG_PD_FRO1M = (1UL << 4), + kPDRUNCFG_PD_FRO192M = (1UL << 5), + kPDRUNCFG_PD_FRO32K = (1UL << 6), + kPDRUNCFG_PD_XTAL32K = (1UL << 7), + kPDRUNCFG_PD_XTAL32M = (1UL << 8), + kPDRUNCFG_PD_PLL0 = (1UL << 9), + kPDRUNCFG_PD_PLL1 = (1UL << 10), + kPDRUNCFG_PD_USB0_PHY = (1UL << 11), + kPDRUNCFG_PD_USB1_PHY = (1UL << 12), + kPDRUNCFG_PD_COMP = (1UL << 13), + kPDRUNCFG_PD_TEMPSENS = (1UL << 14), + kPDRUNCFG_PD_GPADC = (1UL << 15), + kPDRUNCFG_PD_LDOMEM = (1UL << 16), + kPDRUNCFG_PD_LDODEEPSLEEP = (1UL << 17), + kPDRUNCFG_PD_LDOUSBHS = (1UL << 18), + kPDRUNCFG_PD_LDOGPADC = (1UL << 19), + kPDRUNCFG_PD_LDOXO32M = (1UL << 20), + kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21), + kPDRUNCFG_PD_RNG = (1UL << 22), + kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23), + kPDRUNCFG_PD_ROM = (1UL << 24), + /* + This enum member has no practical meaning,it is used to avoid MISRA issue, + user should not trying to use it. + */ + kPDRUNCFG_ForceUnsigned = 0x80000000U, +} pd_bit_t; + +/*! @brief BOD VBAT level */ +typedef enum _power_bod_vbat_level +{ + kPOWER_BodVbatLevel1000mv = 0, /*!< Brown out detector VBAT level 1V */ + kPOWER_BodVbatLevel1100mv = 1, /*!< Brown out detector VBAT level 1.1V */ + kPOWER_BodVbatLevel1200mv = 2, /*!< Brown out detector VBAT level 1.2V */ + kPOWER_BodVbatLevel1300mv = 3, /*!< Brown out detector VBAT level 1.3V */ + kPOWER_BodVbatLevel1400mv = 4, /*!< Brown out detector VBAT level 1.4V */ + kPOWER_BodVbatLevel1500mv = 5, /*!< Brown out detector VBAT level 1.5V */ + kPOWER_BodVbatLevel1600mv = 6, /*!< Brown out detector VBAT level 1.6V */ + kPOWER_BodVbatLevel1650mv = 7, /*!< Brown out detector VBAT level 1.65V */ + kPOWER_BodVbatLevel1700mv = 8, /*!< Brown out detector VBAT level 1.7V */ + kPOWER_BodVbatLevel1750mv = 9, /*!< Brown out detector VBAT level 1.75V */ + kPOWER_BodVbatLevel1800mv = 10, /*!< Brown out detector VBAT level 1.8V */ + kPOWER_BodVbatLevel1900mv = 11, /*!< Brown out detector VBAT level 1.9V */ + kPOWER_BodVbatLevel2000mv = 12, /*!< Brown out detector VBAT level 2V */ + kPOWER_BodVbatLevel2100mv = 13, /*!< Brown out detector VBAT level 2.1V */ + kPOWER_BodVbatLevel2200mv = 14, /*!< Brown out detector VBAT level 2.2V */ + kPOWER_BodVbatLevel2300mv = 15, /*!< Brown out detector VBAT level 2.3V */ + kPOWER_BodVbatLevel2400mv = 16, /*!< Brown out detector VBAT level 2.4V */ + kPOWER_BodVbatLevel2500mv = 17, /*!< Brown out detector VBAT level 2.5V */ + kPOWER_BodVbatLevel2600mv = 18, /*!< Brown out detector VBAT level 2.6V */ + kPOWER_BodVbatLevel2700mv = 19, /*!< Brown out detector VBAT level 2.7V */ + kPOWER_BodVbatLevel2806mv = 20, /*!< Brown out detector VBAT level 2.806V */ + kPOWER_BodVbatLevel2900mv = 21, /*!< Brown out detector VBAT level 2.9V */ + kPOWER_BodVbatLevel3000mv = 22, /*!< Brown out detector VBAT level 3.0V */ + kPOWER_BodVbatLevel3100mv = 23, /*!< Brown out detector VBAT level 3.1V */ + kPOWER_BodVbatLevel3200mv = 24, /*!< Brown out detector VBAT level 3.2V */ + kPOWER_BodVbatLevel3300mv = 25, /*!< Brown out detector VBAT level 3.3V */ +} power_bod_vbat_level_t; + +/*! @brief BOD Hysteresis control */ +typedef enum _power_bod_hyst +{ + kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */ + kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */ + kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */ + kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */ +} power_bod_hyst_t; + +/*! @brief BOD core level */ +typedef enum _power_bod_core_level +{ + kPOWER_BodCoreLevel600mv = 0, /*!< Brown out detector core level 600mV */ + kPOWER_BodCoreLevel650mv = 1, /*!< Brown out detector core level 650mV */ + kPOWER_BodCoreLevel700mv = 2, /*!< Brown out detector core level 700mV */ + kPOWER_BodCoreLevel750mv = 3, /*!< Brown out detector core level 750mV */ + kPOWER_BodCoreLevel800mv = 4, /*!< Brown out detector core level 800mV */ + kPOWER_BodCoreLevel850mv = 5, /*!< Brown out detector core level 850mV */ + kPOWER_BodCoreLevel900mv = 6, /*!< Brown out detector core level 900mV */ + kPOWER_BodCoreLevel950mv = 7, /*!< Brown out detector core level 950mV */ +} power_bod_core_level_t; + +/** + * @brief SRAM instances retention control during low power modes + */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 \ + (1UL << 0) /*!< Enable SRAMX_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 \ + (1UL << 1) /*!< Enable SRAMX_1 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 \ + (1UL << 2) /*!< Enable SRAMX_2 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 \ + (1UL << 3) /*!< Enable SRAMX_3 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM00 \ + (1UL << 4) /*!< Enable SRAM0_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM01 \ + (1UL << 5) /*!< Enable SRAM0_1 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM10 \ + (1UL << 6) /*!< Enable SRAM1_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM20 \ + (1UL << 7) /*!< Enable SRAM2_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM30 \ + (1UL << 8) /*!< Enable SRAM3_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM31 \ + (1UL << 9) /*!< Enable SRAM3_1 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM40 \ + (1UL << 10) /*!< Enable SRAM4_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM41 \ + (1UL << 11) /*!< Enable SRAM4_1 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM42 \ + (1UL << 12) /*!< Enable SRAM4_2 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM43 \ + (1UL << 13) /*!< Enable SRAM4_3 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_USB_HS \ + (1UL << 14) /*!< Enable SRAM USB HS retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_PUF \ + (1UL << 15) /*!< Enable SRAM PUFF retention when entering in Low power modes */ + +/** + * @brief Low Power Modes Wake up sources + */ +#define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/ +#define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */ +#define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */ +#define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */ +#define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */ +#define WAKEUP_ACMP_CAPT (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +// reserved (1ULL << 25) +// reserved (1ULL << 26) +#define WAKEUP_USB0_NEEDCLK (1ULL << 27) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_USB0 (1ULL << 28) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ +#define WAKEUP_EZH_ARCH_B (1ULL << 30) /*!< [SLEEP, ] */ +#define WAKEUP_WAKEUP_MAILBOX (1ULL << 31) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ +// reserved (1ULL << 39) +// reserved (1ULL << 40) +// reserved (1ULL << 41) +#define WAKEUP_SDIO (1ULL << 42) /*!< [SLEEP, ] */ +// reserved (1ULL << 43) +// reserved (1ULL << 44) +// reserved (1ULL << 45) +// reserved (1ULL << 46) +#define WAKEUP_USB1 (1ULL << 47) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_USB1_NEEDCLK (1ULL << 48) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */ +#define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SEC_VIO (1ULL << 53) +#define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */ +#define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */ +#define WAKEUP_PUFF (1ULL << 56) /*!< [SLEEP, ] */ +#define WAKEUP_PQ (1ULL << 57) /*!< [SLEEP, ] */ +#define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */ +// reserved WAKEUP_PVTVF0_AMBER (1ULL << 60) +// reserved WAKEUP_PVTVF0_RED (1ULL << 61) +// reserved WAKEUP_PVTVF1_AMBER (1ULL << 62) +#define WAKEUP_ALLWAKEUPIOS (1ULL << 63) /*!< [ , DEEP POWER DOWN] */ + +/** + * @brief Sleep Postpone + */ +#define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */ +#define LOWPOWER_HWWAKE_PERIPHERALS \ + (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause \ + peripheral clocking to wake up temporarily while the related status is asserted */ +#define LOWPOWER_HWWAKE_SDMA0 \ + (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA \ + completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ +#define LOWPOWER_HWWAKE_SDMA1 \ + (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA \ + completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ +#define LOWPOWER_HWWAKE_ENABLE_FRO192M \ + (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of \ + LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set */ + +#define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */ +#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */ +/** + * @brief Wake up I/O sources + */ +#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */ +#define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */ +#define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */ +#define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */ + +#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */ +#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */ +#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */ +#define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */ + +#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX 8 /*!< Wake-up I/O 0 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX 9 /*!< Wake-up I/O 1 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX 10 /*!< Wake-up I/O 2 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX 11 /*!< Wake-up I/O 3 pull-up/down configuration index */ + +#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down mask */ + +#define LOWPOWER_WAKEUPIO_PULLDOWN 0 /*!< Select pull-down */ +#define LOWPOWER_WAKEUPIO_PULLUP 1 /*!< Select pull-up */ + +#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX \ + 12 /*!< Wake-up I/O 0 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX \ + 13 /*!< Wake-up I/O 1 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX \ + 14 /*!< Wake-up I/O 2 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX \ + 15 /*!< Wake-up I/O 3 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down disable/enable mask */ +#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down disable/enable mask */ +#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down disable/enable mask */ +#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down disable/enable mask */ + +#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX \ + (16) /*!< Wake-up I/O 0 use external pull-up/down disable/enable control index*/ +#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX \ + (17) /*!< Wake-up I/O 1 use external pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX \ + (18) /*!< Wake-up I/O 2 use external pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX \ + (19) /*!< Wake-up I/O 3 use external pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 use external pull-up/down \ + disable/enable mask, 0: disable, 1: enable */ +#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 use external pull-up/down \ + disable/enable mask, 0: disable, 1: enable */ +#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 use external pull-up/down \ + disable/enable mask, 0: disable, 1: enable */ +#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 use external pull-up/down \ + disable/enable mask, 0: disable, 1: enable */ + +#ifdef __cplusplus +extern "C" { +#endif +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral + * + * @param en peripheral for which to enable the PDRUNCFG bit + * @return none + */ +static inline void POWER_EnablePD(pd_bit_t en) +{ + /* PDRUNCFGSET */ + PMC->PDRUNCFGSET0 = (uint32_t)en; +} + +/*! + * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral + * + * @param en peripheral for which to disable the PDRUNCFG bit + * @return none + */ +static inline void POWER_DisablePD(pd_bit_t en) +{ + /* PDRUNCFGCLR */ + PMC->PDRUNCFGCLR0 = (uint32_t)en; +} + +/*! + * @brief set BOD VBAT level. + * + * @param level BOD detect level + * @param hyst BoD Hysteresis control + * @param enBodVbatReset VBAT brown out detect reset + */ +static inline void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset) +{ + PMC->BODVBAT = (PMC->BODVBAT & (~(PMC_BODVBAT_TRIGLVL_MASK | PMC_BODVBAT_HYST_MASK))) | PMC_BODVBAT_TRIGLVL(level) | + PMC_BODVBAT_HYST(hyst); + PMC->RESETCTRL = + (PMC->RESETCTRL & (~PMC_RESETCTRL_BODVBATRESETENABLE_MASK)) | PMC_RESETCTRL_BODVBATRESETENABLE(enBodVbatReset); +} + +#if defined(PMC_BODCORE_TRIGLVL_MASK) +/*! + * @brief set BOD core level. + * + * @param level BOD detect level + * @param hyst BoD Hysteresis control + * @param enBodCoreReset core brown out detect reset + */ +static inline void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset) +{ + PMC->BODCORE = (PMC->BODCORE & (~(PMC_BODCORE_TRIGLVL_MASK | PMC_BODCORE_HYST_MASK))) | PMC_BODCORE_TRIGLVL(level) | + PMC_BODCORE_HYST(hyst); + PMC->RESETCTRL = + (PMC->RESETCTRL & (~PMC_RESETCTRL_BODCORERESETENABLE_MASK)) | PMC_RESETCTRL_BODCORERESETENABLE(enBodCoreReset); +} +#endif + +/*! + * @brief API to enable deep sleep bit in the ARM Core. + * + * @return none + */ +static inline void POWER_EnableDeepSleep(void) +{ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; +} + +/*! + * @brief API to disable deep sleep bit in the ARM Core. + * + * @return none + */ +static inline void POWER_DisableDeepSleep(void) +{ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; +} + +/** + * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event + * This MUST BE EXECUTED outside the Flash: + * either from ROM or from SRAM. The rest could stay in Flash. But, for consistency, it is + * preferable to have all functions defined in this file implemented in ROM. + * + * @return Nothing + */ +void POWER_CycleCpuAndFlash(void); + +/** + * @brief Configures and enters in DEEP-SLEEP low power mode + * @param exclude_from_pd: + * @param sram_retention_ctrl: + * @param wakeup_interrupts: + * @param hardware_wake_ctrl: + + * @return Nothing + * + * !!! IMPORTANT NOTES : + 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. + * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in + case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). + * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be + restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip + reset) reset) + */ +void POWER_EnterDeepSleep(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t hardware_wake_ctrl); + +/** + * @brief Configures and enters in POWERDOWN low power mode + * @param exclude_from_pd: + * @param sram_retention_ctrl: + * @param wakeup_interrupts: + * @param cpu_retention_ctrl: 0 = CPU retention is disable / 1 = CPU retention is enabled, all other values are + RESERVED. + + * @return Nothing + * + * !!! IMPORTANT NOTES : + 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. + * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in + case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). + * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be + restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance + containing the stack used to call this function WILL BE preserved during low power (via parameter + "sram_retention_ctrl") + * 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip + reset) reset) + */ + +void POWER_EnterPowerDown(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t cpu_retention_ctrl); + +/** + * @brief Configures and enters in DEEPPOWERDOWN low power mode + * @param exclude_from_pd: + * @param sram_retention_ctrl: + * @param wakeup_interrupts: + * @param wakeup_io_ctrl: + + * @return Nothing + * + * !!! IMPORTANT NOTES : + 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. + * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back if + DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be + restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip + reset) + */ +void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t wakeup_io_ctrl); + +/** + * @brief Configures and enters in SLEEP low power mode + * @param : + * @return Nothing + */ +void POWER_EnterSleep(void); + +/*! + * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency. + * + * @param system_freq_hz - The desired frequency (in Hertz) at which the part would like to operate, + * note that the voltage and flash wait states should be set before changing frequency + * @return none + */ +void POWER_SetVoltageForFreq(uint32_t system_freq_hz); + +/*! + * @brief Power Library API to return the library version. + * + * @return version number of the power library + */ +uint32_t POWER_GetLibVersion(void); + +/** + * @brief Sets board-specific trim values for 16MHz XTAL + * @param pi32_16MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 + * @param pi32_16MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + * becomes 120 + * @param pi32_16MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + * becomes 120 + * @return none + * @note Following default Values can be used: + * pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 + * pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20 + * pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 + */ +extern void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, + int32_t pi32_16MfXtalPPcbParCappF_x100, + int32_t pi32_16MfXtalNPcbParCappF_x100); +/** + * @brief Sets board-specific trim values for 32kHz XTAL + * @param pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 + * @param pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + becomes 120 + * @param pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + becomes 120 + + * @return none + * @note Following default Values can be used: + * pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 + * pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40 + * pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 + */ +extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, + int32_t pi32_32kfXtalPPcbParCappF_x100, + int32_t pi32_32kfXtalNPcbParCappF_x100); +/** + * @brief Enables and sets LDO for 16MHz XTAL + * + * @return none + */ +extern void POWER_SetXtal16mhzLdo(void); + +/** + * @brief Set up 16-MHz XTAL Trimmings + * @param amp Amplitude + * @param gm Transconductance + * @return none + */ +extern void POWER_SetXtal16mhzTrim(uint32_t amp, uint32_t gm); +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _FSL_POWER_H_ */ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_reset.c b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_reset.c new file mode 100644 index 000000000..4326e0dae --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_reset.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_reset.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.reset" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/*! + * brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1UL << bitPos; + + assert(bitPos < 32u); + + /* reset register is in SYSCON */ + /* set bit */ + SYSCON->PRESETCTRLSET[regIndex] = bitMask; + /* wait until it reads 0b1 */ + while (0u == (SYSCON->PRESETCTRLX[regIndex] & bitMask)) + { + } +} + +/*! + * brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1UL << bitPos; + + assert(bitPos < 32u); + + /* reset register is in SYSCON */ + + /* clear bit */ + SYSCON->PRESETCTRLCLR[regIndex] = bitMask; + /* wait until it reads 0b0 */ + while (bitMask == (SYSCON->PRESETCTRLX[regIndex] & bitMask)) + { + } +} + +/*! + * brief Reset peripheral module. + * + * Reset peripheral module. + * + * param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral) +{ + RESET_SetPeripheralReset(peripheral); + RESET_ClearPeripheralReset(peripheral); +} + +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_reset.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_reset.h new file mode 100644 index 000000000..200a0f42c --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_reset.h @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_RESET_H_ +#define _FSL_RESET_H_ + +#include +#include +#include +#include +#include "fsl_device_registers.h" + +/*! + * @addtogroup reset + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief reset driver version 2.0.2. */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! + * @brief Enumeration for peripheral reset control bits + * + * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers + */ +typedef enum _SYSCON_RSTn +{ + kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */ + kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */ + kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */ + kSRAM3_RST_SHIFT_RSTn = 0 | 5U, /**< SRAM3 reset control */ + kSRAM4_RST_SHIFT_RSTn = 0 | 6U, /**< SRAM4 reset control */ + kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ + kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ + kSPIFI_RST_SHIFT_RSTn = 0 | 10U, /**< SPIFI reset control */ + kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */ + kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ + kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ + kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ + kGPIO2_RST_SHIFT_RSTn = 0 | 16U, /**< GPIO2 reset control */ + kGPIO3_RST_SHIFT_RSTn = 0 | 17U, /**< GPIO3 reset control */ + kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ + kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ + kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ + kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ + kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ + kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */ + kMAILBOX_RST_SHIFT_RSTn = 0 | 26U, /**< Mailbox reset control */ + kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ + + kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ + kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */ + kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ + kSCTIPU_RST_SHIFT_RSTn = 65536 | 6U, /**< SCTIPU reset control */ + kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ + kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ + kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ + kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ + kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ + kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ + kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ + kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ + kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ + kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */ + kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0 Device reset control */ + kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */ + kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */ + kPVT_RST_SHIFT_RSTn = 65536 | 28U, /**< PVT reset control */ + kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */ + kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */ + + kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */ + kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */ + kSDIO_RST_SHIFT_RSTn = 131072 | 3U, /**< SDIO reset control */ + kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USBHS Host reset control */ + kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USBHS Device reset control */ + kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB RAM reset control */ + kUSB1_RST_SHIFT_RSTn = 131072 | 7U, /**< USBHS reset control */ + kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */ + kGPIO4_RST_SHIFT_RSTn = 131072 | 9U, /**< GPIO4 reset control */ + kGPIO5_RST_SHIFT_RSTn = 131072 | 10U, /**< GPIO5 reset control */ + kAES_RST_SHIFT_RSTn = 131072 | 11U, /**< AES reset control */ + kOTP_RST_SHIFT_RSTn = 131072 | 12U, /**< OTP reset control */ + kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */ + kMUX1_RST_SHIFT_RSTn = 131072 | 14U, /**< Input mux1 reset control */ + kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */ + kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */ + kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */ + kPOWERQUAD_RST_SHIFT_RSTn = 131072 | 19U, /**< PowerQuad reset control */ + kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */ + kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */ + kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */ + kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */ + kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */ + kCAP0_RST_SHIFT_RSTn = 131072 | 25U, /**< CASPER reset control */ + kOSTIMER1_RST_SHIFT_RSTn = 131072 | 26U, /**< OSTIMER1 reset control */ + kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */ + kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */ + kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */ + kGPIOSECINT_RST_SHIFT_RSTn = 131072 | 30U, /**< GPIO Secure int reset control */ +} SYSCON_RSTn_t; + +/** Array initializers with peripheral reset bits **/ +#define ADC_RSTS \ + { \ + kADC0_RST_SHIFT_RSTn \ + } /* Reset bits for ADC peripheral */ +#define AES_RSTS \ + { \ + kAES_RST_SHIFT_RSTn \ + } /* Reset bits for AES peripheral */ +#define CRC_RSTS \ + { \ + kCRC_RST_SHIFT_RSTn \ + } /* Reset bits for CRC peripheral */ +#define CTIMER_RSTS \ + { \ + kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \ + kCTIMER4_RST_SHIFT_RSTn \ + } /* Reset bits for CTIMER peripheral */ +#define DMA_RSTS_N \ + { \ + kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \ + } /* Reset bits for DMA peripheral */ + +#define FLEXCOMM_RSTS \ + { \ + kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ + kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kHSLSPI_RST_SHIFT_RSTn \ + } /* Reset bits for FLEXCOMM peripheral */ +#define GINT_RSTS \ + { \ + kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ + } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ +#define GPIO_RSTS_N \ + { \ + kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \ + kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn \ + } /* Reset bits for GPIO peripheral */ +#define INPUTMUX_RSTS \ + { \ + kMUX0_RST_SHIFT_RSTn, kMUX1_RST_SHIFT_RSTn \ + } /* Reset bits for INPUTMUX peripheral */ +#define IOCON_RSTS \ + { \ + kIOCON_RST_SHIFT_RSTn \ + } /* Reset bits for IOCON peripheral */ +#define FLASH_RSTS \ + { \ + kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ + } /* Reset bits for Flash peripheral */ +#define MRT_RSTS \ + { \ + kMRT_RST_SHIFT_RSTn \ + } /* Reset bits for MRT peripheral */ +#define OTP_RSTS \ + { \ + kOTP_RST_SHIFT_RSTn \ + } /* Reset bits for OTP peripheral */ +#define PINT_RSTS \ + { \ + kPINT_RST_SHIFT_RSTn \ + } /* Reset bits for PINT peripheral */ +#define RNG_RSTS \ + { \ + kRNG_RST_SHIFT_RSTn \ + } /* Reset bits for RNG peripheral */ +#define SDIO_RST \ + { \ + kSDIO_RST_SHIFT_RSTn \ + } /* Reset bits for SDIO peripheral */ +#define SCT_RSTS \ + { \ + kSCT0_RST_SHIFT_RSTn \ + } /* Reset bits for SCT peripheral */ +#define SPIFI_RSTS \ + { \ + kSPIFI_RST_SHIFT_RSTn \ + } /* Reset bits for SPIFI peripheral */ +#define USB0D_RST \ + { \ + kUSB0D_RST_SHIFT_RSTn \ + } /* Reset bits for USB0D peripheral */ +#define USB0HMR_RST \ + { \ + kUSB0HMR_RST_SHIFT_RSTn \ + } /* Reset bits for USB0HMR peripheral */ +#define USB0HSL_RST \ + { \ + kUSB0HSL_RST_SHIFT_RSTn \ + } /* Reset bits for USB0HSL peripheral */ +#define USB1H_RST \ + { \ + kUSB1H_RST_SHIFT_RSTn \ + } /* Reset bits for USB1H peripheral */ +#define USB1D_RST \ + { \ + kUSB1D_RST_SHIFT_RSTn \ + } /* Reset bits for USB1D peripheral */ +#define USB1RAM_RST \ + { \ + kUSB1RAM_RST_SHIFT_RSTn \ + } /* Reset bits for USB1RAM peripheral */ +#define UTICK_RSTS \ + { \ + kUTICK_RST_SHIFT_RSTn \ + } /* Reset bits for UTICK peripheral */ +#define WWDT_RSTS \ + { \ + kWWDT_RST_SHIFT_RSTn \ + } /* Reset bits for WWDT peripheral */ +#define CAPT_RSTS_N \ + { \ + kCAP0_RST_SHIFT_RSTn \ + } /* Reset bits for CAPT peripheral */ +#define PLU_RSTS_N \ + { \ + kPLULUT_RST_SHIFT_RSTn \ + } /* Reset bits for PLU peripheral */ +#define OSTIMER_RSTS \ + { \ + kOSTIMER0_RST_SHIFT_RSTn \ + } /* Reset bits for OSTIMER peripheral */ +typedef SYSCON_RSTn_t reset_ip_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Reset peripheral module. + * + * Reset peripheral module. + * + * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_RESET_H_ */ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart.c b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart.c new file mode 100644 index 000000000..94daa9af3 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart.c @@ -0,0 +1,1099 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_usart.h" +#include "fsl_device_registers.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart" +#endif + +/*! + * @brief Used for conversion from `flexcomm_usart_irq_handler_t` to `flexcomm_irq_handler_t` + */ +typedef union usart_to_flexcomm +{ + flexcomm_usart_irq_handler_t usart_master_handler; + flexcomm_irq_handler_t flexcomm_handler; +} usart_to_flexcomm_t; + +enum +{ + kUSART_TxIdle, /* TX idle. */ + kUSART_TxBusy, /* TX busy. */ + kUSART_RxIdle, /* RX idle. */ + kUSART_RxBusy /* RX busy. */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief IRQ name array */ +static const IRQn_Type s_usartIRQ[] = USART_IRQS; + +/*! @brief Array to map USART instance number to base address. */ +static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Get the index corresponding to the USART */ +/*! brief Returns instance number for USART peripheral base address. */ +uint32_t USART_GetInstance(USART_Type *base) +{ + uint32_t i; + + for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT; i++) + { + if ((uint32_t)base == s_usartBaseAddrs[i]) + { + break; + } + } + + assert(i < FSL_FEATURE_SOC_USART_COUNT); + return i; +} + +/*! + * brief Get the length of received data in RX ring buffer. + * + * param handle USART handle pointer. + * return Length of received data in RX ring buffer. + */ +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) +{ + size_t size; + + /* Check arguments */ + assert(NULL != handle); + uint16_t rxRingBufferHead = handle->rxRingBufferHead; + uint16_t rxRingBufferTail = handle->rxRingBufferTail; + + if (rxRingBufferTail > rxRingBufferHead) + { + size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail; + } + else + { + size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail; + } + return size; +} + +static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle) +{ + bool full; + + /* Check arguments */ + assert(NULL != handle); + + if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + return full; +} + +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific USART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize size of the ring buffer. + */ +void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) +{ + /* Check arguments */ + assert(NULL != base); + assert(NULL != handle); + assert(NULL != ringBuffer); + + /* Setup the ringbuffer address */ + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + /* ring buffer is ready we can start receiving data */ + base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +} + +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) +{ + /* Check arguments */ + assert(NULL != base); + assert(NULL != handle); + + if (handle->rxState == (uint8_t)kUSART_RxIdle) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK; + } + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +/*! + * brief Initializes a USART instance with user configuration structure and peripheral clock. + * + * This function configures the USART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the USART_GetDefaultConfig() function. + * Example below shows how to use this API to configure USART. + * code + * usart_config_t usartConfig; + * usartConfig.baudRate_Bps = 115200U; + * usartConfig.parityMode = kUSART_ParityDisabled; + * usartConfig.stopBitCount = kUSART_OneStopBit; + * USART_Init(USART1, &usartConfig, 20000000U); + * endcode + * + * param base USART peripheral base address. + * param config Pointer to user-defined configuration structure. + * param srcClock_Hz USART clock source frequency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_InvalidArgument USART base address is not valid + * retval kStatus_Success Status USART initialize succeed + */ +status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz) +{ + int result; + + /* check arguments */ + assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); + if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* initialize flexcomm to USART mode */ + result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART); + if (kStatus_Success != result) + { + return result; + } + + if (config->enableTx) + { + /* empty and enable txFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK; + /* setup trigger level */ + base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK); + base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark); + /* enable trigger interrupt */ + base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK; + } + + /* empty and enable rxFIFO */ + if (config->enableRx) + { + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK; + /* setup trigger level */ + base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK); + base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark); + /* enable trigger interrupt */ + base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK; + } + /* setup configuration and enable USART */ + base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | + USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | + USART_CFG_SYNCEN((uint32_t)config->syncMode >> 1) | USART_CFG_SYNCMST((uint8_t)config->syncMode) | + USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_MODE32K(config->enableMode32k) | + USART_CFG_ENABLE_MASK; + + /* Setup baudrate */ + if (config->enableMode32k) + { + if ((9600U % config->baudRate_Bps) == 0U) + { + base->BRG = 9600U / config->baudRate_Bps; + } + else + { + return kStatus_USART_BaudrateNotSupport; + } + } + else + { + result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } + } + /* Setting continuous Clock configuration. used for synchronous mode. */ + USART_EnableContinuousSCLK(base, config->enableContinuousSCLK); + + return kStatus_Success; +} + +/*! + * brief Deinitializes a USART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the USART clock. + * + * param base USART peripheral base address. + */ +void USART_Deinit(USART_Type *base) +{ + /* Check arguments */ + assert(NULL != base); + while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) + { + } + /* Disable interrupts, disable dma requests, disable peripheral */ + base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK | + USART_FIFOINTENCLR_RXLVL_MASK; + base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK); + base->CFG &= ~(USART_CFG_ENABLE_MASK); +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the USART configuration structure to a default value. The default + * values are: + * usartConfig->baudRate_Bps = 115200U; + * usartConfig->parityMode = kUSART_ParityDisabled; + * usartConfig->stopBitCount = kUSART_OneStopBit; + * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; + * usartConfig->loopback = false; + * usartConfig->enableTx = false; + * usartConfig->enableRx = false; + * + * param config Pointer to configuration structure. + */ +void USART_GetDefaultConfig(usart_config_t *config) +{ + /* Check arguments */ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Set always all members ! */ + config->baudRate_Bps = 115200U; + config->parityMode = kUSART_ParityDisabled; + config->stopBitCount = kUSART_OneStopBit; + config->bitCountPerChar = kUSART_8BitsPerChar; + config->loopback = false; + config->enableRx = false; + config->enableTx = false; + config->enableMode32k = false; + config->txWatermark = kUSART_TxFifo0; + config->rxWatermark = kUSART_RxFifo1; + config->syncMode = kUSART_SyncModeDisabled; + config->enableContinuousSCLK = false; + config->clockPolarity = kUSART_RxSampleOnFallingEdge; +} + +/*! + * brief Sets the USART instance baud rate. + * + * This function configures the USART module baud rate. This function is used to update + * the USART module baud rate after the USART module is initialized by the USART_Init. + * code + * USART_SetBaudRate(USART1, 115200U, 20000000U); + * endcode + * + * param base USART peripheral base address. + * param baudrate_Bps USART baudrate to be set. + * param srcClock_Hz USART clock source frequency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success Set baudrate succeed. + * retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) +{ + uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1; + uint32_t osrval, brgval, diff, baudrate; + + /* check arguments */ + assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))); + if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* If synchronous master mode is enabled, only configure the BRG value. */ + if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U) + { + if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U) + { + brgval = srcClock_Hz / baudrate_Bps; + base->BRG = brgval - 1U; + } + } + else + { + /* + * Smaller values of OSR can make the sampling position within a data bit less accurate and may + * potentially cause more noise errors or incorrect data. + */ + for (osrval = best_osrval; osrval >= 8U; osrval--) + { + brgval = (((srcClock_Hz * 10U) / ((osrval + 1U) * baudrate_Bps)) - 5U) / 10U; + if (brgval > 0xFFFFU) + { + continue; + } + baudrate = srcClock_Hz / ((osrval + 1U) * (brgval + 1U)); + diff = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate; + if (diff < best_diff) + { + best_diff = diff; + best_osrval = osrval; + best_brgval = brgval; + } + } + + /* value over range */ + if (best_brgval > 0xFFFFU) + { + return kStatus_USART_BaudrateNotSupport; + } + + base->OSR = best_osrval; + base->BRG = best_brgval; + } + + return kStatus_Success; +} + +/*! + * brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source. + * + * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator + * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting + * SYSCON_RTCOSCCTRL_EN bit to 1. + * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that + * 9600 can evenly divide, eg: 4800, 3200. + * + * param base USART peripheral base address. + * param baudRate_Bps USART baudrate to be set.. + * param enableMode32k true is 32k mode, false is normal mode. + * param srcClock_Hz USART clock source frequency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success Set baudrate succeed. + * retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz) +{ + status_t result = kStatus_Success; + base->CFG &= ~(USART_CFG_ENABLE_MASK); + if (enableMode32k) + { + base->CFG |= USART_CFG_MODE32K_MASK; + if ((9600U % baudRate_Bps) == 0U) + { + base->BRG = 9600U / baudRate_Bps - 1U; + } + else + { + return kStatus_USART_BaudrateNotSupport; + } + } + else + { + base->CFG &= ~(USART_CFG_MODE32K_MASK); + result = USART_SetBaudRate(base, baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } + } + base->CFG |= USART_CFG_ENABLE_MASK; + return result; +} + +/*! + * brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * param base USART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + * retval kStatus_USART_Timeout Transmission timed out and was aborted. + * retval kStatus_InvalidArgument Invalid argument. + * retval kStatus_Success Successfully wrote all data. + */ +status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) +{ + /* Check arguments */ + assert(!((NULL == base) || (NULL == data))); +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + if ((NULL == base) || (NULL == data)) + { + return kStatus_InvalidArgument; + } + /* Check whether txFIFO is enabled */ + if (0U == (base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK)) + { + return kStatus_InvalidArgument; + } + for (; length > 0U; length--) + { + /* Loop until txFIFO get some space for new data */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) && (--waitTimes != 0U)) +#else + while (0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_USART_Timeout; + } +#endif + base->FIFOWR = *data; + data++; + } + /* Wait to finish transfer */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & USART_STAT_TXIDLE_MASK)) && (--waitTimes != 0U)) +#else + while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_USART_Timeout; + } +#endif + return kStatus_Success; +} + +/*! + * brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data and read data from the TX register. + * + * param base USART peripheral base address. + * param data Start address of the buffer to store the received data. + * param length Size of the buffer. + * retval kStatus_USART_FramingError Receiver overrun happened while receiving data. + * retval kStatus_USART_ParityError Noise error happened while receiving data. + * retval kStatus_USART_NoiseError Framing error happened while receiving data. + * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. + * retval kStatus_USART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully received all data. + */ +status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) +{ + uint32_t statusFlag; + status_t status = kStatus_Success; +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + /* check arguments */ + assert(!((NULL == base) || (NULL == data))); + if ((NULL == base) || (NULL == data)) + { + return kStatus_InvalidArgument; + } + + /* Check whether rxFIFO is enabled */ + if ((base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK) == 0U) + { + return kStatus_Fail; + } + for (; length > 0U; length--) + { + /* loop until rxFIFO have some data to read */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while (((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) && (--waitTimes != 0U)) +#else + while ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) +#endif + { + } +#if UART_RETRY_TIMES + if (waitTimes == 0U) + { + status = kStatus_USART_Timeout; + break; + } +#endif + /* check rxFIFO statusFlag */ + if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) + { + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; + status = kStatus_USART_RxError; + break; + } + /* check receive statusFlag */ + statusFlag = base->STAT; + /* Clear all status flags */ + base->STAT |= statusFlag; + if ((statusFlag & USART_STAT_PARITYERRINT_MASK) != 0U) + { + status = kStatus_USART_ParityError; + } + if ((statusFlag & USART_STAT_FRAMERRINT_MASK) != 0U) + { + status = kStatus_USART_FramingError; + } + if ((statusFlag & USART_STAT_RXNOISEINT_MASK) != 0U) + { + status = kStatus_USART_NoiseError; + } + + if (kStatus_Success == status) + { + *data = (uint8_t)base->FIFORD; + data++; + } + else + { + break; + } + } + return status; +} + +/*! + * brief Initializes the USART handle. + * + * This function initializes the USART handle which can be used for other USART + * transactional APIs. Usually, for a specified USART instance, + * call this API once to get the initialized handle. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param callback The callback function. + * param userData The parameter of the callback function. + */ +status_t USART_TransferCreateHandle(USART_Type *base, + usart_handle_t *handle, + usart_transfer_callback_t callback, + void *userData) +{ + /* Check 'base' */ + assert(!((NULL == base) || (NULL == handle))); + + uint32_t instance = 0; + usart_to_flexcomm_t handler; + handler.usart_master_handler = USART_TransferHandleIRQ; + + if ((NULL == base) || (NULL == handle)) + { + return kStatus_InvalidArgument; + } + + instance = USART_GetInstance(base); + + (void)memset(handle, 0, sizeof(*handle)); + /* Set the TX/RX state. */ + handle->rxState = (uint8_t)kUSART_RxIdle; + handle->txState = (uint8_t)kUSART_TxIdle; + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + handle->rxWatermark = (uint8_t)USART_FIFOTRIG_RXLVL_GET(base); + handle->txWatermark = (uint8_t)USART_FIFOTRIG_TXLVL_GET(base); + + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(s_usartIRQ[instance]); + + return kStatus_Success; +} + +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the IRQ handler, the USART driver calls the callback + * function and passes the ref kStatus_USART_TxIdle as status parameter. + * + * note The kStatus_USART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, + * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param xfer USART transfer structure. See #usart_transfer_t. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer) +{ + /* Check arguments */ + assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + /* Check xfer members */ + assert(!((0U == xfer->dataSize) || (NULL == xfer->data))); + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* Return error if current TX busy. */ + if ((uint8_t)kUSART_TxBusy == handle->txState) + { + return kStatus_USART_TxBusy; + } + else + { + /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up the + * handle value. */ + uint32_t regPrimask = DisableGlobalIRQ(); + handle->txData = xfer->data; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = (uint8_t)kUSART_TxBusy; + /* Enable transmiter interrupt. */ + base->FIFOINTENSET = USART_FIFOINTENSET_TXLVL_MASK; + /* Re-enable IRQ. */ + EnableGlobalIRQ(regPrimask); + } + return kStatus_Success; +} + +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are still not sent out. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable interrupts */ + USART_DisableInterrupts(base, (uint32_t)kUSART_TxLevelInterruptEnable); + /* Empty txFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK; + + handle->txDataSize = 0U; + handle->txState = (uint8_t)kUSART_TxIdle; +} + +/*! + * brief Get the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by interrupt method. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + if ((uint8_t)kUSART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - handle->txDataSize - + ((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); + + return kStatus_Success; +} + +/*! + * brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the USART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the USART driver notifies the upper layer + * through a callback function and passes the status parameter ref kStatus_USART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param xfer USART transfer structure, see #usart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into transmit queue. + * retval kStatus_USART_RxBusy Previous receive request is not finished. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveNonBlocking(USART_Type *base, + usart_handle_t *handle, + usart_transfer_t *xfer, + size_t *receivedBytes) +{ + uint32_t i; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + uint32_t regPrimask = 0U; + + /* Check arguments */ + assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + /* Check xfer members */ + assert(!((0U == xfer->dataSize) || (NULL == xfer->data))); + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to uart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to uart handle, receive data + to this empty space and trigger callback when finished. */ + if ((uint8_t)kUSART_RxBusy == handle->rxState) + { + return kStatus_USART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0U; + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer != NULL) + { + /* Disable IRQ, protect ring buffer. */ + regPrimask = DisableGlobalIRQ(); + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = USART_TransferGetRxRingBufferLength(handle); + if (bytesToCopy != 0U) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + bytesToReceive -= bytesToCopy; + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive != 0U) + { + /* No data in ring buffer, save the request to UART handle. */ + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = (uint8_t)kUSART_RxBusy; + } + /* Enable IRQ if previously enabled. */ + EnableGlobalIRQ(regPrimask); + /* Call user callback since all data are received. */ + if (0U == bytesToReceive) + { + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up + * the handle value. */ + regPrimask = DisableGlobalIRQ(); + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = (uint8_t)kUSART_RxBusy; + + /* Enable RX interrupt. */ + base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK; + /* Re-enable IRQ. */ + EnableGlobalIRQ(regPrimask); + } + /* Return the how many bytes have read. */ + if (receivedBytes != NULL) + { + *receivedBytes = bytesCurrentReceived; + } + } + return kStatus_Success; +} + +/*! + * brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) +{ + assert(NULL != handle); + + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (NULL == handle->rxRingBuffer) + { + /* Disable interrupts */ + USART_DisableInterrupts(base, (uint32_t)kUSART_RxLevelInterruptEnable); + /* Empty rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + } + + handle->rxDataSize = 0U; + handle->rxState = (uint8_t)kUSART_RxIdle; +} + +/*! + * brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + if ((uint8_t)kUSART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +/*! + * brief USART IRQ handle function. + * + * This function handles the USART transmit and receive IRQ request. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) +{ + /* Check arguments */ + assert((NULL != base) && (NULL != handle)); + + bool receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); + bool sendEnabled = (handle->txDataSize != 0U); + uint8_t rxdata; + size_t tmpsize; + + /* If RX overrun. */ + if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) + { + /* Clear rx error state. */ + base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; + /* clear rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_RxError, handle->userData); + } + } + while ((receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) || + (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U))) + { + /* Receive data */ + if (receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) + { + /* Receive to app bufffer if app buffer is present */ + if (handle->rxDataSize != 0U) + { + rxdata = (uint8_t)base->FIFORD; + *handle->rxData = rxdata; + handle->rxDataSize--; + handle->rxData++; + receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); + if (0U == handle->rxDataSize) + { + if (NULL == handle->rxRingBuffer) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; + } + handle->rxState = (uint8_t)kUSART_RxIdle; + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); + } + } + } + /* Otherwise receive to ring buffer if ring buffer is present */ + else + { + if (handle->rxRingBuffer != NULL) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (USART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData); + } + } + /* If ring buffer is still full after callback function, the oldest data is overridden. */ + if (USART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + /* Read data. */ + rxdata = (uint8_t)base->FIFORD; + handle->rxRingBuffer[handle->rxRingBufferHead] = rxdata; + /* Increase handle->rxRingBufferHead. */ + if ((size_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + } + /* Send data */ + if (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U)) + { + base->FIFOWR = *handle->txData; + handle->txDataSize--; + handle->txData++; + sendEnabled = handle->txDataSize != 0U; + if (!sendEnabled) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK; + + base->INTENSET = USART_INTENSET_TXIDLEEN_MASK; + } + } + } + + /* Tx idle and the interrupt is enabled. */ + if ((0U != (base->INTENSET & USART_INTENSET_TXIDLEEN_MASK)) && (0U != (base->INTSTAT & USART_INTSTAT_TXIDLE_MASK))) + { + /* Set txState to idle only when all data has been sent out to bus. */ + handle->txState = (uint8_t)kUSART_TxIdle; + /* Disable tx idle interrupt */ + base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK; + + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); + } + } + + /* ring buffer is not used */ + if (NULL == handle->rxRingBuffer) + { + tmpsize = handle->rxDataSize; + + /* restore if rx transfer ends and rxLevel is different from default value */ + if ((tmpsize == 0U) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark)) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark); + } + /* decrease level if rx transfer is bellow */ + if ((tmpsize != 0U) && (tmpsize < (USART_FIFOTRIG_RXLVL_GET(base) + 1U))) + { + base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(tmpsize - 1U)); + } + } +} diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart.h new file mode 100644 index 000000000..92979d2e1 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart.h @@ -0,0 +1,750 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_USART_H_ +#define _FSL_USART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup usart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief USART driver version 2.2.0. */ +#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*@}*/ + +#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT) +#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT) + +/*! @brief Retry times for waiting flag. */ +#ifndef UART_RETRY_TIMES +#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */ +#endif + +/*! @brief Error codes for the USART driver. */ +enum +{ + kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */ + kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */ + kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */ + kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */ + kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */ + kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */ + kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */ + kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */ + kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */ + kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */ + kStatus_USART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */ + kStatus_USART_Timeout = MAKE_STATUS(kStatusGroup_LPC_USART, 14), /*!< USART time out. */ +}; + +/*! @brief USART synchronous mode. */ +typedef enum _usart_sync_mode +{ + kUSART_SyncModeDisabled = 0x0U, /*!< Asynchronous mode. */ + kUSART_SyncModeSlave = 0x2U, /*!< Synchronous slave mode. */ + kUSART_SyncModeMaster = 0x3U, /*!< Synchronous master mode. */ +} usart_sync_mode_t; + +/*! @brief USART parity mode. */ +typedef enum _usart_parity_mode +{ + kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} usart_parity_mode_t; + +/*! @brief USART stop bit count. */ +typedef enum _usart_stop_bit_count +{ + kUSART_OneStopBit = 0U, /*!< One stop bit */ + kUSART_TwoStopBit = 1U, /*!< Two stop bits */ +} usart_stop_bit_count_t; + +/*! @brief USART data size. */ +typedef enum _usart_data_len +{ + kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */ + kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */ +} usart_data_len_t; + +/*! @brief USART clock polarity configuration, used in sync mode.*/ +typedef enum _usart_clock_polarity +{ + kUSART_RxSampleOnFallingEdge = 0x0U, /*!< Un_RXD is sampled on the falling edge of SCLK. */ + kUSART_RxSampleOnRisingEdge = 0x1U, /*!< Un_RXD is sampled on the rising edge of SCLK. */ +} usart_clock_polarity_t; + +/*! @brief txFIFO watermark values */ +typedef enum _usart_txfifo_watermark +{ + kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */ + kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */ + kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */ + kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */ + kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */ + kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */ + kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */ + kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */ +} usart_txfifo_watermark_t; + +/*! @brief rxFIFO watermark values */ +typedef enum _usart_rxfifo_watermark +{ + kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */ + kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */ + kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */ + kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */ + kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */ + kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */ + kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */ + kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */ +} usart_rxfifo_watermark_t; + +/*! + * @brief USART interrupt configuration structure, default settings all disabled. + */ +enum _usart_interrupt_enable +{ + kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK), + kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK), + kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK), + kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK), +}; + +/*! + * @brief USART status flags. + * + * This provides constants for the USART status flags for use in the USART functions. + */ +enum _usart_flags +{ + kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */ + kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */ + kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */ + kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */ + kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */ + kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */ +}; + +/*! @brief USART configuration structure. */ +typedef struct _usart_config +{ + uint32_t baudRate_Bps; /*!< USART baud rate */ + usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ + usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */ + bool loopback; /*!< Enable peripheral loopback */ + bool enableRx; /*!< Enable RX */ + bool enableTx; /*!< Enable TX */ + bool enableContinuousSCLK; /*!< USART continuous Clock generation enable in synchronous master mode. */ + bool enableMode32k; /*!< USART uses 32 kHz clock from the RTC oscillator as the clock source. */ + usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ + usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */ + usart_clock_polarity_t clockPolarity; /*!< Selects the clock polarity and sampling edge in synchronous mode. */ +} usart_config_t; + +/*! @brief USART transfer structure. */ +typedef struct _usart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} usart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _usart_handle usart_handle_t; + +/*! @brief USART transfer callback function. */ +typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData); + +/*! @brief USART handle structure. */ +struct _usart_handle +{ + uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + usart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< USART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ + + uint8_t txWatermark; /*!< txFIFO watermark */ + uint8_t rxWatermark; /*!< rxFIFO watermark */ +}; + +/*! @brief Typedef for usart interrupt handler. */ +typedef void (*flexcomm_usart_irq_handler_t)(USART_Type *base, usart_handle_t *handle); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! @brief Returns instance number for USART peripheral base address. */ +uint32_t USART_GetInstance(USART_Type *base); + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes a USART instance with user configuration structure and peripheral clock. + * + * This function configures the USART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the USART_GetDefaultConfig() function. + * Example below shows how to use this API to configure USART. + * @code + * usart_config_t usartConfig; + * usartConfig.baudRate_Bps = 115200U; + * usartConfig.parityMode = kUSART_ParityDisabled; + * usartConfig.stopBitCount = kUSART_OneStopBit; + * USART_Init(USART1, &usartConfig, 20000000U); + * @endcode + * + * @param base USART peripheral base address. + * @param config Pointer to user-defined configuration structure. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_InvalidArgument USART base address is not valid + * @retval kStatus_Success Status USART initialize succeed + */ +status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a USART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the USART clock. + * + * @param base USART peripheral base address. + */ +void USART_Deinit(USART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the USART configuration structure to a default value. The default + * values are: + * usartConfig->baudRate_Bps = 115200U; + * usartConfig->parityMode = kUSART_ParityDisabled; + * usartConfig->stopBitCount = kUSART_OneStopBit; + * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; + * usartConfig->loopback = false; + * usartConfig->enableTx = false; + * usartConfig->enableRx = false; + * + * @param config Pointer to configuration structure. + */ +void USART_GetDefaultConfig(usart_config_t *config); + +/*! + * @brief Sets the USART instance baud rate. + * + * This function configures the USART module baud rate. This function is used to update + * the USART module baud rate after the USART module is initialized by the USART_Init. + * @code + * USART_SetBaudRate(USART1, 115200U, 20000000U); + * @endcode + * + * @param base USART peripheral base address. + * @param baudrate_Bps USART baudrate to be set. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success Set baudrate succeed. + * @retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source + * + * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator + * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting + * SYSCON_RTCOSCCTRL_EN bit to 1. + * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that + * 9600 can evenly divide, eg: 4800, 3200. + * + * @param base USART peripheral base address. + * @param baudRate_Bps USART baudrate to be set.. + * @param enableMode32k true is 32k mode, false is normal mode. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success Set baudrate succeed. + * @retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get USART status flags. + * + * This function get all USART status flags, the flags are returned as the logical + * OR value of the enumerators @ref _usart_flags. To check a specific status, + * compare the return value with enumerators in @ref _usart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1)) + * { + * ... + * } + * @endcode + * + * @param base USART peripheral base address. + * @return USART status flags which are ORed by the enumerators in the _usart_flags. + */ +static inline uint32_t USART_GetStatusFlags(USART_Type *base) +{ + return base->FIFOSTAT; +} + +/*! + * @brief Clear USART status flags. + * + * This function clear supported USART status flags + * Flags that can be cleared or set are: + * kUSART_TxError + * kUSART_RxError + * For example: + * @code + * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError) + * @endcode + * + * @param base USART peripheral base address. + * @param mask status flags to be cleared. + */ +static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask) +{ + /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */ + base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK); +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables USART interrupts according to the provided mask. + * + * This function enables the USART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. + * For example, to enable TX empty interrupt and RX full interrupt: + * @code + * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); + * @endcode + * + * @param base USART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable. + */ +static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) +{ + base->FIFOINTENSET = mask & 0xFUL; +} + +/*! + * @brief Disables USART interrupts according to a provided mask. + * + * This function disables the USART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * @code + * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); + * @endcode + * + * @param base USART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable. + */ +static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) +{ + base->FIFOINTENCLR = mask & 0xFUL; +} + +/*! + * @brief Returns enabled USART interrupts. + * + * This function returns the enabled USART interrupts. + * + * @param base USART peripheral base address. + */ +static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base) +{ + return base->FIFOINTENSET; +} + +/*! + * @brief Enable DMA for Tx + */ +static inline void USART_EnableTxDMA(USART_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK; + } + else + { + base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK); + } +} + +/*! + * @brief Enable DMA for Rx + */ +static inline void USART_EnableRxDMA(USART_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK; + } + else + { + base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK); + } +} + +/*! + * @brief Enable CTS. + * This function will determine whether CTS is used for flow control. + * + * @param base USART peripheral base address. + * @param enable Enable CTS or not, true for enable and false for disable. + */ +static inline void USART_EnableCTS(USART_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= USART_CFG_CTSEN_MASK; + } + else + { + base->CFG &= ~USART_CFG_CTSEN_MASK; + } +} + +/*! + * @brief Continuous Clock generation. + * By default, SCLK is only output while data is being transmitted in synchronous mode. + * Enable this funciton, SCLK will run continuously in synchronous mode, allowing + * characters to be received on Un_RxD independently from transmission on Un_TXD). + * + * @param base USART peripheral base address. + * @param enable Enable Continuous Clock generation mode or not, true for enable and false for disable. + */ +static inline void USART_EnableContinuousSCLK(USART_Type *base, bool enable) +{ + if (enable) + { + base->CTL |= USART_CTL_CC_MASK; + } + else + { + base->CTL &= ~USART_CTL_CC_MASK; + } +} + +/*! + * @brief Enable Continuous Clock generation bit auto clear. + * While enable this cuntion, the Continuous Clock bit is automatically cleared when a complete + * character has been received. This bit is cleared at the same time. + * + * @param base USART peripheral base address. + * @param enable Enable auto clear or not, true for enable and false for disable. + */ +static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable) +{ + if (enable) + { + base->CTL |= USART_CTL_CLRCCONRX_MASK; + } + else + { + base->CTL &= ~USART_CTL_CLRCCONRX_MASK; + } +} +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Writes to the FIFOWR register. + * + * This function writes data to the txFIFO directly. The upper layer must ensure + * that txFIFO has space for data to write before calling this function. + * + * @param base USART peripheral base address. + * @param data The byte to write. + */ +static inline void USART_WriteByte(USART_Type *base, uint8_t data) +{ + base->FIFOWR = data; +} + +/*! + * @brief Reads the FIFORD register directly. + * + * This function reads data from the rxFIFO directly. The upper layer must + * ensure that the rxFIFO is not empty before calling this function. + * + * @param base USART peripheral base address. + * @return The byte read from USART data register. + */ +static inline uint8_t USART_ReadByte(USART_Type *base) +{ + return (uint8_t)base->FIFORD; +} + +/*! + * @brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * @param base USART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_USART_Timeout Transmission timed out and was aborted. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_Success Successfully wrote all data. + */ +status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data and read data from the TX register. + * + * @param base USART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data. + * @retval kStatus_USART_ParityError Noise error happened while receiving data. + * @retval kStatus_USART_NoiseError Framing error happened while receiving data. + * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. + * @retval kStatus_USART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully received all data. + */ +status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the USART handle. + * + * This function initializes the USART handle which can be used for other USART + * transactional APIs. Usually, for a specified USART instance, + * call this API once to get the initialized handle. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +status_t USART_TransferCreateHandle(USART_Type *base, + usart_handle_t *handle, + usart_transfer_callback_t callback, + void *userData); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the IRQ handler, the USART driver calls the callback + * function and passes the @ref kStatus_USART_TxIdle as status parameter. + * + * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, + * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART transfer structure. See #usart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific USART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void USART_TransferStartRingBuffer(USART_Type *base, + usart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param handle USART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are still not sent out. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by interrupt method. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the USART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the USART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART transfer structure, see #usart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into transmit queue. + * @retval kStatus_USART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveNonBlocking(USART_Type *base, + usart_handle_t *handle, + usart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); + +/*! + * @brief USART IRQ handle function. + * + * This function handles the USART transmit and receive IRQ request. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_USART_H_ */ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/fsl_device_registers.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/fsl_device_registers.h new file mode 100644 index 000000000..c3d27c58d --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/fsl_device_registers.h @@ -0,0 +1,44 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV98_cm33_core0)) + +#define LPC55S69_cm33_core0_SERIES + +/* CMSIS-style register definitions */ +#include "LPC55S69_cm33_core0.h" +/* CPU specific feature definitions */ +#include "LPC55S69_cm33_core0_features.h" + +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV98_cm33_core1)) + +#define LPC55S69_cm33_core1_SERIES + +/* CMSIS-style register definitions */ +#include "LPC55S69_cm33_core1.h" +/* CPU specific feature definitions */ +#include "LPC55S69_cm33_core1_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/system_LPC55S69_cm33_core0.c b/source/hic_hal/nxp/lpc55xx/LPC55S69/system_LPC55S69_cm33_core0.c new file mode 100644 index 000000000..595e84d0f --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/system_LPC55S69_cm33_core0.c @@ -0,0 +1,379 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b200418 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2020 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** +** ################################################################### +*/ + +/*! + * @file LPC55S69_cm33_core0 + * @version 1.1 + * @date 2019-05-16 + * @brief Device specific configuration file for LPC55S69_cm33_core0 + * (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +/* PLL0 SSCG control1 */ +#define PLL_SSCG_MD_FRACT_P 0U +#define PLL_SSCG_MD_INT_P 25U +#define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P) +#define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P) + +/* Get predivider (N) from PLL0 NDEC setting */ +static uint32_t findPll0PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL0 PDEC setting */ +static uint32_t findPll0PostDiv(void) +{ + uint32_t postDiv = 1; + + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; + } + else + { + postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + return postDiv; +} + +/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ +static float findPll0MMult(void) +{ + float mMult = 1.0F; + float mMult_fract; + uint32_t mMult_int; + + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) + { + mMult = (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); + } + else + { + mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); + mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P); + mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M) / + (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (mMult == 0.0F) + { + mMult = 1.0F; + } + return mMult; +} + +/* Get predivider (N) from PLL1 NDEC setting */ +static uint32_t findPll1PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL1 PDEC setting */ +static uint32_t findPll1PostDiv(void) +{ + uint32_t postDiv = 1UL; + + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK; + } + else + { + postDiv = 2UL * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + return postDiv; +} + +/* Get multiplier (M) from PLL1 MDEC settings */ +static uint32_t findPll1MMult(void) +{ + uint32_t mMult = 1UL; + + mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK; + + if (mMult == 0UL) + { + mMult = 1UL; + } + return mMult; +} + +/* Get FRO 12M Clk */ +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ +static uint32_t GetFro12MFreq(void) +{ + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; +} + +/* Get FRO 1M Clk */ +/*! brief Return Frequency of FRO 1MHz + * return Frequency of FRO 1MHz + */ +static uint32_t GetFro1MFreq(void) +{ + return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; +} + +/* Get EXT OSC Clk */ +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ +static uint32_t GetExtClkFreq(void) +{ + return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? CLK_CLK_IN : 0U; +} + +/* Get HF FRO Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +static uint32_t GetFroHfFreq(void) +{ + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; +} + +/* Get RTC OSC Clk */ +/*! brief Return Frequency of 32kHz osc + * return Frequency of 32kHz osc + */ +static uint32_t GetOsc32KFreq(void) +{ + return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? + CLK_RTC_32K_CLK : + ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && ((PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK) != 0UL)) ? + CLK_RTC_32K_CLK : + 0U; +} + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__isr_vector; + SCB->VTOR = (uint32_t) &__isr_vector; +#endif + SYSCON->TRACECLKDIV = 0; +/* Optionally enable RAM banks that may be off by default at reset */ +#if !defined(DONT_ENABLE_DISABLED_RAMBANKS) + SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK + | SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK; +#endif + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + uint64_t workRate; + uint64_t workRate1; + + switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) + { + case 0x00: /* MAINCLKSELA clock (main_clk_a)*/ + switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = GetFro12MFreq(); + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = GetExtClkFreq(); + break; + case 0x02: /* Fro 1MHz (fro_1m) */ + clkRate = GetFro1MFreq(); + break; + default: /* = 0x03 = FRO 96 MHz (fro_hf) */ + clkRate = GetFroHfFreq(); + break; + } + break; + case 0x01: /* PLL0 clock (pll0_clk)*/ + switch (SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = GetFro12MFreq(); + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = GetExtClkFreq(); + break; + case 0x02: /* Fro 1MHz (fro_1m) */ + clkRate = GetFro1MFreq(); + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = GetOsc32KFreq(); + break; + default: + clkRate = 0UL; + break; + } + if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) + { + prediv = findPll0PreDiv(); + postdiv = findPll0PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (uint64_t)clkRate * (uint64_t)findPll0MMult(); + clkRate = (uint32_t)(workRate / ((uint64_t)postdiv)); + } + break; + case 0x02: /* PLL1 clock (pll1_clk)*/ + switch (SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = GetFro12MFreq(); + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = GetExtClkFreq(); + break; + case 0x02: /* Fro 1MHz (fro_1m) */ + clkRate = GetFro1MFreq(); + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = GetOsc32KFreq(); + break; + default: + clkRate = 0UL; + break; + } + if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0UL)) + { + /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ + prediv = findPll1PreDiv(); + postdiv = findPll1PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + + /* MDEC used for rate */ + workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult(); + clkRate = (uint32_t)(workRate1 / ((uint64_t)postdiv)); + } + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = GetOsc32KFreq(); + break; + default: + clkRate = 0UL; + break; + } + SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL); +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/system_LPC55S69_cm33_core0.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/system_LPC55S69_cm33_core0.h new file mode 100644 index 000000000..25204afcd --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/system_LPC55S69_cm33_core0.h @@ -0,0 +1,112 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b190830 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** +** ################################################################### +*/ + +/*! + * @file LPC55S69_cm33_core0 + * @version 1.1 + * @date 2019-05-16 + * @brief Device specific configuration file for LPC55S69_cm33_core0 (header + * file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_LPC55S69_cm33_core0_H_ +#define _SYSTEM_LPC55S69_cm33_core0_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ +#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ +#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit(void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate(void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_LPC55S69_cm33_core0_H_ */ diff --git a/source/hic_hal/nxp/lpc55xx/RTE_Device.h b/source/hic_hal/nxp/lpc55xx/RTE_Device.h new file mode 100644 index 000000000..9a06e04ea --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/RTE_Device.h @@ -0,0 +1,32 @@ +/* ----------------------------------------------------------------------------- + * Copyright (C) 2013 ARM Limited. All rights reserved. + * + * $Date: 27. June 2013 + * $Revision: V1.00 + * + * Project: RTE Device Configuration for NXP Kinetis K20 + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define RTE_USART1 1 +#define RTE_USART1_DMA_EN 0 + + +#define RTE_USART1_DMA_TX_DMA_BASE (DMA0) +#define RTE_USART1_DMA_TX_CH (0) +#define RTE_USART1_DMA_TX_DMAMUX_BASE (DMAMUX0) +#define RTE_USART1_DMA_TX_PERI_SEL (5) // DMAMUX source 5 is UART1 TX + +#define RTE_USART1_DMA_RX_DMA_BASE (DMA0) +#define RTE_USART1_DMA_RX_CH (1) +#define RTE_USART1_DMA_RX_DMAMUX_BASE (DMAMUX0) +#define RTE_USART1_DMA_RX_PERI_SEL (4) // DMAMUX source 4 is UART1 RX + + +#endif /* __RTE_DEVICE_H */ + diff --git a/source/hic_hal/nxp/lpc55xx/armcc/keil_lib_power_cm33_core0.lib b/source/hic_hal/nxp/lpc55xx/armcc/keil_lib_power_cm33_core0.lib new file mode 100644 index 0000000000000000000000000000000000000000..8b6b7de904ac1938526df18394a5166b2a306c97 GIT binary patch literal 10560 zcma)B4RBl4l|JuDmSiij6(=Dk3CXkKb&Lr@@*j4Z4bPS%+xfFefYOE5l5GWfV@JX< zO-MUnQii%L+m#^&Z>Q}Bn(44R9mb>!6IilNAV6qY)`0*S+D?_(>28R-Mez@--GsjV z&UA%0bFYJ%q*SM!A&==YpAw#`s&tQ0L>b$j8HT8-jX4vQT z*45Q1iqGq-uF}^cSn%MctpQ1rkZwaHs-QVUbY!Kj&#Td^3JRcCYtvfuBQ!f2%ePy{ z8>i0F$tm(ugj#6)tcw<3DI%54ndiojlP&SF!hk&x38wasI*2X8`4vYmN1HSB6kTBTP}%cZP$jJM3tGOhLTfc+xLbm^g3hbqNo zh1vcswIpth%TMP2z;Vd_1KXjJWM$E+@zx}%3T7yXYg?5_X++yrnxw|k;QJ{Wibg(4 zk!!Qv^1k##chV|Lk5iHY!;D9jq=Te*ME6sPc>PN7bsiCPjUB&`{H}v!^@?`oPpyO) z&r<>+>TznDizAi_$AnzroRBIC&rIYMpS3Ib?&8FRWPShD>E^Bli3v;IS&NeAb|e-n zCGNZgv`rG1?)a*vi;ed-UOb^{Z4Q47d7QbDPeFrP=TE(04QQ>lh=MrOq?MFlMMP^? zlNPE#M2Co5ucQ7jWwo4-3^{|-Px-Xg^Fhv!qDZCW=2m^AX==F?nl7UHpw`MO=o413 zF`@*9TPpe+r)<)&zapGEPUF0mD#R*gz&E&H?RDOda&-UYL2hqk>aZaLGQ z)V$94s)RRkN6NKQ#TwGc^ATyp*DH_s{@OC)+ie}WcX!^%^Sf;$AEXYu>?n`894M16 zXFMPE46k@=g=$Tz(vtYnk;Nm$*a2r#beMCe@U94I?brol@29Ns53#ltNgML9;92&l zG*SQy2Uh(}^kC)3UWb)))ElJHK+3g18XXJDqu!8Z)Z1kp^>*it#=32zW8L=AH&Tbm zf$|9DqfAl(${D(jcg^3?cnLP`e`%j-F0Z66Ai31sKfIriPBWjvvts6x^n68A4qhUwlfYr*gcD?L(HS@@!doXM9S1cvzkv8^s;ACo8!Ms79 z*UBF28b_i*A5Ec`{0@CI-J@-LAE!xldiBkvGqI4v|9WbeJ_$RYTFcMWc4J?BkfQhp zDeKTPfpw8G?23w@aSrflVb}M?FH=P8f^Wd?4cHlH!tZ~lX;{P|UelNhyNBegv*D9z z*ARXW4ZNte6-4;FDF}MUho)V_u@={V&z&KN){AFf7d|^(FKBIY*>F?+xKyUKaZP24 zaV`apUvQ~d=kbS*jN7I2vw1v-$H)~noIj3<;g_`5hax8;wuIIyMbwDQb+6j{OMCuA zn?u{YDA*Bwcn-tXA8quclb2xKcB&(6_*yihpm`>+puivw`U)&*E$6G!<+;w8A zyg0x2SJ2#Q(KX%BEPkSCczkg{+bowp!5)`to4KY^`TG2c@4ci>RX55Nj`8-HCqwGg z15K_(`^=vG|1r=|lo^eaOv4o?o*H#T2$x$sS?y!_&!!I0mY(6(4+Pv5h|y+qNrzZiIHa+B@! z{oh^+=#B^7!THsn?F)aznwn_GCxs5a z${ENnv?l1%LTTWJ;qeDc-#Yr+WH#9H3T=@Eu%Y~=%5{*;CHLf*{Q>mq{@{^OQ^y;Ka*Ebxjw_KKP zwOuBaGc|H~`Vz7=t+mRL-yDrjFLmFtj&pVFwo{Xqo)xxVTsqdt`+E(dUsfGihfJ;c z_0gt_7Wc2xSv|J%wMnTv-}by=x#n87^hMG+ZMt~UCk2zo-$rh>lB^;;Jw8=BaWpjT z$2$u@d4H5$%?^F9bM8!=vDv`~^WMd|=);MkE^u#2jLjZ+Fz+04R@y!@susGN66%!P zINZcmC!iZs7rE=9Tanfgbf?uNZVz-dX`KSyIrSQM8FbsyIu*JLYKeO}bi2~JAaqG} zh1&()gV4#CV`z~LPs8CwW3x|S2jNs()IO6^SGip;xcu7Y_aZHyu5SLRzr;TgbVZbz zq|4!V1zpGa*)?M#f3!aq-4ot3xL#@8u}xvv+ZP^C>O8(`k59QR8tq%Jga-P%`$Bu} zQSPeksc)$5@p`{bja$GG3WvISNoqvXU*+*OP+oU*U@*M@#{TMRvMsW2b5Opez)?tx zq+)rAyp)znCDOIha%qLMQd(toOJ!2I6m z%jmb5Z%$TFQ5IfJZ-H-4+%%Mh%V~QSuB89S8gHjzUYU$|s5h&>ieAeaUq=VB@Oo;^ z!W(I6)_5l!$?7kn`?Bz2dKGhXIv&GMrXso>@$>py@#FRX7W`AtGI0y~c|8qWN&V;_ z7Vuk`pSjHbb+G64Hn4|w!2XJWpJRXFfZ4wt*ec-5@Yf;WMc`91ZnTTDg3UI8D%_!HN3-}*_-xlyM zz&E%5R?yFY%QEr0X%>7H0{(mSZ^+v$t|qUQd%jw?~li3QJ#C>DZqf>`)UMGy;~H&HCcr(H&6p=FsiH!QRw z2d~b-?i^g6gLD1${AyZ|?q8>4Hzm@T_eil^MU!cJ-c!Z$ zdfEVgVWN*KmOb=%8uK$yRpMhb@`~14NurC(^c^>uRDP z>u)ulStl-S9%X$k(aWqaMFFY2!>FA|FYiU?%?7Ugs_|So>tW0K2BIZgBkiCf=U4FT zqAmy%HF3R*Xb0>00f1Cu6PtdO06RAlDO~?05t_PRx}UcY{gCx4(LZtBNOY8Ikg}gn zzi|d;{QX)EZ?oYy$9Xr~ZzAg9IzSZTx`pT)NU{^b9pJi+=t5wXUGXK_g|CUbN zWcvGdH}`&%Ja`)%Bu{s=zaKA|@w|`zH-R-$c@?4_% zy06ZYeKkKX*E}Zk@?~Gk>s0gFiIM6T?76efZ!j-cCZ$=o^0|axV0Bg2&)@aW$NG6I z<6&(a91L|w@Vt^|PjoQsY1w}JjeDU2p66*bcJ=4}gOWSp{02D@WIg#k-96pu|4-n- z--WMGVc&fz%P(Tzd;i|SaKCxHT#b1?t6bJyoqKUk_4PzMLs7lzpP%;&?Xv$D(@mbe zg9C%1F4Xt;b6qy*scPWThqA}hK%JfXw{|Bc>+Tz^r7tW2)(tPHKM5is>L3k4~YFki2(Fc zux;q9o@1#ML5&EiMF2`+5CirSWe=_?xDY|R~A5ILRU8Mid_tNvGuYFB^E?4({Cikd&r+F>+$Yv5sWJE z@_IkN*rWxofVwO~$!(hf^>^EJQ?IOP@EOQ*?aBm0)9!y^moMlKV*(d2UQ2a<*pA(J z*WimCM4JV#%evn5+2ngChi?pgJf8UwqWN)d~xVRzE;6Mgr4DBgYlw&8-O{7rkH%Ip%?i&z}EpIUSIxat?A$Y zVXWxi!`Nr+AKS2)e4oNd3PlD7jxe4=j6p9%&UOM zjKgNck(uj9;N$O5Q%pWNCk_|*6c}+FZv0HXkI;r`CNHPc{;>^<$@c-;;=b|<{*|Te zI8Qq;0DKw$Ccw89*c6j*I~pQiJ^0M$5}(o;|5h1%8UI!y$vh9+u$X+ybNFI{e-&vv z9*66QEdR>D$IrAWCLgY8vi#dG^YsuC``WLoOqLhe|(=~^4*=2zjNT@{ILy-$#-WCA78$)9mmW2+T{DaaUNuz zj|7ZXqTdvg?|klgAn>h+vB~$c!I#P3m9&3s!(#Hin8W81_%@{N*x#RHfS5lk7V&K+ zN{h+&EE?kamI!=&U&waM_ickOsX2ljM^;OhGhspn8vux!glE^MID=VD$X&aFe5S8d9hcyKa3y8!TbCF E0TW?9tN;K2 literal 0 HcmV?d00001 diff --git a/source/hic_hal/nxp/lpc55xx/daplink_addr.h b/source/hic_hal/nxp/lpc55xx/daplink_addr.h new file mode 100644 index 000000000..7973e5b2c --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/daplink_addr.h @@ -0,0 +1,82 @@ +/** + * @file daplink_addr.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DAPLINK_ADDR_H +#define DAPLINK_ADDR_H + +/* Device sizes */ + +#define DAPLINK_ROM_START 0x00000000 +#define DAPLINK_ROM_SIZE 0x00040000 // Intentionally set to only 256 kB of total 640 kB. + +#define DAPLINK_RAM_START 0x20000000 +#define DAPLINK_RAM_SIZE 0x00044000 // 272 kB RAM + +/* ROM sizes */ + +#define DAPLINK_ROM_BL_START 0x00000000 +#define DAPLINK_ROM_BL_SIZE 0x00010000 // 64 kB bootloader + +#define DAPLINK_ROM_CONFIG_ADMIN_START 0x00010000 +#define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00000000 + +#define DAPLINK_ROM_IF_START 0x00010000 +#define DAPLINK_ROM_IF_SIZE 0x0002f000 // 192 kB interface + +#define DAPLINK_ROM_CONFIG_USER_START 0x0003f000 +#define DAPLINK_ROM_CONFIG_USER_SIZE 0x00001000 // 4 kB user config + +/* RAM sizes */ + +#define DAPLINK_RAM_APP_START 0x20000000 +#define DAPLINK_RAM_APP_SIZE 0x00043f00 + +#define DAPLINK_RAM_SHARED_START 0x20043f00 +#define DAPLINK_RAM_SHARED_SIZE 0x00000100 + +/* Flash Programming Info */ + +#define DAPLINK_SECTOR_SIZE 0x00008000 +#define DAPLINK_MIN_WRITE_SIZE 0x00000010 + +/* Current build */ + +#if defined(DAPLINK_BL) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_BL_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_IF_SIZE + +#elif defined(DAPLINK_IF) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_IF_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_BL_SIZE + +#else + +#error "Build must be either bootloader or interface" + +#endif + +#endif diff --git a/source/hic_hal/nxp/lpc55xx/fsl_usb.h b/source/hic_hal/nxp/lpc55xx/fsl_usb.h new file mode 100644 index 000000000..93af25ef7 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/fsl_usb.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __FSL_USB_H__ +#define __FSL_USB_H__ + +#include +#include +#include "fsl_common.h" +// #include "fsl_os_abstraction.h" +#include "usb_misc.h" +#include "usb_spec.h" + +/*! + * @addtogroup usb_drv + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Defines USB stack major version */ +#define USB_STACK_VERSION_MAJOR (2U) +/*! @brief Defines USB stack minor version */ +#define USB_STACK_VERSION_MINOR (6U) +/*! @brief Defines USB stack bugfix version */ +#define USB_STACK_VERSION_BUGFIX (0U) + +/*! @brief USB stack version definition */ +#define USB_MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/*! @brief USB stack component version definition, changed with component in yaml together */ +#define USB_STACK_COMPONENT_VERSION \ + MAKE_VERSION(USB_STACK_VERSION_MAJOR, USB_STACK_VERSION_MINOR, USB_STACK_VERSION_BUGFIX) + +/* + * Component ID used by tools + * + * FSL_COMPONENT_ID "middleware.usb.stack_common" + */ + +/*! @brief USB error code */ +typedef enum _usb_status +{ + kStatus_USB_Success = 0x00U, /*!< Success */ + kStatus_USB_Error, /*!< Failed */ + + kStatus_USB_Busy, /*!< Busy */ + kStatus_USB_InvalidHandle, /*!< Invalid handle */ + kStatus_USB_InvalidParameter, /*!< Invalid parameter */ + kStatus_USB_InvalidRequest, /*!< Invalid request */ + kStatus_USB_ControllerNotFound, /*!< Controller cannot be found */ + kStatus_USB_InvalidControllerInterface, /*!< Invalid controller interface */ + + kStatus_USB_NotSupported, /*!< Configuration is not supported */ + kStatus_USB_Retry, /*!< Enumeration get configuration retry */ + kStatus_USB_TransferStall, /*!< Transfer stalled */ + kStatus_USB_TransferFailed, /*!< Transfer failed */ + kStatus_USB_AllocFail, /*!< Allocation failed */ + kStatus_USB_LackSwapBuffer, /*!< Insufficient swap buffer for KHCI */ + kStatus_USB_TransferCancel, /*!< The transfer cancelled */ + kStatus_USB_BandwidthFail, /*!< Allocate bandwidth failed */ + kStatus_USB_MSDStatusFail, /*!< For MSD, the CSW status means fail */ + kStatus_USB_EHCIAttached, + kStatus_USB_EHCIDetached, + kStatus_USB_DataOverRun, /*!< The amount of data returned by the endpoint exceeded + either the size of the maximum data packet allowed + from the endpoint or the remaining buffer size. */ +} usb_status_t; + +/*! @brief USB host handle type define */ +typedef void *usb_host_handle; + +/*! @brief USB device handle type define. For device stack it is the whole device handle; for host stack it is the + * attached device instance handle*/ +typedef void *usb_device_handle; + +/*! @brief USB OTG handle type define */ +typedef void *usb_otg_handle; + +/*! @brief USB controller ID */ +typedef enum _usb_controller_index +{ + kUSB_ControllerKhci0 = 0U, /*!< KHCI 0U */ + kUSB_ControllerKhci1 = 1U, /*!< KHCI 1U, Currently, there are no platforms which have two KHCI IPs, this is reserved + to be used in the future. */ + kUSB_ControllerEhci0 = 2U, /*!< EHCI 0U */ + kUSB_ControllerEhci1 = 3U, /*!< EHCI 1U, Currently, there are no platforms which have two EHCI IPs, this is reserved + to be used in the future. */ + + kUSB_ControllerLpcIp3511Fs0 = 4U, /*!< LPC USB IP3511 FS controller 0 */ + kUSB_ControllerLpcIp3511Fs1 = 5U, /*!< LPC USB IP3511 FS controller 1, there are no platforms which have two IP3511 + IPs, this is reserved to be used in the future. */ + + kUSB_ControllerLpcIp3511Hs0 = 6U, /*!< LPC USB IP3511 HS controller 0 */ + kUSB_ControllerLpcIp3511Hs1 = 7U, /*!< LPC USB IP3511 HS controller 1, there are no platforms which have two IP3511 + IPs, this is reserved to be used in the future. */ + + kUSB_ControllerOhci0 = 8U, /*!< OHCI 0U */ + kUSB_ControllerOhci1 = 9U, /*!< OHCI 1U, Currently, there are no platforms which have two OHCI IPs, this is reserved + to be used in the future. */ + + kUSB_ControllerIp3516Hs0 = 10U, /*!< IP3516HS 0U */ + kUSB_ControllerIp3516Hs1 = 11U, /*!< IP3516HS 1U, Currently, there are no platforms which have two IP3516HS IPs, + this is reserved to be used in the future. */ + kUSB_ControllerDwc30 = 12U, /*!< DWC3 0U */ + kUSB_ControllerDwc31 = 13U, /*!< DWC3 1U Currently, there are no platforms which have two Dwc IPs, this is reserved + to be used in the future.*/ +} usb_controller_index_t; + +/** + * @brief USB stack version fields + */ +typedef struct _usb_version +{ + uint8_t major; /*!< Major */ + uint8_t minor; /*!< Minor */ + uint8_t bugfix; /*!< Bug fix */ +} usb_version_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! @} */ + +#endif /* __FSL_USB_H__ */ diff --git a/source/hic_hal/nxp/lpc55xx/gcc/libpower_hardabi.a b/source/hic_hal/nxp/lpc55xx/gcc/libpower_hardabi.a new file mode 100644 index 0000000000000000000000000000000000000000..bb57d0128bd4bf886559e88d7a21fb7e2f2a45a5 GIT binary patch literal 62336 zcmc${3tU{)wLiYkIdf))*Es_Nfy^Pv5FjBB2m>S`F;QTEKmq}Qyfk$nKmvxBJYr(i zppB1OuT4y9eMC)duGhBOM(eA+w((W9T3er0TdUSrG-`_`R;p3|-?jHSXU-6Mdw-w* z|M&TyWY6Aft-bbRt+m%)XP?7N*0Q$2_O4Uo7X)Lk(848)78WiJEh-KM3pvU884MN| z3OE>Sjc1G{FeVNBZ&PE#x~ir~ct?9rXLw+wysx9Wr){W<33OH8aOYrUXXik34?dj8 z#{P3b=|8v6iKLp75}fQSI*04JH?8d)9O~}3xSKnN*Y@`ew{7XH?jNik>^#S8b^UN# zPjS)KuJgie18tky`nI+VcK4bz@DMq)sJH99x{iJa2S@!I4&Kn_p`OS9O(fFOy{Vvo zfi35vSUHCZ3l}X~6bvp3Eh#MJ@^6jbSyfjpNfN{@E{Wx_D8$&oqa3f6@GOrNuzYq} zp6lhyE4V8ufp?^Ld>P+s*`es+Wf2UhGvV(ieT=j|-KXT~#SpGe_rD;B&` z_DR6Zi_N^w%sb8eLY^P`bZ>vj;kc~$tQo=SIr1BFmOrTF`0GFD&OSaK&K{egWQW5? zN3%a@n+MF8KYX;jd`?^8uavAQ!Q`ByM_gG`gQ+?19#ON5;FO#FQk2$tJ>fA$ znb+~+_zQ(p`VI0wj=Rzy?n+xV^Y~6Vp={>yvI>9rk=B%&uRr_hYc^BL3I?h4$8lB? ztTqx2SNJ$<4vz(t$AI}}*R?BN9N%4-eSEYzd(4gYb{CHS%9X5`{ntAv5 zn6WBzrO}nr^@^wEaA4J$-e-|#tZee`t;jp z=B|`>CwHCUc|zHESP80G4P#8HJp9nH%JR#nR~&t?B0gL(Hab`_)+#^!zAGDJtC%u2 zSI;;+Ym8OP-=|!1KmES9>go60RhfsYfsMarU(ep2uIlVD7T(+8U*#HOmD9Vv(WR}r zzUy>P#bN1&Y>YzMyVopxQKr#T+k1Pm!Q);vz4aTdzC*uyZ|ov=_{7&Iz9JnRKM}{+ zU)dX&e}lU^vHHeCY1J&NY-ZwZ*YepX-mnU@mzCC|Zg=9|q-(T&j~>%pnRh1L0KFF{ z?X6rD=z3n+a9GJ!XFhzavSKgh_ecfHj?T}QJ?jPq@(Uj?Ytpa&^PNjp&FFr9oE>_8 zJmbLg}uiqE@)ZhW$==f_s*jW`b zk6$3eUMsv~Wy;L4V~}8K_S5gDWdCQ+4|}p#zdnBDD9PxD9igtlu9wHXg$a9Loh<(9 zxV=w|ds*UbB$Wd_aW^Df7k|Av#;Vlte|CUU7-~&fHP|X$zhaE7n9=qKM)(Lu_y~=# zUA{ihp>ygTT@C(H8U)0H)iB>UYACNnP6LaB`8N-~CQSL{Bd zSEp5vnzl8)I%B`EEtW-Vk?pPcB%rh(C9TaK^DFY+7615fXhuZ_^olVyWgaGJOMAOk zWpq6*acKu1JXYEIt?6Y)A1Nyv8y#>%8f9ax4E7|!awW}T(-xX{)K00(j8F-=1({Oa3-1Z_U=QOOuS|3W@vPIec!n^K< zqp2xf9A69kX#2zCPxyk$&KKH1*_YDKDPiIOW!zU@|LCy<7kopotYPNyfldA}`G%g& z3HwNgw?a?Cj(^zk(l|Tt(zt8)i{su=H>^Ale&i>uB$*%fOb_4M@f+YDN1ew}hg;(9N&G;td$Rs@ACcN$U83OMV6g&e02DRBX5Nj%;x(?WM0q3>t(J?-g5ns zTU_#sImg-X_l~?7mXEVRe|Wc9OSI-kYft$09_i%uMmw(J^+qxJZ^zV&L%ng|l}BcZ z_Bt*T?V;Yq@I9paGR8)kk20Ctz~7JgE*iYowbI{BYt-LXc=)1YzRR(ze8k>>>+QY;V(g$GAoh9`?M4@`p$-BfW|=YZX~)W>?K8 zlJdi_r~2E~%btDoShe!#F?aBxzz;sS2u=*;vPX|S){+xA_`xpkXywBntY8htpBQWo zUtB7E!3v)!-2KHTW9eBB-bGrJzwnMX99Y1H;d}mtj@$=U#4}aQ$m2{aer(rC?o0y$d{X2~RcNiayJ8tE3fqsK;vl4*7oG`oW|JNJ~z*)t#cSW>FklOL2Z`3r^5^z^V^n)n6tiJ2yu zGhG|LxcWUKt~JN?=3SVu~D%%}WzJXlEc zP0i^aOLX^-d8LEZEc+qM`3agc=HXsh%lv0cW15sb_BW+Wni_uaE^pYk39~#*^oJ45 zxF8*TO3UXmmiW^|#^CcLhAC;SQ?bmIcJ#DK&)nH9iubqz@{|UUh2$YDj3_{di_B z)p!FRNiNOvv=sLzOiw!-+@3#3DMx9pTK*hB&qyhM2UMnwK`NeS1#MKTPyjtAXbI>^vo znF8o@LCewf96(R{|>0u3G@;YXOyN7s4z( zOy-hWrd+mYJn;g$T)Tz(OAyeN8aJIp zIpr(#uv_RiNzj;SIhvfJVNJMXeIH3p7k!k;`t=0*1XwBS2MA0SV2x>4DRRnm@YczC z6=~NmT5gnuU8M?Yi>%MZ0`#N_>Uy+{Rppr?z>Ttg2Z8AVY?bw=U_PD<0d~mxMFdV2 zV3(|qk%0sR*dyx)NuGuP2V}j*129v7!!qNxNk+g8IDsXQ#ktAS9<-1WOFV>f0wFl% zPZmXiDbP^!%;!FXPP&kY=M9ZbXf*JE4B`r^rm10;4Utp^& zB9_i6D655}&*X%uzW}G}ubGT_>yxP!H@UMNR&9@fziq(@0=~|I6#@Uqg8weyUs&*G z0{*Q9e^ZR+6$_SG0?~M^hSLxpF13}Bs zen+i*C|b$X-klBTBS8ylxiDDyZ-OsJdx>iP-RJ8@e|g%M5WYMnY8Gny;05K6Ma>fJ zO{)2cs9CDDVxh~&M9ng7YA>0;<%?a{zrRpc?HX;`@isM^mrUenq4HOwbN#m(!@n z1$4JIPBs52dbnTvg%{B0g7%cI=8`|5pNRz}%Yw!veOo?2MSw0z|2CYS>=Jdo zl2GqQm=RZRJM*6fXDX}73aOmiMm&bkiRr?C0v7CH2}I*IzR*HSyy^^=Faww*Cdoxh z<62NmZLDoza`Dn+s)<$d4m_h=vQ$|Lkau$q3Y_<6qQ#3W*u@fvmNqW`M_Js@;J`JV zc&{om&F%~=Ao;sxrr8bB^mYrHSBoP>>=96+HjLdyzFI&&?L30^3Mf^3fNJg&P=;2A zAu|SC`bD-ndG$s%G3UWNJ73&K=ZXK_&xc00Tqe`aYGqj z5GC3zWCr^MtyGx#je@pJdzQ@LCP6FHHs%4kSwNNAMPz6P1XQDaMbHlfRHt>)$Zio( zqgW6>Ec4OYZqW)58_5R+twVDy0Q8>%>Jkg$R?&NpwiY{){9i(z1KKD_={8YwSS*1b zmHEg?ZP&a|i~M6j+okCQ{X{^QizRToX!A<#TeQgT5VYOez43s4Dtg$bU5Q;^{+Xa% ztNoUGKO~_2VnN&~S~;NolLE}U1nr>qHEHGN0=iApNM?77nzw5kX!+kGXos|9S^@V8 z=x!~6B!8cP?$@Rg-~EE`0j&?_CI3Ru9@KJ(_Dex~RNH|CA^*3aJ)!-L=J0@^{Z3=F zXnrMV&uBrK(XR#cf_4VAd00R%YaIkVD4D?twn=xyzDf*uh)yr-p- z%|9w=A8K33%6}uEF>N=Nul$&Rjx+z;)Wzdv%B4^UUs}Hdf-kMD0)Ewk=drXz`TB^O zjPOQ#hU9reB<)FBpW3Sg?H7|K@66Nb6$|5kO{~5crd{e|jO{V)ucQ;4; zw8c=%KZ>YZspX#+0RLmF<--L1#A^8|f^K)Td|O1>O)Z~|y;r^?;^EzlQ>~v`EqmpA zBkFzB@)NZB?z38ciJ<$iI>)!y7K5_4Lb#pSER|mMZ@`qUK}q zYwzR&f7oj47(ox3ZD|tO??VFeYC1s=3n)>WM$jVy^06tY@~fP7jV`KeC?l&US93Fw%B zGPGyNmX8aFkMDzsay7b6e~sk#X~e?^`xOoLALjUya6j^$NZglLXIc^s@XCm}8Stp% zKO)>gxwKo+jC_@#`Gk}GuArrAZrXWw3tCXSgIwnx0hzJH)e-JG^RzuQvAu#;s{NXv zeF9phrP4n9Jpq+z-=lr_8Ua;mKPE@>eF4=7CwpzgM}w}*pcRL`nTHfVi1;YpN|f{- z;=d)5ObaL|={$`1p`gx}^zG!d4+?6Tr1N0mKLxc;()%d-x>fYnD(T!G{#V48go$-X z8MF>@L%_Y=A+tYOKLh>9cbfglI`?;Xnf=N7`=q9yoBhc;_jq@k{mB`${t(P3kVQNo zy6uuPXeA+PUra)JTwq6KJxt&e0^B9*b>!K8E5OTTojbZGBYb1LQr5qVhUKROb+@d~ zqqX}x0q&D^H#xVbg%Yoo^?on3hIZleuAiP32;o-w~?8@ zEx_Zl{`wq%?+9>Q))!Ibcg1K<$hwP!e?(Amr|u{4JpsBDy`Mz(z5u<7UO~J^O~ol0 zv^0Z?zM8P(5#KZ@xlGaDA^-bN!85Ap&(SJR!g<75xXa zmcJB(+pXyDl3)KyQ1>bNk4Vd33-DS+pF%2Pt$cm#SM9uFpe? z{sc)u5!AaC{WrAST>`vc(QhZes0#1_MK2&;x8QwH(Z`9`BdCum`ck5LTYdSM?-Ppt z7Bv+os3#QtO^V3l1;||b#Z);#fG(F_O<1o{P-gQh$HQ$@>pF8wTODy@}=`14)* z$JEpmQMu8jpH0;CR_?x9T>5?Flrsdi)unGE>eN;rMW7un{V)YN0h6lgX9Fu6qN5H~ z_mDAU3Tl_Ce}~L#ngDxLy^VtA=>i;3^)KfGoFTwrRsRDy+n{J_yQ;rVOE61J|9n;V zfHQF)iDkJI|e5!B07{YG-ZxdOaW)f@5w&Jy5mRo_71Yys|5^_e8P zJON&drfAG_M9ceCeJYl(Jh#bXRn-|B0_2KJ1qub^S%w4y6>v#B`!Spv(h}x*KB((EsO2+-Q+-s|XF_E1MnQc+*DoO| zp0CpJ#>={XE}eLvC8%%c`j5yaBLaL|*Y74BwF>Y(T~8ocwF&S;UEf1ZZ4yo4VfE?c z`q~9`T-QG!YKIW}3G?`ef(U*C@pEwlLHiAdZxAr~V-BAtU~*6#E*3DY91edWU{W}T zPZ2Qbl*7jaOp4*B%^%>1?-;|g?krr=fD-RN)+x0*m6X7%5S2gh9q^_GwjhW}3p|BoHzn{IdQ1< zQY51U<^#S;WZ-K-2EGnt;2TB;zFo+`w+|Wk4k82JKd=*kPeFhPJ|8mhO+yC0xyZn` z7#a8~k%8}YWZ*j+>k)kCA_LzpWZ>I_416~s1K)GlpTYMFK;U}}8TdZR;e4AQEbt8? z1K-8Sz;`t=@ZEw8e0L$E`5^<}^I)HXL14F;Dj7e^g)}AOSI7*>D2B{4C1XD%I9)Ps zLpDP)z7M1%8`seGBpYW#){1P5AaZfZ#_2$+vauYxb<4(kq;A>x3vAmf8#OSEB-t2- z_BGjf95h`vz6nF}$%a20Lz0cpfJ~8%AHfy+Wn%`WnJODEVJvB~@iC24Hilr6>9P@k zax&177vq$T^RYZLW#bEUG)*?zLl`a|jRasH$_j+<~6dh%|k=;fJ~GP0|uR_7|&ye zOmrEoFq%ZKkv5lW$c2eODooDb1m*GJxsj6`p#+K?f-h$v#J%#~4p6WH0k)$Q#JK%%B zF9ctjV%!D3G?!t3FHJR`17DikNQN@fJjQL%P@30h1|Ll57Vtqsd%-tFF`fe76qm68 zd{b289q>)T03m`Y9^(}BH^pn54Zd{AsGxN$8@GWkT`}GUU%JZ(gD+h*#=)2FHVp8k zdyLiKOZOTVfiFWc9z}n!fnR|yLovPtUxv$A2fhr|NFc~<6oN0qW3+)U!)sg%KG^u5 z!8cVlo&(=h#h8+X%w=o^-&EC@4!)^wqY8XeJ;pHjrh1JACjJ@D9RHG7n2Ks|M z4Ucg>_zbVnrSfHW)@*Locf+4#D#n{I;7pe>LYZpRP!*2>?Xyg;Q31UNCF2@&6qJqg zU?D-T@ei18j$|}owmC2&8JS|-gEn(q#!M`<9Jld23_r(f+zm%LOEMZ^$+KkRLoCo) zE~94_GFS+VZ3*@50rGf!&EFLvgm+@`NRO63eP~FDMU{F2ASzu7T z#x^jxCF3P9z~N0pO}ERqfil%N0tUC+_y7!UkI@eXx7Rp^A$cU@JutvEZi2`?F5?a` zcwp>c@VJeyz~J#1qhRoOr@aP48O61oO??%j^+?4e(c5M1U=T*O1VU$l&+{O{z*$h0 z9C!@o;tjll&$z&c_>2#Hjn9NY3c5-RdWn!2GOH3Z%+7P?(j0wIP*rpd@Pp0Tmo5W$_FHmnsz!`pkH==9RYk&Om=z zZ^$__UiF|EdR@d3UjcDT{Ynwaxx&n(A?YSSfgeF% zERcsiR|>RaU^0teR0v>)a)G1r1=6!rxt>%KSOSxf0uSh907YO?So~Kcx{H+`qtf)h zzz)nlF4Kx&8iD&@=Pd9LNi^^!lpqK0#CEO(Zp3t5fx93ZHIM*Hb_X_KG@ih8ECz32 zI)ok<*n)CAoBlmaz-;t7ZG;;A0ohF88i^V$a8aZCAPFUK3)ozNA0Wt71Mk70+<{r} zz#caJMf77fahp~F*#^4j5c7XwbaG$;j7|w0<0HBSWi{|iXwx0I2Hki9+t7_S(2O4A z0&_9R_&^87kPw*SrIj}o0!s>%pi3=q4LHaz+F&XO5ia3zdvvj+Dr|k zq0O|wtq|Rmz*0ynJ@5~VEhF$xv@M#x5_l}K}L zAuIW=JM{$sf6F_Fo}}FZ+6l}KBsS|}Sfg~d=orIA$8Izz+UpVRy#(}&NOO66y`qJ2 zWiD@UK!ETqvzE(XFA+^0Y>Cv_YR;wK{|>w?@5SHS}2eqC}R%Nyg6k0 ziv)5j5S>VQhu{XKQZbU7f%rZlpI3lf;!e5>ZM_b}p9z@;3kEVsNI%A+BjvS|l`e4? z6S5kJ3PO$x_7#NO0mKL)4?w`uQg;%K^Cv+3h>&+un@ip4gnST)UlZ~jST&H-3Hc%r z&lB>c0*;(R$fH2KhcrJQ_9UGm+RVF^7S$<&4X>OsdIUfJDB0{XF_ZZ|0c6s+@(kFG zv|LP_UY%Nol-~qOF`PcVeN!NvE}sJrKWyR(q(*tz!m?RkW0^?*P`ODxiYn6nGqHT; zJxGK9hsxD)4w~GGG;b;FSo%yLe*nadgnSa_E{zN1<3Jon66*L|<%Z^l#J(aVSH~AB zS4TCF6-YuIU#MIi=K-;ekX#*Ks9YU)072)bLLFbITpe!!@hTw~~#x>ybkB zbK&8rP7upMdQ**~+p?lFf&B&0_aPM%rKAg(KLC0fsbmDe`zRbiT6i&lh2O=;BC9PA zZ|f;n5^qQGpkXB5&O&NuA@P?G-&Ek!kxGca0EPKTbn$V`LP08}aUE5YF0jTGMwN1; zVxsVIZ2+_miH~atg>wj?_WuKg?+`%k--5ycB(wDjYQ2$KA5)W_w_3js74AVQCdy(O zZP)5VX)%rX+NGlsZ}n-=pF-lTzKOycNQ{*R@j;SiOMV6wN>`~#k{f(WFQt`omD)g? z?fi%10qjv{(q_s|ITPWGG*`_fNFw?{LSZBG->0<|GJ)5z$4Es2U`u9` z%Yne98}0s{a;@h5O`|pOf{Q!!`FD^DebEHsslAt6d|A$)O2EqkV9PGSjw?00k}yPe z07=?U4rJa<6Wkz>iE%J7q`U_q8|e&z zTn@xyLekq}(wPF;14I`g=g{mn3gkW@b|bOn9VCq+myeb=T_iziKfNJ4Pom)$xeAE% z7%Jb7bm|6@dy%V*kkaYwl#FELTNVCVnDk4qEghc2G4p9c^M6hg=~aY0jursuGl6|1 z!+wSPDs~F$GAY4qhHjjfeynj!DK)e7@8m2Klsew#uZfajHglYs!M!Y}l#;8RYEtf| z;Bu;xNffpumyGgrIZ3Ld#?K3KXfbd6*Cd$FS2rNp7WmW^( z#H%tv41EDL2By5nNwu%Ze3r9di#bSTj}%ia3gd7=AxwH*PP_-zOI`%!6jY&rkCnd# zh{y_k$W-qQS*`dlU=h49i9R^@Te4bo53r5kT1}j6*52u;aK0E0u}b@2$GGS5*_|)v z(crhDW;@b66;XwBfk564#4Us@BK2G-=e>cNp8;`->=ZS#5)c+4h3Df&OS(u- zrQlcDb6{uQI%@A?G3O@6pF0dCt$Mt4n~TCwp^|iiuKkH8Auzs}8B;W&nT1 z0)7^$TU(2qzH9yq<;2qgA#pkJ)l=C8*pm{)YAOArdzXmmdm8DyC}OFam(+*qj^20u=HIAj3Evg$4r1FgBym zfdo379#={SdVo@tJ=gAx(aPUIH?=}EsGQ_}DQYLzppd|3O`VM~{#4>lf^ju1fEI1qMSIenqULEpEJqS*`nhDT%G*pe z-7RrXv<5Yrk%XG=5y-QF=prOn)4c+D5fB#;lDoqD1o9vd2MEcR>iq)w7!Z#lg~&(e zV7}6J`Zz49`{7E876JQbkY7P6ngif76pkSY6*f`bYw6<|Dfeq)ptT)<_sl@zDqMg< zK2kAN<0_;Vy2D5dX>D`W(L1{9k+|ymQRqc-tf%P^_ay7-Wz=!5r>b;vOg9Kc1woYd zUkuK?2N5(%H%T)I*oBraMp|@PF)H9vTJa&>ENR75D7g;k>p=fL9|3lcbKoDBC6m^B zBzOtN_9IFA7oy(0>tQ57hv*#PUN9U&620|_-rfe{O{9?B8?_(}NZK)sg^z&u_)paN z3<+~?!pBcaaOVsv=By^t@jT1l2=x6x=Lxjz4U!Ru;98_YR=o{W63{U6C2&57HKZho zeAs**zDj1X zOh8EnNL7dc=&h5ITma{ya1H@Q01l#XfPm8gJc+`?NH7QLy&46j3?CGg^3MGjY7$a0 zVHeT}O4p)90VJ+f^t6yt{4%ZXQ7jHhid%8l{V|>~O3D<)&7@>0SMw(*nxU;pPnLY> zP|jfq38w;uDrOM@p{s-`+R}tm5|$*?`cIp>3_Gf7qSPqLElIV0dX2!7g)w;Xw=<}X z^OiI=8w~MN9BsgREo4MYoW-*wzm%Y&1GGjBXi1_jZ@d(G&|?r-H9jD`f}z%53Pf@i z8d`v=DZBuT-|Ub#fCPVEHImRg^)uBaDcY$CG_@#iAP?is zM4JXLpjsv`z>!Yl1+35MF^rHTO>~Ai1``aLW8`wCd1slUun{x;=$;STWXVpGW>2N2 za#SwKT$f~z&a5)4KspVfsu=FGxH@2J)P$HF0yCIGX9) z7zAcK4=tH})cQ@X`OZr472m#Cg3X1vkrZ5UvBczzJryw11r`DK&?w>oXb3Y3O+(fs z-CvQgCVhRv26Y`5S&_;@R{O;X5iEz6ktX$8!w97lBoboL~uji?C9 zr(q&oFi|{0z)5OjKXa;pI;?aeGI0x7HJN#kMO6!}zymvtgt40F{48PA76^gC;$}|` z!aP}lEm-v9=MnprQ9t$G5*fFW`W)xyB?5e1A zI%Pp5s&x8Dfcs*kEQryzrirXpoQUTnlCzo-#$QAuY5Y+;V~>%ciIlyhnz>t;gI zV0;zuh4WT~H{a?oA3x{30R3&vE{!nNc&O7bugOnZ(ST zJi^Q@9+=s0PqGh7<`MPH1Pvp>J}9H6qC^1vQh10;El#x< z`Pp{-ZfQE5ZzDJC1wx+;-tikM0jdyDW*@dGJ$mTNiA%BhI$7>W0axZW^h^c%^ntU zh8|$y45AE+Yz9Q^{G#?WNy;&v*ck0cD9uLY!2}5CqC_ zAZQY(BrKUnLA19D4l2z=a)?s`$*LW-A&HQb9PUrzC)-nEk$~)rVnVb`*(`WKI3mjG zkVNlPf@X+d^TZTeJ z8%Nn^+DJ!;XbHkGbxF1suhYvpvBi#&lF88a;?$f>PJ)ughFCaffMq4NqDEGf&932K zV-BS4(J^K=iu4a8ETgEVT7ck}0z57WaPzRAzY<0zfo2mFyBoDx%Tp$Rz zm(vG{PQ?eDbOIhT5hcVx!0(Y%#u=#iM<<B$I)PV@NatPN(V7>%8U& zdr%yXf>hkjLEaq|uR^lNzZ<~yP6PorA(`D#@m`b8$A3S7hn)xl9z!x2sQ8*m7vl#Y ztlJzgKz_**Q6&D45LY1`Kq3pGoMa6Lgp*Dx{Spbg1{(%&8jRK+}5F_Q(DT%2pHzf3K>9w2?1Xy~jAOr!HUc!X1^kTPR zX~ss7ZY*W+MxDyw2vUY6ecp>x`W!*hx5Ul6eS;>(oyjoc2!Q-@vr*(?hRf|$<#k}A z;fdg&Px61J8_eOwwUp75AK?Z8oOEfx!1Ga7z>6)Ek;{X-JFt@qRs$1n%0=K}`8uCj zb8=rtW-!s$Jqq0CNEC<)Uq{dhq?2xMUIp?aPB@*i8cYep+qaVnG(3e}ux}>_j_Xa7 z1xu5IWw(=Mx6Ohka79^~9V}NmS+2BMILE*I=mTXCNoDKyy7tbe;x;5NfoB4fN6>jl z2`1(YAae+DA(9qFZU8<=xKX6!7(Divy_tl*7|9<)+VkOsL?ps4q$wv8i8+I4mm+1H zOy4s`Eo2atf+yo&)SzZkslpXV)BZ)JJ;$l7RH||nQt*GOMh)_p3vNNpng3JGJ>%4> zkLqdA-~XmA)gzP1Vq6Q5ImF9l#iz^1X*O$FRtDSayMUy50SV*+n#l#CWAw`}Nv1_Y zTWaif8pS$;>1C)_iG<@CeDX`|ywrf$P6sF1PKip%!N&MDE|B(i${U2+6juu8;BnDX zUR+NZbuSzOmHs9Ol%aJf8s}eS`PL;ha2)P4U}~i0X=qR=pWGiH6o$ z4N(s#dkhWrEssHE>T+_A@lz0EJ;vR@Q0oX2@M&K6A{WTD7K-xwZS)$VQa3UivgCqS z+$C2I&?ErT8s(zw)D`U;FCjUEE=d-fn|)Fq0@1qA1E)lRjper2}TZ-^_QJdC<(!0lz3L;FoBK-Ois-VUb2r_#Ej3k{9x$u-H@t3XF{+U5<1G(p5;- zMKYyCbI7!i$Y&wZ7?vTGAz4=i3gq2rOdBnvna?!y17^P8%y*f2(9HjD==otNRbhiN zCM|t|$Jh8mbdms)RJn9PVNw3M{exQu&EHT2R**UbwJ%(UJu*U(C)53Kls3pH#bJuzMT6PJUv&aD8)a^MY{yVCRC`zV@Dx zj!xFTbYtK4fsGi)_JP69p`rfnj?PFZR8Uk<7%2%A6>bE)aiC{pOLyPU#`gZ+0@N;u z)-D+C@9!BZIJdj6xX5HHC@L%}EDRMEg%%bq*~sY|2Rl3PeexT-MW-8wb`1Uh((y!j zOq3fOdCd3Ux0Bv16-3&5i;E-e5ME&f-`v_c*w@xm&_y+fslBJaeJemHzP)#-dnmG{ zy&WJN7bf1`-?zDYOMcs6FHkPLjyT+b7Es3F8#TzA7PTRo;m+R3B%Oke1!4~nAo>~_ z9_;ShB3i=V#4!~(7~oxANmWx-uUk^%+=Xf)@+9O_+>(+I3<5V@oeo@LfrSn#JAy&b zRMnlWN^U>yt|ckj-t*Mn6hAH{PEz9o0q}vWM9_ee6;$Khc^nh(Zu&pUrz-IU%J8!3 z%Ibog>F8T|j0M$nG`+MyJ#(eHJ*XxZ0G&f4SEmQn(gM|2ph{WlROP>S26LvDIRDG8 zm@$7SW6b_km#k(epI%KsYN`u^b}PF+xE@Qgf!MMc`Tq!UE-V$)BneNU9s$)QTUuv@0m%IK-ibs}g7yYOZqKP88Dp zepPczSu?_q$GSP;v&ht5^_@3qrv$F1#V@7+KQ*j326i zvBH|vMG*W9NGe;=gX#?B98$}vu;Kp}_Mt8X%}X)}aWnMKQPXoV<3}$jP}7wMWTI@~ zf>sV+fVDLRT0lkRez0dNPhJ3fRsJBaMEPeZtL|BVdD9Rv#*@rhXQIC}$k9y-_bE+a z!lKJ@Pt6ZPwckU#)0KD7RkC|Iu%uNbI|wDHC2kF@=Pg6?pPf&36H=$Sl|+nqj=HW; zovoY;ZK0`k?hG`9dax`tm$wj7<5Gc_)LEj+G!#>_pxe}-nyU0*(Uqxb1~E+G6DNzJ zb*Q>$s;N9*U>nkG4xcdr-WW0~Zsf*GU2`MOS|-QE==@SFElWdbq@odNJq7~5L`oWg z*ibgrRFkXDFw~l2bq3jTj+)K8&QZk>vbhuE>Y8by8X)kuVPUFM;DtiqJ}_I7hKSE2 zxi5&7@KU#Ot_0aV4SgpmcfmVkE5E;hM7RhXhi=eC%>CT z6;CdZU2ziftB9rm)seh~$ry{UZno2G$aLOglbFsdtWq@bFHI+fFHT`PN%^XwJbfWq z&(F~dd;-cUwqCIei|}m|el?fIwUAr`S!$}^pXO2^{WmV;kUG;XVZvVJR%s>hGnGGG z7%U(OxRskFDb1f|F1(qhk3NmBf+Y6_w9RW}6_|Ar3)NCG^Eh{jSvQ+IKV!K%BOm*8 z7M4kt6s^4Ef2zFT|Fm*Y;`TW=OP!Vv=lMM>sXXNaEU88CrKF?EJ@J$s?LcrNud0i9?B$OxhOS%d%zDDJ{V4m7l?m z;6De+32WqTLnM0STRBr2V82`GfX`GiVee_~Ty8>3Q3kgWoXAYhDcSuE&WueIfl2@v zI0bxSjOPYTb~PKz?0;xMbpL<9g$aA{t11-W_q$wJL~lYFN@^-bE)4H_Spwcr{{BtE z6HeLf3Ysy;hAd7y!Fk+ds*>_8eCYt5x;bK(k9hMuwu~kGg@PKtY1F4-;k-|lfH>2i ziY+rqIY(0bBu3>DY_gfk7Z(H(@sROS6qW>w5sPys;8Zm@A1a_Cse)G_^H;vaNFZ^I zx3jIlS~<#JW4p>g2RxwqUp9{>KSs-$%6Bg;;6?!`SNU^nqx1jI8-0s6dZXDWAUQQg zmiJ=Mx3*AjZalb2T?B)l$ptAX+YsU*xW?qOc_>ssM#zIy+G!R8LcB^vZk;w^i6Fq& z;9j59JQ`MZ4Rm_i-Ky6vSXPVp#5Y4xua6IvO`j*6sV`=s0{_`T2xwy zdjfs2x-3`KDX7R&b@!CHv>ro#6ft-#%oOC(_D^`j zmGkkv9)Cy)RGhog%nP}?$)jT1Tc%12WHqL#ac*EdB;@8uilhY zswt_(@D}sXQK6rQGXF+eE8*GC3aSY-%`7tAId0`VNnKf>R)y5GQill1Q`IOVE7cS( zWo0m^P6?`~Wn0oCx~^|FT4EINBn(LYyYnfTQqrIcu{PDPf!T!zNJ)M!B{&QJfWkX~A z8n!l4-ViBlTvAxbwub8(!mA?ngTriVbyGvAsGb_DuB%!fZm6#Z{bXclGGx(Y$l}S6 zC6gf+PKI1G8FI1tQ+oWz|LXeB<-h1h)7}Chb>JudhUmut`Po2ZXk=iZXGf%c^A@(X zYJE#2T(^p5S6^Pcn#ycVb45*aq_Jj01V3_7XUU?uqr2Y{QR(7^tTG&~Ut1n#)pg~~ zHBI1auBrpQvZ|`FxegyB$)bfUQi0lx75~GH3`ATpoG|CP(tW2D2QBWw6-579gd$JoaBcJEBWy8Wi6(fx$2$$ zha4DF>kf>matFrLw*ymxx4`N`Lb?tOSo5x}j8s-PG4U&h?er^;k@kU+NLyb=WHbMv z$BG8j2v>$9wW}d1QWF1Yu3Ft(Wz96)HZ;&V2sNRa_+iM#riSX;x~fQhRb}m(de+oj z)wH$>U#eq@rn;wdd$_;1*S3BOaZ(LTQApFOVT;#7z?x%gz>;GTu;N(6Vm4A*TNPg4 z-4|{f2)Fet8mMNq4dI5>k(M0;oeVOmZ7y#zEA@{Ii&~|q)zVZRt}+eqU;HxW1iM^_ zIW|@{tyv8%M;a?5>s!j}ii=iFhOB4hH5F)_3m979Cu@<;zP3%!N+Fww39+g(YM>R? z-G-S&wwKUqDg=LJ?OL|gT4H3;&6Twce7W^(v%FaEHfv#+wjm_c+&)~$YQt4cmdGl* zx7CO7muAfynpOCv0#XW8`ofZY@i$Go-p&x^uwF08{0QEwhcmd1J#l3_=!xm zwV^qTsndu|Um2Zmb5%?1n9Uld=4yr_bwdN)+?MMrtHKjkKb(YF69XpqL1V_LBE~b! zhRE}B3$NrS!Hj!z6BX(0$HA{-Xi?9Lg;N-5scLR%ZYjs;qNBH}z&KAv!az?(!bnd> zV$3Ha7qN0UDdFNQy9w999d)%0cAVRWa$N5h&HR#V;F#449=G>_&tT1WGAByJteN6Q6;8_h%Gjn)zEM*B#XelwMy zq;IUj$lEq`lN+yXUKguoOO#ln=E@-R5c8V6=3-X0y1cfbvSJ0!A`n{92vfI&hjm*%*xNFQg^MEJ zOA7gCh>>pBG(*X;Ezovj_p#m-e8b4FC3*6CVB+3%ZA$}O8X_rkt47D%AvRVL8FICP zINMc{V7O6Pz9WJ#4iBM*D6r|nPXc%Ljr5A}i0`&kKNbw(X?jDrsu_!`p=mXKM0xe< z)l952ieKz5Z9^575*}=i(xS`S9-wf{c-_ zL_=OK66xq3;#+I?AbwA}J}fqW@$4$nJrL<@>+Qs^47ZSXA$>u^AzF<>h0%EwIplFewWwqwh7wCCu&#L;_+qx%wvjPU2X_MA%`BPekUp#=A0u!cs8h!9KFm$x)F;n%Ye zf>J0RYAl3(nYXQYG}?mp8YpTeYUqk|q79I?TPYwyL(04Mchd%(zI1 za>YP5wyVx|dvO*{h@dGpwjCvfS0~^8k{fSoL1gLp>3HYwzVq8jelN*?HlE-1a?ff; zg4SkMU&+ih+BQ7g*4`EA?qIk{fsd_XtLtl^=?as+z(Z!gW=qHy$Z%7;2}xjs8Bou`nFn2WZSJ(z(5Rcw1-taQ~pa?>Tf$cN&<7 z8DU!?6rCP$G1^-RUoUo8i+vd5slgtx4R2xK@p*rw>pUyCS&X=vf)Ct3ujhiYEsNrL z-11W_Ix-M}b?|_6Rn>+_1??-AS=D#f6!2 zNw@FtOn9+V0kL-y2rlT(v3d}{jAb?&McLzuqU@nXQTFJfs1jHk_LP$vvrPFcF?^e;&g=R{D>;lNQyRBF5RQSitPJjbGC?eM~3T1Cd7AScT0-u zEsMo1B84?AoM27xQ{gV`xhpz{*Wy*3ZXBG1%Nwn&S6DSGU$Z{K{W-12QY=SW zNM`)c+neM7qOM_`xGfDWs^_<*wVmyC{cRmqkjMi;asjxB#+^RhMGpw)Wu5QYH|$mf zW-s4xGvWf=E>WNrF(WOy!|p%VJouwqOL6vv8JLkLU&*HAXaloNj({SELiioAuzDgz zEn>L4eJgI#n@+EzyHZi3>b$NtM|l%&U|juE9vOo zCgMHEO0-ueMPGcEutHP1jfUS`4_{mFm_ODU`BsRP;zd&uCS(c>%K+bNP497OSogSJ$m+uCb$d>Xh&MI9xKl2MqlhoI8Utf?hz?rc^MxJ{WbeK-?Zqo(Bfh%8Gf zU(-VOge%Hhsv6c-H8s^%Ryj64D5JIsfi}Obs3>2(3MUN}*qp6xnNeFU2&C4w^^9~D z#)3EnYp8@b4X|Y*@FtxxBinWdk=%Za!p~mZ%y> zHZweHKtKiUSvSws{e$hDYs?^%;WfpPo?(8r!q3Pn)>KzRNvl^N9xPhhSP`;2MUc)9 z=qyio@&R2m1i*T&jMUfTZo^)cq{_OObF^A|?{9NkJC4sRPhr`Ksp`gU!>nc0@3 zYL2OS$58vQ{g|MdA9BN#p?0$Z)@X=!NE57S8|n%V?id)R16WL9xU-M^i8&2xQ-~hX zSo^Y=#6&vGdm;+6nusbn8HJE%Vl4z06H&Myz>O^JgCV$t>hd*pEw=vQo?{MZ8&5i* zU4d|-v3bMlFdORX9~=(acQSOaHPNsNne#R$YM$_o=6>z)rBEuxET%{i3_-v+s)>4a zdUiB0$tgwboqeRT(K^&J{dY{ib}Z{S-m_0vqK9k(1+Oy^1?5acK{*pqP)-zO>7ACD zz0T>*3!8z{2T#Vcm;x(0o}pcX-@}>msi-Z&t*ZmDJtR?V4@rQ%BnT*pZg0Z+L~uYP zI}jxRA*i76M`T3|O9J=v^d@weUfhkL;`tHXr9|jRKeVW~>pa|^v~6nZ+e&_rjT9F( zb#8$>gj%o}TI+AZT~|X(O;uB~)ofGW77~qlUn=&dNg}tJ+7;MZYH$xH?z6DtSRpCg zXZ_mhCh-~KW%E21g2#C*?4Z7?-W)hixYmkCwQ!tto9l?N;D+r07$;A5*%onAe=qNz zjF+^;ZwI6G*4smZbB!@Ya!3>#;4v@8w4{)=@dIG)HQ+?H44JxbT-Ov`#dKc~17S>D z_?Uw&e=c{&J#-}=wnlH8d;0sf1ZlZC7M~rkHsBc!9&HX<;|jq)B21uN&3yDk+ccv8 z+DeQ{m`GjoK(}p+1lYDnfGsEjY+ED%t0dY0oL3aEO_8cCrue6>VFeEX`AK#2x~2$M zL=44R?xLCK-PA%B8w*Add%!5yH`v>BbaS%SDyC!YR~8DBnux;GCZaIGi6~5SA_|k8 zh{BX7qG<8g()P+NB(#X47*T|urply>&h7l~5+a)i`+Fk;9oAeo!;0xH-O@3t(l%;M z2J?gY(f!5*0%kcm0dt+4fEiCtz`Q3XVD^&}AcM&Xcp3|X4~_DpP(~{Z8B!ZDFPV_ zqhJZS8BCh1trpLrwzc)(fXqZ--IRB2qTps7KRw`Q2VzMz4O>2dMvNzpvHq-Swe5b3 z;C{{a=yYPJ2VRt>N8v7?Ee!~#kk*i@>dGDEir98>a<{eu0k0*w#fA1Wc3J>%UDgvm z-gLN*Todk6@N5Q8qs#F&LL(2DvF3SDZjB5x#j|XhDOFx=)i%ey?%WP|NXP3C7%{o{ z=5U3$4>Pq_%sa)i%?QpBgwJhZVS0LiRzr59eEL{`wxbnKMVs(vOZ+HDl)J2)1x{%5W1Qo)45mIx*+4=8aEebN`_A04SE7AE<~U z3_e*?LUcw}TQp>Anmq1cf7fP`C{35w_C%XnU(MU;i=Z!=VsE;KuE=0#TQfQjE7+XltY;RE1603E{@hK`V-ZV)-y6hfR@~ zCL$=vhFN)WF9yX7H16RQzrZLp`6SO=h|UTcMfH}GpMvISUmKkwIf1j-0{{# zDyqtHYUl8*mgL0p!FjEy%pVC>t!5qlBY5W|)= zeDd<UV#S=I6bms`48ROo}vs!cc2`h`ScD}^u?FEWktar_5$FFb0=?=zd zJrcAw8#-n+pR>oD$T;6&fyzT>0P9=>u=&QGopv0`bds&Ay1q4?<}xj-_l zn4Z=<&ndaHs;t66T2-VLU!qRJvJXkkMQ2A?CX962Dj( z$9p!*=}jRZhP!YQio9*Gy=yr-*jAd~ThQCq-8ZjeXkgyvfnffYV1C0;Fdu(_xx5`i z%-`JCpO3$4?d|VFxfky`v~B6k@9FH@GTgPiP>?r`boUH*6Wuyk%^$)ODLP;UuA^Do^t#250k+*NnAE7=RcDAmAZ`%AehJVDIK{$_>`LlR) zp<%^Xd$4ejFx^cix7c1iIR30Hudq+<5RPIc3j;3aPfW?7t*fMmD|{_jtA_Gu ztYMinWD<&ob_jd$e3)J}v5twY^CpD1=6Mq>qUN5qZBDgD-G>Mko14Rk!%5y$B9}t% zW8wh}J^U0eWWv*%uLif^d24iF;`DoDs1xV=;_r?l10y{>BLf}%=i;Gn3tVwjilVZ4 zh6zc~<1lCN#5GPsuuQPNt-EJa|8`~_7*kW$lN&SIa5Qgjy0xoumfS)P0SH?Uw$%Ba zVgDys38 zu6f&BhOBJP966^R454|o+%bYt8J6w;^37N!6MiOE}cm_A|^w+v+ z!SPNtUhu_|fTO5wSj}Y_jd@P~O91}v7=NF)ueaNL!xtyFYpnReK8T9GOhWb$T@vPw zhZi-h*I4Nld&GFvwJRuyqnnuse<9y`S;2gqN-N%st`_rQ;*cLgn1)%Mf4EQ)-9HqGjPEo$133O$l}F>VS1mNtq6yg2J>hqZlNz|2;ycah?fn6 zRd`a^(SbL08pW%9{ewfnCHb^R=bux8jq~jO!8!kLHg5X%0s3l_uW{kaU(VMOlQ>Lx zx@IC}@RImAfGn&f?!q5;(O2WeeDw!?ZAZD5@h$f*^%B>m%4Jl8+O{tGIu9ot1e{|L zDMy19TE;H-CF-TF%aqH(U!kp+&(Sb|`Hp(@H7^xf&aSviyq9_|b6>80+jWKV9n=nM z*Glq@8nx-HPv5&xp#^t&FY#RJzD&K`^=;(})GpUrO2T=&0+(ZrUh?gyy&u`eqErrQmBZ zk{vL8xe|T*6!k$iBh%MrI4%WWoe^7KWphEN`Uj9?(5sPKU;Toa0*YP=zDpyP-_2@4 zCVt|PK_`Ctsv2>T)}oh!FRF><_p)z*O#Gxz8Fbyu}$>C5A9CikLUHHYlFVX zCweLPmcQ8k5_tVFy9!xd^io*Tg!)OmK7A*hxRR^_&lUX8L2Uavum7Q4AHUn>xD?cm zt)Dz${IOI8U+EQ#NpZABUzy{dK=+rrA?@x#_LD*&3~)N=27q+;j#Uv z^ZI#q4g7qF<5J+IV(Vw{`VZK3qM9OPKfv1cl)j!yK1_)pMZ(#x>)*(Md*R9rVS;1k*}O!M_|6ruCEp z`&eee2RWR^)|+r4htpY~2|vo=40eSH2RRJ+$NZrNUhd7oSElmwAM0%g>m@`x#Gr@w zu}@oAPKWalsLuXlKr1RCmdTDFC*F<-7>~JdZ-UbXv(Yg9Jz98Rq`a>~Jg1-V*h?HZ znJ-8Aw*KrWbT*dHn~iOu?cCpL@pDV%*eITlX|1XXRVikS?F2Zns1LiaUh1{ zQe1;y<8I8tpD`C7qW&6$_V0wXuo1S#KpcjV7=!Vszhhl&cy`OA8XdSX}AZEVIKCA2d1`LjH_`I?!v?P6JEs! zSgf?QP6e!i-q;df!+!Vih%K-S4#ZJ71!HkJ z>hJsNc(-8|p2HhhfcA1gsO@W@KX$<07=q*Q1N;bA;YQqv*?0-_@F|v+7j*6aC2WW- zu`Bk+;W!Cr;|kn>>G%Vl!K;{$c5*DD{a3=;=!fm`bsU5dI2GsPC%7KJ#e;YnuiyhL zE^niB98Tzt`a8v%Z-+fG7)N6?eu#;<4!2__p28fwkHzH8z4liTYoRadPYvt(9yk#7 zw}dr61!HkJrr`KjLqA5A^^~*H^%rsJ{oS`8L=c^>=_ZACB+gJY0rf;8y$| zPvWn57oTByIgr)*HBf(BR^!d23%I2q^S$C!-Y;C?)Tmr;MVR{QxI%gNhejor{2 zTVWs$z!4aQb1(td;uhS8*?0-_aFM*d*8cUEc-1uAjv2Tg58*L9h3D`xUc=jX9}Dnr zEFlN{+HV=Gh*i-I>tF-)#irOAJ76FNVSgNq!!QCPF&bkq7UOXleu~Ms5x3wD+>1Zp zF+7bIFb8kqJuJXySjyG9zsjLAzJztq3;nP;w!_ZY1N-3HI21?XIE=z+I2#w>68r>{ za2)w;T_D!$5^~3 zk0Y#z)vzYkLm%|VR`@D*#a{R(4#F@TjT3MR&cJ!N5I@FMxE8;}&6tjR@E{(=Q+OVK z!y9-P|HQwsWG(A{DvOoT6>DPyY>dsYEq220_y)d(AvglZ;v{?@XW@KYjET4!Q*aY* z#a*}`4`Vj|gctED-o^*`7Z!83?jHxNjP=n6n_vrUhn=t+2H~3+jG;IZ$Kphc#u+#l z<8TQk;%B%HQ}H`IfJZPJ&)^084X{pxC9e%HSWMYn2A|<5-;Li`~#n0 z@w(g(u{=7XE4pKS^g(~@jNP#}_Qyf^4u<16jKWx4hzYm?lQ0ESaSNv7cX$AgU^bq? z3-}ve$2`o(zfiyC($~jQSQaax3)VyrY>0l?4BKEw?5@5nUlpm%Em2^RCT_E%1o`c7Dtd>!KY=uN&kacc}9--9>^`;i|?JPb#Xk0Or7 z>Ess>$72HdB;sV;Kz8f0R7RIrDvD(67`J8+TZX~~zI34$4CZ1KLpI=m|bCY}?J|JJp%i4b# ztc=yrLzOySs?=#kz8!WX--9>^-@-vS97ka!PR5z4^fOPDeiF&A!ZqYGi1*@QJc_4O zsdG`4{e2rBp?yPZzB<-Ne+s z_;<`FZ;|I}ty2O^tFnDnh^u2w@(qc7u_^fgwWP(;i+CXGhhP}_i8vRRViIn`U3e7F zVJ_xlF(2!A%cC1M#OBx?`>XPr8%jJ%m1Dvw#B)^HA0Ofp)-T6Y@@cq}{2t84(|Apl zdN=W&D*N}5D)0Rq8d+m!Rob~=4f0;Zjj##%cElaPMm?6s%*~@RUT*O$zQ_jcpLAj((W(fztLWv<8(hbqBFW+ZLEiWs`UGc zD)qXM?}oj|4#Br#+TcrJW108`dV@i1=k}M!o}a7wk?x7)O$iz<0?{BaXqj8be~S1l{zCo+@g2NR-cF9SwciS=^ivsK$a@es zz((X-61PP;>5Eb4b>cU$KlyivN8or>wsVpy`*SY&`M4C9;~G`kr>N5YTk^Z`03O1l zsxZe*?^vA7`lOs?PFMwNs?x5mD%;_QEm_|dyI?o$gZ(iC!*HA`btkG)H-`Ki zoKHSMm3B$0?2lwj#WdW3yRn2t+RJ@K4si@CU}coUEF&*36NYj%Lm7%;5cb7^I0T2| zD4dS7FcDYb7Tk_MsdCJ59`CDitosK(Mg37s&FfEus%5b%y5h@d%x9B!ItNtS2jFYi z9pAt=aWsy@D2&G07>lcMEq;k#;SSu52k;PH!W_JZ53zD_>-ei-J@mpZ*bN6@Fiyc~ zxB%mEBO3GWWIydCK7gmun13hhZxZLBG5=2T_IB2BRz+8=jrFhtcEO(58wX%8zN^Y> z`y_lHXW)EXh->f*OvN<(0kiNVp21)6SG3GVZ6IMZY^gwTHj9suB4!~fH z#t+b#4=DXDBHo0XaSwivm+=bT$3L)=yqD1NS4B_s#x@v$#{5HR-;a1Wj>73U3m4va@T!t%f4Ss<; za5o;uAMpm>K|6cvce*oQsPv0av0i|5Gk+AU5WK z%H^%Z>9`*c;(5G;xp)ij;~!YIv~~YfL>F|!y6A~*@l_1Op4b-$U<8iGX#4;ZFcCk; z6g;TPW9JB-z|(jMbMPkSVF5ltyE4{#_UMFFu)gYUu{6Zi*dBwhFOF8_ecU*V!f1@a zIT(*iF%{GBTik{F@gN?>6L=0U;-B~!jd`vzK1WCEIBR1)Y>92LJNCj548ut{1?S^J zT#ajS8}7g?JdT&~3hFVl?$1(K4PQcEY=SMZEgJJ><@(XYbMQl4hAZ$3H0IOF^|ll5 z#2+vV&)_*U=G)5kZV?yY6SOa9-5y7DK{xb7Z)}FG(3qbq^#h6D#J6z-8uNCgT@-ON z8uNE0zkoOqSK&I`i0PPtzoId(SL)m$zK4(T8I~$<-Cq4SD0(|OVHI>kcQob$OFM63 ze{7B+7={rz9;aapF2p6c8rNbPZpD3=i6_yRPb}lgAgj4(8$m{1eN` zdo&%76V^j7Y>url2>aqd9D*Y;0%zeoT!>3>C9cNpXv}+-aqT0{#AA38i#b`xUlJ># zGuFZS*c@A9FYJS(a4gQl1-K43;$b|Bd3YbIRI-k*IvVq!WxF~OkH&Gh99QCgH0C|a z_40`CV+na(9gTV6Qs*G?Q8ea>OWv3tEe*oQogfVob*M_%(imNAMV)#-H&j-oS_W2rIi- zx4#8Hy5xP>Zx1*r0T)m4?(&mh&^ z`tN1+`??T~_5HFcMaHY%7R!68uf;M$eOdme%KcwHMlf_hNg1(pZ75wEx~r1(Kq+m+ zKIn%{F#tPZSL}g7*cU@o=`0LKVgwrFm+gOFV{rz~##oHQL^M99l=ex)$+#XL8z6<9ljZ+21%rttj8~VXP{*R~#-twsUWSwr$R8_Xa_&i6(-%H;&%ec2mTOF^n9_PzA8>uor z?0)lrWZWjqU28OLm?sr^eyOYzp$bKYqG9>j7LV;lj*omA-~gg8u<8smv4s#0tQ z@oZJbxt=&xmGK()OX<(NUpnaaOI%iUmvIogsj?jnh<#Mqo)*MyR2gJ2afmA07eQ>? zUt~Lt+g<7#x4S;C_(o0{GjV9BIB|m2k>({imES~*ubwc^;u{(nY4O#B?~BjCU|sjW zorl3!PA6z>WpiSK!qYMQv-V##UUXsx+ak}Me&L@wHog3F=Fb#CdZ8t#TB(srNg3Dt?+jjaow2F0# z*>03vmZv&Pfc)vwNuF5b=|`tM8T&xn>G)O^!&;sU-MLWS#UK-ifd*7y>ymS=S)9*e1RZk8W-LwFU zIlit%+NDW5J+?F#a|pwWv`d#pv&}}LSx?UoVmrP#8J~l!*V|3rf)2}>NQty-`-6d}>=5~~m9Vtx)bq))SZ2t2t>-R(=62|LV9e`C+EQbn%;B<0m=^e$p9 zQlwtVL9(Cq0nB37)AP>QZttpV*7rDC&qMyq@r|aQd0)yJW3lYz{g0N^diobtq}_tm z@)^1|U@_axDl$HYBp0}Es}Qf)H7aE#*(~7=J=X{ zsQv1qO4GvSvb5VPMfCNeo&0G%-A%erq+a2Ylwz^0F^fpnyyzsCZQGT&F0UUp9hmL@ E3$8r%egFUf literal 0 HcmV?d00001 diff --git a/source/hic_hal/nxp/lpc55xx/gcc/lpc55xx.ld b/source/hic_hal/nxp/lpc55xx/gcc/lpc55xx.ld new file mode 100644 index 000000000..14ba2f409 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/gcc/lpc55xx.ld @@ -0,0 +1,231 @@ +/** + * @file lpc55xx.ld + * @brief + * + * DAPLink Interface Firmware + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * Copyright (c) 2019-2020, ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "daplink_addr.h" + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = DAPLINK_ROM_APP_START, LENGTH = 0x400 + m_text (RX) : ORIGIN = DAPLINK_ROM_APP_START + 0x400, LENGTH = DAPLINK_ROM_APP_SIZE - 0x400 + m_cfgrom (RW) : ORIGIN = DAPLINK_ROM_CONFIG_USER_START, LENGTH = DAPLINK_ROM_CONFIG_USER_SIZE + m_data (RW) : ORIGIN = DAPLINK_RAM_APP_START, LENGTH = DAPLINK_RAM_APP_SIZE + m_cfgram (RW) : ORIGIN = DAPLINK_RAM_SHARED_START, LENGTH = DAPLINK_RAM_SHARED_SIZE + m_usb_ram (RW) : ORIGIN = DAPLINK_USB_RAM_START, LENGTH = DAPLINK_USB_RAM_SIZE +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + FILL(0xffffffff) + . = ALIGN(4); + . += LENGTH(m_interrupts) - (. - ORIGIN(m_interrupts)); /* pad out to end of m_interrupts */ + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + + /* fill .text out to the end of the app */ + .fill __DATA_END : + { + FILL(0xffffffff) + . = ALIGN(4); + . += DAPLINK_ROM_APP_START + DAPLINK_ROM_APP_SIZE - __DATA_END - 4; + /* Need some contents in this section or it won't be copied to bin or hex. The CRC will + * be placed here by post_build_script.py. */ + LONG(0x55555555) + } > m_text + + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + .cfgrom (NOLOAD) : + { + *(cfgrom) + } > m_cfgrom + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + .cfgram (NOLOAD) : + { + *(cfgram) + } > m_cfgram + + .usbram (NOLOAD) : + { + . = ALIGN(4); + *(.usbram) + . = ALIGN(4); + } > m_usb_ram + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region overflowed with stack and heap") +} + diff --git a/source/hic_hal/nxp/lpc55xx/gcc/startup_LPC55S69_cm33_core0.S b/source/hic_hal/nxp/lpc55xx/gcc/startup_LPC55S69_cm33_core0.S new file mode 100644 index 000000000..e5bea755b --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/gcc/startup_LPC55S69_cm33_core0.S @@ -0,0 +1,888 @@ +/* --------------------------------------------------------------------------------------- + * @file: startup_LPC55S69_cm33_core0.s + * @purpose: CMSIS Cortex-M33 Core Device Startup File for the LPC55S69_cm33_core0 + * @version: 1.1 + * @date: 2019-5-16 + * ---------------------------------------------------------------------------------------*/ +/* + * Copyright 1997-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + + .syntax unified + .arch armv8-m.main + .eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */ + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector + +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long SecureFault_Handler /* Secure Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ + .long DMA0_IRQHandler /* DMA0 controller */ + .long GINT0_IRQHandler /* GPIO group 0 */ + .long GINT1_IRQHandler /* GPIO group 1 */ + .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ + .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ + .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ + .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ + .long UTICK0_IRQHandler /* Micro-tick Timer */ + .long MRT0_IRQHandler /* Multi-rate timer */ + .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ + .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ + .long SCT0_IRQHandler /* SCTimer/PWM */ + .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ + .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long ADC0_IRQHandler /* ADC0 */ + .long Reserved39_IRQHandler /* Reserved interrupt */ + .long ACMP_IRQHandler /* ACMP interrupts */ + .long Reserved41_IRQHandler /* Reserved interrupt */ + .long Reserved42_IRQHandler /* Reserved interrupt */ + .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ + .long USB0_IRQHandler /* USB device */ + .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ + .long Reserved46_IRQHandler /* Reserved interrupt */ + .long MAILBOX_IRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */ + .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ + .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ + .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ + .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ + .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ + .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ + .long OS_EVENT_IRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ + .long Reserved55_IRQHandler /* Reserved interrupt */ + .long Reserved56_IRQHandler /* Reserved interrupt */ + .long Reserved57_IRQHandler /* Reserved interrupt */ + .long SDIO_IRQHandler /* SD/MMC */ + .long Reserved59_IRQHandler /* Reserved interrupt */ + .long Reserved60_IRQHandler /* Reserved interrupt */ + .long Reserved61_IRQHandler /* Reserved interrupt */ + .long USB1_PHY_IRQHandler /* USB1_PHY */ + .long USB1_IRQHandler /* USB1 interrupt */ + .long USB1_NEEDCLK_IRQHandler /* USB1 activity */ + .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ + .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ + .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ + .long PLU_IRQHandler /* PLU interrupt */ + .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ + .long HASHCRYPT_IRQHandler /* HASHCRYPT interrupt */ + .long CASER_IRQHandler /* CASPER interrupt */ + .long PUF_IRQHandler /* PUF interrupt */ + .long PQ_IRQHandler /* PQ interrupt */ + .long DMA1_IRQHandler /* DMA1 interrupt */ + .long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ + .size __isr_vector, . - __isr_vector + + .text + .thumb + +/* Reset Handler */ + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + ldr r0, =__StackLimit + msr msplim, r0 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + +/* Add stack / heap initializaiton */ + movs r0, 0 + ldr r1, =__HeapBase + ldr r2, =__HeapLimit +.LC3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC3 + + ldr r1, =__StackLimit + ldr r2, =__StackTop +.LC4: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC4 +/*End of stack / heap initializaiton */ + cpsie i /* Unmask interrupts */ + +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + +// Alternate init code from DFP: +// cpsid i /* mask interrupts */ +// ldr r0, =__StackLimit +// msr msplim, r0 +// ldr r0,=SystemInit +// blx r0 +// cpsie i /* Unmask interrupts */ +// ldr r0,=__main +// bx r0 + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + .align 1 + .thumb_func + .weak WDT_BOD_IRQHandler + .type WDT_BOD_IRQHandler, %function +WDT_BOD_IRQHandler: + ldr r0,=WDT_BOD_DriverIRQHandler + bx r0 + .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler + + .align 1 + .thumb_func + .weak DMA0_IRQHandler + .type DMA0_IRQHandler, %function +DMA0_IRQHandler: + ldr r0,=DMA0_DriverIRQHandler + bx r0 + .size DMA0_IRQHandler, . - DMA0_IRQHandler + + .align 1 + .thumb_func + .weak GINT0_IRQHandler + .type GINT0_IRQHandler, %function +GINT0_IRQHandler: + ldr r0,=GINT0_DriverIRQHandler + bx r0 + .size GINT0_IRQHandler, . - GINT0_IRQHandler + + .align 1 + .thumb_func + .weak GINT1_IRQHandler + .type GINT1_IRQHandler, %function +GINT1_IRQHandler: + ldr r0,=GINT1_DriverIRQHandler + bx r0 + .size GINT1_IRQHandler, . - GINT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT0_IRQHandler + .type PIN_INT0_IRQHandler, %function +PIN_INT0_IRQHandler: + ldr r0,=PIN_INT0_DriverIRQHandler + bx r0 + .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT1_IRQHandler + .type PIN_INT1_IRQHandler, %function +PIN_INT1_IRQHandler: + ldr r0,=PIN_INT1_DriverIRQHandler + bx r0 + .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT2_IRQHandler + .type PIN_INT2_IRQHandler, %function +PIN_INT2_IRQHandler: + ldr r0,=PIN_INT2_DriverIRQHandler + bx r0 + .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT3_IRQHandler + .type PIN_INT3_IRQHandler, %function +PIN_INT3_IRQHandler: + ldr r0,=PIN_INT3_DriverIRQHandler + bx r0 + .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler + + .align 1 + .thumb_func + .weak UTICK0_IRQHandler + .type UTICK0_IRQHandler, %function +UTICK0_IRQHandler: + ldr r0,=UTICK0_DriverIRQHandler + bx r0 + .size UTICK0_IRQHandler, . - UTICK0_IRQHandler + + .align 1 + .thumb_func + .weak MRT0_IRQHandler + .type MRT0_IRQHandler, %function +MRT0_IRQHandler: + ldr r0,=MRT0_DriverIRQHandler + bx r0 + .size MRT0_IRQHandler, . - MRT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER0_IRQHandler + .type CTIMER0_IRQHandler, %function +CTIMER0_IRQHandler: + ldr r0,=CTIMER0_DriverIRQHandler + bx r0 + .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER1_IRQHandler + .type CTIMER1_IRQHandler, %function +CTIMER1_IRQHandler: + ldr r0,=CTIMER1_DriverIRQHandler + bx r0 + .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler + + .align 1 + .thumb_func + .weak SCT0_IRQHandler + .type SCT0_IRQHandler, %function +SCT0_IRQHandler: + ldr r0,=SCT0_DriverIRQHandler + bx r0 + .size SCT0_IRQHandler, . - SCT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER3_IRQHandler + .type CTIMER3_IRQHandler, %function +CTIMER3_IRQHandler: + ldr r0,=CTIMER3_DriverIRQHandler + bx r0 + .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM0_IRQHandler + .type FLEXCOMM0_IRQHandler, %function +FLEXCOMM0_IRQHandler: + ldr r0,=FLEXCOMM0_DriverIRQHandler + bx r0 + .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM1_IRQHandler + .type FLEXCOMM1_IRQHandler, %function +FLEXCOMM1_IRQHandler: + ldr r0,=FLEXCOMM1_DriverIRQHandler + bx r0 + .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM2_IRQHandler + .type FLEXCOMM2_IRQHandler, %function +FLEXCOMM2_IRQHandler: + ldr r0,=FLEXCOMM2_DriverIRQHandler + bx r0 + .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM3_IRQHandler + .type FLEXCOMM3_IRQHandler, %function +FLEXCOMM3_IRQHandler: + ldr r0,=FLEXCOMM3_DriverIRQHandler + bx r0 + .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM4_IRQHandler + .type FLEXCOMM4_IRQHandler, %function +FLEXCOMM4_IRQHandler: + ldr r0,=FLEXCOMM4_DriverIRQHandler + bx r0 + .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM5_IRQHandler + .type FLEXCOMM5_IRQHandler, %function +FLEXCOMM5_IRQHandler: + ldr r0,=FLEXCOMM5_DriverIRQHandler + bx r0 + .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM6_IRQHandler + .type FLEXCOMM6_IRQHandler, %function +FLEXCOMM6_IRQHandler: + ldr r0,=FLEXCOMM6_DriverIRQHandler + bx r0 + .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM7_IRQHandler + .type FLEXCOMM7_IRQHandler, %function +FLEXCOMM7_IRQHandler: + ldr r0,=FLEXCOMM7_DriverIRQHandler + bx r0 + .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler + + .align 1 + .thumb_func + .weak ADC0_IRQHandler + .type ADC0_IRQHandler, %function +ADC0_IRQHandler: + ldr r0,=ADC0_DriverIRQHandler + bx r0 + .size ADC0_IRQHandler, . - ADC0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved39_IRQHandler + .type Reserved39_IRQHandler, %function +Reserved39_IRQHandler: + ldr r0,=Reserved39_DriverIRQHandler + bx r0 + .size Reserved39_IRQHandler, . - Reserved39_IRQHandler + + .align 1 + .thumb_func + .weak ACMP_IRQHandler + .type ACMP_IRQHandler, %function +ACMP_IRQHandler: + ldr r0,=ACMP_DriverIRQHandler + bx r0 + .size ACMP_IRQHandler, . - ACMP_IRQHandler + + .align 1 + .thumb_func + .weak Reserved41_IRQHandler + .type Reserved41_IRQHandler, %function +Reserved41_IRQHandler: + ldr r0,=Reserved41_DriverIRQHandler + bx r0 + .size Reserved41_IRQHandler, . - Reserved41_IRQHandler + + .align 1 + .thumb_func + .weak Reserved42_IRQHandler + .type Reserved42_IRQHandler, %function +Reserved42_IRQHandler: + ldr r0,=Reserved42_DriverIRQHandler + bx r0 + .size Reserved42_IRQHandler, . - Reserved42_IRQHandler + + .align 1 + .thumb_func + .weak USB0_NEEDCLK_IRQHandler + .type USB0_NEEDCLK_IRQHandler, %function +USB0_NEEDCLK_IRQHandler: + ldr r0,=USB0_NEEDCLK_DriverIRQHandler + bx r0 + .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler + + .align 1 + .thumb_func + .weak USB0_IRQHandler + .type USB0_IRQHandler, %function +USB0_IRQHandler: + ldr r0,=USB0_DriverIRQHandler + bx r0 + .size USB0_IRQHandler, . - USB0_IRQHandler + + .align 1 + .thumb_func + .weak RTC_IRQHandler + .type RTC_IRQHandler, %function +RTC_IRQHandler: + ldr r0,=RTC_DriverIRQHandler + bx r0 + .size RTC_IRQHandler, . - RTC_IRQHandler + + .align 1 + .thumb_func + .weak Reserved46_IRQHandler + .type Reserved46_IRQHandler, %function +Reserved46_IRQHandler: + ldr r0,=Reserved46_DriverIRQHandler + bx r0 + .size Reserved46_IRQHandler, . - Reserved46_IRQHandler + + .align 1 + .thumb_func + .weak MAILBOX_IRQHandler + .type MAILBOX_IRQHandler, %function +MAILBOX_IRQHandler: + ldr r0,=MAILBOX_DriverIRQHandler + bx r0 + .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT4_IRQHandler + .type PIN_INT4_IRQHandler, %function +PIN_INT4_IRQHandler: + ldr r0,=PIN_INT4_DriverIRQHandler + bx r0 + .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT5_IRQHandler + .type PIN_INT5_IRQHandler, %function +PIN_INT5_IRQHandler: + ldr r0,=PIN_INT5_DriverIRQHandler + bx r0 + .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT6_IRQHandler + .type PIN_INT6_IRQHandler, %function +PIN_INT6_IRQHandler: + ldr r0,=PIN_INT6_DriverIRQHandler + bx r0 + .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT7_IRQHandler + .type PIN_INT7_IRQHandler, %function +PIN_INT7_IRQHandler: + ldr r0,=PIN_INT7_DriverIRQHandler + bx r0 + .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER2_IRQHandler + .type CTIMER2_IRQHandler, %function +CTIMER2_IRQHandler: + ldr r0,=CTIMER2_DriverIRQHandler + bx r0 + .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER4_IRQHandler + .type CTIMER4_IRQHandler, %function +CTIMER4_IRQHandler: + ldr r0,=CTIMER4_DriverIRQHandler + bx r0 + .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler + + .align 1 + .thumb_func + .weak OS_EVENT_IRQHandler + .type OS_EVENT_IRQHandler, %function +OS_EVENT_IRQHandler: + ldr r0,=OS_EVENT_DriverIRQHandler + bx r0 + .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler + + .align 1 + .thumb_func + .weak Reserved55_IRQHandler + .type Reserved55_IRQHandler, %function +Reserved55_IRQHandler: + ldr r0,=Reserved55_DriverIRQHandler + bx r0 + .size Reserved55_IRQHandler, . - Reserved55_IRQHandler + + .align 1 + .thumb_func + .weak Reserved56_IRQHandler + .type Reserved56_IRQHandler, %function +Reserved56_IRQHandler: + ldr r0,=Reserved56_DriverIRQHandler + bx r0 + .size Reserved56_IRQHandler, . - Reserved56_IRQHandler + + .align 1 + .thumb_func + .weak Reserved57_IRQHandler + .type Reserved57_IRQHandler, %function +Reserved57_IRQHandler: + ldr r0,=Reserved57_DriverIRQHandler + bx r0 + .size Reserved57_IRQHandler, . - Reserved57_IRQHandler + + .align 1 + .thumb_func + .weak SDIO_IRQHandler + .type SDIO_IRQHandler, %function +SDIO_IRQHandler: + ldr r0,=SDIO_DriverIRQHandler + bx r0 + .size SDIO_IRQHandler, . - SDIO_IRQHandler + + .align 1 + .thumb_func + .weak Reserved59_IRQHandler + .type Reserved59_IRQHandler, %function +Reserved59_IRQHandler: + ldr r0,=Reserved59_DriverIRQHandler + bx r0 + .size Reserved59_IRQHandler, . - Reserved59_IRQHandler + + .align 1 + .thumb_func + .weak Reserved60_IRQHandler + .type Reserved60_IRQHandler, %function +Reserved60_IRQHandler: + ldr r0,=Reserved60_DriverIRQHandler + bx r0 + .size Reserved60_IRQHandler, . - Reserved60_IRQHandler + + .align 1 + .thumb_func + .weak Reserved61_IRQHandler + .type Reserved61_IRQHandler, %function +Reserved61_IRQHandler: + ldr r0,=Reserved61_DriverIRQHandler + bx r0 + .size Reserved61_IRQHandler, . - Reserved61_IRQHandler + + .align 1 + .thumb_func + .weak USB1_PHY_IRQHandler + .type USB1_PHY_IRQHandler, %function +USB1_PHY_IRQHandler: + ldr r0,=USB1_PHY_DriverIRQHandler + bx r0 + .size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler + + .align 1 + .thumb_func + .weak USB1_IRQHandler + .type USB1_IRQHandler, %function +USB1_IRQHandler: + ldr r0,=USB1_DriverIRQHandler + bx r0 + .size USB1_IRQHandler, . - USB1_IRQHandler + + .align 1 + .thumb_func + .weak USB1_NEEDCLK_IRQHandler + .type USB1_NEEDCLK_IRQHandler, %function +USB1_NEEDCLK_IRQHandler: + ldr r0,=USB1_NEEDCLK_DriverIRQHandler + bx r0 + .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler + + .align 1 + .thumb_func + .weak SEC_HYPERVISOR_CALL_IRQHandler + .type SEC_HYPERVISOR_CALL_IRQHandler, %function +SEC_HYPERVISOR_CALL_IRQHandler: + ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler + bx r0 + .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler + + .align 1 + .thumb_func + .weak SEC_GPIO_INT0_IRQ0_IRQHandler + .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function +SEC_GPIO_INT0_IRQ0_IRQHandler: + ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler + bx r0 + .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler + + .align 1 + .thumb_func + .weak SEC_GPIO_INT0_IRQ1_IRQHandler + .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function +SEC_GPIO_INT0_IRQ1_IRQHandler: + ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler + bx r0 + .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler + + .align 1 + .thumb_func + .weak PLU_IRQHandler + .type PLU_IRQHandler, %function +PLU_IRQHandler: + ldr r0,=PLU_DriverIRQHandler + bx r0 + .size PLU_IRQHandler, . - PLU_IRQHandler + + .align 1 + .thumb_func + .weak SEC_VIO_IRQHandler + .type SEC_VIO_IRQHandler, %function +SEC_VIO_IRQHandler: + ldr r0,=SEC_VIO_DriverIRQHandler + bx r0 + .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler + + .align 1 + .thumb_func + .weak HASHCRYPT_IRQHandler + .type HASHCRYPT_IRQHandler, %function +HASHCRYPT_IRQHandler: + ldr r0,=HASHCRYPT_DriverIRQHandler + bx r0 + .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler + + .align 1 + .thumb_func + .weak CASER_IRQHandler + .type CASER_IRQHandler, %function +CASER_IRQHandler: + ldr r0,=CASER_DriverIRQHandler + bx r0 + .size CASER_IRQHandler, . - CASER_IRQHandler + + .align 1 + .thumb_func + .weak PUF_IRQHandler + .type PUF_IRQHandler, %function +PUF_IRQHandler: + ldr r0,=PUF_DriverIRQHandler + bx r0 + .size PUF_IRQHandler, . - PUF_IRQHandler + + .align 1 + .thumb_func + .weak PQ_IRQHandler + .type PQ_IRQHandler, %function +PQ_IRQHandler: + ldr r0,=PQ_DriverIRQHandler + bx r0 + .size PQ_IRQHandler, . - PQ_IRQHandler + + .align 1 + .thumb_func + .weak DMA1_IRQHandler + .type DMA1_IRQHandler, %function +DMA1_IRQHandler: + ldr r0,=DMA1_DriverIRQHandler + bx r0 + .size DMA1_IRQHandler, . - DMA1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM8_IRQHandler + .type FLEXCOMM8_IRQHandler, %function +FLEXCOMM8_IRQHandler: + ldr r0,=FLEXCOMM8_DriverIRQHandler + bx r0 + .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SecureFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ + def_irq_handler DMA0_DriverIRQHandler /* DMA0 controller */ + def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */ + def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */ + def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ + def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ + def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ + def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ + def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */ + def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */ + def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */ + def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */ + def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */ + def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */ + def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler ADC0_DriverIRQHandler /* ADC0 */ + def_irq_handler Reserved39_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler ACMP_DriverIRQHandler /* ACMP interrupts */ + def_irq_handler Reserved41_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved42_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */ + def_irq_handler USB0_DriverIRQHandler /* USB device */ + def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */ + def_irq_handler Reserved46_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler MAILBOX_DriverIRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */ + def_irq_handler PIN_INT4_DriverIRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ + def_irq_handler PIN_INT5_DriverIRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ + def_irq_handler PIN_INT6_DriverIRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ + def_irq_handler PIN_INT7_DriverIRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ + def_irq_handler CTIMER2_DriverIRQHandler /* Standard counter/timer CTIMER2 */ + def_irq_handler CTIMER4_DriverIRQHandler /* Standard counter/timer CTIMER4 */ + def_irq_handler OS_EVENT_DriverIRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ + def_irq_handler Reserved55_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved56_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved57_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler SDIO_DriverIRQHandler /* SD/MMC */ + def_irq_handler Reserved59_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved60_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved61_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler USB1_PHY_DriverIRQHandler /* USB1_PHY */ + def_irq_handler USB1_DriverIRQHandler /* USB1 interrupt */ + def_irq_handler USB1_NEEDCLK_DriverIRQHandler /* USB1 activity */ + def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler /* SEC_HYPERVISOR_CALL interrupt */ + def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ + def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ + def_irq_handler PLU_DriverIRQHandler /* PLU interrupt */ + def_irq_handler SEC_VIO_DriverIRQHandler /* SEC_VIO interrupt */ + def_irq_handler HASHCRYPT_DriverIRQHandler /* HASHCRYPT interrupt */ + def_irq_handler CASER_DriverIRQHandler /* CASPER interrupt */ + def_irq_handler PUF_DriverIRQHandler /* PUF interrupt */ + def_irq_handler PQ_DriverIRQHandler /* PQ interrupt */ + def_irq_handler DMA1_DriverIRQHandler /* DMA1 interrupt */ + def_irq_handler FLEXCOMM8_DriverIRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ + + .end diff --git a/source/hic_hal/nxp/lpc55xx/gpio.c b/source/hic_hal/nxp/lpc55xx/gpio.c new file mode 100644 index 000000000..b9d00394b --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/gpio.c @@ -0,0 +1,159 @@ +/** + * @file gpio.c + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2016-2017 NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "fsl_device_registers.h" +#include "DAP_config.h" +#include "gpio.h" +#include "daplink.h" +#include "hic_init.h" +#include "fsl_clock.h" + +static void busy_wait(uint32_t cycles) +{ + volatile uint32_t i = cycles; + while (i > 0) { + i--; + } +} + +void gpio_init(void) +{ + // Enable hardfault on unaligned access for the interface only. + // If this is done in the bootloader than then it might (will) break + // older application firmware or firmware from 3rd party vendors. +#if defined(DAPLINK_IF) + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif +#ifdef LPC55_FIXME + // enable clock to ports + SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK; + SIM->SCGC6 |= SIM_SCGC6_DMAMUX_MASK; + // configure pin as GPIO + LED_CONNECTED_PORT->PCR[LED_CONNECTED_BIT] = PORT_PCR_MUX(1); + // led off - enable output + LED_CONNECTED_GPIO->PDOR = 1UL << LED_CONNECTED_BIT; + LED_CONNECTED_GPIO->PDDR = 1UL << LED_CONNECTED_BIT; + // led on + LED_CONNECTED_GPIO->PCOR = 1UL << LED_CONNECTED_BIT; + // reset button configured as gpio input + PIN_nRESET_GPIO->PDDR &= ~PIN_nRESET; + PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_MUX(1); + /* Enable LVLRST_EN */ + PIN_nRESET_EN_PORT->PCR[PIN_nRESET_EN_BIT] = PORT_PCR_MUX(1) | /* GPIO */ + PORT_PCR_ODE_MASK; /* Open-drain */ + PIN_nRESET_EN_GPIO->PSOR = PIN_nRESET_EN; + PIN_nRESET_EN_GPIO->PDDR |= PIN_nRESET_EN; + // Configure SWO UART RX. + PIN_SWO_RX_PORT->PCR[PIN_SWO_RX_BIT] = PORT_PCR_MUX(3); // UART1 + PIN_SWO_RX_GPIO->PDDR &= ~(1 << PIN_SWO_RX_BIT); // Input + + // Enable pulldowns on power monitor control signals to reduce power consumption. + PIN_CTRL0_PORT->PCR[PIN_CTRL0_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); + PIN_CTRL1_PORT->PCR[PIN_CTRL1_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); + PIN_CTRL2_PORT->PCR[PIN_CTRL2_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); + PIN_CTRL3_PORT->PCR[PIN_CTRL3_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); + + // Enable pulldown on GPIO0_B to prevent it floating. + PIN_GPIO0_B_PORT->PCR[PIN_GPIO0_B_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); + + // configure power enable pin as GPIO + PIN_POWER_EN_PORT->PCR[PIN_POWER_EN_BIT] = PORT_PCR_MUX(1); + // set output to 0 + PIN_POWER_EN_GPIO->PCOR = PIN_POWER_EN; + // switch gpio to output + PIN_POWER_EN_GPIO->PDDR |= PIN_POWER_EN; + + // Let the voltage rails stabilize. This is especailly important + // during software resets, since the target's 3.3v rail can take + // 20-50ms to drain. During this time the target could be driving + // the reset pin low, causing the bootloader to think the reset + // button is pressed. + // Note: With optimization set to -O2 the value 1000000 delays for ~85ms + busy_wait(1000000); +#endif +} + +void gpio_set_board_power(bool powerEnabled) +{ +#ifdef LPC55_FIXME + if (powerEnabled) { + // enable power switch + PIN_POWER_EN_GPIO->PSOR = PIN_POWER_EN; + } + else { + // disable power switch + PIN_POWER_EN_GPIO->PCOR = PIN_POWER_EN; + } +#endif +} + +uint32_t UART1_GetFreq(void) +{ + return CLOCK_GetCoreSysClkFreq(); +} + +void UART1_InitPins(void) +{ + // RX pin inited in gpio_init(); + // TX not used. +} + +void UART1_DeinitPins(void) +{ + // No need to deinit the RX pin. + // TX not used. +} + +void gpio_set_hid_led(gpio_led_state_t state) +{ +#ifdef LPC55_FIXME + if (state) { + LED_CONNECTED_GPIO->PCOR = LED_CONNECTED; // LED on + } else { + LED_CONNECTED_GPIO->PSOR = LED_CONNECTED; // LED off + } +#endif +} + +void gpio_set_cdc_led(gpio_led_state_t state) +{ + gpio_set_hid_led(state); +} + +void gpio_set_msc_led(gpio_led_state_t state) +{ + gpio_set_hid_led(state); +} + +uint8_t gpio_get_reset_btn_no_fwrd(void) +{ +#ifdef LPC55_FIXME + return (PIN_nRESET_GPIO->PDIR & PIN_nRESET) ? 0 : 1; +#else + return 0; +#endif +} + +uint8_t gpio_get_reset_btn_fwrd(void) +{ + return 0; +} diff --git a/source/hic_hal/nxp/lpc55xx/hic_init.c b/source/hic_hal/nxp/lpc55xx/hic_init.c new file mode 100644 index 000000000..0029517fd --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/hic_init.c @@ -0,0 +1,163 @@ +/** + * @file hic_init.c + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2016-2017 NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hic_init.h" +#include "gpio.h" +#include "fsl_clock.h" +#include "usb_phy.h" +#include "util.h" + +static void busy_wait(uint32_t cycles) +{ + volatile uint32_t i; + i = cycles; + + while (i > 0) { + i--; + } +} + +static void fll_delay(void) +{ + // ~2.5ms at 16MHz core clock + busy_wait(10000); +} + +// This IRQ handler will be invoked if VDD falls below the trip point. +void LVD_LVW_IRQHandler(void) +{ +#ifdef LPC55_FIXME + if (PMC->LVDSC1 & PMC_LVDSC1_LVDF_MASK) + { + util_assert(false && "low voltage detect tripped"); + PMC->LVDSC1 |= PMC_LVDSC1_LVDACK_MASK; + } + if (PMC->LVDSC2 & PMC_LVDSC2_LVWF_MASK) + { + util_assert(false && "low voltage warning tripped"); + PMC->LVDSC2 |= PMC_LVDSC2_LVWACK_MASK; + } +#endif +} + +//! - MPU is disabled and gated. +//! - 8kB cache is enabled. SRAM is not cached, so no flushing is required for normal operation. +//! - Enable low voltage warning interrupt. +//! - Disable USB current limiter so the voltage doesn't drop as we enable high speed clocks. +void sdk_init(void) +{ +#ifdef LPC55_FIXME + CLOCK_SetXtal0Freq(16000000U); // 16 MHz crystal + CLOCK_SetXtal32Freq(0); + + // Disable the MPU if it's enabled. + if (SIM->SCGC7 & SIM_SCGC7_MPU_MASK) + { + SYSMPU->CESR = 0; + SIM->SCGC7 &= ~SIM_SCGC7_MPU_MASK; + } + + // Invalidate and enable code cache. + LMEM->PCCCR = LMEM_PCCCR_GO_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_ENCACHE_MASK; + + // Enable LVD/LVW IRQ. + PMC->LVDSC1 |= PMC_LVDSC1_LVDACK_MASK; + PMC->LVDSC1 = PMC_LVDSC1_LVDIE_MASK | PMC_LVDSC1_LVDV(0); // low trip point + PMC->LVDSC2 |= PMC_LVDSC2_LVWACK_MASK; + PMC->LVDSC2 = PMC_LVDSC2_LVWIE_MASK | PMC_LVDSC2_LVWV(0); // low trip point + // NVIC_EnableIRQ(LVD_LVW_IRQn); + + // Disable USB inrush current limiter. + SIM->USBPHYCTL |= SIM_USBPHYCTL_USBDISILIM_MASK; +#endif +} + +//! - Turn on 16MHz crystal oscillator. +//! - Turn on 32kHz IRC. +//! - Switch core clock to System PLL at 120 MHz, bus clock at 60 MHz, flash clock at 24 MHz. +//! - Enable the 480MHz USB PHY PLL. +//! - Ungate USBPHY and USBHS. +//! - Configure the USB PHY. +void hic_enable_usb_clocks(void) +{ +#ifdef LPC55_FIXME + // Enable external oscillator and 32kHz IRC. + MCG->C1 |= MCG_C1_IRCLKEN_MASK; // Select 32k IR. + // Delay at least 100µs for 32kHz IRQ to stabilize. + fll_delay(); + // Configure OSC for very high freq, low power mode. + MCG->C2 = (MCG->C2 & ~(MCG_C2_RANGE_MASK | MCG_C2_HGO_MASK)) | MCG_C2_RANGE(2); + OSC0->CR |= OSC_CR_ERCLKEN_MASK; // Enable OSC. + MCG->C2 |= MCG_C2_EREFS_MASK; // Select OSC as ext ref. + + // Wait for the oscillator to stabilize. + while (!(MCG->S & MCG_S_OSCINIT0_MASK)) + { + } + + // Divide 16MHz xtal by 512 = 31.25kHz + CLOCK_SetFbeMode(4, kMCG_Dmx32Default, kMCG_DrsMid, fll_delay); + + // Set dividers before switching to SYSPLL. + SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) // System/core /1 = 120MHz + | SIM_CLKDIV1_OUTDIV2(1) // Bus /2 = 60Mhz + | SIM_CLKDIV1_OUTDIV3(4) // FlexBus /5 = 24Mhz + | SIM_CLKDIV1_OUTDIV4(4); // Flash /5 = 24MHz + + // 120MHz SYSPLL + mcg_pll_config_t pllConfig; + pllConfig.enableMode = 0; + pllConfig.prdiv = 2 - 1; + pllConfig.vdiv = 30 - 16; + CLOCK_SetPbeMode(kMCG_PllClkSelPll0, &pllConfig); + CLOCK_SetPeeMode(); + + // Enable USB clock source and init phy. This turns on the 480MHz PLL. + CLOCK_EnableUsbhs0Clock(kCLOCK_UsbSrcPll0, CLOCK_GetFreq(kCLOCK_PllFllSelClk)); + USB_EhciPhyInit(0, CPU_XTAL_CLK_HZ); +#endif + SystemCoreClockUpdate(); +} + +void hic_power_target(void) +{ + // Keep powered off in bootloader mode + // to prevent the target from effecting the state + // of the reset line / reset button + if (!daplink_is_bootloader()) { +#ifdef LPC55_FIXME + // configure pin as GPIO + PIN_POWER_EN_PORT->PCR[PIN_POWER_EN_BIT] = PORT_PCR_MUX(1); + // force always on logic 1 + PIN_POWER_EN_GPIO->PSOR = 1UL << PIN_POWER_EN_BIT; + PIN_POWER_EN_GPIO->PDDR |= 1UL << PIN_POWER_EN_BIT; + + // Let the voltage rails stabilize. This is especailly important + // during software resets, since the target's 3.3v rail can take + // 20-50ms to drain. During this time the target could be driving + // the reset pin low, causing the bootloader to think the reset + // button is pressed. + // Note: With optimization set to -O2 the value 5115 delays for ~1ms @ 20.9Mhz core + busy_wait(5115 * 50); +#endif + } +} diff --git a/source/hic_hal/nxp/lpc55xx/hic_init.h b/source/hic_hal/nxp/lpc55xx/hic_init.h new file mode 100644 index 000000000..91f9ddb9a --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/hic_init.h @@ -0,0 +1,35 @@ +/** + * @file hic_init.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2016-2017 NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined(__cplusplus) +extern "C" { +#endif + +//! @brief Set some system-wide hardware settings. +void hic_init(void); + +//! @brief Enable clocks required for USB operation. +void hic_enable_usb_clocks(void); + +#if defined(__cplusplus) +} +#endif diff --git a/source/hic_hal/nxp/lpc55xx/read_uid.c b/source/hic_hal/nxp/lpc55xx/read_uid.c new file mode 100644 index 000000000..8606681de --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/read_uid.c @@ -0,0 +1,38 @@ +/** + * @file read_uid.c + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "fsl_device_registers.h" +#include "read_uid.h" + +void read_unique_id(uint32_t *id) +{ +#ifdef LPC55_FIXME + id[0] = SIM->UIDL; + id[1] = SIM->UIDML; + id[2] = SIM->UIDMH; + id[3] = SIM->UIDH; +#else + id[0] = 0; + id[1] = 0; + id[2] = 0; + id[3] = 0; +#endif +} diff --git a/source/hic_hal/nxp/lpc55xx/uart.c b/source/hic_hal/nxp/lpc55xx/uart.c new file mode 100644 index 000000000..3a817927a --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/uart.c @@ -0,0 +1,257 @@ +/** + * @file uart.c + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2016-2017 NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "string.h" +#include "fsl_device_registers.h" +#include "uart.h" +#include "util.h" +#include "cortex_m.h" +#include "circ_buf.h" +#include "settings.h" // for config_get_overflow_detect + +#define UART_INSTANCE (USART0) +#define UART_IRQ (FLEXCOMM0_IRQn) + +extern uint32_t SystemCoreClock; + +static void clear_buffers(void); + +#define RX_OVRF_MSG "\n" +#define RX_OVRF_MSG_SIZE (sizeof(RX_OVRF_MSG) - 1) +#define BUFFER_SIZE (512) + + +circ_buf_t write_buffer; +uint8_t write_buffer_data[BUFFER_SIZE]; +circ_buf_t read_buffer; +uint8_t read_buffer_data[BUFFER_SIZE]; + +void clear_buffers(void) +{ +#ifdef LPC55_FIXME + util_assert(!(UART_INSTANCE->C2 & UART_C2_TIE_MASK)); +#endif + circ_buf_init(&write_buffer, write_buffer_data, sizeof(write_buffer_data)); + circ_buf_init(&read_buffer, read_buffer_data, sizeof(read_buffer_data)); +} + +int32_t uart_initialize(void) +{ +#ifdef LPC55_FIXME + NVIC_DisableIRQ(UART_IRQ); + // enable clk PORTC + SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK; + // enable clk uart + SIM->SCGC4 |= SIM_SCGC4_UART0_MASK; + + // disable interrupt + NVIC_DisableIRQ(UART_IRQ); + // transmitter and receiver disabled + UART_INSTANCE->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK); + // disable interrupt + UART_INSTANCE->C2 &= ~(UART_C2_RIE_MASK | UART_C2_TIE_MASK); + + clear_buffers(); + + // Enable receiver and transmitter + UART_INSTANCE->C2 |= UART_C2_RE_MASK | UART_C2_TE_MASK; + + // alternate 3: UART0 + PORTB->PCR[16] = PORT_PCR_MUX(3); + PORTB->PCR[17] = PORT_PCR_MUX(3); + + // Enable receive interrupt + UART_INSTANCE->C2 |= UART_C2_RIE_MASK; + NVIC_ClearPendingIRQ(UART_IRQ); + NVIC_EnableIRQ(UART_IRQ); +#endif + return 1; +} + +int32_t uart_uninitialize(void) +{ + #ifdef LPC55_FIXME + // transmitter and receiver disabled + UART_INSTANCE->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK); + // disable interrupt + UART_INSTANCE->C2 &= ~(UART_C2_RIE_MASK | UART_C2_TIE_MASK); + clear_buffers(); +#endif + return 1; +} + +int32_t uart_reset(void) +{ +#ifdef LPC55_FIXME + // disable interrupt + NVIC_DisableIRQ(UART_IRQ); + // disable TIE interrupt + UART_INSTANCE->C2 &= ~(UART_C2_TIE_MASK); + clear_buffers(); + // enable interrupt + NVIC_EnableIRQ(UART_IRQ); +#endif + return 1; +} + +int32_t uart_set_configuration(UART_Configuration *config) +{ +#ifdef LPC55_FIXME + uint8_t data_bits = 8; + uint8_t parity_enable = 0; + uint8_t parity_type = 0; + uint32_t dll; + // disable interrupt + NVIC_DisableIRQ(UART_IRQ); + UART_INSTANCE->C2 &= ~(UART_C2_RIE_MASK | UART_C2_TIE_MASK); + // Disable receiver and transmitter while updating + UART_INSTANCE->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK); + clear_buffers(); + + // set data bits, stop bits, parity + if ((config->DataBits < 8) || (config->DataBits > 9)) { + data_bits = 8; + } + + data_bits -= 8; + + if (config->Parity == 1) { + parity_enable = 1; + parity_type = 1; + data_bits++; + } else if (config->Parity == 2) { + parity_enable = 1; + parity_type = 0; + data_bits++; + } + + // does not support 10 bit data comm + if (data_bits == 2) { + data_bits = 0; + parity_enable = 0; + parity_type = 0; + } + + // data bits, parity and parity mode + UART_INSTANCE->C1 = data_bits << UART_C1_M_SHIFT + | parity_enable << UART_C1_PE_SHIFT + | parity_type << UART_C1_PT_SHIFT; + dll = SystemCoreClock / (16 * config->Baudrate); + // set baudrate + UART_INSTANCE->BDH = (UART_INSTANCE->BDH & ~(UART_BDH_SBR_MASK)) | ((dll >> 8) & UART_BDH_SBR_MASK); + UART_INSTANCE->BDL = (UART_INSTANCE->BDL & ~(UART_BDL_SBR_MASK)) | (dll & UART_BDL_SBR_MASK); + // Enable transmitter and receiver + UART_INSTANCE->C2 |= UART_C2_RE_MASK | UART_C2_TE_MASK; + // Enable UART interrupt + NVIC_ClearPendingIRQ(UART_IRQ); + NVIC_EnableIRQ(UART_IRQ); + UART_INSTANCE->C2 |= UART_C2_RIE_MASK; +#endif + return 1; +} + +int32_t uart_get_configuration(UART_Configuration *config) +{ + return 1; +} + +int32_t uart_write_free(void) +{ + return circ_buf_count_free(&write_buffer); +} + +int32_t uart_write_data(uint8_t *data, uint16_t size) +{ +#ifdef LPC55_FIXME + cortex_int_state_t state; + uint32_t cnt; + + cnt = circ_buf_write(&write_buffer, data, size); + + // Atomically enable TX + state = cortex_int_get_and_disable(); + if (circ_buf_count_used(&write_buffer)) { + UART_INSTANCE->C2 |= UART_C2_TIE_MASK; + } + cortex_int_restore(state); + + return cnt; +#else + return 0; +#endif +} + +int32_t uart_read_data(uint8_t *data, uint16_t size) +{ + return circ_buf_read(&read_buffer, data, size); +} + +void UART0_RX_TX_IRQHandler(void) +{ +#ifdef LPC55_FIXME + uint32_t s1; + volatile uint8_t errorData; + // read interrupt status + s1 = UART_INSTANCE->S1; + // mask off interrupts that are not enabled + if (!(UART_INSTANCE->C2 & UART_C2_RIE_MASK)) { + s1 &= ~UART_S1_RDRF_MASK; + } + if (!(UART_INSTANCE->C2 & UART_C2_TIE_MASK)) { + s1 &= ~UART_S1_TDRE_MASK; + } + + // handle character to transmit + if (s1 & UART_S1_TDRE_MASK) { + // Assert that there is data in the buffer + util_assert(circ_buf_count_used(&write_buffer) > 0); + + // Send out data + UART_INSTANCE->D = circ_buf_pop(&write_buffer); + // Turn off the transmitter if that was the last byte + if (circ_buf_count_used(&write_buffer) == 0) { + // disable TIE interrupt + UART_INSTANCE->C2 &= ~(UART_C2_TIE_MASK); + } + } + + // handle received character + if (s1 & UART_S1_RDRF_MASK) { + if ((s1 & UART_S1_NF_MASK) || (s1 & UART_S1_FE_MASK)) { + errorData = UART_INSTANCE->D; + } else { + uint32_t free; + uint8_t data; + + data = UART_INSTANCE->D; + free = circ_buf_count_free(&read_buffer); + if (free > RX_OVRF_MSG_SIZE) { + circ_buf_push(&read_buffer, data); + } else if ((RX_OVRF_MSG_SIZE == free) && config_get_overflow_detect()) { + circ_buf_write(&read_buffer, (uint8_t*)RX_OVRF_MSG, RX_OVRF_MSG_SIZE); + } else { + // Drop character + } + } + } +#endif +} diff --git a/source/hic_hal/nxp/lpc55xx/usb_buf.h b/source/hic_hal/nxp/lpc55xx/usb_buf.h new file mode 100644 index 000000000..87cc1e40f --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/usb_buf.h @@ -0,0 +1,29 @@ +/** + * @file usb_buf.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef USB_BUF_H +#define USB_BUF_H + +#include "stdint.h" + +uint32_t usb_buffer[512 / 4]; + +#endif diff --git a/source/hic_hal/nxp/lpc55xx/usb_config.c b/source/hic_hal/nxp/lpc55xx/usb_config.c new file mode 100644 index 000000000..d30512bba --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/usb_config.c @@ -0,0 +1,561 @@ +/** + * @file usb_config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "util.h" + +//*** <<< Use Configuration Wizard in Context Menu >>> *** + +// **** +// NOTE: The high speed packet sizes are set to the same size as full speed in this +// USB configuration in order to increase the number of devices that can +// simultaneously be connected to a single USB controller. With the maximium +// high speed packet sizes, only 1 or 2 devices can be connected. +// **** + +// USB Device +// Enable the USB Device functionality +#define USBD_ENABLE 1 +#define USBD_RTX_CORE_STACK 0 +#define USBD_RTX_DEVICE_STACK 0 +#define USBD_RTX_ENDPOINT0_STACK 0 + +// High-speed +// Enable high-speed functionality (if device supports it) +#define USBD_HS_ENABLE 1 +#if (defined(WEBUSB_INTERFACE) || defined(WINUSB_INTERFACE) || defined(BULK_ENDPOINT)) +#define USBD_BOS_ENABLE 1 +#else +#define USBD_BOS_ENABLE 0 +#endif +// Device Settings +// These settings affect Device Descriptor +// Power +// Default Power Setting +// <0=> Bus-powered +// <1=> Self-powered +// Max Endpoint 0 Packet Size +// Maximum packet size for endpoint zero (bMaxPacketSize0) +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes +// Vendor ID <0x0000-0xFFFF> +// Vendor ID assigned by the USB-IF (idVendor) +// Product ID <0x0000-0xFFFF> +// Product ID assigned by the manufacturer (idProduct) +// Device Release Number <0x0000-0xFFFF> +// Device release number in binary-coded decimal (bcdDevice) +// +#define USBD_POWER 0 +#define USBD_MAX_PACKET0 64 +#define USBD_DEVDESC_IDVENDOR 0x0D28 +#define USBD_DEVDESC_IDPRODUCT 0x0204 +#define USBD_DEVDESC_BCDDEVICE 0x1000 //was 0x0100 + +// Configuration Settings +// These settings affect Configuration Descriptor +// Remote Wakeup +// Configuration support for remote wakeup (D5: of bmAttributes) +// Maximum Power Consumption (in mA) <0-510><#/2> +// Maximum power consumption of the USB device +// from the bus in this specific configuration +// when the device is fully operational (bMaxPower) +// +#define USBD_CFGDESC_BMATTRIBUTES 0x80 +#define USBD_CFGDESC_BMAXPOWER 0xFA + +// String Settings +// These settings affect String Descriptor +// Language ID <0x0000-0xFCFF> +// English (United States) = 0x0409 +// Manufacturer String +// String descriptor describing manufacturer +// Product String +// String descriptor describing product +// Serial Number +// Enable serial number string +// If disabled serial number string will not be assigned to the USB Device +// Serial Number String +// String descriptor describing device's serial number +// +// +#define USBD_STRDESC_LANGID 0x0409 +#define USBD_STRDESC_MAN L"Arm" +#ifndef USB_PROD_STR +#define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" +#else +#define _TOWIDE(x) L ## #x +#define TOWIDE(x) _TOWIDE(x) +#define USBD_STRDESC_PROD TOWIDE(USB_PROD_STR) +#endif +#define USBD_STRDESC_SER_ENABLE 1 +#define USBD_STRDESC_SER L"0001A0000000" + +// Class Support +// Enables USB Device Class specific Requests +#define USBD_CLASS_ENABLE 1 + +// Human Interface Device (HID) +// Enable class support for Human Interface Device (HID) +// Interrupt Endpoint Settings +// Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// Interrupt Out Endpoint Number <0=> Not used <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// If interrupt out endpoint is not used select "Not used" +// Endpoint Settings +// Maximum Endpoint Packet Size (in bytes) <0-64> +// Endpoint polling Interval (in ms) <1-255> +// High-speed +// If high-speed is enabled set endpoint settings for it +// Maximum Endpoint Packet Size (in bytes) <0-1024> +// Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// +// +// +// Human Interface Device Settings +// Device specific settings +// HID Interface String +// Number of Input Reports <1-32> +// Number of Output Reports <1-32> +// Maximum Input Report Size (in bytes) <1-65535> +// Maximum Output Report Size (in bytes) <1-65535> +// Maximum Feature Report Size (in bytes) <1-65535> +// +// +#ifndef HID_ENDPOINT +#define HID_ENDPOINT 0 +#else +#define HID_ENDPOINT 1 +#endif + +#ifndef WEBUSB_INTERFACE +#define WEBUSB_INTERFACE 0 +#else +#define WEBUSB_INTERFACE 1 +#endif + +#define USBD_HID_ENABLE HID_ENDPOINT +#define USBD_HID_EP_INTIN 1 +#define USBD_HID_EP_INTOUT 1 + +#define USBD_HID_EP_INTIN_STACK 0 +#define USBD_HID_WMAXPACKETSIZE 64 +#define USBD_HID_BINTERVAL 1 +#define USBD_HID_HS_ENABLE 1 +#define USBD_HID_HS_WMAXPACKETSIZE 64 //| (2<<11) +#define USBD_HID_HS_BINTERVAL 1 +#define USBD_HID_STRDESC L"CMSIS-DAP v1" +#define USBD_WEBUSB_STRDESC L"WebUSB: CMSIS-DAP" +#define USBD_HID_INREPORT_NUM 1 +#define USBD_HID_OUTREPORT_NUM 1 +#define USBD_HID_INREPORT_MAX_SZ 64 +#define USBD_HID_OUTREPORT_MAX_SZ 64 +#define USBD_HID_FEATREPORT_MAX_SZ 1 + +// Mass Storage Device (MSC) +// Enable class support for Mass Storage Device (MSC) +// Bulk Endpoint Settings +// Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// Endpoint Settings +// Maximum Packet Size <1-1024> +// High-speed +// If high-speed is enabled set endpoint settings for it +// Maximum Packet Size <1-1024> +// Maximum NAK Rate <0-255> +// +// +// +// Mass Storage Device Settings +// Device specific settings +// MSC Interface String +// Inquiry Data +// Vendor Identification +// Product Identification +// Product Revision Level +// +// +// +#ifndef MSC_ENDPOINT +#define MSC_ENDPOINT 0 +#else +#define MSC_ENDPOINT 1 +#endif +#define USBD_MSC_ENABLE MSC_ENDPOINT +#define USBD_MSC_EP_BULKIN 2 +#define USBD_MSC_EP_BULKOUT 2 +#define USBD_MSC_EP_BULKIN_STACK 0 +#define USBD_MSC_WMAXPACKETSIZE 64 +#define USBD_MSC_HS_ENABLE 1 +#define USBD_MSC_HS_WMAXPACKETSIZE 512 +#define USBD_MSC_HS_BINTERVAL 0 +#define USBD_MSC_STRDESC L"USB_MSC" +// Make sure changes to USBD_MSC_INQUIRY_DATA are coordinated with mbed-ls +// since this is used to detect DAPLink drives +#define USBD_MSC_INQUIRY_DATA "MBED " \ + "VFS " \ + "0.1" + +// Audio Device (ADC) +// Enable class support for Audio Device (ADC) +// Isochronous Endpoint Settings +// Isochronous Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// Endpoint Settings +// Maximum Endpoint Packet Size (in bytes) <0-1024> +// Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// High-speed +// If high-speed is enabled set endpoint settings for it +// Maximum Endpoint Packet Size (in bytes) <0-1024> +// Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// +// +// +// Audio Device Settings +// Device specific settings +// Audio Control Interface String +// Audio Streaming (Zero Bandwidth) Interface String +// Audio Streaming (Operational) Interface String +// Audio Subframe Size (in bytes) <0-255> +// Sample Resolution (in bits) <0-255> +// Sample Frequency (in Hz) <0-16777215> +// Packet Size (in bytes) <1-256> +// Packet Count <1-16> +// +// +#define USBD_ADC_ENABLE 0 +#define USBD_ADC_EP_ISOOUT 3 +#define USBD_ADC_WMAXPACKETSIZE 64 +#define USBD_ADC_BINTERVAL 1 +#define USBD_ADC_HS_ENABLE 0 +#define USBD_ADC_HS_WMAXPACKETSIZE 64 +#define USBD_ADC_CIF_STRDESC L"USB_ADC" +#define USBD_ADC_SIF1_STRDESC L"USB_ADC1" +#define USBD_ADC_SIF2_STRDESC L"USB_ADC2" +#define USBD_ADC_BSUBFRAMESIZE 2 +#define USBD_ADC_BBITRESOLUTION 16 +#define USBD_ADC_TSAMFREQ 32000 +#define USBD_ADC_CFG_P_S 32 +#define USBD_ADC_CFG_P_C 1 + +// Communication Device (CDC) - Abstract Control Model (ACM) +// Enable class support for Communication Device (CDC) - Abstract Control Model (ACM) +// Interrupt Endpoint Settings +// Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// Endpoint Settings +// Maximum Endpoint Packet Size (in bytes) <0-1024> +// Endpoint polling Interval (in ms) <0-255> +// High-speed +// If high-speed is enabled set endpoint settings for it +// Maximum Endpoint Packet Size (in bytes) <0-1024> +// Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// +// +// +// Bulk Endpoint Settings +// Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// Endpoint Settings +// Maximum Packet Size <1-1024> +// High-speed +// If high-speed is enabled set endpoint settings for it +// Maximum Packet Size <1-1024> +// Maximum NAK Rate <0-255> +// +// +// +// Communication Device Settings +// Device specific settings +// Communication Class Interface String +// Data Class Interface String +// Maximum Communication Device Send Buffer Size +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// Maximum Communication Device Receive Buffer Size +// Minimum size must be as big as maximum packet size for Bulk Out Endpoint +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// +// + +#ifndef CDC_ENDPOINT +#define CDC_ENDPOINT 0 +#else +#define CDC_ENDPOINT 1 +#endif +#define USBD_CDC_ACM_ENABLE CDC_ENDPOINT +#define USBD_CDC_ACM_EP_INTIN 3 +#define USBD_CDC_ACM_EP_INTIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE 16 +#define USBD_CDC_ACM_BINTERVAL 32 +#define USBD_CDC_ACM_HS_ENABLE 1 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE 64 +#define USBD_CDC_ACM_HS_BINTERVAL 2 +#define USBD_CDC_ACM_EP_BULKIN 4 +#define USBD_CDC_ACM_EP_BULKOUT 4 +#define USBD_CDC_ACM_EP_BULKIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE1 64 +#define USBD_CDC_ACM_HS_ENABLE1 1 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE1 512 +#define USBD_CDC_ACM_HS_BINTERVAL1 1 +#define USBD_CDC_ACM_CIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_DIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_SENDBUF_SIZE USBD_CDC_ACM_HS_WMAXPACKETSIZE1 +#define USBD_CDC_ACM_RECEIVEBUF_SIZE USBD_CDC_ACM_HS_WMAXPACKETSIZE1 +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Send Buffer size must be larger or equal to Bulk In maximum packet size!" +#endif +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Receive Buffer size must be larger or equal to Bulk Out maximum packet size!" +#endif + +// Custom Class Device +// Enables USB Custom Class Requests +// Class IDs: +// 0x00 - Class Reserved ID +// 0x01 - Class Audio ID +// 0x02 - Class Communications ID +// 0x03 - Class Human Interface ID +// 0x04 - Class Monitor ID +// 0x05 - Class Physical Interface ID +// 0x06 - Class Power ID +// 0x07 - Class Printer ID +// 0x08 - Class Storage ID +// 0x09 - Class HUB ID +// 0xEF - Class Miscellaneous ID +// 0xFF - Class Vendor Specific ID +// +#define USBD_CLS_ENABLE 0 + +// WebUSB support +#define USBD_WEBUSB_ENABLE WEBUSB_INTERFACE +#define USBD_WEBUSB_VENDOR_CODE 0x21 +#define USBD_WEBUSB_LANDING_URL "os.mbed.com/webusb/landing-page/?bid=" +#define USBD_WEBUSB_ORIGIN_URL "os.mbed.com/" + +// Microsoft OS Descriptors 2.0 (WinUSB) support +#define USBD_WINUSB_ENABLE WINUSB_INTERFACE +#define USBD_WINUSB_VENDOR_CODE 0x20 +// +// + +#ifndef BULK_ENDPOINT +#define BULK_ENDPOINT 0 +#else +#define BULK_ENDPOINT 1 +#endif +#define USBD_BULK_ENABLE BULK_ENDPOINT +#define USBD_BULK_EP_BULKIN 5 +#define USBD_BULK_EP_BULKOUT 5 +#define USBD_BULK_WMAXPACKETSIZE 64 +#define USBD_BULK_HS_ENABLE 1 +#define USBD_BULK_HS_WMAXPACKETSIZE 512 +#define USBD_BULK_STRDESC L"CMSIS-DAP v2" + + +/* USB Device Calculations ---------------------------------------------------*/ + +#define USBD_IF_NUM_MAX (USBD_BULK_ENABLE+USBD_WEBUSB_ENABLE+USBD_HID_ENABLE+USBD_MSC_ENABLE+(USBD_ADC_ENABLE*2)+(USBD_CDC_ACM_ENABLE*2)+USBD_CLS_ENABLE) +#define USBD_MULTI_IF (USBD_CDC_ACM_ENABLE*(USBD_HID_ENABLE|USBD_MSC_ENABLE|USBD_ADC_ENABLE|USBD_CLS_ENABLE|USBD_WEBUSB_ENABLE|USBD_BULK_ENABLE)) +// #define MAX(x, y) (((x) < (y)) ? (y) : (x)) +#define USBD_EP_NUM_CALC0 MAX((USBD_HID_ENABLE *(USBD_HID_EP_INTIN )), (USBD_HID_ENABLE *(USBD_HID_EP_INTOUT!=0)*(USBD_HID_EP_INTOUT))) +#define USBD_EP_NUM_CALC1 MAX((USBD_MSC_ENABLE *(USBD_MSC_EP_BULKIN )), (USBD_MSC_ENABLE *(USBD_MSC_EP_BULKOUT))) +#define USBD_EP_NUM_CALC2 MAX((USBD_ADC_ENABLE *(USBD_ADC_EP_ISOOUT )), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_INTIN))) +#define USBD_EP_NUM_CALC3 MAX((USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKIN)), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKOUT))) +#define USBD_EP_NUM_CALC4 MAX(USBD_EP_NUM_CALC0, USBD_EP_NUM_CALC1) +#define USBD_EP_NUM_CALC5 MAX(USBD_EP_NUM_CALC2, USBD_EP_NUM_CALC3) +#define USBD_EP_NUM_CALC6 MAX(USBD_EP_NUM_CALC4, USBD_EP_NUM_CALC5) +#define USBD_EP_NUM_CALC7 MAX((USBD_BULK_ENABLE*(USBD_BULK_EP_BULKIN)), (USBD_BULK_ENABLE*(USBD_BULK_EP_BULKOUT))) +#define USBD_EP_NUM MAX(USBD_EP_NUM_CALC6, USBD_EP_NUM_CALC7) + +#if (USBD_HID_ENABLE) +#if (USBD_MSC_ENABLE) +#if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_MSC_EP_BULKOUT))) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKOUT))) +#error "HID and Mass Storage Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_ADC_ENABLE) +#if ((USBD_HID_EP_INTIN == USBD_ADC_EP_ISOOUT) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_ADC_EP_ISOOUT))) +#error "HID and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (((USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKOUT))|| \ + ((USBD_HID_EP_INTOUT != 0) && \ + ((USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKOUT)))) +#error "HID and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_MSC_ENABLE) +#if (USBD_ADC_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_ADC_EP_ISOOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_ADC_EP_ISOOUT)) +#error "Mass Storage Device and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Mass Storage Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_ADC_ENABLE) +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Audio Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#define USBD_ADC_CIF_NUM (0) +#define USBD_ADC_SIF1_NUM (1) +#define USBD_ADC_SIF2_NUM (2) + +#define USBD_ADC_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+0) +#define USBD_ADC_SIF1_STR_NUM (3+USBD_STRDESC_SER_ENABLE+1) +#define USBD_ADC_SIF2_STR_NUM (3+USBD_STRDESC_SER_ENABLE+2) +#define USBD_CDC_ACM_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+0) +#define USBD_CDC_ACM_DIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+1) +#define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) +#define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) +#define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) + +#if (USBD_HID_ENABLE) +#if (USBD_HID_HS_ENABLE) +#define USBD_HID_MAX_PACKET ((USBD_HID_HS_WMAXPACKETSIZE > USBD_HID_WMAXPACKETSIZE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) +#else +#define USBD_HID_MAX_PACKET (USBD_HID_WMAXPACKETSIZE) +#endif +#else +#define USBD_HID_MAX_PACKET (0) +#endif +#if (USBD_MSC_ENABLE) +#if (USBD_MSC_HS_ENABLE) +#define USBD_MSC_MAX_PACKET ((USBD_MSC_HS_WMAXPACKETSIZE > USBD_MSC_WMAXPACKETSIZE) ? USBD_MSC_HS_WMAXPACKETSIZE : USBD_MSC_WMAXPACKETSIZE) +#else +#define USBD_MSC_MAX_PACKET (USBD_MSC_WMAXPACKETSIZE) +#endif +#else +#define USBD_MSC_MAX_PACKET (0) +#endif +#if (USBD_ADC_ENABLE) +#if (USBD_ADC_HS_ENABLE) +#define USBD_ADC_MAX_PACKET ((USBD_ADC_HS_WMAXPACKETSIZE > USBD_ADC_WMAXPACKETSIZE) ? USBD_ADC_HS_WMAXPACKETSIZE : USBD_ADC_WMAXPACKETSIZE) +#else +#define USBD_ADC_MAX_PACKET (USBD_ADC_WMAXPACKETSIZE) +#endif +#else +#define USBD_ADC_MAX_PACKET (0) +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (USBD_CDC_ACM_HS_ENABLE) +#define USBD_CDC_ACM_MAX_PACKET ((USBD_CDC_ACM_HS_WMAXPACKETSIZE > USBD_CDC_ACM_WMAXPACKETSIZE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE : USBD_CDC_ACM_WMAXPACKETSIZE) +#else +#define USBD_CDC_ACM_MAX_PACKET (USBD_CDC_ACM_WMAXPACKETSIZE) +#endif +#if (USBD_CDC_ACM_HS_ENABLE1) +#define USBD_CDC_ACM_MAX_PACKET1 ((USBD_CDC_ACM_HS_WMAXPACKETSIZE1 > USBD_CDC_ACM_WMAXPACKETSIZE1) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE1 : USBD_CDC_ACM_WMAXPACKETSIZE1) +#else +#define USBD_CDC_ACM_MAX_PACKET1 (USBD_CDC_ACM_WMAXPACKETSIZE1) +#endif +#else +#define USBD_CDC_ACM_MAX_PACKET (0) +#define USBD_CDC_ACM_MAX_PACKET1 (0) +#endif +#if (USBD_BULK_ENABLE) +#if (USBD_BULK_HS_ENABLE) +#define USBD_BULK_MAX_PACKET ((USBD_BULK_HS_WMAXPACKETSIZE > USBD_BULK_WMAXPACKETSIZE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) +#else +#define USBD_BULK_MAX_PACKET (USBD_BULK_WMAXPACKETSIZE) +#endif +#else +#define USBD_BULK_MAX_PACKET (0) +#endif +#define USBD_MAX_PACKET_CALC0 ((USBD_HID_MAX_PACKET > USBD_HID_MAX_PACKET ) ? (USBD_HID_MAX_PACKET ) : (USBD_HID_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC1 ((USBD_ADC_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET ) ? (USBD_ADC_MAX_PACKET ) : (USBD_CDC_ACM_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC2 ((USBD_MAX_PACKET_CALC0 > USBD_MAX_PACKET_CALC1 ) ? (USBD_MAX_PACKET_CALC0) : (USBD_MAX_PACKET_CALC1 )) +#define USBD_MAX_PACKET_CALC3 ((USBD_BULK_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET1 ) ? (USBD_BULK_MAX_PACKET) : (USBD_CDC_ACM_MAX_PACKET1 )) +#define USBD_MAX_PACKET ((USBD_MAX_PACKET_CALC3 > USBD_MAX_PACKET_CALC2 ) ? (USBD_MAX_PACKET_CALC3) : (USBD_MAX_PACKET_CALC2 )) + + +/*------------------------------------------------------------------------------ + * USB Config Functions + *----------------------------------------------------------------------------*/ + +#ifndef __USB_CONFIG___ +#define __USB_CONFIG__ + +#ifndef __NO_USB_LIB_C +#include "usb_lib.c" +#endif + +#endif /* __USB_CONFIG__ */ diff --git a/source/hic_hal/nxp/lpc55xx/usb_misc.h b/source/hic_hal/nxp/lpc55xx/usb_misc.h new file mode 100644 index 000000000..28a7aa705 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/usb_misc.h @@ -0,0 +1,496 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016, 2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __USB_MISC_H__ +#define __USB_MISC_H__ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Define big endian */ +#define USB_BIG_ENDIAN (0U) +/*! @brief Define little endian */ +#define USB_LITTLE_ENDIAN (1U) + +/*! @brief Define current endian */ +#ifndef ENDIANNESS +#define ENDIANNESS USB_LITTLE_ENDIAN +#endif +/*! @brief Define default timeout value */ +#if (defined(USE_RTOS) && (USE_RTOS > 0)) +#define USB_OSA_WAIT_TIMEOUT (osaWaitForever_c) +#else +#define USB_OSA_WAIT_TIMEOUT (0U) +#endif /* (defined(USE_RTOS) && (USE_RTOS > 0)) */ + +/*! @brief Define USB printf */ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +extern int DbgConsole_Printf(const char *fmt_s, ...); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#ifndef __DSC__ +#if defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE < 1) +#define usb_echo printf +#else +#define usb_echo DbgConsole_Printf +#endif +#else +#define usb_echo +#endif + +#if defined(__ICCARM__) + +#ifndef STRUCT_PACKED +#define STRUCT_PACKED __packed +#endif + +#ifndef STRUCT_UNPACKED +#define STRUCT_UNPACKED +#endif + +#elif defined(__GNUC__) + +#ifndef STRUCT_PACKED +#define STRUCT_PACKED +#endif + +#ifndef STRUCT_UNPACKED +#define STRUCT_UNPACKED __attribute__((__packed__)) +#endif + +#elif defined(__CC_ARM) || (defined(__ARMCC_VERSION)) + +#ifndef STRUCT_PACKED +#define STRUCT_PACKED _Pragma("pack(1U)") +#endif + +#ifndef STRUCT_UNPACKED +#define STRUCT_UNPACKED _Pragma("pack()") +#endif + +#endif + +#define USB_SHORT_GET_LOW(x) (((uint16_t)x) & 0xFFU) +#define USB_SHORT_GET_HIGH(x) ((uint8_t)(((uint16_t)x) >> 8U) & 0xFFU) + +#define USB_LONG_GET_BYTE0(x) ((uint8_t)(((uint32_t)(x))) & 0xFFU) +#define USB_LONG_GET_BYTE1(x) ((uint8_t)(((uint32_t)(x)) >> 8U) & 0xFFU) +#define USB_LONG_GET_BYTE2(x) ((uint8_t)(((uint32_t)(x)) >> 16U) & 0xFFU) +#define USB_LONG_GET_BYTE3(x) ((uint8_t)(((uint32_t)(x)) >> 24U) & 0xFFU) + +#define USB_MEM4_ALIGN_MASK (0x03U) + +/* accessory macro */ +#define USB_MEM4_ALIGN(n) ((n + 3U) & (0xFFFFFFFCu)) +#define USB_MEM32_ALIGN(n) ((n + 31U) & (0xFFFFFFE0u)) +#define USB_MEM64_ALIGN(n) ((n + 63U) & (0xFFFFFFC0u)) + +/* big/little endian */ +#define SWAP2BYTE_CONST(n) ((((n)&0x00FFU) << 8U) | (((n)&0xFF00U) >> 8U)) +#define SWAP4BYTE_CONST(n) \ + ((((n)&0x000000FFU) << 24U) | (((n)&0x0000FF00U) << 8U) | (((n)&0x00FF0000U) >> 8U) | (((n)&0xFF000000U) >> 24U)) + +#define USB_ASSIGN_VALUE_ADDRESS_LONG_BY_BYTE(n, m) \ + { \ + *((uint8_t *)&(n)) = *((uint8_t *)&(m)); \ + *((uint8_t *)&(n) + 1) = *((uint8_t *)&(m) + 1); \ + *((uint8_t *)&(n) + 2) = *((uint8_t *)&(m) + 2); \ + *((uint8_t *)&(n) + 3) = *((uint8_t *)&(m) + 3); \ + } + +#define USB_ASSIGN_VALUE_ADDRESS_SHORT_BY_BYTE(n, m) \ + { \ + *((uint8_t *)&(n)) = *((uint8_t *)&(m)); \ + *((uint8_t *)&(n) + 1) = *((uint8_t *)&(m) + 1); \ + } + +#define USB_ASSIGN_MACRO_VALUE_ADDRESS_LONG_BY_BYTE(n, m) \ + { \ + *((uint8_t *)&(n)) = (uint8_t)m; \ + *((uint8_t *)&(n) + 1) = (uint8_t)(m >> 8); \ + *((uint8_t *)&(n) + 2) = (uint8_t)(m >> 16); \ + *((uint8_t *)&(n) + 3) = (uint8_t)(m >> 24); \ + } + +#define USB_ASSIGN_MACRO_VALUE_ADDRESS_SHORT_BY_BYTE(n, m) \ + { \ + *((uint8_t *)&(n)) = (uint8_t)m; \ + *((uint8_t *)&(n) + 1) = (uint8_t)(m >> 8); \ + } + +#if (ENDIANNESS == USB_BIG_ENDIAN) + +#define USB_SHORT_TO_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n) +#define USB_LONG_TO_LITTLE_ENDIAN(n) SWAP4BYTE_CONST(n) +#define USB_SHORT_FROM_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n) +#define USB_LONG_FROM_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n) + +#define USB_SHORT_TO_BIG_ENDIAN(n) (n) +#define USB_LONG_TO_BIG_ENDIAN(n) (n) +#define USB_SHORT_FROM_BIG_ENDIAN(n) (n) +#define USB_LONG_FROM_BIG_ENDIAN(n) (n) + +#define USB_LONG_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ + { \ + m[3] = (uint8_t)((((uint32_t)(n)) >> 24U) & 0xFFU); \ + m[2] = (uint8_t)((((uint32_t)(n)) >> 16U) & 0xFFU); \ + m[1] = (uint8_t)((((uint32_t)(n)) >> 8U) & 0xFFU); \ + m[0] = (uint8_t)(((uint32_t)(n)) & 0xFFU); \ + } + +#define USB_LONG_FROM_LITTLE_ENDIAN_ADDRESS(n) \ + ((uint32_t)((((uint32_t)n[3]) << 24U) | (((uint32_t)n[2]) << 16U) | (((uint32_t)n[1]) << 8U) | \ + (((uint32_t)n[0]) << 0U))) + +#define USB_LONG_TO_BIG_ENDIAN_ADDRESS(n, m) \ + { \ + m[0] = ((((uint32_t)(n)) >> 24U) & 0xFFU); \ + m[1] = ((((uint32_t)(n)) >> 16U) & 0xFFU); \ + m[2] = ((((uint32_t)(n)) >> 8U) & 0xFFU); \ + m[3] = (((uint32_t)(n)) & 0xFFU); \ + } + +#define USB_LONG_FROM_BIG_ENDIAN_ADDRESS(n) \ + ((uint32_t)((((uint32_t)n[0]) << 24U) | (((uint32_t)n[1]) << 16U) | (((uint32_t)n[2]) << 8U) | \ + (((uint32_t)n[3]) << 0U))) + +#define USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ + { \ + m[1] = ((((uint16_t)(n)) >> 8U) & 0xFFU); \ + m[0] = (((uint16_t)(n)) & 0xFFU); \ + } + +#define USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(n) ((uint16_t)((((uint16_t)n[1]) << 8U) | (((uint16_t)n[0]) << 0U))) + +#define USB_SHORT_TO_BIG_ENDIAN_ADDRESS(n, m) \ + { \ + m[0] = ((((uint16_t)(n)) >> 8U) & 0xFFU); \ + m[1] = (((uint16_t)(n)) & 0xFFU); \ + } + +#define USB_SHORT_FROM_BIG_ENDIAN_ADDRESS(n) ((uint16_t)((((uint16_t)n[0]) << 8U) | (((uint16_t)n[1]) << 0U))) + +#define USB_LONG_TO_LITTLE_ENDIAN_DATA(n, m) \ + { \ + *((uint8_t *)&(m) + 3) = ((((uint32_t)(n)) >> 24U) & 0xFFU); \ + *((uint8_t *)&(m) + 2) = ((((uint32_t)(n)) >> 16U) & 0xFFU); \ + *((uint8_t *)&(m) + 1) = ((((uint32_t)(n)) >> 8U) & 0xFFU); \ + *((uint8_t *)&(m) + 0) = (((uint32_t)(n)) & 0xFFU); \ + } + +#define USB_LONG_FROM_LITTLE_ENDIAN_DATA(n) \ + ((uint32_t)(((uint32_t)(*((uint8_t *)&(n) + 3)) << 24U) | ((uint32_t)(*((uint8_t *)&(n) + 2)) << 16U) | \ + ((uint32_t)(*((uint8_t *)&(n) + 1)) << 8U) | ((uint32_t)(*((uint8_t *)&(n))) << 0U))) + +#define USB_SHORT_TO_LITTLE_ENDIAN_DATA(n, m) \ + { \ + *((uint8_t *)&(m) + 1) = ((((uint16_t)(n)) >> 8U) & 0xFFU); \ + *((uint8_t *)&(m)) = ((((uint16_t)(n))) & 0xFFU); \ + } + +#define USB_SHORT_FROM_LITTLE_ENDIAN_DATA(n) \ + ((uint16_t)((uint16_t)(*((uint8_t *)&(n) + 1)) << 8U) | ((uint16_t)(*((uint8_t *)&(n))))) + +#else + +#define USB_SHORT_TO_LITTLE_ENDIAN(n) (n) +#define USB_LONG_TO_LITTLE_ENDIAN(n) (n) +#define USB_SHORT_FROM_LITTLE_ENDIAN(n) (n) +#define USB_LONG_FROM_LITTLE_ENDIAN(n) (n) + +#define USB_SHORT_TO_BIG_ENDIAN(n) SWAP2BYTE_CONST(n) +#define USB_LONG_TO_BIG_ENDIAN(n) SWAP4BYTE_CONST(n) +#define USB_SHORT_FROM_BIG_ENDIAN(n) SWAP2BYTE_CONST(n) +#define USB_LONG_FROM_BIG_ENDIAN(n) SWAP4BYTE_CONST(n) + +#define USB_LONG_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ + { \ + m[3] = (uint8_t)((((uint32_t)(n)) >> 24U) & 0xFFU); \ + m[2] = (uint8_t)((((uint32_t)(n)) >> 16U) & 0xFFU); \ + m[1] = (uint8_t)((((uint32_t)(n)) >> 8U) & 0xFFU); \ + m[0] = (uint8_t)(((uint32_t)(n)) & 0xFFU); \ + } + +#define USB_LONG_FROM_LITTLE_ENDIAN_ADDRESS(n) \ + ((uint32_t)((((uint32_t)n[3]) << 24U) | (((uint32_t)n[2]) << 16U) | (((uint32_t)n[1]) << 8U) | \ + (((uint32_t)n[0]) << 0U))) + +#define USB_LONG_TO_BIG_ENDIAN_ADDRESS(n, m) \ + { \ + m[0] = ((((uint32_t)(n)) >> 24U) & 0xFFU); \ + m[1] = ((((uint32_t)(n)) >> 16U) & 0xFFU); \ + m[2] = ((((uint32_t)(n)) >> 8U) & 0xFFU); \ + m[3] = (((uint32_t)(n)) & 0xFFU); \ + } + +#define USB_LONG_FROM_BIG_ENDIAN_ADDRESS(n) \ + ((uint32_t)((((uint32_t)n[0]) << 24U) | (((uint32_t)n[1]) << 16U) | (((uint32_t)n[2]) << 8U) | \ + (((uint32_t)n[3]) << 0U))) + +#define USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ + { \ + m[1] = ((((uint16_t)(n)) >> 8U) & 0xFFU); \ + m[0] = (((uint16_t)(n)) & 0xFFU); \ + } + +#define USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(n) ((uint16_t)((((uint16_t)n[1]) << 8U) | (((uint16_t)n[0]) << 0U))) + +#define USB_SHORT_TO_BIG_ENDIAN_ADDRESS(n, m) \ + { \ + m[0] = ((((uint16_t)(n)) >> 8U) & 0xFFU); \ + m[1] = (((uint16_t)(n)) & 0xFFU); \ + } + +#define USB_SHORT_FROM_BIG_ENDIAN_ADDRESS(n) ((uint16_t)((((uint16_t)n[0]) << 8U) | (((uint16_t)n[1]) << 0U))) + +#define USB_LONG_TO_LITTLE_ENDIAN_DATA(n, m) \ + { \ + *((uint8_t *)&(m) + 3) = ((((uint32_t)(n)) >> 24U) & 0xFFU); \ + *((uint8_t *)&(m) + 2) = ((((uint32_t)(n)) >> 16U) & 0xFFU); \ + *((uint8_t *)&(m) + 1) = ((((uint32_t)(n)) >> 8U) & 0xFFU); \ + *((uint8_t *)&(m) + 0) = (((uint32_t)(n)) & 0xFFU); \ + } + +#define USB_LONG_FROM_LITTLE_ENDIAN_DATA(n) \ + ((uint32_t)(((uint32_t)(*((uint8_t *)&(n) + 3)) << 24U) | ((uint32_t)(*((uint8_t *)&(n) + 2)) << 16U) | \ + ((uint32_t)(*((uint8_t *)&(n) + 1)) << 8U) | ((uint32_t)(*((uint8_t *)&(n))) << 0U))) + +#define USB_SHORT_TO_LITTLE_ENDIAN_DATA(n, m) \ + { \ + *((uint8_t *)&(m) + 1) = ((((uint16_t)(n)) >> 8U) & 0xFFU); \ + *((uint8_t *)&(m)) = ((((uint16_t)(n))) & 0xFFU); \ + } + +#define USB_SHORT_FROM_LITTLE_ENDIAN_DATA(n) \ + ((uint16_t)(((uint16_t)(*(((uint8_t *)&(n)) + 1)) << 8U) | ((uint16_t)(*((uint8_t *)&(n)))))) + +#endif + +/* + * The following MACROs (USB_GLOBAL, USB_BDT, USB_RAM_ADDRESS_ALIGNMENT, etc) are only used for USB device stack. + * The USB device global variables are put into the section m_usb_global and m_usb_bdt + * by using the MACRO USB_GLOBAL and USB_BDT. In this way, the USB device + * global variables can be linked into USB dedicated RAM by USB_STACK_USE_DEDICATED_RAM. + * The MACRO USB_STACK_USE_DEDICATED_RAM is used to decide the USB stack uses dedicated RAM or not. The value of + * the macro can be set as 0, USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL, or USB_STACK_DEDICATED_RAM_TYPE_BDT. + * The MACRO USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL means USB device global variables, including USB_BDT and + * USB_GLOBAL, are put into the USB dedicated RAM. This feature can only be enabled when the USB dedicated RAM + * is not less than 2K Bytes. + * The MACRO USB_STACK_DEDICATED_RAM_TYPE_BDT means USB device global variables, only including USB_BDT, are put + * into the USB dedicated RAM, the USB_GLOBAL will be put into .bss section. This feature is used for some SOCs, + * the USB dedicated RAM size is not more than 512 Bytes. + */ +#define USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL 1 +#define USB_STACK_DEDICATED_RAM_TYPE_BDT 2 + +#if defined(__ICCARM__) + +#define USB_WEAK_VAR __attribute__((weak)) +#define USB_WEAK_FUN __attribute__((weak)) +/* disable misra 19.13 */ +_Pragma("diag_suppress=Pm120") +#define USB_ALIGN_PRAGMA(x) _Pragma(#x) + _Pragma("diag_default=Pm120") + +#define USB_RAM_ADDRESS_ALIGNMENT(n) USB_ALIGN_PRAGMA(data_alignment = n) + _Pragma("diag_suppress=Pm120") +#define USB_LINK_SECTION_PART(str) _Pragma(#str) +#define USB_LINK_DMA_INIT_DATA(sec) USB_LINK_SECTION_PART(location = #sec) +#define USB_LINK_USB_GLOBAL _Pragma("location = \"m_usb_global\"") +#define USB_LINK_USB_BDT _Pragma("location = \"m_usb_bdt\"") +#define USB_LINK_USB_GLOBAL_BSS +#define USB_LINK_USB_BDT_BSS + _Pragma("diag_default=Pm120") +#define USB_LINK_DMA_NONINIT_DATA _Pragma("location = \"m_usb_dma_noninit_data\"") +#define USB_LINK_NONCACHE_NONINIT_DATA _Pragma("location = \"NonCacheable\"") +#elif defined(__CC_ARM) || (defined(__ARMCC_VERSION)) + +#define USB_WEAK_VAR __attribute__((weak)) +#define USB_WEAK_FUN __attribute__((weak)) +#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n))) +#define USB_LINK_DMA_INIT_DATA(sec) __attribute__((section(#sec))) +#if defined(__CC_ARM) +#define USB_LINK_USB_GLOBAL __attribute__((section("m_usb_global"))) __attribute__((zero_init)) +#else +#define USB_LINK_USB_GLOBAL __attribute__((section(".bss.m_usb_global"))) +#endif +#if defined(__CC_ARM) +#define USB_LINK_USB_BDT __attribute__((section("m_usb_bdt"))) __attribute__((zero_init)) +#else +#define USB_LINK_USB_BDT __attribute__((section(".bss.m_usb_bdt"))) +#endif +#define USB_LINK_USB_GLOBAL_BSS +#define USB_LINK_USB_BDT_BSS +#if defined(__CC_ARM) +#define USB_LINK_DMA_NONINIT_DATA __attribute__((section("m_usb_dma_noninit_data"))) __attribute__((zero_init)) +#else +#define USB_LINK_DMA_NONINIT_DATA __attribute__((section(".bss.m_usb_dma_noninit_data"))) +#endif +#if defined(__CC_ARM) +#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable"))) __attribute__((zero_init)) +#else +#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section(".bss.NonCacheable"))) +#endif + +#elif defined(__GNUC__) + +#define USB_WEAK_VAR __attribute__((weak)) +#define USB_WEAK_FUN __attribute__((weak)) +#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n))) +#define USB_LINK_DMA_INIT_DATA(sec) __attribute__((section(#sec))) +#define USB_LINK_USB_GLOBAL __attribute__((section("m_usb_global, \"aw\", %nobits @"))) +#define USB_LINK_USB_BDT __attribute__((section("m_usb_bdt, \"aw\", %nobits @"))) +#define USB_LINK_USB_GLOBAL_BSS +#define USB_LINK_USB_BDT_BSS +#define USB_LINK_DMA_NONINIT_DATA __attribute__((section("m_usb_dma_noninit_data, \"aw\", %nobits @"))) +#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable, \"aw\", %nobits @"))) + +#elif (defined(__DSC__) && defined(__CW__)) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#define USB_WEAK_VAR __attribute__((weak)) +#define USB_WEAK_FUN __attribute__((weak)) +#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n))) +#define USB_LINK_USB_BDT_BSS +#define USB_LINK_USB_GLOBAL_BSS +#else +#error The tool-chain is not supported. +#endif + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) + +#if ((defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)) && (defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) +#define USB_CACHE_LINESIZE MAX(FSL_FEATURE_L2CACHE_LINESIZE_BYTE, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#elif (defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)) +#define USB_CACHE_LINESIZE MAX(FSL_FEATURE_L2CACHE_LINESIZE_BYTE, 0) +#elif (defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)) +#define USB_CACHE_LINESIZE MAX(0, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#else +#define USB_CACHE_LINESIZE 4U +#endif + +#else +#define USB_CACHE_LINESIZE 4U +#endif + +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +#define USB_DATA_ALIGN 64U +#else +#define USB_DATA_ALIGN 4U +#endif + +#if (USB_CACHE_LINESIZE > USB_DATA_ALIGN) +#define USB_DATA_ALIGN_SIZE USB_CACHE_LINESIZE +#else +#define USB_DATA_ALIGN_SIZE USB_DATA_ALIGN +#endif + +#define USB_DATA_ALIGN_SIZE_MULTIPLE(n) (((n) + USB_DATA_ALIGN_SIZE - 1U) & (~(USB_DATA_ALIGN_SIZE - 1U))) + +#if defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM == USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL) + +#define USB_GLOBAL USB_LINK_USB_GLOBAL +#define USB_BDT USB_LINK_USB_BDT + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) +#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA +#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(m_usb_dma_init_data) +#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA +#else +#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE)) +#define USB_DMA_DATA_NONINIT_SUB USB_LINK_NONCACHE_NONINIT_DATA +#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(NonCacheable.init) +#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA +#else +#define USB_DMA_DATA_NONINIT_SUB +#define USB_DMA_DATA_INIT_SUB +#define USB_CONTROLLER_DATA USB_LINK_USB_GLOBAL +#endif +#endif + +#elif defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM == USB_STACK_DEDICATED_RAM_TYPE_BDT) + +#define USB_BDT USB_LINK_USB_BDT + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) +#define USB_GLOBAL USB_LINK_DMA_NONINIT_DATA +#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA +#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(m_usb_dma_init_data) +#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA +#else +#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE)) +#define USB_GLOBAL USB_LINK_NONCACHE_NONINIT_DATA +#define USB_DMA_DATA_NONINIT_SUB USB_LINK_NONCACHE_NONINIT_DATA +#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(NonCacheable.init) +#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA +#else +#define USB_GLOBAL USB_LINK_USB_GLOBAL_BSS +#define USB_DMA_DATA_NONINIT_SUB +#define USB_DMA_DATA_INIT_SUB +#define USB_CONTROLLER_DATA +#endif +#endif + +#else + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) + +#define USB_GLOBAL USB_LINK_DMA_NONINIT_DATA +#define USB_BDT USB_LINK_NONCACHE_NONINIT_DATA +#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA +#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(m_usb_dma_init_data) +#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA + +#else + +#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE)) +#define USB_GLOBAL USB_LINK_NONCACHE_NONINIT_DATA +#define USB_BDT USB_LINK_NONCACHE_NONINIT_DATA +#define USB_DMA_DATA_NONINIT_SUB USB_LINK_NONCACHE_NONINIT_DATA +#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(NonCacheable.init) +#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA +#else +#define USB_GLOBAL USB_LINK_USB_GLOBAL_BSS +#define USB_BDT USB_LINK_USB_BDT_BSS +#define USB_DMA_DATA_NONINIT_SUB +#define USB_DMA_DATA_INIT_SUB +#define USB_CONTROLLER_DATA +#endif + +#endif + +#endif + +#define USB_DMA_NONINIT_DATA_ALIGN(n) USB_RAM_ADDRESS_ALIGNMENT(n) USB_DMA_DATA_NONINIT_SUB +#define USB_DMA_INIT_DATA_ALIGN(n) USB_RAM_ADDRESS_ALIGNMENT(n) USB_DMA_DATA_INIT_SUB + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) +#define USB_DMA_DATA_NONCACHEABLE USB_LINK_NONCACHE_NONINIT_DATA + +#else +#define USB_DMA_DATA_NONCACHEABLE +#endif + +#define USB_GLOBAL_DEDICATED_RAM USB_LINK_USB_GLOBAL + +/* #define USB_RAM_ADDRESS_NONCACHEREG_ALIGNMENT(n, var) AT_NONCACHEABLE_SECTION_ALIGN(var, n) */ +/* #define USB_RAM_ADDRESS_NONCACHEREG(var) AT_NONCACHEABLE_SECTION(var) */ + +#endif /* __USB_MISC_H__ */ diff --git a/source/hic_hal/nxp/lpc55xx/usb_phy.c b/source/hic_hal/nxp/lpc55xx/usb_phy.c new file mode 100644 index 000000000..1e198311f --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/usb_phy.c @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_usb.h" +#include "fsl_device_registers.h" + +#include "usb_phy.h" + +void *USB_EhciPhyGetBase(uint8_t controllerId) +{ + void *usbPhyBase = NULL; +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + uint32_t instance; + uint32_t newinstance = 0; + uint32_t usbphy_base_temp[] = USBPHY_BASE_ADDRS; + uint32_t usbphy_base[] = USBPHY_BASE_ADDRS; + uint32_t *temp; + if (controllerId < (uint8_t)kUSB_ControllerEhci0) + { + return NULL; + } + + if ((controllerId == (uint8_t)kUSB_ControllerEhci0) || (controllerId == (uint8_t)kUSB_ControllerEhci1)) + { + controllerId = controllerId - (uint8_t)kUSB_ControllerEhci0; + } + else if ((controllerId == (uint8_t)kUSB_ControllerLpcIp3511Hs0) || + (controllerId == (uint8_t)kUSB_ControllerLpcIp3511Hs1)) + { + controllerId = controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0; + } + else if ((controllerId == (uint8_t)kUSB_ControllerIp3516Hs0) || (controllerId == (uint8_t)kUSB_ControllerIp3516Hs1)) + { + controllerId = controllerId - (uint8_t)kUSB_ControllerIp3516Hs0; + } + else + { + /*no action*/ + } + + for (instance = 0; instance < (sizeof(usbphy_base_temp) / sizeof(usbphy_base_temp[0])); instance++) + { + if (0U != usbphy_base_temp[instance]) + { + usbphy_base[newinstance++] = usbphy_base_temp[instance]; + } + } + if (controllerId > newinstance) + { + return NULL; + } + temp = (uint32_t *)usbphy_base[controllerId]; + usbPhyBase = (void *)temp; +#endif + return usbPhyBase; +} + +/*! + * @brief ehci phy initialization. + * + * This function initialize ehci phy IP. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] freq the external input clock. + * for example: if the external input clock is 16M, the parameter freq should be 16000000. + * + * @retval kStatus_USB_Success cancel successfully. + * @retval kStatus_USB_Error the freq value is incorrect. + */ +uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return (uint8_t)kStatus_USB_Error; + } + +#if ((defined FSL_FEATURE_SOC_ANATOP_COUNT) && (FSL_FEATURE_SOC_ANATOP_COUNT > 0U)) + ANATOP->HW_ANADIG_REG_3P0.RW = + (ANATOP->HW_ANADIG_REG_3P0.RW & + (~(ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x1F) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_ILIMIT_MASK))) | + ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x17) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_LINREG_MASK; + ANATOP->HW_ANADIG_USB2_CHRG_DETECT.SET = + ANATOP_HW_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B_MASK | ANATOP_HW_ANADIG_USB2_CHRG_DETECT_EN_B_MASK; +#endif + +#if (defined USB_ANALOG) + USB_ANALOG->INSTANCE[controllerId - (uint8_t)kUSB_ControllerEhci0].CHRG_DETECT_SET = + USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(1) | USB_ANALOG_CHRG_DETECT_EN_B(1); +#endif + +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + + usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */ +#endif + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */ + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */ + /* PWD register provides overall control of the PHY power state */ + usbPhyBase->PWD = 0U; + if (((uint8_t)kUSB_ControllerIp3516Hs0 == controllerId) || ((uint8_t)kUSB_ControllerIp3516Hs1 == controllerId) || + ((uint8_t)kUSB_ControllerLpcIp3511Hs0 == controllerId) || + ((uint8_t)kUSB_ControllerLpcIp3511Hs1 == controllerId)) + { + usbPhyBase->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK; + usbPhyBase->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK; + } + if (NULL != phyConfig) + { + /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */ + usbPhyBase->TX = + ((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) | + (USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) | + USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM))); + } +#endif + + return (uint8_t)kStatus_USB_Success; +} + +/*! + * @brief ehci phy initialization for suspend and resume. + * + * This function initialize ehci phy IP for suspend and resume. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] freq the external input clock. + * for example: if the external input clock is 16M, the parameter freq should be 16000000. + * + * @retval kStatus_USB_Success cancel successfully. + * @retval kStatus_USB_Error the freq value is incorrect. + */ +uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return (uint8_t)kStatus_USB_Error; + } + +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */ +#endif + +#if ((defined USBPHY_CTRL_AUTORESUME_EN_MASK) && (USBPHY_CTRL_AUTORESUME_EN_MASK > 0U)) + usbPhyBase->CTRL |= USBPHY_CTRL_AUTORESUME_EN_MASK; +#else + usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK; +#endif + usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK; + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */ + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */ + /* PWD register provides overall control of the PHY power state */ + usbPhyBase->PWD = 0U; +#if (defined USBPHY_ANACTRL_PFD_CLKGATE_MASK) + /* now the 480MHz USB clock is up, then configure fractional divider after PLL with PFD + * pfd clock = 480MHz*18/N, where N=18~35 + * Please note that USB1PFDCLK has to be less than 180MHz for RUN or HSRUN mode + */ + usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_FRAC(24); /* N=24 */ + usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_CLK_SEL(1); /* div by 4 */ + + usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_DEV_PULLDOWN_MASK; + usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_PFD_CLKGATE_MASK; + while (0U == (usbPhyBase->ANACTRL & USBPHY_ANACTRL_PFD_STABLE_MASK)) + { + } +#endif + if (NULL != phyConfig) + { + /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */ + usbPhyBase->TX = + ((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) | + (USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) | + USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM))); + } +#endif + + return (uint8_t)kStatus_USB_Success; +} + +/*! + * @brief ehci phy de-initialization. + * + * This function de-initialize ehci phy IP. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + */ +void USB_EhciPhyDeinit(uint8_t controllerId) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return; + } +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; /* power down PLL */ + usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* disable USB clock output from USB PHY PLL */ +#endif + usbPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* set to 1U to gate clocks */ +#endif +} + +/*! + * @brief ehci phy disconnect detection enable or disable. + * + * This function enable/disable host ehci disconnect detection. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] enable + * 1U - enable; + * 0U - disable; + */ +void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return; + } + + if (0U != enable) + { + usbPhyBase->CTRL |= USBPHY_CTRL_ENHOSTDISCONDETECT_MASK; + } + else + { + usbPhyBase->CTRL &= (~USBPHY_CTRL_ENHOSTDISCONDETECT_MASK); + } +#endif +} + +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) +#if ((defined FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE) && (FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE > 0U)) +void USB_PhyDeviceForceEnterFSMode(uint8_t controllerId, uint8_t enable) +{ + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return; + } + + if (0U != enable) + { + uint32_t delay = 1000000; + usbPhyBase->DEBUG0_CLR = USBPHY_DEBUG0_CLKGATE_MASK; + while ((0U != (usbPhyBase->USB1_VBUS_DET_STAT & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)) && (0U != delay)) + { + delay--; + } + usbPhyBase->USB1_LOOPBACK_SET = USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK; + } + else + { + usbPhyBase->DEBUG0_CLR = USBPHY_DEBUG0_CLKGATE_MASK; + usbPhyBase->USB1_LOOPBACK_CLR = USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK; + } +} +#endif +#endif diff --git a/source/hic_hal/nxp/lpc55xx/usb_phy.h b/source/hic_hal/nxp/lpc55xx/usb_phy.h new file mode 100644 index 000000000..014740711 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/usb_phy.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __USB_PHY_H__ +#define __USB_PHY_H__ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +typedef struct _usb_phy_config_struct +{ + uint8_t D_CAL; /* Decode to trim the nominal 17.78mA current source */ + uint8_t TXCAL45DP; /* Decode to trim the nominal 45-Ohm series termination resistance to the USB_DP output pin */ + uint8_t TXCAL45DM; /* Decode to trim the nominal 45-Ohm series termination resistance to the USB_DM output pin */ +} usb_phy_config_struct_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @brief EHCI PHY get USB phy bass address. + * + * This function is used to get USB phy bass address. + * + * @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. + * + * @retval USB phy bass address. + */ +extern void *USB_EhciPhyGetBase(uint8_t controllerId); + +/*! + * @brief EHCI PHY initialization. + * + * This function initializes the EHCI PHY IP. + * + * @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. + * @param[in] freq The external input clock. + * + * @retval kStatus_USB_Success Cancel successfully. + * @retval kStatus_USB_Error The freq value is incorrect. + */ +extern uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig); + +/*! + * @brief ehci phy initialization for suspend and resume. + * + * This function initialize ehci phy IP for suspend and resume. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] freq the external input clock. + * for example: if the external input clock is 16M, the parameter freq should be 16000000. + * + * @retval kStatus_USB_Success cancel successfully. + * @retval kStatus_USB_Error the freq value is incorrect. + */ +extern uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig); + +/*! + * @brief EHCI PHY deinitialization. + * + * This function deinitializes the EHCI PHY IP. + * + * @param[in] controllerId EHCI controller ID; See #usb_controller_index_t. + */ +extern void USB_EhciPhyDeinit(uint8_t controllerId); + +/*! + * @brief EHCI PHY disconnect detection enable or disable. + * + * This function enable/disable the host EHCI disconnect detection. + * + * @param[in] controllerId EHCI controller ID; See #usb_controller_index_t. + * @param[in] enable + * 1U - enable; + * 0U - disable; + */ +extern void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable); +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) +#if ((defined FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE) && (FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE > 0U)) +/*! + * @brief Force the PHY enter FS Mode + * + * on RT500 and RT600, the device doesn't enter FS Mode after vbus is invalide and the controller works as HS. + * + * @param[in] controllerId EHCI controller ID; See #usb_controller_index_t. + * @param[in] enable + * 1U - enable; + * 0U - disable; + */ +extern void USB_PhyDeviceForceEnterFSMode(uint8_t controllerId, uint8_t enable); +#endif +#endif +#if defined(__cplusplus) +} +#endif + +#endif /* __USB_PHY_H__ */ diff --git a/source/hic_hal/nxp/lpc55xx/usb_spec.h b/source/hic_hal/nxp/lpc55xx/usb_spec.h new file mode 100644 index 000000000..a642bd518 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/usb_spec.h @@ -0,0 +1,299 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __USB_SPEC_H__ +#define __USB_SPEC_H__ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* USB speed (the value cannot be changed because EHCI QH use the value directly)*/ +#define USB_SPEED_FULL (0x00U) +#define USB_SPEED_LOW (0x01U) +#define USB_SPEED_HIGH (0x02U) +#define USB_SPEED_SUPER (0x04U) + +/* Set up packet structure */ +typedef struct _usb_setup_struct +{ + uint8_t bmRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} usb_setup_struct_t; + +/* USB standard descriptor endpoint type */ +#define USB_ENDPOINT_CONTROL (0x00U) +#define USB_ENDPOINT_ISOCHRONOUS (0x01U) +#define USB_ENDPOINT_BULK (0x02U) +#define USB_ENDPOINT_INTERRUPT (0x03U) + +/* USB standard descriptor transfer direction (cannot change the value because iTD use the value directly) */ +#define USB_OUT (0U) +#define USB_IN (1U) + +/* USB standard descriptor length */ +#define USB_DESCRIPTOR_LENGTH_DEVICE (0x12U) +#define USB_DESCRIPTOR_LENGTH_CONFIGURE (0x09U) +#define USB_DESCRIPTOR_LENGTH_INTERFACE (0x09U) +#define USB_DESCRIPTOR_LENGTH_ENDPOINT (0x07U) +#define USB_DESCRIPTOR_LENGTH_ENDPOINT_COMPANION (0x06U) +#define USB_DESCRIPTOR_LENGTH_DEVICE_QUALITIER (0x0AU) +#define USB_DESCRIPTOR_LENGTH_OTG_DESCRIPTOR (5U) +#define USB_DESCRIPTOR_LENGTH_BOS_DESCRIPTOR (5U) +#define USB_DESCRIPTOR_LENGTH_DEVICE_CAPABILITY_USB20_EXTENSION (0x07U) +#define USB_DESCRIPTOR_LENGTH_DEVICE_CAPABILITY_SUPERSPEED (0x0AU) + +/* USB Device Capability Type Codes */ +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_WIRELESS (0x01U) +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_USB20_EXTENSION (0x02U) +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_SUPERSPEED (0x03U) + +/* USB standard descriptor type */ +#define USB_DESCRIPTOR_TYPE_DEVICE (0x01U) +#define USB_DESCRIPTOR_TYPE_CONFIGURE (0x02U) +#define USB_DESCRIPTOR_TYPE_STRING (0x03U) +#define USB_DESCRIPTOR_TYPE_INTERFACE (0x04U) +#define USB_DESCRIPTOR_TYPE_ENDPOINT (0x05U) +#define USB_DESCRIPTOR_TYPE_DEVICE_QUALITIER (0x06U) +#define USB_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION (0x07U) +#define USB_DESCRIPTOR_TYPE_INTERFAACE_POWER (0x08U) +#define USB_DESCRIPTOR_TYPE_OTG (0x09U) +#define USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION (0x0BU) +#define USB_DESCRIPTOR_TYPE_BOS (0x0F) +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY (0x10) + +#define USB_DESCRIPTOR_TYPE_HID (0x21U) +#define USB_DESCRIPTOR_TYPE_HID_REPORT (0x22U) +#define USB_DESCRIPTOR_TYPE_HID_PHYSICAL (0x23U) + +#define USB_DESCRIPTOR_TYPE_ENDPOINT_COMPANION (0x30U) + +/* USB standard request type */ +#define USB_REQUEST_TYPE_DIR_MASK (0x80U) +#define USB_REQUEST_TYPE_DIR_SHIFT (7U) +#define USB_REQUEST_TYPE_DIR_OUT (0x00U) +#define USB_REQUEST_TYPE_DIR_IN (0x80U) + +#define USB_REQUEST_TYPE_TYPE_MASK (0x60U) +#define USB_REQUEST_TYPE_TYPE_SHIFT (5U) +#define USB_REQUEST_TYPE_TYPE_STANDARD (0U) +#define USB_REQUEST_TYPE_TYPE_CLASS (0x20U) +#define USB_REQUEST_TYPE_TYPE_VENDOR (0x40U) + +#define USB_REQUEST_TYPE_RECIPIENT_MASK (0x1FU) +#define USB_REQUEST_TYPE_RECIPIENT_SHIFT (0U) +#define USB_REQUEST_TYPE_RECIPIENT_DEVICE (0x00U) +#define USB_REQUEST_TYPE_RECIPIENT_INTERFACE (0x01U) +#define USB_REQUEST_TYPE_RECIPIENT_ENDPOINT (0x02U) +#define USB_REQUEST_TYPE_RECIPIENT_OTHER (0x03U) + +/* USB standard request */ +#define USB_REQUEST_STANDARD_GET_STATUS (0x00U) +#define USB_REQUEST_STANDARD_CLEAR_FEATURE (0x01U) +#define USB_REQUEST_STANDARD_SET_FEATURE (0x03U) +#define USB_REQUEST_STANDARD_SET_ADDRESS (0x05U) +#define USB_REQUEST_STANDARD_GET_DESCRIPTOR (0x06U) +#define USB_REQUEST_STANDARD_SET_DESCRIPTOR (0x07U) +#define USB_REQUEST_STANDARD_GET_CONFIGURATION (0x08U) +#define USB_REQUEST_STANDARD_SET_CONFIGURATION (0x09U) +#define USB_REQUEST_STANDARD_GET_INTERFACE (0x0AU) +#define USB_REQUEST_STANDARD_SET_INTERFACE (0x0BU) +#define USB_REQUEST_STANDARD_SYNCH_FRAME (0x0CU) + +/* USB standard request GET Status */ +#define USB_REQUEST_STANDARD_GET_STATUS_DEVICE_SELF_POWERED_SHIFT (0U) +#define USB_REQUEST_STANDARD_GET_STATUS_DEVICE_REMOTE_WARKUP_SHIFT (1U) + +#define USB_REQUEST_STANDARD_GET_STATUS_ENDPOINT_HALT_MASK (0x01U) +#define USB_REQUEST_STANDARD_GET_STATUS_ENDPOINT_HALT_SHIFT (0U) + +#define USB_REQUEST_STANDARD_GET_STATUS_OTG_STATUS_SELECTOR (0xF000U) + +/* USB standard request CLEAR/SET feature */ +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_ENDPOINT_HALT (0U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_REMOTE_WAKEUP (1U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_TEST_MODE (2U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_B_HNP_ENABLE (3U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_A_HNP_SUPPORT (4U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_A_ALT_HNP_SUPPORT (5U) + +/* USB standard descriptor configure bmAttributes */ +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_MASK (0x80U) +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_SHIFT (7U) + +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_MASK (0x40U) +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_SHIFT (6U) + +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_MASK (0x20U) +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_SHIFT (5U) + +/* USB standard descriptor endpoint bmAttributes */ +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK (0x80U) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT (7U) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_OUT (0U) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_IN (0x80U) + +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_MASK (0x0FU) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_SHFIT (0U) + +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_TYPE_MASK (0x03U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_NUMBER_SHFIT (0U) + +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_MASK (0x0CU) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_SHFIT (2U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_NO_SYNC (0x00U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_ASYNC (0x04U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_ADAPTIVE (0x08U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_SYNC (0x0CU) + +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_MASK (0x30U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_SHFIT (4U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_DATA_ENDPOINT (0x00U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_FEEDBACK_ENDPOINT (0x10U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_IMPLICIT_FEEDBACK_DATA_ENDPOINT (0x20U) + +#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_SIZE_MASK (0x07FFu) +#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_MASK (0x1800u) +#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_SHFIT (11U) + +/* USB standard descriptor otg bmAttributes */ +#define USB_DESCRIPTOR_OTG_ATTRIBUTES_SRP_MASK (0x01u) +#define USB_DESCRIPTOR_OTG_ATTRIBUTES_HNP_MASK (0x02u) +#define USB_DESCRIPTOR_OTG_ATTRIBUTES_ADP_MASK (0x04u) + +/* USB standard descriptor device capability usb20 extension bmAttributes */ +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_LPM_MASK (0x02U) +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_LPM_SHIFT (1U) +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_BESL_MASK (0x04U) +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_BESL_SHIFT (2U) + +/* Language structure */ +typedef struct _usb_language +{ + uint8_t **string; /* The Strings descriptor array */ + uint32_t *length; /* The strings descriptor length array */ + uint16_t languageId; /* The language id of current language */ +} usb_language_t; + +typedef struct _usb_language_list +{ + uint8_t *languageString; /* The String 0U pointer */ + uint32_t stringLength; /* The String 0U Length */ + usb_language_t *languageList; /* The language list */ + uint8_t count; /* The language count */ +} usb_language_list_t; + +typedef struct _usb_descriptor_common +{ + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* DEVICE Descriptor Type */ + uint8_t bData[1]; /* Data */ +} usb_descriptor_common_t; + +typedef struct _usb_descriptor_device +{ + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* DEVICE Descriptor Type */ + uint8_t bcdUSB[2]; /* UUSB Specification Release Number in Binary-Coded Decimal, e.g. 0x0200U */ + uint8_t bDeviceClass; /* Class code */ + uint8_t bDeviceSubClass; /* Sub-Class code */ + uint8_t bDeviceProtocol; /* Protocol code */ + uint8_t bMaxPacketSize0; /* Maximum packet size for endpoint zero */ + uint8_t idVendor[2]; /* Vendor ID (assigned by the USB-IF) */ + uint8_t idProduct[2]; /* Product ID (assigned by the manufacturer) */ + uint8_t bcdDevice[2]; /* Device release number in binary-coded decimal */ + uint8_t iManufacturer; /* Index of string descriptor describing manufacturer */ + uint8_t iProduct; /* Index of string descriptor describing product */ + uint8_t iSerialNumber; /* Index of string descriptor describing the device serial number */ + uint8_t bNumConfigurations; /* Number of possible configurations */ +} usb_descriptor_device_t; + +typedef struct _usb_descriptor_configuration +{ + uint8_t bLength; /* Descriptor size in bytes = 9U */ + uint8_t bDescriptorType; /* CONFIGURATION type = 2U or 7U */ + uint8_t wTotalLength[2]; /* Length of concatenated descriptors */ + uint8_t bNumInterfaces; /* Number of interfaces, this configuration. */ + uint8_t bConfigurationValue; /* Value to set this configuration. */ + uint8_t iConfiguration; /* Index to configuration string */ + uint8_t bmAttributes; /* Configuration characteristics */ + uint8_t bMaxPower; /* Maximum power from bus, 2 mA units */ +} usb_descriptor_configuration_t; + +typedef struct _usb_descriptor_interface +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} usb_descriptor_interface_t; + +typedef struct _usb_descriptor_endpoint +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint8_t wMaxPacketSize[2]; + uint8_t bInterval; +} usb_descriptor_endpoint_t; + +typedef struct _usb_descriptor_endpoint_companion +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bMaxBurst; + uint8_t bmAttributes; + uint8_t wBytesPerInterval[2]; +} usb_descriptor_endpoint_companion_t; + +typedef struct _usb_descriptor_binary_device_object_store +{ + uint8_t bLength; /* Descriptor size in bytes = 5U */ + uint8_t bDescriptorType; /* BOS Descriptor type = 0FU*/ + uint8_t wTotalLength[2]; /*Length of this descriptor and all of its sub descriptors*/ + uint8_t bNumDeviceCaps; /*The number of separate device capability descriptors in the BOS*/ +} usb_descriptor_bos_t; + +typedef struct _usb_descriptor_usb20_extension +{ + uint8_t bLength; /* Descriptor size in bytes = 7U */ + uint8_t bDescriptorType; /* DEVICE CAPABILITY Descriptor type = 0x10U*/ + uint8_t bDevCapabilityType; /*Length of this descriptor and all of its sub descriptors*/ + uint8_t bmAttributes[4]; /*Bitmap encoding of supported device level features.*/ +} usb_descriptor_usb20_extension_t; +typedef struct _usb_descriptor_super_speed_device_capability +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint8_t bmAttributes; + uint8_t wSpeedsSupported[2]; + uint8_t bFunctionalitySupport; + uint8_t bU1DevExitLat; + uint8_t wU2DevExitLat[2]; +} usb_bos_device_capability_susperspeed_desc_t; +typedef union _usb_descriptor_union +{ + usb_descriptor_common_t common; /* Common descriptor */ + usb_descriptor_device_t device; /* Device descriptor */ + usb_descriptor_configuration_t configuration; /* Configuration descriptor */ + usb_descriptor_interface_t interface; /* Interface descriptor */ + usb_descriptor_endpoint_t endpoint; /* Endpoint descriptor */ + usb_descriptor_endpoint_companion_t endpointCompanion; /* Endpoint companion descriptor */ +} usb_descriptor_union_t; + +#endif /* __USB_SPEC_H__ */ diff --git a/source/hic_hal/nxp/lpc55xx/usbd_LPC55xx.c b/source/hic_hal/nxp/lpc55xx/usbd_LPC55xx.c new file mode 100644 index 000000000..84c2f99c1 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/usbd_LPC55xx.c @@ -0,0 +1,873 @@ +/** + * @file usbd_LPC55xx.c + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2020, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "rl_usb.h" +#include "device.h" +#include "compiler.h" +#include "util.h" +#include "fsl_usb.h" +#include "usb_phy.h" +#include "fsl_clock.h" +#include "fsl_iocon.h" +#include "hic_init.h" + +#define __NO_USB_LIB_C +#include "usb_config.c" + +#define BUF_ACTIVE (1UL << 31) +#define EP_DISABLED (1UL << 30) +#define EP_STALL (1UL << 29) +#define TOOGLE_RESET (1UL << 28) +#define EP_TYPE (1UL << 26) + +#define N_BYTES(n) ((n & 0x3FF) << 16) +#define BUF_ADDR(addr) (((addr) >> 6) & 0xFFFF) + +#define EP_OUT_IDX(EPNum) (EPNum * 2 ) +#define EP_IN_IDX(EPNum) (EPNum * 2 + 1) + +#define EP_LIST_BASE 0x40100000 +#define EP_BUF_BASE (uint32_t)(EP_LIST_BASE + 0x100) + +typedef struct BUF_INFO { + uint32_t buf_len; + uint32_t buf_ptr; +} EP_BUF_INFO; + +EP_BUF_INFO EPBufInfo[(USBD_EP_NUM + 1) * 2]; +#if defined ( __CC_ARM ) || defined (__ARMCC_VERSION) +volatile uint32_t EPList[(USBD_EP_NUM + 1) * 2] __attribute__((at(EP_LIST_BASE))); +#elif defined ( __GNUC__ ) +volatile uint32_t EPList[(USBD_EP_NUM + 1) * 2] __attribute__((section(".usbram"))); +#else +#error "Unsupported compiler!" +#endif + +static uint32_t addr = 3 * 64 + EP_BUF_BASE; +static uint32_t ctrl_out_next = 0; + +/* + * Get EP CmdStat pointer + * Parameters: EPNum: endpoint number + * + */ + +uint32_t *GetEpCmdStatPtr(uint32_t EPNum) +{ + uint32_t ptr = 0; + + if (EPNum & 0x80) { + EPNum &= ~0x80; + ptr = 8; + } + + ptr += EP_LIST_BASE + EPNum * 16; + return ((uint32_t *)ptr); +} + + +/* + * Usb interrupt enable/disable + * Parameters: ena: enable/disable + * 0: disable interrupt + * 1: enable interrupt + */ + +#ifdef __RTX +void __svc(1) USBD_Intr(int ena); +void __SVC_1(int ena) +{ + if (ena) { + NVIC_EnableIRQ(USB1_IRQn); /* Enable USB interrupt */ + } else { + NVIC_DisableIRQ(USB1_IRQn); /* Disable USB interrupt */ + } +} +#endif + + + +/* + * USB Device Initialize Function + * Called by the User to initialize USB Device + * Return Value: None + */ + +void USBD_Init(void) +{ + // Enable VBUS pin. + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t port0_pin22_config = (/* Pin is configured as USB0_VBUS */ + IOCON_PIO_FUNC7 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN22 (coords: 78) is configured as USB0_VBUS */ + IOCON_PinMuxSet(IOCON, 0U, 22U, port0_pin22_config); + + // Switch IP to device mode. First enable the USB1 host clock. + CLOCK_EnableClock(kCLOCK_Usbh1); + // Put PHY powerdown under software control + USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; + // According to reference mannual, device mode setting has to be set by access usb host register + USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; + // Disable usb1 host clock + CLOCK_DisableClock(kCLOCK_Usbh1); + + // Enable clocks. + CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_UsbPhySrcExt, BOARD_XTAL0_CLK_HZ); + CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUnused, 0U); + + // Init PHY. + USB_EhciPhyInit(kUSB_ControllerLpcIp3511Hs0, BOARD_XTAL0_CLK_HZ, NULL); + +// SYSCON->SYSAHBCLKCTRL |= (1UL << 6); +// SYSCON->SYSAHBCLKCTRL |= (1UL << 14) | +// (1UL << 27); + USBHSD->DEVCMDSTAT |= USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK; +// IOCON->PIO0_3 &= ~(0x1F); +// IOCON->PIO0_3 |= (1UL << 0); /* Secondary function VBUS */ +// IOCON->PIO0_6 &= ~7; +// IOCON->PIO0_6 |= (1UL << 0); /* Secondary function USB CON */ +// SYSCON->PDRUNCFG &= ~((1UL << 8) | /* USB PLL powered */ +// (1UL << 10)); /* USB transceiver powered */ + USBHSD->DATABUFSTART = EP_BUF_BASE & 0xFFC00000; + USBHSD->EPLISTSTART = EP_LIST_BASE; + + NVIC_EnableIRQ(USB1_IRQn); + USBD_Reset(); +} + + +/* + * USB Device Connect Function + * Called by the User to Connect/Disconnect USB Device + * Parameters: con: Connect/Disconnect + * Return Value: None + */ + +void USBD_Connect(BOOL con) +{ + if (con) { + USBHSD->DEVCMDSTAT |= USBHSD_DEVCMDSTAT_DCON_MASK; /* Set device connect status */ + } else { + USBHSD->DEVCMDSTAT &= ~USBHSD_DEVCMDSTAT_DCON_MASK; /* Clear device connect status */ + } + + return; +} + + +// Disable optimization of this function. It gets a "iteration 8 invokes undefined behavior +// [-Waggressive-loop-optimizations]" warning in gcc if optimisation is enabled, for the first +// loop where EPList[i] is written to disable EPs. +NO_OPTIMIZE_PRE +/* + * USB Device Reset Function + * Called automatically on USB Device Reset + * Return Value: None + */ +void NO_OPTIMIZE_INLINE USBD_Reset(void) +{ + uint32_t i; + uint32_t *ptr; + addr = 3 * 64 + EP_BUF_BASE; + + for (i = 2; i < (5 * 4); i++) { + EPList[i] = (1UL << 30); /* EPs disabled */ + } + + ctrl_out_next = 0; + EPBufInfo[0].buf_len = USBD_MAX_PACKET0; + EPBufInfo[0].buf_ptr = EP_BUF_BASE; + EPBufInfo[1].buf_len = USBD_MAX_PACKET0; + EPBufInfo[1].buf_ptr = EP_BUF_BASE + 2 * 64; + ptr = GetEpCmdStatPtr(0); + *ptr = N_BYTES(EPBufInfo[0].buf_len) | /* EP0 OUT */ + BUF_ADDR(EPBufInfo[0].buf_ptr) | + BUF_ACTIVE; + ptr++; + *ptr = BUF_ADDR(EPBufInfo[0].buf_ptr + 64);/* SETUP */ + USBHSD->DEVCMDSTAT |= USBHSD_DEVCMDSTAT_DEV_EN_MASK; /*USB device enable */ + USBHSD->INTSTAT = 0x2FC; /* clear EP interrupt flags */ + USBHSD->INTEN = (USBHSD_INTEN_FRAME_INT_EN_MASK | /* SOF intr enable */ + USBHSD_INTEN_EP_INT_EN(0) | /* EP0 OUT intr enable */ + USBHSD_INTEN_EP_INT_EN(1) | /* EP0 IN intr enable */ + USBHSD_INTEN_DEV_INT_EN_MASK); /* stat change int en */ +} +NO_OPTIMIZE_POST + +/* + * USB Device Suspend Function + * Called automatically on USB Device Suspend + * Return Value: None + */ + +void USBD_Suspend(void) +{ + /* Performed by Hardware */ +} + + +/* + * USB Device Resume Function + * Called automatically on USB Device Resume + * Return Value: None + */ + +void USBD_Resume(void) +{ + /* Performed by Hardware */ +} + + +/* + * USB Device Remote Wakeup Function + * Called automatically on USB Device Remote Wakeup + * Return Value: None + */ + +void USBD_WakeUp(void) +{ + SYSCON->USB1NEEDCLKCTRL = SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK; + USBHSD->DEVCMDSTAT &= ~USBHSD_DEVCMDSTAT_DSUS_MASK; /*clear device suspend status */ + + while (USBHSD->DEVCMDSTAT & USBHSD_DEVCMDSTAT_DSUS_MASK); + + SYSCON->USB1NEEDCLKCTRL = 0; +} + + +/* + * USB Device Remote Wakeup Configuration Function + * Parameters: cfg: Device Enable/Disable + * Return Value: None + */ + +void USBD_WakeUpCfg(BOOL cfg) +{ + if (cfg == __TRUE) { + USBHSD->DEVCMDSTAT &= ~USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK; /*PPL_ON=0, in suspend clk is stoped */ + } else { + USBHSD->DEVCMDSTAT |= USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK; /*PPL_ON=1, in suspend clk isnt stoped */ + SYSCON->USB1NEEDCLKCTRL = 0; + } +} + + +/* + * USB Device Set Address Function + * Parameters: adr: USB Device Address + * Return Value: None + */ + +void USBD_SetAddress(uint32_t adr, uint32_t setup) +{ + if (!setup) { + USBHSD->DEVCMDSTAT &= ~USBHSD_DEVCMDSTAT_DEV_ADDR_MASK; + USBHSD->DEVCMDSTAT |= adr | USBHSD_DEVCMDSTAT_DEV_EN_MASK; + } +} + + + +/* + * USB Device Configure Function + * Parameters: cfg: Device Configure/Deconfigure + * Return Value: None + */ + +void USBD_Configure(BOOL cfg) +{ + addr = 3 * 64 + EP_BUF_BASE; +} + + +/* + * Configure USB Device Endpoint according to Descriptor + * Parameters: pEPD: Pointer to Device Endpoint Descriptor + * Return Value: None + */ + +void USBD_ConfigEP(USB_ENDPOINT_DESCRIPTOR *pEPD) +{ + uint32_t num, val, type; + uint32_t *ptr; + num = pEPD->bEndpointAddress; + val = pEPD->wMaxPacketSize; + type = pEPD->bmAttributes & USB_ENDPOINT_TYPE_MASK; + + /* IN EPs */ + if (num & 0x80) { + num &= ~0x80; + EPBufInfo[EP_IN_IDX(num)].buf_len = val; + EPBufInfo[EP_IN_IDX(num)].buf_ptr = addr; + addr += ((val + 63) >> 6) * 64; /* calc new free buffer address */ + ptr = GetEpCmdStatPtr(num | 0x80); + *ptr = EP_DISABLED; + + if (type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + *ptr |= EP_TYPE; + } + } + + /* OUT EPs */ + else { + EPBufInfo[EP_OUT_IDX(num)].buf_len = val; + EPBufInfo[EP_OUT_IDX(num)].buf_ptr = addr; + ptr = GetEpCmdStatPtr(num); + *ptr = N_BYTES(EPBufInfo[EP_OUT_IDX(num)].buf_len) | + BUF_ADDR(EPBufInfo[EP_OUT_IDX(num)].buf_ptr) | + EP_DISABLED; + + if (type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + *ptr |= EP_TYPE; + } + + addr += ((val + 63) >> 6) * 64; /* calc new free buffer address */ + } +} + + +/* + * Set Direction for USB Device Control Endpoint + * Parameters: dir: Out (dir == 0), In (dir <> 0) + * Return Value: None + */ + +void USBD_DirCtrlEP(uint32_t dir) +{ + /* Not needed */ +} + + +/* + * Enable USB Device Endpoint + * Parameters: EPNum: Device Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USBD_EnableEP(uint32_t EPNum) +{ + uint32_t *ptr;; + ptr = GetEpCmdStatPtr(EPNum); + + /* IN EP */ + if (EPNum & 0x80) { + EPNum &= ~0x80; + *ptr &= ~EP_DISABLED; + USBHSD->INTSTAT = (1 << EP_IN_IDX(EPNum)); + USBHSD->INTEN |= (1 << EP_IN_IDX(EPNum)); + } + + /* OUT EP */ + else { + *ptr &= ~EP_DISABLED; + *ptr |= BUF_ACTIVE; + USBHSD->INTSTAT = (1 << EP_OUT_IDX(EPNum)); + USBHSD->INTEN |= (1 << EP_OUT_IDX(EPNum)); + } +} + + +/* + * Disable USB Device Endpoint + * Parameters: EPNum: Device Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USBD_DisableEP(uint32_t EPNum) +{ + uint32_t *ptr; + ptr = GetEpCmdStatPtr(EPNum); + *ptr = EP_DISABLED; + + if (EPNum & 0x80) { + EPNum &= ~0x80; + USBHSD->INTEN &= ~(1 << EP_IN_IDX(EPNum)); + + } else { + USBHSD->INTEN &= ~(1 << EP_OUT_IDX(EPNum)); + } +} + + +/* + * Reset USB Device Endpoint + * Parameters: EPNum: Device Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USBD_ResetEP(uint32_t EPNum) +{ + uint32_t *ptr; + ptr = GetEpCmdStatPtr(EPNum); + *ptr |= TOOGLE_RESET; +} + + +/* + * Set Stall for USB Device Endpoint + * Parameters: EPNum: Device Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USBD_SetStallEP(uint32_t EPNum) +{ + uint32_t *ptr; + ptr = GetEpCmdStatPtr(EPNum); + + if (EPNum & 0x7F) { + if (*ptr & BUF_ACTIVE) { + *ptr &= ~(BUF_ACTIVE); + } + + } else { + if (EPNum & 0x80) { + EPNum &= ~0x80; + USBHSD->EPSKIP |= (1 << EP_IN_IDX(EPNum)); + + while (USBHSD->EPSKIP & (1 << EP_IN_IDX(EPNum))); + + } else { + USBHSD->EPSKIP |= (1 << EP_OUT_IDX(EPNum)); + + while (USBHSD->EPSKIP & (1 << EP_OUT_IDX(EPNum))); + } + } + + if ((EPNum & 0x7F) == 0) { + /* Endpoint is stalled so control out won't be next */ + ctrl_out_next = 0; + } + + *ptr |= EP_STALL; +} + + +/* + * Clear Stall for USB Device Endpoint + * Parameters: EPNum: Device Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USBD_ClrStallEP(uint32_t EPNum) +{ + uint32_t *ptr; + ptr = GetEpCmdStatPtr(EPNum); + + if (EPNum & 0x80) { + *ptr &= ~EP_STALL; + + } else { + *ptr &= ~EP_STALL; + *ptr |= BUF_ACTIVE; + } + + USBD_ResetEP(EPNum); +} + + +/* + * Clear USB Device Endpoint Buffer + * Parameters: EPNum: Device Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USBD_ClearEPBuf(uint32_t EPNum) +{ + uint32_t cnt, i; + U8 *dataptr; + + if (EPNum & 0x80) { + EPNum &= ~0x80; + dataptr = (U8 *)EPBufInfo[EP_IN_IDX(EPNum)].buf_ptr; + cnt = EPBufInfo[EP_IN_IDX(EPNum)].buf_len; + + for (i = 0; i < cnt; i++) { + dataptr[i] = 0; + } + + } else { + dataptr = (U8 *)EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr; + cnt = EPBufInfo[EP_OUT_IDX(EPNum)].buf_len; + + for (i = 0; i < cnt; i++) { + dataptr[i] = 0; + } + } +} + + +/* + * Read USB Device Endpoint Data + * Parameters: EPNum: Device Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * pData: Pointer to Data Buffer + * Return Value: Number of bytes read + */ + +uint32_t USBD_ReadEP(uint32_t EPNum, U8 *pData, uint32_t size) +{ + uint32_t cnt, i, xfer_size; + volatile uint32_t *ptr; + U8 *dataptr; + ptr = GetEpCmdStatPtr(EPNum); + int timeout = 256; + + /* Setup packet */ + if ((EPNum == 0) && !ctrl_out_next && (USBHSD->DEVCMDSTAT & USBHSD_DEVCMDSTAT_SETUP_MASK)) { + cnt = USBD_MAX_PACKET0; + + if (size < cnt) { + util_assert(0); + cnt = size; + } + + dataptr = (U8 *)(EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr + 64); + + for (i = 0; i < cnt; i++) { + pData[i] = dataptr[i]; + } + + xfer_size = (pData[7] << 8) | (pData[6] << 0); + if ((xfer_size > 0) && (pData[0] & (1 << 7))) { + /* This control transfer has a data IN stage */ + /* and ends with a zero length data OUT transfer. */ + /* Ensure the data OUT token is not skipped even if */ + /* a SETUP token arrives before USBD_ReadEP has */ + /* been called. */ + ctrl_out_next = 1; + } + + USBHSD->EPSKIP |= (1 << EP_IN_IDX(EPNum)); + + while (USBHSD->EPSKIP & (1 << EP_IN_IDX(EPNum))); + + if (*(ptr + 2) & EP_STALL) { + *(ptr + 2) &= ~(EP_STALL); + } + + if (*ptr & EP_STALL) { + *ptr &= ~(EP_STALL); + } + + USBHSD->DEVCMDSTAT |= USBHSD_DEVCMDSTAT_SETUP_MASK; + } + + /* OUT packet */ + else { + ptr = GetEpCmdStatPtr(EPNum); + cnt = EPBufInfo[EP_OUT_IDX(EPNum)].buf_len - ((*ptr >> 16) & 0x3FF); + dataptr = (U8 *)EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr; + + while ((timeout-- > 0) && (*ptr & BUF_ACTIVE)); //spin on the hardware until it's done + util_assert(!(*ptr & BUF_ACTIVE)); //check for timeout + + if (size < cnt) { + util_assert(0); + cnt = size; + } + + cnt = cnt < size ? cnt : size; + + for (i = 0; i < cnt; i++) { + pData[i] = dataptr[i]; + } + + *ptr = N_BYTES(EPBufInfo[EP_OUT_IDX(EPNum)].buf_len) | + BUF_ADDR(EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr) | + BUF_ACTIVE; + + if (EPNum == 0) { + /* If ctrl_out_next is set then this should be a zero length */ + /* data OUT packet. */ + util_assert(!ctrl_out_next || (cnt == 0)); + ctrl_out_next = 0; + if (USBHSD->DEVCMDSTAT & USBHSD_DEVCMDSTAT_SETUP_MASK) { + // A setup packet is still pending so trigger another interrupt + USBHSD->INTSETSTAT |= USBHSD_INTSETSTAT_EP_SET_INT(0); + } + } + } + + return (cnt); +} + + +/* + * Write USB Device Endpoint Data + * Parameters: EPNum: Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * pData: Pointer to Data Buffer + * cnt: Number of bytes to write + * Return Value: Number of bytes written + */ + +uint32_t USBD_WriteEP(uint32_t EPNum, U8 *pData, uint32_t cnt) +{ + uint32_t i; + volatile uint32_t *ptr; + uint32_t *dataptr; + ptr = GetEpCmdStatPtr(EPNum); + EPNum &= ~0x80; + + while (*ptr & BUF_ACTIVE); + + *ptr &= ~(0x3FFFFFF); + *ptr |= BUF_ADDR(EPBufInfo[EP_IN_IDX(EPNum)].buf_ptr) | + N_BYTES(cnt); + dataptr = (uint32_t *)EPBufInfo[EP_IN_IDX(EPNum)].buf_ptr; + + for (i = 0; i < (cnt + 3) / 4; i++) { + dataptr[i] = __UNALIGNED_UINT32_READ(pData); + pData += 4; + } + + if (EPNum && (*ptr & EP_STALL)) { + return (0); + } + + *ptr |= BUF_ACTIVE; + return (cnt); +} + + +/* + * Get USB Device Last Frame Number + * Parameters: None + * Return Value: Frame Number + */ + +uint32_t USBD_GetFrame(void) +{ + return (USBHSD->INFO & USBHSD_INFO_FRAME_NR_MASK); +} + + +/* + * USB Device Interrupt Service Routine + */ + +void USB1_IRQHandler(void) +{ + NVIC_DisableIRQ(USB1_IRQn); + USBD_SignalHandler(); +} + +void USBD_Handler(void) +{ + uint32_t sts, val, num, i; + sts = USBHSD->INTSTAT; + USBHSD->INTSTAT = sts; + + /* Device Status Interrupt (Reset, Connect change, Suspend/Resume) */ + if (sts & USBHSD_INTSTAT_DEV_INT_MASK) { + val = USBHSD->DEVCMDSTAT; + + /* reset interrupt */ + if (val & USBHSD_DEVCMDSTAT_DRES_C_MASK) { + USBHSD->DEVCMDSTAT |= USBHSD_DEVCMDSTAT_DRES_C_MASK; + USBD_Reset(); + usbd_reset_core(); +#ifdef __RTX + + if (USBD_RTX_DevTask) { + isr_evt_set(USBD_EVT_RESET, USBD_RTX_DevTask); + } + +#else + + if (USBD_P_Reset_Event) { + USBD_P_Reset_Event(); + } + +#endif + } + + /* connect interrupt */ + if (val & USBHSD_DEVCMDSTAT_DCON_C_MASK) { + USBHSD->DEVCMDSTAT |= USBHSD_DEVCMDSTAT_DCON_C_MASK; +#ifdef __RTX + + if (USBD_RTX_DevTask) { + if (val & USBHSD_DEVCMDSTAT_DCON_MASK) { + isr_evt_set(USBD_EVT_POWER_ON, USBD_RTX_DevTask); + } else { + isr_evt_set(USBD_EVT_POWER_OFF, USBD_RTX_DevTask); + } + } + +#else + + if (USBD_P_Power_Event) { + USBD_P_Power_Event((val & USBHSD_DEVCMDSTAT_DCON_MASK) >> USBHSD_DEVCMDSTAT_DCON_SHIFT); + } + +#endif + } + + /* suspend/resume interrupt */ + if (val & USBHSD_DEVCMDSTAT_DSUS_C_MASK) { + USBHSD->DEVCMDSTAT |= USBHSD_DEVCMDSTAT_DSUS_C_MASK; + + /* suspend interrupt */ + if (val & USBHSD_DEVCMDSTAT_DSUS_MASK) { + USBD_Suspend(); +#ifdef __RTX + + if (USBD_RTX_DevTask) { + isr_evt_set(USBD_EVT_SUSPEND, USBD_RTX_DevTask); + } + +#else + + if (USBD_P_Suspend_Event) { + USBD_P_Suspend_Event(); + } + +#endif + } + + /* resume interrupt */ + else { +#ifdef __RTX + + if (USBD_RTX_DevTask) { + isr_evt_set(USBD_EVT_RESUME, USBD_RTX_DevTask); + } + +#else + + if (USBD_P_Resume_Event) { + USBD_P_Resume_Event(); + } + +#endif + } + } + } + + /* Start of Frame */ + if (sts & USBHSD_INTSTAT_FRAME_INT_MASK) { +#ifdef __RTX + + if (USBD_RTX_DevTask) { + isr_evt_set(USBD_EVT_SOF, USBD_RTX_DevTask); + } + +#else + + if (USBD_P_SOF_Event) { + USBD_P_SOF_Event(); + } + +#endif + } + + /* EndPoint Interrupt */ + if (sts & 0x3FF) { + const uint32_t endpoint_count = ((USBD_EP_NUM + 1) * 2); + + for (i = 0; i < endpoint_count; i++) { + // Iterate through endpoints in the reverse order so IN endpoints + // get processed before OUT endpoints if they are both pending. + num = endpoint_count - i - 1; + + if (sts & (1UL << num)) { + /* Setup */ + if ((num == 0) && !ctrl_out_next && (USBHSD->DEVCMDSTAT & USBHSD_DEVCMDSTAT_SETUP_MASK)) { +#ifdef __RTX + + if (USBD_RTX_EPTask[num / 2]) { + isr_evt_set(USBD_EVT_SETUP, USBD_RTX_EPTask[num / 2]); + } + +#else + + if (USBD_P_EP[num / 2]) { + USBD_P_EP[num / 2](USBD_EVT_SETUP); + } + +#endif + } + + /* OUT */ + else if ((num % 2) == 0) { +#ifdef __RTX + + if (USBD_RTX_EPTask[num / 2]) { + isr_evt_set(USBD_EVT_OUT, USBD_RTX_EPTask[num / 2]); + } + +#else + + if (USBD_P_EP[num / 2]) { + USBD_P_EP[num / 2](USBD_EVT_OUT); + } + +#endif + } + + /* IN */ + else { +#ifdef __RTX + + if (USBD_RTX_EPTask[num / 2]) { + isr_evt_set(USBD_EVT_IN, USBD_RTX_EPTask[num / 2]); + } + +#else + + if (USBD_P_EP[num / 2]) { + USBD_P_EP[num / 2](USBD_EVT_IN); + } + +#endif + } + } + } + } + + NVIC_EnableIRQ(USB1_IRQn); +} From 81dabcbc18903c55860c10090bbb5d854e8a50b2 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Tue, 15 Dec 2020 15:42:52 -0600 Subject: [PATCH 121/617] LPC55xx: cleaned up fsl_iocon.h. --- .../nxp/lpc55xx/LPC55S69/drivers/fsl_iocon.h | 95 +++---------------- 1 file changed, 12 insertions(+), 83 deletions(-) diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iocon.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iocon.h index 221080fd6..bee4526fe 100644 --- a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iocon.h +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_iocon.h @@ -38,17 +38,20 @@ */ typedef struct _iocon_group { - uint32_t port : 8; /* Pin port */ - uint32_t pin : 8; /* Pin number */ - uint32_t ionumber : 8; /* IO number */ - uint32_t modefunc : 16; /* Function and mode */ +#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) + uint8_t ionumber; /* IO number */ + uint8_t _; +#else /* FSL_FEATURE_IOCON_ONE_DIMENSION */ + uint8_t port; /* Pin port */ + uint8_t pin; /* Pin number */ +#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */ + uint16_t modefunc; /* Function and mode */ } iocon_group_t; /** * @brief IOCON function and mode selection definitions * @note See the User Manual for specific modes and functions supported by the various pins. */ -#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) #define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ #define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ #define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ @@ -57,6 +60,7 @@ typedef struct _iocon_group #define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ #define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ #define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ +#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) #define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ #define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ #define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ @@ -65,6 +69,8 @@ typedef struct _iocon_group #define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ #define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ #define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ +#endif /* FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH */ + #if defined(IOCON_PIO_MODE_SHIFT) #define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ #define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ @@ -79,7 +85,7 @@ typedef struct _iocon_group #if defined(IOCON_PIO_EGP_SHIFT) #define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ +#define IOCON_I2C_MODE (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ #endif #if defined(IOCON_PIO_SLEW_SHIFT) @@ -150,83 +156,6 @@ typedef struct _iocon_group << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ #endif -#else -#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ -#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ -#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ -#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ -#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ -#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ -#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ -#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ - -#if defined(IOCON_PIO_MODE_SHIFT) -#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ -#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ -#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ -#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ -#endif - -#if defined(IOCON_PIO_I2CSLEW_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ -#endif - -#if defined(IOCON_PIO_EGP_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ -#endif - -#if defined(IOCON_PIO_INVERT_SHIFT) -#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */ -#endif - -#if defined(IOCON_PIO_DIGIMODE_SHIFT) -#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */ -#define IOCON_DIGITAL_EN \ - (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */ -#endif - -#if defined(IOCON_PIO_FILTEROFF_SHIFT) -#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ -#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ -#endif - -#if defined(IOCON_PIO_I2CDRIVE_SHIFT) -#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ -#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ -#endif - -#if defined(IOCON_PIO_OD_SHIFT) -#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */ -#endif - -#if defined(IOCON_PIO_I2CFILTER_SHIFT) -#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ -#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled */ -#endif - -#if defined(IOCON_PIO_S_MODE_SHIFT) -#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ -#define IOCON_S_MODE_1CLK \ - (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_2CLK \ - (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_3CLK \ - (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ -#endif - -#if defined(IOCON_PIO_CLK_DIV_SHIFT) -#define IOCON_CLKDIV(div) \ - ((div) \ - << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ -#endif - -#endif #if defined(__cplusplus) extern "C" { #endif From ecc0fb321e7cbebb72789c84054f510a8109c8b0 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Thu, 10 Dec 2020 18:21:01 -0600 Subject: [PATCH 122/617] LPC55xx: added DAPLink info to gcc vector table. --- .../hic_hal/nxp/lpc55xx/gcc/startup_LPC55S69_cm33_core0.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/source/hic_hal/nxp/lpc55xx/gcc/startup_LPC55S69_cm33_core0.S b/source/hic_hal/nxp/lpc55xx/gcc/startup_LPC55S69_cm33_core0.S index e5bea755b..15833b178 100644 --- a/source/hic_hal/nxp/lpc55xx/gcc/startup_LPC55S69_cm33_core0.S +++ b/source/hic_hal/nxp/lpc55xx/gcc/startup_LPC55S69_cm33_core0.S @@ -32,12 +32,12 @@ __isr_vector: .long BusFault_Handler /* Bus Fault Handler*/ .long UsageFault_Handler /* Usage Fault Handler*/ .long SecureFault_Handler /* Secure Fault Handler*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ - .long 0 /* Reserved*/ + .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ + .long DAPLINK_HIC_ID /* Compatibility*/ + .long DAPLINK_VERSION /* Version*/ .long SVC_Handler /* SVCall Handler*/ .long DebugMon_Handler /* Debug Monitor Handler*/ - .long 0 /* Reserved*/ + .long g_board_info /* Ptr to Board info, family info other target details*/ .long PendSV_Handler /* PendSV Handler*/ .long SysTick_Handler /* SysTick Handler*/ From 6b46efce1ac78fafa0c75b3c3e0d2787cea8869b Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sun, 6 Dec 2020 18:15:02 -0600 Subject: [PATCH 123/617] LPC55xx: daplink_addr.h memory map. --- source/hic_hal/nxp/lpc55xx/daplink_addr.h | 43 +++++++++++++++-------- 1 file changed, 28 insertions(+), 15 deletions(-) diff --git a/source/hic_hal/nxp/lpc55xx/daplink_addr.h b/source/hic_hal/nxp/lpc55xx/daplink_addr.h index 7973e5b2c..8b17669da 100644 --- a/source/hic_hal/nxp/lpc55xx/daplink_addr.h +++ b/source/hic_hal/nxp/lpc55xx/daplink_addr.h @@ -1,9 +1,6 @@ /** - * @file daplink_addr.h - * @brief - * * DAPLink Interface Firmware - * Copyright (c) 2019, ARM Limited, All Rights Reserved + * Copyright (c) 2020, Arm Limited * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -22,13 +19,25 @@ #ifndef DAPLINK_ADDR_H #define DAPLINK_ADDR_H +// Flash layout: +// +// [ 0x0000_0000 - 0x0000_FFFF ]: 64 kB - bootloader +// [ 0x0001_0000 - 0x0004_FFFF ]: 256 kB - interface +// [ 0x0005_0000 - 0x0005_0FFF ]: 4 kB - persistent config (cfgrom) +// +// Notes: +// 1. The interface does not extend to the end of flash because that makes the binary +// firmware image large and slow to program. +// 2. Attempting to program flash starting at 0x96000 fails for some reason, even though +// the UM states that 630 kB is available for the user (0x9d800). + /* Device sizes */ -#define DAPLINK_ROM_START 0x00000000 -#define DAPLINK_ROM_SIZE 0x00040000 // Intentionally set to only 256 kB of total 640 kB. +#define DAPLINK_ROM_START 0x00000000 // NS alias +#define DAPLINK_ROM_SIZE 0x00051000 // 64 kB BL + 256 kB IF + 4 kB config -#define DAPLINK_RAM_START 0x20000000 -#define DAPLINK_RAM_SIZE 0x00044000 // 272 kB RAM +#define DAPLINK_RAM_START 0x20000000 // NS alias +#define DAPLINK_RAM_SIZE 0x00040000 // SRAM 0-3 /* ROM sizes */ @@ -39,23 +48,27 @@ #define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00000000 #define DAPLINK_ROM_IF_START 0x00010000 -#define DAPLINK_ROM_IF_SIZE 0x0002f000 // 192 kB interface +#define DAPLINK_ROM_IF_SIZE 0x00040000 -#define DAPLINK_ROM_CONFIG_USER_START 0x0003f000 -#define DAPLINK_ROM_CONFIG_USER_SIZE 0x00001000 // 4 kB user config +#define DAPLINK_ROM_CONFIG_USER_START 0x00050000 +#define DAPLINK_ROM_CONFIG_USER_SIZE 0x00001000 /* RAM sizes */ #define DAPLINK_RAM_APP_START 0x20000000 -#define DAPLINK_RAM_APP_SIZE 0x00043f00 +#define DAPLINK_RAM_APP_SIZE 0x0003FF00 -#define DAPLINK_RAM_SHARED_START 0x20043f00 +#define DAPLINK_RAM_SHARED_START 0x2003FF00 #define DAPLINK_RAM_SHARED_SIZE 0x00000100 /* Flash Programming Info */ -#define DAPLINK_SECTOR_SIZE 0x00008000 -#define DAPLINK_MIN_WRITE_SIZE 0x00000010 +#define DAPLINK_SECTOR_SIZE 0x00000200 +#define DAPLINK_MIN_WRITE_SIZE 0x00000200 + +/* USB RAM */ +#define DAPLINK_USB_RAM_START 0x40100000 +#define DAPLINK_USB_RAM_SIZE 0x00004000 /* Current build */ From 226ecc0061d146e2d498d2bb5d3d867a11320548 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sun, 6 Dec 2020 18:15:28 -0600 Subject: [PATCH 124/617] LPC55xx: IO_Config.h pin map. --- source/hic_hal/nxp/lpc55xx/IO_Config.h | 216 ++++++------------------- 1 file changed, 49 insertions(+), 167 deletions(-) diff --git a/source/hic_hal/nxp/lpc55xx/IO_Config.h b/source/hic_hal/nxp/lpc55xx/IO_Config.h index b3d1965b2..112cb901b 100644 --- a/source/hic_hal/nxp/lpc55xx/IO_Config.h +++ b/source/hic_hal/nxp/lpc55xx/IO_Config.h @@ -3,7 +3,7 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2020 Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -22,186 +22,68 @@ #ifndef __IO_CONFIG_H__ #define __IO_CONFIG_H__ -#include "fsl_device_registers.h" +#include "device.h" #include "compiler.h" #include "daplink.h" -// This GPIO configuration is only valid for the K26F HIC -COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_K26F); +// This GPIO configuration is only valid for the LPC55xx HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC55XX); +// All pins are PIO0. +#define PIN_PIO_PORT (0) // Debug Port I/O Pins -// SWCLK Pin PTC5 -// (SDA_SWD_SCK on schematic) -#define PIN_SWCLK_PORT PORTC -#define PIN_SWCLK_GPIO PTC -#define PIN_SWCLK_BIT 5 - -// SWDIO Out Pin PTC6 -// (SDA_SWD_DOUT on schematic) -#define PIN_SWDIO_OUT_PORT PORTC -#define PIN_SWDIO_OUT_GPIO PTC -#define PIN_SWDIO_OUT_BIT 6 - -// SWDIO In Pin PTC7 -// (SDA_SWD_DIN on schematic) -#define PIN_SWDIO_IN_PORT PORTC -#define PIN_SWDIO_IN_GPIO PTC -#define PIN_SWDIO_IN_BIT 7 - -// SWDIO Output Enable Pin PTA5 -// (SDA_SWD_OE on schematic) -#define PIN_SWDIO_OE_PORT PORTA -#define PIN_SWDIO_OE_GPIO PTA -#define PIN_SWDIO_OE_BIT 5 - -// SWD Enable Pin PTA4 -// (SDA_SWD_EN on schematic) -#define PIN_SWD_OE_PORT PORTA -#define PIN_SWD_OE_GPIO PTA -#define PIN_SWD_OE_BIT 9 - -// SWO Input Pin PTC3 -// (SDA_SWD_SWO on schematic) -#define PIN_SWO_RX_PORT PORTC -#define PIN_SWO_RX_GPIO PTC -#define PIN_SWO_RX_BIT 3 - -// nRESET Pin PTA7 -#define PIN_nRESET_PORT PORTA -#define PIN_nRESET_GPIO PTA -#define PIN_nRESET_BIT 7 -#define PIN_nRESET (1 << PIN_nRESET_BIT) - -// nRESET Pin Level Shifter Enable PTA6 -// (SDA_LVLRST_EN on schematic) -#define PIN_nRESET_EN_PORT PORTA -#define PIN_nRESET_EN_GPIO PTA -#define PIN_nRESET_EN_BIT 6 -#define PIN_nRESET_EN (1 << PIN_nRESET_EN_BIT) - -// SWD Detect Pin PTA8 -// (x_SWD_DETECT on schematic) -#define PIN_SWD_DETECT_PORT PORTA -#define PIN_SWD_DETECTGPIO PTA -#define PIN_SWD_DETECT_BIT 8 -#define PIN_SWD_DETECT (1 << PIN_SWD_DETECT_BIT) +// SWCLK Pin PIO_0 (O) +// (DBGIF_TCK_SWCLK) +#define PIN_SWCLK_BIT (0) +// SWDIO I/O Pin PIO0_2 (IO) +// (DBGIF_TMS_SWDIO) +#define PIN_SWDIO_OUT_BIT (2) -// Power monitor - -// SDA_G1 Pin PTE17 -#define PIN_G1_PORT PORTE -#define PIN_G1_GPIO PTE -#define PIN_G1_BIT 17 -#define PIN_G1 (1 << PIN_G1_BIT) - -// SDA_G2 Pin PTE18 -#define PIN_G2_PORT PORTE -#define PIN_G2_GPIO PTE -#define PIN_G2_BIT 18 -#define PIN_G2 (1 << PIN_G2_BIT) - -// SDA_LOW_RANGE_EN Pin PTE19 -#define PIN_LOW_RANGE_EN_PORT PORTE -#define PIN_LOW_RANGE_EN_GPIO PTE -#define PIN_LOW_RANGE_EN_BIT 19 -#define PIN_LOW_RANGE_EN (1 << PIN_LOW_RANGE_EN_BIT) - -// SDA_CAL_EN Pin PTE24 -#define PIN_CAL_EN_PORT PORTE -#define PIN_CAL_EN_GPIO PTE -#define PIN_CAL_EN_BIT 24 -#define PIN_CAL_EN (1 << PIN_CAL_EN_BIT) - -// SDA_CTRL0 Pin PTE25 -#define PIN_CTRL0_PORT PORTE -#define PIN_CTRL0_GPIO PTE -#define PIN_CTRL0_BIT 25 -#define PIN_CTRL0 (1 << PIN_CTRL0_BIT) - -// SDA_CTRL1 Pin PTE26 -#define PIN_CTRL1_PORT PORTE -#define PIN_CTRL1_GPIO PTE -#define PIN_CTRL1_BIT 26 -#define PIN_CTRL1 (1 << PIN_CTRL1_BIT) - -// SDA_CTRL2 Pin PTE27 -#define PIN_CTRL2_PORT PORTE -#define PIN_CTRL2_GPIO PTE -#define PIN_CTRL2_BIT 27 -#define PIN_CTRL2 (1 << PIN_CTRL2_BIT) - -// SDA_CTRL3 Pin PTE28 -#define PIN_CTRL3_PORT PORTE -#define PIN_CTRL3_GPIO PTE -#define PIN_CTRL3_BIT 28 -#define PIN_CTRL3 (1 << PIN_CTRL3_BIT) - - -// Misc target connections - -// SDA_GPIO0_B Pin PTB22 -#define PIN_GPIO0_B_PORT PORTB -#define PIN_GPIO0_B_GPIO PTB -#define PIN_GPIO0_B_BIT 22 -#define PIN_GPIO0_B (1 < PIN_GPIO0_B_BIT) - -// SDA_CLKOUT_B Pin PTC -#define PIN_CLKOUT_B_PORT PORTC -#define PIN_CLKOUT_B_GPIO PTC -#define PIN_CLKOUT_B_BIT 3 -#define PIN_CLKOUT_B (1 << PIN_CLKOUT_B_BIT) - - -// Power and fault detection - -// PWR_REG_EN PTE12 -#define PIN_POWER_EN_PORT PORTE -#define PIN_POWER_EN_GPIO PTE -#define PIN_POWER_EN_BIT 12 -#define PIN_POWER_EN (1 << PIN_POWER_EN_BIT) - -// VTRG_FAULT_B PTE11 -#define PIN_VTRG_FAULT_B_PORT PORTE -#define PIN_VTRG_FAULT_B_GPIO PTE -#define PIN_VTRG_FAULT_B_BIT 11 +// SWDIO Output Enable Pin PIO0_28 (O) +// (DBGIF_TMS_SWDIO_TXEN) +#define PIN_SWDIO_OE_BIT (28) -// Debug Unit LEDs +// TDI Output Pin PIO0_1 (O) +// (DBGIF_TDI) +#define PIN_TDI_BIT (1) -// Connected LED PTD4 -#define LED_CONNECTED_PORT PORTD -#define LED_CONNECTED_GPIO PTD -#define LED_CONNECTED_BIT 4 -#define LED_CONNECTED (1 << LED_CONNECTED_BIT) +// TDO/SWO Input Pin PIO0_3 (I) +// (DBGIF_TDO_SWO) +// SWO = function 1 (FC3_RXD_SDA_MOSI_DATA) +#define PIN_SWO_RX_BIT (3) + +// nRESET Pin PIO0_19 (O) +// (DBGIF_RESET) +#define PIN_RESET_BIT (19) +#define PIN_RESET (1 << PIN_RESET_BIT) + +// nRESET Pin Output Enable PIO0_13 (O) +// (DBGIF_RESET_TXEN) +#define PIN_RESET_EN_BIT (13) +#define PIN_RESET_EN (1 << PIN_RESET_EN_BIT) + +// SWD Detect Pin PIO0_22 (I, pullup) +// (DBGIF_DETECT) +#define PIN_SWD_DETECT_BIT (22) +#define PIN_SWD_DETECT (1 << PIN_SWD_DETECT_BIT) + + +// UART +// RX = PIO0_24, function 1 (FC0_RXD_SDA_MOSI_DATA) +// TX = PIO0_25, function 1 (FC0_TXD_SCL_MISO_WS) + +// DBGIF_VREF = PIO0_31 (Analog input, 1/2 target VREF) -// Target Running LED Not available // Debug Unit LEDs -// HID_LED PTD4 -#define PIN_HID_LED_PORT PORTD -#define PIN_HID_LED_GPIO PTD -#define PIN_HID_LED_BIT (4) -#define PIN_HID_LED (1< Date: Mon, 7 Dec 2020 17:28:57 -0600 Subject: [PATCH 125/617] LPC55xx: internal flash driver. --- source/hic_hal/nxp/lpc55xx/FlashPrg.c | 45 ++++++--------------------- 1 file changed, 9 insertions(+), 36 deletions(-) diff --git a/source/hic_hal/nxp/lpc55xx/FlashPrg.c b/source/hic_hal/nxp/lpc55xx/FlashPrg.c index 441671406..1d01c1ebe 100644 --- a/source/hic_hal/nxp/lpc55xx/FlashPrg.c +++ b/source/hic_hal/nxp/lpc55xx/FlashPrg.c @@ -3,7 +3,7 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2020, Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -19,33 +19,15 @@ * limitations under the License. */ +#include #include "FlashOS.h" // FlashOS Structures -#include "fsl_flash.h" -#include "string.h" +#include "fsl_iap.h" #include "cortex_m.h" flash_config_t g_flash; //!< Storage for flash driver. uint32_t Init(uint32_t adr, uint32_t clk, uint32_t fnc) { - cortex_int_state_t state = cortex_int_get_and_disable(); -#if defined (WDOG) - /* Write 0xC520 to the unlock register */ - WDOG->UNLOCK = 0xC520; - /* Followed by 0xD928 to complete the unlock */ - WDOG->UNLOCK = 0xD928; - /* Clear the WDOGEN bit to disable the watchdog */ - WDOG->STCTRLH &= ~WDOG_STCTRLH_WDOGEN_MASK; -#else -#ifdef LPC55_FIXME - /* FIXME: Commenting out next line which seems to disable the watchdog? - source/hic_hal/freescale/kl26z/MKL26Z4/system_MKL26Z4.c:SystemInit.c - */ - SIM->COPC = 0x00u; -#endif -#endif - cortex_int_restore(state); - return (FLASH_Init(&g_flash) != kStatus_Success); } @@ -105,14 +87,8 @@ uint32_t UnInit(uint32_t fnc) */ uint32_t EraseChip(void) { - cortex_int_state_t state = cortex_int_get_and_disable(); - int status = FLASH_EraseAll(&g_flash, kFLASH_apiEraseKey); - if (status == kStatus_Success) - { - status = FLASH_VerifyEraseAll(&g_flash, kFLASH_marginValueNormal); - } - cortex_int_restore(state); - return status; + // Not used in DAPLink. + return 1; } /* @@ -123,10 +99,10 @@ uint32_t EraseChip(void) uint32_t EraseSector(uint32_t adr) { cortex_int_state_t state = cortex_int_get_and_disable(); - int status = FLASH_Erase(&g_flash, adr, g_flash.PFlashSectorSize, kFLASH_apiEraseKey); + int status = FLASH_Erase(&g_flash, adr, g_flash.PFlashSectorSize, kFLASH_ApiEraseKey); if (status == kStatus_Success) { - status = FLASH_VerifyErase(&g_flash, adr, g_flash.PFlashSectorSize, kFLASH_marginValueNormal); + status = FLASH_VerifyErase(&g_flash, adr, g_flash.PFlashSectorSize); } cortex_int_restore(state); return status; @@ -142,13 +118,10 @@ uint32_t EraseSector(uint32_t adr) uint32_t ProgramPage(uint32_t adr, uint32_t sz, uint32_t *buf) { cortex_int_state_t state = cortex_int_get_and_disable(); - int status = FLASH_Program(&g_flash, adr, buf, sz); + int status = FLASH_Program(&g_flash, adr, (uint8_t *)buf, sz); if (status == kStatus_Success) { - // Must use kFlashMargin_User, or kFlashMargin_Factory for verify program - status = FLASH_VerifyProgram(&g_flash, adr, sz, - buf, kFLASH_marginValueUser, - NULL, NULL); + status = FLASH_VerifyProgram(&g_flash, adr, sz, (uint8_t *)buf, NULL, NULL); } cortex_int_restore(state); return status; From c0b356b85f269c87f28798a961dc20a964962819 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Mon, 7 Dec 2020 17:45:25 -0600 Subject: [PATCH 126/617] LPC55xx: read UID implementation. --- source/hic_hal/nxp/lpc55xx/read_uid.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/source/hic_hal/nxp/lpc55xx/read_uid.c b/source/hic_hal/nxp/lpc55xx/read_uid.c index 8606681de..f2402af9e 100644 --- a/source/hic_hal/nxp/lpc55xx/read_uid.c +++ b/source/hic_hal/nxp/lpc55xx/read_uid.c @@ -3,7 +3,7 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2020 Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -19,20 +19,15 @@ * limitations under the License. */ -#include "fsl_device_registers.h" +#include #include "read_uid.h" +//! The RFC4122-compliant UUID resides in the Protected Flash Region. +#define UUID_ADDR (0x0009FC70) + +#define UUID_LENGTH (16) + void read_unique_id(uint32_t *id) { -#ifdef LPC55_FIXME - id[0] = SIM->UIDL; - id[1] = SIM->UIDML; - id[2] = SIM->UIDMH; - id[3] = SIM->UIDH; -#else - id[0] = 0; - id[1] = 0; - id[2] = 0; - id[3] = 0; -#endif + memcpy(id, (void *)UUID_ADDR, UUID_LENGTH); } From 07b385f8793a7bbd72cada35623daa61573f4bc6 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 7 Dec 2020 23:24:32 -0600 Subject: [PATCH 127/617] LPC55xx: Initial stab at uart.c port to fsl_uart_cmsis API --- records/hic_hal/lpc55s69.yaml | 3 +- source/hic_hal/nxp/lpc55xx/DAP_config.h | 2 +- .../nxp/lpc55xx/LPC55S69/drivers/fsl_dma.h | 880 ++++ .../LPC55S69/drivers/fsl_usart_cmsis.c | 3562 +++++++++++++++++ .../LPC55S69/drivers/fsl_usart_cmsis.h | 94 + .../lpc55xx/LPC55S69/drivers/fsl_usart_dma.h | 161 + source/hic_hal/nxp/lpc55xx/RTE_Device.h | 205 +- source/hic_hal/nxp/lpc55xx/pin_mux.c | 145 + source/hic_hal/nxp/lpc55xx/pin_mux.h | 53 + source/hic_hal/nxp/lpc55xx/uart.c | 257 +- 10 files changed, 5194 insertions(+), 168 deletions(-) create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_dma.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart_cmsis.c create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart_cmsis.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart_dma.h create mode 100644 source/hic_hal/nxp/lpc55xx/pin_mux.c create mode 100644 source/hic_hal/nxp/lpc55xx/pin_mux.h diff --git a/records/hic_hal/lpc55s69.yaml b/records/hic_hal/lpc55s69.yaml index e0922a78d..0a4bca259 100644 --- a/records/hic_hal/lpc55s69.yaml +++ b/records/hic_hal/lpc55s69.yaml @@ -12,7 +12,6 @@ common: - source/hic_hal/nxp/lpc55xx - source/hic_hal/nxp/lpc55xx/LPC55S69 - source/hic_hal/nxp/lpc55xx/LPC55S69/drivers - - projectfiles/uvision/lpc55xx_bl/build sources: hic_hal: - source/hic_hal/nxp/lpc55xx @@ -31,6 +30,8 @@ tool_specific: - --no_unaligned_access asm_flags: - --no_unaligned_access + includes: + - projectfiles/uvision/lpc55xx_bl/build sources: hic_hal: - source/hic_hal/nxp/lpc55xx/armcc diff --git a/source/hic_hal/nxp/lpc55xx/DAP_config.h b/source/hic_hal/nxp/lpc55xx/DAP_config.h index 24a5511f3..7076f360b 100644 --- a/source/hic_hal/nxp/lpc55xx/DAP_config.h +++ b/source/hic_hal/nxp/lpc55xx/DAP_config.h @@ -90,7 +90,7 @@ This information includes: /// Indicate that UART Serial Wire Output (SWO) trace is available. /// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available +#define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available /// Maximum SWO UART Baudrate #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_dma.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_dma.h new file mode 100644 index 000000000..e215822ff --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_dma.h @@ -0,0 +1,880 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_DMA_H_ +#define _FSL_DMA_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dma + * @{ + */ + +/*! @file */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief DMA driver version */ +#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 1)) /*!< Version 2.4.1. */ +/*@}*/ + +/*! @brief DMA max transfer size */ +#define DMA_MAX_TRANSFER_COUNT 0x400U +/*! @brief DMA channel numbers */ +#if defined FSL_FEATURE_DMA_NUMBER_OF_CHANNELS +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) FSL_FEATURE_DMA_NUMBER_OF_CHANNELS +#define FSL_FEATURE_DMA_MAX_CHANNELS FSL_FEATURE_DMA_NUMBER_OF_CHANNELS +#define FSL_FEATURE_DMA_ALL_CHANNELS (FSL_FEATURE_DMA_NUMBER_OF_CHANNELS * FSL_FEATURE_SOC_DMA_COUNT) +#endif +/*! @brief DMA head link descriptor table align size */ +#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) +/*! @brief DMA head descriptor table allocate macro + * To simplify user interface, this macro will help allocate descriptor memory, + * user just need to provide the name and the number for the allocate descriptor. + * + * @param name Allocate decriptor name. + * @param number Number of descriptor to be allocated. + */ +#define DMA_ALLOCATE_HEAD_DESCRIPTORS(name, number) \ + SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE) +/*! @brief DMA head descriptor table allocate macro at noncacheable section + * To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, + * user just need to provide the name and the number for the allocate descriptor. + * + * @param name Allocate decriptor name. + * @param number Number of descriptor to be allocated. + */ +#define DMA_ALLOCATE_HEAD_DESCRIPTORS_AT_NONCACHEABLE(name, number) \ + AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE) +/*! @brief DMA link descriptor table allocate macro + * To simplify user interface, this macro will help allocate descriptor memory, + * user just need to provide the name and the number for the allocate descriptor. + * + * @param name Allocate decriptor name. + * @param number Number of descriptor to be allocated. + */ +#define DMA_ALLOCATE_LINK_DESCRIPTORS(name, number) \ + SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE) +/*! @brief DMA link descriptor table allocate macro at noncacheable section + * To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, + * user just need to provide the name and the number for the allocate descriptor. + * + * @param name Allocate decriptor name. + * @param number Number of descriptor to be allocated. + */ +#define DMA_ALLOCATE_LINK_DESCRIPTORS_AT_NONCACHEABLE(name, number) \ + AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE) +/*! @brief DMA transfer buffer address need to align with the transfer width */ +#define DMA_ALLOCATE_DATA_TRANSFER_BUFFER(name, width) SDK_ALIGN(name, width) +/* Channel group consists of 32 channels. channel_group = (channel / 32) */ +#define DMA_CHANNEL_GROUP(channel) (((uint8_t)(channel)) >> 5U) +/* Channel index in channel group. channel_index = (channel % 32) */ +#define DMA_CHANNEL_INDEX(channel) (((uint8_t)(channel)) & 0x1FU) +/*! @brief DMA linked descriptor address algin size */ +#define DMA_COMMON_REG_GET(base, channel, reg) \ + (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) +#define DMA_COMMON_CONST_REG_GET(base, channel, reg) \ + (((volatile const uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) +#define DMA_COMMON_REG_SET(base, channel, reg, value) \ + (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)] = (value)) + +/*! @brief DMA descriptor end address calculate + * @param start start address + * @param inc address interleave size + * @param bytes transfer bytes + * @param width transfer width + */ +#define DMA_DESCRIPTOR_END_ADDRESS(start, inc, bytes, width) \ + ((uint32_t *)((uint32_t)(start) + (inc) * (bytes) - (inc) * (width))) + +/*! @brief DMA channel transfer configurations macro + * @param reload true is reload link descriptor after current exhaust, false is not + * @param clrTrig true is clear trigger status, wait software trigger, false is not + * @param intA enable interruptA + * @param intB enable interruptB + * @param width transfer width + * @param srcInc source address interleave size + * @param dstInc destination address interleave size + * @param bytes transfer bytes + */ +#define DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes) \ + DMA_CHANNEL_XFERCFG_CFGVALID_MASK | DMA_CHANNEL_XFERCFG_RELOAD(reload) | DMA_CHANNEL_XFERCFG_CLRTRIG(clrTrig) | \ + DMA_CHANNEL_XFERCFG_SETINTA(intA) | DMA_CHANNEL_XFERCFG_SETINTB(intB) | \ + DMA_CHANNEL_XFERCFG_WIDTH(width == 4UL ? 2UL : (width - 1UL)) | \ + DMA_CHANNEL_XFERCFG_SRCINC(srcInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (srcInc - 1UL) : srcInc) | \ + DMA_CHANNEL_XFERCFG_DSTINC(dstInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (dstInc - 1UL) : dstInc) | \ + DMA_CHANNEL_XFERCFG_XFERCOUNT(bytes / width - 1UL) + +/*! @brief _dma_transfer_status DMA transfer status */ +enum +{ + kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the + transfer request. */ +}; + +/*! @brief _dma_addr_interleave_size dma address interleave size */ +enum +{ + kDMA_AddressInterleave0xWidth = 0U, /*!< dma source/destination address no interleave */ + kDMA_AddressInterleave1xWidth = 1U, /*!< dma source/destination address interleave 1xwidth */ + kDMA_AddressInterleave2xWidth = 2U, /*!< dma source/destination address interleave 2xwidth */ + kDMA_AddressInterleave4xWidth = 4U, /*!< dma source/destination address interleave 3xwidth */ +}; + +/*! @brief _dma_transfer_width dma transfer width */ +enum +{ + kDMA_Transfer8BitWidth = 1U, /*!< dma channel transfer bit width is 8 bit */ + kDMA_Transfer16BitWidth = 2U, /*!< dma channel transfer bit width is 16 bit */ + kDMA_Transfer32BitWidth = 4U, /*!< dma channel transfer bit width is 32 bit */ +}; + +/*! @brief DMA descriptor structure */ +typedef struct _dma_descriptor +{ + volatile uint32_t xfercfg; /*!< Transfer configuration */ + void *srcEndAddr; /*!< Last source address of DMA transfer */ + void *dstEndAddr; /*!< Last destination address of DMA transfer */ + void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */ +} dma_descriptor_t; + +/*! @brief DMA transfer configuration */ +typedef struct _dma_xfercfg +{ + bool valid; /*!< Descriptor is ready to transfer */ + bool reload; /*!< Reload channel configuration register after + current descriptor is exhausted */ + bool swtrig; /*!< Perform software trigger. Transfer if fired + when 'valid' is set */ + bool clrtrig; /*!< Clear trigger */ + bool intA; /*!< Raises IRQ when transfer is done and set IRQA status register flag */ + bool intB; /*!< Raises IRQ when transfer is done and set IRQB status register flag */ + uint8_t byteWidth; /*!< Byte width of data to transfer */ + uint8_t srcInc; /*!< Increment source address by 'srcInc' x 'byteWidth' */ + uint8_t dstInc; /*!< Increment destination address by 'dstInc' x 'byteWidth' */ + uint16_t transferCount; /*!< Number of transfers */ +} dma_xfercfg_t; + +/*! @brief DMA channel priority */ +typedef enum _dma_priority +{ + kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */ + kDMA_ChannelPriority1, /*!< Channel priority 1 */ + kDMA_ChannelPriority2, /*!< Channel priority 2 */ + kDMA_ChannelPriority3, /*!< Channel priority 3 */ + kDMA_ChannelPriority4, /*!< Channel priority 4 */ + kDMA_ChannelPriority5, /*!< Channel priority 5 */ + kDMA_ChannelPriority6, /*!< Channel priority 6 */ + kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */ +} dma_priority_t; + +/*! @brief DMA interrupt flags */ +typedef enum _dma_int +{ + kDMA_IntA, /*!< DMA interrupt flag A */ + kDMA_IntB, /*!< DMA interrupt flag B */ + kDMA_IntError, /*!< DMA interrupt flag error */ +} dma_irq_t; + +/*! @brief DMA trigger type*/ +typedef enum _dma_trigger_type +{ + kDMA_NoTrigger = 0, /*!< Trigger is disabled */ + kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */ + kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | + DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */ + kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */ + kDMA_RisingEdgeTrigger = + DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */ +} dma_trigger_type_t; + +/*! @brief _dma_burst_size DMA burst size*/ +enum +{ + kDMA_BurstSize1 = 0U, /*!< burst size 1 transfer */ + kDMA_BurstSize2 = 1U, /*!< burst size 2 transfer */ + kDMA_BurstSize4 = 2U, /*!< burst size 4 transfer */ + kDMA_BurstSize8 = 3U, /*!< burst size 8 transfer */ + kDMA_BurstSize16 = 4U, /*!< burst size 16 transfer */ + kDMA_BurstSize32 = 5U, /*!< burst size 32 transfer */ + kDMA_BurstSize64 = 6U, /*!< burst size 64 transfer */ + kDMA_BurstSize128 = 7U, /*!< burst size 128 transfer */ + kDMA_BurstSize256 = 8U, /*!< burst size 256 transfer */ + kDMA_BurstSize512 = 9U, /*!< burst size 512 transfer */ + kDMA_BurstSize1024 = 10U, /*!< burst size 1024 transfer */ +}; + +/*! @brief DMA trigger burst */ +typedef enum _dma_trigger_burst +{ + kDMA_SingleTransfer = 0, /*!< Single transfer */ + kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */ + kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */ + kDMA_EdgeBurstTransfer2 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */ + kDMA_EdgeBurstTransfer4 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */ + kDMA_EdgeBurstTransfer8 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */ + kDMA_EdgeBurstTransfer16 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */ + kDMA_EdgeBurstTransfer32 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */ + kDMA_EdgeBurstTransfer64 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */ + kDMA_EdgeBurstTransfer128 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */ + kDMA_EdgeBurstTransfer256 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */ + kDMA_EdgeBurstTransfer512 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */ + kDMA_EdgeBurstTransfer1024 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */ +} dma_trigger_burst_t; + +/*! @brief DMA burst wrapping */ +typedef enum _dma_burst_wrap +{ + kDMA_NoWrap = 0, /*!< Wrapping is disabled */ + kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */ + kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */ + kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | + DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */ +} dma_burst_wrap_t; + +/*! @brief DMA transfer type */ +typedef enum _dma_transfer_type +{ + kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */ + kDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory (increment only destination) */ + kDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral (increment only source)*/ + kDMA_StaticToStatic, /*!< Peripheral to static memory (do not increment source or destination) */ +} dma_transfer_type_t; + +/*! @brief DMA channel trigger */ +typedef struct _dma_channel_trigger +{ + dma_trigger_type_t type; /*!< Select hardware trigger as edge triggered or level triggered. */ + dma_trigger_burst_t burst; /*!< Select whether hardware triggers cause a single or burst transfer. */ + dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */ +} dma_channel_trigger_t; + +/*! @brief DMA channel trigger */ +typedef struct _dma_channel_config +{ + void *srcStartAddr; /*!< Source data address */ + void *dstStartAddr; /*!< Destination data address */ + void *nextDesc; /*!< Chain custom descriptor */ + uint32_t xferCfg; /*!< channel transfer configurations */ + dma_channel_trigger_t *trigger; /*!< DMA trigger type */ + bool isPeriph; /*!< select the request type */ +} dma_channel_config_t; + +/*! @brief DMA transfer configuration */ +typedef struct _dma_transfer_config +{ + uint8_t *srcAddr; /*!< Source data address */ + uint8_t *dstAddr; /*!< Destination data address */ + uint8_t *nextDesc; /*!< Chain custom descriptor */ + dma_xfercfg_t xfercfg; /*!< Transfer options */ + bool isPeriph; /*!< DMA transfer is driven by peripheral */ +} dma_transfer_config_t; + +/*! @brief Callback for DMA */ +struct _dma_handle; + +/*! @brief Define Callback function for DMA. */ +typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode); + +/*! @brief DMA transfer handle structure */ +typedef struct _dma_handle +{ + dma_callback callback; /*!< Callback function. Invoked when transfer + of descriptor with interrupt flag finishes */ + void *userData; /*!< Callback function parameter */ + DMA_Type *base; /*!< DMA peripheral base address */ + uint8_t channel; /*!< DMA channel number */ +} dma_handle_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name DMA initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes DMA peripheral. + * + * This function enable the DMA clock, set descriptor table and + * enable DMA peripheral. + * + * @param base DMA peripheral base address. + */ +void DMA_Init(DMA_Type *base); + +/*! + * @brief Deinitializes DMA peripheral. + * + * This function gates the DMA clock. + * + * @param base DMA peripheral base address. + */ +void DMA_Deinit(DMA_Type *base); + +/*! + * @brief Install DMA descriptor memory. + * + * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong + * transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has + * a default DMA descriptor buffer, but it support one DMA descriptor for one channel only. + * + * @param base DMA base address. + * @param addr DMA descriptor address + */ +void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr); + +/* @} */ + +/*! + * @name DMA Channel Operation + * @{ + */ + +/*! + * @brief Return whether DMA channel is processing transfer + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return True for active state, false otherwise. + */ +static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + return (DMA_COMMON_CONST_REG_GET(base, channel, ACTIVE) & (1UL << DMA_CHANNEL_INDEX(channel))) != 0UL; +} + +/*! + * @brief Return whether DMA channel is busy + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return True for busy state, false otherwise. + */ +static inline bool DMA_ChannelIsBusy(DMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + return (DMA_COMMON_CONST_REG_GET(base, channel, BUSY) & (1UL << DMA_CHANNEL_INDEX(channel))) != 0UL; +} + +/*! + * @brief Enables the interrupt source for the DMA transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + DMA_COMMON_REG_GET(base, channel, INTENSET) |= 1UL << DMA_CHANNEL_INDEX(channel); +} + +/*! + * @brief Disables the interrupt source for the DMA transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + DMA_COMMON_REG_GET(base, channel, INTENCLR) |= 1UL << DMA_CHANNEL_INDEX(channel); +} + +/*! + * @brief Enable DMA channel. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + DMA_COMMON_REG_GET(base, channel, ENABLESET) |= 1UL << DMA_CHANNEL_INDEX(channel); +} + +/*! + * @brief Disable DMA channel. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + DMA_COMMON_REG_GET(base, channel, ENABLECLR) |= 1UL << DMA_CHANNEL_INDEX(channel); +} + +/*! + * @brief Set PERIPHREQEN of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK; +} + +/*! + * @brief Get PERIPHREQEN value of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return True for enabled PeriphRq, false for disabled. + */ +static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK; +} + +/*! + * @brief Set trigger settings of DMA channel. + * @deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param trigger trigger configuration. + */ +void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger); + +/*! + * @brief set channel config. + * + * This function provide a interface to configure channel configuration reisters. + * + * @param base DMA base address. + * @param channel DMA channel number. + * @param trigger channel configurations structure. + * @param isPeriph true is periph request, false is not. + */ +void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph); + +/*! + * @brief Gets the remaining bytes of the current DMA descriptor transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return The number of bytes which have not been transferred yet. + */ +uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel); + +/*! + * @brief Set priority of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param priority Channel priority value. + */ +static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + base->CHANNEL[channel].CFG = + (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority); +} + +/*! + * @brief Get priority of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return Channel priority value. + */ +static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + return (dma_priority_t)(uint8_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> + DMA_CHANNEL_CFG_CHPRIORITY_SHIFT); +} + +/*! + * @brief Set channel configuration valid. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_SetChannelConfigValid(DMA_Type *base, uint32_t channel) +{ + base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_CFGVALID_MASK; +} + +/*! + * @brief Do software trigger for the channel. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_DoChannelSoftwareTrigger(DMA_Type *base, uint32_t channel) +{ + base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; +} + +/*! + * @brief Load channel transfer configurations. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param xfer transfer configurations. + */ +static inline void DMA_LoadChannelTransferConfig(DMA_Type *base, uint32_t channel, uint32_t xfer) +{ + base->CHANNEL[channel].XFERCFG = xfer; +} + +/*! + * @brief Create application specific DMA descriptor + * to be used in a chain in transfer + * @deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor. + * @param desc DMA descriptor address. + * @param xfercfg Transfer configuration for DMA descriptor. + * @param srcAddr Address of last item to transmit + * @param dstAddr Address of last item to receive. + * @param nextDesc Address of next descriptor in chain. + */ +void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc); + +/*! + * @brief setup dma descriptor + * + * Note: This function do not support configure wrap descriptor. + * + * @param desc DMA descriptor address. + * @param xfercfg Transfer configuration for DMA descriptor. + * @param srcStartAddr Start address of source address. + * @param dstStartAddr Start address of destination address. + * @param nextDesc Address of next descriptor in chain. + */ +void DMA_SetupDescriptor( + dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc); + +/*! + * @brief setup dma channel descriptor + * + * Note: This function support configure wrap descriptor. + * + * @param desc DMA descriptor address. + * @param xfercfg Transfer configuration for DMA descriptor. + * @param srcStartAddr Start address of source address. + * @param dstStartAddr Start address of destination address. + * @param nextDesc Address of next descriptor in chain. + * @param wrapType burst wrap type. + * @param burstSize burst size, reference _dma_burst_size. + */ +void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, + uint32_t xfercfg, + void *srcStartAddr, + void *dstStartAddr, + void *nextDesc, + dma_burst_wrap_t wrapType, + uint32_t burstSize); + +/*! + * @brief load channel transfer decriptor. + * + * This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA + * transfer, the head descriptor table is defined in DMA driver, it is useful for the case: + * 1. for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly + * and then call this api to load the configured descriptor to driver descriptor table. + * @code + * DMA_Init(DMA0); + * DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL); + * DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL); + * DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc); + * DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL); + * while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL)) + * {} + * @endcode + * + * @param base DMA base address. + * @param channel DMA channel. + * @param descriptor configured DMA descriptor. + */ +void DMA_LoadChannelDescriptor(DMA_Type *base, uint32_t channel, dma_descriptor_t *descriptor); + +/* @} */ + +/*! + * @name DMA Transactional Operation + * @{ + */ + +/*! + * @brief Abort running transfer by handle. + * + * This function aborts DMA transfer specified by handle. + * + * @param handle DMA handle pointer. + */ +void DMA_AbortTransfer(dma_handle_t *handle); + +/*! + * @brief Creates the DMA handle. + * + * This function is called if using transaction API for DMA. This function + * initializes the internal state of DMA handle. + * + * @param handle DMA handle pointer. The DMA handle stores callback function and + * parameters. + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel); + +/*! + * @brief Installs a callback function for the DMA transfer. + * + * This callback is called in DMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. + * + * @param handle DMA handle pointer. + * @param callback DMA callback function pointer. + * @param userData Parameter for callback function. + */ +void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData); + +/*! + * @brief Prepares the DMA transfer structure. + * @deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer. + * This function prepares the transfer configuration structure according to the user input. + * + * @param config The user configuration structure of type dma_transfer_t. + * @param srcAddr DMA transfer source address. + * @param dstAddr DMA transfer destination address. + * @param byteWidth DMA transfer destination address width(bytes). + * @param transferBytes DMA transfer bytes to be transferred. + * @param type DMA transfer type. + * @param nextDesc Chain custom descriptor to transfer. + * @note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in + * source address error(SAE). + */ +void DMA_PrepareTransfer(dma_transfer_config_t *config, + void *srcAddr, + void *dstAddr, + uint32_t byteWidth, + uint32_t transferBytes, + dma_transfer_type_t type, + void *nextDesc); + +/*! + * @brief Prepare channel transfer configurations. + * + * This function used to prepare channel transfer configurations. + * + * @param config Pointer to DMA channel transfer configuration structure. + * @param srcStartAddr source start address. + * @param dstStartAddr destination start address. + * @param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. + * @param type transfer type. + * @param trigger DMA channel trigger configurations. + * @param nextDesc address of next descriptor. + */ +void DMA_PrepareChannelTransfer(dma_channel_config_t *config, + void *srcStartAddr, + void *dstStartAddr, + uint32_t xferCfg, + dma_transfer_type_t type, + dma_channel_trigger_t *trigger, + void *nextDesc); + +/*! + * @brief Submits the DMA transfer request. + * @deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer. + * + * This function submits the DMA transfer request according to the transfer configuration structure. + * If the user submits the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * + * @param handle DMA handle pointer. + * @param config Pointer to DMA transfer configuration structure. + * @retval kStatus_DMA_Success It means submit transfer request succeed. + * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config); + +/*! + * @brief Submit channel transfer paramter directly. + * + * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table + * is defined in DMA driver, it is useful for the case: + * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used + for it. + * @code + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, + bytes), srcStartAddr, dstStartAddr, NULL); + DMA_StartTransfer(handle) + * @endcode + * + * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is + required, then application should prepare + * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * @code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc2); + DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, NULL); + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, + bytes), srcStartAddr, dstStartAddr, nextDesc0); + DMA_StartTransfer(handle); + * @endcode + * + * @param handle Pointer to DMA handle. + * @param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. + * @param srcStartAddr source start address. + * @param dstStartAddr destination start address. + * @param nextDesc address of next descriptor. + */ +void DMA_SubmitChannelTransferParameter( + dma_handle_t *handle, uint32_t xferCfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc); + +/*! + * @brief Submit channel descriptor. + * + * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table + is defined in + * DMA driver, this functiono is typical for the ping pong case: + * + * 1. for the ping pong case, application should responsible for the descriptor, for example, application should + * prepare two descriptor table with macro. + * @code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc0); + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelDescriptor(handle, nextDesc0); + DMA_StartTransfer(handle); + * @endcode + * + * @param handle Pointer to DMA handle. + * @param descriptor descriptor to submit. + */ +void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descriptor); + +/*! + * @brief Submits the DMA channel transfer request. + * + * This function submits the DMA transfer request according to the transfer configuration structure. + * If the user submits the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * It is used for the case: + * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used + for it. + * @code + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,NULL); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * @endcode + * + * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is + required, then application should prepare + * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * @code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc2); + DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, NULL); + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * @endcode + * + * 3. for the ping pong case, application should responsible for link descriptor, for example, application should + prepare + * two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * @code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc0); + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * @endcode + * @param handle DMA handle pointer. + * @param config Pointer to DMA transfer configuration structure. + * @retval kStatus_DMA_Success It means submit transfer request succeed. + * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config); + +/*! + * @brief DMA start transfer. + * + * This function enables the channel request. User can call this function after submitting the transfer request + * It will trigger transfer start with software trigger only when hardware trigger is not used. + * + * @param handle DMA handle pointer. + */ +void DMA_StartTransfer(dma_handle_t *handle); + +/*! + * @brief DMA IRQ handler for descriptor transfer complete. + * + * This function clears the channel major interrupt flag and call + * the callback function if it is not NULL. + * + * @param base DMA base address. + */ +void DMA_IRQHandle(DMA_Type *base); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /*_FSL_DMA_H_*/ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart_cmsis.c b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart_cmsis.c new file mode 100644 index 000000000..6e6a200a0 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart_cmsis.c @@ -0,0 +1,3562 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2017 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "fsl_usart_cmsis.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_cmsis" +#endif + +#if (RTE_USART0 || RTE_USART1 || RTE_USART2 || RTE_USART3 || RTE_USART4 || RTE_USART5 || RTE_USART6 || RTE_USART7 || \ + RTE_USART8 || RTE_USART9 || RTE_USART10 || RTE_USART11 || RTE_USART12 || RTE_USART13) + +#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) + +/* + * ARMCC does not support split the data section automatically, so the driver + * needs to split the data to separate sections explicitly, to reduce codesize. + */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) +#endif + +typedef const struct _cmsis_usart_resource +{ + USART_Type *base; /*!< usart peripheral base address. */ + uint32_t (*GetFreq)(void); /*!< Function to get the clock frequency. */ +} cmsis_usart_resource_t; + +typedef struct _cmsis_usart_non_blocking_driver_state +{ + cmsis_usart_resource_t *resource; /*!< Basic usart resource. */ + usart_handle_t *handle; /*!< Interupt transfer handle. */ + ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */ + uint8_t flags; /*!< Control and state flags. */ +} cmsis_usart_non_blocking_driver_state_t; + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) +typedef const struct _cmsis_usart_dma_resource +{ + DMA_Type *txDmaBase; /*!< DMA peripheral base address for TX. */ + uint32_t txDmaChannel; /*!< DMA channel for usart TX. */ + + DMA_Type *rxDmaBase; /*!< DMA peripheral base address for RX. */ + uint32_t rxDmaChannel; /*!< DMA channel for usart RX. */ +} cmsis_usart_dma_resource_t; + +typedef struct _cmsis_usart_dma_driver_state +{ + cmsis_usart_resource_t *resource; /*!< usart basic resource. */ + cmsis_usart_dma_resource_t *dmaResource; /*!< usart DMA resource. */ + usart_dma_handle_t *handle; /*!< usart DMA transfer handle. */ + dma_handle_t *rxHandle; /*!< DMA RX handle. */ + dma_handle_t *txHandle; /*!< DMA TX handle. */ + ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */ + uint8_t flags; /*!< Control and state flags. */ +} cmsis_usart_dma_driver_state_t; +#endif + +enum _usart_transfer_states +{ + kUSART_TxIdle, /*!< TX idle. */ + kUSART_TxBusy, /*!< TX busy. */ + kUSART_RxIdle, /*!< RX idle. */ + kUSART_RxBusy /*!< RX busy. */ +}; + +/* Driver Version */ +static const ARM_DRIVER_VERSION s_usartDriverVersion = {ARM_USART_API_VERSION, ARM_USART_DRV_VERSION}; + +static const ARM_USART_CAPABILITIES s_usartDriverCapabilities = { + 1, /* supports usart (Asynchronous) mode */ + 0, /* supports Synchronous Master mode */ + 0, /* supports Synchronous Slave mode */ + 0, /* supports usart Single-wire mode */ + 0, /* supports usart IrDA mode */ + 0, /* supports usart Smart Card mode */ + 0, /* Smart Card Clock generator */ + 0, /* RTS Flow Control available */ + 0, /* CTS Flow Control available */ + 0, /* Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE */ + 0, /* Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT */ + 0, /* RTS Line: 0=not available, 1=available */ + 0, /* CTS Line: 0=not available, 1=available */ + 0, /* DTR Line: 0=not available, 1=available */ + 0, /* DSR Line: 0=not available, 1=available */ + 0, /* DCD Line: 0=not available, 1=available */ + 0, /* RI Line: 0=not available, 1=available */ + 0, /* Signal CTS change event: \ref ARM_USART_EVENT_CTS */ + 0, /* Signal DSR change event: \ref ARM_USART_EVENT_DSR */ + 0, /* Signal DCD change event: \ref ARM_USART_EVENT_DCD */ + 0, /* Signal RI change event: \ref ARM_USART_EVENT_RI */ +}; + +/* + * Common control function used by usart_NonBlockingControl/usart_DmaControl/usart_EdmaControl + */ +static int32_t USART_CommonControl(uint32_t control, + uint32_t arg, + cmsis_usart_resource_t *resource, + uint8_t *isConfigured) +{ + usart_config_t config; + + USART_GetDefaultConfig(&config); + + switch (control & ARM_USART_CONTROL_Msk) + { + case ARM_USART_MODE_ASYNCHRONOUS: + /* USART Baudrate */ + config.baudRate_Bps = arg; + break; + + /* TX/RX IO is controlled in application layer. */ + case ARM_USART_CONTROL_TX: + if (arg) + { + config.enableTx = true; + } + else + { + config.enableTx = false; + } + return ARM_DRIVER_OK; + + case ARM_USART_CONTROL_RX: + if (arg) + { + config.enableRx = true; + } + else + { + config.enableRx = false; + } + + return ARM_DRIVER_OK; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + switch (control & ARM_USART_PARITY_Msk) + { + case ARM_USART_PARITY_NONE: + config.parityMode = kUSART_ParityDisabled; + break; + case ARM_USART_PARITY_EVEN: + config.parityMode = kUSART_ParityEven; + break; + case ARM_USART_PARITY_ODD: + config.parityMode = kUSART_ParityOdd; + break; + default: + return ARM_USART_ERROR_PARITY; + } + + switch (control & ARM_USART_STOP_BITS_Msk) + { + case ARM_USART_STOP_BITS_1: + /* The GetDefaultConfig has already set for this case. */ + break; + case ARM_USART_STOP_BITS_2: + config.stopBitCount = kUSART_TwoStopBit; + break; + default: + return ARM_USART_ERROR_STOP_BITS; + } + + /* If usart is already configured, deinit it first. */ + if ((*isConfigured) & USART_FLAG_CONFIGURED) + { + USART_Deinit(resource->base); + *isConfigured &= ~USART_FLAG_CONFIGURED; + } + + config.enableTx = true; + config.enableRx = true; + + if (kStatus_USART_BaudrateNotSupport == USART_Init(resource->base, &config, resource->GetFreq())) + { + return ARM_USART_ERROR_BAUDRATE; + } + + *isConfigured |= USART_FLAG_CONFIGURED; + + return ARM_DRIVER_OK; +} + +static ARM_DRIVER_VERSION USARTx_GetVersion(void) +{ + return s_usartDriverVersion; +} + +static ARM_USART_CAPABILITIES USARTx_GetCapabilities(void) +{ + return s_usartDriverCapabilities; +} + +static int32_t USARTx_SetModemControl(ARM_USART_MODEM_CONTROL control) +{ + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static ARM_USART_MODEM_STATUS USARTx_GetModemStatus(void) +{ + ARM_USART_MODEM_STATUS modem_status; + + modem_status.cts = 0U; + modem_status.dsr = 0U; + modem_status.ri = 0U; + modem_status.dcd = 0U; + modem_status.reserved = 0U; + + return modem_status; +} + +#endif + +#if (RTE_USART0_DMA_EN || RTE_USART1_DMA_EN || RTE_USART2_DMA_EN || RTE_USART3_DMA_EN || RTE_USART4_DMA_EN || \ + RTE_USART5_DMA_EN || RTE_USART6_DMA_EN || RTE_USART7_DMA_EN || RTE_USART8_DMA_EN || RTE_USART9_DMA_EN || \ + RTE_USART10_DMA_EN || RTE_USART11_DMA_EN || RTE_USART12_DMA_EN || RTE_USART13_DMA_EN) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) +void KSDK_USART_DmaCallback(USART_Type *base, usart_dma_handle_t *handle, status_t status, void *userData) +{ + uint32_t event = 0U; + + if (kStatus_USART_TxIdle == status) + { + event = ARM_USART_EVENT_SEND_COMPLETE; + } + + if (kStatus_USART_RxIdle == status) + { + event = ARM_USART_EVENT_RECEIVE_COMPLETE; + } + + /* User data is actually CMSIS driver callback. */ + if (userData) + { + ((ARM_USART_SignalEvent_t)userData)(event); + } +} + +static int32_t USART_DmaInitialize(ARM_USART_SignalEvent_t cb_event, cmsis_usart_dma_driver_state_t *usart) +{ + if (!(usart->flags & USART_FLAG_INIT)) + { + usart->cb_event = cb_event; + usart->flags = USART_FLAG_INIT; + } + + return ARM_DRIVER_OK; +} + +static int32_t USART_DmaUninitialize(cmsis_usart_dma_driver_state_t *usart) +{ + usart->flags = USART_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t USART_DmaPowerControl(ARM_POWER_STATE state, cmsis_usart_dma_driver_state_t *usart) +{ + usart_config_t config; + + switch (state) + { + case ARM_POWER_OFF: + if (usart->flags & USART_FLAG_POWER) + { + USART_Deinit(usart->resource->base); + DMA_DisableChannel(usart->dmaResource->rxDmaBase, usart->dmaResource->rxDmaChannel); + DMA_DisableChannel(usart->dmaResource->txDmaBase, usart->dmaResource->txDmaChannel); + usart->flags = USART_FLAG_INIT; + } + break; + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + case ARM_POWER_FULL: + /* Must be initialized first. */ + if (usart->flags == USART_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if (usart->flags & USART_FLAG_POWER) + { + /* Driver already powered */ + break; + } + + USART_GetDefaultConfig(&config); + config.enableTx = true; + config.enableRx = true; + + /* Set up DMA setting. */ + DMA_EnableChannel(usart->dmaResource->txDmaBase, usart->dmaResource->txDmaChannel); + DMA_EnableChannel(usart->dmaResource->rxDmaBase, usart->dmaResource->rxDmaChannel); + + DMA_CreateHandle(usart->rxHandle, usart->dmaResource->rxDmaBase, usart->dmaResource->rxDmaChannel); + DMA_CreateHandle(usart->txHandle, usart->dmaResource->txDmaBase, usart->dmaResource->txDmaChannel); + + /* Setup the usart. */ + USART_Init(usart->resource->base, &config, usart->resource->GetFreq()); + USART_TransferCreateHandleDMA(usart->resource->base, usart->handle, KSDK_USART_DmaCallback, + (void *)usart->cb_event, usart->txHandle, usart->rxHandle); + + usart->flags |= (USART_FLAG_POWER | USART_FLAG_CONFIGURED); + + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +static int32_t USART_DmaSend(const void *data, uint32_t num, cmsis_usart_dma_driver_state_t *usart) +{ + int32_t ret; + status_t status; + usart_transfer_t xfer; + + xfer.data = (uint8_t *)data; + xfer.dataSize = num; + + status = USART_TransferSendDMA(usart->resource->base, usart->handle, &xfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_USART_TxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t USART_DmaReceive(void *data, uint32_t num, cmsis_usart_dma_driver_state_t *usart) +{ + int32_t ret; + status_t status; + usart_transfer_t xfer; + + xfer.data = data; + xfer.dataSize = num; + + status = USART_TransferReceiveDMA(usart->resource->base, usart->handle, &xfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_USART_RxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t USART_DmaTransfer(const void *data_out, + void *data_in, + uint32_t num, + cmsis_usart_dma_driver_state_t *usart) +{ + /* Only in synchronous mode */ + return ARM_DRIVER_ERROR; +} + +static int32_t USART_DmaGetTxCount(cmsis_usart_dma_driver_state_t *usart) +{ + /* Does not support */ + return ARM_DRIVER_ERROR; +} + +static int32_t USART_DmaGetRxCount(cmsis_usart_dma_driver_state_t *usart) +{ + /* Does not support */ + return ARM_DRIVER_ERROR; +} + +static int32_t USART_DmaControl(uint32_t control, uint32_t arg, cmsis_usart_dma_driver_state_t *usart) +{ + /* Must be power on. */ + if (!(usart->flags & USART_FLAG_POWER)) + { + return ARM_DRIVER_ERROR; + } + + /* Does not support these features. */ + if (control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + switch (control & ARM_USART_CONTROL_Msk) + { + /* Abort Send */ + case ARM_USART_ABORT_SEND: + USART_EnableTxDMA(usart->resource->base, false); + DMA_AbortTransfer(usart->handle->txDmaHandle); + usart->handle->txState = kUSART_TxIdle; + return ARM_DRIVER_OK; + + /* Abort receive */ + case ARM_USART_ABORT_RECEIVE: + USART_EnableRxDMA(usart->resource->base, false); + DMA_AbortTransfer(usart->handle->rxDmaHandle); + usart->handle->rxState = kUSART_RxIdle; + return ARM_DRIVER_OK; + + default: + break; + } + + return USART_CommonControl(control, arg, usart->resource, &usart->flags); +} + +static ARM_USART_STATUS USART_DmaGetStatus(cmsis_usart_dma_driver_state_t *usart) +{ + ARM_USART_STATUS stat; + uint32_t ksdk_usart_status = usart->resource->base->STAT; + + stat.tx_busy = ((kUSART_TxBusy == usart->handle->txState) ? (1U) : (0U)); + stat.rx_busy = ((kUSART_RxBusy == usart->handle->rxState) ? (1U) : (0U)); + + stat.tx_underflow = 0U; + stat.rx_overflow = 0U; + + stat.rx_break = (!(!(ksdk_usart_status & USART_STAT_RXBRK_MASK))); + + stat.rx_framing_error = (!(!(ksdk_usart_status & USART_STAT_FRAMERRINT_MASK))); + stat.rx_parity_error = (!(!(ksdk_usart_status & USART_STAT_PARITYERRINT_MASK))); + stat.reserved = 0U; + + return stat; +} +#endif + +#endif + +#if ((RTE_USART0 && !RTE_USART0_DMA_EN) || (RTE_USART1 && !RTE_USART1_DMA_EN) || (RTE_USART2 && !RTE_USART2_DMA_EN) || \ + (RTE_USART3 && !RTE_USART3_DMA_EN) || (RTE_USART4 && !RTE_USART4_DMA_EN) || (RTE_USART5 && !RTE_USART5_DMA_EN) || \ + (RTE_USART6 && !RTE_USART6_DMA_EN) || (RTE_USART7 && !RTE_USART7_DMA_EN) || (RTE_USART8 && !RTE_USART8_DMA_EN) || \ + (RTE_USART9 && !RTE_USART9_DMA_EN) || (RTE_USART10 && !RTE_USART10_DMA_EN) || \ + (RTE_USART11 && !RTE_USART11_DMA_EN) || (RTE_USART12 && !RTE_USART12_DMA_EN) || \ + (RTE_USART13 && !RTE_USART13_DMA_EN)) + +void KSDK_USART_NonBlockingCallback(USART_Type *base, usart_handle_t *handle, status_t status, void *userData) +{ + uint32_t event = 0U; + + if (kStatus_USART_TxIdle == status) + { + event = ARM_USART_EVENT_SEND_COMPLETE; + } + if (kStatus_USART_RxIdle == status) + { + event = ARM_USART_EVENT_RECEIVE_COMPLETE; + } + + /* User data is actually CMSIS driver callback. */ + if (userData) + { + ((ARM_USART_SignalEvent_t)userData)(event); + } +} + +static int32_t USART_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event, + cmsis_usart_non_blocking_driver_state_t *usart) +{ + if (!(usart->flags & USART_FLAG_INIT)) + { + usart->cb_event = cb_event; + usart->flags = USART_FLAG_INIT; + } + + return ARM_DRIVER_OK; +} + +static int32_t USART_NonBlockingUninitialize(cmsis_usart_non_blocking_driver_state_t *usart) +{ + usart->flags = USART_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t USART_NonBlockingPowerControl(ARM_POWER_STATE state, cmsis_usart_non_blocking_driver_state_t *usart) +{ + usart_config_t config; + + switch (state) + { + case ARM_POWER_OFF: + if (usart->flags & USART_FLAG_POWER) + { + USART_Deinit(usart->resource->base); + usart->flags = USART_FLAG_INIT; + } + break; + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + case ARM_POWER_FULL: + /* Must be initialized first. */ + if (usart->flags == USART_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if (usart->flags & USART_FLAG_POWER) + { + /* Driver already powered */ + break; + } + + USART_GetDefaultConfig(&config); + config.enableTx = true; + config.enableRx = true; + + USART_Init(usart->resource->base, &config, usart->resource->GetFreq()); + USART_TransferCreateHandle(usart->resource->base, usart->handle, KSDK_USART_NonBlockingCallback, + (void *)usart->cb_event); + usart->flags |= (USART_FLAG_POWER | USART_FLAG_CONFIGURED); + + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +static int32_t USART_NonBlockingSend(const void *data, uint32_t num, cmsis_usart_non_blocking_driver_state_t *usart) +{ + int32_t ret; + status_t status; + usart_transfer_t xfer; + + xfer.data = (uint8_t *)data; + xfer.dataSize = num; + + status = USART_TransferSendNonBlocking(usart->resource->base, usart->handle, &xfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_USART_TxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t USART_NonBlockingReceive(void *data, uint32_t num, cmsis_usart_non_blocking_driver_state_t *usart) +{ + int32_t ret; + status_t status; + usart_transfer_t xfer; + + xfer.data = data; + xfer.dataSize = num; + + status = USART_TransferReceiveNonBlocking(usart->resource->base, usart->handle, &xfer, NULL); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_USART_RxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t USART_NonBlockingTransfer(const void *data_out, + void *data_in, + uint32_t num, + cmsis_usart_non_blocking_driver_state_t *usart) +{ + /* Only in synchronous mode */ + return ARM_DRIVER_ERROR; +} + +static uint32_t USART_NonBlockingGetTxCount(cmsis_usart_non_blocking_driver_state_t *usart) +{ + uint32_t cnt; + + /* If TX not in progress, then the TX count is txDataSizeAll saved in handle. */ + if (kUSART_TxIdle == usart->handle->txState) + { + cnt = usart->handle->txDataSizeAll; + } + else + { + cnt = usart->handle->txDataSizeAll - usart->handle->txDataSize; + } + + return cnt; +} + +static uint32_t USART_NonBlockingGetRxCount(cmsis_usart_non_blocking_driver_state_t *usart) +{ + uint32_t cnt; + + if (kUSART_RxIdle == usart->handle->rxState) + { + cnt = usart->handle->rxDataSizeAll; + } + else + { + cnt = usart->handle->rxDataSizeAll - usart->handle->rxDataSize; + } + + return cnt; +} + +static int32_t USART_NonBlockingControl(uint32_t control, uint32_t arg, cmsis_usart_non_blocking_driver_state_t *usart) +{ + /* Must be power on. */ + if (!(usart->flags & USART_FLAG_POWER)) + { + return ARM_DRIVER_ERROR; + } + + /* Does not support these features. */ + if (control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + switch (control & ARM_USART_CONTROL_Msk) + { + /* Abort Send */ + case ARM_USART_ABORT_SEND: + usart->resource->base->FIFOINTENSET &= ~USART_FIFOINTENSET_TXLVL_MASK; + usart->handle->txDataSize = 0; + usart->handle->txState = kUSART_TxIdle; + return ARM_DRIVER_OK; + + /* Abort receive */ + case ARM_USART_ABORT_RECEIVE: + usart->resource->base->FIFOINTENSET &= ~USART_FIFOINTENSET_RXLVL_MASK; + usart->handle->rxDataSize = 0U; + usart->handle->rxState = kUSART_RxIdle; + return ARM_DRIVER_OK; + + default: + break; + } + + return USART_CommonControl(control, arg, usart->resource, &usart->flags); +} + +static ARM_USART_STATUS USART_NonBlockingGetStatus(cmsis_usart_non_blocking_driver_state_t *usart) +{ + ARM_USART_STATUS stat; + uint32_t ksdk_usart_status = usart->resource->base->STAT; + + stat.tx_busy = ((kUSART_TxBusy == usart->handle->txState) ? (1U) : (0U)); + stat.rx_busy = ((kUSART_RxBusy == usart->handle->rxState) ? (1U) : (0U)); + + stat.tx_underflow = 0U; + stat.rx_overflow = 0U; + + stat.rx_break = (!(!(ksdk_usart_status & USART_STAT_RXBRK_MASK))); + + stat.rx_framing_error = (!(!(ksdk_usart_status & USART_STAT_FRAMERRINT_MASK))); + stat.rx_parity_error = (!(!(ksdk_usart_status & USART_STAT_PARITYERRINT_MASK))); + stat.reserved = 0U; + + return stat; +} + +#endif + +#if defined(USART0) && RTE_USART0 + +/* User needs to provide the implementation for USART0_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART0_GetFreq(void); +extern void USART0_InitPins(void); +extern void USART0_DeinitPins(void); + +cmsis_usart_resource_t usart0_Resource = {USART0, USART0_GetFreq}; + +/* usart0 Driver Control Block */ + +#if RTE_USART0_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart0_DmaResource = { + RTE_USART0_DMA_TX_DMA_BASE, + RTE_USART0_DMA_TX_CH, + RTE_USART0_DMA_RX_DMA_BASE, + RTE_USART0_DMA_RX_CH, +}; + +usart_dma_handle_t USART0_DmaHandle; +dma_handle_t USART0_DmaRxHandle; +dma_handle_t USART0_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart0_dma_driver_state") +cmsis_usart_dma_driver_state_t usart0_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart0_DmaDriverState = { +#endif + &usart0_Resource, &usart0_DmaResource, &USART0_DmaHandle, &USART0_DmaRxHandle, &USART0_DmaTxHandle, +}; + +static int32_t USART0_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART0_InitPins(); + return USART_DmaInitialize(cb_event, &usart0_DmaDriverState); +} + +static int32_t USART0_DmaUninitialize(void) +{ + USART0_DeinitPins(); + return USART_DmaUninitialize(&usart0_DmaDriverState); +} + +static int32_t USART0_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart0_DmaDriverState); +} + +static int32_t USART0_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart0_DmaDriverState); +} + +static int32_t USART0_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart0_DmaDriverState); +} + +static int32_t USART0_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart0_DmaDriverState); +} + +static uint32_t USART0_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart0_DmaDriverState); +} + +static uint32_t USART0_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart0_DmaDriverState); +} + +static int32_t USART0_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart0_DmaDriverState); +} + +static ARM_USART_STATUS USART0_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart0_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART0_Handle; +#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1) +static uint8_t usart0_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart0_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart0_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart0_NonBlockingDriverState = { +#endif + &usart0_Resource, + &USART0_Handle, +}; + +static int32_t USART0_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART0_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart0_NonBlockingDriverState); +} + +static int32_t USART0_NonBlockingUninitialize(void) +{ + USART0_DeinitPins(); + return USART_NonBlockingUninitialize(&usart0_NonBlockingDriverState); +} + +static int32_t USART0_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart0_NonBlockingDriverState); +#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart0_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart0_NonBlockingDriverState.resource->base, + usart0_NonBlockingDriverState.handle, usart0_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART0_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart0_NonBlockingDriverState); +} + +static int32_t USART0_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart0_NonBlockingDriverState); +} + +static int32_t USART0_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart0_NonBlockingDriverState); +} + +static uint32_t USART0_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart0_NonBlockingDriverState); +} + +static uint32_t USART0_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart0_NonBlockingDriverState); +} + +static int32_t USART0_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart0_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart0_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART0_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart0_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART0 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART0_DMA_EN + USART0_DmaInitialize, USART0_DmaUninitialize, USART0_DmaPowerControl, USART0_DmaSend, USART0_DmaReceive, + USART0_DmaTransfer, USART0_DmaGetTxCount, USART0_DmaGetRxCount, USART0_DmaControl, USART0_DmaGetStatus, +#else + USART0_NonBlockingInitialize, + USART0_NonBlockingUninitialize, + USART0_NonBlockingPowerControl, + USART0_NonBlockingSend, + USART0_NonBlockingReceive, + USART0_NonBlockingTransfer, + USART0_NonBlockingGetTxCount, + USART0_NonBlockingGetRxCount, + USART0_NonBlockingControl, + USART0_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart0 */ + +#if defined(USART1) && RTE_USART1 + +/* User needs to provide the implementation for USART1_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART1_GetFreq(void); +extern void USART1_InitPins(void); +extern void USART1_DeinitPins(void); + +cmsis_usart_resource_t usart1_Resource = {USART1, USART1_GetFreq}; + +#if RTE_USART1_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart1_DmaResource = { + RTE_USART1_DMA_TX_DMA_BASE, + RTE_USART1_DMA_TX_CH, + RTE_USART1_DMA_RX_DMA_BASE, + RTE_USART1_DMA_RX_CH, +}; + +usart_dma_handle_t USART1_DmaHandle; +dma_handle_t USART1_DmaRxHandle; +dma_handle_t USART1_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart1_dma_driver_state") +cmsis_usart_dma_driver_state_t usart1_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart1_DmaDriverState = { +#endif + &usart1_Resource, &usart1_DmaResource, &USART1_DmaHandle, &USART1_DmaRxHandle, &USART1_DmaTxHandle, +}; + +static int32_t USART1_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART1_InitPins(); + return USART_DmaInitialize(cb_event, &usart1_DmaDriverState); +} + +static int32_t USART1_DmaUninitialize(void) +{ + USART1_DeinitPins(); + return USART_DmaUninitialize(&usart1_DmaDriverState); +} + +static int32_t USART1_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart1_DmaDriverState); +} + +static int32_t USART1_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart1_DmaDriverState); +} + +static int32_t USART1_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart1_DmaDriverState); +} + +static int32_t USART1_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart1_DmaDriverState); +} + +static uint32_t USART1_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart1_DmaDriverState); +} + +static uint32_t USART1_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart1_DmaDriverState); +} + +static int32_t USART1_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart1_DmaDriverState); +} + +static ARM_USART_STATUS USART1_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart1_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART1_Handle; +#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) +static uint8_t usart1_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart1_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart1_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart1_NonBlockingDriverState = { +#endif + &usart1_Resource, + &USART1_Handle, +}; + +static int32_t USART1_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART1_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart1_NonBlockingDriverState); +} + +static int32_t USART1_NonBlockingUninitialize(void) +{ + USART1_DeinitPins(); + return USART_NonBlockingUninitialize(&usart1_NonBlockingDriverState); +} + +static int32_t USART1_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart1_NonBlockingDriverState); +#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart1_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart1_NonBlockingDriverState.resource->base, + usart1_NonBlockingDriverState.handle, usart1_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART1_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart1_NonBlockingDriverState); +} + +static int32_t USART1_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart1_NonBlockingDriverState); +} + +static int32_t USART1_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart1_NonBlockingDriverState); +} + +static uint32_t USART1_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart1_NonBlockingDriverState); +} + +static uint32_t USART1_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart1_NonBlockingDriverState); +} + +static int32_t USART1_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart1_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart1_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART1_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart1_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART1 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART1_DMA_EN + USART1_DmaInitialize, USART1_DmaUninitialize, USART1_DmaPowerControl, USART1_DmaSend, USART1_DmaReceive, + USART1_DmaTransfer, USART1_DmaGetTxCount, USART1_DmaGetRxCount, USART1_DmaControl, USART1_DmaGetStatus, +#else + USART1_NonBlockingInitialize, + USART1_NonBlockingUninitialize, + USART1_NonBlockingPowerControl, + USART1_NonBlockingSend, + USART1_NonBlockingReceive, + USART1_NonBlockingTransfer, + USART1_NonBlockingGetTxCount, + USART1_NonBlockingGetRxCount, + USART1_NonBlockingControl, + USART1_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart1 */ + +#if defined(USART2) && RTE_USART2 + +/* User needs to provide the implementation for USART2_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART2_GetFreq(void); +extern void USART2_InitPins(void); +extern void USART2_DeinitPins(void); + +cmsis_usart_resource_t usart2_Resource = {USART2, USART2_GetFreq}; + +/* usart2 Driver Control Block */ + +#if RTE_USART2_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart2_DmaResource = { + RTE_USART2_DMA_TX_DMA_BASE, + RTE_USART2_DMA_TX_CH, + RTE_USART2_DMA_RX_DMA_BASE, + RTE_USART2_DMA_RX_CH, +}; + +usart_dma_handle_t USART2_DmaHandle; +dma_handle_t USART2_DmaRxHandle; +dma_handle_t USART2_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart2_dma_driver_state") +cmsis_usart_dma_driver_state_t usart2_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart2_DmaDriverState = { +#endif + &usart2_Resource, &usart2_DmaResource, &USART2_DmaHandle, &USART2_DmaRxHandle, &USART2_DmaTxHandle, +}; + +static int32_t USART2_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART2_InitPins(); + return USART_DmaInitialize(cb_event, &usart2_DmaDriverState); +} + +static int32_t USART2_DmaUninitialize(void) +{ + USART2_DeinitPins(); + return USART_DmaUninitialize(&usart2_DmaDriverState); +} + +static int32_t USART2_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart2_DmaDriverState); +} + +static int32_t USART2_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart2_DmaDriverState); +} + +static int32_t USART2_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart2_DmaDriverState); +} + +static int32_t USART2_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart2_DmaDriverState); +} + +static uint32_t USART2_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart2_DmaDriverState); +} + +static uint32_t USART2_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart2_DmaDriverState); +} + +static int32_t USART2_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart2_DmaDriverState); +} + +static ARM_USART_STATUS USART2_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart2_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART2_Handle; +#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) +static uint8_t usart2_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart2_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart2_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart2_NonBlockingDriverState = { +#endif + &usart2_Resource, + &USART2_Handle, +}; + +static int32_t USART2_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART2_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart2_NonBlockingDriverState); +} + +static int32_t USART2_NonBlockingUninitialize(void) +{ + USART2_DeinitPins(); + return USART_NonBlockingUninitialize(&usart2_NonBlockingDriverState); +} + +static int32_t USART2_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart2_NonBlockingDriverState); +#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart2_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart2_NonBlockingDriverState.resource->base, + usart2_NonBlockingDriverState.handle, usart2_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART2_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart2_NonBlockingDriverState); +} + +static int32_t USART2_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart2_NonBlockingDriverState); +} + +static int32_t USART2_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart2_NonBlockingDriverState); +} + +static uint32_t USART2_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart2_NonBlockingDriverState); +} + +static uint32_t USART2_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart2_NonBlockingDriverState); +} + +static int32_t USART2_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart2_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart2_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART2_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart2_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART2 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART2_DMA_EN + USART2_DmaInitialize, USART2_DmaUninitialize, USART2_DmaPowerControl, USART2_DmaSend, USART2_DmaReceive, + USART2_DmaTransfer, USART2_DmaGetTxCount, USART2_DmaGetRxCount, USART2_DmaControl, USART2_DmaGetStatus, +#else + USART2_NonBlockingInitialize, + USART2_NonBlockingUninitialize, + USART2_NonBlockingPowerControl, + USART2_NonBlockingSend, + USART2_NonBlockingReceive, + USART2_NonBlockingTransfer, + USART2_NonBlockingGetTxCount, + USART2_NonBlockingGetRxCount, + USART2_NonBlockingControl, + USART2_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart2 */ + +#if defined(USART3) && RTE_USART3 + +/* User needs to provide the implementation for USART3_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART3_GetFreq(void); +extern void USART3_InitPins(void); +extern void USART3_DeinitPins(void); + +cmsis_usart_resource_t usart3_Resource = {USART3, USART3_GetFreq}; + +/* usart3 Driver Control Block */ +#if RTE_USART3_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart3_DmaResource = { + RTE_USART3_DMA_TX_DMA_BASE, + RTE_USART3_DMA_TX_CH, + RTE_USART3_DMA_RX_DMA_BASE, + RTE_USART3_DMA_RX_CH, +}; + +usart_dma_handle_t USART3_DmaHandle; +dma_handle_t USART3_DmaRxHandle; +dma_handle_t USART3_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart3_dma_driver_state") +cmsis_usart_dma_driver_state_t usart3_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart3_DmaDriverState = { +#endif + &usart3_Resource, &usart3_DmaResource, &USART3_DmaHandle, &USART3_DmaRxHandle, &USART3_DmaTxHandle, +}; + +static int32_t USART3_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART3_InitPins(); + return USART_DmaInitialize(cb_event, &usart3_DmaDriverState); +} + +static int32_t USART3_DmaUninitialize(void) +{ + USART3_DeinitPins(); + return USART_DmaUninitialize(&usart3_DmaDriverState); +} + +static int32_t USART3_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart3_DmaDriverState); +} + +static int32_t USART3_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart3_DmaDriverState); +} + +static int32_t USART3_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart3_DmaDriverState); +} + +static int32_t USART3_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart3_DmaDriverState); +} + +static uint32_t USART3_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart3_DmaDriverState); +} + +static uint32_t USART3_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart3_DmaDriverState); +} + +static int32_t USART3_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart3_DmaDriverState); +} + +static ARM_USART_STATUS USART3_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart3_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART3_Handle; +#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) +static uint8_t usart3_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart3_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart3_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart3_NonBlockingDriverState = { +#endif + &usart3_Resource, + &USART3_Handle, +}; + +static int32_t USART3_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART3_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart3_NonBlockingDriverState); +} + +static int32_t USART3_NonBlockingUninitialize(void) +{ + USART3_DeinitPins(); + return USART_NonBlockingUninitialize(&usart3_NonBlockingDriverState); +} + +static int32_t USART3_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart3_NonBlockingDriverState); +#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart3_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart3_NonBlockingDriverState.resource->base, + usart3_NonBlockingDriverState.handle, usart3_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART3_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart3_NonBlockingDriverState); +} + +static int32_t USART3_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart3_NonBlockingDriverState); +} + +static int32_t USART3_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart3_NonBlockingDriverState); +} + +static uint32_t USART3_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart3_NonBlockingDriverState); +} + +static uint32_t USART3_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart3_NonBlockingDriverState); +} + +static int32_t USART3_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart3_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart3_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART3_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart3_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART3 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART3_DMA_EN + USART3_DmaInitialize, USART3_DmaUninitialize, USART3_DmaPowerControl, USART3_DmaSend, USART3_DmaReceive, + USART3_DmaTransfer, USART3_DmaGetTxCount, USART3_DmaGetRxCount, USART3_DmaControl, USART3_DmaGetStatus, +#else + USART3_NonBlockingInitialize, + USART3_NonBlockingUninitialize, + USART3_NonBlockingPowerControl, + USART3_NonBlockingSend, + USART3_NonBlockingReceive, + USART3_NonBlockingTransfer, + USART3_NonBlockingGetTxCount, + USART3_NonBlockingGetRxCount, + USART3_NonBlockingControl, + USART3_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart3 */ + +#if defined(USART4) && RTE_USART4 + +/* User needs to provide the implementation for USART4_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART4_GetFreq(void); +extern void USART4_InitPins(void); +extern void USART4_DeinitPins(void); + +cmsis_usart_resource_t usart4_Resource = {USART4, USART4_GetFreq}; + +#if RTE_USART4_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart4_DmaResource = { + RTE_USART4_DMA_TX_DMA_BASE, + RTE_USART4_DMA_TX_CH, + RTE_USART4_DMA_RX_DMA_BASE, + RTE_USART4_DMA_RX_CH, +}; + +usart_dma_handle_t USART4_DmaHandle; +dma_handle_t USART4_DmaRxHandle; +dma_handle_t USART4_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart4_dma_driver_state") +cmsis_usart_dma_driver_state_t usart4_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart4_DmaDriverState = { +#endif + &usart4_Resource, &usart4_DmaResource, &USART4_DmaHandle, &USART4_DmaRxHandle, &USART4_DmaTxHandle, +}; + +static int32_t USART4_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART4_InitPins(); + return USART_DmaInitialize(cb_event, &usart4_DmaDriverState); +} + +static int32_t USART4_DmaUninitialize(void) +{ + USART4_DeinitPins(); + return USART_DmaUninitialize(&usart4_DmaDriverState); +} + +static int32_t USART4_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart4_DmaDriverState); +} + +static int32_t USART4_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart4_DmaDriverState); +} + +static int32_t USART4_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart4_DmaDriverState); +} + +static int32_t USART4_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart4_DmaDriverState); +} + +static uint32_t USART4_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart4_DmaDriverState); +} + +static uint32_t USART4_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart4_DmaDriverState); +} + +static int32_t USART4_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart4_DmaDriverState); +} + +static ARM_USART_STATUS USART4_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart4_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART4_Handle; +#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) +static uint8_t usart4_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart4_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart4_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart4_NonBlockingDriverState = { +#endif + &usart4_Resource, + &USART4_Handle, +}; + +static int32_t USART4_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART4_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart4_NonBlockingDriverState); +} + +static int32_t USART4_NonBlockingUninitialize(void) +{ + USART4_DeinitPins(); + return USART_NonBlockingUninitialize(&usart4_NonBlockingDriverState); +} + +static int32_t USART4_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart4_NonBlockingDriverState); +#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart4_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart4_NonBlockingDriverState.resource->base, + usart4_NonBlockingDriverState.handle, usart4_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART4_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart4_NonBlockingDriverState); +} + +static int32_t USART4_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart4_NonBlockingDriverState); +} + +static int32_t USART4_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart4_NonBlockingDriverState); +} + +static uint32_t USART4_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart4_NonBlockingDriverState); +} + +static uint32_t USART4_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart4_NonBlockingDriverState); +} + +static int32_t USART4_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart4_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart4_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART4_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart4_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART4 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART4_DMA_EN + USART4_DmaInitialize, USART4_DmaUninitialize, USART4_DmaPowerControl, USART4_DmaSend, USART4_DmaReceive, + USART4_DmaTransfer, USART4_DmaGetTxCount, USART4_DmaGetRxCount, USART4_DmaControl, USART4_DmaGetStatus, +#else + USART4_NonBlockingInitialize, + USART4_NonBlockingUninitialize, + USART4_NonBlockingPowerControl, + USART4_NonBlockingSend, + USART4_NonBlockingReceive, + USART4_NonBlockingTransfer, + USART4_NonBlockingGetTxCount, + USART4_NonBlockingGetRxCount, + USART4_NonBlockingControl, + USART4_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart4 */ + +#if defined(USART5) && RTE_USART5 + +/* User needs to provide the implementation for USART5_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART5_GetFreq(void); +extern void USART5_InitPins(void); +extern void USART5_DeinitPins(void); + +cmsis_usart_resource_t usart5_Resource = {USART5, USART5_GetFreq}; + +#if RTE_USART5_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart5_DmaResource = { + RTE_USART5_DMA_TX_DMA_BASE, + RTE_USART5_DMA_TX_CH, + RTE_USART5_DMA_RX_DMA_BASE, + RTE_USART5_DMA_RX_CH, +}; + +usart_dma_handle_t USART5_DmaHandle; +dma_handle_t USART5_DmaRxHandle; +dma_handle_t USART5_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart5_dma_driver_state") +cmsis_usart_dma_driver_state_t usart5_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart5_DmaDriverState = { +#endif + &usart5_Resource, &usart5_DmaResource, &USART5_DmaHandle, &USART5_DmaRxHandle, &USART5_DmaTxHandle, +}; + +static int32_t USART5_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART5_InitPins(); + return USART_DmaInitialize(cb_event, &usart5_DmaDriverState); +} + +static int32_t USART5_DmaUninitialize(void) +{ + USART5_DeinitPins(); + return USART_DmaUninitialize(&usart5_DmaDriverState); +} + +static int32_t USART5_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart5_DmaDriverState); +} + +static int32_t USART5_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart5_DmaDriverState); +} + +static int32_t USART5_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart5_DmaDriverState); +} + +static int32_t USART5_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart5_DmaDriverState); +} + +static uint32_t USART5_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart5_DmaDriverState); +} + +static uint32_t USART5_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart5_DmaDriverState); +} + +static int32_t USART5_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart5_DmaDriverState); +} + +static ARM_USART_STATUS USART5_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart5_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART5_Handle; +#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1) +static uint8_t usart5_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart5_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart5_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart5_NonBlockingDriverState = { +#endif + &usart5_Resource, + &USART5_Handle, +}; + +static int32_t USART5_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART5_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart5_NonBlockingDriverState); +} + +static int32_t USART5_NonBlockingUninitialize(void) +{ + USART5_DeinitPins(); + return USART_NonBlockingUninitialize(&usart5_NonBlockingDriverState); +} + +static int32_t USART5_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart5_NonBlockingDriverState); +#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart5_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart5_NonBlockingDriverState.resource->base, + usart5_NonBlockingDriverState.handle, usart5_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART5_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart5_NonBlockingDriverState); +} + +static int32_t USART5_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart5_NonBlockingDriverState); +} + +static int32_t USART5_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart5_NonBlockingDriverState); +} + +static uint32_t USART5_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart5_NonBlockingDriverState); +} + +static uint32_t USART5_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart5_NonBlockingDriverState); +} + +static int32_t USART5_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart5_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart5_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART5_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart5_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART5 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART5_DMA_EN + USART5_DmaInitialize, USART5_DmaUninitialize, USART5_DmaPowerControl, USART5_DmaSend, USART5_DmaReceive, + USART5_DmaTransfer, USART5_DmaGetTxCount, USART5_DmaGetRxCount, USART5_DmaControl, USART5_DmaGetStatus, +#else + USART5_NonBlockingInitialize, + USART5_NonBlockingUninitialize, + USART5_NonBlockingPowerControl, + USART5_NonBlockingSend, + USART5_NonBlockingReceive, + USART5_NonBlockingTransfer, + USART5_NonBlockingGetTxCount, + USART5_NonBlockingGetRxCount, + USART5_NonBlockingControl, + USART5_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart5 */ + +#if defined(USART6) && RTE_USART6 + +/* User needs to provide the implementation for USART6_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART6_GetFreq(void); +extern void USART6_InitPins(void); +extern void USART6_DeinitPins(void); + +cmsis_usart_resource_t usart6_Resource = {USART6, USART6_GetFreq}; + +#if RTE_USART6_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart6_DmaResource = { + RTE_USART6_DMA_TX_DMA_BASE, + RTE_USART6_DMA_TX_CH, + RTE_USART6_DMA_RX_DMA_BASE, + RTE_USART6_DMA_RX_CH, +}; + +usart_dma_handle_t USART6_DmaHandle; +dma_handle_t USART6_DmaRxHandle; +dma_handle_t USART6_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart6_dma_driver_state") +cmsis_usart_dma_driver_state_t usart6_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart6_DmaDriverState = { +#endif + &usart6_Resource, &usart6_DmaResource, &USART6_DmaHandle, &USART6_DmaRxHandle, &USART6_DmaTxHandle, +}; + +static int32_t USART6_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART6_InitPins(); + return USART_DmaInitialize(cb_event, &usart6_DmaDriverState); +} + +static int32_t USART6_DmaUninitialize(void) +{ + USART6_DeinitPins(); + return USART_DmaUninitialize(&usart6_DmaDriverState); +} + +static int32_t USART6_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart6_DmaDriverState); +} + +static int32_t USART6_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart6_DmaDriverState); +} + +static int32_t USART6_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart6_DmaDriverState); +} + +static int32_t USART6_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart6_DmaDriverState); +} + +static uint32_t USART6_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart6_DmaDriverState); +} + +static uint32_t USART6_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart6_DmaDriverState); +} + +static int32_t USART6_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart6_DmaDriverState); +} + +static ARM_USART_STATUS USART6_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart6_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART6_Handle; +#if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1) +static uint8_t usart6_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart6_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart6_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart6_NonBlockingDriverState = { +#endif + &usart6_Resource, + &USART6_Handle, +}; + +static int32_t USART6_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART6_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart6_NonBlockingDriverState); +} + +static int32_t USART6_NonBlockingUninitialize(void) +{ + USART6_DeinitPins(); + return USART_NonBlockingUninitialize(&usart6_NonBlockingDriverState); +} + +static int32_t USART6_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart6_NonBlockingDriverState); +#if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart6_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart6_NonBlockingDriverState.resource->base, + usart6_NonBlockingDriverState.handle, usart6_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART6_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart6_NonBlockingDriverState); +} + +static int32_t USART6_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart6_NonBlockingDriverState); +} + +static int32_t USART6_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart6_NonBlockingDriverState); +} + +static uint32_t USART6_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart6_NonBlockingDriverState); +} + +static uint32_t USART6_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart6_NonBlockingDriverState); +} + +static int32_t USART6_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart6_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart6_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART6_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart6_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART6 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART6_DMA_EN + USART6_DmaInitialize, USART6_DmaUninitialize, USART6_DmaPowerControl, USART6_DmaSend, USART6_DmaReceive, + USART6_DmaTransfer, USART6_DmaGetTxCount, USART6_DmaGetRxCount, USART6_DmaControl, USART6_DmaGetStatus, +#else + USART6_NonBlockingInitialize, + USART6_NonBlockingUninitialize, + USART6_NonBlockingPowerControl, + USART6_NonBlockingSend, + USART6_NonBlockingReceive, + USART6_NonBlockingTransfer, + USART6_NonBlockingGetTxCount, + USART6_NonBlockingGetRxCount, + USART6_NonBlockingControl, + USART6_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart6 */ + +#if defined(USART7) && RTE_USART7 + +/* User needs to provide the implementation for USART7_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART7_GetFreq(void); +extern void USART7_InitPins(void); +extern void USART7_DeinitPins(void); + +cmsis_usart_resource_t usart7_Resource = {USART7, USART7_GetFreq}; + +#if RTE_USART7_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart7_DmaResource = { + RTE_USART7_DMA_TX_DMA_BASE, + RTE_USART7_DMA_TX_CH, + RTE_USART7_DMA_RX_DMA_BASE, + RTE_USART7_DMA_RX_CH, +}; + +usart_dma_handle_t USART7_DmaHandle; +dma_handle_t USART7_DmaRxHandle; +dma_handle_t USART7_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart7_dma_driver_state") +cmsis_usart_dma_driver_state_t usart7_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart7_DmaDriverState = { +#endif + &usart7_Resource, &usart7_DmaResource, &USART7_DmaHandle, &USART7_DmaRxHandle, &USART7_DmaTxHandle, +}; + +static int32_t USART7_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART7_InitPins(); + return USART_DmaInitialize(cb_event, &usart7_DmaDriverState); +} + +static int32_t USART7_DmaUninitialize(void) +{ + USART7_DeinitPins(); + return USART_DmaUninitialize(&usart7_DmaDriverState); +} + +static int32_t USART7_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart7_DmaDriverState); +} + +static int32_t USART7_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart7_DmaDriverState); +} + +static int32_t USART7_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart7_DmaDriverState); +} + +static int32_t USART7_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart7_DmaDriverState); +} + +static uint32_t USART7_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart7_DmaDriverState); +} + +static uint32_t USART7_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart7_DmaDriverState); +} + +static int32_t USART7_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart7_DmaDriverState); +} + +static ARM_USART_STATUS USART7_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart7_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART7_Handle; +#if defined(USART7_RX_BUFFER_ENABLE) && (USART7_RX_BUFFER_ENABLE == 1) +static uint8_t usart7_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart7_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart7_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart7_NonBlockingDriverState = { +#endif + &usart7_Resource, + &USART7_Handle, +}; + +static int32_t USART7_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART7_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart7_NonBlockingDriverState); +} + +static int32_t USART7_NonBlockingUninitialize(void) +{ + USART7_DeinitPins(); + return USART_NonBlockingUninitialize(&usart7_NonBlockingDriverState); +} + +static int32_t USART7_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart7_NonBlockingDriverState); +#if defined(USART7_RX_BUFFER_ENABLE) && (USART7_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart7_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart7_NonBlockingDriverState.resource->base, + usart7_NonBlockingDriverState.handle, usart7_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART7_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart7_NonBlockingDriverState); +} + +static int32_t USART7_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart7_NonBlockingDriverState); +} + +static int32_t USART7_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart7_NonBlockingDriverState); +} + +static uint32_t USART7_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart7_NonBlockingDriverState); +} + +static uint32_t USART7_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart7_NonBlockingDriverState); +} + +static int32_t USART7_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart7_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART7_RX_BUFFER_ENABLE) && (USART7_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart7_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART7_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart7_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART7 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART7_DMA_EN + USART7_DmaInitialize, USART7_DmaUninitialize, USART7_DmaPowerControl, USART7_DmaSend, USART7_DmaReceive, + USART7_DmaTransfer, USART7_DmaGetTxCount, USART7_DmaGetRxCount, USART7_DmaControl, USART7_DmaGetStatus, +#else + USART7_NonBlockingInitialize, + USART7_NonBlockingUninitialize, + USART7_NonBlockingPowerControl, + USART7_NonBlockingSend, + USART7_NonBlockingReceive, + USART7_NonBlockingTransfer, + USART7_NonBlockingGetTxCount, + USART7_NonBlockingGetRxCount, + USART7_NonBlockingControl, + USART7_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart7 */ + +#if defined(USART8) && RTE_USART8 + +/* User needs to provide the implementation for USART8_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART8_GetFreq(void); +extern void USART8_InitPins(void); +extern void USART8_DeinitPins(void); + +cmsis_usart_resource_t usart8_Resource = {USART8, USART8_GetFreq}; + +#if RTE_USART8_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart8_DmaResource = { + RTE_USART8_DMA_TX_DMA_BASE, + RTE_USART8_DMA_TX_CH, + RTE_USART8_DMA_RX_DMA_BASE, + RTE_USART8_DMA_RX_CH, +}; + +usart_dma_handle_t USART8_DmaHandle; +dma_handle_t USART8_DmaRxHandle; +dma_handle_t USART8_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart8_dma_driver_state") +cmsis_usart_dma_driver_state_t usart8_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart8_DmaDriverState = { +#endif + &usart8_Resource, &usart8_DmaResource, &USART8_DmaHandle, &USART8_DmaRxHandle, &USART8_DmaTxHandle, +}; + +static int32_t USART8_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART8_InitPins(); + return USART_DmaInitialize(cb_event, &usart8_DmaDriverState); +} + +static int32_t USART8_DmaUninitialize(void) +{ + USART8_DeinitPins(); + return USART_DmaUninitialize(&usart8_DmaDriverState); +} + +static int32_t USART8_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart8_DmaDriverState); +} + +static int32_t USART8_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart8_DmaDriverState); +} + +static int32_t USART8_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart8_DmaDriverState); +} + +static int32_t USART8_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart8_DmaDriverState); +} + +static uint32_t USART8_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart8_DmaDriverState); +} + +static uint32_t USART8_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart8_DmaDriverState); +} + +static int32_t USART8_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart8_DmaDriverState); +} + +static ARM_USART_STATUS USART8_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart8_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART8_Handle; +#if defined(USART8_RX_BUFFER_ENABLE) && (USART8_RX_BUFFER_ENABLE == 1) +static uint8_t usart8_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart8_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart8_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart8_NonBlockingDriverState = { +#endif + &usart8_Resource, + &USART8_Handle, +}; + +static int32_t USART8_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART8_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart8_NonBlockingDriverState); +} + +static int32_t USART8_NonBlockingUninitialize(void) +{ + USART8_DeinitPins(); + return USART_NonBlockingUninitialize(&usart8_NonBlockingDriverState); +} + +static int32_t USART8_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart8_NonBlockingDriverState); +#if defined(USART8_RX_BUFFER_ENABLE) && (USART8_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart8_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart8_NonBlockingDriverState.resource->base, + usart8_NonBlockingDriverState.handle, usart8_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + + return result; +} + +static int32_t USART8_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart8_NonBlockingDriverState); +} + +static int32_t USART8_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart8_NonBlockingDriverState); +} + +static int32_t USART8_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart8_NonBlockingDriverState); +} + +static uint32_t USART8_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart8_NonBlockingDriverState); +} + +static uint32_t USART8_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart8_NonBlockingDriverState); +} + +static int32_t USART8_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart8_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART8_RX_BUFFER_ENABLE) && (USART8_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart8_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART8_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart8_NonBlockingDriverState); +} + +#endif + +/* usart8 Driver Control Block */ +ARM_DRIVER_USART Driver_USART8 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART8_DMA_EN + USART8_DmaInitialize, USART8_DmaUninitialize, USART8_DmaPowerControl, USART8_DmaSend, USART8_DmaReceive, + USART8_DmaTransfer, USART8_DmaGetTxCount, USART8_DmaGetRxCount, USART8_DmaControl, USART8_DmaGetStatus, +#else + USART8_NonBlockingInitialize, + USART8_NonBlockingUninitialize, + USART8_NonBlockingPowerControl, + USART8_NonBlockingSend, + USART8_NonBlockingReceive, + USART8_NonBlockingTransfer, + USART8_NonBlockingGetTxCount, + USART8_NonBlockingGetRxCount, + USART8_NonBlockingControl, + USART8_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart8 */ + +#if defined(USART9) && RTE_USART9 + +/* User needs to provide the implementation for USART9_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART9_GetFreq(void); +extern void USART9_InitPins(void); +extern void USART9_DeinitPins(void); + +cmsis_usart_resource_t usart9_Resource = {USART9, USART9_GetFreq}; + +#if RTE_USART9_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart9_DmaResource = { + RTE_USART9_DMA_TX_DMA_BASE, + RTE_USART9_DMA_TX_CH, + RTE_USART9_DMA_RX_DMA_BASE, + RTE_USART9_DMA_RX_CH, +}; + +usart_dma_handle_t USART9_DmaHandle; +dma_handle_t USART9_DmaRxHandle; +dma_handle_t USART9_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart9_dma_driver_state") +cmsis_usart_dma_driver_state_t usart9_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart9_DmaDriverState = { +#endif + &usart9_Resource, &usart9_DmaResource, &USART9_DmaHandle, &USART9_DmaRxHandle, &USART9_DmaTxHandle, +}; + +static int32_t USART9_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART9_InitPins(); + return USART_DmaInitialize(cb_event, &usart9_DmaDriverState); +} + +static int32_t USART9_DmaUninitialize(void) +{ + USART9_DeinitPins(); + return USART_DmaUninitialize(&usart9_DmaDriverState); +} + +static int32_t USART9_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart9_DmaDriverState); +} + +static int32_t USART9_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart9_DmaDriverState); +} + +static int32_t USART9_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart9_DmaDriverState); +} + +static int32_t USART9_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart9_DmaDriverState); +} + +static uint32_t USART9_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart9_DmaDriverState); +} + +static uint32_t USART9_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart9_DmaDriverState); +} + +static int32_t USART9_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart9_DmaDriverState); +} + +static ARM_USART_STATUS USART9_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart9_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART9_Handle; +#if defined(USART9_RX_BUFFER_ENABLE) && (USART9_RX_BUFFER_ENABLE == 1) +static uint8_t usart9_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart9_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart9_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart9_NonBlockingDriverState = { +#endif + &usart9_Resource, + &USART9_Handle, +}; + +static int32_t USART9_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART9_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart9_NonBlockingDriverState); +} + +static int32_t USART9_NonBlockingUninitialize(void) +{ + USART9_DeinitPins(); + return USART_NonBlockingUninitialize(&usart9_NonBlockingDriverState); +} + +static int32_t USART9_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart9_NonBlockingDriverState); +#if defined(USART9_RX_BUFFER_ENABLE) && (USART9_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart9_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart9_NonBlockingDriverState.resource->base, + usart9_NonBlockingDriverState.handle, usart9_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + + return result; +} + +static int32_t USART9_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart9_NonBlockingDriverState); +} + +static int32_t USART9_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart9_NonBlockingDriverState); +} + +static int32_t USART9_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart9_NonBlockingDriverState); +} + +static uint32_t USART9_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart9_NonBlockingDriverState); +} + +static uint32_t USART9_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart9_NonBlockingDriverState); +} + +static int32_t USART9_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart9_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART9_RX_BUFFER_ENABLE) && (USART9_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart9_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART9_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart9_NonBlockingDriverState); +} + +#endif + +/* usart9 Driver Control Block */ +ARM_DRIVER_USART Driver_USART9 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART9_DMA_EN + USART9_DmaInitialize, USART9_DmaUninitialize, USART9_DmaPowerControl, USART9_DmaSend, USART9_DmaReceive, + USART9_DmaTransfer, USART9_DmaGetTxCount, USART9_DmaGetRxCount, USART9_DmaControl, USART9_DmaGetStatus, +#else + USART9_NonBlockingInitialize, + USART9_NonBlockingUninitialize, + USART9_NonBlockingPowerControl, + USART9_NonBlockingSend, + USART9_NonBlockingReceive, + USART9_NonBlockingTransfer, + USART9_NonBlockingGetTxCount, + USART9_NonBlockingGetRxCount, + USART9_NonBlockingControl, + USART9_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart9 */ + +#if defined(USART10) && RTE_USART10 + +/* User needs to provide the implementation for USART10_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART10_GetFreq(void); +extern void USART10_InitPins(void); +extern void USART10_DeinitPins(void); + +cmsis_usart_resource_t usart10_Resource = {USART10, USART10_GetFreq}; + +#if RTE_USART10_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart10_DmaResource = { + RTE_USART10_DMA_TX_DMA_BASE, + RTE_USART10_DMA_TX_CH, + RTE_USART10_DMA_RX_DMA_BASE, + RTE_USART10_DMA_RX_CH, +}; + +usart_dma_handle_t USART10_DmaHandle; +dma_handle_t USART10_DmaRxHandle; +dma_handle_t USART10_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart10_dma_driver_state") +cmsis_usart_dma_driver_state_t usart10_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart10_DmaDriverState = { +#endif + &usart10_Resource, &usart10_DmaResource, &USART10_DmaHandle, &USART10_DmaRxHandle, &USART10_DmaTxHandle, +}; + +static int32_t USART10_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART10_InitPins(); + return USART_DmaInitialize(cb_event, &usart10_DmaDriverState); +} + +static int32_t USART10_DmaUninitialize(void) +{ + USART10_DeinitPins(); + return USART_DmaUninitialize(&usart10_DmaDriverState); +} + +static int32_t USART10_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart10_DmaDriverState); +} + +static int32_t USART10_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart10_DmaDriverState); +} + +static int32_t USART10_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart10_DmaDriverState); +} + +static int32_t USART10_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart10_DmaDriverState); +} + +static uint32_t USART10_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart10_DmaDriverState); +} + +static uint32_t USART10_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart10_DmaDriverState); +} + +static int32_t USART10_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart10_DmaDriverState); +} + +static ARM_USART_STATUS USART10_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart10_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART10_Handle; +#if defined(USART10_RX_BUFFER_ENABLE) && (USART10_RX_BUFFER_ENABLE == 1) +static uint8_t usart10_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart10_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart10_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart10_NonBlockingDriverState = { +#endif + &usart10_Resource, + &USART10_Handle, +}; + +static int32_t USART10_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART10_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart10_NonBlockingDriverState); +} + +static int32_t USART10_NonBlockingUninitialize(void) +{ + USART10_DeinitPins(); + return USART_NonBlockingUninitialize(&usart10_NonBlockingDriverState); +} + +static int32_t USART10_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart10_NonBlockingDriverState); +#if defined(USART10_RX_BUFFER_ENABLE) && (USART10_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart10_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart10_NonBlockingDriverState.resource->base, + usart10_NonBlockingDriverState.handle, usart10_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART10_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart10_NonBlockingDriverState); +} + +static int32_t USART10_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart10_NonBlockingDriverState); +} + +static int32_t USART10_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart10_NonBlockingDriverState); +} + +static uint32_t USART10_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart10_NonBlockingDriverState); +} + +static uint32_t USART10_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart10_NonBlockingDriverState); +} + +static int32_t USART10_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart10_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART10_RX_BUFFER_ENABLE) && (USART10_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart10_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART10_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart10_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART10 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART10_DMA_EN + USART10_DmaInitialize, USART10_DmaUninitialize, USART10_DmaPowerControl, USART10_DmaSend, USART10_DmaReceive, + USART10_DmaTransfer, USART10_DmaGetTxCount, USART10_DmaGetRxCount, USART10_DmaControl, USART10_DmaGetStatus, +#else + USART10_NonBlockingInitialize, + USART10_NonBlockingUninitialize, + USART10_NonBlockingPowerControl, + USART10_NonBlockingSend, + USART10_NonBlockingReceive, + USART10_NonBlockingTransfer, + USART10_NonBlockingGetTxCount, + USART10_NonBlockingGetRxCount, + USART10_NonBlockingControl, + USART10_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart10 */ + +#if defined(USART11) && RTE_USART11 + +/* User needs to provide the implementation for USART11_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART11_GetFreq(void); +extern void USART11_InitPins(void); +extern void USART11_DeinitPins(void); + +cmsis_usart_resource_t usart11_Resource = {USART11, USART11_GetFreq}; + +#if RTE_USART11_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart11_DmaResource = { + RTE_USART11_DMA_TX_DMA_BASE, + RTE_USART11_DMA_TX_CH, + RTE_USART11_DMA_RX_DMA_BASE, + RTE_USART11_DMA_RX_CH, +}; + +usart_dma_handle_t USART11_DmaHandle; +dma_handle_t USART11_DmaRxHandle; +dma_handle_t USART11_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart11_dma_driver_state") +cmsis_usart_dma_driver_state_t usart11_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart11_DmaDriverState = { +#endif + &usart11_Resource, &usart11_DmaResource, &USART11_DmaHandle, &USART11_DmaRxHandle, &USART11_DmaTxHandle, +}; + +static int32_t USART11_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART11_InitPins(); + return USART_DmaInitialize(cb_event, &usart11_DmaDriverState); +} + +static int32_t USART11_DmaUninitialize(void) +{ + USART11_DeinitPins(); + return USART_DmaUninitialize(&usart11_DmaDriverState); +} + +static int32_t USART11_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart11_DmaDriverState); +} + +static int32_t USART11_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart11_DmaDriverState); +} + +static int32_t USART11_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart11_DmaDriverState); +} + +static int32_t USART11_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart11_DmaDriverState); +} + +static uint32_t USART11_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart11_DmaDriverState); +} + +static uint32_t USART11_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart11_DmaDriverState); +} + +static int32_t USART11_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart11_DmaDriverState); +} + +static ARM_USART_STATUS USART11_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart11_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART11_Handle; +#if defined(USART11_RX_BUFFER_ENABLE) && (USART11_RX_BUFFER_ENABLE == 1) +static uint8_t usart11_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart11_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart11_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart11_NonBlockingDriverState = { +#endif + &usart11_Resource, + &USART11_Handle, +}; + +static int32_t USART11_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART11_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart11_NonBlockingDriverState); +} + +static int32_t USART11_NonBlockingUninitialize(void) +{ + USART11_DeinitPins(); + return USART_NonBlockingUninitialize(&usart11_NonBlockingDriverState); +} + +static int32_t USART11_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart11_NonBlockingDriverState); +#if defined(USART11_RX_BUFFER_ENABLE) && (USART11_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart11_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart11_NonBlockingDriverState.resource->base, + usart11_NonBlockingDriverState.handle, usart11_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART11_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart11_NonBlockingDriverState); +} + +static int32_t USART11_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart11_NonBlockingDriverState); +} + +static int32_t USART11_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart11_NonBlockingDriverState); +} + +static uint32_t USART11_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart11_NonBlockingDriverState); +} + +static uint32_t USART11_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart11_NonBlockingDriverState); +} + +static int32_t USART11_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart11_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART11_RX_BUFFER_ENABLE) && (USART11_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart11_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART11_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart11_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART11 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART11_DMA_EN + USART11_DmaInitialize, USART11_DmaUninitialize, USART11_DmaPowerControl, USART11_DmaSend, USART11_DmaReceive, + USART11_DmaTransfer, USART11_DmaGetTxCount, USART11_DmaGetRxCount, USART11_DmaControl, USART11_DmaGetStatus, +#else + USART11_NonBlockingInitialize, + USART11_NonBlockingUninitialize, + USART11_NonBlockingPowerControl, + USART11_NonBlockingSend, + USART11_NonBlockingReceive, + USART11_NonBlockingTransfer, + USART11_NonBlockingGetTxCount, + USART11_NonBlockingGetRxCount, + USART11_NonBlockingControl, + USART11_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart11 */ + +#if defined(USART12) && RTE_USART12 + +/* User needs to provide the implementation for USART12_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART12_GetFreq(void); +extern void USART12_InitPins(void); +extern void USART12_DeinitPins(void); + +cmsis_usart_resource_t usart12_Resource = {USART12, USART12_GetFreq}; + +#if RTE_USART12_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart12_DmaResource = { + RTE_USART12_DMA_TX_DMA_BASE, + RTE_USART12_DMA_TX_CH, + RTE_USART12_DMA_RX_DMA_BASE, + RTE_USART12_DMA_RX_CH, +}; + +usart_dma_handle_t USART12_DmaHandle; +dma_handle_t USART12_DmaRxHandle; +dma_handle_t USART12_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart12_dma_driver_state") +cmsis_usart_dma_driver_state_t usart12_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart12_DmaDriverState = { +#endif + &usart12_Resource, &usart12_DmaResource, &USART12_DmaHandle, &USART12_DmaRxHandle, &USART12_DmaTxHandle, +}; + +static int32_t USART12_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART12_InitPins(); + return USART_DmaInitialize(cb_event, &usart12_DmaDriverState); +} + +static int32_t USART12_DmaUninitialize(void) +{ + USART12_DeinitPins(); + return USART_DmaUninitialize(&usart12_DmaDriverState); +} + +static int32_t USART12_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart12_DmaDriverState); +} + +static int32_t USART12_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart12_DmaDriverState); +} + +static int32_t USART12_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart12_DmaDriverState); +} + +static int32_t USART12_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart12_DmaDriverState); +} + +static uint32_t USART12_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart12_DmaDriverState); +} + +static uint32_t USART12_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart12_DmaDriverState); +} + +static int32_t USART12_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart12_DmaDriverState); +} + +static ARM_USART_STATUS USART12_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart12_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART12_Handle; +#if defined(USART12_RX_BUFFER_ENABLE) && (USART12_RX_BUFFER_ENABLE == 1) +static uint8_t usart12_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart12_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart12_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart12_NonBlockingDriverState = { +#endif + &usart12_Resource, + &USART12_Handle, +}; + +static int32_t USART12_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART12_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart12_NonBlockingDriverState); +} + +static int32_t USART12_NonBlockingUninitialize(void) +{ + USART12_DeinitPins(); + return USART_NonBlockingUninitialize(&usart12_NonBlockingDriverState); +} + +static int32_t USART12_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart12_NonBlockingDriverState); +#if defined(USART12_RX_BUFFER_ENABLE) && (USART12_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart12_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart12_NonBlockingDriverState.resource->base, + usart12_NonBlockingDriverState.handle, usart12_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART12_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart12_NonBlockingDriverState); +} + +static int32_t USART12_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart12_NonBlockingDriverState); +} + +static int32_t USART12_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart12_NonBlockingDriverState); +} + +static uint32_t USART12_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart12_NonBlockingDriverState); +} + +static uint32_t USART12_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart12_NonBlockingDriverState); +} + +static int32_t USART12_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart12_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART12_RX_BUFFER_ENABLE) && (USART12_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart12_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART12_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart12_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART12 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART12_DMA_EN + USART12_DmaInitialize, USART12_DmaUninitialize, USART12_DmaPowerControl, USART12_DmaSend, USART12_DmaReceive, + USART12_DmaTransfer, USART12_DmaGetTxCount, USART12_DmaGetRxCount, USART12_DmaControl, USART12_DmaGetStatus, +#else + USART12_NonBlockingInitialize, + USART12_NonBlockingUninitialize, + USART12_NonBlockingPowerControl, + USART12_NonBlockingSend, + USART12_NonBlockingReceive, + USART12_NonBlockingTransfer, + USART12_NonBlockingGetTxCount, + USART12_NonBlockingGetRxCount, + USART12_NonBlockingControl, + USART12_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart12 */ + +#if defined(USART13) && RTE_USART13 + +/* User needs to provide the implementation for USART13_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART13_GetFreq(void); +extern void USART13_InitPins(void); +extern void USART13_DeinitPins(void); + +cmsis_usart_resource_t usart13_Resource = {USART13, USART13_GetFreq}; + +#if RTE_USART13_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart13_DmaResource = { + RTE_USART13_DMA_TX_DMA_BASE, + RTE_USART13_DMA_TX_CH, + RTE_USART13_DMA_RX_DMA_BASE, + RTE_USART13_DMA_RX_CH, +}; + +usart_dma_handle_t USART13_DmaHandle; +dma_handle_t USART13_DmaRxHandle; +dma_handle_t USART13_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart13_dma_driver_state") +cmsis_usart_dma_driver_state_t usart13_DmaDriverState = { +#else +cmsis_usart_dma_driver_state_t usart13_DmaDriverState = { +#endif + &usart13_Resource, &usart13_DmaResource, &USART13_DmaHandle, &USART13_DmaRxHandle, &USART13_DmaTxHandle, +}; + +static int32_t USART13_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART13_InitPins(); + return USART_DmaInitialize(cb_event, &usart13_DmaDriverState); +} + +static int32_t USART13_DmaUninitialize(void) +{ + USART13_DeinitPins(); + return USART_DmaUninitialize(&usart13_DmaDriverState); +} + +static int32_t USART13_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart13_DmaDriverState); +} + +static int32_t USART13_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart13_DmaDriverState); +} + +static int32_t USART13_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart13_DmaDriverState); +} + +static int32_t USART13_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart13_DmaDriverState); +} + +static uint32_t USART13_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart13_DmaDriverState); +} + +static uint32_t USART13_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart13_DmaDriverState); +} + +static int32_t USART13_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart13_DmaDriverState); +} + +static ARM_USART_STATUS USART13_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart13_DmaDriverState); +} + +#endif + +#else + +usart_handle_t USART13_Handle; +#if defined(USART13_RX_BUFFER_ENABLE) && (USART13_RX_BUFFER_ENABLE == 1) +static uint8_t usart13_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart13_non_blocking_driver_state") +cmsis_usart_non_blocking_driver_state_t usart13_NonBlockingDriverState = { +#else +cmsis_usart_non_blocking_driver_state_t usart13_NonBlockingDriverState = { +#endif + &usart13_Resource, + &USART13_Handle, +}; + +static int32_t USART13_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ + USART13_InitPins(); + return USART_NonBlockingInitialize(cb_event, &usart13_NonBlockingDriverState); +} + +static int32_t USART13_NonBlockingUninitialize(void) +{ + USART13_DeinitPins(); + return USART_NonBlockingUninitialize(&usart13_NonBlockingDriverState); +} + +static int32_t USART13_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart13_NonBlockingDriverState); +#if defined(USART13_RX_BUFFER_ENABLE) && (USART13_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart13_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart13_NonBlockingDriverState.resource->base, + usart13_NonBlockingDriverState.handle, usart13_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART13_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart13_NonBlockingDriverState); +} + +static int32_t USART13_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart13_NonBlockingDriverState); +} + +static int32_t USART13_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart13_NonBlockingDriverState); +} + +static uint32_t USART13_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart13_NonBlockingDriverState); +} + +static uint32_t USART13_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart13_NonBlockingDriverState); +} + +static int32_t USART13_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart13_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART13_RX_BUFFER_ENABLE) && (USART13_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart13_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART13_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart13_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART13 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART13_DMA_EN + USART13_DmaInitialize, USART13_DmaUninitialize, USART13_DmaPowerControl, USART13_DmaSend, USART13_DmaReceive, + USART13_DmaTransfer, USART13_DmaGetTxCount, USART13_DmaGetRxCount, USART13_DmaControl, USART13_DmaGetStatus, +#else + USART13_NonBlockingInitialize, + USART13_NonBlockingUninitialize, + USART13_NonBlockingPowerControl, + USART13_NonBlockingSend, + USART13_NonBlockingReceive, + USART13_NonBlockingTransfer, + USART13_NonBlockingGetTxCount, + USART13_NonBlockingGetRxCount, + USART13_NonBlockingControl, + USART13_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart13 */ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart_cmsis.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart_cmsis.h new file mode 100644 index 000000000..7638a1575 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart_cmsis.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2017 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _FSL_USART_CMSIS_H_ +#define _FSL_USART_CMSIS_H_ + +#include "fsl_common.h" +#include "Driver_USART.h" +#include "RTE_Device.h" +#include "fsl_usart.h" +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) +#include "fsl_usart_dma.h" +#endif + +#if defined(USART0) +extern ARM_DRIVER_USART Driver_USART0; +#endif /* USART0 */ + +#if defined(USART1) +extern ARM_DRIVER_USART Driver_USART1; +#endif /* USART1 */ + +#if defined(USART2) +extern ARM_DRIVER_USART Driver_USART2; +#endif /* USART2 */ + +#if defined(USART3) +extern ARM_DRIVER_USART Driver_USART3; +#endif /* USART3 */ + +#if defined(USART4) +extern ARM_DRIVER_USART Driver_USART4; +#endif /* USART4 */ + +#if defined(USART5) +extern ARM_DRIVER_USART Driver_USART5; +#endif /* USART5 */ + +#if defined(USART6) +extern ARM_DRIVER_USART Driver_USART6; +#endif /* USART6 */ + +#if defined(USART7) +extern ARM_DRIVER_USART Driver_USART7; +#endif /* USART7 */ + +#if defined(USART8) +extern ARM_DRIVER_USART Driver_USART8; +#endif /* USART8 */ + +#if defined(USART9) +extern ARM_DRIVER_USART Driver_USART9; +#endif /* USART9 */ + +#if defined(USART10) +extern ARM_DRIVER_USART Driver_USART10; +#endif /* USART10 */ + +#if defined(USART11) +extern ARM_DRIVER_USART Driver_USART11; +#endif /* USART11 */ + +#if defined(USART12) +extern ARM_DRIVER_USART Driver_USART12; +#endif /* USART12 */ + +#if defined(USART13) +extern ARM_DRIVER_USART Driver_USART13; +#endif /* USART13 */ + +/* USART Driver state flags */ +#define USART_FLAG_UNINIT (0) +#define USART_FLAG_INIT (1 << 0) +#define USART_FLAG_POWER (1 << 1) +#define USART_FLAG_CONFIGURED (1 << 2) + +#endif /* _FSL_USART_CMSIS_H_ */ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart_dma.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart_dma.h new file mode 100644 index 000000000..7edb4871c --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart_dma.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_USART_DMA_H_ +#define _FSL_USART_DMA_H_ + +#include "fsl_common.h" +#include "fsl_dma.h" +#include "fsl_usart.h" + +/*! + * @addtogroup usart_dma_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief USART dma driver version 2.2.0. */ +#define FSL_USART_DMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*@}*/ + +/* Forward declaration of the handle typedef. */ +typedef struct _usart_dma_handle usart_dma_handle_t; + +/*! @brief UART transfer callback function. */ +typedef void (*usart_dma_transfer_callback_t)(USART_Type *base, + usart_dma_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief UART DMA handle + */ +struct _usart_dma_handle +{ + USART_Type *base; /*!< UART peripheral base address. */ + + usart_dma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + + dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */ + dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name DMA transactional + * @{ + */ + +/*! + * @brief Initializes the USART handle which is used in transactional functions. + * @param base USART peripheral base address. + * @param handle Pointer to usart_dma_handle_t structure. + * @param callback Callback function. + * @param userData User data. + * @param txDmaHandle User-requested DMA handle for TX DMA transfer. + * @param rxDmaHandle User-requested DMA handle for RX DMA transfer. + */ +status_t USART_TransferCreateHandleDMA(USART_Type *base, + usart_dma_handle_t *handle, + usart_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle); + +/*! + * @brief Sends data using DMA. + * + * This function sends data using DMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART DMA transfer structure. See #usart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_USART_TxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); + +/*! + * @brief Receives data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base USART peripheral base address. + * @param handle Pointer to usart_dma_handle_t structure. + * @param xfer USART DMA transfer structure. See #usart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_USART_RxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data using DMA. + * + * This function aborts send data using DMA. + * + * @param base USART peripheral base address + * @param handle Pointer to usart_dma_handle_t structure + */ +void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle); + +/*! + * @brief Aborts the received data using DMA. + * + * This function aborts the received data using DMA. + * + * @param base USART peripheral base address + * @param handle Pointer to usart_dma_handle_t structure + */ +void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_USART_DMA_H_ */ diff --git a/source/hic_hal/nxp/lpc55xx/RTE_Device.h b/source/hic_hal/nxp/lpc55xx/RTE_Device.h index 9a06e04ea..1c330db9d 100644 --- a/source/hic_hal/nxp/lpc55xx/RTE_Device.h +++ b/source/hic_hal/nxp/lpc55xx/RTE_Device.h @@ -1,32 +1,197 @@ -/* ----------------------------------------------------------------------------- - * Copyright (C) 2013 ARM Limited. All rights reserved. +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. * - * $Date: 27. June 2013 - * $Revision: V1.00 - * - * Project: RTE Device Configuration for NXP Kinetis K20 - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + * SPDX-License-Identifier: BSD-3-Clause + */ #ifndef __RTE_DEVICE_H #define __RTE_DEVICE_H - -#define RTE_USART1 1 +/* UART Select, UART0-UART7. */ +/* User needs to provide the implementation for XXX_GetFreq/XXX_InitPins/XXX_DeinitPins +in the application for enabling according instance. */ +#define RTE_USART0 1 +#define RTE_USART0_DMA_EN 0 +#define RTE_USART1 0 #define RTE_USART1_DMA_EN 0 +#define RTE_USART2 0 +#define RTE_USART2_DMA_EN 0 +#define RTE_USART3 1 +#define RTE_USART3_DMA_EN 0 +#define RTE_USART4 0 +#define RTE_USART4_DMA_EN 0 +#define RTE_USART5 0 +#define RTE_USART5_DMA_EN 0 +#define RTE_USART6 0 +#define RTE_USART6_DMA_EN 0 +#define RTE_USART7 0 +#define RTE_USART7_DMA_EN 0 + +/* USART configuration. */ +#define USART_RX_BUFFER_LEN 64 +#define USART0_RX_BUFFER_ENABLE 0 +#define USART1_RX_BUFFER_ENABLE 0 +#define USART2_RX_BUFFER_ENABLE 0 +#define USART3_RX_BUFFER_ENABLE 0 +#define USART4_RX_BUFFER_ENABLE 0 +#define USART5_RX_BUFFER_ENABLE 0 +#define USART6_RX_BUFFER_ENABLE 0 +#define USART7_RX_BUFFER_ENABLE 0 + +#define RTE_USART0_DMA_TX_CH 5 +#define RTE_USART0_DMA_TX_DMA_BASE DMA0 +#define RTE_USART0_DMA_RX_CH 4 +#define RTE_USART0_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART1_DMA_TX_CH 7 +#define RTE_USART1_DMA_TX_DMA_BASE DMA0 +#define RTE_USART1_DMA_RX_CH 6 +#define RTE_USART1_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART2_DMA_TX_CH 8 +#define RTE_USART2_DMA_TX_DMA_BASE DMA0 +#define RTE_USART2_DMA_RX_CH 9 +#define RTE_USART2_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART3_DMA_TX_CH 10 +#define RTE_USART3_DMA_TX_DMA_BASE DMA0 +#define RTE_USART3_DMA_RX_CH 11 +#define RTE_USART3_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART4_DMA_TX_CH 13 +#define RTE_USART4_DMA_TX_DMA_BASE DMA0 +#define RTE_USART4_DMA_RX_CH 12 +#define RTE_USART4_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART5_DMA_TX_CH 15 +#define RTE_USART5_DMA_TX_DMA_BASE DMA0 +#define RTE_USART5_DMA_RX_CH 14 +#define RTE_USART5_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART6_DMA_TX_CH 17 +#define RTE_USART6_DMA_TX_DMA_BASE DMA0 +#define RTE_USART6_DMA_RX_CH 16 +#define RTE_USART6_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART7_DMA_TX_CH 19 +#define RTE_USART7_DMA_TX_DMA_BASE DMA0 +#define RTE_USART7_DMA_RX_CH 18 +#define RTE_USART7_DMA_RX_DMA_BASE DMA0 + +/* I2C Select, I2C0 -I2C7*/ +/* User needs to provide the implementation for XXX_GetFreq/XXX_InitPins/XXX_DeinitPins +in the application for enabling according instance. */ +#define RTE_I2C0 0 +#define RTE_I2C0_DMA_EN 0 +#define RTE_I2C1 0 +#define RTE_I2C1_DMA_EN 0 +#define RTE_I2C2 0 +#define RTE_I2C2_DMA_EN 0 +#define RTE_I2C3 0 +#define RTE_I2C3_DMA_EN 0 +#define RTE_I2C4 0 +#define RTE_I2C4_DMA_EN 0 +#define RTE_I2C5 0 +#define RTE_I2C5_DMA_EN 0 +#define RTE_I2C6 0 +#define RTE_I2C6_DMA_EN 0 +#define RTE_I2C7 0 +#define RTE_I2C7_DMA_EN 0 + +/*I2C configuration*/ +#define RTE_I2C0_Master_DMA_BASE DMA0 +#define RTE_I2C0_Master_DMA_CH 1 + +#define RTE_I2C1_Master_DMA_BASE DMA0 +#define RTE_I2C1_Master_DMA_CH 3 + +#define RTE_I2C2_Master_DMA_BASE DMA0 +#define RTE_I2C2_Master_DMA_CH 5 + +#define RTE_I2C3_Master_DMA_BASE DMA0 +#define RTE_I2C3_Master_DMA_CH 7 + +#define RTE_I2C4_Master_DMA_BASE DMA0 +#define RTE_I2C4_Master_DMA_CH 9 + +#define RTE_I2C5_Master_DMA_BASE DMA0 +#define RTE_I2C5_Master_DMA_CH 11 + +#define RTE_I2C6_Master_DMA_BASE DMA0 +#define RTE_I2C6_Master_DMA_CH 13 + +#define RTE_I2C7_Master_DMA_BASE DMA0 +#define RTE_I2C7_Master_DMA_CH 15 + +/* SPI select, SPI0 - SPI7.*/ +/* User needs to provide the implementation for XXX_GetFreq/XXX_InitPins/XXX_DeinitPins +in the application for enabling according instance. */ +#define RTE_SPI0 0 +#define RTE_SPI0_DMA_EN 0 +#define RTE_SPI1 0 +#define RTE_SPI1_DMA_EN 0 +#define RTE_SPI2 0 +#define RTE_SPI2_DMA_EN 0 +#define RTE_SPI3 0 +#define RTE_SPI3_DMA_EN 0 +#define RTE_SPI4 0 +#define RTE_SPI4_DMA_EN 0 +#define RTE_SPI5 0 +#define RTE_SPI5_DMA_EN 0 +#define RTE_SPI6 0 +#define RTE_SPI6_DMA_EN 0 +#define RTE_SPI7 0 +#define RTE_SPI7_DMA_EN 0 + +/* SPI configuration. */ +#define RTE_SPI0_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI0_DMA_TX_CH 1 +#define RTE_SPI0_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI0_DMA_RX_CH 0 +#define RTE_SPI0_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI1_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI1_DMA_TX_CH 3 +#define RTE_SPI1_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI1_DMA_RX_CH 2 +#define RTE_SPI1_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI2_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI2_DMA_TX_CH 5 +#define RTE_SPI2_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI2_DMA_RX_CH 4 +#define RTE_SPI2_DMA_RX_DMA_BASE DMA0 +#define RTE_SPI3_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI3_DMA_TX_CH 7 +#define RTE_SPI3_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI3_DMA_RX_CH 6 +#define RTE_SPI3_DMA_RX_DMA_BASE DMA0 -#define RTE_USART1_DMA_TX_DMA_BASE (DMA0) -#define RTE_USART1_DMA_TX_CH (0) -#define RTE_USART1_DMA_TX_DMAMUX_BASE (DMAMUX0) -#define RTE_USART1_DMA_TX_PERI_SEL (5) // DMAMUX source 5 is UART1 TX +#define RTE_SPI4_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI4_DMA_TX_CH 9 +#define RTE_SPI4_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI4_DMA_RX_CH 8 +#define RTE_SPI4_DMA_RX_DMA_BASE DMA0 -#define RTE_USART1_DMA_RX_DMA_BASE (DMA0) -#define RTE_USART1_DMA_RX_CH (1) -#define RTE_USART1_DMA_RX_DMAMUX_BASE (DMAMUX0) -#define RTE_USART1_DMA_RX_PERI_SEL (4) // DMAMUX source 4 is UART1 RX +#define RTE_SPI5_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI5_DMA_TX_CH 11 +#define RTE_SPI5_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI5_DMA_RX_CH 10 +#define RTE_SPI5_DMA_RX_DMA_BASE DMA0 +#define RTE_SPI6_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI6_DMA_TX_CH 13 +#define RTE_SPI6_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI6_DMA_RX_CH 12 +#define RTE_SPI6_DMA_RX_DMA_BASE DMA0 -#endif /* __RTE_DEVICE_H */ +#define RTE_SPI7_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI7_DMA_TX_CH 15 +#define RTE_SPI7_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI7_DMA_RX_CH 14 +#define RTE_SPI7_DMA_RX_DMA_BASE DMA0 +#endif /* __RTE_DEVICE_H */ diff --git a/source/hic_hal/nxp/lpc55xx/pin_mux.c b/source/hic_hal/nxp/lpc55xx/pin_mux.c new file mode 100644 index 000000000..dd678e95a --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/pin_mux.c @@ -0,0 +1,145 @@ +/* + * DAPLink Interface Firmware + * Copyright (c) 2020 Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include "pin_mux.h" + +uint32_t USART0_GetFreq(void) +{ + return CLOCK_GetFlexCommClkFreq(0U); +} + +void USART0_InitPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t port0_pin24_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN29 (coords: ?) is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, 0U, 24U, port0_pin24_config); + + const uint32_t port0_pin25_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN30 (coords: ?) is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, 0U, 25U, port0_pin25_config); +} + +void USART0_DeinitPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t port0_pin24_config = (/* Pin is configured as PIO0_24 */ + IOCON_PIO_FUNC0 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN29 (coords: ?) is configured as PIO0_24 */ + IOCON_PinMuxSet(IOCON, 0U, 24U, port0_pin24_config); + + const uint32_t port0_pin25_config = (/* Pin is configured as PIO0_25 */ + IOCON_PIO_FUNC0 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN25 (coords: ?) is configured as PIO0_25 */ + IOCON_PinMuxSet(IOCON, 0U, 25U, port0_pin25_config); +} + +uint32_t USART3_GetFreq(void) +{ + return CLOCK_GetFlexCommClkFreq(3U); +} + +void USART3_InitPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t port0_pin3_config = (/* Pin is configured as FC3_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN3 (coords: ?) is configured as FC3_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, 0U, 3U, port0_pin3_config); +} + +void USART3_DeinitPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t port0_pin3_config = (/* Pin is configured as PIO0_3 */ + IOCON_PIO_FUNC0 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN29 (coords: ?) is configured as PIO0_24 */ + IOCON_PinMuxSet(IOCON, 0U, 3U, port0_pin3_config); +} diff --git a/source/hic_hal/nxp/lpc55xx/pin_mux.h b/source/hic_hal/nxp/lpc55xx/pin_mux.h new file mode 100644 index 000000000..e9af42a31 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/pin_mux.h @@ -0,0 +1,53 @@ +/* + * DAPLink Interface Firmware + * Copyright (c) 2020 Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +//! @name IOCON pin config constants +//@{ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_FUNC7 0x07u /*!<@brief Selects pin function 7 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +//@} + +#if defined(__cplusplus) +extern "C" { +#endif + +//! @name USART0 CMSIS-Driver callbacks +//@{ +uint32_t USART0_GetFreq(void); +void USART0_InitPins(void); +void USART0_DeinitPins(void); +//@} + +//! @name USART3 CMSIS-Driver callbacks +//@{ +uint32_t USART3_GetFreq(void); +void USART3_InitPins(void); +void USART3_DeinitPins(void); +//@} + +#if defined(__cplusplus) +} +#endif diff --git a/source/hic_hal/nxp/lpc55xx/uart.c b/source/hic_hal/nxp/lpc55xx/uart.c index 3a817927a..25053f5df 100644 --- a/source/hic_hal/nxp/lpc55xx/uart.c +++ b/source/hic_hal/nxp/lpc55xx/uart.c @@ -3,8 +3,7 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved - * Copyright (c) 2016-2017 NXP + * Copyright (c) 2020 Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -22,14 +21,15 @@ #include "string.h" #include "fsl_device_registers.h" +#include "fsl_usart_cmsis.h" #include "uart.h" #include "util.h" #include "cortex_m.h" #include "circ_buf.h" #include "settings.h" // for config_get_overflow_detect -#define UART_INSTANCE (USART0) -#define UART_IRQ (FLEXCOMM0_IRQn) +#define USART_INSTANCE (Driver_USART0) +#define USART_IRQ (FLEXCOMM0_IRQn) extern uint32_t SystemCoreClock; @@ -39,133 +39,129 @@ static void clear_buffers(void); #define RX_OVRF_MSG_SIZE (sizeof(RX_OVRF_MSG) - 1) #define BUFFER_SIZE (512) - circ_buf_t write_buffer; uint8_t write_buffer_data[BUFFER_SIZE]; circ_buf_t read_buffer; uint8_t read_buffer_data[BUFFER_SIZE]; +struct { + uint8_t rx; + uint8_t tx; +} cb_buf; + +void uart_handler(uint32_t event); + void clear_buffers(void) { -#ifdef LPC55_FIXME - util_assert(!(UART_INSTANCE->C2 & UART_C2_TIE_MASK)); -#endif circ_buf_init(&write_buffer, write_buffer_data, sizeof(write_buffer_data)); circ_buf_init(&read_buffer, read_buffer_data, sizeof(read_buffer_data)); } int32_t uart_initialize(void) { -#ifdef LPC55_FIXME - NVIC_DisableIRQ(UART_IRQ); - // enable clk PORTC - SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK; - // enable clk uart - SIM->SCGC4 |= SIM_SCGC4_UART0_MASK; - - // disable interrupt - NVIC_DisableIRQ(UART_IRQ); - // transmitter and receiver disabled - UART_INSTANCE->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK); - // disable interrupt - UART_INSTANCE->C2 &= ~(UART_C2_RIE_MASK | UART_C2_TIE_MASK); - clear_buffers(); + Driver_USART0.Initialize(uart_handler); - // Enable receiver and transmitter - UART_INSTANCE->C2 |= UART_C2_RE_MASK | UART_C2_TE_MASK; - - // alternate 3: UART0 - PORTB->PCR[16] = PORT_PCR_MUX(3); - PORTB->PCR[17] = PORT_PCR_MUX(3); - - // Enable receive interrupt - UART_INSTANCE->C2 |= UART_C2_RIE_MASK; - NVIC_ClearPendingIRQ(UART_IRQ); - NVIC_EnableIRQ(UART_IRQ); -#endif return 1; } int32_t uart_uninitialize(void) { - #ifdef LPC55_FIXME - // transmitter and receiver disabled - UART_INSTANCE->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK); - // disable interrupt - UART_INSTANCE->C2 &= ~(UART_C2_RIE_MASK | UART_C2_TIE_MASK); + USART_INSTANCE.Control(ARM_USART_CONTROL_RX, 0); + Driver_USART0.Uninitialize(); clear_buffers(); -#endif + return 1; } int32_t uart_reset(void) { -#ifdef LPC55_FIXME // disable interrupt - NVIC_DisableIRQ(UART_IRQ); - // disable TIE interrupt - UART_INSTANCE->C2 &= ~(UART_C2_TIE_MASK); + NVIC_DisableIRQ(USART_IRQ); clear_buffers(); // enable interrupt - NVIC_EnableIRQ(UART_IRQ); -#endif + NVIC_EnableIRQ(USART_IRQ); + return 1; } int32_t uart_set_configuration(UART_Configuration *config) { -#ifdef LPC55_FIXME - uint8_t data_bits = 8; - uint8_t parity_enable = 0; - uint8_t parity_type = 0; - uint32_t dll; - // disable interrupt - NVIC_DisableIRQ(UART_IRQ); - UART_INSTANCE->C2 &= ~(UART_C2_RIE_MASK | UART_C2_TIE_MASK); - // Disable receiver and transmitter while updating - UART_INSTANCE->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK); - clear_buffers(); + uint32_t control = ARM_USART_MODE_ASYNCHRONOUS; + + switch (config->DataBits) { + case UART_DATA_BITS_5: + control |= UART_DATA_BITS_5; + break; + + case UART_DATA_BITS_6: + control |= ARM_USART_DATA_BITS_6; + break; + + case UART_DATA_BITS_7: + control |= ARM_USART_DATA_BITS_6; + break; + + case UART_DATA_BITS_8: /* fallthrough */ + default: + control |= ARM_USART_DATA_BITS_8; + break; + } + + switch (config->Parity) { + case UART_PARITY_EVEN: + control |= ARM_USART_PARITY_EVEN; + break; + + case UART_PARITY_ODD: + control |= ARM_USART_PARITY_ODD; + break; - // set data bits, stop bits, parity - if ((config->DataBits < 8) || (config->DataBits > 9)) { - data_bits = 8; + case UART_PARITY_NONE: /* fallthrough */ + default: + control |= ARM_USART_PARITY_NONE; + break; } - data_bits -= 8; + switch (config->StopBits) { + case UART_STOP_BITS_1: /* fallthrough */ + default: + control |= ARM_USART_STOP_BITS_1; + break; - if (config->Parity == 1) { - parity_enable = 1; - parity_type = 1; - data_bits++; - } else if (config->Parity == 2) { - parity_enable = 1; - parity_type = 0; - data_bits++; + case UART_STOP_BITS_1_5: + control |= ARM_USART_STOP_BITS_1_5; + break; + + case UART_STOP_BITS_2: + control |= ARM_USART_STOP_BITS_2; + break; } - // does not support 10 bit data comm - if (data_bits == 2) { - data_bits = 0; - parity_enable = 0; - parity_type = 0; + switch (config->FlowControl) { + case UART_FLOW_CONTROL_NONE: /* fallthrough */ + default: + control |= ARM_USART_FLOW_CONTROL_NONE; + break; + + case UART_FLOW_CONTROL_RTS_CTS: + control |= ARM_USART_FLOW_CONTROL_RTS_CTS; + break; } - // data bits, parity and parity mode - UART_INSTANCE->C1 = data_bits << UART_C1_M_SHIFT - | parity_enable << UART_C1_PE_SHIFT - | parity_type << UART_C1_PT_SHIFT; - dll = SystemCoreClock / (16 * config->Baudrate); - // set baudrate - UART_INSTANCE->BDH = (UART_INSTANCE->BDH & ~(UART_BDH_SBR_MASK)) | ((dll >> 8) & UART_BDH_SBR_MASK); - UART_INSTANCE->BDL = (UART_INSTANCE->BDL & ~(UART_BDL_SBR_MASK)) | (dll & UART_BDL_SBR_MASK); - // Enable transmitter and receiver - UART_INSTANCE->C2 |= UART_C2_RE_MASK | UART_C2_TE_MASK; - // Enable UART interrupt - NVIC_ClearPendingIRQ(UART_IRQ); - NVIC_EnableIRQ(UART_IRQ); - UART_INSTANCE->C2 |= UART_C2_RIE_MASK; -#endif + NVIC_DisableIRQ(USART_IRQ); + clear_buffers(); + uint32_t r = USART_INSTANCE.Control(control, config->Baudrate); + if (r != ARM_DRIVER_OK) { + return 0; + } + USART_INSTANCE.Control(ARM_USART_CONTROL_TX, 1); + USART_INSTANCE.Control(ARM_USART_CONTROL_RX, 1); + USART_INSTANCE.Receive(&(cb_buf.rx), 1); + + NVIC_ClearPendingIRQ(USART_IRQ); + NVIC_EnableIRQ(USART_IRQ); + return 1; } @@ -181,23 +177,21 @@ int32_t uart_write_free(void) int32_t uart_write_data(uint8_t *data, uint16_t size) { -#ifdef LPC55_FIXME - cortex_int_state_t state; - uint32_t cnt; - - cnt = circ_buf_write(&write_buffer, data, size); + if (size == 0) { + return 0; + } - // Atomically enable TX - state = cortex_int_get_and_disable(); - if (circ_buf_count_used(&write_buffer)) { - UART_INSTANCE->C2 |= UART_C2_TIE_MASK; + uint32_t cnt = 0; + if (circ_buf_count_used(&write_buffer) > 0) { + cb_buf.tx = circ_buf_pop(&write_buffer); + cnt = circ_buf_write(&write_buffer, data, size); + } else { + cb_buf.tx = data[0]; + cnt = circ_buf_write(&write_buffer, data + 1, size - 1) + 1; } - cortex_int_restore(state); + USART_INSTANCE.Send(&(cb_buf.tx), 1); return cnt; -#else - return 0; -#endif } int32_t uart_read_data(uint8_t *data, uint16_t size) @@ -205,53 +199,24 @@ int32_t uart_read_data(uint8_t *data, uint16_t size) return circ_buf_read(&read_buffer, data, size); } -void UART0_RX_TX_IRQHandler(void) -{ -#ifdef LPC55_FIXME - uint32_t s1; - volatile uint8_t errorData; - // read interrupt status - s1 = UART_INSTANCE->S1; - // mask off interrupts that are not enabled - if (!(UART_INSTANCE->C2 & UART_C2_RIE_MASK)) { - s1 &= ~UART_S1_RDRF_MASK; - } - if (!(UART_INSTANCE->C2 & UART_C2_TIE_MASK)) { - s1 &= ~UART_S1_TDRE_MASK; - } - - // handle character to transmit - if (s1 & UART_S1_TDRE_MASK) { - // Assert that there is data in the buffer - util_assert(circ_buf_count_used(&write_buffer) > 0); - - // Send out data - UART_INSTANCE->D = circ_buf_pop(&write_buffer); - // Turn off the transmitter if that was the last byte - if (circ_buf_count_used(&write_buffer) == 0) { - // disable TIE interrupt - UART_INSTANCE->C2 &= ~(UART_C2_TIE_MASK); +void uart_handler(uint32_t event) { + if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) { + uint32_t free = circ_buf_count_free(&read_buffer); + if (free > RX_OVRF_MSG_SIZE) { + circ_buf_push(&read_buffer, cb_buf.rx); + } else if ((RX_OVRF_MSG_SIZE == free) && config_get_overflow_detect()) { + circ_buf_write(&read_buffer, (uint8_t*)RX_OVRF_MSG, RX_OVRF_MSG_SIZE); + } else { + // Drop character } + USART_INSTANCE.Receive(&(cb_buf.rx), 1); } - // handle received character - if (s1 & UART_S1_RDRF_MASK) { - if ((s1 & UART_S1_NF_MASK) || (s1 & UART_S1_FE_MASK)) { - errorData = UART_INSTANCE->D; - } else { - uint32_t free; - uint8_t data; - - data = UART_INSTANCE->D; - free = circ_buf_count_free(&read_buffer); - if (free > RX_OVRF_MSG_SIZE) { - circ_buf_push(&read_buffer, data); - } else if ((RX_OVRF_MSG_SIZE == free) && config_get_overflow_detect()) { - circ_buf_write(&read_buffer, (uint8_t*)RX_OVRF_MSG, RX_OVRF_MSG_SIZE); - } else { - // Drop character - } + if (event & ARM_USART_EVENT_SEND_COMPLETE) { + if (circ_buf_count_used(&write_buffer) > 0) { + cb_buf.tx = circ_buf_pop(&write_buffer); + USART_INSTANCE.Send(&(cb_buf.tx), 1); } } -#endif } + From 6d013684e6e8d83355447fa7a48204dd275b7acf Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Thu, 10 Dec 2020 17:49:37 -0600 Subject: [PATCH 128/617] LPC55xx: override validate_bin_nvic for bootloader. - Because the LPC5xx series raises bus faults on attempts to read from erased sectors in internal flash, the standard validate_bin_nvic() has to be overridden to prevent the bootloader from faulting when it tries to check if there is a valid interface app in flash. - This is done by supplying a target family and custom NVIC validator function. - The standard NVIC validation code is split out from validate_bin_nvic() into validate_bin_nvic_base() so it can be called from the custom validator once it is determined that the sector is programmed, or if the given address is not in internal flash. - Provide an overridden implementation of flash_is_page_readable() that uses the flash blank check command to see if the page is erased. --- source/board/lpc55s69_bl.c | 40 +++++++++++++++++++++++++-- source/daplink/validation.c | 9 +++++- source/daplink/validation.h | 10 ++++++- source/hic_hal/nxp/lpc55xx/hic_init.c | 35 +++++++++++++++++++++++ 4 files changed, 90 insertions(+), 4 deletions(-) diff --git a/source/board/lpc55s69_bl.c b/source/board/lpc55s69_bl.c index 7e474424c..baada80fb 100644 --- a/source/board/lpc55s69_bl.c +++ b/source/board/lpc55s69_bl.c @@ -24,10 +24,14 @@ #include "compiler.h" #include "target_board.h" #include "target_family.h" +#include "validation.h" +#include "flash_hal.h" // Warning - changing the interface start will break backwards compatibility COMPILER_ASSERT(DAPLINK_ROM_IF_START == (DAPLINK_ROM_START + KB(64))); +static uint8_t lpc55xx_bootloader_validate_nvic(const uint8_t *buf); + /** * List of start and size for each size of flash sector * The size will apply to all sectors between the listed address and the next address @@ -51,8 +55,16 @@ target_cfg_t target_device = { /* .flash_algo not needed for bootloader */ }; -//bootloader has no family -const target_family_descriptor_t *g_target_family = NULL; +/*! + * Special target family for the LPC55xx bootloader. It's only purpose is to override the + * validate_bin_nvic() routine to prevent bus faults from attempting to read erased flash. + */ +static const target_family_descriptor_t g_lpc55xx_bootloader_family = { + .family_id = 0, + .validate_bin_nvic = lpc55xx_bootloader_validate_nvic, +}; + +const target_family_descriptor_t *g_target_family = &g_lpc55xx_bootloader_family; const board_info_t g_board_info = { .info_version = kBoardInfoVersion, @@ -62,3 +74,27 @@ const board_info_t g_board_info = { .daplink_target_url = "https://mbed.com/daplink", .target_cfg = &target_device, }; + +//! @brief Customized NVIC validator. +//! +//! This NVIC validator first checks if the passed-in address points to the internal flash +//! memory. If so, an initial check is made to see if the flash is erased. If it is, then we +//! can't read from it or the flash controller will generate a bus fault. If the address is +//! either outside of flash, such as testing a new interface image in RAM, or the flash +//! sector is programmed, then the standard NVIC validator is called. +uint8_t lpc55xx_bootloader_validate_nvic(const uint8_t *buf) +{ + uint32_t addr = (uint32_t)buf; + + // If the address within internal flash? + if (addr >= DAPLINK_ROM_START && addr < (DAPLINK_ROM_START + DAPLINK_ROM_SIZE)) { + // If the flash sector is erased, then report that the NVIC is invalid. Otherwise + // continue below and perform the usual NVIC validation test. + if (!flash_is_readable(addr, 32)) { + return 0; + } + } + + // Call original implementation. + return validate_bin_nvic_base(buf); +} diff --git a/source/daplink/validation.c b/source/daplink/validation.c index 24c5b2d25..1e3920057 100644 --- a/source/daplink/validation.c +++ b/source/daplink/validation.c @@ -34,7 +34,14 @@ uint8_t validate_bin_nvic(const uint8_t *buf) { if (g_target_family && g_target_family->validate_bin_nvic) { return g_target_family && g_target_family->validate_bin_nvic(buf); - } else if (g_board_info.target_cfg) { + } else { + return validate_bin_nvic_base(buf); + } +} + +uint8_t validate_bin_nvic_base(const uint8_t *buf) +{ + if (!g_board_info.target_cfg) { uint32_t i = 4, nvic_val = 0; uint8_t in_range = 0; // test the initial SP value diff --git a/source/daplink/validation.h b/source/daplink/validation.h index 7363d700a..929d827fb 100644 --- a/source/daplink/validation.h +++ b/source/daplink/validation.h @@ -3,7 +3,7 @@ * @brief Helper functions to determine if a hex or binary file is valid * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2020, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -31,6 +31,14 @@ extern "C" { uint8_t validate_bin_nvic(const uint8_t *buf); uint8_t validate_hexfile(const uint8_t *buf); +/*! + * @brief Baseline implementation of NVIC validator. + * + * This version does not include the redirection to a target family validator if + * one is supplied in the target family struct. + */ +uint8_t validate_bin_nvic_base(const uint8_t *buf); + #ifdef __cplusplus } #endif diff --git a/source/hic_hal/nxp/lpc55xx/hic_init.c b/source/hic_hal/nxp/lpc55xx/hic_init.c index 0029517fd..95cd2e742 100644 --- a/source/hic_hal/nxp/lpc55xx/hic_init.c +++ b/source/hic_hal/nxp/lpc55xx/hic_init.c @@ -25,6 +25,9 @@ #include "fsl_clock.h" #include "usb_phy.h" #include "util.h" +#include "flash_hal.h" + +#define FLASH_CMD_BLANK_CHECK (0x5) static void busy_wait(uint32_t cycles) { @@ -161,3 +164,35 @@ void hic_power_target(void) #endif } } + +// Override the default weak implementation. +bool flash_is_readable(uint32_t addr, uint32_t length) +{ + // Make sure the core clock is less than 100 MHz, or flash commands won't work. + util_assert(SystemCoreClock > 100000000); + + // Return true if the address is within internal flash and the flash sector is not erased. + if (!(addr >= DAPLINK_ROM_START && addr < (DAPLINK_ROM_START + DAPLINK_ROM_SIZE))) { + return false; + } + + // Use the blank check command directly. The address is right-shifted to convert to + // a flash word (16 bytes) address. + FLASH->STARTA = addr >> 4; + FLASH->STOPA = (addr + length - 1) >> 4; + FLASH->INT_CLR_STATUS = FLASH_INT_CLR_STATUS_FAIL_MASK + | FLASH_INT_CLR_STATUS_ERR_MASK + | FLASH_INT_CLR_STATUS_DONE_MASK + | FLASH_INT_CLR_STATUS_ECC_ERR_MASK; + FLASH->CMD = FLASH_CMD_BLANK_CHECK; + + // Wait until command is complete. + while (((FLASH->INT_STATUS) & FLASH_INT_STATUS_DONE_MASK) == 0) { + } + + // Return true (is readable) if the blank check failed, meaning the page is programmed. + // Return false (not readable) for erased page or failure. + return ((FLASH->INT_STATUS & (FLASH_INT_STATUS_FAIL_MASK + | FLASH_INT_STATUS_ERR_MASK + | FLASH_INT_STATUS_ECC_ERR_MASK)) == FLASH_INT_STATUS_FAIL_MASK); +} From 905d7f6c6f2981410020f5a287a10b632ab67d93 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Fri, 11 Dec 2020 17:56:06 -0600 Subject: [PATCH 129/617] LPC55xx: (FIXME) temporarily disabled CRC computation in info.c. --- source/daplink/info.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/source/daplink/info.c b/source/daplink/info.c index 5be10d8e7..41ecd8b1a 100644 --- a/source/daplink/info.c +++ b/source/daplink/info.c @@ -294,22 +294,38 @@ void info_crc_compute() // Compute the CRCs of regions that exist if ((DAPLINK_ROM_BL_SIZE > 0) && flash_is_readable(DAPLINK_ROM_BL_START, DAPLINK_ROM_BL_SIZE - 4)) { +#ifdef INTERFACE_LPC55XX // FIXME: CRC + crc_bootloader = 0; +#else crc_bootloader = crc32((void *)DAPLINK_ROM_BL_START, DAPLINK_ROM_BL_SIZE - 4); +#endif } if ((DAPLINK_ROM_IF_SIZE > 0) && flash_is_readable(DAPLINK_ROM_IF_START, DAPLINK_ROM_IF_SIZE - 4)) { +#ifdef INTERFACE_LPC55XX // FIXME: CRC + crc_interface = 0; +#else crc_interface = crc32((void *)DAPLINK_ROM_IF_START, DAPLINK_ROM_IF_SIZE - 4); +#endif } if ((DAPLINK_ROM_CONFIG_ADMIN_SIZE > 0) && flash_is_readable(DAPLINK_ROM_CONFIG_ADMIN_START, DAPLINK_ROM_CONFIG_ADMIN_SIZE)) { +#ifdef INTERFACE_LPC55XX // FIXME: CRC + crc_config_admin = 0; +#else crc_config_admin = crc32((void *)DAPLINK_ROM_CONFIG_ADMIN_START, DAPLINK_ROM_CONFIG_ADMIN_SIZE); +#endif } if ((DAPLINK_ROM_CONFIG_USER_SIZE > 0) && flash_is_readable(DAPLINK_ROM_CONFIG_USER_START, DAPLINK_ROM_CONFIG_USER_SIZE)) { +#ifdef INTERFACE_LPC55XX // FIXME: CRC + crc_config_user = 0; +#else crc_config_user = crc32((void *)DAPLINK_ROM_CONFIG_USER_START, DAPLINK_ROM_CONFIG_USER_SIZE); +#endif } } From dff878ca89aa517813e0ced6b1325cc566d4305c Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Thu, 17 Dec 2020 19:18:43 -0600 Subject: [PATCH 130/617] LPC55xx: clock init. - Booting BL and IF to 96 MHz, to keep main clock below 100 MHz so internal flash can be programmed. - IF changes to 150 MHz when initing USB clocks. --- source/hic_hal/nxp/lpc55xx/hic_init.c | 270 +++++++++++++++----------- source/hic_hal/nxp/lpc55xx/hic_init.h | 9 +- source/hic_hal/nxp/lpc55xx/pin_mux.c | 18 ++ source/hic_hal/nxp/lpc55xx/pin_mux.h | 3 + 4 files changed, 188 insertions(+), 112 deletions(-) diff --git a/source/hic_hal/nxp/lpc55xx/hic_init.c b/source/hic_hal/nxp/lpc55xx/hic_init.c index 95cd2e742..71136bd83 100644 --- a/source/hic_hal/nxp/lpc55xx/hic_init.c +++ b/source/hic_hal/nxp/lpc55xx/hic_init.c @@ -3,8 +3,7 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved - * Copyright (c) 2016-2017 NXP + * Copyright (c) 2020 Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -21,124 +20,189 @@ */ #include "hic_init.h" -#include "gpio.h" +#include "daplink.h" #include "fsl_clock.h" +#include "fsl_power.h" +#include "fsl_reset.h" +#include "fsl_usb.h" +#include "fsl_iocon.h" #include "usb_phy.h" #include "util.h" #include "flash_hal.h" +#include "pin_mux.h" #define FLASH_CMD_BLANK_CHECK (0x5) -static void busy_wait(uint32_t cycles) +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFROHF96M +outputs: +- {id: System_clock.outFreq, value: 96 MHz} +settings: +- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} +- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk} +sources: +- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF96M(void) { - volatile uint32_t i; - i = cycles; +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ - while (i > 0) { - i--; - } -} + CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ -static void fll_delay(void) -{ - // ~2.5ms at 16MHz core clock - busy_wait(10000); + POWER_SetVoltageForFreq( + 96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + + /*< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; +#endif } -// This IRQ handler will be invoked if VDD falls below the trip point. -void LVD_LVW_IRQHandler(void) +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL150M +called_from_default_init: true +outputs: +- {id: System_clock.outFreq, value: 150 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +void BOARD_BootClockPLL150M(void) { -#ifdef LPC55_FIXME - if (PMC->LVDSC1 & PMC_LVDSC1_LVDF_MASK) - { - util_assert(false && "low voltage detect tripped"); - PMC->LVDSC1 |= PMC_LVDSC1_LVDACK_MASK; - } - if (PMC->LVDSC2 & PMC_LVDSC2_LVWF_MASK) - { - util_assert(false && "low voltage warning tripped"); - PMC->LVDSC2 |= PMC_LVDSC2_LVWACK_MASK; - } +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ +// POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ +// CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ +// CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + POWER_SetVoltageForFreq( + 150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U), + .pllndec = SYSCON_PLL0NDEC_NDIV(8U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(1U), + .pllsscg = {0x0U, (SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 150000000U, + .flags = PLL_SETUPFLAG_WAITLOCK}; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ + + /*< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK; #endif } -//! - MPU is disabled and gated. -//! - 8kB cache is enabled. SRAM is not cached, so no flushing is required for normal operation. -//! - Enable low voltage warning interrupt. -//! - Disable USB current limiter so the voltage doesn't drop as we enable high speed clocks. +//! Setup clocks to run from the FRO HF at 96 MHz. void sdk_init(void) { -#ifdef LPC55_FIXME - CLOCK_SetXtal0Freq(16000000U); // 16 MHz crystal - CLOCK_SetXtal32Freq(0); - - // Disable the MPU if it's enabled. - if (SIM->SCGC7 & SIM_SCGC7_MPU_MASK) - { - SYSMPU->CESR = 0; - SIM->SCGC7 &= ~SIM_SCGC7_MPU_MASK; - } - - // Invalidate and enable code cache. - LMEM->PCCCR = LMEM_PCCCR_GO_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_ENCACHE_MASK; - - // Enable LVD/LVW IRQ. - PMC->LVDSC1 |= PMC_LVDSC1_LVDACK_MASK; - PMC->LVDSC1 = PMC_LVDSC1_LVDIE_MASK | PMC_LVDSC1_LVDV(0); // low trip point - PMC->LVDSC2 |= PMC_LVDSC2_LVWACK_MASK; - PMC->LVDSC2 = PMC_LVDSC2_LVWIE_MASK | PMC_LVDSC2_LVWV(0); // low trip point - // NVIC_EnableIRQ(LVD_LVW_IRQn); - - // Disable USB inrush current limiter. - SIM->USBPHYCTL |= SIM_USBPHYCTL_USBDISILIM_MASK; -#endif + BOARD_BootClockFROHF96M(); } +//! - Configure the VBUS pin. +//! - Switch USB1 to device mode. //! - Turn on 16MHz crystal oscillator. -//! - Turn on 32kHz IRC. -//! - Switch core clock to System PLL at 120 MHz, bus clock at 60 MHz, flash clock at 24 MHz. -//! - Enable the 480MHz USB PHY PLL. +//! - Switch main clock to PLL0 at 150 MHz. //! - Ungate USBPHY and USBHS. -//! - Configure the USB PHY. +//! - Configure the USB PHY and USB1 clocks. void hic_enable_usb_clocks(void) { -#ifdef LPC55_FIXME - // Enable external oscillator and 32kHz IRC. - MCG->C1 |= MCG_C1_IRCLKEN_MASK; // Select 32k IR. - // Delay at least 100µs for 32kHz IRQ to stabilize. - fll_delay(); - // Configure OSC for very high freq, low power mode. - MCG->C2 = (MCG->C2 & ~(MCG_C2_RANGE_MASK | MCG_C2_HGO_MASK)) | MCG_C2_RANGE(2); - OSC0->CR |= OSC_CR_ERCLKEN_MASK; // Enable OSC. - MCG->C2 |= MCG_C2_EREFS_MASK; // Select OSC as ext ref. - - // Wait for the oscillator to stabilize. - while (!(MCG->S & MCG_S_OSCINIT0_MASK)) - { - } - - // Divide 16MHz xtal by 512 = 31.25kHz - CLOCK_SetFbeMode(4, kMCG_Dmx32Default, kMCG_DrsMid, fll_delay); - - // Set dividers before switching to SYSPLL. - SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) // System/core /1 = 120MHz - | SIM_CLKDIV1_OUTDIV2(1) // Bus /2 = 60Mhz - | SIM_CLKDIV1_OUTDIV3(4) // FlexBus /5 = 24Mhz - | SIM_CLKDIV1_OUTDIV4(4); // Flash /5 = 24MHz - - // 120MHz SYSPLL - mcg_pll_config_t pllConfig; - pllConfig.enableMode = 0; - pllConfig.prdiv = 2 - 1; - pllConfig.vdiv = 30 - 16; - CLOCK_SetPbeMode(kMCG_PllClkSelPll0, &pllConfig); - CLOCK_SetPeeMode(); - - // Enable USB clock source and init phy. This turns on the 480MHz PLL. - CLOCK_EnableUsbhs0Clock(kCLOCK_UsbSrcPll0, CLOCK_GetFreq(kCLOCK_PllFllSelClk)); - USB_EhciPhyInit(0, CPU_XTAL_CLK_HZ); + // For the interface, switch to 150 MHz before enabling USB. The bootloader will stay at 96 MHz + // so it can always write internal flash. +#if defined(DAPLINK_IF) + BOARD_BootClockPLL150M(); #endif - SystemCoreClockUpdate(); + + NVIC_ClearPendingIRQ(USB1_IRQn); + NVIC_ClearPendingIRQ(USB1_NEEDCLK_IRQn); + + /* reset the IP to make sure it's in reset state. */ + RESET_PeripheralReset(kUSB1H_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSB1D_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSB1_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn); + + // Enable VBUS pin. + init_vbus_pin(); + + // Switch IP to device mode. First enable the USB1 host clock. + CLOCK_EnableClock(kCLOCK_Usbh1); + // Put PHY powerdown under software control + USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; + // According to reference mannual, device mode setting has to be set by access usb host register + USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; + // Disable usb1 host clock + CLOCK_DisableClock(kCLOCK_Usbh1); + + // Enable clocks. + CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_UsbPhySrcExt, BOARD_XTAL0_CLK_HZ); + CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUnused, 0U); + + // Init PHY. + USB_EhciPhyInit(kUSB_ControllerLpcIp3511Hs0, BOARD_XTAL0_CLK_HZ, NULL); } void hic_power_target(void) @@ -147,21 +211,7 @@ void hic_power_target(void) // to prevent the target from effecting the state // of the reset line / reset button if (!daplink_is_bootloader()) { -#ifdef LPC55_FIXME - // configure pin as GPIO - PIN_POWER_EN_PORT->PCR[PIN_POWER_EN_BIT] = PORT_PCR_MUX(1); - // force always on logic 1 - PIN_POWER_EN_GPIO->PSOR = 1UL << PIN_POWER_EN_BIT; - PIN_POWER_EN_GPIO->PDDR |= 1UL << PIN_POWER_EN_BIT; - - // Let the voltage rails stabilize. This is especailly important - // during software resets, since the target's 3.3v rail can take - // 20-50ms to drain. During this time the target could be driving - // the reset pin low, causing the bootloader to think the reset - // button is pressed. - // Note: With optimization set to -O2 the value 5115 delays for ~1ms @ 20.9Mhz core - busy_wait(5115 * 50); -#endif + // Nothing to do for MCU-Link schematic. } } diff --git a/source/hic_hal/nxp/lpc55xx/hic_init.h b/source/hic_hal/nxp/lpc55xx/hic_init.h index 91f9ddb9a..ce9499dae 100644 --- a/source/hic_hal/nxp/lpc55xx/hic_init.h +++ b/source/hic_hal/nxp/lpc55xx/hic_init.h @@ -3,8 +3,7 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved - * Copyright (c) 2016-2017 NXP + * Copyright (c) 2020 Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -20,6 +19,12 @@ * limitations under the License. */ +#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ + +#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ +#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */ + #if defined(__cplusplus) extern "C" { #endif diff --git a/source/hic_hal/nxp/lpc55xx/pin_mux.c b/source/hic_hal/nxp/lpc55xx/pin_mux.c index dd678e95a..1e60ffe1b 100644 --- a/source/hic_hal/nxp/lpc55xx/pin_mux.c +++ b/source/hic_hal/nxp/lpc55xx/pin_mux.c @@ -143,3 +143,21 @@ void USART3_DeinitPins(void) /* PORT0 PIN29 (coords: ?) is configured as PIO0_24 */ IOCON_PinMuxSet(IOCON, 0U, 3U, port0_pin3_config); } + +void init_vbus_pin(void) +{ + const uint32_t port0_pin22_config = (/* Pin is configured as USB0_VBUS */ + IOCON_PIO_FUNC7 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN22 (coords: 78) is configured as USB0_VBUS */ + IOCON_PinMuxSet(IOCON, 0U, 22U, port0_pin22_config); +} diff --git a/source/hic_hal/nxp/lpc55xx/pin_mux.h b/source/hic_hal/nxp/lpc55xx/pin_mux.h index e9af42a31..27d82395d 100644 --- a/source/hic_hal/nxp/lpc55xx/pin_mux.h +++ b/source/hic_hal/nxp/lpc55xx/pin_mux.h @@ -48,6 +48,9 @@ void USART3_InitPins(void); void USART3_DeinitPins(void); //@} +//! @brief Configure VBUS pin. +void init_vbus_pin(void); + #if defined(__cplusplus) } #endif From 2511e78e24d0eed41c174597e821bb0e50c0c3e7 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sat, 12 Dec 2020 18:18:49 -0600 Subject: [PATCH 131/617] LPC55xx: USB device is enumerating. Lots of cleanup to make USBD driver more understandable. --- source/hic_hal/nxp/lpc55xx/usbd_LPC55xx.c | 201 +++++++++++----------- 1 file changed, 104 insertions(+), 97 deletions(-) diff --git a/source/hic_hal/nxp/lpc55xx/usbd_LPC55xx.c b/source/hic_hal/nxp/lpc55xx/usbd_LPC55xx.c index 84c2f99c1..7d3bc58f1 100644 --- a/source/hic_hal/nxp/lpc55xx/usbd_LPC55xx.c +++ b/source/hic_hal/nxp/lpc55xx/usbd_LPC55xx.c @@ -32,21 +32,49 @@ #define __NO_USB_LIB_C #include "usb_config.c" -#define BUF_ACTIVE (1UL << 31) -#define EP_DISABLED (1UL << 30) -#define EP_STALL (1UL << 29) -#define TOOGLE_RESET (1UL << 28) -#define EP_TYPE (1UL << 26) - -#define N_BYTES(n) ((n & 0x3FF) << 16) -#define BUF_ADDR(addr) (((addr) >> 6) & 0xFFFF) +// Warning: this driver does *not* correctly support either isochronous endpoints or +// interrupt endpoints in rate feedback mode! + +#define EP_BUF_ACTIVE (1UL << 31) +#define EP_DISABLED (1UL << 30) +#define EP_STALL (1UL << 29) +#define EP_TOGGLE_RESET (1UL << 28) +#define EP_RF_TV (1UL << 27) +#define EP_TYPE (1UL << 26) // 0=generic, 1=periodic +#define EP_NBYTES_MASK (0x03fff800) +#define EP_NBYTES_SHIFT (11) +#define EP_BUF_OFFSET_MASK (0x000003ff) +#define EP_BUF_OFFSET_SHIFT (0) + +// DEVCMDSTAT Speed field values. +#define DEVCMDSTAT_SPEED_FULL (0x1) +#define DEVCMDSTAT_SPEED_HIGH (0x2) + +// Alignment and rounding size for endpoint buffers. +#define MIN_BUF_SIZE (64) + +#define N_BYTES(n) (((n) << EP_NBYTES_SHIFT) & EP_NBYTES_MASK) +#define BUF_ADDR(s_next_ep_buf_addr) (((s_next_ep_buf_addr) >> 6) & EP_BUF_OFFSET_MASK) #define EP_OUT_IDX(EPNum) (EPNum * 2 ) #define EP_IN_IDX(EPNum) (EPNum * 2 + 1) -#define EP_LIST_BASE 0x40100000 +#define EP_LIST_BASE (0x40100000) #define EP_BUF_BASE (uint32_t)(EP_LIST_BASE + 0x100) +#define EP0_OUT_BUF_OFFSET (0) +#define EP0_SETUP_BUF_OFFSET (1) +#define EP0_IN_BUF_OFFSET (2) + +#define EP0_OUT_BUF_BASE (EP0_OUT_BUF_OFFSET * USBD_MAX_PACKET0 + EP_BUF_BASE) +#define EP0_SETUP_BUF_BASE (EP0_SETUP_BUF_OFFSET * USBD_MAX_PACKET0 + EP_BUF_BASE) +#define EP0_IN_BUF_BASE (EP0_IN_BUF_OFFSET * USBD_MAX_PACKET0 + EP_BUF_BASE) + +//! @brief Base address of the EP1 OUT buffer. +//! +//! The EP1 OUT buffer starts after the EP0 OUT buffer, SETUP buffer, and EP0 IN buffer. +#define EP1_BUF_BASE (3 * USBD_MAX_PACKET0 + EP_BUF_BASE) + typedef struct BUF_INFO { uint32_t buf_len; uint32_t buf_ptr; @@ -61,8 +89,8 @@ volatile uint32_t EPList[(USBD_EP_NUM + 1) * 2] __attribute__((section(".usbram #error "Unsupported compiler!" #endif -static uint32_t addr = 3 * 64 + EP_BUF_BASE; -static uint32_t ctrl_out_next = 0; +static uint32_t s_next_ep_buf_addr = EP1_BUF_BASE; +static uint32_t s_read_ctrl_out_next = 0; /* * Get EP CmdStat pointer @@ -113,50 +141,13 @@ void __SVC_1(int ena) void USBD_Init(void) { - // Enable VBUS pin. - CLOCK_EnableClock(kCLOCK_Iocon); - - const uint32_t port0_pin22_config = (/* Pin is configured as USB0_VBUS */ - IOCON_PIO_FUNC7 | - /* No addition pin function */ - IOCON_PIO_MODE_INACT | - /* Standard mode, output slew rate control is enabled */ - IOCON_PIO_SLEW_STANDARD | - /* Input function is not inverted */ - IOCON_PIO_INV_DI | - /* Enables digital function */ - IOCON_PIO_DIGITAL_EN | - /* Open drain is disabled */ - IOCON_PIO_OPENDRAIN_DI); - /* PORT0 PIN22 (coords: 78) is configured as USB0_VBUS */ - IOCON_PinMuxSet(IOCON, 0U, 22U, port0_pin22_config); - - // Switch IP to device mode. First enable the USB1 host clock. - CLOCK_EnableClock(kCLOCK_Usbh1); - // Put PHY powerdown under software control - USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; - // According to reference mannual, device mode setting has to be set by access usb host register - USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; - // Disable usb1 host clock - CLOCK_DisableClock(kCLOCK_Usbh1); - - // Enable clocks. - CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_UsbPhySrcExt, BOARD_XTAL0_CLK_HZ); - CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUnused, 0U); - - // Init PHY. - USB_EhciPhyInit(kUSB_ControllerLpcIp3511Hs0, BOARD_XTAL0_CLK_HZ, NULL); - -// SYSCON->SYSAHBCLKCTRL |= (1UL << 6); -// SYSCON->SYSAHBCLKCTRL |= (1UL << 14) | -// (1UL << 27); + // Init clocks, HS PHY, and VBUS pin. + hic_enable_usb_clocks(); + + // Force clocks enabled. USBHSD->DEVCMDSTAT |= USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK; -// IOCON->PIO0_3 &= ~(0x1F); -// IOCON->PIO0_3 |= (1UL << 0); /* Secondary function VBUS */ -// IOCON->PIO0_6 &= ~7; -// IOCON->PIO0_6 |= (1UL << 0); /* Secondary function USB CON */ -// SYSCON->PDRUNCFG &= ~((1UL << 8) | /* USB PLL powered */ -// (1UL << 10)); /* USB transceiver powered */ + + // Setup EP USBHSD->DATABUFSTART = EP_BUF_BASE & 0xFFC00000; USBHSD->EPLISTSTART = EP_LIST_BASE; @@ -197,29 +188,34 @@ void NO_OPTIMIZE_INLINE USBD_Reset(void) { uint32_t i; uint32_t *ptr; - addr = 3 * 64 + EP_BUF_BASE; + s_next_ep_buf_addr = EP1_BUF_BASE; for (i = 2; i < (5 * 4); i++) { EPList[i] = (1UL << 30); /* EPs disabled */ } - ctrl_out_next = 0; + s_read_ctrl_out_next = 0; EPBufInfo[0].buf_len = USBD_MAX_PACKET0; - EPBufInfo[0].buf_ptr = EP_BUF_BASE; + EPBufInfo[0].buf_ptr = EP0_OUT_BUF_BASE; EPBufInfo[1].buf_len = USBD_MAX_PACKET0; - EPBufInfo[1].buf_ptr = EP_BUF_BASE + 2 * 64; + EPBufInfo[1].buf_ptr = EP0_IN_BUF_BASE; ptr = GetEpCmdStatPtr(0); *ptr = N_BYTES(EPBufInfo[0].buf_len) | /* EP0 OUT */ BUF_ADDR(EPBufInfo[0].buf_ptr) | - BUF_ACTIVE; + EP_BUF_ACTIVE; + // EP0 SETUP buf info follows EP0 OUT, precedes EP0 IN. ptr++; - *ptr = BUF_ADDR(EPBufInfo[0].buf_ptr + 64);/* SETUP */ + *ptr = BUF_ADDR(EP0_SETUP_BUF_BASE);/* SETUP */ USBHSD->DEVCMDSTAT |= USBHSD_DEVCMDSTAT_DEV_EN_MASK; /*USB device enable */ USBHSD->INTSTAT = 0x2FC; /* clear EP interrupt flags */ USBHSD->INTEN = (USBHSD_INTEN_FRAME_INT_EN_MASK | /* SOF intr enable */ USBHSD_INTEN_EP_INT_EN(0) | /* EP0 OUT intr enable */ USBHSD_INTEN_EP_INT_EN(1) | /* EP0 IN intr enable */ USBHSD_INTEN_DEV_INT_EN_MASK); /* stat change int en */ + + // Set bus speed. + uint32_t speed = (USBHSD->DEVCMDSTAT & USBHSD_DEVCMDSTAT_Speed_MASK) >> USBHSD_DEVCMDSTAT_Speed_SHIFT; + USBD_HighSpeed = (speed == DEVCMDSTAT_SPEED_HIGH); } NO_OPTIMIZE_POST @@ -305,7 +301,7 @@ void USBD_SetAddress(uint32_t adr, uint32_t setup) void USBD_Configure(BOOL cfg) { - addr = 3 * 64 + EP_BUF_BASE; + s_next_ep_buf_addr = EP1_BUF_BASE; } @@ -327,12 +323,15 @@ void USBD_ConfigEP(USB_ENDPOINT_DESCRIPTOR *pEPD) if (num & 0x80) { num &= ~0x80; EPBufInfo[EP_IN_IDX(num)].buf_len = val; - EPBufInfo[EP_IN_IDX(num)].buf_ptr = addr; - addr += ((val + 63) >> 6) * 64; /* calc new free buffer address */ + EPBufInfo[EP_IN_IDX(num)].buf_ptr = s_next_ep_buf_addr; + s_next_ep_buf_addr += ROUND_UP(val, MIN_BUF_SIZE); /* calc new free buffer address */ ptr = GetEpCmdStatPtr(num | 0x80); *ptr = EP_DISABLED; - if (type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + if (type == USB_ENDPOINT_TYPE_INTERRUPT) { + *ptr |= EP_TYPE | EP_RF_TV; + } + else if (type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { *ptr |= EP_TYPE; } } @@ -340,17 +339,20 @@ void USBD_ConfigEP(USB_ENDPOINT_DESCRIPTOR *pEPD) /* OUT EPs */ else { EPBufInfo[EP_OUT_IDX(num)].buf_len = val; - EPBufInfo[EP_OUT_IDX(num)].buf_ptr = addr; + EPBufInfo[EP_OUT_IDX(num)].buf_ptr = s_next_ep_buf_addr; ptr = GetEpCmdStatPtr(num); *ptr = N_BYTES(EPBufInfo[EP_OUT_IDX(num)].buf_len) | BUF_ADDR(EPBufInfo[EP_OUT_IDX(num)].buf_ptr) | EP_DISABLED; - if (type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + if (type == USB_ENDPOINT_TYPE_INTERRUPT) { + *ptr |= EP_TYPE | EP_RF_TV; + } + else if (type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { *ptr |= EP_TYPE; } - addr += ((val + 63) >> 6) * 64; /* calc new free buffer address */ + s_next_ep_buf_addr += ROUND_UP(val, MIN_BUF_SIZE); /* calc new free buffer address */ } } @@ -391,7 +393,7 @@ void USBD_EnableEP(uint32_t EPNum) /* OUT EP */ else { *ptr &= ~EP_DISABLED; - *ptr |= BUF_ACTIVE; + *ptr |= EP_BUF_ACTIVE; USBHSD->INTSTAT = (1 << EP_OUT_IDX(EPNum)); USBHSD->INTEN |= (1 << EP_OUT_IDX(EPNum)); } @@ -434,7 +436,7 @@ void USBD_ResetEP(uint32_t EPNum) { uint32_t *ptr; ptr = GetEpCmdStatPtr(EPNum); - *ptr |= TOOGLE_RESET; + *ptr |= EP_TOGGLE_RESET; } @@ -452,8 +454,8 @@ void USBD_SetStallEP(uint32_t EPNum) ptr = GetEpCmdStatPtr(EPNum); if (EPNum & 0x7F) { - if (*ptr & BUF_ACTIVE) { - *ptr &= ~(BUF_ACTIVE); + if (*ptr & EP_BUF_ACTIVE) { + *ptr &= ~(EP_BUF_ACTIVE); } } else { @@ -472,7 +474,7 @@ void USBD_SetStallEP(uint32_t EPNum) if ((EPNum & 0x7F) == 0) { /* Endpoint is stalled so control out won't be next */ - ctrl_out_next = 0; + s_read_ctrl_out_next = 0; } *ptr |= EP_STALL; @@ -497,7 +499,7 @@ void USBD_ClrStallEP(uint32_t EPNum) } else { *ptr &= ~EP_STALL; - *ptr |= BUF_ACTIVE; + *ptr |= EP_BUF_ACTIVE; } USBD_ResetEP(EPNum); @@ -515,11 +517,11 @@ void USBD_ClrStallEP(uint32_t EPNum) void USBD_ClearEPBuf(uint32_t EPNum) { uint32_t cnt, i; - U8 *dataptr; + uint8_t *dataptr; if (EPNum & 0x80) { EPNum &= ~0x80; - dataptr = (U8 *)EPBufInfo[EP_IN_IDX(EPNum)].buf_ptr; + dataptr = (uint8_t *)EPBufInfo[EP_IN_IDX(EPNum)].buf_ptr; cnt = EPBufInfo[EP_IN_IDX(EPNum)].buf_len; for (i = 0; i < cnt; i++) { @@ -527,7 +529,7 @@ void USBD_ClearEPBuf(uint32_t EPNum) } } else { - dataptr = (U8 *)EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr; + dataptr = (uint8_t *)EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr; cnt = EPBufInfo[EP_OUT_IDX(EPNum)].buf_len; for (i = 0; i < cnt; i++) { @@ -546,47 +548,52 @@ void USBD_ClearEPBuf(uint32_t EPNum) * Return Value: Number of bytes read */ -uint32_t USBD_ReadEP(uint32_t EPNum, U8 *pData, uint32_t size) +uint32_t USBD_ReadEP(uint32_t EPNum, uint8_t *pData, uint32_t size) { - uint32_t cnt, i, xfer_size; + uint32_t cnt, i;//, xfer_size; volatile uint32_t *ptr; - U8 *dataptr; + uint8_t *dataptr; ptr = GetEpCmdStatPtr(EPNum); int timeout = 256; /* Setup packet */ - if ((EPNum == 0) && !ctrl_out_next && (USBHSD->DEVCMDSTAT & USBHSD_DEVCMDSTAT_SETUP_MASK)) { - cnt = USBD_MAX_PACKET0; + if ((EPNum == 0) && !s_read_ctrl_out_next && (USBHSD->DEVCMDSTAT & USBHSD_DEVCMDSTAT_SETUP_MASK)) { + cnt = sizeof(USB_SETUP_PACKET); if (size < cnt) { util_assert(0); cnt = size; } - dataptr = (U8 *)(EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr + 64); + dataptr = (uint8_t *)(EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr + EP0_SETUP_BUF_OFFSET * USBD_MAX_PACKET0); for (i = 0; i < cnt; i++) { pData[i] = dataptr[i]; } - xfer_size = (pData[7] << 8) | (pData[6] << 0); - if ((xfer_size > 0) && (pData[0] & (1 << 7))) { + // Copy the SETUP packet into a struct we can read from more understandably. + USB_SETUP_PACKET setup; + memcpy(&setup, pData, sizeof(setup)); + + if ((setup.wLength > 0) && setup.bmRequestType.Dir) { /* This control transfer has a data IN stage */ /* and ends with a zero length data OUT transfer. */ /* Ensure the data OUT token is not skipped even if */ /* a SETUP token arrives before USBD_ReadEP has */ /* been called. */ - ctrl_out_next = 1; + s_read_ctrl_out_next = 1; } USBHSD->EPSKIP |= (1 << EP_IN_IDX(EPNum)); while (USBHSD->EPSKIP & (1 << EP_IN_IDX(EPNum))); + // Clear stall on EP0 IN. if (*(ptr + 2) & EP_STALL) { *(ptr + 2) &= ~(EP_STALL); } + // Clear stall on EP0 OUT. if (*ptr & EP_STALL) { *ptr &= ~(EP_STALL); } @@ -597,11 +604,11 @@ uint32_t USBD_ReadEP(uint32_t EPNum, U8 *pData, uint32_t size) /* OUT packet */ else { ptr = GetEpCmdStatPtr(EPNum); - cnt = EPBufInfo[EP_OUT_IDX(EPNum)].buf_len - ((*ptr >> 16) & 0x3FF); - dataptr = (U8 *)EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr; + cnt = EPBufInfo[EP_OUT_IDX(EPNum)].buf_len - ((*ptr & EP_NBYTES_MASK) >> EP_NBYTES_SHIFT); + dataptr = (uint8_t *)EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr; - while ((timeout-- > 0) && (*ptr & BUF_ACTIVE)); //spin on the hardware until it's done - util_assert(!(*ptr & BUF_ACTIVE)); //check for timeout + while ((timeout-- > 0) && (*ptr & EP_BUF_ACTIVE)); //spin on the hardware until it's done + util_assert(!(*ptr & EP_BUF_ACTIVE)); //check for timeout if (size < cnt) { util_assert(0); @@ -616,13 +623,13 @@ uint32_t USBD_ReadEP(uint32_t EPNum, U8 *pData, uint32_t size) *ptr = N_BYTES(EPBufInfo[EP_OUT_IDX(EPNum)].buf_len) | BUF_ADDR(EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr) | - BUF_ACTIVE; + EP_BUF_ACTIVE; if (EPNum == 0) { - /* If ctrl_out_next is set then this should be a zero length */ + /* If s_read_ctrl_out_next is set then this should be a zero length */ /* data OUT packet. */ - util_assert(!ctrl_out_next || (cnt == 0)); - ctrl_out_next = 0; + util_assert(!s_read_ctrl_out_next || (cnt == 0)); + s_read_ctrl_out_next = 0; if (USBHSD->DEVCMDSTAT & USBHSD_DEVCMDSTAT_SETUP_MASK) { // A setup packet is still pending so trigger another interrupt USBHSD->INTSETSTAT |= USBHSD_INTSETSTAT_EP_SET_INT(0); @@ -644,7 +651,7 @@ uint32_t USBD_ReadEP(uint32_t EPNum, U8 *pData, uint32_t size) * Return Value: Number of bytes written */ -uint32_t USBD_WriteEP(uint32_t EPNum, U8 *pData, uint32_t cnt) +uint32_t USBD_WriteEP(uint32_t EPNum, uint8_t *pData, uint32_t cnt) { uint32_t i; volatile uint32_t *ptr; @@ -652,7 +659,7 @@ uint32_t USBD_WriteEP(uint32_t EPNum, U8 *pData, uint32_t cnt) ptr = GetEpCmdStatPtr(EPNum); EPNum &= ~0x80; - while (*ptr & BUF_ACTIVE); + while (*ptr & EP_BUF_ACTIVE); *ptr &= ~(0x3FFFFFF); *ptr |= BUF_ADDR(EPBufInfo[EP_IN_IDX(EPNum)].buf_ptr) | @@ -668,7 +675,7 @@ uint32_t USBD_WriteEP(uint32_t EPNum, U8 *pData, uint32_t cnt) return (0); } - *ptr |= BUF_ACTIVE; + *ptr |= EP_BUF_ACTIVE; return (cnt); } @@ -816,7 +823,7 @@ void USBD_Handler(void) if (sts & (1UL << num)) { /* Setup */ - if ((num == 0) && !ctrl_out_next && (USBHSD->DEVCMDSTAT & USBHSD_DEVCMDSTAT_SETUP_MASK)) { + if ((num == 0) && !s_read_ctrl_out_next && (USBHSD->DEVCMDSTAT & USBHSD_DEVCMDSTAT_SETUP_MASK)) { #ifdef __RTX if (USBD_RTX_EPTask[num / 2]) { From 4d3854fd5f3166539a7554de2ab51c40a0541abf Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Thu, 17 Dec 2020 18:38:58 -0600 Subject: [PATCH 132/617] LPC55xx: few more USBD fixes. --- source/hic_hal/nxp/lpc55xx/usbd_LPC55xx.c | 91 ++++++++++++----------- 1 file changed, 48 insertions(+), 43 deletions(-) diff --git a/source/hic_hal/nxp/lpc55xx/usbd_LPC55xx.c b/source/hic_hal/nxp/lpc55xx/usbd_LPC55xx.c index 7d3bc58f1..01ddbf3f5 100644 --- a/source/hic_hal/nxp/lpc55xx/usbd_LPC55xx.c +++ b/source/hic_hal/nxp/lpc55xx/usbd_LPC55xx.c @@ -35,6 +35,14 @@ // Warning: this driver does *not* correctly support either isochronous endpoints or // interrupt endpoints in rate feedback mode! +// Number of logical endpoints. +#define USBD_MAX_EPS (FSL_FEATURE_USBHSD_EP_NUM) + +// Mask for bit set on EP number to indicate IN EP. +#define USB_IN_MASK (0x80) +// Mask to extract logical EP number from physical. +#define USB_LOGICAL_EP_MASK (0x7f) + #define EP_BUF_ACTIVE (1UL << 31) #define EP_DISABLED (1UL << 30) #define EP_STALL (1UL << 29) @@ -43,7 +51,7 @@ #define EP_TYPE (1UL << 26) // 0=generic, 1=periodic #define EP_NBYTES_MASK (0x03fff800) #define EP_NBYTES_SHIFT (11) -#define EP_BUF_OFFSET_MASK (0x000003ff) +#define EP_BUF_OFFSET_MASK (0x000007ff) #define EP_BUF_OFFSET_SHIFT (0) // DEVCMDSTAT Speed field values. @@ -82,9 +90,9 @@ typedef struct BUF_INFO { EP_BUF_INFO EPBufInfo[(USBD_EP_NUM + 1) * 2]; #if defined ( __CC_ARM ) || defined (__ARMCC_VERSION) -volatile uint32_t EPList[(USBD_EP_NUM + 1) * 2] __attribute__((at(EP_LIST_BASE))); +volatile uint32_t EPList[USBD_MAX_EPS * 4] __attribute__((at(EP_LIST_BASE))); #elif defined ( __GNUC__ ) -volatile uint32_t EPList[(USBD_EP_NUM + 1) * 2] __attribute__((section(".usbram"))); +volatile uint32_t EPList[USBD_MAX_EPS * 4] __attribute__((section(".usbram"))); #else #error "Unsupported compiler!" #endif @@ -100,15 +108,18 @@ static uint32_t s_read_ctrl_out_next = 0; uint32_t *GetEpCmdStatPtr(uint32_t EPNum) { - uint32_t ptr = 0; + uint32_t *ptr = (uint32_t *)EP_LIST_BASE; + + // 4 control words per endpoint: OUT 0, OUT 1, IN 0, IN 1 + // EP0 is different but still has 4 words. + ptr += (EPNum & USB_LOGICAL_EP_MASK) * 4; - if (EPNum & 0x80) { - EPNum &= ~0x80; - ptr = 8; + // For IN endpoints, + if (EPNum & USB_IN_MASK) { + ptr += 2; } - ptr += EP_LIST_BASE + EPNum * 16; - return ((uint32_t *)ptr); + return ptr; } @@ -190,8 +201,9 @@ void NO_OPTIMIZE_INLINE USBD_Reset(void) uint32_t *ptr; s_next_ep_buf_addr = EP1_BUF_BASE; - for (i = 2; i < (5 * 4); i++) { - EPList[i] = (1UL << 30); /* EPs disabled */ + // Disable all EPs. + for (i = 0; i < sizeof(EPList) / sizeof(uint32_t); i++) { + EPList[i] = EP_DISABLED; } s_read_ctrl_out_next = 0; @@ -320,12 +332,12 @@ void USBD_ConfigEP(USB_ENDPOINT_DESCRIPTOR *pEPD) type = pEPD->bmAttributes & USB_ENDPOINT_TYPE_MASK; /* IN EPs */ - if (num & 0x80) { - num &= ~0x80; + if (num & USB_IN_MASK) { + num &= ~USB_IN_MASK; EPBufInfo[EP_IN_IDX(num)].buf_len = val; EPBufInfo[EP_IN_IDX(num)].buf_ptr = s_next_ep_buf_addr; s_next_ep_buf_addr += ROUND_UP(val, MIN_BUF_SIZE); /* calc new free buffer address */ - ptr = GetEpCmdStatPtr(num | 0x80); + ptr = GetEpCmdStatPtr(num | USB_IN_MASK); *ptr = EP_DISABLED; if (type == USB_ENDPOINT_TYPE_INTERRUPT) { @@ -383,8 +395,8 @@ void USBD_EnableEP(uint32_t EPNum) ptr = GetEpCmdStatPtr(EPNum); /* IN EP */ - if (EPNum & 0x80) { - EPNum &= ~0x80; + if (EPNum & USB_IN_MASK) { + EPNum &= ~USB_IN_MASK; *ptr &= ~EP_DISABLED; USBHSD->INTSTAT = (1 << EP_IN_IDX(EPNum)); USBHSD->INTEN |= (1 << EP_IN_IDX(EPNum)); @@ -414,8 +426,8 @@ void USBD_DisableEP(uint32_t EPNum) ptr = GetEpCmdStatPtr(EPNum); *ptr = EP_DISABLED; - if (EPNum & 0x80) { - EPNum &= ~0x80; + if (EPNum & USB_IN_MASK) { + EPNum &= ~USB_IN_MASK; USBHSD->INTEN &= ~(1 << EP_IN_IDX(EPNum)); } else { @@ -453,14 +465,14 @@ void USBD_SetStallEP(uint32_t EPNum) uint32_t *ptr; ptr = GetEpCmdStatPtr(EPNum); - if (EPNum & 0x7F) { + if (EPNum & USB_LOGICAL_EP_MASK) { if (*ptr & EP_BUF_ACTIVE) { *ptr &= ~(EP_BUF_ACTIVE); } } else { - if (EPNum & 0x80) { - EPNum &= ~0x80; + if (EPNum & USB_IN_MASK) { + EPNum &= ~USB_IN_MASK; USBHSD->EPSKIP |= (1 << EP_IN_IDX(EPNum)); while (USBHSD->EPSKIP & (1 << EP_IN_IDX(EPNum))); @@ -472,7 +484,7 @@ void USBD_SetStallEP(uint32_t EPNum) } } - if ((EPNum & 0x7F) == 0) { + if ((EPNum & USB_LOGICAL_EP_MASK) == 0) { /* Endpoint is stalled so control out won't be next */ s_read_ctrl_out_next = 0; } @@ -494,7 +506,7 @@ void USBD_ClrStallEP(uint32_t EPNum) uint32_t *ptr; ptr = GetEpCmdStatPtr(EPNum); - if (EPNum & 0x80) { + if (EPNum & USB_IN_MASK) { *ptr &= ~EP_STALL; } else { @@ -519,8 +531,8 @@ void USBD_ClearEPBuf(uint32_t EPNum) uint32_t cnt, i; uint8_t *dataptr; - if (EPNum & 0x80) { - EPNum &= ~0x80; + if (EPNum & USB_IN_MASK) { + EPNum &= ~USB_IN_MASK; dataptr = (uint8_t *)EPBufInfo[EP_IN_IDX(EPNum)].buf_ptr; cnt = EPBufInfo[EP_IN_IDX(EPNum)].buf_len; @@ -566,10 +578,7 @@ uint32_t USBD_ReadEP(uint32_t EPNum, uint8_t *pData, uint32_t size) } dataptr = (uint8_t *)(EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr + EP0_SETUP_BUF_OFFSET * USBD_MAX_PACKET0); - - for (i = 0; i < cnt; i++) { - pData[i] = dataptr[i]; - } + memcpy(pData, dataptr, cnt); // Copy the SETUP packet into a struct we can read from more understandably. USB_SETUP_PACKET setup; @@ -615,11 +624,9 @@ uint32_t USBD_ReadEP(uint32_t EPNum, uint8_t *pData, uint32_t size) cnt = size; } - cnt = cnt < size ? cnt : size; + cnt = MIN(cnt, size); - for (i = 0; i < cnt; i++) { - pData[i] = dataptr[i]; - } + memcpy(pData, dataptr, cnt); *ptr = N_BYTES(EPBufInfo[EP_OUT_IDX(EPNum)].buf_len) | BUF_ADDR(EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr) | @@ -657,19 +664,17 @@ uint32_t USBD_WriteEP(uint32_t EPNum, uint8_t *pData, uint32_t cnt) volatile uint32_t *ptr; uint32_t *dataptr; ptr = GetEpCmdStatPtr(EPNum); - EPNum &= ~0x80; + EPNum &= ~USB_IN_MASK; while (*ptr & EP_BUF_ACTIVE); - *ptr &= ~(0x3FFFFFF); - *ptr |= BUF_ADDR(EPBufInfo[EP_IN_IDX(EPNum)].buf_ptr) | - N_BYTES(cnt); - dataptr = (uint32_t *)EPBufInfo[EP_IN_IDX(EPNum)].buf_ptr; + uint32_t cmdstat = *ptr; + cmdstat &= ~(EP_NBYTES_MASK | EP_BUF_OFFSET_MASK); + cmdstat |= BUF_ADDR(EPBufInfo[EP_IN_IDX(EPNum)].buf_ptr) | N_BYTES(cnt); + *ptr = cmdstat; - for (i = 0; i < (cnt + 3) / 4; i++) { - dataptr[i] = __UNALIGNED_UINT32_READ(pData); - pData += 4; - } + dataptr = (uint32_t *)EPBufInfo[EP_IN_IDX(EPNum)].buf_ptr; + memcpy(dataptr, pData, cnt); if (EPNum && (*ptr & EP_STALL)) { return (0); @@ -813,7 +818,7 @@ void USBD_Handler(void) } /* EndPoint Interrupt */ - if (sts & 0x3FF) { + if (sts & USBHSD_INTEN_EP_INT_EN_MASK) { const uint32_t endpoint_count = ((USBD_EP_NUM + 1) * 2); for (i = 0; i < endpoint_count; i++) { From b14e642440a61cbaaf2238d4d1027d1700749cd5 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Tue, 15 Dec 2020 15:47:11 -0600 Subject: [PATCH 133/617] LPC55xx: customized USB product strings for bl and if. --- projects.yaml | 1 + records/board/lpc55s69_bl.yaml | 2 ++ records/board/lpc55s69_if.yaml | 3 +++ 3 files changed, 6 insertions(+) create mode 100644 records/board/lpc55s69_if.yaml diff --git a/projects.yaml b/projects.yaml index 2d49fad2f..6d67eea00 100644 --- a/projects.yaml +++ b/projects.yaml @@ -135,6 +135,7 @@ projects: lpc55s69_if: - *module_if - *module_hic_lpc55s69 + - records/board/lpc55s69_if.yaml # Sets the USB product string. - records/family/all_family.yaml max32620_bl: - *module_bl diff --git a/records/board/lpc55s69_bl.yaml b/records/board/lpc55s69_bl.yaml index c32f125ea..752db6eb8 100644 --- a/records/board/lpc55s69_bl.yaml +++ b/records/board/lpc55s69_bl.yaml @@ -1,4 +1,6 @@ common: + macros: + - USB_PROD_STR="LPC55xx DAPLink Bootloader" sources: board: - source/board/lpc55s69_bl.c diff --git a/records/board/lpc55s69_if.yaml b/records/board/lpc55s69_if.yaml new file mode 100644 index 000000000..9a4d6008c --- /dev/null +++ b/records/board/lpc55s69_if.yaml @@ -0,0 +1,3 @@ +common: + macros: + - USB_PROD_STR="LPC55xx DAPLink CMSIS-DAP" From 5a834ea125c0f53bb57365cf875253a0b14a6d0c Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Tue, 15 Dec 2020 15:48:14 -0600 Subject: [PATCH 134/617] LPC55xx: update info.py. --- test/info.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/test/info.py b/test/info.py index 7b948ca5e..3c5290a1f 100644 --- a/test/info.py +++ b/test/info.py @@ -139,6 +139,7 @@ ('max32625_if', False, 0x0000, "bin" ), ('sam3u2c_if', False, 0x0000, "bin" ), ('stm32f103xb_if', False, 0x0000, "bin" ), + ('lpc55s69_if', False, 0x10000, "bin" ), } # Add new HICs here @@ -314,6 +315,7 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y 'k26f': 0x97969909, 'kl27z': 0x9796990B, 'm48ssidae': 0x97969921, + 'lpc55s69': 0x4C504355, } BOARD_ID_LOCKED_WHEN_ERASED = set([ From ffcabd9afac50281f6ce3a18dd0bc29c2e4aa993 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Wed, 16 Dec 2020 12:45:11 -0600 Subject: [PATCH 135/617] LPC55xx: initial IO implementation. - Implemented gpio.c. - Updated IO_Config.h and added mask macros. - Implemented DAP_config.h. --- source/hic_hal/nxp/lpc55xx/DAP_config.h | 162 ++++++++++++------------ source/hic_hal/nxp/lpc55xx/IO_Config.h | 70 +++++++--- source/hic_hal/nxp/lpc55xx/gpio.c | 120 ++++-------------- 3 files changed, 156 insertions(+), 196 deletions(-) diff --git a/source/hic_hal/nxp/lpc55xx/DAP_config.h b/source/hic_hal/nxp/lpc55xx/DAP_config.h index 7076f360b..4a11a936c 100644 --- a/source/hic_hal/nxp/lpc55xx/DAP_config.h +++ b/source/hic_hal/nxp/lpc55xx/DAP_config.h @@ -23,6 +23,7 @@ #define __DAP_CONFIG_H__ #include "IO_Config.h" +#include "fsl_iocon.h" //************************************************************************************************** /** @@ -169,6 +170,20 @@ Configures the DAP Hardware I/O pins for JTAG mode: */ __STATIC_INLINE void PORT_JTAG_SETUP(void) { + // Drive SWCLK, SWDIO, SWDIO_TXEN, nRESET, nRESET_TXEN high. + GPIO->SET[PIN_PIO_PORT] = PIN_TCK_SWCLK_MASK + | PIN_TMS_SWDIO_MASK + | PIN_TMS_SWDIO_TXEN_MASK + | PIN_TDI_MASK + | PIN_RESET_MASK + | PIN_RESET_TXEN_MASK; + + // Set SWCLK and SWDIO to outputs. + GPIO->DIRSET[PIN_PIO_PORT] = PIN_TCK_SWCLK_MASK | PIN_TMS_SWDIO_MASK; + + // Switch TDO_SWO to GPIO input. + IOCON->PIO[PIN_PIO_PORT][PIN_TDO_SWO] = IOCON_FUNC0 | IOCON_DIGITAL_EN; + GPIO->DIRCLR[PIN_PIO_PORT] = PIN_TDO_SWO; } /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET. @@ -178,15 +193,22 @@ Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: */ __STATIC_INLINE void PORT_SWD_SETUP(void) { -// PIN_SWCLK_GPIO->PSOR = 1 << PIN_SWCLK_BIT; -// PIN_SWDIO_OUT_GPIO->PSOR = 1 << PIN_SWDIO_OUT_BIT; -// PIN_SWDIO_OE_GPIO->PSOR = 1 << PIN_SWDIO_OE_BIT; -// PIN_SWD_OE_GPIO->PSOR = 1 << PIN_SWD_OE_BIT; -// PIN_nRESET_GPIO->PSOR = 1 << PIN_nRESET_BIT; -// PIN_SWD_OE_GPIO->PDDR = PIN_SWD_OE_GPIO->PDDR | (1 << PIN_SWD_OE_BIT); -// PIN_nRESET_GPIO->PSOR = PIN_nRESET; -// PIN_nRESET_GPIO->PDDR |= PIN_nRESET; //output -// PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_MUX(1); + // Drive SWCLK, SWDIO, SWDIO_TXEN, nRESET, nRESET_TXEN high. + GPIO->SET[PIN_PIO_PORT] = PIN_TCK_SWCLK_MASK + | PIN_TMS_SWDIO_MASK + | PIN_TMS_SWDIO_TXEN_MASK + | PIN_RESET_MASK + | PIN_RESET_TXEN_MASK; + + + // Set SWCLK and SWDIO to outputs. + GPIO->DIRSET[PIN_PIO_PORT] = PIN_TCK_SWCLK_MASK | PIN_TMS_SWDIO_MASK; + + // Disable TDI (set to input). + GPIO->DIRCLR[PIN_PIO_PORT] = PIN_TDI_MASK; + + // Switch TDO_SWO to Flexcomm. + IOCON->PIO[PIN_PIO_PORT][PIN_TDO_SWO] = IOCON_FUNC1 | IOCON_DIGITAL_EN; } /** Disable JTAG/SWD I/O Pins. @@ -195,12 +217,15 @@ Disables the DAP Hardware I/O pins which configures: */ __STATIC_INLINE void PORT_OFF(void) { -// PIN_SWDIO_OE_GPIO->PCOR = 1 << PIN_SWDIO_OE_BIT; -// PIN_SWD_OE_GPIO->PCOR = 1 << PIN_SWD_OE_BIT; -// PIN_nRESET_GPIO->PSOR = 1 << PIN_nRESET_BIT; -// PIN_nRESET_GPIO->PDDR &= ~PIN_nRESET; //input -// PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] |= PORT_PCR_ISF_MASK; -// PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_MUX(1); + // Disable driving of SWDIO and nRESET. + GPIO->CLR[PIN_PIO_PORT] = PIN_TMS_SWDIO_TXEN_MASK + | PIN_RESET_TXEN_MASK; + + // Disable SWCLK and TDI (set to inputs). + GPIO->DIRCLR[PIN_PIO_PORT] = PIN_TCK_SWCLK_MASK | PIN_TDI_MASK; + + // Switch TDO_SWO to Flexcomm. + IOCON->PIO[PIN_PIO_PORT][PIN_TDO_SWO] = IOCON_FUNC1 | IOCON_DIGITAL_EN; } @@ -211,7 +236,7 @@ __STATIC_INLINE void PORT_OFF(void) */ __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void) { - return (0); // Not available + return GPIO->B[PIN_PIO_PORT][PIN_TCK_SWCLK]; } /** SWCLK/TCK I/O pin: Set Output to High. @@ -219,7 +244,7 @@ Set the SWCLK/TCK DAP hardware I/O pin to high level. */ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void) { -// PIN_SWCLK_GPIO->PSOR = 1 << PIN_SWCLK_BIT; + GPIO->B[PIN_PIO_PORT][PIN_TCK_SWCLK] = 1; } /** SWCLK/TCK I/O pin: Set Output to Low. @@ -227,7 +252,7 @@ Set the SWCLK/TCK DAP hardware I/O pin to low level. */ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void) { -// PIN_SWCLK_GPIO->PCOR = 1 << PIN_SWCLK_BIT; + GPIO->B[PIN_PIO_PORT][PIN_TCK_SWCLK] = 0; } @@ -238,7 +263,7 @@ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void) */ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void) { - return 0; // ((PIN_SWDIO_IN_GPIO->PDIR >> PIN_SWDIO_IN_BIT) & 1); + return GPIO->B[PIN_PIO_PORT][PIN_TMS_SWDIO]; } /** SWDIO/TMS I/O pin: Set Output to High. @@ -246,7 +271,7 @@ Set the SWDIO/TMS DAP hardware I/O pin to high level. */ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void) { -// PIN_SWDIO_OUT_GPIO->PSOR = 1 << PIN_SWDIO_OUT_BIT; + GPIO->B[PIN_PIO_PORT][PIN_TMS_SWDIO] = 1; } /** SWDIO/TMS I/O pin: Set Output to Low. @@ -254,7 +279,7 @@ Set the SWDIO/TMS DAP hardware I/O pin to low level. */ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void) { -// PIN_SWDIO_OUT_GPIO->PCOR = 1 << PIN_SWDIO_OUT_BIT; + GPIO->B[PIN_PIO_PORT][PIN_TMS_SWDIO] = 0; } /** SWDIO I/O pin: Get Input (used in SWD mode only). @@ -262,7 +287,7 @@ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void) */ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void) { - return 0; // (BITBAND_REG(PIN_SWDIO_IN_GPIO->PDIR, PIN_SWDIO_IN_BIT)); + return GPIO->B[PIN_PIO_PORT][PIN_TMS_SWDIO]; } /** SWDIO I/O pin: Set Output (used in SWD mode only). @@ -270,7 +295,7 @@ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void) */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit) { -// BITBAND_REG(PIN_SWDIO_OUT_GPIO->PDOR, PIN_SWDIO_OUT_BIT) = bit; + GPIO->B[PIN_PIO_PORT][PIN_TMS_SWDIO] = bit; } /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only). @@ -279,7 +304,7 @@ called prior \ref PIN_SWDIO_OUT function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void) { -// PIN_SWDIO_OE_GPIO->PSOR = 1 << PIN_SWDIO_OE_BIT; + GPIO->DIRSET[PIN_PIO_PORT] = PIN_TMS_SWDIO_MASK; } /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). @@ -288,7 +313,7 @@ called prior \ref PIN_SWDIO_IN function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void) { -// PIN_SWDIO_OE_GPIO->PCOR = 1 << PIN_SWDIO_OE_BIT; + GPIO->DIRCLR[PIN_PIO_PORT] = PIN_TMS_SWDIO_MASK; } @@ -299,7 +324,7 @@ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void) */ __STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void) { - return (0); // Not available + return GPIO->B[PIN_PIO_PORT][PIN_TDI]; } /** TDI I/O pin: Set Output. @@ -307,7 +332,7 @@ __STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void) */ __STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit) { - ; // Not available + GPIO->B[PIN_PIO_PORT][PIN_TDI] = bit; } @@ -318,7 +343,7 @@ __STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit) */ __STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void) { - return (0); // Not available + return GPIO->B[PIN_PIO_PORT][PIN_TDO_SWO]; } @@ -349,7 +374,7 @@ __STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit) */ __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void) { - return 0; //((PIN_nRESET_GPIO->PDIR >> PIN_nRESET_BIT) & 1); + return GPIO->B[PIN_PIO_PORT][PIN_RESET]; } /** nRESET I/O pin: Set Output. @@ -359,7 +384,7 @@ __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void) */ __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit) { -// BITBAND_REG(PIN_nRESET_GPIO->PDOR, PIN_nRESET_BIT) = bit; + GPIO->B[PIN_PIO_PORT][PIN_RESET] = bit; } ///@} @@ -442,63 +467,32 @@ Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled an */ __STATIC_INLINE void DAP_SETUP(void) { -// SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK | /* Enable Port A Clock */ -// SIM_SCGC5_PORTB_MASK | /* Enable Port B Clock */ -// SIM_SCGC5_PORTC_MASK | /* Enable Port C Clock */ -// SIM_SCGC5_PORTD_MASK; /* Enable Port D Clock */ -// /* Configure I/O pin SWCLK */ -// PIN_SWCLK_PORT->PCR[PIN_SWCLK_BIT] = PORT_PCR_MUX(1) | /* GPIO */ -// PORT_PCR_DSE_MASK; /* High drive strength */ -// PIN_SWCLK_GPIO->PSOR = 1 << PIN_SWCLK_BIT; /* High level */ -// PIN_SWCLK_GPIO->PDDR |= 1 << PIN_SWCLK_BIT; /* Output */ -// /* Configure I/O pin SWDIO_OUT */ -// PIN_SWDIO_OUT_PORT->PCR[PIN_SWDIO_OUT_BIT] = PORT_PCR_MUX(1) | /* GPIO */ -// PORT_PCR_DSE_MASK; /* High drive strength */ -// PIN_SWDIO_OUT_GPIO->PSOR = 1 << PIN_SWDIO_OUT_BIT; /* High level */ -// PIN_SWDIO_OUT_GPIO->PDDR |= 1 << PIN_SWDIO_OUT_BIT; /* Output */ -// /* Configure I/O pin SWDIO_IN */ -// PIN_SWDIO_IN_PORT->PCR[PIN_SWDIO_IN_BIT] = PORT_PCR_MUX(1) | /* GPIO */ -// PORT_PCR_PE_MASK | /* Pull enable */ -// PORT_PCR_PS_MASK; /* Pull-up */ -// PIN_SWDIO_IN_GPIO->PDDR &= ~(1 << PIN_SWDIO_IN_BIT); /* Input */ -// /* Configure I/O pin SWDIO_OE */ -// PIN_SWDIO_OE_PORT->PCR[PIN_SWDIO_OE_BIT] = PORT_PCR_MUX(1) | /* GPIO */ -// PORT_PCR_DSE_MASK; /* High drive strength */ -// PIN_SWDIO_OE_GPIO->PCOR = 1 << PIN_SWDIO_OE_BIT; /* Low level */ -// PIN_SWDIO_OE_GPIO->PDDR |= 1 << PIN_SWDIO_OE_BIT; /* Output */ -// /* Configure I/O pin SWD_OE */ -// PIN_SWD_OE_PORT->PCR[PIN_SWD_OE_BIT] = PORT_PCR_MUX(1) | /* GPIO */ -// PORT_PCR_DSE_MASK; /* High drive strength */ -// PIN_SWD_OE_GPIO->PCOR = 1 << PIN_SWD_OE_BIT; /* Low level */ -// PIN_SWD_OE_GPIO->PDDR |= 1 << PIN_SWD_OE_BIT; /* Output */ -// /* Configure I/O pin nRESET */ -// PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_MUX(1) | /* GPIO */ -// PORT_PCR_PE_MASK | /* Pull enable */ -// PORT_PCR_PS_MASK | /* Pull-up */ -// PORT_PCR_ODE_MASK; /* Open-drain */ -// PIN_nRESET_GPIO->PSOR = 1 << PIN_nRESET_BIT; /* High level */ -// PIN_nRESET_GPIO->PDDR &= ~(1 << PIN_nRESET_BIT); /* Input */ -// // Configure I/O pin LVLRST_EN -// // The nRESET level translator is enabled by default. The translator is auto- -// // direction sensing. So as long as we don't drive nRESET from our side, we won't -// // interfere with another debug probe connected to the target SWD header. -// PIN_nRESET_EN_PORT->PCR[PIN_nRESET_EN_BIT] = PORT_PCR_MUX(1) | /* GPIO */ -// PORT_PCR_ODE_MASK; /* Open-drain */ -// PIN_nRESET_EN_GPIO->PSOR = PIN_nRESET_EN; /* High level */ -// PIN_nRESET_EN_GPIO->PDDR |= PIN_nRESET_EN; /* Output */ -// /* Configure LED */ -// LED_CONNECTED_PORT->PCR[LED_CONNECTED_BIT] = PORT_PCR_MUX(1) | /* GPIO */ -// PORT_PCR_ODE_MASK; /* Open-drain */ -// LED_CONNECTED_GPIO->PCOR = 1 << LED_CONNECTED_BIT; /* Turned on */ -// LED_CONNECTED_GPIO->PDDR |= 1 << LED_CONNECTED_BIT; /* Output */ - - - // Enable clocks. + // Ensure clocks are enabled. SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_IOCON_MASK | SYSCON_AHBCLKCTRL0_GPIO0_MASK; - - + // Configure pins. + static const iocon_group_t kPinConfigs[] = { + { .port = PIN_PIO_PORT, .pin = PIN_TCK_SWCLK, .modefunc = IOCON_FUNC0 | IOCON_DIGITAL_EN | IOCON_SLEW_FAST, }, + { .port = PIN_PIO_PORT, .pin = PIN_TMS_SWDIO, .modefunc = IOCON_FUNC0 | IOCON_DIGITAL_EN | IOCON_SLEW_FAST, }, + { .port = PIN_PIO_PORT, .pin = PIN_TMS_SWDIO_TXEN, .modefunc = IOCON_FUNC0 | IOCON_DIGITAL_EN | IOCON_SLEW_FAST, }, + { .port = PIN_PIO_PORT, .pin = PIN_TDI, .modefunc = IOCON_FUNC0 | IOCON_DIGITAL_EN | IOCON_SLEW_FAST, }, + { .port = PIN_PIO_PORT, .pin = PIN_TDO_SWO, .modefunc = IOCON_FUNC0 | IOCON_DIGITAL_EN, }, + { .port = PIN_PIO_PORT, .pin = PIN_RESET, .modefunc = IOCON_FUNC0 | IOCON_DIGITAL_EN, }, + { .port = PIN_PIO_PORT, .pin = PIN_RESET_TXEN, .modefunc = IOCON_FUNC0 | IOCON_GPIO_MODE | IOCON_DIGITAL_EN, }, + { .port = PIN_PIO_PORT, .pin = PIN_DETECT, .modefunc = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN, }, + { .port = PIN_PIO_PORT, .pin = PIN_HW_VERS_6, .modefunc = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN, }, + { .port = PIN_PIO_PORT, .pin = PIN_HW_VERS_7, .modefunc = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN, }, + }; + + IOCON_SetPinMuxing(IOCON, kPinConfigs, ARRAY_SIZE(kPinConfigs)); + + // Configure GPIO outputs. + GPIO->CLR[PIN_PIO_PORT] = PIN_TMS_SWDIO_TXEN_MASK + | PIN_RESET_TXEN_MASK; + + GPIO->DIRSET[PIN_PIO_PORT] = PIN_TMS_SWDIO_TXEN_MASK + | PIN_RESET_TXEN_MASK; } /** Reset Target Device with custom specific I/O pin or command sequence. diff --git a/source/hic_hal/nxp/lpc55xx/IO_Config.h b/source/hic_hal/nxp/lpc55xx/IO_Config.h index 112cb901b..64d4e4bac 100644 --- a/source/hic_hal/nxp/lpc55xx/IO_Config.h +++ b/source/hic_hal/nxp/lpc55xx/IO_Config.h @@ -30,60 +30,92 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC55XX); // All pins are PIO0. -#define PIN_PIO_PORT (0) +#define PIN_PIO_PORT (0U) // Debug Port I/O Pins // SWCLK Pin PIO_0 (O) -// (DBGIF_TCK_SWCLK) -#define PIN_SWCLK_BIT (0) +#define PIN_TCK_SWCLK (0U) +#define PIN_TCK_SWCLK_MASK (1U << PIN_TCK_SWCLK) // SWDIO I/O Pin PIO0_2 (IO) -// (DBGIF_TMS_SWDIO) -#define PIN_SWDIO_OUT_BIT (2) +// port always has pull-down and digital input (DIGIMODE) enabled (UM11126, section 15.5.1, table 312) +#define PIN_TMS_SWDIO (2U) +#define PIN_TMS_SWDIO_MASK (1U << PIN_TMS_SWDIO) // SWDIO Output Enable Pin PIO0_28 (O) // (DBGIF_TMS_SWDIO_TXEN) -#define PIN_SWDIO_OE_BIT (28) +#define PIN_TMS_SWDIO_TXEN (28U) +#define PIN_TMS_SWDIO_TXEN_MASK (1U << PIN_TMS_SWDIO_TXEN) // TDI Output Pin PIO0_1 (O) // (DBGIF_TDI) -#define PIN_TDI_BIT (1) +#define PIN_TDI (1U) +#define PIN_TDI_MASK (1U << PIN_TDI) // TDO/SWO Input Pin PIO0_3 (I) // (DBGIF_TDO_SWO) // SWO = function 1 (FC3_RXD_SDA_MOSI_DATA) -#define PIN_SWO_RX_BIT (3) +#define PIN_TDO_SWO (3U) +#define PIN_TDO_SWO_MASK (1U << PIN_TDO_SWO) // nRESET Pin PIO0_19 (O) // (DBGIF_RESET) -#define PIN_RESET_BIT (19) -#define PIN_RESET (1 << PIN_RESET_BIT) +#define PIN_RESET (19U) +#define PIN_RESET_MASK (1U << PIN_RESET) // nRESET Pin Output Enable PIO0_13 (O) // (DBGIF_RESET_TXEN) -#define PIN_RESET_EN_BIT (13) -#define PIN_RESET_EN (1 << PIN_RESET_EN_BIT) +// type I pin, combo I2C/IO +// must set EGP to put pin in GPIO mode +#define PIN_RESET_TXEN (13U) +#define PIN_RESET_TXEN_MASK (1U << PIN_RESET_TXEN) // SWD Detect Pin PIO0_22 (I, pullup) // (DBGIF_DETECT) -#define PIN_SWD_DETECT_BIT (22) -#define PIN_SWD_DETECT (1 << PIN_SWD_DETECT_BIT) +#define PIN_DETECT (22U) +#define PIN_DETECT_MASK (1U << PIN_DETECT) + +// HW Version 6 Pin PIO0_18 (I, pullup) +// (HW_VERS_6) +#define PIN_HW_VERS_6 (18U) +#define PIN_HW_VERS_6_MASK (1U << PIN_HW_VERS_6) + +// HW Version 7 Pin PIO0_27 (I, pullup) +// (HW_VERS_7) +#define PIN_HW_VERS_7 (27U) +#define PIN_HW_VERS_7_MASK (1U << PIN_HW_VERS_7) + +// SWD Detect Pin PIO0_31 (A) +// (DBGIF_VREF) +// analog input = 1/2 target VREF +#define PIN_VREF (31U) +#define PIN_VREF_MASK (1U << PIN_VREF) // UART -// RX = PIO0_24, function 1 (FC0_RXD_SDA_MOSI_DATA) -// TX = PIO0_25, function 1 (FC0_TXD_SCL_MISO_WS) -// DBGIF_VREF = PIO0_31 (Analog input, 1/2 target VREF) +// UART Rx Pin PIO0_24 (I) +// (FC0_TARGET_RXD) +// function 1 (FC0_RXD_SDA_MOSI_DATA) +#define PIN_UART_RX (24U) +#define PIN_UART_RX_MASK (1U << PIN_UART_RX) + +// UART Tx Pin PIO0_25 (O) +// (FC0_TARGET_TXD) +// function 1 (FC0_TXD_SCL_MISO_WS) +#define PIN_UART_TX (25U) +#define PIN_UART_TX_MASK (1U << PIN_UART_TX) // Debug Unit LEDs // Connected/Activity LED PIO0_5 // (PIO0_5-ISP_EN-LED1_CTRL) -#define LED_CONNECTED_BIT (5) -#define LED_CONNECTED (1 << LED_CONNECTED_BIT) +// active low +// port always has pull-up and digital input (DIGIMODE) enabled (UM11126, section 15.5.1, table 312) +#define LED_CONNECTED (5U) +#define LED_CONNECTED_MASK (1U << LED_CONNECTED) #endif diff --git a/source/hic_hal/nxp/lpc55xx/gpio.c b/source/hic_hal/nxp/lpc55xx/gpio.c index b9d00394b..dfa98482f 100644 --- a/source/hic_hal/nxp/lpc55xx/gpio.c +++ b/source/hic_hal/nxp/lpc55xx/gpio.c @@ -26,112 +26,50 @@ #include "daplink.h" #include "hic_init.h" #include "fsl_clock.h" - -static void busy_wait(uint32_t cycles) -{ - volatile uint32_t i = cycles; - while (i > 0) { - i--; - } -} +#include "fsl_iocon.h" +#include "fsl_reset.h" void gpio_init(void) { // Enable hardfault on unaligned access for the interface only. // If this is done in the bootloader than then it might (will) break // older application firmware or firmware from 3rd party vendors. -#if defined(DAPLINK_IF) +#if defined(DAPLINK_IF) SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif -#ifdef LPC55_FIXME - // enable clock to ports - SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK; - SIM->SCGC6 |= SIM_SCGC6_DMAMUX_MASK; - // configure pin as GPIO - LED_CONNECTED_PORT->PCR[LED_CONNECTED_BIT] = PORT_PCR_MUX(1); - // led off - enable output - LED_CONNECTED_GPIO->PDOR = 1UL << LED_CONNECTED_BIT; - LED_CONNECTED_GPIO->PDDR = 1UL << LED_CONNECTED_BIT; - // led on - LED_CONNECTED_GPIO->PCOR = 1UL << LED_CONNECTED_BIT; - // reset button configured as gpio input - PIN_nRESET_GPIO->PDDR &= ~PIN_nRESET; - PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_MUX(1); - /* Enable LVLRST_EN */ - PIN_nRESET_EN_PORT->PCR[PIN_nRESET_EN_BIT] = PORT_PCR_MUX(1) | /* GPIO */ - PORT_PCR_ODE_MASK; /* Open-drain */ - PIN_nRESET_EN_GPIO->PSOR = PIN_nRESET_EN; - PIN_nRESET_EN_GPIO->PDDR |= PIN_nRESET_EN; - // Configure SWO UART RX. - PIN_SWO_RX_PORT->PCR[PIN_SWO_RX_BIT] = PORT_PCR_MUX(3); // UART1 - PIN_SWO_RX_GPIO->PDDR &= ~(1 << PIN_SWO_RX_BIT); // Input - - // Enable pulldowns on power monitor control signals to reduce power consumption. - PIN_CTRL0_PORT->PCR[PIN_CTRL0_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); - PIN_CTRL1_PORT->PCR[PIN_CTRL1_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); - PIN_CTRL2_PORT->PCR[PIN_CTRL2_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); - PIN_CTRL3_PORT->PCR[PIN_CTRL3_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); - - // Enable pulldown on GPIO0_B to prevent it floating. - PIN_GPIO0_B_PORT->PCR[PIN_GPIO0_B_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); - // configure power enable pin as GPIO - PIN_POWER_EN_PORT->PCR[PIN_POWER_EN_BIT] = PORT_PCR_MUX(1); - // set output to 0 - PIN_POWER_EN_GPIO->PCOR = PIN_POWER_EN; - // switch gpio to output - PIN_POWER_EN_GPIO->PDDR |= PIN_POWER_EN; - - // Let the voltage rails stabilize. This is especailly important - // during software resets, since the target's 3.3v rail can take - // 20-50ms to drain. During this time the target could be driving - // the reset pin low, causing the bootloader to think the reset - // button is pressed. - // Note: With optimization set to -O2 the value 1000000 delays for ~85ms - busy_wait(1000000); -#endif + // Ensure clocks are enabled. + SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_IOCON_MASK + | SYSCON_AHBCLKCTRL0_GPIO0_MASK; + SYSCON->AHBCLKCTRLSET[1] = SYSCON_AHBCLKCTRL1_FC0_MASK + | SYSCON_AHBCLKCTRL1_FC3_MASK; + + // Reset peripherals. + RESET_PeripheralReset(kIOCON_RST_SHIFT_RSTn); + RESET_PeripheralReset(kGPIO0_RST_SHIFT_RSTn); + RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn); + RESET_PeripheralReset(kFC3_RST_SHIFT_RSTn); + + // Configure pins. + IOCON->PIO[PIN_PIO_PORT][LED_CONNECTED] = IOCON_FUNC0 | IOCON_DIGITAL_EN; + + // Turn off LED. + GPIO->B[PIN_PIO_PORT][LED_CONNECTED] = 1; + // Set LED to output. + GPIO->DIRSET[PIN_PIO_PORT] = LED_CONNECTED_MASK; + // Turn on LED. + GPIO->B[PIN_PIO_PORT][LED_CONNECTED] = 1; } void gpio_set_board_power(bool powerEnabled) { -#ifdef LPC55_FIXME - if (powerEnabled) { - // enable power switch - PIN_POWER_EN_GPIO->PSOR = PIN_POWER_EN; - } - else { - // disable power switch - PIN_POWER_EN_GPIO->PCOR = PIN_POWER_EN; - } -#endif -} - -uint32_t UART1_GetFreq(void) -{ - return CLOCK_GetCoreSysClkFreq(); -} - -void UART1_InitPins(void) -{ - // RX pin inited in gpio_init(); - // TX not used. -} - -void UART1_DeinitPins(void) -{ - // No need to deinit the RX pin. - // TX not used. + // No target power control in this circuit. } void gpio_set_hid_led(gpio_led_state_t state) { -#ifdef LPC55_FIXME - if (state) { - LED_CONNECTED_GPIO->PCOR = LED_CONNECTED; // LED on - } else { - LED_CONNECTED_GPIO->PSOR = LED_CONNECTED; // LED off - } -#endif + // LED is active low, so set to inverse of the enum value. + GPIO->B[PIN_PIO_PORT][LED_CONNECTED] = !(uint8_t)state; } void gpio_set_cdc_led(gpio_led_state_t state) @@ -146,11 +84,7 @@ void gpio_set_msc_led(gpio_led_state_t state) uint8_t gpio_get_reset_btn_no_fwrd(void) { -#ifdef LPC55_FIXME - return (PIN_nRESET_GPIO->PDIR & PIN_nRESET) ? 0 : 1; -#else return 0; -#endif } uint8_t gpio_get_reset_btn_fwrd(void) From 059108fde42e303423568759bbf481c7392929b5 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Wed, 16 Dec 2020 13:52:58 -0600 Subject: [PATCH 136/617] LPC55xx: enable CM33 support in RTX5. --- projects.yaml | 2 +- records/hic_hal/lpc55s69.yaml | 4 ++-- records/rtos/rtos-cm33.yaml | 36 +++++++++++++++++++++++++++++++++++ 3 files changed, 39 insertions(+), 3 deletions(-) create mode 100644 records/rtos/rtos-cm33.yaml diff --git a/projects.yaml b/projects.yaml index 6d67eea00..0a5199cf8 100644 --- a/projects.yaml +++ b/projects.yaml @@ -63,7 +63,7 @@ module: - records/hic_hal/lpc4322.yaml - records/usb/usb-bulk.yaml hic_lpc55s69: &module_hic_lpc55s69 - - records/rtos/rtos-cm3.yaml + - records/rtos/rtos-cm33.yaml - records/hic_hal/lpc55s69.yaml - records/usb/usb-bulk.yaml hic_sam3u2c: &module_hic_sam3u2c diff --git a/records/hic_hal/lpc55s69.yaml b/records/hic_hal/lpc55s69.yaml index 0a4bca259..be71aec54 100644 --- a/records/hic_hal/lpc55s69.yaml +++ b/records/hic_hal/lpc55s69.yaml @@ -36,7 +36,7 @@ tool_specific: hic_hal: - source/hic_hal/nxp/lpc55xx/armcc - source/hic_hal/nxp/lpc55xx/LPC55S69/armcc/keil_lib_power_cm33_core0.lib - make_armcc: + armcc: misc: ld_flags: - --predefine="-Isource/hic_hal/nxp/lpc55xx" @@ -53,7 +53,7 @@ tool_specific: hic_hal: - source/hic_hal/nxp/lpc55xx/armcc - source/hic_hal/nxp/lpc55xx/LPC55S69/armcc/keil_lib_power_cm33_core0.lib - make_gcc_arm: + gcc_arm: misc: c_flags: - -march=armv8-m.main+fp+dsp diff --git a/records/rtos/rtos-cm33.yaml b/records/rtos/rtos-cm33.yaml new file mode 100644 index 000000000..4a9105b80 --- /dev/null +++ b/records/rtos/rtos-cm33.yaml @@ -0,0 +1,36 @@ +common: + macros: + - OS_TICK=10000 + includes: + - source/rtos2/Include + - source/rtos2/RTX/Include + - source/rtos2/RTX/Config + sources: + rtos: + - source/rtos2/RTX/Config/RTX_Config.c + - source/rtos2/RTX/Source/rtx_delay.c + - source/rtos2/RTX/Source/rtx_evr.c + - source/rtos2/RTX/Source/rtx_kernel.c + - source/rtos2/RTX/Source/rtx_lib.c + - source/rtos2/RTX/Source/rtx_memory.c + - source/rtos2/RTX/Source/rtx_mempool.c + - source/rtos2/RTX/Source/rtx_msgqueue.c + - source/rtos2/RTX/Source/rtx_mutex.c + - source/rtos2/RTX/Source/rtx_system.c + - source/rtos2/RTX/Source/rtx_thread.c + - source/rtos2/RTX/Source/rtx_timer.c + - source/rtos2/Source/os_systick.c + +# Note: For armcc, do not use NS version! We don't want the TZ context support. +tool_specific: + uvision: + sources: + rtos: + - source/rtos2/RTX/Source/ARM/irq_armv8mml.s + armcc: + sources: + rtos: + - source/rtos2/RTX/Source/ARM/irq_armv8mml.s + gcc_arm: + sources: + - source/rtos2/RTX/Source/GCC/irq_armv8mml.S From b907677af83b54b78aee5014447385c9ffbbe922 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Thu, 17 Dec 2020 11:58:45 -0600 Subject: [PATCH 137/617] LPC55xx: correct initial EXC_RETURN for v8-M NS. --- source/rtos2/RTX/Source/rtx_core_cm.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/source/rtos2/RTX/Source/rtx_core_cm.h b/source/rtos2/RTX/Source/rtx_core_cm.h index 9bd0c8867..b24e7fd45 100644 --- a/source/rtos2/RTX/Source/rtx_core_cm.h +++ b/source/rtos2/RTX/Source/rtx_core_cm.h @@ -89,6 +89,11 @@ __STATIC_INLINE uint32_t xPSR_InitVal (bool_t privileged, bool_t thumb) { /// Stack Frame Initialization Value (EXC_RETURN[7..0]) #if (DOMAIN_NS == 1) #define STACK_FRAME_INIT_VAL 0xBCU +// --- Begin DAPLink change +// - Change EXC_RETURN.ES and .S to 0 (NS) +#elif (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) +#define STACK_FRAME_INIT_VAL 0xBCU +// --- End DAPLink change #else #define STACK_FRAME_INIT_VAL 0xFDU #endif From ccbcf3726f4dd78ce0f823baf43948bba4a12dc0 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Fri, 18 Dec 2020 19:04:30 -0600 Subject: [PATCH 138/617] LPC55xx: working DAP_config.h. --- source/hic_hal/nxp/lpc55xx/DAP_config.h | 132 +++++++++++++++++------- 1 file changed, 94 insertions(+), 38 deletions(-) diff --git a/source/hic_hal/nxp/lpc55xx/DAP_config.h b/source/hic_hal/nxp/lpc55xx/DAP_config.h index 4a11a936c..7cb5c51ff 100644 --- a/source/hic_hal/nxp/lpc55xx/DAP_config.h +++ b/source/hic_hal/nxp/lpc55xx/DAP_config.h @@ -170,20 +170,20 @@ Configures the DAP Hardware I/O pins for JTAG mode: */ __STATIC_INLINE void PORT_JTAG_SETUP(void) { - // Drive SWCLK, SWDIO, SWDIO_TXEN, nRESET, nRESET_TXEN high. - GPIO->SET[PIN_PIO_PORT] = PIN_TCK_SWCLK_MASK - | PIN_TMS_SWDIO_MASK - | PIN_TMS_SWDIO_TXEN_MASK - | PIN_TDI_MASK - | PIN_RESET_MASK - | PIN_RESET_TXEN_MASK; + // Ground DETECT. + GPIO->B[PIN_PIO_PORT][PIN_DETECT] = 0; - // Set SWCLK and SWDIO to outputs. - GPIO->DIRSET[PIN_PIO_PORT] = PIN_TCK_SWCLK_MASK | PIN_TMS_SWDIO_MASK; + // Set TCK, TMS, TDI GPIO outputs to high. + GPIO->SET[PIN_PIO_PORT] = PIN_TCK_SWCLK_MASK | PIN_TMS_SWDIO_MASK | PIN_TDI_MASK; - // Switch TDO_SWO to GPIO input. + // Switch TCK, TMS, TDI to outputs. + GPIO->DIRSET[PIN_PIO_PORT] = PIN_TCK_SWCLK_MASK | PIN_TMS_SWDIO_MASK | PIN_TDI_MASK; + + // Switch TDO_SWO to GPIO input (TDO). IOCON->PIO[PIN_PIO_PORT][PIN_TDO_SWO] = IOCON_FUNC0 | IOCON_DIGITAL_EN; - GPIO->DIRCLR[PIN_PIO_PORT] = PIN_TDO_SWO; + + // Enable TMS translator output. + GPIO->B[PIN_PIO_PORT][PIN_TMS_SWDIO_TXEN] = 1; } /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET. @@ -193,21 +193,22 @@ Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: */ __STATIC_INLINE void PORT_SWD_SETUP(void) { - // Drive SWCLK, SWDIO, SWDIO_TXEN, nRESET, nRESET_TXEN high. - GPIO->SET[PIN_PIO_PORT] = PIN_TCK_SWCLK_MASK - | PIN_TMS_SWDIO_MASK - | PIN_TMS_SWDIO_TXEN_MASK - | PIN_RESET_MASK - | PIN_RESET_TXEN_MASK; + // Ground DETECT. + GPIO->B[PIN_PIO_PORT][PIN_DETECT] = 0; + // Set SWCLK and SWDIO GPIO outputs to high before enabling the translator. + GPIO->SET[PIN_PIO_PORT] = PIN_TCK_SWCLK_MASK | PIN_TMS_SWDIO_MASK; // Set SWCLK and SWDIO to outputs. GPIO->DIRSET[PIN_PIO_PORT] = PIN_TCK_SWCLK_MASK | PIN_TMS_SWDIO_MASK; - // Disable TDI (set to input). + // Set TDI to input. GPIO->DIRCLR[PIN_PIO_PORT] = PIN_TDI_MASK; - // Switch TDO_SWO to Flexcomm. + // Enable SWDIO translator output. + GPIO->B[PIN_PIO_PORT][PIN_TMS_SWDIO_TXEN] = 1; + + // Switch TDO_SWO to Flexcomm (SWO) IOCON->PIO[PIN_PIO_PORT][PIN_TDO_SWO] = IOCON_FUNC1 | IOCON_DIGITAL_EN; } @@ -224,8 +225,11 @@ __STATIC_INLINE void PORT_OFF(void) // Disable SWCLK and TDI (set to inputs). GPIO->DIRCLR[PIN_PIO_PORT] = PIN_TCK_SWCLK_MASK | PIN_TDI_MASK; - // Switch TDO_SWO to Flexcomm. + // Switch TDO_SWO to Flexcomm (SWO). IOCON->PIO[PIN_PIO_PORT][PIN_TDO_SWO] = IOCON_FUNC1 | IOCON_DIGITAL_EN; + + // Release DETECT. + GPIO->B[PIN_PIO_PORT][PIN_DETECT] = 1; } @@ -305,6 +309,7 @@ called prior \ref PIN_SWDIO_OUT function calls. __STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void) { GPIO->DIRSET[PIN_PIO_PORT] = PIN_TMS_SWDIO_MASK; + GPIO->B[PIN_PIO_PORT][PIN_TMS_SWDIO_TXEN] = 1; } /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). @@ -313,6 +318,7 @@ called prior \ref PIN_SWDIO_IN function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void) { + GPIO->B[PIN_PIO_PORT][PIN_TMS_SWDIO_TXEN] = 0; GPIO->DIRCLR[PIN_PIO_PORT] = PIN_TMS_SWDIO_MASK; } @@ -384,7 +390,23 @@ __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void) */ __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit) { - GPIO->B[PIN_PIO_PORT][PIN_RESET] = bit; + // Only drive RESET low, otherwise let the target pull it high. + if (bit) { + // Change pin to input. + GPIO->DIRCLR[PIN_PIO_PORT] = PIN_RESET_MASK; + // Disable level translator output. + GPIO->B[PIN_PIO_PORT][PIN_RESET_TXEN] = 0; + // Set RESET to high. (Probably not be necessary) + GPIO->B[PIN_PIO_PORT][PIN_RESET] = 1; + } + else { + // Set RESET low. + GPIO->B[PIN_PIO_PORT][PIN_RESET] = 0; + // Enable level translator output to drive. + GPIO->B[PIN_PIO_PORT][PIN_RESET_TXEN] = 1; + // Change pin to output. + GPIO->DIRSET[PIN_PIO_PORT] = PIN_RESET_MASK; + } } ///@} @@ -467,32 +489,66 @@ Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled an */ __STATIC_INLINE void DAP_SETUP(void) { - // Ensure clocks are enabled. - SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_IOCON_MASK - | SYSCON_AHBCLKCTRL0_GPIO0_MASK; - // Configure pins. static const iocon_group_t kPinConfigs[] = { - { .port = PIN_PIO_PORT, .pin = PIN_TCK_SWCLK, .modefunc = IOCON_FUNC0 | IOCON_DIGITAL_EN | IOCON_SLEW_FAST, }, - { .port = PIN_PIO_PORT, .pin = PIN_TMS_SWDIO, .modefunc = IOCON_FUNC0 | IOCON_DIGITAL_EN | IOCON_SLEW_FAST, }, - { .port = PIN_PIO_PORT, .pin = PIN_TMS_SWDIO_TXEN, .modefunc = IOCON_FUNC0 | IOCON_DIGITAL_EN | IOCON_SLEW_FAST, }, - { .port = PIN_PIO_PORT, .pin = PIN_TDI, .modefunc = IOCON_FUNC0 | IOCON_DIGITAL_EN | IOCON_SLEW_FAST, }, - { .port = PIN_PIO_PORT, .pin = PIN_TDO_SWO, .modefunc = IOCON_FUNC0 | IOCON_DIGITAL_EN, }, - { .port = PIN_PIO_PORT, .pin = PIN_RESET, .modefunc = IOCON_FUNC0 | IOCON_DIGITAL_EN, }, - { .port = PIN_PIO_PORT, .pin = PIN_RESET_TXEN, .modefunc = IOCON_FUNC0 | IOCON_GPIO_MODE | IOCON_DIGITAL_EN, }, - { .port = PIN_PIO_PORT, .pin = PIN_DETECT, .modefunc = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN, }, - { .port = PIN_PIO_PORT, .pin = PIN_HW_VERS_6, .modefunc = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN, }, - { .port = PIN_PIO_PORT, .pin = PIN_HW_VERS_7, .modefunc = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN, }, + { .port = PIN_PIO_PORT, .pin = PIN_TCK_SWCLK, .modefunc = IOCON_FUNC0 + | IOCON_DIGITAL_EN + | IOCON_SLEW_FAST + }, + { .port = PIN_PIO_PORT, .pin = PIN_TMS_SWDIO, .modefunc = IOCON_FUNC0 + | IOCON_DIGITAL_EN + | IOCON_SLEW_FAST + }, + { .port = PIN_PIO_PORT, .pin = PIN_TMS_SWDIO_TXEN, .modefunc = IOCON_FUNC0 + | IOCON_DIGITAL_EN + | IOCON_SLEW_FAST + }, + { .port = PIN_PIO_PORT, .pin = PIN_TDI, .modefunc = IOCON_FUNC0 + | IOCON_DIGITAL_EN + | IOCON_SLEW_FAST + }, + { .port = PIN_PIO_PORT, .pin = PIN_TDO_SWO, .modefunc = IOCON_FUNC0 + | IOCON_DIGITAL_EN + }, + { .port = PIN_PIO_PORT, .pin = PIN_RESET, .modefunc = IOCON_FUNC0 + | IOCON_DIGITAL_EN + }, + { .port = PIN_PIO_PORT, .pin = PIN_RESET_TXEN, .modefunc = IOCON_FUNC0 + | IOCON_GPIO_MODE + | IOCON_DIGITAL_EN + }, + { .port = PIN_PIO_PORT, .pin = PIN_DETECT, .modefunc = IOCON_FUNC0 + | IOCON_MODE_PULLUP + | IOCON_DIGITAL_EN + | IOCON_OPENDRAIN_EN + }, + { .port = PIN_PIO_PORT, .pin = PIN_HW_VERS_6, .modefunc = IOCON_FUNC0 + | IOCON_MODE_PULLUP + | IOCON_DIGITAL_EN + | IOCON_OPENDRAIN_EN + }, + { .port = PIN_PIO_PORT, .pin = PIN_HW_VERS_7, .modefunc = IOCON_FUNC0 + | IOCON_MODE_PULLUP + | IOCON_DIGITAL_EN + | IOCON_OPENDRAIN_EN + }, }; IOCON_SetPinMuxing(IOCON, kPinConfigs, ARRAY_SIZE(kPinConfigs)); // Configure GPIO outputs. - GPIO->CLR[PIN_PIO_PORT] = PIN_TMS_SWDIO_TXEN_MASK - | PIN_RESET_TXEN_MASK; + GPIO->CLR[PIN_PIO_PORT] = PIN_TMS_SWDIO_TXEN_MASK // Disable TMS/SWDIO drive. + | PIN_RESET_TXEN_MASK; // Disable RESET drive. + // Set GPIO directions. GPIO->DIRSET[PIN_PIO_PORT] = PIN_TMS_SWDIO_TXEN_MASK - | PIN_RESET_TXEN_MASK; + | PIN_RESET_TXEN_MASK + | PIN_DETECT_MASK; + GPIO->DIRCLR[PIN_PIO_PORT] = PIN_TCK_SWCLK_MASK + | PIN_TMS_SWDIO_MASK + | PIN_TDO_SWO_MASK + | PIN_TDI_MASK + | PIN_RESET_MASK; } /** Reset Target Device with custom specific I/O pin or command sequence. From 8e0785516eedd85ef746f6f99441aea22517d558 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sat, 19 Dec 2020 15:51:22 -0600 Subject: [PATCH 139/617] LPC55xx: add some SDK drivers. --- .../nxp/lpc55xx/LPC55S69/drivers/fsl_crc.c | 173 +++ .../nxp/lpc55xx/LPC55S69/drivers/fsl_crc.h | 183 +++ .../nxp/lpc55xx/LPC55S69/drivers/fsl_ctimer.c | 525 +++++++++ .../nxp/lpc55xx/LPC55S69/drivers/fsl_ctimer.h | 488 ++++++++ .../nxp/lpc55xx/LPC55S69/drivers/fsl_dma.c | 1044 +++++++++++++++++ .../lpc55xx/LPC55S69/drivers/fsl_inputmux.c | 135 +++ .../lpc55xx/LPC55S69/drivers/fsl_inputmux.h | 97 ++ .../drivers/fsl_inputmux_connections.h | 412 +++++++ .../lpc55xx/LPC55S69/drivers/fsl_usart_dma.c | 314 +++++ 9 files changed, 3371 insertions(+) create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_crc.c create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_crc.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_ctimer.c create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_ctimer.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_dma.c create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_inputmux.c create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_inputmux.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_inputmux_connections.h create mode 100644 source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart_dma.c diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_crc.c b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_crc.c new file mode 100644 index 000000000..b903df269 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_crc.c @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_crc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_crc" +#endif + +#if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT +/* @brief Default user configuration structure for CRC-CCITT */ +#define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT +/*< CRC-CCIT polynomial x^16 + x^12 + x^5 + x^0 */ +#define CRC_DRIVER_DEFAULT_REVERSE_IN false +/*< Default is no bit reverse */ +#define CRC_DRIVER_DEFAULT_COMPLEMENT_IN false +/*< Default is without complement of written data */ +#define CRC_DRIVER_DEFAULT_REVERSE_OUT false +/*< Default is no bit reverse */ +#define CRC_DRIVER_DEFAULT_COMPLEMENT_OUT false +/*< Default is without complement of CRC data register read data */ +#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU +/*< Default initial checksum */ +#endif /* CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Enables and configures the CRC peripheral module. + * + * This functions enables the CRC peripheral clock in the LPC SYSCON block. + * It also configures the CRC engine and starts checksum computation by writing the seed. + * + * param base CRC peripheral address. + * param config CRC module configuration structure. + */ +void CRC_Init(CRC_Type *base, const crc_config_t *config) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* enable clock to CRC */ + CLOCK_EnableClock(kCLOCK_Crc); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_CRC_HAS_NO_RESET) && FSL_FEATURE_CRC_HAS_NO_RESET) + RESET_PeripheralReset(kCRC_RST_SHIFT_RSTn); +#endif + + /* configure CRC module and write the seed */ + base->MODE = CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) | + CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) | + CRC_MODE_CMPL_SUM(config->complementOut); + base->SEED = config->seed; +} + +/*! + * brief Loads default values to CRC protocol configuration structure. + * + * Loads default values to CRC protocol configuration structure. The default values are: + * code + * config->polynomial = kCRC_Polynomial_CRC_CCITT; + * config->reverseIn = false; + * config->complementIn = false; + * config->reverseOut = false; + * config->complementOut = false; + * config->seed = 0xFFFFU; + * endcode + * + * param config CRC protocol configuration structure + */ +void CRC_GetDefaultConfig(crc_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_REVERSE_IN, + CRC_DRIVER_DEFAULT_COMPLEMENT_IN, CRC_DRIVER_DEFAULT_REVERSE_OUT, + CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED}; + + *config = default_config; +} + +/*! + * brief resets CRC peripheral module. + * + * param base CRC peripheral address. + */ +void CRC_Reset(CRC_Type *base) +{ + crc_config_t config; + CRC_GetDefaultConfig(&config); + CRC_Init(base, &config); +} + +/*! + * brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure. + * + * The values, including seed, can be used to resume CRC calculation later. + + * param base CRC peripheral address. + * param config CRC protocol configuration structure + */ +void CRC_GetConfig(CRC_Type *base, crc_config_t *config) +{ + /* extract CRC mode settings */ + uint32_t mode = base->MODE; + config->polynomial = + (crc_polynomial_t)(uint32_t)(((uint32_t)(mode & CRC_MODE_CRC_POLY_MASK)) >> CRC_MODE_CRC_POLY_SHIFT); + config->reverseIn = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK); + config->complementIn = (bool)(mode & CRC_MODE_CMPL_WR_MASK); + config->reverseOut = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK); + config->complementOut = (bool)(mode & CRC_MODE_CMPL_SUM_MASK); + + /* reset CRC sum bit reverse and 1's complement setting, so its value can be used as a seed */ + base->MODE = mode & ~((1U << CRC_MODE_BIT_RVS_SUM_SHIFT) | (1U << CRC_MODE_CMPL_SUM_SHIFT)); + + /* now we can obtain intermediate raw CRC sum value */ + config->seed = base->SUM; + + /* restore original CRC sum bit reverse and 1's complement setting */ + base->MODE = mode; +} + +/*! + * brief Writes data to the CRC module. + * + * Writes input data buffer bytes to CRC data register. + * + * param base CRC peripheral address. + * param data Input data stream, MSByte in data[0]. + * param dataSize Size of the input data buffer in bytes. + */ +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) +{ + const uint32_t *data32; + + /* 8-bit reads and writes till source address is aligned 4 bytes */ + while ((0U != dataSize) && (0U != ((uint32_t)data & 3U))) + { + *((__O uint8_t *)&(base->WR_DATA)) = *data; + data++; + dataSize--; + } + + /* use 32-bit reads and writes as long as possible */ + data32 = (const uint32_t *)data; + while (dataSize >= sizeof(uint32_t)) + { + *((__O uint32_t *)&(base->WR_DATA)) = *data32; + data32++; + dataSize -= sizeof(uint32_t); + } + + data = (const uint8_t *)data32; + + /* 8-bit reads and writes till end of data buffer */ + while (0U != dataSize) + { + *((__O uint8_t *)&(base->WR_DATA)) = *data; + data++; + dataSize--; + } +} diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_crc.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_crc.h new file mode 100644 index 000000000..412c9101b --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_crc.h @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CRC_H_ +#define _FSL_CRC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup crc + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CRC driver version. Version 2.0.2. + * + * Current version: 2.0.2 + * + * Change log: + * - Version 2.0.0 + * - initial version + * - Version 2.0.1 + * - add explicit type cast when writing to WR_DATA + * - Version 2.0.2 + * - Fix MISRA issue + */ +#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +#ifndef CRC_DRIVER_CUSTOM_DEFAULTS +/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Uses CRC-16/CCITT-FALSE as default. */ +#define CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT 1 +#endif + +/*! @brief CRC polynomials to use. */ +typedef enum _crc_polynomial +{ + kCRC_Polynomial_CRC_CCITT = 0U, /*!< x^16+x^12+x^5+1 */ + kCRC_Polynomial_CRC_16 = 1U, /*!< x^16+x^15+x^2+1 */ + kCRC_Polynomial_CRC_32 = 2U /*!< x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */ +} crc_polynomial_t; + +/*! + * @brief CRC protocol configuration. + * + * This structure holds the configuration for the CRC protocol. + * + */ +typedef struct _crc_config +{ + crc_polynomial_t polynomial; /*!< CRC polynomial. */ + bool reverseIn; /*!< Reverse bits on input. */ + bool complementIn; /*!< Perform 1's complement on input. */ + bool reverseOut; /*!< Reverse bits on output. */ + bool complementOut; /*!< Perform 1's complement on output. */ + uint32_t seed; /*!< Starting checksum value. */ +} crc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enables and configures the CRC peripheral module. + * + * This functions enables the CRC peripheral clock in the LPC SYSCON block. + * It also configures the CRC engine and starts checksum computation by writing the seed. + * + * @param base CRC peripheral address. + * @param config CRC module configuration structure. + */ +void CRC_Init(CRC_Type *base, const crc_config_t *config); + +/*! + * @brief Disables the CRC peripheral module. + * + * This functions disables the CRC peripheral clock in the LPC SYSCON block. + * + * @param base CRC peripheral address. + */ +static inline void CRC_Deinit(CRC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* disable clock to CRC */ + CLOCK_DisableClock(kCLOCK_Crc); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief resets CRC peripheral module. + * + * @param base CRC peripheral address. + */ +void CRC_Reset(CRC_Type *base); + +/*! + * @brief Loads default values to CRC protocol configuration structure. + * + * Loads default values to CRC protocol configuration structure. The default values are: + * @code + * config->polynomial = kCRC_Polynomial_CRC_CCITT; + * config->reverseIn = false; + * config->complementIn = false; + * config->reverseOut = false; + * config->complementOut = false; + * config->seed = 0xFFFFU; + * @endcode + * + * @param config CRC protocol configuration structure + */ +void CRC_GetDefaultConfig(crc_config_t *config); + +/*! + * @brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure. + * + * The values, including seed, can be used to resume CRC calculation later. + + * @param base CRC peripheral address. + * @param config CRC protocol configuration structure + */ +void CRC_GetConfig(CRC_Type *base, crc_config_t *config); + +/*! + * @brief Writes data to the CRC module. + * + * Writes input data buffer bytes to CRC data register. + * + * @param base CRC peripheral address. + * @param data Input data stream, MSByte in data[0]. + * @param dataSize Size of the input data buffer in bytes. + */ +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize); + +/*! + * @brief Reads 32-bit checksum from the CRC module. + * + * Reads CRC data register. + * + * @param base CRC peripheral address. + * @return final 32-bit checksum, after configured bit reverse and complement operations. + */ +static inline uint32_t CRC_Get32bitResult(CRC_Type *base) +{ + return base->SUM; +} + +/*! + * @brief Reads 16-bit checksum from the CRC module. + * + * Reads CRC data register. + * + * @param base CRC peripheral address. + * @return final 16-bit checksum, after configured bit reverse and complement operations. + */ +static inline uint16_t CRC_Get16bitResult(CRC_Type *base) +{ + return (uint16_t)base->SUM; +} + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* _FSL_CRC_H_ */ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_ctimer.c b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_ctimer.c new file mode 100644 index 000000000..619795c76 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_ctimer.c @@ -0,0 +1,525 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_ctimer.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ctimer" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base Ctimer peripheral base address + * + * @return The Timer instance + */ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to Timer bases for each instance. */ +static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to Timer clocks for each instance. */ +static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET +/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N; +#else +/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; +#endif +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/*! @brief Pointers real ISRs installed by drivers for each instance. */ +static ctimer_callback_t *s_ctimerCallback[FSL_FEATURE_SOC_CTIMER_COUNT] = {0}; + +/*! @brief Callback type installed by drivers for each instance. */ +static ctimer_callback_type_t ctimerCallbackType[FSL_FEATURE_SOC_CTIMER_COUNT] = {kCTIMER_SingleCallback}; + +/*! @brief Array to map timer instance to IRQ number. */ +static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base) +{ + uint32_t instance; + uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ctimerArrayCount; instance++) + { + if (s_ctimerBases[instance] == base) + { + break; + } + } + + assert(instance < ctimerArrayCount); + + return instance; +} + +/*! + * brief Ungates the clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application before using the driver. + * + * param base Ctimer peripheral base address + * param config Pointer to the user configuration structure. + */ +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) +{ + assert(config != NULL); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the timer clock*/ + CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +/* Reset the module. */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) + RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/* Setup the cimer mode and count select */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input); +#endif + /* Setup the timer prescale value */ + base->PR = CTIMER_PR_PRVAL(config->prescale); +} + +/*! + * brief Gates the timer clock. + * + * param base Ctimer peripheral base address + */ +void CTIMER_Deinit(CTIMER_Type *base) +{ + uint32_t index = CTIMER_GetInstance(base); + /* Stop the timer */ + base->TCR &= ~CTIMER_TCR_CEN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the timer clock*/ + CLOCK_DisableClock(s_ctimerClocks[index]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Disable IRQ at NVIC Level */ + (void)DisableIRQ(s_ctimerIRQ[index]); +} + +/*! + * brief Fills in the timers configuration structure with the default settings. + * + * The default values are: + * code + * config->mode = kCTIMER_TimerMode; + * config->input = kCTIMER_Capture_0; + * config->prescale = 0; + * endcode + * param config Pointer to the user configuration structure. + */ +void CTIMER_GetDefaultConfig(ctimer_config_t *config) +{ + assert(config != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Run as a timer */ + config->mode = kCTIMER_TimerMode; + /* This field is ignored when mode is timer */ + config->input = kCTIMER_Capture_0; + /* Timer counter is incremented on every APB bus clock */ + config->prescale = 0; +} + +/*! + * brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function will assign match channel 3 to set the PWM cycle. + * + * note When setting PWM output from multiple output pins, all should use the same PWM + * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. + * + * param base Ctimer peripheral base address + * param matchChannel Match pin to be used to output the PWM signal + * param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz Timer counter clock in Hz + * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt is generated + * + * return kStatus_Success on success + * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle + */ +status_t CTIMER_SetupPwm(CTIMER_Type *base, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt) +{ + assert(pwmFreq_Hz > 0U); + + uint32_t reg; + uint32_t period, pulsePeriod = 0; + uint32_t timerClock = srcClock_Hz / (base->PR + 1U); + uint32_t index = CTIMER_GetInstance(base); + + if (matchChannel == kCTIMER_Match_3) + { + return kStatus_Fail; + } + + /* Enable PWM mode on the channel */ + base->PWMC |= (1UL << (uint32_t)matchChannel); + + /* Clear the stop, reset and interrupt bits for this channel */ + reg = base->MCR; + reg &= + ~(((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK)) + << ((uint32_t)matchChannel * 3U)); + + /* If call back function is valid then enable match interrupt for the channel */ + if (enableInt) + { + reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); + } + + /* Reset the counter when match on channel 3 */ + reg |= CTIMER_MCR_MR3R_MASK; + + base->MCR = reg; + + /* Calculate PWM period match value */ + period = (timerClock / pwmFreq_Hz) - 1U; + + /* Calculate pulse width match value */ + if (dutyCyclePercent == 0U) + { + pulsePeriod = period + 1U; + } + else + { + pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; + } + + /* Match on channel 3 will define the PWM period */ + base->MR[kCTIMER_Match_3] = period; + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + (void)EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +/*! + * brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function will assign match channel 3 to set the PWM cycle. + * + * note When setting PWM output from multiple output pins, all should use the same PWM + * period + * + * param base Ctimer peripheral base address + * param matchChannel Match pin to be used to output the PWM signal + * param pwmPeriod PWM period match value + * param pulsePeriod Pulse width match value + * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt is generated + * + * return kStatus_Success on success + * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period + */ +status_t CTIMER_SetupPwmPeriod( + CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt) +{ +/* Some CTimers only have 16bits , so the value is limited*/ +#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B + assert(!((FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32) && (pulsePeriod > 0xFFFFU))); +#endif + + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + if (matchChannel == kCTIMER_Match_3) + { + return kStatus_Fail; + } + + /* Enable PWM mode on the channel */ + base->PWMC |= (1UL << (uint32_t)matchChannel); + + /* Clear the stop, reset and interrupt bits for this channel */ + reg = base->MCR; + reg &= + ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) + << ((uint32_t)matchChannel * 3U)); + + /* If call back function is valid then enable match interrupt for the channel */ + if (enableInt) + { + reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); + } + + /* Reset the counter when match on channel 3 */ + reg |= CTIMER_MCR_MR3R_MASK; + + base->MCR = reg; + + /* Match on channel 3 will define the PWM period */ + base->MR[kCTIMER_Match_3] = pwmPeriod; + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + (void)EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +/*! + * brief Updates the duty cycle of an active PWM signal. + * + * note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution. + * + * param base Ctimer peripheral base address + * param matchChannel Match pin to be used to output the PWM signal + * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + */ +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent) +{ + uint32_t pulsePeriod = 0, period; + + /* Match channel 3 defines the PWM period */ + period = base->MR[kCTIMER_Match_3]; + + /* For 0% dutycyle, make pulse period greater than period so the event will never occur */ + if (dutyCyclePercent == 0U) + { + pulsePeriod = period + 1U; + } + else + { + pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; + } + + /* Update dutycycle */ + base->MR[matchChannel] = pulsePeriod; +} + +/*! + * brief Setup the match register. + * + * User configuration is used to setup the match value and action to be taken when a match occurs. + * + * param base Ctimer peripheral base address + * param matchChannel Match register to configure + * param config Pointer to the match configuration structure + */ +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config) +{ +/* Some CTimers only have 16bits , so the value is limited*/ +#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B + assert(!(FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32 && config->matchValue > 0xFFFFU)); +#endif + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the counter operation when a match on this channel occurs */ + reg = base->MCR; + reg &= + ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) + << ((uint32_t)matchChannel * 3U)); + reg |= ((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)matchChannel * 3U))); + reg |= ((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)matchChannel * 3U))); + reg |= ((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); + base->MCR = reg; + + reg = base->EMR; + /* Set the match output operation when a match on this channel occurs */ + reg &= ~(((uint32_t)CTIMER_EMR_EMC0_MASK) << ((uint32_t)matchChannel * 2U)); + reg |= ((uint32_t)config->outControl) << (CTIMER_EMR_EMC0_SHIFT + ((uint32_t)matchChannel * 2U)); + + /* Set the initial state of the EM bit/output */ + reg &= ~(((uint32_t)CTIMER_EMR_EM0_MASK) << (uint32_t)matchChannel); + reg |= ((uint32_t)config->outPinInitState) << (uint32_t)matchChannel; + base->EMR = reg; + + /* Set the match value */ + base->MR[matchChannel] = config->matchValue; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); + /* If interrupt is enabled then enable interrupt and update the call back function */ + if (config->enableInterrupt) + { + (void)EnableIRQ(s_ctimerIRQ[index]); + } +} + +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) +/*! + * brief Setup the capture. + * + * param base Ctimer peripheral base address + * param capture Capture channel to configure + * param edge Edge on the channel that will trigger a capture + * param enableInt Flag to enable channel interrupts, if enabled then the registered call back + * is called upon capture + */ +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt) +{ + uint32_t reg = base->CCR; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the capture edge */ + reg &= ~((uint32_t)((uint32_t)CTIMER_CCR_CAP0RE_MASK | (uint32_t)CTIMER_CCR_CAP0FE_MASK | + (uint32_t)CTIMER_CCR_CAP0I_MASK) + << ((uint32_t)capture * 3U)); + reg |= ((uint32_t)edge) << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U)); + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, (((uint32_t)kCTIMER_Capture0Flag) << (uint32_t)capture)); + /* If call back function is valid then enable capture interrupt for the channel and update the call back function */ + if (enableInt) + { + reg |= ((uint32_t)CTIMER_CCR_CAP0I_MASK) << ((uint32_t)capture * 3U); + (void)EnableIRQ(s_ctimerIRQ[index]); + } + base->CCR = reg; +} +#endif + +/*! + * brief Register callback. + * + * param base Ctimer peripheral base address + * param cb_func callback function + * param cb_type callback function type, singular or multiple + */ +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type) +{ + uint32_t index = CTIMER_GetInstance(base); + s_ctimerCallback[index] = cb_func; + ctimerCallbackType[index] = cb_type; +} + +void CTIMER_GenericIRQHandler(uint32_t index) +{ + uint32_t int_stat, i, mask; + /* Get Interrupt status flags */ + int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]); + /* Clear the status flags that were set */ + CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat); + if (ctimerCallbackType[index] == kCTIMER_SingleCallback) + { + if (s_ctimerCallback[index][0] != NULL) + { + s_ctimerCallback[index][0](int_stat); + } + } + else + { +#if defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE + for (i = 0; i <= CTIMER_IR_MR3INT_SHIFT; i++) +#else +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) +#else + for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +#endif + { + mask = 0x01UL << i; + /* For each status flag bit that was set call the callback function if it is valid */ + if (((int_stat & mask) != 0U) && (s_ctimerCallback[index][i] != NULL)) + { + s_ctimerCallback[index][i](int_stat); + } + } + } + SDK_ISR_EXIT_BARRIER; +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(CTIMER0) +void CTIMER0_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(0); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER1) +void CTIMER1_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(1); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER2) +void CTIMER2_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(2); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER3) +void CTIMER3_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(3); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER4) +void CTIMER4_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(4); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_ctimer.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_ctimer.h new file mode 100644 index 000000000..d689c8a97 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_ctimer.h @@ -0,0 +1,488 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_CTIMER_H_ +#define _FSL_CTIMER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ctimer + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3 */ +/*@}*/ + +/*! @brief List of Timer capture channels */ +typedef enum _ctimer_capture_channel +{ + kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ + kCTIMER_Capture_1, /*!< Timer capture channel 1 */ + kCTIMER_Capture_2, /*!< Timer capture channel 2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture_3 /*!< Timer capture channel 3 */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +} ctimer_capture_channel_t; + +/*! @brief List of capture edge options */ +typedef enum _ctimer_capture_edge +{ + kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */ + kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */ + kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */ +} ctimer_capture_edge_t; + +/*! @brief List of Timer match registers */ +typedef enum _ctimer_match +{ + kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */ + kCTIMER_Match_1, /*!< Timer match register 1 */ + kCTIMER_Match_2, /*!< Timer match register 2 */ + kCTIMER_Match_3 /*!< Timer match register 3 */ +} ctimer_match_t; + +/*! @brief List of output control options */ +typedef enum _ctimer_match_output_control +{ + kCTIMER_Output_NoAction = 0U, /*!< No action is taken */ + kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */ + kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */ + kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */ +} ctimer_match_output_control_t; + +/*! @brief List of Timer modes */ +typedef enum _ctimer_timer_mode +{ + kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */ + kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */ + kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */ + kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */ +} ctimer_timer_mode_t; + +/*! @brief List of Timer interrupts */ +typedef enum _ctimer_interrupt_enable +{ + kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ + kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ + kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ + kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ + kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ + kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ +#endif +} ctimer_interrupt_enable_t; + +/*! @brief List of Timer flags */ +typedef enum _ctimer_status_flags +{ + kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ + kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ + kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ + kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ + kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ + kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +#endif +} ctimer_status_flags_t; + +typedef void (*ctimer_callback_t)(uint32_t flags); + +/*! @brief Callback type when registering for a callback. When registering a callback + * an array of function pointers is passed the size could be 1 or 8, the callback + * type will tell that. + */ +typedef enum +{ + kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. + based on the status flags different channels needs to be handled differently */ + kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. + for both match/capture */ +} ctimer_callback_type_t; + +/*! + * @brief Match configuration + * + * This structure holds the configuration settings for each match register. + */ +typedef struct _ctimer_match_config +{ + uint32_t matchValue; /*!< This is stored in the match register */ + bool enableCounterReset; /*!< true: Match will reset the counter + false: Match will not reser the counter */ + bool enableCounterStop; /*!< true: Match will stop the counter + false: Match will not stop the counter */ + ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */ + bool outPinInitState; /*!< Initial value of the EM bit/output */ + bool enableInterrupt; /*!< true: Generate interrupt upon match + false: Do not generate interrupt on match */ + +} ctimer_match_config_t; + +/*! + * @brief Timer configuration structure + * + * This structure holds the configuration settings for the Timer peripheral. To initialize this + * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a + * pointer to the configuration structure instance. + * + * The configuration structure can be made constant so as to reside in flash. + */ +typedef struct _ctimer_config +{ + ctimer_timer_mode_t mode; /*!< Timer mode */ + ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer + modes that rely on this input signal to increment TC */ + uint32_t prescale; /*!< Prescale value */ +} ctimer_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application before using the driver. + * + * @param base Ctimer peripheral base address + * @param config Pointer to the user configuration structure. + */ +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config); + +/*! + * @brief Gates the timer clock. + * + * @param base Ctimer peripheral base address + */ +void CTIMER_Deinit(CTIMER_Type *base); + +/*! + * @brief Fills in the timers configuration structure with the default settings. + * + * The default values are: + * @code + * config->mode = kCTIMER_TimerMode; + * config->input = kCTIMER_Capture_0; + * config->prescale = 0; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void CTIMER_GetDefaultConfig(ctimer_config_t *config); + +/*! @}*/ + +/*! + * @name PWM setup operations + * @{ + */ + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function will assign match channel 3 to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * period + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param pwmPeriod PWM period match value + * @param pulsePeriod Pulse width match value + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt is generated + * + * @return kStatus_Success on success + * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period + */ +status_t CTIMER_SetupPwmPeriod( + CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt); + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function will assign match channel 3 to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz Timer counter clock in Hz + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt is generated + * + * @return kStatus_Success on success + * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle + */ +status_t CTIMER_SetupPwm(CTIMER_Type *base, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt); + +/*! + * @brief Updates the pulse period of an active PWM signal. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param pulsePeriod New PWM pulse width match value + */ +static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod) +{ + /* Update PWM pulse period match value */ + base->MR[matchChannel] = pulsePeriod; +} + +/*! + * @brief Updates the duty cycle of an active PWM signal. + * + * @note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + */ +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent); + +/*! @}*/ + +/*! + * @brief Setup the match register. + * + * User configuration is used to setup the match value and action to be taken when a match occurs. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match register to configure + * @param config Pointer to the match configuration structure + */ +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config); + +/*! + * @brief Setup the capture. + * + * @param base Ctimer peripheral base address + * @param capture Capture channel to configure + * @param edge Edge on the channel that will trigger a capture + * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back + * is called upon capture + */ +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt); + +/*! + * @brief Get the timer count value from TC register. + * + * @param base Ctimer peripheral base address. + * @return return the timer count value. + */ +static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base) +{ + return (base->TC); +} + +/*! + * @brief Register callback. + * + * @param base Ctimer peripheral base address + * @param cb_func callback function + * @param cb_type callback function type, singular or multiple + */ +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type); + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Enable match interrupts */ + base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + +/* Enable capture interrupts */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +#endif +} + +/*! + * @brief Disables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Disable match interrupts */ + base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK)); + +/* Disable capture interrupts */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + )); +#endif +} + +/*! + * @brief Gets the enabled Timer interrupts. + * + * @param base Ctimer peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) +{ + uint32_t enabledIntrs = 0; + + /* Get all the match interrupts enabled */ + enabledIntrs = + base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + +/* Get all the capture interrupts enabled */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +#endif + + return enabledIntrs; +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the Timer status flags. + * + * @param base Ctimer peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base) +{ + return base->IR; +} + +/*! + * @brief Clears the Timer status flags. + * + * @param base Ctimer peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask) +{ + base->IR = mask; +} + +/*! @}*/ + +/*! + * @name Counter Start and Stop + * @{ + */ + +/*! + * @brief Starts the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StartTimer(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CEN_MASK; +} + +/*! + * @brief Stops the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StopTimer(CTIMER_Type *base) +{ + base->TCR &= ~CTIMER_TCR_CEN_MASK; +} + +/*! @}*/ + +/*! + * @brief Reset the counter. + * + * The timer counter and prescale counter are reset on the next positive edge of the APB clock. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_Reset(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CRST_MASK; + base->TCR &= ~CTIMER_TCR_CRST_MASK; +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CTIMER_H_ */ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_dma.c b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_dma.c new file mode 100644 index 000000000..e7fe9a74d --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_dma.c @@ -0,0 +1,1044 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_dma.h" +#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) +#include "fsl_memory.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_dma" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for DMA. + * + * @param base DMA peripheral base address. + */ +static uint32_t DMA_GetInstance(DMA_Type *base); + +/*! + * @brief Get virtual channel number. + * + * @param base DMA peripheral base address. + */ +static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map DMA instance number to base pointer. */ +static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map DMA instance number to clock name. */ +static const clock_ip_name_t s_dmaClockName[] = DMA_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET) +/*! @brief Pointers to DMA resets for each instance. */ +static const reset_ip_name_t s_dmaResets[] = DMA_RSTS_N; +#endif /*! @brief Array to map DMA instance number to IRQ number. */ +static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS; + +/*! @brief Pointers to transfer handle for each DMA channel. */ +static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_ALL_CHANNELS]; +/*! @brief DMA driver internal descriptor table */ +#if (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) +DMA_ALLOCATE_HEAD_DESCRIPTORS_AT_NONCACHEABLE(s_dma_descriptor_table0, FSL_FEATURE_DMA_MAX_CHANNELS); +#else +DMA_ALLOCATE_HEAD_DESCRIPTORS(s_dma_descriptor_table0, FSL_FEATURE_DMA_MAX_CHANNELS); +#endif +#if defined(DMA1) +#if (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) +DMA_ALLOCATE_HEAD_DESCRIPTORS_AT_NONCACHEABLE(s_dma_descriptor_table1, FSL_FEATURE_DMA_MAX_CHANNELS); +#else +DMA_ALLOCATE_HEAD_DESCRIPTORS(s_dma_descriptor_table1, FSL_FEATURE_DMA_MAX_CHANNELS); +#endif +static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0, s_dma_descriptor_table1}; +#else +static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0}; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t DMA_GetInstance(DMA_Type *base) +{ + uint32_t instance; + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++) + { + if (s_dmaBases[instance] == base) + { + break; + } + } + assert(instance < ARRAY_SIZE(s_dmaBases)); + + return instance; +} + +static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base) +{ + uint32_t startChannel = 0, instance = 0; + uint32_t i = 0; + + instance = DMA_GetInstance(base); + + /* Compute start channel */ + for (i = 0; i < instance; i++) + { + startChannel += (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(s_dmaBases[i]); + } + + return startChannel; +} + +/*! + * brief Initializes DMA peripheral. + * + * This function enable the DMA clock, set descriptor table and + * enable DMA peripheral. + * + * param base DMA peripheral base address. + */ +void DMA_Init(DMA_Type *base) +{ + uint32_t instance = DMA_GetInstance(base); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* enable dma clock gate */ + CLOCK_EnableClock(s_dmaClockName[DMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET) + /* Reset the DMA module */ + RESET_PeripheralReset(s_dmaResets[DMA_GetInstance(base)]); +#endif + /* set descriptor table */ +#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) + base->SRAMBASE = MEMORY_ConvertMemoryMapAddress((uint32_t)s_dma_descriptor_table[instance], kMEMORY_Local2DMA); +#else + base->SRAMBASE = (uint32_t)s_dma_descriptor_table[instance]; +#endif + /* enable dma peripheral */ + base->CTRL |= DMA_CTRL_ENABLE_MASK; +} + +/*! + * brief Deinitializes DMA peripheral. + * + * This function gates the DMA clock. + * + * param base DMA peripheral base address. + */ +void DMA_Deinit(DMA_Type *base) +{ + /* Disable DMA peripheral */ + base->CTRL &= ~(DMA_CTRL_ENABLE_MASK); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_dmaClockName[DMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Set trigger settings of DMA channel. + * deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig. + * + * param base DMA peripheral base address. + * param channel DMA channel number. + * param trigger trigger configuration. + */ +void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger) +{ + assert((channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)) && (NULL != trigger)); + + uint32_t tmpReg = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | + DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | + DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK); + tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); + tmpReg |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); + base->CHANNEL[channel].CFG = tmpReg; +} + +/*! + * brief Gets the remaining bytes of the current DMA descriptor transfer. + * + * param base DMA peripheral base address. + * param channel DMA channel number. + * return The number of bytes which have not been transferred yet. + */ +uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + + /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes + * impossible to distinguish between: + * - transfer finishes (represented by value '0x3FF') + * - and remaining 1024 bytes to transfer (value 0x3FF) + * for all descriptor in chain, except the last one. + * If you decide to use this function, please use 1023 transfers as maximal value */ + + /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */ + if ((!DMA_ChannelIsActive(base, channel)) && + (0x3FFUL == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> + DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))) + { + return 0UL; + } + + return ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> + DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + + 1UL; +} + +/* Verify and convert dma_xfercfg_t to XFERCFG register */ +static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr) +{ + assert(xfercfg != NULL); + /* check source increment */ + assert((xfercfg->srcInc <= (uint8_t)kDMA_AddressInterleave4xWidth) && + (xfercfg->dstInc <= (uint8_t)kDMA_AddressInterleave4xWidth)); + /* check data width */ + assert(xfercfg->byteWidth <= (uint8_t)kDMA_Transfer32BitWidth); + /* check transfer count */ + assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT); + + uint32_t xfer = 0; + + /* set valid flag - descriptor is ready now */ + xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid); + /* set reload - allow link to next descriptor */ + xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload); + /* set swtrig flag - start transfer */ + xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig); + /* set transfer count */ + xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig); + /* set INTA */ + xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA); + /* set INTB */ + xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB); + /* set data width */ + xfer |= DMA_CHANNEL_XFERCFG_WIDTH(xfercfg->byteWidth == 4U ? 2U : xfercfg->byteWidth - 1UL); + /* set source increment value */ + xfer |= DMA_CHANNEL_XFERCFG_SRCINC( + (xfercfg->srcInc == (uint8_t)kDMA_AddressInterleave4xWidth) ? (xfercfg->srcInc - 1UL) : xfercfg->srcInc); + /* set destination increment value */ + xfer |= DMA_CHANNEL_XFERCFG_DSTINC( + (xfercfg->dstInc == (uint8_t)kDMA_AddressInterleave4xWidth) ? (xfercfg->dstInc - 1UL) : xfercfg->dstInc); + /* set transfer count */ + xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1UL); + + /* store xferCFG */ + *xfercfg_addr = xfer; +} + +/*! + * brief setup dma descriptor + * Note: This function do not support configure wrap descriptor. + * param desc DMA descriptor address. + * param xfercfg Transfer configuration for DMA descriptor. + * param srcStartAddr Start address of source address. + * param dstStartAddr Start address of destination address. + * param nextDesc Address of next descriptor in chain. + */ +void DMA_SetupDescriptor( + dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) +{ + assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); + +#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) + srcStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)srcStartAddr, kMEMORY_Local2DMA); + dstStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)dstStartAddr, kMEMORY_Local2DMA); + nextDesc = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)nextDesc, kMEMORY_Local2DMA); +#endif + + uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; + + width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT; + srcInc = (xfercfg & DMA_CHANNEL_XFERCFG_SRCINC_MASK) >> DMA_CHANNEL_XFERCFG_SRCINC_SHIFT; + dstInc = (xfercfg & DMA_CHANNEL_XFERCFG_DSTINC_MASK) >> DMA_CHANNEL_XFERCFG_DSTINC_SHIFT; + transferCount = ((xfercfg & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1U; + + /* covert register value to actual value */ + if (width == 2U) + { + width = kDMA_Transfer32BitWidth; + } + else + { + width += 1U; + } + + /* + * Transfers of 16 bit width require an address alignment to a multiple of 2 bytes. + * Transfers of 32 bit width require an address alignment to a multiple of 4 bytes. + * Transfers of 8 bit width can be at any address + */ + if (((NULL != srcStartAddr) && (0UL == ((uint32_t)(uint32_t *)srcStartAddr) % width)) && + ((NULL != dstStartAddr) && (0UL == ((uint32_t)(uint32_t *)dstStartAddr) % width))) + { + if (srcInc == 3U) + { + srcInc = kDMA_AddressInterleave4xWidth; + } + + if (dstInc == 3U) + { + dstInc = kDMA_AddressInterleave4xWidth; + } + + desc->xfercfg = xfercfg; + desc->srcEndAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); + desc->dstEndAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); + desc->linkToNextDesc = nextDesc; + } + else + { + /* if address alignment not satisfy the requirement, reset the descriptor to make sure DMA generate error */ + desc->xfercfg = 0U; + desc->srcEndAddr = NULL; + desc->dstEndAddr = NULL; + } +} + +/*! + * brief setup dma channel descriptor + * Note: This function support configure wrap descriptor. + * param desc DMA descriptor address. + * param xfercfg Transfer configuration for DMA descriptor. + * param srcStartAddr Start address of source address. + * param dstStartAddr Start address of destination address. + * param nextDesc Address of next descriptor in chain. + * param wrapType burst wrap type. + * param burstSize burst size, reference _dma_burst_size. + */ +void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, + uint32_t xfercfg, + void *srcStartAddr, + void *dstStartAddr, + void *nextDesc, + dma_burst_wrap_t wrapType, + uint32_t burstSize) +{ + assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); + +#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) + srcStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)srcStartAddr, kMEMORY_Local2DMA); + dstStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)dstStartAddr, kMEMORY_Local2DMA); + nextDesc = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)nextDesc, kMEMORY_Local2DMA); +#endif + + uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; + + width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT; + srcInc = (xfercfg & DMA_CHANNEL_XFERCFG_SRCINC_MASK) >> DMA_CHANNEL_XFERCFG_SRCINC_SHIFT; + dstInc = (xfercfg & DMA_CHANNEL_XFERCFG_DSTINC_MASK) >> DMA_CHANNEL_XFERCFG_DSTINC_SHIFT; + transferCount = ((xfercfg & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1U; + + /* covert register value to actual value */ + if (width == 2U) + { + width = kDMA_Transfer32BitWidth; + } + else + { + width += 1U; + } + + /* + * Transfers of 16 bit width require an address alignment to a multiple of 2 bytes. + * Transfers of 32 bit width require an address alignment to a multiple of 4 bytes. + * Transfers of 8 bit width can be at any address + */ + if (((NULL != srcStartAddr) && (0UL == ((uint32_t)(uint32_t *)srcStartAddr) % width)) && + ((NULL != dstStartAddr) && (0UL == ((uint32_t)(uint32_t *)dstStartAddr) % width))) + { + if (srcInc == 3U) + { + srcInc = kDMA_AddressInterleave4xWidth; + } + + if (dstInc == 3U) + { + dstInc = kDMA_AddressInterleave4xWidth; + } + + desc->xfercfg = xfercfg; + + if (wrapType == kDMA_NoWrap) + { + desc->srcEndAddr = + DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); + desc->dstEndAddr = + DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); + } + /* for the wrap transfer, the destination address should be determined by the burstSize/width/interleave size */ + if (wrapType == kDMA_SrcWrap) + { + desc->srcEndAddr = + (uint32_t *)((uint32_t)(uint32_t *)srcStartAddr + ((1UL << burstSize) - 1UL) * width * srcInc); + desc->dstEndAddr = + DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); + } + if (wrapType == kDMA_DstWrap) + { + desc->srcEndAddr = + DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); + desc->dstEndAddr = + (uint32_t *)((uint32_t)(uint32_t *)dstStartAddr + ((1UL << burstSize) - 1UL) * width * dstInc); + } + if (wrapType == kDMA_SrcAndDstWrap) + { + desc->srcEndAddr = + (uint32_t *)(((uint32_t)(uint32_t *)srcStartAddr) + ((1UL << burstSize) - 1UL) * width * srcInc); + desc->dstEndAddr = + (uint32_t *)(((uint32_t)(uint32_t *)dstStartAddr) + ((1UL << burstSize) - 1UL) * width * dstInc); + } + + desc->linkToNextDesc = nextDesc; + } + else + { + /* if address alignment not satisfy the requirement, reset the descriptor to make sure DMA generate error */ + desc->xfercfg = 0U; + desc->srcEndAddr = NULL; + desc->dstEndAddr = NULL; + } +} + +/*! + * brief Create application specific DMA descriptor + * to be used in a chain in transfer + * deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor + * param desc DMA descriptor address. + * param xfercfg Transfer configuration for DMA descriptor. + * param srcAddr Address of last item to transmit + * param dstAddr Address of last item to receive. + * param nextDesc Address of next descriptor in chain. + */ +void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc) +{ + assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); + assert((NULL != srcAddr) && (0UL == ((uint32_t)(uint32_t *)srcAddr) % xfercfg->byteWidth)); + assert((NULL != dstAddr) && (0UL == ((uint32_t)(uint32_t *)dstAddr) % xfercfg->byteWidth)); + + uint32_t xfercfg_reg = 0; + + DMA_SetupXferCFG(xfercfg, &xfercfg_reg); + + /* Set descriptor structure */ + DMA_SetupDescriptor(desc, xfercfg_reg, srcAddr, dstAddr, nextDesc); +} + +/*! + * brief Abort running transfer by handle. + * + * This function aborts DMA transfer specified by handle. + * + * param handle DMA handle pointer. + */ +void DMA_AbortTransfer(dma_handle_t *handle) +{ + assert(NULL != handle); + + DMA_DisableChannel(handle->base, handle->channel); + while ((DMA_COMMON_CONST_REG_GET(handle->base, handle->channel, BUSY) & + (1UL << DMA_CHANNEL_INDEX(handle->channel))) != 0UL) + { + } + DMA_COMMON_REG_GET(handle->base, handle->channel, ABORT) |= 1UL << DMA_CHANNEL_INDEX(handle->channel); + DMA_EnableChannel(handle->base, handle->channel); +} + +/*! + * brief Creates the DMA handle. + * + * This function is called if using transaction API for DMA. This function + * initializes the internal state of DMA handle. + * + * param handle DMA handle pointer. The DMA handle stores callback function and + * parameters. + * param base DMA peripheral base address. + * param channel DMA channel number. + */ +void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel) +{ + assert((NULL != handle) && (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + + uint32_t dmaInstance; + uint32_t startChannel = 0; + /* base address is invalid DMA instance */ + dmaInstance = DMA_GetInstance(base); + startChannel = DMA_GetVirtualStartChannel(base); + + (void)memset(handle, 0, sizeof(*handle)); + handle->base = base; + handle->channel = (uint8_t)channel; + s_DMAHandle[startChannel + channel] = handle; + /* Enable NVIC interrupt */ + (void)EnableIRQ(s_dmaIRQNumber[dmaInstance]); + /* Enable channel interrupt */ + DMA_EnableChannelInterrupts(handle->base, channel); +} + +/*! + * brief Installs a callback function for the DMA transfer. + * + * This callback is called in DMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. + * + * param handle DMA handle pointer. + * param callback DMA callback function pointer. + * param userData Parameter for callback function. + */ +void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData) +{ + assert(handle != NULL); + + handle->callback = callback; + handle->userData = userData; +} + +/*! + * brief Prepares the DMA transfer structure. + * deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer and + * DMA_PrepareChannelXfer. + * This function prepares the transfer configuration structure according to the user input. + * + * param config The user configuration structure of type dma_transfer_t. + * param srcAddr DMA transfer source address. + * param dstAddr DMA transfer destination address. + * param byteWidth DMA transfer destination address width(bytes). + * param transferBytes DMA transfer bytes to be transferred. + * param type DMA transfer type. + * param nextDesc Chain custom descriptor to transfer. + * note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in + * source address error(SAE). + */ +void DMA_PrepareTransfer(dma_transfer_config_t *config, + void *srcAddr, + void *dstAddr, + uint32_t byteWidth, + uint32_t transferBytes, + dma_transfer_type_t type, + void *nextDesc) +{ + uint32_t xfer_count; + assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr)); + assert((byteWidth == 1UL) || (byteWidth == 2UL) || (byteWidth == 4UL)); + assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); + + /* check max */ + xfer_count = transferBytes / byteWidth; + assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0UL == transferBytes % byteWidth)); + + (void)memset(config, 0, sizeof(*config)); + + if (type == kDMA_MemoryToMemory) + { + config->xfercfg.srcInc = 1; + config->xfercfg.dstInc = 1; + config->isPeriph = false; + } + + else if (type == kDMA_PeripheralToMemory) + { + /* Peripheral register - source doesn't increment */ + config->xfercfg.srcInc = 0; + config->xfercfg.dstInc = 1; + config->isPeriph = true; + } + else if (type == kDMA_MemoryToPeripheral) + { + /* Peripheral register - destination doesn't increment */ + config->xfercfg.srcInc = 1; + config->xfercfg.dstInc = 0; + config->isPeriph = true; + } + /* kDMA_StaticToStatic */ + else + { + config->xfercfg.srcInc = 0; + config->xfercfg.dstInc = 0; + config->isPeriph = true; + } + + config->dstAddr = (uint8_t *)dstAddr; + config->srcAddr = (uint8_t *)srcAddr; + config->nextDesc = (uint8_t *)nextDesc; + config->xfercfg.transferCount = (uint16_t)xfer_count; + config->xfercfg.byteWidth = (uint8_t)byteWidth; + config->xfercfg.intA = true; + config->xfercfg.reload = nextDesc != NULL; + config->xfercfg.valid = true; +} + +/*! + * brief set channel config. + * + * This function provide a interface to configure channel configuration reisters. + * + * param base DMA base address. + * param channel DMA channel number. + * param config channel configurations structure. + */ +void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMA_MAX_CHANNELS); + + uint32_t tmpReg = DMA_CHANNEL_CFG_PERIPHREQEN_MASK; + + if (trigger != NULL) + { + tmpReg |= DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | + DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | + DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK; + } + + tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); + + if (trigger != NULL) + { + tmpReg |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); + } + + tmpReg |= DMA_CHANNEL_CFG_PERIPHREQEN(isPeriph); + + base->CHANNEL[channel].CFG = tmpReg; +} + +/*! + * brief Prepare channel transfer configurations. + * + * This function used to prepare channel transfer configurations. + * + * param config Pointer to DMA channel transfer configuration structure. + * param srcStartAddr source start address. + * param dstStartAddr destination start address. + * param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. + * param type transfer type. + * param trigger DMA channel trigger configurations. + * param nextDesc address of next descriptor. + */ +void DMA_PrepareChannelTransfer(dma_channel_config_t *config, + void *srcStartAddr, + void *dstStartAddr, + uint32_t xferCfg, + dma_transfer_type_t type, + dma_channel_trigger_t *trigger, + void *nextDesc) +{ + assert((NULL != config) && (NULL != srcStartAddr) && (NULL != dstStartAddr)); + assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); + + /* check max */ + (void)memset(config, 0, sizeof(*config)); + + if (type == kDMA_MemoryToMemory) + { + config->isPeriph = false; + } + else if (type == kDMA_PeripheralToMemory) + { + config->isPeriph = true; + } + else if (type == kDMA_MemoryToPeripheral) + { + config->isPeriph = true; + } + /* kDMA_StaticToStatic */ + else + { + config->isPeriph = true; + } + + config->dstStartAddr = (uint8_t *)dstStartAddr; + config->srcStartAddr = (uint8_t *)srcStartAddr; + config->nextDesc = (uint8_t *)nextDesc; + config->trigger = trigger; + config->xferCfg = xferCfg; +} + +/*! + * brief load channel transfer decriptor. + * + * This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA + * transfer, the head descriptor table is defined in DMA driver, it is useful for the case: + * 1. for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly + * and then call this api to load the configured descriptor to driver descriptor table. code DMA_Init(DMA0); + * DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL); + * DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL); + * DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc); + * DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL); + * while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL)) + * {} + * endcode + * + * param base DMA base address. + * param channel DMA channel. + * param descriptor configured DMA descriptor. + */ +void DMA_LoadChannelDescriptor(DMA_Type *base, uint32_t channel, dma_descriptor_t *descriptor) +{ + assert(NULL != descriptor); + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + + uint32_t instance = DMA_GetInstance(base); + dma_descriptor_t *channelDescriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][channel]); + + channelDescriptor->xfercfg = descriptor->xfercfg; + channelDescriptor->srcEndAddr = descriptor->srcEndAddr; + channelDescriptor->dstEndAddr = descriptor->dstEndAddr; + channelDescriptor->linkToNextDesc = descriptor->linkToNextDesc; + + /* Set channel XFERCFG register according first channel descriptor. */ + base->CHANNEL[channel].XFERCFG = descriptor->xfercfg; +} + +/*! + * brief Install DMA descriptor memory. + * + * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong + * transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has + * a default DMA descriptor buffer, but it support one DMA descriptor for one channel only. + * User should be take care about the address of DMA descriptor pool which required align with 512BYTE. + * + * param handle Pointer to DMA channel transfer handle. + * param addr DMA descriptor address + * param num DMA descriptor number. + */ +void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr) +{ + assert(addr != NULL); + assert((((uint32_t)(uint32_t *)addr) & ((uint32_t)FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0U); + + /* reconfigure the DMA descriptor base address */ + base->SRAMBASE = (uint32_t)(uint32_t *)addr; +} + +/*! + * brief Submit channel transfer paramter directly. + * + * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table + * is defined in DMA driver, it is useful for the case: + * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used + for it. + * code + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, + bytes), srcStartAddr, dstStartAddr, NULL); + DMA_StartTransfer(handle) + * endcode + * + * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is + required, then application should prepare + * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc2); + DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, NULL); + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, + bytes), srcStartAddr, dstStartAddr, nextDesc0); + DMA_StartTransfer(handle); + * endcode + * + * param handle Pointer to DMA handle. + * param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. + * param srcStartAddr source start address. + * param dstStartAddr destination start address. + * param nextDesc address of next descriptor. + */ +void DMA_SubmitChannelTransferParameter( + dma_handle_t *handle, uint32_t xferCfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) +{ + assert((NULL != srcStartAddr) && (NULL != dstStartAddr)); + assert(handle->channel < (uint8_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); + + uint32_t instance = DMA_GetInstance(handle->base); + dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); + + DMA_SetupDescriptor(descriptor, xferCfg, srcStartAddr, dstStartAddr, nextDesc); + + /* Set channel XFERCFG register according first channel descriptor. */ + handle->base->CHANNEL[handle->channel].XFERCFG = xferCfg; +} + +/*! + * brief Submit channel descriptor. + * + * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table + is defined in + * DMA driver, this functiono is typical for the ping pong case: + * + * 1. for the ping pong case, application should responsible for the descriptor, for example, application should + * prepare two descriptor table with macro. + * code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc0); + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelDescriptor(handle, nextDesc0); + DMA_StartTransfer(handle); + * endcode + * + * param handle Pointer to DMA handle. + * param descriptor descriptor to submit. + */ +void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descriptor) +{ + assert((NULL != handle) && (NULL != descriptor)); + + DMA_LoadChannelDescriptor(handle->base, handle->channel, descriptor); +} + +/*! + * brief Submits the DMA channel transfer request. + * + * This function submits the DMA transfer request according to the transfer configuration structure. + * If the user submits the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * It is used for the case: + * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used + for it. + * code + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,NULL); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * endcode + * + * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is + required, then application should prepare + * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc2); + DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, NULL); + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * endcode + * + * 3. for the ping pong case, application should responsible for link descriptor, for example, application should + prepare + * two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc0); + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * endcode + * param handle DMA handle pointer. + * param config Pointer to DMA transfer configuration structure. + * retval kStatus_DMA_Success It means submit transfer request succeed. + * retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config) +{ + assert((NULL != handle) && (NULL != config)); + assert(handle->channel < (uint8_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); + uint32_t instance = DMA_GetInstance(handle->base); + dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); + + /* Previous transfer has not finished */ + if (DMA_ChannelIsActive(handle->base, handle->channel)) + { + return kStatus_DMA_Busy; + } + + /* setup channgel trigger configurations */ + DMA_SetChannelConfig(handle->base, handle->channel, config->trigger, config->isPeriph); + + DMA_SetupChannelDescriptor( + descriptor, config->xferCfg, config->srcStartAddr, config->dstStartAddr, config->nextDesc, + config->trigger == NULL ? kDMA_NoWrap : config->trigger->wrap, + (config->trigger == NULL ? (uint32_t)kDMA_BurstSize1 : + ((uint32_t)config->trigger->burst & (DMA_CHANNEL_CFG_BURSTPOWER_MASK)) >> + DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)); + + /* Set channel XFERCFG register according first channel descriptor. */ + handle->base->CHANNEL[handle->channel].XFERCFG = config->xferCfg; + + return kStatus_Success; +} + +/*! + * brief Submits the DMA transfer request. + * deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer. + * + * This function submits the DMA transfer request according to the transfer configuration structure. + * If the user submits the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * + * param handle DMA handle pointer. + * param config Pointer to DMA transfer configuration structure. + * retval kStatus_DMA_Success It means submit transfer request succeed. + * retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) +{ + assert((NULL != handle) && (NULL != config)); + assert(handle->channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); + + uint32_t instance = DMA_GetInstance(handle->base); + dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); + + /* Previous transfer has not finished */ + if (DMA_ChannelIsActive(handle->base, handle->channel)) + { + return kStatus_DMA_Busy; + } + + /* enable/disable peripheral request */ + if (config->isPeriph) + { + DMA_EnableChannelPeriphRq(handle->base, handle->channel); + } + else + { + DMA_DisableChannelPeriphRq(handle->base, handle->channel); + } + + DMA_CreateDescriptor(descriptor, &config->xfercfg, config->srcAddr, config->dstAddr, config->nextDesc); + /* Set channel XFERCFG register according first channel descriptor. */ + handle->base->CHANNEL[handle->channel].XFERCFG = descriptor->xfercfg; + + return kStatus_Success; +} + +/*! + * brief DMA start transfer. + * + * This function enables the channel request. User can call this function after submitting the transfer request + * It will trigger transfer start with software trigger only when hardware trigger is not used. + * + * param handle DMA handle pointer. + */ +void DMA_StartTransfer(dma_handle_t *handle) +{ + assert(NULL != handle); + + uint32_t channel = handle->channel; + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); + + /* enable channel */ + DMA_EnableChannel(handle->base, channel); + + /* Do software trigger only when HW trigger is not enabled. */ + if ((handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK) == 0U) + { + handle->base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; + } +} + +void DMA_IRQHandle(DMA_Type *base) +{ + dma_handle_t *handle; + uint8_t channel_index; + uint32_t startChannel = DMA_GetVirtualStartChannel(base); + uint32_t i = 0; + + /* Find channels that have completed transfer */ + for (i = 0; i < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base); i++) + { + handle = s_DMAHandle[i + startChannel]; + /* Handle is not present */ + if (NULL == handle) + { + continue; + } + channel_index = DMA_CHANNEL_INDEX(handle->channel); + /* Channel uses INTA flag */ + if ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTA) & (1UL << channel_index)) != 0UL) + { + /* Clear INTA flag */ + DMA_COMMON_REG_SET(handle->base, handle->channel, INTA, (1UL << channel_index)); + if (handle->callback != NULL) + { + (handle->callback)(handle, handle->userData, true, kDMA_IntA); + } + } + /* Channel uses INTB flag */ + if ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTB) & (1UL << channel_index)) != 0UL) + { + /* Clear INTB flag */ + DMA_COMMON_REG_SET(handle->base, handle->channel, INTB, (1UL << channel_index)); + if (handle->callback != NULL) + { + (handle->callback)(handle, handle->userData, true, kDMA_IntB); + } + } + /* Error flag */ + if ((DMA_COMMON_REG_GET(handle->base, handle->channel, ERRINT) & (1UL << channel_index)) != 0UL) + { + /* Clear error flag */ + DMA_COMMON_REG_SET(handle->base, handle->channel, ERRINT, (1UL << channel_index)); + if (handle->callback != NULL) + { + (handle->callback)(handle, handle->userData, false, kDMA_IntError); + } + } + } +} + +void DMA0_DriverIRQHandler(void) +{ + DMA_IRQHandle(DMA0); + SDK_ISR_EXIT_BARRIER; +} + +#if defined(DMA1) +void DMA1_DriverIRQHandler(void) +{ + DMA_IRQHandle(DMA1); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_inputmux.c b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_inputmux.c new file mode 100644 index 000000000..edacd71c4 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_inputmux.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_inputmux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.inputmux" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Initialize INPUTMUX peripheral. + + * This function enables the INPUTMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * + * retval None. + */ +void INPUTMUX_Init(INPUTMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE + CLOCK_EnableClock(kCLOCK_Sct); + CLOCK_EnableClock(kCLOCK_Dma); +#else + CLOCK_EnableClock(kCLOCK_InputMux); +#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Attaches a signal + * + * This function gates the INPUTPMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * param index Destination peripheral to attach the signal to. + * param connection Selects connection. + * + * retval None. + */ +void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection) +{ + uint32_t pmux_id; + uint32_t output_id; + + /* extract pmux to be used */ + pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT; + /* extract function number */ + output_id = ((uint32_t)(connection)) & ((1UL << PMUX_SHIFT) - 1U); + /* programm signal */ + *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4U)) = output_id; +} + +#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) +/*! + * brief Enable/disable a signal + * + * This function gates the INPUTPMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * param signal Enable signal register id and bit offset. + * param enable Selects enable or disable. + * + * retval None. + */ +void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable) +{ + uint32_t ena_id; + uint32_t ena_id_mask = (1UL << (32U - ENA_SHIFT)) - 1U; + uint32_t bit_offset; + +#if defined(FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX) && FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX + uint32_t chmux_offset; + uint32_t chmux_value; + + /* Only enable need to update channel mux */ + if (enable && ((((uint32_t)signal) & (1UL << CHMUX_AVL_SHIFT)) != 0U)) + { + chmux_offset = (((uint32_t)signal) >> CHMUX_OFF_SHIFT) & ((1U << (CHMUX_AVL_SHIFT - CHMUX_OFF_SHIFT)) - 1); + chmux_value = (((uint32_t)signal) >> CHMUX_VAL_SHIFT) & ((1U << (CHMUX_OFF_SHIFT - CHMUX_VAL_SHIFT)) - 1); + *(volatile uint32_t *)(((uint32_t)base) + chmux_offset) = chmux_value; + } + ena_id_mask = (1UL << (CHMUX_VAL_SHIFT - ENA_SHIFT)) - 1U; +#endif + /* extract enable register to be used */ + ena_id = (((uint32_t)signal) >> ENA_SHIFT) & ena_id_mask; + /* extract enable bit offset */ + bit_offset = ((uint32_t)signal) & ((1UL << ENA_SHIFT) - 1U); + /* set signal */ + if (enable) + { + *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1UL << bit_offset); + } + else + { + *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1UL << bit_offset); + } +} +#endif + +/*! + * brief Deinitialize INPUTMUX peripheral. + + * This function disables the INPUTMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * + * retval None. + */ +void INPUTMUX_Deinit(INPUTMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE + CLOCK_DisableClock(kCLOCK_Sct); + CLOCK_DisableClock(kCLOCK_Dma); +#else + CLOCK_DisableClock(kCLOCK_InputMux); +#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_inputmux.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_inputmux.h new file mode 100644 index 000000000..0d67a27b4 --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_inputmux.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_INPUTMUX_H_ +#define _FSL_INPUTMUX_H_ + +#include "fsl_inputmux_connections.h" +#include "fsl_common.h" + +/*! + * @addtogroup inputmux_driver + * @{ + */ + +/*! @file */ +/*! @file fsl_inputmux_connections.h */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Group interrupt driver version for SDK */ +#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*@}*/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Initialize INPUTMUX peripheral. + + * This function enables the INPUTMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * + * @retval None. + */ +void INPUTMUX_Init(INPUTMUX_Type *base); + +/*! + * @brief Attaches a signal + * + * This function gates the INPUTPMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * @param index Destination peripheral to attach the signal to. + * @param connection Selects connection. + * + * @retval None. + */ +void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection); + +#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) +/*! + * @brief Enable/disable a signal + * + * This function gates the INPUTPMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * @param signal Enable signal register id and bit offset. + * @param enable Selects enable or disable. + * + * @retval None. + */ +void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable); +#endif + +/*! + * @brief Deinitialize INPUTMUX peripheral. + + * This function disables the INPUTMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * + * @retval None. + */ +void INPUTMUX_Deinit(INPUTMUX_Type *base); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FSL_INPUTMUX_H_ */ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_inputmux_connections.h b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_inputmux_connections.h new file mode 100644 index 000000000..05340130d --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_inputmux_connections.h @@ -0,0 +1,412 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_INPUTMUX_CONNECTIONS_ +#define _FSL_INPUTMUX_CONNECTIONS_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" +#endif + +/*! + * @addtogroup inputmux_driver + * @{ + */ + +/*! + * @name Input multiplexing connections + * @{ + */ + +/*! @brief Periphinmux IDs */ +#define SCT0_INMUX0 0x00U +#define TIMER0CAPTSEL0 0x20U +#define TIMER1CAPTSEL0 0x40U +#define TIMER2CAPTSEL0 0x60U +#define PINTSEL_PMUX_ID 0xC0U +#define PINTSEL0 0xC0U +#define DMA0_ITRIG_INMUX0 0xE0U +#define DMA0_OTRIG_INMUX0 0x160U +#define FREQMEAS_REF_REG 0x180U +#define FREQMEAS_TARGET_REG 0x184U +#define TIMER3CAPTSEL0 0x1A0U +#define TIMER4CAPTSEL0 0x1C0U +#define PINTSECSEL0 0x1E0U +#define DMA1_ITRIG_INMUX0 0x200U +#define DMA1_OTRIG_INMUX0 0x240U +#define PMUX_SHIFT 20U + +/*! @brief INPUTMUX connections type */ +typedef enum _inputmux_connection_t +{ + /*!< SCT0 INMUX. */ + kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToSct0 = 8U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToSct0 = 9U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToSct0 = 10U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToSct0 = 11U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToSct0 = 12U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_AdcIrqToSct0 = 13U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToSct0 = 14U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Usb1FrameToggleToSct0 = 16U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_CompOutToSct0 = 17U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedSck0ToSct0 = 18U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedSck1ToSct0 = 19U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToSct0 = 20U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToSct0 = 21U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToSct0 = 22U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_DebugHaltedToSct0 = 23U + (SCT0_INMUX0 << PMUX_SHIFT), + + /*!< TIMER0 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer0Captsel = 0U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer0Captsel = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer0Captsel = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer0Captsel = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1FrameToggleToTimer0Captsel = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER1 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer1Captsel = 0U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer1Captsel = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer1Captsel = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer1Captsel = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1FrameToggleToTimer1Captsel = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER2 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer2Captsel = 0U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer2Captsel = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer2Captsel = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer2Captsel = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1FrameToggleToTimer2Captsel = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + + /*!< Pin interrupt select. */ + kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL0 << PMUX_SHIFT), + + /*!< DMA0 Input trigger. */ + kINPUTMUX_PinInt0ToDma0 = 0U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt1ToDma0 = 1U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt2ToDma0 = 2U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt3ToDma0 = 3U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToDma0 = 4U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToDma0 = 5U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToDma0 = 6U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToDma0 = 7U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToDma0 = 8U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToDma0 = 9U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToDma0 = 10U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToDma0 = 11U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToDma0 = 12U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToDma0 = 13U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_CompOutToDma0 = 14U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig0ToDma0 = 15U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig1ToDma0 = 16U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig2ToDma0 = 17U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig3ToDma0 = 18U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Sct0DmaReq0ToDma0 = 19U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Sct0DmaReq1ToDma0 = 20U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_HashDmaRxToDma0 = 21U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + + /*!< DMA0 output trigger. */ + kINPUTMUX_Dma0Hash0TxTrigoutToTriginChannels = 0U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0HsLspiRxTrigoutToTriginChannels = 2U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0HsLspiTxTrigoutToTriginChannels = 3U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm3RxTrigoutToTriginChannels = 8U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm3TxTrigoutToTriginChannels = 9U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm2RxTrigoutToTriginChannels = 10U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm2TxTrigoutToTriginChannels = 11U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm4RxTrigoutToTriginChannels = 12U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm4TxTrigoutToTriginChannels = 13U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm5RxTrigoutToTriginChannels = 14U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm5TxTrigoutToTriginChannels = 15U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm6RxTrigoutToTriginChannels = 16U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm6TxTrigoutToTriginChannels = 17U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm7RxTrigoutToTriginChannels = 18U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm7TxTrigoutToTriginChannels = 19U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Adc0Ch0TrigoutToTriginChannels = 21U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Adc0Ch1TrigoutToTriginChannels = 22U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + + /*!< Selection for frequency measurement reference clock. */ + kINPUTMUX_ExternOscToFreqmeasRef = 0U + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Fro12MhzToFreqmeasRef = 1u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Fro96MhzToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_WdtOscToFreqmeasRef = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_32KhzOscToFreqmeasRef = 4u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_MainClkToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClk_aRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClk_bRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT), + + /*!< Selection for frequency measurement target clock. */ + kINPUTMUX_ExternOscToFreqmeasTarget = 0U + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_Fro12MhzToFreqmeasTarget = 1u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_Fro96MhzToFreqmeasTarget = 2u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_WdtOscToFreqmeasTarget = 3u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_32KhzOscToFreqmeasTarget = 4u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_MainClkToFreqmeasTarget = 5u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClk_aTarget = 6u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClk_bTarget = 7u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + + /*!< TIMER3 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer3Captsel = 0U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer3Captsel = 17U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer3Captsel = 18U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer3Captsel = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1FrameToggleToTimer3Captsel = 21U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + + /*!< Timer4 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer4Captsel = 0U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer4Captsel = 17U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer4Captsel = 18U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer4Captsel = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1FrameToggleToTimer4Captsel = 21U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + + /*Pin interrupt secure select */ + kINPUTMUX_GpioPort0Pin0ToPintSecsel = 0U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin1ToPintSecsel = 1U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin2ToPintSecsel = 2U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin3ToPintSecsel = 3U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin4ToPintSecsel = 4U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin5ToPintSecsel = 5U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin6ToPintSecsel = 6U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin7ToPintSecsel = 7U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin8ToPintSecsel = 8U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin9ToPintSecsel = 9U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin10ToPintSecsel = 10U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin11ToPintSecsel = 11U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin12ToPintSecsel = 12U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin13ToPintSecsel = 13U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin14ToPintSecsel = 14U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin15ToPintSecsel = 15U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin16ToPintSecsel = 16U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin17ToPintSecsel = 17U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin18ToPintSecsel = 18U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin19ToPintSecsel = 19U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin20ToPintSecsel = 20U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin21ToPintSecsel = 21U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin22ToPintSecsel = 22U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin23ToPintSecsel = 23U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin24ToPintSecsel = 24U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin25ToPintSecsel = 25U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin26ToPintSecsel = 26U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin27ToPintSecsel = 27U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin28ToPintSecsel = 28U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin29ToPintSecsel = 29U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin30ToPintSecsel = 30U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin31ToPintSecsel = 31U + (PINTSECSEL0 << PMUX_SHIFT), + + /*!< DMA1 Input trigger. */ + kINPUTMUX_PinInt0ToDma1 = 0U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt1ToDma1 = 1U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt2ToDma1 = 2U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt3ToDma1 = 3U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToDma1 = 4U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToDma1 = 5U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToDma1 = 6U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToDma1 = 7U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig0ToDma1 = 8U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig1ToDma1 = 9U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig2ToDma1 = 10U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig3ToDma1 = 11U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Sct0DmaReq0ToDma1 = 12U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Sct0DmaReq1ToDma1 = 13U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_HashDmaRxToDma1 = 14U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + + /*!< DMA1 output trigger. */ + kINPUTMUX_Dma1Hash0TxTrigoutToTriginChannels = 0U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1HsLspiRxTrigoutToTriginChannels = 2U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1HsLspiTxTrigoutToTriginChannels = 3U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcomm3RxTrigoutToTriginChannels = 8U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcomm3TxTrigoutToTriginChannels = 9U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), +} inputmux_connection_t; + +/*@}*/ + +/*@}*/ + +#endif /* _FSL_INPUTMUX_CONNECTIONS_ */ diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart_dma.c b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart_dma.c new file mode 100644 index 000000000..417c9f27e --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart_dma.c @@ -0,0 +1,314 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_usart.h" +#include "fsl_device_registers.h" +#include "fsl_dma.h" +#include "fsl_flexcomm.h" +#include "fsl_usart_dma.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_dma" +#endif + +/*base, false); + + usartPrivateHandle->handle->txState = (uint8_t)kUSART_TxIdle; + + /* Wait to finish transfer */ + while (0U == (usartPrivateHandle->base->STAT & USART_STAT_TXIDLE_MASK)) + { + } + + if (usartPrivateHandle->handle->callback != NULL) + { + usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_TxIdle, + usartPrivateHandle->handle->userData); + } +} + +static void USART_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode) +{ + assert(handle != NULL); + assert(param != NULL); + + usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param; + + /* Disable UART RX DMA. */ + USART_EnableRxDMA(usartPrivateHandle->base, false); + + usartPrivateHandle->handle->rxState = (uint8_t)kUSART_RxIdle; + + if (usartPrivateHandle->handle->callback != NULL) + { + usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_RxIdle, + usartPrivateHandle->handle->userData); + } +} + +/*! + * brief Initializes the USART handle which is used in transactional functions. + * param base USART peripheral base address. + * param handle Pointer to usart_dma_handle_t structure. + * param callback Callback function. + * param userData User data. + * param txDmaHandle User-requested DMA handle for TX DMA transfer. + * param rxDmaHandle User-requested DMA handle for RX DMA transfer. + */ +status_t USART_TransferCreateHandleDMA(USART_Type *base, + usart_dma_handle_t *handle, + usart_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle) +{ + uint32_t instance = 0; + + /* check 'base' */ + assert(!(NULL == base)); + if (NULL == base) + { + return kStatus_InvalidArgument; + } + /* check 'handle' */ + assert(!(NULL == handle)); + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + + instance = USART_GetInstance(base); + + (void)memset(handle, 0, sizeof(*handle)); + /* assign 'base' and 'handle' */ + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + + /* set tx/rx 'idle' state */ + handle->rxState = (uint8_t)kUSART_RxIdle; + handle->txState = (uint8_t)kUSART_TxIdle; + + handle->callback = callback; + handle->userData = userData; + + handle->rxDmaHandle = rxDmaHandle; + handle->txDmaHandle = txDmaHandle; + + /* Configure TX. */ + if (txDmaHandle != NULL) + { + DMA_SetCallback(txDmaHandle, USART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]); + } + + /* Configure RX. */ + if (rxDmaHandle != NULL) + { + DMA_SetCallback(rxDmaHandle, USART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]); + } + + return kStatus_Success; +} + +/*! + * brief Sends data using DMA. + * + * This function sends data using DMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param xfer USART DMA transfer structure. See #usart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_USART_TxBusy Previous transfer on going. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) +{ + assert(handle != NULL); + assert(handle->txDmaHandle != NULL); + assert(xfer != NULL); + assert(xfer->data != NULL); + assert(xfer->dataSize != 0U); + + dma_transfer_config_t xferConfig; + status_t status; + uint32_t address = (uint32_t)&base->FIFOWR; + + /* If previous TX not finished. */ + if ((uint8_t)kUSART_TxBusy == handle->txState) + { + status = kStatus_USART_TxBusy; + } + else + { + handle->txState = (uint8_t)kUSART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Enable DMA request from txFIFO */ + USART_EnableTxDMA(base, true); + + /* Prepare transfer. */ + DMA_PrepareTransfer(&xferConfig, xfer->data, (uint32_t *)address, sizeof(uint8_t), xfer->dataSize, + kDMA_MemoryToPeripheral, NULL); + + /* Submit transfer. */ + (void)DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); + DMA_StartTransfer(handle->txDmaHandle); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Receives data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * param base USART peripheral base address. + * param handle Pointer to usart_dma_handle_t structure. + * param xfer USART DMA transfer structure. See #usart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_USART_RxBusy Previous transfer on going. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) +{ + assert(handle != NULL); + assert(handle->rxDmaHandle != NULL); + assert(xfer != NULL); + assert(xfer->data != NULL); + assert(xfer->dataSize != 0U); + + dma_transfer_config_t xferConfig; + status_t status; + uint32_t address = (uint32_t)&base->FIFORD; + + /* If previous RX not finished. */ + if ((uint8_t)kUSART_RxBusy == handle->rxState) + { + status = kStatus_USART_RxBusy; + } + else + { + handle->rxState = (uint8_t)kUSART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Enable DMA request from rxFIFO */ + USART_EnableRxDMA(base, true); + + /* Prepare transfer. */ + DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, xfer->data, sizeof(uint8_t), xfer->dataSize, + kDMA_PeripheralToMemory, NULL); + + /* Submit transfer. */ + (void)DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); + DMA_StartTransfer(handle->rxDmaHandle); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the sent data using DMA. + * + * This function aborts send data using DMA. + * + * param base USART peripheral base address + * param handle Pointer to usart_dma_handle_t structure + */ +void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->txDmaHandle); + + /* Stop transfer. */ + DMA_AbortTransfer(handle->txDmaHandle); + handle->txState = (uint8_t)kUSART_TxIdle; +} + +/*! + * brief Aborts the received data using DMA. + * + * This function aborts the received data using DMA. + * + * param base USART peripheral base address + * param handle Pointer to usart_dma_handle_t structure + */ +void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->rxDmaHandle); + + /* Stop transfer. */ + DMA_AbortTransfer(handle->rxDmaHandle); + handle->rxState = (uint8_t)kUSART_RxIdle; +} + +/*! + * brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != handle->rxDmaHandle); + assert(NULL != count); + + if ((uint8_t)kUSART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); + + return kStatus_Success; +} From 1a76171663928e02eafbbccec05b3d440ca9edf0 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Thu, 24 Dec 2020 15:49:37 -0600 Subject: [PATCH 140/617] LPC55xx: fix use of system include in pin_mux.c. --- source/hic_hal/nxp/lpc55xx/pin_mux.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/source/hic_hal/nxp/lpc55xx/pin_mux.c b/source/hic_hal/nxp/lpc55xx/pin_mux.c index 1e60ffe1b..be0822b4b 100644 --- a/source/hic_hal/nxp/lpc55xx/pin_mux.c +++ b/source/hic_hal/nxp/lpc55xx/pin_mux.c @@ -16,8 +16,8 @@ * limitations under the License. */ -#include -#include +#include "fsl_clock.h" +#include "fsl_iocon.h" #include "pin_mux.h" uint32_t USART0_GetFreq(void) From 0a9f14754499c72d4d20b14c0e5da54d30d80c82 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Thu, 24 Dec 2020 18:33:02 -0600 Subject: [PATCH 141/617] LPC55xx: increase main stack size to 0x800. --- records/hic_hal/lpc55s69.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/records/hic_hal/lpc55s69.yaml b/records/hic_hal/lpc55s69.yaml index be71aec54..3400804cf 100644 --- a/records/hic_hal/lpc55s69.yaml +++ b/records/hic_hal/lpc55s69.yaml @@ -63,6 +63,7 @@ tool_specific: - -march=armv8-m.main+fp+dsp - -mfloat-abi=hard - -mfpu=fpv5-sp-d16 + - -Wl,--defsym=__stack_size__=0x800 linker_file: - source/hic_hal/nxp/lpc55xx/gcc/lpc55xx.ld includes: From 82c3c84b0b33c1ced502d6d506f43972fa747e89 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Thu, 24 Dec 2020 18:35:27 -0600 Subject: [PATCH 142/617] LPC55xx: hardware CRC32 with flash readability checking. --- source/hic_hal/nxp/lpc55xx/crc.c | 148 ++++++++++++++++++++++++++ source/hic_hal/nxp/lpc55xx/hic_init.c | 2 + source/hic_hal/nxp/lpc55xx/hic_init.h | 3 + 3 files changed, 153 insertions(+) create mode 100644 source/hic_hal/nxp/lpc55xx/crc.c diff --git a/source/hic_hal/nxp/lpc55xx/crc.c b/source/hic_hal/nxp/lpc55xx/crc.c new file mode 100644 index 000000000..4c08c17bc --- /dev/null +++ b/source/hic_hal/nxp/lpc55xx/crc.c @@ -0,0 +1,148 @@ +/* + * DAPLink Interface Firmware + * Copyright (c) 2020 Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "crc.h" +#include "fsl_crc.h" +#include "flash_hal.h" +#include "daplink_addr.h" +#include "util.h" + +#define TEST_CHECK_VALUE (0) +#define CHECK_VALUE (0xCBF43926) + +#define INITIAL_SEED (0xFFFFFFFF) + +static void crc_checked_write_data(const void *data, int count); +static void crc_write_data_safely(const void *data, int count); + +//! Initialize the CRC engine peripheral for CRC-32. +void hic_crc_init(void) +{ + crc_config_t config = { + .polynomial = kCRC_Polynomial_CRC_32, + .reverseIn = true, + .complementIn = false, + .reverseOut = true, + .complementOut = true, + .seed = INITIAL_SEED, + }; + CRC_Init(CRC_ENGINE, &config); + +#if TEST_CHECK_VALUE + uint32_t sum = crc32("123456789", 9); + if (sum != CHECK_VALUE) { + __BKPT(0); + } + + sum = crc32("1234", 4); + sum = crc32_continue(sum, "56789", 5); + if (sum != CHECK_VALUE) { + __BKPT(0); + } +#endif +} + +//! Test readability of the given buffer. Then either write actual data to the CRC engine, or +//! write fake erased flash data. +void crc_checked_write_data(const void *data, int count) +{ + if (flash_is_readable((uint32_t)data, count)) { + CRC_WriteData(CRC_ENGINE, data, count); + } + else { + // Write full words. + while (count >= sizeof(uint32_t)) { + CRC_ENGINE->WR_DATA = 0xFFFFFFFF; + count -= sizeof(uint32_t); + } + + // Write any trailing bytes. + while (count) { + *((__O uint8_t *)&(CRC_ENGINE->WR_DATA)) = 0xFF; + --count; + } + } +} + +//! Pass data to the CRC engine while ensuring that we don't attempt to read from an erased +//! flash sector. +void crc_write_data_safely(const void *data, int count) +{ + // Skip readability checks if the data is not in flash. + if (!((uint32_t)data >= DAPLINK_ROM_START && (uint32_t)data < (DAPLINK_ROM_START + DAPLINK_ROM_SIZE))) { + CRC_WriteData(CRC_ENGINE, data, count); + return; + } + + // Check leading ragged edge. + uint32_t n = ROUND_UP((uint32_t)data, DAPLINK_SECTOR_SIZE) - (uint32_t)data; + if (n) { + crc_checked_write_data(data, n); + data += n; + count -= n; + } + + // Write sector-size chuncks as they are checked. + while (count >= DAPLINK_SECTOR_SIZE) { + n = MIN(count, DAPLINK_SECTOR_SIZE); + crc_checked_write_data(data, n); + data += n; + count -= n; + } + + // Check trailing ragged edge. + if (count) { + crc_checked_write_data(data, count); + data += count; + count -= count; + } +} + +uint32_t crc32(const void *data, int nBytes) +{ + // Start new CRC with the initial seed, then write the data through the engine. + CRC_ENGINE->SEED = INITIAL_SEED; + crc_write_data_safely(data, nBytes); + + return CRC_ENGINE->SUM; +} + +uint32_t crc32_continue(uint32_t prev_crc, const void *data, int nBytes) +{ + // The previous CRC has been reversed and complemented when read. When writing the SEED register, the + // value will be reversed/complemented according to the MODE input settings. We need to temporarily modify + // the MODE to convert the CRC into a seed. CRC-32 input reverses the data, which the previous CRC has + // already been, but does not complement, though the previous CRC has been. So we need to disable reverse + // and enable complement. + uint32_t mode = CRC_ENGINE->MODE; + CRC_ENGINE->MODE = mode & ~(CRC_MODE_BIT_RVS_WR_MASK | CRC_MODE_CMPL_WR_MASK); + + // Undo post-processing. + prev_crc = __RBIT(prev_crc ^ 0xFFFFFFFF); + + // Continue with the previous CRC, then write the data through the engine. + CRC_ENGINE->SEED = prev_crc; + + // Restore original CRC sum bit reverse and 1's complement setting. + CRC_ENGINE->MODE = mode; + + crc_write_data_safely(data, nBytes); + return CRC_ENGINE->SUM; +} + + diff --git a/source/hic_hal/nxp/lpc55xx/hic_init.c b/source/hic_hal/nxp/lpc55xx/hic_init.c index 71136bd83..2e4cb9bb6 100644 --- a/source/hic_hal/nxp/lpc55xx/hic_init.c +++ b/source/hic_hal/nxp/lpc55xx/hic_init.c @@ -160,6 +160,8 @@ void BOARD_BootClockPLL150M(void) void sdk_init(void) { BOARD_BootClockFROHF96M(); + + hic_crc_init(); } //! - Configure the VBUS pin. diff --git a/source/hic_hal/nxp/lpc55xx/hic_init.h b/source/hic_hal/nxp/lpc55xx/hic_init.h index ce9499dae..ce9c1c221 100644 --- a/source/hic_hal/nxp/lpc55xx/hic_init.h +++ b/source/hic_hal/nxp/lpc55xx/hic_init.h @@ -32,6 +32,9 @@ extern "C" { //! @brief Set some system-wide hardware settings. void hic_init(void); +//! @brief Init CRC peripheral. +void hic_crc_init(void); + //! @brief Enable clocks required for USB operation. void hic_enable_usb_clocks(void); From 90f6baf2756ceae795fa453f5c9e091ac6987e36 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Thu, 24 Dec 2020 18:35:47 -0600 Subject: [PATCH 143/617] LPC55xx: re-enable CRC computation in info.c. --- source/daplink/info.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/source/daplink/info.c b/source/daplink/info.c index 41ecd8b1a..5be10d8e7 100644 --- a/source/daplink/info.c +++ b/source/daplink/info.c @@ -294,38 +294,22 @@ void info_crc_compute() // Compute the CRCs of regions that exist if ((DAPLINK_ROM_BL_SIZE > 0) && flash_is_readable(DAPLINK_ROM_BL_START, DAPLINK_ROM_BL_SIZE - 4)) { -#ifdef INTERFACE_LPC55XX // FIXME: CRC - crc_bootloader = 0; -#else crc_bootloader = crc32((void *)DAPLINK_ROM_BL_START, DAPLINK_ROM_BL_SIZE - 4); -#endif } if ((DAPLINK_ROM_IF_SIZE > 0) && flash_is_readable(DAPLINK_ROM_IF_START, DAPLINK_ROM_IF_SIZE - 4)) { -#ifdef INTERFACE_LPC55XX // FIXME: CRC - crc_interface = 0; -#else crc_interface = crc32((void *)DAPLINK_ROM_IF_START, DAPLINK_ROM_IF_SIZE - 4); -#endif } if ((DAPLINK_ROM_CONFIG_ADMIN_SIZE > 0) && flash_is_readable(DAPLINK_ROM_CONFIG_ADMIN_START, DAPLINK_ROM_CONFIG_ADMIN_SIZE)) { -#ifdef INTERFACE_LPC55XX // FIXME: CRC - crc_config_admin = 0; -#else crc_config_admin = crc32((void *)DAPLINK_ROM_CONFIG_ADMIN_START, DAPLINK_ROM_CONFIG_ADMIN_SIZE); -#endif } if ((DAPLINK_ROM_CONFIG_USER_SIZE > 0) && flash_is_readable(DAPLINK_ROM_CONFIG_USER_START, DAPLINK_ROM_CONFIG_USER_SIZE)) { -#ifdef INTERFACE_LPC55XX // FIXME: CRC - crc_config_user = 0; -#else crc_config_user = crc32((void *)DAPLINK_ROM_CONFIG_USER_START, DAPLINK_ROM_CONFIG_USER_SIZE); -#endif } } From a4695170a33532a70daee0340db4fabf3fa1b2ac Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Thu, 24 Dec 2020 18:46:19 -0600 Subject: [PATCH 144/617] LPC55xx: fix dumb inverted assert condition in flash_is_readable(). --- source/hic_hal/nxp/lpc55xx/hic_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/hic_hal/nxp/lpc55xx/hic_init.c b/source/hic_hal/nxp/lpc55xx/hic_init.c index 2e4cb9bb6..a3afbfa3e 100644 --- a/source/hic_hal/nxp/lpc55xx/hic_init.c +++ b/source/hic_hal/nxp/lpc55xx/hic_init.c @@ -221,7 +221,7 @@ void hic_power_target(void) bool flash_is_readable(uint32_t addr, uint32_t length) { // Make sure the core clock is less than 100 MHz, or flash commands won't work. - util_assert(SystemCoreClock > 100000000); + util_assert(SystemCoreClock < 100000000); // Return true if the address is within internal flash and the flash sector is not erased. if (!(addr >= DAPLINK_ROM_START && addr < (DAPLINK_ROM_START + DAPLINK_ROM_SIZE))) { From 0e0f07ea07c95152bc5f2a79d2babac52e45490e Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Thu, 24 Dec 2020 19:02:50 -0600 Subject: [PATCH 145/617] LPC55xx: fix validate_bin_nvic_base(). --- source/daplink/validation.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/daplink/validation.c b/source/daplink/validation.c index 1e3920057..0a3134f89 100644 --- a/source/daplink/validation.c +++ b/source/daplink/validation.c @@ -41,7 +41,7 @@ uint8_t validate_bin_nvic(const uint8_t *buf) uint8_t validate_bin_nvic_base(const uint8_t *buf) { - if (!g_board_info.target_cfg) { + if (g_board_info.target_cfg) { uint32_t i = 4, nvic_val = 0; uint8_t in_range = 0; // test the initial SP value From 5966b1dd9f50affebfc4537e42e325bf4c70a49a Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 1 Jan 2021 23:20:47 -0600 Subject: [PATCH 146/617] LPC55xx: fix library path --- .../lpc55xx/{ => LPC55S69}/gcc/libpower_hardabi.a | Bin 1 file changed, 0 insertions(+), 0 deletions(-) rename source/hic_hal/nxp/lpc55xx/{ => LPC55S69}/gcc/libpower_hardabi.a (100%) diff --git a/source/hic_hal/nxp/lpc55xx/gcc/libpower_hardabi.a b/source/hic_hal/nxp/lpc55xx/LPC55S69/gcc/libpower_hardabi.a similarity index 100% rename from source/hic_hal/nxp/lpc55xx/gcc/libpower_hardabi.a rename to source/hic_hal/nxp/lpc55xx/LPC55S69/gcc/libpower_hardabi.a From 363870ea53dd6b832b7a28c43c8b5e4616a465a9 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Fri, 1 Jan 2021 15:44:05 -0600 Subject: [PATCH 147/617] LPC55xx: correct bootloader target_device RAM regions addresses. --- source/board/lpc55s69_bl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/source/board/lpc55s69_bl.c b/source/board/lpc55s69_bl.c index baada80fb..fcb53e267 100644 --- a/source/board/lpc55s69_bl.c +++ b/source/board/lpc55s69_bl.c @@ -50,8 +50,8 @@ target_cfg_t target_device = { .flash_regions[0].start = DAPLINK_ROM_IF_START, .flash_regions[0].end = DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE, .flash_regions[0].flags = kRegionIsDefault, - .ram_regions[0].start = 0x30000000, - .ram_regions[0].end = 0x30040000, + .ram_regions[0].start = 0x20000000, + .ram_regions[0].end = 0x20040000, /* .flash_algo not needed for bootloader */ }; From 308f7ac970a5f80acc728b5e46438fac6778badf Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Mon, 4 Jan 2021 17:23:10 -0600 Subject: [PATCH 148/617] Update CMSIS Core headers. --- source/cmsis-core/cachel1_armv7.h | 411 +++ source/cmsis-core/cmsis_armcc.h | 11 +- source/cmsis-core/cmsis_armclang.h | 113 +- source/cmsis-core/cmsis_armclang_ltm.h | 10 +- source/cmsis-core/cmsis_gcc.h | 27 +- source/cmsis-core/cmsis_iccarm.h | 13 +- source/cmsis-core/core_armv81mml.h | 1574 ++++++++- source/cmsis-core/core_armv8mbl.h | 423 ++- source/cmsis-core/core_armv8mml.h | 536 ++- source/cmsis-core/core_cm23.h | 423 ++- source/cmsis-core/core_cm3.h | 9 +- source/cmsis-core/core_cm33.h | 531 ++- source/cmsis-core/core_cm35p.h | 533 ++- source/cmsis-core/core_cm4.h | 9 +- source/cmsis-core/core_cm55.h | 4242 ++++++++++++++++++++++++ source/cmsis-core/core_cm7.h | 403 +-- source/cmsis-core/core_sc000.h | 9 +- source/cmsis-core/core_sc300.h | 9 +- source/cmsis-core/mpu_armv7.h | 13 +- source/cmsis-core/mpu_armv8.h | 12 +- source/cmsis-core/pmu_armv8.h | 337 ++ 21 files changed, 8640 insertions(+), 1008 deletions(-) create mode 100644 source/cmsis-core/cachel1_armv7.h create mode 100644 source/cmsis-core/core_cm55.h create mode 100644 source/cmsis-core/pmu_armv8.h diff --git a/source/cmsis-core/cachel1_armv7.h b/source/cmsis-core/cachel1_armv7.h new file mode 100644 index 000000000..d2c3e2291 --- /dev/null +++ b/source/cmsis-core/cachel1_armv7.h @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.0 + * @date 03. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/source/cmsis-core/cmsis_armcc.h b/source/cmsis-core/cmsis_armcc.h index 548250bfa..237ff6ec3 100644 --- a/source/cmsis-core/cmsis_armcc.h +++ b/source/cmsis-core/cmsis_armcc.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_armcc.h * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file - * @version V5.1.1 - * @date 30. July 2019 + * @version V5.2.1 + * @date 26. March 2020 ******************************************************************************/ /* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -46,6 +46,7 @@ /* __ARM_ARCH_8M_BASE__ not applicable */ /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ /* CMSIS compiler control DSP macros */ #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) @@ -127,7 +128,7 @@ #endif #ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) #endif /* ########################### Core Function Access ########################### */ @@ -875,6 +876,8 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ ((int64_t)(ARG3) << 32U) ) >> 32U)) +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /*@} end of group CMSIS_SIMD_intrinsics */ diff --git a/source/cmsis-core/cmsis_armclang.h b/source/cmsis-core/cmsis_armclang.h index 6a0e8dc7b..90de9dbf8 100644 --- a/source/cmsis-core/cmsis_armclang.h +++ b/source/cmsis-core/cmsis_armclang.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_armclang.h * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V5.2.1 - * @date 30. July 2019 + * @version V5.3.1 + * @date 26. March 2020 ******************************************************************************/ /* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -133,7 +133,7 @@ #endif #ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) #endif /* ########################### Core Function Access ########################### */ @@ -443,9 +443,10 @@ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) #endif -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. @@ -581,26 +582,29 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) } #endif -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) /** \brief Get Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. - + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; @@ -623,7 +627,8 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else @@ -640,13 +645,14 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. - + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; @@ -668,7 +674,8 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) */ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else @@ -688,7 +695,8 @@ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) */ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; @@ -711,7 +719,8 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else @@ -733,7 +742,8 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) */ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; @@ -754,7 +764,8 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) */ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else @@ -763,8 +774,9 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) } #endif -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ /** \brief Get FPSCR @@ -953,10 +965,12 @@ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) } -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. @@ -1023,15 +1037,17 @@ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) */ #define __CLREX __builtin_arm_clrex -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) /** \brief Signed Saturate @@ -1149,9 +1165,10 @@ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ /** \brief Signed Saturate @@ -1202,13 +1219,16 @@ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) return (uint32_t)val; } -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. @@ -1349,8 +1369,9 @@ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) */ #define __STLEX (uint32_t)__builtin_arm_stlex -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ @@ -1429,6 +1450,8 @@ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; diff --git a/source/cmsis-core/cmsis_armclang_ltm.h b/source/cmsis-core/cmsis_armclang_ltm.h index d9f8b8b54..0e5c7349d 100644 --- a/source/cmsis-core/cmsis_armclang_ltm.h +++ b/source/cmsis-core/cmsis_armclang_ltm.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_armclang_ltm.h * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V1.2.1 - * @date 30. July 2019 + * @version V1.3.0 + * @date 26. March 2020 ******************************************************************************/ /* - * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -133,7 +133,7 @@ #endif #ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) #endif @@ -1876,6 +1876,8 @@ __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; diff --git a/source/cmsis-core/cmsis_gcc.h b/source/cmsis-core/cmsis_gcc.h index 6cfd83185..199336b04 100644 --- a/source/cmsis-core/cmsis_gcc.h +++ b/source/cmsis-core/cmsis_gcc.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_gcc.h * @brief CMSIS compiler GCC header file - * @version V5.2.1 - * @date 30. July 2019 + * @version V5.3.0 + * @date 26. March 2020 ******************************************************************************/ /* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -179,7 +179,7 @@ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) #endif #ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) #endif /* ########################### Core Function Access ########################### */ @@ -1962,6 +1962,17 @@ __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) return(result); } +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; @@ -2126,7 +2137,7 @@ __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) return(result); } -#if 0 + #define __PKHBT(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ @@ -2143,13 +2154,7 @@ __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) -#endif - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { diff --git a/source/cmsis-core/cmsis_iccarm.h b/source/cmsis-core/cmsis_iccarm.h index 4020ad76e..58e8e360c 100644 --- a/source/cmsis-core/cmsis_iccarm.h +++ b/source/cmsis-core/cmsis_iccarm.h @@ -1,14 +1,16 @@ /**************************************************************************//** * @file cmsis_iccarm.h * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.1.1 - * @date 30. July 2019 + * @version V5.2.0 + * @date 28. January 2020 ******************************************************************************/ //------------------------------------------------------------------------------ // -// Copyright (c) 2017-2019 IAR Systems -// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// Copyright (c) 2017-2020 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 // // Licensed under the Apache License, Version 2.0 (the "License") // you may not use this file except in compliance with the License. @@ -236,6 +238,7 @@ __packed struct __iar_u32 { uint32_t v; }; #endif #endif +#undef __WEAK /* undo the definition from DLib_Defaults.h */ #ifndef __WEAK #if __ICCARM_V8 #define __WEAK __attribute__((weak)) @@ -961,4 +964,6 @@ __packed struct __iar_u32 { uint32_t v; }; #pragma diag_default=Pe940 #pragma diag_default=Pe177 +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + #endif /* __CMSIS_ICCARM_H__ */ diff --git a/source/cmsis-core/core_armv81mml.h b/source/cmsis-core/core_armv81mml.h index 6ab0df394..571b7f07e 100644 --- a/source/cmsis-core/core_armv81mml.h +++ b/source/cmsis-core/core_armv81mml.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_armv81mml.h * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File - * @version V1.2.0 - * @date 21. October 2019 + * @version V1.4.0 + * @date 15. April 2020 ******************************************************************************/ /* - * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -23,9 +23,11 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ + #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ #endif #ifndef __CORE_ARMV81MML_H_GENERIC @@ -61,15 +63,14 @@ */ #include "cmsis_version.h" - -#define __ARM_ARCH_8M_MAIN__ 1 // patching for now + /* CMSIS ARMV81MML definitions */ #define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ -#define __CORTEX_M (81U) /*!< Cortex-M Core */ +#define __CORTEX_M (81U) /*!< Cortex-M Core */ #if defined ( __CC_ARM ) #error Legacy Arm Compiler does not support Armv8.1-M target architecture. @@ -90,22 +91,11 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif - - #if defined(__ARM_FEATURE_MVE) - #if defined(__MVE_PRESENT) && (__MVE_PRESENT == 1U) - #define __MVE_USED 1U - #else - #error "Compiler generates MVE instructions for a devices without MVE extensions (check __MVE_PRESENT)" - #define __MVE_USED 0U - #endif - #else - #define __MVE_USED 0U - #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) @@ -118,29 +108,18 @@ #else #define __FPU_USED 0U #endif - + #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif - - #if defined(__ARM_FEATURE_MVE) - #if defined(__MVE_PRESENT) && (__MVE_PRESENT == 1U) - #define __MVE_USED 1U - #else - #error "Compiler generates MVE instructions for a devices without MVE extensions (check __MVE_PRESENT)" - #define __MVE_USED 0U - #endif - #else - #define __MVE_USED 0U - #endif - + #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) @@ -158,23 +137,12 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif - #if defined(__ARM_FEATURE_MVE) - #if defined(__MVE_PRESENT) && (__MVE_PRESENT == 1U) - #define __MVE_USED 1U - #else - #error "Compiler generates MVE instructions for a devices without MVE extensions (check __MVE_PRESENT)" - #define __MVE_USED 0U - #endif - #else - #define __MVE_USED 0U - #endif - #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) @@ -242,12 +210,43 @@ #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif - + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" @@ -258,11 +257,11 @@ #warning "__DSP_PRESENT not defined in device header file; using default!" #endif - #ifndef __MVE_PRESENT - #define __MVE_PRESENT 0U - #warning "__MVE_PRESENT not defined in device header file; using default!" + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif - + #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" @@ -1447,6 +1446,823 @@ typedef struct /*@}*/ /* end of group CMSIS_TPI */ +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[4]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */ + uint32_t RESERVED14[3]; + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** @@ -1667,9 +2483,9 @@ typedef struct __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ @@ -1747,7 +2563,7 @@ typedef struct #define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ #define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ -/* Media and FP Feature Register 0 Definitions */ +/* Media and VFP Feature Register 0 Definitions */ #define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ #define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ @@ -1766,7 +2582,7 @@ typedef struct #define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ #define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ -/* Media and FP Feature Register 1 Definitions */ +/* Media and VFP Feature Register 1 Definitions */ #define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ @@ -1785,13 +2601,13 @@ typedef struct #define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ -/* Media and FP Feature Register 2 Definitions */ +/* Media and VFP Feature Register 2 Definitions */ #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ /*@} end of group CMSIS_FPU */ - +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) @@ -1800,7 +2616,7 @@ typedef struct */ /** - \brief Structure type to access the Core Debug Register (CoreDebug). + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { @@ -1814,155 +2630,431 @@ typedef struct } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ -#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< CoreDebug DHCSR: S_FPD Position */ -#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< CoreDebug DHCSR: S_FPD Mask */ +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ -#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< CoreDebug DHCSR: S_SUIDE Position */ -#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< CoreDebug DHCSR: S_SUIDE Mask */ +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ -#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< CoreDebug DHCSR: S_NSUIDE Position */ -#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< CoreDebug DHCSR: S_NSUIDE Mask */ +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ -#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< CoreDebug DHCSR: S_SDE Position */ -#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< CoreDebug DHCSR: S_SDE Mask */ +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ -#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< CoreDebug DHCSR: C_PMOV Position */ -#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< CoreDebug DHCSR: C_PMOV Mask */ +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Set Clear Exception and Monitor Control Register Definitions */ -#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< CoreDebug DSCEMCR: CLR_MON_REQ, Position */ -#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ -#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< CoreDebug DSCEMCR: CLR_MON_PEND, Position */ -#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ -#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< CoreDebug DSCEMCR: SET_MON_REQ, Position */ -#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< CoreDebug DSCEMCR: SET_MON_REQ, Mask */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ -#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< CoreDebug DSCEMCR: SET_MON_PEND, Position */ -#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< CoreDebug DSCEMCR: SET_MON_PEND, Mask */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ /* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< CoreDebug DAUTHCTRL: UIDEN, Position */ -#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< CoreDebug DAUTHCTRL: UIDEN, Mask */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ -#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< CoreDebug DAUTHCTRL: UIDAPEN, Position */ -#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< CoreDebug DAUTHCTRL: UIDAPEN, Mask */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ -#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< CoreDebug DAUTHCTRL: FSDMA, Position */ -#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< CoreDebug DAUTHCTRL: FSDMA, Mask */ +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros @@ -2001,7 +3093,9 @@ typedef struct #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ @@ -2013,13 +3107,20 @@ typedef struct #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ @@ -2030,7 +3131,9 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ @@ -2039,7 +3142,9 @@ typedef struct #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ @@ -2719,6 +3824,14 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) #endif +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface @@ -2757,6 +3870,49 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void) /*@} end of CMSIS_Core_FpuFunctions */ +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif /* ########################## SAU functions #################################### */ @@ -2796,6 +3952,110 @@ __STATIC_INLINE void TZ_SAU_Disable(void) +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface diff --git a/source/cmsis-core/core_armv8mbl.h b/source/cmsis-core/core_armv8mbl.h index 344dca514..932d3d188 100644 --- a/source/cmsis-core/core_armv8mbl.h +++ b/source/cmsis-core/core_armv8mbl.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_armv8mbl.h * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File - * @version V5.0.8 - * @date 12. November 2018 + * @version V5.1.0 + * @date 27. March 2020 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -23,9 +23,11 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ + #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ #endif #ifndef __CORE_ARMV8MBL_H_GENERIC @@ -68,7 +70,7 @@ #define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ -#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ +#define __CORTEX_M (2U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all @@ -975,6 +977,7 @@ typedef struct #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) @@ -983,7 +986,7 @@ typedef struct */ /** - \brief Structure type to access the Core Debug Register (CoreDebug). + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { @@ -991,91 +994,276 @@ typedef struct __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; + uint32_t RESERVED0[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros @@ -1113,7 +1301,9 @@ typedef struct #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ @@ -1124,7 +1314,9 @@ typedef struct #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ @@ -1138,7 +1330,9 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ @@ -1146,7 +1340,9 @@ typedef struct #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ @@ -1163,6 +1359,7 @@ typedef struct Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions + - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** @@ -1838,6 +2035,110 @@ __STATIC_INLINE void TZ_SAU_Disable(void) +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface diff --git a/source/cmsis-core/core_armv8mml.h b/source/cmsis-core/core_armv8mml.h index 5ddb8aeda..a046d9980 100644 --- a/source/cmsis-core/core_armv8mml.h +++ b/source/cmsis-core/core_armv8mml.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_armv8mml.h * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File - * @version V5.1.0 - * @date 12. September 2018 + * @version V5.2.1 + * @date 19. August 2020 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -23,9 +23,11 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ + #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ #endif #ifndef __CORE_ARMV8MML_H_GENERIC @@ -68,7 +70,7 @@ #define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ -#define __CORTEX_M (81U) /*!< Cortex-M Core */ +#define __CORTEX_M (80U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. @@ -248,6 +250,11 @@ #warning "__DSP_PRESENT not defined in device header file; using default!" #endif + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" @@ -538,6 +545,7 @@ typedef struct __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ } SCB_Type; /* SCB CPUID Register Definitions */ @@ -1593,8 +1601,9 @@ typedef struct __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ @@ -1666,7 +1675,7 @@ typedef struct #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ -/* Media and FP Feature Register 0 Definitions */ +/* Media and VFP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ @@ -1691,7 +1700,7 @@ typedef struct #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ -/* Media and FP Feature Register 1 Definitions */ +/* Media and VFP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ @@ -1704,9 +1713,13 @@ typedef struct #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ -/*@} end of group CMSIS_FPU */ +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ +/*@} end of group CMSIS_FPU */ +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) @@ -1715,7 +1728,7 @@ typedef struct */ /** - \brief Structure type to access the Core Debug Register (CoreDebug). + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { @@ -1723,124 +1736,354 @@ typedef struct __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; + uint32_t RESERVED0[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros @@ -1879,7 +2122,9 @@ typedef struct #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ @@ -1891,7 +2136,9 @@ typedef struct #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ @@ -1908,7 +2155,9 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ @@ -1917,7 +2166,9 @@ typedef struct #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ @@ -2636,6 +2887,13 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void) /*@} end of CMSIS_Core_FpuFunctions */ +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + /* ########################## SAU functions #################################### */ /** @@ -2674,6 +2932,110 @@ __STATIC_INLINE void TZ_SAU_Disable(void) +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface diff --git a/source/cmsis-core/core_cm23.h b/source/cmsis-core/core_cm23.h index b79c6af0b..55fff9950 100644 --- a/source/cmsis-core/core_cm23.h +++ b/source/cmsis-core/core_cm23.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_cm23.h * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File - * @version V5.0.8 - * @date 12. November 2018 + * @version V5.1.0 + * @date 11. February 2020 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -23,9 +23,11 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ + #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ #endif #ifndef __CORE_CM23_H_GENERIC @@ -1050,6 +1052,7 @@ typedef struct #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) @@ -1058,7 +1061,7 @@ typedef struct */ /** - \brief Structure type to access the Core Debug Register (CoreDebug). + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { @@ -1066,91 +1069,276 @@ typedef struct __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; + uint32_t RESERVED0[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros @@ -1188,7 +1376,9 @@ typedef struct #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ @@ -1199,7 +1389,9 @@ typedef struct #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ @@ -1213,7 +1405,9 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ @@ -1221,7 +1415,9 @@ typedef struct #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ @@ -1238,6 +1434,7 @@ typedef struct Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions + - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** @@ -1304,11 +1501,11 @@ typedef struct /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else +#else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif - + /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) @@ -1913,6 +2110,110 @@ __STATIC_INLINE void TZ_SAU_Disable(void) +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface diff --git a/source/cmsis-core/core_cm3.h b/source/cmsis-core/core_cm3.h index e568fa38e..24453a886 100644 --- a/source/cmsis-core/core_cm3.h +++ b/source/cmsis-core/core_cm3.h @@ -2,10 +2,10 @@ * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File * @version V5.1.1 - * @date 19. August 2019 + * @date 27. March 2020 ******************************************************************************/ /* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -142,6 +142,11 @@ #warning "__MPU_PRESENT not defined in device header file; using default!" #endif + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" diff --git a/source/cmsis-core/core_cm33.h b/source/cmsis-core/core_cm33.h index 7fed59a88..edd06c066 100644 --- a/source/cmsis-core/core_cm33.h +++ b/source/cmsis-core/core_cm33.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_cm33.h * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File - * @version V5.1.0 - * @date 12. November 2018 + * @version V5.2.1 + * @date 19. August 2020 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -23,9 +23,11 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ + #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ #endif #ifndef __CORE_CM33_H_GENERIC @@ -248,6 +250,11 @@ #warning "__DSP_PRESENT not defined in device header file; using default!" #endif + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" @@ -538,6 +545,7 @@ typedef struct __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ } SCB_Type; /* SCB CPUID Register Definitions */ @@ -1668,8 +1676,9 @@ typedef struct __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ @@ -1741,7 +1750,7 @@ typedef struct #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ -/* Media and FP Feature Register 0 Definitions */ +/* Media and VFP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ @@ -1766,7 +1775,7 @@ typedef struct #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ -/* Media and FP Feature Register 1 Definitions */ +/* Media and VFP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ @@ -1779,9 +1788,13 @@ typedef struct #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ -/*@} end of group CMSIS_FPU */ +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ +/*@} end of group CMSIS_FPU */ +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) @@ -1790,7 +1803,7 @@ typedef struct */ /** - \brief Structure type to access the Core Debug Register (CoreDebug). + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { @@ -1798,124 +1811,354 @@ typedef struct __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; + uint32_t RESERVED0[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros @@ -1954,7 +2197,9 @@ typedef struct #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ @@ -1966,7 +2211,9 @@ typedef struct #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ @@ -1983,7 +2230,9 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ @@ -1992,7 +2241,9 @@ typedef struct #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ @@ -2064,7 +2315,7 @@ typedef struct /* Special LR values for Secure/Non-Secure call handling and exception handling */ -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ @@ -2079,7 +2330,7 @@ typedef struct /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else +#else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif @@ -2749,6 +3000,110 @@ __STATIC_INLINE void TZ_SAU_Disable(void) +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface diff --git a/source/cmsis-core/core_cm35p.h b/source/cmsis-core/core_cm35p.h index 5579c8230..94e6f8084 100644 --- a/source/cmsis-core/core_cm35p.h +++ b/source/cmsis-core/core_cm35p.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_cm35p.h * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File - * @version V1.0.0 - * @date 12. November 2018 + * @version V1.1.1 + * @date 19. August 2020 ******************************************************************************/ /* - * Copyright (c) 2018 Arm Limited. All rights reserved. + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -23,9 +23,11 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ + #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ #endif #ifndef __CORE_CM35P_H_GENERIC @@ -247,7 +249,12 @@ #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif - + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" @@ -538,6 +545,7 @@ typedef struct __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ } SCB_Type; /* SCB CPUID Register Definitions */ @@ -1668,8 +1676,9 @@ typedef struct __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ @@ -1741,7 +1750,7 @@ typedef struct #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ -/* Media and FP Feature Register 0 Definitions */ +/* Media and VFP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ @@ -1766,7 +1775,7 @@ typedef struct #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ -/* Media and FP Feature Register 1 Definitions */ +/* Media and VFP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ @@ -1779,9 +1788,13 @@ typedef struct #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ -/*@} end of group CMSIS_FPU */ +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ +/*@} end of group CMSIS_FPU */ +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) @@ -1790,7 +1803,7 @@ typedef struct */ /** - \brief Structure type to access the Core Debug Register (CoreDebug). + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { @@ -1798,124 +1811,354 @@ typedef struct __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; + uint32_t RESERVED0[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros @@ -1954,7 +2197,9 @@ typedef struct #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ @@ -1966,7 +2211,9 @@ typedef struct #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ @@ -1983,7 +2230,9 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ @@ -1992,7 +2241,9 @@ typedef struct #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ @@ -2064,7 +2315,7 @@ typedef struct /* Special LR values for Secure/Non-Secure call handling and exception handling */ -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ @@ -2079,7 +2330,7 @@ typedef struct /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else +#else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif @@ -2749,6 +3000,110 @@ __STATIC_INLINE void TZ_SAU_Disable(void) +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface diff --git a/source/cmsis-core/core_cm4.h b/source/cmsis-core/core_cm4.h index cfd5af232..4e0e88669 100644 --- a/source/cmsis-core/core_cm4.h +++ b/source/cmsis-core/core_cm4.h @@ -2,10 +2,10 @@ * @file core_cm4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File * @version V5.1.1 - * @date 19. August 2019 + * @date 27. March 2020 ******************************************************************************/ /* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -194,6 +194,11 @@ #warning "__MPU_PRESENT not defined in device header file; using default!" #endif + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" diff --git a/source/cmsis-core/core_cm55.h b/source/cmsis-core/core_cm55.h new file mode 100644 index 000000000..f9f3ff00e --- /dev/null +++ b/source/cmsis-core/core_cm55.h @@ -0,0 +1,4242 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.1.0 + * @date 15. April 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_CM55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[4]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */ + uint32_t RESERVED14[3]; + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/source/cmsis-core/core_cm7.h b/source/cmsis-core/core_cm7.h index 815075e9a..5c14003ac 100644 --- a/source/cmsis-core/core_cm7.h +++ b/source/cmsis-core/core_cm7.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_cm7.h * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V5.1.2 - * @date 19. August 2019 + * @version V5.1.5 + * @date 03. November 2020 ******************************************************************************/ /* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -209,6 +209,11 @@ #warning "__DTCM_PRESENT not defined in device header file; using default!" #endif + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" @@ -496,7 +501,8 @@ typedef struct __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ + uint32_t RESERVED7[5U]; __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ @@ -870,21 +876,24 @@ typedef struct #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ +#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ + +#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ +#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ /* AHBS Control Register Definitions */ #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ /* Auxiliary Bus Fault Status Register Definitions */ #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ @@ -2218,380 +2227,12 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void) /*@} end of CMSIS_Core_FpuFunctions */ - /* ########################## Cache functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - -#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ -#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_FORCEINLINE void SCB_EnableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ - - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_FORCEINLINE void SCB_DisableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_FORCEINLINE void SCB_InvalidateICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief I-Cache Invalidate by address - \details Invalidates I-Cache for the given address. - I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. - I-Cache memory blocks which are part of given address + given size are invalidated. - \param[in] addr address - \param[in] isize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - if ( isize > 0 ) { - int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_ICACHE_LINE_SIZE; - op_size -= __SCB_ICACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_FORCEINLINE void SCB_EnableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_FORCEINLINE void SCB_DisableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_FORCEINLINE void SCB_CleanDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address. - D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are invalidated. - \param[in] addr address - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are cleaned. - \param[in] addr address - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - -/*@} end of CMSIS_Core_CacheFunctions */ +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif /* ################################## SysTick function ############################################ */ diff --git a/source/cmsis-core/core_sc000.h b/source/cmsis-core/core_sc000.h index a8a406176..dbc755fff 100644 --- a/source/cmsis-core/core_sc000.h +++ b/source/cmsis-core/core_sc000.h @@ -2,10 +2,10 @@ * @file core_sc000.h * @brief CMSIS SC000 Core Peripheral Access Layer Header File * @version V5.0.7 - * @date 19. August 2019 + * @date 27. March 2020 ******************************************************************************/ /* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -142,6 +142,11 @@ #warning "__MPU_PRESENT not defined in device header file; using default!" #endif + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" diff --git a/source/cmsis-core/core_sc300.h b/source/cmsis-core/core_sc300.h index f3f2024cb..e8914ba60 100644 --- a/source/cmsis-core/core_sc300.h +++ b/source/cmsis-core/core_sc300.h @@ -2,10 +2,10 @@ * @file core_sc300.h * @brief CMSIS SC300 Core Peripheral Access Layer Header File * @version V5.0.9 - * @date 19. August 2019 + * @date 27. March 2020 ******************************************************************************/ /* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -142,6 +142,11 @@ #warning "__MPU_PRESENT not defined in device header file; using default!" #endif + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" diff --git a/source/cmsis-core/mpu_armv7.h b/source/cmsis-core/mpu_armv7.h index 786bed7de..52e4982ce 100644 --- a/source/cmsis-core/mpu_armv7.h +++ b/source/cmsis-core/mpu_armv7.h @@ -1,11 +1,11 @@ /****************************************************************************** * @file mpu_armv7.h * @brief CMSIS MPU API for Armv7-M MPU - * @version V5.1.0 - * @date 08. March 2019 + * @version V5.1.2 + * @date 25. May 2020 ******************************************************************************/ /* - * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -190,6 +190,7 @@ typedef struct { */ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) { + __DMB(); MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; @@ -207,6 +208,8 @@ __STATIC_INLINE void ARM_MPU_Disable(void) SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); } /** Clear and disable the given MPU region. @@ -220,7 +223,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) /** Configure an MPU region. * \param rbar Value for RBAR register. -* \param rsar Value for RSAR register. +* \param rasr Value for RASR register. */ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) { @@ -231,7 +234,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) /** Configure the given MPU region. * \param rnr Region number to be configured. * \param rbar Value for RBAR register. -* \param rsar Value for RSAR register. +* \param rasr Value for RASR register. */ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) { diff --git a/source/cmsis-core/mpu_armv8.h b/source/cmsis-core/mpu_armv8.h index 0a84e8aa9..ef44ad01d 100644 --- a/source/cmsis-core/mpu_armv8.h +++ b/source/cmsis-core/mpu_armv8.h @@ -1,11 +1,11 @@ /****************************************************************************** * @file mpu_armv8.h * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU - * @version V5.1.1 - * @date 09. August 2019 + * @version V5.1.2 + * @date 10. February 2020 ******************************************************************************/ /* - * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -129,6 +129,7 @@ typedef struct { */ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) { + __DMB(); MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; @@ -146,6 +147,8 @@ __STATIC_INLINE void ARM_MPU_Disable(void) SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); } #ifdef MPU_NS @@ -154,6 +157,7 @@ __STATIC_INLINE void ARM_MPU_Disable(void) */ __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) { + __DMB(); MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; @@ -171,6 +175,8 @@ __STATIC_INLINE void ARM_MPU_Disable_NS(void) SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); } #endif diff --git a/source/cmsis-core/pmu_armv8.h b/source/cmsis-core/pmu_armv8.h new file mode 100644 index 000000000..f8f3d8935 --- /dev/null +++ b/source/cmsis-core/pmu_armv8.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.1 + * @date 15. April 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif From 844a406e9d34a48a3c67b0920cf51d35137a5606 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Tue, 5 Jan 2021 16:24:53 -0600 Subject: [PATCH 149/617] Set __PROGRAM_START macro to force CMSIS __cmsis_start() to be removed. --- records/tools/armcc.yaml | 2 +- records/tools/armclang.yaml | 2 +- records/tools/gcc_arm.yaml | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/records/tools/armcc.yaml b/records/tools/armcc.yaml index 6b055f438..e3265c496 100644 --- a/records/tools/armcc.yaml +++ b/records/tools/armcc.yaml @@ -3,7 +3,7 @@ tool_specific: mcu: - cortex-m0 macros: - - + - __PROGRAM_START linker_file: - source/daplink/daplink.sct misc: diff --git a/records/tools/armclang.yaml b/records/tools/armclang.yaml index e8b4968ca..78e584772 100644 --- a/records/tools/armclang.yaml +++ b/records/tools/armclang.yaml @@ -3,7 +3,7 @@ tool_specific: mcu: - cortex-m0 macros: - - + - __PROGRAM_START linker_file: - source/daplink/daplink.sct misc: diff --git a/records/tools/gcc_arm.yaml b/records/tools/gcc_arm.yaml index 845767e52..3ca532e65 100644 --- a/records/tools/gcc_arm.yaml +++ b/records/tools/gcc_arm.yaml @@ -1,7 +1,7 @@ tool_specific: gcc_arm: macros: - - + - __PROGRAM_START linker_file: - source/daplink/daplink.ld misc: From bcdc9f40cd42d215ab83034c14090d23eea6c486 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 21 Apr 2021 16:25:59 -0500 Subject: [PATCH 150/617] LPC55xx: fix RTOS2 tick configuration --- records/rtos/rtos-cm33.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/records/rtos/rtos-cm33.yaml b/records/rtos/rtos-cm33.yaml index 4a9105b80..746e08049 100644 --- a/records/rtos/rtos-cm33.yaml +++ b/records/rtos/rtos-cm33.yaml @@ -1,6 +1,6 @@ common: macros: - - OS_TICK=10000 + - OS_TICK_FREQ=100 includes: - source/rtos2/Include - source/rtos2/RTX/Include From 90ba4ec0c59dd16f61d1822beb67e3913ed1b40d Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 21 Apr 2021 23:48:53 -0500 Subject: [PATCH 151/617] LPC55xx: Add interface firmware to info.py and armcc/armclang build work-around --- test/info.py | 15 ++++++++------- tools/progen_compile.py | 3 +++ 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/test/info.py b/test/info.py index 3c5290a1f..fff145849 100644 --- a/test/info.py +++ b/test/info.py @@ -135,11 +135,11 @@ ('k26f_if', False, 0x0000, "bin" ), ('lpc11u35_if', False, 0x0000, "bin" ), ('lpc4322_if', False, 0x0000, "bin" ), + ('lpc55s69_if', False, 0x10000, "bin" ), ('max32620_if', False, 0x0000, "bin" ), ('max32625_if', False, 0x0000, "bin" ), ('sam3u2c_if', False, 0x0000, "bin" ), ('stm32f103xb_if', False, 0x0000, "bin" ), - ('lpc55s69_if', False, 0x10000, "bin" ), } # Add new HICs here @@ -239,11 +239,11 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x1102, VENDOR_TO_FAMILY('Nordic', 2), 'sam3u2c_mkit_dk_dongle_nrf5x_if', 'sam3u2c_bl', 'Nordic-nRF52840-DK' ), ( 0x1114, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_ssci1114_if', None, 'LPC1114FN28' ), ( 0x1120, VENDOR_TO_FAMILY('Nordic', 1), 'sam3u2c_mkit_dk_dongle_nrf5x_if', 'sam3u2c_bl', 'Nordic-nRF51-Dongle' ), - ( 0x1200, VENDOR_TO_FAMILY('Stub', 3), 'sam3u2c_ncs36510rf_if', 'sam3u2c_bl', None ),# TODO - Set to 'ncs36510' when non-zero flash addresses are supported + ( 0x1200, VENDOR_TO_FAMILY('Stub', 3), 'sam3u2c_ncs36510rf_if', 'sam3u2c_bl', None ), # TODO - Set to 'ncs36510' when non-zero flash addresses are supported ( 0x1234, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_c027_if', None, 'u-blox-C027' ), - ( 0x1236, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_ublox_evk_odin_w2_if', 'stm32f103xb_bl', 'ublox-EVK-ODIN-W2' ), - ( 0x1237, VENDOR_TO_FAMILY('Nordic', 2), 'sam3u2c_ublox_evk_nina_b1_if', 'sam3u2c_bl', 'U-BLOX-EVK-NINA-B1' ), - ( 0x1238, VENDOR_TO_FAMILY('Nordic', 1), 'kl26z_nina_b1_if', 'kl26z_bl', 'u-blox-NINA-B1' ), + ( 0x1236, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_ublox_evk_odin_w2_if', 'stm32f103xb_bl', 'ublox-EVK-ODIN-W2' ), + ( 0x1237, VENDOR_TO_FAMILY('Nordic', 2), 'sam3u2c_ublox_evk_nina_b1_if', 'sam3u2c_bl', 'U-BLOX-EVK-NINA-B1' ), + ( 0x1238, VENDOR_TO_FAMILY('Nordic', 1), 'kl26z_nina_b1_if', 'kl26z_bl', 'u-blox-NINA-B1' ), ( 0x1304, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_pfm_m487km_if', 'm48ssidae_bl', None ), ( 0x1309, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_m252kg_if', 'm48ssidae_bl', None ), ( 0x1310, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_iot_m263a_if', 'm48ssidae_bl', None ), @@ -283,10 +283,11 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x9014, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_wio3g_if', None, None ), ( 0x9015, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_wiobg96_if', None, None ), ( 0x9016, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_96b_nitrogen_if', None, None ), # TODO - set target to 'Seeed-96Boards-Nitrogen' when mbed-os supports this - ( 0x9017, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_wio_emw3166_if', None, 'WIO_EMW3166' ), # TODO - set target to 'Seeed-96Boards-Nitrogen' when mbed-os supports this + ( 0x9017, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_wio_emw3166_if', None, 'WIO_EMW3166' ), # TODO - set target to 'Seeed-96Boards-Nitrogen' when mbed-os supports this ( 0x9900, VENDOR_TO_FAMILY('Nordic', 1), 'kl26z_microbit_if', 'kl26z_bl', 'Microbit' ), ( 0x9901, VENDOR_TO_FAMILY('Nordic', 1), 'kl26z_microbit_if', 'kl26z_bl', 'Microbit' ), ( 0x9903, VENDOR_TO_FAMILY('Nordic', 2), 'kl27z_microbit_if', 'kl27z_bl', 'Microbit' ), + ( 0xA127, VENDOR_TO_FAMILY('Ambiq', 1), 'kl26z_artemis_dk_if', 'kl26z_bl', 'ARTMBED' ), ( 0xC000, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_cocorico_if', None, 'CoCo-ri-Co' ), ( 0xC006, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_vbluno51_if', None, 'VBLUNO51' ), ( 0xC005, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_mtconnect04s_if', None, 'MtConnect04S' ), @@ -295,11 +296,11 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'k26f_if', None, None ), ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_if', None, None ), ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'lpc4322_if', None, None ), + ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'lpc55s69_if', None, None ), ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'max32620_if', None, None ), ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'max32625_if', None, None ), ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'sam3u2c_if', None, None ), ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_if', None, None ), - ( 0xA127, VENDOR_TO_FAMILY('Ambiq', 1), 'kl26z_artemis_dk_if', 'kl26z_bl', 'ARTMBED' ), ] # Add new HICs here diff --git a/tools/progen_compile.py b/tools/progen_compile.py index 068f6ec21..58299082f 100755 --- a/tools/progen_compile.py +++ b/tools/progen_compile.py @@ -88,6 +88,9 @@ def get_core_count(): print("Unsupported toolchain '%s' (options: %s)\n" % (toolchain, ", ".join(toolchains))) exit(-1) +# armcc does not support Cortex-M33 and lpc55s69 is not ported to armclang +if 'armc' in toolchain: + project_list = filter(lambda p: not p.startswith("lpc55"), project_list) logging_level = logging.DEBUG if args.verbosity >= 2 else (logging.INFO if args.verbosity >= 1 else logging.WARNING) logging.basicConfig(format="%(asctime)s %(name)020s %(levelname)s\t%(message)s", level=logging_level) From 9934a71caac327f5b8ff66f420e0b191c1261b16 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 22 Apr 2021 16:10:39 -0500 Subject: [PATCH 152/617] LPC5xx: Connect HW_VERS6 and HW_VERS7 to reset functionality --- source/hic_hal/nxp/lpc55xx/gpio.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/source/hic_hal/nxp/lpc55xx/gpio.c b/source/hic_hal/nxp/lpc55xx/gpio.c index dfa98482f..385533bc3 100644 --- a/source/hic_hal/nxp/lpc55xx/gpio.c +++ b/source/hic_hal/nxp/lpc55xx/gpio.c @@ -52,6 +52,8 @@ void gpio_init(void) // Configure pins. IOCON->PIO[PIN_PIO_PORT][LED_CONNECTED] = IOCON_FUNC0 | IOCON_DIGITAL_EN; + IOCON->PIO[PIN_PIO_PORT][PIN_HW_VERS_6] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; + IOCON->PIO[PIN_PIO_PORT][PIN_HW_VERS_7] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; // Turn off LED. GPIO->B[PIN_PIO_PORT][LED_CONNECTED] = 1; @@ -59,6 +61,9 @@ void gpio_init(void) GPIO->DIRSET[PIN_PIO_PORT] = LED_CONNECTED_MASK; // Turn on LED. GPIO->B[PIN_PIO_PORT][LED_CONNECTED] = 1; + + GPIO->DIRCLR[PIN_PIO_PORT] = PIN_HW_VERS_6_MASK; + GPIO->DIRCLR[PIN_PIO_PORT] = PIN_HW_VERS_7_MASK; } void gpio_set_board_power(bool powerEnabled) @@ -84,10 +89,10 @@ void gpio_set_msc_led(gpio_led_state_t state) uint8_t gpio_get_reset_btn_no_fwrd(void) { - return 0; + return GPIO->B[PIN_PIO_PORT][PIN_HW_VERS_6] ? 0 : 1; } uint8_t gpio_get_reset_btn_fwrd(void) { - return 0; + return GPIO->B[PIN_PIO_PORT][PIN_HW_VERS_7] ? 0 : 1; } From 6945ae804cc8c6822397b4a9d827c962c0888143 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 22 Apr 2021 16:16:48 -0500 Subject: [PATCH 153/617] Upload .hex version of bootloader in addition to .bin --- .github/workflows/linux.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/linux.yml b/.github/workflows/linux.yml index 6eb6d9b1e..1f8c1b5a1 100644 --- a/.github/workflows/linux.yml +++ b/.github/workflows/linux.yml @@ -70,7 +70,7 @@ jobs: python tools/progen_compile.py --release --parallel -v -v --ignore-failures (ls -lR firmware_*; ccache -s; arm-none-eabi-gcc -v) | tee log.txt mkdir bootloaders - cp projectfiles/make_gcc_arm/*_bl/build/*_crc.bin bootloaders + cp projectfiles/make_gcc_arm/*_bl/build/*_crc.{bin,hex} bootloaders - name: Upload test artifacts uses: actions/upload-artifact@v2 From e8615bdfe3c5760e35d7691ad74bac6914877255 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 19 May 2021 02:46:19 -0500 Subject: [PATCH 154/617] max32620/max32625: Fix for USB setup packet with GCC --- source/hic_hal/maxim/max32620/usbd_max32620.c | 5 +++++ source/hic_hal/maxim/max32625/usbd_max32625.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/source/hic_hal/maxim/max32620/usbd_max32620.c b/source/hic_hal/maxim/max32620/usbd_max32620.c index f2e627b0e..143ceedd9 100644 --- a/source/hic_hal/maxim/max32620/usbd_max32620.c +++ b/source/hic_hal/maxim/max32620/usbd_max32620.c @@ -403,7 +403,12 @@ U32 USBD_ReadEP (U32 EPNum, U8 *pData, U32 size) cnt = size; } setup_waiting = 0; +#if defined ( __GNUC__) + ((U32 *)pData)[0] = MXC_USB->setup0; + ((U32 *)pData)[1] = MXC_USB->setup1; +#else memcpy(pData, (void*)&MXC_USB->setup0, cnt); +#endif /* __GNUC__ */ sup = (USB_SETUP_PACKET*)pData; if ( (sup->bmRequestType.Dir == REQUEST_HOST_TO_DEVICE) && (sup->wLength > 0) ) { diff --git a/source/hic_hal/maxim/max32625/usbd_max32625.c b/source/hic_hal/maxim/max32625/usbd_max32625.c index c9fdf1885..cca506143 100755 --- a/source/hic_hal/maxim/max32625/usbd_max32625.c +++ b/source/hic_hal/maxim/max32625/usbd_max32625.c @@ -403,7 +403,12 @@ U32 USBD_ReadEP (U32 EPNum, U8 *pData, U32 size) cnt = size; } setup_waiting = 0; +#if defined ( __GNUC__) + ((U32 *)pData)[0] = MXC_USB->setup0; + ((U32 *)pData)[1] = MXC_USB->setup1; +#else memcpy(pData, (void*)&MXC_USB->setup0, cnt); +#endif /* __GNUC__ */ sup = (USB_SETUP_PACKET*)pData; if ( (sup->bmRequestType.Dir == REQUEST_HOST_TO_DEVICE) && (sup->wLength > 0) ) { From 122179342adb8632ac1182d3b91041b9fb58b91b Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 19 May 2021 22:21:01 -0500 Subject: [PATCH 155/617] max32620/max32625: Apply GCC USB setup packet fix to all compilers --- source/hic_hal/maxim/max32620/usbd_max32620.c | 13 +++++-------- source/hic_hal/maxim/max32625/usbd_max32625.c | 9 +++------ 2 files changed, 8 insertions(+), 14 deletions(-) diff --git a/source/hic_hal/maxim/max32620/usbd_max32620.c b/source/hic_hal/maxim/max32620/usbd_max32620.c index 143ceedd9..9b09cc9d8 100644 --- a/source/hic_hal/maxim/max32620/usbd_max32620.c +++ b/source/hic_hal/maxim/max32620/usbd_max32620.c @@ -397,18 +397,15 @@ U32 USBD_ReadEP (U32 EPNum, U8 *pData, U32 size) EPNum &= EPNUM_MASK; if ((EPNum == 0) && setup_waiting) { - cnt = USBD_MAX_PACKET0; + cnt = sizeof(USB_SETUP_PACKET); - if (size < cnt) { - cnt = size; - } + if (size < cnt) { + util_assert(0); + return 0; + } setup_waiting = 0; -#if defined ( __GNUC__) ((U32 *)pData)[0] = MXC_USB->setup0; ((U32 *)pData)[1] = MXC_USB->setup1; -#else - memcpy(pData, (void*)&MXC_USB->setup0, cnt); -#endif /* __GNUC__ */ sup = (USB_SETUP_PACKET*)pData; if ( (sup->bmRequestType.Dir == REQUEST_HOST_TO_DEVICE) && (sup->wLength > 0) ) { diff --git a/source/hic_hal/maxim/max32625/usbd_max32625.c b/source/hic_hal/maxim/max32625/usbd_max32625.c index cca506143..37cbd1e9f 100755 --- a/source/hic_hal/maxim/max32625/usbd_max32625.c +++ b/source/hic_hal/maxim/max32625/usbd_max32625.c @@ -397,18 +397,15 @@ U32 USBD_ReadEP (U32 EPNum, U8 *pData, U32 size) EPNum &= EPNUM_MASK; if ((EPNum == 0) && setup_waiting) { - cnt = USBD_MAX_PACKET0; + cnt = sizeof(USB_SETUP_PACKET); if (size < cnt) { - cnt = size; + util_assert(0); + return 0; } setup_waiting = 0; -#if defined ( __GNUC__) ((U32 *)pData)[0] = MXC_USB->setup0; ((U32 *)pData)[1] = MXC_USB->setup1; -#else - memcpy(pData, (void*)&MXC_USB->setup0, cnt); -#endif /* __GNUC__ */ sup = (USB_SETUP_PACKET*)pData; if ( (sup->bmRequestType.Dir == REQUEST_HOST_TO_DEVICE) && (sup->wLength > 0) ) { From cd8a073c9f528727c1678ebdff7d0b3147898e3f Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 24 Apr 2021 20:52:01 -0500 Subject: [PATCH 156/617] USB cleanup: Remove superfluous files --- source/hic_hal/atmel/sam3u2c/usb_buf.h | 31 ---------------------- source/hic_hal/freescale/k20dx/usb_buf.h | 29 -------------------- source/hic_hal/freescale/k26f/usb_buf.h | 29 -------------------- source/hic_hal/maxim/max32620/usb_buf.h | 28 ------------------- source/hic_hal/maxim/max32625/usb_buf.h | 26 ------------------ source/hic_hal/nuvoton/m48ssidae/usb_buf.h | 31 ---------------------- source/hic_hal/nxp/lpc11u35/usb_buf.h | 29 -------------------- source/hic_hal/nxp/lpc4322/usb_buf.h | 29 -------------------- source/hic_hal/nxp/lpc55xx/usb_buf.h | 29 -------------------- source/hic_hal/stm32/stm32f103xb/usb_buf.h | 31 ---------------------- 10 files changed, 292 deletions(-) delete mode 100644 source/hic_hal/atmel/sam3u2c/usb_buf.h delete mode 100644 source/hic_hal/freescale/k20dx/usb_buf.h delete mode 100644 source/hic_hal/freescale/k26f/usb_buf.h delete mode 100644 source/hic_hal/maxim/max32620/usb_buf.h delete mode 100755 source/hic_hal/maxim/max32625/usb_buf.h delete mode 100644 source/hic_hal/nuvoton/m48ssidae/usb_buf.h delete mode 100644 source/hic_hal/nxp/lpc11u35/usb_buf.h delete mode 100644 source/hic_hal/nxp/lpc4322/usb_buf.h delete mode 100644 source/hic_hal/nxp/lpc55xx/usb_buf.h delete mode 100644 source/hic_hal/stm32/stm32f103xb/usb_buf.h diff --git a/source/hic_hal/atmel/sam3u2c/usb_buf.h b/source/hic_hal/atmel/sam3u2c/usb_buf.h deleted file mode 100644 index 7148e65f0..000000000 --- a/source/hic_hal/atmel/sam3u2c/usb_buf.h +++ /dev/null @@ -1,31 +0,0 @@ -/** - * @file usb_buf.h - * @brief - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef USB_BUF_H -#define USB_BUF_H - - -#include "stdint.h" - -#define USB_MSC_BUF_SIZE (512) -uint32_t usb_buffer[USB_MSC_BUF_SIZE / sizeof(uint32_t)]; - -#endif diff --git a/source/hic_hal/freescale/k20dx/usb_buf.h b/source/hic_hal/freescale/k20dx/usb_buf.h deleted file mode 100644 index 87cc1e40f..000000000 --- a/source/hic_hal/freescale/k20dx/usb_buf.h +++ /dev/null @@ -1,29 +0,0 @@ -/** - * @file usb_buf.h - * @brief - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef USB_BUF_H -#define USB_BUF_H - -#include "stdint.h" - -uint32_t usb_buffer[512 / 4]; - -#endif diff --git a/source/hic_hal/freescale/k26f/usb_buf.h b/source/hic_hal/freescale/k26f/usb_buf.h deleted file mode 100644 index 87cc1e40f..000000000 --- a/source/hic_hal/freescale/k26f/usb_buf.h +++ /dev/null @@ -1,29 +0,0 @@ -/** - * @file usb_buf.h - * @brief - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef USB_BUF_H -#define USB_BUF_H - -#include "stdint.h" - -uint32_t usb_buffer[512 / 4]; - -#endif diff --git a/source/hic_hal/maxim/max32620/usb_buf.h b/source/hic_hal/maxim/max32620/usb_buf.h deleted file mode 100644 index 87806f1a1..000000000 --- a/source/hic_hal/maxim/max32620/usb_buf.h +++ /dev/null @@ -1,28 +0,0 @@ -/* CMSIS-DAP Interface Firmware - * Copyright (c) 2009-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef USB_BUF_H -#define USB_BUF_H - -//#include -#include - -//#define USB_MSC_BUF_SIZE (2048) -#define USB_MSC_BUF_SIZE (512) - -__attribute__ ((aligned (64))) -uint32_t usb_buffer[USB_MSC_BUF_SIZE/4]; - -#endif diff --git a/source/hic_hal/maxim/max32625/usb_buf.h b/source/hic_hal/maxim/max32625/usb_buf.h deleted file mode 100755 index 21614821e..000000000 --- a/source/hic_hal/maxim/max32625/usb_buf.h +++ /dev/null @@ -1,26 +0,0 @@ -/* CMSIS-DAP Interface Firmware - * Copyright (c) 2009-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef USB_BUF_H -#define USB_BUF_H - -#include - -#define USB_MSC_BUF_SIZE (512) - -__attribute__ ((aligned (64))) -uint32_t usb_buffer[USB_MSC_BUF_SIZE/4]; - -#endif diff --git a/source/hic_hal/nuvoton/m48ssidae/usb_buf.h b/source/hic_hal/nuvoton/m48ssidae/usb_buf.h deleted file mode 100644 index dbdad064c..000000000 --- a/source/hic_hal/nuvoton/m48ssidae/usb_buf.h +++ /dev/null @@ -1,31 +0,0 @@ -/** - * @file usb_buf.h - * @brief - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef USB_BUF_H -#define USB_BUF_H - - -#include "stdint.h" - -#define USB_MSC_BUF_SIZE (512) -uint32_t usb_buffer[USB_MSC_BUF_SIZE / sizeof(uint32_t)]; - -#endif diff --git a/source/hic_hal/nxp/lpc11u35/usb_buf.h b/source/hic_hal/nxp/lpc11u35/usb_buf.h deleted file mode 100644 index 87cc1e40f..000000000 --- a/source/hic_hal/nxp/lpc11u35/usb_buf.h +++ /dev/null @@ -1,29 +0,0 @@ -/** - * @file usb_buf.h - * @brief - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef USB_BUF_H -#define USB_BUF_H - -#include "stdint.h" - -uint32_t usb_buffer[512 / 4]; - -#endif diff --git a/source/hic_hal/nxp/lpc4322/usb_buf.h b/source/hic_hal/nxp/lpc4322/usb_buf.h deleted file mode 100644 index 87cc1e40f..000000000 --- a/source/hic_hal/nxp/lpc4322/usb_buf.h +++ /dev/null @@ -1,29 +0,0 @@ -/** - * @file usb_buf.h - * @brief - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef USB_BUF_H -#define USB_BUF_H - -#include "stdint.h" - -uint32_t usb_buffer[512 / 4]; - -#endif diff --git a/source/hic_hal/nxp/lpc55xx/usb_buf.h b/source/hic_hal/nxp/lpc55xx/usb_buf.h deleted file mode 100644 index 87cc1e40f..000000000 --- a/source/hic_hal/nxp/lpc55xx/usb_buf.h +++ /dev/null @@ -1,29 +0,0 @@ -/** - * @file usb_buf.h - * @brief - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef USB_BUF_H -#define USB_BUF_H - -#include "stdint.h" - -uint32_t usb_buffer[512 / 4]; - -#endif diff --git a/source/hic_hal/stm32/stm32f103xb/usb_buf.h b/source/hic_hal/stm32/stm32f103xb/usb_buf.h deleted file mode 100644 index dbdad064c..000000000 --- a/source/hic_hal/stm32/stm32f103xb/usb_buf.h +++ /dev/null @@ -1,31 +0,0 @@ -/** - * @file usb_buf.h - * @brief - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef USB_BUF_H -#define USB_BUF_H - - -#include "stdint.h" - -#define USB_MSC_BUF_SIZE (512) -uint32_t usb_buffer[USB_MSC_BUF_SIZE / sizeof(uint32_t)]; - -#endif From edc3398907a4382cf0dc7ba8528ddf359a5dbcb5 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 24 Apr 2021 20:55:29 -0500 Subject: [PATCH 157/617] USB cleanup: consistent header --- source/hic_hal/atmel/sam3u2c/usb_config.c | 2 +- source/hic_hal/freescale/k20dx/usb_config.c | 4 ++-- source/hic_hal/freescale/k26f/usb_config.c | 4 ++-- source/hic_hal/freescale/kl26z/usb_config.c | 2 +- source/hic_hal/freescale/kl27z/usb_config.c | 2 +- source/hic_hal/maxim/max32620/usb_config.c | 21 ++++++++++--------- source/hic_hal/maxim/max32625/usb_config.c | 21 ++++++++++--------- source/hic_hal/nuvoton/m48ssidae/usb_config.c | 6 +++--- source/hic_hal/nxp/lpc11u35/usb_config.c | 2 +- source/hic_hal/nxp/lpc4322/usb_config.c | 2 +- source/hic_hal/nxp/lpc55xx/usb_config.c | 4 ++-- source/hic_hal/stm32/stm32f103xb/usb_config.c | 6 +++--- 12 files changed, 39 insertions(+), 37 deletions(-) diff --git a/source/hic_hal/atmel/sam3u2c/usb_config.c b/source/hic_hal/atmel/sam3u2c/usb_config.c index c748c9adf..9359cc626 100644 --- a/source/hic_hal/atmel/sam3u2c/usb_config.c +++ b/source/hic_hal/atmel/sam3u2c/usb_config.c @@ -1,6 +1,6 @@ /** * @file usb_config.c - * @brief + * @brief USB Device Configuration * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved diff --git a/source/hic_hal/freescale/k20dx/usb_config.c b/source/hic_hal/freescale/k20dx/usb_config.c index 2f1b37185..f4838d775 100644 --- a/source/hic_hal/freescale/k20dx/usb_config.c +++ b/source/hic_hal/freescale/k20dx/usb_config.c @@ -1,6 +1,6 @@ /** - * @file usb_config.h - * @brief + * @file usb_config.c + * @brief USB Device Configuration * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved diff --git a/source/hic_hal/freescale/k26f/usb_config.c b/source/hic_hal/freescale/k26f/usb_config.c index d30512bba..536d261a8 100644 --- a/source/hic_hal/freescale/k26f/usb_config.c +++ b/source/hic_hal/freescale/k26f/usb_config.c @@ -1,6 +1,6 @@ /** - * @file usb_config.h - * @brief + * @file usb_config.c + * @brief USB Device Configuration * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved diff --git a/source/hic_hal/freescale/kl26z/usb_config.c b/source/hic_hal/freescale/kl26z/usb_config.c index a5a325232..aff45f1bb 100644 --- a/source/hic_hal/freescale/kl26z/usb_config.c +++ b/source/hic_hal/freescale/kl26z/usb_config.c @@ -1,6 +1,6 @@ /** * @file usb_config.c - * @brief + * @brief USB Device Configuration * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved diff --git a/source/hic_hal/freescale/kl27z/usb_config.c b/source/hic_hal/freescale/kl27z/usb_config.c index ad35f74d0..48028080c 100644 --- a/source/hic_hal/freescale/kl27z/usb_config.c +++ b/source/hic_hal/freescale/kl27z/usb_config.c @@ -1,6 +1,6 @@ /** * @file usb_config.c - * @brief + * @brief USB Device Configuration * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved diff --git a/source/hic_hal/maxim/max32620/usb_config.c b/source/hic_hal/maxim/max32620/usb_config.c index 82b8110fe..54c58594a 100644 --- a/source/hic_hal/maxim/max32620/usb_config.c +++ b/source/hic_hal/maxim/max32620/usb_config.c @@ -1,25 +1,26 @@ -/* CMSIS-DAP Interface Firmware - * Copyright (c) 2009-2019 ARM Limited +/** + * @file usb_config.c + * @brief USB Device Configuration * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "util.h" -/*------------------------------------------------------------------------------ - * USB Device Configuration - *----------------------------------------------------------------------------*/ - // USB Device // Enable the USB Device functionality #define USBD_ENABLE 1 diff --git a/source/hic_hal/maxim/max32625/usb_config.c b/source/hic_hal/maxim/max32625/usb_config.c index 190f2f762..a882d819e 100755 --- a/source/hic_hal/maxim/max32625/usb_config.c +++ b/source/hic_hal/maxim/max32625/usb_config.c @@ -1,25 +1,26 @@ -/* CMSIS-DAP Interface Firmware - * Copyright (c) 2009-2019 ARM Limited +/** + * @file usb_config.c + * @brief USB Device Configuration * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "util.h" -/*------------------------------------------------------------------------------ - * USB Device Configuration - *----------------------------------------------------------------------------*/ - // USB Device // Enable the USB Device functionality #define USBD_ENABLE 1 diff --git a/source/hic_hal/nuvoton/m48ssidae/usb_config.c b/source/hic_hal/nuvoton/m48ssidae/usb_config.c index 5b4b5b92f..d35052b8f 100644 --- a/source/hic_hal/nuvoton/m48ssidae/usb_config.c +++ b/source/hic_hal/nuvoton/m48ssidae/usb_config.c @@ -1,9 +1,9 @@ /** - * @file usb_config.h - * @brief + * @file usb_config.c + * @brief USB Device Configuration * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may diff --git a/source/hic_hal/nxp/lpc11u35/usb_config.c b/source/hic_hal/nxp/lpc11u35/usb_config.c index 0153f6de8..73fb3f0ab 100644 --- a/source/hic_hal/nxp/lpc11u35/usb_config.c +++ b/source/hic_hal/nxp/lpc11u35/usb_config.c @@ -1,6 +1,6 @@ /** * @file usb_config.c - * @brief + * @brief USB Device Configuration * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved diff --git a/source/hic_hal/nxp/lpc4322/usb_config.c b/source/hic_hal/nxp/lpc4322/usb_config.c index 04306196f..6c6f7217d 100644 --- a/source/hic_hal/nxp/lpc4322/usb_config.c +++ b/source/hic_hal/nxp/lpc4322/usb_config.c @@ -1,6 +1,6 @@ /** * @file usb_config.c - * @brief + * @brief USB Device Configuration * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved diff --git a/source/hic_hal/nxp/lpc55xx/usb_config.c b/source/hic_hal/nxp/lpc55xx/usb_config.c index d30512bba..536d261a8 100644 --- a/source/hic_hal/nxp/lpc55xx/usb_config.c +++ b/source/hic_hal/nxp/lpc55xx/usb_config.c @@ -1,6 +1,6 @@ /** - * @file usb_config.h - * @brief + * @file usb_config.c + * @brief USB Device Configuration * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved diff --git a/source/hic_hal/stm32/stm32f103xb/usb_config.c b/source/hic_hal/stm32/stm32f103xb/usb_config.c index db2a0bca3..29a5dcc5f 100644 --- a/source/hic_hal/stm32/stm32f103xb/usb_config.c +++ b/source/hic_hal/stm32/stm32f103xb/usb_config.c @@ -1,9 +1,9 @@ /** - * @file usb_config.h - * @brief + * @file usb_config.c + * @brief USB Device Configuration * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may From 99648db55132d112cf0004da68574c849cd4bb27 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 24 Apr 2021 20:59:19 -0500 Subject: [PATCH 158/617] USB cleanup: make the line breaks consistent across all usb_config.c files --- source/hic_hal/atmel/sam3u2c/usb_config.c | 1 + source/hic_hal/freescale/k20dx/usb_config.c | 2 +- source/hic_hal/freescale/kl26z/usb_config.c | 6 +----- source/hic_hal/freescale/kl27z/usb_config.c | 6 +----- source/hic_hal/maxim/max32620/usb_config.c | 7 ++++--- source/hic_hal/maxim/max32625/usb_config.c | 6 +++--- source/hic_hal/nuvoton/m48ssidae/usb_config.c | 5 +---- source/hic_hal/nxp/lpc11u35/usb_config.c | 4 +--- source/hic_hal/nxp/lpc4322/usb_config.c | 6 +----- source/hic_hal/stm32/stm32f103xb/usb_config.c | 5 +---- 10 files changed, 15 insertions(+), 33 deletions(-) diff --git a/source/hic_hal/atmel/sam3u2c/usb_config.c b/source/hic_hal/atmel/sam3u2c/usb_config.c index 9359cc626..626378346 100644 --- a/source/hic_hal/atmel/sam3u2c/usb_config.c +++ b/source/hic_hal/atmel/sam3u2c/usb_config.c @@ -317,6 +317,7 @@ // <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes // // + #ifndef CDC_ENDPOINT #define CDC_ENDPOINT 0 #else diff --git a/source/hic_hal/freescale/k20dx/usb_config.c b/source/hic_hal/freescale/k20dx/usb_config.c index f4838d775..d8a42894c 100644 --- a/source/hic_hal/freescale/k20dx/usb_config.c +++ b/source/hic_hal/freescale/k20dx/usb_config.c @@ -391,6 +391,7 @@ #define USBD_BULK_HS_WMAXPACKETSIZE 512 #define USBD_BULK_STRDESC L"CMSIS-DAP v2" + /* USB Device Calculations ---------------------------------------------------*/ #define USBD_IF_NUM_MAX (USBD_BULK_ENABLE+USBD_WEBUSB_ENABLE+USBD_HID_ENABLE+USBD_MSC_ENABLE+(USBD_ADC_ENABLE*2)+(USBD_CDC_ACM_ENABLE*2)+USBD_CLS_ENABLE) @@ -537,7 +538,6 @@ #define USBD_MAX_PACKET ((USBD_MAX_PACKET_CALC3 > USBD_MAX_PACKET_CALC2 ) ? (USBD_MAX_PACKET_CALC3) : (USBD_MAX_PACKET_CALC2 )) - /*------------------------------------------------------------------------------ * USB Config Functions *----------------------------------------------------------------------------*/ diff --git a/source/hic_hal/freescale/kl26z/usb_config.c b/source/hic_hal/freescale/kl26z/usb_config.c index aff45f1bb..680005a86 100644 --- a/source/hic_hal/freescale/kl26z/usb_config.c +++ b/source/hic_hal/freescale/kl26z/usb_config.c @@ -407,7 +407,6 @@ #define USBD_EP_NUM_CALC7 MAX((USBD_BULK_ENABLE*(USBD_BULK_EP_BULKIN)), (USBD_BULK_ENABLE*(USBD_BULK_EP_BULKOUT))) #define USBD_EP_NUM MAX(USBD_EP_NUM_CALC6, USBD_EP_NUM_CALC7) - #if (USBD_HID_ENABLE) #if (USBD_MSC_ENABLE) #if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ @@ -471,7 +470,6 @@ #define USBD_ADC_SIF1_NUM (1) #define USBD_ADC_SIF2_NUM (2) - #define USBD_ADC_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+0) #define USBD_ADC_SIF1_STR_NUM (3+USBD_STRDESC_SER_ENABLE+1) #define USBD_ADC_SIF2_STR_NUM (3+USBD_STRDESC_SER_ENABLE+2) @@ -482,7 +480,6 @@ #define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) #define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) - #if (USBD_HID_ENABLE) #if (USBD_HID_HS_ENABLE) #define USBD_HID_MAX_PACKET ((USBD_HID_HS_WMAXPACKETSIZE > USBD_HID_WMAXPACKETSIZE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) @@ -525,7 +522,6 @@ #define USBD_CDC_ACM_MAX_PACKET (0) #define USBD_CDC_ACM_MAX_PACKET1 (0) #endif - #if (USBD_BULK_ENABLE) #if (USBD_BULK_HS_ENABLE) #define USBD_BULK_MAX_PACKET ((USBD_BULK_HS_WMAXPACKETSIZE > USBD_BULK_WMAXPACKETSIZE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) @@ -535,13 +531,13 @@ #else #define USBD_BULK_MAX_PACKET (0) #endif - #define USBD_MAX_PACKET_CALC0 ((USBD_HID_MAX_PACKET > USBD_HID_MAX_PACKET ) ? (USBD_HID_MAX_PACKET ) : (USBD_HID_MAX_PACKET )) #define USBD_MAX_PACKET_CALC1 ((USBD_ADC_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET ) ? (USBD_ADC_MAX_PACKET ) : (USBD_CDC_ACM_MAX_PACKET )) #define USBD_MAX_PACKET_CALC2 ((USBD_MAX_PACKET_CALC0 > USBD_MAX_PACKET_CALC1 ) ? (USBD_MAX_PACKET_CALC0) : (USBD_MAX_PACKET_CALC1 )) #define USBD_MAX_PACKET_CALC3 ((USBD_BULK_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET1 ) ? (USBD_BULK_MAX_PACKET) : (USBD_CDC_ACM_MAX_PACKET1 )) #define USBD_MAX_PACKET ((USBD_MAX_PACKET_CALC3 > USBD_MAX_PACKET_CALC2 ) ? (USBD_MAX_PACKET_CALC3) : (USBD_MAX_PACKET_CALC2 )) + /*------------------------------------------------------------------------------ * USB Config Functions *----------------------------------------------------------------------------*/ diff --git a/source/hic_hal/freescale/kl27z/usb_config.c b/source/hic_hal/freescale/kl27z/usb_config.c index 48028080c..024cd7e9c 100644 --- a/source/hic_hal/freescale/kl27z/usb_config.c +++ b/source/hic_hal/freescale/kl27z/usb_config.c @@ -407,7 +407,6 @@ #define USBD_EP_NUM_CALC7 MAX((USBD_BULK_ENABLE*(USBD_BULK_EP_BULKIN)), (USBD_BULK_ENABLE*(USBD_BULK_EP_BULKOUT))) #define USBD_EP_NUM MAX(USBD_EP_NUM_CALC6, USBD_EP_NUM_CALC7) - #if (USBD_HID_ENABLE) #if (USBD_MSC_ENABLE) #if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ @@ -471,7 +470,6 @@ #define USBD_ADC_SIF1_NUM (1) #define USBD_ADC_SIF2_NUM (2) - #define USBD_ADC_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+0) #define USBD_ADC_SIF1_STR_NUM (3+USBD_STRDESC_SER_ENABLE+1) #define USBD_ADC_SIF2_STR_NUM (3+USBD_STRDESC_SER_ENABLE+2) @@ -482,7 +480,6 @@ #define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) #define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) - #if (USBD_HID_ENABLE) #if (USBD_HID_HS_ENABLE) #define USBD_HID_MAX_PACKET ((USBD_HID_HS_WMAXPACKETSIZE > USBD_HID_WMAXPACKETSIZE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) @@ -525,7 +522,6 @@ #define USBD_CDC_ACM_MAX_PACKET (0) #define USBD_CDC_ACM_MAX_PACKET1 (0) #endif - #if (USBD_BULK_ENABLE) #if (USBD_BULK_HS_ENABLE) #define USBD_BULK_MAX_PACKET ((USBD_BULK_HS_WMAXPACKETSIZE > USBD_BULK_WMAXPACKETSIZE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) @@ -535,13 +531,13 @@ #else #define USBD_BULK_MAX_PACKET (0) #endif - #define USBD_MAX_PACKET_CALC0 ((USBD_HID_MAX_PACKET > USBD_HID_MAX_PACKET ) ? (USBD_HID_MAX_PACKET ) : (USBD_HID_MAX_PACKET )) #define USBD_MAX_PACKET_CALC1 ((USBD_ADC_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET ) ? (USBD_ADC_MAX_PACKET ) : (USBD_CDC_ACM_MAX_PACKET )) #define USBD_MAX_PACKET_CALC2 ((USBD_MAX_PACKET_CALC0 > USBD_MAX_PACKET_CALC1 ) ? (USBD_MAX_PACKET_CALC0) : (USBD_MAX_PACKET_CALC1 )) #define USBD_MAX_PACKET_CALC3 ((USBD_BULK_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET1 ) ? (USBD_BULK_MAX_PACKET) : (USBD_CDC_ACM_MAX_PACKET1 )) #define USBD_MAX_PACKET ((USBD_MAX_PACKET_CALC3 > USBD_MAX_PACKET_CALC2 ) ? (USBD_MAX_PACKET_CALC3) : (USBD_MAX_PACKET_CALC2 )) + /*------------------------------------------------------------------------------ * USB Config Functions *----------------------------------------------------------------------------*/ diff --git a/source/hic_hal/maxim/max32620/usb_config.c b/source/hic_hal/maxim/max32620/usb_config.c index 54c58594a..57577a9fa 100644 --- a/source/hic_hal/maxim/max32620/usb_config.c +++ b/source/hic_hal/maxim/max32620/usb_config.c @@ -318,6 +318,7 @@ // <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes // // + #ifndef CDC_ENDPOINT #define CDC_ENDPOINT 0 #else @@ -393,6 +394,7 @@ #define USBD_BULK_HS_WMAXPACKETSIZE 512 #define USBD_BULK_STRDESC L"CMSIS-DAP v2" + /* USB Device Calculations ---------------------------------------------------*/ #define USBD_IF_NUM_MAX (USBD_BULK_ENABLE+USBD_WEBUSB_ENABLE+USBD_HID_ENABLE+USBD_MSC_ENABLE+(USBD_ADC_ENABLE*2)+(USBD_CDC_ACM_ENABLE*2)+USBD_CLS_ENABLE) @@ -470,11 +472,11 @@ #endif #endif #endif + #define USBD_ADC_CIF_NUM (0) #define USBD_ADC_SIF1_NUM (1) #define USBD_ADC_SIF2_NUM (2) - #define USBD_ADC_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+0) #define USBD_ADC_SIF1_STR_NUM (3+USBD_STRDESC_SER_ENABLE+1) #define USBD_ADC_SIF2_STR_NUM (3+USBD_STRDESC_SER_ENABLE+2) @@ -527,7 +529,6 @@ #define USBD_CDC_ACM_MAX_PACKET (0) #define USBD_CDC_ACM_MAX_PACKET1 (0) #endif - #if (USBD_BULK_ENABLE) #if (USBD_BULK_HS_ENABLE) #define USBD_BULK_MAX_PACKET ((USBD_BULK_HS_WMAXPACKETSIZE > USBD_BULK_WMAXPACKETSIZE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) @@ -537,13 +538,13 @@ #else #define USBD_BULK_MAX_PACKET (0) #endif - #define USBD_MAX_PACKET_CALC0 ((USBD_HID_MAX_PACKET > USBD_HID_MAX_PACKET ) ? (USBD_HID_MAX_PACKET ) : (USBD_HID_MAX_PACKET )) #define USBD_MAX_PACKET_CALC1 ((USBD_ADC_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET ) ? (USBD_ADC_MAX_PACKET ) : (USBD_CDC_ACM_MAX_PACKET )) #define USBD_MAX_PACKET_CALC2 ((USBD_MAX_PACKET_CALC0 > USBD_MAX_PACKET_CALC1 ) ? (USBD_MAX_PACKET_CALC0) : (USBD_MAX_PACKET_CALC1 )) #define USBD_MAX_PACKET_CALC3 ((USBD_BULK_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET1 ) ? (USBD_BULK_MAX_PACKET) : (USBD_CDC_ACM_MAX_PACKET1 )) #define USBD_MAX_PACKET ((USBD_MAX_PACKET_CALC3 > USBD_MAX_PACKET_CALC2 ) ? (USBD_MAX_PACKET_CALC3) : (USBD_MAX_PACKET_CALC2 )) + /*------------------------------------------------------------------------------ * USB Config Functions *----------------------------------------------------------------------------*/ diff --git a/source/hic_hal/maxim/max32625/usb_config.c b/source/hic_hal/maxim/max32625/usb_config.c index a882d819e..57577a9fa 100755 --- a/source/hic_hal/maxim/max32625/usb_config.c +++ b/source/hic_hal/maxim/max32625/usb_config.c @@ -318,6 +318,7 @@ // <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes // // + #ifndef CDC_ENDPOINT #define CDC_ENDPOINT 0 #else @@ -393,6 +394,7 @@ #define USBD_BULK_HS_WMAXPACKETSIZE 512 #define USBD_BULK_STRDESC L"CMSIS-DAP v2" + /* USB Device Calculations ---------------------------------------------------*/ #define USBD_IF_NUM_MAX (USBD_BULK_ENABLE+USBD_WEBUSB_ENABLE+USBD_HID_ENABLE+USBD_MSC_ENABLE+(USBD_ADC_ENABLE*2)+(USBD_CDC_ACM_ENABLE*2)+USBD_CLS_ENABLE) @@ -470,11 +472,11 @@ #endif #endif #endif + #define USBD_ADC_CIF_NUM (0) #define USBD_ADC_SIF1_NUM (1) #define USBD_ADC_SIF2_NUM (2) - #define USBD_ADC_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+0) #define USBD_ADC_SIF1_STR_NUM (3+USBD_STRDESC_SER_ENABLE+1) #define USBD_ADC_SIF2_STR_NUM (3+USBD_STRDESC_SER_ENABLE+2) @@ -527,7 +529,6 @@ #define USBD_CDC_ACM_MAX_PACKET (0) #define USBD_CDC_ACM_MAX_PACKET1 (0) #endif - #if (USBD_BULK_ENABLE) #if (USBD_BULK_HS_ENABLE) #define USBD_BULK_MAX_PACKET ((USBD_BULK_HS_WMAXPACKETSIZE > USBD_BULK_WMAXPACKETSIZE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) @@ -537,7 +538,6 @@ #else #define USBD_BULK_MAX_PACKET (0) #endif - #define USBD_MAX_PACKET_CALC0 ((USBD_HID_MAX_PACKET > USBD_HID_MAX_PACKET ) ? (USBD_HID_MAX_PACKET ) : (USBD_HID_MAX_PACKET )) #define USBD_MAX_PACKET_CALC1 ((USBD_ADC_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET ) ? (USBD_ADC_MAX_PACKET ) : (USBD_CDC_ACM_MAX_PACKET )) #define USBD_MAX_PACKET_CALC2 ((USBD_MAX_PACKET_CALC0 > USBD_MAX_PACKET_CALC1 ) ? (USBD_MAX_PACKET_CALC0) : (USBD_MAX_PACKET_CALC1 )) diff --git a/source/hic_hal/nuvoton/m48ssidae/usb_config.c b/source/hic_hal/nuvoton/m48ssidae/usb_config.c index d35052b8f..0194dac0c 100644 --- a/source/hic_hal/nuvoton/m48ssidae/usb_config.c +++ b/source/hic_hal/nuvoton/m48ssidae/usb_config.c @@ -390,6 +390,7 @@ #define USBD_BULK_HS_WMAXPACKETSIZE 512 #define USBD_BULK_STRDESC L"CMSIS-DAP v2" + /* USB Device Calculations ---------------------------------------------------*/ #define USBD_IF_NUM_MAX (USBD_BULK_ENABLE+USBD_WEBUSB_ENABLE+USBD_HID_ENABLE+USBD_MSC_ENABLE+(USBD_ADC_ENABLE*2)+(USBD_CDC_ACM_ENABLE*2)+USBD_CLS_ENABLE) @@ -405,7 +406,6 @@ #define USBD_EP_NUM_CALC7 MAX((USBD_BULK_ENABLE*(USBD_BULK_EP_BULKIN)), (USBD_BULK_ENABLE*(USBD_BULK_EP_BULKOUT))) #define USBD_EP_NUM MAX(USBD_EP_NUM_CALC6, USBD_EP_NUM_CALC7) - #if (USBD_HID_ENABLE) #if (USBD_MSC_ENABLE) #if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ @@ -469,7 +469,6 @@ #define USBD_ADC_SIF1_NUM (1) #define USBD_ADC_SIF2_NUM (2) - #define USBD_ADC_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+0) #define USBD_ADC_SIF1_STR_NUM (3+USBD_STRDESC_SER_ENABLE+1) #define USBD_ADC_SIF2_STR_NUM (3+USBD_STRDESC_SER_ENABLE+2) @@ -480,7 +479,6 @@ #define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) #define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) - #if (USBD_HID_ENABLE) #if (USBD_HID_HS_ENABLE) #define USBD_HID_MAX_PACKET ((USBD_HID_HS_WMAXPACKETSIZE > USBD_HID_WMAXPACKETSIZE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) @@ -532,7 +530,6 @@ #else #define USBD_BULK_MAX_PACKET (0) #endif - #define USBD_MAX_PACKET_CALC0 ((USBD_HID_MAX_PACKET > USBD_HID_MAX_PACKET ) ? (USBD_HID_MAX_PACKET ) : (USBD_HID_MAX_PACKET )) #define USBD_MAX_PACKET_CALC1 ((USBD_ADC_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET ) ? (USBD_ADC_MAX_PACKET ) : (USBD_CDC_ACM_MAX_PACKET )) #define USBD_MAX_PACKET_CALC2 ((USBD_MAX_PACKET_CALC0 > USBD_MAX_PACKET_CALC1 ) ? (USBD_MAX_PACKET_CALC0) : (USBD_MAX_PACKET_CALC1 )) diff --git a/source/hic_hal/nxp/lpc11u35/usb_config.c b/source/hic_hal/nxp/lpc11u35/usb_config.c index 73fb3f0ab..15aafac8b 100644 --- a/source/hic_hal/nxp/lpc11u35/usb_config.c +++ b/source/hic_hal/nxp/lpc11u35/usb_config.c @@ -397,6 +397,7 @@ #define USBD_BULK_HS_WMAXPACKETSIZE 512 #define USBD_BULK_STRDESC L"CMSIS-DAP v2" + /* USB Device Calculations ---------------------------------------------------*/ #define USBD_IF_NUM_MAX (USBD_BULK_ENABLE+USBD_WEBUSB_ENABLE+USBD_HID_ENABLE+USBD_MSC_ENABLE+(USBD_ADC_ENABLE*2)+(USBD_CDC_ACM_ENABLE*2)+USBD_CLS_ENABLE) @@ -479,7 +480,6 @@ #define USBD_ADC_SIF1_NUM (1) #define USBD_ADC_SIF2_NUM (2) - #define USBD_ADC_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+0) #define USBD_ADC_SIF1_STR_NUM (3+USBD_STRDESC_SER_ENABLE+1) #define USBD_ADC_SIF2_STR_NUM (3+USBD_STRDESC_SER_ENABLE+2) @@ -532,7 +532,6 @@ #define USBD_CDC_ACM_MAX_PACKET (0) #define USBD_CDC_ACM_MAX_PACKET1 (0) #endif - #if (USBD_BULK_ENABLE) #if (USBD_BULK_HS_ENABLE) #define USBD_BULK_MAX_PACKET ((USBD_BULK_HS_WMAXPACKETSIZE > USBD_BULK_WMAXPACKETSIZE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) @@ -542,7 +541,6 @@ #else #define USBD_BULK_MAX_PACKET (0) #endif - #define USBD_MAX_PACKET_CALC0 ((USBD_HID_MAX_PACKET > USBD_HID_MAX_PACKET ) ? (USBD_HID_MAX_PACKET ) : (USBD_HID_MAX_PACKET )) #define USBD_MAX_PACKET_CALC1 ((USBD_ADC_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET ) ? (USBD_ADC_MAX_PACKET ) : (USBD_CDC_ACM_MAX_PACKET )) #define USBD_MAX_PACKET_CALC2 ((USBD_MAX_PACKET_CALC0 > USBD_MAX_PACKET_CALC1 ) ? (USBD_MAX_PACKET_CALC0) : (USBD_MAX_PACKET_CALC1 )) diff --git a/source/hic_hal/nxp/lpc4322/usb_config.c b/source/hic_hal/nxp/lpc4322/usb_config.c index 6c6f7217d..ab58ae22d 100644 --- a/source/hic_hal/nxp/lpc4322/usb_config.c +++ b/source/hic_hal/nxp/lpc4322/usb_config.c @@ -392,6 +392,7 @@ #define USBD_BULK_HS_WMAXPACKETSIZE 512 #define USBD_BULK_STRDESC L"CMSIS-DAP v2" + /* USB Device Calculations ---------------------------------------------------*/ #define USBD_IF_NUM_MAX (USBD_BULK_ENABLE+USBD_WEBUSB_ENABLE+USBD_HID_ENABLE+USBD_MSC_ENABLE+(USBD_ADC_ENABLE*2)+(USBD_CDC_ACM_ENABLE*2)+USBD_CLS_ENABLE) @@ -407,7 +408,6 @@ #define USBD_EP_NUM_CALC7 MAX((USBD_BULK_ENABLE*(USBD_BULK_EP_BULKIN)), (USBD_BULK_ENABLE*(USBD_BULK_EP_BULKOUT))) #define USBD_EP_NUM MAX(USBD_EP_NUM_CALC6, USBD_EP_NUM_CALC7) - #if (USBD_HID_ENABLE) #if (USBD_MSC_ENABLE) #if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ @@ -471,7 +471,6 @@ #define USBD_ADC_SIF1_NUM (1) #define USBD_ADC_SIF2_NUM (2) - #define USBD_ADC_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+0) #define USBD_ADC_SIF1_STR_NUM (3+USBD_STRDESC_SER_ENABLE+1) #define USBD_ADC_SIF2_STR_NUM (3+USBD_STRDESC_SER_ENABLE+2) @@ -482,7 +481,6 @@ #define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) #define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) - #if (USBD_HID_ENABLE) #if (USBD_HID_HS_ENABLE) #define USBD_HID_MAX_PACKET ((USBD_HID_HS_WMAXPACKETSIZE > USBD_HID_WMAXPACKETSIZE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) @@ -525,7 +523,6 @@ #define USBD_CDC_ACM_MAX_PACKET (0) #define USBD_CDC_ACM_MAX_PACKET1 (0) #endif - #if (USBD_BULK_ENABLE) #if (USBD_BULK_HS_ENABLE) #define USBD_BULK_MAX_PACKET ((USBD_BULK_HS_WMAXPACKETSIZE > USBD_BULK_WMAXPACKETSIZE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) @@ -535,7 +532,6 @@ #else #define USBD_BULK_MAX_PACKET (0) #endif - #define USBD_MAX_PACKET_CALC0 ((USBD_HID_MAX_PACKET > USBD_HID_MAX_PACKET ) ? (USBD_HID_MAX_PACKET ) : (USBD_HID_MAX_PACKET )) #define USBD_MAX_PACKET_CALC1 ((USBD_ADC_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET ) ? (USBD_ADC_MAX_PACKET ) : (USBD_CDC_ACM_MAX_PACKET )) #define USBD_MAX_PACKET_CALC2 ((USBD_MAX_PACKET_CALC0 > USBD_MAX_PACKET_CALC1 ) ? (USBD_MAX_PACKET_CALC0) : (USBD_MAX_PACKET_CALC1 )) diff --git a/source/hic_hal/stm32/stm32f103xb/usb_config.c b/source/hic_hal/stm32/stm32f103xb/usb_config.c index 29a5dcc5f..ecb49706e 100644 --- a/source/hic_hal/stm32/stm32f103xb/usb_config.c +++ b/source/hic_hal/stm32/stm32f103xb/usb_config.c @@ -390,6 +390,7 @@ #define USBD_BULK_HS_WMAXPACKETSIZE 512 #define USBD_BULK_STRDESC L"CMSIS-DAP v2" + /* USB Device Calculations ---------------------------------------------------*/ #define USBD_IF_NUM_MAX (USBD_BULK_ENABLE+USBD_WEBUSB_ENABLE+USBD_HID_ENABLE+USBD_MSC_ENABLE+(USBD_ADC_ENABLE*2)+(USBD_CDC_ACM_ENABLE*2)+USBD_CLS_ENABLE) @@ -405,7 +406,6 @@ #define USBD_EP_NUM_CALC7 MAX((USBD_BULK_ENABLE*(USBD_BULK_EP_BULKIN)), (USBD_BULK_ENABLE*(USBD_BULK_EP_BULKOUT))) #define USBD_EP_NUM MAX(USBD_EP_NUM_CALC6, USBD_EP_NUM_CALC7) - #if (USBD_HID_ENABLE) #if (USBD_MSC_ENABLE) #if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ @@ -469,7 +469,6 @@ #define USBD_ADC_SIF1_NUM (1) #define USBD_ADC_SIF2_NUM (2) - #define USBD_ADC_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+0) #define USBD_ADC_SIF1_STR_NUM (3+USBD_STRDESC_SER_ENABLE+1) #define USBD_ADC_SIF2_STR_NUM (3+USBD_STRDESC_SER_ENABLE+2) @@ -480,7 +479,6 @@ #define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) #define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) - #if (USBD_HID_ENABLE) #if (USBD_HID_HS_ENABLE) #define USBD_HID_MAX_PACKET ((USBD_HID_HS_WMAXPACKETSIZE > USBD_HID_WMAXPACKETSIZE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) @@ -532,7 +530,6 @@ #else #define USBD_BULK_MAX_PACKET (0) #endif - #define USBD_MAX_PACKET_CALC0 ((USBD_HID_MAX_PACKET > USBD_HID_MAX_PACKET ) ? (USBD_HID_MAX_PACKET ) : (USBD_HID_MAX_PACKET )) #define USBD_MAX_PACKET_CALC1 ((USBD_ADC_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET ) ? (USBD_ADC_MAX_PACKET ) : (USBD_CDC_ACM_MAX_PACKET )) #define USBD_MAX_PACKET_CALC2 ((USBD_MAX_PACKET_CALC0 > USBD_MAX_PACKET_CALC1 ) ? (USBD_MAX_PACKET_CALC0) : (USBD_MAX_PACKET_CALC1 )) From c0ae45d75681375926f4e6ed15166d0010980ff4 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 24 Apr 2021 21:00:40 -0500 Subject: [PATCH 159/617] USB cleanup: max32620 and max32625 usb_config.c files are now identical --- source/hic_hal/maxim/max32620/usb_config.c | 10 +++++----- source/hic_hal/maxim/max32625/usb_config.c | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/source/hic_hal/maxim/max32620/usb_config.c b/source/hic_hal/maxim/max32620/usb_config.c index 57577a9fa..665fe6fd9 100644 --- a/source/hic_hal/maxim/max32620/usb_config.c +++ b/source/hic_hal/maxim/max32620/usb_config.c @@ -10,7 +10,7 @@ * not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT @@ -411,15 +411,15 @@ #define USBD_EP_NUM MAX(USBD_EP_NUM_CALC6, USBD_EP_NUM_CALC7) #if (USBD_EP_NUM > 7) -#error "Max32620 only have 8 individual endpoints including EP0!" +#error "Max32620/Max32625 only have 8 individual endpoints including EP0!" #endif #if (USBD_HID_ENABLE) #if (USBD_MSC_ENABLE) -#if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ +#if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ (USBD_HID_EP_INTIN == USBD_MSC_EP_BULKOUT))) || \ - ((USBD_HID_EP_INTOUT != 0) && \ - (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKIN) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKIN) || \ (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKOUT))) #error "HID and Mass Storage Device Interface can not use same Endpoints!" #endif diff --git a/source/hic_hal/maxim/max32625/usb_config.c b/source/hic_hal/maxim/max32625/usb_config.c index 57577a9fa..665fe6fd9 100755 --- a/source/hic_hal/maxim/max32625/usb_config.c +++ b/source/hic_hal/maxim/max32625/usb_config.c @@ -10,7 +10,7 @@ * not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT @@ -411,15 +411,15 @@ #define USBD_EP_NUM MAX(USBD_EP_NUM_CALC6, USBD_EP_NUM_CALC7) #if (USBD_EP_NUM > 7) -#error "Max32620 only have 8 individual endpoints including EP0!" +#error "Max32620/Max32625 only have 8 individual endpoints including EP0!" #endif #if (USBD_HID_ENABLE) #if (USBD_MSC_ENABLE) -#if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ +#if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ (USBD_HID_EP_INTIN == USBD_MSC_EP_BULKOUT))) || \ - ((USBD_HID_EP_INTOUT != 0) && \ - (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKIN) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKIN) || \ (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKOUT))) #error "HID and Mass Storage Device Interface can not use same Endpoints!" #endif From f8ce6cf0e7e4dcf7a02b98c8b4061f3b60a720f5 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 24 Apr 2021 21:02:57 -0500 Subject: [PATCH 160/617] USB cleanup: make USBD_STRDESC_PROD consistently customizable --- source/hic_hal/nuvoton/m48ssidae/usb_config.c | 6 ++++++ source/hic_hal/stm32/stm32f103xb/usb_config.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/source/hic_hal/nuvoton/m48ssidae/usb_config.c b/source/hic_hal/nuvoton/m48ssidae/usb_config.c index 0194dac0c..187f0aec2 100644 --- a/source/hic_hal/nuvoton/m48ssidae/usb_config.c +++ b/source/hic_hal/nuvoton/m48ssidae/usb_config.c @@ -87,7 +87,13 @@ // #define USBD_STRDESC_LANGID 0x0409 #define USBD_STRDESC_MAN L"Arm" +#ifndef USB_PROD_STR #define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" +#else +#define _TOWIDE(x) L ## #x +#define TOWIDE(x) _TOWIDE(x) +#define USBD_STRDESC_PROD TOWIDE(USB_PROD_STR) +#endif #define USBD_STRDESC_SER_ENABLE 1 #define USBD_STRDESC_SER L"0001A0000000" diff --git a/source/hic_hal/stm32/stm32f103xb/usb_config.c b/source/hic_hal/stm32/stm32f103xb/usb_config.c index ecb49706e..97e59ec5e 100644 --- a/source/hic_hal/stm32/stm32f103xb/usb_config.c +++ b/source/hic_hal/stm32/stm32f103xb/usb_config.c @@ -87,7 +87,13 @@ // #define USBD_STRDESC_LANGID 0x0409 #define USBD_STRDESC_MAN L"Arm" +#ifndef USB_PROD_STR #define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" +#else +#define _TOWIDE(x) L ## #x +#define TOWIDE(x) _TOWIDE(x) +#define USBD_STRDESC_PROD TOWIDE(USB_PROD_STR) +#endif #define USBD_STRDESC_SER_ENABLE 1 #define USBD_STRDESC_SER L"0001A0000000" From cfefd79a318a4ee538a8ea3f72c948b9db8a5050 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 24 Apr 2021 21:05:01 -0500 Subject: [PATCH 161/617] USB cleanup: copy-paste failure --- source/hic_hal/freescale/kl26z/usb_config.c | 2 +- source/hic_hal/freescale/kl27z/usb_config.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/source/hic_hal/freescale/kl26z/usb_config.c b/source/hic_hal/freescale/kl26z/usb_config.c index 680005a86..d8a42894c 100644 --- a/source/hic_hal/freescale/kl26z/usb_config.c +++ b/source/hic_hal/freescale/kl26z/usb_config.c @@ -31,7 +31,7 @@ // High-speed // Enable high-speed functionality (if device supports it) #define USBD_HS_ENABLE 0 -#if (defined(WEBUSB_INTERFACE) || defined(WINUSB_INTERFACE) || defined(WINUSB_INTERFACE)) +#if (defined(WEBUSB_INTERFACE) || defined(WINUSB_INTERFACE) || defined(BULK_ENDPOINT)) #define USBD_BOS_ENABLE 1 #else #define USBD_BOS_ENABLE 0 diff --git a/source/hic_hal/freescale/kl27z/usb_config.c b/source/hic_hal/freescale/kl27z/usb_config.c index 024cd7e9c..f15dfc20f 100644 --- a/source/hic_hal/freescale/kl27z/usb_config.c +++ b/source/hic_hal/freescale/kl27z/usb_config.c @@ -31,7 +31,7 @@ // High-speed // Enable high-speed functionality (if device supports it) #define USBD_HS_ENABLE 0 -#if (defined(WEBUSB_INTERFACE) || defined(WINUSB_INTERFACE) || defined(WINUSB_INTERFACE)) +#if (defined(WEBUSB_INTERFACE) || defined(WINUSB_INTERFACE) || defined(BULK_ENDPOINT)) #define USBD_BOS_ENABLE 1 #else #define USBD_BOS_ENABLE 0 From b86a5349eb4d550bfa9b611c278840a984447cd0 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 24 Apr 2021 21:06:14 -0500 Subject: [PATCH 162/617] USB cleanup: fix endpoint check --- source/hic_hal/nuvoton/m48ssidae/usb_config.c | 8 ++++---- source/hic_hal/stm32/stm32f103xb/usb_config.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/source/hic_hal/nuvoton/m48ssidae/usb_config.c b/source/hic_hal/nuvoton/m48ssidae/usb_config.c index 187f0aec2..00ccc99cd 100644 --- a/source/hic_hal/nuvoton/m48ssidae/usb_config.c +++ b/source/hic_hal/nuvoton/m48ssidae/usb_config.c @@ -414,10 +414,10 @@ #if (USBD_HID_ENABLE) #if (USBD_MSC_ENABLE) -#if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ - (USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN)))|| \ - ((USBD_HID_EP_INTOUT != 0) && \ - (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKIN) || \ +#if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_MSC_EP_BULKOUT))) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKIN) || \ (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKOUT))) #error "HID and Mass Storage Device Interface can not use same Endpoints!" #endif diff --git a/source/hic_hal/stm32/stm32f103xb/usb_config.c b/source/hic_hal/stm32/stm32f103xb/usb_config.c index 97e59ec5e..4afa207de 100644 --- a/source/hic_hal/stm32/stm32f103xb/usb_config.c +++ b/source/hic_hal/stm32/stm32f103xb/usb_config.c @@ -414,10 +414,10 @@ #if (USBD_HID_ENABLE) #if (USBD_MSC_ENABLE) -#if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ - (USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN)))|| \ - ((USBD_HID_EP_INTOUT != 0) && \ - (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKIN) || \ +#if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_MSC_EP_BULKOUT))) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKIN) || \ (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKOUT))) #error "HID and Mass Storage Device Interface can not use same Endpoints!" #endif From 2070a7cfa01c42c978c658cce69f79c656cafc37 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 24 Apr 2021 21:08:02 -0500 Subject: [PATCH 163/617] USB cleanup: remove erroneous comment --- source/hic_hal/nuvoton/m48ssidae/usb_config.c | 2 +- source/hic_hal/stm32/stm32f103xb/usb_config.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/source/hic_hal/nuvoton/m48ssidae/usb_config.c b/source/hic_hal/nuvoton/m48ssidae/usb_config.c index 00ccc99cd..279b53e73 100644 --- a/source/hic_hal/nuvoton/m48ssidae/usb_config.c +++ b/source/hic_hal/nuvoton/m48ssidae/usb_config.c @@ -56,7 +56,7 @@ #define USBD_MAX_PACKET0 64 #define USBD_DEVDESC_IDVENDOR 0x0D28 #define USBD_DEVDESC_IDPRODUCT 0x0204 -#define USBD_DEVDESC_BCDDEVICE 0x0100 //was 0x0100 +#define USBD_DEVDESC_BCDDEVICE 0x0100 // Configuration Settings // These settings affect Configuration Descriptor diff --git a/source/hic_hal/stm32/stm32f103xb/usb_config.c b/source/hic_hal/stm32/stm32f103xb/usb_config.c index 4afa207de..bb962873f 100644 --- a/source/hic_hal/stm32/stm32f103xb/usb_config.c +++ b/source/hic_hal/stm32/stm32f103xb/usb_config.c @@ -56,7 +56,7 @@ #define USBD_MAX_PACKET0 64 #define USBD_DEVDESC_IDVENDOR 0x0D28 #define USBD_DEVDESC_IDPRODUCT 0x0204 -#define USBD_DEVDESC_BCDDEVICE 0x0100 //was 0x0100 +#define USBD_DEVDESC_BCDDEVICE 0x0100 // Configuration Settings // These settings affect Configuration Descriptor From 6fd673311ecba9060f624cbc26aff637c983d7e3 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 24 Apr 2021 21:08:38 -0500 Subject: [PATCH 164/617] USB cleanup: fix case --- source/hic_hal/freescale/kl27z/usb_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/hic_hal/freescale/kl27z/usb_config.c b/source/hic_hal/freescale/kl27z/usb_config.c index f15dfc20f..d8a42894c 100644 --- a/source/hic_hal/freescale/kl27z/usb_config.c +++ b/source/hic_hal/freescale/kl27z/usb_config.c @@ -86,7 +86,7 @@ // // #define USBD_STRDESC_LANGID 0x0409 -#define USBD_STRDESC_MAN L"ARM" +#define USBD_STRDESC_MAN L"Arm" #ifndef USB_PROD_STR #define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" #else From 69d69eb6acd782f2ebcb03ba3d5470d56122bf5e Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 24 Apr 2021 21:09:08 -0500 Subject: [PATCH 165/617] USB cleanup: keep order consistent with the other files --- source/hic_hal/nxp/lpc11u35/usb_config.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/source/hic_hal/nxp/lpc11u35/usb_config.c b/source/hic_hal/nxp/lpc11u35/usb_config.c index 15aafac8b..24dc5de89 100644 --- a/source/hic_hal/nxp/lpc11u35/usb_config.c +++ b/source/hic_hal/nxp/lpc11u35/usb_config.c @@ -27,15 +27,15 @@ #define USBD_RTX_CORE_STACK 0 #define USBD_RTX_DEVICE_STACK 0 #define USBD_RTX_ENDPOINT0_STACK 0 + +// High-speed +// Enable high-speed functionality (if device supports it) +#define USBD_HS_ENABLE 0 #if (defined(WEBUSB_INTERFACE) || defined(WINUSB_INTERFACE) || defined(BULK_ENDPOINT)) #define USBD_BOS_ENABLE 1 #else #define USBD_BOS_ENABLE 0 #endif -// High-speed -// Enable high-speed functionality (if device supports it) -#define USBD_HS_ENABLE 0 - // Device Settings // These settings affect Device Descriptor // Power From 0c82dda8f03cc18ca8c352a31838552815f42eb8 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 24 Apr 2021 21:10:20 -0500 Subject: [PATCH 166/617] USB cleanup: make file consistent with k26 and lpc55s69 version --- source/hic_hal/nxp/lpc4322/usb_config.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/source/hic_hal/nxp/lpc4322/usb_config.c b/source/hic_hal/nxp/lpc4322/usb_config.c index ab58ae22d..536d261a8 100644 --- a/source/hic_hal/nxp/lpc4322/usb_config.c +++ b/source/hic_hal/nxp/lpc4322/usb_config.c @@ -21,6 +21,15 @@ #include "util.h" +//*** <<< Use Configuration Wizard in Context Menu >>> *** + +// **** +// NOTE: The high speed packet sizes are set to the same size as full speed in this +// USB configuration in order to increase the number of devices that can +// simultaneously be connected to a single USB controller. With the maximium +// high speed packet sizes, only 1 or 2 devices can be connected. +// **** + // USB Device // Enable the USB Device functionality #define USBD_ENABLE 1 @@ -56,7 +65,7 @@ #define USBD_MAX_PACKET0 64 #define USBD_DEVDESC_IDVENDOR 0x0D28 #define USBD_DEVDESC_IDPRODUCT 0x0204 -#define USBD_DEVDESC_BCDDEVICE 0x1000 +#define USBD_DEVDESC_BCDDEVICE 0x1000 //was 0x0100 // Configuration Settings // These settings affect Configuration Descriptor @@ -153,12 +162,11 @@ #define USBD_HID_EP_INTIN 1 #define USBD_HID_EP_INTOUT 1 -#define USBD_HID_ENABLE HID_ENDPOINT #define USBD_HID_EP_INTIN_STACK 0 #define USBD_HID_WMAXPACKETSIZE 64 #define USBD_HID_BINTERVAL 1 #define USBD_HID_HS_ENABLE 1 -#define USBD_HID_HS_WMAXPACKETSIZE 64 +#define USBD_HID_HS_WMAXPACKETSIZE 64 //| (2<<11) #define USBD_HID_HS_BINTERVAL 1 #define USBD_HID_STRDESC L"CMSIS-DAP v1" #define USBD_WEBUSB_STRDESC L"WebUSB: CMSIS-DAP" From 63156040e1a0ace3b979b5e8dc2e0e843488d717 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 18 May 2021 21:40:55 -0500 Subject: [PATCH 167/617] USB cleanup: fix typo in USBD_BULK_IF_NUM definition (fix for issue #810) --- source/hic_hal/atmel/sam3u2c/usb_config.c | 2 +- source/hic_hal/freescale/k20dx/usb_config.c | 2 +- source/hic_hal/freescale/k26f/usb_config.c | 2 +- source/hic_hal/freescale/kl26z/usb_config.c | 2 +- source/hic_hal/freescale/kl27z/usb_config.c | 2 +- source/hic_hal/maxim/max32620/usb_config.c | 2 +- source/hic_hal/maxim/max32625/usb_config.c | 2 +- source/hic_hal/nuvoton/m48ssidae/usb_config.c | 2 +- source/hic_hal/nxp/lpc11u35/usb_config.c | 2 +- source/hic_hal/nxp/lpc4322/usb_config.c | 2 +- source/hic_hal/nxp/lpc55xx/usb_config.c | 2 +- source/hic_hal/stm32/stm32f103xb/usb_config.c | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-) diff --git a/source/hic_hal/atmel/sam3u2c/usb_config.c b/source/hic_hal/atmel/sam3u2c/usb_config.c index 626378346..bac2355de 100644 --- a/source/hic_hal/atmel/sam3u2c/usb_config.c +++ b/source/hic_hal/atmel/sam3u2c/usb_config.c @@ -484,7 +484,7 @@ #define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) #define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) #define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) -#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_MSC_ENABLE) #if (USBD_HID_ENABLE) #if (USBD_HID_HS_ENABLE) diff --git a/source/hic_hal/freescale/k20dx/usb_config.c b/source/hic_hal/freescale/k20dx/usb_config.c index d8a42894c..e664a1358 100644 --- a/source/hic_hal/freescale/k20dx/usb_config.c +++ b/source/hic_hal/freescale/k20dx/usb_config.c @@ -478,7 +478,7 @@ #define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) #define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) #define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) -#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_MSC_ENABLE) #if (USBD_HID_ENABLE) #if (USBD_HID_HS_ENABLE) diff --git a/source/hic_hal/freescale/k26f/usb_config.c b/source/hic_hal/freescale/k26f/usb_config.c index 536d261a8..ec39a27d2 100644 --- a/source/hic_hal/freescale/k26f/usb_config.c +++ b/source/hic_hal/freescale/k26f/usb_config.c @@ -487,7 +487,7 @@ #define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) #define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) #define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) -#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_MSC_ENABLE) #if (USBD_HID_ENABLE) #if (USBD_HID_HS_ENABLE) diff --git a/source/hic_hal/freescale/kl26z/usb_config.c b/source/hic_hal/freescale/kl26z/usb_config.c index d8a42894c..e664a1358 100644 --- a/source/hic_hal/freescale/kl26z/usb_config.c +++ b/source/hic_hal/freescale/kl26z/usb_config.c @@ -478,7 +478,7 @@ #define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) #define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) #define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) -#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_MSC_ENABLE) #if (USBD_HID_ENABLE) #if (USBD_HID_HS_ENABLE) diff --git a/source/hic_hal/freescale/kl27z/usb_config.c b/source/hic_hal/freescale/kl27z/usb_config.c index d8a42894c..e664a1358 100644 --- a/source/hic_hal/freescale/kl27z/usb_config.c +++ b/source/hic_hal/freescale/kl27z/usb_config.c @@ -478,7 +478,7 @@ #define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) #define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) #define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) -#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_MSC_ENABLE) #if (USBD_HID_ENABLE) #if (USBD_HID_HS_ENABLE) diff --git a/source/hic_hal/maxim/max32620/usb_config.c b/source/hic_hal/maxim/max32620/usb_config.c index 665fe6fd9..be720794c 100644 --- a/source/hic_hal/maxim/max32620/usb_config.c +++ b/source/hic_hal/maxim/max32620/usb_config.c @@ -485,7 +485,7 @@ #define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) #define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) #define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) -#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_MSC_ENABLE) #if (USBD_HID_ENABLE) #if (USBD_HID_HS_ENABLE) diff --git a/source/hic_hal/maxim/max32625/usb_config.c b/source/hic_hal/maxim/max32625/usb_config.c index 665fe6fd9..be720794c 100755 --- a/source/hic_hal/maxim/max32625/usb_config.c +++ b/source/hic_hal/maxim/max32625/usb_config.c @@ -485,7 +485,7 @@ #define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) #define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) #define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) -#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_MSC_ENABLE) #if (USBD_HID_ENABLE) #if (USBD_HID_HS_ENABLE) diff --git a/source/hic_hal/nuvoton/m48ssidae/usb_config.c b/source/hic_hal/nuvoton/m48ssidae/usb_config.c index 279b53e73..761412587 100644 --- a/source/hic_hal/nuvoton/m48ssidae/usb_config.c +++ b/source/hic_hal/nuvoton/m48ssidae/usb_config.c @@ -483,7 +483,7 @@ #define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) #define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) #define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) -#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_MSC_ENABLE) #if (USBD_HID_ENABLE) #if (USBD_HID_HS_ENABLE) diff --git a/source/hic_hal/nxp/lpc11u35/usb_config.c b/source/hic_hal/nxp/lpc11u35/usb_config.c index 24dc5de89..f9696b784 100644 --- a/source/hic_hal/nxp/lpc11u35/usb_config.c +++ b/source/hic_hal/nxp/lpc11u35/usb_config.c @@ -488,7 +488,7 @@ #define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) #define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) #define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) -#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_MSC_ENABLE) #if (USBD_HID_ENABLE) #if (USBD_HID_HS_ENABLE) diff --git a/source/hic_hal/nxp/lpc4322/usb_config.c b/source/hic_hal/nxp/lpc4322/usb_config.c index 536d261a8..ec39a27d2 100644 --- a/source/hic_hal/nxp/lpc4322/usb_config.c +++ b/source/hic_hal/nxp/lpc4322/usb_config.c @@ -487,7 +487,7 @@ #define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) #define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) #define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) -#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_MSC_ENABLE) #if (USBD_HID_ENABLE) #if (USBD_HID_HS_ENABLE) diff --git a/source/hic_hal/nxp/lpc55xx/usb_config.c b/source/hic_hal/nxp/lpc55xx/usb_config.c index 536d261a8..ec39a27d2 100644 --- a/source/hic_hal/nxp/lpc55xx/usb_config.c +++ b/source/hic_hal/nxp/lpc55xx/usb_config.c @@ -487,7 +487,7 @@ #define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) #define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) #define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) -#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_MSC_ENABLE) #if (USBD_HID_ENABLE) #if (USBD_HID_HS_ENABLE) diff --git a/source/hic_hal/stm32/stm32f103xb/usb_config.c b/source/hic_hal/stm32/stm32f103xb/usb_config.c index bb962873f..17e94e74a 100644 --- a/source/hic_hal/stm32/stm32f103xb/usb_config.c +++ b/source/hic_hal/stm32/stm32f103xb/usb_config.c @@ -483,7 +483,7 @@ #define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) #define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) #define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) -#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_BULK_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_MSC_ENABLE) #if (USBD_HID_ENABLE) #if (USBD_HID_HS_ENABLE) From 3f170210f8ccfcd2c7f2a9a98263a46c4c4e8745 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 18 May 2021 21:50:35 -0500 Subject: [PATCH 168/617] USB cleanup: add WINUSB_INTERFACE redefinition for consistency (see #810) --- source/hic_hal/atmel/sam3u2c/usb_config.c | 6 ++++++ source/hic_hal/freescale/k20dx/usb_config.c | 6 ++++++ source/hic_hal/freescale/k26f/usb_config.c | 6 ++++++ source/hic_hal/freescale/kl26z/usb_config.c | 6 ++++++ source/hic_hal/freescale/kl27z/usb_config.c | 6 ++++++ source/hic_hal/maxim/max32620/usb_config.c | 6 ++++++ source/hic_hal/maxim/max32625/usb_config.c | 6 ++++++ source/hic_hal/nuvoton/m48ssidae/usb_config.c | 6 ++++++ source/hic_hal/nxp/lpc11u35/usb_config.c | 6 ++++++ source/hic_hal/nxp/lpc4322/usb_config.c | 6 ++++++ source/hic_hal/nxp/lpc55xx/usb_config.c | 6 ++++++ source/hic_hal/stm32/stm32f103xb/usb_config.c | 6 ++++++ 12 files changed, 72 insertions(+) diff --git a/source/hic_hal/atmel/sam3u2c/usb_config.c b/source/hic_hal/atmel/sam3u2c/usb_config.c index bac2355de..ed39c0cfb 100644 --- a/source/hic_hal/atmel/sam3u2c/usb_config.c +++ b/source/hic_hal/atmel/sam3u2c/usb_config.c @@ -149,6 +149,12 @@ #define WEBUSB_INTERFACE 1 #endif +#ifndef WINUSB_INTERFACE +#define WINUSB_INTERFACE 0 +#else +#define WINUSB_INTERFACE 1 +#endif + #define USBD_HID_ENABLE HID_ENDPOINT #define USBD_HID_EP_INTIN 3 #define USBD_HID_EP_INTIN_STACK 0 diff --git a/source/hic_hal/freescale/k20dx/usb_config.c b/source/hic_hal/freescale/k20dx/usb_config.c index e664a1358..123957820 100644 --- a/source/hic_hal/freescale/k20dx/usb_config.c +++ b/source/hic_hal/freescale/k20dx/usb_config.c @@ -149,6 +149,12 @@ #define WEBUSB_INTERFACE 1 #endif +#ifndef WINUSB_INTERFACE +#define WINUSB_INTERFACE 0 +#else +#define WINUSB_INTERFACE 1 +#endif + #define USBD_HID_ENABLE HID_ENDPOINT #define USBD_HID_EP_INTIN 1 #define USBD_HID_EP_INTOUT 1 diff --git a/source/hic_hal/freescale/k26f/usb_config.c b/source/hic_hal/freescale/k26f/usb_config.c index ec39a27d2..f816f800c 100644 --- a/source/hic_hal/freescale/k26f/usb_config.c +++ b/source/hic_hal/freescale/k26f/usb_config.c @@ -158,6 +158,12 @@ #define WEBUSB_INTERFACE 1 #endif +#ifndef WINUSB_INTERFACE +#define WINUSB_INTERFACE 0 +#else +#define WINUSB_INTERFACE 1 +#endif + #define USBD_HID_ENABLE HID_ENDPOINT #define USBD_HID_EP_INTIN 1 #define USBD_HID_EP_INTOUT 1 diff --git a/source/hic_hal/freescale/kl26z/usb_config.c b/source/hic_hal/freescale/kl26z/usb_config.c index e664a1358..123957820 100644 --- a/source/hic_hal/freescale/kl26z/usb_config.c +++ b/source/hic_hal/freescale/kl26z/usb_config.c @@ -149,6 +149,12 @@ #define WEBUSB_INTERFACE 1 #endif +#ifndef WINUSB_INTERFACE +#define WINUSB_INTERFACE 0 +#else +#define WINUSB_INTERFACE 1 +#endif + #define USBD_HID_ENABLE HID_ENDPOINT #define USBD_HID_EP_INTIN 1 #define USBD_HID_EP_INTOUT 1 diff --git a/source/hic_hal/freescale/kl27z/usb_config.c b/source/hic_hal/freescale/kl27z/usb_config.c index e664a1358..123957820 100644 --- a/source/hic_hal/freescale/kl27z/usb_config.c +++ b/source/hic_hal/freescale/kl27z/usb_config.c @@ -149,6 +149,12 @@ #define WEBUSB_INTERFACE 1 #endif +#ifndef WINUSB_INTERFACE +#define WINUSB_INTERFACE 0 +#else +#define WINUSB_INTERFACE 1 +#endif + #define USBD_HID_ENABLE HID_ENDPOINT #define USBD_HID_EP_INTIN 1 #define USBD_HID_EP_INTOUT 1 diff --git a/source/hic_hal/maxim/max32620/usb_config.c b/source/hic_hal/maxim/max32620/usb_config.c index be720794c..ca50523e1 100644 --- a/source/hic_hal/maxim/max32620/usb_config.c +++ b/source/hic_hal/maxim/max32620/usb_config.c @@ -149,6 +149,12 @@ #define WEBUSB_INTERFACE 1 #endif +#ifndef WINUSB_INTERFACE +#define WINUSB_INTERFACE 0 +#else +#define WINUSB_INTERFACE 1 +#endif + #define USBD_HID_ENABLE HID_ENDPOINT #ifndef BULK_ENDPOINT //check if bulk endpoint is not enabled #define USBD_HID_EP_INTIN 1 diff --git a/source/hic_hal/maxim/max32625/usb_config.c b/source/hic_hal/maxim/max32625/usb_config.c index be720794c..ca50523e1 100755 --- a/source/hic_hal/maxim/max32625/usb_config.c +++ b/source/hic_hal/maxim/max32625/usb_config.c @@ -149,6 +149,12 @@ #define WEBUSB_INTERFACE 1 #endif +#ifndef WINUSB_INTERFACE +#define WINUSB_INTERFACE 0 +#else +#define WINUSB_INTERFACE 1 +#endif + #define USBD_HID_ENABLE HID_ENDPOINT #ifndef BULK_ENDPOINT //check if bulk endpoint is not enabled #define USBD_HID_EP_INTIN 1 diff --git a/source/hic_hal/nuvoton/m48ssidae/usb_config.c b/source/hic_hal/nuvoton/m48ssidae/usb_config.c index 761412587..053f59fed 100644 --- a/source/hic_hal/nuvoton/m48ssidae/usb_config.c +++ b/source/hic_hal/nuvoton/m48ssidae/usb_config.c @@ -149,6 +149,12 @@ #define WEBUSB_INTERFACE 1 #endif +#ifndef WINUSB_INTERFACE +#define WINUSB_INTERFACE 0 +#else +#define WINUSB_INTERFACE 1 +#endif + #define USBD_HID_ENABLE HID_ENDPOINT #ifndef BULK_ENDPOINT //check if bulk endpoint is not enabled #define USBD_HID_EP_INTIN 1 diff --git a/source/hic_hal/nxp/lpc11u35/usb_config.c b/source/hic_hal/nxp/lpc11u35/usb_config.c index f9696b784..9e6233b6c 100644 --- a/source/hic_hal/nxp/lpc11u35/usb_config.c +++ b/source/hic_hal/nxp/lpc11u35/usb_config.c @@ -149,6 +149,12 @@ #define WEBUSB_INTERFACE 1 #endif +#ifndef WINUSB_INTERFACE +#define WINUSB_INTERFACE 0 +#else +#define WINUSB_INTERFACE 1 +#endif + #define USBD_HID_ENABLE HID_ENDPOINT #ifndef BULK_ENDPOINT //check if bulk endpoint is not enabled #define USBD_HID_EP_INTIN 1 diff --git a/source/hic_hal/nxp/lpc4322/usb_config.c b/source/hic_hal/nxp/lpc4322/usb_config.c index ec39a27d2..f816f800c 100644 --- a/source/hic_hal/nxp/lpc4322/usb_config.c +++ b/source/hic_hal/nxp/lpc4322/usb_config.c @@ -158,6 +158,12 @@ #define WEBUSB_INTERFACE 1 #endif +#ifndef WINUSB_INTERFACE +#define WINUSB_INTERFACE 0 +#else +#define WINUSB_INTERFACE 1 +#endif + #define USBD_HID_ENABLE HID_ENDPOINT #define USBD_HID_EP_INTIN 1 #define USBD_HID_EP_INTOUT 1 diff --git a/source/hic_hal/nxp/lpc55xx/usb_config.c b/source/hic_hal/nxp/lpc55xx/usb_config.c index ec39a27d2..f816f800c 100644 --- a/source/hic_hal/nxp/lpc55xx/usb_config.c +++ b/source/hic_hal/nxp/lpc55xx/usb_config.c @@ -158,6 +158,12 @@ #define WEBUSB_INTERFACE 1 #endif +#ifndef WINUSB_INTERFACE +#define WINUSB_INTERFACE 0 +#else +#define WINUSB_INTERFACE 1 +#endif + #define USBD_HID_ENABLE HID_ENDPOINT #define USBD_HID_EP_INTIN 1 #define USBD_HID_EP_INTOUT 1 diff --git a/source/hic_hal/stm32/stm32f103xb/usb_config.c b/source/hic_hal/stm32/stm32f103xb/usb_config.c index 17e94e74a..0e70ae95d 100644 --- a/source/hic_hal/stm32/stm32f103xb/usb_config.c +++ b/source/hic_hal/stm32/stm32f103xb/usb_config.c @@ -149,6 +149,12 @@ #define WEBUSB_INTERFACE 1 #endif +#ifndef WINUSB_INTERFACE +#define WINUSB_INTERFACE 0 +#else +#define WINUSB_INTERFACE 1 +#endif + #define USBD_HID_ENABLE HID_ENDPOINT #ifndef BULK_ENDPOINT //check if bulk endpoint is not enabled #define USBD_HID_EP_INTIN 1 From 0b05775f6e75218692eaa4f3965a8a796e680baf Mon Sep 17 00:00:00 2001 From: thedjnK Date: Fri, 5 Mar 2021 16:31:47 +0000 Subject: [PATCH 169/617] Fix vfs_user.c to properly get magic file index --- source/daplink/drag-n-drop/vfs_user.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/daplink/drag-n-drop/vfs_user.c b/source/daplink/drag-n-drop/vfs_user.c index 20743336c..c4eab4610 100644 --- a/source/daplink/drag-n-drop/vfs_user.c +++ b/source/daplink/drag-n-drop/vfs_user.c @@ -219,7 +219,7 @@ void vfs_user_file_change_handler(const vfs_filename_t filename, vfs_file_change // Compare the new file's name to our table of magic filenames. for (int32_t i = 0; i < ARRAY_SIZE(s_magic_file_info); ++i) { if (!memcmp(filename, s_magic_file_info[i].name, sizeof(vfs_filename_t))) { - which_magic_file = i; + which_magic_file = s_magic_file_info[i].which; } } From 23fed1835f7265c5cb4e1b83bb13f8e09a00395d Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 27 May 2021 21:38:18 -0500 Subject: [PATCH 170/617] sam3u2c: add GCC support for functions executed from RAM --- .../hic_hal/atmel/sam3u2c/flash_hal_SAM3U.c | 28 +++++++++++++++++++ source/hic_hal/atmel/sam3u2c/read_uid.c | 4 +++ 2 files changed, 32 insertions(+) diff --git a/source/hic_hal/atmel/sam3u2c/flash_hal_SAM3U.c b/source/hic_hal/atmel/sam3u2c/flash_hal_SAM3U.c index e247d08b8..562a8d3f9 100644 --- a/source/hic_hal/atmel/sam3u2c/flash_hal_SAM3U.c +++ b/source/hic_hal/atmel/sam3u2c/flash_hal_SAM3U.c @@ -51,7 +51,11 @@ typedef struct { volatile uint32_t MC_FRR; } SFR_TABLE; +#if defined ( __GNUC__ ) +__attribute__((long_call, section(".data"))) +#else __attribute__((section("ram_func"))) +#endif static void _FeedWDT(void) { // @@ -69,7 +73,11 @@ static void _FeedWDT(void) ********************************************************************** */ +#if defined ( __GNUC__ ) +__attribute__((long_call, section(".data"))) +#else __attribute__((section("ram_func"))) +#endif static void _WritePage(uint32_t Addr, volatile uint32_t *pSrc, int PerformErase) { SFR_TABLE *pSFRs; @@ -120,7 +128,11 @@ static void _WritePage(uint32_t Addr, volatile uint32_t *pSrc, int PerformErase) * ********************************************************************** */ +#if defined ( __GNUC__ ) +__attribute__((long_call, section(".data"))) +#else __attribute__((section("ram_func"))) +#endif uint32_t Init(uint32_t adr, uint32_t clk, uint32_t fnc) { // @@ -129,7 +141,11 @@ uint32_t Init(uint32_t adr, uint32_t clk, uint32_t fnc) return (0); } +#if defined ( __GNUC__ ) +__attribute__((long_call, section(".data"))) +#else __attribute__((section("ram_func"))) +#endif uint32_t UnInit(uint32_t fnc) { // @@ -138,7 +154,11 @@ uint32_t UnInit(uint32_t fnc) return (0); } +#if defined ( __GNUC__ ) +__attribute__((long_call, section(".data"))) +#else __attribute__((section("ram_func"))) +#endif uint32_t EraseChip(void) { if (g_board_info.target_cfg) { @@ -162,7 +182,11 @@ uint32_t EraseChip(void) } } +#if defined ( __GNUC__ ) +__attribute__((long_call, section(".data"))) +#else __attribute__((section("ram_func"))) +#endif uint32_t EraseSector(uint32_t adr) { uint32_t NumPagesLeft; @@ -184,7 +208,11 @@ uint32_t EraseSector(uint32_t adr) return (0); // O.K. } +#if defined ( __GNUC__ ) +__attribute__((long_call, section(".data"))) +#else __attribute__((section("ram_func"))) +#endif uint32_t ProgramPage(uint32_t adr, uint32_t sz, uint32_t *buf) { uint32_t NumPagesLeft; diff --git a/source/hic_hal/atmel/sam3u2c/read_uid.c b/source/hic_hal/atmel/sam3u2c/read_uid.c index 3286f9cce..43107616a 100644 --- a/source/hic_hal/atmel/sam3u2c/read_uid.c +++ b/source/hic_hal/atmel/sam3u2c/read_uid.c @@ -40,7 +40,11 @@ void read_unique_id(uint32_t *id) id[3] = unique_id[3]; } +#if defined ( __GNUC__ ) +__attribute__((long_call, section(".data"))) +#else __attribute__((section("ram_func"))) +#endif void create_unique_id(void) { cortex_int_state_t state; From 0b3caf3badde59e3728d42a08459b04705d0531d Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 28 May 2021 16:42:29 -0500 Subject: [PATCH 171/617] hic_docs: Add initial lpc11u35 HIC documentation --- docs/hic/lpc11u35.md | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 docs/hic/lpc11u35.md diff --git a/docs/hic/lpc11u35.md b/docs/hic/lpc11u35.md new file mode 100644 index 000000000..a29e330d1 --- /dev/null +++ b/docs/hic/lpc11u35.md @@ -0,0 +1,39 @@ +# lpc11u35 HIC + +Based on LPC11U35FHI33/501 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet/LPC11U3X.pdf)): +- Cortex-M0 48 Mhz +- 64 KB Flash +- 12 KB RAM +- Full-speed USB 2.0 device controller +- HVQFN32 packaging + +## Memory Map + +| Region | Size | Start | End | +|----------|------|-------------|-------------| +| SRAM0 | 8 KB | 0x1000_0000 | 0x1000_2000 | +| SRAM1 | 2 KB | 0x2000_0000 | 0x2000_0800 | +| USB SRAM | 2 KB | 0x2000_4000 | 0x2000_4800 | + +Because of the flash size limitation, the presence of a ROM USB loader (also Cortex-M0 does not support vector table relocation). + +## DAPLink default pin assignment + +| Signal | I/O | Symbol | Pin | +|-------------|:---:|---------|:---:| +| SWD/JTAG | +| SWCLK / TCK | O | PIO0_7 | 16 | +| SWDIO / TMS | I/O | PIO0_8 | 17 | +| SWO / TDO | I | PIO0_9 | 18 | +| TDI | O | PIO0_17 | 30 | +| nRESET | O | PIO0_2 | 8 | +| UART (CDC) | +| UART TX | O | PIO0_18 | 31 | +| UART RX | I | PIO0_19 | 32 | +| Button | +| NF-RST But. | I | PIO0_1 | 3 | +| F-RST But. | I | PIO1_19 | 1 | +| LEDs | +| HID LED | O | PIO0_21 | 12 | +| MSD LED | O | PIO0_20 | 7 | +| CDC LED | O | PIO0_11 | 21 | From 2842c2cf2179cc06f93bb7f63ed7eb0a12404473 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 28 May 2021 20:00:46 -0500 Subject: [PATCH 172/617] hic_docs: Add initial stm32f103xb HIC documentation --- docs/hic/stm32f103xb.md | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 docs/hic/stm32f103xb.md diff --git a/docs/hic/stm32f103xb.md b/docs/hic/stm32f103xb.md new file mode 100644 index 000000000..8162faa65 --- /dev/null +++ b/docs/hic/stm32f103xb.md @@ -0,0 +1,36 @@ +# stm32f103xb HIC + +Based on STM32F103CBT6 chip ([Datasheet](https://www.st.com/resource/en/datasheet/stm32f103cb.pdf)): +- Cortex-M3 72 Mhz +- 128 KB Flash +- 20 KB RAM +- Full-speed USB 2.0 device controller +- UFQFPN48 packaging + +## Memory Map + +| Region | Size | Start | End | +|----------|--------|-------------|-------------| +| Flash | 128 KB | 0x0800_0000 | 0x0802_0000 | +| SRAM | 20 KB | 0x2000_0000 | 0x2000_5000 | + +## DAPLink default pin assignment + +| Signal | I/O | Symbol | Pin | +|-------------|:---:|---------|:---:| +| SWD/JTAG | +| SWCLK / TCK | O | PB13 | 26 | +| SWDIO / TDO | O | PB14 | 27 | +| SWDIO / TDO | I | PB12 | 25 | +| SWO / TDO | I | PA10 | 31 | +| nRESET | O | PB0 | 18 | +| UART (CDC) | +| UART RX | I | PA2 | 12 | +| UART TX | O | PA3 | 13 | +| Button | +| Button | I | PB15 | 28 | +| LEDs | +| Connect LED | O | PB6 | 42 | +| HID LED | O | PA9 | 30 | +| CDC LED | O | PA9 | 30 | +| MSC LED | O | PA9 | 30 | From 783cf79e5ee6754064480db62396a45bad8d581a Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 28 May 2021 22:41:06 -0500 Subject: [PATCH 173/617] hic_docs: Add initial k20dx HIC documentation --- docs/hic/k20dx.md | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 docs/hic/k20dx.md diff --git a/docs/hic/k20dx.md b/docs/hic/k20dx.md new file mode 100644 index 000000000..40444d0eb --- /dev/null +++ b/docs/hic/k20dx.md @@ -0,0 +1,32 @@ +# k20dx HIC + +Based on MK20DX128VFM5 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet/K20P32M50SF0.pdf): +- Cortex-M4 50 Mhz +- 160 KB Flash +- 16 KB RAM +- Full-speed USB 2.0 OTG controller +- HVQFN32 packaging + +## Memory Map + +| Region | Size | Start | End | +|----------|--------|-------------|-------------| +| Flash | 128 KB | 0x0000_0000 | 0x0002_0000 | +| SRAM | 16 KB | 0x1FFF_E000 | 0x2000_0000 | + +## DAPLink default pin assignment + +| Signal | I/O | Symbol | Pin | +|-------------|:---:|---------|:---:| +| SWD | +| SWCLK | O | PTC5 | 26 | +| SWDIO | O | PTC6 | 27 | +| SWDIO | I | PTC7 | 27 | +| nRESET | O | PTB1 | 21 | +| UART | +| UART RX | I | PTC3 | 24 | +| UART TX | O | PTC4 | 25 | +| Button | +| NF-RST But. | I | PTB1 | 21 | +| LEDs | +| LED | O | PTD4 | 29 | From 0a7695503ef78f139c780e2e4906ce9ca9fca40a Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 29 May 2021 00:15:27 -0500 Subject: [PATCH 174/617] hic_docs: Add initial lpc55xx HIC documentation --- docs/hic/lpc55xx.md | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 docs/hic/lpc55xx.md diff --git a/docs/hic/lpc55xx.md b/docs/hic/lpc55xx.md new file mode 100644 index 000000000..ad6b47863 --- /dev/null +++ b/docs/hic/lpc55xx.md @@ -0,0 +1,45 @@ +# lpc55xx HIC + +Based on LPC55S69JBD64 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet/LPC55S6x.pdf)): +- Cortex-M33 150 Mhz (cores) +- 640 KB Flash +- 320 KB RAM +- High-speed USB 2.0 host/device controller +- HTQFP64 packaging + +In order to support other MCUs from the LPC5500 family, the HIC limits usage +to one core, 320 KB Flash and 256 KB RAM. + +## Memory Map + +| Region | Size | Start | End | +|----------|--------|-------------|-------------| +| Flash | 320 KB | 0x0000_0000 | 0x0005_1000 | +| SRAM | 256 KB | 0x2000_0000 | 0x2004_0000 | +| USB RAM | 16 KB | 0x4010_0000 | 0x4010_4000 | + +## DAPLink default pin assignment + +Reference design is based on [MCU-Link](https://www.nxp.com/design/development-boards/lpcxpresso-boards/mcu-link-debug-probe:MCU-LINK). + +| Signal | I/O | Symbol | Pin | +|-------------|:---:|---------|:---:| +| SWD/JTAG | +| SWCLK / TCK | O | PIO0_0 | 36 | +| SWDIO / TMS | I/O | PIO0_2 | 52 | +| SWO / TDO | I | PIO0_3 | 53 | +| TDI | O | PIO0_1 | 2 | +| nRESET | O | PIO0_19 | 58 | +| GNDDetect | I | PIO0_22 | 50 | +| UART | +| UART RX | I | PIO0_24 | 45 | +| UART TX | O | PIO0_25 | 51 | +| Button | +| NF-RST But. | I | PIO0_18 | 38 | +| F-RST But. | I | PIO1_27 | 18 | +| LEDs | +| Con. LED | O | PIO0_5 | 56 | + +Additional pins are used to drive external circuitry: +- SWDIO TX Enable (PIO0_28, pin 44) +- nRESET Output Enable (PIO0_13, pin 46) From 088739456cd023855c4fda1c5ad8d1d1f42cf3de Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 29 May 2021 01:10:41 -0500 Subject: [PATCH 175/617] hic_docs: Add initial sam3u2c HIC documentation --- docs/hic/sam3u2c.md | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 docs/hic/sam3u2c.md diff --git a/docs/hic/sam3u2c.md b/docs/hic/sam3u2c.md new file mode 100644 index 000000000..32fc47972 --- /dev/null +++ b/docs/hic/sam3u2c.md @@ -0,0 +1,33 @@ +# sam3u2c HIC + +Based on ATSAM3U2C chip ([Datasheet](https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6430-32-bit-Cortex-M3-Microcontroller-SAM3U4-SAM3U2-SAM3U1_Datasheet.pdf)): +- Cortex-M3 96 Mhz +- 128 KB Flash +- 36 KB RAM +- High-speed USB 2.0 device controller +- LQFP100 packaging + +## Memory Map + +| Region | Size | Start | End | +|----------|--------|-------------|-------------| +| Flash | 128 KB | 0x0000_0000 | 0x0001_0000 | +| SRAM | 32 KB | 0x2007_C000 | 0x2008_3FFF | + +## DAPLink default pin assignment + +| Signal | I/O | Symbol | Pin | +|-------------|:---:|---------|:---:| +| SWD/JTAG | +| SWCLK / TCK | O | PA17 | 14 | +| SWDIO / TMS | I/O | PA18 | 17 | +| nRESET | O | PA30 | 30 | +| UART | +| UART TX | O | PA12 | 41 | +| UART RX | I | PA11 | 40 | +| Button | +| NF-RST But. | I | PA25 | 24 | +| LEDs | +| HID LED | O | PA29 | 85 | +| MSD LED | O | PA28 | 84 | +| CDC LED | O | PA31 | 86 | From 649472dd39a4a66218dc10e39f879c3da877ebdd Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 29 May 2021 01:41:08 -0500 Subject: [PATCH 176/617] hic_docs: Add initial kl26z HIC documentation --- docs/hic/kl26z.md | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 docs/hic/kl26z.md diff --git a/docs/hic/kl26z.md b/docs/hic/kl26z.md new file mode 100644 index 000000000..771c7c433 --- /dev/null +++ b/docs/hic/kl26z.md @@ -0,0 +1,34 @@ +# kl26z HIC + +Based on MKL26Z128VFM4 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet/KL26P64M48SF5.pdf)): +- Cortex-M0+ 48 Mhz +- 128 KB Flash +- 16 KB RAM +- Full-speed USB 2.0 OTG controller +- HVQFN32 packaging + +## Memory Map + +| Region | Size | Start | End | +|----------|--------|-------------|-------------| +| Flash | 128 KB | 0x0000_0000 | 0x0002_0000 | +| SRAM | 16 KB | 0x1FFF_F000 | 0x2000_3000 | + +## DAPLink default pin assignment + +| Signal | I/O | Symbol | Pin | +|-------------|:---:|---------|:---:| +| SWD/JTAG | +| SWCLK / TCK | O | PTC5 | 26 | +| SWDIO / TMS | I/O | PTC6 | 27 | +| SWO / TDO | I | PTC7 | 28 | +| nRESET | O | PTC8 | 22 | +| UART | +| UART RX | I | PTC3 | 24 | +| UART TX | O | PTC4 | 25 | +| Button | +| F-RST But. | I | PTB1 | 21 | +| LEDs | +| HID LED | O | PTD4 | 30 | +| MSD LED | O | PTD5 | 29 | +| CDC LED | O | PTD6 | 31 | From 9ad6e41dfae63541b0389ee8da5bb8a7213f277f Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 29 May 2021 01:59:12 -0500 Subject: [PATCH 177/617] hic_docs: Add initial kl27z HIC documentation --- docs/hic/kl27z.md | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 docs/hic/kl27z.md diff --git a/docs/hic/kl27z.md b/docs/hic/kl27z.md new file mode 100644 index 000000000..005e6e2aa --- /dev/null +++ b/docs/hic/kl27z.md @@ -0,0 +1,33 @@ +# kl27z HIC + +Based on MKL27Z256VFM4 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet/KL27P64M48SF6.pdf)): +- Cortex-M0+ 48 Mhz +- 256 KB Flash +- 32 KB RAM +- Full-speed USB 2.0 device controller +- HVQFN32 packaging + +## Memory Map + +| Region | Size | Start | End | +|----------|--------|-------------|-------------| +| Flash | 128 KB | 0x0000_0000 | 0x0002_0000 | +| SRAM | 32 KB | 0x1FFF_E000 | 0x2000_6000 | + +## DAPLink default pin assignment + +| Signal | I/O | Symbol | Pin | +|-------------|:---:|---------|:---:| +| SWD | +| SWCLK | O | PTC6 | 27 | +| SWDIO | I/O | PTC5 | 26 | +| nRESET | O | PTA20 | 19 | +| UART | +| UART RX | I | PTA18 | 17 | +| UART TX | O | PTA19 | 18 | +| Button | +| F-RST But. | I | PTD4 | 29 | +| LEDs | +| HID LED | O | PTB0 | 20 | +| MSD LED | O | PTD0 | 20 | +| CDC LED | O | PTD0 | 20 | From 1c3a214a4cedc8926947155468463d2675e1651e Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 29 May 2021 23:43:00 -0500 Subject: [PATCH 178/617] hic_docs: Add initial max32625 HIC documentation --- docs/hic/max32625.md | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 docs/hic/max32625.md diff --git a/docs/hic/max32625.md b/docs/hic/max32625.md new file mode 100644 index 000000000..0e4df8fb3 --- /dev/null +++ b/docs/hic/max32625.md @@ -0,0 +1,37 @@ +# max32625 HIC + +Based on MAX32625IWY+ chip ([Data Sheet](https://datasheets.maximintegrated.com/en/ds/MAX32625-MAX32626.pdf)): +- Cortex-M4 96 Mhz +- 512 KB Flash +- 160 KB RAM +- Full-speed USB 2.0 device controller +- 63 WLP packaging + +## Memory Map + +| Region | Size | Start | End | +|----------|--------|-------------|-------------| +| Flash | 512 KB | 0x0000_0000 | 0x0008_0000 | +| SRAM | 160 KB | 0x2000_0000 | 0x2002_8000 | + + +## DAPLink default pin assignment + +Reference design is based on [MAX32625PICO](https://www.maximintegrated.com/en/products/microcontrollers/MAX32625PICO.html). + + +| Signal | I/O | Symbol | Pin | +|-------------|:---:|---------|:---:| +| SWD | +| SWCLK | O | P3.2 | G6 | +| SWDIO | I/O | P3.3 | D5 | +| nRESET | O | P3.7 | G8 | +| UART | +| UART RX | I | P2.0 | E6 | +| UART TX | O | P2.1 | F6 | +| Button | +| NF-RST But. | I | P2.7 | G5 | +| LEDs | +| HID LED | O | P2.5 | E5 | +| MSD LED | O | P2.4 | G4 | +| CDC LED | O | P2.6 | G5 | From 6725272430f15c7655f84ee301f8d32032fef84f Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sun, 30 May 2021 00:16:30 -0500 Subject: [PATCH 179/617] hic_docs: Add initial k26f HIC documentation --- docs/hic/k26f.md | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 docs/hic/k26f.md diff --git a/docs/hic/k26f.md b/docs/hic/k26f.md new file mode 100644 index 000000000..ffeb1b80a --- /dev/null +++ b/docs/hic/k26f.md @@ -0,0 +1,33 @@ +# k26f HIC + +Based on MK26FN2M0VMI18 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet/K26P169M180SF5.pdf): +- Cortex-M4 180 Mhz +- 2 MB Flash +- 256 KB RAM +- High-speed USB 2.0 OTG controller +- LFBGA169 packaging + +## Memory Map + +| Region | Size | Start | End | +|----------|--------|-------------|-------------| +| Flash | 256 KB | 0x0000_0000 | 0x0004_0000 | +| SRAM | 256 KB | 0x1FFF_0000 | 0x2003_0000 | + +## DAPLink default pin assignment + +| Signal | I/O | Symbol | Pin | +|-------------|:---:|---------|:---:| +| SWD | +| SWCLK | O | PTC5 | A11 | +| SWDIO | O | PTC6 | A10 | +| SWDIO | I | PTC7 | B10 | +| SWO | I | PTC3 | A12 | +| nRESET | O | PTA7 | L10 | +| UART | +| UART RX | I | PTB16 | F8 | +| UART TX | O | PTB17 | D13 | +| Button | +| NF-RST But. | I | PTB1 | G12 | +| LEDs | +| LED | O | PTD4 | B5 | From 9913759d95591661fd0cc42529dac8415c8fba61 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sun, 30 May 2021 00:47:24 -0500 Subject: [PATCH 180/617] hic_docs: Add initial lpc4322 HIC documentation --- docs/hic/lpc4322.md | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 docs/hic/lpc4322.md diff --git a/docs/hic/lpc4322.md b/docs/hic/lpc4322.md new file mode 100644 index 000000000..1cddc3ab3 --- /dev/null +++ b/docs/hic/lpc4322.md @@ -0,0 +1,34 @@ +# lpc4322 HIC + +Based on LPC4322JET100E chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet/LPC435X_3X_2X_1X.pdf)): +- Cortex-M4 204 Mhz +- 512 KB Flash +- 104 KB RAM +- High-speed USB 2.0 device controller +- TFBGA100 packaging + +## Memory Map + +| Region | Size | Start | End | +|----------|--------|-------------|-------------| +| Flash | 200 KB | 0x1A00_0000 | 0x1A03_2000 | +| SRAM | 32 KB | 0x1000_0000 | 0x1000_8000 | + +## DAPLink default pin assignment + +| Signal | I/O | Symbol | Pin | +|-------------|:---:|---------|:---:| +| SWD/JTAG | +| SWCLK / TCK | O | P1_17 | H10 | +| SWDIO / TMS | I/O | P1_6 | K4 | +| SWO / TDO | I | P1_14 | J8 | +| TDI | O | P0_18 | J10 | +| nRESET | O | P2_5 | D10 | +| GNDDetect | I | P2_13 | A10 | +| UART | +| UART TX | O | P2_0 | G10 | +| UART RX | I | P2_1 | G7 | +| Button | +| NF-RST But. | I | P2_11 | A9 | +| LEDs | +| LED | O | P1_1 | K2 | From 88cfb6e7cd75fa49c638b9120e18d7d1ebf0f6b4 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sun, 30 May 2021 00:51:54 -0500 Subject: [PATCH 181/617] hic_docs: Add HIC index --- docs/hic/README.md | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 docs/hic/README.md diff --git a/docs/hic/README.md b/docs/hic/README.md new file mode 100644 index 000000000..6f8438939 --- /dev/null +++ b/docs/hic/README.md @@ -0,0 +1,12 @@ +# HICs + +- [k20](k20dx.md) +- [k26](k26f.md) +- [kl26z](kl26z.md) +- [kl27z](kl27z.md) +- [lpc11u35](lpc11u35.md) +- [lpc4322](lpc4322.md) +- [lpc55xx](lpc55xx.md) +- [max32625](max32625.md) +- [sam3u2c](sam3u2c.md) +- [stm32f103xb](stm32f103xb.md) From 2bbef69c1683ffeefee9855f35f88db96296aeb6 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sun, 30 May 2021 01:01:33 -0500 Subject: [PATCH 182/617] hic_docs: Add bootloader size --- docs/hic/k20dx.md | 2 ++ docs/hic/k26f.md | 2 ++ docs/hic/kl26z.md | 10 ++++++---- docs/hic/kl27z.md | 2 ++ docs/hic/lpc11u35.md | 13 +++++++------ docs/hic/lpc4322.md | 2 ++ docs/hic/lpc55xx.md | 2 ++ docs/hic/max32625.md | 1 + docs/hic/sam3u2c.md | 2 ++ docs/hic/stm32f103xb.md | 10 ++++++---- 10 files changed, 32 insertions(+), 14 deletions(-) diff --git a/docs/hic/k20dx.md b/docs/hic/k20dx.md index 40444d0eb..4e9166410 100644 --- a/docs/hic/k20dx.md +++ b/docs/hic/k20dx.md @@ -14,6 +14,8 @@ Based on MK20DX128VFM5 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet | Flash | 128 KB | 0x0000_0000 | 0x0002_0000 | | SRAM | 16 KB | 0x1FFF_E000 | 0x2000_0000 | +Bootloader size is 32 KB + ## DAPLink default pin assignment | Signal | I/O | Symbol | Pin | diff --git a/docs/hic/k26f.md b/docs/hic/k26f.md index ffeb1b80a..cbf8aee65 100644 --- a/docs/hic/k26f.md +++ b/docs/hic/k26f.md @@ -14,6 +14,8 @@ Based on MK26FN2M0VMI18 chip ([Data Sheet](https://www.nxp.com/docs/en/data-shee | Flash | 256 KB | 0x0000_0000 | 0x0004_0000 | | SRAM | 256 KB | 0x1FFF_0000 | 0x2003_0000 | +Bootloader size is 64 KB + ## DAPLink default pin assignment | Signal | I/O | Symbol | Pin | diff --git a/docs/hic/kl26z.md b/docs/hic/kl26z.md index 771c7c433..777958837 100644 --- a/docs/hic/kl26z.md +++ b/docs/hic/kl26z.md @@ -14,14 +14,16 @@ Based on MKL26Z128VFM4 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet | Flash | 128 KB | 0x0000_0000 | 0x0002_0000 | | SRAM | 16 KB | 0x1FFF_F000 | 0x2000_3000 | +Bootloader size is 32 KB + ## DAPLink default pin assignment | Signal | I/O | Symbol | Pin | |-------------|:---:|---------|:---:| -| SWD/JTAG | -| SWCLK / TCK | O | PTC5 | 26 | -| SWDIO / TMS | I/O | PTC6 | 27 | -| SWO / TDO | I | PTC7 | 28 | +| SWD | +| SWCLK | O | PTC5 | 26 | +| SWDIO | I/O | PTC6 | 27 | +| SWO | I | PTC7 | 28 | | nRESET | O | PTC8 | 22 | | UART | | UART RX | I | PTC3 | 24 | diff --git a/docs/hic/kl27z.md b/docs/hic/kl27z.md index 005e6e2aa..552682d43 100644 --- a/docs/hic/kl27z.md +++ b/docs/hic/kl27z.md @@ -14,6 +14,8 @@ Based on MKL27Z256VFM4 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet | Flash | 128 KB | 0x0000_0000 | 0x0002_0000 | | SRAM | 32 KB | 0x1FFF_E000 | 0x2000_6000 | +Bootloader size is 32 KB + ## DAPLink default pin assignment | Signal | I/O | Symbol | Pin | diff --git a/docs/hic/lpc11u35.md b/docs/hic/lpc11u35.md index a29e330d1..d75598b85 100644 --- a/docs/hic/lpc11u35.md +++ b/docs/hic/lpc11u35.md @@ -9,11 +9,12 @@ Based on LPC11U35FHI33/501 chip ([Data Sheet](https://www.nxp.com/docs/en/data-s ## Memory Map -| Region | Size | Start | End | -|----------|------|-------------|-------------| -| SRAM0 | 8 KB | 0x1000_0000 | 0x1000_2000 | -| SRAM1 | 2 KB | 0x2000_0000 | 0x2000_0800 | -| USB SRAM | 2 KB | 0x2000_4000 | 0x2000_4800 | +| Region | Size | Start | End | +|----------|-------|-------------|-------------| +| Flash | 64 KB | 0x0000_0000 | 0x0001_0000 | +| SRAM0 | 8 KB | 0x1000_0000 | 0x1000_2000 | +| SRAM1 | 2 KB | 0x2000_0000 | 0x2000_0800 | +| USB SRAM | 2 KB | 0x2000_4000 | 0x2000_4800 | Because of the flash size limitation, the presence of a ROM USB loader (also Cortex-M0 does not support vector table relocation). @@ -27,7 +28,7 @@ Because of the flash size limitation, the presence of a ROM USB loader (also Cor | SWO / TDO | I | PIO0_9 | 18 | | TDI | O | PIO0_17 | 30 | | nRESET | O | PIO0_2 | 8 | -| UART (CDC) | +| UART | | UART TX | O | PIO0_18 | 31 | | UART RX | I | PIO0_19 | 32 | | Button | diff --git a/docs/hic/lpc4322.md b/docs/hic/lpc4322.md index 1cddc3ab3..35d156961 100644 --- a/docs/hic/lpc4322.md +++ b/docs/hic/lpc4322.md @@ -14,6 +14,8 @@ Based on LPC4322JET100E chip ([Data Sheet](https://www.nxp.com/docs/en/data-shee | Flash | 200 KB | 0x1A00_0000 | 0x1A03_2000 | | SRAM | 32 KB | 0x1000_0000 | 0x1000_8000 | +Bootloader size is 64 KB + ## DAPLink default pin assignment | Signal | I/O | Symbol | Pin | diff --git a/docs/hic/lpc55xx.md b/docs/hic/lpc55xx.md index ad6b47863..7fc951021 100644 --- a/docs/hic/lpc55xx.md +++ b/docs/hic/lpc55xx.md @@ -18,6 +18,8 @@ to one core, 320 KB Flash and 256 KB RAM. | SRAM | 256 KB | 0x2000_0000 | 0x2004_0000 | | USB RAM | 16 KB | 0x4010_0000 | 0x4010_4000 | +Bootloader size is 64 KB + ## DAPLink default pin assignment Reference design is based on [MCU-Link](https://www.nxp.com/design/development-boards/lpcxpresso-boards/mcu-link-debug-probe:MCU-LINK). diff --git a/docs/hic/max32625.md b/docs/hic/max32625.md index 0e4df8fb3..9334baa5e 100644 --- a/docs/hic/max32625.md +++ b/docs/hic/max32625.md @@ -14,6 +14,7 @@ Based on MAX32625IWY+ chip ([Data Sheet](https://datasheets.maximintegrated.com/ | Flash | 512 KB | 0x0000_0000 | 0x0008_0000 | | SRAM | 160 KB | 0x2000_0000 | 0x2002_8000 | +Bootloader size is 64 KB ## DAPLink default pin assignment diff --git a/docs/hic/sam3u2c.md b/docs/hic/sam3u2c.md index 32fc47972..21e369572 100644 --- a/docs/hic/sam3u2c.md +++ b/docs/hic/sam3u2c.md @@ -14,6 +14,8 @@ Based on ATSAM3U2C chip ([Datasheet](https://ww1.microchip.com/downloads/en/Devi | Flash | 128 KB | 0x0000_0000 | 0x0001_0000 | | SRAM | 32 KB | 0x2007_C000 | 0x2008_3FFF | +Bootloader size is 32 KB + ## DAPLink default pin assignment | Signal | I/O | Symbol | Pin | diff --git a/docs/hic/stm32f103xb.md b/docs/hic/stm32f103xb.md index 8162faa65..b2178b95c 100644 --- a/docs/hic/stm32f103xb.md +++ b/docs/hic/stm32f103xb.md @@ -14,23 +14,25 @@ Based on STM32F103CBT6 chip ([Datasheet](https://www.st.com/resource/en/datashee | Flash | 128 KB | 0x0800_0000 | 0x0802_0000 | | SRAM | 20 KB | 0x2000_0000 | 0x2000_5000 | +Bootloader size is 48 KB + ## DAPLink default pin assignment | Signal | I/O | Symbol | Pin | |-------------|:---:|---------|:---:| | SWD/JTAG | | SWCLK / TCK | O | PB13 | 26 | -| SWDIO / TDO | O | PB14 | 27 | -| SWDIO / TDO | I | PB12 | 25 | +| SWDIO / TMS | O | PB14 | 27 | +| SWDIO / TMS | I | PB12 | 25 | | SWO / TDO | I | PA10 | 31 | | nRESET | O | PB0 | 18 | | UART (CDC) | | UART RX | I | PA2 | 12 | | UART TX | O | PA3 | 13 | | Button | -| Button | I | PB15 | 28 | +| NF-RST But. | I | PB15 | 28 | | LEDs | -| Connect LED | O | PB6 | 42 | +| Connect. LED| O | PB6 | 42 | | HID LED | O | PA9 | 30 | | CDC LED | O | PA9 | 30 | | MSC LED | O | PA9 | 30 | From 5245f1a665757c911b61824400ea53256f5d8379 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sun, 30 May 2021 01:30:09 -0500 Subject: [PATCH 183/617] hic_docs: make index a table + typos --- docs/hic/README.md | 23 +++++++++++++---------- docs/hic/k20dx.md | 2 +- docs/hic/k26f.md | 2 +- 3 files changed, 15 insertions(+), 12 deletions(-) diff --git a/docs/hic/README.md b/docs/hic/README.md index 6f8438939..2b49b72f7 100644 --- a/docs/hic/README.md +++ b/docs/hic/README.md @@ -1,12 +1,15 @@ # HICs -- [k20](k20dx.md) -- [k26](k26f.md) -- [kl26z](kl26z.md) -- [kl27z](kl27z.md) -- [lpc11u35](lpc11u35.md) -- [lpc4322](lpc4322.md) -- [lpc55xx](lpc55xx.md) -- [max32625](max32625.md) -- [sam3u2c](sam3u2c.md) -- [stm32f103xb](stm32f103xb.md) +| HIC | Core | Freq. | RAM | ROM | USB | +|-------------------------------|:----:|---------|--------|--------|:---:| +| [k20dx](k20dx.md) | M4 | 48 MHz | 16 KB | 128 KB | FS | +| [k26f](k26f.md) | M4 | 120 MHz | 256 KB | 256 KB | HS | +| [kl26z](kl26z.md) | M0+ | 48 Mhz | 16 KB | 128 KB | FS | +| [kl27z](kl27z.md) | M0+ | 48 Mhz | 32 KB | 128 KB | FS | +| [lpc11u35](lpc11u35.md) | M0 | 48 Mhz | 12 KB | 64 KB | FS | +| [lpc4322](lpc4322.md) | M4 | 96 MHz | 256 KB | 256 KB | HS | +| [lpc55xx](lpc55xx.md) | M33 | 150 MHz | 272 KB | 320 KB | HS | +| [max32625](max32625.md) | M4 | 96 MHz | 160 KB | 512 KB | FS | +| [sam3u2c](sam3u2c.md) | M3 | 96 MHz | 32 KB | 128 KB | HS | +| [stm32f103xb](stm32f103xb.md) | M3 | 72 Mhz | 20 KB | 128 KB | FS | + diff --git a/docs/hic/k20dx.md b/docs/hic/k20dx.md index 4e9166410..470d095e9 100644 --- a/docs/hic/k20dx.md +++ b/docs/hic/k20dx.md @@ -1,6 +1,6 @@ # k20dx HIC -Based on MK20DX128VFM5 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet/K20P32M50SF0.pdf): +Based on MK20DX128VFM5 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet/K20P32M50SF0.pdf)): - Cortex-M4 50 Mhz - 160 KB Flash - 16 KB RAM diff --git a/docs/hic/k26f.md b/docs/hic/k26f.md index cbf8aee65..94cf16be5 100644 --- a/docs/hic/k26f.md +++ b/docs/hic/k26f.md @@ -1,6 +1,6 @@ # k26f HIC -Based on MK26FN2M0VMI18 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet/K26P169M180SF5.pdf): +Based on MK26FN2M0VMI18 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet/K26P169M180SF5.pdf)): - Cortex-M4 180 Mhz - 2 MB Flash - 256 KB RAM From 7b60a5a96d03809407b0aae5a7b13757d7de05e6 Mon Sep 17 00:00:00 2001 From: Taylor Heck Date: Thu, 6 May 2021 16:10:33 -0500 Subject: [PATCH 184/617] Fix XDot RESET_PROGRAM. --- source/board/xDot-L151.c | 54 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 52 insertions(+), 2 deletions(-) diff --git a/source/board/xDot-L151.c b/source/board/xDot-L151.c index a0474d443..e7d42cc66 100644 --- a/source/board/xDot-L151.c +++ b/source/board/xDot-L151.c @@ -21,12 +21,62 @@ #include "target_family.h" #include "target_board.h" +#define DBG_Addr (0xe000edf0) +#include "swd_host.h" +#include "cmsis_os2.h" +#include "debug_cm.h" + +static uint8_t xdot_set_state(target_state_t state) +{ + uint32_t val; + + if (state == RESET_PROGRAM) { + swd_init(); + swd_set_target_reset(1); + osDelay(2); + + if (!swd_init_debug()) { + return 0; + } + + // Enable debug + if (!swd_write_word(DBG_HCSR, DBGKEY | C_HALT | C_DEBUGEN)) { + return 0; + } + + // Enable halt on reset + if (!swd_write_word(DBG_EMCR, VC_CORERESET)) { + return 0; + } + + // Deassert reset + swd_set_target_reset(0); + osDelay(2); + + do { + if (!swd_read_word(DBG_HCSR, &val)) { + return 0; + } + } while ((val & S_HALT) == 0); + + // Disable halt on reset + if (!swd_write_word(DBG_EMCR, 0)) { + return 0; + } + } else { + return swd_set_target_state_hw(state); + } + + return 1; +} const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "0350", .family_id = kStub_HWReset_FamilyID, - .daplink_url_name = "XDOT HTM", - .daplink_drive_name = "XDOT ", + .flags = kEnableUnderResetConnect, + .daplink_url_name = "XDOT HTM", + .daplink_drive_name = "XDOT ", .target_cfg = &target_device, + .target_set_state = xdot_set_state }; From 408a2af71fc476058a7395eef4bf9ba42fcaf93b Mon Sep 17 00:00:00 2001 From: ychsu Date: Wed, 7 Apr 2021 18:31:44 +0800 Subject: [PATCH 185/617] Add Nuvoton NuMaker-M2354 board --- projects.yaml | 4 + records/board/numaker_m2354.yaml | 7 + source/board/numaker_iot_m263a.c | 2 +- source/board/numaker_m2354.c | 31 +++++ source/board/numaker_m252kg.c | 2 +- source/board/numaker_pfm_m487km.c | 2 +- source/family/nuvoton/m2354kjfae/flash_blob.c | 121 ++++++++++++++++++ source/family/nuvoton/m2354kjfae/target.c | 46 +++++++ .../family/nuvoton/m2354kjfae/target_reset.c | 81 ++++++++++++ source/family/nuvoton/m252kg6ae/flash_blob.c | 2 +- source/family/nuvoton/m252kg6ae/target.c | 2 +- source/family/nuvoton/m263kiaae/flash_blob.c | 2 +- source/family/nuvoton/m263kiaae/target.c | 2 +- source/family/nuvoton/m487jidae/flash_blob.c | 2 +- source/family/nuvoton/m487jidae/target.c | 2 +- test/info.py | 2 + 16 files changed, 301 insertions(+), 9 deletions(-) create mode 100644 records/board/numaker_m2354.yaml create mode 100644 source/board/numaker_m2354.c create mode 100644 source/family/nuvoton/m2354kjfae/flash_blob.c create mode 100644 source/family/nuvoton/m2354kjfae/target.c create mode 100644 source/family/nuvoton/m2354kjfae/target_reset.c diff --git a/projects.yaml b/projects.yaml index 0a5199cf8..58bf5889d 100644 --- a/projects.yaml +++ b/projects.yaml @@ -683,6 +683,10 @@ projects: - *module_if - *module_hic_m48ssidae - records/board/numaker_pfm_m487km.yaml + m48ssidae_numaker_m2354_if: + - *module_if + - *module_hic_m48ssidae + - records/board/numaker_m2354.yaml lpc4322_hani_iot_if: - *module_if - *module_hic_lpc4322 diff --git a/records/board/numaker_m2354.yaml b/records/board/numaker_m2354.yaml new file mode 100644 index 000000000..8196fa936 --- /dev/null +++ b/records/board/numaker_m2354.yaml @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/numaker_m2354.c + family: + - source/family/nuvoton/m2354kjfae/target.c + - source/family/nuvoton/m2354kjfae/target_reset.c diff --git a/source/board/numaker_iot_m263a.c b/source/board/numaker_iot_m263a.c index 1b20a937f..48973d32c 100644 --- a/source/board/numaker_iot_m263a.c +++ b/source/board/numaker_iot_m263a.c @@ -3,7 +3,7 @@ * @brief board ID for the NuMaker-IoT-M263A board * * DAPLink Interface Firmware - * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2019 Nuvoton Technology Corp. All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may diff --git a/source/board/numaker_m2354.c b/source/board/numaker_m2354.c new file mode 100644 index 000000000..c25151184 --- /dev/null +++ b/source/board/numaker_m2354.c @@ -0,0 +1,31 @@ +/** + * @file numaker_m2354.c + * @brief board ID for the NuMaker-M2354 board + * + * DAPLink Interface Firmware + * Copyright (c) 2021 Nuvoton Technology Corp. All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_family.h" +#include "target_board.h" + +const board_info_t g_board_info = { + .info_version = kBoardInfoVersion, + .board_id = "1312", + .family_id = kStub_SWSysReset_FamilyID, + .flags = kEnablePageErase, + .target_cfg = &target_device, +}; diff --git a/source/board/numaker_m252kg.c b/source/board/numaker_m252kg.c index 6b0c0cb6f..a7cea5160 100644 --- a/source/board/numaker_m252kg.c +++ b/source/board/numaker_m252kg.c @@ -3,7 +3,7 @@ * @brief board ID for the NuMaker-M252KG board * * DAPLink Interface Firmware - * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2019 Nuvoton Technology Corp. All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may diff --git a/source/board/numaker_pfm_m487km.c b/source/board/numaker_pfm_m487km.c index e7bfedc5d..4314db2f9 100644 --- a/source/board/numaker_pfm_m487km.c +++ b/source/board/numaker_pfm_m487km.c @@ -3,7 +3,7 @@ * @brief board ID for the NuMaker-PFM-M487KM board * * DAPLink Interface Firmware - * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2020 Nuvoton Technology Corp. All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may diff --git a/source/family/nuvoton/m2354kjfae/flash_blob.c b/source/family/nuvoton/m2354kjfae/flash_blob.c new file mode 100644 index 000000000..875ec6c2a --- /dev/null +++ b/source/family/nuvoton/m2354kjfae/flash_blob.c @@ -0,0 +1,121 @@ +/* Flash OS Routines (Automagically Generated) + * Copyright (c) 2021 Nuvoton Technology Corp + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +static const uint32_t M2354_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x9018b09a, 0x92169117, 0x90154678, 0x90149815, 0x78c0a814, 0x280006c0, 0xe7ffd528, 0x68004860, + 0x280007c0, 0xe7ffd110, 0x2159485d, 0x21166001, 0x21886001, 0x68006001, 0x280007c0, 0xe7ffd103, + 0x90192001, 0xe7ffe0a1, 0x68014856, 0x43112204, 0x48556001, 0x43116801, 0xe7ff6001, 0x68004853, + 0x280006c0, 0xe7ffd401, 0xe027e7f8, 0x68004848, 0x280007c0, 0xe7ffd110, 0x21594845, 0x21166001, + 0x21886001, 0x68006001, 0x280007c0, 0xe7ffd103, 0x90192001, 0xe7ffe079, 0x6801483e, 0x43112204, + 0x483d6001, 0x43116801, 0xe7ff6001, 0x6800483b, 0x280006c0, 0xe7ffd401, 0xe7ffe7f8, 0x90134678, + 0x90129813, 0x78c0a812, 0x280006c0, 0xe7ffd52d, 0x90114678, 0x90109811, 0x00c09810, 0x4a354934, + 0x46082800, 0x92089109, 0xd4019007, 0x90079808, 0x68019807, 0x43112209, 0x46786001, 0x980f900f, + 0x980e900e, 0x280000c0, 0x92069809, 0xd4019005, 0x90059808, 0x68009805, 0x40089906, 0xd0032809, + 0x2001e7ff, 0xe0309019, 0x4678e02c, 0x980d900d, 0x980c900c, 0x491e00c0, 0x28004a1e, 0x91044608, + 0x90029203, 0x9803d401, 0x98029002, 0x22296801, 0x60014311, 0x900b4678, 0x900a980b, 0x00c0980a, + 0x98042800, 0x90009201, 0x9803d401, 0x98009000, 0x99016800, 0x28294008, 0xe7ffd003, 0x90192001, + 0xe7ffe003, 0x90192000, 0x9819e7ff, 0x4770b01a, 0x40000100, 0x40000200, 0x40000204, 0x40000250, + 0x50000100, 0x50000200, 0x50000204, 0x50000250, 0x5000c000, 0x4000c000, 0x9008b089, 0x4678e7ff, + 0x98079007, 0x98069006, 0x491200c0, 0x28004a12, 0x91029203, 0x9803d401, 0x98029002, 0x07c06800, + 0xd0012800, 0xe7eae7ff, 0x90054678, 0x90049805, 0x00c09804, 0x4a0a4909, 0x92012800, 0xd4019100, + 0x90009801, 0x68019800, 0x43912201, 0x20006001, 0x4770b009, 0x5000c040, 0x4000c040, 0x5000c000, + 0x4000c000, 0x902ab0ac, 0x2101982a, 0x4390070a, 0x982a902a, 0x40104a71, 0x982a902a, 0x0512220f, + 0x05494010, 0xd1074288, 0x982ae7ff, 0x1840496c, 0x2001902a, 0xe0029029, 0x90292000, 0xe7ffe7ff, + 0x90284678, 0x90279828, 0x00c09827, 0x4a664965, 0x92142800, 0xd4019113, 0x90139814, 0x68009813, + 0x280007c0, 0xe7ffd001, 0x4678e7ea, 0x98269026, 0x98259025, 0x495d00c0, 0x28004a5d, 0x91119212, + 0x9812d401, 0x98119011, 0x22406801, 0x60014311, 0x90244678, 0x90239824, 0x00c09823, 0x4a564955, + 0x92102800, 0xd401910f, 0x900f9810, 0x2122980f, 0x982a6001, 0x91224679, 0x91219922, 0x00c99921, + 0x4b4f4a4e, 0x900e2900, 0x920c930d, 0x980dd401, 0x980c900c, 0x6001990e, 0x28009829, 0xe7ffd113, + 0x90204678, 0x901f9820, 0x00c0981f, 0x4a464945, 0x920b2800, 0xd401910a, 0x900a980b, 0x2100980a, + 0x600143c9, 0x4678e011, 0x981e901e, 0x981d901d, 0x493c00c0, 0x28004a3c, 0x91089209, 0x9809d401, + 0x98089008, 0x60014939, 0x4678e7ff, 0x981c901c, 0x981b901b, 0x493600c0, 0x28004a36, 0x91069207, + 0x9807d401, 0x98069006, 0x60012101, 0x8f6ff3bf, 0x4678e7ff, 0x981a901a, 0x98199019, 0x492100c0, + 0x28004a21, 0x91049205, 0x9805d401, 0x98049004, 0x07c06800, 0xd0012800, 0xe7eae7ff, 0x90184678, + 0x90179818, 0x00c09817, 0x4a194918, 0x92032800, 0xd4019102, 0x90029803, 0x68009802, 0x28000640, + 0xe7ffd516, 0x90164678, 0x90159816, 0x00c09815, 0x4a0f490e, 0x92012800, 0xd4019100, 0x90009801, + 0x68019800, 0x43112240, 0x20016001, 0xe002902b, 0x902b2000, 0x982be7ff, 0x4770b02c, 0xfffff800, + 0xffe00000, 0x5000c040, 0x4000c040, 0x5000c000, 0x4000c000, 0x5000c00c, 0x4000c00c, 0x5000c004, + 0x4000c004, 0x5000c008, 0x4000c008, 0x0055aa03, 0x5000c010, 0x4000c010, 0x9028b0aa, 0x92269127, + 0x1cc09827, 0x43882103, 0x98289027, 0x07092101, 0x90284388, 0x4678e7ff, 0x98259025, 0x98249024, + 0x496100c0, 0x28004a61, 0x91129213, 0x9813d401, 0x98129012, 0x07c06800, 0xd0012800, 0xe7eae7ff, + 0x90234678, 0x90229823, 0x00c09822, 0x4a594958, 0x92112800, 0xd4019110, 0x90109811, 0x68019810, + 0x43112240, 0x46786001, 0x98219021, 0x98209020, 0x495100c0, 0x28004a51, 0x910e920f, 0x980fd401, + 0x980e900e, 0x60012121, 0x9827e7ff, 0xd1002800, 0x9828e083, 0x911f4679, 0x911e991f, 0x00c9991e, + 0x4b484a47, 0x900d2900, 0x920b930c, 0x980cd401, 0x980b900b, 0x6001990d, 0x68009826, 0x911d4679, + 0x911c991d, 0x00c9991c, 0x4b404a3f, 0x900a2900, 0x92089309, 0x9809d401, 0x98089008, 0x6001990a, + 0x901b4678, 0x901a981b, 0x00c0981a, 0x4a394938, 0x92072800, 0xd4019106, 0x90069807, 0x21019806, + 0xf3bf6001, 0xe7ff8f6f, 0x90194678, 0x90189819, 0x00c09818, 0x4a254924, 0x92052800, 0xd4019104, + 0x90049805, 0x68009804, 0x280007c0, 0xe7ffd001, 0x4678e7ea, 0x98179017, 0x98169016, 0x491c00c0, + 0x28004a1c, 0x91029203, 0x9803d401, 0x98029002, 0x06406800, 0xd5162800, 0x4678e7ff, 0x98159015, + 0x98149014, 0x491200c0, 0x28004a12, 0x91009201, 0x9801d401, 0x98009000, 0x22406801, 0x60014311, + 0x90292001, 0x9828e00c, 0x90281d00, 0x1d009826, 0x98279026, 0x90271f00, 0x2000e777, 0xe7ff9029, + 0xb02a9829, 0x46c04770, 0x5000c040, 0x4000c040, 0x5000c000, 0x4000c000, 0x5000c00c, 0x4000c00c, + 0x5000c004, 0x4000c004, 0x5000c008, 0x4000c008, 0x5000c010, 0x4000c010, 0x9028b0aa, 0x92269127, + 0x1cc09827, 0x43882103, 0x98289027, 0x07092101, 0x90254008, 0x43889828, 0xe7ff9028, 0x90244678, + 0x90239824, 0x00c09823, 0x4a634962, 0x92122800, 0xd4019111, 0x90119812, 0x68009811, 0x280007c0, + 0xe7ffd001, 0x4678e7ea, 0x98229022, 0x98219021, 0x495a00c0, 0x28004a5a, 0x910f9210, 0x9810d401, + 0x980f900f, 0x22406801, 0x60014311, 0x90204678, 0x901f9820, 0x00c0981f, 0x4a534952, 0x920e2800, + 0xd401910d, 0x900d980e, 0x2100980d, 0xe7ff6001, 0x28009827, 0xe087d100, 0x46799828, 0x991e911e, + 0x991d911d, 0x4a4900c9, 0x29004b49, 0x930b900c, 0xd401920a, 0x900a980b, 0x990c980a, 0x46786001, + 0x981c901c, 0x981b901b, 0x494200c0, 0x28004a42, 0x91089209, 0x9809d401, 0x98089008, 0x60012101, + 0x8f6ff3bf, 0x4678e7ff, 0x981a901a, 0x98199019, 0x493000c0, 0x28004a30, 0x91069207, 0x9807d401, + 0x98069006, 0x07c06800, 0xd0012800, 0xe7eae7ff, 0x90184678, 0x90179818, 0x00c09817, 0x4a284927, + 0x92052800, 0xd4019104, 0x90049805, 0x68009804, 0x28000640, 0xe7ffd516, 0x90164678, 0x90159816, + 0x00c09815, 0x4a1e491d, 0x92032800, 0xd4019102, 0x90029803, 0x68019802, 0x43112240, 0x20016001, + 0xe0249029, 0x90144678, 0x90139814, 0x00c09813, 0x4a1b491a, 0x92012800, 0xd4019100, 0x90009801, + 0x68009800, 0x68099926, 0xd0034288, 0x2001e7ff, 0xe00c9029, 0x1d009828, 0x98269028, 0x90261d00, + 0x1f009827, 0xe7739027, 0x90292000, 0x9829e7ff, 0x4770b02a, 0x5000c040, 0x4000c040, 0x5000c000, + 0x4000c000, 0x5000c00c, 0x4000c00c, 0x5000c004, 0x4000c004, 0x5000c010, 0x4000c010, 0x5000c008, + 0x4000c008, 0x00000000 +}; + +/** +* List of start and size for each size of flash sector - even indexes are start, odd are size +* The size will apply to all sectors between the listed address and the next address +* in the list. +* The last pair in the list will have sectors starting at that address and ending +* at address flash_start + flash_size. +*/ +static const sector_info_t sectors_info[] = { + { 0x00000000, 0x00000800 }, + { 0x00100000, 0x00000800 }, + { 0x00110000, 0x00000800 }, + { 0x10000000, 0x00000800 }, +}; + +#define M2354_PROGRAM_TARGET(LOAD_ADDRESS) { \ + LOAD_ADDRESS + 0x00000021, /* Init */ \ + LOAD_ADDRESS + 0x000001d9, /* UnInit */ \ + 0x0, /* EraseChip */ \ + LOAD_ADDRESS + 0x00000245, /* EraseSector */ \ + LOAD_ADDRESS + 0x00000459, /* ProgramPage */ \ + LOAD_ADDRESS + 0x00000639, /* Verify */ \ + \ + { \ + LOAD_ADDRESS + 0x00000001, /* BKPT : start of blob + 1 */ \ + LOAD_ADDRESS + 0x00000824, /* RSB : blob start + header + rw data offset */ \ + LOAD_ADDRESS + 0x00000b00 /* RSP : stack pointer */ \ + }, \ + \ + LOAD_ADDRESS + 0x00001000, /* mem buffer location */ \ + LOAD_ADDRESS, /* location to write prog_blob in target RAM */ \ + sizeof(M2354_flash_prog_blob), /* prog_blob size */ \ + M2354_flash_prog_blob, /* address of prog_blob */ \ + 0x00000800 /* ram_to_flash_bytes_to_be_written */ \ +} \ + +static const program_target_t M2354_flash = M2354_PROGRAM_TARGET(0x20000000); diff --git a/source/family/nuvoton/m2354kjfae/target.c b/source/family/nuvoton/m2354kjfae/target.c new file mode 100644 index 000000000..bafe17192 --- /dev/null +++ b/source/family/nuvoton/m2354kjfae/target.c @@ -0,0 +1,46 @@ +/** + * @file target.c + * @brief Target information for the m2354kjfae + * + * DAPLink Interface Firmware + * Copyright (c) 2021 Nuvoton Technology Corp. All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_config.h" +#include "flash_blob.c" + +// target information +target_cfg_t target_device = { + .sectors_info = sectors_info, + .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), + .flash_regions[0].start = 0x00000000, + .flash_regions[0].end = 0x00100000, + .flash_regions[0].flags = kRegionIsDefault, + .flash_regions[0].flash_algo = (program_target_t *)&M2354_flash, + .flash_regions[1].start = 0x10000000, + .flash_regions[1].end = 0x10000000 + 0x100000, + .flash_regions[1].flash_algo = (program_target_t *)&M2354_flash, + .flash_regions[2].start = 0x00100000, + .flash_regions[2].end = 0x00100000 + 0x4000, + .flash_regions[2].flash_algo = (program_target_t *)&M2354_flash, + .flash_regions[3].start = 0x00110000, + .flash_regions[3].end = 0x00110000 + 0x2000, + .flash_regions[3].flash_algo = (program_target_t *)&M2354_flash, + .ram_regions[0].start = 0x20000000, + .ram_regions[0].end = 0x20000000 + 0x40000, + .ram_regions[1].start = 0x30000000, + .ram_regions[1].end = 0x30000000 + 0x40000, +}; diff --git a/source/family/nuvoton/m2354kjfae/target_reset.c b/source/family/nuvoton/m2354kjfae/target_reset.c new file mode 100644 index 000000000..21fd23b31 --- /dev/null +++ b/source/family/nuvoton/m2354kjfae/target_reset.c @@ -0,0 +1,81 @@ +/** + * @file target_reset.c + * @brief Target reset for the m2354kjfae + * + * DAPLink Interface Firmware + * Copyright (c) 2021 Nuvoton Technology Corp. All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_family.h" +#include "target_config.h" +#include "swd_host.h" +#include "flash_blob.c" + +#define SCS_DHCSR 0xE000EDF0 +#define SCS_DHCSR_S_SDE 0x00100000 +#define SCU_SRAMNSSET 0x4002F024 + +static program_target_t flash; + +static uint8_t m2354_target_set_state(target_state_t state) +{ + uint32_t i, val, load_address; + + if (state == RESET_PROGRAM) { + if (!swd_set_target_state_sw(state)) { + return 0; + } + + if (!swd_read_word(SCS_DHCSR, &val)) { + return 0; + } + + if (val & SCS_DHCSR_S_SDE) { + load_address = 0x20000000; + } else { + if (!swd_read_word(0x10000000 + SCU_SRAMNSSET, &val)) { + return 0; + } + + for (i = 0; i < 15; i++) { + if (val & (1 << i)) { + break; + } + } + + load_address = 0x30000000 + (0x4000 * i); + } + + const program_target_t M2354_flash = M2354_PROGRAM_TARGET(load_address); + memcpy(&flash, &M2354_flash, sizeof(program_target_t)); + + for (i = 0; i < MAX_REGIONS; i++) { + if (target_device.flash_regions[i].start & 0x10000000) { + target_device.flash_regions[i].flash_algo = (program_target_t *)&flash; + } + } + + return 1; + } + + return swd_set_target_state_sw(state); +} + +const target_family_descriptor_t g_target_family_m2354 = { + .target_set_state = m2354_target_set_state, +}; + +const target_family_descriptor_t *g_target_family = &g_target_family_m2354; diff --git a/source/family/nuvoton/m252kg6ae/flash_blob.c b/source/family/nuvoton/m252kg6ae/flash_blob.c index 51bed444e..b7cae1135 100644 --- a/source/family/nuvoton/m252kg6ae/flash_blob.c +++ b/source/family/nuvoton/m252kg6ae/flash_blob.c @@ -1,5 +1,5 @@ /* Flash OS Routines (Automagically Generated) - * Copyright (c) 2009-2019 ARM Limited + * Copyright (c) 2019 Nuvoton Technology Corp * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/source/family/nuvoton/m252kg6ae/target.c b/source/family/nuvoton/m252kg6ae/target.c index 90b956474..69169ac31 100644 --- a/source/family/nuvoton/m252kg6ae/target.c +++ b/source/family/nuvoton/m252kg6ae/target.c @@ -3,7 +3,7 @@ * @brief Target information for the m252kg6ae * * DAPLink Interface Firmware - * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2019 Nuvoton Technology Corp. All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may diff --git a/source/family/nuvoton/m263kiaae/flash_blob.c b/source/family/nuvoton/m263kiaae/flash_blob.c index 28be351e4..a9bf13500 100644 --- a/source/family/nuvoton/m263kiaae/flash_blob.c +++ b/source/family/nuvoton/m263kiaae/flash_blob.c @@ -1,5 +1,5 @@ /* Flash OS Routines (Automagically Generated) - * Copyright (c) 2009-2019 ARM Limited + * Copyright (c) 2019 Nuvoton Technology Corp * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/source/family/nuvoton/m263kiaae/target.c b/source/family/nuvoton/m263kiaae/target.c index 1338d88d1..1d2ab73fa 100644 --- a/source/family/nuvoton/m263kiaae/target.c +++ b/source/family/nuvoton/m263kiaae/target.c @@ -3,7 +3,7 @@ * @brief Target information for the m263kiaae * * DAPLink Interface Firmware - * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2019 Nuvoton Technology Corp. All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may diff --git a/source/family/nuvoton/m487jidae/flash_blob.c b/source/family/nuvoton/m487jidae/flash_blob.c index 8279470c7..58d8d337c 100644 --- a/source/family/nuvoton/m487jidae/flash_blob.c +++ b/source/family/nuvoton/m487jidae/flash_blob.c @@ -1,5 +1,5 @@ /* Flash OS Routines (Automagically Generated) - * Copyright (c) 2009-2019 ARM Limited + * Copyright (c) 2020 Nuvoton Technology Corp * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/source/family/nuvoton/m487jidae/target.c b/source/family/nuvoton/m487jidae/target.c index f2e0356fa..860e9253f 100644 --- a/source/family/nuvoton/m487jidae/target.c +++ b/source/family/nuvoton/m487jidae/target.c @@ -3,7 +3,7 @@ * @brief Target information for the m487jidae * * DAPLink Interface Firmware - * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2020 Nuvoton Technology Corp. All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may diff --git a/test/info.py b/test/info.py index fff145849..48f801d3d 100644 --- a/test/info.py +++ b/test/info.py @@ -247,6 +247,7 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x1304, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_pfm_m487km_if', 'm48ssidae_bl', None ), ( 0x1309, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_m252kg_if', 'm48ssidae_bl', None ), ( 0x1310, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_iot_m263a_if', 'm48ssidae_bl', None ), + ( 0x1312, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_m2354_if', 'm48ssidae_bl', None ), ( 0x2201, VENDOR_TO_FAMILY('Wiznet', 1), 'lpc11u35_wizwiki_w7500_if', None, 'WIZwiki-W7500' ), ( 0x2202, VENDOR_TO_FAMILY('Wiznet', 1), 'lpc11u35_wizwiki_w7500_eco_if', None, 'WIZwiki-W7500ECO' ), ( 0x2203, VENDOR_TO_FAMILY('Wiznet', 1), 'lpc11u35_wizwiki_w7500p_if', None, 'WIZwiki-W7500P' ), @@ -368,6 +369,7 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y 0x1304, # NuMaker-PFM-M487KM 0x1309, # NuMaker-M252KG 0x1310, # NuMaker-IoT-M263A + 0x1312, # NuMaker-M2354 0x2410, # lpc11u35_mbed_cloud_connect_if 0x3103, # dipdap_sdt51822b 0x3104, # dipdap_sdt52832b From 448aec6b816e2c5126fef01a59fb6f97ef72628d Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sun, 6 Dec 2020 17:02:53 -0600 Subject: [PATCH 186/617] Remove admin config area in ROM. The admin config area was never used, and simply confuses the memory map. --- source/daplink/daplink.h | 2 -- source/daplink/info.c | 12 ------------ source/daplink/info.h | 1 - source/hic_hal/atmel/sam3u2c/daplink_addr.h | 5 +---- source/hic_hal/freescale/k20dx/daplink_addr.h | 5 +---- source/hic_hal/freescale/k26f/daplink_addr.h | 3 --- source/hic_hal/freescale/kl26z/daplink_addr.h | 5 +---- source/hic_hal/maxim/max32620/daplink_addr.h | 5 +---- source/hic_hal/maxim/max32625/daplink_addr.h | 3 --- source/hic_hal/nuvoton/m48ssidae/daplink_addr.h | 3 --- source/hic_hal/nxp/lpc11u35/daplink_addr.h | 3 --- source/hic_hal/nxp/lpc4322/daplink_addr.h | 3 --- source/hic_hal/stm32/stm32f103xb/daplink_addr.h | 3 --- 13 files changed, 4 insertions(+), 49 deletions(-) diff --git a/source/daplink/daplink.h b/source/daplink/daplink.h index daf330a0d..f73cc2a78 100644 --- a/source/daplink/daplink.h +++ b/source/daplink/daplink.h @@ -37,8 +37,6 @@ extern "C" { // ROM check COMPILER_ASSERT(DAPLINK_ROM_BL_START == DAPLINK_ROM_START); -COMPILER_ASSERT(DAPLINK_ROM_BL_START + DAPLINK_ROM_BL_SIZE == DAPLINK_ROM_CONFIG_ADMIN_START); -COMPILER_ASSERT(DAPLINK_ROM_CONFIG_ADMIN_START + DAPLINK_ROM_CONFIG_ADMIN_SIZE == DAPLINK_ROM_IF_START); COMPILER_ASSERT(DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE == DAPLINK_ROM_CONFIG_USER_START); COMPILER_ASSERT(DAPLINK_ROM_CONFIG_USER_START + DAPLINK_ROM_CONFIG_USER_SIZE == DAPLINK_ROM_START + DAPLINK_ROM_SIZE); diff --git a/source/daplink/info.c b/source/daplink/info.c index 5be10d8e7..05efa202c 100644 --- a/source/daplink/info.c +++ b/source/daplink/info.c @@ -46,7 +46,6 @@ static uint32_t hic_id = DAPLINK_HIC_ID; static uint32_t crc_bootloader; static uint32_t crc_interface; -static uint32_t crc_config_admin; static uint32_t crc_config_user; // Strings @@ -274,11 +273,6 @@ uint32_t info_get_crc_interface() return crc_interface; } -uint32_t info_get_crc_config_admin() -{ - return crc_config_admin; -} - uint32_t info_get_crc_config_user() { return crc_config_user; @@ -288,7 +282,6 @@ void info_crc_compute() { crc_bootloader = 0; crc_interface = 0; - crc_config_admin = 0; crc_config_user = 0; // Compute the CRCs of regions that exist @@ -302,11 +295,6 @@ void info_crc_compute() crc_interface = crc32((void *)DAPLINK_ROM_IF_START, DAPLINK_ROM_IF_SIZE - 4); } - if ((DAPLINK_ROM_CONFIG_ADMIN_SIZE > 0) - && flash_is_readable(DAPLINK_ROM_CONFIG_ADMIN_START, DAPLINK_ROM_CONFIG_ADMIN_SIZE)) { - crc_config_admin = crc32((void *)DAPLINK_ROM_CONFIG_ADMIN_START, DAPLINK_ROM_CONFIG_ADMIN_SIZE); - } - if ((DAPLINK_ROM_CONFIG_USER_SIZE > 0) && flash_is_readable(DAPLINK_ROM_CONFIG_USER_START, DAPLINK_ROM_CONFIG_USER_SIZE)) { crc_config_user = crc32((void *)DAPLINK_ROM_CONFIG_USER_START, DAPLINK_ROM_CONFIG_USER_SIZE); diff --git a/source/daplink/info.h b/source/daplink/info.h index 389725fa1..2250f84a7 100644 --- a/source/daplink/info.h +++ b/source/daplink/info.h @@ -78,7 +78,6 @@ bool info_get_config_user_present(void); // the given region is present. uint32_t info_get_crc_bootloader(void); uint32_t info_get_crc_interface(void); -uint32_t info_get_crc_config_admin(void); uint32_t info_get_crc_config_user(void); // Get version info as an integer diff --git a/source/hic_hal/atmel/sam3u2c/daplink_addr.h b/source/hic_hal/atmel/sam3u2c/daplink_addr.h index 3728821bf..216b5befe 100644 --- a/source/hic_hal/atmel/sam3u2c/daplink_addr.h +++ b/source/hic_hal/atmel/sam3u2c/daplink_addr.h @@ -1,6 +1,6 @@ /** * @file daplink_addr.h - * @brief + * @brief * * DAPLink Interface Firmware * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved @@ -35,9 +35,6 @@ #define DAPLINK_ROM_BL_START 0x00080000 #define DAPLINK_ROM_BL_SIZE 0x00008000 -#define DAPLINK_ROM_CONFIG_ADMIN_START 0x00088000 -#define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00000000 - #define DAPLINK_ROM_IF_START 0x00088000 #define DAPLINK_ROM_IF_SIZE 0x00017000 diff --git a/source/hic_hal/freescale/k20dx/daplink_addr.h b/source/hic_hal/freescale/k20dx/daplink_addr.h index 42947fba4..f51973990 100644 --- a/source/hic_hal/freescale/k20dx/daplink_addr.h +++ b/source/hic_hal/freescale/k20dx/daplink_addr.h @@ -1,6 +1,6 @@ /** * @file daplink_addr.h - * @brief + * @brief * * DAPLink Interface Firmware * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved @@ -35,9 +35,6 @@ #define DAPLINK_ROM_BL_START 0x00000000 #define DAPLINK_ROM_BL_SIZE 0x00008000 -#define DAPLINK_ROM_CONFIG_ADMIN_START 0x00008000 -#define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00000000 - #define DAPLINK_ROM_IF_START 0x00008000 #define DAPLINK_ROM_IF_SIZE 0x00017C00 diff --git a/source/hic_hal/freescale/k26f/daplink_addr.h b/source/hic_hal/freescale/k26f/daplink_addr.h index 0a7cb9009..df6b1c120 100644 --- a/source/hic_hal/freescale/k26f/daplink_addr.h +++ b/source/hic_hal/freescale/k26f/daplink_addr.h @@ -35,9 +35,6 @@ #define DAPLINK_ROM_BL_START 0x00000000 #define DAPLINK_ROM_BL_SIZE 0x00010000 // 64 kB bootloader -#define DAPLINK_ROM_CONFIG_ADMIN_START 0x00010000 -#define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00000000 - #define DAPLINK_ROM_IF_START 0x00010000 #define DAPLINK_ROM_IF_SIZE 0x0002f000 // 192 kB interface diff --git a/source/hic_hal/freescale/kl26z/daplink_addr.h b/source/hic_hal/freescale/kl26z/daplink_addr.h index 44fc73e91..96c7041c3 100644 --- a/source/hic_hal/freescale/kl26z/daplink_addr.h +++ b/source/hic_hal/freescale/kl26z/daplink_addr.h @@ -1,6 +1,6 @@ /** * @file daplink_addr.h - * @brief + * @brief * * DAPLink Interface Firmware * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved @@ -36,9 +36,6 @@ #define DAPLINK_ROM_BL_START 0x00000000 #define DAPLINK_ROM_BL_SIZE 0x00008000 -#define DAPLINK_ROM_CONFIG_ADMIN_START 0x00008000 -#define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00000000 - #define DAPLINK_ROM_IF_START 0x00008000 #define DAPLINK_ROM_IF_SIZE 0x00017C00 diff --git a/source/hic_hal/maxim/max32620/daplink_addr.h b/source/hic_hal/maxim/max32620/daplink_addr.h index 4fce86c03..b438a9bd6 100644 --- a/source/hic_hal/maxim/max32620/daplink_addr.h +++ b/source/hic_hal/maxim/max32620/daplink_addr.h @@ -1,6 +1,6 @@ /** * @file daplink_addr.h - * @brief + * @brief * * DAPLink Interface Firmware * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved @@ -35,9 +35,6 @@ #define DAPLINK_ROM_BL_START 0x00000000 #define DAPLINK_ROM_BL_SIZE 0x0000E000 -#define DAPLINK_ROM_CONFIG_ADMIN_START 0x0000E000 -#define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00002000 - #define DAPLINK_ROM_IF_START 0x00010000 #define DAPLINK_ROM_IF_SIZE 0x0006E000 diff --git a/source/hic_hal/maxim/max32625/daplink_addr.h b/source/hic_hal/maxim/max32625/daplink_addr.h index 3336f6bb9..e06f03f9d 100755 --- a/source/hic_hal/maxim/max32625/daplink_addr.h +++ b/source/hic_hal/maxim/max32625/daplink_addr.h @@ -35,9 +35,6 @@ #define DAPLINK_ROM_BL_START 0x00000000 #define DAPLINK_ROM_BL_SIZE 0x0000E000 -#define DAPLINK_ROM_CONFIG_ADMIN_START 0x0000E000 -#define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00002000 - #define DAPLINK_ROM_IF_START 0x00010000 #define DAPLINK_ROM_IF_SIZE 0x0006E000 diff --git a/source/hic_hal/nuvoton/m48ssidae/daplink_addr.h b/source/hic_hal/nuvoton/m48ssidae/daplink_addr.h index bb039ca01..221a2a762 100644 --- a/source/hic_hal/nuvoton/m48ssidae/daplink_addr.h +++ b/source/hic_hal/nuvoton/m48ssidae/daplink_addr.h @@ -37,9 +37,6 @@ #define DAPLINK_ROM_BL_START 0x00000000 #define DAPLINK_ROM_BL_SIZE KB(48) -#define DAPLINK_ROM_CONFIG_ADMIN_START 0x0000C000 -#define DAPLINK_ROM_CONFIG_ADMIN_SIZE KB(0) - #define DAPLINK_ROM_IF_START 0x0000C000 #define DAPLINK_ROM_IF_SIZE KB(204) diff --git a/source/hic_hal/nxp/lpc11u35/daplink_addr.h b/source/hic_hal/nxp/lpc11u35/daplink_addr.h index 6db79e769..2133ea3e7 100644 --- a/source/hic_hal/nxp/lpc11u35/daplink_addr.h +++ b/source/hic_hal/nxp/lpc11u35/daplink_addr.h @@ -38,9 +38,6 @@ #define DAPLINK_ROM_BL_START 0x00000000 #define DAPLINK_ROM_BL_SIZE 0x00000000 -#define DAPLINK_ROM_CONFIG_ADMIN_START 0x00000000 -#define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00000000 - #define DAPLINK_ROM_IF_START 0x00000000 #define DAPLINK_ROM_IF_SIZE 0x0000F000 diff --git a/source/hic_hal/nxp/lpc4322/daplink_addr.h b/source/hic_hal/nxp/lpc4322/daplink_addr.h index 107b3b2a9..d4d94fa3b 100644 --- a/source/hic_hal/nxp/lpc4322/daplink_addr.h +++ b/source/hic_hal/nxp/lpc4322/daplink_addr.h @@ -35,9 +35,6 @@ #define DAPLINK_ROM_BL_START 0x1A000000 #define DAPLINK_ROM_BL_SIZE 0x0000E000 -#define DAPLINK_ROM_CONFIG_ADMIN_START 0x1A00E000 -#define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00002000 - #define DAPLINK_ROM_IF_START 0x1A010000 #define DAPLINK_ROM_IF_SIZE 0x00020000 diff --git a/source/hic_hal/stm32/stm32f103xb/daplink_addr.h b/source/hic_hal/stm32/stm32f103xb/daplink_addr.h index 340f88423..74cc4dc55 100644 --- a/source/hic_hal/stm32/stm32f103xb/daplink_addr.h +++ b/source/hic_hal/stm32/stm32f103xb/daplink_addr.h @@ -35,9 +35,6 @@ #define DAPLINK_ROM_BL_START 0x08000000 #define DAPLINK_ROM_BL_SIZE 0x0000BC00 -#define DAPLINK_ROM_CONFIG_ADMIN_START 0x0800BC00 -#define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00000400 - #define DAPLINK_ROM_IF_START 0x0800C000 #define DAPLINK_ROM_IF_SIZE 0x00013C00 From e8768d12093c29dc45f3fc679e6f5950d2a0037c Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 8 Jun 2021 00:05:56 -0500 Subject: [PATCH 187/617] lpc11u35: fix invalid TDI and TDO pin ports This issue was raised in #502 --- source/board/override_96b_nitrogen/IO_Config_Override.h | 4 ++-- .../IO_Config_Override.h | 2 +- source/board/override_lpc11u35_reset/IO_Config_Override.h | 4 ++-- source/board/override_mtb/IO_Config_Override.h | 2 +- source/board/override_tiny/IO_Config_Override.h | 4 ++-- source/board/override_vbluno51/IO_Config_Override.h | 4 ++-- source/hic_hal/nxp/lpc11u35/IO_Config.h | 4 ++-- 7 files changed, 12 insertions(+), 12 deletions(-) diff --git a/source/board/override_96b_nitrogen/IO_Config_Override.h b/source/board/override_96b_nitrogen/IO_Config_Override.h index 07eaa918d..45c1fdcab 100644 --- a/source/board/override_96b_nitrogen/IO_Config_Override.h +++ b/source/board/override_96b_nitrogen/IO_Config_Override.h @@ -92,14 +92,14 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35); #define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) // TDI Pin PIO0_17 -#define PIN_TDI_PORT 17 +#define PIN_TDI_PORT 0 #define PIN_TDI_BIT 17 #define PIN_TDI (1 << PIN_TDI_BIT) #define PIN_TDI_IOCON LPC_IOCON->PIO0_17 #define PIN_TDI_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) // SWO/TDO Pin PIO0_9 -#define PIN_TDO_PORT 9 +#define PIN_TDO_PORT 0 #define PIN_TDO_BIT 9 #define PIN_TDO (1 << PIN_TDO_BIT) #define PIN_TDO_IOCON LPC_IOCON->PIO0_9 diff --git a/source/board/override_lpc11u35_6LoWPAN_BorderRouter/IO_Config_Override.h b/source/board/override_lpc11u35_6LoWPAN_BorderRouter/IO_Config_Override.h index 787436713..620de1a18 100644 --- a/source/board/override_lpc11u35_6LoWPAN_BorderRouter/IO_Config_Override.h +++ b/source/board/override_lpc11u35_6LoWPAN_BorderRouter/IO_Config_Override.h @@ -92,7 +92,7 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35); #define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) // TDI Pin PIO0_17 -#define PIN_TDI_PORT 17 +#define PIN_TDI_PORT 0 #define PIN_TDI_BIT 17 #define PIN_TDI (1 << PIN_TDI_BIT) #define PIN_TDI_IOCON LPC_IOCON->PIO0_17 diff --git a/source/board/override_lpc11u35_reset/IO_Config_Override.h b/source/board/override_lpc11u35_reset/IO_Config_Override.h index 1253a58fe..233675071 100644 --- a/source/board/override_lpc11u35_reset/IO_Config_Override.h +++ b/source/board/override_lpc11u35_reset/IO_Config_Override.h @@ -92,14 +92,14 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35); #define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) // TDI Pin PIO0_17 -#define PIN_TDI_PORT 17 +#define PIN_TDI_PORT 0 #define PIN_TDI_BIT 17 #define PIN_TDI (1 << PIN_TDI_BIT) #define PIN_TDI_IOCON LPC_IOCON->PIO0_17 #define PIN_TDI_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) // SWO/TDO Pin PIO0_9 -#define PIN_TDO_PORT 9 +#define PIN_TDO_PORT 0 #define PIN_TDO_BIT 9 #define PIN_TDO (1 << PIN_TDO_BIT) #define PIN_TDO_IOCON LPC_IOCON->PIO0_9 diff --git a/source/board/override_mtb/IO_Config_Override.h b/source/board/override_mtb/IO_Config_Override.h index 787436713..620de1a18 100644 --- a/source/board/override_mtb/IO_Config_Override.h +++ b/source/board/override_mtb/IO_Config_Override.h @@ -92,7 +92,7 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35); #define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) // TDI Pin PIO0_17 -#define PIN_TDI_PORT 17 +#define PIN_TDI_PORT 0 #define PIN_TDI_BIT 17 #define PIN_TDI (1 << PIN_TDI_BIT) #define PIN_TDI_IOCON LPC_IOCON->PIO0_17 diff --git a/source/board/override_tiny/IO_Config_Override.h b/source/board/override_tiny/IO_Config_Override.h index 148821d52..2b0b311af 100644 --- a/source/board/override_tiny/IO_Config_Override.h +++ b/source/board/override_tiny/IO_Config_Override.h @@ -92,14 +92,14 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35); #define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) // TDI Pin PIO0_17 -#define PIN_TDI_PORT 17 +#define PIN_TDI_PORT 0 #define PIN_TDI_BIT 17 #define PIN_TDI (1 << PIN_TDI_BIT) #define PIN_TDI_IOCON LPC_IOCON->PIO0_17 #define PIN_TDI_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) // SWO/TDO Pin PIO0_9 -#define PIN_TDO_PORT 9 +#define PIN_TDO_PORT 0 #define PIN_TDO_BIT 9 #define PIN_TDO (1 << PIN_TDO_BIT) #define PIN_TDO_IOCON LPC_IOCON->PIO0_9 diff --git a/source/board/override_vbluno51/IO_Config_Override.h b/source/board/override_vbluno51/IO_Config_Override.h index 2382a8793..44214d9a0 100644 --- a/source/board/override_vbluno51/IO_Config_Override.h +++ b/source/board/override_vbluno51/IO_Config_Override.h @@ -97,14 +97,14 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35); #define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) // TDI Pin PIO0_17 -#define PIN_TDI_PORT 17 +#define PIN_TDI_PORT 0 #define PIN_TDI_BIT 17 #define PIN_TDI (1 << PIN_TDI_BIT) #define PIN_TDI_IOCON LPC_IOCON->PIO0_17 #define PIN_TDI_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) // SWO/TDO Pin PIO0_9 -#define PIN_TDO_PORT 9 +#define PIN_TDO_PORT 0 #define PIN_TDO_BIT 9 #define PIN_TDO (1 << PIN_TDO_BIT) #define PIN_TDO_IOCON LPC_IOCON->PIO0_9 diff --git a/source/hic_hal/nxp/lpc11u35/IO_Config.h b/source/hic_hal/nxp/lpc11u35/IO_Config.h index 3acc7d6c6..c36fcffbb 100644 --- a/source/hic_hal/nxp/lpc11u35/IO_Config.h +++ b/source/hic_hal/nxp/lpc11u35/IO_Config.h @@ -102,14 +102,14 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35); #define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) // TDI Pin PIO0_17 -#define PIN_TDI_PORT 17 +#define PIN_TDI_PORT 0 #define PIN_TDI_BIT 17 #define PIN_TDI (1 << PIN_TDI_BIT) #define PIN_TDI_IOCON LPC_IOCON->PIO0_17 #define PIN_TDI_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) // SWO/TDO Pin PIO0_9 -#define PIN_TDO_PORT 9 +#define PIN_TDO_PORT 0 #define PIN_TDO_BIT 9 #define PIN_TDO (1 << PIN_TDO_BIT) #define PIN_TDO_IOCON LPC_IOCON->PIO0_9 From 2f12fb22883e310e2edaee2ab1b5ff6cefb47cbb Mon Sep 17 00:00:00 2001 From: "Sadik.Ozer" Date: Mon, 21 Sep 2020 12:47:28 +0300 Subject: [PATCH 188/617] Add MAX32665HSP board Signed-off-by: Sadik.Ozer --- projects.yaml | 4 + records/board/max32665hsp.yaml | 6 ++ source/board/max32665hsp.c | 47 ++++++++ source/family/maxim/max32665/flash_blob.c | 126 ++++++++++++++++++++++ source/family/maxim/max32665/target.c | 54 ++++++++++ test/info.py | 3 + 6 files changed, 240 insertions(+) create mode 100644 records/board/max32665hsp.yaml create mode 100644 source/board/max32665hsp.c create mode 100644 source/family/maxim/max32665/flash_blob.c create mode 100644 source/family/maxim/max32665/target.c diff --git a/projects.yaml b/projects.yaml index 58bf5889d..7367e1c8f 100644 --- a/projects.yaml +++ b/projects.yaml @@ -663,6 +663,10 @@ projects: - *module_if - *module_hic_max32625 - records/board/max32630fthr.yaml + max32625_max32665hsp_if: + - *module_if + - *module_hic_max32625 + - records/board/max32665hsp.yaml lpc11u35_wio_emw3166_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/max32665hsp.yaml b/records/board/max32665hsp.yaml new file mode 100644 index 000000000..3da81d492 --- /dev/null +++ b/records/board/max32665hsp.yaml @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/max32665hsp.c + family: + - source/family/maxim/max32665/target.c diff --git a/source/board/max32665hsp.c b/source/board/max32665hsp.c new file mode 100644 index 000000000..1417c9d7a --- /dev/null +++ b/source/board/max32665hsp.c @@ -0,0 +1,47 @@ +/** + * @file max32665hsp.c + * @brief board ID for the Maxim Integrated's MAX32665HSP + * + * DAPLink Interface Firmware + * + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* +*/ + +#include "target_family.h" +#include "target_board.h" + +const board_info_t g_board_info = { + .board_id = "0419", + .family_id = kStub_SWSysReset_FamilyID, + .flags = kEnablePageErase, + .target_cfg = &target_device, +}; diff --git a/source/family/maxim/max32665/flash_blob.c b/source/family/maxim/max32665/flash_blob.c new file mode 100644 index 000000000..5d81677a6 --- /dev/null +++ b/source/family/maxim/max32665/flash_blob.c @@ -0,0 +1,126 @@ +/** + * @file flash_blob.c + * @brief Flash algorithm for the MAX32665 + * + * DAPLink Interface Firmware + * + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* +*/ + +#include "flash_blob.h" + + +const uint32_t flash_algo_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x2400b5f8, 0x4605460e, 0x0f0ff010, 0xf06fbf1c, 0xbdf80002, 0x5080f1a5, 0xf5b049fe, 0xd30a2f00, + 0x2000f5a0, 0xf5b04afc, 0xd3102f00, 0x5084f1a5, 0x4f80f5b0, 0x460cd201, 0xf1a5e00a, 0xf5a05084, + 0xf5b04080, 0xbf284f80, 0x0002f06f, 0x4614d201, 0x28002000, 0xbdf8bf18, 0x46284669, 0xfa6af000, + 0xbfb82800, 0x68a0bdf8, 0x0f07f010, 0xf06fbf18, 0xd10e0005, 0xf0106a60, 0xd0030f02, 0xf0206a60, + 0x62610102, 0xf02068a0, 0xf0404070, 0x60a15100, 0x28002000, 0xbdf8bf18, 0xf02068a0, 0x60a00010, + 0x60209800, 0x63206830, 0x63606870, 0x63a068b0, 0x63e068f0, 0xf04068a0, 0x60a00001, 0xf01068a0, + 0xd1fb0f07, 0xf02068a0, 0x60a04070, 0xf0106a60, 0xd0060f02, 0xf0206a60, 0x62600002, 0x0006f06f, + 0xf04fbdf8, 0x68014080, 0x0140f041, 0x68016001, 0x0f40f011, 0x2004d1fb, 0x0110f105, 0xbf8842a9, + 0x0080eb05, 0x6829d90a, 0x42916832, 0xf06fd002, 0xbdf80006, 0x1d361d2d, 0xd8f442a8, 0xbdf82000, + 0x45f0e92d, 0xb0872600, 0x1e704603, 0x90059600, 0x960148ba, 0x96039602, 0x6802460f, 0x46314635, + 0x6f00f412, 0x6800bf07, 0x5f80f410, 0x0006f06f, 0xbf18b007, 0x85f0e8bd, 0x0f03f013, 0xf06fbf1e, + 0xb0070002, 0x85f0e8bd, 0x1d1c4618, 0x0c01f04f, 0x4284aa05, 0xeb00bf88, 0xd90b0c8c, 0xf8d26804, + 0x45448000, 0xf06fd002, 0xe0030106, 0x1d121d00, 0xd8f34584, 0xbf1c0008, 0xe8bdb007, 0xf00385f0, + 0xf023080f, 0xf1aa0a0f, 0x499a5080, 0x2f00f5b0, 0xf5a0d30a, 0x4a982000, 0x2f00f5b0, 0xf1aad310, + 0xf5b05084, 0xd2014f80, 0xe00a460d, 0x5084f1aa, 0x4080f5a0, 0x4f80f5b0, 0xf06fbf28, 0xd2010002, + 0x20004615, 0xbf1c2800, 0xe8bdb007, 0xa90485f0, 0xf0004650, 0x2800f99f, 0xb007bfbc, 0x85f0e8bd, + 0xf01068a8, 0xbf180f07, 0x0005f06f, 0x6a68d10e, 0x0f02f010, 0x6a68d003, 0x0102f020, 0x68a86269, + 0x4070f020, 0x5100f040, 0x200060a9, 0xbf1c2800, 0xe8bdb007, 0x465485f0, 0x0010f10a, 0xbf384582, + 0xd2064669, 0x2b04f854, 0x2026f841, 0x42841c76, 0x9804d3f8, 0xf1b86028, 0xbf380f04, 0xd3099700, + 0x0f08f1b8, 0x9701bf38, 0xf1b8d304, 0xbf340f0c, 0x97039702, 0x46504669, 0xfec2f7ff, 0xe8bdb007, + 0x200085f0, 0x4a644b63, 0xb148e00a, 0xbf0c2801, 0x21004611, 0xf0116889, 0xd0030f07, 0x47702001, + 0xe7f74619, 0x28021c40, 0x2000dbef, 0x20004770, 0x20014770, 0xb4104770, 0xf04f2100, 0x4c554280, + 0xc154f8df, 0xb151e00b, 0xbf0c2901, 0x20004660, 0xf0136883, 0xd0040f07, 0x2001bc10, 0x46204770, + 0x6a43e7f6, 0x0f02f013, 0x6a43d003, 0x0302f023, 0x68836243, 0x4370f023, 0x5300f043, 0x68836083, + 0x437ff423, 0x432af443, 0x68836083, 0x0302f043, 0x68836083, 0x0f07f013, 0x6883d1fb, 0x4370f023, + 0x6a436083, 0x0f02f013, 0x6a41d006, 0x0102f021, 0xbc106241, 0x47702001, 0xf0406810, 0x60100040, + 0xf0106810, 0xd1fb0f40, 0x29021c49, 0xbc10dbbb, 0x47702000, 0xf1a0b5f8, 0x4e2e5180, 0x46024d2e, + 0x2f00f5b1, 0x4634d201, 0xf1a0e007, 0xf5a15180, 0xf5b12100, 0xd20b2f00, 0x4669462c, 0xf0004610, + 0x2800f8d9, 0x68a0bf04, 0x0f07f010, 0xe00dd10c, 0x5184f1a0, 0x4f80f5b1, 0xf1a2d3e5, 0xf5a05084, + 0xf5b04080, 0xd3e74f80, 0xbdf82001, 0xf0106a60, 0xd0030f02, 0xf0206a60, 0x62610102, 0xf02068a0, + 0xf0404070, 0x60a15100, 0xf42068a0, 0xf440407f, 0x60a040aa, 0x60209800, 0xf04068a0, 0x60a00004, + 0xe0202000, 0x2801b1f8, 0x4629bf0c, 0x68892100, 0x0f07f011, 0x1c40d1f4, 0xdbf32802, 0xf02068a0, + 0x60a04070, 0xf0106a60, 0xd00e0f02, 0xf0206a60, 0xe0050002, 0x40029000, 0x40029400, 0x40006c00, + 0x20016260, 0x4631bdf8, 0xf04fe7e1, 0x68014080, 0x0140f041, 0x68016001, 0x0f40f011, 0x2000d1fb, + 0xe92dbdf8, 0x461645f8, 0x4605460c, 0xf010466f, 0xd0270f03, 0x0003f025, 0x0a03f005, 0x0804f1ca, + 0x90006800, 0x0004f1c8, 0x46424438, 0xf0004631, 0xeba5f88c, 0x9900000a, 0xfe52f7ff, 0xbf182800, + 0x85f8e8bd, 0xeba44445, 0x44460408, 0x4628e00a, 0xf7ff6831, 0x2800fe45, 0xe8bdbf18, 0x1f2485f8, + 0x1d361d2d, 0xd3022c04, 0x0f0ff015, 0x2c10d1ef, 0x4631d30c, 0xf7ff4628, 0x2800fda3, 0xe8bdbf18, + 0x3c1085f8, 0x36103510, 0xd2f22c10, 0xd30c2c04, 0x68314628, 0xfe24f7ff, 0xbf182800, 0x85f8e8bd, + 0x1d2d1f24, 0x2c041d36, 0xb174d2f2, 0x90006828, 0x46314622, 0xf0004668, 0x4628f848, 0xf7ff6839, + 0x2800fe0f, 0xe8bdbf18, 0x200085f8, 0x85f8e8bd, 0xeb000889, 0x42810181, 0x6803d90a, 0xc000f8d2, + 0xd0014563, 0x47702001, 0x1d121d00, 0xd8f44281, 0x47702000, 0x5280f1a0, 0x2f00f5b2, 0xf3c0bf3c, + 0x60080012, 0xf1a0d31f, 0xf5a25280, 0xf5b22200, 0xbf3c2f00, 0x2000f5a0, 0x0012f3c0, 0xf1a0d312, + 0xf5b25284, 0xd3094f80, 0x4280f5a2, 0x4f80f5b2, 0xf5a0bf32, 0xf06f4080, 0x47700002, 0x000df3c0, + 0x2000f500, 0x20006008, 0xea404770, 0x079b0301, 0xe009d003, 0x1f12c908, 0x2a04c008, 0xe003d2fa, + 0x3b01f811, 0x3b01f800, 0xd2f91e52, 0x00004770, 0x00000000 +}; + +/** +* List of start and size for each size of flash sector +* The size will apply to all sectors between the listed address and the next address +* in the list. +* The last pair in the list will have sectors starting at that address and ending +* at address start + size. +*/ +static const sector_info_t sectors_info[] = { + {0x10000000, 0x2000}, + }; + +const program_target_t flash = { + 0x200002a3, // Init + 0x200002cf, // UnInit + 0x200002d7, // EraseChip + 0x20000375, // EraseSector + 0x20000463, // ProgramPage + 0x20000531, // Verify + + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + { + 0x20000001, + 0x200005d0, + 0x20000800 + }, + + 0x20000000 + 0x00000A00, // program_buffer + 0x20000000, // algo_start + sizeof(flash_algo_blob), // algo_size + flash_algo_blob, // image + + 0x00002000 // ram_to_flash_bytes_to_be_written +}; diff --git a/source/family/maxim/max32665/target.c b/source/family/maxim/max32665/target.c new file mode 100644 index 000000000..8d6dfe34d --- /dev/null +++ b/source/family/maxim/max32665/target.c @@ -0,0 +1,54 @@ +/** + * @file target.c + * @brief Target information for the MAX32665 + * + * DAPLink Interface Firmware + * + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* +*/ + +#include "target_config.h" + +#include "flash_blob.c" + +/* ME14 -- MAX32665 1MiB Flash, 560KiB RAM */ +target_cfg_t target_device = { + .sectors_info = sectors_info, + .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), + .flash_regions[0].start = 0x10000000, + .flash_regions[0].end = 0x10100000, + .flash_regions[0].flags = kRegionIsDefault, + .flash_regions[0].flash_algo = (program_target_t *) &flash, + .ram_regions[0].start = 0x20000000, + .ram_regions[0].end = 0x2008C000, +}; + diff --git a/test/info.py b/test/info.py index 48f801d3d..c64d43ce7 100644 --- a/test/info.py +++ b/test/info.py @@ -130,6 +130,7 @@ ('max32620_max32625mbed_if', False, 0x0000, "bin" ), ('max32625_max32620fthr_if', False, 0x0000, "bin" ), ('max32625_max32630fthr_if', False, 0x0000, "bin" ), + ('max32625_max32665hsp_if', False, 0x0000, "bin" ), ('kl26z_if', False, 0x0000, "bin" ), ('k20dx_if', False, 0x0000, "bin" ), ('k26f_if', False, 0x0000, "bin" ), @@ -191,6 +192,7 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0350, VENDOR_TO_FAMILY('Stub', 1), 'k20dx_xdot_l151_if', 'k20dx_bl', None ), # TODO - set target to 'MTS-xDot-L151CC' when mbed-os supports this ( 0x0360, VENDOR_TO_FAMILY('NXP', 1), 'lpc4322_hani_iot_if', 'lpc4322_bl', 'HANI-IOT' ), ( 0x0409, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32630fthr_if', 'max32625_bl', 'MAX32630' ), + ( 0x0419, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32665hsp_if', 'max32625_bl', 'MAX32665' ), ( 0x0415, VENDOR_TO_FAMILY('Stub', 1), 'max32620_max32625mbed_if', 'max32620_bl', 'MAX32625' ), ( 0x0418, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32620fthr_if', 'max32625_bl', 'MAX32620' ), ( 0x0450, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_ublox_odin_w2_if', None, None ), @@ -358,6 +360,7 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y 0x0409, # MAX32630FTHR 0x0415, # MAX32625MBED 0x0418, # MAX32620FTHR + 0x0419, # MAX32665HSP 0x0450, # mtb_ublox_odin_w2 0x0456, # lpc11u35_mtb_murata_abz_078_if 0x0457, # lpc11u35_mtb_rak811_if From 583f7e40cf265eafbbc4a533ff18e56b91661677 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 9 Jun 2021 10:59:12 -0500 Subject: [PATCH 189/617] Update YAML release files to match new gh-pages scripts --- tools/make_update_yml.py | 174 --------------------------------- tools/package_release_files.py | 115 ++++++++++++++++++---- tools/update_yml.py | 93 ------------------ 3 files changed, 98 insertions(+), 284 deletions(-) delete mode 100644 tools/make_update_yml.py mode change 100755 => 100644 tools/package_release_files.py delete mode 100755 tools/update_yml.py diff --git a/tools/make_update_yml.py b/tools/make_update_yml.py deleted file mode 100644 index bbc2e93a1..000000000 --- a/tools/make_update_yml.py +++ /dev/null @@ -1,174 +0,0 @@ -#!/usr/bin/env python -# -# DAPLink Interface Firmware -# Copyright (c) 2009-2018, ARM Limited, All Rights Reserved -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); you may -# not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# - -import logging - -logger = logging.getLogger('yaml gen') - -class DefaultList(list): - def sort(self, *args, **kwargs): - pass - -class TargetList(list): - def sort(self, *args, **kwargs): - pass - -class InstructionList(list): - def sort(self, *args, **kwargs): - pass - - -#instruction steps for firmware -InstructionsText = { - 'default':InstructionList([ - ('windows', [ - '1. Download the firmware file.', - '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate and mount as `BOOTLOADER` or `MAINTENANCE`. For boards that enumerate as `BOOTLOADER` [see our blog to determine if an update for the DAPLink bootloader is available.](https://os.mbed.com/blog/entry/DAPLink-bootloader-update/)', - '3. Drag-and-drop the firmware file onto the mounted drive.', - '4. Wait for the file copy operation to complete.', - '5. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.' - ]), - ('osx', [ - '1. Download the firmware file.', - '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate as `BOOTLOADER` or `MAINTENANCE`. For boards that enumerate as `BOOTLOADER` [see our blog to determine if an update for the DAPLink bootloader is available.](https://os.mbed.com/blog/entry/DAPLink-bootloader-update/)', - '3. In a terminal execute', - ' - `sudo mount -u -w -o sync /Volumes/MAINTENANCE ; cp -X /Volumes/MAINTENANCE/`', - ' - Note: If your drive does not mount as `MAINTENANCE` make sure to change this to match the name of the mounted disk attached to your system.', - '4. Wait for the file copy operation to complete.', - '5. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.' - ]), - ('linux', [ - '1. Download the firmware file.', - '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate as `BOOTLOADER` or `MAINTENANCE`. For boards that enumerate as `BOOTLOADER` [see our blog to determine if an update for the DAPLink bootloader is available.](https://os.mbed.com/blog/entry/DAPLink-bootloader-update/)', - '3. In a terminal execute', - ' - `cp && sync`', - ' - Note: make sure to change `MAINTENANCE` to the name of the mount point of the drive on your system.', - '4. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.' - ]) - ]), - 'lpc11u35':InstructionList([ - ('windows', [ - '1. Download the firmware file.', - '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate and mount as `CRP DISABLD`', - '3. Delete the file named `firmware.bin`, then drag and drop or copy the new bin file', - '4. Wait for the file copy operation to complete.', - '5. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.' - ]), - ('osx', [ - '1. Download the firmware file.', - '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate and mount as `CRP DISABLD`', - '3. Delete the file named `firmware.bin`', - '4. In a terminal execute', - ' - `sudo mount -u -w -o sync /Volumes/CRP\ DISABLD ; rm /Volumes/CRP\ DISABLD/firmware.bin && cp -X /Volumes/CRP\ DISABLD/`', - '5. Wait for the file copy operation to complete.', - '6. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.' - ]), - ('linux', [ - '1. Download the firmware file.', - '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate and mount as `CRP DISABLD`', - '3. Delete the file named `firmware.bin`', - '4. In a terminal execute', - ' - `cp && sync`', - ' - Note: make sure to change `CRP DISABLD` to the name of the mount point on your system.', - '5. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.' - ]) - ]) - -} - - -def string_writer(element): - if type(element) is str: - return element - elif type(element) is int: - return "_0x%04i" % element - else: - return None - - -def yml_object_parser(f, entry, level, tabs): - header = " " * level * tabs - if type(entry) is list: - for element in entry: - yml_object_parser(f, element, level, tabs); - - elif type(entry) is dict: - for key in entry: - f.write('-' + ' ' * (level * tabs -1) + string_writer(key) + ": "); - value = string_writer(entry[key]) - if value is not None: - f.write(value) - f.write('\n') - else: - f.write('\n') - yml_object_parser(f, entry[key], level + 1, tabs); - - - elif type(entry) is DefaultList: - for target in entry: - if type(target) is tuple: - #print target - f.write(" " * level * tabs + string_writer(target[0]) + ": "); - value = string_writer(target[1]) - if value is not None: - f.write(value) - f.write('\n') - else: - f.write('\n') - yml_object_parser(f, target[1], level + 1, tabs); - else: - logger.error("Not expecting input type %s %s " % (type(target), str(target))) - - elif type(entry) is TargetList: - #print "found TargetList" - for target in entry: - if type(target) is tuple: - #print target - f.write(" " * (level-1) * tabs + string_writer(target[0]) + ": "); - value = string_writer(target[1]) - if value is not None: - f.write(value) - f.write('\n') - else: - f.write('\n') - yml_object_parser(f, target[1], level, tabs); - else: - logger.error("Not expecting input type %s %s " % (type(target), str(target))) - - elif type(entry) is InstructionList: - #print "found InstructionList" - for target in entry: - if type(target) is tuple: - f.write(" " * level * tabs + string_writer(target[0]) + ": |\n") - if type(target[1]) is list: - for texts in target[1]: - f.write(" " * (level + 1) * tabs + string_writer(texts) + "\n") - else: - logger.error("Not expecting input type %s %s " % (type(target[1]), str(target[1]))) - else: - logger.error("Not expecting input type %s %s " % (type(target), str(target))) - else: - logger.error("Not expecting input type %s %s " % (type(entry), str(entry))) - - -def make_update_yml_file(file_loc, entries, explicit_start=False, tab=2): - with open(file_loc, "w") as yml_file: - if explicit_start is True: - yml_file.write("---\n") - yml_object_parser(yml_file, entries, 1, tab); diff --git a/tools/package_release_files.py b/tools/package_release_files.py old mode 100755 new mode 100644 index 7365de0aa..2b3630e2b --- a/tools/package_release_files.py +++ b/tools/package_release_files.py @@ -24,7 +24,76 @@ import yaml import subprocess import zipfile -from make_update_yml import DefaultList, TargetList, InstructionsText, make_update_yml_file +from collections import OrderedDict + +class literal(str): + pass + +def literal_presenter(dumper, data): + return dumper.represent_scalar('tag:yaml.org,2002:str', data, style='|') + +yaml.add_representer(literal, literal_presenter) + +def ordered_dict_presenter(dumper, data): + return dumper.represent_dict(data.items()) +yaml.add_representer(OrderedDict, ordered_dict_presenter) + +instructions = { + 'default': OrderedDict( + windows=literal("\n".join([ + '1. Download the firmware file.', + '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate and mount as `BOOTLOADER` or `MAINTENANCE`. For boards that enumerate as `BOOTLOADER` [see our blog to determine if an update for the DAPLink bootloader is available.](https://os.mbed.com/blog/entry/DAPLink-bootloader-update/)', + '3. Drag-and-drop the firmware file onto the mounted drive.', + '4. Wait for the file copy operation to complete.', + '5. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.' + ])), + osx=literal("\n".join([ + '1. Download the firmware file.', + '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate as `BOOTLOADER` or `MAINTENANCE`. For boards that enumerate as `BOOTLOADER` [see our blog to determine if an update for the DAPLink bootloader is available.](https://os.mbed.com/blog/entry/DAPLink-bootloader-update/)', + '3. In a terminal execute', + ' - `sudo mount -u -w -o sync /Volumes/MAINTENANCE ; cp -X /Volumes/MAINTENANCE/`', + ' - Note: If your drive does not mount as `MAINTENANCE` make sure to change this to match the name of the mounted disk attached to your system.', + '4. Wait for the file copy operation to complete.', + '5. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.' + ])), + linux=literal("\n".join([ + '1. Download the firmware file.', + '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate as `BOOTLOADER` or `MAINTENANCE`. For boards that enumerate as `BOOTLOADER` [see our blog to determine if an update for the DAPLink bootloader is available.](https://os.mbed.com/blog/entry/DAPLink-bootloader-update/)', + '3. In a terminal execute', + ' - `cp && sync`', + ' - Note: make sure to change `MAINTENANCE` to the name of the mount point of the drive on your system.', + '4. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.' + ])) + ), + 'lpc11u35': { + 'windows': literal("\n".join([ + '1. Download the firmware file.', + '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate and mount as `CRP DISABLD`', + '3. Delete the file named `firmware.bin`, then drag and drop or copy the new bin file', + '4. Wait for the file copy operation to complete.', + '5. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.' + ])), + 'osx': literal("\n".join([ + '1. Download the firmware file.', + '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate and mount as `CRP DISABLD`', + '3. Delete the file named `firmware.bin`', + '4. In a terminal execute', + ' - `sudo mount -u -w -o sync /Volumes/CRP\ DISABLD ; rm /Volumes/CRP\ DISABLD/firmware.bin && cp -X /Volumes/CRP\ DISABLD/`', + '5. Wait for the file copy operation to complete.', + '6. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.' + ])), + 'linux': literal("\n".join([ + '1. Download the firmware file.', + '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate and mount as `CRP DISABLD`', + '3. Delete the file named `firmware.bin`', + '4. In a terminal execute', + ' - `cp && sync`', + ' - Note: make sure to change `CRP DISABLD` to the name of the mount point on your system.', + '5. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.' + ])) + } +} + def make_bin_zip(dir, name): working_dir = os.getcwd() @@ -41,12 +110,14 @@ def package_release_files(source, dest, version, toolchain, release_info, suppor output_dir = dest build_number = "%04i" % version - update_yml_entries = [{'default':DefaultList([ - ('website', 'http://os.mbed.com/platforms'), - ('fw_version', "'" + build_number + "'"), - ('image_format', '.bin'), - ('instructions', InstructionsText['default']) - ]) }] + update_yml_entries = { + 'default': OrderedDict( + website='http://os.mbed.com/platforms', + fw_version=build_number, + image_format='.bin', + instructions=instructions), + 'targets': {} + } if os.path.exists(output_dir): shutil.rmtree(output_dir) @@ -83,25 +154,35 @@ def package_release_files(source, dest, version, toolchain, release_info, suppor if target is not None: target_name = target else: + # Skip bare interface firmwares + if len(base_name) == 0: + continue target_name = base_name.upper() - fw_instuction = InstructionsText['default'] - for fw_name_key in InstructionsText: + fw_instuction = 'default' + for fw_name_key in instructions: if fw_name_key in dest_name.lower(): - fw_instuction = InstructionsText[fw_name_key] + fw_instuction = fw_name_key break if extension == 'bin': - update_yml_entries.append({target_name:TargetList([ - ('name', target_name), - ('product_code', "'" + format(product_code, '04x') + "'"), - ('fw_name', host_mcu + "_" + base_name + dest_offset_str), - ('instructions', fw_instuction) - ])}) + update_yml_entries['targets'][target_name] = OrderedDict( + name=target_name, + product_code=format(product_code, '04x'), + fw_name=host_mcu + "_" + base_name + dest_offset_str, + instructions=fw_instuction + ) make_bin_zip(output_dir, build_number + '_release_package_' + subprocess.check_output(['git', 'rev-parse', '--short', 'HEAD']).decode().strip() + '.zip') + print("Writing %s" % (os.path.join(output_dir, 'default.yml'))) + with open(os.path.join(output_dir, 'default.yml'), "w") as yml_file: + yml_file.write("---\n") + yml_file.write(yaml.dump(update_yml_entries['default'])) + print("Writing %s" % (os.path.join(output_dir, 'targets.yml'))) + with open(os.path.join(output_dir, 'targets.yml'), "w") as yml_file: + yml_file.write("---\n") + yml_file.write(yaml.dump(update_yml_entries['targets'])) - make_update_yml_file(os.path.join(output_dir, 'update.yml'), update_yml_entries, explicit_start=True) if __name__ == "__main__": self_path = os.path.abspath(__file__) diff --git a/tools/update_yml.py b/tools/update_yml.py deleted file mode 100755 index eea220ef8..000000000 --- a/tools/update_yml.py +++ /dev/null @@ -1,93 +0,0 @@ -#!/usr/bin/env python -# -# DAPLink Interface Firmware -# Copyright (c) 2009-2018, ARM Limited, All Rights Reserved -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); you may -# not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# - -import yaml - -#classes needed to generate update.yml files -class TargetList(list): - def sort(self, *args, **kwargs): - pass - -class InstructionList(unicode): - def sort(self, *args, **kwargs): - pass - -#Remove the sorting by default -yaml.add_representer(TargetList, yaml.representer.SafeRepresenter.represent_dict) -#needed block style for the instruction steps -yaml.add_representer(InstructionList, lambda dumper, data: dumper.represent_scalar(u'tag:yaml.org,2002:str', data, style='|') ) - - -#instruction steps for firmware -InstructionsText = { - 'default':TargetList([ - ('windows', InstructionList( - '1. Download the firmware file.\n' - '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate and mount as `BOOTLOADER` or `MAINTENANCE`. For boards that enumerate as `BOOTLOADER` [see our blog to determine if an update for the DAPLink bootloader is available.](https://os.mbed.com/blog/entry/DAPLink-bootloader-update/)\n' - '3. Drag-and-drop the firmware file onto the mounted drive.\n' - '4. Wait for the file copy operation to complete.\n' - '5. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.\n' - )), - ('osx', InstructionList( - '1. Download the firmware file.\n' - '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate as `BOOTLOADER` or `MAINTENANCE`. For boards that enumerate as `BOOTLOADER` [see our blog to determine if an update for the DAPLink bootloader is available.](https://os.mbed.com/blog/entry/DAPLink-bootloader-update/)\n' - '3. In a terminal execute\n' - ' - `sudo mount -u -w -o sync /Volumes/MAINTENANCE ; cp -X /Volumes/MAINTENANCE/`\n' - ' - Note: If your drive does not mount as `MAINTENANCE` make sure to change this to match the name of the mounted disk attached to your system.\n' - '4. Wait for the file copy operation to complete.\n' - '5. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.\n' - )), - ('linux', InstructionList( - '1. Download the firmware file.\n' - '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate as `BOOTLOADER` or `MAINTENANCE`. For boards that enumerate as `BOOTLOADER` [see our blog to determine if an update for the DAPLink bootloader is available.](https://os.mbed.com/blog/entry/DAPLink-bootloader-update/)\n' - '3. In a terminal execute\n' - ' - `cp && sync`\n' - ' - Note: make sure to change `MAINTENANCE` to the name of the mount point of the drive on your system.\n' - '4. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.\n' - )) - ]), - 'lpc11u35':TargetList([ - ('windows', InstructionList( - '1. Download the firmware file.\n' - '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate and mount as `CRP DISABLD`\n' - '3. Delete the file named `firmware.bin`\n' - '4. Wait for the file copy operation to complete.\n' - '5. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.\n' - )), - ('osx', InstructionList( - '1. Download the firmware file.\n' - '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate and mount as `CRP DISABLD`\n' - '3. Delete the file named `firmware.bin`' - '4. In a terminal execute\n' - ' - `sudo mount -u -w -o sync /Volumes/CRP\ DISABLD ; rm /Volumes/CRP\ DISABLD/firmware.bin && cp -X /Volumes/CRP\ DISABLD/`\n' - '5. Wait for the file copy operation to complete.\n' - '6. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.\n' - )), - ('linux', InstructionList( - '1. Download the firmware file.\n' - '2. While holding down the boards reset button, connect the boards USB debug port to the computer. It should enumerate and mount as `CRP DISABLD`\n' - '3. Delete the file named `firmware.bin`\n' - '4. In a terminal execute\n' - ' - `cp && sync`\n' - ' - Note: make sure to change `CRP DISABLD` to the name of the mount point on your system.\n' - '5. Power cycle the board. It will now enumerate and mount as `DAPLINK` or the name of the board.\n' - )) - ]) - -} From 037d27fb5f577c9bbf12f1401070dc2a115baf6e Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 9 Jun 2021 18:25:07 -0500 Subject: [PATCH 190/617] Enable GitHub Actions on the new 'develop' branch --- .github/workflows/linux.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/linux.yml b/.github/workflows/linux.yml index 1f8c1b5a1..f73a8fe13 100644 --- a/.github/workflows/linux.yml +++ b/.github/workflows/linux.yml @@ -2,7 +2,7 @@ name: Build DAPLink (Linux) on: push: branches: - - experimental_compilers + - develop workflow_dispatch: jobs: From ad7c2c00a3c0c7925a5af1462ff1ec184af27aed Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 9 Jun 2021 18:34:19 -0500 Subject: [PATCH 191/617] Update branch name in README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index e6572d542..22d06e3b0 100644 --- a/README.md +++ b/README.md @@ -95,7 +95,7 @@ The following command combines generation and compilation: [![DAPLink](/docs/images/daplink-website-logo-link.png)](https://armmbed.github.io/DAPLink/) **Note:** The master branch requires an Arm Compiler 5 or Keil MDK license to build. See the -[experimental_compilers](https://github.com/ARMmbed/DAPLink/tree/experimental_compilers) branch for gcc and Arm +[develop](https://github.com/ARMmbed/DAPLink/tree/develop) branch for gcc and Arm Compiler 6 support. As soon as testing is complete, gcc will become the default compiler and AC5 support will be dropped. From 71c2ad1e64811cd5f0cb481ab5e8d280b19f6f9f Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 9 Jun 2021 18:41:19 -0500 Subject: [PATCH 192/617] Update branch name in README.md --- README.md | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/README.md b/README.md index 22d06e3b0..cd828ce67 100644 --- a/README.md +++ b/README.md @@ -1,9 +1,8 @@ -# Warning: Experimental branch +# Warning: Development branch -This is is an experimental branch: -- It adds support for the GCC (`gcc_arm`) and ARMC6 (`armclang`) compilers. +This is is a development branch: +- It adds support for the GCC (`gcc_arm`) and ARMC6 (`armclang`) compilers, ARMC5 (`armcc`) will be deprecated. - It focuses on `progen` support using `make` and `cmake`. -- It will be frequently rebased. ## Setup @@ -27,7 +26,7 @@ Get the sources and create a virtual environment ``` $ git clone https://github.com/ARMmbed/DAPLink $ cd DAPLink -$ git checkout experimental_compilers +$ git checkout develop $ virtualenv venv ``` From 737c8c91db4b0807ee1fc3b7b4df8282dc42b843 Mon Sep 17 00:00:00 2001 From: Yasuhiro ISHII <822772+yishii@users.noreply.github.com> Date: Thu, 22 Nov 2018 18:56:25 +0900 Subject: [PATCH 193/617] Modify PIN_nRESET_IN for PIN_nRESET_FET_DRIVE. --- source/hic_hal/nxp/lpc11u35/DAP_config.h | 31 ++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/source/hic_hal/nxp/lpc11u35/DAP_config.h b/source/hic_hal/nxp/lpc11u35/DAP_config.h index 69a14f160..6b3e0a162 100644 --- a/source/hic_hal/nxp/lpc11u35/DAP_config.h +++ b/source/hic_hal/nxp/lpc11u35/DAP_config.h @@ -45,6 +45,11 @@ Provides definitions about: #define CONF_JTAG #endif +// Configure SWD option by default +#if !defined(CONF_JTAG) && !defined(CONF_SWD) +#define CONF_SWD +#endif + /// Processor Clock of the Cortex-M MCU used in the Debug Unit. /// This value is used to calculate the SWD/JTAG clock speed. #define CPU_CLOCK 48000000 ///< Specifies the CPU Clock in Hz @@ -59,7 +64,11 @@ Provides definitions about: /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. /// This information is returned by the command \ref DAP_Info as part of Capabilities. +#if defined(CONF_SWD) #define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available +#else +#define DAP_SWD 0 ///< SWD Mode: 1 = available, 0 = not available +#endif /// Indicate that JTAG communication mode is available at the Debug Port. /// This information is returned by the command \ref DAP_Info as part of Capabilities. @@ -75,7 +84,11 @@ Provides definitions about: /// Default communication mode on the Debug Access Port. /// Used for the command \ref DAP_Connect when Port Default mode is selected. +#if (DAP_SWD != 0) #define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG. +#else +#define DAP_DEFAULT_PORT 2 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG. +#endif /// Default communication speed on the Debug Access Port for SWD and JTAG mode. /// Used to initialize the default SWD/JTAG clock frequency. @@ -173,6 +186,20 @@ Configures the DAP Hardware I/O pins for JTAG mode: __STATIC_INLINE void PORT_JTAG_SETUP(void) { #if (DAP_JTAG != 0) + LPC_GPIO->SET[PIN_SWCLK_PORT] = PIN_SWCLK; + LPC_GPIO->SET[PIN_SWDIO_PORT] = PIN_SWDIO; +#if !defined(PIN_nRESET_FET_DRIVE) + // open drain logic + LPC_GPIO->DIR[PIN_nRESET_PORT] &= ~PIN_nRESET; + LPC_GPIO->CLR[PIN_nRESET_PORT] = PIN_nRESET; +#else + // FET drive logic + LPC_GPIO->DIR[PIN_nRESET_PORT] |= PIN_nRESET; + LPC_GPIO->CLR[PIN_nRESET_PORT] = PIN_nRESET; +#endif + LPC_GPIO->DIR[PIN_SWCLK_PORT] |= PIN_SWCLK; + LPC_GPIO->DIR[PIN_SWDIO_PORT] |= PIN_SWDIO; + LPC_GPIO->SET[PIN_TDI_PORT] = PIN_TDI; LPC_GPIO->DIR[PIN_TDI_PORT] |= PIN_TDI; LPC_GPIO->DIR[PIN_TDO_PORT] &= ~PIN_TDO; @@ -392,7 +419,11 @@ __STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit) */ __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void) { +#if !defined(PIN_nRESET_FET_DRIVE) return LPC_GPIO->B[PIN_nRESET_BIT + PIN_nRESET_PORT * 32] & 0x1; +#else + return (LPC_GPIO->B[PIN_nRESET_BIT + PIN_nRESET_PORT * 32] & 0x1) == 1 ? 0 : 1; +#endif } /** nRESET I/O pin: Set Output. From 1342597fc1e82e8edf38d4ce35b77e4ad6bb69aa Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Thu, 17 Jun 2021 23:07:37 +0900 Subject: [PATCH 194/617] add comments --- source/hic_hal/nxp/lpc11u35/DAP_config.h | 40 ++++++++++++++---------- 1 file changed, 23 insertions(+), 17 deletions(-) diff --git a/source/hic_hal/nxp/lpc11u35/DAP_config.h b/source/hic_hal/nxp/lpc11u35/DAP_config.h index 6b3e0a162..71526202a 100644 --- a/source/hic_hal/nxp/lpc11u35/DAP_config.h +++ b/source/hic_hal/nxp/lpc11u35/DAP_config.h @@ -42,12 +42,7 @@ Provides definitions about: // Configure JTAG option #if defined(BOARD_BAMBINO_210) || defined(BOARD_BAMBINO_210E) // LPC43xx multicore targets require JTAG to debug slave cores -#define CONF_JTAG -#endif - -// Configure SWD option by default -#if !defined(CONF_JTAG) && !defined(CONF_SWD) -#define CONF_SWD +#define DAP_JTAG 1 #endif /// Processor Clock of the Cortex-M MCU used in the Debug Unit. @@ -64,18 +59,14 @@ Provides definitions about: /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. /// This information is returned by the command \ref DAP_Info as part of Capabilities. -#if defined(CONF_SWD) +#ifndef DAP_SWD #define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available -#else -#define DAP_SWD 0 ///< SWD Mode: 1 = available, 0 = not available #endif /// Indicate that JTAG communication mode is available at the Debug Port. /// This information is returned by the command \ref DAP_Info as part of Capabilities. -#if defined(CONF_JTAG) -#define DAP_JTAG 1 ///< JTAG Mode: 1 = available -#else -#define DAP_JTAG 0 ///< JTAG Mode: 0 = not available +#ifndef DAP_JTAG +#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available #endif /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port. @@ -84,10 +75,12 @@ Provides definitions about: /// Default communication mode on the Debug Access Port. /// Used for the command \ref DAP_Connect when Port Default mode is selected. -#if (DAP_SWD != 0) +#if (DAP_SWD == 1) #define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG. -#else +#elif (DAP_JTAG == 1) #define DAP_DEFAULT_PORT 2 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG. +#else +#error Must enable DAP_SWD and/or DAP_JTAG #endif /// Default communication speed on the Debug Access Port for SWD and JTAG mode. @@ -189,15 +182,23 @@ __STATIC_INLINE void PORT_JTAG_SETUP(void) LPC_GPIO->SET[PIN_SWCLK_PORT] = PIN_SWCLK; LPC_GPIO->SET[PIN_SWDIO_PORT] = PIN_SWDIO; #if !defined(PIN_nRESET_FET_DRIVE) - // open drain logic + /* Open drain logic (for ordinary board). + * nRESET line should be pulled up by the board. + * To output high level (reset release signal), + * set as input direction. */ LPC_GPIO->DIR[PIN_nRESET_PORT] &= ~PIN_nRESET; LPC_GPIO->CLR[PIN_nRESET_PORT] = PIN_nRESET; #else - // FET drive logic + /* FET drive logic (for special board like as blueninja) + * This setting treats nRESET line as positive logic. + * High level indicates that reset signal is asserted. + * Low level indicates that reset signal is deasserted. */ LPC_GPIO->DIR[PIN_nRESET_PORT] |= PIN_nRESET; LPC_GPIO->CLR[PIN_nRESET_PORT] = PIN_nRESET; #endif + // SWCLK and TCK are aliases for the same line. LPC_GPIO->DIR[PIN_SWCLK_PORT] |= PIN_SWCLK; + // SWDIO and TMS are aliases for the same line. LPC_GPIO->DIR[PIN_SWDIO_PORT] |= PIN_SWDIO; LPC_GPIO->SET[PIN_TDI_PORT] = PIN_TDI; @@ -420,8 +421,13 @@ __STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit) __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void) { #if !defined(PIN_nRESET_FET_DRIVE) + // open drain logic return LPC_GPIO->B[PIN_nRESET_BIT + PIN_nRESET_PORT * 32] & 0x1; #else + /* FET drive logic (for special board like as blueninja) + * This setting treats nRESET line as positive logic. + * High level indicates that reset signal is asserted. + * Low level indicates that reset signal is deasserted. */ return (LPC_GPIO->B[PIN_nRESET_BIT + PIN_nRESET_PORT * 32] & 0x1) == 1 ? 0 : 1; #endif } From 9a80c38bfc371d6941b984663ade60a2b5c5f64d Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 16 Jul 2021 04:58:27 -0500 Subject: [PATCH 195/617] g_board_info missing in some startup files + consistency/comment fixes --- source/hic_hal/atmel/sam3u2c/armcc/startup_SAM3U.s | 2 +- .../hic_hal/freescale/k26f/armcc/startup_MK26F18.s | 10 +++++----- .../hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s | 12 ++++++------ source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S | 10 +++++----- .../hic_hal/maxim/max32620/armcc/startup_MAX32620.S | 2 +- .../hic_hal/nuvoton/m48ssidae/armcc/startup_M480.s | 4 ++-- source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s | 6 +++--- 7 files changed, 23 insertions(+), 23 deletions(-) diff --git a/source/hic_hal/atmel/sam3u2c/armcc/startup_SAM3U.s b/source/hic_hal/atmel/sam3u2c/armcc/startup_SAM3U.s index 077762c99..e30116e57 100644 --- a/source/hic_hal/atmel/sam3u2c/armcc/startup_SAM3U.s +++ b/source/hic_hal/atmel/sam3u2c/armcc/startup_SAM3U.s @@ -63,7 +63,7 @@ __Vectors DCD __initial_sp ; 0: Top of Stack DCD 0 ; 7: Reserved DCD DAPLINK_BUILD_KEY ; 8: Build type - BL/IF DCD DAPLINK_HIC_ID ; 9: Compatibility - DCD DAPLINK_VERSION ; 10:Version + DCD DAPLINK_VERSION ; 10: Version DCD SVC_Handler ; 11: SVCall Handler DCD DebugMon_Handler ; 12: Debug Monitor Handler DCD g_board_info ; 13: Ptr to Board info, family info other target details diff --git a/source/hic_hal/freescale/k26f/armcc/startup_MK26F18.s b/source/hic_hal/freescale/k26f/armcc/startup_MK26F18.s index 1777a5e22..d056601ab 100644 --- a/source/hic_hal/freescale/k26f/armcc/startup_MK26F18.s +++ b/source/hic_hal/freescale/k26f/armcc/startup_MK26F18.s @@ -73,7 +73,7 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size - + IMPORT g_board_info __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ;NMI Handler @@ -82,12 +82,12 @@ __Vectors DCD __initial_sp ; Top of Stack DCD BusFault_Handler ;Bus Fault Handler DCD UsageFault_Handler ;Usage Fault Handler DCD 0 ;Reserved - DCD DAPLINK_BUILD_KEY ; Build type - BL/IF - DCD DAPLINK_HIC_ID ; Compatibility - DCD DAPLINK_VERSION ; Version + DCD DAPLINK_BUILD_KEY ;Build type - BL/IF + DCD DAPLINK_HIC_ID ;Compatibility + DCD DAPLINK_VERSION ;Version DCD SVC_Handler ;SVCall Handler DCD DebugMon_Handler ;Debug Monitor Handler - DCD 0 ;Reserved + DCD g_board_info ;Ptr to Board info, family info other target details DCD PendSV_Handler ;PendSV Handler DCD SysTick_Handler ;SysTick Handler diff --git a/source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s b/source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s index e6d2eaea1..d4f013eab 100644 --- a/source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s +++ b/source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s @@ -72,20 +72,20 @@ __heap_limit EXPORT __Vectors_End EXPORT __Vectors_Size IMPORT g_board_info -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler +__Vectors DCD __initial_sp ;Top of Stack + DCD Reset_Handler ;Reset Handler DCD NMI_Handler ;NMI Handler DCD HardFault_Handler ;Hard Fault Handler DCD 0 ;Reserved DCD 0 ;Reserved DCD 0 ;Reserved DCD 0 ;Reserved - DCD DAPLINK_BUILD_KEY ; Build type - BL/IF - DCD DAPLINK_HIC_ID ; Compatibility - DCD DAPLINK_VERSION ; Version + DCD DAPLINK_BUILD_KEY ;Build type - BL/IF + DCD DAPLINK_HIC_ID ;Compatibility + DCD DAPLINK_VERSION ;Version DCD SVC_Handler ;SVCall Handler DCD 0 ;Reserved - DCD g_board_info ; Ptr to Board info, family info other target details + DCD g_board_info ;Ptr to Board info, family info other target details DCD PendSV_Handler ;PendSV Handler DCD SysTick_Handler ;SysTick Handler diff --git a/source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S b/source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S index 10059050d..03ddf2576 100644 --- a/source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S +++ b/source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S @@ -21,8 +21,8 @@ .section .isr_vector, "a" .align 2 - .globl __Vectors -__Vectors: + .globl __isr_vector +__isr_vector: .long __StackTop /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* NMI Handler*/ @@ -36,7 +36,7 @@ __Vectors: .long DAPLINK_VERSION /* Version*/ .long SVC_Handler /* SVCall Handler*/ .long 0 /* Reserved*/ - .long 0 /* Reserved*/ + .long g_board_info /* Ptr to Board info, family info other target details*/ .long PendSV_Handler /* PendSV Handler*/ .long SysTick_Handler /* SysTick Handler*/ @@ -74,7 +74,7 @@ __Vectors: .long PORTA_IRQHandler /* PORTA Pin detect*/ .long PORTC_PORTD_IRQHandler /* Single interrupt vector for PORTC; PORTD Pin detect*/ - .size __Vectors, . - __Vectors + .size __isr_vector, . - __isr_vector /* Flash Configuration */ .section .FlashConfig, "a" @@ -97,7 +97,7 @@ Reset_Handler: cpsid i /* Mask interrupts */ .equ VTOR, 0xE000ED08 ldr r0, =VTOR - ldr r1, =__Vectors + ldr r1, =__isr_vector str r1, [r0] ldr r2, [r1] msr msp, r2 diff --git a/source/hic_hal/maxim/max32620/armcc/startup_MAX32620.S b/source/hic_hal/maxim/max32620/armcc/startup_MAX32620.S index 376ae36ed..7f2277fcc 100644 --- a/source/hic_hal/maxim/max32620/armcc/startup_MAX32620.S +++ b/source/hic_hal/maxim/max32620/armcc/startup_MAX32620.S @@ -62,7 +62,7 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size - IMPORT g_board_info + IMPORT g_board_info __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler diff --git a/source/hic_hal/nuvoton/m48ssidae/armcc/startup_M480.s b/source/hic_hal/nuvoton/m48ssidae/armcc/startup_M480.s index c3c44243d..3cd352d5e 100644 --- a/source/hic_hal/nuvoton/m48ssidae/armcc/startup_M480.s +++ b/source/hic_hal/nuvoton/m48ssidae/armcc/startup_M480.s @@ -69,7 +69,7 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size - + IMPORT g_board_info __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler @@ -83,7 +83,7 @@ __Vectors DCD __initial_sp ; Top of Stack DCD DAPLINK_VERSION ; Version DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved + DCD g_board_info ; Ptr to Board info, family info other target details DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler diff --git a/source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s b/source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s index 67fee7f16..488aa1091 100644 --- a/source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s +++ b/source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s @@ -61,9 +61,9 @@ __Vectors DCD __initial_sp ; 0 Top of Stack DCD BusFault_Handler ; 5 Bus Fault Handler DCD UsageFault_Handler ; 6 Usage Fault Handler DCD Sign_Value ; 7 Reserved - DCD DAPLINK_BUILD_KEY ; Build type - BL/IF - DCD DAPLINK_HIC_ID ; Compatibility - DCD DAPLINK_VERSION ; Version + DCD DAPLINK_BUILD_KEY ; 8 Build type - BL/IF + DCD DAPLINK_HIC_ID ; 9 Compatibility + DCD DAPLINK_VERSION ; 10 Version DCD SVC_Handler ; 11 SVCall Handler DCD DebugMon_Handler ; 12 Debug Monitor Handler DCD g_board_info ; 13 Ptr to Board info, family info other target details From f47a55b0b8764525623c856c3eb25212bb126a35 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 16 Jul 2021 04:59:15 -0500 Subject: [PATCH 196/617] Highlight DAPLink-specific changes in startup files --- source/hic_hal/atmel/sam3u2c/armcc/startup_SAM3U.s | 8 ++++---- source/hic_hal/atmel/sam3u2c/gcc/startup_SAM3U.S | 8 ++++---- source/hic_hal/freescale/k20dx/armcc/startup_MK20D5.s | 8 ++++---- source/hic_hal/freescale/k20dx/gcc/startup_MK20D5.S | 8 ++++---- source/hic_hal/freescale/k26f/armcc/startup_MK26F18.s | 8 ++++---- source/hic_hal/freescale/k26f/gcc/startup_MK26F18.S | 8 ++++---- source/hic_hal/freescale/kl26z/armcc/startup_MKL26Z4.s | 8 ++++---- source/hic_hal/freescale/kl26z/gcc/startup_MKL26Z4.S | 8 ++++---- source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s | 8 ++++---- source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S | 8 ++++---- source/hic_hal/maxim/max32620/armcc/startup_MAX32620.S | 8 ++++---- source/hic_hal/maxim/max32620/gcc/startup_MAX32620.S | 8 ++++---- source/hic_hal/maxim/max32625/armcc/startup_max32625.S | 8 ++++---- source/hic_hal/maxim/max32625/gcc/startup_max32625.S | 8 ++++---- source/hic_hal/nuvoton/m48ssidae/armcc/startup_M480.s | 8 ++++---- source/hic_hal/nuvoton/m48ssidae/gcc/startup_M480.S | 8 ++++---- source/hic_hal/nxp/lpc11u35/armcc/startup_LPC11Uxx.s | 8 ++++---- source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11Uxx.S | 8 ++++---- source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s | 8 ++++---- source/hic_hal/nxp/lpc4322/gcc/startup_LPC43xx.S | 8 ++++---- .../hic_hal/nxp/lpc55xx/gcc/startup_LPC55S69_cm33_core0.S | 8 ++++---- .../hic_hal/stm32/stm32f103xb/armcc/startup_stm32f103xb.S | 8 ++++---- .../hic_hal/stm32/stm32f103xb/gcc/startup_stm32f103xb.S | 8 ++++---- 23 files changed, 92 insertions(+), 92 deletions(-) diff --git a/source/hic_hal/atmel/sam3u2c/armcc/startup_SAM3U.s b/source/hic_hal/atmel/sam3u2c/armcc/startup_SAM3U.s index e30116e57..e29bb302d 100644 --- a/source/hic_hal/atmel/sam3u2c/armcc/startup_SAM3U.s +++ b/source/hic_hal/atmel/sam3u2c/armcc/startup_SAM3U.s @@ -61,12 +61,12 @@ __Vectors DCD __initial_sp ; 0: Top of Stack DCD BusFault_Handler ; 5: Bus Fault Handler DCD UsageFault_Handler ; 6: Usage Fault Handler DCD 0 ; 7: Reserved - DCD DAPLINK_BUILD_KEY ; 8: Build type - BL/IF - DCD DAPLINK_HIC_ID ; 9: Compatibility - DCD DAPLINK_VERSION ; 10: Version + DCD DAPLINK_BUILD_KEY ; 8: DAPLINK: Build type (BL/IF) + DCD DAPLINK_HIC_ID ; 9: DAPLINK: Compatibility + DCD DAPLINK_VERSION ; 10: DAPLINK: Version DCD SVC_Handler ; 11: SVCall Handler DCD DebugMon_Handler ; 12: Debug Monitor Handler - DCD g_board_info ; 13: Ptr to Board info, family info other target details + DCD g_board_info ; 13: DAPLINK: Pointer to board/family/target info DCD PendSV_Handler ; 14: PendSV Handler DCD SysTick_Handler ; 15: SysTick Handler diff --git a/source/hic_hal/atmel/sam3u2c/gcc/startup_SAM3U.S b/source/hic_hal/atmel/sam3u2c/gcc/startup_SAM3U.S index 54afeb91a..c2f482118 100644 --- a/source/hic_hal/atmel/sam3u2c/gcc/startup_SAM3U.S +++ b/source/hic_hal/atmel/sam3u2c/gcc/startup_SAM3U.S @@ -38,12 +38,12 @@ __isr_vector: .long BusFault_Handler /* Bus Fault Handler*/ .long UsageFault_Handler /* Usage Fault Handler*/ .long 0 /* Reserved*/ - .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ - .long DAPLINK_HIC_ID /* Compatibility*/ - .long DAPLINK_VERSION /* Version*/ + .long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF)*/ + .long DAPLINK_HIC_ID /* DAPLINK: Compatibility*/ + .long DAPLINK_VERSION /* DAPLINK: Version*/ .long SVC_Handler /* SVCall Handler*/ .long DebugMon_Handler /* Debug Monitor Handler*/ - .long g_board_info /* Ptr to Board info, family info other target details*/ + .long g_board_info /* DAPLINK: Pointer to board/family/target info*/ .long PendSV_Handler /* PendSV Handler*/ .long SysTick_Handler /* SysTick Handler*/ diff --git a/source/hic_hal/freescale/k20dx/armcc/startup_MK20D5.s b/source/hic_hal/freescale/k20dx/armcc/startup_MK20D5.s index d90300254..02ce501cf 100644 --- a/source/hic_hal/freescale/k20dx/armcc/startup_MK20D5.s +++ b/source/hic_hal/freescale/k20dx/armcc/startup_MK20D5.s @@ -61,12 +61,12 @@ __Vectors DCD __initial_sp ; Top of Stack DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved - DCD DAPLINK_BUILD_KEY ; Build type - BL/IF - DCD DAPLINK_HIC_ID ; Compatibility - DCD DAPLINK_VERSION ; Version + DCD DAPLINK_BUILD_KEY ; DAPLINK: Build type (BL/IF) + DCD DAPLINK_HIC_ID ; DAPLINK: Compatibility + DCD DAPLINK_VERSION ; DAPLINK: Version DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler - DCD g_board_info ; Ptr to Board info, family info other target details + DCD g_board_info ; DAPLINK: Pointer to board/family/target info DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler diff --git a/source/hic_hal/freescale/k20dx/gcc/startup_MK20D5.S b/source/hic_hal/freescale/k20dx/gcc/startup_MK20D5.S index cbf89d9f0..1320335ec 100644 --- a/source/hic_hal/freescale/k20dx/gcc/startup_MK20D5.S +++ b/source/hic_hal/freescale/k20dx/gcc/startup_MK20D5.S @@ -38,12 +38,12 @@ __isr_vector: .long BusFault_Handler /* Bus Fault Handler*/ .long UsageFault_Handler /* Usage Fault Handler*/ .long 0 /* Reserved*/ - .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ - .long DAPLINK_HIC_ID /* Compatibility*/ - .long DAPLINK_VERSION /* Version*/ + .long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF)*/ + .long DAPLINK_HIC_ID /* DAPLINK: Compatibility*/ + .long DAPLINK_VERSION /* DAPLINK: Version*/ .long SVC_Handler /* SVCall Handler*/ .long DebugMon_Handler /* Debug Monitor Handler*/ - .long g_board_info /* Ptr to Board info, family info other target details*/ + .long g_board_info /* DAPLINK: Pointer to board/family/target info*/ .long PendSV_Handler /* PendSV Handler*/ .long SysTick_Handler /* SysTick Handler*/ diff --git a/source/hic_hal/freescale/k26f/armcc/startup_MK26F18.s b/source/hic_hal/freescale/k26f/armcc/startup_MK26F18.s index d056601ab..cf0b7b849 100644 --- a/source/hic_hal/freescale/k26f/armcc/startup_MK26F18.s +++ b/source/hic_hal/freescale/k26f/armcc/startup_MK26F18.s @@ -82,12 +82,12 @@ __Vectors DCD __initial_sp ; Top of Stack DCD BusFault_Handler ;Bus Fault Handler DCD UsageFault_Handler ;Usage Fault Handler DCD 0 ;Reserved - DCD DAPLINK_BUILD_KEY ;Build type - BL/IF - DCD DAPLINK_HIC_ID ;Compatibility - DCD DAPLINK_VERSION ;Version + DCD DAPLINK_BUILD_KEY ;DAPLINK: Build type (BL/IF) + DCD DAPLINK_HIC_ID ;DAPLINK: Compatibility + DCD DAPLINK_VERSION ;DAPLINK: Version DCD SVC_Handler ;SVCall Handler DCD DebugMon_Handler ;Debug Monitor Handler - DCD g_board_info ;Ptr to Board info, family info other target details + DCD g_board_info ;DAPLINK: Pointer to board/family/target info DCD PendSV_Handler ;PendSV Handler DCD SysTick_Handler ;SysTick Handler diff --git a/source/hic_hal/freescale/k26f/gcc/startup_MK26F18.S b/source/hic_hal/freescale/k26f/gcc/startup_MK26F18.S index d3cca0fc9..6021323b3 100644 --- a/source/hic_hal/freescale/k26f/gcc/startup_MK26F18.S +++ b/source/hic_hal/freescale/k26f/gcc/startup_MK26F18.S @@ -29,12 +29,12 @@ __isr_vector: .long BusFault_Handler /* Bus Fault Handler*/ .long UsageFault_Handler /* Usage Fault Handler*/ .long 0 /* Reserved*/ - .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ - .long DAPLINK_HIC_ID /* Compatibility*/ - .long DAPLINK_VERSION /* Version*/ + .long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF)*/ + .long DAPLINK_HIC_ID /* DAPLINK: Compatibility*/ + .long DAPLINK_VERSION /* DAPLINK: Version*/ .long SVC_Handler /* SVCall Handler*/ .long DebugMon_Handler /* Debug Monitor Handler*/ - .long g_board_info /* Ptr to Board info, family info other target details*/ + .long g_board_info /* DAPLINK: Pointer to board/family/target info*/ .long PendSV_Handler /* PendSV Handler*/ .long SysTick_Handler /* SysTick Handler*/ diff --git a/source/hic_hal/freescale/kl26z/armcc/startup_MKL26Z4.s b/source/hic_hal/freescale/kl26z/armcc/startup_MKL26Z4.s index 7ca0dc0fd..764805f42 100644 --- a/source/hic_hal/freescale/kl26z/armcc/startup_MKL26Z4.s +++ b/source/hic_hal/freescale/kl26z/armcc/startup_MKL26Z4.s @@ -59,12 +59,12 @@ __Vectors DCD __initial_sp ; Top of Stack DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved - DCD DAPLINK_BUILD_KEY ; Build type - BL/IF - DCD DAPLINK_HIC_ID ; Compatibility - DCD DAPLINK_VERSION ; Version + DCD DAPLINK_BUILD_KEY ; DAPLINK: Build type (BL/IF) + DCD DAPLINK_HIC_ID ; DAPLINK: Compatibility + DCD DAPLINK_VERSION ; DAPLINK: Version DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved - DCD g_board_info ; Ptr to Board info, family info other target details + DCD g_board_info ; DAPLINK: Pointer to board/family/target info DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler diff --git a/source/hic_hal/freescale/kl26z/gcc/startup_MKL26Z4.S b/source/hic_hal/freescale/kl26z/gcc/startup_MKL26Z4.S index 1cac80a0d..59aab8f42 100644 --- a/source/hic_hal/freescale/kl26z/gcc/startup_MKL26Z4.S +++ b/source/hic_hal/freescale/kl26z/gcc/startup_MKL26Z4.S @@ -56,12 +56,12 @@ __isr_vector: .long 0 /* Reserved*/ .long 0 /* Reserved*/ .long 0 /* Reserved*/ - .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ - .long DAPLINK_HIC_ID /* Compatibility*/ - .long DAPLINK_VERSION /* Version*/ + .long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF)*/ + .long DAPLINK_HIC_ID /* DAPLINK: Compatibility*/ + .long DAPLINK_VERSION /* DAPLINK: Version*/ .long SVC_Handler /* SVCall Handler*/ .long 0 /* Reserved*/ - .long g_board_info /* Ptr to Board info, family info other target details*/ + .long g_board_info /* DAPLINK: Pointer to board/family/target info*/ .long PendSV_Handler /* PendSV Handler*/ .long SysTick_Handler /* SysTick Handler*/ diff --git a/source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s b/source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s index d4f013eab..06f59c896 100644 --- a/source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s +++ b/source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s @@ -80,12 +80,12 @@ __Vectors DCD __initial_sp ;Top of Stack DCD 0 ;Reserved DCD 0 ;Reserved DCD 0 ;Reserved - DCD DAPLINK_BUILD_KEY ;Build type - BL/IF - DCD DAPLINK_HIC_ID ;Compatibility - DCD DAPLINK_VERSION ;Version + DCD DAPLINK_BUILD_KEY ;DAPLINK: Build type (BL/IF) + DCD DAPLINK_HIC_ID ;DAPLINK: Compatibility + DCD DAPLINK_VERSION ;DAPLINK: Version DCD SVC_Handler ;SVCall Handler DCD 0 ;Reserved - DCD g_board_info ;Ptr to Board info, family info other target details + DCD g_board_info ;DAPLINK: Pointer to board/family/target info DCD PendSV_Handler ;PendSV Handler DCD SysTick_Handler ;SysTick Handler diff --git a/source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S b/source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S index 03ddf2576..b22302ae6 100644 --- a/source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S +++ b/source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S @@ -31,12 +31,12 @@ __isr_vector: .long 0 /* Reserved*/ .long 0 /* Reserved*/ .long 0 /* Reserved*/ - .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ - .long DAPLINK_HIC_ID /* Compatibility*/ - .long DAPLINK_VERSION /* Version*/ + .long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF)*/ + .long DAPLINK_HIC_ID /* DAPLINK: Compatibility*/ + .long DAPLINK_VERSION /* DAPLINK: Version*/ .long SVC_Handler /* SVCall Handler*/ .long 0 /* Reserved*/ - .long g_board_info /* Ptr to Board info, family info other target details*/ + .long g_board_info /* DAPLINK: Pointer to board/family/target info*/ .long PendSV_Handler /* PendSV Handler*/ .long SysTick_Handler /* SysTick Handler*/ diff --git a/source/hic_hal/maxim/max32620/armcc/startup_MAX32620.S b/source/hic_hal/maxim/max32620/armcc/startup_MAX32620.S index 7f2277fcc..681579515 100644 --- a/source/hic_hal/maxim/max32620/armcc/startup_MAX32620.S +++ b/source/hic_hal/maxim/max32620/armcc/startup_MAX32620.S @@ -71,12 +71,12 @@ __Vectors DCD __initial_sp ; Top of Stack DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved - DCD DAPLINK_BUILD_KEY ; Reserved - DCD DAPLINK_HIC_ID ; Reserved - DCD DAPLINK_VERSION ; Reserved + DCD DAPLINK_BUILD_KEY ; DAPLINK: Build type (BL/IF) + DCD DAPLINK_HIC_ID ; DAPLINK: Compatibility + DCD DAPLINK_VERSION ; DAPLINK: Version DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler - DCD g_board_info ; Ptr to Board info, family info other target details + DCD g_board_info ; DAPLINK: Pointer to board/family/target info DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler diff --git a/source/hic_hal/maxim/max32620/gcc/startup_MAX32620.S b/source/hic_hal/maxim/max32620/gcc/startup_MAX32620.S index ee1fc680b..6fee1ebfc 100644 --- a/source/hic_hal/maxim/max32620/gcc/startup_MAX32620.S +++ b/source/hic_hal/maxim/max32620/gcc/startup_MAX32620.S @@ -38,12 +38,12 @@ __isr_vector: .long BusFault_Handler /* Bus Fault Handler*/ .long UsageFault_Handler /* Usage Fault Handler*/ .long 0 /* Reserved*/ - .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ - .long DAPLINK_HIC_ID /* Compatibility*/ - .long DAPLINK_VERSION /* Version*/ + .long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF)*/ + .long DAPLINK_HIC_ID /* DAPLINK: Compatibility*/ + .long DAPLINK_VERSION /* DAPLINK: Version*/ .long SVC_Handler /* SVCall Handler*/ .long DebugMon_Handler /* Debug Monitor Handler*/ - .long g_board_info /* Ptr to Board info, family info other target details*/ + .long g_board_info /* DAPLINK: Pointer to board/family/target info*/ .long PendSV_Handler /* PendSV Handler*/ .long SysTick_Handler /* SysTick Handler*/ diff --git a/source/hic_hal/maxim/max32625/armcc/startup_max32625.S b/source/hic_hal/maxim/max32625/armcc/startup_max32625.S index e1e006033..446dbc60c 100755 --- a/source/hic_hal/maxim/max32625/armcc/startup_max32625.S +++ b/source/hic_hal/maxim/max32625/armcc/startup_max32625.S @@ -75,12 +75,12 @@ __Vectors DCD __initial_sp ; Top of Stack DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved - DCD DAPLINK_BUILD_KEY ; Build type - BL/IF - DCD DAPLINK_HIC_ID ; Compatibility - DCD DAPLINK_VERSION ; Version + DCD DAPLINK_BUILD_KEY ; DAPLINK: Build type (BL/IF) + DCD DAPLINK_HIC_ID ; DAPLINK: Compatibility + DCD DAPLINK_VERSION ; DAPLINK: Version DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler - DCD g_board_info ; Ptr to Board info, family info other target details + DCD g_board_info ; DAPLINK: Pointer to board/family/target info DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler diff --git a/source/hic_hal/maxim/max32625/gcc/startup_max32625.S b/source/hic_hal/maxim/max32625/gcc/startup_max32625.S index 9df241d1d..680420f21 100644 --- a/source/hic_hal/maxim/max32625/gcc/startup_max32625.S +++ b/source/hic_hal/maxim/max32625/gcc/startup_max32625.S @@ -46,12 +46,12 @@ __isr_vector: .long BusFault_Handler /* Bus Fault Handler */ .long UsageFault_Handler /* Usage Fault Handler */ .long 0 /* Reserved */ - .long DAPLINK_BUILD_KEY /* Build type - BL/IF */ - .long DAPLINK_HIC_ID /* Compatibility */ - .long DAPLINK_VERSION /* Version */ + .long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF) */ + .long DAPLINK_HIC_ID /* DAPLINK: Compatibility */ + .long DAPLINK_VERSION /* DAPLINK: Version */ .long SVC_Handler /* SVCall Handler */ .long DebugMon_Handler /* Debug Monitor Handler */ - .long g_board_info /* Ptr to Board info, family info other target details */ + .long g_board_info /* DAPLINK: Pointer to board/family/target info */ .long PendSV_Handler /* PendSV Handler */ .long SysTick_Handler /* SysTick Handler */ diff --git a/source/hic_hal/nuvoton/m48ssidae/armcc/startup_M480.s b/source/hic_hal/nuvoton/m48ssidae/armcc/startup_M480.s index 3cd352d5e..4bdd57cc6 100644 --- a/source/hic_hal/nuvoton/m48ssidae/armcc/startup_M480.s +++ b/source/hic_hal/nuvoton/m48ssidae/armcc/startup_M480.s @@ -78,12 +78,12 @@ __Vectors DCD __initial_sp ; Top of Stack DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved - DCD DAPLINK_BUILD_KEY ; Build type - BL/IF - DCD DAPLINK_HIC_ID ; Compatibility - DCD DAPLINK_VERSION ; Version + DCD DAPLINK_BUILD_KEY ; DAPLINK: Build type (BL/IF) + DCD DAPLINK_HIC_ID ; DAPLINK: Compatibility + DCD DAPLINK_VERSION ; DAPLINK: Version DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler - DCD g_board_info ; Ptr to Board info, family info other target details + DCD g_board_info ; DAPLINK: Pointer to board/family/target info DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler diff --git a/source/hic_hal/nuvoton/m48ssidae/gcc/startup_M480.S b/source/hic_hal/nuvoton/m48ssidae/gcc/startup_M480.S index 1c06187ca..f0de23ea2 100644 --- a/source/hic_hal/nuvoton/m48ssidae/gcc/startup_M480.S +++ b/source/hic_hal/nuvoton/m48ssidae/gcc/startup_M480.S @@ -38,12 +38,12 @@ __isr_vector: .long BusFault_Handler /* Bus Fault Handler*/ .long UsageFault_Handler /* Usage Fault Handler*/ .long 0 /* Reserved*/ - .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ - .long DAPLINK_HIC_ID /* Compatibility*/ - .long DAPLINK_VERSION /* Version*/ + .long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF)*/ + .long DAPLINK_HIC_ID /* DAPLINK: Compatibility*/ + .long DAPLINK_VERSION /* DAPLINK: Version*/ .long SVC_Handler /* SVCall Handler*/ .long DebugMon_Handler /* Debug Monitor Handler*/ - .long g_board_info /* Ptr to Board info, family info other target details*/ + .long g_board_info /* DAPLINK: Pointer to board/family/target info*/ .long PendSV_Handler /* PendSV Handler*/ .long SysTick_Handler /* SysTick Handler*/ diff --git a/source/hic_hal/nxp/lpc11u35/armcc/startup_LPC11Uxx.s b/source/hic_hal/nxp/lpc11u35/armcc/startup_LPC11Uxx.s index d65106a40..42f0e58d8 100644 --- a/source/hic_hal/nxp/lpc11u35/armcc/startup_LPC11Uxx.s +++ b/source/hic_hal/nxp/lpc11u35/armcc/startup_LPC11Uxx.s @@ -59,12 +59,12 @@ __Vectors DCD __initial_sp ; Top of Stack DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved - DCD DAPLINK_BUILD_KEY ; Build type - BL/IF - DCD DAPLINK_HIC_ID ; Compatibility - DCD DAPLINK_VERSION ; Version + DCD DAPLINK_BUILD_KEY ; DAPLINK: Build type (BL/IF) + DCD DAPLINK_HIC_ID ; DAPLINK: Compatibility + DCD DAPLINK_VERSION ; DAPLINK: Version DCD SVC_Handler ; SVCall Handler DCD 0 ; Reserved - DCD g_board_info ; Ptr to Board info, family info other target details + DCD g_board_info ; DAPLINK: Pointer to board/family/target info DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler diff --git a/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11Uxx.S b/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11Uxx.S index ba844a58e..493344cdc 100644 --- a/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11Uxx.S +++ b/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11Uxx.S @@ -34,12 +34,12 @@ __isr_vector: .long 0 /* Reserved */ .long 0 /* Reserved */ .long 0 /* Reserved */ - .long DAPLINK_BUILD_KEY /* Build type - BL/IF */ - .long DAPLINK_HIC_ID /* Compatibility */ - .long DAPLINK_VERSION /* Version */ + .long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF) */ + .long DAPLINK_HIC_ID /* DAPLINK: Compatibility */ + .long DAPLINK_VERSION /* DAPLINK: Version */ .long SVC_Handler /* SVCall Handler */ .long 0 /* Reserved */ - .long g_board_info /* Ptr to Board info, family info other target details */ + .long g_board_info /* DAPLINK: Pointer to board/family/target info */ .long PendSV_Handler /* PendSV Handler */ .long SysTick_Handler /* SysTick Handler */ diff --git a/source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s b/source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s index 488aa1091..14a928ade 100644 --- a/source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s +++ b/source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s @@ -61,12 +61,12 @@ __Vectors DCD __initial_sp ; 0 Top of Stack DCD BusFault_Handler ; 5 Bus Fault Handler DCD UsageFault_Handler ; 6 Usage Fault Handler DCD Sign_Value ; 7 Reserved - DCD DAPLINK_BUILD_KEY ; 8 Build type - BL/IF - DCD DAPLINK_HIC_ID ; 9 Compatibility - DCD DAPLINK_VERSION ; 10 Version + DCD DAPLINK_BUILD_KEY ; 8 DAPLINK: Build type (BL/IF) + DCD DAPLINK_HIC_ID ; 9 DAPLINK: Compatibility + DCD DAPLINK_VERSION ; 10 DAPLINK: Version DCD SVC_Handler ; 11 SVCall Handler DCD DebugMon_Handler ; 12 Debug Monitor Handler - DCD g_board_info ; 13 Ptr to Board info, family info other target details + DCD g_board_info ; 13 DAPLINK: Pointer to board/family/target info DCD PendSV_Handler ; 14 PendSV Handler DCD SysTick_Handler ; 15 SysTick Handler diff --git a/source/hic_hal/nxp/lpc4322/gcc/startup_LPC43xx.S b/source/hic_hal/nxp/lpc4322/gcc/startup_LPC43xx.S index 51ff0d917..6bd7bffec 100644 --- a/source/hic_hal/nxp/lpc4322/gcc/startup_LPC43xx.S +++ b/source/hic_hal/nxp/lpc4322/gcc/startup_LPC43xx.S @@ -38,12 +38,12 @@ __isr_vector: .long BusFault_Handler /* Bus Fault Handler*/ .long UsageFault_Handler /* Usage Fault Handler*/ .long 0x5A5A5A5A /* Reserved*/ - .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ - .long DAPLINK_HIC_ID /* Compatibility*/ - .long DAPLINK_VERSION /* Version*/ + .long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF)*/ + .long DAPLINK_HIC_ID /* DAPLINK: Compatibility*/ + .long DAPLINK_VERSION /* DAPLINK: Version*/ .long SVC_Handler /* SVCall Handler*/ .long DebugMon_Handler /* Debug Monitor Handler*/ - .long g_board_info /* Ptr to Board info, family info other target details*/ + .long g_board_info /* DAPLINK: Pointer to board/family/target info*/ .long PendSV_Handler /* PendSV Handler*/ .long SysTick_Handler /* SysTick Handler*/ diff --git a/source/hic_hal/nxp/lpc55xx/gcc/startup_LPC55S69_cm33_core0.S b/source/hic_hal/nxp/lpc55xx/gcc/startup_LPC55S69_cm33_core0.S index 15833b178..f304e606f 100644 --- a/source/hic_hal/nxp/lpc55xx/gcc/startup_LPC55S69_cm33_core0.S +++ b/source/hic_hal/nxp/lpc55xx/gcc/startup_LPC55S69_cm33_core0.S @@ -32,12 +32,12 @@ __isr_vector: .long BusFault_Handler /* Bus Fault Handler*/ .long UsageFault_Handler /* Usage Fault Handler*/ .long SecureFault_Handler /* Secure Fault Handler*/ - .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ - .long DAPLINK_HIC_ID /* Compatibility*/ - .long DAPLINK_VERSION /* Version*/ + .long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF)*/ + .long DAPLINK_HIC_ID /* DAPLINK: Compatibility*/ + .long DAPLINK_VERSION /* DAPLINK: Version*/ .long SVC_Handler /* SVCall Handler*/ .long DebugMon_Handler /* Debug Monitor Handler*/ - .long g_board_info /* Ptr to Board info, family info other target details*/ + .long g_board_info /* DAPLINK: Pointer to board/family/target info*/ .long PendSV_Handler /* PendSV Handler*/ .long SysTick_Handler /* SysTick Handler*/ diff --git a/source/hic_hal/stm32/stm32f103xb/armcc/startup_stm32f103xb.S b/source/hic_hal/stm32/stm32f103xb/armcc/startup_stm32f103xb.S index 25c08d903..155b92a47 100644 --- a/source/hic_hal/stm32/stm32f103xb/armcc/startup_stm32f103xb.S +++ b/source/hic_hal/stm32/stm32f103xb/armcc/startup_stm32f103xb.S @@ -83,12 +83,12 @@ __Vectors DCD __initial_sp ; Top of Stack DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved - DCD DAPLINK_BUILD_KEY ; Build type - BL/IF - DCD DAPLINK_HIC_ID ; Compatibility - DCD DAPLINK_VERSION ; Version + DCD DAPLINK_BUILD_KEY ; DAPLINK: Build type (BL/IF) + DCD DAPLINK_HIC_ID ; DAPLINK: Compatibility + DCD DAPLINK_VERSION ; DAPLINK: Version DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler - DCD g_board_info ; Ptr to Board info, family info other target details + DCD g_board_info ; DAPLINK: Pointer to board/family/target info DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler diff --git a/source/hic_hal/stm32/stm32f103xb/gcc/startup_stm32f103xb.S b/source/hic_hal/stm32/stm32f103xb/gcc/startup_stm32f103xb.S index ddc406b7c..db60afd57 100644 --- a/source/hic_hal/stm32/stm32f103xb/gcc/startup_stm32f103xb.S +++ b/source/hic_hal/stm32/stm32f103xb/gcc/startup_stm32f103xb.S @@ -38,12 +38,12 @@ __isr_vector: .long BusFault_Handler /* Bus Fault Handler*/ .long UsageFault_Handler /* Usage Fault Handler*/ .long 0 /* Reserved*/ - .long DAPLINK_BUILD_KEY /* Build type - BL/IF*/ - .long DAPLINK_HIC_ID /* Compatibility*/ - .long DAPLINK_VERSION /* Version*/ + .long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF)*/ + .long DAPLINK_HIC_ID /* DAPLINK: Compatibility*/ + .long DAPLINK_VERSION /* DAPLINK: Version*/ .long SVC_Handler /* SVCall Handler*/ .long DebugMon_Handler /* Debug Monitor Handler*/ - .long g_board_info /* Ptr to Board info, family info other target details*/ + .long g_board_info /* DAPLINK: Pointer to board/family/target info*/ .long PendSV_Handler /* PendSV Handler*/ .long SysTick_Handler /* SysTick Handler*/ From b3ce2c1c1e319aaf863ff5c5cf171779213df994 Mon Sep 17 00:00:00 2001 From: iosabi Date: Mon, 9 Aug 2021 23:33:51 +0200 Subject: [PATCH 197/617] LPC55xx: fix USART0 initialization The USART0 CMSIS driver needs to be first initialized with `Initialize`, then powered up with `PowerControl(ARM_POWER_FULL)` and then configured. Without the call to `PowerControl` the USART0 block was never powered and the call to `Control` to configure the baudrate was silently failing. Verified that the RX/TX pins (PIO0_24 and 25) work after this patch by connecting them to another USB-to-UART at 115200 bps. --- source/hic_hal/nxp/lpc55xx/uart.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/source/hic_hal/nxp/lpc55xx/uart.c b/source/hic_hal/nxp/lpc55xx/uart.c index 25053f5df..660c811e9 100644 --- a/source/hic_hal/nxp/lpc55xx/uart.c +++ b/source/hic_hal/nxp/lpc55xx/uart.c @@ -61,6 +61,7 @@ int32_t uart_initialize(void) { clear_buffers(); Driver_USART0.Initialize(uart_handler); + Driver_USART0.PowerControl(ARM_POWER_FULL); return 1; } @@ -68,6 +69,8 @@ int32_t uart_initialize(void) int32_t uart_uninitialize(void) { USART_INSTANCE.Control(ARM_USART_CONTROL_RX, 0); + USART_INSTANCE.Control(ARM_USART_ABORT_RECEIVE, 0U); + Driver_USART0.PowerControl(ARM_POWER_OFF); Driver_USART0.Uninitialize(); clear_buffers(); From 2ec92f5ff4d2255903225a9a3aa75aabdecad8f3 Mon Sep 17 00:00:00 2001 From: iosabi Date: Tue, 10 Aug 2021 01:34:19 +0200 Subject: [PATCH 198/617] LPC55xx: Fix ARM_USART_ABORT_{SEND,RECEIVE} control calls The FIFOINTENSET register is used to read the currently enabled interrupts in the USART block and to enable new interrupts by writing a 1, but it can't be used to disable them. For that we need to use the FIFOINTENTCLR register. USART_TransferAbortSend and USART_TransferAbortReceive are the equivalent functions using the same API that the rest of this driver is using so it makes more sense to use those functions instead. --- .../nxp/lpc55xx/LPC55S69/drivers/fsl_usart_cmsis.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart_cmsis.c b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart_cmsis.c index 6e6a200a0..debbd6345 100644 --- a/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart_cmsis.c +++ b/source/hic_hal/nxp/lpc55xx/LPC55S69/drivers/fsl_usart_cmsis.c @@ -683,16 +683,12 @@ static int32_t USART_NonBlockingControl(uint32_t control, uint32_t arg, cmsis_us { /* Abort Send */ case ARM_USART_ABORT_SEND: - usart->resource->base->FIFOINTENSET &= ~USART_FIFOINTENSET_TXLVL_MASK; - usart->handle->txDataSize = 0; - usart->handle->txState = kUSART_TxIdle; + USART_TransferAbortSend(usart->resource->base, usart->handle); return ARM_DRIVER_OK; /* Abort receive */ case ARM_USART_ABORT_RECEIVE: - usart->resource->base->FIFOINTENSET &= ~USART_FIFOINTENSET_RXLVL_MASK; - usart->handle->rxDataSize = 0U; - usart->handle->rxState = kUSART_RxIdle; + USART_TransferAbortReceive(usart->resource->base, usart->handle); return ARM_DRIVER_OK; default: From 8fe86c376769252e7b0eb8fa439ee0df62d9e0dd Mon Sep 17 00:00:00 2001 From: iosabi Date: Tue, 10 Aug 2021 01:50:01 +0200 Subject: [PATCH 199/617] LPC55xx: Abort previous Receive() call when reconfiguring `uart_set_configuration()` configures the USART driver baudrate and starts a new `Receive()` call of one byte which calls again the next one byte `Receive()` from its callback. `uart_set_configuration()` would normally be called only once, but there's nothing preventing the USBD_CDC_ACM code to change the baudrate multiple times. Calling `Receive()` while another call is pending on the same handle returns an `ARM_DRIVER_ERROR_BUSY` error and fail. This commit aborts the ongoing transfer (if any) before starting a new one. Without this commit the RX side of the USART0 would not work if `uart_set_configuration()` was called multiple times after connection, something that's apparently normal with some Linux serial tools. With this patch the RX side works reliably. --- source/hic_hal/nxp/lpc55xx/uart.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/source/hic_hal/nxp/lpc55xx/uart.c b/source/hic_hal/nxp/lpc55xx/uart.c index 660c811e9..94d5077b7 100644 --- a/source/hic_hal/nxp/lpc55xx/uart.c +++ b/source/hic_hal/nxp/lpc55xx/uart.c @@ -154,6 +154,11 @@ int32_t uart_set_configuration(UART_Configuration *config) NVIC_DisableIRQ(USART_IRQ); clear_buffers(); + + // If there was no Receive() call in progress aborting it is harmless. + USART_INSTANCE.Control(ARM_USART_CONTROL_RX, 0U); + USART_INSTANCE.Control(ARM_USART_ABORT_RECEIVE, 0U); + uint32_t r = USART_INSTANCE.Control(control, config->Baudrate); if (r != ARM_DRIVER_OK) { return 0; From 2fefbbf03dbacb0ac6f5da487dad19bbe0958074 Mon Sep 17 00:00:00 2001 From: Russ Butler Date: Tue, 10 Aug 2021 17:23:59 -0500 Subject: [PATCH 200/617] Fix k64f stack overflow during WebUSB flashing When flashing via the WebUSB interface (CMSIS v2) the K64F hangs and USB eventually times out. This is because the main stack overflows during this operation casuing RTX to trap and loop forever in osRtxErrorNotify. This patch prevents a stack overflow by by increasing the main stack size from 800 bytes to 864 bytes. Note - maximum stack usage recorded during WebUSB flashing is 816 bytes. --- source/daplink/interface/tasks.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/daplink/interface/tasks.h b/source/daplink/interface/tasks.h index f0274440f..438ea5f9a 100644 --- a/source/daplink/interface/tasks.h +++ b/source/daplink/interface/tasks.h @@ -25,7 +25,7 @@ // trouble here is that reset for different targets is implemented differently so all targets // have to use the largest stack or these have to be defined in multiple places... Not ideal // may want to move away from threads for some of these behaviours to optimize mempory usage (RAM) -#define MAIN_TASK_STACK (800) +#define MAIN_TASK_STACK (864) #define MAIN_TASK_PRIORITY (osPriorityNormal) #endif From 28605433b6ffbfa0e59055e964d4ee28b6c3831a Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sun, 13 Jun 2021 21:01:02 -0500 Subject: [PATCH 201/617] run_test: Fix for progen builds --- test/daplink_firmware.py | 6 ++++-- test/run_test.py | 12 ++++++++---- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/test/daplink_firmware.py b/test/daplink_firmware.py index 1bd6b364a..e2e5f2357 100644 --- a/test/daplink_firmware.py +++ b/test/daplink_firmware.py @@ -35,7 +35,9 @@ def load_bundle_from_project(tool='uvision'): Note - This does not build the project. It only returns the firmware that has already been built. """ - assert (tool == 'uvision' or tool == 'mbedcli'), 'Input tool %s is not supported' % (tool) + progen_toolchains = ['make_gcc_arm', 'make_armclang', 'make_armcc', + 'cmake_gcc_arm', 'cmake_armclang', 'cmake_armcc'] + assert (tool in progen_toolchains or tool == 'uvision' or tool == 'mbedcli'), 'Input tool %s is not supported' % (tool) self_path = os.path.abspath(__file__) test_dir = os.path.dirname(self_path) @@ -43,7 +45,7 @@ def load_bundle_from_project(tool='uvision'): assert os.path.basename(test_dir) == 'test', 'The script "%s" must be ' \ 'located in the "test" directory of daplink to work correctly.' - if tool == 'uvision': + if tool in progen_toolchains or tool == 'uvision': project_dir = os.path.join(daplink_dir, 'projectfiles', tool) build_folder = 'build' elif tool == 'mbedcli': diff --git a/test/run_test.py b/test/run_test.py index 91d099df1..3610fdfab 100644 --- a/test/run_test.py +++ b/test/run_test.py @@ -29,8 +29,9 @@ Directory with firmware images to test --firmware {k20dx_k64f_if,lpc11u35_sscity_if,...} (run script with --help to see full list) Firmware to test - --project-tool TOOL choices=['uvision', 'mbedcli'],'Tool used to compile the project', - default='uvision' + --project-tool {make_gcc_arm,make_armclang,make_armcc,cmake_gcc_arm,cmake_armclang,cmake_armcc,uvision,mbedcli} + Tool used to compile the project + default='make_gcc_arm' --logdir LOGDIR Directory to log test results to --noloadif Skip load step for interface. --notestendpt Dont test the interface USB endpoints. @@ -521,6 +522,9 @@ def main(): firmware_choices = [firmware for firmware in firmware_list if firmware.endswith('_if')] + progen_toolchains = ['make_gcc_arm', 'make_armclang', 'make_armcc', + 'cmake_gcc_arm', 'cmake_armclang', 'cmake_armcc'] + toolchains = ['uvision', 'mbedcli'] description = 'DAPLink validation and testing tool' parser = argparse.ArgumentParser(description=description) parser.add_argument('--targetdir', @@ -533,9 +537,9 @@ def main(): parser.add_argument('--firmwaredir', help='Directory with firmware images to test', default=None) - parser.add_argument('--project-tool', choices=['uvision', 'mbedcli'], + parser.add_argument('--project-tool', choices=progen_toolchains + toolchains, help='Tool used to compile the project', - default='uvision') + default='make_gcc_arm') parser.add_argument('--firmware', help='Firmware to test', action='append', choices=firmware_choices, default=[], required=False) parser.add_argument('--logdir', help='Directory to log test results to', From 7dc4fd4803a5cd40614272e0931f077d54d2ebaa Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sun, 13 Jun 2021 21:07:29 -0500 Subject: [PATCH 202/617] run_test: Send break before flushing buffers Some extraneous byte is being received when break is sent. This might change might introduce a race condition. --- test/serial_test.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/serial_test.py b/test/serial_test.py index e53a9ae8b..a5853276c 100644 --- a/test/serial_test.py +++ b/test/serial_test.py @@ -91,9 +91,9 @@ def new_session_with_baud(self, baud, parent_test): self.raw_serial.timeout = 1.0 # Reset the target + self.raw_serial.sendBreak() self.raw_serial.reset_output_buffer() self.raw_serial.reset_input_buffer() - self.raw_serial.sendBreak() # Wait until the target is initialized expected_resp = "{init}" From 6113c13fb7e7d48a99997da834c0d459751e9487 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 14 Jun 2021 02:29:44 -0500 Subject: [PATCH 203/617] run_test: re-organize tests --- test/board.py | 725 ++++++++++++++++- test/{daplink_firmware.py => bundle.py} | 118 +-- test/daplink_board.py | 727 ------------------ test/firmware.py | 104 ++- test/run_test.py | 18 +- test/test_info.py | 3 +- test/{ => tests}/test_daplink.py | 6 +- test/{hid_test.py => tests/test_hid.py} | 0 test/{msd_test.py => tests/test_msd.py} | 3 + test/{serial_test.py => tests/test_serial.py} | 10 +- test/{usb_test.py => tests/test_usb.py} | 9 +- test/{ => tests}/usb_cdc.py | 0 test/{ => tests}/usb_hid.py | 0 test/{ => tests}/usb_msd.py | 0 14 files changed, 834 insertions(+), 889 deletions(-) rename test/{daplink_firmware.py => bundle.py} (56%) delete mode 100644 test/daplink_board.py rename test/{ => tests}/test_daplink.py (99%) rename test/{hid_test.py => tests/test_hid.py} (100%) rename test/{msd_test.py => tests/test_msd.py} (99%) rename test/{serial_test.py => tests/test_serial.py} (95%) rename test/{usb_test.py => tests/test_usb.py} (98%) rename test/{ => tests}/usb_cdc.py (100%) rename test/{ => tests}/usb_hid.py (100%) rename test/{ => tests}/usb_msd.py (100%) diff --git a/test/board.py b/test/board.py index 702c79588..dce3b97da 100644 --- a/test/board.py +++ b/test/board.py @@ -15,52 +15,713 @@ # See the License for the specific language governing permissions and # limitations under the License. # - + from __future__ import absolute_import +import os +import re +import time +import subprocess +import sys +import binascii +import itertools +import mbed_lstools +import info +from tests import test_daplink +from test_info import TestInfoStub, TestInfo +from intelhex import IntelHex +from pyocd.core.helpers import ConnectHelper -class Board(object): +FILE_IGNORE_PATTERN_LIST = [ + re.compile("\\._\\.Trashes") +] - def update_interface(self): - raise NotImplementedError() - def update_bootloader(self): - raise NotImplementedError() +# This prevents the following error message from getting +# displayed on windows if the mbed dismounts unexpectedly +# during a transfer: +# There is no disk in the drive. Please insert a disk into +# drive \Device\\ +def disable_popup(): + if sys.platform.startswith("win"): + # pylint: disable=invalid-name + import ctypes + SEM_FAILCRITICALERRORS = 1 + GetErrorMode = \ + ctypes.windll.kernel32.GetErrorMode # @UndefinedVariable + GetErrorMode.restype = ctypes.c_uint + GetErrorMode.argtypes = [] + SetErrorMode = \ + ctypes.windll.kernel32.SetErrorMode # @UndefinedVariable + SetErrorMode.restype = ctypes.c_uint + SetErrorMode.argtypes = [ctypes.c_uint] - def prepare_for_testing(self): - raise NotImplementedError() + err_mode = GetErrorMode() + err_mode |= SEM_FAILCRITICALERRORS + SetErrorMode(err_mode) - @property - def hw_msd_support(self): - """Set to True if the hardware supports mass storage""" - raise NotImplementedError() +disable_popup() - @property - def hw_cdc_support(self): - """Set to True if the hardware supports a serial port""" - raise NotImplementedError() - @property - def hw_hid_support(self): - """Set to True if the hardware supports HID""" - raise NotImplementedError() +def get_all_attached_daplink_boards(): + all_boards = [] + lstools = mbed_lstools.create() + mbed_list = lstools.list_mbeds() + for mbed in mbed_list: + unique_id = mbed['target_id'] + board = DaplinkBoard(unique_id) + if board._mode is not None: #Valid daplink should have set this mode + all_boards.append(board) + else: + print("Warning: DAPLink tests cannot be done on board %s" % board.unique_id) + return all_boards + + +def _unique_id_to_host_id(unique_id): + """Return the chip id unique to the daplink host procesor + + Unique ID has the following fomat + Board ID - 4 bytes + Version - 4 bytes + Host ID - Everything else + """ + return unique_id[8:8 + 32] + + +def _get_board_endpoints(unique_id): + """Return a tuple of unique_id, serial_port, mount_point""" + lstools = mbed_lstools.create() + mbed_list = lstools.list_mbeds() + + host_id = _unique_id_to_host_id(unique_id) + for mbed in mbed_list: + mbed_unique_id = mbed['target_id'] + mbed_serial_port = mbed['serial_port'] + mbed_mount_point = mbed['mount_point'] + mbed_host_id = _unique_id_to_host_id(mbed_unique_id) + if mbed_host_id == host_id: + return mbed_unique_id, mbed_serial_port, mbed_mount_point + return None + + +def _ranges(i): + for _, b in itertools.groupby(enumerate(i), lambda x_y: x_y[1] - x_y[0]): + b = list(b) + yield b[0][1], b[-1][1] + + +def _parse_kvp_file(file_path, parent_test=None): + """Parse details.txt and return True if successful""" + test_info = None + kvp = {} + if parent_test is not None: + test_info = parent_test.create_subtest('parse_kvp_file') + line_format = re.compile("^([a-zA-Z0-9 ]+): +(.+)$") + if not os.path.isfile(file_path): + return kvp + + with open(file_path, "r") as file_handle: + for line in file_handle: + if len(line) <= 0: + if test_info is not None: + test_info.failure("Empty line in %s" % file_path) + continue + + if line[0] == '#': + # The line is a comment + continue + + match = line_format.match(line) + if match is None: + if test_info is not None: + test_info.failure("Invalid line: %s" % line) + continue + + key = match.group(1) + key = key.lower().replace(" ", "_") + value = match.group(2) + value = value.lower() + value = value.strip() + if key in kvp: + if test_info is not None: + test_info.failure("Duplicate key %s" % key) + continue + kvp[key] = value + return kvp + + +def _compute_crc(hex_file_path): + # Read in hex file + new_hex_file = IntelHex() + new_hex_file.padding = 0xFF + new_hex_file.fromfile(hex_file_path, format='hex') + + # Get the starting and ending address + addresses = new_hex_file.addresses() + addresses.sort() + start_end_pairs = list(_ranges(addresses)) + regions = len(start_end_pairs) + assert regions == 1, ("Error - only 1 region allowed in " + "hex file %i found." % regions) + start, end = start_end_pairs[0] + + # Compute checksum over the range (don't include data at location of crc) + size = end - start + 1 + crc_size = size - 4 + data = new_hex_file.tobinarray(start=start, size=crc_size) + data_crc32 = binascii.crc32(data) & 0xFFFFFFFF + + # Grab the crc from the image + embedded_crc32 = (((new_hex_file[end - 3] & 0xFF) << 0) | + ((new_hex_file[end - 2] & 0xFF) << 8) | + ((new_hex_file[end - 1] & 0xFF) << 16) | + ((new_hex_file[end - 0] & 0xFF) << 24)) + return data_crc32, embedded_crc32 + + +def _run_chkdsk(drive): + args = ["chkdsk", drive] + process = subprocess.Popen(args, stdin=subprocess.PIPE, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE) + process.communicate(input=bytearray('n\r\n',encoding='ascii')) # Answer no if prompted + process.wait() + return process.returncode + + +class AssertInfo(object): + + def __init__(self, file_name, line_number): + self._file = file_name + self._line = line_number @property - def mount_point(self): - """Mount point of the drive or None if no SW support""" - raise NotImplementedError() + def file(self): + return self._file @property - def serial_port(self): - """Serial port string usable with pySerial or None if no SW support""" - raise NotImplementedError() + def line(self): + return self._line + + +class DaplinkBoard(object): + + MODE_IF = "interface" + MODE_BL = "bootloader" + + # Keys for details.txt + KEY_UNIQUE_ID = "unique_id" + KEY_HIC_ID = "hic_id" + KEY_MODE = "daplink_mode" + KEY_BL_VERSION = "bootloader_version" + KEY_IF_VERSION = "interface_version" + KEY_GIT_SHA = "git_sha" + KEY_LOCAL_MODS = "local_mods" + KEY_USB_INTERFACES = "usb_interfaces" + KEY_BL_CRC = "bootloader_crc" + KEY_IF_CRC = "interface_crc" + KEY_REMOUNT_COUNT = "remount_count" + + def __init__(self, unique_id): + + self.unique_id = unique_id + self.details_txt = None + self._mode = None + self._remount_count = None + self._assert = None + self._check_fs_on_remount = False + self._manage_assert = False + self.update_board_info() + + def __str__(self): + return "Name=%s Unique ID=%s" % (self.name, self.get_unique_id()) + + def get_unique_id(self): + return self.unique_id + + def get_board_id(self): + return self.board_id @property - def board_id(self): - """The ID of this board type""" - raise NotImplementedError() + def hic_id(self): + return self._hic_id @property - def unique_id(self): - """ID which uniquely identifies this board""" - raise NotImplementedError() + def name(self): + if self.board_id in info.BOARD_ID_TO_BUILD_TARGET: + board_target = info.BOARD_ID_TO_BUILD_TARGET[self.board_id] + else: + board_target = "Unknown" + return board_target + + def get_serial_port(self): + return self.serial_port + + def get_mount_point(self): + return self.mount_point + + def get_connected(self): + """Check if the board is connected""" + return os.path.isdir(self.mount_point) + + def get_failure_message_and_type(self): + """Get the failure message and types from fail.txt + + return None if there there is no failure + """ + error = None + error_type = None + fail_file = self.get_file_path('FAIL.TXT') + if not self.get_connected(): + raise Exception('Board not connected') + if os.path.isfile(fail_file): + with open(fail_file, 'r') as fail_file_handle: + msg = fail_file_handle.read() + lines = msg.splitlines() + if len(lines) == 2: + if lines[0].startswith('error: '): + error = lines[0][7:] + else: + raise Exception('Can not parse error line in FAIL.TXT') + if lines[1].startswith('type: '): + error_type = lines[1][6:] + else: + raise Exception('Can not parse type line in FAIL.TXT') + else: + raise Exception('Wrong number of lines in FAIL.TXT, expected: 2') + return error, error_type + + def get_assert_info(self): + """Return an AssertInfo if an assert occurred, else None""" + return self._assert + + def get_mode(self): + """Return either MODE_IF or MODE_BL""" + assert ((self._mode is DaplinkBoard.MODE_BL) or + (self._mode is DaplinkBoard.MODE_IF)) + return self._mode + + def get_file_path(self, file_name): + """Convenience function to the path to a file on the drive""" + return os.path.normpath(self.mount_point + os.sep + file_name) + + def refresh(self, parent_test): + """Remount driver to get updated contents""" + refresh_filename = self.get_file_path('REFRESH.ACT') + with open(refresh_filename, 'wb') as _: + pass + self.wait_for_remount(parent_test) + + def set_mode(self, mode, parent_test=None): + """Set the mode to either MODE_IF or MODE_BL""" + assert ((mode is DaplinkBoard.MODE_BL) or + (mode is DaplinkBoard.MODE_IF)) + if parent_test is None: + parent_test = TestInfoStub() + test_info = parent_test.create_subtest('set_mode') + current_mode = self.get_mode() + if current_mode is mode: + # No mode change needed + return + + if mode is self.MODE_BL: + test_info.info("changing mode IF -> BL") + # Create file to enter BL mode + start_bl_path = self.get_file_path('START_BL.ACT') + with open(start_bl_path, 'wb') as _: pass + elif mode is self.MODE_IF: + test_info.info("changing mode BL -> IF") + # Create file to enter IF mode + start_if_path = self.get_file_path('START_IF.ACT') + with open(start_if_path, 'wb') as _: pass + else: + test_info.warning("Board is in unknown mode") + self.wait_for_remount(test_info) + + new_mode = self.get_mode() + if new_mode != mode: + test_info.failure("Board in wrong mode: %s" % new_mode) + raise Exception("Could not change board mode") + + def set_check_fs_on_remount(self, enabled): + assert isinstance(enabled, bool) + self._check_fs_on_remount = enabled + self.set_assert_auto_manage(enabled) + + def set_assert_auto_manage(self, enabled): + assert isinstance(enabled, bool) + self.clear_assert() + self._manage_assert = enabled + + def clear_assert(self): + assert_path = self.get_file_path("ASSERT.TXT") + if os.path.isfile(assert_path): + os.remove(assert_path) + self.wait_for_remount(TestInfoStub()) + + def run_board_test(self, parent_test): + test_daplink.daplink_test(self, parent_test) + + def read_target_memory(self, addr, size, resume=True): + assert self.get_mode() == self.MODE_IF + with ConnectHelper.session_with_chosen_probe(unique_id=self.get_unique_id(), + resume_on_disconnect=resume) as session: + data = session.target.read_memory_block8(addr, size) + return bytearray(data) + + def test_fs(self, parent_test): + """Check if the raw filesystem is valid""" + if sys.platform.startswith("win"): + test_info = parent_test.create_subtest('test_fs') + returncode = _run_chkdsk(self.mount_point) + test_info.info('chkdsk returned %s' % returncode) + if returncode != 0: + test_info.failure('Disk corrupt') + + # Windows 8/10 workaround - rerun chkdsk until disk caching is on + # Notes about this problem: + # - This is less likely to occur when the "storage" service is + # turned off and/or you are running as administrator + # - When creating a directory with os.mkdir the + # following error occurs: "WindowsError: [Error 1392] The + # file or directory is corrupted and unreadable: ''" + # - When creating a file with open(, "wb") the + # following error occurs: "OError: [Errno 22] invalid + # mode ('wb') or filename: ''" + # - When a file or directory is created on the drive in explorer + # and you preform a refresh, the newly created file or + # directory disappears + persist_test_dir = self.get_file_path("persist_test_dir") + for _ in range(10): + try: + os.mkdir(persist_test_dir) + except EnvironmentError as exception: + test_info.info("cache check exception %s" % exception) + if os.path.exists(persist_test_dir): + os.rmdir(persist_test_dir) + break + test_info.info("running checkdisk to re-enable caching") + _run_chkdsk(self.mount_point) + else: + raise Exception("Unable to re-enable caching") + + # TODO - as a future improvement add linux and mac support + + # Tests for the following: + # 1. Correct files present -TODO + # 2. Contents of file are valid ascii + # 3. Each line ends with \r\n + # 4. There is no whitespace at the end of the line + # 5. Each file ends with \r\n + def test_fs_contents(self, parent_test): + """Check if the file contents are valid""" + test_info = parent_test.create_subtest('test_fs_contents') + non_ascii = b'[^\x20-\x7F\r\n]' + non_cr_lf = b'\r[^\n]|[^\r]\n' + trail_white = b'(?:\ \r|\ \n)' + end_of_file = b'\r\n$' + files = os.listdir(self.mount_point) + non_ascii_re = re.compile(non_ascii) + non_cr_lf_re = re.compile(non_cr_lf) + trail_white_re = re.compile(trail_white) + end_of_file_re = re.compile(end_of_file) + for filename in files: + filepath = self.get_file_path(filename) + if not os.path.isfile(filepath): + test_info.info("Skipping non file item %s" % filepath) + continue + skip = False + for pattern in FILE_IGNORE_PATTERN_LIST: + if pattern.match(filename): + skip = True + break + if skip: + continue + + with open(filepath, 'rb') as file_handle: + file_contents = file_handle.read() + if non_ascii_re.search(file_contents): + test_info.failure("Non ascii characters in %s" % filepath) + elif non_cr_lf_re.search(file_contents): + test_info.failure("File has non-standard line endings %s" % + filepath) + elif trail_white_re.search(file_contents): + test_info.warning("File trailing whitespace %s" % + filepath) + elif end_of_file_re.search(file_contents) is None: + test_info.warning("No newline at end of file %s" % + filepath) + else: + test_info.info("File %s valid" % filepath) + + self.test_details_txt(test_info) + + def load_interface(self, filepath, parent_test): + """Load an interface binary or hex""" + assert isinstance(filepath, str), "Invalid bootloader image!" + assert isinstance(parent_test, TestInfo), "Invalid parent test object!" + + test_info = parent_test.create_subtest('load_interface') + self.set_mode(self.MODE_BL, test_info) + + data_crc, crc_in_image = _compute_crc(filepath) + assert data_crc == crc_in_image, ("CRC in interface is wrong " + "expected 0x%x, found 0x%x" % + (data_crc, crc_in_image)) + + filename = os.path.basename(filepath) + with open(filepath, 'rb') as firmware_file: + data = firmware_file.read() + out_file = self.get_file_path(filename) + start = time.time() + with open(out_file, 'wb') as firmware_file: + firmware_file.write(data) + stop = time.time() + test_info.info("programming took %s s" % (stop - start)) + self.wait_for_remount(test_info) + + # Check the CRC + self.set_mode(self.MODE_IF, test_info) + if DaplinkBoard.KEY_IF_CRC not in self.details_txt: + test_info.failure("No interface CRC in details.txt") + return + details_crc = int(self.details_txt[DaplinkBoard.KEY_IF_CRC], 0) + test_info.info("Interface crc: 0x%x" % details_crc) + if data_crc != details_crc: + test_info.failure("Interface CRC is wrong") + + def load_bootloader(self, filepath, parent_test): + """Load a bootloader binary or hex""" + assert isinstance(filepath, str), "Invalid bootloader image!" + assert isinstance(parent_test, TestInfo), "Invalid parent test object!" + + test_info = parent_test.create_subtest('load_bootloader') + self.set_mode(self.MODE_IF, test_info) + + # Check image CRC + data_crc, crc_in_image = _compute_crc(filepath) + assert data_crc == crc_in_image, ("CRC in bootloader is wrong " + "expected 0x%x, found 0x%x" % + (data_crc, crc_in_image)) + + filename = os.path.basename(filepath) + with open(filepath, 'rb') as firmware_file: + data = firmware_file.read() + out_file = self.get_file_path(filename) + start = time.time() + with open(out_file, 'wb') as firmware_file: + firmware_file.write(data) + stop = time.time() + test_info.info("programming took %s s" % (stop - start)) + self.wait_for_remount(test_info) + + # Check the CRC + self.set_mode(self.MODE_IF, test_info) + if DaplinkBoard.KEY_BL_CRC not in self.details_txt: + test_info.failure("No bootloader CRC in details.txt") + return + details_crc = int(self.details_txt[DaplinkBoard.KEY_BL_CRC], 0) + test_info.info("Bootloader crc: 0x%x" % details_crc) + if data_crc != details_crc: + test_info.failure("Bootloader CRC is wrong") + + def wait_for_remount(self, parent_test, wait_time=600): + mode = self._mode + count = self._remount_count + test_info = parent_test.create_subtest('wait_for_remount') + + elapsed = 0 + start = time.time() + remounted = False + while os.path.isdir(self.mount_point): + if self.update_board_info(False): #check info if it is already mounted + if mode is not None and self._mode is not None and mode is not self._mode: + remounted = True + test_info.info("already remounted with change mode") + break + elif count is not None and self._remount_count is not None and count != self._remount_count: + remounted = True + test_info.info("already remounted with change mount count") + break + if elapsed > wait_time: + raise Exception("Dismount timed out") + time.sleep(0.1) + elapsed += 0.2 + else: + stop = time.time() + test_info.info("unmount took %s s" % (stop - start)) + elapsed = 0 + start = time.time() + + while not remounted: + if self.update_board_info(False): + if os.path.isdir(self.mount_point): + # Information returned by mbed-ls could be old. + # Only break from the loop if the second call to + # mbed-ls returns the same mount point. + tmp_mount = self.mount_point + if self.update_board_info(False): + if tmp_mount == self.mount_point: + break + if elapsed > wait_time: + raise Exception("Mount timed out") + time.sleep(0.1) + elapsed += 0.1 + stop = time.time() + test_info.info("mount took %s s" % (stop - start)) + + if count is not None and self._remount_count is not None: + expected_count = (0 if mode is not self._mode + else (count + 1) & 0xFFFFFFFF) + if expected_count != self._remount_count: + test_info.failure('Expected remount count of %s got %s' % + (expected_count, self._remount_count)) + + # If enabled check the filesystem + if self._check_fs_on_remount: + self.test_fs(parent_test) + self.test_fs_contents(parent_test) + self.test_details_txt(parent_test) + if self._manage_assert: + if self._assert is not None: + test_info.failure('Assert on line %s in file %s' % + (self._assert.line, self._assert.file)) + self.clear_assert() + + def update_board_info(self, exptn_on_fail=True): + """Update board info + + Update all board information variables that could + change when remounting or changing modes. + Note - before this function is set self.unique_id + must be set. + """ + + try: + endpoints = _get_board_endpoints(self.unique_id) + if endpoints is None: + if exptn_on_fail: + raise Exception("Could not update board info: %s" % + self.unique_id) + return False + self.unique_id, self.serial_port, self.mount_point = endpoints + # Serial port can be missing + if self.unique_id is None: + if exptn_on_fail: + raise Exception("Mount point is null") + return False + if self.mount_point is None: + if exptn_on_fail: + raise Exception("Mount point is null") + return False + self.board_id = int(self.unique_id[0:4], 16) + self._hic_id = int(self.unique_id[-8:], 16) + + # Note - Some legacy boards might not have details.txt + details_txt_path = self.get_file_path("details.txt") + self.details_txt = _parse_kvp_file(details_txt_path) + self._parse_assert_txt() + + self._remount_count = None + if DaplinkBoard.KEY_REMOUNT_COUNT in self.details_txt: + self._remount_count = int(self.details_txt[DaplinkBoard.KEY_REMOUNT_COUNT]) + self._mode = None + if DaplinkBoard.KEY_MODE in self.details_txt: + DETAILS_TO_MODE = { + "interface": DaplinkBoard.MODE_IF, + "bootloader": DaplinkBoard.MODE_BL, + } + mode_str = self.details_txt[DaplinkBoard.KEY_MODE] + self._mode = DETAILS_TO_MODE[mode_str] + else: + #check for race condition here + return False + return True + except Exception as e: + if exptn_on_fail: + raise e + else: + return False + + def test_details_txt(self, parent_test): + """Check that details.txt has all requied fields""" + test_info = parent_test.create_subtest('test_details_txt') + required_key_and_format = { + DaplinkBoard.KEY_UNIQUE_ID: re.compile("^[a-f0-9]{48}$"), + DaplinkBoard.KEY_HIC_ID: re.compile("^[a-f0-9]{8}$"), + DaplinkBoard.KEY_GIT_SHA: re.compile("^[a-f0-9]{40}$"), + DaplinkBoard.KEY_LOCAL_MODS: re.compile("^[01]{1}$"), + DaplinkBoard.KEY_USB_INTERFACES: re.compile("^.+$"), + DaplinkBoard.KEY_MODE: re.compile("(interface|bootloader)"), + } + optional_key_and_format = { + DaplinkBoard.KEY_BL_VERSION: re.compile("^[0-9]{4}$"), + DaplinkBoard.KEY_IF_VERSION: re.compile("^[0-9]{4}$"), + DaplinkBoard.KEY_BL_CRC: re.compile("^0x[a-f0-9]{8}$"), + DaplinkBoard.KEY_IF_CRC: re.compile("^0x[a-f0-9]{8}$"), + } + # 1. keys and values are alphanumeric + # 2. no duplicate keys + # 3. format is key : value + # 4. required keys are present + # 5. optional keys have the expected format + details_txt_path = self.get_file_path("details.txt") + details_txt = _parse_kvp_file(details_txt_path, test_info) + if not details_txt: + test_info.failure("Could not parse details.txt") + return + + # Check for required keys + for key in required_key_and_format: + if key not in details_txt: + test_info.failure("Missing detail.txt entry: %s" % key) + continue + + value = details_txt[key] + pattern = required_key_and_format[key] + if pattern.match(value) is None: + test_info.failure("Bad format detail.txt %s: %s" % + (key, value)) + + # Check format of optional values + for key in optional_key_and_format: + if key not in details_txt: + continue + + value = details_txt[key] + pattern = optional_key_and_format[key] + if pattern.match(value) is None: + test_info.failure("Bad format detail.txt %s: %s" % + (key, value)) + + # Check details.txt contents + details_unique_id = None + details_hic_id = None + if DaplinkBoard.KEY_UNIQUE_ID in details_txt: + details_unique_id = details_txt[DaplinkBoard.KEY_UNIQUE_ID] + if DaplinkBoard.KEY_HIC_ID in details_txt: + details_hic_id = details_txt[DaplinkBoard.KEY_HIC_ID] + if details_unique_id is not None: + if details_unique_id != self.unique_id: + test_info.failure("Unique ID mismatch in details.txt " + "details.txt=%s, usb=%s" % + (details_unique_id, self.unique_id)) + if details_hic_id is not None: + usb_hic = details_unique_id[-8:] + if details_hic_id != usb_hic: + test_info.failure("HIC ID is not the last 8 " + "digits of unique ID " + "details.txt=%s, usb=%s" % + (details_hic_id, usb_hic)) + + def _parse_assert_txt(self): + file_path = self.get_file_path("ASSERT.TXT") + if not os.path.isfile(file_path): + self._assert = None + return + + assert_table = _parse_kvp_file(file_path) + assert "file" in assert_table + assert "line" in assert_table + + self._assert = AssertInfo(assert_table["file"], assert_table['line']) diff --git a/test/daplink_firmware.py b/test/bundle.py similarity index 56% rename from test/daplink_firmware.py rename to test/bundle.py index e2e5f2357..b710caf75 100644 --- a/test/daplink_firmware.py +++ b/test/bundle.py @@ -1,6 +1,6 @@ # # DAPLink Interface Firmware -# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved +# Copyright (c) 2009-2021, Arm Limited, All Rights Reserved # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -15,12 +15,9 @@ # See the License for the specific language governing permissions and # limitations under the License. # - -from __future__ import absolute_import + import os -import info -import re -import firmware +from firmware import DAPLinkFirmware def load_bundle_from_release(directory): @@ -37,7 +34,7 @@ def load_bundle_from_project(tool='uvision'): """ progen_toolchains = ['make_gcc_arm', 'make_armclang', 'make_armcc', 'cmake_gcc_arm', 'cmake_armclang', 'cmake_armcc'] - assert (tool in progen_toolchains or tool == 'uvision' or tool == 'mbedcli'), 'Input tool %s is not supported' % (tool) + assert (tool in progen_toolchains or tool == 'uvision' or tool == 'mbedcli'), 'Input tool %s is not supported' % (tool) self_path = os.path.abspath(__file__) test_dir = os.path.dirname(self_path) @@ -55,7 +52,24 @@ def load_bundle_from_project(tool='uvision'): return ProjectFirmwareBundle(project_dir, build_folder) -class ReleaseFirmwareBundle(firmware.FirmwareBundle): +class FirmwareBundle(object): + + def get_firmware_list(self): + """Return the firmware objects associated with this bundle""" + raise NotImplementedError() + + @property + def build_sha(self): + """The GIT SHA this build was created at as a string or None""" + raise NotImplementedError() + + @property + def build_local_mods(self): + """True if this was a clean build, False otherwise""" + raise NotImplementedError() + + +class ReleaseFirmwareBundle(FirmwareBundle): """Class to abstract access a formal build as a bundle""" def __init__(self, directory): @@ -86,18 +100,18 @@ def build_local_mods(self): raise NotImplementedError() -class ProjectFirmwareBundle(firmware.FirmwareBundle): +class ProjectFirmwareBundle(FirmwareBundle): """Class to abstract access to daplink's build directory as a bundle""" def __init__(self, project_dir, build_folder): if not os.path.exists(project_dir): - print ("Error: DAPLink project folder %s missing" % project_dir) + print("Error: DAPLink project folder %s missing" % project_dir) exit(-1) project_dir_list = os.listdir(project_dir) if not project_dir_list: - print ("Error: DAPLink projects not build yet at %s" % project_dir) + print("Error: DAPLink projects not build yet at %s" % project_dir) exit(-1) firmware_list = [] @@ -119,85 +133,3 @@ def build_sha(self): @property def build_local_mods(self): raise NotImplementedError() - - -class DAPLinkFirmware(firmware.Firmware): - """Class to abstract access to a daplink firmware image""" - - _IF_RE = re.compile("^([a-z0-9]+)([_a-z0-9]*)_if$") - _BL_RE = re.compile("^([a-z0-9]+)_bl$") - - def __init__(self, name, bundle, directory): - self._name = name - self._bundle = bundle - self._directory = directory - self._valid = False - - # Set type - self._type = None - string_hic = None - match = self._IF_RE.match(name) - if match: - string_hic = match.group(1) - self._type = self.TYPE.INTERFACE - match = self._BL_RE.match(name) - if match: - string_hic = match.group(1) - self._type = self.TYPE.BOOTLOADER - if self._type is None: - assert False, 'Bad project name "%s"' % name - - # Set HIC - assert string_hic in info.HIC_STRING_TO_ID, 'Unknown HIC "%s" must ' \ - 'be added to HIC_STRING_TO_ID in info.py' % string_hic - self._hic_id = info.HIC_STRING_TO_ID[string_hic] - - # Check firmware name and type - assert self._type in self.TYPE, "Invalid type %s" % self._type - if self._type is self.TYPE.INTERFACE: - if name not in info.FIRMWARE_SET: - print('Warning: board "%s" no entry in SUPPORTED_CONFIGURATIONS in info.py' % name) - - # Set file paths - self._bin_path = self._directory + os.sep + '%s_crc.bin' % name - self._hex_path = self._directory + os.sep + '%s_crc.hex' % name - self._bin_path = os.path.abspath(self._bin_path) - self._hex_path = os.path.abspath(self._hex_path) - if not os.path.isfile(self._bin_path): - return # Failure - if not os.path.isfile(self._hex_path): - return # Failure - - self._valid = True - - def __str__(self): - return "Name=%s" % (self.name) - - @property - def valid(self): - """Set to True if the firmware is valid""" - return self._valid - - @property - def name(self): - return self._name - - @property - def hic_id(self): - return self._hic_id - - @property - def type(self): - return self._type - - @property - def bin_path(self): - return self._bin_path - - @property - def hex_path(self): - return self._hex_path - - @property - def elf_path(self): - return self._elf_path diff --git a/test/daplink_board.py b/test/daplink_board.py deleted file mode 100644 index 37fa799f1..000000000 --- a/test/daplink_board.py +++ /dev/null @@ -1,727 +0,0 @@ -# -# DAPLink Interface Firmware -# Copyright (c) 2009-2016, ARM Limited, All Rights Reserved -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); you may -# not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# - -from __future__ import absolute_import - -import os -import re -import time -import subprocess -import sys -import binascii -import itertools -import mbed_lstools -import info -import test_daplink -from test_info import TestInfoStub, TestInfo -from intelhex import IntelHex -from pyocd.core.helpers import ConnectHelper - -FILE_IGNORE_PATTERN_LIST = [ - re.compile("\\._\\.Trashes") -] - - -# This prevents the following error message from getting -# displayed on windows if the mbed dismounts unexpectedly -# during a transfer: -# There is no disk in the drive. Please insert a disk into -# drive \Device\\ -def disable_popup(): - if sys.platform.startswith("win"): - # pylint: disable=invalid-name - import ctypes - SEM_FAILCRITICALERRORS = 1 - GetErrorMode = \ - ctypes.windll.kernel32.GetErrorMode # @UndefinedVariable - GetErrorMode.restype = ctypes.c_uint - GetErrorMode.argtypes = [] - SetErrorMode = \ - ctypes.windll.kernel32.SetErrorMode # @UndefinedVariable - SetErrorMode.restype = ctypes.c_uint - SetErrorMode.argtypes = [ctypes.c_uint] - - err_mode = GetErrorMode() - err_mode |= SEM_FAILCRITICALERRORS - SetErrorMode(err_mode) - -disable_popup() - - -def get_all_attached_daplink_boards(): - all_boards = [] - lstools = mbed_lstools.create() - mbed_list = lstools.list_mbeds() - for mbed in mbed_list: - unique_id = mbed['target_id'] - board = DaplinkBoard(unique_id) - if board._mode is not None: #Valid daplink should have set this mode - all_boards.append(board) - else: - print("Warning: DAPLink tests cannot be done on board %s" % board.unique_id) - return all_boards - - -def _unique_id_to_host_id(unique_id): - """Return the chip id unique to the daplink host procesor - - Unique ID has the following fomat - Board ID - 4 bytes - Version - 4 bytes - Host ID - Everything else - """ - return unique_id[8:8 + 32] - - -def _get_board_endpoints(unique_id): - """Return a tuple of unique_id, serial_port, mount_point""" - lstools = mbed_lstools.create() - mbed_list = lstools.list_mbeds() - - host_id = _unique_id_to_host_id(unique_id) - for mbed in mbed_list: - mbed_unique_id = mbed['target_id'] - mbed_serial_port = mbed['serial_port'] - mbed_mount_point = mbed['mount_point'] - mbed_host_id = _unique_id_to_host_id(mbed_unique_id) - if mbed_host_id == host_id: - return mbed_unique_id, mbed_serial_port, mbed_mount_point - return None - - -def _ranges(i): - for _, b in itertools.groupby(enumerate(i), lambda x_y: x_y[1] - x_y[0]): - b = list(b) - yield b[0][1], b[-1][1] - - -def _parse_kvp_file(file_path, parent_test=None): - """Parse details.txt and return True if successful""" - test_info = None - kvp = {} - if parent_test is not None: - test_info = parent_test.create_subtest('parse_kvp_file') - line_format = re.compile("^([a-zA-Z0-9 ]+): +(.+)$") - if not os.path.isfile(file_path): - return kvp - - with open(file_path, "r") as file_handle: - for line in file_handle: - if len(line) <= 0: - if test_info is not None: - test_info.failure("Empty line in %s" % file_path) - continue - - if line[0] == '#': - # The line is a comment - continue - - match = line_format.match(line) - if match is None: - if test_info is not None: - test_info.failure("Invalid line: %s" % line) - continue - - key = match.group(1) - key = key.lower().replace(" ", "_") - value = match.group(2) - value = value.lower() - value = value.strip() - if key in kvp: - if test_info is not None: - test_info.failure("Duplicate key %s" % key) - continue - kvp[key] = value - return kvp - - -def _compute_crc(hex_file_path): - # Read in hex file - new_hex_file = IntelHex() - new_hex_file.padding = 0xFF - new_hex_file.fromfile(hex_file_path, format='hex') - - # Get the starting and ending address - addresses = new_hex_file.addresses() - addresses.sort() - start_end_pairs = list(_ranges(addresses)) - regions = len(start_end_pairs) - assert regions == 1, ("Error - only 1 region allowed in " - "hex file %i found." % regions) - start, end = start_end_pairs[0] - - # Compute checksum over the range (don't include data at location of crc) - size = end - start + 1 - crc_size = size - 4 - data = new_hex_file.tobinarray(start=start, size=crc_size) - data_crc32 = binascii.crc32(data) & 0xFFFFFFFF - - # Grab the crc from the image - embedded_crc32 = (((new_hex_file[end - 3] & 0xFF) << 0) | - ((new_hex_file[end - 2] & 0xFF) << 8) | - ((new_hex_file[end - 1] & 0xFF) << 16) | - ((new_hex_file[end - 0] & 0xFF) << 24)) - return data_crc32, embedded_crc32 - - -def _run_chkdsk(drive): - args = ["chkdsk", drive] - process = subprocess.Popen(args, stdin=subprocess.PIPE, - stdout=subprocess.PIPE, - stderr=subprocess.PIPE) - process.communicate(input=bytearray('n\r\n',encoding='ascii')) # Answer no if prompted - process.wait() - return process.returncode - - -class AssertInfo(object): - - def __init__(self, file_name, line_number): - self._file = file_name - self._line = line_number - - @property - def file(self): - return self._file - - @property - def line(self): - return self._line - - -class DaplinkBoard(object): - - MODE_IF = "interface" - MODE_BL = "bootloader" - - # Keys for details.txt - KEY_UNIQUE_ID = "unique_id" - KEY_HIC_ID = "hic_id" - KEY_MODE = "daplink_mode" - KEY_BL_VERSION = "bootloader_version" - KEY_IF_VERSION = "interface_version" - KEY_GIT_SHA = "git_sha" - KEY_LOCAL_MODS = "local_mods" - KEY_USB_INTERFACES = "usb_interfaces" - KEY_BL_CRC = "bootloader_crc" - KEY_IF_CRC = "interface_crc" - KEY_REMOUNT_COUNT = "remount_count" - - def __init__(self, unique_id): - - self.unique_id = unique_id - self.details_txt = None - self._mode = None - self._remount_count = None - self._assert = None - self._check_fs_on_remount = False - self._manage_assert = False - self.update_board_info() - - def __str__(self): - return "Name=%s Unique ID=%s" % (self.name, self.get_unique_id()) - - def get_unique_id(self): - return self.unique_id - - def get_board_id(self): - return self.board_id - - @property - def hic_id(self): - return self._hic_id - - @property - def name(self): - if self.board_id in info.BOARD_ID_TO_BUILD_TARGET: - board_target = info.BOARD_ID_TO_BUILD_TARGET[self.board_id] - else: - board_target = "Unknown" - return board_target - - def get_serial_port(self): - return self.serial_port - - def get_mount_point(self): - return self.mount_point - - def get_connected(self): - """Check if the board is connected""" - return os.path.isdir(self.mount_point) - - def get_failure_message_and_type(self): - """Get the failure message and types from fail.txt - - return None if there there is no failure - """ - error = None - error_type = None - fail_file = self.get_file_path('FAIL.TXT') - if not self.get_connected(): - raise Exception('Board not connected') - if os.path.isfile(fail_file): - with open(fail_file, 'r') as fail_file_handle: - msg = fail_file_handle.read() - lines = msg.splitlines() - if len(lines) == 2: - if lines[0].startswith('error: '): - error = lines[0][7:] - else: - raise Exception('Can not parse error line in FAIL.TXT') - if lines[1].startswith('type: '): - error_type = lines[1][6:] - else: - raise Exception('Can not parse type line in FAIL.TXT') - else: - raise Exception('Wrong number of lines in FAIL.TXT, expected: 2') - return error, error_type - - def get_assert_info(self): - """Return an AssertInfo if an assert occurred, else None""" - return self._assert - - def get_mode(self): - """Return either MODE_IF or MODE_BL""" - assert ((self._mode is DaplinkBoard.MODE_BL) or - (self._mode is DaplinkBoard.MODE_IF)) - return self._mode - - def get_file_path(self, file_name): - """Convenience function to the path to a file on the drive""" - return os.path.normpath(self.mount_point + os.sep + file_name) - - def refresh(self, parent_test): - """Remount driver to get updated contents""" - refresh_filename = self.get_file_path('REFRESH.ACT') - with open(refresh_filename, 'wb') as _: - pass - self.wait_for_remount(parent_test) - - def set_mode(self, mode, parent_test=None): - """Set the mode to either MODE_IF or MODE_BL""" - assert ((mode is DaplinkBoard.MODE_BL) or - (mode is DaplinkBoard.MODE_IF)) - if parent_test is None: - parent_test = TestInfoStub() - test_info = parent_test.create_subtest('set_mode') - current_mode = self.get_mode() - if current_mode is mode: - # No mode change needed - return - - if mode is self.MODE_BL: - test_info.info("changing mode IF -> BL") - # Create file to enter BL mode - start_bl_path = self.get_file_path('START_BL.ACT') - with open(start_bl_path, 'wb') as _: pass - elif mode is self.MODE_IF: - test_info.info("changing mode BL -> IF") - # Create file to enter IF mode - start_if_path = self.get_file_path('START_IF.ACT') - with open(start_if_path, 'wb') as _: pass - else: - test_info.warning("Board is in unknown mode") - self.wait_for_remount(test_info) - - new_mode = self.get_mode() - if new_mode != mode: - test_info.failure("Board in wrong mode: %s" % new_mode) - raise Exception("Could not change board mode") - - def set_check_fs_on_remount(self, enabled): - assert isinstance(enabled, bool) - self._check_fs_on_remount = enabled - self.set_assert_auto_manage(enabled) - - def set_assert_auto_manage(self, enabled): - assert isinstance(enabled, bool) - self.clear_assert() - self._manage_assert = enabled - - def clear_assert(self): - assert_path = self.get_file_path("ASSERT.TXT") - if os.path.isfile(assert_path): - os.remove(assert_path) - self.wait_for_remount(TestInfoStub()) - - def run_board_test(self, parent_test): - test_daplink.daplink_test(self, parent_test) - - def read_target_memory(self, addr, size, resume=True): - assert self.get_mode() == self.MODE_IF - with ConnectHelper.session_with_chosen_probe(unique_id=self.get_unique_id(), - resume_on_disconnect=resume) as session: - data = session.target.read_memory_block8(addr, size) - return bytearray(data) - - def test_fs(self, parent_test): - """Check if the raw filesystem is valid""" - if sys.platform.startswith("win"): - test_info = parent_test.create_subtest('test_fs') - returncode = _run_chkdsk(self.mount_point) - test_info.info('chkdsk returned %s' % returncode) - if returncode != 0: - test_info.failure('Disk corrupt') - - # Windows 8/10 workaround - rerun chkdsk until disk caching is on - # Notes about this problem: - # - This is less likely to occur when the "storage" service is - # turned off and/or you are running as administrator - # - When creating a directory with os.mkdir the - # following error occurs: "WindowsError: [Error 1392] The - # file or directory is corrupted and unreadable: ''" - # - When creating a file with open(, "wb") the - # following error occurs: "OError: [Errno 22] invalid - # mode ('wb') or filename: ''" - # - When a file or directory is created on the drive in explorer - # and you preform a refresh, the newly created file or - # directory disappears - persist_test_dir = self.get_file_path("persist_test_dir") - for _ in range(10): - try: - os.mkdir(persist_test_dir) - except EnvironmentError as exception: - test_info.info("cache check exception %s" % exception) - if os.path.exists(persist_test_dir): - os.rmdir(persist_test_dir) - break - test_info.info("running checkdisk to re-enable caching") - _run_chkdsk(self.mount_point) - else: - raise Exception("Unable to re-enable caching") - - # TODO - as a future improvement add linux and mac support - - # Tests for the following: - # 1. Correct files present -TODO - # 2. Contents of file are valid ascii - # 3. Each line ends with \r\n - # 4. There is no whitespace at the end of the line - # 5. Each file ends with \r\n - def test_fs_contents(self, parent_test): - """Check if the file contents are valid""" - test_info = parent_test.create_subtest('test_fs_contents') - non_ascii = b'[^\x20-\x7F\r\n]' - non_cr_lf = b'\r[^\n]|[^\r]\n' - trail_white = b'(?:\ \r|\ \n)' - end_of_file = b'\r\n$' - files = os.listdir(self.mount_point) - non_ascii_re = re.compile(non_ascii) - non_cr_lf_re = re.compile(non_cr_lf) - trail_white_re = re.compile(trail_white) - end_of_file_re = re.compile(end_of_file) - for filename in files: - filepath = self.get_file_path(filename) - if not os.path.isfile(filepath): - test_info.info("Skipping non file item %s" % filepath) - continue - skip = False - for pattern in FILE_IGNORE_PATTERN_LIST: - if pattern.match(filename): - skip = True - break - if skip: - continue - - with open(filepath, 'rb') as file_handle: - file_contents = file_handle.read() - if non_ascii_re.search(file_contents): - test_info.failure("Non ascii characters in %s" % filepath) - elif non_cr_lf_re.search(file_contents): - test_info.failure("File has non-standard line endings %s" % - filepath) - elif trail_white_re.search(file_contents): - test_info.warning("File trailing whitespace %s" % - filepath) - elif end_of_file_re.search(file_contents) is None: - test_info.warning("No newline at end of file %s" % - filepath) - else: - test_info.info("File %s valid" % filepath) - - self.test_details_txt(test_info) - - def load_interface(self, filepath, parent_test): - """Load an interface binary or hex""" - assert isinstance(filepath, str), "Invalid bootloader image!" - assert isinstance(parent_test, TestInfo), "Invalid parent test object!" - - test_info = parent_test.create_subtest('load_interface') - self.set_mode(self.MODE_BL, test_info) - - data_crc, crc_in_image = _compute_crc(filepath) - assert data_crc == crc_in_image, ("CRC in interface is wrong " - "expected 0x%x, found 0x%x" % - (data_crc, crc_in_image)) - - filename = os.path.basename(filepath) - with open(filepath, 'rb') as firmware_file: - data = firmware_file.read() - out_file = self.get_file_path(filename) - start = time.time() - with open(out_file, 'wb') as firmware_file: - firmware_file.write(data) - stop = time.time() - test_info.info("programming took %s s" % (stop - start)) - self.wait_for_remount(test_info) - - # Check the CRC - self.set_mode(self.MODE_IF, test_info) - if DaplinkBoard.KEY_IF_CRC not in self.details_txt: - test_info.failure("No interface CRC in details.txt") - return - details_crc = int(self.details_txt[DaplinkBoard.KEY_IF_CRC], 0) - test_info.info("Interface crc: 0x%x" % details_crc) - if data_crc != details_crc: - test_info.failure("Interface CRC is wrong") - - def load_bootloader(self, filepath, parent_test): - """Load a bootloader binary or hex""" - assert isinstance(filepath, str), "Invalid bootloader image!" - assert isinstance(parent_test, TestInfo), "Invalid parent test object!" - - test_info = parent_test.create_subtest('load_bootloader') - self.set_mode(self.MODE_IF, test_info) - - # Check image CRC - data_crc, crc_in_image = _compute_crc(filepath) - assert data_crc == crc_in_image, ("CRC in bootloader is wrong " - "expected 0x%x, found 0x%x" % - (data_crc, crc_in_image)) - - filename = os.path.basename(filepath) - with open(filepath, 'rb') as firmware_file: - data = firmware_file.read() - out_file = self.get_file_path(filename) - start = time.time() - with open(out_file, 'wb') as firmware_file: - firmware_file.write(data) - stop = time.time() - test_info.info("programming took %s s" % (stop - start)) - self.wait_for_remount(test_info) - - # Check the CRC - self.set_mode(self.MODE_IF, test_info) - if DaplinkBoard.KEY_BL_CRC not in self.details_txt: - test_info.failure("No bootloader CRC in details.txt") - return - details_crc = int(self.details_txt[DaplinkBoard.KEY_BL_CRC], 0) - test_info.info("Bootloader crc: 0x%x" % details_crc) - if data_crc != details_crc: - test_info.failure("Bootloader CRC is wrong") - - def wait_for_remount(self, parent_test, wait_time=600): - mode = self._mode - count = self._remount_count - test_info = parent_test.create_subtest('wait_for_remount') - - elapsed = 0 - start = time.time() - remounted = False - while os.path.isdir(self.mount_point): - if self.update_board_info(False): #check info if it is already mounted - if mode is not None and self._mode is not None and mode is not self._mode: - remounted = True - test_info.info("already remounted with change mode") - break - elif count is not None and self._remount_count is not None and count != self._remount_count: - remounted = True - test_info.info("already remounted with change mount count") - break - if elapsed > wait_time: - raise Exception("Dismount timed out") - time.sleep(0.1) - elapsed += 0.2 - else: - stop = time.time() - test_info.info("unmount took %s s" % (stop - start)) - elapsed = 0 - start = time.time() - - while not remounted: - if self.update_board_info(False): - if os.path.isdir(self.mount_point): - # Information returned by mbed-ls could be old. - # Only break from the loop if the second call to - # mbed-ls returns the same mount point. - tmp_mount = self.mount_point - if self.update_board_info(False): - if tmp_mount == self.mount_point: - break - if elapsed > wait_time: - raise Exception("Mount timed out") - time.sleep(0.1) - elapsed += 0.1 - stop = time.time() - test_info.info("mount took %s s" % (stop - start)) - - if count is not None and self._remount_count is not None: - expected_count = (0 if mode is not self._mode - else (count + 1) & 0xFFFFFFFF) - if expected_count != self._remount_count: - test_info.failure('Expected remount count of %s got %s' % - (expected_count, self._remount_count)) - - # If enabled check the filesystem - if self._check_fs_on_remount: - self.test_fs(parent_test) - self.test_fs_contents(parent_test) - self.test_details_txt(parent_test) - if self._manage_assert: - if self._assert is not None: - test_info.failure('Assert on line %s in file %s' % - (self._assert.line, self._assert.file)) - self.clear_assert() - - def update_board_info(self, exptn_on_fail=True): - """Update board info - - Update all board information variables that could - change when remounting or changing modes. - Note - before this function is set self.unique_id - must be set. - """ - - try: - endpoints = _get_board_endpoints(self.unique_id) - if endpoints is None: - if exptn_on_fail: - raise Exception("Could not update board info: %s" % - self.unique_id) - return False - self.unique_id, self.serial_port, self.mount_point = endpoints - # Serial port can be missing - if self.unique_id is None: - if exptn_on_fail: - raise Exception("Mount point is null") - return False - if self.mount_point is None: - if exptn_on_fail: - raise Exception("Mount point is null") - return False - self.board_id = int(self.unique_id[0:4], 16) - self._hic_id = int(self.unique_id[-8:], 16) - - # Note - Some legacy boards might not have details.txt - details_txt_path = self.get_file_path("details.txt") - self.details_txt = _parse_kvp_file(details_txt_path) - self._parse_assert_txt() - - self._remount_count = None - if DaplinkBoard.KEY_REMOUNT_COUNT in self.details_txt: - self._remount_count = int(self.details_txt[DaplinkBoard.KEY_REMOUNT_COUNT]) - self._mode = None - if DaplinkBoard.KEY_MODE in self.details_txt: - DETAILS_TO_MODE = { - "interface": DaplinkBoard.MODE_IF, - "bootloader": DaplinkBoard.MODE_BL, - } - mode_str = self.details_txt[DaplinkBoard.KEY_MODE] - self._mode = DETAILS_TO_MODE[mode_str] - else: - #check for race condition here - return False - return True - except Exception as e: - if exptn_on_fail: - raise e - else: - return False - - def test_details_txt(self, parent_test): - """Check that details.txt has all requied fields""" - test_info = parent_test.create_subtest('test_details_txt') - required_key_and_format = { - DaplinkBoard.KEY_UNIQUE_ID: re.compile("^[a-f0-9]{48}$"), - DaplinkBoard.KEY_HIC_ID: re.compile("^[a-f0-9]{8}$"), - DaplinkBoard.KEY_GIT_SHA: re.compile("^[a-f0-9]{40}$"), - DaplinkBoard.KEY_LOCAL_MODS: re.compile("^[01]{1}$"), - DaplinkBoard.KEY_USB_INTERFACES: re.compile("^.+$"), - DaplinkBoard.KEY_MODE: re.compile("(interface|bootloader)"), - } - optional_key_and_format = { - DaplinkBoard.KEY_BL_VERSION: re.compile("^[0-9]{4}$"), - DaplinkBoard.KEY_IF_VERSION: re.compile("^[0-9]{4}$"), - DaplinkBoard.KEY_BL_CRC: re.compile("^0x[a-f0-9]{8}$"), - DaplinkBoard.KEY_IF_CRC: re.compile("^0x[a-f0-9]{8}$"), - } - # 1. keys and values are alphanumeric - # 2. no duplicate keys - # 3. format is key : value - # 4. required keys are present - # 5. optional keys have the expected format - details_txt_path = self.get_file_path("details.txt") - details_txt = _parse_kvp_file(details_txt_path, test_info) - if not details_txt: - test_info.failure("Could not parse details.txt") - return - - # Check for required keys - for key in required_key_and_format: - if key not in details_txt: - test_info.failure("Missing detail.txt entry: %s" % key) - continue - - value = details_txt[key] - pattern = required_key_and_format[key] - if pattern.match(value) is None: - test_info.failure("Bad format detail.txt %s: %s" % - (key, value)) - - # Check format of optional values - for key in optional_key_and_format: - if key not in details_txt: - continue - - value = details_txt[key] - pattern = optional_key_and_format[key] - if pattern.match(value) is None: - test_info.failure("Bad format detail.txt %s: %s" % - (key, value)) - - # Check details.txt contents - details_unique_id = None - details_hic_id = None - if DaplinkBoard.KEY_UNIQUE_ID in details_txt: - details_unique_id = details_txt[DaplinkBoard.KEY_UNIQUE_ID] - if DaplinkBoard.KEY_HIC_ID in details_txt: - details_hic_id = details_txt[DaplinkBoard.KEY_HIC_ID] - if details_unique_id is not None: - if details_unique_id != self.unique_id: - test_info.failure("Unique ID mismatch in details.txt " - "details.txt=%s, usb=%s" % - (details_unique_id, self.unique_id)) - if details_hic_id is not None: - usb_hic = details_unique_id[-8:] - if details_hic_id != usb_hic: - test_info.failure("HIC ID is not the last 8 " - "digits of unique ID " - "details.txt=%s, usb=%s" % - (details_hic_id, usb_hic)) - - def _parse_assert_txt(self): - file_path = self.get_file_path("ASSERT.TXT") - if not os.path.isfile(file_path): - self._assert = None - return - - assert_table = _parse_kvp_file(file_path) - assert "file" in assert_table - assert "line" in assert_table - - self._assert = AssertInfo(assert_table["file"], assert_table['line']) diff --git a/test/firmware.py b/test/firmware.py index bb4e5da38..b7b089aa2 100644 --- a/test/firmware.py +++ b/test/firmware.py @@ -15,26 +15,12 @@ # See the License for the specific language governing permissions and # limitations under the License. # - + from __future__ import absolute_import from enum import Enum - - -class FirmwareBundle(object): - - def get_firmware_list(self): - """Return the firmware objects associated with this bundle""" - raise NotImplementedError() - - @property - def build_sha(self): - """The GIT SHA this build was created at as a string or None""" - raise NotImplementedError() - - @property - def build_local_mods(self): - """True if this was a clean build, False otherwise""" - raise NotImplementedError() +import os +import info +import re class Firmware(object): @@ -77,3 +63,85 @@ def hex_path(self): def elf_path(self): """Path to the hex vesion of this firmware or None""" raise NotImplementedError() + + +class DAPLinkFirmware(Firmware): + """Class to abstract access to a daplink firmware image""" + + _IF_RE = re.compile("^([a-z0-9]+)([_a-z0-9]*)_if$") + _BL_RE = re.compile("^([a-z0-9]+)_bl$") + + def __init__(self, name, bundle, directory): + self._name = name + self._bundle = bundle + self._directory = directory + self._valid = False + + # Set type + self._type = None + string_hic = None + match = self._IF_RE.match(name) + if match: + string_hic = match.group(1) + self._type = self.TYPE.INTERFACE + match = self._BL_RE.match(name) + if match: + string_hic = match.group(1) + self._type = self.TYPE.BOOTLOADER + if self._type is None: + assert False, 'Bad project name "%s"' % name + + # Set HIC + assert string_hic in info.HIC_STRING_TO_ID, 'Unknown HIC "%s" must ' \ + 'be added to HIC_STRING_TO_ID in info.py' % string_hic + self._hic_id = info.HIC_STRING_TO_ID[string_hic] + + # Check firmware name and type + assert self._type in self.TYPE, "Invalid type %s" % self._type + if self._type is self.TYPE.INTERFACE: + if name not in info.FIRMWARE_SET: + print('Warning: board "%s" no entry in SUPPORTED_CONFIGURATIONS in info.py' % name) + + # Set file paths + self._bin_path = self._directory + os.sep + '%s_crc.bin' % name + self._hex_path = self._directory + os.sep + '%s_crc.hex' % name + self._bin_path = os.path.abspath(self._bin_path) + self._hex_path = os.path.abspath(self._hex_path) + if not os.path.isfile(self._bin_path): + return # Failure + if not os.path.isfile(self._hex_path): + return # Failure + + self._valid = True + + def __str__(self): + return "Name=%s" % (self.name) + + @property + def valid(self): + """Set to True if the firmware is valid""" + return self._valid + + @property + def name(self): + return self._name + + @property + def hic_id(self): + return self._hic_id + + @property + def type(self): + return self._type + + @property + def bin_path(self): + return self._bin_path + + @property + def hex_path(self): + return self._hex_path + + @property + def elf_path(self): + return self._elf_path diff --git a/test/run_test.py b/test/run_test.py index 3610fdfab..a8422a2c7 100644 --- a/test/run_test.py +++ b/test/run_test.py @@ -67,17 +67,17 @@ import argparse import subprocess from enum import Enum -from hid_test import test_hid -from serial_test import test_serial -from msd_test import test_mass_storage -from usb_test import test_usb -from daplink_board import get_all_attached_daplink_boards +from tests.test_hid import test_hid +from tests.test_serial import test_serial +from tests.test_msd import test_mass_storage +from tests.test_usb import test_usb +from board import get_all_attached_daplink_boards from project_generator.generate import Generator from test_info import TestInfo -from daplink_firmware import load_bundle_from_project, load_bundle_from_release +from bundle import load_bundle_from_release, load_bundle_from_project from firmware import Firmware from target import load_target_bundle, build_target_bundle -from test_daplink import daplink_test +from tests.test_daplink import daplink_test import info DEFAULT_TEST_DIR = './test_results' @@ -226,7 +226,7 @@ def run_tests(self): test_configuration.bl_firmware) test_info.info("Target: %s" % test_configuration.target) - + if self._load_if: if_path = test_configuration.if_firmware.hex_path board.load_interface(if_path, test_info) @@ -587,7 +587,7 @@ def main(): print(" images can be built with the RESTful Compile API.") print("NOTE: you can skip the endpoint tests altogether ") print("with --notestendpt") - + exit(-1) if args.targetdir is not None: diff --git a/test/test_info.py b/test/test_info.py index f959ea095..2f39e2491 100644 --- a/test/test_info.py +++ b/test/test_info.py @@ -15,7 +15,7 @@ # See the License for the specific language governing permissions and # limitations under the License. # - + from __future__ import absolute_import from __future__ import print_function import six @@ -185,5 +185,6 @@ def create_subtest(self, name): def _print_msg(msg): print(get_timestamp_tag() + "%s"%(msg,)) + def get_timestamp_tag(): return "[{:0<17f}] ".format(time.time()) diff --git a/test/test_daplink.py b/test/tests/test_daplink.py similarity index 99% rename from test/test_daplink.py rename to test/tests/test_daplink.py index c9836159d..89a3a43a1 100644 --- a/test/test_daplink.py +++ b/test/tests/test_daplink.py @@ -28,8 +28,8 @@ except ImportError: from io import StringIO -from msd_test import (MassStorageTester, MOCK_DIR_LIST, MOCK_FILE_LIST, - MOCK_DIR_LIST_AFTER, MOCK_FILE_LIST_AFTER) +from tests.test_msd import (MassStorageTester, MOCK_DIR_LIST, MOCK_FILE_LIST, + MOCK_DIR_LIST_AFTER, MOCK_FILE_LIST_AFTER) TRIGGER_ASSERT_FILE_NAME = "ASSERT.ACT" ASSERT_FILE_NAME = "ASSERT.TXT" @@ -135,7 +135,7 @@ def daplink_test(workspace, parent_test): len(section_list)) start, length = section_list[0] - bin_data = bytearray(intel_hex.tobinarray(start=start, size=length)) + bin_data = bytearray(intel_hex.tobinarray(start=start, size=length)) sio = StringIO() intel_hex.tofile(sio, format='hex') hex_data = sio.getvalue() diff --git a/test/hid_test.py b/test/tests/test_hid.py similarity index 100% rename from test/hid_test.py rename to test/tests/test_hid.py diff --git a/test/msd_test.py b/test/tests/test_msd.py similarity index 99% rename from test/msd_test.py rename to test/tests/test_msd.py index 2d6fbc0eb..6ddfc6d42 100644 --- a/test/msd_test.py +++ b/test/tests/test_msd.py @@ -29,6 +29,7 @@ from pyocd.core.helpers import ConnectHelper from pyocd.core.memory_map import MemoryType + def _same(d1, d2): assert type(d1) is bytearray assert type(d2) is bytearray @@ -39,6 +40,7 @@ def _same(d1, d2): return False return True + MOCK_DIR_LIST = [ "test", "blarg", @@ -65,6 +67,7 @@ def _same(d1, d2): ("file2.jpg", "file contents here") ] + class MassStorageTester(object): RETRY_COUNT = 5 diff --git a/test/serial_test.py b/test/tests/test_serial.py similarity index 95% rename from test/serial_test.py rename to test/tests/test_serial.py index a5853276c..ed8164315 100644 --- a/test/serial_test.py +++ b/test/tests/test_serial.py @@ -28,7 +28,7 @@ def _same(d1, d2): - #Do a string or bytearray compare + #Do a string or bytearray compare if d1 != d2: return False return True @@ -43,7 +43,7 @@ def _same(d1, d2): #56000, #TODO - uncomment once daplink-validation supports 56000 on nrf5x 57600, 115200, - ] +] timing_test_baud = standard_baud[3:] @@ -65,7 +65,7 @@ class SerialTester(object): """Helper object to buffer serial and setup baud""" def __init__(self, port): - self.raw_serial = serial.Serial(port=port,bytesize=serial.EIGHTBITS, parity=serial.PARITY_NONE, stopbits=serial.STOPBITS_ONE, timeout=None, xonxoff=False, rtscts=False, write_timeout=None, dsrdtr=False, inter_byte_timeout=None, exclusive=None) + self.raw_serial = serial.Serial(port=port, bytesize=serial.EIGHTBITS, parity=serial.PARITY_NONE, stopbits=serial.STOPBITS_ONE, timeout=None, xonxoff=False, rtscts=False, write_timeout=None, dsrdtr=False, inter_byte_timeout=None, exclusive=None) self.raw_serial.write_timeout = ERROR_TIMEOUT_SECONDS self._queue = queue.Queue() self._write_thread = threading.Thread(target=self._serial_main) @@ -239,6 +239,10 @@ def test_serial(workspace, parent_test): test_info.info("fail size - %s" % data_size) break + # Break if already failed + if not test_pass: + break + if test_pass: test_info.info("Pass") else: diff --git a/test/usb_test.py b/test/tests/test_usb.py similarity index 98% rename from test/usb_test.py rename to test/tests/test_usb.py index 2e80976a6..e181b90df 100644 --- a/test/usb_test.py +++ b/test/tests/test_usb.py @@ -20,13 +20,14 @@ from __future__ import print_function import os +import sys import usb.core import functools import threading import time -from usb_cdc import USBCdc -from usb_hid import USBHid -from usb_msd import USBMsd, Fat +from tests.usb_cdc import USBCdc +from tests.usb_hid import USBHid +from tests.usb_msd import USBMsd, Fat DISMOUNT_TIME_S = 10.00 @@ -95,6 +96,8 @@ def test_usb(workspace, parent_test, force=False): def main(): """Run the usb test as a stand alone program""" + tests_dir = os.path.dirname(os.path.dirname(os.path.abspath(__file__))) + sys.path.append(tests_dir) import test_info import mock diff --git a/test/usb_cdc.py b/test/tests/usb_cdc.py similarity index 100% rename from test/usb_cdc.py rename to test/tests/usb_cdc.py diff --git a/test/usb_hid.py b/test/tests/usb_hid.py similarity index 100% rename from test/usb_hid.py rename to test/tests/usb_hid.py diff --git a/test/usb_msd.py b/test/tests/usb_msd.py similarity index 100% rename from test/usb_msd.py rename to test/tests/usb_msd.py From 63408ef213b4f527753d299973f20003c8763580 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 14 Jun 2021 23:42:08 -0500 Subject: [PATCH 204/617] run_test: add '--quick' flag that reduces the number of tests --- test/run_test.py | 20 +++++++++++--------- test/tests/test_daplink.py | 2 +- test/tests/test_hid.py | 2 +- test/tests/test_msd.py | 21 +++++++++++---------- test/tests/test_serial.py | 19 ++++++++++++------- test/tests/test_usb.py | 2 +- 6 files changed, 37 insertions(+), 29 deletions(-) diff --git a/test/run_test.py b/test/run_test.py index a8422a2c7..e2817652a 100644 --- a/test/run_test.py +++ b/test/run_test.py @@ -89,13 +89,13 @@ VERB_LEVELS = [VERB_MINIMAL, VERB_NORMAL, VERB_VERBOSE, VERB_ALL] -def test_endpoints(workspace, parent_test): +def test_endpoints(workspace, parent_test, quick=False): """Run tests to validate DAPLINK fimrware""" test_info = parent_test.create_subtest('test_endpoints') - test_hid(workspace, test_info) - test_serial(workspace, test_info) - test_mass_storage(workspace, test_info) - test_usb(workspace, test_info) + test_hid(workspace, test_info, quick) + test_serial(workspace, test_info, quick) + test_mass_storage(workspace, test_info, quick) + test_usb(workspace, test_info, False, quick) class TestConfiguration(object): @@ -207,7 +207,7 @@ def set_firmware_filter(self, name_list): assert self._firmware_filter is None self._firmware_filter = set(name_list) - def run_tests(self): + def run_tests(self, quick=False): """Run all configurations""" # Tests can only be run once per TestManager instance assert self._state is self._STATE.CONFIGURED @@ -239,10 +239,10 @@ def run_tests(self): board.set_check_fs_on_remount(True) if self._test_daplink: - daplink_test(test_configuration, test_info) + daplink_test(test_configuration, test_info, quick) if self._test_ep: - test_endpoints(test_configuration, test_info) + test_endpoints(test_configuration, test_info, quick) if test_info.get_failed(): all_tests_pass = False @@ -550,6 +550,8 @@ def main(): 'USB endpoints.', default=False, action='store_true') parser.add_argument('--loadbl', help='Load bootloader before test.', default=False, action='store_true') + parser.add_argument('--quick', help='Run shorter test sequences', + default=False, action='store_true') parser.add_argument('--testdl', help='Run DAPLink specific tests. ' 'The DAPLink test tests bootloader updates so use' 'with caution', @@ -686,7 +688,7 @@ def main(): exit(0) # Run tests - tester.run_tests() + tester.run_tests(args.quick) # Print test results tester.print_results(args.verbose) diff --git a/test/tests/test_daplink.py b/test/tests/test_daplink.py index 89a3a43a1..c42e50e1b 100644 --- a/test/tests/test_daplink.py +++ b/test/tests/test_daplink.py @@ -124,7 +124,7 @@ def _check_data_correct(self, expected_data, test_info): return actual_crc32 == expected_crc32 -def daplink_test(workspace, parent_test): +def daplink_test(workspace, parent_test, quick=False): board = workspace.board interface = workspace.if_firmware test_info = parent_test.create_subtest('daplink_test') diff --git a/test/tests/test_hid.py b/test/tests/test_hid.py index 8b382a986..81463d32d 100644 --- a/test/tests/test_hid.py +++ b/test/tests/test_hid.py @@ -35,7 +35,7 @@ # TODO - test ram/rom transfer speeds -def test_hid(workspace, parent_test): +def test_hid(workspace, parent_test, quick=False): test_info = parent_test.create_subtest("HID test") board = workspace.board with ConnectHelper.session_with_chosen_probe(unique_id=board.get_unique_id()) as session: diff --git a/test/tests/test_msd.py b/test/tests/test_msd.py index 6ddfc6d42..677f9dcf9 100644 --- a/test/tests/test_msd.py +++ b/test/tests/test_msd.py @@ -304,7 +304,7 @@ def _run(self, test_info): test_info.failure('Data does not match') -def test_mass_storage(workspace, parent_test): +def test_mass_storage(workspace, parent_test, quick=False): """Test the mass storage endpoint Requirements: @@ -346,7 +346,7 @@ def test_mass_storage(workspace, parent_test): test.run() # Test loading a binary file with flushes - if not bad_vector_table: + if not bad_vector_table and not quick: test = MassStorageTester(board, test_info, "Load binary with flushes") test.set_programming_data(bin_file_contents, 'image.bin') test.set_expected_data(bin_file_contents, start) @@ -360,14 +360,15 @@ def test_mass_storage(workspace, parent_test): test.run() # Test loading a hex file with flushes - test = MassStorageTester(board, test_info, "Load hex with flushes") - test.set_programming_data(hex_file_contents, 'image.hex') - test.set_expected_data(bin_file_contents, start) - test.set_flush_size(0x1000) - test.run() + if not quick: + test = MassStorageTester(board, test_info, "Load hex with flushes") + test.set_programming_data(hex_file_contents, 'image.hex') + test.set_expected_data(bin_file_contents, start) + test.set_flush_size(0x1000) + test.run() # Test loading a binary smaller than a sector - if not bad_vector_table: + if not bad_vector_table and not quick: test = MassStorageTester(board, test_info, "Load .bin smaller than sector") test_data_size = 0x789 test_data = bin_file_contents[0:0 + test_data_size] @@ -385,7 +386,7 @@ def test_mass_storage(workspace, parent_test): # Test loading a blank binary with a vector table but padded with 0xFF. # A blank image can lock some devices. - if not bad_vector_table: + if not bad_vector_table and not quick: test = MassStorageTester(board, test_info, "Load blank binary + vector table") test.set_programming_data(vectors_and_pad, 'image.bin') if locked_when_erased: @@ -408,7 +409,7 @@ def test_mass_storage(workspace, parent_test): # when a binary file is loaded, since there is no way to # tell where the end of the file is. - if page_erase_supported: + if page_erase_supported and not quick: # Test page erase, a.k.a. sector erase by generating iHex with discrete addresses, # programing the device then comparing device memory against expected content. test = MassStorageTester(board, test_info, "Sector Erase") diff --git a/test/tests/test_serial.py b/test/tests/test_serial.py index ed8164315..cfd6ce307 100644 --- a/test/tests/test_serial.py +++ b/test/tests/test_serial.py @@ -33,8 +33,9 @@ def _same(d1, d2): return False return True + # http://digital.ni.com/public.nsf/allkb/D37754FFA24F7C3F86256706005B9BE7 -standard_baud = [ +standard_test_baud_rates = [ 9600, 14400, 19200, @@ -44,7 +45,9 @@ def _same(d1, d2): 57600, 115200, ] -timing_test_baud = standard_baud[3:] +standard_timing_baud_rates = standard_test_baud_rates[3:] +quick_test_baud_rates = [9600, 115200] +quick_timing_baud_rates = [115200] def calc_timeout(length, baud): @@ -161,7 +164,7 @@ def _serial_main(self): self._queue.task_done() -def test_serial(workspace, parent_test): +def test_serial(workspace, parent_test, quick=False): """Test the serial port endpoint Requirements: @@ -183,13 +186,15 @@ def test_serial(workspace, parent_test): # whole time. Use the property 'baudrate' to change the baud # instead of opening a new instance. + test_baud_rates = quick_test_baud_rates if quick else standard_test_baud_rates + timing_baud_rates = quick_timing_baud_rates if quick else standard_timing_baud_rates with SerialTester(port) as sp: # Generate a 4KB block of dummy data # and test supported baud rates test_data = [i for i in range(0, 256)] * 4 * 4 test_data = bytearray(test_data) - for baud in standard_baud: + for baud in test_baud_rates: test_info.info("Testing baud %i" % baud) success = sp.new_session_with_baud(baud, test_info) @@ -215,7 +220,7 @@ def test_serial(workspace, parent_test): # 4. Read back all data test_data = [i for i in range(0, 256)] * 4 * 4 test_data = bytearray(test_data) - for baud in timing_test_baud: + for baud in timing_baud_rates: test_info.info("Timing test baud %i" % baud) success = sp.new_session_with_baud(baud, test_info) @@ -255,7 +260,7 @@ def test_serial(workspace, parent_test): test_data = bytearray(test_data) sp.new_session_with_baud(115200, test_info) sp.set_read_timeout(0) - for baud in standard_baud: + for baud in test_baud_rates: sp.raw_serial.baudrate = baud sp.write(test_data) xfer_time = float(len(test_data) * 10) / float(baud) @@ -266,7 +271,7 @@ def test_serial(workspace, parent_test): sp.flush() sp.raw_serial.baudrate = 115200 sp.set_read_timeout(1.0) - sp.read(128 * len(standard_baud)) + sp.read(128 * len(test_baud_rates)) # Generate a 8 KB block of dummy data # and test a large block transfer diff --git a/test/tests/test_usb.py b/test/tests/test_usb.py index e181b90df..206329842 100644 --- a/test/tests/test_usb.py +++ b/test/tests/test_usb.py @@ -32,7 +32,7 @@ DISMOUNT_TIME_S = 10.00 -def test_usb(workspace, parent_test, force=False): +def test_usb(workspace, parent_test, force=False, quick=False): """Run raw USB tests Requirements: From 9fadc935f81e33ebd25d53352b07c3b79104e780 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 6 Aug 2021 13:44:54 +0200 Subject: [PATCH 205/617] run_test: relax bootloader name constraint --- test/firmware.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/firmware.py b/test/firmware.py index b7b089aa2..e83ad55eb 100644 --- a/test/firmware.py +++ b/test/firmware.py @@ -69,7 +69,7 @@ class DAPLinkFirmware(Firmware): """Class to abstract access to a daplink firmware image""" _IF_RE = re.compile("^([a-z0-9]+)([_a-z0-9]*)_if$") - _BL_RE = re.compile("^([a-z0-9]+)_bl$") + _BL_RE = re.compile("^([a-z0-9]+)([_a-z0-9]*)_bl$") def __init__(self, name, bundle, directory): self._name = name From d61c67dd71ecdd2832005b5369fee59f3b9de95d Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 6 Aug 2021 13:45:29 +0200 Subject: [PATCH 206/617] run_test: fix micro:bit test configuration --- test/info.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/test/info.py b/test/info.py index c64d43ce7..8f21f2ce1 100644 --- a/test/info.py +++ b/test/info.py @@ -289,7 +289,8 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x9017, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_wio_emw3166_if', None, 'WIO_EMW3166' ), # TODO - set target to 'Seeed-96Boards-Nitrogen' when mbed-os supports this ( 0x9900, VENDOR_TO_FAMILY('Nordic', 1), 'kl26z_microbit_if', 'kl26z_bl', 'Microbit' ), ( 0x9901, VENDOR_TO_FAMILY('Nordic', 1), 'kl26z_microbit_if', 'kl26z_bl', 'Microbit' ), - ( 0x9903, VENDOR_TO_FAMILY('Nordic', 2), 'kl27z_microbit_if', 'kl27z_bl', 'Microbit' ), + ( 0x9903, VENDOR_TO_FAMILY('Nordic', 2), 'kl27z_microbit_if', 'kl27z_bl', 'Microbitv2' ), + ( 0x9904, VENDOR_TO_FAMILY('Nordic', 2), 'kl27z_microbit_if', 'kl27z_bl', 'Microbitv2' ), ( 0xA127, VENDOR_TO_FAMILY('Ambiq', 1), 'kl26z_artemis_dk_if', 'kl26z_bl', 'ARTMBED' ), ( 0xC000, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_cocorico_if', None, 'CoCo-ri-Co' ), ( 0xC006, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_vbluno51_if', None, 'VBLUNO51' ), From 04cfdbea3a4e671469327c10450d28f48a8d1340 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 11 Aug 2021 07:31:34 -0500 Subject: [PATCH 207/617] Reduce main stack size for lpc11u35 --- records/hic_hal/lpc11u35.yaml | 2 ++ source/daplink/interface/tasks.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/records/hic_hal/lpc11u35.yaml b/records/hic_hal/lpc11u35.yaml index 7251d3cd3..02fffb9c7 100644 --- a/records/hic_hal/lpc11u35.yaml +++ b/records/hic_hal/lpc11u35.yaml @@ -30,6 +30,8 @@ tool_specific: hic_hal: - source/hic_hal/nxp/lpc11u35/armcc gcc_arm: + macros: + - MAIN_TASK_STACK=832 linker_file: - source/hic_hal/nxp/lpc11u35/gcc/lpc11u35.ld sources: diff --git a/source/daplink/interface/tasks.h b/source/daplink/interface/tasks.h index 438ea5f9a..b2eec8d29 100644 --- a/source/daplink/interface/tasks.h +++ b/source/daplink/interface/tasks.h @@ -25,7 +25,9 @@ // trouble here is that reset for different targets is implemented differently so all targets // have to use the largest stack or these have to be defined in multiple places... Not ideal // may want to move away from threads for some of these behaviours to optimize mempory usage (RAM) +#ifndef MAIN_TASK_STACK #define MAIN_TASK_STACK (864) +#endif #define MAIN_TASK_PRIORITY (osPriorityNormal) #endif From 3fbfe09b94f2dae980376e8cef10286c10e84c5c Mon Sep 17 00:00:00 2001 From: iosabi Date: Sat, 14 Aug 2021 19:42:41 +0200 Subject: [PATCH 208/617] LPC55xx: Fix uart_write_data() with pending transfers. `uart_write_data()` uses a circular buffer to enqueue next TX bytes and a single `cb_buf.tx` byte for the "current" byte it is sending. This function was always calling `USART_INSTANCE.Send` without checking whether a transfer was already in progress, which would cause the fsl_uart_cmsis.c to override the current transfer if there was one in progress. This would cause the next byte in the circular buffer (the one returned by `pop`) to be discarded when `uart_write_data()` is called and there is already data pending in the circular buffer. This bug can be reliably reproduced when issuing multiple writes on the /dev/ttyACM0 device on a short period of time. This patch fixes the problem by adding a flag that tells whether the current transfer is still ongoing or not. At the moment, since all the `Send()` calls use a size of 1 this flag can only be 0 or 1, but it will increased in the future for a more performant implementation. Tested on Linux sending multiple writes of various lengths and checking the receiving end on a different USB-to-UART adapter. --- source/hic_hal/nxp/lpc55xx/uart.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/source/hic_hal/nxp/lpc55xx/uart.c b/source/hic_hal/nxp/lpc55xx/uart.c index 94d5077b7..c26adc1e7 100644 --- a/source/hic_hal/nxp/lpc55xx/uart.c +++ b/source/hic_hal/nxp/lpc55xx/uart.c @@ -45,6 +45,10 @@ circ_buf_t read_buffer; uint8_t read_buffer_data[BUFFER_SIZE]; struct { + // Number of bytes pending to be transferred. This is 0 if there is no + // ongoing transfer and the uart_handler processed the last transfer. + volatile uint32_t tx_size; + uint8_t rx; uint8_t tx; } cb_buf; @@ -60,6 +64,7 @@ void clear_buffers(void) int32_t uart_initialize(void) { clear_buffers(); + cb_buf.tx_size = 0; Driver_USART0.Initialize(uart_handler); Driver_USART0.PowerControl(ARM_POWER_FULL); @@ -73,6 +78,7 @@ int32_t uart_uninitialize(void) Driver_USART0.PowerControl(ARM_POWER_OFF); Driver_USART0.Uninitialize(); clear_buffers(); + cb_buf.tx_size = 0; return 1; } @@ -189,15 +195,17 @@ int32_t uart_write_data(uint8_t *data, uint16_t size) return 0; } - uint32_t cnt = 0; - if (circ_buf_count_used(&write_buffer) > 0) { + // Disable interrupts to prevent the uart_handler from modifying the + // circular buffer at the same time. + NVIC_DisableIRQ(USART_IRQ); + uint32_t cnt = circ_buf_write(&write_buffer, data, size); + if (cb_buf.tx_size == 0 && circ_buf_count_used(&write_buffer) > 0) { + // There's no pending transfer, so we need to start the process. cb_buf.tx = circ_buf_pop(&write_buffer); - cnt = circ_buf_write(&write_buffer, data, size); - } else { - cb_buf.tx = data[0]; - cnt = circ_buf_write(&write_buffer, data + 1, size - 1) + 1; + USART_INSTANCE.Send(&(cb_buf.tx), 1); + cb_buf.tx_size = 1; } - USART_INSTANCE.Send(&(cb_buf.tx), 1); + NVIC_EnableIRQ(USART_IRQ); return cnt; } @@ -224,6 +232,10 @@ void uart_handler(uint32_t event) { if (circ_buf_count_used(&write_buffer) > 0) { cb_buf.tx = circ_buf_pop(&write_buffer); USART_INSTANCE.Send(&(cb_buf.tx), 1); + } else { + // Signals that next call to uart_write_data() should start a + // transfer. + cb_buf.tx_size = 0; } } } From 50ed535e44180e90cc5e5b64e8118f143b37e28f Mon Sep 17 00:00:00 2001 From: iosabi Date: Sat, 14 Aug 2021 23:07:34 +0200 Subject: [PATCH 209/617] LPC55xx: Improve UART TX performance. Without this patch, transmitting at 921600 baudrate with 8n1 mode yields to about 49.8KiB/s instead of the theoretical limit of 90 KiB/s. The reason for this is because between the rising edge of the last data bit (start of the STOP bit) and the falling edge before the START bit of the next transfer we observe about 9.7us gap while the minimum is just the length of a single STOP bit (about 1.1us). This gap is attributed to the CPU time running the event handler (uart_handler) and scheduling a new transfer. The performance was measured using a USB-to-UART probe running with: `picocom -b 921600 /dev/ttyUSB0 | pv >/dev/null` and also looking at the TX signal on the oscilloscope. This commit creates two new functions in the circular buffer module that let you peek into the internal buffer (avoiding a memcpy) and more importantly allowing to return larger buffers to be passed to the UART driver in a single Send() call. The UART module in the chip already has a small FIFO that would allow the non-blocking transfer to enqueue the buffer with 0 delay between consecutive bytes of the same transfer. Given the 512 byte circular buffer size and the maximum 128 byte transfer size this means that only one every 128 bytes would have a ~9us bigger gap with the previous one than needed. At a baudrate of 921600, 128 bytes take 1389 us to transmit so a 9 us delay is about a 1% performance degradation. After this patch the effective TX bandwidth goes up 89.4 KiB/s, just shy of the theoretical maximum of 90 KiB/s and consistent with the expected performance. --- source/daplink/circ_buf.c | 44 +++++++++++++++++++++++++++++ source/daplink/circ_buf.h | 9 ++++++ source/hic_hal/nxp/lpc55xx/uart.c | 47 +++++++++++++++++++------------ 3 files changed, 82 insertions(+), 18 deletions(-) diff --git a/source/daplink/circ_buf.c b/source/daplink/circ_buf.c index 9f191d9b7..437b79275 100644 --- a/source/daplink/circ_buf.c +++ b/source/daplink/circ_buf.c @@ -134,3 +134,47 @@ uint32_t circ_buf_write(circ_buf_t *circ_buf, const uint8_t *data, uint32_t size return cnt; } + +const uint8_t* circ_buf_peek(circ_buf_t *circ_buf, uint32_t* size) +{ + uint32_t cnt; + uint8_t* ret; + cortex_int_state_t state; + + state = cortex_int_get_and_disable(); + + if (circ_buf->tail >= circ_buf->head) { + cnt = circ_buf->tail - circ_buf->head; + } else { + // We can't peek all the bytes in the circular buffer in this case. + cnt = circ_buf->size - circ_buf->head; + } + ret = circ_buf->buf + circ_buf->head; + + cortex_int_restore(state); + + if (size) { + *size = cnt; + } + return ret; +} + +void circ_buf_pop_n(circ_buf_t *circ_buf, uint32_t n) +{ + cortex_int_state_t state; + + state = cortex_int_get_and_disable(); + + if (circ_buf->tail >= circ_buf->head) { + util_assert(circ_buf->tail - circ_buf->head <= n); + circ_buf->head += n; + } else { + util_assert(circ_buf->tail + circ_buf->size - circ_buf->head <= n); + circ_buf->head += n; + if (circ_buf->head >= circ_buf->size) { + circ_buf->head -= circ_buf->size; + } + } + + cortex_int_restore(state); +} diff --git a/source/daplink/circ_buf.h b/source/daplink/circ_buf.h index 245abbdff..c1412aab0 100644 --- a/source/daplink/circ_buf.h +++ b/source/daplink/circ_buf.h @@ -57,6 +57,15 @@ uint32_t circ_buf_read(circ_buf_t *circ_buf, uint8_t *data, uint32_t size); // Attempt to write size bytes to the buffer. Return the number of bytes written uint32_t circ_buf_write(circ_buf_t *circ_buf, const uint8_t *data, uint32_t size); +// Returns a pointer to the next byte on the circular buffer and stores in the +// value pointed by "size" the number of bytes available in that region, which +// may be less than the total number of bytes in the circular buffer. +const uint8_t* circ_buf_peek(circ_buf_t *circ_buf, uint32_t* size); + +// Remove n bytes from the front of the circular buffer. The values are +// discarded. +void circ_buf_pop_n(circ_buf_t *circ_buf, uint32_t n); + #ifdef __cplusplus } #endif diff --git a/source/hic_hal/nxp/lpc55xx/uart.c b/source/hic_hal/nxp/lpc55xx/uart.c index c26adc1e7..f69648d1d 100644 --- a/source/hic_hal/nxp/lpc55xx/uart.c +++ b/source/hic_hal/nxp/lpc55xx/uart.c @@ -50,7 +50,6 @@ struct { volatile uint32_t tx_size; uint8_t rx; - uint8_t tx; } cb_buf; void uart_handler(uint32_t event); @@ -189,23 +188,41 @@ int32_t uart_write_free(void) return circ_buf_count_free(&write_buffer); } +// Start a new TX transfer if there are bytes pending to be transferred on the +// write_buffer buffer. The transferred bytes are not removed from the circular +// by this function, only the event handler will remove them once the transfer +// is done. +static void uart_start_tx_transfer() { + uint32_t tx_size = 0; + const uint8_t* buf = circ_buf_peek(&write_buffer, &tx_size); + if (tx_size > BUFFER_SIZE / 4) { + // The bytes being transferred remain on the circular buffer memory + // until the transfer is done. Limiting the UART transfer size + // allows the uart_handler to clear those bytes earlier. + tx_size = BUFFER_SIZE / 4; + } + cb_buf.tx_size = tx_size; + if (tx_size) { + USART_INSTANCE.Send(buf, tx_size); + } +} + int32_t uart_write_data(uint8_t *data, uint16_t size) { if (size == 0) { return 0; } - // Disable interrupts to prevent the uart_handler from modifying the - // circular buffer at the same time. - NVIC_DisableIRQ(USART_IRQ); uint32_t cnt = circ_buf_write(&write_buffer, data, size); - if (cb_buf.tx_size == 0 && circ_buf_count_used(&write_buffer) > 0) { - // There's no pending transfer, so we need to start the process. - cb_buf.tx = circ_buf_pop(&write_buffer); - USART_INSTANCE.Send(&(cb_buf.tx), 1); - cb_buf.tx_size = 1; + if (cb_buf.tx_size == 0) { + // There's no pending transfer and the value of cb_buf.tx_size will not + // change to non-zero by the event handler once it is zero. Note that it + // is entirely possible that we transferred all the bytes we added to + // the circular buffer in this function by the time we are in this + // branch, in that case uart_start_tx_transfer() would not schedule any + // transfer. + uart_start_tx_transfer(); } - NVIC_EnableIRQ(USART_IRQ); return cnt; } @@ -229,14 +246,8 @@ void uart_handler(uint32_t event) { } if (event & ARM_USART_EVENT_SEND_COMPLETE) { - if (circ_buf_count_used(&write_buffer) > 0) { - cb_buf.tx = circ_buf_pop(&write_buffer); - USART_INSTANCE.Send(&(cb_buf.tx), 1); - } else { - // Signals that next call to uart_write_data() should start a - // transfer. - cb_buf.tx_size = 0; - } + circ_buf_pop_n(&write_buffer, cb_buf.tx_size); + uart_start_tx_transfer(); } } From e212b0f6c643f7c5bf6652e760ecf62bafc565ca Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Wed, 20 May 2020 14:01:52 -0500 Subject: [PATCH 210/617] Incompatible image detection feature -Added ROM setting to enable/disable feature via .cfg files. -Implemented hook at flash_decoder layer once the first 12 vectors are obtained (flash decoder min size) --- source/daplink/drag-n-drop/flash_decoder.c | 38 +++++++++++++++++++++ source/daplink/drag-n-drop/flash_decoder.h | 1 + source/daplink/drag-n-drop/vfs_user.c | 10 ++++++ source/daplink/error.c | 4 +++ source/daplink/error.h | 1 + source/daplink/settings/settings.h | 2 ++ source/daplink/settings/settings_rom.c | 15 +++++++- source/daplink/settings/settings_rom_stub.c | 10 ++++++ tools/generate_config.py | 13 ++++--- 9 files changed, 88 insertions(+), 6 deletions(-) diff --git a/source/daplink/drag-n-drop/flash_decoder.c b/source/daplink/drag-n-drop/flash_decoder.c index 3854f57e2..440332c20 100644 --- a/source/daplink/drag-n-drop/flash_decoder.c +++ b/source/daplink/drag-n-drop/flash_decoder.c @@ -29,6 +29,7 @@ #include "settings.h" // for config_get_automation_allowed #include "validation.h" #include "target_board.h" +#include "cmsis_compiler.h" // Set to 1 to enable debugging #define DEBUG_FLASH_DECODER 0 @@ -59,6 +60,11 @@ static bool flash_type_target_bin; static bool flash_decoder_is_at_end(uint32_t addr, const uint8_t *data, uint32_t size); +__WEAK uint8_t board_detect_incompatible_image(const uint8_t *data, uint32_t size) +{ + return 0; // Return 0 if image is compatible +} + flash_decoder_type_t flash_decoder_detect_type(const uint8_t *data, uint32_t size, uint32_t addr, bool addr_valid) { daplink_info_t info; @@ -179,6 +185,28 @@ error_t flash_decoder_get_flash(flash_decoder_type_t type, uint32_t addr, bool a return status; } +error_t flash_decoder_validate_target_image(flash_decoder_type_t type, const uint8_t *data, uint32_t size) +{ + error_t status = ERROR_SUCCESS; + + if (daplink_is_interface()) { + if (FLASH_DECODER_TYPE_TARGET == type) { + if (g_board_info.target_cfg) { + if (board_detect_incompatible_image(data, size)){ + status = ERROR_FD_INCOMPATIBLE_IMAGE; + flash_intf_target->init(); + flash_intf_target->erase_chip(); + flash_intf_target->uninit(); + } else { + status = ERROR_SUCCESS; + } + } + } + } + + return status; +} + error_t flash_decoder_open(void) { flash_decoder_printf("flash_decoder_open()\r\n"); @@ -262,6 +290,16 @@ error_t flash_decoder_write(uint32_t addr, const uint8_t *data, uint32_t size) state = DECODER_STATE_ERROR; return status; } + + // Validate incompatible target image file + if (config_get_detect_incompatible_target()){ + status = flash_decoder_validate_target_image(flash_type, flash_buf, flash_buf_pos); + + if (ERROR_SUCCESS != status) { + state = DECODER_STATE_ERROR; + return status; + } + } flash_decoder_printf(" flash_start_addr=0x%x\r\n", flash_start_addr); // Initialize flash manager diff --git a/source/daplink/drag-n-drop/flash_decoder.h b/source/daplink/drag-n-drop/flash_decoder.h index 2895c93d0..bf6b0bd8c 100644 --- a/source/daplink/drag-n-drop/flash_decoder.h +++ b/source/daplink/drag-n-drop/flash_decoder.h @@ -45,6 +45,7 @@ typedef enum { flash_decoder_type_t flash_decoder_detect_type(const uint8_t *data, uint32_t size, uint32_t addr, bool addr_valid); error_t flash_decoder_get_flash(flash_decoder_type_t type, uint32_t addr, bool addr_valid, uint32_t *start_addr, const flash_intf_t **flash_intf); +error_t flash_decoder_validate_target_image(flash_decoder_type_t type, const uint8_t *data, uint32_t size); error_t flash_decoder_open(void); error_t flash_decoder_write(uint32_t addr, const uint8_t *data, uint32_t size); error_t flash_decoder_close(void); diff --git a/source/daplink/drag-n-drop/vfs_user.c b/source/daplink/drag-n-drop/vfs_user.c index c4eab4610..c141d6409 100644 --- a/source/daplink/drag-n-drop/vfs_user.c +++ b/source/daplink/drag-n-drop/vfs_user.c @@ -66,6 +66,8 @@ typedef enum _magic_file { kOverflowOffConfigFile, //!< Disable UART overflow reporting. kMSDOnConfigFile, //!< Enable USB MSC. Uh.... kMSDOffConfigFile, //!< Disable USB MSC. + kImageCheckOnConfigFile, //!< Enable Incompatible target image detection. + kImageCheckOffConfigFile, //!< Disable Incompatible target image detection. kPageEraseActionFile, //!< Enable page programming and sector erase for drag and drop. kChipEraseActionFile, //!< Enable page programming and chip erase for drag and drop. } magic_file_t; @@ -110,6 +112,8 @@ static const magic_file_info_t s_magic_file_info[] = { { "OVFL_OFFCFG", kOverflowOffConfigFile }, { "MSD_ON CFG", kMSDOnConfigFile }, { "MSD_OFF CFG", kMSDOffConfigFile }, + { "COMP_ON CFG", kImageCheckOnConfigFile }, + { "COMP_OFFCFG", kImageCheckOffConfigFile }, { "PAGE_ON ACT", kPageEraseActionFile }, { "PAGE_OFFACT", kChipEraseActionFile }, }; @@ -268,6 +272,12 @@ void vfs_user_file_change_handler(const vfs_filename_t filename, vfs_file_change case kMSDOffConfigFile: config_ram_set_disable_msd(true); break; + case kImageCheckOnConfigFile: + config_set_detect_incompatible_target(true); + break; + case kImageCheckOffConfigFile: + config_set_detect_incompatible_target(false); + break; case kPageEraseActionFile: config_ram_set_page_erase(true); break; diff --git a/source/daplink/error.c b/source/daplink/error.c index 965c2dfbd..6ae288930 100644 --- a/source/daplink/error.c +++ b/source/daplink/error.c @@ -99,6 +99,8 @@ static const char *const error_message[] = { "The starting address for the interface update is wrong.", // ERROR_FD_UNSUPPORTED_UPDATE "The application file format is unknown and cannot be parsed and/or processed.", + // ERROR_FD_INCOMPATIBLE_IMAGE + "The application image is not compatible with the target.", /* Flash IAP interface */ @@ -203,6 +205,8 @@ static error_type_t error_type[] = { ERROR_TYPE_USER, // ERROR_FD_UNSUPPORTED_UPDATE ERROR_TYPE_USER, + // ERROR_FD_INCOMPATIBLE_IMAGE + ERROR_TYPE_USER, /* Flash IAP interface */ diff --git a/source/daplink/error.h b/source/daplink/error.h index c3a096086..325337ba2 100644 --- a/source/daplink/error.h +++ b/source/daplink/error.h @@ -66,6 +66,7 @@ typedef enum { ERROR_FD_BL_UPDT_ADDR_WRONG, ERROR_FD_INTF_UPDT_ADDR_WRONG, ERROR_FD_UNSUPPORTED_UPDATE, + ERROR_FD_INCOMPATIBLE_IMAGE, /* Flash IAP interface */ ERROR_IAP_INIT, diff --git a/source/daplink/settings/settings.h b/source/daplink/settings/settings.h index 7a84ba6f4..0e823ae82 100644 --- a/source/daplink/settings/settings.h +++ b/source/daplink/settings/settings.h @@ -42,9 +42,11 @@ void config_init(void); void config_set_auto_rst(bool on); void config_set_automation_allowed(bool on); void config_set_overflow_detect(bool on); +void config_set_detect_incompatible_target(bool on); bool config_get_auto_rst(void); bool config_get_automation_allowed(void); bool config_get_overflow_detect(void); +bool config_get_detect_incompatible_target(void); // Get/set settings residing in shared ram void config_ram_set_hold_in_bl(bool hold); diff --git a/source/daplink/settings/settings_rom.c b/source/daplink/settings/settings_rom.c index be01a5ba9..e355459e8 100644 --- a/source/daplink/settings/settings_rom.c +++ b/source/daplink/settings/settings_rom.c @@ -46,11 +46,12 @@ typedef struct __attribute__((__packed__)) cfg_setting { uint8_t overflow_detect; // Add new members here + uint8_t detect_incompatible_target; } cfg_setting_t; // Make sure FORMAT in generate_config.py is updated if size changes -COMPILER_ASSERT(sizeof(cfg_setting_t) == 9); +COMPILER_ASSERT(sizeof(cfg_setting_t) == 10); // Sector buffer must be as big or bigger than settings COMPILER_ASSERT(sizeof(cfg_setting_t) < SECTOR_BUFFER_SIZE); @@ -74,6 +75,7 @@ static const cfg_setting_t config_default = { .auto_rst = 1, .automation_allowed = 1, .overflow_detect = 1, + .detect_incompatible_target = 0 }; // Check if the configuration in flash needs to be updated @@ -169,6 +171,12 @@ void config_set_overflow_detect(bool on) program_cfg(&config_rom_copy); } +void config_set_detect_incompatible_target(bool on) +{ + config_rom_copy.detect_incompatible_target = on; + program_cfg(&config_rom_copy); +} + bool config_get_auto_rst() { return config_rom_copy.auto_rst; @@ -183,3 +191,8 @@ bool config_get_overflow_detect() { return config_rom_copy.overflow_detect; } + +bool config_get_detect_incompatible_target() +{ + return config_rom_copy.detect_incompatible_target; +} diff --git a/source/daplink/settings/settings_rom_stub.c b/source/daplink/settings/settings_rom_stub.c index 22d82013e..29826280f 100644 --- a/source/daplink/settings/settings_rom_stub.c +++ b/source/daplink/settings/settings_rom_stub.c @@ -41,6 +41,11 @@ void config_set_overflow_detect(bool on) // Do nothing } +void config_set_detect_incompatible_target(bool on) +{ + // Do nothing +} + bool config_get_auto_rst() { return false; @@ -55,3 +60,8 @@ bool config_get_overflow_detect() { return false; } + +bool config_get_detect_incompatible_target() +{ + return false; +} diff --git a/tools/generate_config.py b/tools/generate_config.py index e13424192..d36c03844 100755 --- a/tools/generate_config.py +++ b/tools/generate_config.py @@ -23,24 +23,25 @@ CFG_KEY = 0x6b766c64 # Must stay in sync with the structure cfg_setting -# in the header file config_settings.h: +# in the source file settings_rom.c: # 32 - key # 16 - offset_of_end # 8 - auto_rst # 8 - automation_allowed # 8 - overflow_detect +# 8 - detect_incompatible_target # 0 - 'end' member omitted -FORMAT = ' Date: Wed, 20 May 2020 14:14:21 -0500 Subject: [PATCH 211/617] Fat binaries feature --- source/daplink/drag-n-drop/intelhex.c | 44 +++++++++++++++++++-------- 1 file changed, 31 insertions(+), 13 deletions(-) diff --git a/source/daplink/drag-n-drop/intelhex.c b/source/daplink/drag-n-drop/intelhex.c index 58f7c7883..4ecff98fc 100644 --- a/source/daplink/drag-n-drop/intelhex.c +++ b/source/daplink/drag-n-drop/intelhex.c @@ -22,6 +22,7 @@ #include #include "intelhex.h" +#include "cmsis_compiler.h" typedef enum hex_record_t hex_record_t; enum hex_record_t { @@ -30,7 +31,9 @@ enum hex_record_t { EXT_SEG_ADDR_RECORD = 2, START_SEG_ADDR_RECORD = 3, EXT_LINEAR_ADDR_RECORD = 4, - START_LINEAR_ADDR_RECORD = 5 + START_LINEAR_ADDR_RECORD = 5, + CUSTOM_METADATA_RECORD = 0x0A, + CUSTOM_DATA_RECORD = 0x0D, }; typedef union hex_line_t hex_line_t; @@ -82,6 +85,9 @@ static uint8_t validate_checksum(hex_line_t *record) static hex_line_t line = {0}, shadow_line = {0}; static uint32_t next_address_to_write = 0; static uint8_t low_nibble = 0, idx = 0, record_processed = 0, load_unaligned_record = 0; +static uint16_t binary_version = 0; +uint16_t board_id_hex __WEAK; +uint16_t board_id_hex_min __WEAK; void reset_hex_parser(void) { @@ -92,6 +98,7 @@ void reset_hex_parser(void) idx = 0; record_processed = 0; load_unaligned_record = 0; + binary_version = 0; } hexfile_parse_status_t parse_hex_blob(const uint8_t *hex_blob, const uint32_t hex_blob_size, uint32_t *hex_parse_cnt, uint8_t *bin_buf, const uint32_t bin_buf_size, uint32_t *bin_buf_address, uint32_t *bin_buf_cnt) @@ -147,23 +154,34 @@ hexfile_parse_status_t parse_hex_blob(const uint8_t *hex_blob, const uint32_t he line.address = swap16(line.address); switch (line.record_type) { + case CUSTOM_METADATA_RECORD: + binary_version = (uint16_t) line.data[0] << 8 | line.data[1]; + break; case DATA_RECORD: + case CUSTOM_DATA_RECORD: // keeping a record of the last hex record memcpy(shadow_line.buf, line.buf, sizeof(hex_line_t)); - // verify this is a continous block of memory or need to exit and dump - if (((next_address_to_write & 0xffff0000) | line.address) != next_address_to_write) { - load_unaligned_record = 1; - status = HEX_PARSE_UNALIGNED; - goto hex_parser_exit; + if (binary_version == 0 || (binary_version >= board_id_hex_min && binary_version <= board_id_hex)){ + // Only save data from the correct binary + // verify this is a continous block of memory or need to exit and dump + if (((next_address_to_write & 0xffff0000) | line.address) != next_address_to_write) { + load_unaligned_record = 1; + status = HEX_PARSE_UNALIGNED; + goto hex_parser_exit; + } + + // move from line buffer back to input buffer + memcpy(bin_buf, line.data, line.byte_count); + bin_buf += line.byte_count; + *bin_buf_cnt = (uint32_t)(*bin_buf_cnt) + line.byte_count; + // Save next address to write + next_address_to_write = ((next_address_to_write & 0xffff0000) | line.address) + line.byte_count; + } + else { + status = HEX_PARSE_OK; + goto hex_parser_exit; } - - // move from line buffer back to input buffer - memcpy(bin_buf, line.data, line.byte_count); - bin_buf += line.byte_count; - *bin_buf_cnt = (uint32_t)(*bin_buf_cnt) + line.byte_count; - // Save next address to write - next_address_to_write = ((next_address_to_write & 0xffff0000) | line.address) + line.byte_count; break; case EOF_RECORD: From 4c2cbf1964a3f424a533568bb17f482ff1e0f01c Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Wed, 20 May 2020 14:17:37 -0500 Subject: [PATCH 212/617] Interface main task changes -hook for custom reset button handling -hook for 30ms event tick -hook for power down event -usb state udpate --- source/daplink/interface/main_interface.c | 59 +++++++++++++++-------- 1 file changed, 40 insertions(+), 19 deletions(-) diff --git a/source/daplink/interface/main_interface.c b/source/daplink/interface/main_interface.c index 24f9678e7..01bbbb4cf 100644 --- a/source/daplink/interface/main_interface.c +++ b/source/daplink/interface/main_interface.c @@ -143,6 +143,35 @@ static main_led_state_t msc_led_state = MAIN_LED_FLASH; main_usb_connect_t usb_state; static bool usb_test_mode = false; +__WEAK void board_30ms_hook(void){} + +__WEAK void handle_reset_button(void) +{ + // button state + static uint8_t reset_pressed = 0; + + // handle reset button without eventing + if (!reset_pressed && gpio_get_reset_btn_fwrd()) { +#ifdef DRAG_N_DROP_SUPPORT + if (!flash_intf_target->flash_busy()) //added checking if flashing on target is in progress +#endif + { + // Reset button pressed + target_set_state(RESET_HOLD); + reset_pressed = 1; + } + } else if (reset_pressed && !gpio_get_reset_btn_fwrd()) { + // Reset button released + target_set_state(RESET_RUN); + reset_pressed = 0; + } +} + +__WEAK void board_handle_powerdown() +{ + // TODO: put the interface chip in sleep mode +} + // Timer task, set flags every 30mS and 90mS void timer_task_30mS(void * arg) { @@ -229,8 +258,6 @@ void main_task(void * arg) // USB uint32_t usb_state_count = USB_BUSY_TIME; uint32_t usb_no_config_count = USB_CONFIGURE_TIMEOUT; - // button state - uint8_t reset_pressed = 0; #ifdef PBON_BUTTON uint8_t power_on = 1; #endif @@ -332,8 +359,7 @@ void main_task(void * arg) gpio_set_cdc_led(GPIO_LED_OFF); gpio_set_msc_led(GPIO_LED_OFF); - // TODO: put the interface chip in sleep mode - while (1); + board_handle_powerdown(); } if (flags & FLAGS_MAIN_DISABLEDEBUG) { @@ -382,12 +408,19 @@ void main_task(void * arg) // powered by a USB wall wart or similar power source. Go ahead and enable // board power. gpio_set_board_power(true); + usb_state = USB_DISCONNECTED; } break; case USB_CONNECTED: case USB_DISCONNECTED: + if (usbd_configured()) { + usb_state = USB_CONNECTED; + } + else { + usb_state = USB_DISCONNECTED; + } default: break; } @@ -396,21 +429,7 @@ void main_task(void * arg) // 30mS tick used for flashing LED when USB is busy if (flags & FLAGS_MAIN_30MS) { - // handle reset button without eventing - if (!reset_pressed && gpio_get_reset_btn_fwrd()) { -#ifdef DRAG_N_DROP_SUPPORT - if (!flash_intf_target->flash_busy()) //added checking if flashing on target is in progress -#endif - { - // Reset button pressed - target_set_state(RESET_HOLD); - reset_pressed = 1; - } - } else if (reset_pressed && !gpio_get_reset_btn_fwrd()) { - // Reset button released - target_set_state(RESET_RUN); - reset_pressed = 0; - } + handle_reset_button(); #ifdef PBON_BUTTON // handle PBON pressed @@ -434,6 +453,8 @@ void main_task(void * arg) } } #endif + // 30ms event hook function + board_30ms_hook(); // DAP LED if (hid_led_usb_activity) { From 2635ad58ff0ab44194157f2adfffe481541e556f Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Wed, 20 May 2020 19:25:00 -0500 Subject: [PATCH 213/617] Add microbit specific features -Add KL27Z NXP drivers -Power monitor (detect power source) -Board Rev Id detection -i2c support -low power support -button and LED handling --- records/board/microbitv2.yaml | 3 +- source/board/microbitv2/IO_Config_Override.h | 161 ++ source/board/microbitv2/flexio_pwm.c | 120 + source/board/microbitv2/flexio_pwm.h | 19 + source/board/microbitv2/microbitv2.c | 328 ++- source/board/microbitv2/power.c | 181 ++ source/board/microbitv2/power.h | 32 + source/board/microbitv2/pwr_mon.c | 103 + source/board/microbitv2/pwr_mon.h | 31 + source/hic_hal/adc.h | 23 + source/hic_hal/freescale/kl27z/adc.c | 46 + .../freescale/kl27z/armcc/startup_MKL27Z4.s | 21 +- source/hic_hal/freescale/kl27z/fsl_adc16.c | 370 +++ source/hic_hal/freescale/kl27z/fsl_adc16.h | 526 ++++ source/hic_hal/freescale/kl27z/fsl_flexio.c | 427 +++ source/hic_hal/freescale/kl27z/fsl_flexio.h | 701 +++++ source/hic_hal/freescale/kl27z/fsl_gpio.c | 345 +++ source/hic_hal/freescale/kl27z/fsl_gpio.h | 538 ++++ source/hic_hal/freescale/kl27z/fsl_i2c.c | 2394 +++++++++++++++++ source/hic_hal/freescale/kl27z/fsl_i2c.h | 795 ++++++ source/hic_hal/freescale/kl27z/fsl_llwu.c | 453 ++++ source/hic_hal/freescale/kl27z/fsl_llwu.h | 303 +++ source/hic_hal/freescale/kl27z/fsl_pmc.c | 120 + source/hic_hal/freescale/kl27z/fsl_pmc.h | 419 +++ source/hic_hal/freescale/kl27z/fsl_port.h | 476 ++++ source/hic_hal/freescale/kl27z/fsl_rcm.c | 65 + source/hic_hal/freescale/kl27z/fsl_rcm.h | 408 +++ source/hic_hal/freescale/kl27z/fsl_smc.c | 511 ++++ source/hic_hal/freescale/kl27z/fsl_smc.h | 421 +++ source/hic_hal/freescale/kl27z/fsl_tpm.c | 766 ++++++ source/hic_hal/freescale/kl27z/fsl_tpm.h | 630 +++++ source/hic_hal/freescale/kl27z/i2c.c | 173 ++ source/hic_hal/freescale/kl27z/i2c.h | 14 + 33 files changed, 11914 insertions(+), 9 deletions(-) create mode 100644 source/board/microbitv2/IO_Config_Override.h create mode 100644 source/board/microbitv2/flexio_pwm.c create mode 100644 source/board/microbitv2/flexio_pwm.h create mode 100644 source/board/microbitv2/power.c create mode 100644 source/board/microbitv2/power.h create mode 100644 source/board/microbitv2/pwr_mon.c create mode 100644 source/board/microbitv2/pwr_mon.h create mode 100644 source/hic_hal/adc.h create mode 100644 source/hic_hal/freescale/kl27z/adc.c create mode 100644 source/hic_hal/freescale/kl27z/fsl_adc16.c create mode 100644 source/hic_hal/freescale/kl27z/fsl_adc16.h create mode 100644 source/hic_hal/freescale/kl27z/fsl_flexio.c create mode 100644 source/hic_hal/freescale/kl27z/fsl_flexio.h create mode 100644 source/hic_hal/freescale/kl27z/fsl_gpio.c create mode 100644 source/hic_hal/freescale/kl27z/fsl_gpio.h create mode 100644 source/hic_hal/freescale/kl27z/fsl_i2c.c create mode 100644 source/hic_hal/freescale/kl27z/fsl_i2c.h create mode 100644 source/hic_hal/freescale/kl27z/fsl_llwu.c create mode 100644 source/hic_hal/freescale/kl27z/fsl_llwu.h create mode 100644 source/hic_hal/freescale/kl27z/fsl_pmc.c create mode 100644 source/hic_hal/freescale/kl27z/fsl_pmc.h create mode 100644 source/hic_hal/freescale/kl27z/fsl_port.h create mode 100644 source/hic_hal/freescale/kl27z/fsl_rcm.c create mode 100644 source/hic_hal/freescale/kl27z/fsl_rcm.h create mode 100644 source/hic_hal/freescale/kl27z/fsl_smc.c create mode 100644 source/hic_hal/freescale/kl27z/fsl_smc.h create mode 100644 source/hic_hal/freescale/kl27z/fsl_tpm.c create mode 100644 source/hic_hal/freescale/kl27z/fsl_tpm.h create mode 100644 source/hic_hal/freescale/kl27z/i2c.c create mode 100644 source/hic_hal/freescale/kl27z/i2c.h diff --git a/records/board/microbitv2.yaml b/records/board/microbitv2.yaml index 70c95fae8..1a67ccbef 100644 --- a/records/board/microbitv2.yaml +++ b/records/board/microbitv2.yaml @@ -4,9 +4,10 @@ common: - CDC_LED_DEF=GPIO_LED_ON - MSC_LED_DEF=GPIO_LED_ON - USB_PROD_STR="BBC micro:bit CMSIS-DAP" + - IO_CONFIG_OVERRIDE sources: board: - - source/board/microbitv2/microbitv2.c + - source/board/microbitv2/ target: - source/family/nordic/nrf5x/target.c - source/family/nordic/target_reset_nrf52.c diff --git a/source/board/microbitv2/IO_Config_Override.h b/source/board/microbitv2/IO_Config_Override.h new file mode 100644 index 000000000..df08e214a --- /dev/null +++ b/source/board/microbitv2/IO_Config_Override.h @@ -0,0 +1,161 @@ +/** + * @file IO_Config_Override.h + * @brief Alternative IO for KL27Z based Hardware Interface Circuit + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "MKL27Z4.h" +#include "compiler.h" +#include "daplink.h" + +// This GPIO configuration is only valid for the KL27 HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_KL27Z); + + +// Debug Port I/O Pins + +// SWCLK Pin PTC6 +#define PIN_SWCLK_PORT PORTC +#define PIN_SWCLK_GPIO FGPIOC +#define PIN_SWCLK_BIT (6) +#define PIN_SWCLK (1< FLEXIO_MIN_FREQUENCY)); + + uint32_t lowerValue = 0; /* Number of clock cycles in high logic state in one period */ + uint32_t upperValue = 0; /* Number of clock cycles in low logic state in one period */ + uint32_t sum = 0; /* Number of clock cycles in one period */ + flexio_timer_config_t fxioTimerConfig; + + /* Check parameter */ + if (duty > 99) + { + duty = 99; + PIN_RED_LED_GPIO->PDDR |= PIN_RED_LED; + PIN_RED_LED_GPIO->PSOR = PIN_RED_LED; + PORT_SetPinMux(PIN_RED_LED_PORT, PIN_RED_LED_BIT, kPORT_MuxAsGpio); + } + else if (duty == 0) + { + duty = 1; + PIN_RED_LED_GPIO->PDDR |= PIN_RED_LED; + PIN_RED_LED_GPIO->PCOR = PIN_RED_LED; + PORT_SetPinMux(PIN_RED_LED_PORT, PIN_RED_LED_BIT, kPORT_MuxAsGpio); + } + else { + flexio_pwm_init_pins(); + } + + /* Configure the timer DEMO_FLEXIO_TIMER_CH for generating PWM */ + fxioTimerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0U); + fxioTimerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + fxioTimerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + fxioTimerConfig.pinConfig = kFLEXIO_PinConfigOutput; + fxioTimerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + fxioTimerConfig.pinSelect = DEMO_FLEXIO_OUTPUTPIN; /* Set pwm output */ + fxioTimerConfig.timerMode = kFLEXIO_TimerModeDisabled; + fxioTimerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + fxioTimerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + fxioTimerConfig.timerDisable = kFLEXIO_TimerDisableNever; + fxioTimerConfig.timerEnable = kFLEXIO_TimerEnabledAlways; + fxioTimerConfig.timerReset = kFLEXIO_TimerResetNever; + fxioTimerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + fxioTimerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + + /* Calculate timer lower and upper values of TIMCMP */ + /* Calculate the nearest integer value for sum, using formula round(x) = (2 * floor(x) + 1) / 2 */ + /* sum = DEMO_FLEXIO_CLOCK_FREQUENCY / freq_H */ + sum = (DEMO_FLEXIO_CLOCK_FREQUENCY * 2 / freq_Hz + 1) / 2; + /* Calculate the nearest integer value for lowerValue, the high period of the pwm output */ + /* lowerValue = sum * duty / 100 */ + lowerValue = (sum * duty / 50 + 1) / 2; + /* Calculate upper value, the low period of the pwm output */ + upperValue = sum - lowerValue; + fxioTimerConfig.timerCompare = ((upperValue - 1) << 8U) | (lowerValue - 1); + + FLEXIO_SetTimerConfig(DEMO_FLEXIO_BASEADDR, DEMO_FLEXIO_TIMER_CH, &fxioTimerConfig); + + /* Set Timer mode to kFLEXIO_TimerModeDual8BitPWM to start timer */ + DEMO_FLEXIO_BASEADDR->TIMCTL[DEMO_FLEXIO_TIMER_CH] |= FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitPWM); +} + +void flexio_pwm_init_pins(void) +{ + PORT_SetPinMux(PIN_RED_LED_PORT, PIN_RED_LED_BIT, kPORT_MuxAlt6); +} + +void flexio_pwm_deinit_pins(void) +{ + PORT_SetPinMux(PIN_RED_LED_PORT, PIN_RED_LED_BIT, kPORT_PinDisabledOrAnalog); +} diff --git a/source/board/microbitv2/flexio_pwm.h b/source/board/microbitv2/flexio_pwm.h new file mode 100644 index 000000000..8c70a2990 --- /dev/null +++ b/source/board/microbitv2/flexio_pwm.h @@ -0,0 +1,19 @@ +#ifndef FLEXIO_PWM_H_ +#define FLEXIO_PWM_H_ + +#include "IO_Config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void flexio_pwm_init(void); +void flexio_pwm_init_pins(void); +void flexio_pwm_deinit_pins(void); +void flexio_pwm_set_dutycycle(uint8_t duty); + +#ifdef __cplusplus +} +#endif + +#endif /* FLEXIO_PWM_H_ */ diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 355388db5..9e947a48f 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -23,18 +23,337 @@ #include "DAP.h" #include "target_family.h" #include "target_board.h" +#include "flexio_pwm.h" +#include "gpio.h" +#include "power.h" +#include "rl_usb.h" +#include "pwr_mon.h" +#include "main_interface.h" +#include "i2c.h" +#include "adc.h" +#include "fsl_port.h" +#include "fsl_gpio.h" + +#ifdef DRAG_N_DROP_SUPPORT +#include "flash_intf.h" +#endif + +#define M0_RESERVED_VECT_OFFSET (4 * 4) +#define M0_RESERVED_VECT_SIZE (3 * 4) // Size for mem fault, bus fault and usage fault vectors + +#define BRD_ID_1_UPPER_THR_V 935 // Upper threshold in mV for 100nF and 4700R +#define BRD_ID_1_LOWER_THR_V 268 // Lower threshold in mV for 100nF and 4700R + +#define PWR_LED_ON_BATT_BRIGHTNESS 40 // LED Brightness while being powered by battery +#define PWR_LED_FADEOUT_MIN_BRIGHTNESS 30 // Minimum LED brightness when fading out const char * const board_id_mb_2_0 = "9903"; +const char * const board_id_mb_2_1 = "9904"; + +uint16_t board_id_hex_min = 0x9903; +uint16_t board_id_hex = 0; + +typedef enum { + BOARD_VERSION_2_0 = 0, + BOARD_VERSION_2_1 = 1, +} mb_version_t; extern target_cfg_t target_device_nrf52_64; +extern main_usb_connect_t usb_state; +extern bool go_to_sleep; -// Called in main_task() to init before USB and files are configured -static void prerun_board_config(void) { +typedef enum main_shutdown_state { + MAIN_SHUTDOWN_WAITING = 0, + MAIN_SHUTDOWN_PENDING, + MAIN_SHUTDOWN_REACHED, + MAIN_SHUTDOWN_REQUESTED, + MAIN_LED_BLINK, + MAIN_LED_FULL_BRIGHTNESS, + MAIN_SHUTDOWN_CANCEL +} main_shutdown_state_t; + +extern void main_powerdown_event(void); + +// shutdown state +static main_shutdown_state_t main_shutdown_state = MAIN_SHUTDOWN_WAITING; +static uint8_t shutdown_led_dc = 100; +static uint8_t power_led_max_duty_cycle = 100; +static app_power_mode_t interface_power_mode; +static power_source_t power_source; + +// Board Rev ID detection. Reads BRD_REV_ID voltage +// Depends on gpio_init() to have been executed already +static mb_version_t read_brd_rev_id_pin(void) { + gpio_pin_config_t pin_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 0U + }; + mb_version_t board_version = BOARD_VERSION_2_0; + uint32_t board_rev_id_adc = 0; + uint32_t board_rev_id_mv = 0; + + // Set Board Rev ID pin as output but pin disabled + PORT_SetPinMux(PIN_BOARD_REV_ID_PORT , PIN_BOARD_REV_ID_BIT, kPORT_PinDisabledOrAnalog); + PORT_SetPinDriveStrength(PIN_BOARD_REV_ID_PORT, PIN_BOARD_REV_ID_BIT, kPORT_HighDriveStrength); + GPIO_PinInit(PIN_BOARD_REV_ID_GPIO, PIN_BOARD_REV_ID_BIT, &pin_config); + + adc_init(); + + // 1. Discharge capacitor + // Drive BRD_REV_ID pin to low + GPIO_PortClear(PIN_BOARD_REV_ID_GPIO, PIN_BOARD_REV_ID); + PORT_SetPinMux(PIN_BOARD_REV_ID_PORT , PIN_BOARD_REV_ID_BIT, kPORT_MuxAsGpio); + // Add a 3ms delay to allow the 100nF Cap to discharge + // at least 5*RC with 4700R. + for (uint32_t count = 16 * 3000; count > 0UL; count--); + + // 2. Charge capacitor for 100us + // Drive BRD_REV_ID pin to high + GPIO_PortSet(PIN_BOARD_REV_ID_GPIO, PIN_BOARD_REV_ID); + // Add a ~100us delay + // 3 clock cycles per loop at -O2 ARMCC optimization + for (uint32_t count = 1600; count > 0UL; count--); + // Change pin to ADC (High-Z). Capacitor will stop charging + PORT_SetPinMux(PIN_BOARD_REV_ID_PORT , PIN_BOARD_REV_ID_BIT, kPORT_PinDisabledOrAnalog); + + // 3. Take ADC measurement + board_rev_id_adc = adc_read_channel(0, PIN_BOARD_REV_ID_ADC_CH, PIN_BOARD_REV_ID_ADC_MUX); + board_rev_id_mv = board_rev_id_adc * 3300 / 0xFFF; // Convert ADC 12-bit value to mV with 3.3V reference + + // 4. Discharge capacitor + // Drive BRD_REV_ID pin to low + GPIO_PortClear(PIN_BOARD_REV_ID_GPIO, PIN_BOARD_REV_ID); + PORT_SetPinMux(PIN_BOARD_REV_ID_PORT , PIN_BOARD_REV_ID_BIT, kPORT_MuxAsGpio); + // Add a 3ms delay to allow the 100nF Cap to discharge + // at least 5*RC with 4700R. + for (uint32_t count = 16 * 3000; count > 0UL; count--); + + // 5. Identify board ID depending on voltage + if ( board_rev_id_mv > BRD_ID_1_LOWER_THR_V && board_rev_id_mv < BRD_ID_1_UPPER_THR_V) { + board_version = BOARD_VERSION_2_1; + } else { + board_version = BOARD_VERSION_2_0; + } + + return board_version; +} + +static void set_board_id(mb_version_t board_version) { target_device = target_device_nrf52_64; - target_device.rt_board_id = board_id_mb_2_0; + switch (board_version) { + case BOARD_VERSION_2_0: + target_device.rt_board_id = board_id_mb_2_0; + board_id_hex = 0x9903; + break; + case BOARD_VERSION_2_1: + target_device.rt_board_id = board_id_mb_2_1; + board_id_hex = 0x9904; + break; + default: + target_device.rt_board_id = board_id_mb_2_0; + board_id_hex = 0x9903; + break; + } +} + +// Apply a gamma curve to the LED. Input brightness between 0-100 +static inline uint8_t get_led_gamma(uint8_t brightness) { + uint8_t duty_cycle; + duty_cycle = (brightness * brightness * brightness + 5000) / 10000; + return duty_cycle; } -// USB HID override function return 1 if the activity is trivial or response is null +// Called in main_task() to init before USB and files are configured +static void prerun_board_config(void) +{ + mb_version_t board_version = read_brd_rev_id_pin(); + set_board_id(board_version); + + // init power monitoring + power_init(); + pwr_mon_init(); + + power_source = pwr_mon_get_power_source(); + + flexio_pwm_init(); + flexio_pwm_init_pins(); + + if (power_source == PWR_BATT_ONLY){ + // Turn on the red LED with low duty cycle to conserve power. + power_led_max_duty_cycle = PWR_LED_ON_BATT_BRIGHTNESS; + + } else { + // Turn on the red LED with max duty cycle when powered by USB or EC + power_led_max_duty_cycle = 100; + } + uint8_t gamma_led_dc = get_led_gamma(power_led_max_duty_cycle); + flexio_pwm_set_dutycycle(gamma_led_dc); + + i2c_initialize(); +} + +// Handle the reset button behavior, this function is called in the main task every 30ms +void handle_reset_button() +{ + // button state + static uint8_t reset_pressed = 0; + // reset button state count + static uint16_t gpio_reset_count = 0; + + // handle reset button without eventing + if (!reset_pressed && gpio_get_reset_btn_fwrd()) { +#ifdef DRAG_N_DROP_SUPPORT + if (!flash_intf_target->flash_busy()) //added checking if flashing on target is in progress +#endif + { + // Reset button pressed + target_set_state(RESET_HOLD); + reset_pressed = 1; + gpio_reset_count = 0; + main_shutdown_state = MAIN_LED_FULL_BRIGHTNESS; + } + } else if (reset_pressed && !gpio_get_reset_btn_fwrd()) { + // Reset button released + target_set_state(RESET_RUN); + reset_pressed = 0; + + if (gpio_reset_count <= RESET_SHORT_PRESS) { + main_shutdown_state = MAIN_LED_BLINK; + } + else if (gpio_reset_count < RESET_LONG_PRESS) { + // Indicate button has been released to stop to cancel the shutdown + main_shutdown_state = MAIN_LED_BLINK; + } + else if (gpio_reset_count >= RESET_LONG_PRESS) { + // Indicate the button has been released when shutdown is requested + main_shutdown_state = MAIN_SHUTDOWN_REQUESTED; + } + } else if (reset_pressed && gpio_get_reset_btn_fwrd()) { + // Reset button is still pressed + if (gpio_reset_count > RESET_SHORT_PRESS && gpio_reset_count < RESET_LONG_PRESS) { + // Enter the shutdown pending state to begin LED dimming + main_shutdown_state = MAIN_SHUTDOWN_PENDING; + } + else if (gpio_reset_count >= RESET_LONG_PRESS) { + // Enter the shutdown reached state to blink LED + main_shutdown_state = MAIN_SHUTDOWN_REACHED; + } + + // Avoid overflow, stop counting after longest event + if (gpio_reset_count <= RESET_MAX_LENGTH_PRESS) { + gpio_reset_count++; + } + } +} + +void board_30ms_hook() +{ + static uint8_t blink_in_progress = 0; + + if (go_to_sleep) { + go_to_sleep = false; + main_shutdown_state = MAIN_SHUTDOWN_REQUESTED; + } + + if (usb_state == USB_CONNECTED) { + // configure pin as GPIO + PIN_HID_LED_PORT->PCR[PIN_HID_LED_BIT] = PORT_PCR_MUX(1); + power_led_max_duty_cycle = 100; + } + else if (usb_state == USB_DISCONNECTED) { + // Disable pin + PIN_HID_LED_PORT->PCR[PIN_HID_LED_BIT] = PORT_PCR_MUX(0); + power_led_max_duty_cycle = PWR_LED_ON_BATT_BRIGHTNESS; + } + + switch (main_shutdown_state) { + case MAIN_LED_FULL_BRIGHTNESS: + // Jump power LED to full brightness + shutdown_led_dc = 100; + break; + case MAIN_SHUTDOWN_CANCEL: + main_shutdown_state = MAIN_SHUTDOWN_WAITING; + // Set the PWM value back to max duty cycle + shutdown_led_dc = power_led_max_duty_cycle; + break; + case MAIN_SHUTDOWN_PENDING: + // Fade the PWM until the board is about to be shut down + if (shutdown_led_dc > PWR_LED_FADEOUT_MIN_BRIGHTNESS) { + shutdown_led_dc--; + } + break; + case MAIN_SHUTDOWN_REACHED: + // Turn off LED to indicate we are waiting for release + shutdown_led_dc = 0; + break; + case MAIN_SHUTDOWN_REQUESTED: + // TODO: put nRF into deep sleep and wake nRF when KL27 wakes up + if (power_source == PWR_BATT_ONLY || usb_state == USB_DISCONNECTED) { + interface_power_mode = kAPP_PowerModeVlls0; + main_powerdown_event(); + } + main_shutdown_state = MAIN_SHUTDOWN_WAITING; + break; + case MAIN_SHUTDOWN_WAITING: + // Set the PWM value back to max duty cycle + shutdown_led_dc = power_led_max_duty_cycle; + break; + case MAIN_LED_BLINK: + + if (blink_in_progress) { + blink_in_progress--; + if (blink_in_progress == 5) { + shutdown_led_dc = 0; + } + } else { + blink_in_progress = 10; + shutdown_led_dc = 100; + } + + if (blink_in_progress == 0) { + main_shutdown_state = MAIN_SHUTDOWN_WAITING; + } + break; + default: + break; + } + uint8_t gamma_led_dc = get_led_gamma(shutdown_led_dc); + flexio_pwm_set_dutycycle(gamma_led_dc); +} + +void board_handle_powerdown() +{ + switch(interface_power_mode){ + case kAPP_PowerModeVlps: + power_enter_VLPS(); + break; + case kAPP_PowerModeVlls0: + power_enter_VLLS0(); + break; + default: + break; + } + + i2c_deinitialize(); + i2c_initialize(); + + usbd_connect(1); + + gpio_set_hid_led(HID_LED_DEF); +} + +uint8_t board_detect_incompatible_image(const uint8_t *data, uint32_t size) +{ + uint8_t result = 0; + + // Check difference in vectors (mem fault, bus fault, usage fault) + // If these vectors are 0, we assume it's an M0 image (not compatible) + result = memcmp(data + M0_RESERVED_VECT_OFFSET, (uint8_t[M0_RESERVED_VECT_SIZE]){0}, M0_RESERVED_VECT_SIZE); + + return result == 0; +} + +// USB HID override function return 1 if the activity is trivial or response is null uint8_t usbd_hid_no_activity(uint8_t *buf) { if(buf[0] == ID_DAP_Vendor3 && buf[1] == 0) @@ -52,3 +371,4 @@ const board_info_t g_board_info = { .prerun_board_config = prerun_board_config, .target_cfg = &target_device, }; + diff --git a/source/board/microbitv2/power.c b/source/board/microbitv2/power.c new file mode 100644 index 000000000..e6f362c46 --- /dev/null +++ b/source/board/microbitv2/power.c @@ -0,0 +1,181 @@ +/** + * @file power.c + * @brief + */ +#include "fsl_smc.h" +#include "fsl_rcm.h" +#include "fsl_llwu.h" +#include "fsl_pmc.h" +#include "fsl_port.h" +#include "fsl_clock.h" + +#include "power.h" +#include "IO_Config.h" +#include "uart.h" +#include "rl_usb.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void power_set_wakeup_config(app_power_mode_t targetMode); +static void power_mode_switch(smc_power_state_t curPowerState, app_power_mode_t targetPowerMode); +static void power_pre_switch_hook(smc_power_state_t originPowerState, app_power_mode_t targetMode); +static void power_post_switch_hook(smc_power_state_t originPowerState, app_power_mode_t targetMode); +static void power_enter_mode(app_power_mode_t targetPowerMode); + +/******************************************************************************* + * Code + ******************************************************************************/ +void LLWU_IRQHandler(void) +{ + /* If wakeup by external pin BTN_NOT_PRESSED. */ + if (LLWU_GetExternalWakeupPinFlag(LLWU, PIN_SW_RESET_LLWU_PIN)) + { + PORT_SetPinInterruptConfig(PIN_SW_RESET_PORT, PIN_SW_RESET_BIT, kPORT_InterruptOrDMADisabled); + PORT_ClearPinsInterruptFlags(PIN_SW_RESET_PORT, (1U << PIN_SW_RESET_BIT)); + LLWU_ClearExternalWakeupPinFlag(LLWU, PIN_SW_RESET_LLWU_PIN); + } + /* If wakeup by external pin WAKE_ON_EDGE. */ + if (LLWU_GetExternalWakeupPinFlag(LLWU, PIN_WAKE_ON_EDGE_LLWU_PIN)) + { + PORT_ClearPinsInterruptFlags(PIN_WAKE_ON_EDGE_PORT, (1U << PIN_WAKE_ON_EDGE_BIT)); + LLWU_ClearExternalWakeupPinFlag(LLWU, PIN_WAKE_ON_EDGE_LLWU_PIN); + } +} + +void PORTCD_IRQHandler(void) +{ + if ((1U << PIN_SW_RESET_BIT) & PORT_GetPinsInterruptFlags(PIN_SW_RESET_PORT)) + { + /* Disable interrupt. */ + PORT_SetPinInterruptConfig(PIN_SW_RESET_PORT, PIN_SW_RESET_BIT, kPORT_InterruptOrDMADisabled); + PORT_ClearPinsInterruptFlags(PIN_SW_RESET_PORT, (1U << PIN_SW_RESET_BIT)); + } + if ((1U << PIN_WAKE_ON_EDGE_BIT) & PORT_GetPinsInterruptFlags(PIN_WAKE_ON_EDGE_PORT)) + { + PORT_ClearPinsInterruptFlags(PIN_WAKE_ON_EDGE_PORT, (1U << PIN_WAKE_ON_EDGE_BIT)); + + /* Reset USB on cable detach (VBUS falling edge) */ + USBD_Reset(); + usbd_reset_core(); + } +} + +void power_init(void) +{ + // Configure pin as GPIO + PORT_SetPinMux(PIN_WAKE_ON_EDGE_PORT, PIN_WAKE_ON_EDGE_BIT, kPORT_MuxAsGpio); + + /* Power related. */ + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); + if (kRCM_SourceWakeup & RCM_GetPreviousResetSources(RCM)) /* Wakeup from VLLS. */ + { + PMC_ClearPeriphIOIsolationFlag(PMC); + NVIC_ClearPendingIRQ(LLWU_IRQn); + } + + /* Enable rising edge interrupt on WAKE_ON_EDGE pin (VBUS falling edge) to detect USB detach */ + PORT_SetPinInterruptConfig(PIN_WAKE_ON_EDGE_PORT, PIN_WAKE_ON_EDGE_BIT, kPORT_InterruptRisingEdge); + + NVIC_EnableIRQ(LLWU_IRQn); + NVIC_EnableIRQ(PORTC_PORTD_IRQn); +} + +void power_enter_VLLS0() +{ + power_enter_mode(kAPP_PowerModeVlls0); +} + +void power_enter_VLPS() +{ + power_enter_mode(kAPP_PowerModeVlps); +} + +static void power_enter_mode(app_power_mode_t targetPowerMode) +{ + smc_power_state_t curPowerState = (smc_power_state_t) 0; + + curPowerState = SMC_GetPowerModeState(SMC); + + if ((targetPowerMode > kAPP_PowerModeMin) && (targetPowerMode < kAPP_PowerModeMax)) + { + power_pre_switch_hook(curPowerState, targetPowerMode); + power_set_wakeup_config(targetPowerMode); + power_mode_switch(curPowerState, targetPowerMode); + power_post_switch_hook(curPowerState, targetPowerMode); + } +} + +static void power_set_wakeup_config(app_power_mode_t targetMode) +{ + PORT_SetPinInterruptConfig(PIN_SW_RESET_PORT, PIN_SW_RESET_BIT, PIN_SW_RESET_PORT_WAKEUP_TYPE); + PORT_SetPinInterruptConfig(PIN_WAKE_ON_EDGE_PORT, PIN_WAKE_ON_EDGE_BIT, PIN_WAKE_ON_EDGE_PORT_WAKEUP_TYPE); + + /* If targetMode is VLLS/LLS, setup LLWU. */ + if ((kAPP_PowerModeWait != targetMode) && (kAPP_PowerModeVlpw != targetMode) && + (kAPP_PowerModeVlps != targetMode) && (kAPP_PowerModeStop != targetMode)) + { + LLWU_SetExternalWakeupPinMode(LLWU, PIN_SW_RESET_LLWU_PIN, PIN_SW_RESET_LLWU_WAKEUP_TYPE); + LLWU_SetExternalWakeupPinMode(LLWU, PIN_WAKE_ON_EDGE_LLWU_PIN, PIN_WAKE_ON_EDGE_LLWU_WAKEUP_TYPE); + NVIC_EnableIRQ(LLWU_IRQn); + } +} + +static void power_mode_switch(smc_power_state_t curPowerState, app_power_mode_t targetPowerMode) +{ + smc_power_mode_vlls_config_t vlls_config; + vlls_config.enablePorDetectInVlls0 = true; + + switch (targetPowerMode) + { + case kAPP_PowerModeVlps: + SMC_PreEnterStopModes(); + SMC_SetPowerModeVlps(SMC); + SMC_PostExitStopModes(); + break; + + case kAPP_PowerModeVlls0: + vlls_config.subMode = kSMC_StopSub0; + SMC_PreEnterStopModes(); + SMC_SetPowerModeVlls(SMC, &vlls_config); + SMC_PostExitStopModes(); + break; + + default: + break; + } +} + +static void power_pre_switch_hook(smc_power_state_t originPowerState, app_power_mode_t targetMode) +{ + /* Wait for debug console output finished. */ + while (!(LPUART_STAT_TC_MASK & UART->STAT)) + { + } + uart_uninitialize(); + + /* + * Set pin for current leakage. + * UART RX pin: Set to pinmux to disable. + * UART TX pin: Don't need to change. + */ + PORT_SetPinMux(UART_PORT, PIN_UART_RX_BIT, kPORT_PinDisabledOrAnalog); + PORT_SetPinMux(PIN_RED_LED_PORT, PIN_RED_LED_BIT, kPORT_PinDisabledOrAnalog); + PORT_SetPinMux(PIN_HID_LED_PORT, PIN_HID_LED_BIT, kPORT_PinDisabledOrAnalog); +} + +static void power_post_switch_hook(smc_power_state_t originPowerState, app_power_mode_t targetMode) +{ + /* + * UART RX pin is set to disable for current leakage, need to re-configure pinmux. + * UART TX pin: Don't need to change. + */ + PORT_SetPinMux(UART_PORT, PIN_UART_RX_BIT, (port_mux_t)PIN_UART_RX_MUX_ALT); + PORT_SetPinMux(PIN_RED_LED_PORT, PIN_RED_LED_BIT, kPORT_MuxAlt3); + PORT_SetPinMux(PIN_HID_LED_PORT, PIN_HID_LED_BIT, kPORT_PinDisabledOrAnalog); + + uart_initialize(); + + /* Change to rising edge interrupt on WAKE_ON_EDGE pin (VBUS falling edge) to detect USB detach */ + PORT_SetPinInterruptConfig(PIN_WAKE_ON_EDGE_PORT, PIN_WAKE_ON_EDGE_BIT, kPORT_InterruptRisingEdge); +} diff --git a/source/board/microbitv2/power.h b/source/board/microbitv2/power.h new file mode 100644 index 000000000..629924b70 --- /dev/null +++ b/source/board/microbitv2/power.h @@ -0,0 +1,32 @@ +#ifndef POWER_H_ +#define POWER_H_ + +#include "fsl_common.h" +#include "fsl_smc.h" + +/* Power mode definition used in application. */ +typedef enum _app_power_mode +{ + kAPP_PowerModeMin = 0, + kAPP_PowerModeRun, /* Normal RUN mode */ + kAPP_PowerModeWait, /* WAIT mode. */ + kAPP_PowerModeStop, /* STOP mode. */ + kAPP_PowerModeVlpr, /* VLPR mode. */ + kAPP_PowerModeVlpw, /* VLPW mode. */ + kAPP_PowerModeVlps, /* VLPS mode. */ + kAPP_PowerModeLls, /* LLS mode. */ + kAPP_PowerModeVlls0, /* VLLS0 mode. */ + kAPP_PowerModeVlls1, /* VLLS1 mode. */ + kAPP_PowerModeVlls3, /* VLLS3 mode. */ + kAPP_PowerModeMax +} app_power_mode_t; + +void power_init(void); + +/* Lowest power mode available in KL27*/ +void power_enter_VLLS0(void); + +/* Lowest power mode that allows I2C operation with address match wakeup */ +void power_enter_VLPS(void); + +#endif /* POWER_H_ */ diff --git a/source/board/microbitv2/pwr_mon.c b/source/board/microbitv2/pwr_mon.c new file mode 100644 index 000000000..3d05c7c6c --- /dev/null +++ b/source/board/microbitv2/pwr_mon.c @@ -0,0 +1,103 @@ +/** + * @file power_monitor.c + * @brief + */ + +#include "pwr_mon.h" +#include "adc.h" +#include "fsl_adc16.h" +#include "fsl_pmc.h" +#include "fsl_port.h" +#include "fsl_gpio.h" + +#define ADC_VBG_CHANNEL 27U +#define ADC_VBG_MUX (kADC16_ChannelMuxA) +#define ADC_VREFH_CHANNEL 29U +#define ADC_VREFH_MUX (kADC16_ChannelMuxA) + +#define ADC_MV_TO_ADC(x) ((x) * 0xFFF / 3300) // Convert mV to ADC value (12bit and 3.3V reference) + +void pwr_mon_bandgap_init(void); +uint32_t pwr_mon_read_vbg(uint32_t channelGroup); +uint32_t pwr_mon_adc_to_mv(uint32_t raw_adc); + +void pwr_mon_init(void) +{ + gpio_pin_config_t pin_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 0U + }; + + adc_init(); + + // Configure VMON_BAT and RUN_VBAT_SENSE + GPIO_PinInit(PIN_RUN_VBAT_SENSE_GPIO, PIN_RUN_VBAT_SENSE_BIT, &pin_config); + PORT_SetPinMux(PIN_RUN_VBAT_SENSE_PORT, PIN_RUN_VBAT_SENSE_BIT, kPORT_MuxAsGpio); + PORT_SetPinMux(PIN_VMON_BAT_PORT, PIN_VMON_BAT_BIT, PIN_VMON_BAT_ALT_MODE); +} + +power_source_t pwr_mon_get_power_source(void) { + power_source_t power_source = PWR_SOURCE_NONE; + uint32_t bat_voltage_mv = 0; + // Detect if device is battery powered + GPIO_PinWrite(PIN_RUN_VBAT_SENSE_GPIO, PIN_RUN_VBAT_SENSE_BIT, 1); + // Add a ~3ms delay to allow the 100nF capacitors to charge to about 3*RC. + // 3 clock cycles per loop at -O2 ARMCC optimization + for (uint32_t count = 48000; count > 0UL; count--); + uint32_t bat_adc = adc_read_channel(0, PIN_VMON_BAT_ADC_CH, PIN_VMON_BAT_ADC_MUX); + GPIO_PinWrite(PIN_RUN_VBAT_SENSE_GPIO, PIN_RUN_VBAT_SENSE_BIT, 0); + + bool usb_on = (((PIN_WAKE_ON_EDGE_GPIO->PDIR) >> PIN_WAKE_ON_EDGE_BIT) & 0x01U) ? false : true; + + // Compensate for voltage divider with ratio of 11 + bat_adc = bat_adc * 11; + + bat_voltage_mv = pwr_mon_adc_to_mv(bat_adc); + + if (usb_on == true && bat_voltage_mv < (2500)) { + power_source = PWR_USB_ONLY; + } else if (usb_on == true && bat_voltage_mv >= (2500)) { + power_source = PWR_USB_AND_BATT; + } else if (usb_on == false && bat_voltage_mv >= (2500)) { + power_source = PWR_BATT_ONLY; + } else if (usb_on == false && bat_voltage_mv < (2500)) { + power_source = PWR_SOURCE_NONE; + } + + return power_source; +} + +uint32_t pwr_mon_vcc_mv(void) { + // ADC read the Vref (same as Vcc) and the Vbg 1V internal reference + uint32_t vref_high = adc_read_channel(0, ADC_VREFH_CHANNEL, ADC_VREFH_MUX); + uint32_t ref_volt = pwr_mon_read_vbg(0); + + // Reference voltage is 1V, scale to millivolts + return vref_high * 1000 / ref_volt; +} + +void pwr_mon_bandgap_init(void) { + pmc_bandgap_buffer_config_t pmcBandgapConfig; + pmcBandgapConfig.enable = true; + pmcBandgapConfig.enableInLowPowerMode = true; + PMC_ConfigureBandgapBuffer(PMC, &pmcBandgapConfig); +} + +uint32_t pwr_mon_read_vbg(uint32_t channelGroup) { + // Ensure the Vbg is enabled from first use only + static bool bandgap_enabled = false; + if (!bandgap_enabled) { + pwr_mon_bandgap_init(); + bandgap_enabled = true; + } + return adc_read_channel(channelGroup, ADC_VBG_CHANNEL, ADC_VBG_MUX); +} + +uint32_t pwr_mon_adc_to_mv(uint32_t raw_adc) +{ + // ADC read Vbg, a 1V internal reference + uint32_t ref_volt_read = pwr_mon_read_vbg(0); + + // Scale ADC read out to millivolts + return (raw_adc * 1000) / ref_volt_read; +} diff --git a/source/board/microbitv2/pwr_mon.h b/source/board/microbitv2/pwr_mon.h new file mode 100644 index 000000000..15797386c --- /dev/null +++ b/source/board/microbitv2/pwr_mon.h @@ -0,0 +1,31 @@ +/** + * @file power_monitor.h + * @brief + */ + +#ifndef PWR_MON_H +#define PWR_MON_H + +#include "IO_Config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PWR_SOURCE_NONE = 0, + PWR_USB_ONLY, + PWR_BATT_ONLY, + PWR_USB_AND_BATT +} power_source_t; + +void pwr_mon_init(void); +power_source_t pwr_mon_get_power_source(void); +uint32_t pwr_mon_vcc_mv(void); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/source/hic_hal/adc.h b/source/hic_hal/adc.h new file mode 100644 index 000000000..6045b1da6 --- /dev/null +++ b/source/hic_hal/adc.h @@ -0,0 +1,23 @@ +/** + * @file adc.h + * @brief + */ + +#ifndef ADC_H +#define ADC_H + +#include "IO_Config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void adc_init(void); +void adc_init_pins(void); +uint32_t adc_read_channel(uint32_t channelGroup, uint32_t channelNumber, uint32_t channelMux); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/source/hic_hal/freescale/kl27z/adc.c b/source/hic_hal/freescale/kl27z/adc.c new file mode 100644 index 000000000..62c3aae2b --- /dev/null +++ b/source/hic_hal/freescale/kl27z/adc.c @@ -0,0 +1,46 @@ +/** + * @file adc.c + * @brief + */ + +#include "adc.h" +#include "fsl_adc16.h" + +#define ADC_BASE ADC0 + +void adc_init(void) +{ + adc16_config_t adc16ConfigStruct; + adc16ConfigStruct.referenceVoltageSource = kADC16_ReferenceVoltageSourceVref; + adc16ConfigStruct.clockSource = kADC16_ClockSourceAsynchronousClock; + adc16ConfigStruct.enableAsynchronousClock = true; + adc16ConfigStruct.clockDivider = kADC16_ClockDivider1; + adc16ConfigStruct.resolution = kADC16_ResolutionSE12Bit; + adc16ConfigStruct.longSampleMode = kADC16_LongSampleCycle24; + adc16ConfigStruct.enableHighSpeed = false; + adc16ConfigStruct.enableLowPower = false; + adc16ConfigStruct.enableContinuousConversion = false; + //ADC16_GetDefaultConfig(&adc16ConfigStruct); + ADC16_Init(ADC_BASE, &adc16ConfigStruct); + ADC16_SetHardwareAverage(ADC_BASE, kADC16_HardwareAverageCount8); + ADC16_DoAutoCalibration(ADC_BASE); +} + +void adc_init_pins() +{ + +} + +uint32_t adc_read_channel(uint32_t channelGroup, uint32_t channelNumber, uint32_t channelMux) +{ + adc16_channel_config_t adc16ChannelConfigStruct; + adc16ChannelConfigStruct.channelNumber = channelNumber; + adc16ChannelConfigStruct.enableInterruptOnConversionCompleted = false; + adc16ChannelConfigStruct.enableDifferentialConversion = false; + + ADC16_SetChannelMuxMode(ADC_BASE, (adc16_channel_mux_mode_t)channelMux); + ADC16_SetChannelConfig(ADC_BASE, channelGroup, &adc16ChannelConfigStruct); + while (0U == (kADC16_ChannelConversionDoneFlag & + ADC16_GetChannelStatusFlags(ADC_BASE, channelGroup))); + return ADC16_GetChannelConversionValue(ADC_BASE, channelGroup); +} diff --git a/source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s b/source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s index 06f59c896..910b90bab 100644 --- a/source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s +++ b/source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s @@ -339,6 +339,19 @@ SysTick_Handler\ EXPORT SysTick_Handler [WEAK] B . ENDP +I2C0_IRQHandler\ + PROC + EXPORT I2C0_IRQHandler [WEAK] + LDR R0, =I2C0_DriverIRQHandler + BX R0 + ENDP + +I2C1_IRQHandler\ + PROC + EXPORT I2C1_IRQHandler [WEAK] + LDR R0, =I2C1_DriverIRQHandler + BX R0 + ENDP Default_Handler\ PROC EXPORT DMA0_IRQHandler [WEAK] @@ -349,8 +362,8 @@ Default_Handler\ EXPORT FTFA_IRQHandler [WEAK] EXPORT PMC_IRQHandler [WEAK] EXPORT LLWU_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C0_DriverIRQHandler [WEAK] + EXPORT I2C1_DriverIRQHandler [WEAK] EXPORT SPI0_IRQHandler [WEAK] EXPORT SPI1_IRQHandler [WEAK] EXPORT LPUART0_IRQHandler [WEAK] @@ -382,8 +395,8 @@ Reserved20_IRQHandler FTFA_IRQHandler PMC_IRQHandler LLWU_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler +I2C0_DriverIRQHandler +I2C1_DriverIRQHandler SPI0_IRQHandler SPI1_IRQHandler LPUART0_IRQHandler diff --git a/source/hic_hal/freescale/kl27z/fsl_adc16.c b/source/hic_hal/freescale/kl27z/fsl_adc16.c new file mode 100644 index 000000000..db5b03c20 --- /dev/null +++ b/source/hic_hal/freescale/kl27z/fsl_adc16.c @@ -0,0 +1,370 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_adc16.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for ADC16 module. + * + * @param base ADC16 peripheral base address + */ +static uint32_t ADC16_GetInstance(ADC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to ADC16 bases for each instance. */ +static ADC_Type *const s_adc16Bases[] = ADC_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to ADC16 clocks for each instance. */ +static const clock_ip_name_t s_adc16Clocks[] = ADC16_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t ADC16_GetInstance(ADC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_ADC16_COUNT; instance++) + { + if (s_adc16Bases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_ADC16_COUNT); + + return instance; +} + +void ADC16_Init(ADC_Type *base, const adc16_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_adc16Clocks[ADC16_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* ADCx_CFG1. */ + tmp32 = ADC_CFG1_ADICLK(config->clockSource) | ADC_CFG1_MODE(config->resolution); + if (kADC16_LongSampleDisabled != config->longSampleMode) + { + tmp32 |= ADC_CFG1_ADLSMP_MASK; + } + tmp32 |= ADC_CFG1_ADIV(config->clockDivider); + if (config->enableLowPower) + { + tmp32 |= ADC_CFG1_ADLPC_MASK; + } + base->CFG1 = tmp32; + + /* ADCx_CFG2. */ + tmp32 = base->CFG2 & ~(ADC_CFG2_ADACKEN_MASK | ADC_CFG2_ADHSC_MASK | ADC_CFG2_ADLSTS_MASK); + if (kADC16_LongSampleDisabled != config->longSampleMode) + { + tmp32 |= ADC_CFG2_ADLSTS(config->longSampleMode); + } + if (config->enableHighSpeed) + { + tmp32 |= ADC_CFG2_ADHSC_MASK; + } + if (config->enableAsynchronousClock) + { + tmp32 |= ADC_CFG2_ADACKEN_MASK; + } + base->CFG2 = tmp32; + + /* ADCx_SC2. */ + tmp32 = base->SC2 & ~(ADC_SC2_REFSEL_MASK); + tmp32 |= ADC_SC2_REFSEL(config->referenceVoltageSource); + base->SC2 = tmp32; + + /* ADCx_SC3. */ + if (config->enableContinuousConversion) + { + base->SC3 |= ADC_SC3_ADCO_MASK; + } + else + { + base->SC3 &= ~ADC_SC3_ADCO_MASK; + } +} + +void ADC16_Deinit(ADC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_adc16Clocks[ADC16_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void ADC16_GetDefaultConfig(adc16_config_t *config) +{ + assert(NULL != config); + + config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref; + config->clockSource = kADC16_ClockSourceAsynchronousClock; + config->enableAsynchronousClock = true; + config->clockDivider = kADC16_ClockDivider8; + config->resolution = kADC16_ResolutionSE12Bit; + config->longSampleMode = kADC16_LongSampleDisabled; + config->enableHighSpeed = false; + config->enableLowPower = false; + config->enableContinuousConversion = false; +} + +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION +status_t ADC16_DoAutoCalibration(ADC_Type *base) +{ + bool bHWTrigger = false; + volatile uint32_t tmp32; /* 'volatile' here is for the dummy read of ADCx_R[0] register. */ + status_t status = kStatus_Success; + + /* The calibration would be failed when in hardwar mode. + * Remember the hardware trigger state here and restore it later if the hardware trigger is enabled.*/ + if (0U != (ADC_SC2_ADTRG_MASK & base->SC2)) + { + bHWTrigger = true; + base->SC2 &= ~ADC_SC2_ADTRG_MASK; + } + + /* Clear the CALF and launch the calibration. */ + base->SC3 |= ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK; + while (0U == (kADC16_ChannelConversionDoneFlag & ADC16_GetChannelStatusFlags(base, 0U))) + { + /* Check the CALF when the calibration is active. */ + if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base))) + { + status = kStatus_Fail; + break; + } + } + tmp32 = base->R[0]; /* Dummy read to clear COCO caused by calibration. */ + + /* Restore the hardware trigger setting if it was enabled before. */ + if (bHWTrigger) + { + base->SC2 |= ADC_SC2_ADTRG_MASK; + } + /* Check the CALF at the end of calibration. */ + if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base))) + { + status = kStatus_Fail; + } + if (kStatus_Success != status) /* Check if the calibration process is succeed. */ + { + return status; + } + + /* Calculate the calibration values. */ + tmp32 = base->CLP0 + base->CLP1 + base->CLP2 + base->CLP3 + base->CLP4 + base->CLPS; + tmp32 = 0x8000U | (tmp32 >> 1U); + base->PG = tmp32; + +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + tmp32 = base->CLM0 + base->CLM1 + base->CLM2 + base->CLM3 + base->CLM4 + base->CLMS; + tmp32 = 0x8000U | (tmp32 >> 1U); + base->MG = tmp32; +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ + + return kStatus_Success; +} +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ + +#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT +void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode) +{ + if (kADC16_ChannelMuxA == mode) + { + base->CFG2 &= ~ADC_CFG2_MUXSEL_MASK; + } + else /* kADC16_ChannelMuxB. */ + { + base->CFG2 |= ADC_CFG2_MUXSEL_MASK; + } +} +#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ + +void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config) +{ + uint32_t tmp32 = base->SC2 & ~(ADC_SC2_ACFE_MASK | ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK); + + if (!config) /* Pass "NULL" to disable the feature. */ + { + base->SC2 = tmp32; + return; + } + /* Enable the feature. */ + tmp32 |= ADC_SC2_ACFE_MASK; + + /* Select the hardware compare working mode. */ + switch (config->hardwareCompareMode) + { + case kADC16_HardwareCompareMode0: + break; + case kADC16_HardwareCompareMode1: + tmp32 |= ADC_SC2_ACFGT_MASK; + break; + case kADC16_HardwareCompareMode2: + tmp32 |= ADC_SC2_ACREN_MASK; + break; + case kADC16_HardwareCompareMode3: + tmp32 |= ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK; + break; + default: + break; + } + base->SC2 = tmp32; + + /* Load the compare values. */ + base->CV1 = ADC_CV1_CV(config->value1); + base->CV2 = ADC_CV2_CV(config->value2); +} + +#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE +void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode) +{ + uint32_t tmp32 = base->SC3 & ~(ADC_SC3_AVGE_MASK | ADC_SC3_AVGS_MASK); + + if (kADC16_HardwareAverageDisabled != mode) + { + tmp32 |= ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(mode); + } + base->SC3 = tmp32; +} +#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ + +#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA +void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config) +{ + uint32_t tmp32; + + if (!config) /* Passing "NULL" is to disable the feature. */ + { + base->PGA = 0U; + return; + } + + /* Enable the PGA and set the gain value. */ + tmp32 = ADC_PGA_PGAEN_MASK | ADC_PGA_PGAG(config->pgaGain); + + /* Configure the misc features for PGA. */ + if (config->enableRunInNormalMode) + { + tmp32 |= ADC_PGA_PGALPb_MASK; + } +#if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING + if (config->disablePgaChopping) + { + tmp32 |= ADC_PGA_PGACHPb_MASK; + } +#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */ +#if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT + if (config->enableRunInOffsetMeasurement) + { + tmp32 |= ADC_PGA_PGAOFSM_MASK; + } +#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */ + base->PGA = tmp32; +} +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +uint32_t ADC16_GetStatusFlags(ADC_Type *base) +{ + uint32_t ret = 0; + + if (0U != (base->SC2 & ADC_SC2_ADACT_MASK)) + { + ret |= kADC16_ActiveFlag; + } +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION + if (0U != (base->SC3 & ADC_SC3_CALF_MASK)) + { + ret |= kADC16_CalibrationFailedFlag; + } +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ + return ret; +} + +void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask) +{ +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION + if (0U != (mask & kADC16_CalibrationFailedFlag)) + { + base->SC3 |= ADC_SC3_CALF_MASK; + } +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ +} + +void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config) +{ + assert(channelGroup < ADC_SC1_COUNT); + assert(NULL != config); + + uint32_t sc1 = ADC_SC1_ADCH(config->channelNumber); /* Set the channel number. */ + +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + /* Enable the differential conversion. */ + if (config->enableDifferentialConversion) + { + sc1 |= ADC_SC1_DIFF_MASK; + } +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ + /* Enable the interrupt when the conversion is done. */ + if (config->enableInterruptOnConversionCompleted) + { + sc1 |= ADC_SC1_AIEN_MASK; + } + base->SC1[channelGroup] = sc1; +} + +uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup) +{ + assert(channelGroup < ADC_SC1_COUNT); + + uint32_t ret = 0U; + + if (0U != (base->SC1[channelGroup] & ADC_SC1_COCO_MASK)) + { + ret |= kADC16_ChannelConversionDoneFlag; + } + return ret; +} diff --git a/source/hic_hal/freescale/kl27z/fsl_adc16.h b/source/hic_hal/freescale/kl27z/fsl_adc16.h new file mode 100644 index 000000000..fa9f20ed7 --- /dev/null +++ b/source/hic_hal/freescale/kl27z/fsl_adc16.h @@ -0,0 +1,526 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_ADC16_H_ +#define _FSL_ADC16_H_ + +#include "fsl_common.h" +#include "fsl_clock.h" + +/*! + * @addtogroup adc16 + * @{ + */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief ADC16 driver version 2.0.0. */ +#define FSL_ADC16_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @brief Channel status flags. + */ +enum _adc16_channel_status_flags +{ + kADC16_ChannelConversionDoneFlag = ADC_SC1_COCO_MASK, /*!< Conversion done. */ +}; + +/*! + * @brief Converter status flags. + */ +enum _adc16_status_flags +{ + kADC16_ActiveFlag = ADC_SC2_ADACT_MASK, /*!< Converter is active. */ +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION + kADC16_CalibrationFailedFlag = ADC_SC3_CALF_MASK, /*!< Calibration is failed. */ +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ +}; + +#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT +/*! + * @brief Channel multiplexer mode for each channel. + * + * For some ADC16 channels, there are two pin selections in channel multiplexer. For example, ADC0_SE4a and ADC0_SE4b + * are the different channels that share the same channel number. + */ +typedef enum _adc_channel_mux_mode +{ + kADC16_ChannelMuxA = 0U, /*!< For channel with channel mux a. */ + kADC16_ChannelMuxB = 1U, /*!< For channel with channel mux b. */ +} adc16_channel_mux_mode_t; +#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ + +/*! + * @brief Clock divider for the converter. + */ +typedef enum _adc16_clock_divider +{ + kADC16_ClockDivider1 = 0U, /*!< For divider 1 from the input clock to the module. */ + kADC16_ClockDivider2 = 1U, /*!< For divider 2 from the input clock to the module. */ + kADC16_ClockDivider4 = 2U, /*!< For divider 4 from the input clock to the module. */ + kADC16_ClockDivider8 = 3U, /*!< For divider 8 from the input clock to the module. */ +} adc16_clock_divider_t; + +/*! + *@brief Converter's resolution. + */ +typedef enum _adc16_resolution +{ + /* This group of enumeration is for internal use which is related to register setting. */ + kADC16_Resolution8or9Bit = 0U, /*!< Single End 8-bit or Differential Sample 9-bit. */ + kADC16_Resolution12or13Bit = 1U, /*!< Single End 12-bit or Differential Sample 13-bit. */ + kADC16_Resolution10or11Bit = 2U, /*!< Single End 10-bit or Differential Sample 11-bit. */ + + /* This group of enumeration is for a public user. */ + kADC16_ResolutionSE8Bit = kADC16_Resolution8or9Bit, /*!< Single End 8-bit. */ + kADC16_ResolutionSE12Bit = kADC16_Resolution12or13Bit, /*!< Single End 12-bit. */ + kADC16_ResolutionSE10Bit = kADC16_Resolution10or11Bit, /*!< Single End 10-bit. */ +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + kADC16_ResolutionDF9Bit = kADC16_Resolution8or9Bit, /*!< Differential Sample 9-bit. */ + kADC16_ResolutionDF13Bit = kADC16_Resolution12or13Bit, /*!< Differential Sample 13-bit. */ + kADC16_ResolutionDF11Bit = kADC16_Resolution10or11Bit, /*!< Differential Sample 11-bit. */ +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ + +#if defined(FSL_FEATURE_ADC16_MAX_RESOLUTION) && (FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U) + /* 16-bit is supported by default. */ + kADC16_Resolution16Bit = 3U, /*!< Single End 16-bit or Differential Sample 16-bit. */ + kADC16_ResolutionSE16Bit = kADC16_Resolution16Bit, /*!< Single End 16-bit. */ +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + kADC16_ResolutionDF16Bit = kADC16_Resolution16Bit, /*!< Differential Sample 16-bit. */ +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ +#endif /* FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U */ +} adc16_resolution_t; + +/*! + * @brief Clock source. + */ +typedef enum _adc16_clock_source +{ + kADC16_ClockSourceAlt0 = 0U, /*!< Selection 0 of the clock source. */ + kADC16_ClockSourceAlt1 = 1U, /*!< Selection 1 of the clock source. */ + kADC16_ClockSourceAlt2 = 2U, /*!< Selection 2 of the clock source. */ + kADC16_ClockSourceAlt3 = 3U, /*!< Selection 3 of the clock source. */ + + /* Chip defined clock source */ + kADC16_ClockSourceAsynchronousClock = kADC16_ClockSourceAlt3, /*!< Using internal asynchronous clock. */ +} adc16_clock_source_t; + +/*! + * @brief Long sample mode. + */ +typedef enum _adc16_long_sample_mode +{ + kADC16_LongSampleCycle24 = 0U, /*!< 20 extra ADCK cycles, 24 ADCK cycles total. */ + kADC16_LongSampleCycle16 = 1U, /*!< 12 extra ADCK cycles, 16 ADCK cycles total. */ + kADC16_LongSampleCycle10 = 2U, /*!< 6 extra ADCK cycles, 10 ADCK cycles total. */ + kADC16_LongSampleCycle6 = 3U, /*!< 2 extra ADCK cycles, 6 ADCK cycles total. */ + kADC16_LongSampleDisabled = 4U, /*!< Disable the long sample feature. */ +} adc16_long_sample_mode_t; + +/*! + * @brief Reference voltage source. + */ +typedef enum _adc16_reference_voltage_source +{ + kADC16_ReferenceVoltageSourceVref = 0U, /*!< For external pins pair of VrefH and VrefL. */ + kADC16_ReferenceVoltageSourceValt = 1U, /*!< For alternate reference pair of ValtH and ValtL. */ +} adc16_reference_voltage_source_t; + +#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE +/*! + * @brief Hardware average mode. + */ +typedef enum _adc16_hardware_average_mode +{ + kADC16_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */ + kADC16_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */ + kADC16_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */ + kADC16_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */ + kADC16_HardwareAverageDisabled = 4U, /*!< Disable the hardware average feature.*/ +} adc16_hardware_average_mode_t; +#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ + +/*! + * @brief Hardware compare mode. + */ +typedef enum _adc16_hardware_compare_mode +{ + kADC16_HardwareCompareMode0 = 0U, /*!< x < value1. */ + kADC16_HardwareCompareMode1 = 1U, /*!< x > value1. */ + kADC16_HardwareCompareMode2 = 2U, /*!< if value1 <= value2, then x < value1 || x > value2; + else, value1 > x > value2. */ + kADC16_HardwareCompareMode3 = 3U, /*!< if value1 <= value2, then value1 <= x <= value2; + else x >= value1 || x <= value2. */ +} adc16_hardware_compare_mode_t; + +#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA +/*! + * @brief PGA's Gain mode. + */ +typedef enum _adc16_pga_gain +{ + kADC16_PGAGainValueOf1 = 0U, /*!< For amplifier gain of 1. */ + kADC16_PGAGainValueOf2 = 1U, /*!< For amplifier gain of 2. */ + kADC16_PGAGainValueOf4 = 2U, /*!< For amplifier gain of 4. */ + kADC16_PGAGainValueOf8 = 3U, /*!< For amplifier gain of 8. */ + kADC16_PGAGainValueOf16 = 4U, /*!< For amplifier gain of 16. */ + kADC16_PGAGainValueOf32 = 5U, /*!< For amplifier gain of 32. */ + kADC16_PGAGainValueOf64 = 6U, /*!< For amplifier gain of 64. */ +} adc16_pga_gain_t; +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +/*! + * @brief ADC16 converter configuration. + */ +typedef struct _adc16_config +{ + adc16_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */ + adc16_clock_source_t clockSource; /*!< Select the input clock source to converter. */ + bool enableAsynchronousClock; /*!< Enable the asynchronous clock output. */ + adc16_clock_divider_t clockDivider; /*!< Select the divider of input clock source. */ + adc16_resolution_t resolution; /*!< Select the sample resolution mode. */ + adc16_long_sample_mode_t longSampleMode; /*!< Select the long sample mode. */ + bool enableHighSpeed; /*!< Enable the high-speed mode. */ + bool enableLowPower; /*!< Enable low power. */ + bool enableContinuousConversion; /*!< Enable continuous conversion mode. */ +} adc16_config_t; + +/*! + * @brief ADC16 Hardware comparison configuration. + */ +typedef struct _adc16_hardware_compare_config +{ + adc16_hardware_compare_mode_t hardwareCompareMode; /*!< Select the hardware compare mode. + See "adc16_hardware_compare_mode_t". */ + int16_t value1; /*!< Setting value1 for hardware compare mode. */ + int16_t value2; /*!< Setting value2 for hardware compare mode. */ +} adc16_hardware_compare_config_t; + +/*! + * @brief ADC16 channel conversion configuration. + */ +typedef struct _adc16_channel_config +{ + uint32_t channelNumber; /*!< Setting the conversion channel number. The available range is 0-31. + See channel connection information for each chip in Reference + Manual document. */ + bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */ +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + bool enableDifferentialConversion; /*!< Using Differential sample mode. */ +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ +} adc16_channel_config_t; + +#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA +/*! + * @brief ADC16 programmable gain amplifier configuration. + */ +typedef struct _adc16_pga_config +{ + adc16_pga_gain_t pgaGain; /*!< Setting PGA gain. */ + bool enableRunInNormalMode; /*!< Enable PGA working in normal mode, or low power mode by default. */ +#if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING + bool disablePgaChopping; /*!< Disable the PGA chopping function. + The PGA employs chopping to remove/reduce offset and 1/f noise and offers + an offset measurement configuration that aids the offset calibration. */ +#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */ +#if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT + bool enableRunInOffsetMeasurement; /*!< Enable the PGA working in offset measurement mode. + When this feature is enabled, the PGA disconnects itself from the external + inputs and auto-configures into offset measurement mode. With this field + set, run the ADC in the recommended settings and enable the maximum hardware + averaging to get the PGA offset number. The output is the + (PGA offset * (64+1)) for the given PGA setting. */ +#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */ +} adc16_pga_config_t; +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the ADC16 module. + * + * @param base ADC16 peripheral base address. + * @param config Pointer to configuration structure. See "adc16_config_t". + */ +void ADC16_Init(ADC_Type *base, const adc16_config_t *config); + +/*! + * @brief De-initializes the ADC16 module. + * + * @param base ADC16 peripheral base address. + */ +void ADC16_Deinit(ADC_Type *base); + +/*! + * @brief Gets an available pre-defined settings for the converter's configuration. + * + * This function initializes the converter configuration structure with available settings. The default values are as follows. + * @code + * config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref; + * config->clockSource = kADC16_ClockSourceAsynchronousClock; + * config->enableAsynchronousClock = true; + * config->clockDivider = kADC16_ClockDivider8; + * config->resolution = kADC16_ResolutionSE12Bit; + * config->longSampleMode = kADC16_LongSampleDisabled; + * config->enableHighSpeed = false; + * config->enableLowPower = false; + * config->enableContinuousConversion = false; + * @endcode + * @param config Pointer to the configuration structure. + */ +void ADC16_GetDefaultConfig(adc16_config_t *config); + +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION +/*! + * @brief Automates the hardware calibration. + * + * This auto calibration helps to adjust the plus/minus side gain automatically. + * Execute the calibration before using the converter. Note that the hardware trigger should be used + * during the calibration. + * + * @param base ADC16 peripheral base address. + * + * @return Execution status. + * @retval kStatus_Success Calibration is done successfully. + * @retval kStatus_Fail Calibration has failed. + */ +status_t ADC16_DoAutoCalibration(ADC_Type *base); +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ + +#if defined(FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION) && FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION +/*! + * @brief Sets the offset value for the conversion result. + * + * This offset value takes effect on the conversion result. If the offset value is not zero, the reading result + * is subtracted by it. Note, the hardware calibration fills the offset value automatically. + * + * @param base ADC16 peripheral base address. + * @param value Setting offset value. + */ +static inline void ADC16_SetOffsetValue(ADC_Type *base, int16_t value) +{ + base->OFS = (uint32_t)(value); +} +#endif /* FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION */ + +/* @} */ + +/*! + * @name Advanced Features + * @{ + */ + +#if defined(FSL_FEATURE_ADC16_HAS_DMA) && FSL_FEATURE_ADC16_HAS_DMA +/*! + * @brief Enables generating the DMA trigger when the conversion is complete. + * + * @param base ADC16 peripheral base address. + * @param enable Switcher of the DMA feature. "true" means enabled, "false" means not enabled. + */ +static inline void ADC16_EnableDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->SC2 |= ADC_SC2_DMAEN_MASK; + } + else + { + base->SC2 &= ~ADC_SC2_DMAEN_MASK; + } +} +#endif /* FSL_FEATURE_ADC16_HAS_DMA */ + +/*! + * @brief Enables the hardware trigger mode. + * + * @param base ADC16 peripheral base address. + * @param enable Switcher of the hardware trigger feature. "true" means enabled, "false" means not enabled. + */ +static inline void ADC16_EnableHardwareTrigger(ADC_Type *base, bool enable) +{ + if (enable) + { + base->SC2 |= ADC_SC2_ADTRG_MASK; + } + else + { + base->SC2 &= ~ADC_SC2_ADTRG_MASK; + } +} + +#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT +/*! + * @brief Sets the channel mux mode. + * + * Some sample pins share the same channel index. The channel mux mode decides which pin is used for an + * indicated channel. + * + * @param base ADC16 peripheral base address. + * @param mode Setting channel mux mode. See "adc16_channel_mux_mode_t". + */ +void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode); +#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ + +/*! + * @brief Configures the hardware compare mode. + * + * The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the result + * in the compare range is available. To compare the range, see "adc16_hardware_compare_mode_t" or the appopriate reference + * manual for more information. + * + * @param base ADC16 peripheral base address. + * @param config Pointer to the "adc16_hardware_compare_config_t" structure. Passing "NULL" disables the feature. + */ +void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config); + +#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE +/*! + * @brief Sets the hardware average mode. + * + * The hardware average mode provides a way to process the conversion result automatically by using hardware. The multiple + * conversion results are accumulated and averaged internally making them easier to read. + * + * @param base ADC16 peripheral base address. + * @param mode Setting the hardware average mode. See "adc16_hardware_average_mode_t". + */ +void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode); +#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ + +#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA +/*! + * @brief Configures the PGA for the converter's front end. + * + * @param base ADC16 peripheral base address. + * @param config Pointer to the "adc16_pga_config_t" structure. Passing "NULL" disables the feature. + */ +void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config); +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +/*! + * @brief Gets the status flags of the converter. + * + * @param base ADC16 peripheral base address. + * + * @return Flags' mask if indicated flags are asserted. See "_adc16_status_flags". + */ +uint32_t ADC16_GetStatusFlags(ADC_Type *base); + +/*! + * @brief Clears the status flags of the converter. + * + * @param base ADC16 peripheral base address. + * @param mask Mask value for the cleared flags. See "_adc16_status_flags". + */ +void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Conversion Channel + * @{ + */ + +/*! + * @brief Configures the conversion channel. + * + * This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API + * configures the channel while the external trigger source helps to trigger the conversion. + * + * Note that the "Channel Group" has a detailed description. + * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one + * group of status and control registers, one for each conversion. The channel group parameter indicates which group of + * registers are used, for example, channel group 0 is for Group A registers and channel group 1 is for Group B registers. The + * channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of + * the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and hardware + * trigger modes. Channel group 1 and greater indicates multiple channel group registers for + * use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual for the + * number of SC1n registers (channel groups) specific to this device. Channel group 1 or greater are not used + * for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion. + * Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and + * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a + * conversion aborts the current conversion. + * + * @param base ADC16 peripheral base address. + * @param channelGroup Channel group index. + * @param config Pointer to the "adc16_channel_config_t" structure for the conversion channel. + */ +void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config); + +/*! + * @brief Gets the conversion value. + * + * @param base ADC16 peripheral base address. + * @param channelGroup Channel group index. + * + * @return Conversion value. + */ +static inline uint32_t ADC16_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup) +{ + assert(channelGroup < ADC_R_COUNT); + + return base->R[channelGroup]; +} + +/*! + * @brief Gets the status flags of channel. + * + * @param base ADC16 peripheral base address. + * @param channelGroup Channel group index. + * + * @return Flags' mask if indicated flags are asserted. See "_adc16_channel_status_flags". + */ +uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_ADC16_H_ */ diff --git a/source/hic_hal/freescale/kl27z/fsl_flexio.c b/source/hic_hal/freescale/kl27z/fsl_flexio.c new file mode 100644 index 000000000..9cb5046e0 --- /dev/null +++ b/source/hic_hal/freescale/kl27z/fsl_flexio.c @@ -0,0 +1,427 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio" +#endif + +/*< @brief user configurable flexio handle count. */ +#define FLEXIO_HANDLE_COUNT 2 + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to flexio bases for each instance. */ +FLEXIO_Type *const s_flexioBases[] = FLEXIO_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to flexio clocks for each instance. */ +const clock_ip_name_t s_flexioClocks[] = FLEXIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*< @brief pointer to array of FLEXIO handle. */ +static void *s_flexioHandle[FLEXIO_HANDLE_COUNT]; + +/*< @brief pointer to array of FLEXIO IP types. */ +static void *s_flexioType[FLEXIO_HANDLE_COUNT]; + +/*< @brief pointer to array of FLEXIO Isr. */ +static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT]; + +/******************************************************************************* + * Codes + ******************************************************************************/ + +/*! + * brief Get instance number for FLEXIO module. + * + * param base FLEXIO peripheral base address. + */ +uint32_t FLEXIO_GetInstance(FLEXIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_flexioBases); instance++) + { + if (s_flexioBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_flexioBases)); + + return instance; +} + +/*! + * brief Configures the FlexIO with a FlexIO configuration. The configuration structure + * can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig(). + * + * Example + code + flexio_config_t config = { + .enableFlexio = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false + }; + FLEXIO_Configure(base, &config); + endcode + * + * param base FlexIO peripheral base address + * param userConfig pointer to flexio_config_t structure +*/ +void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig) +{ + uint32_t ctrlReg = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(s_flexioClocks[FLEXIO_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + FLEXIO_Reset(base); + + ctrlReg = base->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DBGE(userConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(userConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(userConfig->enableFlexio)); + if (!userConfig->enableInDoze) + { + ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->CTRL = ctrlReg; +} + +/*! + * brief Gates the FlexIO clock. Call this API to stop the FlexIO clock. + * + * note After calling this API, call the FLEXO_Init to use the FlexIO module. + * + * param base FlexIO peripheral base address + */ +void FLEXIO_Deinit(FLEXIO_Type *base) +{ + FLEXIO_Enable(base, false); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_flexioClocks[FLEXIO_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Gets the default configuration to configure the FlexIO module. The configuration + * can used directly to call the FLEXIO_Configure(). + * + * Example: + code + flexio_config_t config; + FLEXIO_GetDefaultConfig(&config); + endcode + * + * param userConfig pointer to flexio_config_t structure +*/ +void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig) +{ + assert(userConfig); + + /* Initializes the configure structure to zero. */ + memset(userConfig, 0, sizeof(*userConfig)); + + userConfig->enableFlexio = true; + userConfig->enableInDoze = false; + userConfig->enableInDebug = true; + userConfig->enableFastAccess = false; +} + +/*! + * brief Resets the FlexIO module. + * + * param base FlexIO peripheral base address + */ +void FLEXIO_Reset(FLEXIO_Type *base) +{ + /*do software reset, software reset operation affect all other FLEXIO registers except CTRL*/ + base->CTRL |= FLEXIO_CTRL_SWRST_MASK; + base->CTRL = 0; +} + +/*! + * brief Gets the shifter buffer address for the DMA transfer usage. + * + * param base FlexIO peripheral base address + * param type Shifter type of flexio_shifter_buffer_type_t + * param index Shifter index + * return Corresponding shifter buffer index + */ +uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index) +{ + assert(index < FLEXIO_SHIFTBUF_COUNT); + + uint32_t address = 0; + + switch (type) + { + case kFLEXIO_ShifterBuffer: + address = (uint32_t) & (base->SHIFTBUF[index]); + break; + + case kFLEXIO_ShifterBufferBitSwapped: + address = (uint32_t) & (base->SHIFTBUFBIS[index]); + break; + + case kFLEXIO_ShifterBufferByteSwapped: + address = (uint32_t) & (base->SHIFTBUFBYS[index]); + break; + + case kFLEXIO_ShifterBufferBitByteSwapped: + address = (uint32_t) & (base->SHIFTBUFBBS[index]); + break; + +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP + case kFLEXIO_ShifterBufferNibbleByteSwapped: + address = (uint32_t) & (base->SHIFTBUFNBS[index]); + break; + +#endif +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP + case kFLEXIO_ShifterBufferHalfWordSwapped: + address = (uint32_t) & (base->SHIFTBUFHWS[index]); + break; + +#endif +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP + case kFLEXIO_ShifterBufferNibbleSwapped: + address = (uint32_t) & (base->SHIFTBUFNIS[index]); + break; + +#endif + default: + break; + } + return address; +} + +/*! + * brief Configures the shifter with the shifter configuration. The configuration structure + * covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper + * mode, select which timer controls the shifter to shift, whether to generate start bit/stop + * bit, and the polarity of start bit and stop bit. + * + * Example + code + flexio_shifter_config_t config = { + .timerSelect = 0, + .timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinPolarity = kFLEXIO_PinActiveLow, + .shifterMode = kFLEXIO_ShifterModeTransmit, + .inputSource = kFLEXIO_ShifterInputFromPin, + .shifterStop = kFLEXIO_ShifterStopBitHigh, + .shifterStart = kFLEXIO_ShifterStartBitLow + }; + FLEXIO_SetShifterConfig(base, &config); + endcode + * + * param base FlexIO peripheral base address + * param index Shifter index + * param shifterConfig Pointer to flexio_shifter_config_t structure +*/ +void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig) +{ + base->SHIFTCFG[index] = FLEXIO_SHIFTCFG_INSRC(shifterConfig->inputSource) +#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH + | FLEXIO_SHIFTCFG_PWIDTH(shifterConfig->parallelWidth) +#endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */ + | FLEXIO_SHIFTCFG_SSTOP(shifterConfig->shifterStop) | + FLEXIO_SHIFTCFG_SSTART(shifterConfig->shifterStart); + + base->SHIFTCTL[index] = + FLEXIO_SHIFTCTL_TIMSEL(shifterConfig->timerSelect) | FLEXIO_SHIFTCTL_TIMPOL(shifterConfig->timerPolarity) | + FLEXIO_SHIFTCTL_PINCFG(shifterConfig->pinConfig) | FLEXIO_SHIFTCTL_PINSEL(shifterConfig->pinSelect) | + FLEXIO_SHIFTCTL_PINPOL(shifterConfig->pinPolarity) | FLEXIO_SHIFTCTL_SMOD(shifterConfig->shifterMode); +} + +/*! + * brief Configures the timer with the timer configuration. The configuration structure + * covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper + * mode, select trigger source for timer and the timer pin output and the timing for timer. + * + * Example + code + flexio_timer_config_t config = { + .triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0), + .triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow, + .triggerSource = kFLEXIO_TimerTriggerSourceInternal, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinSelect = 0, + .pinPolarity = kFLEXIO_PinActiveHigh, + .timerMode = kFLEXIO_TimerModeDual8BitBaudBit, + .timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset, + .timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput, + .timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput, + .timerDisable = kFLEXIO_TimerDisableOnTimerCompare, + .timerEnable = kFLEXIO_TimerEnableOnTriggerHigh, + .timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable, + .timerStart = kFLEXIO_TimerStartBitEnabled + }; + FLEXIO_SetTimerConfig(base, &config); + endcode + * + * param base FlexIO peripheral base address + * param index Timer index + * param timerConfig Pointer to the flexio_timer_config_t structure +*/ +void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig) +{ + base->TIMCFG[index] = + FLEXIO_TIMCFG_TIMOUT(timerConfig->timerOutput) | FLEXIO_TIMCFG_TIMDEC(timerConfig->timerDecrement) | + FLEXIO_TIMCFG_TIMRST(timerConfig->timerReset) | FLEXIO_TIMCFG_TIMDIS(timerConfig->timerDisable) | + FLEXIO_TIMCFG_TIMENA(timerConfig->timerEnable) | FLEXIO_TIMCFG_TSTOP(timerConfig->timerStop) | + FLEXIO_TIMCFG_TSTART(timerConfig->timerStart); + + base->TIMCMP[index] = FLEXIO_TIMCMP_CMP(timerConfig->timerCompare); + + base->TIMCTL[index] = FLEXIO_TIMCTL_TRGSEL(timerConfig->triggerSelect) | + FLEXIO_TIMCTL_TRGPOL(timerConfig->triggerPolarity) | + FLEXIO_TIMCTL_TRGSRC(timerConfig->triggerSource) | + FLEXIO_TIMCTL_PINCFG(timerConfig->pinConfig) | FLEXIO_TIMCTL_PINSEL(timerConfig->pinSelect) | + FLEXIO_TIMCTL_PINPOL(timerConfig->pinPolarity) | FLEXIO_TIMCTL_TIMOD(timerConfig->timerMode); +} + +/*! + * brief Registers the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * param base Pointer to the FlexIO simulated peripheral type. + * param handle Pointer to the handler for FlexIO simulated peripheral. + * param isr FlexIO simulated peripheral interrupt handler. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr) +{ + assert(base); + assert(handle); + assert(isr); + + uint8_t index = 0; + + /* Find the an empty handle pointer to store the handle. */ + for (index = 0; index < FLEXIO_HANDLE_COUNT; index++) + { + if (s_flexioHandle[index] == NULL) + { + /* Register FLEXIO simulated driver base, handle and isr. */ + s_flexioType[index] = base; + s_flexioHandle[index] = handle; + s_flexioIsr[index] = isr; + break; + } + } + + if (index == FLEXIO_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + else + { + return kStatus_Success; + } +} + +/*! + * brief Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * param base Pointer to the FlexIO simulated peripheral type. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_UnregisterHandleIRQ(void *base) +{ + assert(base); + + uint8_t index = 0; + + /* Find the index from base address mappings. */ + for (index = 0; index < FLEXIO_HANDLE_COUNT; index++) + { + if (s_flexioType[index] == base) + { + /* Unregister FLEXIO simulated driver handle and isr. */ + s_flexioType[index] = NULL; + s_flexioHandle[index] = NULL; + s_flexioIsr[index] = NULL; + break; + } + } + + if (index == FLEXIO_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + else + { + return kStatus_Success; + } +} + +void FLEXIO_CommonIRQHandler(void) +{ + uint8_t index; + + for (index = 0; index < FLEXIO_HANDLE_COUNT; index++) + { + if (s_flexioHandle[index]) + { + s_flexioIsr[index](s_flexioType[index], s_flexioHandle[index]); + } + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void FLEXIO_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void FLEXIO0_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void FLEXIO1_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void UART2_FLEXIO_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void FLEXIO2_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void FLEXIO3_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} diff --git a/source/hic_hal/freescale/kl27z/fsl_flexio.h b/source/hic_hal/freescale/kl27z/fsl_flexio.h new file mode 100644 index 000000000..6a984040d --- /dev/null +++ b/source/hic_hal/freescale/kl27z/fsl_flexio.h @@ -0,0 +1,701 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_FLEXIO_H_ +#define _FSL_FLEXIO_H_ + +#include "fsl_common.h" +#include "fsl_clock.h" + +/*! + * @addtogroup flexio_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO driver version 2.0.2. */ +#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! @brief Calculate FlexIO timer trigger.*/ +#define FLEXIO_TIMER_TRIGGER_SEL_PININPUT(x) ((uint32_t)(x) << 1U) +#define FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(x) (((uint32_t)(x) << 2U) | 0x1U) +#define FLEXIO_TIMER_TRIGGER_SEL_TIMn(x) (((uint32_t)(x) << 2U) | 0x3U) + +/*! @brief Define time of timer trigger polarity.*/ +typedef enum _flexio_timer_trigger_polarity +{ + kFLEXIO_TimerTriggerPolarityActiveHigh = 0x0U, /*!< Active high. */ + kFLEXIO_TimerTriggerPolarityActiveLow = 0x1U, /*!< Active low. */ +} flexio_timer_trigger_polarity_t; + +/*! @brief Define type of timer trigger source.*/ +typedef enum _flexio_timer_trigger_source +{ + kFLEXIO_TimerTriggerSourceExternal = 0x0U, /*!< External trigger selected. */ + kFLEXIO_TimerTriggerSourceInternal = 0x1U, /*!< Internal trigger selected. */ +} flexio_timer_trigger_source_t; + +/*! @brief Define type of timer/shifter pin configuration.*/ +typedef enum _flexio_pin_config +{ + kFLEXIO_PinConfigOutputDisabled = 0x0U, /*!< Pin output disabled. */ + kFLEXIO_PinConfigOpenDrainOrBidirection = 0x1U, /*!< Pin open drain or bidirectional output enable. */ + kFLEXIO_PinConfigBidirectionOutputData = 0x2U, /*!< Pin bidirectional output data. */ + kFLEXIO_PinConfigOutput = 0x3U, /*!< Pin output. */ +} flexio_pin_config_t; + +/*! @brief Definition of pin polarity.*/ +typedef enum _flexio_pin_polarity +{ + kFLEXIO_PinActiveHigh = 0x0U, /*!< Active high. */ + kFLEXIO_PinActiveLow = 0x1U, /*!< Active low. */ +} flexio_pin_polarity_t; + +/*! @brief Define type of timer work mode.*/ +typedef enum _flexio_timer_mode +{ + kFLEXIO_TimerModeDisabled = 0x0U, /*!< Timer Disabled. */ + kFLEXIO_TimerModeDual8BitBaudBit = 0x1U, /*!< Dual 8-bit counters baud/bit mode. */ + kFLEXIO_TimerModeDual8BitPWM = 0x2U, /*!< Dual 8-bit counters PWM mode. */ + kFLEXIO_TimerModeSingle16Bit = 0x3U, /*!< Single 16-bit counter mode. */ +} flexio_timer_mode_t; + +/*! @brief Define type of timer initial output or timer reset condition.*/ +typedef enum _flexio_timer_output +{ + kFLEXIO_TimerOutputOneNotAffectedByReset = 0x0U, /*!< Logic one when enabled and is not affected by timer + reset. */ + kFLEXIO_TimerOutputZeroNotAffectedByReset = 0x1U, /*!< Logic zero when enabled and is not affected by timer + reset. */ + kFLEXIO_TimerOutputOneAffectedByReset = 0x2U, /*!< Logic one when enabled and on timer reset. */ + kFLEXIO_TimerOutputZeroAffectedByReset = 0x3U, /*!< Logic zero when enabled and on timer reset. */ +} flexio_timer_output_t; + +/*! @brief Define type of timer decrement.*/ +typedef enum _flexio_timer_decrement_source +{ + kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput = 0x0U, /*!< Decrement counter on FlexIO clock, Shift clock + equals Timer output. */ + kFLEXIO_TimerDecSrcOnTriggerInputShiftTimerOutput = 0x1U, /*!< Decrement counter on Trigger input (both edges), + Shift clock equals Timer output. */ + kFLEXIO_TimerDecSrcOnPinInputShiftPinInput = 0x2U, /*!< Decrement counter on Pin input (both edges), + Shift clock equals Pin input. */ + kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput = 0x3U, /*!< Decrement counter on Trigger input (both edges), + Shift clock equals Trigger input. */ +} flexio_timer_decrement_source_t; + +/*! @brief Define type of timer reset condition.*/ +typedef enum _flexio_timer_reset_condition +{ + kFLEXIO_TimerResetNever = 0x0U, /*!< Timer never reset. */ + kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput = 0x2U, /*!< Timer reset on Timer Pin equal to Timer Output. */ + kFLEXIO_TimerResetOnTimerTriggerEqualToTimerOutput = 0x3U, /*!< Timer reset on Timer Trigger equal to + Timer Output. */ + kFLEXIO_TimerResetOnTimerPinRisingEdge = 0x4U, /*!< Timer reset on Timer Pin rising edge. */ + kFLEXIO_TimerResetOnTimerTriggerRisingEdge = 0x6U, /*!< Timer reset on Trigger rising edge. */ + kFLEXIO_TimerResetOnTimerTriggerBothEdge = 0x7U, /*!< Timer reset on Trigger rising or falling edge. */ +} flexio_timer_reset_condition_t; + +/*! @brief Define type of timer disable condition.*/ +typedef enum _flexio_timer_disable_condition +{ + kFLEXIO_TimerDisableNever = 0x0U, /*!< Timer never disabled. */ + kFLEXIO_TimerDisableOnPreTimerDisable = 0x1U, /*!< Timer disabled on Timer N-1 disable. */ + kFLEXIO_TimerDisableOnTimerCompare = 0x2U, /*!< Timer disabled on Timer compare. */ + kFLEXIO_TimerDisableOnTimerCompareTriggerLow = 0x3U, /*!< Timer disabled on Timer compare and Trigger Low. */ + kFLEXIO_TimerDisableOnPinBothEdge = 0x4U, /*!< Timer disabled on Pin rising or falling edge. */ + kFLEXIO_TimerDisableOnPinBothEdgeTriggerHigh = 0x5U, /*!< Timer disabled on Pin rising or falling edge provided + Trigger is high. */ + kFLEXIO_TimerDisableOnTriggerFallingEdge = 0x6U, /*!< Timer disabled on Trigger falling edge. */ +} flexio_timer_disable_condition_t; + +/*! @brief Define type of timer enable condition.*/ +typedef enum _flexio_timer_enable_condition +{ + kFLEXIO_TimerEnabledAlways = 0x0U, /*!< Timer always enabled. */ + kFLEXIO_TimerEnableOnPrevTimerEnable = 0x1U, /*!< Timer enabled on Timer N-1 enable. */ + kFLEXIO_TimerEnableOnTriggerHigh = 0x2U, /*!< Timer enabled on Trigger high. */ + kFLEXIO_TimerEnableOnTriggerHighPinHigh = 0x3U, /*!< Timer enabled on Trigger high and Pin high. */ + kFLEXIO_TimerEnableOnPinRisingEdge = 0x4U, /*!< Timer enabled on Pin rising edge. */ + kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh = 0x5U, /*!< Timer enabled on Pin rising edge and Trigger high. */ + kFLEXIO_TimerEnableOnTriggerRisingEdge = 0x6U, /*!< Timer enabled on Trigger rising edge. */ + kFLEXIO_TimerEnableOnTriggerBothEdge = 0x7U, /*!< Timer enabled on Trigger rising or falling edge. */ +} flexio_timer_enable_condition_t; + +/*! @brief Define type of timer stop bit generate condition.*/ +typedef enum _flexio_timer_stop_bit_condition +{ + kFLEXIO_TimerStopBitDisabled = 0x0U, /*!< Stop bit disabled. */ + kFLEXIO_TimerStopBitEnableOnTimerCompare = 0x1U, /*!< Stop bit is enabled on timer compare. */ + kFLEXIO_TimerStopBitEnableOnTimerDisable = 0x2U, /*!< Stop bit is enabled on timer disable. */ + kFLEXIO_TimerStopBitEnableOnTimerCompareDisable = 0x3U, /*!< Stop bit is enabled on timer compare and timer + disable. */ +} flexio_timer_stop_bit_condition_t; + +/*! @brief Define type of timer start bit generate condition.*/ +typedef enum _flexio_timer_start_bit_condition +{ + kFLEXIO_TimerStartBitDisabled = 0x0U, /*!< Start bit disabled. */ + kFLEXIO_TimerStartBitEnabled = 0x1U, /*!< Start bit enabled. */ +} flexio_timer_start_bit_condition_t; + +/*! @brief Define type of timer polarity for shifter control. */ +typedef enum _flexio_shifter_timer_polarity +{ + kFLEXIO_ShifterTimerPolarityOnPositive = 0x0U, /*!< Shift on positive edge of shift clock. */ + kFLEXIO_ShifterTimerPolarityOnNegitive = 0x1U, /*!< Shift on negative edge of shift clock. */ +} flexio_shifter_timer_polarity_t; + +/*! @brief Define type of shifter working mode.*/ +typedef enum _flexio_shifter_mode +{ + kFLEXIO_ShifterDisabled = 0x0U, /*!< Shifter is disabled. */ + kFLEXIO_ShifterModeReceive = 0x1U, /*!< Receive mode. */ + kFLEXIO_ShifterModeTransmit = 0x2U, /*!< Transmit mode. */ + kFLEXIO_ShifterModeMatchStore = 0x4U, /*!< Match store mode. */ + kFLEXIO_ShifterModeMatchContinuous = 0x5U, /*!< Match continuous mode. */ +#if FSL_FEATURE_FLEXIO_HAS_STATE_MODE + kFLEXIO_ShifterModeState = 0x6U, /*!< SHIFTBUF contents are used for storing + programmable state attributes. */ +#endif /* FSL_FEATURE_FLEXIO_HAS_STATE_MODE */ +#if FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE + kFLEXIO_ShifterModeLogic = 0x7U, /*!< SHIFTBUF contents are used for implementing + programmable logic look up table. */ +#endif /* FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE */ +} flexio_shifter_mode_t; + +/*! @brief Define type of shifter input source.*/ +typedef enum _flexio_shifter_input_source +{ + kFLEXIO_ShifterInputFromPin = 0x0U, /*!< Shifter input from pin. */ + kFLEXIO_ShifterInputFromNextShifterOutput = 0x1U, /*!< Shifter input from Shifter N+1. */ +} flexio_shifter_input_source_t; + +/*! @brief Define of STOP bit configuration.*/ +typedef enum _flexio_shifter_stop_bit +{ + kFLEXIO_ShifterStopBitDisable = 0x0U, /*!< Disable shifter stop bit. */ + kFLEXIO_ShifterStopBitLow = 0x2U, /*!< Set shifter stop bit to logic low level. */ + kFLEXIO_ShifterStopBitHigh = 0x3U, /*!< Set shifter stop bit to logic high level. */ +} flexio_shifter_stop_bit_t; + +/*! @brief Define type of START bit configuration.*/ +typedef enum _flexio_shifter_start_bit +{ + kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable = 0x0U, /*!< Disable shifter start bit, transmitter loads + data on enable. */ + kFLEXIO_ShifterStartBitDisabledLoadDataOnShift = 0x1U, /*!< Disable shifter start bit, transmitter loads + data on first shift. */ + kFLEXIO_ShifterStartBitLow = 0x2U, /*!< Set shifter start bit to logic low level. */ + kFLEXIO_ShifterStartBitHigh = 0x3U, /*!< Set shifter start bit to logic high level. */ +} flexio_shifter_start_bit_t; + +/*! @brief Define FlexIO shifter buffer type*/ +typedef enum _flexio_shifter_buffer_type +{ + kFLEXIO_ShifterBuffer = 0x0U, /*!< Shifter Buffer N Register. */ + kFLEXIO_ShifterBufferBitSwapped = 0x1U, /*!< Shifter Buffer N Bit Byte Swapped Register. */ + kFLEXIO_ShifterBufferByteSwapped = 0x2U, /*!< Shifter Buffer N Byte Swapped Register. */ + kFLEXIO_ShifterBufferBitByteSwapped = 0x3U, /*!< Shifter Buffer N Bit Swapped Register. */ +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP + kFLEXIO_ShifterBufferNibbleByteSwapped = 0x4U, /*!< Shifter Buffer N Nibble Byte Swapped Register. */ +#endif /*FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP*/ +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP + kFLEXIO_ShifterBufferHalfWordSwapped = 0x5U, /*!< Shifter Buffer N Half Word Swapped Register. */ +#endif +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP + kFLEXIO_ShifterBufferNibbleSwapped = 0x6U, /*!< Shifter Buffer N Nibble Swapped Register. */ +#endif +} flexio_shifter_buffer_type_t; + +/*! @brief Define FlexIO user configuration structure. */ +typedef struct _flexio_config_ +{ + bool enableFlexio; /*!< Enable/disable FlexIO module */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, fast access requires + the FlexIO clock to be at least twice the frequency of the bus clock. */ +} flexio_config_t; + +/*! @brief Define FlexIO timer configuration structure. */ +typedef struct _flexio_timer_config +{ + /* Trigger. */ + uint32_t triggerSelect; /*!< The internal trigger selection number using MACROs. */ + flexio_timer_trigger_polarity_t triggerPolarity; /*!< Trigger Polarity. */ + flexio_timer_trigger_source_t triggerSource; /*!< Trigger Source, internal (see 'trgsel') or external. */ + /* Pin. */ + flexio_pin_config_t pinConfig; /*!< Timer Pin Configuration. */ + uint32_t pinSelect; /*!< Timer Pin number Select. */ + flexio_pin_polarity_t pinPolarity; /*!< Timer Pin Polarity. */ + /* Timer. */ + flexio_timer_mode_t timerMode; /*!< Timer work Mode. */ + flexio_timer_output_t timerOutput; /*!< Configures the initial state of the Timer Output and + whether it is affected by the Timer reset. */ + flexio_timer_decrement_source_t timerDecrement; /*!< Configures the source of the Timer decrement and the + source of the Shift clock. */ + flexio_timer_reset_condition_t timerReset; /*!< Configures the condition that causes the timer counter + (and optionally the timer output) to be reset. */ + flexio_timer_disable_condition_t timerDisable; /*!< Configures the condition that causes the Timer to be + disabled and stop decrementing. */ + flexio_timer_enable_condition_t timerEnable; /*!< Configures the condition that causes the Timer to be + enabled and start decrementing. */ + flexio_timer_stop_bit_condition_t timerStop; /*!< Timer STOP Bit generation. */ + flexio_timer_start_bit_condition_t timerStart; /*!< Timer STRAT Bit generation. */ + uint32_t timerCompare; /*!< Value for Timer Compare N Register. */ +} flexio_timer_config_t; + +/*! @brief Define FlexIO shifter configuration structure. */ +typedef struct _flexio_shifter_config +{ + /* Timer. */ + uint32_t timerSelect; /*!< Selects which Timer is used for controlling the + logic/shift register and generating the Shift clock. */ + flexio_shifter_timer_polarity_t timerPolarity; /*!< Timer Polarity. */ + /* Pin. */ + flexio_pin_config_t pinConfig; /*!< Shifter Pin Configuration. */ + uint32_t pinSelect; /*!< Shifter Pin number Select. */ + flexio_pin_polarity_t pinPolarity; /*!< Shifter Pin Polarity. */ + /* Shifter. */ + flexio_shifter_mode_t shifterMode; /*!< Configures the mode of the Shifter. */ +#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH + uint32_t parallelWidth; /*!< Configures the parallel width when using parallel mode.*/ +#endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */ + flexio_shifter_input_source_t inputSource; /*!< Selects the input source for the shifter. */ + flexio_shifter_stop_bit_t shifterStop; /*!< Shifter STOP bit. */ + flexio_shifter_start_bit_t shifterStart; /*!< Shifter START bit. */ +} flexio_shifter_config_t; + +/*! @brief typedef for FlexIO simulated driver interrupt handler.*/ +typedef void (*flexio_isr_t)(void *base, void *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to flexio bases for each instance. */ +extern FLEXIO_Type *const s_flexioBases[]; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to flexio clocks for each instance. */ +extern const clock_ip_name_t s_flexioClocks[]; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name FlexIO Initialization and De-initialization + * @{ + */ + +/*! + * @brief Gets the default configuration to configure the FlexIO module. The configuration + * can used directly to call the FLEXIO_Configure(). + * + * Example: + @code + flexio_config_t config; + FLEXIO_GetDefaultConfig(&config); + @endcode + * + * @param userConfig pointer to flexio_config_t structure +*/ +void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig); + +/*! + * @brief Configures the FlexIO with a FlexIO configuration. The configuration structure + * can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig(). + * + * Example + @code + flexio_config_t config = { + .enableFlexio = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false + }; + FLEXIO_Configure(base, &config); + @endcode + * + * @param base FlexIO peripheral base address + * @param userConfig pointer to flexio_config_t structure +*/ +void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig); + +/*! + * @brief Gates the FlexIO clock. Call this API to stop the FlexIO clock. + * + * @note After calling this API, call the FLEXO_Init to use the FlexIO module. + * + * @param base FlexIO peripheral base address + */ +void FLEXIO_Deinit(FLEXIO_Type *base); + +/*! + * @brief Get instance number for FLEXIO module. + * + * @param base FLEXIO peripheral base address. + */ +uint32_t FLEXIO_GetInstance(FLEXIO_Type *base); + +/* @} */ + +/*! + * @name FlexIO Basic Operation + * @{ + */ + +/*! + * @brief Resets the FlexIO module. + * + * @param base FlexIO peripheral base address + */ +void FLEXIO_Reset(FLEXIO_Type *base); + +/*! + * @brief Enables the FlexIO module operation. + * + * @param base FlexIO peripheral base address + * @param enable true to enable, false to disable. + */ +static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } + else + { + base->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; + } +} + +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS +/*! + * @brief Reads the input data on each of the FlexIO pins. + * + * @param base FlexIO peripheral base address + * @return FlexIO pin input data + */ +static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base) +{ + return base->PIN; +} +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/ + +#if defined(FSL_FEATURE_FLEXIO_HAS_STATE_MODE) && FSL_FEATURE_FLEXIO_HAS_STATE_MODE +/*! + * @brief Gets the current state pointer for state mode use. + * + * @param base FlexIO peripheral base address + * @return current State pointer + */ +static inline uint8_t FLEXIO_GetShifterState(FLEXIO_Type *base) +{ + return ((base->SHIFTSTATE) & FLEXIO_SHIFTSTATE_STATE_MASK); +} +#endif /*FSL_FEATURE_FLEXIO_HAS_STATE_MODE*/ + +/*! + * @brief Configures the shifter with the shifter configuration. The configuration structure + * covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper + * mode, select which timer controls the shifter to shift, whether to generate start bit/stop + * bit, and the polarity of start bit and stop bit. + * + * Example + @code + flexio_shifter_config_t config = { + .timerSelect = 0, + .timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinPolarity = kFLEXIO_PinActiveLow, + .shifterMode = kFLEXIO_ShifterModeTransmit, + .inputSource = kFLEXIO_ShifterInputFromPin, + .shifterStop = kFLEXIO_ShifterStopBitHigh, + .shifterStart = kFLEXIO_ShifterStartBitLow + }; + FLEXIO_SetShifterConfig(base, &config); + @endcode + * + * @param base FlexIO peripheral base address + * @param index Shifter index + * @param shifterConfig Pointer to flexio_shifter_config_t structure +*/ +void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig); +/*! + * @brief Configures the timer with the timer configuration. The configuration structure + * covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper + * mode, select trigger source for timer and the timer pin output and the timing for timer. + * + * Example + @code + flexio_timer_config_t config = { + .triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0), + .triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow, + .triggerSource = kFLEXIO_TimerTriggerSourceInternal, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinSelect = 0, + .pinPolarity = kFLEXIO_PinActiveHigh, + .timerMode = kFLEXIO_TimerModeDual8BitBaudBit, + .timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset, + .timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput, + .timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput, + .timerDisable = kFLEXIO_TimerDisableOnTimerCompare, + .timerEnable = kFLEXIO_TimerEnableOnTriggerHigh, + .timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable, + .timerStart = kFLEXIO_TimerStartBitEnabled + }; + FLEXIO_SetTimerConfig(base, &config); + @endcode + * + * @param base FlexIO peripheral base address + * @param index Timer index + * @param timerConfig Pointer to the flexio_timer_config_t structure +*/ +void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig); + +/* @} */ + +/*! + * @name FlexIO Interrupt Operation + * @{ + */ + +/*! + * @brief Enables the shifter status interrupt. The interrupt generates when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask The shifter status mask which can be calculated by (1 << shifter index) + * @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTSIEN |= mask; +} + +/*! + * @brief Disables the shifter status interrupt. The interrupt won't generate when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask The shifter status mask which can be calculated by (1 << shifter index) + * @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTSIEN &= ~mask; +} + +/*! + * @brief Enables the shifter error interrupt. The interrupt generates when the corresponding SEF is set. + * + * @param base FlexIO peripheral base address + * @param mask The shifter error mask which can be calculated by (1 << shifter index) + * @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTEIEN |= mask; +} + +/*! + * @brief Disables the shifter error interrupt. The interrupt won't generate when the corresponding SEF is set. + * + * @param base FlexIO peripheral base address + * @param mask The shifter error mask which can be calculated by (1 << shifter index) + * @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTEIEN &= ~mask; +} + +/*! + * @brief Enables the timer status interrupt. The interrupt generates when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask The timer status mask which can be calculated by (1 << timer index) + * @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate + * the mask by using ((1 << timer index0) | (1 << timer index1)) + */ +static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->TIMIEN |= mask; +} + +/*! + * @brief Disables the timer status interrupt. The interrupt won't generate when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask The timer status mask which can be calculated by (1 << timer index) + * @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate + * the mask by using ((1 << timer index0) | (1 << timer index1)) + */ +static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->TIMIEN &= ~mask; +} + +/* @} */ + +/*! + * @name FlexIO Status Operation + * @{ + */ + +/*! + * @brief Gets the shifter status flags. + * + * @param base FlexIO peripheral base address + * @return Shifter status flags + */ +static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base) +{ + return ((base->SHIFTSTAT) & FLEXIO_SHIFTSTAT_SSF_MASK); +} + +/*! + * @brief Clears the shifter status flags. + * + * @param base FlexIO peripheral base address + * @param mask The shifter status mask which can be calculated by (1 << shifter index) + * @note For clearing multiple shifter status flags, for example, two shifter status flags, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTSTAT = mask; +} + +/*! + * @brief Gets the shifter error flags. + * + * @param base FlexIO peripheral base address + * @return Shifter error flags + */ +static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base) +{ + return ((base->SHIFTERR) & FLEXIO_SHIFTERR_SEF_MASK); +} + +/*! + * @brief Clears the shifter error flags. + * + * @param base FlexIO peripheral base address + * @param mask The shifter error mask which can be calculated by (1 << shifter index) + * @note For clearing multiple shifter error flags, for example, two shifter error flags, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTERR = mask; +} + +/*! + * @brief Gets the timer status flags. + * + * @param base FlexIO peripheral base address + * @return Timer status flags + */ +static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base) +{ + return ((base->TIMSTAT) & FLEXIO_TIMSTAT_TSF_MASK); +} + +/*! + * @brief Clears the timer status flags. + * + * @param base FlexIO peripheral base address + * @param mask The timer status mask which can be calculated by (1 << timer index) + * @note For clearing multiple timer status flags, for example, two timer status flags, can calculate + * the mask by using ((1 << timer index0) | (1 << timer index1)) + */ +static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask) +{ + base->TIMSTAT = mask; +} + +/* @} */ + +/*! + * @name FlexIO DMA Operation + * @{ + */ + +/*! + * @brief Enables/disables the shifter status DMA. The DMA request generates when the corresponding SSF is set. + * + * @note For multiple shifter status DMA enables, for example, calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + * + * @param base FlexIO peripheral base address + * @param mask The shifter status mask which can be calculated by (1 << shifter index) + * @param enable True to enable, false to disable. + */ +static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->SHIFTSDEN |= mask; + } + else + { + base->SHIFTSDEN &= ~mask; + } +} + +/*! + * @brief Gets the shifter buffer address for the DMA transfer usage. + * + * @param base FlexIO peripheral base address + * @param type Shifter type of flexio_shifter_buffer_type_t + * @param index Shifter index + * @return Corresponding shifter buffer index + */ +uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index); + +/*! + * @brief Registers the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * @param base Pointer to the FlexIO simulated peripheral type. + * @param handle Pointer to the handler for FlexIO simulated peripheral. + * @param isr FlexIO simulated peripheral interrupt handler. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr); + +/*! + * @brief Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * @param base Pointer to the FlexIO simulated peripheral type. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_UnregisterHandleIRQ(void *base); +/* @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /*_FSL_FLEXIO_H_*/ diff --git a/source/hic_hal/freescale/kl27z/fsl_gpio.c b/source/hic_hal/freescale/kl27z/fsl_gpio.c new file mode 100644 index 000000000..7f2b16bea --- /dev/null +++ b/source/hic_hal/freescale/kl27z/fsl_gpio.c @@ -0,0 +1,345 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_gpio.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.gpio" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +static PORT_Type *const s_portBases[] = PORT_BASE_PTRS; +static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; +#endif + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map FGPIO instance number to clock name. */ +static const clock_ip_name_t s_fgpioClockName[] = FGPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */ + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +/*! + * @brief Gets the GPIO instance according to the GPIO base + * + * @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.) + * @retval GPIO instance + */ +static uint32_t GPIO_GetInstance(GPIO_Type *base); +#endif +/******************************************************************************* + * Code + ******************************************************************************/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +static uint32_t GPIO_GetInstance(GPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++) + { + if (s_gpioBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_gpioBases)); + + return instance; +} +#endif +/*! + * brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, as either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration. + * code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * param pin GPIO port pin number + * param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) +{ + assert(NULL != config); + + uint32_t u32flag = 1; + + if (config->pinDirection == kGPIO_DigitalInput) + { + base->PDDR &= ~(u32flag << pin); + } + else + { + GPIO_PinWrite(base, pin, config->outputLogic); + base->PDDR |= (u32flag << pin); + } +} + +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +/*! + * brief Reads the GPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * retval The current GPIO port interrupt status flag, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base) +{ + uint8_t instance; + PORT_Type *portBase; + instance = (uint8_t)GPIO_GetInstance(base); + portBase = s_portBases[instance]; + return portBase->ISFR; +} +#endif +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +/*! + * brief Clears multiple GPIO pin interrupt status flags. + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * param mask GPIO pin number macro + */ +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + uint8_t instance; + PORT_Type *portBase; + instance = (uint8_t)GPIO_GetInstance(base); + portBase = s_portBases[instance]; + portBase->ISFR = mask; +} +#else +/*! + * brief Clears GPIO pin interrupt status flags. + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * param mask GPIO pin number macro + */ +void GPIO_GpioClearInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + base->ISFR[0] = mask; +} +#endif + +#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER +/*! + * brief The GPIO module supports a device-specific number of data ports, organized as 32-bit + * words/8-bit Bytes. Each 32-bit/8-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the GPIO programming model. If the GPIO module's GACR register + * organized as 32-bit words, the attribute controls for the 4 data bytes in the GACR follow a standard little + * endian data convention. + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * param mask GPIO pin number macro + */ +void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute) +{ +#if defined(FSL_FEATURE_GPIO_ATTRIBUTE_CHECKER_WORD_WIDTH) && FSL_FEATURE_GPIO_ATTRIBUTE_CHECKER_WORD_WIDTH + base->GACR = ((uint32_t)attribute << GPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB1_SHIFT) | + ((uint32_t)attribute << GPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB3_SHIFT); +#elif defined(FSL_FEATURE_GPIO_ATTRIBUTE_CHECKER_BYTE_WIDTH) && FSL_FEATURE_GPIO_ATTRIBUTE_CHECKER_BYTE_WIDTH + base->GACR = ((uint8_t)attribute << GPIO_GACR_ACB_SHIFT); +#endif +} +#endif + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS; +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +/*! + * @brief Gets the FGPIO instance according to the GPIO base + * + * @param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.) + * @retval FGPIO instance + */ +static uint32_t FGPIO_GetInstance(FGPIO_Type *base); +#endif +/******************************************************************************* + * Code + ******************************************************************************/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +static uint32_t FGPIO_GetInstance(FGPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_fgpioBases); instance++) + { + if (s_fgpioBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_fgpioBases)); + + return instance; +} +#endif +#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL +/*! + * brief Initializes the FGPIO peripheral. + * + * This function ungates the FGPIO clock. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + */ +void FGPIO_PortInit(FGPIO_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate FGPIO periphral clock */ + CLOCK_EnableClock(s_fgpioClockName[FGPIO_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} +#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */ + +/*! + * brief Initializes a FGPIO pin used by the board. + * + * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file. + * Then, call the FGPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration: + * code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * param pin FGPIO port pin number + * param config FGPIO pin configuration pointer + */ +void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) +{ + assert(NULL != config); + + uint32_t u32flag = 1; + + if (config->pinDirection == kGPIO_DigitalInput) + { + base->PDDR &= ~(u32flag << pin); + } + else + { + FGPIO_PinWrite(base, pin, config->outputLogic); + base->PDDR |= (u32flag << pin); + } +} +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +/*! + * brief Reads the FGPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level-sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base) +{ + uint8_t instance; + instance = (uint8_t)FGPIO_GetInstance(base); + PORT_Type *portBase; + portBase = s_portBases[instance]; + return portBase->ISFR; +} + +/*! + * brief Clears the multiple FGPIO pin interrupt status flag. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * param mask FGPIO pin number macro + */ +void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask) +{ + uint8_t instance; + instance = (uint8_t)FGPIO_GetInstance(base); + PORT_Type *portBase; + portBase = s_portBases[instance]; + portBase->ISFR = mask; +} +#endif +#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER +/*! + * brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit + * words. Each 32-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data + * bytes in the GACR follow a standard little endian + * data convention. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * param mask FGPIO pin number macro + */ +void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute) +{ + base->GACR = (attribute << FGPIO_GACR_ACB0_SHIFT) | (attribute << FGPIO_GACR_ACB1_SHIFT) | + (attribute << FGPIO_GACR_ACB2_SHIFT) | (attribute << FGPIO_GACR_ACB3_SHIFT); +} +#endif + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ diff --git a/source/hic_hal/freescale/kl27z/fsl_gpio.h b/source/hic_hal/freescale/kl27z/fsl_gpio.h new file mode 100644 index 000000000..14ea5094e --- /dev/null +++ b/source/hic_hal/freescale/kl27z/fsl_gpio.h @@ -0,0 +1,538 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_GPIO_H_ +#define _FSL_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gpio + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief GPIO driver version 2.4.1. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 4, 1)) +/*@}*/ + +/*! @brief GPIO direction definition */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} gpio_pin_direction_t; + +#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER +/*! @brief GPIO checker attribute */ +typedef enum _gpio_checker_attribute +{ + kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW = + 0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW = + 0x01U, /*!< User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW = + 0x02U, /*!< User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW = + 0x03U, /*!< User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW = + 0x04U, /*!< User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW = + 0x05U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR = + 0x06U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read */ + kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN = + 0x07U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:None */ + kGPIO_IgnoreAttributeCheck = 0x80U, /*!< Ignores the attribute check */ +} gpio_checker_attribute_t; +#endif + +/*! + * @brief The GPIO pin configuration structure. + * + * Each pin can only be configured as either an output pin or an input pin at a time. + * If configured as an input pin, leave the outputConfig unused. + * Note that in some use cases, the corresponding port property should be configured in advance + * with the PORT_SetPinConfig(). + */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ + /* Output configurations; ignore if configured as an input pin */ + uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ +} gpio_pin_config_t; + +#if (defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +/*! @brief Configures the interrupt generation condition. */ +typedef enum _gpio_interrupt_config +{ + kGPIO_InterruptStatusFlagDisabled = 0x0U, /*!< Interrupt status flag is disabled. */ + kGPIO_DMARisingEdge = 0x1U, /*!< ISF flag and DMA request on rising edge. */ + kGPIO_DMAFallingEdge = 0x2U, /*!< ISF flag and DMA request on falling edge. */ + kGPIO_DMAEitherEdge = 0x3U, /*!< ISF flag and DMA request on either edge. */ + kGPIO_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */ + kGPIO_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */ + kGPIO_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */ + kGPIO_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */ + kGPIO_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */ + kGPIO_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */ + kGPIO_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */ + kGPIO_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */ + kGPIO_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */ + kGPIO_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */ +} gpio_interrupt_config_t; +#endif +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup gpio_driver + * @{ + */ + +/*! @name GPIO Configuration */ +/*@{*/ + +/*! + * @brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, as either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration. + * @code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param pin GPIO port pin number + * @param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); + +/*@}*/ + +/*! @name GPIO Output Operations */ +/*@{*/ + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param pin GPIO pin number + * @param output GPIO pin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output) +{ + uint32_t u32flag = 1; + + if (output == 0U) + { + base->PCOR = u32flag << pin; + } + else + { + base->PSOR = u32flag << pin; + } +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask) +{ + base->PSOR = mask; +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask) +{ + base->PCOR = mask; +} + +/*! + * @brief Reverses the current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask) +{ + base->PTOR = mask; +} + +/*@}*/ + +/*! @name GPIO Input Operations */ +/*@{*/ + +/*! + * @brief Reads the current input value of the GPIO port. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param pin GPIO pin number + * @retval GPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin) +{ + return (((base->PDIR) >> pin) & 0x01U); +} + +/*@}*/ + +/*! @name GPIO Interrupt */ +/*@{*/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +/*! + * @brief Reads the GPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @retval The current GPIO port interrupt status flag, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base); + +/*! + * @brief Clears multiple GPIO pin interrupt status flags. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask); +#else +/*! + * @brief Configures the gpio pin interrupt/DMA request. + * + * @param base GPIO peripheral base pointer. + * @param pin GPIO pin number. + * @param config GPIO pin interrupt configuration. + * - #kGPIO_InterruptStatusFlagDisabled: Interrupt/DMA request disabled. + * - #kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). + * - #kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). + * - #kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). + * - #kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). + * - #kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). + * - #kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). + * - #kGPIO_InterruptLogicZero : Interrupt when logic zero. + * - #kGPIO_InterruptRisingEdge : Interrupt on rising edge. + * - #kGPIO_InterruptFallingEdge: Interrupt on falling edge. + * - #kGPIO_InterruptEitherEdge : Interrupt on either edge. + * - #kGPIO_InterruptLogicOne : Interrupt when logic one. + * - #kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit). + * - #kGPIO_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit). + */ +static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_config_t config) +{ + assert(base); + + base->ICR[pin] = (base->ICR[pin] & ~GPIO_ICR_IRQC_MASK) | GPIO_ICR_IRQC(config); +} +/*! + * brief Clears GPIO pin interrupt status flags. + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * param mask GPIO pin number macro + */ +void GPIO_GpioClearInterruptFlags(GPIO_Type *base, uint32_t mask); +/*! + * @brief Reads the GPIO DMA request flags. + * The corresponding flag will be cleared automatically at the completion of the requested + * DMA transfer + */ +static inline uint32_t GPIO_GetPinsDMARequestFlags(GPIO_Type *base) +{ + assert(base); + return (base->ISFR[1]); +} + +/*! + * @brief Sets the GPIO interrupt configuration in PCR register for multiple pins. + * + * @param base GPIO peripheral base pointer. + * @param mask GPIO pin number macro. + * @param config GPIO pin interrupt configuration. + * - #kGPIO_InterruptStatusFlagDisabled: Interrupt disabled. + * - #kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). + * - #kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). + * - #kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). + * - #kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). + * - #kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). + * - #kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). + * - #kGPIO_InterruptLogicZero : Interrupt when logic zero. + * - #kGPIO_InterruptRisingEdge : Interrupt on rising edge. + * - #kGPIO_InterruptFallingEdge: Interrupt on falling edge. + * - #kGPIO_InterruptEitherEdge : Interrupt on either edge. + * - #kGPIO_InterruptLogicOne : Interrupt when logic one. + * - #kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit). + * - #kGPIO_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).. + */ +static inline void GPIO_SetMultipleInterruptPinsConfig(GPIO_Type *base, uint32_t mask, gpio_interrupt_config_t config) +{ + assert(base); + + if (mask & 0xffffU) + { + base->GICLR = (GPIO_ICR_IRQC(config)) | (mask & 0xffffU); + } + mask = mask >> 16; + if (mask) + { + base->GICHR = (GPIO_ICR_IRQC(config)) | (mask & 0xffffU); + } +} +#endif + +#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER +/*! + * brief The GPIO module supports a device-specific number of data ports, organized as 32-bit + * words/8-bit Bytes. Each 32-bit/8-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the GPIO programming model. If the GPIO module's GACR register + * organized as 32-bit words, the attribute controls for the 4 data bytes in the GACR follow a standard little + * endian data convention. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute); +#endif + +/*@}*/ +/*! @} */ + +/*! + * @addtogroup fgpio_driver + * @{ + */ + +/* + * Introduces the FGPIO feature. + * + * The FGPIO features are only support on some Kinetis MCUs. The FGPIO registers are aliased to the IOPORT + * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and + * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO. + */ + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +/*! @name FGPIO Configuration */ +/*@{*/ + +#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL +/*! + * @brief Initializes the FGPIO peripheral. + * + * This function ungates the FGPIO clock. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + */ +void FGPIO_PortInit(FGPIO_Type *base); +#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */ + +/*! + * @brief Initializes a FGPIO pin used by the board. + * + * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file. + * Then, call the FGPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration: + * @code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param pin FGPIO port pin number + * @param config FGPIO pin configuration pointer + */ +void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); + +/*@}*/ + +/*! @name FGPIO Output Operations */ +/*@{*/ + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param pin FGPIO pin number + * @param output FGPIOpin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void FGPIO_PinWrite(FGPIO_Type *base, uint32_t pin, uint8_t output) +{ + uint32_t u32flag = 1; + + if (output == 0U) + { + base->PCOR = u32flag << pin; + } + else + { + base->PSOR = u32flag << pin; + } +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +static inline void FGPIO_PortSet(FGPIO_Type *base, uint32_t mask) +{ + base->PSOR = mask; +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 0. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +static inline void FGPIO_PortClear(FGPIO_Type *base, uint32_t mask) +{ + base->PCOR = mask; +} + +/*! + * @brief Reverses the current output logic of the multiple FGPIO pins. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +static inline void FGPIO_PortToggle(FGPIO_Type *base, uint32_t mask) +{ + base->PTOR = mask; +} +/*@}*/ + +/*! @name FGPIO Input Operations */ +/*@{*/ + +/*! + * @brief Reads the current input value of the FGPIO port. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param pin FGPIO pin number + * @retval FGPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t FGPIO_PinRead(FGPIO_Type *base, uint32_t pin) +{ + return (((base->PDIR) >> pin) & 0x01U); +} +/*@}*/ + +/*! @name FGPIO Interrupt */ +/*@{*/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) + +/*! + * @brief Reads the FGPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level-sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base); + +/*! + * @brief Clears the multiple FGPIO pin interrupt status flag. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask); +#endif +#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER +/*! + * @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit + * words. Each 32-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data + * bytes in the GACR follow a standard little endian + * data convention. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute); +#endif + +/*@}*/ + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_GPIO_H_*/ diff --git a/source/hic_hal/freescale/kl27z/fsl_i2c.c b/source/hic_hal/freescale/kl27z/fsl_i2c.c new file mode 100644 index 000000000..3752dfecc --- /dev/null +++ b/source/hic_hal/freescale/kl27z/fsl_i2c.c @@ -0,0 +1,2394 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_i2c.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.i2c" +#endif + +/*! @brief i2c transfer state. */ +enum _i2c_transfer_states +{ + kIdleState = 0x0U, /*!< I2C bus idle. */ + kCheckAddressState = 0x1U, /*!< 7-bit address check state. */ + kSendCommandState = 0x2U, /*!< Send command byte phase. */ + kSendDataState = 0x3U, /*!< Send data transfer phase. */ + kReceiveDataBeginState = 0x4U, /*!< Receive data transfer phase begin. */ + kReceiveDataState = 0x5U, /*!< Receive data transfer phase. */ +}; + +/*! @brief Common sets of flags used by the driver. */ +enum _i2c_flag_constants +{ +/*! All flags which are cleared by the driver upon starting a transfer. */ +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StartDetectFlag | kI2C_StopDetectFlag, + kIrqFlags = kI2C_GlobalInterruptEnable | kI2C_StartStopDetectInterruptEnable, +#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StopDetectFlag, + kIrqFlags = kI2C_GlobalInterruptEnable | kI2C_StopDetectInterruptEnable, +#else + kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag, + kIrqFlags = kI2C_GlobalInterruptEnable, +#endif + +}; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*i2c_isr_t)(I2C_Type *base, void *i2cHandle); + +/*! @brief static variable to keep current configured baudrate. */ +#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL +static uint32_t g_baudrate = 100000; +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Set SCL/SDA hold time, this API receives SCL stop hold time, calculate the + * closest SCL divider and MULT value for the SDA hold time, SCL start and SCL stop + * hold time. To reduce the ROM size, SDA/SCL hold value mapping table is not provided, + * assume SCL divider = SCL stop hold value *2 to get the closest SCL divider value and MULT + * value, then the related SDA hold time, SCL start and SCL stop hold time is used. + * + * @param base I2C peripheral base address. + * @param sourceClock_Hz I2C functional clock frequency in Hertz. + * @param sclStopHoldTime_ns SCL stop hold time in ns. + */ +static void I2C_SetHoldTime(I2C_Type *base, uint32_t sclStopHoldTime_ns, uint32_t sourceClock_Hz); + +/*! + * @brief Set up master transfer, send slave address and decide the initial + * transfer state. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param xfer pointer to i2c_master_transfer_t structure. + */ +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Check and clear status operation. + * + * @param base I2C peripheral base address. + * @param status current i2c hardware status. + * @retval kStatus_Success No error found. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStatus_I2C_Nak Received Nak error. + */ +static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status); + +/*! + * @brief Master run transfer state machine to perform a byte of transfer. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + * @param isDone input param to get whether the thing is done, true is done + * @retval kStatus_Success No error found. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStatus_I2C_Nak Received Nak error. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + */ +static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone); + +/*! + * @brief I2C common interrupt handler. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + */ +static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to i2c handles for each instance. */ +static void *s_i2cHandle[FSL_FEATURE_SOC_I2C_COUNT]; + +/*! @brief SCL clock divider used to calculate baudrate. */ +static const uint16_t s_i2cDividerTable[] = { + 20, 22, 24, 26, 28, 30, 34, 40, 28, 32, 36, 40, 44, 48, 56, 68, + 48, 56, 64, 72, 80, 88, 104, 128, 80, 96, 112, 128, 144, 160, 192, 240, + 160, 192, 224, 256, 288, 320, 384, 480, 320, 384, 448, 512, 576, 640, 768, 960, + 640, 768, 896, 1024, 1152, 1280, 1536, 1920, 1280, 1536, 1792, 2048, 2304, 2560, 3072, 3840}; + +/*! @brief Pointers to i2c IRQ number for each instance. */ +static const IRQn_Type s_i2cIrqs[] = I2C_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to i2c clocks for each instance. */ +static const clock_ip_name_t s_i2cClocks[] = I2C_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointer to master IRQ handler for each instance. */ +static i2c_isr_t s_i2cMasterIsr; + +/*! @brief Pointer to slave IRQ handler for each instance. */ +static i2c_isr_t s_i2cSlaveIsr; + +/*! @brief Pointers to i2c bases for each instance. */ +static I2C_Type *const s_i2cBases[] = I2C_BASE_PTRS; +/******************************************************************************* + * Codes + ******************************************************************************/ + +/*! + * brief Get instance number for I2C module. + * + * param base I2C peripheral base address. + */ +uint32_t I2C_GetInstance(I2C_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_i2cBases); instance++) + { + if (s_i2cBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_i2cBases)); + + return instance; +} + +static void I2C_SetHoldTime(I2C_Type *base, uint32_t sclStopHoldTime_ns, uint32_t sourceClock_Hz) +{ + uint32_t multiplier; + uint32_t computedSclHoldTime; + uint32_t absError; + uint32_t bestError = UINT32_MAX; + uint32_t bestMult = 0u; + uint32_t bestIcr = 0u; + uint32_t u32flag = 1u; + uint8_t mult; + uint8_t i; + + /* Search for the settings with the lowest error. Mult is the MULT field of the I2C_F register, + * and ranges from 0-2. It selects the multiplier factor for the divider. */ + /* SDA hold time = bus period (s) * mul * SDA hold value. */ + /* SCL start hold time = bus period (s) * mul * SCL start hold value. */ + /* SCL stop hold time = bus period (s) * mul * SCL stop hold value. */ + + for (mult = 0u; (mult <= 2u) && (bestError != 0u); ++mult) + { + multiplier = u32flag << mult; + + /* Scan table to find best match. */ + for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(s_i2cDividerTable[0]); ++i) + { + /* Assume SCL hold(stop) value = s_i2cDividerTable[i]/2. */ + computedSclHoldTime = ((multiplier * s_i2cDividerTable[i]) * 500000U) / (sourceClock_Hz / 1000U); + absError = sclStopHoldTime_ns > computedSclHoldTime ? (sclStopHoldTime_ns - computedSclHoldTime) : + (computedSclHoldTime - sclStopHoldTime_ns); + + if (absError < bestError) + { + bestMult = mult; + bestIcr = i; + bestError = absError; + + /* If the error is 0, then we can stop searching because we won't find a better match. */ + if (absError == 0u) + { + break; + } + } + } + } + + /* Set frequency register based on best settings. */ + base->F = I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr); +} + +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + status_t result = kStatus_Success; + i2c_direction_t direction = xfer->direction; + + /* Initialize the handle transfer information. */ + handle->transfer = *xfer; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Initial transfer state. */ + if (handle->transfer.subaddressSize > 0u) + { + if (xfer->direction == kI2C_Read) + { + direction = kI2C_Write; + } + } + + handle->state = (uint8_t)kCheckAddressState; + + /* Clear all status before transfer. */ + I2C_MasterClearStatusFlags(base, (uint32_t)kClearFlags); + + /* Handle no start option. */ + if (0U != (handle->transfer.flags & (uint32_t)kI2C_TransferNoStartFlag)) + { + /* No need to send start flag, directly go to send command or data */ + if (handle->transfer.subaddressSize > 0u) + { + handle->state = (uint8_t)kSendCommandState; + } + else + { + if (direction == kI2C_Write) + { + /* Next state, send data. */ + handle->state = (uint8_t)kSendDataState; + } + else + { + /* Only support write with no stop signal. */ + return kStatus_InvalidArgument; + } + } + + /* Wait for TCF bit and manually trigger tx interrupt. */ + while (0U == (base->S & (uint8_t)kI2C_TransferCompleteFlag)) + { + } + I2C_MasterTransferHandleIRQ(base, handle); + } + /* If repeated start is requested, send repeated start. */ + else if (0U != (handle->transfer.flags & (uint32_t)kI2C_TransferRepeatedStartFlag)) + { + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction); + } + + return result; +} + +static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check arbitration lost. */ + if (0U != (status & (uint32_t)kI2C_ArbitrationLostFlag)) + { + /* Clear arbitration lost flag. */ + base->S = (uint8_t)kI2C_ArbitrationLostFlag; + result = kStatus_I2C_ArbitrationLost; + } + /* Check NAK */ + else if (0U != (status & (uint32_t)kI2C_ReceiveNakFlag)) + { + result = kStatus_I2C_Nak; + } + else + { + } + + return result; +} + +static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) +{ + status_t result = kStatus_Success; + uint32_t statusFlags = base->S; + *isDone = false; + volatile uint8_t dummy = 0; + uint32_t tmpDataSize = handle->transfer.dataSize; + bool ignoreNak = ((handle->state == (uint8_t)kSendDataState) && (tmpDataSize == 0U)) || + ((handle->state == (uint8_t)kReceiveDataState) && (tmpDataSize == 1U)); + + /* Add this to avoid build warning. */ + dummy++; + + /* Check & clear error flags. */ + result = I2C_CheckAndClearError(base, statusFlags); + + /* Ignore Nak when it's appeared for last byte. */ + if ((result == kStatus_I2C_Nak) && ignoreNak) + { + result = kStatus_Success; + } + + /* Handle Check address state to check the slave address is Acked in slave + probe application. */ + if (handle->state == (uint8_t)kCheckAddressState) + { + if (0U != (statusFlags & (uint8_t)kI2C_ReceiveNakFlag)) + { + result = kStatus_I2C_Addr_Nak; + } + else + { + if (handle->transfer.subaddressSize > 0U) + { + handle->state = (uint8_t)kSendCommandState; + } + else + { + if (handle->transfer.direction == kI2C_Write) + { + /* Next state, send data. */ + handle->state = (uint8_t)kSendDataState; + } + else + { + /* Next state, receive data begin. */ + handle->state = (uint8_t)kReceiveDataBeginState; + } + } + } + } + + if (0 != result) + { + return result; + } + + /* Run state machine. */ + switch (handle->state) + { + /* Send I2C command. */ + case (uint8_t)kSendCommandState: + if (0U != (handle->transfer.subaddressSize)) + { + handle->transfer.subaddressSize--; + base->D = (uint8_t)((handle->transfer.subaddress) >> (8U * handle->transfer.subaddressSize)); + } + else + { + if (handle->transfer.direction == kI2C_Write) + { + /* Send first byte of data. */ + if (handle->transfer.dataSize > 0U) + { + /* Next state, send data. */ + handle->state = (uint8_t)kSendDataState; + base->D = *handle->transfer.data; + handle->transfer.data++; + handle->transfer.dataSize--; + } + else + { + *isDone = true; + } + } + else + { + /* Send repeated start and slave address. */ + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read); + + /* Next state, receive data begin. */ + handle->state = (uint8_t)kReceiveDataBeginState; + } + } + break; + + /* Send I2C data. */ + case (uint8_t)kSendDataState: + /* Send one byte of data. */ + if (handle->transfer.dataSize > 0U) + { + base->D = *handle->transfer.data; + handle->transfer.data++; + handle->transfer.dataSize--; + } + else + { + *isDone = true; + } + break; + + /* Start I2C data receive. */ + case (uint8_t)kReceiveDataBeginState: + +#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL + base->SMB |= I2C_SMB_FACK_MASK; +#endif + + base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Read dummy to release the bus. */ + dummy = base->D; + + if (handle->transfer.dataSize == 1U) + { + /* Issue NACK on read. */ + base->C1 |= I2C_C1_TXAK_MASK; +#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL + base->SMB &= ~(uint8_t)I2C_SMB_FACK_MASK; +#endif + } + + /* Next state, receive data. */ + handle->state = (uint8_t)kReceiveDataState; + break; + + /* Receive I2C data. */ + case (uint8_t)kReceiveDataState: + /* Receive one byte of data. */ + if (0U != (handle->transfer.dataSize--)) + { + if (handle->transfer.dataSize == 0U) + { + *isDone = true; + + /* Send stop if kI2C_TransferNoStop is not asserted. */ + if (0U == (handle->transfer.flags & (uint32_t)kI2C_TransferNoStopFlag)) + { + result = I2C_MasterStop(base); + } + else + { + base->C1 |= I2C_C1_TX_MASK; + } + } + + /* Read the data byte into the transfer buffer. */ + *handle->transfer.data = base->D; + handle->transfer.data++; + +#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL + if (handle->transfer.dataSize != 0U) + { + /* Clear the TXAK flag. */ + base->C1 &= ~(uint8_t)I2C_C1_TXAK_MASK; + + for (uint32_t i = SystemCoreClock / (2U * g_baudrate); i > 0U; i--) + { + __NOP(); + } + + /* Do dummy read. */ + dummy = base->D; + } +#endif + if (handle->transfer.dataSize == 1U) + { + /* Issue NACK on read. */ + base->C1 |= I2C_C1_TXAK_MASK; +#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL + base->SMB &= ~(uint8_t)I2C_SMB_FACK_MASK; +#endif + } + } + + break; + + default: + break; + } + + return result; +} + +static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle) +{ + uint8_t tmpS = base->S; + uint8_t tmpC1 = base->C1; + + /* Check if master interrupt. */ + if ((0U != (tmpC1 & I2C_C1_MST_MASK)) || (0U != (tmpS & (uint8_t)kI2C_ArbitrationLostFlag))) + { + s_i2cMasterIsr(base, handle); + } + else + { + s_i2cSlaveIsr(base, handle); + } + __DSB(); +} + +/*! + * brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and configure the I2C with master configuration. + * + * note This API should be called at the beginning of the application. + * Otherwise, any operation to the I2C module can cause a hard fault + * because the clock is not enabled. The configuration structure can be custom filled + * or it can be set with default values by using the I2C_MasterGetDefaultConfig(). + * After calling this API, the master is ready to transfer. + * This is an example. + * code + * i2c_master_config_t config = { + * .enableMaster = true, + * .enableStopHold = false, + * .highDrive = false, + * .baudRate_Bps = 100000, + * .glitchFilterWidth = 0 + * }; + * I2C_MasterInit(I2C0, &config, 12000000U); + * endcode + * + * param base I2C base pointer + * param masterConfig A pointer to the master configuration structure + * param srcClock_Hz I2C peripheral clock frequency in Hz + */ +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert(NULL != masterConfig); + assert(0U != srcClock_Hz); + + /* Temporary register for filter read. */ + uint8_t fltReg; +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE + uint8_t s2Reg; +#endif +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable I2C clock. */ + CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset the module. */ + base->A1 = 0; + base->F = 0; + base->C1 = 0; + base->S = 0xFFU; + base->C2 = 0; +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + base->FLT = 0x50U; +#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + base->FLT = 0x40U; +#endif + base->RA = 0; + + /* Disable I2C prior to configuring it. */ + base->C1 &= ~(uint8_t)(I2C_C1_IICEN_MASK); + + /* Clear all flags. */ + I2C_MasterClearStatusFlags(base, (uint32_t)kClearFlags); + + /* Configure baud rate. */ + I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); + + /* Read out the FLT register. */ + fltReg = base->FLT; + +#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF + /* Configure the stop / hold enable. */ + fltReg &= ~(uint8_t)(I2C_FLT_SHEN_MASK); + fltReg |= I2C_FLT_SHEN(masterConfig->enableStopHold); +#endif + + /* Configure the glitch filter value. */ + fltReg &= ~(uint8_t)(I2C_FLT_FLT_MASK); + fltReg |= I2C_FLT_FLT(masterConfig->glitchFilterWidth); + + /* Write the register value back to the filter register. */ + base->FLT = fltReg; + +/* Enable/Disable double buffering. */ +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE + s2Reg = (uint8_t)(base->S2 & (~I2C_S2_DFEN_MASK)); + base->S2 = s2Reg | I2C_S2_DFEN(masterConfig->enableDoubleBuffering); +#endif + + /* Enable the I2C peripheral based on the configuration. */ + base->C1 = I2C_C1_IICEN(masterConfig->enableMaster); +} + +/*! + * brief De-initializes the I2C master peripheral. Call this API to gate the I2C clock. + * The I2C master module can't work unless the I2C_MasterInit is called. + * param base I2C base pointer + */ +void I2C_MasterDeinit(I2C_Type *base) +{ + /* Disable I2C module. */ + I2C_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable I2C clock. */ + CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Sets the I2C master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterConfigure(). + * Use the initialized structure unchanged in the I2C_MasterConfigure() or modify + * the structure before calling the I2C_MasterConfigure(). + * This is an example. + * code + * i2c_master_config_t config; + * I2C_MasterGetDefaultConfig(&config); + * endcode + * param masterConfig A pointer to the master configuration structure. + */ +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) +{ + assert(NULL != masterConfig); + + /* Initializes the configure structure to zero. */ + (void)memset(masterConfig, 0, sizeof(*masterConfig)); + + /* Default baud rate at 100kbps. */ + masterConfig->baudRate_Bps = 100000U; + +/* Default stop hold enable is disabled. */ +#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF + masterConfig->enableStopHold = false; +#endif + + /* Default glitch filter value is no filter. */ + masterConfig->glitchFilterWidth = 0U; + +/* Default enable double buffering. */ +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE + masterConfig->enableDoubleBuffering = true; +#endif + + /* Enable the I2C peripheral. */ + masterConfig->enableMaster = true; +} + +/*! + * brief Enables I2C interrupt requests. + * + * param base I2C base pointer + * param mask interrupt source + * The parameter can be combination of the following source if defined: + * arg kI2C_GlobalInterruptEnable + * arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * arg kI2C_SdaTimeoutInterruptEnable + */ +void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask) +{ +#ifdef I2C_HAS_STOP_DETECT + uint8_t fltReg; +#endif + + if (0U != (mask & (uint32_t)kI2C_GlobalInterruptEnable)) + { + base->C1 |= I2C_C1_IICIE_MASK; + } + +#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + if (0U != (mask & (uint32_t)kI2C_StopDetectInterruptEnable)) + { + fltReg = base->FLT; + + /* Keep STOPF flag. */ + fltReg &= ~I2C_FLT_STOPF_MASK; + + /* Stop detect enable. */ + fltReg |= I2C_FLT_STOPIE_MASK; + base->FLT = fltReg; + } +#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + if (0U != (mask & (uint32_t)kI2C_StartStopDetectInterruptEnable)) + { + fltReg = base->FLT; + + /* Keep STARTF and STOPF flags. */ + fltReg &= ~(uint8_t)(I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK); + + /* Start and stop detect enable. */ + fltReg |= I2C_FLT_SSIE_MASK; + base->FLT = fltReg; + } +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +} + +/*! + * brief Disables I2C interrupt requests. + * + * param base I2C base pointer + * param mask interrupt source + * The parameter can be combination of the following source if defined: + * arg kI2C_GlobalInterruptEnable + * arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * arg kI2C_SdaTimeoutInterruptEnable + */ +void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask) +{ + if (0U != (mask & (uint32_t)kI2C_GlobalInterruptEnable)) + { + base->C1 &= ~(uint8_t)I2C_C1_IICIE_MASK; + } + +#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + if (0U != (mask & (uint32_t)kI2C_StopDetectInterruptEnable)) + { + base->FLT &= ~(I2C_FLT_STOPIE_MASK | I2C_FLT_STOPF_MASK); + } +#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + if (0U != (mask & (uint32_t)kI2C_StartStopDetectInterruptEnable)) + { + base->FLT &= ~(uint8_t)(I2C_FLT_SSIE_MASK | I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK); + } +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +} + +/*! + * brief Sets the I2C master transfer baud rate. + * + * param base I2C base pointer + * param baudRate_Bps the baud rate value in bps + * param srcClock_Hz Source clock + */ +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t multiplier; + uint32_t computedRate; + uint32_t absError; + uint32_t bestError = UINT32_MAX; + uint32_t bestMult = 0u; + uint32_t bestIcr = 0u; + uint32_t u32flag = 1u; + uint8_t mult; + uint8_t i; + + /* Search for the settings with the lowest error. Mult is the MULT field of the I2C_F register, + * and ranges from 0-2. It selects the multiplier factor for the divider. */ + for (mult = 0u; (mult <= 2u) && (bestError != 0u); ++mult) + { + multiplier = u32flag << mult; + + /* Scan table to find best match. */ + for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(uint16_t); ++i) + { + computedRate = srcClock_Hz / (multiplier * s_i2cDividerTable[i]); + absError = baudRate_Bps > computedRate ? (baudRate_Bps - computedRate) : (computedRate - baudRate_Bps); + + if (absError < bestError) + { + bestMult = mult; + bestIcr = i; + bestError = absError; + + /* If the error is 0, then we can stop searching because we won't find a better match. */ + if (absError == 0u) + { + break; + } + } + } + } + +#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL + g_baudrate = baudRate_Bps; +#endif + /* Set frequency register based on best settings. */ + base->F = I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr); +} + +/*! + * brief Sends a START on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. + * The slave address is sent following the I2C START signal. + * + * param base I2C peripheral base pointer + * param address 7-bit slave device address. + * param direction Master transfer directions(transmit/receive). + * retval kStatus_Success Successfully send the start signal. + * retval kStatus_I2C_Busy Current bus is busy. + */ +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + status_t result = kStatus_Success; + uint32_t statusFlags = I2C_MasterGetStatusFlags(base); + + /* Return an error if the bus is already in use. */ + if (0U != (statusFlags & (uint32_t)kI2C_BusBusyFlag)) + { + result = kStatus_I2C_Busy; + } + else + { + /* Send the START signal. */ + base->C1 |= I2C_C1_MST_MASK | I2C_C1_TX_MASK; + +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; + while ((0U == (base->S2 & I2C_S2_EMPTY_MASK)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else + while (0U == (base->S2 & I2C_S2_EMPTY_MASK)) + { + } +#endif +#endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */ + + base->D = (uint8_t)(((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); + } + + return result; +} + +/*! + * brief Sends a REPEATED START on the I2C bus. + * + * param base I2C peripheral base pointer + * param address 7-bit slave device address. + * param direction Master transfer directions(transmit/receive). + * retval kStatus_Success Successfully send the start signal. + * retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. + */ +status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + status_t result = kStatus_Success; + uint8_t savedMult; + uint32_t statusFlags = I2C_MasterGetStatusFlags(base); + uint8_t timeDelay = 6; + + /* Return an error if the bus is already in use, but not by us. */ + if ((0U == (base->C1 & I2C_C1_MST_MASK)) && (0U != (statusFlags & (uint32_t)kI2C_BusBusyFlag))) + { + result = kStatus_I2C_Busy; + } + else + { + savedMult = base->F; + base->F = savedMult & (~(uint8_t)I2C_F_MULT_MASK); + + /* We are already in a transfer, so send a repeated start. */ + base->C1 |= I2C_C1_RSTA_MASK | I2C_C1_TX_MASK; + + /* Restore the multiplier factor. */ + base->F = savedMult; + + /* Add some delay to wait the Re-Start signal. */ + while (0U != (timeDelay--)) + { + __NOP(); + } + +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; + while ((!(base->S2 & I2C_S2_EMPTY_MASK)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else + while (0U == (base->S2 & I2C_S2_EMPTY_MASK)) + { + } +#endif +#endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */ + + base->D = (uint8_t)(((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); + } + + return result; +} + +/*! + * brief Sends a STOP signal on the I2C bus. + * + * retval kStatus_Success Successfully send the stop signal. + * retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterStop(I2C_Type *base) +{ + status_t result = kStatus_Success; + + /* Issue the STOP command on the bus. */ + base->C1 &= ~(uint8_t)(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until bus not busy. */ + while ((base->S & (uint8_t)kI2C_BusBusyFlag) && (--waitTimes)) + { + } + + if (waitTimes == 0) + { + result = kStatus_I2C_Timeout; + } +#else + /* Wait until data transfer complete. */ + while (0U != (base->S & (uint8_t)kI2C_BusBusyFlag)) + { + } +#endif + + return result; +} + +/*! + * brief Gets the I2C status flags. + * + * param base I2C base pointer + * return status flag, use status flag to AND #_i2c_flags to get the related status. + */ +uint32_t I2C_MasterGetStatusFlags(I2C_Type *base) +{ + uint32_t statusFlags = base->S; + +#ifdef I2C_HAS_STOP_DETECT + /* Look up the STOPF bit from the filter register. */ + if (0U != (base->FLT & I2C_FLT_STOPF_MASK)) + { + statusFlags |= (uint32_t)kI2C_StopDetectFlag; + } +#endif + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + /* Look up the STARTF bit from the filter register. */ + if (0U != (base->FLT & I2C_FLT_STARTF_MASK)) + { + statusFlags |= (uint32_t)kI2C_StartDetectFlag; + } +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ + + return statusFlags; +} + +/*! + * brief Performs a polling send transaction on the I2C bus. + * + * param base The I2C peripheral base pointer. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag + * to issue a stop and kI2C_TransferNoStop to not send a stop. + * retval kStatus_Success Successfully complete the data transmission. + * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags) +{ + status_t result = kStatus_Success; + uint8_t statusFlags = 0; + +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until the data register is ready for transmit. */ + while ((!(base->S & kI2C_TransferCompleteFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else + /* Wait until the data register is ready for transmit. */ + while (0U == (base->S & (uint8_t)kI2C_TransferCompleteFlag)) + { + } +#endif + + /* Clear the IICIF flag. */ + base->S = (uint8_t)kI2C_IntPendingFlag; + + /* Setup the I2C peripheral to transmit data. */ + base->C1 |= I2C_C1_TX_MASK; + + while (0U != (txSize--)) + { + /* Send a byte of data. */ + base->D = *txBuff++; + +#if I2C_WAIT_TIMEOUT + waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until data transfer complete. */ + while ((!(base->S & kI2C_IntPendingFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else + /* Wait until data transfer complete. */ + while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) + { + } +#endif + statusFlags = base->S; + + /* Clear the IICIF flag. */ + base->S = (uint8_t)kI2C_IntPendingFlag; + + /* Check if arbitration lost or no acknowledgement (NAK), return failure status. */ + if (0U != (statusFlags & (uint8_t)kI2C_ArbitrationLostFlag)) + { + base->S = (uint8_t)kI2C_ArbitrationLostFlag; + result = kStatus_I2C_ArbitrationLost; + } + + if ((0U != (statusFlags & (uint8_t)kI2C_ReceiveNakFlag)) && (0U != txSize)) + { + base->S = (uint8_t)kI2C_ReceiveNakFlag; + result = kStatus_I2C_Nak; + } + + if (result != kStatus_Success) + { + /* Breaking out of the send loop. */ + break; + } + } + + if (((result == kStatus_Success) && (0U == (flags & (uint32_t)kI2C_TransferNoStopFlag))) || + (result == kStatus_I2C_Nak)) + { + /* Clear the IICIF flag. */ + base->S = (uint8_t)kI2C_IntPendingFlag; + + /* Send stop. */ + result = I2C_MasterStop(base); + } + + return result; +} + +/*! + * brief Performs a polling receive transaction on the I2C bus. + * + * note The I2C_MasterReadBlocking function stops the bus before reading the final byte. + * Without stopping the bus prior for the final read, the bus issues another read, resulting + * in garbage data being read into the data register. + * + * param base I2C peripheral base pointer. + * param rxBuff The pointer to the data to store the received data. + * param rxSize The length in bytes of the data to be received. + * param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag + * to issue a stop and kI2C_TransferNoStop to not send a stop. + * retval kStatus_Success Successfully complete the data transmission. + * retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags) +{ + status_t result = kStatus_Success; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + +#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL + base->SMB |= I2C_SMB_FACK_MASK; +#endif + +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until the data register is ready for transmit. */ + while ((!(base->S & kI2C_TransferCompleteFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else + /* Wait until the data register is ready for transmit. */ + while (0U == (base->S & (uint8_t)kI2C_TransferCompleteFlag)) + { + } +#endif + + /* Setup the I2C peripheral to receive data. */ + base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Do dummy read. */ + dummy = base->D; + + if (rxSize == 1U) + { + /* Issue NACK on read. */ + base->C1 |= I2C_C1_TXAK_MASK; +#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL + base->SMB &= ~(uint8_t)I2C_SMB_FACK_MASK; +#endif + } + + /* Clear the IICIF flag. */ + base->S = (uint8_t)kI2C_IntPendingFlag; + + while (0U != (rxSize--)) + { +#if I2C_WAIT_TIMEOUT + waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until data transfer complete. */ + while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else + /* Wait until data transfer complete. */ + while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) + { + } +#endif + + if (rxSize == 0U) + { + if (0U == (flags & (uint32_t)kI2C_TransferNoStopFlag)) + { + /* Issue STOP command before reading last byte. */ + result = I2C_MasterStop(base); + } + else + { + /* Change direction to Tx to avoid extra clocks. */ + base->C1 |= I2C_C1_TX_MASK; + } + } + + /* Read from the data register. */ + *rxBuff++ = base->D; + +#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL + if (rxSize != 0U) + { + /* Clear the TXAK flag. */ + base->C1 &= ~(uint8_t)I2C_C1_TXAK_MASK; + + for (uint32_t i = (SystemCoreClock / (2U * g_baudrate)); i > 0U; i--) + { + __NOP(); + } + + /* Do dummy read. */ + dummy = base->D; + } +#endif + + if (rxSize == 1U) + { + base->C1 |= I2C_C1_TXAK_MASK; +#if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL + /* Issue NACK on read. */ + base->SMB &= ~(uint8_t)I2C_SMB_FACK_MASK; +#endif + } + + /* Clear the IICIF flag. */ + base->S = (uint8_t)kI2C_IntPendingFlag; + } + + return result; +} + +/*! + * brief Performs a master polling transfer on the I2C bus. + * + * note The API does not return until the transfer succeeds or fails due + * to arbitration lost or receiving a NAK. + * + * param base I2C peripheral base address. + * param xfer Pointer to the transfer structure. + * retval kStatus_Success Successfully complete the data transmission. + * retval kStatus_I2C_Busy Previous transmission still not finished. + * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) +{ + assert(NULL != xfer); + + i2c_direction_t direction = xfer->direction; + status_t result = kStatus_Success; + + /* Clear all status before transfer. */ + I2C_MasterClearStatusFlags(base, (uint32_t)kClearFlags); + +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until the data register is ready for transmit. */ + while ((0U == (base->S & kI2C_TransferCompleteFlag)) && (0U != (--waitTimes))) + { + } + if (waitTimes == 0U) + { + return kStatus_I2C_Timeout; + } +#else + /* Wait until the data register is ready for transmit. */ + while (0U == (base->S & (uint8_t)kI2C_TransferCompleteFlag)) + { + } +#endif + + /* Change to send write address when it's a read operation with command. */ + if ((xfer->subaddressSize > 0U) && (xfer->direction == kI2C_Read)) + { + direction = kI2C_Write; + } + + /* Handle no start option, only support write with no start signal. */ + if (0U != (xfer->flags & (uint32_t)kI2C_TransferNoStartFlag)) + { + if (direction == kI2C_Read) + { + return kStatus_InvalidArgument; + } + } + /* If repeated start is requested, send repeated start. */ + else if (0U != (xfer->flags & (uint32_t)kI2C_TransferRepeatedStartFlag)) + { + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I2C_MasterStart(base, xfer->slaveAddress, direction); + } + + if (0U == (xfer->flags & (uint32_t)kI2C_TransferNoStartFlag)) + { + /* Return if error. */ + if (0 != result) + { + return result; + } + +#if I2C_WAIT_TIMEOUT + waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until data transfer complete. */ + while ((!(base->S & kI2C_IntPendingFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else + /* Wait until data transfer complete. */ + while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) + { + } +#endif + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + /* Return if error. */ + if (0 != result) + { + if (result == kStatus_I2C_Nak) + { + result = kStatus_I2C_Addr_Nak; + + (void)I2C_MasterStop(base); + } + + return result; + } + } + + /* Send subaddress. */ + if (0U != (xfer->subaddressSize)) + { + do + { + /* Clear interrupt pending flag. */ + base->S = (uint8_t)kI2C_IntPendingFlag; + + xfer->subaddressSize--; + base->D = (uint8_t)((xfer->subaddress) >> (8U * xfer->subaddressSize)); + +#if I2C_WAIT_TIMEOUT + waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until data transfer complete. */ + while ((!(base->S & kI2C_IntPendingFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else + /* Wait until data transfer complete. */ + while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) + { + } +#endif + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + if (0 != result) + { + if (result == kStatus_I2C_Nak) + { + (void)I2C_MasterStop(base); + } + + return result; + } + + } while (xfer->subaddressSize > 0u); + + if (xfer->direction == kI2C_Read) + { + /* Clear pending flag. */ + base->S = (uint8_t)kI2C_IntPendingFlag; + + /* Send repeated start and slave address. */ + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, kI2C_Read); + + /* Return if error. */ + if (0 != result) + { + return result; + } + +#if I2C_WAIT_TIMEOUT + waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until data transfer complete. */ + while ((!(base->S & kI2C_IntPendingFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else + /* Wait until data transfer complete. */ + while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) + { + } +#endif + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + if (0 != result) + { + if (result == kStatus_I2C_Nak) + { + result = kStatus_I2C_Addr_Nak; + + (void)I2C_MasterStop(base); + } + + return result; + } + } + } + + /* Transmit data. */ + if (xfer->direction == kI2C_Write) + { + if (xfer->dataSize > 0U) + { + uint8_t *tmpData = xfer->data; + size_t tmpDataSize = xfer->dataSize; + uint32_t tmpFlags = xfer->flags; + /* Send Data. */ + result = I2C_MasterWriteBlocking(base, tmpData, tmpDataSize, tmpFlags); + } + else if (0U == (xfer->flags & (uint32_t)kI2C_TransferNoStopFlag)) + { + /* Send stop. */ + result = I2C_MasterStop(base); + } + else + { + /* Add this to fix MISRA C2012 rule15.7 issue: Empty else without comment. */ + } + } + + /* Receive Data. */ + if ((xfer->dataSize > 0u) && (xfer->direction == kI2C_Read)) + { + uint8_t *tmpData = xfer->data; + size_t tmpDataSize = xfer->dataSize; + uint32_t tmpFlags = xfer->flags; + + result = I2C_MasterReadBlocking(base, tmpData, tmpDataSize, tmpFlags); + } + + return result; +} + +/*! + * brief Initializes the I2C handle which is used in transactional functions. + * + * param base I2C base pointer. + * param handle pointer to i2c_master_handle_t structure to store the transfer state. + * param callback pointer to user callback function. + * param userData user parameter passed to the callback function. + */ +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData) +{ + assert(NULL != handle); + + uint32_t instance = I2C_GetInstance(base); + + /* Zero handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Set callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + s_i2cHandle[instance] = handle; + + /* Save master interrupt handler. */ + s_i2cMasterIsr = I2C_MasterTransferHandleIRQ; + + /* Enable NVIC interrupt. */ + (void)EnableIRQ(s_i2cIrqs[instance]); +} + +/*! + * brief Performs a master interrupt non-blocking transfer on the I2C bus. + * + * note Calling the API returns immediately after transfer initiates. The user needs + * to call I2C_MasterGetTransferCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_I2C_Busy, the transfer + * is finished. + * + * param base I2C base pointer. + * param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * param xfer pointer to i2c_master_transfer_t structure. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_I2C_Busy Previous transmission still not finished. + * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + */ +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != xfer); + + status_t result = kStatus_Success; + + /* Check if the I2C bus is idle - if not return busy status. */ + if (handle->state != (uint8_t)kIdleState) + { + result = kStatus_I2C_Busy; + } + else + { + /* Start up the master transfer state machine. */ + result = I2C_InitTransferStateMachine(base, handle, xfer); + + if (result == kStatus_Success) + { + /* Enable the I2C interrupts. */ + I2C_EnableInterrupts(base, (uint32_t)kI2C_GlobalInterruptEnable); + } + } + + return result; +} + +/*! + * brief Aborts an interrupt non-blocking transfer early. + * + * note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base I2C base pointer. + * param handle pointer to i2c_master_handle_t structure which stores the transfer state + * retval kStatus_I2C_Timeout Timeout during polling flag. + * retval kStatus_Success Successfully abort the transfer. + */ +status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) +{ + assert(NULL != handle); + + volatile uint8_t dummy = 0; +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; +#endif + + /* Add this to avoid build warning. */ + dummy++; + + /* Disable interrupt. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_GlobalInterruptEnable); + + /* Reset the state to idle. */ + handle->state = (uint8_t)kIdleState; + + /* If the bus is already in use, but not by us */ + if (0U == (base->C1 & I2C_C1_MST_MASK)) + { + return kStatus_I2C_Busy; + } + + /* Send STOP signal. */ + if (handle->transfer.direction == kI2C_Read) + { + base->C1 |= I2C_C1_TXAK_MASK; + +#if I2C_WAIT_TIMEOUT + /* Wait until data transfer complete. */ + while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else + /* Wait until data transfer complete. */ + while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) + { + } +#endif + base->S = (uint8_t)kI2C_IntPendingFlag; + + base->C1 &= ~(uint8_t)(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + dummy = base->D; + } + else + { +#if I2C_WAIT_TIMEOUT + /* Wait until data transfer complete. */ + while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else + /* Wait until data transfer complete. */ + while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) + { + } +#endif + base->S = (uint8_t)kI2C_IntPendingFlag; + base->C1 &= ~(uint8_t)(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + } + + return kStatus_Success; +} + +/*! + * brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * param base I2C base pointer. + * param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) +{ + assert(NULL != handle); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + *count = handle->transferSize - handle->transfer.dataSize; + + return kStatus_Success; +} + +/*! + * brief Master interrupt handler. + * + * param base I2C base pointer. + * param i2cHandle pointer to i2c_master_handle_t structure. + */ +void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle) +{ + assert(NULL != i2cHandle); + + i2c_master_handle_t *handle = (i2c_master_handle_t *)i2cHandle; + status_t result = kStatus_Success; + bool isDone; + + /* Clear the interrupt flag. */ + base->S = (uint8_t)kI2C_IntPendingFlag; + + /* Check transfer complete flag. */ + result = I2C_MasterTransferRunStateMachine(base, handle, &isDone); + + if ((true == isDone) || (0 != result)) + { + /* Send stop command if transfer done or received Nak. */ + if ((0U == (handle->transfer.flags & (uint32_t)kI2C_TransferNoStopFlag)) || (result == kStatus_I2C_Nak) || + (result == kStatus_I2C_Addr_Nak)) + { + /* Ensure stop command is a need. */ + if (0U != (base->C1 & I2C_C1_MST_MASK)) + { + if (I2C_MasterStop(base) != kStatus_Success) + { + result = kStatus_I2C_Timeout; + } + } + } + + /* Restore handle to idle state. */ + handle->state = (uint8_t)kIdleState; + + /* Disable interrupt. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_GlobalInterruptEnable); + + /* Call the callback function after the function has completed. */ + if (NULL != (handle->completionCallback)) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } +} + +/*! + * brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and initialize the I2C with the slave configuration. + * + * note This API should be called at the beginning of the application. + * Otherwise, any operation to the I2C module can cause a hard fault + * because the clock is not enabled. The configuration structure can partly be set + * with default values by I2C_SlaveGetDefaultConfig() or it can be custom filled by the user. + * This is an example. + * code + * i2c_slave_config_t config = { + * .enableSlave = true, + * .enableGeneralCall = false, + * .addressingMode = kI2C_Address7bit, + * .slaveAddress = 0x1DU, + * .enableWakeUp = false, + * .enablehighDrive = false, + * .enableBaudRateCtl = false, + * .sclStopHoldTime_ns = 4000 + * }; + * I2C_SlaveInit(I2C0, &config, 12000000U); + * endcode + * + * param base I2C base pointer + * param slaveConfig A pointer to the slave configuration structure + * param srcClock_Hz I2C peripheral clock frequency in Hz + */ +void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz) +{ + assert(NULL != slaveConfig); + + uint8_t tmpReg; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset the module. */ + base->A1 = 0; + base->F = 0; + base->C1 = 0; + base->S = 0xFFU; + base->C2 = 0; +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + base->FLT = 0x50U; +#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + base->FLT = 0x40U; +#endif + base->RA = 0; + + /* Configure addressing mode. */ + switch (slaveConfig->addressingMode) + { + case kI2C_Address7bit: + base->A1 = (uint8_t)(((uint32_t)(slaveConfig->slaveAddress)) << 1U); + break; + + case kI2C_RangeMatch: + assert(slaveConfig->slaveAddress < slaveConfig->upperAddress); + base->A1 = (uint8_t)(((uint32_t)(slaveConfig->slaveAddress)) << 1U); + base->RA = (uint8_t)(((uint32_t)(slaveConfig->upperAddress)) << 1U); + base->C2 |= I2C_C2_RMEN_MASK; + break; + + default: + break; + } + + /* Configure low power wake up feature. */ + tmpReg = base->C1; + tmpReg &= ~(uint8_t)I2C_C1_WUEN_MASK; + base->C1 = tmpReg | I2C_C1_WUEN(slaveConfig->enableWakeUp) | I2C_C1_IICEN(slaveConfig->enableSlave); + + /* Configure general call & baud rate control. */ + tmpReg = base->C2; + tmpReg &= ~(uint8_t)(I2C_C2_SBRC_MASK | I2C_C2_GCAEN_MASK); + tmpReg |= I2C_C2_SBRC(slaveConfig->enableBaudRateCtl) | I2C_C2_GCAEN(slaveConfig->enableGeneralCall); + base->C2 = tmpReg; + +/* Enable/Disable double buffering. */ +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE + tmpReg = (uint8_t)(base->S2 & (~I2C_S2_DFEN_MASK)); + base->S2 = tmpReg | I2C_S2_DFEN(slaveConfig->enableDoubleBuffering); +#endif + + /* Set hold time. */ + I2C_SetHoldTime(base, slaveConfig->sclStopHoldTime_ns, srcClock_Hz); +} + +/*! + * brief De-initializes the I2C slave peripheral. Calling this API gates the I2C clock. + * The I2C slave module can't work unless the I2C_SlaveInit is called to enable the clock. + * param base I2C base pointer + */ +void I2C_SlaveDeinit(I2C_Type *base) +{ + /* Disable I2C module. */ + I2C_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable I2C clock. */ + CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Sets the I2C slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the I2C_SlaveConfigure(). + * Modify fields of the structure before calling the I2C_SlaveConfigure(). + * This is an example. + * code + * i2c_slave_config_t config; + * I2C_SlaveGetDefaultConfig(&config); + * endcode + * param slaveConfig A pointer to the slave configuration structure. + */ +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) +{ + assert(NULL != slaveConfig); + + /* Initializes the configure structure to zero. */ + (void)memset(slaveConfig, 0, sizeof(*slaveConfig)); + + /* By default slave is addressed with 7-bit address. */ + slaveConfig->addressingMode = kI2C_Address7bit; + + /* General call mode is disabled by default. */ + slaveConfig->enableGeneralCall = false; + + /* Slave address match waking up MCU from low power mode is disabled. */ + slaveConfig->enableWakeUp = false; + + /* Independent slave mode baud rate at maximum frequency is disabled. */ + slaveConfig->enableBaudRateCtl = false; + +/* Default enable double buffering. */ +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE + slaveConfig->enableDoubleBuffering = true; +#endif + + /* Set default SCL stop hold time to 4us which is minimum requirement in I2C spec. */ + slaveConfig->sclStopHoldTime_ns = 4000; + + /* Enable the I2C peripheral. */ + slaveConfig->enableSlave = true; +} + +/*! + * brief Performs a polling send transaction on the I2C bus. + * + * param base The I2C peripheral base pointer. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * retval kStatus_Success Successfully complete the data transmission. + * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) +{ + status_t result = kStatus_Success; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + /* Check start flag. */ + while (0U == (base->FLT & I2C_FLT_STARTF_MASK)) + { + } + /* Clear STARTF flag. */ + base->FLT |= I2C_FLT_STARTF_MASK; + /* Clear the IICIF flag. */ + base->S = (uint8_t)kI2C_IntPendingFlag; +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ + +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until data transfer complete. */ + while ((!(base->S & kI2C_AddressMatchFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else + /* Wait for address match flag. */ + while (0U == (base->S & (uint8_t)kI2C_AddressMatchFlag)) + { + } +#endif + /* Read dummy to release bus. */ + dummy = base->D; + + result = I2C_MasterWriteBlocking(base, txBuff, txSize, (uint32_t)kI2C_TransferNoStopFlag); + + /* Switch to receive mode. */ + base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Read dummy to release bus. */ + dummy = base->D; + + return result; +} + +/*! + * brief Performs a polling receive transaction on the I2C bus. + * + * param base I2C peripheral base pointer. + * param rxBuff The pointer to the data to store the received data. + * param rxSize The length in bytes of the data to be received. + * retval kStatus_Success Successfully complete data receive. + * retval kStatus_I2C_Timeout Wait status flag timeout. + */ +status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) +{ + status_t result = kStatus_Success; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + +/* Wait until address match. */ +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + /* Check start flag. */ + while (0U == (base->FLT & I2C_FLT_STARTF_MASK)) + { + } + /* Clear STARTF flag. */ + base->FLT |= I2C_FLT_STARTF_MASK; + /* Clear the IICIF flag. */ + base->S = (uint8_t)kI2C_IntPendingFlag; +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ + +#if I2C_WAIT_TIMEOUT + uint32_t waitTimes = I2C_WAIT_TIMEOUT; + /* Wait for address match and int pending flag. */ + while ((!(base->S & kI2C_AddressMatchFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } + + waitTimes = I2C_WAIT_TIMEOUT; + while ((!(base->S & kI2C_IntPendingFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else + /* Wait for address match and int pending flag. */ + while (0U == (base->S & (uint8_t)kI2C_AddressMatchFlag)) + { + } + while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) + { + } +#endif + + /* Read dummy to release bus. */ + dummy = base->D; + + /* Clear the IICIF flag. */ + base->S = (uint8_t)kI2C_IntPendingFlag; + + /* Setup the I2C peripheral to receive data. */ + base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK); + + while (0U != (rxSize--)) + { +#if I2C_WAIT_TIMEOUT + waitTimes = I2C_WAIT_TIMEOUT; + /* Wait until data transfer complete. */ + while ((0U == (base->S & kI2C_IntPendingFlag)) && (--waitTimes)) + { + } + if (waitTimes == 0) + { + return kStatus_I2C_Timeout; + } +#else + /* Wait until data transfer complete. */ + while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) + { + } +#endif + /* Clear the IICIF flag. */ + base->S = (uint8_t)kI2C_IntPendingFlag; + + /* Read from the data register. */ + *rxBuff++ = base->D; + } + + return result; +} + +/*! + * brief Initializes the I2C handle which is used in transactional functions. + * + * param base I2C base pointer. + * param handle pointer to i2c_slave_handle_t structure to store the transfer state. + * param callback pointer to user callback function. + * param userData user parameter passed to the callback function. + */ +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData) +{ + assert(NULL != handle); + + uint32_t instance = I2C_GetInstance(base); + + /* Zero handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Set callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + s_i2cHandle[instance] = handle; + + /* Save slave interrupt handler. */ + s_i2cSlaveIsr = I2C_SlaveTransferHandleIRQ; + + /* Enable NVIC interrupt. */ + (void)EnableIRQ(s_i2cIrqs[instance]); +} + +/*! + * brief Starts accepting slave transfers. + * + * Call this API after calling the I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and passes events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The I2C peripheral base address. + * param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. + * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * retval #kStatus_Success Slave transfers were successfully started. + * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) +{ + assert(NULL != handle); + + /* Check if the I2C bus is idle - if not return busy status. */ + if (true == handle->isBusy) + { + return kStatus_I2C_Busy; + } + else + { + /* Disable LPI2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, (uint32_t)kIrqFlags); + + /* Clear transfer in handle. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Record that we're busy. */ + handle->isBusy = true; + + /* Set up event mask. tx and rx are always enabled. */ + handle->eventMask = eventMask | (uint32_t)kI2C_SlaveTransmitEvent | (uint32_t)kI2C_SlaveReceiveEvent | + (uint32_t)kI2C_SlaveGenaralcallEvent; + + /* Clear all flags. */ + I2C_SlaveClearStatusFlags(base, (uint32_t)kClearFlags); + + /* Enable I2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + I2C_EnableInterrupts(base, (uint32_t)kIrqFlags); + } + + return kStatus_Success; +} + +/*! + * brief Aborts the slave transfer. + * + * note This API can be called at any time to stop slave for handling the bus events. + * + * param base I2C base pointer. + * param handle pointer to i2c_slave_handle_t structure which stores the transfer state. + */ +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) +{ + assert(NULL != handle); + + if (true == handle->isBusy) + { + /* Disable interrupts. */ + I2C_DisableInterrupts(base, (uint32_t)kIrqFlags); + + /* Reset transfer info. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Reset the state to idle. */ + handle->isBusy = false; + } +} + +/*! + * brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. + * + * param base I2C base pointer. + * param handle pointer to i2c_slave_handle_t structure. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) +{ + assert(NULL != handle); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (false == handle->isBusy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + *count = handle->transfer.transferredCount; + + return kStatus_Success; +} + +/*! + * brief Slave interrupt handler. + * + * param base I2C base pointer. + * param i2cHandle pointer to i2c_slave_handle_t structure which stores the transfer state + */ +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle) +{ + assert(NULL != i2cHandle); + + uint16_t status; + bool doTransmit = false; + i2c_slave_handle_t *handle = (i2c_slave_handle_t *)i2cHandle; + i2c_slave_transfer_t *xfer; + volatile uint8_t dummy = 0; + size_t tmpDataSize = 0; + + /* Add this to avoid build warning. */ + dummy++; + + status = (uint16_t)I2C_SlaveGetStatusFlags(base); + xfer = &(handle->transfer); + +#ifdef I2C_HAS_STOP_DETECT + /* Check stop flag. */ + if (0U != (status & (uint16_t)kI2C_StopDetectFlag)) + { + I2C_MasterClearStatusFlags(base, (uint32_t)kI2C_StopDetectFlag); + + /* Clear the interrupt flag. */ + base->S = (uint8_t)kI2C_IntPendingFlag; + + /* Call slave callback if this is the STOP of the transfer. */ + if (true == handle->isBusy) + { + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + if ((0U != (handle->eventMask & (uint32_t)xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + + if (0U == (status & (uint16_t)kI2C_AddressMatchFlag)) + { + return; + } + } +#endif /* I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + /* Check start flag. */ + if (0U != (status & (uint16_t)kI2C_StartDetectFlag)) + { + I2C_MasterClearStatusFlags(base, (uint32_t)kI2C_StartDetectFlag); + + /* Clear the interrupt flag. */ + base->S = (uint8_t)kI2C_IntPendingFlag; + + xfer->event = kI2C_SlaveStartEvent; + + if ((0U != (handle->eventMask & (uint32_t)xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + + if (0U == (status & (uint16_t)kI2C_AddressMatchFlag)) + { + return; + } + } +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ + + /* Clear the interrupt flag. */ + base->S = (uint8_t)kI2C_IntPendingFlag; + + /* Check NAK */ + if (0U != (status & (uint16_t)kI2C_ReceiveNakFlag)) + { + /* Set receive mode. */ + base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Read dummy. */ + dummy = base->D; + + if (handle->transfer.dataSize != 0u) + { + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_I2C_Nak; + handle->isBusy = false; + + if ((0U != (handle->eventMask & (uint32_t)xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + else + { +#ifndef I2C_HAS_STOP_DETECT + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + if ((0U != (handle->eventMask & (uint32_t)xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } +#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */ + } + } + /* Check address match. */ + else if (0U != (status & (uint16_t)kI2C_AddressMatchFlag)) + { + handle->isBusy = true; + xfer->event = kI2C_SlaveAddressMatchEvent; + + /* Slave transmit, master reading from slave. */ + if (0U != (status & (uint16_t)kI2C_TransferDirectionFlag)) + { + /* Change direction to send data. */ + base->C1 |= I2C_C1_TX_MASK; + + doTransmit = true; + } + else + { + /* Slave receive, master writing to slave. */ + base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Read dummy to release the bus. */ + dummy = base->D; + + if (dummy == 0u) + { + xfer->event = kI2C_SlaveGenaralcallEvent; + } + } + + if ((0U != (handle->eventMask & (uint32_t)xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + /* Check transfer complete flag. */ + else if (0U != (status & (uint16_t)kI2C_TransferCompleteFlag)) + { + /* Slave transmit, master reading from slave. */ + if (0U != (status & (uint16_t)kI2C_TransferDirectionFlag)) + { + doTransmit = true; + } + else + { + tmpDataSize = xfer->dataSize; + /* If we're out of data, invoke callback to get more. */ + if ((NULL == xfer->data) || (0U == tmpDataSize)) + { + xfer->event = kI2C_SlaveReceiveEvent; + + if (NULL != handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + xfer->transferredCount = 0; + } + + /* Slave receive, master writing to slave. */ + uint8_t data = base->D; + + if (0U != (handle->transfer.dataSize)) + { + /* Receive data. */ + *handle->transfer.data++ = data; + handle->transfer.dataSize--; + xfer->transferredCount++; + if (0U == handle->transfer.dataSize) + { +#ifndef I2C_HAS_STOP_DETECT + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + /* Proceed receive complete event. */ + if ((handle->eventMask & (uint32_t)xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } +#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */ + } + } + } + } + else + { + /* Read dummy to release bus. */ + dummy = base->D; + } + + /* Send data if there is the need. */ + if (doTransmit) + { + tmpDataSize = xfer->dataSize; + /* If we're out of data, invoke callback to get more. */ + if ((NULL == xfer->data) || (0U == tmpDataSize)) + { + xfer->event = kI2C_SlaveTransmitEvent; + + if (NULL != handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + xfer->transferredCount = 0; + } + + if (0U != (handle->transfer.dataSize)) + { + /* Send data. */ + base->D = *handle->transfer.data++; + handle->transfer.dataSize--; + xfer->transferredCount++; + } + else + { + /* Switch to receive mode. */ + base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Read dummy to release bus. */ + dummy = base->D; + +#ifndef I2C_HAS_STOP_DETECT + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + /* Proceed txdone event. */ + if ((handle->eventMask & (uint32_t)xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } +#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */ + } + } +} + +#if defined(I2C0) +void I2C0_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C0, s_i2cHandle[0]); +} +#endif + +#if defined(I2C1) +void I2C1_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C1, s_i2cHandle[1]); +} +#endif + +#if defined(I2C2) +void I2C2_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C2, s_i2cHandle[2]); +} +#endif + +#if defined(I2C3) +void I2C3_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C3, s_i2cHandle[3]); +} +#endif diff --git a/source/hic_hal/freescale/kl27z/fsl_i2c.h b/source/hic_hal/freescale/kl27z/fsl_i2c.h new file mode 100644 index 000000000..f67c977bc --- /dev/null +++ b/source/hic_hal/freescale/kl27z/fsl_i2c.h @@ -0,0 +1,795 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_I2C_H_ +#define _FSL_I2C_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup i2c_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2C driver version 2.0.7. */ +#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 7)) +/*@}*/ + +/*! @brief Timeout times for waiting flag. */ +#ifndef I2C_WAIT_TIMEOUT +#define I2C_WAIT_TIMEOUT 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/*! @brief Mater Fast ack control, control if master needs to manually write ack, this is used to +low the speed of transfer for SoCs with feature FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */ +#ifndef I2C_MASTER_FACK_CONTROL +#define I2C_MASTER_FACK_CONTROL 0U /* Default defines to zero means master will send ack automatically. */ +#endif + +#if (defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT || \ + defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT) +#define I2C_HAS_STOP_DETECT +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT / FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +/*! @brief I2C status return codes. */ +enum _i2c_status +{ + kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_I2C, 0), /*!< I2C is busy with current transfer. */ + kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_I2C, 1), /*!< Bus is Idle. */ + kStatus_I2C_Nak = MAKE_STATUS(kStatusGroup_I2C, 2), /*!< NAK received during transfer. */ + kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_I2C, 3), /*!< Arbitration lost during transfer. */ + kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_I2C, 4), /*!< Timeout poling status flags. */ + kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_I2C, 5), /*!< NAK received during the address probe. */ +}; + +/*! + * @brief I2C peripheral flags + * + * The following status register flags can be cleared: + * - #kI2C_ArbitrationLostFlag + * - #kI2C_IntPendingFlag + * - #kI2C_StartDetectFlag + * - #kI2C_StopDetectFlag + * + * @note These enumerations are meant to be OR'd together to form a bit mask. + * + */ +enum _i2c_flags +{ + kI2C_ReceiveNakFlag = I2C_S_RXAK_MASK, /*!< I2C receive NAK flag. */ + kI2C_IntPendingFlag = I2C_S_IICIF_MASK, /*!< I2C interrupt pending flag. */ + kI2C_TransferDirectionFlag = I2C_S_SRW_MASK, /*!< I2C transfer direction flag. */ + kI2C_RangeAddressMatchFlag = I2C_S_RAM_MASK, /*!< I2C range address match flag. */ + kI2C_ArbitrationLostFlag = I2C_S_ARBL_MASK, /*!< I2C arbitration lost flag. */ + kI2C_BusBusyFlag = I2C_S_BUSY_MASK, /*!< I2C bus busy flag. */ + kI2C_AddressMatchFlag = I2C_S_IAAS_MASK, /*!< I2C address match flag. */ + kI2C_TransferCompleteFlag = I2C_S_TCF_MASK, /*!< I2C transfer complete flag. */ +#ifdef I2C_HAS_STOP_DETECT + kI2C_StopDetectFlag = I2C_FLT_STOPF_MASK << 8, /*!< I2C stop detect flag. */ +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT / FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kI2C_StartDetectFlag = I2C_FLT_STARTF_MASK << 8, /*!< I2C start detect flag. */ +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +}; + +/*! @brief I2C feature interrupt source. */ +enum _i2c_interrupt_enable +{ + kI2C_GlobalInterruptEnable = I2C_C1_IICIE_MASK, /*!< I2C global interrupt. */ + +#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + kI2C_StopDetectInterruptEnable = I2C_FLT_STOPIE_MASK, /*!< I2C stop detect interrupt. */ +#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kI2C_StartStopDetectInterruptEnable = I2C_FLT_SSIE_MASK, /*!< I2C start&stop detect interrupt. */ +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +}; + +/*! @brief The direction of master and slave transfers. */ +typedef enum _i2c_direction +{ + kI2C_Write = 0x0U, /*!< Master transmits to the slave. */ + kI2C_Read = 0x1U, /*!< Master receives from the slave. */ +} i2c_direction_t; + +/*! @brief Addressing mode. */ +typedef enum _i2c_slave_address_mode +{ + kI2C_Address7bit = 0x0U, /*!< 7-bit addressing mode. */ + kI2C_RangeMatch = 0X2U, /*!< Range address match addressing mode. */ +} i2c_slave_address_mode_t; + +/*! @brief I2C transfer control flag. */ +enum _i2c_master_transfer_flags +{ + kI2C_TransferDefaultFlag = 0x0U, /*!< A transfer starts with a start signal, stops with a stop signal. */ + kI2C_TransferNoStartFlag = 0x1U, /*!< A transfer starts without a start signal, only support write only or + write+read with no start flag, do not support read only with no start flag. */ + kI2C_TransferRepeatedStartFlag = 0x2U, /*!< A transfer starts with a repeated start signal. */ + kI2C_TransferNoStopFlag = 0x4U, /*!< A transfer ends without a stop signal. */ +}; + +/*! + * @brief Set of events sent to the callback for nonblocking slave transfers. + * + * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together + * events is passed to I2C_SlaveTransferNonBlocking() to specify which events to enable. + * Then, when the slave callback is invoked, it is passed the current event through its @a transfer + * parameter. + * + * @note These enumerations are meant to be OR'd together to form a bit mask of events. + */ +typedef enum _i2c_slave_transfer_event +{ + kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ + kI2C_SlaveTransmitEvent = 0x02U, /*!< A callback is requested to provide data to transmit + (slave-transmitter role). */ + kI2C_SlaveReceiveEvent = 0x04U, /*!< A callback is requested to provide a buffer in which to place received + data (slave-receiver role). */ + kI2C_SlaveTransmitAckEvent = 0x08U, /*!< A callback needs to either transmit an ACK or NACK. */ +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kI2C_SlaveStartEvent = 0x10U, /*!< A start/repeated start was detected. */ +#endif + kI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected or finished transfer, completing the transfer. */ + kI2C_SlaveGenaralcallEvent = 0x40U, /*!< Received the general call address after a start or repeated start. */ + + /*! A bit mask of all available events. */ + kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kI2C_SlaveStartEvent | +#endif + kI2C_SlaveCompletionEvent | kI2C_SlaveGenaralcallEvent, +} i2c_slave_transfer_event_t; + +/*! @brief I2C master user configuration. */ +typedef struct _i2c_master_config +{ + bool enableMaster; /*!< Enables the I2C peripheral at initialization time. */ +#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF + bool enableStopHold; /*!< Controls the stop hold enable. */ +#endif +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE + bool enableDoubleBuffering; /*!< Controls double buffer enable; notice that + enabling the double buffer disables the clock stretch. */ +#endif + uint32_t baudRate_Bps; /*!< Baud rate configuration of I2C peripheral. */ + uint8_t glitchFilterWidth; /*!< Controls the width of the glitch. */ +} i2c_master_config_t; + +/*! @brief I2C slave user configuration. */ +typedef struct _i2c_slave_config +{ + bool enableSlave; /*!< Enables the I2C peripheral at initialization time. */ + bool enableGeneralCall; /*!< Enables the general call addressing mode. */ + bool enableWakeUp; /*!< Enables/disables waking up MCU from low-power mode. */ +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE + bool enableDoubleBuffering; /*!< Controls a double buffer enable; notice that + enabling the double buffer disables the clock stretch. */ +#endif + bool enableBaudRateCtl; /*!< Enables/disables independent slave baud rate on SCL in very fast I2C modes. */ + uint16_t slaveAddress; /*!< A slave address configuration. */ + uint16_t upperAddress; /*!< A maximum boundary slave address used in a range matching mode. */ + i2c_slave_address_mode_t + addressingMode; /*!< An addressing mode configuration of i2c_slave_address_mode_config_t. */ + uint32_t sclStopHoldTime_ns; /*!< the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C + data) while SCL is high (stop condition), SDA hold time and SCL start hold time + are also configured according to the SCL stop hold time. */ +} i2c_slave_config_t; + +/*! @brief I2C master handle typedef. */ +typedef struct _i2c_master_handle i2c_master_handle_t; + +/*! @brief I2C master transfer callback typedef. */ +typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, + i2c_master_handle_t *handle, + status_t status, + void *userData); + +/*! @brief I2C slave handle typedef. */ +typedef struct _i2c_slave_handle i2c_slave_handle_t; + +/*! @brief I2C master transfer structure. */ +typedef struct _i2c_master_transfer +{ + uint32_t flags; /*!< A transfer flag which controls the transfer. */ + uint8_t slaveAddress; /*!< 7-bit slave address. */ + i2c_direction_t direction; /*!< A transfer direction, read or write. */ + uint32_t subaddress; /*!< A sub address. Transferred MSB first. */ + uint8_t subaddressSize; /*!< A size of the command buffer. */ + uint8_t *volatile data; /*!< A transfer buffer. */ + volatile size_t dataSize; /*!< A transfer size. */ +} i2c_master_transfer_t; + +/*! @brief I2C master handle structure. */ +struct _i2c_master_handle +{ + i2c_master_transfer_t transfer; /*!< I2C master transfer copy. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + uint8_t state; /*!< A transfer state maintained during transfer. */ + i2c_master_transfer_callback_t completionCallback; /*!< A callback function called when the transfer is finished. */ + void *userData; /*!< A callback parameter passed to the callback function. */ +}; + +/*! @brief I2C slave transfer structure. */ +typedef struct _i2c_slave_transfer +{ + i2c_slave_transfer_event_t event; /*!< A reason that the callback is invoked. */ + uint8_t *volatile data; /*!< A transfer buffer. */ + volatile size_t dataSize; /*!< A transfer size. */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kI2C_SlaveCompletionEvent. */ + size_t transferredCount; /*!< A number of bytes actually transferred since the start or since the last repeated + start. */ +} i2c_slave_transfer_t; + +/*! @brief I2C slave transfer callback typedef. */ +typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData); + +/*! @brief I2C slave handle structure. */ +struct _i2c_slave_handle +{ + volatile bool isBusy; /*!< Indicates whether a transfer is busy. */ + i2c_slave_transfer_t transfer; /*!< I2C slave transfer copy. */ + uint32_t eventMask; /*!< A mask of enabled events. */ + i2c_slave_transfer_callback_t callback; /*!< A callback function called at the transfer event. */ + void *userData; /*!< A callback parameter passed to the callback. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and configure the I2C with master configuration. + * + * @note This API should be called at the beginning of the application. + * Otherwise, any operation to the I2C module can cause a hard fault + * because the clock is not enabled. The configuration structure can be custom filled + * or it can be set with default values by using the I2C_MasterGetDefaultConfig(). + * After calling this API, the master is ready to transfer. + * This is an example. + * @code + * i2c_master_config_t config = { + * .enableMaster = true, + * .enableStopHold = false, + * .highDrive = false, + * .baudRate_Bps = 100000, + * .glitchFilterWidth = 0 + * }; + * I2C_MasterInit(I2C0, &config, 12000000U); + * @endcode + * + * @param base I2C base pointer + * @param masterConfig A pointer to the master configuration structure + * @param srcClock_Hz I2C peripheral clock frequency in Hz + */ +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and initialize the I2C with the slave configuration. + * + * @note This API should be called at the beginning of the application. + * Otherwise, any operation to the I2C module can cause a hard fault + * because the clock is not enabled. The configuration structure can partly be set + * with default values by I2C_SlaveGetDefaultConfig() or it can be custom filled by the user. + * This is an example. + * @code + * i2c_slave_config_t config = { + * .enableSlave = true, + * .enableGeneralCall = false, + * .addressingMode = kI2C_Address7bit, + * .slaveAddress = 0x1DU, + * .enableWakeUp = false, + * .enablehighDrive = false, + * .enableBaudRateCtl = false, + * .sclStopHoldTime_ns = 4000 + * }; + * I2C_SlaveInit(I2C0, &config, 12000000U); + * @endcode + * + * @param base I2C base pointer + * @param slaveConfig A pointer to the slave configuration structure + * @param srcClock_Hz I2C peripheral clock frequency in Hz + */ +void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz); + +/*! + * @brief De-initializes the I2C master peripheral. Call this API to gate the I2C clock. + * The I2C master module can't work unless the I2C_MasterInit is called. + * @param base I2C base pointer + */ +void I2C_MasterDeinit(I2C_Type *base); + +/*! + * @brief De-initializes the I2C slave peripheral. Calling this API gates the I2C clock. + * The I2C slave module can't work unless the I2C_SlaveInit is called to enable the clock. + * @param base I2C base pointer + */ +void I2C_SlaveDeinit(I2C_Type *base); + +/*! + * @brief Get instance number for I2C module. + * + * @param base I2C peripheral base address. + */ +uint32_t I2C_GetInstance(I2C_Type *base); + +/*! + * @brief Sets the I2C master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterConfigure(). + * Use the initialized structure unchanged in the I2C_MasterConfigure() or modify + * the structure before calling the I2C_MasterConfigure(). + * This is an example. + * @code + * i2c_master_config_t config; + * I2C_MasterGetDefaultConfig(&config); + * @endcode + * @param masterConfig A pointer to the master configuration structure. + */ +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); + +/*! + * @brief Sets the I2C slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the I2C_SlaveConfigure(). + * Modify fields of the structure before calling the I2C_SlaveConfigure(). + * This is an example. + * @code + * i2c_slave_config_t config; + * I2C_SlaveGetDefaultConfig(&config); + * @endcode + * @param slaveConfig A pointer to the slave configuration structure. + */ +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); + +/*! + * @brief Enables or disables the I2C peripheral operation. + * + * @param base I2C base pointer + * @param enable Pass true to enable and false to disable the module. + */ +static inline void I2C_Enable(I2C_Type *base, bool enable) +{ + if (enable) + { + base->C1 |= I2C_C1_IICEN_MASK; + } + else + { + base->C1 &= ~(uint8_t)I2C_C1_IICEN_MASK; + } +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the I2C status flags. + * + * @param base I2C base pointer + * @return status flag, use status flag to AND #_i2c_flags to get the related status. + */ +uint32_t I2C_MasterGetStatusFlags(I2C_Type *base); + +/*! + * @brief Gets the I2C status flags. + * + * @param base I2C base pointer + * @return status flag, use status flag to AND #_i2c_flags to get the related status. + */ +static inline uint32_t I2C_SlaveGetStatusFlags(I2C_Type *base) +{ + return I2C_MasterGetStatusFlags(base); +} + +/*! + * @brief Clears the I2C status flag state. + * + * The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag. + * + * @param base I2C base pointer + * @param statusMask The status flag mask, defined in type i2c_status_flag_t. + * The parameter can be any combination of the following values: + * @arg kI2C_StartDetectFlag (if available) + * @arg kI2C_StopDetectFlag (if available) + * @arg kI2C_ArbitrationLostFlag + * @arg kI2C_IntPendingFlagFlag + */ +static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ +/* Must clear the STARTF / STOPF bits prior to clearing IICIF */ +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + if ((uint32_t)kI2C_StartDetectFlag == (statusMask & (uint32_t)kI2C_StartDetectFlag)) + { + /* Shift the odd-ball flags back into place. */ + base->FLT |= (uint8_t)(statusMask >> 8U); + } +#endif + +#ifdef I2C_HAS_STOP_DETECT + if ((uint32_t)kI2C_StopDetectFlag == (statusMask & (uint32_t)kI2C_StopDetectFlag)) + { + /* Shift the odd-ball flags back into place. */ + base->FLT |= (uint8_t)(statusMask >> 8U); + } +#endif + + base->S = (uint8_t)statusMask; +} + +/*! + * @brief Clears the I2C status flag state. + * + * The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag + * + * @param base I2C base pointer + * @param statusMask The status flag mask, defined in type i2c_status_flag_t. + * The parameter can be any combination of the following values: + * @arg kI2C_StartDetectFlag (if available) + * @arg kI2C_StopDetectFlag (if available) + * @arg kI2C_ArbitrationLostFlag + * @arg kI2C_IntPendingFlagFlag + */ +static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + I2C_MasterClearStatusFlags(base, statusMask); +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables I2C interrupt requests. + * + * @param base I2C base pointer + * @param mask interrupt source + * The parameter can be combination of the following source if defined: + * @arg kI2C_GlobalInterruptEnable + * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * @arg kI2C_SdaTimeoutInterruptEnable + */ +void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask); + +/*! + * @brief Disables I2C interrupt requests. + * + * @param base I2C base pointer + * @param mask interrupt source + * The parameter can be combination of the following source if defined: + * @arg kI2C_GlobalInterruptEnable + * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * @arg kI2C_SdaTimeoutInterruptEnable + */ +void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask); + +/*! + * @name DMA Control + * @{ + */ +#if defined(FSL_FEATURE_I2C_HAS_DMA_SUPPORT) && FSL_FEATURE_I2C_HAS_DMA_SUPPORT +/*! + * @brief Enables/disables the I2C DMA interrupt. + * + * @param base I2C base pointer + * @param enable true to enable, false to disable + */ +static inline void I2C_EnableDMA(I2C_Type *base, bool enable) +{ + if (enable) + { + base->C1 |= I2C_C1_DMAEN_MASK; + } + else + { + base->C1 &= ~(uint8_t)I2C_C1_DMAEN_MASK; + } +} + +#endif /* FSL_FEATURE_I2C_HAS_DMA_SUPPORT */ + +/*! + * @brief Gets the I2C tx/rx data register address. This API is used to provide a transfer address + * for I2C DMA transfer configuration. + * + * @param base I2C base pointer + * @return data register address + */ +static inline uint32_t I2C_GetDataRegAddr(I2C_Type *base) +{ + return (uint32_t)(&(base->D)); +} + +/* @} */ +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Sets the I2C master transfer baud rate. + * + * @param base I2C base pointer + * @param baudRate_Bps the baud rate value in bps + * @param srcClock_Hz Source clock + */ +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Sends a START on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. + * The slave address is sent following the I2C START signal. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy. + */ +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); + +/*! + * @brief Sends a STOP signal on the I2C bus. + * + * @retval kStatus_Success Successfully send the stop signal. + * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterStop(I2C_Type *base); + +/*! + * @brief Sends a REPEATED START on the I2C bus. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. + */ +status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); + +/*! + * @brief Performs a polling send transaction on the I2C bus. + * + * @param base The I2C peripheral base pointer. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag + * to issue a stop and kI2C_TransferNoStop to not send a stop. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags); + +/*! + * @brief Performs a polling receive transaction on the I2C bus. + * + * @note The I2C_MasterReadBlocking function stops the bus before reading the final byte. + * Without stopping the bus prior for the final read, the bus issues another read, resulting + * in garbage data being read into the data register. + * + * @param base I2C peripheral base pointer. + * @param rxBuff The pointer to the data to store the received data. + * @param rxSize The length in bytes of the data to be received. + * @param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag + * to issue a stop and kI2C_TransferNoStop to not send a stop. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags); + +/*! + * @brief Performs a polling send transaction on the I2C bus. + * + * @param base The I2C peripheral base pointer. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transaction on the I2C bus. + * + * @param base I2C peripheral base pointer. + * @param rxBuff The pointer to the data to store the received data. + * @param rxSize The length in bytes of the data to be received. + * @retval kStatus_Success Successfully complete data receive. + * @retval kStatus_I2C_Timeout Wait status flag timeout. + */ +status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to arbitration lost or receiving a NAK. + * + * @param base I2C peripheral base address. + * @param xfer Pointer to the transfer structure. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the I2C handle which is used in transactional functions. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure to store the transfer state. + * @param callback pointer to user callback function. + * @param userData user parameter passed to the callback function. + */ +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a master interrupt non-blocking transfer on the I2C bus. + * + * @note Calling the API returns immediately after transfer initiates. The user needs + * to call I2C_MasterGetTransferCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_I2C_Busy, the transfer + * is finished. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param xfer pointer to i2c_master_transfer_t structure. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + */ +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Aborts an interrupt non-blocking transfer early. + * + * @note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + * @retval kStatus_I2C_Timeout Timeout during polling flag. + * @retval kStatus_Success Successfully abort the transfer. + */ +status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); + +/*! + * @brief Master interrupt handler. + * + * @param base I2C base pointer. + * @param i2cHandle pointer to i2c_master_handle_t structure. + */ +void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle); + +/*! + * @brief Initializes the I2C handle which is used in transactional functions. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure to store the transfer state. + * @param callback pointer to user callback function. + * @param userData user parameter passed to the callback function. + */ +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling the I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and passes events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval #kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Aborts the slave transfer. + * + * @note This API can be called at any time to stop slave for handling the bus events. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure which stores the transfer state. + */ +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); + +/*! + * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); + +/*! + * @brief Slave interrupt handler. + * + * @param base I2C base pointer. + * @param i2cHandle pointer to i2c_slave_handle_t structure which stores the transfer state + */ +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle); + +/* @} */ +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ +/*@}*/ + +#endif /* _FSL_I2C_H_*/ diff --git a/source/hic_hal/freescale/kl27z/fsl_llwu.c b/source/hic_hal/freescale/kl27z/fsl_llwu.c new file mode 100644 index 000000000..4436c6dd2 --- /dev/null +++ b/source/hic_hal/freescale/kl27z/fsl_llwu.c @@ -0,0 +1,453 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_llwu.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.llwu" +#endif + +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) +/*! + * brief Sets the external input pin source mode. + * + * This function sets the external input pin source mode that is used + * as a wake up source. + * + * param base LLWU peripheral base address. + * param pinIndex A pin index to be enabled as an external wakeup source starting from 1. + * param pinMode A pin configuration mode defined in the llwu_external_pin_modes_t. + */ +void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + volatile uint32_t *regBase; + uint32_t regOffset; + uint32_t reg; + + switch (pinIndex >> 4U) + { + case 0U: + regBase = &base->PE1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 1U: + regBase = &base->PE2; + break; +#endif + default: + regBase = NULL; + break; + } +#else + volatile uint8_t *regBase; + uint8_t regOffset; + uint8_t reg; + switch (pinIndex >> 2U) + { + case 0U: + regBase = &base->PE1; + break; + case 1U: + regBase = &base->PE2; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 2U: + regBase = &base->PE3; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 12)) + case 3U: + regBase = &base->PE4; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 4U: + regBase = &base->PE5; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 20)) + case 5U: + regBase = &base->PE6; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 6U: + regBase = &base->PE7; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 28)) + case 7U: + regBase = &base->PE8; + break; +#endif + default: + regBase = NULL; + break; + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH == 32 */ + + if (NULL != regBase) + { + reg = *regBase; +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + regOffset = ((pinIndex & 0x0FU) << 1U); +#else + regOffset = (uint8_t)((pinIndex & 0x03U) << 1U); +#endif + reg &= ~(0x3U << regOffset); + reg |= (uint8_t)((uint32_t)pinMode << regOffset); + *regBase = reg; + } +} + +/*! + * brief Gets the external wakeup source flag. + * + * This function checks the external pin flag to detect whether the MCU is + * woken up by the specific pin. + * + * param base LLWU peripheral base address. + * param pinIndex A pin index, which starts from 1. + * return True if the specific pin is a wakeup source. + */ +bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + return (bool)(base->PF & (1U << pinIndex)); +#else + volatile uint8_t *regBase; + + switch (pinIndex >> 3U) + { +#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) + case 0U: + regBase = &base->PF1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 1U: + regBase = &base->PF2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 2U: + regBase = &base->PF3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 3U: + regBase = &base->PF4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#else + case 0U: + regBase = &base->F1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 1U: + regBase = &base->F2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 2U: + regBase = &base->F3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 3U: + regBase = &base->F4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#endif /* FSL_FEATURE_LLWU_HAS_PF */ + default: + regBase = NULL; + break; + } + + if (NULL != regBase) + { + if (0U != (*regBase & (1U << pinIndex % 8U))) + { + return true; + } + else + { + return false; + } + } + else + { + return false; + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} + +/*! + * brief Clears the external wakeup source flag. + * + * This function clears the external wakeup source flag for a specific pin. + * + * param base LLWU peripheral base address. + * param pinIndex A pin index, which starts from 1. + */ +void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + base->PF = (1U << pinIndex); +#else + volatile uint8_t *regBase; + switch (pinIndex >> 3U) + { +#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) + case 0U: + regBase = &base->PF1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 1U: + regBase = &base->PF2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 2U: + regBase = &base->PF3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 3U: + regBase = &base->PF4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#else + case 0U: + regBase = &base->F1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 1U: + regBase = &base->F2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 2U: + regBase = &base->F3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 3U: + regBase = &base->F4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#endif /* FSL_FEATURE_LLWU_HAS_PF */ + default: + regBase = NULL; + break; + } + if (NULL != regBase) + { + *regBase = (1U << pinIndex % 8U); + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) +/*! + * brief Sets the pin filter configuration. + * + * This function sets the pin filter configuration. + * + * param base LLWU peripheral base address. + * param filterIndex A pin filter index used to enable/disable the digital filter, starting from 1. + * param filterMode A filter mode configuration + */ +void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + base->FILT = ((base->FILT) & ~((LLWU_FILT_FILTSEL1_MASK | LLWU_FILT_FILTE1_MASK) << ((filterIndex - 1U) * 8U))) | + ((LLWU_FILT_FILTSEL1(filterMode.pinIndex) | LLWU_FILT_FILTE1(filterMode.filterMode)) + << ((filterIndex - 1U) * 8U)) | + LLWU_FILT_FILTF1_MASK /* W1C to clear the FILTF flag bit. */ + ; +#else + volatile uint8_t *regBase; + + switch (filterIndex) + { + case 1U: + regBase = &base->FILT1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) + case 2U: + regBase = &base->FILT2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) + case 3U: + regBase = &base->FILT3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) + case 4U: + regBase = &base->FILT4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + default: + regBase = NULL; + break; + } + + if (NULL != regBase) + { + *regBase = (uint8_t)((*regBase & ~(LLWU_FILT1_FILTSEL_MASK | LLWU_FILT1_FILTE_MASK)) | + LLWU_FILT1_FILTSEL(filterMode.pinIndex) | LLWU_FILT1_FILTE(filterMode.filterMode) | + LLWU_FILT1_FILTF_MASK) /* W1C to clear the FILTF flag bit. */ + ; + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} + +/*! + * brief Gets the pin filter configuration. + * + * This function gets the pin filter flag. + * + * param base LLWU peripheral base address. + * param filterIndex A pin filter index, which starts from 1. + * return True if the flag is a source of the existing low-leakage power mode. + */ +bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + return (bool)(base->FILT & (1U << (filterIndex * 8U - 1))); +#else + bool status = false; + + switch (filterIndex) + { + case 1: + status = ((base->FILT1 & LLWU_FILT1_FILTF_MASK) != 0U); + break; +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) + case 2: + status = ((base->FILT2 & LLWU_FILT2_FILTF_MASK) != 0U); + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) + case 3: + status = (base->FILT3 & LLWU_FILT3_FILTF_MASK); + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) + case 4: + status = (base->FILT4 & LLWU_FILT4_FILTF_MASK); + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + default: + break; + } + + return status; +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} + +/*! + * brief Clears the pin filter configuration. + * + * This function clears the pin filter flag. + * + * param base LLWU peripheral base address. + * param filterIndex A pin filter index to clear the flag, starting from 1. + */ +void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + uint32_t reg; + + reg = base->FILT; + switch (filterIndex) + { + case 1: + reg |= LLWU_FILT_FILTF1_MASK; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) + case 2: + reg |= LLWU_FILT_FILTF2_MASK; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1 */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) + case 3: + reg |= LLWU_FILT_FILTF3_MASK; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2 */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) + case 4: + reg |= LLWU_FILT_FILTF4_MASK; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3 */ + default: + break; + } + base->FILT = reg; +#else + volatile uint8_t *regBase; + uint8_t reg; + + switch (filterIndex) + { + case 1: + regBase = &base->FILT1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) + case 2: + regBase = &base->FILT2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) + case 3: + regBase = &base->FILT3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) + case 4: + regBase = &base->FILT4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + default: + regBase = NULL; + break; + } + + if (NULL != regBase) + { + reg = *regBase; + reg |= LLWU_FILT1_FILTF_MASK; + *regBase = reg; + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + +#if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE) +/*! + * brief Sets the reset pin mode. + * + * This function determines how the reset pin is used as a low leakage mode exit source. + * + * param pinEnable Enable reset the pin filter + * param pinFilterEnable Specify whether the pin filter is enabled in Low-Leakage power mode. + */ +void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool pinFilterEnable) +{ + uint8_t reg; + + reg = base->RST; + reg &= ~(LLWU_RST_LLRSTE_MASK | LLWU_RST_RSTFILT_MASK); + reg |= (((uint32_t)pinEnable << LLWU_RST_LLRSTE_SHIFT) | ((uint32_t)pinFilterEnable << LLWU_RST_RSTFILT_SHIFT)); + base->RST = reg; +} +#endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */ diff --git a/source/hic_hal/freescale/kl27z/fsl_llwu.h b/source/hic_hal/freescale/kl27z/fsl_llwu.h new file mode 100644 index 000000000..ee1a68825 --- /dev/null +++ b/source/hic_hal/freescale/kl27z/fsl_llwu.h @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_LLWU_H_ +#define _FSL_LLWU_H_ + +#include "fsl_common.h" + +/*! @addtogroup llwu */ +/*! @{ */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LLWU driver version 2.0.2. */ +#define FSL_LLWU_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! + * @brief External input pin control modes + */ +typedef enum _llwu_external_pin_mode +{ + kLLWU_ExternalPinDisable = 0U, /*!< Pin disabled as a wakeup input. */ + kLLWU_ExternalPinRisingEdge = 1U, /*!< Pin enabled with the rising edge detection. */ + kLLWU_ExternalPinFallingEdge = 2U, /*!< Pin enabled with the falling edge detection.*/ + kLLWU_ExternalPinAnyEdge = 3U /*!< Pin enabled with any change detection. */ +} llwu_external_pin_mode_t; + +/*! + * @brief Digital filter control modes + */ +typedef enum _llwu_pin_filter_mode +{ + kLLWU_PinFilterDisable = 0U, /*!< Filter disabled. */ + kLLWU_PinFilterRisingEdge = 1U, /*!< Filter positive edge detection.*/ + kLLWU_PinFilterFallingEdge = 2U, /*!< Filter negative edge detection.*/ + kLLWU_PinFilterAnyEdge = 3U /*!< Filter any edge detection. */ +} llwu_pin_filter_mode_t; + +#if (defined(FSL_FEATURE_LLWU_HAS_VERID) && FSL_FEATURE_LLWU_HAS_VERID) +/*! + * @brief IP version ID definition. + */ +typedef struct _llwu_version_id +{ + uint16_t feature; /*!< A feature specification number. */ + uint8_t minor; /*!< The minor version number. */ + uint8_t major; /*!< The major version number. */ +} llwu_version_id_t; +#endif /* FSL_FEATURE_LLWU_HAS_VERID */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PARAM) && FSL_FEATURE_LLWU_HAS_PARAM) +/*! + * @brief IP parameter definition. + */ +typedef struct _llwu_param +{ + uint8_t filters; /*!< A number of the pin filter. */ + uint8_t dmas; /*!< A number of the wakeup DMA. */ + uint8_t modules; /*!< A number of the wakeup module. */ + uint8_t pins; /*!< A number of the wake up pin. */ +} llwu_param_t; +#endif /* FSL_FEATURE_LLWU_HAS_PARAM */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) +/*! + * @brief An external input pin filter control structure + */ +typedef struct _llwu_external_pin_filter_mode +{ + uint32_t pinIndex; /*!< A pin number */ + llwu_pin_filter_mode_t filterMode; /*!< Filter mode */ +} llwu_external_pin_filter_mode_t; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Low-Leakage Wakeup Unit Control APIs + * @{ + */ + +#if (defined(FSL_FEATURE_LLWU_HAS_VERID) && FSL_FEATURE_LLWU_HAS_VERID) +/*! + * @brief Gets the LLWU version ID. + * + * This function gets the LLWU version ID, including the major version number, + * the minor version number, and the feature specification number. + * + * @param base LLWU peripheral base address. + * @param versionId A pointer to the version ID structure. + */ +static inline void LLWU_GetVersionId(LLWU_Type *base, llwu_version_id_t *versionId) +{ + *((uint32_t *)versionId) = base->VERID; +} +#endif /* FSL_FEATURE_LLWU_HAS_VERID */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PARAM) && FSL_FEATURE_LLWU_HAS_PARAM) +/*! + * @brief Gets the LLWU parameter. + * + * This function gets the LLWU parameter, including a wakeup pin number, a module + * number, a DMA number, and a pin filter number. + * + * @param base LLWU peripheral base address. + * @param param A pointer to the LLWU parameter structure. + */ +static inline void LLWU_GetParam(LLWU_Type *base, llwu_param_t *param) +{ + *((uint32_t *)param) = base->PARAM; +} +#endif /* FSL_FEATURE_LLWU_HAS_PARAM */ + +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) +/*! + * @brief Sets the external input pin source mode. + * + * This function sets the external input pin source mode that is used + * as a wake up source. + * + * @param base LLWU peripheral base address. + * @param pinIndex A pin index to be enabled as an external wakeup source starting from 1. + * @param pinMode A pin configuration mode defined in the llwu_external_pin_modes_t. + */ +void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode); + +/*! + * @brief Gets the external wakeup source flag. + * + * This function checks the external pin flag to detect whether the MCU is + * woken up by the specific pin. + * + * @param base LLWU peripheral base address. + * @param pinIndex A pin index, which starts from 1. + * @return True if the specific pin is a wakeup source. + */ +bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex); + +/*! + * @brief Clears the external wakeup source flag. + * + * This function clears the external wakeup source flag for a specific pin. + * + * @param base LLWU peripheral base address. + * @param pinIndex A pin index, which starts from 1. + */ +void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex); +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ + +#if (defined(FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE) && FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE) +/*! + * @brief Enables/disables the internal module source. + * + * This function enables/disables the internal module source mode that is used + * as a wake up source. + * + * @param base LLWU peripheral base address. + * @param moduleIndex A module index to be enabled as an internal wakeup source starting from 1. + * @param enable An enable or a disable setting + */ +static inline void LLWU_EnableInternalModuleInterruptWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable) +{ + if (enable) + { + base->ME |= 1U << moduleIndex; + } + else + { + base->ME &= ~(1U << moduleIndex); + } +} + +#if (!(defined(FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG) && \ + FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG)) +/* Re-define the register which includes the internal wakeup module flag. */ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) /* 32-bit LLWU. */ +#if (defined(FSL_FEATURE_LLWU_HAS_MF) && FSL_FEATURE_LLWU_HAS_MF) +#define INTERNAL_WAKEUP_MODULE_FLAG_REG MF +#else +#error "Unsupported internal module flag register." +#endif +#else /* 8-bit LLUW. */ +#if (defined(FSL_FEATURE_LLWU_HAS_MF) && FSL_FEATURE_LLWU_HAS_MF) +#define INTERNAL_WAKEUP_MODULE_FLAG_REG MF5 +#elif (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) +#define INTERNAL_WAKEUP_MODULE_FLAG_REG PF3 +#elif (!(defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))) +#define INTERNAL_WAKEUP_MODULE_FLAG_REG F3 +#else +#error "Unsupported internal module flag register." +#endif +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ + +/*! + * @brief Gets the external wakeup source flag. + * + * This function checks the external pin flag to detect whether the system is + * woken up by the specific pin. + * + * @param base LLWU peripheral base address. + * @param moduleIndex A module index, which starts from 1. + * @return True if the specific pin is a wake up source. + */ +static inline bool LLWU_GetInternalWakeupModuleFlag(LLWU_Type *base, uint32_t moduleIndex) +{ + return ((1U << moduleIndex) == (base->INTERNAL_WAKEUP_MODULE_FLAG_REG & (1U << moduleIndex))); +} +#endif /* FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG */ +#endif /* FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE */ + +#if (defined(FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG) && FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG) +/*! + * @brief Enables/disables the internal module DMA wakeup source. + * + * This function enables/disables the internal DMA that is used as a wake up source. + * + * @param base LLWU peripheral base address. + * @param moduleIndex An internal module index which is used as a DMA request source, starting from 1. + * @param enable Enable or disable the DMA request source + */ +static inline void LLWU_EnableInternalModuleDmaRequestWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable) +{ + if (enable) + { + base->DE |= 1U << moduleIndex; + } + else + { + base->DE &= ~(1U << moduleIndex); + } +} +#endif /* FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) +/*! + * @brief Sets the pin filter configuration. + * + * This function sets the pin filter configuration. + * + * @param base LLWU peripheral base address. + * @param filterIndex A pin filter index used to enable/disable the digital filter, starting from 1. + * @param filterMode A filter mode configuration + */ +void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode); + +/*! + * @brief Gets the pin filter configuration. + * + * This function gets the pin filter flag. + * + * @param base LLWU peripheral base address. + * @param filterIndex A pin filter index, which starts from 1. + * @return True if the flag is a source of the existing low-leakage power mode. + */ +bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex); + +/*! + * @brief Clears the pin filter configuration. + * + * This function clears the pin filter flag. + * + * @param base LLWU peripheral base address. + * @param filterIndex A pin filter index to clear the flag, starting from 1. + */ +void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex); + +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + +#if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE) +/*! + * @brief Sets the reset pin mode. + * + * This function determines how the reset pin is used as a low leakage mode exit source. + * + * @param pinEnable Enable reset the pin filter + * @param pinFilterEnable Specify whether the pin filter is enabled in Low-Leakage power mode. + */ +void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool pinFilterEnable); +#endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ +#endif /* _FSL_LLWU_H_*/ diff --git a/source/hic_hal/freescale/kl27z/fsl_pmc.c b/source/hic_hal/freescale/kl27z/fsl_pmc.c new file mode 100644 index 000000000..c3cbaf0a4 --- /dev/null +++ b/source/hic_hal/freescale/kl27z/fsl_pmc.c @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_pmc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pmc" +#endif + +#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) +/*! + * brief Gets the PMC parameter. + * + * This function gets the PMC parameter including the VLPO enable and the HVD enable. + * + * param base PMC peripheral base address. + * param param Pointer to PMC param structure. + */ +void PMC_GetParam(PMC_Type *base, pmc_param_t *param) +{ + uint32_t reg = base->PARAM; + ; + param->vlpoEnable = (bool)(reg & PMC_PARAM_VLPOE_MASK); + param->hvdEnable = (bool)(reg & PMC_PARAM_HVDE_MASK); +} +#endif /* FSL_FEATURE_PMC_HAS_PARAM */ + +/*! + * brief Configures the low-voltage detect setting. + * + * This function configures the low-voltage detect setting, including the trip + * point voltage setting, enables or disables the interrupt, enables or disables the system reset. + * + * param base PMC peripheral base address. + * param config Low-voltage detect configuration structure. + */ +void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config_t *config) +{ + base->LVDSC1 = (uint8_t)((0U | +#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV) + ((uint32_t)config->voltSelect << PMC_LVDSC1_LVDV_SHIFT) | +#endif + ((uint32_t)config->enableInt << PMC_LVDSC1_LVDIE_SHIFT) | + ((uint32_t)config->enableReset << PMC_LVDSC1_LVDRE_SHIFT) + /* Clear the Low Voltage Detect Flag with previous power detect setting */ + | PMC_LVDSC1_LVDACK_MASK)); +} + +/*! + * brief Configures the low-voltage warning setting. + * + * This function configures the low-voltage warning setting, including the trip + * point voltage setting and enabling or disabling the interrupt. + * + * param base PMC peripheral base address. + * param config Low-voltage warning configuration structure. + */ +void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_config_t *config) +{ + base->LVDSC2 = (uint8_t)((0U | +#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV) + ((uint32_t)config->voltSelect << PMC_LVDSC2_LVWV_SHIFT) | +#endif + ((uint32_t)config->enableInt << PMC_LVDSC2_LVWIE_SHIFT) + /* Clear the Low Voltage Warning Flag with previous power detect setting */ + | PMC_LVDSC2_LVWACK_MASK)); +} + +#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) +/*! + * brief Configures the high-voltage detect setting. + * + * This function configures the high-voltage detect setting, including the trip + * point voltage setting, enabling or disabling the interrupt, enabling or disabling the system reset. + * + * param base PMC peripheral base address. + * param config High-voltage detect configuration structure. + */ +void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_config_t *config) +{ + base->HVDSC1 = (((uint32_t)config->voltSelect << PMC_HVDSC1_HVDV_SHIFT) | + ((uint32_t)config->enableInt << PMC_HVDSC1_HVDIE_SHIFT) | + ((uint32_t)config->enableReset << PMC_HVDSC1_HVDRE_SHIFT) + /* Clear the High Voltage Detect Flag with previous power detect setting */ + | PMC_HVDSC1_HVDACK_MASK); +} +#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ + +#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ + (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ + (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) +/*! + * brief Configures the PMC bandgap. + * + * This function configures the PMC bandgap, including the drive select and + * behavior in low-power mode. + * + * param base PMC peripheral base address. + * param config Pointer to the configuration structure + */ +void PMC_ConfigureBandgapBuffer(PMC_Type *base, const pmc_bandgap_buffer_config_t *config) +{ + base->REGSC = (uint8_t)(0U +#if (defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) + | ((uint32_t)config->enable << PMC_REGSC_BGBE_SHIFT) +#endif /* FSL_FEATURE_PMC_HAS_BGBE */ +#if (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) + | (((uint32_t)config->enableInLowPowerMode << PMC_REGSC_BGEN_SHIFT)) +#endif /* FSL_FEATURE_PMC_HAS_BGEN */ +#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS) + | ((uint32_t)config->drive << PMC_REGSC_BGBDS_SHIFT) +#endif /* FSL_FEATURE_PMC_HAS_BGBDS */ + ); +} +#endif diff --git a/source/hic_hal/freescale/kl27z/fsl_pmc.h b/source/hic_hal/freescale/kl27z/fsl_pmc.h new file mode 100644 index 000000000..adcee6512 --- /dev/null +++ b/source/hic_hal/freescale/kl27z/fsl_pmc.h @@ -0,0 +1,419 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_PMC_H_ +#define _FSL_PMC_H_ + +#include "fsl_common.h" + +/*! @addtogroup pmc */ +/*! @{ */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief PMC driver version */ +#define FSL_PMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ +/*@}*/ + +#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV) +/*! + * @brief Low-voltage Detect Voltage Select + */ +typedef enum _pmc_low_volt_detect_volt_select +{ + kPMC_LowVoltDetectLowTrip = 0U, /*!< Low-trip point selected (VLVD = VLVDL )*/ + kPMC_LowVoltDetectHighTrip = 1U /*!< High-trip point selected (VLVD = VLVDH )*/ +} pmc_low_volt_detect_volt_select_t; +#endif + +#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV) +/*! + * @brief Low-voltage Warning Voltage Select + */ +typedef enum _pmc_low_volt_warning_volt_select +{ + kPMC_LowVoltWarningLowTrip = 0U, /*!< Low-trip point selected (VLVW = VLVW1)*/ + kPMC_LowVoltWarningMid1Trip = 1U, /*!< Mid 1 trip point selected (VLVW = VLVW2)*/ + kPMC_LowVoltWarningMid2Trip = 2U, /*!< Mid 2 trip point selected (VLVW = VLVW3)*/ + kPMC_LowVoltWarningHighTrip = 3U /*!< High-trip point selected (VLVW = VLVW4)*/ +} pmc_low_volt_warning_volt_select_t; +#endif + +#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) +/*! + * @brief High-voltage Detect Voltage Select + */ +typedef enum _pmc_high_volt_detect_volt_select +{ + kPMC_HighVoltDetectLowTrip = 0U, /*!< Low-trip point selected (VHVD = VHVDL )*/ + kPMC_HighVoltDetectHighTrip = 1U /*!< High-trip point selected (VHVD = VHVDH )*/ +} pmc_high_volt_detect_volt_select_t; +#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ + +#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS) +/*! + * @brief Bandgap Buffer Drive Select. + */ +typedef enum _pmc_bandgap_buffer_drive_select +{ + kPMC_BandgapBufferDriveLow = 0U, /*!< Low-drive. */ + kPMC_BandgapBufferDriveHigh = 1U /*!< High-drive. */ +} pmc_bandgap_buffer_drive_select_t; +#endif /* FSL_FEATURE_PMC_HAS_BGBDS */ + +#if (defined(FSL_FEATURE_PMC_HAS_VLPO) && FSL_FEATURE_PMC_HAS_VLPO) +/*! + * @brief VLPx Option + */ +typedef enum _pmc_vlp_freq_option +{ + kPMC_FreqRestrict = 0U, /*!< Frequency is restricted in VLPx mode. */ + kPMC_FreqUnrestrict = 1U /*!< Frequency is unrestricted in VLPx mode. */ +} pmc_vlp_freq_mode_t; +#endif /* FSL_FEATURE_PMC_HAS_VLPO */ + +#if (defined(FSL_FEATURE_PMC_HAS_VERID) && FSL_FEATURE_PMC_HAS_VERID) +/*! + @brief IP version ID definition. + */ +typedef struct _pmc_version_id +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor version number. */ + uint8_t major; /*!< Major version number. */ +} pmc_version_id_t; +#endif /* FSL_FEATURE_PMC_HAS_VERID */ + +#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) +/*! @brief IP parameter definition. */ +typedef struct _pmc_param +{ + bool vlpoEnable; /*!< VLPO enable. */ + bool hvdEnable; /*!< HVD enable. */ +} pmc_param_t; +#endif /* FSL_FEATURE_PMC_HAS_PARAM */ + +/*! + * @brief Low-voltage Detect Configuration Structure + */ +typedef struct _pmc_low_volt_detect_config +{ + bool enableInt; /*!< Enable interrupt when Low-voltage detect*/ + bool enableReset; /*!< Enable system reset when Low-voltage detect*/ +#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV) + pmc_low_volt_detect_volt_select_t voltSelect; /*!< Low-voltage detect trip point voltage selection*/ +#endif +} pmc_low_volt_detect_config_t; + +/*! + * @brief Low-voltage Warning Configuration Structure + */ +typedef struct _pmc_low_volt_warning_config +{ + bool enableInt; /*!< Enable interrupt when low-voltage warning*/ +#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV) + pmc_low_volt_warning_volt_select_t voltSelect; /*!< Low-voltage warning trip point voltage selection*/ +#endif +} pmc_low_volt_warning_config_t; + +#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) +/*! + * @brief High-voltage Detect Configuration Structure + */ +typedef struct _pmc_high_volt_detect_config +{ + bool enableInt; /*!< Enable interrupt when high-voltage detect*/ + bool enableReset; /*!< Enable system reset when high-voltage detect*/ + pmc_high_volt_detect_volt_select_t voltSelect; /*!< High-voltage detect trip point voltage selection*/ +} pmc_high_volt_detect_config_t; +#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ + +#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ + (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ + (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) +/*! + * @brief Bandgap Buffer configuration. + */ +typedef struct _pmc_bandgap_buffer_config +{ +#if (defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) + bool enable; /*!< Enable bandgap buffer. */ +#endif +#if (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) + bool enableInLowPowerMode; /*!< Enable bandgap buffer in low-power mode. */ +#endif /* FSL_FEATURE_PMC_HAS_BGEN */ +#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS) + pmc_bandgap_buffer_drive_select_t drive; /*!< Bandgap buffer drive select. */ +#endif /* FSL_FEATURE_PMC_HAS_BGBDS */ +} pmc_bandgap_buffer_config_t; +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! @name Power Management Controller Control APIs*/ +/*@{*/ + +#if (defined(FSL_FEATURE_PMC_HAS_VERID) && FSL_FEATURE_PMC_HAS_VERID) +/*! + * @brief Gets the PMC version ID. + * + * This function gets the PMC version ID, including major version number, + * minor version number, and a feature specification number. + * + * @param base PMC peripheral base address. + * @param versionId Pointer to version ID structure. + */ +static inline void PMC_GetVersionId(PMC_Type *base, pmc_version_id_t *versionId) +{ + *((uint32_t *)versionId) = base->VERID; +} +#endif /* FSL_FEATURE_PMC_HAS_VERID */ + +#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) +/*! + * @brief Gets the PMC parameter. + * + * This function gets the PMC parameter including the VLPO enable and the HVD enable. + * + * @param base PMC peripheral base address. + * @param param Pointer to PMC param structure. + */ +void PMC_GetParam(PMC_Type *base, pmc_param_t *param); +#endif + +/*! + * @brief Configures the low-voltage detect setting. + * + * This function configures the low-voltage detect setting, including the trip + * point voltage setting, enables or disables the interrupt, enables or disables the system reset. + * + * @param base PMC peripheral base address. + * @param config Low-voltage detect configuration structure. + */ +void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config_t *config); + +/*! + * @brief Gets the Low-voltage Detect Flag status. + * + * This function reads the current LVDF status. If it returns 1, a low-voltage event is detected. + * + * @param base PMC peripheral base address. + * @return Current low-voltage detect flag + * - true: Low-voltage detected + * - false: Low-voltage not detected + */ +static inline bool PMC_GetLowVoltDetectFlag(PMC_Type *base) +{ + if (0U != (base->LVDSC1 & PMC_LVDSC1_LVDF_MASK)) + { + return true; + } + else + { + return false; + } +} + +/*! + * @brief Acknowledges clearing the Low-voltage Detect flag. + * + * This function acknowledges the low-voltage detection errors (write 1 to + * clear LVDF). + * + * @param base PMC peripheral base address. + */ +static inline void PMC_ClearLowVoltDetectFlag(PMC_Type *base) +{ + base->LVDSC1 |= PMC_LVDSC1_LVDACK_MASK; +} + +/*! + * @brief Configures the low-voltage warning setting. + * + * This function configures the low-voltage warning setting, including the trip + * point voltage setting and enabling or disabling the interrupt. + * + * @param base PMC peripheral base address. + * @param config Low-voltage warning configuration structure. + */ +void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_config_t *config); + +/*! + * @brief Gets the Low-voltage Warning Flag status. + * + * This function polls the current LVWF status. When 1 is returned, it + * indicates a low-voltage warning event. LVWF is set when V Supply transitions + * below the trip point or after reset and V Supply is already below the V LVW. + * + * @param base PMC peripheral base address. + * @return Current LVWF status + * - true: Low-voltage Warning Flag is set. + * - false: the Low-voltage Warning does not happen. + */ +static inline bool PMC_GetLowVoltWarningFlag(PMC_Type *base) +{ + if (0U != (base->LVDSC2 & PMC_LVDSC2_LVWF_MASK)) + { + return true; + } + else + { + return false; + } +} + +/*! + * @brief Acknowledges the Low-voltage Warning flag. + * + * This function acknowledges the low voltage warning errors (write 1 to + * clear LVWF). + * + * @param base PMC peripheral base address. + */ +static inline void PMC_ClearLowVoltWarningFlag(PMC_Type *base) +{ + base->LVDSC2 |= PMC_LVDSC2_LVWACK_MASK; +} + +#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) +/*! + * @brief Configures the high-voltage detect setting. + * + * This function configures the high-voltage detect setting, including the trip + * point voltage setting, enabling or disabling the interrupt, enabling or disabling the system reset. + * + * @param base PMC peripheral base address. + * @param config High-voltage detect configuration structure. + */ +void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_config_t *config); + +/*! + * @brief Gets the High-voltage Detect Flag status. + * + * This function reads the current HVDF status. If it returns 1, a low + * voltage event is detected. + * + * @param base PMC peripheral base address. + * @return Current high-voltage detect flag + * - true: High-voltage detected + * - false: High-voltage not detected + */ +static inline bool PMC_GetHighVoltDetectFlag(PMC_Type *base) +{ + return (bool)(base->HVDSC1 & PMC_HVDSC1_HVDF_MASK); +} + +/*! + * @brief Acknowledges clearing the High-voltage Detect flag. + * + * This function acknowledges the high-voltage detection errors (write 1 to + * clear HVDF). + * + * @param base PMC peripheral base address. + */ +static inline void PMC_ClearHighVoltDetectFlag(PMC_Type *base) +{ + base->HVDSC1 |= PMC_HVDSC1_HVDACK_MASK; +} +#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ + +#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ + (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ + (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) +/*! + * @brief Configures the PMC bandgap. + * + * This function configures the PMC bandgap, including the drive select and + * behavior in low-power mode. + * + * @param base PMC peripheral base address. + * @param config Pointer to the configuration structure + */ +void PMC_ConfigureBandgapBuffer(PMC_Type *base, const pmc_bandgap_buffer_config_t *config); +#endif + +#if (defined(FSL_FEATURE_PMC_HAS_ACKISO) && FSL_FEATURE_PMC_HAS_ACKISO) +/*! + * @brief Gets the acknowledge Peripherals and I/O pads isolation flag. + * + * This function reads the Acknowledge Isolation setting that indicates + * whether certain peripherals and the I/O pads are in a latched state as + * a result of having been in the VLLS mode. + * + * @param base PMC peripheral base address. + * @param base Base address for current PMC instance. + * @return ACK isolation + * 0 - Peripherals and I/O pads are in a normal run state. + * 1 - Certain peripherals and I/O pads are in an isolated and + * latched state. + */ +static inline bool PMC_GetPeriphIOIsolationFlag(PMC_Type *base) +{ + return (0U != (base->REGSC & PMC_REGSC_ACKISO_MASK)) ? true : false; +} + +/*! + * @brief Acknowledges the isolation flag to Peripherals and I/O pads. + * + * This function clears the ACK Isolation flag. Writing one to this setting + * when it is set releases the I/O pads and certain peripherals to their normal + * run mode state. + * + * @param base PMC peripheral base address. + */ +static inline void PMC_ClearPeriphIOIsolationFlag(PMC_Type *base) +{ + base->REGSC |= PMC_REGSC_ACKISO_MASK; +} +#endif /* FSL_FEATURE_PMC_HAS_ACKISO */ + +#if (defined(FSL_FEATURE_PMC_HAS_REGONS) && FSL_FEATURE_PMC_HAS_REGONS) +/*! + * @brief Gets the regulator regulation status. + * + * This function returns the regulator to run a regulation status. It provides + * the current status of the internal voltage regulator. + * + * @param base PMC peripheral base address. + * @param base Base address for current PMC instance. + * @return Regulation status + * 0 - Regulator is in a stop regulation or in transition to/from the regulation. + * 1 - Regulator is in a run regulation. + * + */ +static inline bool PMC_IsRegulatorInRunRegulation(PMC_Type *base) +{ + if (0U != (base->REGSC & PMC_REGSC_REGONS_MASK)) + { + return true; + } + else + { + return false; + } +} +#endif /* FSL_FEATURE_PMC_HAS_REGONS */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* _FSL_PMC_H_*/ diff --git a/source/hic_hal/freescale/kl27z/fsl_port.h b/source/hic_hal/freescale/kl27z/fsl_port.h new file mode 100644 index 000000000..128047bd2 --- /dev/null +++ b/source/hic_hal/freescale/kl27z/fsl_port.h @@ -0,0 +1,476 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_PORT_H_ +#define _FSL_PORT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup port + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.port" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! Version 2.1.0. */ +#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE +/*! @brief Internal resistor pull feature selection */ +enum _port_pull +{ + kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */ + kPORT_PullDown = 2U, /*!< Internal pull-down resistor is enabled. */ + kPORT_PullUp = 3U, /*!< Internal pull-up resistor is enabled. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */ + +#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE +/*! @brief Slew rate selection */ +enum _port_slew_rate +{ + kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */ + kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */ + +#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN +/*! @brief Open Drain feature enable/disable */ +enum _port_open_drain_enable +{ + kPORT_OpenDrainDisable = 0U, /*!< Open drain output is disabled. */ + kPORT_OpenDrainEnable = 1U, /*!< Open drain output is enabled. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ + +#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER +/*! @brief Passive filter feature enable/disable */ +enum _port_passive_filter_enable +{ + kPORT_PassiveFilterDisable = 0U, /*!< Passive input filter is disabled. */ + kPORT_PassiveFilterEnable = 1U, /*!< Passive input filter is enabled. */ +}; +#endif + +#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH +/*! @brief Configures the drive strength. */ +enum _port_drive_strength +{ + kPORT_LowDriveStrength = 0U, /*!< Low-drive strength is configured. */ + kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */ + +#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK +/*! @brief Unlock/lock the pin control register field[15:0] */ +enum _port_lock_register +{ + kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */ + kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ + +#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH +/*! @brief Pin mux selection */ +typedef enum _port_mux +{ + kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */ + kPORT_MuxAsGpio = 1U, /*!< Corresponding pin is configured as GPIO. */ + kPORT_MuxAlt2 = 2U, /*!< Chip-specific */ + kPORT_MuxAlt3 = 3U, /*!< Chip-specific */ + kPORT_MuxAlt4 = 4U, /*!< Chip-specific */ + kPORT_MuxAlt5 = 5U, /*!< Chip-specific */ + kPORT_MuxAlt6 = 6U, /*!< Chip-specific */ + kPORT_MuxAlt7 = 7U, /*!< Chip-specific */ + kPORT_MuxAlt8 = 8U, /*!< Chip-specific */ + kPORT_MuxAlt9 = 9U, /*!< Chip-specific */ + kPORT_MuxAlt10 = 10U, /*!< Chip-specific */ + kPORT_MuxAlt11 = 11U, /*!< Chip-specific */ + kPORT_MuxAlt12 = 12U, /*!< Chip-specific */ + kPORT_MuxAlt13 = 13U, /*!< Chip-specific */ + kPORT_MuxAlt14 = 14U, /*!< Chip-specific */ + kPORT_MuxAlt15 = 15U, /*!< Chip-specific */ +} port_mux_t; +#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */ + +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +/*! @brief Configures the interrupt generation condition. */ +typedef enum _port_interrupt +{ + kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */ +#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST + kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */ + kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */ + kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */ +#endif +#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG + kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */ + kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */ + kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */ +#endif + kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */ + kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */ + kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */ + kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */ + kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */ +#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER + kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */ + kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */ +#endif +} port_interrupt_t; +#endif + +#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER +/*! @brief Digital filter clock source selection */ +typedef enum _port_digital_filter_clock_source +{ + kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */ + kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */ +} port_digital_filter_clock_source_t; + +/*! @brief PORT digital filter feature configuration definition */ +typedef struct _port_digital_filter_config +{ + uint32_t digitalFilterWidth; /*!< Set digital filter width */ + port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */ +} port_digital_filter_config_t; +#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ + +#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH +/*! @brief PORT pin configuration structure */ +typedef struct _port_pin_config +{ +#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE + uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */ +#else + uint16_t : 2; +#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */ + +#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE + uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */ + + uint16_t : 1; + +#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER + uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_PASSIVE_FILTER */ + +#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN + uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ + +#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH + uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */ +#else + uint16_t : 1; +#endif + + uint16_t : 1; + +#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 3) + uint16_t mux : 3; /*!< Pin mux Configure */ + uint16_t : 4; +#elif defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 4) + uint16_t mux : 4; /*!< Pin mux Configure */ + uint16_t : 3; +#else + uint16_t : 7, +#endif + +#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK + uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ +} port_pin_config_t; +#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the port PCR register. + * + * This is an example to define an input pin or output pin PCR configuration. + * @code + * // Define a digital input pin PCR configuration + * port_pin_config_t config = { + * kPORT_PullUp, + * kPORT_FastSlewRate, + * kPORT_PassiveFilterDisable, + * kPORT_OpenDrainDisable, + * kPORT_LowDriveStrength, + * kPORT_MuxAsGpio, + * kPORT_UnLockRegister, + * }; + * @endcode + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param config PORT PCR register configuration structure. + */ +static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config) +{ + assert(config); + uint32_t addr = (uint32_t)&base->PCR[pin]; + *(volatile uint16_t *)(addr) = *((const uint16_t *)config); +} + +/*! + * @brief Sets the port PCR register for multiple pins. + * + * This is an example to define input pins or output pins PCR configuration. + * @code + * // Define a digital input pin PCR configuration + * port_pin_config_t config = { + * kPORT_PullUp , + * kPORT_PullEnable, + * kPORT_FastSlewRate, + * kPORT_PassiveFilterDisable, + * kPORT_OpenDrainDisable, + * kPORT_LowDriveStrength, + * kPORT_MuxAsGpio, + * kPORT_UnlockRegister, + * }; + * @endcode + * + * @param base PORT peripheral base pointer. + * @param mask PORT pin number macro. + * @param config PORT PCR register configuration structure. + */ +static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config) +{ + assert(config); + + uint16_t pcrl = *((const uint16_t *)config); + + if (mask & 0xffffU) + { + base->GPCLR = ((mask & 0xffffU) << 16) | pcrl; + } + if (mask >> 16) + { + base->GPCHR = (mask & 0xffff0000U) | pcrl; + } +} + +#if defined(FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG) && FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG +/*! + * @brief Sets the port interrupt configuration in PCR register for multiple pins. + * + * @param base PORT peripheral base pointer. + * @param mask PORT pin number macro. + * @param config PORT pin interrupt configuration. + * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled. + * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). + * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). + * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). + * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). + * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). + * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). + * - #kPORT_InterruptLogicZero : Interrupt when logic zero. + * - #kPORT_InterruptRisingEdge : Interrupt on rising edge. + * - #kPORT_InterruptFallingEdge: Interrupt on falling edge. + * - #kPORT_InterruptEitherEdge : Interrupt on either edge. + * - #kPORT_InterruptLogicOne : Interrupt when logic one. + * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit). + * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).. + */ +static inline void PORT_SetMultipleInterruptPinsConfig(PORT_Type *base, uint32_t mask, port_interrupt_t config) +{ + assert(config); + + if (mask & 0xffffU) + { + base->GICLR = (config << 16) | (mask & 0xffffU); + } + mask = mask >> 16; + if (mask) + { + base->GICHR = (config << 16) | (mask & 0xffffU); + } +} +#endif + +/*! + * @brief Configures the pin muxing. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param mux pin muxing slot selection. + * - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function. + * - #kPORT_MuxAsGpio : Set as GPIO. + * - #kPORT_MuxAlt2 : chip-specific. + * - #kPORT_MuxAlt3 : chip-specific. + * - #kPORT_MuxAlt4 : chip-specific. + * - #kPORT_MuxAlt5 : chip-specific. + * - #kPORT_MuxAlt6 : chip-specific. + * - #kPORT_MuxAlt7 : chip-specific. + * @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because + * the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is + * reset to zero : kPORT_PinDisabledOrAnalog). + * This function is recommended to use to reset the pin mux + * + */ +static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux); +} +#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */ + +#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER + +/*! + * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin. + * + * @param base PORT peripheral base pointer. + * @param mask PORT pin number macro. + */ +static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable) +{ + if (enable == true) + { + base->DFER |= mask; + } + else + { + base->DFER &= ~mask; + } +} + +/*! + * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin. + * + * @param base PORT peripheral base pointer. + * @param config PORT digital filter configuration structure. + */ +static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config) +{ + assert(config); + + base->DFCR = PORT_DFCR_CS(config->clockSource); + base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth); +} + +#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ + +/*@}*/ + +/*! @name Interrupt */ +/*@{*/ + +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +/*! + * @brief Configures the port pin interrupt/DMA request. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param config PORT pin interrupt configuration. + * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled. + * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). + * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). + * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). + * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). + * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). + * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). + * - #kPORT_InterruptLogicZero : Interrupt when logic zero. + * - #kPORT_InterruptRisingEdge : Interrupt on rising edge. + * - #kPORT_InterruptFallingEdge: Interrupt on falling edge. + * - #kPORT_InterruptEitherEdge : Interrupt on either edge. + * - #kPORT_InterruptLogicOne : Interrupt when logic one. + * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit). + * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit). + */ +static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config); +} +#endif + +#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH +/*! + * @brief Configures the port pin drive strength. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param config PORT pin drive strength + * - #kPORT_LowDriveStrength = 0U - Low-drive strength is configured. + * - #kPORT_HighDriveStrength = 1U - High-drive strength is configured. + */ +static inline void PORT_SetPinDriveStrength(PORT_Type *base, uint32_t pin, uint8_t strength) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE_MASK) | PORT_PCR_DSE(strength); +} +#endif + +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +/*! + * @brief Reads the whole port status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base PORT peripheral base pointer. + * @return Current port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 16 have the interrupt. + */ +static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base) +{ + return base->ISFR; +} + +/*! + * @brief Clears the multiple pin interrupt status flag. + * + * @param base PORT peripheral base pointer. + * @param mask PORT pin number macro. + */ +static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask) +{ + base->ISFR = mask; +} +#endif + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PORT_H_ */ diff --git a/source/hic_hal/freescale/kl27z/fsl_rcm.c b/source/hic_hal/freescale/kl27z/fsl_rcm.c new file mode 100644 index 000000000..475f47938 --- /dev/null +++ b/source/hic_hal/freescale/kl27z/fsl_rcm.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_rcm.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.rcm" +#endif + +/*! + * brief Configures the reset pin filter. + * + * This function sets the reset pin filter including the filter source, filter + * width, and so on. + * + * param base RCM peripheral base address. + * param config Pointer to the configuration structure. + */ +void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config) +{ + assert(NULL != config); + +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) + uint32_t reg; + + reg = (((uint32_t)config->enableFilterInStop << RCM_RPC_RSTFLTSS_SHIFT) | (uint32_t)config->filterInRunWait); + if (config->filterInRunWait == kRCM_FilterBusClock) + { + reg |= ((uint32_t)config->busClockFilterCount << RCM_RPC_RSTFLTSEL_SHIFT); + } + base->RPC = reg; +#else + base->RPFC = (((uint8_t)config->enableFilterInStop << RCM_RPFC_RSTFLTSS_SHIFT) | (uint8_t)config->filterInRunWait); + if (config->filterInRunWait == kRCM_FilterBusClock) + { + base->RPFW = config->busClockFilterCount; + } +#endif /* FSL_FEATURE_RCM_REG_WIDTH */ +} + +#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) +/*! + * brief Forces the boot from ROM. + * + * This function forces booting from ROM during all subsequent system resets. + * + * param base RCM peripheral base address. + * param config Boot configuration. + */ +void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config) +{ + uint32_t reg; + + reg = base->FM; + reg &= ~RCM_FM_FORCEROM_MASK; + reg |= ((uint32_t)config << RCM_FM_FORCEROM_SHIFT); + base->FM = reg; +} +#endif /* #if FSL_FEATURE_RCM_HAS_BOOTROM */ diff --git a/source/hic_hal/freescale/kl27z/fsl_rcm.h b/source/hic_hal/freescale/kl27z/fsl_rcm.h new file mode 100644 index 000000000..28d6692c3 --- /dev/null +++ b/source/hic_hal/freescale/kl27z/fsl_rcm.h @@ -0,0 +1,408 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_RCM_H_ +#define _FSL_RCM_H_ + +#include "fsl_common.h" + +/*! @addtogroup rcm */ +/*! @{*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief RCM driver version 2.0.2. */ +#define FSL_RCM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! + * @brief System Reset Source Name definitions + */ +typedef enum _rcm_reset_source +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) +/* RCM register bit width is 32. */ +#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP) + kRCM_SourceWakeup = RCM_SRS_WAKEUP_MASK, /*!< Low-leakage wakeup reset */ +#endif + kRCM_SourceLvd = RCM_SRS_LVD_MASK, /*!< Low-voltage detect reset */ +#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC) + kRCM_SourceLoc = RCM_SRS_LOC_MASK, /*!< Loss of clock reset */ +#endif /* FSL_FEATURE_RCM_HAS_LOC */ +#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL) + kRCM_SourceLol = RCM_SRS_LOL_MASK, /*!< Loss of lock reset */ +#endif /* FSL_FEATURE_RCM_HAS_LOL */ + kRCM_SourceWdog = RCM_SRS_WDOG_MASK, /*!< Watchdog reset */ + kRCM_SourcePin = RCM_SRS_PIN_MASK, /*!< External pin reset */ + kRCM_SourcePor = RCM_SRS_POR_MASK, /*!< Power on reset */ +#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG) + kRCM_SourceJtag = RCM_SRS_JTAG_MASK, /*!< JTAG generated reset */ +#endif /* FSL_FEATURE_RCM_HAS_JTAG */ + kRCM_SourceLockup = RCM_SRS_LOCKUP_MASK, /*!< Core lock up reset */ + kRCM_SourceSw = RCM_SRS_SW_MASK, /*!< Software reset */ +#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP) + kRCM_SourceMdmap = RCM_SRS_MDM_AP_MASK, /*!< MDM-AP system reset */ +#endif /* FSL_FEATURE_RCM_HAS_MDM_AP */ +#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT) + kRCM_SourceEzpt = RCM_SRS_EZPT_MASK, /*!< EzPort reset */ +#endif /* FSL_FEATURE_RCM_HAS_EZPORT */ + kRCM_SourceSackerr = RCM_SRS_SACKERR_MASK, /*!< Parameter could get all reset flags */ + +#else /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ +/* RCM register bit width is 8. */ +#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP) + kRCM_SourceWakeup = RCM_SRS0_WAKEUP_MASK, /*!< Low-leakage wakeup reset */ +#endif + kRCM_SourceLvd = RCM_SRS0_LVD_MASK, /*!< Low-voltage detect reset */ +#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC) + kRCM_SourceLoc = RCM_SRS0_LOC_MASK, /*!< Loss of clock reset */ +#endif /* FSL_FEATURE_RCM_HAS_LOC */ +#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL) + kRCM_SourceLol = RCM_SRS0_LOL_MASK, /*!< Loss of lock reset */ +#endif /* FSL_FEATURE_RCM_HAS_LOL */ + kRCM_SourceWdog = RCM_SRS0_WDOG_MASK, /*!< Watchdog reset */ + kRCM_SourcePin = RCM_SRS0_PIN_MASK, /*!< External pin reset */ + kRCM_SourcePor = RCM_SRS0_POR_MASK, /*!< Power on reset */ +#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG) + kRCM_SourceJtag = RCM_SRS1_JTAG_MASK << 8U, /*!< JTAG generated reset */ +#endif /* FSL_FEATURE_RCM_HAS_JTAG */ + kRCM_SourceLockup = RCM_SRS1_LOCKUP_MASK << 8U, /*!< Core lock up reset */ + kRCM_SourceSw = RCM_SRS1_SW_MASK << 8U, /*!< Software reset */ +#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP) + kRCM_SourceMdmap = RCM_SRS1_MDM_AP_MASK << 8U, /*!< MDM-AP system reset */ +#endif /* FSL_FEATURE_RCM_HAS_MDM_AP */ +#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT) + kRCM_SourceEzpt = RCM_SRS1_EZPT_MASK << 8U, /*!< EzPort reset */ +#endif /* FSL_FEATURE_RCM_HAS_EZPORT */ + kRCM_SourceSackerr = RCM_SRS1_SACKERR_MASK << 8U, /*!< Parameter could get all reset flags */ +#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ + kRCM_SourceAll = (int)0xffffffffU, +} rcm_reset_source_t; + +/*! + * @brief Reset pin filter select in Run and Wait modes. + */ +typedef enum _rcm_run_wait_filter_mode +{ + kRCM_FilterDisable = 0U, /*!< All filtering disabled */ + kRCM_FilterBusClock = 1U, /*!< Bus clock filter enabled */ + kRCM_FilterLpoClock = 2U /*!< LPO clock filter enabled */ +} rcm_run_wait_filter_mode_t; + +#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) +/*! + * @brief Boot from ROM configuration. + */ +typedef enum _rcm_boot_rom_config +{ + kRCM_BootFlash = 0U, /*!< Boot from flash */ + kRCM_BootRomCfg0 = 1U, /*!< Boot from boot ROM due to BOOTCFG0 */ + kRCM_BootRomFopt = 2U, /*!< Boot from boot ROM due to FOPT[7] */ + kRCM_BootRomBoth = 3U /*!< Boot from boot ROM due to both BOOTCFG0 and FOPT[7] */ +} rcm_boot_rom_config_t; +#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */ + +#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE) +/*! + * @brief Maximum delay time from interrupt asserts to system reset. + */ +typedef enum _rcm_reset_delay +{ + kRCM_ResetDelay8Lpo = 0U, /*!< Delay 8 LPO cycles. */ + kRCM_ResetDelay32Lpo = 1U, /*!< Delay 32 LPO cycles. */ + kRCM_ResetDelay128Lpo = 2U, /*!< Delay 128 LPO cycles. */ + kRCM_ResetDelay512Lpo = 3U /*!< Delay 512 LPO cycles. */ +} rcm_reset_delay_t; + +/*! + * @brief System reset interrupt enable bit definitions. + */ +typedef enum _rcm_interrupt_enable +{ + kRCM_IntNone = 0U, /*!< No interrupt enabled. */ + kRCM_IntLossOfClk = RCM_SRIE_LOC_MASK, /*!< Loss of clock interrupt. */ + kRCM_IntLossOfLock = RCM_SRIE_LOL_MASK, /*!< Loss of lock interrupt. */ + kRCM_IntWatchDog = RCM_SRIE_WDOG_MASK, /*!< Watch dog interrupt. */ + kRCM_IntExternalPin = RCM_SRIE_PIN_MASK, /*!< External pin interrupt. */ + kRCM_IntGlobal = RCM_SRIE_GIE_MASK, /*!< Global interrupts. */ + kRCM_IntCoreLockup = RCM_SRIE_LOCKUP_MASK, /*!< Core lock up interrupt */ + kRCM_IntSoftware = RCM_SRIE_SW_MASK, /*!< software interrupt */ + kRCM_IntStopModeAckErr = RCM_SRIE_SACKERR_MASK, /*!< Stop mode ACK error interrupt. */ +#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1) + kRCM_IntCore1 = RCM_SRIE_CORE1_MASK, /*!< Core 1 interrupt. */ +#endif + kRCM_IntAll = RCM_SRIE_LOC_MASK /*!< Enable all interrupts. */ + | RCM_SRIE_LOL_MASK | RCM_SRIE_WDOG_MASK | RCM_SRIE_PIN_MASK | RCM_SRIE_GIE_MASK | + RCM_SRIE_LOCKUP_MASK | RCM_SRIE_SW_MASK | RCM_SRIE_SACKERR_MASK +#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1) + | RCM_SRIE_CORE1_MASK +#endif +} rcm_interrupt_enable_t; +#endif /* FSL_FEATURE_RCM_HAS_SRIE */ + +#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID) +/*! + * @brief IP version ID definition. + */ +typedef struct _rcm_version_id +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor version number. */ + uint8_t major; /*!< Major version number. */ +} rcm_version_id_t; +#endif + +/*! + * @brief Reset pin filter configuration. + */ +typedef struct _rcm_reset_pin_filter_config +{ + bool enableFilterInStop; /*!< Reset pin filter select in stop mode. */ + rcm_run_wait_filter_mode_t filterInRunWait; /*!< Reset pin filter in run/wait mode. */ + uint8_t busClockFilterCount; /*!< Reset pin bus clock filter width. */ +} rcm_reset_pin_filter_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! @name Reset Control Module APIs*/ +/*@{*/ + +#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID) +/*! + * @brief Gets the RCM version ID. + * + * This function gets the RCM version ID including the major version number, + * the minor version number, and the feature specification number. + * + * @param base RCM peripheral base address. + * @param versionId Pointer to the version ID structure. + */ +static inline void RCM_GetVersionId(RCM_Type *base, rcm_version_id_t *versionId) +{ + *((uint32_t *)versionId) = base->VERID; +} +#endif + +#if (defined(FSL_FEATURE_RCM_HAS_PARAM) && FSL_FEATURE_RCM_HAS_PARAM) +/*! + * @brief Gets the reset source implemented status. + * + * This function gets the RCM parameter that indicates whether the corresponding reset source is implemented. + * Use source masks defined in the rcm_reset_source_t to get the desired source status. + * + * This is an example. + * @code + * uint32_t status; + * + * To test whether the MCU is reset using Watchdog. + * status = RCM_GetResetSourceImplementedStatus(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); + * @endcode + * + * @param base RCM peripheral base address. + * @return All reset source implemented status bit map. + */ +static inline uint32_t RCM_GetResetSourceImplementedStatus(RCM_Type *base) +{ + return base->PARAM; +} +#endif /* FSL_FEATURE_RCM_HAS_PARAM */ + +/*! + * @brief Gets the reset source status which caused a previous reset. + * + * This function gets the current reset source status. Use source masks + * defined in the rcm_reset_source_t to get the desired source status. + * + * This is an example. + * @code + * uint32_t resetStatus; + * + * To get all reset source statuses. + * resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceAll; + * + * To test whether the MCU is reset using Watchdog. + * resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceWdog; + * + * To test multiple reset sources. + * resetStatus = RCM_GetPreviousResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); + * @endcode + * + * @param base RCM peripheral base address. + * @return All reset source status bit map. + */ +static inline uint32_t RCM_GetPreviousResetSources(RCM_Type *base) +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) + return base->SRS; +#else + uint8_t tmpSrs0 = base->SRS0; + uint8_t tmpSrs1 = base->SRS1; + return (uint32_t)((uint32_t)tmpSrs0 | ((uint32_t)tmpSrs1 << 8U)); +#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ +} + +#if (defined(FSL_FEATURE_RCM_HAS_SSRS) && FSL_FEATURE_RCM_HAS_SSRS) +/*! + * @brief Gets the sticky reset source status. + * + * This function gets the current reset source status that has not been cleared + * by software for a specific source. + * + * This is an example. + * @code + * uint32_t resetStatus; + * + * To get all reset source statuses. + * resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceAll; + * + * To test whether the MCU is reset using Watchdog. + * resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceWdog; + * + * To test multiple reset sources. + * resetStatus = RCM_GetStickyResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); + * @endcode + * + * @param base RCM peripheral base address. + * @return All reset source status bit map. + */ +static inline uint32_t RCM_GetStickyResetSources(RCM_Type *base) +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) + return base->SSRS; +#else + return (base->SSRS0 | ((uint32_t)base->SSRS1 << 8U)); +#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ +} + +/*! + * @brief Clears the sticky reset source status. + * + * This function clears the sticky system reset flags indicated by source masks. + * + * This is an example. + * @code + * Clears multiple reset sources. + * RCM_ClearStickyResetSources(kRCM_SourceWdog | kRCM_SourcePin); + * @endcode + * + * @param base RCM peripheral base address. + * @param sourceMasks reset source status bit map + */ +static inline void RCM_ClearStickyResetSources(RCM_Type *base, uint32_t sourceMasks) +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) + base->SSRS = sourceMasks; +#else + base->SSRS0 = (sourceMasks & 0xffU); + base->SSRS1 = ((sourceMasks >> 8U) & 0xffU); +#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ +} +#endif /* FSL_FEATURE_RCM_HAS_SSRS */ + +/*! + * @brief Configures the reset pin filter. + * + * This function sets the reset pin filter including the filter source, filter + * width, and so on. + * + * @param base RCM peripheral base address. + * @param config Pointer to the configuration structure. + */ +void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config); + +#if (defined(FSL_FEATURE_RCM_HAS_EZPMS) && FSL_FEATURE_RCM_HAS_EZPMS) +/*! + * @brief Gets the EZP_MS_B pin assert status. + * + * This function gets the easy port mode status (EZP_MS_B) pin assert status. + * + * @param base RCM peripheral base address. + * @return status true - asserted, false - reasserted + */ +static inline bool RCM_GetEasyPortModePinStatus(RCM_Type *base) +{ + return (bool)(base->MR & RCM_MR_EZP_MS_MASK); +} +#endif /* FSL_FEATURE_RCM_HAS_EZPMS */ + +#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) +/*! + * @brief Gets the ROM boot source. + * + * This function gets the ROM boot source during the last chip reset. + * + * @param base RCM peripheral base address. + * @return The ROM boot source. + */ +static inline rcm_boot_rom_config_t RCM_GetBootRomSource(RCM_Type *base) +{ + return (rcm_boot_rom_config_t)((base->MR & RCM_MR_BOOTROM_MASK) >> RCM_MR_BOOTROM_SHIFT); +} + +/*! + * @brief Clears the ROM boot source flag. + * + * This function clears the ROM boot source flag. + * + * @param base Register base address of RCM + */ +static inline void RCM_ClearBootRomSource(RCM_Type *base) +{ + base->MR |= RCM_MR_BOOTROM_MASK; +} + +/*! + * @brief Forces the boot from ROM. + * + * This function forces booting from ROM during all subsequent system resets. + * + * @param base RCM peripheral base address. + * @param config Boot configuration. + */ +void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config); +#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */ + +#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE) +/*! + * @brief Sets the system reset interrupt configuration. + * + * For a graceful shut down, the RCM supports delaying the assertion of the system + * reset for a period of time when the reset interrupt is generated. This function + * can be used to enable the interrupt and the delay period. The interrupts + * are passed in as bit mask. See rcm_int_t for details. For example, to + * delay a reset for 512 LPO cycles after the WDOG timeout or loss-of-clock occurs, + * configure as follows: + * RCM_SetSystemResetInterruptConfig(kRCM_IntWatchDog | kRCM_IntLossOfClk, kRCM_ResetDelay512Lpo); + * + * @param base RCM peripheral base address. + * @param intMask Bit mask of the system reset interrupts to enable. See + * rcm_interrupt_enable_t for details. + * @param Delay Bit mask of the system reset interrupts to enable. + */ +static inline void RCM_SetSystemResetInterruptConfig(RCM_Type *base, uint32_t intMask, rcm_reset_delay_t delay) +{ + base->SRIE = (intMask | delay); +} +#endif /* FSL_FEATURE_RCM_HAS_SRIE */ +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* _FSL_RCM_H_ */ diff --git a/source/hic_hal/freescale/kl27z/fsl_smc.c b/source/hic_hal/freescale/kl27z/fsl_smc.c new file mode 100644 index 000000000..b3998d037 --- /dev/null +++ b/source/hic_hal/freescale/kl27z/fsl_smc.c @@ -0,0 +1,511 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_smc.h" +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.smc" +#endif + +typedef void (*smc_stop_ram_func_t)(void); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void SMC_EnterStopRamFunc(void); + +/******************************************************************************* + * Variables + ******************************************************************************/ +static uint32_t g_savedPrimask; + +/* + * The ram function code is: + * + * uint32_t i; + * for (i=0; i<0x8; i++) + * { + * __NOP(); + * } + * __DSB(); + * __WFI(); + * __ISB(); + * + * When entring the stop modes, the flash prefetch might be interrupted, thus + * the prefetched code or data might be broken. To make sure the flash is idle + * when entring the stop modes, the code is moved to ram. And delay for a while + * before WFI to make sure previous flash prefetch is finished. + * + * Only need to do like this when code is in flash, if code is in rom or ram, + * this is not necessary. + */ +static uint16_t s_stopRamFuncArray[] = { + 0x2000, /* MOVS R0, #0 */ + 0x2808, /* CMP R0, #8 */ + 0xD202, /* BCS.N */ + 0xBF00, /* NOP */ + 0x1C40, /* ADDS R0, R0, #1 */ + 0xE7FA, /* B.N */ + 0xF3BF, 0x8F4F, /* DSB */ + 0xBF30, /* WFI */ + 0xF3BF, 0x8F6F, /* ISB */ + 0x4770, /* BX LR */ +}; + +/******************************************************************************* + * Code + ******************************************************************************/ +static void SMC_EnterStopRamFunc(void) +{ + uint32_t ramFuncEntry = ((uint32_t)(s_stopRamFuncArray)) + 1U; + smc_stop_ram_func_t stopRamFunc = (smc_stop_ram_func_t)ramFuncEntry; + stopRamFunc(); +} + +#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) +/*! + * brief Gets the SMC parameter. + * + * This function gets the SMC parameter including the enabled power mdoes. + * + * param base SMC peripheral base address. + * param param Pointer to the SMC param structure. + */ +void SMC_GetParam(SMC_Type *base, smc_param_t *param) +{ + uint32_t reg = base->PARAM; + param->hsrunEnable = (bool)(reg & SMC_PARAM_EHSRUN_MASK); + param->llsEnable = (bool)(reg & SMC_PARAM_ELLS_MASK); + param->lls2Enable = (bool)(reg & SMC_PARAM_ELLS2_MASK); + param->vlls0Enable = (bool)(reg & SMC_PARAM_EVLLS0_MASK); +} +#endif /* FSL_FEATURE_SMC_HAS_PARAM */ + +/*! + * brief Prepares to enter stop modes. + * + * This function should be called before entering STOP/VLPS/LLS/VLLS modes. + */ +void SMC_PreEnterStopModes(void) +{ + g_savedPrimask = DisableGlobalIRQ(); + __ISB(); +} + +/*! + * brief Recovers after wake up from stop modes. + * + * This function should be called after wake up from STOP/VLPS/LLS/VLLS modes. + * It is used with ref SMC_PreEnterStopModes. + */ +void SMC_PostExitStopModes(void) +{ + EnableGlobalIRQ(g_savedPrimask); + __ISB(); +} + +/*! + * brief Prepares to enter wait modes. + * + * This function should be called before entering WAIT/VLPW modes. + */ +void SMC_PreEnterWaitModes(void) +{ + g_savedPrimask = DisableGlobalIRQ(); + __ISB(); +} + +/*! + * brief Recovers after wake up from stop modes. + * + * This function should be called after wake up from WAIT/VLPW modes. + * It is used with ref SMC_PreEnterWaitModes. + */ +void SMC_PostExitWaitModes(void) +{ + EnableGlobalIRQ(g_savedPrimask); + __ISB(); +} + +/*! + * brief Configures the system to RUN power mode. + * + * param base SMC peripheral base address. + * return SMC configuration error code. + */ +status_t SMC_SetPowerModeRun(SMC_Type *base) +{ + uint8_t reg; + + reg = base->PMCTRL; + /* configure Normal RUN mode */ + reg &= ~(uint8_t)SMC_PMCTRL_RUNM_MASK; + reg |= ((uint8_t)kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT); + base->PMCTRL = reg; + + return kStatus_Success; +} + +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) +/*! + * brief Configures the system to HSRUN power mode. + * + * param base SMC peripheral base address. + * return SMC configuration error code. + */ +status_t SMC_SetPowerModeHsrun(SMC_Type *base) +{ + uint8_t reg; + + reg = base->PMCTRL; + /* configure High Speed RUN mode */ + reg &= ~SMC_PMCTRL_RUNM_MASK; + reg |= ((uint8_t)kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT); + base->PMCTRL = reg; + + return kStatus_Success; +} +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ + +/*! + * brief Configures the system to WAIT power mode. + * + * param base SMC peripheral base address. + * return SMC configuration error code. + */ +status_t SMC_SetPowerModeWait(SMC_Type *base) +{ + /* configure Normal Wait mode */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + __DSB(); + __WFI(); + __ISB(); + + return kStatus_Success; +} + +/*! + * brief Configures the system to Stop power mode. + * + * param base SMC peripheral base address. + * param option Partial Stop mode option. + * return SMC configuration error code. + */ +status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option) +{ + uint8_t reg; + +#if (defined(FSL_FEATURE_SMC_HAS_PSTOPO) && FSL_FEATURE_SMC_HAS_PSTOPO) + /* configure the Partial Stop mode in Normal Stop mode */ + reg = base->STOPCTRL; + reg &= ~(uint8_t)SMC_STOPCTRL_PSTOPO_MASK; + reg |= ((uint8_t)option << SMC_STOPCTRL_PSTOPO_SHIFT); + base->STOPCTRL = reg; +#endif + + /* configure Normal Stop mode */ + reg = base->PMCTRL; + reg &= ~(uint8_t)SMC_PMCTRL_STOPM_MASK; + reg |= ((uint8_t)kSMC_StopNormal << SMC_PMCTRL_STOPM_SHIFT); + base->PMCTRL = reg; + + /* Set the SLEEPDEEP bit to enable deep sleep mode (stop mode) */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* read back to make sure the configuration valid before enter stop mode */ + (void)base->PMCTRL; + SMC_EnterStopRamFunc(); + + /* check whether the power mode enter Stop mode succeed */ + if (0U != (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)) + { + return kStatus_SMC_StopAbort; + } + else + { + return kStatus_Success; + } +} + +/*! + * brief Configures the system to VLPR power mode. + * + * param base SMC peripheral base address. + * return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlpr(SMC_Type *base +#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) + , + bool wakeupMode +#endif +) +{ + uint8_t reg; + + reg = base->PMCTRL; +#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) + /* configure whether the system remains in VLP mode on an interrupt */ + if (wakeupMode) + { + /* exits to RUN mode on an interrupt */ + reg |= SMC_PMCTRL_LPWUI_MASK; + } + else + { + /* remains in VLP mode on an interrupt */ + reg &= ~(uint8_t)SMC_PMCTRL_LPWUI_MASK; + } +#endif /* FSL_FEATURE_SMC_HAS_LPWUI */ + + /* configure VLPR mode */ + reg &= ~(uint8_t)SMC_PMCTRL_RUNM_MASK; + reg |= ((uint8_t)kSMC_RunVlpr << SMC_PMCTRL_RUNM_SHIFT); + base->PMCTRL = reg; + + return kStatus_Success; +} + +/*! + * brief Configures the system to VLPW power mode. + * + * param base SMC peripheral base address. + * return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlpw(SMC_Type *base) +{ + /* configure VLPW mode */ + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + __DSB(); + __WFI(); + __ISB(); + + return kStatus_Success; +} + +/*! + * brief Configures the system to VLPS power mode. + * + * param base SMC peripheral base address. + * return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlps(SMC_Type *base) +{ + uint8_t reg; + + /* configure VLPS mode */ + reg = base->PMCTRL; + reg &= ~(uint8_t)SMC_PMCTRL_STOPM_MASK; + reg |= ((uint8_t)kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT); + base->PMCTRL = reg; + + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* read back to make sure the configuration valid before enter stop mode */ + (void)base->PMCTRL; + SMC_EnterStopRamFunc(); + + /* check whether the power mode enter VLPS mode succeed */ + if (0U != (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)) + { + return kStatus_SMC_StopAbort; + } + else + { + return kStatus_Success; + } +} + +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) +/*! + * brief Configures the system to LLS power mode. + * + * param base SMC peripheral base address. + * return SMC configuration error code. + */ +status_t SMC_SetPowerModeLls(SMC_Type *base +#if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ + (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)) + , + const smc_power_mode_lls_config_t *config +#endif +) +{ + uint8_t reg; + + /* configure to LLS mode */ + reg = base->PMCTRL; + reg &= ~(uint8_t)SMC_PMCTRL_STOPM_MASK; + reg |= ((uint8_t)kSMC_StopLls << SMC_PMCTRL_STOPM_SHIFT); + base->PMCTRL = reg; + +/* configure LLS sub-mode*/ +#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + reg = base->STOPCTRL; + reg &= ~(uint8_t)SMC_STOPCTRL_LLSM_MASK; + reg |= ((uint8_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT); + base->STOPCTRL = reg; +#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */ + +#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) + if (config->enableLpoClock) + { + base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK; + } + else + { + base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK; + } +#endif /* FSL_FEATURE_SMC_HAS_LPOPO */ + + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* read back to make sure the configuration valid before enter stop mode */ + (void)base->PMCTRL; + SMC_EnterStopRamFunc(); + + /* check whether the power mode enter LLS mode succeed */ + if (0U != (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)) + { + return kStatus_SMC_StopAbort; + } + else + { + return kStatus_Success; + } +} +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ + +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) +/*! + * brief Configures the system to VLLS power mode. + * + * param base SMC peripheral base address. + * param config The VLLS power mode configuration structure. + * return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config) +{ + uint8_t reg; + +#if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO) +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ + (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ + (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + if (config->subMode == kSMC_StopSub0) +#endif + { + /* configure whether the Por Detect work in Vlls0 mode */ + if (true == config->enablePorDetectInVlls0) + { +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + base->VLLSCTRL &= ~SMC_VLLSCTRL_PORPO_MASK; +#else + base->STOPCTRL &= ~(uint8_t)SMC_STOPCTRL_PORPO_MASK; +#endif + } + else + { +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + base->VLLSCTRL |= SMC_VLLSCTRL_PORPO_MASK; +#else + base->STOPCTRL |= SMC_STOPCTRL_PORPO_MASK; +#endif + } + } +#endif /* FSL_FEATURE_SMC_HAS_PORPO */ + +#if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) + else if (config->subMode == kSMC_StopSub2) + { + /* configure whether the Por Detect work in Vlls0 mode */ + if (true == config->enableRam2InVlls2) + { +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + base->VLLSCTRL |= SMC_VLLSCTRL_RAM2PO_MASK; +#else + base->STOPCTRL |= SMC_STOPCTRL_RAM2PO_MASK; +#endif + } + else + { +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + base->VLLSCTRL &= ~SMC_VLLSCTRL_RAM2PO_MASK; +#else + base->STOPCTRL &= ~(uint8_t)SMC_STOPCTRL_RAM2PO_MASK; +#endif + } + } + else + { + /* Add this to fix MISRA C2012 rule15.7 issue: Empty else without comment. */ + } +#endif /* FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION */ + + /* configure to VLLS mode */ + reg = base->PMCTRL; + reg &= ~(uint8_t)SMC_PMCTRL_STOPM_MASK; + reg |= ((uint8_t)kSMC_StopVlls << SMC_PMCTRL_STOPM_SHIFT); + base->PMCTRL = reg; + +/* configure the VLLS sub-mode */ +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + reg = base->VLLSCTRL; + reg &= ~SMC_VLLSCTRL_VLLSM_MASK; + reg |= ((uint8_t)config->subMode << SMC_VLLSCTRL_VLLSM_SHIFT); + base->VLLSCTRL = reg; +#else +#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + reg = base->STOPCTRL; + reg &= ~(uint8_t)SMC_STOPCTRL_LLSM_MASK; + reg |= ((uint8_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT); + base->STOPCTRL = reg; +#else + reg = base->STOPCTRL; + reg &= ~SMC_STOPCTRL_VLLSM_MASK; + reg |= ((uint8_t)config->subMode << SMC_STOPCTRL_VLLSM_SHIFT); + base->STOPCTRL = reg; +#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */ +#endif + +#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) + if (config->enableLpoClock) + { + base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK; + } + else + { + base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK; + } +#endif /* FSL_FEATURE_SMC_HAS_LPOPO */ + + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* read back to make sure the configuration valid before enter stop mode */ + (void)base->PMCTRL; + SMC_EnterStopRamFunc(); + + /* check whether the power mode enter LLS mode succeed */ + if (0U != (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)) + { + return kStatus_SMC_StopAbort; + } + else + { + return kStatus_Success; + } +} +#endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */ diff --git a/source/hic_hal/freescale/kl27z/fsl_smc.h b/source/hic_hal/freescale/kl27z/fsl_smc.h new file mode 100644 index 000000000..e5c318e1a --- /dev/null +++ b/source/hic_hal/freescale/kl27z/fsl_smc.h @@ -0,0 +1,421 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_SMC_H_ +#define _FSL_SMC_H_ + +#include "fsl_common.h" + +/*! @addtogroup smc */ +/*! @{ */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SMC driver version 2.0.5. */ +#define FSL_SMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) +/*@}*/ + +/*! + * @brief Power Modes Protection + */ +typedef enum _smc_power_mode_protection +{ +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) + kSMC_AllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK, /*!< Allow Very-low-leakage Stop Mode. */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) + kSMC_AllowPowerModeLls = SMC_PMPROT_ALLS_MASK, /*!< Allow Low-leakage Stop Mode. */ +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ + kSMC_AllowPowerModeVlp = SMC_PMPROT_AVLP_MASK, /*!< Allow Very-Low-power Mode. */ +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) + kSMC_AllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High-speed Run mode. */ +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ + kSMC_AllowPowerModeAll = (0U +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) + | SMC_PMPROT_AVLLS_MASK +#endif +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) + | SMC_PMPROT_ALLS_MASK +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ + | SMC_PMPROT_AVLP_MASK +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) + | kSMC_AllowPowerModeHsrun +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ + ) /*!< Allow all power mode. */ +} smc_power_mode_protection_t; + +/*! + * @brief Power Modes in PMSTAT + */ +typedef enum _smc_power_state +{ + kSMC_PowerStateRun = 0x01U << 0U, /*!< 0000_0001 - Current power mode is RUN */ + kSMC_PowerStateStop = 0x01U << 1U, /*!< 0000_0010 - Current power mode is STOP */ + kSMC_PowerStateVlpr = 0x01U << 2U, /*!< 0000_0100 - Current power mode is VLPR */ + kSMC_PowerStateVlpw = 0x01U << 3U, /*!< 0000_1000 - Current power mode is VLPW */ + kSMC_PowerStateVlps = 0x01U << 4U, /*!< 0001_0000 - Current power mode is VLPS */ +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) + kSMC_PowerStateLls = 0x01U << 5U, /*!< 0010_0000 - Current power mode is LLS */ +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) + kSMC_PowerStateVlls = 0x01U << 6U, /*!< 0100_0000 - Current power mode is VLLS */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) + kSMC_PowerStateHsrun = 0x01U << 7U /*!< 1000_0000 - Current power mode is HSRUN */ +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ +} smc_power_state_t; + +/*! + * @brief Run mode definition + */ +typedef enum _smc_run_mode +{ + kSMC_RunNormal = 0U, /*!< Normal RUN mode. */ + kSMC_RunVlpr = 2U, /*!< Very-low-power RUN mode. */ +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) + kSMC_Hsrun = 3U /*!< High-speed Run mode (HSRUN). */ +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ +} smc_run_mode_t; + +/*! + * @brief Stop mode definition + */ +typedef enum _smc_stop_mode +{ + kSMC_StopNormal = 0U, /*!< Normal STOP mode. */ + kSMC_StopVlps = 2U, /*!< Very-low-power STOP mode. */ +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) + kSMC_StopLls = 3U, /*!< Low-leakage Stop mode. */ +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) + kSMC_StopVlls = 4U /*!< Very-low-leakage Stop mode. */ +#endif +} smc_stop_mode_t; + +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ + (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ + (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) +/*! + * @brief VLLS/LLS stop sub mode definition + */ +typedef enum _smc_stop_submode +{ + kSMC_StopSub0 = 0U, /*!< Stop submode 0, for VLLS0/LLS0. */ + kSMC_StopSub1 = 1U, /*!< Stop submode 1, for VLLS1/LLS1. */ + kSMC_StopSub2 = 2U, /*!< Stop submode 2, for VLLS2/LLS2. */ + kSMC_StopSub3 = 3U /*!< Stop submode 3, for VLLS3/LLS3. */ +} smc_stop_submode_t; +#endif + +/*! + * @brief Partial STOP option + */ +typedef enum _smc_partial_stop_mode +{ + kSMC_PartialStop = 0U, /*!< STOP - Normal Stop mode*/ + kSMC_PartialStop1 = 1U, /*!< Partial Stop with both system and bus clocks disabled*/ + kSMC_PartialStop2 = 2U, /*!< Partial Stop with system clock disabled and bus clock enabled*/ +} smc_partial_stop_option_t; + +/*! + * @brief SMC configuration status. + */ +enum _smc_status +{ + kStatus_SMC_StopAbort = MAKE_STATUS(kStatusGroup_POWER, 0) /*!< Entering Stop mode is abort*/ +}; + +#if (defined(FSL_FEATURE_SMC_HAS_VERID) && FSL_FEATURE_SMC_HAS_VERID) +/*! + * @brief IP version ID definition. + */ +typedef struct _smc_version_id +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor version number. */ + uint8_t major; /*!< Major version number. */ +} smc_version_id_t; +#endif /* FSL_FEATURE_SMC_HAS_VERID */ + +#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) +/*! + * @brief IP parameter definition. + */ +typedef struct _smc_param +{ + bool hsrunEnable; /*!< HSRUN mode enable. */ + bool llsEnable; /*!< LLS mode enable. */ + bool lls2Enable; /*!< LLS2 mode enable. */ + bool vlls0Enable; /*!< VLLS0 mode enable. */ +} smc_param_t; +#endif /* FSL_FEATURE_SMC_HAS_PARAM */ + +#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ + (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) +/*! + * @brief SMC Low-Leakage Stop power mode configuration. + */ +typedef struct _smc_power_mode_lls_config +{ +#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + smc_stop_submode_t subMode; /*!< Low-leakage Stop sub-mode */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) + bool enableLpoClock; /*!< Enable LPO clock in LLS mode */ +#endif +} smc_power_mode_lls_config_t; +#endif /* (FSL_FEATURE_SMC_HAS_LLS_SUBMODE || FSL_FEATURE_SMC_HAS_LPOPO) */ + +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) +/*! + * @brief SMC Very Low-Leakage Stop power mode configuration. + */ +typedef struct _smc_power_mode_vlls_config +{ +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ + (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ + (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + smc_stop_submode_t subMode; /*!< Very Low-leakage Stop sub-mode */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO) + bool enablePorDetectInVlls0; /*!< Enable Power on reset detect in VLLS mode */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) + bool enableRam2InVlls2; /*!< Enable RAM2 power in VLLS2 */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) + bool enableLpoClock; /*!< Enable LPO clock in VLLS mode */ +#endif +} smc_power_mode_vlls_config_t; +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! @name System mode controller APIs*/ +/*@{*/ + +#if (defined(FSL_FEATURE_SMC_HAS_VERID) && FSL_FEATURE_SMC_HAS_VERID) +/*! + * @brief Gets the SMC version ID. + * + * This function gets the SMC version ID, including major version number, + * minor version number, and feature specification number. + * + * @param base SMC peripheral base address. + * @param versionId Pointer to the version ID structure. + */ +static inline void SMC_GetVersionId(SMC_Type *base, smc_version_id_t *versionId) +{ + *((uint32_t *)versionId) = base->VERID; +} +#endif /* FSL_FEATURE_SMC_HAS_VERID */ + +#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) +/*! + * @brief Gets the SMC parameter. + * + * This function gets the SMC parameter including the enabled power mdoes. + * + * @param base SMC peripheral base address. + * @param param Pointer to the SMC param structure. + */ +void SMC_GetParam(SMC_Type *base, smc_param_t *param); +#endif + +/*! + * @brief Configures all power mode protection settings. + * + * This function configures the power mode protection settings for + * supported power modes in the specified chip family. The available power modes + * are defined in the smc_power_mode_protection_t. This should be done at an early + * system level initialization stage. See the reference manual for details. + * This register can only write once after the power reset. + * + * The allowed modes are passed as bit map. For example, to allow LLS and VLLS, + * use SMC_SetPowerModeProtection(kSMC_AllowPowerModeVlls | kSMC_AllowPowerModeVlps). + * To allow all modes, use SMC_SetPowerModeProtection(kSMC_AllowPowerModeAll). + * + * @param base SMC peripheral base address. + * @param allowedModes Bitmap of the allowed power modes. + */ +static inline void SMC_SetPowerModeProtection(SMC_Type *base, uint8_t allowedModes) +{ + base->PMPROT = allowedModes; +} + +/*! + * @brief Gets the current power mode status. + * + * This function returns the current power mode status. After the application + * switches the power mode, it should always check the status to check whether it + * runs into the specified mode or not. The application should check + * this mode before switching to a different mode. The system requires that + * only certain modes can switch to other specific modes. See the + * reference manual for details and the smc_power_state_t for information about + * the power status. + * + * @param base SMC peripheral base address. + * @return Current power mode status. + */ +static inline smc_power_state_t SMC_GetPowerModeState(SMC_Type *base) +{ + return (smc_power_state_t)base->PMSTAT; +} + +/*! + * @brief Prepares to enter stop modes. + * + * This function should be called before entering STOP/VLPS/LLS/VLLS modes. + */ +void SMC_PreEnterStopModes(void); + +/*! + * @brief Recovers after wake up from stop modes. + * + * This function should be called after wake up from STOP/VLPS/LLS/VLLS modes. + * It is used with @ref SMC_PreEnterStopModes. + */ +void SMC_PostExitStopModes(void); + +/*! + * @brief Prepares to enter wait modes. + * + * This function should be called before entering WAIT/VLPW modes. + */ +void SMC_PreEnterWaitModes(void); + +/*! + * @brief Recovers after wake up from stop modes. + * + * This function should be called after wake up from WAIT/VLPW modes. + * It is used with @ref SMC_PreEnterWaitModes. + */ +void SMC_PostExitWaitModes(void); + +/*! + * @brief Configures the system to RUN power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeRun(SMC_Type *base); + +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) +/*! + * @brief Configures the system to HSRUN power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeHsrun(SMC_Type *base); +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ + +/*! + * @brief Configures the system to WAIT power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeWait(SMC_Type *base); + +/*! + * @brief Configures the system to Stop power mode. + * + * @param base SMC peripheral base address. + * @param option Partial Stop mode option. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option); + +#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) +/*! + * @brief Configures the system to VLPR power mode. + * + * @param base SMC peripheral base address. + * @param wakeupMode Enter Normal Run mode if true, else stay in VLPR mode. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlpr(SMC_Type *base, bool wakeupMode); +#else +/*! + * @brief Configures the system to VLPR power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlpr(SMC_Type *base); +#endif /* FSL_FEATURE_SMC_HAS_LPWUI */ + +/*! + * @brief Configures the system to VLPW power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlpw(SMC_Type *base); + +/*! + * @brief Configures the system to VLPS power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlps(SMC_Type *base); + +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) +#if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ + (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)) +/*! + * @brief Configures the system to LLS power mode. + * + * @param base SMC peripheral base address. + * @param config The LLS power mode configuration structure + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeLls(SMC_Type *base, const smc_power_mode_lls_config_t *config); +#else +/*! + * @brief Configures the system to LLS power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeLls(SMC_Type *base); +#endif +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ + +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) +/*! + * @brief Configures the system to VLLS power mode. + * + * @param base SMC peripheral base address. + * @param config The VLLS power mode configuration structure. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config); +#endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_SMC_H_ */ diff --git a/source/hic_hal/freescale/kl27z/fsl_tpm.c b/source/hic_hal/freescale/kl27z/fsl_tpm.c new file mode 100644 index 000000000..9a390a2be --- /dev/null +++ b/source/hic_hal/freescale/kl27z/fsl_tpm.c @@ -0,0 +1,766 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_tpm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define TPM_COMBINE_SHIFT (8U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base TPM peripheral base address + * + * @return The TPM instance + */ +static uint32_t TPM_GetInstance(TPM_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to TPM bases for each instance. */ +static TPM_Type *const s_tpmBases[] = TPM_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to TPM clocks for each instance. */ +static const clock_ip_name_t s_tpmClocks[] = TPM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t TPM_GetInstance(TPM_Type *base) +{ + uint32_t instance; + uint32_t tpmArrayCount = (sizeof(s_tpmBases) / sizeof(s_tpmBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < tpmArrayCount; instance++) + { + if (s_tpmBases[instance] == base) + { + break; + } + } + + assert(instance < tpmArrayCount); + + return instance; +} + +void TPM_Init(TPM_Type *base, const tpm_config_t *config) +{ + assert(config); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the module clock */ + CLOCK_EnableClock(s_tpmClocks[TPM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_TPM_HAS_GLOBAL) && FSL_FEATURE_TPM_HAS_GLOBAL + /* TPM reset is available on certain SoC's */ + TPM_Reset(base); +#endif + + /* Set the clock prescale factor */ + base->SC = TPM_SC_PS(config->prescale); + + /* Setup the counter operation */ + base->CONF = TPM_CONF_DOZEEN(config->enableDoze) | TPM_CONF_GTBEEN(config->useGlobalTimeBase) | + TPM_CONF_CROT(config->enableReloadOnTrigger) | TPM_CONF_CSOT(config->enableStartOnTrigger) | + TPM_CONF_CSOO(config->enableStopOnOverflow) | +#if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER + TPM_CONF_CPOT(config->enablePauseOnTrigger) | +#endif +#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION + TPM_CONF_TRGSRC(config->triggerSource) | +#endif + TPM_CONF_TRGSEL(config->triggerSelect); + if (config->enableDebugMode) + { + base->CONF |= TPM_CONF_DBGMODE_MASK; + } + else + { + base->CONF &= ~TPM_CONF_DBGMODE_MASK; + } +} + +void TPM_Deinit(TPM_Type *base) +{ + /* Stop the counter */ + base->SC &= ~TPM_SC_CMOD_MASK; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the TPM clock */ + CLOCK_DisableClock(s_tpmClocks[TPM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void TPM_GetDefaultConfig(tpm_config_t *config) +{ + assert(config); + + /* TPM clock divide by 1 */ + config->prescale = kTPM_Prescale_Divide_1; + /* Use internal TPM counter as timebase */ + config->useGlobalTimeBase = false; + /* TPM counter continues in doze mode */ + config->enableDoze = false; + /* TPM counter pauses when in debug mode */ + config->enableDebugMode = false; + /* TPM counter will not be reloaded on input trigger */ + config->enableReloadOnTrigger = false; + /* TPM counter continues running after overflow */ + config->enableStopOnOverflow = false; + /* TPM counter starts immediately once it is enabled */ + config->enableStartOnTrigger = false; +#if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER + config->enablePauseOnTrigger = false; +#endif + /* Choose trigger select 0 as input trigger for controlling counter operation */ + config->triggerSelect = kTPM_Trigger_Select_0; +#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION + /* Choose external trigger source to control counter operation */ + config->triggerSource = kTPM_TriggerSource_External; +#endif +} + +status_t TPM_SetupPwm(TPM_Type *base, + const tpm_chnl_pwm_signal_param_t *chnlParams, + uint8_t numOfChnls, + tpm_pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz) +{ + assert(chnlParams); + assert(pwmFreq_Hz); + assert(numOfChnls); + assert(srcClock_Hz); +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE + if(mode == kTPM_CombinedPwm) + { + assert(FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base)); + } +#endif + + uint32_t mod; + uint32_t tpmClock = (srcClock_Hz / (1U << (base->SC & TPM_SC_PS_MASK))); + uint16_t cnv; + uint8_t i; + +#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL + /* The TPM's QDCTRL register required to be effective */ + if( FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base) ) + { + /* Clear quadrature Decoder mode because in quadrature Decoder mode PWM doesn't operate*/ + base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK; + } +#endif + + switch (mode) + { + case kTPM_EdgeAlignedPwm: +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE + case kTPM_CombinedPwm: +#endif + base->SC &= ~TPM_SC_CPWMS_MASK; + mod = (tpmClock / pwmFreq_Hz) - 1; + break; + case kTPM_CenterAlignedPwm: + base->SC |= TPM_SC_CPWMS_MASK; + mod = tpmClock / (pwmFreq_Hz * 2); + break; + default: + return kStatus_Fail; + } + + /* Return an error in case we overflow the registers, probably would require changing + * clock source to get the desired frequency */ + if (mod > 65535U) + { + return kStatus_Fail; + } + /* Set the PWM period */ + base->MOD = mod; + + /* Setup each TPM channel */ + for (i = 0; i < numOfChnls; i++) + { + /* Return error if requested dutycycle is greater than the max allowed */ + if (chnlParams->dutyCyclePercent > 100) + { + return kStatus_Fail; + } +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE + if (mode == kTPM_CombinedPwm) + { + uint16_t cnvFirstEdge; + + /* This check is added for combined mode as the channel number should be the pair number */ + if (chnlParams->chnlNumber >= (FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2)) + { + return kStatus_Fail; + } + + /* Return error if requested value is greater than the max allowed */ + if (chnlParams->firstEdgeDelayPercent > 100) + { + return kStatus_Fail; + } + /* Configure delay of the first edge */ + if (chnlParams->firstEdgeDelayPercent == 0) + { + /* No delay for the first edge */ + cnvFirstEdge = 0; + } + else + { + cnvFirstEdge = (mod * chnlParams->firstEdgeDelayPercent) / 100; + } + /* Configure dutycycle */ + if (chnlParams->dutyCyclePercent == 0) + { + /* Signal stays low */ + cnv = 0; + cnvFirstEdge = 0; + } + else + { + cnv = (mod * chnlParams->dutyCyclePercent) / 100; + /* For 100% duty cycle */ + if (cnv >= mod) + { + cnv = mod + 1; + } + } + + /* Set the combine bit for the channel pair */ + base->COMBINE |= (1U << (TPM_COMBINE_COMBINE0_SHIFT + (TPM_COMBINE_SHIFT * chnlParams->chnlNumber))); + + /* When switching mode, disable channel n first */ + base->CONTROLS[chnlParams->chnlNumber * 2].CnSC &= + ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + + /* Wait till mode change to disable channel is acknowledged */ + while ((base->CONTROLS[chnlParams->chnlNumber * 2].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } + + /* Set the requested PWM mode for channel n, PWM output requires mode select to be set to 2 */ + base->CONTROLS[chnlParams->chnlNumber * 2].CnSC |= + ((chnlParams->level << TPM_CnSC_ELSA_SHIFT) | (2U << TPM_CnSC_MSA_SHIFT)); + + /* Wait till mode change is acknowledged */ + while (!(base->CONTROLS[chnlParams->chnlNumber * 2].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } + /* Set the channel pair values */ + base->CONTROLS[chnlParams->chnlNumber * 2].CnV = cnvFirstEdge; + + /* When switching mode, disable channel n + 1 first */ + base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC &= + ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + + /* Wait till mode change to disable channel is acknowledged */ + while ((base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } + + /* Set the requested PWM mode for channel n + 1, PWM output requires mode select to be set to 2 */ + base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC |= + ((chnlParams->level << TPM_CnSC_ELSA_SHIFT) | (2U << TPM_CnSC_MSA_SHIFT)); + + /* Wait till mode change is acknowledged */ + while (!(base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } + /* Set the channel pair values */ + base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv; + } + else + { +#endif + if (chnlParams->dutyCyclePercent == 0) + { + /* Signal stays low */ + cnv = 0; + } + else + { + cnv = (mod * chnlParams->dutyCyclePercent) / 100; + /* For 100% duty cycle */ + if (cnv >= mod) + { + cnv = mod + 1; + } + } + + /* When switching mode, disable channel first */ + base->CONTROLS[chnlParams->chnlNumber].CnSC &= + ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + + /* Wait till mode change to disable channel is acknowledged */ + while ((base->CONTROLS[chnlParams->chnlNumber].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } + + /* Set the requested PWM mode, PWM output requires mode select to be set to 2 */ + base->CONTROLS[chnlParams->chnlNumber].CnSC |= + ((chnlParams->level << TPM_CnSC_ELSA_SHIFT) | (2U << TPM_CnSC_MSA_SHIFT)); + + /* Wait till mode change is acknowledged */ + while (!(base->CONTROLS[chnlParams->chnlNumber].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } + base->CONTROLS[chnlParams->chnlNumber].CnV = cnv; +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE + } +#endif + + chnlParams++; + } + + return kStatus_Success; +} + +void TPM_UpdatePwmDutycycle(TPM_Type *base, + tpm_chnl_t chnlNumber, + tpm_pwm_mode_t currentPwmMode, + uint8_t dutyCyclePercent) +{ + assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base)); +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE + if(currentPwmMode == kTPM_CombinedPwm) + { + assert(FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base)); + } +#endif + + uint16_t cnv, mod; + + mod = base->MOD; +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE + if (currentPwmMode == kTPM_CombinedPwm) + { + uint16_t cnvFirstEdge; + + /* This check is added for combined mode as the channel number should be the pair number */ + if (chnlNumber >= (FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2)) + { + return; + } + cnv = (mod * dutyCyclePercent) / 100; + cnvFirstEdge = base->CONTROLS[chnlNumber * 2].CnV; + /* For 100% duty cycle */ + if (cnv >= mod) + { + cnv = mod + 1; + } + base->CONTROLS[(chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv; + } + else + { +#endif + cnv = (mod * dutyCyclePercent) / 100; + /* For 100% duty cycle */ + if (cnv >= mod) + { + cnv = mod + 1; + } + base->CONTROLS[chnlNumber].CnV = cnv; +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE + } +#endif +} + +void TPM_UpdateChnlEdgeLevelSelect(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t level) +{ + assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base)); + + uint32_t reg = base->CONTROLS[chnlNumber].CnSC & ~(TPM_CnSC_CHF_MASK); + + /* When switching mode, disable channel first */ + base->CONTROLS[chnlNumber].CnSC &= + ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + + /* Wait till mode change to disable channel is acknowledged */ + while ((base->CONTROLS[chnlNumber].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } + + /* Clear the field and write the new level value */ + reg &= ~(TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + reg |= ((uint32_t)level << TPM_CnSC_ELSA_SHIFT) & (TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + + base->CONTROLS[chnlNumber].CnSC = reg; + + /* Wait till mode change is acknowledged */ + reg &= (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + while (reg != (base->CONTROLS[chnlNumber].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } +} + +void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capture_edge_t captureMode) +{ + assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base)); + +#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL + /* The TPM's QDCTRL register required to be effective */ + if( FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base) ) + { + /* Clear quadrature Decoder mode for channel 0 or 1*/ + if ((chnlNumber == 0) || (chnlNumber == 1)) + { + base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK; + } + } +#endif + +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE + /* The TPM's COMBINE register required to be effective */ + if( FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base) ) + { + /* Clear the combine bit for chnlNumber */ + base->COMBINE &= ~(1U << TPM_COMBINE_SHIFT * (chnlNumber / 2)); + } +#endif + + /* When switching mode, disable channel first */ + base->CONTROLS[chnlNumber].CnSC &= + ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + + /* Wait till mode change to disable channel is acknowledged */ + while ((base->CONTROLS[chnlNumber].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } + + /* Set the requested input capture mode */ + base->CONTROLS[chnlNumber].CnSC |= captureMode; + + /* Wait till mode change is acknowledged */ + while (!(base->CONTROLS[chnlNumber].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } +} + +void TPM_SetupOutputCompare(TPM_Type *base, + tpm_chnl_t chnlNumber, + tpm_output_compare_mode_t compareMode, + uint32_t compareValue) +{ + assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base)); + +#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL + /* The TPM's QDCTRL register required to be effective */ + if( FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base) ) + { + /* Clear quadrature Decoder mode for channel 0 or 1 */ + if ((chnlNumber == 0) || (chnlNumber == 1)) + { + base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK; + } + } +#endif + + /* When switching mode, disable channel first */ + base->CONTROLS[chnlNumber].CnSC &= + ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + + /* Wait till mode change to disable channel is acknowledged */ + while ((base->CONTROLS[chnlNumber].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } + + /* Setup the channel output behaviour when a match occurs with the compare value */ + base->CONTROLS[chnlNumber].CnSC |= compareMode; + + /* Setup the compare value */ + base->CONTROLS[chnlNumber].CnV = compareValue; + + /* Wait till mode change is acknowledged */ + while (!(base->CONTROLS[chnlNumber].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } +} + +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE +void TPM_SetupDualEdgeCapture(TPM_Type *base, + tpm_chnl_t chnlPairNumber, + const tpm_dual_edge_capture_param_t *edgeParam, + uint32_t filterValue) +{ + assert(edgeParam); + assert(chnlPairNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2); + assert(FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base)); + + uint32_t reg; + +#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL + /* The TPM's QDCTRL register required to be effective */ + if( FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base) ) + { + /* Clear quadrature Decoder mode for channel 0 or 1*/ + if (chnlPairNumber == 0) + { + base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK; + } + } +#endif + + /* Unlock: When switching mode, disable channel first */ + base->CONTROLS[chnlPairNumber * 2].CnSC &= + ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + + /* Wait till mode change to disable channel is acknowledged */ + while ((base->CONTROLS[chnlPairNumber * 2].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } + + base->CONTROLS[chnlPairNumber * 2 + 1].CnSC &= + ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + + /* Wait till mode change to disable channel is acknowledged */ + while ((base->CONTROLS[chnlPairNumber * 2 + 1].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } + + /* Now, the registers for input mode can be operated. */ + if (edgeParam->enableSwap) + { + /* Set the combine and swap bits for the channel pair */ + base->COMBINE |= (TPM_COMBINE_COMBINE0_MASK | TPM_COMBINE_COMSWAP0_MASK) + << (TPM_COMBINE_SHIFT * chnlPairNumber); + + /* Input filter setup for channel n+1 input */ + reg = base->FILTER; + reg &= ~(TPM_FILTER_CH0FVAL_MASK << (TPM_FILTER_CH1FVAL_SHIFT * (chnlPairNumber + 1))); + reg |= (filterValue << (TPM_FILTER_CH1FVAL_SHIFT * (chnlPairNumber + 1))); + base->FILTER = reg; + } + else + { + reg = base->COMBINE; + /* Clear the swap bit for the channel pair */ + reg &= ~(TPM_COMBINE_COMSWAP0_MASK << (TPM_COMBINE_COMSWAP0_SHIFT * chnlPairNumber)); + + /* Set the combine bit for the channel pair */ + reg |= TPM_COMBINE_COMBINE0_MASK << (TPM_COMBINE_SHIFT * chnlPairNumber); + base->COMBINE = reg; + + /* Input filter setup for channel n input */ + reg = base->FILTER; + reg &= ~(TPM_FILTER_CH0FVAL_MASK << (TPM_FILTER_CH1FVAL_SHIFT * chnlPairNumber)); + reg |= (filterValue << (TPM_FILTER_CH1FVAL_SHIFT * chnlPairNumber)); + base->FILTER = reg; + } + + /* Setup the edge detection from channel n */ + base->CONTROLS[chnlPairNumber * 2].CnSC |= edgeParam->currChanEdgeMode; + + /* Wait till mode change is acknowledged */ + while (!(base->CONTROLS[chnlPairNumber * 2].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } + + /* Setup the edge detection from channel n+1 */ + base->CONTROLS[(chnlPairNumber * 2) + 1].CnSC |= edgeParam->nextChanEdgeMode; + + /* Wait till mode change is acknowledged */ + while (!(base->CONTROLS[(chnlPairNumber * 2) + 1].CnSC & + (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } +} +#endif + +#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL +void TPM_SetupQuadDecode(TPM_Type *base, + const tpm_phase_params_t *phaseAParams, + const tpm_phase_params_t *phaseBParams, + tpm_quad_decode_mode_t quadMode) +{ + assert(phaseAParams); + assert(phaseBParams); + assert(FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base)); + + base->CONTROLS[0].CnSC &= ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + + /* Wait till mode change to disable channel is acknowledged */ + while ((base->CONTROLS[0].CnSC & (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } + uint32_t reg; + + /* Set Phase A filter value */ + reg = base->FILTER; + reg &= ~(TPM_FILTER_CH0FVAL_MASK); + reg |= TPM_FILTER_CH0FVAL(phaseAParams->phaseFilterVal); + base->FILTER = reg; + +#if defined(FSL_FEATURE_TPM_HAS_POL) && FSL_FEATURE_TPM_HAS_POL + /* Set Phase A polarity */ + if (phaseAParams->phasePolarity) + { + base->POL |= TPM_POL_POL0_MASK; + } + else + { + base->POL &= ~TPM_POL_POL0_MASK; + } +#endif + + base->CONTROLS[1].CnSC &= ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); + + /* Wait till mode change to disable channel is acknowledged */ + while ((base->CONTROLS[1].CnSC & (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK))) + { + } + /* Set Phase B filter value */ + reg = base->FILTER; + reg &= ~(TPM_FILTER_CH1FVAL_MASK); + reg |= TPM_FILTER_CH1FVAL(phaseBParams->phaseFilterVal); + base->FILTER = reg; +#if defined(FSL_FEATURE_TPM_HAS_POL) && FSL_FEATURE_TPM_HAS_POL + /* Set Phase B polarity */ + if (phaseBParams->phasePolarity) + { + base->POL |= TPM_POL_POL1_MASK; + } + else + { + base->POL &= ~TPM_POL_POL1_MASK; + } +#endif + + /* Set Quadrature mode */ + reg = base->QDCTRL; + reg &= ~(TPM_QDCTRL_QUADMODE_MASK); + reg |= TPM_QDCTRL_QUADMODE(quadMode); + base->QDCTRL = reg; + + /* Enable Quad decode */ + base->QDCTRL |= TPM_QDCTRL_QUADEN_MASK; +} + +#endif + +void TPM_EnableInterrupts(TPM_Type *base, uint32_t mask) +{ + uint32_t chnlInterrupts = (mask & 0xFF); + uint8_t chnlNumber = 0; + + /* Enable the timer overflow interrupt */ + if (mask & kTPM_TimeOverflowInterruptEnable) + { + base->SC |= TPM_SC_TOIE_MASK; + } + + /* Enable the channel interrupts */ + while (chnlInterrupts) + { + if (chnlInterrupts & 0x1) + { + base->CONTROLS[chnlNumber].CnSC |= TPM_CnSC_CHIE_MASK; + } + chnlNumber++; + chnlInterrupts = chnlInterrupts >> 1U; + } +} + +void TPM_DisableInterrupts(TPM_Type *base, uint32_t mask) +{ + uint32_t chnlInterrupts = (mask & 0xFF); + uint8_t chnlNumber = 0; + + /* Disable the timer overflow interrupt */ + if (mask & kTPM_TimeOverflowInterruptEnable) + { + base->SC &= ~TPM_SC_TOIE_MASK; + } + + /* Disable the channel interrupts */ + while (chnlInterrupts) + { + if (chnlInterrupts & 0x1) + { + base->CONTROLS[chnlNumber].CnSC &= ~TPM_CnSC_CHIE_MASK; + } + chnlNumber++; + chnlInterrupts = chnlInterrupts >> 1U; + } +} + +uint32_t TPM_GetEnabledInterrupts(TPM_Type *base) +{ + uint32_t enabledInterrupts = 0; + int8_t chnlCount = FSL_FEATURE_TPM_CHANNEL_COUNTn(base); + + /* The CHANNEL_COUNT macro returns -1 if it cannot match the TPM instance */ + assert(chnlCount != -1); + + /* Check if timer overflow interrupt is enabled */ + if (base->SC & TPM_SC_TOIE_MASK) + { + enabledInterrupts |= kTPM_TimeOverflowInterruptEnable; + } + + /* Check if the channel interrupts are enabled */ + while (chnlCount > 0) + { + chnlCount--; + if (base->CONTROLS[chnlCount].CnSC & TPM_CnSC_CHIE_MASK) + { + enabledInterrupts |= (1U << chnlCount); + } + } + + return enabledInterrupts; +} diff --git a/source/hic_hal/freescale/kl27z/fsl_tpm.h b/source/hic_hal/freescale/kl27z/fsl_tpm.h new file mode 100644 index 000000000..5722a2bf3 --- /dev/null +++ b/source/hic_hal/freescale/kl27z/fsl_tpm.h @@ -0,0 +1,630 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_TPM_H_ +#define _FSL_TPM_H_ + +#include "fsl_common.h" +#include "fsl_clock.h" + +/*! + * @addtogroup tpm + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_TPM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */ +/*@}*/ + +/*! + * @brief List of TPM channels. + * @note Actual number of available channels is SoC dependent + */ +typedef enum _tpm_chnl +{ + kTPM_Chnl_0 = 0U, /*!< TPM channel number 0*/ + kTPM_Chnl_1, /*!< TPM channel number 1 */ + kTPM_Chnl_2, /*!< TPM channel number 2 */ + kTPM_Chnl_3, /*!< TPM channel number 3 */ + kTPM_Chnl_4, /*!< TPM channel number 4 */ + kTPM_Chnl_5, /*!< TPM channel number 5 */ + kTPM_Chnl_6, /*!< TPM channel number 6 */ + kTPM_Chnl_7 /*!< TPM channel number 7 */ +} tpm_chnl_t; + +/*! @brief TPM PWM operation modes */ +typedef enum _tpm_pwm_mode +{ + kTPM_EdgeAlignedPwm = 0U, /*!< Edge aligned PWM */ + kTPM_CenterAlignedPwm, /*!< Center aligned PWM */ +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE + kTPM_CombinedPwm /*!< Combined PWM */ +#endif +} tpm_pwm_mode_t; + +/*! @brief TPM PWM output pulse mode: high-true, low-true or no output */ +typedef enum _tpm_pwm_level_select +{ + kTPM_NoPwmSignal = 0U, /*!< No PWM output on pin */ + kTPM_LowTrue, /*!< Low true pulses */ + kTPM_HighTrue /*!< High true pulses */ +} tpm_pwm_level_select_t; + +/*! @brief Options to configure a TPM channel's PWM signal */ +typedef struct _tpm_chnl_pwm_signal_param +{ + tpm_chnl_t chnlNumber; /*!< TPM channel to configure. + In combined mode (available in some SoC's, this represents the + channel pair number */ + tpm_pwm_level_select_t level; /*!< PWM output active level select */ + uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 + 0=inactive signal(0% duty cycle)... + 100=always active signal (100% duty cycle)*/ +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE + uint8_t firstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate asymmetrical PWM. + Specifies the delay to the first edge in a PWM period. + If unsure, leave as 0; Should be specified as + percentage of the PWM period */ +#endif +} tpm_chnl_pwm_signal_param_t; + +/*! + * @brief Trigger options available. + * + * This is used for both internal & external trigger sources (external option available in certain SoC's) + * + * @note The actual trigger options available is SoC-specific. + */ +typedef enum _tpm_trigger_select +{ + kTPM_Trigger_Select_0 = 0U, + kTPM_Trigger_Select_1, + kTPM_Trigger_Select_2, + kTPM_Trigger_Select_3, + kTPM_Trigger_Select_4, + kTPM_Trigger_Select_5, + kTPM_Trigger_Select_6, + kTPM_Trigger_Select_7, + kTPM_Trigger_Select_8, + kTPM_Trigger_Select_9, + kTPM_Trigger_Select_10, + kTPM_Trigger_Select_11, + kTPM_Trigger_Select_12, + kTPM_Trigger_Select_13, + kTPM_Trigger_Select_14, + kTPM_Trigger_Select_15 +} tpm_trigger_select_t; + +#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION +/*! + * @brief Trigger source options available + * + * @note This selection is available only on some SoC's. For SoC's without this selection, the only + * trigger source available is internal triger. + */ +typedef enum _tpm_trigger_source +{ + kTPM_TriggerSource_External = 0U, /*!< Use external trigger input */ + kTPM_TriggerSource_Internal /*!< Use internal trigger */ +} tpm_trigger_source_t; +#endif + +/*! @brief TPM output compare modes */ +typedef enum _tpm_output_compare_mode +{ + kTPM_NoOutputSignal = (1U << TPM_CnSC_MSA_SHIFT), /*!< No channel output when counter reaches CnV */ + kTPM_ToggleOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (1U << TPM_CnSC_ELSA_SHIFT)), /*!< Toggle output */ + kTPM_ClearOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (2U << TPM_CnSC_ELSA_SHIFT)), /*!< Clear output */ + kTPM_SetOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (3U << TPM_CnSC_ELSA_SHIFT)), /*!< Set output */ + kTPM_HighPulseOutput = ((3U << TPM_CnSC_MSA_SHIFT) | (1U << TPM_CnSC_ELSA_SHIFT)), /*!< Pulse output high */ + kTPM_LowPulseOutput = ((3U << TPM_CnSC_MSA_SHIFT) | (2U << TPM_CnSC_ELSA_SHIFT)) /*!< Pulse output low */ +} tpm_output_compare_mode_t; + +/*! @brief TPM input capture edge */ +typedef enum _tpm_input_capture_edge +{ + kTPM_RisingEdge = (1U << TPM_CnSC_ELSA_SHIFT), /*!< Capture on rising edge only */ + kTPM_FallingEdge = (2U << TPM_CnSC_ELSA_SHIFT), /*!< Capture on falling edge only */ + kTPM_RiseAndFallEdge = (3U << TPM_CnSC_ELSA_SHIFT) /*!< Capture on rising or falling edge */ +} tpm_input_capture_edge_t; + +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE +/*! + * @brief TPM dual edge capture parameters + * + * @note This mode is available only on some SoC's. + */ +typedef struct _tpm_dual_edge_capture_param +{ + bool enableSwap; /*!< true: Use channel n+1 input, channel n input is ignored; + false: Use channel n input, channel n+1 input is ignored */ + tpm_input_capture_edge_t currChanEdgeMode; /*!< Input capture edge select for channel n */ + tpm_input_capture_edge_t nextChanEdgeMode; /*!< Input capture edge select for channel n+1 */ +} tpm_dual_edge_capture_param_t; +#endif + +#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL +/*! + * @brief TPM quadrature decode modes + * + * @note This mode is available only on some SoC's. + */ +typedef enum _tpm_quad_decode_mode +{ + kTPM_QuadPhaseEncode = 0U, /*!< Phase A and Phase B encoding mode */ + kTPM_QuadCountAndDir /*!< Count and direction encoding mode */ +} tpm_quad_decode_mode_t; + +/*! @brief TPM quadrature phase polarities */ +typedef enum _tpm_phase_polarity +{ + kTPM_QuadPhaseNormal = 0U, /*!< Phase input signal is not inverted */ + kTPM_QuadPhaseInvert /*!< Phase input signal is inverted */ +} tpm_phase_polarity_t; + +/*! @brief TPM quadrature decode phase parameters */ +typedef struct _tpm_phase_param +{ + uint32_t phaseFilterVal; /*!< Filter value, filter is disabled when the value is zero */ + tpm_phase_polarity_t phasePolarity; /*!< Phase polarity */ +} tpm_phase_params_t; +#endif + +/*! @brief TPM clock source selection*/ +typedef enum _tpm_clock_source +{ + kTPM_SystemClock = 1U, /*!< System clock */ + kTPM_ExternalClock /*!< External clock */ +} tpm_clock_source_t; + +/*! @brief TPM prescale value selection for the clock source*/ +typedef enum _tpm_clock_prescale +{ + kTPM_Prescale_Divide_1 = 0U, /*!< Divide by 1 */ + kTPM_Prescale_Divide_2, /*!< Divide by 2 */ + kTPM_Prescale_Divide_4, /*!< Divide by 4 */ + kTPM_Prescale_Divide_8, /*!< Divide by 8 */ + kTPM_Prescale_Divide_16, /*!< Divide by 16 */ + kTPM_Prescale_Divide_32, /*!< Divide by 32 */ + kTPM_Prescale_Divide_64, /*!< Divide by 64 */ + kTPM_Prescale_Divide_128 /*!< Divide by 128 */ +} tpm_clock_prescale_t; + +/*! + * @brief TPM config structure + * + * This structure holds the configuration settings for the TPM peripheral. To initialize this + * structure to reasonable defaults, call the TPM_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _tpm_config +{ + tpm_clock_prescale_t prescale; /*!< Select TPM clock prescale value */ + bool useGlobalTimeBase; /*!< true: Use of an external global time base is enabled; + false: disabled */ + tpm_trigger_select_t triggerSelect; /*!< Input trigger to use for controlling the counter operation */ +#if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION + tpm_trigger_source_t triggerSource; /*!< Decides if we use external or internal trigger. */ +#endif + bool enableDoze; /*!< true: TPM counter is paused in doze mode; + false: TPM counter continues in doze mode */ + bool enableDebugMode; /*!< true: TPM counter continues in debug mode; + false: TPM counter is paused in debug mode */ + bool enableReloadOnTrigger; /*!< true: TPM counter is reloaded on trigger; + false: TPM counter not reloaded */ + bool enableStopOnOverflow; /*!< true: TPM counter stops after overflow; + false: TPM counter continues running after overflow */ + bool enableStartOnTrigger; /*!< true: TPM counter only starts when a trigger is detected; + false: TPM counter starts immediately */ +#if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER + bool enablePauseOnTrigger; /*!< true: TPM counter will pause while trigger remains asserted; + false: TPM counter continues running */ +#endif +} tpm_config_t; + +/*! @brief List of TPM interrupts */ +typedef enum _tpm_interrupt_enable +{ + kTPM_Chnl0InterruptEnable = (1U << 0), /*!< Channel 0 interrupt.*/ + kTPM_Chnl1InterruptEnable = (1U << 1), /*!< Channel 1 interrupt.*/ + kTPM_Chnl2InterruptEnable = (1U << 2), /*!< Channel 2 interrupt.*/ + kTPM_Chnl3InterruptEnable = (1U << 3), /*!< Channel 3 interrupt.*/ + kTPM_Chnl4InterruptEnable = (1U << 4), /*!< Channel 4 interrupt.*/ + kTPM_Chnl5InterruptEnable = (1U << 5), /*!< Channel 5 interrupt.*/ + kTPM_Chnl6InterruptEnable = (1U << 6), /*!< Channel 6 interrupt.*/ + kTPM_Chnl7InterruptEnable = (1U << 7), /*!< Channel 7 interrupt.*/ + kTPM_TimeOverflowInterruptEnable = (1U << 8) /*!< Time overflow interrupt.*/ +} tpm_interrupt_enable_t; + +/*! @brief List of TPM flags */ +typedef enum _tpm_status_flags +{ + kTPM_Chnl0Flag = (1U << 0), /*!< Channel 0 flag */ + kTPM_Chnl1Flag = (1U << 1), /*!< Channel 1 flag */ + kTPM_Chnl2Flag = (1U << 2), /*!< Channel 2 flag */ + kTPM_Chnl3Flag = (1U << 3), /*!< Channel 3 flag */ + kTPM_Chnl4Flag = (1U << 4), /*!< Channel 4 flag */ + kTPM_Chnl5Flag = (1U << 5), /*!< Channel 5 flag */ + kTPM_Chnl6Flag = (1U << 6), /*!< Channel 6 flag */ + kTPM_Chnl7Flag = (1U << 7), /*!< Channel 7 flag */ + kTPM_TimeOverflowFlag = (1U << 8) /*!< Time overflow flag */ +} tpm_status_flags_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the TPM clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the TPM driver. + * + * @param base TPM peripheral base address + * @param config Pointer to user's TPM config structure. + */ +void TPM_Init(TPM_Type *base, const tpm_config_t *config); + +/*! + * @brief Stops the counter and gates the TPM clock + * + * @param base TPM peripheral base address + */ +void TPM_Deinit(TPM_Type *base); + +/*! + * @brief Fill in the TPM config struct with the default settings + * + * The default values are: + * @code + * config->prescale = kTPM_Prescale_Divide_1; + * config->useGlobalTimeBase = false; + * config->dozeEnable = false; + * config->dbgMode = false; + * config->enableReloadOnTrigger = false; + * config->enableStopOnOverflow = false; + * config->enableStartOnTrigger = false; + *#if FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER + * config->enablePauseOnTrigger = false; + *#endif + * config->triggerSelect = kTPM_Trigger_Select_0; + *#if FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION + * config->triggerSource = kTPM_TriggerSource_External; + *#endif + * @endcode + * @param config Pointer to user's TPM config structure. + */ +void TPM_GetDefaultConfig(tpm_config_t *config); + +/*! @}*/ + +/*! + * @name Channel mode operations + * @{ + */ + +/*! + * @brief Configures the PWM signal parameters + * + * User calls this function to configure the PWM signals period, mode, dutycycle and edge. Use this + * function to configure all the TPM channels that will be used to output a PWM signal + * + * @param base TPM peripheral base address + * @param chnlParams Array of PWM channel parameters to configure the channel(s) + * @param numOfChnls Number of channels to configure, this should be the size of the array passed in + * @param mode PWM operation mode, options available in enumeration ::tpm_pwm_mode_t + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz TPM counter clock in Hz + * + * @return kStatus_Success if the PWM setup was successful, + * kStatus_Error on failure + */ +status_t TPM_SetupPwm(TPM_Type *base, + const tpm_chnl_pwm_signal_param_t *chnlParams, + uint8_t numOfChnls, + tpm_pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz); + +/*! + * @brief Update the duty cycle of an active PWM signal + * + * @param base TPM peripheral base address + * @param chnlNumber The channel number. In combined mode, this represents + * the channel pair number + * @param currentPwmMode The current PWM mode set during PWM setup + * @param dutyCyclePercent New PWM pulse width, value should be between 0 to 100 + * 0=inactive signal(0% duty cycle)... + * 100=active signal (100% duty cycle) + */ +void TPM_UpdatePwmDutycycle(TPM_Type *base, + tpm_chnl_t chnlNumber, + tpm_pwm_mode_t currentPwmMode, + uint8_t dutyCyclePercent); + +/*! + * @brief Update the edge level selection for a channel + * + * @param base TPM peripheral base address + * @param chnlNumber The channel number + * @param level The level to be set to the ELSnB:ELSnA field; valid values are 00, 01, 10, 11. + * See the appropriate SoC reference manual for details about this field. + */ +void TPM_UpdateChnlEdgeLevelSelect(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t level); + +/*! + * @brief Enables capturing an input signal on the channel using the function parameters. + * + * When the edge specified in the captureMode argument occurs on the channel, the TPM counter is captured into + * the CnV register. The user has to read the CnV register separately to get this value. + * + * @param base TPM peripheral base address + * @param chnlNumber The channel number + * @param captureMode Specifies which edge to capture + */ +void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capture_edge_t captureMode); + +/*! + * @brief Configures the TPM to generate timed pulses. + * + * When the TPM counter matches the value of compareVal argument (this is written into CnV reg), the channel + * output is changed based on what is specified in the compareMode argument. + * + * @param base TPM peripheral base address + * @param chnlNumber The channel number + * @param compareMode Action to take on the channel output when the compare condition is met + * @param compareValue Value to be programmed in the CnV register. + */ +void TPM_SetupOutputCompare(TPM_Type *base, + tpm_chnl_t chnlNumber, + tpm_output_compare_mode_t compareMode, + uint32_t compareValue); + +#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE +/*! + * @brief Configures the dual edge capture mode of the TPM. + * + * This function allows to measure a pulse width of the signal on the input of channel of a + * channel pair. The filter function is disabled if the filterVal argument passed is zero. + * + * @param base TPM peripheral base address + * @param chnlPairNumber The TPM channel pair number; options are 0, 1, 2, 3 + * @param edgeParam Sets up the dual edge capture function + * @param filterValue Filter value, specify 0 to disable filter. + */ +void TPM_SetupDualEdgeCapture(TPM_Type *base, + tpm_chnl_t chnlPairNumber, + const tpm_dual_edge_capture_param_t *edgeParam, + uint32_t filterValue); +#endif + +#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL +/*! + * @brief Configures the parameters and activates the quadrature decode mode. + * + * @param base TPM peripheral base address + * @param phaseAParams Phase A configuration parameters + * @param phaseBParams Phase B configuration parameters + * @param quadMode Selects encoding mode used in quadrature decoder mode + */ +void TPM_SetupQuadDecode(TPM_Type *base, + const tpm_phase_params_t *phaseAParams, + const tpm_phase_params_t *phaseBParams, + tpm_quad_decode_mode_t quadMode); +#endif + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected TPM interrupts. + * + * @param base TPM peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::tpm_interrupt_enable_t + */ +void TPM_EnableInterrupts(TPM_Type *base, uint32_t mask); + +/*! + * @brief Disables the selected TPM interrupts. + * + * @param base TPM peripheral base address + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::tpm_interrupt_enable_t + */ +void TPM_DisableInterrupts(TPM_Type *base, uint32_t mask); + +/*! + * @brief Gets the enabled TPM interrupts. + * + * @param base TPM peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::tpm_interrupt_enable_t + */ +uint32_t TPM_GetEnabledInterrupts(TPM_Type *base); + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the TPM status flags + * + * @param base TPM peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::tpm_status_flags_t + */ +static inline uint32_t TPM_GetStatusFlags(TPM_Type *base) +{ + return base->STATUS; +} + +/*! + * @brief Clears the TPM status flags + * + * @param base TPM peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::tpm_status_flags_t + */ +static inline void TPM_ClearStatusFlags(TPM_Type *base, uint32_t mask) +{ + /* Clear the status flags */ + base->STATUS = mask; +} + +/*! @}*/ + +/*! + * @name Read and write the timer period + * @{ + */ + +/*! + * @brief Sets the timer period in units of ticks. + * + * Timers counts from 0 until it equals the count value set here. The count value is written to + * the MOD register. + * + * @note + * 1. This API allows the user to use the TPM module as a timer. Do not mix usage + * of this API with TPM's PWM setup API's. + * 2. Call the utility macros provided in the fsl_common.h to convert usec or msec to ticks. + * + * @param base TPM peripheral base address + * @param ticks A timer period in units of ticks, which should be equal or greater than 1. + */ +static inline void TPM_SetTimerPeriod(TPM_Type *base, uint32_t ticks) +{ + base->MOD = ticks; +} + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value in a range from 0 to a + * timer period. + * + * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec. + * + * @param base TPM peripheral base address + * + * @return The current counter value in ticks + */ +static inline uint32_t TPM_GetCurrentTimerCount(TPM_Type *base) +{ + return (uint32_t)((base->CNT & TPM_CNT_COUNT_MASK) >> TPM_CNT_COUNT_SHIFT); +} + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the TPM counter. + * + * + * @param base TPM peripheral base address + * @param clockSource TPM clock source; once clock source is set the counter will start running + */ +static inline void TPM_StartTimer(TPM_Type *base, tpm_clock_source_t clockSource) +{ + uint32_t reg = base->SC; + + reg &= ~(TPM_SC_CMOD_MASK); + reg |= TPM_SC_CMOD(clockSource); + base->SC = reg; +} + +/*! + * @brief Stops the TPM counter. + * + * @param base TPM peripheral base address + */ +static inline void TPM_StopTimer(TPM_Type *base) +{ + /* Set clock source to none to disable counter */ + base->SC &= ~(TPM_SC_CMOD_MASK); + + /* Wait till this reads as zero acknowledging the counter is disabled */ + while (base->SC & TPM_SC_CMOD_MASK) + { + } +} + +/*! @}*/ + +#if defined(FSL_FEATURE_TPM_HAS_GLOBAL) && FSL_FEATURE_TPM_HAS_GLOBAL +/*! + * @brief Performs a software reset on the TPM module. + * + * Reset all internal logic and registers, except the Global Register. Remains set until cleared by software.. + * + * @note TPM software reset is available on certain SoC's only + * + * @param base TPM peripheral base address + */ +static inline void TPM_Reset(TPM_Type *base) +{ + base->GLOBAL |= TPM_GLOBAL_RST_MASK; + base->GLOBAL &= ~TPM_GLOBAL_RST_MASK; +} +#endif + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_TPM_H_ */ diff --git a/source/hic_hal/freescale/kl27z/i2c.c b/source/hic_hal/freescale/kl27z/i2c.c new file mode 100644 index 000000000..264c108f3 --- /dev/null +++ b/source/hic_hal/freescale/kl27z/i2c.c @@ -0,0 +1,173 @@ +#include "i2c.h" +#include "fsl_i2c.h" +#include "fsl_clock.h" +#include "fsl_port.h" +#include "settings.h" // for config_get_overflow_detect + +/* I2C source clock */ +#define I2C_SLAVE_BASEADDR I2C1 +#define I2C_SLAVE_CLK_SRC I2C1_CLK_SRC +#define I2C_SLAVE_CLK_FREQ CLOCK_GetFreq(I2C1_CLK_SRC) + +#define I2C_MASTER_SLAVE_ADDR_7BIT 0x7AU +#define I2C_DATA_LENGTH (32U) + +// We'll start with 5 RX commands +#define RX_CMDS_LENGTH 5 +#define I2C_CMD_SLEEP 0xABU + +static void i2c_cmd_sleep_callback(void); + +typedef struct _cmd_callback { + uint8_t cmdValue; + void (*callback)(); +} cmd_callback_t; + +static cmd_callback_t i2cSleepCmd = { + .cmdValue = I2C_CMD_SLEEP, + .callback = i2c_cmd_sleep_callback, +}; + +static cmd_callback_t *rx_cmds[RX_CMDS_LENGTH]; + +static uint8_t g_slave_buff[I2C_DATA_LENGTH]; +static i2c_slave_handle_t g_s_handle; +static volatile bool g_SlaveCompletionFlag = false; +static volatile bool g_SlaveRxFlag = false; + +bool go_to_sleep = false; + + +static void i2c_cmd_sleep_callback() { + go_to_sleep = true; +} + +static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData) { + switch (xfer->event) + { + /* Address match event */ + case kI2C_SlaveAddressMatchEvent: + xfer->data = NULL; + xfer->dataSize = 0; + break; + /* Transmit request */ + case kI2C_SlaveTransmitEvent: + /* Update information for transmit process */ + for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++) { + g_slave_buff[i] = i; + } + xfer->data = g_slave_buff; + xfer->dataSize = I2C_DATA_LENGTH; + break; + + /* Receive request */ + case kI2C_SlaveReceiveEvent: + /* Update information for received process */ + // Hack: Default driver can't differentiate between RX or TX on + // completion event, so we set a flag here. Can't process more + // than I2C_DATA_LENGTH bytes on RX + memset(&g_slave_buff, 0, sizeof(g_slave_buff)); + xfer->data = g_slave_buff; + xfer->dataSize = I2C_DATA_LENGTH; + g_SlaveRxFlag = true; + break; + + /* Transfer done */ + case kI2C_SlaveCompletionEvent: + g_SlaveCompletionFlag = true; + xfer->data = NULL; + xfer->dataSize = 0; + + // Default driver couldn't differentiate between RX or TX completion + // Check flag set in kI2C_SlaveReceiveEvent + if (g_SlaveRxFlag) { + // Check all registered commands + for (uint8_t i = 0; i < RX_CMDS_LENGTH; i++) { + if (rx_cmds[i] != NULL && (g_slave_buff[0] == (rx_cmds[i])->cmdValue)) { + rx_cmds[i]->callback(); + } + } + } + g_SlaveRxFlag = false; + break; + + default: + g_SlaveCompletionFlag = false; + break; + } +} + +static void i2c_init_pins(void) { + /* Port C Clock Gate Control: Clock enabled */ + CLOCK_EnableClock(kCLOCK_PortC); + + /* PORTC1 is configured as I2C1_SCL */ + PORT_SetPinMux(PORTC, 1U, kPORT_MuxAlt2); + + PORTC->PCR[1] = ((PORTC->PCR[1] & + /* Mask bits to zero which are setting */ + (~(PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK))) + + /* Pull Enable: Internal pullup or pulldown resistor is enabled on the corresponding pin. */ + | (uint32_t)(PORT_PCR_PE_MASK)); + + /* PORTC2 is configured as I2C1_SDA */ + PORT_SetPinMux(PORTC, 2U, kPORT_MuxAlt2); + + PORTC->PCR[2] = ((PORTC->PCR[2] & + /* Mask bits to zero which are setting */ + (~(PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK))) + + /* Pull Enable: Internal pullup or pulldown resistor is enabled on the corresponding pin. */ + | (uint32_t)(PORT_PCR_PE_MASK)); +} + +static int32_t i2c_start_transfer(void) { + memset(&g_slave_buff, 0, sizeof(g_slave_buff)); + memset(&g_s_handle, 0, sizeof(g_s_handle)); + + I2C_SlaveTransferCreateHandle(I2C_SLAVE_BASEADDR, &g_s_handle, + i2c_slave_callback, NULL); + + /* Set up slave transfer. */ + I2C_SlaveTransferNonBlocking(I2C_SLAVE_BASEADDR, &g_s_handle, + kI2C_SlaveCompletionEvent | kI2C_SlaveAddressMatchEvent); + + return 1; +} + +static status_t i2c_slave_register_cmd_callback(cmd_callback_t *cmdCalback) { + for (uint8_t i = 0; i < RX_CMDS_LENGTH; i++) { + if (rx_cmds[i] == NULL) { + rx_cmds[i] = cmdCalback; + return kStatus_Success; + } + } + return kStatus_Fail; +} + +int32_t i2c_initialize(void) { + i2c_slave_config_t slaveConfig; + + i2c_init_pins(); + + status_t cmd_register_status = i2c_slave_register_cmd_callback(&i2cSleepCmd); + + I2C_SlaveGetDefaultConfig(&slaveConfig); + + slaveConfig.addressingMode = kI2C_Address7bit; + slaveConfig.slaveAddress = I2C_MASTER_SLAVE_ADDR_7BIT; + slaveConfig.enableWakeUp = true; + + I2C_SlaveInit(I2C_SLAVE_BASEADDR, &slaveConfig, I2C_SLAVE_CLK_FREQ); + + i2c_start_transfer(); + + return 1; +} + +int32_t i2c_deinitialize(void) { + I2C_SlaveDeinit(I2C_SLAVE_BASEADDR); + return 1; +} + diff --git a/source/hic_hal/freescale/kl27z/i2c.h b/source/hic_hal/freescale/kl27z/i2c.h new file mode 100644 index 000000000..e5177a782 --- /dev/null +++ b/source/hic_hal/freescale/kl27z/i2c.h @@ -0,0 +1,14 @@ +/* + * i2c.h + * + */ + +#ifndef I2C_H_ +#define I2C_H_ + +#include "fsl_common.h" + +int32_t i2c_initialize(void); +int32_t i2c_deinitialize(void); + +#endif /* I2C_H_ */ From 27dc59a26e459d4f8947bb33a35af75313f701b2 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Fri, 21 Aug 2020 14:06:13 -0500 Subject: [PATCH 214/617] Sync latest features including: -build filesystem hook for error blob app and DATA.BIN file creation -Added microbit custom BL project for custom URL in HELP_FAQ.HTM -I2C comms and flash interface -SWD clock speed improvements --- projects.yaml | 4 + records/board/kl27z_microbit_bl.yaml | 4 + records/board/microbitv2.yaml | 3 + source/board/kl27z_microbit_bl.c | 64 +++ source/board/microbitv2/IO_Config_Override.h | 14 +- source/board/microbitv2/i2c_commands.h | 147 ++++++ source/board/microbitv2/led_error_app.h | 179 ++++++++ source/board/microbitv2/microbitv2.c | 425 +++++++++++++++++- source/daplink/cmsis-dap/DAP.c | 21 +- source/daplink/drag-n-drop/flash_decoder.c | 11 +- source/daplink/drag-n-drop/vfs_user.c | 4 + source/hic_hal/freescale/kl27z/DAP_config.h | 2 +- .../kl27z/{fsl_i2c.c => fsl_i2c_mod.c} | 13 + source/hic_hal/freescale/kl27z/i2c.c | 140 ++++-- source/hic_hal/freescale/kl27z/i2c.h | 22 + 15 files changed, 977 insertions(+), 76 deletions(-) create mode 100644 records/board/kl27z_microbit_bl.yaml create mode 100644 source/board/kl27z_microbit_bl.c create mode 100644 source/board/microbitv2/i2c_commands.h create mode 100644 source/board/microbitv2/led_error_app.h rename source/hic_hal/freescale/kl27z/{fsl_i2c.c => fsl_i2c_mod.c} (99%) diff --git a/projects.yaml b/projects.yaml index 7367e1c8f..8f8cf4e88 100644 --- a/projects.yaml +++ b/projects.yaml @@ -99,6 +99,10 @@ projects: - *module_if - *module_hic_kl27z - records/family/all_family.yaml + kl27z_microbit_bl: + - *module_bl + - records/hic_hal/kl27z.yaml + - records/board/kl27z_microbit_bl.yaml k20dx_bl: - *module_bl - records/hic_hal/k20dx.yaml diff --git a/records/board/kl27z_microbit_bl.yaml b/records/board/kl27z_microbit_bl.yaml new file mode 100644 index 000000000..02a2ed9b3 --- /dev/null +++ b/records/board/kl27z_microbit_bl.yaml @@ -0,0 +1,4 @@ +common: + sources: + board: + - source/board/kl27z_microbit_bl.c diff --git a/records/board/microbitv2.yaml b/records/board/microbitv2.yaml index 1a67ccbef..7158e7f47 100644 --- a/records/board/microbitv2.yaml +++ b/records/board/microbitv2.yaml @@ -5,6 +5,9 @@ common: - MSC_LED_DEF=GPIO_LED_ON - USB_PROD_STR="BBC micro:bit CMSIS-DAP" - IO_CONFIG_OVERRIDE + - DELAY_FAST_CYCLES=2U + includes: + - source/board/microbitv2 sources: board: - source/board/microbitv2/ diff --git a/source/board/kl27z_microbit_bl.c b/source/board/kl27z_microbit_bl.c new file mode 100644 index 000000000..f2cf061d8 --- /dev/null +++ b/source/board/kl27z_microbit_bl.c @@ -0,0 +1,64 @@ +/** + * @file kl27z_microbit_bl.c + * @brief board ID and meta-data for the hardware interface circuit (HIC) based on the NXP KL27Z + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_config.h" +#include "daplink_addr.h" +#include "compiler.h" +#include "target_board.h" +#include "target_family.h" + +// Warning - changing the interface start will break backwards compatibility +COMPILER_ASSERT(DAPLINK_ROM_IF_START == KB(32)); +COMPILER_ASSERT(DAPLINK_ROM_IF_SIZE == (KB(128) - KB(32) - KB(1))); + +/** +* List of start and size for each size of flash sector +* The size will apply to all sectors between the listed address and the next address +* in the list. +* The last pair in the list will have sectors starting at that address and ending +* at address start + size. +*/ +static const sector_info_t sectors_info[] = { + {DAPLINK_ROM_IF_START, 1024}, + }; + +// kl26z128 target information +target_cfg_t target_device = { + .sectors_info = sectors_info, + .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), + .flash_regions[0].start = DAPLINK_ROM_IF_START, + .flash_regions[0].end = DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE, + .flash_regions[0].flags = kRegionIsDefault, + .ram_regions[0].start = 0x1FFFE000, + .ram_regions[0].end = 0x20006000, +}; + +//bootloader has no family +const target_family_descriptor_t *g_target_family = NULL; + +const board_info_t g_board_info = { + .info_version = kBoardInfoVersion, + .board_id = "0000", + .daplink_url_name = "HELP_FAQHTM", + .daplink_drive_name = "MAINTENANCE", + .daplink_target_url = "https://microbit.org/device/?id=@B&v=@V&bl=1", + .target_cfg = &target_device, +}; diff --git a/source/board/microbitv2/IO_Config_Override.h b/source/board/microbitv2/IO_Config_Override.h index df08e214a..2668ab62a 100644 --- a/source/board/microbitv2/IO_Config_Override.h +++ b/source/board/microbitv2/IO_Config_Override.h @@ -123,10 +123,11 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_KL27Z); #define PIN_RED_LED (1< + +#include "cmsis_compiler.h" +#include "virtual_fs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*! i2c command Id type enumeration */ +typedef enum cmdId_tag { + gReadRequest_c = 0x10, + gReadResponse_c = 0x11, + gWriteRequest_c = 0x12, + gWriteResponse_c = 0x13, + gErrorResponse_c = 0x20 +} cmdId_t; + +/*! property Id type enumeration */ +typedef enum propertyId_tag { + gDAPLinkBoardVersion_c = 0x01, + gI2CProtocolVersion_c = 0x02, + gDAPLinkVersion_c = 0x03, + gPowerState_c = 0x04, + gPowerConsumption_c = 0x05, + gUSBEnumerationState_c = 0x06, + gPowerMode_c = 0x07, + gNRFPowerMode_c = 0x08 +} propertyId_t; + +/*! property Id type enumeration */ +typedef enum errorCode_tag { + gErrorSuccess = 0x30, + gErrorIncompleteCommand_c = 0x31, + gErrorUnknownCommand_c = 0x32, + gErrorCommandDisallowed_c = 0x33, + gErrorUnknownProperty_c = 0x34, + gErrorWrongPropertySize_c = 0x35, + gErrorReadDisallowed_c = 0x36, + gErrorWriteDisallowed_c = 0x37, + gErrorWriteFail_c = 0x38 +} errorCode_t; + +typedef __PACKED_STRUCT readReqCmd_tag { + uint8_t propertyId; +} readReqCmd_t; + +#define MAX_PROPERTY_SIZE 8 + +typedef __PACKED_STRUCT readRspCmd_tag { + uint8_t propertyId; + uint8_t dataSize; + uint8_t data[MAX_PROPERTY_SIZE]; +} readRspCmd_t; + +typedef __PACKED_STRUCT writeReqCmd_tag { + uint8_t propertyId; + uint8_t dataSize; + uint8_t data[MAX_PROPERTY_SIZE]; +} writeReqCmd_t; + +typedef __PACKED_STRUCT writeRspCmd_tag { + uint8_t propertyId; +} writeRspCmd_t; + +typedef __PACKED_STRUCT errorRspCmd_tag { + uint8_t errorCode; +} errorRspCmd_t; + +/*! i2c command structure*/ +typedef __PACKED_STRUCT i2cCommand_tag { + uint8_t cmdId; + __PACKED_UNION { + readReqCmd_t readReqCmd; + readRspCmd_t readRspCmd; + writeReqCmd_t writeReqCmd; + writeRspCmd_t writeRspCmd; + errorRspCmd_t errorRspCmd; + } cmdData; +} i2cCommand_t; + +typedef __PACKED_STRUCT flashConfig_tag { + uint32_t key; // Magic key to indicate a valid record + vfs_filename_t fileName; + uint32_t fileSizeKB; + bool fileVisible; +} flashConfig_t; + +/*! Flash interface command type */ +typedef enum flashCmdId_tag { + gFlashCfgFileName_c = 0x01, + gFlashCfgFileSize_c = 0x02, + gFlashCfgFileVisible_c = 0x03, + gFlashCfgWrite_c = 0x04, + gFlashCfgErase_c = 0x05, + gFlashStorageSize_c = 0x06, + gFlashSectorSize_c = 0x07, + gFlashRemountMSD_c = 0x08, + gFlashStatus_c = 0x09, + gFlashDataRead_c = 0x0A, + gFlashDataWrite_c = 0x0B, + gFlashDataErase_c = 0x0C, + gFlashError_c = 0x20 +} flashCmdId_t; + +typedef __PACKED_STRUCT flashDataWriteCmd_tag { + uint8_t addr2; + uint8_t addr1; + uint8_t addr0; + uint32_t length; + uint8_t data[1024]; +} flashDataWriteCmd_t; + +typedef __PACKED_STRUCT flashDataEraseCmd_tag { + uint8_t sAddr2; + uint8_t sAddr1; + uint8_t sAddr0; + uint8_t pad; + uint8_t eAddr2; + uint8_t eAddr1; + uint8_t eAddr0; +} flashDataEraseCmd_t; + +/*! i2c command structure*/ +typedef __PACKED_STRUCT i2cFlashCmd_tag { + uint8_t cmdId; + __PACKED_UNION { + flashDataWriteCmd_t write; + flashDataWriteCmd_t read; + flashDataEraseCmd_t erase; + uint8_t data[1024]; + } cmdData; +} i2cFlashCmd_t; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/source/board/microbitv2/led_error_app.h b/source/board/microbitv2/led_error_app.h new file mode 100644 index 000000000..d5fd37d20 --- /dev/null +++ b/source/board/microbitv2/led_error_app.h @@ -0,0 +1,179 @@ +// Program to display error code 0-999 on LEDs: face,E,digit,digit,digit + +unsigned int led_error_bin_len = 2036; + +// Offset of 2 byte error code, low byte first +unsigned int led_error_bin_code = 1928; + +unsigned char led_error_bin_data[] = { + 0x00, 0x00, 0x02, 0x20, 0xb5, 0x02, 0x00, 0x00, 0xdd, 0x02, 0x00, 0x00, + 0xdf, 0x02, 0x00, 0x00, 0xe1, 0x02, 0x00, 0x00, 0xe3, 0x02, 0x00, 0x00, + 0xe5, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe7, 0x02, 0x00, 0x00, + 0xe9, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xeb, 0x02, 0x00, 0x00, + 0xed, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0xb5, 0x05, 0x4c, + 0x23, 0x78, 0x33, 0xb9, 0x04, 0x4b, 0x13, 0xb1, 0x04, 0x48, 0xaf, 0xf3, + 0x00, 0x80, 0x01, 0x23, 0x23, 0x70, 0x10, 0xbd, 0x74, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0x74, 0x07, 0x00, 0x00, 0x08, 0xb5, 0x03, 0x4b, + 0x1b, 0xb1, 0x03, 0x49, 0x03, 0x48, 0xaf, 0xf3, 0x00, 0x80, 0x08, 0xbd, + 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x20, 0x74, 0x07, 0x00, 0x00, + 0x15, 0x4b, 0x00, 0x2b, 0x08, 0xbf, 0x13, 0x4b, 0x9d, 0x46, 0xa3, 0xf5, + 0x80, 0x3a, 0x00, 0x21, 0x8b, 0x46, 0x0f, 0x46, 0x13, 0x48, 0x14, 0x4a, + 0x12, 0x1a, 0x00, 0xf0, 0x4f, 0xfa, 0x0f, 0x4b, 0x00, 0x2b, 0x00, 0xd0, + 0x98, 0x47, 0x0e, 0x4b, 0x00, 0x2b, 0x00, 0xd0, 0x98, 0x47, 0x00, 0x20, + 0x00, 0x21, 0x04, 0x00, 0x0d, 0x00, 0x0d, 0x48, 0x00, 0x28, 0x02, 0xd0, + 0x0c, 0x48, 0xaf, 0xf3, 0x00, 0x80, 0x00, 0xf0, 0x17, 0xfa, 0x20, 0x00, + 0x29, 0x00, 0x00, 0xf0, 0xf5, 0xf9, 0x00, 0xf0, 0xfd, 0xf9, 0x00, 0xbf, + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x20, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x74, 0x00, 0x00, 0x20, 0x90, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x49, 0x07, 0x4a, + 0x07, 0x4b, 0x9b, 0x1a, 0x03, 0xdd, 0x04, 0x3b, 0xc8, 0x58, 0xd0, 0x50, + 0xfb, 0xdc, 0x00, 0xf0, 0x2f, 0xf8, 0xff, 0xf7, 0xb9, 0xff, 0x00, 0x00, + 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x74, 0x00, 0x00, 0x20, + 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, + 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xbf, 0xf3, 0x4f, 0x8f, + 0x05, 0x49, 0x06, 0x4b, 0xca, 0x68, 0x02, 0xf4, 0xe0, 0x62, 0x13, 0x43, + 0xcb, 0x60, 0xbf, 0xf3, 0x4f, 0x8f, 0x00, 0xbf, 0xfd, 0xe7, 0x00, 0xbf, + 0x00, 0xed, 0x00, 0xe0, 0x04, 0x00, 0xfa, 0x05, 0x03, 0x4b, 0x18, 0x68, + 0xa0, 0xf1, 0x0d, 0x03, 0x58, 0x42, 0x58, 0x41, 0x70, 0x47, 0x00, 0xbf, + 0x30, 0x01, 0x00, 0x10, 0x08, 0xb5, 0xff, 0xf7, 0xf3, 0xff, 0x40, 0xb1, + 0x4f, 0xf0, 0x80, 0x43, 0x00, 0x22, 0xc3, 0xf8, 0x0c, 0x21, 0xc3, 0xf8, + 0x10, 0x21, 0xc3, 0xf8, 0x38, 0x25, 0xff, 0xf7, 0xe7, 0xff, 0x00, 0x28, + 0x46, 0xd0, 0x4f, 0xf0, 0x80, 0x52, 0x59, 0x4b, 0xd2, 0xf8, 0x04, 0x14, + 0xc3, 0xf8, 0x20, 0x15, 0xd2, 0xf8, 0x08, 0x14, 0xc3, 0xf8, 0x24, 0x15, + 0xd2, 0xf8, 0x0c, 0x14, 0xc3, 0xf8, 0x28, 0x15, 0xd2, 0xf8, 0x10, 0x14, + 0xc3, 0xf8, 0x2c, 0x15, 0xd2, 0xf8, 0x14, 0x14, 0xc3, 0xf8, 0x30, 0x15, + 0xd2, 0xf8, 0x18, 0x14, 0xc3, 0xf8, 0x34, 0x15, 0xd2, 0xf8, 0x1c, 0x14, + 0xc3, 0xf8, 0x40, 0x15, 0xd2, 0xf8, 0x20, 0x14, 0xc3, 0xf8, 0x44, 0x15, + 0xd2, 0xf8, 0x24, 0x14, 0xc3, 0xf8, 0x48, 0x15, 0xd2, 0xf8, 0x28, 0x14, + 0xc3, 0xf8, 0x4c, 0x15, 0xd2, 0xf8, 0x2c, 0x14, 0xc3, 0xf8, 0x50, 0x15, + 0xd2, 0xf8, 0x30, 0x14, 0xc3, 0xf8, 0x54, 0x15, 0xd2, 0xf8, 0x34, 0x14, + 0xc3, 0xf8, 0x60, 0x15, 0xd2, 0xf8, 0x38, 0x14, 0xc3, 0xf8, 0x64, 0x15, + 0xd2, 0xf8, 0x3c, 0x14, 0xc3, 0xf8, 0x68, 0x15, 0xd2, 0xf8, 0x40, 0x14, + 0xc3, 0xf8, 0x6c, 0x15, 0xd2, 0xf8, 0x44, 0x24, 0xc3, 0xf8, 0x70, 0x25, + 0xff, 0xf7, 0x9c, 0xff, 0x48, 0xb1, 0x4f, 0xf0, 0x80, 0x43, 0xd3, 0xf8, + 0x00, 0x24, 0xd1, 0x07, 0x44, 0xbf, 0x6f, 0xf0, 0x01, 0x02, 0xc3, 0xf8, + 0x00, 0x24, 0x31, 0x4a, 0xd2, 0xf8, 0x88, 0x30, 0x43, 0xf4, 0x70, 0x03, + 0xc2, 0xf8, 0x88, 0x30, 0xbf, 0xf3, 0x4f, 0x8f, 0xbf, 0xf3, 0x6f, 0x8f, + 0x4f, 0xf0, 0x10, 0x23, 0xd3, 0xf8, 0x0c, 0x22, 0xd2, 0x07, 0x1e, 0xd5, + 0x29, 0x4b, 0x01, 0x22, 0xc3, 0xf8, 0x04, 0x25, 0xd3, 0xf8, 0x00, 0x24, + 0x00, 0x2a, 0xfb, 0xd0, 0x4f, 0xf0, 0x10, 0x22, 0xd2, 0xf8, 0x0c, 0x32, + 0x23, 0xf0, 0x01, 0x03, 0xc2, 0xf8, 0x0c, 0x32, 0x21, 0x4b, 0x1a, 0x46, + 0xd3, 0xf8, 0x00, 0x14, 0x00, 0x29, 0xfb, 0xd0, 0x00, 0x21, 0xc3, 0xf8, + 0x04, 0x15, 0xd2, 0xf8, 0x00, 0x34, 0x00, 0x2b, 0xfb, 0xd0, 0xff, 0xf7, + 0x4f, 0xff, 0xd3, 0xf8, 0x00, 0x22, 0x00, 0x2a, 0x03, 0xdb, 0xd3, 0xf8, + 0x04, 0x32, 0x00, 0x2b, 0x23, 0xda, 0x16, 0x4b, 0x01, 0x22, 0xc3, 0xf8, + 0x04, 0x25, 0xd3, 0xf8, 0x00, 0x24, 0x00, 0x2a, 0xfb, 0xd0, 0x4f, 0xf0, + 0x10, 0x22, 0x12, 0x21, 0xc2, 0xf8, 0x00, 0x12, 0xd3, 0xf8, 0x00, 0x24, + 0x00, 0x2a, 0xfb, 0xd0, 0x4f, 0xf0, 0x10, 0x23, 0x12, 0x22, 0xc3, 0xf8, + 0x04, 0x22, 0x0b, 0x4b, 0x1a, 0x46, 0xd3, 0xf8, 0x00, 0x14, 0x00, 0x29, + 0xfb, 0xd0, 0x00, 0x21, 0xc3, 0xf8, 0x04, 0x15, 0xd2, 0xf8, 0x00, 0x34, + 0x00, 0x2b, 0xfb, 0xd0, 0xd1, 0xe7, 0x05, 0x4b, 0x05, 0x4a, 0x1a, 0x60, + 0x08, 0xbd, 0x00, 0xbf, 0x00, 0xc0, 0x00, 0x40, 0x00, 0xed, 0x00, 0xe0, + 0x00, 0xe0, 0x01, 0x40, 0x00, 0x00, 0x00, 0x20, 0x00, 0x90, 0xd0, 0x03, + 0x1f, 0x28, 0x86, 0xbf, 0x00, 0xf0, 0x1f, 0x00, 0x04, 0x4a, 0x4f, 0xf0, + 0xa0, 0x42, 0x01, 0x23, 0x03, 0xfa, 0x00, 0xf0, 0xc2, 0xf8, 0x08, 0x05, + 0x70, 0x47, 0x00, 0xbf, 0x00, 0x03, 0x00, 0x50, 0x80, 0x5c, 0xc1, 0xf1, + 0x04, 0x01, 0x08, 0x41, 0xc0, 0x43, 0x00, 0xf0, 0x01, 0x00, 0x70, 0x47, + 0x00, 0x23, 0x4f, 0xf0, 0xa0, 0x42, 0x83, 0x42, 0x00, 0xdb, 0x70, 0x47, + 0xd2, 0xf8, 0x04, 0x15, 0x01, 0x33, 0xf8, 0xe7, 0x38, 0xb5, 0x1c, 0x20, + 0xff, 0xf7, 0xda, 0xff, 0x0b, 0x20, 0xff, 0xf7, 0xd7, 0xff, 0x1f, 0x20, + 0xff, 0xf7, 0xd4, 0xff, 0x25, 0x20, 0xff, 0xf7, 0xd1, 0xff, 0x0b, 0x4c, + 0x0b, 0x4d, 0x1e, 0x20, 0xff, 0xf7, 0xcc, 0xff, 0x00, 0x22, 0x01, 0x20, + 0x13, 0x5d, 0x1f, 0x2b, 0x86, 0xbf, 0x03, 0xf0, 0x1f, 0x03, 0x29, 0x46, + 0x4f, 0xf0, 0xa0, 0x41, 0x01, 0x32, 0x00, 0xfa, 0x03, 0xf3, 0x05, 0x2a, + 0xc1, 0xf8, 0x0c, 0x35, 0xf0, 0xd1, 0x38, 0xbd, 0x69, 0x07, 0x00, 0x00, + 0x00, 0x03, 0x00, 0x50, 0x2d, 0xe9, 0xf8, 0x4f, 0x80, 0x46, 0x3e, 0x48, + 0x3e, 0x4d, 0x00, 0x22, 0x82, 0x46, 0x03, 0x24, 0x13, 0x5c, 0x1f, 0x2b, + 0x86, 0xbf, 0x03, 0xf0, 0x1f, 0x03, 0x29, 0x46, 0x4f, 0xf0, 0xa0, 0x41, + 0x03, 0xf5, 0xe0, 0x73, 0x01, 0x32, 0x05, 0x2a, 0x41, 0xf8, 0x23, 0x40, + 0xf0, 0xd1, 0x36, 0x48, 0x34, 0x4d, 0x00, 0x22, 0x03, 0x24, 0x13, 0x5c, + 0x1f, 0x2b, 0x86, 0xbf, 0x03, 0xf0, 0x1f, 0x03, 0x29, 0x46, 0x4f, 0xf0, + 0xa0, 0x41, 0x03, 0xf5, 0xe0, 0x73, 0x01, 0x32, 0x05, 0x2a, 0x41, 0xf8, + 0x23, 0x40, 0xf0, 0xd1, 0xff, 0xf7, 0xac, 0xff, 0x4f, 0xf0, 0x01, 0x09, + 0x00, 0x25, 0x01, 0x2d, 0x46, 0xdc, 0x2a, 0x4c, 0x2a, 0x4b, 0x00, 0x2d, + 0x08, 0xbf, 0x1c, 0x46, 0x0e, 0xe0, 0x01, 0x39, 0x93, 0xfb, 0xf2, 0xf3, + 0x02, 0x29, 0xfa, 0xd1, 0x98, 0xfb, 0xf3, 0xf3, 0x93, 0xfb, 0xf2, 0xf4, + 0x02, 0xfb, 0x14, 0x34, 0x23, 0x4b, 0x04, 0xeb, 0x84, 0x04, 0x1c, 0x44, + 0x32, 0x27, 0x00, 0x26, 0x1d, 0x4b, 0x98, 0x5d, 0xff, 0xf7, 0x6a, 0xff, + 0x4f, 0xf0, 0x00, 0x0b, 0x32, 0x46, 0x59, 0x46, 0x20, 0x46, 0x1a, 0xf8, + 0x0b, 0x30, 0xff, 0xf7, 0x71, 0xff, 0x28, 0xbb, 0x1f, 0x2b, 0x86, 0xbf, + 0x03, 0xf0, 0x1f, 0x03, 0x13, 0x4a, 0x4f, 0xf0, 0xa0, 0x42, 0x09, 0xfa, + 0x03, 0xf3, 0xc2, 0xf8, 0x0c, 0x35, 0x0b, 0xf1, 0x01, 0x0b, 0xbb, 0xf1, + 0x05, 0x0f, 0xe7, 0xd1, 0x44, 0xf6, 0x20, 0x60, 0x01, 0x36, 0xff, 0xf7, + 0x63, 0xff, 0xff, 0xf7, 0x6b, 0xff, 0x05, 0x2e, 0xd8, 0xd1, 0x01, 0x3f, + 0xd5, 0xd1, 0x0d, 0x48, 0x01, 0x35, 0xff, 0xf7, 0x59, 0xff, 0x05, 0x2d, + 0xb7, 0xd1, 0xb5, 0xe7, 0x29, 0x46, 0x64, 0x23, 0x0a, 0x22, 0xbd, 0xe7, + 0x18, 0x46, 0xff, 0xf7, 0x37, 0xff, 0xe0, 0xe7, 0x5f, 0x07, 0x00, 0x00, + 0x00, 0x03, 0x00, 0x50, 0x69, 0x07, 0x00, 0x00, 0x28, 0x07, 0x00, 0x00, + 0x64, 0x07, 0x00, 0x00, 0x2d, 0x07, 0x00, 0x00, 0xa0, 0x86, 0x01, 0x00, + 0x08, 0xb5, 0x03, 0x4b, 0x98, 0x88, 0xff, 0xf7, 0x6d, 0xff, 0x00, 0x20, + 0x08, 0xbd, 0x00, 0xbf, 0x04, 0x00, 0x00, 0x20, 0x08, 0xb5, 0x07, 0x4b, + 0x04, 0x46, 0x13, 0xb1, 0x00, 0x21, 0xaf, 0xf3, 0x00, 0x80, 0x05, 0x4b, + 0x18, 0x68, 0x83, 0x6a, 0x03, 0xb1, 0x98, 0x47, 0x20, 0x46, 0x00, 0xf0, + 0x31, 0xf8, 0x00, 0xbf, 0x00, 0x00, 0x00, 0x00, 0x70, 0x07, 0x00, 0x00, + 0x70, 0xb5, 0x0d, 0x4e, 0x0d, 0x4c, 0xa4, 0x1b, 0xa4, 0x10, 0x00, 0x25, + 0xa5, 0x42, 0x09, 0xd1, 0x0b, 0x4e, 0x0c, 0x4c, 0x00, 0xf0, 0x22, 0xf8, + 0xa4, 0x1b, 0xa4, 0x10, 0x00, 0x25, 0xa5, 0x42, 0x05, 0xd1, 0x70, 0xbd, + 0x56, 0xf8, 0x25, 0x30, 0x98, 0x47, 0x01, 0x35, 0xee, 0xe7, 0x56, 0xf8, + 0x25, 0x30, 0x98, 0x47, 0x01, 0x35, 0xf2, 0xe7, 0x6c, 0x00, 0x00, 0x20, + 0x6c, 0x00, 0x00, 0x20, 0x6c, 0x00, 0x00, 0x20, 0x70, 0x00, 0x00, 0x20, + 0x02, 0x44, 0x03, 0x46, 0x93, 0x42, 0x00, 0xd1, 0x70, 0x47, 0x03, 0xf8, + 0x01, 0x1b, 0xf9, 0xe7, 0xfe, 0xe7, 0x00, 0xbf, 0xf8, 0xb5, 0x00, 0xbf, + 0xf8, 0xbc, 0x08, 0xbc, 0x9e, 0x46, 0x70, 0x47, 0xf8, 0xb5, 0x00, 0xbf, + 0xf8, 0xbc, 0x08, 0xbc, 0x9e, 0x46, 0x70, 0x47, 0x1e, 0xd0, 0x1c, 0x90, + 0x1e, 0x0c, 0x92, 0x52, 0x52, 0x4c, 0x04, 0x8c, 0x84, 0x84, 0x8e, 0x1c, + 0x82, 0x4c, 0x90, 0x1e, 0x1e, 0xc2, 0x44, 0x92, 0x4c, 0x06, 0xca, 0x52, + 0x5f, 0xe2, 0x1f, 0xf0, 0x1e, 0xc1, 0x3e, 0x02, 0x44, 0x8e, 0xd1, 0x2e, + 0x1f, 0xe2, 0x44, 0x88, 0x10, 0x0e, 0xd1, 0x2e, 0xd1, 0x2e, 0x0e, 0xd1, + 0x2e, 0xc4, 0x88, 0x1c, 0x0b, 0x1f, 0x25, 0x1e, 0x1b, 0x1b, 0x00, 0x0e, + 0x11, 0x15, 0x16, 0x0f, 0x18, 0x13, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0xc8, 0xfa, 0xff, 0x7f, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x90, 0xd0, 0x03, 0xde, 0xc0, 0xce, 0xfa, 0x46, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x25, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00 +}; diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 9e947a48f..497c863ce 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -30,9 +30,16 @@ #include "pwr_mon.h" #include "main_interface.h" #include "i2c.h" +#include "i2c_commands.h" #include "adc.h" #include "fsl_port.h" #include "fsl_gpio.h" +#include "led_error_app.h" +#include "flash_manager.h" +#include "virtual_fs.h" +#include "vfs_manager.h" +#include "cortex_m.h" +#include "FlashPrg.h" #ifdef DRAG_N_DROP_SUPPORT #include "flash_intf.h" @@ -47,6 +54,15 @@ #define PWR_LED_ON_BATT_BRIGHTNESS 40 // LED Brightness while being powered by battery #define PWR_LED_FADEOUT_MIN_BRIGHTNESS 30 // Minimum LED brightness when fading out +#define FLASH_CONFIG_ADDRESS (0x00020000) +#define FLASH_STORAGE_ADDRESS (0x00020400) +#define FLASH_CFG_FILENAME "DATA BIN" +#define FLASH_CFG_FILESIZEKB 126 +#define FLASH_CFG_FILEVISIBLE false + +// 'kvld' in hex - key valid +#define CFG_KEY 0x6b766c64 + const char * const board_id_mb_2_0 = "9903"; const char * const board_id_mb_2_1 = "9904"; @@ -66,6 +82,7 @@ typedef enum main_shutdown_state { MAIN_SHUTDOWN_WAITING = 0, MAIN_SHUTDOWN_PENDING, MAIN_SHUTDOWN_REACHED, + MAIN_SHUTDOWN_REACHED_FADE, MAIN_SHUTDOWN_REQUESTED, MAIN_LED_BLINK, MAIN_LED_FULL_BRIGHTNESS, @@ -74,12 +91,29 @@ typedef enum main_shutdown_state { extern void main_powerdown_event(void); +static void i2c_write_comms_callback(uint8_t* pData, uint8_t size); +static void i2c_read_comms_callback(uint8_t* pData, uint8_t size); +static void i2c_write_flash_callback(uint8_t* pData, uint8_t size); +static void i2c_read_flash_callback(uint8_t* pData, uint8_t size); +static uint32_t read_file_data_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors); + // shutdown state static main_shutdown_state_t main_shutdown_state = MAIN_SHUTDOWN_WAITING; static uint8_t shutdown_led_dc = 100; static uint8_t power_led_max_duty_cycle = 100; -static app_power_mode_t interface_power_mode; +static uint8_t initial_fade_brightness = 80; +static app_power_mode_t interface_power_mode = kAPP_PowerModeVlls0; static power_source_t power_source; +// reset button state count +static uint16_t gpio_reset_count = 0; +static bool do_remount = false; + +flashConfig_t gflashConfig = { + .key = CFG_KEY, + .fileName = FLASH_CFG_FILENAME, + .fileSizeKB = FLASH_CFG_FILESIZEKB, + .fileVisible = FLASH_CFG_FILEVISIBLE, +}; // Board Rev ID detection. Reads BRD_REV_ID voltage // Depends on gpio_init() to have been executed already @@ -190,6 +224,28 @@ static void prerun_board_config(void) flexio_pwm_set_dutycycle(gamma_led_dc); i2c_initialize(); + i2c_RegisterWriteCallback(i2c_write_comms_callback, I2C_SLAVE_NRF_KL_COMMS); + i2c_RegisterReadCallback(i2c_read_comms_callback, I2C_SLAVE_NRF_KL_COMMS); + i2c_RegisterWriteCallback(i2c_write_flash_callback, I2C_SLAVE_FLASH); + i2c_RegisterReadCallback(i2c_read_flash_callback, I2C_SLAVE_FLASH); + + gpio_pin_config_t pin_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 0U + }; + + /* COMBINED_SENSOR_INT pin mux ALT0 (Disabled High-Z) */ + PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); + /* COMBINED_SENSOR_INT as output default low when pin mux ALT1 */ + GPIO_PinInit(COMBINED_SENSOR_INT_GPIO, COMBINED_SENSOR_INT_PIN, &pin_config); + + // Load Config from Flash if present + flashConfig_t * pflashConfigROM; + pflashConfigROM = (void *)FLASH_CONFIG_ADDRESS; + + if (CFG_KEY == pflashConfigROM->key) { + memcpy(&gflashConfig, pflashConfigROM, sizeof(flashConfig_t)); + } } // Handle the reset button behavior, this function is called in the main task every 30ms @@ -197,8 +253,6 @@ void handle_reset_button() { // button state static uint8_t reset_pressed = 0; - // reset button state count - static uint16_t gpio_reset_count = 0; // handle reset button without eventing if (!reset_pressed && gpio_get_reset_btn_fwrd()) { @@ -220,24 +274,33 @@ void handle_reset_button() if (gpio_reset_count <= RESET_SHORT_PRESS) { main_shutdown_state = MAIN_LED_BLINK; } - else if (gpio_reset_count < RESET_LONG_PRESS) { + else if (gpio_reset_count < RESET_MID_PRESS) { // Indicate button has been released to stop to cancel the shutdown main_shutdown_state = MAIN_LED_BLINK; } - else if (gpio_reset_count >= RESET_LONG_PRESS) { + else if (gpio_reset_count >= RESET_MID_PRESS) { // Indicate the button has been released when shutdown is requested + interface_power_mode = kAPP_PowerModeVlls0; main_shutdown_state = MAIN_SHUTDOWN_REQUESTED; } } else if (reset_pressed && gpio_get_reset_btn_fwrd()) { // Reset button is still pressed - if (gpio_reset_count > RESET_SHORT_PRESS && gpio_reset_count < RESET_LONG_PRESS) { + if (gpio_reset_count <= RESET_SHORT_PRESS) { // Enter the shutdown pending state to begin LED dimming main_shutdown_state = MAIN_SHUTDOWN_PENDING; } - else if (gpio_reset_count >= RESET_LONG_PRESS) { + else if (gpio_reset_count < RESET_MID_PRESS) { + // Enter the shutdown pending state to begin LED dimming + main_shutdown_state = MAIN_SHUTDOWN_PENDING; + } + else if (gpio_reset_count < RESET_LONG_PRESS) { // Enter the shutdown reached state to blink LED main_shutdown_state = MAIN_SHUTDOWN_REACHED; } + else if (gpio_reset_count >= RESET_LONG_PRESS) { + // Enter the shutdown reached state to blink LED + main_shutdown_state = MAIN_SHUTDOWN_REACHED_FADE; + } // Avoid overflow, stop counting after longest event if (gpio_reset_count <= RESET_MAX_LENGTH_PRESS) { @@ -249,11 +312,6 @@ void handle_reset_button() void board_30ms_hook() { static uint8_t blink_in_progress = 0; - - if (go_to_sleep) { - go_to_sleep = false; - main_shutdown_state = MAIN_SHUTDOWN_REQUESTED; - } if (usb_state == USB_CONNECTED) { // configure pin as GPIO @@ -268,8 +326,8 @@ void board_30ms_hook() switch (main_shutdown_state) { case MAIN_LED_FULL_BRIGHTNESS: - // Jump power LED to full brightness - shutdown_led_dc = 100; + // Jump power LED to initial fade brightness + shutdown_led_dc = initial_fade_brightness; break; case MAIN_SHUTDOWN_CANCEL: main_shutdown_state = MAIN_SHUTDOWN_WAITING; @@ -278,18 +336,21 @@ void board_30ms_hook() break; case MAIN_SHUTDOWN_PENDING: // Fade the PWM until the board is about to be shut down - if (shutdown_led_dc > PWR_LED_FADEOUT_MIN_BRIGHTNESS) { - shutdown_led_dc--; - } + shutdown_led_dc = initial_fade_brightness - gpio_reset_count * (initial_fade_brightness - PWR_LED_FADEOUT_MIN_BRIGHTNESS)/(RESET_MID_PRESS); break; case MAIN_SHUTDOWN_REACHED: - // Turn off LED to indicate we are waiting for release - shutdown_led_dc = 0; + // Hold LED in min brightness + shutdown_led_dc = PWR_LED_FADEOUT_MIN_BRIGHTNESS; + break; + case MAIN_SHUTDOWN_REACHED_FADE: + // Fast fade to off + if (shutdown_led_dc > 0) { + shutdown_led_dc--; + } break; case MAIN_SHUTDOWN_REQUESTED: // TODO: put nRF into deep sleep and wake nRF when KL27 wakes up if (power_source == PWR_BATT_ONLY || usb_state == USB_DISCONNECTED) { - interface_power_mode = kAPP_PowerModeVlls0; main_powerdown_event(); } main_shutdown_state = MAIN_SHUTDOWN_WAITING; @@ -319,6 +380,12 @@ void board_30ms_hook() } uint8_t gamma_led_dc = get_led_gamma(shutdown_led_dc); flexio_pwm_set_dutycycle(gamma_led_dc); + + // Remount if requested. + if (do_remount) { + do_remount = false; + vfs_mngr_fs_remount(); + } } void board_handle_powerdown() @@ -342,6 +409,51 @@ void board_handle_powerdown() gpio_set_hid_led(HID_LED_DEF); } +void vfs_user_build_filesystem_hook() { + uint32_t file_size; + error_t status; + error_t error = vfs_mngr_get_transfer_status(); + + // Microbit error codes for DAPLink in the 500-599 range + uint16_t microbit_error = error + 500; + + if (error != ERROR_SUCCESS) { + // Error code offset after "0xFACEC0DE" magic word + led_error_bin_data[led_error_bin_code] = (uint8_t) microbit_error & 0xFF; + led_error_bin_data[led_error_bin_code + 1] = (uint8_t) (microbit_error >> 8) & 0xFF; + + status = flash_manager_init(flash_intf_target); + if (status != ERROR_SUCCESS) { + util_assert(0); + } + + status = flash_manager_data(0, (const uint8_t*)led_error_bin_data, led_error_bin_len); + if (status != ERROR_SUCCESS) { + flash_manager_uninit(); + util_assert(0); + } + + status = flash_manager_uninit(); + if (status != ERROR_SUCCESS) { + util_assert(0); + } + } + + file_size = gflashConfig.fileSizeKB * 1024; + + if (gflashConfig.fileVisible) { + vfs_create_file(gflashConfig.fileName, read_file_data_txt, 0, file_size); + } +} + +// File callback to be used with vfs_add_file to return file contents +static uint32_t read_file_data_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors) +{ + memcpy(data, (uint8_t *) (FLASH_STORAGE_ADDRESS + VFS_SECTOR_SIZE * sector_offset), VFS_SECTOR_SIZE); + + return VFS_SECTOR_SIZE; +} + uint8_t board_detect_incompatible_image(const uint8_t *data, uint32_t size) { uint8_t result = 0; @@ -372,3 +484,276 @@ const board_info_t g_board_info = { .target_cfg = &target_device, }; +static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { + i2cCommand_t* pI2cCommand = (i2cCommand_t*) pData; + i2cCommand_t i2cResponse = {0}; + + switch (pI2cCommand->cmdId) { + case gReadRequest_c: + i2cResponse.cmdId = gReadResponse_c; + i2cResponse.cmdData.readRspCmd.propertyId = pI2cCommand->cmdData.readReqCmd.propertyId; + switch (pI2cCommand->cmdData.readReqCmd.propertyId) { + case gDAPLinkBoardVersion_c: + i2cResponse.cmdData.readRspCmd.dataSize = sizeof(board_id_hex); + memcpy(&i2cResponse.cmdData.readRspCmd.data, &board_id_hex, sizeof(board_id_hex)); + break; + case gI2CProtocolVersion_c: { + uint32_t i2c_version = 1; + i2cResponse.cmdData.readRspCmd.dataSize = sizeof(i2c_version); + memcpy(&i2cResponse.cmdData.readRspCmd.data, &i2c_version, sizeof(i2c_version)); + } + break; + case gDAPLinkVersion_c: { + uint32_t daplink_version = DAPLINK_VERSION; + i2cResponse.cmdData.readRspCmd.dataSize = sizeof(daplink_version); + memcpy(&i2cResponse.cmdData.readRspCmd.data, &daplink_version, sizeof(daplink_version)); + } + break; + case gPowerState_c: + i2cResponse.cmdData.readRspCmd.dataSize = sizeof(power_source); + memcpy(&i2cResponse.cmdData.readRspCmd.data, &power_source, sizeof(power_source)); + break; + case gPowerConsumption_c: { + uint32_t power_consumption = 1; + i2cResponse.cmdData.readRspCmd.dataSize = sizeof(power_consumption); + memcpy(&i2cResponse.cmdData.readRspCmd.data, &power_consumption, sizeof(power_consumption)); + } + break; + case gUSBEnumerationState_c: + i2cResponse.cmdData.readRspCmd.dataSize = sizeof(usb_state); + memcpy(&i2cResponse.cmdData.readRspCmd.data, &usb_state, sizeof(usb_state)); + break; + case gPowerMode_c: + case gNRFPowerMode_c: + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorReadDisallowed_c; + break; + default: + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorUnknownProperty_c; + break; + } + break; + case gReadResponse_c: + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorCommandDisallowed_c; + break; + case gWriteRequest_c: + switch (pI2cCommand->cmdData.writeReqCmd.propertyId) { + case gDAPLinkBoardVersion_c: + case gI2CProtocolVersion_c: + case gDAPLinkVersion_c: + case gPowerState_c: + case gPowerConsumption_c: + case gUSBEnumerationState_c: + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWriteDisallowed_c; + break; + case gPowerMode_c: + if (pI2cCommand->cmdData.writeReqCmd.dataSize == 1) { + if (pI2cCommand->cmdData.writeReqCmd.data[0] == kAPP_PowerModeVlls0) { + if (power_source == PWR_BATT_ONLY || usb_state == USB_DISCONNECTED) { + interface_power_mode = kAPP_PowerModeVlls0; + i2cResponse.cmdId = gWriteResponse_c; + i2cResponse.cmdData.writeRspCmd.propertyId = pI2cCommand->cmdData.writeReqCmd.propertyId; + } else { + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWriteDisallowed_c; + } + } else if (pI2cCommand->cmdData.writeReqCmd.data[0] == kAPP_PowerModeVlps) { + if (power_source == PWR_BATT_ONLY || usb_state == USB_DISCONNECTED) { + interface_power_mode = kAPP_PowerModeVlps; + i2cResponse.cmdId = gWriteResponse_c; + i2cResponse.cmdData.writeRspCmd.propertyId = pI2cCommand->cmdData.writeReqCmd.propertyId; + } else { + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWriteDisallowed_c; + } + } else { + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWriteFail_c; + } + } else { + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWrongPropertySize_c; + } + break; + case gNRFPowerMode_c: + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWriteDisallowed_c; + break; + default: + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorUnknownProperty_c; + break; + } + break; + case gWriteResponse_c: + break; + case gErrorResponse_c: + break; + default: + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorUnknownProperty_c; + break; + } + + i2c_fillBuffer((uint8_t*) &i2cResponse, 0, sizeof(i2cResponse)); + + // Response ready, assert COMBINED_SENSOR_INT + PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_MuxAsGpio); +} + +static void i2c_read_comms_callback(uint8_t* pData, uint8_t size) { + i2cCommand_t* pI2cCommand = (i2cCommand_t*) pData; + + switch (pI2cCommand->cmdId) { + case gWriteResponse_c: + switch (pI2cCommand->cmdData.writeRspCmd.propertyId) { + case gPowerMode_c: + main_shutdown_state = MAIN_SHUTDOWN_REQUESTED; + break; + } + break; + } + + // Release COMBINED_SENSOR_INT + PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); +} + +static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { + i2cFlashCmd_t* pI2cCommand = (i2cFlashCmd_t*) pData; + + uint32_t status; + cortex_int_state_t state; + + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, sizeof(i2cFlashCmd_t) - 1024); + + uint32_t address = pI2cCommand->cmdData.write.addr2 << 16 | + pI2cCommand->cmdData.write.addr1 << 8 | + pI2cCommand->cmdData.write.addr0 << 0; + address = address + FLASH_STORAGE_ADDRESS; + uint32_t length = __REV(pI2cCommand->cmdData.write.length); + uint32_t data = (uint32_t) pI2cCommand->cmdData.write.data; + + switch (pI2cCommand->cmdId) { + case gFlashDataWrite_c: + state = cortex_int_get_and_disable(); + status = ProgramPage(address, length, (uint32_t *) data); + cortex_int_restore(state); + + if (0 != status) { + i2c_clearBuffer(); + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } + else { + i2c_fillBuffer((uint8_t*) address, sizeof(i2cFlashCmd_t) - 1024, length); + } + break; + case gFlashDataRead_c: { + i2c_fillBuffer((uint8_t*) address, sizeof(i2cFlashCmd_t) - 1024, length); + } + break; + case gFlashDataErase_c: { + state = cortex_int_get_and_disable(); + status = EraseSector(address); + cortex_int_restore(state); + + if (status != 0) { + i2c_clearBuffer(); + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } + } + break; + case gFlashCfgFileName_c: + memcpy(gflashConfig.fileName, pI2cCommand->cmdData.data, 11); + break; + case gFlashCfgFileSize_c: + gflashConfig.fileSizeKB = pI2cCommand->cmdData.data[0]; + break; + case gFlashCfgFileVisible_c: + gflashConfig.fileVisible = pI2cCommand->cmdData.data[0]; + break; + case gFlashCfgWrite_c: + // Check first is config is already present in flash + // If differences are found, erase and write new config + if (0 != memcmp(&gflashConfig, (void *)FLASH_CONFIG_ADDRESS, sizeof(flashConfig_t))) { + state = cortex_int_get_and_disable(); + status = EraseSector(FLASH_CONFIG_ADDRESS); + cortex_int_restore(state); + + if (status != 0) { + i2c_clearBuffer(); + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } + else { + state = cortex_int_get_and_disable(); + status = ProgramPage(FLASH_CONFIG_ADDRESS, sizeof(flashConfig_t), (uint32_t *) &gflashConfig); + cortex_int_restore(state); + } + } + break; + case gFlashCfgErase_c: + // Erase flash sector containing flash config + state = cortex_int_get_and_disable(); + status = EraseSector(FLASH_CONFIG_ADDRESS); + cortex_int_restore(state); + + if (status != 0) { + i2c_clearBuffer(); + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } + else { + // Return flash config (RAM) to default values + gflashConfig.key = CFG_KEY; + memcpy(gflashConfig.fileName, FLASH_CFG_FILENAME, 11); + gflashConfig.fileSizeKB = FLASH_CFG_FILESIZEKB; + gflashConfig.fileVisible = FLASH_CFG_FILEVISIBLE; + } + break; + case gFlashStorageSize_c: + i2c_clearBuffer(); + pI2cCommand->cmdId = gFlashStorageSize_c; + pI2cCommand->cmdData.data[0] = 128; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 2); + break; + case gFlashSectorSize_c: + i2c_clearBuffer(); + pI2cCommand->cmdId = gFlashSectorSize_c; + pI2cCommand->cmdData.data[0] = 0x04; + pI2cCommand->cmdData.data[1] = 0x00; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 3); + break; + case gFlashStatus_c: + break; + case gFlashRemountMSD_c: + do_remount = true; + break; + default: + i2c_clearBuffer(); + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + break; + } + + // Response ready, assert COMBINED_SENSOR_INT + PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_MuxAsGpio); +} + +static void i2c_read_flash_callback(uint8_t* pData, uint8_t size) { + i2cCommand_t* pI2cCommand = (i2cCommand_t*) pData; + + switch (pI2cCommand->cmdId) { + case gWriteResponse_c: + break; + } + + i2c_clearBuffer(); + + // Release COMBINED_SENSOR_INT + PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); +} diff --git a/source/daplink/cmsis-dap/DAP.c b/source/daplink/cmsis-dap/DAP.c index d94bcd201..5ff8bc34b 100644 --- a/source/daplink/cmsis-dap/DAP.c +++ b/source/daplink/cmsis-dap/DAP.c @@ -1777,8 +1777,8 @@ void DAP_Setup(void) { // Default settings DAP_Data.debug_port = 0U; - DAP_Data.fast_clock = 0U; - DAP_Data.clock_delay = CLOCK_DELAY(DAP_DEFAULT_SWJ_CLOCK); + // DAP_Data.fast_clock = 0U; + // DAP_Data.clock_delay = CLOCK_DELAY(DAP_DEFAULT_SWJ_CLOCK); DAP_Data.nominal_clock = DAP_DEFAULT_SWJ_CLOCK; DAP_Data.transfer.idle_cycles = 0U; DAP_Data.transfer.retry_count = 100U; @@ -1792,5 +1792,22 @@ void DAP_Setup(void) { DAP_Data.jtag_dev.count = 0U; #endif + if (DAP_DEFAULT_SWJ_CLOCK >= MAX_SWJ_CLOCK(DELAY_FAST_CYCLES)) { + DAP_Data.fast_clock = 1U; + DAP_Data.clock_delay = 1U; + } else { + DAP_Data.fast_clock = 0U; + + uint32_t delay = ((CPU_CLOCK/2U) + (DAP_DEFAULT_SWJ_CLOCK - 1U)) / DAP_DEFAULT_SWJ_CLOCK; + if (delay > IO_PORT_WRITE_CYCLES) { + delay -= IO_PORT_WRITE_CYCLES; + delay = (delay + (DELAY_SLOW_CYCLES - 1U)) / DELAY_SLOW_CYCLES; + } else { + delay = 1U; + } + + DAP_Data.clock_delay = delay; + } + DAP_SETUP(); // Device specific setup } diff --git a/source/daplink/drag-n-drop/flash_decoder.c b/source/daplink/drag-n-drop/flash_decoder.c index 440332c20..ce7109fd1 100644 --- a/source/daplink/drag-n-drop/flash_decoder.c +++ b/source/daplink/drag-n-drop/flash_decoder.c @@ -130,9 +130,14 @@ error_t flash_decoder_get_flash(flash_decoder_type_t type, uint32_t addr, bool a flash_intf_local = flash_intf_iap_protected; } } else if (FLASH_DECODER_TYPE_TARGET == type) { - // "Target" update in this case would be a 3rd party interface application - flash_start_local = DAPLINK_ROM_IF_START; - flash_intf_local = flash_intf_iap_protected; + if (addr_valid && (DAPLINK_ROM_IF_START != addr)) { + // Address is wrong so display error message + status = ERROR_FD_INTF_UPDT_ADDR_WRONG; + } else { + // "Target" update in this case would be a 3rd party interface application + flash_start_local = DAPLINK_ROM_IF_START; + flash_intf_local = flash_intf_iap_protected; + } } else { status = ERROR_FD_UNSUPPORTED_UPDATE; } diff --git a/source/daplink/drag-n-drop/vfs_user.c b/source/daplink/drag-n-drop/vfs_user.c index c141d6409..815cf0628 100644 --- a/source/daplink/drag-n-drop/vfs_user.c +++ b/source/daplink/drag-n-drop/vfs_user.c @@ -138,6 +138,8 @@ static void erase_target(void); static uint32_t expand_info(uint8_t *buf, uint32_t bufsize); +__WEAK void vfs_user_build_filesystem_hook(){} + void vfs_user_build_filesystem() { uint32_t file_size; @@ -177,6 +179,8 @@ void vfs_user_build_filesystem() file_size = get_file_size(read_file_need_bl_txt); vfs_create_file("NEED_BL TXT", read_file_need_bl_txt, 0, file_size); } + + vfs_user_build_filesystem_hook(); } // Default file change hook. diff --git a/source/hic_hal/freescale/kl27z/DAP_config.h b/source/hic_hal/freescale/kl27z/DAP_config.h index 672e62906..8268194e0 100644 --- a/source/hic_hal/freescale/kl27z/DAP_config.h +++ b/source/hic_hal/freescale/kl27z/DAP_config.h @@ -68,7 +68,7 @@ Provides definitions about: /// Default communication speed on the Debug Access Port for SWD and JTAG mode. /// Used to initialize the default SWD/JTAG clock frequency. /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting. -#define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz. +#define DAP_DEFAULT_SWJ_CLOCK 8000000 ///< Default SWD/JTAG clock frequency in Hz. /// Maximum Package Size for Command and Response data. /// This configuration settings is used to optimized the communication performance with the diff --git a/source/hic_hal/freescale/kl27z/fsl_i2c.c b/source/hic_hal/freescale/kl27z/fsl_i2c_mod.c similarity index 99% rename from source/hic_hal/freescale/kl27z/fsl_i2c.c rename to source/hic_hal/freescale/kl27z/fsl_i2c_mod.c index 3752dfecc..7e7eaa323 100644 --- a/source/hic_hal/freescale/kl27z/fsl_i2c.c +++ b/source/hic_hal/freescale/kl27z/fsl_i2c_mod.c @@ -1,3 +1,11 @@ +/* This is a modification of the default fsl_i2c.c driver. + * + * Needed in order to be able to identify slave address that triggered the + * kI2C_SlaveAddressMatchEvent from an address range configuration. + * Address is saved the i2c slave hanlder user data pointer, which is passed + * to the interrupt handler callback from the i2c_slave.c. + */ + /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP @@ -2240,6 +2248,8 @@ void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle) base->C1 |= I2C_C1_TX_MASK; doTransmit = true; + // Store the slave address match + dummy = base->D; } else { @@ -2247,6 +2257,7 @@ void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle) base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); /* Read dummy to release the bus. */ + // Which happens to contain the slave address match dummy = base->D; if (dummy == 0u) @@ -2257,6 +2268,8 @@ void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle) if ((0U != (handle->eventMask & (uint32_t)xfer->event)) && (NULL != handle->callback)) { + // Store the matched slave address in userData + *(uint8_t *)(handle->userData) = dummy; handle->callback(base, xfer, handle->userData); } } diff --git a/source/hic_hal/freescale/kl27z/i2c.c b/source/hic_hal/freescale/kl27z/i2c.c index 264c108f3..c5ad54f30 100644 --- a/source/hic_hal/freescale/kl27z/i2c.c +++ b/source/hic_hal/freescale/kl27z/i2c.c @@ -9,38 +9,26 @@ #define I2C_SLAVE_CLK_SRC I2C1_CLK_SRC #define I2C_SLAVE_CLK_FREQ CLOCK_GetFreq(I2C1_CLK_SRC) -#define I2C_MASTER_SLAVE_ADDR_7BIT 0x7AU -#define I2C_DATA_LENGTH (32U) +#define I2C_SLAVE_LOWER_ADDR_7BIT (0x70U) +#define I2C_SLAVE_UPPER_ADDR_7BIT (0x72U) +#define I2C_DATA_LENGTH (1024U + 8U) // We'll start with 5 RX commands #define RX_CMDS_LENGTH 5 #define I2C_CMD_SLEEP 0xABU -static void i2c_cmd_sleep_callback(void); - -typedef struct _cmd_callback { - uint8_t cmdValue; - void (*callback)(); -} cmd_callback_t; - -static cmd_callback_t i2cSleepCmd = { - .cmdValue = I2C_CMD_SLEEP, - .callback = i2c_cmd_sleep_callback, -}; - -static cmd_callback_t *rx_cmds[RX_CMDS_LENGTH]; - static uint8_t g_slave_buff[I2C_DATA_LENGTH]; static i2c_slave_handle_t g_s_handle; static volatile bool g_SlaveCompletionFlag = false; static volatile bool g_SlaveRxFlag = false; +uint8_t address_match = 0; -bool go_to_sleep = false; - - -static void i2c_cmd_sleep_callback() { - go_to_sleep = true; -} +static i2cWriteCallback_t pfWriteCommsCallback = NULL; +static i2cReadCallback_t pfReadCommsCallback = NULL; +static i2cWriteCallback_t pfWriteHIDCallback = NULL; +static i2cReadCallback_t pfReadHIDCallback = NULL; +static i2cWriteCallback_t pfWriteFlashCallback = NULL; +static i2cReadCallback_t pfReadFlashCallback = NULL; static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData) { switch (xfer->event) @@ -49,13 +37,12 @@ static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void case kI2C_SlaveAddressMatchEvent: xfer->data = NULL; xfer->dataSize = 0; + // fsl_i2c.c IRQ updated in fsl_i2c_mod.c to include I2C D register + address_match = *(uint8_t*)userData >> 1; break; /* Transmit request */ case kI2C_SlaveTransmitEvent: /* Update information for transmit process */ - for (uint32_t i = 0U; i < I2C_DATA_LENGTH; i++) { - g_slave_buff[i] = i; - } xfer->data = g_slave_buff; xfer->dataSize = I2C_DATA_LENGTH; break; @@ -81,14 +68,28 @@ static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void // Default driver couldn't differentiate between RX or TX completion // Check flag set in kI2C_SlaveReceiveEvent if (g_SlaveRxFlag) { - // Check all registered commands - for (uint8_t i = 0; i < RX_CMDS_LENGTH; i++) { - if (rx_cmds[i] != NULL && (g_slave_buff[0] == (rx_cmds[i])->cmdValue)) { - rx_cmds[i]->callback(); - } + g_SlaveRxFlag = false; + + if (pfWriteCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { + pfWriteCommsCallback(&g_slave_buff[0], xfer->transferredCount); + } + if (pfWriteHIDCallback && address_match == I2C_SLAVE_HID) { + pfWriteHIDCallback(&g_slave_buff[0], xfer->transferredCount); + } + if (pfWriteFlashCallback && address_match == I2C_SLAVE_FLASH) { + pfWriteFlashCallback(&g_slave_buff[0], xfer->transferredCount); + } + } else { + if (pfReadCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { + pfReadCommsCallback(&g_slave_buff[0], xfer->transferredCount); + } + if (pfReadHIDCallback && address_match == I2C_SLAVE_HID) { + pfReadHIDCallback(&g_slave_buff[0], xfer->transferredCount); + } + if (pfReadFlashCallback && address_match == I2C_SLAVE_FLASH) { + pfReadFlashCallback(&g_slave_buff[0], xfer->transferredCount); } } - g_SlaveRxFlag = false; break; default: @@ -127,7 +128,7 @@ static int32_t i2c_start_transfer(void) { memset(&g_s_handle, 0, sizeof(g_s_handle)); I2C_SlaveTransferCreateHandle(I2C_SLAVE_BASEADDR, &g_s_handle, - i2c_slave_callback, NULL); + i2c_slave_callback, &address_match); /* Set up slave transfer. */ I2C_SlaveTransferNonBlocking(I2C_SLAVE_BASEADDR, &g_s_handle, @@ -136,27 +137,16 @@ static int32_t i2c_start_transfer(void) { return 1; } -static status_t i2c_slave_register_cmd_callback(cmd_callback_t *cmdCalback) { - for (uint8_t i = 0; i < RX_CMDS_LENGTH; i++) { - if (rx_cmds[i] == NULL) { - rx_cmds[i] = cmdCalback; - return kStatus_Success; - } - } - return kStatus_Fail; -} - int32_t i2c_initialize(void) { i2c_slave_config_t slaveConfig; i2c_init_pins(); - status_t cmd_register_status = i2c_slave_register_cmd_callback(&i2cSleepCmd); - I2C_SlaveGetDefaultConfig(&slaveConfig); - slaveConfig.addressingMode = kI2C_Address7bit; - slaveConfig.slaveAddress = I2C_MASTER_SLAVE_ADDR_7BIT; + slaveConfig.addressingMode = kI2C_RangeMatch; + slaveConfig.slaveAddress = I2C_SLAVE_LOWER_ADDR_7BIT; + slaveConfig.upperAddress = I2C_SLAVE_UPPER_ADDR_7BIT; slaveConfig.enableWakeUp = true; I2C_SlaveInit(I2C_SLAVE_BASEADDR, &slaveConfig, I2C_SLAVE_CLK_FREQ); @@ -171,3 +161,61 @@ int32_t i2c_deinitialize(void) { return 1; } +status_t i2c_RegisterWriteCallback(i2cWriteCallback_t writeCallback, uint8_t slaveAddress) +{ + status_t status = kStatus_Success; + + switch (slaveAddress){ + case I2C_SLAVE_NRF_KL_COMMS: + pfWriteCommsCallback = writeCallback; + break; + case I2C_SLAVE_HID: + pfWriteHIDCallback = writeCallback; + break; + case I2C_SLAVE_FLASH: + pfWriteFlashCallback = writeCallback; + break; + default: + status = kStatus_Fail; + break; + } + + return status; +} + +status_t i2c_RegisterReadCallback(i2cReadCallback_t readCallback, uint8_t slaveAddress) +{ + status_t status = kStatus_Success; + + switch (slaveAddress) { + case I2C_SLAVE_NRF_KL_COMMS: + pfReadCommsCallback = readCallback; + break; + case I2C_SLAVE_HID: + pfReadHIDCallback = readCallback; + break; + case I2C_SLAVE_FLASH: + pfReadFlashCallback = readCallback; + break; + default: + status = kStatus_Fail; + break; + } + + return status; +} + +void i2c_clearBuffer (void) { + memset(&g_slave_buff, 0, sizeof(g_slave_buff)); +} + +void i2c_fillBuffer (uint8_t* data, uint32_t position, uint32_t size) { + if ((position + size) > I2C_DATA_LENGTH) { + return; + } + + for (uint32_t i = 0; i < size; i++) { + g_slave_buff[position + i] = data[i]; + } +} + diff --git a/source/hic_hal/freescale/kl27z/i2c.h b/source/hic_hal/freescale/kl27z/i2c.h index e5177a782..95e783d03 100644 --- a/source/hic_hal/freescale/kl27z/i2c.h +++ b/source/hic_hal/freescale/kl27z/i2c.h @@ -8,7 +8,29 @@ #include "fsl_common.h" +#define I2C_SLAVE_NRF_KL_COMMS (0x70U) +#define I2C_SLAVE_HID (0x71U) +#define I2C_SLAVE_FLASH (0x72U) + +/*! i2c Write Callback prototype */ +typedef void (*i2cWriteCallback_t) +( + uint8_t* pData, + uint8_t size +); + +/*! i2c Read Callback prototype */ +typedef void (*i2cReadCallback_t) +( + uint8_t* pData, + uint8_t size +); + int32_t i2c_initialize(void); int32_t i2c_deinitialize(void); +status_t i2c_RegisterWriteCallback(i2cWriteCallback_t writeCallback, uint8_t slaveAddress); +status_t i2c_RegisterReadCallback(i2cReadCallback_t readCallback, uint8_t slaveAddress); +void i2c_clearBuffer(void); +void i2c_fillBuffer(uint8_t* data, uint32_t position, uint32_t size); #endif /* I2C_H_ */ From 3d01fbe5fc4f7da68b7025409238aa1f68029193 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Fri, 21 Aug 2020 21:55:12 -0500 Subject: [PATCH 215/617] Add Power LED sleep state ON/OFF support in I2C comms interface -Make power LED remain active in VLPS mode. Changed FlexIO source clock to one that is active in VLPS. -Removed NRF Power mode property -Added Power LED sleep state property -Changed size of properties 0x01-03 to 2B --- source/board/microbitv2/flexio_pwm.c | 20 ++++++++--- source/board/microbitv2/i2c_commands.h | 2 +- source/board/microbitv2/microbitv2.c | 47 +++++++++++++++++++------- source/board/microbitv2/power.c | 2 -- 4 files changed, 50 insertions(+), 21 deletions(-) diff --git a/source/board/microbitv2/flexio_pwm.c b/source/board/microbitv2/flexio_pwm.c index c5cc28a76..7d148faf9 100644 --- a/source/board/microbitv2/flexio_pwm.c +++ b/source/board/microbitv2/flexio_pwm.c @@ -19,8 +19,8 @@ #define DEMO_FLEXIO_OUTPUTPIN 7U /* Select FXIO_D7 as PWM output */ #define DEMO_FLEXIO_TIMER_CH 0U /* Flexio timer0 used */ -#define DEMO_FLEXIO_CLOCK_FREQUENCY CLOCK_GetFreq(kCLOCK_McgIrc48MClk) -#define DEMO_FLEXIO_FREQUENCY 200000U +#define DEMO_FLEXIO_CLOCK_FREQUENCY CLOCK_GetFreq(kCLOCK_McgInternalRefClk) +#define DEMO_FLEXIO_FREQUENCY 31250U #define FLEXIO_MAX_FREQUENCY (DEMO_FLEXIO_CLOCK_FREQUENCY / 2U) #define FLEXIO_MIN_FREQUENCY (DEMO_FLEXIO_CLOCK_FREQUENCY / 256U) @@ -35,14 +35,24 @@ void flexio_pwm_init(void) { flexio_config_t fxioUserConfig; - - CLOCK_SetFlexio0Clock(1U); + + /* Enable the LIRC clock in the MCG */ + MCG->C1 |= MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK; + + /* Select the clock source for the FlexIO + 00 - Clock disabled + 01 - MCGPCLK clock + 10 - OSCERCLK clock + 11 - MCGIRCLK clock + */ + CLOCK_SetFlexio0Clock(3U); /* Init flexio, use default configure - * Disable doze and fast access mode + * Enable in Doze and fast access mode * Enable in debug mode */ FLEXIO_GetDefaultConfig(&fxioUserConfig); + fxioUserConfig.enableInDoze = true; FLEXIO_Init(DEMO_FLEXIO_BASEADDR, &fxioUserConfig); } diff --git a/source/board/microbitv2/i2c_commands.h b/source/board/microbitv2/i2c_commands.h index a06609477..237efde42 100644 --- a/source/board/microbitv2/i2c_commands.h +++ b/source/board/microbitv2/i2c_commands.h @@ -33,7 +33,7 @@ typedef enum propertyId_tag { gPowerConsumption_c = 0x05, gUSBEnumerationState_c = 0x06, gPowerMode_c = 0x07, - gNRFPowerMode_c = 0x08 + gPowerLedSleepState_c = 0x08 } propertyId_t; /*! property Id type enumeration */ diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 497c863ce..09e66ea72 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -51,8 +51,10 @@ #define BRD_ID_1_UPPER_THR_V 935 // Upper threshold in mV for 100nF and 4700R #define BRD_ID_1_LOWER_THR_V 268 // Lower threshold in mV for 100nF and 4700R -#define PWR_LED_ON_BATT_BRIGHTNESS 40 // LED Brightness while being powered by battery -#define PWR_LED_FADEOUT_MIN_BRIGHTNESS 30 // Minimum LED brightness when fading out +#define PWR_LED_ON_MAX_BRIGHTNESS 100 // Max LED Brightness (PC Connected) +#define PWR_LED_INIT_FADE_BRIGHTNESS 80 // Initial fade LED Brightness +#define PWR_LED_ON_BATT_BRIGHTNESS 40 // LED Brightness while being powered by battery +#define PWR_LED_FADEOUT_MIN_BRIGHTNESS 30 // Minimum LED brightness when fading out #define FLASH_CONFIG_ADDRESS (0x00020000) #define FLASH_STORAGE_ADDRESS (0x00020400) @@ -99,9 +101,10 @@ static uint32_t read_file_data_txt(uint32_t sector_offset, uint8_t *data, uint32 // shutdown state static main_shutdown_state_t main_shutdown_state = MAIN_SHUTDOWN_WAITING; -static uint8_t shutdown_led_dc = 100; -static uint8_t power_led_max_duty_cycle = 100; -static uint8_t initial_fade_brightness = 80; +static uint8_t shutdown_led_dc = PWR_LED_ON_MAX_BRIGHTNESS; +static uint8_t power_led_max_duty_cycle = PWR_LED_ON_MAX_BRIGHTNESS; +static uint8_t initial_fade_brightness = PWR_LED_INIT_FADE_BRIGHTNESS; +static bool power_led_sleep_state_on = true; static app_power_mode_t interface_power_mode = kAPP_PowerModeVlls0; static power_source_t power_source; // reset button state count @@ -218,7 +221,7 @@ static void prerun_board_config(void) } else { // Turn on the red LED with max duty cycle when powered by USB or EC - power_led_max_duty_cycle = 100; + power_led_max_duty_cycle = PWR_LED_ON_MAX_BRIGHTNESS; } uint8_t gamma_led_dc = get_led_gamma(power_led_max_duty_cycle); flexio_pwm_set_dutycycle(gamma_led_dc); @@ -316,7 +319,7 @@ void board_30ms_hook() if (usb_state == USB_CONNECTED) { // configure pin as GPIO PIN_HID_LED_PORT->PCR[PIN_HID_LED_BIT] = PORT_PCR_MUX(1); - power_led_max_duty_cycle = 100; + power_led_max_duty_cycle = PWR_LED_ON_MAX_BRIGHTNESS; } else if (usb_state == USB_DISCONNECTED) { // Disable pin @@ -352,7 +355,15 @@ void board_30ms_hook() // TODO: put nRF into deep sleep and wake nRF when KL27 wakes up if (power_source == PWR_BATT_ONLY || usb_state == USB_DISCONNECTED) { main_powerdown_event(); + + if (power_led_sleep_state_on == true) { + shutdown_led_dc = PWR_LED_ON_BATT_BRIGHTNESS; + } + else { + shutdown_led_dc = 0; + } } + main_shutdown_state = MAIN_SHUTDOWN_WAITING; break; case MAIN_SHUTDOWN_WAITING: @@ -498,13 +509,13 @@ static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { memcpy(&i2cResponse.cmdData.readRspCmd.data, &board_id_hex, sizeof(board_id_hex)); break; case gI2CProtocolVersion_c: { - uint32_t i2c_version = 1; + uint16_t i2c_version = 1; i2cResponse.cmdData.readRspCmd.dataSize = sizeof(i2c_version); memcpy(&i2cResponse.cmdData.readRspCmd.data, &i2c_version, sizeof(i2c_version)); } break; case gDAPLinkVersion_c: { - uint32_t daplink_version = DAPLINK_VERSION; + uint16_t daplink_version = DAPLINK_VERSION; i2cResponse.cmdData.readRspCmd.dataSize = sizeof(daplink_version); memcpy(&i2cResponse.cmdData.readRspCmd.data, &daplink_version, sizeof(daplink_version)); } @@ -524,7 +535,6 @@ static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { memcpy(&i2cResponse.cmdData.readRspCmd.data, &usb_state, sizeof(usb_state)); break; case gPowerMode_c: - case gNRFPowerMode_c: i2cResponse.cmdId = gErrorResponse_c; i2cResponse.cmdData.errorRspCmd.errorCode = gErrorReadDisallowed_c; break; @@ -578,9 +588,20 @@ static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWrongPropertySize_c; } break; - case gNRFPowerMode_c: - i2cResponse.cmdId = gErrorResponse_c; - i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWriteDisallowed_c; + case gPowerLedSleepState_c: + if (pI2cCommand->cmdData.writeReqCmd.dataSize == 1) { + if (pI2cCommand->cmdData.writeReqCmd.data[0] != 0) { + power_led_sleep_state_on = true; + } + else { + power_led_sleep_state_on = false; + } + i2cResponse.cmdId = gWriteResponse_c; + i2cResponse.cmdData.writeRspCmd.propertyId = pI2cCommand->cmdData.writeReqCmd.propertyId; + } else { + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWrongPropertySize_c; + } break; default: i2cResponse.cmdId = gErrorResponse_c; diff --git a/source/board/microbitv2/power.c b/source/board/microbitv2/power.c index e6f362c46..f8dcdde51 100644 --- a/source/board/microbitv2/power.c +++ b/source/board/microbitv2/power.c @@ -160,7 +160,6 @@ static void power_pre_switch_hook(smc_power_state_t originPowerState, app_power_ * UART TX pin: Don't need to change. */ PORT_SetPinMux(UART_PORT, PIN_UART_RX_BIT, kPORT_PinDisabledOrAnalog); - PORT_SetPinMux(PIN_RED_LED_PORT, PIN_RED_LED_BIT, kPORT_PinDisabledOrAnalog); PORT_SetPinMux(PIN_HID_LED_PORT, PIN_HID_LED_BIT, kPORT_PinDisabledOrAnalog); } @@ -171,7 +170,6 @@ static void power_post_switch_hook(smc_power_state_t originPowerState, app_power * UART TX pin: Don't need to change. */ PORT_SetPinMux(UART_PORT, PIN_UART_RX_BIT, (port_mux_t)PIN_UART_RX_MUX_ALT); - PORT_SetPinMux(PIN_RED_LED_PORT, PIN_RED_LED_BIT, kPORT_MuxAlt3); PORT_SetPinMux(PIN_HID_LED_PORT, PIN_HID_LED_BIT, kPORT_PinDisabledOrAnalog); uart_initialize(); From 84f1e9af2186d36d206d0ab53940bd9f3e33c57c Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Tue, 25 Aug 2020 20:18:49 -0500 Subject: [PATCH 216/617] Fix FlexIO clock ranges in assert --- source/board/microbitv2/flexio_pwm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/board/microbitv2/flexio_pwm.c b/source/board/microbitv2/flexio_pwm.c index 7d148faf9..a3196bf5f 100644 --- a/source/board/microbitv2/flexio_pwm.c +++ b/source/board/microbitv2/flexio_pwm.c @@ -60,7 +60,7 @@ void flexio_pwm_set_dutycycle(uint8_t duty) { uint32_t freq_Hz = DEMO_FLEXIO_FREQUENCY; - assert((freq_Hz < FLEXIO_MAX_FREQUENCY) && (freq_Hz > FLEXIO_MIN_FREQUENCY)); + assert((freq_Hz <= FLEXIO_MAX_FREQUENCY) && (freq_Hz >= FLEXIO_MIN_FREQUENCY)); uint32_t lowerValue = 0; /* Number of clock cycles in high logic state in one period */ uint32_t upperValue = 0; /* Number of clock cycles in low logic state in one period */ From 193e1562cdb1ae314d8945acb42ef35c2cb481d9 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Tue, 1 Sep 2020 12:22:29 -0500 Subject: [PATCH 217/617] #80 Add incompatible image detection feature in details.txt file. Add documentation on the feautre. --- docs/MSD_COMMANDS.md | 5 +++++ source/daplink/drag-n-drop/vfs_user.c | 3 +++ 2 files changed, 8 insertions(+) diff --git a/docs/MSD_COMMANDS.md b/docs/MSD_COMMANDS.md index 6b5903597..b70a555ac 100644 --- a/docs/MSD_COMMANDS.md +++ b/docs/MSD_COMMANDS.md @@ -82,3 +82,8 @@ data fast enough from DAPLink and an overflow occurs the text ``` Date: Tue, 1 Sep 2020 14:07:45 -0500 Subject: [PATCH 218/617] Validate allowed filename extensions in the I2C Flash interface (.bin, .txt, .csv, .htm, .wav). --- source/board/microbitv2/microbitv2.c | 41 ++++++++++++++++++++++++- source/daplink/drag-n-drop/virtual_fs.c | 3 +- source/daplink/drag-n-drop/virtual_fs.h | 4 +++ 3 files changed, 45 insertions(+), 3 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 09e66ea72..5118fdb96 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -642,6 +642,28 @@ static void i2c_read_comms_callback(uint8_t* pData, uint8_t size) { PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); } +static bool file_extension_valid(const vfs_filename_t filename) +{ + const char *valid_extensions[] = { + "BIN", + "TXT", + "CSV", + "HTM", + "WAV", + }; + uint32_t i; + + // Check for invalid starting characters + for (i = 0; i < (sizeof((valid_extensions))/sizeof((valid_extensions)[0])); i++) { + if (0 == memcmp(&filename[8], valid_extensions[i], 3)) { + return true; + } + } + + // Some checks failed so file extension is invalid + return false; +} + static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { i2cFlashCmd_t* pI2cCommand = (i2cFlashCmd_t*) pData; @@ -689,7 +711,24 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { } break; case gFlashCfgFileName_c: - memcpy(gflashConfig.fileName, pI2cCommand->cmdData.data, 11); + // Validate 8.3 filename + if (true != filename_valid((char *) pI2cCommand->cmdData.data) || size != 12) { + // Send error if invalid filename + i2c_clearBuffer(); + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } + else { + // Validate allowed extensions (.bin, .txt, .csv, .htm, .wav) + if ( true == file_extension_valid((char *) pI2cCommand->cmdData.data)) { + memcpy(gflashConfig.fileName, pI2cCommand->cmdData.data, 11); + } + // If invalid extension is requested, .bin will be used + else { + memcpy(gflashConfig.fileName, pI2cCommand->cmdData.data, 8); + memcpy(&gflashConfig.fileName[8], "BIN", 3); + } + } break; case gFlashCfgFileSize_c: gflashConfig.fileSizeKB = pI2cCommand->cmdData.data[0]; diff --git a/source/daplink/drag-n-drop/virtual_fs.c b/source/daplink/drag-n-drop/virtual_fs.c index 94c80bfb3..c8b903e3b 100644 --- a/source/daplink/drag-n-drop/virtual_fs.c +++ b/source/daplink/drag-n-drop/virtual_fs.c @@ -114,7 +114,6 @@ static void write_dir(uint32_t offset, const uint8_t *data, uint32_t size); static void file_change_cb_stub(const vfs_filename_t filename, vfs_file_change_t change, vfs_file_t file, vfs_file_t new_file_data); static uint32_t cluster_to_sector(uint32_t cluster_idx); -static bool filename_valid(const vfs_filename_t filename); static bool filename_character_valid(char character); // If sector size changes update comment below @@ -684,7 +683,7 @@ static uint32_t cluster_to_sector(uint32_t cluster_idx) return sectors_before_data + (cluster_idx - 2) * mbr.sectors_per_cluster; } -static bool filename_valid(const vfs_filename_t filename) +bool filename_valid(const vfs_filename_t filename) { // Information on valid 8.3 filenames can be found in // the microsoft hardware whitepaper: diff --git a/source/daplink/drag-n-drop/virtual_fs.h b/source/daplink/drag-n-drop/virtual_fs.h index 581017c8f..aa6713da2 100644 --- a/source/daplink/drag-n-drop/virtual_fs.h +++ b/source/daplink/drag-n-drop/virtual_fs.h @@ -23,6 +23,7 @@ #define VIRTUAL_FS_H #include +#include #ifdef __cplusplus extern "C" { @@ -101,6 +102,9 @@ void vfs_read(uint32_t sector, uint8_t *buf, uint32_t num_of_sectors); // Write one or more sectors to the virtual filesystem void vfs_write(uint32_t sector, const uint8_t *buf, uint32_t num_of_sectors); +// Validate 8.3 filenames +bool filename_valid(const vfs_filename_t filename); + #ifdef __cplusplus } #endif From 1712499c184d1934dc129cd1719b1902004a7213 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Thu, 3 Sep 2020 09:25:06 -0500 Subject: [PATCH 219/617] Update power handling for off/stand-by modes -Add property for Kl27 user event (wakeup or long button press) -Blink LED when attempting to enter deep sleep but are PC connected -Hold interrupt line to send I2C message on reset long press -Clear I2C responses after first read in the comms interface --- source/board/microbitv2/i2c_commands.h | 16 +++-- source/board/microbitv2/microbitv2.c | 91 +++++++++++++++++--------- 2 files changed, 72 insertions(+), 35 deletions(-) diff --git a/source/board/microbitv2/i2c_commands.h b/source/board/microbitv2/i2c_commands.h index 237efde42..80d44c72d 100644 --- a/source/board/microbitv2/i2c_commands.h +++ b/source/board/microbitv2/i2c_commands.h @@ -17,9 +17,9 @@ extern "C" { /*! i2c command Id type enumeration */ typedef enum cmdId_tag { - gReadRequest_c = 0x10, - gReadResponse_c = 0x11, - gWriteRequest_c = 0x12, + gReadRequest_c = 0x10, + gReadResponse_c = 0x11, + gWriteRequest_c = 0x12, gWriteResponse_c = 0x13, gErrorResponse_c = 0x20 } cmdId_t; @@ -33,9 +33,17 @@ typedef enum propertyId_tag { gPowerConsumption_c = 0x05, gUSBEnumerationState_c = 0x06, gPowerMode_c = 0x07, - gPowerLedSleepState_c = 0x08 + gPowerLedSleepState_c = 0x08, + gUserEvent_c = 0x09 } propertyId_t; +/*! user event type enumeration */ +typedef enum userEventType_tag { + gWakeFromResetButton_c = 0x01, + gWakeFromWakeOnEdge_c = 0x02, + gResetButtonLongPress_c = 0x03, +} userEventType_t; + /*! property Id type enumeration */ typedef enum errorCode_tag { gErrorSuccess = 0x30, diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 5118fdb96..9fe2e4b68 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -82,11 +82,14 @@ extern bool go_to_sleep; typedef enum main_shutdown_state { MAIN_SHUTDOWN_WAITING = 0, + MAIN_SHUTDOWN_WAITING_OFF, MAIN_SHUTDOWN_PENDING, MAIN_SHUTDOWN_REACHED, MAIN_SHUTDOWN_REACHED_FADE, + MAIN_SHUTDOWN_ALERT, MAIN_SHUTDOWN_REQUESTED, - MAIN_LED_BLINK, + MAIN_LED_BLINK_ONCE, + MAIN_LED_BLINKING, MAIN_LED_FULL_BRIGHTNESS, MAIN_SHUTDOWN_CANCEL } main_shutdown_state_t; @@ -107,6 +110,7 @@ static uint8_t initial_fade_brightness = PWR_LED_INIT_FADE_BRIGHTNESS; static bool power_led_sleep_state_on = true; static app_power_mode_t interface_power_mode = kAPP_PowerModeVlls0; static power_source_t power_source; +static main_usb_connect_t prev_usb_state; // reset button state count static uint16_t gpio_reset_count = 0; static bool do_remount = false; @@ -275,16 +279,15 @@ void handle_reset_button() reset_pressed = 0; if (gpio_reset_count <= RESET_SHORT_PRESS) { - main_shutdown_state = MAIN_LED_BLINK; + main_shutdown_state = MAIN_LED_BLINK_ONCE; } else if (gpio_reset_count < RESET_MID_PRESS) { // Indicate button has been released to stop to cancel the shutdown - main_shutdown_state = MAIN_LED_BLINK; + main_shutdown_state = MAIN_LED_BLINK_ONCE; } else if (gpio_reset_count >= RESET_MID_PRESS) { // Indicate the button has been released when shutdown is requested - interface_power_mode = kAPP_PowerModeVlls0; - main_shutdown_state = MAIN_SHUTDOWN_REQUESTED; + main_shutdown_state = MAIN_SHUTDOWN_ALERT; } } else if (reset_pressed && gpio_get_reset_btn_fwrd()) { // Reset button is still pressed @@ -326,6 +329,11 @@ void board_30ms_hook() PIN_HID_LED_PORT->PCR[PIN_HID_LED_BIT] = PORT_PCR_MUX(0); power_led_max_duty_cycle = PWR_LED_ON_BATT_BRIGHTNESS; } + + if (prev_usb_state != usb_state) { + power_source = pwr_mon_get_power_source(); + } + prev_usb_state = usb_state; switch (main_shutdown_state) { case MAIN_LED_FULL_BRIGHTNESS: @@ -351,26 +359,55 @@ void board_30ms_hook() shutdown_led_dc--; } break; + case MAIN_SHUTDOWN_ALERT: + { + // Assert the interrupt line and prepare I2C response + i2cCommand_t i2cResponse = {0}; + i2cResponse.cmdId = gReadResponse_c; + i2cResponse.cmdData.readRspCmd.propertyId = (uint8_t) gUserEvent_c; + i2cResponse.cmdData.readRspCmd.dataSize = 1; + i2cResponse.cmdData.readRspCmd.data[0] = gResetButtonLongPress_c; + + i2c_fillBuffer((uint8_t*) &i2cResponse, 0, sizeof(i2cResponse)); + + // Response ready, assert COMBINED_SENSOR_INT + PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_MuxAsGpio); + + // Keep LED off + main_shutdown_state = MAIN_SHUTDOWN_WAITING_OFF; + } + break; case MAIN_SHUTDOWN_REQUESTED: - // TODO: put nRF into deep sleep and wake nRF when KL27 wakes up if (power_source == PWR_BATT_ONLY || usb_state == USB_DISCONNECTED) { main_powerdown_event(); - - if (power_led_sleep_state_on == true) { - shutdown_led_dc = PWR_LED_ON_BATT_BRIGHTNESS; - } - else { - shutdown_led_dc = 0; - } + shutdown_led_dc = 0; + main_shutdown_state = MAIN_SHUTDOWN_WAITING; + } + else { + main_shutdown_state = MAIN_LED_BLINKING; } - main_shutdown_state = MAIN_SHUTDOWN_WAITING; break; case MAIN_SHUTDOWN_WAITING: // Set the PWM value back to max duty cycle shutdown_led_dc = power_led_max_duty_cycle; break; - case MAIN_LED_BLINK: + case MAIN_SHUTDOWN_WAITING_OFF: + shutdown_led_dc = 0; + break; + case MAIN_LED_BLINKING: + // Blink the LED to indicate standby mode + if (shutdown_led_dc < 10) { + shutdown_led_dc++; + } else if (shutdown_led_dc == 10) { + shutdown_led_dc = 100; + } else if (shutdown_led_dc <= 90) { + shutdown_led_dc = 0; + } else if (shutdown_led_dc > 90) { + shutdown_led_dc--; + } + break; + case MAIN_LED_BLINK_ONCE: if (blink_in_progress) { blink_in_progress--; @@ -562,23 +599,13 @@ static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { case gPowerMode_c: if (pI2cCommand->cmdData.writeReqCmd.dataSize == 1) { if (pI2cCommand->cmdData.writeReqCmd.data[0] == kAPP_PowerModeVlls0) { - if (power_source == PWR_BATT_ONLY || usb_state == USB_DISCONNECTED) { - interface_power_mode = kAPP_PowerModeVlls0; - i2cResponse.cmdId = gWriteResponse_c; - i2cResponse.cmdData.writeRspCmd.propertyId = pI2cCommand->cmdData.writeReqCmd.propertyId; - } else { - i2cResponse.cmdId = gErrorResponse_c; - i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWriteDisallowed_c; - } + interface_power_mode = kAPP_PowerModeVlls0; + i2cResponse.cmdId = gWriteResponse_c; + i2cResponse.cmdData.writeRspCmd.propertyId = pI2cCommand->cmdData.writeReqCmd.propertyId; } else if (pI2cCommand->cmdData.writeReqCmd.data[0] == kAPP_PowerModeVlps) { - if (power_source == PWR_BATT_ONLY || usb_state == USB_DISCONNECTED) { - interface_power_mode = kAPP_PowerModeVlps; - i2cResponse.cmdId = gWriteResponse_c; - i2cResponse.cmdData.writeRspCmd.propertyId = pI2cCommand->cmdData.writeReqCmd.propertyId; - } else { - i2cResponse.cmdId = gErrorResponse_c; - i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWriteDisallowed_c; - } + interface_power_mode = kAPP_PowerModeVlps; + i2cResponse.cmdId = gWriteResponse_c; + i2cResponse.cmdData.writeRspCmd.propertyId = pI2cCommand->cmdData.writeReqCmd.propertyId; } else { i2cResponse.cmdId = gErrorResponse_c; i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWriteFail_c; @@ -638,6 +665,8 @@ static void i2c_read_comms_callback(uint8_t* pData, uint8_t size) { break; } + i2c_clearBuffer(); + // Release COMBINED_SENSOR_INT PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); } From d757dd9cd273807b844e5866c869befa1d84f173 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Thu, 3 Sep 2020 09:34:48 -0500 Subject: [PATCH 220/617] #33 Update error app from https://github.com/microbit-foundation/standalone-error-program/ at d472f7a --- source/board/microbitv2/led_error_app.h | 118 ++++++++++++------------ 1 file changed, 58 insertions(+), 60 deletions(-) diff --git a/source/board/microbitv2/led_error_app.h b/source/board/microbitv2/led_error_app.h index d5fd37d20..f927d978c 100644 --- a/source/board/microbitv2/led_error_app.h +++ b/source/board/microbitv2/led_error_app.h @@ -1,9 +1,9 @@ // Program to display error code 0-999 on LEDs: face,E,digit,digit,digit -unsigned int led_error_bin_len = 2036; +unsigned int led_error_bin_len = 2016; // Offset of 2 byte error code, low byte first -unsigned int led_error_bin_code = 1928; +unsigned int led_error_bin_code = 1908; unsigned char led_error_bin_data[] = { 0x00, 0x00, 0x02, 0x20, 0xb5, 0x02, 0x00, 0x00, 0xdd, 0x02, 0x00, 0x00, @@ -51,22 +51,22 @@ unsigned char led_error_bin_data[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0xb5, 0x05, 0x4c, 0x23, 0x78, 0x33, 0xb9, 0x04, 0x4b, 0x13, 0xb1, 0x04, 0x48, 0xaf, 0xf3, 0x00, 0x80, 0x01, 0x23, 0x23, 0x70, 0x10, 0xbd, 0x74, 0x00, 0x00, 0x20, - 0x00, 0x00, 0x00, 0x00, 0x74, 0x07, 0x00, 0x00, 0x08, 0xb5, 0x03, 0x4b, + 0x00, 0x00, 0x00, 0x00, 0x60, 0x07, 0x00, 0x00, 0x08, 0xb5, 0x03, 0x4b, 0x1b, 0xb1, 0x03, 0x49, 0x03, 0x48, 0xaf, 0xf3, 0x00, 0x80, 0x08, 0xbd, - 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x20, 0x74, 0x07, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x20, 0x60, 0x07, 0x00, 0x00, 0x15, 0x4b, 0x00, 0x2b, 0x08, 0xbf, 0x13, 0x4b, 0x9d, 0x46, 0xa3, 0xf5, 0x80, 0x3a, 0x00, 0x21, 0x8b, 0x46, 0x0f, 0x46, 0x13, 0x48, 0x14, 0x4a, - 0x12, 0x1a, 0x00, 0xf0, 0x4f, 0xfa, 0x0f, 0x4b, 0x00, 0x2b, 0x00, 0xd0, + 0x12, 0x1a, 0x00, 0xf0, 0x47, 0xfa, 0x0f, 0x4b, 0x00, 0x2b, 0x00, 0xd0, 0x98, 0x47, 0x0e, 0x4b, 0x00, 0x2b, 0x00, 0xd0, 0x98, 0x47, 0x00, 0x20, 0x00, 0x21, 0x04, 0x00, 0x0d, 0x00, 0x0d, 0x48, 0x00, 0x28, 0x02, 0xd0, - 0x0c, 0x48, 0xaf, 0xf3, 0x00, 0x80, 0x00, 0xf0, 0x17, 0xfa, 0x20, 0x00, - 0x29, 0x00, 0x00, 0xf0, 0xf5, 0xf9, 0x00, 0xf0, 0xfd, 0xf9, 0x00, 0xbf, + 0x0c, 0x48, 0xaf, 0xf3, 0x00, 0x80, 0x00, 0xf0, 0x0f, 0xfa, 0x20, 0x00, + 0x29, 0x00, 0x00, 0xf0, 0xed, 0xf9, 0x00, 0xf0, 0xf5, 0xf9, 0x00, 0xbf, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x74, 0x00, 0x00, 0x20, 0x90, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x49, 0x07, 0x4a, 0x07, 0x4b, 0x9b, 0x1a, 0x03, 0xdd, 0x04, 0x3b, 0xc8, 0x58, 0xd0, 0x50, 0xfb, 0xdc, 0x00, 0xf0, 0x2f, 0xf8, 0xff, 0xf7, 0xb9, 0xff, 0x00, 0x00, - 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x74, 0x00, 0x00, 0x20, + 0x6c, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x74, 0x00, 0x00, 0x20, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xbf, 0xf3, 0x4f, 0x8f, 0x05, 0x49, 0x06, 0x4b, 0xca, 0x68, 0x02, 0xf4, 0xe0, 0x62, 0x13, 0x43, @@ -119,61 +119,59 @@ unsigned char led_error_bin_data[] = { 0x0b, 0x4d, 0x1e, 0x20, 0xff, 0xf7, 0xcc, 0xff, 0x00, 0x22, 0x01, 0x20, 0x13, 0x5d, 0x1f, 0x2b, 0x86, 0xbf, 0x03, 0xf0, 0x1f, 0x03, 0x29, 0x46, 0x4f, 0xf0, 0xa0, 0x41, 0x01, 0x32, 0x00, 0xfa, 0x03, 0xf3, 0x05, 0x2a, - 0xc1, 0xf8, 0x0c, 0x35, 0xf0, 0xd1, 0x38, 0xbd, 0x69, 0x07, 0x00, 0x00, - 0x00, 0x03, 0x00, 0x50, 0x2d, 0xe9, 0xf8, 0x4f, 0x80, 0x46, 0x3e, 0x48, - 0x3e, 0x4d, 0x00, 0x22, 0x82, 0x46, 0x03, 0x24, 0x13, 0x5c, 0x1f, 0x2b, + 0xc1, 0xf8, 0x0c, 0x35, 0xf0, 0xd1, 0x38, 0xbd, 0x54, 0x07, 0x00, 0x00, + 0x00, 0x03, 0x00, 0x50, 0x2d, 0xe9, 0xf8, 0x4f, 0x80, 0x46, 0x3b, 0x48, + 0x3b, 0x4d, 0x00, 0x22, 0x82, 0x46, 0x03, 0x24, 0x13, 0x5c, 0x1f, 0x2b, 0x86, 0xbf, 0x03, 0xf0, 0x1f, 0x03, 0x29, 0x46, 0x4f, 0xf0, 0xa0, 0x41, 0x03, 0xf5, 0xe0, 0x73, 0x01, 0x32, 0x05, 0x2a, 0x41, 0xf8, 0x23, 0x40, - 0xf0, 0xd1, 0x36, 0x48, 0x34, 0x4d, 0x00, 0x22, 0x03, 0x24, 0x13, 0x5c, + 0xf0, 0xd1, 0x33, 0x48, 0x31, 0x4d, 0x00, 0x22, 0x03, 0x24, 0x13, 0x5c, 0x1f, 0x2b, 0x86, 0xbf, 0x03, 0xf0, 0x1f, 0x03, 0x29, 0x46, 0x4f, 0xf0, 0xa0, 0x41, 0x03, 0xf5, 0xe0, 0x73, 0x01, 0x32, 0x05, 0x2a, 0x41, 0xf8, 0x23, 0x40, 0xf0, 0xd1, 0xff, 0xf7, 0xac, 0xff, 0x4f, 0xf0, 0x01, 0x09, - 0x00, 0x25, 0x01, 0x2d, 0x46, 0xdc, 0x2a, 0x4c, 0x2a, 0x4b, 0x00, 0x2d, - 0x08, 0xbf, 0x1c, 0x46, 0x0e, 0xe0, 0x01, 0x39, 0x93, 0xfb, 0xf2, 0xf3, - 0x02, 0x29, 0xfa, 0xd1, 0x98, 0xfb, 0xf3, 0xf3, 0x93, 0xfb, 0xf2, 0xf4, - 0x02, 0xfb, 0x14, 0x34, 0x23, 0x4b, 0x04, 0xeb, 0x84, 0x04, 0x1c, 0x44, - 0x32, 0x27, 0x00, 0x26, 0x1d, 0x4b, 0x98, 0x5d, 0xff, 0xf7, 0x6a, 0xff, - 0x4f, 0xf0, 0x00, 0x0b, 0x32, 0x46, 0x59, 0x46, 0x20, 0x46, 0x1a, 0xf8, - 0x0b, 0x30, 0xff, 0xf7, 0x71, 0xff, 0x28, 0xbb, 0x1f, 0x2b, 0x86, 0xbf, - 0x03, 0xf0, 0x1f, 0x03, 0x13, 0x4a, 0x4f, 0xf0, 0xa0, 0x42, 0x09, 0xfa, - 0x03, 0xf3, 0xc2, 0xf8, 0x0c, 0x35, 0x0b, 0xf1, 0x01, 0x0b, 0xbb, 0xf1, - 0x05, 0x0f, 0xe7, 0xd1, 0x44, 0xf6, 0x20, 0x60, 0x01, 0x36, 0xff, 0xf7, - 0x63, 0xff, 0xff, 0xf7, 0x6b, 0xff, 0x05, 0x2e, 0xd8, 0xd1, 0x01, 0x3f, - 0xd5, 0xd1, 0x0d, 0x48, 0x01, 0x35, 0xff, 0xf7, 0x59, 0xff, 0x05, 0x2d, - 0xb7, 0xd1, 0xb5, 0xe7, 0x29, 0x46, 0x64, 0x23, 0x0a, 0x22, 0xbd, 0xe7, - 0x18, 0x46, 0xff, 0xf7, 0x37, 0xff, 0xe0, 0xe7, 0x5f, 0x07, 0x00, 0x00, - 0x00, 0x03, 0x00, 0x50, 0x69, 0x07, 0x00, 0x00, 0x28, 0x07, 0x00, 0x00, - 0x64, 0x07, 0x00, 0x00, 0x2d, 0x07, 0x00, 0x00, 0xa0, 0x86, 0x01, 0x00, - 0x08, 0xb5, 0x03, 0x4b, 0x98, 0x88, 0xff, 0xf7, 0x6d, 0xff, 0x00, 0x20, - 0x08, 0xbd, 0x00, 0xbf, 0x04, 0x00, 0x00, 0x20, 0x08, 0xb5, 0x07, 0x4b, - 0x04, 0x46, 0x13, 0xb1, 0x00, 0x21, 0xaf, 0xf3, 0x00, 0x80, 0x05, 0x4b, - 0x18, 0x68, 0x83, 0x6a, 0x03, 0xb1, 0x98, 0x47, 0x20, 0x46, 0x00, 0xf0, - 0x31, 0xf8, 0x00, 0xbf, 0x00, 0x00, 0x00, 0x00, 0x70, 0x07, 0x00, 0x00, - 0x70, 0xb5, 0x0d, 0x4e, 0x0d, 0x4c, 0xa4, 0x1b, 0xa4, 0x10, 0x00, 0x25, - 0xa5, 0x42, 0x09, 0xd1, 0x0b, 0x4e, 0x0c, 0x4c, 0x00, 0xf0, 0x22, 0xf8, - 0xa4, 0x1b, 0xa4, 0x10, 0x00, 0x25, 0xa5, 0x42, 0x05, 0xd1, 0x70, 0xbd, - 0x56, 0xf8, 0x25, 0x30, 0x98, 0x47, 0x01, 0x35, 0xee, 0xe7, 0x56, 0xf8, - 0x25, 0x30, 0x98, 0x47, 0x01, 0x35, 0xf2, 0xe7, 0x6c, 0x00, 0x00, 0x20, - 0x6c, 0x00, 0x00, 0x20, 0x6c, 0x00, 0x00, 0x20, 0x70, 0x00, 0x00, 0x20, - 0x02, 0x44, 0x03, 0x46, 0x93, 0x42, 0x00, 0xd1, 0x70, 0x47, 0x03, 0xf8, - 0x01, 0x1b, 0xf9, 0xe7, 0xfe, 0xe7, 0x00, 0xbf, 0xf8, 0xb5, 0x00, 0xbf, - 0xf8, 0xbc, 0x08, 0xbc, 0x9e, 0x46, 0x70, 0x47, 0xf8, 0xb5, 0x00, 0xbf, - 0xf8, 0xbc, 0x08, 0xbc, 0x9e, 0x46, 0x70, 0x47, 0x1e, 0xd0, 0x1c, 0x90, - 0x1e, 0x0c, 0x92, 0x52, 0x52, 0x4c, 0x04, 0x8c, 0x84, 0x84, 0x8e, 0x1c, - 0x82, 0x4c, 0x90, 0x1e, 0x1e, 0xc2, 0x44, 0x92, 0x4c, 0x06, 0xca, 0x52, - 0x5f, 0xe2, 0x1f, 0xf0, 0x1e, 0xc1, 0x3e, 0x02, 0x44, 0x8e, 0xd1, 0x2e, - 0x1f, 0xe2, 0x44, 0x88, 0x10, 0x0e, 0xd1, 0x2e, 0xd1, 0x2e, 0x0e, 0xd1, - 0x2e, 0xc4, 0x88, 0x1c, 0x0b, 0x1f, 0x25, 0x1e, 0x1b, 0x1b, 0x00, 0x0e, - 0x11, 0x15, 0x16, 0x0f, 0x18, 0x13, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x20, - 0x00, 0x00, 0x00, 0x00, 0xc8, 0xfa, 0xff, 0x7f, 0x01, 0x00, 0x00, 0x00, - 0x00, 0x90, 0xd0, 0x03, 0xde, 0xc0, 0xce, 0xfa, 0x46, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x25, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00 + 0x28, 0x4c, 0x00, 0x26, 0x32, 0x27, 0x00, 0x25, 0x25, 0x4b, 0x58, 0x5d, + 0xff, 0xf7, 0x80, 0xff, 0x4f, 0xf0, 0x00, 0x0b, 0x2a, 0x46, 0x59, 0x46, + 0x20, 0x46, 0x1a, 0xf8, 0x0b, 0x30, 0xff, 0xf7, 0x87, 0xff, 0xa0, 0xbb, + 0x1f, 0x2b, 0x86, 0xbf, 0x03, 0xf0, 0x1f, 0x03, 0x1b, 0x4a, 0x4f, 0xf0, + 0xa0, 0x42, 0x09, 0xfa, 0x03, 0xf3, 0xc2, 0xf8, 0x0c, 0x35, 0x0b, 0xf1, + 0x01, 0x0b, 0xbb, 0xf1, 0x05, 0x0f, 0xe7, 0xd1, 0x44, 0xf6, 0x20, 0x60, + 0x01, 0x35, 0xff, 0xf7, 0x79, 0xff, 0xff, 0xf7, 0x81, 0xff, 0x05, 0x2d, + 0xd8, 0xd1, 0x01, 0x3f, 0xd5, 0xd1, 0x13, 0x48, 0x01, 0x36, 0xff, 0xf7, + 0x6f, 0xff, 0x04, 0x2e, 0xcc, 0xd0, 0x31, 0x46, 0x64, 0x23, 0x0a, 0x22, + 0x02, 0xe0, 0x01, 0x39, 0x93, 0xfb, 0xf2, 0xf3, 0x01, 0x29, 0xfa, 0xd1, + 0x98, 0xfb, 0xf3, 0xf3, 0x93, 0xfb, 0xf2, 0xf4, 0x02, 0xfb, 0x14, 0x34, + 0x09, 0x4b, 0x04, 0xeb, 0x84, 0x04, 0x1c, 0x44, 0xba, 0xe7, 0x18, 0x46, + 0xff, 0xf7, 0x3e, 0xff, 0xd1, 0xe7, 0x00, 0xbf, 0x4a, 0x07, 0x00, 0x00, + 0x00, 0x03, 0x00, 0x50, 0x54, 0x07, 0x00, 0x00, 0x4f, 0x07, 0x00, 0x00, + 0x40, 0x42, 0x0f, 0x00, 0x18, 0x07, 0x00, 0x00, 0x08, 0xb5, 0x03, 0x4b, + 0x98, 0x88, 0xff, 0xf7, 0x75, 0xff, 0x00, 0x20, 0x08, 0xbd, 0x00, 0xbf, + 0x04, 0x00, 0x00, 0x20, 0x08, 0xb5, 0x07, 0x4b, 0x04, 0x46, 0x13, 0xb1, + 0x00, 0x21, 0xaf, 0xf3, 0x00, 0x80, 0x05, 0x4b, 0x18, 0x68, 0x83, 0x6a, + 0x03, 0xb1, 0x98, 0x47, 0x20, 0x46, 0x00, 0xf0, 0x31, 0xf8, 0x00, 0xbf, + 0x00, 0x00, 0x00, 0x00, 0x5c, 0x07, 0x00, 0x00, 0x70, 0xb5, 0x0d, 0x4e, + 0x0d, 0x4c, 0xa4, 0x1b, 0xa4, 0x10, 0x00, 0x25, 0xa5, 0x42, 0x09, 0xd1, + 0x0b, 0x4e, 0x0c, 0x4c, 0x00, 0xf0, 0x22, 0xf8, 0xa4, 0x1b, 0xa4, 0x10, + 0x00, 0x25, 0xa5, 0x42, 0x05, 0xd1, 0x70, 0xbd, 0x56, 0xf8, 0x25, 0x30, + 0x98, 0x47, 0x01, 0x35, 0xee, 0xe7, 0x56, 0xf8, 0x25, 0x30, 0x98, 0x47, + 0x01, 0x35, 0xf2, 0xe7, 0x6c, 0x00, 0x00, 0x20, 0x6c, 0x00, 0x00, 0x20, + 0x6c, 0x00, 0x00, 0x20, 0x70, 0x00, 0x00, 0x20, 0x02, 0x44, 0x03, 0x46, + 0x93, 0x42, 0x00, 0xd1, 0x70, 0x47, 0x03, 0xf8, 0x01, 0x1b, 0xf9, 0xe7, + 0xfe, 0xe7, 0x00, 0xbf, 0xf8, 0xb5, 0x00, 0xbf, 0xf8, 0xbc, 0x08, 0xbc, + 0x9e, 0x46, 0x70, 0x47, 0xf8, 0xb5, 0x00, 0xbf, 0xf8, 0xbc, 0x08, 0xbc, + 0x9e, 0x46, 0x70, 0x47, 0x0c, 0x92, 0x52, 0x52, 0x4c, 0x04, 0x8c, 0x84, + 0x84, 0x8e, 0x1c, 0x82, 0x4c, 0x90, 0x1e, 0x1e, 0xc2, 0x44, 0x92, 0x4c, + 0x06, 0xca, 0x52, 0x5f, 0xe2, 0x1f, 0xf0, 0x1e, 0xc1, 0x3e, 0x02, 0x44, + 0x8e, 0xd1, 0x2e, 0x1f, 0xe2, 0x44, 0x88, 0x10, 0x0e, 0xd1, 0x2e, 0xd1, + 0x2e, 0x0e, 0xd1, 0x2e, 0xc4, 0x88, 0x1c, 0x0b, 0x1f, 0x25, 0x1e, 0x1b, + 0x1b, 0x00, 0x0e, 0x11, 0x15, 0x16, 0x0f, 0x18, 0x13, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xdc, 0xfa, 0xff, 0x7f, + 0x01, 0x00, 0x00, 0x00, 0x00, 0x90, 0xd0, 0x03, 0xde, 0xc0, 0xce, 0xfa, + 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x25, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00 }; From 37d3a53ea96e46ef738c218a090e5902d84d711f Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Thu, 3 Sep 2020 20:43:52 -0500 Subject: [PATCH 221/617] Update wake from deep sleep handling -Change wake up when the reset button is pressed instead of released -Add hook in bootloader project to bypass reset button check to jump directly to the interface -Reset the nRF whenever we wakeup from the reset button independently of the press duration --- source/board/kl27z_microbit_bl.c | 16 ++++++++++++++++ source/board/microbitv2/IO_Config_Override.h | 4 ++-- source/board/microbitv2/microbitv2.c | 5 ++++- source/board/microbitv2/power.c | 7 +++---- source/daplink/bootloader/main_bootloader.c | 7 ++++++- 5 files changed, 31 insertions(+), 8 deletions(-) diff --git a/source/board/kl27z_microbit_bl.c b/source/board/kl27z_microbit_bl.c index f2cf061d8..8f65423b5 100644 --- a/source/board/kl27z_microbit_bl.c +++ b/source/board/kl27z_microbit_bl.c @@ -24,6 +24,8 @@ #include "compiler.h" #include "target_board.h" #include "target_family.h" +#include "fsl_device_registers.h" +#include "gpio.h" // Warning - changing the interface start will break backwards compatibility COMPILER_ASSERT(DAPLINK_ROM_IF_START == KB(32)); @@ -62,3 +64,17 @@ const board_info_t g_board_info = { .daplink_target_url = "https://microbit.org/device/?id=@B&v=@V&bl=1", .target_cfg = &target_device, }; + +bool reset_button_pressed() +{ + bool btn_pressed = false; + // Bypass button check if we are waking from Low Leakage Wakeup Reset + if (RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) { + btn_pressed = false; + } + else { + btn_pressed = gpio_get_reset_btn(); + } + + return btn_pressed; +} diff --git a/source/board/microbitv2/IO_Config_Override.h b/source/board/microbitv2/IO_Config_Override.h index 2668ab62a..5e7309c88 100644 --- a/source/board/microbitv2/IO_Config_Override.h +++ b/source/board/microbitv2/IO_Config_Override.h @@ -100,8 +100,8 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_KL27Z); #define SW_RESET_PRESSED (0) #define SW_RESET_NOT_PRESSED (1) #define PIN_SW_RESET_LLWU_PIN (14) -#define PIN_SW_RESET_LLWU_WAKEUP_TYPE kLLWU_ExternalPinRisingEdge -#define PIN_SW_RESET_PORT_WAKEUP_TYPE kPORT_InterruptRisingEdge +#define PIN_SW_RESET_LLWU_WAKEUP_TYPE kLLWU_ExternalPinFallingEdge +#define PIN_SW_RESET_PORT_WAKEUP_TYPE kPORT_InterruptFallingEdge // WAKE_ON_EDGE PTC4 #define PIN_WAKE_ON_EDGE_PORT PORTC diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 9fe2e4b68..1a0d0e599 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -71,6 +71,8 @@ const char * const board_id_mb_2_1 = "9904"; uint16_t board_id_hex_min = 0x9903; uint16_t board_id_hex = 0; +volatile uint8_t wake_from_reset = 0; + typedef enum { BOARD_VERSION_2_0 = 0, BOARD_VERSION_2_1 = 1, @@ -262,7 +264,7 @@ void handle_reset_button() static uint8_t reset_pressed = 0; // handle reset button without eventing - if (!reset_pressed && gpio_get_reset_btn_fwrd()) { + if (!reset_pressed && (gpio_get_reset_btn_fwrd() || wake_from_reset)) { #ifdef DRAG_N_DROP_SUPPORT if (!flash_intf_target->flash_busy()) //added checking if flashing on target is in progress #endif @@ -271,6 +273,7 @@ void handle_reset_button() target_set_state(RESET_HOLD); reset_pressed = 1; gpio_reset_count = 0; + wake_from_reset = 0; main_shutdown_state = MAIN_LED_FULL_BRIGHTNESS; } } else if (reset_pressed && !gpio_get_reset_btn_fwrd()) { diff --git a/source/board/microbitv2/power.c b/source/board/microbitv2/power.c index f8dcdde51..0a15920e0 100644 --- a/source/board/microbitv2/power.c +++ b/source/board/microbitv2/power.c @@ -23,6 +23,8 @@ static void power_pre_switch_hook(smc_power_state_t originPowerState, app_power_ static void power_post_switch_hook(smc_power_state_t originPowerState, app_power_mode_t targetMode); static void power_enter_mode(app_power_mode_t targetPowerMode); +extern volatile uint8_t wake_from_reset; + /******************************************************************************* * Code ******************************************************************************/ @@ -31,14 +33,12 @@ void LLWU_IRQHandler(void) /* If wakeup by external pin BTN_NOT_PRESSED. */ if (LLWU_GetExternalWakeupPinFlag(LLWU, PIN_SW_RESET_LLWU_PIN)) { - PORT_SetPinInterruptConfig(PIN_SW_RESET_PORT, PIN_SW_RESET_BIT, kPORT_InterruptOrDMADisabled); - PORT_ClearPinsInterruptFlags(PIN_SW_RESET_PORT, (1U << PIN_SW_RESET_BIT)); LLWU_ClearExternalWakeupPinFlag(LLWU, PIN_SW_RESET_LLWU_PIN); + wake_from_reset = 1; } /* If wakeup by external pin WAKE_ON_EDGE. */ if (LLWU_GetExternalWakeupPinFlag(LLWU, PIN_WAKE_ON_EDGE_LLWU_PIN)) { - PORT_ClearPinsInterruptFlags(PIN_WAKE_ON_EDGE_PORT, (1U << PIN_WAKE_ON_EDGE_BIT)); LLWU_ClearExternalWakeupPinFlag(LLWU, PIN_WAKE_ON_EDGE_LLWU_PIN); } } @@ -71,7 +71,6 @@ void power_init(void) if (kRCM_SourceWakeup & RCM_GetPreviousResetSources(RCM)) /* Wakeup from VLLS. */ { PMC_ClearPeriphIOIsolationFlag(PMC); - NVIC_ClearPendingIRQ(LLWU_IRQn); } /* Enable rising edge interrupt on WAKE_ON_EDGE pin (VBUS falling edge) to detect USB detach */ diff --git a/source/daplink/bootloader/main_bootloader.c b/source/daplink/bootloader/main_bootloader.c index f4b9541cd..74eeb85ca 100644 --- a/source/daplink/bootloader/main_bootloader.c +++ b/source/daplink/bootloader/main_bootloader.c @@ -100,6 +100,11 @@ static main_led_state_t msc_led_state = MAIN_LED_FLASH; static main_usb_busy_t usb_busy; static uint32_t usb_busy_count; +__WEAK bool reset_button_pressed() +{ + return gpio_get_reset_btn(); +} + // Timer task, set flags every 30mS and 90mS void timer_task_30mS(void * arg) { @@ -262,7 +267,7 @@ int main(void) // check for invalid app image or rst button press. Should be checksum or CRC but NVIC validation is better than nothing. // If the interface has set the hold in bootloader setting don't jump to app - if (!gpio_get_reset_btn() + if (!reset_button_pressed() && g_board_info.target_cfg && validate_bin_nvic((uint8_t *)g_board_info.target_cfg->flash_regions[0].start) && !config_ram_get_initial_hold_in_bl()) { From ed1cebb060b8219b2ec7f28e5db4ff170c8e3356 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Mon, 7 Sep 2020 17:38:51 -0500 Subject: [PATCH 222/617] Red LED updates -Keep red LED ON after a long press. -When the reset button is pressed, the KL27 will reset the `Power LED Sleep state` value to the default ON -Red LED in deep sleep mode now depends on the `Power LED Sleep state` it can be either HIGH or LOW but no PWM. --- source/board/microbitv2/microbitv2.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 1a0d0e599..5ef8000ec 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -280,6 +280,7 @@ void handle_reset_button() // Reset button released target_set_state(RESET_RUN); reset_pressed = 0; + power_led_sleep_state_on = true; if (gpio_reset_count <= RESET_SHORT_PRESS) { main_shutdown_state = MAIN_LED_BLINK_ONCE; @@ -376,20 +377,28 @@ void board_30ms_hook() // Response ready, assert COMBINED_SENSOR_INT PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_MuxAsGpio); - // Keep LED off - main_shutdown_state = MAIN_SHUTDOWN_WAITING_OFF; + // Return LED to ON after release of long press + main_shutdown_state = MAIN_SHUTDOWN_WAITING; } break; case MAIN_SHUTDOWN_REQUESTED: if (power_source == PWR_BATT_ONLY || usb_state == USB_DISCONNECTED) { main_powerdown_event(); - shutdown_led_dc = 0; + + // In VLLS0, set the LED either ON or LOW, depending on power_led_sleep_state_on + // When the duty cycle is 0% or 100%, the FlexIO driver will configure the pin as GPIO + if (power_led_sleep_state_on == true) { + shutdown_led_dc = PWR_LED_ON_MAX_BRIGHTNESS; + } + else { + shutdown_led_dc = 0; + } + main_shutdown_state = MAIN_SHUTDOWN_WAITING; } else { main_shutdown_state = MAIN_LED_BLINKING; } - break; case MAIN_SHUTDOWN_WAITING: // Set the PWM value back to max duty cycle From d182a1c106547fc00ab66d5b9312d579aa904e86 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Wed, 9 Sep 2020 23:25:05 -0500 Subject: [PATCH 223/617] Delay deep sleep requests after we have determined if USB is enumerated or not. --- source/board/microbitv2/microbitv2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 5ef8000ec..27e8db44e 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -396,7 +396,7 @@ void board_30ms_hook() main_shutdown_state = MAIN_SHUTDOWN_WAITING; } - else { + else if (usb_state == USB_CONNECTED){ main_shutdown_state = MAIN_LED_BLINKING; } break; From db45927c62df967145ee0b339866760fcce078dd Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Thu, 10 Sep 2020 00:14:11 -0500 Subject: [PATCH 224/617] Reset usb timeout counters for the next time we want to connect --- source/daplink/interface/main_interface.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/source/daplink/interface/main_interface.c b/source/daplink/interface/main_interface.c index 01bbbb4cf..a0460bac0 100644 --- a/source/daplink/interface/main_interface.c +++ b/source/daplink/interface/main_interface.c @@ -420,6 +420,8 @@ void main_task(void * arg) } else { usb_state = USB_DISCONNECTED; + usb_state_count = USB_CONNECT_DELAY; + usb_no_config_count = USB_CONFIGURE_TIMEOUT; } default: break; From 2a8b346209f531e1e28f8c2b03b9b67505b58748 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Thu, 10 Sep 2020 00:30:57 -0500 Subject: [PATCH 225/617] Enter light sleep when idle --- source/board/microbitv2/microbitv2.c | 35 +++++++++++++++++----------- 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 27e8db44e..0a1c21306 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -324,20 +324,26 @@ void board_30ms_hook() static uint8_t blink_in_progress = 0; if (usb_state == USB_CONNECTED) { - // configure pin as GPIO - PIN_HID_LED_PORT->PCR[PIN_HID_LED_BIT] = PORT_PCR_MUX(1); - power_led_max_duty_cycle = PWR_LED_ON_MAX_BRIGHTNESS; + // configure pin as GPIO + PIN_HID_LED_PORT->PCR[PIN_HID_LED_BIT] = PORT_PCR_MUX(1); + power_led_max_duty_cycle = PWR_LED_ON_MAX_BRIGHTNESS; } else if (usb_state == USB_DISCONNECTED) { - // Disable pin - PIN_HID_LED_PORT->PCR[PIN_HID_LED_BIT] = PORT_PCR_MUX(0); - power_led_max_duty_cycle = PWR_LED_ON_BATT_BRIGHTNESS; + // Disable pin + PIN_HID_LED_PORT->PCR[PIN_HID_LED_BIT] = PORT_PCR_MUX(0); + power_led_max_duty_cycle = PWR_LED_ON_BATT_BRIGHTNESS; } if (prev_usb_state != usb_state) { - power_source = pwr_mon_get_power_source(); + power_source = pwr_mon_get_power_source(); } prev_usb_state = usb_state; + + // Enter light sleep if USB is not enumerated and main_shutdown_state is idle + if (usb_state == USB_DISCONNECTED && main_shutdown_state == MAIN_SHUTDOWN_WAITING) { + interface_power_mode = kAPP_PowerModeVlps; + main_shutdown_state = MAIN_SHUTDOWN_REQUESTED; + } switch (main_shutdown_state) { case MAIN_LED_FULL_BRIGHTNESS: @@ -387,8 +393,10 @@ void board_30ms_hook() // In VLLS0, set the LED either ON or LOW, depending on power_led_sleep_state_on // When the duty cycle is 0% or 100%, the FlexIO driver will configure the pin as GPIO - if (power_led_sleep_state_on == true) { + if (power_led_sleep_state_on == true && interface_power_mode == kAPP_PowerModeVlls0) { shutdown_led_dc = PWR_LED_ON_MAX_BRIGHTNESS; + } else if (power_led_sleep_state_on == true && interface_power_mode == kAPP_PowerModeVlps) { + shutdown_led_dc = PWR_LED_ON_BATT_BRIGHTNESS; } else { shutdown_led_dc = 0; @@ -418,6 +426,11 @@ void board_30ms_hook() } else if (shutdown_led_dc > 90) { shutdown_led_dc--; } + + // If we are no longer PC connected, go into idle mode + if (usb_state == USB_DISCONNECTED) { + main_shutdown_state = MAIN_SHUTDOWN_WAITING; + } break; case MAIN_LED_BLINK_ONCE: @@ -464,7 +477,7 @@ void board_handle_powerdown() i2c_deinitialize(); i2c_initialize(); - usbd_connect(1); + usb_state = USB_CONNECTING; gpio_set_hid_led(HID_LED_DEF); } @@ -614,10 +627,6 @@ static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { interface_power_mode = kAPP_PowerModeVlls0; i2cResponse.cmdId = gWriteResponse_c; i2cResponse.cmdData.writeRspCmd.propertyId = pI2cCommand->cmdData.writeReqCmd.propertyId; - } else if (pI2cCommand->cmdData.writeReqCmd.data[0] == kAPP_PowerModeVlps) { - interface_power_mode = kAPP_PowerModeVlps; - i2cResponse.cmdId = gWriteResponse_c; - i2cResponse.cmdData.writeRspCmd.propertyId = pI2cCommand->cmdData.writeReqCmd.propertyId; } else { i2cResponse.cmdId = gErrorResponse_c; i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWriteFail_c; From 153cd3efef2162fea5c7ccc7033cb645515d1a2f Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Thu, 10 Sep 2020 02:14:27 -0500 Subject: [PATCH 226/617] Send event for wake on edge and release the interrupt line on every new event so the nrf can see the new edges. --- source/board/microbitv2/microbitv2.c | 23 +++++++++++++++++++---- source/board/microbitv2/power.c | 14 +++++++++++--- 2 files changed, 30 insertions(+), 7 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 0a1c21306..fb401ea32 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -55,6 +55,7 @@ #define PWR_LED_INIT_FADE_BRIGHTNESS 80 // Initial fade LED Brightness #define PWR_LED_ON_BATT_BRIGHTNESS 40 // LED Brightness while being powered by battery #define PWR_LED_FADEOUT_MIN_BRIGHTNESS 30 // Minimum LED brightness when fading out +#define PWR_LED_SLEEP_STATE_DEFAULT true #define FLASH_CONFIG_ADDRESS (0x00020000) #define FLASH_STORAGE_ADDRESS (0x00020400) @@ -72,6 +73,7 @@ uint16_t board_id_hex_min = 0x9903; uint16_t board_id_hex = 0; volatile uint8_t wake_from_reset = 0; +volatile uint8_t wake_from_usb = 0; typedef enum { BOARD_VERSION_2_0 = 0, @@ -109,7 +111,7 @@ static main_shutdown_state_t main_shutdown_state = MAIN_SHUTDOWN_WAITING; static uint8_t shutdown_led_dc = PWR_LED_ON_MAX_BRIGHTNESS; static uint8_t power_led_max_duty_cycle = PWR_LED_ON_MAX_BRIGHTNESS; static uint8_t initial_fade_brightness = PWR_LED_INIT_FADE_BRIGHTNESS; -static bool power_led_sleep_state_on = true; +static bool power_led_sleep_state_on = PWR_LED_SLEEP_STATE_DEFAULT; static app_power_mode_t interface_power_mode = kAPP_PowerModeVlls0; static power_source_t power_source; static main_usb_connect_t prev_usb_state; @@ -280,7 +282,7 @@ void handle_reset_button() // Reset button released target_set_state(RESET_RUN); reset_pressed = 0; - power_led_sleep_state_on = true; + power_led_sleep_state_on = PWR_LED_SLEEP_STATE_DEFAULT; if (gpio_reset_count <= RESET_SHORT_PRESS) { main_shutdown_state = MAIN_LED_BLINK_ONCE; @@ -344,6 +346,10 @@ void board_30ms_hook() interface_power_mode = kAPP_PowerModeVlps; main_shutdown_state = MAIN_SHUTDOWN_REQUESTED; } + + if (wake_from_usb) { + main_shutdown_state = MAIN_SHUTDOWN_ALERT; + } switch (main_shutdown_state) { case MAIN_LED_FULL_BRIGHTNESS: @@ -371,12 +377,21 @@ void board_30ms_hook() break; case MAIN_SHUTDOWN_ALERT: { - // Assert the interrupt line and prepare I2C response + // Release COMBINED_SENSOR_INT in case it was previously asserted + PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); + + // Prepare I2C response i2cCommand_t i2cResponse = {0}; i2cResponse.cmdId = gReadResponse_c; i2cResponse.cmdData.readRspCmd.propertyId = (uint8_t) gUserEvent_c; i2cResponse.cmdData.readRspCmd.dataSize = 1; - i2cResponse.cmdData.readRspCmd.data[0] = gResetButtonLongPress_c; + + if (wake_from_usb) { + i2cResponse.cmdData.readRspCmd.data[0] = gWakeFromWakeOnEdge_c; + wake_from_usb = 0; + } else { + i2cResponse.cmdData.readRspCmd.data[0] = gResetButtonLongPress_c; + } i2c_fillBuffer((uint8_t*) &i2cResponse, 0, sizeof(i2cResponse)); diff --git a/source/board/microbitv2/power.c b/source/board/microbitv2/power.c index 0a15920e0..6612cf040 100644 --- a/source/board/microbitv2/power.c +++ b/source/board/microbitv2/power.c @@ -24,6 +24,7 @@ static void power_post_switch_hook(smc_power_state_t originPowerState, app_power static void power_enter_mode(app_power_mode_t targetPowerMode); extern volatile uint8_t wake_from_reset; +extern volatile uint8_t wake_from_usb; /******************************************************************************* * Code @@ -40,6 +41,7 @@ void LLWU_IRQHandler(void) if (LLWU_GetExternalWakeupPinFlag(LLWU, PIN_WAKE_ON_EDGE_LLWU_PIN)) { LLWU_ClearExternalWakeupPinFlag(LLWU, PIN_WAKE_ON_EDGE_LLWU_PIN); + wake_from_usb = 1; } } @@ -55,9 +57,15 @@ void PORTCD_IRQHandler(void) { PORT_ClearPinsInterruptFlags(PIN_WAKE_ON_EDGE_PORT, (1U << PIN_WAKE_ON_EDGE_BIT)); - /* Reset USB on cable detach (VBUS falling edge) */ - USBD_Reset(); - usbd_reset_core(); + if ((PIN_WAKE_ON_EDGE_PORT->PCR[PIN_WAKE_ON_EDGE_BIT] & PORT_PCR_IRQC_MASK) == PORT_PCR_IRQC(kPORT_InterruptRisingEdge)) { + /* Reset USB on cable detach (VBUS falling edge) */ + USBD_Reset(); + usbd_reset_core(); + } + else { + // Cable inserted + wake_from_usb = 1; + } } } From ad13da7677c8cbafd687650cb3fec0b2962fc292 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Thu, 10 Sep 2020 02:21:04 -0500 Subject: [PATCH 227/617] Add I2C nop command on the comms interface. Doing an i2c write witht this command doesn't assert the interrupt line. --- source/board/microbitv2/i2c_commands.h | 1 + source/board/microbitv2/microbitv2.c | 10 ++++++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/source/board/microbitv2/i2c_commands.h b/source/board/microbitv2/i2c_commands.h index 80d44c72d..d75099e1d 100644 --- a/source/board/microbitv2/i2c_commands.h +++ b/source/board/microbitv2/i2c_commands.h @@ -17,6 +17,7 @@ extern "C" { /*! i2c command Id type enumeration */ typedef enum cmdId_tag { + gNopCmd_c = 0x00, gReadRequest_c = 0x10, gReadResponse_c = 0x11, gWriteRequest_c = 0x12, diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index fb401ea32..184bad670 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -575,6 +575,7 @@ const board_info_t g_board_info = { static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { i2cCommand_t* pI2cCommand = (i2cCommand_t*) pData; i2cCommand_t i2cResponse = {0}; + bool assert_interrupt = true; switch (pI2cCommand->cmdId) { case gReadRequest_c: @@ -676,6 +677,9 @@ static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { break; case gErrorResponse_c: break; + case gNopCmd_c: + assert_interrupt = false; + break; default: i2cResponse.cmdId = gErrorResponse_c; i2cResponse.cmdData.errorRspCmd.errorCode = gErrorUnknownProperty_c; @@ -684,8 +688,10 @@ static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { i2c_fillBuffer((uint8_t*) &i2cResponse, 0, sizeof(i2cResponse)); - // Response ready, assert COMBINED_SENSOR_INT - PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_MuxAsGpio); + if (assert_interrupt) { + // Response ready, assert COMBINED_SENSOR_INT + PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_MuxAsGpio); + } } static void i2c_read_comms_callback(uint8_t* pData, uint8_t size) { From 4986535442f334fdf4e8b3a63f469d2af972f8d1 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Fri, 11 Sep 2020 01:33:59 -0500 Subject: [PATCH 228/617] Prevent Nop cmd from overwriting response from previous i2c write --- source/board/microbitv2/microbitv2.c | 3 +-- source/hic_hal/freescale/kl27z/i2c.c | 28 +++++++++++++++------------- 2 files changed, 16 insertions(+), 15 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 184bad670..5118788fd 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -686,9 +686,8 @@ static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { break; } - i2c_fillBuffer((uint8_t*) &i2cResponse, 0, sizeof(i2cResponse)); - if (assert_interrupt) { + i2c_fillBuffer((uint8_t*) &i2cResponse, 0, sizeof(i2cResponse)); // Response ready, assert COMBINED_SENSOR_INT PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_MuxAsGpio); } diff --git a/source/hic_hal/freescale/kl27z/i2c.c b/source/hic_hal/freescale/kl27z/i2c.c index c5ad54f30..50328ba63 100644 --- a/source/hic_hal/freescale/kl27z/i2c.c +++ b/source/hic_hal/freescale/kl27z/i2c.c @@ -17,7 +17,8 @@ #define RX_CMDS_LENGTH 5 #define I2C_CMD_SLEEP 0xABU -static uint8_t g_slave_buff[I2C_DATA_LENGTH]; +static uint8_t g_slave_TX_buff[I2C_DATA_LENGTH]; +static uint8_t g_slave_RX_buff[I2C_DATA_LENGTH]; static i2c_slave_handle_t g_s_handle; static volatile bool g_SlaveCompletionFlag = false; static volatile bool g_SlaveRxFlag = false; @@ -43,7 +44,7 @@ static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void /* Transmit request */ case kI2C_SlaveTransmitEvent: /* Update information for transmit process */ - xfer->data = g_slave_buff; + xfer->data = g_slave_TX_buff; xfer->dataSize = I2C_DATA_LENGTH; break; @@ -53,8 +54,8 @@ static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void // Hack: Default driver can't differentiate between RX or TX on // completion event, so we set a flag here. Can't process more // than I2C_DATA_LENGTH bytes on RX - memset(&g_slave_buff, 0, sizeof(g_slave_buff)); - xfer->data = g_slave_buff; + memset(&g_slave_RX_buff, 0, sizeof(g_slave_RX_buff)); + xfer->data = g_slave_RX_buff; xfer->dataSize = I2C_DATA_LENGTH; g_SlaveRxFlag = true; break; @@ -71,23 +72,23 @@ static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void g_SlaveRxFlag = false; if (pfWriteCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { - pfWriteCommsCallback(&g_slave_buff[0], xfer->transferredCount); + pfWriteCommsCallback(&g_slave_RX_buff[0], xfer->transferredCount); } if (pfWriteHIDCallback && address_match == I2C_SLAVE_HID) { - pfWriteHIDCallback(&g_slave_buff[0], xfer->transferredCount); + pfWriteHIDCallback(&g_slave_RX_buff[0], xfer->transferredCount); } if (pfWriteFlashCallback && address_match == I2C_SLAVE_FLASH) { - pfWriteFlashCallback(&g_slave_buff[0], xfer->transferredCount); + pfWriteFlashCallback(&g_slave_RX_buff[0], xfer->transferredCount); } } else { if (pfReadCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { - pfReadCommsCallback(&g_slave_buff[0], xfer->transferredCount); + pfReadCommsCallback(&g_slave_TX_buff[0], xfer->transferredCount); } if (pfReadHIDCallback && address_match == I2C_SLAVE_HID) { - pfReadHIDCallback(&g_slave_buff[0], xfer->transferredCount); + pfReadHIDCallback(&g_slave_TX_buff[0], xfer->transferredCount); } if (pfReadFlashCallback && address_match == I2C_SLAVE_FLASH) { - pfReadFlashCallback(&g_slave_buff[0], xfer->transferredCount); + pfReadFlashCallback(&g_slave_TX_buff[0], xfer->transferredCount); } } break; @@ -124,7 +125,8 @@ static void i2c_init_pins(void) { } static int32_t i2c_start_transfer(void) { - memset(&g_slave_buff, 0, sizeof(g_slave_buff)); + memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); + memset(&g_slave_RX_buff, 0, sizeof(g_slave_RX_buff)); memset(&g_s_handle, 0, sizeof(g_s_handle)); I2C_SlaveTransferCreateHandle(I2C_SLAVE_BASEADDR, &g_s_handle, @@ -206,7 +208,7 @@ status_t i2c_RegisterReadCallback(i2cReadCallback_t readCallback, uint8_t slaveA } void i2c_clearBuffer (void) { - memset(&g_slave_buff, 0, sizeof(g_slave_buff)); + memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); } void i2c_fillBuffer (uint8_t* data, uint32_t position, uint32_t size) { @@ -215,7 +217,7 @@ void i2c_fillBuffer (uint8_t* data, uint32_t position, uint32_t size) { } for (uint32_t i = 0; i < size; i++) { - g_slave_buff[position + i] = data[i]; + g_slave_TX_buff[position + i] = data[i]; } } From f74f449e538add0d8639a279350fe462b51b04ef Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Fri, 11 Sep 2020 01:42:32 -0500 Subject: [PATCH 229/617] Add I2C property to enable/disable automatic light sleep when idle --- source/board/microbitv2/i2c_commands.h | 3 ++- source/board/microbitv2/microbitv2.c | 19 ++++++++++++++++++- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/source/board/microbitv2/i2c_commands.h b/source/board/microbitv2/i2c_commands.h index d75099e1d..37e1fd804 100644 --- a/source/board/microbitv2/i2c_commands.h +++ b/source/board/microbitv2/i2c_commands.h @@ -35,7 +35,8 @@ typedef enum propertyId_tag { gUSBEnumerationState_c = 0x06, gPowerMode_c = 0x07, gPowerLedSleepState_c = 0x08, - gUserEvent_c = 0x09 + gUserEvent_c = 0x09, + gAutomaticSleep_c = 0x0A } propertyId_t; /*! user event type enumeration */ diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 5118788fd..20f7bb079 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -56,6 +56,7 @@ #define PWR_LED_ON_BATT_BRIGHTNESS 40 // LED Brightness while being powered by battery #define PWR_LED_FADEOUT_MIN_BRIGHTNESS 30 // Minimum LED brightness when fading out #define PWR_LED_SLEEP_STATE_DEFAULT true +#define AUTOMATIC_SLEEP_DEFAULT true #define FLASH_CONFIG_ADDRESS (0x00020000) #define FLASH_STORAGE_ADDRESS (0x00020400) @@ -112,6 +113,7 @@ static uint8_t shutdown_led_dc = PWR_LED_ON_MAX_BRIGHTNESS; static uint8_t power_led_max_duty_cycle = PWR_LED_ON_MAX_BRIGHTNESS; static uint8_t initial_fade_brightness = PWR_LED_INIT_FADE_BRIGHTNESS; static bool power_led_sleep_state_on = PWR_LED_SLEEP_STATE_DEFAULT; +static bool automatic_sleep_on = AUTOMATIC_SLEEP_DEFAULT; static app_power_mode_t interface_power_mode = kAPP_PowerModeVlls0; static power_source_t power_source; static main_usb_connect_t prev_usb_state; @@ -342,7 +344,7 @@ void board_30ms_hook() prev_usb_state = usb_state; // Enter light sleep if USB is not enumerated and main_shutdown_state is idle - if (usb_state == USB_DISCONNECTED && main_shutdown_state == MAIN_SHUTDOWN_WAITING) { + if (usb_state == USB_DISCONNECTED && main_shutdown_state == MAIN_SHUTDOWN_WAITING && automatic_sleep_on == true) { interface_power_mode = kAPP_PowerModeVlps; main_shutdown_state = MAIN_SHUTDOWN_REQUESTED; } @@ -667,6 +669,21 @@ static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWrongPropertySize_c; } break; + case gAutomaticSleep_c: + if (pI2cCommand->cmdData.writeReqCmd.dataSize == 1) { + if (pI2cCommand->cmdData.writeReqCmd.data[0] != 0) { + automatic_sleep_on = true; + } + else { + automatic_sleep_on = false; + } + i2cResponse.cmdId = gWriteResponse_c; + i2cResponse.cmdData.writeRspCmd.propertyId = pI2cCommand->cmdData.writeReqCmd.propertyId; + } else { + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWrongPropertySize_c; + } + break; default: i2cResponse.cmdId = gErrorResponse_c; i2cResponse.cmdData.errorRspCmd.errorCode = gErrorUnknownProperty_c; From 042dbb1f2dc59a96e5512a7bce7b51f717782bd3 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Fri, 11 Sep 2020 01:50:18 -0500 Subject: [PATCH 230/617] Temporal fix for broken details.txt --- source/daplink/drag-n-drop/vfs_user.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/source/daplink/drag-n-drop/vfs_user.c b/source/daplink/drag-n-drop/vfs_user.c index c6d19848e..5119c1646 100644 --- a/source/daplink/drag-n-drop/vfs_user.c +++ b/source/daplink/drag-n-drop/vfs_user.c @@ -118,7 +118,7 @@ static const magic_file_info_t s_magic_file_info[] = { { "PAGE_OFFACT", kChipEraseActionFile }, }; -static uint8_t file_buffer[VFS_SECTOR_SIZE]; +static uint8_t file_buffer[VFS_SECTOR_SIZE+100]; static char assert_buf[64 + 1]; static uint16_t assert_line; static assert_source_t assert_source; @@ -348,12 +348,22 @@ static uint32_t read_file_mbed_htm(uint32_t sector_offset, uint8_t *data, uint32 // File callback to be used with vfs_add_file to return file contents static uint32_t read_file_details_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors) { + uint32_t size = 0; - if (sector_offset != 0) { + if (sector_offset > 1) { return 0; } + + size = update_details_txt_file(file_buffer, VFS_SECTOR_SIZE+100); + + if (size - VFS_SECTOR_SIZE * sector_offset > VFS_SECTOR_SIZE) { + memcpy(data, file_buffer + sector_offset * VFS_SECTOR_SIZE, VFS_SECTOR_SIZE); + } + else { + memcpy(data, file_buffer + sector_offset * VFS_SECTOR_SIZE, size - VFS_SECTOR_SIZE * sector_offset); + } - return update_details_txt_file(data, VFS_SECTOR_SIZE); + return size; } // Text representation of each error type, starting from the rightmost bit From 9522cd9d3f02545625c9da7725955a81fbbe7da7 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Fri, 11 Sep 2020 02:11:11 -0500 Subject: [PATCH 231/617] Prevent entering light sleep if I2C transaction is ongoing --- source/board/microbitv2/microbitv2.c | 5 ++++- source/hic_hal/freescale/kl27z/i2c.c | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 20f7bb079..7b86ec96b 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -34,6 +34,7 @@ #include "adc.h" #include "fsl_port.h" #include "fsl_gpio.h" +#include "fsl_i2c.h" #include "led_error_app.h" #include "flash_manager.h" #include "virtual_fs.h" @@ -84,6 +85,7 @@ typedef enum { extern target_cfg_t target_device_nrf52_64; extern main_usb_connect_t usb_state; extern bool go_to_sleep; +extern i2c_slave_handle_t g_s_handle; typedef enum main_shutdown_state { MAIN_SHUTDOWN_WAITING = 0, @@ -344,7 +346,8 @@ void board_30ms_hook() prev_usb_state = usb_state; // Enter light sleep if USB is not enumerated and main_shutdown_state is idle - if (usb_state == USB_DISCONNECTED && main_shutdown_state == MAIN_SHUTDOWN_WAITING && automatic_sleep_on == true) { + if (usb_state == USB_DISCONNECTED && main_shutdown_state == MAIN_SHUTDOWN_WAITING + && automatic_sleep_on == true && g_s_handle.isBusy == false) { interface_power_mode = kAPP_PowerModeVlps; main_shutdown_state = MAIN_SHUTDOWN_REQUESTED; } diff --git a/source/hic_hal/freescale/kl27z/i2c.c b/source/hic_hal/freescale/kl27z/i2c.c index 50328ba63..02e27018e 100644 --- a/source/hic_hal/freescale/kl27z/i2c.c +++ b/source/hic_hal/freescale/kl27z/i2c.c @@ -19,7 +19,7 @@ static uint8_t g_slave_TX_buff[I2C_DATA_LENGTH]; static uint8_t g_slave_RX_buff[I2C_DATA_LENGTH]; -static i2c_slave_handle_t g_s_handle; +i2c_slave_handle_t g_s_handle; static volatile bool g_SlaveCompletionFlag = false; static volatile bool g_SlaveRxFlag = false; uint8_t address_match = 0; @@ -135,6 +135,9 @@ static int32_t i2c_start_transfer(void) { /* Set up slave transfer. */ I2C_SlaveTransferNonBlocking(I2C_SLAVE_BASEADDR, &g_s_handle, kI2C_SlaveCompletionEvent | kI2C_SlaveAddressMatchEvent); + + // i2c handle will be busy until an address match + g_s_handle.isBusy = false; return 1; } From 42f1f4987d0495d565114a1983fdb7903db3337b Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Fri, 11 Sep 2020 02:14:19 -0500 Subject: [PATCH 232/617] Temporal modification of USB max power to 300mA --- source/hic_hal/freescale/kl27z/usb_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/hic_hal/freescale/kl27z/usb_config.c b/source/hic_hal/freescale/kl27z/usb_config.c index 123957820..63fac8b02 100644 --- a/source/hic_hal/freescale/kl27z/usb_config.c +++ b/source/hic_hal/freescale/kl27z/usb_config.c @@ -68,7 +68,7 @@ // when the device is fully operational (bMaxPower) // #define USBD_CFGDESC_BMATTRIBUTES 0x80 -#define USBD_CFGDESC_BMAXPOWER 0xFA +#define USBD_CFGDESC_BMAXPOWER 0x96 // Temporal modification to 300mA for microbit // String Settings // These settings affect String Descriptor From da007679031b847594473c4f88f18f5148fcffbf Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Fri, 11 Sep 2020 02:18:34 -0500 Subject: [PATCH 233/617] Reset the Power LED sleep state when waking up the NRF with COMBINED_SENSOR_INT caused by WAKE_ON_EDGE --- source/board/microbitv2/microbitv2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 7b86ec96b..d3a5be353 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -394,6 +394,7 @@ void board_30ms_hook() if (wake_from_usb) { i2cResponse.cmdData.readRspCmd.data[0] = gWakeFromWakeOnEdge_c; wake_from_usb = 0; + power_led_sleep_state_on = PWR_LED_SLEEP_STATE_DEFAULT; } else { i2cResponse.cmdData.readRspCmd.data[0] = gResetButtonLongPress_c; } From f6ec70d00657e113a0ec46f42a35d691f371114a Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Fri, 11 Sep 2020 11:01:11 -0500 Subject: [PATCH 234/617] Do not clear I2C buffers after waking up from VLPS --- source/hic_hal/freescale/kl27z/i2c.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/source/hic_hal/freescale/kl27z/i2c.c b/source/hic_hal/freescale/kl27z/i2c.c index 02e27018e..018d75346 100644 --- a/source/hic_hal/freescale/kl27z/i2c.c +++ b/source/hic_hal/freescale/kl27z/i2c.c @@ -125,8 +125,6 @@ static void i2c_init_pins(void) { } static int32_t i2c_start_transfer(void) { - memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); - memset(&g_slave_RX_buff, 0, sizeof(g_slave_RX_buff)); memset(&g_s_handle, 0, sizeof(g_s_handle)); I2C_SlaveTransferCreateHandle(I2C_SLAVE_BASEADDR, &g_s_handle, From dc06579660eea13d310902024e808a18150d4381 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Fri, 11 Sep 2020 14:11:57 -0500 Subject: [PATCH 235/617] Remove references to i2c flash status cmd --- source/board/microbitv2/i2c_commands.h | 1 - source/board/microbitv2/microbitv2.c | 2 -- 2 files changed, 3 deletions(-) diff --git a/source/board/microbitv2/i2c_commands.h b/source/board/microbitv2/i2c_commands.h index 37e1fd804..9439d0dff 100644 --- a/source/board/microbitv2/i2c_commands.h +++ b/source/board/microbitv2/i2c_commands.h @@ -114,7 +114,6 @@ typedef enum flashCmdId_tag { gFlashStorageSize_c = 0x06, gFlashSectorSize_c = 0x07, gFlashRemountMSD_c = 0x08, - gFlashStatus_c = 0x09, gFlashDataRead_c = 0x0A, gFlashDataWrite_c = 0x0B, gFlashDataErase_c = 0x0C, diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index d3a5be353..96d3230b3 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -879,8 +879,6 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { pI2cCommand->cmdData.data[1] = 0x00; i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 3); break; - case gFlashStatus_c: - break; case gFlashRemountMSD_c: do_remount = true; break; From ef11504f839d92a25719fe2e310ccfdc100da749 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Mon, 14 Sep 2020 15:21:28 -0500 Subject: [PATCH 236/617] Prevent entering light-sleep mode when USB Host does re-enumeration (e.g attaching usb device to VM) --- source/board/microbitv2/microbitv2.c | 10 +++++++--- source/board/microbitv2/power.c | 2 ++ 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 96d3230b3..0981a666f 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -76,6 +76,7 @@ uint16_t board_id_hex = 0; volatile uint8_t wake_from_reset = 0; volatile uint8_t wake_from_usb = 0; +volatile bool usb_pc_connected = false; typedef enum { BOARD_VERSION_2_0 = 0, @@ -330,6 +331,9 @@ void board_30ms_hook() static uint8_t blink_in_progress = 0; if (usb_state == USB_CONNECTED) { + /* Set usb_pc_connected to true to prevent entering sleep mode when host does re-enumeration. + * Will be set to false when the USB cable is detached. */ + usb_pc_connected = true; // configure pin as GPIO PIN_HID_LED_PORT->PCR[PIN_HID_LED_BIT] = PORT_PCR_MUX(1); power_led_max_duty_cycle = PWR_LED_ON_MAX_BRIGHTNESS; @@ -346,7 +350,7 @@ void board_30ms_hook() prev_usb_state = usb_state; // Enter light sleep if USB is not enumerated and main_shutdown_state is idle - if (usb_state == USB_DISCONNECTED && main_shutdown_state == MAIN_SHUTDOWN_WAITING + if (usb_state == USB_DISCONNECTED && !usb_pc_connected && main_shutdown_state == MAIN_SHUTDOWN_WAITING && automatic_sleep_on == true && g_s_handle.isBusy == false) { interface_power_mode = kAPP_PowerModeVlps; main_shutdown_state = MAIN_SHUTDOWN_REQUESTED; @@ -409,7 +413,7 @@ void board_30ms_hook() } break; case MAIN_SHUTDOWN_REQUESTED: - if (power_source == PWR_BATT_ONLY || usb_state == USB_DISCONNECTED) { + if (power_source == PWR_BATT_ONLY || (usb_state == USB_DISCONNECTED && !usb_pc_connected)) { main_powerdown_event(); // In VLLS0, set the LED either ON or LOW, depending on power_led_sleep_state_on @@ -449,7 +453,7 @@ void board_30ms_hook() } // If we are no longer PC connected, go into idle mode - if (usb_state == USB_DISCONNECTED) { + if (usb_state == USB_DISCONNECTED && !usb_pc_connected) { main_shutdown_state = MAIN_SHUTDOWN_WAITING; } break; diff --git a/source/board/microbitv2/power.c b/source/board/microbitv2/power.c index 6612cf040..27861112a 100644 --- a/source/board/microbitv2/power.c +++ b/source/board/microbitv2/power.c @@ -25,6 +25,7 @@ static void power_enter_mode(app_power_mode_t targetPowerMode); extern volatile uint8_t wake_from_reset; extern volatile uint8_t wake_from_usb; +extern volatile bool usb_pc_connected; /******************************************************************************* * Code @@ -61,6 +62,7 @@ void PORTCD_IRQHandler(void) /* Reset USB on cable detach (VBUS falling edge) */ USBD_Reset(); usbd_reset_core(); + usb_pc_connected = false; } else { // Cable inserted From f26ed3f7240ac9cebf231ebfac288b1c97a7c8bd Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Mon, 14 Sep 2020 21:02:46 -0500 Subject: [PATCH 237/617] Set usb_state to disconnected immediately after cable deatch, instead of waiting to the main loop poll to update the status. --- source/board/microbitv2/power.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/source/board/microbitv2/power.c b/source/board/microbitv2/power.c index 27861112a..1f1cb26c5 100644 --- a/source/board/microbitv2/power.c +++ b/source/board/microbitv2/power.c @@ -9,6 +9,7 @@ #include "fsl_port.h" #include "fsl_clock.h" +#include "main_interface.h" #include "power.h" #include "IO_Config.h" #include "uart.h" @@ -26,6 +27,7 @@ static void power_enter_mode(app_power_mode_t targetPowerMode); extern volatile uint8_t wake_from_reset; extern volatile uint8_t wake_from_usb; extern volatile bool usb_pc_connected; +extern main_usb_connect_t usb_state; /******************************************************************************* * Code @@ -63,6 +65,7 @@ void PORTCD_IRQHandler(void) USBD_Reset(); usbd_reset_core(); usb_pc_connected = false; + usb_state = USB_DISCONNECTED; } else { // Cable inserted From 3fc19b5961266b9751551ef6ab49c5c68d157e96 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Mon, 14 Sep 2020 21:04:41 -0500 Subject: [PATCH 238/617] Lower battery voltage threshold for determining power source to avoid getting PWR_SOURCE_NONE. --- source/board/microbitv2/pwr_mon.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/source/board/microbitv2/pwr_mon.c b/source/board/microbitv2/pwr_mon.c index 3d05c7c6c..43803f89e 100644 --- a/source/board/microbitv2/pwr_mon.c +++ b/source/board/microbitv2/pwr_mon.c @@ -16,6 +16,7 @@ #define ADC_VREFH_MUX (kADC16_ChannelMuxA) #define ADC_MV_TO_ADC(x) ((x) * 0xFFF / 3300) // Convert mV to ADC value (12bit and 3.3V reference) +#define BATT_MIN_VOLTAGE 1500 void pwr_mon_bandgap_init(void); uint32_t pwr_mon_read_vbg(uint32_t channelGroup); @@ -54,13 +55,13 @@ power_source_t pwr_mon_get_power_source(void) { bat_voltage_mv = pwr_mon_adc_to_mv(bat_adc); - if (usb_on == true && bat_voltage_mv < (2500)) { + if (usb_on == true && bat_voltage_mv < (BATT_MIN_VOLTAGE)) { power_source = PWR_USB_ONLY; - } else if (usb_on == true && bat_voltage_mv >= (2500)) { + } else if (usb_on == true && bat_voltage_mv >= (BATT_MIN_VOLTAGE)) { power_source = PWR_USB_AND_BATT; - } else if (usb_on == false && bat_voltage_mv >= (2500)) { + } else if (usb_on == false && bat_voltage_mv >= (BATT_MIN_VOLTAGE)) { power_source = PWR_BATT_ONLY; - } else if (usb_on == false && bat_voltage_mv < (2500)) { + } else if (usb_on == false && bat_voltage_mv < (BATT_MIN_VOLTAGE)) { power_source = PWR_SOURCE_NONE; } From 39a96740b95a996e99b9d26b68f341d3c06ca238 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Tue, 29 Sep 2020 20:34:09 -0500 Subject: [PATCH 239/617] I2C Flash interface updates -Add support for reading flash config data -Change filesize to bytes instead of KB -Fix address ranges in erase storage cmd -Add more validations to different commands --- source/board/microbitv2/i2c_commands.h | 2 +- source/board/microbitv2/microbitv2.c | 207 +++++++++++++++++-------- 2 files changed, 143 insertions(+), 66 deletions(-) diff --git a/source/board/microbitv2/i2c_commands.h b/source/board/microbitv2/i2c_commands.h index 9439d0dff..2272d7e23 100644 --- a/source/board/microbitv2/i2c_commands.h +++ b/source/board/microbitv2/i2c_commands.h @@ -100,7 +100,7 @@ typedef __PACKED_STRUCT i2cCommand_tag { typedef __PACKED_STRUCT flashConfig_tag { uint32_t key; // Magic key to indicate a valid record vfs_filename_t fileName; - uint32_t fileSizeKB; + uint32_t fileSize; bool fileVisible; } flashConfig_t; diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 0981a666f..f9d56c879 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -60,10 +60,13 @@ #define AUTOMATIC_SLEEP_DEFAULT true #define FLASH_CONFIG_ADDRESS (0x00020000) +#define FLASH_CONFIG_SIZE (0x00000400) +#define FLASH_DAL_CFG_SIZE (0x00000400) +#define FLASH_INTERFACE_SIZE (128*1024) #define FLASH_STORAGE_ADDRESS (0x00020400) -#define FLASH_CFG_FILENAME "DATA BIN" -#define FLASH_CFG_FILESIZEKB 126 -#define FLASH_CFG_FILEVISIBLE false +#define FLASH_CFG_FILENAME "DATA BIN" +#define FLASH_CFG_FILESIZE (126*1024) +#define FLASH_CFG_FILEVISIBLE false // 'kvld' in hex - key valid #define CFG_KEY 0x6b766c64 @@ -127,7 +130,7 @@ static bool do_remount = false; flashConfig_t gflashConfig = { .key = CFG_KEY, .fileName = FLASH_CFG_FILENAME, - .fileSizeKB = FLASH_CFG_FILESIZEKB, + .fileSize = FLASH_CFG_FILESIZE, .fileVisible = FLASH_CFG_FILEVISIBLE, }; @@ -537,7 +540,7 @@ void vfs_user_build_filesystem_hook() { } } - file_size = gflashConfig.fileSizeKB * 1024; + file_size = gflashConfig.fileSize; if (gflashConfig.fileVisible) { vfs_create_file(gflashConfig.fileName, read_file_data_txt, 0, file_size); @@ -737,7 +740,7 @@ static void i2c_read_comms_callback(uint8_t* pData, uint8_t size) { PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); } -static bool file_extension_valid(const vfs_filename_t filename) +static bool file_extension_allowed(const vfs_filename_t filename) { const char *valid_extensions[] = { "BIN", @@ -762,74 +765,161 @@ static bool file_extension_valid(const vfs_filename_t filename) static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { i2cFlashCmd_t* pI2cCommand = (i2cFlashCmd_t*) pData; - uint32_t status; + uint32_t status = 0; cortex_int_state_t state; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, sizeof(i2cFlashCmd_t) - 1024); - - uint32_t address = pI2cCommand->cmdData.write.addr2 << 16 | + uint32_t storage_address = pI2cCommand->cmdData.write.addr2 << 16 | pI2cCommand->cmdData.write.addr1 << 8 | pI2cCommand->cmdData.write.addr0 << 0; - address = address + FLASH_STORAGE_ADDRESS; + uint32_t address = storage_address + FLASH_STORAGE_ADDRESS; uint32_t length = __REV(pI2cCommand->cmdData.write.length); uint32_t data = (uint32_t) pI2cCommand->cmdData.write.data; + i2c_clearBuffer(); + switch (pI2cCommand->cmdId) { case gFlashDataWrite_c: - state = cortex_int_get_and_disable(); - status = ProgramPage(address, length, (uint32_t *) data); - cortex_int_restore(state); - - if (0 != status) { - i2c_clearBuffer(); + /* Validate length field matches with I2C Write data */ + if (size == length + 8) { + /* Address range and alignment validation done inside ProgramPage() */ + state = cortex_int_get_and_disable(); + status = ProgramPage(address, length, (uint32_t *) data); + cortex_int_restore(state); + + if (0 != status) { + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } + else { + /* Fill TX Buffer with received command args */ + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, sizeof(i2cFlashCmd_t) - 1024); + /* Fill TX Buffer with Flash Data Written */ + i2c_fillBuffer((uint8_t*) address, sizeof(i2cFlashCmd_t) - 1024, length); + } + } else { pI2cCommand->cmdId = gFlashError_c; i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); } - else { - i2c_fillBuffer((uint8_t*) address, sizeof(i2cFlashCmd_t) - 1024, length); - } break; case gFlashDataRead_c: { - i2c_fillBuffer((uint8_t*) address, sizeof(i2cFlashCmd_t) - 1024, length); + /* Do address range validation */ + if (address + length > (FLASH_CONFIG_ADDRESS + FLASH_INTERFACE_SIZE)) { + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } else { + /* Fill TX Buffer with received command args */ + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, sizeof(i2cFlashCmd_t) - 1024); + /* Fill TX Buffer with Flash Data Read */ + i2c_fillBuffer((uint8_t*) address, sizeof(i2cFlashCmd_t) - 1024, length); + } } break; case gFlashDataErase_c: { - state = cortex_int_get_and_disable(); - status = EraseSector(address); - cortex_int_restore(state); + uint32_t address = pI2cCommand->cmdData.erase.sAddr2 << 16 | + pI2cCommand->cmdData.erase.sAddr1 << 8 | + pI2cCommand->cmdData.erase.sAddr0 << 0; + uint32_t start_addr = address + FLASH_STORAGE_ADDRESS; - if (status != 0) { - i2c_clearBuffer(); + address = pI2cCommand->cmdData.erase.eAddr2 << 16 | + pI2cCommand->cmdData.erase.eAddr1 << 8 | + pI2cCommand->cmdData.erase.eAddr0 << 0; + uint32_t end_addr = address + FLASH_STORAGE_ADDRESS; + + /* Do address range validation */ + if (start_addr % DAPLINK_SECTOR_SIZE == 0 && + end_addr % DAPLINK_SECTOR_SIZE == 0 && + start_addr <= end_addr && + start_addr < (FLASH_CONFIG_ADDRESS + FLASH_INTERFACE_SIZE) && + end_addr < (FLASH_CONFIG_ADDRESS + FLASH_INTERFACE_SIZE)) { + for (uint32_t addr = start_addr; addr <= end_addr && status == 0; addr += DAPLINK_SECTOR_SIZE) { + state = cortex_int_get_and_disable(); + status = EraseSector(addr); + cortex_int_restore(state); + } + + if (status != 0) { + pI2cCommand->cmdId = gFlashError_c; + } + } else { pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); } + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } break; - case gFlashCfgFileName_c: - // Validate 8.3 filename - if (true != filename_valid((char *) pI2cCommand->cmdData.data) || size != 12) { - // Send error if invalid filename - i2c_clearBuffer(); - pI2cCommand->cmdId = gFlashError_c; + case gFlashCfgFileName_c: + if (size == 1) { + /* If size is 1 (only cmd id), this means it's a read */ i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - } - else { - // Validate allowed extensions (.bin, .txt, .csv, .htm, .wav) - if ( true == file_extension_valid((char *) pI2cCommand->cmdData.data)) { - memcpy(gflashConfig.fileName, pI2cCommand->cmdData.data, 11); + i2c_fillBuffer((uint8_t*) &gflashConfig.fileName, 1, sizeof(gflashConfig.fileName)); + } else if (size == 12) { + /* If size is 12 (cmd id + 11B data), this means it's a write */ + /* Validate 8.3 filename */ + if (filename_valid((char *) pI2cCommand->cmdData.data)) { + // Check allowed extensions (.bin, .txt, .csv, .htm, .wav) + if (file_extension_allowed((char *) pI2cCommand->cmdData.data)) { + memcpy(gflashConfig.fileName, pI2cCommand->cmdData.data, 11); + } + // If disallowed extension is requested, .bin will be used + else { + memcpy(gflashConfig.fileName, pI2cCommand->cmdData.data, 8); + memcpy(&gflashConfig.fileName[8], "BIN", 3); + } + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBuffer((uint8_t*) &gflashConfig.fileName, 1, sizeof(gflashConfig.fileName)); } - // If invalid extension is requested, .bin will be used else { - memcpy(gflashConfig.fileName, pI2cCommand->cmdData.data, 8); - memcpy(&gflashConfig.fileName[8], "BIN", 3); + // Send error if invalid filename + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); } - } + } else { + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } break; - case gFlashCfgFileSize_c: - gflashConfig.fileSizeKB = pI2cCommand->cmdData.data[0]; + case gFlashCfgFileSize_c: + if (size == 1) { + /* If size is 1 (only cmd id), this means it's a read */ + uint32_t tempFileSize = __REV(gflashConfig.fileSize); + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBuffer((uint8_t*) &tempFileSize, 1, sizeof(gflashConfig.fileSize)); + } else if (size == 5) { + /* If size is 5 (cmd id + 4B data), this means it's a write */ + uint32_t tempFileSize = pI2cCommand->cmdData.data[0] << 24 | + pI2cCommand->cmdData.data[1] << 16 | + pI2cCommand->cmdData.data[2] << 8 | + pI2cCommand->cmdData.data[3] << 0; + + /* Validate file size */ + if (tempFileSize <= (FLASH_INTERFACE_SIZE - FLASH_CONFIG_SIZE - FLASH_DAL_CFG_SIZE)) { + gflashConfig.fileSize = tempFileSize; + tempFileSize = __REV(gflashConfig.fileSize); + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBuffer((uint8_t*) &tempFileSize, 1, sizeof(gflashConfig.fileSize)); + } else { + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } + } else { + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } break; case gFlashCfgFileVisible_c: - gflashConfig.fileVisible = pI2cCommand->cmdData.data[0]; + if (size == 1) { + /* If size is 1 (only cmd id), this means it's a read */ + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBuffer((uint8_t*) &gflashConfig.fileVisible, 1, sizeof(gflashConfig.fileVisible)); + } else if (size == 2) { + /* If size is 2 (cmd id + 1B data), this means it's a write */ + gflashConfig.fileVisible = pI2cCommand->cmdData.data[0]; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBuffer((uint8_t*) &gflashConfig.fileVisible, 1, sizeof(gflashConfig.fileVisible)); + } else { + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } break; case gFlashCfgWrite_c: // Check first is config is already present in flash @@ -840,9 +930,7 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { cortex_int_restore(state); if (status != 0) { - i2c_clearBuffer(); pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); } else { state = cortex_int_get_and_disable(); @@ -850,6 +938,7 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { cortex_int_restore(state); } } + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); break; case gFlashCfgErase_c: // Erase flash sector containing flash config @@ -858,36 +947,31 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { cortex_int_restore(state); if (status != 0) { - i2c_clearBuffer(); pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); } else { // Return flash config (RAM) to default values gflashConfig.key = CFG_KEY; memcpy(gflashConfig.fileName, FLASH_CFG_FILENAME, 11); - gflashConfig.fileSizeKB = FLASH_CFG_FILESIZEKB; + gflashConfig.fileSize = FLASH_CFG_FILESIZE; gflashConfig.fileVisible = FLASH_CFG_FILEVISIBLE; } + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); break; case gFlashStorageSize_c: - i2c_clearBuffer(); - pI2cCommand->cmdId = gFlashStorageSize_c; - pI2cCommand->cmdData.data[0] = 128; + pI2cCommand->cmdData.data[0] = (FLASH_INTERFACE_SIZE - FLASH_CONFIG_SIZE - FLASH_DAL_CFG_SIZE)/1024; i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 2); break; case gFlashSectorSize_c: - i2c_clearBuffer(); - pI2cCommand->cmdId = gFlashSectorSize_c; - pI2cCommand->cmdData.data[0] = 0x04; - pI2cCommand->cmdData.data[1] = 0x00; + pI2cCommand->cmdData.data[0] = (DAPLINK_SECTOR_SIZE >> 8) & 0xFF; + pI2cCommand->cmdData.data[1] = DAPLINK_SECTOR_SIZE & 0xFF; i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 3); break; case gFlashRemountMSD_c: do_remount = true; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); break; default: - i2c_clearBuffer(); pI2cCommand->cmdId = gFlashError_c; i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); break; @@ -898,13 +982,6 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { } static void i2c_read_flash_callback(uint8_t* pData, uint8_t size) { - i2cCommand_t* pI2cCommand = (i2cCommand_t*) pData; - - switch (pI2cCommand->cmdId) { - case gWriteResponse_c: - break; - } - i2c_clearBuffer(); // Release COMBINED_SENSOR_INT From ddef0bdeb65a31d184002d7869e89e284003d7dd Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Thu, 1 Oct 2020 10:46:50 -0500 Subject: [PATCH 240/617] Fix lost serial bytes during flash operations -Keep interrupts enabled during flash operations -Shortened I2C ISR --- source/board/microbitv2/microbitv2.c | 49 ++++++++++++------- source/daplink/interface/main_interface.c | 18 +++++++ source/daplink/interface/main_interface.h | 1 + source/hic_hal/freescale/kl27z/i2c.c | 57 +++++++++++------------ 4 files changed, 76 insertions(+), 49 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index f9d56c879..7609a7be8 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -40,7 +40,7 @@ #include "virtual_fs.h" #include "vfs_manager.h" #include "cortex_m.h" -#include "FlashPrg.h" +#include "fsl_flash.h" #ifdef DRAG_N_DROP_SUPPORT #include "flash_intf.h" @@ -90,6 +90,7 @@ extern target_cfg_t target_device_nrf52_64; extern main_usb_connect_t usb_state; extern bool go_to_sleep; extern i2c_slave_handle_t g_s_handle; +extern flash_config_t g_flash; typedef enum main_shutdown_state { MAIN_SHUTDOWN_WAITING = 0, @@ -762,11 +763,33 @@ static bool file_extension_allowed(const vfs_filename_t filename) return false; } +static uint32_t erase_storage_sector(uint32_t adr) +{ + int status = FLASH_Erase(&g_flash, adr, g_flash.PFlashSectorSize, kFLASH_apiEraseKey); + if (status == kStatus_Success) + { + status = FLASH_VerifyErase(&g_flash, adr, g_flash.PFlashSectorSize, kFLASH_marginValueNormal); + } + return status; +} + +static uint32_t program_storage_page(uint32_t adr, uint32_t sz, uint32_t *buf) +{ + int status = FLASH_Program(&g_flash, adr, buf, sz); + if (status == kStatus_Success) + { + // Must use kFlashMargin_User, or kFlashMargin_Factory for verify program + status = FLASH_VerifyProgram(&g_flash, adr, sz, + buf, kFLASH_marginValueUser, + NULL, NULL); + } + return status; +} + static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { i2cFlashCmd_t* pI2cCommand = (i2cFlashCmd_t*) pData; uint32_t status = 0; - cortex_int_state_t state; uint32_t storage_address = pI2cCommand->cmdData.write.addr2 << 16 | pI2cCommand->cmdData.write.addr1 << 8 | @@ -781,10 +804,8 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { case gFlashDataWrite_c: /* Validate length field matches with I2C Write data */ if (size == length + 8) { - /* Address range and alignment validation done inside ProgramPage() */ - state = cortex_int_get_and_disable(); - status = ProgramPage(address, length, (uint32_t *) data); - cortex_int_restore(state); + /* Address range and alignment validation done inside program_storage_page() */ + status = program_storage_page(address, length, (uint32_t *) data); if (0 != status) { pI2cCommand->cmdId = gFlashError_c; @@ -832,9 +853,7 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { start_addr < (FLASH_CONFIG_ADDRESS + FLASH_INTERFACE_SIZE) && end_addr < (FLASH_CONFIG_ADDRESS + FLASH_INTERFACE_SIZE)) { for (uint32_t addr = start_addr; addr <= end_addr && status == 0; addr += DAPLINK_SECTOR_SIZE) { - state = cortex_int_get_and_disable(); - status = EraseSector(addr); - cortex_int_restore(state); + status = erase_storage_sector(addr); } if (status != 0) { @@ -925,26 +944,20 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { // Check first is config is already present in flash // If differences are found, erase and write new config if (0 != memcmp(&gflashConfig, (void *)FLASH_CONFIG_ADDRESS, sizeof(flashConfig_t))) { - state = cortex_int_get_and_disable(); - status = EraseSector(FLASH_CONFIG_ADDRESS); - cortex_int_restore(state); + status = erase_storage_sector(FLASH_CONFIG_ADDRESS); if (status != 0) { pI2cCommand->cmdId = gFlashError_c; } else { - state = cortex_int_get_and_disable(); - status = ProgramPage(FLASH_CONFIG_ADDRESS, sizeof(flashConfig_t), (uint32_t *) &gflashConfig); - cortex_int_restore(state); + status = program_storage_page(FLASH_CONFIG_ADDRESS, sizeof(flashConfig_t), (uint32_t *) &gflashConfig); } } i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); break; case gFlashCfgErase_c: // Erase flash sector containing flash config - state = cortex_int_get_and_disable(); - status = EraseSector(FLASH_CONFIG_ADDRESS); - cortex_int_restore(state); + status = erase_storage_sector(FLASH_CONFIG_ADDRESS); if (status != 0) { pI2cCommand->cmdId = gFlashError_c; diff --git a/source/daplink/interface/main_interface.c b/source/daplink/interface/main_interface.c index a0460bac0..645ea3eaa 100644 --- a/source/daplink/interface/main_interface.c +++ b/source/daplink/interface/main_interface.c @@ -73,6 +73,7 @@ void __libc_init_array (void) {} // Reset events #define FLAGS_MAIN_RESET (1 << 2) // Other Events +#define FLAGS_BOARD_EVENT (1 << 3) #define FLAGS_MAIN_POWERDOWN (1 << 4) #define FLAGS_MAIN_DISABLEDEBUG (1 << 5) #define FLAGS_MAIN_PROC_USB (1 << 9) @@ -172,6 +173,11 @@ __WEAK void board_handle_powerdown() // TODO: put the interface chip in sleep mode } +__WEAK void board_custom_event() +{ + +} + // Timer task, set flags every 30mS and 90mS void timer_task_30mS(void * arg) { @@ -221,6 +227,13 @@ void main_powerdown_event(void) return; } +// Set custom board event +void main_board_event(void) +{ + osThreadFlagsSet(main_task_id, FLAGS_BOARD_EVENT); + return; +} + // Disable debug on target void main_disable_debug_event(void) { @@ -331,6 +344,7 @@ void main_task(void * arg) | FLAGS_MAIN_DISABLEDEBUG // Disable target debug | FLAGS_MAIN_PROC_USB // process usb events | FLAGS_MAIN_CDC_EVENT // cdc event + | FLAGS_BOARD_EVENT // custom board event , osFlagsWaitAny , osWaitForever); @@ -370,6 +384,10 @@ void main_task(void * arg) if (flags & FLAGS_MAIN_CDC_EVENT) { cdc_process_event(); } + + if (flags & FLAGS_BOARD_EVENT) { + board_custom_event(); + } if (flags & FLAGS_MAIN_90MS) { // Update USB busy status diff --git a/source/daplink/interface/main_interface.h b/source/daplink/interface/main_interface.h index 06d8cdb3d..e27c2dc46 100644 --- a/source/daplink/interface/main_interface.h +++ b/source/daplink/interface/main_interface.h @@ -48,6 +48,7 @@ extern "C" { void main_reset_target(uint8_t send_unique_id); void main_usb_set_test_mode(bool enabled); void main_powerdown_event(void); +void main_board_event(void); void main_disable_debug_event(void); void main_cdc_send_event(void); void main_msc_disconnect_event(void); diff --git a/source/hic_hal/freescale/kl27z/i2c.c b/source/hic_hal/freescale/kl27z/i2c.c index 018d75346..078911f71 100644 --- a/source/hic_hal/freescale/kl27z/i2c.c +++ b/source/hic_hal/freescale/kl27z/i2c.c @@ -3,6 +3,7 @@ #include "fsl_clock.h" #include "fsl_port.h" #include "settings.h" // for config_get_overflow_detect +#include "main_interface.h" /* I2C source clock */ #define I2C_SLAVE_BASEADDR I2C1 @@ -13,21 +14,17 @@ #define I2C_SLAVE_UPPER_ADDR_7BIT (0x72U) #define I2C_DATA_LENGTH (1024U + 8U) -// We'll start with 5 RX commands -#define RX_CMDS_LENGTH 5 -#define I2C_CMD_SLEEP 0xABU static uint8_t g_slave_TX_buff[I2C_DATA_LENGTH]; static uint8_t g_slave_RX_buff[I2C_DATA_LENGTH]; i2c_slave_handle_t g_s_handle; static volatile bool g_SlaveCompletionFlag = false; static volatile bool g_SlaveRxFlag = false; -uint8_t address_match = 0; +static uint8_t address_match = 0; +static uint32_t transferredCount = 0; static i2cWriteCallback_t pfWriteCommsCallback = NULL; static i2cReadCallback_t pfReadCommsCallback = NULL; -static i2cWriteCallback_t pfWriteHIDCallback = NULL; -static i2cReadCallback_t pfReadHIDCallback = NULL; static i2cWriteCallback_t pfWriteFlashCallback = NULL; static i2cReadCallback_t pfReadFlashCallback = NULL; @@ -46,6 +43,7 @@ static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void /* Update information for transmit process */ xfer->data = g_slave_TX_buff; xfer->dataSize = I2C_DATA_LENGTH; + g_SlaveRxFlag = false; break; /* Receive request */ @@ -65,32 +63,12 @@ static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void g_SlaveCompletionFlag = true; xfer->data = NULL; xfer->dataSize = 0; + transferredCount = xfer->transferredCount; // Default driver couldn't differentiate between RX or TX completion // Check flag set in kI2C_SlaveReceiveEvent - if (g_SlaveRxFlag) { - g_SlaveRxFlag = false; - - if (pfWriteCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { - pfWriteCommsCallback(&g_slave_RX_buff[0], xfer->transferredCount); - } - if (pfWriteHIDCallback && address_match == I2C_SLAVE_HID) { - pfWriteHIDCallback(&g_slave_RX_buff[0], xfer->transferredCount); - } - if (pfWriteFlashCallback && address_match == I2C_SLAVE_FLASH) { - pfWriteFlashCallback(&g_slave_RX_buff[0], xfer->transferredCount); - } - } else { - if (pfReadCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { - pfReadCommsCallback(&g_slave_TX_buff[0], xfer->transferredCount); - } - if (pfReadHIDCallback && address_match == I2C_SLAVE_HID) { - pfReadHIDCallback(&g_slave_TX_buff[0], xfer->transferredCount); - } - if (pfReadFlashCallback && address_match == I2C_SLAVE_FLASH) { - pfReadFlashCallback(&g_slave_TX_buff[0], xfer->transferredCount); - } - } + + main_board_event(); break; default: @@ -99,6 +77,25 @@ static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void } } +void board_custom_event() { + + if (g_SlaveRxFlag) { + if (pfWriteCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { + pfWriteCommsCallback(&g_slave_RX_buff[0], transferredCount); + } + if (pfWriteFlashCallback && address_match == I2C_SLAVE_FLASH) { + pfWriteFlashCallback(&g_slave_RX_buff[0], transferredCount); + } + } else { + if (pfReadCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { + pfReadCommsCallback(&g_slave_TX_buff[0], transferredCount); + } + if (pfReadFlashCallback && address_match == I2C_SLAVE_FLASH) { + pfReadFlashCallback(&g_slave_TX_buff[0], transferredCount); + } + } +} + static void i2c_init_pins(void) { /* Port C Clock Gate Control: Clock enabled */ CLOCK_EnableClock(kCLOCK_PortC); @@ -173,7 +170,6 @@ status_t i2c_RegisterWriteCallback(i2cWriteCallback_t writeCallback, uint8_t sla pfWriteCommsCallback = writeCallback; break; case I2C_SLAVE_HID: - pfWriteHIDCallback = writeCallback; break; case I2C_SLAVE_FLASH: pfWriteFlashCallback = writeCallback; @@ -195,7 +191,6 @@ status_t i2c_RegisterReadCallback(i2cReadCallback_t readCallback, uint8_t slaveA pfReadCommsCallback = readCallback; break; case I2C_SLAVE_HID: - pfReadHIDCallback = readCallback; break; case I2C_SLAVE_FLASH: pfReadFlashCallback = readCallback; From 9a7ef01a2cf6848f1d9162533f7afd4f8bdf1131 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Thu, 1 Oct 2020 23:03:47 -0500 Subject: [PATCH 241/617] Move I2C files, to board specific folder --- source/{hic_hal/freescale/kl27z => board/microbitv2}/i2c.c | 0 source/{hic_hal/freescale/kl27z => board/microbitv2}/i2c.h | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename source/{hic_hal/freescale/kl27z => board/microbitv2}/i2c.c (100%) rename source/{hic_hal/freescale/kl27z => board/microbitv2}/i2c.h (100%) diff --git a/source/hic_hal/freescale/kl27z/i2c.c b/source/board/microbitv2/i2c.c similarity index 100% rename from source/hic_hal/freescale/kl27z/i2c.c rename to source/board/microbitv2/i2c.c diff --git a/source/hic_hal/freescale/kl27z/i2c.h b/source/board/microbitv2/i2c.h similarity index 100% rename from source/hic_hal/freescale/kl27z/i2c.h rename to source/board/microbitv2/i2c.h From ec0c8cf43993fef7b4d66d6bba16511e4e0e3024 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Fri, 2 Oct 2020 00:07:23 -0500 Subject: [PATCH 242/617] Don't enable bandgap reference during low power modes --- source/board/microbitv2/pwr_mon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/board/microbitv2/pwr_mon.c b/source/board/microbitv2/pwr_mon.c index 43803f89e..0473fa68e 100644 --- a/source/board/microbitv2/pwr_mon.c +++ b/source/board/microbitv2/pwr_mon.c @@ -80,7 +80,7 @@ uint32_t pwr_mon_vcc_mv(void) { void pwr_mon_bandgap_init(void) { pmc_bandgap_buffer_config_t pmcBandgapConfig; pmcBandgapConfig.enable = true; - pmcBandgapConfig.enableInLowPowerMode = true; + pmcBandgapConfig.enableInLowPowerMode = false; PMC_ConfigureBandgapBuffer(PMC, &pmcBandgapConfig); } From d2655e0b5d050423f0113e9341f99e8edd300945 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Fri, 2 Oct 2020 20:14:22 -0500 Subject: [PATCH 243/617] Low power updates: -Disable USB regulator, it's not needed since we use external regulator -Disable more pins during power down, and disable unecessary internal pullups --- source/board/microbitv2/i2c.c | 14 -------- source/board/microbitv2/power.c | 46 +++++++++++++++++++++------ source/hic_hal/freescale/kl27z/uart.c | 2 +- 3 files changed, 37 insertions(+), 25 deletions(-) diff --git a/source/board/microbitv2/i2c.c b/source/board/microbitv2/i2c.c index 078911f71..df17cda95 100644 --- a/source/board/microbitv2/i2c.c +++ b/source/board/microbitv2/i2c.c @@ -103,22 +103,8 @@ static void i2c_init_pins(void) { /* PORTC1 is configured as I2C1_SCL */ PORT_SetPinMux(PORTC, 1U, kPORT_MuxAlt2); - PORTC->PCR[1] = ((PORTC->PCR[1] & - /* Mask bits to zero which are setting */ - (~(PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK))) - - /* Pull Enable: Internal pullup or pulldown resistor is enabled on the corresponding pin. */ - | (uint32_t)(PORT_PCR_PE_MASK)); - /* PORTC2 is configured as I2C1_SDA */ PORT_SetPinMux(PORTC, 2U, kPORT_MuxAlt2); - - PORTC->PCR[2] = ((PORTC->PCR[2] & - /* Mask bits to zero which are setting */ - (~(PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK))) - - /* Pull Enable: Internal pullup or pulldown resistor is enabled on the corresponding pin. */ - | (uint32_t)(PORT_PCR_PE_MASK)); } static int32_t i2c_start_transfer(void) { diff --git a/source/board/microbitv2/power.c b/source/board/microbitv2/power.c index 1f1cb26c5..8f3609718 100644 --- a/source/board/microbitv2/power.c +++ b/source/board/microbitv2/power.c @@ -86,6 +86,11 @@ void power_init(void) PMC_ClearPeriphIOIsolationFlag(PMC); } + /* Allow writes to USBREGEN */ + SIM->SOPT1CFG |= SIM_SOPT1CFG_URWE_MASK; + /* Disable USB voltage regulator */ + SIM->SOPT1 &= ~SIM_SOPT1_USBREGEN_MASK; + /* Enable rising edge interrupt on WAKE_ON_EDGE pin (VBUS falling edge) to detect USB detach */ PORT_SetPinInterruptConfig(PIN_WAKE_ON_EDGE_PORT, PIN_WAKE_ON_EDGE_BIT, kPORT_InterruptRisingEdge); @@ -166,23 +171,44 @@ static void power_pre_switch_hook(smc_power_state_t originPowerState, app_power_ } uart_uninitialize(); - /* - * Set pin for current leakage. - * UART RX pin: Set to pinmux to disable. - * UART TX pin: Don't need to change. - */ + /* Disable pins to lower current leakage */ PORT_SetPinMux(UART_PORT, PIN_UART_RX_BIT, kPORT_PinDisabledOrAnalog); + PORT_SetPinMux(UART_PORT, PIN_UART_TX_BIT, kPORT_PinDisabledOrAnalog); PORT_SetPinMux(PIN_HID_LED_PORT, PIN_HID_LED_BIT, kPORT_PinDisabledOrAnalog); + + /* Disable I/O pin SWCLK */ + PIN_SWCLK_PORT->PCR[PIN_SWCLK_BIT] = 0; + + /* Disable I/O pin SWDIO */ + PIN_SWDIO_PORT->PCR[PIN_SWDIO_BIT] = 0; + + /* If targetMode is VLLS0, disable I2C pins */ + if (kAPP_PowerModeVlls0 == targetMode) + { + /* PORTC1 is configured as I2C1_SCL */ + PORT_SetPinMux(PORTC, 1U, kPORT_PinDisabledOrAnalog); + + /* PORTC2 is configured as I2C1_SDA */ + PORT_SetPinMux(PORTC, 2U, kPORT_PinDisabledOrAnalog); + } } static void power_post_switch_hook(smc_power_state_t originPowerState, app_power_mode_t targetMode) { - /* - * UART RX pin is set to disable for current leakage, need to re-configure pinmux. - * UART TX pin: Don't need to change. - */ + + /* Configure I/O pin SWCLK */ + PIN_SWCLK_PORT->PCR[PIN_SWCLK_BIT] = PORT_PCR_MUX(1) | /* GPIO */ + PORT_PCR_PE_MASK; /* Pull (Down) enable */ + PIN_SWCLK_GPIO->PSOR = PIN_SWCLK; /* High level */ + PIN_SWCLK_GPIO->PDDR |= PIN_SWCLK; /* Output */ + /* Configure I/O pin SWDIO */ + PIN_SWDIO_PORT->PCR[PIN_SWDIO_BIT] = PORT_PCR_MUX(1) | /* GPIO */ + PORT_PCR_PE_MASK | /* Pull enable */ + PORT_PCR_PS_MASK; /* Pull-up */ + + /* re-configure pinmux of disabled pins */ PORT_SetPinMux(UART_PORT, PIN_UART_RX_BIT, (port_mux_t)PIN_UART_RX_MUX_ALT); - PORT_SetPinMux(PIN_HID_LED_PORT, PIN_HID_LED_BIT, kPORT_PinDisabledOrAnalog); + PORT_SetPinMux(UART_PORT, PIN_UART_TX_BIT, (port_mux_t)PIN_UART_TX_MUX_ALT); uart_initialize(); diff --git a/source/hic_hal/freescale/kl27z/uart.c b/source/hic_hal/freescale/kl27z/uart.c index a57ee653b..bac956b27 100644 --- a/source/hic_hal/freescale/kl27z/uart.c +++ b/source/hic_hal/freescale/kl27z/uart.c @@ -86,7 +86,7 @@ int32_t uart_initialize(void) clear_buffers(); // alternate setting - UART_PORT->PCR[PIN_UART_RX_BIT] = PORT_PCR_MUX(PIN_UART_RX_MUX_ALT) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; + UART_PORT->PCR[PIN_UART_RX_BIT] = PORT_PCR_MUX(PIN_UART_RX_MUX_ALT); UART_PORT->PCR[PIN_UART_TX_BIT] = PORT_PCR_MUX(PIN_UART_TX_MUX_ALT); // transmitter and receiver enabled UART->CTRL |= LPUART_CTRL_RE_MASK | LPUART_CTRL_TE_MASK; From 0cd67bb2b589e6df1b5d5b97912b435870cee7ea Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Mon, 5 Oct 2020 20:24:42 -0500 Subject: [PATCH 244/617] Request debugger power down after target is set to RUN state. --- source/daplink/interface/swd_host.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/source/daplink/interface/swd_host.c b/source/daplink/interface/swd_host.c index ff0b7170c..1e51ee319 100644 --- a/source/daplink/interface/swd_host.c +++ b/source/daplink/interface/swd_host.c @@ -1051,6 +1051,19 @@ uint8_t swd_set_target_state_sw(target_state_t state) osDelay(2); swd_set_target_reset(0); osDelay(2); + + // Power down + if (!swd_write_dp(DP_CTRL_STAT, 0x0)) { + return 0; + } + + // Wait until ACK is deasserted + do { + if (!swd_read_dp(DP_CTRL_STAT, &val)) { + return 0; + } + } while ((val & (CSYSPWRUPACK | CDBGPWRUPACK)) == 1); + swd_off(); break; From 8c4c0e5512c19c76b4c42815435903d81557419c Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Tue, 6 Oct 2020 19:25:09 -0500 Subject: [PATCH 245/617] Increase priority of I2C --- source/board/microbitv2/i2c.c | 2 ++ source/board/microbitv2/power.c | 2 ++ source/hic_hal/freescale/kl27z/uart.c | 2 ++ source/hic_hal/freescale/usbd_kinetis.c | 1 + 4 files changed, 7 insertions(+) diff --git a/source/board/microbitv2/i2c.c b/source/board/microbitv2/i2c.c index df17cda95..cb1508b24 100644 --- a/source/board/microbitv2/i2c.c +++ b/source/board/microbitv2/i2c.c @@ -136,6 +136,8 @@ int32_t i2c_initialize(void) { slaveConfig.enableWakeUp = true; I2C_SlaveInit(I2C_SLAVE_BASEADDR, &slaveConfig, I2C_SLAVE_CLK_FREQ); + + NVIC_SetPriority(I2C1_IRQn, 0x00); /* set highest priority */ i2c_start_transfer(); diff --git a/source/board/microbitv2/power.c b/source/board/microbitv2/power.c index 8f3609718..019c1b448 100644 --- a/source/board/microbitv2/power.c +++ b/source/board/microbitv2/power.c @@ -94,7 +94,9 @@ void power_init(void) /* Enable rising edge interrupt on WAKE_ON_EDGE pin (VBUS falling edge) to detect USB detach */ PORT_SetPinInterruptConfig(PIN_WAKE_ON_EDGE_PORT, PIN_WAKE_ON_EDGE_BIT, kPORT_InterruptRisingEdge); + NVIC_SetPriority(LLWU_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); NVIC_EnableIRQ(LLWU_IRQn); + NVIC_SetPriority(PORTC_PORTD_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); NVIC_EnableIRQ(PORTC_PORTD_IRQn); } diff --git a/source/hic_hal/freescale/kl27z/uart.c b/source/hic_hal/freescale/kl27z/uart.c index bac956b27..da531e5ad 100644 --- a/source/hic_hal/freescale/kl27z/uart.c +++ b/source/hic_hal/freescale/kl27z/uart.c @@ -92,6 +92,8 @@ int32_t uart_initialize(void) UART->CTRL |= LPUART_CTRL_RE_MASK | LPUART_CTRL_TE_MASK; // Enable receiver interrupt and RX Overrun interrupt UART->CTRL |= LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK; + + NVIC_SetPriority(UART_RX_TX_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); NVIC_ClearPendingIRQ(UART_RX_TX_IRQn); NVIC_EnableIRQ(UART_RX_TX_IRQn); return 1; diff --git a/source/hic_hal/freescale/usbd_kinetis.c b/source/hic_hal/freescale/usbd_kinetis.c index 4f06f63fd..61a0bf436 100644 --- a/source/hic_hal/freescale/usbd_kinetis.c +++ b/source/hic_hal/freescale/usbd_kinetis.c @@ -227,6 +227,7 @@ void USBD_Reset(void) USB0->ERREN = 0xFF; /* enable error interrupt sources */ USB0->ADDR = 0x00; /* set default address */ + NVIC_SetPriority(USB0_IRQn, 0x01); /* set second highest priority */ NVIC_EnableIRQ(USB0_IRQn); } From 4559877da604e003ec225b68442b4a74035fa641 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Wed, 7 Oct 2020 01:23:28 -0500 Subject: [PATCH 246/617] I2C low power updates -Add timeout for staying in RUN mode after waking up or receiving I2C transaction -Prevent entering sleep if I2C command is being processed -Update power source when usb is attached/detached -Don't process I2C Writes with nop cmd --- source/board/microbitv2/IO_Config_Override.h | 2 +- source/board/microbitv2/i2c.c | 16 ++++++-- source/board/microbitv2/microbitv2.c | 41 +++++++++----------- source/board/microbitv2/power.c | 20 ++++++---- 4 files changed, 45 insertions(+), 34 deletions(-) diff --git a/source/board/microbitv2/IO_Config_Override.h b/source/board/microbitv2/IO_Config_Override.h index 5e7309c88..2859c5eb1 100644 --- a/source/board/microbitv2/IO_Config_Override.h +++ b/source/board/microbitv2/IO_Config_Override.h @@ -110,7 +110,7 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_KL27Z); #define PIN_WAKE_ON_EDGE (1<event) { @@ -37,6 +40,7 @@ static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void xfer->dataSize = 0; // fsl_i2c.c IRQ updated in fsl_i2c_mod.c to include I2C D register address_match = *(uint8_t*)userData >> 1; + i2c_wake_timeout = 3; // 3 * 30ms tick = 90ms timeout break; /* Transmit request */ case kI2C_SlaveTransmitEvent: @@ -67,8 +71,13 @@ static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void // Default driver couldn't differentiate between RX or TX completion // Check flag set in kI2C_SlaveReceiveEvent - - main_board_event(); + + // Ignore NOP cmd in I2C Write + if (!(g_SlaveRxFlag && g_slave_RX_buff[0] == 0x00)) { + main_board_event(); + } + + i2c_allow_sleep = false; break; default: @@ -76,7 +85,7 @@ static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void break; } } - +// Hook function executed in the main task void board_custom_event() { if (g_SlaveRxFlag) { @@ -94,6 +103,7 @@ void board_custom_event() { pfReadFlashCallback(&g_slave_TX_buff[0], transferredCount); } } + i2c_allow_sleep = true; } static void i2c_init_pins(void) { diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 7609a7be8..0abc70d60 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -80,6 +80,9 @@ uint16_t board_id_hex = 0; volatile uint8_t wake_from_reset = 0; volatile uint8_t wake_from_usb = 0; volatile bool usb_pc_connected = false; +uint8_t i2c_wake_timeout = 0; +bool i2c_allow_sleep = true; +power_source_t power_source; typedef enum { BOARD_VERSION_2_0 = 0, @@ -98,8 +101,8 @@ typedef enum main_shutdown_state { MAIN_SHUTDOWN_PENDING, MAIN_SHUTDOWN_REACHED, MAIN_SHUTDOWN_REACHED_FADE, - MAIN_SHUTDOWN_ALERT, MAIN_SHUTDOWN_REQUESTED, + MAIN_USER_EVENT, MAIN_LED_BLINK_ONCE, MAIN_LED_BLINKING, MAIN_LED_FULL_BRIGHTNESS, @@ -122,13 +125,11 @@ static uint8_t initial_fade_brightness = PWR_LED_INIT_FADE_BRIGHTNESS; static bool power_led_sleep_state_on = PWR_LED_SLEEP_STATE_DEFAULT; static bool automatic_sleep_on = AUTOMATIC_SLEEP_DEFAULT; static app_power_mode_t interface_power_mode = kAPP_PowerModeVlls0; -static power_source_t power_source; -static main_usb_connect_t prev_usb_state; // reset button state count static uint16_t gpio_reset_count = 0; static bool do_remount = false; -flashConfig_t gflashConfig = { +static flashConfig_t gflashConfig = { .key = CFG_KEY, .fileName = FLASH_CFG_FILENAME, .fileSize = FLASH_CFG_FILESIZE, @@ -302,7 +303,7 @@ void handle_reset_button() } else if (gpio_reset_count >= RESET_MID_PRESS) { // Indicate the button has been released when shutdown is requested - main_shutdown_state = MAIN_SHUTDOWN_ALERT; + main_shutdown_state = MAIN_USER_EVENT; } } else if (reset_pressed && gpio_get_reset_btn_fwrd()) { // Reset button is still pressed @@ -348,21 +349,24 @@ void board_30ms_hook() power_led_max_duty_cycle = PWR_LED_ON_BATT_BRIGHTNESS; } - if (prev_usb_state != usb_state) { - power_source = pwr_mon_get_power_source(); + if (wake_from_usb) { + main_shutdown_state = MAIN_USER_EVENT; + + if (usb_state == USB_DISCONNECTED) { + usb_state = USB_CONNECTING; + } + } + + if (i2c_wake_timeout > 0) { + i2c_wake_timeout--; } - prev_usb_state = usb_state; // Enter light sleep if USB is not enumerated and main_shutdown_state is idle if (usb_state == USB_DISCONNECTED && !usb_pc_connected && main_shutdown_state == MAIN_SHUTDOWN_WAITING - && automatic_sleep_on == true && g_s_handle.isBusy == false) { + && automatic_sleep_on == true && g_s_handle.isBusy == false && i2c_wake_timeout == 0 && i2c_allow_sleep) { interface_power_mode = kAPP_PowerModeVlps; main_shutdown_state = MAIN_SHUTDOWN_REQUESTED; } - - if (wake_from_usb) { - main_shutdown_state = MAIN_SHUTDOWN_ALERT; - } switch (main_shutdown_state) { case MAIN_LED_FULL_BRIGHTNESS: @@ -388,7 +392,7 @@ void board_30ms_hook() shutdown_led_dc--; } break; - case MAIN_SHUTDOWN_ALERT: + case MAIN_USER_EVENT: { // Release COMBINED_SENSOR_INT in case it was previously asserted PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); @@ -502,13 +506,6 @@ void board_handle_powerdown() default: break; } - - i2c_deinitialize(); - i2c_initialize(); - - usb_state = USB_CONNECTING; - - gpio_set_hid_led(HID_LED_DEF); } void vfs_user_build_filesystem_hook() { @@ -711,7 +708,7 @@ static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { break; default: i2cResponse.cmdId = gErrorResponse_c; - i2cResponse.cmdData.errorRspCmd.errorCode = gErrorUnknownProperty_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorUnknownCommand_c; break; } diff --git a/source/board/microbitv2/power.c b/source/board/microbitv2/power.c index 019c1b448..802502972 100644 --- a/source/board/microbitv2/power.c +++ b/source/board/microbitv2/power.c @@ -11,8 +11,10 @@ #include "main_interface.h" #include "power.h" +#include "pwr_mon.h" #include "IO_Config.h" #include "uart.h" +#include "i2c.h" #include "rl_usb.h" /******************************************************************************* @@ -28,6 +30,7 @@ extern volatile uint8_t wake_from_reset; extern volatile uint8_t wake_from_usb; extern volatile bool usb_pc_connected; extern main_usb_connect_t usb_state; +extern power_source_t power_source; /******************************************************************************* * Code @@ -59,8 +62,12 @@ void PORTCD_IRQHandler(void) if ((1U << PIN_WAKE_ON_EDGE_BIT) & PORT_GetPinsInterruptFlags(PIN_WAKE_ON_EDGE_PORT)) { PORT_ClearPinsInterruptFlags(PIN_WAKE_ON_EDGE_PORT, (1U << PIN_WAKE_ON_EDGE_BIT)); + + power_source = pwr_mon_get_power_source(); - if ((PIN_WAKE_ON_EDGE_PORT->PCR[PIN_WAKE_ON_EDGE_BIT] & PORT_PCR_IRQC_MASK) == PORT_PCR_IRQC(kPORT_InterruptRisingEdge)) { + bool usb_on = (((PIN_WAKE_ON_EDGE_GPIO->PDIR) >> PIN_WAKE_ON_EDGE_BIT) & 0x01U) ? false : true; + + if (usb_on == false) { /* Reset USB on cable detach (VBUS falling edge) */ USBD_Reset(); usbd_reset_core(); @@ -91,8 +98,8 @@ void power_init(void) /* Disable USB voltage regulator */ SIM->SOPT1 &= ~SIM_SOPT1_USBREGEN_MASK; - /* Enable rising edge interrupt on WAKE_ON_EDGE pin (VBUS falling edge) to detect USB detach */ - PORT_SetPinInterruptConfig(PIN_WAKE_ON_EDGE_PORT, PIN_WAKE_ON_EDGE_BIT, kPORT_InterruptRisingEdge); + /* Enable either edge interrupt on WAKE_ON_EDGE pin to detect USB attach/detach */ + PORT_SetPinInterruptConfig(PIN_WAKE_ON_EDGE_PORT, PIN_WAKE_ON_EDGE_BIT, PIN_WAKE_ON_EDGE_PORT_WAKEUP_TYPE); NVIC_SetPriority(LLWU_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); NVIC_EnableIRQ(LLWU_IRQn); @@ -128,7 +135,6 @@ static void power_enter_mode(app_power_mode_t targetPowerMode) static void power_set_wakeup_config(app_power_mode_t targetMode) { PORT_SetPinInterruptConfig(PIN_SW_RESET_PORT, PIN_SW_RESET_BIT, PIN_SW_RESET_PORT_WAKEUP_TYPE); - PORT_SetPinInterruptConfig(PIN_WAKE_ON_EDGE_PORT, PIN_WAKE_ON_EDGE_BIT, PIN_WAKE_ON_EDGE_PORT_WAKEUP_TYPE); /* If targetMode is VLLS/LLS, setup LLWU. */ if ((kAPP_PowerModeWait != targetMode) && (kAPP_PowerModeVlpw != targetMode) && @@ -197,7 +203,6 @@ static void power_pre_switch_hook(smc_power_state_t originPowerState, app_power_ static void power_post_switch_hook(smc_power_state_t originPowerState, app_power_mode_t targetMode) { - /* Configure I/O pin SWCLK */ PIN_SWCLK_PORT->PCR[PIN_SWCLK_BIT] = PORT_PCR_MUX(1) | /* GPIO */ PORT_PCR_PE_MASK; /* Pull (Down) enable */ @@ -213,7 +218,6 @@ static void power_post_switch_hook(smc_power_state_t originPowerState, app_power PORT_SetPinMux(UART_PORT, PIN_UART_TX_BIT, (port_mux_t)PIN_UART_TX_MUX_ALT); uart_initialize(); - - /* Change to rising edge interrupt on WAKE_ON_EDGE pin (VBUS falling edge) to detect USB detach */ - PORT_SetPinInterruptConfig(PIN_WAKE_ON_EDGE_PORT, PIN_WAKE_ON_EDGE_BIT, kPORT_InterruptRisingEdge); + i2c_deinitialize(); + i2c_initialize(); } From 97d9210742d38a56fa9ca955d9c3d529edbf9316 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Wed, 7 Oct 2020 17:53:03 -0500 Subject: [PATCH 247/617] #64 Assume "PC connected" at the start of USB communication instead of waiting for the whole enumeration process to be finished. --- source/board/microbitv2/microbitv2.c | 10 +++++++--- source/usb/usb_lib.c | 3 +++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 0abc70d60..1aedafe5d 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -336,9 +336,6 @@ void board_30ms_hook() static uint8_t blink_in_progress = 0; if (usb_state == USB_CONNECTED) { - /* Set usb_pc_connected to true to prevent entering sleep mode when host does re-enumeration. - * Will be set to false when the USB cable is detached. */ - usb_pc_connected = true; // configure pin as GPIO PIN_HID_LED_PORT->PCR[PIN_HID_LED_BIT] = PORT_PCR_MUX(1); power_led_max_duty_cycle = PWR_LED_ON_MAX_BRIGHTNESS; @@ -508,6 +505,13 @@ void board_handle_powerdown() } } +void board_usb_sof_event(void) +{ + /* Set usb_pc_connected to true to prevent entering sleep mode when host does re-enumeration. + * Will be set to false when the USB cable is detached. */ + usb_pc_connected = true; +} + void vfs_user_build_filesystem_hook() { uint32_t file_size; error_t status; diff --git a/source/usb/usb_lib.c b/source/usb/usb_lib.c index cbf06ff96..fef24c524 100644 --- a/source/usb/usb_lib.c +++ b/source/usb/usb_lib.c @@ -1068,6 +1068,8 @@ __WEAK void USBD_Reset_Event(void) #endif #endif /* ((USBD_CDC_ACM_ENABLE)) */ +__WEAK void board_usb_sof_event(void) {} + #if ((USBD_HID_ENABLE) || (USBD_ADC_ENABLE) || (USBD_CDC_ACM_ENABLE) || (USBD_CLS_ENABLE)) #ifndef __RTX __WEAK void USBD_SOF_Event(void) @@ -1084,6 +1086,7 @@ __WEAK void USBD_SOF_Event(void) #if (USBD_CLS_ENABLE) USBD_CLS_SOF_Event(); #endif + board_usb_sof_event(); } #endif #endif /* ((USBD_HID_ENABLE) || (USBD_ADC_ENABLE) || (USBD_CDC_ACM_ENABLE) || (USBD_CLS_ENABLE)) */ From fbc4161eeee026dd4f9b168dcbd852c75d1b2d0e Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Thu, 8 Oct 2020 21:59:58 -0500 Subject: [PATCH 248/617] #86 Change type of reset during button press and block button handling when target flash operation is in progress --- source/board/microbitv2/microbitv2.c | 88 ++++++++++++++-------------- 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 1aedafe5d..788405642 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -275,58 +275,58 @@ void handle_reset_button() // button state static uint8_t reset_pressed = 0; - // handle reset button without eventing - if (!reset_pressed && (gpio_get_reset_btn_fwrd() || wake_from_reset)) { #ifdef DRAG_N_DROP_SUPPORT - if (!flash_intf_target->flash_busy()) //added checking if flashing on target is in progress + if (!flash_intf_target->flash_busy()) //added checking if flashing on target is in progress #endif - { + { + // handle reset button without eventing + if (!reset_pressed && (gpio_get_reset_btn_fwrd() || wake_from_reset)) { // Reset button pressed - target_set_state(RESET_HOLD); + target_set_state(RESET_PROGRAM); reset_pressed = 1; gpio_reset_count = 0; wake_from_reset = 0; main_shutdown_state = MAIN_LED_FULL_BRIGHTNESS; - } - } else if (reset_pressed && !gpio_get_reset_btn_fwrd()) { - // Reset button released - target_set_state(RESET_RUN); - reset_pressed = 0; - power_led_sleep_state_on = PWR_LED_SLEEP_STATE_DEFAULT; - - if (gpio_reset_count <= RESET_SHORT_PRESS) { - main_shutdown_state = MAIN_LED_BLINK_ONCE; - } - else if (gpio_reset_count < RESET_MID_PRESS) { - // Indicate button has been released to stop to cancel the shutdown - main_shutdown_state = MAIN_LED_BLINK_ONCE; - } - else if (gpio_reset_count >= RESET_MID_PRESS) { - // Indicate the button has been released when shutdown is requested - main_shutdown_state = MAIN_USER_EVENT; - } - } else if (reset_pressed && gpio_get_reset_btn_fwrd()) { - // Reset button is still pressed - if (gpio_reset_count <= RESET_SHORT_PRESS) { - // Enter the shutdown pending state to begin LED dimming - main_shutdown_state = MAIN_SHUTDOWN_PENDING; - } - else if (gpio_reset_count < RESET_MID_PRESS) { - // Enter the shutdown pending state to begin LED dimming - main_shutdown_state = MAIN_SHUTDOWN_PENDING; - } - else if (gpio_reset_count < RESET_LONG_PRESS) { - // Enter the shutdown reached state to blink LED - main_shutdown_state = MAIN_SHUTDOWN_REACHED; - } - else if (gpio_reset_count >= RESET_LONG_PRESS) { - // Enter the shutdown reached state to blink LED - main_shutdown_state = MAIN_SHUTDOWN_REACHED_FADE; - } + } else if (reset_pressed && !gpio_get_reset_btn_fwrd()) { + // Reset button released + target_set_state(RESET_RUN); + reset_pressed = 0; + power_led_sleep_state_on = PWR_LED_SLEEP_STATE_DEFAULT; + + if (gpio_reset_count <= RESET_SHORT_PRESS) { + main_shutdown_state = MAIN_LED_BLINK_ONCE; + } + else if (gpio_reset_count < RESET_MID_PRESS) { + // Indicate button has been released to stop to cancel the shutdown + main_shutdown_state = MAIN_LED_BLINK_ONCE; + } + else if (gpio_reset_count >= RESET_MID_PRESS) { + // Indicate the button has been released when shutdown is requested + main_shutdown_state = MAIN_USER_EVENT; + } + } else if (reset_pressed && gpio_get_reset_btn_fwrd()) { + // Reset button is still pressed + if (gpio_reset_count <= RESET_SHORT_PRESS) { + // Enter the shutdown pending state to begin LED dimming + main_shutdown_state = MAIN_SHUTDOWN_PENDING; + } + else if (gpio_reset_count < RESET_MID_PRESS) { + // Enter the shutdown pending state to begin LED dimming + main_shutdown_state = MAIN_SHUTDOWN_PENDING; + } + else if (gpio_reset_count < RESET_LONG_PRESS) { + // Enter the shutdown reached state to blink LED + main_shutdown_state = MAIN_SHUTDOWN_REACHED; + } + else if (gpio_reset_count >= RESET_LONG_PRESS) { + // Enter the shutdown reached state to blink LED + main_shutdown_state = MAIN_SHUTDOWN_REACHED_FADE; + } - // Avoid overflow, stop counting after longest event - if (gpio_reset_count <= RESET_MAX_LENGTH_PRESS) { - gpio_reset_count++; + // Avoid overflow, stop counting after longest event + if (gpio_reset_count <= RESET_MAX_LENGTH_PRESS) { + gpio_reset_count++; + } } } } From 3db99b532993d684b66840dca95bc38224b35962 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Thu, 8 Oct 2020 23:09:34 -0500 Subject: [PATCH 249/617] #84 #82 Add hook for detecting when flashing has completed to return LED to its default state and clear pending I2C interrupts --- source/board/microbitv2/microbitv2.c | 12 ++++++++++++ source/daplink/drag-n-drop/vfs_manager.c | 4 ++++ 2 files changed, 16 insertions(+) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 788405642..5802c0394 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -512,6 +512,18 @@ void board_usb_sof_event(void) usb_pc_connected = true; } +void board_vfs_stream_closed_hook() +{ + // Return LED to default ON state + main_shutdown_state = MAIN_SHUTDOWN_WAITING; + + // Clear any pending I2C response + i2c_clearBuffer(); + + // Release COMBINED_SENSOR_INT + PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); +} + void vfs_user_build_filesystem_hook() { uint32_t file_size; error_t status; diff --git a/source/daplink/drag-n-drop/vfs_manager.c b/source/daplink/drag-n-drop/vfs_manager.c index 64a90ba94..d50ae01bc 100644 --- a/source/daplink/drag-n-drop/vfs_manager.c +++ b/source/daplink/drag-n-drop/vfs_manager.c @@ -158,6 +158,7 @@ static void transfer_stream_open(stream_type_t stream, uint32_t start_sector); static void transfer_stream_data(uint32_t sector, const uint8_t *data, uint32_t size); static void transfer_update_state(error_t status); +__WEAK void board_vfs_stream_closed_hook(void){} void vfs_mngr_fs_enable(bool enable) { @@ -717,6 +718,9 @@ static void transfer_stream_data(uint32_t sector, const uint8_t *data, uint32_t file_transfer_state.stream_open = false; file_transfer_state.stream_finished = true; file_transfer_state.stream_optional_finish = true; + + // Custom board hook to notify that a stream has close (flashing finished) + board_vfs_stream_closed_hook(); } else if (ERROR_SUCCESS_DONE_OR_CONTINUE == status) { status = ERROR_SUCCESS; file_transfer_state.stream_optional_finish = true; From fea3b83b488f2cb8c92c397ba1ae861f7fa6c01a Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Fri, 9 Oct 2020 00:13:37 -0500 Subject: [PATCH 250/617] #20 LED Behavior updates --- source/board/microbitv2/flexio_pwm.c | 8 +++---- source/board/microbitv2/microbitv2.c | 36 +++++++++++++++++----------- 2 files changed, 26 insertions(+), 18 deletions(-) diff --git a/source/board/microbitv2/flexio_pwm.c b/source/board/microbitv2/flexio_pwm.c index a3196bf5f..5e81d13ac 100644 --- a/source/board/microbitv2/flexio_pwm.c +++ b/source/board/microbitv2/flexio_pwm.c @@ -68,9 +68,9 @@ void flexio_pwm_set_dutycycle(uint8_t duty) flexio_timer_config_t fxioTimerConfig; /* Check parameter */ - if (duty > 99) + if (duty >= 255) { - duty = 99; + duty = 254; PIN_RED_LED_GPIO->PDDR |= PIN_RED_LED; PIN_RED_LED_GPIO->PSOR = PIN_RED_LED; PORT_SetPinMux(PIN_RED_LED_PORT, PIN_RED_LED_BIT, kPORT_MuxAsGpio); @@ -107,8 +107,8 @@ void flexio_pwm_set_dutycycle(uint8_t duty) /* sum = DEMO_FLEXIO_CLOCK_FREQUENCY / freq_H */ sum = (DEMO_FLEXIO_CLOCK_FREQUENCY * 2 / freq_Hz + 1) / 2; /* Calculate the nearest integer value for lowerValue, the high period of the pwm output */ - /* lowerValue = sum * duty / 100 */ - lowerValue = (sum * duty / 50 + 1) / 2; + /* lowerValue = sum * duty / 255 */ + lowerValue = (sum * duty / 127 + 1) / 2; /* Calculate upper value, the low period of the pwm output */ upperValue = sum - lowerValue; fxioTimerConfig.timerCompare = ((upperValue - 1) << 8U) | (lowerValue - 1); diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 5802c0394..0ace13696 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -52,10 +52,10 @@ #define BRD_ID_1_UPPER_THR_V 935 // Upper threshold in mV for 100nF and 4700R #define BRD_ID_1_LOWER_THR_V 268 // Lower threshold in mV for 100nF and 4700R -#define PWR_LED_ON_MAX_BRIGHTNESS 100 // Max LED Brightness (PC Connected) -#define PWR_LED_INIT_FADE_BRIGHTNESS 80 // Initial fade LED Brightness -#define PWR_LED_ON_BATT_BRIGHTNESS 40 // LED Brightness while being powered by battery -#define PWR_LED_FADEOUT_MIN_BRIGHTNESS 30 // Minimum LED brightness when fading out +#define PWR_LED_ON_MAX_BRIGHTNESS 255 // Max LED Brightness (PC Connected) +#define PWR_LED_INIT_FADE_BRIGHTNESS 200 // Initial fade LED Brightness +#define PWR_LED_ON_BATT_BRIGHTNESS 100 // LED Brightness while being powered by battery +#define PWR_LED_FADEOUT_MIN_BRIGHTNESS 80 // Minimum LED brightness when fading out #define PWR_LED_SLEEP_STATE_DEFAULT true #define AUTOMATIC_SLEEP_DEFAULT true @@ -120,6 +120,7 @@ static uint32_t read_file_data_txt(uint32_t sector_offset, uint8_t *data, uint32 // shutdown state static main_shutdown_state_t main_shutdown_state = MAIN_SHUTDOWN_WAITING; static uint8_t shutdown_led_dc = PWR_LED_ON_MAX_BRIGHTNESS; +static uint8_t final_fade_led_dc = 0; static uint8_t power_led_max_duty_cycle = PWR_LED_ON_MAX_BRIGHTNESS; static uint8_t initial_fade_brightness = PWR_LED_INIT_FADE_BRIGHTNESS; static bool power_led_sleep_state_on = PWR_LED_SLEEP_STATE_DEFAULT; @@ -211,10 +212,10 @@ static void set_board_id(mb_version_t board_version) { } } -// Apply a gamma curve to the LED. Input brightness between 0-100 +// Apply a gamma curve to the LED. Input brightness between 0-255 static inline uint8_t get_led_gamma(uint8_t brightness) { uint8_t duty_cycle; - duty_cycle = (brightness * brightness * brightness + 5000) / 10000; + duty_cycle = (brightness * brightness * brightness + 32512) / (255*255); return duty_cycle; } @@ -382,11 +383,12 @@ void board_30ms_hook() case MAIN_SHUTDOWN_REACHED: // Hold LED in min brightness shutdown_led_dc = PWR_LED_FADEOUT_MIN_BRIGHTNESS; + final_fade_led_dc = get_led_gamma(PWR_LED_FADEOUT_MIN_BRIGHTNESS); break; case MAIN_SHUTDOWN_REACHED_FADE: // Fast fade to off - if (shutdown_led_dc > 0) { - shutdown_led_dc--; + if (final_fade_led_dc > 0) { + final_fade_led_dc--; } break; case MAIN_USER_EVENT: @@ -450,10 +452,10 @@ void board_30ms_hook() if (shutdown_led_dc < 10) { shutdown_led_dc++; } else if (shutdown_led_dc == 10) { - shutdown_led_dc = 100; - } else if (shutdown_led_dc <= 90) { + shutdown_led_dc = PWR_LED_ON_MAX_BRIGHTNESS; + } else if (shutdown_led_dc <= (PWR_LED_ON_MAX_BRIGHTNESS - 10)) { shutdown_led_dc = 0; - } else if (shutdown_led_dc > 90) { + } else if (shutdown_led_dc > (PWR_LED_ON_MAX_BRIGHTNESS - 10)) { shutdown_led_dc--; } @@ -471,7 +473,7 @@ void board_30ms_hook() } } else { blink_in_progress = 10; - shutdown_led_dc = 100; + shutdown_led_dc = PWR_LED_ON_MAX_BRIGHTNESS; } if (blink_in_progress == 0) { @@ -481,8 +483,14 @@ void board_30ms_hook() default: break; } - uint8_t gamma_led_dc = get_led_gamma(shutdown_led_dc); - flexio_pwm_set_dutycycle(gamma_led_dc); + + // Use gamma curve except in final fade + if (main_shutdown_state != MAIN_SHUTDOWN_REACHED_FADE) { + uint8_t gamma_led_dc = get_led_gamma(shutdown_led_dc); + flexio_pwm_set_dutycycle(gamma_led_dc); + } else { + flexio_pwm_set_dutycycle(final_fade_led_dc); + } // Remount if requested. if (do_remount) { From 8beea11ef5609d8b694728595a40f5b43a3a843b Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Mon, 12 Oct 2020 21:16:35 -0500 Subject: [PATCH 251/617] #62 Take ADC measurements for VIN and battery --- source/board/microbitv2/microbitv2.c | 8 +++-- source/board/microbitv2/pwr_mon.c | 47 +++++++++++++++++----------- source/board/microbitv2/pwr_mon.h | 3 +- 3 files changed, 35 insertions(+), 23 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 0ace13696..bb6c41313 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -638,9 +638,11 @@ static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { memcpy(&i2cResponse.cmdData.readRspCmd.data, &power_source, sizeof(power_source)); break; case gPowerConsumption_c: { - uint32_t power_consumption = 1; - i2cResponse.cmdData.readRspCmd.dataSize = sizeof(power_consumption); - memcpy(&i2cResponse.cmdData.readRspCmd.data, &power_consumption, sizeof(power_consumption)); + uint32_t vin_voltage_uv = pwr_mon_get_vin_mv() * 1000; + uint32_t vbat_voltage_uv = pwr_mon_get_vbat_mv() * 1000; + i2cResponse.cmdData.readRspCmd.dataSize = sizeof(vin_voltage_uv) + sizeof(vbat_voltage_uv); + memcpy(&i2cResponse.cmdData.readRspCmd.data[0], &vbat_voltage_uv, sizeof(vbat_voltage_uv)); + memcpy(&i2cResponse.cmdData.readRspCmd.data[sizeof(vbat_voltage_uv)], &vin_voltage_uv, sizeof(vin_voltage_uv)); } break; case gUSBEnumerationState_c: diff --git a/source/board/microbitv2/pwr_mon.c b/source/board/microbitv2/pwr_mon.c index 0473fa68e..37ebf7019 100644 --- a/source/board/microbitv2/pwr_mon.c +++ b/source/board/microbitv2/pwr_mon.c @@ -19,8 +19,8 @@ #define BATT_MIN_VOLTAGE 1500 void pwr_mon_bandgap_init(void); -uint32_t pwr_mon_read_vbg(uint32_t channelGroup); -uint32_t pwr_mon_adc_to_mv(uint32_t raw_adc); +static uint32_t pwr_mon_read_vbg(uint32_t channelGroup); +static uint32_t pwr_mon_adc_to_mv(uint32_t raw_adc); void pwr_mon_init(void) { @@ -40,21 +40,14 @@ void pwr_mon_init(void) power_source_t pwr_mon_get_power_source(void) { power_source_t power_source = PWR_SOURCE_NONE; uint32_t bat_voltage_mv = 0; - // Detect if device is battery powered - GPIO_PinWrite(PIN_RUN_VBAT_SENSE_GPIO, PIN_RUN_VBAT_SENSE_BIT, 1); - // Add a ~3ms delay to allow the 100nF capacitors to charge to about 3*RC. - // 3 clock cycles per loop at -O2 ARMCC optimization - for (uint32_t count = 48000; count > 0UL; count--); - uint32_t bat_adc = adc_read_channel(0, PIN_VMON_BAT_ADC_CH, PIN_VMON_BAT_ADC_MUX); - GPIO_PinWrite(PIN_RUN_VBAT_SENSE_GPIO, PIN_RUN_VBAT_SENSE_BIT, 0); - + + // Read WAKE_ON_EDGE pin for detecting if board is USB powered bool usb_on = (((PIN_WAKE_ON_EDGE_GPIO->PDIR) >> PIN_WAKE_ON_EDGE_BIT) & 0x01U) ? false : true; - // Compensate for voltage divider with ratio of 11 - bat_adc = bat_adc * 11; - - bat_voltage_mv = pwr_mon_adc_to_mv(bat_adc); + // Read battery voltage + bat_voltage_mv = pwr_mon_get_vbat_mv(); + // Get power source based on battery and USB if (usb_on == true && bat_voltage_mv < (BATT_MIN_VOLTAGE)) { power_source = PWR_USB_ONLY; } else if (usb_on == true && bat_voltage_mv >= (BATT_MIN_VOLTAGE)) { @@ -68,8 +61,24 @@ power_source_t pwr_mon_get_power_source(void) { return power_source; } -uint32_t pwr_mon_vcc_mv(void) { - // ADC read the Vref (same as Vcc) and the Vbg 1V internal reference +uint32_t pwr_mon_get_vbat_mv(void) { + // Enable voltage divider to take measurement + GPIO_PinWrite(PIN_RUN_VBAT_SENSE_GPIO, PIN_RUN_VBAT_SENSE_BIT, 1); + // Add a ~3ms delay to allow the 100nF capacitors to charge to about 3*RC. + // 3 clock cycles per loop at -O2 ARMCC optimization + for (uint32_t count = 48000; count > 0UL; count--); + uint32_t bat_adc = adc_read_channel(0, PIN_VMON_BAT_ADC_CH, PIN_VMON_BAT_ADC_MUX); + // Disable voltage divider + GPIO_PinWrite(PIN_RUN_VBAT_SENSE_GPIO, PIN_RUN_VBAT_SENSE_BIT, 0); + + // Compensate for voltage divider with ratio of 11 + bat_adc = bat_adc * 11; + + return pwr_mon_adc_to_mv(bat_adc); +} + +uint32_t pwr_mon_get_vin_mv(void) { + // ADC read the Vref (same as Vdda) and the Vbg 1V internal reference uint32_t vref_high = adc_read_channel(0, ADC_VREFH_CHANNEL, ADC_VREFH_MUX); uint32_t ref_volt = pwr_mon_read_vbg(0); @@ -77,14 +86,14 @@ uint32_t pwr_mon_vcc_mv(void) { return vref_high * 1000 / ref_volt; } -void pwr_mon_bandgap_init(void) { +static void pwr_mon_bandgap_init(void) { pmc_bandgap_buffer_config_t pmcBandgapConfig; pmcBandgapConfig.enable = true; pmcBandgapConfig.enableInLowPowerMode = false; PMC_ConfigureBandgapBuffer(PMC, &pmcBandgapConfig); } -uint32_t pwr_mon_read_vbg(uint32_t channelGroup) { +static uint32_t pwr_mon_read_vbg(uint32_t channelGroup) { // Ensure the Vbg is enabled from first use only static bool bandgap_enabled = false; if (!bandgap_enabled) { @@ -94,7 +103,7 @@ uint32_t pwr_mon_read_vbg(uint32_t channelGroup) { return adc_read_channel(channelGroup, ADC_VBG_CHANNEL, ADC_VBG_MUX); } -uint32_t pwr_mon_adc_to_mv(uint32_t raw_adc) +static uint32_t pwr_mon_adc_to_mv(uint32_t raw_adc) { // ADC read Vbg, a 1V internal reference uint32_t ref_volt_read = pwr_mon_read_vbg(0); diff --git a/source/board/microbitv2/pwr_mon.h b/source/board/microbitv2/pwr_mon.h index 15797386c..d5524d6a8 100644 --- a/source/board/microbitv2/pwr_mon.h +++ b/source/board/microbitv2/pwr_mon.h @@ -21,7 +21,8 @@ typedef enum { void pwr_mon_init(void); power_source_t pwr_mon_get_power_source(void); -uint32_t pwr_mon_vcc_mv(void); +uint32_t pwr_mon_get_vin_mv(void); +uint32_t pwr_mon_get_vbat_mv(void); #ifdef __cplusplus From 694d52651d4e60dc578268f1c0041b7ba6eac329 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Mon, 12 Oct 2020 23:37:48 -0500 Subject: [PATCH 252/617] #87 WebUSB LED blink workaround --- source/daplink/cmsis-dap/DAP_vendor.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/source/daplink/cmsis-dap/DAP_vendor.c b/source/daplink/cmsis-dap/DAP_vendor.c index 5a4fd79db..ce34cab28 100644 --- a/source/daplink/cmsis-dap/DAP_vendor.c +++ b/source/daplink/cmsis-dap/DAP_vendor.c @@ -102,6 +102,9 @@ uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { // uart read int32_t read_len = 62; read_len = uart_read_data(response + 1, read_len); + if (read_len) { + main_blink_cdc_led(MAIN_LED_FLASH); + } response[0] = read_len; // increment request and response count num += (read_len + 1); @@ -112,6 +115,7 @@ uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { int32_t write_len = *request; request++; uart_write_data((uint8_t *)request, write_len); + main_blink_cdc_led(MAIN_LED_FLASH); *response = 1; num += ((write_len + 1) << 16) | 1; break; @@ -157,6 +161,7 @@ uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { // write to mass storage device uint32_t write_len = *request; request++; + main_blink_msc_led(MAIN_LED_FLASH); *response = stream_write((uint8_t *)request, write_len); num += ((write_len + 1) << 16) | 1; break; From cc8643baf643495e17e5b624a6241b1e7614925d Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Tue, 13 Oct 2020 23:05:20 -0500 Subject: [PATCH 253/617] #86 Return reset button to default state after flashing finishes to ignore any long press event --- source/board/microbitv2/microbitv2.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index bb6c41313..351f02f6d 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -128,6 +128,8 @@ static bool automatic_sleep_on = AUTOMATIC_SLEEP_DEFAULT; static app_power_mode_t interface_power_mode = kAPP_PowerModeVlls0; // reset button state count static uint16_t gpio_reset_count = 0; +// button state +static uint8_t reset_pressed = 0; static bool do_remount = false; static flashConfig_t gflashConfig = { @@ -273,9 +275,6 @@ static void prerun_board_config(void) // Handle the reset button behavior, this function is called in the main task every 30ms void handle_reset_button() { - // button state - static uint8_t reset_pressed = 0; - #ifdef DRAG_N_DROP_SUPPORT if (!flash_intf_target->flash_busy()) //added checking if flashing on target is in progress #endif @@ -522,7 +521,9 @@ void board_usb_sof_event(void) void board_vfs_stream_closed_hook() { - // Return LED to default ON state + // Return reset button and LED to default state + reset_pressed = 0; + power_led_sleep_state_on = PWR_LED_SLEEP_STATE_DEFAULT; main_shutdown_state = MAIN_SHUTDOWN_WAITING; // Clear any pending I2C response From 0c4c141e06889cc236c1a0cf2ad9b062b1dfb4c9 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Wed, 14 Oct 2020 01:03:28 -0500 Subject: [PATCH 254/617] #92 Erase flash storage with erase.act file and allow filesize of up to 127KB --- source/board/microbitv2/microbitv2.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 351f02f6d..11f28f782 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -61,7 +61,6 @@ #define FLASH_CONFIG_ADDRESS (0x00020000) #define FLASH_CONFIG_SIZE (0x00000400) -#define FLASH_DAL_CFG_SIZE (0x00000400) #define FLASH_INTERFACE_SIZE (128*1024) #define FLASH_STORAGE_ADDRESS (0x00020400) #define FLASH_CFG_FILENAME "DATA BIN" @@ -533,6 +532,16 @@ void board_vfs_stream_closed_hook() PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); } +bool vfs_user_magic_file_hook(const vfs_filename_t filename, bool *do_remount) +{ + if (!memcmp(filename, "ERASE ACT", sizeof(vfs_filename_t))) { + // Erase last 128KB flash block + FLASH_Erase(&g_flash, FLASH_CONFIG_ADDRESS, g_flash.PFlashTotalSize / g_flash.PFlashBlockCount, kFLASH_apiEraseKey); + } + + return false; +} + void vfs_user_build_filesystem_hook() { uint32_t file_size; error_t status; @@ -935,7 +944,7 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { pI2cCommand->cmdData.data[3] << 0; /* Validate file size */ - if (tempFileSize <= (FLASH_INTERFACE_SIZE - FLASH_CONFIG_SIZE - FLASH_DAL_CFG_SIZE)) { + if (tempFileSize <= (FLASH_INTERFACE_SIZE - FLASH_CONFIG_SIZE)) { gflashConfig.fileSize = tempFileSize; tempFileSize = __REV(gflashConfig.fileSize); i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); @@ -996,7 +1005,7 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); break; case gFlashStorageSize_c: - pI2cCommand->cmdData.data[0] = (FLASH_INTERFACE_SIZE - FLASH_CONFIG_SIZE - FLASH_DAL_CFG_SIZE)/1024; + pI2cCommand->cmdData.data[0] = (FLASH_INTERFACE_SIZE - FLASH_CONFIG_SIZE)/1024; i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 2); break; case gFlashSectorSize_c: From 57cbe85a6f338e61385d625935505b6bae61a9fd Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Wed, 14 Oct 2020 01:07:23 -0500 Subject: [PATCH 255/617] #54 Bump DAPLink version to 257 --- records/tools/version.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/records/tools/version.yaml b/records/tools/version.yaml index e76642cb8..f217dddb0 100644 --- a/records/tools/version.yaml +++ b/records/tools/version.yaml @@ -1,3 +1,3 @@ common: macros: - - DAPLINK_VERSION=256 + - DAPLINK_VERSION=257 From 84fdb29b404f1429497a7991fa3a99aa6b4e8e3a Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Wed, 14 Oct 2020 20:31:01 -0500 Subject: [PATCH 256/617] #87 Improve power source handling with edge connector --- source/board/microbitv2/microbitv2.c | 1 + source/board/microbitv2/pwr_mon.c | 13 ++++++++++--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 11f28f782..cf9260bef 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -644,6 +644,7 @@ static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { } break; case gPowerState_c: + power_source = pwr_mon_get_power_source(); i2cResponse.cmdData.readRspCmd.dataSize = sizeof(power_source); memcpy(&i2cResponse.cmdData.readRspCmd.data, &power_source, sizeof(power_source)); break; diff --git a/source/board/microbitv2/pwr_mon.c b/source/board/microbitv2/pwr_mon.c index 37ebf7019..c83cec78c 100644 --- a/source/board/microbitv2/pwr_mon.c +++ b/source/board/microbitv2/pwr_mon.c @@ -40,6 +40,7 @@ void pwr_mon_init(void) power_source_t pwr_mon_get_power_source(void) { power_source_t power_source = PWR_SOURCE_NONE; uint32_t bat_voltage_mv = 0; + uint32_t vin_voltage_mv = 0; // Read WAKE_ON_EDGE pin for detecting if board is USB powered bool usb_on = (((PIN_WAKE_ON_EDGE_GPIO->PDIR) >> PIN_WAKE_ON_EDGE_BIT) & 0x01U) ? false : true; @@ -47,15 +48,21 @@ power_source_t pwr_mon_get_power_source(void) { // Read battery voltage bat_voltage_mv = pwr_mon_get_vbat_mv(); + // Read Vin voltage + vin_voltage_mv = pwr_mon_get_vin_mv(); + // Get power source based on battery and USB if (usb_on == true && bat_voltage_mv < (BATT_MIN_VOLTAGE)) { power_source = PWR_USB_ONLY; } else if (usb_on == true && bat_voltage_mv >= (BATT_MIN_VOLTAGE)) { power_source = PWR_USB_AND_BATT; } else if (usb_on == false && bat_voltage_mv >= (BATT_MIN_VOLTAGE)) { - power_source = PWR_BATT_ONLY; - } else if (usb_on == false && bat_voltage_mv < (BATT_MIN_VOLTAGE)) { - power_source = PWR_SOURCE_NONE; + // If battery voltage is greater than Vin, it means the battery is used + if ( bat_voltage_mv + 200 > vin_voltage_mv ) { + power_source = PWR_BATT_ONLY; + } else { + power_source = PWR_SOURCE_NONE; + } } return power_source; From ee7e9a312199dc7a0aa06dc89579dcc276195ad0 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Thu, 15 Oct 2020 13:25:11 -0500 Subject: [PATCH 257/617] #95 Ignore out of bounds read for the storage file --- source/board/microbitv2/microbitv2.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index cf9260bef..c74b72066 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -582,7 +582,10 @@ void vfs_user_build_filesystem_hook() { // File callback to be used with vfs_add_file to return file contents static uint32_t read_file_data_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors) { - memcpy(data, (uint8_t *) (FLASH_STORAGE_ADDRESS + VFS_SECTOR_SIZE * sector_offset), VFS_SECTOR_SIZE); + // Ignore out of bound reads + if ( (FLASH_STORAGE_ADDRESS + VFS_SECTOR_SIZE * sector_offset) < (FLASH_CONFIG_ADDRESS + FLASH_INTERFACE_SIZE) ) { + memcpy(data, (uint8_t *) (FLASH_STORAGE_ADDRESS + VFS_SECTOR_SIZE * sector_offset), VFS_SECTOR_SIZE); + } return VFS_SECTOR_SIZE; } From b47b6872f72b6af9c8ec6819dbd383dc8032ba7b Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Sun, 18 Oct 2020 00:10:46 -0500 Subject: [PATCH 258/617] #99 Enable flash protection on DAPLink bootloader region - Set backdoor key to 'MICROBIT'. - Enable FPROT for first 32 kB of flash. - Fix FPROTx numbering according to KL27 RM, where FPROT3 is at address 0x408. - Enable backdoor key in FSEC. - Added asterisks next to selected options in comments for FOPT and FSEC. --- .../freescale/kl27z/armcc/startup_MKL27Z4.s | 120 +++++++++--------- 1 file changed, 60 insertions(+), 60 deletions(-) diff --git a/source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s b/source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s index 910b90bab..18074d8ec 100644 --- a/source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s +++ b/source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s @@ -167,49 +167,35 @@ __Vectors_Size EQU __Vectors_End - __Vectors ; Backdoor Comparison Key 5. <0x0-0xFF:2> ; Backdoor Comparison Key 6. <0x0-0xFF:2> ; Backdoor Comparison Key 7. <0x0-0xFF:2> -BackDoorK0 EQU 0xFF -BackDoorK1 EQU 0xFF -BackDoorK2 EQU 0xFF -BackDoorK3 EQU 0xFF -BackDoorK4 EQU 0xFF -BackDoorK5 EQU 0xFF -BackDoorK6 EQU 0xFF -BackDoorK7 EQU 0xFF +BackDoorK0 EQU 0x4D ; 'M' +BackDoorK1 EQU 0x49 ; 'I' +BackDoorK2 EQU 0x43 ; 'C' +BackDoorK3 EQU 0x52 ; 'R' +BackDoorK4 EQU 0x4F ; 'O' +BackDoorK5 EQU 0x42 ; 'B' +BackDoorK6 EQU 0x49 ; 'I' +BackDoorK7 EQU 0x54 ; 'T' ; ; Program flash protection bytes (FPROT) ; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. ; Each bit protects a 1/32 region of the program flash memory. -; FPROT0 -; Program Flash Region Protect Register 0 +; FPROT3 +; Program Flash Region Protect Register 3 ; 1/32 - 8/32 region -; FPROT0.0 -; FPROT0.1 -; FPROT0.2 -; FPROT0.3 -; FPROT0.4 -; FPROT0.5 -; FPROT0.6 -; FPROT0.7 -nFPROT0 EQU 0x00 -FPROT0 EQU nFPROT0:EOR:0xFF -; -; FPROT1 -; Program Flash Region Protect Register 1 -; 9/32 - 16/32 region -; FPROT1.0 -; FPROT1.1 -; FPROT1.2 -; FPROT1.3 -; FPROT1.4 -; FPROT1.5 -; FPROT1.6 -; FPROT1.7 -nFPROT1 EQU 0x00 -FPROT1 EQU nFPROT1:EOR:0xFF +; FPROT3.0 +; FPROT3.1 +; FPROT3.2 +; FPROT3.3 +; FPROT3.4 +; FPROT3.5 +; FPROT3.6 +; FPROT3.7 +nFPROT3 EQU 0x0F ; Enable protection of the first 32 kB of flash +FPROT3 EQU nFPROT3:EOR:0xFF ; ; FPROT2 ; Program Flash Region Protect Register 2 -; 17/32 - 24/32 region +; 9/32 - 16/32 region ; FPROT2.0 ; FPROT2.1 ; FPROT2.2 @@ -221,43 +207,57 @@ FPROT1 EQU nFPROT1:EOR:0xFF nFPROT2 EQU 0x00 FPROT2 EQU nFPROT2:EOR:0xFF ; -; FPROT3 -; Program Flash Region Protect Register 3 +; FPROT1 +; Program Flash Region Protect Register 1 +; 17/32 - 24/32 region +; FPROT1.0 +; FPROT1.1 +; FPROT1.2 +; FPROT1.3 +; FPROT1.4 +; FPROT1.5 +; FPROT1.6 +; FPROT1.7 +nFPROT1 EQU 0x00 +FPROT1 EQU nFPROT1:EOR:0xFF +; +; FPROT0 +; Program Flash Region Protect Register 0 ; 25/32 - 32/32 region -; FPROT3.0 -; FPROT3.1 -; FPROT3.2 -; FPROT3.3 -; FPROT3.4 -; FPROT3.5 -; FPROT3.6 -; FPROT3.7 -nFPROT3 EQU 0x00 -FPROT3 EQU nFPROT3:EOR:0xFF +; FPROT0.0 +; FPROT0.1 +; FPROT0.2 +; FPROT0.3 +; FPROT0.4 +; FPROT0.5 +; FPROT0.6 +; FPROT0.7 +nFPROT0 EQU 0x00 +FPROT0 EQU nFPROT0:EOR:0xFF ; ; ; Flash nonvolatile option byte (FOPT) ; Allows the user to customize the operation of the MCU at boot time. ; LPBOOT0 ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. -; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. +; * <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. ; BOOTPIN_OPT -; <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin +; * <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin ; <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits ; NMI_DIS -; <0=> NMI interrupts are always blocked +; * <0=> NMI interrupts are always blocked ; <1=> NMI_b pin/interrupts reset default to enabled ; RESET_PIN_CFG ; <0=> RESET pin is disabled following a POR and cannot be enabled as reset function -; <1=> RESET_b pin is dedicated +; * <1=> RESET_b pin is dedicated ; LPBOOT1 ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. -; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. +; * <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. ; FAST_INIT ; <0=> Slower initialization -; <1=> Fast Initialization +; * <1=> Fast Initialization ; BOOTSRC_SEL -; <0=> Boot from Flash +; * <0=> Boot from Flash ; <2=> Boot from ROM ; <3=> Boot from ROM ; Boot source selection @@ -267,21 +267,21 @@ FOPT EQU 0x39 ; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", ; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! ; SEC -; <2=> MCU security status is unsecure +; * <2=> MCU security status is unsecure ; <3=> MCU security status is secure ; Flash Security ; FSLACC ; <2=> Freescale factory access denied -; <3=> Freescale factory access granted +; * <3=> Freescale factory access granted ; Freescale Failure Analysis Access Code ; MEEN ; <2=> Mass erase is disabled -; <3=> Mass erase is enabled +; * <3=> Mass erase is enabled ; KEYEN -; <2=> Backdoor key access enabled +; * <2=> Backdoor key access enabled ; <3=> Backdoor key access disabled ; Backdoor Key Security Enable -FSEC EQU 0xFE +FSEC EQU 0xBE ; ; @@ -293,7 +293,7 @@ FSEC EQU 0xFE DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 - DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 + DCB FPROT3 , FPROT2 , FPROT1 , FPROT0 DCB FSEC , FOPT , 0xFF , 0xFF AREA |.text|, CODE, READONLY From 01b1f06f9cc9b9750b5ec2888a62359ce1aa3e8a Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Tue, 5 Jan 2021 22:47:20 -0600 Subject: [PATCH 259/617] Formatting and indentation --- source/daplink/cmsis-dap/DAP.c | 2 -- source/daplink/drag-n-drop/intelhex.c | 4 ++-- source/daplink/interface/main_interface.c | 16 ++++++++-------- source/daplink/settings/settings_rom.c | 2 +- 4 files changed, 11 insertions(+), 13 deletions(-) diff --git a/source/daplink/cmsis-dap/DAP.c b/source/daplink/cmsis-dap/DAP.c index 5ff8bc34b..7e96462d2 100644 --- a/source/daplink/cmsis-dap/DAP.c +++ b/source/daplink/cmsis-dap/DAP.c @@ -1777,8 +1777,6 @@ void DAP_Setup(void) { // Default settings DAP_Data.debug_port = 0U; - // DAP_Data.fast_clock = 0U; - // DAP_Data.clock_delay = CLOCK_DELAY(DAP_DEFAULT_SWJ_CLOCK); DAP_Data.nominal_clock = DAP_DEFAULT_SWJ_CLOCK; DAP_Data.transfer.idle_cycles = 0U; DAP_Data.transfer.retry_count = 100U; diff --git a/source/daplink/drag-n-drop/intelhex.c b/source/daplink/drag-n-drop/intelhex.c index 4ecff98fc..fe222540b 100644 --- a/source/daplink/drag-n-drop/intelhex.c +++ b/source/daplink/drag-n-drop/intelhex.c @@ -32,8 +32,8 @@ enum hex_record_t { START_SEG_ADDR_RECORD = 3, EXT_LINEAR_ADDR_RECORD = 4, START_LINEAR_ADDR_RECORD = 5, - CUSTOM_METADATA_RECORD = 0x0A, - CUSTOM_DATA_RECORD = 0x0D, + CUSTOM_METADATA_RECORD = 0x0A, + CUSTOM_DATA_RECORD = 0x0D, }; typedef union hex_line_t hex_line_t; diff --git a/source/daplink/interface/main_interface.c b/source/daplink/interface/main_interface.c index 645ea3eaa..281df332b 100644 --- a/source/daplink/interface/main_interface.c +++ b/source/daplink/interface/main_interface.c @@ -433,14 +433,14 @@ void main_task(void * arg) case USB_CONNECTED: case USB_DISCONNECTED: - if (usbd_configured()) { - usb_state = USB_CONNECTED; - } - else { - usb_state = USB_DISCONNECTED; - usb_state_count = USB_CONNECT_DELAY; - usb_no_config_count = USB_CONFIGURE_TIMEOUT; - } + if (usbd_configured()) { + usb_state = USB_CONNECTED; + } + else { + usb_state = USB_DISCONNECTED; + usb_state_count = USB_CONNECT_DELAY; + usb_no_config_count = USB_CONFIGURE_TIMEOUT; + } default: break; } diff --git a/source/daplink/settings/settings_rom.c b/source/daplink/settings/settings_rom.c index e355459e8..2ecd00ca8 100644 --- a/source/daplink/settings/settings_rom.c +++ b/source/daplink/settings/settings_rom.c @@ -44,9 +44,9 @@ typedef struct __attribute__((__packed__)) cfg_setting { uint8_t auto_rst; uint8_t automation_allowed; uint8_t overflow_detect; + uint8_t detect_incompatible_target; // Add new members here - uint8_t detect_incompatible_target; } cfg_setting_t; From 0db13f527c4d78d52796a7f142c467b494d46cdc Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Tue, 5 Jan 2021 23:24:59 -0600 Subject: [PATCH 260/617] Add copyright and license header --- source/board/kl27z_microbit_bl.c | 1 + source/board/microbitv2/flexio_pwm.c | 24 +++++++++++++++++++----- source/board/microbitv2/flexio_pwm.h | 22 ++++++++++++++++++++++ source/board/microbitv2/i2c.c | 22 ++++++++++++++++++++++ source/board/microbitv2/i2c.h | 21 +++++++++++++++++++-- source/board/microbitv2/i2c_commands.h | 19 ++++++++++++++++++- source/board/microbitv2/led_error_app.h | 22 ++++++++++++++++++++++ source/board/microbitv2/microbitv2.c | 2 ++ source/board/microbitv2/power.c | 20 +++++++++++++++++++- source/board/microbitv2/power.h | 22 ++++++++++++++++++++++ source/board/microbitv2/pwr_mon.c | 19 ++++++++++++++++++- source/board/microbitv2/pwr_mon.h | 19 ++++++++++++++++++- source/hic_hal/adc.h | 19 ++++++++++++++++++- source/hic_hal/freescale/kl27z/adc.c | 19 ++++++++++++++++++- 14 files changed, 238 insertions(+), 13 deletions(-) diff --git a/source/board/kl27z_microbit_bl.c b/source/board/kl27z_microbit_bl.c index 8f65423b5..7d0c668ff 100644 --- a/source/board/kl27z_microbit_bl.c +++ b/source/board/kl27z_microbit_bl.c @@ -4,6 +4,7 @@ * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * Copyright 2020 NXP * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may diff --git a/source/board/microbitv2/flexio_pwm.c b/source/board/microbitv2/flexio_pwm.c index 5e81d13ac..496c027b6 100644 --- a/source/board/microbitv2/flexio_pwm.c +++ b/source/board/microbitv2/flexio_pwm.c @@ -1,9 +1,23 @@ -/* - * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. +/** + * @file flexio_pwm.c + * @brief * - * SPDX-License-Identifier: BSD-3-Clause + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright 2020 NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #include "fsl_flexio.h" diff --git a/source/board/microbitv2/flexio_pwm.h b/source/board/microbitv2/flexio_pwm.h index 8c70a2990..2846a8ae0 100644 --- a/source/board/microbitv2/flexio_pwm.h +++ b/source/board/microbitv2/flexio_pwm.h @@ -1,3 +1,25 @@ +/** + * @file flexio_pwm.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright 2020 NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + #ifndef FLEXIO_PWM_H_ #define FLEXIO_PWM_H_ diff --git a/source/board/microbitv2/i2c.c b/source/board/microbitv2/i2c.c index 6db14d7d6..bf3efe8d7 100644 --- a/source/board/microbitv2/i2c.c +++ b/source/board/microbitv2/i2c.c @@ -1,3 +1,25 @@ +/** + * @file i2c.c + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright 2020 NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + #include "i2c.h" #include "fsl_i2c.h" #include "fsl_clock.h" diff --git a/source/board/microbitv2/i2c.h b/source/board/microbitv2/i2c.h index 95e783d03..8de362943 100644 --- a/source/board/microbitv2/i2c.h +++ b/source/board/microbitv2/i2c.h @@ -1,6 +1,23 @@ -/* - * i2c.h +/** + * @file i2c.h + * @brief * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright 2020 NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #ifndef I2C_H_ diff --git a/source/board/microbitv2/i2c_commands.h b/source/board/microbitv2/i2c_commands.h index 2272d7e23..f799222df 100644 --- a/source/board/microbitv2/i2c_commands.h +++ b/source/board/microbitv2/i2c_commands.h @@ -1,6 +1,23 @@ /** - * @file i2c_commands.h + * @file i2c_commands.h * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright 2020 NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #ifndef I2C_COMMANDS_H diff --git a/source/board/microbitv2/led_error_app.h b/source/board/microbitv2/led_error_app.h index f927d978c..081c1aeac 100644 --- a/source/board/microbitv2/led_error_app.h +++ b/source/board/microbitv2/led_error_app.h @@ -1,3 +1,25 @@ +/** + * @file led_error_app.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright 2020 Micro:bit Educational Foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + // Program to display error code 0-999 on LEDs: face,E,digit,digit,digit unsigned int led_error_bin_len = 2016; diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index c74b72066..86081c516 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -4,6 +4,7 @@ * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * Copyright 2020 NXP * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -18,6 +19,7 @@ * See the License for the specific language governing permissions and * limitations under the License. */ + #include "fsl_device_registers.h" #include "IO_Config.h" #include "DAP.h" diff --git a/source/board/microbitv2/power.c b/source/board/microbitv2/power.c index 802502972..fd95a4480 100644 --- a/source/board/microbitv2/power.c +++ b/source/board/microbitv2/power.c @@ -1,7 +1,25 @@ /** - * @file power.c + * @file power.c * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright 2020 NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ + #include "fsl_smc.h" #include "fsl_rcm.h" #include "fsl_llwu.h" diff --git a/source/board/microbitv2/power.h b/source/board/microbitv2/power.h index 629924b70..43254b783 100644 --- a/source/board/microbitv2/power.h +++ b/source/board/microbitv2/power.h @@ -1,3 +1,25 @@ +/** + * @file power.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright 2020 NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + #ifndef POWER_H_ #define POWER_H_ diff --git a/source/board/microbitv2/pwr_mon.c b/source/board/microbitv2/pwr_mon.c index c83cec78c..6a0a2d56b 100644 --- a/source/board/microbitv2/pwr_mon.c +++ b/source/board/microbitv2/pwr_mon.c @@ -1,6 +1,23 @@ /** - * @file power_monitor.c + * @file pwr_mon.c * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright 2020 NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #include "pwr_mon.h" diff --git a/source/board/microbitv2/pwr_mon.h b/source/board/microbitv2/pwr_mon.h index d5524d6a8..cc9ac6871 100644 --- a/source/board/microbitv2/pwr_mon.h +++ b/source/board/microbitv2/pwr_mon.h @@ -1,6 +1,23 @@ /** - * @file power_monitor.h + * @file pwr_mon.h * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright 2020 NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #ifndef PWR_MON_H diff --git a/source/hic_hal/adc.h b/source/hic_hal/adc.h index 6045b1da6..e2bbcc618 100644 --- a/source/hic_hal/adc.h +++ b/source/hic_hal/adc.h @@ -1,6 +1,23 @@ /** - * @file adc.h + * @file adc.h * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright 2020 NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #ifndef ADC_H diff --git a/source/hic_hal/freescale/kl27z/adc.c b/source/hic_hal/freescale/kl27z/adc.c index 62c3aae2b..7c0fb8c38 100644 --- a/source/hic_hal/freescale/kl27z/adc.c +++ b/source/hic_hal/freescale/kl27z/adc.c @@ -1,6 +1,23 @@ /** - * @file adc.c + * @file adc.c * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright 2020 NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #include "adc.h" From 1c981f011113d4c7979b9c5e8da8097896b7e294 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 8 Jan 2021 20:13:41 -0600 Subject: [PATCH 261/617] Consistent use of static for function (cherry picked from commit fb4d5da87e367446077bc336251c2510d95182a9) --- source/board/microbitv2/pwr_mon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/board/microbitv2/pwr_mon.c b/source/board/microbitv2/pwr_mon.c index 6a0a2d56b..bf89089ba 100644 --- a/source/board/microbitv2/pwr_mon.c +++ b/source/board/microbitv2/pwr_mon.c @@ -35,7 +35,7 @@ #define ADC_MV_TO_ADC(x) ((x) * 0xFFF / 3300) // Convert mV to ADC value (12bit and 3.3V reference) #define BATT_MIN_VOLTAGE 1500 -void pwr_mon_bandgap_init(void); +static void pwr_mon_bandgap_init(void); static uint32_t pwr_mon_read_vbg(uint32_t channelGroup); static uint32_t pwr_mon_adc_to_mv(uint32_t raw_adc); From 412be24aa15a1b5a0c33747761e7f9c9f5ca49ee Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 13 Jan 2021 00:08:45 -0600 Subject: [PATCH 262/617] Make microbit bootloader optional for kl27z HIC (cherry picked from commit 1d7ad5dd3094cd607b4c663a87e8f85b7eb44d0a) Modifications: -Only define MICROBIT_LOCK_BOOTLOADER for kl27z_microbit_bl project -Keep only one common: section in kl27z_microbit_bl.yaml --- records/board/kl27z_microbit_bl.yaml | 2 ++ .../freescale/kl27z/armcc/startup_MKL27Z4.s | 19 +++++++++++++++++++ .../freescale/kl27z/gcc/startup_MKL27Z4.S | 11 +++++++++++ 3 files changed, 32 insertions(+) diff --git a/records/board/kl27z_microbit_bl.yaml b/records/board/kl27z_microbit_bl.yaml index 02a2ed9b3..da46b813a 100644 --- a/records/board/kl27z_microbit_bl.yaml +++ b/records/board/kl27z_microbit_bl.yaml @@ -1,4 +1,6 @@ common: + macros: + - MICROBIT_LOCK_BOOTLOADER sources: board: - source/board/kl27z_microbit_bl.c diff --git a/source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s b/source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s index 18074d8ec..ac06bcb11 100644 --- a/source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s +++ b/source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s @@ -167,6 +167,7 @@ __Vectors_Size EQU __Vectors_End - __Vectors ; Backdoor Comparison Key 5. <0x0-0xFF:2> ; Backdoor Comparison Key 6. <0x0-0xFF:2> ; Backdoor Comparison Key 7. <0x0-0xFF:2> +#if defined(MICROBIT_LOCK_BOOTLOADER) BackDoorK0 EQU 0x4D ; 'M' BackDoorK1 EQU 0x49 ; 'I' BackDoorK2 EQU 0x43 ; 'C' @@ -175,6 +176,16 @@ BackDoorK4 EQU 0x4F ; 'O' BackDoorK5 EQU 0x42 ; 'B' BackDoorK6 EQU 0x49 ; 'I' BackDoorK7 EQU 0x54 ; 'T' +#else +BackDoorK0 EQU 0xFF +BackDoorK1 EQU 0xFF +BackDoorK2 EQU 0xFF +BackDoorK3 EQU 0xFF +BackDoorK4 EQU 0xFF +BackDoorK5 EQU 0xFF +BackDoorK6 EQU 0xFF +BackDoorK7 EQU 0xFF +#endif ; ; Program flash protection bytes (FPROT) ; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. @@ -190,7 +201,11 @@ BackDoorK7 EQU 0x54 ; 'T' ; FPROT3.5 ; FPROT3.6 ; FPROT3.7 +#if defined(MICROBIT_LOCK_BOOTLOADER) nFPROT3 EQU 0x0F ; Enable protection of the first 32 kB of flash +#else +nFPROT3 EQU 0x00 +#endif FPROT3 EQU nFPROT3:EOR:0xFF ; ; FPROT2 @@ -281,7 +296,11 @@ FOPT EQU 0x39 ; * <2=> Backdoor key access enabled ; <3=> Backdoor key access disabled ; Backdoor Key Security Enable +#if defined(MICROBIT_LOCK_BOOTLOADER) FSEC EQU 0xBE +#else +FSEC EQU 0xFE +#endif ; ; diff --git a/source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S b/source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S index b22302ae6..1c670491e 100644 --- a/source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S +++ b/source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S @@ -76,12 +76,23 @@ __isr_vector: .size __isr_vector, . - __isr_vector +#if defined(DAPLINK_BL) + /* TODO: Bootloader Configuration Area (BCA) used by Kinetis ROM Bootloader +#endif + /* Flash Configuration */ .section .FlashConfig, "a" +#if defined(MICROBIT_LOCK_BOOTLOADER) + .long 0x5243494D + .long 0x5449424F + .long 0xFFFFFFF0 + .long 0xFFFF39FE +#else .long 0xFFFFFFFF .long 0xFFFFFFFF .long 0xFFFFFFFF .long 0xFFFF3FFE +#endif .text .thumb From c49bf3329dda68ef9fe814dea8d0fa2879882e3d Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Thu, 21 Jan 2021 19:35:01 -0600 Subject: [PATCH 263/617] Change storage API to avoid armgcc warning --- source/board/microbitv2/microbitv2.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 86081c516..8d4c5d2e3 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -812,14 +812,17 @@ static uint32_t erase_storage_sector(uint32_t adr) return status; } -static uint32_t program_storage_page(uint32_t adr, uint32_t sz, uint32_t *buf) +static uint32_t program_storage_page(uint32_t adr, uint32_t sz, uint8_t *buf) { - int status = FLASH_Program(&g_flash, adr, buf, sz); + /* Verify data is word aligned */ + util_assert(!((uint32_t)buf & 0x3)); + + int status = FLASH_Program(&g_flash, adr, (uint32_t *) buf, sz); if (status == kStatus_Success) { // Must use kFlashMargin_User, or kFlashMargin_Factory for verify program status = FLASH_VerifyProgram(&g_flash, adr, sz, - buf, kFLASH_marginValueUser, + (uint32_t *) buf, kFLASH_marginValueUser, NULL, NULL); } return status; @@ -844,7 +847,7 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { /* Validate length field matches with I2C Write data */ if (size == length + 8) { /* Address range and alignment validation done inside program_storage_page() */ - status = program_storage_page(address, length, (uint32_t *) data); + status = program_storage_page(address, length, (uint8_t *) data); if (0 != status) { pI2cCommand->cmdId = gFlashError_c; @@ -989,7 +992,7 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { pI2cCommand->cmdId = gFlashError_c; } else { - status = program_storage_page(FLASH_CONFIG_ADDRESS, sizeof(flashConfig_t), (uint32_t *) &gflashConfig); + status = program_storage_page(FLASH_CONFIG_ADDRESS, sizeof(flashConfig_t), (uint8_t *) &gflashConfig); } } i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); From ac1cfb433c88bef1e13a5ee9aaaf8900c6285a26 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Thu, 12 Aug 2021 09:59:41 -0500 Subject: [PATCH 264/617] remove arm copyright from newly added files update formatting made microbit specific changes to be board configurable via yaml files --- records/board/microbitv2.yaml | 3 + source/board/kl27z_microbit_bl.c | 1 - source/board/microbitv2/flexio_pwm.c | 1 - source/board/microbitv2/flexio_pwm.h | 1 - source/board/microbitv2/i2c.c | 239 ------ source/board/microbitv2/i2c.h | 53 -- source/board/microbitv2/i2c_commands.c | 683 ++++++++++++++++++ source/board/microbitv2/i2c_commands.h | 27 +- source/board/microbitv2/led_error_app.c | 198 +++++ source/board/microbitv2/led_error_app.h | 188 +---- source/board/microbitv2/microbitv2.c | 498 +------------ source/board/microbitv2/microbitv2.h | 63 ++ source/board/microbitv2/power.c | 3 +- source/board/microbitv2/power.h | 1 - source/board/microbitv2/pwr_mon.c | 1 - source/board/microbitv2/pwr_mon.h | 1 - source/daplink/drag-n-drop/vfs_user.c | 9 +- source/daplink/error.h | 1 + source/daplink/interface/main_interface.c | 5 +- source/hic_hal/adc.h | 1 - source/hic_hal/atmel/sam3u2c/usb_config.c | 4 + source/hic_hal/freescale/k20dx/usb_config.c | 4 + source/hic_hal/freescale/k26f/usb_config.c | 4 + source/hic_hal/freescale/kl26z/usb_config.c | 4 + source/hic_hal/freescale/kl27z/DAP_config.h | 4 +- source/hic_hal/freescale/kl27z/adc.c | 1 - source/hic_hal/freescale/kl27z/usb_config.c | 7 +- source/hic_hal/maxim/max32620/usb_config.c | 4 + source/hic_hal/maxim/max32625/usb_config.c | 4 + source/hic_hal/nuvoton/m48ssidae/usb_config.c | 4 + source/hic_hal/nxp/lpc11u35/usb_config.c | 4 + source/hic_hal/nxp/lpc4322/usb_config.c | 4 + source/hic_hal/stm32/stm32f103xb/usb_config.c | 4 + 33 files changed, 1064 insertions(+), 965 deletions(-) delete mode 100644 source/board/microbitv2/i2c.c delete mode 100644 source/board/microbitv2/i2c.h create mode 100644 source/board/microbitv2/i2c_commands.c create mode 100644 source/board/microbitv2/led_error_app.c create mode 100644 source/board/microbitv2/microbitv2.h diff --git a/records/board/microbitv2.yaml b/records/board/microbitv2.yaml index 7158e7f47..1d67d7b59 100644 --- a/records/board/microbitv2.yaml +++ b/records/board/microbitv2.yaml @@ -6,6 +6,9 @@ common: - USB_PROD_STR="BBC micro:bit CMSIS-DAP" - IO_CONFIG_OVERRIDE - DELAY_FAST_CYCLES=2U + - DAP_DEFAULT_SWJ_CLOCK=8000000 + - BOARD_USB_BMAXPOWER=0x96 + - BOARD_EXTRA_BUFFER=100 includes: - source/board/microbitv2 sources: diff --git a/source/board/kl27z_microbit_bl.c b/source/board/kl27z_microbit_bl.c index 7d0c668ff..0dc3c0bb9 100644 --- a/source/board/kl27z_microbit_bl.c +++ b/source/board/kl27z_microbit_bl.c @@ -3,7 +3,6 @@ * @brief board ID and meta-data for the hardware interface circuit (HIC) based on the NXP KL27Z * * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved * Copyright 2020 NXP * SPDX-License-Identifier: Apache-2.0 * diff --git a/source/board/microbitv2/flexio_pwm.c b/source/board/microbitv2/flexio_pwm.c index 496c027b6..b0450d359 100644 --- a/source/board/microbitv2/flexio_pwm.c +++ b/source/board/microbitv2/flexio_pwm.c @@ -3,7 +3,6 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved * Copyright 2020 NXP * SPDX-License-Identifier: Apache-2.0 * diff --git a/source/board/microbitv2/flexio_pwm.h b/source/board/microbitv2/flexio_pwm.h index 2846a8ae0..d4cd36708 100644 --- a/source/board/microbitv2/flexio_pwm.h +++ b/source/board/microbitv2/flexio_pwm.h @@ -3,7 +3,6 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved * Copyright 2020 NXP * SPDX-License-Identifier: Apache-2.0 * diff --git a/source/board/microbitv2/i2c.c b/source/board/microbitv2/i2c.c deleted file mode 100644 index bf3efe8d7..000000000 --- a/source/board/microbitv2/i2c.c +++ /dev/null @@ -1,239 +0,0 @@ -/** - * @file i2c.c - * @brief - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved - * Copyright 2020 NXP - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "i2c.h" -#include "fsl_i2c.h" -#include "fsl_clock.h" -#include "fsl_port.h" -#include "settings.h" // for config_get_overflow_detect -#include "main_interface.h" - -/* I2C source clock */ -#define I2C_SLAVE_BASEADDR I2C1 -#define I2C_SLAVE_CLK_SRC I2C1_CLK_SRC -#define I2C_SLAVE_CLK_FREQ CLOCK_GetFreq(I2C1_CLK_SRC) - -#define I2C_SLAVE_LOWER_ADDR_7BIT (0x70U) -#define I2C_SLAVE_UPPER_ADDR_7BIT (0x72U) -#define I2C_DATA_LENGTH (1024U + 8U) - - -static uint8_t g_slave_TX_buff[I2C_DATA_LENGTH]; -static uint8_t g_slave_RX_buff[I2C_DATA_LENGTH]; -i2c_slave_handle_t g_s_handle; -static volatile bool g_SlaveCompletionFlag = false; -static volatile bool g_SlaveRxFlag = false; -static uint8_t address_match = 0; -static uint32_t transferredCount = 0; - -static i2cWriteCallback_t pfWriteCommsCallback = NULL; -static i2cReadCallback_t pfReadCommsCallback = NULL; -static i2cWriteCallback_t pfWriteFlashCallback = NULL; -static i2cReadCallback_t pfReadFlashCallback = NULL; - -extern uint8_t i2c_wake_timeout; -extern bool i2c_allow_sleep; - -static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData) { - switch (xfer->event) - { - /* Address match event */ - case kI2C_SlaveAddressMatchEvent: - xfer->data = NULL; - xfer->dataSize = 0; - // fsl_i2c.c IRQ updated in fsl_i2c_mod.c to include I2C D register - address_match = *(uint8_t*)userData >> 1; - i2c_wake_timeout = 3; // 3 * 30ms tick = 90ms timeout - break; - /* Transmit request */ - case kI2C_SlaveTransmitEvent: - /* Update information for transmit process */ - xfer->data = g_slave_TX_buff; - xfer->dataSize = I2C_DATA_LENGTH; - g_SlaveRxFlag = false; - break; - - /* Receive request */ - case kI2C_SlaveReceiveEvent: - /* Update information for received process */ - // Hack: Default driver can't differentiate between RX or TX on - // completion event, so we set a flag here. Can't process more - // than I2C_DATA_LENGTH bytes on RX - memset(&g_slave_RX_buff, 0, sizeof(g_slave_RX_buff)); - xfer->data = g_slave_RX_buff; - xfer->dataSize = I2C_DATA_LENGTH; - g_SlaveRxFlag = true; - break; - - /* Transfer done */ - case kI2C_SlaveCompletionEvent: - g_SlaveCompletionFlag = true; - xfer->data = NULL; - xfer->dataSize = 0; - transferredCount = xfer->transferredCount; - - // Default driver couldn't differentiate between RX or TX completion - // Check flag set in kI2C_SlaveReceiveEvent - - // Ignore NOP cmd in I2C Write - if (!(g_SlaveRxFlag && g_slave_RX_buff[0] == 0x00)) { - main_board_event(); - } - - i2c_allow_sleep = false; - break; - - default: - g_SlaveCompletionFlag = false; - break; - } -} -// Hook function executed in the main task -void board_custom_event() { - - if (g_SlaveRxFlag) { - if (pfWriteCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { - pfWriteCommsCallback(&g_slave_RX_buff[0], transferredCount); - } - if (pfWriteFlashCallback && address_match == I2C_SLAVE_FLASH) { - pfWriteFlashCallback(&g_slave_RX_buff[0], transferredCount); - } - } else { - if (pfReadCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { - pfReadCommsCallback(&g_slave_TX_buff[0], transferredCount); - } - if (pfReadFlashCallback && address_match == I2C_SLAVE_FLASH) { - pfReadFlashCallback(&g_slave_TX_buff[0], transferredCount); - } - } - i2c_allow_sleep = true; -} - -static void i2c_init_pins(void) { - /* Port C Clock Gate Control: Clock enabled */ - CLOCK_EnableClock(kCLOCK_PortC); - - /* PORTC1 is configured as I2C1_SCL */ - PORT_SetPinMux(PORTC, 1U, kPORT_MuxAlt2); - - /* PORTC2 is configured as I2C1_SDA */ - PORT_SetPinMux(PORTC, 2U, kPORT_MuxAlt2); -} - -static int32_t i2c_start_transfer(void) { - memset(&g_s_handle, 0, sizeof(g_s_handle)); - - I2C_SlaveTransferCreateHandle(I2C_SLAVE_BASEADDR, &g_s_handle, - i2c_slave_callback, &address_match); - - /* Set up slave transfer. */ - I2C_SlaveTransferNonBlocking(I2C_SLAVE_BASEADDR, &g_s_handle, - kI2C_SlaveCompletionEvent | kI2C_SlaveAddressMatchEvent); - - // i2c handle will be busy until an address match - g_s_handle.isBusy = false; - - return 1; -} - -int32_t i2c_initialize(void) { - i2c_slave_config_t slaveConfig; - - i2c_init_pins(); - - I2C_SlaveGetDefaultConfig(&slaveConfig); - - slaveConfig.addressingMode = kI2C_RangeMatch; - slaveConfig.slaveAddress = I2C_SLAVE_LOWER_ADDR_7BIT; - slaveConfig.upperAddress = I2C_SLAVE_UPPER_ADDR_7BIT; - slaveConfig.enableWakeUp = true; - - I2C_SlaveInit(I2C_SLAVE_BASEADDR, &slaveConfig, I2C_SLAVE_CLK_FREQ); - - NVIC_SetPriority(I2C1_IRQn, 0x00); /* set highest priority */ - - i2c_start_transfer(); - - return 1; -} - -int32_t i2c_deinitialize(void) { - I2C_SlaveDeinit(I2C_SLAVE_BASEADDR); - return 1; -} - -status_t i2c_RegisterWriteCallback(i2cWriteCallback_t writeCallback, uint8_t slaveAddress) -{ - status_t status = kStatus_Success; - - switch (slaveAddress){ - case I2C_SLAVE_NRF_KL_COMMS: - pfWriteCommsCallback = writeCallback; - break; - case I2C_SLAVE_HID: - break; - case I2C_SLAVE_FLASH: - pfWriteFlashCallback = writeCallback; - break; - default: - status = kStatus_Fail; - break; - } - - return status; -} - -status_t i2c_RegisterReadCallback(i2cReadCallback_t readCallback, uint8_t slaveAddress) -{ - status_t status = kStatus_Success; - - switch (slaveAddress) { - case I2C_SLAVE_NRF_KL_COMMS: - pfReadCommsCallback = readCallback; - break; - case I2C_SLAVE_HID: - break; - case I2C_SLAVE_FLASH: - pfReadFlashCallback = readCallback; - break; - default: - status = kStatus_Fail; - break; - } - - return status; -} - -void i2c_clearBuffer (void) { - memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); -} - -void i2c_fillBuffer (uint8_t* data, uint32_t position, uint32_t size) { - if ((position + size) > I2C_DATA_LENGTH) { - return; - } - - for (uint32_t i = 0; i < size; i++) { - g_slave_TX_buff[position + i] = data[i]; - } -} - diff --git a/source/board/microbitv2/i2c.h b/source/board/microbitv2/i2c.h deleted file mode 100644 index 8de362943..000000000 --- a/source/board/microbitv2/i2c.h +++ /dev/null @@ -1,53 +0,0 @@ -/** - * @file i2c.h - * @brief - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved - * Copyright 2020 NXP - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef I2C_H_ -#define I2C_H_ - -#include "fsl_common.h" - -#define I2C_SLAVE_NRF_KL_COMMS (0x70U) -#define I2C_SLAVE_HID (0x71U) -#define I2C_SLAVE_FLASH (0x72U) - -/*! i2c Write Callback prototype */ -typedef void (*i2cWriteCallback_t) -( - uint8_t* pData, - uint8_t size -); - -/*! i2c Read Callback prototype */ -typedef void (*i2cReadCallback_t) -( - uint8_t* pData, - uint8_t size -); - -int32_t i2c_initialize(void); -int32_t i2c_deinitialize(void); -status_t i2c_RegisterWriteCallback(i2cWriteCallback_t writeCallback, uint8_t slaveAddress); -status_t i2c_RegisterReadCallback(i2cReadCallback_t readCallback, uint8_t slaveAddress); -void i2c_clearBuffer(void); -void i2c_fillBuffer(uint8_t* data, uint32_t position, uint32_t size); - -#endif /* I2C_H_ */ diff --git a/source/board/microbitv2/i2c_commands.c b/source/board/microbitv2/i2c_commands.c new file mode 100644 index 000000000..f3e42b159 --- /dev/null +++ b/source/board/microbitv2/i2c_commands.c @@ -0,0 +1,683 @@ +/** + * @file i2c_commands.c + * @brief Microbit appliation layer for I2C operations + * + * DAPLink Interface Firmware + * Copyright 2020 NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "i2c_commands.h" +#include "fsl_i2c.h" +#include "fsl_clock.h" +#include "fsl_port.h" +#include "fsl_flash.h" +#include "settings.h" // for config_get_overflow_detect +#include "main_interface.h" +#include "pwr_mon.h" +#include "power.h" +#include "microbitv2.h" + +/* I2C source clock */ +#define I2C_SLAVE_BASEADDR I2C1 +#define I2C_SLAVE_CLK_SRC I2C1_CLK_SRC +#define I2C_SLAVE_CLK_FREQ CLOCK_GetFreq(I2C1_CLK_SRC) + +#define I2C_SLAVE_LOWER_ADDR_7BIT (0x70U) +#define I2C_SLAVE_UPPER_ADDR_7BIT (0x72U) +#define I2C_DATA_LENGTH (1024U + 8U) + + +static uint8_t g_slave_TX_buff[I2C_DATA_LENGTH]; +static uint8_t g_slave_RX_buff[I2C_DATA_LENGTH]; +i2c_slave_handle_t g_s_handle; +static volatile bool g_SlaveCompletionFlag = false; +static volatile bool g_SlaveRxFlag = false; +static uint8_t address_match = 0; +static uint32_t transferredCount = 0; + +static i2cWriteCallback_t pfWriteCommsCallback = NULL; +static i2cReadCallback_t pfReadCommsCallback = NULL; +static i2cWriteCallback_t pfWriteFlashCallback = NULL; +static i2cReadCallback_t pfReadFlashCallback = NULL; + +extern uint8_t i2c_wake_timeout; +extern bool i2c_allow_sleep; +extern uint16_t board_id_hex; +extern power_source_t power_source; +extern main_usb_connect_t usb_state; +extern app_power_mode_t interface_power_mode; +extern bool power_led_sleep_state_on; +extern bool automatic_sleep_on; +extern main_shutdown_state_t main_shutdown_state; +extern bool do_remount; +extern flashConfig_t gflashConfig; +extern flash_config_t g_flash; + + +static void i2c_write_comms_callback(uint8_t* pData, uint8_t size); +static void i2c_read_comms_callback(uint8_t* pData, uint8_t size); +static void i2c_write_flash_callback(uint8_t* pData, uint8_t size); +static void i2c_read_flash_callback(uint8_t* pData, uint8_t size); + +static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData) { + switch (xfer->event) + { + /* Address match event */ + case kI2C_SlaveAddressMatchEvent: + xfer->data = NULL; + xfer->dataSize = 0; + // fsl_i2c.c IRQ updated in fsl_i2c_mod.c to include I2C D register + address_match = *(uint8_t*)userData >> 1; + i2c_wake_timeout = 3; // 3 * 30ms tick = 90ms timeout + break; + /* Transmit request */ + case kI2C_SlaveTransmitEvent: + /* Update information for transmit process */ + xfer->data = g_slave_TX_buff; + xfer->dataSize = I2C_DATA_LENGTH; + g_SlaveRxFlag = false; + break; + + /* Receive request */ + case kI2C_SlaveReceiveEvent: + /* Update information for received process */ + // Hack: Default driver can't differentiate between RX or TX on + // completion event, so we set a flag here. Can't process more + // than I2C_DATA_LENGTH bytes on RX + memset(&g_slave_RX_buff, 0, sizeof(g_slave_RX_buff)); + xfer->data = g_slave_RX_buff; + xfer->dataSize = I2C_DATA_LENGTH; + g_SlaveRxFlag = true; + break; + + /* Transfer done */ + case kI2C_SlaveCompletionEvent: + g_SlaveCompletionFlag = true; + xfer->data = NULL; + xfer->dataSize = 0; + transferredCount = xfer->transferredCount; + + // Default driver couldn't differentiate between RX or TX completion + // Check flag set in kI2C_SlaveReceiveEvent + + // Ignore NOP cmd in I2C Write + if (!(g_SlaveRxFlag && g_slave_RX_buff[0] == 0x00)) { + main_board_event(); + } + + i2c_allow_sleep = false; + break; + + default: + g_SlaveCompletionFlag = false; + break; + } +} +// Hook function executed in the main task +void board_custom_event() { + + if (g_SlaveRxFlag) { + if (pfWriteCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { + pfWriteCommsCallback(&g_slave_RX_buff[0], transferredCount); + } + if (pfWriteFlashCallback && address_match == I2C_SLAVE_FLASH) { + pfWriteFlashCallback(&g_slave_RX_buff[0], transferredCount); + } + } else { + if (pfReadCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { + pfReadCommsCallback(&g_slave_TX_buff[0], transferredCount); + } + if (pfReadFlashCallback && address_match == I2C_SLAVE_FLASH) { + pfReadFlashCallback(&g_slave_TX_buff[0], transferredCount); + } + } + i2c_allow_sleep = true; +} + +static void i2c_init_pins(void) { + /* Port C Clock Gate Control: Clock enabled */ + CLOCK_EnableClock(kCLOCK_PortC); + + /* PORTC1 is configured as I2C1_SCL */ + PORT_SetPinMux(PORTC, 1U, kPORT_MuxAlt2); + + /* PORTC2 is configured as I2C1_SDA */ + PORT_SetPinMux(PORTC, 2U, kPORT_MuxAlt2); +} + +static int32_t i2c_start_transfer(void) { + memset(&g_s_handle, 0, sizeof(g_s_handle)); + + I2C_SlaveTransferCreateHandle(I2C_SLAVE_BASEADDR, &g_s_handle, + i2c_slave_callback, &address_match); + + /* Set up slave transfer. */ + I2C_SlaveTransferNonBlocking(I2C_SLAVE_BASEADDR, &g_s_handle, + kI2C_SlaveCompletionEvent | kI2C_SlaveAddressMatchEvent); + + // i2c handle will be busy until an address match + g_s_handle.isBusy = false; + + return 1; +} + +void i2c_initialize(void) { + i2c_slave_config_t slaveConfig; + + i2c_init_pins(); + + I2C_SlaveGetDefaultConfig(&slaveConfig); + + slaveConfig.addressingMode = kI2C_RangeMatch; + slaveConfig.slaveAddress = I2C_SLAVE_LOWER_ADDR_7BIT; + slaveConfig.upperAddress = I2C_SLAVE_UPPER_ADDR_7BIT; + slaveConfig.enableWakeUp = true; + + I2C_SlaveInit(I2C_SLAVE_BASEADDR, &slaveConfig, I2C_SLAVE_CLK_FREQ); + + NVIC_SetPriority(I2C1_IRQn, 0x00); /* set highest priority */ + + i2c_start_transfer(); + + i2c_registerWriteCallback(i2c_write_comms_callback, I2C_SLAVE_NRF_KL_COMMS); + i2c_registerReadCallback(i2c_read_comms_callback, I2C_SLAVE_NRF_KL_COMMS); + i2c_registerWriteCallback(i2c_write_flash_callback, I2C_SLAVE_FLASH); + i2c_registerReadCallback(i2c_read_flash_callback, I2C_SLAVE_FLASH); + + return; +} + +void i2c_deinitialize(void) { + I2C_SlaveDeinit(I2C_SLAVE_BASEADDR); + return ; +} + +status_t i2c_registerWriteCallback(i2cWriteCallback_t writeCallback, uint8_t slaveAddress) +{ + status_t status = kStatus_Success; + + switch (slaveAddress){ + case I2C_SLAVE_NRF_KL_COMMS: + pfWriteCommsCallback = writeCallback; + break; + case I2C_SLAVE_HID: + break; + case I2C_SLAVE_FLASH: + pfWriteFlashCallback = writeCallback; + break; + default: + status = kStatus_Fail; + break; + } + + return status; +} + +status_t i2c_registerReadCallback(i2cReadCallback_t readCallback, uint8_t slaveAddress) +{ + status_t status = kStatus_Success; + + switch (slaveAddress) { + case I2C_SLAVE_NRF_KL_COMMS: + pfReadCommsCallback = readCallback; + break; + case I2C_SLAVE_HID: + break; + case I2C_SLAVE_FLASH: + pfReadFlashCallback = readCallback; + break; + default: + status = kStatus_Fail; + break; + } + + return status; +} + +void i2c_clearBuffer (void) { + memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); +} + +void i2c_fillBuffer (uint8_t* data, uint32_t position, uint32_t size) { + if ((position + size) > I2C_DATA_LENGTH) { + return; + } + + for (uint32_t i = 0; i < size; i++) { + g_slave_TX_buff[position + i] = data[i]; + } +} + +static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { + i2cCommand_t* pI2cCommand = (i2cCommand_t*) pData; + i2cCommand_t i2cResponse = {0}; + bool assert_interrupt = true; + + switch (pI2cCommand->cmdId) { + case gReadRequest_c: + i2cResponse.cmdId = gReadResponse_c; + i2cResponse.cmdData.readRspCmd.propertyId = pI2cCommand->cmdData.readReqCmd.propertyId; + switch (pI2cCommand->cmdData.readReqCmd.propertyId) { + case gDAPLinkBoardVersion_c: + i2cResponse.cmdData.readRspCmd.dataSize = sizeof(board_id_hex); + memcpy(&i2cResponse.cmdData.readRspCmd.data, &board_id_hex, sizeof(board_id_hex)); + break; + case gI2CProtocolVersion_c: { + uint16_t i2c_version = 1; + i2cResponse.cmdData.readRspCmd.dataSize = sizeof(i2c_version); + memcpy(&i2cResponse.cmdData.readRspCmd.data, &i2c_version, sizeof(i2c_version)); + } + break; + case gDAPLinkVersion_c: { + uint16_t daplink_version = DAPLINK_VERSION; + i2cResponse.cmdData.readRspCmd.dataSize = sizeof(daplink_version); + memcpy(&i2cResponse.cmdData.readRspCmd.data, &daplink_version, sizeof(daplink_version)); + } + break; + case gPowerState_c: + power_source = pwr_mon_get_power_source(); + i2cResponse.cmdData.readRspCmd.dataSize = sizeof(power_source); + memcpy(&i2cResponse.cmdData.readRspCmd.data, &power_source, sizeof(power_source)); + break; + case gPowerConsumption_c: { + uint32_t vin_voltage_uv = pwr_mon_get_vin_mv() * 1000; + uint32_t vbat_voltage_uv = pwr_mon_get_vbat_mv() * 1000; + i2cResponse.cmdData.readRspCmd.dataSize = sizeof(vin_voltage_uv) + sizeof(vbat_voltage_uv); + memcpy(&i2cResponse.cmdData.readRspCmd.data[0], &vbat_voltage_uv, sizeof(vbat_voltage_uv)); + memcpy(&i2cResponse.cmdData.readRspCmd.data[sizeof(vbat_voltage_uv)], &vin_voltage_uv, sizeof(vin_voltage_uv)); + } + break; + case gUSBEnumerationState_c: + i2cResponse.cmdData.readRspCmd.dataSize = sizeof(usb_state); + memcpy(&i2cResponse.cmdData.readRspCmd.data, &usb_state, sizeof(usb_state)); + break; + case gPowerMode_c: + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorReadDisallowed_c; + break; + default: + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorUnknownProperty_c; + break; + } + break; + case gReadResponse_c: + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorCommandDisallowed_c; + break; + case gWriteRequest_c: + switch (pI2cCommand->cmdData.writeReqCmd.propertyId) { + case gDAPLinkBoardVersion_c: + case gI2CProtocolVersion_c: + case gDAPLinkVersion_c: + case gPowerState_c: + case gPowerConsumption_c: + case gUSBEnumerationState_c: + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWriteDisallowed_c; + break; + case gPowerMode_c: + if (pI2cCommand->cmdData.writeReqCmd.dataSize == 1) { + if (pI2cCommand->cmdData.writeReqCmd.data[0] == kAPP_PowerModeVlls0) { + interface_power_mode = kAPP_PowerModeVlls0; + i2cResponse.cmdId = gWriteResponse_c; + i2cResponse.cmdData.writeRspCmd.propertyId = pI2cCommand->cmdData.writeReqCmd.propertyId; + } else { + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWriteFail_c; + } + } else { + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWrongPropertySize_c; + } + break; + case gPowerLedSleepState_c: + if (pI2cCommand->cmdData.writeReqCmd.dataSize == 1) { + if (pI2cCommand->cmdData.writeReqCmd.data[0] != 0) { + power_led_sleep_state_on = true; + } + else { + power_led_sleep_state_on = false; + } + i2cResponse.cmdId = gWriteResponse_c; + i2cResponse.cmdData.writeRspCmd.propertyId = pI2cCommand->cmdData.writeReqCmd.propertyId; + } else { + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWrongPropertySize_c; + } + break; + case gAutomaticSleep_c: + if (pI2cCommand->cmdData.writeReqCmd.dataSize == 1) { + if (pI2cCommand->cmdData.writeReqCmd.data[0] != 0) { + automatic_sleep_on = true; + } + else { + automatic_sleep_on = false; + } + i2cResponse.cmdId = gWriteResponse_c; + i2cResponse.cmdData.writeRspCmd.propertyId = pI2cCommand->cmdData.writeReqCmd.propertyId; + } else { + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWrongPropertySize_c; + } + break; + default: + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorUnknownProperty_c; + break; + } + break; + case gWriteResponse_c: + break; + case gErrorResponse_c: + break; + case gNopCmd_c: + assert_interrupt = false; + break; + default: + i2cResponse.cmdId = gErrorResponse_c; + i2cResponse.cmdData.errorRspCmd.errorCode = gErrorUnknownCommand_c; + break; + } + + if (assert_interrupt) { + i2c_fillBuffer((uint8_t*) &i2cResponse, 0, sizeof(i2cResponse)); + // Response ready, assert COMBINED_SENSOR_INT + PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_MuxAsGpio); + } +} + +static void i2c_read_comms_callback(uint8_t* pData, uint8_t size) { + i2cCommand_t* pI2cCommand = (i2cCommand_t*) pData; + + switch (pI2cCommand->cmdId) { + case gWriteResponse_c: + switch (pI2cCommand->cmdData.writeRspCmd.propertyId) { + case gPowerMode_c: + main_shutdown_state = MAIN_SHUTDOWN_REQUESTED; + break; + } + break; + } + + i2c_clearBuffer(); + + // Release COMBINED_SENSOR_INT + PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); +} + +static bool file_extension_allowed(const vfs_filename_t filename) +{ + const char *valid_extensions[] = { + "BIN", + "TXT", + "CSV", + "HTM", + "WAV", + }; + uint32_t i; + + // Check for invalid starting characters + for (i = 0; i < (sizeof((valid_extensions))/sizeof((valid_extensions)[0])); i++) { + if (0 == memcmp(&filename[8], valid_extensions[i], 3)) { + return true; + } + } + + // Some checks failed so file extension is invalid + return false; +} + +static uint32_t erase_storage_sector(uint32_t adr) +{ + int status = FLASH_Erase(&g_flash, adr, g_flash.PFlashSectorSize, kFLASH_apiEraseKey); + if (status == kStatus_Success) + { + status = FLASH_VerifyErase(&g_flash, adr, g_flash.PFlashSectorSize, kFLASH_marginValueNormal); + } + return status; +} + +static uint32_t program_storage_page(uint32_t adr, uint32_t sz, uint8_t *buf) +{ + /* Verify data is word aligned */ + util_assert(!((uint32_t)buf & 0x3)); + + int status = FLASH_Program(&g_flash, adr, (uint32_t *) buf, sz); + if (status == kStatus_Success) + { + // Must use kFlashMargin_User, or kFlashMargin_Factory for verify program + status = FLASH_VerifyProgram(&g_flash, adr, sz, + (uint32_t *) buf, kFLASH_marginValueUser, + NULL, NULL); + } + return status; +} + +static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { + i2cFlashCmd_t* pI2cCommand = (i2cFlashCmd_t*) pData; + + uint32_t status = 0; + + uint32_t storage_address = pI2cCommand->cmdData.write.addr2 << 16 | + pI2cCommand->cmdData.write.addr1 << 8 | + pI2cCommand->cmdData.write.addr0 << 0; + uint32_t address = storage_address + FLASH_STORAGE_ADDRESS; + uint32_t length = __REV(pI2cCommand->cmdData.write.length); + uint32_t data = (uint32_t) pI2cCommand->cmdData.write.data; + + i2c_clearBuffer(); + + switch (pI2cCommand->cmdId) { + case gFlashDataWrite_c: + /* Validate length field matches with I2C Write data */ + if (size == length + 8) { + /* Address range and alignment validation done inside program_storage_page() */ + status = program_storage_page(address, length, (uint8_t *) data); + + if (0 != status) { + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } + else { + /* Fill TX Buffer with received command args */ + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, sizeof(i2cFlashCmd_t) - 1024); + /* Fill TX Buffer with Flash Data Written */ + i2c_fillBuffer((uint8_t*) address, sizeof(i2cFlashCmd_t) - 1024, length); + } + } else { + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } + break; + case gFlashDataRead_c: { + /* Do address range validation */ + if (address + length > (FLASH_CONFIG_ADDRESS + FLASH_INTERFACE_SIZE)) { + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } else { + /* Fill TX Buffer with received command args */ + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, sizeof(i2cFlashCmd_t) - 1024); + /* Fill TX Buffer with Flash Data Read */ + i2c_fillBuffer((uint8_t*) address, sizeof(i2cFlashCmd_t) - 1024, length); + } + } + break; + case gFlashDataErase_c: { + uint32_t address = pI2cCommand->cmdData.erase.sAddr2 << 16 | + pI2cCommand->cmdData.erase.sAddr1 << 8 | + pI2cCommand->cmdData.erase.sAddr0 << 0; + uint32_t start_addr = address + FLASH_STORAGE_ADDRESS; + + address = pI2cCommand->cmdData.erase.eAddr2 << 16 | + pI2cCommand->cmdData.erase.eAddr1 << 8 | + pI2cCommand->cmdData.erase.eAddr0 << 0; + uint32_t end_addr = address + FLASH_STORAGE_ADDRESS; + + /* Do address range validation */ + if (start_addr % DAPLINK_SECTOR_SIZE == 0 && + end_addr % DAPLINK_SECTOR_SIZE == 0 && + start_addr <= end_addr && + start_addr < (FLASH_CONFIG_ADDRESS + FLASH_INTERFACE_SIZE) && + end_addr < (FLASH_CONFIG_ADDRESS + FLASH_INTERFACE_SIZE)) { + for (uint32_t addr = start_addr; addr <= end_addr && status == 0; addr += DAPLINK_SECTOR_SIZE) { + status = erase_storage_sector(addr); + } + + if (status != 0) { + pI2cCommand->cmdId = gFlashError_c; + } + } else { + pI2cCommand->cmdId = gFlashError_c; + } + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + + } + break; + case gFlashCfgFileName_c: + if (size == 1) { + /* If size is 1 (only cmd id), this means it's a read */ + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBuffer((uint8_t*) &gflashConfig.fileName, 1, sizeof(gflashConfig.fileName)); + } else if (size == 12) { + /* If size is 12 (cmd id + 11B data), this means it's a write */ + /* Validate 8.3 filename */ + if (filename_valid((char *) pI2cCommand->cmdData.data)) { + // Check allowed extensions (.bin, .txt, .csv, .htm, .wav) + if (file_extension_allowed((char *) pI2cCommand->cmdData.data)) { + memcpy(gflashConfig.fileName, pI2cCommand->cmdData.data, 11); + } + // If disallowed extension is requested, .bin will be used + else { + memcpy(gflashConfig.fileName, pI2cCommand->cmdData.data, 8); + memcpy(&gflashConfig.fileName[8], "BIN", 3); + } + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBuffer((uint8_t*) &gflashConfig.fileName, 1, sizeof(gflashConfig.fileName)); + } + else { + // Send error if invalid filename + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } + } else { + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } + break; + case gFlashCfgFileSize_c: + if (size == 1) { + /* If size is 1 (only cmd id), this means it's a read */ + uint32_t tempFileSize = __REV(gflashConfig.fileSize); + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBuffer((uint8_t*) &tempFileSize, 1, sizeof(gflashConfig.fileSize)); + } else if (size == 5) { + /* If size is 5 (cmd id + 4B data), this means it's a write */ + uint32_t tempFileSize = pI2cCommand->cmdData.data[0] << 24 | + pI2cCommand->cmdData.data[1] << 16 | + pI2cCommand->cmdData.data[2] << 8 | + pI2cCommand->cmdData.data[3] << 0; + + /* Validate file size */ + if (tempFileSize <= (FLASH_INTERFACE_SIZE - FLASH_CONFIG_SIZE)) { + gflashConfig.fileSize = tempFileSize; + tempFileSize = __REV(gflashConfig.fileSize); + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBuffer((uint8_t*) &tempFileSize, 1, sizeof(gflashConfig.fileSize)); + } else { + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } + } else { + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } + break; + case gFlashCfgFileVisible_c: + if (size == 1) { + /* If size is 1 (only cmd id), this means it's a read */ + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBuffer((uint8_t*) &gflashConfig.fileVisible, 1, sizeof(gflashConfig.fileVisible)); + } else if (size == 2) { + /* If size is 2 (cmd id + 1B data), this means it's a write */ + gflashConfig.fileVisible = pI2cCommand->cmdData.data[0]; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBuffer((uint8_t*) &gflashConfig.fileVisible, 1, sizeof(gflashConfig.fileVisible)); + } else { + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } + break; + case gFlashCfgWrite_c: + // Check first is config is already present in flash + // If differences are found, erase and write new config + if (0 != memcmp(&gflashConfig, (void *)FLASH_CONFIG_ADDRESS, sizeof(flashConfig_t))) { + status = erase_storage_sector(FLASH_CONFIG_ADDRESS); + + if (status != 0) { + pI2cCommand->cmdId = gFlashError_c; + } + else { + status = program_storage_page(FLASH_CONFIG_ADDRESS, sizeof(flashConfig_t), (uint8_t *) &gflashConfig); + } + } + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + break; + case gFlashCfgErase_c: + // Erase flash sector containing flash config + status = erase_storage_sector(FLASH_CONFIG_ADDRESS); + + if (status != 0) { + pI2cCommand->cmdId = gFlashError_c; + } + else { + // Return flash config (RAM) to default values + gflashConfig.key = CFG_KEY; + memcpy(gflashConfig.fileName, FLASH_CFG_FILENAME, 11); + gflashConfig.fileSize = FLASH_CFG_FILESIZE; + gflashConfig.fileVisible = FLASH_CFG_FILEVISIBLE; + } + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + break; + case gFlashStorageSize_c: + pI2cCommand->cmdData.data[0] = (FLASH_INTERFACE_SIZE - FLASH_CONFIG_SIZE)/1024; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 2); + break; + case gFlashSectorSize_c: + pI2cCommand->cmdData.data[0] = (DAPLINK_SECTOR_SIZE >> 8) & 0xFF; + pI2cCommand->cmdData.data[1] = DAPLINK_SECTOR_SIZE & 0xFF; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 3); + break; + case gFlashRemountMSD_c: + do_remount = true; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + break; + default: + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + break; + } + + // Response ready, assert COMBINED_SENSOR_INT + PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_MuxAsGpio); +} + +static void i2c_read_flash_callback(uint8_t* pData, uint8_t size) { + i2c_clearBuffer(); + + // Release COMBINED_SENSOR_INT + PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); +} diff --git a/source/board/microbitv2/i2c_commands.h b/source/board/microbitv2/i2c_commands.h index f799222df..f18436210 100644 --- a/source/board/microbitv2/i2c_commands.h +++ b/source/board/microbitv2/i2c_commands.h @@ -3,7 +3,6 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved * Copyright 2020 NXP * SPDX-License-Identifier: Apache-2.0 * @@ -27,11 +26,16 @@ #include "cmsis_compiler.h" #include "virtual_fs.h" +#include "fsl_common.h" #ifdef __cplusplus extern "C" { #endif +#define I2C_SLAVE_NRF_KL_COMMS (0x70U) +#define I2C_SLAVE_HID (0x71U) +#define I2C_SLAVE_FLASH (0x72U) + /*! i2c command Id type enumeration */ typedef enum cmdId_tag { gNopCmd_c = 0x00, @@ -166,6 +170,27 @@ typedef __PACKED_STRUCT i2cFlashCmd_tag { } cmdData; } i2cFlashCmd_t; +/*! i2c Write Callback prototype */ +typedef void (*i2cWriteCallback_t) +( + uint8_t* pData, + uint8_t size +); + +/*! i2c Read Callback prototype */ +typedef void (*i2cReadCallback_t) +( + uint8_t* pData, + uint8_t size +); + +void i2c_initialize(void); +void i2c_deinitialize(void); +status_t i2c_registerWriteCallback(i2cWriteCallback_t writeCallback, uint8_t slaveAddress); +status_t i2c_registerReadCallback(i2cReadCallback_t readCallback, uint8_t slaveAddress); +void i2c_clearBuffer(void); +void i2c_fillBuffer(uint8_t* data, uint32_t position, uint32_t size); + #ifdef __cplusplus } #endif diff --git a/source/board/microbitv2/led_error_app.c b/source/board/microbitv2/led_error_app.c new file mode 100644 index 000000000..32de07e70 --- /dev/null +++ b/source/board/microbitv2/led_error_app.c @@ -0,0 +1,198 @@ +/** + * @file led_error_app.c + * @brief + * + * DAPLink Interface Firmware + * Copyright 2020 Micro:bit Educational Foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +// Program to display error code 0-999 on LEDs: face,E,digit,digit,digit + +unsigned int g_led_error_bin_len = 2016; + +// Offset of 2 byte error code, low byte first +unsigned int g_led_error_bin_code = 1908; + +unsigned char g_led_error_bin_data[] = { + 0x00, 0x00, 0x02, 0x20, 0xb5, 0x02, 0x00, 0x00, 0xdd, 0x02, 0x00, 0x00, + 0xdf, 0x02, 0x00, 0x00, 0xe1, 0x02, 0x00, 0x00, 0xe3, 0x02, 0x00, 0x00, + 0xe5, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe7, 0x02, 0x00, 0x00, + 0xe9, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xeb, 0x02, 0x00, 0x00, + 0xed, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xef, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0xb5, 0x05, 0x4c, + 0x23, 0x78, 0x33, 0xb9, 0x04, 0x4b, 0x13, 0xb1, 0x04, 0x48, 0xaf, 0xf3, + 0x00, 0x80, 0x01, 0x23, 0x23, 0x70, 0x10, 0xbd, 0x74, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0x60, 0x07, 0x00, 0x00, 0x08, 0xb5, 0x03, 0x4b, + 0x1b, 0xb1, 0x03, 0x49, 0x03, 0x48, 0xaf, 0xf3, 0x00, 0x80, 0x08, 0xbd, + 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x20, 0x60, 0x07, 0x00, 0x00, + 0x15, 0x4b, 0x00, 0x2b, 0x08, 0xbf, 0x13, 0x4b, 0x9d, 0x46, 0xa3, 0xf5, + 0x80, 0x3a, 0x00, 0x21, 0x8b, 0x46, 0x0f, 0x46, 0x13, 0x48, 0x14, 0x4a, + 0x12, 0x1a, 0x00, 0xf0, 0x47, 0xfa, 0x0f, 0x4b, 0x00, 0x2b, 0x00, 0xd0, + 0x98, 0x47, 0x0e, 0x4b, 0x00, 0x2b, 0x00, 0xd0, 0x98, 0x47, 0x00, 0x20, + 0x00, 0x21, 0x04, 0x00, 0x0d, 0x00, 0x0d, 0x48, 0x00, 0x28, 0x02, 0xd0, + 0x0c, 0x48, 0xaf, 0xf3, 0x00, 0x80, 0x00, 0xf0, 0x0f, 0xfa, 0x20, 0x00, + 0x29, 0x00, 0x00, 0xf0, 0xed, 0xf9, 0x00, 0xf0, 0xf5, 0xf9, 0x00, 0xbf, + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x20, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x74, 0x00, 0x00, 0x20, 0x90, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x49, 0x07, 0x4a, + 0x07, 0x4b, 0x9b, 0x1a, 0x03, 0xdd, 0x04, 0x3b, 0xc8, 0x58, 0xd0, 0x50, + 0xfb, 0xdc, 0x00, 0xf0, 0x2f, 0xf8, 0xff, 0xf7, 0xb9, 0xff, 0x00, 0x00, + 0x6c, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x74, 0x00, 0x00, 0x20, + 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, + 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xbf, 0xf3, 0x4f, 0x8f, + 0x05, 0x49, 0x06, 0x4b, 0xca, 0x68, 0x02, 0xf4, 0xe0, 0x62, 0x13, 0x43, + 0xcb, 0x60, 0xbf, 0xf3, 0x4f, 0x8f, 0x00, 0xbf, 0xfd, 0xe7, 0x00, 0xbf, + 0x00, 0xed, 0x00, 0xe0, 0x04, 0x00, 0xfa, 0x05, 0x03, 0x4b, 0x18, 0x68, + 0xa0, 0xf1, 0x0d, 0x03, 0x58, 0x42, 0x58, 0x41, 0x70, 0x47, 0x00, 0xbf, + 0x30, 0x01, 0x00, 0x10, 0x08, 0xb5, 0xff, 0xf7, 0xf3, 0xff, 0x40, 0xb1, + 0x4f, 0xf0, 0x80, 0x43, 0x00, 0x22, 0xc3, 0xf8, 0x0c, 0x21, 0xc3, 0xf8, + 0x10, 0x21, 0xc3, 0xf8, 0x38, 0x25, 0xff, 0xf7, 0xe7, 0xff, 0x00, 0x28, + 0x46, 0xd0, 0x4f, 0xf0, 0x80, 0x52, 0x59, 0x4b, 0xd2, 0xf8, 0x04, 0x14, + 0xc3, 0xf8, 0x20, 0x15, 0xd2, 0xf8, 0x08, 0x14, 0xc3, 0xf8, 0x24, 0x15, + 0xd2, 0xf8, 0x0c, 0x14, 0xc3, 0xf8, 0x28, 0x15, 0xd2, 0xf8, 0x10, 0x14, + 0xc3, 0xf8, 0x2c, 0x15, 0xd2, 0xf8, 0x14, 0x14, 0xc3, 0xf8, 0x30, 0x15, + 0xd2, 0xf8, 0x18, 0x14, 0xc3, 0xf8, 0x34, 0x15, 0xd2, 0xf8, 0x1c, 0x14, + 0xc3, 0xf8, 0x40, 0x15, 0xd2, 0xf8, 0x20, 0x14, 0xc3, 0xf8, 0x44, 0x15, + 0xd2, 0xf8, 0x24, 0x14, 0xc3, 0xf8, 0x48, 0x15, 0xd2, 0xf8, 0x28, 0x14, + 0xc3, 0xf8, 0x4c, 0x15, 0xd2, 0xf8, 0x2c, 0x14, 0xc3, 0xf8, 0x50, 0x15, + 0xd2, 0xf8, 0x30, 0x14, 0xc3, 0xf8, 0x54, 0x15, 0xd2, 0xf8, 0x34, 0x14, + 0xc3, 0xf8, 0x60, 0x15, 0xd2, 0xf8, 0x38, 0x14, 0xc3, 0xf8, 0x64, 0x15, + 0xd2, 0xf8, 0x3c, 0x14, 0xc3, 0xf8, 0x68, 0x15, 0xd2, 0xf8, 0x40, 0x14, + 0xc3, 0xf8, 0x6c, 0x15, 0xd2, 0xf8, 0x44, 0x24, 0xc3, 0xf8, 0x70, 0x25, + 0xff, 0xf7, 0x9c, 0xff, 0x48, 0xb1, 0x4f, 0xf0, 0x80, 0x43, 0xd3, 0xf8, + 0x00, 0x24, 0xd1, 0x07, 0x44, 0xbf, 0x6f, 0xf0, 0x01, 0x02, 0xc3, 0xf8, + 0x00, 0x24, 0x31, 0x4a, 0xd2, 0xf8, 0x88, 0x30, 0x43, 0xf4, 0x70, 0x03, + 0xc2, 0xf8, 0x88, 0x30, 0xbf, 0xf3, 0x4f, 0x8f, 0xbf, 0xf3, 0x6f, 0x8f, + 0x4f, 0xf0, 0x10, 0x23, 0xd3, 0xf8, 0x0c, 0x22, 0xd2, 0x07, 0x1e, 0xd5, + 0x29, 0x4b, 0x01, 0x22, 0xc3, 0xf8, 0x04, 0x25, 0xd3, 0xf8, 0x00, 0x24, + 0x00, 0x2a, 0xfb, 0xd0, 0x4f, 0xf0, 0x10, 0x22, 0xd2, 0xf8, 0x0c, 0x32, + 0x23, 0xf0, 0x01, 0x03, 0xc2, 0xf8, 0x0c, 0x32, 0x21, 0x4b, 0x1a, 0x46, + 0xd3, 0xf8, 0x00, 0x14, 0x00, 0x29, 0xfb, 0xd0, 0x00, 0x21, 0xc3, 0xf8, + 0x04, 0x15, 0xd2, 0xf8, 0x00, 0x34, 0x00, 0x2b, 0xfb, 0xd0, 0xff, 0xf7, + 0x4f, 0xff, 0xd3, 0xf8, 0x00, 0x22, 0x00, 0x2a, 0x03, 0xdb, 0xd3, 0xf8, + 0x04, 0x32, 0x00, 0x2b, 0x23, 0xda, 0x16, 0x4b, 0x01, 0x22, 0xc3, 0xf8, + 0x04, 0x25, 0xd3, 0xf8, 0x00, 0x24, 0x00, 0x2a, 0xfb, 0xd0, 0x4f, 0xf0, + 0x10, 0x22, 0x12, 0x21, 0xc2, 0xf8, 0x00, 0x12, 0xd3, 0xf8, 0x00, 0x24, + 0x00, 0x2a, 0xfb, 0xd0, 0x4f, 0xf0, 0x10, 0x23, 0x12, 0x22, 0xc3, 0xf8, + 0x04, 0x22, 0x0b, 0x4b, 0x1a, 0x46, 0xd3, 0xf8, 0x00, 0x14, 0x00, 0x29, + 0xfb, 0xd0, 0x00, 0x21, 0xc3, 0xf8, 0x04, 0x15, 0xd2, 0xf8, 0x00, 0x34, + 0x00, 0x2b, 0xfb, 0xd0, 0xd1, 0xe7, 0x05, 0x4b, 0x05, 0x4a, 0x1a, 0x60, + 0x08, 0xbd, 0x00, 0xbf, 0x00, 0xc0, 0x00, 0x40, 0x00, 0xed, 0x00, 0xe0, + 0x00, 0xe0, 0x01, 0x40, 0x00, 0x00, 0x00, 0x20, 0x00, 0x90, 0xd0, 0x03, + 0x1f, 0x28, 0x86, 0xbf, 0x00, 0xf0, 0x1f, 0x00, 0x04, 0x4a, 0x4f, 0xf0, + 0xa0, 0x42, 0x01, 0x23, 0x03, 0xfa, 0x00, 0xf0, 0xc2, 0xf8, 0x08, 0x05, + 0x70, 0x47, 0x00, 0xbf, 0x00, 0x03, 0x00, 0x50, 0x80, 0x5c, 0xc1, 0xf1, + 0x04, 0x01, 0x08, 0x41, 0xc0, 0x43, 0x00, 0xf0, 0x01, 0x00, 0x70, 0x47, + 0x00, 0x23, 0x4f, 0xf0, 0xa0, 0x42, 0x83, 0x42, 0x00, 0xdb, 0x70, 0x47, + 0xd2, 0xf8, 0x04, 0x15, 0x01, 0x33, 0xf8, 0xe7, 0x38, 0xb5, 0x1c, 0x20, + 0xff, 0xf7, 0xda, 0xff, 0x0b, 0x20, 0xff, 0xf7, 0xd7, 0xff, 0x1f, 0x20, + 0xff, 0xf7, 0xd4, 0xff, 0x25, 0x20, 0xff, 0xf7, 0xd1, 0xff, 0x0b, 0x4c, + 0x0b, 0x4d, 0x1e, 0x20, 0xff, 0xf7, 0xcc, 0xff, 0x00, 0x22, 0x01, 0x20, + 0x13, 0x5d, 0x1f, 0x2b, 0x86, 0xbf, 0x03, 0xf0, 0x1f, 0x03, 0x29, 0x46, + 0x4f, 0xf0, 0xa0, 0x41, 0x01, 0x32, 0x00, 0xfa, 0x03, 0xf3, 0x05, 0x2a, + 0xc1, 0xf8, 0x0c, 0x35, 0xf0, 0xd1, 0x38, 0xbd, 0x54, 0x07, 0x00, 0x00, + 0x00, 0x03, 0x00, 0x50, 0x2d, 0xe9, 0xf8, 0x4f, 0x80, 0x46, 0x3b, 0x48, + 0x3b, 0x4d, 0x00, 0x22, 0x82, 0x46, 0x03, 0x24, 0x13, 0x5c, 0x1f, 0x2b, + 0x86, 0xbf, 0x03, 0xf0, 0x1f, 0x03, 0x29, 0x46, 0x4f, 0xf0, 0xa0, 0x41, + 0x03, 0xf5, 0xe0, 0x73, 0x01, 0x32, 0x05, 0x2a, 0x41, 0xf8, 0x23, 0x40, + 0xf0, 0xd1, 0x33, 0x48, 0x31, 0x4d, 0x00, 0x22, 0x03, 0x24, 0x13, 0x5c, + 0x1f, 0x2b, 0x86, 0xbf, 0x03, 0xf0, 0x1f, 0x03, 0x29, 0x46, 0x4f, 0xf0, + 0xa0, 0x41, 0x03, 0xf5, 0xe0, 0x73, 0x01, 0x32, 0x05, 0x2a, 0x41, 0xf8, + 0x23, 0x40, 0xf0, 0xd1, 0xff, 0xf7, 0xac, 0xff, 0x4f, 0xf0, 0x01, 0x09, + 0x28, 0x4c, 0x00, 0x26, 0x32, 0x27, 0x00, 0x25, 0x25, 0x4b, 0x58, 0x5d, + 0xff, 0xf7, 0x80, 0xff, 0x4f, 0xf0, 0x00, 0x0b, 0x2a, 0x46, 0x59, 0x46, + 0x20, 0x46, 0x1a, 0xf8, 0x0b, 0x30, 0xff, 0xf7, 0x87, 0xff, 0xa0, 0xbb, + 0x1f, 0x2b, 0x86, 0xbf, 0x03, 0xf0, 0x1f, 0x03, 0x1b, 0x4a, 0x4f, 0xf0, + 0xa0, 0x42, 0x09, 0xfa, 0x03, 0xf3, 0xc2, 0xf8, 0x0c, 0x35, 0x0b, 0xf1, + 0x01, 0x0b, 0xbb, 0xf1, 0x05, 0x0f, 0xe7, 0xd1, 0x44, 0xf6, 0x20, 0x60, + 0x01, 0x35, 0xff, 0xf7, 0x79, 0xff, 0xff, 0xf7, 0x81, 0xff, 0x05, 0x2d, + 0xd8, 0xd1, 0x01, 0x3f, 0xd5, 0xd1, 0x13, 0x48, 0x01, 0x36, 0xff, 0xf7, + 0x6f, 0xff, 0x04, 0x2e, 0xcc, 0xd0, 0x31, 0x46, 0x64, 0x23, 0x0a, 0x22, + 0x02, 0xe0, 0x01, 0x39, 0x93, 0xfb, 0xf2, 0xf3, 0x01, 0x29, 0xfa, 0xd1, + 0x98, 0xfb, 0xf3, 0xf3, 0x93, 0xfb, 0xf2, 0xf4, 0x02, 0xfb, 0x14, 0x34, + 0x09, 0x4b, 0x04, 0xeb, 0x84, 0x04, 0x1c, 0x44, 0xba, 0xe7, 0x18, 0x46, + 0xff, 0xf7, 0x3e, 0xff, 0xd1, 0xe7, 0x00, 0xbf, 0x4a, 0x07, 0x00, 0x00, + 0x00, 0x03, 0x00, 0x50, 0x54, 0x07, 0x00, 0x00, 0x4f, 0x07, 0x00, 0x00, + 0x40, 0x42, 0x0f, 0x00, 0x18, 0x07, 0x00, 0x00, 0x08, 0xb5, 0x03, 0x4b, + 0x98, 0x88, 0xff, 0xf7, 0x75, 0xff, 0x00, 0x20, 0x08, 0xbd, 0x00, 0xbf, + 0x04, 0x00, 0x00, 0x20, 0x08, 0xb5, 0x07, 0x4b, 0x04, 0x46, 0x13, 0xb1, + 0x00, 0x21, 0xaf, 0xf3, 0x00, 0x80, 0x05, 0x4b, 0x18, 0x68, 0x83, 0x6a, + 0x03, 0xb1, 0x98, 0x47, 0x20, 0x46, 0x00, 0xf0, 0x31, 0xf8, 0x00, 0xbf, + 0x00, 0x00, 0x00, 0x00, 0x5c, 0x07, 0x00, 0x00, 0x70, 0xb5, 0x0d, 0x4e, + 0x0d, 0x4c, 0xa4, 0x1b, 0xa4, 0x10, 0x00, 0x25, 0xa5, 0x42, 0x09, 0xd1, + 0x0b, 0x4e, 0x0c, 0x4c, 0x00, 0xf0, 0x22, 0xf8, 0xa4, 0x1b, 0xa4, 0x10, + 0x00, 0x25, 0xa5, 0x42, 0x05, 0xd1, 0x70, 0xbd, 0x56, 0xf8, 0x25, 0x30, + 0x98, 0x47, 0x01, 0x35, 0xee, 0xe7, 0x56, 0xf8, 0x25, 0x30, 0x98, 0x47, + 0x01, 0x35, 0xf2, 0xe7, 0x6c, 0x00, 0x00, 0x20, 0x6c, 0x00, 0x00, 0x20, + 0x6c, 0x00, 0x00, 0x20, 0x70, 0x00, 0x00, 0x20, 0x02, 0x44, 0x03, 0x46, + 0x93, 0x42, 0x00, 0xd1, 0x70, 0x47, 0x03, 0xf8, 0x01, 0x1b, 0xf9, 0xe7, + 0xfe, 0xe7, 0x00, 0xbf, 0xf8, 0xb5, 0x00, 0xbf, 0xf8, 0xbc, 0x08, 0xbc, + 0x9e, 0x46, 0x70, 0x47, 0xf8, 0xb5, 0x00, 0xbf, 0xf8, 0xbc, 0x08, 0xbc, + 0x9e, 0x46, 0x70, 0x47, 0x0c, 0x92, 0x52, 0x52, 0x4c, 0x04, 0x8c, 0x84, + 0x84, 0x8e, 0x1c, 0x82, 0x4c, 0x90, 0x1e, 0x1e, 0xc2, 0x44, 0x92, 0x4c, + 0x06, 0xca, 0x52, 0x5f, 0xe2, 0x1f, 0xf0, 0x1e, 0xc1, 0x3e, 0x02, 0x44, + 0x8e, 0xd1, 0x2e, 0x1f, 0xe2, 0x44, 0x88, 0x10, 0x0e, 0xd1, 0x2e, 0xd1, + 0x2e, 0x0e, 0xd1, 0x2e, 0xc4, 0x88, 0x1c, 0x0b, 0x1f, 0x25, 0x1e, 0x1b, + 0x1b, 0x00, 0x0e, 0x11, 0x15, 0x16, 0x0f, 0x18, 0x13, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xdc, 0xfa, 0xff, 0x7f, + 0x01, 0x00, 0x00, 0x00, 0x00, 0x90, 0xd0, 0x03, 0xde, 0xc0, 0xce, 0xfa, + 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x25, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00 +}; diff --git a/source/board/microbitv2/led_error_app.h b/source/board/microbitv2/led_error_app.h index 081c1aeac..c618a048f 100644 --- a/source/board/microbitv2/led_error_app.h +++ b/source/board/microbitv2/led_error_app.h @@ -3,7 +3,6 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved * Copyright 2020 Micro:bit Educational Foundation * SPDX-License-Identifier: Apache-2.0 * @@ -20,180 +19,19 @@ * limitations under the License. */ -// Program to display error code 0-999 on LEDs: face,E,digit,digit,digit +#ifndef LED_ERROR_APP_H +#define LED_ERROR_APP_H -unsigned int led_error_bin_len = 2016; +#ifdef __cplusplus +extern "C" { +#endif -// Offset of 2 byte error code, low byte first -unsigned int led_error_bin_code = 1908; +extern unsigned int g_led_error_bin_len; +extern unsigned int g_led_error_bin_code; +extern unsigned char g_led_error_bin_data[]; -unsigned char led_error_bin_data[] = { - 0x00, 0x00, 0x02, 0x20, 0xb5, 0x02, 0x00, 0x00, 0xdd, 0x02, 0x00, 0x00, - 0xdf, 0x02, 0x00, 0x00, 0xe1, 0x02, 0x00, 0x00, 0xe3, 0x02, 0x00, 0x00, - 0xe5, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe7, 0x02, 0x00, 0x00, - 0xe9, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xeb, 0x02, 0x00, 0x00, - 0xed, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, - 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, - 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, - 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, - 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, - 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, - 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, - 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, - 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, - 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, - 0xef, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, - 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, - 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xef, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xef, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0xb5, 0x05, 0x4c, - 0x23, 0x78, 0x33, 0xb9, 0x04, 0x4b, 0x13, 0xb1, 0x04, 0x48, 0xaf, 0xf3, - 0x00, 0x80, 0x01, 0x23, 0x23, 0x70, 0x10, 0xbd, 0x74, 0x00, 0x00, 0x20, - 0x00, 0x00, 0x00, 0x00, 0x60, 0x07, 0x00, 0x00, 0x08, 0xb5, 0x03, 0x4b, - 0x1b, 0xb1, 0x03, 0x49, 0x03, 0x48, 0xaf, 0xf3, 0x00, 0x80, 0x08, 0xbd, - 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x20, 0x60, 0x07, 0x00, 0x00, - 0x15, 0x4b, 0x00, 0x2b, 0x08, 0xbf, 0x13, 0x4b, 0x9d, 0x46, 0xa3, 0xf5, - 0x80, 0x3a, 0x00, 0x21, 0x8b, 0x46, 0x0f, 0x46, 0x13, 0x48, 0x14, 0x4a, - 0x12, 0x1a, 0x00, 0xf0, 0x47, 0xfa, 0x0f, 0x4b, 0x00, 0x2b, 0x00, 0xd0, - 0x98, 0x47, 0x0e, 0x4b, 0x00, 0x2b, 0x00, 0xd0, 0x98, 0x47, 0x00, 0x20, - 0x00, 0x21, 0x04, 0x00, 0x0d, 0x00, 0x0d, 0x48, 0x00, 0x28, 0x02, 0xd0, - 0x0c, 0x48, 0xaf, 0xf3, 0x00, 0x80, 0x00, 0xf0, 0x0f, 0xfa, 0x20, 0x00, - 0x29, 0x00, 0x00, 0xf0, 0xed, 0xf9, 0x00, 0xf0, 0xf5, 0xf9, 0x00, 0xbf, - 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x20, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x74, 0x00, 0x00, 0x20, 0x90, 0x00, 0x00, 0x20, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x49, 0x07, 0x4a, - 0x07, 0x4b, 0x9b, 0x1a, 0x03, 0xdd, 0x04, 0x3b, 0xc8, 0x58, 0xd0, 0x50, - 0xfb, 0xdc, 0x00, 0xf0, 0x2f, 0xf8, 0xff, 0xf7, 0xb9, 0xff, 0x00, 0x00, - 0x6c, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x74, 0x00, 0x00, 0x20, - 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, - 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xbf, 0xf3, 0x4f, 0x8f, - 0x05, 0x49, 0x06, 0x4b, 0xca, 0x68, 0x02, 0xf4, 0xe0, 0x62, 0x13, 0x43, - 0xcb, 0x60, 0xbf, 0xf3, 0x4f, 0x8f, 0x00, 0xbf, 0xfd, 0xe7, 0x00, 0xbf, - 0x00, 0xed, 0x00, 0xe0, 0x04, 0x00, 0xfa, 0x05, 0x03, 0x4b, 0x18, 0x68, - 0xa0, 0xf1, 0x0d, 0x03, 0x58, 0x42, 0x58, 0x41, 0x70, 0x47, 0x00, 0xbf, - 0x30, 0x01, 0x00, 0x10, 0x08, 0xb5, 0xff, 0xf7, 0xf3, 0xff, 0x40, 0xb1, - 0x4f, 0xf0, 0x80, 0x43, 0x00, 0x22, 0xc3, 0xf8, 0x0c, 0x21, 0xc3, 0xf8, - 0x10, 0x21, 0xc3, 0xf8, 0x38, 0x25, 0xff, 0xf7, 0xe7, 0xff, 0x00, 0x28, - 0x46, 0xd0, 0x4f, 0xf0, 0x80, 0x52, 0x59, 0x4b, 0xd2, 0xf8, 0x04, 0x14, - 0xc3, 0xf8, 0x20, 0x15, 0xd2, 0xf8, 0x08, 0x14, 0xc3, 0xf8, 0x24, 0x15, - 0xd2, 0xf8, 0x0c, 0x14, 0xc3, 0xf8, 0x28, 0x15, 0xd2, 0xf8, 0x10, 0x14, - 0xc3, 0xf8, 0x2c, 0x15, 0xd2, 0xf8, 0x14, 0x14, 0xc3, 0xf8, 0x30, 0x15, - 0xd2, 0xf8, 0x18, 0x14, 0xc3, 0xf8, 0x34, 0x15, 0xd2, 0xf8, 0x1c, 0x14, - 0xc3, 0xf8, 0x40, 0x15, 0xd2, 0xf8, 0x20, 0x14, 0xc3, 0xf8, 0x44, 0x15, - 0xd2, 0xf8, 0x24, 0x14, 0xc3, 0xf8, 0x48, 0x15, 0xd2, 0xf8, 0x28, 0x14, - 0xc3, 0xf8, 0x4c, 0x15, 0xd2, 0xf8, 0x2c, 0x14, 0xc3, 0xf8, 0x50, 0x15, - 0xd2, 0xf8, 0x30, 0x14, 0xc3, 0xf8, 0x54, 0x15, 0xd2, 0xf8, 0x34, 0x14, - 0xc3, 0xf8, 0x60, 0x15, 0xd2, 0xf8, 0x38, 0x14, 0xc3, 0xf8, 0x64, 0x15, - 0xd2, 0xf8, 0x3c, 0x14, 0xc3, 0xf8, 0x68, 0x15, 0xd2, 0xf8, 0x40, 0x14, - 0xc3, 0xf8, 0x6c, 0x15, 0xd2, 0xf8, 0x44, 0x24, 0xc3, 0xf8, 0x70, 0x25, - 0xff, 0xf7, 0x9c, 0xff, 0x48, 0xb1, 0x4f, 0xf0, 0x80, 0x43, 0xd3, 0xf8, - 0x00, 0x24, 0xd1, 0x07, 0x44, 0xbf, 0x6f, 0xf0, 0x01, 0x02, 0xc3, 0xf8, - 0x00, 0x24, 0x31, 0x4a, 0xd2, 0xf8, 0x88, 0x30, 0x43, 0xf4, 0x70, 0x03, - 0xc2, 0xf8, 0x88, 0x30, 0xbf, 0xf3, 0x4f, 0x8f, 0xbf, 0xf3, 0x6f, 0x8f, - 0x4f, 0xf0, 0x10, 0x23, 0xd3, 0xf8, 0x0c, 0x22, 0xd2, 0x07, 0x1e, 0xd5, - 0x29, 0x4b, 0x01, 0x22, 0xc3, 0xf8, 0x04, 0x25, 0xd3, 0xf8, 0x00, 0x24, - 0x00, 0x2a, 0xfb, 0xd0, 0x4f, 0xf0, 0x10, 0x22, 0xd2, 0xf8, 0x0c, 0x32, - 0x23, 0xf0, 0x01, 0x03, 0xc2, 0xf8, 0x0c, 0x32, 0x21, 0x4b, 0x1a, 0x46, - 0xd3, 0xf8, 0x00, 0x14, 0x00, 0x29, 0xfb, 0xd0, 0x00, 0x21, 0xc3, 0xf8, - 0x04, 0x15, 0xd2, 0xf8, 0x00, 0x34, 0x00, 0x2b, 0xfb, 0xd0, 0xff, 0xf7, - 0x4f, 0xff, 0xd3, 0xf8, 0x00, 0x22, 0x00, 0x2a, 0x03, 0xdb, 0xd3, 0xf8, - 0x04, 0x32, 0x00, 0x2b, 0x23, 0xda, 0x16, 0x4b, 0x01, 0x22, 0xc3, 0xf8, - 0x04, 0x25, 0xd3, 0xf8, 0x00, 0x24, 0x00, 0x2a, 0xfb, 0xd0, 0x4f, 0xf0, - 0x10, 0x22, 0x12, 0x21, 0xc2, 0xf8, 0x00, 0x12, 0xd3, 0xf8, 0x00, 0x24, - 0x00, 0x2a, 0xfb, 0xd0, 0x4f, 0xf0, 0x10, 0x23, 0x12, 0x22, 0xc3, 0xf8, - 0x04, 0x22, 0x0b, 0x4b, 0x1a, 0x46, 0xd3, 0xf8, 0x00, 0x14, 0x00, 0x29, - 0xfb, 0xd0, 0x00, 0x21, 0xc3, 0xf8, 0x04, 0x15, 0xd2, 0xf8, 0x00, 0x34, - 0x00, 0x2b, 0xfb, 0xd0, 0xd1, 0xe7, 0x05, 0x4b, 0x05, 0x4a, 0x1a, 0x60, - 0x08, 0xbd, 0x00, 0xbf, 0x00, 0xc0, 0x00, 0x40, 0x00, 0xed, 0x00, 0xe0, - 0x00, 0xe0, 0x01, 0x40, 0x00, 0x00, 0x00, 0x20, 0x00, 0x90, 0xd0, 0x03, - 0x1f, 0x28, 0x86, 0xbf, 0x00, 0xf0, 0x1f, 0x00, 0x04, 0x4a, 0x4f, 0xf0, - 0xa0, 0x42, 0x01, 0x23, 0x03, 0xfa, 0x00, 0xf0, 0xc2, 0xf8, 0x08, 0x05, - 0x70, 0x47, 0x00, 0xbf, 0x00, 0x03, 0x00, 0x50, 0x80, 0x5c, 0xc1, 0xf1, - 0x04, 0x01, 0x08, 0x41, 0xc0, 0x43, 0x00, 0xf0, 0x01, 0x00, 0x70, 0x47, - 0x00, 0x23, 0x4f, 0xf0, 0xa0, 0x42, 0x83, 0x42, 0x00, 0xdb, 0x70, 0x47, - 0xd2, 0xf8, 0x04, 0x15, 0x01, 0x33, 0xf8, 0xe7, 0x38, 0xb5, 0x1c, 0x20, - 0xff, 0xf7, 0xda, 0xff, 0x0b, 0x20, 0xff, 0xf7, 0xd7, 0xff, 0x1f, 0x20, - 0xff, 0xf7, 0xd4, 0xff, 0x25, 0x20, 0xff, 0xf7, 0xd1, 0xff, 0x0b, 0x4c, - 0x0b, 0x4d, 0x1e, 0x20, 0xff, 0xf7, 0xcc, 0xff, 0x00, 0x22, 0x01, 0x20, - 0x13, 0x5d, 0x1f, 0x2b, 0x86, 0xbf, 0x03, 0xf0, 0x1f, 0x03, 0x29, 0x46, - 0x4f, 0xf0, 0xa0, 0x41, 0x01, 0x32, 0x00, 0xfa, 0x03, 0xf3, 0x05, 0x2a, - 0xc1, 0xf8, 0x0c, 0x35, 0xf0, 0xd1, 0x38, 0xbd, 0x54, 0x07, 0x00, 0x00, - 0x00, 0x03, 0x00, 0x50, 0x2d, 0xe9, 0xf8, 0x4f, 0x80, 0x46, 0x3b, 0x48, - 0x3b, 0x4d, 0x00, 0x22, 0x82, 0x46, 0x03, 0x24, 0x13, 0x5c, 0x1f, 0x2b, - 0x86, 0xbf, 0x03, 0xf0, 0x1f, 0x03, 0x29, 0x46, 0x4f, 0xf0, 0xa0, 0x41, - 0x03, 0xf5, 0xe0, 0x73, 0x01, 0x32, 0x05, 0x2a, 0x41, 0xf8, 0x23, 0x40, - 0xf0, 0xd1, 0x33, 0x48, 0x31, 0x4d, 0x00, 0x22, 0x03, 0x24, 0x13, 0x5c, - 0x1f, 0x2b, 0x86, 0xbf, 0x03, 0xf0, 0x1f, 0x03, 0x29, 0x46, 0x4f, 0xf0, - 0xa0, 0x41, 0x03, 0xf5, 0xe0, 0x73, 0x01, 0x32, 0x05, 0x2a, 0x41, 0xf8, - 0x23, 0x40, 0xf0, 0xd1, 0xff, 0xf7, 0xac, 0xff, 0x4f, 0xf0, 0x01, 0x09, - 0x28, 0x4c, 0x00, 0x26, 0x32, 0x27, 0x00, 0x25, 0x25, 0x4b, 0x58, 0x5d, - 0xff, 0xf7, 0x80, 0xff, 0x4f, 0xf0, 0x00, 0x0b, 0x2a, 0x46, 0x59, 0x46, - 0x20, 0x46, 0x1a, 0xf8, 0x0b, 0x30, 0xff, 0xf7, 0x87, 0xff, 0xa0, 0xbb, - 0x1f, 0x2b, 0x86, 0xbf, 0x03, 0xf0, 0x1f, 0x03, 0x1b, 0x4a, 0x4f, 0xf0, - 0xa0, 0x42, 0x09, 0xfa, 0x03, 0xf3, 0xc2, 0xf8, 0x0c, 0x35, 0x0b, 0xf1, - 0x01, 0x0b, 0xbb, 0xf1, 0x05, 0x0f, 0xe7, 0xd1, 0x44, 0xf6, 0x20, 0x60, - 0x01, 0x35, 0xff, 0xf7, 0x79, 0xff, 0xff, 0xf7, 0x81, 0xff, 0x05, 0x2d, - 0xd8, 0xd1, 0x01, 0x3f, 0xd5, 0xd1, 0x13, 0x48, 0x01, 0x36, 0xff, 0xf7, - 0x6f, 0xff, 0x04, 0x2e, 0xcc, 0xd0, 0x31, 0x46, 0x64, 0x23, 0x0a, 0x22, - 0x02, 0xe0, 0x01, 0x39, 0x93, 0xfb, 0xf2, 0xf3, 0x01, 0x29, 0xfa, 0xd1, - 0x98, 0xfb, 0xf3, 0xf3, 0x93, 0xfb, 0xf2, 0xf4, 0x02, 0xfb, 0x14, 0x34, - 0x09, 0x4b, 0x04, 0xeb, 0x84, 0x04, 0x1c, 0x44, 0xba, 0xe7, 0x18, 0x46, - 0xff, 0xf7, 0x3e, 0xff, 0xd1, 0xe7, 0x00, 0xbf, 0x4a, 0x07, 0x00, 0x00, - 0x00, 0x03, 0x00, 0x50, 0x54, 0x07, 0x00, 0x00, 0x4f, 0x07, 0x00, 0x00, - 0x40, 0x42, 0x0f, 0x00, 0x18, 0x07, 0x00, 0x00, 0x08, 0xb5, 0x03, 0x4b, - 0x98, 0x88, 0xff, 0xf7, 0x75, 0xff, 0x00, 0x20, 0x08, 0xbd, 0x00, 0xbf, - 0x04, 0x00, 0x00, 0x20, 0x08, 0xb5, 0x07, 0x4b, 0x04, 0x46, 0x13, 0xb1, - 0x00, 0x21, 0xaf, 0xf3, 0x00, 0x80, 0x05, 0x4b, 0x18, 0x68, 0x83, 0x6a, - 0x03, 0xb1, 0x98, 0x47, 0x20, 0x46, 0x00, 0xf0, 0x31, 0xf8, 0x00, 0xbf, - 0x00, 0x00, 0x00, 0x00, 0x5c, 0x07, 0x00, 0x00, 0x70, 0xb5, 0x0d, 0x4e, - 0x0d, 0x4c, 0xa4, 0x1b, 0xa4, 0x10, 0x00, 0x25, 0xa5, 0x42, 0x09, 0xd1, - 0x0b, 0x4e, 0x0c, 0x4c, 0x00, 0xf0, 0x22, 0xf8, 0xa4, 0x1b, 0xa4, 0x10, - 0x00, 0x25, 0xa5, 0x42, 0x05, 0xd1, 0x70, 0xbd, 0x56, 0xf8, 0x25, 0x30, - 0x98, 0x47, 0x01, 0x35, 0xee, 0xe7, 0x56, 0xf8, 0x25, 0x30, 0x98, 0x47, - 0x01, 0x35, 0xf2, 0xe7, 0x6c, 0x00, 0x00, 0x20, 0x6c, 0x00, 0x00, 0x20, - 0x6c, 0x00, 0x00, 0x20, 0x70, 0x00, 0x00, 0x20, 0x02, 0x44, 0x03, 0x46, - 0x93, 0x42, 0x00, 0xd1, 0x70, 0x47, 0x03, 0xf8, 0x01, 0x1b, 0xf9, 0xe7, - 0xfe, 0xe7, 0x00, 0xbf, 0xf8, 0xb5, 0x00, 0xbf, 0xf8, 0xbc, 0x08, 0xbc, - 0x9e, 0x46, 0x70, 0x47, 0xf8, 0xb5, 0x00, 0xbf, 0xf8, 0xbc, 0x08, 0xbc, - 0x9e, 0x46, 0x70, 0x47, 0x0c, 0x92, 0x52, 0x52, 0x4c, 0x04, 0x8c, 0x84, - 0x84, 0x8e, 0x1c, 0x82, 0x4c, 0x90, 0x1e, 0x1e, 0xc2, 0x44, 0x92, 0x4c, - 0x06, 0xca, 0x52, 0x5f, 0xe2, 0x1f, 0xf0, 0x1e, 0xc1, 0x3e, 0x02, 0x44, - 0x8e, 0xd1, 0x2e, 0x1f, 0xe2, 0x44, 0x88, 0x10, 0x0e, 0xd1, 0x2e, 0xd1, - 0x2e, 0x0e, 0xd1, 0x2e, 0xc4, 0x88, 0x1c, 0x0b, 0x1f, 0x25, 0x1e, 0x1b, - 0x1b, 0x00, 0x0e, 0x11, 0x15, 0x16, 0x0f, 0x18, 0x13, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xdc, 0xfa, 0xff, 0x7f, - 0x01, 0x00, 0x00, 0x00, 0x00, 0x90, 0xd0, 0x03, 0xde, 0xc0, 0xce, 0xfa, - 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x25, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00 -}; +#ifdef __cplusplus +} +#endif + +#endif diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 8d4c5d2e3..aa6912d6a 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -31,7 +31,6 @@ #include "rl_usb.h" #include "pwr_mon.h" #include "main_interface.h" -#include "i2c.h" #include "i2c_commands.h" #include "adc.h" #include "fsl_port.h" @@ -43,35 +42,12 @@ #include "vfs_manager.h" #include "cortex_m.h" #include "fsl_flash.h" +#include "microbitv2.h" #ifdef DRAG_N_DROP_SUPPORT #include "flash_intf.h" #endif -#define M0_RESERVED_VECT_OFFSET (4 * 4) -#define M0_RESERVED_VECT_SIZE (3 * 4) // Size for mem fault, bus fault and usage fault vectors - -#define BRD_ID_1_UPPER_THR_V 935 // Upper threshold in mV for 100nF and 4700R -#define BRD_ID_1_LOWER_THR_V 268 // Lower threshold in mV for 100nF and 4700R - -#define PWR_LED_ON_MAX_BRIGHTNESS 255 // Max LED Brightness (PC Connected) -#define PWR_LED_INIT_FADE_BRIGHTNESS 200 // Initial fade LED Brightness -#define PWR_LED_ON_BATT_BRIGHTNESS 100 // LED Brightness while being powered by battery -#define PWR_LED_FADEOUT_MIN_BRIGHTNESS 80 // Minimum LED brightness when fading out -#define PWR_LED_SLEEP_STATE_DEFAULT true -#define AUTOMATIC_SLEEP_DEFAULT true - -#define FLASH_CONFIG_ADDRESS (0x00020000) -#define FLASH_CONFIG_SIZE (0x00000400) -#define FLASH_INTERFACE_SIZE (128*1024) -#define FLASH_STORAGE_ADDRESS (0x00020400) -#define FLASH_CFG_FILENAME "DATA BIN" -#define FLASH_CFG_FILESIZE (126*1024) -#define FLASH_CFG_FILEVISIBLE false - -// 'kvld' in hex - key valid -#define CFG_KEY 0x6b766c64 - const char * const board_id_mb_2_0 = "9903"; const char * const board_id_mb_2_1 = "9904"; @@ -84,6 +60,18 @@ volatile bool usb_pc_connected = false; uint8_t i2c_wake_timeout = 0; bool i2c_allow_sleep = true; power_source_t power_source; +app_power_mode_t interface_power_mode = kAPP_PowerModeVlls0; +bool power_led_sleep_state_on = PWR_LED_SLEEP_STATE_DEFAULT; +bool automatic_sleep_on = AUTOMATIC_SLEEP_DEFAULT; +main_shutdown_state_t main_shutdown_state = MAIN_SHUTDOWN_WAITING; +bool do_remount = false; + +flashConfig_t gflashConfig = { + .key = CFG_KEY, + .fileName = FLASH_CFG_FILENAME, + .fileSize = FLASH_CFG_FILESIZE, + .fileVisible = FLASH_CFG_FILEVISIBLE, +}; typedef enum { BOARD_VERSION_2_0 = 0, @@ -96,49 +84,19 @@ extern bool go_to_sleep; extern i2c_slave_handle_t g_s_handle; extern flash_config_t g_flash; -typedef enum main_shutdown_state { - MAIN_SHUTDOWN_WAITING = 0, - MAIN_SHUTDOWN_WAITING_OFF, - MAIN_SHUTDOWN_PENDING, - MAIN_SHUTDOWN_REACHED, - MAIN_SHUTDOWN_REACHED_FADE, - MAIN_SHUTDOWN_REQUESTED, - MAIN_USER_EVENT, - MAIN_LED_BLINK_ONCE, - MAIN_LED_BLINKING, - MAIN_LED_FULL_BRIGHTNESS, - MAIN_SHUTDOWN_CANCEL -} main_shutdown_state_t; - extern void main_powerdown_event(void); -static void i2c_write_comms_callback(uint8_t* pData, uint8_t size); -static void i2c_read_comms_callback(uint8_t* pData, uint8_t size); -static void i2c_write_flash_callback(uint8_t* pData, uint8_t size); -static void i2c_read_flash_callback(uint8_t* pData, uint8_t size); static uint32_t read_file_data_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors); // shutdown state -static main_shutdown_state_t main_shutdown_state = MAIN_SHUTDOWN_WAITING; static uint8_t shutdown_led_dc = PWR_LED_ON_MAX_BRIGHTNESS; static uint8_t final_fade_led_dc = 0; static uint8_t power_led_max_duty_cycle = PWR_LED_ON_MAX_BRIGHTNESS; static uint8_t initial_fade_brightness = PWR_LED_INIT_FADE_BRIGHTNESS; -static bool power_led_sleep_state_on = PWR_LED_SLEEP_STATE_DEFAULT; -static bool automatic_sleep_on = AUTOMATIC_SLEEP_DEFAULT; -static app_power_mode_t interface_power_mode = kAPP_PowerModeVlls0; // reset button state count static uint16_t gpio_reset_count = 0; // button state static uint8_t reset_pressed = 0; -static bool do_remount = false; - -static flashConfig_t gflashConfig = { - .key = CFG_KEY, - .fileName = FLASH_CFG_FILENAME, - .fileSize = FLASH_CFG_FILESIZE, - .fileVisible = FLASH_CFG_FILEVISIBLE, -}; // Board Rev ID detection. Reads BRD_REV_ID voltage // Depends on gpio_init() to have been executed already @@ -249,10 +207,6 @@ static void prerun_board_config(void) flexio_pwm_set_dutycycle(gamma_led_dc); i2c_initialize(); - i2c_RegisterWriteCallback(i2c_write_comms_callback, I2C_SLAVE_NRF_KL_COMMS); - i2c_RegisterReadCallback(i2c_read_comms_callback, I2C_SLAVE_NRF_KL_COMMS); - i2c_RegisterWriteCallback(i2c_write_flash_callback, I2C_SLAVE_FLASH); - i2c_RegisterReadCallback(i2c_read_flash_callback, I2C_SLAVE_FLASH); gpio_pin_config_t pin_config = { .pinDirection = kGPIO_DigitalOutput, @@ -554,15 +508,15 @@ void vfs_user_build_filesystem_hook() { if (error != ERROR_SUCCESS) { // Error code offset after "0xFACEC0DE" magic word - led_error_bin_data[led_error_bin_code] = (uint8_t) microbit_error & 0xFF; - led_error_bin_data[led_error_bin_code + 1] = (uint8_t) (microbit_error >> 8) & 0xFF; + g_led_error_bin_data[g_led_error_bin_code] = (uint8_t) microbit_error & 0xFF; + g_led_error_bin_data[g_led_error_bin_code + 1] = (uint8_t) (microbit_error >> 8) & 0xFF; status = flash_manager_init(flash_intf_target); if (status != ERROR_SUCCESS) { util_assert(0); } - status = flash_manager_data(0, (const uint8_t*)led_error_bin_data, led_error_bin_len); + status = flash_manager_data(0, (const uint8_t*)g_led_error_bin_data, g_led_error_bin_len); if (status != ERROR_SUCCESS) { flash_manager_uninit(); util_assert(0); @@ -622,423 +576,3 @@ const board_info_t g_board_info = { .target_cfg = &target_device, }; -static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { - i2cCommand_t* pI2cCommand = (i2cCommand_t*) pData; - i2cCommand_t i2cResponse = {0}; - bool assert_interrupt = true; - - switch (pI2cCommand->cmdId) { - case gReadRequest_c: - i2cResponse.cmdId = gReadResponse_c; - i2cResponse.cmdData.readRspCmd.propertyId = pI2cCommand->cmdData.readReqCmd.propertyId; - switch (pI2cCommand->cmdData.readReqCmd.propertyId) { - case gDAPLinkBoardVersion_c: - i2cResponse.cmdData.readRspCmd.dataSize = sizeof(board_id_hex); - memcpy(&i2cResponse.cmdData.readRspCmd.data, &board_id_hex, sizeof(board_id_hex)); - break; - case gI2CProtocolVersion_c: { - uint16_t i2c_version = 1; - i2cResponse.cmdData.readRspCmd.dataSize = sizeof(i2c_version); - memcpy(&i2cResponse.cmdData.readRspCmd.data, &i2c_version, sizeof(i2c_version)); - } - break; - case gDAPLinkVersion_c: { - uint16_t daplink_version = DAPLINK_VERSION; - i2cResponse.cmdData.readRspCmd.dataSize = sizeof(daplink_version); - memcpy(&i2cResponse.cmdData.readRspCmd.data, &daplink_version, sizeof(daplink_version)); - } - break; - case gPowerState_c: - power_source = pwr_mon_get_power_source(); - i2cResponse.cmdData.readRspCmd.dataSize = sizeof(power_source); - memcpy(&i2cResponse.cmdData.readRspCmd.data, &power_source, sizeof(power_source)); - break; - case gPowerConsumption_c: { - uint32_t vin_voltage_uv = pwr_mon_get_vin_mv() * 1000; - uint32_t vbat_voltage_uv = pwr_mon_get_vbat_mv() * 1000; - i2cResponse.cmdData.readRspCmd.dataSize = sizeof(vin_voltage_uv) + sizeof(vbat_voltage_uv); - memcpy(&i2cResponse.cmdData.readRspCmd.data[0], &vbat_voltage_uv, sizeof(vbat_voltage_uv)); - memcpy(&i2cResponse.cmdData.readRspCmd.data[sizeof(vbat_voltage_uv)], &vin_voltage_uv, sizeof(vin_voltage_uv)); - } - break; - case gUSBEnumerationState_c: - i2cResponse.cmdData.readRspCmd.dataSize = sizeof(usb_state); - memcpy(&i2cResponse.cmdData.readRspCmd.data, &usb_state, sizeof(usb_state)); - break; - case gPowerMode_c: - i2cResponse.cmdId = gErrorResponse_c; - i2cResponse.cmdData.errorRspCmd.errorCode = gErrorReadDisallowed_c; - break; - default: - i2cResponse.cmdId = gErrorResponse_c; - i2cResponse.cmdData.errorRspCmd.errorCode = gErrorUnknownProperty_c; - break; - } - break; - case gReadResponse_c: - i2cResponse.cmdId = gErrorResponse_c; - i2cResponse.cmdData.errorRspCmd.errorCode = gErrorCommandDisallowed_c; - break; - case gWriteRequest_c: - switch (pI2cCommand->cmdData.writeReqCmd.propertyId) { - case gDAPLinkBoardVersion_c: - case gI2CProtocolVersion_c: - case gDAPLinkVersion_c: - case gPowerState_c: - case gPowerConsumption_c: - case gUSBEnumerationState_c: - i2cResponse.cmdId = gErrorResponse_c; - i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWriteDisallowed_c; - break; - case gPowerMode_c: - if (pI2cCommand->cmdData.writeReqCmd.dataSize == 1) { - if (pI2cCommand->cmdData.writeReqCmd.data[0] == kAPP_PowerModeVlls0) { - interface_power_mode = kAPP_PowerModeVlls0; - i2cResponse.cmdId = gWriteResponse_c; - i2cResponse.cmdData.writeRspCmd.propertyId = pI2cCommand->cmdData.writeReqCmd.propertyId; - } else { - i2cResponse.cmdId = gErrorResponse_c; - i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWriteFail_c; - } - } else { - i2cResponse.cmdId = gErrorResponse_c; - i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWrongPropertySize_c; - } - break; - case gPowerLedSleepState_c: - if (pI2cCommand->cmdData.writeReqCmd.dataSize == 1) { - if (pI2cCommand->cmdData.writeReqCmd.data[0] != 0) { - power_led_sleep_state_on = true; - } - else { - power_led_sleep_state_on = false; - } - i2cResponse.cmdId = gWriteResponse_c; - i2cResponse.cmdData.writeRspCmd.propertyId = pI2cCommand->cmdData.writeReqCmd.propertyId; - } else { - i2cResponse.cmdId = gErrorResponse_c; - i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWrongPropertySize_c; - } - break; - case gAutomaticSleep_c: - if (pI2cCommand->cmdData.writeReqCmd.dataSize == 1) { - if (pI2cCommand->cmdData.writeReqCmd.data[0] != 0) { - automatic_sleep_on = true; - } - else { - automatic_sleep_on = false; - } - i2cResponse.cmdId = gWriteResponse_c; - i2cResponse.cmdData.writeRspCmd.propertyId = pI2cCommand->cmdData.writeReqCmd.propertyId; - } else { - i2cResponse.cmdId = gErrorResponse_c; - i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWrongPropertySize_c; - } - break; - default: - i2cResponse.cmdId = gErrorResponse_c; - i2cResponse.cmdData.errorRspCmd.errorCode = gErrorUnknownProperty_c; - break; - } - break; - case gWriteResponse_c: - break; - case gErrorResponse_c: - break; - case gNopCmd_c: - assert_interrupt = false; - break; - default: - i2cResponse.cmdId = gErrorResponse_c; - i2cResponse.cmdData.errorRspCmd.errorCode = gErrorUnknownCommand_c; - break; - } - - if (assert_interrupt) { - i2c_fillBuffer((uint8_t*) &i2cResponse, 0, sizeof(i2cResponse)); - // Response ready, assert COMBINED_SENSOR_INT - PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_MuxAsGpio); - } -} - -static void i2c_read_comms_callback(uint8_t* pData, uint8_t size) { - i2cCommand_t* pI2cCommand = (i2cCommand_t*) pData; - - switch (pI2cCommand->cmdId) { - case gWriteResponse_c: - switch (pI2cCommand->cmdData.writeRspCmd.propertyId) { - case gPowerMode_c: - main_shutdown_state = MAIN_SHUTDOWN_REQUESTED; - break; - } - break; - } - - i2c_clearBuffer(); - - // Release COMBINED_SENSOR_INT - PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); -} - -static bool file_extension_allowed(const vfs_filename_t filename) -{ - const char *valid_extensions[] = { - "BIN", - "TXT", - "CSV", - "HTM", - "WAV", - }; - uint32_t i; - - // Check for invalid starting characters - for (i = 0; i < (sizeof((valid_extensions))/sizeof((valid_extensions)[0])); i++) { - if (0 == memcmp(&filename[8], valid_extensions[i], 3)) { - return true; - } - } - - // Some checks failed so file extension is invalid - return false; -} - -static uint32_t erase_storage_sector(uint32_t adr) -{ - int status = FLASH_Erase(&g_flash, adr, g_flash.PFlashSectorSize, kFLASH_apiEraseKey); - if (status == kStatus_Success) - { - status = FLASH_VerifyErase(&g_flash, adr, g_flash.PFlashSectorSize, kFLASH_marginValueNormal); - } - return status; -} - -static uint32_t program_storage_page(uint32_t adr, uint32_t sz, uint8_t *buf) -{ - /* Verify data is word aligned */ - util_assert(!((uint32_t)buf & 0x3)); - - int status = FLASH_Program(&g_flash, adr, (uint32_t *) buf, sz); - if (status == kStatus_Success) - { - // Must use kFlashMargin_User, or kFlashMargin_Factory for verify program - status = FLASH_VerifyProgram(&g_flash, adr, sz, - (uint32_t *) buf, kFLASH_marginValueUser, - NULL, NULL); - } - return status; -} - -static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { - i2cFlashCmd_t* pI2cCommand = (i2cFlashCmd_t*) pData; - - uint32_t status = 0; - - uint32_t storage_address = pI2cCommand->cmdData.write.addr2 << 16 | - pI2cCommand->cmdData.write.addr1 << 8 | - pI2cCommand->cmdData.write.addr0 << 0; - uint32_t address = storage_address + FLASH_STORAGE_ADDRESS; - uint32_t length = __REV(pI2cCommand->cmdData.write.length); - uint32_t data = (uint32_t) pI2cCommand->cmdData.write.data; - - i2c_clearBuffer(); - - switch (pI2cCommand->cmdId) { - case gFlashDataWrite_c: - /* Validate length field matches with I2C Write data */ - if (size == length + 8) { - /* Address range and alignment validation done inside program_storage_page() */ - status = program_storage_page(address, length, (uint8_t *) data); - - if (0 != status) { - pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - } - else { - /* Fill TX Buffer with received command args */ - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, sizeof(i2cFlashCmd_t) - 1024); - /* Fill TX Buffer with Flash Data Written */ - i2c_fillBuffer((uint8_t*) address, sizeof(i2cFlashCmd_t) - 1024, length); - } - } else { - pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - } - break; - case gFlashDataRead_c: { - /* Do address range validation */ - if (address + length > (FLASH_CONFIG_ADDRESS + FLASH_INTERFACE_SIZE)) { - pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - } else { - /* Fill TX Buffer with received command args */ - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, sizeof(i2cFlashCmd_t) - 1024); - /* Fill TX Buffer with Flash Data Read */ - i2c_fillBuffer((uint8_t*) address, sizeof(i2cFlashCmd_t) - 1024, length); - } - } - break; - case gFlashDataErase_c: { - uint32_t address = pI2cCommand->cmdData.erase.sAddr2 << 16 | - pI2cCommand->cmdData.erase.sAddr1 << 8 | - pI2cCommand->cmdData.erase.sAddr0 << 0; - uint32_t start_addr = address + FLASH_STORAGE_ADDRESS; - - address = pI2cCommand->cmdData.erase.eAddr2 << 16 | - pI2cCommand->cmdData.erase.eAddr1 << 8 | - pI2cCommand->cmdData.erase.eAddr0 << 0; - uint32_t end_addr = address + FLASH_STORAGE_ADDRESS; - - /* Do address range validation */ - if (start_addr % DAPLINK_SECTOR_SIZE == 0 && - end_addr % DAPLINK_SECTOR_SIZE == 0 && - start_addr <= end_addr && - start_addr < (FLASH_CONFIG_ADDRESS + FLASH_INTERFACE_SIZE) && - end_addr < (FLASH_CONFIG_ADDRESS + FLASH_INTERFACE_SIZE)) { - for (uint32_t addr = start_addr; addr <= end_addr && status == 0; addr += DAPLINK_SECTOR_SIZE) { - status = erase_storage_sector(addr); - } - - if (status != 0) { - pI2cCommand->cmdId = gFlashError_c; - } - } else { - pI2cCommand->cmdId = gFlashError_c; - } - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - - } - break; - case gFlashCfgFileName_c: - if (size == 1) { - /* If size is 1 (only cmd id), this means it's a read */ - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - i2c_fillBuffer((uint8_t*) &gflashConfig.fileName, 1, sizeof(gflashConfig.fileName)); - } else if (size == 12) { - /* If size is 12 (cmd id + 11B data), this means it's a write */ - /* Validate 8.3 filename */ - if (filename_valid((char *) pI2cCommand->cmdData.data)) { - // Check allowed extensions (.bin, .txt, .csv, .htm, .wav) - if (file_extension_allowed((char *) pI2cCommand->cmdData.data)) { - memcpy(gflashConfig.fileName, pI2cCommand->cmdData.data, 11); - } - // If disallowed extension is requested, .bin will be used - else { - memcpy(gflashConfig.fileName, pI2cCommand->cmdData.data, 8); - memcpy(&gflashConfig.fileName[8], "BIN", 3); - } - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - i2c_fillBuffer((uint8_t*) &gflashConfig.fileName, 1, sizeof(gflashConfig.fileName)); - } - else { - // Send error if invalid filename - pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - } - } else { - pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - } - break; - case gFlashCfgFileSize_c: - if (size == 1) { - /* If size is 1 (only cmd id), this means it's a read */ - uint32_t tempFileSize = __REV(gflashConfig.fileSize); - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - i2c_fillBuffer((uint8_t*) &tempFileSize, 1, sizeof(gflashConfig.fileSize)); - } else if (size == 5) { - /* If size is 5 (cmd id + 4B data), this means it's a write */ - uint32_t tempFileSize = pI2cCommand->cmdData.data[0] << 24 | - pI2cCommand->cmdData.data[1] << 16 | - pI2cCommand->cmdData.data[2] << 8 | - pI2cCommand->cmdData.data[3] << 0; - - /* Validate file size */ - if (tempFileSize <= (FLASH_INTERFACE_SIZE - FLASH_CONFIG_SIZE)) { - gflashConfig.fileSize = tempFileSize; - tempFileSize = __REV(gflashConfig.fileSize); - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - i2c_fillBuffer((uint8_t*) &tempFileSize, 1, sizeof(gflashConfig.fileSize)); - } else { - pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - } - } else { - pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - } - break; - case gFlashCfgFileVisible_c: - if (size == 1) { - /* If size is 1 (only cmd id), this means it's a read */ - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - i2c_fillBuffer((uint8_t*) &gflashConfig.fileVisible, 1, sizeof(gflashConfig.fileVisible)); - } else if (size == 2) { - /* If size is 2 (cmd id + 1B data), this means it's a write */ - gflashConfig.fileVisible = pI2cCommand->cmdData.data[0]; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - i2c_fillBuffer((uint8_t*) &gflashConfig.fileVisible, 1, sizeof(gflashConfig.fileVisible)); - } else { - pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - } - break; - case gFlashCfgWrite_c: - // Check first is config is already present in flash - // If differences are found, erase and write new config - if (0 != memcmp(&gflashConfig, (void *)FLASH_CONFIG_ADDRESS, sizeof(flashConfig_t))) { - status = erase_storage_sector(FLASH_CONFIG_ADDRESS); - - if (status != 0) { - pI2cCommand->cmdId = gFlashError_c; - } - else { - status = program_storage_page(FLASH_CONFIG_ADDRESS, sizeof(flashConfig_t), (uint8_t *) &gflashConfig); - } - } - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - break; - case gFlashCfgErase_c: - // Erase flash sector containing flash config - status = erase_storage_sector(FLASH_CONFIG_ADDRESS); - - if (status != 0) { - pI2cCommand->cmdId = gFlashError_c; - } - else { - // Return flash config (RAM) to default values - gflashConfig.key = CFG_KEY; - memcpy(gflashConfig.fileName, FLASH_CFG_FILENAME, 11); - gflashConfig.fileSize = FLASH_CFG_FILESIZE; - gflashConfig.fileVisible = FLASH_CFG_FILEVISIBLE; - } - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - break; - case gFlashStorageSize_c: - pI2cCommand->cmdData.data[0] = (FLASH_INTERFACE_SIZE - FLASH_CONFIG_SIZE)/1024; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 2); - break; - case gFlashSectorSize_c: - pI2cCommand->cmdData.data[0] = (DAPLINK_SECTOR_SIZE >> 8) & 0xFF; - pI2cCommand->cmdData.data[1] = DAPLINK_SECTOR_SIZE & 0xFF; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 3); - break; - case gFlashRemountMSD_c: - do_remount = true; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - break; - default: - pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - break; - } - - // Response ready, assert COMBINED_SENSOR_INT - PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_MuxAsGpio); -} - -static void i2c_read_flash_callback(uint8_t* pData, uint8_t size) { - i2c_clearBuffer(); - - // Release COMBINED_SENSOR_INT - PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); -} diff --git a/source/board/microbitv2/microbitv2.h b/source/board/microbitv2/microbitv2.h new file mode 100644 index 000000000..ea0d60c1f --- /dev/null +++ b/source/board/microbitv2/microbitv2.h @@ -0,0 +1,63 @@ +/** + * @file microbitv2.h + * @brief + * + * DAPLink Interface Firmware + * Copyright 2020 NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MICROBITV2_H_ +#define MICROBITV2_H_ + +#define M0_RESERVED_VECT_OFFSET (4 * 4) +#define M0_RESERVED_VECT_SIZE (3 * 4) // Size for mem fault, bus fault and usage fault vectors + +#define BRD_ID_1_UPPER_THR_V 935 // Upper threshold in mV for 100nF and 4700R +#define BRD_ID_1_LOWER_THR_V 268 // Lower threshold in mV for 100nF and 4700R + +#define PWR_LED_ON_MAX_BRIGHTNESS 255 // Max LED Brightness (PC Connected) +#define PWR_LED_INIT_FADE_BRIGHTNESS 200 // Initial fade LED Brightness +#define PWR_LED_ON_BATT_BRIGHTNESS 100 // LED Brightness while being powered by battery +#define PWR_LED_FADEOUT_MIN_BRIGHTNESS 80 // Minimum LED brightness when fading out +#define PWR_LED_SLEEP_STATE_DEFAULT true +#define AUTOMATIC_SLEEP_DEFAULT true + +#define FLASH_CONFIG_ADDRESS (0x00020000) +#define FLASH_CONFIG_SIZE (0x00000400) +#define FLASH_INTERFACE_SIZE (128*1024) +#define FLASH_STORAGE_ADDRESS (0x00020400) +#define FLASH_CFG_FILENAME "DATA BIN" +#define FLASH_CFG_FILESIZE (126*1024) +#define FLASH_CFG_FILEVISIBLE false + +// 'kvld' in hex - key valid +#define CFG_KEY 0x6b766c64 + +typedef enum main_shutdown_state { + MAIN_SHUTDOWN_WAITING = 0, + MAIN_SHUTDOWN_WAITING_OFF, + MAIN_SHUTDOWN_PENDING, + MAIN_SHUTDOWN_REACHED, + MAIN_SHUTDOWN_REACHED_FADE, + MAIN_SHUTDOWN_REQUESTED, + MAIN_USER_EVENT, + MAIN_LED_BLINK_ONCE, + MAIN_LED_BLINKING, + MAIN_LED_FULL_BRIGHTNESS, + MAIN_SHUTDOWN_CANCEL +} main_shutdown_state_t; + +#endif /* MICROBITV2_H_ */ diff --git a/source/board/microbitv2/power.c b/source/board/microbitv2/power.c index fd95a4480..1ee666670 100644 --- a/source/board/microbitv2/power.c +++ b/source/board/microbitv2/power.c @@ -3,7 +3,6 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved * Copyright 2020 NXP * SPDX-License-Identifier: Apache-2.0 * @@ -32,7 +31,7 @@ #include "pwr_mon.h" #include "IO_Config.h" #include "uart.h" -#include "i2c.h" +#include "i2c_commands.h" #include "rl_usb.h" /******************************************************************************* diff --git a/source/board/microbitv2/power.h b/source/board/microbitv2/power.h index 43254b783..e16035ecc 100644 --- a/source/board/microbitv2/power.h +++ b/source/board/microbitv2/power.h @@ -3,7 +3,6 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved * Copyright 2020 NXP * SPDX-License-Identifier: Apache-2.0 * diff --git a/source/board/microbitv2/pwr_mon.c b/source/board/microbitv2/pwr_mon.c index bf89089ba..0fe9ca83d 100644 --- a/source/board/microbitv2/pwr_mon.c +++ b/source/board/microbitv2/pwr_mon.c @@ -3,7 +3,6 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved * Copyright 2020 NXP * SPDX-License-Identifier: Apache-2.0 * diff --git a/source/board/microbitv2/pwr_mon.h b/source/board/microbitv2/pwr_mon.h index cc9ac6871..7ed5f7efe 100644 --- a/source/board/microbitv2/pwr_mon.h +++ b/source/board/microbitv2/pwr_mon.h @@ -3,7 +3,6 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved * Copyright 2020 NXP * SPDX-License-Identifier: Apache-2.0 * diff --git a/source/daplink/drag-n-drop/vfs_user.c b/source/daplink/drag-n-drop/vfs_user.c index 5119c1646..b92790f0d 100644 --- a/source/daplink/drag-n-drop/vfs_user.c +++ b/source/daplink/drag-n-drop/vfs_user.c @@ -45,6 +45,11 @@ //! device. This is to accomodate for hex file programming. #define VFS_DISK_SIZE (MB(64)) +// Additional buffer space to display more than 512 bytes in DETAILS.TXT +#if !defined(BOARD_EXTRA_BUFFER) +#define BOARD_EXTRA_BUFFER 0 +#endif + //! @brief Constants for magic action or config files. //! //! The "magic files" are files with a special name that if created on the USB MSC volume, will @@ -118,7 +123,7 @@ static const magic_file_info_t s_magic_file_info[] = { { "PAGE_OFFACT", kChipEraseActionFile }, }; -static uint8_t file_buffer[VFS_SECTOR_SIZE+100]; +static uint8_t file_buffer[VFS_SECTOR_SIZE+BOARD_EXTRA_BUFFER]; static char assert_buf[64 + 1]; static uint16_t assert_line; static assert_source_t assert_source; @@ -354,7 +359,7 @@ static uint32_t read_file_details_txt(uint32_t sector_offset, uint8_t *data, uin return 0; } - size = update_details_txt_file(file_buffer, VFS_SECTOR_SIZE+100); + size = update_details_txt_file(file_buffer, VFS_SECTOR_SIZE+BOARD_EXTRA_BUFFER); if (size - VFS_SECTOR_SIZE * sector_offset > VFS_SECTOR_SIZE) { memcpy(data, file_buffer + sector_offset * VFS_SECTOR_SIZE, VFS_SECTOR_SIZE); diff --git a/source/daplink/error.h b/source/daplink/error.h index 325337ba2..ed248cbae 100644 --- a/source/daplink/error.h +++ b/source/daplink/error.h @@ -27,6 +27,7 @@ extern "C" { #endif // Keep in sync with the lists error_message and error_type +// New values shold be added to the end of the enum to preserve error codes typedef enum { /* Shared errors */ ERROR_SUCCESS = 0, diff --git a/source/daplink/interface/main_interface.c b/source/daplink/interface/main_interface.c index 281df332b..76bd7240f 100644 --- a/source/daplink/interface/main_interface.c +++ b/source/daplink/interface/main_interface.c @@ -144,7 +144,10 @@ static main_led_state_t msc_led_state = MAIN_LED_FLASH; main_usb_connect_t usb_state; static bool usb_test_mode = false; -__WEAK void board_30ms_hook(void){} +__WEAK void board_30ms_hook(void) +{ + +} __WEAK void handle_reset_button(void) { diff --git a/source/hic_hal/adc.h b/source/hic_hal/adc.h index e2bbcc618..4d70131f3 100644 --- a/source/hic_hal/adc.h +++ b/source/hic_hal/adc.h @@ -3,7 +3,6 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved * Copyright 2020 NXP * SPDX-License-Identifier: Apache-2.0 * diff --git a/source/hic_hal/atmel/sam3u2c/usb_config.c b/source/hic_hal/atmel/sam3u2c/usb_config.c index ed39c0cfb..e78132cd4 100644 --- a/source/hic_hal/atmel/sam3u2c/usb_config.c +++ b/source/hic_hal/atmel/sam3u2c/usb_config.c @@ -68,7 +68,11 @@ // when the device is fully operational (bMaxPower) // #define USBD_CFGDESC_BMATTRIBUTES 0x80 +#if !defined(BOARD_USB_BMAXPOWER) #define USBD_CFGDESC_BMAXPOWER 0xFA +#else +#define USBD_CFGDESC_BMAXPOWER BOARD_USB_BMAXPOWER +#endif // String Settings // These settings affect String Descriptor diff --git a/source/hic_hal/freescale/k20dx/usb_config.c b/source/hic_hal/freescale/k20dx/usb_config.c index 123957820..972a0523f 100644 --- a/source/hic_hal/freescale/k20dx/usb_config.c +++ b/source/hic_hal/freescale/k20dx/usb_config.c @@ -68,7 +68,11 @@ // when the device is fully operational (bMaxPower) // #define USBD_CFGDESC_BMATTRIBUTES 0x80 +#if !defined(BOARD_USB_BMAXPOWER) #define USBD_CFGDESC_BMAXPOWER 0xFA +#else +#define USBD_CFGDESC_BMAXPOWER BOARD_USB_BMAXPOWER +#endif // String Settings // These settings affect String Descriptor diff --git a/source/hic_hal/freescale/k26f/usb_config.c b/source/hic_hal/freescale/k26f/usb_config.c index f816f800c..9b8dde6c1 100644 --- a/source/hic_hal/freescale/k26f/usb_config.c +++ b/source/hic_hal/freescale/k26f/usb_config.c @@ -77,7 +77,11 @@ // when the device is fully operational (bMaxPower) // #define USBD_CFGDESC_BMATTRIBUTES 0x80 +#if !defined(BOARD_USB_BMAXPOWER) #define USBD_CFGDESC_BMAXPOWER 0xFA +#else +#define USBD_CFGDESC_BMAXPOWER BOARD_USB_BMAXPOWER +#endif // String Settings // These settings affect String Descriptor diff --git a/source/hic_hal/freescale/kl26z/usb_config.c b/source/hic_hal/freescale/kl26z/usb_config.c index 123957820..972a0523f 100644 --- a/source/hic_hal/freescale/kl26z/usb_config.c +++ b/source/hic_hal/freescale/kl26z/usb_config.c @@ -68,7 +68,11 @@ // when the device is fully operational (bMaxPower) // #define USBD_CFGDESC_BMATTRIBUTES 0x80 +#if !defined(BOARD_USB_BMAXPOWER) #define USBD_CFGDESC_BMAXPOWER 0xFA +#else +#define USBD_CFGDESC_BMAXPOWER BOARD_USB_BMAXPOWER +#endif // String Settings // These settings affect String Descriptor diff --git a/source/hic_hal/freescale/kl27z/DAP_config.h b/source/hic_hal/freescale/kl27z/DAP_config.h index 8268194e0..3bd98065c 100644 --- a/source/hic_hal/freescale/kl27z/DAP_config.h +++ b/source/hic_hal/freescale/kl27z/DAP_config.h @@ -68,7 +68,9 @@ Provides definitions about: /// Default communication speed on the Debug Access Port for SWD and JTAG mode. /// Used to initialize the default SWD/JTAG clock frequency. /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting. -#define DAP_DEFAULT_SWJ_CLOCK 8000000 ///< Default SWD/JTAG clock frequency in Hz. +#if !defined(DAP_DEFAULT_SWJ_CLOCK) +#define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz. +#endif /// Maximum Package Size for Command and Response data. /// This configuration settings is used to optimized the communication performance with the diff --git a/source/hic_hal/freescale/kl27z/adc.c b/source/hic_hal/freescale/kl27z/adc.c index 7c0fb8c38..cc4ddfacd 100644 --- a/source/hic_hal/freescale/kl27z/adc.c +++ b/source/hic_hal/freescale/kl27z/adc.c @@ -3,7 +3,6 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved * Copyright 2020 NXP * SPDX-License-Identifier: Apache-2.0 * diff --git a/source/hic_hal/freescale/kl27z/usb_config.c b/source/hic_hal/freescale/kl27z/usb_config.c index 63fac8b02..7bd4a8225 100644 --- a/source/hic_hal/freescale/kl27z/usb_config.c +++ b/source/hic_hal/freescale/kl27z/usb_config.c @@ -68,7 +68,12 @@ // when the device is fully operational (bMaxPower) // #define USBD_CFGDESC_BMATTRIBUTES 0x80 -#define USBD_CFGDESC_BMAXPOWER 0x96 // Temporal modification to 300mA for microbit + +#if !defined(BOARD_USB_BMAXPOWER) +#define USBD_CFGDESC_BMAXPOWER 0xFA +#else +#define USBD_CFGDESC_BMAXPOWER BOARD_USB_BMAXPOWER +#endif // String Settings // These settings affect String Descriptor diff --git a/source/hic_hal/maxim/max32620/usb_config.c b/source/hic_hal/maxim/max32620/usb_config.c index ca50523e1..21abdbaf3 100644 --- a/source/hic_hal/maxim/max32620/usb_config.c +++ b/source/hic_hal/maxim/max32620/usb_config.c @@ -68,7 +68,11 @@ // when the device is fully operational (bMaxPower) // #define USBD_CFGDESC_BMATTRIBUTES 0x80 +#if !defined(BOARD_USB_BMAXPOWER) #define USBD_CFGDESC_BMAXPOWER 0xFA +#else +#define USBD_CFGDESC_BMAXPOWER BOARD_USB_BMAXPOWER +#endif // String Settings // These settings affect String Descriptor diff --git a/source/hic_hal/maxim/max32625/usb_config.c b/source/hic_hal/maxim/max32625/usb_config.c index ca50523e1..21abdbaf3 100755 --- a/source/hic_hal/maxim/max32625/usb_config.c +++ b/source/hic_hal/maxim/max32625/usb_config.c @@ -68,7 +68,11 @@ // when the device is fully operational (bMaxPower) // #define USBD_CFGDESC_BMATTRIBUTES 0x80 +#if !defined(BOARD_USB_BMAXPOWER) #define USBD_CFGDESC_BMAXPOWER 0xFA +#else +#define USBD_CFGDESC_BMAXPOWER BOARD_USB_BMAXPOWER +#endif // String Settings // These settings affect String Descriptor diff --git a/source/hic_hal/nuvoton/m48ssidae/usb_config.c b/source/hic_hal/nuvoton/m48ssidae/usb_config.c index 053f59fed..79ae70d77 100644 --- a/source/hic_hal/nuvoton/m48ssidae/usb_config.c +++ b/source/hic_hal/nuvoton/m48ssidae/usb_config.c @@ -68,7 +68,11 @@ // when the device is fully operational (bMaxPower) // #define USBD_CFGDESC_BMATTRIBUTES 0x80 +#if !defined(BOARD_USB_BMAXPOWER) #define USBD_CFGDESC_BMAXPOWER 0xFA +#else +#define USBD_CFGDESC_BMAXPOWER BOARD_USB_BMAXPOWER +#endif // String Settings // These settings affect String Descriptor diff --git a/source/hic_hal/nxp/lpc11u35/usb_config.c b/source/hic_hal/nxp/lpc11u35/usb_config.c index 9e6233b6c..56a3ef7de 100644 --- a/source/hic_hal/nxp/lpc11u35/usb_config.c +++ b/source/hic_hal/nxp/lpc11u35/usb_config.c @@ -68,7 +68,11 @@ // when the device is fully operational (bMaxPower) // #define USBD_CFGDESC_BMATTRIBUTES 0x80 +#if !defined(BOARD_USB_BMAXPOWER) #define USBD_CFGDESC_BMAXPOWER 0xFA +#else +#define USBD_CFGDESC_BMAXPOWER BOARD_USB_BMAXPOWER +#endif // String Settings // These settings affect String Descriptor diff --git a/source/hic_hal/nxp/lpc4322/usb_config.c b/source/hic_hal/nxp/lpc4322/usb_config.c index f816f800c..9b8dde6c1 100644 --- a/source/hic_hal/nxp/lpc4322/usb_config.c +++ b/source/hic_hal/nxp/lpc4322/usb_config.c @@ -77,7 +77,11 @@ // when the device is fully operational (bMaxPower) // #define USBD_CFGDESC_BMATTRIBUTES 0x80 +#if !defined(BOARD_USB_BMAXPOWER) #define USBD_CFGDESC_BMAXPOWER 0xFA +#else +#define USBD_CFGDESC_BMAXPOWER BOARD_USB_BMAXPOWER +#endif // String Settings // These settings affect String Descriptor diff --git a/source/hic_hal/stm32/stm32f103xb/usb_config.c b/source/hic_hal/stm32/stm32f103xb/usb_config.c index 0e70ae95d..354b57ae0 100644 --- a/source/hic_hal/stm32/stm32f103xb/usb_config.c +++ b/source/hic_hal/stm32/stm32f103xb/usb_config.c @@ -68,7 +68,11 @@ // when the device is fully operational (bMaxPower) // #define USBD_CFGDESC_BMATTRIBUTES 0x80 +#if !defined(BOARD_USB_BMAXPOWER) #define USBD_CFGDESC_BMAXPOWER 0xFA +#else +#define USBD_CFGDESC_BMAXPOWER BOARD_USB_BMAXPOWER +#endif // String Settings // These settings affect String Descriptor From 046f2a5651e572b007a121bc1c1f5e613cd6a48d Mon Sep 17 00:00:00 2001 From: Russ Butler Date: Fri, 13 Aug 2021 14:16:01 -0500 Subject: [PATCH 265/617] Fix unterminated comment on kl27z GCC Fix GCC builds by closing the unterminated comment in startup_MKL27Z4.S. --- source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S b/source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S index 1c670491e..b3c1af858 100644 --- a/source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S +++ b/source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S @@ -77,7 +77,7 @@ __isr_vector: .size __isr_vector, . - __isr_vector #if defined(DAPLINK_BL) - /* TODO: Bootloader Configuration Area (BCA) used by Kinetis ROM Bootloader + /* TODO: Bootloader Configuration Area (BCA) used by Kinetis ROM Bootloader */ #endif /* Flash Configuration */ From 0bdc48e7be5b5e6e8eed9c2a7ac1e28fddc6c5f1 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Thu, 19 Aug 2021 13:59:37 -0500 Subject: [PATCH 266/617] Updates after review: Consider BOARD_EXTRA_BUFFER in sector offset calculation Follow ADIv6 for powering down the debug interface Add comment to .yaml file on DELAY_FAST_CYCLES Don't erase target image if incompatible image is enabled and triggered. --- records/board/microbitv2.yaml | 2 +- source/daplink/drag-n-drop/flash_decoder.c | 3 --- source/daplink/drag-n-drop/vfs_user.c | 3 ++- source/daplink/interface/swd_host.c | 20 ++++++++++++++++++-- 4 files changed, 21 insertions(+), 7 deletions(-) diff --git a/records/board/microbitv2.yaml b/records/board/microbitv2.yaml index 1d67d7b59..2c6e5960c 100644 --- a/records/board/microbitv2.yaml +++ b/records/board/microbitv2.yaml @@ -5,7 +5,7 @@ common: - MSC_LED_DEF=GPIO_LED_ON - USB_PROD_STR="BBC micro:bit CMSIS-DAP" - IO_CONFIG_OVERRIDE - - DELAY_FAST_CYCLES=2U + - DELAY_FAST_CYCLES=2U # Fast delay needed to reach 8MHz SWD clock speed - DAP_DEFAULT_SWJ_CLOCK=8000000 - BOARD_USB_BMAXPOWER=0x96 - BOARD_EXTRA_BUFFER=100 diff --git a/source/daplink/drag-n-drop/flash_decoder.c b/source/daplink/drag-n-drop/flash_decoder.c index ce7109fd1..46b4bc7ae 100644 --- a/source/daplink/drag-n-drop/flash_decoder.c +++ b/source/daplink/drag-n-drop/flash_decoder.c @@ -199,9 +199,6 @@ error_t flash_decoder_validate_target_image(flash_decoder_type_t type, const uin if (g_board_info.target_cfg) { if (board_detect_incompatible_image(data, size)){ status = ERROR_FD_INCOMPATIBLE_IMAGE; - flash_intf_target->init(); - flash_intf_target->erase_chip(); - flash_intf_target->uninit(); } else { status = ERROR_SUCCESS; } diff --git a/source/daplink/drag-n-drop/vfs_user.c b/source/daplink/drag-n-drop/vfs_user.c index b92790f0d..bbbcf9e8b 100644 --- a/source/daplink/drag-n-drop/vfs_user.c +++ b/source/daplink/drag-n-drop/vfs_user.c @@ -355,7 +355,8 @@ static uint32_t read_file_details_txt(uint32_t sector_offset, uint8_t *data, uin { uint32_t size = 0; - if (sector_offset > 1) { + // Check that sector is valid depending on file_buffer size + if (sector_offset > (VFS_SECTOR_SIZE + BOARD_EXTRA_BUFFER - 1) / VFS_SECTOR_SIZE) { return 0; } diff --git a/source/daplink/interface/swd_host.c b/source/daplink/interface/swd_host.c index 1e51ee319..d98fa2c64 100644 --- a/source/daplink/interface/swd_host.c +++ b/source/daplink/interface/swd_host.c @@ -1053,7 +1053,23 @@ uint8_t swd_set_target_state_sw(target_state_t state) osDelay(2); // Power down - if (!swd_write_dp(DP_CTRL_STAT, 0x0)) { + // Per ADIv6 spec. Clear first CSYSPWRUPREQ followed by CDBGPWRUPREQ + if (!swd_read_dp(DP_CTRL_STAT, &val)) { + return 0; + } + + if (!swd_write_dp(DP_CTRL_STAT, val & ~CSYSPWRUPREQ)) { + return 0; + } + + // Wait until ACK is deasserted + do { + if (!swd_read_dp(DP_CTRL_STAT, &val)) { + return 0; + } + } while ((val & (CSYSPWRUPACK)) == 1); + + if (!swd_write_dp(DP_CTRL_STAT, val & ~CDBGPWRUPREQ)) { return 0; } @@ -1062,7 +1078,7 @@ uint8_t swd_set_target_state_sw(target_state_t state) if (!swd_read_dp(DP_CTRL_STAT, &val)) { return 0; } - } while ((val & (CSYSPWRUPACK | CDBGPWRUPACK)) == 1); + } while ((val & (CDBGPWRUPACK)) == 1); swd_off(); break; From fd42dbddd134e6e6cc1f017368ba4952c8ea180f Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 20 Aug 2021 12:53:21 -0500 Subject: [PATCH 267/617] Revert version to 0256 --- records/tools/version.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/records/tools/version.yaml b/records/tools/version.yaml index f217dddb0..e76642cb8 100644 --- a/records/tools/version.yaml +++ b/records/tools/version.yaml @@ -1,3 +1,3 @@ common: macros: - - DAPLINK_VERSION=257 + - DAPLINK_VERSION=256 From d9cff962722883135dd99598759ed1a93e246681 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 9 Sep 2021 21:54:53 -0500 Subject: [PATCH 268/617] armclang: configuration section interferes with bin/hex files generation --- source/daplink/daplink.ac6.sct | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/source/daplink/daplink.ac6.sct b/source/daplink/daplink.ac6.sct index c6bbe86c3..09c291cfe 100644 --- a/source/daplink/daplink.ac6.sct +++ b/source/daplink/daplink.ac6.sct @@ -53,8 +53,8 @@ LR_IROM1 DAPLINK_ROM_APP_START DAPLINK_ROM_APP_SIZE { } } -LR_CONFIG DAPLINK_ROM_CONFIG_USER_START DAPLINK_ROM_CONFIG_USER_SIZE { ; reserve last sector for config data - ER_CONFIG DAPLINK_ROM_CONFIG_USER_START UNINIT DAPLINK_ROM_CONFIG_USER_SIZE { - .ANY (cfgrom) - } -} +; LR_CONFIG DAPLINK_ROM_CONFIG_USER_START DAPLINK_ROM_CONFIG_USER_SIZE { ; reserve last sector for config data +; ER_CONFIG DAPLINK_ROM_CONFIG_USER_START UNINIT DAPLINK_ROM_CONFIG_USER_SIZE { +; .ANY (cfgrom) +; } +; } From 257033e657914739d60dbef633623044adc332eb Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 6 Aug 2021 12:33:09 +0200 Subject: [PATCH 269/617] Make compact build description in DETAILS.TXT to save space (#719) --- source/daplink/drag-n-drop/vfs_user.c | 39 ++++++++++++++------------- tools/pre_build_script.py | 13 +++++++-- 2 files changed, 31 insertions(+), 21 deletions(-) diff --git a/source/daplink/drag-n-drop/vfs_user.c b/source/daplink/drag-n-drop/vfs_user.c index bbbcf9e8b..b963e5436 100644 --- a/source/daplink/drag-n-drop/vfs_user.c +++ b/source/daplink/drag-n-drop/vfs_user.c @@ -4,7 +4,7 @@ * * DAPLink Interface Firmware * Copyright (c) 2009-2020, ARM Limited, All Rights Reserved - * Copyright 2019, Cypress Semiconductor Corporation + * Copyright 2019, Cypress Semiconductor Corporation * or a subsidiary of Cypress Semiconductor Corporation. * SPDX-License-Identifier: Apache-2.0 * @@ -497,6 +497,20 @@ static uint32_t update_html_file(uint8_t *data, uint32_t datasize) return expand_info(data, datasize); } +#if defined(__CC_ARM) +#define COMPILER_DESCRIPTION "armcc" +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +#define COMPILER_DESCRIPTION "armclang" +#elif defined(__GNUC__) +#define COMPILER_DESCRIPTION "gcc" +#endif + +#if (GIT_LOCAL_MODS) +#define LOCAL_MODS ", local mods" +#else +#define LOCAL_MODS "" +#endif + static uint32_t update_details_txt_file(uint8_t *data, uint32_t datasize) { uint32_t pos=0; @@ -504,10 +518,13 @@ static uint32_t update_details_txt_file(uint8_t *data, uint32_t datasize) char *buf = (char *)data; - //Needed by expand_info strlen + // Needed by expand_info strlen memset(buf, 0, datasize); pos += util_write_string(buf + pos, "# DAPLink Firmware - see https://mbed.com/daplink\r\n"); + // Build ID + pos += util_write_string(buf + pos, "Build ID: " GIT_DESCRIPTION \ + " (" COMPILER_DESCRIPTION LOCAL_MODS ")\r\n"); // Unique ID pos += util_write_string(buf + pos, "Unique ID: @U\r\n"); // HIC ID @@ -550,22 +567,6 @@ static uint32_t update_details_txt_file(uint8_t *data, uint32_t datasize) pos += util_write_string(buf + pos, "\r\n"); } -#if defined(__CC_ARM) - pos += util_write_string(buf + pos, "Compiler: armcc\r\n"); -#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - pos += util_write_string(buf + pos, "Compiler: armclang\r\n"); -#elif defined(__GNUC__) - pos += util_write_string(buf + pos, "Compiler: gcc\r\n"); -#endif - - // GIT sha - pos += util_write_string(buf + pos, "Git SHA: "); - pos += util_write_string(buf + pos, GIT_COMMIT_SHA); - pos += util_write_string(buf + pos, "\r\n"); - // Local modifications when making the build - pos += util_write_string(buf + pos, "Local Mods: "); - pos += util_write_uint32(buf + pos, GIT_LOCAL_MODS); - pos += util_write_string(buf + pos, "\r\n"); // Supported USB endpoints pos += util_write_string(buf + pos, "USB Interfaces: "); #ifdef MSC_ENDPOINT @@ -599,7 +600,7 @@ static uint32_t update_details_txt_file(uint8_t *data, uint32_t datasize) pos += util_write_uint32(buf + pos, remount_count); pos += util_write_string(buf + pos, "\r\n"); - //Target URL + // Target URL pos += util_write_string(buf + pos, "URL: @R\r\n"); return expand_info(data, datasize); diff --git a/tools/pre_build_script.py b/tools/pre_build_script.py index 2046a6e08..37ae5e83f 100755 --- a/tools/pre_build_script.py +++ b/tools/pre_build_script.py @@ -48,6 +48,7 @@ #ifndef VERSION_GIT_H #define VERSION_GIT_H +#define GIT_DESCRIPTION \"%s\" #define GIT_COMMIT_SHA \"%s\" #define GIT_LOCAL_MODS %d @@ -59,6 +60,15 @@ def generate_version_file(version_git_dir): + # Get the git description. + print("#> Getting git description") + try: + git_description = check_output("git describe HEAD", shell=True) + git_description = git_description.decode().strip() + except: + print("#> ERROR: Failed to get git description, do you have git.exe in your PATH environment variable?") + return 1 + output_file = os.path.join(os.path.normpath(version_git_dir),'version_git.h') print("#> Pre-build script start") @@ -80,9 +90,8 @@ def generate_version_file(version_git_dir): else: git_has_changes = 0 - # Create the version file. Only overwrite an existing file if it changes. - version_text = VERSION_GIT_FILE_TEMPLATE % (git_sha, git_has_changes) + version_text = VERSION_GIT_FILE_TEMPLATE % (git_description, git_sha, git_has_changes) try: with open(output_file, 'r') as version_file: current_version_text = version_file.read() From 6b64de6ca4c8384b13b9c3b7ae6c547326741c98 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 13 Aug 2021 01:29:20 +0200 Subject: [PATCH 270/617] Rewrite VFS read() methods to support multiple sectors Size can be determined without a full-sized buffer --- source/daplink/drag-n-drop/vfs_user.c | 288 +++++++++++++------------- source/daplink/util.c | 29 +++ source/daplink/util.h | 5 + 3 files changed, 178 insertions(+), 144 deletions(-) diff --git a/source/daplink/drag-n-drop/vfs_user.c b/source/daplink/drag-n-drop/vfs_user.c index b963e5436..cc7459da9 100644 --- a/source/daplink/drag-n-drop/vfs_user.c +++ b/source/daplink/drag-n-drop/vfs_user.c @@ -83,21 +83,6 @@ typedef struct _magic_file_info { magic_file_t which; //!< Enum for the file. } magic_file_info_t; -static const char mbed_redirect_file[] = - "\r\n" - "\r\n" - "\r\n" - "\r\n" - "\r\n" - "mbed Website Shortcut\r\n" - "\r\n" - "\r\n" - "\r\n" - "\r\n" - "\r\n"; - static const char error_prefix[] = "error: "; static const char error_type_prefix[] = "type: "; @@ -123,7 +108,6 @@ static const magic_file_info_t s_magic_file_info[] = { { "PAGE_OFFACT", kChipEraseActionFile }, }; -static uint8_t file_buffer[VFS_SECTOR_SIZE+BOARD_EXTRA_BUFFER]; static char assert_buf[64 + 1]; static uint16_t assert_line; static assert_source_t assert_source; @@ -138,7 +122,7 @@ static uint32_t read_file_assert_txt(uint32_t sector_offset, uint8_t *data, uint static uint32_t read_file_need_bl_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors); static uint32_t update_html_file(uint8_t *data, uint32_t datasize); -static uint32_t update_details_txt_file(uint8_t *data, uint32_t datasize); +static uint32_t update_details_txt_file(uint8_t *data, uint32_t datasize, uint32_t start); static void erase_target(void); static uint32_t expand_info(uint8_t *buf, uint32_t bufsize); @@ -184,7 +168,7 @@ void vfs_user_build_filesystem() file_size = get_file_size(read_file_need_bl_txt); vfs_create_file("NEED_BL TXT", read_file_need_bl_txt, 0, file_size); } - + vfs_user_build_filesystem_hook(); } @@ -337,39 +321,70 @@ void vfs_user_disconnecting() static uint32_t get_file_size(vfs_read_cb_t read_func) { // Determine size of the file by faking a read - return read_func(0, file_buffer, 1); + return read_func(0, NULL, 0); } -// File callback to be used with vfs_add_file to return file contents -static uint32_t read_file_mbed_htm(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors) -{ - if (sector_offset != 0) { - return 0; +#ifndef EXPANSION_BUFFER_SIZE +#define EXPANSION_BUFFER_SIZE 128 +#endif + +uint32_t expand_string_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, uint8_t *input) { + uint8_t str_buf[EXPANSION_BUFFER_SIZE]; + memset(str_buf, 0, sizeof(str_buf)); + for(uint32_t i = 0; (i < (sizeof(str_buf) - 1)) && 0 != input[i]; i++) { + str_buf[i] = input[i]; } + uint32_t l = expand_info(str_buf, sizeof(str_buf)); - return update_html_file(data, VFS_SECTOR_SIZE); + return util_write_in_region(buf, size, start, pos, str_buf, l); +} + +uint32_t setting_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, uint8_t *label, uint32_t boolean) { + uint32_t l = util_write_string_in_region(buf, size, start, pos, label); + if (boolean) { + l += util_write_in_region(buf, size, start, pos + l, ": 1\r\n", 5); + } else { + l += util_write_in_region(buf, size, start, pos + l, ": 0\r\n", 5); + } + return l; } + // File callback to be used with vfs_add_file to return file contents -static uint32_t read_file_details_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors) +static uint32_t read_file_mbed_htm(uint32_t sector_offset, uint8_t *buf, uint32_t num_sectors) { - uint32_t size = 0; + uint32_t start = sector_offset * VFS_SECTOR_SIZE; + uint32_t size = num_sectors * VFS_SECTOR_SIZE; + uint32_t pos = 0; - // Check that sector is valid depending on file_buffer size - if (sector_offset > (VFS_SECTOR_SIZE + BOARD_EXTRA_BUFFER - 1) / VFS_SECTOR_SIZE) { + if ((sector_offset != 0) && (buf != NULL)) { return 0; } - - size = update_details_txt_file(file_buffer, VFS_SECTOR_SIZE+BOARD_EXTRA_BUFFER); - - if (size - VFS_SECTOR_SIZE * sector_offset > VFS_SECTOR_SIZE) { - memcpy(data, file_buffer + sector_offset * VFS_SECTOR_SIZE, VFS_SECTOR_SIZE); - } - else { - memcpy(data, file_buffer + sector_offset * VFS_SECTOR_SIZE, size - VFS_SECTOR_SIZE * sector_offset); - } - return size; + pos += util_write_string_in_region(buf, size, start, pos, + "\r\n" + "\r\n" + "\r\n" + "\r\n" + "\r\n" + "mbed Website Shortcut\r\n" + "\r\n" + "\r\n" + "\r\n" + "\r\n" + "\r\n"); + + return pos; +} + +// File callback to be used with vfs_add_file to return file contents +static uint32_t read_file_details_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors) +{ + return update_details_txt_file(data, num_sectors * VFS_SECTOR_SIZE, sector_offset * VFS_SECTOR_SIZE); } // Text representation of each error type, starting from the rightmost bit @@ -384,58 +399,58 @@ static const char* const error_type_names[] = { COMPILER_ASSERT(1 << ARRAY_SIZE(error_type_names) == ERROR_TYPE_MASK + 1); // File callback to be used with vfs_add_file to return file contents -static uint32_t read_file_fail_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors) +static uint32_t read_file_fail_txt(uint32_t sector_offset, uint8_t *buf, uint32_t num_sectors) { - uint32_t size = 0; - char *buf = (char *)data; + uint32_t start = sector_offset * VFS_SECTOR_SIZE; + uint32_t size = num_sectors * VFS_SECTOR_SIZE; + uint32_t pos = 0; error_t status = vfs_mngr_get_transfer_status(); const char *contents = error_get_string(status); error_type_t type = error_get_type(status); - if (sector_offset != 0) { + if ((sector_offset != 0) && (buf != NULL)) { return 0; } - size += util_write_string(buf + size, error_prefix); - size += util_write_string(buf + size, contents); - size += util_write_string(buf + size, "\r\n"); - size += util_write_string(buf + size, error_type_prefix); + pos += util_write_string_in_region(buf, size, start, pos, error_prefix); + pos += util_write_string_in_region(buf, size, start, pos, contents); + pos += util_write_in_region(buf, size, start, pos, "\r\n", 2); + pos += util_write_string_in_region(buf, size, start, pos, error_type_prefix); // Write each applicable error type, separated by commas int index = 0; bool first = true; while (type && index < ARRAY_SIZE(error_type_names)) { if (!first) { - size += util_write_string(buf + size, ", "); + pos += util_write_in_region(buf, size, start, pos, ", ", 2); } if (type & 1) { - size += util_write_string(buf + size, error_type_names[index]); + pos += util_write_string_in_region(buf, size, start, pos, error_type_names[index]); first = false; } index++; type >>= 1; } - size += util_write_string(buf + size, "\r\n"); - return size; + pos += util_write_in_region(buf, size, start, pos, "\r\n", 2); + return pos; } // File callback to be used with vfs_add_file to return file contents -static uint32_t read_file_assert_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors) +static uint32_t read_file_assert_txt(uint32_t sector_offset, uint8_t *buf, uint32_t num_sectors) { - uint32_t pos; + uint32_t start = sector_offset * VFS_SECTOR_SIZE; + uint32_t size = num_sectors * VFS_SECTOR_SIZE; + uint32_t pos = 0; const char *source_str; - char *buf = (char *)data; uint32_t * hexdumps = 0; uint8_t valid_hexdumps = 0; uint8_t index = 0; - if (sector_offset != 0) { + if ((sector_offset != 0) && (buf != NULL)) { return 0; } - pos = 0; - if (ASSERT_SOURCE_BL == assert_source) { source_str = "Bootloader"; } else if (ASSERT_SOURCE_APP == assert_source) { @@ -444,27 +459,30 @@ static uint32_t read_file_assert_txt(uint32_t sector_offset, uint8_t *data, uint source_str = 0; } - pos += util_write_string(buf + pos, "Assert\r\n"); - pos += util_write_string(buf + pos, "File: "); - pos += util_write_string(buf + pos, assert_buf); - pos += util_write_string(buf + pos, "\r\n"); - pos += util_write_string(buf + pos, "Line: "); - pos += util_write_uint32(buf + pos, assert_line); - pos += util_write_string(buf + pos, "\r\n"); + pos += util_write_string_in_region(buf, size, start, pos, "Assert\r\n"); + pos += util_write_string_in_region(buf, size, start, pos, "File: "); + pos += util_write_string_in_region(buf, size, start, pos, assert_buf); + pos += util_write_string_in_region(buf, size, start, pos, "\r\n"); + pos += util_write_string_in_region(buf, size, start, pos, "Line: "); + uint8_t lineno[10]; + uint32_t digits = util_write_uint32(lineno, assert_line); + pos += util_write_in_region(buf, size, start, pos, lineno, digits); + pos += util_write_string_in_region(buf, size, start, pos, "\r\n"); if (source_str != 0) { - pos += util_write_string(buf + pos, "Source: "); - pos += util_write_string(buf + pos, source_str); - pos += util_write_string(buf + pos, "\r\n"); + pos += util_write_string_in_region(buf, size, start, pos, "Source: "); + pos += util_write_string_in_region(buf, size, start, pos, source_str); + pos += util_write_string_in_region(buf, size, start, pos, "\r\n"); } valid_hexdumps = config_ram_get_hexdumps(&hexdumps); if ((valid_hexdumps > 0) && (hexdumps != 0)) { //print hexdumps - pos += util_write_string(buf + pos, "Hexdumps\r\n"); + pos += util_write_string_in_region(buf, size, start, pos, "Hexdumps\r\n"); while ((index < valid_hexdumps) && ((pos + 10) < VFS_SECTOR_SIZE)) { //hexdumps + newline is always 10 characters - pos += util_write_hex32(buf + pos, hexdumps[index++]); - pos += util_write_string(buf + pos, "\r\n"); + uint8_t hex[10] = { 0, 0, 0, 0, 0, 0, 0, 0, '\r', '\n' }; + util_write_hex32(hex, hexdumps[index++]); + pos += util_write_in_region(buf, size, start, pos, hex, 10); } } @@ -478,25 +496,17 @@ static uint32_t read_file_need_bl_txt(uint32_t sector_offset, uint8_t *data, uin "Reload the bootloader to fix this error message.\r\n"; uint32_t size = strlen(contents); - if (sector_offset != 0) { - return 0; + if (data != NULL) { + if (sector_offset != 0) { + return 0; + } + + memcpy(data, contents, size); } - memcpy(data, contents, size); return size; } - -static uint32_t update_html_file(uint8_t *data, uint32_t datasize) -{ - char *buf = (char *)data; - //Needed by expand_info strlen - memset(buf, 0, datasize); - memcpy(buf, mbed_redirect_file, strlen(mbed_redirect_file)); - //expand - return expand_info(data, datasize); -} - #if defined(__CC_ARM) #define COMPILER_DESCRIPTION "armcc" #elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) @@ -511,99 +521,89 @@ static uint32_t update_html_file(uint8_t *data, uint32_t datasize) #define LOCAL_MODS "" #endif -static uint32_t update_details_txt_file(uint8_t *data, uint32_t datasize) +static uint32_t update_details_txt_file(uint8_t *buf, uint32_t size, uint32_t start) { - uint32_t pos=0; - const char *mode_str; - - char *buf = (char *)data; - - // Needed by expand_info strlen - memset(buf, 0, datasize); + uint32_t pos = 0; - pos += util_write_string(buf + pos, "# DAPLink Firmware - see https://mbed.com/daplink\r\n"); + pos += util_write_string_in_region(buf, size, start, pos, "# DAPLink Firmware - see https://mbed.com/daplink\r\n"); // Build ID - pos += util_write_string(buf + pos, "Build ID: " GIT_DESCRIPTION \ + pos += util_write_string_in_region(buf, size, start, pos, "Build ID: " GIT_DESCRIPTION \ " (" COMPILER_DESCRIPTION LOCAL_MODS ")\r\n"); // Unique ID - pos += util_write_string(buf + pos, "Unique ID: @U\r\n"); + pos += expand_string_in_region(buf, size, start, pos, "Unique ID: @U\r\n"); // HIC ID - pos += util_write_string(buf + pos, "HIC ID: @D\r\n"); + pos += expand_string_in_region(buf, size, start, pos, "HIC ID: @D\r\n"); // Settings - pos += util_write_string(buf + pos, "Auto Reset: "); - pos += util_write_string(buf + pos, config_get_auto_rst() ? "1" : "0"); - pos += util_write_string(buf + pos, "\r\n"); - pos += util_write_string(buf + pos, "Automation allowed: "); - pos += util_write_string(buf + pos, config_get_automation_allowed() ? "1" : "0"); - pos += util_write_string(buf + pos, "\r\n"); - pos += util_write_string(buf + pos, "Overflow detection: "); - pos += util_write_string(buf + pos, config_get_overflow_detect() ? "1" : "0"); - pos += util_write_string(buf + pos, "\r\n"); - pos += util_write_string(buf + pos, "Incompatible image detection: "); - pos += util_write_string(buf + pos, config_get_detect_incompatible_target() ? "1" : "0"); - pos += util_write_string(buf + pos, "\r\n"); - pos += util_write_string(buf + pos, "Page erasing: "); - pos += util_write_string(buf + pos, config_ram_get_page_erase() ? "1" : "0"); - pos += util_write_string(buf + pos, "\r\n"); - // Current mode - mode_str = daplink_is_bootloader() ? "Bootloader" : "Interface"; - pos += util_write_string(buf + pos, "Daplink Mode: "); - pos += util_write_string(buf + pos, mode_str); - pos += util_write_string(buf + pos, "\r\n"); - // Current build's version - pos += util_write_string(buf + pos, mode_str); - pos += util_write_string(buf + pos, " Version: @V\r\n"); + pos += setting_in_region(buf, size, start, pos, "Auto Reset", config_get_auto_rst()); + pos += setting_in_region(buf, size, start, pos, "Automation allowed", config_get_automation_allowed()); + pos += setting_in_region(buf, size, start, pos, "Overflow detection", config_get_overflow_detect()); + pos += setting_in_region(buf, size, start, pos, "Incompatible image detection", config_get_detect_incompatible_target()); + pos += setting_in_region(buf, size, start, pos, "Page erasing", config_ram_get_page_erase()); + // Current mode and version + if(daplink_is_bootloader()) { + pos += util_write_string_in_region(buf, size, start, pos, "Daplink Mode: Bootloader\r\n"); + pos += expand_string_in_region(buf, size, start, pos, "Bootloader Version: @V\r\n"); + } else { + pos += util_write_string_in_region(buf, size, start, pos, "Daplink Mode: Interface\r\n"); + pos += expand_string_in_region(buf, size, start, pos, "Interface Version: @V\r\n"); + } // Other builds version (bl or if) if (!daplink_is_bootloader() && info_get_bootloader_present()) { - pos += util_write_string(buf + pos, "Bootloader Version: "); - pos += util_write_uint32_zp(buf + pos, info_get_bootloader_version(), 4); - pos += util_write_string(buf + pos, "\r\n"); + uint8_t version[6] = { 0, 0, 0, 0, '\r', '\n' }; + pos += util_write_string_in_region(buf, size, start, pos, "Bootloader Version: "); + util_write_uint32_zp(version, info_get_bootloader_version(), 4); + pos += util_write_in_region(buf, size, start, pos, version, 6); } if (!daplink_is_interface() && info_get_interface_present()) { - pos += util_write_string(buf + pos, "Interface Version: "); - pos += util_write_uint32_zp(buf + pos, info_get_interface_version(), 4); - pos += util_write_string(buf + pos, "\r\n"); + uint8_t version[6] = { 0, 0, 0, 0, '\r', '\n' }; + pos += util_write_string_in_region(buf, size, start, pos, "Interface Version: "); + util_write_uint32_zp(version, info_get_interface_version(), 4); + pos += util_write_in_region(buf, size, start, pos, version, 6); } // Supported USB endpoints - pos += util_write_string(buf + pos, "USB Interfaces: "); + pos += util_write_string_in_region(buf, size, start, pos, "USB Interfaces: " #ifdef MSC_ENDPOINT - pos += util_write_string(buf + pos, "MSD"); + "MSD" #endif #ifdef CDC_ENDPOINT - pos += util_write_string(buf + pos, ", CDC"); + ", CDC" #endif #ifdef HID_ENDPOINT - pos += util_write_string(buf + pos, ", HID"); + ", HID" #endif #if (WEBUSB_INTERFACE) - pos += util_write_string(buf + pos, ", WebUSB"); + ", WebUSB" #endif - pos += util_write_string(buf + pos, "\r\n"); + "\r\n" + ); + uint8_t crc[10] = { 0, 0, 0, 0, 0, 0, 0, 0, '\r', '\n' }; // CRC of the bootloader (if there is one) if (info_get_bootloader_present()) { - pos += util_write_string(buf + pos, "Bootloader CRC: 0x"); - pos += util_write_hex32(buf + pos, info_get_crc_bootloader()); - pos += util_write_string(buf + pos, "\r\n"); + pos += util_write_string_in_region(buf, size, start, pos, "Bootloader CRC: 0x"); + util_write_hex32(crc, info_get_crc_bootloader()); + pos += util_write_in_region(buf, size, start, pos, crc, 10); } - // CRC of the interface - pos += util_write_string(buf + pos, "Interface CRC: 0x"); - pos += util_write_hex32(buf + pos, info_get_crc_interface()); - pos += util_write_string(buf + pos, "\r\n"); + pos += util_write_string_in_region(buf, size, start, pos, "Interface CRC: 0x"); + util_write_hex32(crc, info_get_crc_interface()); + pos += util_write_in_region(buf, size, start, pos, crc, 10); // Number of remounts that have occurred - pos += util_write_string(buf + pos, "Remount count: "); - pos += util_write_uint32(buf + pos, remount_count); - pos += util_write_string(buf + pos, "\r\n"); + uint8_t count[12]; + pos += util_write_string_in_region(buf, size, start, pos, "Remount count: "); + uint32_t digits = util_write_uint32(count, remount_count); + count[digits++] = '\r'; + count[digits++] = '\n'; + pos += util_write_in_region(buf, size, start, pos, count, digits); - // Target URL - pos += util_write_string(buf + pos, "URL: @R\r\n"); + //Target URL + pos += expand_string_in_region(buf, size, start, pos, "URL: @R\r\n"); - return expand_info(data, datasize); + return pos; } // Fill buf with the contents of the mbed redirect file by diff --git a/source/daplink/util.c b/source/daplink/util.c index 9caf0fdbb..1025b4b8c 100644 --- a/source/daplink/util.c +++ b/source/daplink/util.c @@ -110,6 +110,35 @@ uint32_t util_write_string(char *str, const char *data) return pos; } +uint32_t util_write_string_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, const uint8_t *input) { + uint32_t length = strlen(input); + + return util_write_in_region(buf, size, start, pos, input, length); +} + +uint32_t util_write_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, const uint8_t *input, uint32_t length) { + if (buf != NULL) { + // Check if there is something to copy + if (((pos + length) >= start) && (pos <= (start + size))) { + uint32_t i_off = 0; + uint32_t o_off = 0; + uint32_t l = length; + if (pos < start) { + i_off = start - pos; + l -= i_off; + } else { + o_off = pos - start; + } + if ((pos + length) > (start + size)) { + l -= (pos + length) - (start + size); + } + memcpy(buf + o_off, input + i_off, l); + } + } + + return length; +} + void _util_assert(bool expression, const char *filename, uint16_t line) { bool assert_set; diff --git a/source/daplink/util.h b/source/daplink/util.h index a8e3fc932..5e1d5df95 100644 --- a/source/daplink/util.h +++ b/source/daplink/util.h @@ -66,6 +66,11 @@ uint32_t util_write_uint32(char *str, uint32_t value); uint32_t util_write_uint32_zp(char *str, uint32_t value, uint16_t total_size); uint32_t util_write_string(char *str, const char *data); +uint32_t util_write_in_region(uint8_t *buf, uint32_t size, uint32_t start, + uint32_t pos, const uint8_t *input, uint32_t length); +uint32_t util_write_string_in_region(uint8_t *buf, uint32_t size, uint32_t start, + uint32_t pos, const uint8_t *input); + __STATIC_INLINE uint32_t util_div_round_up(uint32_t dividen, uint32_t divisor) { return (dividen + divisor - 1) / divisor; From 0a2212b45def5782209c1d44cc0adb111d8d0b69 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 13 Aug 2021 02:55:53 +0200 Subject: [PATCH 271/617] Some factorization in VFS file generation to reduce code size --- source/daplink/drag-n-drop/vfs_user.c | 97 ++++++++++++++------------- 1 file changed, 52 insertions(+), 45 deletions(-) diff --git a/source/daplink/drag-n-drop/vfs_user.c b/source/daplink/drag-n-drop/vfs_user.c index cc7459da9..c2ecbf77f 100644 --- a/source/daplink/drag-n-drop/vfs_user.c +++ b/source/daplink/drag-n-drop/vfs_user.c @@ -83,9 +83,6 @@ typedef struct _magic_file_info { magic_file_t which; //!< Enum for the file. } magic_file_info_t; -static const char error_prefix[] = "error: "; -static const char error_type_prefix[] = "type: "; - static const vfs_filename_t assert_file = "ASSERT TXT"; //! @brief Table of magic files and their names. @@ -349,6 +346,31 @@ uint32_t setting_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t return l; } +uint32_t string_field_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, uint8_t *label, const uint8_t *value) { + uint32_t l = util_write_string_in_region(buf, size, start, pos, label); + l += util_write_in_region(buf, size, start, pos + l, ": ", 2); + l += util_write_string_in_region(buf, size, start, pos, value); + l += util_write_in_region(buf, size, start, pos + l, "\r\n", 2); + return l; +} + +uint32_t uint32_field_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, uint8_t *label, uint32_t value) { + uint8_t number[14] = {':', ' '}; + uint32_t l = util_write_string_in_region(buf, size, start, pos, label); + uint32_t digits = util_write_uint32(number + 2, value) + 2; + number[digits++] = '\r'; + number[digits++] = '\n'; + l += util_write_in_region(buf, size, start, pos + l, number, digits); + return l; +} + +uint32_t hex32_field_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, uint8_t *label, uint32_t value) { + uint8_t hex[14] = { ':', ' ', '0', 'x', 0, 0, 0, 0, 0, 0, 0, 0, '\r', '\n' }; + uint32_t l = util_write_string_in_region(buf, size, start, pos, label); + util_write_hex32(hex + 4, value); + l += util_write_in_region(buf, size, start, pos + l, hex, sizeof(hex)); + return l; +} // File callback to be used with vfs_add_file to return file contents static uint32_t read_file_mbed_htm(uint32_t sector_offset, uint8_t *buf, uint32_t num_sectors) @@ -412,10 +434,8 @@ static uint32_t read_file_fail_txt(uint32_t sector_offset, uint8_t *buf, uint32_ return 0; } - pos += util_write_string_in_region(buf, size, start, pos, error_prefix); - pos += util_write_string_in_region(buf, size, start, pos, contents); - pos += util_write_in_region(buf, size, start, pos, "\r\n", 2); - pos += util_write_string_in_region(buf, size, start, pos, error_type_prefix); + pos += string_field_in_region(buf, size, start, pos, "error", contents); + pos += util_write_string_in_region(buf, size, start, pos, "type: "); // Write each applicable error type, separated by commas int index = 0; @@ -460,19 +480,11 @@ static uint32_t read_file_assert_txt(uint32_t sector_offset, uint8_t *buf, uint3 } pos += util_write_string_in_region(buf, size, start, pos, "Assert\r\n"); - pos += util_write_string_in_region(buf, size, start, pos, "File: "); - pos += util_write_string_in_region(buf, size, start, pos, assert_buf); - pos += util_write_string_in_region(buf, size, start, pos, "\r\n"); - pos += util_write_string_in_region(buf, size, start, pos, "Line: "); - uint8_t lineno[10]; - uint32_t digits = util_write_uint32(lineno, assert_line); - pos += util_write_in_region(buf, size, start, pos, lineno, digits); - pos += util_write_string_in_region(buf, size, start, pos, "\r\n"); + pos += string_field_in_region(buf, size, start, pos, "File", assert_buf); + pos += uint32_field_in_region(buf, size, start, pos, "Line", assert_line); if (source_str != 0) { - pos += util_write_string_in_region(buf, size, start, pos, "Source: "); - pos += util_write_string_in_region(buf, size, start, pos, source_str); - pos += util_write_string_in_region(buf, size, start, pos, "\r\n"); + pos += string_field_in_region(buf, size, start, pos, "Source", source_str); } valid_hexdumps = config_ram_get_hexdumps(&hexdumps); @@ -539,29 +551,31 @@ static uint32_t update_details_txt_file(uint8_t *buf, uint32_t size, uint32_t st pos += setting_in_region(buf, size, start, pos, "Overflow detection", config_get_overflow_detect()); pos += setting_in_region(buf, size, start, pos, "Incompatible image detection", config_get_detect_incompatible_target()); pos += setting_in_region(buf, size, start, pos, "Page erasing", config_ram_get_page_erase()); + // Current mode and version - if(daplink_is_bootloader()) { - pos += util_write_string_in_region(buf, size, start, pos, "Daplink Mode: Bootloader\r\n"); - pos += expand_string_in_region(buf, size, start, pos, "Bootloader Version: @V\r\n"); - } else { - pos += util_write_string_in_region(buf, size, start, pos, "Daplink Mode: Interface\r\n"); - pos += expand_string_in_region(buf, size, start, pos, "Interface Version: @V\r\n"); - } +#if defined(DAPLINK_BL) + pos += util_write_string_in_region(buf, size, start, pos, "Daplink Mode: Bootloader\r\n"); + pos += expand_string_in_region(buf, size, start, pos, "Bootloader Version: @V\r\n"); - // Other builds version (bl or if) - if (!daplink_is_bootloader() && info_get_bootloader_present()) { + if (info_get_interface_present()) { uint8_t version[6] = { 0, 0, 0, 0, '\r', '\n' }; - pos += util_write_string_in_region(buf, size, start, pos, "Bootloader Version: "); - util_write_uint32_zp(version, info_get_bootloader_version(), 4); + pos += util_write_string_in_region(buf, size, start, pos, "Interface Version: "); + util_write_uint32_zp(version, info_get_interface_version(), 4); pos += util_write_in_region(buf, size, start, pos, version, 6); } +#elif defined(DAPLINK_IF) + pos += util_write_string_in_region(buf, size, start, pos, "Daplink Mode: Interface\r\n"); + pos += expand_string_in_region(buf, size, start, pos, "Interface Version: @V\r\n"); - if (!daplink_is_interface() && info_get_interface_present()) { +#if DAPLINK_ROM_BL_SIZE != 0 + if (info_get_bootloader_present()) { uint8_t version[6] = { 0, 0, 0, 0, '\r', '\n' }; - pos += util_write_string_in_region(buf, size, start, pos, "Interface Version: "); - util_write_uint32_zp(version, info_get_interface_version(), 4); + pos += util_write_string_in_region(buf, size, start, pos, "Bootloader Version: "); + util_write_uint32_zp(version, info_get_bootloader_version(), 4); pos += util_write_in_region(buf, size, start, pos, version, 6); } +#endif +#endif // Supported USB endpoints pos += util_write_string_in_region(buf, size, start, pos, "USB Interfaces: " @@ -580,25 +594,18 @@ static uint32_t update_details_txt_file(uint8_t *buf, uint32_t size, uint32_t st "\r\n" ); - uint8_t crc[10] = { 0, 0, 0, 0, 0, 0, 0, 0, '\r', '\n' }; +#if DAPLINK_ROM_BL_SIZE != 0 // CRC of the bootloader (if there is one) if (info_get_bootloader_present()) { - pos += util_write_string_in_region(buf, size, start, pos, "Bootloader CRC: 0x"); - util_write_hex32(crc, info_get_crc_bootloader()); - pos += util_write_in_region(buf, size, start, pos, crc, 10); + pos += hex32_field_in_region(buf, size, start, pos, "Bootloader CRC", info_get_crc_bootloader()); } +#endif + // CRC of the interface - pos += util_write_string_in_region(buf, size, start, pos, "Interface CRC: 0x"); - util_write_hex32(crc, info_get_crc_interface()); - pos += util_write_in_region(buf, size, start, pos, crc, 10); + pos += hex32_field_in_region(buf, size, start, pos, "Interface CRC", info_get_crc_interface()); // Number of remounts that have occurred - uint8_t count[12]; - pos += util_write_string_in_region(buf, size, start, pos, "Remount count: "); - uint32_t digits = util_write_uint32(count, remount_count); - count[digits++] = '\r'; - count[digits++] = '\n'; - pos += util_write_in_region(buf, size, start, pos, count, digits); + pos += uint32_field_in_region(buf, size, start, pos, "Remount count", remount_count); //Target URL pos += expand_string_in_region(buf, size, start, pos, "URL: @R\r\n"); From 4823e74db82fd2b4b24973ee323d0c99cfde18a1 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 13 Aug 2021 03:15:41 +0200 Subject: [PATCH 272/617] Additional code size reduction for VFS content generation --- source/daplink/drag-n-drop/vfs_user.c | 34 ++++++++++----------------- 1 file changed, 12 insertions(+), 22 deletions(-) diff --git a/source/daplink/drag-n-drop/vfs_user.c b/source/daplink/drag-n-drop/vfs_user.c index c2ecbf77f..a7ca30203 100644 --- a/source/daplink/drag-n-drop/vfs_user.c +++ b/source/daplink/drag-n-drop/vfs_user.c @@ -336,16 +336,6 @@ uint32_t expand_string_in_region(uint8_t *buf, uint32_t size, uint32_t start, ui return util_write_in_region(buf, size, start, pos, str_buf, l); } -uint32_t setting_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, uint8_t *label, uint32_t boolean) { - uint32_t l = util_write_string_in_region(buf, size, start, pos, label); - if (boolean) { - l += util_write_in_region(buf, size, start, pos + l, ": 1\r\n", 5); - } else { - l += util_write_in_region(buf, size, start, pos + l, ": 0\r\n", 5); - } - return l; -} - uint32_t string_field_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, uint8_t *label, const uint8_t *value) { uint32_t l = util_write_string_in_region(buf, size, start, pos, label); l += util_write_in_region(buf, size, start, pos + l, ": ", 2); @@ -354,22 +344,22 @@ uint32_t string_field_in_region(uint8_t *buf, uint32_t size, uint32_t start, uin return l; } +uint32_t setting_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, uint8_t *label, uint32_t boolean) { + return string_field_in_region(buf, size, start, pos, label, boolean ? "1" : "0"); +} + uint32_t uint32_field_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, uint8_t *label, uint32_t value) { - uint8_t number[14] = {':', ' '}; - uint32_t l = util_write_string_in_region(buf, size, start, pos, label); - uint32_t digits = util_write_uint32(number + 2, value) + 2; - number[digits++] = '\r'; - number[digits++] = '\n'; - l += util_write_in_region(buf, size, start, pos + l, number, digits); - return l; + uint8_t number[11]; + uint32_t digits = util_write_uint32(number, value); + number[digits] = 0; + return string_field_in_region(buf, size, start, pos, label, number); } uint32_t hex32_field_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, uint8_t *label, uint32_t value) { - uint8_t hex[14] = { ':', ' ', '0', 'x', 0, 0, 0, 0, 0, 0, 0, 0, '\r', '\n' }; - uint32_t l = util_write_string_in_region(buf, size, start, pos, label); - util_write_hex32(hex + 4, value); - l += util_write_in_region(buf, size, start, pos + l, hex, sizeof(hex)); - return l; + uint8_t hex[11] = { '0', 'x' }; + util_write_hex32(hex + 2, value); + hex[10] = 0; + return string_field_in_region(buf, size, start, pos, label, hex); } // File callback to be used with vfs_add_file to return file contents From 62489dd4eec1e68291dd26da92a116b10079c13a Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 19 Aug 2021 23:41:48 +0200 Subject: [PATCH 273/617] Restore "Git SHA" and "Local mods" --- source/daplink/drag-n-drop/vfs_user.c | 32 +++++++++++++++++---------- source/daplink/util.c | 4 +--- 2 files changed, 21 insertions(+), 15 deletions(-) diff --git a/source/daplink/drag-n-drop/vfs_user.c b/source/daplink/drag-n-drop/vfs_user.c index a7ca30203..82277b607 100644 --- a/source/daplink/drag-n-drop/vfs_user.c +++ b/source/daplink/drag-n-drop/vfs_user.c @@ -527,10 +527,10 @@ static uint32_t update_details_txt_file(uint8_t *buf, uint32_t size, uint32_t st { uint32_t pos = 0; - pos += util_write_string_in_region(buf, size, start, pos, "# DAPLink Firmware - see https://mbed.com/daplink\r\n"); - // Build ID - pos += util_write_string_in_region(buf, size, start, pos, "Build ID: " GIT_DESCRIPTION \ - " (" COMPILER_DESCRIPTION LOCAL_MODS ")\r\n"); + pos += util_write_string_in_region(buf, size, start, pos, + "# DAPLink Firmware - see https://mbed.com/daplink\r\n" + // Build ID + "Build ID: " GIT_DESCRIPTION " (" COMPILER_DESCRIPTION LOCAL_MODS ")\r\n"); // Unique ID pos += expand_string_in_region(buf, size, start, pos, "Unique ID: @U\r\n"); // HIC ID @@ -567,22 +567,30 @@ static uint32_t update_details_txt_file(uint8_t *buf, uint32_t size, uint32_t st #endif #endif - // Supported USB endpoints - pos += util_write_string_in_region(buf, size, start, pos, "USB Interfaces: " + pos += util_write_string_in_region(buf, size, start, pos, + // Full commit hash + "Git SHA: " GIT_COMMIT_SHA "\r\n" + // Local modifications when making the build +#if GIT_LOCAL_MODS + "Local Mods: 1\r\n" +#else + "Local Mods: 0\r\n" +#endif + // Supported USB endpoints + "USB Interfaces: " #ifdef MSC_ENDPOINT - "MSD" + "MSD" #endif #ifdef CDC_ENDPOINT - ", CDC" + ", CDC" #endif #ifdef HID_ENDPOINT - ", HID" + ", HID" #endif #if (WEBUSB_INTERFACE) - ", WebUSB" + ", WebUSB" #endif - "\r\n" - ); + "\r\n"); #if DAPLINK_ROM_BL_SIZE != 0 // CRC of the bootloader (if there is one) diff --git a/source/daplink/util.c b/source/daplink/util.c index 1025b4b8c..a26df2de1 100644 --- a/source/daplink/util.c +++ b/source/daplink/util.c @@ -111,9 +111,7 @@ uint32_t util_write_string(char *str, const char *data) } uint32_t util_write_string_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, const uint8_t *input) { - uint32_t length = strlen(input); - - return util_write_in_region(buf, size, start, pos, input, length); + return util_write_in_region(buf, size, start, pos, input, strlen(input)); } uint32_t util_write_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, const uint8_t *input, uint32_t length) { From c481ae79b70604b9e3d30450865e263f0c3c0781 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 13 Sep 2021 23:43:18 -0500 Subject: [PATCH 274/617] Fix for small rendering error --- source/daplink/drag-n-drop/vfs_user.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/daplink/drag-n-drop/vfs_user.c b/source/daplink/drag-n-drop/vfs_user.c index 82277b607..2a466ae8b 100644 --- a/source/daplink/drag-n-drop/vfs_user.c +++ b/source/daplink/drag-n-drop/vfs_user.c @@ -339,7 +339,7 @@ uint32_t expand_string_in_region(uint8_t *buf, uint32_t size, uint32_t start, ui uint32_t string_field_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, uint8_t *label, const uint8_t *value) { uint32_t l = util_write_string_in_region(buf, size, start, pos, label); l += util_write_in_region(buf, size, start, pos + l, ": ", 2); - l += util_write_string_in_region(buf, size, start, pos, value); + l += util_write_string_in_region(buf, size, start, pos + l, value); l += util_write_in_region(buf, size, start, pos + l, "\r\n", 2); return l; } From a73eed900682352602d113d375948629d96c2903 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 10 Sep 2021 02:27:34 -0500 Subject: [PATCH 275/617] nRF52840 has 256 KB of RAM Replace target_device_nrf52840 with target_device_nrf52840_256. This is needed for nvic_validate_base() to succeed validating initial SP. --- source/board/mtb_laird_bl654.c | 4 ++-- source/family/nordic/nrf5x/target.c | 28 ++++++++-------------------- 2 files changed, 10 insertions(+), 22 deletions(-) diff --git a/source/board/mtb_laird_bl654.c b/source/board/mtb_laird_bl654.c index 1d2a4fddf..3aed7322c 100644 --- a/source/board/mtb_laird_bl654.c +++ b/source/board/mtb_laird_bl654.c @@ -22,12 +22,12 @@ #include "target_board.h" #include "target_family.h" -extern target_cfg_t target_device_nrf52840_256; +extern target_cfg_t target_device_nrf52840; const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "0465", .family_id = kNordic_Nrf52_FamilyID, - .target_cfg = &target_device_nrf52840_256, + .target_cfg = &target_device_nrf52840, }; diff --git a/source/family/nordic/nrf5x/target.c b/source/family/nordic/nrf5x/target.c index 7a9d7100f..2414f4879 100644 --- a/source/family/nordic/nrf5x/target.c +++ b/source/family/nordic/nrf5x/target.c @@ -31,7 +31,7 @@ target_cfg_t target_device = { // Default is nRF51 .flash_regions[0].start = 0, .flash_regions[0].end = KB(256), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20004000, .erase_reset = 1, @@ -43,44 +43,32 @@ target_cfg_t target_device_nrf52 = { .flash_regions[0].start = 0, .flash_regions[0].end = KB(512), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash_nrf52, + .flash_regions[0].flash_algo = (program_target_t *) &flash_nrf52, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20008000, .erase_reset = 1, }; -target_cfg_t target_device_nrf52840 = { +target_cfg_t target_device_nrf52_64 = { .sectors_info = sectors_info_nrf52, .sector_info_length = (sizeof(sectors_info_nrf52))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, - .flash_regions[0].end = KB(1024), + .flash_regions[0].end = KB(512), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash_nrf52, + .flash_regions[0].flash_algo = (program_target_t *) &flash_nrf52, .ram_regions[0].start = 0x20000000, - .ram_regions[0].end = 0x20008000, + .ram_regions[0].end = 0x20010000, .erase_reset = 1, }; -target_cfg_t target_device_nrf52840_256 = { +target_cfg_t target_device_nrf52840 = { .sectors_info = sectors_info_nrf52, .sector_info_length = (sizeof(sectors_info_nrf52))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(1024), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash_nrf52, + .flash_regions[0].flash_algo = (program_target_t *) &flash_nrf52, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20040000, .erase_reset = 1, }; - -target_cfg_t target_device_nrf52_64 = { - .sectors_info = sectors_info_nrf52, - .sector_info_length = (sizeof(sectors_info_nrf52))/(sizeof(sector_info_t)), - .flash_regions[0].start = 0, - .flash_regions[0].end = KB(512), - .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash_nrf52, - .ram_regions[0].start = 0x20000000, - .ram_regions[0].end = 0x20010000, - .erase_reset = 1, -}; From 1e1755c763e6712980992d5c6445ca8540968fe6 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 10 Sep 2021 22:58:02 -0500 Subject: [PATCH 276/617] Define nrf52833 target device for microbitv2 --- source/board/microbitv2/microbitv2.c | 92 ++++++++++++++-------------- source/family/nordic/nrf5x/target.c | 16 ++++- 2 files changed, 59 insertions(+), 49 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index aa6912d6a..5f5d7bdaa 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -19,7 +19,7 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + #include "fsl_device_registers.h" #include "IO_Config.h" #include "DAP.h" @@ -28,7 +28,7 @@ #include "flexio_pwm.h" #include "gpio.h" #include "power.h" -#include "rl_usb.h" +#include "rl_usb.h" #include "pwr_mon.h" #include "main_interface.h" #include "i2c_commands.h" @@ -78,7 +78,7 @@ typedef enum { BOARD_VERSION_2_1 = 1, } mb_version_t; -extern target_cfg_t target_device_nrf52_64; +extern target_cfg_t target_device_nrf52833; extern main_usb_connect_t usb_state; extern bool go_to_sleep; extern i2c_slave_handle_t g_s_handle; @@ -115,15 +115,15 @@ static mb_version_t read_brd_rev_id_pin(void) { GPIO_PinInit(PIN_BOARD_REV_ID_GPIO, PIN_BOARD_REV_ID_BIT, &pin_config); adc_init(); - + // 1. Discharge capacitor // Drive BRD_REV_ID pin to low GPIO_PortClear(PIN_BOARD_REV_ID_GPIO, PIN_BOARD_REV_ID); PORT_SetPinMux(PIN_BOARD_REV_ID_PORT , PIN_BOARD_REV_ID_BIT, kPORT_MuxAsGpio); - // Add a 3ms delay to allow the 100nF Cap to discharge + // Add a 3ms delay to allow the 100nF Cap to discharge // at least 5*RC with 4700R. for (uint32_t count = 16 * 3000; count > 0UL; count--); - + // 2. Charge capacitor for 100us // Drive BRD_REV_ID pin to high GPIO_PortSet(PIN_BOARD_REV_ID_GPIO, PIN_BOARD_REV_ID); @@ -132,42 +132,41 @@ static mb_version_t read_brd_rev_id_pin(void) { for (uint32_t count = 1600; count > 0UL; count--); // Change pin to ADC (High-Z). Capacitor will stop charging PORT_SetPinMux(PIN_BOARD_REV_ID_PORT , PIN_BOARD_REV_ID_BIT, kPORT_PinDisabledOrAnalog); - + // 3. Take ADC measurement board_rev_id_adc = adc_read_channel(0, PIN_BOARD_REV_ID_ADC_CH, PIN_BOARD_REV_ID_ADC_MUX); board_rev_id_mv = board_rev_id_adc * 3300 / 0xFFF; // Convert ADC 12-bit value to mV with 3.3V reference - + // 4. Discharge capacitor // Drive BRD_REV_ID pin to low GPIO_PortClear(PIN_BOARD_REV_ID_GPIO, PIN_BOARD_REV_ID); PORT_SetPinMux(PIN_BOARD_REV_ID_PORT , PIN_BOARD_REV_ID_BIT, kPORT_MuxAsGpio); - // Add a 3ms delay to allow the 100nF Cap to discharge + // Add a 3ms delay to allow the 100nF Cap to discharge // at least 5*RC with 4700R. for (uint32_t count = 16 * 3000; count > 0UL; count--); - + // 5. Identify board ID depending on voltage if ( board_rev_id_mv > BRD_ID_1_LOWER_THR_V && board_rev_id_mv < BRD_ID_1_UPPER_THR_V) { board_version = BOARD_VERSION_2_1; } else { board_version = BOARD_VERSION_2_0; } - + return board_version; } static void set_board_id(mb_version_t board_version) { - target_device = target_device_nrf52_64; switch (board_version) { case BOARD_VERSION_2_0: - target_device.rt_board_id = board_id_mb_2_0; + g_board_info.target_cfg->rt_board_id = board_id_mb_2_0; board_id_hex = 0x9903; break; case BOARD_VERSION_2_1: - target_device.rt_board_id = board_id_mb_2_1; + g_board_info.target_cfg->rt_board_id = board_id_mb_2_1; board_id_hex = 0x9904; break; default: - target_device.rt_board_id = board_id_mb_2_0; + g_board_info.target_cfg->rt_board_id = board_id_mb_2_0; board_id_hex = 0x9903; break; } @@ -185,7 +184,7 @@ static void prerun_board_config(void) { mb_version_t board_version = read_brd_rev_id_pin(); set_board_id(board_version); - + // init power monitoring power_init(); pwr_mon_init(); @@ -194,20 +193,20 @@ static void prerun_board_config(void) flexio_pwm_init(); flexio_pwm_init_pins(); - + if (power_source == PWR_BATT_ONLY){ // Turn on the red LED with low duty cycle to conserve power. power_led_max_duty_cycle = PWR_LED_ON_BATT_BRIGHTNESS; - + } else { // Turn on the red LED with max duty cycle when powered by USB or EC power_led_max_duty_cycle = PWR_LED_ON_MAX_BRIGHTNESS; } uint8_t gamma_led_dc = get_led_gamma(power_led_max_duty_cycle); flexio_pwm_set_dutycycle(gamma_led_dc); - + i2c_initialize(); - + gpio_pin_config_t pin_config = { .pinDirection = kGPIO_DigitalOutput, .outputLogic = 0U @@ -217,11 +216,11 @@ static void prerun_board_config(void) PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); /* COMBINED_SENSOR_INT as output default low when pin mux ALT1 */ GPIO_PinInit(COMBINED_SENSOR_INT_GPIO, COMBINED_SENSOR_INT_PIN, &pin_config); - + // Load Config from Flash if present flashConfig_t * pflashConfigROM; pflashConfigROM = (void *)FLASH_CONFIG_ADDRESS; - + if (CFG_KEY == pflashConfigROM->key) { memcpy(&gflashConfig, pflashConfigROM, sizeof(flashConfig_t)); } @@ -289,7 +288,7 @@ void handle_reset_button() void board_30ms_hook() { static uint8_t blink_in_progress = 0; - + if (usb_state == USB_CONNECTED) { // configure pin as GPIO PIN_HID_LED_PORT->PCR[PIN_HID_LED_BIT] = PORT_PCR_MUX(1); @@ -300,22 +299,22 @@ void board_30ms_hook() PIN_HID_LED_PORT->PCR[PIN_HID_LED_BIT] = PORT_PCR_MUX(0); power_led_max_duty_cycle = PWR_LED_ON_BATT_BRIGHTNESS; } - + if (wake_from_usb) { main_shutdown_state = MAIN_USER_EVENT; - + if (usb_state == USB_DISCONNECTED) { usb_state = USB_CONNECTING; } } - + if (i2c_wake_timeout > 0) { i2c_wake_timeout--; } - + // Enter light sleep if USB is not enumerated and main_shutdown_state is idle - if (usb_state == USB_DISCONNECTED && !usb_pc_connected && main_shutdown_state == MAIN_SHUTDOWN_WAITING - && automatic_sleep_on == true && g_s_handle.isBusy == false && i2c_wake_timeout == 0 && i2c_allow_sleep) { + if (usb_state == USB_DISCONNECTED && !usb_pc_connected && main_shutdown_state == MAIN_SHUTDOWN_WAITING + && automatic_sleep_on == true && g_s_handle.isBusy == false && i2c_wake_timeout == 0 && i2c_allow_sleep) { interface_power_mode = kAPP_PowerModeVlps; main_shutdown_state = MAIN_SHUTDOWN_REQUESTED; } @@ -349,13 +348,13 @@ void board_30ms_hook() { // Release COMBINED_SENSOR_INT in case it was previously asserted PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); - + // Prepare I2C response i2cCommand_t i2cResponse = {0}; i2cResponse.cmdId = gReadResponse_c; i2cResponse.cmdData.readRspCmd.propertyId = (uint8_t) gUserEvent_c; i2cResponse.cmdData.readRspCmd.dataSize = 1; - + if (wake_from_usb) { i2cResponse.cmdData.readRspCmd.data[0] = gWakeFromWakeOnEdge_c; wake_from_usb = 0; @@ -368,7 +367,7 @@ void board_30ms_hook() // Response ready, assert COMBINED_SENSOR_INT PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_MuxAsGpio); - + // Return LED to ON after release of long press main_shutdown_state = MAIN_SHUTDOWN_WAITING; } @@ -376,7 +375,7 @@ void board_30ms_hook() case MAIN_SHUTDOWN_REQUESTED: if (power_source == PWR_BATT_ONLY || (usb_state == USB_DISCONNECTED && !usb_pc_connected)) { main_powerdown_event(); - + // In VLLS0, set the LED either ON or LOW, depending on power_led_sleep_state_on // When the duty cycle is 0% or 100%, the FlexIO driver will configure the pin as GPIO if (power_led_sleep_state_on == true && interface_power_mode == kAPP_PowerModeVlls0) { @@ -387,7 +386,7 @@ void board_30ms_hook() else { shutdown_led_dc = 0; } - + main_shutdown_state = MAIN_SHUTDOWN_WAITING; } else if (usb_state == USB_CONNECTED){ @@ -412,14 +411,14 @@ void board_30ms_hook() } else if (shutdown_led_dc > (PWR_LED_ON_MAX_BRIGHTNESS - 10)) { shutdown_led_dc--; } - + // If we are no longer PC connected, go into idle mode if (usb_state == USB_DISCONNECTED && !usb_pc_connected) { main_shutdown_state = MAIN_SHUTDOWN_WAITING; } break; case MAIN_LED_BLINK_ONCE: - + if (blink_in_progress) { blink_in_progress--; if (blink_in_progress == 5) { @@ -429,8 +428,8 @@ void board_30ms_hook() blink_in_progress = 10; shutdown_led_dc = PWR_LED_ON_MAX_BRIGHTNESS; } - - if (blink_in_progress == 0) { + + if (blink_in_progress == 0) { main_shutdown_state = MAIN_SHUTDOWN_WAITING; } break; @@ -445,7 +444,7 @@ void board_30ms_hook() } else { flexio_pwm_set_dutycycle(final_fade_led_dc); } - + // Remount if requested. if (do_remount) { do_remount = false; @@ -480,10 +479,10 @@ void board_vfs_stream_closed_hook() reset_pressed = 0; power_led_sleep_state_on = PWR_LED_SLEEP_STATE_DEFAULT; main_shutdown_state = MAIN_SHUTDOWN_WAITING; - + // Clear any pending I2C response i2c_clearBuffer(); - + // Release COMBINED_SENSOR_INT PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); } @@ -494,7 +493,7 @@ bool vfs_user_magic_file_hook(const vfs_filename_t filename, bool *do_remount) // Erase last 128KB flash block FLASH_Erase(&g_flash, FLASH_CONFIG_ADDRESS, g_flash.PFlashTotalSize / g_flash.PFlashBlockCount, kFLASH_apiEraseKey); } - + return false; } @@ -529,7 +528,7 @@ void vfs_user_build_filesystem_hook() { } file_size = gflashConfig.fileSize; - + if (gflashConfig.fileVisible) { vfs_create_file(gflashConfig.fileName, read_file_data_txt, 0, file_size); } @@ -549,11 +548,11 @@ static uint32_t read_file_data_txt(uint32_t sector_offset, uint8_t *data, uint32 uint8_t board_detect_incompatible_image(const uint8_t *data, uint32_t size) { uint8_t result = 0; - + // Check difference in vectors (mem fault, bus fault, usage fault) // If these vectors are 0, we assume it's an M0 image (not compatible) result = memcmp(data + M0_RESERVED_VECT_OFFSET, (uint8_t[M0_RESERVED_VECT_SIZE]){0}, M0_RESERVED_VECT_SIZE); - + return result == 0; } @@ -573,6 +572,5 @@ const board_info_t g_board_info = { .daplink_drive_name = "MICROBIT", .daplink_target_url = "https://microbit.org/device/?id=@B&v=@V", .prerun_board_config = prerun_board_config, - .target_cfg = &target_device, + .target_cfg = &target_device_nrf52833, }; - diff --git a/source/family/nordic/nrf5x/target.c b/source/family/nordic/nrf5x/target.c index 2414f4879..466f4e96b 100644 --- a/source/family/nordic/nrf5x/target.c +++ b/source/family/nordic/nrf5x/target.c @@ -1,9 +1,9 @@ /** * @file target.c - * @brief Target information for the nrf51 + * @brief Target information for the nRF52 Family * * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2021, Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -61,6 +61,18 @@ target_cfg_t target_device_nrf52_64 = { .erase_reset = 1, }; +target_cfg_t target_device_nrf52833 = { + .sectors_info = sectors_info_nrf52, + .sector_info_length = (sizeof(sectors_info_nrf52))/(sizeof(sector_info_t)), + .flash_regions[0].start = 0, + .flash_regions[0].end = KB(512), + .flash_regions[0].flags = kRegionIsDefault, + .flash_regions[0].flash_algo = (program_target_t *) &flash_nrf52, + .ram_regions[0].start = 0x20000000, + .ram_regions[0].end = 0x20020000, + .erase_reset = 1, +}; + target_cfg_t target_device_nrf52840 = { .sectors_info = sectors_info_nrf52, .sector_info_length = (sizeof(sectors_info_nrf52))/(sizeof(sector_info_t)), From e01415b73b4580798bc22bad556dc75a22df21af Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 10 Sep 2021 23:01:29 -0500 Subject: [PATCH 277/617] Fix configuration for boards that use 64 KB version of nRF52832 --- source/board/96b_nitrogen.c | 4 ++-- source/board/dipdap_sdt52832b.c | 4 ++-- source/board/mtb_laird_bl652.c | 4 ++-- source/board/mtb_nina_b112.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/source/board/96b_nitrogen.c b/source/board/96b_nitrogen.c index 2bec71cb9..cc5b02d68 100644 --- a/source/board/96b_nitrogen.c +++ b/source/board/96b_nitrogen.c @@ -22,11 +22,11 @@ #include "target_board.h" #include "target_family.h" -extern target_cfg_t target_device_nrf52; +extern target_cfg_t target_device_nrf52_64; const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "9014", .family_id = kNordic_Nrf52_FamilyID, - .target_cfg = &target_device_nrf52, + .target_cfg = &target_device_nrf52_64, }; diff --git a/source/board/dipdap_sdt52832b.c b/source/board/dipdap_sdt52832b.c index 6553e54eb..bfd4ead59 100644 --- a/source/board/dipdap_sdt52832b.c +++ b/source/board/dipdap_sdt52832b.c @@ -22,12 +22,12 @@ #include "target_board.h" #include "target_family.h" -extern target_cfg_t target_device_nrf52; +extern target_cfg_t target_device_nrf52_64; const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "3104", .family_id = kNordic_Nrf52_FamilyID, .flags = kEnablePageErase, - .target_cfg = &target_device_nrf52, + .target_cfg = &target_device_nrf52_64, }; diff --git a/source/board/mtb_laird_bl652.c b/source/board/mtb_laird_bl652.c index bc2a037ae..d03b59a36 100644 --- a/source/board/mtb_laird_bl652.c +++ b/source/board/mtb_laird_bl652.c @@ -22,11 +22,11 @@ #include "target_board.h" #include "target_family.h" -extern target_cfg_t target_device_nrf52; +extern target_cfg_t target_device_nrf52_64; const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "0461", .family_id = kNordic_Nrf52_FamilyID, - .target_cfg = &target_device_nrf52, + .target_cfg = &target_device_nrf52_64, }; diff --git a/source/board/mtb_nina_b112.c b/source/board/mtb_nina_b112.c index e030fda50..8fab63945 100644 --- a/source/board/mtb_nina_b112.c +++ b/source/board/mtb_nina_b112.c @@ -22,11 +22,11 @@ #include "target_board.h" #include "target_family.h" -extern target_cfg_t target_device_nrf52; +extern target_cfg_t target_device_nrf52_64; const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "0455", .family_id = kNordic_Nrf52_FamilyID, - .target_cfg = &target_device_nrf52, + .target_cfg = &target_device_nrf52_64, }; From b89dbad442f9560e49cef38c1cd18aee5443656b Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 10 Sep 2021 23:10:53 -0500 Subject: [PATCH 278/617] Make nRF51822 target configurations (16 and 32 KB RAM) more explicit sdt51822b.c and sscity.c used the 16 KB instead of 32 KB version --- docs/PORT_BOARD.md | 32 ++++++++-------- records/board/archble.yaml | 2 +- records/board/archlink.yaml | 2 +- records/board/arm_watch_nrf51.yaml | 2 +- records/board/dipdap_sdt51822b.yaml | 2 +- records/board/hrm1017.yaml | 2 +- records/board/microbit.yaml | 2 +- records/board/mtconnect04s.yaml | 2 +- records/board/rbl.yaml | 2 +- records/board/rblnano.yaml | 2 +- records/board/ssci_chibi.yaml | 2 +- records/board/sscity.yaml | 2 +- records/board/tiny.yaml | 2 +- records/board/vbluno51.yaml | 4 +- source/board/archble.c | 4 +- source/board/archlink.c | 4 +- source/board/arm_watch_nrf51.c | 4 +- source/board/dipdap_sdt51822b.c | 6 ++- source/board/hrm1017.c | 6 ++- source/board/microbit.c | 16 ++++---- source/board/mtconnect04s.c | 8 ++-- source/board/rbl.c | 4 +- source/board/rblnano.c | 4 +- source/board/ssci_chibi.c | 6 ++- source/board/sscity.c | 5 ++- source/board/tiny.c | 4 +- source/board/vbluno51.c | 4 +- source/family/nordic/nrf51822/flash_blob.c | 8 ++-- source/family/nordic/nrf51822/target_32.c | 38 ------------------- .../nrf51822/{target_16.c => target_nrf51.c} | 31 ++++++++++----- 30 files changed, 107 insertions(+), 105 deletions(-) delete mode 100644 source/family/nordic/nrf51822/target_32.c rename source/family/nordic/nrf51822/{target_16.c => target_nrf51.c} (50%) diff --git a/docs/PORT_BOARD.md b/docs/PORT_BOARD.md index 0323fb15e..ebcfbf750 100644 --- a/docs/PORT_BOARD.md +++ b/docs/PORT_BOARD.md @@ -16,18 +16,18 @@ common: board: - source/board/myboardname.c family: - - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/nrf51822/target_nrf51.c - source/family/nordic/target_reset_nrf51.c ``` This assumes there is already target support present in the codebase. If adding a new target family is needed, additional steps in [Porting target family guide](PORT_TARGET_FAMILY.md) will be needed. If the target support exists `source/board/myboardname.c` needs creation with a BOARD ID. If you're developing a custom or non-official Mbed platform, then can use any BOARD ID and the `mbedls` [mocking feature](https://github.com/ARMmbed/mbed-os-tools/blob/master/packages/mbed-ls/README.md#mocking-renaming-platforms). ```c /** - * @file myboard.c + * @file myboardname.c * @brief board_info api for my board * * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2021, Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -46,34 +46,36 @@ This assumes there is already target support present in the codebase. If adding #include "target_family.h" #include "target_board.h" +extern target_cfg_t target_device_nrf51822_16; + const board_info_t g_board_info = { .board_id = "0x240", .family_id = kStub_HWReset_FamilyID, .flags = kEnablePageErase|kEnableUnderResetConnect, - .target_cfg = &target_device, + .target_cfg = &target_device_nrf51822_16, }; ``` The complete fields of board_info api with description is in `source/target/target_board.h`. ```c -// Flags for board_info -enum { +// Flags for board_info +enum { kEnablePageErase = 1, /*!< Enable page programming and sector erase for drag and drop */ kEnableUnderResetConnect = 1<<1, /*!< Enable under reset connection when enabling debug mode */ }; -typedef struct __attribute__((__packed__)) board_info { - uint16_t infoVersion; /*!< Version number of the board */ - uint16_t family_id; /*!< Use to select target family from defined target family ids */ +typedef struct __attribute__((__packed__)) board_info { + uint16_t infoVersion; /*!< Version number of the board */ + uint16_t family_id; /*!< Use to select target family from defined target family ids */ char board_id[5]; /*!< 4-char board ID plus null terminator */ - uint8_t _padding[3]; + uint8_t _padding[3]; uint32_t flags; /*!< Combination of kEnablePageErase and kEnableUnderResetConnect */ - target_cfg_t *target_cfg; /*!< Specific chip configuration for the target and enables MSD when non-NULL */ - - // fields used by MSD + target_cfg_t *target_cfg; /*!< Specific chip configuration for the target and enables MSD when non-NULL */ + + // fields used by MSD vfs_filename_t daplink_url_name; /*!< Customize the URL file name */ vfs_filename_t daplink_drive_name; /*!< Customize the MSD DAPLink drive name */ char daplink_target_url[64]; /*!< Customize the target url in DETAILS.TXT */ - + // some specific board initilization void (*prerun_board_config)(void); /*!< Specific board debug/ID related initialization */ void (*swd_set_target_reset)(uint8_t asserted); /*!< Boards can customize how to send reset to the target precedence over target family */ @@ -99,7 +101,7 @@ Configration Fields * Firmware - The name of the firmware as shown in projects.yaml. * Bootloader - The name of the bootloader firmware as shown in projects.yaml. Only required on HICs with a DAPLink bootloader. * Target - Name of the target for this board. - * If this is an mbed official board then the target should match the name in the mbed platform page URL. For example the K64F is located at https://developer.mbed.org/platforms/FRDM-K64F/ so it would have the target name `FRDM-K64F`. Using this naming convention allows the automated tests to use the RESTful Compile API. the automated tests will build the target UART application on-the-fly in the cloud using the RESTful Compile API, download it to the PC, then download the resulting image to the target. + * If this is an mbed official board then the target should match the name in the mbed platform page URL. For example the K64F is located at https://developer.mbed.org/platforms/FRDM-K64F/ so it would have the target name `FRDM-K64F`. Using this naming convention allows the automated tests to use the RESTful Compile API. the automated tests will build the target UART application on-the-fly in the cloud using the RESTful Compile API, download it to the PC, then download the resulting image to the target. * If it is not, you will need to build the UART application yourself and supply it to `test/run_tests.py` via --targetdir. In this case, the target is the application image filename sans extension. You may need to update one or more other dictionaries. See comments in the code for guidance. diff --git a/records/board/archble.yaml b/records/board/archble.yaml index 655655121..5b7853e4d 100644 --- a/records/board/archble.yaml +++ b/records/board/archble.yaml @@ -7,5 +7,5 @@ common: board: - source/board/archble.c family: - - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/nrf51822/target_nrf51.c - source/family/nordic/target_reset_nrf51.c diff --git a/records/board/archlink.yaml b/records/board/archlink.yaml index 34819ec45..978cf0d58 100644 --- a/records/board/archlink.yaml +++ b/records/board/archlink.yaml @@ -7,5 +7,5 @@ common: board: - source/board/archlink.c family: - - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/nrf51822/target_nrf51.c - source/family/nordic/target_reset_nrf51.c diff --git a/records/board/arm_watch_nrf51.yaml b/records/board/arm_watch_nrf51.yaml index 378832ba1..b5ef8a0d8 100644 --- a/records/board/arm_watch_nrf51.yaml +++ b/records/board/arm_watch_nrf51.yaml @@ -3,5 +3,5 @@ common: board: - source/board/arm_watch_nrf51.c family: - - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/nrf51822/target_nrf51.c - source/family/nordic/target_reset_nrf51.c diff --git a/records/board/dipdap_sdt51822b.yaml b/records/board/dipdap_sdt51822b.yaml index c9eaef423..b3eaf8884 100644 --- a/records/board/dipdap_sdt51822b.yaml +++ b/records/board/dipdap_sdt51822b.yaml @@ -3,5 +3,5 @@ common: board: - source/board/dipdap_sdt51822b.c family: - - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/nrf51822/target_nrf51.c - source/family/nordic/target_reset_nrf51.c diff --git a/records/board/hrm1017.yaml b/records/board/hrm1017.yaml index 9465145cd..6e7683bdb 100644 --- a/records/board/hrm1017.yaml +++ b/records/board/hrm1017.yaml @@ -3,5 +3,5 @@ common: board: - source/board/hrm1017.c family: - - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/nrf51822/target_nrf51.c - source/family/nordic/target_reset_nrf51.c diff --git a/records/board/microbit.yaml b/records/board/microbit.yaml index 02d6357e4..d63af54d5 100644 --- a/records/board/microbit.yaml +++ b/records/board/microbit.yaml @@ -8,5 +8,5 @@ common: board: - source/board/microbit.c family: - - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/nrf51822/target_nrf51.c - source/family/nordic/target_reset_nrf51.c diff --git a/records/board/mtconnect04s.yaml b/records/board/mtconnect04s.yaml index 2702f5372..26f7b328b 100644 --- a/records/board/mtconnect04s.yaml +++ b/records/board/mtconnect04s.yaml @@ -3,5 +3,5 @@ common: board: - source/board/mtconnect04s.c family: - - source/family/nordic/nrf51822/target_32.c + - source/family/nordic/nrf51822/target_nrf51.c - source/family/nordic/target_reset_nrf51.c diff --git a/records/board/rbl.yaml b/records/board/rbl.yaml index 66ed6859a..09fb0ebba 100644 --- a/records/board/rbl.yaml +++ b/records/board/rbl.yaml @@ -3,5 +3,5 @@ common: board: - source/board/rbl.c family: - - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/nrf51822/target_nrf51.c - source/family/nordic/target_reset_nrf51.c diff --git a/records/board/rblnano.yaml b/records/board/rblnano.yaml index 1cd168c63..327e2c7c6 100644 --- a/records/board/rblnano.yaml +++ b/records/board/rblnano.yaml @@ -3,5 +3,5 @@ common: board: - source/board/rblnano.c family: - - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/nrf51822/target_nrf51.c - source/family/nordic/target_reset_nrf51.c diff --git a/records/board/ssci_chibi.yaml b/records/board/ssci_chibi.yaml index 0225969b3..f53d4c327 100644 --- a/records/board/ssci_chibi.yaml +++ b/records/board/ssci_chibi.yaml @@ -3,5 +3,5 @@ common: board: - source/board/ssci_chibi.c family: - - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/nrf51822/target_nrf51.c - source/family/nordic/target_reset_nrf51.c diff --git a/records/board/sscity.yaml b/records/board/sscity.yaml index c0447d410..8bbce0baa 100644 --- a/records/board/sscity.yaml +++ b/records/board/sscity.yaml @@ -3,5 +3,5 @@ common: board: - source/board/sscity.c family: - - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/nrf51822/target_nrf51.c - source/family/nordic/target_reset_nrf51.c diff --git a/records/board/tiny.yaml b/records/board/tiny.yaml index 2410793f4..e54f91587 100644 --- a/records/board/tiny.yaml +++ b/records/board/tiny.yaml @@ -7,5 +7,5 @@ common: board: - source/board/tiny.c family: - - source/family/nordic/nrf51822/target_16.c + - source/family/nordic/nrf51822/target_nrf51.c - source/family/nordic/target_reset_nrf51.c diff --git a/records/board/vbluno51.yaml b/records/board/vbluno51.yaml index 5a0d862b0..5a62cdc30 100644 --- a/records/board/vbluno51.yaml +++ b/records/board/vbluno51.yaml @@ -1,11 +1,11 @@ common: macros: - - IO_CONFIG_OVERRIDE + - IO_CONFIG_OVERRIDE includes: - source/board/override_vbluno51 sources: board: - source/board/vbluno51.c family: - - source/family/nordic/nrf51822/target_32.c + - source/family/nordic/nrf51822/target_nrf51.c - source/family/nordic/target_reset_nrf51.c diff --git a/source/board/archble.c b/source/board/archble.c index ff342b739..673514efc 100644 --- a/source/board/archble.c +++ b/source/board/archble.c @@ -22,9 +22,11 @@ #include "target_board.h" #include "target_family.h" +extern target_cfg_t target_device_nrf51822_16; + const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "9009", .family_id = kNordic_Nrf51_FamilyID, - .target_cfg = &target_device, + .target_cfg = &target_device_nrf51822_16, }; diff --git a/source/board/archlink.c b/source/board/archlink.c index 4eb13981d..b11e99279 100644 --- a/source/board/archlink.c +++ b/source/board/archlink.c @@ -22,9 +22,11 @@ #include "target_board.h" #include "target_family.h" +extern target_cfg_t target_device_nrf51822_16; + const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "9013", .family_id = kNordic_Nrf51_FamilyID, - .target_cfg = &target_device, + .target_cfg = &target_device_nrf51822_16, }; diff --git a/source/board/arm_watch_nrf51.c b/source/board/arm_watch_nrf51.c index 4f36dd1b8..5e60a87c6 100644 --- a/source/board/arm_watch_nrf51.c +++ b/source/board/arm_watch_nrf51.c @@ -22,9 +22,11 @@ #include "target_board.h" #include "target_family.h" +extern target_cfg_t target_device_nrf51822_16; + const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "5052", .family_id = kNordic_Nrf51_FamilyID, - .target_cfg = &target_device, + .target_cfg = &target_device_nrf51822_16, }; diff --git a/source/board/dipdap_sdt51822b.c b/source/board/dipdap_sdt51822b.c index 9f6354e74..12076e070 100644 --- a/source/board/dipdap_sdt51822b.c +++ b/source/board/dipdap_sdt51822b.c @@ -18,14 +18,16 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + #include "target_board.h" #include "target_family.h" +extern target_cfg_t target_device_nrf51822_32; + const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "3103", .family_id = kNordic_Nrf51_FamilyID, .flags = kEnablePageErase, - .target_cfg = &target_device, + .target_cfg = &target_device_nrf51822_32, }; diff --git a/source/board/hrm1017.c b/source/board/hrm1017.c index 77e5a7ee9..169714ed6 100644 --- a/source/board/hrm1017.c +++ b/source/board/hrm1017.c @@ -21,10 +21,12 @@ #include "target_board.h" #include "target_family.h" +extern target_cfg_t target_device_nrf51822_16; + const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "1017", .family_id = kNordic_Nrf51_FamilyID, - .daplink_drive_name = "MBED ", - .target_cfg = &target_device, + .daplink_drive_name = "MBED ", + .target_cfg = &target_device_nrf51822_16, }; diff --git a/source/board/microbit.c b/source/board/microbit.c index 0e99db2f6..a0a16240b 100644 --- a/source/board/microbit.c +++ b/source/board/microbit.c @@ -51,13 +51,13 @@ static uint8_t read_board_type_pin(void) { static void set_board_id(mb_version_t board_version) { switch (board_version) { case BOARD_VERSION_1_3: - target_device.rt_board_id = board_id_mb_1_3; + g_board_info.target_cfg->rt_board_id = board_id_mb_1_3; break; case BOARD_VERSION_1_5: - target_device.rt_board_id = board_id_mb_1_5; + g_board_info.target_cfg->rt_board_id = board_id_mb_1_5; break; default: - target_device.rt_board_id = board_id_mb_1_5; + g_board_info.target_cfg->rt_board_id = board_id_mb_1_5; break; } } @@ -69,7 +69,7 @@ static void prerun_board_config(void) { set_board_id(board_version); } -// USB HID override function return 1 if the activity is trivial or response is null +// USB HID override function return 1 if the activity is trivial or response is null uint8_t usbd_hid_no_activity(uint8_t *buf) { if(buf[0] == ID_DAP_Vendor3 && buf[1] == 0) @@ -78,12 +78,14 @@ uint8_t usbd_hid_no_activity(uint8_t *buf) return 0; } +extern target_cfg_t target_device_nrf51822_16; + const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .family_id = kNordic_Nrf51_FamilyID, - .daplink_url_name = "MICROBITHTM", - .daplink_drive_name = "MICROBIT ", + .daplink_url_name = "MICROBITHTM", + .daplink_drive_name = "MICROBIT ", .daplink_target_url = "https://microbit.org/device/?id=@B&v=@V", .prerun_board_config = prerun_board_config, - .target_cfg = &target_device, + .target_cfg = &target_device_nrf51822_16, }; diff --git a/source/board/mtconnect04s.c b/source/board/mtconnect04s.c index f3349a48c..1ee34c95a 100644 --- a/source/board/mtconnect04s.c +++ b/source/board/mtconnect04s.c @@ -22,12 +22,14 @@ #include "target_board.h" #include "target_family.h" +extern target_cfg_t target_device_nrf51822_32; + const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "C005", .family_id = kNordic_Nrf51_FamilyID, - .daplink_url_name = "HELP HTM", - .daplink_drive_name = "MTCONNEC04S", + .daplink_url_name = "HELP HTM", + .daplink_drive_name = "MTCONNEC04S", .daplink_target_url = "https://blog.mtmtech.com.tw/mtconnect04s/", - .target_cfg = &target_device, + .target_cfg = &target_device_nrf51822_32, }; diff --git a/source/board/rbl.c b/source/board/rbl.c index e8f013f56..c23c0bb00 100644 --- a/source/board/rbl.c +++ b/source/board/rbl.c @@ -22,9 +22,11 @@ #include "target_board.h" #include "target_family.h" +extern target_cfg_t target_device_nrf51822_16; + const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "1090", .family_id = kNordic_Nrf51_FamilyID, - .target_cfg = &target_device, + .target_cfg = &target_device_nrf51822_16, }; diff --git a/source/board/rblnano.c b/source/board/rblnano.c index 9adda7352..bc236a5ca 100644 --- a/source/board/rblnano.c +++ b/source/board/rblnano.c @@ -22,9 +22,11 @@ #include "target_board.h" #include "target_family.h" +extern target_cfg_t target_device_nrf51822_16; + const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "1095", .family_id = kNordic_Nrf51_FamilyID, - .target_cfg = &target_device, + .target_cfg = &target_device_nrf51822_16, }; diff --git a/source/board/ssci_chibi.c b/source/board/ssci_chibi.c index fd385422e..3b3f8f4c3 100644 --- a/source/board/ssci_chibi.c +++ b/source/board/ssci_chibi.c @@ -22,11 +22,13 @@ #include "target_board.h" #include "target_family.h" +extern target_cfg_t target_device_nrf51822_16; + const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "1021", .family_id = kNordic_Nrf51_FamilyID, - .daplink_drive_name = "MBED ", - .target_cfg = &target_device, + .daplink_drive_name = "MBED ", + .target_cfg = &target_device_nrf51822_16, }; diff --git a/source/board/sscity.c b/source/board/sscity.c index 29e2e9a08..2faf81a50 100644 --- a/source/board/sscity.c +++ b/source/board/sscity.c @@ -22,11 +22,12 @@ #include "target_family.h" #include "target_board.h" +extern target_cfg_t target_device_nrf51822_32; + const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "1019", .family_id = kNordic_Nrf51_FamilyID, .daplink_drive_name = "MBED ", - .target_cfg = &target_device, + .target_cfg = &target_device_nrf51822_32, }; - diff --git a/source/board/tiny.c b/source/board/tiny.c index a6ebc7d0e..cdd4b84c1 100644 --- a/source/board/tiny.c +++ b/source/board/tiny.c @@ -22,9 +22,11 @@ #include "target_board.h" #include "target_family.h" +extern target_cfg_t target_device_nrf51822_16; + const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "9012", .family_id = kNordic_Nrf51_FamilyID, - .target_cfg = &target_device, + .target_cfg = &target_device_nrf51822_16, }; diff --git a/source/board/vbluno51.c b/source/board/vbluno51.c index c33f54641..edf5bdaf1 100644 --- a/source/board/vbluno51.c +++ b/source/board/vbluno51.c @@ -28,11 +28,13 @@ static void vbluno_prerun_board_config() uart_enable_flow_control(false); } +extern target_cfg_t target_device_nrf51822_32; + const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "C006", .family_id = kNordic_Nrf51_FamilyID, .daplink_target_url = "https://os.mbed.com/platforms/VBLUNO51/", .prerun_board_config = vbluno_prerun_board_config, - .target_cfg = &target_device, + .target_cfg = &target_device_nrf51822_32, }; diff --git a/source/family/nordic/nrf51822/flash_blob.c b/source/family/nordic/nrf51822/flash_blob.c index 37b723964..7d695f0b2 100644 --- a/source/family/nordic/nrf51822/flash_blob.c +++ b/source/family/nordic/nrf51822/flash_blob.c @@ -1,9 +1,9 @@ /** * @file flash_blob.c - * @brief Flash algorithm for the nrf51 + * @brief Flash algorithm for the nRF51822 * * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2021, Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -40,11 +40,11 @@ static const uint32_t nRF51822AA_FLM[] = { * The last pair in the list will have sectors starting at that address and ending * at address start + size. */ -static const sector_info_t sectors_info[] = { +static const sector_info_t sectors_info_nrf51[] = { {0, 1024}, }; -static const program_target_t flash = { +static const program_target_t flash_nrf51 = { .init = 0x20000021, .uninit = 0x20000025, .erase_chip = 0x20000029, diff --git a/source/family/nordic/nrf51822/target_32.c b/source/family/nordic/nrf51822/target_32.c deleted file mode 100644 index 1b273f715..000000000 --- a/source/family/nordic/nrf51822/target_32.c +++ /dev/null @@ -1,38 +0,0 @@ -/** - * @file target_32.c - * @brief Target information for the nrf51 - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_config.h" - -// The file flash_blob.c must only be included in target.c -#include "flash_blob.c" - -// target information -target_cfg_t target_device = { - .sectors_info = sectors_info, - .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), - .flash_regions[0].start = 0, - .flash_regions[0].end = KB(256), - .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, - .ram_regions[0].start = 0x20000000, - .ram_regions[0].end = 0x20008000, - .erase_reset = 1, -}; diff --git a/source/family/nordic/nrf51822/target_16.c b/source/family/nordic/nrf51822/target_nrf51.c similarity index 50% rename from source/family/nordic/nrf51822/target_16.c rename to source/family/nordic/nrf51822/target_nrf51.c index eabd3af1c..dba8aa517 100644 --- a/source/family/nordic/nrf51822/target_16.c +++ b/source/family/nordic/nrf51822/target_nrf51.c @@ -1,9 +1,9 @@ /** - * @file target_16.c - * @brief Target information for the nrf51 + * @file nrf51822/target_nrf51.c + * @brief Target information for the nRF51822 * * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2021, Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -24,15 +24,28 @@ // The file flash_blob.c must only be included in target.c #include "flash_blob.c" -// target information -target_cfg_t target_device = { - .sectors_info = sectors_info, - .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), +// target information for model with 16 KB RAM +target_cfg_t target_device_nrf51822_16 = { + .sectors_info = sectors_info_nrf51, + .sector_info_length = (sizeof(sectors_info_nrf51))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(256), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash_nrf51, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20004000, - .erase_reset = 1, + .erase_reset = 1, +}; + +// target information for model with 32 KB RAM +target_cfg_t target_device_nrf51822_32 = { + .sectors_info = sectors_info_nrf51, + .sector_info_length = (sizeof(sectors_info_nrf51))/(sizeof(sector_info_t)), + .flash_regions[0].start = 0, + .flash_regions[0].end = KB(256), + .flash_regions[0].flags = kRegionIsDefault, + .flash_regions[0].flash_algo = (program_target_t *) &flash_nrf51, + .ram_regions[0].start = 0x20000000, + .ram_regions[0].end = 0x20008000, + .erase_reset = 1, }; From 2faacbe9233c1c10782efe01f404ac5c47497651 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 10 Sep 2021 23:18:10 -0500 Subject: [PATCH 279/617] Remove nRF51 from nordic/nrf5x and fix for mkit_dk_dongle.nrf5x.c rRF51 target configurations is already in notdic/nrf52822. nRF51-Dongle, nRF51-DK and nRF52-DK use MCU model with largest RAM size --- records/board/96b_nitrogen.yaml | 2 +- records/board/dipdap_sdt52832b.yaml | 2 +- records/board/ep_agora.yaml | 2 +- records/board/microbitv2.yaml | 2 +- records/board/mkit_dk_dongle_nrf5x.yaml | 3 +- records/board/mtb_aconno_acn52832.yaml | 2 +- records/board/mtb_laird_bl652.yaml | 2 +- records/board/mtb_laird_bl654.yaml | 2 +- records/board/mtb_murata_bl241.yaml | 2 +- records/board/mtb_nina_b112.yaml | 2 +- records/board/nina_b1.yaml | 2 +- records/board/ublox_evk_nina_b1.yaml | 2 +- source/board/mkit_dk_dongle_nrf5x.c | 38 ++++++------- source/board/ublox_evk_nina_b1.c | 4 +- .../nordic/{nrf5x => nrf52}/flash_blob.c | 53 ++++--------------- .../family/nordic/{nrf5x => nrf52}/target.c | 17 ++---- 16 files changed, 48 insertions(+), 89 deletions(-) rename source/family/nordic/{nrf5x => nrf52}/flash_blob.c (53%) rename source/family/nordic/{nrf5x => nrf52}/target.c (84%) diff --git a/records/board/96b_nitrogen.yaml b/records/board/96b_nitrogen.yaml index f5abfd125..99e89ee46 100644 --- a/records/board/96b_nitrogen.yaml +++ b/records/board/96b_nitrogen.yaml @@ -7,5 +7,5 @@ common: board: - source/board/96b_nitrogen.c family: - - source/family/nordic/nrf5x/target.c + - source/family/nordic/nrf52/target.c - source/family/nordic/target_reset_nrf52.c diff --git a/records/board/dipdap_sdt52832b.yaml b/records/board/dipdap_sdt52832b.yaml index 7ca7e0aba..4868bca78 100644 --- a/records/board/dipdap_sdt52832b.yaml +++ b/records/board/dipdap_sdt52832b.yaml @@ -3,5 +3,5 @@ common: board: - source/board/dipdap_sdt52832b.c family: - - source/family/nordic/nrf5x/target.c + - source/family/nordic/nrf52/target.c - source/family/nordic/target_reset_nrf52.c diff --git a/records/board/ep_agora.yaml b/records/board/ep_agora.yaml index b8bf98acd..a051a7eb7 100644 --- a/records/board/ep_agora.yaml +++ b/records/board/ep_agora.yaml @@ -3,5 +3,5 @@ common: board: - source/board/ep_agora.c family: - - source/family/nordic/nrf5x/target.c + - source/family/nordic/nrf52/target.c - source/family/nordic/target_reset_nrf52.c diff --git a/records/board/microbitv2.yaml b/records/board/microbitv2.yaml index 2c6e5960c..2207c733f 100644 --- a/records/board/microbitv2.yaml +++ b/records/board/microbitv2.yaml @@ -15,5 +15,5 @@ common: board: - source/board/microbitv2/ target: - - source/family/nordic/nrf5x/target.c + - source/family/nordic/nrf52/target.c - source/family/nordic/target_reset_nrf52.c diff --git a/records/board/mkit_dk_dongle_nrf5x.yaml b/records/board/mkit_dk_dongle_nrf5x.yaml index 0b848a065..1f880f0eb 100644 --- a/records/board/mkit_dk_dongle_nrf5x.yaml +++ b/records/board/mkit_dk_dongle_nrf5x.yaml @@ -7,6 +7,7 @@ common: board: - source/board/mkit_dk_dongle_nrf5x.c family: - - source/family/nordic/nrf5x/target.c + - source/family/nordic/nrf51822/target_nrf51.c + - source/family/nordic/nrf52/target.c - source/family/nordic/target_reset_nrf51.c - source/family/nordic/target_reset_nrf52.c diff --git a/records/board/mtb_aconno_acn52832.yaml b/records/board/mtb_aconno_acn52832.yaml index 7fc6a6ecd..9e03f9209 100644 --- a/records/board/mtb_aconno_acn52832.yaml +++ b/records/board/mtb_aconno_acn52832.yaml @@ -7,5 +7,5 @@ common: board: - source/board/mtb_aconno_acn52832.c family: - - source/family/nordic/nrf5x/target.c + - source/family/nordic/nrf52/target.c - source/family/nordic/target_reset_nrf52.c diff --git a/records/board/mtb_laird_bl652.yaml b/records/board/mtb_laird_bl652.yaml index 2f7fd0838..ab2b38429 100644 --- a/records/board/mtb_laird_bl652.yaml +++ b/records/board/mtb_laird_bl652.yaml @@ -7,5 +7,5 @@ common: board: - source/board/mtb_laird_bl652.c family: - - source/family/nordic/nrf5x/target.c + - source/family/nordic/nrf52/target.c - source/family/nordic/target_reset_nrf52.c diff --git a/records/board/mtb_laird_bl654.yaml b/records/board/mtb_laird_bl654.yaml index 786b68d64..d3b38a7dd 100644 --- a/records/board/mtb_laird_bl654.yaml +++ b/records/board/mtb_laird_bl654.yaml @@ -7,5 +7,5 @@ common: board: - source/board/mtb_laird_bl654.c family: - - source/family/nordic/nrf5x/target.c + - source/family/nordic/nrf52/target.c - source/family/nordic/target_reset_nrf52.c diff --git a/records/board/mtb_murata_bl241.yaml b/records/board/mtb_murata_bl241.yaml index ee16a5123..a04d2d0d9 100644 --- a/records/board/mtb_murata_bl241.yaml +++ b/records/board/mtb_murata_bl241.yaml @@ -7,5 +7,5 @@ common: board: - source/board/mtb_murata_bl241.c family: - - source/family/nordic/nrf5x/target.c + - source/family/nordic/nrf52/target.c - source/family/nordic/target_reset_nrf52.c diff --git a/records/board/mtb_nina_b112.yaml b/records/board/mtb_nina_b112.yaml index 6150b8b78..074bbe8a8 100644 --- a/records/board/mtb_nina_b112.yaml +++ b/records/board/mtb_nina_b112.yaml @@ -7,5 +7,5 @@ common: board: - source/board/mtb_nina_b112.c family: - - source/family/nordic/nrf5x/target.c + - source/family/nordic/nrf52/target.c - source/family/nordic/target_reset_nrf52.c diff --git a/records/board/nina_b1.yaml b/records/board/nina_b1.yaml index 224ed6283..4bc825b2b 100644 --- a/records/board/nina_b1.yaml +++ b/records/board/nina_b1.yaml @@ -7,5 +7,5 @@ common: board: - source/board/nina_b1.c family: - - source/family/nordic/nrf5x/target.c + - source/family/nordic/nrf52/target.c - source/family/nordic/target_reset_nrf51.c diff --git a/records/board/ublox_evk_nina_b1.yaml b/records/board/ublox_evk_nina_b1.yaml index c8a00ffd9..0ed22e8af 100644 --- a/records/board/ublox_evk_nina_b1.yaml +++ b/records/board/ublox_evk_nina_b1.yaml @@ -7,5 +7,5 @@ common: board: - source/board/ublox_evk_nina_b1.c family: - - source/family/nordic/nrf5x/target.c + - source/family/nordic/nrf52/target.c - source/family/nordic/target_reset_nrf52.c diff --git a/source/board/mkit_dk_dongle_nrf5x.c b/source/board/mkit_dk_dongle_nrf5x.c index dcfae56f7..4407442b1 100644 --- a/source/board/mkit_dk_dongle_nrf5x.c +++ b/source/board/mkit_dk_dongle_nrf5x.c @@ -1,9 +1,9 @@ /** - * @file nrf5x.c + * @file mkit_dk_dongle_nrf5x.c * @brief board ID for the Nordic nRF5x developments boards * * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2021, Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -34,25 +34,27 @@ const char *board_id_nrf51_dongle = "1120"; const char *board_id_nrf52_dk = "1101"; const char *board_id_nrf52840_dk = "1102"; -extern target_cfg_t target_device_nrf52; +extern target_cfg_t target_device_nrf51822_16; +extern target_cfg_t target_device_nrf51822_32; +extern target_cfg_t target_device_nrf52_64; extern target_cfg_t target_device_nrf52840; +target_cfg_t target_device; static uint8_t device_type; static void set_target_device(uint32_t device) { device_type = device; if (device == 0) { - // Target device already set to nRF51 - } - else if (device == 1) { - target_device = target_device_nrf52; - } - else if (device == 2) { + target_device = target_device_nrf51822_16; + } else if (device == 1) { + target_device = target_device_nrf51822_32; + } else if (device == 2) { + target_device = target_device_nrf52_64; + } else if (device == 3) { target_device = target_device_nrf52840; } } - static void nrf_prerun_board_config(void) { // Work around for setting the correct board id based on GPIOs @@ -88,30 +90,28 @@ static void nrf_prerun_board_config(void) * 1 | 1 | 0 | undefined */ - if (bit3) { set_target_device(0); target_device.rt_family_id = kNordic_Nrf51_FamilyID; target_device.rt_board_id = board_id_nrf51_mkit; // 1070 - //Note only a setting of 111 is defined + // Note only a setting of 111 is defined util_assert(bit2 && bit1); } else { if (!bit2 && bit1) { - set_target_device(0); + set_target_device(1); target_device.rt_family_id = kNordic_Nrf51_FamilyID; target_device.rt_board_id = board_id_nrf51_dk; // 1100 - } - else if (!bit2 && !bit1) { - set_target_device(0); + } else if (!bit2 && !bit1) { + set_target_device(1); target_device.rt_family_id = kNordic_Nrf51_FamilyID; target_device.rt_board_id = board_id_nrf51_dongle; // 1120 } else if (bit2 && !bit1) { - set_target_device(1); + set_target_device(2); target_device.rt_family_id = kNordic_Nrf52_FamilyID; target_device.rt_board_id = board_id_nrf52_dk; // 1101 } else { //(bit2 && bit1) - set_target_device(2); + set_target_device(3); target_device.rt_family_id = kNordic_Nrf52_FamilyID; target_device.rt_board_id = board_id_nrf52840_dk; // 1102 } @@ -126,7 +126,7 @@ static void nrf_swd_set_target_reset(uint8_t asserted){ if (asserted && device_type == 0) { PIOA->PIO_OER = PIN_SWDIO; PIOA->PIO_OER = PIN_SWCLK; - }else if(!asserted) { + } else if(!asserted) { PIOA->PIO_MDER = PIN_SWDIO | PIN_SWCLK | PIN_nRESET; } } diff --git a/source/board/ublox_evk_nina_b1.c b/source/board/ublox_evk_nina_b1.c index 960d4dad5..cffda9d9f 100644 --- a/source/board/ublox_evk_nina_b1.c +++ b/source/board/ublox_evk_nina_b1.c @@ -29,10 +29,12 @@ static void nina_swd_set_target_reset(uint8_t asserted){ } } +extern target_cfg_t target_device_nrf52_64; + const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "1237", .family_id = kNordic_Nrf52_FamilyID, .swd_set_target_reset = nina_swd_set_target_reset, - .target_cfg = &target_device, + .target_cfg = &target_device_nrf52_64, }; diff --git a/source/family/nordic/nrf5x/flash_blob.c b/source/family/nordic/nrf52/flash_blob.c similarity index 53% rename from source/family/nordic/nrf5x/flash_blob.c rename to source/family/nordic/nrf52/flash_blob.c index 1d50b84da..4147aa573 100644 --- a/source/family/nordic/nrf5x/flash_blob.c +++ b/source/family/nordic/nrf52/flash_blob.c @@ -1,9 +1,9 @@ /** * @file flash_blob.c - * @brief Flash algorithm for the nrf51 + * @brief Flash algorithm for the nRF52 family * * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2021, Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -21,27 +21,15 @@ #include "flash_blob.h" -static const uint32_t nRF51822AA_FLM[] = { - 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, - - /*0x020*/ 0x47702000, 0x47702000, 0x4c26b570, 0x60602002, 0x60e02001, 0x68284d24, 0xd00207c0L, 0x60602000, - /*0x040*/ 0xf000bd70L, 0xe7f6f82cL, 0x4c1eb570, 0x60612102, 0x4288491e, 0x2001d302, 0xe0006160L, 0x4d1a60a0, - /*0x060*/ 0xf81df000L, 0x7c06828, 0x2000d0fa, 0xbd706060L, 0x4605b5f8, 0x4813088e, 0x46142101, 0x4f126041, - /*0x080*/ 0xc501cc01L, 0x7c06838, 0x1e76d006, 0x480dd1f8, 0x60412100, 0xbdf84608L, 0xf801f000L, 0x480ce7f2, - /*0x0A0*/ 0x6006840, 0xd00b0e00L, 0x6849490a, 0xd0072900L, 0x4a0a4909, 0xd00007c3L, 0x1d09600a, 0xd1f90840L, - /*0x0C0*/ 0x4770, 0x4001e500, 0x4001e400, 0x10001000, 0x40010400, 0x40010500, 0x40010600, 0x6e524635, - /*0x0E0*/ 0x0, -}; - static const uint32_t nRF52832AA_FLM[] = { 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, - 0x47702000, 0x47702000, 0x4c2bb570, 0x60202002, 0x20014929, 0x60083108, 0x68284d28, 0xd00207c0, - 0x60202000, 0xf000bd70, 0xe7f6f833, 0x4c22b570, 0x60212102, 0x2f10f1b0, 0x491fd303, 0x31102001, - 0x491de001, 0x60081d09, 0xf0004d1c, 0x6828f821, 0xd0fa07c0, 0x60202000, 0xe92dbd70, 0xf8df41f0, - 0x088e8058, 0x46142101, 0xf8c84605, 0x4f131000, 0xc501cc01, 0x07c06838, 0x1e76d007, 0x2100d1f8, - 0x1000f8c8, 0xe8bd4608, 0xf00081f0, 0xe7f1f801, 0x6800480b, 0x00fff010, 0x490ad00c, 0x29006809, - 0x4908d008, 0x31fc4a08, 0xd00007c3, 0x1d09600a, 0xd1f90840, 0x00004770, 0x4001e504, 0x4001e400, - 0x40010404, 0x40010504, 0x6e524635, 0x00000000, + 0x47702000, 0x47702000, 0x4c2bb570, 0x60202002, 0x20014929, 0x60083108, 0x68284d28, 0xd00207c0, + 0x60202000, 0xf000bd70, 0xe7f6f833, 0x4c22b570, 0x60212102, 0x2f10f1b0, 0x491fd303, 0x31102001, + 0x491de001, 0x60081d09, 0xf0004d1c, 0x6828f821, 0xd0fa07c0, 0x60202000, 0xe92dbd70, 0xf8df41f0, + 0x088e8058, 0x46142101, 0xf8c84605, 0x4f131000, 0xc501cc01, 0x07c06838, 0x1e76d007, 0x2100d1f8, + 0x1000f8c8, 0xe8bd4608, 0xf00081f0, 0xe7f1f801, 0x6800480b, 0x00fff010, 0x490ad00c, 0x29006809, + 0x4908d008, 0x31fc4a08, 0xd00007c3, 0x1d09600a, 0xd1f90840, 0x00004770, 0x4001e504, 0x4001e400, + 0x40010404, 0x40010504, 0x6e524635, 0x00000000, }; /** @@ -51,29 +39,6 @@ static const uint32_t nRF52832AA_FLM[] = { * The last pair in the list will have sectors starting at that address and ending * at address start + size. */ -static const sector_info_t sectors_info[] = { - {0, 1024}, - }; - -static const program_target_t flash = { // Default is nrf51 - .init = 0x20000021, - .uninit = 0x20000025, - .erase_chip = 0x20000029, - .erase_sector = 0x20000049, - .program_page = 0x20000071, - .verify = 0x0, - { - .breakpoint = 0x20000001, - .static_base = 0x20000020 + 0x00000150, - .stack_pointer = 0x20001000 - }, - .program_buffer = 0x20000200, - .algo_start = 0x20000000, - .algo_size = 0x00000150, - .algo_blob = nRF51822AA_FLM, - .program_buffer_size = 512 // should be USBD_MSC_BlockSize -}; - static const sector_info_t sectors_info_nrf52[] = { {0, 4096}, }; diff --git a/source/family/nordic/nrf5x/target.c b/source/family/nordic/nrf52/target.c similarity index 84% rename from source/family/nordic/nrf5x/target.c rename to source/family/nordic/nrf52/target.c index 466f4e96b..a8461ba5d 100644 --- a/source/family/nordic/nrf5x/target.c +++ b/source/family/nordic/nrf52/target.c @@ -24,19 +24,7 @@ // The file flash_blob.c must only be included in target.c #include "flash_blob.c" -// target information -target_cfg_t target_device = { // Default is nRF51 - .sectors_info = sectors_info, - .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), - .flash_regions[0].start = 0, - .flash_regions[0].end = KB(256), - .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, - .ram_regions[0].start = 0x20000000, - .ram_regions[0].end = 0x20004000, - .erase_reset = 1, -}; - +// target information for model with 32 KB RAM target_cfg_t target_device_nrf52 = { .sectors_info = sectors_info_nrf52, .sector_info_length = (sizeof(sectors_info_nrf52))/(sizeof(sector_info_t)), @@ -49,6 +37,7 @@ target_cfg_t target_device_nrf52 = { .erase_reset = 1, }; +// target information for nRF52832 with 64 KB RAM / 512 KB Flash target_cfg_t target_device_nrf52_64 = { .sectors_info = sectors_info_nrf52, .sector_info_length = (sizeof(sectors_info_nrf52))/(sizeof(sector_info_t)), @@ -61,6 +50,7 @@ target_cfg_t target_device_nrf52_64 = { .erase_reset = 1, }; +// target information for nRF52833 with 128 KB RAM / 512 KB Flash target_cfg_t target_device_nrf52833 = { .sectors_info = sectors_info_nrf52, .sector_info_length = (sizeof(sectors_info_nrf52))/(sizeof(sector_info_t)), @@ -73,6 +63,7 @@ target_cfg_t target_device_nrf52833 = { .erase_reset = 1, }; +// target information for nRF52840 with 256 KB RAM / 1024 KB Flash target_cfg_t target_device_nrf52840 = { .sectors_info = sectors_info_nrf52, .sector_info_length = (sizeof(sectors_info_nrf52))/(sizeof(sector_info_t)), From d5890785dfc0ea9614c2fe4c4f95c8a9007f428c Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 15 Sep 2021 01:30:33 -0500 Subject: [PATCH 280/617] run_test: support for release directory --- test/board.py | 31 +++++++++++++------ test/bundle.py | 8 +++-- test/firmware.py | 80 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 106 insertions(+), 13 deletions(-) diff --git a/test/board.py b/test/board.py index dce3b97da..fccad5100 100644 --- a/test/board.py +++ b/test/board.py @@ -464,10 +464,12 @@ def load_interface(self, filepath, parent_test): test_info = parent_test.create_subtest('load_interface') self.set_mode(self.MODE_BL, test_info) - data_crc, crc_in_image = _compute_crc(filepath) - assert data_crc == crc_in_image, ("CRC in interface is wrong " - "expected 0x%x, found 0x%x" % - (data_crc, crc_in_image)) + # Check image CRC + if '.hex' in filepath: + data_crc, crc_in_image = _compute_crc(filepath) + assert data_crc == crc_in_image, ("CRC in interface is wrong " + "expected 0x%x, found 0x%x" % + (data_crc, crc_in_image)) filename = os.path.basename(filepath) with open(filepath, 'rb') as firmware_file: @@ -480,8 +482,12 @@ def load_interface(self, filepath, parent_test): test_info.info("programming took %s s" % (stop - start)) self.wait_for_remount(test_info) - # Check the CRC self.set_mode(self.MODE_IF, test_info) + + if '.hex' not in filepath: + return + + # Check the CRC if DaplinkBoard.KEY_IF_CRC not in self.details_txt: test_info.failure("No interface CRC in details.txt") return @@ -499,10 +505,11 @@ def load_bootloader(self, filepath, parent_test): self.set_mode(self.MODE_IF, test_info) # Check image CRC - data_crc, crc_in_image = _compute_crc(filepath) - assert data_crc == crc_in_image, ("CRC in bootloader is wrong " - "expected 0x%x, found 0x%x" % - (data_crc, crc_in_image)) + if '.hex' in filepath: + data_crc, crc_in_image = _compute_crc(filepath) + assert data_crc == crc_in_image, ("CRC in bootloader is wrong " + "expected 0x%x, found 0x%x" % + (data_crc, crc_in_image)) filename = os.path.basename(filepath) with open(filepath, 'rb') as firmware_file: @@ -515,8 +522,12 @@ def load_bootloader(self, filepath, parent_test): test_info.info("programming took %s s" % (stop - start)) self.wait_for_remount(test_info) - # Check the CRC self.set_mode(self.MODE_IF, test_info) + + if '.hex' not in filepath: + return + + # Check the CRC if DaplinkBoard.KEY_BL_CRC not in self.details_txt: test_info.failure("No bootloader CRC in details.txt") return diff --git a/test/bundle.py b/test/bundle.py index b710caf75..8aadbf7c4 100644 --- a/test/bundle.py +++ b/test/bundle.py @@ -17,7 +17,7 @@ # import os -from firmware import DAPLinkFirmware +from firmware import DAPLinkFirmware, ReleaseFirmware def load_bundle_from_release(directory): @@ -82,8 +82,10 @@ def __init__(self, directory): if daplink_firmware.valid: firmware_list.append(daplink_firmware) elif os.path.isfile(path): - # Parse relevent info - pass + if (('.bin' in name) or ('.hex' in name)): + daplink_firmware = ReleaseFirmware(name, self, path) + if daplink_firmware.valid: + firmware_list.append(daplink_firmware) else: assert False self._firmware_list = firmware_list diff --git a/test/firmware.py b/test/firmware.py index e83ad55eb..47897b665 100644 --- a/test/firmware.py +++ b/test/firmware.py @@ -145,3 +145,83 @@ def hex_path(self): @property def elf_path(self): return self._elf_path + + +class ReleaseFirmware(Firmware): + """Class to abstract access to a daplink firmware image""" + + _IF_RE = re.compile("^([a-z0-9]+)([_a-z0-9]*)_if$") + _BL_RE = re.compile("^([a-z0-9]+)([_a-z0-9]*)_bl$") + + def __init__(self, file, bundle, path): + name = re.sub(r'^[0-9]+_(.*?)[_]+0x[0-9a-f]+[.][a-z]+$', r'\1', file, flags=re.IGNORECASE) + "_if" + # print(name) + + self._name = name + self._bundle = bundle + self._directory = os.path.dirname(path) + self._valid = False + # Set type + self._type = None + string_hic = None + match = self._IF_RE.match(name) + if match: + string_hic = match.group(1) + self._type = self.TYPE.INTERFACE + if self._type is None: + assert False, 'Bad project name "%s"' % name + + # Set HIC + assert string_hic in info.HIC_STRING_TO_ID, 'Unknown HIC "%s" must ' \ + 'be added to HIC_STRING_TO_ID in info.py' % string_hic + self._hic_id = info.HIC_STRING_TO_ID[string_hic] + + # Check firmware name and type + assert self._type in self.TYPE, "Invalid type %s" % self._type + if self._type is self.TYPE.INTERFACE: + if name not in info.FIRMWARE_SET: + print('Warning: board "%s" no entry in SUPPORTED_CONFIGURATIONS in info.py' % name) + + # Set file paths + self._bin_path = path + self._hex_path = path + self._bin_path = os.path.abspath(self._bin_path) + self._hex_path = os.path.abspath(self._hex_path) + if not os.path.isfile(self._bin_path): + return # Failure + if not os.path.isfile(self._hex_path): + return # Failure + + self._valid = True + + def __str__(self): + return "Name=%s" % (self.name) + + @property + def valid(self): + """Set to True if the firmware is valid""" + return self._valid + + @property + def name(self): + return self._name + + @property + def hic_id(self): + return self._hic_id + + @property + def type(self): + return self._type + + @property + def bin_path(self): + return self._bin_path + + @property + def hex_path(self): + return self._hex_path + + @property + def elf_path(self): + return self._elf_path From 2659aaf57c676caa91bdabfe9d2604a09a7502ff Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 15 Sep 2021 02:06:42 -0500 Subject: [PATCH 281/617] CI should not use shallow clones --- .github/workflows/linux.yml | 2 ++ .github/workflows/windows.yml | 2 ++ 2 files changed, 4 insertions(+) diff --git a/.github/workflows/linux.yml b/.github/workflows/linux.yml index f73a8fe13..4d3a80569 100644 --- a/.github/workflows/linux.yml +++ b/.github/workflows/linux.yml @@ -30,6 +30,8 @@ jobs: - name: Checkout source files uses: actions/checkout@v2 + with: + fetch-depth: 0 - name: Install Python module run: | diff --git a/.github/workflows/windows.yml b/.github/workflows/windows.yml index dec6e6fc8..1fa672680 100644 --- a/.github/workflows/windows.yml +++ b/.github/workflows/windows.yml @@ -27,6 +27,8 @@ jobs: - name: Checkout source files uses: actions/checkout@v2 + with: + fetch-depth: 0 - name: Install Embedded Arm Toolchain if: steps.cache-arm-gcc.outputs.cache-hit != 'true' From 58480166962190b144e0e1b45ce4aa700a0ffde3 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 15 Sep 2021 20:50:30 -0500 Subject: [PATCH 282/617] Add both .bin and .hex file to release --- tools/package_release_files.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tools/package_release_files.py b/tools/package_release_files.py index 2b3630e2b..14ce0f3b4 100644 --- a/tools/package_release_files.py +++ b/tools/package_release_files.py @@ -146,6 +146,12 @@ def package_release_files(source, dest, version, toolchain, release_info, suppor dest_name = build_number + "_" + host_mcu + "_" + base_name + dest_offset_str + "." + extension dest_path = os.path.join(output_dir, dest_name) shutil.copyfile(source_path, dest_path) + if extension == 'bin': + shutil.copyfile(os.path.join(source_dir_part, prj_name + "_crc" + ".hex"), + os.path.join(output_dir, build_number + "_" + host_mcu + "_" + base_name + dest_offset_str + ".hex")) + else: + shutil.copyfile(os.path.join(source_dir_part, prj_name + "_crc" + legacy_str + source_offset_str + ".bin"), + os.path.join(output_dir, build_number + "_" + host_mcu + "_" + base_name + dest_offset_str + ".bin")) product_code = 'NOT SUPPORTED' for board_id, family_id, fimware, bootloader, target in supported_configurations: From e3d07fe6aba86b3ba7a0b713133f0a8219e268ed Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 16 Sep 2021 01:44:23 -0500 Subject: [PATCH 283/617] run_test: tests only work with .hex interface files --- test/bundle.py | 2 +- test/firmware.py | 10 +++------- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/test/bundle.py b/test/bundle.py index 8aadbf7c4..73faadca1 100644 --- a/test/bundle.py +++ b/test/bundle.py @@ -82,7 +82,7 @@ def __init__(self, directory): if daplink_firmware.valid: firmware_list.append(daplink_firmware) elif os.path.isfile(path): - if (('.bin' in name) or ('.hex' in name)): + if ('.hex' in name): daplink_firmware = ReleaseFirmware(name, self, path) if daplink_firmware.valid: firmware_list.append(daplink_firmware) diff --git a/test/firmware.py b/test/firmware.py index 47897b665..528e29a07 100644 --- a/test/firmware.py +++ b/test/firmware.py @@ -183,15 +183,11 @@ def __init__(self, file, bundle, path): print('Warning: board "%s" no entry in SUPPORTED_CONFIGURATIONS in info.py' % name) # Set file paths - self._bin_path = path - self._hex_path = path - self._bin_path = os.path.abspath(self._bin_path) - self._hex_path = os.path.abspath(self._hex_path) - if not os.path.isfile(self._bin_path): - return # Failure + self._hex_path = os.path.abspath(path) if not os.path.isfile(self._hex_path): return # Failure - + bin_path = re.sub(r'[.]hex', r'.bin', self._hex_path) + self._bin_path = bin_path if os.path.isfile(bin_path) else None self._valid = True def __str__(self): From e5021c7f7196c60393b7dd0e67d5f597db48adb0 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 16 Sep 2021 01:44:50 -0500 Subject: [PATCH 284/617] run_test: python 3 compatibility issue --- test/tests/test_serial.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/tests/test_serial.py b/test/tests/test_serial.py index cfd6ce307..9f7f5f1fa 100644 --- a/test/tests/test_serial.py +++ b/test/tests/test_serial.py @@ -80,7 +80,7 @@ def __enter__(self): def __exit__(self, exception_type, value, traceback): self._queue.put(None) self._write_thread.join(ERROR_TIMEOUT_SECONDS) - assert not self._write_thread.isAlive(), "Thread join failed" + assert not self._write_thread.is_alive(), "Thread join failed" self.raw_serial.close() self.raw_serial = None return False From 2b4ee772cd01c8abf550818a28f871d0ffba64d8 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 16 Sep 2021 01:46:14 -0500 Subject: [PATCH 285/617] gcc 10.3 and armclang fix for RAM functions --- source/daplink/compiler.h | 3 ++ source/daplink/daplink.ld | 1 + .../hic_hal/atmel/sam3u2c/flash_hal_SAM3U.c | 42 ++++--------------- source/hic_hal/atmel/sam3u2c/read_uid.c | 7 +--- source/hic_hal/freescale/kinetis.ld | 1 + source/hic_hal/nxp/lpc11u35/gcc/lpc11u35.ld | 1 + source/hic_hal/nxp/lpc55xx/gcc/lpc55xx.ld | 1 + 7 files changed, 16 insertions(+), 40 deletions(-) diff --git a/source/daplink/compiler.h b/source/daplink/compiler.h index 0d9e73a65..4774e1598 100644 --- a/source/daplink/compiler.h +++ b/source/daplink/compiler.h @@ -49,14 +49,17 @@ extern "C" { _Pragma("O0") #define NO_OPTIMIZE_INLINE #define NO_OPTIMIZE_POST _Pragma("pop") +#define RAM_FUNCTION __attribute__((section("ram_func"))) #elif (defined(__ARMCC_VERSION)) /* ARMCLANG */ #define NO_OPTIMIZE_PRE #define NO_OPTIMIZE_INLINE #define NO_OPTIMIZE_POST +#define RAM_FUNCTION __attribute__((section("ram_func"))) #elif (defined(__GNUC__)) #define NO_OPTIMIZE_PRE #define NO_OPTIMIZE_INLINE __attribute__((optimize("O0"))) #define NO_OPTIMIZE_POST +#define RAM_FUNCTION __attribute__((long_call, section(".ram_func"))) #else #error "Unknown compiler" #endif diff --git a/source/daplink/daplink.ld b/source/daplink/daplink.ld index 375fb378e..9e352d6d1 100644 --- a/source/daplink/daplink.ld +++ b/source/daplink/daplink.ld @@ -149,6 +149,7 @@ SECTIONS __data_start__ = .; /* create a global symbol at data start */ *(.data) /* .data sections */ *(.data*) /* .data* sections */ + *(.ram_func) /* RAM functions */ KEEP(*(.jcr*)) . = ALIGN(4); __data_end__ = .; /* define a global symbol at data end */ diff --git a/source/hic_hal/atmel/sam3u2c/flash_hal_SAM3U.c b/source/hic_hal/atmel/sam3u2c/flash_hal_SAM3U.c index 562a8d3f9..351e6dd84 100644 --- a/source/hic_hal/atmel/sam3u2c/flash_hal_SAM3U.c +++ b/source/hic_hal/atmel/sam3u2c/flash_hal_SAM3U.c @@ -51,11 +51,7 @@ typedef struct { volatile uint32_t MC_FRR; } SFR_TABLE; -#if defined ( __GNUC__ ) -__attribute__((long_call, section(".data"))) -#else -__attribute__((section("ram_func"))) -#endif +RAM_FUNCTION static void _FeedWDT(void) { // @@ -73,11 +69,7 @@ static void _FeedWDT(void) ********************************************************************** */ -#if defined ( __GNUC__ ) -__attribute__((long_call, section(".data"))) -#else -__attribute__((section("ram_func"))) -#endif +RAM_FUNCTION static void _WritePage(uint32_t Addr, volatile uint32_t *pSrc, int PerformErase) { SFR_TABLE *pSFRs; @@ -128,11 +120,7 @@ static void _WritePage(uint32_t Addr, volatile uint32_t *pSrc, int PerformErase) * ********************************************************************** */ -#if defined ( __GNUC__ ) -__attribute__((long_call, section(".data"))) -#else -__attribute__((section("ram_func"))) -#endif +RAM_FUNCTION uint32_t Init(uint32_t adr, uint32_t clk, uint32_t fnc) { // @@ -141,11 +129,7 @@ uint32_t Init(uint32_t adr, uint32_t clk, uint32_t fnc) return (0); } -#if defined ( __GNUC__ ) -__attribute__((long_call, section(".data"))) -#else -__attribute__((section("ram_func"))) -#endif +RAM_FUNCTION uint32_t UnInit(uint32_t fnc) { // @@ -154,11 +138,7 @@ uint32_t UnInit(uint32_t fnc) return (0); } -#if defined ( __GNUC__ ) -__attribute__((long_call, section(".data"))) -#else -__attribute__((section("ram_func"))) -#endif +RAM_FUNCTION uint32_t EraseChip(void) { if (g_board_info.target_cfg) { @@ -182,11 +162,7 @@ uint32_t EraseChip(void) } } -#if defined ( __GNUC__ ) -__attribute__((long_call, section(".data"))) -#else -__attribute__((section("ram_func"))) -#endif +RAM_FUNCTION uint32_t EraseSector(uint32_t adr) { uint32_t NumPagesLeft; @@ -208,11 +184,7 @@ uint32_t EraseSector(uint32_t adr) return (0); // O.K. } -#if defined ( __GNUC__ ) -__attribute__((long_call, section(".data"))) -#else -__attribute__((section("ram_func"))) -#endif +RAM_FUNCTION uint32_t ProgramPage(uint32_t adr, uint32_t sz, uint32_t *buf) { uint32_t NumPagesLeft; diff --git a/source/hic_hal/atmel/sam3u2c/read_uid.c b/source/hic_hal/atmel/sam3u2c/read_uid.c index 43107616a..af64d81a2 100644 --- a/source/hic_hal/atmel/sam3u2c/read_uid.c +++ b/source/hic_hal/atmel/sam3u2c/read_uid.c @@ -24,6 +24,7 @@ #include "read_uid.h" #include "sam3u.h" #include "cortex_m.h" +#include "compiler.h" bool unique_id_created = false; static uint32_t unique_id[4]; @@ -40,11 +41,7 @@ void read_unique_id(uint32_t *id) id[3] = unique_id[3]; } -#if defined ( __GNUC__ ) -__attribute__((long_call, section(".data"))) -#else -__attribute__((section("ram_func"))) -#endif +RAM_FUNCTION void create_unique_id(void) { cortex_int_state_t state; diff --git a/source/hic_hal/freescale/kinetis.ld b/source/hic_hal/freescale/kinetis.ld index 4572b23d3..6e94bfcd7 100644 --- a/source/hic_hal/freescale/kinetis.ld +++ b/source/hic_hal/freescale/kinetis.ld @@ -157,6 +157,7 @@ SECTIONS __data_start__ = .; /* create a global symbol at data start */ *(.data) /* .data sections */ *(.data*) /* .data* sections */ + *(.ram_func) /* RAM functions */ KEEP(*(.jcr*)) . = ALIGN(4); __data_end__ = .; /* define a global symbol at data end */ diff --git a/source/hic_hal/nxp/lpc11u35/gcc/lpc11u35.ld b/source/hic_hal/nxp/lpc11u35/gcc/lpc11u35.ld index dd49c146d..7f9699607 100644 --- a/source/hic_hal/nxp/lpc11u35/gcc/lpc11u35.ld +++ b/source/hic_hal/nxp/lpc11u35/gcc/lpc11u35.ld @@ -152,6 +152,7 @@ SECTIONS *(RAM1) *(.data) /* .data sections */ *(.data*) /* .data* sections */ + *(.ram_func) /* RAM functions */ KEEP(*(.jcr*)) . = ALIGN(4); __data_end__ = .; /* define a global symbol at data end */ diff --git a/source/hic_hal/nxp/lpc55xx/gcc/lpc55xx.ld b/source/hic_hal/nxp/lpc55xx/gcc/lpc55xx.ld index 14ba2f409..d29877567 100644 --- a/source/hic_hal/nxp/lpc55xx/gcc/lpc55xx.ld +++ b/source/hic_hal/nxp/lpc55xx/gcc/lpc55xx.ld @@ -149,6 +149,7 @@ SECTIONS __data_start__ = .; /* create a global symbol at data start */ *(.data) /* .data sections */ *(.data*) /* .data* sections */ + *(.ram_func) /* RAM functions */ KEEP(*(.jcr*)) . = ALIGN(4); __data_end__ = .; /* define a global symbol at data end */ From 0668ae16a6ea1ac3e6c93cc954a4c78d78e9be54 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 16 Sep 2021 02:18:27 -0500 Subject: [PATCH 286/617] Fix char signedness warnings reported by armclang --- source/daplink/drag-n-drop/vfs_user.c | 27 +++++++++++++-------------- source/daplink/util.c | 4 ++-- source/daplink/util.h | 4 ++-- 3 files changed, 17 insertions(+), 18 deletions(-) diff --git a/source/daplink/drag-n-drop/vfs_user.c b/source/daplink/drag-n-drop/vfs_user.c index 2a466ae8b..ab37c0f81 100644 --- a/source/daplink/drag-n-drop/vfs_user.c +++ b/source/daplink/drag-n-drop/vfs_user.c @@ -118,7 +118,6 @@ static uint32_t read_file_fail_txt(uint32_t sector_offset, uint8_t *data, uint32 static uint32_t read_file_assert_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors); static uint32_t read_file_need_bl_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors); -static uint32_t update_html_file(uint8_t *data, uint32_t datasize); static uint32_t update_details_txt_file(uint8_t *data, uint32_t datasize, uint32_t start); static void erase_target(void); @@ -325,18 +324,18 @@ static uint32_t get_file_size(vfs_read_cb_t read_func) #define EXPANSION_BUFFER_SIZE 128 #endif -uint32_t expand_string_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, uint8_t *input) { - uint8_t str_buf[EXPANSION_BUFFER_SIZE]; +uint32_t expand_string_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, const char *input) { + char str_buf[EXPANSION_BUFFER_SIZE]; memset(str_buf, 0, sizeof(str_buf)); for(uint32_t i = 0; (i < (sizeof(str_buf) - 1)) && 0 != input[i]; i++) { str_buf[i] = input[i]; } - uint32_t l = expand_info(str_buf, sizeof(str_buf)); + uint32_t l = expand_info((uint8_t *)str_buf, sizeof(str_buf)); return util_write_in_region(buf, size, start, pos, str_buf, l); } -uint32_t string_field_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, uint8_t *label, const uint8_t *value) { +uint32_t string_field_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, const char *label, const char *value) { uint32_t l = util_write_string_in_region(buf, size, start, pos, label); l += util_write_in_region(buf, size, start, pos + l, ": ", 2); l += util_write_string_in_region(buf, size, start, pos + l, value); @@ -344,19 +343,19 @@ uint32_t string_field_in_region(uint8_t *buf, uint32_t size, uint32_t start, uin return l; } -uint32_t setting_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, uint8_t *label, uint32_t boolean) { +uint32_t setting_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, const char *label, uint32_t boolean) { return string_field_in_region(buf, size, start, pos, label, boolean ? "1" : "0"); } -uint32_t uint32_field_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, uint8_t *label, uint32_t value) { - uint8_t number[11]; +uint32_t uint32_field_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, const char *label, uint32_t value) { + char number[11]; uint32_t digits = util_write_uint32(number, value); number[digits] = 0; - return string_field_in_region(buf, size, start, pos, label, number); + return string_field_in_region(buf, size, start, pos, label, (char *)number); } -uint32_t hex32_field_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, uint8_t *label, uint32_t value) { - uint8_t hex[11] = { '0', 'x' }; +uint32_t hex32_field_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, const char *label, uint32_t value) { + char hex[11] = { '0', 'x' }; util_write_hex32(hex + 2, value); hex[10] = 0; return string_field_in_region(buf, size, start, pos, label, hex); @@ -482,7 +481,7 @@ static uint32_t read_file_assert_txt(uint32_t sector_offset, uint8_t *buf, uint3 //print hexdumps pos += util_write_string_in_region(buf, size, start, pos, "Hexdumps\r\n"); while ((index < valid_hexdumps) && ((pos + 10) < VFS_SECTOR_SIZE)) { //hexdumps + newline is always 10 characters - uint8_t hex[10] = { 0, 0, 0, 0, 0, 0, 0, 0, '\r', '\n' }; + char hex[10] = { 0, 0, 0, 0, 0, 0, 0, 0, '\r', '\n' }; util_write_hex32(hex, hexdumps[index++]); pos += util_write_in_region(buf, size, start, pos, hex, 10); } @@ -548,7 +547,7 @@ static uint32_t update_details_txt_file(uint8_t *buf, uint32_t size, uint32_t st pos += expand_string_in_region(buf, size, start, pos, "Bootloader Version: @V\r\n"); if (info_get_interface_present()) { - uint8_t version[6] = { 0, 0, 0, 0, '\r', '\n' }; + char version[6] = { 0, 0, 0, 0, '\r', '\n' }; pos += util_write_string_in_region(buf, size, start, pos, "Interface Version: "); util_write_uint32_zp(version, info_get_interface_version(), 4); pos += util_write_in_region(buf, size, start, pos, version, 6); @@ -559,7 +558,7 @@ static uint32_t update_details_txt_file(uint8_t *buf, uint32_t size, uint32_t st #if DAPLINK_ROM_BL_SIZE != 0 if (info_get_bootloader_present()) { - uint8_t version[6] = { 0, 0, 0, 0, '\r', '\n' }; + char version[6] = { 0, 0, 0, 0, '\r', '\n' }; pos += util_write_string_in_region(buf, size, start, pos, "Bootloader Version: "); util_write_uint32_zp(version, info_get_bootloader_version(), 4); pos += util_write_in_region(buf, size, start, pos, version, 6); diff --git a/source/daplink/util.c b/source/daplink/util.c index a26df2de1..9a7b1f445 100644 --- a/source/daplink/util.c +++ b/source/daplink/util.c @@ -110,11 +110,11 @@ uint32_t util_write_string(char *str, const char *data) return pos; } -uint32_t util_write_string_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, const uint8_t *input) { +uint32_t util_write_string_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, const char *input) { return util_write_in_region(buf, size, start, pos, input, strlen(input)); } -uint32_t util_write_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, const uint8_t *input, uint32_t length) { +uint32_t util_write_in_region(uint8_t *buf, uint32_t size, uint32_t start, uint32_t pos, const char *input, uint32_t length) { if (buf != NULL) { // Check if there is something to copy if (((pos + length) >= start) && (pos <= (start + size))) { diff --git a/source/daplink/util.h b/source/daplink/util.h index 5e1d5df95..f0970bb7d 100644 --- a/source/daplink/util.h +++ b/source/daplink/util.h @@ -67,9 +67,9 @@ uint32_t util_write_uint32_zp(char *str, uint32_t value, uint16_t total_size); uint32_t util_write_string(char *str, const char *data); uint32_t util_write_in_region(uint8_t *buf, uint32_t size, uint32_t start, - uint32_t pos, const uint8_t *input, uint32_t length); + uint32_t pos, const char *input, uint32_t length); uint32_t util_write_string_in_region(uint8_t *buf, uint32_t size, uint32_t start, - uint32_t pos, const uint8_t *input); + uint32_t pos, const char *input); __STATIC_INLINE uint32_t util_div_round_up(uint32_t dividen, uint32_t divisor) { From 12a8ee931c8774a95a0b27cbe135bdf8edf68897 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 16 Sep 2021 22:46:38 -0500 Subject: [PATCH 287/617] Fix for k20dx build with armclang --- records/hic_hal/k20dx.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/records/hic_hal/k20dx.yaml b/records/hic_hal/k20dx.yaml index 85f981e0e..9188bb008 100644 --- a/records/hic_hal/k20dx.yaml +++ b/records/hic_hal/k20dx.yaml @@ -37,6 +37,9 @@ tool_specific: hic_hal: - source/hic_hal/freescale/k20dx/armcc armclang: + misc: + common_flags: + - -mfpu=none sources: hic_hal: - source/hic_hal/freescale/k20dx/armcc From 2f4065e8af4619b47040b4daf533591a59964477 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 16 Sep 2021 22:55:46 -0500 Subject: [PATCH 288/617] Use compiler generated RAM functions for fsl_flash.c --- source/hic_hal/freescale/iap/fsl_flash.c | 32 +++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/source/hic_hal/freescale/iap/fsl_flash.c b/source/hic_hal/freescale/iap/fsl_flash.c index b704c2791..566f0849c 100644 --- a/source/hic_hal/freescale/iap/fsl_flash.c +++ b/source/hic_hal/freescale/iap/fsl_flash.c @@ -29,6 +29,8 @@ */ #include "fsl_flash.h" +#include "compiler.h" +#define USE_RAM_FUNC /******************************************************************************* * Definitions @@ -237,12 +239,14 @@ enum _flash_config_area_range ******************************************************************************/ #if FLASH_DRIVER_IS_FLASH_RESIDENT +#ifndef USE_RAM_FUNC /*! @brief Copy flash_run_command() to RAM*/ static void copy_flash_run_command(uint8_t *flashRunCommand); /*! @brief Copy flash_cache_clear_command() to RAM*/ static void copy_flash_cache_clear_command(uint8_t *flashCacheClearCommand); /*! @brief Check whether flash execute-in-ram functions are ready*/ static status_t flash_check_execute_in_ram_function_info(flash_config_t *config); +#endif #endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ /*! @brief Internal function Flash command sequence. Called by driver APIs only*/ @@ -318,13 +322,19 @@ volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFL->FPROT3; #endif #if FLASH_DRIVER_IS_FLASH_RESIDENT +#ifdef USE_RAM_FUNC +#define callFlashRunCommand flash_run_command +#define callFlashCacheClearCommand flash_cache_clear_command +#else /*! @brief A function pointer used to point to relocated flash_run_command() */ static void (*callFlashRunCommand)(FTFx_REG_ACCESS_TYPE ftfx_fstat); /*! @brief A function pointer used to point to relocated flash_cache_clear_command() */ static void (*callFlashCacheClearCommand)(FTFx_REG32_ACCESS_TYPE ftfx_reg); +#endif #endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ #if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED) +#ifndef USE_RAM_FUNC /*! @brief A static buffer used to hold flash_run_command() */ static uint8_t s_flashRunCommand[kFLASH_executeInRamFunctionMaxSize]; /*! @brief A static buffer used to hold flash_cache_clear_command() */ @@ -332,6 +342,7 @@ static uint8_t s_flashCacheClearCommand[kFLASH_executeInRamFunctionMaxSize]; /*! @brief Flash execute-in-ram function information */ static flash_execute_in_ram_function_config_t s_flashExecuteInRamFunctionInfo; #endif +#endif /*! * @brief Table of pflash sizes. @@ -414,6 +425,7 @@ status_t FLASH_Init(flash_config_t *config) /* copy required flash commands to RAM */ #if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED) +#ifndef USE_RAM_FUNC if (kStatus_FLASH_Success != flash_check_execute_in_ram_function_info(config)) { s_flashExecuteInRamFunctionInfo.activeFunctionCount = 0; @@ -422,6 +434,7 @@ status_t FLASH_Init(flash_config_t *config) config->flashExecuteInRamFunctionInfo = &s_flashExecuteInRamFunctionInfo.activeFunctionCount; FLASH_PrepareExecuteInRamFunctions(config); } +#endif #endif config->FlexRAMBlockBase = FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS; @@ -455,6 +468,7 @@ status_t FLASH_SetCallback(flash_config_t *config, flash_callback_t callback) } #if FLASH_DRIVER_IS_FLASH_RESIDENT +#ifndef USE_RAM_FUNC status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config) { flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo; @@ -472,6 +486,7 @@ status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config) return kStatus_FLASH_Success; } +#endif #endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ status_t FLASH_EraseAll(flash_config_t *config, uint32_t key) @@ -1890,6 +1905,9 @@ status_t FLASH_VerifyProgram(flash_config_t *config, * It is for flash-resident bootloader only, not technically required for ROM or * flashloader (RAM-resident bootloader). */ +#ifdef USE_RAM_FUNC +RAM_FUNCTION +#endif void flash_run_command(FTFx_REG_ACCESS_TYPE ftfx_fstat) { /* clear CCIF bit */ @@ -1902,6 +1920,7 @@ void flash_run_command(FTFx_REG_ACCESS_TYPE ftfx_fstat) } } +#ifndef USE_RAM_FUNC /*! * @brief Be used for determining the size of flash_run_command() * @@ -1946,6 +1965,7 @@ static void copy_flash_run_command(uint8_t *flashRunCommand) memcpy((void *)flashRunCommand, (void *)flash_run_command_start_addr, funcLength); callFlashRunCommand = (void (*)(FTFx_REG_ACCESS_TYPE ftfx_fstat))((uint32_t)flashRunCommand + 1); } +#endif #endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ /*! @@ -1964,12 +1984,13 @@ static status_t flash_command_sequence(flash_config_t *config) /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK; +#ifndef USE_RAM_FUNC status_t returnCode = flash_check_execute_in_ram_function_info(config); if (kStatus_FLASH_Success != returnCode) { return returnCode; } - +#endif /* We pass the ftfx_fstat address as a parameter to flash_run_comamnd() instead of using * pre-processed MICRO sentences or operating global variable in flash_run_comamnd() * to make sure that flash_run_command() will be compiled into position-independent code (PIC). */ @@ -2022,6 +2043,9 @@ static status_t flash_command_sequence(flash_config_t *config) * It is for flash-resident bootloader only, not technically required for ROM or * flashloader (RAM-resident bootloader). */ +#ifdef USE_RAM_FUNC +RAM_FUNCTION +#endif void flash_cache_clear_command(FTFx_REG32_ACCESS_TYPE ftfx_reg) { #if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS @@ -2044,6 +2068,7 @@ void flash_cache_clear_command(FTFx_REG32_ACCESS_TYPE ftfx_reg) __DSB(); } +#ifndef USE_RAM_FUNC /*! * @brief Be used for determining the size of flash_cache_clear_command() * @@ -2088,6 +2113,7 @@ static void copy_flash_cache_clear_command(uint8_t *flashCacheClearCommand) memcpy((void *)flashCacheClearCommand, (void *)flash_cache_clear_command_start_addr, funcLength); callFlashCacheClearCommand = (void (*)(FTFx_REG32_ACCESS_TYPE ftfx_reg))((uint32_t)flashCacheClearCommand + 1); } +#endif #endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ /*! @@ -2113,11 +2139,13 @@ void __attribute__((optimize("O0"))) flash_cache_clear(flash_config_t *config) #endif { #if FLASH_DRIVER_IS_FLASH_RESIDENT +#ifndef USE_RAM_FUNC status_t returnCode = flash_check_execute_in_ram_function_info(config); if (kStatus_FLASH_Success != returnCode) { return; } +#endif /* We pass the ftfx register address as a parameter to flash_cache_clear_comamnd() instead of using * pre-processed MACROs or a global variable in flash_cache_clear_comamnd() @@ -2180,6 +2208,7 @@ void __attribute__((optimize("O0"))) flash_cache_clear(flash_config_t *config) #endif #if FLASH_DRIVER_IS_FLASH_RESIDENT +#ifndef USE_RAM_FUNC /*! @brief Check whether flash execute-in-ram functions are ready */ static status_t flash_check_execute_in_ram_function_info(flash_config_t *config) { @@ -2200,6 +2229,7 @@ static status_t flash_check_execute_in_ram_function_info(flash_config_t *config) return kStatus_FLASH_ExecuteInRamFunctionNotReady; } +#endif #endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ /*! @brief Validates the range and alignment of the given address range.*/ From 8d944210dc6eb19c8bc726465a089ed259049bbe Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 17 Sep 2021 17:56:07 -0500 Subject: [PATCH 289/617] Removing old RAM function mechanism in fsl_flash.c --- source/hic_hal/freescale/iap/fsl_flash.c | 225 +---------------------- 1 file changed, 10 insertions(+), 215 deletions(-) diff --git a/source/hic_hal/freescale/iap/fsl_flash.c b/source/hic_hal/freescale/iap/fsl_flash.c index 566f0849c..417afdfb9 100644 --- a/source/hic_hal/freescale/iap/fsl_flash.c +++ b/source/hic_hal/freescale/iap/fsl_flash.c @@ -238,17 +238,6 @@ enum _flash_config_area_range * Prototypes ******************************************************************************/ -#if FLASH_DRIVER_IS_FLASH_RESIDENT -#ifndef USE_RAM_FUNC -/*! @brief Copy flash_run_command() to RAM*/ -static void copy_flash_run_command(uint8_t *flashRunCommand); -/*! @brief Copy flash_cache_clear_command() to RAM*/ -static void copy_flash_cache_clear_command(uint8_t *flashCacheClearCommand); -/*! @brief Check whether flash execute-in-ram functions are ready*/ -static status_t flash_check_execute_in_ram_function_info(flash_config_t *config); -#endif -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - /*! @brief Internal function Flash command sequence. Called by driver APIs only*/ static status_t flash_command_sequence(flash_config_t *config); @@ -321,29 +310,6 @@ volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFL->FPROT3; #error "Unknown flash controller" #endif -#if FLASH_DRIVER_IS_FLASH_RESIDENT -#ifdef USE_RAM_FUNC -#define callFlashRunCommand flash_run_command -#define callFlashCacheClearCommand flash_cache_clear_command -#else -/*! @brief A function pointer used to point to relocated flash_run_command() */ -static void (*callFlashRunCommand)(FTFx_REG_ACCESS_TYPE ftfx_fstat); -/*! @brief A function pointer used to point to relocated flash_cache_clear_command() */ -static void (*callFlashCacheClearCommand)(FTFx_REG32_ACCESS_TYPE ftfx_reg); -#endif -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - -#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED) -#ifndef USE_RAM_FUNC -/*! @brief A static buffer used to hold flash_run_command() */ -static uint8_t s_flashRunCommand[kFLASH_executeInRamFunctionMaxSize]; -/*! @brief A static buffer used to hold flash_cache_clear_command() */ -static uint8_t s_flashCacheClearCommand[kFLASH_executeInRamFunctionMaxSize]; -/*! @brief Flash execute-in-ram function information */ -static flash_execute_in_ram_function_config_t s_flashExecuteInRamFunctionInfo; -#endif -#endif - /*! * @brief Table of pflash sizes. * @@ -423,20 +389,6 @@ status_t FLASH_Init(flash_config_t *config) config->PFlashCallback = NULL; -/* copy required flash commands to RAM */ -#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED) -#ifndef USE_RAM_FUNC - if (kStatus_FLASH_Success != flash_check_execute_in_ram_function_info(config)) - { - s_flashExecuteInRamFunctionInfo.activeFunctionCount = 0; - s_flashExecuteInRamFunctionInfo.flashRunCommand = s_flashRunCommand; - s_flashExecuteInRamFunctionInfo.flashCacheClearCommand = s_flashCacheClearCommand; - config->flashExecuteInRamFunctionInfo = &s_flashExecuteInRamFunctionInfo.activeFunctionCount; - FLASH_PrepareExecuteInRamFunctions(config); - } -#endif -#endif - config->FlexRAMBlockBase = FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS; config->FlexRAMTotalSize = FSL_FEATURE_FLASH_FLEX_RAM_SIZE; @@ -467,28 +419,6 @@ status_t FLASH_SetCallback(flash_config_t *config, flash_callback_t callback) return kStatus_FLASH_Success; } -#if FLASH_DRIVER_IS_FLASH_RESIDENT -#ifndef USE_RAM_FUNC -status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config) -{ - flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo; - - copy_flash_run_command(flashExecuteInRamFunctionInfo->flashRunCommand); - copy_flash_cache_clear_command(flashExecuteInRamFunctionInfo->flashCacheClearCommand); - flashExecuteInRamFunctionInfo->activeFunctionCount = kFLASH_executeInRamFunctionTotalNum; - - return kStatus_FLASH_Success; -} -#endif -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - status_t FLASH_EraseAll(flash_config_t *config, uint32_t key) { status_t returnCode; @@ -1905,9 +1835,8 @@ status_t FLASH_VerifyProgram(flash_config_t *config, * It is for flash-resident bootloader only, not technically required for ROM or * flashloader (RAM-resident bootloader). */ -#ifdef USE_RAM_FUNC + RAM_FUNCTION -#endif void flash_run_command(FTFx_REG_ACCESS_TYPE ftfx_fstat) { /* clear CCIF bit */ @@ -1919,53 +1848,6 @@ void flash_run_command(FTFx_REG_ACCESS_TYPE ftfx_fstat) { } } - -#ifndef USE_RAM_FUNC -/*! - * @brief Be used for determining the size of flash_run_command() - * - * This function must be defined that lexically follows flash_run_command(), - * so we can determine the size of flash_run_command() at runtime and not worry - * about toolchain or code generation differences. - */ -void flash_run_command_end(void) -{ -} - -/*! - * @brief Copy flash_run_command() to RAM - * - * This function copys the memory between flash_run_command() and flash_run_command_end() - * into the buffer which is also means that copying flash_run_command() to RAM. - */ -static void copy_flash_run_command(uint8_t *flashRunCommand) -{ - /* Calculate the valid length of flash_run_command() memory. - * Set max size(64 bytes) as default function size, in case some compiler allocates - * flash_run_command_end ahead of flash_run_command. */ - uint32_t funcLength = kFLASH_executeInRamFunctionMaxSize; - uint32_t flash_run_command_start_addr = (uint32_t)flash_run_command & (~1U); - uint32_t flash_run_command_end_addr = (uint32_t)flash_run_command_end & (~1U); - if (flash_run_command_end_addr > flash_run_command_start_addr) - { - funcLength = flash_run_command_end_addr - flash_run_command_start_addr; - - assert(funcLength <= kFLASH_executeInRamFunctionMaxSize); - - /* In case some compiler allocates other function in the middle of flash_run_command - * and flash_run_command_end. */ - if (funcLength > kFLASH_executeInRamFunctionMaxSize) - { - funcLength = kFLASH_executeInRamFunctionMaxSize; - } - } - - /* Since the value of ARM function pointer is always odd, but the real start address - * of function memory should be even, that's why -1 and +1 operation exist. */ - memcpy((void *)flashRunCommand, (void *)flash_run_command_start_addr, funcLength); - callFlashRunCommand = (void (*)(FTFx_REG_ACCESS_TYPE ftfx_fstat))((uint32_t)flashRunCommand + 1); -} -#endif #endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ /*! @@ -1984,17 +1866,10 @@ static status_t flash_command_sequence(flash_config_t *config) /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK; -#ifndef USE_RAM_FUNC - status_t returnCode = flash_check_execute_in_ram_function_info(config); - if (kStatus_FLASH_Success != returnCode) - { - return returnCode; - } -#endif /* We pass the ftfx_fstat address as a parameter to flash_run_comamnd() instead of using * pre-processed MICRO sentences or operating global variable in flash_run_comamnd() * to make sure that flash_run_command() will be compiled into position-independent code (PIC). */ - callFlashRunCommand((FTFx_REG_ACCESS_TYPE)(&FTFx->FSTAT)); + flash_run_command((FTFx_REG_ACCESS_TYPE)(&FTFx->FSTAT)); #else /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK; @@ -2043,9 +1918,8 @@ static status_t flash_command_sequence(flash_config_t *config) * It is for flash-resident bootloader only, not technically required for ROM or * flashloader (RAM-resident bootloader). */ -#ifdef USE_RAM_FUNC + RAM_FUNCTION -#endif void flash_cache_clear_command(FTFx_REG32_ACCESS_TYPE ftfx_reg) { #if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS @@ -2067,53 +1941,6 @@ void flash_cache_clear_command(FTFx_REG32_ACCESS_TYPE ftfx_reg) __ISB(); __DSB(); } - -#ifndef USE_RAM_FUNC -/*! - * @brief Be used for determining the size of flash_cache_clear_command() - * - * This function must be defined that lexically follows flash_cache_clear_command(), - * so we can determine the size of flash_cache_clear_command() at runtime and not worry - * about toolchain or code generation differences. - */ -void flash_cache_clear_command_end(void) -{ -} - -/*! - * @brief Copy flash_cache_clear_command() to RAM - * - * This function copys the memory between flash_cache_clear_command() and flash_cache_clear_command_end() - * into the buffer which is also means that copying flash_cache_clear_command() to RAM. - */ -static void copy_flash_cache_clear_command(uint8_t *flashCacheClearCommand) -{ - /* Calculate the valid length of flash_cache_clear_command() memory. - * Set max size(64 bytes) as default function size, in case some compiler allocates - * flash_cache_clear_command_end ahead of flash_cache_clear_command. */ - uint32_t funcLength = kFLASH_executeInRamFunctionMaxSize; - uint32_t flash_cache_clear_command_start_addr = (uint32_t)flash_cache_clear_command & (~1U); - uint32_t flash_cache_clear_command_end_addr = (uint32_t)flash_cache_clear_command_end & (~1U); - if (flash_cache_clear_command_end_addr > flash_cache_clear_command_start_addr) - { - funcLength = flash_cache_clear_command_end_addr - flash_cache_clear_command_start_addr; - - assert(funcLength <= kFLASH_executeInRamFunctionMaxSize); - - /* In case some compiler allocates other function in the middle of flash_cache_clear_command - * and flash_cache_clear_command_end. */ - if (funcLength > kFLASH_executeInRamFunctionMaxSize) - { - funcLength = kFLASH_executeInRamFunctionMaxSize; - } - } - - /* Since the value of ARM function pointer is always odd, but the real start address - * of function memory should be even, that's why -1 and +1 operation exist. */ - memcpy((void *)flashCacheClearCommand, (void *)flash_cache_clear_command_start_addr, funcLength); - callFlashCacheClearCommand = (void (*)(FTFx_REG32_ACCESS_TYPE ftfx_reg))((uint32_t)flashCacheClearCommand + 1); -} -#endif #endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ /*! @@ -2139,39 +1966,32 @@ void __attribute__((optimize("O0"))) flash_cache_clear(flash_config_t *config) #endif { #if FLASH_DRIVER_IS_FLASH_RESIDENT -#ifndef USE_RAM_FUNC - status_t returnCode = flash_check_execute_in_ram_function_info(config); - if (kStatus_FLASH_Success != returnCode) - { - return; - } -#endif /* We pass the ftfx register address as a parameter to flash_cache_clear_comamnd() instead of using * pre-processed MACROs or a global variable in flash_cache_clear_comamnd() * to make sure that flash_cache_clear_command() will be compiled into position-independent code (PIC). */ #if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS #if defined(MCM) - callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM->PLACR); + flash_cache_clear_command((FTFx_REG32_ACCESS_TYPE)&MCM->PLACR); #endif #if defined(MCM0) - callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM0->PLACR); + flash_cache_clear_command((FTFx_REG32_ACCESS_TYPE)&MCM0->PLACR); #endif #if defined(MCM1) - callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM1->PLACR); + flash_cache_clear_command((FTFx_REG32_ACCESS_TYPE)&MCM1->PLACR); #endif #elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS #if defined(FMC_PFB01CR_CINV_WAY_MASK) - callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR); + flash_cache_clear_command((FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR); #else - callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR); + flash_cache_clear_command((FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR); #endif #elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS - callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[0]); + flash_cache_clear_command((FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[0]); #else /* #error "Unknown flash cache controller" */ /* meaningless code, just a workaround to solve warning*/ - callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)0); + flash_cache_clear_command((FTFx_REG32_ACCESS_TYPE)0); #endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */ #else @@ -2207,31 +2027,6 @@ void __attribute__((optimize("O0"))) flash_cache_clear(flash_config_t *config) /* #pragma GCC pop_options */ #endif -#if FLASH_DRIVER_IS_FLASH_RESIDENT -#ifndef USE_RAM_FUNC -/*! @brief Check whether flash execute-in-ram functions are ready */ -static status_t flash_check_execute_in_ram_function_info(flash_config_t *config) -{ - flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo; - - if (config == NULL) - { - return kStatus_FLASH_InvalidArgument; - } - - flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo; - - if ((config->flashExecuteInRamFunctionInfo) && - (kFLASH_executeInRamFunctionTotalNum == flashExecuteInRamFunctionInfo->activeFunctionCount)) - { - return kStatus_FLASH_Success; - } - - return kStatus_FLASH_ExecuteInRamFunctionNotReady; -} -#endif -#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ - /*! @brief Validates the range and alignment of the given address range.*/ static status_t flash_check_range(flash_config_t *config, uint32_t startAddress, From 918b0bd37397fda1cdc4cc86f213faf98949f774 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 17 Sep 2021 17:59:19 -0500 Subject: [PATCH 290/617] Remove commented out code from fsl_flash.c --- source/hic_hal/freescale/iap/fsl_flash.c | 1450 ---------------------- 1 file changed, 1450 deletions(-) diff --git a/source/hic_hal/freescale/iap/fsl_flash.c b/source/hic_hal/freescale/iap/fsl_flash.c index 417afdfb9..1564de15c 100644 --- a/source/hic_hal/freescale/iap/fsl_flash.c +++ b/source/hic_hal/freescale/iap/fsl_flash.c @@ -256,34 +256,6 @@ static status_t flash_get_matched_operation_info(flash_config_t *config, /*! @brief Validates the given user key for flash erase APIs.*/ static status_t flash_check_user_key(uint32_t key); -// #if FLASH_SSD_IS_FLEXNVM_ENABLED -// /*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/ -// static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config); -// #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -// #if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD -// /*! @brief Validates the range of the given resource address.*/ -// static status_t flash_check_resource_range(uint32_t start, -// uint32_t lengthInBytes, -// uint32_t alignmentBaseline, -// flash_read_resource_option_t option); -// #endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ -// -// #if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD -// /*! @brief Validates the gived swap control option.*/ -// static status_t flash_check_swap_control_option(flash_swap_control_option_t option); -// #endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ -// -// #if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP -// /*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/ -// static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address); -// #endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ -// -// #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD -// /*! @brief Validates the gived flexram function option.*/ -// static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option); -// #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ - /******************************************************************************* * Variables ******************************************************************************/ @@ -526,72 +498,6 @@ status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBy return (returnCode); } -// #if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD -// status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key) -// { -// status_t returnCode; -// -// if (config == NULL) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// /* Prepare passing parameter to erase all flash blocks (unsecure). */ -// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_BLOCK_UNSECURE, 0xFFFFFFU); -// -// /* Validate the user key */ -// returnCode = flash_check_user_key(key); -// if (returnCode) -// { -// return returnCode; -// } -// -// /* calling flash command sequence function to execute the command */ -// returnCode = flash_command_sequence(config); -// -// flash_cache_clear(config); -// -// #if FLASH_SSD_IS_FLEXNVM_ENABLED -// /* Data flash IFR will be erased by erase all unsecure command, so we need to -// * update FlexNVM memory partition status synchronously */ -// if (returnCode == kStatus_FLASH_Success) -// { -// returnCode = flash_update_flexnvm_memory_partition_status(config); -// } -// #endif -// -// return returnCode; -// } -// #endif /* FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD */ -// -// status_t FLASH_EraseAllExecuteOnlySegments(flash_config_t *config, uint32_t key) -// { -// status_t returnCode; -// -// if (config == NULL) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// /* preparing passing parameter to erase all execute-only segments -// * 1st element for the FCCOB register */ -// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT, 0xFFFFFFU); -// -// /* Validate the user key */ -// returnCode = flash_check_user_key(key); -// if (returnCode) -// { -// return returnCode; -// } -// -// /* calling flash command sequence function to execute the command */ -// returnCode = flash_command_sequence(config); -// -// flash_cache_clear(config); -// -// return returnCode; -// } - status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes) { status_t returnCode; @@ -659,420 +565,6 @@ status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, ui return (returnCode); } -// status_t FLASH_ProgramOnce(flash_config_t *config, uint32_t index, uint32_t *src, uint32_t lengthInBytes) -// { -// status_t returnCode; -// -// if ((config == NULL) || (src == NULL)) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// /* pass paramters to FTFx */ -// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_PROGRAM_ONCE, index, 0xFFFFU); -// -// kFCCOBx[1] = *src; -// -// /* Note: Have to seperate the first index from the rest if it equals 0 -// * to avoid a pointless comparison of unsigned int to 0 compiler warning */ -// #if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT -// #if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT -// if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) || -// /* Range check */ -// ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) && -// (lengthInBytes == 8)) -// #endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */ -// { -// kFCCOBx[2] = *(src + 1); -// } -// #endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */ -// -// /* calling flash command sequence function to execute the command */ -// returnCode = flash_command_sequence(config); -// -// flash_cache_clear(config); -// -// return returnCode; -// } -// -// #if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD -// status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes) -// { -// status_t returnCode; -// uint32_t sectorSize; -// flash_operation_config_t flashInfo; -// #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD -// bool needSwitchFlexRamMode = false; -// #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ -// -// if (src == NULL) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// flash_get_matched_operation_info(config, start, &flashInfo); -// -// /* Check the supplied address range. */ -// returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectionCmdAddressAligment); -// if (returnCode) -// { -// return returnCode; -// } -// -// start = flashInfo.convertedAddress; -// sectorSize = flashInfo.activeSectorSize; -// -// #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD -// /* Switch function of FlexRAM if needed */ -// if (!(FTFx->FCNFG & FTFx_FCNFG_RAMRDY_MASK)) -// { -// needSwitchFlexRamMode = true; -// -// returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableAsRam); -// if (returnCode != kStatus_FLASH_Success) -// { -// return kStatus_FLASH_SetFlexramAsRamError; -// } -// } -// #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ -// -// while (lengthInBytes > 0) -// { -// /* Make sure the write operation doesn't span two sectors */ -// uint32_t endAddressOfCurrentSector = ALIGN_UP(start, sectorSize); -// uint32_t lengthTobeProgrammedOfCurrentSector; -// uint32_t currentOffset = 0; -// -// if (endAddressOfCurrentSector == start) -// { -// endAddressOfCurrentSector += sectorSize; -// } -// -// if (lengthInBytes + start > endAddressOfCurrentSector) -// { -// lengthTobeProgrammedOfCurrentSector = endAddressOfCurrentSector - start; -// } -// else -// { -// lengthTobeProgrammedOfCurrentSector = lengthInBytes; -// } -// -// /* Program Current Sector */ -// while (lengthTobeProgrammedOfCurrentSector > 0) -// { -// /* Make sure the program size doesn't exceeds Acceleration RAM size */ -// uint32_t programSizeOfCurrentPass; -// uint32_t numberOfPhases; -// -// if (lengthTobeProgrammedOfCurrentSector > kFLASH_accelerationRamSize) -// { -// programSizeOfCurrentPass = kFLASH_accelerationRamSize; -// } -// else -// { -// programSizeOfCurrentPass = lengthTobeProgrammedOfCurrentSector; -// } -// -// /* Copy data to FlexRAM */ -// memcpy((void *)FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS, src + currentOffset / 4, programSizeOfCurrentPass); -// /* Set start address of the data to be programmed */ -// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_SECTION, start + currentOffset); -// /* Set program size in terms of FEATURE_FLASH_SECTION_CMD_ADDRESS_ALIGMENT */ -// numberOfPhases = programSizeOfCurrentPass / flashInfo.sectionCmdAddressAligment; -// -// kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_2(numberOfPhases, 0xFFFFU); -// -// /* Peform command sequence */ -// returnCode = flash_command_sequence(config); -// -// /* calling flash callback function if it is available */ -// if (config->PFlashCallback) -// { -// config->PFlashCallback(); -// } -// -// if (returnCode != kStatus_FLASH_Success) -// { -// flash_cache_clear(config); -// return returnCode; -// } -// -// lengthTobeProgrammedOfCurrentSector -= programSizeOfCurrentPass; -// currentOffset += programSizeOfCurrentPass; -// } -// -// src += currentOffset / 4; -// start += currentOffset; -// lengthInBytes -= currentOffset; -// } -// -// flash_cache_clear(config); -// -// #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD -// /* Restore function of FlexRAM if needed. */ -// if (needSwitchFlexRamMode) -// { -// returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableForEeprom); -// if (returnCode != kStatus_FLASH_Success) -// { -// return kStatus_FLASH_RecoverFlexramAsEepromError; -// } -// } -// #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ -// -// return returnCode; -// } -// #endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD */ -// -// #if FLASH_SSD_IS_FLEXNVM_ENABLED -// status_t FLASH_EepromWrite(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) -// { -// status_t returnCode; -// bool needSwitchFlexRamMode = false; -// -// if (config == NULL) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// /* Validates the range of the given address */ -// if ((start < config->FlexRAMBlockBase) || -// ((start + lengthInBytes) > (config->FlexRAMBlockBase + config->EEpromTotalSize))) -// { -// return kStatus_FLASH_AddressError; -// } -// -// returnCode = kStatus_FLASH_Success; -// -// /* Switch function of FlexRAM if needed */ -// if (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK)) -// { -// needSwitchFlexRamMode = true; -// -// returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableForEeprom); -// if (returnCode != kStatus_FLASH_Success) -// { -// return kStatus_FLASH_SetFlexramAsEepromError; -// } -// } -// -// /* Write data to FlexRAM when it is used as EEPROM emulator */ -// while (lengthInBytes > 0) -// { -// if ((!(start & 0x3U)) && (lengthInBytes >= 4)) -// { -// *(uint32_t *)start = *(uint32_t *)src; -// start += 4; -// src += 4; -// lengthInBytes -= 4; -// } -// else if ((!(start & 0x1U)) && (lengthInBytes >= 2)) -// { -// *(uint16_t *)start = *(uint16_t *)src; -// start += 2; -// src += 2; -// lengthInBytes -= 2; -// } -// else -// { -// *(uint8_t *)start = *src; -// start += 1; -// src += 1; -// lengthInBytes -= 1; -// } -// /* Wait till EEERDY bit is set */ -// while (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK)) -// { -// } -// -// /* Check for protection violation error */ -// if (FTFx->FSTAT & FTFx_FSTAT_FPVIOL_MASK) -// { -// return kStatus_FLASH_ProtectionViolation; -// } -// } -// -// /* Switch function of FlexRAM if needed */ -// if (needSwitchFlexRamMode) -// { -// returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableAsRam); -// if (returnCode != kStatus_FLASH_Success) -// { -// return kStatus_FLASH_RecoverFlexramAsRamError; -// } -// } -// -// return returnCode; -// } -// #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ -// -// #if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD -// status_t FLASH_ReadResource( -// flash_config_t *config, uint32_t start, uint32_t *dst, uint32_t lengthInBytes, flash_read_resource_option_t option) -// { -// status_t returnCode; -// flash_operation_config_t flashInfo; -// -// if ((config == NULL) || (dst == NULL)) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// flash_get_matched_operation_info(config, start, &flashInfo); -// -// /* Check the supplied address range. */ -// returnCode = flash_check_resource_range(start, lengthInBytes, flashInfo.resourceCmdAddressAligment, option); -// if (returnCode != kStatus_FLASH_Success) -// { -// return returnCode; -// } -// -// while (lengthInBytes > 0) -// { -// /* preparing passing parameter */ -// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_READ_RESOURCE, start); -// if (flashInfo.resourceCmdAddressAligment == 4) -// { -// kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); -// } -// else if (flashInfo.resourceCmdAddressAligment == 8) -// { -// kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); -// } -// else -// { -// } -// -// /* calling flash command sequence function to execute the command */ -// returnCode = flash_command_sequence(config); -// -// if (kStatus_FLASH_Success != returnCode) -// { -// break; -// } -// -// /* fetch data */ -// *dst++ = kFCCOBx[1]; -// if (flashInfo.resourceCmdAddressAligment == 8) -// { -// *dst++ = kFCCOBx[2]; -// } -// /* update start address for next iteration */ -// start += flashInfo.resourceCmdAddressAligment; -// /* update lengthInBytes for next iteration */ -// lengthInBytes -= flashInfo.resourceCmdAddressAligment; -// } -// -// return (returnCode); -// } -// #endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ -// -// status_t FLASH_ReadOnce(flash_config_t *config, uint32_t index, uint32_t *dst, uint32_t lengthInBytes) -// { -// status_t returnCode; -// -// if ((config == NULL) || (dst == NULL)) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// /* pass paramters to FTFx */ -// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_READ_ONCE, index, 0xFFFFU); -// -// /* calling flash command sequence function to execute the command */ -// returnCode = flash_command_sequence(config); -// -// if (kStatus_FLASH_Success == returnCode) -// { -// *dst = kFCCOBx[1]; -// /* Note: Have to seperate the first index from the rest if it equals 0 -// * to avoid a pointless comparison of unsigned int to 0 compiler warning */ -// #if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT -// #if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT -// if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) || -// /* Range check */ -// ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) && -// (lengthInBytes == 8)) -// #endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */ -// { -// *(dst + 1) = kFCCOBx[2]; -// } -// #endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */ -// } -// -// return returnCode; -// } -// -// status_t FLASH_GetSecurityState(flash_config_t *config, flash_security_state_t *state) -// { -// /* store data read from flash register */ -// uint8_t registerValue; -// -// if ((config == NULL) || (state == NULL)) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// /* Get flash security register value */ -// registerValue = FTFx->FSEC; -// -// /* check the status of the flash security bits in the security register */ -// if (FLASH_SECURITY_STATE_UNSECURED == (registerValue & FTFx_FSEC_SEC_MASK)) -// { -// /* Flash in unsecured state */ -// *state = kFLASH_securityStateNotSecure; -// } -// else -// { -// /* Flash in secured state -// * check for backdoor key security enable bit */ -// if (FLASH_SECURITY_STATE_KEYEN == (registerValue & FTFx_FSEC_KEYEN_MASK)) -// { -// /* Backdoor key security enabled */ -// *state = kFLASH_securityStateBackdoorEnabled; -// } -// else -// { -// /* Backdoor key security disabled */ -// *state = kFLASH_securityStateBackdoorDisabled; -// } -// } -// -// return (kStatus_FLASH_Success); -// } -// -// status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey) -// { -// uint8_t registerValue; /* registerValue */ -// status_t returnCode; /* return code variable */ -// -// if ((config == NULL) || (backdoorKey == NULL)) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// /* set the default return code as kStatus_Success */ -// returnCode = kStatus_FLASH_Success; -// -// /* Get flash security register value */ -// registerValue = FTFx->FSEC; -// -// /* Check to see if flash is in secure state (any state other than 0x2) -// * If not, then skip this since flash is not secure */ -// if (0x02 != (registerValue & 0x03)) -// { -// /* preparing passing parameter to erase a flash block */ -// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SECURITY_BY_PASS, 0xFFFFFFU); -// kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[0], backdoorKey[1], backdoorKey[2], backdoorKey[3]); -// kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[4], backdoorKey[5], backdoorKey[6], backdoorKey[7]); -// -// /* calling flash command sequence function to execute the command */ -// returnCode = flash_command_sequence(config); -// } -// -// return (returnCode); -// } - status_t FLASH_VerifyEraseAll(flash_config_t *config, flash_margin_value_t margin) { if (config == NULL) @@ -1204,628 +696,6 @@ status_t FLASH_VerifyProgram(flash_config_t *config, return (returnCode); } -// status_t FLASH_VerifyEraseAllExecuteOnlySegments(flash_config_t *config, flash_margin_value_t margin) -// { -// if (config == NULL) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// /* preparing passing parameter to verify erase all execute-only segments command */ -// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT, margin, 0xFFFFU); -// -// /* calling flash command sequence function to execute the command */ -// return flash_command_sequence(config); -// } -// -// status_t FLASH_IsProtected(flash_config_t *config, -// uint32_t start, -// uint32_t lengthInBytes, -// flash_protection_state_t *protection_state) -// { -// uint32_t endAddress; /* end address for protection check */ -// uint32_t protectionRegionSize; /* size of flash protection region */ -// uint32_t regionCheckedCounter; /* increments each time the flash address was checked for -// * protection status */ -// uint32_t regionCounter; /* incrementing variable used to increment through the flash -// * protection regions */ -// uint32_t protectStatusCounter; /* increments each time a flash region was detected as protected */ -// -// uint8_t flashRegionProtectStatus[FSL_FEATURE_FTFx_REGION_COUNT]; /* array of the protection status for each -// * protection region */ -// uint32_t flashRegionAddress[FSL_FEATURE_FTFx_REGION_COUNT + 1]; /* array of the start addresses for each flash -// * protection region. Note this is REGION_COUNT+1 -// * due to requiring the next start address after -// * the end of flash for loop-check purposes below */ -// status_t returnCode; -// -// if (protection_state == NULL) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// /* Check the supplied address range. */ -// returnCode = flash_check_range(config, start, lengthInBytes, FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE); -// if (returnCode) -// { -// return returnCode; -// } -// -// /* calculating Flash end address */ -// endAddress = start + lengthInBytes; -// -// /* Calculate the size of the flash protection region -// * If the flash density is > 32KB, then protection region is 1/32 of total flash density -// * Else if flash density is < 32KB, then flash protection region is set to 1KB */ -// if (config->PFlashTotalSize > 32 * 1024) -// { -// protectionRegionSize = (config->PFlashTotalSize) / FSL_FEATURE_FTFx_REGION_COUNT; -// } -// else -// { -// protectionRegionSize = 1024; -// } -// -// /* populate the flashRegionAddress array with the start address of each flash region */ -// regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ -// -// /* populate up to 33rd element of array, this is the next address after end of flash array */ -// while (regionCounter <= FSL_FEATURE_FTFx_REGION_COUNT) -// { -// flashRegionAddress[regionCounter] = config->PFlashBlockBase + protectionRegionSize * regionCounter; -// regionCounter++; -// } -// -// /* populate flashRegionProtectStatus array with status information -// * Protection status for each region is stored in the FPROT[3:0] registers -// * Each bit represents one region of flash -// * 4 registers * 8-bits-per-register = 32-bits (32-regions) -// * The convention is: -// * FPROT3[bit 0] is the first protection region (start of flash memory) -// * FPROT0[bit 7] is the last protection region (end of flash memory) -// * regionCounter is used to determine which FPROT[3:0] register to check for protection status -// * Note: FPROT=1 means NOT protected, FPROT=0 means protected */ -// regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ -// while (regionCounter < FSL_FEATURE_FTFx_REGION_COUNT) -// { -// if (regionCounter < 8) -// { -// flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT3) >> regionCounter) & (0x01u); -// } -// else if ((regionCounter >= 8) && (regionCounter < 16)) -// { -// flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT2) >> (regionCounter - 8)) & (0x01u); -// } -// else if ((regionCounter >= 16) && (regionCounter < 24)) -// { -// flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT1) >> (regionCounter - 16)) & (0x01u); -// } -// else -// { -// flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT0) >> (regionCounter - 24)) & (0x01u); -// } -// regionCounter++; -// } -// -// /* loop through the flash regions and check -// * desired flash address range for protection status -// * loop stops when it is detected that start has exceeded the endAddress */ -// regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ -// regionCheckedCounter = 0; -// protectStatusCounter = 0; /* make sure protectStatusCounter is initialized to 0 first */ -// while (start < endAddress) -// { -// /* check to see if the address falls within this protection region -// * Note that if the entire flash is to be checked, the last protection -// * region checked would consist of the last protection start address and -// * the start address following the end of flash */ -// if ((start >= flashRegionAddress[regionCounter]) && (start < flashRegionAddress[regionCounter + 1])) -// { -// /* increment regionCheckedCounter to indicate this region was checked */ -// regionCheckedCounter++; -// -// /* check the protection status of this region -// * Note: FPROT=1 means NOT protected, FPROT=0 means protected */ -// if (!flashRegionProtectStatus[regionCounter]) -// { -// /* increment protectStatusCounter to indicate this region is protected */ -// protectStatusCounter++; -// } -// start += protectionRegionSize; /* increment to an address within the next region */ -// } -// regionCounter++; /* increment regionCounter to check for the next flash protection region */ -// } -// -// /* if protectStatusCounter == 0, then no region of the desired flash region is protected */ -// if (protectStatusCounter == 0) -// { -// *protection_state = kFLASH_protectionStateUnprotected; -// } -// /* if protectStatusCounter == regionCheckedCounter, then each region checked was protected */ -// else if (protectStatusCounter == regionCheckedCounter) -// { -// *protection_state = kFLASH_protectionStateProtected; -// } -// /* if protectStatusCounter != regionCheckedCounter, then protection status is mixed -// * In other words, some regions are protected while others are unprotected */ -// else -// { -// *protection_state = kFLASH_protectionStateMixed; -// } -// -// return (returnCode); -// } -// -// status_t FLASH_IsExecuteOnly(flash_config_t *config, -// uint32_t start, -// uint32_t lengthInBytes, -// flash_execute_only_access_state_t *access_state) -// { -// status_t returnCode; -// -// if (access_state == NULL) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// /* Check the supplied address range. */ -// returnCode = flash_check_range(config, start, lengthInBytes, FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE); -// if (returnCode) -// { -// return returnCode; -// } -// -// #if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL -// { -// uint32_t executeOnlySegmentCounter = 0; -// -// /* calculating end address */ -// uint32_t endAddress = start + lengthInBytes; -// -// /* Aligning start address and end address */ -// uint32_t alignedStartAddress = ALIGN_DOWN(start, config->PFlashAccessSegmentSize); -// uint32_t alignedEndAddress = ALIGN_UP(endAddress, config->PFlashAccessSegmentSize); -// -// uint32_t segmentIndex = 0; -// uint32_t maxSupportedExecuteOnlySegmentCount = -// (alignedEndAddress - alignedStartAddress) / config->PFlashAccessSegmentSize; -// -// while (start < endAddress) -// { -// uint32_t xacc; -// -// segmentIndex = start / config->PFlashAccessSegmentSize; -// -// if (segmentIndex < 32) -// { -// xacc = *(const volatile uint32_t *)&FTFx->XACCL3; -// } -// else if (segmentIndex < config->PFlashAccessSegmentCount) -// { -// xacc = *(const volatile uint32_t *)&FTFx->XACCH3; -// segmentIndex -= 32; -// } -// else -// { -// break; -// } -// -// /* Determine if this address range is in a execute-only protection flash segment. */ -// if ((~xacc) & (1u << segmentIndex)) -// { -// executeOnlySegmentCounter++; -// } -// -// start += config->PFlashAccessSegmentSize; -// } -// -// if (executeOnlySegmentCounter < 1u) -// { -// *access_state = kFLASH_accessStateUnLimited; -// } -// else if (executeOnlySegmentCounter < maxSupportedExecuteOnlySegmentCount) -// { -// *access_state = kFLASH_accessStateMixed; -// } -// else -// { -// *access_state = kFLASH_accessStateExecuteOnly; -// } -// } -// #else -// *access_state = kFLASH_accessStateUnLimited; -// #endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ -// -// return (returnCode); -// } - -// status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) -// { -// if ((config == NULL) || (value == NULL)) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// switch (whichProperty) -// { -// case kFLASH_propertyPflashSectorSize: -// *value = config->PFlashSectorSize; -// break; -// -// case kFLASH_propertyPflashTotalSize: -// *value = config->PFlashTotalSize; -// break; -// -// case kFLASH_propertyPflashBlockSize: -// *value = config->PFlashTotalSize / FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT; -// break; -// -// case kFLASH_propertyPflashBlockCount: -// *value = config->PFlashBlockCount; -// break; -// -// case kFLASH_propertyPflashBlockBaseAddr: -// *value = config->PFlashBlockBase; -// break; -// -// case kFLASH_propertyPflashFacSupport: -// #if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) -// *value = FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL; -// #else -// *value = 0; -// #endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ -// break; -// -// case kFLASH_propertyPflashAccessSegmentSize: -// *value = config->PFlashAccessSegmentSize; -// break; -// -// case kFLASH_propertyPflashAccessSegmentCount: -// *value = config->PFlashAccessSegmentCount; -// break; -// -// #if FLASH_SSD_IS_FLEXNVM_ENABLED -// case kFLASH_propertyDflashSectorSize: -// *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE; -// break; -// case kFLASH_propertyDflashTotalSize: -// *value = config->DFlashTotalSize; -// break; -// case kFLASH_propertyDflashBlockSize: -// *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE; -// break; -// case kFLASH_propertyDflashBlockCount: -// *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT; -// break; -// case kFLASH_propertyDflashBlockBaseAddr: -// *value = config->DFlashBlockBase; -// break; -// case kFLASH_propertyEepromTotalSize: -// *value = config->EEpromTotalSize; -// break; -// #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ -// -// default: /* catch inputs that are not recognized */ -// return kStatus_FLASH_UnknownProperty; -// } -// -// return kStatus_FLASH_Success; -// } - -// #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD -// status_t FLASH_SetFlexramFunction(flash_config_t *config, flash_flexram_function_option_t option) -// { -// status_t status; -// -// if (config == NULL) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// status = flasn_check_flexram_function_option_range(option); -// if (status != kStatus_FLASH_Success) -// { -// return status; -// } -// -// /* preparing passing parameter to verify all block command */ -// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_SET_FLEXRAM_FUNCTION, option, 0xFFFFU); -// -// /* calling flash command sequence function to execute the command */ -// return flash_command_sequence(config); -// } -// #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ -// -// #if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD -// status_t FLASH_SwapControl(flash_config_t *config, -// uint32_t address, -// flash_swap_control_option_t option, -// flash_swap_state_config_t *returnInfo) -// { -// status_t returnCode; -// -// if ((config == NULL) || (returnInfo == NULL)) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// if (address & (FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT - 1)) -// { -// return kStatus_FLASH_AlignmentError; -// } -// -// /* Make sure address provided is in the lower half of Program flash but not in the Flash Configuration Field */ -// if ((address >= (config->PFlashTotalSize / 2)) || -// ((address >= kFLASH_configAreaStart) && (address <= kFLASH_configAreaEnd))) -// { -// return kStatus_FLASH_SwapIndicatorAddressError; -// } -// -// /* Check the option. */ -// returnCode = flash_check_swap_control_option(option); -// if (returnCode) -// { -// return returnCode; -// } -// -// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SWAP_CONTROL, address); -// kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); -// -// returnCode = flash_command_sequence(config); -// -// returnInfo->flashSwapState = (flash_swap_state_t)FTFx->FCCOB5; -// returnInfo->currentSwapBlockStatus = (flash_swap_block_status_t)FTFx->FCCOB6; -// returnInfo->nextSwapBlockStatus = (flash_swap_block_status_t)FTFx->FCCOB7; -// -// return returnCode; -// } -// #endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ -// -// #if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP -// status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_function_option_t option) -// { -// flash_swap_state_config_t returnInfo; -// status_t returnCode; -// -// memset(&returnInfo, 0xFFU, sizeof(returnInfo)); -// -// do -// { -// returnCode = FLASH_SwapControl(config, address, kFLASH_swapControlOptionReportStatus, &returnInfo); -// if (returnCode != kStatus_FLASH_Success) -// { -// return returnCode; -// } -// -// if (kFLASH_swapFunctionOptionDisable == option) -// { -// if (returnInfo.flashSwapState == kFLASH_swapStateDisabled) -// { -// return kStatus_FLASH_Success; -// } -// else if (returnInfo.flashSwapState == kFLASH_swapStateUninitialized) -// { -// /* The swap system changed to the DISABLED state with Program flash block 0 -// * located at relative flash address 0x0_0000 */ -// returnCode = FLASH_SwapControl(config, address, kFLASH_swapControlOptionDisableSystem, &returnInfo); -// } -// else -// { -// /* Swap disable should be requested only when swap system is in the uninitialized state */ -// return kStatus_FLASH_SwapSystemNotInUninitialized; -// } -// } -// else -// { -// /* When first swap: the initial swap state is Uninitialized, flash swap inidicator address is unset, -// * the swap procedure should be Uninitialized -> Update-Erased -> Complete. -// * After the first swap has been completed, the flash swap inidicator address cannot be modified -// * unless EraseAllBlocks command is issued, the swap procedure is changed to Update -> Update-Erased -> -// * Complete. */ -// switch (returnInfo.flashSwapState) -// { -// case kFLASH_swapStateUninitialized: -// /* If current swap mode is Uninitialized, Initialize Swap to Initialized/READY state. */ -// returnCode = -// FLASH_SwapControl(config, address, kFLASH_swapControlOptionIntializeSystem, &returnInfo); -// break; -// case kFLASH_swapStateReady: -// /* Validate whether the address provided to the swap system is matched to -// * swap indicator address in the IFR */ -// returnCode = flash_validate_swap_indicator_address(config, address); -// if (returnCode == kStatus_FLASH_Success) -// { -// /* If current swap mode is Initialized/Ready, Initialize Swap to UPDATE state. */ -// returnCode = -// FLASH_SwapControl(config, address, kFLASH_swapControlOptionSetInUpdateState, &returnInfo); -// } -// break; -// case kFLASH_swapStateUpdate: -// /* If current swap mode is Update, Erase indicator sector in non active block -// * to proceed swap system to update-erased state */ -// returnCode = FLASH_Erase(config, address + (config->PFlashTotalSize >> 1), -// FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT, kFLASH_apiEraseKey); -// break; -// case kFLASH_swapStateUpdateErased: -// /* If current swap mode is Update or Update-Erased, progress Swap to COMPLETE State */ -// returnCode = -// FLASH_SwapControl(config, address, kFLASH_swapControlOptionSetInCompleteState, &returnInfo); -// break; -// case kFLASH_swapStateComplete: -// break; -// case kFLASH_swapStateDisabled: -// /* When swap system is in disabled state, We need to clear swap system back to uninitialized -// * by issuing EraseAllBlocks command */ -// returnCode = kStatus_FLASH_SwapSystemNotInUninitialized; -// break; -// default: -// returnCode = kStatus_FLASH_InvalidArgument; -// break; -// } -// } -// if (returnCode != kStatus_FLASH_Success) -// { -// break; -// } -// } while (!((kFLASH_swapStateComplete == returnInfo.flashSwapState) && (kFLASH_swapFunctionOptionEnable == option))); -// -// return returnCode; -// } -// #endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ -// -// #if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD -// status_t FLASH_ProgramPartition(flash_config_t *config, -// flash_partition_flexram_load_option_t option, -// uint32_t eepromDataSizeCode, -// uint32_t flexnvmPartitionCode) -// { -// status_t returnCode; -// -// if (config == NULL) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// /* eepromDataSizeCode[7:6], flexnvmPartitionCode[7:4] should be all 1'b0 -// * or it will cause access error. */ -// /* eepromDataSizeCode &= 0x3FU; */ -// /* flexnvmPartitionCode &= 0x0FU; */ -// -// /* preparing passing parameter to program the flash block */ -// kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_2_1(FTFx_PROGRAM_PARTITION, 0xFFFFU, option); -// kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_2(eepromDataSizeCode, flexnvmPartitionCode, 0xFFFFU); -// -// /* calling flash command sequence function to execute the command */ -// returnCode = flash_command_sequence(config); -// -// flash_cache_clear(config); -// -// #if FLASH_SSD_IS_FLEXNVM_ENABLED -// /* Data flash IFR will be updated by program partition command during reset sequence, -// * so we just set reserved values for partitioned FlexNVM size here */ -// config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED; -// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -// #endif -// -// return (returnCode); -// } -// #endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD */ -// -// status_t FLASH_PflashSetProtection(flash_config_t *config, uint32_t protectStatus) -// { -// if (config == NULL) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// *kFPROT = protectStatus; -// -// if (protectStatus != *kFPROT) -// { -// return kStatus_FLASH_CommandFailure; -// } -// -// return kStatus_FLASH_Success; -// } -// -// status_t FLASH_PflashGetProtection(flash_config_t *config, uint32_t *protectStatus) -// { -// if ((config == NULL) || (protectStatus == NULL)) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// *protectStatus = *kFPROT; -// -// return kStatus_FLASH_Success; -// } -// -// #if FLASH_SSD_IS_FLEXNVM_ENABLED -// status_t FLASH_DflashSetProtection(flash_config_t *config, uint8_t protectStatus) -// { -// if (config == NULL) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED)) -// { -// return kStatus_FLASH_CommandNotSupported; -// } -// -// FTFx->FDPROT = protectStatus; -// -// if (FTFx->FDPROT != protectStatus) -// { -// return kStatus_FLASH_CommandFailure; -// } -// -// return kStatus_FLASH_Success; -// } -// #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ -// -// #if FLASH_SSD_IS_FLEXNVM_ENABLED -// status_t FLASH_DflashGetProtection(flash_config_t *config, uint8_t *protectStatus) -// { -// if ((config == NULL) || (protectStatus == NULL)) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED)) -// { -// return kStatus_FLASH_CommandNotSupported; -// } -// -// *protectStatus = FTFx->FDPROT; -// -// return kStatus_FLASH_Success; -// } -// #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ -// -// #if FLASH_SSD_IS_FLEXNVM_ENABLED -// status_t FLASH_EepromSetProtection(flash_config_t *config, uint8_t protectStatus) -// { -// if (config == NULL) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED)) -// { -// return kStatus_FLASH_CommandNotSupported; -// } -// -// FTFx->FEPROT = protectStatus; -// -// if (FTFx->FEPROT != protectStatus) -// { -// return kStatus_FLASH_CommandFailure; -// } -// -// return kStatus_FLASH_Success; -// } -// #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ -// -// #if FLASH_SSD_IS_FLEXNVM_ENABLED -// status_t FLASH_EepromGetProtection(flash_config_t *config, uint8_t *protectStatus) -// { -// if ((config == NULL) || (protectStatus == NULL)) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED)) -// { -// return kStatus_FLASH_CommandNotSupported; -// } -// -// *protectStatus = FTFx->FEPROT; -// -// return kStatus_FLASH_Success; -// } -// #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - #if FLASH_DRIVER_IS_FLASH_RESIDENT /*! * @brief Run flash command @@ -2115,323 +985,3 @@ static status_t flash_check_user_key(uint32_t key) return kStatus_FLASH_Success; } - -// #if FLASH_SSD_IS_FLEXNVM_ENABLED -// /*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/ -// static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config) -// { -// struct -// { -// uint32_t reserved0; -// uint8_t FlexNVMPartitionCode; -// uint8_t EEPROMDataSetSize; -// uint16_t reserved1; -// } dataIFRReadOut; -// status_t returnCode; -// -// if (config == NULL) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// /* Get FlexNVM memory partition info from data flash IFR */ -// returnCode = FLASH_ReadResource(config, DFLASH_IFR_READRESOURCE_START_ADDRESS, (uint32_t *)&dataIFRReadOut, -// sizeof(dataIFRReadOut), kFLASH_resourceOptionFlashIfr); -// if (returnCode != kStatus_FLASH_Success) -// { -// return kStatus_FLASH_PartitionStatusUpdateFailure; -// } -// -// /* Fill out partitioned EEPROM size */ -// dataIFRReadOut.EEPROMDataSetSize &= 0x0FU; -// switch (dataIFRReadOut.EEPROMDataSetSize) -// { -// case 0x00U: -// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000; -// break; -// case 0x01U: -// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001; -// break; -// case 0x02U: -// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010; -// break; -// case 0x03U: -// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011; -// break; -// case 0x04U: -// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100; -// break; -// case 0x05U: -// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101; -// break; -// case 0x06U: -// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110; -// break; -// case 0x07U: -// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111; -// break; -// case 0x08U: -// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000; -// break; -// case 0x09U: -// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001; -// break; -// case 0x0AU: -// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010; -// break; -// case 0x0BU: -// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011; -// break; -// case 0x0CU: -// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100; -// break; -// case 0x0DU: -// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101; -// break; -// case 0x0EU: -// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110; -// break; -// case 0x0FU: -// config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111; -// break; -// default: -// config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED; -// break; -// } -// -// /* Fill out partitioned DFlash size */ -// dataIFRReadOut.FlexNVMPartitionCode &= 0x0FU; -// switch (dataIFRReadOut.FlexNVMPartitionCode) -// { -// case 0x00U: -// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 != 0xFFFFFFFF) -// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000; -// #else -// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 */ -// break; -// case 0x01U: -// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 != 0xFFFFFFFF) -// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001; -// #else -// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 */ -// break; -// case 0x02U: -// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 != 0xFFFFFFFF) -// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010; -// #else -// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 */ -// break; -// case 0x03U: -// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 != 0xFFFFFFFF) -// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011; -// #else -// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 */ -// break; -// case 0x04U: -// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 != 0xFFFFFFFF) -// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100; -// #else -// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 */ -// break; -// case 0x05U: -// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 != 0xFFFFFFFF) -// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101; -// #else -// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 */ -// break; -// case 0x06U: -// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 != 0xFFFFFFFF) -// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110; -// #else -// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 */ -// break; -// case 0x07U: -// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 != 0xFFFFFFFF) -// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111; -// #else -// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 */ -// break; -// case 0x08U: -// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 != 0xFFFFFFFF) -// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000; -// #else -// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 */ -// break; -// case 0x09U: -// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 != 0xFFFFFFFF) -// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001; -// #else -// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 */ -// break; -// case 0x0AU: -// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 != 0xFFFFFFFF) -// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010; -// #else -// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 */ -// break; -// case 0x0BU: -// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 != 0xFFFFFFFF) -// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011; -// #else -// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 */ -// break; -// case 0x0CU: -// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 != 0xFFFFFFFF) -// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100; -// #else -// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 */ -// break; -// case 0x0DU: -// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 != 0xFFFFFFFF) -// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101; -// #else -// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 */ -// break; -// case 0x0EU: -// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 != 0xFFFFFFFF) -// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110; -// #else -// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 */ -// break; -// case 0x0FU: -// #if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 != 0xFFFFFFFF) -// config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111; -// #else -// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -// #endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 */ -// break; -// default: -// config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; -// break; -// } -// -// return kStatus_FLASH_Success; -// } -// #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ - -// #if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD -// /*! @brief Validates the range of the given resource address.*/ -// static status_t flash_check_resource_range(uint32_t start, -// uint32_t lengthInBytes, -// uint32_t alignmentBaseline, -// flash_read_resource_option_t option) -// { -// status_t status; -// uint32_t maxReadbleAddress; -// -// if ((start & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1))) -// { -// return kStatus_FLASH_AlignmentError; -// } -// -// status = kStatus_FLASH_Success; -// -// maxReadbleAddress = start + lengthInBytes - 1; -// if (option == kFLASH_resourceOptionVersionId) -// { -// if ((start != kFLASH_resourceRangeVersionIdStart) || -// ((start + lengthInBytes - 1) != kFLASH_resourceRangeVersionIdEnd)) -// { -// status = kStatus_FLASH_InvalidArgument; -// } -// } -// else if (option == kFLASH_resourceOptionFlashIfr) -// { -// if (maxReadbleAddress < kFLASH_resourceRangePflashIfrSizeInBytes) -// { -// } -// #if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP -// else if ((start >= kFLASH_resourceRangePflashSwapIfrStart) && -// (maxReadbleAddress <= kFLASH_resourceRangePflashSwapIfrEnd)) -// { -// } -// #endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ -// else if ((start >= kFLASH_resourceRangeDflashIfrStart) && -// (maxReadbleAddress <= kFLASH_resourceRangeDflashIfrEnd)) -// { -// } -// else -// { -// status = kStatus_FLASH_InvalidArgument; -// } -// } -// else -// { -// status = kStatus_FLASH_InvalidArgument; -// } -// -// return status; -// } -// #endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ - -// #if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD -// /*! @brief Validates the gived swap control option.*/ -// static status_t flash_check_swap_control_option(flash_swap_control_option_t option) -// { -// if ((option == kFLASH_swapControlOptionIntializeSystem) || (option == kFLASH_swapControlOptionSetInUpdateState) || -// (option == kFLASH_swapControlOptionSetInCompleteState) || (option == kFLASH_swapControlOptionReportStatus) || -// (option == kFLASH_swapControlOptionDisableSystem)) -// { -// return kStatus_FLASH_Success; -// } -// -// return kStatus_FLASH_InvalidArgument; -// } -// #endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ -// -// #if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP -// /*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/ -// static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address) -// { -// flash_swap_ifr_field_config_t flashSwapIfrField; -// uint32_t swapIndicatorAddress; -// -// status_t returnCode; -// returnCode = FLASH_ReadResource(config, kFLASH_resourceRangePflashSwapIfrStart, (uint32_t *)&flashSwapIfrField, -// sizeof(flash_swap_ifr_field_config_t), kFLASH_resourceOptionFlashIfr); -// if (returnCode != kStatus_FLASH_Success) -// { -// return returnCode; -// } -// -// /* The high 2 byte value of Swap Indicator Address is stored in Program Flash Swap IFR Field, -// * the low 4 bit value of Swap Indicator Address is always 4'b0000 */ -// swapIndicatorAddress = -// (uint32_t)flashSwapIfrField.swapIndicatorAddress * FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT; -// if (address != swapIndicatorAddress) -// { -// return kStatus_FLASH_SwapIndicatorAddressError; -// } -// -// return returnCode; -// } -// #endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ -// -// #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD -// /*! @brief Validates the gived flexram function option.*/ -// static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option) -// { -// if ((option != kFLASH_flexramFunctionOptionAvailableAsRam) && -// (option != kFLASH_flexramFunctionOptionAvailableForEeprom)) -// { -// return kStatus_FLASH_InvalidArgument; -// } -// -// return kStatus_FLASH_Success; -// } -// #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ From edb6798638a3055a74e507411167db40fe80eb04 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 17 Sep 2021 21:53:49 -0500 Subject: [PATCH 291/617] Fix for micro:bit universal hex support - The extraneous store for load_unaligned_record seems to be a compiler issue. - The exit with HEX_PARSE_OK in the else clause seems very wrong. If the version does not match one should simply continue to the next line and not mark the whole buffer as processed. - The shadow_line content was never used only ever written to. --- source/daplink/drag-n-drop/intelhex.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/source/daplink/drag-n-drop/intelhex.c b/source/daplink/drag-n-drop/intelhex.c index fe222540b..065a7ed11 100644 --- a/source/daplink/drag-n-drop/intelhex.c +++ b/source/daplink/drag-n-drop/intelhex.c @@ -82,7 +82,7 @@ static uint8_t validate_checksum(hex_line_t *record) return (result == 0); } -static hex_line_t line = {0}, shadow_line = {0}; +static hex_line_t line = {0}; static uint32_t next_address_to_write = 0; static uint8_t low_nibble = 0, idx = 0, record_processed = 0, load_unaligned_record = 0; static uint16_t binary_version = 0; @@ -92,7 +92,6 @@ uint16_t board_id_hex_min __WEAK; void reset_hex_parser(void) { memset(line.buf, 0, sizeof(hex_line_t)); - memset(shadow_line.buf, 0, sizeof(hex_line_t)); next_address_to_write = 0; low_nibble = 0; idx = 0; @@ -157,11 +156,9 @@ hexfile_parse_status_t parse_hex_blob(const uint8_t *hex_blob, const uint32_t he case CUSTOM_METADATA_RECORD: binary_version = (uint16_t) line.data[0] << 8 | line.data[1]; break; + case DATA_RECORD: case CUSTOM_DATA_RECORD: - // keeping a record of the last hex record - memcpy(shadow_line.buf, line.buf, sizeof(hex_line_t)); - if (binary_version == 0 || (binary_version >= board_id_hex_min && binary_version <= board_id_hex)){ // Only save data from the correct binary // verify this is a continous block of memory or need to exit and dump @@ -169,6 +166,9 @@ hexfile_parse_status_t parse_hex_blob(const uint8_t *hex_blob, const uint32_t he load_unaligned_record = 1; status = HEX_PARSE_UNALIGNED; goto hex_parser_exit; + } else { + // This should be superfluous but it is necessary for GCC + load_unaligned_record = 0; } // move from line buffer back to input buffer @@ -178,10 +178,6 @@ hexfile_parse_status_t parse_hex_blob(const uint8_t *hex_blob, const uint32_t he // Save next address to write next_address_to_write = ((next_address_to_write & 0xffff0000) | line.address) + line.byte_count; } - else { - status = HEX_PARSE_OK; - goto hex_parser_exit; - } break; case EOF_RECORD: From fb4b2292981671c6441d08eec8e51c3a685f4390 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 18 Sep 2021 01:04:42 -0500 Subject: [PATCH 292/617] Fix for family reset on armcc Partial revert of [eb3fa9d2] --- source/target/target_family.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/source/target/target_family.c b/source/target/target_family.c index 54c919642..050928c4a 100644 --- a/source/target/target_family.c +++ b/source/target/target_family.c @@ -44,20 +44,20 @@ const target_family_descriptor_t g_sw_sysresetreq_family = { }; // Weak references to family definitions. -extern __WEAK const target_family_descriptor_t g_nxp_kinetis_kseries; -extern __WEAK const target_family_descriptor_t g_nxp_kinetis_lseries; -extern __WEAK const target_family_descriptor_t g_nxp_kinetis_k32w_series; -extern __WEAK const target_family_descriptor_t g_nxp_mimxrt; -extern __WEAK const target_family_descriptor_t g_nxp_rapid_iot; -extern __WEAK const target_family_descriptor_t g_nxp_lpc55xx_series; -extern __WEAK const target_family_descriptor_t g_nordic_nrf51; -extern __WEAK const target_family_descriptor_t g_nordic_nrf52; -extern __WEAK const target_family_descriptor_t g_realtek_rtl8195am; -extern __WEAK const target_family_descriptor_t g_ti_family; -extern __WEAK const target_family_descriptor_t g_wiznet_family; -extern __WEAK const target_family_descriptor_t g_renesas_family; -extern __WEAK const target_family_descriptor_t g_toshiba_tz_family; -extern __WEAK const target_family_descriptor_t g_ambiq_ama3b1kk; +__WEAK const target_family_descriptor_t g_nxp_kinetis_kseries = {0}; +__WEAK const target_family_descriptor_t g_nxp_kinetis_lseries = {0}; +__WEAK const target_family_descriptor_t g_nxp_kinetis_k32w_series = {0}; +__WEAK const target_family_descriptor_t g_nxp_mimxrt = {0}; +__WEAK const target_family_descriptor_t g_nxp_rapid_iot = {0}; +__WEAK const target_family_descriptor_t g_nxp_lpc55xx_series = {0}; +__WEAK const target_family_descriptor_t g_nordic_nrf51 = {0}; +__WEAK const target_family_descriptor_t g_nordic_nrf52 = {0}; +__WEAK const target_family_descriptor_t g_realtek_rtl8195am = {0}; +__WEAK const target_family_descriptor_t g_ti_family = {0}; +__WEAK const target_family_descriptor_t g_wiznet_family = {0}; +__WEAK const target_family_descriptor_t g_renesas_family = {0}; +__WEAK const target_family_descriptor_t g_toshiba_tz_family = {0}; +__WEAK const target_family_descriptor_t g_ambiq_ama3b1kk = {0}; //! @brief Terminator value for g_families list. //! From 6932f9d7a61124c1786b853bce00b1b745168822 Mon Sep 17 00:00:00 2001 From: carlosperate Date: Sun, 19 Sep 2021 22:57:43 +0100 Subject: [PATCH 293/617] Python 3 updates for generate_config.py script. --- tools/generate_config.py | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/tools/generate_config.py b/tools/generate_config.py index d36c03844..8b3a72bd4 100755 --- a/tools/generate_config.py +++ b/tools/generate_config.py @@ -17,6 +17,8 @@ # limitations under the License. # +from __future__ import print_function + import struct import argparse from intelhex import IntelHex @@ -38,7 +40,6 @@ def create_hex(filename, addr, auto_rst, automation_allowed, overflow_detect, detect_incompatible_target, pad_size): - file_format = 'hex' intel_hex = IntelHex() intel_hex.puts(addr, struct.pack(FORMAT, CFG_KEY, FORMAT_LENGTH, auto_rst, automation_allowed, overflow_detect, detect_incompatible_target)) @@ -46,8 +47,7 @@ def create_hex(filename, addr, auto_rst, automation_allowed, pad_byte_count = pad_size - (FORMAT_LENGTH % pad_size) pad_data = '\xFF' * pad_byte_count intel_hex.puts(pad_addr, pad_data) - with open(filename, 'wb') as f: - intel_hex.tofile(f, file_format) + intel_hex.write_hex_file(filename) def str_to_int(val): @@ -67,18 +67,18 @@ def str_to_int(val): def main(): args = parser.parse_args() - print "Output file %s" % args.output_file - print "Config Offset 0x%x" % args.addr + print("Output file %s" % args.output_file) + print("Config Offset 0x%x" % args.addr) if args.addr % MINIMUM_ALIGN != 0: - print "WARNING! Configuration is not on a 1K boundary" + print("WARNING! Configuration is not on a 1K boundary") if args.addr % args.pad != 0: - print "WARNING! Configuration is not aligned to pad size" - print "Settings:" - print " auto_rst: %i" % args.auto_rst - print " automation_allowed: %i" % args.automation_allowed - print " overflow_detect: %i" % args.overflow_detect - print " detect_incompatible_target: %i" % args.detect_incompatible_target - print "" + print("WARNING! Configuration is not aligned to pad size") + print("Settings:") + print(" auto_rst: %i" % args.auto_rst) + print(" automation_allowed: %i" % args.automation_allowed) + print(" overflow_detect: %i" % args.overflow_detect) + print(" detect_incompatible_target: %i" % args.detect_incompatible_target) + print("") create_hex(args.output_file, args.addr, args.auto_rst, args.automation_allowed, args.overflow_detect, args.detect_incompatible_target, args.pad) From a144d48093911fdc9df6f362236634fe79eb9459 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 21 Sep 2021 13:04:49 -0500 Subject: [PATCH 294/617] Fix MSD functionality with armclang flash_algo_valid() was optimized away. There is no NO_OPTIMIZE* macros for armclang (because feature does not currently exist). Moving default g_board_info value to a separate file seems to do the trick. --- records/daplink/target_board.yaml | 1 + source/target/target_board.c | 12 +--------- source/target/target_default.c | 37 +++++++++++++++++++++++++++++++ 3 files changed, 39 insertions(+), 11 deletions(-) create mode 100644 source/target/target_default.c diff --git a/records/daplink/target_board.yaml b/records/daplink/target_board.yaml index 24b9e9a92..0149e2629 100644 --- a/records/daplink/target_board.yaml +++ b/records/daplink/target_board.yaml @@ -4,3 +4,4 @@ common: sources: target: - source/target/target_board.c + - source/target/target_default.c diff --git a/source/target/target_board.c b/source/target/target_board.c index 520353889..6399815f2 100644 --- a/source/target/target_board.c +++ b/source/target/target_board.c @@ -1,6 +1,6 @@ /** * @file target_board.c - * @brief Implementation of target_family.h + * @brief Implementation of target_board.h * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -23,16 +23,6 @@ #include "target_board.h" #include "compiler.h" -// Default empty board info. -__WEAK -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "0000", - .daplink_url_name = "MBED HTM", - .daplink_drive_name = "DAPLINK ", - .daplink_target_url = "https://mbed.org/device/?code=@U?version=@V?target_id=@T", -}; - // Disable optimization of these functions. // // This is required because for the "no target" builds, the compiler sees g_board_info fields as diff --git a/source/target/target_default.c b/source/target/target_default.c new file mode 100644 index 000000000..c679fd269 --- /dev/null +++ b/source/target/target_default.c @@ -0,0 +1,37 @@ +/** + * @file target_default.c + * @brief Default target board info + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2021, Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "target_board.h" +#include "compiler.h" + +// g_board_info needed to be moved away from target_board.c to prevent +// compilers from make optimization decisions based on it. + +// Default empty board info. +__WEAK +const board_info_t g_board_info = { + .info_version = kBoardInfoVersion, + .board_id = "0000", + .daplink_url_name = "MBED HTM", + .daplink_drive_name = "DAPLINK ", + .daplink_target_url = "https://mbed.org/device/?code=@U?version=@V?target_id=@T", +}; From 783c1d8c4607e039d3bf1850bf98049aca9b2d33 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 20 Sep 2021 23:58:46 -0500 Subject: [PATCH 295/617] Fix UART regression with armcc --- records/hic_hal/k20dx.yaml | 9 +++++++++ records/hic_hal/k26f.yaml | 8 ++++++++ records/hic_hal/m48ssidae.yaml | 10 ++++++++++ records/hic_hal/stm32f103xb.yaml | 10 ++++++++++ records/tools/armcc.yaml | 2 -- source/hic_hal/maxim/max32620/system_max32620.c | 14 ++++++++++++++ source/hic_hal/maxim/max32620/uart.c | 4 ++-- source/hic_hal/maxim/max32625/system_max32625.c | 14 ++++++++++++++ source/hic_hal/maxim/max32625/uart.c | 4 ++-- 9 files changed, 69 insertions(+), 6 deletions(-) diff --git a/records/hic_hal/k20dx.yaml b/records/hic_hal/k20dx.yaml index 9188bb008..dbaac8081 100644 --- a/records/hic_hal/k20dx.yaml +++ b/records/hic_hal/k20dx.yaml @@ -33,6 +33,11 @@ tool_specific: hic_hal: - source/hic_hal/freescale/k20dx/armcc armcc: + misc: + asm_flags: + - --no_unaligned_access + c_flags: + - --no_unaligned_access sources: hic_hal: - source/hic_hal/freescale/k20dx/armcc @@ -40,6 +45,10 @@ tool_specific: misc: common_flags: - -mfpu=none + asm_flags: + - --no_unaligned_access + c_flags: + - --no_unaligned_access sources: hic_hal: - source/hic_hal/freescale/k20dx/armcc diff --git a/records/hic_hal/k26f.yaml b/records/hic_hal/k26f.yaml index d7cd05516..51b7b2344 100644 --- a/records/hic_hal/k26f.yaml +++ b/records/hic_hal/k26f.yaml @@ -40,12 +40,20 @@ tool_specific: - source/hic_hal/freescale/k26f/armcc armcc: misc: + asm_flags: + - --no_unaligned_access c_flags: + - --no_unaligned_access - --diag_suppress=66 # disable warning about enums not fitting in signed 32-bit sources: hic_hal: - source/hic_hal/freescale/k26f/armcc armclang: + misc: + asm_flags: + - --no_unaligned_access + c_flags: + - --no_unaligned_access sources: hic_hal: - source/hic_hal/freescale/k26f/armcc diff --git a/records/hic_hal/m48ssidae.yaml b/records/hic_hal/m48ssidae.yaml index eb7159d1c..7bc6011fd 100644 --- a/records/hic_hal/m48ssidae.yaml +++ b/records/hic_hal/m48ssidae.yaml @@ -28,10 +28,20 @@ tool_specific: hic_hal: - source/hic_hal/nuvoton/m48ssidae/armcc armcc: + misc: + asm_flags: + - --no_unaligned_access + c_flags: + - --no_unaligned_access sources: hic_hal: - source/hic_hal/nuvoton/m48ssidae/armcc armclang: + misc: + asm_flags: + - --no_unaligned_access + c_flags: + - --no_unaligned_access sources: hic_hal: - source/hic_hal/nuvoton/m48ssidae/armcc diff --git a/records/hic_hal/stm32f103xb.yaml b/records/hic_hal/stm32f103xb.yaml index b1ff0351b..e180d1c93 100644 --- a/records/hic_hal/stm32f103xb.yaml +++ b/records/hic_hal/stm32f103xb.yaml @@ -31,10 +31,20 @@ tool_specific: hic_hal: - source/hic_hal/stm32/stm32f103xb/armcc armcc: + misc: + asm_flags: + - --no_unaligned_access + c_flags: + - --no_unaligned_access sources: hic_hal: - source/hic_hal/stm32/stm32f103xb/armcc armclang: + misc: + asm_flags: + - --no_unaligned_access + c_flags: + - --no_unaligned_access sources: hic_hal: - source/hic_hal/stm32/stm32f103xb/armcc diff --git a/records/tools/armcc.yaml b/records/tools/armcc.yaml index e3265c496..6b36c2e58 100644 --- a/records/tools/armcc.yaml +++ b/records/tools/armcc.yaml @@ -9,7 +9,6 @@ tool_specific: misc: asm_flags: - -g - - --no_unaligned_access c_flags: - -O2 - -Ospace @@ -19,7 +18,6 @@ tool_specific: - --split_sections - --interleave - -g - - --no_unaligned_access ld_flags: - --bestdebug - --summary_stderr diff --git a/source/hic_hal/maxim/max32620/system_max32620.c b/source/hic_hal/maxim/max32620/system_max32620.c index 38966c5d6..ace08d480 100644 --- a/source/hic_hal/maxim/max32620/system_max32620.c +++ b/source/hic_hal/maxim/max32620/system_max32620.c @@ -291,6 +291,20 @@ __weak void SystemInit(void) /* Perform an initial trim of the internal ring oscillator */ CLKMAN_TrimRO(); +#if !defined (__CC_ARM) // Prevent Keil tools from calling these functions until post scatter load SystemCoreClockUpdate(); Board_Init(); +#endif /* ! __CC_ARM */ } + +#if defined ( __CC_ARM ) +extern void $Super$$main(void); +// This will be executed after the RAM initialization +void $Sub$$main(void) +{ + SystemCoreClockUpdate(); + Board_Init(); + // Call to main function + $Super$$main(); +} +#endif diff --git a/source/hic_hal/maxim/max32620/uart.c b/source/hic_hal/maxim/max32620/uart.c index a405e0191..0d4a9b4a5 100644 --- a/source/hic_hal/maxim/max32620/uart.c +++ b/source/hic_hal/maxim/max32620/uart.c @@ -135,7 +135,7 @@ int32_t uart_reset(void) /******************************************************************************/ int32_t uart_set_configuration(UART_Configuration *config) { - uint32_t ctrl; + uint32_t ctrl = 0; // Get current configuration; clearing parameters that may be configured here ctrl = CdcAcmUart->ctrl & ~(MXC_F_UART_CTRL_PARITY | @@ -183,7 +183,7 @@ int32_t uart_set_configuration(UART_Configuration *config) /******************************************************************************/ int32_t uart_get_configuration(UART_Configuration *config) { - uint32_t ctrl; + uint32_t ctrl = 0; // Capture current configuration ctrl = CdcAcmUart->ctrl; diff --git a/source/hic_hal/maxim/max32625/system_max32625.c b/source/hic_hal/maxim/max32625/system_max32625.c index f7433db58..1d2ac026a 100755 --- a/source/hic_hal/maxim/max32625/system_max32625.c +++ b/source/hic_hal/maxim/max32625/system_max32625.c @@ -284,6 +284,20 @@ __weak void SystemInit(void) /* Perform an initial trim of the internal ring oscillator */ CLKMAN_TrimRO(); +#if !defined (__CC_ARM) // Prevent Keil tools from calling these functions until post scatter load SystemCoreClockUpdate(); Board_Init(); +#endif /* ! __CC_ARM */ } + +#if defined ( __CC_ARM ) +extern void $Super$$main(void); +// This will be executed after the RAM initialization +void $Sub$$main(void) +{ + SystemCoreClockUpdate(); + Board_Init(); + // Call to main function + $Super$$main(); +} +#endif diff --git a/source/hic_hal/maxim/max32625/uart.c b/source/hic_hal/maxim/max32625/uart.c index e1f0035e2..acad019a5 100755 --- a/source/hic_hal/maxim/max32625/uart.c +++ b/source/hic_hal/maxim/max32625/uart.c @@ -237,7 +237,7 @@ int32_t uart_reset(void) /******************************************************************************/ int32_t uart_set_configuration(UART_Configuration *config) { - uint32_t ctrl; + uint32_t ctrl = 0; // Disable UART, clear FIFOs and configuration CdcAcmUart->ctrl = 0; @@ -286,7 +286,7 @@ int32_t uart_set_configuration(UART_Configuration *config) /******************************************************************************/ int32_t uart_get_configuration(UART_Configuration *config) { - uint32_t ctrl; + uint32_t ctrl = 0; // Capture current configuration ctrl = CdcAcmUart->ctrl; From 39f2a2280893ad6048b5d0a51cb291207efa2448 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 21 Sep 2021 23:26:23 -0500 Subject: [PATCH 296/617] armclang does not support --no_unaligned_access flag --- records/hic_hal/k20dx.yaml | 4 ---- records/hic_hal/k26f.yaml | 5 ----- records/hic_hal/m48ssidae.yaml | 5 ----- records/hic_hal/stm32f103xb.yaml | 5 ----- 4 files changed, 19 deletions(-) diff --git a/records/hic_hal/k20dx.yaml b/records/hic_hal/k20dx.yaml index dbaac8081..21bdaec14 100644 --- a/records/hic_hal/k20dx.yaml +++ b/records/hic_hal/k20dx.yaml @@ -45,10 +45,6 @@ tool_specific: misc: common_flags: - -mfpu=none - asm_flags: - - --no_unaligned_access - c_flags: - - --no_unaligned_access sources: hic_hal: - source/hic_hal/freescale/k20dx/armcc diff --git a/records/hic_hal/k26f.yaml b/records/hic_hal/k26f.yaml index 51b7b2344..d9426d350 100644 --- a/records/hic_hal/k26f.yaml +++ b/records/hic_hal/k26f.yaml @@ -49,11 +49,6 @@ tool_specific: hic_hal: - source/hic_hal/freescale/k26f/armcc armclang: - misc: - asm_flags: - - --no_unaligned_access - c_flags: - - --no_unaligned_access sources: hic_hal: - source/hic_hal/freescale/k26f/armcc diff --git a/records/hic_hal/m48ssidae.yaml b/records/hic_hal/m48ssidae.yaml index 7bc6011fd..4763d6de7 100644 --- a/records/hic_hal/m48ssidae.yaml +++ b/records/hic_hal/m48ssidae.yaml @@ -37,11 +37,6 @@ tool_specific: hic_hal: - source/hic_hal/nuvoton/m48ssidae/armcc armclang: - misc: - asm_flags: - - --no_unaligned_access - c_flags: - - --no_unaligned_access sources: hic_hal: - source/hic_hal/nuvoton/m48ssidae/armcc diff --git a/records/hic_hal/stm32f103xb.yaml b/records/hic_hal/stm32f103xb.yaml index e180d1c93..3b7e51ef8 100644 --- a/records/hic_hal/stm32f103xb.yaml +++ b/records/hic_hal/stm32f103xb.yaml @@ -40,11 +40,6 @@ tool_specific: hic_hal: - source/hic_hal/stm32/stm32f103xb/armcc armclang: - misc: - asm_flags: - - --no_unaligned_access - c_flags: - - --no_unaligned_access sources: hic_hal: - source/hic_hal/stm32/stm32f103xb/armcc From 24f6836ac44ec9b8eba64e6fe0fa87b83caf53cd Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 21 Sep 2021 09:21:47 -0500 Subject: [PATCH 297/617] Recover performance for block-aligned uhex images --- source/daplink/drag-n-drop/intelhex.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/source/daplink/drag-n-drop/intelhex.c b/source/daplink/drag-n-drop/intelhex.c index 065a7ed11..3ef080e6e 100644 --- a/source/daplink/drag-n-drop/intelhex.c +++ b/source/daplink/drag-n-drop/intelhex.c @@ -106,6 +106,8 @@ hexfile_parse_status_t parse_hex_blob(const uint8_t *hex_blob, const uint32_t he hexfile_parse_status_t status = HEX_PARSE_UNINIT; // reset the amount of data that is being return'd *bin_buf_cnt = (uint32_t)0; + // Check if hex blob is aligned on a line boundary + uint8_t block_aligned = ((hex_blob[hex_blob_size - 1] == '\n') || (hex_blob[hex_blob_size - 1] == '\r')) ? 1 : 0; // we had an exit state where the address was unaligned to the previous record and data count. // Need to pop the last record into the buffer before decoding anthing else since it was @@ -177,6 +179,10 @@ hexfile_parse_status_t parse_hex_blob(const uint8_t *hex_blob, const uint32_t he *bin_buf_cnt = (uint32_t)(*bin_buf_cnt) + line.byte_count; // Save next address to write next_address_to_write = ((next_address_to_write & 0xffff0000) | line.address) + line.byte_count; + } else if (block_aligned) { + // If hex buffer is aligned on line boundary we can skip until next block + status = HEX_PARSE_OK; + goto hex_parser_exit; } break; From 0c760d07b1428631953001120391d300b63cb4ad Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 21 Sep 2021 11:01:30 -0500 Subject: [PATCH 298/617] Recover performance for sector-aligned uhex images --- source/daplink/drag-n-drop/intelhex.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/source/daplink/drag-n-drop/intelhex.c b/source/daplink/drag-n-drop/intelhex.c index 3ef080e6e..f729d9e9e 100644 --- a/source/daplink/drag-n-drop/intelhex.c +++ b/source/daplink/drag-n-drop/intelhex.c @@ -84,7 +84,7 @@ static uint8_t validate_checksum(hex_line_t *record) static hex_line_t line = {0}; static uint32_t next_address_to_write = 0; -static uint8_t low_nibble = 0, idx = 0, record_processed = 0, load_unaligned_record = 0; +static uint8_t low_nibble = 0, idx = 0, record_processed = 0, load_unaligned_record = 0, skip_until_aligned = 0; static uint16_t binary_version = 0; uint16_t board_id_hex __WEAK; uint16_t board_id_hex_min __WEAK; @@ -98,6 +98,7 @@ void reset_hex_parser(void) record_processed = 0; load_unaligned_record = 0; binary_version = 0; + skip_until_aligned = 0; } hexfile_parse_status_t parse_hex_blob(const uint8_t *hex_blob, const uint32_t hex_blob_size, uint32_t *hex_parse_cnt, uint8_t *bin_buf, const uint32_t bin_buf_size, uint32_t *bin_buf_address, uint32_t *bin_buf_cnt) @@ -108,6 +109,16 @@ hexfile_parse_status_t parse_hex_blob(const uint8_t *hex_blob, const uint32_t he *bin_buf_cnt = (uint32_t)0; // Check if hex blob is aligned on a line boundary uint8_t block_aligned = ((hex_blob[hex_blob_size - 1] == '\n') || (hex_blob[hex_blob_size - 1] == '\r')) ? 1 : 0; + if (skip_until_aligned) { + if (hex_blob[0] == ':') { + // This is block is aligned we can stop skipping + skip_until_aligned = 0; + } else { + // This is block is not aligned we can skip it + status = HEX_PARSE_OK; + goto hex_parser_exit; + } + } // we had an exit state where the address was unaligned to the previous record and data count. // Need to pop the last record into the buffer before decoding anthing else since it was @@ -179,8 +190,13 @@ hexfile_parse_status_t parse_hex_blob(const uint8_t *hex_blob, const uint32_t he *bin_buf_cnt = (uint32_t)(*bin_buf_cnt) + line.byte_count; // Save next address to write next_address_to_write = ((next_address_to_write & 0xffff0000) | line.address) + line.byte_count; - } else if (block_aligned) { - // If hex buffer is aligned on line boundary we can skip until next block + } else { + // If block is aligned on line we can skip until next block. + // Otherwise we assume it is sector aligned so we will have + // to start skipping block until we find one aligned on record. + if (!block_aligned) { + skip_until_aligned = 1; + } status = HEX_PARSE_OK; goto hex_parser_exit; } From 930ef1df6827f2a9af603e9d599bf33ff5a5818d Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 21 Sep 2021 11:29:21 -0500 Subject: [PATCH 299/617] Unify optimization for sector- and block-aligned uhex images --- source/daplink/drag-n-drop/intelhex.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/source/daplink/drag-n-drop/intelhex.c b/source/daplink/drag-n-drop/intelhex.c index f729d9e9e..3bf059cbb 100644 --- a/source/daplink/drag-n-drop/intelhex.c +++ b/source/daplink/drag-n-drop/intelhex.c @@ -107,8 +107,6 @@ hexfile_parse_status_t parse_hex_blob(const uint8_t *hex_blob, const uint32_t he hexfile_parse_status_t status = HEX_PARSE_UNINIT; // reset the amount of data that is being return'd *bin_buf_cnt = (uint32_t)0; - // Check if hex blob is aligned on a line boundary - uint8_t block_aligned = ((hex_blob[hex_blob_size - 1] == '\n') || (hex_blob[hex_blob_size - 1] == '\r')) ? 1 : 0; if (skip_until_aligned) { if (hex_blob[0] == ':') { // This is block is aligned we can stop skipping @@ -191,12 +189,10 @@ hexfile_parse_status_t parse_hex_blob(const uint8_t *hex_blob, const uint32_t he // Save next address to write next_address_to_write = ((next_address_to_write & 0xffff0000) | line.address) + line.byte_count; } else { - // If block is aligned on line we can skip until next block. - // Otherwise we assume it is sector aligned so we will have - // to start skipping block until we find one aligned on record. - if (!block_aligned) { - skip_until_aligned = 1; - } + // This is Universal Hex block that does not match our version. + // We can skip this block and all blocks until we find a + // block aligned on a record boundary. + skip_until_aligned = 1; status = HEX_PARSE_OK; goto hex_parser_exit; } From be7e2140a456fd33568d78de983f3bf80d7ab0e3 Mon Sep 17 00:00:00 2001 From: "Sadik.Ozer" Date: Mon, 23 Aug 2021 11:50:57 +0300 Subject: [PATCH 300/617] Add MAX32660EVSYS board Signed-off-by: Sadik.Ozer --- projects.yaml | 4 + records/board/max32660evsys.yaml | 6 ++ source/board/max32660evsys.c | 50 ++++++++++ source/family/maxim/max32660/flash_blob.c | 106 ++++++++++++++++++++++ source/family/maxim/max32660/target.c | 53 +++++++++++ test/info.py | 3 + 6 files changed, 222 insertions(+) create mode 100644 records/board/max32660evsys.yaml create mode 100644 source/board/max32660evsys.c create mode 100644 source/family/maxim/max32660/flash_blob.c create mode 100644 source/family/maxim/max32660/target.c diff --git a/projects.yaml b/projects.yaml index 8f8cf4e88..0ce30b70e 100644 --- a/projects.yaml +++ b/projects.yaml @@ -667,6 +667,10 @@ projects: - *module_if - *module_hic_max32625 - records/board/max32630fthr.yaml + max32625_max32660evsys_if: + - *module_if + - *module_hic_max32625 + - records/board/max32660evsys.yaml max32625_max32665hsp_if: - *module_if - *module_hic_max32625 diff --git a/records/board/max32660evsys.yaml b/records/board/max32660evsys.yaml new file mode 100644 index 000000000..4618eb02f --- /dev/null +++ b/records/board/max32660evsys.yaml @@ -0,0 +1,6 @@ +common: + sources: + board: + - source/board/max32660evsys.c + family: + - source/family/maxim/max32660/target.c diff --git a/source/board/max32660evsys.c b/source/board/max32660evsys.c new file mode 100644 index 000000000..267676028 --- /dev/null +++ b/source/board/max32660evsys.c @@ -0,0 +1,50 @@ +/** + * @file max32660evsys.c + * @brief board ID for the Maxim Integrated's MAX32660EVSYS + * + * DAPLink Interface Firmware + * + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* +*/ + +#include "target_family.h" +#include "target_board.h" + +const board_info_t g_board_info = { + .info_version = kBoardInfoVersion, + .board_id = "0421", + .family_id = kStub_HWReset_FamilyID, + .flags = kEnablePageErase, + .target_cfg = &target_device, + .daplink_url_name = "MAX32660HTM", + .daplink_target_url = "http://www.maximintegrated.com/max32660", +}; diff --git a/source/family/maxim/max32660/flash_blob.c b/source/family/maxim/max32660/flash_blob.c new file mode 100644 index 000000000..f4a4f6c6a --- /dev/null +++ b/source/family/maxim/max32660/flash_blob.c @@ -0,0 +1,106 @@ +/** + * @file flash_blob.c + * @brief Flash algorithm for the MAX32660 + * + * DAPLink Interface Firmware + * + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* +*/ + +#include "flash_blob.h" + +#define FLC_BASE 0x40029000 +#define CLK_DIV 0x00000060 +#define BRST_SIZE 0x00000080 +#define FLASH_BASE 0x00000000 +#define FLASH_SIZE KB(256) +#define FLASH_SECTOR KB(8) + +#define DEV_CFG_TARGET_ADDRESS (0x0000025cUL) // From flash_algo map file +#define FLASH_ALGO_GEN_ADDER 32 +#define DEV_CFG_LOCAL_ADDRESS ((uint8_t*)((unsigned int)flash_algo_blob + DEV_CFG_TARGET_ADDRESS + FLASH_ALGO_GEN_ADDER)) + +const uint32_t flash_algo_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x4603b510, 0x4893460c, 0x68414448, 0xf0006888, 0xb1087080, 0xbd102001, 0x4448488e, 0x60486880, + 0xe7f82000, 0x488b4602, 0x68414448, 0xf0206888, 0x60884070, 0x47702000, 0x44484886, 0x68886841, + 0x7080f000, 0x2001b108, 0x6a484770, 0x2000b148, 0x6a486248, 0x2002b128, 0x6a486248, 0x2001b108, + 0x6888e7f2, 0x4070f020, 0x5000f040, 0x20006088, 0xb510e7ea, 0x44484877, 0xf7ff6844, 0xb108ffdd, + 0xbd102001, 0xf42068a0, 0xf440407f, 0x60a0402a, 0xf04068a0, 0x60a00002, 0x68a0bf00, 0x7080f000, + 0xd1fa2800, 0xf02068a0, 0x60a04070, 0xf0006a60, 0xb1080002, 0xe7e42001, 0xe7e22000, 0x4605b570, + 0x44484864, 0xf7ff6844, 0xb108ffb7, 0xbd702001, 0xf42068a0, 0xf440407f, 0x60a040aa, 0x68a06025, + 0x0004f040, 0xbf0060a0, 0xf00068a0, 0x28007080, 0x68a0d1fa, 0x4070f020, 0x6a6060a0, 0x0002f000, + 0x2001b108, 0x2000e7e3, 0xe92de7e1, 0x460747f0, 0x4690468a, 0x4448484f, 0x46566844, 0xf0084645, + 0xb1100003, 0xe8bd2001, 0x464587f0, 0xff84f7ff, 0x2001b108, 0x68a0e7f7, 0x6000f020, 0x68a060a0, + 0x0010f040, 0xe00e60a0, 0xcd016027, 0x68a06320, 0x0001f040, 0xbf0060a0, 0xf00068a0, 0x28007080, + 0x1d3fd1fa, 0x2e041f36, 0xf007d303, 0x2800001f, 0x4838d1ea, 0x68c04448, 0xd1212880, 0xd31f2e10, + 0xf02068a0, 0x60a00010, 0xf04068a0, 0x60a06000, 0x6027e014, 0x6320cd01, 0x6360cd01, 0x63a0cd01, + 0x63e0cd01, 0xf04068a0, 0x60a00001, 0x68a0bf00, 0x7080f000, 0xd1fa2800, 0x3e103710, 0xd2e82e10, + 0xd3192e04, 0xf02068a0, 0x60a06000, 0xf04068a0, 0x60a00010, 0x6027e00e, 0x6320cd01, 0xf04068a0, + 0x60a00001, 0x68a0bf00, 0x7080f000, 0xd1fa2800, 0x1f361d3f, 0xd2ee2e04, 0x68a2b306, 0x6200f022, + 0x68a260a2, 0x0210f042, 0xf04f60a2, 0x21ff30ff, 0x682ae005, 0x0201ea62, 0x02094010, 0x2e001e76, + 0x6027d1f7, 0x68a26320, 0x0201f042, 0xbf0060a2, 0xf00268a2, 0x2a007280, 0xbf00d1fa, 0xf02068a0, + 0x60a04070, 0xf0006a60, 0xb1080002, 0xe76a2001, 0xe7682000, 0x00000004, 0x00000000, 0x00000000, + FLC_BASE, CLK_DIV, BRST_SIZE, FLASH_BASE, FLASH_SIZE, FLASH_SECTOR, +}; + +/** +* List of start and size for each size of flash sector +* The size will apply to all sectors between the listed address and the next address +* in the list. +* The last pair in the list will have sectors starting at that address and ending +* at address start + size. +*/ +static const sector_info_t sectors_info[] = { + {FLASH_BASE, FLASH_SECTOR}, + }; + +const program_target_t flash = { + 0x20000021, // Init + 0x20000045, // UnInit + 0x20000093, // EraseChip + 0x200000DD, // EraseSector + 0x2000012B, // ProgramPage + 0x00000000, // Verify + + // RSB : base address is address of Execution Region PrgData in map file + // to access global/static data + // RSP : Initial stack pointer + {0x20000001, 0x20000258 + FLASH_ALGO_GEN_ADDER, 0x20001000}, // {breakpoint, RSB, RSP} + + 0x20000400, // program_buffer + 0x20000000, // algo_start + sizeof(flash_algo_blob), // algo_size + flash_algo_blob, // image + + 512 // ram_to_flash_bytes_to_be_written +}; diff --git a/source/family/maxim/max32660/target.c b/source/family/maxim/max32660/target.c new file mode 100644 index 000000000..92dc81967 --- /dev/null +++ b/source/family/maxim/max32660/target.c @@ -0,0 +1,53 @@ +/** + * @file target.c + * @brief Target information for the MAX32660 + * + * DAPLink Interface Firmware + * + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* +*/ + +#include "target_config.h" + +#include "flash_blob.c" + +/* ME11 -- MAX32660 256KiB Flash, 96KiB RAM */ +target_cfg_t target_device = { + .sectors_info = sectors_info, + .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), + .flash_regions[0].start = 0x00000000, + .flash_regions[0].end = 0x00000000 + KB(256), + .flash_regions[0].flags = kRegionIsDefault, + .flash_regions[0].flash_algo = (program_target_t *) &flash, + .ram_regions[0].start = 0x20000000, + .ram_regions[0].end = 0x20000000 + KB(96), +}; diff --git a/test/info.py b/test/info.py index 8f21f2ce1..30e8314d9 100644 --- a/test/info.py +++ b/test/info.py @@ -130,6 +130,7 @@ ('max32620_max32625mbed_if', False, 0x0000, "bin" ), ('max32625_max32620fthr_if', False, 0x0000, "bin" ), ('max32625_max32630fthr_if', False, 0x0000, "bin" ), + ('max32625_max32660evsys_if', False, 0x0000, "bin" ), ('max32625_max32665hsp_if', False, 0x0000, "bin" ), ('kl26z_if', False, 0x0000, "bin" ), ('k20dx_if', False, 0x0000, "bin" ), @@ -195,6 +196,7 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0419, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32665hsp_if', 'max32625_bl', 'MAX32665' ), ( 0x0415, VENDOR_TO_FAMILY('Stub', 1), 'max32620_max32625mbed_if', 'max32620_bl', 'MAX32625' ), ( 0x0418, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32620fthr_if', 'max32625_bl', 'MAX32620' ), + ( 0x0421, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32660evsys_if', 'max32625_bl', 'MAX32660' ), ( 0x0450, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_ublox_odin_w2_if', None, None ), ( 0x0451, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_mxchip_emw3166_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0453, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_mts_xdot_if', None, None ), @@ -362,6 +364,7 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y 0x0415, # MAX32625MBED 0x0418, # MAX32620FTHR 0x0419, # MAX32665HSP + 0x0421, # MAX32660EVSYS 0x0450, # mtb_ublox_odin_w2 0x0456, # lpc11u35_mtb_murata_abz_078_if 0x0457, # lpc11u35_mtb_rak811_if From abc85cc4c016f6903d0986fa9b41460c7c64f557 Mon Sep 17 00:00:00 2001 From: "Sadik.Ozer" Date: Fri, 3 Sep 2021 14:16:41 +0300 Subject: [PATCH 301/617] Add custom reset for MAX32660 Signed-off-by: Sadik.Ozer --- records/board/max32660evsys.yaml | 1 + source/board/max32660evsys.c | 2 +- .../maxim/max32660/target_reset_max32660.c | 103 ++++++++++++++++++ source/target/target_family.c | 2 + source/target/target_family.h | 2 + 5 files changed, 109 insertions(+), 1 deletion(-) create mode 100644 source/family/maxim/max32660/target_reset_max32660.c diff --git a/records/board/max32660evsys.yaml b/records/board/max32660evsys.yaml index 4618eb02f..ad86523a4 100644 --- a/records/board/max32660evsys.yaml +++ b/records/board/max32660evsys.yaml @@ -4,3 +4,4 @@ common: - source/board/max32660evsys.c family: - source/family/maxim/max32660/target.c + - source/family/maxim/max32660/target_reset_max32660.c diff --git a/source/board/max32660evsys.c b/source/board/max32660evsys.c index 267676028..00651d0f9 100644 --- a/source/board/max32660evsys.c +++ b/source/board/max32660evsys.c @@ -42,7 +42,7 @@ const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "0421", - .family_id = kStub_HWReset_FamilyID, + .family_id = kMaxim_MAX32660_FamilyID, .flags = kEnablePageErase, .target_cfg = &target_device, .daplink_url_name = "MAX32660HTM", diff --git a/source/family/maxim/max32660/target_reset_max32660.c b/source/family/maxim/max32660/target_reset_max32660.c new file mode 100644 index 000000000..3efcd2b24 --- /dev/null +++ b/source/family/maxim/max32660/target_reset_max32660.c @@ -0,0 +1,103 @@ +/** + * @file target_reset.c + * @brief Target reset for the MAX32660 + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "target_family.h" +#include "swd_host.h" +#include "DAP_Config.h" +#include "target_board.h" + +#define DBG_Addr (0xe000edf0) // Default Core debug base addresses + +#define TARGET_MXC_BASE_FLC ((uint32_t)0x40029000UL) // Flash controller base address + +#define INCREASE_DELAY 10 +#define MAX_DELAY 30000 + + +/* RESET_PROGRAM state halts the processor on reset by default but the SWD + * is unavailable for 1024 clocks after reset. + * This code will reset and halt after the SWD lockout period. + */ +static uint8_t target_set_state_max32660(target_state_t state) +{ + unsigned int halt_timeout, halt_retries = 10; + unsigned int lockout_delay, i; + uint32_t val; + + if (state != RESET_PROGRAM) { + return swd_set_target_state_hw(state); + } + + /* Reset the target and halt it when SWD is available */ + while (halt_retries--) { + halt_timeout = 10; + lockout_delay = 0; + + /* Wait for SWD lockout period after reset */ + do { + swd_init(); + + PIN_nRESET_OUT(0); + for (i = 0; i < 1000; i++); + PIN_nRESET_OUT(1); + for (i = 0; i < lockout_delay; i++); + + lockout_delay += INCREASE_DELAY; + + } while ((JTAG2SWD() == 0) && (lockout_delay < MAX_DELAY)); + + if (lockout_delay >= MAX_DELAY) { + continue; + } + + if (!swd_write_dp(DP_CTRL_STAT, CSYSPWRUPREQ | CDBGPWRUPREQ | TRNNORMAL | MASKLANE)) { + continue; + } + + /* Dummy read here forces the line buffer to actually read flash the + * next time the flash memory base address has to be read. + * Generally, address read here should be an offset by atleast the size + * of line buffer (128 bytes) from the base address. + */ + uint8_t tmp; + swd_read_byte(g_board_info.target_cfg->flash_regions[0].start + 0x2000, &tmp); + + /* Set the Debug, and Halt bits and wait until core is halted or timeout */ + if (swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN | C_HALT)) { + do { + if (!swd_read_word(DBG_HCSR, &val)) { + break; + } + } while (((val & S_HALT) == 0) && (halt_timeout--)); + } + + if (val & S_HALT) { + return 1; + } + } + + return 0; +} + +const target_family_descriptor_t g_maxim_max32660 = { + .family_id = kMaxim_MAX32660_FamilyID, + .target_set_state = target_set_state_max32660, + .default_reset_type = kHardwareReset, +}; diff --git a/source/target/target_family.c b/source/target/target_family.c index 050928c4a..585e9b1e6 100644 --- a/source/target/target_family.c +++ b/source/target/target_family.c @@ -58,6 +58,7 @@ __WEAK const target_family_descriptor_t g_wiznet_family = {0}; __WEAK const target_family_descriptor_t g_renesas_family = {0}; __WEAK const target_family_descriptor_t g_toshiba_tz_family = {0}; __WEAK const target_family_descriptor_t g_ambiq_ama3b1kk = {0}; +__WEAK const target_family_descriptor_t g_maxim_max32660 = {0}; //! @brief Terminator value for g_families list. //! @@ -90,6 +91,7 @@ const target_family_descriptor_t *g_families[] = { &g_renesas_family, &g_toshiba_tz_family, &g_ambiq_ama3b1kk, + &g_maxim_max32660, FAMILY_LIST_TERMINATOR // list terminator }; diff --git a/source/target/target_family.h b/source/target/target_family.h index c780c63a2..bdb828e9b 100644 --- a/source/target/target_family.h +++ b/source/target/target_family.h @@ -61,6 +61,7 @@ enum _vendor_ids { kStub_VendorID = 0, kNXP_VendorID = 11, kTI_VendorID = 16, + kMaxim_VendorID = 23, kNordic_VendorID = 54, kToshiba_VendorID = 92, kRenesas_VendorID = 117, @@ -105,6 +106,7 @@ typedef enum _family_id { kWiznet_W7500_FamilyID = VENDOR_TO_FAMILY(kWiznet_VendorID, 1), kRenesas_FamilyID = VENDOR_TO_FAMILY(kRenesas_VendorID, 1), kAmbiq_ama3b1kk_FamilyID = VENDOR_TO_FAMILY(kAmbiq_VendorID, 1), + kMaxim_MAX32660_FamilyID = VENDOR_TO_FAMILY(kMaxim_VendorID, 4), } family_id_t; //! @brief Defines all characteristics of a device family. From a1a06ea1cc5fc1f246159d89de5c7c36140cb957 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 1 Oct 2021 12:12:21 -0500 Subject: [PATCH 302/617] git describe fallback when no tag present (fixes #857) --- tools/pre_build_script.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/pre_build_script.py b/tools/pre_build_script.py index 37ae5e83f..5e19c3977 100755 --- a/tools/pre_build_script.py +++ b/tools/pre_build_script.py @@ -63,7 +63,7 @@ def generate_version_file(version_git_dir): # Get the git description. print("#> Getting git description") try: - git_description = check_output("git describe HEAD", shell=True) + git_description = check_output("git describe HEAD --always --tags", shell=True) git_description = git_description.decode().strip() except: print("#> ERROR: Failed to get git description, do you have git.exe in your PATH environment variable?") From 89edbefea366f2faccc691c97536ab2bba714566 Mon Sep 17 00:00:00 2001 From: Keyur Hariya Date: Wed, 10 Mar 2021 10:49:58 -0600 Subject: [PATCH 303/617] Add custom reset for MAX32630 targets --- records/board/max32630fthr.yaml | 1 + source/board/max32630fthr.c | 2 +- source/family/maxim/max32630/target.c | 2 +- .../maxim/max32630/target_reset_max32630.c | 111 ++++++++++++++++++ source/target/target_family.c | 2 + source/target/target_family.h | 3 +- 6 files changed, 118 insertions(+), 3 deletions(-) create mode 100644 source/family/maxim/max32630/target_reset_max32630.c diff --git a/records/board/max32630fthr.yaml b/records/board/max32630fthr.yaml index ad0ca06cd..c7ec808d9 100644 --- a/records/board/max32630fthr.yaml +++ b/records/board/max32630fthr.yaml @@ -4,3 +4,4 @@ common: - source/board/max32630fthr.c family: - source/family/maxim/max32630/target.c + - source/family/maxim/max32630/target_reset_max32630.c diff --git a/source/board/max32630fthr.c b/source/board/max32630fthr.c index 05491f52a..8b277222b 100644 --- a/source/board/max32630fthr.c +++ b/source/board/max32630fthr.c @@ -25,7 +25,7 @@ const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "0409", - .family_id = kStub_HWReset_FamilyID, + .family_id = kMaxim_MAX32630_FamilyID, .flags = kEnablePageErase, .target_cfg = &target_device, }; diff --git a/source/family/maxim/max32630/target.c b/source/family/maxim/max32630/target.c index 5713bad56..ab2c347bb 100644 --- a/source/family/maxim/max32630/target.c +++ b/source/family/maxim/max32630/target.c @@ -30,7 +30,7 @@ target_cfg_t target_device = { .flash_regions[0].start = 0, .flash_regions[0].end = 0x200000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20080000, }; diff --git a/source/family/maxim/max32630/target_reset_max32630.c b/source/family/maxim/max32630/target_reset_max32630.c new file mode 100644 index 000000000..a2236c786 --- /dev/null +++ b/source/family/maxim/max32630/target_reset_max32630.c @@ -0,0 +1,111 @@ +/** + * @file target_reset.c + * @brief Target reset for the MAX32630 + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "target_family.h" +#include "swd_host.h" +#include "DAP_Config.h" +#include "target_board.h" + +#define DBG_Addr (0xe000edf0) // Default Core debug base addresses + +#define TARGET_MXC_BASE_FLC ((uint32_t)0x40002000UL) // Flash controller base address +#define TARGET_MXC_R_FLC_PERFORM (TARGET_MXC_BASE_FLC + (uint32_t)0x00000050UL) // Flash controller perform register + +#define INCREASE_DELAY 10 +#define MAX_DELAY 30000 + + +/* RESET_PROGRAM state halts the processor on reset by default but the SWD + * is unavailable for 1024 clocks after reset. + * This code will reset and halt after the SWD lockout period. + */ +static uint8_t target_set_state_max32630(target_state_t state) +{ + unsigned int halt_timeout, halt_retries = 10; + unsigned int lockout_delay, i; + uint32_t val; + + if (state != RESET_PROGRAM) { + return swd_set_target_state_hw(state); + } + + /* Reset the target and halt it when SWD is available */ + while (halt_retries--) { + halt_timeout = 10; + lockout_delay = 0; + + /* Wait for SWD lockout period after reset */ + do { + swd_init(); + + PIN_nRESET_OUT(0); + for (i = 0; i < 1000; i++); + PIN_nRESET_OUT(1); + for (i = 0; i < lockout_delay; i++); + + lockout_delay += INCREASE_DELAY; + + } while ((JTAG2SWD() == 0) && (lockout_delay < MAX_DELAY)); + + if (lockout_delay >= MAX_DELAY) { + continue; + } + + if (!swd_write_dp(DP_CTRL_STAT, CSYSPWRUPREQ | CDBGPWRUPREQ | TRNNORMAL | MASKLANE)) { + continue; + } + + /* Dummy read here forces the line buffer to actually read flash the + * next time the flash memory base address has to be read. + * Generally, address read here should be an offset by atleast the size + * of line buffer (128 bytes) from the base address. + */ + uint8_t tmp; + swd_read_byte(g_board_info.target_cfg->flash_regions[0].start + 0x2000, &tmp); + + /* Set the Debug, and Halt bits and wait until core is halted or timeout */ + if (swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN | C_HALT)) { + do { + if (!swd_read_word(DBG_HCSR, &val)) { + break; + } + } while (((val & S_HALT) == 0) && (halt_timeout--)); + } + + if (val & S_HALT) { + /* Setting the Flash Controller Perform register to 0 allows + * the Flash Controller pending bit to clear, otherwise the + * bit remains set which could fail flash operation. + */ + val = 0; + swd_write_word(TARGET_MXC_R_FLC_PERFORM, val); + + return 1; + } + } + + return 0; +} + +const target_family_descriptor_t g_maxim_max32630 = { + .family_id = kMaxim_MAX32630_FamilyID, + .target_set_state = target_set_state_max32630, + .default_reset_type = kHardwareReset, +}; diff --git a/source/target/target_family.c b/source/target/target_family.c index 585e9b1e6..1425d81e5 100644 --- a/source/target/target_family.c +++ b/source/target/target_family.c @@ -59,6 +59,7 @@ __WEAK const target_family_descriptor_t g_renesas_family = {0}; __WEAK const target_family_descriptor_t g_toshiba_tz_family = {0}; __WEAK const target_family_descriptor_t g_ambiq_ama3b1kk = {0}; __WEAK const target_family_descriptor_t g_maxim_max32660 = {0}; +__WEAK const target_family_descriptor_t g_maxim_max32630 = {0}; //! @brief Terminator value for g_families list. //! @@ -92,6 +93,7 @@ const target_family_descriptor_t *g_families[] = { &g_toshiba_tz_family, &g_ambiq_ama3b1kk, &g_maxim_max32660, + &g_maxim_max32630, FAMILY_LIST_TERMINATOR // list terminator }; diff --git a/source/target/target_family.h b/source/target/target_family.h index bdb828e9b..b4af8ef63 100644 --- a/source/target/target_family.h +++ b/source/target/target_family.h @@ -61,7 +61,7 @@ enum _vendor_ids { kStub_VendorID = 0, kNXP_VendorID = 11, kTI_VendorID = 16, - kMaxim_VendorID = 23, + kMaxim_VendorID = 23, kNordic_VendorID = 54, kToshiba_VendorID = 92, kRenesas_VendorID = 117, @@ -107,6 +107,7 @@ typedef enum _family_id { kRenesas_FamilyID = VENDOR_TO_FAMILY(kRenesas_VendorID, 1), kAmbiq_ama3b1kk_FamilyID = VENDOR_TO_FAMILY(kAmbiq_VendorID, 1), kMaxim_MAX32660_FamilyID = VENDOR_TO_FAMILY(kMaxim_VendorID, 4), + kMaxim_MAX32630_FamilyID = VENDOR_TO_FAMILY(kMaxim_VendorID, 2), } family_id_t; //! @brief Defines all characteristics of a device family. From 661490ba2577992a3a96a517fa8e57174347f01f Mon Sep 17 00:00:00 2001 From: Keyur Hariya Date: Wed, 10 Mar 2021 10:56:54 -0600 Subject: [PATCH 304/617] Cleanup --- source/family/maxim/max32630/flash_blob.c | 6 +++--- source/family/maxim/max32630/target.c | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/source/family/maxim/max32630/flash_blob.c b/source/family/maxim/max32630/flash_blob.c index e9193e1de..6326d43c8 100644 --- a/source/family/maxim/max32630/flash_blob.c +++ b/source/family/maxim/max32630/flash_blob.c @@ -25,8 +25,8 @@ #define CLK_DIV 0x00000060 #define BRST_SIZE 0x00000020 #define FLASH_BASE 0x00000000 -#define FLASH_SIZE 0x00200000 -#define FLASH_SECTOR 0x00002000 +#define FLASH_SIZE MB(2) +#define FLASH_SECTOR KB(8) #define DEV_CFG_TARGET_ADDRESS (0x0000025cUL) // From flash_algo map file #define FLASH_ALGO_GEN_ADDER 32 @@ -64,7 +64,7 @@ const uint32_t flash_algo_blob[] = { * at address start + size. */ static const sector_info_t sectors_info[] = { - {0, 0x2000}, + {FLASH_BASE, FLASH_SECTOR}, }; const program_target_t flash = { diff --git a/source/family/maxim/max32630/target.c b/source/family/maxim/max32630/target.c index ab2c347bb..736e9375c 100644 --- a/source/family/maxim/max32630/target.c +++ b/source/family/maxim/max32630/target.c @@ -23,14 +23,14 @@ #include "flash_blob.c" -/* ME03 -- MAX32630 2MiB Flash, 512KiB RAM */ +/* MAX32630 2MiB Flash, 512KiB RAM */ target_cfg_t target_device = { .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), - .flash_regions[0].start = 0, - .flash_regions[0].end = 0x200000, + .flash_regions[0].start = FLASH_BASE, + .flash_regions[0].end = FLASH_BASE + FLASH_SIZE, .flash_regions[0].flags = kRegionIsDefault, .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, - .ram_regions[0].end = 0x20080000, + .ram_regions[0].end = 0x20000000 + KB(512), }; From e42e04fbbb6dadd91d0901db99717a9d7bd58fa1 Mon Sep 17 00:00:00 2001 From: Keyur Hariya Date: Wed, 17 Mar 2021 15:41:42 -0500 Subject: [PATCH 305/617] Update flash algo blob This update uses the individual flash operation bits to check the status of flash instead of checking pending bit for all operations. --- source/family/maxim/max32630/flash_blob.c | 86 +++++++++++------------ 1 file changed, 40 insertions(+), 46 deletions(-) diff --git a/source/family/maxim/max32630/flash_blob.c b/source/family/maxim/max32630/flash_blob.c index 6326d43c8..4c899c7da 100644 --- a/source/family/maxim/max32630/flash_blob.c +++ b/source/family/maxim/max32630/flash_blob.c @@ -22,68 +22,62 @@ #include "flash_blob.h" #define FLC_BASE 0x40002000 -#define CLK_DIV 0x00000060 -#define BRST_SIZE 0x00000020 +#define CLOCK_DIV 0x00000060 +#define BURST_SIZE 0x00000020 #define FLASH_BASE 0x00000000 #define FLASH_SIZE MB(2) #define FLASH_SECTOR KB(8) -#define DEV_CFG_TARGET_ADDRESS (0x0000025cUL) // From flash_algo map file -#define FLASH_ALGO_GEN_ADDER 32 -#define DEV_CFG_LOCAL_ADDRESS ((uint8_t*)((unsigned int)flash_algo_blob + DEV_CFG_TARGET_ADDRESS + FLASH_ALGO_GEN_ADDER)) - -const uint32_t flash_algo_blob[] = { +static const uint32_t flash_algo_blob[] = { 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, - 0x4603b510, 0x4893460c, 0x68414448, 0xf0006888, 0xb1087080, 0xbd102001, 0x4448488e, 0x60486880, - 0xe7f82000, 0x488b4602, 0x68414448, 0xf0206888, 0x60884070, 0x47702000, 0x44484886, 0x68886841, - 0x7080f000, 0x2001b108, 0x6a484770, 0x2000b148, 0x6a486248, 0x2002b128, 0x6a486248, 0x2001b108, - 0x6888e7f2, 0x4070f020, 0x5000f040, 0x20006088, 0xb510e7ea, 0x44484877, 0xf7ff6844, 0xb108ffdd, - 0xbd102001, 0xf42068a0, 0xf440407f, 0x60a0402a, 0xf04068a0, 0x60a00002, 0x68a0bf00, 0x7080f000, - 0xd1fa2800, 0xf02068a0, 0x60a04070, 0xf0006a60, 0xb1080002, 0xe7e42001, 0xe7e22000, 0x4605b570, - 0x44484864, 0xf7ff6844, 0xb108ffb7, 0xbd702001, 0xf42068a0, 0xf440407f, 0x60a040aa, 0x68a06025, - 0x0004f040, 0xbf0060a0, 0xf00068a0, 0x28007080, 0x68a0d1fa, 0x4070f020, 0x6a6060a0, 0x0002f000, - 0x2001b108, 0x2000e7e3, 0xe92de7e1, 0x460747f0, 0x4690468a, 0x4448484f, 0x46566844, 0xf0084645, - 0xb1100003, 0xe8bd2001, 0x464587f0, 0xff84f7ff, 0x2001b108, 0x68a0e7f7, 0x6000f020, 0x68a060a0, - 0x0010f040, 0xe00e60a0, 0xcd016027, 0x68a06320, 0x0001f040, 0xbf0060a0, 0xf00068a0, 0x28007080, - 0x1d3fd1fa, 0x2e041f36, 0xf007d303, 0x2800001f, 0x4838d1ea, 0x68c04448, 0xd1212880, 0xd31f2e10, - 0xf02068a0, 0x60a00010, 0xf04068a0, 0x60a06000, 0x6027e014, 0x6320cd01, 0x6360cd01, 0x63a0cd01, - 0x63e0cd01, 0xf04068a0, 0x60a00001, 0x68a0bf00, 0x7080f000, 0xd1fa2800, 0x3e103710, 0xd2e82e10, - 0xd3192e04, 0xf02068a0, 0x60a06000, 0xf04068a0, 0x60a00010, 0x6027e00e, 0x6320cd01, 0xf04068a0, - 0x60a00001, 0x68a0bf00, 0x7080f000, 0xd1fa2800, 0x1f361d3f, 0xd2ee2e04, 0x68a2b306, 0x6200f022, - 0x68a260a2, 0x0210f042, 0xf04f60a2, 0x21ff30ff, 0x682ae005, 0x0201ea62, 0x02094010, 0x2e001e76, - 0x6027d1f7, 0x68a26320, 0x0201f042, 0xbf0060a2, 0xf00268a2, 0x2a007280, 0xbf00d1fa, 0xf02068a0, - 0x60a04070, 0xf0006a60, 0xb1080002, 0xe76a2001, 0xe7682000, 0x00000004, 0x00000000, 0x00000000, - FLC_BASE, CLK_DIV, BRST_SIZE, FLASH_BASE, FLASH_SIZE, FLASH_SECTOR, + 0x44494986, 0x68826808, 0x0f07f012, 0x2001bf1c, 0x68494770, 0x20006041, 0x48804770, 0x68004448, + 0xf0216881, 0x60814170, 0x47702000, 0xb510487b, 0x68044448, 0xf8d6f000, 0x68a0b9b0, 0x407ff420, + 0x402af440, 0x68a060a0, 0x0002f040, 0x68a060a0, 0x0f02f010, 0x68a0d1fb, 0x4070f020, 0x6a6060a0, + 0x0002f010, 0xbd10bf08, 0xbd102001, 0x4605b570, 0x4448486a, 0xf0006804, 0xb9b8f8b5, 0xf42068a0, + 0xf440407f, 0x60a040aa, 0x68a06025, 0x0004f040, 0x68a060a0, 0x0f04f010, 0x68a0d1fb, 0x4070f020, + 0x6a6060a0, 0x0002f010, 0xbd70bf08, 0xbd702001, 0x41f0e92d, 0x8164f8df, 0x44c8460d, 0xf8d84606, + 0x46174000, 0x0f03f012, 0xf000d17e, 0x2800f88b, 0x68a0d17a, 0x6000f020, 0x68a060a0, 0x0010f040, + 0xe00d60a0, 0xf8576026, 0x63200b04, 0xf04068a0, 0x60a00001, 0xf01068a0, 0xd1fb0f01, 0x1d361f2d, + 0xd3022d04, 0x0f1ff016, 0xf8d8d1ec, 0x28800008, 0x2d10d122, 0x68a0d320, 0x0010f020, 0x68a060a0, + 0x6000f040, 0x602660a0, 0x0b04f857, 0xf8576320, 0x63600b04, 0x0b04f857, 0xf85763a0, 0x63e00b04, + 0xf04068a0, 0x60a00001, 0xf01068a0, 0xd1fb0f01, 0x36103d10, 0xd2e62d10, 0xd3172d04, 0xf02068a0, + 0x60a06000, 0xf04068a0, 0x60a00010, 0xf8576026, 0x63200b04, 0xf04068a0, 0x60a00001, 0xf01068a0, + 0xd1fb0f01, 0x1d361f2d, 0xd2ef2d04, 0x68a0b1dd, 0x6000f020, 0x68a060a0, 0x0010f040, 0x683a60a0, + 0x31fff04f, 0xea6220ff, 0x40190300, 0x1e6d0200, 0x6026d1f9, 0x68a06321, 0x0001f040, 0x68a060a0, + 0x0f01f010, 0xe000d1fb, 0x68a0e009, 0x4070f020, 0x6a6060a0, 0x0002f010, 0xe8bdbf08, 0x200181f0, + 0x81f0e8bd, 0x4448480d, 0x68816800, 0x0f07f011, 0x6a41d109, 0x2100b149, 0x6a416241, 0x2102b129, + 0x6a416241, 0x2001b109, 0x68814770, 0x4170f021, 0x5100f041, 0x20006081, 0x00004770, 0x00000004, + 0x00000000, FLC_BASE, CLOCK_DIV, BURST_SIZE, }; /** -* List of start and size for each size of flash sector +* List of start and size for each size of flash sector - even indexes are start, odd are size * The size will apply to all sectors between the listed address and the next address * in the list. * The last pair in the list will have sectors starting at that address and ending -* at address start + size. +* at address flash_start + flash_size. */ static const sector_info_t sectors_info[] = { - {FLASH_BASE, FLASH_SECTOR}, - }; + FLASH_BASE, FLASH_SECTOR, +}; -const program_target_t flash = { +static const program_target_t flash = { 0x20000021, // Init - 0x20000045, // UnInit - 0x20000093, // EraseChip - 0x200000DD, // EraseSector - 0x2000012B, // ProgramPage + 0x2000003b, // UnInit + 0x2000004d, // EraseChip + 0x2000008d, // EraseSector + 0x200000d1, // ProgramPage 0x00000000, // Verify - // RSB : base address is address of Execution Region PrgData in map file - // to access global/static data - // RSP : Initial stack pointer - {0x20000001, 0x20000258 + FLASH_ALGO_GEN_ADDER, 0x20001000}, // {breakpoint, RSB, RSP} - - 0x20000400, // program_buffer - 0x20000000, // algo_start - sizeof(flash_algo_blob), // algo_size - flash_algo_blob, // image + { + 0x20000001, // BKPT : start of blob + 1 + 0x20000240, // RSB : blob start + header + rw data offset + 0x20000500 // RSP : stack pointer + }, - 512 // ram_to_flash_bytes_to_be_written + 0x20000000 + 0x00000A00, // mem buffer location + 0x20000000, // location to write prog_blob in target RAM + sizeof(flash_algo_blob), // prog_blob size + flash_algo_blob, // address of prog_blob + 0x00000400 // ram_to_flash_bytes_to_be_written }; From 776ae27f8b97e2e9e21ced66c14b97fcf5474aa3 Mon Sep 17 00:00:00 2001 From: Keyur Hariya Date: Thu, 25 Mar 2021 21:00:38 -0500 Subject: [PATCH 306/617] Change the MUX to other pins before reading voltage to avoid false reading --- source/hic_hal/maxim/max32625/gpio.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/source/hic_hal/maxim/max32625/gpio.c b/source/hic_hal/maxim/max32625/gpio.c index 36f87ffae..71a2b5161 100755 --- a/source/hic_hal/maxim/max32625/gpio.c +++ b/source/hic_hal/maxim/max32625/gpio.c @@ -228,16 +228,22 @@ void gpio_init(void) MXC_F_ADC_CTRL_ADC_REFBUF_PU | MXC_F_ADC_CTRL_ADC_CHGPUMP_PU); + // Change the MUX to other pins before measuring the voltage to avoid false reading + MXC_SETBIT(&MXC_GPIO->out_val[SWD_DIP_SEL_PORT], SWD_DIP_SEL_PIN); // High to connect Bn <-> Cn + uint16_t tmp_hdr_vio = readADC(HDR_VIO_CH); + + MXC_CLRBIT(&MXC_GPIO->out_val[SWD_DIP_SEL_PORT], SWD_DIP_SEL_PIN); // Low to connect Bn <-> An + uint16_t tmp_swd_vio = readADC(SWD_VIO_CH); + // Set IO interface - if (readADC(SWD_VIO_CH) > VIO_ADC_MIN) { + if (tmp_swd_vio > VIO_ADC_MIN) { target_set_interface(IO_SWD_EXT); - } else if (readADC(HDR_VIO_CH) > VIO_ADC_MIN) { + } else if (tmp_hdr_vio > VIO_ADC_MIN) { target_set_interface(IO_DIP_EXT); } else { // Default to SWD interface target_set_interface(IO_SWD_EXT); } - } /******************************************************************************/ From 2544630897ea8b60a3c0f780c28170d1f7ac8504 Mon Sep 17 00:00:00 2001 From: Keyur Hariya Date: Fri, 19 Mar 2021 12:32:45 -0500 Subject: [PATCH 307/617] Add custom reset for MAX32620 targets --- records/board/max32620fthr.yaml | 1 + source/board/max32620fthr.c | 2 +- .../maxim/max32620/target_reset_max32620.c | 111 ++++++++++++++++++ source/target/target_family.c | 2 + source/target/target_family.h | 1 + 5 files changed, 116 insertions(+), 1 deletion(-) create mode 100644 source/family/maxim/max32620/target_reset_max32620.c diff --git a/records/board/max32620fthr.yaml b/records/board/max32620fthr.yaml index 4c3c126b2..13519d0af 100644 --- a/records/board/max32620fthr.yaml +++ b/records/board/max32620fthr.yaml @@ -4,3 +4,4 @@ common: - source/board/max32620fthr.c family: - source/family/maxim/max32620/target.c + - source/family/maxim/max32620/target_reset_max32620.c \ No newline at end of file diff --git a/source/board/max32620fthr.c b/source/board/max32620fthr.c index e301176c4..6e7d42554 100644 --- a/source/board/max32620fthr.c +++ b/source/board/max32620fthr.c @@ -25,7 +25,7 @@ const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "0418", - .family_id = kStub_HWReset_FamilyID, + .family_id = kMaxim_MAX32620_FamilyID, .flags = kEnablePageErase, .target_cfg = &target_device, }; diff --git a/source/family/maxim/max32620/target_reset_max32620.c b/source/family/maxim/max32620/target_reset_max32620.c new file mode 100644 index 000000000..7315602c7 --- /dev/null +++ b/source/family/maxim/max32620/target_reset_max32620.c @@ -0,0 +1,111 @@ +/** + * @file target_reset.c + * @brief Target reset for the MAX32620 + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "target_family.h" +#include "swd_host.h" +#include "DAP_Config.h" +#include "target_board.h" + +#define DBG_Addr (0xe000edf0) // Default Core debug base addresses + +#define TARGET_MXC_BASE_FLC ((uint32_t)0x40002000UL) // Flash controller base address +#define TARGET_MXC_R_FLC_PERFORM (TARGET_MXC_BASE_FLC + (uint32_t)0x00000050UL) // Flash controller perform register + +#define INCREASE_DELAY 10 +#define MAX_DELAY 30000 + + +/* RESET_PROGRAM state halts the processor on reset by default but the SWD + * is unavailable for 1024 clocks after reset. + * This code will reset and halt after the SWD lockout period. + */ +static uint8_t target_set_state_max32620(target_state_t state) +{ + unsigned int halt_timeout, halt_retries = 10; + unsigned int lockout_delay, i; + uint32_t val; + + if (state != RESET_PROGRAM) { + return swd_set_target_state_hw(state); + } + + /* Reset the target and halt it when SWD is available */ + while (halt_retries--) { + halt_timeout = 10; + lockout_delay = 0; + + /* Wait for SWD lockout period after reset */ + do { + swd_init(); + + PIN_nRESET_OUT(0); + for (i = 0; i < 1000; i++); + PIN_nRESET_OUT(1); + for (i = 0; i < lockout_delay; i++); + + lockout_delay += INCREASE_DELAY; + + } while ((JTAG2SWD() == 0) && (lockout_delay < MAX_DELAY)); + + if (lockout_delay >= MAX_DELAY) { + continue; + } + + if (!swd_write_dp(DP_CTRL_STAT, CSYSPWRUPREQ | CDBGPWRUPREQ | TRNNORMAL | MASKLANE)) { + continue; + } + + /* Dummy read here forces the line buffer to actually read flash the + * next time the flash memory base address has to be read. + * Generally, address read here should be an offset by atleast the size + * of line buffer (128 bytes) from the base address. + */ + uint8_t tmp; + swd_read_byte(g_board_info.target_cfg->flash_regions[0].start + 0x2000, &tmp); + + /* Set the Debug, and Halt bits and wait until core is halted or timeout */ + if (swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN | C_HALT)) { + do { + if (!swd_read_word(DBG_HCSR, &val)) { + break; + } + } while (((val & S_HALT) == 0) && (halt_timeout--)); + } + + if (val & S_HALT) { + /* Setting the Flash Controller Perform register to 0 allows + * the Flash Controller pending bit to clear, otherwise the + * bit remains set which could fail flash operation. + */ + val = 0; + swd_write_word(TARGET_MXC_R_FLC_PERFORM, val); + + return 1; + } + } + + return 0; +} + +const target_family_descriptor_t g_maxim_max32620 = { + .family_id = kMaxim_MAX32620_FamilyID, + .target_set_state = target_set_state_max32620, + .default_reset_type = kHardwareReset, +}; diff --git a/source/target/target_family.c b/source/target/target_family.c index 1425d81e5..d92eb88d4 100644 --- a/source/target/target_family.c +++ b/source/target/target_family.c @@ -60,6 +60,7 @@ __WEAK const target_family_descriptor_t g_toshiba_tz_family = {0}; __WEAK const target_family_descriptor_t g_ambiq_ama3b1kk = {0}; __WEAK const target_family_descriptor_t g_maxim_max32660 = {0}; __WEAK const target_family_descriptor_t g_maxim_max32630 = {0}; +__WEAK const target_family_descriptor_t g_maxim_max32620 = {0}; //! @brief Terminator value for g_families list. //! @@ -94,6 +95,7 @@ const target_family_descriptor_t *g_families[] = { &g_ambiq_ama3b1kk, &g_maxim_max32660, &g_maxim_max32630, + &g_maxim_max32620, FAMILY_LIST_TERMINATOR // list terminator }; diff --git a/source/target/target_family.h b/source/target/target_family.h index b4af8ef63..5d318087d 100644 --- a/source/target/target_family.h +++ b/source/target/target_family.h @@ -108,6 +108,7 @@ typedef enum _family_id { kAmbiq_ama3b1kk_FamilyID = VENDOR_TO_FAMILY(kAmbiq_VendorID, 1), kMaxim_MAX32660_FamilyID = VENDOR_TO_FAMILY(kMaxim_VendorID, 4), kMaxim_MAX32630_FamilyID = VENDOR_TO_FAMILY(kMaxim_VendorID, 2), + kMaxim_MAX32620_FamilyID = VENDOR_TO_FAMILY(kMaxim_VendorID, 3), } family_id_t; //! @brief Defines all characteristics of a device family. From 0492822c36444573d12093135fdec6d1c21a0bfe Mon Sep 17 00:00:00 2001 From: Keyur Hariya Date: Fri, 19 Mar 2021 14:06:40 -0500 Subject: [PATCH 308/617] Cleanup --- source/family/maxim/max32620/flash_blob.c | 6 +++--- source/family/maxim/max32620/target.c | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/source/family/maxim/max32620/flash_blob.c b/source/family/maxim/max32620/flash_blob.c index 4a90aad95..628c481fd 100644 --- a/source/family/maxim/max32620/flash_blob.c +++ b/source/family/maxim/max32620/flash_blob.c @@ -25,8 +25,8 @@ #define CLK_DIV 0x00000060 #define BRST_SIZE 0x00000020 #define FLASH_BASE 0x00000000 -#define FLASH_SIZE 0x00200000 -#define FLASH_SECTOR 0x00002000 +#define FLASH_SIZE MB(2) +#define FLASH_SECTOR KB(8) #define DEV_CFG_TARGET_ADDRESS (0x0000025cUL) // From flash_algo map file #define FLASH_ALGO_GEN_ADDER 32 @@ -64,7 +64,7 @@ const uint32_t flash_algo_blob[] = { * at address start + size. */ static const sector_info_t sectors_info[] = { - {0, 0x2000}, + {FLASH_BASE, FLASH_SECTOR}, }; const program_target_t flash = { diff --git a/source/family/maxim/max32620/target.c b/source/family/maxim/max32620/target.c index ca12cc13f..5d3cb3cfe 100644 --- a/source/family/maxim/max32620/target.c +++ b/source/family/maxim/max32620/target.c @@ -23,14 +23,14 @@ #include "flash_blob.c" -/* ME02 -- MAX32620 2MiB Flash, 256KiB RAM */ +/* MAX32620 2MiB Flash, 256KiB RAM */ target_cfg_t target_device = { .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), - .flash_regions[0].start = 0, - .flash_regions[0].end = 0x200000, + .flash_regions[0].start = FLASH_BASE, + .flash_regions[0].end = FLASH_BASE + FLASH_SIZE, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, - .ram_regions[0].end = 0x20040000, + .ram_regions[0].end = 0x20000000 + KB(256), }; From bbd3fcaad68454a8a3abeb77a63f9b4ec7078450 Mon Sep 17 00:00:00 2001 From: Keyur Hariya Date: Fri, 19 Mar 2021 14:10:36 -0500 Subject: [PATCH 309/617] Update flash algo blob This update uses the individual flash operation bits to check the status of flash instead of checking pending bit for all operations. --- source/family/maxim/max32620/flash_blob.c | 86 +++++++++++------------ 1 file changed, 40 insertions(+), 46 deletions(-) diff --git a/source/family/maxim/max32620/flash_blob.c b/source/family/maxim/max32620/flash_blob.c index 628c481fd..901f7e202 100644 --- a/source/family/maxim/max32620/flash_blob.c +++ b/source/family/maxim/max32620/flash_blob.c @@ -22,68 +22,62 @@ #include "flash_blob.h" #define FLC_BASE 0x40002000 -#define CLK_DIV 0x00000060 -#define BRST_SIZE 0x00000020 +#define CLOCK_DIV 0x00000060 +#define BURST_SIZE 0x00000020 #define FLASH_BASE 0x00000000 #define FLASH_SIZE MB(2) #define FLASH_SECTOR KB(8) -#define DEV_CFG_TARGET_ADDRESS (0x0000025cUL) // From flash_algo map file -#define FLASH_ALGO_GEN_ADDER 32 -#define DEV_CFG_LOCAL_ADDRESS ((uint8_t*)((unsigned int)flash_algo_blob + DEV_CFG_TARGET_ADDRESS + FLASH_ALGO_GEN_ADDER)) - -const uint32_t flash_algo_blob[] = { +static const uint32_t flash_algo_blob[] = { 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, - 0x4603b510, 0x4893460c, 0x68414448, 0xf0006888, 0xb1087080, 0xbd102001, 0x4448488e, 0x60486880, - 0xe7f82000, 0x488b4602, 0x68414448, 0xf0206888, 0x60884070, 0x47702000, 0x44484886, 0x68886841, - 0x7080f000, 0x2001b108, 0x6a484770, 0x2000b148, 0x6a486248, 0x2002b128, 0x6a486248, 0x2001b108, - 0x6888e7f2, 0x4070f020, 0x5000f040, 0x20006088, 0xb510e7ea, 0x44484877, 0xf7ff6844, 0xb108ffdd, - 0xbd102001, 0xf42068a0, 0xf440407f, 0x60a0402a, 0xf04068a0, 0x60a00002, 0x68a0bf00, 0x7080f000, - 0xd1fa2800, 0xf02068a0, 0x60a04070, 0xf0006a60, 0xb1080002, 0xe7e42001, 0xe7e22000, 0x4605b570, - 0x44484864, 0xf7ff6844, 0xb108ffb7, 0xbd702001, 0xf42068a0, 0xf440407f, 0x60a040aa, 0x68a06025, - 0x0004f040, 0xbf0060a0, 0xf00068a0, 0x28007080, 0x68a0d1fa, 0x4070f020, 0x6a6060a0, 0x0002f000, - 0x2001b108, 0x2000e7e3, 0xe92de7e1, 0x460747f0, 0x4690468a, 0x4448484f, 0x46566844, 0xf0084645, - 0xb1100003, 0xe8bd2001, 0x464587f0, 0xff84f7ff, 0x2001b108, 0x68a0e7f7, 0x6000f020, 0x68a060a0, - 0x0010f040, 0xe00e60a0, 0xcd016027, 0x68a06320, 0x0001f040, 0xbf0060a0, 0xf00068a0, 0x28007080, - 0x1d3fd1fa, 0x2e041f36, 0xf007d303, 0x2800001f, 0x4838d1ea, 0x68c04448, 0xd1212880, 0xd31f2e10, - 0xf02068a0, 0x60a00010, 0xf04068a0, 0x60a06000, 0x6027e014, 0x6320cd01, 0x6360cd01, 0x63a0cd01, - 0x63e0cd01, 0xf04068a0, 0x60a00001, 0x68a0bf00, 0x7080f000, 0xd1fa2800, 0x3e103710, 0xd2e82e10, - 0xd3192e04, 0xf02068a0, 0x60a06000, 0xf04068a0, 0x60a00010, 0x6027e00e, 0x6320cd01, 0xf04068a0, - 0x60a00001, 0x68a0bf00, 0x7080f000, 0xd1fa2800, 0x1f361d3f, 0xd2ee2e04, 0x68a2b306, 0x6200f022, - 0x68a260a2, 0x0210f042, 0xf04f60a2, 0x21ff30ff, 0x682ae005, 0x0201ea62, 0x02094010, 0x2e001e76, - 0x6027d1f7, 0x68a26320, 0x0201f042, 0xbf0060a2, 0xf00268a2, 0x2a007280, 0xbf00d1fa, 0xf02068a0, - 0x60a04070, 0xf0006a60, 0xb1080002, 0xe76a2001, 0xe7682000, 0x00000004, 0x00000000, 0x00000000, - FLC_BASE, CLK_DIV, BRST_SIZE, FLASH_BASE, FLASH_SIZE, FLASH_SECTOR, + 0x44494986, 0x68826808, 0x0f07f012, 0x2001bf1c, 0x68494770, 0x20006041, 0x48804770, 0x68004448, + 0xf0216881, 0x60814170, 0x47702000, 0xb510487b, 0x68044448, 0xf8d6f000, 0x68a0b9b0, 0x407ff420, + 0x402af440, 0x68a060a0, 0x0002f040, 0x68a060a0, 0x0f02f010, 0x68a0d1fb, 0x4070f020, 0x6a6060a0, + 0x0002f010, 0xbd10bf08, 0xbd102001, 0x4605b570, 0x4448486a, 0xf0006804, 0xb9b8f8b5, 0xf42068a0, + 0xf440407f, 0x60a040aa, 0x68a06025, 0x0004f040, 0x68a060a0, 0x0f04f010, 0x68a0d1fb, 0x4070f020, + 0x6a6060a0, 0x0002f010, 0xbd70bf08, 0xbd702001, 0x41f0e92d, 0x8164f8df, 0x44c8460d, 0xf8d84606, + 0x46174000, 0x0f03f012, 0xf000d17e, 0x2800f88b, 0x68a0d17a, 0x6000f020, 0x68a060a0, 0x0010f040, + 0xe00d60a0, 0xf8576026, 0x63200b04, 0xf04068a0, 0x60a00001, 0xf01068a0, 0xd1fb0f01, 0x1d361f2d, + 0xd3022d04, 0x0f1ff016, 0xf8d8d1ec, 0x28800008, 0x2d10d122, 0x68a0d320, 0x0010f020, 0x68a060a0, + 0x6000f040, 0x602660a0, 0x0b04f857, 0xf8576320, 0x63600b04, 0x0b04f857, 0xf85763a0, 0x63e00b04, + 0xf04068a0, 0x60a00001, 0xf01068a0, 0xd1fb0f01, 0x36103d10, 0xd2e62d10, 0xd3172d04, 0xf02068a0, + 0x60a06000, 0xf04068a0, 0x60a00010, 0xf8576026, 0x63200b04, 0xf04068a0, 0x60a00001, 0xf01068a0, + 0xd1fb0f01, 0x1d361f2d, 0xd2ef2d04, 0x68a0b1dd, 0x6000f020, 0x68a060a0, 0x0010f040, 0x683a60a0, + 0x31fff04f, 0xea6220ff, 0x40190300, 0x1e6d0200, 0x6026d1f9, 0x68a06321, 0x0001f040, 0x68a060a0, + 0x0f01f010, 0xe000d1fb, 0x68a0e009, 0x4070f020, 0x6a6060a0, 0x0002f010, 0xe8bdbf08, 0x200181f0, + 0x81f0e8bd, 0x4448480d, 0x68816800, 0x0f07f011, 0x6a41d109, 0x2100b149, 0x6a416241, 0x2102b129, + 0x6a416241, 0x2001b109, 0x68814770, 0x4170f021, 0x5100f041, 0x20006081, 0x00004770, 0x00000004, + 0x00000000, FLC_BASE, CLOCK_DIV, BURST_SIZE, }; /** -* List of start and size for each size of flash sector +* List of start and size for each size of flash sector - even indexes are start, odd are size * The size will apply to all sectors between the listed address and the next address * in the list. * The last pair in the list will have sectors starting at that address and ending -* at address start + size. +* at address flash_start + flash_size. */ static const sector_info_t sectors_info[] = { - {FLASH_BASE, FLASH_SECTOR}, - }; + FLASH_BASE, FLASH_SECTOR, +}; -const program_target_t flash = { +static const program_target_t flash = { 0x20000021, // Init - 0x20000045, // UnInit - 0x20000093, // EraseChip - 0x200000DD, // EraseSector - 0x2000012B, // ProgramPage + 0x2000003b, // UnInit + 0x2000004d, // EraseChip + 0x2000008d, // EraseSector + 0x200000d1, // ProgramPage 0x00000000, // Verify - // RSB : base address is address of Execution Region PrgData in map file - // to access global/static data - // RSP : Initial stack pointer - {0x20000001, 0x20000258 + FLASH_ALGO_GEN_ADDER, 0x20001000}, // {breakpoint, RSB, RSP} - - 0x20000400, // program_buffer - 0x20000000, // algo_start - sizeof(flash_algo_blob), // algo_size - flash_algo_blob, // image + { + 0x20000001, // BKPT : start of blob + 1 + 0x20000240, // RSB : blob start + header + rw data offset + 0x20000500 // RSP : stack pointer + }, - 512 // ram_to_flash_bytes_to_be_written + 0x20000000 + 0x00000A00, // mem buffer location + 0x20000000, // location to write prog_blob in target RAM + sizeof(flash_algo_blob), // prog_blob size + flash_algo_blob, // address of prog_blob + 0x00000400 // ram_to_flash_bytes_to_be_written }; From 4afe159c47e75fd33c4ed8840dcacdffcc9a22a3 Mon Sep 17 00:00:00 2001 From: Keyur Hariya Date: Mon, 23 Aug 2021 15:25:07 -0500 Subject: [PATCH 310/617] Add newline at file end --- records/board/max32620fthr.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/records/board/max32620fthr.yaml b/records/board/max32620fthr.yaml index 13519d0af..07cf8cc93 100644 --- a/records/board/max32620fthr.yaml +++ b/records/board/max32620fthr.yaml @@ -4,4 +4,4 @@ common: - source/board/max32620fthr.c family: - source/family/maxim/max32620/target.c - - source/family/maxim/max32620/target_reset_max32620.c \ No newline at end of file + - source/family/maxim/max32620/target_reset_max32620.c From 201ccec1e6224da25a99f4d20ae2a1b2929f8d28 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 2 Oct 2021 00:10:31 -0500 Subject: [PATCH 311/617] Sorting projects in projects.yaml Sorted according to Python sort(), script provided --- projects.yaml | 575 +++++++++++++++++++++-------------------- tools/projects_sort.py | 64 +++++ 2 files changed, 353 insertions(+), 286 deletions(-) create mode 100755 tools/projects_sort.py diff --git a/projects.yaml b/projects.yaml index 0ce30b70e..8d4c77d0d 100644 --- a/projects.yaml +++ b/projects.yaml @@ -83,26 +83,7 @@ module: - records/hic_hal/m48ssidae.yaml projects: - kl26z_bl: - - *module_bl - - records/hic_hal/kl26z.yaml - - records/board/kl26z_bl.yaml - kl26z_if: - - *module_if - - *module_hic_kl26z - - records/family/all_family.yaml - kl27z_bl: - - *module_bl - - records/hic_hal/kl27z.yaml - - records/board/kl27z_bl.yaml - kl27z_if: - - *module_if - - *module_hic_kl27z - - records/family/all_family.yaml - kl27z_microbit_bl: - - *module_bl - - records/hic_hal/kl27z.yaml - - records/board/kl27z_microbit_bl.yaml + # HIC bootloaders and all target interfaces k20dx_bl: - *module_bl - records/hic_hal/k20dx.yaml @@ -119,6 +100,22 @@ projects: - *module_if - *module_hic_k26f - records/family/all_family.yaml + kl26z_bl: + - *module_bl + - records/hic_hal/kl26z.yaml + - records/board/kl26z_bl.yaml + kl26z_if: + - *module_if + - *module_hic_kl26z + - records/family/all_family.yaml + kl27z_bl: + - *module_bl + - records/hic_hal/kl27z.yaml + - records/board/kl27z_bl.yaml + kl27z_if: + - *module_if + - *module_hic_kl27z + - records/family/all_family.yaml lpc11u35_if: - *module_if - *module_hic_lpc11u35 @@ -141,6 +138,10 @@ projects: - *module_hic_lpc55s69 - records/board/lpc55s69_if.yaml # Sets the USB product string. - records/family/all_family.yaml + m48ssidae_bl: + - *module_bl + - records/hic_hal/m48ssidae.yaml + - records/board/m48ssidae_bl.yaml max32620_bl: - *module_bl - records/hic_hal/max32620.yaml @@ -176,26 +177,16 @@ projects: - *module_hic_stm32f103xb - records/family/all_family.yaml - records/usb/usb-bulk.yaml - sam3u2c_mkit_dk_dongle_nrf5x_if: - - *module_if - - *module_hic_sam3u2c - - records/board/mkit_dk_dongle_nrf5x.yaml - kl26z_microbit_if: - - *module_if - - *module_hic_kl26z - - records/board/microbit.yaml - kl27z_microbit_if: - - *module_if - - *module_hic_kl27z - - records/board/microbitv2.yaml - kl26z_nina_b1_if: + + # Other projects + k20dx_ep_agora_if: - *module_if - - *module_hic_kl26z - - records/board/nina_b1.yaml - kl26z_artemis_dk_if: + - *module_hic_k20dx + - records/board/ep_agora.yaml + k20dx_ep_kairos_if: - *module_if - - *module_hic_kl26z - - records/board/artemis_dk.yaml + - *module_hic_k20dx + - records/board/ep_kairos.yaml k20dx_frdmk20dx_if: - *module_if - *module_hic_k20dx @@ -204,26 +195,14 @@ projects: - *module_if - *module_hic_k20dx - records/board/frdmk22f.yaml - k20dx_frdmkw24d_if: - - *module_if - - *module_hic_k20dx - - records/board/frdmkw24d.yaml - k20dx_frdmkw41z_if: + k20dx_frdmk28f_if: - *module_if - *module_hic_k20dx - - records/board/frdmkw41z.yaml + - records/board/frdmk28f.yaml k20dx_frdmk64f_if: - *module_if - *module_hic_k20dx - records/board/frdmk64f.yaml - k20dx_hexiwear_if: - - *module_if - - *module_hic_k20dx - - records/board/hexiwear.yaml - k20dx_rapid_iot_if: - - *module_if - - *module_hic_k20dx - - records/board/rapid_iot.yaml k20dx_frdmk66f_if: - *module_if - *module_hic_k20dx @@ -232,10 +211,6 @@ projects: - *module_if - *module_hic_k20dx - records/board/frdmk82f.yaml - k20dx_frdmk28f_if: - - *module_if - - *module_hic_k20dx - - records/board/frdmk28f.yaml k20dx_frdmke15z_if: - *module_if - *module_hic_k20dx @@ -260,6 +235,10 @@ projects: - *module_if - *module_hic_k20dx - records/board/frdmkl27z.yaml + k20dx_frdmkl28z_if: + - *module_if + - *module_hic_k20dx + - records/board/frdmkl28z.yaml k20dx_frdmkl43z_if: - *module_if - *module_hic_k20dx @@ -268,38 +247,26 @@ projects: - *module_if - *module_hic_k20dx - records/board/frdmkl46z.yaml - k20dx_frdmkl28z_if: - - *module_if - - *module_hic_k20dx - - records/board/frdmkl28z.yaml k20dx_frdmkl82z_if: - *module_if - *module_hic_k20dx - records/board/frdmkl82z.yaml - k20dx_twrkl28z72m_if: - - *module_if - - *module_hic_k20dx - - records/board/twrkl28z72m.yaml - k20dx_twrke18f_if: - - *module_if - - *module_hic_k20dx - - records/board/twrke18f.yaml - k20dx_hvpke18f_if: + k20dx_frdmkw24d_if: - *module_if - *module_hic_k20dx - - records/board/hvpke18f.yaml - k20dx_rbl_if: + - records/board/frdmkw24d.yaml + k20dx_frdmkw41z_if: - *module_if - *module_hic_k20dx - - records/board/rbl.yaml - k20dx_rblnano_if: + - records/board/frdmkw41z.yaml + k20dx_hexiwear_if: - *module_if - *module_hic_k20dx - - records/board/rblnano.yaml - k20dx_xdot_l151_if: + - records/board/hexiwear.yaml + k20dx_hvpke18f_if: - *module_if - *module_hic_k20dx - - records/board/xDot-L151.yaml + - records/board/hvpke18f.yaml k20dx_mimxrt1020_evk_qspi_if: - *module_if - *module_hic_k20dx @@ -312,190 +279,206 @@ projects: - *module_if - *module_hic_k20dx - records/board/mimxrt1050_evk_qspi.yaml - k20dx_ep_agora_if: + k20dx_rapid_iot_if: - *module_if - *module_hic_k20dx - - records/board/ep_agora.yaml - k20dx_ep_kairos_if: + - records/board/rapid_iot.yaml + k20dx_rbl_if: - *module_if - *module_hic_k20dx - - records/board/ep_kairos.yaml + - records/board/rbl.yaml + k20dx_rblnano_if: + - *module_if + - *module_hic_k20dx + - records/board/rblnano.yaml + k20dx_twrke18f_if: + - *module_if + - *module_hic_k20dx + - records/board/twrke18f.yaml + k20dx_twrkl28z72m_if: + - *module_if + - *module_hic_k20dx + - records/board/twrkl28z72m.yaml + k20dx_xdot_l151_if: + - *module_if + - *module_hic_k20dx + - records/board/xDot-L151.yaml k26f_frdmk32w042_if: - *module_if - *module_hic_k26f - records/board/frdmk32w042.yaml - lpc11u35_ff1705_l151_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/FF1705_L151.yaml - lpc11u35_lpc812xpresso_if: + kl26z_artemis_dk_if: - *module_if - - *module_hic_lpc11u35 - - records/board/lpc812xpresso.yaml - lpc11u35_lpc824xpresso_if: + - *module_hic_kl26z + - records/board/artemis_dk.yaml + kl26z_microbit_if: - *module_if - - *module_hic_lpc11u35 - - records/board/lpc824xpresso.yaml - lpc4322_lpc54114xpresso_if: + - *module_hic_kl26z + - records/board/microbit.yaml + kl26z_nina_b1_if: - *module_if - - *module_hic_lpc4322 - - records/board/lpc54114xpresso.yaml - lpc4322_lpc54608xpresso_if: + - *module_hic_kl26z + - records/board/nina_b1.yaml + kl27z_microbit_bl: + - *module_bl + - records/hic_hal/kl27z.yaml + - records/board/kl27z_microbit_bl.yaml + kl27z_microbit_if: - *module_if - - *module_hic_lpc4322 - - records/board/lpc54608xpresso.yaml - lpc4322_lpc55s69xpresso_if: + - *module_hic_kl27z + - records/board/microbitv2.yaml + lpc11u35_6lowpan_borderrouterethernet_if: - *module_if - - *module_hic_lpc4322 - - records/board/lpc55S69xpresso.yaml - lpc11u35_ff_lpc546xx_if: + - *module_hic_lpc11u35 + - records/board/6LoWPAN_BorderRouterETHERNET.yaml + lpc11u35_6lowpan_borderrouterhat_if: - *module_if - *module_hic_lpc11u35 - - records/board/ff_lpc546xx.yaml - lpc11u35_lpc4088dm_if: + - records/board/6LoWPAN_BorderRouterHAT.yaml + lpc11u35_6lowpan_borderrouterusb_if: - *module_if - *module_hic_lpc11u35 - - records/board/lpc4088dm.yaml - lpc11u35_lpc4088qsb_if: + - records/board/6LoWPAN_BorderRouterUSB.yaml + lpc11u35_96b_nitrogen_if: - *module_if - *module_hic_lpc11u35 - - records/board/lpc4088qsb.yaml + - records/board/96b_nitrogen.yaml lpc11u35_archble_if: - *module_if - *module_hic_lpc11u35 - records/board/archble.yaml - lpc11u35_tiny_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/tiny.yaml - lpc11u35_archpro_if: + lpc11u35_archlink_if: - *module_if - *module_hic_lpc11u35 - - records/board/archpro.yaml + - records/board/archlink.yaml lpc11u35_archmax_if: - *module_if - *module_hic_lpc11u35 - records/board/archmax.yaml - lpc11u35_wio3g_if: + lpc11u35_archpro_if: - *module_if - *module_hic_lpc11u35 - - records/board/wio3g.yaml - lpc11u35_wiobg96_if: + - records/board/archpro.yaml + lpc11u35_arm_watch_efm32_if: - *module_if - *module_hic_lpc11u35 - - records/board/wiobg96.yaml - lpc11u35_hrm1017_if: + - records/board/arm_watch_efm32.yaml + lpc11u35_arm_watch_nrf51_if: - *module_if - *module_hic_lpc11u35 - - records/board/hrm1017.yaml - lpc11u35_sscity_if: + - records/board/arm_watch_nrf51.yaml + lpc11u35_arm_watch_stm32f411_if: - *module_if - *module_hic_lpc11u35 - - records/board/sscity.yaml - lpc11u35_ssci824_if: + - records/board/arm_watch_stm32f411.yaml + lpc11u35_blueninja_if: - *module_if - *module_hic_lpc11u35 - - records/board/ssci824.yaml - lpc11u35_ssci1114_if: + - records/board/blueninja.yaml + lpc11u35_c027_if: - *module_if - *module_hic_lpc11u35 - - records/board/ssci1114.yaml - lpc11u35_ssci_chibi_if: + - records/board/c027.yaml + lpc11u35_cocorico_if: - *module_if - *module_hic_lpc11u35 - - records/board/ssci_chibi.yaml - lpc11u35_ro359b_if: + - records/board/cocorico.yaml + lpc11u35_dipdap_cc3220sf_if: - *module_if - *module_hic_lpc11u35 - - records/board/ro359b.yaml - lpc11u35_c027_if: + - records/board/dipdap_cc3220sf.yaml + lpc11u35_dipdap_sdt32429b_if: - *module_if - *module_hic_lpc11u35 - - records/board/c027.yaml - lpc11u35_arm_watch_stm32f411_if: + - records/board/dipdap_sdt32429b.yaml + lpc11u35_dipdap_sdt32439b_if: - *module_if - *module_hic_lpc11u35 - - records/board/arm_watch_stm32f411.yaml - lpc11u35_arm_watch_efm32_if: + - records/board/dipdap_sdt32439b.yaml + lpc11u35_dipdap_sdt51822b_if: - *module_if - *module_hic_lpc11u35 - - records/board/arm_watch_efm32.yaml - lpc11u35_arm_watch_nrf51_if: + - records/board/dipdap_sdt51822b.yaml + lpc11u35_dipdap_sdt52832b_if: - *module_if - *module_hic_lpc11u35 - - records/board/arm_watch_nrf51.yaml - lpc11u35_archlink_if: + - records/board/dipdap_sdt52832b.yaml + lpc11u35_dipdap_sdt64b_if: - *module_if - *module_hic_lpc11u35 - - records/board/archlink.yaml - lpc11u35_6lowpan_borderrouterusb_if: + - records/board/dipdap_sdt64b.yaml + lpc11u35_ff1705_l151_if: - *module_if - *module_hic_lpc11u35 - - records/board/6LoWPAN_BorderRouterUSB.yaml - lpc11u35_6lowpan_borderrouterhat_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/6LoWPAN_BorderRouterHAT.yaml - lpc11u35_6lowpan_borderrouterethernet_if: + - records/board/FF1705_L151.yaml + lpc11u35_ff_lpc546xx_if: - *module_if - *module_hic_lpc11u35 - - records/board/6LoWPAN_BorderRouterETHERNET.yaml - lpc11u35_cocorico_if: + - records/board/ff_lpc546xx.yaml + lpc11u35_gr_lychee_if: - *module_if - *module_hic_lpc11u35 - - records/board/cocorico.yaml + - records/board/gr-lychee.yaml lpc11u35_gr_peach_if: - *module_if - *module_hic_lpc11u35 - records/board/gr-peach.yaml - lpc11u35_blueninja_if: + lpc11u35_hrm1017_if: - *module_if - *module_hic_lpc11u35 - - records/board/blueninja.yaml - lpc11u35_nz32_sc151_if: + - records/board/hrm1017.yaml + lpc11u35_lpc4088dm_if: - *module_if - *module_hic_lpc11u35 - - records/board/nz32_sc151.yaml - lpc11u35_wizwiki_w7500_if: + - records/board/lpc4088dm.yaml + lpc11u35_lpc4088qsb_if: - *module_if - *module_hic_lpc11u35 - - records/board/wizwiki_w7500.yaml - lpc11u35_wizwiki_w7500_eco_if: + - records/board/lpc4088qsb.yaml + lpc11u35_lpc812xpresso_if: - *module_if - *module_hic_lpc11u35 - - records/board/wizwiki_w7500_eco.yaml - lpc11u35_wizwiki_w7500p_if: + - records/board/lpc812xpresso.yaml + lpc11u35_lpc824xpresso_if: - *module_if - *module_hic_lpc11u35 - - records/board/wizwiki_w7500p.yaml + - records/board/lpc824xpresso.yaml lpc11u35_mbed_cloud_connect_if: - *module_if - *module_hic_lpc11u35 - records/board/mbed_cloud_connect.yaml - lpc11u35_rtl8195am_if: + lpc11u35_mini_iot_lpc54018_if: - *module_if - *module_hic_lpc11u35 - - records/board/rtl8195am.yaml - sam3u2c_ncs36510rf_if: + - records/board/mini_iot_lpc54018.yaml + lpc11u35_mtb_aconno_acn52832_if: - *module_if - - *module_hic_sam3u2c - - records/board/ncs36510rf.yaml - sam3u2c_ublox_evk_nina_b1_if: + - *module_hic_lpc11u35 + - records/board/mtb_aconno_acn52832.yaml + lpc11u35_mtb_laird_bl652_if: - *module_if - - *module_hic_sam3u2c - - records/board/ublox_evk_nina_b1.yaml - lpc11u35_vbluno51_if: + - *module_hic_lpc11u35 + - records/board/mtb_laird_bl652.yaml + lpc11u35_mtb_laird_bl654_if: - *module_if - *module_hic_lpc11u35 - - records/board/vbluno51.yaml - lpc11u35_mtconnect04s_if: + - records/board/mtb_laird_bl654.yaml + lpc11u35_mtb_mts_dragonfly_if: - *module_if - *module_hic_lpc11u35 - - records/board/mtconnect04s.yaml - lpc11u35_96b_nitrogen_if: + - records/board/mtb_mts_dragonfly.yaml + lpc11u35_mtb_mts_xdot_if: - *module_if - *module_hic_lpc11u35 - - records/board/96b_nitrogen.yaml + - records/board/mtb_mts_xdot.yaml + lpc11u35_mtb_murata_abz_078_if: + - *module_if + - *module_hic_lpc11u35 + - records/board/mtb_murata_abz_078.yaml + lpc11u35_mtb_murata_bl241_if: + - *module_if + - *module_hic_lpc11u35 + - records/board/mtb_murata_bl241.yaml lpc11u35_mtb_mxchip_emw3166_if: - *module_if - *module_hic_lpc11u35 @@ -504,157 +487,153 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/mtb_nina_b112.yaml - lpc11u35_mtb_murata_abz_078_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/mtb_murata_abz_078.yaml lpc11u35_mtb_rak811_if: - *module_if - *module_hic_lpc11u35 - records/board/mtb_rak811.yaml - lpc11u35_mtb_wise1510_if: + lpc11u35_mtb_stm32f439_if: - *module_if - *module_hic_lpc11u35 - - records/board/mtb_wise1510.yaml - lpc11u35_mtb_wise1530_if: + - records/board/mtb_stm32f439.yaml + lpc11u35_mtb_stm32l475_if: - *module_if - *module_hic_lpc11u35 - - records/board/mtb_wise1530.yaml - lpc11u35_mtb_wise1570_if: + - records/board/mtb_stm32l475.yaml + lpc11u35_mtb_stm_s2lp_if: - *module_if - *module_hic_lpc11u35 - - records/board/mtb_wise1570.yaml - lpc11u35_mtb_laird_bl652_if: + - records/board/mtb_stm_s2lp.yaml + lpc11u35_mtb_ublox_odin_w2_if: - *module_if - *module_hic_lpc11u35 - - records/board/mtb_laird_bl652.yaml + - records/board/mtb_ublox_odin_w2.yaml lpc11u35_mtb_usi_wm_bn_bm_22_if: - *module_if - *module_hic_lpc11u35 - records/board/mtb_usi_wm_bn_bm_22.yaml - lpc11u35_gr_lychee_if: + lpc11u35_mtb_wise1510_if: - *module_if - *module_hic_lpc11u35 - - records/board/gr-lychee.yaml - lpc11u35_dipdap_sdt32429b_if: + - records/board/mtb_wise1510.yaml + lpc11u35_mtb_wise1530_if: - *module_if - *module_hic_lpc11u35 - - records/board/dipdap_sdt32429b.yaml - lpc11u35_dipdap_sdt32439b_if: + - records/board/mtb_wise1530.yaml + lpc11u35_mtb_wise1570_if: - *module_if - *module_hic_lpc11u35 - - records/board/dipdap_sdt32439b.yaml - lpc11u35_dipdap_sdt64b_if: + - records/board/mtb_wise1570.yaml + lpc11u35_mtconnect04s_if: - *module_if - *module_hic_lpc11u35 - - records/board/dipdap_sdt64b.yaml - lpc11u35_dipdap_sdt51822b_if: + - records/board/mtconnect04s.yaml + lpc11u35_musca_a_if: - *module_if - *module_hic_lpc11u35 - - records/board/dipdap_sdt51822b.yaml - lpc11u35_dipdap_sdt52832b_if: + - records/board/musca_a.yaml + - records/tools/gcc_arm_lto.yaml + lpc11u35_musca_b_eflash_if: - *module_if - *module_hic_lpc11u35 - - records/board/dipdap_sdt52832b.yaml - lpc11u35_mtb_ublox_odin_w2_if: + - records/board/musca_b_eflash.yaml + - records/tools/gcc_arm_lto.yaml + lpc11u35_musca_b_if: - *module_if - *module_hic_lpc11u35 - - records/board/mtb_ublox_odin_w2.yaml - lpc11u35_mtb_mts_dragonfly_if: + - records/board/musca_b.yaml + - records/tools/gcc_arm_lto.yaml + lpc11u35_nz32_sc151_if: - *module_if - *module_hic_lpc11u35 - - records/board/mtb_mts_dragonfly.yaml - lpc11u35_mtb_mts_xdot_if: + - records/board/nz32_sc151.yaml + lpc11u35_ro359b_if: - *module_if - *module_hic_lpc11u35 - - records/board/mtb_mts_xdot.yaml - lpc11u35_dipdap_cc3220sf_if: + - records/board/ro359b.yaml + lpc11u35_rtl8195am_if: - *module_if - *module_hic_lpc11u35 - - records/board/dipdap_cc3220sf.yaml - stm32f103xb_stm32f103rb_if: - - *module_if - - *module_hic_stm32f103xb - - records/board/stm32f103rb.yaml - stm32f103xb_stm32f072rb_if: - - *module_if - - *module_hic_stm32f103xb - - records/board/stm32f072rb.yaml - stm32f103xb_stm32f334r8_if: - - *module_if - - *module_hic_stm32f103xb - - records/board/stm32f334r8.yaml - stm32f103xb_stm32f401re_if: - - *module_if - - *module_hic_stm32f103xb - - records/board/stm32f401re.yaml - stm32f103xb_stm32f411re_if: - - *module_if - - *module_hic_stm32f103xb - - records/board/stm32f411re.yaml - stm32f103xb_stm32f429zi_if: - - *module_if - - *module_hic_stm32f103xb - - records/board/stm32f429zi.yaml - stm32f103xb_ublox_evk_odin_w2_if: - - *module_if - - *module_hic_stm32f103xb - - records/board/ublox_evk_odin_w2.yaml - stm32f103xb_stm32l476rg_if: - - *module_if - - *module_hic_stm32f103xb - - records/board/stm32l476rg.yaml - stm32f103xb_stm32f746zg_if: + - records/board/rtl8195am.yaml + lpc11u35_ssci1114_if: - *module_if - - *module_hic_stm32f103xb - - records/board/stm32f746zg.yaml - stm32f103xb_stm32f207zg_if: + - *module_hic_lpc11u35 + - records/board/ssci1114.yaml + lpc11u35_ssci824_if: - *module_if - - *module_hic_stm32f103xb - - records/board/stm32f207zg.yaml - lpc11u35_mtb_laird_bl654_if: + - *module_hic_lpc11u35 + - records/board/ssci824.yaml + lpc11u35_ssci_chibi_if: - *module_if - *module_hic_lpc11u35 - - records/board/mtb_laird_bl654.yaml - lpc11u35_mtb_murata_bl241_if: + - records/board/ssci_chibi.yaml + lpc11u35_sscity_if: - *module_if - *module_hic_lpc11u35 - - records/board/mtb_murata_bl241.yaml - lpc11u35_mtb_stm_s2lp_if: + - records/board/sscity.yaml + lpc11u35_tiny_if: - *module_if - *module_hic_lpc11u35 - - records/board/mtb_stm_s2lp.yaml - lpc11u35_mini_iot_lpc54018_if: + - records/board/tiny.yaml + lpc11u35_vbluno51_if: - *module_if - *module_hic_lpc11u35 - - records/board/mini_iot_lpc54018.yaml - lpc11u35_mtb_stm32l475_if: + - records/board/vbluno51.yaml + lpc11u35_wio3g_if: - *module_if - *module_hic_lpc11u35 - - records/board/mtb_stm32l475.yaml - lpc11u35_mtb_aconno_acn52832_if: + - records/board/wio3g.yaml + lpc11u35_wio_emw3166_if: - *module_if - *module_hic_lpc11u35 - - records/board/mtb_aconno_acn52832.yaml - lpc11u35_mtb_stm32f439_if: + - records/board/wio_emw3166.yaml + lpc11u35_wiobg96_if: - *module_if - *module_hic_lpc11u35 - - records/board/mtb_stm32f439.yaml - lpc11u35_musca_a_if: + - records/board/wiobg96.yaml + lpc11u35_wizwiki_w7500_eco_if: - *module_if - *module_hic_lpc11u35 - - records/board/musca_a.yaml - - records/tools/gcc_arm_lto.yaml - lpc11u35_musca_b_if: + - records/board/wizwiki_w7500_eco.yaml + lpc11u35_wizwiki_w7500_if: - *module_if - *module_hic_lpc11u35 - - records/board/musca_b.yaml - - records/tools/gcc_arm_lto.yaml - lpc11u35_musca_b_eflash_if: + - records/board/wizwiki_w7500.yaml + lpc11u35_wizwiki_w7500p_if: - *module_if - *module_hic_lpc11u35 - - records/board/musca_b_eflash.yaml - - records/tools/gcc_arm_lto.yaml + - records/board/wizwiki_w7500p.yaml + lpc4322_hani_iot_if: + - *module_if + - *module_hic_lpc4322 + - records/board/hani_iot.yaml + lpc4322_lpc54114xpresso_if: + - *module_if + - *module_hic_lpc4322 + - records/board/lpc54114xpresso.yaml + lpc4322_lpc54608xpresso_if: + - *module_if + - *module_hic_lpc4322 + - records/board/lpc54608xpresso.yaml + lpc4322_lpc55s69xpresso_if: + - *module_if + - *module_hic_lpc4322 + - records/board/lpc55S69xpresso.yaml + m48ssidae_numaker_iot_m263a_if: + - *module_if + - *module_hic_m48ssidae + - records/board/numaker_iot_m263a.yaml + m48ssidae_numaker_m2354_if: + - *module_if + - *module_hic_m48ssidae + - records/board/numaker_m2354.yaml + m48ssidae_numaker_m252kg_if: + - *module_if + - *module_hic_m48ssidae + - records/board/numaker_m252kg.yaml + m48ssidae_numaker_pfm_m487km_if: + - *module_if + - *module_hic_m48ssidae + - records/board/numaker_pfm_m487km.yaml max32620_max32625mbed_if: - *module_if - *module_hic_max32620 @@ -675,31 +654,55 @@ projects: - *module_if - *module_hic_max32625 - records/board/max32665hsp.yaml - lpc11u35_wio_emw3166_if: + sam3u2c_mkit_dk_dongle_nrf5x_if: - *module_if - - *module_hic_lpc11u35 - - records/board/wio_emw3166.yaml - m48ssidae_bl: - - *module_bl - - records/hic_hal/m48ssidae.yaml - - records/board/m48ssidae_bl.yaml - m48ssidae_numaker_m252kg_if: + - *module_hic_sam3u2c + - records/board/mkit_dk_dongle_nrf5x.yaml + sam3u2c_ncs36510rf_if: - *module_if - - *module_hic_m48ssidae - - records/board/numaker_m252kg.yaml - m48ssidae_numaker_iot_m263a_if: + - *module_hic_sam3u2c + - records/board/ncs36510rf.yaml + sam3u2c_ublox_evk_nina_b1_if: - *module_if - - *module_hic_m48ssidae - - records/board/numaker_iot_m263a.yaml - m48ssidae_numaker_pfm_m487km_if: + - *module_hic_sam3u2c + - records/board/ublox_evk_nina_b1.yaml + stm32f103xb_stm32f072rb_if: - *module_if - - *module_hic_m48ssidae - - records/board/numaker_pfm_m487km.yaml - m48ssidae_numaker_m2354_if: + - *module_hic_stm32f103xb + - records/board/stm32f072rb.yaml + stm32f103xb_stm32f103rb_if: - *module_if - - *module_hic_m48ssidae - - records/board/numaker_m2354.yaml - lpc4322_hani_iot_if: + - *module_hic_stm32f103xb + - records/board/stm32f103rb.yaml + stm32f103xb_stm32f207zg_if: - *module_if - - *module_hic_lpc4322 - - records/board/hani_iot.yaml + - *module_hic_stm32f103xb + - records/board/stm32f207zg.yaml + stm32f103xb_stm32f334r8_if: + - *module_if + - *module_hic_stm32f103xb + - records/board/stm32f334r8.yaml + stm32f103xb_stm32f401re_if: + - *module_if + - *module_hic_stm32f103xb + - records/board/stm32f401re.yaml + stm32f103xb_stm32f411re_if: + - *module_if + - *module_hic_stm32f103xb + - records/board/stm32f411re.yaml + stm32f103xb_stm32f429zi_if: + - *module_if + - *module_hic_stm32f103xb + - records/board/stm32f429zi.yaml + stm32f103xb_stm32f746zg_if: + - *module_if + - *module_hic_stm32f103xb + - records/board/stm32f746zg.yaml + stm32f103xb_stm32l476rg_if: + - *module_if + - *module_hic_stm32f103xb + - records/board/stm32l476rg.yaml + stm32f103xb_ublox_evk_odin_w2_if: + - *module_if + - *module_hic_stm32f103xb + - records/board/ublox_evk_odin_w2.yaml diff --git a/tools/projects_sort.py b/tools/projects_sort.py new file mode 100755 index 000000000..b31146294 --- /dev/null +++ b/tools/projects_sort.py @@ -0,0 +1,64 @@ +#!/usr/bin/env python +# +# DAPLink Interface Firmware +# Copyright (c) 2009-2021, Arm Limited, All Rights Reserved +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +import os +import re +import sys +import yaml + +PROJECTS_YAML = "projects.yaml" + +project_list = [] +with open(PROJECTS_YAML, 'r') as top_yaml: + try: + topdict = yaml.safe_load(top_yaml) + for dict_key in topdict: + if dict_key == 'projects': + for project in topdict[dict_key]: + project_list.append(project) + break + except yaml.YAMLError as ex: + print("Found yaml parse error", ex) + +_IF_RE = re.compile("^[a-z0-9]+_if$") +_BL_RE = re.compile("^[a-z0-9]+_bl$") + +hics = [] +boards = [] +for p in project_list: + if _IF_RE.match(p) or _BL_RE.match(p): + hics.append(p) + else: + boards.append(p) + +hics.sort() +for p in hics: + print(p) +print() +boards.sort() +for p in boards: + print(p) + +all_sorted = hics + boards +for i in range(len(project_list)): + if project_list[i] != all_sorted[i]: + sys.stderr.write("Found '%s' expected '%s'\n" % (project_list[i], all_sorted[i])) + break + +exit(0) From a52d186cfeb2d938b30aadae89c8949853df8864 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 5 Oct 2021 19:35:25 -0500 Subject: [PATCH 312/617] Use exit code to signal failure + copyright --- tools/projects_sort.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tools/projects_sort.py b/tools/projects_sort.py index b31146294..d4d23dfad 100755 --- a/tools/projects_sort.py +++ b/tools/projects_sort.py @@ -2,6 +2,7 @@ # # DAPLink Interface Firmware # Copyright (c) 2009-2021, Arm Limited, All Rights Reserved +# Copyright (c) 2021 Mathias Brossard # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -48,17 +49,18 @@ boards.append(p) hics.sort() +boards.sort() +all_sorted = hics + boards + for p in hics: print(p) print() -boards.sort() for p in boards: print(p) -all_sorted = hics + boards for i in range(len(project_list)): if project_list[i] != all_sorted[i]: sys.stderr.write("Found '%s' expected '%s'\n" % (project_list[i], all_sorted[i])) - break + exit(-1) exit(0) From 05f6562a6bcaaec36290bf7bbb9bd7cad483c61a Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Thu, 14 Oct 2021 17:03:48 -0500 Subject: [PATCH 313/617] DAP: refactor clock calculation code (#867) * DAP: refactored clock delay calculation into Set_DAP_Clock_Delay(). * DAP.c: remove unused CLOCK_DELAY macro. * DAP: update DAP.c file version. --- source/daplink/cmsis-dap/DAP.c | 67 +++++++++++++++------------------- 1 file changed, 30 insertions(+), 37 deletions(-) diff --git a/source/daplink/cmsis-dap/DAP.c b/source/daplink/cmsis-dap/DAP.c index 7e96462d2..c2da841a2 100644 --- a/source/daplink/cmsis-dap/DAP.c +++ b/source/daplink/cmsis-dap/DAP.c @@ -19,8 +19,8 @@ * * ---------------------------------------------------------------------- * - * $Date: 1. December 2017 - * $Revision: V2.0.0 + * $Date: 7. September 2021 + * $Revision: V2.1.1 * * Project: CMSIS-DAP Source * Title: DAP.c CMSIS-DAP Commands @@ -56,9 +56,6 @@ #define MAX_SWJ_CLOCK(delay_cycles) \ ((CPU_CLOCK/2U) / (IO_PORT_WRITE_CYCLES + delay_cycles)) -#define CLOCK_DELAY(swj_clock) \ - (((CPU_CLOCK/2U) / swj_clock) - IO_PORT_WRITE_CYCLES) - DAP_Data_t DAP_Data; // DAP Data volatile uint8_t DAP_TransferAbort; // Transfer Abort Flag @@ -368,6 +365,31 @@ static uint32_t DAP_SWJ_Pins(const uint8_t *request, uint8_t *response) { } +// Common clock delay calculation routine +// clock: requested SWJ frequency in Hertz +// return: void +static void Set_DAP_Clock_Delay(uint32_t clock) { + uint32_t delay; + + if (clock >= MAX_SWJ_CLOCK(DELAY_FAST_CYCLES)) { + DAP_Data.fast_clock = 1U; + DAP_Data.clock_delay = 1U; + } else { + DAP_Data.fast_clock = 0U; + + delay = ((CPU_CLOCK/2U) + (clock - 1U)) / clock; + if (delay > IO_PORT_WRITE_CYCLES) { + delay -= IO_PORT_WRITE_CYCLES; + delay = (delay + (DELAY_SLOW_CYCLES - 1U)) / DELAY_SLOW_CYCLES; + } else { + delay = 1U; + } + + DAP_Data.clock_delay = delay; + } +} + + // Process SWJ Clock command and prepare response // request: pointer to request data // response: pointer to response data @@ -390,22 +412,7 @@ static uint32_t DAP_SWJ_Clock(const uint8_t *request, uint8_t *response) { DAP_Data.nominal_clock = clock; - if (clock >= MAX_SWJ_CLOCK(DELAY_FAST_CYCLES)) { - DAP_Data.fast_clock = 1U; - DAP_Data.clock_delay = 1U; - } else { - DAP_Data.fast_clock = 0U; - - delay = ((CPU_CLOCK/2U) + (clock - 1U)) / clock; - if (delay > IO_PORT_WRITE_CYCLES) { - delay -= IO_PORT_WRITE_CYCLES; - delay = (delay + (DELAY_SLOW_CYCLES - 1U)) / DELAY_SLOW_CYCLES; - } else { - delay = 1U; - } - - DAP_Data.clock_delay = delay; - } + Set_DAP_Clock_Delay(clock); *response = DAP_OK; #else @@ -1790,22 +1797,8 @@ void DAP_Setup(void) { DAP_Data.jtag_dev.count = 0U; #endif - if (DAP_DEFAULT_SWJ_CLOCK >= MAX_SWJ_CLOCK(DELAY_FAST_CYCLES)) { - DAP_Data.fast_clock = 1U; - DAP_Data.clock_delay = 1U; - } else { - DAP_Data.fast_clock = 0U; - - uint32_t delay = ((CPU_CLOCK/2U) + (DAP_DEFAULT_SWJ_CLOCK - 1U)) / DAP_DEFAULT_SWJ_CLOCK; - if (delay > IO_PORT_WRITE_CYCLES) { - delay -= IO_PORT_WRITE_CYCLES; - delay = (delay + (DELAY_SLOW_CYCLES - 1U)) / DELAY_SLOW_CYCLES; - } else { - delay = 1U; - } - - DAP_Data.clock_delay = delay; - } + // Sets DAP_Data.fast_clock and DAP_Data.clock_delay. + Set_DAP_Clock_Delay(DAP_DEFAULT_SWJ_CLOCK); DAP_SETUP(); // Device specific setup } From 8a684bbf4e9ca96b8e950b51875dfc78d198459e Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Fri, 15 Oct 2021 13:38:24 -0500 Subject: [PATCH 314/617] Set version in target configs. (#863) * target_family.h: rename VENDOR_TO_FAMILY macro to CREATE_FAMILY_ID. The new name much better reflects the purpose of the macro. * Set target config struct versions. --- source/board/ep_kairos.c | 2 +- source/board/k20dx_bl.c | 5 ++- source/board/k26f_bl.c | 3 +- source/board/kl26z_bl.c | 3 +- source/board/kl27z_bl.c | 3 +- source/board/kl27z_microbit_bl.c | 5 ++- source/board/lpc4088dm.c | 2 +- source/board/lpc4088qsb.c | 2 +- source/board/lpc4322_bl.c | 3 +- source/board/lpc55s69_bl.c | 1 + source/board/m48ssidae_bl.c | 1 + source/board/max32620_bl.c | 3 +- source/board/max32625_bl.c | 3 +- source/board/sam3u2c_bl.c | 3 +- source/board/stm32f103xb_bl.c | 3 +- source/family/ambiq/ama3b1kk/target.c | 1 + source/family/arm/musca_a/target.c | 1 + source/family/arm/musca_b/target.c | 1 + source/family/freescale/k20dx/target.c | 3 +- source/family/freescale/k22f/target.c | 3 +- source/family/freescale/k28f/target.c | 3 +- source/family/freescale/k32w042/target.c | 3 +- source/family/freescale/k64f/target.c | 3 +- source/family/freescale/k66f/target.c | 3 +- source/family/freescale/k82f/target.c | 3 +- source/family/freescale/ke15z/target.c | 3 +- source/family/freescale/ke18f/target.c | 3 +- source/family/freescale/kl02z/target.c | 3 +- source/family/freescale/kl05z/target.c | 3 +- source/family/freescale/kl25z/target.c | 3 +- source/family/freescale/kl26z/target.c | 3 +- source/family/freescale/kl27z/target.c | 3 +- source/family/freescale/kl28z/target.c | 3 +- source/family/freescale/kl43z/target.c | 3 +- source/family/freescale/kl46z/target.c | 3 +- source/family/freescale/kl82z/target.c | 3 +- source/family/freescale/kw24d/target.c | 3 +- source/family/freescale/kw41z/target.c | 3 +- .../freescale/mimxrt1020_spi_flash/target.c | 3 +- .../freescale/mimxrt1050_hyper_flash/target.c | 3 +- .../freescale/mimxrt1050_spi_flash/target.c | 3 +- source/family/freescale/rapid_iot/target.c | 11 +++-- source/family/maxim/max32620/target.c | 1 + source/family/maxim/max32625/target.c | 3 +- source/family/maxim/max32630/target.c | 1 + source/family/maxim/max32660/target.c | 3 +- source/family/maxim/max32665/target.c | 5 ++- source/family/nordic/nrf51822/target_nrf51.c | 2 + source/family/nordic/nrf52/target.c | 4 ++ source/family/nuvoton/m2354kjfae/target.c | 1 + source/family/nuvoton/m252kg6ae/target.c | 1 + source/family/nuvoton/m263kiaae/target.c | 1 + source/family/nuvoton/m487jidae/target.c | 1 + source/family/nxp/lpc1114/target.c | 3 +- source/family/nxp/lpc1768/target.c | 3 +- source/family/nxp/lpc4088/target_lpc4088dm.c | 3 +- source/family/nxp/lpc4088/target_lpc4088qsb.c | 3 +- source/family/nxp/lpc54018/target.c | 3 +- source/family/nxp/lpc54114/target.c | 3 +- source/family/nxp/lpc54608/target.c | 3 +- source/family/nxp/lpc55S6X/target.c | 3 +- source/family/nxp/lpc812/target.c | 3 +- source/family/nxp/lpc824/target.c | 3 +- source/family/nxp/target_reset_lpc4088.c | 2 +- source/family/onsemi/ncs36510/target.c | 3 +- source/family/realtek/rtl8195am/target.c | 3 +- source/family/renesas/rza1h/gr-peach/target.c | 3 +- .../family/renesas/rza1lu/gr-lychee/target.c | 3 +- source/family/siliconlabs/efm32gg/target.c | 3 +- source/family/st/nz32_sc151/target.c | 3 +- source/family/st/stm32f072rb/target.c | 5 ++- source/family/st/stm32f103rb/target.c | 5 ++- source/family/st/stm32f207zg/target.c | 5 ++- source/family/st/stm32f334r8/target.c | 5 ++- source/family/st/stm32f401re/target.c | 5 ++- source/family/st/stm32f407/target.c | 3 +- source/family/st/stm32f407ve/target.c | 3 +- source/family/st/stm32f411/target.c | 3 +- source/family/st/stm32f412re/target.c | 3 +- source/family/st/stm32f412rg/target.c | 3 +- source/family/st/stm32f429zi/target.c | 3 +- source/family/st/stm32f437vg/target.c | 5 ++- source/family/st/stm32f439zi/target.c | 3 +- source/family/st/stm32f746zg/target.c | 5 ++- source/family/st/stm32l082cz/target.c | 3 +- source/family/st/stm32l151cbxxa/target.c | 3 +- source/family/st/stm32l443rc/target.c | 3 +- source/family/st/stm32l476rg/target.c | 5 ++- source/family/st/stm32l486jg/target.c | 3 +- source/family/st/stm32l4xx_1024/target.c | 3 +- source/family/st/xDot-L151/target.c | 3 +- source/family/ti/cc3220sf/target.c | 3 +- source/family/toshiba/tz10xx/target_remap0.c | 3 +- source/family/wiznet/w7500/target.c | 5 ++- source/target/target_config.h | 7 +++ source/target/target_family.h | 44 +++++++++---------- 96 files changed, 221 insertions(+), 118 deletions(-) diff --git a/source/board/ep_kairos.c b/source/board/ep_kairos.c index 8ea20ff77..3774bcf0d 100644 --- a/source/board/ep_kairos.c +++ b/source/board/ep_kairos.c @@ -25,7 +25,7 @@ const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "2601", - .family_id = VENDOR_TO_FAMILY(kNXP_VendorID, 0), //ID not maching the predefined family ids + .family_id = CREATE_FAMILY_ID(kNXP_VendorID, 0), //ID not maching the predefined family ids .flags = kEnablePageErase, .target_cfg = &target_device, }; diff --git a/source/board/k20dx_bl.c b/source/board/k20dx_bl.c index ec71217b5..9ce1754d1 100644 --- a/source/board/k20dx_bl.c +++ b/source/board/k20dx_bl.c @@ -42,14 +42,15 @@ static const sector_info_t sectors_info[] = { // k20dx128 target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = DAPLINK_ROM_IF_START, .flash_regions[0].end = DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE, - .flash_regions[0].flags = kRegionIsDefault, + .flash_regions[0].flags = kRegionIsDefault, .ram_regions[0].start = 0x1fffe000, .ram_regions[0].end = 0x20002000, - // flash_algo not needed for bootloader + // flash_algo not needed for bootloader }; //bootloader has no family diff --git a/source/board/k26f_bl.c b/source/board/k26f_bl.c index 1c9bc692d..76c788040 100644 --- a/source/board/k26f_bl.c +++ b/source/board/k26f_bl.c @@ -41,11 +41,12 @@ static const sector_info_t sectors_info[] = { // k26f target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = DAPLINK_ROM_IF_START, .flash_regions[0].end = DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE, - .flash_regions[0].flags = kRegionIsDefault, + .flash_regions[0].flags = kRegionIsDefault, .ram_regions[0].start = 0x1fff0000, .ram_regions[0].end = 0x20030000, /* .flash_algo not needed for bootloader */ diff --git a/source/board/kl26z_bl.c b/source/board/kl26z_bl.c index 6658a120d..74b412fee 100644 --- a/source/board/kl26z_bl.c +++ b/source/board/kl26z_bl.c @@ -42,11 +42,12 @@ static const sector_info_t sectors_info[] = { // kl26z128 target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = DAPLINK_ROM_IF_START, .flash_regions[0].end = DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE, - .flash_regions[0].flags = kRegionIsDefault, + .flash_regions[0].flags = kRegionIsDefault, .ram_regions[0].start = 0x1FFFF000, .ram_regions[0].end = 0x20003000, }; diff --git a/source/board/kl27z_bl.c b/source/board/kl27z_bl.c index 5a1579c0a..7c8e2e154 100644 --- a/source/board/kl27z_bl.c +++ b/source/board/kl27z_bl.c @@ -42,11 +42,12 @@ static const sector_info_t sectors_info[] = { // kl26z128 target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = DAPLINK_ROM_IF_START, .flash_regions[0].end = DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE, - .flash_regions[0].flags = kRegionIsDefault, + .flash_regions[0].flags = kRegionIsDefault, .ram_regions[0].start = 0x1FFFE000, .ram_regions[0].end = 0x20006000, }; diff --git a/source/board/kl27z_microbit_bl.c b/source/board/kl27z_microbit_bl.c index 0dc3c0bb9..bbd9fe52c 100644 --- a/source/board/kl27z_microbit_bl.c +++ b/source/board/kl27z_microbit_bl.c @@ -44,11 +44,12 @@ static const sector_info_t sectors_info[] = { // kl26z128 target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = DAPLINK_ROM_IF_START, .flash_regions[0].end = DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE, - .flash_regions[0].flags = kRegionIsDefault, + .flash_regions[0].flags = kRegionIsDefault, .ram_regions[0].start = 0x1FFFE000, .ram_regions[0].end = 0x20006000, }; @@ -75,6 +76,6 @@ bool reset_button_pressed() else { btn_pressed = gpio_get_reset_btn(); } - + return btn_pressed; } diff --git a/source/board/lpc4088dm.c b/source/board/lpc4088dm.c index 046951950..3da3b09c9 100644 --- a/source/board/lpc4088dm.c +++ b/source/board/lpc4088dm.c @@ -25,6 +25,6 @@ const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "1062", - .family_id = VENDOR_TO_FAMILY(kNXP_VendorID, 0), //custom + .family_id = CREATE_FAMILY_ID(kNXP_VendorID, 0), //custom .target_cfg = &target_device, }; diff --git a/source/board/lpc4088qsb.c b/source/board/lpc4088qsb.c index 4097e0b1e..cc345dbf3 100644 --- a/source/board/lpc4088qsb.c +++ b/source/board/lpc4088qsb.c @@ -25,6 +25,6 @@ const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "1060", - .family_id = VENDOR_TO_FAMILY(kNXP_VendorID, 0), //custom + .family_id = CREATE_FAMILY_ID(kNXP_VendorID, 0), //custom .target_cfg = &target_device, }; diff --git a/source/board/lpc4322_bl.c b/source/board/lpc4322_bl.c index d9f2efe04..ff5edde57 100644 --- a/source/board/lpc4322_bl.c +++ b/source/board/lpc4322_bl.c @@ -42,11 +42,12 @@ static const sector_info_t sectors_info[] = { // lpc4322 target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = DAPLINK_ROM_IF_START, .flash_regions[0].end = DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE, - .flash_regions[0].flags = kRegionIsDefault, + .flash_regions[0].flags = kRegionIsDefault, .ram_regions[0].start = 0x10000000, .ram_regions[0].end = 0x10008000, /* .flash_algo not needed for bootloader */ diff --git a/source/board/lpc55s69_bl.c b/source/board/lpc55s69_bl.c index fcb53e267..42998403d 100644 --- a/source/board/lpc55s69_bl.c +++ b/source/board/lpc55s69_bl.c @@ -45,6 +45,7 @@ static const sector_info_t sectors_info[] = { // lpc55s69 target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = DAPLINK_ROM_IF_START, diff --git a/source/board/m48ssidae_bl.c b/source/board/m48ssidae_bl.c index a78199a61..4a9815479 100644 --- a/source/board/m48ssidae_bl.c +++ b/source/board/m48ssidae_bl.c @@ -42,6 +42,7 @@ static const sector_info_t sectors_info[] = { // m48ssidae target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = DAPLINK_ROM_IF_START, diff --git a/source/board/max32620_bl.c b/source/board/max32620_bl.c index 149c68670..33c2d7c4c 100644 --- a/source/board/max32620_bl.c +++ b/source/board/max32620_bl.c @@ -36,11 +36,12 @@ static const sector_info_t sectors_info[] = { /* ME02 -- MAX32620 2MiB Flash, 256KiB RAM */ target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x00000000 + 0x10000, .flash_regions[0].end = 0x00000000 + MB(2), - .flash_regions[0].flags = kRegionIsDefault, + .flash_regions[0].flags = kRegionIsDefault, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20040000, /* .flash_algo not needed for bootloader */ diff --git a/source/board/max32625_bl.c b/source/board/max32625_bl.c index 6b306d7d4..2aa6c5a5b 100644 --- a/source/board/max32625_bl.c +++ b/source/board/max32625_bl.c @@ -38,11 +38,12 @@ static const sector_info_t sectors_info[] = { /* ME03 -- MAX32625 512KiB Flash, 160KiB RAM */ target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x00000000 + 0x10000, .flash_regions[0].end = 0x00000000 + KB(512), - .flash_regions[0].flags = kRegionIsDefault, + .flash_regions[0].flags = kRegionIsDefault, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20028000, /* .flash_algo not needed for bootloader */ diff --git a/source/board/sam3u2c_bl.c b/source/board/sam3u2c_bl.c index 9080ed358..fce82120e 100644 --- a/source/board/sam3u2c_bl.c +++ b/source/board/sam3u2c_bl.c @@ -42,11 +42,12 @@ static const sector_info_t sectors_info[] = { // atsam3u2c target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = DAPLINK_ROM_IF_START, .flash_regions[0].end = DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE, - .flash_regions[0].flags = kRegionIsDefault, + .flash_regions[0].flags = kRegionIsDefault, .ram_regions[0].start = 0x2007C000, .ram_regions[0].end = 0x20084000, /* .flash_algo not needed for bootloader */ diff --git a/source/board/stm32f103xb_bl.c b/source/board/stm32f103xb_bl.c index 1da40ec6b..26a56d3ca 100644 --- a/source/board/stm32f103xb_bl.c +++ b/source/board/stm32f103xb_bl.c @@ -36,11 +36,12 @@ static const sector_info_t sectors_info[] = { // stm32f103 target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000 + KB(48), .flash_regions[0].end = 0x08000000 + KB(128), - .flash_regions[0].flags = kRegionIsDefault, + .flash_regions[0].flags = kRegionIsDefault, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20005000, /* .flash_algo not needed for bootloader */ diff --git a/source/family/ambiq/ama3b1kk/target.c b/source/family/ambiq/ama3b1kk/target.c index bd9a9afae..599a717d7 100644 --- a/source/family/ambiq/ama3b1kk/target.c +++ b/source/family/ambiq/ama3b1kk/target.c @@ -26,6 +26,7 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = (const sector_info_t *)sectors_info, .sector_info_length = (sizeof(sectors_info)) / (sizeof(sector_info_t)), .flash_regions[0].start = 0x0C000, diff --git a/source/family/arm/musca_a/target.c b/source/family/arm/musca_a/target.c index f554c97f8..28dcee445 100644 --- a/source/family/arm/musca_a/target.c +++ b/source/family/arm/musca_a/target.c @@ -40,6 +40,7 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = (MUSCA_A_NS_FLASH_START), diff --git a/source/family/arm/musca_b/target.c b/source/family/arm/musca_b/target.c index 30961b8e1..0eafe1f08 100644 --- a/source/family/arm/musca_b/target.c +++ b/source/family/arm/musca_b/target.c @@ -29,6 +29,7 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), diff --git a/source/family/freescale/k20dx/target.c b/source/family/freescale/k20dx/target.c index 4442166c9..4f31e1e0e 100644 --- a/source/family/freescale/k20dx/target.c +++ b/source/family/freescale/k20dx/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(128), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFF8000, .ram_regions[0].end = 0x20008000, }; diff --git a/source/family/freescale/k22f/target.c b/source/family/freescale/k22f/target.c index d00b6ad91..0d14eaaa1 100644 --- a/source/family/freescale/k22f/target.c +++ b/source/family/freescale/k22f/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(512), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFF0000, .ram_regions[0].end = 0x20010000, }; diff --git a/source/family/freescale/k28f/target.c b/source/family/freescale/k28f/target.c index da950b836..1ea39b3a6 100644 --- a/source/family/freescale/k28f/target.c +++ b/source/family/freescale/k28f/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = MB(2), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFC0000, .ram_regions[0].end = 0x20040000, }; diff --git a/source/family/freescale/k32w042/target.c b/source/family/freescale/k32w042/target.c index 7a97ebc7d..9fa817148 100644 --- a/source/family/freescale/k32w042/target.c +++ b/source/family/freescale/k32w042/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(1024), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, // M4 DTCM .ram_regions[0].end = 0x20030000, }; diff --git a/source/family/freescale/k64f/target.c b/source/family/freescale/k64f/target.c index 458943fc4..4558f465b 100644 --- a/source/family/freescale/k64f/target.c +++ b/source/family/freescale/k64f/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x00000000, .flash_regions[0].end = 0x00100000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1fff0000, .ram_regions[0].end = 0x20030000, }; diff --git a/source/family/freescale/k66f/target.c b/source/family/freescale/k66f/target.c index fe7d5207f..5d1b6775c 100644 --- a/source/family/freescale/k66f/target.c +++ b/source/family/freescale/k66f/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x00000000, .flash_regions[0].end = 0x00200000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1fff0000, .ram_regions[0].end = 0x20030000, }; diff --git a/source/family/freescale/k82f/target.c b/source/family/freescale/k82f/target.c index 8c82420bf..b0fa3d7fe 100644 --- a/source/family/freescale/k82f/target.c +++ b/source/family/freescale/k82f/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(256), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFF0000, .ram_regions[0].end = 0x20030000, }; diff --git a/source/family/freescale/ke15z/target.c b/source/family/freescale/ke15z/target.c index cf3bc8cc2..4688275e5 100644 --- a/source/family/freescale/ke15z/target.c +++ b/source/family/freescale/ke15z/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(256), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFFE000, .ram_regions[0].end = 0x20006000, }; diff --git a/source/family/freescale/ke18f/target.c b/source/family/freescale/ke18f/target.c index 163e702b2..c96d51151 100644 --- a/source/family/freescale/ke18f/target.c +++ b/source/family/freescale/ke18f/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(512), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFF8000, .ram_regions[0].end = 0x20008000, }; diff --git a/source/family/freescale/kl02z/target.c b/source/family/freescale/kl02z/target.c index bc23899f9..3984c7a1e 100644 --- a/source/family/freescale/kl02z/target.c +++ b/source/family/freescale/kl02z/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(32), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFFFC00, .ram_regions[0].end = 0x20000C00, }; diff --git a/source/family/freescale/kl05z/target.c b/source/family/freescale/kl05z/target.c index a038c220c..02d1f0c02 100644 --- a/source/family/freescale/kl05z/target.c +++ b/source/family/freescale/kl05z/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(32), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFFFC00, .ram_regions[0].end = 0x20000C00, }; diff --git a/source/family/freescale/kl25z/target.c b/source/family/freescale/kl25z/target.c index 0d6e8bde3..94f316af0 100644 --- a/source/family/freescale/kl25z/target.c +++ b/source/family/freescale/kl25z/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(128), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFF0000, .ram_regions[0].end = 0x20004000, }; diff --git a/source/family/freescale/kl26z/target.c b/source/family/freescale/kl26z/target.c index 583b9f083..cb2761d90 100644 --- a/source/family/freescale/kl26z/target.c +++ b/source/family/freescale/kl26z/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(128), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFF0000, .ram_regions[0].end = 0x20004000, }; diff --git a/source/family/freescale/kl27z/target.c b/source/family/freescale/kl27z/target.c index 66a3b3c9d..8fad952f4 100644 --- a/source/family/freescale/kl27z/target.c +++ b/source/family/freescale/kl27z/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(64), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFFF000, .ram_regions[0].end = 0x20003000, }; diff --git a/source/family/freescale/kl28z/target.c b/source/family/freescale/kl28z/target.c index 815cefd15..8bffa7a40 100644 --- a/source/family/freescale/kl28z/target.c +++ b/source/family/freescale/kl28z/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(256), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFF8000, .ram_regions[0].end = 0x20018000, }; diff --git a/source/family/freescale/kl43z/target.c b/source/family/freescale/kl43z/target.c index 051efb41d..cecb824e1 100644 --- a/source/family/freescale/kl43z/target.c +++ b/source/family/freescale/kl43z/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(256), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1fffe000, .ram_regions[0].end = 0x20006000, }; diff --git a/source/family/freescale/kl46z/target.c b/source/family/freescale/kl46z/target.c index cfdb4b60e..9a4c9e6b6 100644 --- a/source/family/freescale/kl46z/target.c +++ b/source/family/freescale/kl46z/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(256), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFFE000, .ram_regions[0].end = 0x20006000, }; diff --git a/source/family/freescale/kl82z/target.c b/source/family/freescale/kl82z/target.c index 2b5ca95d3..2c985a5e2 100644 --- a/source/family/freescale/kl82z/target.c +++ b/source/family/freescale/kl82z/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(128), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFFA000, .ram_regions[0].end = 0x20012000, }; diff --git a/source/family/freescale/kw24d/target.c b/source/family/freescale/kw24d/target.c index b09bdcaa0..607a02f39 100644 --- a/source/family/freescale/kw24d/target.c +++ b/source/family/freescale/kw24d/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(512), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFF8000, .ram_regions[0].end = 0x20008000, }; diff --git a/source/family/freescale/kw41z/target.c b/source/family/freescale/kw41z/target.c index 37a801dc4..6f18a8071 100644 --- a/source/family/freescale/kw41z/target.c +++ b/source/family/freescale/kw41z/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(512), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFF8000, .ram_regions[0].end = 0x20018000, }; diff --git a/source/family/freescale/mimxrt1020_spi_flash/target.c b/source/family/freescale/mimxrt1020_spi_flash/target.c index 725104884..64a4871ed 100644 --- a/source/family/freescale/mimxrt1020_spi_flash/target.c +++ b/source/family/freescale/mimxrt1020_spi_flash/target.c @@ -27,12 +27,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x60000000, .flash_regions[0].end = 0x60000000 + MB(64), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20000000 + MB(64), }; diff --git a/source/family/freescale/mimxrt1050_hyper_flash/target.c b/source/family/freescale/mimxrt1050_hyper_flash/target.c index 99fce204c..0e890faa5 100644 --- a/source/family/freescale/mimxrt1050_hyper_flash/target.c +++ b/source/family/freescale/mimxrt1050_hyper_flash/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x60000000, .flash_regions[0].end = 0x60000000 + MB(64), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20000000 + MB(64), }; diff --git a/source/family/freescale/mimxrt1050_spi_flash/target.c b/source/family/freescale/mimxrt1050_spi_flash/target.c index 99fce204c..0e890faa5 100644 --- a/source/family/freescale/mimxrt1050_spi_flash/target.c +++ b/source/family/freescale/mimxrt1050_spi_flash/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x60000000, .flash_regions[0].end = 0x60000000 + MB(64), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20000000 + MB(64), }; diff --git a/source/family/freescale/rapid_iot/target.c b/source/family/freescale/rapid_iot/target.c index fc91a8295..c8ceddc41 100644 --- a/source/family/freescale/rapid_iot/target.c +++ b/source/family/freescale/rapid_iot/target.c @@ -28,38 +28,41 @@ // default target information is k64f target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info_k64, .sector_info_length = (sizeof(sectors_info_k64))/(sizeof(sector_info_t)), #ifdef BOARD_RAPID_IOT .flash_regions[0].start = 0x00014000, #else .flash_regions[0].start = 0x00000000, -#endif +#endif .flash_regions[0].end = MB(1), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash_k64, + .flash_regions[0].flash_algo = (program_target_t *) &flash_k64, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20030000, }; target_cfg_t target_device_kw40 = { + .version = kTargetConfigVersion, .sectors_info = sectors_info_kw40, .sector_info_length = (sizeof(sectors_info_kw40))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(160), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash_kw40, + .flash_regions[0].flash_algo = (program_target_t *) &flash_kw40, .ram_regions[0].start = 0x1FFFF000, .ram_regions[0].end = 0x20004000, }; target_cfg_t target_device_kw41 = { + .version = kTargetConfigVersion, .sectors_info = sectors_info_kw41, .sector_info_length = (sizeof(sectors_info_kw41))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x4000, .flash_regions[0].end = KB(512), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash_kw41, + .flash_regions[0].flash_algo = (program_target_t *) &flash_kw41, .ram_regions[0].start = 0x1FFF8000, .ram_regions[0].end = 0x20018000, }; diff --git a/source/family/maxim/max32620/target.c b/source/family/maxim/max32620/target.c index 5d3cb3cfe..51e67accc 100644 --- a/source/family/maxim/max32620/target.c +++ b/source/family/maxim/max32620/target.c @@ -25,6 +25,7 @@ /* MAX32620 2MiB Flash, 256KiB RAM */ target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = FLASH_BASE, diff --git a/source/family/maxim/max32625/target.c b/source/family/maxim/max32625/target.c index 402d33b87..349e2f71c 100644 --- a/source/family/maxim/max32625/target.c +++ b/source/family/maxim/max32625/target.c @@ -25,12 +25,13 @@ /* ME03 -- MAX32625 512KiB Flash, 160KiB RAM */ target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = 0x80000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20028000, }; diff --git a/source/family/maxim/max32630/target.c b/source/family/maxim/max32630/target.c index 736e9375c..8cfd1cb9f 100644 --- a/source/family/maxim/max32630/target.c +++ b/source/family/maxim/max32630/target.c @@ -25,6 +25,7 @@ /* MAX32630 2MiB Flash, 512KiB RAM */ target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = FLASH_BASE, diff --git a/source/family/maxim/max32660/target.c b/source/family/maxim/max32660/target.c index 92dc81967..cebbd3ae0 100644 --- a/source/family/maxim/max32660/target.c +++ b/source/family/maxim/max32660/target.c @@ -21,7 +21,7 @@ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Except as contained in this notice, the name of Maxim Integrated @@ -42,6 +42,7 @@ /* ME11 -- MAX32660 256KiB Flash, 96KiB RAM */ target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x00000000, diff --git a/source/family/maxim/max32665/target.c b/source/family/maxim/max32665/target.c index 8d6dfe34d..982349117 100644 --- a/source/family/maxim/max32665/target.c +++ b/source/family/maxim/max32665/target.c @@ -21,7 +21,7 @@ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Except as contained in this notice, the name of Maxim Integrated @@ -42,12 +42,13 @@ /* ME14 -- MAX32665 1MiB Flash, 560KiB RAM */ target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x10000000, .flash_regions[0].end = 0x10100000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x2008C000, }; diff --git a/source/family/nordic/nrf51822/target_nrf51.c b/source/family/nordic/nrf51822/target_nrf51.c index dba8aa517..ff965c2a2 100644 --- a/source/family/nordic/nrf51822/target_nrf51.c +++ b/source/family/nordic/nrf51822/target_nrf51.c @@ -26,6 +26,7 @@ // target information for model with 16 KB RAM target_cfg_t target_device_nrf51822_16 = { + .version = kTargetConfigVersion, .sectors_info = sectors_info_nrf51, .sector_info_length = (sizeof(sectors_info_nrf51))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, @@ -39,6 +40,7 @@ target_cfg_t target_device_nrf51822_16 = { // target information for model with 32 KB RAM target_cfg_t target_device_nrf51822_32 = { + .version = kTargetConfigVersion, .sectors_info = sectors_info_nrf51, .sector_info_length = (sizeof(sectors_info_nrf51))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, diff --git a/source/family/nordic/nrf52/target.c b/source/family/nordic/nrf52/target.c index a8461ba5d..a9a1dd595 100644 --- a/source/family/nordic/nrf52/target.c +++ b/source/family/nordic/nrf52/target.c @@ -26,6 +26,7 @@ // target information for model with 32 KB RAM target_cfg_t target_device_nrf52 = { + .version = kTargetConfigVersion, .sectors_info = sectors_info_nrf52, .sector_info_length = (sizeof(sectors_info_nrf52))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, @@ -39,6 +40,7 @@ target_cfg_t target_device_nrf52 = { // target information for nRF52832 with 64 KB RAM / 512 KB Flash target_cfg_t target_device_nrf52_64 = { + .version = kTargetConfigVersion, .sectors_info = sectors_info_nrf52, .sector_info_length = (sizeof(sectors_info_nrf52))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, @@ -52,6 +54,7 @@ target_cfg_t target_device_nrf52_64 = { // target information for nRF52833 with 128 KB RAM / 512 KB Flash target_cfg_t target_device_nrf52833 = { + .version = kTargetConfigVersion, .sectors_info = sectors_info_nrf52, .sector_info_length = (sizeof(sectors_info_nrf52))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, @@ -65,6 +68,7 @@ target_cfg_t target_device_nrf52833 = { // target information for nRF52840 with 256 KB RAM / 1024 KB Flash target_cfg_t target_device_nrf52840 = { + .version = kTargetConfigVersion, .sectors_info = sectors_info_nrf52, .sector_info_length = (sizeof(sectors_info_nrf52))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, diff --git a/source/family/nuvoton/m2354kjfae/target.c b/source/family/nuvoton/m2354kjfae/target.c index bafe17192..8abf8e0fd 100644 --- a/source/family/nuvoton/m2354kjfae/target.c +++ b/source/family/nuvoton/m2354kjfae/target.c @@ -24,6 +24,7 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x00000000, diff --git a/source/family/nuvoton/m252kg6ae/target.c b/source/family/nuvoton/m252kg6ae/target.c index 69169ac31..9c5bb6cd0 100644 --- a/source/family/nuvoton/m252kg6ae/target.c +++ b/source/family/nuvoton/m252kg6ae/target.c @@ -26,6 +26,7 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x00000000, diff --git a/source/family/nuvoton/m263kiaae/target.c b/source/family/nuvoton/m263kiaae/target.c index 1d2ab73fa..19254a793 100644 --- a/source/family/nuvoton/m263kiaae/target.c +++ b/source/family/nuvoton/m263kiaae/target.c @@ -26,6 +26,7 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x00000000, diff --git a/source/family/nuvoton/m487jidae/target.c b/source/family/nuvoton/m487jidae/target.c index 860e9253f..56dc2a004 100644 --- a/source/family/nuvoton/m487jidae/target.c +++ b/source/family/nuvoton/m487jidae/target.c @@ -26,6 +26,7 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x00000000, diff --git a/source/family/nxp/lpc1114/target.c b/source/family/nxp/lpc1114/target.c index dbb1cecab..2bf0e5119 100644 --- a/source/family/nxp/lpc1114/target.c +++ b/source/family/nxp/lpc1114/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(32), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x10000000, .ram_regions[0].end = 0x10001000, }; diff --git a/source/family/nxp/lpc1768/target.c b/source/family/nxp/lpc1768/target.c index dcc29406d..0aaef122c 100644 --- a/source/family/nxp/lpc1768/target.c +++ b/source/family/nxp/lpc1768/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(512), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x10000000, .ram_regions[0].end = 0x10008000, }; diff --git a/source/family/nxp/lpc4088/target_lpc4088dm.c b/source/family/nxp/lpc4088/target_lpc4088dm.c index 4d7ce909e..9379c08de 100644 --- a/source/family/nxp/lpc4088/target_lpc4088dm.c +++ b/source/family/nxp/lpc4088/target_lpc4088dm.c @@ -26,12 +26,13 @@ // The LPC4088 Display Module has 512K internal flash and 16M external QSPI flash target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = MB(16) + KB(512), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x10000000, .ram_regions[0].end = 0x10010000, }; diff --git a/source/family/nxp/lpc4088/target_lpc4088qsb.c b/source/family/nxp/lpc4088/target_lpc4088qsb.c index ef2f6ecfa..104022900 100644 --- a/source/family/nxp/lpc4088/target_lpc4088qsb.c +++ b/source/family/nxp/lpc4088/target_lpc4088qsb.c @@ -26,12 +26,13 @@ // The LPC4088 QuickStart Board has 512K internal flash and 8M external QSPI flash target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = MB(8) + KB(512), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x10000000, .ram_regions[0].end = 0x10010000, }; diff --git a/source/family/nxp/lpc54018/target.c b/source/family/nxp/lpc54018/target.c index d4b01ac17..5532b5c91 100644 --- a/source/family/nxp/lpc54018/target.c +++ b/source/family/nxp/lpc54018/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x10000000, .flash_regions[0].end = 0x11000000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x00000000, .ram_regions[0].end = 0x00030000, }; diff --git a/source/family/nxp/lpc54114/target.c b/source/family/nxp/lpc54114/target.c index e26f366d5..968281218 100644 --- a/source/family/nxp/lpc54114/target.c +++ b/source/family/nxp/lpc54114/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(256), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20028000, }; diff --git a/source/family/nxp/lpc54608/target.c b/source/family/nxp/lpc54608/target.c index bbe9e222a..e00a6c9f7 100644 --- a/source/family/nxp/lpc54608/target.c +++ b/source/family/nxp/lpc54608/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(512), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20028000, }; diff --git a/source/family/nxp/lpc55S6X/target.c b/source/family/nxp/lpc55S6X/target.c index cee0db0fe..c7f256c03 100644 --- a/source/family/nxp/lpc55S6X/target.c +++ b/source/family/nxp/lpc55S6X/target.c @@ -26,6 +26,7 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, @@ -34,7 +35,7 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .flash_regions[1].start = 0x10000000, .flash_regions[1].end = 0x10000000 + KB(608), - .flash_regions[1].flash_algo = (program_target_t *) &flash, + .flash_regions[1].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20044000, .ram_regions[1].start = 0x30000000, diff --git a/source/family/nxp/lpc812/target.c b/source/family/nxp/lpc812/target.c index 21a41d764..03f8a4def 100644 --- a/source/family/nxp/lpc812/target.c +++ b/source/family/nxp/lpc812/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(64), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x10000000, .ram_regions[0].end = 0x10001000, }; diff --git a/source/family/nxp/lpc824/target.c b/source/family/nxp/lpc824/target.c index e0acd0a29..6c809411c 100644 --- a/source/family/nxp/lpc824/target.c +++ b/source/family/nxp/lpc824/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = KB(32), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x10000000, .ram_regions[0].end = 0x10002000, }; diff --git a/source/family/nxp/target_reset_lpc4088.c b/source/family/nxp/target_reset_lpc4088.c index 022ec5b4d..0e5887fec 100644 --- a/source/family/nxp/target_reset_lpc4088.c +++ b/source/family/nxp/target_reset_lpc4088.c @@ -69,7 +69,7 @@ static uint8_t lpc4088_target_set_state(target_state_t state) } const target_family_descriptor_t g_nxp_lpc4088 = { - .family_id = VENDOR_TO_FAMILY(kNXP_VendorID, 0), //ID not maching the predefined family ids + .family_id = CREATE_FAMILY_ID(kNXP_VendorID, 0), //ID not maching the predefined family ids .prerun_target_config = prerun_target_config, .target_set_state = lpc4088_target_set_state, }; diff --git a/source/family/onsemi/ncs36510/target.c b/source/family/onsemi/ncs36510/target.c index e14b9c624..9cfe787b2 100644 --- a/source/family/onsemi/ncs36510/target.c +++ b/source/family/onsemi/ncs36510/target.c @@ -21,12 +21,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x00002000, .flash_regions[0].end = 0x00151FFF, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x3FFF4000, .ram_regions[0].end = 0x3FFFFFFF, }; diff --git a/source/family/realtek/rtl8195am/target.c b/source/family/realtek/rtl8195am/target.c index 845fd160c..b81fde9c2 100644 --- a/source/family/realtek/rtl8195am/target.c +++ b/source/family/realtek/rtl8195am/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x00000000, .flash_regions[0].end = 0x00000000 + MB(2), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x10007000, .ram_regions[0].end = 0x10070000, }; diff --git a/source/family/renesas/rza1h/gr-peach/target.c b/source/family/renesas/rza1h/gr-peach/target.c index 9ef6c4a6f..b31c4eae7 100644 --- a/source/family/renesas/rza1h/gr-peach/target.c +++ b/source/family/renesas/rza1h/gr-peach/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = MB(8), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20A00000, }; diff --git a/source/family/renesas/rza1lu/gr-lychee/target.c b/source/family/renesas/rza1lu/gr-lychee/target.c index 1377a6955..8533a94c0 100644 --- a/source/family/renesas/rza1lu/gr-lychee/target.c +++ b/source/family/renesas/rza1lu/gr-lychee/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = MB(8), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20300000, }; diff --git a/source/family/siliconlabs/efm32gg/target.c b/source/family/siliconlabs/efm32gg/target.c index 3304f6ef0..cff78867c 100644 --- a/source/family/siliconlabs/efm32gg/target.c +++ b/source/family/siliconlabs/efm32gg/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = MB(1), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20010000, }; diff --git a/source/family/st/nz32_sc151/target.c b/source/family/st/nz32_sc151/target.c index 310d0b28d..55e343436 100644 --- a/source/family/st/nz32_sc151/target.c +++ b/source/family/st/nz32_sc151/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08000000 + KB(256), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20000000 + KB(32), }; diff --git a/source/family/st/stm32f072rb/target.c b/source/family/st/stm32f072rb/target.c index bfa98cb48..31c4545cf 100644 --- a/source/family/st/stm32f072rb/target.c +++ b/source/family/st/stm32f072rb/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the + * @brief Target information for the * * DAPLink Interface Firmware * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08020000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20004000, }; diff --git a/source/family/st/stm32f103rb/target.c b/source/family/st/stm32f103rb/target.c index d1b3bba10..273e73b59 100644 --- a/source/family/st/stm32f103rb/target.c +++ b/source/family/st/stm32f103rb/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the + * @brief Target information for the * * DAPLink Interface Firmware * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08020000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20005000, }; diff --git a/source/family/st/stm32f207zg/target.c b/source/family/st/stm32f207zg/target.c index ce076e435..57892c664 100644 --- a/source/family/st/stm32f207zg/target.c +++ b/source/family/st/stm32f207zg/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the + * @brief Target information for the * * DAPLink Interface Firmware * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08100000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20020000, }; diff --git a/source/family/st/stm32f334r8/target.c b/source/family/st/stm32f334r8/target.c index 858ed83b4..49751317e 100644 --- a/source/family/st/stm32f334r8/target.c +++ b/source/family/st/stm32f334r8/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the + * @brief Target information for the * * DAPLink Interface Firmware * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08010000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20003000, }; diff --git a/source/family/st/stm32f401re/target.c b/source/family/st/stm32f401re/target.c index 3d4d35c8e..3445e9e77 100644 --- a/source/family/st/stm32f401re/target.c +++ b/source/family/st/stm32f401re/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the + * @brief Target information for the * * DAPLink Interface Firmware * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08080000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20018000, }; diff --git a/source/family/st/stm32f407/target.c b/source/family/st/stm32f407/target.c index c526e8f88..56765e536 100644 --- a/source/family/st/stm32f407/target.c +++ b/source/family/st/stm32f407/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08100000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20020000, }; diff --git a/source/family/st/stm32f407ve/target.c b/source/family/st/stm32f407ve/target.c index 68e43dad4..344dc5905 100644 --- a/source/family/st/stm32f407ve/target.c +++ b/source/family/st/stm32f407ve/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08080000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20020000, }; diff --git a/source/family/st/stm32f411/target.c b/source/family/st/stm32f411/target.c index ed2f9fd1a..9e7f46961 100644 --- a/source/family/st/stm32f411/target.c +++ b/source/family/st/stm32f411/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08000000 + KB(512), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20020000, }; diff --git a/source/family/st/stm32f412re/target.c b/source/family/st/stm32f412re/target.c index 9416b2f80..ef7cc5791 100644 --- a/source/family/st/stm32f412re/target.c +++ b/source/family/st/stm32f412re/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08080000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20040000, }; diff --git a/source/family/st/stm32f412rg/target.c b/source/family/st/stm32f412rg/target.c index 646d29fd3..bca2cec25 100644 --- a/source/family/st/stm32f412rg/target.c +++ b/source/family/st/stm32f412rg/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08100000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20040000, }; diff --git a/source/family/st/stm32f429zi/target.c b/source/family/st/stm32f429zi/target.c index 5f165fedd..f8cf162dc 100644 --- a/source/family/st/stm32f429zi/target.c +++ b/source/family/st/stm32f429zi/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08200000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20030000, }; diff --git a/source/family/st/stm32f437vg/target.c b/source/family/st/stm32f437vg/target.c index ad1401579..cd1d76e24 100644 --- a/source/family/st/stm32f437vg/target.c +++ b/source/family/st/stm32f437vg/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the + * @brief Target information for the * * DAPLink Interface Firmware * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08100000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20030000, }; diff --git a/source/family/st/stm32f439zi/target.c b/source/family/st/stm32f439zi/target.c index 5f165fedd..f8cf162dc 100644 --- a/source/family/st/stm32f439zi/target.c +++ b/source/family/st/stm32f439zi/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08200000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20030000, }; diff --git a/source/family/st/stm32f746zg/target.c b/source/family/st/stm32f746zg/target.c index 8e642ac33..d0583c996 100644 --- a/source/family/st/stm32f746zg/target.c +++ b/source/family/st/stm32f746zg/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the + * @brief Target information for the * * DAPLink Interface Firmware * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08100000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20000000 + 0x50000, }; diff --git a/source/family/st/stm32l082cz/target.c b/source/family/st/stm32l082cz/target.c index b6bdba721..6fe6ef86d 100644 --- a/source/family/st/stm32l082cz/target.c +++ b/source/family/st/stm32l082cz/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08030000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20005000, }; diff --git a/source/family/st/stm32l151cbxxa/target.c b/source/family/st/stm32l151cbxxa/target.c index 1da0c81e3..656cfcef9 100644 --- a/source/family/st/stm32l151cbxxa/target.c +++ b/source/family/st/stm32l151cbxxa/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08000000 + KB(128), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20000000 + KB(32), }; diff --git a/source/family/st/stm32l443rc/target.c b/source/family/st/stm32l443rc/target.c index a98dbccc0..190ae8d6d 100644 --- a/source/family/st/stm32l443rc/target.c +++ b/source/family/st/stm32l443rc/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08040000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x2000c000, }; diff --git a/source/family/st/stm32l476rg/target.c b/source/family/st/stm32l476rg/target.c index 441c48f1e..7d657c5e0 100644 --- a/source/family/st/stm32l476rg/target.c +++ b/source/family/st/stm32l476rg/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the + * @brief Target information for the * * DAPLink Interface Firmware * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08100000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20018000, }; diff --git a/source/family/st/stm32l486jg/target.c b/source/family/st/stm32l486jg/target.c index d84764cd3..928f5691f 100644 --- a/source/family/st/stm32l486jg/target.c +++ b/source/family/st/stm32l486jg/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08100000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20018000, }; diff --git a/source/family/st/stm32l4xx_1024/target.c b/source/family/st/stm32l4xx_1024/target.c index 608277664..b84b304d1 100644 --- a/source/family/st/stm32l4xx_1024/target.c +++ b/source/family/st/stm32l4xx_1024/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device_stm32l475 = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08100000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20000000 + 0x00018000, .ram_regions[1].start = 0x10000188, diff --git a/source/family/st/xDot-L151/target.c b/source/family/st/xDot-L151/target.c index 310d0b28d..55e343436 100644 --- a/source/family/st/xDot-L151/target.c +++ b/source/family/st/xDot-L151/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x08000000, .flash_regions[0].end = 0x08000000 + KB(256), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20000000 + KB(32), }; diff --git a/source/family/ti/cc3220sf/target.c b/source/family/ti/cc3220sf/target.c index d7aa1f94d..aa6d34a66 100644 --- a/source/family/ti/cc3220sf/target.c +++ b/source/family/ti/cc3220sf/target.c @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x01000000, .flash_regions[0].end = 0x01000000 + MB(1), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20040000, }; diff --git a/source/family/toshiba/tz10xx/target_remap0.c b/source/family/toshiba/tz10xx/target_remap0.c index 0a0a47fa4..5d6d57b68 100644 --- a/source/family/toshiba/tz10xx/target_remap0.c +++ b/source/family/toshiba/tz10xx/target_remap0.c @@ -27,12 +27,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0, .flash_regions[0].end = MB(1), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20008000, }; diff --git a/source/family/wiznet/w7500/target.c b/source/family/wiznet/w7500/target.c index ba8a39b26..c0ab81aeb 100644 --- a/source/family/wiznet/w7500/target.c +++ b/source/family/wiznet/w7500/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the W7500 + * @brief Target information for the W7500 * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -26,12 +26,13 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x00000000, .flash_regions[0].end = 0x00000000 + KB(128), .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20004000, }; diff --git a/source/target/target_config.h b/source/target/target_config.h index 630fee846..6efcca4f4 100644 --- a/source/target/target_config.h +++ b/source/target/target_config.h @@ -28,6 +28,13 @@ #include "flash_blob.h" #include "util.h" +//! @brief Current target configuration version. +//! +//! - Version 0: Initial version. +enum _target_config_version { + kTargetConfigVersion = 0, //!< The current board info version. +}; + //! This can vary from target to target and should be in the structure or flash blob #define TARGET_AUTO_INCREMENT_PAGE_SIZE (1024) diff --git a/source/target/target_family.h b/source/target/target_family.h index 5d318087d..b4119cb65 100644 --- a/source/target/target_family.h +++ b/source/target/target_family.h @@ -26,7 +26,7 @@ #include //! @brief Creates a family ID from a vendor ID and family index within that vendor. -#define VENDOR_TO_FAMILY(vendor, family) ((vendor) << 8 | (family)) +#define CREATE_FAMILY_ID(vendor, family) ((vendor) << 8 | (family)) //! @brief States into which the target can be placed. //! @@ -72,7 +72,7 @@ enum _vendor_ids { //! @brief Unique IDs for device families supported by DAPLink. //! -//! The values of these enums are created with the VENDOR_TO_FAMILY() macro. Vendor IDs come from +//! The values of these enums are created with the CREATE_FAMILY_ID() macro. Vendor IDs come from //! the #_vendor_ids enumeration. The family index for each ID is simply an integer that is unique //! within the family. //! @@ -89,26 +89,26 @@ enum _vendor_ids { //! Then pick a unique family index by adding 1 to the highest existing family index within that //! vendor. For a family with a new vendor, the family index should be 1. typedef enum _family_id { - kStub_HWReset_FamilyID = VENDOR_TO_FAMILY(kStub_VendorID, 1), - kStub_SWVectReset_FamilyID = VENDOR_TO_FAMILY(kStub_VendorID, 2), - kStub_SWSysReset_FamilyID = VENDOR_TO_FAMILY(kStub_VendorID, 3), - kNXP_KinetisK_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 1), - kNXP_KinetisL_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 2), - kNXP_Mimxrt_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 3), - kNXP_RapidIot_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 4), - kNXP_KinetisK32W_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 5), - kNXP_LPC55xx_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 6), - kNordic_Nrf51_FamilyID = VENDOR_TO_FAMILY(kNordic_VendorID, 1), - kNordic_Nrf52_FamilyID = VENDOR_TO_FAMILY(kNordic_VendorID, 2), - kRealtek_Rtl8195am_FamilyID = VENDOR_TO_FAMILY(kRealtek_VendorID, 1), - kTI_Cc3220sf_FamilyID = VENDOR_TO_FAMILY(kTI_VendorID, 1), - kToshiba_Tz_FamilyID = VENDOR_TO_FAMILY(kToshiba_VendorID, 1), - kWiznet_W7500_FamilyID = VENDOR_TO_FAMILY(kWiznet_VendorID, 1), - kRenesas_FamilyID = VENDOR_TO_FAMILY(kRenesas_VendorID, 1), - kAmbiq_ama3b1kk_FamilyID = VENDOR_TO_FAMILY(kAmbiq_VendorID, 1), - kMaxim_MAX32660_FamilyID = VENDOR_TO_FAMILY(kMaxim_VendorID, 4), - kMaxim_MAX32630_FamilyID = VENDOR_TO_FAMILY(kMaxim_VendorID, 2), - kMaxim_MAX32620_FamilyID = VENDOR_TO_FAMILY(kMaxim_VendorID, 3), + kStub_HWReset_FamilyID = CREATE_FAMILY_ID(kStub_VendorID, 1), + kStub_SWVectReset_FamilyID = CREATE_FAMILY_ID(kStub_VendorID, 2), + kStub_SWSysReset_FamilyID = CREATE_FAMILY_ID(kStub_VendorID, 3), + kNXP_KinetisK_FamilyID = CREATE_FAMILY_ID(kNXP_VendorID, 1), + kNXP_KinetisL_FamilyID = CREATE_FAMILY_ID(kNXP_VendorID, 2), + kNXP_Mimxrt_FamilyID = CREATE_FAMILY_ID(kNXP_VendorID, 3), + kNXP_RapidIot_FamilyID = CREATE_FAMILY_ID(kNXP_VendorID, 4), + kNXP_KinetisK32W_FamilyID = CREATE_FAMILY_ID(kNXP_VendorID, 5), + kNXP_LPC55xx_FamilyID = CREATE_FAMILY_ID(kNXP_VendorID, 6), + kNordic_Nrf51_FamilyID = CREATE_FAMILY_ID(kNordic_VendorID, 1), + kNordic_Nrf52_FamilyID = CREATE_FAMILY_ID(kNordic_VendorID, 2), + kRealtek_Rtl8195am_FamilyID = CREATE_FAMILY_ID(kRealtek_VendorID, 1), + kTI_Cc3220sf_FamilyID = CREATE_FAMILY_ID(kTI_VendorID, 1), + kToshiba_Tz_FamilyID = CREATE_FAMILY_ID(kToshiba_VendorID, 1), + kWiznet_W7500_FamilyID = CREATE_FAMILY_ID(kWiznet_VendorID, 1), + kRenesas_FamilyID = CREATE_FAMILY_ID(kRenesas_VendorID, 1), + kAmbiq_ama3b1kk_FamilyID = CREATE_FAMILY_ID(kAmbiq_VendorID, 1), + kMaxim_MAX32660_FamilyID = CREATE_FAMILY_ID(kMaxim_VendorID, 4), + kMaxim_MAX32630_FamilyID = CREATE_FAMILY_ID(kMaxim_VendorID, 2), + kMaxim_MAX32620_FamilyID = CREATE_FAMILY_ID(kMaxim_VendorID, 3), } family_id_t; //! @brief Defines all characteristics of a device family. From 58a8a02e4a7a6b90be6fed6957b7b450ea281ed6 Mon Sep 17 00:00:00 2001 From: ozersa <46590392+ozersa@users.noreply.github.com> Date: Fri, 15 Oct 2021 22:14:09 +0300 Subject: [PATCH 315/617] Merge MAX32620/30/60 target reset feature (#865) * Merge MAX32620/30/60 target reset feature Signed-off-by: Sadik.Ozer * Divide familyID as MAX3262X and MAX3266X Signed-off-by: Sadik.Ozer --- records/board/max32620fthr.yaml | 2 +- records/board/max32630fthr.yaml | 2 +- records/board/max32660evsys.yaml | 2 +- source/board/max32620fthr.c | 2 +- source/board/max32630fthr.c | 2 +- source/board/max32660evsys.c | 2 +- .../maxim/max32620/target_reset_max32620.c | 111 ------------------ .../maxim/max32630/target_reset_max32630.c | 111 ------------------ ...set_max32660.c => target_reset_max32xxx.c} | 44 +++++-- source/target/target_family.c | 10 +- source/target/target_family.h | 5 +- 11 files changed, 48 insertions(+), 245 deletions(-) delete mode 100644 source/family/maxim/max32620/target_reset_max32620.c delete mode 100644 source/family/maxim/max32630/target_reset_max32630.c rename source/family/maxim/{max32660/target_reset_max32660.c => target_reset_max32xxx.c} (67%) diff --git a/records/board/max32620fthr.yaml b/records/board/max32620fthr.yaml index 07cf8cc93..449cd345a 100644 --- a/records/board/max32620fthr.yaml +++ b/records/board/max32620fthr.yaml @@ -4,4 +4,4 @@ common: - source/board/max32620fthr.c family: - source/family/maxim/max32620/target.c - - source/family/maxim/max32620/target_reset_max32620.c + - source/family/maxim/target_reset_max32xxx.c diff --git a/records/board/max32630fthr.yaml b/records/board/max32630fthr.yaml index c7ec808d9..c7bb775ef 100644 --- a/records/board/max32630fthr.yaml +++ b/records/board/max32630fthr.yaml @@ -4,4 +4,4 @@ common: - source/board/max32630fthr.c family: - source/family/maxim/max32630/target.c - - source/family/maxim/max32630/target_reset_max32630.c + - source/family/maxim/target_reset_max32xxx.c diff --git a/records/board/max32660evsys.yaml b/records/board/max32660evsys.yaml index ad86523a4..0ae6e27ab 100644 --- a/records/board/max32660evsys.yaml +++ b/records/board/max32660evsys.yaml @@ -4,4 +4,4 @@ common: - source/board/max32660evsys.c family: - source/family/maxim/max32660/target.c - - source/family/maxim/max32660/target_reset_max32660.c + - source/family/maxim/target_reset_max32xxx.c diff --git a/source/board/max32620fthr.c b/source/board/max32620fthr.c index 6e7d42554..ac818e050 100644 --- a/source/board/max32620fthr.c +++ b/source/board/max32620fthr.c @@ -25,7 +25,7 @@ const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "0418", - .family_id = kMaxim_MAX32620_FamilyID, + .family_id = kMaxim_MAX3262X_FamilyID, .flags = kEnablePageErase, .target_cfg = &target_device, }; diff --git a/source/board/max32630fthr.c b/source/board/max32630fthr.c index 8b277222b..f42917228 100644 --- a/source/board/max32630fthr.c +++ b/source/board/max32630fthr.c @@ -25,7 +25,7 @@ const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "0409", - .family_id = kMaxim_MAX32630_FamilyID, + .family_id = kMaxim_MAX3262X_FamilyID, .flags = kEnablePageErase, .target_cfg = &target_device, }; diff --git a/source/board/max32660evsys.c b/source/board/max32660evsys.c index 00651d0f9..8fb685050 100644 --- a/source/board/max32660evsys.c +++ b/source/board/max32660evsys.c @@ -42,7 +42,7 @@ const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "0421", - .family_id = kMaxim_MAX32660_FamilyID, + .family_id = kMaxim_MAX3266X_FamilyID, .flags = kEnablePageErase, .target_cfg = &target_device, .daplink_url_name = "MAX32660HTM", diff --git a/source/family/maxim/max32620/target_reset_max32620.c b/source/family/maxim/max32620/target_reset_max32620.c deleted file mode 100644 index 7315602c7..000000000 --- a/source/family/maxim/max32620/target_reset_max32620.c +++ /dev/null @@ -1,111 +0,0 @@ -/** - * @file target_reset.c - * @brief Target reset for the MAX32620 - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "target_family.h" -#include "swd_host.h" -#include "DAP_Config.h" -#include "target_board.h" - -#define DBG_Addr (0xe000edf0) // Default Core debug base addresses - -#define TARGET_MXC_BASE_FLC ((uint32_t)0x40002000UL) // Flash controller base address -#define TARGET_MXC_R_FLC_PERFORM (TARGET_MXC_BASE_FLC + (uint32_t)0x00000050UL) // Flash controller perform register - -#define INCREASE_DELAY 10 -#define MAX_DELAY 30000 - - -/* RESET_PROGRAM state halts the processor on reset by default but the SWD - * is unavailable for 1024 clocks after reset. - * This code will reset and halt after the SWD lockout period. - */ -static uint8_t target_set_state_max32620(target_state_t state) -{ - unsigned int halt_timeout, halt_retries = 10; - unsigned int lockout_delay, i; - uint32_t val; - - if (state != RESET_PROGRAM) { - return swd_set_target_state_hw(state); - } - - /* Reset the target and halt it when SWD is available */ - while (halt_retries--) { - halt_timeout = 10; - lockout_delay = 0; - - /* Wait for SWD lockout period after reset */ - do { - swd_init(); - - PIN_nRESET_OUT(0); - for (i = 0; i < 1000; i++); - PIN_nRESET_OUT(1); - for (i = 0; i < lockout_delay; i++); - - lockout_delay += INCREASE_DELAY; - - } while ((JTAG2SWD() == 0) && (lockout_delay < MAX_DELAY)); - - if (lockout_delay >= MAX_DELAY) { - continue; - } - - if (!swd_write_dp(DP_CTRL_STAT, CSYSPWRUPREQ | CDBGPWRUPREQ | TRNNORMAL | MASKLANE)) { - continue; - } - - /* Dummy read here forces the line buffer to actually read flash the - * next time the flash memory base address has to be read. - * Generally, address read here should be an offset by atleast the size - * of line buffer (128 bytes) from the base address. - */ - uint8_t tmp; - swd_read_byte(g_board_info.target_cfg->flash_regions[0].start + 0x2000, &tmp); - - /* Set the Debug, and Halt bits and wait until core is halted or timeout */ - if (swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN | C_HALT)) { - do { - if (!swd_read_word(DBG_HCSR, &val)) { - break; - } - } while (((val & S_HALT) == 0) && (halt_timeout--)); - } - - if (val & S_HALT) { - /* Setting the Flash Controller Perform register to 0 allows - * the Flash Controller pending bit to clear, otherwise the - * bit remains set which could fail flash operation. - */ - val = 0; - swd_write_word(TARGET_MXC_R_FLC_PERFORM, val); - - return 1; - } - } - - return 0; -} - -const target_family_descriptor_t g_maxim_max32620 = { - .family_id = kMaxim_MAX32620_FamilyID, - .target_set_state = target_set_state_max32620, - .default_reset_type = kHardwareReset, -}; diff --git a/source/family/maxim/max32630/target_reset_max32630.c b/source/family/maxim/max32630/target_reset_max32630.c deleted file mode 100644 index a2236c786..000000000 --- a/source/family/maxim/max32630/target_reset_max32630.c +++ /dev/null @@ -1,111 +0,0 @@ -/** - * @file target_reset.c - * @brief Target reset for the MAX32630 - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "target_family.h" -#include "swd_host.h" -#include "DAP_Config.h" -#include "target_board.h" - -#define DBG_Addr (0xe000edf0) // Default Core debug base addresses - -#define TARGET_MXC_BASE_FLC ((uint32_t)0x40002000UL) // Flash controller base address -#define TARGET_MXC_R_FLC_PERFORM (TARGET_MXC_BASE_FLC + (uint32_t)0x00000050UL) // Flash controller perform register - -#define INCREASE_DELAY 10 -#define MAX_DELAY 30000 - - -/* RESET_PROGRAM state halts the processor on reset by default but the SWD - * is unavailable for 1024 clocks after reset. - * This code will reset and halt after the SWD lockout period. - */ -static uint8_t target_set_state_max32630(target_state_t state) -{ - unsigned int halt_timeout, halt_retries = 10; - unsigned int lockout_delay, i; - uint32_t val; - - if (state != RESET_PROGRAM) { - return swd_set_target_state_hw(state); - } - - /* Reset the target and halt it when SWD is available */ - while (halt_retries--) { - halt_timeout = 10; - lockout_delay = 0; - - /* Wait for SWD lockout period after reset */ - do { - swd_init(); - - PIN_nRESET_OUT(0); - for (i = 0; i < 1000; i++); - PIN_nRESET_OUT(1); - for (i = 0; i < lockout_delay; i++); - - lockout_delay += INCREASE_DELAY; - - } while ((JTAG2SWD() == 0) && (lockout_delay < MAX_DELAY)); - - if (lockout_delay >= MAX_DELAY) { - continue; - } - - if (!swd_write_dp(DP_CTRL_STAT, CSYSPWRUPREQ | CDBGPWRUPREQ | TRNNORMAL | MASKLANE)) { - continue; - } - - /* Dummy read here forces the line buffer to actually read flash the - * next time the flash memory base address has to be read. - * Generally, address read here should be an offset by atleast the size - * of line buffer (128 bytes) from the base address. - */ - uint8_t tmp; - swd_read_byte(g_board_info.target_cfg->flash_regions[0].start + 0x2000, &tmp); - - /* Set the Debug, and Halt bits and wait until core is halted or timeout */ - if (swd_write_word(DBG_HCSR, DBGKEY | C_DEBUGEN | C_HALT)) { - do { - if (!swd_read_word(DBG_HCSR, &val)) { - break; - } - } while (((val & S_HALT) == 0) && (halt_timeout--)); - } - - if (val & S_HALT) { - /* Setting the Flash Controller Perform register to 0 allows - * the Flash Controller pending bit to clear, otherwise the - * bit remains set which could fail flash operation. - */ - val = 0; - swd_write_word(TARGET_MXC_R_FLC_PERFORM, val); - - return 1; - } - } - - return 0; -} - -const target_family_descriptor_t g_maxim_max32630 = { - .family_id = kMaxim_MAX32630_FamilyID, - .target_set_state = target_set_state_max32630, - .default_reset_type = kHardwareReset, -}; diff --git a/source/family/maxim/max32660/target_reset_max32660.c b/source/family/maxim/target_reset_max32xxx.c similarity index 67% rename from source/family/maxim/max32660/target_reset_max32660.c rename to source/family/maxim/target_reset_max32xxx.c index 3efcd2b24..3123144c4 100644 --- a/source/family/maxim/max32660/target_reset_max32660.c +++ b/source/family/maxim/target_reset_max32xxx.c @@ -1,6 +1,6 @@ /** - * @file target_reset.c - * @brief Target reset for the MAX32660 + * @file target_reset_max32xxx.c + * @brief Target reset for the Maxim micros * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -25,7 +25,12 @@ #define DBG_Addr (0xe000edf0) // Default Core debug base addresses -#define TARGET_MXC_BASE_FLC ((uint32_t)0x40029000UL) // Flash controller base address +// +#define MAX3262X_FLC_BASE ((uint32_t)0x40002000UL) // Flash controller base address +#define MAX3262X_R_FLC_PERFORM (MAX3262X_FLC_BASE + (uint32_t)0x50UL) // Flash controller perform register +// +#define MAX3266X_FLC_BASE ((uint32_t)0x40029000UL) // Flash controller base address + #define INCREASE_DELAY 10 #define MAX_DELAY 30000 @@ -35,7 +40,7 @@ * is unavailable for 1024 clocks after reset. * This code will reset and halt after the SWD lockout period. */ -static uint8_t target_set_state_max32660(target_state_t state) +static uint8_t target_set_state_max326xx(target_state_t state, uint32_t reg_flc_perform) { unsigned int halt_timeout, halt_retries = 10; unsigned int lockout_delay, i; @@ -89,15 +94,38 @@ static uint8_t target_set_state_max32660(target_state_t state) } if (val & S_HALT) { - return 1; + if (reg_flc_perform) { + /* Setting the Flash Controller Perform register to 0 allows + * the Flash Controller pending bit to clear, otherwise the + * bit remains set which could fail flash operation. + */ + val = 0; + swd_write_word(reg_flc_perform, val); + } + + return 1; } } return 0; } -const target_family_descriptor_t g_maxim_max32660 = { - .family_id = kMaxim_MAX32660_FamilyID, - .target_set_state = target_set_state_max32660, +static uint8_t target_set_state_max3262x(target_state_t state) { + return target_set_state_max326xx(state, MAX3262X_R_FLC_PERFORM); +} + +static uint8_t target_set_state_max3266x(target_state_t state) { + return target_set_state_max326xx(state, 0); +} + +const target_family_descriptor_t g_maxim_max3262x_family = { + .family_id = kMaxim_MAX3262X_FamilyID, + .target_set_state = target_set_state_max3262x, + .default_reset_type = kHardwareReset, +}; + +const target_family_descriptor_t g_maxim_max3266x_family = { + .family_id = kMaxim_MAX3266X_FamilyID, + .target_set_state = target_set_state_max3266x, .default_reset_type = kHardwareReset, }; diff --git a/source/target/target_family.c b/source/target/target_family.c index d92eb88d4..556696360 100644 --- a/source/target/target_family.c +++ b/source/target/target_family.c @@ -58,9 +58,8 @@ __WEAK const target_family_descriptor_t g_wiznet_family = {0}; __WEAK const target_family_descriptor_t g_renesas_family = {0}; __WEAK const target_family_descriptor_t g_toshiba_tz_family = {0}; __WEAK const target_family_descriptor_t g_ambiq_ama3b1kk = {0}; -__WEAK const target_family_descriptor_t g_maxim_max32660 = {0}; -__WEAK const target_family_descriptor_t g_maxim_max32630 = {0}; -__WEAK const target_family_descriptor_t g_maxim_max32620 = {0}; +__WEAK const target_family_descriptor_t g_maxim_max3262x_family = {0}; +__WEAK const target_family_descriptor_t g_maxim_max3266x_family = {0}; //! @brief Terminator value for g_families list. //! @@ -93,9 +92,8 @@ const target_family_descriptor_t *g_families[] = { &g_renesas_family, &g_toshiba_tz_family, &g_ambiq_ama3b1kk, - &g_maxim_max32660, - &g_maxim_max32630, - &g_maxim_max32620, + &g_maxim_max3262x_family, + &g_maxim_max3266x_family, FAMILY_LIST_TERMINATOR // list terminator }; diff --git a/source/target/target_family.h b/source/target/target_family.h index b4119cb65..20141106d 100644 --- a/source/target/target_family.h +++ b/source/target/target_family.h @@ -106,9 +106,8 @@ typedef enum _family_id { kWiznet_W7500_FamilyID = CREATE_FAMILY_ID(kWiznet_VendorID, 1), kRenesas_FamilyID = CREATE_FAMILY_ID(kRenesas_VendorID, 1), kAmbiq_ama3b1kk_FamilyID = CREATE_FAMILY_ID(kAmbiq_VendorID, 1), - kMaxim_MAX32660_FamilyID = CREATE_FAMILY_ID(kMaxim_VendorID, 4), - kMaxim_MAX32630_FamilyID = CREATE_FAMILY_ID(kMaxim_VendorID, 2), - kMaxim_MAX32620_FamilyID = CREATE_FAMILY_ID(kMaxim_VendorID, 3), + kMaxim_MAX3262X_FamilyID = CREATE_FAMILY_ID(kMaxim_VendorID, 1), + kMaxim_MAX3266X_FamilyID = CREATE_FAMILY_ID(kMaxim_VendorID, 2), } family_id_t; //! @brief Defines all characteristics of a device family. From fdada325310205ca3db28d441963fb2799ae5449 Mon Sep 17 00:00:00 2001 From: ozersa <46590392+ozersa@users.noreply.github.com> Date: Fri, 15 Oct 2021 23:47:22 +0300 Subject: [PATCH 316/617] Add MAX32666FTHR and remove MAX32665HSP (#869) * Add MAX32666FTHR * Remove MAX32665HSP Signed-off-by: Sadik.Ozer --- projects.yaml | 4 +- records/board/max32665hsp.yaml | 6 -- records/board/max32666fthr.yaml | 7 ++ source/board/max32665hsp.c | 47 -------- source/board/max32666fthr.c | 33 ++++++ source/family/maxim/max32665/flash_blob.c | 126 ---------------------- source/family/maxim/max32665/target.c | 55 ---------- source/family/maxim/max32666/flash_blob.c | 80 ++++++++++++++ source/family/maxim/max32666/target.c | 36 +++++++ test/info.py | 6 +- 10 files changed, 161 insertions(+), 239 deletions(-) delete mode 100644 records/board/max32665hsp.yaml create mode 100644 records/board/max32666fthr.yaml delete mode 100644 source/board/max32665hsp.c create mode 100644 source/board/max32666fthr.c delete mode 100644 source/family/maxim/max32665/flash_blob.c delete mode 100644 source/family/maxim/max32665/target.c create mode 100644 source/family/maxim/max32666/flash_blob.c create mode 100644 source/family/maxim/max32666/target.c diff --git a/projects.yaml b/projects.yaml index 8d4c77d0d..2926040e7 100644 --- a/projects.yaml +++ b/projects.yaml @@ -650,10 +650,10 @@ projects: - *module_if - *module_hic_max32625 - records/board/max32660evsys.yaml - max32625_max32665hsp_if: + max32625_max32666fthr_if: - *module_if - *module_hic_max32625 - - records/board/max32665hsp.yaml + - records/board/max32666fthr.yaml sam3u2c_mkit_dk_dongle_nrf5x_if: - *module_if - *module_hic_sam3u2c diff --git a/records/board/max32665hsp.yaml b/records/board/max32665hsp.yaml deleted file mode 100644 index 3da81d492..000000000 --- a/records/board/max32665hsp.yaml +++ /dev/null @@ -1,6 +0,0 @@ -common: - sources: - board: - - source/board/max32665hsp.c - family: - - source/family/maxim/max32665/target.c diff --git a/records/board/max32666fthr.yaml b/records/board/max32666fthr.yaml new file mode 100644 index 000000000..ad49fd967 --- /dev/null +++ b/records/board/max32666fthr.yaml @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/max32666fthr.c + family: + - source/family/maxim/max32666/target.c + - source/family/maxim/target_reset_max32xxx.c diff --git a/source/board/max32665hsp.c b/source/board/max32665hsp.c deleted file mode 100644 index 1417c9d7a..000000000 --- a/source/board/max32665hsp.c +++ /dev/null @@ -1,47 +0,0 @@ -/** - * @file max32665hsp.c - * @brief board ID for the Maxim Integrated's MAX32665HSP - * - * DAPLink Interface Firmware - * - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* -*/ - -#include "target_family.h" -#include "target_board.h" - -const board_info_t g_board_info = { - .board_id = "0419", - .family_id = kStub_SWSysReset_FamilyID, - .flags = kEnablePageErase, - .target_cfg = &target_device, -}; diff --git a/source/board/max32666fthr.c b/source/board/max32666fthr.c new file mode 100644 index 000000000..785aa5764 --- /dev/null +++ b/source/board/max32666fthr.c @@ -0,0 +1,33 @@ +/** + * @file max32666fthr.c + * @brief board ID for the Maxim Integrated's max32666fthr + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_family.h" +#include "target_board.h" + +const board_info_t g_board_info = { + .info_version = kBoardInfoVersion, + .board_id = "0422", + .family_id = kMaxim_MAX3266X_FamilyID, + .flags = kEnablePageErase, + .target_cfg = &target_device, + .daplink_url_name = "MAX32666HTM", + .daplink_target_url = "http://www.maximintegrated.com/max32666fthr", +}; diff --git a/source/family/maxim/max32665/flash_blob.c b/source/family/maxim/max32665/flash_blob.c deleted file mode 100644 index 5d81677a6..000000000 --- a/source/family/maxim/max32665/flash_blob.c +++ /dev/null @@ -1,126 +0,0 @@ -/** - * @file flash_blob.c - * @brief Flash algorithm for the MAX32665 - * - * DAPLink Interface Firmware - * - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* -*/ - -#include "flash_blob.h" - - -const uint32_t flash_algo_blob[] = { - 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, - 0x2400b5f8, 0x4605460e, 0x0f0ff010, 0xf06fbf1c, 0xbdf80002, 0x5080f1a5, 0xf5b049fe, 0xd30a2f00, - 0x2000f5a0, 0xf5b04afc, 0xd3102f00, 0x5084f1a5, 0x4f80f5b0, 0x460cd201, 0xf1a5e00a, 0xf5a05084, - 0xf5b04080, 0xbf284f80, 0x0002f06f, 0x4614d201, 0x28002000, 0xbdf8bf18, 0x46284669, 0xfa6af000, - 0xbfb82800, 0x68a0bdf8, 0x0f07f010, 0xf06fbf18, 0xd10e0005, 0xf0106a60, 0xd0030f02, 0xf0206a60, - 0x62610102, 0xf02068a0, 0xf0404070, 0x60a15100, 0x28002000, 0xbdf8bf18, 0xf02068a0, 0x60a00010, - 0x60209800, 0x63206830, 0x63606870, 0x63a068b0, 0x63e068f0, 0xf04068a0, 0x60a00001, 0xf01068a0, - 0xd1fb0f07, 0xf02068a0, 0x60a04070, 0xf0106a60, 0xd0060f02, 0xf0206a60, 0x62600002, 0x0006f06f, - 0xf04fbdf8, 0x68014080, 0x0140f041, 0x68016001, 0x0f40f011, 0x2004d1fb, 0x0110f105, 0xbf8842a9, - 0x0080eb05, 0x6829d90a, 0x42916832, 0xf06fd002, 0xbdf80006, 0x1d361d2d, 0xd8f442a8, 0xbdf82000, - 0x45f0e92d, 0xb0872600, 0x1e704603, 0x90059600, 0x960148ba, 0x96039602, 0x6802460f, 0x46314635, - 0x6f00f412, 0x6800bf07, 0x5f80f410, 0x0006f06f, 0xbf18b007, 0x85f0e8bd, 0x0f03f013, 0xf06fbf1e, - 0xb0070002, 0x85f0e8bd, 0x1d1c4618, 0x0c01f04f, 0x4284aa05, 0xeb00bf88, 0xd90b0c8c, 0xf8d26804, - 0x45448000, 0xf06fd002, 0xe0030106, 0x1d121d00, 0xd8f34584, 0xbf1c0008, 0xe8bdb007, 0xf00385f0, - 0xf023080f, 0xf1aa0a0f, 0x499a5080, 0x2f00f5b0, 0xf5a0d30a, 0x4a982000, 0x2f00f5b0, 0xf1aad310, - 0xf5b05084, 0xd2014f80, 0xe00a460d, 0x5084f1aa, 0x4080f5a0, 0x4f80f5b0, 0xf06fbf28, 0xd2010002, - 0x20004615, 0xbf1c2800, 0xe8bdb007, 0xa90485f0, 0xf0004650, 0x2800f99f, 0xb007bfbc, 0x85f0e8bd, - 0xf01068a8, 0xbf180f07, 0x0005f06f, 0x6a68d10e, 0x0f02f010, 0x6a68d003, 0x0102f020, 0x68a86269, - 0x4070f020, 0x5100f040, 0x200060a9, 0xbf1c2800, 0xe8bdb007, 0x465485f0, 0x0010f10a, 0xbf384582, - 0xd2064669, 0x2b04f854, 0x2026f841, 0x42841c76, 0x9804d3f8, 0xf1b86028, 0xbf380f04, 0xd3099700, - 0x0f08f1b8, 0x9701bf38, 0xf1b8d304, 0xbf340f0c, 0x97039702, 0x46504669, 0xfec2f7ff, 0xe8bdb007, - 0x200085f0, 0x4a644b63, 0xb148e00a, 0xbf0c2801, 0x21004611, 0xf0116889, 0xd0030f07, 0x47702001, - 0xe7f74619, 0x28021c40, 0x2000dbef, 0x20004770, 0x20014770, 0xb4104770, 0xf04f2100, 0x4c554280, - 0xc154f8df, 0xb151e00b, 0xbf0c2901, 0x20004660, 0xf0136883, 0xd0040f07, 0x2001bc10, 0x46204770, - 0x6a43e7f6, 0x0f02f013, 0x6a43d003, 0x0302f023, 0x68836243, 0x4370f023, 0x5300f043, 0x68836083, - 0x437ff423, 0x432af443, 0x68836083, 0x0302f043, 0x68836083, 0x0f07f013, 0x6883d1fb, 0x4370f023, - 0x6a436083, 0x0f02f013, 0x6a41d006, 0x0102f021, 0xbc106241, 0x47702001, 0xf0406810, 0x60100040, - 0xf0106810, 0xd1fb0f40, 0x29021c49, 0xbc10dbbb, 0x47702000, 0xf1a0b5f8, 0x4e2e5180, 0x46024d2e, - 0x2f00f5b1, 0x4634d201, 0xf1a0e007, 0xf5a15180, 0xf5b12100, 0xd20b2f00, 0x4669462c, 0xf0004610, - 0x2800f8d9, 0x68a0bf04, 0x0f07f010, 0xe00dd10c, 0x5184f1a0, 0x4f80f5b1, 0xf1a2d3e5, 0xf5a05084, - 0xf5b04080, 0xd3e74f80, 0xbdf82001, 0xf0106a60, 0xd0030f02, 0xf0206a60, 0x62610102, 0xf02068a0, - 0xf0404070, 0x60a15100, 0xf42068a0, 0xf440407f, 0x60a040aa, 0x60209800, 0xf04068a0, 0x60a00004, - 0xe0202000, 0x2801b1f8, 0x4629bf0c, 0x68892100, 0x0f07f011, 0x1c40d1f4, 0xdbf32802, 0xf02068a0, - 0x60a04070, 0xf0106a60, 0xd00e0f02, 0xf0206a60, 0xe0050002, 0x40029000, 0x40029400, 0x40006c00, - 0x20016260, 0x4631bdf8, 0xf04fe7e1, 0x68014080, 0x0140f041, 0x68016001, 0x0f40f011, 0x2000d1fb, - 0xe92dbdf8, 0x461645f8, 0x4605460c, 0xf010466f, 0xd0270f03, 0x0003f025, 0x0a03f005, 0x0804f1ca, - 0x90006800, 0x0004f1c8, 0x46424438, 0xf0004631, 0xeba5f88c, 0x9900000a, 0xfe52f7ff, 0xbf182800, - 0x85f8e8bd, 0xeba44445, 0x44460408, 0x4628e00a, 0xf7ff6831, 0x2800fe45, 0xe8bdbf18, 0x1f2485f8, - 0x1d361d2d, 0xd3022c04, 0x0f0ff015, 0x2c10d1ef, 0x4631d30c, 0xf7ff4628, 0x2800fda3, 0xe8bdbf18, - 0x3c1085f8, 0x36103510, 0xd2f22c10, 0xd30c2c04, 0x68314628, 0xfe24f7ff, 0xbf182800, 0x85f8e8bd, - 0x1d2d1f24, 0x2c041d36, 0xb174d2f2, 0x90006828, 0x46314622, 0xf0004668, 0x4628f848, 0xf7ff6839, - 0x2800fe0f, 0xe8bdbf18, 0x200085f8, 0x85f8e8bd, 0xeb000889, 0x42810181, 0x6803d90a, 0xc000f8d2, - 0xd0014563, 0x47702001, 0x1d121d00, 0xd8f44281, 0x47702000, 0x5280f1a0, 0x2f00f5b2, 0xf3c0bf3c, - 0x60080012, 0xf1a0d31f, 0xf5a25280, 0xf5b22200, 0xbf3c2f00, 0x2000f5a0, 0x0012f3c0, 0xf1a0d312, - 0xf5b25284, 0xd3094f80, 0x4280f5a2, 0x4f80f5b2, 0xf5a0bf32, 0xf06f4080, 0x47700002, 0x000df3c0, - 0x2000f500, 0x20006008, 0xea404770, 0x079b0301, 0xe009d003, 0x1f12c908, 0x2a04c008, 0xe003d2fa, - 0x3b01f811, 0x3b01f800, 0xd2f91e52, 0x00004770, 0x00000000 -}; - -/** -* List of start and size for each size of flash sector -* The size will apply to all sectors between the listed address and the next address -* in the list. -* The last pair in the list will have sectors starting at that address and ending -* at address start + size. -*/ -static const sector_info_t sectors_info[] = { - {0x10000000, 0x2000}, - }; - -const program_target_t flash = { - 0x200002a3, // Init - 0x200002cf, // UnInit - 0x200002d7, // EraseChip - 0x20000375, // EraseSector - 0x20000463, // ProgramPage - 0x20000531, // Verify - - // BKPT : start of blob + 1 - // RSB : blob start + header + rw data offset - // RSP : stack pointer - { - 0x20000001, - 0x200005d0, - 0x20000800 - }, - - 0x20000000 + 0x00000A00, // program_buffer - 0x20000000, // algo_start - sizeof(flash_algo_blob), // algo_size - flash_algo_blob, // image - - 0x00002000 // ram_to_flash_bytes_to_be_written -}; diff --git a/source/family/maxim/max32665/target.c b/source/family/maxim/max32665/target.c deleted file mode 100644 index 982349117..000000000 --- a/source/family/maxim/max32665/target.c +++ /dev/null @@ -1,55 +0,0 @@ -/** - * @file target.c - * @brief Target information for the MAX32665 - * - * DAPLink Interface Firmware - * - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* -*/ - -#include "target_config.h" - -#include "flash_blob.c" - -/* ME14 -- MAX32665 1MiB Flash, 560KiB RAM */ -target_cfg_t target_device = { - .version = kTargetConfigVersion, - .sectors_info = sectors_info, - .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), - .flash_regions[0].start = 0x10000000, - .flash_regions[0].end = 0x10100000, - .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, - .ram_regions[0].start = 0x20000000, - .ram_regions[0].end = 0x2008C000, -}; - diff --git a/source/family/maxim/max32666/flash_blob.c b/source/family/maxim/max32666/flash_blob.c new file mode 100644 index 000000000..f48be7110 --- /dev/null +++ b/source/family/maxim/max32666/flash_blob.c @@ -0,0 +1,80 @@ +/** + * @file flash_blob.c + * @brief Flash algorithm for the MAX32666 + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "flash_blob.h" + +#define FLC_BASE 0x40029000 +#define CLOCK_DIV 0x00000060 +#define BURST_SIZE 0x00000080 +#define FLASH_BASE 0x10000000 +#define FLASH_SIZE MB(1) +#define FLASH_SECTOR KB(8) + +static const uint32_t flash_algo_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x44494975, 0x68826808, 0x0f07f012, 0x2001bf1c, 0x68494770, 0x20006041, 0x486f4770, 0x68004448, + 0xf0216881, 0x60814170, 0x47702000, 0xb510486a, 0x68044448, 0xf8b4f000, 0x68a0b9b0, 0x407ff420, + 0x402af440, 0x68a060a0, 0x0002f040, 0x68a060a0, 0x0f02f010, 0x68a0d1fb, 0x4070f020, 0x6a6060a0, + 0x0002f010, 0xbd10bf08, 0xbd102001, 0x4605b570, 0x44484859, 0xf0006804, 0xb9b8f893, 0xf42068a0, + 0xf440407f, 0x60a040aa, 0x68a06025, 0x0004f040, 0x68a060a0, 0x0f04f010, 0x68a0d1fb, 0x4070f020, + 0x6a6060a0, 0x0002f010, 0xbd70bf08, 0xbd702001, 0x41f0e92d, 0x8120f8df, 0x44c8460d, 0xf8d84606, + 0x46174000, 0x0f03f012, 0xf000d167, 0x2800f869, 0xe00dd163, 0xf8576026, 0x63200b04, 0xf04068a0, + 0x60a00001, 0xf01068a0, 0xd1fb0f01, 0x1d361f2d, 0xd3022d04, 0x0f1ff016, 0xf8d8d1ec, 0x28800008, + 0x2d10d11a, 0x6026d318, 0x0b04f857, 0xf8576320, 0x63600b04, 0x0b04f857, 0xf85763a0, 0x63e00b04, + 0xf04068a0, 0x60a00001, 0xf01068a0, 0xd1fb0f01, 0x36103d10, 0xd2e62d10, 0xd30f2d04, 0xf8576026, + 0x63200b04, 0xf04068a0, 0x60a00001, 0xf01068a0, 0xd1fb0f01, 0x1d361f2d, 0xd2ef2d04, 0x683ab19d, + 0x31fff04f, 0xea6220ff, 0x40190300, 0x1e6d0200, 0x6026d1f9, 0x68a06321, 0x0001f040, 0x68a060a0, + 0x0f01f010, 0x68a0d1fb, 0x4070f020, 0x6a6060a0, 0x0002f010, 0xe8bdbf08, 0x200181f0, 0x81f0e8bd, + 0x4448480d, 0x68816800, 0x0f07f011, 0x6a41d109, 0x2100b149, 0x6a416241, 0x2102b129, 0x6a416241, + 0x2001b109, 0x68814770, 0x4170f021, 0x5100f041, 0x20006081, 0x00004770, 0x00000004, 0x00000000, + FLC_BASE, CLOCK_DIV, BURST_SIZE, +}; + +/** +* List of start and size for each size of flash sector - even indexes are start, odd are size +* The size will apply to all sectors between the listed address and the next address +* in the list. +* The last pair in the list will have sectors starting at that address and ending +* at address flash_start + flash_size. +*/ +static const sector_info_t sectors_info[] = { + FLASH_BASE, FLASH_SECTOR, +}; + +static const program_target_t flash = { + 0x20000021, // Init + 0x2000003b, // UnInit + 0x2000004d, // EraseChip + 0x2000008d, // EraseSector + 0x200000d1, // ProgramPage + 0x00000000, // Verify + { + 0x20000001, // BKPT : start of blob + 1 + 0x200001fc, // RSB : blob start + header + rw data offset + 0x20000500 // RSP : stack pointer + }, + + 0x20000000 + 0x00000A00, // mem buffer location + 0x20000000, // location to write prog_blob in target RAM + sizeof(flash_algo_blob), // prog_blob size + flash_algo_blob, // address of prog_blob + 0x00000400 // ram_to_flash_bytes_to_be_written +}; diff --git a/source/family/maxim/max32666/target.c b/source/family/maxim/max32666/target.c new file mode 100644 index 000000000..b9524f370 --- /dev/null +++ b/source/family/maxim/max32666/target.c @@ -0,0 +1,36 @@ +/** + * @file target.c + * @brief Target information for the MAX32666 + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_config.h" + +#include "flash_blob.c" + +/* MAX32666 1MiB Flash, 560KiB RAM */ +target_cfg_t target_device = { + .sectors_info = sectors_info, + .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), + .flash_regions[0].start = FLASH_BASE, + .flash_regions[0].end = FLASH_BASE + FLASH_SIZE, + .flash_regions[0].flags = kRegionIsDefault, + .flash_regions[0].flash_algo = (program_target_t *) &flash, + .ram_regions[0].start = 0x20000000, + .ram_regions[0].end = 0x20000000 + KB(560), +}; diff --git a/test/info.py b/test/info.py index 30e8314d9..6b07b2873 100644 --- a/test/info.py +++ b/test/info.py @@ -131,7 +131,7 @@ ('max32625_max32620fthr_if', False, 0x0000, "bin" ), ('max32625_max32630fthr_if', False, 0x0000, "bin" ), ('max32625_max32660evsys_if', False, 0x0000, "bin" ), - ('max32625_max32665hsp_if', False, 0x0000, "bin" ), + ('max32625_max32666fthr_if', False, 0x0000, "bin" ), ('kl26z_if', False, 0x0000, "bin" ), ('k20dx_if', False, 0x0000, "bin" ), ('k26f_if', False, 0x0000, "bin" ), @@ -193,10 +193,10 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0350, VENDOR_TO_FAMILY('Stub', 1), 'k20dx_xdot_l151_if', 'k20dx_bl', None ), # TODO - set target to 'MTS-xDot-L151CC' when mbed-os supports this ( 0x0360, VENDOR_TO_FAMILY('NXP', 1), 'lpc4322_hani_iot_if', 'lpc4322_bl', 'HANI-IOT' ), ( 0x0409, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32630fthr_if', 'max32625_bl', 'MAX32630' ), - ( 0x0419, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32665hsp_if', 'max32625_bl', 'MAX32665' ), ( 0x0415, VENDOR_TO_FAMILY('Stub', 1), 'max32620_max32625mbed_if', 'max32620_bl', 'MAX32625' ), ( 0x0418, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32620fthr_if', 'max32625_bl', 'MAX32620' ), ( 0x0421, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32660evsys_if', 'max32625_bl', 'MAX32660' ), + ( 0x0422, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32666fthr_if', 'max32625_bl', 'MAX32666' ), ( 0x0450, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_ublox_odin_w2_if', None, None ), ( 0x0451, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_mxchip_emw3166_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0453, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_mts_xdot_if', None, None ), @@ -363,8 +363,8 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y 0x0409, # MAX32630FTHR 0x0415, # MAX32625MBED 0x0418, # MAX32620FTHR - 0x0419, # MAX32665HSP 0x0421, # MAX32660EVSYS + 0x0422, # MAX32666FTHR 0x0450, # mtb_ublox_odin_w2 0x0456, # lpc11u35_mtb_murata_abz_078_if 0x0457, # lpc11u35_mtb_rak811_if From db0c15e73d4bc92137bec39240a763845c008bc9 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Thu, 14 Oct 2021 10:31:03 -0500 Subject: [PATCH 317/617] CONTRIBUTING.md: clarify some licensing rules. --- CONTRIBUTING.md | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index ac8b40f23..634720b2a 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -52,6 +52,17 @@ file. If a file is newly added by you, it must contain the standard license head require an Arm copyright. Please note that we do not list changes in each source file by copyright owner, as this becomes a burden to maintain. +Exceptions to Apache 2.0 licensing can be made for imported source libraries, usually drivers for +HICs or target families. In such cases, the license must be listed by the [Open Source Initiative](https://opensource.org) +(OSI) and is required to be compatible with Apache 2.0. In addition, the Arm open source team must have +previously approved use of the license—if this is not the case, then a request for approval can be +made as long as the license meets other requirements. In all cases, license exceptions will be reviewed +by the maintainers. + +All source files, including any imported sources with other license, must include an +[SPDX License Identifier](https://spdx.dev/ids/) in the header comment. This allows for easy and +clear identification of the file's license. + ## Process From 4021607dca616069648db4e09a0f7702f5d07788 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 15 Oct 2021 19:16:48 -0500 Subject: [PATCH 318/617] Fix MSD flashing for kl26z (microbit) (#853) * Call swd_init_debug() after reset + fix ACK checks --- source/daplink/interface/swd_host.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/source/daplink/interface/swd_host.c b/source/daplink/interface/swd_host.c index d98fa2c64..ea6d07974 100644 --- a/source/daplink/interface/swd_host.c +++ b/source/daplink/interface/swd_host.c @@ -4,7 +4,7 @@ * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * Copyright 2019, Cypress Semiconductor Corporation + * Copyright 2019, Cypress Semiconductor Corporation * or a subsidiary of Cypress Semiconductor Corporation. * SPDX-License-Identifier: Apache-2.0 * @@ -1051,35 +1051,39 @@ uint8_t swd_set_target_state_sw(target_state_t state) osDelay(2); swd_set_target_reset(0); osDelay(2); - + + if (!swd_init_debug()) { + return 0; + } + // Power down // Per ADIv6 spec. Clear first CSYSPWRUPREQ followed by CDBGPWRUPREQ if (!swd_read_dp(DP_CTRL_STAT, &val)) { return 0; } - + if (!swd_write_dp(DP_CTRL_STAT, val & ~CSYSPWRUPREQ)) { return 0; } - + // Wait until ACK is deasserted do { if (!swd_read_dp(DP_CTRL_STAT, &val)) { return 0; } - } while ((val & (CSYSPWRUPACK)) == 1); - + } while ((val & (CSYSPWRUPACK)) != 0); + if (!swd_write_dp(DP_CTRL_STAT, val & ~CDBGPWRUPREQ)) { return 0; } - + // Wait until ACK is deasserted do { if (!swd_read_dp(DP_CTRL_STAT, &val)) { return 0; } - } while ((val & (CDBGPWRUPACK)) == 1); - + } while ((val & (CDBGPWRUPACK)) != 0); + swd_off(); break; From ba9078b7bdffb09914ff1fd6a3a021c8520b96bd Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 15 Oct 2021 20:03:47 -0500 Subject: [PATCH 319/617] Fix DAP_config.h file name case --- source/family/maxim/target_reset_max32xxx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/family/maxim/target_reset_max32xxx.c b/source/family/maxim/target_reset_max32xxx.c index 3123144c4..6124fbc9c 100644 --- a/source/family/maxim/target_reset_max32xxx.c +++ b/source/family/maxim/target_reset_max32xxx.c @@ -20,7 +20,7 @@ */ #include "target_family.h" #include "swd_host.h" -#include "DAP_Config.h" +#include "DAP_config.h" #include "target_board.h" #define DBG_Addr (0xe000edf0) // Default Core debug base addresses From d0cd67616d07a37ba7d9539754697bcf92b75c34 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sun, 10 Oct 2021 15:55:38 -0500 Subject: [PATCH 320/617] details.txt: change DAPLink URL to daplink.io. --- source/daplink/drag-n-drop/vfs_user.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/daplink/drag-n-drop/vfs_user.c b/source/daplink/drag-n-drop/vfs_user.c index ab37c0f81..b09ac5bd8 100644 --- a/source/daplink/drag-n-drop/vfs_user.c +++ b/source/daplink/drag-n-drop/vfs_user.c @@ -527,7 +527,7 @@ static uint32_t update_details_txt_file(uint8_t *buf, uint32_t size, uint32_t st uint32_t pos = 0; pos += util_write_string_in_region(buf, size, start, pos, - "# DAPLink Firmware - see https://mbed.com/daplink\r\n" + "# DAPLink Firmware - see https://daplink.io/\r\n" // Build ID "Build ID: " GIT_DESCRIPTION " (" COMPILER_DESCRIPTION LOCAL_MODS ")\r\n"); // Unique ID From 98b43101845182fdf7b82890ba89d3ea904a23ca Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 15 Oct 2021 22:28:09 -0500 Subject: [PATCH 321/617] daplink_target_url: change DAPLink URL to daplink.io + remove trailing '/' in DETAILS.TXT --- source/board/k20dx_bl.c | 2 +- source/board/k26f_bl.c | 2 +- source/board/kl26z_bl.c | 2 +- source/board/kl27z_bl.c | 2 +- source/board/lpc4322_bl.c | 2 +- source/board/lpc55s69_bl.c | 2 +- source/board/m48ssidae_bl.c | 2 +- source/board/max32620_bl.c | 2 +- source/board/max32625_bl.c | 2 +- source/board/sam3u2c_bl.c | 2 +- source/board/stm32f103xb_bl.c | 2 +- source/daplink/drag-n-drop/vfs_user.c | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-) diff --git a/source/board/k20dx_bl.c b/source/board/k20dx_bl.c index 9ce1754d1..e1be158b3 100644 --- a/source/board/k20dx_bl.c +++ b/source/board/k20dx_bl.c @@ -61,6 +61,6 @@ const board_info_t g_board_info = { .board_id = "0000", .daplink_url_name = "HELP_FAQHTM", .daplink_drive_name = "MAINTENANCE", - .daplink_target_url = "https://mbed.com/daplink", + .daplink_target_url = "https://daplink.io", .target_cfg = &target_device, }; diff --git a/source/board/k26f_bl.c b/source/board/k26f_bl.c index 76c788040..e54096814 100644 --- a/source/board/k26f_bl.c +++ b/source/board/k26f_bl.c @@ -60,6 +60,6 @@ const board_info_t g_board_info = { .board_id = "0000", .daplink_url_name = "HELP_FAQHTM", .daplink_drive_name = "BOOTLOADER", - .daplink_target_url = "https://mbed.com/daplink", + .daplink_target_url = "https://daplink.io", .target_cfg = &target_device, }; diff --git a/source/board/kl26z_bl.c b/source/board/kl26z_bl.c index 74b412fee..12b9f0b42 100644 --- a/source/board/kl26z_bl.c +++ b/source/board/kl26z_bl.c @@ -60,6 +60,6 @@ const board_info_t g_board_info = { .board_id = "0000", .daplink_url_name = "HELP_FAQHTM", .daplink_drive_name = "MAINTENANCE", - .daplink_target_url = "https://mbed.com/daplink", + .daplink_target_url = "https://daplink.io", .target_cfg = &target_device, }; diff --git a/source/board/kl27z_bl.c b/source/board/kl27z_bl.c index 7c8e2e154..882a1a81f 100644 --- a/source/board/kl27z_bl.c +++ b/source/board/kl27z_bl.c @@ -60,6 +60,6 @@ const board_info_t g_board_info = { .board_id = "0000", .daplink_url_name = "HELP_FAQHTM", .daplink_drive_name = "MAINTENANCE", - .daplink_target_url = "https://mbed.com/daplink", + .daplink_target_url = "https://daplink.io", .target_cfg = &target_device, }; diff --git a/source/board/lpc4322_bl.c b/source/board/lpc4322_bl.c index ff5edde57..3b196a0a8 100644 --- a/source/board/lpc4322_bl.c +++ b/source/board/lpc4322_bl.c @@ -61,6 +61,6 @@ const board_info_t g_board_info = { .board_id = "0000", .daplink_url_name = "HELP_FAQHTM", .daplink_drive_name = "MAINTENANCE", - .daplink_target_url = "https://mbed.com/daplink", + .daplink_target_url = "https://daplink.io", .target_cfg = &target_device, }; diff --git a/source/board/lpc55s69_bl.c b/source/board/lpc55s69_bl.c index 42998403d..e6704f408 100644 --- a/source/board/lpc55s69_bl.c +++ b/source/board/lpc55s69_bl.c @@ -72,7 +72,7 @@ const board_info_t g_board_info = { .board_id = "0000", .daplink_url_name = "HELP_FAQHTM", .daplink_drive_name = "BOOTLOADER", - .daplink_target_url = "https://mbed.com/daplink", + .daplink_target_url = "https://daplink.io", .target_cfg = &target_device, }; diff --git a/source/board/m48ssidae_bl.c b/source/board/m48ssidae_bl.c index 4a9815479..45003a59f 100644 --- a/source/board/m48ssidae_bl.c +++ b/source/board/m48ssidae_bl.c @@ -61,6 +61,6 @@ const board_info_t g_board_info = { .board_id = "0000", .daplink_url_name = "HELP_FAQHTM", .daplink_drive_name = "MAINTENANCE", - .daplink_target_url = "https://mbed.com/daplink", + .daplink_target_url = "https://daplink.io", .target_cfg = &target_device, }; diff --git a/source/board/max32620_bl.c b/source/board/max32620_bl.c index 33c2d7c4c..364326f62 100644 --- a/source/board/max32620_bl.c +++ b/source/board/max32620_bl.c @@ -55,6 +55,6 @@ const board_info_t g_board_info = { .board_id = "0000", .daplink_url_name = "HELP_FAQHTM", .daplink_drive_name = "MAINTENANCE", - .daplink_target_url = "https://mbed.com/daplink", + .daplink_target_url = "https://daplink.io", .target_cfg = &target_device, }; diff --git a/source/board/max32625_bl.c b/source/board/max32625_bl.c index 2aa6c5a5b..bda558504 100644 --- a/source/board/max32625_bl.c +++ b/source/board/max32625_bl.c @@ -57,6 +57,6 @@ const board_info_t g_board_info = { .board_id = "0000", .daplink_url_name = "HELP_FAQHTM", .daplink_drive_name = "MAINTENANCE", - .daplink_target_url = "https://mbed.com/daplink", + .daplink_target_url = "https://daplink.io", .target_cfg = &target_device, }; diff --git a/source/board/sam3u2c_bl.c b/source/board/sam3u2c_bl.c index fce82120e..4a11623ba 100644 --- a/source/board/sam3u2c_bl.c +++ b/source/board/sam3u2c_bl.c @@ -61,6 +61,6 @@ const board_info_t g_board_info = { .board_id = "0000", .daplink_url_name = "HELP_FAQHTM", .daplink_drive_name = "MAINTENANCE", - .daplink_target_url = "https://mbed.com/daplink", + .daplink_target_url = "https://daplink.io", .target_cfg = &target_device, }; diff --git a/source/board/stm32f103xb_bl.c b/source/board/stm32f103xb_bl.c index 26a56d3ca..aca75e0b5 100644 --- a/source/board/stm32f103xb_bl.c +++ b/source/board/stm32f103xb_bl.c @@ -55,6 +55,6 @@ const board_info_t g_board_info = { .board_id = "0000", .daplink_url_name = "HELP_FAQHTM", .daplink_drive_name = "MAINTENANCE", - .daplink_target_url = "https://mbed.com/daplink", + .daplink_target_url = "https://daplink.io", .target_cfg = &target_device, }; diff --git a/source/daplink/drag-n-drop/vfs_user.c b/source/daplink/drag-n-drop/vfs_user.c index b09ac5bd8..881ec6d34 100644 --- a/source/daplink/drag-n-drop/vfs_user.c +++ b/source/daplink/drag-n-drop/vfs_user.c @@ -527,7 +527,7 @@ static uint32_t update_details_txt_file(uint8_t *buf, uint32_t size, uint32_t st uint32_t pos = 0; pos += util_write_string_in_region(buf, size, start, pos, - "# DAPLink Firmware - see https://daplink.io/\r\n" + "# DAPLink Firmware - see https://daplink.io\r\n" // Build ID "Build ID: " GIT_DESCRIPTION " (" COMPILER_DESCRIPTION LOCAL_MODS ")\r\n"); // Unique ID From bb18a2241920e3a4b5f45ba190521471af31530e Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Thu, 23 Sep 2021 16:40:47 -0500 Subject: [PATCH 322/617] CMSIS-Drivers: move headers to source/hic_hal/cmsis-driver. --- records/daplink/bootloader.yaml | 1 + records/daplink/interface.yaml | 1 + .../k26f => cmsis-driver}/Driver_Common.h | 0 .../k26f => cmsis-driver}/Driver_USART.h | 0 source/hic_hal/nxp/lpc55xx/Driver_Common.h | 69 ---- source/hic_hal/nxp/lpc55xx/Driver_USART.h | 341 ------------------ 6 files changed, 2 insertions(+), 410 deletions(-) rename source/hic_hal/{freescale/k26f => cmsis-driver}/Driver_Common.h (100%) rename source/hic_hal/{freescale/k26f => cmsis-driver}/Driver_USART.h (100%) delete mode 100644 source/hic_hal/nxp/lpc55xx/Driver_Common.h delete mode 100644 source/hic_hal/nxp/lpc55xx/Driver_USART.h diff --git a/records/daplink/bootloader.yaml b/records/daplink/bootloader.yaml index 11e1d7644..2ff6ba126 100644 --- a/records/daplink/bootloader.yaml +++ b/records/daplink/bootloader.yaml @@ -7,6 +7,7 @@ common: - source/daplink/bootloader - source/cmsis-core - source/hic_hal + - source/hic_hal/cmsis-driver sources: daplink_bl: - source/daplink diff --git a/records/daplink/interface.yaml b/records/daplink/interface.yaml index 583a2ff4e..d329b6550 100644 --- a/records/daplink/interface.yaml +++ b/records/daplink/interface.yaml @@ -7,6 +7,7 @@ common: - source/daplink/interface - source/cmsis-core - source/hic_hal + - source/hic_hal/cmsis-driver sources: daplink_if: - source/daplink diff --git a/source/hic_hal/freescale/k26f/Driver_Common.h b/source/hic_hal/cmsis-driver/Driver_Common.h similarity index 100% rename from source/hic_hal/freescale/k26f/Driver_Common.h rename to source/hic_hal/cmsis-driver/Driver_Common.h diff --git a/source/hic_hal/freescale/k26f/Driver_USART.h b/source/hic_hal/cmsis-driver/Driver_USART.h similarity index 100% rename from source/hic_hal/freescale/k26f/Driver_USART.h rename to source/hic_hal/cmsis-driver/Driver_USART.h diff --git a/source/hic_hal/nxp/lpc55xx/Driver_Common.h b/source/hic_hal/nxp/lpc55xx/Driver_Common.h deleted file mode 100644 index 59d5b759c..000000000 --- a/source/hic_hal/nxp/lpc55xx/Driver_Common.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 2. Feb 2017 - * $Revision: V2.0 - * - * Project: Common Driver definitions - */ - -/* History: - * Version 2.0 - * Changed prefix ARM_DRV -> ARM_DRIVER - * Added General return codes definitions - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.00 - * Initial release - */ - -#ifndef DRIVER_COMMON_H_ -#define DRIVER_COMMON_H_ - -#include -#include -#include - -#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor)) - -/** -\brief Driver Version -*/ -typedef struct _ARM_DRIVER_VERSION { - uint16_t api; ///< API version - uint16_t drv; ///< Driver version -} ARM_DRIVER_VERSION; - -/* General return codes */ -#define ARM_DRIVER_OK 0 ///< Operation succeeded -#define ARM_DRIVER_ERROR -1 ///< Unspecified error -#define ARM_DRIVER_ERROR_BUSY -2 ///< Driver is busy -#define ARM_DRIVER_ERROR_TIMEOUT -3 ///< Timeout occurred -#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported -#define ARM_DRIVER_ERROR_PARAMETER -5 ///< Parameter error -#define ARM_DRIVER_ERROR_SPECIFIC -6 ///< Start of driver specific errors - -/** -\brief General power states -*/ -typedef enum _ARM_POWER_STATE { - ARM_POWER_OFF, ///< Power off: no operation possible - ARM_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events - ARM_POWER_FULL ///< Power on: full operation at maximum performance -} ARM_POWER_STATE; - -#endif /* DRIVER_COMMON_H_ */ diff --git a/source/hic_hal/nxp/lpc55xx/Driver_USART.h b/source/hic_hal/nxp/lpc55xx/Driver_USART.h deleted file mode 100644 index e60bf51a3..000000000 --- a/source/hic_hal/nxp/lpc55xx/Driver_USART.h +++ /dev/null @@ -1,341 +0,0 @@ -/* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 2. Feb 2017 - * $Revision: V2.3 - * - * Project: USART (Universal Synchronous Asynchronous Receiver Transmitter) - * Driver definitions - */ - -/* History: - * Version 2.3 - * ARM_USART_STATUS and ARM_USART_MODEM_STATUS made volatile - * Version 2.2 - * Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions - * Version 2.1 - * Removed optional argument parameter from Signal Event - * Version 2.0 - * New simplified driver: - * complexity moved to upper layer (especially data handling) - * more unified API for different communication interfaces - * renamed driver UART -> USART (Asynchronous & Synchronous) - * Added modes: - * Synchronous - * Single-wire - * IrDA - * Smart Card - * Changed prefix ARM_DRV -> ARM_DRIVER - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.01 - * Added events: - * ARM_UART_EVENT_TX_EMPTY, ARM_UART_EVENT_RX_TIMEOUT - * ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD - * Added functions: SetTxThreshold, SetRxThreshold - * Added "rx_timeout_event" to capabilities - * Version 1.00 - * Initial release - */ - -#ifndef DRIVER_USART_H_ -#define DRIVER_USART_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "Driver_Common.h" - -#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */ - - -/****** USART Control Codes *****/ - -#define ARM_USART_CONTROL_Pos 0 -#define ARM_USART_CONTROL_Msk (0xFFUL << ARM_USART_CONTROL_Pos) - -/*----- USART Control Codes: Mode -----*/ -#define ARM_USART_MODE_ASYNCHRONOUS (0x01UL << ARM_USART_CONTROL_Pos) ///< UART (Asynchronous); arg = Baudrate -#define ARM_USART_MODE_SYNCHRONOUS_MASTER (0x02UL << ARM_USART_CONTROL_Pos) ///< Synchronous Master (generates clock signal); arg = Baudrate -#define ARM_USART_MODE_SYNCHRONOUS_SLAVE (0x03UL << ARM_USART_CONTROL_Pos) ///< Synchronous Slave (external clock signal) -#define ARM_USART_MODE_SINGLE_WIRE (0x04UL << ARM_USART_CONTROL_Pos) ///< UART Single-wire (half-duplex); arg = Baudrate -#define ARM_USART_MODE_IRDA (0x05UL << ARM_USART_CONTROL_Pos) ///< UART IrDA; arg = Baudrate -#define ARM_USART_MODE_SMART_CARD (0x06UL << ARM_USART_CONTROL_Pos) ///< UART Smart Card; arg = Baudrate - -/*----- USART Control Codes: Mode Parameters: Data Bits -----*/ -#define ARM_USART_DATA_BITS_Pos 8 -#define ARM_USART_DATA_BITS_Msk (7UL << ARM_USART_DATA_BITS_Pos) -#define ARM_USART_DATA_BITS_5 (5UL << ARM_USART_DATA_BITS_Pos) ///< 5 Data bits -#define ARM_USART_DATA_BITS_6 (6UL << ARM_USART_DATA_BITS_Pos) ///< 6 Data bit -#define ARM_USART_DATA_BITS_7 (7UL << ARM_USART_DATA_BITS_Pos) ///< 7 Data bits -#define ARM_USART_DATA_BITS_8 (0UL << ARM_USART_DATA_BITS_Pos) ///< 8 Data bits (default) -#define ARM_USART_DATA_BITS_9 (1UL << ARM_USART_DATA_BITS_Pos) ///< 9 Data bits - -/*----- USART Control Codes: Mode Parameters: Parity -----*/ -#define ARM_USART_PARITY_Pos 12 -#define ARM_USART_PARITY_Msk (3UL << ARM_USART_PARITY_Pos) -#define ARM_USART_PARITY_NONE (0UL << ARM_USART_PARITY_Pos) ///< No Parity (default) -#define ARM_USART_PARITY_EVEN (1UL << ARM_USART_PARITY_Pos) ///< Even Parity -#define ARM_USART_PARITY_ODD (2UL << ARM_USART_PARITY_Pos) ///< Odd Parity - -/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/ -#define ARM_USART_STOP_BITS_Pos 14 -#define ARM_USART_STOP_BITS_Msk (3UL << ARM_USART_STOP_BITS_Pos) -#define ARM_USART_STOP_BITS_1 (0UL << ARM_USART_STOP_BITS_Pos) ///< 1 Stop bit (default) -#define ARM_USART_STOP_BITS_2 (1UL << ARM_USART_STOP_BITS_Pos) ///< 2 Stop bits -#define ARM_USART_STOP_BITS_1_5 (2UL << ARM_USART_STOP_BITS_Pos) ///< 1.5 Stop bits -#define ARM_USART_STOP_BITS_0_5 (3UL << ARM_USART_STOP_BITS_Pos) ///< 0.5 Stop bits - -/*----- USART Control Codes: Mode Parameters: Flow Control -----*/ -#define ARM_USART_FLOW_CONTROL_Pos 16 -#define ARM_USART_FLOW_CONTROL_Msk (3UL << ARM_USART_FLOW_CONTROL_Pos) -#define ARM_USART_FLOW_CONTROL_NONE (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default) -#define ARM_USART_FLOW_CONTROL_RTS (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control -#define ARM_USART_FLOW_CONTROL_CTS (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control -#define ARM_USART_FLOW_CONTROL_RTS_CTS (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control - -/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/ -#define ARM_USART_CPOL_Pos 18 -#define ARM_USART_CPOL_Msk (1UL << ARM_USART_CPOL_Pos) -#define ARM_USART_CPOL0 (0UL << ARM_USART_CPOL_Pos) ///< CPOL = 0 (default) -#define ARM_USART_CPOL1 (1UL << ARM_USART_CPOL_Pos) ///< CPOL = 1 - -/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/ -#define ARM_USART_CPHA_Pos 19 -#define ARM_USART_CPHA_Msk (1UL << ARM_USART_CPHA_Pos) -#define ARM_USART_CPHA0 (0UL << ARM_USART_CPHA_Pos) ///< CPHA = 0 (default) -#define ARM_USART_CPHA1 (1UL << ARM_USART_CPHA_Pos) ///< CPHA = 1 - - -/*----- USART Control Codes: Miscellaneous Controls -----*/ -#define ARM_USART_SET_DEFAULT_TX_VALUE (0x10UL << ARM_USART_CONTROL_Pos) ///< Set default Transmit value (Synchronous Receive only); arg = value -#define ARM_USART_SET_IRDA_PULSE (0x11UL << ARM_USART_CONTROL_Pos) ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period -#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Guard Time; arg = number of bit periods -#define ARM_USART_SET_SMART_CARD_CLOCK (0x13UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated -#define ARM_USART_CONTROL_SMART_CARD_NACK (0x14UL << ARM_USART_CONTROL_Pos) ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled -#define ARM_USART_CONTROL_TX (0x15UL << ARM_USART_CONTROL_Pos) ///< Transmitter; arg: 0=disabled, 1=enabled -#define ARM_USART_CONTROL_RX (0x16UL << ARM_USART_CONTROL_Pos) ///< Receiver; arg: 0=disabled, 1=enabled -#define ARM_USART_CONTROL_BREAK (0x17UL << ARM_USART_CONTROL_Pos) ///< Continuous Break transmission; arg: 0=disabled, 1=enabled -#define ARM_USART_ABORT_SEND (0x18UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Send -#define ARM_USART_ABORT_RECEIVE (0x19UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Receive -#define ARM_USART_ABORT_TRANSFER (0x1AUL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Transfer - - - -/****** USART specific error codes *****/ -#define ARM_USART_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported -#define ARM_USART_ERROR_BAUDRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified baudrate not supported -#define ARM_USART_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported -#define ARM_USART_ERROR_PARITY (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Parity not supported -#define ARM_USART_ERROR_STOP_BITS (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified number of Stop bits not supported -#define ARM_USART_ERROR_FLOW_CONTROL (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Flow Control not supported -#define ARM_USART_ERROR_CPOL (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock Polarity not supported -#define ARM_USART_ERROR_CPHA (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Clock Phase not supported - - -/** -\brief USART Status -*/ -typedef volatile struct _ARM_USART_STATUS { - uint32_t tx_busy : 1; ///< Transmitter busy flag - uint32_t rx_busy : 1; ///< Receiver busy flag - uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation) - uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation) - uint32_t rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation) - uint32_t rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation) - uint32_t rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation) - uint32_t reserved : 25; -} ARM_USART_STATUS; - -/** -\brief USART Modem Control -*/ -typedef enum _ARM_USART_MODEM_CONTROL { - ARM_USART_RTS_CLEAR, ///< Deactivate RTS - ARM_USART_RTS_SET, ///< Activate RTS - ARM_USART_DTR_CLEAR, ///< Deactivate DTR - ARM_USART_DTR_SET ///< Activate DTR -} ARM_USART_MODEM_CONTROL; - -/** -\brief USART Modem Status -*/ -typedef volatile struct _ARM_USART_MODEM_STATUS { - uint32_t cts : 1; ///< CTS state: 1=Active, 0=Inactive - uint32_t dsr : 1; ///< DSR state: 1=Active, 0=Inactive - uint32_t dcd : 1; ///< DCD state: 1=Active, 0=Inactive - uint32_t ri : 1; ///< RI state: 1=Active, 0=Inactive - uint32_t reserved : 28; -} ARM_USART_MODEM_STATUS; - - -/****** USART Event *****/ -#define ARM_USART_EVENT_SEND_COMPLETE (1UL << 0) ///< Send completed; however USART may still transmit data -#define ARM_USART_EVENT_RECEIVE_COMPLETE (1UL << 1) ///< Receive completed -#define ARM_USART_EVENT_TRANSFER_COMPLETE (1UL << 2) ///< Transfer completed -#define ARM_USART_EVENT_TX_COMPLETE (1UL << 3) ///< Transmit completed (optional) -#define ARM_USART_EVENT_TX_UNDERFLOW (1UL << 4) ///< Transmit data not available (Synchronous Slave) -#define ARM_USART_EVENT_RX_OVERFLOW (1UL << 5) ///< Receive data overflow -#define ARM_USART_EVENT_RX_TIMEOUT (1UL << 6) ///< Receive character timeout (optional) -#define ARM_USART_EVENT_RX_BREAK (1UL << 7) ///< Break detected on receive -#define ARM_USART_EVENT_RX_FRAMING_ERROR (1UL << 8) ///< Framing error detected on receive -#define ARM_USART_EVENT_RX_PARITY_ERROR (1UL << 9) ///< Parity error detected on receive -#define ARM_USART_EVENT_CTS (1UL << 10) ///< CTS state changed (optional) -#define ARM_USART_EVENT_DSR (1UL << 11) ///< DSR state changed (optional) -#define ARM_USART_EVENT_DCD (1UL << 12) ///< DCD state changed (optional) -#define ARM_USART_EVENT_RI (1UL << 13) ///< RI state changed (optional) - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_USART_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION - - \fn ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void) - \brief Get driver capabilities - \return \ref ARM_USART_CAPABILITIES - - \fn int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event) - \brief Initialize USART Interface. - \param[in] cb_event Pointer to \ref ARM_USART_SignalEvent - \return \ref execution_status - - \fn int32_t ARM_USART_Uninitialize (void) - \brief De-initialize USART Interface. - \return \ref execution_status - - \fn int32_t ARM_USART_PowerControl (ARM_POWER_STATE state) - \brief Control USART Interface Power. - \param[in] state Power state - \return \ref execution_status - - \fn int32_t ARM_USART_Send (const void *data, uint32_t num) - \brief Start sending data to USART transmitter. - \param[in] data Pointer to buffer with data to send to USART transmitter - \param[in] num Number of data items to send - \return \ref execution_status - - \fn int32_t ARM_USART_Receive (void *data, uint32_t num) - \brief Start receiving data from USART receiver. - \param[out] data Pointer to buffer for data to receive from USART receiver - \param[in] num Number of data items to receive - \return \ref execution_status - - \fn int32_t ARM_USART_Transfer (const void *data_out, - void *data_in, - uint32_t num) - \brief Start sending/receiving data to/from USART transmitter/receiver. - \param[in] data_out Pointer to buffer with data to send to USART transmitter - \param[out] data_in Pointer to buffer for data to receive from USART receiver - \param[in] num Number of data items to transfer - \return \ref execution_status - - \fn uint32_t ARM_USART_GetTxCount (void) - \brief Get transmitted data count. - \return number of data items transmitted - - \fn uint32_t ARM_USART_GetRxCount (void) - \brief Get received data count. - \return number of data items received - - \fn int32_t ARM_USART_Control (uint32_t control, uint32_t arg) - \brief Control USART Interface. - \param[in] control Operation - \param[in] arg Argument of operation (optional) - \return common \ref execution_status and driver specific \ref usart_execution_status - - \fn ARM_USART_STATUS ARM_USART_GetStatus (void) - \brief Get USART status. - \return USART status \ref ARM_USART_STATUS - - \fn int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control) - \brief Set USART Modem Control line state. - \param[in] control \ref ARM_USART_MODEM_CONTROL - \return \ref execution_status - - \fn ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void) - \brief Get USART Modem Status lines state. - \return modem status \ref ARM_USART_MODEM_STATUS - - \fn void ARM_USART_SignalEvent (uint32_t event) - \brief Signal USART Events. - \param[in] event \ref USART_events notification mask - \return none -*/ - -typedef void (*ARM_USART_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event. - - -/** -\brief USART Device Driver Capabilities. -*/ -typedef struct _ARM_USART_CAPABILITIES { - uint32_t asynchronous : 1; ///< supports UART (Asynchronous) mode - uint32_t synchronous_master : 1; ///< supports Synchronous Master mode - uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode - uint32_t single_wire : 1; ///< supports UART Single-wire mode - uint32_t irda : 1; ///< supports UART IrDA mode - uint32_t smart_card : 1; ///< supports UART Smart Card mode - uint32_t smart_card_clock : 1; ///< Smart Card Clock generator available - uint32_t flow_control_rts : 1; ///< RTS Flow Control available - uint32_t flow_control_cts : 1; ///< CTS Flow Control available - uint32_t event_tx_complete : 1; ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE - uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT - uint32_t rts : 1; ///< RTS Line: 0=not available, 1=available - uint32_t cts : 1; ///< CTS Line: 0=not available, 1=available - uint32_t dtr : 1; ///< DTR Line: 0=not available, 1=available - uint32_t dsr : 1; ///< DSR Line: 0=not available, 1=available - uint32_t dcd : 1; ///< DCD Line: 0=not available, 1=available - uint32_t ri : 1; ///< RI Line: 0=not available, 1=available - uint32_t event_cts : 1; ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS - uint32_t event_dsr : 1; ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR - uint32_t event_dcd : 1; ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD - uint32_t event_ri : 1; ///< Signal RI change event: \ref ARM_USART_EVENT_RI - uint32_t reserved : 11; ///< Reserved (must be zero) -} ARM_USART_CAPABILITIES; - - -/** -\brief Access structure of the USART Driver. -*/ -typedef struct _ARM_DRIVER_USART { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USART_GetVersion : Get driver version. - ARM_USART_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_USART_SignalEvent_t cb_event); ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power. - int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter. - int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver. - int32_t (*Transfer) (const void *data_out, - void *data_in, - uint32_t num); ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART. - uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count. - uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count. - int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_USART_Control : Control USART Interface. - ARM_USART_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_USART_GetStatus : Get USART status. - int32_t (*SetModemControl) (ARM_USART_MODEM_CONTROL control); ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state. - ARM_USART_MODEM_STATUS (*GetModemStatus) (void); ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state. -} const ARM_DRIVER_USART; - -#ifdef __cplusplus -} -#endif - -#endif /* DRIVER_USART_H_ */ From 097de1768215a2c0901da1829f55197c75ca1cfb Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sun, 27 Jun 2021 13:22:39 -0500 Subject: [PATCH 323/617] DAP: update to v2.1 reference code. - Merge in v2.1 changes. - Update DAP_config.h for all HICs. --- source/daplink/cmsis-dap/DAP.c | 69 +- source/daplink/cmsis-dap/DAP.h | 78 ++- source/daplink/cmsis-dap/DAP_UART.c | 652 ++++++++++++++++++ source/daplink/cmsis-dap/SWO.c | 94 ++- source/daplink/cmsis-dap/dap_strings.h | 92 ++- source/hic_hal/atmel/sam3u2c/DAP_config.h | 71 +- source/hic_hal/device.h | 2 +- source/hic_hal/freescale/k20dx/DAP_config.h | 44 +- source/hic_hal/freescale/k26f/DAP_config.h | 75 +- source/hic_hal/freescale/kl26z/DAP_config.h | 68 +- source/hic_hal/freescale/kl27z/DAP_config.h | 69 +- source/hic_hal/maxim/max32620/DAP_config.h | 84 ++- source/hic_hal/maxim/max32625/DAP_config.h | 59 +- source/hic_hal/nuvoton/m48ssidae/DAP_config.h | 72 +- source/hic_hal/nxp/lpc11u35/DAP_config.h | 73 +- source/hic_hal/nxp/lpc4322/DAP_config.h | 108 ++- source/hic_hal/nxp/lpc4322/IO_Config.h | 40 +- source/hic_hal/nxp/lpc4322/gpio.c | 3 +- source/hic_hal/nxp/lpc55xx/DAP_config.h | 56 +- source/hic_hal/stm32/stm32f103xb/DAP_config.h | 69 +- 20 files changed, 1490 insertions(+), 388 deletions(-) create mode 100644 source/daplink/cmsis-dap/DAP_UART.c diff --git a/source/daplink/cmsis-dap/DAP.c b/source/daplink/cmsis-dap/DAP.c index c2da841a2..0710f5478 100644 --- a/source/daplink/cmsis-dap/DAP.c +++ b/source/daplink/cmsis-dap/DAP.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020 ARM Limited. All rights reserved. + * Copyright (c) 2013-2021 ARM Limited. All rights reserved. * Copyright 2019, Cypress Semiconductor Corporation * or a subsidiary of Cypress Semiconductor Corporation. * @@ -63,10 +63,6 @@ volatile uint8_t DAP_TransferAbort; // Transfer Abort Flag static const char DAP_FW_Ver [] = DAP_FW_VER; -#if TARGET_DEVICE_FIXED -static const char TargetDeviceVendor [] = TARGET_DEVICE_VENDOR; -static const char TargetDeviceName [] = TARGET_DEVICE_NAME; -#endif // Get DAP Information @@ -86,24 +82,24 @@ static uint8_t DAP_Info(uint8_t id, uint8_t *info) { case DAP_ID_SER_NUM: length = DAP_GetSerNumString((char *)info); break; - case DAP_ID_CMSIS_DAP_VER: + case DAP_ID_DAP_FW_VER: length = (uint8_t)sizeof(DAP_FW_Ver); memcpy(info, DAP_FW_Ver, length); break; case DAP_ID_DEVICE_VENDOR: -#if TARGET_DEVICE_FIXED - length = (uint8_t)sizeof(TargetDeviceVendor); - memcpy(info, TargetDeviceVendor, length); -#endif + length = DAP_GetTargetDeviceVendorString((char *)info); break; case DAP_ID_DEVICE_NAME: -#if TARGET_DEVICE_FIXED - length = (uint8_t)sizeof(TargetDeviceName); - memcpy(info, TargetDeviceName, length); -#endif + length = DAP_GetTargetDeviceNameString((char *)info); + break; + case DAP_ID_BOARD_VENDOR: + length = DAP_GetTargetBoardVendorString((char *)info); + break; + case DAP_ID_BOARD_NAME: + length = DAP_GetTargetBoardNameString((char *)info); break; case DAP_ID_PRODUCT_FW_VER: - length = DAP_ProductFirmwareVerString((char *)info); + length = DAP_GetProductFirmwareVersionString((char *)info); break; case DAP_ID_CAPABILITIES: info[0] = ((DAP_SWD != 0) ? (1U << 0) : 0U) | @@ -112,8 +108,11 @@ static uint8_t DAP_Info(uint8_t id, uint8_t *info) { ((SWO_MANCHESTER != 0) ? (1U << 3) : 0U) | /* Atomic Commands */ (1U << 4) | ((TIMESTAMP_CLOCK != 0U) ? (1U << 5) : 0U) | - ((SWO_STREAM != 0U) ? (1U << 6) : 0U); - length = 1U; + ((SWO_STREAM != 0U) ? (1U << 6) : 0U) | + ((DAP_UART != 0U) ? (1U << 7) : 0U); + + info[1] = ((DAP_UART_USB_COM_PORT != 0) ? (1U << 0) : 0U); + length = 2U; break; case DAP_ID_TIMESTAMP_CLOCK: #if (TIMESTAMP_CLOCK != 0U) @@ -122,6 +121,24 @@ static uint8_t DAP_Info(uint8_t id, uint8_t *info) { info[2] = (uint8_t)(TIMESTAMP_CLOCK >> 16); info[3] = (uint8_t)(TIMESTAMP_CLOCK >> 24); length = 4U; +#endif + break; + case DAP_ID_UART_RX_BUFFER_SIZE: +#if (DAP_UART != 0) + info[0] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 0); + info[1] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 8); + info[2] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 16); + info[3] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 24); + length = 4U; +#endif + break; + case DAP_ID_UART_TX_BUFFER_SIZE: +#if (DAP_UART != 0) + info[0] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 0); + info[1] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 8); + info[2] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 16); + info[3] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 24); + length = 4U; #endif break; case DAP_ID_SWO_BUFFER_SIZE: @@ -1744,6 +1761,24 @@ uint32_t DAP_ProcessCommand(const uint8_t *request, uint8_t *response) { break; #endif +#if (DAP_UART != 0) + case ID_DAP_UART_Transport: + num = UART_Transport(request, response); + break; + case ID_DAP_UART_Configure: + num = UART_Configure(request, response); + break; + case ID_DAP_UART_Control: + num = UART_Control(request, response); + break; + case ID_DAP_UART_Status: + num = UART_Status(response); + break; + case ID_DAP_UART_Transfer: + num = UART_Transfer(request, response); + break; +#endif + default: *(response-1) = ID_DAP_Invalid; return ((1U << 16) | 1U); diff --git a/source/daplink/cmsis-dap/DAP.h b/source/daplink/cmsis-dap/DAP.h index 02a38ca3d..02286dee5 100644 --- a/source/daplink/cmsis-dap/DAP.h +++ b/source/daplink/cmsis-dap/DAP.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020 ARM Limited. All rights reserved. + * Copyright (c) 2013-2021 ARM Limited. All rights reserved. * Copyright 2019, Cypress Semiconductor Corporation * or a subsidiary of Cypress Semiconductor Corporation. * @@ -19,8 +19,8 @@ * * ---------------------------------------------------------------------- * - * $Date: 26. November 2019 - * $Revision: V2.0.0 + * $Date: 26. May 2021 + * $Revision: V2.1.0 * * Project: CMSIS-DAP Include * Title: DAP.h Definitions @@ -33,9 +33,9 @@ // DAP Firmware Version #ifdef DAP_FW_V1 -#define DAP_FW_VER "1.2.0" +#define DAP_FW_VER "1.3.0" #else -#define DAP_FW_VER "2.0.0" +#define DAP_FW_VER "2.1.0" #endif // DAP Command IDs @@ -65,6 +65,11 @@ #define ID_DAP_SWO_Status 0x1BU #define ID_DAP_SWO_ExtendedStatus 0x1EU #define ID_DAP_SWO_Data 0x1CU +#define ID_DAP_UART_Transport 0x1FU +#define ID_DAP_UART_Configure 0x20U +#define ID_DAP_UART_Control 0x22U +#define ID_DAP_UART_Status 0x23U +#define ID_DAP_UART_Transfer 0x21U #define ID_DAP_QueueCommands 0x7EU #define ID_DAP_ExecuteCommands 0x7FU @@ -118,13 +123,16 @@ #define DAP_ID_VENDOR 1U #define DAP_ID_PRODUCT 2U #define DAP_ID_SER_NUM 3U -#define DAP_ID_CMSIS_DAP_VER 4U -#define DAP_ID_FW_VER 4U // Deprecated alias of DAP_ID_CMSIS_DAP_VER for backwards compatibility. +#define DAP_ID_DAP_FW_VER 4U #define DAP_ID_DEVICE_VENDOR 5U #define DAP_ID_DEVICE_NAME 6U -#define DAP_ID_PRODUCT_FW_VER 7U +#define DAP_ID_BOARD_VENDOR 7U +#define DAP_ID_BOARD_NAME 8U +#define DAP_ID_PRODUCT_FW_VER 9U #define DAP_ID_CAPABILITIES 0xF0U #define DAP_ID_TIMESTAMP_CLOCK 0xF1U +#define DAP_ID_UART_RX_BUFFER_SIZE 0xFBU +#define DAP_ID_UART_TX_BUFFER_SIZE 0xFCU #define DAP_ID_SWO_BUFFER_SIZE 0xFDU #define DAP_ID_PACKET_COUNT 0xFEU #define DAP_ID_PACKET_SIZE 0xFFU @@ -174,6 +182,30 @@ #define DAP_SWO_STREAM_ERROR (1U<<6) #define DAP_SWO_BUFFER_OVERRUN (1U<<7) +// DAP UART Transport +#define DAP_UART_TRANSPORT_NONE 0U +#define DAP_UART_TRANSPORT_USB_COM_PORT 1U +#define DAP_UART_TRANSPORT_DAP_COMMAND 2U + +// DAP UART Control +#define DAP_UART_CONTROL_RX_ENABLE (1U<<0) +#define DAP_UART_CONTROL_RX_DISABLE (1U<<1) +#define DAP_UART_CONTROL_RX_BUF_FLUSH (1U<<2) +#define DAP_UART_CONTROL_TX_ENABLE (1U<<4) +#define DAP_UART_CONTROL_TX_DISABLE (1U<<5) +#define DAP_UART_CONTROL_TX_BUF_FLUSH (1U<<6) + +// DAP UART Status +#define DAP_UART_STATUS_RX_ENABLED (1U<<0) +#define DAP_UART_STATUS_RX_DATA_LOST (1U<<1) +#define DAP_UART_STATUS_FRAMING_ERROR (1U<<2) +#define DAP_UART_STATUS_PARITY_ERROR (1U<<3) +#define DAP_UART_STATUS_TX_ENABLED (1U<<4) + +// DAP UART Configure Error +#define DAP_UART_CFG_ERROR_DATA_BITS (1U<<0) +#define DAP_UART_CFG_ERROR_PARITY (1U<<1) +#define DAP_UART_CFG_ERROR_STOP_BITS (1U<<2) // Debug Port Register Addresses #define DP_IDCODE 0x00U // IDCODE Register (SW Read only) @@ -272,17 +304,25 @@ extern void SWO_QueueTransfer (uint8_t *buf, uint32_t num); extern void SWO_AbortTransfer (void); extern void SWO_TransferComplete (void); -extern uint32_t UART_SWO_Mode (uint32_t enable); -extern uint32_t UART_SWO_Baudrate (uint32_t baudrate); -extern uint32_t UART_SWO_Control (uint32_t active); -extern void UART_SWO_Capture (uint8_t *buf, uint32_t num); -extern uint32_t UART_SWO_GetCount (void); - -extern uint32_t Manchester_SWO_Mode (uint32_t enable); -extern uint32_t Manchester_SWO_Baudrate (uint32_t baudrate); -extern uint32_t Manchester_SWO_Control (uint32_t active); -extern void Manchester_SWO_Capture (uint8_t *buf, uint32_t num); -extern uint32_t Manchester_SWO_GetCount (void); +extern uint32_t SWO_Mode_UART (uint32_t enable); +extern uint32_t SWO_Baudrate_UART (uint32_t baudrate); +extern uint32_t SWO_Control_UART (uint32_t active); +extern void SWO_Capture_UART (uint8_t *buf, uint32_t num); +extern uint32_t SWO_GetCount_UART (void); + +extern uint32_t SWO_Mode_Manchester (uint32_t enable); +extern uint32_t SWO_Baudrate_Manchester (uint32_t baudrate); +extern uint32_t SWO_Control_Manchester (uint32_t active); +extern void SWO_Capture_Manchester (uint8_t *buf, uint32_t num); +extern uint32_t SWO_GetCount_Manchester (void); + +extern uint32_t UART_Transport (const uint8_t *request, uint8_t *response); +extern uint32_t UART_Configure (const uint8_t *request, uint8_t *response); +extern uint32_t UART_Control (const uint8_t *request, uint8_t *response); +extern uint32_t UART_Status (uint8_t *response); +extern uint32_t UART_Transfer (const uint8_t *request, uint8_t *response); + +extern uint8_t USB_COM_PORT_Activate (uint32_t cmd); extern uint32_t DAP_ProcessVendorCommand (const uint8_t *request, uint8_t *response); extern uint32_t DAP_ProcessCommand (const uint8_t *request, uint8_t *response); diff --git a/source/daplink/cmsis-dap/DAP_UART.c b/source/daplink/cmsis-dap/DAP_UART.c new file mode 100644 index 000000000..a29c84742 --- /dev/null +++ b/source/daplink/cmsis-dap/DAP_UART.c @@ -0,0 +1,652 @@ +/* + * Copyright (c) 2021 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 1. March 2021 + * $Revision: V1.0.0 + * + * Project: CMSIS-DAP Source + * Title: UART.c CMSIS-DAP UART + * + *---------------------------------------------------------------------------*/ + +#include "DAP_config.h" +#include "DAP.h" + +#if (DAP_UART != 0) + +#ifdef DAP_FW_V1 +#error "UART Communication Port not supported in DAP V1!" +#endif + +#include "Driver_USART.h" + +#include "cmsis_os2.h" +#include + +#define UART_RX_BLOCK_SIZE 32U /* Uart Rx Block Size (must be 2^n) */ + +// USART Driver +#define _USART_Driver_(n) Driver_USART##n +#define USART_Driver_(n) _USART_Driver_(n) +extern ARM_DRIVER_USART USART_Driver_(DAP_UART_DRIVER); +#define pUSART (&USART_Driver_(DAP_UART_DRIVER)) + +// UART Configuration +#if (DAP_UART_USB_COM_PORT != 0) +static uint8_t UartTransport = DAP_UART_TRANSPORT_USB_COM_PORT; +#else +static uint8_t UartTransport = DAP_UART_TRANSPORT_NONE; +#endif + +// UART Flags +static uint8_t UartConfigured = 0U; +static uint8_t UartReceiveEnabled = 0U; +static uint8_t UartTransmitEnabled = 0U; +static uint8_t UartTransmitActive = 0U; + +// UART TX Buffer +static uint8_t UartTxBuf[DAP_UART_TX_BUFFER_SIZE]; +static volatile uint32_t UartTxIndexI = 0U; +static volatile uint32_t UartTxIndexO = 0U; + +// UART RX Buffer +static uint8_t UartRxBuf[DAP_UART_RX_BUFFER_SIZE]; +static volatile uint32_t UartRxIndexI = 0U; +static volatile uint32_t UartRxIndexO = 0U; + +// Uart Errors +static volatile uint8_t UartErrorRxDataLost = 0U; +static volatile uint8_t UartErrorFraming = 0U; +static volatile uint8_t UartErrorParity = 0U; + +// UART Transmit +static uint32_t UartTxNum = 0U; + +// Function prototypes +static uint8_t UART_Init (void); +static void UART_Uninit (void); +static uint8_t UART_Get_Status (void); +static uint8_t UART_Receive_Enable (void); +static uint8_t UART_Transmit_Enable (void); +static void UART_Receive_Disable (void); +static void UART_Transmit_Disable (void); +static void UART_Receive_Flush (void); +static void UART_Transmit_Flush (void); +static void UART_Receive (void); +static void UART_Transmit (void); + + +// USART Driver Callback function +// event: event mask +static void USART_Callback (uint32_t event) { + if (event & ARM_USART_EVENT_SEND_COMPLETE) { + UartTxIndexO += UartTxNum; + UartTransmitActive = 0U; + UART_Transmit(); + } + if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) { + UartRxIndexI += UART_RX_BLOCK_SIZE; + UART_Receive(); + } + if (event & ARM_USART_EVENT_RX_OVERFLOW) { + UartErrorRxDataLost = 1U; + } + if (event & ARM_USART_EVENT_RX_FRAMING_ERROR) { + UartErrorFraming = 1U; + } + if (event & ARM_USART_EVENT_RX_PARITY_ERROR) { + UartErrorParity = 1U; + } +} + +// Init UART +// return: DAP_OK or DAP_ERROR +static uint8_t UART_Init (void) { + int32_t status; + uint8_t ret = DAP_ERROR; + + UartConfigured = 0U; + UartReceiveEnabled = 0U; + UartTransmitEnabled = 0U; + UartTransmitActive = 0U; + UartErrorRxDataLost = 0U; + UartErrorFraming = 0U; + UartErrorParity = 0U; + UartTxIndexI = 0U; + UartTxIndexO = 0U; + UartRxIndexI = 0U; + UartRxIndexO = 0U; + UartTxNum = 0U; + + status = pUSART->Initialize(USART_Callback); + if (status == ARM_DRIVER_OK) { + status = pUSART->PowerControl(ARM_POWER_FULL); + } + if (status == ARM_DRIVER_OK) { + ret = DAP_OK; + } + + return (ret); +} + +// Un-Init UART +static void UART_Uninit (void) { + UartConfigured = 0U; + + pUSART->PowerControl(ARM_POWER_OFF); + pUSART->Uninitialize(); +} + +// Get UART Status +// return: status +static uint8_t UART_Get_Status (void) { + uint8_t status = 0U; + + if (UartReceiveEnabled != 0U) { + status |= DAP_UART_STATUS_RX_ENABLED; + } + if (UartErrorRxDataLost != 0U) { + UartErrorRxDataLost = 0U; + status |= DAP_UART_STATUS_RX_DATA_LOST; + } + if (UartErrorFraming != 0U) { + UartErrorFraming = 0U; + status |= DAP_UART_STATUS_FRAMING_ERROR; + } + if (UartErrorParity != 0U) { + UartErrorParity = 0U; + status |= DAP_UART_STATUS_PARITY_ERROR; + } + if (UartTransmitEnabled != 0U) { + status |= DAP_UART_STATUS_TX_ENABLED; + } + + return (status); +} + +// Enable UART Receive +// return: DAP_OK or DAP_ERROR +static uint8_t UART_Receive_Enable (void) { + int32_t status; + uint8_t ret = DAP_ERROR; + + if (UartReceiveEnabled == 0U) { + // Flush Buffers + UartRxIndexI = 0U; + UartRxIndexO = 0U; + + UART_Receive(); + status = pUSART->Control(ARM_USART_CONTROL_RX, 1U); + if (status == ARM_DRIVER_OK) { + UartReceiveEnabled = 1U; + ret = DAP_OK; + } + } else { + ret = DAP_OK; + } + + return (ret); +} + +// Enable UART Transmit +// return: DAP_OK or DAP_ERROR +static uint8_t UART_Transmit_Enable (void) { + int32_t status; + uint8_t ret = DAP_ERROR; + + if (UartTransmitEnabled == 0U) { + // Flush Buffers + UartTransmitActive = 0U; + UartTxIndexI = 0U; + UartTxIndexO = 0U; + UartTxNum = 0U; + + status = pUSART->Control(ARM_USART_CONTROL_TX, 1U); + if (status == ARM_DRIVER_OK) { + UartTransmitEnabled = 1U; + ret = DAP_OK; + } + } else { + ret = DAP_OK; + } + + return (ret); +} + +// Disable UART Receive +static void UART_Receive_Disable (void) { + if (UartReceiveEnabled != 0U) { + pUSART->Control(ARM_USART_CONTROL_RX, 0U); + pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U); + UartReceiveEnabled = 0U; + } +} + +// Disable UART Transmit +static void UART_Transmit_Disable (void) { + if (UartTransmitEnabled != 0U) { + pUSART->Control(ARM_USART_ABORT_SEND, 0U); + pUSART->Control(ARM_USART_CONTROL_TX, 0U); + UartTransmitActive = 0U; + UartTransmitEnabled = 0U; + } +} + +// Flush UART Receive buffer +static void UART_Receive_Flush (void) { + pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U); + UartRxIndexI = 0U; + UartRxIndexO = 0U; + if (UartReceiveEnabled != 0U) { + UART_Receive(); + } +} + +// Flush UART Transmit buffer +static void UART_Transmit_Flush (void) { + pUSART->Control(ARM_USART_ABORT_SEND, 0U); + UartTransmitActive = 0U; + UartTxIndexI = 0U; + UartTxIndexO = 0U; + UartTxNum = 0U; +} + +// Receive data from target via UART +static void UART_Receive (void) { + uint32_t index; + + index = UartRxIndexI & (DAP_UART_RX_BUFFER_SIZE - 1U); + pUSART->Receive(&UartRxBuf[index], UART_RX_BLOCK_SIZE); +} + +// Transmit available data to target via UART +static void UART_Transmit (void) { + uint32_t count; + uint32_t index; + + count = UartTxIndexI - UartTxIndexO; + index = UartTxIndexO & (DAP_UART_TX_BUFFER_SIZE - 1U); + + if (count != 0U) { + if ((index + count) <= DAP_UART_TX_BUFFER_SIZE) { + UartTxNum = count; + } else { + UartTxNum = DAP_UART_TX_BUFFER_SIZE - index; + } + UartTransmitActive = 1U; + pUSART->Send(&UartTxBuf[index], UartTxNum); + } +} + +// Process UART Transport command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t UART_Transport (const uint8_t *request, uint8_t *response) { + uint8_t transport; + uint8_t ret = DAP_ERROR; + + transport = *request; + switch (transport) { + case DAP_UART_TRANSPORT_NONE: + switch (UartTransport) { + case DAP_UART_TRANSPORT_NONE: + ret = DAP_OK; + break; + case DAP_UART_TRANSPORT_USB_COM_PORT: +#if (DAP_UART_USB_COM_PORT != 0) + USB_COM_PORT_Activate(0U); + UartTransport = DAP_UART_TRANSPORT_NONE; + ret = DAP_OK; +#endif + break; + case DAP_UART_TRANSPORT_DAP_COMMAND: + UART_Receive_Disable(); + UART_Transmit_Disable(); + UART_Uninit(); + UartTransport = DAP_UART_TRANSPORT_NONE; + ret= DAP_OK; + break; + } + break; + case DAP_UART_TRANSPORT_USB_COM_PORT: + switch (UartTransport) { + case DAP_UART_TRANSPORT_NONE: +#if (DAP_UART_USB_COM_PORT != 0) + if (USB_COM_PORT_Activate(1U) == 0U) { + UartTransport = DAP_UART_TRANSPORT_USB_COM_PORT; + ret = DAP_OK; + } +#endif + break; + case DAP_UART_TRANSPORT_USB_COM_PORT: + ret = DAP_OK; + break; + case DAP_UART_TRANSPORT_DAP_COMMAND: + UART_Receive_Disable(); + UART_Transmit_Disable(); + UART_Uninit(); + UartTransport = DAP_UART_TRANSPORT_NONE; +#if (DAP_UART_USB_COM_PORT != 0) + if (USB_COM_PORT_Activate(1U) == 0U) { + UartTransport = DAP_UART_TRANSPORT_USB_COM_PORT; + ret = DAP_OK; + } +#endif + break; + } + break; + case DAP_UART_TRANSPORT_DAP_COMMAND: + switch (UartTransport) { + case DAP_UART_TRANSPORT_NONE: + ret = UART_Init(); + if (ret == DAP_OK) { + UartTransport = DAP_UART_TRANSPORT_DAP_COMMAND; + } + break; + case DAP_UART_TRANSPORT_USB_COM_PORT: +#if (DAP_UART_USB_COM_PORT != 0) + USB_COM_PORT_Activate(0U); + UartTransport = DAP_UART_TRANSPORT_NONE; +#endif + ret = UART_Init(); + if (ret == DAP_OK) { + UartTransport = DAP_UART_TRANSPORT_DAP_COMMAND; + } + break; + case DAP_UART_TRANSPORT_DAP_COMMAND: + ret = DAP_OK; + break; + } + break; + default: + break; + } + + *response = ret; + + return ((1U << 16) | 1U); +} + +// Process UART Configure command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t UART_Configure (const uint8_t *request, uint8_t *response) { + uint8_t control, status; + uint32_t baudrate; + int32_t result; + + if (UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) { + status = DAP_UART_CFG_ERROR_DATA_BITS | + DAP_UART_CFG_ERROR_PARITY | + DAP_UART_CFG_ERROR_STOP_BITS; + baudrate = 0U; // baudrate error + } else { + + status = 0U; + control = *request; + baudrate = (uint32_t)(*(request+1) << 0) | + (uint32_t)(*(request+2) << 8) | + (uint32_t)(*(request+3) << 16) | + (uint32_t)(*(request+4) << 24); + + result = pUSART->Control(control | + ARM_USART_MODE_ASYNCHRONOUS | + ARM_USART_FLOW_CONTROL_NONE, + baudrate); + if (result == ARM_DRIVER_OK) { + UartConfigured = 1U; + } else { + UartConfigured = 0U; + switch (result) { + case ARM_USART_ERROR_BAUDRATE: + status = 0U; + baudrate = 0U; + break; + case ARM_USART_ERROR_DATA_BITS: + status = DAP_UART_CFG_ERROR_DATA_BITS; + break; + case ARM_USART_ERROR_PARITY: + status = DAP_UART_CFG_ERROR_PARITY; + break; + case ARM_USART_ERROR_STOP_BITS: + status = DAP_UART_CFG_ERROR_STOP_BITS; + break; + default: + status = DAP_UART_CFG_ERROR_DATA_BITS | + DAP_UART_CFG_ERROR_PARITY | + DAP_UART_CFG_ERROR_STOP_BITS; + baudrate = 0U; + break; + } + } + } + + *response++ = status; + *response++ = (uint8_t)(baudrate >> 0); + *response++ = (uint8_t)(baudrate >> 8); + *response++ = (uint8_t)(baudrate >> 16); + *response = (uint8_t)(baudrate >> 24); + + return ((5U << 16) | 5U); +} + +// Process UART Control command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t UART_Control (const uint8_t *request, uint8_t *response) { + uint8_t control; + uint8_t result; + uint8_t ret = DAP_OK; + + if (UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) { + ret = DAP_ERROR; + } else { + + control = *request; + + if ((control & DAP_UART_CONTROL_RX_DISABLE) != 0U) { + // Receive disable + UART_Receive_Disable(); + } else if ((control & DAP_UART_CONTROL_RX_ENABLE) != 0U) { + // Receive enable + if (UartConfigured != 0U) { + result = UART_Receive_Enable(); + if (result != DAP_OK) { + ret = DAP_ERROR; + } + } else { + ret = DAP_ERROR; + } + } + if ((control & DAP_UART_CONTROL_RX_BUF_FLUSH) != 0U) { + UART_Receive_Flush(); + } + + if ((control & DAP_UART_CONTROL_TX_DISABLE) != 0U) { + // Transmit disable + UART_Transmit_Disable(); + } else if ((control & DAP_UART_CONTROL_TX_ENABLE) != 0U) { + // Transmit enable + if (UartConfigured != 0U) { + result = UART_Transmit_Enable(); + if (result != DAP_OK) { + ret = DAP_ERROR; + } + } else { + ret = DAP_ERROR; + } + } + if ((control & DAP_UART_CONTROL_TX_BUF_FLUSH) != 0U) { + UART_Transmit_Flush(); + } + } + + *response = ret; + + return ((1U << 16) | 1U); +} + +// Process UART Status command and prepare response +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t UART_Status (uint8_t *response) { + uint32_t rx_cnt, tx_cnt; + uint32_t cnt; + uint8_t status; + + if ((UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) || + (UartConfigured == 0U)) { + rx_cnt = 0U; + tx_cnt = 0U; + status = 0U; + } else { + + rx_cnt = UartRxIndexI - UartRxIndexO; + rx_cnt += pUSART->GetRxCount(); + if (rx_cnt > (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2))) { + // Overflow + UartErrorRxDataLost = 1U; + rx_cnt = (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2)); + UartRxIndexO = UartRxIndexI - rx_cnt; + } + + tx_cnt = UartTxIndexI - UartTxIndexO; + cnt = pUSART->GetTxCount(); + if (UartTransmitActive != 0U) { + tx_cnt -= cnt; + } + + status = UART_Get_Status(); + } + + *response++ = status; + *response++ = (uint8_t)(rx_cnt >> 0); + *response++ = (uint8_t)(rx_cnt >> 8); + *response++ = (uint8_t)(rx_cnt >> 16); + *response++ = (uint8_t)(rx_cnt >> 24); + *response++ = (uint8_t)(tx_cnt >> 0); + *response++ = (uint8_t)(tx_cnt >> 8); + *response++ = (uint8_t)(tx_cnt >> 16); + *response = (uint8_t)(tx_cnt >> 24); + + return ((0U << 16) | 9U); +} + +// Process UART Transfer command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t UART_Transfer (const uint8_t *request, uint8_t *response) { + uint32_t rx_cnt, tx_cnt; + uint32_t rx_num, tx_num; + uint8_t *rx_data; + const + uint8_t *tx_data; + uint32_t num; + uint32_t index; + uint8_t status; + + if (UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) { + status = 0U; + rx_cnt = 0U; + tx_cnt = 0U; + } else { + + // RX Data + rx_cnt = ((uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8)); + + if (rx_cnt > (DAP_PACKET_SIZE - 6U)) { + rx_cnt = (DAP_PACKET_SIZE - 6U); + } + rx_num = UartRxIndexI - UartRxIndexO; + rx_num += pUSART->GetRxCount(); + if (rx_num > (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2))) { + // Overflow + UartErrorRxDataLost = 1U; + rx_num = (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2)); + UartRxIndexO = UartRxIndexI - rx_num; + } + if (rx_cnt > rx_num) { + rx_cnt = rx_num; + } + + rx_data = (response+5); + index = UartRxIndexO & (DAP_UART_RX_BUFFER_SIZE - 1U); + if ((index + rx_cnt) <= DAP_UART_RX_BUFFER_SIZE) { + memcpy( rx_data, &UartRxBuf[index], rx_cnt); + } else { + num = DAP_UART_RX_BUFFER_SIZE - index; + memcpy( rx_data, &UartRxBuf[index], num); + memcpy(&rx_data[num], &UartRxBuf[0], rx_cnt - num); + } + UartRxIndexO += rx_cnt; + + // TX Data + tx_cnt = ((uint32_t)(*(request+2) << 0) | + (uint32_t)(*(request+3) << 8)); + tx_data = (request+4); + + if (tx_cnt > (DAP_PACKET_SIZE - 5U)) { + tx_cnt = (DAP_PACKET_SIZE - 5U); + } + tx_num = UartTxIndexI - UartTxIndexO; + num = pUSART->GetTxCount(); + if (UartTransmitActive != 0U) { + tx_num -= num; + } + if (tx_cnt > (DAP_UART_TX_BUFFER_SIZE - tx_num)) { + tx_cnt = (DAP_UART_TX_BUFFER_SIZE - tx_num); + } + + index = UartTxIndexI & (DAP_UART_TX_BUFFER_SIZE - 1U); + if ((index + tx_cnt) <= DAP_UART_TX_BUFFER_SIZE) { + memcpy(&UartTxBuf[index], tx_data, tx_cnt); + } else { + num = DAP_UART_TX_BUFFER_SIZE - index; + memcpy(&UartTxBuf[index], tx_data, num); + memcpy(&UartTxBuf[0], &tx_data[num], tx_cnt - num); + } + UartTxIndexI += tx_cnt; + + if (UartTransmitActive == 0U) { + UART_Transmit(); + } + + status = UART_Get_Status(); + } + + *response++ = status; + *response++ = (uint8_t)(tx_cnt >> 0); + *response++ = (uint8_t)(tx_cnt >> 8); + *response++ = (uint8_t)(rx_cnt >> 0); + *response = (uint8_t)(rx_cnt >> 8); + + return (((4U + tx_cnt) << 16) | (5U + rx_cnt)); +} + +#endif /* DAP_UART */ diff --git a/source/daplink/cmsis-dap/SWO.c b/source/daplink/cmsis-dap/SWO.c index 56c97cb16..4a850cf88 100644 --- a/source/daplink/cmsis-dap/SWO.c +++ b/source/daplink/cmsis-dap/SWO.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2021 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -17,8 +17,8 @@ * * ---------------------------------------------------------------------- * - * $Date: 1. December 2017 - * $Revision: V2.0.0 + * $Date: 29. March 2021 + * $Revision: V2.0.1 * * Project: CMSIS-DAP Source * Title: SWO.c CMSIS-DAP SWO I/O @@ -32,6 +32,8 @@ #endif #if (SWO_STREAM != 0) #include "cmsis_os2.h" +#define osObjectsExternal +#include "osObjects.h" #endif #if (SWO_STREAM != 0) @@ -42,15 +44,11 @@ #if (SWO_UART != 0) -#ifndef SWO_USART_PORT -#define SWO_USART_PORT 0 /* USART Port Number */ -#endif - // USART Driver #define _USART_Driver_(n) Driver_USART##n #define USART_Driver_(n) _USART_Driver_(n) -extern ARM_DRIVER_USART USART_Driver_(SWO_USART_PORT); -#define pUSART (&USART_Driver_(SWO_USART_PORT)) +extern ARM_DRIVER_USART USART_Driver_(SWO_UART_DRIVER); +#define pUSART (&USART_Driver_(SWO_UART_DRIVER)) static uint8_t USART_Ready = 0U; @@ -79,7 +77,7 @@ static volatile uint32_t TraceIndexO = 0U; /* Outgoing Trace Index */ static volatile uint8_t TraceUpdate; /* Trace Update Flag */ static uint32_t TraceBlockSize; /* Current Trace Block Size */ -#if (TIMESTAMP_CLOCK != 0U) +#if (TIMESTAMP_CLOCK != 0U) // Trace Timestamp static volatile struct { uint32_t index; @@ -112,14 +110,14 @@ static void USART_Callback (uint32_t event) { uint32_t num; if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) { -#if (TIMESTAMP_CLOCK != 0U) +#if (TIMESTAMP_CLOCK != 0U) TraceTimestamp.tick = TIMESTAMP_GET(); #endif index_o = TraceIndexO; index_i = TraceIndexI; index_i += TraceBlockSize; TraceIndexI = index_i; -#if (TIMESTAMP_CLOCK != 0U) +#if (TIMESTAMP_CLOCK != 0U) TraceTimestamp.index = index_i; #endif num = TRACE_BLOCK_SIZE - (index_i & (TRACE_BLOCK_SIZE - 1U)); @@ -150,10 +148,10 @@ static void USART_Callback (uint32_t event) { } } -// Enable or disable UART SWO Mode +// Enable or disable SWO Mode (UART) // enable: enable flag // return: 1 - Success, 0 - Error -__WEAK uint32_t UART_SWO_Mode (uint32_t enable) { +__WEAK uint32_t SWO_Mode_UART (uint32_t enable) { int32_t status; USART_Ready = 0U; @@ -177,10 +175,10 @@ __WEAK uint32_t UART_SWO_Mode (uint32_t enable) { return (1U); } -// Configure UART SWO Baudrate +// Configure SWO Baudrate (UART) // baudrate: requested baudrate // return: actual baudrate or 0 when not configured -__WEAK uint32_t UART_SWO_Baudrate (uint32_t baudrate) { +__WEAK uint32_t SWO_Baudrate_UART (uint32_t baudrate) { int32_t status; uint32_t index; uint32_t num; @@ -223,14 +221,14 @@ __WEAK uint32_t UART_SWO_Baudrate (uint32_t baudrate) { return (baudrate); } -// Control UART SWO Capture +// Control SWO Capture (UART) // active: active flag // return: 1 - Success, 0 - Error -__WEAK uint32_t UART_SWO_Control (uint32_t active) { +__WEAK uint32_t SWO_Control_UART (uint32_t active) { int32_t status; if (active) { - if (!USART_Ready) { + if (!USART_Ready) { return (0U); } TraceBlockSize = 1U; @@ -252,17 +250,17 @@ __WEAK uint32_t UART_SWO_Control (uint32_t active) { return (1U); } -// Start UART SWO Capture +// Start SWO Capture (UART) // buf: pointer to buffer for capturing // num: number of bytes to capture -__WEAK void UART_SWO_Capture (uint8_t *buf, uint32_t num) { +__WEAK void SWO_Capture_UART (uint8_t *buf, uint32_t num) { TraceBlockSize = num; pUSART->Receive(buf, num); } -// Get UART SWO Pending Trace Count +// Get SWO Pending Trace Count (UART) // return: number of pending trace data bytes -__WEAK uint32_t UART_SWO_GetCount (void) { +__WEAK uint32_t SWO_GetCount_UART (void) { uint32_t count; if (pUSART->GetStatus().rx_busy) { @@ -278,36 +276,36 @@ __WEAK uint32_t UART_SWO_GetCount (void) { #if (SWO_MANCHESTER != 0) -// Enable or disable Manchester SWO Mode +// Enable or disable SWO Mode (Manchester) // enable: enable flag // return: 1 - Success, 0 - Error -__WEAK uint32_t Manchester_SWO_Mode (uint32_t enable) { +__WEAK uint32_t SWO_Mode_Manchester (uint32_t enable) { return (0U); } -// Configure Manchester SWO Baudrate +// Configure SWO Baudrate (Manchester) // baudrate: requested baudrate // return: actual baudrate or 0 when not configured -__WEAK uint32_t Manchester_SWO_Baudrate (uint32_t baudrate) { +__WEAK uint32_t SWO_Baudrate_Manchester (uint32_t baudrate) { return (0U); } -// Control Manchester SWO Capture +// Control SWO Capture (Manchester) // active: active flag // return: 1 - Success, 0 - Error -__WEAK uint32_t Manchester_SWO_Control (uint32_t active) { +__WEAK uint32_t SWO_Control_Manchester (uint32_t active) { return (0U); } -// Start Manchester SWO Capture +// Start SWO Capture (Manchester) // buf: pointer to buffer for capturing // num: number of bytes to capture -__WEAK void Manchester_SWO_Capture (uint8_t *buf, uint32_t num) { +__WEAK void SWO_Capture_Manchester (uint8_t *buf, uint32_t num) { } -// Get Manchester SWO Pending Trace Count +// Get SWO Pending Trace Count (Manchester) // return: number of pending trace data bytes -__WEAK uint32_t Manchester_SWO_GetCount (void) { +__WEAK uint32_t SWO_GetCount_Manchester (void) { } #endif /* (SWO_MANCHESTER != 0) */ @@ -331,7 +329,7 @@ static void ClearTrace (void) { TraceIndexI = 0U; TraceIndexO = 0U; -#if (TIMESTAMP_CLOCK != 0U) +#if (TIMESTAMP_CLOCK != 0U) TraceTimestamp.index = 0U; TraceTimestamp.tick = 0U; #endif @@ -351,13 +349,13 @@ static void ResumeTrace (void) { #if (SWO_UART != 0) case DAP_SWO_UART: TraceStatus = DAP_SWO_CAPTURE_ACTIVE; - UART_SWO_Capture(&TraceBuf[index_i], 1U); + SWO_Capture_UART(&TraceBuf[index_i], 1U); break; #endif #if (SWO_MANCHESTER != 0) case DAP_SWO_MANCHESTER: TraceStatus = DAP_SWO_CAPTURE_ACTIVE; - Manchester_SWO_Capture(&TraceBuf[index_i], 1U); + SWO_Capture_Manchester(&TraceBuf[index_i], 1U); break; #endif default: @@ -379,12 +377,12 @@ static uint32_t GetTraceCount (void) { switch (TraceMode) { #if (SWO_UART != 0) case DAP_SWO_UART: - count += UART_SWO_GetCount(); + count += SWO_GetCount_UART(); break; #endif #if (SWO_MANCHESTER != 0) case DAP_SWO_MANCHESTER: - count += Manchester_SWO_GetCount(); + count += SWO_GetCount_Manchester(); break; #endif default: @@ -471,12 +469,12 @@ uint32_t SWO_Mode (const uint8_t *request, uint8_t *response) { switch (TraceMode) { #if (SWO_UART != 0) case DAP_SWO_UART: - UART_SWO_Mode(0U); + SWO_Mode_UART(0U); break; #endif #if (SWO_MANCHESTER != 0) case DAP_SWO_MANCHESTER: - Manchester_SWO_Mode(0U); + SWO_Mode_Manchester(0U); break; #endif default: @@ -489,12 +487,12 @@ uint32_t SWO_Mode (const uint8_t *request, uint8_t *response) { break; #if (SWO_UART != 0) case DAP_SWO_UART: - result = UART_SWO_Mode(1U); + result = SWO_Mode_UART(1U); break; #endif #if (SWO_MANCHESTER != 0) case DAP_SWO_MANCHESTER: - result = Manchester_SWO_Mode(1U); + result = SWO_Mode_Manchester(1U); break; #endif default: @@ -535,12 +533,12 @@ uint32_t SWO_Baudrate (const uint8_t *request, uint8_t *response) { switch (TraceMode) { #if (SWO_UART != 0) case DAP_SWO_UART: - baudrate = UART_SWO_Baudrate(baudrate); + baudrate = SWO_Baudrate_UART(baudrate); break; #endif #if (SWO_MANCHESTER != 0) case DAP_SWO_MANCHESTER: - baudrate = Manchester_SWO_Baudrate(baudrate); + baudrate = SWO_Baudrate_Manchester(baudrate); break; #endif default: @@ -579,12 +577,12 @@ uint32_t SWO_Control (const uint8_t *request, uint8_t *response) { switch (TraceMode) { #if (SWO_UART != 0) case DAP_SWO_UART: - result = UART_SWO_Control(active); + result = SWO_Control_UART(active); break; #endif #if (SWO_MANCHESTER != 0) case DAP_SWO_MANCHESTER: - result = Manchester_SWO_Control(active); + result = SWO_Control_Manchester(active); break; #endif default: @@ -642,7 +640,7 @@ uint32_t SWO_ExtendedStatus (const uint8_t *request, uint8_t *response) { uint8_t cmd; uint8_t status; uint32_t count; -#if (TIMESTAMP_CLOCK != 0U) +#if (TIMESTAMP_CLOCK != 0U) uint32_t index; uint32_t tick; #endif @@ -666,7 +664,7 @@ uint32_t SWO_ExtendedStatus (const uint8_t *request, uint8_t *response) { num += 4U; } -#if (TIMESTAMP_CLOCK != 0U) +#if (TIMESTAMP_CLOCK != 0U) if (cmd & 0x04U) { do { TraceUpdate = 0U; diff --git a/source/daplink/cmsis-dap/dap_strings.h b/source/daplink/cmsis-dap/dap_strings.h index cb7f73bb1..ba89799bc 100644 --- a/source/daplink/cmsis-dap/dap_strings.h +++ b/source/daplink/cmsis-dap/dap_strings.h @@ -21,18 +21,18 @@ #include "cmsis_compiler.h" #include "info.h" -/** Get Vendor ID string. -\param str Pointer to buffer to store the string. -\return String length. +/** Get Vendor Name string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). */ __STATIC_INLINE uint8_t DAP_GetVendorString (char *str) { (void)str; return (0U); } -/** Get Product ID string. -\param str Pointer to buffer to store the string. -\return String length. +/** Get Product Name string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). */ __STATIC_INLINE uint8_t DAP_GetProductString (char *str) { (void)str; @@ -40,8 +40,8 @@ __STATIC_INLINE uint8_t DAP_GetProductString (char *str) { } /** Get Serial Number string. -\param str Pointer to buffer to store the string. -\return String length. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). */ __STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) { const char * data = info_get_unique_id(); @@ -50,11 +50,79 @@ __STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) { return length; } -/** Get firmware version string. -\param str Pointer to buffer to store the string. -\return String length. +/** Get Target Device Vendor string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). */ -__STATIC_INLINE uint8_t DAP_ProductFirmwareVerString (char *str) { +__STATIC_INLINE uint8_t DAP_GetTargetDeviceVendorString (char *str) { +#if TARGET_FIXED != 0 + uint8_t len; + + strcpy(str, TargetDeviceVendor); + len = (uint8_t)(strlen(TargetDeviceVendor) + 1U); + return (len); +#else + (void)str; + return (0U); +#endif +} + +/** Get Target Device Name string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetTargetDeviceNameString (char *str) { +#if TARGET_FIXED != 0 + uint8_t len; + + strcpy(str, TargetDeviceName); + len = (uint8_t)(strlen(TargetDeviceName) + 1U); + return (len); +#else + (void)str; + return (0U); +#endif +} + +/** Get Target Board Vendor string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetTargetBoardVendorString (char *str) { +#if TARGET_FIXED != 0 + uint8_t len; + + strcpy(str, TargetBoardVendor); + len = (uint8_t)(strlen(TargetBoardVendor) + 1U); + return (len); +#else + (void)str; + return (0U); +#endif +} + +/** Get Target Board Name string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetTargetBoardNameString (char *str) { +#if TARGET_FIXED != 0 + uint8_t len; + + strcpy(str, TargetBoardName); + len = (uint8_t)(strlen(TargetBoardName) + 1U); + return (len); +#else + (void)str; + return (0U); +#endif +} + +/** Get Product Firmware Version string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetProductFirmwareVersionString (char *str) { const char * data = info_get_version(); uint8_t length = (uint8_t)strlen(data) + 1; memcpy(str, data, length); diff --git a/source/hic_hal/atmel/sam3u2c/DAP_config.h b/source/hic_hal/atmel/sam3u2c/DAP_config.h index bb39b9aa4..22b5c0478 100644 --- a/source/hic_hal/atmel/sam3u2c/DAP_config.h +++ b/source/hic_hal/atmel/sam3u2c/DAP_config.h @@ -3,7 +3,7 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2021, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -22,19 +22,29 @@ #ifndef __DAP_CONFIG_H__ #define __DAP_CONFIG_H__ +#include "IO_Config.h" + //************************************************************************************************** /** \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information \ingroup DAP_ConfigIO_gr @{ -Provides definitions about: +Provides definitions about the hardware and configuration of the Debug Unit. + +This information includes: - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. + - Debug Unit Identification strings (Vendor, Product, Serial Number). - Debug Unit communication packet size. - - Debug Access Port communication mode (JTAG or SWD). + - Debug Access Port supported modes and settings (JTAG/SWD and SWO). - Optional information about a connected Target Device (for Evaluation Boards). */ -#include "IO_Config.h" +#ifdef _RTE_ +#include "RTE_Components.h" +#include CMSIS_device_header +#else +#include "device.h" // Debug Unit Cortex-M Processor Header File +#endif /// Processor Clock of the Cortex-M MCU used in the Debug Unit. /// This value is used to calculate the SWD/JTAG clock speed. @@ -43,10 +53,10 @@ Provides definitions about: /// Number of processor cycles for I/O Port write operations. /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors -/// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses +/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be -/// requrired. -#define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0 +/// required. +#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. /// This information is returned by the command \ref DAP_Info as part of Capabilities. @@ -70,12 +80,17 @@ Provides definitions about: #define DAP_DEFAULT_SWJ_CLOCK 2000000 ///< Default SWD/JTAG clock frequency in Hz. /// Maximum Package Size for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the -/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB. -#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed. +/// This configuration settings is used to optimize the communication performance with the +/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB, +/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB. +#ifndef HID_ENDPOINT //HID end points currently set limits to 64 +#define DAP_PACKET_SIZE 512 ///< Specifies Packet Size in bytes. +#else +#define DAP_PACKET_SIZE 64 ///< Specifies Packet Size in bytes. +#endif /// Maximum Package Buffers for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the +/// This configuration settings is used to optimize the communication performance with the /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB. #define DAP_PACKET_COUNT 4 ///< Buffers: 64 = Full-Speed, 4 = High-Speed. @@ -84,15 +99,18 @@ Provides definitions about: /// This information is returned by the command \ref DAP_Info as part of Capabilities. #define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available +/// USART Driver instance number for the UART SWO. +#define SWO_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#). + /// Maximum SWO UART Baudrate #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz /// Indicate that Manchester Serial Wire Output (SWO) trace is available. /// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available +#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available. /// SWO Trace Buffer Size. -#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n) +#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n). /// SWO Streaming Trace. #define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available. @@ -100,17 +118,28 @@ Provides definitions about: /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. #define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported). +/// Indicate that UART Communication Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART 0 ///< DAP UART: 1 = available, 0 = not available. + +/// USART Driver instance number for the UART Communication Port. +#define DAP_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#). + +/// UART Receive Buffer Size. +#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n). + +/// UART Transmit Buffer Size. +#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n). + +/// Indicate that UART Communication via USB COM Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available. /// Debug Unit is connected to fixed Target Device. /// The Debug Unit may be part of an evaluation board and always connected to a fixed -/// known device. In this case a Device Vendor and Device Name string is stored which -/// may be used by the debugger or IDE to configure device parameters. -#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown; - -#if TARGET_DEVICE_FIXED -#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor -#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device -#endif +/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings +/// are stored and may be used by the debugger or IDE to configure device parameters. +#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown; ///@} diff --git a/source/hic_hal/device.h b/source/hic_hal/device.h index 00b9ecbc2..0e21d93c5 100644 --- a/source/hic_hal/device.h +++ b/source/hic_hal/device.h @@ -39,7 +39,7 @@ #elif defined (INTERFACE_SAM3U2C) #include "sam3u2c.h" #elif defined (INTERFACE_STM32F103XB) -#include "stm32f103xb.h" +#include "stm32f1xx.h" #elif defined (INTERFACE_M48SSIDAE) #include "M480.h" #else diff --git a/source/hic_hal/freescale/k20dx/DAP_config.h b/source/hic_hal/freescale/k20dx/DAP_config.h index e6a7c809f..4af90be49 100644 --- a/source/hic_hal/freescale/k20dx/DAP_config.h +++ b/source/hic_hal/freescale/k20dx/DAP_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2021 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -17,8 +17,8 @@ * * ---------------------------------------------------------------------- * - * $Date: 1. December 2017 - * $Revision: V2.0.0 + * $Date: 16. June 2021 + * $Revision: V2.1.0 * * Project: CMSIS-DAP Configuration * Title: DAP_config.h CMSIS-DAP Configuration File (Template) @@ -45,6 +45,13 @@ This information includes: - Optional information about a connected Target Device (for Evaluation Boards). */ +#ifdef _RTE_ +#include "RTE_Components.h" +#include CMSIS_device_header +#else +#include "device.h" // Debug Unit Cortex-M Processor Header File +#endif + /// Processor Clock of the Cortex-M MCU used in the Debug Unit. /// This value is used to calculate the SWD/JTAG clock speed. #define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz. @@ -94,6 +101,9 @@ This information includes: /// This information is returned by the command \ref DAP_Info as part of Capabilities. #define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available. +/// USART Driver instance number for the UART SWO. +#define SWO_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#). + /// Maximum SWO UART Baudrate. #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz. @@ -110,16 +120,28 @@ This information includes: /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. #define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported). +/// Indicate that UART Communication Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART 0 ///< DAP UART: 1 = available, 0 = not available. + +/// USART Driver instance number for the UART Communication Port. +#define DAP_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#). + +/// UART Receive Buffer Size. +#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n). + +/// UART Transmit Buffer Size. +#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n). + +/// Indicate that UART Communication via USB COM Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available. + /// Debug Unit is connected to fixed Target Device. /// The Debug Unit may be part of an evaluation board and always connected to a fixed -/// known device. In this case a Device Vendor and Device Name string is stored which -/// may be used by the debugger or IDE to configure device parameters. -#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown; - -#if TARGET_DEVICE_FIXED -#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor -#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device -#endif +/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings +/// are stored and may be used by the debugger or IDE to configure device parameters. +#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown; ///@} diff --git a/source/hic_hal/freescale/k26f/DAP_config.h b/source/hic_hal/freescale/k26f/DAP_config.h index 2add04ee2..49b92d9f3 100644 --- a/source/hic_hal/freescale/k26f/DAP_config.h +++ b/source/hic_hal/freescale/k26f/DAP_config.h @@ -3,7 +3,7 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2021, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -33,12 +33,18 @@ Provides definitions about the hardware and configuration of the Debug Unit. This information includes: - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. + - Debug Unit Identification strings (Vendor, Product, Serial Number). - Debug Unit communication packet size. - - Debug Access Port communication mode (JTAG or SWD). + - Debug Access Port supported modes and settings (JTAG/SWD and SWO). - Optional information about a connected Target Device (for Evaluation Boards). */ -#include "fsl_device_registers.h" // Debug Unit Cortex-M Processor Header File +#ifdef _RTE_ +#include "RTE_Components.h" +#include CMSIS_device_header +#else +#include "device.h" // Debug Unit Cortex-M Processor Header File +#endif /// Processor Clock of the Cortex-M MCU used in the Debug Unit. /// This value is used to calculate the SWD/JTAG clock speed. @@ -74,16 +80,17 @@ This information includes: #define DAP_DEFAULT_SWJ_CLOCK 4000000 ///< Default SWD/JTAG clock frequency in Hz. /// Maximum Package Size for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the -/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB. +/// This configuration settings is used to optimize the communication performance with the +/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB, +/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB. #ifndef HID_ENDPOINT //HID end points currently set limits to 64 -#define DAP_PACKET_SIZE 512 ///< USB: 64 = Full-Speed, 512 = High-Speed. +#define DAP_PACKET_SIZE 512 ///< Specifies Packet Size in bytes. #else -#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 512 = High-Speed. +#define DAP_PACKET_SIZE 64 ///< Specifies Packet Size in bytes. #endif /// Maximum Package Buffers for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the +/// This configuration settings is used to optimize the communication performance with the /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB. #define DAP_PACKET_COUNT 64U ///< Buffers: 64 = Full-Speed, 4 = High-Speed. @@ -92,17 +99,18 @@ This information includes: /// This information is returned by the command \ref DAP_Info as part of Capabilities. #define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available +/// USART Driver instance number for the UART SWO. +#define SWO_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#). + /// Maximum SWO UART Baudrate #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz /// Indicate that Manchester Serial Wire Output (SWO) trace is available. /// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available +#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available. /// SWO Trace Buffer Size. -#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n) - -#define SWO_USART_PORT 1 ///< UART1 is used for the SWO UART. +#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n). /// SWO Streaming Trace. #define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available. @@ -110,19 +118,32 @@ This information includes: /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. #define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported). +/// Indicate that UART Communication Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART 0 ///< DAP UART: 1 = available, 0 = not available. + +/// USART Driver instance number for the UART Communication Port. +#define DAP_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#). + +/// UART Receive Buffer Size. +#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n). + +/// UART Transmit Buffer Size. +#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n). + +/// Indicate that UART Communication via USB COM Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available. + /// Debug Unit is connected to fixed Target Device. /// The Debug Unit may be part of an evaluation board and always connected to a fixed -/// known device. In this case a Device Vendor and Device Name string is stored which -/// may be used by the debugger or IDE to configure device parameters. -#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown; - -#if TARGET_DEVICE_FIXED -#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor -#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device -#endif +/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings +/// are stored and may be used by the debugger or IDE to configure device parameters. +#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown; ///@} + //************************************************************************************************** /** \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access @@ -166,14 +187,14 @@ Configures the DAP Hardware I/O pins for JTAG mode: - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level. - TDO to input mode. */ -static inline void PORT_JTAG_SETUP(void) {} +__STATIC_INLINE void PORT_JTAG_SETUP(void) {} /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET. Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: - SWCLK, SWDIO, nRESET to output mode and set to default high level. - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode). */ -static inline void PORT_SWD_SETUP(void) +__STATIC_INLINE void PORT_SWD_SETUP(void) { PIN_SWCLK_GPIO->PSOR = 1 << PIN_SWCLK_BIT; PIN_SWDIO_OUT_GPIO->PSOR = 1 << PIN_SWDIO_OUT_BIT; @@ -190,7 +211,7 @@ static inline void PORT_SWD_SETUP(void) Disables the DAP Hardware I/O pins which configures: - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode. */ -static inline void PORT_OFF(void) +__STATIC_INLINE void PORT_OFF(void) { PIN_SWDIO_OE_GPIO->PCOR = 1 << PIN_SWDIO_OE_BIT; PIN_SWD_OE_GPIO->PCOR = 1 << PIN_SWD_OE_BIT; @@ -380,7 +401,7 @@ It is recommended to provide the following LEDs for status indication: - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit. - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit. */ -static inline void LED_CONNECTED_OUT(uint32_t bit) +__STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit) { BITBAND_REG(LED_CONNECTED_GPIO->PDOR, LED_CONNECTED_BIT) = ~bit; } @@ -390,7 +411,7 @@ static inline void LED_CONNECTED_OUT(uint32_t bit) - 1: Target Running LED ON: program execution in target started. - 0: Target Running LED OFF: program execution in target stopped. */ -static inline void LED_RUNNING_OUT(uint32_t bit) +__STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit) { ; // Not available } @@ -437,7 +458,7 @@ Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled an - for nTRST, nRESET a weak pull-up (if available) is enabled. - LED output pins are enabled and LEDs are turned off. */ -static inline void DAP_SETUP(void) +__STATIC_INLINE void DAP_SETUP(void) { SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK | /* Enable Port A Clock */ SIM_SCGC5_PORTB_MASK | /* Enable Port B Clock */ @@ -497,7 +518,7 @@ when a device needs a time-critical unlock sequence that enables the debug port. \return 0 = no device specific reset sequence is implemented.\n 1 = a device specific reset sequence is implemented. */ -static inline uint32_t RESET_TARGET(void) +__STATIC_INLINE uint32_t RESET_TARGET(void) { return (0); // change to '1' when a device reset sequence is implemented } diff --git a/source/hic_hal/freescale/kl26z/DAP_config.h b/source/hic_hal/freescale/kl26z/DAP_config.h index 672e62906..d0228c39a 100644 --- a/source/hic_hal/freescale/kl26z/DAP_config.h +++ b/source/hic_hal/freescale/kl26z/DAP_config.h @@ -3,7 +3,7 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2021, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -30,13 +30,23 @@ \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information \ingroup DAP_ConfigIO_gr @{ -Provides definitions about: +Provides definitions about the hardware and configuration of the Debug Unit. + +This information includes: - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. + - Debug Unit Identification strings (Vendor, Product, Serial Number). - Debug Unit communication packet size. - - Debug Access Port communication mode (JTAG or SWD). + - Debug Access Port supported modes and settings (JTAG/SWD and SWO). - Optional information about a connected Target Device (for Evaluation Boards). */ +#ifdef _RTE_ +#include "RTE_Components.h" +#include CMSIS_device_header +#else +#include "device.h" // Debug Unit Cortex-M Processor Header File +#endif + /// Processor Clock of the Cortex-M MCU used in the Debug Unit. /// This value is used to calculate the SWD/JTAG clock speed. #define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz @@ -44,9 +54,9 @@ Provides definitions about: /// Number of processor cycles for I/O Port write operations. /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors -/// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses +/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be -/// requrired. +/// required. #define IO_PORT_WRITE_CYCLES 1 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. @@ -71,12 +81,17 @@ Provides definitions about: #define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz. /// Maximum Package Size for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the -/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB. -#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed. +/// This configuration settings is used to optimize the communication performance with the +/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB, +/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB. +#ifndef HID_ENDPOINT //HID end points currently set limits to 64 +#define DAP_PACKET_SIZE 512 ///< Specifies Packet Size in bytes. +#else +#define DAP_PACKET_SIZE 64 ///< Specifies Packet Size in bytes. +#endif /// Maximum Package Buffers for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the +/// This configuration settings is used to optimize the communication performance with the /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB. #define DAP_PACKET_COUNT 5 ///< Buffers: 64 = Full-Speed, 4 = High-Speed. @@ -85,33 +100,48 @@ Provides definitions about: /// This information is returned by the command \ref DAP_Info as part of Capabilities. #define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available +/// USART Driver instance number for the UART SWO. +#define SWO_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#). + /// Maximum SWO UART Baudrate #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz /// Indicate that Manchester Serial Wire Output (SWO) trace is available. /// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available +#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available. /// SWO Trace Buffer Size. -#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n) +#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n). /// SWO Streaming Trace. #define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available. /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. #define TIMESTAMP_CLOCK 0U ///< Timestamp clock in Hz (0 = timestamps not supported). +// DAPLink: disabled because we use DWT for timestamps and M0+ doesn't have a DWT. + +/// Indicate that UART Communication Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART 0 ///< DAP UART: 1 = available, 0 = not available. +/// USART Driver instance number for the UART Communication Port. +#define DAP_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#). + +/// UART Receive Buffer Size. +#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n). + +/// UART Transmit Buffer Size. +#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n). + +/// Indicate that UART Communication via USB COM Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available. /// Debug Unit is connected to fixed Target Device. /// The Debug Unit may be part of an evaluation board and always connected to a fixed -/// known device. In this case a Device Vendor and Device Name string is stored which -/// may be used by the debugger or IDE to configure device parameters. -#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown; - -#if TARGET_DEVICE_FIXED -#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor -#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device -#endif +/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings +/// are stored and may be used by the debugger or IDE to configure device parameters. +#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown; ///@} diff --git a/source/hic_hal/freescale/kl27z/DAP_config.h b/source/hic_hal/freescale/kl27z/DAP_config.h index 3bd98065c..e172f48e2 100644 --- a/source/hic_hal/freescale/kl27z/DAP_config.h +++ b/source/hic_hal/freescale/kl27z/DAP_config.h @@ -3,7 +3,7 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2021, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -19,7 +19,6 @@ * limitations under the License. */ - #ifndef __DAP_CONFIG_H__ #define __DAP_CONFIG_H__ @@ -30,13 +29,23 @@ \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information \ingroup DAP_ConfigIO_gr @{ -Provides definitions about: +Provides definitions about the hardware and configuration of the Debug Unit. + +This information includes: - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. + - Debug Unit Identification strings (Vendor, Product, Serial Number). - Debug Unit communication packet size. - - Debug Access Port communication mode (JTAG or SWD). + - Debug Access Port supported modes and settings (JTAG/SWD and SWO). - Optional information about a connected Target Device (for Evaluation Boards). */ +#ifdef _RTE_ +#include "RTE_Components.h" +#include CMSIS_device_header +#else +#include "device.h" // Debug Unit Cortex-M Processor Header File +#endif + /// Processor Clock of the Cortex-M MCU used in the Debug Unit. /// This value is used to calculate the SWD/JTAG clock speed. #define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz @@ -44,9 +53,9 @@ Provides definitions about: /// Number of processor cycles for I/O Port write operations. /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors -/// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses +/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be -/// requrired. +/// required. #define IO_PORT_WRITE_CYCLES 1 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. @@ -73,12 +82,17 @@ Provides definitions about: #endif /// Maximum Package Size for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the -/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB. -#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed. +/// This configuration settings is used to optimize the communication performance with the +/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB, +/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB. +#ifndef HID_ENDPOINT //HID end points currently set limits to 64 +#define DAP_PACKET_SIZE 512 ///< Specifies Packet Size in bytes. +#else +#define DAP_PACKET_SIZE 64 ///< Specifies Packet Size in bytes. +#endif /// Maximum Package Buffers for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the +/// This configuration settings is used to optimize the communication performance with the /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB. #define DAP_PACKET_COUNT 5 ///< Buffers: 64 = Full-Speed, 4 = High-Speed. @@ -87,33 +101,48 @@ Provides definitions about: /// This information is returned by the command \ref DAP_Info as part of Capabilities. #define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available +/// USART Driver instance number for the UART SWO. +#define SWO_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#). + /// Maximum SWO UART Baudrate #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz /// Indicate that Manchester Serial Wire Output (SWO) trace is available. /// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available +#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available. /// SWO Trace Buffer Size. -#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n) +#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n). /// SWO Streaming Trace. #define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available. /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. #define TIMESTAMP_CLOCK 0U ///< Timestamp clock in Hz (0 = timestamps not supported). +// DAPLink: disabled because we use DWT for timestamps and M0+ doesn't have a DWT. + +/// Indicate that UART Communication Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART 0 ///< DAP UART: 1 = available, 0 = not available. + +/// USART Driver instance number for the UART Communication Port. +#define DAP_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#). +/// UART Receive Buffer Size. +#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n). + +/// UART Transmit Buffer Size. +#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n). + +/// Indicate that UART Communication via USB COM Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available. /// Debug Unit is connected to fixed Target Device. /// The Debug Unit may be part of an evaluation board and always connected to a fixed -/// known device. In this case a Device Vendor and Device Name string is stored which -/// may be used by the debugger or IDE to configure device parameters. -#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown; - -#if TARGET_DEVICE_FIXED -#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor -#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device -#endif +/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings +/// are stored and may be used by the debugger or IDE to configure device parameters. +#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown; ///@} diff --git a/source/hic_hal/maxim/max32620/DAP_config.h b/source/hic_hal/maxim/max32620/DAP_config.h index 8bc2cd30b..9dc1bace4 100644 --- a/source/hic_hal/maxim/max32620/DAP_config.h +++ b/source/hic_hal/maxim/max32620/DAP_config.h @@ -1,3 +1,24 @@ +/** + * @file DAP_config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2021, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + #ifndef __DAP_CONFIG_H__ #define __DAP_CONFIG_H__ @@ -6,10 +27,13 @@ \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information \ingroup DAP_ConfigIO_gr @{ -Provides definitions about: +Provides definitions about the hardware and configuration of the Debug Unit. + +This information includes: - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. + - Debug Unit Identification strings (Vendor, Product, Serial Number). - Debug Unit communication packet size. - - Debug Access Port communication mode (JTAG or SWD). + - Debug Access Port supported modes and settings (JTAG/SWD and SWO). - Optional information about a connected Target Device (for Evaluation Boards). */ @@ -26,10 +50,10 @@ Provides definitions about: /// Number of processor cycles for I/O Port write operations. /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors -/// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses +/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be /// required. -#define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles +#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. /// This information is returned by the command \ref DAP_Info as part of Capabilities. @@ -37,11 +61,11 @@ Provides definitions about: /// Indicate that JTAG communication mode is available at the Debug Port. /// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define DAP_JTAG 0 ///< JTAG Mode: 1 = available +#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available. /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port. /// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255. -#define DAP_JTAG_DEV_CNT 8 ///< Maximum number of JTAG devices on scan chain +#define DAP_JTAG_DEV_CNT 0 ///< Maximum number of JTAG devices on scan chain /// Default communication mode on the Debug Access Port. /// Used for the command \ref DAP_Connect when Port Default mode is selected. @@ -53,12 +77,17 @@ Provides definitions about: #define DAP_DEFAULT_SWJ_CLOCK 3000000 ///< Default SWD/JTAG clock frequency in Hz. /// Maximum Package Size for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the -/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB. -#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed. +/// This configuration settings is used to optimize the communication performance with the +/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB, +/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB. +#ifndef HID_ENDPOINT //HID end points currently set limits to 64 +#define DAP_PACKET_SIZE 512 ///< Specifies Packet Size in bytes. +#else +#define DAP_PACKET_SIZE 64 ///< Specifies Packet Size in bytes. +#endif /// Maximum Package Buffers for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the +/// This configuration settings is used to optimize the communication performance with the /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB. #define DAP_PACKET_COUNT 1 ///< Buffers: 64 = Full-Speed, 4 = High-Speed. @@ -67,15 +96,18 @@ Provides definitions about: /// This information is returned by the command \ref DAP_Info as part of Capabilities. #define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available +/// USART Driver instance number for the UART SWO. +#define SWO_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#). + /// Maximum SWO UART Baudrate #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz /// Indicate that Manchester Serial Wire Output (SWO) trace is available. /// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available +#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available. /// SWO Trace Buffer Size. -#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n) +#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n). /// SWO Streaming Trace. #define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available. @@ -83,16 +115,28 @@ Provides definitions about: /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. #define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported). +/// Indicate that UART Communication Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART 0 ///< DAP UART: 1 = available, 0 = not available. + +/// USART Driver instance number for the UART Communication Port. +#define DAP_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#). + +/// UART Receive Buffer Size. +#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n). + +/// UART Transmit Buffer Size. +#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n). + +/// Indicate that UART Communication via USB COM Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available. + /// Debug Unit is connected to fixed Target Device. /// The Debug Unit may be part of an evaluation board and always connected to a fixed -/// known device. In this case a Device Vendor and Device Name string is stored which -/// may be used by the debugger or IDE to configure device parameters. -#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown; - -#if TARGET_DEVICE_FIXED -#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor -#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device -#endif +/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings +/// are stored and may be used by the debugger or IDE to configure device parameters. +#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown; ///@} diff --git a/source/hic_hal/maxim/max32625/DAP_config.h b/source/hic_hal/maxim/max32625/DAP_config.h index afc67b81d..9a0b83a55 100644 --- a/source/hic_hal/maxim/max32625/DAP_config.h +++ b/source/hic_hal/maxim/max32625/DAP_config.h @@ -3,7 +3,7 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2021, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -27,10 +27,13 @@ \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information \ingroup DAP_ConfigIO_gr @{ -Provides definitions about: +Provides definitions about the hardware and configuration of the Debug Unit. + +This information includes: - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. + - Debug Unit Identification strings (Vendor, Product, Serial Number). - Debug Unit communication packet size. - - Debug Access Port communication mode (JTAG or SWD). + - Debug Access Port supported modes and settings (JTAG/SWD and SWO). - Optional information about a connected Target Device (for Evaluation Boards). */ @@ -50,7 +53,7 @@ Provides definitions about: /// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be /// required. -#define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0 +#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. /// This information is returned by the command \ref DAP_Info as part of Capabilities. @@ -74,12 +77,17 @@ Provides definitions about: #define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz. /// Maximum Package Size for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the -/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB. -#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed. +/// This configuration settings is used to optimize the communication performance with the +/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB, +/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB. +#ifndef HID_ENDPOINT //HID end points currently set limits to 64 +#define DAP_PACKET_SIZE 512 ///< Specifies Packet Size in bytes. +#else +#define DAP_PACKET_SIZE 64 ///< Specifies Packet Size in bytes. +#endif /// Maximum Package Buffers for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the +/// This configuration settings is used to optimize the communication performance with the /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB. #define DAP_PACKET_COUNT 4 ///< Buffers: 64 = Full-Speed, 4 = High-Speed. @@ -88,15 +96,18 @@ Provides definitions about: /// This information is returned by the command \ref DAP_Info as part of Capabilities. #define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available +/// USART Driver instance number for the UART SWO. +#define SWO_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#). + /// Maximum SWO UART Baudrate #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz /// Indicate that Manchester Serial Wire Output (SWO) trace is available. /// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available +#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available. /// SWO Trace Buffer Size. -#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n) +#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n). /// SWO Streaming Trace. #define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available. @@ -104,16 +115,28 @@ Provides definitions about: /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. #define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported). +/// Indicate that UART Communication Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART 0 ///< DAP UART: 1 = available, 0 = not available. + +/// USART Driver instance number for the UART Communication Port. +#define DAP_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#). + +/// UART Receive Buffer Size. +#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n). + +/// UART Transmit Buffer Size. +#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n). + +/// Indicate that UART Communication via USB COM Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available. + /// Debug Unit is connected to fixed Target Device. /// The Debug Unit may be part of an evaluation board and always connected to a fixed -/// known device. In this case a Device Vendor and Device Name string is stored which -/// may be used by the debugger or IDE to configure device parameters. -#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown; - -#if TARGET_DEVICE_FIXED -#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor -#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device -#endif +/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings +/// are stored and may be used by the debugger or IDE to configure device parameters. +#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown; ///@} diff --git a/source/hic_hal/nuvoton/m48ssidae/DAP_config.h b/source/hic_hal/nuvoton/m48ssidae/DAP_config.h index 76894260c..08c256b7f 100644 --- a/source/hic_hal/nuvoton/m48ssidae/DAP_config.h +++ b/source/hic_hal/nuvoton/m48ssidae/DAP_config.h @@ -3,7 +3,7 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2021, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -26,17 +26,19 @@ #include "cmsis_os2.h" #include "IO_Config.h" #include "uart.h" -//#include "debug_cm.h" -//#include "swd_host.h" + //************************************************************************************************** /** \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information \ingroup DAP_ConfigIO_gr @{ -Provides definitions about: +Provides definitions about the hardware and configuration of the Debug Unit. + +This information includes: - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. + - Debug Unit Identification strings (Vendor, Product, Serial Number). - Debug Unit communication packet size. - - Debug Access Port communication mode (JTAG or SWD). + - Debug Access Port supported modes and settings (JTAG/SWD and SWO). - Optional information about a connected Target Device (for Evaluation Boards). */ @@ -47,10 +49,10 @@ Provides definitions about: /// Number of processor cycles for I/O Port write operations. /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors -/// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses +/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be -/// requrired. -#define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0 +/// required. +#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. /// This information is returned by the command \ref DAP_Info as part of Capabilities. @@ -74,29 +76,41 @@ Provides definitions about: #define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz. /// Maximum Package Size for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the -/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB. -#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed. +/// This configuration settings is used to optimize the communication performance with the +/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB, +/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB. +#ifndef HID_ENDPOINT //HID end points currently set limits to 64 +#define DAP_PACKET_SIZE 512 ///< Specifies Packet Size in bytes. +#else +#define DAP_PACKET_SIZE 64 ///< Specifies Packet Size in bytes. +#endif /// Maximum Package Buffers for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the +/// This configuration settings is used to optimize the communication performance with the /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB. -#define DAP_PACKET_COUNT 64 ///< Buffers: 64 = Full-Speed, 4 = High-Speed. +#ifndef HID_ENDPOINT +#define DAP_PACKET_COUNT 4U ///< Buffers: 64 = Full-Speed, 4 = High-Speed. +#else +#define DAP_PACKET_COUNT 64U ///< Buffers: 64 = Full-Speed, 4 = High-Speed. +#endif /// Indicate that UART Serial Wire Output (SWO) trace is available. /// This information is returned by the command \ref DAP_Info as part of Capabilities. #define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available +/// USART Driver instance number for the UART SWO. +#define SWO_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#). + /// Maximum SWO UART Baudrate #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz /// Indicate that Manchester Serial Wire Output (SWO) trace is available. /// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available +#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available. /// SWO Trace Buffer Size. -#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n) +#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n). /// SWO Streaming Trace. #define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available. @@ -104,16 +118,28 @@ Provides definitions about: /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. #define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported). +/// Indicate that UART Communication Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART 0 ///< DAP UART: 1 = available, 0 = not available. + +/// USART Driver instance number for the UART Communication Port. +#define DAP_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#). + +/// UART Receive Buffer Size. +#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n). + +/// UART Transmit Buffer Size. +#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n). + +/// Indicate that UART Communication via USB COM Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available. + /// Debug Unit is connected to fixed Target Device. /// The Debug Unit may be part of an evaluation board and always connected to a fixed -/// known device. In this case a Device Vendor and Device Name string is stored which -/// may be used by the debugger or IDE to configure device parameters. -#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown; - -#if TARGET_DEVICE_FIXED -#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor -#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device -#endif +/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings +/// are stored and may be used by the debugger or IDE to configure device parameters. +#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown; ///@} diff --git a/source/hic_hal/nxp/lpc11u35/DAP_config.h b/source/hic_hal/nxp/lpc11u35/DAP_config.h index 71526202a..3b9d6ef49 100644 --- a/source/hic_hal/nxp/lpc11u35/DAP_config.h +++ b/source/hic_hal/nxp/lpc11u35/DAP_config.h @@ -3,7 +3,7 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2021, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -22,21 +22,23 @@ #ifndef __DAP_CONFIG_H__ #define __DAP_CONFIG_H__ +#include "IO_Config.h" //************************************************************************************************** /** \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information \ingroup DAP_ConfigIO_gr @{ -Provides definitions about: +Provides definitions about the hardware and configuration of the Debug Unit. + +This information includes: - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. + - Debug Unit Identification strings (Vendor, Product, Serial Number). - Debug Unit communication packet size. - - Debug Access Port communication mode (JTAG or SWD). + - Debug Access Port supported modes and settings (JTAG/SWD and SWO). - Optional information about a connected Target Device (for Evaluation Boards). */ -#include "IO_Config.h" - // Board configuration options // Configure JTAG option @@ -47,15 +49,15 @@ Provides definitions about: /// Processor Clock of the Cortex-M MCU used in the Debug Unit. /// This value is used to calculate the SWD/JTAG clock speed. -#define CPU_CLOCK 48000000 ///< Specifies the CPU Clock in Hz +#define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz /// Number of processor cycles for I/O Port write operations. /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors -/// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses +/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be /// required. -#define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0 +#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. /// This information is returned by the command \ref DAP_Info as part of Capabilities. @@ -66,7 +68,7 @@ Provides definitions about: /// Indicate that JTAG communication mode is available at the Debug Port. /// This information is returned by the command \ref DAP_Info as part of Capabilities. #ifndef DAP_JTAG -#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available +#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available. #endif /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port. @@ -79,7 +81,7 @@ Provides definitions about: #define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG. #elif (DAP_JTAG == 1) #define DAP_DEFAULT_PORT 2 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG. -#else +#else #error Must enable DAP_SWD and/or DAP_JTAG #endif @@ -89,12 +91,17 @@ Provides definitions about: #define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz. /// Maximum Package Size for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the -/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB. -#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed. +/// This configuration settings is used to optimize the communication performance with the +/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB, +/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB. +#ifndef HID_ENDPOINT //HID end points currently set limits to 64 +#define DAP_PACKET_SIZE 512 ///< Specifies Packet Size in bytes. +#else +#define DAP_PACKET_SIZE 64 ///< Specifies Packet Size in bytes. +#endif /// Maximum Package Buffers for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the +/// This configuration settings is used to optimize the communication performance with the /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB. #define DAP_PACKET_COUNT 1 ///< Buffers: 64 = Full-Speed, 4 = High-Speed. @@ -103,32 +110,48 @@ Provides definitions about: /// This information is returned by the command \ref DAP_Info as part of Capabilities. #define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available +/// USART Driver instance number for the UART SWO. +#define SWO_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#). + /// Maximum SWO UART Baudrate #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz /// Indicate that Manchester Serial Wire Output (SWO) trace is available. /// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available +#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available. /// SWO Trace Buffer Size. -#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n) +#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n). /// SWO Streaming Trace. #define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available. /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. -#define TIMESTAMP_CLOCK 0 //100000000U ///< Timestamp clock in Hz (0 = timestamps not supported). +#define TIMESTAMP_CLOCK 0U ///< Timestamp clock in Hz (0 = timestamps not supported). +// DAPLink: disabled because we use DWT for timestamps and M0 doesn't have a DWT. + +/// Indicate that UART Communication Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART 0 ///< DAP UART: 1 = available, 0 = not available. + +/// USART Driver instance number for the UART Communication Port. +#define DAP_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#). + +/// UART Receive Buffer Size. +#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n). + +/// UART Transmit Buffer Size. +#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n). + +/// Indicate that UART Communication via USB COM Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available. /// Debug Unit is connected to fixed Target Device. /// The Debug Unit may be part of an evaluation board and always connected to a fixed -/// known device. In this case a Device Vendor and Device Name string is stored which -/// may be used by the debugger or IDE to configure device parameters. -#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown; - -#if TARGET_DEVICE_FIXED -#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor -#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device -#endif +/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings +/// are stored and may be used by the debugger or IDE to configure device parameters. +#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown; ///@} diff --git a/source/hic_hal/nxp/lpc4322/DAP_config.h b/source/hic_hal/nxp/lpc4322/DAP_config.h index 25310eb4c..a79b5c63d 100644 --- a/source/hic_hal/nxp/lpc4322/DAP_config.h +++ b/source/hic_hal/nxp/lpc4322/DAP_config.h @@ -1,9 +1,9 @@ /** - * @file DAP_config.c + * @file DAP_config.h * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2021, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -22,20 +22,23 @@ #ifndef __DAP_CONFIG_H__ #define __DAP_CONFIG_H__ - +#include +#include "IO_Config.h" //************************************************************************************************** /** \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information \ingroup DAP_ConfigIO_gr @{ -Provides definitions about: +Provides definitions about the hardware and configuration of the Debug Unit. + +This information includes: - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. + - Debug Unit Identification strings (Vendor, Product, Serial Number). - Debug Unit communication packet size. - - Debug Access Port communication mode (JTAG or SWD). + - Debug Access Port supported modes and settings (JTAG/SWD and SWO). - Optional information about a connected Target Device (for Evaluation Boards). */ -#include "LPC43xx.h" // Debug Unit Cortex-M Processor Header File #include "lpc43xx_scu.h" typedef unsigned int BOOL; @@ -54,10 +57,10 @@ typedef unsigned int BOOL; /// Number of processor cycles for I/O Port write operations. /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors -/// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses +/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be /// required. -#define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0 +#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. /// This information is returned by the command \ref DAP_Info as part of Capabilities. @@ -81,12 +84,17 @@ typedef unsigned int BOOL; #define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz. /// Maximum Package Size for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the -/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB. -#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed. +/// This configuration settings is used to optimize the communication performance with the +/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB, +/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB. +#ifndef HID_ENDPOINT //HID end points currently set limits to 64 +#define DAP_PACKET_SIZE 512 ///< Specifies Packet Size in bytes. +#else +#define DAP_PACKET_SIZE 64 ///< Specifies Packet Size in bytes. +#endif /// Maximum Package Buffers for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the +/// This configuration settings is used to optimize the communication performance with the /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB. #define DAP_PACKET_COUNT 1 ///< Buffers: 64 = Full-Speed, 4 = High-Speed. @@ -95,15 +103,18 @@ typedef unsigned int BOOL; /// This information is returned by the command \ref DAP_Info as part of Capabilities. #define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available +/// USART Driver instance number for the UART SWO. +#define SWO_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#). + /// Maximum SWO UART Baudrate #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz /// Indicate that Manchester Serial Wire Output (SWO) trace is available. /// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available +#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available. /// SWO Trace Buffer Size. -#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n) +#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n). /// SWO Streaming Trace. #define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available. @@ -111,17 +122,28 @@ typedef unsigned int BOOL; /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. #define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported). +/// Indicate that UART Communication Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART 0 ///< DAP UART: 1 = available, 0 = not available. + +/// USART Driver instance number for the UART Communication Port. +#define DAP_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#). + +/// UART Receive Buffer Size. +#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n). + +/// UART Transmit Buffer Size. +#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n). + +/// Indicate that UART Communication via USB COM Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available. /// Debug Unit is connected to fixed Target Device. /// The Debug Unit may be part of an evaluation board and always connected to a fixed -/// known device. In this case a Device Vendor and Device Name string is stored which -/// may be used by the debugger or IDE to configure device parameters. -#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown; - -#if TARGET_DEVICE_FIXED -#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor -#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device -#endif +/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings +/// are stored and may be used by the debugger or IDE to configure device parameters. +#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown; ///@} @@ -132,44 +154,8 @@ typedef unsigned int BOOL; #define CCU_CLK_STAT_RUN (1UL << 0) // State of Reset Ouput Enable buffer -extern BOOL gpio_reset_pin_is_input; - -// Debug Port I/O Pins - -// SWCLK Pin P1_17: GPIO0[12] -#define PORT_SWCLK 0 -#define PIN_SWCLK_IN_BIT 12 -#define PIN_SWCLK (1<SET[PORT_##str] = PIN_##str -#define X_CLR(str) LPC_GPIO_PORT->CLR[PORT_##str] = PIN_##str -#define X_DIR_OUT(str) LPC_GPIO_PORT->DIR[PORT_##str] |= (PIN_##str) -#define X_DIR_IN(str) LPC_GPIO_PORT->DIR[PORT_##str] &= ~(PIN_##str) -#define X_BYTE(str) LPC_GPIO_PORT->B[(PORT_##str << 5) + PIN_##str##_IN_BIT] //************************************************************************************************** @@ -417,12 +403,12 @@ __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit) // release device hardware reset. (reset INPUT, reset oe LOW=INPUT) X_DIR_IN(nRESET); X_CLR(RESET_TXE); - gpio_reset_pin_is_input = __TRUE; + gpio_reset_pin_is_input = true; LPC_GPIO_PIN_INT->IST = 0x01; // ACK any pending edge interrupt LPC_GPIO_PIN_INT->SIENF |= 0x1; // Enable falling edge interrupt } else { // issue a device hardware reset. (reset OUTPUT+LOW, reset oe HIGH=OUTPUT) - gpio_reset_pin_is_input = __FALSE; + gpio_reset_pin_is_input = false; LPC_GPIO_PIN_INT->CIENF |= 0x1; // Disable falling edge interrupt LPC_GPIO_PIN_INT->IST = 0x01; // ACK any pending edge interrupt X_SET(RESET_TXE); diff --git a/source/hic_hal/nxp/lpc4322/IO_Config.h b/source/hic_hal/nxp/lpc4322/IO_Config.h index 7873cfce9..a5ac392b1 100644 --- a/source/hic_hal/nxp/lpc4322/IO_Config.h +++ b/source/hic_hal/nxp/lpc4322/IO_Config.h @@ -25,9 +25,47 @@ #define __IO_CONFIG_H__ #include "daplink.h" -#include "LPC43xx.h" +#include "device.h" // This GPIO configuration is only valid for the LPC4322 HIC COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC4322); +// Debug Port I/O Pins + +// SWCLK Pin P1_17: GPIO0[12] +#define PORT_SWCLK 0 +#define PIN_SWCLK_IN_BIT 12 +#define PIN_SWCLK (1<SET[PORT_##str] = PIN_##str +#define X_CLR(str) LPC_GPIO_PORT->CLR[PORT_##str] = PIN_##str +#define X_DIR_OUT(str) LPC_GPIO_PORT->DIR[PORT_##str] |= (PIN_##str) +#define X_DIR_IN(str) LPC_GPIO_PORT->DIR[PORT_##str] &= ~(PIN_##str) +#define X_BYTE(str) LPC_GPIO_PORT->B[(PORT_##str << 5) + PIN_##str##_IN_BIT] + + #endif diff --git a/source/hic_hal/nxp/lpc4322/gpio.c b/source/hic_hal/nxp/lpc4322/gpio.c index 489f6d579..953297227 100644 --- a/source/hic_hal/nxp/lpc4322/gpio.c +++ b/source/hic_hal/nxp/lpc4322/gpio.c @@ -19,6 +19,7 @@ * limitations under the License. */ +#include #include "LPC43xx.h" #include "lpc43xx_scu.h" #include "gpio.h" @@ -26,7 +27,7 @@ #include "DAP_config.h" // For the nRESET and RESET_TXE port/pin info #include "IO_Config.h" -BOOL gpio_reset_pin_is_input = __TRUE; +bool gpio_reset_pin_is_input = true; // Connected LED P1_1: GPIO0[8] #define LED_CONNECTED_PORT 0 diff --git a/source/hic_hal/nxp/lpc55xx/DAP_config.h b/source/hic_hal/nxp/lpc55xx/DAP_config.h index 7cb5c51ff..c5da0b66e 100644 --- a/source/hic_hal/nxp/lpc55xx/DAP_config.h +++ b/source/hic_hal/nxp/lpc55xx/DAP_config.h @@ -3,7 +3,7 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2020 Arm Limited, All Rights Reserved + * Copyright (c) 2009-2021, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -34,12 +34,18 @@ Provides definitions about the hardware and configuration of the Debug Unit. This information includes: - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. + - Debug Unit Identification strings (Vendor, Product, Serial Number). - Debug Unit communication packet size. - - Debug Access Port communication mode (JTAG or SWD). + - Debug Access Port supported modes and settings (JTAG/SWD and SWO). - Optional information about a connected Target Device (for Evaluation Boards). */ +#ifdef _RTE_ +#include "RTE_Components.h" +#include CMSIS_device_header +#else #include "device.h" // Debug Unit Cortex-M Processor Header File +#endif /// Processor Clock of the Cortex-M MCU used in the Debug Unit. /// This value is used to calculate the SWD/JTAG clock speed. @@ -75,16 +81,17 @@ This information includes: #define DAP_DEFAULT_SWJ_CLOCK 4000000U ///< Default SWD/JTAG clock frequency in Hz. /// Maximum Package Size for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the -/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB. +/// This configuration settings is used to optimize the communication performance with the +/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB, +/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB. #ifndef HID_ENDPOINT //HID end points currently set limits to 64 -#define DAP_PACKET_SIZE 512 ///< USB: 64 = Full-Speed, 512 = High-Speed. +#define DAP_PACKET_SIZE 512 ///< Specifies Packet Size in bytes. #else -#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 512 = High-Speed. +#define DAP_PACKET_SIZE 64 ///< Specifies Packet Size in bytes. #endif /// Maximum Package Buffers for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the +/// This configuration settings is used to optimize the communication performance with the /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB. #define DAP_PACKET_COUNT 4U ///< Buffers: 64 = Full-Speed, 4 = High-Speed. @@ -93,15 +100,19 @@ This information includes: /// This information is returned by the command \ref DAP_Info as part of Capabilities. #define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available +/// USART Driver instance number for the UART SWO. +#define SWO_UART_DRIVER 3 ///< USART Driver instance number (Driver_USART#). +// DAPLink: FC3 is used for the SWO UART. + /// Maximum SWO UART Baudrate #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz /// Indicate that Manchester Serial Wire Output (SWO) trace is available. /// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available +#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available. /// SWO Trace Buffer Size. -#define SWO_BUFFER_SIZE 8192U ///< SWO Trace Buffer Size in bytes (must be 2^n) +#define SWO_BUFFER_SIZE 8192U ///< SWO Trace Buffer Size in bytes (must be 2^n). /// SWO Streaming Trace. #define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available. @@ -109,19 +120,28 @@ This information includes: /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. #define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported). -#define SWO_USART_PORT 3 ///< FC3 is used for the SWO UART. +/// Indicate that UART Communication Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART 0 ///< DAP UART: 1 = available, 0 = not available. + +/// USART Driver instance number for the UART Communication Port. +#define DAP_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#). +/// UART Receive Buffer Size. +#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n). + +/// UART Transmit Buffer Size. +#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n). + +/// Indicate that UART Communication via USB COM Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available. /// Debug Unit is connected to fixed Target Device. /// The Debug Unit may be part of an evaluation board and always connected to a fixed -/// known device. In this case a Device Vendor and Device Name string is stored which -/// may be used by the debugger or IDE to configure device parameters. -#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown; - -#if TARGET_DEVICE_FIXED -#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor -#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device -#endif +/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings +/// are stored and may be used by the debugger or IDE to configure device parameters. +#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown; ///@} diff --git a/source/hic_hal/stm32/stm32f103xb/DAP_config.h b/source/hic_hal/stm32/stm32f103xb/DAP_config.h index ce250bccc..34013e77d 100644 --- a/source/hic_hal/stm32/stm32f103xb/DAP_config.h +++ b/source/hic_hal/stm32/stm32f103xb/DAP_config.h @@ -3,7 +3,7 @@ * @brief * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2021, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -22,22 +22,20 @@ #ifndef __DAP_CONFIG_H__ #define __DAP_CONFIG_H__ -#include "stm32f1xx.h" -#include "stdint.h" -#include "cmsis_os2.h" #include "IO_Config.h" -#include "uart.h" -//#include "debug_cm.h" -//#include "swd_host.h" + //************************************************************************************************** /** \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information \ingroup DAP_ConfigIO_gr @{ -Provides definitions about: +Provides definitions about the hardware and configuration of the Debug Unit. + +This information includes: - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. + - Debug Unit Identification strings (Vendor, Product, Serial Number). - Debug Unit communication packet size. - - Debug Access Port communication mode (JTAG or SWD). + - Debug Access Port supported modes and settings (JTAG/SWD and SWO). - Optional information about a connected Target Device (for Evaluation Boards). */ @@ -48,10 +46,10 @@ Provides definitions about: /// Number of processor cycles for I/O Port write operations. /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors -/// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses +/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be -/// requrired. -#define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0 +/// required. +#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. /// This information is returned by the command \ref DAP_Info as part of Capabilities. @@ -75,12 +73,17 @@ Provides definitions about: #define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz. /// Maximum Package Size for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the -/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB. -#define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed. +/// This configuration settings is used to optimize the communication performance with the +/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB, +/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB. +#ifndef HID_ENDPOINT //HID end points currently set limits to 64 +#define DAP_PACKET_SIZE 512 ///< Specifies Packet Size in bytes. +#else +#define DAP_PACKET_SIZE 64 ///< Specifies Packet Size in bytes. +#endif /// Maximum Package Buffers for Command and Response data. -/// This configuration settings is used to optimized the communication performance with the +/// This configuration settings is used to optimize the communication performance with the /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB. #define DAP_PACKET_COUNT 4 ///< Buffers: 64 = Full-Speed, 4 = High-Speed. @@ -89,15 +92,18 @@ Provides definitions about: /// This information is returned by the command \ref DAP_Info as part of Capabilities. #define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available +/// USART Driver instance number for the UART SWO. +#define SWO_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#). + /// Maximum SWO UART Baudrate #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz /// Indicate that Manchester Serial Wire Output (SWO) trace is available. /// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available +#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available. /// SWO Trace Buffer Size. -#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n) +#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n). /// SWO Streaming Trace. #define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available. @@ -105,17 +111,28 @@ Provides definitions about: /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. #define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported). +/// Indicate that UART Communication Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART 0 ///< DAP UART: 1 = available, 0 = not available. + +/// USART Driver instance number for the UART Communication Port. +#define DAP_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#). + +/// UART Receive Buffer Size. +#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n). + +/// UART Transmit Buffer Size. +#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n). + +/// Indicate that UART Communication via USB COM Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available. /// Debug Unit is connected to fixed Target Device. /// The Debug Unit may be part of an evaluation board and always connected to a fixed -/// known device. In this case a Device Vendor and Device Name string is stored which -/// may be used by the debugger or IDE to configure device parameters. -#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown; - -#if TARGET_DEVICE_FIXED -#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor -#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device -#endif +/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings +/// are stored and may be used by the debugger or IDE to configure device parameters. +#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown; ///@} From e97b46a5f43186edf3b2b89d6d015bacda3dcd70 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sat, 9 Oct 2021 18:12:08 -0500 Subject: [PATCH 324/617] CMSIS-DAP v2.1 board and target string support. - Add string fields to board and target structs. - Update dap_strings.h functions to return board and target strings when available. - Refactored code in dap_strings.h to use common return_dap_string() utility. --- source/daplink/cmsis-dap/dap_strings.h | 106 +++++++++++++------------ source/target/target_board.h | 8 +- source/target/target_config.h | 13 ++- 3 files changed, 72 insertions(+), 55 deletions(-) diff --git a/source/daplink/cmsis-dap/dap_strings.h b/source/daplink/cmsis-dap/dap_strings.h index ba89799bc..850ede31b 100644 --- a/source/daplink/cmsis-dap/dap_strings.h +++ b/source/daplink/cmsis-dap/dap_strings.h @@ -20,14 +20,39 @@ #include "cmsis_compiler.h" #include "info.h" +#include "util.h" +#include "target_board.h" + +#if !defined(CMSIS_DAP_PRODUCT_NAME) +#define CMSIS_DAP_PRODUCT_NAME "DAPLink" +#endif + +//! Maximum output buffer length of all these functions. +#define MAX_DAP_STR_LEN (60) + +//! @brief Utility to copy string to output buffer and return length. +//! +//! The source string is limited to the maximum output buffer size defined +//! by the MAX_DAP_STR_LEN macro. +static uint8_t return_dap_string(char *dst, const char *src) +{ + int length = MIN(MAX_DAP_STR_LEN, strlen(src) + 1); + memcpy(dst, src, length); + dst[MAX_DAP_STR_LEN - 1] = 0; // Ensure there's a terminating NULL. + return length; +} /** Get Vendor Name string. \param str Pointer to buffer to store the string (max 60 characters). \return String length (including terminating NULL character) or 0 (no string). */ __STATIC_INLINE uint8_t DAP_GetVendorString (char *str) { - (void)str; - return (0U); +#if defined(CMSIS_DAP_VENDOR_NAME) + return return_dap_string(str, CMSIS_DAP_VENDOR_NAME); +#else + (void)str; + return (0U); +#endif } /** Get Product Name string. @@ -35,8 +60,7 @@ __STATIC_INLINE uint8_t DAP_GetVendorString (char *str) { \return String length (including terminating NULL character) or 0 (no string). */ __STATIC_INLINE uint8_t DAP_GetProductString (char *str) { - (void)str; - return (0U); + return return_dap_string(str, CMSIS_DAP_PRODUCT_NAME); } /** Get Serial Number string. @@ -44,10 +68,7 @@ __STATIC_INLINE uint8_t DAP_GetProductString (char *str) { \return String length (including terminating NULL character) or 0 (no string). */ __STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) { - const char * data = info_get_unique_id(); - uint8_t length = (uint8_t)strlen(data) + 1; - memcpy(str, data, length); - return length; + return return_dap_string(str, info_get_unique_id()); } /** Get Target Device Vendor string. @@ -55,16 +76,12 @@ __STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) { \return String length (including terminating NULL character) or 0 (no string). */ __STATIC_INLINE uint8_t DAP_GetTargetDeviceVendorString (char *str) { -#if TARGET_FIXED != 0 - uint8_t len; - - strcpy(str, TargetDeviceVendor); - len = (uint8_t)(strlen(TargetDeviceVendor) + 1U); - return (len); -#else - (void)str; - return (0U); -#endif + if (g_board_info.target_cfg && g_board_info.target_cfg->target_vendor) { + return return_dap_string(str, g_board_info.target_cfg->target_vendor); + } + else { + return (0U); + } } /** Get Target Device Name string. @@ -72,16 +89,12 @@ __STATIC_INLINE uint8_t DAP_GetTargetDeviceVendorString (char *str) { \return String length (including terminating NULL character) or 0 (no string). */ __STATIC_INLINE uint8_t DAP_GetTargetDeviceNameString (char *str) { -#if TARGET_FIXED != 0 - uint8_t len; - - strcpy(str, TargetDeviceName); - len = (uint8_t)(strlen(TargetDeviceName) + 1U); - return (len); -#else - (void)str; - return (0U); -#endif + if (g_board_info.target_cfg && g_board_info.target_cfg->target_part_number) { + return return_dap_string(str, g_board_info.target_cfg->target_part_number); + } + else { + return (0U); + } } /** Get Target Board Vendor string. @@ -89,16 +102,12 @@ __STATIC_INLINE uint8_t DAP_GetTargetDeviceNameString (char *str) { \return String length (including terminating NULL character) or 0 (no string). */ __STATIC_INLINE uint8_t DAP_GetTargetBoardVendorString (char *str) { -#if TARGET_FIXED != 0 - uint8_t len; - - strcpy(str, TargetBoardVendor); - len = (uint8_t)(strlen(TargetBoardVendor) + 1U); - return (len); -#else - (void)str; - return (0U); -#endif + if (g_board_info.board_vendor) { + return return_dap_string(str, g_board_info.board_vendor); + } + else { + return (0U); + } } /** Get Target Board Name string. @@ -106,16 +115,12 @@ __STATIC_INLINE uint8_t DAP_GetTargetBoardVendorString (char *str) { \return String length (including terminating NULL character) or 0 (no string). */ __STATIC_INLINE uint8_t DAP_GetTargetBoardNameString (char *str) { -#if TARGET_FIXED != 0 - uint8_t len; - - strcpy(str, TargetBoardName); - len = (uint8_t)(strlen(TargetBoardName) + 1U); - return (len); -#else - (void)str; - return (0U); -#endif + if (g_board_info.board_name) { + return return_dap_string(str, g_board_info.board_name); + } + else { + return (0U); + } } /** Get Product Firmware Version string. @@ -123,8 +128,5 @@ __STATIC_INLINE uint8_t DAP_GetTargetBoardNameString (char *str) { \return String length (including terminating NULL character) or 0 (no string). */ __STATIC_INLINE uint8_t DAP_GetProductFirmwareVersionString (char *str) { - const char * data = info_get_version(); - uint8_t length = (uint8_t)strlen(data) + 1; - memcpy(str, data, length); - return length; + return return_dap_string(str, info_get_version()); } diff --git a/source/target/target_board.h b/source/target/target_board.h index 7ae102e0b..6b4476aa4 100644 --- a/source/target/target_board.h +++ b/source/target/target_board.h @@ -55,7 +55,7 @@ enum _board_info_flags { * by the device family. */ typedef struct board_info { - uint16_t info_version; /*!< Version number of the board info */ + uint16_t info_version; /*!< Version number of the board info */ uint16_t family_id; /*!< Use to select or identify target family from defined target family or custom ones */ char board_id[5]; /*!< 4-char board ID plus null terminator */ uint8_t _padding[3]; @@ -76,6 +76,12 @@ typedef struct board_info { uint8_t (*target_set_state)(target_state_t state); /*!< Boards can customize target debug states with precedence over target family */ uint32_t soft_reset_type; /*!< Boards can override software reset type to VECTRESET or SYSRESETREQ */ //@} + + //! @name CMSIS-DAP v2.1 board strings + //@{ + char *board_vendor; //!< Board vendor. Maximum 60 characters including terminal NULL. + char *board_name; //!< Board name. Maximum 60 characters including terminal NULL. + //@} } board_info_t; //! @brief Information describing the board on which DAPLink is running. diff --git a/source/target/target_config.h b/source/target/target_config.h index 6efcca4f4..49f689beb 100644 --- a/source/target/target_config.h +++ b/source/target/target_config.h @@ -30,9 +30,9 @@ //! @brief Current target configuration version. //! -//! - Version 0: Initial version. +//! - Version 1: Initial version. enum _target_config_version { - kTargetConfigVersion = 0, //!< The current board info version. + kTargetConfigVersion = 1, //!< The current board info version. }; //! This can vary from target to target and should be in the structure or flash blob @@ -71,6 +71,15 @@ typedef struct __attribute__((__packed__)) target_cfg { uint16_t rt_family_id; /*!< If assigned, this is a flexible family ID */ uint8_t erase_reset; /*!< Reset after performing an erase */ uint8_t pad; + + //! @name CMSIS-DAP v2.1 target strings + //@{ + char *target_vendor; /*!< Must match the Dvendor attribute value of the CMSIS DFP, excluding the + colon and vendor code suffix when present. Maximum 60 characters including + terminal NULL. */ + char *target_part_number; /*!< Part number of the target device. Must match the Dname attribute value + of the device's CMSIS DFP. Maximum 60 characters including terminal NULL. */ + //@} } target_cfg_t; extern target_cfg_t target_device; From e92f150c7517167aecc4c1297c7986d03e2c16c2 Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sat, 9 Oct 2021 18:12:50 -0500 Subject: [PATCH 325/617] Docs: add string customisation; cleanup PORT_TARGET_FAMILY.md. --- docs/PORT_TARGET_FAMILY.md | 160 ++--------------------------------- docs/string_customization.md | 51 +++++++++++ 2 files changed, 59 insertions(+), 152 deletions(-) create mode 100644 docs/string_customization.md diff --git a/docs/PORT_TARGET_FAMILY.md b/docs/PORT_TARGET_FAMILY.md index ec238e692..72cb8d82f 100644 --- a/docs/PORT_TARGET_FAMILY.md +++ b/docs/PORT_TARGET_FAMILY.md @@ -58,6 +58,7 @@ static uint8_t security_bits_set(uint32_t addr, uint8_t *data, uint32_t size) } const target_family_descriptor_t g_target_family = { + .version = kTargetFamilyVersion, .family_id = myFamilyID, .default_reset_type = kHardwareReset, .target_before_init_debug = target_before_init_debug, @@ -67,106 +68,9 @@ const target_family_descriptor_t g_target_family = { }; ``` -The target family api is located in `source/target/target_family.h` and target_reset file can customize the function apis according to the family specification. Family id is a combination of vendor id and an incrementing id. There are predefined family id stubs that can be used for generic reset types; kStub_HWReset_FamilyID, kStub_SWVectReset_FamilyID and kStub_SWSysReset_FamilyID. +The target family api is located in `source/target/target_family.h` and target_reset file can customize the function apis according to the family specification. Family id is a combination of vendor id and an incrementing id. There are predefined family id stubs that can be used for generic reset types; `kStub_HWReset_FamilyID`, `kStub_SWVectReset_FamilyID`, and `kStub_SWSysReset_FamilyID`. -```c -/** - * @file target_family.h - * @brief - * - * DAPLink Interface Firmware - * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef TARGET_FAMILY_H -#define TARGET_FAMILY_H - -#include -#include -#include "target_reset.h" - -#define VENDOR_TO_FAMILY(x, y) (x<<8 | y) - -typedef enum _reset_type { - kHardwareReset=1, - kSoftwareReset, -} reset_type_t; - -enum _vendor_ids { - kStub_VendorID = 0, - kNXP_VendorID = 11, - kTI_VendorID = 16, - kNordic_VendorID = 54, - kToshiba_VendorID = 92, - kRenesas_VendorID = 117, - kWiznet_VendorID = 122, - kRealtek_VendorID = 124, -}; - -typedef enum _family_id { - kStub_HWReset_FamilyID = VENDOR_TO_FAMILY(kStub_VendorID, 1), - kStub_SWVectReset_FamilyID = VENDOR_TO_FAMILY(kStub_VendorID, 2), - kStub_SWSysReset_FamilyID = VENDOR_TO_FAMILY(kStub_VendorID, 3), - kNXP_KinetisK_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 1), - kNXP_KinetisL_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 2), - kNXP_Mimxrt_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 3), - kNXP_RapidIot_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 4), - kNXP_KinetisK32W_FamilyID = VENDOR_TO_FAMILY(kNXP_VendorID, 5), - kNordic_Nrf51_FamilyID = VENDOR_TO_FAMILY(kNordic_VendorID, 1), - kNordic_Nrf52_FamilyID = VENDOR_TO_FAMILY(kNordic_VendorID, 2), - kRealtek_Rtl8195am_FamilyID = VENDOR_TO_FAMILY(kRealtek_VendorID, 1), - kTI_Cc3220sf_FamilyID = VENDOR_TO_FAMILY(kTI_VendorID, 1), - kToshiba_Tz_FamilyID = VENDOR_TO_FAMILY(kToshiba_VendorID, 1), - kWiznet_W7500_FamilyID = VENDOR_TO_FAMILY(kWiznet_VendorID, 1), - kRenesas_FamilyID = VENDOR_TO_FAMILY(kRenesas_VendorID, 1), -} family_id_t; - -typedef struct target_family_descriptor { - uint16_t family_id; /*!< Use to select or identify target family from defined target family or custom ones */ - reset_type_t default_reset_type; /*!< Target family can select predefined reset from kHardwareReset and kSoftwareReset */ - uint32_t soft_reset_type; /*!< Families can override software reset type to VECTRESET or SYSRESETREQ */ - void (*target_before_init_debug)(void); /*!< Target dependant function before debug initialization */ - void (*prerun_target_config)(void); /*!< Target specific initialization */ - uint8_t (*target_unlock_sequence)(void); /*!< Unlock targets that can enter lock state */ - uint8_t (*security_bits_set)(uint32_t addr, uint8_t *data, uint32_t size); /*!< Check security bits in the programmable flash region */ - uint8_t (*target_set_state)(TARGET_RESET_STATE state); /*!< Families can customize target debug states in target_reset.h */ - void (*swd_set_target_reset)(uint8_t asserted); /*!< Families can customize how to send reset to the target */ - uint8_t (*validate_bin_nvic)(const uint8_t *buf); /*!< Validate a bin file to be flash by drag and drop */ - uint8_t (*validate_hexfile)(const uint8_t *buf); /*!< Validate a hex file to be flash by drag and drop */ -} target_family_descriptor_t; - -extern const target_family_descriptor_t *g_target_family; - -#ifdef __cplusplus -extern "C" { -#endif - -void init_family(void); -uint8_t target_family_valid(void); -uint8_t target_set_state(TARGET_RESET_STATE state); -void swd_set_target_reset(uint8_t asserted); - -#ifdef __cplusplus -} -#endif - -#endif -``` - -A flash algorithm blob is needed to program the target MCUs internal (or external) flash memory. This blob contains position independent functions for erasing, reading and writing to the flash controller. Flash algorithm blobs are created from the [FlashAlgo project.](https://github.com/mbedmicro/FlashAlgo) An example blob is shown below and would be added to `source/family///flash_blob.c` +A flash algorithm blob is needed to program the target MCUs internal (or external) flash memory. This blob contains position independent functions for erasing, reading and writing to the flash controller. Flash algorithm blobs are created from the [FlashAlgo project.](https://github.com/pyocd/FlashAlgo). An example blob is shown below and would be added to `source/family///flash_blob.c` ```c /** @@ -193,28 +97,7 @@ A flash algorithm blob is needed to program the target MCUs internal (or externa #include "flash_blob.h" static const uint32_t targetname_blob[] = { - 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, - 0x4770ba40, 0x4770bac0, 0x4c0cb510, 0xf04068a0, 0x60a00001, 0x301af246, 0xf44f6560, 0x60e07040, - 0x20012100, 0xf83ef000, 0x65612100, 0xf02168a1, 0x60a10101, 0xbf182800, 0xbd102001, 0x400c0000, - 0x4684b510, 0xf44f2300, 0xf8505180, 0x1f092b04, 0x1c52d002, 0xe001d0f9, 0xd0131c50, 0x68a04c0c, - 0x0001f040, 0xf8c460a0, 0x2001c010, 0x200260e0, 0x210060e0, 0xf0002001, 0x4603f815, 0xf02068a0, - 0x60a00001, 0xbf142b00, 0x20002001, 0x0000bd10, 0x400c0000, 0xf6414902, 0x63c83071, 0x47702000, - 0x400c0000, 0x4b14b410, 0xc050f8df, 0x201cf8dc, 0x0f16f012, 0xf8dcd014, 0xf0200008, 0xf8cc0005, - 0xf0120008, 0xbf1e0f02, 0x0001f06f, 0x4770bc10, 0x0f04f012, 0xf04fbf1e, 0xbc1030ff, 0xe0074770, - 0x428a4002, 0xbc10d102, 0x47702000, 0xd1dd1e5b, 0xf06fbc10, 0x47700002, 0x00989680, 0x400c0000, - 0x4df0e92d, 0x1cc84604, 0x0603f020, 0x46904859, 0xf0416881, 0x60810101, 0xd9732e07, 0x0f07f014, - 0xf8d8d011, 0x61041000, 0x60c22201, 0x21086181, 0x210060c1, 0xf7ff4610, 0x2800ffb5, 0x1d24d17e, - 0x0810f108, 0x484b1f36, 0xf0416881, 0x60810104, 0xbf882e07, 0x0a02f06f, 0xf504d966, 0x46015080, - 0x010bf36f, 0x42b11b09, 0x4635bf8e, 0x000bf36f, 0xf0151b05, 0xbf180f04, 0x46471f2d, 0x20012100, - 0xff90f7ff, 0xd13b2800, 0xe0e8f8df, 0x4010f8ce, 0xf8ce2001, 0xf857000c, 0xf8ce0b04, 0xf8570018, - 0xf8ce0b04, 0x20080018, 0x000cf8ce, 0x0208f1a5, 0xd9332a07, 0x0b08f04f, 0x46dc482f, 0x101cf8de, - 0x0f16f011, 0xf8ded012, 0xf0200008, 0xf8ce0005, 0xf0110008, 0xbf180f02, 0x0001f06f, 0xf011d10f, - 0xbf180f04, 0x30fff04f, 0xe007d109, 0x010bea01, 0xd1014561, 0xe0022000, 0xd1df1e40, 0xb1104650, - 0xe00bb9e0, 0xf857e01c, 0xf8ce0b04, 0xf8570018, 0xf8ce0b04, 0x3a080018, 0xd8cb2a07, 0xeb081b76, - 0x442c0885, 0xd8982e07, 0x20012100, 0xff3af7ff, 0x4810b920, 0xf0216881, 0xe0000104, 0x6081e00f, - 0x480cb186, 0x1000f8d8, 0x22016104, 0x618160c2, 0x60c12108, 0x46102100, 0xff24f7ff, 0x2001b110, - 0x8df0e8bd, 0x68814803, 0x0101f021, 0x20006081, 0x8df0e8bd, 0x400c0000, 0x00989680, 0x68814803, - 0x0105f021, 0x20006081, 0x00004770, 0x400c0000, 0x00000000, + 0xE00ABE00, /* ... */, 0x00000000, }; /** @@ -283,48 +166,21 @@ The last required file is the target MCU description file `source/family//< #include "flash_blob.c" target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x00000000, .flash_regions[0].end = 0x00200000, .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, + .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1fff0000, .ram_regions[0].end = 0x20030000, }; ``` -Complete target configuration api is located in `source/target/target_config.h` -```c -enum _region_flags { - kRegionIsDefault = (1 << 0), //out of bounds regions will use the same flash algo if this is set - kRegionIsSecure = (1 << 1) -}; +Complete target configuration api is located in `source/target/target_config.h` -typedef struct region_info { - uint32_t start; - uint32_t end; - uint32_t flags; - uint8_t alias_index; /*! Date: Sat, 9 Oct 2021 18:12:37 -0500 Subject: [PATCH 326/617] Set a number of board and target strings. - Targets: AmbiqMicro, Arm, NXP, Maxim, Nordic. - Boards: Ambiq, NXP, Maxim, micro:bit, plus several others. --- source/board/artemis_dk.c | 4 +++- source/board/ep_kairos.c | 6 ++++-- source/board/ff_lpc546xx.c | 4 +++- source/board/frdmk20dx.c | 2 ++ source/board/frdmk22f.c | 2 ++ source/board/frdmk28f.c | 2 ++ source/board/frdmk64f.c | 2 ++ source/board/frdmk66f.c | 5 +++-- source/board/frdmk82f.c | 6 ++++-- source/board/frdmke15z.c | 2 ++ source/board/frdmkl02z.c | 2 ++ source/board/frdmkl05z.c | 2 ++ source/board/frdmkl25z.c | 2 ++ source/board/frdmkl26z.c | 2 ++ source/board/frdmkl27z.c | 2 ++ source/board/frdmkl28z.c | 2 ++ source/board/frdmkl43z.c | 2 ++ source/board/frdmkl46z.c | 2 ++ source/board/frdmkl82z.c | 2 ++ source/board/frdmkw24d.c | 3 ++- source/board/frdmkw41z.c | 5 +++-- source/board/hani_iot.c | 3 ++- source/board/hvpke18f.c | 2 ++ source/board/lpc4088dm.c | 2 ++ source/board/lpc4088qsb.c | 2 ++ source/board/lpc54114xpresso.c | 2 ++ source/board/lpc54608xpresso.c | 2 ++ source/board/lpc55S69xpresso.c | 5 +++-- source/board/lpc812xpresso.c | 2 ++ source/board/lpc824xpresso.c | 2 ++ source/board/max32620fthr.c | 4 ++++ source/board/max32625mbed.c | 4 ++++ source/board/max32630fthr.c | 4 ++++ source/board/max32660evsys.c | 8 +++++--- source/board/max32666fthr.c | 4 +++- source/board/microbit.c | 2 ++ source/board/microbitv2/microbitv2.c | 2 ++ source/board/mimxrt1020_evk.c | 2 ++ source/board/mimxrt1050_evk.c | 2 ++ source/board/mini_iot_lpc54018.c | 6 ++++-- source/board/musca_a.c | 4 +++- source/board/musca_b.c | 4 +++- source/board/scci824.c | 8 ++++---- source/board/ssci1114.c | 5 +++-- source/board/twrke18f.c | 2 ++ source/board/twrkl28z72m.c | 2 ++ source/family/ambiq/ama3b1kk/target.c | 2 ++ source/family/arm/musca_a/target.c | 2 ++ source/family/arm/musca_b/target.c | 3 +++ source/family/freescale/k20dx/target.c | 2 ++ source/family/freescale/k28f/target.c | 4 +++- source/family/freescale/k64f/target.c | 2 ++ source/family/freescale/k66f/target.c | 2 ++ source/family/freescale/k82f/target.c | 4 +++- source/family/freescale/ke15z/target.c | 2 ++ source/family/freescale/ke18f/target.c | 2 ++ source/family/freescale/kl02z/target.c | 2 ++ source/family/freescale/kl05z/target.c | 2 ++ source/family/freescale/kl25z/target.c | 2 ++ source/family/freescale/kl26z/target.c | 2 ++ source/family/freescale/kl27z/target.c | 2 ++ source/family/freescale/kl28z/target.c | 4 +++- source/family/freescale/kl43z/target.c | 2 ++ source/family/freescale/kl46z/target.c | 2 ++ source/family/freescale/kl82z/target.c | 4 +++- source/family/freescale/kw24d/target.c | 2 ++ source/family/freescale/kw41z/target.c | 2 ++ source/family/freescale/mimxrt1020_spi_flash/target.c | 2 ++ source/family/freescale/mimxrt1050_hyper_flash/target.c | 4 +++- source/family/freescale/mimxrt1050_spi_flash/target.c | 4 +++- source/family/maxim/max32620/target.c | 2 ++ source/family/maxim/max32625/target.c | 2 ++ source/family/maxim/max32630/target.c | 3 +++ source/family/maxim/max32660/target.c | 2 ++ source/family/maxim/max32666/target.c | 2 ++ source/family/nordic/nrf51822/target_nrf51.c | 4 ++++ source/family/nordic/nrf52/target.c | 8 ++++++++ source/family/nxp/lpc1114/target.c | 2 ++ source/family/nxp/lpc1768/target.c | 2 ++ source/family/nxp/lpc4088/target_lpc4088dm.c | 4 +++- source/family/nxp/lpc4088/target_lpc4088qsb.c | 4 +++- source/family/nxp/lpc54018/target.c | 2 ++ source/family/nxp/lpc54114/target.c | 2 ++ source/family/nxp/lpc54608/target.c | 2 ++ source/family/nxp/lpc55S6X/target.c | 2 ++ source/family/nxp/lpc812/target.c | 2 ++ source/family/nxp/lpc824/target.c | 2 ++ 87 files changed, 218 insertions(+), 36 deletions(-) diff --git a/source/board/artemis_dk.c b/source/board/artemis_dk.c index 13153e7a2..c91de44ba 100644 --- a/source/board/artemis_dk.c +++ b/source/board/artemis_dk.c @@ -1,6 +1,6 @@ /** * @file microbit.c - * @brief board ID for the BBC Microbit board + * @brief board ID for the SparkFun Artemis Development Kit * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -69,4 +69,6 @@ const board_info_t g_board_info = { .daplink_target_url = "https://www.sparkfun.com/artemis", .prerun_board_config = prerun_board_config, .target_cfg = &target_device, + .board_vendor = "SparkFun", + .board_name = "Artemis Development Kit", }; diff --git a/source/board/ep_kairos.c b/source/board/ep_kairos.c index 3774bcf0d..159e4d6bb 100644 --- a/source/board/ep_kairos.c +++ b/source/board/ep_kairos.c @@ -1,6 +1,6 @@ /** - * @file lpc55S69xpresso.c - * @brief board ID for the NXP LPC54608Xpresso board + * @file ep_kairos.c + * @brief board ID for the Embedded Planet Kairos board * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -28,4 +28,6 @@ const board_info_t g_board_info = { .family_id = CREATE_FAMILY_ID(kNXP_VendorID, 0), //ID not maching the predefined family ids .flags = kEnablePageErase, .target_cfg = &target_device, + .board_vendor = "Embedded Planet", + .board_name = "Kairos", }; diff --git a/source/board/ff_lpc546xx.c b/source/board/ff_lpc546xx.c index c205b5989..89d5a511d 100644 --- a/source/board/ff_lpc546xx.c +++ b/source/board/ff_lpc546xx.c @@ -1,6 +1,6 @@ /** * @file ff_lpc546xx.c - * @brief board ID for the NXP LPC54608Xpresso board + * @brief board ID for the L-Tek FF-LPC546XX board * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -30,4 +30,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "FF-LPC546XX", .daplink_target_url = "https://os.mbed.com/platforms/L-TEK-FF-LPC546XX", .target_cfg = &target_device, + .board_vendor = "L-Tek", + .board_name = "FF-LPC546XX", }; diff --git a/source/board/frdmk20dx.c b/source/board/frdmk20dx.c index f600465de..a141ebc3e 100644 --- a/source/board/frdmk20dx.c +++ b/source/board/frdmk20dx.c @@ -27,4 +27,6 @@ const board_info_t g_board_info = { .board_id = "0230", .family_id = kNXP_KinetisK_FamilyID, .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "FRDM-K20D50M", }; diff --git a/source/board/frdmk22f.c b/source/board/frdmk22f.c index b4934a09e..58365bd3d 100644 --- a/source/board/frdmk22f.c +++ b/source/board/frdmk22f.c @@ -27,4 +27,6 @@ const board_info_t g_board_info = { .board_id = "0231", .family_id = kNXP_KinetisK_FamilyID, .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "FRDM-K22F", }; diff --git a/source/board/frdmk28f.c b/source/board/frdmk28f.c index dbac9fd6a..41d995c39 100644 --- a/source/board/frdmk28f.c +++ b/source/board/frdmk28f.c @@ -30,4 +30,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "FRDM-K28FD", .daplink_target_url = "http://www.nxp.com/frdm-k28f", .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "FRDM-K28F", }; diff --git a/source/board/frdmk64f.c b/source/board/frdmk64f.c index fd88d8e4a..151e85e52 100644 --- a/source/board/frdmk64f.c +++ b/source/board/frdmk64f.c @@ -28,4 +28,6 @@ const board_info_t g_board_info = { .family_id = kNXP_KinetisK_FamilyID, .flags = kEnablePageErase, .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "FRDM-K64F", }; diff --git a/source/board/frdmk66f.c b/source/board/frdmk66f.c index e0e1a8cee..1f75a21c2 100755 --- a/source/board/frdmk66f.c +++ b/source/board/frdmk66f.c @@ -1,6 +1,6 @@ /** * @file frdmk66f.c - * @brief board ID for the NXP FRDM-K64F board + * @brief board ID for the NXP FRDM-K66F board * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -31,5 +31,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "FRDM-K66FD", .daplink_target_url = "http://www.nxp.com/frdm-k66f", .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "FRDM-K66F", }; - diff --git a/source/board/frdmk82f.c b/source/board/frdmk82f.c index 07bc5cccb..a241600f9 100644 --- a/source/board/frdmk82f.c +++ b/source/board/frdmk82f.c @@ -1,6 +1,6 @@ /** - * @file frdmk66f.c - * @brief board ID for the NXP FRDM-K64F board + * @file frdmk82f.c + * @brief board ID for the NXP FRDM-K82F board * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -30,4 +30,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "FRDM-K82FD", .daplink_target_url = "http://www.nxp.com/frdm-k82f", .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "FRDM-K82F", }; diff --git a/source/board/frdmke15z.c b/source/board/frdmke15z.c index caa70f5fa..c0ef4e460 100644 --- a/source/board/frdmke15z.c +++ b/source/board/frdmke15z.c @@ -30,4 +30,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "FRDM-KE15ZD", .daplink_target_url = "http://www.nxp.com/frdm-ke15z", .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "FRDM-KE15Z", }; diff --git a/source/board/frdmkl02z.c b/source/board/frdmkl02z.c index 818d5135a..12fd5c293 100644 --- a/source/board/frdmkl02z.c +++ b/source/board/frdmkl02z.c @@ -27,4 +27,6 @@ const board_info_t g_board_info = { .board_id = "0204", .family_id = kNXP_KinetisL_FamilyID, .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "FRDM-KL02Z", }; diff --git a/source/board/frdmkl05z.c b/source/board/frdmkl05z.c index e77d4a514..423697b03 100644 --- a/source/board/frdmkl05z.c +++ b/source/board/frdmkl05z.c @@ -27,4 +27,6 @@ const board_info_t g_board_info = { .board_id = "0210", .family_id = kNXP_KinetisL_FamilyID, .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "FRDM-KL05Z", }; diff --git a/source/board/frdmkl25z.c b/source/board/frdmkl25z.c index a04b47102..45ae49ee8 100644 --- a/source/board/frdmkl25z.c +++ b/source/board/frdmkl25z.c @@ -27,4 +27,6 @@ const board_info_t g_board_info = { .board_id = "0200", .family_id = kNXP_KinetisL_FamilyID, .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "FRDM-KL25Z", }; diff --git a/source/board/frdmkl26z.c b/source/board/frdmkl26z.c index ae132dedb..3f5144d29 100644 --- a/source/board/frdmkl26z.c +++ b/source/board/frdmkl26z.c @@ -27,4 +27,6 @@ const board_info_t g_board_info = { .board_id = "0260", .family_id = kNXP_KinetisL_FamilyID, .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "FRDM-KL26Z", }; diff --git a/source/board/frdmkl27z.c b/source/board/frdmkl27z.c index 62484510c..e7039f70e 100644 --- a/source/board/frdmkl27z.c +++ b/source/board/frdmkl27z.c @@ -30,4 +30,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "FRDM-KL27ZD", .daplink_target_url = "http://www.nxp.com/frdm-kl27z", .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "FRDM-KL27Z", }; diff --git a/source/board/frdmkl28z.c b/source/board/frdmkl28z.c index adac17d80..df79ac2d4 100644 --- a/source/board/frdmkl28z.c +++ b/source/board/frdmkl28z.c @@ -30,4 +30,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "FRDM-KL28ZD", .daplink_target_url = "http://www.nxp.com/frdm-kl28z", .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "FRDM-KL28Z", }; diff --git a/source/board/frdmkl43z.c b/source/board/frdmkl43z.c index 5c46e0d33..ca9d3d7b4 100644 --- a/source/board/frdmkl43z.c +++ b/source/board/frdmkl43z.c @@ -30,4 +30,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "FRDM-KL43ZD", .daplink_target_url = "http://www.nxp.com/frdm-kl43z", .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "FRDM-KL43Z", }; diff --git a/source/board/frdmkl46z.c b/source/board/frdmkl46z.c index 4b973328e..fcbbbac37 100644 --- a/source/board/frdmkl46z.c +++ b/source/board/frdmkl46z.c @@ -27,4 +27,6 @@ const board_info_t g_board_info = { .board_id = "0220", .family_id = kNXP_KinetisL_FamilyID, .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "FRDM-KL46Z", }; diff --git a/source/board/frdmkl82z.c b/source/board/frdmkl82z.c index 087bbe36c..cfdef4f57 100644 --- a/source/board/frdmkl82z.c +++ b/source/board/frdmkl82z.c @@ -30,4 +30,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "FRDM-KL82Z", .daplink_target_url = "http://www.nxp.com/frdm-kl82z", .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "FRDM-KL82Z", }; diff --git a/source/board/frdmkw24d.c b/source/board/frdmkw24d.c index a3d5193db..3f4fb2476 100644 --- a/source/board/frdmkw24d.c +++ b/source/board/frdmkw24d.c @@ -30,5 +30,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "FRDM-KW24D", .daplink_target_url = "http://www.nxp.com/frdm-kw24d", .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "FRDM-KW24D", }; - diff --git a/source/board/frdmkw41z.c b/source/board/frdmkw41z.c index 6d331b0a6..8321e6607 100644 --- a/source/board/frdmkw41z.c +++ b/source/board/frdmkw41z.c @@ -1,6 +1,6 @@ /** * @file frdmkw41z.c - * @brief board ID for the NXP FRDM-KW24F board + * @brief board ID for the NXP FRDM-KW41Z board * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -30,5 +30,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "FRDM-KW41Z", .daplink_target_url = "http://www.nxp.com/frdm-kw41z", .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "FRDM-KW41Z", }; - diff --git a/source/board/hani_iot.c b/source/board/hani_iot.c index d353d18a3..242f26a31 100644 --- a/source/board/hani_iot.c +++ b/source/board/hani_iot.c @@ -31,5 +31,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "HANI_IOT", .daplink_target_url = "https://os.mbed.com/platforms/HANI-IOT/", .target_cfg = &target_device, + .board_vendor = "Arrow", + .board_name = "HANI-IOT", }; - diff --git a/source/board/hvpke18f.c b/source/board/hvpke18f.c index 7436ee4cf..909456b1f 100644 --- a/source/board/hvpke18f.c +++ b/source/board/hvpke18f.c @@ -30,4 +30,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "HVP-KE18FD", .daplink_target_url = "http://www.nxp.com/hvp-ke18f", .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "HVP-KE18F", }; diff --git a/source/board/lpc4088dm.c b/source/board/lpc4088dm.c index 3da3b09c9..aca69cf25 100644 --- a/source/board/lpc4088dm.c +++ b/source/board/lpc4088dm.c @@ -27,4 +27,6 @@ const board_info_t g_board_info = { .board_id = "1062", .family_id = CREATE_FAMILY_ID(kNXP_VendorID, 0), //custom .target_cfg = &target_device, + .board_vendor = "Embedded Artists", + .board_name = "LPC4088 Display Module", }; diff --git a/source/board/lpc4088qsb.c b/source/board/lpc4088qsb.c index cc345dbf3..cf91e2219 100644 --- a/source/board/lpc4088qsb.c +++ b/source/board/lpc4088qsb.c @@ -27,4 +27,6 @@ const board_info_t g_board_info = { .board_id = "1060", .family_id = CREATE_FAMILY_ID(kNXP_VendorID, 0), //custom .target_cfg = &target_device, + .board_vendor = "Embedded Artists", + .board_name = "LPC4088 QuickStart Board", }; diff --git a/source/board/lpc54114xpresso.c b/source/board/lpc54114xpresso.c index e8a807abb..c8c0a7eb8 100644 --- a/source/board/lpc54114xpresso.c +++ b/source/board/lpc54114xpresso.c @@ -30,4 +30,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "LPC54114", .daplink_target_url = "https://os.mbed.com/platforms/LPCXpresso54114/", .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "LPC54114Xpresso", }; diff --git a/source/board/lpc54608xpresso.c b/source/board/lpc54608xpresso.c index 5c753fb8f..44aab182d 100644 --- a/source/board/lpc54608xpresso.c +++ b/source/board/lpc54608xpresso.c @@ -30,4 +30,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "LPC546XX", .daplink_target_url = "https://os.mbed.com/platforms/LPCXpresso54608/", .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "LPC54608Xpresso", }; diff --git a/source/board/lpc55S69xpresso.c b/source/board/lpc55S69xpresso.c index a743721e6..1603188e4 100644 --- a/source/board/lpc55S69xpresso.c +++ b/source/board/lpc55S69xpresso.c @@ -1,6 +1,6 @@ /** * @file lpc55S69xpresso.c - * @brief board ID for the NXP LPC54608Xpresso board + * @brief board ID for the NXP LPCXpresso55S69 board * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -31,5 +31,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "LPC55S69", .daplink_target_url = "https://os.mbed.com/platforms/LPCXpresso55S69/", .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "LPCXpresso55S69", }; - diff --git a/source/board/lpc812xpresso.c b/source/board/lpc812xpresso.c index 9eb02a633..d484a7654 100644 --- a/source/board/lpc812xpresso.c +++ b/source/board/lpc812xpresso.c @@ -27,4 +27,6 @@ const board_info_t g_board_info = { .board_id = "1050", .family_id = kStub_HWReset_FamilyID, .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "LPC812Xpresso", }; diff --git a/source/board/lpc824xpresso.c b/source/board/lpc824xpresso.c index 176254adc..0c03deff5 100644 --- a/source/board/lpc824xpresso.c +++ b/source/board/lpc824xpresso.c @@ -27,4 +27,6 @@ const board_info_t g_board_info = { .board_id = "0824", .family_id = kStub_HWReset_FamilyID, .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "LPC824Xpresso", }; diff --git a/source/board/max32620fthr.c b/source/board/max32620fthr.c index ac818e050..babfc86c0 100644 --- a/source/board/max32620fthr.c +++ b/source/board/max32620fthr.c @@ -28,4 +28,8 @@ const board_info_t g_board_info = { .family_id = kMaxim_MAX3262X_FamilyID, .flags = kEnablePageErase, .target_cfg = &target_device, + .daplink_url_name = "MAX32620HTM", + .daplink_target_url = "http://www.maximintegrated.com/max32620fthr", + .board_vendor = "Maxim Integrated", + .board_name = "MAX32620FTHR", }; diff --git a/source/board/max32625mbed.c b/source/board/max32625mbed.c index 895be7eab..d7c02a3c1 100644 --- a/source/board/max32625mbed.c +++ b/source/board/max32625mbed.c @@ -28,4 +28,8 @@ const board_info_t g_board_info = { .family_id = kStub_HWReset_FamilyID, .flags = kEnablePageErase, .target_cfg = &target_device, + .daplink_url_name = "MAX32625HTM", + .daplink_target_url = "http://www.maximintegrated.com/max32625mbed", + .board_vendor = "Maxim Integrated", + .board_name = "MAX32625MBED", }; diff --git a/source/board/max32630fthr.c b/source/board/max32630fthr.c index f42917228..3407f43a3 100644 --- a/source/board/max32630fthr.c +++ b/source/board/max32630fthr.c @@ -28,4 +28,8 @@ const board_info_t g_board_info = { .family_id = kMaxim_MAX3262X_FamilyID, .flags = kEnablePageErase, .target_cfg = &target_device, + .daplink_url_name = "MAX32620HTM", + .daplink_target_url = "http://www.maximintegrated.com/max32630fthr", + .board_vendor = "Maxim Integrated", + .board_name = "MAX32630FTHR", }; diff --git a/source/board/max32660evsys.c b/source/board/max32660evsys.c index 8fb685050..0bf97b10d 100644 --- a/source/board/max32660evsys.c +++ b/source/board/max32660evsys.c @@ -1,6 +1,6 @@ /** * @file max32660evsys.c - * @brief board ID for the Maxim Integrated's MAX32660EVSYS + * @brief board ID for the Maxim Integrated's MAX32660-EVSYS * * DAPLink Interface Firmware * @@ -21,7 +21,7 @@ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Except as contained in this notice, the name of Maxim Integrated @@ -46,5 +46,7 @@ const board_info_t g_board_info = { .flags = kEnablePageErase, .target_cfg = &target_device, .daplink_url_name = "MAX32660HTM", - .daplink_target_url = "http://www.maximintegrated.com/max32660", + .daplink_target_url = "http://www.maximintegrated.com/max32660-evsys", + .board_vendor = "Maxim Integrated", + .board_name = "MAX32660-EVSYS", }; diff --git a/source/board/max32666fthr.c b/source/board/max32666fthr.c index 785aa5764..629d18e00 100644 --- a/source/board/max32666fthr.c +++ b/source/board/max32666fthr.c @@ -1,6 +1,6 @@ /** * @file max32666fthr.c - * @brief board ID for the Maxim Integrated's max32666fthr + * @brief board ID for the Maxim Integrated's MAX32666FTHR * * DAPLink Interface Firmware * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved @@ -30,4 +30,6 @@ const board_info_t g_board_info = { .target_cfg = &target_device, .daplink_url_name = "MAX32666HTM", .daplink_target_url = "http://www.maximintegrated.com/max32666fthr", + .board_vendor = "Maxim Integrated", + .board_name = "MAX32666FTHR", }; diff --git a/source/board/microbit.c b/source/board/microbit.c index a0a16240b..a3e0b46dc 100644 --- a/source/board/microbit.c +++ b/source/board/microbit.c @@ -88,4 +88,6 @@ const board_info_t g_board_info = { .daplink_target_url = "https://microbit.org/device/?id=@B&v=@V", .prerun_board_config = prerun_board_config, .target_cfg = &target_device_nrf51822_16, + .board_vendor = "Micro:bit Educational Foundation", + .board_name = "BBC micro:bit V1", }; diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 5f5d7bdaa..188fbbb29 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -573,4 +573,6 @@ const board_info_t g_board_info = { .daplink_target_url = "https://microbit.org/device/?id=@B&v=@V", .prerun_board_config = prerun_board_config, .target_cfg = &target_device_nrf52833, + .board_vendor = "Micro:bit Educational Foundation", + .board_name = "BBC micro:bit V2", }; diff --git a/source/board/mimxrt1020_evk.c b/source/board/mimxrt1020_evk.c index a500a30cc..137a945da 100644 --- a/source/board/mimxrt1020_evk.c +++ b/source/board/mimxrt1020_evk.c @@ -31,4 +31,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "RT1020-EVK", .daplink_target_url = "http://www.nxp.com/imxrt1020evk", .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "MIMXRT1020-EVK", }; diff --git a/source/board/mimxrt1050_evk.c b/source/board/mimxrt1050_evk.c index f18f45de3..1a497123a 100644 --- a/source/board/mimxrt1050_evk.c +++ b/source/board/mimxrt1050_evk.c @@ -30,4 +30,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "RT1050-EVK", .daplink_target_url = "http://www.nxp.com/imxrt1050evk", .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "MIMXRT1050-EVKB", }; diff --git a/source/board/mini_iot_lpc54018.c b/source/board/mini_iot_lpc54018.c index 01e1995b5..43b051012 100644 --- a/source/board/mini_iot_lpc54018.c +++ b/source/board/mini_iot_lpc54018.c @@ -1,6 +1,6 @@ /** - * @file iotmodule_lpc54018.c - * @brief board ID for the NXP LPC54608Xpresso board + * @file mini_iot_lpc54018.c + * @brief board ID for the NXP LPC54018 IoT Module board * * DAPLink Interface Firmware * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved @@ -30,4 +30,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "MINI-54018", .daplink_target_url = "https://os.mbed.com/platforms/LPC54018IoTModule/", .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "LPC54018 IoT Module", }; diff --git a/source/board/musca_a.c b/source/board/musca_a.c index 1d0f6db02..d55915266 100644 --- a/source/board/musca_a.c +++ b/source/board/musca_a.c @@ -1,6 +1,6 @@ /** * @file musca_a.c - * @brief board ID for the ARM MUSCA A board + * @brief board ID for the ARM MUSCA A1 board * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -92,4 +92,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "MBED ", .target_cfg = &target_device, .prerun_board_config = prerun_board_config, + .board_vendor = "ARM", + .board_name = "Musca", }; diff --git a/source/board/musca_b.c b/source/board/musca_b.c index 38659de23..8d4df02ad 100644 --- a/source/board/musca_b.c +++ b/source/board/musca_b.c @@ -1,6 +1,6 @@ /** * @file musca_b.c - * @brief board ID for the ARM MUSCA B board + * @brief board ID for the ARM MUSCA B1 board * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -100,4 +100,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "MBED ", .target_cfg = &target_device, .prerun_board_config = prerun_board_config, + .board_vendor = "ARM", + .board_name = "Musca_B1", }; diff --git a/source/board/scci824.c b/source/board/scci824.c index 8aaf9ebb0..dda696744 100644 --- a/source/board/scci824.c +++ b/source/board/scci824.c @@ -1,6 +1,6 @@ /** - * @file ss824.c - * @brief board ID for the Switch Science LPC824 board + * @file scci824.c + * @brief board ID for the Switch Science mbed LPC824 board * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -28,6 +28,6 @@ const board_info_t g_board_info = { .family_id = kStub_HWReset_FamilyID, .daplink_drive_name = "MBED ", .target_cfg = &target_device, + .board_vendor = "Switch Science", + .board_name = "mbed LPC824", }; - - diff --git a/source/board/ssci1114.c b/source/board/ssci1114.c index cef0a732c..55a88be97 100644 --- a/source/board/ssci1114.c +++ b/source/board/ssci1114.c @@ -1,6 +1,6 @@ /** * @file ssci1114.c - * @brief board ID for the Switch Science LPC1114 board + * @brief board ID for the Switch Science mbed LPC1114FN28 board * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -28,5 +28,6 @@ const board_info_t g_board_info = { .family_id = kStub_HWReset_FamilyID, .daplink_drive_name = "MBED ", .target_cfg = &target_device, + .board_vendor = "Switch Science", + .board_name = "mbed LPC1114FN28", }; - diff --git a/source/board/twrke18f.c b/source/board/twrke18f.c index 41cc92c88..963437b3f 100644 --- a/source/board/twrke18f.c +++ b/source/board/twrke18f.c @@ -30,4 +30,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "TWR-KE18FD", .daplink_target_url = "http://www.nxp.com/twr-ke18f", .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "TWR-KE18F", }; diff --git a/source/board/twrkl28z72m.c b/source/board/twrkl28z72m.c index 0004462e5..7728124e6 100644 --- a/source/board/twrkl28z72m.c +++ b/source/board/twrkl28z72m.c @@ -30,4 +30,6 @@ const board_info_t g_board_info = { .daplink_drive_name = "TWR-KL28ZD", .daplink_target_url = "http://www.nxp.com/twr-kl28z72m", .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "TWR-KL28Z72M", }; diff --git a/source/family/ambiq/ama3b1kk/target.c b/source/family/ambiq/ama3b1kk/target.c index 599a717d7..89a1bccd1 100644 --- a/source/family/ambiq/ama3b1kk/target.c +++ b/source/family/ambiq/ama3b1kk/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *)&flash, .ram_regions[0].start = 0x10000000, .ram_regions[0].end = 0x10060000, + .target_vendor = "AmbiqMicro", + .target_part_number = "AMA3B1KK-KBR", }; diff --git a/source/family/arm/musca_a/target.c b/source/family/arm/musca_a/target.c index 28dcee445..c34f35890 100644 --- a/source/family/arm/musca_a/target.c +++ b/source/family/arm/musca_a/target.c @@ -61,4 +61,6 @@ target_cfg_t target_device = { .ram_regions[0].end = (MUSCA_A_NS_RAM_START + MUSCA_A_RAM_SIZE), .ram_regions[1].start = (MUSCA_A_S_RAM_START), .ram_regions[1].end = (MUSCA_A_S_RAM_START + MUSCA_A_RAM_SIZE), + .target_vendor = "ARM", + .target_part_number = "Musca", }; diff --git a/source/family/arm/musca_b/target.c b/source/family/arm/musca_b/target.c index 0eafe1f08..e15b4c149 100644 --- a/source/family/arm/musca_b/target.c +++ b/source/family/arm/musca_b/target.c @@ -79,4 +79,7 @@ target_cfg_t target_device = { .ram_regions[0].end = (MUSCA_B_NS_RAM_START + MUSCA_B_RAM_SIZE), .ram_regions[1].start = (MUSCA_B_S_RAM_START), .ram_regions[1].end = (MUSCA_B_S_RAM_START + MUSCA_B_RAM_SIZE), + + .target_vendor = "ARM", + .target_part_number = "Musca_B1", }; diff --git a/source/family/freescale/k20dx/target.c b/source/family/freescale/k20dx/target.c index 4f31e1e0e..dedf9a665 100644 --- a/source/family/freescale/k20dx/target.c +++ b/source/family/freescale/k20dx/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFF8000, .ram_regions[0].end = 0x20008000, + .target_vendor = "NXP", + .target_part_number = "MK20DX128xxx5", }; diff --git a/source/family/freescale/k28f/target.c b/source/family/freescale/k28f/target.c index 1ea39b3a6..96c6b6a33 100644 --- a/source/family/freescale/k28f/target.c +++ b/source/family/freescale/k28f/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the k66f + * @brief Target information for the k28f * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFC0000, .ram_regions[0].end = 0x20040000, + .target_vendor = "NXP", + .target_part_number = "MK28FN2M0VMI15", }; diff --git a/source/family/freescale/k64f/target.c b/source/family/freescale/k64f/target.c index 4558f465b..62c8be9e1 100644 --- a/source/family/freescale/k64f/target.c +++ b/source/family/freescale/k64f/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1fff0000, .ram_regions[0].end = 0x20030000, + .target_vendor = "NXP", + .target_part_number = "MK64FN1M0VLL12", }; diff --git a/source/family/freescale/k66f/target.c b/source/family/freescale/k66f/target.c index 5d1b6775c..e7254deda 100644 --- a/source/family/freescale/k66f/target.c +++ b/source/family/freescale/k66f/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1fff0000, .ram_regions[0].end = 0x20030000, + .target_vendor = "NXP", + .target_part_number = "MK66FN2M0VMD18", }; diff --git a/source/family/freescale/k82f/target.c b/source/family/freescale/k82f/target.c index b0fa3d7fe..4283e330b 100644 --- a/source/family/freescale/k82f/target.c +++ b/source/family/freescale/k82f/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the k66f + * @brief Target information for the k82f * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFF0000, .ram_regions[0].end = 0x20030000, + .target_vendor = "NXP", + .target_part_number = "MK82FN256VLL15", }; diff --git a/source/family/freescale/ke15z/target.c b/source/family/freescale/ke15z/target.c index 4688275e5..0df1b8b9e 100644 --- a/source/family/freescale/ke15z/target.c +++ b/source/family/freescale/ke15z/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFFE000, .ram_regions[0].end = 0x20006000, + .target_vendor = "NXP", + .target_part_number = "MKE15Z256VLL7", }; diff --git a/source/family/freescale/ke18f/target.c b/source/family/freescale/ke18f/target.c index c96d51151..e8035b756 100644 --- a/source/family/freescale/ke18f/target.c +++ b/source/family/freescale/ke18f/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFF8000, .ram_regions[0].end = 0x20008000, + .target_vendor = "NXP", + .target_part_number = "MKE18F512VLL16", }; diff --git a/source/family/freescale/kl02z/target.c b/source/family/freescale/kl02z/target.c index 3984c7a1e..4c2757c5a 100644 --- a/source/family/freescale/kl02z/target.c +++ b/source/family/freescale/kl02z/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFFFC00, .ram_regions[0].end = 0x20000C00, + .target_vendor = "NXP", + .target_part_number = "MKL02Z32VFM4", }; diff --git a/source/family/freescale/kl05z/target.c b/source/family/freescale/kl05z/target.c index 02d1f0c02..4fb2b3e15 100644 --- a/source/family/freescale/kl05z/target.c +++ b/source/family/freescale/kl05z/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFFFC00, .ram_regions[0].end = 0x20000C00, + .target_vendor = "NXP", + .target_part_number = "MKL05Z32xxx4", }; diff --git a/source/family/freescale/kl25z/target.c b/source/family/freescale/kl25z/target.c index 94f316af0..9194bf6e4 100644 --- a/source/family/freescale/kl25z/target.c +++ b/source/family/freescale/kl25z/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFF0000, .ram_regions[0].end = 0x20004000, + .target_vendor = "NXP", + .target_part_number = "MKL25Z128xxx4", }; diff --git a/source/family/freescale/kl26z/target.c b/source/family/freescale/kl26z/target.c index cb2761d90..73c2615c3 100644 --- a/source/family/freescale/kl26z/target.c +++ b/source/family/freescale/kl26z/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFF0000, .ram_regions[0].end = 0x20004000, + .target_vendor = "NXP", + .target_part_number = "MKL26Z128VLH4", }; diff --git a/source/family/freescale/kl27z/target.c b/source/family/freescale/kl27z/target.c index 8fad952f4..a33f2cd48 100644 --- a/source/family/freescale/kl27z/target.c +++ b/source/family/freescale/kl27z/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFFF000, .ram_regions[0].end = 0x20003000, + .target_vendor = "NXP", + .target_part_number = "MKL27Z64VLH4", }; diff --git a/source/family/freescale/kl28z/target.c b/source/family/freescale/kl28z/target.c index 8bffa7a40..e6997681c 100644 --- a/source/family/freescale/kl28z/target.c +++ b/source/family/freescale/kl28z/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the kl46z + * @brief Target information for the kl28z * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFF8000, .ram_regions[0].end = 0x20018000, + .target_vendor = "NXP", + .target_part_number = "MKL28Z512VLL7", }; diff --git a/source/family/freescale/kl43z/target.c b/source/family/freescale/kl43z/target.c index cecb824e1..ff77a28b7 100644 --- a/source/family/freescale/kl43z/target.c +++ b/source/family/freescale/kl43z/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1fffe000, .ram_regions[0].end = 0x20006000, + .target_vendor = "NXP", + .target_part_number = "MKL28Z512VLL7", }; diff --git a/source/family/freescale/kl46z/target.c b/source/family/freescale/kl46z/target.c index 9a4c9e6b6..d5d9fbf3d 100644 --- a/source/family/freescale/kl46z/target.c +++ b/source/family/freescale/kl46z/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFFE000, .ram_regions[0].end = 0x20006000, + .target_vendor = "NXP", + .target_part_number = "MKL46Z256VLL4", }; diff --git a/source/family/freescale/kl82z/target.c b/source/family/freescale/kl82z/target.c index 2c985a5e2..134512abc 100644 --- a/source/family/freescale/kl82z/target.c +++ b/source/family/freescale/kl82z/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the kl46z + * @brief Target information for the kl82z * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFFA000, .ram_regions[0].end = 0x20012000, + .target_vendor = "NXP", + .target_part_number = "MKL82Z128VLK7", }; diff --git a/source/family/freescale/kw24d/target.c b/source/family/freescale/kw24d/target.c index 607a02f39..457d3f7e2 100644 --- a/source/family/freescale/kw24d/target.c +++ b/source/family/freescale/kw24d/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFF8000, .ram_regions[0].end = 0x20008000, + .target_vendor = "NXP", + .target_part_number = "MKW24D512xxx5", }; diff --git a/source/family/freescale/kw41z/target.c b/source/family/freescale/kw41z/target.c index 6f18a8071..13fb71e89 100644 --- a/source/family/freescale/kw41z/target.c +++ b/source/family/freescale/kw41z/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x1FFF8000, .ram_regions[0].end = 0x20018000, + .target_vendor = "NXP", + .target_part_number = "MKW41Z512xxx4", }; diff --git a/source/family/freescale/mimxrt1020_spi_flash/target.c b/source/family/freescale/mimxrt1020_spi_flash/target.c index 64a4871ed..0e9ae5a7f 100644 --- a/source/family/freescale/mimxrt1020_spi_flash/target.c +++ b/source/family/freescale/mimxrt1020_spi_flash/target.c @@ -36,4 +36,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20000000 + MB(64), + .target_vendor = "NXP", + .target_part_number = "MIMXRT1021DAG5A", }; diff --git a/source/family/freescale/mimxrt1050_hyper_flash/target.c b/source/family/freescale/mimxrt1050_hyper_flash/target.c index 0e890faa5..e36390f98 100644 --- a/source/family/freescale/mimxrt1050_hyper_flash/target.c +++ b/source/family/freescale/mimxrt1050_hyper_flash/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the i.MXRT1050 + * @brief Target information for the i.MXRT1050 (HyperFlash) * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20000000 + MB(64), + .target_vendor = "NXP", + .target_part_number = "MIMXRT1052DVL6A", }; diff --git a/source/family/freescale/mimxrt1050_spi_flash/target.c b/source/family/freescale/mimxrt1050_spi_flash/target.c index 0e890faa5..f63df0435 100644 --- a/source/family/freescale/mimxrt1050_spi_flash/target.c +++ b/source/family/freescale/mimxrt1050_spi_flash/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the i.MXRT1050 + * @brief Target information for the i.MXRT1050 (QSPI Flash) * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20000000 + MB(64), + .target_vendor = "NXP", + .target_part_number = "MIMXRT1052DVL6A", }; diff --git a/source/family/maxim/max32620/target.c b/source/family/maxim/max32620/target.c index 51e67accc..1492ec6f0 100644 --- a/source/family/maxim/max32620/target.c +++ b/source/family/maxim/max32620/target.c @@ -34,4 +34,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20000000 + KB(256), + .target_vendor = "Maxim", + .target_part_number = "MAX32620", }; diff --git a/source/family/maxim/max32625/target.c b/source/family/maxim/max32625/target.c index 349e2f71c..acc2c1281 100644 --- a/source/family/maxim/max32625/target.c +++ b/source/family/maxim/max32625/target.c @@ -34,4 +34,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20028000, + .target_vendor = "Maxim", + .target_part_number = "MAX32625", }; diff --git a/source/family/maxim/max32630/target.c b/source/family/maxim/max32630/target.c index 8cfd1cb9f..8a00dfe5f 100644 --- a/source/family/maxim/max32630/target.c +++ b/source/family/maxim/max32630/target.c @@ -34,4 +34,7 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20000000 + KB(512), + // No CMSIS Pack for MAX32630 + // .target_vendor = "Maxim", + // .target_part_number = "MAX32630", }; diff --git a/source/family/maxim/max32660/target.c b/source/family/maxim/max32660/target.c index cebbd3ae0..520245933 100644 --- a/source/family/maxim/max32660/target.c +++ b/source/family/maxim/max32660/target.c @@ -51,4 +51,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20000000 + KB(96), + .target_vendor = "Maxim", + .target_part_number = "MAX32660", }; diff --git a/source/family/maxim/max32666/target.c b/source/family/maxim/max32666/target.c index b9524f370..0fb8f989b 100644 --- a/source/family/maxim/max32666/target.c +++ b/source/family/maxim/max32666/target.c @@ -33,4 +33,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20000000 + KB(560), + .target_vendor = "Maxim", + .target_part_number = "MAX32666", }; diff --git a/source/family/nordic/nrf51822/target_nrf51.c b/source/family/nordic/nrf51822/target_nrf51.c index ff965c2a2..a0844fe18 100644 --- a/source/family/nordic/nrf51822/target_nrf51.c +++ b/source/family/nordic/nrf51822/target_nrf51.c @@ -36,6 +36,8 @@ target_cfg_t target_device_nrf51822_16 = { .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20004000, .erase_reset = 1, + .target_vendor = "NordicSemiconductor", + .target_part_number = "nRF51822_xxAA", }; // target information for model with 32 KB RAM @@ -50,4 +52,6 @@ target_cfg_t target_device_nrf51822_32 = { .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20008000, .erase_reset = 1, + .target_vendor = "NordicSemiconductor", + .target_part_number = "nRF51822_xxAA", }; diff --git a/source/family/nordic/nrf52/target.c b/source/family/nordic/nrf52/target.c index a9a1dd595..fccc1ed2e 100644 --- a/source/family/nordic/nrf52/target.c +++ b/source/family/nordic/nrf52/target.c @@ -36,6 +36,8 @@ target_cfg_t target_device_nrf52 = { .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20008000, .erase_reset = 1, + .target_vendor = "NordicSemiconductor", + .target_part_number = "nRF52832_xxAB", }; // target information for nRF52832 with 64 KB RAM / 512 KB Flash @@ -50,6 +52,8 @@ target_cfg_t target_device_nrf52_64 = { .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20010000, .erase_reset = 1, + .target_vendor = "NordicSemiconductor", + .target_part_number = "nRF52832_xxAA", }; // target information for nRF52833 with 128 KB RAM / 512 KB Flash @@ -64,6 +68,8 @@ target_cfg_t target_device_nrf52833 = { .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20020000, .erase_reset = 1, + .target_vendor = "NordicSemiconductor", + .target_part_number = "nRF52833_xxAA", }; // target information for nRF52840 with 256 KB RAM / 1024 KB Flash @@ -78,4 +84,6 @@ target_cfg_t target_device_nrf52840 = { .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20040000, .erase_reset = 1, + .target_vendor = "NordicSemiconductor", + .target_part_number = "nRF52840_xxAA", }; diff --git a/source/family/nxp/lpc1114/target.c b/source/family/nxp/lpc1114/target.c index 2bf0e5119..641102ac4 100644 --- a/source/family/nxp/lpc1114/target.c +++ b/source/family/nxp/lpc1114/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x10000000, .ram_regions[0].end = 0x10001000, + .target_vendor = "NXP", + .target_part_number = "LPC1114FN28/102", }; diff --git a/source/family/nxp/lpc1768/target.c b/source/family/nxp/lpc1768/target.c index 0aaef122c..637b86866 100644 --- a/source/family/nxp/lpc1768/target.c +++ b/source/family/nxp/lpc1768/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x10000000, .ram_regions[0].end = 0x10008000, + .target_vendor = "NXP", + .target_part_number = "LPC1768", }; diff --git a/source/family/nxp/lpc4088/target_lpc4088dm.c b/source/family/nxp/lpc4088/target_lpc4088dm.c index 9379c08de..6ccf7dd77 100644 --- a/source/family/nxp/lpc4088/target_lpc4088dm.c +++ b/source/family/nxp/lpc4088/target_lpc4088dm.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the lpc4088 + * @brief Target information for the lpc4088dm * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x10000000, .ram_regions[0].end = 0x10010000, + .target_vendor = "NXP", + .target_part_number = "LPC4088FET208", }; diff --git a/source/family/nxp/lpc4088/target_lpc4088qsb.c b/source/family/nxp/lpc4088/target_lpc4088qsb.c index 104022900..24ef65aef 100644 --- a/source/family/nxp/lpc4088/target_lpc4088qsb.c +++ b/source/family/nxp/lpc4088/target_lpc4088qsb.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the lpc4088 + * @brief Target information for the lpc4088qsb * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x10000000, .ram_regions[0].end = 0x10010000, + .target_vendor = "NXP", + .target_part_number = "LPC4088FET208", }; diff --git a/source/family/nxp/lpc54018/target.c b/source/family/nxp/lpc54018/target.c index 5532b5c91..47170cee8 100644 --- a/source/family/nxp/lpc54018/target.c +++ b/source/family/nxp/lpc54018/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x00000000, .ram_regions[0].end = 0x00030000, + .target_vendor = "NXP", + .target_part_number = "LPC54018JET180", }; diff --git a/source/family/nxp/lpc54114/target.c b/source/family/nxp/lpc54114/target.c index 968281218..db01f84e3 100644 --- a/source/family/nxp/lpc54114/target.c +++ b/source/family/nxp/lpc54114/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20028000, + .target_vendor = "NXP", + .target_part_number = "LPC54114J256BD64", }; diff --git a/source/family/nxp/lpc54608/target.c b/source/family/nxp/lpc54608/target.c index e00a6c9f7..617337770 100644 --- a/source/family/nxp/lpc54608/target.c +++ b/source/family/nxp/lpc54608/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20028000, + .target_vendor = "NXP", + .target_part_number = "LPC54608J512ET180", }; diff --git a/source/family/nxp/lpc55S6X/target.c b/source/family/nxp/lpc55S6X/target.c index c7f256c03..7a48aa7f4 100644 --- a/source/family/nxp/lpc55S6X/target.c +++ b/source/family/nxp/lpc55S6X/target.c @@ -40,4 +40,6 @@ target_cfg_t target_device = { .ram_regions[0].end = 0x20044000, .ram_regions[1].start = 0x30000000, .ram_regions[1].end = 0x30000000 + 0x00044000, + .target_vendor = "NXP", + .target_part_number = "LPC55S69JBD100", }; diff --git a/source/family/nxp/lpc812/target.c b/source/family/nxp/lpc812/target.c index 03f8a4def..1c6847882 100644 --- a/source/family/nxp/lpc812/target.c +++ b/source/family/nxp/lpc812/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x10000000, .ram_regions[0].end = 0x10001000, + .target_vendor = "NXP", + .target_part_number = "LPC812M101JDH20", }; diff --git a/source/family/nxp/lpc824/target.c b/source/family/nxp/lpc824/target.c index 6c809411c..efcd0f87d 100644 --- a/source/family/nxp/lpc824/target.c +++ b/source/family/nxp/lpc824/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x10000000, .ram_regions[0].end = 0x10002000, + .target_vendor = "NXP", + .target_part_number = "LPC824M201JHI33", }; From d073af1c2d6096c7fcaada2e9efbe19f0739d976 Mon Sep 17 00:00:00 2001 From: "Sadik.Ozer" Date: Tue, 19 Oct 2021 09:22:45 +0300 Subject: [PATCH 327/617] Update licence to Apache V2 Signed-off-by: Sadik.Ozer --- source/board/max32660evsys.c | 41 +++++++---------------- source/family/maxim/max32660/flash_blob.c | 41 +++++++---------------- source/family/maxim/max32660/target.c | 41 +++++++---------------- 3 files changed, 36 insertions(+), 87 deletions(-) diff --git a/source/board/max32660evsys.c b/source/board/max32660evsys.c index 0bf97b10d..820edb4e4 100644 --- a/source/board/max32660evsys.c +++ b/source/board/max32660evsys.c @@ -3,38 +3,21 @@ * @brief board ID for the Maxim Integrated's MAX32660-EVSYS * * DAPLink Interface Firmware + * Copyright (c) 2009-2021, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 * - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: + * http://www.apache.org/licenses/LICENSE-2.0 * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* -*/ + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ #include "target_family.h" #include "target_board.h" diff --git a/source/family/maxim/max32660/flash_blob.c b/source/family/maxim/max32660/flash_blob.c index f4a4f6c6a..fcd87f6d4 100644 --- a/source/family/maxim/max32660/flash_blob.c +++ b/source/family/maxim/max32660/flash_blob.c @@ -3,38 +3,21 @@ * @brief Flash algorithm for the MAX32660 * * DAPLink Interface Firmware + * Copyright (c) 2009-2021, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 * - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: + * http://www.apache.org/licenses/LICENSE-2.0 * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* -*/ + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ #include "flash_blob.h" diff --git a/source/family/maxim/max32660/target.c b/source/family/maxim/max32660/target.c index 520245933..bae08dfc8 100644 --- a/source/family/maxim/max32660/target.c +++ b/source/family/maxim/max32660/target.c @@ -3,38 +3,21 @@ * @brief Target information for the MAX32660 * * DAPLink Interface Firmware + * Copyright (c) 2009-2021, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 * - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: + * http://www.apache.org/licenses/LICENSE-2.0 * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. - ******************************************************************************* -*/ + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ #include "target_config.h" From baa0310e032cb0b166abbf733d8357b52c976cd2 Mon Sep 17 00:00:00 2001 From: ozersa <46590392+ozersa@users.noreply.github.com> Date: Wed, 20 Oct 2021 17:13:31 +0300 Subject: [PATCH 328/617] max32625_hic: Optimization of GPIO drive (#875) Signed-off-by: Sadik.Ozer --- source/hic_hal/maxim/max32625/DAP_config.h | 90 +++++---------------- source/hic_hal/maxim/max32625/IO_Config.h | 5 ++ source/hic_hal/maxim/max32625/gpio.c | 93 ++++++++-------------- 3 files changed, 59 insertions(+), 129 deletions(-) diff --git a/source/hic_hal/maxim/max32625/DAP_config.h b/source/hic_hal/maxim/max32625/DAP_config.h index 9a0b83a55..596969818 100644 --- a/source/hic_hal/maxim/max32625/DAP_config.h +++ b/source/hic_hal/maxim/max32625/DAP_config.h @@ -207,33 +207,20 @@ Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: */ __STATIC_INLINE void PORT_SWD_SETUP (void) { - uint32_t out_mode; - // Ensure that the GPIO clock is enabled if (MXC_CLKMAN->sys_clk_ctrl_6_gpio == MXC_V_CLKMAN_CLK_SCALE_DISABLED) { MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_V_CLKMAN_CLK_SCALE_DIV_1; } // Initial state - MXC_GPIO->out_val[swclk_port] |= (1 << swclk_pin); - MXC_GPIO->out_val[swdio_port] |= (1 << swdio_pin); - MXC_GPIO->out_val[nreset_port] |= (1 << nreset_pin); + MXC_GPIO_SETBIT(swclk_port, swclk_pin); + MXC_GPIO_SETBIT(swdio_port, swdio_pin); + MXC_GPIO_SETBIT(nreset_port, nreset_pin); // Output mode - out_mode = MXC_GPIO->out_mode[swclk_port]; - out_mode &= ~(0xFU << (4 * swclk_pin)); - out_mode |= (MXC_V_GPIO_OUT_MODE_NORMAL << (4 * swclk_pin)); - MXC_GPIO->out_mode[swclk_port] = out_mode; - - out_mode = MXC_GPIO->out_mode[swdio_port]; - out_mode &= ~(0xFU << (4 * swdio_pin)); - out_mode |= (MXC_V_GPIO_OUT_MODE_NORMAL << (4 * swdio_pin)); - MXC_GPIO->out_mode[swdio_port] = out_mode; - - out_mode = MXC_GPIO->out_mode[nreset_port]; - out_mode &= ~(0xFU << (4 * nreset_pin)); - out_mode |= (MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << (4 * nreset_pin)); - MXC_GPIO->out_mode[nreset_port] = out_mode; + MXC_GPIO_SETMODE(swclk_port, swclk_pin, MXC_V_GPIO_OUT_MODE_NORMAL); + MXC_GPIO_SETMODE(swdio_port, swdio_pin, MXC_V_GPIO_OUT_MODE_NORMAL); + MXC_GPIO_SETMODE(nreset_port, nreset_pin, MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP); tck_in = (volatile uint32_t *)BITBAND(&MXC_GPIO->in_val[swclk_port], swclk_pin); tck_out = (volatile uint32_t *)BITBAND(&MXC_GPIO->out_val[swclk_port], swclk_pin); @@ -249,28 +236,15 @@ Disables the DAP Hardware I/O pins which configures: */ __STATIC_INLINE void PORT_OFF (void) { - uint32_t out_mode; - // Disable weak pullup in high-z output mode - MXC_GPIO->out_val[swclk_port] &= ~(1 << swclk_pin); - MXC_GPIO->out_val[swdio_port] &= ~(1 << swdio_pin); - MXC_GPIO->out_val[nreset_port] &= ~(1 << nreset_pin); + MXC_GPIO_CLRBIT(swclk_port, swclk_pin); + MXC_GPIO_CLRBIT(swdio_port, swdio_pin); + MXC_GPIO_CLRBIT(nreset_port, nreset_pin); // High-z output mode - out_mode = MXC_GPIO->out_mode[swclk_port]; - out_mode &= ~(0xFU << (4 * swclk_pin)); - out_mode |= (MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << (4 * swclk_pin)); - MXC_GPIO->out_mode[swclk_port] = out_mode; - - out_mode = MXC_GPIO->out_mode[swdio_port]; - out_mode &= ~(0xFU << (4 * swdio_pin)); - out_mode |= (MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << (4 * swdio_pin)); - MXC_GPIO->out_mode[swdio_port] = out_mode; - - out_mode = MXC_GPIO->out_mode[nreset_port]; - out_mode &= ~(0xFU << (4 * nreset_pin)); - out_mode |= (MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << (4 * nreset_pin)); - MXC_GPIO->out_mode[nreset_port] = out_mode; + MXC_GPIO_SETMODE(swclk_port, swclk_pin, MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP); + MXC_GPIO_SETMODE(swdio_port, swdio_pin, MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP); + MXC_GPIO_SETMODE(nreset_port, nreset_pin, MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP); } // SWCLK/TCK I/O pin ------------------------------------- @@ -347,12 +321,7 @@ called prior \ref PIN_SWDIO_OUT function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) { - uint32_t out_mode; - - out_mode = MXC_GPIO->out_mode[swdio_port]; - out_mode &= ~(0xFU << (4 * swdio_pin)); - out_mode |= (MXC_V_GPIO_OUT_MODE_NORMAL << (4 * swdio_pin)); - MXC_GPIO->out_mode[swdio_port] = out_mode; + MXC_GPIO_SETMODE(swdio_port, swdio_pin, MXC_V_GPIO_OUT_MODE_NORMAL); } /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). @@ -361,12 +330,8 @@ called prior \ref PIN_SWDIO_IN function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) { - uint32_t out_mode; - - out_mode = MXC_GPIO->out_mode[swdio_port]; - out_mode &= ~(0xFU << (4 * swdio_pin)); - MXC_GPIO->out_mode[swdio_port] = out_mode; - MXC_GPIO->out_val[swdio_port] &= ~(1 << swdio_pin); + MXC_GPIO_SETMODE(swdio_port, swdio_pin, MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z); + MXC_GPIO_CLRBIT(swdio_port, swdio_pin); } // TDI Pin I/O --------------------------------------------- @@ -512,29 +477,16 @@ Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled an */ __STATIC_INLINE void DAP_SETUP (void) { - uint32_t out_mode; - // Weak pull-up disabled - MXC_GPIO->out_val[swclk_port] &= ~(1 << swclk_pin); - MXC_GPIO->out_val[swdio_port] &= ~(1 << swdio_pin); + MXC_GPIO_CLRBIT(swclk_port, swclk_pin); + MXC_GPIO_CLRBIT(swdio_port, swdio_pin); // Weak pull-up enabled - MXC_GPIO->out_val[nreset_port] |= (1 << nreset_pin); + MXC_GPIO_SETBIT(nreset_port, nreset_pin); // High-Z output mode - out_mode = MXC_GPIO->out_mode[swclk_port]; - out_mode &= ~(0xFU << (4 * swclk_pin)); - out_mode |= (MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << (4 * swclk_pin)); - MXC_GPIO->out_mode[swclk_port] = out_mode; - - out_mode = MXC_GPIO->out_mode[swdio_port]; - out_mode &= ~(0xFU << (4 * swdio_pin)); - out_mode |= (MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << (4 * swdio_pin)); - MXC_GPIO->out_mode[swdio_port] = out_mode; - - out_mode = MXC_GPIO->out_mode[nreset_port]; - out_mode &= ~(0xFU << (4 * nreset_pin)); - out_mode |= (MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << (4 * nreset_pin)); - MXC_GPIO->out_mode[nreset_port] = out_mode; + MXC_GPIO_SETMODE(swclk_port, swclk_pin, MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP); + MXC_GPIO_SETMODE(swdio_port, swdio_pin, MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP); + MXC_GPIO_SETMODE(nreset_port, nreset_pin, MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP); } /** Reset Target Device with custom specific I/O pin or command sequence. diff --git a/source/hic_hal/maxim/max32625/IO_Config.h b/source/hic_hal/maxim/max32625/IO_Config.h index d5fd7a3cb..d7d53d105 100644 --- a/source/hic_hal/maxim/max32625/IO_Config.h +++ b/source/hic_hal/maxim/max32625/IO_Config.h @@ -102,4 +102,9 @@ typedef enum { #define CDC_ACM_UART_SWD 2 #define CDC_ACM_UART_DIP 0 +#define MXC_GPIO_SETMODE(pt, pn, m) (MXC_GPIO->out_mode[pt] = (MXC_GPIO->out_mode[pt] & ~(0xFU << (4 * pn))) | (m << (4 * pn))) +#define MXC_GPIO_SETBIT(pt, pn) (MXC_SETBIT(&MXC_GPIO->out_val[pt], pn)) +#define MXC_GPIO_CLRBIT(pt, pn) (MXC_CLRBIT(&MXC_GPIO->out_val[pt], pn)) +#define MXC_GPIO_GETBIT(pt, pn) (MXC_GETBIT(&MXC_GPIO->in_val[pt], pn)) + #endif diff --git a/source/hic_hal/maxim/max32625/gpio.c b/source/hic_hal/maxim/max32625/gpio.c index 71a2b5161..0d89bd655 100755 --- a/source/hic_hal/maxim/max32625/gpio.c +++ b/source/hic_hal/maxim/max32625/gpio.c @@ -108,9 +108,9 @@ void target_set_interface(TARGET_INTERFACE mode) nreset_port = PIN_nRESET_PORT; nreset_pin = PIN_nRESET_PIN; - MXC_CLRBIT(&MXC_GPIO->out_val[EN_VDDIOH_PORT], EN_VDDIOH_PIN); // Low to disable SWOUT - MXC_SETBIT(&MXC_GPIO->out_val[IOH_OW_EN_PORT], IOH_OW_EN_PIN); // High to power MAX14689 - MXC_SETBIT(&MXC_GPIO->out_val[SWD_DIP_SEL_PORT], SWD_DIP_SEL_PIN); // High to connect Bn <-> Cn + MXC_GPIO_CLRBIT(EN_VDDIOH_PORT, EN_VDDIOH_PIN); // Low to disable SWOUT + MXC_GPIO_SETBIT(IOH_OW_EN_PORT, IOH_OW_EN_PIN); // High to power MAX14689 + MXC_GPIO_SETBIT(SWD_DIP_SEL_PORT, SWD_DIP_SEL_PIN); // High to connect Bn <-> Cn uart_set_instance(CDC_ACM_UART_SWD); break; case IO_DIP_EXT: @@ -121,9 +121,9 @@ void target_set_interface(TARGET_INTERFACE mode) nreset_port = PIN_DIP_nRESET_PORT; nreset_pin = PIN_DIP_nRESET_PIN; - MXC_CLRBIT(&MXC_GPIO->out_val[EN_VDDIOH_PORT], EN_VDDIOH_PIN); // Low to disable SWOUT - MXC_SETBIT(&MXC_GPIO->out_val[IOH_OW_EN_PORT], IOH_OW_EN_PIN); // High to power MAX14689 - MXC_CLRBIT(&MXC_GPIO->out_val[SWD_DIP_SEL_PORT], SWD_DIP_SEL_PIN); // Low to connect Bn <-> An + MXC_GPIO_CLRBIT(EN_VDDIOH_PORT, EN_VDDIOH_PIN); // Low to disable SWOUT + MXC_GPIO_SETBIT(IOH_OW_EN_PORT, IOH_OW_EN_PIN); // High to power MAX14689 + MXC_GPIO_CLRBIT(SWD_DIP_SEL_PORT, SWD_DIP_SEL_PIN); // Low to connect Bn <-> An uart_set_instance(CDC_ACM_UART_DIP); break; } @@ -133,7 +133,6 @@ void target_set_interface(TARGET_INTERFACE mode) void gpio_init(void) { int i; - uint32_t out_mode; // Ensure that the GPIO clock is enabled if (MXC_CLKMAN->sys_clk_ctrl_6_gpio == MXC_S_CLKMAN_CLK_SCALE_DISABLED) { @@ -147,60 +146,34 @@ void gpio_init(void) // Set to enable the board to power VDDIOH and in turn the target micro // Clear to disable the board from powering VDDIOH - MXC_CLRBIT(&MXC_GPIO->out_val[EN_VDDIOH_PORT], EN_VDDIOH_PIN); - out_mode = MXC_GPIO->out_mode[EN_VDDIOH_PORT]; - out_mode &= ~(0xFU << (4 * EN_VDDIOH_PIN)); - out_mode |= (MXC_V_GPIO_OUT_MODE_NORMAL << (4 * EN_VDDIOH_PIN)); - MXC_GPIO->out_mode[EN_VDDIOH_PORT] = out_mode; + MXC_GPIO_CLRBIT(EN_VDDIOH_PORT, EN_VDDIOH_PIN); + MXC_GPIO_SETMODE(EN_VDDIOH_PORT, EN_VDDIOH_PIN, MXC_V_GPIO_OUT_MODE_NORMAL); // LED initial state off - MXC_GPIO->out_val[PIN_DAP_LED_PORT] |= (1 << PIN_DAP_LED_PIN); - MXC_GPIO->out_val[PIN_MSD_LED_PORT] |= (1 << PIN_MSD_LED_PIN); - MXC_GPIO->out_val[PIN_CDC_LED_PORT] |= (1 << PIN_CDC_LED_PIN); - - // LED outputs - out_mode = MXC_GPIO->out_mode[PIN_DAP_LED_PORT]; - out_mode &= ~(0xFU << (4 * PIN_DAP_LED_PIN)); - out_mode |= (MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << (4 * PIN_DAP_LED_PIN)); - MXC_GPIO->out_mode[PIN_DAP_LED_PORT] = out_mode; - - out_mode = MXC_GPIO->out_mode[PIN_MSD_LED_PORT]; - out_mode &= ~(0xFU << (4 * PIN_MSD_LED_PIN)); - out_mode |= (MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << (4 * PIN_MSD_LED_PIN)); - MXC_GPIO->out_mode[PIN_MSD_LED_PORT] = out_mode; - - out_mode = MXC_GPIO->out_mode[PIN_CDC_LED_PORT]; - out_mode &= ~(0xFU << (4 * PIN_CDC_LED_PIN)); - out_mode |= (MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << (4 * PIN_CDC_LED_PIN)); - MXC_GPIO->out_mode[PIN_CDC_LED_PORT] = out_mode; + MXC_GPIO_SETBIT(PIN_DAP_LED_PORT, PIN_DAP_LED_PIN); + MXC_GPIO_SETBIT(PIN_MSD_LED_PORT, PIN_MSD_LED_PIN); + MXC_GPIO_SETBIT(PIN_CDC_LED_PORT, PIN_CDC_LED_PIN); + + // LED outputs + MXC_GPIO_SETMODE(PIN_DAP_LED_PORT, PIN_DAP_LED_PIN, MXC_V_GPIO_OUT_MODE_OPEN_DRAIN); + MXC_GPIO_SETMODE(PIN_MSD_LED_PORT, PIN_MSD_LED_PIN, MXC_V_GPIO_OUT_MODE_OPEN_DRAIN); + MXC_GPIO_SETMODE(PIN_CDC_LED_PORT, PIN_CDC_LED_PIN, MXC_V_GPIO_OUT_MODE_OPEN_DRAIN); // Button Input - out_mode = MXC_GPIO->out_mode[PIN_RESET_IN_NO_FWRD_PORT]; - out_mode &= ~(0xFU << (4 * PIN_RESET_IN_NO_FWRD_PIN)); - out_mode |= (MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << (4 * PIN_RESET_IN_NO_FWRD_PIN)); - MXC_GPIO->out_mode[PIN_RESET_IN_NO_FWRD_PORT] = out_mode; - MXC_GPIO->out_val[PIN_RESET_IN_NO_FWRD_PORT] |= (0x1U << PIN_RESET_IN_NO_FWRD_PIN); + MXC_GPIO_SETMODE(PIN_RESET_IN_NO_FWRD_PORT, PIN_RESET_IN_NO_FWRD_PIN, MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP); + MXC_GPIO_SETBIT(PIN_RESET_IN_NO_FWRD_PORT, PIN_RESET_IN_NO_FWRD_PIN); // IOH_1W_EN (must be configured for strong drive) - MXC_SETBIT(&MXC_GPIO->out_val[IOH_OW_EN_PORT], IOH_OW_EN_PIN); - out_mode = MXC_GPIO->out_mode[IOH_OW_EN_PORT]; - out_mode &= ~(0xFU << (4 * IOH_OW_EN_PIN)); - out_mode |= (MXC_V_GPIO_OUT_MODE_FAST_DRIVE << (4 * IOH_OW_EN_PIN)); - MXC_GPIO->out_mode[IOH_OW_EN_PORT] = out_mode; + MXC_GPIO_SETBIT(IOH_OW_EN_PORT, IOH_OW_EN_PIN); + MXC_GPIO_SETMODE(IOH_OW_EN_PORT, IOH_OW_EN_PIN, MXC_V_GPIO_OUT_MODE_FAST_DRIVE); // SWD_DIP_SEL (must be configured for strong drive) - MXC_CLRBIT(&MXC_GPIO->out_val[SWD_DIP_SEL_PORT], SWD_DIP_SEL_PIN); - out_mode = MXC_GPIO->out_mode[SWD_DIP_SEL_PORT]; - out_mode &= ~(0xFU << (4 * SWD_DIP_SEL_PIN)); - out_mode |= (MXC_V_GPIO_OUT_MODE_FAST_DRIVE << (4 * SWD_DIP_SEL_PIN)); - MXC_GPIO->out_mode[SWD_DIP_SEL_PORT] = out_mode; + MXC_GPIO_CLRBIT(SWD_DIP_SEL_PORT, SWD_DIP_SEL_PIN); + MXC_GPIO_SETMODE(SWD_DIP_SEL_PORT, SWD_DIP_SEL_PIN, MXC_V_GPIO_OUT_MODE_FAST_DRIVE); // Strong pull-up disable - MXC_SETBIT(&MXC_GPIO->out_val[OWM_SUP_PORT], OWM_SUP_PIN); - out_mode = MXC_GPIO->out_mode[OWM_SUP_PORT]; - out_mode &= ~(0xFU << (4 * OWM_SUP_PIN)); - out_mode |= (MXC_V_GPIO_OUT_MODE_NORMAL << (4 * OWM_SUP_PIN)); - MXC_GPIO->out_mode[OWM_SUP_PORT] = out_mode; + MXC_GPIO_SETBIT(OWM_SUP_PORT, OWM_SUP_PIN); + MXC_GPIO_SETMODE(OWM_SUP_PORT, OWM_SUP_PIN, MXC_V_GPIO_OUT_MODE_NORMAL); // VDDIOH driver isn't strong enough with the strong pull-up MXC_IOMAN->use_vddioh_1 &= ~(1U << (((OWM_PORT - 4) * 8) + OWM_PIN)); @@ -229,10 +202,10 @@ void gpio_init(void) MXC_F_ADC_CTRL_ADC_CHGPUMP_PU); // Change the MUX to other pins before measuring the voltage to avoid false reading - MXC_SETBIT(&MXC_GPIO->out_val[SWD_DIP_SEL_PORT], SWD_DIP_SEL_PIN); // High to connect Bn <-> Cn + MXC_GPIO_SETBIT(SWD_DIP_SEL_PORT, SWD_DIP_SEL_PIN); // High to connect Bn <-> Cn uint16_t tmp_hdr_vio = readADC(HDR_VIO_CH); - MXC_CLRBIT(&MXC_GPIO->out_val[SWD_DIP_SEL_PORT], SWD_DIP_SEL_PIN); // Low to connect Bn <-> An + MXC_GPIO_CLRBIT(SWD_DIP_SEL_PORT, SWD_DIP_SEL_PIN); // Low to connect Bn <-> An uint16_t tmp_swd_vio = readADC(SWD_VIO_CH); // Set IO interface @@ -250,9 +223,9 @@ void gpio_init(void) void gpio_set_hid_led(gpio_led_state_t state) { if (state == GPIO_LED_ON) { - MXC_CLRBIT(&MXC_GPIO->out_val[PIN_DAP_LED_PORT], PIN_DAP_LED_PIN); + MXC_GPIO_CLRBIT(PIN_DAP_LED_PORT, PIN_DAP_LED_PIN); } else { - MXC_SETBIT(&MXC_GPIO->out_val[PIN_DAP_LED_PORT], PIN_DAP_LED_PIN); + MXC_GPIO_SETBIT(PIN_DAP_LED_PORT, PIN_DAP_LED_PIN); } } @@ -260,9 +233,9 @@ void gpio_set_hid_led(gpio_led_state_t state) void gpio_set_msc_led(gpio_led_state_t state) { if (state == GPIO_LED_ON) { - MXC_CLRBIT(&MXC_GPIO->out_val[PIN_MSD_LED_PORT], PIN_MSD_LED_PIN); + MXC_GPIO_CLRBIT(PIN_MSD_LED_PORT, PIN_MSD_LED_PIN); } else { - MXC_SETBIT(&MXC_GPIO->out_val[PIN_MSD_LED_PORT], PIN_MSD_LED_PIN); + MXC_GPIO_SETBIT(PIN_MSD_LED_PORT, PIN_MSD_LED_PIN); } } @@ -270,16 +243,16 @@ void gpio_set_msc_led(gpio_led_state_t state) void gpio_set_cdc_led(gpio_led_state_t state) { if (state == GPIO_LED_ON) { - MXC_CLRBIT(&MXC_GPIO->out_val[PIN_CDC_LED_PORT], PIN_CDC_LED_PIN); + MXC_GPIO_CLRBIT(PIN_CDC_LED_PORT, PIN_CDC_LED_PIN); } else { - MXC_SETBIT(&MXC_GPIO->out_val[PIN_CDC_LED_PORT], PIN_CDC_LED_PIN); + MXC_GPIO_SETBIT(PIN_CDC_LED_PORT, PIN_CDC_LED_PIN); } } /******************************************************************************/ uint8_t gpio_get_reset_btn_no_fwrd(void) { - return !MXC_GETBIT(&MXC_GPIO->in_val[PIN_RESET_IN_NO_FWRD_PORT], PIN_RESET_IN_NO_FWRD_PIN); + return !MXC_GPIO_GETBIT(PIN_RESET_IN_NO_FWRD_PORT, PIN_RESET_IN_NO_FWRD_PIN); } /******************************************************************************/ From 408658234cc47394fa5baf93c3e03afd0ca0327d Mon Sep 17 00:00:00 2001 From: ozersa <46590392+ozersa@users.noreply.github.com> Date: Wed, 20 Oct 2021 18:14:50 +0300 Subject: [PATCH 329/617] Provide a way to select SWD or DIP interface (#878) Signed-off-by: Sadik.Ozer --- source/hic_hal/maxim/max32625/gpio.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/source/hic_hal/maxim/max32625/gpio.c b/source/hic_hal/maxim/max32625/gpio.c index 0d89bd655..94fea6985 100755 --- a/source/hic_hal/maxim/max32625/gpio.c +++ b/source/hic_hal/maxim/max32625/gpio.c @@ -57,6 +57,7 @@ static inline void use_vddioh(int port, int pin) } /******************************************************************************/ +#if !defined(MAX3625_FORCE_IO_SWD_EXT) && !defined(MAX3625_FORCE_IO_DIP_EXT) static uint16_t readADC(uint8_t ch) { uint32_t ctrl_tmp; @@ -95,6 +96,7 @@ static uint16_t readADC(uint8_t ch) return (uint16_t)(MXC_ADC->data); } +#endif /******************************************************************************/ void target_set_interface(TARGET_INTERFACE mode) @@ -195,6 +197,11 @@ void gpio_init(void) MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED; MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE; +#if defined(MAX3625_FORCE_IO_SWD_EXT) + target_set_interface(IO_SWD_EXT); +#elif defined(MAX3625_FORCE_IO_DIP_EXT) + target_set_interface(IO_DIP_EXT); +#else MXC_ADC->ctrl = (MXC_F_ADC_CTRL_ADC_PU | MXC_F_ADC_CTRL_ADC_CLK_EN | MXC_F_ADC_CTRL_BUF_PU | @@ -217,6 +224,7 @@ void gpio_init(void) // Default to SWD interface target_set_interface(IO_SWD_EXT); } +#endif } /******************************************************************************/ From 7ebb737d1ecb358fc4131bf7901d8d951134b9e3 Mon Sep 17 00:00:00 2001 From: "Sadik.Ozer" Date: Wed, 20 Oct 2021 09:55:15 +0300 Subject: [PATCH 330/617] Add MAX78000FTHR Signed-off-by: Sadik.Ozer --- projects.yaml | 4 + records/board/max78000fthr.yaml | 7 ++ source/board/max78000fthr.c | 33 +++++++++ source/family/maxim/max78000/flash_blob.c | 89 +++++++++++++++++++++++ source/family/maxim/max78000/target.c | 36 +++++++++ test/info.py | 3 + 6 files changed, 172 insertions(+) create mode 100644 records/board/max78000fthr.yaml create mode 100644 source/board/max78000fthr.c create mode 100644 source/family/maxim/max78000/flash_blob.c create mode 100644 source/family/maxim/max78000/target.c diff --git a/projects.yaml b/projects.yaml index 2926040e7..a909751c3 100644 --- a/projects.yaml +++ b/projects.yaml @@ -654,6 +654,10 @@ projects: - *module_if - *module_hic_max32625 - records/board/max32666fthr.yaml + max32625_max78000fthr_if: + - *module_if + - *module_hic_max32625 + - records/board/max78000fthr.yaml sam3u2c_mkit_dk_dongle_nrf5x_if: - *module_if - *module_hic_sam3u2c diff --git a/records/board/max78000fthr.yaml b/records/board/max78000fthr.yaml new file mode 100644 index 000000000..c713c29e4 --- /dev/null +++ b/records/board/max78000fthr.yaml @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/max78000fthr.c + family: + - source/family/maxim/max78000/target.c + - source/family/maxim/target_reset_max32xxx.c diff --git a/source/board/max78000fthr.c b/source/board/max78000fthr.c new file mode 100644 index 000000000..74c4fe99b --- /dev/null +++ b/source/board/max78000fthr.c @@ -0,0 +1,33 @@ +/** + * @file max78000fthr.c + * @brief board ID for the Maxim Integrated's MAX78000FTHR + * + * DAPLink Interface Firmware + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_family.h" +#include "target_board.h" + +const board_info_t g_board_info = { + .info_version = kBoardInfoVersion, + .board_id = "0423", + .family_id = kMaxim_MAX3266X_FamilyID, + .flags = kEnablePageErase, + .target_cfg = &target_device, + .daplink_url_name = "MAX78000HTM", + .daplink_target_url = "http://www.maximintegrated.com/max78000fthr", +}; diff --git a/source/family/maxim/max78000/flash_blob.c b/source/family/maxim/max78000/flash_blob.c new file mode 100644 index 000000000..91cee17ea --- /dev/null +++ b/source/family/maxim/max78000/flash_blob.c @@ -0,0 +1,89 @@ +/** + * @file flash_blob.c + * @brief Flash algorithm for the MAX78000 + * + * DAPLink Interface Firmware + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "flash_blob.h" + +#define FLC_BASE 0x40029000 +#define CLK_DIV 0x00000064 +#define BRST_SIZE 0x00000080 +#define FLASH_BASE 0x10000000 +#define FLASH_SIZE KB(512) +#define FLASH_SECTOR KB(8) + +#define DEV_CFG_TARGET_ADDRESS (0x0000025cUL) // From flash_algo map file +#define FLASH_ALGO_GEN_ADDER 32 +#define DEV_CFG_LOCAL_ADDRESS ((uint8_t*)((unsigned int)flash_algo_blob + DEV_CFG_TARGET_ADDRESS + FLASH_ALGO_GEN_ADDER)) + +const uint32_t flash_algo_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x4603b510, 0x4893460c, 0x68414448, 0xf0006888, 0xb1087080, 0xbd102001, 0x4448488e, 0x60486880, + 0xe7f82000, 0x488b4602, 0x68414448, 0xf0206888, 0x60884070, 0x47702000, 0x44484886, 0x68886841, + 0x7080f000, 0x2001b108, 0x6a484770, 0x2000b148, 0x6a486248, 0x2002b128, 0x6a486248, 0x2001b108, + 0x6888e7f2, 0x4070f020, 0x5000f040, 0x20006088, 0xb510e7ea, 0x44484877, 0xf7ff6844, 0xb108ffdd, + 0xbd102001, 0xf42068a0, 0xf440407f, 0x60a0402a, 0xf04068a0, 0x60a00002, 0x68a0bf00, 0x7080f000, + 0xd1fa2800, 0xf02068a0, 0x60a04070, 0xf0006a60, 0xb1080002, 0xe7e42001, 0xe7e22000, 0x4605b570, + 0x44484864, 0xf7ff6844, 0xb108ffb7, 0xbd702001, 0xf42068a0, 0xf440407f, 0x60a040aa, 0x68a06025, + 0x0004f040, 0xbf0060a0, 0xf00068a0, 0x28007080, 0x68a0d1fa, 0x4070f020, 0x6a6060a0, 0x0002f000, + 0x2001b108, 0x2000e7e3, 0xe92de7e1, 0x460747f0, 0x4690468a, 0x4448484f, 0x46566844, 0xf0084645, + 0xb1100003, 0xe8bd2001, 0x464587f0, 0xff84f7ff, 0x2001b108, 0x68a0e7f7, 0x6000f020, 0x68a060a0, + 0x0010f040, 0xe00e60a0, 0xcd016027, 0x68a06320, 0x0001f040, 0xbf0060a0, 0xf00068a0, 0x28007080, + 0x1d3fd1fa, 0x2e041f36, 0xf007d303, 0x2800001f, 0x4838d1ea, 0x68c04448, 0xd1212880, 0xd31f2e10, + 0xf02068a0, 0x60a00010, 0xf04068a0, 0x60a06000, 0x6027e014, 0x6320cd01, 0x6360cd01, 0x63a0cd01, + 0x63e0cd01, 0xf04068a0, 0x60a00001, 0x68a0bf00, 0x7080f000, 0xd1fa2800, 0x3e103710, 0xd2e82e10, + 0xd3192e04, 0xf02068a0, 0x60a06000, 0xf04068a0, 0x60a00010, 0x6027e00e, 0x6320cd01, 0xf04068a0, + 0x60a00001, 0x68a0bf00, 0x7080f000, 0xd1fa2800, 0x1f361d3f, 0xd2ee2e04, 0x68a2b306, 0x6200f022, + 0x68a260a2, 0x0210f042, 0xf04f60a2, 0x21ff30ff, 0x682ae005, 0x0201ea62, 0x02094010, 0x2e001e76, + 0x6027d1f7, 0x68a26320, 0x0201f042, 0xbf0060a2, 0xf00268a2, 0x2a007280, 0xbf00d1fa, 0xf02068a0, + 0x60a04070, 0xf0006a60, 0xb1080002, 0xe76a2001, 0xe7682000, 0x00000004, 0x00000000, 0x00000000, + FLC_BASE, CLK_DIV, BRST_SIZE, FLASH_BASE, FLASH_SIZE, FLASH_SECTOR, +}; + +/** +* List of start and size for each size of flash sector +* The size will apply to all sectors between the listed address and the next address +* in the list. +* The last pair in the list will have sectors starting at that address and ending +* at address start + size. +*/ +static const sector_info_t sectors_info[] = { + {FLASH_BASE, FLASH_SECTOR}, + }; + +const program_target_t flash = { + 0x20000021, // Init + 0x20000045, // UnInit + 0x20000093, // EraseChip + 0x200000DD, // EraseSector + 0x2000012B, // ProgramPage + 0x00000000, // Verify + + // RSB : base address is address of Execution Region PrgData in map file + // to access global/static data + // RSP : Initial stack pointer + {0x20000001, 0x20000258 + FLASH_ALGO_GEN_ADDER, 0x20001000}, // {breakpoint, RSB, RSP} + + 0x20000400, // program_buffer + 0x20000000, // algo_start + sizeof(flash_algo_blob), // algo_size + flash_algo_blob, // image + + 512 // ram_to_flash_bytes_to_be_written +}; diff --git a/source/family/maxim/max78000/target.c b/source/family/maxim/max78000/target.c new file mode 100644 index 000000000..b4223bdf0 --- /dev/null +++ b/source/family/maxim/max78000/target.c @@ -0,0 +1,36 @@ +/** + * @file target.c + * @brief Target information for the MAX78000 + * + * DAPLink Interface Firmware + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_config.h" + +#include "flash_blob.c" + +/* MAX78000 512KiB Flash, 128KiB RAM */ +target_cfg_t target_device = { + .sectors_info = sectors_info, + .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), + .flash_regions[0].start = FLASH_BASE, + .flash_regions[0].end = FLASH_BASE + FLASH_SIZE, + .flash_regions[0].flags = kRegionIsDefault, + .flash_regions[0].flash_algo = (program_target_t *) &flash, + .ram_regions[0].start = 0x20000000, + .ram_regions[0].end = 0x20000000 + KB(128), +}; diff --git a/test/info.py b/test/info.py index 6b07b2873..48493efe7 100644 --- a/test/info.py +++ b/test/info.py @@ -132,6 +132,7 @@ ('max32625_max32630fthr_if', False, 0x0000, "bin" ), ('max32625_max32660evsys_if', False, 0x0000, "bin" ), ('max32625_max32666fthr_if', False, 0x0000, "bin" ), + ('max32625_max78000fthr_if', False, 0x0000, "bin" ), ('kl26z_if', False, 0x0000, "bin" ), ('k20dx_if', False, 0x0000, "bin" ), ('k26f_if', False, 0x0000, "bin" ), @@ -197,6 +198,7 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0418, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32620fthr_if', 'max32625_bl', 'MAX32620' ), ( 0x0421, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32660evsys_if', 'max32625_bl', 'MAX32660' ), ( 0x0422, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32666fthr_if', 'max32625_bl', 'MAX32666' ), + ( 0x0423, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max78000fthr_if', 'max32625_bl', 'MAX78000' ), ( 0x0450, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_ublox_odin_w2_if', None, None ), ( 0x0451, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_mxchip_emw3166_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0453, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_mts_xdot_if', None, None ), @@ -365,6 +367,7 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y 0x0418, # MAX32620FTHR 0x0421, # MAX32660EVSYS 0x0422, # MAX32666FTHR + 0x0423, # MAX78000FTHR 0x0450, # mtb_ublox_odin_w2 0x0456, # lpc11u35_mtb_murata_abz_078_if 0x0457, # lpc11u35_mtb_rak811_if From cf95cd6987eadc4e0d0d7d6da8ed190a7fbb7bdf Mon Sep 17 00:00:00 2001 From: "Sadik.Ozer" Date: Wed, 20 Oct 2021 09:57:11 +0300 Subject: [PATCH 331/617] MAX78000 delta Fix typo Signed-off-by: Sadik.Ozer --- records/board/max78000fthr.yaml | 3 +++ source/family/maxim/target_reset_max32xxx.c | 4 ++-- source/hic_hal/maxim/max32625/gpio.c | 19 +++++++++++++++---- 3 files changed, 20 insertions(+), 6 deletions(-) diff --git a/records/board/max78000fthr.yaml b/records/board/max78000fthr.yaml index c713c29e4..00d612d58 100644 --- a/records/board/max78000fthr.yaml +++ b/records/board/max78000fthr.yaml @@ -5,3 +5,6 @@ common: family: - source/family/maxim/max78000/target.c - source/family/maxim/target_reset_max32xxx.c + macros: + - MAX32625_GPIO_USE_VDDIO + - MAX32625_FORCE_IO_SWD_EXT diff --git a/source/family/maxim/target_reset_max32xxx.c b/source/family/maxim/target_reset_max32xxx.c index 6124fbc9c..2ca4970ed 100644 --- a/source/family/maxim/target_reset_max32xxx.c +++ b/source/family/maxim/target_reset_max32xxx.c @@ -33,7 +33,7 @@ #define INCREASE_DELAY 10 -#define MAX_DELAY 30000 +#define MAX_DELAY 30000 // ~2.82ms /* RESET_PROGRAM state halts the processor on reset by default but the SWD @@ -53,7 +53,7 @@ static uint8_t target_set_state_max326xx(target_state_t state, uint32_t reg_flc_ /* Reset the target and halt it when SWD is available */ while (halt_retries--) { halt_timeout = 10; - lockout_delay = 0; + lockout_delay = 7450; // ~700.6us /* Wait for SWD lockout period after reset */ do { diff --git a/source/hic_hal/maxim/max32625/gpio.c b/source/hic_hal/maxim/max32625/gpio.c index 94fea6985..f5734c38a 100755 --- a/source/hic_hal/maxim/max32625/gpio.c +++ b/source/hic_hal/maxim/max32625/gpio.c @@ -57,7 +57,7 @@ static inline void use_vddioh(int port, int pin) } /******************************************************************************/ -#if !defined(MAX3625_FORCE_IO_SWD_EXT) && !defined(MAX3625_FORCE_IO_DIP_EXT) +#if !defined(MAX32625_FORCE_IO_SWD_EXT) && !defined(MAX32625_FORCE_IO_DIP_EXT) static uint16_t readADC(uint8_t ch) { uint32_t ctrl_tmp; @@ -182,6 +182,12 @@ void gpio_init(void) // 1V8 VDDIO is not high enough to turn off the FET if VDDIOH is 3V3 MXC_IOMAN->use_vddioh_1 |= (1U << (((OWM_PORT - 4) * 8) + OWM_SUP_PIN)); +#if defined(MAX32625_GPIO_USE_VDDIO) + // Use VDDIO + MXC_IOMAN->use_vddioh_0 = 0; + MXC_IOMAN->use_vddioh_1 = 0; +#else + // Use VDDIOH use_vddioh(PIN_nRESET_PORT, PIN_nRESET_PIN); use_vddioh(PIN_DIP_nRESET_PORT, PIN_DIP_nRESET_PIN); use_vddioh(PIN_SWCLK_PORT, PIN_SWCLK_PIN); @@ -192,14 +198,19 @@ void gpio_init(void) use_vddioh(PIN_RX_PORT, PIN_RX_PIN); use_vddioh(PIN_DIP_TX_PORT, PIN_DIP_TX_PIN); use_vddioh(PIN_DIP_RX_PORT, PIN_DIP_RX_PIN); - +#endif + // LEDs use VDDIOH + use_vddioh(PIN_DAP_LED_PORT, PIN_DAP_LED_PIN); + use_vddioh(PIN_MSD_LED_PORT, PIN_MSD_LED_PIN); + use_vddioh(PIN_CDC_LED_PORT, PIN_CDC_LED_PIN); + // Setup the ADC; read the ADC to set IO interface MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED; MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE; -#if defined(MAX3625_FORCE_IO_SWD_EXT) +#if defined(MAX32625_FORCE_IO_SWD_EXT) target_set_interface(IO_SWD_EXT); -#elif defined(MAX3625_FORCE_IO_DIP_EXT) +#elif defined(MAX32625_FORCE_IO_DIP_EXT) target_set_interface(IO_DIP_EXT); #else MXC_ADC->ctrl = (MXC_F_ADC_CTRL_ADC_PU | From 0feda6e07d1ad2f84101da07807a9fa4d37f18c4 Mon Sep 17 00:00:00 2001 From: ozersa <46590392+ozersa@users.noreply.github.com> Date: Wed, 20 Oct 2021 21:02:06 +0300 Subject: [PATCH 332/617] Disable Reset pin interrupt - Fix for old bootloader firmware (#879) Signed-off-by: Sadik.Ozer --- source/hic_hal/maxim/max32625/gpio.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/source/hic_hal/maxim/max32625/gpio.c b/source/hic_hal/maxim/max32625/gpio.c index f5734c38a..932988532 100755 --- a/source/hic_hal/maxim/max32625/gpio.c +++ b/source/hic_hal/maxim/max32625/gpio.c @@ -236,6 +236,10 @@ void gpio_init(void) target_set_interface(IO_SWD_EXT); } #endif + + // Disable Reset pin interrupt - Fix for old bootloader firmware + MXC_GPIO->inten[PIN_RESET_IN_NO_FWRD_PORT] &= ~(1 << PIN_RESET_IN_NO_FWRD_PIN); + NVIC_DisableIRQ(GPIO_P2_IRQn); } /******************************************************************************/ From d1f365fb8b803e5cc57e0835b5a2c0e63d841592 Mon Sep 17 00:00:00 2001 From: Markus Klein Date: Sat, 13 Mar 2021 23:20:08 +0100 Subject: [PATCH 333/617] Add support for NXP FRDM-KL03 board --- projects.yaml | 4 + records/board/frdmkl03z.yaml | 7 ++ source/board/frdmkl03z.c | 30 +++++++ source/family/freescale/kl03z/flash_blob.c | 98 ++++++++++++++++++++++ source/family/freescale/kl03z/target.c | 37 ++++++++ test/info.py | 2 + 6 files changed, 178 insertions(+) create mode 100644 records/board/frdmkl03z.yaml create mode 100644 source/board/frdmkl03z.c create mode 100644 source/family/freescale/kl03z/flash_blob.c create mode 100644 source/family/freescale/kl03z/target.c diff --git a/projects.yaml b/projects.yaml index a909751c3..9d52cfde0 100644 --- a/projects.yaml +++ b/projects.yaml @@ -219,6 +219,10 @@ projects: - *module_if - *module_hic_k20dx - records/board/frdmkl02z.yaml + k20dx_frdmkl03z_if: + - *module_if + - *module_hic_k20dx + - records/board/frdmkl03z.yaml k20dx_frdmkl05z_if: - *module_if - *module_hic_k20dx diff --git a/records/board/frdmkl03z.yaml b/records/board/frdmkl03z.yaml new file mode 100644 index 000000000..d20a68304 --- /dev/null +++ b/records/board/frdmkl03z.yaml @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/frdmkl03z.c + family: + - source/family/freescale/kl03z/target.c + - source/family/freescale/target_reset_Lseries.c diff --git a/source/board/frdmkl03z.c b/source/board/frdmkl03z.c new file mode 100644 index 000000000..36e12fe36 --- /dev/null +++ b/source/board/frdmkl03z.c @@ -0,0 +1,30 @@ +/** + * @file frdmkl03z.c + * @brief board ID for the NXP FRDM-KL03Z board + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_board.h" +#include "target_family.h" + +const board_info_t g_board_info = { + .info_version = kBoardInfoVersion, + .board_id = "0207", + .family_id = kNXP_KinetisL_FamilyID, + .target_cfg = &target_device, +}; diff --git a/source/family/freescale/kl03z/flash_blob.c b/source/family/freescale/kl03z/flash_blob.c new file mode 100644 index 000000000..dabf7360e --- /dev/null +++ b/source/family/freescale/kl03z/flash_blob.c @@ -0,0 +1,98 @@ +/** + * @file flash_blob.c + * @brief Flash algorithm for the kl03z + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "flash_blob.h" + +static const uint32_t KL03Z_FLM[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x492bb510, 0x60082000, 0x4448482a, 0xf88af000, 0xd0002800, 0xbd102001, 0x47702000, 0xb5104825, + 0xf0004448, 0x0004f871, 0x4822d105, 0x44482100, 0xf908f000, 0xf0004604, 0x4620f834, 0xb570bd10, + 0x46014605, 0x2201481b, 0xf0004448, 0x0004f837, 0x4818d107, 0x22012300, 0x44484629, 0xf8baf000, + 0xf0004604, 0x4620f81e, 0xb5febd70, 0x460b460d, 0x46014607, 0x4616480f, 0xf0004448, 0x0004f887, + 0x9001d10b, 0x21019002, 0x9100480a, 0x462a4633, 0x44484639, 0xf8e4f000, 0xf0004604, 0x4620f802, + 0x4805bdfe, 0x220168c1, 0x43110292, 0x477060c1, 0x40048100, 0x00000004, 0xf0003000, 0x4614b5f8, + 0xf000460d, 0x2800f848, 0x192cd118, 0x05a11e64, 0x0aa1d003, 0x028c1c49, 0x4e091e64, 0x2709447e, + 0xd80b42a5, 0x60056830, 0x71c74806, 0xf8e8f000, 0xd1032800, 0x02892101, 0xe7f1186d, 0x0000bdf8, + 0x0000038c, 0x40020000, 0x2800b510, 0x4904d005, 0x71c82044, 0xf8d4f000, 0x2004bd10, 0x0000bd10, + 0x40020000, 0xd0122800, 0x68c94916, 0x01094a16, 0x00490f09, 0x5a51447a, 0xd00a0309, 0x60022200, + 0x21016041, 0x02896081, 0x461060c1, 0x20044770, 0x20644770, 0x28004770, 0x460bd005, 0x079b4313, + 0x2065d003, 0x20044770, 0x68034770, 0xd804428b, 0x18896840, 0x42881818, 0x2066d201, 0x20004770, + 0x00004770, 0x40048040, 0x00000312, 0x461db5f8, 0x460e0014, 0x461ad017, 0xffddf7ff, 0xd1132800, + 0x447f4f0a, 0xd00f2d00, 0x60066838, 0x6839cc01, 0x49076048, 0x71c82006, 0xf882f000, 0xd1032800, + 0x1f2d1d36, 0x2004e7ee, 0x0000bdf8, 0x000002c6, 0x40020000, 0xb081b5ff, 0x460e4614, 0xf7ff4605, + 0x2800ffba, 0x68a9d127, 0xf0006868, 0x9000f881, 0x42404271, 0x424d4001, 0xd10142b5, 0x182d9800, + 0xd0172c00, 0x42a71baf, 0x4627d900, 0x08b9480b, 0x68004478, 0x480a6006, 0x71c22201, 0x72c20a0a, + 0x99047281, 0xf0007241, 0x2800f84b, 0x1be4d103, 0xe7e319f6, 0xb0052000, 0x0000bdf0, 0x00000258, + 0x40020000, 0x2800b510, 0x4804d006, 0x71c22240, 0xf0007181, 0xbd10f835, 0xbd102004, 0x40020000, + 0x9f08b5f8, 0x4616001c, 0xd004460d, 0xff73f7ff, 0xd1012800, 0x2004e01d, 0x480fbdf8, 0x68014478, + 0x490e600d, 0x71ca2202, 0x72ca9a06, 0x68216800, 0xf0006081, 0x2800f815, 0x9907d008, 0xd0002900, + 0x2f00600d, 0x2100d0e8, 0xbdf86039, 0x1d241f36, 0x2e001d2d, 0xbdf8d1e1, 0x000001ec, 0x40020000, + 0x2170480a, 0x21807001, 0x78017001, 0xd0fc09c9, 0x06817800, 0x2067d501, 0x06c14770, 0x2068d501, + 0x07c04770, 0x2069d0fc, 0x00004770, 0x40020000, 0x09032200, 0xd32c428b, 0x428b0a03, 0x2300d311, + 0xe04e469c, 0x430b4603, 0x2200d43c, 0x428b0843, 0x0903d331, 0xd31c428b, 0x428b0a03, 0x4694d301, + 0x09c3e03f, 0xd301428b, 0x1ac001cb, 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152, 0xd301428b, + 0x1ac0014b, 0x09034152, 0xd301428b, 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb, 0x08834152, + 0xd301428b, 0x1ac0008b, 0x08434152, 0xd301428b, 0x1ac0004b, 0x1a414152, 0x4601d200, 0x46104152, + 0xe05d4770, 0xd0000fca, 0x10034249, 0x4240d300, 0x22004053, 0x0903469c, 0xd32d428b, 0x428b0a03, + 0x22fcd312, 0xba120189, 0x428b0a03, 0x0189d30c, 0x428b1192, 0x0189d308, 0x428b1192, 0x0189d304, + 0x1192d03a, 0x0989e000, 0x428b09c3, 0x01cbd301, 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0, + 0x428b0943, 0x014bd301, 0x41521ac0, 0x428b0903, 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301, + 0x41521ac0, 0x428b0883, 0x008bd301, 0x41521ac0, 0x0843d2d9, 0xd301428b, 0x1ac0004b, 0x1a414152, + 0x4601d200, 0x41524663, 0x4610105b, 0x4240d301, 0xd5002b00, 0x47704249, 0x105b4663, 0x4240d300, + 0x2000b501, 0x46c046c0, 0x0002bd02, 0x00000004, 0x00000008, 0x00000010, 0x00000020, 0x00000040, + 0x00000000, 0x00000000, 0x00000020, 0x40020004, 0x00000000, +}; + +/** +* List of start and size for each size of flash sector +* The size will apply to all sectors between the listed address and the next address +* in the list. +* The last pair in the list will have sectors starting at that address and ending +* at address start + size. +*/ +static const sector_info_t sectors_info[] = { + {0, 1024}, + }; + +static const program_target_t flash = { + 0x20000021, // Init + 0x20000039, // UnInit + 0x2000003D, // EraseChip + 0x2000005F, // EraseSector + 0x2000008B, // ProgramPage + 0x0, // Verify + + // breakpoint = RAM start + 1 + // RSB : base address is address of Execution Region PrgData in map file + // to access global/static data + // RSP : Initial stack pointer + { + 0x20000001, // breakpoint instruction address + 0x20000000 + 0x20 + 0x470, // static base register value (image start + header + static base offset) + 0x20000800 // initial stack pointer + }, + + 0x20000a00, // program_buffer, any valid RAM location with +512 bytes of headroom + 0x20000000, // algo_start, start of RAM + sizeof(KL03Z_FLM), // algo_size, size of array above + KL03Z_FLM, // image, flash algo instruction array + 512 // ram_to_flash_bytes_to_be_written +}; diff --git a/source/family/freescale/kl03z/target.c b/source/family/freescale/kl03z/target.c new file mode 100644 index 000000000..0b0e39c64 --- /dev/null +++ b/source/family/freescale/kl03z/target.c @@ -0,0 +1,37 @@ +/** + * @file target.c + * @brief Target information for the kl03z + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_config.h" + +// The file flash_blob.c must only be included in target.c +#include "flash_blob.c" + +// target information +target_cfg_t target_device = { + .sectors_info = sectors_info, + .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), + .flash_regions[0].start = 0, + .flash_regions[0].end = KB(32), + .flash_regions[0].flags = kRegionIsDefault, + .flash_regions[0].flash_algo = (program_target_t *) &flash, + .ram_regions[0].start = 0x1FFFFC00, + .ram_regions[0].end = 0x20000C00, +}; diff --git a/test/info.py b/test/info.py index 48493efe7..0eb566708 100644 --- a/test/info.py +++ b/test/info.py @@ -43,6 +43,7 @@ ("k20dx_frdmkw24d_if", True, 0x8000, "bin" ), ("k20dx_frdmkw41z_if", True, 0x8000, "bin" ), ("k20dx_frdmkl02z_if", True, 0x8000, "bin" ), + ("k20dx_frdmkl03z_if", True, 0x8000, "bin" ), ("k20dx_frdmkl05z_if", True, 0x8000, "bin" ), ("k20dx_frdmkl25z_if", True, 0x8000, "bin" ), ("k20dx_frdmkl26z_if", True, 0x8000, "bin" ), @@ -169,6 +170,7 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0204, VENDOR_TO_FAMILY('NXP', 2), 'k20dx_frdmkl02z_if', 'k20dx_bl', None ), ( 0x0205, VENDOR_TO_FAMILY('NXP', 2), 'k20dx_frdmkl28z_if', 'k20dx_bl', None ), ( 0x0206, VENDOR_TO_FAMILY('NXP', 1), 'k20dx_twrke18f_if', 'k20dx_bl', None ), + ( 0x0207, VENDOR_TO_FAMILY('NXP', 2), 'k20dx_frdmkl03z_if', 'k20dx_bl', 'FRDM-KL03Z' ), ( 0x0210, VENDOR_TO_FAMILY('NXP', 2), 'k20dx_frdmkl05z_if', 'k20dx_bl', 'FRDM-KL05Z' ), ( 0x0213, VENDOR_TO_FAMILY('NXP', 2), 'k20dx_frdmke15z_if', 'k20dx_bl', None ), ( 0x0214, VENDOR_TO_FAMILY('NXP', 4), 'k20dx_hexiwear_if', 'k20dx_bl', 'HEXIWEAR' ), From ab4ec3c1fde8e378832a040270362d4c35e71717 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 21 Oct 2021 08:40:00 -0500 Subject: [PATCH 334/617] Additional CMSIS-DAP 2.1 board and target information (#871) --- source/board/96b_nitrogen.c | 2 ++ source/board/FF1705_L151.c | 5 +++-- source/board/archble.c | 4 +++- source/board/archlink.c | 4 +++- source/board/archmax.c | 4 +++- source/board/archpro.c | 5 +++-- source/board/blueninja.c | 4 +++- source/board/c027.c | 5 ++++- source/board/ep_agora.c | 2 ++ source/board/gr-lychee.c | 2 ++ source/board/gr-peach.c | 2 ++ source/board/hexiwear.c | 2 ++ source/board/hrm1017.c | 4 +++- source/board/mkit_dk_dongle_nrf5x.c | 19 ++++++++++++++++--- source/board/numaker_iot_m263a.c | 4 +++- source/board/numaker_m2354.c | 4 +++- source/board/numaker_m252kg.c | 4 +++- source/board/numaker_pfm_m487km.c | 4 +++- source/board/rtl8195am.c | 4 +++- source/board/ssci_chibi.c | 6 ++++-- source/board/sscity.c | 4 +++- source/board/stm32f072rb.c | 6 ++++-- source/board/stm32f103rb.c | 4 +++- source/board/stm32f207zg.c | 6 ++++-- source/board/stm32f334r8.c | 6 ++++-- source/board/stm32f401re.c | 4 +++- source/board/stm32f411re.c | 6 ++++-- source/board/stm32f429zi.c | 4 +++- source/board/stm32f746zg.c | 6 ++++-- source/board/stm32l476rg.c | 6 ++++-- source/board/ublox_evk_nina_b1.c | 3 +++ source/board/ublox_evk_odin_w2.c | 7 +++++-- source/board/xDot-L151.c | 6 ++++-- source/family/nuvoton/m2354kjfae/target.c | 2 ++ source/family/nuvoton/m252kg6ae/target.c | 2 ++ source/family/nuvoton/m263kiaae/target.c | 2 ++ source/family/nuvoton/m487jidae/target.c | 2 ++ source/family/st/stm32f072rb/target.c | 4 +++- source/family/st/stm32f103rb/target.c | 4 +++- source/family/st/stm32f207zg/target.c | 4 +++- source/family/st/stm32f334r8/target.c | 4 +++- source/family/st/stm32f401re/target.c | 4 +++- source/family/st/stm32f407ve/target.c | 4 +++- source/family/st/stm32f411/target.c | 4 +++- source/family/st/stm32f412rg/target.c | 2 ++ source/family/st/stm32f429zi/target.c | 4 +++- source/family/st/stm32f437vg/target.c | 4 +++- source/family/st/stm32f439zi/target.c | 4 +++- source/family/st/stm32f746zg/target.c | 4 +++- source/family/st/stm32l476rg/target.c | 4 +++- source/family/st/stm32l4xx_1024/target.c | 2 ++ source/family/st/xDot-L151/target.c | 4 +++- 52 files changed, 169 insertions(+), 53 deletions(-) diff --git a/source/board/96b_nitrogen.c b/source/board/96b_nitrogen.c index cc5b02d68..d26ec55d6 100644 --- a/source/board/96b_nitrogen.c +++ b/source/board/96b_nitrogen.c @@ -29,4 +29,6 @@ const board_info_t g_board_info = { .board_id = "9014", .family_id = kNordic_Nrf52_FamilyID, .target_cfg = &target_device_nrf52_64, + .board_vendor = "Seeed Studio", + .board_name = "96Boards Nitrogen", }; diff --git a/source/board/FF1705_L151.c b/source/board/FF1705_L151.c index 9d65f45df..9130f256c 100644 --- a/source/board/FF1705_L151.c +++ b/source/board/FF1705_L151.c @@ -28,7 +28,8 @@ const board_info_t g_board_info = { .family_id = kStub_HWReset_FamilyID, .daplink_url_name = "FF1705 HTM", .daplink_drive_name = "FF1705 ", - .daplink_target_url = "https://mbed.org/device/?code=@U?version=@V?target_id=@T", + .daplink_target_url = "https://os.mbed.com/platforms/L-TEK-FF1705", .target_cfg = &target_device, + .board_vendor = "L-Tek", + .board_name = "FF1705", }; - diff --git a/source/board/archble.c b/source/board/archble.c index 673514efc..edd7ba41a 100644 --- a/source/board/archble.c +++ b/source/board/archble.c @@ -1,6 +1,6 @@ /** * @file archble.c - * @brief board ID for the Seeed Studio ArchBLE board + * @brief board ID for the Seeed Studio Arch BLE board * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -29,4 +29,6 @@ const board_info_t g_board_info = { .board_id = "9009", .family_id = kNordic_Nrf51_FamilyID, .target_cfg = &target_device_nrf51822_16, + .board_vendor = "Seeed Studio", + .board_name = "Arch BLE", }; diff --git a/source/board/archlink.c b/source/board/archlink.c index b11e99279..c79a7cd4d 100644 --- a/source/board/archlink.c +++ b/source/board/archlink.c @@ -1,6 +1,6 @@ /** * @file archlink.c - * @brief board ID for the Seeed Studio ArchLink board + * @brief board ID for the Seeed Studio Arch Link board * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -29,4 +29,6 @@ const board_info_t g_board_info = { .board_id = "9013", .family_id = kNordic_Nrf51_FamilyID, .target_cfg = &target_device_nrf51822_16, + .board_vendor = "Seeed Studio", + .board_name = "Arch Link", }; diff --git a/source/board/archmax.c b/source/board/archmax.c index 239a4fd88..6e0be0f74 100644 --- a/source/board/archmax.c +++ b/source/board/archmax.c @@ -1,6 +1,6 @@ /** * @file archmax.c - * @brief board ID for the Seeed Studio ArchMax board + * @brief board ID for the Seeed Studio Arch Max board * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -27,4 +27,6 @@ const board_info_t g_board_info = { .board_id = "9011", .family_id = kStub_HWReset_FamilyID, .target_cfg = &target_device, + .board_vendor = "Seeed Studio", + .board_name = "Arch Max", }; diff --git a/source/board/archpro.c b/source/board/archpro.c index c57893370..146b772bb 100644 --- a/source/board/archpro.c +++ b/source/board/archpro.c @@ -1,6 +1,6 @@ /** * @file archpro.c - * @brief board ID for the Seeed Studio ArchPro board + * @brief board ID for the Seeed Studio Arch Pro board * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -27,5 +27,6 @@ const board_info_t g_board_info = { .board_id = "9004", .family_id = kStub_HWReset_FamilyID, .target_cfg = &target_device, + .board_vendor = "Seeed Studio", + .board_name = "Arch Pro", }; - diff --git a/source/board/blueninja.c b/source/board/blueninja.c index 703d7ee10..6cf81b076 100644 --- a/source/board/blueninja.c +++ b/source/board/blueninja.c @@ -26,7 +26,7 @@ static uint8_t target_set_state_by_board(target_state_t state) { - + if (RESET_PROGRAM == state) { LPC_GPIO->SET[PIN_PWH_PORT] = PIN_PWH; osDelay(10); @@ -40,4 +40,6 @@ const board_info_t g_board_info = { .family_id = kToshiba_Tz_FamilyID, .target_set_state = target_set_state_by_board, .target_cfg = &target_device, + .board_vendor = "Cerevo", + .board_name = "BlueNinja", }; diff --git a/source/board/c027.c b/source/board/c027.c index 981fe8e8a..8eab81734 100644 --- a/source/board/c027.c +++ b/source/board/c027.c @@ -1,6 +1,6 @@ /** * @file c027.c - * @brief board ID for the Ublox C027 board + * @brief board ID for the u-blox C027 board * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -26,5 +26,8 @@ const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "1234", .family_id = kStub_HWReset_FamilyID, + .daplink_target_url = "https://os.mbed.com/platforms/u-blox-C027", .target_cfg = &target_device, + .board_vendor = "u-blox", + .board_name = "C027", }; diff --git a/source/board/ep_agora.c b/source/board/ep_agora.c index 01c331496..ae473b961 100644 --- a/source/board/ep_agora.c +++ b/source/board/ep_agora.c @@ -30,4 +30,6 @@ const board_info_t g_board_info = { .board_id = "2600", .family_id = kNordic_Nrf52_FamilyID, .target_cfg = &target_device_nrf52840, + .board_vendor = "Embedded Planet", + .board_name = "Agora", }; diff --git a/source/board/gr-lychee.c b/source/board/gr-lychee.c index dae3a6fce..0b5ce56e2 100644 --- a/source/board/gr-lychee.c +++ b/source/board/gr-lychee.c @@ -29,4 +29,6 @@ const board_info_t g_board_info = { .flags = kEnablePageErase, .daplink_drive_name = "MBED ", .target_cfg = &target_device, + .board_vendor = "Renesas", + .board_name = "GR-LYCHEE", }; diff --git a/source/board/gr-peach.c b/source/board/gr-peach.c index 277aaa658..b4327be83 100644 --- a/source/board/gr-peach.c +++ b/source/board/gr-peach.c @@ -29,4 +29,6 @@ const board_info_t g_board_info = { .flags = kEnablePageErase, .daplink_drive_name = "MBED ", .target_cfg = &target_device, + .board_vendor = "Renesas", + .board_name = "GR-PEACH", }; diff --git a/source/board/hexiwear.c b/source/board/hexiwear.c index 15ea2eed4..87f25a896 100644 --- a/source/board/hexiwear.c +++ b/source/board/hexiwear.c @@ -51,6 +51,8 @@ const board_info_t g_board_info = { .daplink_target_url = "http://www.hexiwear.com/", .target_cfg = &target_device, .prerun_board_config = prerun_board_config, + .board_vendor = "Mikroe", + .board_name = "Hexiwear", }; static void prerun_board_config(void) diff --git a/source/board/hrm1017.c b/source/board/hrm1017.c index 169714ed6..7b85e3b88 100644 --- a/source/board/hrm1017.c +++ b/source/board/hrm1017.c @@ -1,6 +1,6 @@ /** * @file hrm1017.c - * @brief board ID for the Switch Science HRM1017 board + * @brief board ID for the Switch Science mbed HRM1017 board * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -29,4 +29,6 @@ const board_info_t g_board_info = { .family_id = kNordic_Nrf51_FamilyID, .daplink_drive_name = "MBED ", .target_cfg = &target_device_nrf51822_16, + .board_vendor = "Switch Science", + .board_name = "mbed HRM1017", }; diff --git a/source/board/mkit_dk_dongle_nrf5x.c b/source/board/mkit_dk_dongle_nrf5x.c index 4407442b1..012346685 100644 --- a/source/board/mkit_dk_dongle_nrf5x.c +++ b/source/board/mkit_dk_dongle_nrf5x.c @@ -34,6 +34,13 @@ const char *board_id_nrf51_dongle = "1120"; const char *board_id_nrf52_dk = "1101"; const char *board_id_nrf52840_dk = "1102"; +const char *board_name_nrf51_mkit = "nRF51822-mKIT"; +const char *board_name_nrf51_dk = "nRF51-DK"; +const char *board_name_nrf51_dongle = "nRF51-Dongle"; +const char *board_name_nrf52_dk = "nRF52-DK"; +const char *board_name_nrf52840_dk = "nRF52840-DK"; +static char board_name[14]; + extern target_cfg_t target_device_nrf51822_16; extern target_cfg_t target_device_nrf51822_32; extern target_cfg_t target_device_nrf52_64; @@ -84,7 +91,7 @@ static void nrf_prerun_board_config(void) * 0 | 0 | 1 | 1100 | nRF51-DK * 0 | 1 | 0 | 1101 | nRF52-DK * 0 | 1 | 1 | 1102 | nRF52840-DK - * 1 | 1 | 1 | 1070 | older nRF51 (mkit) + * 1 | 1 | 1 | 1070 | nRF51822-mKIT * 1 | 0 | 0 | undefined * 1 | 0 | 1 | undefined * 1 | 1 | 0 | undefined @@ -94,6 +101,7 @@ static void nrf_prerun_board_config(void) set_target_device(0); target_device.rt_family_id = kNordic_Nrf51_FamilyID; target_device.rt_board_id = board_id_nrf51_mkit; // 1070 + memcpy(board_name, board_name_nrf51_mkit, sizeof(board_name_nrf51_mkit)); // Note only a setting of 111 is defined util_assert(bit2 && bit1); } else { @@ -101,19 +109,22 @@ static void nrf_prerun_board_config(void) set_target_device(1); target_device.rt_family_id = kNordic_Nrf51_FamilyID; target_device.rt_board_id = board_id_nrf51_dk; // 1100 + memcpy(board_name, board_name_nrf51_dk, sizeof(board_name_nrf51_dk)); } else if (!bit2 && !bit1) { set_target_device(1); target_device.rt_family_id = kNordic_Nrf51_FamilyID; target_device.rt_board_id = board_id_nrf51_dongle; // 1120 - } - else if (bit2 && !bit1) { + memcpy(board_name, board_name_nrf51_dongle, sizeof(board_name_nrf51_dongle)); + } else if (bit2 && !bit1) { set_target_device(2); target_device.rt_family_id = kNordic_Nrf52_FamilyID; target_device.rt_board_id = board_id_nrf52_dk; // 1101 + memcpy(board_name, board_name_nrf52_dk, sizeof(board_name_nrf52_dk)); } else { //(bit2 && bit1) set_target_device(3); target_device.rt_family_id = kNordic_Nrf52_FamilyID; target_device.rt_board_id = board_id_nrf52840_dk; // 1102 + memcpy(board_name, board_name_nrf52840_dk, sizeof(board_name_nrf52840_dk)); } } @@ -137,4 +148,6 @@ const board_info_t g_board_info = { .prerun_board_config = nrf_prerun_board_config, .swd_set_target_reset = nrf_swd_set_target_reset, .target_cfg = &target_device, + .board_vendor = "Nordic Semiconductor", + .board_name = board_name, }; diff --git a/source/board/numaker_iot_m263a.c b/source/board/numaker_iot_m263a.c index 48973d32c..7ffeabb99 100644 --- a/source/board/numaker_iot_m263a.c +++ b/source/board/numaker_iot_m263a.c @@ -1,6 +1,6 @@ /** * @file numaker_iot_m263a.c - * @brief board ID for the NuMaker-IoT-M263A board + * @brief board ID for the Nuvoton NuMaker-IoT-M263A board * * DAPLink Interface Firmware * Copyright (c) 2019 Nuvoton Technology Corp. All Rights Reserved @@ -28,4 +28,6 @@ const board_info_t g_board_info = { .family_id = kStub_SWSysReset_FamilyID, .flags = kEnablePageErase, .target_cfg = &target_device, + .board_vendor = "Nuvoton", + .board_name = "NuMaker-IoT-M263A", }; diff --git a/source/board/numaker_m2354.c b/source/board/numaker_m2354.c index c25151184..201ee43b0 100644 --- a/source/board/numaker_m2354.c +++ b/source/board/numaker_m2354.c @@ -1,6 +1,6 @@ /** * @file numaker_m2354.c - * @brief board ID for the NuMaker-M2354 board + * @brief board ID for the Nuvoton NuMaker-M2354 board * * DAPLink Interface Firmware * Copyright (c) 2021 Nuvoton Technology Corp. All Rights Reserved @@ -28,4 +28,6 @@ const board_info_t g_board_info = { .family_id = kStub_SWSysReset_FamilyID, .flags = kEnablePageErase, .target_cfg = &target_device, + .board_vendor = "Nuvoton", + .board_name = "NuMaker-M2354", }; diff --git a/source/board/numaker_m252kg.c b/source/board/numaker_m252kg.c index a7cea5160..d65e58639 100644 --- a/source/board/numaker_m252kg.c +++ b/source/board/numaker_m252kg.c @@ -1,6 +1,6 @@ /** * @file numaker_m252kg.c - * @brief board ID for the NuMaker-M252KG board + * @brief board ID for the Nuvoton NuMaker-M252KG board * * DAPLink Interface Firmware * Copyright (c) 2019 Nuvoton Technology Corp. All Rights Reserved @@ -28,4 +28,6 @@ const board_info_t g_board_info = { .family_id = kStub_SWSysReset_FamilyID, .flags = kEnablePageErase, .target_cfg = &target_device, + .board_vendor = "Nuvoton", + .board_name = "NuMaker-M252KG", }; diff --git a/source/board/numaker_pfm_m487km.c b/source/board/numaker_pfm_m487km.c index 4314db2f9..7feab979f 100644 --- a/source/board/numaker_pfm_m487km.c +++ b/source/board/numaker_pfm_m487km.c @@ -1,6 +1,6 @@ /** * @file numaker_pfm_m487km.c - * @brief board ID for the NuMaker-PFM-M487KM board + * @brief board ID for the Nuvoton NuMaker-PFM-M487KM board * * DAPLink Interface Firmware * Copyright (c) 2020 Nuvoton Technology Corp. All Rights Reserved @@ -28,4 +28,6 @@ const board_info_t g_board_info = { .family_id = kStub_SWSysReset_FamilyID, .flags = kEnablePageErase, .target_cfg = &target_device, + .board_vendor = "Nuvoton", + .board_name = "NuMaker-PFM-M487KM", }; diff --git a/source/board/rtl8195am.c b/source/board/rtl8195am.c index a285f4629..aeab54c2b 100644 --- a/source/board/rtl8195am.c +++ b/source/board/rtl8195am.c @@ -28,6 +28,8 @@ const board_info_t g_board_info = { .board_id = "4600", .family_id = kRealtek_Rtl8195am_FamilyID, .flags = kEnablePageErase, + .daplink_target_url = "https://os.mbed.com/platforms/Realtek-RTL8195AM", .target_cfg = &target_device, + .board_vendor = "Realtek", + .board_name = "RTL8195AM", }; - diff --git a/source/board/ssci_chibi.c b/source/board/ssci_chibi.c index 3b3f8f4c3..7b4757b12 100644 --- a/source/board/ssci_chibi.c +++ b/source/board/ssci_chibi.c @@ -1,6 +1,6 @@ /** * @file sscity.c - * @brief board ID for the Switch Science ty51822r3 board + * @brief board ID for the Switch Science mbed TY51822r3 board * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -29,6 +29,8 @@ const board_info_t g_board_info = { .board_id = "1021", .family_id = kNordic_Nrf51_FamilyID, .daplink_drive_name = "MBED ", + .daplink_target_url = "https://os.mbed.com/platforms/Switch-Science-mbed-TY51822r3", .target_cfg = &target_device_nrf51822_16, + .board_vendor = "Switch Science", + .board_name = "mbed TY51822r3", }; - diff --git a/source/board/sscity.c b/source/board/sscity.c index 2faf81a50..203d95ccd 100644 --- a/source/board/sscity.c +++ b/source/board/sscity.c @@ -1,6 +1,6 @@ /** * @file sscity.c - * @brief board ID for the Switch Science ty51822r3 board + * @brief board ID for the Switch Science mbed TY51822r3 board * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -30,4 +30,6 @@ const board_info_t g_board_info = { .family_id = kNordic_Nrf51_FamilyID, .daplink_drive_name = "MBED ", .target_cfg = &target_device_nrf51822_32, + .board_vendor = "Switch Science", + .board_name = "mbed TY51822r3", }; diff --git a/source/board/stm32f072rb.c b/source/board/stm32f072rb.c index bf9ea6d48..02ba9fb56 100644 --- a/source/board/stm32f072rb.c +++ b/source/board/stm32f072rb.c @@ -1,6 +1,6 @@ /** - * @file stm32f103rb.c - * @brief board ID for the STM32 NUCLEO-F103RB board + * @file stm32f072rb.c + * @brief board information for STMicroelectronics NUCLEO-F072RB * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -27,4 +27,6 @@ const board_info_t g_board_info = { .board_id = "0720", .family_id = kStub_HWReset_FamilyID, .target_cfg = &target_device, + .board_vendor = "STMicroelectronics", + .board_name = "NUCLEO-F072RB", }; diff --git a/source/board/stm32f103rb.c b/source/board/stm32f103rb.c index 369e98783..1be1e6f77 100644 --- a/source/board/stm32f103rb.c +++ b/source/board/stm32f103rb.c @@ -1,6 +1,6 @@ /** * @file stm32f103rb.c - * @brief board ID for the STM32 NUCLEO-F103RB board + * @brief board information for STMicroelectronics NUCLEO-F103RB * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -27,4 +27,6 @@ const board_info_t g_board_info = { .board_id = "0700", .family_id = kStub_HWReset_FamilyID, .target_cfg = &target_device, + .board_vendor = "STMicroelectronics", + .board_name = "NUCLEO-F103RB", }; diff --git a/source/board/stm32f207zg.c b/source/board/stm32f207zg.c index 536352893..2a378258b 100644 --- a/source/board/stm32f207zg.c +++ b/source/board/stm32f207zg.c @@ -1,6 +1,6 @@ /** - * @file stm32f103rb.c - * @brief board ID for the STM32 NUCLEO-F103RB board + * @file stm32f207zg.c + * @brief board information for the STMicroelectronics NUCLEO-F207ZG * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -27,4 +27,6 @@ const board_info_t g_board_info = { .board_id = "0835", .family_id = kStub_HWReset_FamilyID, .target_cfg = &target_device, + .board_vendor = "STMicroelectronics", + .board_name = "NUCLEO-F207ZG", }; diff --git a/source/board/stm32f334r8.c b/source/board/stm32f334r8.c index d34936c29..22fae25fa 100644 --- a/source/board/stm32f334r8.c +++ b/source/board/stm32f334r8.c @@ -1,6 +1,6 @@ /** - * @file stm32f103rb.c - * @brief board ID for the STM32 NUCLEO-F103RB board + * @file stm32f334r8.c + * @brief board information for STMicroelectronics NUCLEO-F334R8 * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -27,4 +27,6 @@ const board_info_t g_board_info = { .board_id = "0735", .family_id = kStub_HWReset_FamilyID, .target_cfg = &target_device, + .board_vendor = "STMicroelectronics", + .board_name = "NUCLEO-F334R8", }; diff --git a/source/board/stm32f401re.c b/source/board/stm32f401re.c index e79e2ec3e..b90a39212 100644 --- a/source/board/stm32f401re.c +++ b/source/board/stm32f401re.c @@ -1,6 +1,6 @@ /** * @file stm32f401re.c - * @brief board ID for the STM32 NUCLEO-F401RE board + * @brief board information for STMicroelectronics NUCLEO-F401RE * * DAPLink Interface Firmware * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved @@ -27,4 +27,6 @@ const board_info_t g_board_info = { .board_id = "0720", .family_id = kStub_HWReset_FamilyID, .target_cfg = &target_device, + .board_vendor = "STMicroelectronics", + .board_name = "NUCLEO-F401RE", }; diff --git a/source/board/stm32f411re.c b/source/board/stm32f411re.c index 6819c35b1..67f9c813a 100644 --- a/source/board/stm32f411re.c +++ b/source/board/stm32f411re.c @@ -1,6 +1,6 @@ /** - * @file stm32f103rb.c - * @brief board ID for the STM32 NUCLEO-F103RB board + * @file stm32f411re.c + * @brief board information for STMicroelectronics NUCLEO-F411RE * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -27,4 +27,6 @@ const board_info_t g_board_info = { .board_id = "0740", .family_id = kStub_HWReset_FamilyID, .target_cfg = &target_device, + .board_vendor = "STMicroelectronics", + .board_name = "NUCLEO-F411RE", }; diff --git a/source/board/stm32f429zi.c b/source/board/stm32f429zi.c index 833d4b5b1..454208066 100644 --- a/source/board/stm32f429zi.c +++ b/source/board/stm32f429zi.c @@ -1,6 +1,6 @@ /** * @file stm32f429zi.c - * @brief board ID for the STM32 NUCLEO-F429ZI board + * @brief board information for STMicroelectronics NUCLEO-F429ZI * * DAPLink Interface Firmware * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved @@ -27,4 +27,6 @@ const board_info_t g_board_info = { .board_id = "0796", .family_id = kStub_HWReset_FamilyID, .target_cfg = &target_device, + .board_vendor = "STMicroelectronics", + .board_name = "NUCLEO-F429ZI", }; diff --git a/source/board/stm32f746zg.c b/source/board/stm32f746zg.c index cf2f0e368..f391a5d1b 100644 --- a/source/board/stm32f746zg.c +++ b/source/board/stm32f746zg.c @@ -1,6 +1,6 @@ /** - * @file stm32f103rb.c - * @brief board ID for the STM32 NUCLEO-F103RB board + * @file stm32f746zg.c + * @brief board information for STMicroelectronics NUCLEO-F746ZG * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -27,4 +27,6 @@ const board_info_t g_board_info = { .board_id = "0816", .family_id = kStub_HWReset_FamilyID, .target_cfg = &target_device, + .board_vendor = "STMicroelectronics", + .board_name = "NUCLEO-F746ZG", }; diff --git a/source/board/stm32l476rg.c b/source/board/stm32l476rg.c index ca2613bf1..34dd88d8f 100644 --- a/source/board/stm32l476rg.c +++ b/source/board/stm32l476rg.c @@ -1,6 +1,6 @@ /** - * @file stm32f103rb.c - * @brief board ID for the STM32 NUCLEO-F103RB board + * @file stm32l476rg.c + * @brief board information for STMicroelectronics NUCLEO-L476RG * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -27,4 +27,6 @@ const board_info_t g_board_info = { .board_id = "0765", .family_id = kStub_HWReset_FamilyID, .target_cfg = &target_device, + .board_vendor = "STMicroelectronics", + .board_name = "NUCLEO-L476RG", }; diff --git a/source/board/ublox_evk_nina_b1.c b/source/board/ublox_evk_nina_b1.c index cffda9d9f..aa6c0178c 100644 --- a/source/board/ublox_evk_nina_b1.c +++ b/source/board/ublox_evk_nina_b1.c @@ -36,5 +36,8 @@ const board_info_t g_board_info = { .board_id = "1237", .family_id = kNordic_Nrf52_FamilyID, .swd_set_target_reset = nina_swd_set_target_reset, + .daplink_target_url = "https://os.mbed.com/platforms/u-blox-EVK-NINA-B1", .target_cfg = &target_device_nrf52_64, + .board_vendor = "u-blox", + .board_name = "EVK-NINA-B1", }; diff --git a/source/board/ublox_evk_odin_w2.c b/source/board/ublox_evk_odin_w2.c index 99cc18c46..2ac636abf 100644 --- a/source/board/ublox_evk_odin_w2.c +++ b/source/board/ublox_evk_odin_w2.c @@ -1,6 +1,6 @@ /** - * @file stm32f429zi.c - * @brief board ID for the STM32 NUCLEO-F429ZI board + * @file ublox_evk_odin_w2.c + * @brief board ID for the u-blox EVK-ODIN-W2 board * * DAPLink Interface Firmware * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved @@ -26,5 +26,8 @@ const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "1236", .family_id = kStub_HWReset_FamilyID, + .daplink_target_url = "https://os.mbed.com/platforms/ublox-EVK-ODIN-W2/", .target_cfg = &target_device, + .board_vendor = "u-blox", + .board_name = "EVK-ODIN-W2", }; diff --git a/source/board/xDot-L151.c b/source/board/xDot-L151.c index e7d42cc66..e7a7803c7 100644 --- a/source/board/xDot-L151.c +++ b/source/board/xDot-L151.c @@ -29,7 +29,7 @@ static uint8_t xdot_set_state(target_state_t state) { uint32_t val; - + if (state == RESET_PROGRAM) { swd_init(); swd_set_target_reset(1); @@ -78,5 +78,7 @@ const board_info_t g_board_info = { .daplink_url_name = "XDOT HTM", .daplink_drive_name = "XDOT ", .target_cfg = &target_device, - .target_set_state = xdot_set_state + .target_set_state = xdot_set_state, + .board_vendor = "MultiTech", + .board_name = "xDot", }; diff --git a/source/family/nuvoton/m2354kjfae/target.c b/source/family/nuvoton/m2354kjfae/target.c index 8abf8e0fd..f47bccdb4 100644 --- a/source/family/nuvoton/m2354kjfae/target.c +++ b/source/family/nuvoton/m2354kjfae/target.c @@ -44,4 +44,6 @@ target_cfg_t target_device = { .ram_regions[0].end = 0x20000000 + 0x40000, .ram_regions[1].start = 0x30000000, .ram_regions[1].end = 0x30000000 + 0x40000, + .target_vendor = "Nuvoton", + .target_part_number = "M2354KJFAE", }; diff --git a/source/family/nuvoton/m252kg6ae/target.c b/source/family/nuvoton/m252kg6ae/target.c index 9c5bb6cd0..4621ff207 100644 --- a/source/family/nuvoton/m252kg6ae/target.c +++ b/source/family/nuvoton/m252kg6ae/target.c @@ -38,4 +38,6 @@ target_cfg_t target_device = { .flash_regions[1].flash_algo = (program_target_t *)&M251_LD_4_flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20008000, + .target_vendor = "Nuvoton", + .target_part_number = "M252KG6AE", }; diff --git a/source/family/nuvoton/m263kiaae/target.c b/source/family/nuvoton/m263kiaae/target.c index 19254a793..399f1c4d0 100644 --- a/source/family/nuvoton/m263kiaae/target.c +++ b/source/family/nuvoton/m263kiaae/target.c @@ -38,4 +38,6 @@ target_cfg_t target_device = { .flash_regions[1].flash_algo = (program_target_t *)&M261_LD_4_flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20018000, + .target_vendor = "Nuvoton", + .target_part_number = "M263KIAAE", }; diff --git a/source/family/nuvoton/m487jidae/target.c b/source/family/nuvoton/m487jidae/target.c index 56dc2a004..841380d6f 100644 --- a/source/family/nuvoton/m487jidae/target.c +++ b/source/family/nuvoton/m487jidae/target.c @@ -41,4 +41,6 @@ target_cfg_t target_device = { .flash_regions[2].flash_algo = (program_target_t *)&M487_AP_SP_flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20028000, + .target_vendor = "Nuvoton", + .target_part_number = "M487JIDAE", }; diff --git a/source/family/st/stm32f072rb/target.c b/source/family/st/stm32f072rb/target.c index 31c4545cf..b2ba6bb10 100644 --- a/source/family/st/stm32f072rb/target.c +++ b/source/family/st/stm32f072rb/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the + * @brief Target information for the STM32F072RB * * DAPLink Interface Firmware * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20004000, + .target_vendor = "STMicroelectronics", + .target_part_number = "STM32F072RBTx", }; diff --git a/source/family/st/stm32f103rb/target.c b/source/family/st/stm32f103rb/target.c index 273e73b59..6ea434701 100644 --- a/source/family/st/stm32f103rb/target.c +++ b/source/family/st/stm32f103rb/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the + * @brief Target information for the STM32F103RB * * DAPLink Interface Firmware * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20005000, + .target_vendor = "STMicroelectronics", + .target_part_number = "STM32F103RB", }; diff --git a/source/family/st/stm32f207zg/target.c b/source/family/st/stm32f207zg/target.c index 57892c664..414da1504 100644 --- a/source/family/st/stm32f207zg/target.c +++ b/source/family/st/stm32f207zg/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the + * @brief Target information for the STM32F207ZG * * DAPLink Interface Firmware * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20020000, + .target_vendor = "STMicroelectronics", + .target_part_number = "STM32F207ZGTx", }; diff --git a/source/family/st/stm32f334r8/target.c b/source/family/st/stm32f334r8/target.c index 49751317e..435a8f155 100644 --- a/source/family/st/stm32f334r8/target.c +++ b/source/family/st/stm32f334r8/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the + * @brief Target information for the STM32F334R8 * * DAPLink Interface Firmware * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20003000, + .target_vendor = "STMicroelectronics", + .target_part_number = "STM32F334R8Tx", }; diff --git a/source/family/st/stm32f401re/target.c b/source/family/st/stm32f401re/target.c index 3445e9e77..83ff7859f 100644 --- a/source/family/st/stm32f401re/target.c +++ b/source/family/st/stm32f401re/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the + * @brief Target information for the STM32F401RE * * DAPLink Interface Firmware * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20018000, + .target_vendor = "STMicroelectronics", + .target_part_number = "STM32F401RETx", }; diff --git a/source/family/st/stm32f407ve/target.c b/source/family/st/stm32f407ve/target.c index 344dc5905..29de0584c 100644 --- a/source/family/st/stm32f407ve/target.c +++ b/source/family/st/stm32f407ve/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the stm32f407 + * @brief Target information for the STM32F407VE * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20020000, + .target_vendor = "STMicroelectronics", + .target_part_number = "STM32F407VETx", }; diff --git a/source/family/st/stm32f411/target.c b/source/family/st/stm32f411/target.c index 9e7f46961..1b97a8541 100644 --- a/source/family/st/stm32f411/target.c +++ b/source/family/st/stm32f411/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the stm32f411 + * @brief Target information for the STM32F411RE * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20020000, + .target_vendor = "STMicroelectronics", + .target_part_number = "STM32F411RETx", }; diff --git a/source/family/st/stm32f412rg/target.c b/source/family/st/stm32f412rg/target.c index bca2cec25..52cb24a11 100644 --- a/source/family/st/stm32f412rg/target.c +++ b/source/family/st/stm32f412rg/target.c @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20040000, + .target_vendor = "STMicroelectronics", + .target_part_number = "STM32F412RGTx", }; diff --git a/source/family/st/stm32f429zi/target.c b/source/family/st/stm32f429zi/target.c index f8cf162dc..555bad131 100644 --- a/source/family/st/stm32f429zi/target.c +++ b/source/family/st/stm32f429zi/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the + * @brief Target information for the STM32F429ZI * * DAPLink Interface Firmware * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20030000, + .target_vendor = "STMicroelectronics", + .target_part_number = "STM32F429ZITx", }; diff --git a/source/family/st/stm32f437vg/target.c b/source/family/st/stm32f437vg/target.c index cd1d76e24..9518d394e 100644 --- a/source/family/st/stm32f437vg/target.c +++ b/source/family/st/stm32f437vg/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the + * @brief Target information for the STM32F437VG * * DAPLink Interface Firmware * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20030000, + .target_vendor = "STMicroelectronics", + .target_part_number = "STM32F437VGTx", }; diff --git a/source/family/st/stm32f439zi/target.c b/source/family/st/stm32f439zi/target.c index f8cf162dc..c248f6e34 100644 --- a/source/family/st/stm32f439zi/target.c +++ b/source/family/st/stm32f439zi/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the + * @brief Target information for the STM32F439ZI * * DAPLink Interface Firmware * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20030000, + .target_vendor = "STMicroelectronics", + .target_part_number = "STM32F439ZITx", }; diff --git a/source/family/st/stm32f746zg/target.c b/source/family/st/stm32f746zg/target.c index d0583c996..d237b7979 100644 --- a/source/family/st/stm32f746zg/target.c +++ b/source/family/st/stm32f746zg/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the + * @brief Target information for the STM32F746ZG * * DAPLink Interface Firmware * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20000000 + 0x50000, + .target_vendor = "STMicroelectronics", + .target_part_number = "STM32F746ZGTx", }; diff --git a/source/family/st/stm32l476rg/target.c b/source/family/st/stm32l476rg/target.c index 7d657c5e0..cff33353a 100644 --- a/source/family/st/stm32l476rg/target.c +++ b/source/family/st/stm32l476rg/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the + * @brief Target information for the STM32L476RG * * DAPLink Interface Firmware * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20018000, + .target_vendor = "STMicroelectronics", + .target_part_number = "STM32L476RGTx", }; diff --git a/source/family/st/stm32l4xx_1024/target.c b/source/family/st/stm32l4xx_1024/target.c index b84b304d1..d25ebad91 100644 --- a/source/family/st/stm32l4xx_1024/target.c +++ b/source/family/st/stm32l4xx_1024/target.c @@ -37,4 +37,6 @@ target_cfg_t target_device_stm32l475 = { .ram_regions[0].end = 0x20000000 + 0x00018000, .ram_regions[1].start = 0x10000188, .ram_regions[1].end = 0x10008000, + .target_vendor = "STMicroelectronics", + .target_part_number = "STM32L486JGYx", }; diff --git a/source/family/st/xDot-L151/target.c b/source/family/st/xDot-L151/target.c index 55e343436..aefbee34c 100644 --- a/source/family/st/xDot-L151/target.c +++ b/source/family/st/xDot-L151/target.c @@ -1,6 +1,6 @@ /** * @file target.c - * @brief Target information for the stm32l151 + * @brief Target information for the STM32L151CC * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved @@ -35,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, .ram_regions[0].end = 0x20000000 + KB(32), + .target_vendor = "STMicroelectronics", + .target_part_number = "STM32L151CCUx", }; From 17f0442db098d62805c892aac6ea29d8a47f71c4 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 21 Oct 2021 01:51:37 -0500 Subject: [PATCH 335/617] github_actions: update GNU Arm Embedded Toolchain to 10.3-2021.07 --- .github/workflows/linux.yml | 8 ++++---- .github/workflows/windows.yml | 7 ++++--- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/.github/workflows/linux.yml b/.github/workflows/linux.yml index 4d3a80569..e6dedd45e 100644 --- a/.github/workflows/linux.yml +++ b/.github/workflows/linux.yml @@ -14,7 +14,7 @@ jobs: id: cache-arm-gcc uses: actions/cache@v2 env: - cache-name: arm-gcc-9-2020-q2 + cache-name: arm-gcc-10.3-2021-07 with: path: ${{ runner.temp }}/arm-gcc key: ${{ runner.os }}-${{ env.cache-name }} @@ -40,11 +40,11 @@ jobs: - name: Install Embedded Arm Toolchain if: steps.cache-arm-gcc.outputs.cache-hit != 'true' run: | - curl -O -L https://developer.arm.com/-/media/Files/downloads/gnu-rm/9-2020q2/gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 - md5sum gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 + curl -O -L https://developer.arm.com/-/media/Files/downloads/gnu-rm/10.3-2021.07/gcc-arm-none-eabi-10.3-2021.07-x86_64-linux.tar.bz2 + md5sum gcc-arm-none-eabi-10.3-2021.07-x86_64-linux.tar.bz2 echo Installing in ${{ runner.temp }}/arm-gcc mkdir -p ${{ runner.temp }}/arm-gcc - tar jvxf gcc-arm-none-eabi-9-2020-q2-update-x86_64-linux.tar.bz2 -C ${{ runner.temp }}/arm-gcc --strip-components 1 + tar jvxf gcc-arm-none-eabi-10.3-2021.07-x86_64-linux.tar.bz2 -C ${{ runner.temp }}/arm-gcc --strip-components 1 - name: Install dependencies run: | diff --git a/.github/workflows/windows.yml b/.github/workflows/windows.yml index 1fa672680..0230c13a1 100644 --- a/.github/workflows/windows.yml +++ b/.github/workflows/windows.yml @@ -11,7 +11,7 @@ jobs: id: cache-arm-gcc uses: actions/cache@v2 env: - cache-name: arm-gcc-9-2020-q2 + cache-name: arm-gcc-10.3-2021-07 with: path: ${{ runner.temp }}/arm-gcc key: ${{ runner.os }}-${{ env.cache-name }} @@ -33,9 +33,10 @@ jobs: - name: Install Embedded Arm Toolchain if: steps.cache-arm-gcc.outputs.cache-hit != 'true' run: | - (New-Object System.Net.WebClient).DownloadFile("https://developer.arm.com/-/media/Files/downloads/gnu-rm/9-2020q2/gcc-arm-none-eabi-9-2020-q2-update-win32.zip","gcc-arm-none-eabi-9-2020-q2-update-win32.zip"); + (New-Object System.Net.WebClient).DownloadFile("https://developer.arm.com/-/media/Files/downloads/gnu-rm/10.3-2021.07/gcc-arm-none-eabi-10.3-2021.07-win32.zip","gcc-arm-none-eabi-10.3-2021.07-win32.zip"); echo "Installing gcc-arm-none-eabi-9-2020-q2-update-win32 in ${{ runner.temp }}\arm-gcc"; - Expand-Archive -Path .\gcc-arm-none-eabi-9-2020-q2-update-win32.zip -DestinationPath ${{ runner.temp }}\arm-gcc -PassThru; + Expand-Archive -Path .\gcc-arm-none-eabi-10.3-2021.07-win32.zip -DestinationPath ${{ runner.temp }} -PassThru; + Rename-Item -Path ${{ runner.temp }}\gcc-arm-none-eabi-10.3-2021.07 -NewName ${{ runner.temp }}\arm-gcc - name: Check Embedded Arm Toolchain run: | From 84f9afb3c6a66f5ca135d806922be02e20fbd384 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 21 Oct 2021 02:06:13 -0500 Subject: [PATCH 336/617] github_actions: remove --ignore-failures from progen_compile.py call --- .github/workflows/linux.yml | 2 +- .github/workflows/windows.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/linux.yml b/.github/workflows/linux.yml index e6dedd45e..555b41fec 100644 --- a/.github/workflows/linux.yml +++ b/.github/workflows/linux.yml @@ -69,7 +69,7 @@ jobs: - name: Compile run: | export PATH="/usr/lib/ccache:${{ runner.temp }}/arm-gcc/bin/:/home/runner/.local/bin:$PATH" - python tools/progen_compile.py --release --parallel -v -v --ignore-failures + python tools/progen_compile.py --release --parallel -v (ls -lR firmware_*; ccache -s; arm-none-eabi-gcc -v) | tee log.txt mkdir bootloaders cp projectfiles/make_gcc_arm/*_bl/build/*_crc.{bin,hex} bootloaders diff --git a/.github/workflows/windows.yml b/.github/workflows/windows.yml index 0230c13a1..be724dc1c 100644 --- a/.github/workflows/windows.yml +++ b/.github/workflows/windows.yml @@ -49,7 +49,7 @@ jobs: - name: Compile run: | - python tools/progen_compile.py -t cmake_gcc_arm -g mingw-make --release --parallel -v --ignore-failures + python tools/progen_compile.py -t cmake_gcc_arm -g mingw-make --release --parallel -v shell: cmd - name: Upload test artifacts From 546c1eca3db1ffbb6d46a025bddf373e2b3da87f Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 19 Oct 2021 23:02:58 -0500 Subject: [PATCH 337/617] deprecation: removing unused stm32f407, stm32f412re and stm32f437vg targets --- source/family/st/stm32f407/flash_blob.c | 71 ---------------------- source/family/st/stm32f407/target.c | 38 ------------ source/family/st/stm32f412re/flash_blob.c | 73 ----------------------- source/family/st/stm32f412re/target.c | 38 ------------ source/family/st/stm32f437vg/flash_blob.c | 65 -------------------- source/family/st/stm32f437vg/target.c | 40 ------------- 6 files changed, 325 deletions(-) delete mode 100644 source/family/st/stm32f407/flash_blob.c delete mode 100644 source/family/st/stm32f407/target.c delete mode 100644 source/family/st/stm32f412re/flash_blob.c delete mode 100644 source/family/st/stm32f412re/target.c delete mode 100644 source/family/st/stm32f437vg/flash_blob.c delete mode 100644 source/family/st/stm32f437vg/target.c diff --git a/source/family/st/stm32f407/flash_blob.c b/source/family/st/stm32f407/flash_blob.c deleted file mode 100644 index 246e90c68..000000000 --- a/source/family/st/stm32f407/flash_blob.c +++ /dev/null @@ -1,71 +0,0 @@ -/** - * @file flash_blob.c - * @brief Flash algorithm for the stm32f407 - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "flash_blob.h" - - -static const uint32_t STM32F407_FLM[] = { - 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, - - /*0x020*/ 0xe000300, 0xd3022820L, 0x1d000940, 0x28104770, 0x900d302, 0x47701cc0, 0x47700880, 0x49414842, - /*0x040*/ 0x49426041, 0x21006041, 0x68c16001, 0x431122f0, 0x694060c1, 0xd4060680L, 0x493d483e, 0x21066001, - /*0x060*/ 0x493d6041, 0x20006081, 0x48374770, 0x5426901, 0x61014311, 0x47702000, 0x4833b510, 0x24046901, - /*0x080*/ 0x61014321, 0x3a26901, 0x61014311, 0x4a314933, 0x6011e000, 0x3db68c3, 0x6901d4fb, 0x610143a1, - /*0x0A0*/ 0xbd102000L, 0xf7ffb530L, 0x4927ffbb, 0x23f068ca, 0x60ca431a, 0x610c2402, 0x700690a, 0x43020e40, - /*0x0C0*/ 0x6908610a, 0x431003e2, 0x48246108, 0xe0004a21L, 0x68cd6010, 0xd4fb03edL, 0x43a06908, 0x68c86108, - /*0x0E0*/ 0xf000600, 0x68c8d003, 0x60c84318, 0xbd302001L, 0x4d15b570, 0x8891cc9, 0x8968eb, 0x433326f0, - /*0x100*/ 0x230060eb, 0x4b16612b, 0x692ce017, 0x612c431c, 0x60046814, 0x3e468ec, 0x692cd4fc, 0x640864, - /*0x120*/ 0x68ec612c, 0xf240624, 0x68e8d004, 0x60e84330, 0xbd702001L, 0x1d121d00, 0x29001f09, 0x2000d1e5, - /*0x140*/ 0xbd70, 0x45670123, 0x40023c00, 0xcdef89abL, 0x5555, 0x40003000, 0xfff, 0xaaaa, - /*0x160*/ 0x201, 0x0, -}; - -/** -* List of start and size for each size of flash sector -* The size will apply to all sectors between the listed address and the next address -* in the list. -* The last pair in the list will have sectors starting at that address and ending -* at address start + size. -*/ -static const sector_info_t sectors_info[] = { - {0x08000000, 1024}, -}; - -static const program_target_t flash = { - 0x2000003D, // Init - 0x2000006B, // UnInit - 0x20000079, // EraseChip - 0x200000A5, // EraseSector - 0x200000F1, // ProgramPage - 0x0, // Verify - -// RSB : base adreess is address of Execution Region PrgData in map file -// to access global/static data -// RSP : Initial stack pointer - - {0x20000001, 0x20000020 + 0x00000144, 0x20002000}, // {breakpoint, RSB, RSP} - - 0x20001000, // program_buffer - 0x20000000, // algo_start - 0x00000170, // algo_size - STM32F407_FLM,// image - 512 // ram_to_flash_bytes_to_be_written -}; diff --git a/source/family/st/stm32f407/target.c b/source/family/st/stm32f407/target.c deleted file mode 100644 index 56765e536..000000000 --- a/source/family/st/stm32f407/target.c +++ /dev/null @@ -1,38 +0,0 @@ -/** - * @file target.c - * @brief Target information for the stm32f407 - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_config.h" - -// The file flash_blob.c must only be included in target.c -#include "flash_blob.c" - -// target information -target_cfg_t target_device = { - .version = kTargetConfigVersion, - .sectors_info = sectors_info, - .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), - .flash_regions[0].start = 0x08000000, - .flash_regions[0].end = 0x08100000, - .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, - .ram_regions[0].start = 0x20000000, - .ram_regions[0].end = 0x20020000, -}; diff --git a/source/family/st/stm32f412re/flash_blob.c b/source/family/st/stm32f412re/flash_blob.c deleted file mode 100644 index 68bf4b815..000000000 --- a/source/family/st/stm32f412re/flash_blob.c +++ /dev/null @@ -1,73 +0,0 @@ -/* Flash OS Routines (Automagically Generated) - * Copyright (c) 2009-2019 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - #include "flash_blob.h" - -static const uint32_t _flash_prog_blob[] = { - 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, - 0x03004601, 0x28200e00, 0x0940d302, 0xe0051d00, 0xd3022810, 0x1cc00900, 0x0880e000, 0xd50102c9, - 0x43082110, 0x48424770, 0x60414940, 0x60414941, 0x60012100, 0x22f068c1, 0x60c14311, 0x06806940, - 0x483ed406, 0x6001493c, 0x60412106, 0x6081493c, 0x47702000, 0x69014836, 0x43110542, 0x20006101, - 0xb5104770, 0x69014832, 0x43212404, 0x69016101, 0x431103a2, 0x49336101, 0xe0004a30, 0x68c36011, - 0xd4fb03db, 0x43a16901, 0x20006101, 0xb530bd10, 0xffb6f7ff, 0x68ca4926, 0x431a23f0, 0x240260ca, - 0x690a610c, 0x0e0006c0, 0x610a4302, 0x03e26908, 0x61084310, 0x4a214823, 0x6010e000, 0x03ed68cd, - 0x6908d4fb, 0x610843a0, 0x060068c8, 0xd0030f00, 0x431868c8, 0x200160c8, 0xb570bd30, 0x1cc94d14, - 0x68eb0889, 0x26f00089, 0x60eb4333, 0x612b2300, 0xe0174b15, 0x431c692c, 0x6814612c, 0x68ec6004, - 0xd4fc03e4, 0x0864692c, 0x612c0064, 0x062468ec, 0xd0040f24, 0x433068e8, 0x200160e8, 0x1d00bd70, - 0x1f091d12, 0xd1e52900, 0xbd702000, 0x45670123, 0x40023c00, 0xcdef89ab, 0x00005555, 0x40003000, - 0x00000fff, 0x0000aaaa, 0x00000201, 0x00000000 -}; - -// Start address of flash -static const uint32_t flash_start = 0x08000000; -// Size of flash -static const uint32_t flash_size = 0x00080000; - -/** -* List of start and size for each size of flash sector - even indexes are start, odd are size -* The size will apply to all sectors between the listed address and the next address -* in the list. -* The last pair in the list will have sectors starting at that address and ending -* at address flash_start + flash_size. -*/ -static const sector_info_t sectors_info[] = { - { 0x08000000, 0x00004000 }, - { 0x08010000, 0x00010000 }, - { 0x08020000, 0x00010000 }, -}; - -static const program_target_t flash = { - 0x20000047, // Init - 0x20000075, // UnInit - 0x20000083, // EraseChip - 0x200000af, // EraseSector - 0x200000fb, // ProgramPage - 0x0, // Verify - - // BKPT : start of blob + 1 - // RSB : blob start + header + rw data offset - // RSP : stack pointer - { - 0x20000001, - 0x2000016c, - 0x20000800 - }, - - 0x20000000 + 0x00000A00, // mem buffer location - 0x20000000, // location to write prog_blob in target RAM - sizeof(_flash_prog_blob), // prog_blob size - _flash_prog_blob, // address of prog_blob - 0x00000400 // ram_to_flash_bytes_to_be_written -}; diff --git a/source/family/st/stm32f412re/target.c b/source/family/st/stm32f412re/target.c deleted file mode 100644 index ef7cc5791..000000000 --- a/source/family/st/stm32f412re/target.c +++ /dev/null @@ -1,38 +0,0 @@ -/** - * @file target.c - * @brief Target information for the stm32f412re - * - * DAPLink Interface Firmware - * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_config.h" - -// The file flash_blob.c must only be included in target.c -#include "flash_blob.c" - -// target information -target_cfg_t target_device = { - .version = kTargetConfigVersion, - .sectors_info = sectors_info, - .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), - .flash_regions[0].start = 0x08000000, - .flash_regions[0].end = 0x08080000, - .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, - .ram_regions[0].start = 0x20000000, - .ram_regions[0].end = 0x20040000, -}; diff --git a/source/family/st/stm32f437vg/flash_blob.c b/source/family/st/stm32f437vg/flash_blob.c deleted file mode 100644 index 4d303dfe7..000000000 --- a/source/family/st/stm32f437vg/flash_blob.c +++ /dev/null @@ -1,65 +0,0 @@ -/* Flash OS Routines (Automagically Generated) - * Copyright (c) 2009-2019 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -static const uint32_t STM32F437VG_flash_prog_blob[] = { - 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, - 0x0e000300, 0xd3022820, 0x1d000940, 0x28104770, 0x0900d302, 0x47701cc0, 0x47700880, 0x49414842, - 0x49426041, 0x21006041, 0x68c16001, 0x431122f0, 0x694060c1, 0xd4060680, 0x493d483e, 0x21066001, - 0x493d6041, 0x20006081, 0x48374770, 0x05426901, 0x61014311, 0x47702000, 0x4833b510, 0x24046901, - 0x61014321, 0x03a26901, 0x61014311, 0x4a314933, 0x6011e000, 0x03db68c3, 0x6901d4fb, 0x610143a1, - 0xbd102000, 0xf7ffb530, 0x4927ffbb, 0x23f068ca, 0x60ca431a, 0x610c2402, 0x0700690a, 0x43020e40, - 0x6908610a, 0x431003e2, 0x48246108, 0xe0004a21, 0x68cd6010, 0xd4fb03ed, 0x43a06908, 0x68c86108, - 0x0f000600, 0x68c8d003, 0x60c84318, 0xbd302001, 0x4d15b570, 0x08891cc9, 0x008968eb, 0x433326f0, - 0x230060eb, 0x4b16612b, 0x692ce017, 0x612c431c, 0x60046814, 0x03e468ec, 0x692cd4fc, 0x00640864, - 0x68ec612c, 0x0f240624, 0x68e8d004, 0x60e84330, 0xbd702001, 0x1d121d00, 0x29001f09, 0x2000d1e5, - 0x0000bd70, 0x45670123, 0x40023c00, 0xcdef89ab, 0x00005555, 0x40003000, 0x00000fff, 0x0000aaaa, - 0x00000201, 0x00000000 -}; - -/** -* List of start and size for each size of flash sector -* The size will apply to all sectors between the listed address and the next address -* in the list. -* The last pair in the list will have sectors starting at that address and ending -* at address start + size. -*/ -static const sector_info_t sectors_info[] = { - {0x08000000, 0x4000}, -}; - -static const program_target_t flash = { - 0x2000003d, // Init - 0x2000006b, // UnInit - 0x20000079, // EraseChip - 0x200000a5, // EraseSector - 0x200000f1, // ProgramPage - 0x0, // Verify - - // BKPT : start of blob + 1 - // RSB : blob start + header + rw data offset - // RSP : stack pointer - { - 0x20000001, - 0x20000164, - 0x20000800 - }, - - 0x20000000 + 0x00000A00, // mem buffer location - 0x20000000, // location to write prog_blob in target RAM - sizeof(STM32F437VG_flash_prog_blob), // prog_blob size - STM32F437VG_flash_prog_blob, // address of prog_blob - 0x00000400 // ram_to_flash_bytes_to_be_written -}; diff --git a/source/family/st/stm32f437vg/target.c b/source/family/st/stm32f437vg/target.c deleted file mode 100644 index 9518d394e..000000000 --- a/source/family/st/stm32f437vg/target.c +++ /dev/null @@ -1,40 +0,0 @@ -/** - * @file target.c - * @brief Target information for the STM32F437VG - * - * DAPLink Interface Firmware - * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_config.h" - -// The file flash_blob.c must only be included in target.c -#include "flash_blob.c" - -// target information -target_cfg_t target_device = { - .version = kTargetConfigVersion, - .sectors_info = sectors_info, - .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), - .flash_regions[0].start = 0x08000000, - .flash_regions[0].end = 0x08100000, - .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, - .ram_regions[0].start = 0x20000000, - .ram_regions[0].end = 0x20030000, - .target_vendor = "STMicroelectronics", - .target_part_number = "STM32F437VGTx", -}; From 966e8c3a29d6a4e4fbeb794a610e7dcf992be358 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 19 Oct 2021 23:04:59 -0500 Subject: [PATCH 338/617] deprecation: remove lpc11u35_arm_watch_efm32_if project --- projects.yaml | 4 ---- records/board/arm_watch_efm32.yaml | 6 ------ source/board/arm_watch_efm32.c | 30 ------------------------------ test/info.py | 1 - 4 files changed, 41 deletions(-) delete mode 100644 records/board/arm_watch_efm32.yaml delete mode 100644 source/board/arm_watch_efm32.c diff --git a/projects.yaml b/projects.yaml index 9d52cfde0..4e4bd03d3 100644 --- a/projects.yaml +++ b/projects.yaml @@ -363,10 +363,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/archpro.yaml - lpc11u35_arm_watch_efm32_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/arm_watch_efm32.yaml lpc11u35_arm_watch_nrf51_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/arm_watch_efm32.yaml b/records/board/arm_watch_efm32.yaml deleted file mode 100644 index 24fb3e77a..000000000 --- a/records/board/arm_watch_efm32.yaml +++ /dev/null @@ -1,6 +0,0 @@ -common: - sources: - board: - - source/board/arm_watch_efm32.c - family: - - source/family/siliconlabs/efm32gg/target.c diff --git a/source/board/arm_watch_efm32.c b/source/board/arm_watch_efm32.c deleted file mode 100644 index 4e9a54a42..000000000 --- a/source/board/arm_watch_efm32.c +++ /dev/null @@ -1,30 +0,0 @@ -/** - * @file arm_watch_efm32.c - * @brief board ID for the ARM Wearable Reference Design EFM32 MCU - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_board.h" -#include "target_family.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "5051", - .family_id = kStub_SWSysReset_FamilyID, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index 0eb566708..c7802cf42 100644 --- a/test/info.py +++ b/test/info.py @@ -273,7 +273,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x5007, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_musca_b_if', None, 'ARM_MUSCA_B1' ), ( 0x5007, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_musca_b_eflash_if', None, 'ARM_MUSCA_B1' ), ( 0x5050, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_arm_watch_stm32f411_if', None, None ), - ( 0x5051, VENDOR_TO_FAMILY('Stub', 3), 'lpc11u35_arm_watch_efm32_if', None, None ), ( 0x5052, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_arm_watch_nrf51_if', None, None ), ( 0x5500, VENDOR_TO_FAMILY('Renesas', 1), 'lpc11u35_gr_peach_if', None, None ), # TODO - Set to 'Renesas-GR-PEACH' once this target builds ( 0x5501, VENDOR_TO_FAMILY('Renesas', 1), 'lpc11u35_gr_lychee_if', None, None ), # TODO - Set to 'Renesas-GR-LYCHEE' once this target builds From 5e33bab79a84b1b26b7492a771fb5ed64c91f0b3 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 19 Oct 2021 23:05:21 -0500 Subject: [PATCH 339/617] deprecation: remove unused efm32gg target --- .../family/siliconlabs/efm32gg/flash_blob.c | 82 ------------------- source/family/siliconlabs/efm32gg/target.c | 38 --------- 2 files changed, 120 deletions(-) delete mode 100644 source/family/siliconlabs/efm32gg/flash_blob.c delete mode 100644 source/family/siliconlabs/efm32gg/target.c diff --git a/source/family/siliconlabs/efm32gg/flash_blob.c b/source/family/siliconlabs/efm32gg/flash_blob.c deleted file mode 100644 index 1da2c4d2c..000000000 --- a/source/family/siliconlabs/efm32gg/flash_blob.c +++ /dev/null @@ -1,82 +0,0 @@ -/** - * @file flash_blob.c - * @brief Flash algorithm for the efm32gg - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "flash_blob.h" - -static const uint32_t efm32gg_flash_prog_blob[] = { - 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, - 0x4770ba40, 0x4770bac0, 0x4c0cb510, 0xf04068a0, 0x60a00001, 0x301af246, 0xf44f6560, 0x60e07040, - 0x20012100, 0xf83ef000, 0x65612100, 0xf02168a1, 0x60a10101, 0xbf182800, 0xbd102001, 0x400c0000, - 0x4684b510, 0xf44f2300, 0xf8505180, 0x1f092b04, 0x1c52d002, 0xe001d0f9, 0xd0131c50, 0x68a04c0c, - 0x0001f040, 0xf8c460a0, 0x2001c010, 0x200260e0, 0x210060e0, 0xf0002001, 0x4603f815, 0xf02068a0, - 0x60a00001, 0xbf142b00, 0x20002001, 0x0000bd10, 0x400c0000, 0xf6414902, 0x63c83071, 0x47702000, - 0x400c0000, 0x4b14b410, 0xc050f8df, 0x201cf8dc, 0x0f16f012, 0xf8dcd014, 0xf0200008, 0xf8cc0005, - 0xf0120008, 0xbf1e0f02, 0x0001f06f, 0x4770bc10, 0x0f04f012, 0xf04fbf1e, 0xbc1030ff, 0xe0074770, - 0x428a4002, 0xbc10d102, 0x47702000, 0xd1dd1e5b, 0xf06fbc10, 0x47700002, 0x00989680, 0x400c0000, - 0x4df0e92d, 0x1cc84604, 0x0603f020, 0x46904859, 0xf0416881, 0x60810101, 0xd9732e07, 0x0f07f014, - 0xf8d8d011, 0x61041000, 0x60c22201, 0x21086181, 0x210060c1, 0xf7ff4610, 0x2800ffb5, 0x1d24d17e, - 0x0810f108, 0x484b1f36, 0xf0416881, 0x60810104, 0xbf882e07, 0x0a02f06f, 0xf504d966, 0x46015080, - 0x010bf36f, 0x42b11b09, 0x4635bf8e, 0x000bf36f, 0xf0151b05, 0xbf180f04, 0x46471f2d, 0x20012100, - 0xff90f7ff, 0xd13b2800, 0xe0e8f8df, 0x4010f8ce, 0xf8ce2001, 0xf857000c, 0xf8ce0b04, 0xf8570018, - 0xf8ce0b04, 0x20080018, 0x000cf8ce, 0x0208f1a5, 0xd9332a07, 0x0b08f04f, 0x46dc482f, 0x101cf8de, - 0x0f16f011, 0xf8ded012, 0xf0200008, 0xf8ce0005, 0xf0110008, 0xbf180f02, 0x0001f06f, 0xf011d10f, - 0xbf180f04, 0x30fff04f, 0xe007d109, 0x010bea01, 0xd1014561, 0xe0022000, 0xd1df1e40, 0xb1104650, - 0xe00bb9e0, 0xf857e01c, 0xf8ce0b04, 0xf8570018, 0xf8ce0b04, 0x3a080018, 0xd8cb2a07, 0xeb081b76, - 0x442c0885, 0xd8982e07, 0x20012100, 0xff3af7ff, 0x4810b920, 0xf0216881, 0xe0000104, 0x6081e00f, - 0x480cb186, 0x1000f8d8, 0x22016104, 0x618160c2, 0x60c12108, 0x46102100, 0xff24f7ff, 0x2001b110, - 0x8df0e8bd, 0x68814803, 0x0101f021, 0x20006081, 0x8df0e8bd, 0x400c0000, 0x00989680, 0x68814803, - 0x0105f021, 0x20006081, 0x00004770, 0x400c0000, 0x00000000, -}; - -/** -* List of start and size for each size of flash sector -* The size will apply to all sectors between the listed address and the next address -* in the list. -* The last pair in the list will have sectors starting at that address and ending -* at address start + size. -*/ -static const sector_info_t sectors_info[] = { - {0, 4096}, -}; - -static const program_target_t flash = { - 0x200000B5, // Init - 0x2000029D, // UnInit - 0x20000029, // EraseChip - 0x20000061, // EraseSector - 0x20000121, // ProgramPage - 0x0, // Verify - - // BKPT : start of blob + 1 - // RSB : blob start + header + rw data offset - // RSP : stack pointer - { - 0x20000000 + 0x00000001, - 0x20000000 + 0x00000020 + 0x00000290, - 0x20000800 - }, - - 0x20000000 + 0x00000A00, // mem buffer location - 0x20000000, // location to write prog_blob in target RAM - sizeof(efm32gg_flash_prog_blob), // prog_blob size - efm32gg_flash_prog_blob, // address of prog_blob - 0x00000200 // ram_to_flash_bytes_to_be_written -}; diff --git a/source/family/siliconlabs/efm32gg/target.c b/source/family/siliconlabs/efm32gg/target.c deleted file mode 100644 index cff78867c..000000000 --- a/source/family/siliconlabs/efm32gg/target.c +++ /dev/null @@ -1,38 +0,0 @@ -/** - * @file target.c - * @brief Target information for the efm32gg - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_config.h" - -// The file flash_blob.c must only be included in target.c -#include "flash_blob.c" - -// target information -target_cfg_t target_device = { - .version = kTargetConfigVersion, - .sectors_info = sectors_info, - .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), - .flash_regions[0].start = 0, - .flash_regions[0].end = MB(1), - .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, - .ram_regions[0].start = 0x20000000, - .ram_regions[0].end = 0x20010000, -}; From 517ddb92e50cfb46891ef954c1061036e00b7d46 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 19 Oct 2021 23:06:06 -0500 Subject: [PATCH 340/617] deprecation: remove lpc11u35_arm_watch_nrf51_if project --- projects.yaml | 4 ---- records/board/arm_watch_nrf51.yaml | 7 ------- source/board/arm_watch_nrf51.c | 32 ------------------------------ test/info.py | 1 - 4 files changed, 44 deletions(-) delete mode 100644 records/board/arm_watch_nrf51.yaml delete mode 100644 source/board/arm_watch_nrf51.c diff --git a/projects.yaml b/projects.yaml index 4e4bd03d3..bc697eaa7 100644 --- a/projects.yaml +++ b/projects.yaml @@ -363,10 +363,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/archpro.yaml - lpc11u35_arm_watch_nrf51_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/arm_watch_nrf51.yaml lpc11u35_arm_watch_stm32f411_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/arm_watch_nrf51.yaml b/records/board/arm_watch_nrf51.yaml deleted file mode 100644 index b5ef8a0d8..000000000 --- a/records/board/arm_watch_nrf51.yaml +++ /dev/null @@ -1,7 +0,0 @@ -common: - sources: - board: - - source/board/arm_watch_nrf51.c - family: - - source/family/nordic/nrf51822/target_nrf51.c - - source/family/nordic/target_reset_nrf51.c diff --git a/source/board/arm_watch_nrf51.c b/source/board/arm_watch_nrf51.c deleted file mode 100644 index 5e60a87c6..000000000 --- a/source/board/arm_watch_nrf51.c +++ /dev/null @@ -1,32 +0,0 @@ -/** - * @file arm_watch_nrf51.c - * @brief board ID for the ARM Wearable Reference Design nRF51822 MCU - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_board.h" -#include "target_family.h" - -extern target_cfg_t target_device_nrf51822_16; - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "5052", - .family_id = kNordic_Nrf51_FamilyID, - .target_cfg = &target_device_nrf51822_16, -}; diff --git a/test/info.py b/test/info.py index c7802cf42..7593ca1c9 100644 --- a/test/info.py +++ b/test/info.py @@ -273,7 +273,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x5007, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_musca_b_if', None, 'ARM_MUSCA_B1' ), ( 0x5007, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_musca_b_eflash_if', None, 'ARM_MUSCA_B1' ), ( 0x5050, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_arm_watch_stm32f411_if', None, None ), - ( 0x5052, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_arm_watch_nrf51_if', None, None ), ( 0x5500, VENDOR_TO_FAMILY('Renesas', 1), 'lpc11u35_gr_peach_if', None, None ), # TODO - Set to 'Renesas-GR-PEACH' once this target builds ( 0x5501, VENDOR_TO_FAMILY('Renesas', 1), 'lpc11u35_gr_lychee_if', None, None ), # TODO - Set to 'Renesas-GR-LYCHEE' once this target builds ( 0x6660, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_nz32_sc151_if', None, None ), # TODO - set target to 'NZ32-SC151' when mbed-os supports this From dfce1f18cc6c727a97ab14de2981d3bd43911589 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 19 Oct 2021 23:11:58 -0500 Subject: [PATCH 341/617] deprecation: remove lpc11u35_arm_watch_stm32f411_if project --- projects.yaml | 4 ---- records/board/arm_watch_stm32f411.yaml | 6 ----- source/board/arm_watch_stm32f411.c | 31 -------------------------- test/info.py | 1 - 4 files changed, 42 deletions(-) delete mode 100644 records/board/arm_watch_stm32f411.yaml delete mode 100644 source/board/arm_watch_stm32f411.c diff --git a/projects.yaml b/projects.yaml index bc697eaa7..270ad6eb2 100644 --- a/projects.yaml +++ b/projects.yaml @@ -363,10 +363,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/archpro.yaml - lpc11u35_arm_watch_stm32f411_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/arm_watch_stm32f411.yaml lpc11u35_blueninja_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/arm_watch_stm32f411.yaml b/records/board/arm_watch_stm32f411.yaml deleted file mode 100644 index 84cc8beed..000000000 --- a/records/board/arm_watch_stm32f411.yaml +++ /dev/null @@ -1,6 +0,0 @@ -common: - sources: - board: - - source/board/arm_watch_stm32f411.c - family: - - source/family/st/stm32f411/target.c diff --git a/source/board/arm_watch_stm32f411.c b/source/board/arm_watch_stm32f411.c deleted file mode 100644 index 15de94db4..000000000 --- a/source/board/arm_watch_stm32f411.c +++ /dev/null @@ -1,31 +0,0 @@ -/** - * @file arm_watch_stm32f411.c - * @brief board ID for the ARM Wearable Reference Design STM32F411 MCU - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "5050", - .family_id = kStub_HWReset_FamilyID, - .target_cfg = &target_device, -}; - diff --git a/test/info.py b/test/info.py index 7593ca1c9..e084404c3 100644 --- a/test/info.py +++ b/test/info.py @@ -272,7 +272,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x5006, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_musca_a_if', None, 'ARM_MUSCA_A1' ), ( 0x5007, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_musca_b_if', None, 'ARM_MUSCA_B1' ), ( 0x5007, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_musca_b_eflash_if', None, 'ARM_MUSCA_B1' ), - ( 0x5050, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_arm_watch_stm32f411_if', None, None ), ( 0x5500, VENDOR_TO_FAMILY('Renesas', 1), 'lpc11u35_gr_peach_if', None, None ), # TODO - Set to 'Renesas-GR-PEACH' once this target builds ( 0x5501, VENDOR_TO_FAMILY('Renesas', 1), 'lpc11u35_gr_lychee_if', None, None ), # TODO - Set to 'Renesas-GR-LYCHEE' once this target builds ( 0x6660, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_nz32_sc151_if', None, None ), # TODO - set target to 'NZ32-SC151' when mbed-os supports this From 750ccc5dacd8e1d543bd251a33fb0e80ece50d7b Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 19 Oct 2021 23:23:02 -0500 Subject: [PATCH 342/617] deprecation: remove lpc11u35_dipdap_cc3220sf_if project --- projects.yaml | 8 -------- records/board/cocorico.yaml | 6 ------ records/board/dipdap_cc3220sf.yaml | 9 --------- source/board/cocorico.c | 30 ----------------------------- source/board/dipdap_cc3220sf.c | 31 ------------------------------ test/info.py | 4 ---- 6 files changed, 88 deletions(-) delete mode 100644 records/board/cocorico.yaml delete mode 100644 records/board/dipdap_cc3220sf.yaml delete mode 100644 source/board/cocorico.c delete mode 100644 source/board/dipdap_cc3220sf.c diff --git a/projects.yaml b/projects.yaml index 270ad6eb2..c7c683f49 100644 --- a/projects.yaml +++ b/projects.yaml @@ -371,14 +371,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/c027.yaml - lpc11u35_cocorico_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/cocorico.yaml - lpc11u35_dipdap_cc3220sf_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/dipdap_cc3220sf.yaml lpc11u35_dipdap_sdt32429b_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/cocorico.yaml b/records/board/cocorico.yaml deleted file mode 100644 index 76c379b71..000000000 --- a/records/board/cocorico.yaml +++ /dev/null @@ -1,6 +0,0 @@ -common: - sources: - board: - - source/board/cocorico.c - family: - - source/family/nxp/lpc812/target.c diff --git a/records/board/dipdap_cc3220sf.yaml b/records/board/dipdap_cc3220sf.yaml deleted file mode 100644 index 53f64d18b..000000000 --- a/records/board/dipdap_cc3220sf.yaml +++ /dev/null @@ -1,9 +0,0 @@ -common: - sources: - macros: - - SOFT_RESET=VECTRESET - board: - - source/board/dipdap_cc3220sf.c - family: - - source/family/ti/cc3220sf/target.c - - source/family/ti/target_reset_ti.c diff --git a/source/board/cocorico.c b/source/board/cocorico.c deleted file mode 100644 index e6b0f8f1e..000000000 --- a/source/board/cocorico.c +++ /dev/null @@ -1,30 +0,0 @@ -/** - * @file cocorico.c - * @brief board ID for the Elektor CoCo-ri-Co! board - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "C000", - .family_id = kStub_HWReset_FamilyID, - .target_cfg = &target_device, -}; diff --git a/source/board/dipdap_cc3220sf.c b/source/board/dipdap_cc3220sf.c deleted file mode 100644 index f395793a0..000000000 --- a/source/board/dipdap_cc3220sf.c +++ /dev/null @@ -1,31 +0,0 @@ -/** - * @file dipdap_cc3220sf.c - * @brief board ID for the dipdap cc3220sf board - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "3300", - .family_id = kTI_Cc3220sf_FamilyID, - .flags = kEnablePageErase, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index e084404c3..af4d1668a 100644 --- a/test/info.py +++ b/test/info.py @@ -118,7 +118,6 @@ ('lpc11u35_mtb_ublox_odin_w2_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_mts_dragonfly_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_mts_xdot_if', False, 0x0000, "bin" ), - ('lpc11u35_dipdap_cc3220sf_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_laird_bl654_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_murata_bl241_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_stm_s2lp_if', False, 0x0000, "bin" ), @@ -267,7 +266,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x3105, VENDOR_TO_FAMILY('NXP', 1), 'lpc11u35_dipdap_sdt64b_if', None, None ), ( 0x3103, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_dipdap_sdt51822b_if', None, None ), ( 0x3110, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_dipdap_sdt32439b_if', None, None ), - ( 0x3300, VENDOR_TO_FAMILY('TI', 1), 'lpc11u35_dipdap_cc3220sf_if', None, 'CC3220SF' ), ( 0x4600, VENDOR_TO_FAMILY('Realtek', 1), 'lpc11u35_rtl8195am_if', None, 'REALTEK-RTL8195AM' ), ( 0x5006, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_musca_a_if', None, 'ARM_MUSCA_A1' ), ( 0x5007, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_musca_b_if', None, 'ARM_MUSCA_B1' ), @@ -295,7 +293,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x9903, VENDOR_TO_FAMILY('Nordic', 2), 'kl27z_microbit_if', 'kl27z_bl', 'Microbitv2' ), ( 0x9904, VENDOR_TO_FAMILY('Nordic', 2), 'kl27z_microbit_if', 'kl27z_bl', 'Microbitv2' ), ( 0xA127, VENDOR_TO_FAMILY('Ambiq', 1), 'kl26z_artemis_dk_if', 'kl26z_bl', 'ARTMBED' ), - ( 0xC000, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_cocorico_if', None, 'CoCo-ri-Co' ), ( 0xC006, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_vbluno51_if', None, 'VBLUNO51' ), ( 0xC005, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_mtconnect04s_if', None, 'MtConnect04S' ), ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'kl26z_if', None, None ), @@ -385,7 +382,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y 0x3105, # dipdap_sdt64b 0x3108, # dipdap_sdt32429b 0x3110, # dipdap_sdt32439b - 0x3300, # dipdap_cc3220sf 0x4600, # REALTEK-RTL8195AM 0x5500, # GR-PEACH 0x5501, # GR-LYCHEE From a639707ac14e837a613edb4d5d24523395dbe88e Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 19 Oct 2021 23:29:17 -0500 Subject: [PATCH 343/617] deprecation: remove unused cc3220sf target --- source/family/ti/cc3220sf/flash_blob.c | 86 -------------------------- source/family/ti/cc3220sf/target.c | 38 ------------ 2 files changed, 124 deletions(-) delete mode 100644 source/family/ti/cc3220sf/flash_blob.c delete mode 100644 source/family/ti/cc3220sf/target.c diff --git a/source/family/ti/cc3220sf/flash_blob.c b/source/family/ti/cc3220sf/flash_blob.c deleted file mode 100644 index 6272c1c17..000000000 --- a/source/family/ti/cc3220sf/flash_blob.c +++ /dev/null @@ -1,86 +0,0 @@ -/* Flash OS Routines (Automagically Generated) - * Copyright (c) 2009-2019 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -static const uint32_t cc3220sf_flash_prog_blob[] = { - 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, - 0xd1fd3801, 0x49964770, 0x6e48b418, 0x0000f440, 0x4b946648, 0xf241681a, 0x380140d5, 0xf042d1fd, - 0x60180010, 0x40d5f241, 0xd1fd3801, 0xf8d24a8e, 0xf040016c, 0xf8c2003c, 0x4b8c016c, 0xf0406c98, - 0x64980001, 0x6480f44f, 0x6cd86820, 0x0001f040, 0xf04f64d8, 0xf8cd0c00, 0x9800c000, 0x90001c40, - 0xd3fa2810, 0xf0206cd8, 0x64d80001, 0xf0206c98, 0x64980001, 0x68c0487e, 0x0ffff010, 0x487dd106, - 0xc000f8c0, 0x40d5f241, 0xd1fd3801, 0x00c8f8d1, 0x2802b2c0, 0xf8d2d113, 0xf0200110, 0xf420000f, - 0xf0406040, 0xf8c20002, 0xf8d20110, 0xf0200114, 0xf420000f, 0xf0406040, 0xf8c20002, 0xf8d20114, - 0xf0400184, 0xf8c20002, 0x486b0184, 0xf3c06800, 0x280e5083, 0x00b0f8d1, 0x007cf420, 0xf440bf0c, - 0xf4400048, 0xf8c10024, 0x486400b0, 0xf0236803, 0x60035380, 0xb2806820, 0xd2062802, 0x00a8f8d1, - 0x0004f040, 0x00a8f8c1, 0x6820e022, 0xd01f0c00, 0x0188f8d2, 0x00e1f040, 0x0188f8c2, 0x68034858, - 0x0f01f013, 0x6803d014, 0x0301f023, 0xf8d26003, 0xf4400188, 0xf8c27000, 0x48520188, 0xf0226802, - 0x60020201, 0xf8c01d00, 0x1d00c000, 0xc000f8c0, 0x6800484d, 0xf3c00f02, 0x2a036003, 0xd22cd00f, - 0x6800484a, 0x1080f3c0, 0x6a88b158, 0x0080f020, 0x69086288, 0x4070f020, 0x5080f040, 0xb9e0e01c, - 0x6a48e7ee, 0x000ff020, 0x6070f420, 0x30c0f420, 0x0001f040, 0x60a0f440, 0x3080f440, 0x6a886248, - 0x0080f020, 0x4070f020, 0x007ff420, 0x104cf440, 0x69086288, 0x4070f020, 0xbc186108, 0x0000f04f, - 0x20004770, 0x48324770, 0x2201f640, 0x49316142, 0x68816081, 0x0f04f011, 0x68c0d1fb, 0xbf184010, - 0x47702001, 0x2201f640, 0x614a4929, 0x482a6008, 0x68886088, 0x0f02f010, 0x68c8d1fb, 0xbf184010, - 0x47702001, 0xf242b430, 0x4b216c01, 0xc014f8c3, 0xbf182900, 0xc084f8df, 0xf020d01e, 0x601c047f, - 0xf000e00b, 0xf105057c, 0xf5054580, 0xf852257d, 0xf8c54b04, 0x1d004100, 0xf0101f09, 0xd1010f7c, - 0xb90c6b1c, 0xd1ec2900, 0xc020f8c3, 0xf0146a1c, 0xd1fb0f01, 0xd1e02900, 0x2000bc30, 0x00004770, - 0x4402f000, 0x4402fc18, 0x4402e000, 0x44025000, 0x4402d000, 0x4402f804, 0x4402dc78, 0x4402fc74, - 0x4402fc20, 0x4402f818, 0x4402dc80, 0x4402f840, 0x400fd000, 0xa4420004, 0xa4420002, 0xa4420001, - 0x00000004, 0x00000008, 0x00000014, 0x00000018, 0x00000024, 0x00000028, 0x00000030, 0x00000034, - 0x00000040, 0x00000044, 0x00000048, 0x0000004c, 0x00000050, 0x00000054, 0x00000058, 0x0000005c, - 0x00000060, 0x00000064, 0x00000068, 0x0000006c, 0x00000070, 0x00000074, 0x00000078, 0x0000007c, - 0x00000080, 0x00000084, 0x00000088, 0x0000008c, 0x00000090, 0x00000094, 0x00000098, 0x0000009c, - 0x000000a0, 0x000000a4, 0x000000a8, 0x000000ac, 0x000000b8, 0x000000bc, 0x000000c8, 0x000000cc, - 0x000000d8, 0x000000dc, 0x00000000 -}; - -// Start address of flash -static const uint32_t flash_start = 0x01000000; -// Size of flash -static const uint32_t flash_size = 0x00100000; - -/** -* List of start and size for each size of flash sector -* The size will apply to all sectors between the listed address and the next address -* in the list. -* The last pair in the list will have sectors starting at that address and ending -* at address start + size. -*/ -static const sector_info_t sectors_info[] = { - {0x01000000, 2048}, -}; - -static const program_target_t flash = { - 0x20000027, // Init - 0x200001e3, // UnInit - 0x200001e7, // EraseChip - 0x20000205, // EraseSector - 0x20000225, // ProgramPage - 0x0, // Verify - - // BKPT : start of blob + 1 - // RSB : blob start + header + rw data offset - // RSP : stack pointer - { - 0x20000001, - 0x20000368, - 0x20000600 - }, - - 0x20000000 + 0x00000A00, // mem buffer location - 0x20000000, // location to write prog_blob in target RAM - sizeof(cc3220sf_flash_prog_blob), // prog_blob size - cc3220sf_flash_prog_blob, // address of prog_blob - 0x00000400 // ram_to_flash_bytes_to_be_written -}; diff --git a/source/family/ti/cc3220sf/target.c b/source/family/ti/cc3220sf/target.c deleted file mode 100644 index aa6d34a66..000000000 --- a/source/family/ti/cc3220sf/target.c +++ /dev/null @@ -1,38 +0,0 @@ -/** - * @file target.c - * @brief Target information for the cc3220sf - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_config.h" - -// The file flash_blob.c must only be included in target.c -#include "flash_blob.c" - -// target information -target_cfg_t target_device = { - .version = kTargetConfigVersion, - .sectors_info = sectors_info, - .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), - .flash_regions[0].start = 0x01000000, - .flash_regions[0].end = 0x01000000 + MB(1), - .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, - .ram_regions[0].start = 0x20000000, - .ram_regions[0].end = 0x20040000, -}; From b86fbca9c187d5a1b1218eece5f9033c56b70b45 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 19 Oct 2021 23:32:12 -0500 Subject: [PATCH 344/617] deprecation: remove g_ti_family reset family --- records/family/all_family.yaml | 1 - records/family/ti_family.yaml | 4 -- source/family/ti/target_reset_ti.c | 62 ------------------------------ source/target/target_family.c | 2 - 4 files changed, 69 deletions(-) delete mode 100644 records/family/ti_family.yaml delete mode 100644 source/family/ti/target_reset_ti.c diff --git a/records/family/all_family.yaml b/records/family/all_family.yaml index 5f175197f..e4527d8ed 100644 --- a/records/family/all_family.yaml +++ b/records/family/all_family.yaml @@ -8,7 +8,6 @@ common: - source/family/nordic/target_reset_nrf51.c - source/family/nordic/target_reset_nrf52.c - source/family/realtek/target_reset_realtek_rtl8195am.c - - source/family/ti/target_reset_ti.c - source/family/toshiba/target_reset_tz.c - source/family/wiznet/target_reset_wiznet.c - source/family/renesas/target_reset_rza.c diff --git a/records/family/ti_family.yaml b/records/family/ti_family.yaml deleted file mode 100644 index 8bcc45d64..000000000 --- a/records/family/ti_family.yaml +++ /dev/null @@ -1,4 +0,0 @@ -common: - sources: - target: - - source/target/ti/target_reset_ti.c diff --git a/source/family/ti/target_reset_ti.c b/source/family/ti/target_reset_ti.c deleted file mode 100644 index e045f2cfd..000000000 --- a/source/family/ti/target_reset_ti.c +++ /dev/null @@ -1,62 +0,0 @@ -/** - * @file target_reset.c - * @brief Target reset for the cc3220sf - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "swd_host.h" -#include "target_family.h" - -#define GPRCM_0_APPS_SOFT_RESET_ADDR 0x4402D000 -#define GPRCM_0_RESET_MCU_VALUE 0x1 -#define GPRCM_0_RESET_MCU_PERIPH_VALUE 0x2 - -static uint8_t target_set_state_ti(target_state_t state) -{ - swd_set_soft_reset(VECTRESET); - if (state == POST_FLASH_RESET) - { - // TI recommends reset via writing to PRCM register instead of AIRCR. - // Reset apps processor and associated peripheral. - uint32_t write_value = GPRCM_0_RESET_MCU_PERIPH_VALUE; - swd_write_memory(GPRCM_0_APPS_SOFT_RESET_ADDR, (uint8_t *)&write_value, sizeof(write_value)); - return 1; - } - return swd_set_target_state_sw(state); -} - -const uint32_t cookieList[]= -{ - 0x5AA5A55A, - 0x000FF800, - 0xEFA3247D -}; - -// Override the weak validate_bin_nvic function. The weak function expects NVIC at the beginning of the flash. -// On CC3220SF, the beginning of the flash is the cookie list, which allows the boot ROM code to jump into onchip flash directly bypassing external flash. -static uint8_t validate_bin_nvic_ti(const uint8_t *buf) -{ - return (memcmp(buf, cookieList, sizeof(cookieList)) == 0); -} - -const target_family_descriptor_t g_ti_family = { - .family_id = kTI_Cc3220sf_FamilyID, - .target_set_state = target_set_state_ti, - .validate_bin_nvic = validate_bin_nvic_ti, -}; - diff --git a/source/target/target_family.c b/source/target/target_family.c index 556696360..6f3b55907 100644 --- a/source/target/target_family.c +++ b/source/target/target_family.c @@ -53,7 +53,6 @@ __WEAK const target_family_descriptor_t g_nxp_lpc55xx_series = {0}; __WEAK const target_family_descriptor_t g_nordic_nrf51 = {0}; __WEAK const target_family_descriptor_t g_nordic_nrf52 = {0}; __WEAK const target_family_descriptor_t g_realtek_rtl8195am = {0}; -__WEAK const target_family_descriptor_t g_ti_family = {0}; __WEAK const target_family_descriptor_t g_wiznet_family = {0}; __WEAK const target_family_descriptor_t g_renesas_family = {0}; __WEAK const target_family_descriptor_t g_toshiba_tz_family = {0}; @@ -87,7 +86,6 @@ const target_family_descriptor_t *g_families[] = { &g_nordic_nrf51, &g_nordic_nrf52, &g_realtek_rtl8195am, - &g_ti_family, &g_wiznet_family, &g_renesas_family, &g_toshiba_tz_family, From b7ff181b79b0a82fecac16624f4dc8a2e6bbac7e Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 19 Oct 2021 23:42:26 -0500 Subject: [PATCH 345/617] deprecation: remove lpc11u35_dipdap_sdt32429b_if project --- projects.yaml | 4 ---- records/board/dipdap_sdt32429b.yaml | 6 ------ source/board/dipdap_sdt32429b.c | 31 ----------------------------- test/info.py | 2 -- 4 files changed, 43 deletions(-) delete mode 100644 records/board/dipdap_sdt32429b.yaml delete mode 100644 source/board/dipdap_sdt32429b.c diff --git a/projects.yaml b/projects.yaml index c7c683f49..f817407d2 100644 --- a/projects.yaml +++ b/projects.yaml @@ -371,10 +371,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/c027.yaml - lpc11u35_dipdap_sdt32429b_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/dipdap_sdt32429b.yaml lpc11u35_dipdap_sdt32439b_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/dipdap_sdt32429b.yaml b/records/board/dipdap_sdt32429b.yaml deleted file mode 100644 index 49d71e3fa..000000000 --- a/records/board/dipdap_sdt32429b.yaml +++ /dev/null @@ -1,6 +0,0 @@ -common: - sources: - board: - - source/board/dipdap_sdt32429b.c - family: - - source/family/st/stm32f429zi/target.c diff --git a/source/board/dipdap_sdt32429b.c b/source/board/dipdap_sdt32429b.c deleted file mode 100644 index 4f8fe7f65..000000000 --- a/source/board/dipdap_sdt32429b.c +++ /dev/null @@ -1,31 +0,0 @@ -/** - * @file dipdap_sdt32429b.c - * @brief board file for DIPDAP targeting STM32F429ZI - * - * DAPLink Interface Firmware - * Copyright (c) 2018, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "3108", - .family_id = kStub_HWReset_FamilyID, - .flags = kEnablePageErase, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index af4d1668a..98587b5f8 100644 --- a/test/info.py +++ b/test/info.py @@ -111,7 +111,6 @@ ('lpc11u35_mtb_laird_bl652_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_usi_wm_bn_bm_22_if', False, 0x0000, "bin" ), ('lpc11u35_dipdap_sdt52832b_if', False, 0x0000, "bin" ), - ('lpc11u35_dipdap_sdt32429b_if', False, 0x0000, "bin" ), ('lpc11u35_dipdap_sdt32439b_if', False, 0x0000, "bin" ), ('lpc11u35_dipdap_sdt64b_if', False, 0x0000, "bin" ), ('lpc11u35_dipdap_sdt51822b_if', False, 0x0000, "bin" ), @@ -262,7 +261,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x2600, VENDOR_TO_FAMILY('Nordic', 2), 'k20dx_ep_agora_if', None, None ), ( 0x2601, VENDOR_TO_FAMILY('NXP', 0), 'k20dx_ep_kairos_if', None, None ), ( 0x3104, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_dipdap_sdt52832b_if', None, None ), - ( 0x3108, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_dipdap_sdt32429b_if', None, None ), ( 0x3105, VENDOR_TO_FAMILY('NXP', 1), 'lpc11u35_dipdap_sdt64b_if', None, None ), ( 0x3103, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_dipdap_sdt51822b_if', None, None ), ( 0x3110, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_dipdap_sdt32439b_if', None, None ), From e1456632cc3e1e6fbc8ff4ae36adeeea77016c84 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 19 Oct 2021 23:43:06 -0500 Subject: [PATCH 346/617] deprecation: remove lpc11u35_dipdap_sdt32439b_if project --- projects.yaml | 4 ---- records/board/dipdap_sdt32439b.yaml | 6 ------ source/board/dipdap_sdt32439b.c | 31 ----------------------------- test/info.py | 2 -- 4 files changed, 43 deletions(-) delete mode 100644 records/board/dipdap_sdt32439b.yaml delete mode 100644 source/board/dipdap_sdt32439b.c diff --git a/projects.yaml b/projects.yaml index f817407d2..c99642648 100644 --- a/projects.yaml +++ b/projects.yaml @@ -371,10 +371,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/c027.yaml - lpc11u35_dipdap_sdt32439b_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/dipdap_sdt32439b.yaml lpc11u35_dipdap_sdt51822b_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/dipdap_sdt32439b.yaml b/records/board/dipdap_sdt32439b.yaml deleted file mode 100644 index 6396c00ac..000000000 --- a/records/board/dipdap_sdt32439b.yaml +++ /dev/null @@ -1,6 +0,0 @@ -common: - sources: - board: - - source/board/dipdap_sdt32439b.c - family: - - source/family/st/stm32f439zi/target.c diff --git a/source/board/dipdap_sdt32439b.c b/source/board/dipdap_sdt32439b.c deleted file mode 100644 index 9eb28ea64..000000000 --- a/source/board/dipdap_sdt32439b.c +++ /dev/null @@ -1,31 +0,0 @@ -/** - * @file dipdap_sdt32439b.c - * @brief board file for DIPDAP targeting STM32F439ZI - * - * DAPLink Interface Firmware - * Copyright (c) 2018, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "3110", - .family_id = kStub_HWReset_FamilyID, - .flags = kEnablePageErase, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index 98587b5f8..209919f27 100644 --- a/test/info.py +++ b/test/info.py @@ -111,7 +111,6 @@ ('lpc11u35_mtb_laird_bl652_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_usi_wm_bn_bm_22_if', False, 0x0000, "bin" ), ('lpc11u35_dipdap_sdt52832b_if', False, 0x0000, "bin" ), - ('lpc11u35_dipdap_sdt32439b_if', False, 0x0000, "bin" ), ('lpc11u35_dipdap_sdt64b_if', False, 0x0000, "bin" ), ('lpc11u35_dipdap_sdt51822b_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_ublox_odin_w2_if', False, 0x0000, "bin" ), @@ -263,7 +262,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x3104, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_dipdap_sdt52832b_if', None, None ), ( 0x3105, VENDOR_TO_FAMILY('NXP', 1), 'lpc11u35_dipdap_sdt64b_if', None, None ), ( 0x3103, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_dipdap_sdt51822b_if', None, None ), - ( 0x3110, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_dipdap_sdt32439b_if', None, None ), ( 0x4600, VENDOR_TO_FAMILY('Realtek', 1), 'lpc11u35_rtl8195am_if', None, 'REALTEK-RTL8195AM' ), ( 0x5006, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_musca_a_if', None, 'ARM_MUSCA_A1' ), ( 0x5007, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_musca_b_if', None, 'ARM_MUSCA_B1' ), From 944a10463aa34c2844df30d3c4b9277c74bf4e63 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 19 Oct 2021 23:43:34 -0500 Subject: [PATCH 347/617] deprecation: remove lpc11u35_dipdap_sdt51822b_if project --- projects.yaml | 4 ---- records/board/dipdap_sdt51822b.yaml | 7 ------ source/board/dipdap_sdt51822b.c | 33 ----------------------------- test/info.py | 2 -- 4 files changed, 46 deletions(-) delete mode 100644 records/board/dipdap_sdt51822b.yaml delete mode 100644 source/board/dipdap_sdt51822b.c diff --git a/projects.yaml b/projects.yaml index c99642648..f08dbb1c1 100644 --- a/projects.yaml +++ b/projects.yaml @@ -371,10 +371,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/c027.yaml - lpc11u35_dipdap_sdt51822b_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/dipdap_sdt51822b.yaml lpc11u35_dipdap_sdt52832b_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/dipdap_sdt51822b.yaml b/records/board/dipdap_sdt51822b.yaml deleted file mode 100644 index b3eaf8884..000000000 --- a/records/board/dipdap_sdt51822b.yaml +++ /dev/null @@ -1,7 +0,0 @@ -common: - sources: - board: - - source/board/dipdap_sdt51822b.c - family: - - source/family/nordic/nrf51822/target_nrf51.c - - source/family/nordic/target_reset_nrf51.c diff --git a/source/board/dipdap_sdt51822b.c b/source/board/dipdap_sdt51822b.c deleted file mode 100644 index 12076e070..000000000 --- a/source/board/dipdap_sdt51822b.c +++ /dev/null @@ -1,33 +0,0 @@ -/** - * @file dipdap_sdt51822b.c - * @brief board ID for the dipdap sdt51822 board - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_board.h" -#include "target_family.h" - -extern target_cfg_t target_device_nrf51822_32; - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "3103", - .family_id = kNordic_Nrf51_FamilyID, - .flags = kEnablePageErase, - .target_cfg = &target_device_nrf51822_32, -}; diff --git a/test/info.py b/test/info.py index 209919f27..dfdd24525 100644 --- a/test/info.py +++ b/test/info.py @@ -112,7 +112,6 @@ ('lpc11u35_mtb_usi_wm_bn_bm_22_if', False, 0x0000, "bin" ), ('lpc11u35_dipdap_sdt52832b_if', False, 0x0000, "bin" ), ('lpc11u35_dipdap_sdt64b_if', False, 0x0000, "bin" ), - ('lpc11u35_dipdap_sdt51822b_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_ublox_odin_w2_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_mts_dragonfly_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_mts_xdot_if', False, 0x0000, "bin" ), @@ -261,7 +260,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x2601, VENDOR_TO_FAMILY('NXP', 0), 'k20dx_ep_kairos_if', None, None ), ( 0x3104, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_dipdap_sdt52832b_if', None, None ), ( 0x3105, VENDOR_TO_FAMILY('NXP', 1), 'lpc11u35_dipdap_sdt64b_if', None, None ), - ( 0x3103, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_dipdap_sdt51822b_if', None, None ), ( 0x4600, VENDOR_TO_FAMILY('Realtek', 1), 'lpc11u35_rtl8195am_if', None, 'REALTEK-RTL8195AM' ), ( 0x5006, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_musca_a_if', None, 'ARM_MUSCA_A1' ), ( 0x5007, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_musca_b_if', None, 'ARM_MUSCA_B1' ), From 4042e8b231321205ae1a75d7a3b5c7e878ab85ef Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 19 Oct 2021 23:44:57 -0500 Subject: [PATCH 348/617] deprecation: remove lpc11u35_dipdap_sdt52832b_if project --- projects.yaml | 4 ---- records/board/dipdap_sdt52832b.yaml | 7 ------ source/board/dipdap_sdt52832b.c | 33 ----------------------------- test/info.py | 2 -- 4 files changed, 46 deletions(-) delete mode 100644 records/board/dipdap_sdt52832b.yaml delete mode 100644 source/board/dipdap_sdt52832b.c diff --git a/projects.yaml b/projects.yaml index f08dbb1c1..e72c00219 100644 --- a/projects.yaml +++ b/projects.yaml @@ -371,10 +371,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/c027.yaml - lpc11u35_dipdap_sdt52832b_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/dipdap_sdt52832b.yaml lpc11u35_dipdap_sdt64b_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/dipdap_sdt52832b.yaml b/records/board/dipdap_sdt52832b.yaml deleted file mode 100644 index 4868bca78..000000000 --- a/records/board/dipdap_sdt52832b.yaml +++ /dev/null @@ -1,7 +0,0 @@ -common: - sources: - board: - - source/board/dipdap_sdt52832b.c - family: - - source/family/nordic/nrf52/target.c - - source/family/nordic/target_reset_nrf52.c diff --git a/source/board/dipdap_sdt52832b.c b/source/board/dipdap_sdt52832b.c deleted file mode 100644 index bfd4ead59..000000000 --- a/source/board/dipdap_sdt52832b.c +++ /dev/null @@ -1,33 +0,0 @@ -/** - * @file dipdap_sdt52832b.c - * @brief board file for DIPDAP targeting nRF52832 - * - * DAPLink Interface Firmware - * Copyright (c) 2018, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_board.h" -#include "target_family.h" - -extern target_cfg_t target_device_nrf52_64; - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "3104", - .family_id = kNordic_Nrf52_FamilyID, - .flags = kEnablePageErase, - .target_cfg = &target_device_nrf52_64, -}; diff --git a/test/info.py b/test/info.py index dfdd24525..65df253ce 100644 --- a/test/info.py +++ b/test/info.py @@ -110,7 +110,6 @@ ('lpc11u35_mtb_wise1570_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_laird_bl652_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_usi_wm_bn_bm_22_if', False, 0x0000, "bin" ), - ('lpc11u35_dipdap_sdt52832b_if', False, 0x0000, "bin" ), ('lpc11u35_dipdap_sdt64b_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_ublox_odin_w2_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_mts_dragonfly_if', False, 0x0000, "bin" ), @@ -258,7 +257,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x2410, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mbed_cloud_connect_if', None, None ), ( 0x2600, VENDOR_TO_FAMILY('Nordic', 2), 'k20dx_ep_agora_if', None, None ), ( 0x2601, VENDOR_TO_FAMILY('NXP', 0), 'k20dx_ep_kairos_if', None, None ), - ( 0x3104, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_dipdap_sdt52832b_if', None, None ), ( 0x3105, VENDOR_TO_FAMILY('NXP', 1), 'lpc11u35_dipdap_sdt64b_if', None, None ), ( 0x4600, VENDOR_TO_FAMILY('Realtek', 1), 'lpc11u35_rtl8195am_if', None, 'REALTEK-RTL8195AM' ), ( 0x5006, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_musca_a_if', None, 'ARM_MUSCA_A1' ), From 46650481dc5f9c6c45930cf11df688854af6b645 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 19 Oct 2021 23:48:02 -0500 Subject: [PATCH 349/617] deprecation: remove lpc11u35_dipdap_sdt64b_if project --- projects.yaml | 4 ---- records/board/dipdap_sdt64b.yaml | 7 ------- source/board/dipdap_sdt64b.c | 31 ------------------------------- test/info.py | 2 -- 4 files changed, 44 deletions(-) delete mode 100644 records/board/dipdap_sdt64b.yaml delete mode 100644 source/board/dipdap_sdt64b.c diff --git a/projects.yaml b/projects.yaml index e72c00219..5c89dfdb1 100644 --- a/projects.yaml +++ b/projects.yaml @@ -371,10 +371,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/c027.yaml - lpc11u35_dipdap_sdt64b_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/dipdap_sdt64b.yaml lpc11u35_ff1705_l151_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/dipdap_sdt64b.yaml b/records/board/dipdap_sdt64b.yaml deleted file mode 100644 index 9526c1c75..000000000 --- a/records/board/dipdap_sdt64b.yaml +++ /dev/null @@ -1,7 +0,0 @@ -common: - sources: - board: - - source/board/dipdap_sdt64b.c - family: - - source/family/freescale/k64f/target.c - - source/family/freescale/target_reset_Kseries.c diff --git a/source/board/dipdap_sdt64b.c b/source/board/dipdap_sdt64b.c deleted file mode 100644 index b11d1b5ac..000000000 --- a/source/board/dipdap_sdt64b.c +++ /dev/null @@ -1,31 +0,0 @@ -/** - * @file dipdap_sdt64b.c - * @brief board ID for the dipdap sdt64b board - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_board.h" -#include "target_family.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "3105", - .family_id = kNXP_KinetisK_FamilyID, - .flags = kEnablePageErase, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index 65df253ce..645885e48 100644 --- a/test/info.py +++ b/test/info.py @@ -110,7 +110,6 @@ ('lpc11u35_mtb_wise1570_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_laird_bl652_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_usi_wm_bn_bm_22_if', False, 0x0000, "bin" ), - ('lpc11u35_dipdap_sdt64b_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_ublox_odin_w2_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_mts_dragonfly_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_mts_xdot_if', False, 0x0000, "bin" ), @@ -257,7 +256,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x2410, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mbed_cloud_connect_if', None, None ), ( 0x2600, VENDOR_TO_FAMILY('Nordic', 2), 'k20dx_ep_agora_if', None, None ), ( 0x2601, VENDOR_TO_FAMILY('NXP', 0), 'k20dx_ep_kairos_if', None, None ), - ( 0x3105, VENDOR_TO_FAMILY('NXP', 1), 'lpc11u35_dipdap_sdt64b_if', None, None ), ( 0x4600, VENDOR_TO_FAMILY('Realtek', 1), 'lpc11u35_rtl8195am_if', None, 'REALTEK-RTL8195AM' ), ( 0x5006, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_musca_a_if', None, 'ARM_MUSCA_A1' ), ( 0x5007, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_musca_b_if', None, 'ARM_MUSCA_B1' ), From 8b9593f4929d955d8f34622ddd2f2841206b5790 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:04:37 -0500 Subject: [PATCH 350/617] deprecation: remove lpc11u35_mbed_cloud_connect_if project --- projects.yaml | 4 ---- records/board/mbed_cloud_connect.yaml | 6 ------ source/board/mbed_cloud_connect.c | 31 --------------------------- test/info.py | 3 --- 4 files changed, 44 deletions(-) delete mode 100644 records/board/mbed_cloud_connect.yaml delete mode 100644 source/board/mbed_cloud_connect.c diff --git a/projects.yaml b/projects.yaml index 5c89dfdb1..2bc1cfdaf 100644 --- a/projects.yaml +++ b/projects.yaml @@ -407,10 +407,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/lpc824xpresso.yaml - lpc11u35_mbed_cloud_connect_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/mbed_cloud_connect.yaml lpc11u35_mini_iot_lpc54018_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/mbed_cloud_connect.yaml b/records/board/mbed_cloud_connect.yaml deleted file mode 100644 index a4eedbbc8..000000000 --- a/records/board/mbed_cloud_connect.yaml +++ /dev/null @@ -1,6 +0,0 @@ -common: - sources: - board: - - source/board/mbed_cloud_connect.c - family: - - source/family/st/stm32f439zi/target.c diff --git a/source/board/mbed_cloud_connect.c b/source/board/mbed_cloud_connect.c deleted file mode 100644 index 9033add79..000000000 --- a/source/board/mbed_cloud_connect.c +++ /dev/null @@ -1,31 +0,0 @@ -/** - * @file mbed_cloud_connect.c - * @brief board ID for the mbed cloud connect board - * - * DAPLink Interface Firmware - * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "2410", - .family_id = kStub_HWReset_FamilyID, - .flags = kEnablePageErase, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index 645885e48..a41f75d7c 100644 --- a/test/info.py +++ b/test/info.py @@ -98,7 +98,6 @@ ("sam3u2c_ublox_evk_nina_b1_if", True, 0x5000, "bin" ), ("lpc11u35_vbluno51_if", False, 0x0000, "bin" ), ('lpc11u35_mtconnect04s_if', False, 0x0000, "bin" ), - ('lpc11u35_mbed_cloud_connect_if', False, 0x0000, "bin" ), ("lpc11u35_rtl8195am_if", False, 0x0000, "bin" ), ("lpc11u35_96b_nitrogen_if", False, 0x0000, "bin" ), ('lpc11u35_mtb_mxchip_emw3166_if', False, 0x0000, "bin" ), @@ -253,7 +252,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x2201, VENDOR_TO_FAMILY('Wiznet', 1), 'lpc11u35_wizwiki_w7500_if', None, 'WIZwiki-W7500' ), ( 0x2202, VENDOR_TO_FAMILY('Wiznet', 1), 'lpc11u35_wizwiki_w7500_eco_if', None, 'WIZwiki-W7500ECO' ), ( 0x2203, VENDOR_TO_FAMILY('Wiznet', 1), 'lpc11u35_wizwiki_w7500p_if', None, 'WIZwiki-W7500P' ), - ( 0x2410, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mbed_cloud_connect_if', None, None ), ( 0x2600, VENDOR_TO_FAMILY('Nordic', 2), 'k20dx_ep_agora_if', None, None ), ( 0x2601, VENDOR_TO_FAMILY('NXP', 0), 'k20dx_ep_kairos_if', None, None ), ( 0x4600, VENDOR_TO_FAMILY('Realtek', 1), 'lpc11u35_rtl8195am_if', None, 'REALTEK-RTL8195AM' ), @@ -366,7 +364,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y 0x1309, # NuMaker-M252KG 0x1310, # NuMaker-IoT-M263A 0x1312, # NuMaker-M2354 - 0x2410, # lpc11u35_mbed_cloud_connect_if 0x3103, # dipdap_sdt51822b 0x3104, # dipdap_sdt52832b 0x3105, # dipdap_sdt64b From 1feb71008d9a25e8f5bebea2f4ea6694ea46114b Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:09:19 -0500 Subject: [PATCH 351/617] deprecation: remove lpc11u35_mtb_aconno_acn52832_if project --- projects.yaml | 4 ---- records/board/mtb_aconno_acn52832.yaml | 11 --------- source/board/mtb_aconno_acn52832.c | 31 -------------------------- test/info.py | 2 -- 4 files changed, 48 deletions(-) delete mode 100644 records/board/mtb_aconno_acn52832.yaml delete mode 100644 source/board/mtb_aconno_acn52832.c diff --git a/projects.yaml b/projects.yaml index 2bc1cfdaf..74d0207f1 100644 --- a/projects.yaml +++ b/projects.yaml @@ -411,10 +411,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/mini_iot_lpc54018.yaml - lpc11u35_mtb_aconno_acn52832_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/mtb_aconno_acn52832.yaml lpc11u35_mtb_laird_bl652_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/mtb_aconno_acn52832.yaml b/records/board/mtb_aconno_acn52832.yaml deleted file mode 100644 index 9e03f9209..000000000 --- a/records/board/mtb_aconno_acn52832.yaml +++ /dev/null @@ -1,11 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_mtb - sources: - board: - - source/board/mtb_aconno_acn52832.c - family: - - source/family/nordic/nrf52/target.c - - source/family/nordic/target_reset_nrf52.c diff --git a/source/board/mtb_aconno_acn52832.c b/source/board/mtb_aconno_acn52832.c deleted file mode 100644 index 733e77618..000000000 --- a/source/board/mtb_aconno_acn52832.c +++ /dev/null @@ -1,31 +0,0 @@ -/** - * @file mtb_aconno_acn52832.c - * @brief board ID for mtb_aconno_acn52832 - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_board.h" -#include "target_family.h" - -extern target_cfg_t target_device_nrf52_64; - -const board_info_t g_board_info = { - .board_id = "0472", - .family_id = kNordic_Nrf52_FamilyID, - .target_cfg = &target_device_nrf52_64, -}; diff --git a/test/info.py b/test/info.py index a41f75d7c..d4a5f4b9c 100644 --- a/test/info.py +++ b/test/info.py @@ -116,7 +116,6 @@ ('lpc11u35_mtb_murata_bl241_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_stm_s2lp_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_stm32l475_if', False, 0x0000, "bin" ), - ('lpc11u35_mtb_aconno_acn52832_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_stm32f439_if', False, 0x0000, "bin" ), ('lpc11u35_musca_a_if', False, 0x0000, "bin" ), ('lpc11u35_musca_b_if', False, 0x0000, "bin" ), @@ -211,7 +210,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0467, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_stm_s2lp_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0468, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_stm32l475_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0469, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_stm32f439_if', None, None ), # TODO - set target when mbed-os supports this - ( 0x0472, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_mtb_aconno_acn52832_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0700, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f103rb_if', 'stm32f103xb_bl', 'ST-Nucleo-F103RB' ), ( 0x0720, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f401re_if', 'stm32f103xb_bl', 'ST-Nucleo-F401RE' ), ( 0x0720, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f072rb_if', 'stm32f103xb_bl', 'ST-Nucleo-F072RB' ), From d7286eb5bd2ee835fe5b6c074399ff85083bfbff Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:10:58 -0500 Subject: [PATCH 352/617] deprecation: remove lpc11u35_mtb_laird_bl652_if project --- projects.yaml | 4 ---- records/board/mtb_laird_bl652.yaml | 11 ---------- source/board/mtb_laird_bl652.c | 32 ------------------------------ test/info.py | 2 -- 4 files changed, 49 deletions(-) delete mode 100644 records/board/mtb_laird_bl652.yaml delete mode 100644 source/board/mtb_laird_bl652.c diff --git a/projects.yaml b/projects.yaml index 74d0207f1..ed58d158a 100644 --- a/projects.yaml +++ b/projects.yaml @@ -411,10 +411,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/mini_iot_lpc54018.yaml - lpc11u35_mtb_laird_bl652_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/mtb_laird_bl652.yaml lpc11u35_mtb_laird_bl654_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/mtb_laird_bl652.yaml b/records/board/mtb_laird_bl652.yaml deleted file mode 100644 index ab2b38429..000000000 --- a/records/board/mtb_laird_bl652.yaml +++ /dev/null @@ -1,11 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_mtb - sources: - board: - - source/board/mtb_laird_bl652.c - family: - - source/family/nordic/nrf52/target.c - - source/family/nordic/target_reset_nrf52.c diff --git a/source/board/mtb_laird_bl652.c b/source/board/mtb_laird_bl652.c deleted file mode 100644 index d03b59a36..000000000 --- a/source/board/mtb_laird_bl652.c +++ /dev/null @@ -1,32 +0,0 @@ -/** - * @file mtb_laird_bl652.c - * @brief board ID for the Laird BL652 - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_board.h" -#include "target_family.h" - -extern target_cfg_t target_device_nrf52_64; - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "0461", - .family_id = kNordic_Nrf52_FamilyID, - .target_cfg = &target_device_nrf52_64, -}; diff --git a/test/info.py b/test/info.py index d4a5f4b9c..1d97abd24 100644 --- a/test/info.py +++ b/test/info.py @@ -107,7 +107,6 @@ ('lpc11u35_mtb_wise1510_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_wise1530_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_wise1570_if', False, 0x0000, "bin" ), - ('lpc11u35_mtb_laird_bl652_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_usi_wm_bn_bm_22_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_ublox_odin_w2_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_mts_dragonfly_if', False, 0x0000, "bin" ), @@ -203,7 +202,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0458, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1510_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0459, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1530_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0460, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1570_if', None, None ), # TODO - set target when mbed-os supports this - ( 0x0461, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_mtb_laird_bl652_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0462, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_usi_wm_bn_bm_22_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0465, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_mtb_laird_bl654_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0466, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_mtb_murata_bl241_if', None, None ), # TODO - set target when mbed-os supports this From 2c46de49859ae72f513707d4568e580d3f3fd066 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:12:22 -0500 Subject: [PATCH 353/617] deprecation: remove lpc11u35_mtb_laird_bl654_if project --- projects.yaml | 4 ---- records/board/mtb_laird_bl654.yaml | 11 ---------- source/board/mtb_laird_bl654.c | 33 ------------------------------ test/info.py | 2 -- 4 files changed, 50 deletions(-) delete mode 100644 records/board/mtb_laird_bl654.yaml delete mode 100644 source/board/mtb_laird_bl654.c diff --git a/projects.yaml b/projects.yaml index ed58d158a..d2af62706 100644 --- a/projects.yaml +++ b/projects.yaml @@ -411,10 +411,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/mini_iot_lpc54018.yaml - lpc11u35_mtb_laird_bl654_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/mtb_laird_bl654.yaml lpc11u35_mtb_mts_dragonfly_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/mtb_laird_bl654.yaml b/records/board/mtb_laird_bl654.yaml deleted file mode 100644 index d3b38a7dd..000000000 --- a/records/board/mtb_laird_bl654.yaml +++ /dev/null @@ -1,11 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_mtb - sources: - board: - - source/board/mtb_laird_bl654.c - family: - - source/family/nordic/nrf52/target.c - - source/family/nordic/target_reset_nrf52.c diff --git a/source/board/mtb_laird_bl654.c b/source/board/mtb_laird_bl654.c deleted file mode 100644 index 3aed7322c..000000000 --- a/source/board/mtb_laird_bl654.c +++ /dev/null @@ -1,33 +0,0 @@ -/** - * @file mtb_laird_bl654.c - * @brief board ID for the Laird BL654 - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_board.h" -#include "target_family.h" - -extern target_cfg_t target_device_nrf52840; - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "0465", - .family_id = kNordic_Nrf52_FamilyID, - .target_cfg = &target_device_nrf52840, -}; - diff --git a/test/info.py b/test/info.py index 1d97abd24..a622f507c 100644 --- a/test/info.py +++ b/test/info.py @@ -111,7 +111,6 @@ ('lpc11u35_mtb_ublox_odin_w2_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_mts_dragonfly_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_mts_xdot_if', False, 0x0000, "bin" ), - ('lpc11u35_mtb_laird_bl654_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_murata_bl241_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_stm_s2lp_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_stm32l475_if', False, 0x0000, "bin" ), @@ -203,7 +202,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0459, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1530_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0460, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1570_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0462, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_usi_wm_bn_bm_22_if', None, None ), # TODO - set target when mbed-os supports this - ( 0x0465, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_mtb_laird_bl654_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0466, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_mtb_murata_bl241_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0467, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_stm_s2lp_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0468, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_stm32l475_if', None, None ), # TODO - set target when mbed-os supports this From 334fc57c974ca24037f81df86ff6a67786b8e9f3 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:14:11 -0500 Subject: [PATCH 354/617] deprecation: remove lpc11u35_mtb_mts_dragonfly_if project --- projects.yaml | 4 ---- records/board/mtb_mts_dragonfly.yaml | 10 ---------- source/board/mtb_mts_dragonfly.c | 30 ---------------------------- test/info.py | 2 -- 4 files changed, 46 deletions(-) delete mode 100644 records/board/mtb_mts_dragonfly.yaml delete mode 100644 source/board/mtb_mts_dragonfly.c diff --git a/projects.yaml b/projects.yaml index d2af62706..1a268cc9c 100644 --- a/projects.yaml +++ b/projects.yaml @@ -411,10 +411,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/mini_iot_lpc54018.yaml - lpc11u35_mtb_mts_dragonfly_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/mtb_mts_dragonfly.yaml lpc11u35_mtb_mts_xdot_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/mtb_mts_dragonfly.yaml b/records/board/mtb_mts_dragonfly.yaml deleted file mode 100644 index 2c0155267..000000000 --- a/records/board/mtb_mts_dragonfly.yaml +++ /dev/null @@ -1,10 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_mtb - sources: - board: - - source/board/mtb_mts_dragonfly.c - family: - - source/family/st/stm32f411/target.c diff --git a/source/board/mtb_mts_dragonfly.c b/source/board/mtb_mts_dragonfly.c deleted file mode 100644 index d0713b98b..000000000 --- a/source/board/mtb_mts_dragonfly.c +++ /dev/null @@ -1,30 +0,0 @@ -/** - * @file mtb_mts_dragonfly.c - * @brief board ID for the MTB Dragonfly - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "0454", - .family_id = kStub_HWReset_FamilyID, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index a622f507c..a04c2031b 100644 --- a/test/info.py +++ b/test/info.py @@ -109,7 +109,6 @@ ('lpc11u35_mtb_wise1570_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_usi_wm_bn_bm_22_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_ublox_odin_w2_if', False, 0x0000, "bin" ), - ('lpc11u35_mtb_mts_dragonfly_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_mts_xdot_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_murata_bl241_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_stm_s2lp_if', False, 0x0000, "bin" ), @@ -194,7 +193,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0450, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_ublox_odin_w2_if', None, None ), ( 0x0451, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_mxchip_emw3166_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0453, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_mts_xdot_if', None, None ), - ( 0x0454, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_mts_dragonfly_if', None, None ), ( 0x0455, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_mtb_nina_b112_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0456, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_murata_abz_078_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0457, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_rak811_if', None, None ), # TODO - set target when mbed-os supports this From fa53f0c2bbe03a2f4c531f6f1f12ce588514bbb5 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:15:57 -0500 Subject: [PATCH 355/617] deprecation: remove lpc11u35_mtb_mts_xdot_if project --- projects.yaml | 4 ---- records/board/mtb_mts_xdot.yaml | 10 ---------- source/board/mtb_mts_xdot.c | 30 ------------------------------ test/info.py | 2 -- 4 files changed, 46 deletions(-) delete mode 100644 records/board/mtb_mts_xdot.yaml delete mode 100644 source/board/mtb_mts_xdot.c diff --git a/projects.yaml b/projects.yaml index 1a268cc9c..546c61dc2 100644 --- a/projects.yaml +++ b/projects.yaml @@ -411,10 +411,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/mini_iot_lpc54018.yaml - lpc11u35_mtb_mts_xdot_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/mtb_mts_xdot.yaml lpc11u35_mtb_murata_abz_078_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/mtb_mts_xdot.yaml b/records/board/mtb_mts_xdot.yaml deleted file mode 100644 index da5453e6f..000000000 --- a/records/board/mtb_mts_xdot.yaml +++ /dev/null @@ -1,10 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_mtb - sources: - board: - - source/board/mtb_mts_xdot.c - family: - - source/family/st/xDot-L151/target.c diff --git a/source/board/mtb_mts_xdot.c b/source/board/mtb_mts_xdot.c deleted file mode 100644 index 647b4371c..000000000 --- a/source/board/mtb_mts_xdot.c +++ /dev/null @@ -1,30 +0,0 @@ -/** - * @file mtb_mts_xdot.c - * @brief board ID for the MultiTech xDot - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "0453", - .family_id = kStub_HWReset_FamilyID, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index a04c2031b..4c0428c70 100644 --- a/test/info.py +++ b/test/info.py @@ -109,7 +109,6 @@ ('lpc11u35_mtb_wise1570_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_usi_wm_bn_bm_22_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_ublox_odin_w2_if', False, 0x0000, "bin" ), - ('lpc11u35_mtb_mts_xdot_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_murata_bl241_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_stm_s2lp_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_stm32l475_if', False, 0x0000, "bin" ), @@ -192,7 +191,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0423, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max78000fthr_if', 'max32625_bl', 'MAX78000' ), ( 0x0450, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_ublox_odin_w2_if', None, None ), ( 0x0451, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_mxchip_emw3166_if', None, None ), # TODO - set target when mbed-os supports this - ( 0x0453, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_mts_xdot_if', None, None ), ( 0x0455, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_mtb_nina_b112_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0456, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_murata_abz_078_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0457, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_rak811_if', None, None ), # TODO - set target when mbed-os supports this From 59c224d31da5595fa4e51e9ace1ad26ed03440c5 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:18:16 -0500 Subject: [PATCH 356/617] deprecation: remove lpc11u35_mtb_murata_abz_078_if project --- projects.yaml | 4 ---- records/board/mtb_murata_abz_078.yaml | 10 --------- source/board/mtb_murata_abz_078.c | 31 --------------------------- test/info.py | 3 --- 4 files changed, 48 deletions(-) delete mode 100644 records/board/mtb_murata_abz_078.yaml delete mode 100644 source/board/mtb_murata_abz_078.c diff --git a/projects.yaml b/projects.yaml index 546c61dc2..cc40c244f 100644 --- a/projects.yaml +++ b/projects.yaml @@ -411,10 +411,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/mini_iot_lpc54018.yaml - lpc11u35_mtb_murata_abz_078_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/mtb_murata_abz_078.yaml lpc11u35_mtb_murata_bl241_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/mtb_murata_abz_078.yaml b/records/board/mtb_murata_abz_078.yaml deleted file mode 100644 index 62f77ab49..000000000 --- a/records/board/mtb_murata_abz_078.yaml +++ /dev/null @@ -1,10 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_mtb - sources: - board: - - source/board/mtb_murata_abz_078.c - family: - - source/family/st/stm32l082cz/target.c diff --git a/source/board/mtb_murata_abz_078.c b/source/board/mtb_murata_abz_078.c deleted file mode 100644 index 840899447..000000000 --- a/source/board/mtb_murata_abz_078.c +++ /dev/null @@ -1,31 +0,0 @@ -/** - * @file mtb_murata_abz_078.c - * @brief board ID for the Murata abz - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "0456", - .family_id = kStub_HWReset_FamilyID, - .flags = kEnablePageErase, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index 4c0428c70..180faff7d 100644 --- a/test/info.py +++ b/test/info.py @@ -102,7 +102,6 @@ ("lpc11u35_96b_nitrogen_if", False, 0x0000, "bin" ), ('lpc11u35_mtb_mxchip_emw3166_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_nina_b112_if', False, 0x0000, "bin" ), - ('lpc11u35_mtb_murata_abz_078_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_rak811_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_wise1510_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_wise1530_if', False, 0x0000, "bin" ), @@ -192,7 +191,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0450, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_ublox_odin_w2_if', None, None ), ( 0x0451, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_mxchip_emw3166_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0455, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_mtb_nina_b112_if', None, None ), # TODO - set target when mbed-os supports this - ( 0x0456, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_murata_abz_078_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0457, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_rak811_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0458, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1510_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0459, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1530_if', None, None ), # TODO - set target when mbed-os supports this @@ -343,7 +341,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y 0x0422, # MAX32666FTHR 0x0423, # MAX78000FTHR 0x0450, # mtb_ublox_odin_w2 - 0x0456, # lpc11u35_mtb_murata_abz_078_if 0x0457, # lpc11u35_mtb_rak811_if 0x0460, # WISE-1570 0x0468, # lpc11u35_mtb_stm32l475_if From 82eac479eb5a9ac7ba53fbde54bad07a134f3818 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:19:22 -0500 Subject: [PATCH 357/617] deprecation: remove lpc11u35_mtb_murata_bl241_if project --- projects.yaml | 4 ---- records/board/mtb_murata_bl241.yaml | 11 ---------- source/board/mtb_murata_bl241.c | 32 ----------------------------- test/info.py | 2 -- 4 files changed, 49 deletions(-) delete mode 100644 records/board/mtb_murata_bl241.yaml delete mode 100644 source/board/mtb_murata_bl241.c diff --git a/projects.yaml b/projects.yaml index cc40c244f..75aa1744f 100644 --- a/projects.yaml +++ b/projects.yaml @@ -411,10 +411,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/mini_iot_lpc54018.yaml - lpc11u35_mtb_murata_bl241_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/mtb_murata_bl241.yaml lpc11u35_mtb_mxchip_emw3166_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/mtb_murata_bl241.yaml b/records/board/mtb_murata_bl241.yaml deleted file mode 100644 index a04d2d0d9..000000000 --- a/records/board/mtb_murata_bl241.yaml +++ /dev/null @@ -1,11 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_mtb - sources: - board: - - source/board/mtb_murata_bl241.c - family: - - source/family/nordic/nrf52/target.c - - source/family/nordic/target_reset_nrf52.c diff --git a/source/board/mtb_murata_bl241.c b/source/board/mtb_murata_bl241.c deleted file mode 100644 index 4756f0c62..000000000 --- a/source/board/mtb_murata_bl241.c +++ /dev/null @@ -1,32 +0,0 @@ -/** - * @file mtb_murata_bl241.c - * @brief board ID for the Murata bl241 - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_board.h" -#include "target_family.h" - -extern target_cfg_t target_device_nrf52_64; - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "0466", - .family_id = kNordic_Nrf52_FamilyID, - .target_cfg = &target_device_nrf52_64, -}; diff --git a/test/info.py b/test/info.py index 180faff7d..cf0a9626b 100644 --- a/test/info.py +++ b/test/info.py @@ -108,7 +108,6 @@ ('lpc11u35_mtb_wise1570_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_usi_wm_bn_bm_22_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_ublox_odin_w2_if', False, 0x0000, "bin" ), - ('lpc11u35_mtb_murata_bl241_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_stm_s2lp_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_stm32l475_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_stm32f439_if', False, 0x0000, "bin" ), @@ -196,7 +195,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0459, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1530_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0460, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1570_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0462, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_usi_wm_bn_bm_22_if', None, None ), # TODO - set target when mbed-os supports this - ( 0x0466, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_mtb_murata_bl241_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0467, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_stm_s2lp_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0468, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_stm32l475_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0469, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_stm32f439_if', None, None ), # TODO - set target when mbed-os supports this From a45960d8fe9bbd3b6949a17885e812c226266401 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:21:01 -0500 Subject: [PATCH 358/617] deprecation: remove lpc11u35_mtb_mxchip_emw3166_if project --- projects.yaml | 4 ---- records/board/mtb_mxchip_emw3166.yaml | 10 --------- source/board/mtb_mxchip_emw3166.c | 30 --------------------------- test/info.py | 2 -- 4 files changed, 46 deletions(-) delete mode 100644 records/board/mtb_mxchip_emw3166.yaml delete mode 100644 source/board/mtb_mxchip_emw3166.c diff --git a/projects.yaml b/projects.yaml index 75aa1744f..143956ca0 100644 --- a/projects.yaml +++ b/projects.yaml @@ -411,10 +411,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/mini_iot_lpc54018.yaml - lpc11u35_mtb_mxchip_emw3166_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/mtb_mxchip_emw3166.yaml lpc11u35_mtb_nina_b112_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/mtb_mxchip_emw3166.yaml b/records/board/mtb_mxchip_emw3166.yaml deleted file mode 100644 index f24678cd6..000000000 --- a/records/board/mtb_mxchip_emw3166.yaml +++ /dev/null @@ -1,10 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_mtb - sources: - board: - - source/board/mtb_mxchip_emw3166.c - family: - - source/family/st/stm32f412rg/target.c diff --git a/source/board/mtb_mxchip_emw3166.c b/source/board/mtb_mxchip_emw3166.c deleted file mode 100644 index abf40768f..000000000 --- a/source/board/mtb_mxchip_emw3166.c +++ /dev/null @@ -1,30 +0,0 @@ -/** - * @file mtb_mxchip_emw3166.c - * @brief board ID for MXCHIP EMW3166 - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "0451", - .family_id = kStub_HWReset_FamilyID, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index cf0a9626b..9bd762bb6 100644 --- a/test/info.py +++ b/test/info.py @@ -100,7 +100,6 @@ ('lpc11u35_mtconnect04s_if', False, 0x0000, "bin" ), ("lpc11u35_rtl8195am_if", False, 0x0000, "bin" ), ("lpc11u35_96b_nitrogen_if", False, 0x0000, "bin" ), - ('lpc11u35_mtb_mxchip_emw3166_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_nina_b112_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_rak811_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_wise1510_if', False, 0x0000, "bin" ), @@ -188,7 +187,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0422, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32666fthr_if', 'max32625_bl', 'MAX32666' ), ( 0x0423, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max78000fthr_if', 'max32625_bl', 'MAX78000' ), ( 0x0450, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_ublox_odin_w2_if', None, None ), - ( 0x0451, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_mxchip_emw3166_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0455, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_mtb_nina_b112_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0457, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_rak811_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0458, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1510_if', None, None ), # TODO - set target when mbed-os supports this From 3671b187e1c0aebc4c929f2b7c197d8ddbba7f0f Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:23:45 -0500 Subject: [PATCH 359/617] deprecation: remove lpc11u35_mtb_nina_b112_if project --- projects.yaml | 4 ---- records/board/mtb_nina_b112.yaml | 11 ----------- source/board/mtb_nina_b112.c | 32 -------------------------------- test/info.py | 2 -- 4 files changed, 49 deletions(-) delete mode 100644 records/board/mtb_nina_b112.yaml delete mode 100644 source/board/mtb_nina_b112.c diff --git a/projects.yaml b/projects.yaml index 143956ca0..adf7a0f9d 100644 --- a/projects.yaml +++ b/projects.yaml @@ -411,10 +411,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/mini_iot_lpc54018.yaml - lpc11u35_mtb_nina_b112_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/mtb_nina_b112.yaml lpc11u35_mtb_rak811_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/mtb_nina_b112.yaml b/records/board/mtb_nina_b112.yaml deleted file mode 100644 index 074bbe8a8..000000000 --- a/records/board/mtb_nina_b112.yaml +++ /dev/null @@ -1,11 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_mtb - sources: - board: - - source/board/mtb_nina_b112.c - family: - - source/family/nordic/nrf52/target.c - - source/family/nordic/target_reset_nrf52.c diff --git a/source/board/mtb_nina_b112.c b/source/board/mtb_nina_b112.c deleted file mode 100644 index 8fab63945..000000000 --- a/source/board/mtb_nina_b112.c +++ /dev/null @@ -1,32 +0,0 @@ -/** - * @file mtb_ninab112.c - * @brief board ID for MTB nina - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_board.h" -#include "target_family.h" - -extern target_cfg_t target_device_nrf52_64; - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "0455", - .family_id = kNordic_Nrf52_FamilyID, - .target_cfg = &target_device_nrf52_64, -}; diff --git a/test/info.py b/test/info.py index 9bd762bb6..5d2b4d8b1 100644 --- a/test/info.py +++ b/test/info.py @@ -100,7 +100,6 @@ ('lpc11u35_mtconnect04s_if', False, 0x0000, "bin" ), ("lpc11u35_rtl8195am_if", False, 0x0000, "bin" ), ("lpc11u35_96b_nitrogen_if", False, 0x0000, "bin" ), - ('lpc11u35_mtb_nina_b112_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_rak811_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_wise1510_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_wise1530_if', False, 0x0000, "bin" ), @@ -187,7 +186,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0422, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32666fthr_if', 'max32625_bl', 'MAX32666' ), ( 0x0423, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max78000fthr_if', 'max32625_bl', 'MAX78000' ), ( 0x0450, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_ublox_odin_w2_if', None, None ), - ( 0x0455, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_mtb_nina_b112_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0457, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_rak811_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0458, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1510_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0459, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1530_if', None, None ), # TODO - set target when mbed-os supports this From 3c4e1ce5364c176f998f7599812bbc9abca8994a Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:26:30 -0500 Subject: [PATCH 360/617] deprecation: remove lpc11u35_mtb_rak811_if project --- projects.yaml | 4 ---- records/board/mtb_rak811.yaml | 11 ----------- source/board/mtb_rak811.c | 31 ------------------------------- test/info.py | 3 --- 4 files changed, 49 deletions(-) delete mode 100644 records/board/mtb_rak811.yaml delete mode 100644 source/board/mtb_rak811.c diff --git a/projects.yaml b/projects.yaml index adf7a0f9d..258ce45f2 100644 --- a/projects.yaml +++ b/projects.yaml @@ -411,10 +411,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/mini_iot_lpc54018.yaml - lpc11u35_mtb_rak811_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/mtb_rak811.yaml lpc11u35_mtb_stm32f439_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/mtb_rak811.yaml b/records/board/mtb_rak811.yaml deleted file mode 100644 index e4c25ba5e..000000000 --- a/records/board/mtb_rak811.yaml +++ /dev/null @@ -1,11 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_mtb - sources: - board: - - source/board/mtb_rak811.c - family: - - source/family/st/stm32l151cbxxa/target.c - diff --git a/source/board/mtb_rak811.c b/source/board/mtb_rak811.c deleted file mode 100644 index fd23bdf2e..000000000 --- a/source/board/mtb_rak811.c +++ /dev/null @@ -1,31 +0,0 @@ -/** - * @file mtb_rak811.c - * @brief board ID for the RAK811 - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "0457", - .family_id = kStub_HWReset_FamilyID, - .flags = kEnablePageErase, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index 5d2b4d8b1..e19c531f6 100644 --- a/test/info.py +++ b/test/info.py @@ -100,7 +100,6 @@ ('lpc11u35_mtconnect04s_if', False, 0x0000, "bin" ), ("lpc11u35_rtl8195am_if", False, 0x0000, "bin" ), ("lpc11u35_96b_nitrogen_if", False, 0x0000, "bin" ), - ('lpc11u35_mtb_rak811_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_wise1510_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_wise1530_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_wise1570_if', False, 0x0000, "bin" ), @@ -186,7 +185,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0422, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32666fthr_if', 'max32625_bl', 'MAX32666' ), ( 0x0423, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max78000fthr_if', 'max32625_bl', 'MAX78000' ), ( 0x0450, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_ublox_odin_w2_if', None, None ), - ( 0x0457, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_rak811_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0458, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1510_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0459, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1530_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0460, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1570_if', None, None ), # TODO - set target when mbed-os supports this @@ -335,7 +333,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y 0x0422, # MAX32666FTHR 0x0423, # MAX78000FTHR 0x0450, # mtb_ublox_odin_w2 - 0x0457, # lpc11u35_mtb_rak811_if 0x0460, # WISE-1570 0x0468, # lpc11u35_mtb_stm32l475_if 0x0469, # lpc11u35_mtb_stm32f439_if From d13257fb7ca174596f6f4c28d413f567adb251b2 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:27:26 -0500 Subject: [PATCH 361/617] deprecation: remove unused stm32l151cbxxa target --- source/family/st/stm32l151cbxxa/flash_blob.c | 75 -------------------- source/family/st/stm32l151cbxxa/target.c | 38 ---------- 2 files changed, 113 deletions(-) delete mode 100644 source/family/st/stm32l151cbxxa/flash_blob.c delete mode 100644 source/family/st/stm32l151cbxxa/target.c diff --git a/source/family/st/stm32l151cbxxa/flash_blob.c b/source/family/st/stm32l151cbxxa/flash_blob.c deleted file mode 100644 index 719b592b5..000000000 --- a/source/family/st/stm32l151cbxxa/flash_blob.c +++ /dev/null @@ -1,75 +0,0 @@ -/* Flash OS Routines (Automagically Generated) - * Copyright (c) 2009-2019 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -static const uint32_t stm32l1xx_128_flash_prog_blob[] = { - 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, - 0x4603b510, 0x6980486e, 0x0224240f, 0x4c6c4320, 0x486c61a0, 0x486c60e0, 0x486c60e0, 0x486c6120, - 0x46206120, 0x240169c0, 0x40200524, 0xd1062800, 0x4c694868, 0x20066020, 0x48686060, 0x200060a0, - 0x4601bd10, 0x6840485e, 0x43102202, 0x60504a5c, 0x68404610, 0x43102201, 0x60504a59, 0x47702000, - 0x48574601, 0x22016840, 0x43100252, 0x60504a54, 0x68404610, 0x43102208, 0x60504a51, 0x60082000, - 0x4857e002, 0x60104a54, 0x6980484d, 0x0fc007c0, 0xd1f62800, 0x6840484a, 0x02522201, 0x4a484390, - 0x46106050, 0x22086840, 0x4a454390, 0x20006050, 0x46034770, 0x47702001, 0x4603b530, 0x1dc82480, - 0x0a0130f8, 0x483e0209, 0x00e56840, 0x4d3c4328, 0x46286068, 0x25086840, 0x4d394328, 0xbf006068, - 0x6810e005, 0x1d1b6018, 0x1f091d12, 0x29001f24, 0x2c00d001, 0xe002d1f5, 0x4d374839, 0x48306028, - 0x07c06980, 0x28000fc0, 0x482dd1f6, 0x250f6980, 0x4028022d, 0xd0062800, 0x69804829, 0x4d284328, - 0x200161a8, 0x4826bd30, 0x25016840, 0x43a802ad, 0x60684d23, 0x68404628, 0x43a82508, 0x60684d20, - 0x68404628, 0x4328152d, 0x60684d1d, 0x68404628, 0x43282508, 0x60684d1a, 0xe0052480, 0x60186810, - 0x1d121d1b, 0x1f241f09, 0xd0012900, 0xd1f52c00, 0x481be002, 0x60284d18, 0x69804811, 0x0fc007c0, - 0xd1f62800, 0x6980480e, 0x022d250f, 0x28004028, 0x480bd006, 0x43286980, 0x61a84d09, 0xe7c12001, - 0x68404807, 0x02ad2501, 0x4d0543a8, 0x46286068, 0x25086840, 0x4d0243a8, 0x20006068, 0x0000e7b2, - 0x40023c00, 0x89abcdef, 0x02030405, 0x8c9daebf, 0x13141516, 0x00005555, 0x40003000, 0x00000fff, - 0x0000aaaa, 0x00000000 -}; - -// Start address of flash -static const uint32_t flash_start = 0x08000000; -// Size of flash -static const uint32_t flash_size = 0x00020000; - -/** -* List of start and size for each size of flash sector -* The size will apply to all sectors between the listed address and the next address -* in the list. -* The last pair in the list will have sectors starting at that address and ending -* at address start + size. -*/ -static const sector_info_t sectors_info[] = { - {0x08000000, 0x00000100}, -}; - -static const program_target_t flash = { - 0x20000021, // Init - 0x20000063, // UnInit - 0xffffffff, // EraseChip - NOT SUPPORTED - 0x20000081, // EraseSector - 0x200000d9, // ProgramPage - 0x0, // Verify - - // BKPT : start of blob + 1 - // RSB : blob start + header + rw data offset - // RSP : stack pointer - { - 0x20000001, - 0x20000204, - 0x20000800 - }, - - 0x20000000 + 0x00000A00, // mem buffer location - 0x20000000, // location to write prog_blob in target RAM - sizeof(stm32l1xx_128_flash_prog_blob), // prog_blob size - stm32l1xx_128_flash_prog_blob, // address of prog_blob - 0x00000100 // ram_to_flash_bytes_to_be_written -}; diff --git a/source/family/st/stm32l151cbxxa/target.c b/source/family/st/stm32l151cbxxa/target.c deleted file mode 100644 index 656cfcef9..000000000 --- a/source/family/st/stm32l151cbxxa/target.c +++ /dev/null @@ -1,38 +0,0 @@ -/** - * @file target.c - * @brief Target information for the stm32l151cbxxa - * - * DAPLink Interface Firmware - * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_config.h" - -// The file flash_blob.c must only be included in target.c -#include "flash_blob.c" - -// target information -target_cfg_t target_device = { - .version = kTargetConfigVersion, - .sectors_info = sectors_info, - .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), - .flash_regions[0].start = 0x08000000, - .flash_regions[0].end = 0x08000000 + KB(128), - .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, - .ram_regions[0].start = 0x20000000, - .ram_regions[0].end = 0x20000000 + KB(32), -}; From ac16055f6e185f37bd11dab23fbd22387b696c3d Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:29:03 -0500 Subject: [PATCH 362/617] deprecation: remove lpc11u35_mtb_stm32f439_if project --- projects.yaml | 4 ---- records/board/mtb_stm32f439.yaml | 10 ---------- source/board/mtb_stm32f439.c | 30 ------------------------------ test/info.py | 3 --- 4 files changed, 47 deletions(-) delete mode 100644 records/board/mtb_stm32f439.yaml delete mode 100644 source/board/mtb_stm32f439.c diff --git a/projects.yaml b/projects.yaml index 258ce45f2..7dc3fefd6 100644 --- a/projects.yaml +++ b/projects.yaml @@ -411,10 +411,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/mini_iot_lpc54018.yaml - lpc11u35_mtb_stm32f439_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/mtb_stm32f439.yaml lpc11u35_mtb_stm32l475_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/mtb_stm32f439.yaml b/records/board/mtb_stm32f439.yaml deleted file mode 100644 index 57d7e6649..000000000 --- a/records/board/mtb_stm32f439.yaml +++ /dev/null @@ -1,10 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_mtb - sources: - board: - - source/board/mtb_stm32f439.c - family: - - source/family/st/stm32f439zi/target.c diff --git a/source/board/mtb_stm32f439.c b/source/board/mtb_stm32f439.c deleted file mode 100644 index 969e69d0e..000000000 --- a/source/board/mtb_stm32f439.c +++ /dev/null @@ -1,30 +0,0 @@ -/** - * @file mtb_stm32f439.c - * @brief board file for stm32f439 - * - * DAPLink Interface Firmware - * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -const board_info_t g_board_info = { - .board_id = "0469", - .family_id = kStub_HWReset_FamilyID, - .flags = kEnablePageErase|kEnableUnderResetConnect, - .target_cfg = &target_device, -}; \ No newline at end of file diff --git a/test/info.py b/test/info.py index e19c531f6..e433603ed 100644 --- a/test/info.py +++ b/test/info.py @@ -107,7 +107,6 @@ ('lpc11u35_mtb_ublox_odin_w2_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_stm_s2lp_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_stm32l475_if', False, 0x0000, "bin" ), - ('lpc11u35_mtb_stm32f439_if', False, 0x0000, "bin" ), ('lpc11u35_musca_a_if', False, 0x0000, "bin" ), ('lpc11u35_musca_b_if', False, 0x0000, "bin" ), ('lpc11u35_musca_b_eflash_if', False, 0x0000, "bin" ), @@ -191,7 +190,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0462, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_usi_wm_bn_bm_22_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0467, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_stm_s2lp_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0468, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_stm32l475_if', None, None ), # TODO - set target when mbed-os supports this - ( 0x0469, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_stm32f439_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0700, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f103rb_if', 'stm32f103xb_bl', 'ST-Nucleo-F103RB' ), ( 0x0720, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f401re_if', 'stm32f103xb_bl', 'ST-Nucleo-F401RE' ), ( 0x0720, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f072rb_if', 'stm32f103xb_bl', 'ST-Nucleo-F072RB' ), @@ -335,7 +333,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y 0x0450, # mtb_ublox_odin_w2 0x0460, # WISE-1570 0x0468, # lpc11u35_mtb_stm32l475_if - 0x0469, # lpc11u35_mtb_stm32f439_if 0x1101, # Nordic-nRF52-DK 0x1102, # Nordic-nRF52840-DK 0x1304, # NuMaker-PFM-M487KM From bc7eaca420f346042fd677cee4cd5e0b0e070c80 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:48:22 -0500 Subject: [PATCH 363/617] deprecation: remove lpc11u35_mtb_stm32l475_if project --- projects.yaml | 4 ---- records/board/mtb_stm32l475.yaml | 10 ---------- source/board/mtb_stm32l475.c | 32 -------------------------------- test/info.py | 3 --- 4 files changed, 49 deletions(-) delete mode 100644 records/board/mtb_stm32l475.yaml delete mode 100644 source/board/mtb_stm32l475.c diff --git a/projects.yaml b/projects.yaml index 7dc3fefd6..b7ecbfe10 100644 --- a/projects.yaml +++ b/projects.yaml @@ -411,10 +411,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/mini_iot_lpc54018.yaml - lpc11u35_mtb_stm32l475_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/mtb_stm32l475.yaml lpc11u35_mtb_stm_s2lp_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/mtb_stm32l475.yaml b/records/board/mtb_stm32l475.yaml deleted file mode 100644 index 65be37fc2..000000000 --- a/records/board/mtb_stm32l475.yaml +++ /dev/null @@ -1,10 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_mtb - sources: - board: - - source/board/mtb_stm32l475.c - family: - - source/family/st/stm32l4xx_1024/target.c diff --git a/source/board/mtb_stm32l475.c b/source/board/mtb_stm32l475.c deleted file mode 100644 index 8a4fb6c67..000000000 --- a/source/board/mtb_stm32l475.c +++ /dev/null @@ -1,32 +0,0 @@ -/** - * @file mtb_stm32l475.c - * @brief board ID for the mtb_stm32l475 - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -extern target_cfg_t target_device_stm32l475; - -const board_info_t g_board_info = { - .board_id = "0468", - .family_id = kStub_HWReset_FamilyID, - .flags = kEnablePageErase|kEnableUnderResetConnect, - .target_cfg = &target_device_stm32l475, -}; \ No newline at end of file diff --git a/test/info.py b/test/info.py index e433603ed..4514f9d5e 100644 --- a/test/info.py +++ b/test/info.py @@ -106,7 +106,6 @@ ('lpc11u35_mtb_usi_wm_bn_bm_22_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_ublox_odin_w2_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_stm_s2lp_if', False, 0x0000, "bin" ), - ('lpc11u35_mtb_stm32l475_if', False, 0x0000, "bin" ), ('lpc11u35_musca_a_if', False, 0x0000, "bin" ), ('lpc11u35_musca_b_if', False, 0x0000, "bin" ), ('lpc11u35_musca_b_eflash_if', False, 0x0000, "bin" ), @@ -189,7 +188,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0460, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1570_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0462, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_usi_wm_bn_bm_22_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0467, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_stm_s2lp_if', None, None ), # TODO - set target when mbed-os supports this - ( 0x0468, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_stm32l475_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0700, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f103rb_if', 'stm32f103xb_bl', 'ST-Nucleo-F103RB' ), ( 0x0720, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f401re_if', 'stm32f103xb_bl', 'ST-Nucleo-F401RE' ), ( 0x0720, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f072rb_if', 'stm32f103xb_bl', 'ST-Nucleo-F072RB' ), @@ -332,7 +330,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y 0x0423, # MAX78000FTHR 0x0450, # mtb_ublox_odin_w2 0x0460, # WISE-1570 - 0x0468, # lpc11u35_mtb_stm32l475_if 0x1101, # Nordic-nRF52-DK 0x1102, # Nordic-nRF52840-DK 0x1304, # NuMaker-PFM-M487KM From ea56d6d2ecd419b42884225899670c519c1a9157 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:50:09 -0500 Subject: [PATCH 364/617] deprecation: remove lpc11u35_mtb_stm_s2lp_if project --- projects.yaml | 4 ---- records/board/mtb_stm_s2lp.yaml | 10 ---------- source/board/mtb_stm_s2lp.c | 30 ------------------------------ test/info.py | 2 -- 4 files changed, 46 deletions(-) delete mode 100644 records/board/mtb_stm_s2lp.yaml delete mode 100644 source/board/mtb_stm_s2lp.c diff --git a/projects.yaml b/projects.yaml index b7ecbfe10..2d2d0ab21 100644 --- a/projects.yaml +++ b/projects.yaml @@ -411,10 +411,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/mini_iot_lpc54018.yaml - lpc11u35_mtb_stm_s2lp_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/mtb_stm_s2lp.yaml lpc11u35_mtb_ublox_odin_w2_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/mtb_stm_s2lp.yaml b/records/board/mtb_stm_s2lp.yaml deleted file mode 100644 index 1f46931a4..000000000 --- a/records/board/mtb_stm_s2lp.yaml +++ /dev/null @@ -1,10 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_mtb - sources: - board: - - source/board/mtb_stm_s2lp.c - family: - - source/family/st/stm32f429zi/target.c diff --git a/source/board/mtb_stm_s2lp.c b/source/board/mtb_stm_s2lp.c deleted file mode 100644 index d9ec43d63..000000000 --- a/source/board/mtb_stm_s2lp.c +++ /dev/null @@ -1,30 +0,0 @@ -/** - * @file mtb_stm_s2lp.c - * @brief board ID for the STM S2 LP - * - * DAPLink Interface Firmware - * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "0467", - .family_id = kStub_HWReset_FamilyID, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index 4514f9d5e..83ea7a478 100644 --- a/test/info.py +++ b/test/info.py @@ -105,7 +105,6 @@ ('lpc11u35_mtb_wise1570_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_usi_wm_bn_bm_22_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_ublox_odin_w2_if', False, 0x0000, "bin" ), - ('lpc11u35_mtb_stm_s2lp_if', False, 0x0000, "bin" ), ('lpc11u35_musca_a_if', False, 0x0000, "bin" ), ('lpc11u35_musca_b_if', False, 0x0000, "bin" ), ('lpc11u35_musca_b_eflash_if', False, 0x0000, "bin" ), @@ -187,7 +186,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0459, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1530_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0460, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1570_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0462, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_usi_wm_bn_bm_22_if', None, None ), # TODO - set target when mbed-os supports this - ( 0x0467, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_stm_s2lp_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0700, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f103rb_if', 'stm32f103xb_bl', 'ST-Nucleo-F103RB' ), ( 0x0720, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f401re_if', 'stm32f103xb_bl', 'ST-Nucleo-F401RE' ), ( 0x0720, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f072rb_if', 'stm32f103xb_bl', 'ST-Nucleo-F072RB' ), From 1cda47b51dbf97358fc0ee3c3e510b95330a9bdf Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:51:25 -0500 Subject: [PATCH 365/617] deprecation: remove lpc11u35_mtb_ublox_odin_w2_if project --- projects.yaml | 4 ---- records/board/mtb_ublox_odin_w2.yaml | 10 --------- source/board/mtb_ublox_odin_w2.c | 31 ---------------------------- test/info.py | 3 --- 4 files changed, 48 deletions(-) delete mode 100644 records/board/mtb_ublox_odin_w2.yaml delete mode 100644 source/board/mtb_ublox_odin_w2.c diff --git a/projects.yaml b/projects.yaml index 2d2d0ab21..6782c7d20 100644 --- a/projects.yaml +++ b/projects.yaml @@ -411,10 +411,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/mini_iot_lpc54018.yaml - lpc11u35_mtb_ublox_odin_w2_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/mtb_ublox_odin_w2.yaml lpc11u35_mtb_usi_wm_bn_bm_22_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/mtb_ublox_odin_w2.yaml b/records/board/mtb_ublox_odin_w2.yaml deleted file mode 100644 index fe067d674..000000000 --- a/records/board/mtb_ublox_odin_w2.yaml +++ /dev/null @@ -1,10 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_mtb - sources: - board: - - source/board/mtb_ublox_odin_w2.c - family: - - source/family/st/stm32f439zi/target.c diff --git a/source/board/mtb_ublox_odin_w2.c b/source/board/mtb_ublox_odin_w2.c deleted file mode 100644 index 057b55b69..000000000 --- a/source/board/mtb_ublox_odin_w2.c +++ /dev/null @@ -1,31 +0,0 @@ -/** - * @file mtb_ublox_odin_w2.c - * @brief board file for UBLOX ODIN W2 - * - * DAPLink Interface Firmware - * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "0450", - .family_id = kStub_HWReset_FamilyID, - .flags = kEnablePageErase|kEnableUnderResetConnect, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index 83ea7a478..6fc40012b 100644 --- a/test/info.py +++ b/test/info.py @@ -104,7 +104,6 @@ ('lpc11u35_mtb_wise1530_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_wise1570_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_usi_wm_bn_bm_22_if', False, 0x0000, "bin" ), - ('lpc11u35_mtb_ublox_odin_w2_if', False, 0x0000, "bin" ), ('lpc11u35_musca_a_if', False, 0x0000, "bin" ), ('lpc11u35_musca_b_if', False, 0x0000, "bin" ), ('lpc11u35_musca_b_eflash_if', False, 0x0000, "bin" ), @@ -181,7 +180,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0421, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32660evsys_if', 'max32625_bl', 'MAX32660' ), ( 0x0422, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32666fthr_if', 'max32625_bl', 'MAX32666' ), ( 0x0423, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max78000fthr_if', 'max32625_bl', 'MAX78000' ), - ( 0x0450, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_ublox_odin_w2_if', None, None ), ( 0x0458, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1510_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0459, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1530_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0460, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1570_if', None, None ), # TODO - set target when mbed-os supports this @@ -326,7 +324,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y 0x0421, # MAX32660EVSYS 0x0422, # MAX32666FTHR 0x0423, # MAX78000FTHR - 0x0450, # mtb_ublox_odin_w2 0x0460, # WISE-1570 0x1101, # Nordic-nRF52-DK 0x1102, # Nordic-nRF52840-DK From d2e53b03ee15df424f9e78a2c76aa35cab9616fc Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:52:46 -0500 Subject: [PATCH 366/617] deprecation: remove lpc11u35_mtb_usi_wm_bn_bm_22_if project --- projects.yaml | 4 ---- records/board/mtb_usi_wm_bn_bm_22.yaml | 10 -------- source/board/mtb_usi_wm_bn_bm_22.c | 32 -------------------------- test/info.py | 2 -- 4 files changed, 48 deletions(-) delete mode 100644 records/board/mtb_usi_wm_bn_bm_22.yaml delete mode 100644 source/board/mtb_usi_wm_bn_bm_22.c diff --git a/projects.yaml b/projects.yaml index 6782c7d20..0c30b6d26 100644 --- a/projects.yaml +++ b/projects.yaml @@ -411,10 +411,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/mini_iot_lpc54018.yaml - lpc11u35_mtb_usi_wm_bn_bm_22_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/mtb_usi_wm_bn_bm_22.yaml lpc11u35_mtb_wise1510_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/mtb_usi_wm_bn_bm_22.yaml b/records/board/mtb_usi_wm_bn_bm_22.yaml deleted file mode 100644 index 911a93f81..000000000 --- a/records/board/mtb_usi_wm_bn_bm_22.yaml +++ /dev/null @@ -1,10 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_mtb - sources: - board: - - source/board/mtb_usi_wm_bn_bm_22.c - family: - - source/family/st/stm32f412rg/target.c diff --git a/source/board/mtb_usi_wm_bn_bm_22.c b/source/board/mtb_usi_wm_bn_bm_22.c deleted file mode 100644 index 67636b8c2..000000000 --- a/source/board/mtb_usi_wm_bn_bm_22.c +++ /dev/null @@ -1,32 +0,0 @@ -/** - * @file mtb_usi_wm_bn_bm_22.c - * @brief board ID for the mtb usi - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -extern target_cfg_t target_device; - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "0462", - .family_id = kStub_HWReset_FamilyID, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index 6fc40012b..da491a5e8 100644 --- a/test/info.py +++ b/test/info.py @@ -103,7 +103,6 @@ ('lpc11u35_mtb_wise1510_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_wise1530_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_wise1570_if', False, 0x0000, "bin" ), - ('lpc11u35_mtb_usi_wm_bn_bm_22_if', False, 0x0000, "bin" ), ('lpc11u35_musca_a_if', False, 0x0000, "bin" ), ('lpc11u35_musca_b_if', False, 0x0000, "bin" ), ('lpc11u35_musca_b_eflash_if', False, 0x0000, "bin" ), @@ -183,7 +182,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0458, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1510_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0459, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1530_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0460, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1570_if', None, None ), # TODO - set target when mbed-os supports this - ( 0x0462, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_usi_wm_bn_bm_22_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0700, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f103rb_if', 'stm32f103xb_bl', 'ST-Nucleo-F103RB' ), ( 0x0720, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f401re_if', 'stm32f103xb_bl', 'ST-Nucleo-F401RE' ), ( 0x0720, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f072rb_if', 'stm32f103xb_bl', 'ST-Nucleo-F072RB' ), From 64562ed8520ce760222233a7406c370a1687257c Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:54:49 -0500 Subject: [PATCH 367/617] deprecation: remove lpc11u35_mtb_wise1510_if project --- projects.yaml | 4 ---- records/board/mtb_wise1510.yaml | 10 ---------- source/board/mtb_wise1510.c | 30 ------------------------------ test/info.py | 3 --- 4 files changed, 47 deletions(-) delete mode 100644 records/board/mtb_wise1510.yaml delete mode 100644 source/board/mtb_wise1510.c diff --git a/projects.yaml b/projects.yaml index 0c30b6d26..919b80088 100644 --- a/projects.yaml +++ b/projects.yaml @@ -411,10 +411,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/mini_iot_lpc54018.yaml - lpc11u35_mtb_wise1510_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/mtb_wise1510.yaml lpc11u35_mtb_wise1530_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/mtb_wise1510.yaml b/records/board/mtb_wise1510.yaml deleted file mode 100644 index a88bb9529..000000000 --- a/records/board/mtb_wise1510.yaml +++ /dev/null @@ -1,10 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_mtb - sources: - board: - - source/board/mtb_wise1510.c - family: - - source/family/st/stm32l443rc/target.c diff --git a/source/board/mtb_wise1510.c b/source/board/mtb_wise1510.c deleted file mode 100644 index fe20901b5..000000000 --- a/source/board/mtb_wise1510.c +++ /dev/null @@ -1,30 +0,0 @@ -/** - * @file mtb_wise1510.c - * @brief board ID for the MTB Wise 1510 - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "0458", - .family_id = kStub_HWReset_FamilyID, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index da491a5e8..297aed951 100644 --- a/test/info.py +++ b/test/info.py @@ -100,7 +100,6 @@ ('lpc11u35_mtconnect04s_if', False, 0x0000, "bin" ), ("lpc11u35_rtl8195am_if", False, 0x0000, "bin" ), ("lpc11u35_96b_nitrogen_if", False, 0x0000, "bin" ), - ('lpc11u35_mtb_wise1510_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_wise1530_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_wise1570_if', False, 0x0000, "bin" ), ('lpc11u35_musca_a_if', False, 0x0000, "bin" ), @@ -178,8 +177,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0418, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32620fthr_if', 'max32625_bl', 'MAX32620' ), ( 0x0421, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32660evsys_if', 'max32625_bl', 'MAX32660' ), ( 0x0422, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32666fthr_if', 'max32625_bl', 'MAX32666' ), - ( 0x0423, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max78000fthr_if', 'max32625_bl', 'MAX78000' ), - ( 0x0458, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1510_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0459, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1530_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0460, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1570_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0700, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f103rb_if', 'stm32f103xb_bl', 'ST-Nucleo-F103RB' ), From 448e53f37483d782ce230bf31b5af570ffae047f Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:55:30 -0500 Subject: [PATCH 368/617] deprecation: remove unused stm32l443rc target --- source/family/st/stm32l443rc/flash_blob.c | 73 ----------------------- source/family/st/stm32l443rc/target.c | 38 ------------ 2 files changed, 111 deletions(-) delete mode 100644 source/family/st/stm32l443rc/flash_blob.c delete mode 100644 source/family/st/stm32l443rc/target.c diff --git a/source/family/st/stm32l443rc/flash_blob.c b/source/family/st/stm32l443rc/flash_blob.c deleted file mode 100644 index 896501394..000000000 --- a/source/family/st/stm32l443rc/flash_blob.c +++ /dev/null @@ -1,73 +0,0 @@ -/* Flash OS Routines (Automagically Generated) - * Copyright (c) 2009-2019 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - #include "flash_blob.h" - -static const uint32_t _flash_prog_blob[] = { - 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, - 0x8f4ff3bf, 0x48584770, 0x49586800, 0x0d000500, 0xd0001840, 0x47702001, 0x6a004855, 0x0fc00280, - 0xb5004770, 0xf7ff4602, 0x2801ffee, 0xf7ffd108, 0x2801fff3, 0x484fd104, 0xd3014282, 0xbd002001, - 0xbd002000, 0x4602b500, 0xffddf7ff, 0xd0022801, 0x0d8002d0, 0x4948bd00, 0x40080ad0, 0xd5f90391, - 0x300130ff, 0x4842bd00, 0x60814944, 0x60814944, 0x60012100, 0x61014943, 0x03c06a00, 0x4843d406, - 0x60014941, 0x60412106, 0x60814941, 0x47702000, 0x49372001, 0x614807c0, 0x47702000, 0x47702001, - 0x49384833, 0x13c16101, 0x69416141, 0x04122201, 0x61414311, 0x4a354937, 0x6011e000, 0x03db6903, - 0x2100d4fb, 0x46086141, 0xb5104770, 0xf7ff4604, 0x4603ffa8, 0xf7ff4620, 0x4925ffb5, 0x610c4c29, - 0x02d800c2, 0x43021c92, 0x6948614a, 0x04122201, 0x61484310, 0x8f4ff3bf, 0x4a244826, 0x6010e000, - 0x03db690b, 0x2000d4fb, 0x69086148, 0xd0014020, 0x2001610c, 0xb5f0bd10, 0x4d151dc9, 0x4f1908c9, - 0x612f00c9, 0x616b2300, 0xe0184c1a, 0x616b2301, 0x60036813, 0x60436853, 0x8f4ff3bf, 0xe0004b13, - 0x692e601c, 0xd4fb03f6, 0x616b2300, 0x423b692b, 0x612fd002, 0xbdf02001, 0x39083008, 0x29003208, - 0x2000d1e4, 0x0000bdf0, 0xe0042000, 0xfffffbcb, 0x40022000, 0x08020000, 0x000003bf, 0x45670123, - 0xcdef89ab, 0x0000c3fa, 0x00005555, 0x40003000, 0x00000fff, 0x0000aaaa, 0x00000000 -}; - -// Start address of flash -static const uint32_t flash_start = 0x08000000; -// Size of flash -static const uint32_t flash_size = 0x00040000; - -/** -* List of start and size for each size of flash sector -* The size will apply to all sectors between the listed address and the next address -* in the list. -* The last pair in the list will have sectors starting at that address and ending -* at address start + size. -*/ -static const sector_info_t sectors_info[] = { - {0x08000000, 0x00000800}, -}; - -static const program_target_t flash = { - 0x20000087, // Init - 0x200000b1, // UnInit - 0x200000c1, // EraseChip - 0x200000eb, // EraseSector - 0x20000137, // ProgramPage - 0x0, // Verify - - // BKPT : start of blob + 1 - // RSB : blob start + header + rw data offset - // RSP : stack pointer - { - 0x20000001, - 0x200001b8, - 0x20000800 - }, - - 0x20000000 + 0x00000A00, // mem buffer location - 0x20000000, // location to write prog_blob in target RAM - sizeof(_flash_prog_blob), // prog_blob size - _flash_prog_blob, // address of prog_blob - 0x00000400 // ram_to_flash_bytes_to_be_written -}; diff --git a/source/family/st/stm32l443rc/target.c b/source/family/st/stm32l443rc/target.c deleted file mode 100644 index 190ae8d6d..000000000 --- a/source/family/st/stm32l443rc/target.c +++ /dev/null @@ -1,38 +0,0 @@ -/** - * @file target.c - * @brief Target information for the stm32l443rc - * - * DAPLink Interface Firmware - * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_config.h" - -// The file flash_blob.c must only be included in target.c -#include "flash_blob.c" - -// target information -target_cfg_t target_device = { - .version = kTargetConfigVersion, - .sectors_info = sectors_info, - .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), - .flash_regions[0].start = 0x08000000, - .flash_regions[0].end = 0x08040000, - .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, - .ram_regions[0].start = 0x20000000, - .ram_regions[0].end = 0x2000c000, -}; From 79682971bd03510ae6e81c6d57011cdbd45ebcae Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:56:57 -0500 Subject: [PATCH 369/617] deprecation: remove lpc11u35_mtb_wise1530_if project --- projects.yaml | 4 ---- records/board/mtb_wise1530.yaml | 10 ---------- source/board/mtb_wise1530.c | 30 ------------------------------ test/info.py | 2 -- 4 files changed, 46 deletions(-) delete mode 100644 records/board/mtb_wise1530.yaml delete mode 100644 source/board/mtb_wise1530.c diff --git a/projects.yaml b/projects.yaml index 919b80088..f65612a14 100644 --- a/projects.yaml +++ b/projects.yaml @@ -411,10 +411,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/mini_iot_lpc54018.yaml - lpc11u35_mtb_wise1530_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/mtb_wise1530.yaml lpc11u35_mtb_wise1570_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/mtb_wise1530.yaml b/records/board/mtb_wise1530.yaml deleted file mode 100644 index b2cd6ce75..000000000 --- a/records/board/mtb_wise1530.yaml +++ /dev/null @@ -1,10 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_mtb - sources: - board: - - source/board/mtb_wise1530.c - family: - - source/family/st/stm32f412rg/target.c diff --git a/source/board/mtb_wise1530.c b/source/board/mtb_wise1530.c deleted file mode 100644 index c5b59d277..000000000 --- a/source/board/mtb_wise1530.c +++ /dev/null @@ -1,30 +0,0 @@ -/** - * @file mtb_wise1530.c - * @brief board ID for the MTB Wise 1530 - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "0459", - .family_id = kStub_HWReset_FamilyID, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index 297aed951..a9611dd0a 100644 --- a/test/info.py +++ b/test/info.py @@ -100,7 +100,6 @@ ('lpc11u35_mtconnect04s_if', False, 0x0000, "bin" ), ("lpc11u35_rtl8195am_if", False, 0x0000, "bin" ), ("lpc11u35_96b_nitrogen_if", False, 0x0000, "bin" ), - ('lpc11u35_mtb_wise1530_if', False, 0x0000, "bin" ), ('lpc11u35_mtb_wise1570_if', False, 0x0000, "bin" ), ('lpc11u35_musca_a_if', False, 0x0000, "bin" ), ('lpc11u35_musca_b_if', False, 0x0000, "bin" ), @@ -177,7 +176,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0418, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32620fthr_if', 'max32625_bl', 'MAX32620' ), ( 0x0421, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32660evsys_if', 'max32625_bl', 'MAX32660' ), ( 0x0422, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32666fthr_if', 'max32625_bl', 'MAX32666' ), - ( 0x0459, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1530_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0460, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1570_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0700, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f103rb_if', 'stm32f103xb_bl', 'ST-Nucleo-F103RB' ), ( 0x0720, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f401re_if', 'stm32f103xb_bl', 'ST-Nucleo-F401RE' ), From 6544c81507ab5fc5d791a9bfe8b5a2ade9b489f9 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:58:24 -0500 Subject: [PATCH 370/617] deprecation: remove lpc11u35_mtb_wise1570_if project --- projects.yaml | 4 ---- records/board/mtb_wise1570.yaml | 10 ---------- source/board/mtb_wise1570.c | 31 ------------------------------- test/info.py | 2 -- 4 files changed, 47 deletions(-) delete mode 100644 records/board/mtb_wise1570.yaml delete mode 100644 source/board/mtb_wise1570.c diff --git a/projects.yaml b/projects.yaml index f65612a14..dee4c0e84 100644 --- a/projects.yaml +++ b/projects.yaml @@ -411,10 +411,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/mini_iot_lpc54018.yaml - lpc11u35_mtb_wise1570_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/mtb_wise1570.yaml lpc11u35_mtconnect04s_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/mtb_wise1570.yaml b/records/board/mtb_wise1570.yaml deleted file mode 100644 index 53853e489..000000000 --- a/records/board/mtb_wise1570.yaml +++ /dev/null @@ -1,10 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_mtb - sources: - board: - - source/board/mtb_wise1570.c - family: - - source/family/st/stm32l486jg/target.c diff --git a/source/board/mtb_wise1570.c b/source/board/mtb_wise1570.c deleted file mode 100644 index 671a49ba1..000000000 --- a/source/board/mtb_wise1570.c +++ /dev/null @@ -1,31 +0,0 @@ -/** - * @file mtb_wise1570.c - * @brief board ID for the MTB Wise 1570 - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "0460", - .family_id = kStub_HWReset_FamilyID, - .flags = kEnablePageErase|kEnableUnderResetConnect, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index a9611dd0a..c83fbf43e 100644 --- a/test/info.py +++ b/test/info.py @@ -100,7 +100,6 @@ ('lpc11u35_mtconnect04s_if', False, 0x0000, "bin" ), ("lpc11u35_rtl8195am_if", False, 0x0000, "bin" ), ("lpc11u35_96b_nitrogen_if", False, 0x0000, "bin" ), - ('lpc11u35_mtb_wise1570_if', False, 0x0000, "bin" ), ('lpc11u35_musca_a_if', False, 0x0000, "bin" ), ('lpc11u35_musca_b_if', False, 0x0000, "bin" ), ('lpc11u35_musca_b_eflash_if', False, 0x0000, "bin" ), @@ -176,7 +175,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0418, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32620fthr_if', 'max32625_bl', 'MAX32620' ), ( 0x0421, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32660evsys_if', 'max32625_bl', 'MAX32660' ), ( 0x0422, VENDOR_TO_FAMILY('Stub', 1), 'max32625_max32666fthr_if', 'max32625_bl', 'MAX32666' ), - ( 0x0460, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_mtb_wise1570_if', None, None ), # TODO - set target when mbed-os supports this ( 0x0700, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f103rb_if', 'stm32f103xb_bl', 'ST-Nucleo-F103RB' ), ( 0x0720, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f401re_if', 'stm32f103xb_bl', 'ST-Nucleo-F401RE' ), ( 0x0720, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_stm32f072rb_if', 'stm32f103xb_bl', 'ST-Nucleo-F072RB' ), From a29190c6c313fa52caa40b9dba3fcd84043382cd Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 00:59:13 -0500 Subject: [PATCH 371/617] deprecation: remove unused stm32l486jg target --- source/family/st/stm32l486jg/flash_blob.c | 73 ----------------------- source/family/st/stm32l486jg/target.c | 38 ------------ 2 files changed, 111 deletions(-) delete mode 100644 source/family/st/stm32l486jg/flash_blob.c delete mode 100644 source/family/st/stm32l486jg/target.c diff --git a/source/family/st/stm32l486jg/flash_blob.c b/source/family/st/stm32l486jg/flash_blob.c deleted file mode 100644 index 646072f3f..000000000 --- a/source/family/st/stm32l486jg/flash_blob.c +++ /dev/null @@ -1,73 +0,0 @@ -/* Flash OS Routines (Automagically Generated) - * Copyright (c) 2009-2019 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - #include "flash_blob.h" - -static const uint32_t _flash_prog_blob[] = { - 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, - 0x8f4ff3bf, 0x48584770, 0x49586800, 0x0d000500, 0xd0001840, 0x47702001, 0x6a004855, 0x0fc00280, - 0xb5004770, 0xf7ff4602, 0x2801ffee, 0xf7ffd108, 0x2801fff3, 0x484fd104, 0xd3014282, 0xbd002001, - 0xbd002000, 0x4602b500, 0xffddf7ff, 0xd0022801, 0x0d8002d0, 0x4948bd00, 0x40080ad0, 0xd5f90311, - 0x300130ff, 0x4842bd00, 0x60814944, 0x60814944, 0x60012100, 0x61014943, 0x03c06a00, 0x4843d406, - 0x60014941, 0x60412106, 0x60814941, 0x47702000, 0x49372001, 0x614807c0, 0x47702000, 0x47702001, - 0x49384833, 0x13c16101, 0x69416141, 0x04122201, 0x61414311, 0x4a354937, 0x6011e000, 0x03db6903, - 0x2100d4fb, 0x46086141, 0xb5104770, 0xf7ff4604, 0x4603ffa8, 0xf7ff4620, 0x4925ffb5, 0x610c4c29, - 0x02d800c2, 0x43021c92, 0x6948614a, 0x04122201, 0x61484310, 0x8f4ff3bf, 0x4a244826, 0x6010e000, - 0x03db690b, 0x2000d4fb, 0x69086148, 0xd0014020, 0x2001610c, 0xb5f0bd10, 0x4d151dc9, 0x4f1908c9, - 0x612f00c9, 0x616b2300, 0xe0184c1a, 0x616b2301, 0x60036813, 0x60436853, 0x8f4ff3bf, 0xe0004b13, - 0x692e601c, 0xd4fb03f6, 0x616b2300, 0x423b692b, 0x612fd002, 0xbdf02001, 0x39083008, 0x29003208, - 0x2000d1e4, 0x0000bdf0, 0xe0042000, 0xfffffbcb, 0x40022000, 0x08080000, 0x000002ff, 0x45670123, - 0xcdef89ab, 0x0000c3fa, 0x00005555, 0x40003000, 0x00000fff, 0x0000aaaa, 0x00000000 -}; - -// Start address of flash -static const uint32_t flash_start = 0x08000000; -// Size of flash -static const uint32_t flash_size = 0x00100000; - -/** -* List of start and size for each size of flash sector -* The size will apply to all sectors between the listed address and the next address -* in the list. -* The last pair in the list will have sectors starting at that address and ending -* at address start + size. -*/ -static const sector_info_t sectors_info[] = { - {0x08000000, 0x00000800}, -}; - -static const program_target_t flash = { - 0x20000087, // Init - 0x200000b1, // UnInit - 0x200000c1, // EraseChip - 0x200000eb, // EraseSector - 0x20000137, // ProgramPage - 0x0, // Verify - - // BKPT : start of blob + 1 - // RSB : blob start + header + rw data offset - // RSP : stack pointer - { - 0x20000001, - 0x200001b8, - 0x20000800 - }, - - 0x20000000 + 0x00000A00, // mem buffer location - 0x20000000, // location to write prog_blob in target RAM - sizeof(_flash_prog_blob), // prog_blob size - _flash_prog_blob, // address of prog_blob - 0x00000400 // ram_to_flash_bytes_to_be_written -}; diff --git a/source/family/st/stm32l486jg/target.c b/source/family/st/stm32l486jg/target.c deleted file mode 100644 index 928f5691f..000000000 --- a/source/family/st/stm32l486jg/target.c +++ /dev/null @@ -1,38 +0,0 @@ -/** - * @file target.c - * @brief Target information for the stm32l486jg - * - * DAPLink Interface Firmware - * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_config.h" - -// The file flash_blob.c must only be included in target.c -#include "flash_blob.c" - -// target information -target_cfg_t target_device = { - .version = kTargetConfigVersion, - .sectors_info = sectors_info, - .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), - .flash_regions[0].start = 0x08000000, - .flash_regions[0].end = 0x08100000, - .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, - .ram_regions[0].start = 0x20000000, - .ram_regions[0].end = 0x20018000, -}; From eab03006969a47faa39a461ee391682f7da4b9d8 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 01:00:01 -0500 Subject: [PATCH 372/617] deprecation: remove lpc11u35_mtconnect04s_if project --- projects.yaml | 4 ---- records/board/mtconnect04s.yaml | 7 ------- source/board/mtconnect04s.c | 35 --------------------------------- test/info.py | 2 -- 4 files changed, 48 deletions(-) delete mode 100644 records/board/mtconnect04s.yaml delete mode 100644 source/board/mtconnect04s.c diff --git a/projects.yaml b/projects.yaml index dee4c0e84..f33b88100 100644 --- a/projects.yaml +++ b/projects.yaml @@ -411,10 +411,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/mini_iot_lpc54018.yaml - lpc11u35_mtconnect04s_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/mtconnect04s.yaml lpc11u35_musca_a_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/mtconnect04s.yaml b/records/board/mtconnect04s.yaml deleted file mode 100644 index 26f7b328b..000000000 --- a/records/board/mtconnect04s.yaml +++ /dev/null @@ -1,7 +0,0 @@ -common: - sources: - board: - - source/board/mtconnect04s.c - family: - - source/family/nordic/nrf51822/target_nrf51.c - - source/family/nordic/target_reset_nrf51.c diff --git a/source/board/mtconnect04s.c b/source/board/mtconnect04s.c deleted file mode 100644 index 1ee34c95a..000000000 --- a/source/board/mtconnect04s.c +++ /dev/null @@ -1,35 +0,0 @@ -/** - * @file mtconnect04s.c - * @brief board ID for the MtM MtConnect04S developments board - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_board.h" -#include "target_family.h" - -extern target_cfg_t target_device_nrf51822_32; - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "C005", - .family_id = kNordic_Nrf51_FamilyID, - .daplink_url_name = "HELP HTM", - .daplink_drive_name = "MTCONNEC04S", - .daplink_target_url = "https://blog.mtmtech.com.tw/mtconnect04s/", - .target_cfg = &target_device_nrf51822_32, -}; diff --git a/test/info.py b/test/info.py index c83fbf43e..e18caf7c9 100644 --- a/test/info.py +++ b/test/info.py @@ -97,7 +97,6 @@ ('lpc11u35_wizwiki_w7500p_if', False, 0x0000, "bin" ), ("sam3u2c_ublox_evk_nina_b1_if", True, 0x5000, "bin" ), ("lpc11u35_vbluno51_if", False, 0x0000, "bin" ), - ('lpc11u35_mtconnect04s_if', False, 0x0000, "bin" ), ("lpc11u35_rtl8195am_if", False, 0x0000, "bin" ), ("lpc11u35_96b_nitrogen_if", False, 0x0000, "bin" ), ('lpc11u35_musca_a_if', False, 0x0000, "bin" ), @@ -245,7 +244,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x9904, VENDOR_TO_FAMILY('Nordic', 2), 'kl27z_microbit_if', 'kl27z_bl', 'Microbitv2' ), ( 0xA127, VENDOR_TO_FAMILY('Ambiq', 1), 'kl26z_artemis_dk_if', 'kl26z_bl', 'ARTMBED' ), ( 0xC006, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_vbluno51_if', None, 'VBLUNO51' ), - ( 0xC005, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_mtconnect04s_if', None, 'MtConnect04S' ), ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'kl26z_if', None, None ), ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'k20dx_if', None, None ), ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'k26f_if', None, None ), From 638f5e278f9c996adfd4f30817e4ac8e0aca73cb Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 01:01:17 -0500 Subject: [PATCH 373/617] deprecation: remove IO override header used for mtb boards --- .../board/override_mtb/IO_Config_Override.h | 108 ------------------ 1 file changed, 108 deletions(-) delete mode 100644 source/board/override_mtb/IO_Config_Override.h diff --git a/source/board/override_mtb/IO_Config_Override.h b/source/board/override_mtb/IO_Config_Override.h deleted file mode 100644 index 620de1a18..000000000 --- a/source/board/override_mtb/IO_Config_Override.h +++ /dev/null @@ -1,108 +0,0 @@ -/** - * @file IO_Config_Override.c - * @brief Alternative IO for LPC11U35 based Hardware Interface Circuit for all 6LoWPAN_BorderRouter, Moved SWCLK - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __IO_CONFIG_H__ -#define __IO_CONFIG_H__ - -#include "LPC11Uxx.h" -#include "daplink.h" - -// This GPIO configuration is only valid for the LPC11U35 HIC -COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35); - -// Peripheral register bit masks (used for pin inits) -#define FUNC_0 0 -#define FUNC_1 1 -#define PULL_DOWN_ENABLED (1 << 3) -#define PULL_UP_ENABLED (2 << 3) -#define OPENDRAIN (1 << 10) - -// DAP LED PIO0_21 -#define PIN_DAP_LED_PORT 0 -#define PIN_DAP_LED_BIT 21 -#define PIN_DAP_LED (1 << PIN_DAP_LED_BIT) -#define PIN_DAP_LED_IOCON LPC_IOCON->PIO0_21 -#define PIN_DAP_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) - -// MSD LED PIO0_20 -#define PIN_MSD_LED_PORT 0 -#define PIN_MSD_LED_BIT 20 -#define PIN_MSD_LED (1 << PIN_MSD_LED_BIT) -#define PIN_MSD_LED_IOCON LPC_IOCON->PIO0_20 -#define PIN_MSD_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) - -// CDC LED PIO0_11 -#define PIN_CDC_LED_PORT 0 -#define PIN_CDC_LED_BIT 11 -#define PIN_CDC_LED (1 << PIN_CDC_LED_BIT) -#define PIN_CDC_LED_IOCON LPC_IOCON->TDI_PIO0_11 -#define PIN_CDC_LED_IOCON_INIT (FUNC_1 | PULL_UP_ENABLED) - -// Non-Forwarded Reset in PIN PIO1_19 -#define PIN_RESET_IN_PORT 1 -#define PIN_RESET_IN_BIT 19 -#define PIN_RESET_IN (1 << PIN_RESET_IN_BIT) -#define PIN_RESET_IN_IOCON LPC_IOCON->PIO1_19 -#define PIN_RESET_IN_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) - -// Forwarded Reset in PIN PIO0_1 -#define PIN_RESET_IN_FWRD_PORT 0 -#define PIN_RESET_IN_FWRD_BIT 1 -#define PIN_RESET_IN_FWRD (1 << PIN_RESET_IN_FWRD_BIT) -#define PIN_RESET_IN_FWRD_IOCON LPC_IOCON->PIO0_1 -#define PIN_RESET_IN_FWRD_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) - -// nRESET OUT Pin PIO0_2 -#define PIN_nRESET_PORT 0 -#define PIN_nRESET_BIT 2 -#define PIN_nRESET (1 << PIN_nRESET_BIT) -#define PIN_nRESET_IOCON LPC_IOCON->PIO0_2 -#define PIN_nRESET_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) - -// SWCLK/TCK Pin PIO0_9 -#define PIN_SWCLK_PORT 0 -#define PIN_SWCLK_BIT 9 -#define PIN_SWCLK (1 << PIN_SWCLK_BIT) -#define PIN_SWCLK_TCK_IOCON LPC_IOCON->PIO0_9 -#define PIN_SWCLK_TCK_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) - -// SWDIO/TMS In/Out Pin PIO0_8 -#define PIN_SWDIO_PORT 0 -#define PIN_SWDIO_BIT 8 -#define PIN_SWDIO (1 << PIN_SWDIO_BIT) -#define PIN_SWDIO_TMS_IOCON LPC_IOCON->PIO0_8 -#define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) - -// TDI Pin PIO0_17 -#define PIN_TDI_PORT 0 -#define PIN_TDI_BIT 17 -#define PIN_TDI (1 << PIN_TDI_BIT) -#define PIN_TDI_IOCON LPC_IOCON->PIO0_17 -#define PIN_TDI_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) - -// SWO/TDO Pin PIO0_010 -#define PIN_TDO_PORT 0 -#define PIN_TDO_BIT 10 -#define PIN_TDO (1 << PIN_TDO_BIT) -#define PIN_TDO_IOCON LPC_IOCON->PIO0_010 -#define PIN_TDO_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) - -#endif From ebacc7a20b7335ef39de34d2a1d54491e18aa931 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 22:34:16 -0500 Subject: [PATCH 374/617] deprecation: remove k20dx_rbl_if project --- projects.yaml | 4 ---- records/board/rbl.yaml | 7 ------- source/board/rbl.c | 32 -------------------------------- test/info.py | 2 -- 4 files changed, 45 deletions(-) delete mode 100644 records/board/rbl.yaml delete mode 100644 source/board/rbl.c diff --git a/projects.yaml b/projects.yaml index f33b88100..b0e7682e9 100644 --- a/projects.yaml +++ b/projects.yaml @@ -287,10 +287,6 @@ projects: - *module_if - *module_hic_k20dx - records/board/rapid_iot.yaml - k20dx_rbl_if: - - *module_if - - *module_hic_k20dx - - records/board/rbl.yaml k20dx_rblnano_if: - *module_if - *module_hic_k20dx diff --git a/records/board/rbl.yaml b/records/board/rbl.yaml deleted file mode 100644 index 09fb0ebba..000000000 --- a/records/board/rbl.yaml +++ /dev/null @@ -1,7 +0,0 @@ -common: - sources: - board: - - source/board/rbl.c - family: - - source/family/nordic/nrf51822/target_nrf51.c - - source/family/nordic/target_reset_nrf51.c diff --git a/source/board/rbl.c b/source/board/rbl.c deleted file mode 100644 index c23c0bb00..000000000 --- a/source/board/rbl.c +++ /dev/null @@ -1,32 +0,0 @@ -/** - * @file rbl.c - * @brief board ID for the Red Bear Labs Arduino based nRF51822 board - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_board.h" -#include "target_family.h" - -extern target_cfg_t target_device_nrf51822_16; - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "1090", - .family_id = kNordic_Nrf51_FamilyID, - .target_cfg = &target_device_nrf51822_16, -}; diff --git a/test/info.py b/test/info.py index e18caf7c9..6e6dad9fd 100644 --- a/test/info.py +++ b/test/info.py @@ -72,7 +72,6 @@ ("lpc11u35_sscity_if", False, 0x0000, "bin" ), ("lpc11u35_ssci824_if", False, 0x0000, "bin" ), ("lpc11u35_ro359b_if", False, 0x0000, "bin" ), - ("k20dx_rbl_if", True, 0x5000, "bin" ), ("k20dx_rblnano_if", True, 0x5000, "bin" ), ("lpc11u35_archlink_if", False, 0x0000, "bin" ), ("lpc11u35_tiny_if", False, 0x0000, "bin" ), @@ -195,7 +194,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x1060, VENDOR_TO_FAMILY('NXP', 0), 'lpc11u35_lpc4088qsb_if', None, 'EA-LPC4088' ), ( 0x1062, VENDOR_TO_FAMILY('NXP', 0), 'lpc11u35_lpc4088dm_if', None, 'EA-LPC4088-Display-Module' ), ( 0x1070, VENDOR_TO_FAMILY('Nordic', 1), 'sam3u2c_mkit_dk_dongle_nrf5x_if', 'sam3u2c_bl', 'Nordic-nRF51822' ), - ( 0x1090, VENDOR_TO_FAMILY('Nordic', 1), 'k20dx_rbl_if', 'k20dx_bl', 'RedBearLab-nRF51822' ), ( 0x1095, VENDOR_TO_FAMILY('Nordic', 1), 'k20dx_rblnano_if', 'k20dx_bl', 'RedBearLab-BLE-Nano' ), ( 0x1100, VENDOR_TO_FAMILY('Nordic', 1), 'sam3u2c_mkit_dk_dongle_nrf5x_if', 'sam3u2c_bl', 'Nordic-nRF51-DK' ), ( 0x1101, VENDOR_TO_FAMILY('Nordic', 2), 'sam3u2c_mkit_dk_dongle_nrf5x_if', 'sam3u2c_bl', 'Nordic-nRF52-DK' ), From e3b7bfb4218c13534b687af9a2825d379ebebbc9 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 22:35:52 -0500 Subject: [PATCH 375/617] deprecation: remove k20dx_rblnano_if project --- projects.yaml | 4 ---- records/board/rblnano.yaml | 7 ------- source/board/rblnano.c | 32 -------------------------------- test/info.py | 2 -- 4 files changed, 45 deletions(-) delete mode 100644 records/board/rblnano.yaml delete mode 100644 source/board/rblnano.c diff --git a/projects.yaml b/projects.yaml index b0e7682e9..50e3fb6b2 100644 --- a/projects.yaml +++ b/projects.yaml @@ -287,10 +287,6 @@ projects: - *module_if - *module_hic_k20dx - records/board/rapid_iot.yaml - k20dx_rblnano_if: - - *module_if - - *module_hic_k20dx - - records/board/rblnano.yaml k20dx_twrke18f_if: - *module_if - *module_hic_k20dx diff --git a/records/board/rblnano.yaml b/records/board/rblnano.yaml deleted file mode 100644 index 327e2c7c6..000000000 --- a/records/board/rblnano.yaml +++ /dev/null @@ -1,7 +0,0 @@ -common: - sources: - board: - - source/board/rblnano.c - family: - - source/family/nordic/nrf51822/target_nrf51.c - - source/family/nordic/target_reset_nrf51.c diff --git a/source/board/rblnano.c b/source/board/rblnano.c deleted file mode 100644 index bc236a5ca..000000000 --- a/source/board/rblnano.c +++ /dev/null @@ -1,32 +0,0 @@ -/** - * @file rblnano.c - * @brief board ID for the Red Bear Labs Nano board - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_board.h" -#include "target_family.h" - -extern target_cfg_t target_device_nrf51822_16; - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "1095", - .family_id = kNordic_Nrf51_FamilyID, - .target_cfg = &target_device_nrf51822_16, -}; diff --git a/test/info.py b/test/info.py index 6e6dad9fd..b13f7b8b3 100644 --- a/test/info.py +++ b/test/info.py @@ -72,7 +72,6 @@ ("lpc11u35_sscity_if", False, 0x0000, "bin" ), ("lpc11u35_ssci824_if", False, 0x0000, "bin" ), ("lpc11u35_ro359b_if", False, 0x0000, "bin" ), - ("k20dx_rblnano_if", True, 0x5000, "bin" ), ("lpc11u35_archlink_if", False, 0x0000, "bin" ), ("lpc11u35_tiny_if", False, 0x0000, "bin" ), ("lpc11u35_c027_if", False, 0x0000, "bin" ), @@ -194,7 +193,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x1060, VENDOR_TO_FAMILY('NXP', 0), 'lpc11u35_lpc4088qsb_if', None, 'EA-LPC4088' ), ( 0x1062, VENDOR_TO_FAMILY('NXP', 0), 'lpc11u35_lpc4088dm_if', None, 'EA-LPC4088-Display-Module' ), ( 0x1070, VENDOR_TO_FAMILY('Nordic', 1), 'sam3u2c_mkit_dk_dongle_nrf5x_if', 'sam3u2c_bl', 'Nordic-nRF51822' ), - ( 0x1095, VENDOR_TO_FAMILY('Nordic', 1), 'k20dx_rblnano_if', 'k20dx_bl', 'RedBearLab-BLE-Nano' ), ( 0x1100, VENDOR_TO_FAMILY('Nordic', 1), 'sam3u2c_mkit_dk_dongle_nrf5x_if', 'sam3u2c_bl', 'Nordic-nRF51-DK' ), ( 0x1101, VENDOR_TO_FAMILY('Nordic', 2), 'sam3u2c_mkit_dk_dongle_nrf5x_if', 'sam3u2c_bl', 'Nordic-nRF52-DK' ), ( 0x1102, VENDOR_TO_FAMILY('Nordic', 2), 'sam3u2c_mkit_dk_dongle_nrf5x_if', 'sam3u2c_bl', 'Nordic-nRF52840-DK' ), From 4fe510ac168c41682e76db37f7c5190d01293870 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 22:37:09 -0500 Subject: [PATCH 376/617] deprecation: remove lpc11u35_6lowpan_borderrouterethernet_if project --- projects.yaml | 4 --- .../board/6LoWPAN_BorderRouterETHERNET.yaml | 12 -------- source/board/6LoWPAN_BorderRouterETHERNET.c | 30 ------------------- test/info.py | 2 -- 4 files changed, 48 deletions(-) delete mode 100644 records/board/6LoWPAN_BorderRouterETHERNET.yaml delete mode 100644 source/board/6LoWPAN_BorderRouterETHERNET.c diff --git a/projects.yaml b/projects.yaml index 50e3fb6b2..ed580f1d0 100644 --- a/projects.yaml +++ b/projects.yaml @@ -323,10 +323,6 @@ projects: - *module_if - *module_hic_kl27z - records/board/microbitv2.yaml - lpc11u35_6lowpan_borderrouterethernet_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/6LoWPAN_BorderRouterETHERNET.yaml lpc11u35_6lowpan_borderrouterhat_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/6LoWPAN_BorderRouterETHERNET.yaml b/records/board/6LoWPAN_BorderRouterETHERNET.yaml deleted file mode 100644 index 8fc5b8f4a..000000000 --- a/records/board/6LoWPAN_BorderRouterETHERNET.yaml +++ /dev/null @@ -1,12 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_lpc11u35_6LoWPAN_BorderRouter - sources: - board: - - source/board/6LoWPAN_BorderRouterETHERNET.c - family: - - source/family/freescale/k64f/target.c - - source/family/freescale/target_reset_Kseries.c - diff --git a/source/board/6LoWPAN_BorderRouterETHERNET.c b/source/board/6LoWPAN_BorderRouterETHERNET.c deleted file mode 100644 index c11037dbf..000000000 --- a/source/board/6LoWPAN_BorderRouterETHERNET.c +++ /dev/null @@ -1,30 +0,0 @@ -/** - * @file 6LoWPAN_BorderRouterETHERNET.c - * @brief board ID for the 6LoWPAN_BorderRouterETHERNET - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_board.h" -#include "target_family.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "7404", - .family_id = kNXP_KinetisK_FamilyID, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index b13f7b8b3..70dd106bf 100644 --- a/test/info.py +++ b/test/info.py @@ -86,7 +86,6 @@ ("k20dx_xdot_l151_if", False, 0x8000, "bin" ), ('lpc11u35_6lowpan_borderrouterhat_if', None, 0x0000, "bin" ), ('lpc11u35_6lowpan_borderrouterusb_if', None, 0x0000, "bin" ), - ('lpc11u35_6lowpan_borderrouterethernet_if', None, 0x0000, "bin" ), ('lpc11u35_gr_peach_if', None, 0x0000, "bin" ), ('lpc11u35_gr_lychee_if', None, 0x0000, "bin" ), ('lpc11u35_nz32_sc151_if', False, 0x0000, "bin" ), @@ -222,7 +221,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x7010, VENDOR_TO_FAMILY('Toshiba', 1), 'lpc11u35_blueninja_if', None, None ), # TODO - set target to 'BlueNinja-CDP-TZ01B' when mbed-os supports this ( 0x7402, VENDOR_TO_FAMILY('NXP', 1), 'lpc11u35_6lowpan_borderrouterhat_if', None, 'mbed-6LoWPAN-Border-Router-HAT' ), ( 0x7403, VENDOR_TO_FAMILY('NXP', 1), 'lpc11u35_6lowpan_borderrouterusb_if', None, 'mbed-6LoWPAN-Border-Router-USB' ), - ( 0x7404, VENDOR_TO_FAMILY('NXP', 1), 'lpc11u35_6lowpan_borderrouterethernet_if', None, 'mbed-6LoWPAN-Border-Router-ETHERNET' ), ( 0x8080, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_ff1705_l151_if', None, None ), # TODO - set target to 'L-TEK-FF1705' when mbed-os supports this ( 0x8081, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_ff_lpc546xx_if', None, None ), # TODO - set target to 'L-TEK-FF-LPC546XX' when mbed-os supports this ( 0x9004, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_archpro_if', None, 'Seeeduino-Arch-Pro' ), From 6d1fe9840d2945692dc1e16e85781c17bd7cfa52 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 22:38:06 -0500 Subject: [PATCH 377/617] deprecation: remove lpc11u35_6lowpan_borderrouterhat_if project --- projects.yaml | 4 --- records/board/6LoWPAN_BorderRouterHAT.yaml | 12 --------- source/board/6LoWPAN_BorderRouterHAT.c | 30 ---------------------- test/info.py | 2 -- 4 files changed, 48 deletions(-) delete mode 100644 records/board/6LoWPAN_BorderRouterHAT.yaml delete mode 100644 source/board/6LoWPAN_BorderRouterHAT.c diff --git a/projects.yaml b/projects.yaml index ed580f1d0..4bbdd5ef4 100644 --- a/projects.yaml +++ b/projects.yaml @@ -323,10 +323,6 @@ projects: - *module_if - *module_hic_kl27z - records/board/microbitv2.yaml - lpc11u35_6lowpan_borderrouterhat_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/6LoWPAN_BorderRouterHAT.yaml lpc11u35_6lowpan_borderrouterusb_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/6LoWPAN_BorderRouterHAT.yaml b/records/board/6LoWPAN_BorderRouterHAT.yaml deleted file mode 100644 index d97455272..000000000 --- a/records/board/6LoWPAN_BorderRouterHAT.yaml +++ /dev/null @@ -1,12 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_lpc11u35_6LoWPAN_BorderRouter - sources: - board: - - source/board/6LoWPAN_BorderRouterHAT.c - family: - - source/family/freescale/k64f/target.c - - source/family/freescale/target_reset_Kseries.c - diff --git a/source/board/6LoWPAN_BorderRouterHAT.c b/source/board/6LoWPAN_BorderRouterHAT.c deleted file mode 100644 index a4f3b4d6b..000000000 --- a/source/board/6LoWPAN_BorderRouterHAT.c +++ /dev/null @@ -1,30 +0,0 @@ -/** - * @file 6LoWPAN_BorderRouterHAT.c - * @brief board ID for the 6LoWPAN_BorderRouterHAT - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_board.h" -#include "target_family.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "7402", - .family_id = kNXP_KinetisK_FamilyID, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index 70dd106bf..30ecf7dd1 100644 --- a/test/info.py +++ b/test/info.py @@ -84,7 +84,6 @@ ('lpc11u35_ff_lpc546xx_if', False, 0x0000, "bin" ), ('lpc11u35_mini_iot_lpc54018_if', False, 0x0000, "bin" ), ("k20dx_xdot_l151_if", False, 0x8000, "bin" ), - ('lpc11u35_6lowpan_borderrouterhat_if', None, 0x0000, "bin" ), ('lpc11u35_6lowpan_borderrouterusb_if', None, 0x0000, "bin" ), ('lpc11u35_gr_peach_if', None, 0x0000, "bin" ), ('lpc11u35_gr_lychee_if', None, 0x0000, "bin" ), @@ -219,7 +218,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x5501, VENDOR_TO_FAMILY('Renesas', 1), 'lpc11u35_gr_lychee_if', None, None ), # TODO - Set to 'Renesas-GR-LYCHEE' once this target builds ( 0x6660, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_nz32_sc151_if', None, None ), # TODO - set target to 'NZ32-SC151' when mbed-os supports this ( 0x7010, VENDOR_TO_FAMILY('Toshiba', 1), 'lpc11u35_blueninja_if', None, None ), # TODO - set target to 'BlueNinja-CDP-TZ01B' when mbed-os supports this - ( 0x7402, VENDOR_TO_FAMILY('NXP', 1), 'lpc11u35_6lowpan_borderrouterhat_if', None, 'mbed-6LoWPAN-Border-Router-HAT' ), ( 0x7403, VENDOR_TO_FAMILY('NXP', 1), 'lpc11u35_6lowpan_borderrouterusb_if', None, 'mbed-6LoWPAN-Border-Router-USB' ), ( 0x8080, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_ff1705_l151_if', None, None ), # TODO - set target to 'L-TEK-FF1705' when mbed-os supports this ( 0x8081, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_ff_lpc546xx_if', None, None ), # TODO - set target to 'L-TEK-FF-LPC546XX' when mbed-os supports this From 4c128e2d759c79a77d6d7d87b6938542b40e96b7 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 22:39:07 -0500 Subject: [PATCH 378/617] deprecation: remove lpc11u35_6lowpan_borderrouterusb_if project --- projects.yaml | 4 --- records/board/6LoWPAN_BorderRouterUSB.yaml | 12 --------- source/board/6LoWPAN_BorderRouterUSB.c | 31 ---------------------- test/info.py | 2 -- 4 files changed, 49 deletions(-) delete mode 100644 records/board/6LoWPAN_BorderRouterUSB.yaml delete mode 100644 source/board/6LoWPAN_BorderRouterUSB.c diff --git a/projects.yaml b/projects.yaml index 4bbdd5ef4..3407590d0 100644 --- a/projects.yaml +++ b/projects.yaml @@ -323,10 +323,6 @@ projects: - *module_if - *module_hic_kl27z - records/board/microbitv2.yaml - lpc11u35_6lowpan_borderrouterusb_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/6LoWPAN_BorderRouterUSB.yaml lpc11u35_96b_nitrogen_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/6LoWPAN_BorderRouterUSB.yaml b/records/board/6LoWPAN_BorderRouterUSB.yaml deleted file mode 100644 index 208364419..000000000 --- a/records/board/6LoWPAN_BorderRouterUSB.yaml +++ /dev/null @@ -1,12 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_lpc11u35_6LoWPAN_BorderRouter - sources: - board: - - source/board/6LoWPAN_BorderRouterUSB.c - family: - - source/family/freescale/k64f/target.c - - source/family/freescale/target_reset_Kseries.c - diff --git a/source/board/6LoWPAN_BorderRouterUSB.c b/source/board/6LoWPAN_BorderRouterUSB.c deleted file mode 100644 index 7e18e7e2c..000000000 --- a/source/board/6LoWPAN_BorderRouterUSB.c +++ /dev/null @@ -1,31 +0,0 @@ -/** - * @file 6LoWPAN_BorderRouterUSB.c - * @brief board ID for the 6LoWPAN_BorderRouterUSB - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_board.h" -#include "target_family.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "7403", - .family_id = kNXP_KinetisK_FamilyID, - .target_cfg = &target_device, -}; - diff --git a/test/info.py b/test/info.py index 30ecf7dd1..419463ae6 100644 --- a/test/info.py +++ b/test/info.py @@ -84,7 +84,6 @@ ('lpc11u35_ff_lpc546xx_if', False, 0x0000, "bin" ), ('lpc11u35_mini_iot_lpc54018_if', False, 0x0000, "bin" ), ("k20dx_xdot_l151_if", False, 0x8000, "bin" ), - ('lpc11u35_6lowpan_borderrouterusb_if', None, 0x0000, "bin" ), ('lpc11u35_gr_peach_if', None, 0x0000, "bin" ), ('lpc11u35_gr_lychee_if', None, 0x0000, "bin" ), ('lpc11u35_nz32_sc151_if', False, 0x0000, "bin" ), @@ -218,7 +217,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x5501, VENDOR_TO_FAMILY('Renesas', 1), 'lpc11u35_gr_lychee_if', None, None ), # TODO - Set to 'Renesas-GR-LYCHEE' once this target builds ( 0x6660, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_nz32_sc151_if', None, None ), # TODO - set target to 'NZ32-SC151' when mbed-os supports this ( 0x7010, VENDOR_TO_FAMILY('Toshiba', 1), 'lpc11u35_blueninja_if', None, None ), # TODO - set target to 'BlueNinja-CDP-TZ01B' when mbed-os supports this - ( 0x7403, VENDOR_TO_FAMILY('NXP', 1), 'lpc11u35_6lowpan_borderrouterusb_if', None, 'mbed-6LoWPAN-Border-Router-USB' ), ( 0x8080, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_ff1705_l151_if', None, None ), # TODO - set target to 'L-TEK-FF1705' when mbed-os supports this ( 0x8081, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_ff_lpc546xx_if', None, None ), # TODO - set target to 'L-TEK-FF-LPC546XX' when mbed-os supports this ( 0x9004, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_archpro_if', None, 'Seeeduino-Arch-Pro' ), From 90069c24b2ff9450f8b8969e3df11ae64fb25dea Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 22:40:00 -0500 Subject: [PATCH 379/617] deprecation: remove IO override header used for 6lowpan_borderrouter boards --- .../IO_Config_Override.h | 108 ------------------ 1 file changed, 108 deletions(-) delete mode 100644 source/board/override_lpc11u35_6LoWPAN_BorderRouter/IO_Config_Override.h diff --git a/source/board/override_lpc11u35_6LoWPAN_BorderRouter/IO_Config_Override.h b/source/board/override_lpc11u35_6LoWPAN_BorderRouter/IO_Config_Override.h deleted file mode 100644 index 620de1a18..000000000 --- a/source/board/override_lpc11u35_6LoWPAN_BorderRouter/IO_Config_Override.h +++ /dev/null @@ -1,108 +0,0 @@ -/** - * @file IO_Config_Override.c - * @brief Alternative IO for LPC11U35 based Hardware Interface Circuit for all 6LoWPAN_BorderRouter, Moved SWCLK - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __IO_CONFIG_H__ -#define __IO_CONFIG_H__ - -#include "LPC11Uxx.h" -#include "daplink.h" - -// This GPIO configuration is only valid for the LPC11U35 HIC -COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35); - -// Peripheral register bit masks (used for pin inits) -#define FUNC_0 0 -#define FUNC_1 1 -#define PULL_DOWN_ENABLED (1 << 3) -#define PULL_UP_ENABLED (2 << 3) -#define OPENDRAIN (1 << 10) - -// DAP LED PIO0_21 -#define PIN_DAP_LED_PORT 0 -#define PIN_DAP_LED_BIT 21 -#define PIN_DAP_LED (1 << PIN_DAP_LED_BIT) -#define PIN_DAP_LED_IOCON LPC_IOCON->PIO0_21 -#define PIN_DAP_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) - -// MSD LED PIO0_20 -#define PIN_MSD_LED_PORT 0 -#define PIN_MSD_LED_BIT 20 -#define PIN_MSD_LED (1 << PIN_MSD_LED_BIT) -#define PIN_MSD_LED_IOCON LPC_IOCON->PIO0_20 -#define PIN_MSD_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) - -// CDC LED PIO0_11 -#define PIN_CDC_LED_PORT 0 -#define PIN_CDC_LED_BIT 11 -#define PIN_CDC_LED (1 << PIN_CDC_LED_BIT) -#define PIN_CDC_LED_IOCON LPC_IOCON->TDI_PIO0_11 -#define PIN_CDC_LED_IOCON_INIT (FUNC_1 | PULL_UP_ENABLED) - -// Non-Forwarded Reset in PIN PIO1_19 -#define PIN_RESET_IN_PORT 1 -#define PIN_RESET_IN_BIT 19 -#define PIN_RESET_IN (1 << PIN_RESET_IN_BIT) -#define PIN_RESET_IN_IOCON LPC_IOCON->PIO1_19 -#define PIN_RESET_IN_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) - -// Forwarded Reset in PIN PIO0_1 -#define PIN_RESET_IN_FWRD_PORT 0 -#define PIN_RESET_IN_FWRD_BIT 1 -#define PIN_RESET_IN_FWRD (1 << PIN_RESET_IN_FWRD_BIT) -#define PIN_RESET_IN_FWRD_IOCON LPC_IOCON->PIO0_1 -#define PIN_RESET_IN_FWRD_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) - -// nRESET OUT Pin PIO0_2 -#define PIN_nRESET_PORT 0 -#define PIN_nRESET_BIT 2 -#define PIN_nRESET (1 << PIN_nRESET_BIT) -#define PIN_nRESET_IOCON LPC_IOCON->PIO0_2 -#define PIN_nRESET_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) - -// SWCLK/TCK Pin PIO0_9 -#define PIN_SWCLK_PORT 0 -#define PIN_SWCLK_BIT 9 -#define PIN_SWCLK (1 << PIN_SWCLK_BIT) -#define PIN_SWCLK_TCK_IOCON LPC_IOCON->PIO0_9 -#define PIN_SWCLK_TCK_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) - -// SWDIO/TMS In/Out Pin PIO0_8 -#define PIN_SWDIO_PORT 0 -#define PIN_SWDIO_BIT 8 -#define PIN_SWDIO (1 << PIN_SWDIO_BIT) -#define PIN_SWDIO_TMS_IOCON LPC_IOCON->PIO0_8 -#define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) - -// TDI Pin PIO0_17 -#define PIN_TDI_PORT 0 -#define PIN_TDI_BIT 17 -#define PIN_TDI (1 << PIN_TDI_BIT) -#define PIN_TDI_IOCON LPC_IOCON->PIO0_17 -#define PIN_TDI_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) - -// SWO/TDO Pin PIO0_010 -#define PIN_TDO_PORT 0 -#define PIN_TDO_BIT 10 -#define PIN_TDO (1 << PIN_TDO_BIT) -#define PIN_TDO_IOCON LPC_IOCON->PIO0_010 -#define PIN_TDO_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) - -#endif From 1bbf166d4aa75093321c8d4341adfa9e3d03e6b1 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 22:43:12 -0500 Subject: [PATCH 380/617] deprecation: remove lpc11u35_vbluno51_if project --- projects.yaml | 4 - records/board/vbluno51.yaml | 11 -- .../override_vbluno51/IO_Config_Override.h | 113 ------------------ source/board/vbluno51.c | 40 ------- test/info.py | 3 - 5 files changed, 171 deletions(-) delete mode 100644 records/board/vbluno51.yaml delete mode 100644 source/board/override_vbluno51/IO_Config_Override.h delete mode 100644 source/board/vbluno51.c diff --git a/projects.yaml b/projects.yaml index 3407590d0..f5a4aae3c 100644 --- a/projects.yaml +++ b/projects.yaml @@ -438,10 +438,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/tiny.yaml - lpc11u35_vbluno51_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/vbluno51.yaml lpc11u35_wio3g_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/vbluno51.yaml b/records/board/vbluno51.yaml deleted file mode 100644 index 5a62cdc30..000000000 --- a/records/board/vbluno51.yaml +++ /dev/null @@ -1,11 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_vbluno51 - sources: - board: - - source/board/vbluno51.c - family: - - source/family/nordic/nrf51822/target_nrf51.c - - source/family/nordic/target_reset_nrf51.c diff --git a/source/board/override_vbluno51/IO_Config_Override.h b/source/board/override_vbluno51/IO_Config_Override.h deleted file mode 100644 index 44214d9a0..000000000 --- a/source/board/override_vbluno51/IO_Config_Override.h +++ /dev/null @@ -1,113 +0,0 @@ -/** - * @file IO_Config_Override.c - * @brief Alternative IO for LPC11U35 based Hardware Interface Circuit - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2017, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - * The VBLUno51 board use PIO0_9(18) pin for TGT_SWCLK function. - * Because it uses RTS/CTS pins for UART Hardware flow control feature. - */ - -#ifndef __IO_CONFIG_H__ -#define __IO_CONFIG_H__ - -#include "LPC11Uxx.h" -#include "daplink.h" - -// This GPIO configuration is only valid for the LPC11U35 HIC -COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC11U35); - -// Peripheral register bit masks (used for pin inits) -#define FUNC_0 0 -#define FUNC_1 1 -#define PULL_DOWN_ENABLED (1 << 3) -#define PULL_UP_ENABLED (2 << 3) -#define OPENDRAIN (1 << 10) - -// DAP LED PIO0_21 -#define PIN_DAP_LED_PORT 0 -#define PIN_DAP_LED_BIT 21 -#define PIN_DAP_LED (1 << PIN_DAP_LED_BIT) -#define PIN_DAP_LED_IOCON LPC_IOCON->PIO0_21 -#define PIN_DAP_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) - -// MSD LED PIO0_20 -#define PIN_MSD_LED_PORT 0 -#define PIN_MSD_LED_BIT 20 -#define PIN_MSD_LED (1 << PIN_MSD_LED_BIT) -#define PIN_MSD_LED_IOCON LPC_IOCON->PIO0_20 -#define PIN_MSD_LED_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) - -// CDC LED PIO0_11 -#define PIN_CDC_LED_PORT 0 -#define PIN_CDC_LED_BIT 11 -#define PIN_CDC_LED (1 << PIN_CDC_LED_BIT) -#define PIN_CDC_LED_IOCON LPC_IOCON->TDI_PIO0_11 -#define PIN_CDC_LED_IOCON_INIT (FUNC_1 | PULL_UP_ENABLED) - -// Non-Forwarded Reset in PIN PIO1_19 -#define PIN_RESET_IN_PORT 1 -#define PIN_RESET_IN_BIT 19 -#define PIN_RESET_IN (1 << PIN_RESET_IN_BIT) -#define PIN_RESET_IN_IOCON LPC_IOCON->PIO1_19 -#define PIN_RESET_IN_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) - -// Forwarded Reset in PIN PIO0_1 -#define PIN_RESET_IN_FWRD_PORT 0 -#define PIN_RESET_IN_FWRD_BIT 1 -#define PIN_RESET_IN_FWRD (1 << PIN_RESET_IN_FWRD_BIT) -#define PIN_RESET_IN_FWRD_IOCON LPC_IOCON->PIO0_1 -#define PIN_RESET_IN_FWRD_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) - -// nRESET OUT Pin PIO0_2 -#define PIN_nRESET_PORT 0 -#define PIN_nRESET_BIT 2 -#define PIN_nRESET (1 << PIN_nRESET_BIT) -#define PIN_nRESET_IOCON LPC_IOCON->PIO0_2 -#define PIN_nRESET_IOCON_INIT (FUNC_0 | OPENDRAIN | PULL_UP_ENABLED) - -// SWCLK/TCK Pin PIO0_9 -#define PIN_SWCLK_PORT 0 -#define PIN_SWCLK_BIT 9 -#define PIN_SWCLK (1 << PIN_SWCLK_BIT) -#define PIN_SWCLK_TCK_IOCON LPC_IOCON->PIO0_9 -#define PIN_SWCLK_TCK_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) - -// SWDIO/TMS In/Out Pin PIO0_8 -#define PIN_SWDIO_PORT 0 -#define PIN_SWDIO_BIT 8 -#define PIN_SWDIO (1 << PIN_SWDIO_BIT) -#define PIN_SWDIO_TMS_IOCON LPC_IOCON->PIO0_8 -#define PIN_SWDIO_TMS_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) - -// TDI Pin PIO0_17 -#define PIN_TDI_PORT 0 -#define PIN_TDI_BIT 17 -#define PIN_TDI (1 << PIN_TDI_BIT) -#define PIN_TDI_IOCON LPC_IOCON->PIO0_17 -#define PIN_TDI_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) - -// SWO/TDO Pin PIO0_9 -#define PIN_TDO_PORT 0 -#define PIN_TDO_BIT 9 -#define PIN_TDO (1 << PIN_TDO_BIT) -#define PIN_TDO_IOCON LPC_IOCON->PIO0_9 -#define PIN_TDO_IOCON_INIT (FUNC_0 | PULL_UP_ENABLED) - -#endif diff --git a/source/board/vbluno51.c b/source/board/vbluno51.c deleted file mode 100644 index edf5bdaf1..000000000 --- a/source/board/vbluno51.c +++ /dev/null @@ -1,40 +0,0 @@ -/** - * @file vbluno51.c - * @brief Board ID for the VBLUno51 board (VNG Bluetooth Low Energy UNO nRF51822 board) - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "uart.h" -#include "target_board.h" -#include "target_family.h" - -static void vbluno_prerun_board_config() -{ - uart_enable_flow_control(false); -} - -extern target_cfg_t target_device_nrf51822_32; - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "C006", - .family_id = kNordic_Nrf51_FamilyID, - .daplink_target_url = "https://os.mbed.com/platforms/VBLUNO51/", - .prerun_board_config = vbluno_prerun_board_config, - .target_cfg = &target_device_nrf51822_32, -}; diff --git a/test/info.py b/test/info.py index 419463ae6..108858c54 100644 --- a/test/info.py +++ b/test/info.py @@ -91,7 +91,6 @@ ('lpc11u35_wizwiki_w7500_eco_if', False, 0x0000, "bin" ), ('lpc11u35_wizwiki_w7500p_if', False, 0x0000, "bin" ), ("sam3u2c_ublox_evk_nina_b1_if", True, 0x5000, "bin" ), - ("lpc11u35_vbluno51_if", False, 0x0000, "bin" ), ("lpc11u35_rtl8195am_if", False, 0x0000, "bin" ), ("lpc11u35_96b_nitrogen_if", False, 0x0000, "bin" ), ('lpc11u35_musca_a_if', False, 0x0000, "bin" ), @@ -233,7 +232,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x9903, VENDOR_TO_FAMILY('Nordic', 2), 'kl27z_microbit_if', 'kl27z_bl', 'Microbitv2' ), ( 0x9904, VENDOR_TO_FAMILY('Nordic', 2), 'kl27z_microbit_if', 'kl27z_bl', 'Microbitv2' ), ( 0xA127, VENDOR_TO_FAMILY('Ambiq', 1), 'kl26z_artemis_dk_if', 'kl26z_bl', 'ARTMBED' ), - ( 0xC006, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_vbluno51_if', None, 'VBLUNO51' ), ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'kl26z_if', None, None ), ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'k20dx_if', None, None ), ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'k26f_if', None, None ), @@ -339,7 +337,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y 'SSCI-MBIT', 'BlueNinja', 'U-BLOX-EVK-NINA-B1', - 'VNG-VBLUno51', 'REALTEK-RTL8195AM'] BOARD_ID_TO_BUILD_TARGET = {config[0]: config[4] for config in From 19f5ece4de3d12891fd7481aece8afb7d3a7ed5a Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 22:59:53 -0500 Subject: [PATCH 381/617] deprecation: remove lpc11u35_wio3g_if project --- projects.yaml | 4 ---- records/board/wio3g.yaml | 6 ------ source/board/wio3g.c | 30 ------------------------------ test/info.py | 2 -- 4 files changed, 42 deletions(-) delete mode 100644 records/board/wio3g.yaml delete mode 100644 source/board/wio3g.c diff --git a/projects.yaml b/projects.yaml index f5a4aae3c..04da327be 100644 --- a/projects.yaml +++ b/projects.yaml @@ -438,10 +438,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/tiny.yaml - lpc11u35_wio3g_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/wio3g.yaml lpc11u35_wio_emw3166_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/wio3g.yaml b/records/board/wio3g.yaml deleted file mode 100644 index 5558edc7d..000000000 --- a/records/board/wio3g.yaml +++ /dev/null @@ -1,6 +0,0 @@ -common: - sources: - board: - - source/board/wio3g.c - family: - - source/family/st/stm32f439zi/target.c diff --git a/source/board/wio3g.c b/source/board/wio3g.c deleted file mode 100644 index c134aa07b..000000000 --- a/source/board/wio3g.c +++ /dev/null @@ -1,30 +0,0 @@ -/** - * @file wio3g.c - * @brief board ID for the mbed cloud connect board - * - * DAPLink Interface Firmware - * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -const board_info_t g_board_info = { - .board_id = "9014", - .family_id = kStub_HWReset_FamilyID, - .flags = kEnablePageErase|kEnableUnderResetConnect, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index 108858c54..d0dd13609 100644 --- a/test/info.py +++ b/test/info.py @@ -65,7 +65,6 @@ ("lpc11u35_archble_if", False, 0x0000, "bin" ), ("lpc11u35_archpro_if", False, 0x0000, "bin" ), ("lpc11u35_archmax_if", False, 0x0000, "bin" ), - ("lpc11u35_wio3g_if", False, 0x0000, "bin" ), ("lpc11u35_wiobg96_if", False, 0x0000, "bin" ), ("lpc11u35_wio_emw3166_if", False, 0x0000, "bin" ), ("lpc11u35_hrm1017_if", False, 0x0000, "bin" ), @@ -223,7 +222,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x9011, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_archmax_if', None, 'Seeed-Arch-Max' ), ( 0x9012, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_tiny_if', None, 'Seeed-Tiny-BLE' ), ( 0x9013, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_archlink_if', None, 'Seeed-Arch-Link' ), - ( 0x9014, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_wio3g_if', None, None ), ( 0x9015, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_wiobg96_if', None, None ), ( 0x9016, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_96b_nitrogen_if', None, None ), # TODO - set target to 'Seeed-96Boards-Nitrogen' when mbed-os supports this ( 0x9017, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_wio_emw3166_if', None, 'WIO_EMW3166' ), # TODO - set target to 'Seeed-96Boards-Nitrogen' when mbed-os supports this From 6e2a3a72b90ad9888df060b7c2c5a3f27a654323 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 23:00:53 -0500 Subject: [PATCH 382/617] deprecation: remove lpc11u35_wio_emw3166_if project --- projects.yaml | 4 ---- records/board/wio_emw3166.yaml | 6 ------ source/board/wio_emw3166.c | 31 ------------------------------- test/info.py | 2 -- 4 files changed, 43 deletions(-) delete mode 100644 records/board/wio_emw3166.yaml delete mode 100644 source/board/wio_emw3166.c diff --git a/projects.yaml b/projects.yaml index 04da327be..f546b088c 100644 --- a/projects.yaml +++ b/projects.yaml @@ -438,10 +438,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/tiny.yaml - lpc11u35_wio_emw3166_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/wio_emw3166.yaml lpc11u35_wiobg96_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/wio_emw3166.yaml b/records/board/wio_emw3166.yaml deleted file mode 100644 index 2ca78d8c0..000000000 --- a/records/board/wio_emw3166.yaml +++ /dev/null @@ -1,6 +0,0 @@ -common: - sources: - board: - - source/board/wio_emw3166.c - family: - - source/family/st/stm32f412rg/target.c diff --git a/source/board/wio_emw3166.c b/source/board/wio_emw3166.c deleted file mode 100644 index 473445e6c..000000000 --- a/source/board/wio_emw3166.c +++ /dev/null @@ -1,31 +0,0 @@ -/** - * @file wio_emw3166.c - * @brief board ID for Seeed Wio EMW3166 - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "9017", - .family_id = kStub_HWReset_FamilyID, - .flags = kEnablePageErase|kEnableUnderResetConnect, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index d0dd13609..81c3caa2b 100644 --- a/test/info.py +++ b/test/info.py @@ -66,7 +66,6 @@ ("lpc11u35_archpro_if", False, 0x0000, "bin" ), ("lpc11u35_archmax_if", False, 0x0000, "bin" ), ("lpc11u35_wiobg96_if", False, 0x0000, "bin" ), - ("lpc11u35_wio_emw3166_if", False, 0x0000, "bin" ), ("lpc11u35_hrm1017_if", False, 0x0000, "bin" ), ("lpc11u35_sscity_if", False, 0x0000, "bin" ), ("lpc11u35_ssci824_if", False, 0x0000, "bin" ), @@ -224,7 +223,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x9013, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_archlink_if', None, 'Seeed-Arch-Link' ), ( 0x9015, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_wiobg96_if', None, None ), ( 0x9016, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_96b_nitrogen_if', None, None ), # TODO - set target to 'Seeed-96Boards-Nitrogen' when mbed-os supports this - ( 0x9017, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_wio_emw3166_if', None, 'WIO_EMW3166' ), # TODO - set target to 'Seeed-96Boards-Nitrogen' when mbed-os supports this ( 0x9900, VENDOR_TO_FAMILY('Nordic', 1), 'kl26z_microbit_if', 'kl26z_bl', 'Microbit' ), ( 0x9901, VENDOR_TO_FAMILY('Nordic', 1), 'kl26z_microbit_if', 'kl26z_bl', 'Microbit' ), ( 0x9903, VENDOR_TO_FAMILY('Nordic', 2), 'kl27z_microbit_if', 'kl27z_bl', 'Microbitv2' ), From 23d0fad010229d7b58189b60de0dbda2167c3d4d Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 23:01:32 -0500 Subject: [PATCH 383/617] deprecation: remove unused stm32f412r target --- source/family/st/stm32f412rg/flash_blob.c | 73 ----------------------- source/family/st/stm32f412rg/target.c | 40 ------------- 2 files changed, 113 deletions(-) delete mode 100644 source/family/st/stm32f412rg/flash_blob.c delete mode 100644 source/family/st/stm32f412rg/target.c diff --git a/source/family/st/stm32f412rg/flash_blob.c b/source/family/st/stm32f412rg/flash_blob.c deleted file mode 100644 index a1a10c85d..000000000 --- a/source/family/st/stm32f412rg/flash_blob.c +++ /dev/null @@ -1,73 +0,0 @@ -/* Flash OS Routines (Automagically Generated) - * Copyright (c) 2009-2019 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - #include "flash_blob.h" - -static const uint32_t _flash_prog_blob[] = { - 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, - 0x03004601, 0x28200e00, 0x0940d302, 0xe0051d00, 0xd3022810, 0x1cc00900, 0x0880e000, 0xd50102c9, - 0x43082110, 0x48424770, 0x60414940, 0x60414941, 0x60012100, 0x22f068c1, 0x60c14311, 0x06806940, - 0x483ed406, 0x6001493c, 0x60412106, 0x6081493c, 0x47702000, 0x69014836, 0x43110542, 0x20006101, - 0xb5104770, 0x69014832, 0x43212404, 0x69016101, 0x431103a2, 0x49336101, 0xe0004a30, 0x68c36011, - 0xd4fb03db, 0x43a16901, 0x20006101, 0xb530bd10, 0xffb6f7ff, 0x68ca4926, 0x431a23f0, 0x240260ca, - 0x690a610c, 0x0e0006c0, 0x610a4302, 0x03e26908, 0x61084310, 0x4a214823, 0x6010e000, 0x03ed68cd, - 0x6908d4fb, 0x610843a0, 0x060068c8, 0xd0030f00, 0x431868c8, 0x200160c8, 0xb570bd30, 0x1cc94d14, - 0x68eb0889, 0x26f00089, 0x60eb4333, 0x612b2300, 0xe0174b15, 0x431c692c, 0x6814612c, 0x68ec6004, - 0xd4fc03e4, 0x0864692c, 0x612c0064, 0x062468ec, 0xd0040f24, 0x433068e8, 0x200160e8, 0x1d00bd70, - 0x1f091d12, 0xd1e52900, 0xbd702000, 0x45670123, 0x40023c00, 0xcdef89ab, 0x00005555, 0x40003000, - 0x00000fff, 0x0000aaaa, 0x00000201, 0x00000000 -}; - -// Start address of flash -static const uint32_t flash_start = 0x08000000; -// Size of flash -static const uint32_t flash_size = 0x00080000; - -/** -* List of start and size for each size of flash sector - even indexes are start, odd are size -* The size will apply to all sectors between the listed address and the next address -* in the list. -* The last pair in the list will have sectors starting at that address and ending -* at address flash_start + flash_size. -*/ -static const sector_info_t sectors_info[] = { - { 0x08000000, 0x00004000 }, - { 0x08010000, 0x00010000 }, - { 0x08020000, 0x00020000 }, -}; - -static const program_target_t flash = { - 0x20000047, // Init - 0x20000075, // UnInit - 0x20000083, // EraseChip - 0x200000af, // EraseSector - 0x200000fb, // ProgramPage - 0x0, // Verify - - // BKPT : start of blob + 1 - // RSB : blob start + header + rw data offset - // RSP : stack pointer - { - 0x20000001, - 0x2000016c, - 0x20000800 - }, - - 0x20000000 + 0x00000A00, // mem buffer location - 0x20000000, // location to write prog_blob in target RAM - sizeof(_flash_prog_blob), // prog_blob size - _flash_prog_blob, // address of prog_blob - 0x00000400 // ram_to_flash_bytes_to_be_written -}; diff --git a/source/family/st/stm32f412rg/target.c b/source/family/st/stm32f412rg/target.c deleted file mode 100644 index 52cb24a11..000000000 --- a/source/family/st/stm32f412rg/target.c +++ /dev/null @@ -1,40 +0,0 @@ -/** - * @file target.c - * @brief Target information for the stm32f412rg - * - * DAPLink Interface Firmware - * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_config.h" - -// The file flash_blob.c must only be included in target.c -#include "flash_blob.c" - -// target information -target_cfg_t target_device = { - .version = kTargetConfigVersion, - .sectors_info = sectors_info, - .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), - .flash_regions[0].start = 0x08000000, - .flash_regions[0].end = 0x08100000, - .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, - .ram_regions[0].start = 0x20000000, - .ram_regions[0].end = 0x20040000, - .target_vendor = "STMicroelectronics", - .target_part_number = "STM32F412RGTx", -}; From ff7a531b9d5ea8e9dce316e12ef196629edacfc9 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 23:03:31 -0500 Subject: [PATCH 384/617] deprecation: remove lpc11u35_wiobg96_if project --- projects.yaml | 4 ---- records/board/wiobg96.yaml | 6 ------ source/board/wiobg96.c | 30 ------------------------------ test/info.py | 2 -- 4 files changed, 42 deletions(-) delete mode 100644 records/board/wiobg96.yaml delete mode 100644 source/board/wiobg96.c diff --git a/projects.yaml b/projects.yaml index f546b088c..8c1e5aa61 100644 --- a/projects.yaml +++ b/projects.yaml @@ -438,10 +438,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/tiny.yaml - lpc11u35_wiobg96_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/wiobg96.yaml lpc11u35_wizwiki_w7500_eco_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/wiobg96.yaml b/records/board/wiobg96.yaml deleted file mode 100644 index 521767e2d..000000000 --- a/records/board/wiobg96.yaml +++ /dev/null @@ -1,6 +0,0 @@ -common: - sources: - board: - - source/board/wiobg96.c - family: - - source/family/st/stm32f439zi/target.c diff --git a/source/board/wiobg96.c b/source/board/wiobg96.c deleted file mode 100644 index 629df1db4..000000000 --- a/source/board/wiobg96.c +++ /dev/null @@ -1,30 +0,0 @@ -/** - * @file wiobg96.c - * @brief board ID for the mbed cloud connect board - * - * DAPLink Interface Firmware - * Copyright (c) 2018-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -const board_info_t g_board_info = { - .board_id = "9015", - .family_id = kStub_HWReset_FamilyID, - .flags = kEnablePageErase|kEnableUnderResetConnect, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index 81c3caa2b..cd4046dad 100644 --- a/test/info.py +++ b/test/info.py @@ -65,7 +65,6 @@ ("lpc11u35_archble_if", False, 0x0000, "bin" ), ("lpc11u35_archpro_if", False, 0x0000, "bin" ), ("lpc11u35_archmax_if", False, 0x0000, "bin" ), - ("lpc11u35_wiobg96_if", False, 0x0000, "bin" ), ("lpc11u35_hrm1017_if", False, 0x0000, "bin" ), ("lpc11u35_sscity_if", False, 0x0000, "bin" ), ("lpc11u35_ssci824_if", False, 0x0000, "bin" ), @@ -221,7 +220,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x9011, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_archmax_if', None, 'Seeed-Arch-Max' ), ( 0x9012, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_tiny_if', None, 'Seeed-Tiny-BLE' ), ( 0x9013, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_archlink_if', None, 'Seeed-Arch-Link' ), - ( 0x9015, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_wiobg96_if', None, None ), ( 0x9016, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_96b_nitrogen_if', None, None ), # TODO - set target to 'Seeed-96Boards-Nitrogen' when mbed-os supports this ( 0x9900, VENDOR_TO_FAMILY('Nordic', 1), 'kl26z_microbit_if', 'kl26z_bl', 'Microbit' ), ( 0x9901, VENDOR_TO_FAMILY('Nordic', 1), 'kl26z_microbit_if', 'kl26z_bl', 'Microbit' ), From 7ca112bca0f41ca40a4caae9766734d154c9b7a4 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 23:05:31 -0500 Subject: [PATCH 385/617] deprecation: remove lpc11u35_wizwiki_w7500_eco_if project --- projects.yaml | 4 --- records/board/wizwiki_w7500_eco.yaml | 7 ---- source/board/wizwiki_w7500_eco.c | 49 ---------------------------- test/info.py | 2 -- 4 files changed, 62 deletions(-) delete mode 100644 records/board/wizwiki_w7500_eco.yaml delete mode 100644 source/board/wizwiki_w7500_eco.c diff --git a/projects.yaml b/projects.yaml index 8c1e5aa61..52d9a80a1 100644 --- a/projects.yaml +++ b/projects.yaml @@ -438,10 +438,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/tiny.yaml - lpc11u35_wizwiki_w7500_eco_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/wizwiki_w7500_eco.yaml lpc11u35_wizwiki_w7500_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/wizwiki_w7500_eco.yaml b/records/board/wizwiki_w7500_eco.yaml deleted file mode 100644 index 29647b177..000000000 --- a/records/board/wizwiki_w7500_eco.yaml +++ /dev/null @@ -1,7 +0,0 @@ -common: - sources: - board: - - source/board/wizwiki_w7500_eco.c - family: - - source/family/wiznet/w7500/target.c - - source/family/wiznet/target_reset_wiznet.c diff --git a/source/board/wizwiki_w7500_eco.c b/source/board/wizwiki_w7500_eco.c deleted file mode 100644 index b65a9e066..000000000 --- a/source/board/wizwiki_w7500_eco.c +++ /dev/null @@ -1,49 +0,0 @@ -/** - * @file wizwiki_w7500_eco.c - * @brief board ID for the WIZnet WIZwiki-W7500ECO board - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "cmsis_os2.h" -#include "target_family.h" -#include "target_board.h" -#include "swd_host.h" - -static uint8_t target_set_state_by_board(target_state_t state) -{ - if( state == RESET_PROGRAM ) - { - do - { - swd_set_target_reset(1); - osDelay(2); - - swd_set_target_reset(0); - osDelay(2); - } while(!swd_init_debug()); - } - return 1; -} - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "2202", - .family_id = kWiznet_W7500_FamilyID, - .target_set_state = target_set_state_by_board, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index cd4046dad..e04d5726c 100644 --- a/test/info.py +++ b/test/info.py @@ -85,7 +85,6 @@ ('lpc11u35_gr_lychee_if', None, 0x0000, "bin" ), ('lpc11u35_nz32_sc151_if', False, 0x0000, "bin" ), ('lpc11u35_wizwiki_w7500_if', False, 0x0000, "bin" ), - ('lpc11u35_wizwiki_w7500_eco_if', False, 0x0000, "bin" ), ('lpc11u35_wizwiki_w7500p_if', False, 0x0000, "bin" ), ("sam3u2c_ublox_evk_nina_b1_if", True, 0x5000, "bin" ), ("lpc11u35_rtl8195am_if", False, 0x0000, "bin" ), @@ -201,7 +200,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x1310, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_iot_m263a_if', 'm48ssidae_bl', None ), ( 0x1312, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_m2354_if', 'm48ssidae_bl', None ), ( 0x2201, VENDOR_TO_FAMILY('Wiznet', 1), 'lpc11u35_wizwiki_w7500_if', None, 'WIZwiki-W7500' ), - ( 0x2202, VENDOR_TO_FAMILY('Wiznet', 1), 'lpc11u35_wizwiki_w7500_eco_if', None, 'WIZwiki-W7500ECO' ), ( 0x2203, VENDOR_TO_FAMILY('Wiznet', 1), 'lpc11u35_wizwiki_w7500p_if', None, 'WIZwiki-W7500P' ), ( 0x2600, VENDOR_TO_FAMILY('Nordic', 2), 'k20dx_ep_agora_if', None, None ), ( 0x2601, VENDOR_TO_FAMILY('NXP', 0), 'k20dx_ep_kairos_if', None, None ), From 77357bfa87d3c7acb6dcb3137225de75c000f5a7 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 23:06:37 -0500 Subject: [PATCH 386/617] deprecation: remove lpc11u35_wizwiki_w7500_if project --- projects.yaml | 4 --- records/board/wizwiki_w7500.yaml | 7 ----- source/board/wizwiki_w7500.c | 49 -------------------------------- test/info.py | 2 -- 4 files changed, 62 deletions(-) delete mode 100644 records/board/wizwiki_w7500.yaml delete mode 100644 source/board/wizwiki_w7500.c diff --git a/projects.yaml b/projects.yaml index 52d9a80a1..76b36b842 100644 --- a/projects.yaml +++ b/projects.yaml @@ -438,10 +438,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/tiny.yaml - lpc11u35_wizwiki_w7500_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/wizwiki_w7500.yaml lpc11u35_wizwiki_w7500p_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/wizwiki_w7500.yaml b/records/board/wizwiki_w7500.yaml deleted file mode 100644 index a7e9a5249..000000000 --- a/records/board/wizwiki_w7500.yaml +++ /dev/null @@ -1,7 +0,0 @@ -common: - sources: - board: - - source/board/wizwiki_w7500.c - family: - - source/family/wiznet/w7500/target.c - - source/family/wiznet/target_reset_wiznet.c diff --git a/source/board/wizwiki_w7500.c b/source/board/wizwiki_w7500.c deleted file mode 100644 index 92bccabe1..000000000 --- a/source/board/wizwiki_w7500.c +++ /dev/null @@ -1,49 +0,0 @@ -/** - * @file wizwiki_w7500.c - * @brief board ID for the WIZnet WIZwiki-W7500 board - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "cmsis_os2.h" -#include "target_family.h" -#include "target_board.h" -#include "swd_host.h" - -static uint8_t target_set_state_by_board(target_state_t state) -{ - if( state == RESET_PROGRAM ) - { - do - { - swd_set_target_reset(1); - osDelay(2); - - swd_set_target_reset(0); - osDelay(2); - } while(!swd_init_debug()); - } - return 1; -} - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "2201", - .family_id = kWiznet_W7500_FamilyID, - .target_set_state = target_set_state_by_board, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index e04d5726c..7d1253665 100644 --- a/test/info.py +++ b/test/info.py @@ -84,7 +84,6 @@ ('lpc11u35_gr_peach_if', None, 0x0000, "bin" ), ('lpc11u35_gr_lychee_if', None, 0x0000, "bin" ), ('lpc11u35_nz32_sc151_if', False, 0x0000, "bin" ), - ('lpc11u35_wizwiki_w7500_if', False, 0x0000, "bin" ), ('lpc11u35_wizwiki_w7500p_if', False, 0x0000, "bin" ), ("sam3u2c_ublox_evk_nina_b1_if", True, 0x5000, "bin" ), ("lpc11u35_rtl8195am_if", False, 0x0000, "bin" ), @@ -199,7 +198,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x1309, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_m252kg_if', 'm48ssidae_bl', None ), ( 0x1310, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_iot_m263a_if', 'm48ssidae_bl', None ), ( 0x1312, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_m2354_if', 'm48ssidae_bl', None ), - ( 0x2201, VENDOR_TO_FAMILY('Wiznet', 1), 'lpc11u35_wizwiki_w7500_if', None, 'WIZwiki-W7500' ), ( 0x2203, VENDOR_TO_FAMILY('Wiznet', 1), 'lpc11u35_wizwiki_w7500p_if', None, 'WIZwiki-W7500P' ), ( 0x2600, VENDOR_TO_FAMILY('Nordic', 2), 'k20dx_ep_agora_if', None, None ), ( 0x2601, VENDOR_TO_FAMILY('NXP', 0), 'k20dx_ep_kairos_if', None, None ), From 8c305ad31bfcedf153edf7ab1328105e6b889a7b Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 23:07:44 -0500 Subject: [PATCH 387/617] deprecation: remove lpc11u35_wizwiki_w7500p_if project --- projects.yaml | 4 --- records/board/wizwiki_w7500p.yaml | 7 ----- source/board/wizwiki_w7500p.c | 49 ------------------------------- test/info.py | 2 -- 4 files changed, 62 deletions(-) delete mode 100644 records/board/wizwiki_w7500p.yaml delete mode 100644 source/board/wizwiki_w7500p.c diff --git a/projects.yaml b/projects.yaml index 76b36b842..119a16d7f 100644 --- a/projects.yaml +++ b/projects.yaml @@ -438,10 +438,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/tiny.yaml - lpc11u35_wizwiki_w7500p_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/wizwiki_w7500p.yaml lpc4322_hani_iot_if: - *module_if - *module_hic_lpc4322 diff --git a/records/board/wizwiki_w7500p.yaml b/records/board/wizwiki_w7500p.yaml deleted file mode 100644 index 15f03acff..000000000 --- a/records/board/wizwiki_w7500p.yaml +++ /dev/null @@ -1,7 +0,0 @@ -common: - sources: - board: - - source/board/wizwiki_w7500p.c - family: - - source/family/wiznet/w7500/target.c - - source/family/wiznet/target_reset_wiznet.c diff --git a/source/board/wizwiki_w7500p.c b/source/board/wizwiki_w7500p.c deleted file mode 100644 index 709acc28b..000000000 --- a/source/board/wizwiki_w7500p.c +++ /dev/null @@ -1,49 +0,0 @@ -/** - * @file wizwiki_w7500p.c - * @brief board ID for the WIZnet WIZwiki-W7500P board - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "cmsis_os2.h" -#include "target_family.h" -#include "target_board.h" -#include "swd_host.h" - -static uint8_t target_set_state_by_board(target_state_t state) -{ - if( state == RESET_PROGRAM ) - { - do - { - swd_set_target_reset(1); - osDelay(2); - - swd_set_target_reset(0); - osDelay(2); - } while(!swd_init_debug()); - } - return 1; -} - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "2203", - .family_id = kWiznet_W7500_FamilyID, - .target_set_state = target_set_state_by_board, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index 7d1253665..018c65119 100644 --- a/test/info.py +++ b/test/info.py @@ -84,7 +84,6 @@ ('lpc11u35_gr_peach_if', None, 0x0000, "bin" ), ('lpc11u35_gr_lychee_if', None, 0x0000, "bin" ), ('lpc11u35_nz32_sc151_if', False, 0x0000, "bin" ), - ('lpc11u35_wizwiki_w7500p_if', False, 0x0000, "bin" ), ("sam3u2c_ublox_evk_nina_b1_if", True, 0x5000, "bin" ), ("lpc11u35_rtl8195am_if", False, 0x0000, "bin" ), ("lpc11u35_96b_nitrogen_if", False, 0x0000, "bin" ), @@ -198,7 +197,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x1309, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_m252kg_if', 'm48ssidae_bl', None ), ( 0x1310, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_iot_m263a_if', 'm48ssidae_bl', None ), ( 0x1312, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_m2354_if', 'm48ssidae_bl', None ), - ( 0x2203, VENDOR_TO_FAMILY('Wiznet', 1), 'lpc11u35_wizwiki_w7500p_if', None, 'WIZwiki-W7500P' ), ( 0x2600, VENDOR_TO_FAMILY('Nordic', 2), 'k20dx_ep_agora_if', None, None ), ( 0x2601, VENDOR_TO_FAMILY('NXP', 0), 'k20dx_ep_kairos_if', None, None ), ( 0x4600, VENDOR_TO_FAMILY('Realtek', 1), 'lpc11u35_rtl8195am_if', None, 'REALTEK-RTL8195AM' ), From 5f880c2823dc10d7383b5d8e1932d4e94db98e0d Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 23:11:41 -0500 Subject: [PATCH 388/617] deprecation: remove unused wiz7500 target --- source/family/wiznet/w7500/flash_blob.c | 68 ------------------------- source/family/wiznet/w7500/target.c | 38 -------------- 2 files changed, 106 deletions(-) delete mode 100644 source/family/wiznet/w7500/flash_blob.c delete mode 100644 source/family/wiznet/w7500/target.c diff --git a/source/family/wiznet/w7500/flash_blob.c b/source/family/wiznet/w7500/flash_blob.c deleted file mode 100644 index 69c0e385e..000000000 --- a/source/family/wiznet/w7500/flash_blob.c +++ /dev/null @@ -1,68 +0,0 @@ -/** - * @file flash_blob.c - * @brief Flash algorithm for the W7500 - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "flash_blob.h" -static const uint32_t w7500_flash_prog_blob[] = { - 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, - 0x4d27b430, 0x606c2400, 0x1e644d26, 0x4c26602c, 0x086d6925, 0x6125006d, 0x46a44c24, 0x4760bc30, - 0x47702000, 0x47702000, 0x2014b570, 0x21004c1c, 0x4d1c6061, 0x602c1e4c, 0x69224c1b, 0x006d0855, - 0x460b6125, 0x461a4c19, 0x200047a0, 0xb570bd70, 0x49132512, 0x604a2200, 0x17494b12, 0x4c126019, - 0x08496921, 0x61210049, 0x4c104601, 0x46284613, 0x200047a0, 0xb570bd70, 0x4b092422, 0x605d2500, - 0x175b4d08, 0x4d08602b, 0x085e692b, 0x612e0076, 0x4601460b, 0x4c054620, 0x200047a0, 0x0000bd70, - 0xe000ed00, 0xe000e180, 0xe000e000, 0x1fff1001, 0x00000000, -}; - -/** -* List of start and size for each size of flash sector -* The size will apply to all sectors between the listed address and the next address -* in the list. -* The last pair in the list will have sectors starting at that address and ending -* at address start + size. -*/ -static const sector_info_t sectors_info[] = { - {0, 256}, -}; - -static const program_target_t flash = { - 0x20000041, // Init - 0x20000045, // UnInit - 0x20000049, // EraseChip - 0x2000006F, // EraseSector - 0x20000097, // ProgramPage - 0x0, // Verify - - // BKPT : start of blob + 1 - // RSB : blob start + header + rw data offset - // RSP : stack pointer - { - 0x20000000 + 0x00000001, - 0x20000000 + 0x00000020 + 0x000000b0, - 0x20000800 - }, - - 0x20000000 + 0x00000A00, // mem buffer location - 0x20000000, // location to write prog_blob in target RAM - sizeof(w7500_flash_prog_blob), // prog_blob size - w7500_flash_prog_blob, // address of prog_blob - - // Do not modify. program_buffer_size of W7500 must be set to 0x00000100 - 0x00000100 // ram_to_flash_bytes_to_be_written -}; diff --git a/source/family/wiznet/w7500/target.c b/source/family/wiznet/w7500/target.c deleted file mode 100644 index c0ab81aeb..000000000 --- a/source/family/wiznet/w7500/target.c +++ /dev/null @@ -1,38 +0,0 @@ -/** - * @file target.c - * @brief Target information for the W7500 - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_config.h" - -// The file flash_blob.c must only be included in target.c -#include "flash_blob.c" - -// target information -target_cfg_t target_device = { - .version = kTargetConfigVersion, - .sectors_info = sectors_info, - .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), - .flash_regions[0].start = 0x00000000, - .flash_regions[0].end = 0x00000000 + KB(128), - .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, - .ram_regions[0].start = 0x20000000, - .ram_regions[0].end = 0x20004000, -}; From 64c624a75d6f3b6db444b8339a0853b36f7fc848 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 23:12:43 -0500 Subject: [PATCH 389/617] deprecation: remove g_wiznet_family reset family --- records/family/all_family.yaml | 1 - source/family/wiznet/target_reset_wiznet.c | 55 ---------------------- source/target/target_family.c | 2 - source/target/target_family.h | 2 - 4 files changed, 60 deletions(-) delete mode 100644 source/family/wiznet/target_reset_wiznet.c diff --git a/records/family/all_family.yaml b/records/family/all_family.yaml index e4527d8ed..2af952c67 100644 --- a/records/family/all_family.yaml +++ b/records/family/all_family.yaml @@ -9,5 +9,4 @@ common: - source/family/nordic/target_reset_nrf52.c - source/family/realtek/target_reset_realtek_rtl8195am.c - source/family/toshiba/target_reset_tz.c - - source/family/wiznet/target_reset_wiznet.c - source/family/renesas/target_reset_rza.c diff --git a/source/family/wiznet/target_reset_wiznet.c b/source/family/wiznet/target_reset_wiznet.c deleted file mode 100644 index c2cbebe67..000000000 --- a/source/family/wiznet/target_reset_wiznet.c +++ /dev/null @@ -1,55 +0,0 @@ -/** - * @file target_reset.c - * @brief Target reset for the W7500 - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "cmsis_os2.h" -#include "swd_host.h" -#include "target_family.h" -#include "target_board.h" - -static uint8_t target_set_state_wiznet(target_state_t state) { - uint8_t status; - - if( state == RESET_RUN ) - { - do - { - swd_set_target_reset(1); - osDelay(2); - swd_set_target_reset(0); - osDelay(2); - } while(!swd_init_debug()); - - swd_off(); - status = 1; - } - else - { - status = swd_set_target_state_sw(state); - } - - return status; -} - - -const target_family_descriptor_t g_wiznet_family = { - .family_id = kWiznet_W7500_FamilyID, - .target_set_state = target_set_state_wiznet, -}; diff --git a/source/target/target_family.c b/source/target/target_family.c index 6f3b55907..b1066b590 100644 --- a/source/target/target_family.c +++ b/source/target/target_family.c @@ -53,7 +53,6 @@ __WEAK const target_family_descriptor_t g_nxp_lpc55xx_series = {0}; __WEAK const target_family_descriptor_t g_nordic_nrf51 = {0}; __WEAK const target_family_descriptor_t g_nordic_nrf52 = {0}; __WEAK const target_family_descriptor_t g_realtek_rtl8195am = {0}; -__WEAK const target_family_descriptor_t g_wiznet_family = {0}; __WEAK const target_family_descriptor_t g_renesas_family = {0}; __WEAK const target_family_descriptor_t g_toshiba_tz_family = {0}; __WEAK const target_family_descriptor_t g_ambiq_ama3b1kk = {0}; @@ -86,7 +85,6 @@ const target_family_descriptor_t *g_families[] = { &g_nordic_nrf51, &g_nordic_nrf52, &g_realtek_rtl8195am, - &g_wiznet_family, &g_renesas_family, &g_toshiba_tz_family, &g_ambiq_ama3b1kk, diff --git a/source/target/target_family.h b/source/target/target_family.h index 20141106d..0f31e7e9f 100644 --- a/source/target/target_family.h +++ b/source/target/target_family.h @@ -65,7 +65,6 @@ enum _vendor_ids { kNordic_VendorID = 54, kToshiba_VendorID = 92, kRenesas_VendorID = 117, - kWiznet_VendorID = 122, kRealtek_VendorID = 124, kAmbiq_VendorID = 120, }; @@ -103,7 +102,6 @@ typedef enum _family_id { kRealtek_Rtl8195am_FamilyID = CREATE_FAMILY_ID(kRealtek_VendorID, 1), kTI_Cc3220sf_FamilyID = CREATE_FAMILY_ID(kTI_VendorID, 1), kToshiba_Tz_FamilyID = CREATE_FAMILY_ID(kToshiba_VendorID, 1), - kWiznet_W7500_FamilyID = CREATE_FAMILY_ID(kWiznet_VendorID, 1), kRenesas_FamilyID = CREATE_FAMILY_ID(kRenesas_VendorID, 1), kAmbiq_ama3b1kk_FamilyID = CREATE_FAMILY_ID(kAmbiq_VendorID, 1), kMaxim_MAX3262X_FamilyID = CREATE_FAMILY_ID(kMaxim_VendorID, 1), From 27d3f58afc332717fbdfb9c8680d19f730543af1 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 23:13:43 -0500 Subject: [PATCH 390/617] deprecation: remove sam3u2c_ncs36510rf_if project --- projects.yaml | 4 ---- records/board/ncs36510rf.yaml | 6 ------ source/board/ncs36510rf.c | 32 -------------------------------- test/info.py | 2 -- 4 files changed, 44 deletions(-) delete mode 100644 records/board/ncs36510rf.yaml delete mode 100644 source/board/ncs36510rf.c diff --git a/projects.yaml b/projects.yaml index 119a16d7f..e11d73dcd 100644 --- a/projects.yaml +++ b/projects.yaml @@ -498,10 +498,6 @@ projects: - *module_if - *module_hic_sam3u2c - records/board/mkit_dk_dongle_nrf5x.yaml - sam3u2c_ncs36510rf_if: - - *module_if - - *module_hic_sam3u2c - - records/board/ncs36510rf.yaml sam3u2c_ublox_evk_nina_b1_if: - *module_if - *module_hic_sam3u2c diff --git a/records/board/ncs36510rf.yaml b/records/board/ncs36510rf.yaml deleted file mode 100644 index c8916a4a5..000000000 --- a/records/board/ncs36510rf.yaml +++ /dev/null @@ -1,6 +0,0 @@ -common: - sources: - board: - - source/board/ncs36510rf.c - family: - - source/family/onsemi/ncs36510/target.c diff --git a/source/board/ncs36510rf.c b/source/board/ncs36510rf.c deleted file mode 100644 index 2e4a407ce..000000000 --- a/source/board/ncs36510rf.c +++ /dev/null @@ -1,32 +0,0 @@ -/* CMSIS-DAP Interface Firmware - * Copyright (c) 2009-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "uart.h" -#include "target_board.h" -#include "target_family.h" - -static void prerun_board_config() -{ - uart_enable_flow_control(false); -} - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "1200", - .family_id = kStub_SWSysReset_FamilyID, - .prerun_board_config = prerun_board_config, - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index 018c65119..ccfc1aae7 100644 --- a/test/info.py +++ b/test/info.py @@ -72,7 +72,6 @@ ("lpc11u35_archlink_if", False, 0x0000, "bin" ), ("lpc11u35_tiny_if", False, 0x0000, "bin" ), ("lpc11u35_c027_if", False, 0x0000, "bin" ), - ("sam3u2c_ncs36510rf_if", False, 0x8000, "bin" ), ("kl26z_nina_b1_if", False, 0x8000, "bin" ), ("lpc11u35_lpc4088dm_if", False, 0x0000, "bin" ), ("lpc11u35_lpc4088qsb_if", False, 0x0000, "bin" ), @@ -188,7 +187,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x1102, VENDOR_TO_FAMILY('Nordic', 2), 'sam3u2c_mkit_dk_dongle_nrf5x_if', 'sam3u2c_bl', 'Nordic-nRF52840-DK' ), ( 0x1114, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_ssci1114_if', None, 'LPC1114FN28' ), ( 0x1120, VENDOR_TO_FAMILY('Nordic', 1), 'sam3u2c_mkit_dk_dongle_nrf5x_if', 'sam3u2c_bl', 'Nordic-nRF51-Dongle' ), - ( 0x1200, VENDOR_TO_FAMILY('Stub', 3), 'sam3u2c_ncs36510rf_if', 'sam3u2c_bl', None ), # TODO - Set to 'ncs36510' when non-zero flash addresses are supported ( 0x1234, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_c027_if', None, 'u-blox-C027' ), ( 0x1236, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_ublox_evk_odin_w2_if', 'stm32f103xb_bl', 'ublox-EVK-ODIN-W2' ), ( 0x1237, VENDOR_TO_FAMILY('Nordic', 2), 'sam3u2c_ublox_evk_nina_b1_if', 'sam3u2c_bl', 'U-BLOX-EVK-NINA-B1' ), From 5f4f96bcd7a661612a4dca2224728d5da8362349 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 23:14:19 -0500 Subject: [PATCH 391/617] deprecation: remove unused ncs36510 target --- source/family/onsemi/ncs36510/flash_blob.c | 83 ---------------------- source/family/onsemi/ncs36510/target.c | 33 --------- 2 files changed, 116 deletions(-) delete mode 100644 source/family/onsemi/ncs36510/flash_blob.c delete mode 100644 source/family/onsemi/ncs36510/target.c diff --git a/source/family/onsemi/ncs36510/flash_blob.c b/source/family/onsemi/ncs36510/flash_blob.c deleted file mode 100644 index 440402244..000000000 --- a/source/family/onsemi/ncs36510/flash_blob.c +++ /dev/null @@ -1,83 +0,0 @@ -/* Flash OS Routines (Automagically Generated) - * Copyright (c) 2009-2019 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -static const uint32_t ncs36510_flash_prog_blob[] = { - 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, - 0x4770ba40, 0x4770bac0, 0x4770ba40, 0x4770bac0, 0x49876842, 0x68016111, 0xf4116840, 0x49851f80, - 0x6181bf14, 0x47706141, 0x68406801, 0x1f80f411, 0x6801d004, 0x0f02f011, 0x4770d1fb, 0xf0116801, - 0xd1fb0f01, 0x68014770, 0xf4116840, 0x68411f80, 0xf041bf14, 0xf0410101, 0x60410102, 0x68014770, - 0xf4116840, 0x68411f80, 0xf021bf14, 0xf0210101, 0x60410102, 0x68434770, 0x611a4a6d, 0x68436802, - 0x1f80f412, 0xbf144a6b, 0x615a619a, 0x60d16842, 0x21016842, 0xe7c76091, 0xf4116801, 0x68411f80, - 0xf44fbf14, 0xf44f1281, 0x60ca5200, 0x49606842, 0x68016111, 0xf4116842, 0x495e1f80, 0x6191bf14, - 0x21026151, 0x60916842, 0x4770e7ae, 0x1e5b6808, 0xf810d305, 0xf802cb01, 0x1e5bcb01, 0x6008d2f9, - 0x47702001, 0x4604b510, 0x46116808, 0x5f00f5b0, 0x020af3c0, 0xb132d20b, 0x020af3c0, 0x6200f5c2, - 0xd205429a, 0xf5b3e00a, 0xd8076f00, 0xb13ae00b, 0x020af3c0, 0x6200f5c2, 0xd204429a, 0xbd102000, - 0x6f00f5b3, 0x6862d8fa, 0xc004f8d2, 0x0c40f04c, 0xc004f8c2, 0xc004f8d4, 0xf8cc4a3d, 0x68222010, - 0xc004f8d4, 0x1f80f412, 0xbf144a3a, 0x2018f8cc, 0x2014f8cc, 0xf000461a, 0x4620f8f7, 0xff64f7ff, - 0xbd102001, 0x4d32b530, 0x46844c32, 0xd2562906, 0xf001e8df, 0x421f0355, 0x68015334, 0x1f80f411, - 0xf44fbf14, 0xf44f1181, 0x68425100, 0x684160d1, 0x6801610d, 0x1f80f411, 0xbf146841, 0x614c618c, - 0x68422102, 0xf7ff6091, 0x4660ff3f, 0xff3cf7ff, 0x6811e035, 0x61156842, 0xf4126802, 0x68421f80, - 0x6194bf14, 0x68426154, 0x684260d1, 0x60912101, 0xff2af7ff, 0xf7ff4660, 0xe020ff27, 0x0000f8dc, - 0x1f80f410, 0x0004f8dc, 0xbf146841, 0x0101f041, 0x0102f041, 0xe0126041, 0x0000f8dc, 0x1f80f410, - 0x0004f8dc, 0xbf146841, 0x0101f021, 0x0102f021, 0x46606041, 0xff08f7ff, 0xf7ffe001, 0x2001ff05, - 0x69c1bd30, 0x0f01f011, 0x69c0bf18, 0x00004770, 0xbb781ae9, 0xb56d9099, 0xb5104838, 0xf4216901, - 0x61010100, 0xf0216901, 0x61014180, 0x49354834, 0xf04f6001, 0x211f20e0, 0x1180f8c0, 0x1280f8c0, - 0xf04f4931, 0x60086020, 0x22004830, 0x44782103, 0xff78f7ff, 0xbd102000, 0x47702000, 0x47702000, - 0xb510482b, 0xf7ff4478, 0x482aff07, 0xf7ff4478, 0x2000ff03, 0xb501bd10, 0xf5b09800, 0xbf3c5f00, - 0xbd082001, 0x5100f5a0, 0x2fa0f5b1, 0x4822d204, 0x2102466a, 0xe0084478, 0x1081f5a0, 0x2fa0f5b0, - 0x481ed205, 0x2102466a, 0xf7ff4478, 0x2000ff4b, 0xb507bd08, 0xf5b09800, 0xd3165f00, 0x5c00f5a0, - 0x2fa0f5bc, 0x4816d204, 0x4669460b, 0xe0084478, 0x1081f5a0, 0x2fa0f5b0, 0x4812d20a, 0x4669460b, - 0xf7ff4478, 0x2801feef, 0xb003d002, 0xbd002001, 0x2000b003, 0x2000bd00, 0x00004770, 0x4001b000, - 0x4001e000, 0x2082353f, 0xe000ed04, 0x00000106, 0x000000e4, 0x000000e8, 0x000000b4, 0x000000ac, - 0x0000007c, 0x00000074, 0x0301ea40, 0xd003079b, 0xc908e009, 0xc0081f12, 0xd2fa2a04, 0xf811e003, - 0xf8003b01, 0x1e523b01, 0x4770d2f9, 0x00000000, 0x40017000, 0x00000008, 0x00100000, 0x40017000, - 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000 -}; - -/** -* List of start and size for each size of flash sector -* The size will apply to all sectors between the listed address and the next address -* in the list. -* The last pair in the list will have sectors starting at that address and ending -* at address start + size. -*/ -static const sector_info_t sectors_info[] = { - {0x00002000, 0x800}, -}; - -static const program_target_t flash = { - 0x3fff4259, // Init - 0x3fff4299, // UnInit - 0x3fff42a1, // EraseChip - 0x3fff42b7, // EraseSector - 0x3fff42f3, // ProgramPage - 0x0, // Verify - - // BKPT : start of blob + 1 - // RSB : blob start + header + rw data offset - // RSP : stack pointer - { - 0x3fff4001, - 0x3fff43a4, - 0x3fff4800 - }, - - 0x3fff4000 + 0x00000A00, // mem buffer location - 0x3fff4000, // location to write prog_blob in target RAM - sizeof(ncs36510_flash_prog_blob), // prog_blob size - ncs36510_flash_prog_blob, // address of prog_blob - 0x00000200 // ram_to_flash_bytes_to_be_written -}; diff --git a/source/family/onsemi/ncs36510/target.c b/source/family/onsemi/ncs36510/target.c deleted file mode 100644 index 9cfe787b2..000000000 --- a/source/family/onsemi/ncs36510/target.c +++ /dev/null @@ -1,33 +0,0 @@ -/* CMSIS-DAP Interface Firmware - * Copyright (c) 2009-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_config.h" - -// The file flash_blob.c must only be included in target.c -#include "flash_blob.c" - -// target information -target_cfg_t target_device = { - .version = kTargetConfigVersion, - .sectors_info = sectors_info, - .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), - .flash_regions[0].start = 0x00002000, - .flash_regions[0].end = 0x00151FFF, - .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, - .ram_regions[0].start = 0x3FFF4000, - .ram_regions[0].end = 0x3FFFFFFF, -}; From dcbfa88ac03df2780845b318edeb07c9650a3eab Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 20 Oct 2021 23:18:02 -0500 Subject: [PATCH 392/617] deprecation: remove kl26z_nina_b1_if project --- projects.yaml | 4 ---- records/board/nina_b1.yaml | 11 ----------- source/board/nina_b1.c | 33 --------------------------------- test/info.py | 2 -- 4 files changed, 50 deletions(-) delete mode 100644 records/board/nina_b1.yaml delete mode 100644 source/board/nina_b1.c diff --git a/projects.yaml b/projects.yaml index e11d73dcd..f9d330648 100644 --- a/projects.yaml +++ b/projects.yaml @@ -311,10 +311,6 @@ projects: - *module_if - *module_hic_kl26z - records/board/microbit.yaml - kl26z_nina_b1_if: - - *module_if - - *module_hic_kl26z - - records/board/nina_b1.yaml kl27z_microbit_bl: - *module_bl - records/hic_hal/kl27z.yaml diff --git a/records/board/nina_b1.yaml b/records/board/nina_b1.yaml deleted file mode 100644 index 4bc825b2b..000000000 --- a/records/board/nina_b1.yaml +++ /dev/null @@ -1,11 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - includes: - - source/board/override_mkl26z_reset - sources: - board: - - source/board/nina_b1.c - family: - - source/family/nordic/nrf52/target.c - - source/family/nordic/target_reset_nrf51.c diff --git a/source/board/nina_b1.c b/source/board/nina_b1.c deleted file mode 100644 index b29c2915a..000000000 --- a/source/board/nina_b1.c +++ /dev/null @@ -1,33 +0,0 @@ -/** - * @file nina_b1.c - * @brief board ID for the u-blox NINA-B1 EVA maker board - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_board.h" -#include "target_family.h" - -extern target_cfg_t target_device_nrf52; - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "1238", - .family_id = kNordic_Nrf51_FamilyID, - .daplink_target_url = "https://os.mbed.com/platforms/VBLUNO51/", - .target_cfg = &target_device_nrf52, -}; diff --git a/test/info.py b/test/info.py index ccfc1aae7..eea29d73b 100644 --- a/test/info.py +++ b/test/info.py @@ -72,7 +72,6 @@ ("lpc11u35_archlink_if", False, 0x0000, "bin" ), ("lpc11u35_tiny_if", False, 0x0000, "bin" ), ("lpc11u35_c027_if", False, 0x0000, "bin" ), - ("kl26z_nina_b1_if", False, 0x8000, "bin" ), ("lpc11u35_lpc4088dm_if", False, 0x0000, "bin" ), ("lpc11u35_lpc4088qsb_if", False, 0x0000, "bin" ), ('lpc11u35_ssci_chibi_if', False, 0x0000, "bin" ), @@ -190,7 +189,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x1234, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_c027_if', None, 'u-blox-C027' ), ( 0x1236, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_ublox_evk_odin_w2_if', 'stm32f103xb_bl', 'ublox-EVK-ODIN-W2' ), ( 0x1237, VENDOR_TO_FAMILY('Nordic', 2), 'sam3u2c_ublox_evk_nina_b1_if', 'sam3u2c_bl', 'U-BLOX-EVK-NINA-B1' ), - ( 0x1238, VENDOR_TO_FAMILY('Nordic', 1), 'kl26z_nina_b1_if', 'kl26z_bl', 'u-blox-NINA-B1' ), ( 0x1304, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_pfm_m487km_if', 'm48ssidae_bl', None ), ( 0x1309, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_m252kg_if', 'm48ssidae_bl', None ), ( 0x1310, VENDOR_TO_FAMILY('Stub', 3), 'm48ssidae_numaker_iot_m263a_if', 'm48ssidae_bl', None ), From 0dcc7c4c1e77eaff53fc8cb2571938bd701c9a8b Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 21 Oct 2021 00:05:49 -0500 Subject: [PATCH 393/617] deprecation: remove lpc11u35_ro359b_if project --- projects.yaml | 4 ---- records/board/ro359b.yaml | 6 ------ source/board/ro359b.c | 31 ------------------------------- test/info.py | 3 --- 4 files changed, 44 deletions(-) delete mode 100644 records/board/ro359b.yaml delete mode 100644 source/board/ro359b.c diff --git a/projects.yaml b/projects.yaml index f9d330648..ca346c8ff 100644 --- a/projects.yaml +++ b/projects.yaml @@ -406,10 +406,6 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/nz32_sc151.yaml - lpc11u35_ro359b_if: - - *module_if - - *module_hic_lpc11u35 - - records/board/ro359b.yaml lpc11u35_rtl8195am_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/ro359b.yaml b/records/board/ro359b.yaml deleted file mode 100644 index 41bb9c686..000000000 --- a/records/board/ro359b.yaml +++ /dev/null @@ -1,6 +0,0 @@ -common: - sources: - board: - - source/board/ro359b.c - family: - - source/family/freescale/k64f/target.c diff --git a/source/board/ro359b.c b/source/board/ro359b.c deleted file mode 100644 index 95b19c595..000000000 --- a/source/board/ro359b.c +++ /dev/null @@ -1,31 +0,0 @@ -/** - * @file ro359b.c - * @brief board ID for the RO359B board - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_board.h" -#include "target_family.h" - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .board_id = "1022", - .family_id = kStub_HWReset_FamilyID, - .daplink_drive_name = "MBED ", - .target_cfg = &target_device, -}; diff --git a/test/info.py b/test/info.py index eea29d73b..a831e5d4b 100644 --- a/test/info.py +++ b/test/info.py @@ -68,7 +68,6 @@ ("lpc11u35_hrm1017_if", False, 0x0000, "bin" ), ("lpc11u35_sscity_if", False, 0x0000, "bin" ), ("lpc11u35_ssci824_if", False, 0x0000, "bin" ), - ("lpc11u35_ro359b_if", False, 0x0000, "bin" ), ("lpc11u35_archlink_if", False, 0x0000, "bin" ), ("lpc11u35_tiny_if", False, 0x0000, "bin" ), ("lpc11u35_c027_if", False, 0x0000, "bin" ), @@ -174,7 +173,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x1018, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_ssci824_if', None, 'Switch-Science-mbed-LPC824' ), ( 0x1019, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_sscity_if', None, 'Switch-Science-mbed-TY51822r3' ), ( 0x1021, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_ssci_chibi_if', None, None ), # TODO - set target to 'SSCI-MBIT' when mbed-os supports this - ( 0x1022, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_ro359b_if', None, None ), ( 0x1050, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_lpc812xpresso_if', None, 'NXP-LPC800-MAX' ), ( 0x1054, VENDOR_TO_FAMILY('Stub', 1), 'lpc4322_lpc54114xpresso_if', 'lpc4322_bl', 'LPCXpresso54114' ), ( 0x1056, VENDOR_TO_FAMILY('Stub', 1), 'lpc4322_lpc54608xpresso_if', 'lpc4322_bl', 'LPCXpresso54608' ), @@ -265,7 +263,6 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y 0x0261, # FRDM-KL27Z 0x0262, # FRDM-KL43Z 0x0218, # FRDM-KL82Z - 0x1022, # RO359B (K24F) 0x0201, # KW41Z ]) From 27037b1e1661a92c39e13d40a875a425243fb70e Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 22 Oct 2021 21:37:02 -0500 Subject: [PATCH 394/617] github_actions: enable build on pull-requests to develop branch --- .github/workflows/linux.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.github/workflows/linux.yml b/.github/workflows/linux.yml index 555b41fec..cb6b5b728 100644 --- a/.github/workflows/linux.yml +++ b/.github/workflows/linux.yml @@ -3,6 +3,9 @@ on: push: branches: - develop + pull_request: + branches: + - develop workflow_dispatch: jobs: From f5fb4b96ba930fdb529eacef7e22c4ed06e96461 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 23 Oct 2021 00:24:27 -0500 Subject: [PATCH 395/617] doc: move build instructions from README.md to docs/DEVELOPERS-GUIDE.md --- README.md | 111 ++++------------------------ docs/DEVELOPERS-GUIDE.md | 154 +++++++++++++++++---------------------- 2 files changed, 81 insertions(+), 184 deletions(-) diff --git a/README.md b/README.md index cd828ce67..52c756c66 100644 --- a/README.md +++ b/README.md @@ -1,102 +1,15 @@ -# Warning: Development branch - -This is is a development branch: -- It adds support for the GCC (`gcc_arm`) and ARMC6 (`armclang`) compilers, ARMC5 (`armcc`) will be deprecated. -- It focuses on `progen` support using `make` and `cmake`. - -## Setup - -DAPLink sources are compiled using `progen` (from [project-generator](https://github.com/project-generator/project_generator)) which can be run on Linux, MacOS and Windows. - -Install the necessary tools listed below. Skip any step where a compatible tool already exists. - -* Install [Python 3](https://www.python.org/downloads/) . Add to PATH. -* Install [Git](https://git-scm.com/downloads) . Add to PATH. -* Install a compiler: - * [GNU Arm Embedded Toolchain](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads) . This compiler will be identified as `gcc_arm`. - * [Arm Compiler 6](https://developer.arm.com/tools-and-software/embedded/arm-compiler) . This compiler will be identified as `armclang`. Only supported on Linux and Windows. - * [Keil MDK](https://developer.arm.com/tools-and-software/embedded/keil-mdk) or [Arm Compiler 5](https://developer.arm.com/tools-and-software/embedded/arm-compiler/downloads/legacy-compilers#arm-compiler-5). This compiler will be identified as `armcc`. Only supported on Linux and Windows. -* Install `make` (tested with [GNU Make](https://www.gnu.org/software/make)). [CMake](https://cmake.org) can alternatively be used in conjunction with different implementations of `make` as well as [ninja](https://ninja-build.org). -* Install virtualenv in your global Python installation eg: `pip install virtualenv`. - -**Step 1.** Initial setup. - -Get the sources and create a virtual environment - -``` -$ git clone https://github.com/ARMmbed/DAPLink -$ cd DAPLink -$ git checkout develop -$ virtualenv venv -``` - -## Activate virtual environment -**Step 2.** Activate the virtual environment and update requirements. This is necessary when you open a new shell. **This should be done every time you pull new changes** - -``` -$ venv/Scripts/activate (For Linux) -$ venv/Scripts/activate.bat (For Windows) -(venv) $ pip install -r requirements.txt -``` - -## Build -**This should be done every time you pull new changes** -You can use the `progen` command-line tool from project-generator or the `tools/progen_compile.py` wrapper tool. +[![DAPLink](/docs/images/daplink-website-logo-link.png)](https://daplink.io/) -**Step 4.1.** Using `progen_compile.py` +[![Linux Build (develop)](https://github.com/ARMmbed/DAPLink/actions/workflows/linux.yml/badge.svg?branch=develop)](https://github.com/ARMmbed/DAPLink/actions/workflows/linux.yml) -``` -(venv) $ python tools/progen_compile.py [-t ] [--clean] [-v] [--parallel] [ [ ...]] -``` - -* `-t `: choose the toolchain to build. The default is `make_gcc_arm`. Other options tested are `make_gcc_arm`, `make_armclang`, `make_armcc`, `cmake_gcc_arm`, `cmake_armclang`, `cmake_armcc`. -* `--clean`: will clear existing compilation products and force recompilation of all files. -* `-v`: will make compilation process more verbose (typically listing all commands with their arguments) -* `--parallel`: enable parallel compilation within a project (projects are compiled sequentially). -* ``: target project to compile (e.g. `stm32f103xb_bl`, `lpc11u35_if`), if none is specified all (140 to 150) projects will be compiled. - -**Step 4.2.** Using `progen` with `make` - -The following command combines generation and compilation: - -``` -(venv) $ progen generate -t make_gcc_arm -p -b -``` - -Alternatively one can separate those task: -``` -(venv) $ progen generate -t make_gcc_arm -p -(venv) $ make -C projectfiles/make_gcc_arm/ [] [VERBOSE=1] -``` -Where: -* ``: target project to compile (e.g. `stm32f103xb_bl`, `lpc11u35_if`). -* ``: build target, can be `all`, `clean` or `help`. -* `VERBOSE=1`: display additional compilation information. - -**Step 4.3.** Using `progen` with `cmake` - -The following command combines generation and compilation: - -``` -(venv) $ progen generate -t cmake_gcc_arm -o generator= -p -b -``` -* ``: use `CMake` generators among the following options: - * `make` (`Unix Makefiles`) - * `mingw-make` (`MinGW Makefiles`) - * `msys-make` (`MSYS Makefiles`, untested) - * `ninja` (`Ninja`) - * `nmake` (`NMake Makefiles`, untested) -* ``: target project to compile (e.g. `stm32f103xb_bl`, `lpc11u35_if`). - -# End of warning +# Warning: Development branch -[![DAPLink](/docs/images/daplink-website-logo-link.png)](https://armmbed.github.io/DAPLink/) +This is is a development branch of DAPLink: +- It adds support for the GCC (`gcc_arm`) and ARMC6 (`armclang`) compilers. ARMC5 (`armcc`) will be deprecated. +- It focuses on `progen` support using `make` and `cmake`. -**Note:** The master branch requires an Arm Compiler 5 or Keil MDK license to build. See the -[develop](https://github.com/ARMmbed/DAPLink/tree/develop) branch for gcc and Arm -Compiler 6 support. As soon as testing is complete, gcc will become the default compiler and AC5 support will be -dropped. +**Note:** The main branch of DAPLink requires an Arm Compiler 5 or Keil MDK license to build. ---- @@ -114,12 +27,18 @@ For more detailed usability information [see the users guide.](docs/USERS-GUIDE. ## Compatibility There are many ARM microcontroller-based Hardware Interface Circuits (HICs) that DAPLink interface firmware runs on. These can be found as standalone boards (debugger) or as part of a development kit. Some branded circuits that are known to be IO compatible are: -* [NXP OpenSDA based on K20, K22 and KL26](http://www.nxp.com/products/software-and-tools/run-time-software/kinetis-software-and-tools/ides-for-kinetis-mcus/opensda-serial-and-debug-adapter:OPENSDA) + +* [Maxim Integrated MAX32625PICO based on MAX32625](https://www.maximintegrated.com/en/products/microcontrollers/MAX32625PICO.html) +* Nuvoton Nu-Link2-Me based on M48SSIDAE * [NXP LPC-Link2 based on LPC11U35 or LPC4322](https://www.nxp.com/support/developer-resources/hardware-development-tools/lpcxpresso-boards:LPCXPRESSO-BOARDS) +* [NXP MCU-LINK on LPC55xx](https://www.nxp.com/design/microcontrollers-developer-resources/mcu-link-debug-probe:MCU-LINK) +* [NXP OpenSDA based on K20, K22, KL26Z and KL27Z](http://www.nxp.com/products/software-and-tools/run-time-software/kinetis-software-and-tools/ides-for-kinetis-mcus/opensda-serial-and-debug-adapter:OPENSDA) * [Segger J-Link OB based on Atmel SAM3U](https://www.segger.com/products/debug-probes/j-link/models/j-link-ob/) +* [STMicroelectronics ST-LINK/V2 (on NUCLEO boards) based on STM32F103CB](https://www.st.com/en/evaluation-tools/stm32-nucleo-boards.html) + ## Releases -There are many board builds (board = HIC + target combination) created from this repository. Quarterly releases will contain new features and bugfixes. Standalone bugfixes are released once reported, verified and fixed. Both quarterly and bugfix releases will result in the build number being incremented. Many development kits and products ship with DAPLink interface firmware or are capable of running DAPLink firmware. **[The current release builds and instructions for updating DAPLink interface firmware is hosted on the DAPLink release site.](https://armmbed.github.io/DAPLink/)** Release notes and previous release builds can be found under GitHub releases. +There are many board builds (board = HIC + target combination) created from this repository. Quarterly releases will contain new features and bugfixes. Standalone bugfixes are released once reported, verified and fixed. Both quarterly and bugfix releases will result in the build number being incremented. Many development kits and products ship with DAPLink interface firmware or are capable of running DAPLink firmware. **[The current release builds and instructions for updating DAPLink interface firmware is hosted on the DAPLink release site.](https://daplink.io/)** Release notes and previous release builds can be found under GitHub releases. ## Contribute diff --git a/docs/DEVELOPERS-GUIDE.md b/docs/DEVELOPERS-GUIDE.md index 64784fb1a..ee8f4bce9 100644 --- a/docs/DEVELOPERS-GUIDE.md +++ b/docs/DEVELOPERS-GUIDE.md @@ -1,19 +1,20 @@ # DAPLink Developers Guide ## Setup -DAPLink sources can be compiled using Keil MDK-ARM or mbed cli tool with arm compiler, which could be run both on Linux and Windows. See [here](AUTOMATED_TESTS.md) for test instructions on both OS and Mac. + +DAPLink sources are compiled using `progen` (from [project-generator](https://github.com/project-generator/project_generator)) which can be run on Linux, MacOS and Windows. Install the necessary tools listed below. Skip any step where a compatible tool already exists. -* Install [Python 2, 2.7.11 or above](https://www.python.org/downloads/) . Add to PATH. +* Install [Python 3](https://www.python.org/downloads/) . Add to PATH. * Install [Git](https://git-scm.com/downloads) . Add to PATH. -* Install [Keil MDK-ARM](https://www.keil.com/download/product/), preferably version 5. Set environment variable "UV4" to - the absolute path of the UV4 executable if you don't install to the default location. Note that "UV4" is what's used for - both MDK versions 4 and 5. This step can be skipped if you plan to use mbed cli, but you still need Arm Compiler 5, and - MDK is required to debug. +* Install a compiler: + * [GNU Arm Embedded Toolchain](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads) . This compiler will be identified as `gcc_arm`. + * [Arm Compiler 6](https://developer.arm.com/tools-and-software/embedded/arm-compiler) . This compiler will be identified as `armclang`. Only supported on Linux and Windows. + * [Keil MDK](https://developer.arm.com/tools-and-software/embedded/keil-mdk) or [Arm Compiler 5](https://developer.arm.com/tools-and-software/embedded/arm-compiler/downloads/legacy-compilers#arm-compiler-5). This compiler will be identified as `armcc`. Only supported on Linux and Windows. +* Install `make` (tested with [GNU Make](https://www.gnu.org/software/make)). [CMake](https://cmake.org) can alternatively be used in conjunction with different implementations of `make` as well as [ninja](https://ninja-build.org). * Install virtualenv in your global Python installation eg: `pip install virtualenv`. - **Step 1.** Initial setup. Get the sources and create a virtual environment @@ -25,101 +26,83 @@ $ pip install virtualenv $ virtualenv venv ``` -**Step 2.** One-time mbed-cli setup. - -This step is only required once if you are planning to use the mbed-cli build method. - -First run step 3 below to activate the virtual environment. Then execute these commands. -``` -$ mbed deploy -$ mbed config root . -$ mbed config ARM_PATH -``` - - ## Activate virtual environment -**Step 3.** Activate the virtual environment and update requirements. This is necessary when you open a new shell. **This should be done every time you pull new changes** +**Step 2.** Activate the virtual environment and update requirements. This is necessary when you open a new shell. **This should be done every time you pull new changes** ``` $ venv/Scripts/activate (For Linux) $ venv/Scripts/activate.bat (For Windows) -$ pip install -r requirements.txt +(venv) $ pip install -r requirements.txt ``` - ## Build **This should be done every time you pull new changes** -There are two ways to build DAPLink. You can generate Keil MDK project files and build within MDK. MDK is also used to debug DAPLink running on the interface chip. Or, you can use the `mbedcli_compile.py` script to build projects from the command line without requiring MDK. +There are two ways to build DAPLink. You can use the `progen` command-line tool from project-generator or the `tools/progen_compile.py` wrapper tool. +**Step 3.1.** Using `progen_compile.py` -**Step 4.1.** For MDK progen compilation. - -This command generates MDK project files under the `projectfiles/uvision` directory. ``` -$ progen generate -t uvision +(venv) $ python tools/progen_compile.py [-t ] [--clean] [-v] [--parallel] [ [ ...]] ``` -To only generate one specific project, use a command like this: -``` -progen generate -f projects.yaml -p stm32f103xb_stm32f746zg_if -t uvision -``` -These options to `progen` set the parameters: -- `-f` for the input projects file -- `-p` for the project name -- `-t` to specify the IDE name +* `-t `: choose the toolchain to build. The default is `make_gcc_arm`. Other options tested are `make_gcc_arm`, `make_armclang`, `make_armcc`, `cmake_gcc_arm`, `cmake_armclang`, `cmake_armcc`. +* `--clean`: will clear existing compilation products and force recompilation of all files. +* `-v`: will make compilation process more verbose (typically listing all commands with their arguments) +* `--parallel`: enable parallel compilation within a project (projects are compiled sequentially). +* ``: target project to compile (e.g. `stm32f103xb_bl`, `lpc11u35_if`), if none is specified all (140 to 150) projects will be compiled. +**Step 3.2.** Using `progen` with `make` -**Step 4.2.** For mbed-cli project compilation +The following command combines generation and compilation: -This command will build all projects: ``` -$ tools/mbedcli_compile.py +(venv) $ progen generate -t make_gcc_arm -p -b ``` -To build only a subset of projects, add the project name(s) to the end of the command line. Valid project names are listed -in the usage text shown with `--help`. The first time you build after each pull you should add `--clean` to perform a -complete re-build. +Alternatively one can separate those task: +``` +(venv) $ progen generate -t make_gcc_arm -p +(venv) $ make -C projectfiles/make_gcc_arm/ [] [VERBOSE=1] +``` +Where: +* ``: target project to compile (e.g. `stm32f103xb_bl`, `lpc11u35_if`). +* ``: build target, can be `all`, `clean` or `help`. +* `VERBOSE=1`: display additional compilation information. -## Contribute -We would love to have your changes! Pull requests should be made once a changeset is [rebased onto Master](https://www.atlassian.com/git/tutorials/merging-vs-rebasing/workflow-walkthrough). See the [contributing guide](../CONTRIBUTING.md) for detailed requirements and guidelines for contributions. +**Step 3.3.** Using `progen` with `cmake` -## Mbed-cli compile environment +The following command combines generation and compilation: -### Features -- Support both Python 2.x and 3.x versions. -- Can compile a list of projects or the all of the projects. -- Can generate the release directory with one command. +``` +(venv) $ progen generate -t cmake_gcc_arm -o generator= -p -b +``` +* ``: use `CMake` generators among the following options: + * `make` (`Unix Makefiles`) + * `mingw-make` (`MinGW Makefiles`) + * `msys-make` (`MSYS Makefiles`, untested) + * `ninja` (`Ninja`) + * `nmake` (`NMake Makefiles`) +* ``: target project to compile (e.g. `stm32f103xb_bl`, `lpc11u35_if`). -### Prerequisite -mbed-cli is included in `requirements.txt`, so it will be installed automatically when configuring -your development environment using the steps described above. +**Step 3.4.** Using `progen` for MDK compilation. -### `tools/mbedcli_compile.py` script -Arguments +This command generates MDK project files under the `projectfiles/uvision` directory. +``` +$ progen generate -t uvision ``` -positional arguments: - projects Selectively compile only the firmware specified - otherwise all projects -optional arguments: - -h, --help show this help message and exit - --release Create a release with the yaml version file - --build-folder BUILD_FOLDER - Release directory to grab files from - --release-folder RELEASE_FOLDER - Directory to create and place files in - --toolchain TOOLCHAIN - Toolchain directory if present - --clean Rebuild or delete build folder before compile - -v Pass verbosity level to mbed compile -vv for more +To only generate one specific project, use a command like this: +``` +progen generate -f projects.yaml -p stm32f103xb_stm32f746zg_if -t uvision ``` -Valid projects are listed on help. +These options to `progen` set the parameters: +- `-f` for the input projects file +- `-p` for the project name +- `-t` to specify the IDE name -Generate files needed by mbed-cli -* `custom_profile.json` lists toolchain profile or compile flags parsed from the yaml files -* `custom_targets.json` contains platform information for specific hics. -* `.mbedignore` filters all files not needed for the project. +## Contribute +We would love to have your changes! Pull requests should be made once a changeset is [rebased onto main](https://www.atlassian.com/git/tutorials/merging-vs-rebasing/workflow-walkthrough). See the [contributing guide](../CONTRIBUTING.md) for detailed requirements and guidelines for contributions. ## Port There are three defined ways in which DAPLink can be extended. These are adding target support, adding board support and adding HIC support. Details on porting each of these can be found below. @@ -128,15 +111,24 @@ There are three defined ways in which DAPLink can be extended. These are adding * [Adding a new board](PORT_BOARD.md) * [Adding a new HIC](PORT_HIC.md) - ## Test DAPLink has an extensive set of automated tests written in Python. They are used for regression testing, but you can use them to validate your DAPLink port. Details are [here](AUTOMATED_TESTS.md) An option to search for the daplink firmware build in uvision and mbedcli build folders. -`python test/run_test.py --project-tool mbedcli ...` or `python test/run_test.py --project-tool uvision ...`. +`python test/run_test.py --project-tool make_gcc_arm ...` or `python test/run_test.py --project-tool uvision ...`. ## Release +### Release using `progen_compile.py` + +* Create a tag with the correct release version and push it to github +* Clean the repo you will be building from by running 'git clean -xdf' followed by 'git reset --hard' +* Run the `progen_compile.py` command with the following parameters (see above for the `-t` flag): +``` +(venv) $ python tools/progen_compile.py [-t ] --clean -v --parallel --release +``` +* All release deliverables will be created and stored in `firmware_` (where `` is the DAPLink version). Save this wherever your builds are stored. + ### Release using uvision DAPLink contains scripts to automate most of the steps of building a release. In addition to building the release, these scripts also save relevant build information such as git SHA and python tool versions so the same build can be reproduced. The recommended steps for creating a release are below. @@ -150,20 +142,6 @@ Note: A previous build can be reproduced by using the ``build_requirements.txt`` To do this add the additional argument ``build_requirements.txt`` when calling ``build_release_uvision.bat`` in step 2. This will install and build with the exact version of the python packages used to create that build. -### Release using mbedcli - -If the project list is not specify, all interface and booloader projects will be compiled. If `--release_version` is given, a folder (`firmware` on default or specified by `--release_folder`, to be concatenated with the version number), will be generated with the bin, update.yml and zip file containing the bins for release -``` -$ venv/Scripts/activate -$ pip install -r requirements3.txt -$ tools/mbedcli_compile.py --release_version 0250 --release_folder firmware -``` - -There is an intermediate step in uvision environment in creating a release directory. This step is not needed in mbedcli environment but to make this equivalent directory invoke -`copy_release_files.py --project-tool mbedcli` -To make a release directory from the step above. -`package_release_files.py SRC_DIR DEST_DIR VERSION_NUMBER --toolchain ARM` - ## MDK If you want to use the MDK (uVision) IDE to work with the DAPLink code, you must launch it in the right environment. The project will fail to build otherwise. To launch uVision properly, use ``tools/launch_uvision.bat`` From 2024a091d958f21e2238ea8ed5fadeccd238e484 Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Thu, 4 Nov 2021 16:34:48 -0600 Subject: [PATCH 396/617] Serial and I2C fixes for Microbit V2 (#892) -Enabled UART HW overrun interrupt -Optimized time spent in I2C IRQ handler by moving bufffer clearing outside -Add I2C busy singaling mechanism -Add I2C ASCII encoding window command feature --- source/board/microbitv2/i2c_commands.c | 88 ++++++++++++++++++++++---- source/board/microbitv2/i2c_commands.h | 6 +- source/board/microbitv2/microbitv2.c | 32 +++++++++- source/hic_hal/freescale/kl27z/uart.c | 2 +- 4 files changed, 110 insertions(+), 18 deletions(-) diff --git a/source/board/microbitv2/i2c_commands.c b/source/board/microbitv2/i2c_commands.c index f3e42b159..d34c05bde 100644 --- a/source/board/microbitv2/i2c_commands.c +++ b/source/board/microbitv2/i2c_commands.c @@ -47,6 +47,9 @@ static volatile bool g_SlaveCompletionFlag = false; static volatile bool g_SlaveRxFlag = false; static uint8_t address_match = 0; static uint32_t transferredCount = 0; +static const uint8_t g_slave_busy_error_buff[] = {gErrorResponse_c, gErrorBusy_c}; +static uint8_t g_slave_TX_buff_ready = 0; +static uint8_t g_slave_busy = 0; static i2cWriteCallback_t pfWriteCommsCallback = NULL; static i2cReadCallback_t pfReadCommsCallback = NULL; @@ -73,6 +76,8 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size); static void i2c_read_flash_callback(uint8_t* pData, uint8_t size); static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData) { + i2cCommand_t i2cResponse = {0}; + switch (xfer->event) { /* Address match event */ @@ -86,21 +91,31 @@ static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void /* Transmit request */ case kI2C_SlaveTransmitEvent: /* Update information for transmit process */ - xfer->data = g_slave_TX_buff; - xfer->dataSize = I2C_DATA_LENGTH; + // Send response if the buffer is ready, otherwise send busy error + if (g_slave_TX_buff_ready) { + xfer->data = g_slave_TX_buff; + xfer->dataSize = I2C_DATA_LENGTH; + } else { + xfer->data = (uint8_t*)g_slave_busy_error_buff; + xfer->dataSize = sizeof(g_slave_busy_error_buff); + g_slave_busy = 1; + } g_SlaveRxFlag = false; break; /* Receive request */ case kI2C_SlaveReceiveEvent: /* Update information for received process */ + // We don't need to clear g_slave_RX_buff because we also have the + // transferredCount to know what data is valid + xfer->data = g_slave_RX_buff; + xfer->dataSize = I2C_DATA_LENGTH; + // Hack: Default driver can't differentiate between RX or TX on // completion event, so we set a flag here. Can't process more // than I2C_DATA_LENGTH bytes on RX - memset(&g_slave_RX_buff, 0, sizeof(g_slave_RX_buff)); - xfer->data = g_slave_RX_buff; - xfer->dataSize = I2C_DATA_LENGTH; g_SlaveRxFlag = true; + break; /* Transfer done */ @@ -115,9 +130,20 @@ static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void // Ignore NOP cmd in I2C Write if (!(g_SlaveRxFlag && g_slave_RX_buff[0] == 0x00)) { - main_board_event(); + // Only process events if the busy error was not read + if (!g_slave_busy) { + main_board_event(); + } else { + g_slave_busy = 0; + } } + // Buffer with response is not ready after an I2C Write inside the IRQ + // It will be ready when the task attends the I2C event + if(g_SlaveRxFlag) { + g_slave_TX_buff_ready = 0; + } + i2c_allow_sleep = false; break; @@ -130,6 +156,7 @@ static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void void board_custom_event() { if (g_SlaveRxFlag) { + i2c_clearBuffer(); if (pfWriteCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { pfWriteCommsCallback(&g_slave_RX_buff[0], transferredCount); } @@ -259,6 +286,7 @@ void i2c_fillBuffer (uint8_t* data, uint32_t position, uint32_t size) { for (uint32_t i = 0; i < size; i++) { g_slave_TX_buff[position + i] = data[i]; } + g_slave_TX_buff_ready = 1; } static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { @@ -276,7 +304,7 @@ static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { memcpy(&i2cResponse.cmdData.readRspCmd.data, &board_id_hex, sizeof(board_id_hex)); break; case gI2CProtocolVersion_c: { - uint16_t i2c_version = 1; + uint16_t i2c_version = 2; i2cResponse.cmdData.readRspCmd.dataSize = sizeof(i2c_version); memcpy(&i2cResponse.cmdData.readRspCmd.data, &i2c_version, sizeof(i2c_version)); } @@ -413,8 +441,6 @@ static void i2c_read_comms_callback(uint8_t* pData, uint8_t size) { break; } - i2c_clearBuffer(); - // Release COMBINED_SENSOR_INT PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); } @@ -478,8 +504,6 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { uint32_t address = storage_address + FLASH_STORAGE_ADDRESS; uint32_t length = __REV(pI2cCommand->cmdData.write.length); uint32_t data = (uint32_t) pI2cCommand->cmdData.write.data; - - i2c_clearBuffer(); switch (pI2cCommand->cmdId) { case gFlashDataWrite_c: @@ -606,6 +630,44 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); } break; + case gFlashCfgEncWindow_c: + if (size == 1) { + /* If size is 1 (only cmd id), this means it's a read */ + uint32_t tempFileEncWindowStart = __REV(gflashConfig.fileEncWindowStart); + uint32_t tempFileEncWindowEnd = __REV(gflashConfig.fileEncWindowEnd); + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBuffer((uint8_t*) &tempFileEncWindowStart, 1, sizeof(gflashConfig.fileEncWindowStart)); + i2c_fillBuffer((uint8_t*) &tempFileEncWindowEnd, 5, sizeof(gflashConfig.fileEncWindowEnd)); + } else if (size == 9) { + /* If size is 9 (cmd id + 8B data), this means it's a write */ + uint32_t tempFileEncWindowStart = pI2cCommand->cmdData.data[0] << 24 | + pI2cCommand->cmdData.data[1] << 16 | + pI2cCommand->cmdData.data[2] << 8 | + pI2cCommand->cmdData.data[3] << 0; + uint32_t tempFileEncWindowEnd = pI2cCommand->cmdData.data[4] << 24 | + pI2cCommand->cmdData.data[5] << 16 | + pI2cCommand->cmdData.data[6] << 8 | + pI2cCommand->cmdData.data[7] << 0; + + /* Validate encoding window */ + if (tempFileEncWindowStart <= tempFileEncWindowEnd) { + gflashConfig.fileEncWindowStart = tempFileEncWindowStart; + tempFileEncWindowStart = __REV(gflashConfig.fileEncWindowStart); + gflashConfig.fileEncWindowEnd = tempFileEncWindowEnd; + tempFileEncWindowEnd = __REV(gflashConfig.fileEncWindowEnd); + + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBuffer((uint8_t*) &tempFileEncWindowStart, 1, sizeof(gflashConfig.fileEncWindowStart)); + i2c_fillBuffer((uint8_t*) &tempFileEncWindowEnd, 5, sizeof(gflashConfig.fileEncWindowEnd)); + } else { + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } + } else { + pI2cCommand->cmdId = gFlashError_c; + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + } + break; case gFlashCfgFileVisible_c: if (size == 1) { /* If size is 1 (only cmd id), this means it's a read */ @@ -649,6 +711,8 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { memcpy(gflashConfig.fileName, FLASH_CFG_FILENAME, 11); gflashConfig.fileSize = FLASH_CFG_FILESIZE; gflashConfig.fileVisible = FLASH_CFG_FILEVISIBLE; + gflashConfig.fileEncWindowStart = 0; + gflashConfig.fileEncWindowEnd = 0; } i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); break; @@ -676,8 +740,6 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { } static void i2c_read_flash_callback(uint8_t* pData, uint8_t size) { - i2c_clearBuffer(); - // Release COMBINED_SENSOR_INT PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); } diff --git a/source/board/microbitv2/i2c_commands.h b/source/board/microbitv2/i2c_commands.h index f18436210..5f975cca6 100644 --- a/source/board/microbitv2/i2c_commands.h +++ b/source/board/microbitv2/i2c_commands.h @@ -77,7 +77,8 @@ typedef enum errorCode_tag { gErrorWrongPropertySize_c = 0x35, gErrorReadDisallowed_c = 0x36, gErrorWriteDisallowed_c = 0x37, - gErrorWriteFail_c = 0x38 + gErrorWriteFail_c = 0x38, + gErrorBusy_c = 0x39 } errorCode_t; typedef __PACKED_STRUCT readReqCmd_tag { @@ -123,6 +124,8 @@ typedef __PACKED_STRUCT flashConfig_tag { vfs_filename_t fileName; uint32_t fileSize; bool fileVisible; + uint32_t fileEncWindowStart; + uint32_t fileEncWindowEnd; } flashConfig_t; /*! Flash interface command type */ @@ -135,6 +138,7 @@ typedef enum flashCmdId_tag { gFlashStorageSize_c = 0x06, gFlashSectorSize_c = 0x07, gFlashRemountMSD_c = 0x08, + gFlashCfgEncWindow_c = 0x09, gFlashDataRead_c = 0x0A, gFlashDataWrite_c = 0x0B, gFlashDataErase_c = 0x0C, diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 188fbbb29..b8c69fa98 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -71,6 +71,8 @@ flashConfig_t gflashConfig = { .fileName = FLASH_CFG_FILENAME, .fileSize = FLASH_CFG_FILESIZE, .fileVisible = FLASH_CFG_FILEVISIBLE, + .fileEncWindowStart = 0, + .fileEncWindowEnd = 0, }; typedef enum { @@ -527,7 +529,8 @@ void vfs_user_build_filesystem_hook() { } } - file_size = gflashConfig.fileSize; + // Add encoding window file size. 1B encoded into 2B ASCII + file_size = gflashConfig.fileSize + (gflashConfig.fileEncWindowEnd - gflashConfig.fileEncWindowStart); if (gflashConfig.fileVisible) { vfs_create_file(gflashConfig.fileName, read_file_data_txt, 0, file_size); @@ -537,9 +540,32 @@ void vfs_user_build_filesystem_hook() { // File callback to be used with vfs_add_file to return file contents static uint32_t read_file_data_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors) { + uint32_t read_address = FLASH_STORAGE_ADDRESS + (VFS_SECTOR_SIZE * sector_offset); + uint32_t encoded_data_offset = (gflashConfig.fileEncWindowEnd - gflashConfig.fileEncWindowStart); + // Ignore out of bound reads - if ( (FLASH_STORAGE_ADDRESS + VFS_SECTOR_SIZE * sector_offset) < (FLASH_CONFIG_ADDRESS + FLASH_INTERFACE_SIZE) ) { - memcpy(data, (uint8_t *) (FLASH_STORAGE_ADDRESS + VFS_SECTOR_SIZE * sector_offset), VFS_SECTOR_SIZE); + if ( read_address < (FLASH_CONFIG_ADDRESS + FLASH_INTERFACE_SIZE + encoded_data_offset) ) { + for (uint32_t i = 0; i < VFS_SECTOR_SIZE; i++) { + if (i + (VFS_SECTOR_SIZE * sector_offset) < gflashConfig.fileEncWindowStart) { + // If data is before encoding window, no offset is needed + data[i] = *(uint8_t *) (read_address + i); + } else if(i + (VFS_SECTOR_SIZE * sector_offset) < (gflashConfig.fileEncWindowStart + encoded_data_offset * 2)) { + // Data inside encoding window needs to consider encoding window start and size + uint8_t enc_byte = *(uint8_t *) (FLASH_STORAGE_ADDRESS + ((VFS_SECTOR_SIZE * sector_offset) + gflashConfig.fileEncWindowStart + i ) / 2); + if (i % 2 == 0) { + // High nibble + enc_byte = 0x0F & (enc_byte >> 4); + } else { + // Low nibble + enc_byte = 0x0F & enc_byte; + } + // Encode one nibble to one ASCII byte + data[i] = enc_byte <= 9 ? enc_byte + 0x30 : enc_byte + 0x37; + } else { + // If data is after encoding window, adjustment is needed + data[i] = *(uint8_t *) (read_address + i - encoded_data_offset); + } + } } return VFS_SECTOR_SIZE; diff --git a/source/hic_hal/freescale/kl27z/uart.c b/source/hic_hal/freescale/kl27z/uart.c index da531e5ad..080d51379 100644 --- a/source/hic_hal/freescale/kl27z/uart.c +++ b/source/hic_hal/freescale/kl27z/uart.c @@ -180,7 +180,7 @@ int32_t uart_set_configuration(UART_Configuration *config) // Enable UART interrupt NVIC_ClearPendingIRQ(UART_RX_TX_IRQn); NVIC_EnableIRQ(UART_RX_TX_IRQn); - UART->CTRL |= LPUART_CTRL_RIE_MASK; + UART->CTRL |= LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK; return 1; } From 82d9b4deb61445c854a9283e85e3abd69b0faa2f Mon Sep 17 00:00:00 2001 From: Chris Reed Date: Sun, 7 Nov 2021 22:53:28 -0600 Subject: [PATCH 397/617] DAP: define constants for DAPLink's CMSIS-DAP vendor commands. (#891) --- source/daplink/cmsis-dap/DAP_vendor.c | 25 ++++++------ .../cmsis-dap/daplink_vendor_commands.h | 39 +++++++++++++++++++ 2 files changed, 52 insertions(+), 12 deletions(-) create mode 100644 source/daplink/cmsis-dap/daplink_vendor_commands.h diff --git a/source/daplink/cmsis-dap/DAP_vendor.c b/source/daplink/cmsis-dap/DAP_vendor.c index ce34cab28..91dcb17fb 100644 --- a/source/daplink/cmsis-dap/DAP_vendor.c +++ b/source/daplink/cmsis-dap/DAP_vendor.c @@ -2,6 +2,7 @@ * Copyright (c) 2013-2020 Arm Limited. All rights reserved. * Copyright 2019, Cypress Semiconductor Corporation * or a subsidiary of Cypress Semiconductor Corporation. + * Copyright (c) 2021 Chris Reed * * SPDX-License-Identifier: Apache-2.0 * @@ -38,7 +39,7 @@ #include "target_family.h" #include "flash_manager.h" #include - +#include "daplink_vendor_commands.h" #ifdef DRAG_N_DROP_SUPPORT #include "file_stream.h" @@ -67,7 +68,7 @@ uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { *response++ = *request; // copy Command ID switch (*request++) { // first byte in request is Command ID - case ID_DAP_Vendor0: { + case ID_DAP_GetUniqueID: { const char *id_str = info_get_unique_id(); uint8_t len = strlen(id_str); *response++ = len; @@ -75,7 +76,7 @@ uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { num += (len + 1); // increment response count by ID length + length byte break; } - case ID_DAP_Vendor1: { + case ID_DAP_UART_GetLineCoding: { // get line coding int32_t read_len = sizeof(CDC_LINE_CODING); CDC_LINE_CODING cdc_line_coding; @@ -84,7 +85,7 @@ uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { num += (read_len + 1); break; } - case ID_DAP_Vendor2: { + case ID_DAP_UART_SetConfiguration: { // set uart configuration CDC_LINE_CODING cdc_line_coding; USBD_CDC_ACM_PortGetLineCoding(&cdc_line_coding); @@ -98,7 +99,7 @@ uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { num += (sizeof(uint32_t) << 16) | 1; break; } - case ID_DAP_Vendor3: { + case ID_DAP_UART_Read: { // uart read int32_t read_len = 62; read_len = uart_read_data(response + 1, read_len); @@ -110,7 +111,7 @@ uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { num += (read_len + 1); break; } - case ID_DAP_Vendor4: { + case ID_DAP_UART_Write: { // uart write int32_t write_len = *request; request++; @@ -123,7 +124,7 @@ uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { case ID_DAP_Vendor5: break; case ID_DAP_Vendor6: break; case ID_DAP_Vendor7: break; - case ID_DAP_Vendor8: { + case ID_DAP_SetUSBTestMode: { *response = 1; if (0 == *request) { main_usb_set_test_mode(false); @@ -135,7 +136,7 @@ uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { num += (1U << 16) | 1U; // increment request and response count each by 1 break; } - case ID_DAP_Vendor9: { + case ID_DAP_ResetTargetIfNoAutoReset: { // reset target *response = 1; if (!config_get_auto_rst()) { @@ -145,19 +146,19 @@ uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { break; } #ifdef DRAG_N_DROP_SUPPORT - case ID_DAP_Vendor10: { + case ID_DAP_MSD_Open: { // open mass storage device stream *response = stream_open((stream_type_t)(*request)); num += (1 << 16) | 1; break; } - case ID_DAP_Vendor11: { + case ID_DAP_MSD_Close: { // close mass storage device stream *response = stream_close(); num += 1; break; } - case ID_DAP_Vendor12: { + case ID_DAP_MSD_Write: { // write to mass storage device uint32_t write_len = *request; request++; @@ -167,7 +168,7 @@ uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { break; } #endif - case ID_DAP_Vendor13: { + case ID_DAP_SelectEraseMode: { // switching between chip erase and page erase // COMMAND(OUT Packet) // BYTE 0 1000 1110 0x8D diff --git a/source/daplink/cmsis-dap/daplink_vendor_commands.h b/source/daplink/cmsis-dap/daplink_vendor_commands.h new file mode 100644 index 000000000..18aee7492 --- /dev/null +++ b/source/daplink/cmsis-dap/daplink_vendor_commands.h @@ -0,0 +1,39 @@ +/* + * DAPLink Interface Firmware + * Copyright (c) 2021 Chris Reed + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/** + * @file + * @brief Vendor-specific CMSIS-DAP command constants. + */ + +#include "DAP.h" + +//! @name DAPLink vendor-specific CMSIS-DAP command IDs +//@{ +#define ID_DAP_GetUniqueID ID_DAP_Vendor0 +#define ID_DAP_UART_GetLineCoding ID_DAP_Vendor1 +#define ID_DAP_UART_SetConfiguration ID_DAP_Vendor2 +#define ID_DAP_UART_Read ID_DAP_Vendor3 +#define ID_DAP_UART_Write ID_DAP_Vendor4 +#define ID_DAP_SetUSBTestMode ID_DAP_Vendor8 +#define ID_DAP_ResetTargetIfNoAutoReset ID_DAP_Vendor9 +#define ID_DAP_MSD_Open ID_DAP_Vendor10 +#define ID_DAP_MSD_Close ID_DAP_Vendor11 +#define ID_DAP_MSD_Write ID_DAP_Vendor12 +#define ID_DAP_SelectEraseMode ID_DAP_Vendor13 +//@} + From 28242d448685276743ac741c30eace7fc53d9027 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 19 Jun 2021 23:54:29 -0500 Subject: [PATCH 398/617] nrf52820_hic: Import CMSIS startup/system for nRF52820 --- .../nrf52820/armcc/arm_startup_nrf52820.s | 349 + .../nrf52820/cmsis/compiler_abstraction.h | 249 + source/hic_hal/nordic/nrf52820/cmsis/nrf.h | 195 + .../nordic/nrf52820/cmsis/nrf51_erratas.h | 3770 +++++ .../nordic/nrf52820/cmsis/nrf51_to_nrf52.h | 2364 +++ source/hic_hal/nordic/nrf52820/cmsis/nrf52.h | 2452 +++ .../hic_hal/nordic/nrf52820/cmsis/nrf52820.h | 2105 +++ .../nrf52820/cmsis/nrf52820_bitfields.h | 12096 +++++++++++++++ .../nrf52820/cmsis/nrf52820_peripherals.h | 240 + .../nrf52820/cmsis/nrf52833_to_nrf52820.h | 54 + .../nordic/nrf52820/cmsis/nrf52_bitfields.h | 12663 ++++++++++++++++ .../nordic/nrf52820/cmsis/nrf52_erratas.h | 9265 +++++++++++ .../nordic/nrf52820/cmsis/nrf52_name_change.h | 81 + .../nordic/nrf52820/cmsis/nrf52_to_nrf52810.h | 162 + .../nordic/nrf52820/cmsis/nrf52_to_nrf52833.h | 159 + .../nordic/nrf52820/cmsis/nrf52_to_nrf52840.h | 161 + .../nordic/nrf52820/cmsis/nrf53_erratas.h | 2922 ++++ .../nordic/nrf52820/cmsis/nrf91_erratas.h | 750 + .../nordic/nrf52820/cmsis/nrf_erratas.h | 59 + .../nordic/nrf52820/cmsis/system_nrf52820.c | 119 + .../nordic/nrf52820/cmsis/system_nrf52820.h | 61 + .../nrf52820/gcc/ses_startup_nrf52820.S | 358 + .../nrf52820/gcc/ses_startup_nrf_common.S | 193 + .../nordic/nrf52820/nrfx/nrfx_config.h | 2245 +++ 24 files changed, 53072 insertions(+) create mode 100644 source/hic_hal/nordic/nrf52820/armcc/arm_startup_nrf52820.s create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/compiler_abstraction.h create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/nrf.h create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/nrf51_erratas.h create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/nrf51_to_nrf52.h create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/nrf52.h create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/nrf52820.h create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/nrf52820_bitfields.h create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/nrf52820_peripherals.h create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/nrf52833_to_nrf52820.h create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/nrf52_bitfields.h create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/nrf52_erratas.h create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/nrf52_name_change.h create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52810.h create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52833.h create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52840.h create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/nrf53_erratas.h create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/nrf91_erratas.h create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/nrf_erratas.h create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/system_nrf52820.c create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/system_nrf52820.h create mode 100644 source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf52820.S create mode 100644 source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf_common.S create mode 100644 source/hic_hal/nordic/nrf52820/nrfx/nrfx_config.h diff --git a/source/hic_hal/nordic/nrf52820/armcc/arm_startup_nrf52820.s b/source/hic_hal/nordic/nrf52820/armcc/arm_startup_nrf52820.s new file mode 100644 index 000000000..02d9a3b39 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/armcc/arm_startup_nrf52820.s @@ -0,0 +1,349 @@ +; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +; NOTICE: This file has been modified by Nordic Semiconductor ASA. + + IF :DEF: __STARTUP_CONFIG +#ifdef __STARTUP_CONFIG +#include "startup_config.h" +#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT +#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 +#endif +#endif + ENDIF + + IF :DEF: __STARTUP_CONFIG +Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE + ELIF :DEF: __STACK_SIZE +Stack_Size EQU __STACK_SIZE + ELSE +Stack_Size EQU 2048 + ENDIF + + IF :DEF: __STARTUP_CONFIG +Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT + ELSE +Stack_Align EQU 3 + ENDIF + + AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align +Stack_Mem SPACE Stack_Size +__initial_sp + + IF :DEF: __STARTUP_CONFIG +Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE + ELIF :DEF: __HEAP_SIZE +Heap_Size EQU __HEAP_SIZE + ELSE +Heap_Size EQU 2048 + ENDIF + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD MemoryManagement_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 ; Reserved + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD POWER_CLOCK_IRQHandler + DCD RADIO_IRQHandler + DCD UARTE0_UART0_IRQHandler + DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler + DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler + DCD 0 ; Reserved + DCD GPIOTE_IRQHandler + DCD 0 ; Reserved + DCD TIMER0_IRQHandler + DCD TIMER1_IRQHandler + DCD TIMER2_IRQHandler + DCD RTC0_IRQHandler + DCD TEMP_IRQHandler + DCD RNG_IRQHandler + DCD ECB_IRQHandler + DCD CCM_AAR_IRQHandler + DCD WDT_IRQHandler + DCD RTC1_IRQHandler + DCD QDEC_IRQHandler + DCD COMP_IRQHandler + DCD SWI0_EGU0_IRQHandler + DCD SWI1_EGU1_IRQHandler + DCD SWI2_EGU2_IRQHandler + DCD SWI3_EGU3_IRQHandler + DCD SWI4_EGU4_IRQHandler + DCD SWI5_EGU5_IRQHandler + DCD TIMER3_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD USBD_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemoryManagement_Handler\ + PROC + EXPORT MemoryManagement_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT POWER_CLOCK_IRQHandler [WEAK] + EXPORT RADIO_IRQHandler [WEAK] + EXPORT UARTE0_UART0_IRQHandler [WEAK] + EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK] + EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK] + EXPORT GPIOTE_IRQHandler [WEAK] + EXPORT TIMER0_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT RTC0_IRQHandler [WEAK] + EXPORT TEMP_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT ECB_IRQHandler [WEAK] + EXPORT CCM_AAR_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC1_IRQHandler [WEAK] + EXPORT QDEC_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT SWI0_EGU0_IRQHandler [WEAK] + EXPORT SWI1_EGU1_IRQHandler [WEAK] + EXPORT SWI2_EGU2_IRQHandler [WEAK] + EXPORT SWI3_EGU3_IRQHandler [WEAK] + EXPORT SWI4_EGU4_IRQHandler [WEAK] + EXPORT SWI5_EGU5_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT USBD_IRQHandler [WEAK] +POWER_CLOCK_IRQHandler +RADIO_IRQHandler +UARTE0_UART0_IRQHandler +SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +GPIOTE_IRQHandler +TIMER0_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +RTC0_IRQHandler +TEMP_IRQHandler +RNG_IRQHandler +ECB_IRQHandler +CCM_AAR_IRQHandler +WDT_IRQHandler +RTC1_IRQHandler +QDEC_IRQHandler +COMP_IRQHandler +SWI0_EGU0_IRQHandler +SWI1_EGU1_IRQHandler +SWI2_EGU2_IRQHandler +SWI3_EGU3_IRQHandler +SWI4_EGU4_IRQHandler +SWI5_EGU5_IRQHandler +TIMER3_IRQHandler +USBD_IRQHandler + B . + ENDP + ALIGN + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/source/hic_hal/nordic/nrf52820/cmsis/compiler_abstraction.h b/source/hic_hal/nordic/nrf52820/cmsis/compiler_abstraction.h new file mode 100644 index 000000000..cf750ce55 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/compiler_abstraction.h @@ -0,0 +1,249 @@ +/* + +Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef _COMPILER_ABSTRACTION_H +#define _COMPILER_ABSTRACTION_H + +/*lint ++flb "Enter library region" */ + +#ifndef NRF_STRING_CONCATENATE_IMPL + #define NRF_STRING_CONCATENATE_IMPL(lhs, rhs) lhs ## rhs +#endif +#ifndef NRF_STRING_CONCATENATE + #define NRF_STRING_CONCATENATE(lhs, rhs) NRF_STRING_CONCATENATE_IMPL(lhs, rhs) +#endif +#if __LINT__ == 1 + #ifndef NRF_STATIC_ASSERT + #define NRF_STATIC_ASSERT(cond, msg) + #endif +#endif + +#if defined ( __CC_ARM ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE __inline + #endif + + #ifndef __WEAK + #define __WEAK __weak + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __align(n) + #endif + + #ifndef __PACKED + #define __PACKED __packed + #endif + + #ifndef __UNUSED + #define __UNUSED __attribute__((unused)) + #endif + + #define GET_SP() __current_sp() + + #ifndef NRF_STATIC_ASSERT + #define NRF_STATIC_ASSERT(cond, msg) \ + ;enum { NRF_STRING_CONCATENATE(static_assert_on_line_, __LINE__) = 1 / (!!(cond)) } + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE __inline + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __attribute__((aligned(n))) + #endif + + #ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) + #endif + + #ifndef __UNUSED + #define __UNUSED __attribute__((unused)) + #endif + + #define GET_SP() __current_sp() + + #ifndef NRF_STATIC_ASSERT + #define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg) + #endif + +#elif defined ( __ICCARM__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __WEAK + #define __WEAK __weak + #endif + + #ifndef __ALIGN + #define STRING_PRAGMA(x) _Pragma(#x) + #define __ALIGN(n) STRING_PRAGMA(data_alignment = n) + #endif + + #ifndef __PACKED + #define __PACKED __packed + #endif + + #ifndef __UNUSED + #define __UNUSED + #endif + + #define GET_SP() __get_SP() + + #ifndef NRF_STATIC_ASSERT + #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg) + #endif + +#elif defined ( __GNUC__ ) || defined ( __clang__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __attribute__((aligned(n))) + #endif + + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + + #ifndef __UNUSED + #define __UNUSED __attribute__((unused)) + #endif + + #define GET_SP() gcc_current_sp() + + static inline unsigned int gcc_current_sp(void) + { + unsigned int stack_pointer = 0; + __asm__ __volatile__ ("mov %0, sp" : "=r"(stack_pointer)); + return stack_pointer; + } + + #ifndef NRF_STATIC_ASSERT + #define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg) + #endif + +#elif defined ( __TASKING__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __align(n) + #endif + + /* Not defined for TASKING. */ + #ifndef __PACKED + #define __PACKED + #endif + + #ifndef __UNUSED + #define __UNUSED __attribute__((unused)) + #endif + + #define GET_SP() __get_MSP() + + #ifndef NRF_STATIC_ASSERT + #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg) + #endif + +#endif + +#define NRF_MDK_VERSION_ASSERT_AT_LEAST(major, minor, micro) \ + NRF_STATIC_ASSERT( \ + ( \ + (major < MDK_MAJOR_VERSION) || \ + (major == MDK_MAJOR_VERSION && minor < MDK_MINOR_VERSION) || \ + (major == MDK_MAJOR_VERSION && minor == MDK_MINOR_VERSION && micro < MDK_MICRO_VERSION) \ + ), "MDK version mismatch.") + +#define NRF_MDK_VERSION_ASSERT_EXACT(major, minor, micro) \ + NRF_STATIC_ASSERT( \ + ( \ + (major != MDK_MAJOR_VERSION) || \ + (major != MDK_MAJOR_VERSION) || \ + (major != MDK_MAJOR_VERSION) \ + ), "MDK version mismatch.") + +/*lint --flb "Leave library region" */ + +#endif diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf.h new file mode 100644 index 000000000..7d639fb0a --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf.h @@ -0,0 +1,195 @@ +/* + +Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF_H +#define NRF_H + +/* MDK version */ +#define MDK_MAJOR_VERSION 8 +#define MDK_MINOR_VERSION 35 +#define MDK_MICRO_VERSION 0 + +/* Define NRF51_SERIES for common use in nRF51 series devices. Only if not previously defined. */ +#if defined (NRF51) ||\ + defined (NRF51422_XXAA) ||\ + defined (NRF51422_XXAB) ||\ + defined (NRF51422_XXAC) ||\ + defined (NRF51801_XXAB) ||\ + defined (NRF51802_XXAA) ||\ + defined (NRF51822_XXAA) ||\ + defined (NRF51822_XXAB) ||\ + defined (NRF51822_XXAC) ||\ + defined (NRF51824_XXAA) + #ifndef NRF51_SERIES + #define NRF51_SERIES + #endif + #ifndef NRF51 + #define NRF51 + #endif +#endif + +/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */ +#if defined (NRF52) + #ifndef NRF52832_XXAA + #define NRF52832_XXAA + #endif +#endif + +/* Define NRF52_SERIES for common use in nRF52 series devices. Only if not previously defined. */ +#if defined (NRF52805_XXAA) || defined (NRF52810_XXAA) || defined (NRF52811_XXAA) || defined (NRF52820_XXAA) || defined (NRF52832_XXAA) || defined (NRF52832_XXAB) || defined (NRF52833_XXAA) || defined (NRF52840_XXAA) + #ifndef NRF52_SERIES + #define NRF52_SERIES + #endif +#endif + +/* Define NRF53_SERIES for common use in nRF53 series devices. */ +#if defined (NRF5340_XXAA_APPLICATION) || defined (NRF5340_XXAA_NETWORK) + #ifndef NRF53_SERIES + #define NRF53_SERIES + #endif +#endif + +/* Define NRF91_SERIES for common use in nRF91 series devices. */ +#if defined (NRF9160_XXAA) + #ifndef NRF91_SERIES + #define NRF91_SERIES + #endif +#endif + +/* Define coprocessor domains */ +#if defined (NRF5340_XXAA_APPLICATION) || defined (NRF5340_XXAA_NETWORK) + #ifndef NRF5340_XXAA + #define NRF5340_XXAA + #endif +#endif +#if defined (NRF5340_XXAA_APPLICATION) + #ifndef NRF_APPLICATION + #define NRF_APPLICATION + #endif +#endif +#if defined (NRF5340_XXAA_NETWORK) + #ifndef NRF_NETWORK + #define NRF_NETWORK + #endif +#endif + +/* Apply compatibility macros for old nRF5340 macros */ +#if defined(NRF5340_XXAA) + #if defined (NRF_APPLICATION) + #ifndef NRF5340_XXAA_APPLICATION + #define NRF5340_XXAA_APPLICATION + #endif + #endif + #if defined (NRF_NETWORK) + #ifndef NRF5340_XXAA_NETWORK + #define NRF5340_XXAA_NETWORK + #endif + #endif +#endif + +/* Device selection for device includes. */ +#if defined (NRF51) + #include "nrf51.h" + #include "nrf51_bitfields.h" + #include "nrf51_deprecated.h" + +#elif defined (NRF52805_XXAA) + #include "nrf52805.h" + #include "nrf52805_bitfields.h" + #include "nrf51_to_nrf52810.h" + #include "nrf52_to_nrf52810.h" + #include "nrf52810_to_nrf52811.h" +#elif defined (NRF52810_XXAA) + #include "nrf52810.h" + #include "nrf52810_bitfields.h" + #include "nrf51_to_nrf52810.h" + #include "nrf52_to_nrf52810.h" + #include "nrf52810_name_change.h" +#elif defined (NRF52811_XXAA) + #include "nrf52811.h" + #include "nrf52811_bitfields.h" + #include "nrf51_to_nrf52810.h" + #include "nrf52_to_nrf52810.h" + #include "nrf52810_to_nrf52811.h" +#elif defined (NRF52820_XXAA) + #include "nrf52820.h" + #include "nrf52820_bitfields.h" + #include "nrf51_to_nrf52.h" + #include "nrf52_to_nrf52833.h" + #include "nrf52833_to_nrf52820.h" +#elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB) + #include "nrf52.h" + #include "nrf52_bitfields.h" + #include "nrf51_to_nrf52.h" + #include "nrf52_name_change.h" +#elif defined (NRF52833_XXAA) + #include "nrf52833.h" + #include "nrf52833_bitfields.h" + #include "nrf52_to_nrf52833.h" + #include "nrf51_to_nrf52.h" +#elif defined (NRF52840_XXAA) + #include "nrf52840.h" + #include "nrf52840_bitfields.h" + #include "nrf51_to_nrf52840.h" + #include "nrf52_to_nrf52840.h" + +#elif defined (NRF5340_XXAA) + #if defined(NRF_APPLICATION) + #include "nrf5340_application.h" + #include "nrf5340_application_bitfields.h" + #elif defined (NRF_NETWORK) + #include "nrf5340_network.h" + #include "nrf5340_network_bitfields.h" + #endif + +#elif defined (NRF9160_XXAA) + #include "nrf9160.h" + #include "nrf9160_bitfields.h" + #include "nrf9160_name_change.h" + +#else + #error "Device must be defined. See nrf.h." +#endif /* NRF51, NRF52805_XXAA, NRF52810_XXAA, NRF52811_XXAA, NRF52820_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52833_XXAA, NRF52840_XXAA, NRF5340_XXAA_APPLICATION, NRF5340_XXAA_NETWORK, NRF9160_XXAA */ + +#include "compiler_abstraction.h" + +#endif /* NRF_H */ + diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf51_erratas.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf51_erratas.h new file mode 100644 index 000000000..3882dfd0c --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf51_erratas.h @@ -0,0 +1,3770 @@ +#ifndef NRF51_ERRATAS_H +#define NRF51_ERRATAS_H + +/* + +Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#include +#include +#include "compiler_abstraction.h" + +static bool nrf51_errata_1(void) __UNUSED; +static bool nrf51_errata_2(void) __UNUSED; +static bool nrf51_errata_3(void) __UNUSED; +static bool nrf51_errata_4(void) __UNUSED; +static bool nrf51_errata_5(void) __UNUSED; +static bool nrf51_errata_6(void) __UNUSED; +static bool nrf51_errata_7(void) __UNUSED; +static bool nrf51_errata_8(void) __UNUSED; +static bool nrf51_errata_9(void) __UNUSED; +static bool nrf51_errata_10(void) __UNUSED; +static bool nrf51_errata_11(void) __UNUSED; +static bool nrf51_errata_12(void) __UNUSED; +static bool nrf51_errata_13(void) __UNUSED; +static bool nrf51_errata_14(void) __UNUSED; +static bool nrf51_errata_15(void) __UNUSED; +static bool nrf51_errata_16(void) __UNUSED; +static bool nrf51_errata_17(void) __UNUSED; +static bool nrf51_errata_18(void) __UNUSED; +static bool nrf51_errata_19(void) __UNUSED; +static bool nrf51_errata_20(void) __UNUSED; +static bool nrf51_errata_21(void) __UNUSED; +static bool nrf51_errata_22(void) __UNUSED; +static bool nrf51_errata_23(void) __UNUSED; +static bool nrf51_errata_24(void) __UNUSED; +static bool nrf51_errata_25(void) __UNUSED; +static bool nrf51_errata_26(void) __UNUSED; +static bool nrf51_errata_27(void) __UNUSED; +static bool nrf51_errata_28(void) __UNUSED; +static bool nrf51_errata_29(void) __UNUSED; +static bool nrf51_errata_30(void) __UNUSED; +static bool nrf51_errata_31(void) __UNUSED; +static bool nrf51_errata_32(void) __UNUSED; +static bool nrf51_errata_33(void) __UNUSED; +static bool nrf51_errata_34(void) __UNUSED; +static bool nrf51_errata_35(void) __UNUSED; +static bool nrf51_errata_36(void) __UNUSED; +static bool nrf51_errata_37(void) __UNUSED; +static bool nrf51_errata_38(void) __UNUSED; +static bool nrf51_errata_39(void) __UNUSED; +static bool nrf51_errata_40(void) __UNUSED; +static bool nrf51_errata_41(void) __UNUSED; +static bool nrf51_errata_42(void) __UNUSED; +static bool nrf51_errata_43(void) __UNUSED; +static bool nrf51_errata_44(void) __UNUSED; +static bool nrf51_errata_45(void) __UNUSED; +static bool nrf51_errata_46(void) __UNUSED; +static bool nrf51_errata_47(void) __UNUSED; +static bool nrf51_errata_48(void) __UNUSED; +static bool nrf51_errata_49(void) __UNUSED; +static bool nrf51_errata_50(void) __UNUSED; +static bool nrf51_errata_51(void) __UNUSED; +static bool nrf51_errata_52(void) __UNUSED; +static bool nrf51_errata_53(void) __UNUSED; +static bool nrf51_errata_54(void) __UNUSED; +static bool nrf51_errata_55(void) __UNUSED; +static bool nrf51_errata_56(void) __UNUSED; +static bool nrf51_errata_57(void) __UNUSED; +static bool nrf51_errata_58(void) __UNUSED; +static bool nrf51_errata_59(void) __UNUSED; +static bool nrf51_errata_60(void) __UNUSED; +static bool nrf51_errata_61(void) __UNUSED; +static bool nrf51_errata_62(void) __UNUSED; +static bool nrf51_errata_63(void) __UNUSED; +static bool nrf51_errata_64(void) __UNUSED; +static bool nrf51_errata_65(void) __UNUSED; +static bool nrf51_errata_66(void) __UNUSED; +static bool nrf51_errata_67(void) __UNUSED; +static bool nrf51_errata_68(void) __UNUSED; +static bool nrf51_errata_69(void) __UNUSED; +static bool nrf51_errata_70(void) __UNUSED; +static bool nrf51_errata_71(void) __UNUSED; +static bool nrf51_errata_72(void) __UNUSED; +static bool nrf51_errata_73(void) __UNUSED; +static bool nrf51_errata_74(void) __UNUSED; +static bool nrf51_errata_75(void) __UNUSED; +static bool nrf51_errata_76(void) __UNUSED; +static bool nrf51_errata_77(void) __UNUSED; +static bool nrf51_errata_78(void) __UNUSED; + +static bool nrf51_errata_1(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_2(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_3(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_4(void) +{ + #ifndef NRF51_SERIES + return false; + #else + return false; + #endif +} + +static bool nrf51_errata_5(void) +{ + #ifndef NRF51_SERIES + return false; + #else + return false; + #endif +} + +static bool nrf51_errata_6(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_7(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_8(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_9(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_10(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_11(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_12(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_13(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_14(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_15(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_16(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_17(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_18(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_19(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_20(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_21(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_22(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_23(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_24(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_25(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_26(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_27(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_28(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_29(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_30(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_31(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_32(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_33(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_34(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_35(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_36(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_37(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_38(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return true; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_39(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_40(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_41(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_42(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_43(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_44(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_45(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_46(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return false; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_47(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_48(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_49(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_50(void) +{ + #ifndef NRF51_SERIES + return false; + #else + return false; + #endif +} + +static bool nrf51_errata_51(void) +{ + #ifndef NRF51_SERIES + return false; + #else + return false; + #endif +} + +static bool nrf51_errata_52(void) +{ + #ifndef NRF51_SERIES + return false; + #else + return false; + #endif +} + +static bool nrf51_errata_53(void) +{ + #ifndef NRF51_SERIES + return false; + #else + return false; + #endif +} + +static bool nrf51_errata_54(void) +{ + #ifndef NRF51_SERIES + return false; + #else + return false; + #endif +} + +static bool nrf51_errata_55(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_56(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_57(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_58(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_59(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_60(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_61(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return true; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_62(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_63(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_64(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_65(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_66(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return false; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_67(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return true; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_68(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_69(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_70(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return true; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_71(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return false; + case 0x0Aul: + return false; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_72(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return true; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_73(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return false; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_74(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return false; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_75(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return true; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_76(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x07ul: + return false; + case 0x08ul: + return false; + case 0x09ul: + return false; + case 0x0Aul: + return true; + case 0x0Bul: + return false; + case 0x0Cul: + return false; + case 0x0Dul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf51_errata_77(void) +{ + #ifndef NRF51_SERIES + return false; + #else + return false; + #endif +} + +static bool nrf51_errata_78(void) +{ + #ifndef NRF51_SERIES + return false; + #else + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422)\ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + if (var1 == 0x01) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x07ul: + return true; + case 0x08ul: + return true; + case 0x09ul: + return true; + case 0x0Aul: + return false; + case 0x0Bul: + return true; + case 0x0Cul: + return true; + case 0x0Dul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +#endif /* NRF51_ERRATAS_H */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf51_to_nrf52.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf51_to_nrf52.h new file mode 100644 index 000000000..49eeb1c98 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf51_to_nrf52.h @@ -0,0 +1,2364 @@ +/* + +Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF51_TO_NRF52_H +#define NRF51_TO_NRF52_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52 devices. + * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the + * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros + * from the nrf51_deprecated.h file. */ + + +/* IRQ */ +/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ +#ifndef UART0_IRQHandler + #define UART0_IRQHandler UARTE0_UART0_IRQHandler +#endif +#ifndef SPI0_TWI0_IRQHandler + #define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#endif +#ifndef SPI1_TWI1_IRQHandler + #define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#endif +#ifndef ADC_IRQHandler + #define ADC_IRQHandler SAADC_IRQHandler +#endif +#ifndef LPCOMP_IRQHandler + #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler +#endif +#ifndef SWI0_IRQHandler + #define SWI0_IRQHandler SWI0_EGU0_IRQHandler +#endif +#ifndef SWI1_IRQHandler + #define SWI1_IRQHandler SWI1_EGU1_IRQHandler +#endif +#ifndef SWI2_IRQHandler + #define SWI2_IRQHandler SWI2_EGU2_IRQHandler +#endif +#ifndef SWI3_IRQHandler + #define SWI3_IRQHandler SWI3_EGU3_IRQHandler +#endif +#ifndef SWI4_IRQHandler + #define SWI4_IRQHandler SWI4_EGU4_IRQHandler +#endif +#ifndef SWI5_IRQHandler + #define SWI5_IRQHandler SWI5_EGU5_IRQHandler +#endif + +#ifndef UART0_IRQn + #define UART0_IRQn UARTE0_UART0_IRQn +#endif +#ifndef SPI0_TWI0_IRQn + #define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn +#endif +#ifndef SPI1_TWI1_IRQn + #define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn +#endif +#ifndef ADC_IRQn + #define ADC_IRQn SAADC_IRQn +#endif +#ifndef LPCOMP_IRQn + #define LPCOMP_IRQn COMP_LPCOMP_IRQn +#endif +#ifndef SWI0_IRQn + #define SWI0_IRQn SWI0_EGU0_IRQn +#endif +#ifndef SWI1_IRQn + #define SWI1_IRQn SWI1_EGU1_IRQn +#endif +#ifndef SWI2_IRQn + #define SWI2_IRQn SWI2_EGU2_IRQn +#endif +#ifndef SWI3_IRQn + #define SWI3_IRQn SWI3_EGU3_IRQn +#endif +#ifndef SWI4_IRQn + #define SWI4_IRQn SWI4_EGU4_IRQn +#endif +#ifndef SWI5_IRQn + #define SWI5_IRQn SWI5_EGU5_IRQn +#endif + + +/* UICR */ +/* Register RBPCONF was renamed to APPROTECT. */ +#ifndef RBPCONF + #define RBPCONF APPROTECT +#endif + +#ifndef UICR_RBPCONF_PALL_Pos + #define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos +#endif +#ifndef UICR_RBPCONF_PALL_Msk + #define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk +#endif +#ifndef UICR_RBPCONF_PALL_Enabled + #define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled +#endif +#ifndef UICR_RBPCONF_PALL_Disabled + #define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled +#endif + +/* GPIO */ +/* GPIO port was renamed to P0. */ +#ifndef NRF_GPIO + #define NRF_GPIO NRF_P0 +#endif +#ifndef NRF_GPIO_BASE + #define NRF_GPIO_BASE NRF_P0_BASE +#endif + +/* QDEC */ +/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */ +#ifndef PSELLED + #define PSELLED PSEL.LED +#endif +#ifndef PSELA + #define PSELA PSEL.A +#endif +#ifndef PSELB + #define PSELB PSEL.B +#endif + + +/* SPIS */ +/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ +#ifndef PSELSCK + #define PSELSCK PSEL.SCK +#endif +#ifndef PSELMISO + #define PSELMISO PSEL.MISO +#endif +#ifndef PSELMOSI + #define PSELMOSI PSEL.MOSI +#endif +#ifndef PSELCSN + #define PSELCSN PSEL.CSN +#endif + +/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ +#ifndef RXDPTR + #define RXDPTR RXD.PTR +#endif +#ifndef MAXRX + #define MAXRX RXD.MAXCNT +#endif +#ifndef AMOUNTRX + #define AMOUNTRX RXD.AMOUNT +#endif + +#ifndef SPIS_MAXRX_MAXRX_Pos + #define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos +#endif +#ifndef SPIS_MAXRX_MAXRX_Msk + #define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk +#endif + +#ifndef SPIS_AMOUNTRX_AMOUNTRX_Pos + #define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos +#endif +#ifndef SPIS_AMOUNTRX_AMOUNTRX_Msk + #define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk +#endif + +/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ +#ifndef TXDPTR + #define TXDPTR TXD.PTR +#endif +#ifndef MAXTX + #define MAXTX TXD.MAXCNT +#endif +#ifndef AMOUNTTX + #define AMOUNTTX TXD.AMOUNT +#endif + +#ifndef SPIS_MAXTX_MAXTX_Pos + #define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos +#endif +#ifndef SPIS_MAXTX_MAXTX_Msk + #define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk +#endif + +#ifndef SPIS_AMOUNTTX_AMOUNTTX_Pos + #define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos +#endif +#ifndef SPIS_AMOUNTTX_AMOUNTTX_Msk + #define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk +#endif + +/* MPU */ +/* Part of MPU module was renamed BPROT, while the rest was eliminated. */ +#ifndef NRF_MPU + #define NRF_MPU NRF_BPROT +#endif + +/* Register DISABLEINDEBUG macros were affected. */ +#ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos + #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos +#endif +#ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk + #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk +#endif +#ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled + #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled +#endif +#ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled + #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled +#endif + +/* Registers PROTENSET0 and PROTENSET1 were affected and renamed as CONFIG0 and CONFIG1. */ +#ifndef PROTENSET0 + #define PROTENSET0 CONFIG0 +#endif +#ifndef PROTENSET1 + #define PROTENSET1 CONFIG1 +#endif + +#ifndef MPU_PROTENSET1_PROTREG63_Pos + #define MPU_PROTENSET1_PROTREG63_Pos BPROT_CONFIG1_REGION63_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG63_Msk + #define MPU_PROTENSET1_PROTREG63_Msk BPROT_CONFIG1_REGION63_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG63_Disabled + #define MPU_PROTENSET1_PROTREG63_Disabled BPROT_CONFIG1_REGION63_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG63_Enabled + #define MPU_PROTENSET1_PROTREG63_Enabled BPROT_CONFIG1_REGION63_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG63_Set + #define MPU_PROTENSET1_PROTREG63_Set BPROT_CONFIG1_REGION63_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG62_Pos + #define MPU_PROTENSET1_PROTREG62_Pos BPROT_CONFIG1_REGION62_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG62_Msk + #define MPU_PROTENSET1_PROTREG62_Msk BPROT_CONFIG1_REGION62_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG62_Disabled + #define MPU_PROTENSET1_PROTREG62_Disabled BPROT_CONFIG1_REGION62_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG62_Enabled + #define MPU_PROTENSET1_PROTREG62_Enabled BPROT_CONFIG1_REGION62_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG62_Set + #define MPU_PROTENSET1_PROTREG62_Set BPROT_CONFIG1_REGION62_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG61_Pos + #define MPU_PROTENSET1_PROTREG61_Pos BPROT_CONFIG1_REGION61_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG61_Msk + #define MPU_PROTENSET1_PROTREG61_Msk BPROT_CONFIG1_REGION61_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG61_Disabled + #define MPU_PROTENSET1_PROTREG61_Disabled BPROT_CONFIG1_REGION61_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG61_Enabled + #define MPU_PROTENSET1_PROTREG61_Enabled BPROT_CONFIG1_REGION61_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG61_Set + #define MPU_PROTENSET1_PROTREG61_Set BPROT_CONFIG1_REGION61_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG60_Pos + #define MPU_PROTENSET1_PROTREG60_Pos BPROT_CONFIG1_REGION60_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG60_Msk + #define MPU_PROTENSET1_PROTREG60_Msk BPROT_CONFIG1_REGION60_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG60_Disabled + #define MPU_PROTENSET1_PROTREG60_Disabled BPROT_CONFIG1_REGION60_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG60_Enabled + #define MPU_PROTENSET1_PROTREG60_Enabled BPROT_CONFIG1_REGION60_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG60_Set + #define MPU_PROTENSET1_PROTREG60_Set BPROT_CONFIG1_REGION60_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG59_Pos + #define MPU_PROTENSET1_PROTREG59_Pos BPROT_CONFIG1_REGION59_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG59_Msk + #define MPU_PROTENSET1_PROTREG59_Msk BPROT_CONFIG1_REGION59_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG59_Disabled + #define MPU_PROTENSET1_PROTREG59_Disabled BPROT_CONFIG1_REGION59_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG59_Enabled + #define MPU_PROTENSET1_PROTREG59_Enabled BPROT_CONFIG1_REGION59_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG59_Set + #define MPU_PROTENSET1_PROTREG59_Set BPROT_CONFIG1_REGION59_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG58_Pos + #define MPU_PROTENSET1_PROTREG58_Pos BPROT_CONFIG1_REGION58_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG58_Msk + #define MPU_PROTENSET1_PROTREG58_Msk BPROT_CONFIG1_REGION58_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG58_Disabled + #define MPU_PROTENSET1_PROTREG58_Disabled BPROT_CONFIG1_REGION58_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG58_Enabled + #define MPU_PROTENSET1_PROTREG58_Enabled BPROT_CONFIG1_REGION58_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG58_Set + #define MPU_PROTENSET1_PROTREG58_Set BPROT_CONFIG1_REGION58_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG57_Pos + #define MPU_PROTENSET1_PROTREG57_Pos BPROT_CONFIG1_REGION57_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG57_Msk + #define MPU_PROTENSET1_PROTREG57_Msk BPROT_CONFIG1_REGION57_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG57_Disabled + #define MPU_PROTENSET1_PROTREG57_Disabled BPROT_CONFIG1_REGION57_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG57_Enabled + #define MPU_PROTENSET1_PROTREG57_Enabled BPROT_CONFIG1_REGION57_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG57_Set + #define MPU_PROTENSET1_PROTREG57_Set BPROT_CONFIG1_REGION57_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG56_Pos + #define MPU_PROTENSET1_PROTREG56_Pos BPROT_CONFIG1_REGION56_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG56_Msk + #define MPU_PROTENSET1_PROTREG56_Msk BPROT_CONFIG1_REGION56_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG56_Disabled + #define MPU_PROTENSET1_PROTREG56_Disabled BPROT_CONFIG1_REGION56_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG56_Enabled + #define MPU_PROTENSET1_PROTREG56_Enabled BPROT_CONFIG1_REGION56_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG56_Set + #define MPU_PROTENSET1_PROTREG56_Set BPROT_CONFIG1_REGION56_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG55_Pos + #define MPU_PROTENSET1_PROTREG55_Pos BPROT_CONFIG1_REGION55_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG55_Msk + #define MPU_PROTENSET1_PROTREG55_Msk BPROT_CONFIG1_REGION55_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG55_Disabled + #define MPU_PROTENSET1_PROTREG55_Disabled BPROT_CONFIG1_REGION55_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG55_Enabled + #define MPU_PROTENSET1_PROTREG55_Enabled BPROT_CONFIG1_REGION55_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG55_Set + #define MPU_PROTENSET1_PROTREG55_Set BPROT_CONFIG1_REGION55_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG54_Pos + #define MPU_PROTENSET1_PROTREG54_Pos BPROT_CONFIG1_REGION54_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG54_Msk + #define MPU_PROTENSET1_PROTREG54_Msk BPROT_CONFIG1_REGION54_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG54_Disabled + #define MPU_PROTENSET1_PROTREG54_Disabled BPROT_CONFIG1_REGION54_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG54_Enabled + #define MPU_PROTENSET1_PROTREG54_Enabled BPROT_CONFIG1_REGION54_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG54_Set + #define MPU_PROTENSET1_PROTREG54_Set BPROT_CONFIG1_REGION54_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG53_Pos + #define MPU_PROTENSET1_PROTREG53_Pos BPROT_CONFIG1_REGION53_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG53_Msk + #define MPU_PROTENSET1_PROTREG53_Msk BPROT_CONFIG1_REGION53_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG53_Disabled + #define MPU_PROTENSET1_PROTREG53_Disabled BPROT_CONFIG1_REGION53_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG53_Enabled + #define MPU_PROTENSET1_PROTREG53_Enabled BPROT_CONFIG1_REGION53_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG53_Set + #define MPU_PROTENSET1_PROTREG53_Set BPROT_CONFIG1_REGION53_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG52_Pos + #define MPU_PROTENSET1_PROTREG52_Pos BPROT_CONFIG1_REGION52_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG52_Msk + #define MPU_PROTENSET1_PROTREG52_Msk BPROT_CONFIG1_REGION52_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG52_Disabled + #define MPU_PROTENSET1_PROTREG52_Disabled BPROT_CONFIG1_REGION52_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG52_Enabled + #define MPU_PROTENSET1_PROTREG52_Enabled BPROT_CONFIG1_REGION52_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG52_Set + #define MPU_PROTENSET1_PROTREG52_Set BPROT_CONFIG1_REGION52_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG51_Pos + #define MPU_PROTENSET1_PROTREG51_Pos BPROT_CONFIG1_REGION51_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG51_Msk + #define MPU_PROTENSET1_PROTREG51_Msk BPROT_CONFIG1_REGION51_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG51_Disabled + #define MPU_PROTENSET1_PROTREG51_Disabled BPROT_CONFIG1_REGION51_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG51_Enabled + #define MPU_PROTENSET1_PROTREG51_Enabled BPROT_CONFIG1_REGION51_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG51_Set + #define MPU_PROTENSET1_PROTREG51_Set BPROT_CONFIG1_REGION51_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG50_Pos + #define MPU_PROTENSET1_PROTREG50_Pos BPROT_CONFIG1_REGION50_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG50_Msk + #define MPU_PROTENSET1_PROTREG50_Msk BPROT_CONFIG1_REGION50_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG50_Disabled + #define MPU_PROTENSET1_PROTREG50_Disabled BPROT_CONFIG1_REGION50_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG50_Enabled + #define MPU_PROTENSET1_PROTREG50_Enabled BPROT_CONFIG1_REGION50_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG50_Set + #define MPU_PROTENSET1_PROTREG50_Set BPROT_CONFIG1_REGION50_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG49_Pos + #define MPU_PROTENSET1_PROTREG49_Pos BPROT_CONFIG1_REGION49_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG49_Msk + #define MPU_PROTENSET1_PROTREG49_Msk BPROT_CONFIG1_REGION49_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG49_Disabled + #define MPU_PROTENSET1_PROTREG49_Disabled BPROT_CONFIG1_REGION49_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG49_Enabled + #define MPU_PROTENSET1_PROTREG49_Enabled BPROT_CONFIG1_REGION49_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG49_Set + #define MPU_PROTENSET1_PROTREG49_Set BPROT_CONFIG1_REGION49_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG48_Pos + #define MPU_PROTENSET1_PROTREG48_Pos BPROT_CONFIG1_REGION48_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG48_Msk + #define MPU_PROTENSET1_PROTREG48_Msk BPROT_CONFIG1_REGION48_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG48_Disabled + #define MPU_PROTENSET1_PROTREG48_Disabled BPROT_CONFIG1_REGION48_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG48_Enabled + #define MPU_PROTENSET1_PROTREG48_Enabled BPROT_CONFIG1_REGION48_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG48_Set + #define MPU_PROTENSET1_PROTREG48_Set BPROT_CONFIG1_REGION48_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG47_Pos + #define MPU_PROTENSET1_PROTREG47_Pos BPROT_CONFIG1_REGION47_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG47_Msk + #define MPU_PROTENSET1_PROTREG47_Msk BPROT_CONFIG1_REGION47_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG47_Disabled + #define MPU_PROTENSET1_PROTREG47_Disabled BPROT_CONFIG1_REGION47_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG47_Enabled + #define MPU_PROTENSET1_PROTREG47_Enabled BPROT_CONFIG1_REGION47_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG47_Set + #define MPU_PROTENSET1_PROTREG47_Set BPROT_CONFIG1_REGION47_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG46_Pos + #define MPU_PROTENSET1_PROTREG46_Pos BPROT_CONFIG1_REGION46_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG46_Msk + #define MPU_PROTENSET1_PROTREG46_Msk BPROT_CONFIG1_REGION46_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG46_Disabled + #define MPU_PROTENSET1_PROTREG46_Disabled BPROT_CONFIG1_REGION46_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG46_Enabled + #define MPU_PROTENSET1_PROTREG46_Enabled BPROT_CONFIG1_REGION46_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG46_Set + #define MPU_PROTENSET1_PROTREG46_Set BPROT_CONFIG1_REGION46_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG45_Pos + #define MPU_PROTENSET1_PROTREG45_Pos BPROT_CONFIG1_REGION45_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG45_Msk + #define MPU_PROTENSET1_PROTREG45_Msk BPROT_CONFIG1_REGION45_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG45_Disabled + #define MPU_PROTENSET1_PROTREG45_Disabled BPROT_CONFIG1_REGION45_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG45_Enabled + #define MPU_PROTENSET1_PROTREG45_Enabled BPROT_CONFIG1_REGION45_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG45_Set + #define MPU_PROTENSET1_PROTREG45_Set BPROT_CONFIG1_REGION45_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG44_Pos + #define MPU_PROTENSET1_PROTREG44_Pos BPROT_CONFIG1_REGION44_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG44_Msk + #define MPU_PROTENSET1_PROTREG44_Msk BPROT_CONFIG1_REGION44_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG44_Disabled + #define MPU_PROTENSET1_PROTREG44_Disabled BPROT_CONFIG1_REGION44_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG44_Enabled + #define MPU_PROTENSET1_PROTREG44_Enabled BPROT_CONFIG1_REGION44_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG44_Set + #define MPU_PROTENSET1_PROTREG44_Set BPROT_CONFIG1_REGION44_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG43_Pos + #define MPU_PROTENSET1_PROTREG43_Pos BPROT_CONFIG1_REGION43_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG43_Msk + #define MPU_PROTENSET1_PROTREG43_Msk BPROT_CONFIG1_REGION43_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG43_Disabled + #define MPU_PROTENSET1_PROTREG43_Disabled BPROT_CONFIG1_REGION43_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG43_Enabled + #define MPU_PROTENSET1_PROTREG43_Enabled BPROT_CONFIG1_REGION43_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG43_Set + #define MPU_PROTENSET1_PROTREG43_Set BPROT_CONFIG1_REGION43_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG42_Pos + #define MPU_PROTENSET1_PROTREG42_Pos BPROT_CONFIG1_REGION42_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG42_Msk + #define MPU_PROTENSET1_PROTREG42_Msk BPROT_CONFIG1_REGION42_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG42_Disabled + #define MPU_PROTENSET1_PROTREG42_Disabled BPROT_CONFIG1_REGION42_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG42_Enabled + #define MPU_PROTENSET1_PROTREG42_Enabled BPROT_CONFIG1_REGION42_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG42_Set + #define MPU_PROTENSET1_PROTREG42_Set BPROT_CONFIG1_REGION42_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG41_Pos + #define MPU_PROTENSET1_PROTREG41_Pos BPROT_CONFIG1_REGION41_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG41_Msk + #define MPU_PROTENSET1_PROTREG41_Msk BPROT_CONFIG1_REGION41_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG41_Disabled + #define MPU_PROTENSET1_PROTREG41_Disabled BPROT_CONFIG1_REGION41_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG41_Enabled + #define MPU_PROTENSET1_PROTREG41_Enabled BPROT_CONFIG1_REGION41_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG41_Set + #define MPU_PROTENSET1_PROTREG41_Set BPROT_CONFIG1_REGION41_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG40_Pos + #define MPU_PROTENSET1_PROTREG40_Pos BPROT_CONFIG1_REGION40_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG40_Msk + #define MPU_PROTENSET1_PROTREG40_Msk BPROT_CONFIG1_REGION40_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG40_Disabled + #define MPU_PROTENSET1_PROTREG40_Disabled BPROT_CONFIG1_REGION40_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG40_Enabled + #define MPU_PROTENSET1_PROTREG40_Enabled BPROT_CONFIG1_REGION40_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG40_Set + #define MPU_PROTENSET1_PROTREG40_Set BPROT_CONFIG1_REGION40_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG39_Pos + #define MPU_PROTENSET1_PROTREG39_Pos BPROT_CONFIG1_REGION39_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG39_Msk + #define MPU_PROTENSET1_PROTREG39_Msk BPROT_CONFIG1_REGION39_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG39_Disabled + #define MPU_PROTENSET1_PROTREG39_Disabled BPROT_CONFIG1_REGION39_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG39_Enabled + #define MPU_PROTENSET1_PROTREG39_Enabled BPROT_CONFIG1_REGION39_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG39_Set + #define MPU_PROTENSET1_PROTREG39_Set BPROT_CONFIG1_REGION39_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG38_Pos + #define MPU_PROTENSET1_PROTREG38_Pos BPROT_CONFIG1_REGION38_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG38_Msk + #define MPU_PROTENSET1_PROTREG38_Msk BPROT_CONFIG1_REGION38_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG38_Disabled + #define MPU_PROTENSET1_PROTREG38_Disabled BPROT_CONFIG1_REGION38_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG38_Enabled + #define MPU_PROTENSET1_PROTREG38_Enabled BPROT_CONFIG1_REGION38_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG38_Set + #define MPU_PROTENSET1_PROTREG38_Set BPROT_CONFIG1_REGION38_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG37_Pos + #define MPU_PROTENSET1_PROTREG37_Pos BPROT_CONFIG1_REGION37_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG37_Msk + #define MPU_PROTENSET1_PROTREG37_Msk BPROT_CONFIG1_REGION37_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG37_Disabled + #define MPU_PROTENSET1_PROTREG37_Disabled BPROT_CONFIG1_REGION37_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG37_Enabled + #define MPU_PROTENSET1_PROTREG37_Enabled BPROT_CONFIG1_REGION37_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG37_Set + #define MPU_PROTENSET1_PROTREG37_Set BPROT_CONFIG1_REGION37_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG36_Pos + #define MPU_PROTENSET1_PROTREG36_Pos BPROT_CONFIG1_REGION36_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG36_Msk + #define MPU_PROTENSET1_PROTREG36_Msk BPROT_CONFIG1_REGION36_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG36_Disabled + #define MPU_PROTENSET1_PROTREG36_Disabled BPROT_CONFIG1_REGION36_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG36_Enabled + #define MPU_PROTENSET1_PROTREG36_Enabled BPROT_CONFIG1_REGION36_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG36_Set + #define MPU_PROTENSET1_PROTREG36_Set BPROT_CONFIG1_REGION36_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG35_Pos + #define MPU_PROTENSET1_PROTREG35_Pos BPROT_CONFIG1_REGION35_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG35_Msk + #define MPU_PROTENSET1_PROTREG35_Msk BPROT_CONFIG1_REGION35_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG35_Disabled + #define MPU_PROTENSET1_PROTREG35_Disabled BPROT_CONFIG1_REGION35_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG35_Enabled + #define MPU_PROTENSET1_PROTREG35_Enabled BPROT_CONFIG1_REGION35_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG35_Set + #define MPU_PROTENSET1_PROTREG35_Set BPROT_CONFIG1_REGION35_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG34_Pos + #define MPU_PROTENSET1_PROTREG34_Pos BPROT_CONFIG1_REGION34_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG34_Msk + #define MPU_PROTENSET1_PROTREG34_Msk BPROT_CONFIG1_REGION34_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG34_Disabled + #define MPU_PROTENSET1_PROTREG34_Disabled BPROT_CONFIG1_REGION34_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG34_Enabled + #define MPU_PROTENSET1_PROTREG34_Enabled BPROT_CONFIG1_REGION34_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG34_Set + #define MPU_PROTENSET1_PROTREG34_Set BPROT_CONFIG1_REGION34_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG33_Pos + #define MPU_PROTENSET1_PROTREG33_Pos BPROT_CONFIG1_REGION33_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG33_Msk + #define MPU_PROTENSET1_PROTREG33_Msk BPROT_CONFIG1_REGION33_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG33_Disabled + #define MPU_PROTENSET1_PROTREG33_Disabled BPROT_CONFIG1_REGION33_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG33_Enabled + #define MPU_PROTENSET1_PROTREG33_Enabled BPROT_CONFIG1_REGION33_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG33_Set + #define MPU_PROTENSET1_PROTREG33_Set BPROT_CONFIG1_REGION33_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG32_Pos + #define MPU_PROTENSET1_PROTREG32_Pos BPROT_CONFIG1_REGION32_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG32_Msk + #define MPU_PROTENSET1_PROTREG32_Msk BPROT_CONFIG1_REGION32_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG32_Disabled + #define MPU_PROTENSET1_PROTREG32_Disabled BPROT_CONFIG1_REGION32_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG32_Enabled + #define MPU_PROTENSET1_PROTREG32_Enabled BPROT_CONFIG1_REGION32_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG32_Set + #define MPU_PROTENSET1_PROTREG32_Set BPROT_CONFIG1_REGION32_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG31_Pos + #define MPU_PROTENSET0_PROTREG31_Pos BPROT_CONFIG0_REGION31_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG31_Msk + #define MPU_PROTENSET0_PROTREG31_Msk BPROT_CONFIG0_REGION31_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG31_Disabled + #define MPU_PROTENSET0_PROTREG31_Disabled BPROT_CONFIG0_REGION31_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG31_Enabled + #define MPU_PROTENSET0_PROTREG31_Enabled BPROT_CONFIG0_REGION31_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG31_Set + #define MPU_PROTENSET0_PROTREG31_Set BPROT_CONFIG0_REGION31_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG30_Pos + #define MPU_PROTENSET0_PROTREG30_Pos BPROT_CONFIG0_REGION30_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG30_Msk + #define MPU_PROTENSET0_PROTREG30_Msk BPROT_CONFIG0_REGION30_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG30_Disabled + #define MPU_PROTENSET0_PROTREG30_Disabled BPROT_CONFIG0_REGION30_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG30_Enabled + #define MPU_PROTENSET0_PROTREG30_Enabled BPROT_CONFIG0_REGION30_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG30_Set + #define MPU_PROTENSET0_PROTREG30_Set BPROT_CONFIG0_REGION30_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG29_Pos + #define MPU_PROTENSET0_PROTREG29_Pos BPROT_CONFIG0_REGION29_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG29_Msk + #define MPU_PROTENSET0_PROTREG29_Msk BPROT_CONFIG0_REGION29_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG29_Disabled + #define MPU_PROTENSET0_PROTREG29_Disabled BPROT_CONFIG0_REGION29_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG29_Enabled + #define MPU_PROTENSET0_PROTREG29_Enabled BPROT_CONFIG0_REGION29_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG29_Set + #define MPU_PROTENSET0_PROTREG29_Set BPROT_CONFIG0_REGION29_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG28_Pos + #define MPU_PROTENSET0_PROTREG28_Pos BPROT_CONFIG0_REGION28_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG28_Msk + #define MPU_PROTENSET0_PROTREG28_Msk BPROT_CONFIG0_REGION28_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG28_Disabled + #define MPU_PROTENSET0_PROTREG28_Disabled BPROT_CONFIG0_REGION28_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG28_Enabled + #define MPU_PROTENSET0_PROTREG28_Enabled BPROT_CONFIG0_REGION28_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG28_Set + #define MPU_PROTENSET0_PROTREG28_Set BPROT_CONFIG0_REGION28_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG27_Pos + #define MPU_PROTENSET0_PROTREG27_Pos BPROT_CONFIG0_REGION27_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG27_Msk + #define MPU_PROTENSET0_PROTREG27_Msk BPROT_CONFIG0_REGION27_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG27_Disabled + #define MPU_PROTENSET0_PROTREG27_Disabled BPROT_CONFIG0_REGION27_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG27_Enabled + #define MPU_PROTENSET0_PROTREG27_Enabled BPROT_CONFIG0_REGION27_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG27_Set + #define MPU_PROTENSET0_PROTREG27_Set BPROT_CONFIG0_REGION27_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG26_Pos + #define MPU_PROTENSET0_PROTREG26_Pos BPROT_CONFIG0_REGION26_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG26_Msk + #define MPU_PROTENSET0_PROTREG26_Msk BPROT_CONFIG0_REGION26_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG26_Disabled + #define MPU_PROTENSET0_PROTREG26_Disabled BPROT_CONFIG0_REGION26_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG26_Enabled + #define MPU_PROTENSET0_PROTREG26_Enabled BPROT_CONFIG0_REGION26_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG26_Set + #define MPU_PROTENSET0_PROTREG26_Set BPROT_CONFIG0_REGION26_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG25_Pos + #define MPU_PROTENSET0_PROTREG25_Pos BPROT_CONFIG0_REGION25_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG25_Msk + #define MPU_PROTENSET0_PROTREG25_Msk BPROT_CONFIG0_REGION25_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG25_Disabled + #define MPU_PROTENSET0_PROTREG25_Disabled BPROT_CONFIG0_REGION25_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG25_Enabled + #define MPU_PROTENSET0_PROTREG25_Enabled BPROT_CONFIG0_REGION25_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG25_Set + #define MPU_PROTENSET0_PROTREG25_Set BPROT_CONFIG0_REGION25_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG24_Pos + #define MPU_PROTENSET0_PROTREG24_Pos BPROT_CONFIG0_REGION24_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG24_Msk + #define MPU_PROTENSET0_PROTREG24_Msk BPROT_CONFIG0_REGION24_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG24_Disabled + #define MPU_PROTENSET0_PROTREG24_Disabled BPROT_CONFIG0_REGION24_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG24_Enabled + #define MPU_PROTENSET0_PROTREG24_Enabled BPROT_CONFIG0_REGION24_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG24_Set + #define MPU_PROTENSET0_PROTREG24_Set BPROT_CONFIG0_REGION24_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG23_Pos + #define MPU_PROTENSET0_PROTREG23_Pos BPROT_CONFIG0_REGION23_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG23_Msk + #define MPU_PROTENSET0_PROTREG23_Msk BPROT_CONFIG0_REGION23_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG23_Disabled + #define MPU_PROTENSET0_PROTREG23_Disabled BPROT_CONFIG0_REGION23_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG23_Enabled + #define MPU_PROTENSET0_PROTREG23_Enabled BPROT_CONFIG0_REGION23_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG23_Set + #define MPU_PROTENSET0_PROTREG23_Set BPROT_CONFIG0_REGION23_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG22_Pos + #define MPU_PROTENSET0_PROTREG22_Pos BPROT_CONFIG0_REGION22_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG22_Msk + #define MPU_PROTENSET0_PROTREG22_Msk BPROT_CONFIG0_REGION22_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG22_Disabled + #define MPU_PROTENSET0_PROTREG22_Disabled BPROT_CONFIG0_REGION22_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG22_Enabled + #define MPU_PROTENSET0_PROTREG22_Enabled BPROT_CONFIG0_REGION22_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG22_Set + #define MPU_PROTENSET0_PROTREG22_Set BPROT_CONFIG0_REGION22_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG21_Pos + #define MPU_PROTENSET0_PROTREG21_Pos BPROT_CONFIG0_REGION21_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG21_Msk + #define MPU_PROTENSET0_PROTREG21_Msk BPROT_CONFIG0_REGION21_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG21_Disabled + #define MPU_PROTENSET0_PROTREG21_Disabled BPROT_CONFIG0_REGION21_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG21_Enabled + #define MPU_PROTENSET0_PROTREG21_Enabled BPROT_CONFIG0_REGION21_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG21_Set + #define MPU_PROTENSET0_PROTREG21_Set BPROT_CONFIG0_REGION21_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG20_Pos + #define MPU_PROTENSET0_PROTREG20_Pos BPROT_CONFIG0_REGION20_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG20_Msk + #define MPU_PROTENSET0_PROTREG20_Msk BPROT_CONFIG0_REGION20_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG20_Disabled + #define MPU_PROTENSET0_PROTREG20_Disabled BPROT_CONFIG0_REGION20_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG20_Enabled + #define MPU_PROTENSET0_PROTREG20_Enabled BPROT_CONFIG0_REGION20_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG20_Set + #define MPU_PROTENSET0_PROTREG20_Set BPROT_CONFIG0_REGION20_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG19_Pos + #define MPU_PROTENSET0_PROTREG19_Pos BPROT_CONFIG0_REGION19_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG19_Msk + #define MPU_PROTENSET0_PROTREG19_Msk BPROT_CONFIG0_REGION19_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG19_Disabled + #define MPU_PROTENSET0_PROTREG19_Disabled BPROT_CONFIG0_REGION19_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG19_Enabled + #define MPU_PROTENSET0_PROTREG19_Enabled BPROT_CONFIG0_REGION19_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG19_Set + #define MPU_PROTENSET0_PROTREG19_Set BPROT_CONFIG0_REGION19_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG18_Pos + #define MPU_PROTENSET0_PROTREG18_Pos BPROT_CONFIG0_REGION18_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG18_Msk + #define MPU_PROTENSET0_PROTREG18_Msk BPROT_CONFIG0_REGION18_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG18_Disabled + #define MPU_PROTENSET0_PROTREG18_Disabled BPROT_CONFIG0_REGION18_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG18_Enabled + #define MPU_PROTENSET0_PROTREG18_Enabled BPROT_CONFIG0_REGION18_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG18_Set + #define MPU_PROTENSET0_PROTREG18_Set BPROT_CONFIG0_REGION18_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG17_Pos + #define MPU_PROTENSET0_PROTREG17_Pos BPROT_CONFIG0_REGION17_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG17_Msk + #define MPU_PROTENSET0_PROTREG17_Msk BPROT_CONFIG0_REGION17_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG17_Disabled + #define MPU_PROTENSET0_PROTREG17_Disabled BPROT_CONFIG0_REGION17_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG17_Enabled + #define MPU_PROTENSET0_PROTREG17_Enabled BPROT_CONFIG0_REGION17_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG17_Set + #define MPU_PROTENSET0_PROTREG17_Set BPROT_CONFIG0_REGION17_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG16_Pos + #define MPU_PROTENSET0_PROTREG16_Pos BPROT_CONFIG0_REGION16_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG16_Msk + #define MPU_PROTENSET0_PROTREG16_Msk BPROT_CONFIG0_REGION16_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG16_Disabled + #define MPU_PROTENSET0_PROTREG16_Disabled BPROT_CONFIG0_REGION16_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG16_Enabled + #define MPU_PROTENSET0_PROTREG16_Enabled BPROT_CONFIG0_REGION16_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG16_Set + #define MPU_PROTENSET0_PROTREG16_Set BPROT_CONFIG0_REGION16_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG16_Set + #define MPU_PROTENSET0_PROTREG15_Pos BPROT_CONFIG0_REGION15_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG15_Msk + #define MPU_PROTENSET0_PROTREG15_Msk BPROT_CONFIG0_REGION15_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG15_Disabled + #define MPU_PROTENSET0_PROTREG15_Disabled BPROT_CONFIG0_REGION15_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG15_Enabled + #define MPU_PROTENSET0_PROTREG15_Enabled BPROT_CONFIG0_REGION15_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG15_Set + #define MPU_PROTENSET0_PROTREG15_Set BPROT_CONFIG0_REGION15_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG14_Pos + #define MPU_PROTENSET0_PROTREG14_Pos BPROT_CONFIG0_REGION14_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG14_Msk + #define MPU_PROTENSET0_PROTREG14_Msk BPROT_CONFIG0_REGION14_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG14_Disabled + #define MPU_PROTENSET0_PROTREG14_Disabled BPROT_CONFIG0_REGION14_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG14_Enabled + #define MPU_PROTENSET0_PROTREG14_Enabled BPROT_CONFIG0_REGION14_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG14_Set + #define MPU_PROTENSET0_PROTREG14_Set BPROT_CONFIG0_REGION14_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG13_Pos + #define MPU_PROTENSET0_PROTREG13_Pos BPROT_CONFIG0_REGION13_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG13_Msk + #define MPU_PROTENSET0_PROTREG13_Msk BPROT_CONFIG0_REGION13_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG13_Disabled + #define MPU_PROTENSET0_PROTREG13_Disabled BPROT_CONFIG0_REGION13_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG13_Enabled + #define MPU_PROTENSET0_PROTREG13_Enabled BPROT_CONFIG0_REGION13_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG13_Set + #define MPU_PROTENSET0_PROTREG13_Set BPROT_CONFIG0_REGION13_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG12_Pos + #define MPU_PROTENSET0_PROTREG12_Pos BPROT_CONFIG0_REGION12_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG12_Msk + #define MPU_PROTENSET0_PROTREG12_Msk BPROT_CONFIG0_REGION12_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG12_Disabled + #define MPU_PROTENSET0_PROTREG12_Disabled BPROT_CONFIG0_REGION12_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG12_Enabled + #define MPU_PROTENSET0_PROTREG12_Enabled BPROT_CONFIG0_REGION12_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG12_Set + #define MPU_PROTENSET0_PROTREG12_Set BPROT_CONFIG0_REGION12_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG11_Pos + #define MPU_PROTENSET0_PROTREG11_Pos BPROT_CONFIG0_REGION11_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG11_Msk + #define MPU_PROTENSET0_PROTREG11_Msk BPROT_CONFIG0_REGION11_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG11_Disabled + #define MPU_PROTENSET0_PROTREG11_Disabled BPROT_CONFIG0_REGION11_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG11_Enabled + #define MPU_PROTENSET0_PROTREG11_Enabled BPROT_CONFIG0_REGION11_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG11_Set + #define MPU_PROTENSET0_PROTREG11_Set BPROT_CONFIG0_REGION11_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG10_Pos + #define MPU_PROTENSET0_PROTREG10_Pos BPROT_CONFIG0_REGION10_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG10_Msk + #define MPU_PROTENSET0_PROTREG10_Msk BPROT_CONFIG0_REGION10_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG10_Disabled + #define MPU_PROTENSET0_PROTREG10_Disabled BPROT_CONFIG0_REGION10_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG10_Enabled + #define MPU_PROTENSET0_PROTREG10_Enabled BPROT_CONFIG0_REGION10_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG10_Set + #define MPU_PROTENSET0_PROTREG10_Set BPROT_CONFIG0_REGION10_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG9_Pos + #define MPU_PROTENSET0_PROTREG9_Pos BPROT_CONFIG0_REGION9_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG9_Msk + #define MPU_PROTENSET0_PROTREG9_Msk BPROT_CONFIG0_REGION9_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG9_Disabled + #define MPU_PROTENSET0_PROTREG9_Disabled BPROT_CONFIG0_REGION9_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG9_Enabled + #define MPU_PROTENSET0_PROTREG9_Enabled BPROT_CONFIG0_REGION9_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG9_Set + #define MPU_PROTENSET0_PROTREG9_Set BPROT_CONFIG0_REGION9_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG8_Pos + #define MPU_PROTENSET0_PROTREG8_Pos BPROT_CONFIG0_REGION8_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG8_Msk + #define MPU_PROTENSET0_PROTREG8_Msk BPROT_CONFIG0_REGION8_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG8_Disabled + #define MPU_PROTENSET0_PROTREG8_Disabled BPROT_CONFIG0_REGION8_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG8_Enabled + #define MPU_PROTENSET0_PROTREG8_Enabled BPROT_CONFIG0_REGION8_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG8_Set + #define MPU_PROTENSET0_PROTREG8_Set BPROT_CONFIG0_REGION8_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG7_Pos + #define MPU_PROTENSET0_PROTREG7_Pos BPROT_CONFIG0_REGION7_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG7_Msk + #define MPU_PROTENSET0_PROTREG7_Msk BPROT_CONFIG0_REGION7_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG7_Disabled + #define MPU_PROTENSET0_PROTREG7_Disabled BPROT_CONFIG0_REGION7_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG7_Enabled + #define MPU_PROTENSET0_PROTREG7_Enabled BPROT_CONFIG0_REGION7_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG7_Set + #define MPU_PROTENSET0_PROTREG7_Set BPROT_CONFIG0_REGION7_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG6_Pos + #define MPU_PROTENSET0_PROTREG6_Pos BPROT_CONFIG0_REGION6_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG6_Msk + #define MPU_PROTENSET0_PROTREG6_Msk BPROT_CONFIG0_REGION6_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG6_Disabled + #define MPU_PROTENSET0_PROTREG6_Disabled BPROT_CONFIG0_REGION6_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG6_Enabled + #define MPU_PROTENSET0_PROTREG6_Enabled BPROT_CONFIG0_REGION6_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG6_Set + #define MPU_PROTENSET0_PROTREG6_Set BPROT_CONFIG0_REGION6_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG5_Pos + #define MPU_PROTENSET0_PROTREG5_Pos BPROT_CONFIG0_REGION5_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG5_Msk + #define MPU_PROTENSET0_PROTREG5_Msk BPROT_CONFIG0_REGION5_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG5_Disabled + #define MPU_PROTENSET0_PROTREG5_Disabled BPROT_CONFIG0_REGION5_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG5_Enabled + #define MPU_PROTENSET0_PROTREG5_Enabled BPROT_CONFIG0_REGION5_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG5_Set + #define MPU_PROTENSET0_PROTREG5_Set BPROT_CONFIG0_REGION5_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG4_Pos + #define MPU_PROTENSET0_PROTREG4_Pos BPROT_CONFIG0_REGION4_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG4_Msk + #define MPU_PROTENSET0_PROTREG4_Msk BPROT_CONFIG0_REGION4_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG4_Disabled + #define MPU_PROTENSET0_PROTREG4_Disabled BPROT_CONFIG0_REGION4_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG4_Enabled + #define MPU_PROTENSET0_PROTREG4_Enabled BPROT_CONFIG0_REGION4_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG4_Set + #define MPU_PROTENSET0_PROTREG4_Set BPROT_CONFIG0_REGION4_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG3_Pos + #define MPU_PROTENSET0_PROTREG3_Pos BPROT_CONFIG0_REGION3_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG3_Msk + #define MPU_PROTENSET0_PROTREG3_Msk BPROT_CONFIG0_REGION3_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG3_Disabled + #define MPU_PROTENSET0_PROTREG3_Disabled BPROT_CONFIG0_REGION3_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG3_Enabled + #define MPU_PROTENSET0_PROTREG3_Enabled BPROT_CONFIG0_REGION3_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG3_Set + #define MPU_PROTENSET0_PROTREG3_Set BPROT_CONFIG0_REGION3_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG2_Pos + #define MPU_PROTENSET0_PROTREG2_Pos BPROT_CONFIG0_REGION2_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG2_Msk + #define MPU_PROTENSET0_PROTREG2_Msk BPROT_CONFIG0_REGION2_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG2_Disabled + #define MPU_PROTENSET0_PROTREG2_Disabled BPROT_CONFIG0_REGION2_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG2_Enabled + #define MPU_PROTENSET0_PROTREG2_Enabled BPROT_CONFIG0_REGION2_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG2_Set + #define MPU_PROTENSET0_PROTREG2_Set BPROT_CONFIG0_REGION2_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG1_Pos + #define MPU_PROTENSET0_PROTREG1_Pos BPROT_CONFIG0_REGION1_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG1_Msk + #define MPU_PROTENSET0_PROTREG1_Msk BPROT_CONFIG0_REGION1_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG1_Disabled + #define MPU_PROTENSET0_PROTREG1_Disabled BPROT_CONFIG0_REGION1_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG1_Enabled + #define MPU_PROTENSET0_PROTREG1_Enabled BPROT_CONFIG0_REGION1_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG1_Set + #define MPU_PROTENSET0_PROTREG1_Set BPROT_CONFIG0_REGION1_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG0_Pos + #define MPU_PROTENSET0_PROTREG0_Pos BPROT_CONFIG0_REGION0_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG0_Msk + #define MPU_PROTENSET0_PROTREG0_Msk BPROT_CONFIG0_REGION0_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG0_Disabled + #define MPU_PROTENSET0_PROTREG0_Disabled BPROT_CONFIG0_REGION0_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG0_Enabled + #define MPU_PROTENSET0_PROTREG0_Enabled BPROT_CONFIG0_REGION0_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG0_Set + #define MPU_PROTENSET0_PROTREG0_Set BPROT_CONFIG0_REGION0_Enabled +#endif + + +/* From nrf51_deprecated.h */ + +/* NVMC */ +/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ +#ifndef ERASEPROTECTEDPAGE + #define ERASEPROTECTEDPAGE ERASEPCR0 +#endif + + +/* IRQ */ +/* COMP module was eliminated. Adapted to nrf52 headers. */ +#ifndef LPCOMP_COMP_IRQHandler + #define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler +#endif +#ifndef LPCOMP_COMP_IRQn + #define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn +#endif + + +/* REFSEL register redefined enumerated values and added some more. */ +#ifndef LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd +#endif + +/* RADIO */ +/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ +#ifndef RADIO_CRCCNF_SKIP_ADDR_Pos + #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos +#endif +#ifndef RADIO_CRCCNF_SKIP_ADDR_Msk + #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk +#endif +#ifndef RADIO_CRCCNF_SKIP_ADDR_Include + #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include +#endif +#ifndef RADIO_CRCCNF_SKIP_ADDR_Skip + #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip +#endif + + +/* FICR */ +/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ +#ifndef DEVICEID0 + #define DEVICEID0 DEVICEID[0] +#endif +#ifndef DEVICEID1 + #define DEVICEID1 DEVICEID[1] +#endif + +/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ +#ifndef ER0 + #define ER0 ER[0] +#endif +#ifndef ER1 + #define ER1 ER[1] +#endif +#ifndef ER2 + #define ER2 ER[2] +#endif +#ifndef ER3 + #define ER3 ER[3] +#endif + +/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ +#ifndef IR0 + #define IR0 IR[0] +#endif +#ifndef IR1 + #define IR1 IR[1] +#endif +#ifndef IR2 + #define IR2 IR[2] +#endif +#ifndef IR3 + #define IR3 IR[3] +#endif + +/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ +#ifndef DEVICEADDR0 + #define DEVICEADDR0 DEVICEADDR[0] +#endif +#ifndef DEVICEADDR1 + #define DEVICEADDR1 DEVICEADDR[1] +#endif + + +/* PPI */ +/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ +#ifndef TASKS_CHG0EN + #define TASKS_CHG0EN TASKS_CHG[0].EN +#endif +#ifndef TASKS_CHG0DIS + #define TASKS_CHG0DIS TASKS_CHG[0].DIS +#endif +#ifndef TASKS_CHG1EN + #define TASKS_CHG1EN TASKS_CHG[1].EN +#endif +#ifndef TASKS_CHG1DIS + #define TASKS_CHG1DIS TASKS_CHG[1].DIS +#endif +#ifndef TASKS_CHG2EN + #define TASKS_CHG2EN TASKS_CHG[2].EN +#endif +#ifndef TASKS_CHG2DIS + #define TASKS_CHG2DIS TASKS_CHG[2].DIS +#endif +#ifndef TASKS_CHG3EN + #define TASKS_CHG3EN TASKS_CHG[3].EN +#endif +#ifndef TASKS_CHG3DIS + #define TASKS_CHG3DIS TASKS_CHG[3].DIS +#endif + +/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ +#ifndef CH0_EEP + #define CH0_EEP CH[0].EEP +#endif +#ifndef CH0_TEP + #define CH0_TEP CH[0].TEP +#endif +#ifndef CH1_EEP + #define CH1_EEP CH[1].EEP +#endif +#ifndef CH1_TEP + #define CH1_TEP CH[1].TEP +#endif +#ifndef CH2_EEP + #define CH2_EEP CH[2].EEP +#endif +#ifndef CH2_TEP + #define CH2_TEP CH[2].TEP +#endif +#ifndef CH3_EEP + #define CH3_EEP CH[3].EEP +#endif +#ifndef CH3_TEP + #define CH3_TEP CH[3].TEP +#endif +#ifndef CH4_EEP + #define CH4_EEP CH[4].EEP +#endif +#ifndef CH4_TEP + #define CH4_TEP CH[4].TEP +#endif +#ifndef CH5_EEP + #define CH5_EEP CH[5].EEP +#endif +#ifndef CH5_TEP + #define CH5_TEP CH[5].TEP +#endif +#ifndef CH6_EEP + #define CH6_EEP CH[6].EEP +#endif +#ifndef CH6_TEP + #define CH6_TEP CH[6].TEP +#endif +#ifndef CH7_EEP + #define CH7_EEP CH[7].EEP +#endif +#ifndef CH7_TEP + #define CH7_TEP CH[7].TEP +#endif +#ifndef CH8_EEP + #define CH8_EEP CH[8].EEP +#endif +#ifndef CH8_TEP + #define CH8_TEP CH[8].TEP +#endif +#ifndef CH9_EEP + #define CH9_EEP CH[9].EEP +#endif +#ifndef CH9_TEP + #define CH9_TEP CH[9].TEP +#endif +#ifndef CH10_EEP + #define CH10_EEP CH[10].EEP +#endif +#ifndef CH10_TEP + #define CH10_TEP CH[10].TEP +#endif +#ifndef CH11_EEP + #define CH11_EEP CH[11].EEP +#endif +#ifndef CH11_TEP + #define CH11_TEP CH[11].TEP +#endif +#ifndef CH12_EEP + #define CH12_EEP CH[12].EEP +#endif +#ifndef CH12_TEP + #define CH12_TEP CH[12].TEP +#endif +#ifndef CH13_EEP + #define CH13_EEP CH[13].EEP +#endif +#ifndef CH13_TEP + #define CH13_TEP CH[13].TEP +#endif +#ifndef CH14_EEP + #define CH14_EEP CH[14].EEP +#endif +#ifndef CH14_TEP + #define CH14_TEP CH[14].TEP +#endif +#ifndef CH15_EEP + #define CH15_EEP CH[15].EEP +#endif +#ifndef CH15_TEP + #define CH15_TEP CH[15].TEP +#endif + +/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ +#ifndef CHG0 + #define CHG0 CHG[0] +#endif +#ifndef CHG1 + #define CHG1 CHG[1] +#endif +#ifndef CHG2 + #define CHG2 CHG[2] +#endif +#ifndef CHG3 + #define CHG3 CHG[3] +#endif + +/* All bitfield macros for the CHGx registers therefore changed name. */ +#ifndef PPI_CHG0_CH15_Pos + #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG0_CH15_Msk + #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG0_CH15_Excluded + #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG0_CH15_Included + #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG0_CH14_Pos + #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG0_CH14_Msk + #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG0_CH14_Excluded + #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG0_CH14_Included + #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG0_CH13_Pos + #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG0_CH13_Msk + #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG0_CH13_Excluded + #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG0_CH13_Included + #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG0_CH12_Pos + #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG0_CH12_Msk + #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG0_CH12_Excluded + #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG0_CH12_Included + #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG0_CH11_Pos + #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG0_CH11_Msk + #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG0_CH11_Excluded + #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG0_CH11_Included + #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG0_CH10_Pos + #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG0_CH10_Msk + #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG0_CH10_Excluded + #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG0_CH10_Included + #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG0_CH9_Pos + #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG0_CH9_Msk + #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG0_CH9_Excluded + #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG0_CH9_Included + #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG0_CH8_Pos + #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG0_CH8_Msk + #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG0_CH8_Excluded + #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG0_CH8_Included + #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG0_CH7_Pos + #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG0_CH7_Msk + #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG0_CH7_Excluded + #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG0_CH7_Included + #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG0_CH6_Pos + #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG0_CH6_Msk + #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG0_CH6_Excluded + #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG0_CH6_Included + #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG0_CH5_Pos + #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG0_CH5_Msk + #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG0_CH5_Excluded + #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG0_CH5_Included + #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG0_CH4_Pos + #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG0_CH4_Msk + #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG0_CH4_Excluded + #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG0_CH4_Included + #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG0_CH3_Pos + #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG0_CH3_Msk + #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG0_CH3_Excluded + #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG0_CH3_Included + #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG0_CH2_Pos + #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG0_CH2_Msk + #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG0_CH2_Excluded + #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG0_CH2_Included + #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG0_CH1_Pos + #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG0_CH1_Msk + #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG0_CH1_Excluded + #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG0_CH1_Included + #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG0_CH0_Pos + #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG0_CH0_Msk + #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG0_CH0_Excluded + #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG0_CH0_Included + #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included +#endif + +#ifndef PPI_CHG1_CH15_Pos + #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG1_CH15_Msk + #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG1_CH15_Excluded + #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG1_CH15_Included + #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG1_CH14_Pos + #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG1_CH14_Msk + #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG1_CH14_Excluded + #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG1_CH14_Included + #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG1_CH13_Pos + #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG1_CH13_Msk + #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG1_CH13_Excluded + #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG1_CH13_Included + #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG1_CH12_Pos + #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG1_CH12_Msk + #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG1_CH12_Excluded + #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG1_CH12_Included + #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG1_CH11_Pos + #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG1_CH11_Msk + #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG1_CH11_Excluded + #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG1_CH11_Included + #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG1_CH10_Pos + #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG1_CH10_Msk + #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG1_CH10_Excluded + #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG1_CH10_Included + #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG1_CH9_Pos + #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG1_CH9_Msk + #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG1_CH9_Excluded + #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG1_CH9_Included + #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG1_CH8_Pos + #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG1_CH8_Msk + #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG1_CH8_Excluded + #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG1_CH8_Included + #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG1_CH7_Pos + #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG1_CH7_Msk + #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG1_CH7_Excluded + #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG1_CH7_Included + #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG1_CH6_Pos + #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG1_CH6_Msk + #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG1_CH6_Excluded + #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG1_CH6_Included + #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG1_CH5_Pos + #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG1_CH5_Msk + #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG1_CH5_Excluded + #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG1_CH5_Included + #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG1_CH4_Pos + #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG1_CH4_Msk + #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG1_CH4_Excluded + #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG1_CH4_Included + #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG1_CH3_Pos + #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG1_CH3_Msk + #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG1_CH3_Excluded + #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG1_CH3_Included + #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG1_CH2_Pos + #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG1_CH2_Msk + #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG1_CH2_Excluded + #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG1_CH2_Included + #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG1_CH1_Pos + #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG1_CH1_Msk + #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG1_CH1_Excluded + #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG1_CH1_Included + #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG1_CH0_Pos + #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG1_CH0_Msk + #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG1_CH0_Excluded + #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG1_CH0_Included + #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included +#endif + +#ifndef PPI_CHG2_CH15_Pos + #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG2_CH15_Msk + #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG2_CH15_Excluded + #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG2_CH15_Included + #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG2_CH14_Pos + #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG2_CH14_Msk + #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG2_CH14_Excluded + #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG2_CH14_Included + #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG2_CH13_Pos + #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG2_CH13_Msk + #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG2_CH13_Excluded + #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG2_CH13_Included + #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG2_CH12_Pos + #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG2_CH12_Msk + #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG2_CH12_Excluded + #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG2_CH12_Included + #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG2_CH11_Pos + #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG2_CH11_Msk + #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG2_CH11_Excluded + #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG2_CH11_Included + #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG2_CH10_Pos + #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG2_CH10_Msk + #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG2_CH10_Excluded + #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG2_CH10_Included + #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG2_CH9_Pos + #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG2_CH9_Msk + #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG2_CH9_Excluded + #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG2_CH9_Included + #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG2_CH8_Pos + #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG2_CH8_Msk + #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG2_CH8_Excluded + #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG2_CH8_Included + #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG2_CH7_Pos + #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG2_CH7_Msk + #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG2_CH7_Excluded + #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG2_CH7_Included + #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG2_CH6_Pos + #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG2_CH6_Msk + #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG2_CH6_Excluded + #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG2_CH6_Included + #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG2_CH5_Pos + #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG2_CH5_Msk + #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG2_CH5_Excluded + #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG2_CH5_Included + #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG2_CH4_Pos + #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG2_CH4_Msk + #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG2_CH4_Excluded + #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG2_CH4_Included + #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG2_CH3_Pos + #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG2_CH3_Msk + #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG2_CH3_Excluded + #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG2_CH3_Included + #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG2_CH2_Pos + #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG2_CH2_Msk + #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG2_CH2_Excluded + #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG2_CH2_Included + #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG2_CH1_Pos + #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG2_CH1_Msk + #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG2_CH1_Excluded + #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG2_CH1_Included + #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG2_CH0_Pos + #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG2_CH0_Msk + #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG2_CH0_Excluded + #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG2_CH0_Included + #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included +#endif + +#ifndef PPI_CHG3_CH15_Pos + #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG3_CH15_Msk + #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG3_CH15_Excluded + #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG3_CH15_Included + #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG3_CH14_Pos + #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG3_CH14_Msk + #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG3_CH14_Excluded + #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG3_CH14_Included + #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG3_CH13_Pos + #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG3_CH13_Msk + #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG3_CH13_Excluded + #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG3_CH13_Included + #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG3_CH12_Pos + #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG3_CH12_Msk + #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG3_CH12_Excluded + #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG3_CH12_Included + #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG3_CH11_Pos + #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG3_CH11_Msk + #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG3_CH11_Excluded + #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG3_CH11_Included + #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG3_CH10_Pos + #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG3_CH10_Msk + #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG3_CH10_Excluded + #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG3_CH10_Included + #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG3_CH9_Pos + #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG3_CH9_Msk + #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG3_CH9_Excluded + #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG3_CH9_Included + #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG3_CH8_Pos + #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG3_CH8_Msk + #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG3_CH8_Excluded + #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG3_CH8_Included + #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG3_CH7_Pos + #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG3_CH7_Msk + #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG3_CH7_Excluded + #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG3_CH7_Included + #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG3_CH6_Pos + #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG3_CH6_Msk + #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG3_CH6_Excluded + #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG3_CH6_Included + #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG3_CH5_Pos + #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG3_CH5_Msk + #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG3_CH5_Excluded + #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG3_CH5_Included + #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG3_CH4_Pos + #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG3_CH4_Msk + #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG3_CH4_Excluded + #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG3_CH4_Included + #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG3_CH3_Pos + #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG3_CH3_Msk + #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG3_CH3_Excluded + #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG3_CH3_Included + #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG3_CH2_Pos + #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG3_CH2_Msk + #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG3_CH2_Excluded + #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG3_CH2_Included + #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG3_CH1_Pos + #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG3_CH1_Msk + #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG3_CH1_Excluded + #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG3_CH1_Included + #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG3_CH0_Pos + #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG3_CH0_Msk + #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG3_CH0_Excluded + #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG3_CH0_Included + #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included +#endif + + + +/*lint --flb "Leave library region" */ + +#endif /* NRF51_TO_NRF52_H */ + diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52.h new file mode 100644 index 000000000..2e8c7b09c --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52.h @@ -0,0 +1,2452 @@ +/* + * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @file nrf52.h + * @brief CMSIS HeaderFile + * @version 1 + * @date 14. August 2020 + * @note Generated by SVDConv V3.3.35 on Friday, 14.08.2020 15:04:39 + * from File 'nrf52.svd', + * last modified on Friday, 14.08.2020 13:04:32 + */ + + + +/** @addtogroup Nordic Semiconductor + * @{ + */ + + +/** @addtogroup nrf52 + * @{ + */ + + +#ifndef NRF52_H +#define NRF52_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* =========================================== nrf52 Specific Interrupt Numbers ============================================ */ + POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ + RADIO_IRQn = 1, /*!< 1 RADIO */ + UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ + NFCT_IRQn = 5, /*!< 5 NFCT */ + GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ + SAADC_IRQn = 7, /*!< 7 SAADC */ + TIMER0_IRQn = 8, /*!< 8 TIMER0 */ + TIMER1_IRQn = 9, /*!< 9 TIMER1 */ + TIMER2_IRQn = 10, /*!< 10 TIMER2 */ + RTC0_IRQn = 11, /*!< 11 RTC0 */ + TEMP_IRQn = 12, /*!< 12 TEMP */ + RNG_IRQn = 13, /*!< 13 RNG */ + ECB_IRQn = 14, /*!< 14 ECB */ + CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ + WDT_IRQn = 16, /*!< 16 WDT */ + RTC1_IRQn = 17, /*!< 17 RTC1 */ + QDEC_IRQn = 18, /*!< 18 QDEC */ + COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ + SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ + SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ + SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ + SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ + SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ + SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ + TIMER3_IRQn = 26, /*!< 26 TIMER3 */ + TIMER4_IRQn = 27, /*!< 27 TIMER4 */ + PWM0_IRQn = 28, /*!< 28 PWM0 */ + PDM_IRQn = 29, /*!< 29 PDM */ + MWU_IRQn = 32, /*!< 32 MWU */ + PWM1_IRQn = 33, /*!< 33 PWM1 */ + PWM2_IRQn = 34, /*!< 34 PWM2 */ + SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ + RTC2_IRQn = 36, /*!< 36 RTC2 */ + I2S_IRQn = 37, /*!< 37 I2S */ + FPU_IRQn = 38 /*!< 38 FPU */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __DSP_PRESENT 1 /*!< DSP present or not */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 1 /*!< FPU present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ +#include "system_nrf52.h" /*!< nrf52 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + + +/** + * @brief FICR_INFO [INFO] (Device info) + */ +typedef struct { + __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ + __IM uint32_t VARIANT; /*!< (@ 0x00000004) Part Variant, Hardware version and Production + configuration */ + __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ + __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ + __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ + __IOM uint32_t UNUSED0[3]; /*!< (@ 0x00000014) Description collection[0]: Unspecified */ +} FICR_INFO_Type; /*!< Size = 32 (0x20) */ + + +/** + * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) + */ +typedef struct { + __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0. */ + __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1. */ + __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2. */ + __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3. */ + __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4. */ + __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5. */ + __IM uint32_t B0; /*!< (@ 0x00000018) y-intercept B0. */ + __IM uint32_t B1; /*!< (@ 0x0000001C) y-intercept B1. */ + __IM uint32_t B2; /*!< (@ 0x00000020) y-intercept B2. */ + __IM uint32_t B3; /*!< (@ 0x00000024) y-intercept B3. */ + __IM uint32_t B4; /*!< (@ 0x00000028) y-intercept B4. */ + __IM uint32_t B5; /*!< (@ 0x0000002C) y-intercept B5. */ + __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0. */ + __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1. */ + __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2. */ + __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3. */ + __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4. */ +} FICR_TEMP_Type; /*!< Size = 68 (0x44) */ + + +/** + * @brief FICR_NFC [NFC] (Unspecified) + */ +typedef struct { + __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC Tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST and NFCID1_LAST. */ + __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC Tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST and NFCID1_LAST. */ + __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC Tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST and NFCID1_LAST. */ + __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC Tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST and NFCID1_LAST. */ +} FICR_NFC_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief POWER_RAM [RAM] (Unspecified) + */ +typedef struct { + __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster[0]: RAM0 power control register */ + __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[0]: RAM0 power control set + register */ + __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[0]: RAM0 power control clear + register */ + __IM uint32_t RESERVED; +} POWER_RAM_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UARTE_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ + __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ + __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ + __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ +} UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_RXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_TXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPIM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ +} SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ + __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ + __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ +} SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ +} SPIS_RXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPIS_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ +} SPIS_TXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief TWIM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIS_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ +} TWIS_RXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ +} TWIS_TXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPI_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO */ +} SPI_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified) + */ +typedef struct { + __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frames */ +} NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief NFCT_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ + __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ +} NFCT_TXD_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief NFCT_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ +} NFCT_RXD_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SAADC_EVENTS_CH [EVENTS_CH] (Unspecified) + */ +typedef struct { + __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[0]: Last results is equal + or above CH[0].LIMIT.HIGH */ + __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[0]: Last results is equal + or below CH[0].LIMIT.LOW */ +} SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SAADC_CH [CH] (Unspecified) + */ +typedef struct { + __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster[0]: Input positive pin selection + for CH[0] */ + __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster[0]: Input negative pin selection + for CH[0] */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster[0]: Input configuration for + CH[0] */ + __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster[0]: High/low limits for event + monitoring a channel */ +} SAADC_CH_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last + START */ +} SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief QDEC_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ + __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ + __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ +} QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief PWM_SEQ [SEQ] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[0]: Beginning address in + Data RAM of this sequence */ + __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster[0]: Amount of values (duty + cycles) in this sequence */ + __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[0]: Amount of additional + PWM periods between samples loaded into + compare register */ + __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[0]: Time added after the + sequence */ + __IM uint32_t RESERVED[4]; +} PWM_SEQ_Type; /*!< Size = 32 (0x20) */ + + +/** + * @brief PWM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[0]: Output pin select + for PWM channel 0 */ +} PWM_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief PDM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ + __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ +} PDM_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PDM_SAMPLE [SAMPLE] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with + EasyDMA */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA + mode */ +} PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) + */ +typedef struct { + __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[0]: Enable channel group + 0 */ + __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[0]: Disable channel group + 0 */ +} PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_CH [CH] (PPI Channel) + */ +typedef struct { + __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster[0]: Channel 0 event end-point */ + __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster[0]: Channel 0 task end-point */ +} PPI_CH_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_FORK [FORK] (Fork) + */ +typedef struct { + __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster[0]: Channel 0 task end-point */ +} PPI_FORK_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Unspecified) + */ +typedef struct { + __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[0]: Write access to region + 0 detected */ + __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[0]: Read access to region + 0 detected */ +} MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Unspecified) + */ +typedef struct { + __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[0]: Write access to peripheral + region 0 detected */ + __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[0]: Read access to peripheral + region 0 detected */ +} MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief MWU_PERREGION [PERREGION] (Unspecified) + */ +typedef struct { + __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster[0]: Source of event/interrupt + in region 0, write access detected while + corresponding subregion was enabled for + watching */ + __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster[0]: Source of event/interrupt + in region 0, read access detected while + corresponding subregion was enabled for + watching */ +} MWU_PERREGION_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief MWU_REGION [REGION] (Unspecified) + */ +typedef struct { + __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster[0]: Start address for region + 0 */ + __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster[0]: End address of region + 0 */ + __IM uint32_t RESERVED[2]; +} MWU_REGION_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief MWU_PREGION [PREGION] (Unspecified) + */ +typedef struct { + __IM uint32_t START; /*!< (@ 0x00000000) Description cluster[0]: Reserved for future use */ + __IM uint32_t END; /*!< (@ 0x00000004) Description cluster[0]: Reserved for future use */ + __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster[0]: Subregions of region + 0 */ + __IM uint32_t RESERVED; +} MWU_PREGION_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief I2S_CONFIG [CONFIG] (Unspecified) + */ +typedef struct { + __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ + __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ + __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ + __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ + __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ + __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ + __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ + __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ + __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ + __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ +} I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ + + +/** + * @brief I2S_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ +} I2S_RXD_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief I2S_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ +} I2S_TXD_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief I2S_RXTXD [RXTXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ +} I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief I2S_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ + __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ + __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ + __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ + __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ +} I2S_PSEL_Type; /*!< Size = 20 (0x14) */ + + +/** @} */ /* End of group Device_Peripheral_clusters */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ FICR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Factory Information Configuration Registers (FICR) + */ + +typedef struct { /*!< (@ 0x10000000) FICR Structure */ + __IM uint32_t RESERVED[4]; + __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ + __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ + __IM uint32_t RESERVED1[18]; + __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection[0]: Device identifier */ + __IM uint32_t RESERVED2[6]; + __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection[0]: Encryption Root, word + 0 */ + __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection[0]: Identity Root, word + 0 */ + __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ + __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection[0]: Device address 0 */ + __IM uint32_t RESERVED3[21]; + __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ + __IM uint32_t RESERVED4[185]; + __IOM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization + coefficients */ + __IM uint32_t RESERVED5[2]; + __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ +} NRF_FICR_Type; /*!< Size = 1120 (0x460) */ + + + +/* =========================================================================================================================== */ +/* ================ UICR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief User Information Configuration Registers (UICR) + */ + +typedef struct { /*!< (@ 0x10001000) UICR Structure */ + __IOM uint32_t UNUSED0; /*!< (@ 0x00000000) Unspecified */ + __IOM uint32_t UNUSED1; /*!< (@ 0x00000004) Unspecified */ + __IOM uint32_t UNUSED2; /*!< (@ 0x00000008) Unspecified */ + __IM uint32_t RESERVED; + __IOM uint32_t UNUSED3; /*!< (@ 0x00000010) Unspecified */ + __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection[0]: Reserved for Nordic + firmware design */ + __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection[0]: Reserved for Nordic + hardware design */ + __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection[0]: Reserved for customer */ + __IM uint32_t RESERVED1[64]; + __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[0]: Mapping of the nRESET + function (see POWER chapter for details) */ + __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access Port protection */ + __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: + NFC antenna or GPIO */ +} NRF_UICR_Type; /*!< Size = 528 (0x210) */ + + + +/* =========================================================================================================================== */ +/* ================ BPROT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Block Protect (BPROT) + */ + +typedef struct { /*!< (@ 0x40000000) BPROT Structure */ + __IM uint32_t RESERVED[384]; + __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */ + __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */ + __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug interface + mode */ + __IOM uint32_t UNUSED0; /*!< (@ 0x0000060C) Unspecified */ + __IOM uint32_t CONFIG2; /*!< (@ 0x00000610) Block protect configuration register 2 */ + __IOM uint32_t CONFIG3; /*!< (@ 0x00000614) Block protect configuration register 3 */ +} NRF_BPROT_Type; /*!< Size = 1560 (0x618) */ + + + +/* =========================================================================================================================== */ +/* ================ POWER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power control (POWER) + */ + +typedef struct { /*!< (@ 0x40000000) POWER Structure */ + __IM uint32_t RESERVED[30]; + __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ + __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ + __IM uint32_t RESERVED1[34]; + __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ + __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ + __IM uint32_t RESERVED3[122]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[61]; + __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ + __IM uint32_t RESERVED5[9]; + __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ + __IM uint32_t RESERVED6[53]; + __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure comparator configuration */ + __IM uint32_t RESERVED8[2]; + __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ + __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ + __IOM uint32_t RAMON; /*!< (@ 0x00000524) Deprecated register - RAM on/off register (this + register is retained) */ + __IM uint32_t RESERVED9[11]; + __IOM uint32_t RAMONB; /*!< (@ 0x00000554) Deprecated register - RAM on/off register (this + register is retained) */ + __IM uint32_t RESERVED10[8]; + __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DC/DC enable register */ + __IM uint32_t RESERVED11[225]; + __IOM POWER_RAM_Type RAM[8]; /*!< (@ 0x00000900) Unspecified */ +} NRF_POWER_Type; /*!< Size = 2432 (0x980) */ + + + +/* =========================================================================================================================== */ +/* ================ CLOCK ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Clock control (CLOCK) + */ + +typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ + __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */ + __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */ + __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ + __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ + __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ + __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ + __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ + __IM uint32_t RESERVED[57]; + __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ + __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ + __IM uint32_t RESERVED1; + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator complete event */ + __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ + __IM uint32_t RESERVED2[124]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[63]; + __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been + triggered */ + __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ + __IM uint32_t RESERVED4; + __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been + triggered */ + __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ + __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART + task was triggered */ + __IM uint32_t RESERVED5[62]; + __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ + __IM uint32_t RESERVED6[7]; + __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ + __IM uint32_t RESERVED7[8]; + __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the Trace Port debug interface */ +} NRF_CLOCK_Type; /*!< Size = 1376 (0x560) */ + + + +/* =========================================================================================================================== */ +/* ================ RADIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 2.4 GHz Radio (RADIO) + */ + +typedef struct { /*!< (@ 0x40001000) RADIO Structure */ + __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ + __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ + __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ + __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of + the receive signal strength. */ + __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ + __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ + __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ + __IM uint32_t RESERVED[55]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ + __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ + __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ + __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ + __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received + packet */ + __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last + received packet */ + __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete. */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value. */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ + __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ + __IM uint32_t RESERVED3[50]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED4[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED5[61]; + __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ + __IM uint32_t RESERVED6; + __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ + __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ + __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ + __IM uint32_t RESERVED7[60]; + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ + __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ + __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ + __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ + __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ + __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ + __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ + __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ + __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ + __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ + __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ + __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ + __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ + __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ + __IOM uint32_t UNUSED0; /*!< (@ 0x00000540) Unspecified */ + __IOM uint32_t TIFS; /*!< (@ 0x00000544) Inter Frame Spacing in us */ + __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ + __IM uint32_t RESERVED8; + __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ + __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ + __IM uint32_t RESERVED10[39]; + __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection[0]: Device address base + segment 0 */ + __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection[0]: Device address prefix + 0 */ + __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ + __IM uint32_t RESERVED11[3]; + __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ + __IM uint32_t RESERVED12[618]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ +} NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ UARTE0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART with EasyDMA (UARTE0) + */ + +typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ + __IM uint32_t RESERVED[7]; + __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ + __IM uint32_t RESERVED1[52]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet + transferred to Data RAM) */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ + __IM uint32_t RESERVED6; + __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ + __IM uint32_t RESERVED7[41]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ + __IM uint32_t RESERVED10[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED11; + __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[3]; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source + selected. */ + __IM uint32_t RESERVED13[3]; + __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IM uint32_t RESERVED14; + __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED15[7]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ +} NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal Asynchronous Receiver/Transmitter (UART0) + */ + +typedef struct { /*!< (@ 0x40002000) UART0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ + __IM uint32_t RESERVED[3]; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ + __IM uint32_t RESERVED1[56]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ + __IM uint32_t RESERVED3; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ + __IM uint32_t RESERVED5[46]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED6[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED7[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ + __IM uint32_t RESERVED8[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED9; + __IOM uint32_t PSELRTS; /*!< (@ 0x00000508) Pin select for RTS */ + __IOM uint32_t PSELTXD; /*!< (@ 0x0000050C) Pin select for TXD */ + __IOM uint32_t PSELCTS; /*!< (@ 0x00000510) Pin select for CTS */ + __IOM uint32_t PSELRXD; /*!< (@ 0x00000514) Pin select for RXD */ + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED10; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate */ + __IM uint32_t RESERVED11[17]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ +} NRF_UART_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ SPIM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0) + */ + +typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED4; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ + __IM uint32_t RESERVED6[10]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ + __IM uint32_t RESERVED7[44]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED8[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ + __IM uint32_t RESERVED10; + __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED11[4]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED12[3]; + __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED13[26]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in + case and over-read of the TXD buffer. */ +} NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ SPIS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI Slave 0 (SPIS0) + */ + +typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */ + __IM uint32_t RESERVED[9]; + __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ + __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave + to acquire it */ + __IM uint32_t RESERVED1[54]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ + __IM uint32_t RESERVED4[53]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED6[61]; + __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ + __IM uint32_t RESERVED7[15]; + __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ + __IM uint32_t RESERVED8[47]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ + __IM uint32_t RESERVED9; + __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED10[7]; + __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ + __IM uint32_t RESERVED11; + __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ + __IM uint32_t RESERVED12; + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED13; + __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case + of an ignored transaction. */ + __IM uint32_t RESERVED14[24]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ +} NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ TWIM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0) + */ + +typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the + TWI master is not suspended. */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND + task has been issued, TWI traffic is now + suspended. */ + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED6[2]; + __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ + __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last + byte */ + __IM uint32_t RESERVED7[39]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED10[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ + __IM uint32_t RESERVED11; + __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[5]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency */ + __IM uint32_t RESERVED13[3]; + __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED14[13]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ +} NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ + + + +/* =========================================================================================================================== */ +/* ================ TWIS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0) + */ + +typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ + __IM uint32_t RESERVED[5]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED2[3]; + __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ + __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ + __IM uint32_t RESERVED3[51]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED5[9]; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED6[4]; + __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ + __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ + __IM uint32_t RESERVED7[37]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[113]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ + __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had + a match */ + __IM uint32_t RESERVED10[10]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ + __IM uint32_t RESERVED11; + __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[9]; + __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IM uint32_t RESERVED13; + __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED14[14]; + __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection[0]: TWI slave address + 0 */ + __IM uint32_t RESERVED15; + __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match + mechanism */ + __IM uint32_t RESERVED16[10]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case + of an over-read of the transmit buffer. */ +} NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial Peripheral Interface 0 (SPI0) + */ + +typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ + __IM uint32_t RESERVED[66]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ + __IM uint32_t RESERVED1[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ + __IM uint32_t RESERVED3; + __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED4; + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED5; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ +} NRF_SPI_Type; /*!< Size = 1368 (0x558) */ + + + +/* =========================================================================================================================== */ +/* ================ TWI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Interface 0 (TWI0) + */ + +typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ + __IM uint32_t RESERVED4[4]; + __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED6[4]; + __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte + that is sent or received */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ + __IM uint32_t RESERVED8[45]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED9[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED10[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED11[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ + __IM uint32_t RESERVED12; + __IOM uint32_t PSELSCL; /*!< (@ 0x00000508) Pin select for SCL */ + __IOM uint32_t PSELSDA; /*!< (@ 0x0000050C) Pin select for SDA */ + __IM uint32_t RESERVED13[2]; + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED14; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency */ + __IM uint32_t RESERVED15[24]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ +} NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ + + + +/* =========================================================================================================================== */ +/* ================ NFCT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief NFC-A compatible radio (NFCT) + */ + +typedef struct { /*!< (@ 0x40005000) NFCT Structure */ + __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFC peripheral for incoming and outgoing + frames, change state to activated */ + __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFC peripheral */ + __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to + sense mode */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of a outgoing frame, change + state to transmit */ + __IM uint32_t RESERVED[3]; + __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ + __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ + __IM uint32_t RESERVED2[53]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFC peripheral is ready to receive and send + frames */ + __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ + __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ + __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted + frame */ + __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air + symbol of a frame */ + __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received + frame */ + __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data have been checked (CRC, parity) + and transferred to RAM, and EasyDMA has + ended accessing the RX buffer */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register + contains details on the source of the error. */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX + register contains details on the source + of the error. */ + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) + in Data RAM full. */ + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA + has ended accessing the TX buffer */ + __IM uint32_t RESERVED4; + __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ + __IM uint32_t RESERVED5[3]; + __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC Auto collision resolution error reported. */ + __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC Auto collision resolution successfully completed */ + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ + __IM uint32_t RESERVED6[43]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED7[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED8[62]; + __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ + __IM uint32_t RESERVED9; + __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ + __IM uint32_t RESERVED10[8]; + __IM uint32_t CURRENTLOADCTRL; /*!< (@ 0x00000430) Current value driven to the NFC Load Control */ + __IM uint32_t RESERVED11[2]; + __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ + __IM uint32_t RESERVED12[49]; + __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ + __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ + __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in + Data RAM */ + __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of allocated for TXD and RXD data storage + buffer in Data RAM */ + __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */ + __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */ + __IM uint32_t RESERVED13[26]; + __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ + __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ + __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ + __IM uint32_t RESERVED14; + __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ + __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ +} NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOTE ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Tasks and Events (GPIOTE) + */ + +typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ + __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection[0]: Task for writing to + pin specified in CONFIG[0].PSEL. Action + on pin is configured in CONFIG[0].POLARITY. */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection[0]: Task for writing to + pin specified in CONFIG[0].PSEL. Action + on pin is to set it high. */ + __IM uint32_t RESERVED1[4]; + __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection[0]: Task for writing to + pin specified in CONFIG[0].PSEL. Action + on pin is to set it low. */ + __IM uint32_t RESERVED2[32]; + __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection[0]: Event generated from + pin specified in CONFIG[0].PSEL */ + __IM uint32_t RESERVED3[23]; + __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins + with SENSE mechanism enabled */ + __IM uint32_t RESERVED4[97]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED5[129]; + __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection[0]: Configuration for + OUT[n], SET[n] and CLR[n] tasks and IN[n] + event */ +} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ + + + +/* =========================================================================================================================== */ +/* ================ SAADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Analog to Digital Converter (SAADC) + */ + +typedef struct { /*!< (@ 0x40007000) SAADC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in + RAM */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels + are sampled */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ + __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending + on the mode, multiple conversions might + be needed for a result to be transferred + to RAM. */ + __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ + __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ + __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Unspecified */ + __IM uint32_t RESERVED1[106]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ + __IM uint32_t RESERVED4[3]; + __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ + __IM uint32_t RESERVED5[24]; + __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ + __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should + not be combined with SCAN. The RESOLUTION + is applied before averaging, thus for high + OVERSAMPLE a higher RESOLUTION should be + used. */ + __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ + __IM uint32_t RESERVED6[12]; + __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ +} NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Timer/Counter 0 (TIMER0) + */ + +typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ + __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ + __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ + __IM uint32_t RESERVED[11]; + __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection[0]: Capture Timer value + to CC[0] register */ + __IM uint32_t RESERVED1[58]; + __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection[0]: Compare event on CC[0] + match */ + __IM uint32_t RESERVED2[42]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED3[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[126]; + __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ + __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ + __IM uint32_t RESERVED5; + __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection[0]: Capture/Compare register + 0 */ +} NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real time counter 0 (RTC0) + */ + +typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ + __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ + __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ + __IM uint32_t RESERVED1[14]; + __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection[0]: Compare event on CC[0] + match */ + __IM uint32_t RESERVED2[109]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[13]; + __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ + __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ + __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ + __IM uint32_t RESERVED4[110]; + __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ + __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu + t be written when RTC is stopped */ + __IM uint32_t RESERVED5[13]; + __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection[0]: Compare register 0 */ +} NRF_RTC_Type; /*!< Size = 1360 (0x550) */ + + + +/* =========================================================================================================================== */ +/* ================ TEMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Temperature Sensor (TEMP) + */ + +typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[127]; + __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ + __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ + __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ + __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ + __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ + __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ + __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ + __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ + __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ + __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ + __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ + __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ + __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ + __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ + __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ +} NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ + + + +/* =========================================================================================================================== */ +/* ================ RNG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Random Number Generator (RNG) + */ + +typedef struct { /*!< (@ 0x4000D000) RNG Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number + written to the VALUE register */ + __IM uint32_t RESERVED1[63]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[126]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ + __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ +} NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ + + + +/* =========================================================================================================================== */ +/* ================ ECB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES ECB Mode Encryption (ECB) + */ + +typedef struct { /*!< (@ 0x4000E000) ECB Structure */ + __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ + __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ + __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB + task or due to an error */ + __IM uint32_t RESERVED1[127]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ +} NRF_ECB_Type; /*!< Size = 1288 (0x508) */ + + + +/* =========================================================================================================================== */ +/* ================ CCM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES CCM Mode Encryption (CCM) + */ + +typedef struct { /*!< (@ 0x4000F000) CCM Structure */ + __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation + will stop by itself when completed. */ + __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will + stop by itself when completed. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ + __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) CCM error event */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ + __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and + NONCE vector */ + __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ + __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ +} NRF_CCM_Type; /*!< Size = 1304 (0x518) */ + + + +/* =========================================================================================================================== */ +/* ================ AAR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Accelerated Address Resolver (AAR) + */ + +typedef struct { /*!< (@ 0x4000F000) AAR Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified + in the IRK data structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ + __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ + __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ + __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ + __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ + __IM uint32_t RESERVED5; + __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ +} NRF_AAR_Type; /*!< Size = 1304 (0x518) */ + + + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer (WDT) + */ + +typedef struct { /*!< (@ 0x40010000) WDT Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ + __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ + __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ + __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ + __IM uint32_t RESERVED4[60]; + __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection[0]: Reload request 0 */ +} NRF_WDT_Type; /*!< Size = 1568 (0x620) */ + + + +/* =========================================================================================================================== */ +/* ================ QDEC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Quadrature Decoder (QDEC) + */ + +typedef struct { /*!< (@ 0x40012000) QDEC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ + __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ + __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ + __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ + __IM uint32_t RESERVED[59]; + __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value + written to the SAMPLE register */ + __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ + __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ + __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ + __IM uint32_t RESERVED1[59]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ + __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ + __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ + __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ + __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY + and DBLRDY events can be generated */ + __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ + __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the + READCLRACC or RDCLRACC task */ + __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ + __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ + __IM uint32_t RESERVED4[5]; + __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ + __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected + double transitions */ + __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC + or RDCLRDBL task */ +} NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ + + + +/* =========================================================================================================================== */ +/* ================ COMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Comparator (COMP) + */ + +typedef struct { /*!< (@ 0x40013000) COMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ + __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ + __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ + __IOM uint32_t ISOURCE; /*!< (@ 0x0000053C) Current source select on analog input */ +} NRF_COMP_Type; /*!< Size = 1344 (0x540) */ + + + +/* =========================================================================================================================== */ +/* ================ LPCOMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Low Power Comparator (LPCOMP) + */ + +typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ + __IM uint32_t RESERVED5[4]; + __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ + __IM uint32_t RESERVED6[5]; + __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ +} NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */ + + + +/* =========================================================================================================================== */ +/* ================ SWI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Software interrupt 0 (SWI0) + */ + +typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ + __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ +} NRF_SWI_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ EGU0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Event Generator Unit 0 (EGU0) + */ + +typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ + __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection[0]: Trigger 0 for triggering + the corresponding TRIGGERED[0] event */ + __IM uint32_t RESERVED[48]; + __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection[0]: Event number 0 generated + by triggering the corresponding TRIGGER[0] + task */ + __IM uint32_t RESERVED1[112]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ +} NRF_EGU_Type; /*!< Size = 780 (0x30c) */ + + + +/* =========================================================================================================================== */ +/* ================ PWM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse Width Modulation Unit 0 (PWM0) + */ + +typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at + the end of current PWM period, and stops + sequence playback */ + __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection[0]: Loads the first PWM + value on all enabled channels from sequence + 0, and starts playing that sequence at the + rate defined in SEQ[0]REFRESH and/or DECODER.MODE. + Causes PWM generation to start it was not + running. */ + __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on + all enabled channels if DECODER.MODE=NextStep. + Does not cause PWM generation to start it + was not running. */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses + are no longer generated */ + __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection[0]: First PWM period started + on sequence 0 */ + __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection[0]: Emitted at end of + every sequence 0, when last value from RAM + has been applied to wave counter */ + __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ + __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount + of times defined in LOOP.CNT */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ + __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter + counts */ + __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ + __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ + __IOM uint32_t LOOP; /*!< (@ 0x00000514) Amount of playback of a loop */ + __IM uint32_t RESERVED5[2]; + __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ + __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ +} NRF_PWM_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) + */ + +typedef struct { /*!< (@ 0x4001D000) PDM Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified + by SAMPLE.MAXCNT (or the last sample after + a STOP task has been received) to Data RAM */ + __IM uint32_t RESERVED1[125]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ + __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ + __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' + signals */ + __IM uint32_t RESERVED3[3]; + __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ + __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ + __IM uint32_t RESERVED4[8]; + __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ + __IM uint32_t RESERVED5[6]; + __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ +} NRF_PDM_Type; /*!< Size = 1384 (0x568) */ + + + +/* =========================================================================================================================== */ +/* ================ NVMC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Non Volatile Memory Controller (NVMC) + */ + +typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ + __IM uint32_t RESERVED[256]; + __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ + __IM uint32_t RESERVED1[64]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ + + union { + __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in Code area */ + __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a + page in Code area. Equivalent to ERASEPAGE. */ + }; + __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ + __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a + page in Code area. Equivalent to ERASEPAGE. */ + __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing User Information Configuration + Registers */ + __IM uint32_t RESERVED2[10]; + __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-Code cache configuration register. */ + __IM uint32_t RESERVED3; + __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-Code cache hit counter. */ + __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-Code cache miss counter. */ +} NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ + + + +/* =========================================================================================================================== */ +/* ================ PPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Programmable Peripheral Interconnect (PPI) + */ + +typedef struct { /*!< (@ 0x4001F000) PPI Structure */ + __IOM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ + __IM uint32_t RESERVED[308]; + __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ + __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ + __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ + __IM uint32_t RESERVED1; + __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ + __IM uint32_t RESERVED2[148]; + __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection[0]: Channel group 0 */ + __IM uint32_t RESERVED3[62]; + __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ +} NRF_PPI_Type; /*!< Size = 2448 (0x990) */ + + + +/* =========================================================================================================================== */ +/* ================ MWU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Memory Watch Unit (MWU) + */ + +typedef struct { /*!< (@ 0x40020000) MWU Structure */ + __IM uint32_t RESERVED[64]; + __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Unspecified */ + __IM uint32_t RESERVED1[16]; + __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Unspecified */ + __IM uint32_t RESERVED2[100]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable non-maskable interrupt */ + __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable non-maskable interrupt */ + __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable non-maskable interrupt */ + __IM uint32_t RESERVED4[53]; + __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t REGIONEN; /*!< (@ 0x00000510) Enable/disable regions watch */ + __IOM uint32_t REGIONENSET; /*!< (@ 0x00000514) Enable regions watch */ + __IOM uint32_t REGIONENCLR; /*!< (@ 0x00000518) Disable regions watch */ + __IM uint32_t RESERVED6[57]; + __IOM MWU_REGION_Type REGION[4]; /*!< (@ 0x00000600) Unspecified */ + __IM uint32_t RESERVED7[32]; + __IOM MWU_PREGION_Type PREGION[2]; /*!< (@ 0x000006C0) Unspecified */ +} NRF_MWU_Type; /*!< Size = 1760 (0x6e0) */ + + + +/* =========================================================================================================================== */ +/* ================ I2S ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Inter-IC Sound (I2S) + */ + +typedef struct { /*!< (@ 0x40025000) I2S Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK + generator when this is enabled. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. + Triggering this task will cause the {event:STOPPED} + event to be generated. */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal + double-buffers. When the I2S module is started + and RX is enabled, this event will be generated + for every RXTXD.MAXCNT words that are received + on the SDIN pin. */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal + double-buffers. When the I2S module is started + and TX is enabled, this event will be generated + for every RXTXD.MAXCNT words that are sent + on the SDOUT pin. */ + __IM uint32_t RESERVED2[122]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ + __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ + __IM uint32_t RESERVED4[3]; + __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ + __IM uint32_t RESERVED5; + __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ + __IM uint32_t RESERVED6[3]; + __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ + __IM uint32_t RESERVED7[3]; + __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ +} NRF_I2S_Type; /*!< Size = 1396 (0x574) */ + + + +/* =========================================================================================================================== */ +/* ================ FPU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief FPU (FPU) + */ + +typedef struct { /*!< (@ 0x40026000) FPU Structure */ + __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ +} NRF_FPU_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ P0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Port 1 (P0) + */ + +typedef struct { /*!< (@ 0x50000000) P0 Structure */ + __IM uint32_t RESERVED[321]; + __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ + __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ + __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ + __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ + __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ + __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ + __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ + __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that + have met the criteria set in the PIN_CNF[n].SENSE + registers */ + __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour + and LDETECT mode */ + __IM uint32_t RESERVED1[118]; + __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[0]: Configuration of GPIO + pins */ +} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define NRF_FICR_BASE 0x10000000UL +#define NRF_UICR_BASE 0x10001000UL +#define NRF_BPROT_BASE 0x40000000UL +#define NRF_POWER_BASE 0x40000000UL +#define NRF_CLOCK_BASE 0x40000000UL +#define NRF_RADIO_BASE 0x40001000UL +#define NRF_UARTE0_BASE 0x40002000UL +#define NRF_UART0_BASE 0x40002000UL +#define NRF_SPIM0_BASE 0x40003000UL +#define NRF_SPIS0_BASE 0x40003000UL +#define NRF_TWIM0_BASE 0x40003000UL +#define NRF_TWIS0_BASE 0x40003000UL +#define NRF_SPI0_BASE 0x40003000UL +#define NRF_TWI0_BASE 0x40003000UL +#define NRF_SPIM1_BASE 0x40004000UL +#define NRF_SPIS1_BASE 0x40004000UL +#define NRF_TWIM1_BASE 0x40004000UL +#define NRF_TWIS1_BASE 0x40004000UL +#define NRF_SPI1_BASE 0x40004000UL +#define NRF_TWI1_BASE 0x40004000UL +#define NRF_NFCT_BASE 0x40005000UL +#define NRF_GPIOTE_BASE 0x40006000UL +#define NRF_SAADC_BASE 0x40007000UL +#define NRF_TIMER0_BASE 0x40008000UL +#define NRF_TIMER1_BASE 0x40009000UL +#define NRF_TIMER2_BASE 0x4000A000UL +#define NRF_RTC0_BASE 0x4000B000UL +#define NRF_TEMP_BASE 0x4000C000UL +#define NRF_RNG_BASE 0x4000D000UL +#define NRF_ECB_BASE 0x4000E000UL +#define NRF_CCM_BASE 0x4000F000UL +#define NRF_AAR_BASE 0x4000F000UL +#define NRF_WDT_BASE 0x40010000UL +#define NRF_RTC1_BASE 0x40011000UL +#define NRF_QDEC_BASE 0x40012000UL +#define NRF_COMP_BASE 0x40013000UL +#define NRF_LPCOMP_BASE 0x40013000UL +#define NRF_SWI0_BASE 0x40014000UL +#define NRF_EGU0_BASE 0x40014000UL +#define NRF_SWI1_BASE 0x40015000UL +#define NRF_EGU1_BASE 0x40015000UL +#define NRF_SWI2_BASE 0x40016000UL +#define NRF_EGU2_BASE 0x40016000UL +#define NRF_SWI3_BASE 0x40017000UL +#define NRF_EGU3_BASE 0x40017000UL +#define NRF_SWI4_BASE 0x40018000UL +#define NRF_EGU4_BASE 0x40018000UL +#define NRF_SWI5_BASE 0x40019000UL +#define NRF_EGU5_BASE 0x40019000UL +#define NRF_TIMER3_BASE 0x4001A000UL +#define NRF_TIMER4_BASE 0x4001B000UL +#define NRF_PWM0_BASE 0x4001C000UL +#define NRF_PDM_BASE 0x4001D000UL +#define NRF_NVMC_BASE 0x4001E000UL +#define NRF_PPI_BASE 0x4001F000UL +#define NRF_MWU_BASE 0x40020000UL +#define NRF_PWM1_BASE 0x40021000UL +#define NRF_PWM2_BASE 0x40022000UL +#define NRF_SPIM2_BASE 0x40023000UL +#define NRF_SPIS2_BASE 0x40023000UL +#define NRF_SPI2_BASE 0x40023000UL +#define NRF_RTC2_BASE 0x40024000UL +#define NRF_I2S_BASE 0x40025000UL +#define NRF_FPU_BASE 0x40026000UL +#define NRF_P0_BASE 0x50000000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) +#define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) +#define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) +#define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) +#define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) +#define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) +#define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) +#define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) +#define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) +#define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) +#define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) +#define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) +#define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) +#define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) +#define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) +#define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) +#define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) +#define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) +#define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) +#define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) +#define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE) +#define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) +#define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) +#define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) +#define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) +#define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) +#define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) +#define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) +#define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) +#define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) +#define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) +#define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) +#define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) +#define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) +#define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) +#define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) +#define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) +#define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) +#define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) +#define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) +#define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) +#define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) +#define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) +#define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) +#define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) +#define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) +#define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) +#define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) +#define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) +#define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) +#define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE) +#define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) +#define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) +#define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) +#define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) +#define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE) +#define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE) +#define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE) +#define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE) +#define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE) +#define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE) +#define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE) +#define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE) +#define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE) +#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* NRF52_H */ + + +/** @} */ /* End of group nrf52 */ + +/** @} */ /* End of group Nordic Semiconductor */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52820.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52820.h new file mode 100644 index 000000000..5ba199743 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52820.h @@ -0,0 +1,2105 @@ +/* + * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @file nrf52820.h + * @brief CMSIS HeaderFile + * @version 1 + * @date 14. August 2020 + * @note Generated by SVDConv V3.3.35 on Friday, 14.08.2020 15:04:39 + * from File 'nrf52820.svd', + * last modified on Friday, 14.08.2020 13:04:32 + */ + + + +/** @addtogroup Nordic Semiconductor + * @{ + */ + + +/** @addtogroup nrf52820 + * @{ + */ + + +#ifndef NRF52820_H +#define NRF52820_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================== nrf52820 Specific Interrupt Numbers ========================================== */ + POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ + RADIO_IRQn = 1, /*!< 1 RADIO */ + UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ + GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ + TIMER0_IRQn = 8, /*!< 8 TIMER0 */ + TIMER1_IRQn = 9, /*!< 9 TIMER1 */ + TIMER2_IRQn = 10, /*!< 10 TIMER2 */ + RTC0_IRQn = 11, /*!< 11 RTC0 */ + TEMP_IRQn = 12, /*!< 12 TEMP */ + RNG_IRQn = 13, /*!< 13 RNG */ + ECB_IRQn = 14, /*!< 14 ECB */ + CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ + WDT_IRQn = 16, /*!< 16 WDT */ + RTC1_IRQn = 17, /*!< 17 RTC1 */ + QDEC_IRQn = 18, /*!< 18 QDEC */ + COMP_IRQn = 19, /*!< 19 COMP */ + SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ + SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ + SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ + SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ + SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ + SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ + TIMER3_IRQn = 26, /*!< 26 TIMER3 */ + USBD_IRQn = 39 /*!< 39 USBD */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __DSP_PRESENT 1 /*!< DSP present or not */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 0 /*!< FPU present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ +#include "system_nrf52820.h" /*!< nrf52820 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + + +/** + * @brief FICR_INFO [INFO] (Device info) + */ +typedef struct { + __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ + __IM uint32_t VARIANT; /*!< (@ 0x00000004) Build code (hardware version and production configuration) */ + __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ + __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ + __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ +} FICR_INFO_Type; /*!< Size = 20 (0x14) */ + + +/** + * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) + */ +typedef struct { + __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */ + __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */ + __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */ + __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */ + __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */ + __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */ + __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */ + __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */ + __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */ + __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */ + __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */ + __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */ + __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */ + __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */ + __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */ + __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */ + __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */ +} FICR_TEMP_Type; /*!< Size = 68 (0x44) */ + + +/** + * @brief POWER_RAM [RAM] (Unspecified) + */ +typedef struct { + __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */ + __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ + __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear + register */ + __IM uint32_t RESERVED; +} POWER_RAM_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief RADIO_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t DFEGPIO[8]; /*!< (@ 0x00000000) Description collection: Pin select for DFE pin + n */ +} RADIO_PSEL_Type; /*!< Size = 32 (0x20) */ + + +/** + * @brief RADIO_DFEPACKET [DFEPACKET] (DFE packet EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of samples transferred in the last transaction */ +} RADIO_DFEPACKET_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief UART_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */ + __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */ + __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */ + __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */ +} UART_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UARTE_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ + __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ + __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ + __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ +} UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_RXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_TXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPI_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ +} SPI_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPIM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ +} SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ + __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ + __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ +} SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIS_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIS_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWI_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA */ +} TWI_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIS_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIS_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIS_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief QDEC_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ + __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ + __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ +} QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief ACL_ACL [ACL] (Unspecified) + */ +typedef struct { + __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Start address of region + to protect. The start address must be word-aligned. */ + __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect + counting from address ACL[n].ADDR. Write + '0' as no effect. */ + __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster: Access permissions for region + n as defined by start address ACL[n].ADDR + and size ACL[n].SIZE */ + __IM uint32_t RESERVED; +} ACL_ACL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) + */ +typedef struct { + __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ + __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ +} PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_CH [CH] (PPI Channel) + */ +typedef struct { + __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event end-point */ + __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task end-point */ +} PPI_CH_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_FORK [FORK] (Fork) + */ +typedef struct { + __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task end-point */ +} PPI_FORK_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief USBD_HALTED [HALTED] (Unspecified) + */ +typedef struct { + __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection: IN endpoint halted status. + Can be used as is as response to a GetStatus() + request to endpoint. */ + __IM uint32_t RESERVED; + __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection: OUT endpoint halted status. + Can be used as is as response to a GetStatus() + request to endpoint. */ +} USBD_HALTED_Type; /*!< Size = 68 (0x44) */ + + +/** + * @brief USBD_SIZE [SIZE] (Unspecified) + */ +typedef struct { + __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection: Number of bytes received + last in the data stage of this OUT endpoint */ + __IM uint32_t ISOOUT; /*!< (@ 0x00000020) Number of bytes received last on this ISO OUT + data endpoint */ +} USBD_SIZE_Type; /*!< Size = 36 (0x24) */ + + +/** + * @brief USBD_EPIN [EPIN] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes + to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred + in the last transaction */ + __IM uint32_t RESERVED[2]; +} USBD_EPIN_Type; /*!< Size = 20 (0x14) */ + + +/** + * @brief USBD_ISOIN [ISOIN] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} USBD_ISOIN_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief USBD_EPOUT [EPOUT] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes + to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred + in the last transaction */ + __IM uint32_t RESERVED[2]; +} USBD_EPOUT_Type; /*!< Size = 20 (0x14) */ + + +/** + * @brief USBD_ISOOUT [ISOOUT] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} USBD_ISOOUT_Type; /*!< Size = 12 (0xc) */ + + +/** @} */ /* End of group Device_Peripheral_clusters */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ FICR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Factory information configuration registers (FICR) + */ + +typedef struct { /*!< (@ 0x10000000) FICR Structure */ + __IM uint32_t RESERVED[4]; + __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ + __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ + __IM uint32_t RESERVED1[18]; + __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */ + __IM uint32_t RESERVED2[6]; + __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption root, word + n */ + __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity Root, word n */ + __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ + __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */ + __IM uint32_t RESERVED3[21]; + __IM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ + __IM uint32_t RESERVED4[143]; + __IM uint32_t PRODTEST[3]; /*!< (@ 0x00000350) Description collection: Production test signature + n */ + __IM uint32_t RESERVED5[42]; + __IM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization + coefficients */ +} NRF_FICR_Type; /*!< Size = 1096 (0x448) */ + + + +/* =========================================================================================================================== */ +/* ================ UICR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief User information configuration registers (UICR) + */ + +typedef struct { /*!< (@ 0x10001000) UICR Structure */ + __IM uint32_t RESERVED[5]; + __IOM uint32_t NRFFW[13]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware + design */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware + design */ + __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET + function (see POWER chapter for details) */ + __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ + __IM uint32_t RESERVED3; + __IOM uint32_t DEBUGCTRL; /*!< (@ 0x00000210) Processor debug control */ + __IM uint32_t RESERVED4[60]; + __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) Output voltage from REG0 regulator stage. The + maximum output voltage from this stage is + given as VDDH - VREG0DROP. */ +} NRF_UICR_Type; /*!< Size = 776 (0x308) */ + + + +/* =========================================================================================================================== */ +/* ================ CLOCK ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Clock control (CLOCK) + */ + +typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ + __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFXO crystal oscillator */ + __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFXO crystal oscillator */ + __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK */ + __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK */ + __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC */ + __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ + __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ + __IM uint32_t RESERVED[57]; + __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFXO crystal oscillator started */ + __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ + __IM uint32_t RESERVED1; + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFRC completed */ + __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ + __IM uint32_t RESERVED2[5]; + __IOM uint32_t EVENTS_CTSTARTED; /*!< (@ 0x00000128) Calibration timer has been started and is ready + to process new tasks */ + __IOM uint32_t EVENTS_CTSTOPPED; /*!< (@ 0x0000012C) Calibration timer has been stopped and is ready + to process new tasks */ + __IM uint32_t RESERVED3[117]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[63]; + __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been + triggered */ + __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ + __IM uint32_t RESERVED5; + __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been + triggered */ + __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ + __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART + task was triggered */ + __IM uint32_t RESERVED6[62]; + __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t HFXODEBOUNCE; /*!< (@ 0x00000528) HFXO debounce time. The HFXO is started by triggering + the TASKS_HFCLKSTART task. */ + __IOM uint32_t LFXODEBOUNCE; /*!< (@ 0x0000052C) LFXO debounce time. The LFXO is started by triggering + the TASKS_LFCLKSTART task when the LFCLKSRC + register is configured for Xtal. */ + __IM uint32_t RESERVED8[2]; + __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ +} NRF_CLOCK_Type; /*!< Size = 1340 (0x53c) */ + + + +/* =========================================================================================================================== */ +/* ================ POWER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power control (POWER) + */ + +typedef struct { /*!< (@ 0x40000000) POWER Structure */ + __IM uint32_t RESERVED[30]; + __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ + __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-power mode (variable latency) */ + __IM uint32_t RESERVED1[34]; + __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ + __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ + __IOM uint32_t EVENTS_USBDETECTED; /*!< (@ 0x0000011C) Voltage supply detected on VBUS */ + __IOM uint32_t EVENTS_USBREMOVED; /*!< (@ 0x00000120) Voltage supply removed from VBUS */ + __IOM uint32_t EVENTS_USBPWRRDY; /*!< (@ 0x00000124) USB 3.3 V supply ready */ + __IM uint32_t RESERVED3[119]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[61]; + __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ + __IM uint32_t RESERVED5[9]; + __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ + __IM uint32_t RESERVED6[3]; + __IM uint32_t USBREGSTATUS; /*!< (@ 0x00000438) USB supply status */ + __IM uint32_t RESERVED7[49]; + __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ + __IM uint32_t RESERVED8[3]; + __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power-fail comparator configuration */ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ + __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ + __IM uint32_t RESERVED10[21]; + __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC converter for REG1 stage */ + __IM uint32_t RESERVED11[49]; + __IM uint32_t MAINREGSTATUS; /*!< (@ 0x00000640) Main supply status */ + __IM uint32_t RESERVED12[175]; + __IOM POWER_RAM_Type RAM[4]; /*!< (@ 0x00000900) Unspecified */ +} NRF_POWER_Type; /*!< Size = 2368 (0x940) */ + + + +/* =========================================================================================================================== */ +/* ================ P0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Port 1 (P0) + */ + +typedef struct { /*!< (@ 0x50000000) P0 Structure */ + __IM uint32_t RESERVED[321]; + __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ + __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ + __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ + __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ + __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ + __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ + __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ + __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that + have met the criteria set in the PIN_CNF[n].SENSE + registers */ + __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour + and LDETECT mode */ + __IM uint32_t RESERVED1[118]; + __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO + pins */ +} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ + + + +/* =========================================================================================================================== */ +/* ================ RADIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 2.4 GHz radio (RADIO) + */ + +typedef struct { /*!< (@ 0x40001000) RADIO Structure */ + __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ + __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ + __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ + __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of + the receive signal strength */ + __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ + __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ + __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ + __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000024) Start the energy detect measurement used in IEEE + 802.15.4 mode */ + __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000028) Stop the energy detect measurement */ + __OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessment used in IEEE + 802.15.4 mode */ + __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x00000030) Stop the clear channel assessment */ + __IM uint32_t RESERVED[51]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ + __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ + __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ + __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ + __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received + packet */ + __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last + received packet */ + __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ + __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ + __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ + __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new + ED sample is ready for readout from the + RADIO.EDSAMPLE register */ + __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ + __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ + __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ + __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000014C) The CCA has stopped */ + __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000150) Ble_LR CI field received, receive mode is changed + from Ble_LR125Kbit to Ble_LR500Kbit. */ + __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started + TX path */ + __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started + RX path */ + __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_SYNC; /*!< (@ 0x00000168) Preamble indicator */ + __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated when last bit is sent on air, or received + from air */ + __IOM uint32_t EVENTS_CTEPRESENT; /*!< (@ 0x00000170) CTE is present (early warning right after receiving + CTEInfo byte) */ + __IM uint32_t RESERVED4[35]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED6[61]; + __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ + __IM uint32_t RESERVED7; + __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ + __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ + __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ + __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ + __IM uint32_t RESERVED8[13]; + __IM uint32_t CTESTATUS; /*!< (@ 0x0000044C) CTEInfo parsed from received packet */ + __IM uint32_t RESERVED9[2]; + __IM uint32_t DFESTATUS; /*!< (@ 0x00000458) DFE status information */ + __IM uint32_t RESERVED10[42]; + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ + __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ + __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ + __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ + __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ + __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ + __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ + __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ + __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ + __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ + __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ + __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ + __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ + __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ + __IM uint32_t RESERVED11; + __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ + __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ + __IM uint32_t RESERVED12; + __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ + __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ + __IM uint32_t RESERVED13[2]; + __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ + __IM uint32_t RESERVED14[39]; + __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment + n */ + __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix + n */ + __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ + __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ + __IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */ + __IM uint32_t RESERVED15; + __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ + __IM uint32_t RESERVED16[3]; + __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */ + __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */ + __IM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ + __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */ + __IM uint32_t RESERVED17[164]; + __IOM uint32_t DFEMODE; /*!< (@ 0x00000900) Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure + (AOD) */ + __IOM uint32_t CTEINLINECONF; /*!< (@ 0x00000904) Configuration for CTE inline mode */ + __IM uint32_t RESERVED18[2]; + __IOM uint32_t DFECTRL1; /*!< (@ 0x00000910) Various configuration for Direction finding */ + __IOM uint32_t DFECTRL2; /*!< (@ 0x00000914) Start offset for Direction finding */ + __IM uint32_t RESERVED19[4]; + __IOM uint32_t SWITCHPATTERN; /*!< (@ 0x00000928) GPIO patterns to be used for each antenna */ + __IOM uint32_t CLEARPATTERN; /*!< (@ 0x0000092C) Clear the GPIO pattern array for antenna control */ + __IOM RADIO_PSEL_Type PSEL; /*!< (@ 0x00000930) Unspecified */ + __IOM RADIO_DFEPACKET_Type DFEPACKET; /*!< (@ 0x00000950) DFE packet EasyDMA channel */ + __IM uint32_t RESERVED20[424]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ +} NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal Asynchronous Receiver/Transmitter (UART0) + */ + +typedef struct { /*!< (@ 0x40002000) UART0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ + __IM uint32_t RESERVED[3]; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ + __IM uint32_t RESERVED1[56]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ + __IM uint32_t RESERVED3; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ + __IM uint32_t RESERVED5[46]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED6[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED7[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ + __IM uint32_t RESERVED8[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED9; + __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED10; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source + selected. */ + __IM uint32_t RESERVED11[17]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ +} NRF_UART_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ UARTE0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART with EasyDMA (UARTE0) + */ + +typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ + __IM uint32_t RESERVED[7]; + __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ + __IM uint32_t RESERVED1[52]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet + transferred to Data RAM) */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ + __IM uint32_t RESERVED6; + __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ + __IM uint32_t RESERVED7[41]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write + one to clear. */ + __IM uint32_t RESERVED10[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED11; + __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[3]; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source + selected. */ + __IM uint32_t RESERVED13[3]; + __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IM uint32_t RESERVED14; + __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED15[7]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ +} NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial Peripheral Interface 0 (SPI0) + */ + +typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ + __IM uint32_t RESERVED[66]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ + __IM uint32_t RESERVED1[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ + __IM uint32_t RESERVED3; + __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED4; + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED5; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ +} NRF_SPI_Type; /*!< Size = 1368 (0x558) */ + + + +/* =========================================================================================================================== */ +/* ================ SPIM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0) + */ + +typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED4; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ + __IM uint32_t RESERVED6[10]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ + __IM uint32_t RESERVED7[44]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED8[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ + __IM uint32_t RESERVED10; + __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED11[4]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED12[3]; + __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED13[26]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have + been transmitted in the case when RXD.MAXCNT + is greater than TXD.MAXCNT */ +} NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ SPIS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI Slave 0 (SPIS0) + */ + +typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */ + __IM uint32_t RESERVED[9]; + __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ + __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave + to acquire it */ + __IM uint32_t RESERVED1[54]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ + __IM uint32_t RESERVED4[53]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED6[61]; + __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ + __IM uint32_t RESERVED7[15]; + __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ + __IM uint32_t RESERVED8[47]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ + __IM uint32_t RESERVED9; + __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED10[7]; + __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ + __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED11; + __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case + of an ignored transaction. */ + __IM uint32_t RESERVED12[24]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ +} NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ TWI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Interface 0 (TWI0) + */ + +typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ + __IM uint32_t RESERVED4[4]; + __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED6[4]; + __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte + that is sent or received */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ + __IM uint32_t RESERVED8[45]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED9[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED10[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED11[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ + __IM uint32_t RESERVED12; + __IOM TWI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED13[2]; + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED14; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED15[24]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ +} NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ + + + +/* =========================================================================================================================== */ +/* ================ TWIM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0) + */ + +typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the + TWI master is not suspended. */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND + task has been issued, TWI traffic is now + suspended. */ + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED6[2]; + __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ + __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last + byte */ + __IM uint32_t RESERVED7[39]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED10[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ + __IM uint32_t RESERVED11; + __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[5]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED13[3]; + __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED14[13]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ +} NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ + + + +/* =========================================================================================================================== */ +/* ================ TWIS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0) + */ + +typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ + __IM uint32_t RESERVED[5]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED2[3]; + __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ + __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ + __IM uint32_t RESERVED3[51]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED5[9]; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED6[4]; + __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ + __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ + __IM uint32_t RESERVED7[37]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[113]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ + __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had + a match */ + __IM uint32_t RESERVED10[10]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ + __IM uint32_t RESERVED11; + __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[9]; + __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED13[13]; + __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ + __IM uint32_t RESERVED14; + __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match + mechanism */ + __IM uint32_t RESERVED15[10]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case + of an over-read of the transmit buffer. */ +} NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOTE ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Tasks and Events (GPIOTE) + */ + +typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ + __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is configured in CONFIG[n].POLARITY. */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is to set it high. */ + __IM uint32_t RESERVED1[4]; + __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is to set it low. */ + __IM uint32_t RESERVED2[32]; + __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from + pin specified in CONFIG[n].PSEL */ + __IM uint32_t RESERVED3[23]; + __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins + with SENSE mechanism enabled */ + __IM uint32_t RESERVED4[97]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED5[129]; + __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], + SET[n], and CLR[n] tasks and IN[n] event */ +} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Timer/Counter 0 (TIMER0) + */ + +typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ + __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ + __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ + __IM uint32_t RESERVED[11]; + __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to + CC[n] register */ + __IM uint32_t RESERVED1[58]; + __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] + match */ + __IM uint32_t RESERVED2[42]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED3[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[126]; + __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ + __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ + __IM uint32_t RESERVED5; + __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register + n */ +} NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real time counter 0 (RTC0) + */ + +typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ + __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ + __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ + __IM uint32_t RESERVED1[14]; + __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] + match */ + __IM uint32_t RESERVED2[109]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[13]; + __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ + __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ + __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ + __IM uint32_t RESERVED4[110]; + __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ + __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu + t be written when RTC is stopped */ + __IM uint32_t RESERVED5[13]; + __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ +} NRF_RTC_Type; /*!< Size = 1360 (0x550) */ + + + +/* =========================================================================================================================== */ +/* ================ TEMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Temperature Sensor (TEMP) + */ + +typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[127]; + __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ + __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ + __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ + __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ + __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ + __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ + __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ + __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ + __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ + __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ + __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ + __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ + __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ + __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ + __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ +} NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ + + + +/* =========================================================================================================================== */ +/* ================ RNG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Random Number Generator (RNG) + */ + +typedef struct { /*!< (@ 0x4000D000) RNG Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number + written to the VALUE register */ + __IM uint32_t RESERVED1[63]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[126]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ + __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ +} NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ + + + +/* =========================================================================================================================== */ +/* ================ ECB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES ECB Mode Encryption (ECB) + */ + +typedef struct { /*!< (@ 0x4000E000) ECB Structure */ + __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ + __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ + __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB + task or due to an error */ + __IM uint32_t RESERVED1[127]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ +} NRF_ECB_Type; /*!< Size = 1288 (0x508) */ + + + +/* =========================================================================================================================== */ +/* ================ AAR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Accelerated Address Resolver (AAR) + */ + +typedef struct { /*!< (@ 0x4000F000) AAR Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified + in the IRK data structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ + __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ + __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ + __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ + __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ + __IM uint32_t RESERVED5; + __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ +} NRF_AAR_Type; /*!< Size = 1304 (0x518) */ + + + +/* =========================================================================================================================== */ +/* ================ CCM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES CCM Mode Encryption (CCM) + */ + +typedef struct { /*!< (@ 0x4000F000) CCM Structure */ + __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation + will stop by itself when completed. */ + __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will + stop by itself when completed. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ + __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with + the contents of the RATEOVERRIDE register + for any ongoing encryption/decryption */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ + __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ + __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and + NONCE vector */ + __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ + __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ + __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of key-stream generated when MODE.LENGTH + = Extended. */ + __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ +} NRF_CCM_Type; /*!< Size = 1312 (0x520) */ + + + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer (WDT) + */ + +typedef struct { /*!< (@ 0x40010000) WDT Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ + __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ + __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ + __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ + __IM uint32_t RESERVED4[60]; + __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ +} NRF_WDT_Type; /*!< Size = 1568 (0x620) */ + + + +/* =========================================================================================================================== */ +/* ================ QDEC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Quadrature Decoder (QDEC) + */ + +typedef struct { /*!< (@ 0x40012000) QDEC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ + __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ + __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ + __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ + __IM uint32_t RESERVED[59]; + __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value + written to the SAMPLE register */ + __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ + __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ + __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ + __IM uint32_t RESERVED1[59]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ + __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ + __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ + __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ + __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY + and DBLRDY events can be generated */ + __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ + __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the + READCLRACC or RDCLRACC task */ + __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ + __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ + __IM uint32_t RESERVED4[5]; + __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ + __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected + double transitions */ + __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC + or RDCLRDBL task */ +} NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ + + + +/* =========================================================================================================================== */ +/* ================ COMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Comparator (COMP) + */ + +typedef struct { /*!< (@ 0x40013000) COMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ + __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ + __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ +} NRF_COMP_Type; /*!< Size = 1340 (0x53c) */ + + + +/* =========================================================================================================================== */ +/* ================ EGU0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Event generator unit 0 (EGU0) + */ + +typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ + __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering + the corresponding TRIGGERED[n] event */ + __IM uint32_t RESERVED[48]; + __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated + by triggering the corresponding TRIGGER[n] + task */ + __IM uint32_t RESERVED1[112]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ +} NRF_EGU_Type; /*!< Size = 780 (0x30c) */ + + + +/* =========================================================================================================================== */ +/* ================ SWI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Software interrupt 0 (SWI0) + */ + +typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ + __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ +} NRF_SWI_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ ACL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Access control lists (ACL) + */ + +typedef struct { /*!< (@ 0x4001E000) ACL Structure */ + __IM uint32_t RESERVED[512]; + __IOM ACL_ACL_Type ACL[8]; /*!< (@ 0x00000800) Unspecified */ +} NRF_ACL_Type; /*!< Size = 2176 (0x880) */ + + + +/* =========================================================================================================================== */ +/* ================ NVMC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Non Volatile Memory Controller (NVMC) + */ + +typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ + __IM uint32_t RESERVED[256]; + __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ + __IM uint32_t RESERVED1; + __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ + __IM uint32_t RESERVED2[62]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ + + union { + __OM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ + __OM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a + page in code area, equivalent to ERASEPAGE */ + }; + __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ + __OM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a + page in code area, equivalent to ERASEPAGE */ + __OM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration + registers */ + __OM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code + area */ + __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ +} NRF_NVMC_Type; /*!< Size = 1312 (0x520) */ + + + +/* =========================================================================================================================== */ +/* ================ PPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Programmable Peripheral Interconnect (PPI) + */ + +typedef struct { /*!< (@ 0x4001F000) PPI Structure */ + __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ + __IM uint32_t RESERVED[308]; + __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ + __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ + __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ + __IM uint32_t RESERVED1; + __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ + __IM uint32_t RESERVED2[148]; + __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */ + __IM uint32_t RESERVED3[62]; + __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ +} NRF_PPI_Type; /*!< Size = 2448 (0x990) */ + + + +/* =========================================================================================================================== */ +/* ================ USBD ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal serial bus device (USBD) + */ + +typedef struct { /*!< (@ 0x40027000) USBD Structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection: Captures the EPIN[n].PTR + and EPIN[n].MAXCNT registers values, and + enables endpoint IN n to respond to traffic + from host */ + __OM uint32_t TASKS_STARTISOIN; /*!< (@ 0x00000024) Captures the ISOIN.PTR and ISOIN.MAXCNT registers + values, and enables sending data on ISO + endpoint */ + __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection: Captures the EPOUT[n].PTR + and EPOUT[n].MAXCNT registers values, and + enables endpoint n to respond to traffic + from host */ + __OM uint32_t TASKS_STARTISOOUT; /*!< (@ 0x00000048) Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers + values, and enables receiving of data on + ISO endpoint */ + __OM uint32_t TASKS_EP0RCVOUT; /*!< (@ 0x0000004C) Allows OUT data stage on control endpoint 0 */ + __OM uint32_t TASKS_EP0STATUS; /*!< (@ 0x00000050) Allows status stage on control endpoint 0 */ + __OM uint32_t TASKS_EP0STALL; /*!< (@ 0x00000054) Stalls data and status stage on control endpoint + 0 */ + __OM uint32_t TASKS_DPDMDRIVE; /*!< (@ 0x00000058) Forces D+ and D- lines into the state defined + in the DPDMVALUE register */ + __OM uint32_t TASKS_DPDMNODRIVE; /*!< (@ 0x0000005C) Stops forcing D+ and D- lines into any state + (USB engine takes control) */ + __IM uint32_t RESERVED1[40]; + __IOM uint32_t EVENTS_USBRESET; /*!< (@ 0x00000100) Signals that a USB reset condition has been detected + on USB lines */ + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000104) Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, + or EPOUT[n].PTR and EPOUT[n].MAXCNT registers + have been captured on all endpoints reported + in the EPSTATUS register */ + __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection: The whole EPIN[n] buffer + has been consumed. The buffer can be accessed + safely by software. */ + __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place + on the control endpoint */ + __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The + buffer can be accessed safely by software. */ + __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection: The whole EPOUT[n] buffer + has been consumed. The buffer can be accessed + safely by software. */ + __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The + buffer can be accessed safely by software. */ + __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition + has been detected on USB lines */ + __IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific + events has occurred. Check EVENTCAUSE register + to find the cause. */ + __IOM uint32_t EVENTS_EP0SETUP; /*!< (@ 0x0000015C) A valid SETUP token has been received (and acknowledged) + on the control endpoint */ + __IOM uint32_t EVENTS_EPDATA; /*!< (@ 0x00000160) A data transfer has occurred on a data endpoint, + indicated by the EPDATASTATUS register */ + __IM uint32_t RESERVED2[39]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[61]; + __IOM uint32_t EVENTCAUSE; /*!< (@ 0x00000400) Details on what caused the USBEVENT event */ + __IM uint32_t RESERVED5[7]; + __IOM USBD_HALTED_Type HALTED; /*!< (@ 0x00000420) Unspecified */ + __IM uint32_t RESERVED6; + __IOM uint32_t EPSTATUS; /*!< (@ 0x00000468) Provides information on which endpoint's EasyDMA + registers have been captured */ + __IOM uint32_t EPDATASTATUS; /*!< (@ 0x0000046C) Provides information on which endpoint(s) an + acknowledged data transfer has occurred + (EPDATA event) */ + __IM uint32_t USBADDR; /*!< (@ 0x00000470) Device USB address */ + __IM uint32_t RESERVED7[3]; + __IM uint32_t BMREQUESTTYPE; /*!< (@ 0x00000480) SETUP data, byte 0, bmRequestType */ + __IM uint32_t BREQUEST; /*!< (@ 0x00000484) SETUP data, byte 1, bRequest */ + __IM uint32_t WVALUEL; /*!< (@ 0x00000488) SETUP data, byte 2, LSB of wValue */ + __IM uint32_t WVALUEH; /*!< (@ 0x0000048C) SETUP data, byte 3, MSB of wValue */ + __IM uint32_t WINDEXL; /*!< (@ 0x00000490) SETUP data, byte 4, LSB of wIndex */ + __IM uint32_t WINDEXH; /*!< (@ 0x00000494) SETUP data, byte 5, MSB of wIndex */ + __IM uint32_t WLENGTHL; /*!< (@ 0x00000498) SETUP data, byte 6, LSB of wLength */ + __IM uint32_t WLENGTHH; /*!< (@ 0x0000049C) SETUP data, byte 7, MSB of wLength */ + __IOM USBD_SIZE_Type SIZE; /*!< (@ 0x000004A0) Unspecified */ + __IM uint32_t RESERVED8[15]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable USB */ + __IOM uint32_t USBPULLUP; /*!< (@ 0x00000504) Control of the USB pull-up */ + __IOM uint32_t DPDMVALUE; /*!< (@ 0x00000508) State D+ and D- lines will be forced into by + the DPDMDRIVE task. The DPDMNODRIVE task + reverts the control of the lines to MAC + IP (no forcing). */ + __IOM uint32_t DTOGGLE; /*!< (@ 0x0000050C) Data toggle control and status */ + __IOM uint32_t EPINEN; /*!< (@ 0x00000510) Endpoint IN enable */ + __IOM uint32_t EPOUTEN; /*!< (@ 0x00000514) Endpoint OUT enable */ + __OM uint32_t EPSTALL; /*!< (@ 0x00000518) STALL endpoints */ + __IOM uint32_t ISOSPLIT; /*!< (@ 0x0000051C) Controls the split of ISO buffers */ + __IM uint32_t FRAMECNTR; /*!< (@ 0x00000520) Returns the current value of the start of frame + counter */ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t LOWPOWER; /*!< (@ 0x0000052C) Controls USBD peripheral low power mode during + USB suspend */ + __IOM uint32_t ISOINCONFIG; /*!< (@ 0x00000530) Controls the response of the ISO IN endpoint + to an IN token when no data is ready to + be sent */ + __IM uint32_t RESERVED10[51]; + __IOM USBD_EPIN_Type EPIN[8]; /*!< (@ 0x00000600) Unspecified */ + __IOM USBD_ISOIN_Type ISOIN; /*!< (@ 0x000006A0) Unspecified */ + __IM uint32_t RESERVED11[21]; + __IOM USBD_EPOUT_Type EPOUT[8]; /*!< (@ 0x00000700) Unspecified */ + __IOM USBD_ISOOUT_Type ISOOUT; /*!< (@ 0x000007A0) Unspecified */ +} NRF_USBD_Type; /*!< Size = 1964 (0x7ac) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define NRF_FICR_BASE 0x10000000UL +#define NRF_UICR_BASE 0x10001000UL +#define NRF_CLOCK_BASE 0x40000000UL +#define NRF_POWER_BASE 0x40000000UL +#define NRF_P0_BASE 0x50000000UL +#define NRF_RADIO_BASE 0x40001000UL +#define NRF_UART0_BASE 0x40002000UL +#define NRF_UARTE0_BASE 0x40002000UL +#define NRF_SPI0_BASE 0x40003000UL +#define NRF_SPIM0_BASE 0x40003000UL +#define NRF_SPIS0_BASE 0x40003000UL +#define NRF_TWI0_BASE 0x40003000UL +#define NRF_TWIM0_BASE 0x40003000UL +#define NRF_TWIS0_BASE 0x40003000UL +#define NRF_SPI1_BASE 0x40004000UL +#define NRF_SPIM1_BASE 0x40004000UL +#define NRF_SPIS1_BASE 0x40004000UL +#define NRF_TWI1_BASE 0x40004000UL +#define NRF_TWIM1_BASE 0x40004000UL +#define NRF_TWIS1_BASE 0x40004000UL +#define NRF_GPIOTE_BASE 0x40006000UL +#define NRF_TIMER0_BASE 0x40008000UL +#define NRF_TIMER1_BASE 0x40009000UL +#define NRF_TIMER2_BASE 0x4000A000UL +#define NRF_RTC0_BASE 0x4000B000UL +#define NRF_TEMP_BASE 0x4000C000UL +#define NRF_RNG_BASE 0x4000D000UL +#define NRF_ECB_BASE 0x4000E000UL +#define NRF_AAR_BASE 0x4000F000UL +#define NRF_CCM_BASE 0x4000F000UL +#define NRF_WDT_BASE 0x40010000UL +#define NRF_RTC1_BASE 0x40011000UL +#define NRF_QDEC_BASE 0x40012000UL +#define NRF_COMP_BASE 0x40013000UL +#define NRF_EGU0_BASE 0x40014000UL +#define NRF_SWI0_BASE 0x40014000UL +#define NRF_EGU1_BASE 0x40015000UL +#define NRF_SWI1_BASE 0x40015000UL +#define NRF_EGU2_BASE 0x40016000UL +#define NRF_SWI2_BASE 0x40016000UL +#define NRF_EGU3_BASE 0x40017000UL +#define NRF_SWI3_BASE 0x40017000UL +#define NRF_EGU4_BASE 0x40018000UL +#define NRF_SWI4_BASE 0x40018000UL +#define NRF_EGU5_BASE 0x40019000UL +#define NRF_SWI5_BASE 0x40019000UL +#define NRF_TIMER3_BASE 0x4001A000UL +#define NRF_ACL_BASE 0x4001E000UL +#define NRF_NVMC_BASE 0x4001E000UL +#define NRF_PPI_BASE 0x4001F000UL +#define NRF_USBD_BASE 0x40027000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) +#define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) +#define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) +#define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) +#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) +#define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) +#define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) +#define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) +#define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) +#define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) +#define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) +#define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) +#define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) +#define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) +#define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) +#define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) +#define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) +#define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) +#define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) +#define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) +#define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) +#define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) +#define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) +#define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) +#define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) +#define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) +#define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) +#define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) +#define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) +#define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) +#define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) +#define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) +#define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) +#define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) +#define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) +#define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) +#define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) +#define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) +#define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) +#define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) +#define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) +#define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) +#define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) +#define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) +#define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) +#define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) +#define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) +#define NRF_ACL ((NRF_ACL_Type*) NRF_ACL_BASE) +#define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) +#define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) +#define NRF_USBD ((NRF_USBD_Type*) NRF_USBD_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* NRF52820_H */ + + +/** @} */ /* End of group nrf52820 */ + +/** @} */ /* End of group Nordic Semiconductor */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_bitfields.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_bitfields.h new file mode 100644 index 000000000..827b8f376 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_bitfields.h @@ -0,0 +1,12096 @@ +/* + +Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef __NRF52820_BITS_H +#define __NRF52820_BITS_H + +/*lint ++flb "Enter library region" */ + +/* Peripheral: AAR */ +/* Description: Accelerated Address Resolver */ + +/* Register: AAR_TASKS_START */ +/* Description: Start resolving addresses based on IRKs specified in the IRK data structure */ + +/* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */ +#define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: AAR_TASKS_STOP */ +/* Description: Stop resolving addresses */ + +/* Bit 0 : Stop resolving addresses */ +#define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: AAR_EVENTS_END */ +/* Description: Address resolution procedure complete */ + +/* Bit 0 : Address resolution procedure complete */ +#define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ + +/* Register: AAR_EVENTS_RESOLVED */ +/* Description: Address resolved */ + +/* Bit 0 : Address resolved */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */ + +/* Register: AAR_EVENTS_NOTRESOLVED */ +/* Description: Address not resolved */ + +/* Bit 0 : Address not resolved */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */ + +/* Register: AAR_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */ +#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event RESOLVED */ +#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event END */ +#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Register: AAR_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */ +#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event RESOLVED */ +#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event END */ +#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Register: AAR_STATUS */ +/* Description: Resolution status */ + +/* Bits 3..0 : The IRK that was used last time an address was resolved */ +#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ + +/* Register: AAR_ENABLE */ +/* Description: Enable AAR */ + +/* Bits 1..0 : Enable or disable AAR */ +#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */ + +/* Register: AAR_NIRK */ +/* Description: Number of IRKs */ + +/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */ +#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ +#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ + +/* Register: AAR_IRKPTR */ +/* Description: Pointer to IRK data structure */ + +/* Bits 31..0 : Pointer to the IRK data structure */ +#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */ +#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */ + +/* Register: AAR_ADDRPTR */ +/* Description: Pointer to the resolvable address */ + +/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */ +#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */ +#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */ + +/* Register: AAR_SCRATCHPTR */ +/* Description: Pointer to data area used for temporary storage */ + +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. */ +#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ +#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ + + +/* Peripheral: ACL */ +/* Description: Access control lists */ + +/* Register: ACL_ACL_ADDR */ +/* Description: Description cluster: Start address of region to protect. The start address must be word-aligned. */ + +/* Bits 31..0 : Start address of flash region n. The start address must point to a flash page boundary. */ +#define ACL_ACL_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ +#define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ + +/* Register: ACL_ACL_SIZE */ +/* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */ + +/* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size. */ +#define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ +#define ACL_ACL_SIZE_SIZE_Msk (0xFFFFFFFFUL << ACL_ACL_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ + +/* Register: ACL_ACL_PERM */ +/* Description: Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */ + +/* Bit 2 : Configure read permissions for region n. Write '0' has no effect. */ +#define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */ +#define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos) /*!< Bit mask of READ field. */ +#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n */ +#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n */ + +/* Bit 1 : Configure write and erase permissions for region n. Write '0' has no effect. */ +#define ACL_ACL_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */ +#define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n */ +#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n */ + + +/* Peripheral: CCM */ +/* Description: AES CCM Mode Encryption */ + +/* Register: CCM_TASKS_KSGEN */ +/* Description: Start generation of key-stream. This operation will stop by itself when completed. */ + +/* Bit 0 : Start generation of key-stream. This operation will stop by itself when completed. */ +#define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */ +#define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */ +#define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */ + +/* Register: CCM_TASKS_CRYPT */ +/* Description: Start encryption/decryption. This operation will stop by itself when completed. */ + +/* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */ +#define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */ +#define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */ +#define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */ + +/* Register: CCM_TASKS_STOP */ +/* Description: Stop encryption/decryption */ + +/* Bit 0 : Stop encryption/decryption */ +#define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: CCM_TASKS_RATEOVERRIDE */ +/* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ + +/* Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ +#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */ +#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */ +#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */ + +/* Register: CCM_EVENTS_ENDKSGEN */ +/* Description: Key-stream generation complete */ + +/* Bit 0 : Key-stream generation complete */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */ + +/* Register: CCM_EVENTS_ENDCRYPT */ +/* Description: Encrypt/decrypt complete */ + +/* Bit 0 : Encrypt/decrypt complete */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */ + +/* Register: CCM_EVENTS_ERROR */ +/* Description: Deprecated register - CCM error event */ + +/* Bit 0 : Deprecated field - CCM error event */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: CCM_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: CCM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Deprecated intsetfield - Write '1' to enable interrupt for event ERROR */ +#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */ +#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */ +#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */ + +/* Register: CCM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Deprecated intclrfield - Write '1' to disable interrupt for event ERROR */ +#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */ +#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */ +#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */ + +/* Register: CCM_MICSTATUS */ +/* Description: MIC check result */ + +/* Bit 0 : The result of the MIC check performed during the previous decryption operation */ +#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */ +#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */ + +/* Register: CCM_ENABLE */ +/* Description: Enable */ + +/* Bits 1..0 : Enable or disable CCM */ +#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ + +/* Register: CCM_MODE */ +/* Description: Operation mode */ + +/* Bit 24 : Packet length configuration */ +#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ +#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ +#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. */ +#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ + +/* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */ +#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ +#define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ +#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */ +#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */ +#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */ +#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 Kbps */ + +/* Bit 0 : The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. */ +#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */ +#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */ + +/* Register: CCM_CNFPTR */ +/* Description: Pointer to data structure holding AES key and NONCE vector */ + +/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */ +#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */ +#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */ + +/* Register: CCM_INPTR */ +/* Description: Input pointer */ + +/* Bits 31..0 : Input pointer */ +#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */ +#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */ + +/* Register: CCM_OUTPTR */ +/* Description: Output pointer */ + +/* Bits 31..0 : Output pointer */ +#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */ +#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */ + +/* Register: CCM_SCRATCHPTR */ +/* Description: Pointer to data area used for temporary storage */ + +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, + MIC generation and encryption/decryption. */ +#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ +#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ + +/* Register: CCM_MAXPACKETSIZE */ +/* Description: Length of key-stream generated when MODE.LENGTH = Extended. */ + +/* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ +#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */ +#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */ + +/* Register: CCM_RATEOVERRIDE */ +/* Description: Data rate override setting. */ + +/* Bits 1..0 : Data rate override setting. */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */ + + +/* Peripheral: CLOCK */ +/* Description: Clock control */ + +/* Register: CLOCK_TASKS_HFCLKSTART */ +/* Description: Start HFXO crystal oscillator */ + +/* Bit 0 : Start HFXO crystal oscillator */ +#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */ +#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */ +#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_TASKS_HFCLKSTOP */ +/* Description: Stop HFXO crystal oscillator */ + +/* Bit 0 : Stop HFXO crystal oscillator */ +#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */ +#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */ +#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_TASKS_LFCLKSTART */ +/* Description: Start LFCLK */ + +/* Bit 0 : Start LFCLK */ +#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */ +#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */ +#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_TASKS_LFCLKSTOP */ +/* Description: Stop LFCLK */ + +/* Bit 0 : Stop LFCLK */ +#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */ +#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */ +#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_TASKS_CAL */ +/* Description: Start calibration of LFRC */ + +/* Bit 0 : Start calibration of LFRC */ +#define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */ +#define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */ +#define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_TASKS_CTSTART */ +/* Description: Start calibration timer */ + +/* Bit 0 : Start calibration timer */ +#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos (0UL) /*!< Position of TASKS_CTSTART field. */ +#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Msk (0x1UL << CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos) /*!< Bit mask of TASKS_CTSTART field. */ +#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_TASKS_CTSTOP */ +/* Description: Stop calibration timer */ + +/* Bit 0 : Stop calibration timer */ +#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos (0UL) /*!< Position of TASKS_CTSTOP field. */ +#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */ +#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_EVENTS_HFCLKSTARTED */ +/* Description: HFXO crystal oscillator started */ + +/* Bit 0 : HFXO crystal oscillator started */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: CLOCK_EVENTS_LFCLKSTARTED */ +/* Description: LFCLK started */ + +/* Bit 0 : LFCLK started */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: CLOCK_EVENTS_DONE */ +/* Description: Calibration of LFRC completed */ + +/* Bit 0 : Calibration of LFRC completed */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ + +/* Register: CLOCK_EVENTS_CTTO */ +/* Description: Calibration timer timeout */ + +/* Bit 0 : Calibration timer timeout */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos (0UL) /*!< Position of EVENTS_CTTO field. */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Msk (0x1UL << CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos) /*!< Bit mask of EVENTS_CTTO field. */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Generated (1UL) /*!< Event generated */ + +/* Register: CLOCK_EVENTS_CTSTARTED */ +/* Description: Calibration timer has been started and is ready to process new tasks */ + +/* Bit 0 : Calibration timer has been started and is ready to process new tasks */ +#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos (0UL) /*!< Position of EVENTS_CTSTARTED field. */ +#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Msk (0x1UL << CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos) /*!< Bit mask of EVENTS_CTSTARTED field. */ +#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: CLOCK_EVENTS_CTSTOPPED */ +/* Description: Calibration timer has been stopped and is ready to process new tasks */ + +/* Bit 0 : Calibration timer has been stopped and is ready to process new tasks */ +#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos (0UL) /*!< Position of EVENTS_CTSTOPPED field. */ +#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Msk (0x1UL << CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos) /*!< Bit mask of EVENTS_CTSTOPPED field. */ +#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: CLOCK_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 11 : Write '1' to enable interrupt for event CTSTOPPED */ +#define CLOCK_INTENSET_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */ +#define CLOCK_INTENSET_CTSTOPPED_Msk (0x1UL << CLOCK_INTENSET_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */ +#define CLOCK_INTENSET_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_CTSTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for event CTSTARTED */ +#define CLOCK_INTENSET_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */ +#define CLOCK_INTENSET_CTSTARTED_Msk (0x1UL << CLOCK_INTENSET_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */ +#define CLOCK_INTENSET_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_CTSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event CTTO */ +#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event DONE */ +#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */ +#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */ +#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Register: CLOCK_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 11 : Write '1' to disable interrupt for event CTSTOPPED */ +#define CLOCK_INTENCLR_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */ +#define CLOCK_INTENCLR_CTSTOPPED_Msk (0x1UL << CLOCK_INTENCLR_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */ +#define CLOCK_INTENCLR_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_CTSTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for event CTSTARTED */ +#define CLOCK_INTENCLR_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */ +#define CLOCK_INTENCLR_CTSTARTED_Msk (0x1UL << CLOCK_INTENCLR_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */ +#define CLOCK_INTENCLR_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_CTSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event CTTO */ +#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event DONE */ +#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Register: CLOCK_HFCLKRUN */ +/* Description: Status indicating that HFCLKSTART task has been triggered */ + +/* Bit 0 : HFCLKSTART task triggered or not */ +#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_HFCLKSTAT */ +/* Description: HFCLK status */ + +/* Bit 16 : HFCLK state */ +#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */ +#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */ + +/* Bit 0 : Source of HFCLK */ +#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */ +#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */ + +/* Register: CLOCK_LFCLKRUN */ +/* Description: Status indicating that LFCLKSTART task has been triggered */ + +/* Bit 0 : LFCLKSTART task triggered or not */ +#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_LFCLKSTAT */ +/* Description: LFCLK status */ + +/* Bit 16 : LFCLK state */ +#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */ +#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */ + +/* Bits 1..0 : Source of LFCLK */ +#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */ +#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */ +#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */ + +/* Register: CLOCK_LFCLKSRCCOPY */ +/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */ +#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */ +#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */ + +/* Register: CLOCK_LFCLKSRC */ +/* Description: Clock source for the LFCLK */ + +/* Bit 17 : Enable or disable external source for LFCLK */ +#define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */ +#define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */ + +/* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */ +#define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */ +#define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */ +#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */ +#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */ + +/* Register: CLOCK_HFXODEBOUNCE */ +/* Description: HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. */ + +/* Bits 7..0 : HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us. */ +#define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Pos (0UL) /*!< Position of HFXODEBOUNCE field. */ +#define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Msk (0xFFUL << CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Pos) /*!< Bit mask of HFXODEBOUNCE field. */ +#define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Db256us (0x10UL) /*!< 256 us debounce time. Recommended for 1.6 mm x 2.0 mm crystals and larger. */ +#define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Db1024us (0x40UL) /*!< 1024 us debounce time. Recommended for 1.6 mm x 1.2 mm crystals and smaller. */ + +/* Register: CLOCK_LFXODEBOUNCE */ +/* Description: LFXO debounce time. The LFXO is started by triggering the TASKS_LFCLKSTART task when the LFCLKSRC register is configured for Xtal. */ + +/* Bit 0 : LFXO debounce time. */ +#define CLOCK_LFXODEBOUNCE_LFXODEBOUNCE_Pos (0UL) /*!< Position of LFXODEBOUNCE field. */ +#define CLOCK_LFXODEBOUNCE_LFXODEBOUNCE_Msk (0x1UL << CLOCK_LFXODEBOUNCE_LFXODEBOUNCE_Pos) /*!< Bit mask of LFXODEBOUNCE field. */ +#define CLOCK_LFXODEBOUNCE_LFXODEBOUNCE_Normal (0UL) /*!< 8192 32.768 kHz periods, or 0.25 s. Recommended for normal Operating Temperature conditions. */ +#define CLOCK_LFXODEBOUNCE_LFXODEBOUNCE_Extended (1UL) /*!< 16384 32.768 kHz periods, or 0.5 s. Recommended for Extended Operating Temperature conditions. */ + +/* Register: CLOCK_CTIV */ +/* Description: Calibration timer interval */ + +/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */ +#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ +#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ + + +/* Peripheral: COMP */ +/* Description: Comparator */ + +/* Register: COMP_TASKS_START */ +/* Description: Start comparator */ + +/* Bit 0 : Start comparator */ +#define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define COMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: COMP_TASKS_STOP */ +/* Description: Stop comparator */ + +/* Bit 0 : Stop comparator */ +#define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define COMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: COMP_TASKS_SAMPLE */ +/* Description: Sample comparator value */ + +/* Bit 0 : Sample comparator value */ +#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ +#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ +#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ + +/* Register: COMP_EVENTS_READY */ +/* Description: COMP is ready and output is valid */ + +/* Bit 0 : COMP is ready and output is valid */ +#define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ +#define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ + +/* Register: COMP_EVENTS_DOWN */ +/* Description: Downward crossing */ + +/* Bit 0 : Downward crossing */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */ + +/* Register: COMP_EVENTS_UP */ +/* Description: Upward crossing */ + +/* Bit 0 : Upward crossing */ +#define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */ +#define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */ +#define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */ + +/* Register: COMP_EVENTS_CROSS */ +/* Description: Downward or upward crossing */ + +/* Bit 0 : Downward or upward crossing */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */ + +/* Register: COMP_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 4 : Shortcut between event CROSS and task STOP */ +#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ +#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ +#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event UP and task STOP */ +#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ +#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ +#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between event DOWN and task STOP */ +#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ +#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ +#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between event READY and task STOP */ +#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ +#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ +#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event READY and task SAMPLE */ +#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ +#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ +#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: COMP_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 3 : Enable or disable interrupt for event CROSS */ +#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event UP */ +#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event DOWN */ +#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event READY */ +#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */ + +/* Register: COMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 3 : Write '1' to enable interrupt for event CROSS */ +#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event UP */ +#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event DOWN */ +#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event READY */ +#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: COMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 3 : Write '1' to disable interrupt for event CROSS */ +#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event UP */ +#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event DOWN */ +#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event READY */ +#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: COMP_RESULT */ +/* Description: Compare result */ + +/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ +#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ +#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ < VIN-) */ +#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ > VIN-) */ + +/* Register: COMP_ENABLE */ +/* Description: COMP enable */ + +/* Bits 1..0 : Enable or disable COMP */ +#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ + +/* Register: COMP_PSEL */ +/* Description: Pin select */ + +/* Bits 2..0 : Analog pin select */ +#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ +#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ +#define COMP_PSEL_PSEL_VddhDiv5 (7UL) /*!< VDDH/5 selected as analog input */ + +/* Register: COMP_REFSEL */ +/* Description: Reference source select for single-ended mode */ + +/* Bits 2..0 : Reference select */ +#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ +#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V) */ +#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) */ +#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) */ +#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */ +#define COMP_REFSEL_REFSEL_ARef (5UL) /*!< VREF = AREF */ + +/* Register: COMP_EXTREFSEL */ +/* Description: External reference select */ + +/* Bits 2..0 : External analog reference select */ +#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */ + +/* Register: COMP_TH */ +/* Description: Threshold configuration for hysteresis unit */ + +/* Bits 13..8 : VUP = (THUP+1)/64*VREF */ +#define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */ +#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */ + +/* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */ +#define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */ +#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */ + +/* Register: COMP_MODE */ +/* Description: Mode configuration */ + +/* Bit 8 : Main operation modes */ +#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ +#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ +#define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */ +#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */ + +/* Bits 1..0 : Speed and power modes */ +#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ +#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ +#define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */ +#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */ +#define COMP_MODE_SP_High (2UL) /*!< High-speed mode */ + +/* Register: COMP_HYST */ +/* Description: Comparator hysteresis enable */ + +/* Bit 0 : Comparator hysteresis */ +#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ +#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ +#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ +#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */ + + +/* Peripheral: ECB */ +/* Description: AES ECB Mode Encryption */ + +/* Register: ECB_TASKS_STARTECB */ +/* Description: Start ECB block encrypt */ + +/* Bit 0 : Start ECB block encrypt */ +#define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */ +#define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */ +#define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */ + +/* Register: ECB_TASKS_STOPECB */ +/* Description: Abort a possible executing ECB operation */ + +/* Bit 0 : Abort a possible executing ECB operation */ +#define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */ +#define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */ +#define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */ + +/* Register: ECB_EVENTS_ENDECB */ +/* Description: ECB block encrypt complete */ + +/* Bit 0 : ECB block encrypt complete */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */ + +/* Register: ECB_EVENTS_ERRORECB */ +/* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */ + +/* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */ + +/* Register: ECB_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 1 : Write '1' to enable interrupt for event ERRORECB */ +#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event ENDECB */ +#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */ + +/* Register: ECB_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 1 : Write '1' to disable interrupt for event ERRORECB */ +#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event ENDECB */ +#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */ + +/* Register: ECB_ECBDATAPTR */ +/* Description: ECB block encrypt memory pointers */ + +/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */ +#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */ +#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */ + + +/* Peripheral: EGU */ +/* Description: Event generator unit 0 */ + +/* Register: EGU_TASKS_TRIGGER */ +/* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */ + +/* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */ +#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ +#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */ +#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */ + +/* Register: EGU_EVENTS_TRIGGERED */ +/* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */ + +/* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */ + +/* Register: EGU_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ +#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ +#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ +#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ +#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ +#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ +#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ +#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ +#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ +#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ +#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ +#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ +#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ +#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ +#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ +#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ +#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */ + +/* Register: EGU_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ +#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ +#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ +#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ +#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ +#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ +#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ +#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ +#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ +#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ +#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ +#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ +#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ +#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ +#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ +#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ +#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */ + +/* Register: EGU_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ +#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ +#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ +#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ +#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ +#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ +#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ +#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ +#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ +#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ +#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ +#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ +#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ +#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ +#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ +#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ +#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */ + + +/* Peripheral: FICR */ +/* Description: Factory information configuration registers */ + +/* Register: FICR_CODEPAGESIZE */ +/* Description: Code memory page size */ + +/* Bits 31..0 : Code memory page size */ +#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */ +#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */ + +/* Register: FICR_CODESIZE */ +/* Description: Code memory size */ + +/* Bits 31..0 : Code memory size in number of pages */ +#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */ +#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ + +/* Register: FICR_DEVICEID */ +/* Description: Description collection: Device identifier */ + +/* Bits 31..0 : 64 bit unique device identifier */ +#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ +#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ + +/* Register: FICR_ER */ +/* Description: Description collection: Encryption root, word n */ + +/* Bits 31..0 : Encryption root, word n */ +#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */ +#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */ + +/* Register: FICR_IR */ +/* Description: Description collection: Identity Root, word n */ + +/* Bits 31..0 : Identity Root, word n */ +#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */ +#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */ + +/* Register: FICR_DEVICEADDRTYPE */ +/* Description: Device address type */ + +/* Bit 0 : Device address type */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */ + +/* Register: FICR_DEVICEADDR */ +/* Description: Description collection: Device address n */ + +/* Bits 31..0 : 48 bit device address */ +#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */ +#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */ + +/* Register: FICR_INFO_PART */ +/* Description: Part code */ + +/* Bits 31..0 : Part code */ +#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ +#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ +#define FICR_INFO_PART_PART_N52820 (0x52820UL) /*!< nRF52820 */ +#define FICR_INFO_PART_PART_N52833 (0x52833UL) /*!< nRF52833 */ +#define FICR_INFO_PART_PART_N52840 (0x52840UL) /*!< nRF52840 */ +#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_VARIANT */ +/* Description: Build code (hardware version and production configuration) */ + +/* Bits 31..0 : Build code (hardware version and production configuration). Encoded as ASCII. */ +#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ +#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_PACKAGE */ +/* Description: Package option */ + +/* Bits 31..0 : Package option */ +#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_QD (0x2007UL) /*!< QDxx - 40-pin QFN */ +#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_RAM */ +/* Description: RAM variant */ + +/* Bits 31..0 : RAM variant */ +#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ +#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ +#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */ +#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */ +#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */ +#define FICR_INFO_RAM_RAM_K128 (0x80UL) /*!< 128 kByte RAM */ +#define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kByte RAM */ +#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_FLASH */ +/* Description: Flash variant */ + +/* Bits 31..0 : Flash variant */ +#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K2048 (0x800UL) /*!< 2 MByte FLASH */ +#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_PRODTEST */ +/* Description: Description collection: Production test signature n */ + +/* Bits 31..0 : Production test signature n */ +#define FICR_PRODTEST_PRODTEST_Pos (0UL) /*!< Position of PRODTEST field. */ +#define FICR_PRODTEST_PRODTEST_Msk (0xFFFFFFFFUL << FICR_PRODTEST_PRODTEST_Pos) /*!< Bit mask of PRODTEST field. */ +#define FICR_PRODTEST_PRODTEST_Done (0xBB42319FUL) /*!< Production tests done */ +#define FICR_PRODTEST_PRODTEST_NotDone (0xFFFFFFFFUL) /*!< Production tests not done */ + +/* Register: FICR_TEMP_A0 */ +/* Description: Slope definition A0 */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A1 */ +/* Description: Slope definition A1 */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A2 */ +/* Description: Slope definition A2 */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A3 */ +/* Description: Slope definition A3 */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A4 */ +/* Description: Slope definition A4 */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A5 */ +/* Description: Slope definition A5 */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_B0 */ +/* Description: Y-intercept B0 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B1 */ +/* Description: Y-intercept B1 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B2 */ +/* Description: Y-intercept B2 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B3 */ +/* Description: Y-intercept B3 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B4 */ +/* Description: Y-intercept B4 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B5 */ +/* Description: Y-intercept B5 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_T0 */ +/* Description: Segment end T0 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T1 */ +/* Description: Segment end T1 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T2 */ +/* Description: Segment end T2 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T3 */ +/* Description: Segment end T3 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T4 */ +/* Description: Segment end T4 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */ + + +/* Peripheral: GPIOTE */ +/* Description: GPIO Tasks and Events */ + +/* Register: GPIOTE_TASKS_OUT */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ + +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ +#define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */ +#define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */ +#define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */ + +/* Register: GPIOTE_TASKS_SET */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ + +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ +#define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */ +#define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */ +#define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */ + +/* Register: GPIOTE_TASKS_CLR */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ + +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ +#define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */ +#define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */ +#define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */ + +/* Register: GPIOTE_EVENTS_IN */ +/* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */ + +/* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */ + +/* Register: GPIOTE_EVENTS_PORT */ +/* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */ + +/* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */ + +/* Register: GPIOTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 31 : Write '1' to enable interrupt for event PORT */ +#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event IN[7] */ +#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event IN[6] */ +#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event IN[5] */ +#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event IN[4] */ +#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event IN[3] */ +#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event IN[2] */ +#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event IN[1] */ +#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event IN[0] */ +#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */ + +/* Register: GPIOTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 31 : Write '1' to disable interrupt for event PORT */ +#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event IN[7] */ +#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event IN[6] */ +#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event IN[5] */ +#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event IN[4] */ +#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event IN[3] */ +#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event IN[2] */ +#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event IN[1] */ +#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event IN[0] */ +#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ + +/* Register: GPIOTE_CONFIG */ +/* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */ + +/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ +#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */ +#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */ + +/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */ +#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */ +#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ + +/* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */ +#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ +#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ + +/* Bits 1..0 : Mode */ +#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */ +#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */ +#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */ + + +/* Peripheral: NVMC */ +/* Description: Non Volatile Memory Controller */ + +/* Register: NVMC_READY */ +/* Description: Ready flag */ + +/* Bit 0 : NVMC is ready or busy */ +#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ +#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ +#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */ +#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ + +/* Register: NVMC_READYNEXT */ +/* Description: Ready flag */ + +/* Bit 0 : NVMC can accept a new write operation */ +#define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */ +#define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */ +#define NVMC_READYNEXT_READYNEXT_Busy (0UL) /*!< NVMC cannot accept any write operation */ +#define NVMC_READYNEXT_READYNEXT_Ready (1UL) /*!< NVMC is ready */ + +/* Register: NVMC_CONFIG */ +/* Description: Configuration register */ + +/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. */ +#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ +#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ +#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ +#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */ +#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */ + +/* Register: NVMC_ERASEPAGE */ +/* Description: Register for erasing a page in code area */ + +/* Bits 31..0 : Register for starting erase of a page in code area */ +#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */ +#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */ + +/* Register: NVMC_ERASEPCR1 */ +/* Description: Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE */ + +/* Bits 31..0 : Register for erasing a page in code area, equivalent to ERASEPAGE */ +#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */ +#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */ + +/* Register: NVMC_ERASEALL */ +/* Description: Register for erasing all non-volatile user memory */ + +/* Bit 0 : Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */ +#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ +#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */ + +/* Register: NVMC_ERASEPCR0 */ +/* Description: Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE */ + +/* Bits 31..0 : Register for starting erase of a page in code area, equivalent to ERASEPAGE */ +#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */ +#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */ + +/* Register: NVMC_ERASEUICR */ +/* Description: Register for erasing user information configuration registers */ + +/* Bit 0 : Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased. */ +#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */ +#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */ + +/* Register: NVMC_ERASEPAGEPARTIAL */ +/* Description: Register for partial erase of a page in code area */ + +/* Bits 31..0 : Register for starting partial erase of a page in code area */ +#define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos (0UL) /*!< Position of ERASEPAGEPARTIAL field. */ +#define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos) /*!< Bit mask of ERASEPAGEPARTIAL field. */ + +/* Register: NVMC_ERASEPAGEPARTIALCFG */ +/* Description: Register for partial erase configuration */ + +/* Bits 6..0 : Duration of the partial erase in milliseconds */ +#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */ +#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */ + + +/* Peripheral: GPIO */ +/* Description: GPIO Port 1 */ + +/* Register: GPIO_OUT */ +/* Description: Write GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */ + +/* Register: GPIO_OUTSET */ +/* Description: Set individual bits in GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Register: GPIO_OUTCLR */ +/* Description: Clear individual bits in GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Register: GPIO_IN */ +/* Description: Read GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */ + +/* Bit 30 : Pin 30 */ +#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */ + +/* Bit 29 : Pin 29 */ +#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */ + +/* Bit 28 : Pin 28 */ +#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */ + +/* Bit 27 : Pin 27 */ +#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */ + +/* Bit 26 : Pin 26 */ +#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */ + +/* Bit 25 : Pin 25 */ +#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */ + +/* Bit 24 : Pin 24 */ +#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */ + +/* Bit 23 : Pin 23 */ +#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */ + +/* Bit 22 : Pin 22 */ +#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */ + +/* Bit 21 : Pin 21 */ +#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */ + +/* Bit 20 : Pin 20 */ +#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */ + +/* Bit 19 : Pin 19 */ +#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */ + +/* Bit 18 : Pin 18 */ +#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */ + +/* Bit 17 : Pin 17 */ +#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */ + +/* Bit 16 : Pin 16 */ +#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */ + +/* Bit 15 : Pin 15 */ +#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */ + +/* Bit 14 : Pin 14 */ +#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */ + +/* Bit 13 : Pin 13 */ +#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */ + +/* Bit 12 : Pin 12 */ +#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */ + +/* Bit 11 : Pin 11 */ +#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */ + +/* Bit 10 : Pin 10 */ +#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */ + +/* Bit 9 : Pin 9 */ +#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */ + +/* Bit 8 : Pin 8 */ +#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */ + +/* Bit 7 : Pin 7 */ +#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */ + +/* Bit 6 : Pin 6 */ +#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */ + +/* Bit 5 : Pin 5 */ +#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */ + +/* Bit 4 : Pin 4 */ +#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */ + +/* Bit 3 : Pin 3 */ +#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */ + +/* Bit 2 : Pin 2 */ +#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */ + +/* Bit 1 : Pin 1 */ +#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */ + +/* Bit 0 : Pin 0 */ +#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */ + +/* Register: GPIO_DIR */ +/* Description: Direction of GPIO pins */ + +/* Bit 31 : Pin 31 */ +#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */ + +/* Bit 30 : Pin 30 */ +#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */ + +/* Bit 29 : Pin 29 */ +#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */ + +/* Bit 28 : Pin 28 */ +#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */ + +/* Bit 27 : Pin 27 */ +#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */ + +/* Bit 26 : Pin 26 */ +#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */ + +/* Bit 25 : Pin 25 */ +#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */ + +/* Bit 24 : Pin 24 */ +#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */ + +/* Bit 23 : Pin 23 */ +#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */ + +/* Bit 22 : Pin 22 */ +#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */ + +/* Bit 21 : Pin 21 */ +#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */ + +/* Bit 20 : Pin 20 */ +#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */ + +/* Bit 19 : Pin 19 */ +#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */ + +/* Bit 18 : Pin 18 */ +#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */ + +/* Bit 17 : Pin 17 */ +#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */ + +/* Bit 16 : Pin 16 */ +#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */ + +/* Bit 15 : Pin 15 */ +#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */ + +/* Bit 14 : Pin 14 */ +#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */ + +/* Bit 13 : Pin 13 */ +#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */ + +/* Bit 12 : Pin 12 */ +#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */ + +/* Bit 11 : Pin 11 */ +#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */ + +/* Bit 10 : Pin 10 */ +#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */ + +/* Bit 9 : Pin 9 */ +#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */ + +/* Bit 8 : Pin 8 */ +#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */ + +/* Bit 7 : Pin 7 */ +#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */ + +/* Bit 6 : Pin 6 */ +#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */ + +/* Bit 5 : Pin 5 */ +#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */ + +/* Bit 4 : Pin 4 */ +#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */ + +/* Bit 3 : Pin 3 */ +#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */ + +/* Bit 2 : Pin 2 */ +#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */ + +/* Bit 1 : Pin 1 */ +#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */ + +/* Bit 0 : Pin 0 */ +#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */ + +/* Register: GPIO_DIRSET */ +/* Description: DIR set register */ + +/* Bit 31 : Set as output pin 31 */ +#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 30 : Set as output pin 30 */ +#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 29 : Set as output pin 29 */ +#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 28 : Set as output pin 28 */ +#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 27 : Set as output pin 27 */ +#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 26 : Set as output pin 26 */ +#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 25 : Set as output pin 25 */ +#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 24 : Set as output pin 24 */ +#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 23 : Set as output pin 23 */ +#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 22 : Set as output pin 22 */ +#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 21 : Set as output pin 21 */ +#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 20 : Set as output pin 20 */ +#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 19 : Set as output pin 19 */ +#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 18 : Set as output pin 18 */ +#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 17 : Set as output pin 17 */ +#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 16 : Set as output pin 16 */ +#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 15 : Set as output pin 15 */ +#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 14 : Set as output pin 14 */ +#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 13 : Set as output pin 13 */ +#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 12 : Set as output pin 12 */ +#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 11 : Set as output pin 11 */ +#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 10 : Set as output pin 10 */ +#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 9 : Set as output pin 9 */ +#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 8 : Set as output pin 8 */ +#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 7 : Set as output pin 7 */ +#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 6 : Set as output pin 6 */ +#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 5 : Set as output pin 5 */ +#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 4 : Set as output pin 4 */ +#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 3 : Set as output pin 3 */ +#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 2 : Set as output pin 2 */ +#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 1 : Set as output pin 1 */ +#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 0 : Set as output pin 0 */ +#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Register: GPIO_DIRCLR */ +/* Description: DIR clear register */ + +/* Bit 31 : Set as input pin 31 */ +#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 30 : Set as input pin 30 */ +#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 29 : Set as input pin 29 */ +#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 28 : Set as input pin 28 */ +#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 27 : Set as input pin 27 */ +#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 26 : Set as input pin 26 */ +#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 25 : Set as input pin 25 */ +#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 24 : Set as input pin 24 */ +#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 23 : Set as input pin 23 */ +#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 22 : Set as input pin 22 */ +#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 21 : Set as input pin 21 */ +#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 20 : Set as input pin 20 */ +#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 19 : Set as input pin 19 */ +#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 18 : Set as input pin 18 */ +#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 17 : Set as input pin 17 */ +#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 16 : Set as input pin 16 */ +#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 15 : Set as input pin 15 */ +#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 14 : Set as input pin 14 */ +#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 13 : Set as input pin 13 */ +#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 12 : Set as input pin 12 */ +#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 11 : Set as input pin 11 */ +#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 10 : Set as input pin 10 */ +#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 9 : Set as input pin 9 */ +#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 8 : Set as input pin 8 */ +#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 7 : Set as input pin 7 */ +#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 6 : Set as input pin 6 */ +#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 5 : Set as input pin 5 */ +#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 4 : Set as input pin 4 */ +#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 3 : Set as input pin 3 */ +#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 2 : Set as input pin 2 */ +#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 1 : Set as input pin 1 */ +#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 0 : Set as input pin 0 */ +#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Register: GPIO_LATCH */ +/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ + +/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ + +/* Register: GPIO_DETECTMODE */ +/* Description: Select between default DETECT signal behaviour and LDETECT mode */ + +/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */ +#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ +#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ + +/* Register: GPIO_PIN_CNF */ +/* Description: Description collection: Configuration of GPIO pins */ + +/* Bits 17..16 : Pin sensing mechanism */ +#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */ +#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */ +#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */ + +/* Bits 10..8 : Drive configuration */ +#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */ +#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */ +#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */ +#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */ + +/* Bits 3..2 : Pull configuration */ +#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ +#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ +#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */ +#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */ +#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */ + +/* Bit 1 : Connect or disconnect input buffer */ +#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */ +#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */ + +/* Bit 0 : Pin direction. Same physical register as DIR register */ +#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ +#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ +#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */ +#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */ + + +/* Peripheral: POWER */ +/* Description: Power control */ + +/* Register: POWER_TASKS_CONSTLAT */ +/* Description: Enable Constant Latency mode */ + +/* Bit 0 : Enable Constant Latency mode */ +#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */ +#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */ +#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */ + +/* Register: POWER_TASKS_LOWPWR */ +/* Description: Enable Low-power mode (variable latency) */ + +/* Bit 0 : Enable Low-power mode (variable latency) */ +#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */ +#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */ +#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */ + +/* Register: POWER_EVENTS_POFWARN */ +/* Description: Power failure warning */ + +/* Bit 0 : Power failure warning */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */ + +/* Register: POWER_EVENTS_SLEEPENTER */ +/* Description: CPU entered WFI/WFE sleep */ + +/* Bit 0 : CPU entered WFI/WFE sleep */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */ + +/* Register: POWER_EVENTS_SLEEPEXIT */ +/* Description: CPU exited WFI/WFE sleep */ + +/* Bit 0 : CPU exited WFI/WFE sleep */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */ + +/* Register: POWER_EVENTS_USBDETECTED */ +/* Description: Voltage supply detected on VBUS */ + +/* Bit 0 : Voltage supply detected on VBUS */ +#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos (0UL) /*!< Position of EVENTS_USBDETECTED field. */ +#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Msk (0x1UL << POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos) /*!< Bit mask of EVENTS_USBDETECTED field. */ +#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Generated (1UL) /*!< Event generated */ + +/* Register: POWER_EVENTS_USBREMOVED */ +/* Description: Voltage supply removed from VBUS */ + +/* Bit 0 : Voltage supply removed from VBUS */ +#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos (0UL) /*!< Position of EVENTS_USBREMOVED field. */ +#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Msk (0x1UL << POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos) /*!< Bit mask of EVENTS_USBREMOVED field. */ +#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Generated (1UL) /*!< Event generated */ + +/* Register: POWER_EVENTS_USBPWRRDY */ +/* Description: USB 3.3 V supply ready */ + +/* Bit 0 : USB 3.3 V supply ready */ +#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos (0UL) /*!< Position of EVENTS_USBPWRRDY field. */ +#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Msk (0x1UL << POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos) /*!< Bit mask of EVENTS_USBPWRRDY field. */ +#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Generated (1UL) /*!< Event generated */ + +/* Register: POWER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 9 : Write '1' to enable interrupt for event USBPWRRDY */ +#define POWER_INTENSET_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */ +#define POWER_INTENSET_USBPWRRDY_Msk (0x1UL << POWER_INTENSET_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */ +#define POWER_INTENSET_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_USBPWRRDY_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for event USBREMOVED */ +#define POWER_INTENSET_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */ +#define POWER_INTENSET_USBREMOVED_Msk (0x1UL << POWER_INTENSET_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */ +#define POWER_INTENSET_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_USBREMOVED_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event USBDETECTED */ +#define POWER_INTENSET_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */ +#define POWER_INTENSET_USBDETECTED_Msk (0x1UL << POWER_INTENSET_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */ +#define POWER_INTENSET_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_USBDETECTED_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */ +#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */ +#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event POFWARN */ +#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */ + +/* Register: POWER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 9 : Write '1' to disable interrupt for event USBPWRRDY */ +#define POWER_INTENCLR_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */ +#define POWER_INTENCLR_USBPWRRDY_Msk (0x1UL << POWER_INTENCLR_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */ +#define POWER_INTENCLR_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_USBPWRRDY_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for event USBREMOVED */ +#define POWER_INTENCLR_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */ +#define POWER_INTENCLR_USBREMOVED_Msk (0x1UL << POWER_INTENCLR_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */ +#define POWER_INTENCLR_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_USBREMOVED_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event USBDETECTED */ +#define POWER_INTENCLR_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */ +#define POWER_INTENCLR_USBDETECTED_Msk (0x1UL << POWER_INTENCLR_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */ +#define POWER_INTENCLR_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_USBDETECTED_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */ +#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */ +#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event POFWARN */ +#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */ + +/* Register: POWER_RESETREAS */ +/* Description: Reset reason */ + +/* Bit 20 : Reset due to wake up from System OFF mode by VBUS rising into valid range */ +#define POWER_RESETREAS_VBUS_Pos (20UL) /*!< Position of VBUS field. */ +#define POWER_RESETREAS_VBUS_Msk (0x1UL << POWER_RESETREAS_VBUS_Pos) /*!< Bit mask of VBUS field. */ +#define POWER_RESETREAS_VBUS_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_VBUS_Detected (1UL) /*!< Detected */ + +/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */ +#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ +#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ +#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */ + +/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */ +#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ +#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ +#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */ + +/* Bit 3 : Reset from CPU lock-up detected */ +#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */ + +/* Bit 2 : Reset from soft reset detected */ +#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ +#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ +#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */ + +/* Bit 1 : Reset from watchdog detected */ +#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ +#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ +#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */ + +/* Bit 0 : Reset from pin-reset detected */ +#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */ + +/* Register: POWER_RAMSTATUS */ +/* Description: Deprecated register - RAM status register */ + +/* Bit 1 : RAM block 1 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */ + +/* Bit 0 : RAM block 0 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */ + +/* Register: POWER_USBREGSTATUS */ +/* Description: USB supply status */ + +/* Bit 1 : USB supply output settling time elapsed */ +#define POWER_USBREGSTATUS_OUTPUTRDY_Pos (1UL) /*!< Position of OUTPUTRDY field. */ +#define POWER_USBREGSTATUS_OUTPUTRDY_Msk (0x1UL << POWER_USBREGSTATUS_OUTPUTRDY_Pos) /*!< Bit mask of OUTPUTRDY field. */ +#define POWER_USBREGSTATUS_OUTPUTRDY_NotReady (0UL) /*!< USBREG output settling time not elapsed */ +#define POWER_USBREGSTATUS_OUTPUTRDY_Ready (1UL) /*!< USBREG output settling time elapsed (same information as USBPWRRDY event) */ + +/* Bit 0 : VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) */ +#define POWER_USBREGSTATUS_VBUSDETECT_Pos (0UL) /*!< Position of VBUSDETECT field. */ +#define POWER_USBREGSTATUS_VBUSDETECT_Msk (0x1UL << POWER_USBREGSTATUS_VBUSDETECT_Pos) /*!< Bit mask of VBUSDETECT field. */ +#define POWER_USBREGSTATUS_VBUSDETECT_NoVbus (0UL) /*!< VBUS voltage below valid threshold */ +#define POWER_USBREGSTATUS_VBUSDETECT_VbusPresent (1UL) /*!< VBUS voltage above valid threshold */ + +/* Register: POWER_SYSTEMOFF */ +/* Description: System OFF register */ + +/* Bit 0 : Enable System OFF mode */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */ + +/* Register: POWER_POFCON */ +/* Description: Power-fail comparator configuration */ + +/* Bits 11..8 : Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH). */ +#define POWER_POFCON_THRESHOLDVDDH_Pos (8UL) /*!< Position of THRESHOLDVDDH field. */ +#define POWER_POFCON_THRESHOLDVDDH_Msk (0xFUL << POWER_POFCON_THRESHOLDVDDH_Pos) /*!< Bit mask of THRESHOLDVDDH field. */ +#define POWER_POFCON_THRESHOLDVDDH_V27 (0UL) /*!< Set threshold to 2.7 V */ +#define POWER_POFCON_THRESHOLDVDDH_V28 (1UL) /*!< Set threshold to 2.8 V */ +#define POWER_POFCON_THRESHOLDVDDH_V29 (2UL) /*!< Set threshold to 2.9 V */ +#define POWER_POFCON_THRESHOLDVDDH_V30 (3UL) /*!< Set threshold to 3.0 V */ +#define POWER_POFCON_THRESHOLDVDDH_V31 (4UL) /*!< Set threshold to 3.1 V */ +#define POWER_POFCON_THRESHOLDVDDH_V32 (5UL) /*!< Set threshold to 3.2 V */ +#define POWER_POFCON_THRESHOLDVDDH_V33 (6UL) /*!< Set threshold to 3.3 V */ +#define POWER_POFCON_THRESHOLDVDDH_V34 (7UL) /*!< Set threshold to 3.4 V */ +#define POWER_POFCON_THRESHOLDVDDH_V35 (8UL) /*!< Set threshold to 3.5 V */ +#define POWER_POFCON_THRESHOLDVDDH_V36 (9UL) /*!< Set threshold to 3.6 V */ +#define POWER_POFCON_THRESHOLDVDDH_V37 (10UL) /*!< Set threshold to 3.7 V */ +#define POWER_POFCON_THRESHOLDVDDH_V38 (11UL) /*!< Set threshold to 3.8 V */ +#define POWER_POFCON_THRESHOLDVDDH_V39 (12UL) /*!< Set threshold to 3.9 V */ +#define POWER_POFCON_THRESHOLDVDDH_V40 (13UL) /*!< Set threshold to 4.0 V */ +#define POWER_POFCON_THRESHOLDVDDH_V41 (14UL) /*!< Set threshold to 4.1 V */ +#define POWER_POFCON_THRESHOLDVDDH_V42 (15UL) /*!< Set threshold to 4.2 V */ + +/* Bits 4..1 : Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages. */ +#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */ +#define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */ +#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */ +#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */ +#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */ +#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */ +#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */ +#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */ +#define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */ +#define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */ +#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */ +#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */ + +/* Bit 0 : Enable or disable power failure warning */ +#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ +#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ +#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */ +#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_GPREGRET */ +/* Description: General purpose retention register */ + +/* Bits 7..0 : General purpose retention register */ +#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_GPREGRET2 */ +/* Description: General purpose retention register */ + +/* Bits 7..0 : General purpose retention register */ +#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_DCDCEN */ +/* Description: Enable DC/DC converter for REG1 stage */ + +/* Bit 0 : Enable DC/DC converter for REG1 stage. */ +#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */ +#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_MAINREGSTATUS */ +/* Description: Main supply status */ + +/* Bit 0 : Main supply status */ +#define POWER_MAINREGSTATUS_MAINREGSTATUS_Pos (0UL) /*!< Position of MAINREGSTATUS field. */ +#define POWER_MAINREGSTATUS_MAINREGSTATUS_Msk (0x1UL << POWER_MAINREGSTATUS_MAINREGSTATUS_Pos) /*!< Bit mask of MAINREGSTATUS field. */ +#define POWER_MAINREGSTATUS_MAINREGSTATUS_Normal (0UL) /*!< Normal voltage mode. Voltage supplied on VDD. */ +#define POWER_MAINREGSTATUS_MAINREGSTATUS_High (1UL) /*!< High voltage mode. Voltage supplied on VDDH. */ + +/* Register: POWER_RAM_POWER */ +/* Description: Description cluster: RAMn power control register */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is off */ +#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is off */ +#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 on or off in System ON mode. */ +#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 on or off in System ON mode. */ +#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */ + +/* Register: POWER_RAM_POWERSET */ +/* Description: Description cluster: RAMn power control set register */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ + +/* Register: POWER_RAM_POWERCLR */ +/* Description: Description cluster: RAMn power control clear register */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */ + +/* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */ + +/* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */ + + +/* Peripheral: PPI */ +/* Description: Programmable Peripheral Interconnect */ + +/* Register: PPI_TASKS_CHG_EN */ +/* Description: Description cluster: Enable channel group n */ + +/* Bit 0 : Enable channel group n */ +#define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */ +#define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ +#define PPI_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */ + +/* Register: PPI_TASKS_CHG_DIS */ +/* Description: Description cluster: Disable channel group n */ + +/* Bit 0 : Disable channel group n */ +#define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */ +#define PPI_TASKS_CHG_DIS_DIS_Msk (0x1UL << PPI_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */ +#define PPI_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */ + +/* Register: PPI_CHEN */ +/* Description: Channel enable register */ + +/* Bit 31 : Enable or disable channel 31 */ +#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */ + +/* Bit 30 : Enable or disable channel 30 */ +#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */ + +/* Bit 29 : Enable or disable channel 29 */ +#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */ + +/* Bit 28 : Enable or disable channel 28 */ +#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */ + +/* Bit 27 : Enable or disable channel 27 */ +#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */ + +/* Bit 26 : Enable or disable channel 26 */ +#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */ + +/* Bit 25 : Enable or disable channel 25 */ +#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */ + +/* Bit 24 : Enable or disable channel 24 */ +#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */ + +/* Bit 23 : Enable or disable channel 23 */ +#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */ + +/* Bit 22 : Enable or disable channel 22 */ +#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */ + +/* Bit 21 : Enable or disable channel 21 */ +#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */ + +/* Bit 20 : Enable or disable channel 20 */ +#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */ + +/* Bit 19 : Enable or disable channel 19 */ +#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */ + +/* Bit 18 : Enable or disable channel 18 */ +#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */ + +/* Bit 17 : Enable or disable channel 17 */ +#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */ + +/* Bit 16 : Enable or disable channel 16 */ +#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */ + +/* Bit 15 : Enable or disable channel 15 */ +#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */ + +/* Bit 14 : Enable or disable channel 14 */ +#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */ + +/* Bit 13 : Enable or disable channel 13 */ +#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */ + +/* Bit 12 : Enable or disable channel 12 */ +#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */ + +/* Bit 11 : Enable or disable channel 11 */ +#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */ + +/* Bit 10 : Enable or disable channel 10 */ +#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */ + +/* Bit 9 : Enable or disable channel 9 */ +#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */ + +/* Bit 8 : Enable or disable channel 8 */ +#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */ + +/* Bit 7 : Enable or disable channel 7 */ +#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */ + +/* Bit 6 : Enable or disable channel 6 */ +#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */ + +/* Bit 5 : Enable or disable channel 5 */ +#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */ + +/* Bit 4 : Enable or disable channel 4 */ +#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */ + +/* Bit 3 : Enable or disable channel 3 */ +#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */ + +/* Bit 2 : Enable or disable channel 2 */ +#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */ + +/* Bit 1 : Enable or disable channel 1 */ +#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */ + +/* Bit 0 : Enable or disable channel 0 */ +#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */ + +/* Register: PPI_CHENSET */ +/* Description: Channel enable set register */ + +/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */ + +/* Register: PPI_CHENCLR */ +/* Description: Channel enable clear register */ + +/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ + +/* Register: PPI_CH_EEP */ +/* Description: Description cluster: Channel n event end-point */ + +/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ +#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ +#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ + +/* Register: PPI_CH_TEP */ +/* Description: Description cluster: Channel n task end-point */ + +/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ +#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ +#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ + +/* Register: PPI_CHG */ +/* Description: Description collection: Channel group n */ + +/* Bit 31 : Include or exclude channel 31 */ +#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH31_Included (1UL) /*!< Include */ + +/* Bit 30 : Include or exclude channel 30 */ +#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH30_Included (1UL) /*!< Include */ + +/* Bit 29 : Include or exclude channel 29 */ +#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH29_Included (1UL) /*!< Include */ + +/* Bit 28 : Include or exclude channel 28 */ +#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH28_Included (1UL) /*!< Include */ + +/* Bit 27 : Include or exclude channel 27 */ +#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH27_Included (1UL) /*!< Include */ + +/* Bit 26 : Include or exclude channel 26 */ +#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH26_Included (1UL) /*!< Include */ + +/* Bit 25 : Include or exclude channel 25 */ +#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH25_Included (1UL) /*!< Include */ + +/* Bit 24 : Include or exclude channel 24 */ +#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH24_Included (1UL) /*!< Include */ + +/* Bit 23 : Include or exclude channel 23 */ +#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH23_Included (1UL) /*!< Include */ + +/* Bit 22 : Include or exclude channel 22 */ +#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH22_Included (1UL) /*!< Include */ + +/* Bit 21 : Include or exclude channel 21 */ +#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH21_Included (1UL) /*!< Include */ + +/* Bit 20 : Include or exclude channel 20 */ +#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH20_Included (1UL) /*!< Include */ + +/* Bit 19 : Include or exclude channel 19 */ +#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH19_Included (1UL) /*!< Include */ + +/* Bit 18 : Include or exclude channel 18 */ +#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH18_Included (1UL) /*!< Include */ + +/* Bit 17 : Include or exclude channel 17 */ +#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH17_Included (1UL) /*!< Include */ + +/* Bit 16 : Include or exclude channel 16 */ +#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH16_Included (1UL) /*!< Include */ + +/* Bit 15 : Include or exclude channel 15 */ +#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH15_Included (1UL) /*!< Include */ + +/* Bit 14 : Include or exclude channel 14 */ +#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH14_Included (1UL) /*!< Include */ + +/* Bit 13 : Include or exclude channel 13 */ +#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH13_Included (1UL) /*!< Include */ + +/* Bit 12 : Include or exclude channel 12 */ +#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH12_Included (1UL) /*!< Include */ + +/* Bit 11 : Include or exclude channel 11 */ +#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH11_Included (1UL) /*!< Include */ + +/* Bit 10 : Include or exclude channel 10 */ +#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH10_Included (1UL) /*!< Include */ + +/* Bit 9 : Include or exclude channel 9 */ +#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH9_Included (1UL) /*!< Include */ + +/* Bit 8 : Include or exclude channel 8 */ +#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH8_Included (1UL) /*!< Include */ + +/* Bit 7 : Include or exclude channel 7 */ +#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH7_Included (1UL) /*!< Include */ + +/* Bit 6 : Include or exclude channel 6 */ +#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH6_Included (1UL) /*!< Include */ + +/* Bit 5 : Include or exclude channel 5 */ +#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH5_Included (1UL) /*!< Include */ + +/* Bit 4 : Include or exclude channel 4 */ +#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH4_Included (1UL) /*!< Include */ + +/* Bit 3 : Include or exclude channel 3 */ +#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH3_Included (1UL) /*!< Include */ + +/* Bit 2 : Include or exclude channel 2 */ +#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH2_Included (1UL) /*!< Include */ + +/* Bit 1 : Include or exclude channel 1 */ +#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH1_Included (1UL) /*!< Include */ + +/* Bit 0 : Include or exclude channel 0 */ +#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH0_Included (1UL) /*!< Include */ + +/* Register: PPI_FORK_TEP */ +/* Description: Description cluster: Channel n task end-point */ + +/* Bits 31..0 : Pointer to task register */ +#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ +#define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ + + +/* Peripheral: QDEC */ +/* Description: Quadrature Decoder */ + +/* Register: QDEC_TASKS_START */ +/* Description: Task starting the quadrature decoder */ + +/* Bit 0 : Task starting the quadrature decoder */ +#define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define QDEC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: QDEC_TASKS_STOP */ +/* Description: Task stopping the quadrature decoder */ + +/* Bit 0 : Task stopping the quadrature decoder */ +#define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define QDEC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: QDEC_TASKS_READCLRACC */ +/* Description: Read and clear ACC and ACCDBL */ + +/* Bit 0 : Read and clear ACC and ACCDBL */ +#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */ +#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */ +#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (1UL) /*!< Trigger task */ + +/* Register: QDEC_TASKS_RDCLRACC */ +/* Description: Read and clear ACC */ + +/* Bit 0 : Read and clear ACC */ +#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */ +#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */ +#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (1UL) /*!< Trigger task */ + +/* Register: QDEC_TASKS_RDCLRDBL */ +/* Description: Read and clear ACCDBL */ + +/* Bit 0 : Read and clear ACCDBL */ +#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */ +#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */ +#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (1UL) /*!< Trigger task */ + +/* Register: QDEC_EVENTS_SAMPLERDY */ +/* Description: Event being generated for every new sample value written to the SAMPLE register */ + +/* Bit 0 : Event being generated for every new sample value written to the SAMPLE register */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (1UL) /*!< Event generated */ + +/* Register: QDEC_EVENTS_REPORTRDY */ +/* Description: Non-null report ready */ + +/* Bit 0 : Non-null report ready */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (1UL) /*!< Event generated */ + +/* Register: QDEC_EVENTS_ACCOF */ +/* Description: ACC or ACCDBL register overflow */ + +/* Bit 0 : ACC or ACCDBL register overflow */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (1UL) /*!< Event generated */ + +/* Register: QDEC_EVENTS_DBLRDY */ +/* Description: Double displacement(s) detected */ + +/* Bit 0 : Double displacement(s) detected */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (1UL) /*!< Event generated */ + +/* Register: QDEC_EVENTS_STOPPED */ +/* Description: QDEC has been stopped */ + +/* Bit 0 : QDEC has been stopped */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: QDEC_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between event DBLRDY and task STOP */ +#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event REPORTRDY and task STOP */ +#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between event SAMPLERDY and task STOP */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: QDEC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 4 : Write '1' to enable interrupt for event STOPPED */ +#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event DBLRDY */ +#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event ACCOF */ +#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event REPORTRDY */ +#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */ +#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */ + +/* Register: QDEC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 4 : Write '1' to disable interrupt for event STOPPED */ +#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event DBLRDY */ +#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event ACCOF */ +#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event REPORTRDY */ +#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */ +#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */ + +/* Register: QDEC_ENABLE */ +/* Description: Enable the quadrature decoder */ + +/* Bit 0 : Enable or disable the quadrature decoder */ +#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: QDEC_LEDPOL */ +/* Description: LED output pin polarity */ + +/* Bit 0 : LED output pin polarity */ +#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */ +#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */ + +/* Register: QDEC_SAMPLEPER */ +/* Description: Sample period */ + +/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */ +#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */ + +/* Register: QDEC_SAMPLE */ +/* Description: Motion sample value */ + +/* Bits 31..0 : Last motion sample */ +#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ +#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ + +/* Register: QDEC_REPORTPER */ +/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ + +/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */ +#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */ +#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */ +#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */ +#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */ +#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */ +#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */ +#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */ +#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */ +#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */ + +/* Register: QDEC_ACC */ +/* Description: Register accumulating the valid transitions */ + +/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */ +#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ +#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ + +/* Register: QDEC_ACCREAD */ +/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */ + +/* Bits 31..0 : Snapshot of the ACC register. */ +#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */ +#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */ + +/* Register: QDEC_PSEL_LED */ +/* Description: Pin select for LED signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_A */ +/* Description: Pin select for A signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_B */ +/* Description: Pin select for B signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_DBFEN */ +/* Description: Enable input debounce filters */ + +/* Bit 0 : Enable input debounce filters */ +#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */ +#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */ + +/* Register: QDEC_LEDPRE */ +/* Description: Time period the LED is switched ON prior to sampling */ + +/* Bits 8..0 : Period in us the LED is switched on prior to sampling */ +#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ +#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ + +/* Register: QDEC_ACCDBL */ +/* Description: Register accumulating the number of detected double transitions */ + +/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */ +#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ +#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ + +/* Register: QDEC_ACCDBLREAD */ +/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */ + +/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ + + +/* Peripheral: RADIO */ +/* Description: 2.4 GHz radio */ + +/* Register: RADIO_TASKS_TXEN */ +/* Description: Enable RADIO in TX mode */ + +/* Bit 0 : Enable RADIO in TX mode */ +#define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */ +#define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */ +#define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_RXEN */ +/* Description: Enable RADIO in RX mode */ + +/* Bit 0 : Enable RADIO in RX mode */ +#define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */ +#define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */ +#define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_START */ +/* Description: Start RADIO */ + +/* Bit 0 : Start RADIO */ +#define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RADIO_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_STOP */ +/* Description: Stop RADIO */ + +/* Bit 0 : Stop RADIO */ +#define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_DISABLE */ +/* Description: Disable RADIO */ + +/* Bit 0 : Disable RADIO */ +#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ +#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */ +#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_RSSISTART */ +/* Description: Start the RSSI and take one single sample of the receive signal strength */ + +/* Bit 0 : Start the RSSI and take one single sample of the receive signal strength */ +#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */ +#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */ +#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_RSSISTOP */ +/* Description: Stop the RSSI measurement */ + +/* Bit 0 : Stop the RSSI measurement */ +#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */ +#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */ +#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_BCSTART */ +/* Description: Start the bit counter */ + +/* Bit 0 : Start the bit counter */ +#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */ +#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */ +#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_BCSTOP */ +/* Description: Stop the bit counter */ + +/* Bit 0 : Stop the bit counter */ +#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */ +#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */ +#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_EDSTART */ +/* Description: Start the energy detect measurement used in IEEE 802.15.4 mode */ + +/* Bit 0 : Start the energy detect measurement used in IEEE 802.15.4 mode */ +#define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field. */ +#define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART field. */ +#define RADIO_TASKS_EDSTART_TASKS_EDSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_EDSTOP */ +/* Description: Stop the energy detect measurement */ + +/* Bit 0 : Stop the energy detect measurement */ +#define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL) /*!< Position of TASKS_EDSTOP field. */ +#define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP field. */ +#define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_CCASTART */ +/* Description: Start the clear channel assessment used in IEEE 802.15.4 mode */ + +/* Bit 0 : Start the clear channel assessment used in IEEE 802.15.4 mode */ +#define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field. */ +#define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of TASKS_CCASTART field. */ +#define RADIO_TASKS_CCASTART_TASKS_CCASTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_CCASTOP */ +/* Description: Stop the clear channel assessment */ + +/* Bit 0 : Stop the clear channel assessment */ +#define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field. */ +#define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos) /*!< Bit mask of TASKS_CCASTOP field. */ +#define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_EVENTS_READY */ +/* Description: RADIO has ramped up and is ready to be started */ + +/* Bit 0 : RADIO has ramped up and is ready to be started */ +#define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ +#define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_ADDRESS */ +/* Description: Address sent or received */ + +/* Bit 0 : Address sent or received */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_PAYLOAD */ +/* Description: Packet payload sent or received */ + +/* Bit 0 : Packet payload sent or received */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_END */ +/* Description: Packet sent or received */ + +/* Bit 0 : Packet sent or received */ +#define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_DISABLED */ +/* Description: RADIO has been disabled */ + +/* Bit 0 : RADIO has been disabled */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_DEVMATCH */ +/* Description: A device address match occurred on the last received packet */ + +/* Bit 0 : A device address match occurred on the last received packet */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_DEVMISS */ +/* Description: No device address match occurred on the last received packet */ + +/* Bit 0 : No device address match occurred on the last received packet */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_RSSIEND */ +/* Description: Sampling of receive signal strength complete */ + +/* Bit 0 : Sampling of receive signal strength complete */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_BCMATCH */ +/* Description: Bit counter reached bit count value */ + +/* Bit 0 : Bit counter reached bit count value */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_CRCOK */ +/* Description: Packet received with CRC ok */ + +/* Bit 0 : Packet received with CRC ok */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_CRCERROR */ +/* Description: Packet received with CRC error */ + +/* Bit 0 : Packet received with CRC error */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_FRAMESTART */ +/* Description: IEEE 802.15.4 length field received */ + +/* Bit 0 : IEEE 802.15.4 length field received */ +#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */ +#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of EVENTS_FRAMESTART field. */ +#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_EDEND */ +/* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register */ + +/* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register */ +#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */ +#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */ +#define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_EDSTOPPED */ +/* Description: The sampling of energy detection has stopped */ + +/* Bit 0 : The sampling of energy detection has stopped */ +#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field. */ +#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos) /*!< Bit mask of EVENTS_EDSTOPPED field. */ +#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_CCAIDLE */ +/* Description: Wireless medium in idle - clear to send */ + +/* Bit 0 : Wireless medium in idle - clear to send */ +#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL) /*!< Position of EVENTS_CCAIDLE field. */ +#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos) /*!< Bit mask of EVENTS_CCAIDLE field. */ +#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_CCABUSY */ +/* Description: Wireless medium busy - do not send */ + +/* Bit 0 : Wireless medium busy - do not send */ +#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL) /*!< Position of EVENTS_CCABUSY field. */ +#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos) /*!< Bit mask of EVENTS_CCABUSY field. */ +#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_CCASTOPPED */ +/* Description: The CCA has stopped */ + +/* Bit 0 : The CCA has stopped */ +#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL) /*!< Position of EVENTS_CCASTOPPED field. */ +#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos) /*!< Bit mask of EVENTS_CCASTOPPED field. */ +#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_RATEBOOST */ +/* Description: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */ + +/* Bit 0 : Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */ +#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL) /*!< Position of EVENTS_RATEBOOST field. */ +#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos) /*!< Bit mask of EVENTS_RATEBOOST field. */ +#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_TXREADY */ +/* Description: RADIO has ramped up and is ready to be started TX path */ + +/* Bit 0 : RADIO has ramped up and is ready to be started TX path */ +#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field. */ +#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of EVENTS_TXREADY field. */ +#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_RXREADY */ +/* Description: RADIO has ramped up and is ready to be started RX path */ + +/* Bit 0 : RADIO has ramped up and is ready to be started RX path */ +#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */ +#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of EVENTS_RXREADY field. */ +#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_MHRMATCH */ +/* Description: MAC header match found */ + +/* Bit 0 : MAC header match found */ +#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */ +#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of EVENTS_MHRMATCH field. */ +#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_SYNC */ +/* Description: Preamble indicator */ + +/* Bit 0 : Preamble indicator */ +#define RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos (0UL) /*!< Position of EVENTS_SYNC field. */ +#define RADIO_EVENTS_SYNC_EVENTS_SYNC_Msk (0x1UL << RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos) /*!< Bit mask of EVENTS_SYNC field. */ +#define RADIO_EVENTS_SYNC_EVENTS_SYNC_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_SYNC_EVENTS_SYNC_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_PHYEND */ +/* Description: Generated when last bit is sent on air, or received from air */ + +/* Bit 0 : Generated when last bit is sent on air, or received from air */ +#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */ +#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */ +#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_CTEPRESENT */ +/* Description: CTE is present (early warning right after receiving CTEInfo byte) */ + +/* Bit 0 : CTE is present (early warning right after receiving CTEInfo byte) */ +#define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos (0UL) /*!< Position of EVENTS_CTEPRESENT field. */ +#define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Msk (0x1UL << RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos) /*!< Bit mask of EVENTS_CTEPRESENT field. */ +#define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 21 : Shortcut between event PHYEND and task START */ +#define RADIO_SHORTS_PHYEND_START_Pos (21UL) /*!< Position of PHYEND_START field. */ +#define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field. */ +#define RADIO_SHORTS_PHYEND_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_PHYEND_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 20 : Shortcut between event PHYEND and task DISABLE */ +#define RADIO_SHORTS_PHYEND_DISABLE_Pos (20UL) /*!< Position of PHYEND_DISABLE field. */ +#define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field. */ +#define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_PHYEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 19 : Shortcut between event RXREADY and task START */ +#define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */ +#define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */ +#define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 18 : Shortcut between event TXREADY and task START */ +#define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */ +#define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */ +#define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 17 : Shortcut between event CCAIDLE and task STOP */ +#define RADIO_SHORTS_CCAIDLE_STOP_Pos (17UL) /*!< Position of CCAIDLE_STOP field. */ +#define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */ +#define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_CCAIDLE_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 16 : Shortcut between event EDEND and task DISABLE */ +#define RADIO_SHORTS_EDEND_DISABLE_Pos (16UL) /*!< Position of EDEND_DISABLE field. */ +#define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */ +#define RADIO_SHORTS_EDEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_EDEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 15 : Shortcut between event READY and task EDSTART */ +#define RADIO_SHORTS_READY_EDSTART_Pos (15UL) /*!< Position of READY_EDSTART field. */ +#define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */ +#define RADIO_SHORTS_READY_EDSTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_READY_EDSTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 14 : Shortcut between event FRAMESTART and task BCSTART */ +#define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (14UL) /*!< Position of FRAMESTART_BCSTART field. */ +#define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART field. */ +#define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 13 : Shortcut between event CCABUSY and task DISABLE */ +#define RADIO_SHORTS_CCABUSY_DISABLE_Pos (13UL) /*!< Position of CCABUSY_DISABLE field. */ +#define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */ +#define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 12 : Shortcut between event CCAIDLE and task TXEN */ +#define RADIO_SHORTS_CCAIDLE_TXEN_Pos (12UL) /*!< Position of CCAIDLE_TXEN field. */ +#define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */ +#define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 11 : Shortcut between event RXREADY and task CCASTART */ +#define RADIO_SHORTS_RXREADY_CCASTART_Pos (11UL) /*!< Position of RXREADY_CCASTART field. */ +#define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART field. */ +#define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_RXREADY_CCASTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 6 : Shortcut between event ADDRESS and task BCSTART */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between event END and task START */ +#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ +#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event DISABLED and task RXEN */ +#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between event DISABLED and task TXEN */ +#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between event END and task DISABLE */ +#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event READY and task START */ +#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ +#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ +#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: RADIO_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 28 : Write '1' to enable interrupt for event CTEPRESENT */ +#define RADIO_INTENSET_CTEPRESENT_Pos (28UL) /*!< Position of CTEPRESENT field. */ +#define RADIO_INTENSET_CTEPRESENT_Msk (0x1UL << RADIO_INTENSET_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */ +#define RADIO_INTENSET_CTEPRESENT_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CTEPRESENT_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CTEPRESENT_Set (1UL) /*!< Enable */ + +/* Bit 27 : Write '1' to enable interrupt for event PHYEND */ +#define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ +#define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ +#define RADIO_INTENSET_PHYEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */ + +/* Bit 26 : Write '1' to enable interrupt for event SYNC */ +#define RADIO_INTENSET_SYNC_Pos (26UL) /*!< Position of SYNC field. */ +#define RADIO_INTENSET_SYNC_Msk (0x1UL << RADIO_INTENSET_SYNC_Pos) /*!< Bit mask of SYNC field. */ +#define RADIO_INTENSET_SYNC_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_SYNC_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_SYNC_Set (1UL) /*!< Enable */ + +/* Bit 23 : Write '1' to enable interrupt for event MHRMATCH */ +#define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ +#define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ +#define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */ + +/* Bit 22 : Write '1' to enable interrupt for event RXREADY */ +#define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ +#define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ +#define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */ + +/* Bit 21 : Write '1' to enable interrupt for event TXREADY */ +#define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ +#define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ +#define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event RATEBOOST */ +#define RADIO_INTENSET_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ +#define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ +#define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_RATEBOOST_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */ +#define RADIO_INTENSET_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ +#define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ +#define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CCASTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for event CCABUSY */ +#define RADIO_INTENSET_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ +#define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ +#define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CCABUSY_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for event CCAIDLE */ +#define RADIO_INTENSET_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ +#define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ +#define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CCAIDLE_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */ +#define RADIO_INTENSET_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ +#define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ +#define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_EDSTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 15 : Write '1' to enable interrupt for event EDEND */ +#define RADIO_INTENSET_EDEND_Pos (15UL) /*!< Position of EDEND field. */ +#define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos) /*!< Bit mask of EDEND field. */ +#define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_EDEND_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for event FRAMESTART */ +#define RADIO_INTENSET_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ +#define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ +#define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to enable interrupt for event CRCERROR */ +#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ +#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to enable interrupt for event CRCOK */ +#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ +#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ +#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for event BCMATCH */ +#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event RSSIEND */ +#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event DEVMISS */ +#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */ +#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event DISABLED */ +#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event END */ +#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */ +#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event ADDRESS */ +#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event READY */ +#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: RADIO_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 28 : Write '1' to disable interrupt for event CTEPRESENT */ +#define RADIO_INTENCLR_CTEPRESENT_Pos (28UL) /*!< Position of CTEPRESENT field. */ +#define RADIO_INTENCLR_CTEPRESENT_Msk (0x1UL << RADIO_INTENCLR_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */ +#define RADIO_INTENCLR_CTEPRESENT_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CTEPRESENT_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CTEPRESENT_Clear (1UL) /*!< Disable */ + +/* Bit 27 : Write '1' to disable interrupt for event PHYEND */ +#define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ +#define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ +#define RADIO_INTENCLR_PHYEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */ + +/* Bit 26 : Write '1' to disable interrupt for event SYNC */ +#define RADIO_INTENCLR_SYNC_Pos (26UL) /*!< Position of SYNC field. */ +#define RADIO_INTENCLR_SYNC_Msk (0x1UL << RADIO_INTENCLR_SYNC_Pos) /*!< Bit mask of SYNC field. */ +#define RADIO_INTENCLR_SYNC_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_SYNC_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_SYNC_Clear (1UL) /*!< Disable */ + +/* Bit 23 : Write '1' to disable interrupt for event MHRMATCH */ +#define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ +#define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ +#define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 22 : Write '1' to disable interrupt for event RXREADY */ +#define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ +#define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ +#define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */ + +/* Bit 21 : Write '1' to disable interrupt for event TXREADY */ +#define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ +#define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ +#define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event RATEBOOST */ +#define RADIO_INTENCLR_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ +#define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ +#define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_RATEBOOST_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */ +#define RADIO_INTENCLR_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ +#define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ +#define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CCASTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for event CCABUSY */ +#define RADIO_INTENCLR_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ +#define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ +#define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CCABUSY_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for event CCAIDLE */ +#define RADIO_INTENCLR_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ +#define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ +#define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CCAIDLE_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */ +#define RADIO_INTENCLR_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ +#define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ +#define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_EDSTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 15 : Write '1' to disable interrupt for event EDEND */ +#define RADIO_INTENCLR_EDEND_Pos (15UL) /*!< Position of EDEND field. */ +#define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos) /*!< Bit mask of EDEND field. */ +#define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_EDEND_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for event FRAMESTART */ +#define RADIO_INTENCLR_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ +#define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ +#define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to disable interrupt for event CRCERROR */ +#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ +#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to disable interrupt for event CRCOK */ +#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ +#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ +#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for event BCMATCH */ +#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event RSSIEND */ +#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event DEVMISS */ +#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */ +#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event DISABLED */ +#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event END */ +#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */ +#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event ADDRESS */ +#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event READY */ +#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: RADIO_CRCSTATUS */ +/* Description: CRC status */ + +/* Bit 0 : CRC status of packet received */ +#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */ + +/* Register: RADIO_RXMATCH */ +/* Description: Received address */ + +/* Bits 2..0 : Received address */ +#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ +#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ + +/* Register: RADIO_RXCRC */ +/* Description: CRC field of previously received packet */ + +/* Bits 23..0 : CRC field of previously received packet */ +#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ +#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ + +/* Register: RADIO_DAI */ +/* Description: Device address match index */ + +/* Bits 2..0 : Device address match index */ +#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ +#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ + +/* Register: RADIO_PDUSTAT */ +/* Description: Payload status */ + +/* Bits 2..1 : Status on what rate packet is received with in Long Range */ +#define RADIO_PDUSTAT_CISTAT_Pos (1UL) /*!< Position of CISTAT field. */ +#define RADIO_PDUSTAT_CISTAT_Msk (0x3UL << RADIO_PDUSTAT_CISTAT_Pos) /*!< Bit mask of CISTAT field. */ +#define RADIO_PDUSTAT_CISTAT_LR125kbit (0UL) /*!< Frame is received at 125 kbps */ +#define RADIO_PDUSTAT_CISTAT_LR500kbit (1UL) /*!< Frame is received at 500 kbps */ + +/* Bit 0 : Status on payload length vs. PCNF1.MAXLEN */ +#define RADIO_PDUSTAT_PDUSTAT_Pos (0UL) /*!< Position of PDUSTAT field. */ +#define RADIO_PDUSTAT_PDUSTAT_Msk (0x1UL << RADIO_PDUSTAT_PDUSTAT_Pos) /*!< Bit mask of PDUSTAT field. */ +#define RADIO_PDUSTAT_PDUSTAT_LessThan (0UL) /*!< Payload less than PCNF1.MAXLEN */ +#define RADIO_PDUSTAT_PDUSTAT_GreaterThan (1UL) /*!< Payload greater than PCNF1.MAXLEN */ + +/* Register: RADIO_CTESTATUS */ +/* Description: CTEInfo parsed from received packet */ + +/* Bits 7..6 : CTEType parsed from packet */ +#define RADIO_CTESTATUS_CTETYPE_Pos (6UL) /*!< Position of CTETYPE field. */ +#define RADIO_CTESTATUS_CTETYPE_Msk (0x3UL << RADIO_CTESTATUS_CTETYPE_Pos) /*!< Bit mask of CTETYPE field. */ + +/* Bit 5 : RFU parsed from packet */ +#define RADIO_CTESTATUS_RFU_Pos (5UL) /*!< Position of RFU field. */ +#define RADIO_CTESTATUS_RFU_Msk (0x1UL << RADIO_CTESTATUS_RFU_Pos) /*!< Bit mask of RFU field. */ + +/* Bits 4..0 : CTETime parsed from packet */ +#define RADIO_CTESTATUS_CTETIME_Pos (0UL) /*!< Position of CTETIME field. */ +#define RADIO_CTESTATUS_CTETIME_Msk (0x1FUL << RADIO_CTESTATUS_CTETIME_Pos) /*!< Bit mask of CTETIME field. */ + +/* Register: RADIO_DFESTATUS */ +/* Description: DFE status information */ + +/* Bit 4 : Internal state of sampling state machine */ +#define RADIO_DFESTATUS_SAMPLINGSTATE_Pos (4UL) /*!< Position of SAMPLINGSTATE field. */ +#define RADIO_DFESTATUS_SAMPLINGSTATE_Msk (0x1UL << RADIO_DFESTATUS_SAMPLINGSTATE_Pos) /*!< Bit mask of SAMPLINGSTATE field. */ +#define RADIO_DFESTATUS_SAMPLINGSTATE_Idle (0UL) /*!< Sampling state Idle */ +#define RADIO_DFESTATUS_SAMPLINGSTATE_Sampling (1UL) /*!< Sampling state Sampling */ + +/* Bits 2..0 : Internal state of switching state machine */ +#define RADIO_DFESTATUS_SWITCHINGSTATE_Pos (0UL) /*!< Position of SWITCHINGSTATE field. */ +#define RADIO_DFESTATUS_SWITCHINGSTATE_Msk (0x7UL << RADIO_DFESTATUS_SWITCHINGSTATE_Pos) /*!< Bit mask of SWITCHINGSTATE field. */ +#define RADIO_DFESTATUS_SWITCHINGSTATE_Idle (0UL) /*!< Switching state Idle */ +#define RADIO_DFESTATUS_SWITCHINGSTATE_Offset (1UL) /*!< Switching state Offset */ +#define RADIO_DFESTATUS_SWITCHINGSTATE_Guard (2UL) /*!< Switching state Guard */ +#define RADIO_DFESTATUS_SWITCHINGSTATE_Ref (3UL) /*!< Switching state Ref */ +#define RADIO_DFESTATUS_SWITCHINGSTATE_Switching (4UL) /*!< Switching state Switching */ +#define RADIO_DFESTATUS_SWITCHINGSTATE_Ending (5UL) /*!< Switching state Ending */ + +/* Register: RADIO_PACKETPTR */ +/* Description: Packet pointer */ + +/* Bits 31..0 : Packet pointer */ +#define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */ +#define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */ + +/* Register: RADIO_FREQUENCY */ +/* Description: Frequency */ + +/* Bit 8 : Channel map selection. */ +#define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ +#define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ +#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */ +#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */ + +/* Bits 6..0 : Radio channel frequency */ +#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ + +/* Register: RADIO_TXPOWER */ +/* Description: Output power */ + +/* Bits 7..0 : RADIO output power */ +#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_0dBm (0x0UL) /*!< 0 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos2dBm (0x2UL) /*!< +2 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x3UL) /*!< +3 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x4UL) /*!< +4 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos5dBm (0x5UL) /*!< +5 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos6dBm (0x6UL) /*!< +6 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos7dBm (0x7UL) /*!< +7 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos8dBm (0x8UL) /*!< +8 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL) /*!< Deprecated enumerator - -40 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ + +/* Register: RADIO_MODE */ +/* Description: Data rate and modulation */ + +/* Bits 3..0 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */ +#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbps Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbps Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbps BLE */ +#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbps BLE */ +#define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long range 125 kbps TX, 125 kbps and 500 kbps RX */ +#define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long range 500 kbps TX, 125 kbps and 500 kbps RX */ +#define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbps */ + +/* Register: RADIO_PCNF0 */ +/* Description: Packet configuration register 0 */ + +/* Bits 30..29 : Length of TERM field in Long Range operation */ +#define RADIO_PCNF0_TERMLEN_Pos (29UL) /*!< Position of TERMLEN field. */ +#define RADIO_PCNF0_TERMLEN_Msk (0x3UL << RADIO_PCNF0_TERMLEN_Pos) /*!< Bit mask of TERMLEN field. */ + +/* Bit 26 : Indicates if LENGTH field contains CRC or not */ +#define RADIO_PCNF0_CRCINC_Pos (26UL) /*!< Position of CRCINC field. */ +#define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field. */ +#define RADIO_PCNF0_CRCINC_Exclude (0UL) /*!< LENGTH does not contain CRC */ +#define RADIO_PCNF0_CRCINC_Include (1UL) /*!< LENGTH includes CRC */ + +/* Bits 25..24 : Length of preamble on air. Decision point: TASKS_START task */ +#define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */ +#define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */ +#define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */ +#define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */ +#define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */ +#define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for BLE long range */ + +/* Bits 23..22 : Length of code indicator - long range */ +#define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */ +#define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */ + +/* Bit 20 : Include or exclude S1 field in RAM */ +#define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */ +#define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */ +#define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ +#define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ + +/* Bits 19..16 : Length on air of S1 field in number of bits. */ +#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ +#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ + +/* Bit 8 : Length on air of S0 field in number of bytes. */ +#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ +#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ + +/* Bits 3..0 : Length on air of LENGTH field in number of bits. */ +#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ +#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ + +/* Register: RADIO_PCNF1 */ +/* Description: Packet configuration register 1 */ + +/* Bit 25 : Enable or disable packet whitening */ +#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */ +#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. */ +#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */ +#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ + +/* Bits 18..16 : Base address length in number of bytes */ +#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ +#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ + +/* Bits 15..8 : Static length in number of bytes */ +#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ +#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ + +/* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */ +#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ +#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + +/* Register: RADIO_BASE0 */ +/* Description: Base address 0 */ + +/* Bits 31..0 : Base address 0 */ +#define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */ +#define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */ + +/* Register: RADIO_BASE1 */ +/* Description: Base address 1 */ + +/* Bits 31..0 : Base address 1 */ +#define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */ +#define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */ + +/* Register: RADIO_PREFIX0 */ +/* Description: Prefixes bytes for logical addresses 0-3 */ + +/* Bits 31..24 : Address prefix 3. */ +#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ +#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ + +/* Bits 23..16 : Address prefix 2. */ +#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ +#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ + +/* Bits 15..8 : Address prefix 1. */ +#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ +#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ + +/* Bits 7..0 : Address prefix 0. */ +#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ +#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ + +/* Register: RADIO_PREFIX1 */ +/* Description: Prefixes bytes for logical addresses 4-7 */ + +/* Bits 31..24 : Address prefix 7. */ +#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ +#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ + +/* Bits 23..16 : Address prefix 6. */ +#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ +#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ + +/* Bits 15..8 : Address prefix 5. */ +#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ +#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ + +/* Bits 7..0 : Address prefix 4. */ +#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ +#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ + +/* Register: RADIO_TXADDRESS */ +/* Description: Transmit address select */ + +/* Bits 2..0 : Transmit address select */ +#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ +#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ + +/* Register: RADIO_RXADDRESSES */ +/* Description: Receive address select */ + +/* Bit 7 : Enable or disable reception on logical address 7. */ +#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable reception on logical address 6. */ +#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable reception on logical address 5. */ +#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable reception on logical address 4. */ +#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable reception on logical address 3. */ +#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable reception on logical address 2. */ +#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable reception on logical address 1. */ +#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable reception on logical address 0. */ +#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */ + +/* Register: RADIO_CRCCNF */ +/* Description: CRC configuration */ + +/* Bits 9..8 : Include or exclude packet address field out of CRC calculation. */ +#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Msk (0x3UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */ +#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ +#define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after length field. */ + +/* Bits 1..0 : CRC length in number of bytes. */ +#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ +#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ +#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ +#define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */ +#define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */ +#define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */ + +/* Register: RADIO_CRCPOLY */ +/* Description: CRC polynomial */ + +/* Bits 23..0 : CRC polynomial */ +#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ +#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ + +/* Register: RADIO_CRCINIT */ +/* Description: CRC initial value */ + +/* Bits 23..0 : CRC initial value */ +#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ +#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ + +/* Register: RADIO_TIFS */ +/* Description: Interframe spacing in us */ + +/* Bits 9..0 : Interframe spacing in us */ +#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ +#define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ + +/* Register: RADIO_RSSISAMPLE */ +/* Description: RSSI sample */ + +/* Bits 6..0 : RSSI sample */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ + +/* Register: RADIO_STATE */ +/* Description: Current radio state */ + +/* Bits 3..0 : Current radio state */ +#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ +#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ +#define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */ +#define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */ +#define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */ +#define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */ +#define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */ +#define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */ +#define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */ +#define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */ +#define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */ + +/* Register: RADIO_DATAWHITEIV */ +/* Description: Data whitening initial value */ + +/* Bits 6..0 : Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ + +/* Register: RADIO_BCC */ +/* Description: Bit counter compare */ + +/* Bits 31..0 : Bit counter compare */ +#define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */ +#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ + +/* Register: RADIO_DAB */ +/* Description: Description collection: Device address base segment n */ + +/* Bits 31..0 : Device address base segment n */ +#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ +#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ + +/* Register: RADIO_DAP */ +/* Description: Description collection: Device address prefix n */ + +/* Bits 15..0 : Device address prefix n */ +#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ +#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ + +/* Register: RADIO_DACNF */ +/* Description: Device address match configuration */ + +/* Bit 15 : TxAdd for device address 7 */ +#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ +#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ + +/* Bit 14 : TxAdd for device address 6 */ +#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ +#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ + +/* Bit 13 : TxAdd for device address 5 */ +#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ +#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ + +/* Bit 12 : TxAdd for device address 4 */ +#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ +#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ + +/* Bit 11 : TxAdd for device address 3 */ +#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ +#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ + +/* Bit 10 : TxAdd for device address 2 */ +#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ +#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ + +/* Bit 9 : TxAdd for device address 1 */ +#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ +#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ + +/* Bit 8 : TxAdd for device address 0 */ +#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ +#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ + +/* Bit 7 : Enable or disable device address matching using device address 7 */ +#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ +#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ +#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */ + +/* Bit 6 : Enable or disable device address matching using device address 6 */ +#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ +#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ +#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */ + +/* Bit 5 : Enable or disable device address matching using device address 5 */ +#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ +#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ +#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */ + +/* Bit 4 : Enable or disable device address matching using device address 4 */ +#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ +#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ +#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */ + +/* Bit 3 : Enable or disable device address matching using device address 3 */ +#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ +#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ +#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */ + +/* Bit 2 : Enable or disable device address matching using device address 2 */ +#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ +#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ +#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */ + +/* Bit 1 : Enable or disable device address matching using device address 1 */ +#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ +#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ +#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */ + +/* Bit 0 : Enable or disable device address matching using device address 0 */ +#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ +#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ +#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */ + +/* Register: RADIO_MHRMATCHCONF */ +/* Description: Search pattern configuration */ + +/* Bits 31..0 : Search pattern configuration */ +#define RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos (0UL) /*!< Position of MHRMATCHCONF field. */ +#define RADIO_MHRMATCHCONF_MHRMATCHCONF_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos) /*!< Bit mask of MHRMATCHCONF field. */ + +/* Register: RADIO_MHRMATCHMAS */ +/* Description: Pattern mask */ + +/* Bits 31..0 : Pattern mask */ +#define RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos (0UL) /*!< Position of MHRMATCHMAS field. */ +#define RADIO_MHRMATCHMAS_MHRMATCHMAS_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos) /*!< Bit mask of MHRMATCHMAS field. */ + +/* Register: RADIO_MODECNF0 */ +/* Description: Radio mode configuration register 0 */ + +/* Bits 9..8 : Default TX value */ +#define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */ +#define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */ +#define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */ +#define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */ +#define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */ + +/* Bit 0 : Radio ramp-up time */ +#define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ +#define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ +#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */ +#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information */ + +/* Register: RADIO_SFD */ +/* Description: IEEE 802.15.4 start of frame delimiter */ + +/* Bits 7..0 : IEEE 802.15.4 start of frame delimiter */ +#define RADIO_SFD_SFD_Pos (0UL) /*!< Position of SFD field. */ +#define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field. */ + +/* Register: RADIO_EDCNT */ +/* Description: IEEE 802.15.4 energy detect loop count */ + +/* Bits 20..0 : IEEE 802.15.4 energy detect loop count */ +#define RADIO_EDCNT_EDCNT_Pos (0UL) /*!< Position of EDCNT field. */ +#define RADIO_EDCNT_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCNT_EDCNT_Pos) /*!< Bit mask of EDCNT field. */ + +/* Register: RADIO_EDSAMPLE */ +/* Description: IEEE 802.15.4 energy detect level */ + +/* Bits 7..0 : IEEE 802.15.4 energy detect level */ +#define RADIO_EDSAMPLE_EDLVL_Pos (0UL) /*!< Position of EDLVL field. */ +#define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field. */ + +/* Register: RADIO_CCACTRL */ +/* Description: IEEE 802.15.4 clear channel assessment control */ + +/* Bits 31..24 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. */ +#define RADIO_CCACTRL_CCACORRCNT_Pos (24UL) /*!< Position of CCACORRCNT field. */ +#define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field. */ + +/* Bits 23..16 : CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode. */ +#define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL) /*!< Position of CCACORRTHRES field. */ +#define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field. */ + +/* Bits 15..8 : CCA energy busy threshold. Used in all the CCA modes except CarrierMode. */ +#define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL) /*!< Position of CCAEDTHRES field. */ +#define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field. */ + +/* Bits 2..0 : CCA mode of operation */ +#define RADIO_CCACTRL_CCAMODE_Pos (0UL) /*!< Position of CCAMODE field. */ +#define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field. */ +#define RADIO_CCACTRL_CCAMODE_EdMode (0UL) /*!< Energy above threshold */ +#define RADIO_CCACTRL_CCAMODE_CarrierMode (1UL) /*!< Carrier seen */ +#define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (2UL) /*!< Energy above threshold AND carrier seen */ +#define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL) /*!< Energy above threshold OR carrier seen */ +#define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL) /*!< Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */ + +/* Register: RADIO_DFEMODE */ +/* Description: Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) */ + +/* Bits 1..0 : Direction finding operation mode */ +#define RADIO_DFEMODE_DFEOPMODE_Pos (0UL) /*!< Position of DFEOPMODE field. */ +#define RADIO_DFEMODE_DFEOPMODE_Msk (0x3UL << RADIO_DFEMODE_DFEOPMODE_Pos) /*!< Bit mask of DFEOPMODE field. */ +#define RADIO_DFEMODE_DFEOPMODE_Disabled (0UL) /*!< Direction finding mode disabled */ +#define RADIO_DFEMODE_DFEOPMODE_AoD (2UL) /*!< Direction finding mode set to AoD */ +#define RADIO_DFEMODE_DFEOPMODE_AoA (3UL) /*!< Direction finding mode set to AoA */ + +/* Register: RADIO_CTEINLINECONF */ +/* Description: Configuration for CTE inline mode */ + +/* Bits 31..24 : S0 bit mask to set which bit to match */ +#define RADIO_CTEINLINECONF_S0MASK_Pos (24UL) /*!< Position of S0MASK field. */ +#define RADIO_CTEINLINECONF_S0MASK_Msk (0xFFUL << RADIO_CTEINLINECONF_S0MASK_Pos) /*!< Bit mask of S0MASK field. */ + +/* Bits 23..16 : S0 bit pattern to match */ +#define RADIO_CTEINLINECONF_S0CONF_Pos (16UL) /*!< Position of S0CONF field. */ +#define RADIO_CTEINLINECONF_S0CONF_Msk (0xFFUL << RADIO_CTEINLINECONF_S0CONF_Pos) /*!< Bit mask of S0CONF field. */ + +/* Bits 15..13 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos (13UL) /*!< Position of CTEINLINERXMODE2US field. */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos) /*!< Bit mask of CTEINLINERXMODE2US field. */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (1UL) /*!< 4us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (2UL) /*!< 2us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (3UL) /*!< 1us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (4UL) /*!< 0.5us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (5UL) /*!< 0.25us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (6UL) /*!< 0.125us */ + +/* Bits 12..10 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos (10UL) /*!< Position of CTEINLINERXMODE1US field. */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos) /*!< Bit mask of CTEINLINERXMODE1US field. */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (1UL) /*!< 4us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (2UL) /*!< 2us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (3UL) /*!< 1us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (4UL) /*!< 0.5us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (5UL) /*!< 0.25us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (6UL) /*!< 0.125us */ + +/* Bits 7..6 : Max range of CTETime */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos (6UL) /*!< Position of CTETIMEVALIDRANGE field. */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Msk (0x3UL << RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos) /*!< Bit mask of CTETIMEVALIDRANGE field. */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0UL) /*!< 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20 */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (1UL) /*!< 31 in 8us unit */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (2UL) /*!< 63 in 8us unit */ + +/* Bit 4 : Sampling/switching if CRC is not OK */ +#define RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos (4UL) /*!< Position of CTEERRORHANDLING field. */ +#define RADIO_CTEINLINECONF_CTEERRORHANDLING_Msk (0x1UL << RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos) /*!< Bit mask of CTEERRORHANDLING field. */ +#define RADIO_CTEINLINECONF_CTEERRORHANDLING_No (0UL) /*!< No sampling and antenna switching when CRC is not OK */ +#define RADIO_CTEINLINECONF_CTEERRORHANDLING_Yes (1UL) /*!< Sampling and antenna switching also when CRC is not OK */ + +/* Bit 3 : CTEInfo is S1 byte or not */ +#define RADIO_CTEINLINECONF_CTEINFOINS1_Pos (3UL) /*!< Position of CTEINFOINS1 field. */ +#define RADIO_CTEINLINECONF_CTEINFOINS1_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINFOINS1_Pos) /*!< Bit mask of CTEINFOINS1 field. */ +#define RADIO_CTEINLINECONF_CTEINFOINS1_NotInS1 (0UL) /*!< CTEInfo is NOT in S1 byte (advertising PDU) */ +#define RADIO_CTEINLINECONF_CTEINFOINS1_InS1 (1UL) /*!< CTEInfo is in S1 byte (data PDU) */ + +/* Bit 0 : Enable parsing of CTEInfo from received packet in BLE modes */ +#define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos (0UL) /*!< Position of CTEINLINECTRLEN field. */ +#define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos) /*!< Bit mask of CTEINLINECTRLEN field. */ +#define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Disabled (0UL) /*!< Parsing of CTEInfo is disabled */ +#define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Enabled (1UL) /*!< Parsing of CTEInfo is enabled */ + +/* Register: RADIO_DFECTRL1 */ +/* Description: Various configuration for Direction finding */ + +/* Bits 27..24 : Gain will be lowered by the specified number of gain steps at the start of CTE */ +#define RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos (24UL) /*!< Position of AGCBACKOFFGAIN field. */ +#define RADIO_DFECTRL1_AGCBACKOFFGAIN_Msk (0xFUL << RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos) /*!< Bit mask of AGCBACKOFFGAIN field. */ + +/* Bits 23..20 : Repeat each individual antenna pattern N times sequentially, i.e. P0, P0, P1, P1, P2, P2, P3, P3, etc. */ +#define RADIO_DFECTRL1_REPEATPATTERN_Pos (20UL) /*!< Position of REPEATPATTERN field. */ +#define RADIO_DFECTRL1_REPEATPATTERN_Msk (0xFUL << RADIO_DFECTRL1_REPEATPATTERN_Pos) /*!< Bit mask of REPEATPATTERN field. */ +#define RADIO_DFECTRL1_REPEATPATTERN_NoRepeat (0UL) /*!< Do not repeat (1 time in total) */ + +/* Bits 18..16 : Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 */ +#define RADIO_DFECTRL1_TSAMPLESPACING_Pos (16UL) /*!< Position of TSAMPLESPACING field. */ +#define RADIO_DFECTRL1_TSAMPLESPACING_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACING_Pos) /*!< Bit mask of TSAMPLESPACING field. */ +#define RADIO_DFECTRL1_TSAMPLESPACING_4us (1UL) /*!< 4us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_2us (2UL) /*!< 2us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_1us (3UL) /*!< 1us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_500ns (4UL) /*!< 0.5us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_250ns (5UL) /*!< 0.25us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_125ns (6UL) /*!< 0.125us */ + +/* Bit 15 : Whether to sample I/Q or magnitude/phase */ +#define RADIO_DFECTRL1_SAMPLETYPE_Pos (15UL) /*!< Position of SAMPLETYPE field. */ +#define RADIO_DFECTRL1_SAMPLETYPE_Msk (0x1UL << RADIO_DFECTRL1_SAMPLETYPE_Pos) /*!< Bit mask of SAMPLETYPE field. */ +#define RADIO_DFECTRL1_SAMPLETYPE_IQ (0UL) /*!< Complex samples in I and Q */ +#define RADIO_DFECTRL1_SAMPLETYPE_MagPhase (1UL) /*!< Complex samples as magnitude and phase */ + +/* Bits 14..12 : Interval between samples in the REFERENCE period */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos (12UL) /*!< Position of TSAMPLESPACINGREF field. */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos) /*!< Bit mask of TSAMPLESPACINGREF field. */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (1UL) /*!< 4us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (2UL) /*!< 2us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (3UL) /*!< 1us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (4UL) /*!< 0.5us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (5UL) /*!< 0.25us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (6UL) /*!< 0.125us */ + +/* Bits 10..8 : Interval between every time the antenna is changed in the SWITCHING state */ +#define RADIO_DFECTRL1_TSWITCHSPACING_Pos (8UL) /*!< Position of TSWITCHSPACING field. */ +#define RADIO_DFECTRL1_TSWITCHSPACING_Msk (0x7UL << RADIO_DFECTRL1_TSWITCHSPACING_Pos) /*!< Bit mask of TSWITCHSPACING field. */ +#define RADIO_DFECTRL1_TSWITCHSPACING_4us (1UL) /*!< 4us */ +#define RADIO_DFECTRL1_TSWITCHSPACING_2us (2UL) /*!< 2us */ +#define RADIO_DFECTRL1_TSWITCHSPACING_1us (3UL) /*!< 1us */ + +/* Bit 7 : Add CTE extension and do antenna switching/sampling in this extension */ +#define RADIO_DFECTRL1_DFEINEXTENSION_Pos (7UL) /*!< Position of DFEINEXTENSION field. */ +#define RADIO_DFECTRL1_DFEINEXTENSION_Msk (0x1UL << RADIO_DFECTRL1_DFEINEXTENSION_Pos) /*!< Bit mask of DFEINEXTENSION field. */ +#define RADIO_DFECTRL1_DFEINEXTENSION_Payload (0UL) /*!< Antenna switching/sampling is done in the packet payload */ +#define RADIO_DFECTRL1_DFEINEXTENSION_CRC (1UL) /*!< AoA/AoD procedure triggered at end of CRC */ + +/* Bits 5..0 : Length of the AoA/AoD procedure in number of 8 us units */ +#define RADIO_DFECTRL1_NUMBEROF8US_Pos (0UL) /*!< Position of NUMBEROF8US field. */ +#define RADIO_DFECTRL1_NUMBEROF8US_Msk (0x3FUL << RADIO_DFECTRL1_NUMBEROF8US_Pos) /*!< Bit mask of NUMBEROF8US field. */ + +/* Register: RADIO_DFECTRL2 */ +/* Description: Start offset for Direction finding */ + +/* Bits 27..16 : Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start */ +#define RADIO_DFECTRL2_TSAMPLEOFFSET_Pos (16UL) /*!< Position of TSAMPLEOFFSET field. */ +#define RADIO_DFECTRL2_TSAMPLEOFFSET_Msk (0xFFFUL << RADIO_DFECTRL2_TSAMPLEOFFSET_Pos) /*!< Bit mask of TSAMPLEOFFSET field. */ + +/* Bits 12..0 : Signed value offset after the end of the CRC before starting switching in number of 16M cycles */ +#define RADIO_DFECTRL2_TSWITCHOFFSET_Pos (0UL) /*!< Position of TSWITCHOFFSET field. */ +#define RADIO_DFECTRL2_TSWITCHOFFSET_Msk (0x1FFFUL << RADIO_DFECTRL2_TSWITCHOFFSET_Pos) /*!< Bit mask of TSWITCHOFFSET field. */ + +/* Register: RADIO_SWITCHPATTERN */ +/* Description: GPIO patterns to be used for each antenna */ + +/* Bits 7..0 : Fill array of GPIO patterns for antenna control */ +#define RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos (0UL) /*!< Position of SWITCHPATTERN field. */ +#define RADIO_SWITCHPATTERN_SWITCHPATTERN_Msk (0xFFUL << RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos) /*!< Bit mask of SWITCHPATTERN field. */ + +/* Register: RADIO_CLEARPATTERN */ +/* Description: Clear the GPIO pattern array for antenna control */ + +/* Bit 0 : Clears GPIO pattern array for antenna control */ +#define RADIO_CLEARPATTERN_CLEARPATTERN_Pos (0UL) /*!< Position of CLEARPATTERN field. */ +#define RADIO_CLEARPATTERN_CLEARPATTERN_Msk (0x1UL << RADIO_CLEARPATTERN_CLEARPATTERN_Pos) /*!< Bit mask of CLEARPATTERN field. */ +#define RADIO_CLEARPATTERN_CLEARPATTERN_Clear (1UL) /*!< Clear the GPIO pattern */ + +/* Register: RADIO_PSEL_DFEGPIO */ +/* Description: Description collection: Pin select for DFE pin n */ + +/* Bit 31 : Connection */ +#define RADIO_PSEL_DFEGPIO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define RADIO_PSEL_DFEGPIO_CONNECT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define RADIO_PSEL_DFEGPIO_CONNECT_Connected (0UL) /*!< Connect */ +#define RADIO_PSEL_DFEGPIO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define RADIO_PSEL_DFEGPIO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define RADIO_PSEL_DFEGPIO_PIN_Msk (0x1FUL << RADIO_PSEL_DFEGPIO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: RADIO_DFEPACKET_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define RADIO_DFEPACKET_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define RADIO_DFEPACKET_PTR_PTR_Msk (0xFFFFFFFFUL << RADIO_DFEPACKET_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: RADIO_DFEPACKET_MAXCNT */ +/* Description: Maximum number of buffer words to transfer */ + +/* Bits 13..0 : Maximum number of buffer words to transfer */ +#define RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define RADIO_DFEPACKET_MAXCNT_MAXCNT_Msk (0x3FFFUL << RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: RADIO_DFEPACKET_AMOUNT */ +/* Description: Number of samples transferred in the last transaction */ + +/* Bits 15..0 : Number of samples transferred in the last transaction */ +#define RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define RADIO_DFEPACKET_AMOUNT_AMOUNT_Msk (0xFFFFUL << RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: RADIO_POWER */ +/* Description: Peripheral power control */ + +/* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */ +#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */ +#define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */ + + +/* Peripheral: RNG */ +/* Description: Random Number Generator */ + +/* Register: RNG_TASKS_START */ +/* Description: Task starting the random number generator */ + +/* Bit 0 : Task starting the random number generator */ +#define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RNG_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: RNG_TASKS_STOP */ +/* Description: Task stopping the random number generator */ + +/* Bit 0 : Task stopping the random number generator */ +#define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RNG_EVENTS_VALRDY */ +/* Description: Event being generated for every new random number written to the VALUE register */ + +/* Bit 0 : Event being generated for every new random number written to the VALUE register */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL) /*!< Event not generated */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL) /*!< Event generated */ + +/* Register: RNG_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 0 : Shortcut between event VALRDY and task STOP */ +#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: RNG_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to enable interrupt for event VALRDY */ +#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ +#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */ +#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */ + +/* Register: RNG_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to disable interrupt for event VALRDY */ +#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ +#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */ +#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */ + +/* Register: RNG_CONFIG */ +/* Description: Configuration register */ + +/* Bit 0 : Bias correction */ +#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */ +#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */ + +/* Register: RNG_VALUE */ +/* Description: Output random number */ + +/* Bits 7..0 : Generated random number */ +#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ +#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + +/* Peripheral: RTC */ +/* Description: Real time counter 0 */ + +/* Register: RTC_TASKS_START */ +/* Description: Start RTC COUNTER */ + +/* Bit 0 : Start RTC COUNTER */ +#define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: RTC_TASKS_STOP */ +/* Description: Stop RTC COUNTER */ + +/* Bit 0 : Stop RTC COUNTER */ +#define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RTC_TASKS_CLEAR */ +/* Description: Clear RTC COUNTER */ + +/* Bit 0 : Clear RTC COUNTER */ +#define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ +#define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ +#define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ + +/* Register: RTC_TASKS_TRIGOVRFLW */ +/* Description: Set COUNTER to 0xFFFFF0 */ + +/* Bit 0 : Set COUNTER to 0xFFFFF0 */ +#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */ +#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */ +#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */ + +/* Register: RTC_EVENTS_TICK */ +/* Description: Event on COUNTER increment */ + +/* Bit 0 : Event on COUNTER increment */ +#define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */ +#define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */ +#define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */ + +/* Register: RTC_EVENTS_OVRFLW */ +/* Description: Event on COUNTER overflow */ + +/* Bit 0 : Event on COUNTER overflow */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */ + +/* Register: RTC_EVENTS_COMPARE */ +/* Description: Description collection: Compare event on CC[n] match */ + +/* Bit 0 : Compare event on CC[n] match */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ + +/* Register: RTC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ +#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ +#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ +#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ +#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event OVRFLW */ +#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event TICK */ +#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ +#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ +#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ +#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ +#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event OVRFLW */ +#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event TICK */ +#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_EVTEN */ +/* Description: Enable or disable event routing */ + +/* Bit 19 : Enable or disable event routing for event COMPARE[3] */ +#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Disable */ + +/* Bit 18 : Enable or disable event routing for event COMPARE[2] */ +#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Disable */ + +/* Bit 17 : Enable or disable event routing for event COMPARE[1] */ +#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Disable */ + +/* Bit 16 : Enable or disable event routing for event COMPARE[0] */ +#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Disable */ + +/* Bit 1 : Enable or disable event routing for event OVRFLW */ +#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Disable */ + +/* Bit 0 : Enable or disable event routing for event TICK */ +#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Disable */ + +/* Register: RTC_EVTENSET */ +/* Description: Enable event routing */ + +/* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */ +#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */ +#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */ +#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */ +#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable event routing for event OVRFLW */ +#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable event routing for event TICK */ +#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_EVTENCLR */ +/* Description: Disable event routing */ + +/* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */ +#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */ +#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */ +#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */ +#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable event routing for event OVRFLW */ +#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable event routing for event TICK */ +#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_COUNTER */ +/* Description: Current COUNTER value */ + +/* Bits 23..0 : Counter value */ +#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ +#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ + +/* Register: RTC_PRESCALER */ +/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */ + +/* Bits 11..0 : Prescaler value */ +#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: RTC_CC */ +/* Description: Description collection: Compare register n */ + +/* Bits 23..0 : Compare value */ +#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ +#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ + + +/* Peripheral: SPI */ +/* Description: Serial Peripheral Interface 0 */ + +/* Register: SPI_EVENTS_READY */ +/* Description: TXD byte sent and RXD byte received */ + +/* Bit 0 : TXD byte sent and RXD byte received */ +#define SPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ +#define SPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << SPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define SPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define SPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ + +/* Register: SPI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to enable interrupt for event READY */ +#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: SPI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to disable interrupt for event READY */ +#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: SPI_ENABLE */ +/* Description: Enable SPI */ + +/* Bits 3..0 : Enable or disable SPI */ +#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */ +#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */ + +/* Register: SPI_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPI_PSEL_SCK_CONNECT_Msk (0x1UL << SPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPI_PSEL_SCK_PIN_Msk (0x1FUL << SPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPI_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPI_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPI_PSEL_MOSI_CONNECT_Msk (0x1UL << SPI_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPI_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPI_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPI_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPI_PSEL_MOSI_PIN_Msk (0x1FUL << SPI_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPI_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPI_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPI_PSEL_MISO_CONNECT_Msk (0x1UL << SPI_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPI_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPI_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPI_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPI_PSEL_MISO_PIN_Msk (0x1FUL << SPI_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPI_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RX data received. Double buffered */ +#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: SPI_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TX data to send. Double buffered */ +#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: SPI_FREQUENCY */ +/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : SPI master data rate */ +#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ + +/* Register: SPI_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + + +/* Peripheral: SPIM */ +/* Description: Serial Peripheral Interface Master with EasyDMA 0 */ + +/* Register: SPIM_TASKS_START */ +/* Description: Start SPI transaction */ + +/* Bit 0 : Start SPI transaction */ +#define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIM_TASKS_STOP */ +/* Description: Stop SPI transaction */ + +/* Bit 0 : Stop SPI transaction */ +#define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIM_TASKS_SUSPEND */ +/* Description: Suspend SPI transaction */ + +/* Bit 0 : Suspend SPI transaction */ +#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIM_TASKS_RESUME */ +/* Description: Resume SPI transaction */ + +/* Bit 0 : Resume SPI transaction */ +#define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIM_EVENTS_STOPPED */ +/* Description: SPI transaction has stopped */ + +/* Bit 0 : SPI transaction has stopped */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: SPIM_EVENTS_ENDRX */ +/* Description: End of RXD buffer reached */ + +/* Bit 0 : End of RXD buffer reached */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ + +/* Register: SPIM_EVENTS_END */ +/* Description: End of RXD buffer and TXD buffer reached */ + +/* Bit 0 : End of RXD buffer and TXD buffer reached */ +#define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ + +/* Register: SPIM_EVENTS_ENDTX */ +/* Description: End of TXD buffer reached */ + +/* Bit 0 : End of TXD buffer reached */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ + +/* Register: SPIM_EVENTS_STARTED */ +/* Description: Transaction started */ + +/* Bit 0 : Transaction started */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ + +/* Register: SPIM_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 17 : Shortcut between event END and task START */ +#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ +#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ +#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to enable interrupt for event STARTED */ +#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for event ENDTX */ +#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event END */ +#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ +#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: SPIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to disable interrupt for event STARTED */ +#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for event ENDTX */ +#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event END */ +#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ +#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: SPIM_ENABLE */ +/* Description: Enable SPIM */ + +/* Bits 3..0 : Enable or disable SPIM */ +#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */ +#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */ + +/* Register: SPIM_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_FREQUENCY */ +/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : SPI master data rate */ +#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ + +/* Register: SPIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 14..0 : Maximum number of bytes in receive buffer */ +#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 14..0 : Number of bytes transferred in the last transaction */ +#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_TXD_MAXCNT */ +/* Description: Number of bytes in transmit buffer */ + +/* Bits 14..0 : Maximum number of bytes in transmit buffer */ +#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 14..0 : Number of bytes transferred in the last transaction */ +#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIM_ORC */ +/* Description: Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT */ + +/* Bits 7..0 : Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. */ +#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: SPIS */ +/* Description: SPI Slave 0 */ + +/* Register: SPIS_TASKS_ACQUIRE */ +/* Description: Acquire SPI semaphore */ + +/* Bit 0 : Acquire SPI semaphore */ +#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */ +#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */ +#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIS_TASKS_RELEASE */ +/* Description: Release SPI semaphore, enabling the SPI slave to acquire it */ + +/* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */ +#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */ +#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */ +#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIS_EVENTS_END */ +/* Description: Granted transaction completed */ + +/* Bit 0 : Granted transaction completed */ +#define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ + +/* Register: SPIS_EVENTS_ENDRX */ +/* Description: End of RXD buffer reached */ + +/* Bit 0 : End of RXD buffer reached */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ + +/* Register: SPIS_EVENTS_ACQUIRED */ +/* Description: Semaphore acquired */ + +/* Bit 0 : Semaphore acquired */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */ + +/* Register: SPIS_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 2 : Shortcut between event END and task ACQUIRE */ +#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ +#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */ +#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ +#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event END */ +#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Register: SPIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */ +#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ +#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event END */ +#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Register: SPIS_SEMSTAT */ +/* Description: Semaphore status register */ + +/* Bits 1..0 : Semaphore status */ +#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */ +#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */ +#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */ +#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */ + +/* Register: SPIS_STATUS */ +/* Description: Status from last transaction */ + +/* Bit 1 : RX buffer overflow detected, and prevented */ +#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Bit 0 : TX buffer over-read detected, and prevented */ +#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Register: SPIS_ENABLE */ +/* Description: Enable SPI slave */ + +/* Bits 3..0 : Enable or disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */ + +/* Register: SPIS_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_CSN */ +/* Description: Pin select for CSN signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_RXD_PTR */ +/* Description: RXD data pointer */ + +/* Bits 31..0 : RXD data pointer */ +#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 14..0 : Maximum number of bytes in receive buffer */ +#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_RXD_AMOUNT */ +/* Description: Number of bytes received in last granted transaction */ + +/* Bits 14..0 : Number of bytes received in the last granted transaction */ +#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIS_TXD_PTR */ +/* Description: TXD data pointer */ + +/* Bits 31..0 : TXD data pointer */ +#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 14..0 : Maximum number of bytes in transmit buffer */ +#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_TXD_AMOUNT */ +/* Description: Number of bytes transmitted in last granted transaction */ + +/* Bits 14..0 : Number of bytes transmitted in last granted transaction */ +#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIS_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIS_DEF */ +/* Description: Default character. Character clocked out in case of an ignored transaction. */ + +/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */ +#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ +#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ + +/* Register: SPIS_ORC */ +/* Description: Over-read character */ + +/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */ +#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: TEMP */ +/* Description: Temperature Sensor */ + +/* Register: TEMP_TASKS_START */ +/* Description: Start temperature measurement */ + +/* Bit 0 : Start temperature measurement */ +#define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: TEMP_TASKS_STOP */ +/* Description: Stop temperature measurement */ + +/* Bit 0 : Stop temperature measurement */ +#define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: TEMP_EVENTS_DATARDY */ +/* Description: Temperature measurement complete, data ready */ + +/* Bit 0 : Temperature measurement complete, data ready */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */ + +/* Register: TEMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to enable interrupt for event DATARDY */ +#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ +#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */ +#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */ + +/* Register: TEMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to disable interrupt for event DATARDY */ +#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ +#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */ +#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */ + +/* Register: TEMP_TEMP */ +/* Description: Temperature in degC (0.25deg steps) */ + +/* Bits 31..0 : Temperature in degC (0.25deg steps) */ +#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */ +#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ + +/* Register: TEMP_A0 */ +/* Description: Slope of 1st piece wise linear function */ + +/* Bits 11..0 : Slope of 1st piece wise linear function */ +#define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ +#define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ + +/* Register: TEMP_A1 */ +/* Description: Slope of 2nd piece wise linear function */ + +/* Bits 11..0 : Slope of 2nd piece wise linear function */ +#define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ +#define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ + +/* Register: TEMP_A2 */ +/* Description: Slope of 3rd piece wise linear function */ + +/* Bits 11..0 : Slope of 3rd piece wise linear function */ +#define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ +#define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ + +/* Register: TEMP_A3 */ +/* Description: Slope of 4th piece wise linear function */ + +/* Bits 11..0 : Slope of 4th piece wise linear function */ +#define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ +#define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ + +/* Register: TEMP_A4 */ +/* Description: Slope of 5th piece wise linear function */ + +/* Bits 11..0 : Slope of 5th piece wise linear function */ +#define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ +#define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ + +/* Register: TEMP_A5 */ +/* Description: Slope of 6th piece wise linear function */ + +/* Bits 11..0 : Slope of 6th piece wise linear function */ +#define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ +#define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ + +/* Register: TEMP_B0 */ +/* Description: y-intercept of 1st piece wise linear function */ + +/* Bits 13..0 : y-intercept of 1st piece wise linear function */ +#define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ +#define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ + +/* Register: TEMP_B1 */ +/* Description: y-intercept of 2nd piece wise linear function */ + +/* Bits 13..0 : y-intercept of 2nd piece wise linear function */ +#define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ +#define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ + +/* Register: TEMP_B2 */ +/* Description: y-intercept of 3rd piece wise linear function */ + +/* Bits 13..0 : y-intercept of 3rd piece wise linear function */ +#define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ +#define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ + +/* Register: TEMP_B3 */ +/* Description: y-intercept of 4th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 4th piece wise linear function */ +#define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ +#define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ + +/* Register: TEMP_B4 */ +/* Description: y-intercept of 5th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 5th piece wise linear function */ +#define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ +#define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ + +/* Register: TEMP_B5 */ +/* Description: y-intercept of 6th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 6th piece wise linear function */ +#define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ +#define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ + +/* Register: TEMP_T0 */ +/* Description: End point of 1st piece wise linear function */ + +/* Bits 7..0 : End point of 1st piece wise linear function */ +#define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ +#define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ + +/* Register: TEMP_T1 */ +/* Description: End point of 2nd piece wise linear function */ + +/* Bits 7..0 : End point of 2nd piece wise linear function */ +#define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ +#define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ + +/* Register: TEMP_T2 */ +/* Description: End point of 3rd piece wise linear function */ + +/* Bits 7..0 : End point of 3rd piece wise linear function */ +#define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ +#define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ + +/* Register: TEMP_T3 */ +/* Description: End point of 4th piece wise linear function */ + +/* Bits 7..0 : End point of 4th piece wise linear function */ +#define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ +#define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ + +/* Register: TEMP_T4 */ +/* Description: End point of 5th piece wise linear function */ + +/* Bits 7..0 : End point of 5th piece wise linear function */ +#define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ +#define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ + + +/* Peripheral: TIMER */ +/* Description: Timer/Counter 0 */ + +/* Register: TIMER_TASKS_START */ +/* Description: Start Timer */ + +/* Bit 0 : Start Timer */ +#define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_TASKS_STOP */ +/* Description: Stop Timer */ + +/* Bit 0 : Stop Timer */ +#define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_TASKS_COUNT */ +/* Description: Increment Timer (Counter mode only) */ + +/* Bit 0 : Increment Timer (Counter mode only) */ +#define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */ +#define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */ +#define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_TASKS_CLEAR */ +/* Description: Clear time */ + +/* Bit 0 : Clear time */ +#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ +#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ +#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_TASKS_SHUTDOWN */ +/* Description: Deprecated register - Shut down timer */ + +/* Bit 0 : Deprecated field - Shut down timer */ +#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */ +#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */ +#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_TASKS_CAPTURE */ +/* Description: Description collection: Capture Timer value to CC[n] register */ + +/* Bit 0 : Capture Timer value to CC[n] register */ +#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ +#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */ +#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_EVENTS_COMPARE */ +/* Description: Description collection: Compare event on CC[n] match */ + +/* Bit 0 : Compare event on CC[n] match */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ + +/* Register: TIMER_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 13 : Shortcut between event COMPARE[5] and task STOP */ +#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 12 : Shortcut between event COMPARE[4] and task STOP */ +#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 11 : Shortcut between event COMPARE[3] and task STOP */ +#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between event COMPARE[2] and task STOP */ +#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between event COMPARE[1] and task STOP */ +#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between event COMPARE[0] and task STOP */ +#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TIMER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */ +#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */ +#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ +#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ +#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ +#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ +#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Register: TIMER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */ +#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */ +#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ +#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ +#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ +#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ +#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Register: TIMER_MODE */ +/* Description: Timer mode selection */ + +/* Bits 1..0 : Timer mode */ +#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */ +#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */ +#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */ + +/* Register: TIMER_BITMODE */ +/* Description: Configure the number of bits used by the TIMER */ + +/* Bits 1..0 : Timer bit width */ +#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */ + +/* Register: TIMER_PRESCALER */ +/* Description: Timer prescaler register */ + +/* Bits 3..0 : Prescaler value */ +#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: TIMER_CC */ +/* Description: Description collection: Capture/Compare register n */ + +/* Bits 31..0 : Capture/Compare value */ +#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ +#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ + + +/* Peripheral: TWI */ +/* Description: I2C compatible Two-Wire Interface 0 */ + +/* Register: TWI_TASKS_STARTRX */ +/* Description: Start TWI receive sequence */ + +/* Bit 0 : Start TWI receive sequence */ +#define TWI_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define TWI_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWI_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define TWI_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWI_TASKS_STARTTX */ +/* Description: Start TWI transmit sequence */ + +/* Bit 0 : Start TWI transmit sequence */ +#define TWI_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define TWI_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWI_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define TWI_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWI_TASKS_STOP */ +/* Description: Stop TWI transaction */ + +/* Bit 0 : Stop TWI transaction */ +#define TWI_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TWI_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWI_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWI_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWI_TASKS_SUSPEND */ +/* Description: Suspend TWI transaction */ + +/* Bit 0 : Suspend TWI transaction */ +#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWI_TASKS_RESUME */ +/* Description: Resume TWI transaction */ + +/* Bit 0 : Resume TWI transaction */ +#define TWI_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define TWI_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWI_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWI_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWI_EVENTS_STOPPED */ +/* Description: TWI stopped */ + +/* Bit 0 : TWI stopped */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_EVENTS_RXDREADY */ +/* Description: TWI RXD byte received */ + +/* Bit 0 : TWI RXD byte received */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos (0UL) /*!< Position of EVENTS_RXDREADY field. */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Msk (0x1UL << TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos) /*!< Bit mask of EVENTS_RXDREADY field. */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_EVENTS_TXDSENT */ +/* Description: TWI TXD byte sent */ + +/* Bit 0 : TWI TXD byte sent */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos (0UL) /*!< Position of EVENTS_TXDSENT field. */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Msk (0x1UL << TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos) /*!< Bit mask of EVENTS_TXDSENT field. */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_EVENTS_ERROR */ +/* Description: TWI error */ + +/* Bit 0 : TWI error */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWI_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_EVENTS_BB */ +/* Description: TWI byte boundary, generated before each byte that is sent or received */ + +/* Bit 0 : TWI byte boundary, generated before each byte that is sent or received */ +#define TWI_EVENTS_BB_EVENTS_BB_Pos (0UL) /*!< Position of EVENTS_BB field. */ +#define TWI_EVENTS_BB_EVENTS_BB_Msk (0x1UL << TWI_EVENTS_BB_EVENTS_BB_Pos) /*!< Bit mask of EVENTS_BB field. */ +#define TWI_EVENTS_BB_EVENTS_BB_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_BB_EVENTS_BB_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_EVENTS_SUSPENDED */ +/* Description: TWI entered the suspended state */ + +/* Bit 0 : TWI entered the suspended state */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 1 : Shortcut between event BB and task STOP */ +#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event BB and task SUSPEND */ +#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ +#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for event BB */ +#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event TXDSENT */ +#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event RXDREADY */ +#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ +#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for event BB */ +#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event TXDSENT */ +#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event RXDREADY */ +#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWI_ERRORSRC */ +/* Description: Error source */ + +/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ +#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */ +#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : NACK received after sending the address (write '1' to clear) */ +#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */ +#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ +#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ + +/* Register: TWI_ENABLE */ +/* Description: Enable TWI */ + +/* Bits 3..0 : Enable or disable TWI */ +#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */ +#define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */ + +/* Register: TWI_PSEL_SCL */ +/* Description: Pin select for SCL */ + +/* Bit 31 : Connection */ +#define TWI_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWI_PSEL_SCL_CONNECT_Msk (0x1UL << TWI_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWI_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWI_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWI_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWI_PSEL_SCL_PIN_Msk (0x1FUL << TWI_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWI_PSEL_SDA */ +/* Description: Pin select for SDA */ + +/* Bit 31 : Connection */ +#define TWI_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWI_PSEL_SDA_CONNECT_Msk (0x1UL << TWI_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWI_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWI_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWI_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWI_PSEL_SDA_PIN_Msk (0x1FUL << TWI_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWI_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RXD register */ +#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: TWI_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TXD register */ +#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: TWI_FREQUENCY */ +/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : TWI master clock frequency */ +#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ +#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */ + +/* Register: TWI_ADDRESS */ +/* Description: Address used in the TWI transfer */ + +/* Bits 6..0 : Address used in the TWI transfer */ +#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* Peripheral: TWIM */ +/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */ + +/* Register: TWIM_TASKS_STARTRX */ +/* Description: Start TWI receive sequence */ + +/* Bit 0 : Start TWI receive sequence */ +#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIM_TASKS_STARTTX */ +/* Description: Start TWI transmit sequence */ + +/* Bit 0 : Start TWI transmit sequence */ +#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIM_TASKS_STOP */ +/* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */ + +/* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */ +#define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIM_TASKS_SUSPEND */ +/* Description: Suspend TWI transaction */ + +/* Bit 0 : Suspend TWI transaction */ +#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIM_TASKS_RESUME */ +/* Description: Resume TWI transaction */ + +/* Bit 0 : Resume TWI transaction */ +#define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIM_EVENTS_STOPPED */ +/* Description: TWI stopped */ + +/* Bit 0 : TWI stopped */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_ERROR */ +/* Description: TWI error */ + +/* Bit 0 : TWI error */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_SUSPENDED */ +/* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ + +/* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_RXSTARTED */ +/* Description: Receive sequence started */ + +/* Bit 0 : Receive sequence started */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_TXSTARTED */ +/* Description: Transmit sequence started */ + +/* Bit 0 : Transmit sequence started */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_LASTRX */ +/* Description: Byte boundary, starting to receive the last byte */ + +/* Bit 0 : Byte boundary, starting to receive the last byte */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_LASTTX */ +/* Description: Byte boundary, starting to transmit the last byte */ + +/* Bit 0 : Byte boundary, starting to transmit the last byte */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 12 : Shortcut between event LASTRX and task STOP */ +#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 11 : Shortcut between event LASTRX and task SUSPEND */ +#define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */ +#define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */ +#define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between event LASTRX and task STARTTX */ +#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between event LASTTX and task STOP */ +#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between event LASTTX and task SUSPEND */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 7 : Shortcut between event LASTTX and task STARTRX */ +#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 24 : Enable or disable interrupt for event LASTTX */ +#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ + +/* Bit 23 : Enable or disable interrupt for event LASTRX */ +#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ +#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ +#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for event SUSPENDED */ +#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for event ERROR */ +#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event STOPPED */ +#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 24 : Write '1' to enable interrupt for event LASTTX */ +#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ + +/* Bit 23 : Write '1' to enable interrupt for event LASTRX */ +#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ +#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ +#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ +#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 24 : Write '1' to disable interrupt for event LASTTX */ +#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ + +/* Bit 23 : Write '1' to disable interrupt for event LASTRX */ +#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ +#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ +#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ +#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIM_ERRORSRC */ +/* Description: Error source */ + +/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ +#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 1 : NACK received after sending the address (write '1' to clear) */ +#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */ + +/* Bit 0 : Overrun error */ +#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */ + +/* Register: TWIM_ENABLE */ +/* Description: Enable TWIM */ + +/* Bits 3..0 : Enable or disable TWIM */ +#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */ +#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */ + +/* Register: TWIM_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_FREQUENCY */ +/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : TWI master clock frequency */ +#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ + +/* Register: TWIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 14..0 : Maximum number of bytes in receive buffer */ +#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 14..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 14..0 : Maximum number of bytes in transmit buffer */ +#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 14..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_ADDRESS */ +/* Description: Address used in the TWI transfer */ + +/* Bits 6..0 : Address used in the TWI transfer */ +#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* Peripheral: TWIS */ +/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */ + +/* Register: TWIS_TASKS_STOP */ +/* Description: Stop TWI transaction */ + +/* Bit 0 : Stop TWI transaction */ +#define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIS_TASKS_SUSPEND */ +/* Description: Suspend TWI transaction */ + +/* Bit 0 : Suspend TWI transaction */ +#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIS_TASKS_RESUME */ +/* Description: Resume TWI transaction */ + +/* Bit 0 : Resume TWI transaction */ +#define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIS_TASKS_PREPARERX */ +/* Description: Prepare the TWI slave to respond to a write command */ + +/* Bit 0 : Prepare the TWI slave to respond to a write command */ +#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */ +#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */ +#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIS_TASKS_PREPARETX */ +/* Description: Prepare the TWI slave to respond to a read command */ + +/* Bit 0 : Prepare the TWI slave to respond to a read command */ +#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */ +#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */ +#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIS_EVENTS_STOPPED */ +/* Description: TWI stopped */ + +/* Bit 0 : TWI stopped */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_EVENTS_ERROR */ +/* Description: TWI error */ + +/* Bit 0 : TWI error */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_EVENTS_RXSTARTED */ +/* Description: Receive sequence started */ + +/* Bit 0 : Receive sequence started */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_EVENTS_TXSTARTED */ +/* Description: Transmit sequence started */ + +/* Bit 0 : Transmit sequence started */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_EVENTS_WRITE */ +/* Description: Write command received */ + +/* Bit 0 : Write command received */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_EVENTS_READ */ +/* Description: Read command received */ + +/* Bit 0 : Read command received */ +#define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */ +#define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */ +#define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 14 : Shortcut between event READ and task SUSPEND */ +#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 13 : Shortcut between event WRITE and task SUSPEND */ +#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIS_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 26 : Enable or disable interrupt for event READ */ +#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable interrupt for event WRITE */ +#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ +#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ +#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for event ERROR */ +#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event STOPPED */ +#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 26 : Write '1' to enable interrupt for event READ */ +#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to enable interrupt for event WRITE */ +#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ +#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ +#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 26 : Write '1' to disable interrupt for event READ */ +#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to disable interrupt for event WRITE */ +#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ +#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ +#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIS_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : TX buffer over-read detected, and prevented */ +#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */ + +/* Bit 2 : NACK sent after receiving a data byte */ +#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 0 : RX buffer overflow detected, and prevented */ +#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */ + +/* Register: TWIS_MATCH */ +/* Description: Status register indicating which address had a match */ + +/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ +#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ +#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + +/* Register: TWIS_ENABLE */ +/* Description: Enable TWIS */ + +/* Bits 3..0 : Enable or disable TWIS */ +#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */ +#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */ + +/* Register: TWIS_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_RXD_PTR */ +/* Description: RXD Data pointer */ + +/* Bits 31..0 : RXD Data pointer */ +#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in RXD buffer */ + +/* Bits 14..0 : Maximum number of bytes in RXD buffer */ +#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last RXD transaction */ + +/* Bits 14..0 : Number of bytes transferred in the last RXD transaction */ +#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIS_TXD_PTR */ +/* Description: TXD Data pointer */ + +/* Bits 31..0 : TXD Data pointer */ +#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in TXD buffer */ + +/* Bits 14..0 : Maximum number of bytes in TXD buffer */ +#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last TXD transaction */ + +/* Bits 14..0 : Number of bytes transferred in the last TXD transaction */ +#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIS_ADDRESS */ +/* Description: Description collection: TWI slave address n */ + +/* Bits 6..0 : TWI slave address */ +#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + +/* Register: TWIS_CONFIG */ +/* Description: Configuration register for the address match mechanism */ + +/* Bit 1 : Enable or disable address matching on ADDRESS[1] */ +#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */ + +/* Bit 0 : Enable or disable address matching on ADDRESS[0] */ +#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */ + +/* Register: TWIS_ORC */ +/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */ + +/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */ +#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: UART */ +/* Description: Universal Asynchronous Receiver/Transmitter */ + +/* Register: UART_TASKS_STARTRX */ +/* Description: Start UART receiver */ + +/* Bit 0 : Start UART receiver */ +#define UART_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define UART_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UART_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define UART_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UART_TASKS_STOPRX */ +/* Description: Stop UART receiver */ + +/* Bit 0 : Stop UART receiver */ +#define UART_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ +#define UART_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UART_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ +#define UART_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UART_TASKS_STARTTX */ +/* Description: Start UART transmitter */ + +/* Bit 0 : Start UART transmitter */ +#define UART_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define UART_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UART_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define UART_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UART_TASKS_STOPTX */ +/* Description: Stop UART transmitter */ + +/* Bit 0 : Stop UART transmitter */ +#define UART_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ +#define UART_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UART_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ +#define UART_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UART_TASKS_SUSPEND */ +/* Description: Suspend UART */ + +/* Bit 0 : Suspend UART */ +#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ + +/* Register: UART_EVENTS_CTS */ +/* Description: CTS is activated (set low). Clear To Send. */ + +/* Bit 0 : CTS is activated (set low). Clear To Send. */ +#define UART_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ +#define UART_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UART_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ +#define UART_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */ + +/* Register: UART_EVENTS_NCTS */ +/* Description: CTS is deactivated (set high). Not Clear To Send. */ + +/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UART_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */ + +/* Register: UART_EVENTS_RXDRDY */ +/* Description: Data received in RXD */ + +/* Bit 0 : Data received in RXD */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */ + +/* Register: UART_EVENTS_TXDRDY */ +/* Description: Data sent from TXD */ + +/* Bit 0 : Data sent from TXD */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */ + +/* Register: UART_EVENTS_ERROR */ +/* Description: Error detected */ + +/* Bit 0 : Error detected */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UART_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: UART_EVENTS_RXTO */ +/* Description: Receiver timeout */ + +/* Bit 0 : Receiver timeout */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UART_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */ + +/* Register: UART_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 4 : Shortcut between event NCTS and task STOPRX */ +#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */ +#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event CTS and task STARTRX */ +#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: UART_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 17 : Write '1' to enable interrupt for event RXTO */ +#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ +#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ +#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event NCTS */ +#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event CTS */ +#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_CTS_Set (1UL) /*!< Enable */ + +/* Register: UART_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 17 : Write '1' to disable interrupt for event RXTO */ +#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ +#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ +#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event NCTS */ +#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event CTS */ +#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */ + +/* Register: UART_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : Break condition */ +#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ + +/* Bit 2 : Framing error occurred */ +#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : Parity error */ +#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ + +/* Register: UART_ENABLE */ +/* Description: Enable UART */ + +/* Bits 3..0 : Enable or disable UART */ +#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */ +#define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */ + +/* Register: UART_PSEL_RTS */ +/* Description: Pin select for RTS */ + +/* Bit 31 : Connection */ +#define UART_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_RTS_CONNECT_Msk (0x1UL << UART_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_RTS_PIN_Msk (0x1FUL << UART_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_PSEL_TXD */ +/* Description: Pin select for TXD */ + +/* Bit 31 : Connection */ +#define UART_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_TXD_CONNECT_Msk (0x1UL << UART_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_TXD_PIN_Msk (0x1FUL << UART_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_PSEL_CTS */ +/* Description: Pin select for CTS */ + +/* Bit 31 : Connection */ +#define UART_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_CTS_CONNECT_Msk (0x1UL << UART_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_CTS_PIN_Msk (0x1FUL << UART_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_PSEL_RXD */ +/* Description: Pin select for RXD */ + +/* Bit 31 : Connection */ +#define UART_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_RXD_CONNECT_Msk (0x1UL << UART_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_RXD_PIN_Msk (0x1FUL << UART_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RX data received in previous transfers, double buffered */ +#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: UART_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TX data to be transferred */ +#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: UART_BAUDRATE */ +/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : Baud rate */ +#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ +#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ +#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ +#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ +#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */ +#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ +#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */ +#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ +#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */ +#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ +#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */ +#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ +#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */ +#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */ +#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ +#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */ +#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */ +#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ + +/* Register: UART_CONFIG */ +/* Description: Configuration of parity and hardware flow control */ + +/* Bit 8 : Even or odd parity type */ +#define UART_CONFIG_PARITYTYPE_Pos (8UL) /*!< Position of PARITYTYPE field. */ +#define UART_CONFIG_PARITYTYPE_Msk (0x1UL << UART_CONFIG_PARITYTYPE_Pos) /*!< Bit mask of PARITYTYPE field. */ +#define UART_CONFIG_PARITYTYPE_Even (0UL) /*!< Even parity */ +#define UART_CONFIG_PARITYTYPE_Odd (1UL) /*!< Odd parity */ + +/* Bit 4 : Stop bits */ +#define UART_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ +#define UART_CONFIG_STOP_Msk (0x1UL << UART_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ +#define UART_CONFIG_STOP_One (0UL) /*!< One stop bit */ +#define UART_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ + +/* Bits 3..1 : Parity */ +#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ +#define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */ + +/* Bit 0 : Hardware flow control */ +#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ +#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ + + +/* Peripheral: UARTE */ +/* Description: UART with EasyDMA */ + +/* Register: UARTE_TASKS_STARTRX */ +/* Description: Start UART receiver */ + +/* Bit 0 : Start UART receiver */ +#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UARTE_TASKS_STOPRX */ +/* Description: Stop UART receiver */ + +/* Bit 0 : Stop UART receiver */ +#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ +#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ +#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UARTE_TASKS_STARTTX */ +/* Description: Start UART transmitter */ + +/* Bit 0 : Start UART transmitter */ +#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UARTE_TASKS_STOPTX */ +/* Description: Stop UART transmitter */ + +/* Bit 0 : Stop UART transmitter */ +#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ +#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ +#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UARTE_TASKS_FLUSHRX */ +/* Description: Flush RX FIFO into RX buffer */ + +/* Bit 0 : Flush RX FIFO into RX buffer */ +#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */ +#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */ +#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UARTE_EVENTS_CTS */ +/* Description: CTS is activated (set low). Clear To Send. */ + +/* Bit 0 : CTS is activated (set low). Clear To Send. */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_NCTS */ +/* Description: CTS is deactivated (set high). Not Clear To Send. */ + +/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_RXDRDY */ +/* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */ + +/* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_ENDRX */ +/* Description: Receive buffer is filled up */ + +/* Bit 0 : Receive buffer is filled up */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_TXDRDY */ +/* Description: Data sent from TXD */ + +/* Bit 0 : Data sent from TXD */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_ENDTX */ +/* Description: Last TX byte transmitted */ + +/* Bit 0 : Last TX byte transmitted */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_ERROR */ +/* Description: Error detected */ + +/* Bit 0 : Error detected */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_RXTO */ +/* Description: Receiver timeout */ + +/* Bit 0 : Receiver timeout */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_RXSTARTED */ +/* Description: UART receiver has started */ + +/* Bit 0 : UART receiver has started */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_TXSTARTED */ +/* Description: UART transmitter has started */ + +/* Bit 0 : UART transmitter has started */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_TXSTOPPED */ +/* Description: Transmitter stopped */ + +/* Bit 0 : Transmitter stopped */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 6 : Shortcut between event ENDRX and task STOPRX */ +#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between event ENDRX and task STARTRX */ +#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: UARTE_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 22 : Enable or disable interrupt for event TXSTOPPED */ +#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ +#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ +#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for event RXTO */ +#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for event ERROR */ +#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for event ENDTX */ +#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for event TXDRDY */ +#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for event ENDRX */ +#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event RXDRDY */ +#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event NCTS */ +#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event CTS */ +#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */ + +/* Register: UARTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */ +#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ +#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ +#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for event RXTO */ +#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for event ENDTX */ +#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ +#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ +#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ +#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event NCTS */ +#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event CTS */ +#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */ + +/* Register: UARTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */ +#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ +#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ +#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for event RXTO */ +#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for event ENDTX */ +#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ +#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ +#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ +#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event NCTS */ +#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event CTS */ +#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ + +/* Register: UARTE_ERRORSRC */ +/* Description: Error source Note : this register is read / write one to clear. */ + +/* Bit 3 : Break condition */ +#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ + +/* Bit 2 : Framing error occurred */ +#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : Parity error */ +#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ + +/* Register: UARTE_ENABLE */ +/* Description: Enable UART */ + +/* Bits 3..0 : Enable or disable UARTE */ +#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */ +#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */ + +/* Register: UARTE_PSEL_RTS */ +/* Description: Pin select for RTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_TXD */ +/* Description: Pin select for TXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_CTS */ +/* Description: Pin select for CTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_RXD */ +/* Description: Pin select for RXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_BAUDRATE */ +/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : Baud rate */ +#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ + +/* Register: UARTE_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 14..0 : Maximum number of bytes in receive buffer */ +#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 14..0 : Number of bytes transferred in the last transaction */ +#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 14..0 : Maximum number of bytes in transmit buffer */ +#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 14..0 : Number of bytes transferred in the last transaction */ +#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_CONFIG */ +/* Description: Configuration of parity and hardware flow control */ + +/* Bit 8 : Even or odd parity type */ +#define UARTE_CONFIG_PARITYTYPE_Pos (8UL) /*!< Position of PARITYTYPE field. */ +#define UARTE_CONFIG_PARITYTYPE_Msk (0x1UL << UARTE_CONFIG_PARITYTYPE_Pos) /*!< Bit mask of PARITYTYPE field. */ +#define UARTE_CONFIG_PARITYTYPE_Even (0UL) /*!< Even parity */ +#define UARTE_CONFIG_PARITYTYPE_Odd (1UL) /*!< Odd parity */ + +/* Bit 4 : Stop bits */ +#define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ +#define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ +#define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */ +#define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ + +/* Bits 3..1 : Parity */ +#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ +#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */ + +/* Bit 0 : Hardware flow control */ +#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ +#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ + + +/* Peripheral: UICR */ +/* Description: User information configuration registers */ + +/* Register: UICR_NRFFW */ +/* Description: Description collection: Reserved for Nordic firmware design */ + +/* Bits 31..0 : Reserved for Nordic firmware design */ +#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */ +#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */ + +/* Register: UICR_NRFHW */ +/* Description: Description collection: Reserved for Nordic hardware design */ + +/* Bits 31..0 : Reserved for Nordic hardware design */ +#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */ +#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */ + +/* Register: UICR_CUSTOMER */ +/* Description: Description collection: Reserved for customer */ + +/* Bits 31..0 : Reserved for customer */ +#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ +#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ + +/* Register: UICR_PSELRESET */ +/* Description: Description collection: Mapping of the nRESET function (see POWER chapter for details) */ + +/* Bit 31 : Connection */ +#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */ +#define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : GPIO pin number onto which nRESET is exposed */ +#define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UICR_APPROTECT */ +/* Description: Access port protection */ + +/* Bits 7..0 : Enable or disable access port protection. */ +#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ +#define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ +#define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ +#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ + +/* Register: UICR_DEBUGCTRL */ +/* Description: Processor debug control */ + +/* Bits 15..8 : Configure CPU flash patch and breakpoint (FPB) unit behavior */ +#define UICR_DEBUGCTRL_CPUFPBEN_Pos (8UL) /*!< Position of CPUFPBEN field. */ +#define UICR_DEBUGCTRL_CPUFPBEN_Msk (0xFFUL << UICR_DEBUGCTRL_CPUFPBEN_Pos) /*!< Bit mask of CPUFPBEN field. */ +#define UICR_DEBUGCTRL_CPUFPBEN_Disabled (0x00UL) /*!< Disable CPU FPB unit. Writes into the FPB registers will be ignored. */ +#define UICR_DEBUGCTRL_CPUFPBEN_Enabled (0xFFUL) /*!< Enable CPU FPB unit (default behavior) */ + +/* Register: UICR_REGOUT0 */ +/* Description: Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VREG0DROP. */ + +/* Bits 2..0 : Output voltage from REG0 regulator stage. */ +#define UICR_REGOUT0_VOUT_Pos (0UL) /*!< Position of VOUT field. */ +#define UICR_REGOUT0_VOUT_Msk (0x7UL << UICR_REGOUT0_VOUT_Pos) /*!< Bit mask of VOUT field. */ +#define UICR_REGOUT0_VOUT_1V8 (0UL) /*!< 1.8 V */ +#define UICR_REGOUT0_VOUT_2V1 (1UL) /*!< 2.1 V */ +#define UICR_REGOUT0_VOUT_2V4 (2UL) /*!< 2.4 V */ +#define UICR_REGOUT0_VOUT_2V7 (3UL) /*!< 2.7 V */ +#define UICR_REGOUT0_VOUT_3V0 (4UL) /*!< 3.0 V */ +#define UICR_REGOUT0_VOUT_3V3 (5UL) /*!< 3.3 V */ +#define UICR_REGOUT0_VOUT_DEFAULT (7UL) /*!< Default voltage: 1.8 V */ + + +/* Peripheral: USBD */ +/* Description: Universal serial bus device */ + +/* Register: USBD_TASKS_STARTEPIN */ +/* Description: Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */ + +/* Bit 0 : Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */ +#define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos (0UL) /*!< Position of TASKS_STARTEPIN field. */ +#define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Msk (0x1UL << USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos) /*!< Bit mask of TASKS_STARTEPIN field. */ +#define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Trigger (1UL) /*!< Trigger task */ + +/* Register: USBD_TASKS_STARTISOIN */ +/* Description: Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */ + +/* Bit 0 : Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */ +#define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos (0UL) /*!< Position of TASKS_STARTISOIN field. */ +#define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Msk (0x1UL << USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos) /*!< Bit mask of TASKS_STARTISOIN field. */ +#define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Trigger (1UL) /*!< Trigger task */ + +/* Register: USBD_TASKS_STARTEPOUT */ +/* Description: Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */ + +/* Bit 0 : Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */ +#define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos (0UL) /*!< Position of TASKS_STARTEPOUT field. */ +#define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Msk (0x1UL << USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos) /*!< Bit mask of TASKS_STARTEPOUT field. */ +#define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Trigger (1UL) /*!< Trigger task */ + +/* Register: USBD_TASKS_STARTISOOUT */ +/* Description: Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */ + +/* Bit 0 : Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */ +#define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos (0UL) /*!< Position of TASKS_STARTISOOUT field. */ +#define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Msk (0x1UL << USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos) /*!< Bit mask of TASKS_STARTISOOUT field. */ +#define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Trigger (1UL) /*!< Trigger task */ + +/* Register: USBD_TASKS_EP0RCVOUT */ +/* Description: Allows OUT data stage on control endpoint 0 */ + +/* Bit 0 : Allows OUT data stage on control endpoint 0 */ +#define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos (0UL) /*!< Position of TASKS_EP0RCVOUT field. */ +#define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Msk (0x1UL << USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos) /*!< Bit mask of TASKS_EP0RCVOUT field. */ +#define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Trigger (1UL) /*!< Trigger task */ + +/* Register: USBD_TASKS_EP0STATUS */ +/* Description: Allows status stage on control endpoint 0 */ + +/* Bit 0 : Allows status stage on control endpoint 0 */ +#define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos (0UL) /*!< Position of TASKS_EP0STATUS field. */ +#define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Msk (0x1UL << USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos) /*!< Bit mask of TASKS_EP0STATUS field. */ +#define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger (1UL) /*!< Trigger task */ + +/* Register: USBD_TASKS_EP0STALL */ +/* Description: Stalls data and status stage on control endpoint 0 */ + +/* Bit 0 : Stalls data and status stage on control endpoint 0 */ +#define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos (0UL) /*!< Position of TASKS_EP0STALL field. */ +#define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Msk (0x1UL << USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos) /*!< Bit mask of TASKS_EP0STALL field. */ +#define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Trigger (1UL) /*!< Trigger task */ + +/* Register: USBD_TASKS_DPDMDRIVE */ +/* Description: Forces D+ and D- lines into the state defined in the DPDMVALUE register */ + +/* Bit 0 : Forces D+ and D- lines into the state defined in the DPDMVALUE register */ +#define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos (0UL) /*!< Position of TASKS_DPDMDRIVE field. */ +#define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Msk (0x1UL << USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos) /*!< Bit mask of TASKS_DPDMDRIVE field. */ +#define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Trigger (1UL) /*!< Trigger task */ + +/* Register: USBD_TASKS_DPDMNODRIVE */ +/* Description: Stops forcing D+ and D- lines into any state (USB engine takes control) */ + +/* Bit 0 : Stops forcing D+ and D- lines into any state (USB engine takes control) */ +#define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos (0UL) /*!< Position of TASKS_DPDMNODRIVE field. */ +#define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Msk (0x1UL << USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos) /*!< Bit mask of TASKS_DPDMNODRIVE field. */ +#define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Trigger (1UL) /*!< Trigger task */ + +/* Register: USBD_EVENTS_USBRESET */ +/* Description: Signals that a USB reset condition has been detected on USB lines */ + +/* Bit 0 : Signals that a USB reset condition has been detected on USB lines */ +#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos (0UL) /*!< Position of EVENTS_USBRESET field. */ +#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Msk (0x1UL << USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos) /*!< Bit mask of EVENTS_USBRESET field. */ +#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_EVENTS_STARTED */ +/* Description: Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */ + +/* Bit 0 : Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */ +#define USBD_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ +#define USBD_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << USBD_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define USBD_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_EVENTS_ENDEPIN */ +/* Description: Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */ + +/* Bit 0 : The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */ +#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos (0UL) /*!< Position of EVENTS_ENDEPIN field. */ +#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Msk (0x1UL << USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos) /*!< Bit mask of EVENTS_ENDEPIN field. */ +#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_EVENTS_EP0DATADONE */ +/* Description: An acknowledged data transfer has taken place on the control endpoint */ + +/* Bit 0 : An acknowledged data transfer has taken place on the control endpoint */ +#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos (0UL) /*!< Position of EVENTS_EP0DATADONE field. */ +#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Msk (0x1UL << USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos) /*!< Bit mask of EVENTS_EP0DATADONE field. */ +#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_EVENTS_ENDISOIN */ +/* Description: The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */ + +/* Bit 0 : The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */ +#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos (0UL) /*!< Position of EVENTS_ENDISOIN field. */ +#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Msk (0x1UL << USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos) /*!< Bit mask of EVENTS_ENDISOIN field. */ +#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_EVENTS_ENDEPOUT */ +/* Description: Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */ + +/* Bit 0 : The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */ +#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos (0UL) /*!< Position of EVENTS_ENDEPOUT field. */ +#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Msk (0x1UL << USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos) /*!< Bit mask of EVENTS_ENDEPOUT field. */ +#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_EVENTS_ENDISOOUT */ +/* Description: The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */ + +/* Bit 0 : The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */ +#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos (0UL) /*!< Position of EVENTS_ENDISOOUT field. */ +#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Msk (0x1UL << USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos) /*!< Bit mask of EVENTS_ENDISOOUT field. */ +#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_EVENTS_SOF */ +/* Description: Signals that a SOF (start of frame) condition has been detected on USB lines */ + +/* Bit 0 : Signals that a SOF (start of frame) condition has been detected on USB lines */ +#define USBD_EVENTS_SOF_EVENTS_SOF_Pos (0UL) /*!< Position of EVENTS_SOF field. */ +#define USBD_EVENTS_SOF_EVENTS_SOF_Msk (0x1UL << USBD_EVENTS_SOF_EVENTS_SOF_Pos) /*!< Bit mask of EVENTS_SOF field. */ +#define USBD_EVENTS_SOF_EVENTS_SOF_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_SOF_EVENTS_SOF_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_EVENTS_USBEVENT */ +/* Description: An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */ + +/* Bit 0 : An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */ +#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos (0UL) /*!< Position of EVENTS_USBEVENT field. */ +#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Msk (0x1UL << USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos) /*!< Bit mask of EVENTS_USBEVENT field. */ +#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_EVENTS_EP0SETUP */ +/* Description: A valid SETUP token has been received (and acknowledged) on the control endpoint */ + +/* Bit 0 : A valid SETUP token has been received (and acknowledged) on the control endpoint */ +#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos (0UL) /*!< Position of EVENTS_EP0SETUP field. */ +#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Msk (0x1UL << USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos) /*!< Bit mask of EVENTS_EP0SETUP field. */ +#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_EVENTS_EPDATA */ +/* Description: A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */ + +/* Bit 0 : A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */ +#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos (0UL) /*!< Position of EVENTS_EPDATA field. */ +#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Msk (0x1UL << USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos) /*!< Bit mask of EVENTS_EPDATA field. */ +#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 4 : Shortcut between event ENDEPOUT[0] and task EP0RCVOUT */ +#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos (4UL) /*!< Position of ENDEPOUT0_EP0RCVOUT field. */ +#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos) /*!< Bit mask of ENDEPOUT0_EP0RCVOUT field. */ +#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Disabled (0UL) /*!< Disable shortcut */ +#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event ENDEPOUT[0] and task EP0STATUS */ +#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos (3UL) /*!< Position of ENDEPOUT0_EP0STATUS field. */ +#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos) /*!< Bit mask of ENDEPOUT0_EP0STATUS field. */ +#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */ +#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between event EP0DATADONE and task EP0STATUS */ +#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos (2UL) /*!< Position of EP0DATADONE_EP0STATUS field. */ +#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos) /*!< Bit mask of EP0DATADONE_EP0STATUS field. */ +#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */ +#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between event EP0DATADONE and task STARTEPOUT[0] */ +#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos (1UL) /*!< Position of EP0DATADONE_STARTEPOUT0 field. */ +#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPOUT0 field. */ +#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Disabled (0UL) /*!< Disable shortcut */ +#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event EP0DATADONE and task STARTEPIN[0] */ +#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos (0UL) /*!< Position of EP0DATADONE_STARTEPIN0 field. */ +#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPIN0 field. */ +#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Disabled (0UL) /*!< Disable shortcut */ +#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: USBD_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 24 : Enable or disable interrupt for event EPDATA */ +#define USBD_INTEN_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ +#define USBD_INTEN_EPDATA_Msk (0x1UL << USBD_INTEN_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ +#define USBD_INTEN_EPDATA_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_EPDATA_Enabled (1UL) /*!< Enable */ + +/* Bit 23 : Enable or disable interrupt for event EP0SETUP */ +#define USBD_INTEN_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ +#define USBD_INTEN_EP0SETUP_Msk (0x1UL << USBD_INTEN_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ +#define USBD_INTEN_EP0SETUP_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_EP0SETUP_Enabled (1UL) /*!< Enable */ + +/* Bit 22 : Enable or disable interrupt for event USBEVENT */ +#define USBD_INTEN_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ +#define USBD_INTEN_USBEVENT_Msk (0x1UL << USBD_INTEN_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ +#define USBD_INTEN_USBEVENT_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_USBEVENT_Enabled (1UL) /*!< Enable */ + +/* Bit 21 : Enable or disable interrupt for event SOF */ +#define USBD_INTEN_SOF_Pos (21UL) /*!< Position of SOF field. */ +#define USBD_INTEN_SOF_Msk (0x1UL << USBD_INTEN_SOF_Pos) /*!< Bit mask of SOF field. */ +#define USBD_INTEN_SOF_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_SOF_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for event ENDISOOUT */ +#define USBD_INTEN_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ +#define USBD_INTEN_ENDISOOUT_Msk (0x1UL << USBD_INTEN_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ +#define USBD_INTEN_ENDISOOUT_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDISOOUT_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for event ENDEPOUT[7] */ +#define USBD_INTEN_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ +#define USBD_INTEN_ENDEPOUT7_Msk (0x1UL << USBD_INTEN_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ +#define USBD_INTEN_ENDEPOUT7_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT7_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for event ENDEPOUT[6] */ +#define USBD_INTEN_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ +#define USBD_INTEN_ENDEPOUT6_Msk (0x1UL << USBD_INTEN_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ +#define USBD_INTEN_ENDEPOUT6_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT6_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for event ENDEPOUT[5] */ +#define USBD_INTEN_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ +#define USBD_INTEN_ENDEPOUT5_Msk (0x1UL << USBD_INTEN_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ +#define USBD_INTEN_ENDEPOUT5_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT5_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable interrupt for event ENDEPOUT[4] */ +#define USBD_INTEN_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ +#define USBD_INTEN_ENDEPOUT4_Msk (0x1UL << USBD_INTEN_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ +#define USBD_INTEN_ENDEPOUT4_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT4_Enabled (1UL) /*!< Enable */ + +/* Bit 15 : Enable or disable interrupt for event ENDEPOUT[3] */ +#define USBD_INTEN_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ +#define USBD_INTEN_ENDEPOUT3_Msk (0x1UL << USBD_INTEN_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ +#define USBD_INTEN_ENDEPOUT3_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT3_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for event ENDEPOUT[2] */ +#define USBD_INTEN_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ +#define USBD_INTEN_ENDEPOUT2_Msk (0x1UL << USBD_INTEN_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ +#define USBD_INTEN_ENDEPOUT2_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT2_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for event ENDEPOUT[1] */ +#define USBD_INTEN_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ +#define USBD_INTEN_ENDEPOUT1_Msk (0x1UL << USBD_INTEN_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ +#define USBD_INTEN_ENDEPOUT1_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT1_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for event ENDEPOUT[0] */ +#define USBD_INTEN_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ +#define USBD_INTEN_ENDEPOUT0_Msk (0x1UL << USBD_INTEN_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ +#define USBD_INTEN_ENDEPOUT0_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT0_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for event ENDISOIN */ +#define USBD_INTEN_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ +#define USBD_INTEN_ENDISOIN_Msk (0x1UL << USBD_INTEN_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ +#define USBD_INTEN_ENDISOIN_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDISOIN_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for event EP0DATADONE */ +#define USBD_INTEN_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ +#define USBD_INTEN_EP0DATADONE_Msk (0x1UL << USBD_INTEN_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ +#define USBD_INTEN_EP0DATADONE_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_EP0DATADONE_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for event ENDEPIN[7] */ +#define USBD_INTEN_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ +#define USBD_INTEN_ENDEPIN7_Msk (0x1UL << USBD_INTEN_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ +#define USBD_INTEN_ENDEPIN7_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN7_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for event ENDEPIN[6] */ +#define USBD_INTEN_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ +#define USBD_INTEN_ENDEPIN6_Msk (0x1UL << USBD_INTEN_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ +#define USBD_INTEN_ENDEPIN6_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN6_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for event ENDEPIN[5] */ +#define USBD_INTEN_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ +#define USBD_INTEN_ENDEPIN5_Msk (0x1UL << USBD_INTEN_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ +#define USBD_INTEN_ENDEPIN5_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN5_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for event ENDEPIN[4] */ +#define USBD_INTEN_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ +#define USBD_INTEN_ENDEPIN4_Msk (0x1UL << USBD_INTEN_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ +#define USBD_INTEN_ENDEPIN4_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN4_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for event ENDEPIN[3] */ +#define USBD_INTEN_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ +#define USBD_INTEN_ENDEPIN3_Msk (0x1UL << USBD_INTEN_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ +#define USBD_INTEN_ENDEPIN3_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN3_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for event ENDEPIN[2] */ +#define USBD_INTEN_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ +#define USBD_INTEN_ENDEPIN2_Msk (0x1UL << USBD_INTEN_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ +#define USBD_INTEN_ENDEPIN2_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN2_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for event ENDEPIN[1] */ +#define USBD_INTEN_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ +#define USBD_INTEN_ENDEPIN1_Msk (0x1UL << USBD_INTEN_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ +#define USBD_INTEN_ENDEPIN1_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN1_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event ENDEPIN[0] */ +#define USBD_INTEN_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ +#define USBD_INTEN_ENDEPIN0_Msk (0x1UL << USBD_INTEN_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ +#define USBD_INTEN_ENDEPIN0_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event STARTED */ +#define USBD_INTEN_STARTED_Pos (1UL) /*!< Position of STARTED field. */ +#define USBD_INTEN_STARTED_Msk (0x1UL << USBD_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define USBD_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event USBRESET */ +#define USBD_INTEN_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ +#define USBD_INTEN_USBRESET_Msk (0x1UL << USBD_INTEN_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ +#define USBD_INTEN_USBRESET_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_USBRESET_Enabled (1UL) /*!< Enable */ + +/* Register: USBD_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 24 : Write '1' to enable interrupt for event EPDATA */ +#define USBD_INTENSET_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ +#define USBD_INTENSET_EPDATA_Msk (0x1UL << USBD_INTENSET_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ +#define USBD_INTENSET_EPDATA_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_EPDATA_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_EPDATA_Set (1UL) /*!< Enable */ + +/* Bit 23 : Write '1' to enable interrupt for event EP0SETUP */ +#define USBD_INTENSET_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ +#define USBD_INTENSET_EP0SETUP_Msk (0x1UL << USBD_INTENSET_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ +#define USBD_INTENSET_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_EP0SETUP_Set (1UL) /*!< Enable */ + +/* Bit 22 : Write '1' to enable interrupt for event USBEVENT */ +#define USBD_INTENSET_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ +#define USBD_INTENSET_USBEVENT_Msk (0x1UL << USBD_INTENSET_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ +#define USBD_INTENSET_USBEVENT_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_USBEVENT_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_USBEVENT_Set (1UL) /*!< Enable */ + +/* Bit 21 : Write '1' to enable interrupt for event SOF */ +#define USBD_INTENSET_SOF_Pos (21UL) /*!< Position of SOF field. */ +#define USBD_INTENSET_SOF_Msk (0x1UL << USBD_INTENSET_SOF_Pos) /*!< Bit mask of SOF field. */ +#define USBD_INTENSET_SOF_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_SOF_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_SOF_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event ENDISOOUT */ +#define USBD_INTENSET_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ +#define USBD_INTENSET_ENDISOOUT_Msk (0x1UL << USBD_INTENSET_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ +#define USBD_INTENSET_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDISOOUT_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event ENDEPOUT[7] */ +#define USBD_INTENSET_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ +#define USBD_INTENSET_ENDEPOUT7_Msk (0x1UL << USBD_INTENSET_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ +#define USBD_INTENSET_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT7_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for event ENDEPOUT[6] */ +#define USBD_INTENSET_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ +#define USBD_INTENSET_ENDEPOUT6_Msk (0x1UL << USBD_INTENSET_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ +#define USBD_INTENSET_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT6_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for event ENDEPOUT[5] */ +#define USBD_INTENSET_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ +#define USBD_INTENSET_ENDEPOUT5_Msk (0x1UL << USBD_INTENSET_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ +#define USBD_INTENSET_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT5_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for event ENDEPOUT[4] */ +#define USBD_INTENSET_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ +#define USBD_INTENSET_ENDEPOUT4_Msk (0x1UL << USBD_INTENSET_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ +#define USBD_INTENSET_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT4_Set (1UL) /*!< Enable */ + +/* Bit 15 : Write '1' to enable interrupt for event ENDEPOUT[3] */ +#define USBD_INTENSET_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ +#define USBD_INTENSET_ENDEPOUT3_Msk (0x1UL << USBD_INTENSET_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ +#define USBD_INTENSET_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT3_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for event ENDEPOUT[2] */ +#define USBD_INTENSET_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ +#define USBD_INTENSET_ENDEPOUT2_Msk (0x1UL << USBD_INTENSET_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ +#define USBD_INTENSET_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT2_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to enable interrupt for event ENDEPOUT[1] */ +#define USBD_INTENSET_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ +#define USBD_INTENSET_ENDEPOUT1_Msk (0x1UL << USBD_INTENSET_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ +#define USBD_INTENSET_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT1_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to enable interrupt for event ENDEPOUT[0] */ +#define USBD_INTENSET_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ +#define USBD_INTENSET_ENDEPOUT0_Msk (0x1UL << USBD_INTENSET_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ +#define USBD_INTENSET_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT0_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to enable interrupt for event ENDISOIN */ +#define USBD_INTENSET_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ +#define USBD_INTENSET_ENDISOIN_Msk (0x1UL << USBD_INTENSET_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ +#define USBD_INTENSET_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDISOIN_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for event EP0DATADONE */ +#define USBD_INTENSET_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ +#define USBD_INTENSET_EP0DATADONE_Msk (0x1UL << USBD_INTENSET_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ +#define USBD_INTENSET_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_EP0DATADONE_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ENDEPIN[7] */ +#define USBD_INTENSET_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ +#define USBD_INTENSET_ENDEPIN7_Msk (0x1UL << USBD_INTENSET_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ +#define USBD_INTENSET_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN7_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for event ENDEPIN[6] */ +#define USBD_INTENSET_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ +#define USBD_INTENSET_ENDEPIN6_Msk (0x1UL << USBD_INTENSET_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ +#define USBD_INTENSET_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN6_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event ENDEPIN[5] */ +#define USBD_INTENSET_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ +#define USBD_INTENSET_ENDEPIN5_Msk (0x1UL << USBD_INTENSET_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ +#define USBD_INTENSET_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN5_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event ENDEPIN[4] */ +#define USBD_INTENSET_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ +#define USBD_INTENSET_ENDEPIN4_Msk (0x1UL << USBD_INTENSET_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ +#define USBD_INTENSET_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN4_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event ENDEPIN[3] */ +#define USBD_INTENSET_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ +#define USBD_INTENSET_ENDEPIN3_Msk (0x1UL << USBD_INTENSET_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ +#define USBD_INTENSET_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN3_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event ENDEPIN[2] */ +#define USBD_INTENSET_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ +#define USBD_INTENSET_ENDEPIN2_Msk (0x1UL << USBD_INTENSET_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ +#define USBD_INTENSET_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN2_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event ENDEPIN[1] */ +#define USBD_INTENSET_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ +#define USBD_INTENSET_ENDEPIN1_Msk (0x1UL << USBD_INTENSET_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ +#define USBD_INTENSET_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN1_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event ENDEPIN[0] */ +#define USBD_INTENSET_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ +#define USBD_INTENSET_ENDEPIN0_Msk (0x1UL << USBD_INTENSET_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ +#define USBD_INTENSET_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STARTED */ +#define USBD_INTENSET_STARTED_Pos (1UL) /*!< Position of STARTED field. */ +#define USBD_INTENSET_STARTED_Msk (0x1UL << USBD_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define USBD_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event USBRESET */ +#define USBD_INTENSET_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ +#define USBD_INTENSET_USBRESET_Msk (0x1UL << USBD_INTENSET_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ +#define USBD_INTENSET_USBRESET_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_USBRESET_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_USBRESET_Set (1UL) /*!< Enable */ + +/* Register: USBD_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 24 : Write '1' to disable interrupt for event EPDATA */ +#define USBD_INTENCLR_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ +#define USBD_INTENCLR_EPDATA_Msk (0x1UL << USBD_INTENCLR_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ +#define USBD_INTENCLR_EPDATA_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_EPDATA_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_EPDATA_Clear (1UL) /*!< Disable */ + +/* Bit 23 : Write '1' to disable interrupt for event EP0SETUP */ +#define USBD_INTENCLR_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ +#define USBD_INTENCLR_EP0SETUP_Msk (0x1UL << USBD_INTENCLR_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ +#define USBD_INTENCLR_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_EP0SETUP_Clear (1UL) /*!< Disable */ + +/* Bit 22 : Write '1' to disable interrupt for event USBEVENT */ +#define USBD_INTENCLR_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ +#define USBD_INTENCLR_USBEVENT_Msk (0x1UL << USBD_INTENCLR_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ +#define USBD_INTENCLR_USBEVENT_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_USBEVENT_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_USBEVENT_Clear (1UL) /*!< Disable */ + +/* Bit 21 : Write '1' to disable interrupt for event SOF */ +#define USBD_INTENCLR_SOF_Pos (21UL) /*!< Position of SOF field. */ +#define USBD_INTENCLR_SOF_Msk (0x1UL << USBD_INTENCLR_SOF_Pos) /*!< Bit mask of SOF field. */ +#define USBD_INTENCLR_SOF_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_SOF_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_SOF_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event ENDISOOUT */ +#define USBD_INTENCLR_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ +#define USBD_INTENCLR_ENDISOOUT_Msk (0x1UL << USBD_INTENCLR_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ +#define USBD_INTENCLR_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDISOOUT_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event ENDEPOUT[7] */ +#define USBD_INTENCLR_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ +#define USBD_INTENCLR_ENDEPOUT7_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ +#define USBD_INTENCLR_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT7_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for event ENDEPOUT[6] */ +#define USBD_INTENCLR_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ +#define USBD_INTENCLR_ENDEPOUT6_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ +#define USBD_INTENCLR_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT6_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for event ENDEPOUT[5] */ +#define USBD_INTENCLR_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ +#define USBD_INTENCLR_ENDEPOUT5_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ +#define USBD_INTENCLR_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT5_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for event ENDEPOUT[4] */ +#define USBD_INTENCLR_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ +#define USBD_INTENCLR_ENDEPOUT4_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ +#define USBD_INTENCLR_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT4_Clear (1UL) /*!< Disable */ + +/* Bit 15 : Write '1' to disable interrupt for event ENDEPOUT[3] */ +#define USBD_INTENCLR_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ +#define USBD_INTENCLR_ENDEPOUT3_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ +#define USBD_INTENCLR_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT3_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for event ENDEPOUT[2] */ +#define USBD_INTENCLR_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ +#define USBD_INTENCLR_ENDEPOUT2_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ +#define USBD_INTENCLR_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT2_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to disable interrupt for event ENDEPOUT[1] */ +#define USBD_INTENCLR_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ +#define USBD_INTENCLR_ENDEPOUT1_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ +#define USBD_INTENCLR_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT1_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to disable interrupt for event ENDEPOUT[0] */ +#define USBD_INTENCLR_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ +#define USBD_INTENCLR_ENDEPOUT0_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ +#define USBD_INTENCLR_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT0_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to disable interrupt for event ENDISOIN */ +#define USBD_INTENCLR_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ +#define USBD_INTENCLR_ENDISOIN_Msk (0x1UL << USBD_INTENCLR_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ +#define USBD_INTENCLR_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDISOIN_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for event EP0DATADONE */ +#define USBD_INTENCLR_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ +#define USBD_INTENCLR_EP0DATADONE_Msk (0x1UL << USBD_INTENCLR_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ +#define USBD_INTENCLR_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_EP0DATADONE_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ENDEPIN[7] */ +#define USBD_INTENCLR_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ +#define USBD_INTENCLR_ENDEPIN7_Msk (0x1UL << USBD_INTENCLR_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ +#define USBD_INTENCLR_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN7_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for event ENDEPIN[6] */ +#define USBD_INTENCLR_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ +#define USBD_INTENCLR_ENDEPIN6_Msk (0x1UL << USBD_INTENCLR_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ +#define USBD_INTENCLR_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN6_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event ENDEPIN[5] */ +#define USBD_INTENCLR_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ +#define USBD_INTENCLR_ENDEPIN5_Msk (0x1UL << USBD_INTENCLR_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ +#define USBD_INTENCLR_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN5_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event ENDEPIN[4] */ +#define USBD_INTENCLR_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ +#define USBD_INTENCLR_ENDEPIN4_Msk (0x1UL << USBD_INTENCLR_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ +#define USBD_INTENCLR_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN4_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event ENDEPIN[3] */ +#define USBD_INTENCLR_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ +#define USBD_INTENCLR_ENDEPIN3_Msk (0x1UL << USBD_INTENCLR_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ +#define USBD_INTENCLR_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN3_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event ENDEPIN[2] */ +#define USBD_INTENCLR_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ +#define USBD_INTENCLR_ENDEPIN2_Msk (0x1UL << USBD_INTENCLR_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ +#define USBD_INTENCLR_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN2_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event ENDEPIN[1] */ +#define USBD_INTENCLR_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ +#define USBD_INTENCLR_ENDEPIN1_Msk (0x1UL << USBD_INTENCLR_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ +#define USBD_INTENCLR_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN1_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event ENDEPIN[0] */ +#define USBD_INTENCLR_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ +#define USBD_INTENCLR_ENDEPIN0_Msk (0x1UL << USBD_INTENCLR_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ +#define USBD_INTENCLR_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STARTED */ +#define USBD_INTENCLR_STARTED_Pos (1UL) /*!< Position of STARTED field. */ +#define USBD_INTENCLR_STARTED_Msk (0x1UL << USBD_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define USBD_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event USBRESET */ +#define USBD_INTENCLR_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ +#define USBD_INTENCLR_USBRESET_Msk (0x1UL << USBD_INTENCLR_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ +#define USBD_INTENCLR_USBRESET_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_USBRESET_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_USBRESET_Clear (1UL) /*!< Disable */ + +/* Register: USBD_EVENTCAUSE */ +/* Description: Details on what caused the USBEVENT event */ + +/* Bit 11 : USB device is ready for normal operation. Write '1' to clear. */ +#define USBD_EVENTCAUSE_READY_Pos (11UL) /*!< Position of READY field. */ +#define USBD_EVENTCAUSE_READY_Msk (0x1UL << USBD_EVENTCAUSE_READY_Pos) /*!< Bit mask of READY field. */ +#define USBD_EVENTCAUSE_READY_NotDetected (0UL) /*!< USBEVENT was not issued due to USBD peripheral ready */ +#define USBD_EVENTCAUSE_READY_Ready (1UL) /*!< USBD peripheral is ready */ + +/* Bit 10 : USB MAC has been woken up and operational. Write '1' to clear. */ +#define USBD_EVENTCAUSE_USBWUALLOWED_Pos (10UL) /*!< Position of USBWUALLOWED field. */ +#define USBD_EVENTCAUSE_USBWUALLOWED_Msk (0x1UL << USBD_EVENTCAUSE_USBWUALLOWED_Pos) /*!< Bit mask of USBWUALLOWED field. */ +#define USBD_EVENTCAUSE_USBWUALLOWED_NotAllowed (0UL) /*!< Wake up not allowed */ +#define USBD_EVENTCAUSE_USBWUALLOWED_Allowed (1UL) /*!< Wake up allowed */ + +/* Bit 9 : Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. */ +#define USBD_EVENTCAUSE_RESUME_Pos (9UL) /*!< Position of RESUME field. */ +#define USBD_EVENTCAUSE_RESUME_Msk (0x1UL << USBD_EVENTCAUSE_RESUME_Pos) /*!< Bit mask of RESUME field. */ +#define USBD_EVENTCAUSE_RESUME_NotDetected (0UL) /*!< Resume not detected */ +#define USBD_EVENTCAUSE_RESUME_Detected (1UL) /*!< Resume detected */ + +/* Bit 8 : Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. */ +#define USBD_EVENTCAUSE_SUSPEND_Pos (8UL) /*!< Position of SUSPEND field. */ +#define USBD_EVENTCAUSE_SUSPEND_Msk (0x1UL << USBD_EVENTCAUSE_SUSPEND_Pos) /*!< Bit mask of SUSPEND field. */ +#define USBD_EVENTCAUSE_SUSPEND_NotDetected (0UL) /*!< Suspend not detected */ +#define USBD_EVENTCAUSE_SUSPEND_Detected (1UL) /*!< Suspend detected */ + +/* Bit 0 : CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. */ +#define USBD_EVENTCAUSE_ISOOUTCRC_Pos (0UL) /*!< Position of ISOOUTCRC field. */ +#define USBD_EVENTCAUSE_ISOOUTCRC_Msk (0x1UL << USBD_EVENTCAUSE_ISOOUTCRC_Pos) /*!< Bit mask of ISOOUTCRC field. */ +#define USBD_EVENTCAUSE_ISOOUTCRC_NotDetected (0UL) /*!< No error detected */ +#define USBD_EVENTCAUSE_ISOOUTCRC_Detected (1UL) /*!< Error detected */ + +/* Register: USBD_HALTED_EPIN */ +/* Description: Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ + +/* Bits 15..0 : IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ +#define USBD_HALTED_EPIN_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */ +#define USBD_HALTED_EPIN_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPIN_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */ +#define USBD_HALTED_EPIN_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */ +#define USBD_HALTED_EPIN_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */ + +/* Register: USBD_HALTED_EPOUT */ +/* Description: Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ + +/* Bits 15..0 : OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ +#define USBD_HALTED_EPOUT_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */ +#define USBD_HALTED_EPOUT_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPOUT_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */ +#define USBD_HALTED_EPOUT_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */ +#define USBD_HALTED_EPOUT_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */ + +/* Register: USBD_EPSTATUS */ +/* Description: Provides information on which endpoint's EasyDMA registers have been captured */ + +/* Bit 24 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT8_Pos (24UL) /*!< Position of EPOUT8 field. */ +#define USBD_EPSTATUS_EPOUT8_Msk (0x1UL << USBD_EPSTATUS_EPOUT8_Pos) /*!< Bit mask of EPOUT8 field. */ +#define USBD_EPSTATUS_EPOUT8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 23 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */ +#define USBD_EPSTATUS_EPOUT7_Msk (0x1UL << USBD_EPSTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */ +#define USBD_EPSTATUS_EPOUT7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 22 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */ +#define USBD_EPSTATUS_EPOUT6_Msk (0x1UL << USBD_EPSTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */ +#define USBD_EPSTATUS_EPOUT6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 21 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */ +#define USBD_EPSTATUS_EPOUT5_Msk (0x1UL << USBD_EPSTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */ +#define USBD_EPSTATUS_EPOUT5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 20 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */ +#define USBD_EPSTATUS_EPOUT4_Msk (0x1UL << USBD_EPSTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */ +#define USBD_EPSTATUS_EPOUT4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 19 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */ +#define USBD_EPSTATUS_EPOUT3_Msk (0x1UL << USBD_EPSTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */ +#define USBD_EPSTATUS_EPOUT3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 18 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */ +#define USBD_EPSTATUS_EPOUT2_Msk (0x1UL << USBD_EPSTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */ +#define USBD_EPSTATUS_EPOUT2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 17 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */ +#define USBD_EPSTATUS_EPOUT1_Msk (0x1UL << USBD_EPSTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */ +#define USBD_EPSTATUS_EPOUT1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 16 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT0_Pos (16UL) /*!< Position of EPOUT0 field. */ +#define USBD_EPSTATUS_EPOUT0_Msk (0x1UL << USBD_EPSTATUS_EPOUT0_Pos) /*!< Bit mask of EPOUT0 field. */ +#define USBD_EPSTATUS_EPOUT0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 8 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN8_Pos (8UL) /*!< Position of EPIN8 field. */ +#define USBD_EPSTATUS_EPIN8_Msk (0x1UL << USBD_EPSTATUS_EPIN8_Pos) /*!< Bit mask of EPIN8 field. */ +#define USBD_EPSTATUS_EPIN8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 7 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */ +#define USBD_EPSTATUS_EPIN7_Msk (0x1UL << USBD_EPSTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */ +#define USBD_EPSTATUS_EPIN7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 6 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */ +#define USBD_EPSTATUS_EPIN6_Msk (0x1UL << USBD_EPSTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */ +#define USBD_EPSTATUS_EPIN6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 5 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */ +#define USBD_EPSTATUS_EPIN5_Msk (0x1UL << USBD_EPSTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */ +#define USBD_EPSTATUS_EPIN5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 4 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */ +#define USBD_EPSTATUS_EPIN4_Msk (0x1UL << USBD_EPSTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */ +#define USBD_EPSTATUS_EPIN4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 3 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */ +#define USBD_EPSTATUS_EPIN3_Msk (0x1UL << USBD_EPSTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */ +#define USBD_EPSTATUS_EPIN3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 2 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */ +#define USBD_EPSTATUS_EPIN2_Msk (0x1UL << USBD_EPSTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */ +#define USBD_EPSTATUS_EPIN2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 1 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */ +#define USBD_EPSTATUS_EPIN1_Msk (0x1UL << USBD_EPSTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */ +#define USBD_EPSTATUS_EPIN1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 0 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN0_Pos (0UL) /*!< Position of EPIN0 field. */ +#define USBD_EPSTATUS_EPIN0_Msk (0x1UL << USBD_EPSTATUS_EPIN0_Pos) /*!< Bit mask of EPIN0 field. */ +#define USBD_EPSTATUS_EPIN0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Register: USBD_EPDATASTATUS */ +/* Description: Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) */ + +/* Bit 23 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */ +#define USBD_EPDATASTATUS_EPOUT7_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */ +#define USBD_EPDATASTATUS_EPOUT7_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT7_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 22 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */ +#define USBD_EPDATASTATUS_EPOUT6_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */ +#define USBD_EPDATASTATUS_EPOUT6_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT6_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 21 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */ +#define USBD_EPDATASTATUS_EPOUT5_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */ +#define USBD_EPDATASTATUS_EPOUT5_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT5_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 20 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */ +#define USBD_EPDATASTATUS_EPOUT4_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */ +#define USBD_EPDATASTATUS_EPOUT4_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT4_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 19 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */ +#define USBD_EPDATASTATUS_EPOUT3_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */ +#define USBD_EPDATASTATUS_EPOUT3_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT3_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 18 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */ +#define USBD_EPDATASTATUS_EPOUT2_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */ +#define USBD_EPDATASTATUS_EPOUT2_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT2_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 17 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */ +#define USBD_EPDATASTATUS_EPOUT1_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */ +#define USBD_EPDATASTATUS_EPOUT1_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT1_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 7 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */ +#define USBD_EPDATASTATUS_EPIN7_Msk (0x1UL << USBD_EPDATASTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */ +#define USBD_EPDATASTATUS_EPIN7_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN7_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 6 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */ +#define USBD_EPDATASTATUS_EPIN6_Msk (0x1UL << USBD_EPDATASTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */ +#define USBD_EPDATASTATUS_EPIN6_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN6_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 5 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */ +#define USBD_EPDATASTATUS_EPIN5_Msk (0x1UL << USBD_EPDATASTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */ +#define USBD_EPDATASTATUS_EPIN5_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN5_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 4 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */ +#define USBD_EPDATASTATUS_EPIN4_Msk (0x1UL << USBD_EPDATASTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */ +#define USBD_EPDATASTATUS_EPIN4_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN4_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 3 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */ +#define USBD_EPDATASTATUS_EPIN3_Msk (0x1UL << USBD_EPDATASTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */ +#define USBD_EPDATASTATUS_EPIN3_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN3_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 2 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */ +#define USBD_EPDATASTATUS_EPIN2_Msk (0x1UL << USBD_EPDATASTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */ +#define USBD_EPDATASTATUS_EPIN2_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN2_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 1 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */ +#define USBD_EPDATASTATUS_EPIN1_Msk (0x1UL << USBD_EPDATASTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */ +#define USBD_EPDATASTATUS_EPIN1_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN1_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Register: USBD_USBADDR */ +/* Description: Device USB address */ + +/* Bits 6..0 : Device USB address */ +#define USBD_USBADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ +#define USBD_USBADDR_ADDR_Msk (0x7FUL << USBD_USBADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ + +/* Register: USBD_BMREQUESTTYPE */ +/* Description: SETUP data, byte 0, bmRequestType */ + +/* Bit 7 : Data transfer direction */ +#define USBD_BMREQUESTTYPE_DIRECTION_Pos (7UL) /*!< Position of DIRECTION field. */ +#define USBD_BMREQUESTTYPE_DIRECTION_Msk (0x1UL << USBD_BMREQUESTTYPE_DIRECTION_Pos) /*!< Bit mask of DIRECTION field. */ +#define USBD_BMREQUESTTYPE_DIRECTION_HostToDevice (0UL) /*!< Host-to-device */ +#define USBD_BMREQUESTTYPE_DIRECTION_DeviceToHost (1UL) /*!< Device-to-host */ + +/* Bits 6..5 : Data transfer type */ +#define USBD_BMREQUESTTYPE_TYPE_Pos (5UL) /*!< Position of TYPE field. */ +#define USBD_BMREQUESTTYPE_TYPE_Msk (0x3UL << USBD_BMREQUESTTYPE_TYPE_Pos) /*!< Bit mask of TYPE field. */ +#define USBD_BMREQUESTTYPE_TYPE_Standard (0UL) /*!< Standard */ +#define USBD_BMREQUESTTYPE_TYPE_Class (1UL) /*!< Class */ +#define USBD_BMREQUESTTYPE_TYPE_Vendor (2UL) /*!< Vendor */ + +/* Bits 4..0 : Data transfer type */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Pos (0UL) /*!< Position of RECIPIENT field. */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Msk (0x1FUL << USBD_BMREQUESTTYPE_RECIPIENT_Pos) /*!< Bit mask of RECIPIENT field. */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Device (0UL) /*!< Device */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Interface (1UL) /*!< Interface */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Endpoint (2UL) /*!< Endpoint */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Other (3UL) /*!< Other */ + +/* Register: USBD_BREQUEST */ +/* Description: SETUP data, byte 1, bRequest */ + +/* Bits 7..0 : SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. */ +#define USBD_BREQUEST_BREQUEST_Pos (0UL) /*!< Position of BREQUEST field. */ +#define USBD_BREQUEST_BREQUEST_Msk (0xFFUL << USBD_BREQUEST_BREQUEST_Pos) /*!< Bit mask of BREQUEST field. */ +#define USBD_BREQUEST_BREQUEST_STD_GET_STATUS (0UL) /*!< Standard request GET_STATUS */ +#define USBD_BREQUEST_BREQUEST_STD_CLEAR_FEATURE (1UL) /*!< Standard request CLEAR_FEATURE */ +#define USBD_BREQUEST_BREQUEST_STD_SET_FEATURE (3UL) /*!< Standard request SET_FEATURE */ +#define USBD_BREQUEST_BREQUEST_STD_SET_ADDRESS (5UL) /*!< Standard request SET_ADDRESS */ +#define USBD_BREQUEST_BREQUEST_STD_GET_DESCRIPTOR (6UL) /*!< Standard request GET_DESCRIPTOR */ +#define USBD_BREQUEST_BREQUEST_STD_SET_DESCRIPTOR (7UL) /*!< Standard request SET_DESCRIPTOR */ +#define USBD_BREQUEST_BREQUEST_STD_GET_CONFIGURATION (8UL) /*!< Standard request GET_CONFIGURATION */ +#define USBD_BREQUEST_BREQUEST_STD_SET_CONFIGURATION (9UL) /*!< Standard request SET_CONFIGURATION */ +#define USBD_BREQUEST_BREQUEST_STD_GET_INTERFACE (10UL) /*!< Standard request GET_INTERFACE */ +#define USBD_BREQUEST_BREQUEST_STD_SET_INTERFACE (11UL) /*!< Standard request SET_INTERFACE */ +#define USBD_BREQUEST_BREQUEST_STD_SYNCH_FRAME (12UL) /*!< Standard request SYNCH_FRAME */ + +/* Register: USBD_WVALUEL */ +/* Description: SETUP data, byte 2, LSB of wValue */ + +/* Bits 7..0 : SETUP data, byte 2, LSB of wValue */ +#define USBD_WVALUEL_WVALUEL_Pos (0UL) /*!< Position of WVALUEL field. */ +#define USBD_WVALUEL_WVALUEL_Msk (0xFFUL << USBD_WVALUEL_WVALUEL_Pos) /*!< Bit mask of WVALUEL field. */ + +/* Register: USBD_WVALUEH */ +/* Description: SETUP data, byte 3, MSB of wValue */ + +/* Bits 7..0 : SETUP data, byte 3, MSB of wValue */ +#define USBD_WVALUEH_WVALUEH_Pos (0UL) /*!< Position of WVALUEH field. */ +#define USBD_WVALUEH_WVALUEH_Msk (0xFFUL << USBD_WVALUEH_WVALUEH_Pos) /*!< Bit mask of WVALUEH field. */ + +/* Register: USBD_WINDEXL */ +/* Description: SETUP data, byte 4, LSB of wIndex */ + +/* Bits 7..0 : SETUP data, byte 4, LSB of wIndex */ +#define USBD_WINDEXL_WINDEXL_Pos (0UL) /*!< Position of WINDEXL field. */ +#define USBD_WINDEXL_WINDEXL_Msk (0xFFUL << USBD_WINDEXL_WINDEXL_Pos) /*!< Bit mask of WINDEXL field. */ + +/* Register: USBD_WINDEXH */ +/* Description: SETUP data, byte 5, MSB of wIndex */ + +/* Bits 7..0 : SETUP data, byte 5, MSB of wIndex */ +#define USBD_WINDEXH_WINDEXH_Pos (0UL) /*!< Position of WINDEXH field. */ +#define USBD_WINDEXH_WINDEXH_Msk (0xFFUL << USBD_WINDEXH_WINDEXH_Pos) /*!< Bit mask of WINDEXH field. */ + +/* Register: USBD_WLENGTHL */ +/* Description: SETUP data, byte 6, LSB of wLength */ + +/* Bits 7..0 : SETUP data, byte 6, LSB of wLength */ +#define USBD_WLENGTHL_WLENGTHL_Pos (0UL) /*!< Position of WLENGTHL field. */ +#define USBD_WLENGTHL_WLENGTHL_Msk (0xFFUL << USBD_WLENGTHL_WLENGTHL_Pos) /*!< Bit mask of WLENGTHL field. */ + +/* Register: USBD_WLENGTHH */ +/* Description: SETUP data, byte 7, MSB of wLength */ + +/* Bits 7..0 : SETUP data, byte 7, MSB of wLength */ +#define USBD_WLENGTHH_WLENGTHH_Pos (0UL) /*!< Position of WLENGTHH field. */ +#define USBD_WLENGTHH_WLENGTHH_Msk (0xFFUL << USBD_WLENGTHH_WLENGTHH_Pos) /*!< Bit mask of WLENGTHH field. */ + +/* Register: USBD_SIZE_EPOUT */ +/* Description: Description collection: Number of bytes received last in the data stage of this OUT endpoint */ + +/* Bits 6..0 : Number of bytes received last in the data stage of this OUT endpoint */ +#define USBD_SIZE_EPOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */ +#define USBD_SIZE_EPOUT_SIZE_Msk (0x7FUL << USBD_SIZE_EPOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */ + +/* Register: USBD_SIZE_ISOOUT */ +/* Description: Number of bytes received last on this ISO OUT data endpoint */ + +/* Bit 16 : Zero-length data packet received */ +#define USBD_SIZE_ISOOUT_ZERO_Pos (16UL) /*!< Position of ZERO field. */ +#define USBD_SIZE_ISOOUT_ZERO_Msk (0x1UL << USBD_SIZE_ISOOUT_ZERO_Pos) /*!< Bit mask of ZERO field. */ +#define USBD_SIZE_ISOOUT_ZERO_Normal (0UL) /*!< No zero-length data received, use value in SIZE */ +#define USBD_SIZE_ISOOUT_ZERO_ZeroData (1UL) /*!< Zero-length data received, ignore value in SIZE */ + +/* Bits 9..0 : Number of bytes received last on this ISO OUT data endpoint */ +#define USBD_SIZE_ISOOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */ +#define USBD_SIZE_ISOOUT_SIZE_Msk (0x3FFUL << USBD_SIZE_ISOOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */ + +/* Register: USBD_ENABLE */ +/* Description: Enable USB */ + +/* Bit 0 : Enable USB */ +#define USBD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define USBD_ENABLE_ENABLE_Msk (0x1UL << USBD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define USBD_ENABLE_ENABLE_Disabled (0UL) /*!< USB peripheral is disabled */ +#define USBD_ENABLE_ENABLE_Enabled (1UL) /*!< USB peripheral is enabled */ + +/* Register: USBD_USBPULLUP */ +/* Description: Control of the USB pull-up */ + +/* Bit 0 : Control of the USB pull-up on the D+ line */ +#define USBD_USBPULLUP_CONNECT_Pos (0UL) /*!< Position of CONNECT field. */ +#define USBD_USBPULLUP_CONNECT_Msk (0x1UL << USBD_USBPULLUP_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define USBD_USBPULLUP_CONNECT_Disabled (0UL) /*!< Pull-up is disconnected */ +#define USBD_USBPULLUP_CONNECT_Enabled (1UL) /*!< Pull-up is connected to D+ */ + +/* Register: USBD_DPDMVALUE */ +/* Description: State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). */ + +/* Bits 4..0 : State D+ and D- lines will be forced into by the DPDMDRIVE task */ +#define USBD_DPDMVALUE_STATE_Pos (0UL) /*!< Position of STATE field. */ +#define USBD_DPDMVALUE_STATE_Msk (0x1FUL << USBD_DPDMVALUE_STATE_Pos) /*!< Bit mask of STATE field. */ +#define USBD_DPDMVALUE_STATE_Resume (1UL) /*!< D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) */ +#define USBD_DPDMVALUE_STATE_J (2UL) /*!< D+ forced high, D- forced low (J state) */ +#define USBD_DPDMVALUE_STATE_K (4UL) /*!< D+ forced low, D- forced high (K state) */ + +/* Register: USBD_DTOGGLE */ +/* Description: Data toggle control and status */ + +/* Bits 9..8 : Data toggle value */ +#define USBD_DTOGGLE_VALUE_Pos (8UL) /*!< Position of VALUE field. */ +#define USBD_DTOGGLE_VALUE_Msk (0x3UL << USBD_DTOGGLE_VALUE_Pos) /*!< Bit mask of VALUE field. */ +#define USBD_DTOGGLE_VALUE_Nop (0UL) /*!< No action on data toggle when writing the register with this value */ +#define USBD_DTOGGLE_VALUE_Data0 (1UL) /*!< Data toggle is DATA0 on endpoint set by EP and IO */ +#define USBD_DTOGGLE_VALUE_Data1 (2UL) /*!< Data toggle is DATA1 on endpoint set by EP and IO */ + +/* Bit 7 : Selects IN or OUT endpoint */ +#define USBD_DTOGGLE_IO_Pos (7UL) /*!< Position of IO field. */ +#define USBD_DTOGGLE_IO_Msk (0x1UL << USBD_DTOGGLE_IO_Pos) /*!< Bit mask of IO field. */ +#define USBD_DTOGGLE_IO_Out (0UL) /*!< Selects OUT endpoint */ +#define USBD_DTOGGLE_IO_In (1UL) /*!< Selects IN endpoint */ + +/* Bits 2..0 : Select bulk endpoint number */ +#define USBD_DTOGGLE_EP_Pos (0UL) /*!< Position of EP field. */ +#define USBD_DTOGGLE_EP_Msk (0x7UL << USBD_DTOGGLE_EP_Pos) /*!< Bit mask of EP field. */ + +/* Register: USBD_EPINEN */ +/* Description: Endpoint IN enable */ + +/* Bit 8 : Enable ISO IN endpoint */ +#define USBD_EPINEN_ISOIN_Pos (8UL) /*!< Position of ISOIN field. */ +#define USBD_EPINEN_ISOIN_Msk (0x1UL << USBD_EPINEN_ISOIN_Pos) /*!< Bit mask of ISOIN field. */ +#define USBD_EPINEN_ISOIN_Disable (0UL) /*!< Disable ISO IN endpoint 8 */ +#define USBD_EPINEN_ISOIN_Enable (1UL) /*!< Enable ISO IN endpoint 8 */ + +/* Bit 7 : Enable IN endpoint 7 */ +#define USBD_EPINEN_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define USBD_EPINEN_IN7_Msk (0x1UL << USBD_EPINEN_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define USBD_EPINEN_IN7_Disable (0UL) /*!< Disable endpoint IN 7 (no response to IN tokens) */ +#define USBD_EPINEN_IN7_Enable (1UL) /*!< Enable endpoint IN 7 (response to IN tokens) */ + +/* Bit 6 : Enable IN endpoint 6 */ +#define USBD_EPINEN_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define USBD_EPINEN_IN6_Msk (0x1UL << USBD_EPINEN_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define USBD_EPINEN_IN6_Disable (0UL) /*!< Disable endpoint IN 6 (no response to IN tokens) */ +#define USBD_EPINEN_IN6_Enable (1UL) /*!< Enable endpoint IN 6 (response to IN tokens) */ + +/* Bit 5 : Enable IN endpoint 5 */ +#define USBD_EPINEN_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define USBD_EPINEN_IN5_Msk (0x1UL << USBD_EPINEN_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define USBD_EPINEN_IN5_Disable (0UL) /*!< Disable endpoint IN 5 (no response to IN tokens) */ +#define USBD_EPINEN_IN5_Enable (1UL) /*!< Enable endpoint IN 5 (response to IN tokens) */ + +/* Bit 4 : Enable IN endpoint 4 */ +#define USBD_EPINEN_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define USBD_EPINEN_IN4_Msk (0x1UL << USBD_EPINEN_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define USBD_EPINEN_IN4_Disable (0UL) /*!< Disable endpoint IN 4 (no response to IN tokens) */ +#define USBD_EPINEN_IN4_Enable (1UL) /*!< Enable endpoint IN 4 (response to IN tokens) */ + +/* Bit 3 : Enable IN endpoint 3 */ +#define USBD_EPINEN_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define USBD_EPINEN_IN3_Msk (0x1UL << USBD_EPINEN_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define USBD_EPINEN_IN3_Disable (0UL) /*!< Disable endpoint IN 3 (no response to IN tokens) */ +#define USBD_EPINEN_IN3_Enable (1UL) /*!< Enable endpoint IN 3 (response to IN tokens) */ + +/* Bit 2 : Enable IN endpoint 2 */ +#define USBD_EPINEN_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define USBD_EPINEN_IN2_Msk (0x1UL << USBD_EPINEN_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define USBD_EPINEN_IN2_Disable (0UL) /*!< Disable endpoint IN 2 (no response to IN tokens) */ +#define USBD_EPINEN_IN2_Enable (1UL) /*!< Enable endpoint IN 2 (response to IN tokens) */ + +/* Bit 1 : Enable IN endpoint 1 */ +#define USBD_EPINEN_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define USBD_EPINEN_IN1_Msk (0x1UL << USBD_EPINEN_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define USBD_EPINEN_IN1_Disable (0UL) /*!< Disable endpoint IN 1 (no response to IN tokens) */ +#define USBD_EPINEN_IN1_Enable (1UL) /*!< Enable endpoint IN 1 (response to IN tokens) */ + +/* Bit 0 : Enable IN endpoint 0 */ +#define USBD_EPINEN_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define USBD_EPINEN_IN0_Msk (0x1UL << USBD_EPINEN_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define USBD_EPINEN_IN0_Disable (0UL) /*!< Disable endpoint IN 0 (no response to IN tokens) */ +#define USBD_EPINEN_IN0_Enable (1UL) /*!< Enable endpoint IN 0 (response to IN tokens) */ + +/* Register: USBD_EPOUTEN */ +/* Description: Endpoint OUT enable */ + +/* Bit 8 : Enable ISO OUT endpoint 8 */ +#define USBD_EPOUTEN_ISOOUT_Pos (8UL) /*!< Position of ISOOUT field. */ +#define USBD_EPOUTEN_ISOOUT_Msk (0x1UL << USBD_EPOUTEN_ISOOUT_Pos) /*!< Bit mask of ISOOUT field. */ +#define USBD_EPOUTEN_ISOOUT_Disable (0UL) /*!< Disable ISO OUT endpoint 8 */ +#define USBD_EPOUTEN_ISOOUT_Enable (1UL) /*!< Enable ISO OUT endpoint 8 */ + +/* Bit 7 : Enable OUT endpoint 7 */ +#define USBD_EPOUTEN_OUT7_Pos (7UL) /*!< Position of OUT7 field. */ +#define USBD_EPOUTEN_OUT7_Msk (0x1UL << USBD_EPOUTEN_OUT7_Pos) /*!< Bit mask of OUT7 field. */ +#define USBD_EPOUTEN_OUT7_Disable (0UL) /*!< Disable endpoint OUT 7 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT7_Enable (1UL) /*!< Enable endpoint OUT 7 (response to OUT tokens) */ + +/* Bit 6 : Enable OUT endpoint 6 */ +#define USBD_EPOUTEN_OUT6_Pos (6UL) /*!< Position of OUT6 field. */ +#define USBD_EPOUTEN_OUT6_Msk (0x1UL << USBD_EPOUTEN_OUT6_Pos) /*!< Bit mask of OUT6 field. */ +#define USBD_EPOUTEN_OUT6_Disable (0UL) /*!< Disable endpoint OUT 6 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT6_Enable (1UL) /*!< Enable endpoint OUT 6 (response to OUT tokens) */ + +/* Bit 5 : Enable OUT endpoint 5 */ +#define USBD_EPOUTEN_OUT5_Pos (5UL) /*!< Position of OUT5 field. */ +#define USBD_EPOUTEN_OUT5_Msk (0x1UL << USBD_EPOUTEN_OUT5_Pos) /*!< Bit mask of OUT5 field. */ +#define USBD_EPOUTEN_OUT5_Disable (0UL) /*!< Disable endpoint OUT 5 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT5_Enable (1UL) /*!< Enable endpoint OUT 5 (response to OUT tokens) */ + +/* Bit 4 : Enable OUT endpoint 4 */ +#define USBD_EPOUTEN_OUT4_Pos (4UL) /*!< Position of OUT4 field. */ +#define USBD_EPOUTEN_OUT4_Msk (0x1UL << USBD_EPOUTEN_OUT4_Pos) /*!< Bit mask of OUT4 field. */ +#define USBD_EPOUTEN_OUT4_Disable (0UL) /*!< Disable endpoint OUT 4 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT4_Enable (1UL) /*!< Enable endpoint OUT 4 (response to OUT tokens) */ + +/* Bit 3 : Enable OUT endpoint 3 */ +#define USBD_EPOUTEN_OUT3_Pos (3UL) /*!< Position of OUT3 field. */ +#define USBD_EPOUTEN_OUT3_Msk (0x1UL << USBD_EPOUTEN_OUT3_Pos) /*!< Bit mask of OUT3 field. */ +#define USBD_EPOUTEN_OUT3_Disable (0UL) /*!< Disable endpoint OUT 3 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT3_Enable (1UL) /*!< Enable endpoint OUT 3 (response to OUT tokens) */ + +/* Bit 2 : Enable OUT endpoint 2 */ +#define USBD_EPOUTEN_OUT2_Pos (2UL) /*!< Position of OUT2 field. */ +#define USBD_EPOUTEN_OUT2_Msk (0x1UL << USBD_EPOUTEN_OUT2_Pos) /*!< Bit mask of OUT2 field. */ +#define USBD_EPOUTEN_OUT2_Disable (0UL) /*!< Disable endpoint OUT 2 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT2_Enable (1UL) /*!< Enable endpoint OUT 2 (response to OUT tokens) */ + +/* Bit 1 : Enable OUT endpoint 1 */ +#define USBD_EPOUTEN_OUT1_Pos (1UL) /*!< Position of OUT1 field. */ +#define USBD_EPOUTEN_OUT1_Msk (0x1UL << USBD_EPOUTEN_OUT1_Pos) /*!< Bit mask of OUT1 field. */ +#define USBD_EPOUTEN_OUT1_Disable (0UL) /*!< Disable endpoint OUT 1 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT1_Enable (1UL) /*!< Enable endpoint OUT 1 (response to OUT tokens) */ + +/* Bit 0 : Enable OUT endpoint 0 */ +#define USBD_EPOUTEN_OUT0_Pos (0UL) /*!< Position of OUT0 field. */ +#define USBD_EPOUTEN_OUT0_Msk (0x1UL << USBD_EPOUTEN_OUT0_Pos) /*!< Bit mask of OUT0 field. */ +#define USBD_EPOUTEN_OUT0_Disable (0UL) /*!< Disable endpoint OUT 0 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT0_Enable (1UL) /*!< Enable endpoint OUT 0 (response to OUT tokens) */ + +/* Register: USBD_EPSTALL */ +/* Description: STALL endpoints */ + +/* Bit 8 : Stall selected endpoint */ +#define USBD_EPSTALL_STALL_Pos (8UL) /*!< Position of STALL field. */ +#define USBD_EPSTALL_STALL_Msk (0x1UL << USBD_EPSTALL_STALL_Pos) /*!< Bit mask of STALL field. */ +#define USBD_EPSTALL_STALL_UnStall (0UL) /*!< Don't stall selected endpoint */ +#define USBD_EPSTALL_STALL_Stall (1UL) /*!< Stall selected endpoint */ + +/* Bit 7 : Selects IN or OUT endpoint */ +#define USBD_EPSTALL_IO_Pos (7UL) /*!< Position of IO field. */ +#define USBD_EPSTALL_IO_Msk (0x1UL << USBD_EPSTALL_IO_Pos) /*!< Bit mask of IO field. */ +#define USBD_EPSTALL_IO_Out (0UL) /*!< Selects OUT endpoint */ +#define USBD_EPSTALL_IO_In (1UL) /*!< Selects IN endpoint */ + +/* Bits 2..0 : Select endpoint number */ +#define USBD_EPSTALL_EP_Pos (0UL) /*!< Position of EP field. */ +#define USBD_EPSTALL_EP_Msk (0x7UL << USBD_EPSTALL_EP_Pos) /*!< Bit mask of EP field. */ + +/* Register: USBD_ISOSPLIT */ +/* Description: Controls the split of ISO buffers */ + +/* Bits 15..0 : Controls the split of ISO buffers */ +#define USBD_ISOSPLIT_SPLIT_Pos (0UL) /*!< Position of SPLIT field. */ +#define USBD_ISOSPLIT_SPLIT_Msk (0xFFFFUL << USBD_ISOSPLIT_SPLIT_Pos) /*!< Bit mask of SPLIT field. */ +#define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either iso IN or OUT */ +#define USBD_ISOSPLIT_SPLIT_HalfIN (0x0080UL) /*!< Lower half for IN, upper half for OUT */ + +/* Register: USBD_FRAMECNTR */ +/* Description: Returns the current value of the start of frame counter */ + +/* Bits 10..0 : Returns the current value of the start of frame counter */ +#define USBD_FRAMECNTR_FRAMECNTR_Pos (0UL) /*!< Position of FRAMECNTR field. */ +#define USBD_FRAMECNTR_FRAMECNTR_Msk (0x7FFUL << USBD_FRAMECNTR_FRAMECNTR_Pos) /*!< Bit mask of FRAMECNTR field. */ + +/* Register: USBD_LOWPOWER */ +/* Description: Controls USBD peripheral low power mode during USB suspend */ + +/* Bit 0 : Controls USBD peripheral low-power mode during USB suspend */ +#define USBD_LOWPOWER_LOWPOWER_Pos (0UL) /*!< Position of LOWPOWER field. */ +#define USBD_LOWPOWER_LOWPOWER_Msk (0x1UL << USBD_LOWPOWER_LOWPOWER_Pos) /*!< Bit mask of LOWPOWER field. */ +#define USBD_LOWPOWER_LOWPOWER_ForceNormal (0UL) /*!< Software must write this value to exit low power mode and before performing a remote wake-up */ +#define USBD_LOWPOWER_LOWPOWER_LowPower (1UL) /*!< Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral */ + +/* Register: USBD_ISOINCONFIG */ +/* Description: Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */ + +/* Bit 0 : Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */ +#define USBD_ISOINCONFIG_RESPONSE_Pos (0UL) /*!< Position of RESPONSE field. */ +#define USBD_ISOINCONFIG_RESPONSE_Msk (0x1UL << USBD_ISOINCONFIG_RESPONSE_Pos) /*!< Bit mask of RESPONSE field. */ +#define USBD_ISOINCONFIG_RESPONSE_NoResp (0UL) /*!< Endpoint does not respond in that case */ +#define USBD_ISOINCONFIG_RESPONSE_ZeroData (1UL) /*!< Endpoint responds with a zero-length data packet in that case */ + +/* Register: USBD_EPIN_PTR */ +/* Description: Description cluster: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define USBD_EPIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: USBD_EPIN_MAXCNT */ +/* Description: Description cluster: Maximum number of bytes to transfer */ + +/* Bits 6..0 : Maximum number of bytes to transfer */ +#define USBD_EPIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define USBD_EPIN_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: USBD_EPIN_AMOUNT */ +/* Description: Description cluster: Number of bytes transferred in the last transaction */ + +/* Bits 6..0 : Number of bytes transferred in the last transaction */ +#define USBD_EPIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define USBD_EPIN_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: USBD_ISOIN_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define USBD_ISOIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define USBD_ISOIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: USBD_ISOIN_MAXCNT */ +/* Description: Maximum number of bytes to transfer */ + +/* Bits 9..0 : Maximum number of bytes to transfer */ +#define USBD_ISOIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define USBD_ISOIN_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: USBD_ISOIN_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 9..0 : Number of bytes transferred in the last transaction */ +#define USBD_ISOIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define USBD_ISOIN_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: USBD_EPOUT_PTR */ +/* Description: Description cluster: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define USBD_EPOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: USBD_EPOUT_MAXCNT */ +/* Description: Description cluster: Maximum number of bytes to transfer */ + +/* Bits 6..0 : Maximum number of bytes to transfer */ +#define USBD_EPOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define USBD_EPOUT_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: USBD_EPOUT_AMOUNT */ +/* Description: Description cluster: Number of bytes transferred in the last transaction */ + +/* Bits 6..0 : Number of bytes transferred in the last transaction */ +#define USBD_EPOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define USBD_EPOUT_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: USBD_ISOOUT_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define USBD_ISOOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define USBD_ISOOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: USBD_ISOOUT_MAXCNT */ +/* Description: Maximum number of bytes to transfer */ + +/* Bits 9..0 : Maximum number of bytes to transfer */ +#define USBD_ISOOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define USBD_ISOOUT_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: USBD_ISOOUT_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 9..0 : Number of bytes transferred in the last transaction */ +#define USBD_ISOOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define USBD_ISOOUT_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + +/* Peripheral: WDT */ +/* Description: Watchdog Timer */ + +/* Register: WDT_TASKS_START */ +/* Description: Start the watchdog */ + +/* Bit 0 : Start the watchdog */ +#define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: WDT_EVENTS_TIMEOUT */ +/* Description: Watchdog timeout */ + +/* Bit 0 : Watchdog timeout */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */ + +/* Register: WDT_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */ +#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */ + +/* Register: WDT_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */ +#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */ + +/* Register: WDT_RUNSTATUS */ +/* Description: Run status */ + +/* Bit 0 : Indicates whether or not the watchdog is running */ +#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */ +#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */ + +/* Register: WDT_REQSTATUS */ +/* Description: Request status */ + +/* Bit 7 : Request status for RR[7] register */ +#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ + +/* Bit 6 : Request status for RR[6] register */ +#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ + +/* Bit 5 : Request status for RR[5] register */ +#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ + +/* Bit 4 : Request status for RR[4] register */ +#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ + +/* Bit 3 : Request status for RR[3] register */ +#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ + +/* Bit 2 : Request status for RR[2] register */ +#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ + +/* Bit 1 : Request status for RR[1] register */ +#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ + +/* Bit 0 : Request status for RR[0] register */ +#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ + +/* Register: WDT_CRV */ +/* Description: Counter reload value */ + +/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */ +#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */ +#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */ + +/* Register: WDT_RREN */ +/* Description: Enable register for reload request registers */ + +/* Bit 7 : Enable or disable RR[7] register */ +#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */ +#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */ + +/* Bit 6 : Enable or disable RR[6] register */ +#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */ +#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */ + +/* Bit 5 : Enable or disable RR[5] register */ +#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */ +#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */ + +/* Bit 4 : Enable or disable RR[4] register */ +#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */ +#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */ + +/* Bit 3 : Enable or disable RR[3] register */ +#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */ +#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */ + +/* Bit 2 : Enable or disable RR[2] register */ +#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */ +#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */ + +/* Bit 1 : Enable or disable RR[1] register */ +#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */ +#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */ + +/* Bit 0 : Enable or disable RR[0] register */ +#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */ +#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */ + +/* Register: WDT_CONFIG */ +/* Description: Configuration register */ + +/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ +#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ +#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ + +/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ + +/* Register: WDT_RR */ +/* Description: Description collection: Reload request n */ + +/* Bits 31..0 : Reload request register */ +#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ +#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ +#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */ + + +/*lint --flb "Leave library region" */ +#endif diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_peripherals.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_peripherals.h new file mode 100644 index 000000000..0dd2dcba0 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_peripherals.h @@ -0,0 +1,240 @@ +/* + +Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef _NRF52820_PERIPHERALS_H +#define _NRF52820_PERIPHERALS_H + +/* Clock Peripheral */ +#define CLOCK_PRESENT +#define CLOCK_COUNT 1 + +/* Power Peripheral */ +#define POWER_PRESENT +#define POWER_COUNT 1 + +#define POWER_FEATURE_RAM_REGISTERS_PRESENT +#define POWER_FEATURE_RAM_REGISTERS_COUNT 4 + +#define POWER_FEATURE_VDDH_PRESENT + +/* Non-Volatile Memory Controller */ +#define NVMC_PRESENT +#define NVMC_COUNT 1 + +/* Systick timer */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 + +/* Software Interrupts */ +#define SWI_PRESENT +#define SWI_COUNT 6 + +/* GPIO */ +#define GPIO_PRESENT +#define GPIO_COUNT 1 + +#define P0_PIN_NUM (18) +#define P0_FEATURE_PINS_PRESENT (nrf52_errata_230() ? 0xF0168E3Ful : 0x7017C1FFul) + +/* ACL */ +#define ACL_PRESENT + +#define ACL_REGIONS_COUNT 8 + +/* Radio */ +#define RADIO_PRESENT +#define RADIO_COUNT 1 + +#define RADIO_EASYDMA_MAXCNT_SIZE 16 +#define RADIO_FEATURE_IEEE_802_15_4_PRESENT + +#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos8dBm + +/* Accelerated Address Resolver */ +#define AAR_PRESENT +#define AAR_COUNT 1 + +#define AAR_MAX_IRK_NUM 16 + +/* AES Electronic CodeBook mode encryption */ +#define ECB_PRESENT +#define ECB_COUNT 1 + +/* AES CCM mode encryption */ +#define CCM_PRESENT +#define CCM_COUNT 1 + +/* Peripheral to Peripheral Interconnect */ +#define PPI_PRESENT +#define PPI_COUNT 1 + +#define PPI_CH_NUM 20 +#define PPI_FIXED_CH_NUM 12 +#define PPI_GROUP_NUM 6 +#define PPI_FEATURE_FORKS_PRESENT + +/* Event Generator Unit */ +#define EGU_PRESENT +#define EGU_COUNT 6 + +#define EGU0_CH_NUM 16 +#define EGU1_CH_NUM 16 +#define EGU2_CH_NUM 16 +#define EGU3_CH_NUM 16 +#define EGU4_CH_NUM 16 +#define EGU5_CH_NUM 16 + +/* Timer/Counter */ +#define TIMER_PRESENT +#define TIMER_COUNT 4 + +#define TIMER0_MAX_SIZE 32 +#define TIMER1_MAX_SIZE 32 +#define TIMER2_MAX_SIZE 32 +#define TIMER3_MAX_SIZE 32 + +#define TIMER0_CC_NUM 4 +#define TIMER1_CC_NUM 4 +#define TIMER2_CC_NUM 4 +#define TIMER3_CC_NUM 6 + +/* Real Time Counter */ +#define RTC_PRESENT +#define RTC_COUNT 2 + +#define RTC0_CC_NUM 3 +#define RTC1_CC_NUM 4 + +/* RNG */ +#define RNG_PRESENT +#define RNG_COUNT 1 + +/* Watchdog Timer */ +#define WDT_PRESENT +#define WDT_COUNT 1 + +/* Temperature Sensor */ +#define TEMP_PRESENT +#define TEMP_COUNT 1 + +/* Serial Peripheral Interface Master */ +#define SPI_PRESENT +#define SPI_COUNT 2 + +/* Serial Peripheral Interface Master with DMA */ +#define SPIM_PRESENT +#define SPIM_COUNT 2 + +#define SPIM0_MAX_DATARATE 8 +#define SPIM1_MAX_DATARATE 8 + +#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0 +#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0 + +#define SPIM0_FEATURE_DCX_PRESENT 0 +#define SPIM1_FEATURE_DCX_PRESENT 0 + +#define SPIM0_FEATURE_RXDELAY_PRESENT 0 +#define SPIM1_FEATURE_RXDELAY_PRESENT 0 + +#define SPIM0_EASYDMA_MAXCNT_SIZE 16 +#define SPIM1_EASYDMA_MAXCNT_SIZE 16 + +/* Serial Peripheral Interface Slave with DMA*/ +#define SPIS_PRESENT +#define SPIS_COUNT 2 + +#define SPIS0_EASYDMA_MAXCNT_SIZE 16 +#define SPIS1_EASYDMA_MAXCNT_SIZE 16 + +/* Two Wire Interface Master */ +#define TWI_PRESENT +#define TWI_COUNT 2 + +/* Two Wire Interface Master with DMA */ +#define TWIM_PRESENT +#define TWIM_COUNT 2 + +#define TWIM0_EASYDMA_MAXCNT_SIZE 16 +#define TWIM1_EASYDMA_MAXCNT_SIZE 16 + +/* Two Wire Interface Slave with DMA */ +#define TWIS_PRESENT +#define TWIS_COUNT 2 + +#define TWIS0_EASYDMA_MAXCNT_SIZE 16 +#define TWIS1_EASYDMA_MAXCNT_SIZE 16 + +/* Universal Asynchronous Receiver-Transmitter */ +#define UART_PRESENT +#define UART_COUNT 1 + +/* Universal Asynchronous Receiver-Transmitter with DMA */ +#define UARTE_PRESENT +#define UARTE_COUNT 1 + +#define UARTE0_EASYDMA_MAXCNT_SIZE 16 + +/* Quadrature Decoder */ +#define QDEC_PRESENT +#define QDEC_COUNT 1 + +/* GPIO Tasks and Events */ +#define GPIOTE_PRESENT +#define GPIOTE_COUNT 1 + +#define GPIOTE_CH_NUM 8 + +#define GPIOTE_FEATURE_SET_PRESENT +#define GPIOTE_FEATURE_CLR_PRESENT + +/* Comparator */ +#define COMP_PRESENT +#define COMP_COUNT 1 + + +/* Universal Serial Bus Device */ +#define USBD_PRESENT +#define USBD_COUNT 1 + +#define USBD_EASYDMA_MAXCNT_SIZE 7 + +#endif // _NRF52820_PERIPHERALS_H diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52833_to_nrf52820.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52833_to_nrf52820.h new file mode 100644 index 000000000..09777aeca --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52833_to_nrf52820.h @@ -0,0 +1,54 @@ +/* + +Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF52833_TO_NRF52820_H +#define NRF52833_TO_NRF52820_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the name changes between nRF52833 and nRF52820 devices. + * It redefines the old nRF52833 names into the new ones as long as the functionality is still supported. If the + * functionality is gone, there old names are not defined, so compilation will fail. */ + +/* Differences between latest nRF52833 headers and nRF52820 headers. */ + +#endif /* NRF52833_TO_NRF52820_H */ + diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_bitfields.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_bitfields.h new file mode 100644 index 000000000..70672e800 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_bitfields.h @@ -0,0 +1,12663 @@ +/* + +Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef __NRF52_BITS_H +#define __NRF52_BITS_H + +/*lint ++flb "Enter library region" */ + +/* Peripheral: AAR */ +/* Description: Accelerated Address Resolver */ + +/* Register: AAR_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */ +#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */ +#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for END event */ +#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Register: AAR_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */ +#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */ +#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for END event */ +#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Register: AAR_STATUS */ +/* Description: Resolution status */ + +/* Bits 3..0 : The IRK that was used last time an address was resolved */ +#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ + +/* Register: AAR_ENABLE */ +/* Description: Enable AAR */ + +/* Bits 1..0 : Enable or disable AAR */ +#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */ + +/* Register: AAR_NIRK */ +/* Description: Number of IRKs */ + +/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */ +#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ +#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ + +/* Register: AAR_IRKPTR */ +/* Description: Pointer to IRK data structure */ + +/* Bits 31..0 : Pointer to the IRK data structure */ +#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */ +#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */ + +/* Register: AAR_ADDRPTR */ +/* Description: Pointer to the resolvable address */ + +/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */ +#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */ +#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */ + +/* Register: AAR_SCRATCHPTR */ +/* Description: Pointer to data area used for temporary storage */ + +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */ +#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ +#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ + + +/* Peripheral: BPROT */ +/* Description: Block Protect */ + +/* Register: BPROT_CONFIG0 */ +/* Description: Block protect configuration register 0 */ + +/* Bit 31 : Enable protection for region 31. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */ +#define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */ +#define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */ + +/* Bit 30 : Enable protection for region 30. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */ +#define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */ +#define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */ + +/* Bit 29 : Enable protection for region 29. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */ +#define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */ +#define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */ + +/* Bit 28 : Enable protection for region 28. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */ +#define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */ +#define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */ + +/* Bit 27 : Enable protection for region 27. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */ +#define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */ +#define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */ + +/* Bit 26 : Enable protection for region 26. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */ +#define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */ +#define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */ + +/* Bit 25 : Enable protection for region 25. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */ +#define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */ +#define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */ + +/* Bit 24 : Enable protection for region 24. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */ +#define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */ +#define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */ + +/* Bit 23 : Enable protection for region 23. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */ +#define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */ +#define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */ + +/* Bit 22 : Enable protection for region 22. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */ +#define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */ +#define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */ + +/* Bit 21 : Enable protection for region 21. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */ +#define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */ +#define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */ + +/* Bit 20 : Enable protection for region 20. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */ +#define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */ +#define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */ + +/* Bit 19 : Enable protection for region 19. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */ +#define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */ +#define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */ + +/* Bit 18 : Enable protection for region 18. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */ +#define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */ +#define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */ + +/* Bit 17 : Enable protection for region 17. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */ +#define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */ +#define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */ + +/* Bit 16 : Enable protection for region 16. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */ +#define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */ +#define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */ + +/* Bit 15 : Enable protection for region 15. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */ +#define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */ +#define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */ + +/* Bit 14 : Enable protection for region 14. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */ +#define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */ +#define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */ + +/* Bit 13 : Enable protection for region 13. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */ +#define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */ +#define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */ + +/* Bit 12 : Enable protection for region 12. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */ +#define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */ +#define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */ + +/* Bit 11 : Enable protection for region 11. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */ +#define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */ +#define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */ + +/* Bit 10 : Enable protection for region 10. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */ +#define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */ +#define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */ + +/* Bit 9 : Enable protection for region 9. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */ +#define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */ +#define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */ + +/* Bit 8 : Enable protection for region 8. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */ +#define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */ +#define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */ + +/* Bit 7 : Enable protection for region 7. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */ +#define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */ +#define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */ + +/* Bit 6 : Enable protection for region 6. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */ +#define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */ +#define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */ + +/* Bit 5 : Enable protection for region 5. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */ +#define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */ +#define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */ + +/* Bit 4 : Enable protection for region 4. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */ +#define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */ +#define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */ + +/* Bit 3 : Enable protection for region 3. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */ +#define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */ +#define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */ + +/* Bit 2 : Enable protection for region 2. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */ +#define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */ +#define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */ + +/* Bit 1 : Enable protection for region 1. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */ +#define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */ +#define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */ + +/* Bit 0 : Enable protection for region 0. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */ +#define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */ +#define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */ + +/* Register: BPROT_CONFIG1 */ +/* Description: Block protect configuration register 1 */ + +/* Bit 31 : Enable protection for region 63. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION63_Pos (31UL) /*!< Position of REGION63 field. */ +#define BPROT_CONFIG1_REGION63_Msk (0x1UL << BPROT_CONFIG1_REGION63_Pos) /*!< Bit mask of REGION63 field. */ +#define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 30 : Enable protection for region 62. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION62_Pos (30UL) /*!< Position of REGION62 field. */ +#define BPROT_CONFIG1_REGION62_Msk (0x1UL << BPROT_CONFIG1_REGION62_Pos) /*!< Bit mask of REGION62 field. */ +#define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 29 : Enable protection for region 61. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION61_Pos (29UL) /*!< Position of REGION61 field. */ +#define BPROT_CONFIG1_REGION61_Msk (0x1UL << BPROT_CONFIG1_REGION61_Pos) /*!< Bit mask of REGION61 field. */ +#define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 28 : Enable protection for region 60. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION60_Pos (28UL) /*!< Position of REGION60 field. */ +#define BPROT_CONFIG1_REGION60_Msk (0x1UL << BPROT_CONFIG1_REGION60_Pos) /*!< Bit mask of REGION60 field. */ +#define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 27 : Enable protection for region 59. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION59_Pos (27UL) /*!< Position of REGION59 field. */ +#define BPROT_CONFIG1_REGION59_Msk (0x1UL << BPROT_CONFIG1_REGION59_Pos) /*!< Bit mask of REGION59 field. */ +#define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 26 : Enable protection for region 58. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION58_Pos (26UL) /*!< Position of REGION58 field. */ +#define BPROT_CONFIG1_REGION58_Msk (0x1UL << BPROT_CONFIG1_REGION58_Pos) /*!< Bit mask of REGION58 field. */ +#define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 25 : Enable protection for region 57. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION57_Pos (25UL) /*!< Position of REGION57 field. */ +#define BPROT_CONFIG1_REGION57_Msk (0x1UL << BPROT_CONFIG1_REGION57_Pos) /*!< Bit mask of REGION57 field. */ +#define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 24 : Enable protection for region 56. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION56_Pos (24UL) /*!< Position of REGION56 field. */ +#define BPROT_CONFIG1_REGION56_Msk (0x1UL << BPROT_CONFIG1_REGION56_Pos) /*!< Bit mask of REGION56 field. */ +#define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 23 : Enable protection for region 55. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION55_Pos (23UL) /*!< Position of REGION55 field. */ +#define BPROT_CONFIG1_REGION55_Msk (0x1UL << BPROT_CONFIG1_REGION55_Pos) /*!< Bit mask of REGION55 field. */ +#define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 22 : Enable protection for region 54. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION54_Pos (22UL) /*!< Position of REGION54 field. */ +#define BPROT_CONFIG1_REGION54_Msk (0x1UL << BPROT_CONFIG1_REGION54_Pos) /*!< Bit mask of REGION54 field. */ +#define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 21 : Enable protection for region 53. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION53_Pos (21UL) /*!< Position of REGION53 field. */ +#define BPROT_CONFIG1_REGION53_Msk (0x1UL << BPROT_CONFIG1_REGION53_Pos) /*!< Bit mask of REGION53 field. */ +#define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 20 : Enable protection for region 52. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION52_Pos (20UL) /*!< Position of REGION52 field. */ +#define BPROT_CONFIG1_REGION52_Msk (0x1UL << BPROT_CONFIG1_REGION52_Pos) /*!< Bit mask of REGION52 field. */ +#define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 19 : Enable protection for region 51. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION51_Pos (19UL) /*!< Position of REGION51 field. */ +#define BPROT_CONFIG1_REGION51_Msk (0x1UL << BPROT_CONFIG1_REGION51_Pos) /*!< Bit mask of REGION51 field. */ +#define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 18 : Enable protection for region 50. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION50_Pos (18UL) /*!< Position of REGION50 field. */ +#define BPROT_CONFIG1_REGION50_Msk (0x1UL << BPROT_CONFIG1_REGION50_Pos) /*!< Bit mask of REGION50 field. */ +#define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 17 : Enable protection for region 49. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION49_Pos (17UL) /*!< Position of REGION49 field. */ +#define BPROT_CONFIG1_REGION49_Msk (0x1UL << BPROT_CONFIG1_REGION49_Pos) /*!< Bit mask of REGION49 field. */ +#define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 16 : Enable protection for region 48. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION48_Pos (16UL) /*!< Position of REGION48 field. */ +#define BPROT_CONFIG1_REGION48_Msk (0x1UL << BPROT_CONFIG1_REGION48_Pos) /*!< Bit mask of REGION48 field. */ +#define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 15 : Enable protection for region 47. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */ +#define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */ +#define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 14 : Enable protection for region 46. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */ +#define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */ +#define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 13 : Enable protection for region 45. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */ +#define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */ +#define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 12 : Enable protection for region 44. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */ +#define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */ +#define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 11 : Enable protection for region 43. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */ +#define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */ +#define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 10 : Enable protection for region 42. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */ +#define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */ +#define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 9 : Enable protection for region 41. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */ +#define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */ +#define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 8 : Enable protection for region 40. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */ +#define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */ +#define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 7 : Enable protection for region 39. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */ +#define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */ +#define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 6 : Enable protection for region 38. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */ +#define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */ +#define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 5 : Enable protection for region 37. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */ +#define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */ +#define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 4 : Enable protection for region 36. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */ +#define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */ +#define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 3 : Enable protection for region 35. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */ +#define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */ +#define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 2 : Enable protection for region 34. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */ +#define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */ +#define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 1 : Enable protection for region 33. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */ +#define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */ +#define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 0 : Enable protection for region 32. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */ +#define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */ +#define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */ + +/* Register: BPROT_DISABLEINDEBUG */ +/* Description: Disable protection mechanism in debug interface mode */ + +/* Bit 0 : Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */ + +/* Register: BPROT_CONFIG2 */ +/* Description: Block protect configuration register 2 */ + +/* Bit 31 : Enable protection for region 95. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION95_Pos (31UL) /*!< Position of REGION95 field. */ +#define BPROT_CONFIG2_REGION95_Msk (0x1UL << BPROT_CONFIG2_REGION95_Pos) /*!< Bit mask of REGION95 field. */ +#define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 30 : Enable protection for region 94. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION94_Pos (30UL) /*!< Position of REGION94 field. */ +#define BPROT_CONFIG2_REGION94_Msk (0x1UL << BPROT_CONFIG2_REGION94_Pos) /*!< Bit mask of REGION94 field. */ +#define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 29 : Enable protection for region 93. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION93_Pos (29UL) /*!< Position of REGION93 field. */ +#define BPROT_CONFIG2_REGION93_Msk (0x1UL << BPROT_CONFIG2_REGION93_Pos) /*!< Bit mask of REGION93 field. */ +#define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 28 : Enable protection for region 92. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION92_Pos (28UL) /*!< Position of REGION92 field. */ +#define BPROT_CONFIG2_REGION92_Msk (0x1UL << BPROT_CONFIG2_REGION92_Pos) /*!< Bit mask of REGION92 field. */ +#define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 27 : Enable protection for region 91. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION91_Pos (27UL) /*!< Position of REGION91 field. */ +#define BPROT_CONFIG2_REGION91_Msk (0x1UL << BPROT_CONFIG2_REGION91_Pos) /*!< Bit mask of REGION91 field. */ +#define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 26 : Enable protection for region 90. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION90_Pos (26UL) /*!< Position of REGION90 field. */ +#define BPROT_CONFIG2_REGION90_Msk (0x1UL << BPROT_CONFIG2_REGION90_Pos) /*!< Bit mask of REGION90 field. */ +#define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 25 : Enable protection for region 89. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION89_Pos (25UL) /*!< Position of REGION89 field. */ +#define BPROT_CONFIG2_REGION89_Msk (0x1UL << BPROT_CONFIG2_REGION89_Pos) /*!< Bit mask of REGION89 field. */ +#define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 24 : Enable protection for region 88. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION88_Pos (24UL) /*!< Position of REGION88 field. */ +#define BPROT_CONFIG2_REGION88_Msk (0x1UL << BPROT_CONFIG2_REGION88_Pos) /*!< Bit mask of REGION88 field. */ +#define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 23 : Enable protection for region 87. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION87_Pos (23UL) /*!< Position of REGION87 field. */ +#define BPROT_CONFIG2_REGION87_Msk (0x1UL << BPROT_CONFIG2_REGION87_Pos) /*!< Bit mask of REGION87 field. */ +#define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 22 : Enable protection for region 86. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION86_Pos (22UL) /*!< Position of REGION86 field. */ +#define BPROT_CONFIG2_REGION86_Msk (0x1UL << BPROT_CONFIG2_REGION86_Pos) /*!< Bit mask of REGION86 field. */ +#define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 21 : Enable protection for region 85. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION85_Pos (21UL) /*!< Position of REGION85 field. */ +#define BPROT_CONFIG2_REGION85_Msk (0x1UL << BPROT_CONFIG2_REGION85_Pos) /*!< Bit mask of REGION85 field. */ +#define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 20 : Enable protection for region 84. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION84_Pos (20UL) /*!< Position of REGION84 field. */ +#define BPROT_CONFIG2_REGION84_Msk (0x1UL << BPROT_CONFIG2_REGION84_Pos) /*!< Bit mask of REGION84 field. */ +#define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 19 : Enable protection for region 83. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION83_Pos (19UL) /*!< Position of REGION83 field. */ +#define BPROT_CONFIG2_REGION83_Msk (0x1UL << BPROT_CONFIG2_REGION83_Pos) /*!< Bit mask of REGION83 field. */ +#define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 18 : Enable protection for region 82. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION82_Pos (18UL) /*!< Position of REGION82 field. */ +#define BPROT_CONFIG2_REGION82_Msk (0x1UL << BPROT_CONFIG2_REGION82_Pos) /*!< Bit mask of REGION82 field. */ +#define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 17 : Enable protection for region 81. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION81_Pos (17UL) /*!< Position of REGION81 field. */ +#define BPROT_CONFIG2_REGION81_Msk (0x1UL << BPROT_CONFIG2_REGION81_Pos) /*!< Bit mask of REGION81 field. */ +#define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 16 : Enable protection for region 80. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION80_Pos (16UL) /*!< Position of REGION80 field. */ +#define BPROT_CONFIG2_REGION80_Msk (0x1UL << BPROT_CONFIG2_REGION80_Pos) /*!< Bit mask of REGION80 field. */ +#define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 15 : Enable protection for region 79. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION79_Pos (15UL) /*!< Position of REGION79 field. */ +#define BPROT_CONFIG2_REGION79_Msk (0x1UL << BPROT_CONFIG2_REGION79_Pos) /*!< Bit mask of REGION79 field. */ +#define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 14 : Enable protection for region 78. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION78_Pos (14UL) /*!< Position of REGION78 field. */ +#define BPROT_CONFIG2_REGION78_Msk (0x1UL << BPROT_CONFIG2_REGION78_Pos) /*!< Bit mask of REGION78 field. */ +#define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 13 : Enable protection for region 77. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION77_Pos (13UL) /*!< Position of REGION77 field. */ +#define BPROT_CONFIG2_REGION77_Msk (0x1UL << BPROT_CONFIG2_REGION77_Pos) /*!< Bit mask of REGION77 field. */ +#define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 12 : Enable protection for region 76. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION76_Pos (12UL) /*!< Position of REGION76 field. */ +#define BPROT_CONFIG2_REGION76_Msk (0x1UL << BPROT_CONFIG2_REGION76_Pos) /*!< Bit mask of REGION76 field. */ +#define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 11 : Enable protection for region 75. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION75_Pos (11UL) /*!< Position of REGION75 field. */ +#define BPROT_CONFIG2_REGION75_Msk (0x1UL << BPROT_CONFIG2_REGION75_Pos) /*!< Bit mask of REGION75 field. */ +#define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 10 : Enable protection for region 74. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION74_Pos (10UL) /*!< Position of REGION74 field. */ +#define BPROT_CONFIG2_REGION74_Msk (0x1UL << BPROT_CONFIG2_REGION74_Pos) /*!< Bit mask of REGION74 field. */ +#define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 9 : Enable protection for region 73. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION73_Pos (9UL) /*!< Position of REGION73 field. */ +#define BPROT_CONFIG2_REGION73_Msk (0x1UL << BPROT_CONFIG2_REGION73_Pos) /*!< Bit mask of REGION73 field. */ +#define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 8 : Enable protection for region 72. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION72_Pos (8UL) /*!< Position of REGION72 field. */ +#define BPROT_CONFIG2_REGION72_Msk (0x1UL << BPROT_CONFIG2_REGION72_Pos) /*!< Bit mask of REGION72 field. */ +#define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 7 : Enable protection for region 71. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION71_Pos (7UL) /*!< Position of REGION71 field. */ +#define BPROT_CONFIG2_REGION71_Msk (0x1UL << BPROT_CONFIG2_REGION71_Pos) /*!< Bit mask of REGION71 field. */ +#define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 6 : Enable protection for region 70. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION70_Pos (6UL) /*!< Position of REGION70 field. */ +#define BPROT_CONFIG2_REGION70_Msk (0x1UL << BPROT_CONFIG2_REGION70_Pos) /*!< Bit mask of REGION70 field. */ +#define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 5 : Enable protection for region 69. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION69_Pos (5UL) /*!< Position of REGION69 field. */ +#define BPROT_CONFIG2_REGION69_Msk (0x1UL << BPROT_CONFIG2_REGION69_Pos) /*!< Bit mask of REGION69 field. */ +#define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 4 : Enable protection for region 68. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION68_Pos (4UL) /*!< Position of REGION68 field. */ +#define BPROT_CONFIG2_REGION68_Msk (0x1UL << BPROT_CONFIG2_REGION68_Pos) /*!< Bit mask of REGION68 field. */ +#define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 3 : Enable protection for region 67. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION67_Pos (3UL) /*!< Position of REGION67 field. */ +#define BPROT_CONFIG2_REGION67_Msk (0x1UL << BPROT_CONFIG2_REGION67_Pos) /*!< Bit mask of REGION67 field. */ +#define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 2 : Enable protection for region 66. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */ +#define BPROT_CONFIG2_REGION66_Msk (0x1UL << BPROT_CONFIG2_REGION66_Pos) /*!< Bit mask of REGION66 field. */ +#define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 1 : Enable protection for region 65. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */ +#define BPROT_CONFIG2_REGION65_Msk (0x1UL << BPROT_CONFIG2_REGION65_Pos) /*!< Bit mask of REGION65 field. */ +#define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 0 : Enable protection for region 64. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION64_Pos (0UL) /*!< Position of REGION64 field. */ +#define BPROT_CONFIG2_REGION64_Msk (0x1UL << BPROT_CONFIG2_REGION64_Pos) /*!< Bit mask of REGION64 field. */ +#define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */ + +/* Register: BPROT_CONFIG3 */ +/* Description: Block protect configuration register 3 */ + +/* Bit 31 : Enable protection for region 127. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION127_Pos (31UL) /*!< Position of REGION127 field. */ +#define BPROT_CONFIG3_REGION127_Msk (0x1UL << BPROT_CONFIG3_REGION127_Pos) /*!< Bit mask of REGION127 field. */ +#define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 30 : Enable protection for region 126. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION126_Pos (30UL) /*!< Position of REGION126 field. */ +#define BPROT_CONFIG3_REGION126_Msk (0x1UL << BPROT_CONFIG3_REGION126_Pos) /*!< Bit mask of REGION126 field. */ +#define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 29 : Enable protection for region 125. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION125_Pos (29UL) /*!< Position of REGION125 field. */ +#define BPROT_CONFIG3_REGION125_Msk (0x1UL << BPROT_CONFIG3_REGION125_Pos) /*!< Bit mask of REGION125 field. */ +#define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 28 : Enable protection for region 124. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION124_Pos (28UL) /*!< Position of REGION124 field. */ +#define BPROT_CONFIG3_REGION124_Msk (0x1UL << BPROT_CONFIG3_REGION124_Pos) /*!< Bit mask of REGION124 field. */ +#define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 27 : Enable protection for region 123. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION123_Pos (27UL) /*!< Position of REGION123 field. */ +#define BPROT_CONFIG3_REGION123_Msk (0x1UL << BPROT_CONFIG3_REGION123_Pos) /*!< Bit mask of REGION123 field. */ +#define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 26 : Enable protection for region 122. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION122_Pos (26UL) /*!< Position of REGION122 field. */ +#define BPROT_CONFIG3_REGION122_Msk (0x1UL << BPROT_CONFIG3_REGION122_Pos) /*!< Bit mask of REGION122 field. */ +#define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 25 : Enable protection for region 121. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION121_Pos (25UL) /*!< Position of REGION121 field. */ +#define BPROT_CONFIG3_REGION121_Msk (0x1UL << BPROT_CONFIG3_REGION121_Pos) /*!< Bit mask of REGION121 field. */ +#define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 24 : Enable protection for region 120. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION120_Pos (24UL) /*!< Position of REGION120 field. */ +#define BPROT_CONFIG3_REGION120_Msk (0x1UL << BPROT_CONFIG3_REGION120_Pos) /*!< Bit mask of REGION120 field. */ +#define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 23 : Enable protection for region 119. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION119_Pos (23UL) /*!< Position of REGION119 field. */ +#define BPROT_CONFIG3_REGION119_Msk (0x1UL << BPROT_CONFIG3_REGION119_Pos) /*!< Bit mask of REGION119 field. */ +#define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 22 : Enable protection for region 118. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION118_Pos (22UL) /*!< Position of REGION118 field. */ +#define BPROT_CONFIG3_REGION118_Msk (0x1UL << BPROT_CONFIG3_REGION118_Pos) /*!< Bit mask of REGION118 field. */ +#define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 21 : Enable protection for region 117. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION117_Pos (21UL) /*!< Position of REGION117 field. */ +#define BPROT_CONFIG3_REGION117_Msk (0x1UL << BPROT_CONFIG3_REGION117_Pos) /*!< Bit mask of REGION117 field. */ +#define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 20 : Enable protection for region 116. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION116_Pos (20UL) /*!< Position of REGION116 field. */ +#define BPROT_CONFIG3_REGION116_Msk (0x1UL << BPROT_CONFIG3_REGION116_Pos) /*!< Bit mask of REGION116 field. */ +#define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 19 : Enable protection for region 115. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION115_Pos (19UL) /*!< Position of REGION115 field. */ +#define BPROT_CONFIG3_REGION115_Msk (0x1UL << BPROT_CONFIG3_REGION115_Pos) /*!< Bit mask of REGION115 field. */ +#define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 18 : Enable protection for region 114. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION114_Pos (18UL) /*!< Position of REGION114 field. */ +#define BPROT_CONFIG3_REGION114_Msk (0x1UL << BPROT_CONFIG3_REGION114_Pos) /*!< Bit mask of REGION114 field. */ +#define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 17 : Enable protection for region 113. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION113_Pos (17UL) /*!< Position of REGION113 field. */ +#define BPROT_CONFIG3_REGION113_Msk (0x1UL << BPROT_CONFIG3_REGION113_Pos) /*!< Bit mask of REGION113 field. */ +#define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 16 : Enable protection for region 112. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION112_Pos (16UL) /*!< Position of REGION112 field. */ +#define BPROT_CONFIG3_REGION112_Msk (0x1UL << BPROT_CONFIG3_REGION112_Pos) /*!< Bit mask of REGION112 field. */ +#define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 15 : Enable protection for region 111. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION111_Pos (15UL) /*!< Position of REGION111 field. */ +#define BPROT_CONFIG3_REGION111_Msk (0x1UL << BPROT_CONFIG3_REGION111_Pos) /*!< Bit mask of REGION111 field. */ +#define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 14 : Enable protection for region 110. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION110_Pos (14UL) /*!< Position of REGION110 field. */ +#define BPROT_CONFIG3_REGION110_Msk (0x1UL << BPROT_CONFIG3_REGION110_Pos) /*!< Bit mask of REGION110 field. */ +#define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 13 : Enable protection for region 109. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION109_Pos (13UL) /*!< Position of REGION109 field. */ +#define BPROT_CONFIG3_REGION109_Msk (0x1UL << BPROT_CONFIG3_REGION109_Pos) /*!< Bit mask of REGION109 field. */ +#define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 12 : Enable protection for region 108. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION108_Pos (12UL) /*!< Position of REGION108 field. */ +#define BPROT_CONFIG3_REGION108_Msk (0x1UL << BPROT_CONFIG3_REGION108_Pos) /*!< Bit mask of REGION108 field. */ +#define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 11 : Enable protection for region 107. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION107_Pos (11UL) /*!< Position of REGION107 field. */ +#define BPROT_CONFIG3_REGION107_Msk (0x1UL << BPROT_CONFIG3_REGION107_Pos) /*!< Bit mask of REGION107 field. */ +#define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 10 : Enable protection for region 106. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION106_Pos (10UL) /*!< Position of REGION106 field. */ +#define BPROT_CONFIG3_REGION106_Msk (0x1UL << BPROT_CONFIG3_REGION106_Pos) /*!< Bit mask of REGION106 field. */ +#define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 9 : Enable protection for region 105. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION105_Pos (9UL) /*!< Position of REGION105 field. */ +#define BPROT_CONFIG3_REGION105_Msk (0x1UL << BPROT_CONFIG3_REGION105_Pos) /*!< Bit mask of REGION105 field. */ +#define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 8 : Enable protection for region 104. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION104_Pos (8UL) /*!< Position of REGION104 field. */ +#define BPROT_CONFIG3_REGION104_Msk (0x1UL << BPROT_CONFIG3_REGION104_Pos) /*!< Bit mask of REGION104 field. */ +#define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 7 : Enable protection for region 103. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION103_Pos (7UL) /*!< Position of REGION103 field. */ +#define BPROT_CONFIG3_REGION103_Msk (0x1UL << BPROT_CONFIG3_REGION103_Pos) /*!< Bit mask of REGION103 field. */ +#define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 6 : Enable protection for region 102. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION102_Pos (6UL) /*!< Position of REGION102 field. */ +#define BPROT_CONFIG3_REGION102_Msk (0x1UL << BPROT_CONFIG3_REGION102_Pos) /*!< Bit mask of REGION102 field. */ +#define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 5 : Enable protection for region 101. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION101_Pos (5UL) /*!< Position of REGION101 field. */ +#define BPROT_CONFIG3_REGION101_Msk (0x1UL << BPROT_CONFIG3_REGION101_Pos) /*!< Bit mask of REGION101 field. */ +#define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 4 : Enable protection for region 100. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION100_Pos (4UL) /*!< Position of REGION100 field. */ +#define BPROT_CONFIG3_REGION100_Msk (0x1UL << BPROT_CONFIG3_REGION100_Pos) /*!< Bit mask of REGION100 field. */ +#define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 3 : Enable protection for region 99. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION99_Pos (3UL) /*!< Position of REGION99 field. */ +#define BPROT_CONFIG3_REGION99_Msk (0x1UL << BPROT_CONFIG3_REGION99_Pos) /*!< Bit mask of REGION99 field. */ +#define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 2 : Enable protection for region 98. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */ +#define BPROT_CONFIG3_REGION98_Msk (0x1UL << BPROT_CONFIG3_REGION98_Pos) /*!< Bit mask of REGION98 field. */ +#define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 1 : Enable protection for region 97. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */ +#define BPROT_CONFIG3_REGION97_Msk (0x1UL << BPROT_CONFIG3_REGION97_Pos) /*!< Bit mask of REGION97 field. */ +#define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 0 : Enable protection for region 96. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION96_Pos (0UL) /*!< Position of REGION96 field. */ +#define BPROT_CONFIG3_REGION96_Msk (0x1UL << BPROT_CONFIG3_REGION96_Pos) /*!< Bit mask of REGION96 field. */ +#define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */ + + +/* Peripheral: CCM */ +/* Description: AES CCM Mode Encryption */ + +/* Register: CCM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: CCM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to Enable interrupt for ERROR event */ +#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */ +#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */ +#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */ + +/* Register: CCM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to Disable interrupt for ERROR event */ +#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */ +#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */ +#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */ + +/* Register: CCM_MICSTATUS */ +/* Description: MIC check result */ + +/* Bit 0 : The result of the MIC check performed during the previous decryption operation */ +#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */ +#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */ + +/* Register: CCM_ENABLE */ +/* Description: Enable */ + +/* Bits 1..0 : Enable or disable CCM */ +#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ + +/* Register: CCM_MODE */ +/* Description: Operation mode */ + +/* Bit 24 : Packet length configuration */ +#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ +#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ +#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field is 5-bit */ +#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-bit */ + +/* Bit 16 : Data rate that the CCM shall run in synch with */ +#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ +#define CCM_MODE_DATARATE_Msk (0x1UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ +#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */ +#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */ + +/* Bit 0 : The mode of operation to be used */ +#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */ +#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */ + +/* Register: CCM_CNFPTR */ +/* Description: Pointer to data structure holding AES key and NONCE vector */ + +/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */ +#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */ +#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */ + +/* Register: CCM_INPTR */ +/* Description: Input pointer */ + +/* Bits 31..0 : Input pointer */ +#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */ +#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */ + +/* Register: CCM_OUTPTR */ +/* Description: Output pointer */ + +/* Bits 31..0 : Output pointer */ +#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */ +#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */ + +/* Register: CCM_SCRATCHPTR */ +/* Description: Pointer to data area used for temporary storage */ + +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */ +#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ +#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ + + +/* Peripheral: CLOCK */ +/* Description: Clock control */ + +/* Register: CLOCK_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 4 : Write '1' to Enable interrupt for CTTO event */ +#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for DONE event */ +#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */ +#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */ +#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Register: CLOCK_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 4 : Write '1' to Disable interrupt for CTTO event */ +#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for DONE event */ +#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Register: CLOCK_HFCLKRUN */ +/* Description: Status indicating that HFCLKSTART task has been triggered */ + +/* Bit 0 : HFCLKSTART task triggered or not */ +#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_HFCLKSTAT */ +/* Description: HFCLK status */ + +/* Bit 16 : HFCLK state */ +#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */ +#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */ + +/* Bit 0 : Source of HFCLK */ +#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */ +#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */ + +/* Register: CLOCK_LFCLKRUN */ +/* Description: Status indicating that LFCLKSTART task has been triggered */ + +/* Bit 0 : LFCLKSTART task triggered or not */ +#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_LFCLKSTAT */ +/* Description: LFCLK status */ + +/* Bit 16 : LFCLK state */ +#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */ +#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */ + +/* Bits 1..0 : Source of LFCLK */ +#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ + +/* Register: CLOCK_LFCLKSRCCOPY */ +/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ + +/* Register: CLOCK_LFCLKSRC */ +/* Description: Clock source for the LFCLK */ + +/* Bit 17 : Enable or disable external source for LFCLK */ +#define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */ +#define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */ + +/* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */ +#define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */ +#define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ + +/* Register: CLOCK_CTIV */ +/* Description: Calibration timer interval */ + +/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */ +#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ +#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ + +/* Register: CLOCK_TRACECONFIG */ +/* Description: Clocking options for the Trace Port debug interface */ + +/* Bits 17..16 : Pin multiplexing of trace signals. */ +#define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */ +#define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */ +#define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */ +#define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */ +#define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */ + +/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */ + + +/* Peripheral: COMP */ +/* Description: Comparator */ + +/* Register: COMP_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between CROSS event and STOP task */ +#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ +#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ +#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between UP event and STOP task */ +#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ +#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ +#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between DOWN event and STOP task */ +#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ +#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ +#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between READY event and STOP task */ +#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ +#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ +#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between READY event and SAMPLE task */ +#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ +#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ +#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: COMP_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 3 : Enable or disable interrupt for CROSS event */ +#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for UP event */ +#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for DOWN event */ +#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for READY event */ +#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */ + +/* Register: COMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 3 : Write '1' to Enable interrupt for CROSS event */ +#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for UP event */ +#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for DOWN event */ +#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for READY event */ +#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: COMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 3 : Write '1' to Disable interrupt for CROSS event */ +#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for UP event */ +#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for DOWN event */ +#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for READY event */ +#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: COMP_RESULT */ +/* Description: Compare result */ + +/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ +#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ +#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ < VIN-) */ +#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ > VIN-) */ + +/* Register: COMP_ENABLE */ +/* Description: COMP enable */ + +/* Bits 1..0 : Enable or disable COMP */ +#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ + +/* Register: COMP_PSEL */ +/* Description: Pin select */ + +/* Bits 2..0 : Analog pin select */ +#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ +#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */ + +/* Register: COMP_REFSEL */ +/* Description: Reference source select for single-ended mode */ + +/* Bits 2..0 : Reference select */ +#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ +#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V) */ +#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) */ +#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) */ +#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */ +#define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD >= VREF >= AREFMIN) */ + +/* Register: COMP_EXTREFSEL */ +/* Description: External reference select */ + +/* Bits 2..0 : External analog reference select */ +#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (4UL) /*!< Use AIN4 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (5UL) /*!< Use AIN5 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (6UL) /*!< Use AIN6 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (7UL) /*!< Use AIN7 as external analog reference */ + +/* Register: COMP_TH */ +/* Description: Threshold configuration for hysteresis unit */ + +/* Bits 13..8 : VUP = (THUP+1)/64*VREF */ +#define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */ +#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */ + +/* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */ +#define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */ +#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */ + +/* Register: COMP_MODE */ +/* Description: Mode configuration */ + +/* Bit 8 : Main operation modes */ +#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ +#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ +#define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */ +#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */ + +/* Bits 1..0 : Speed and power modes */ +#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ +#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ +#define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */ +#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */ +#define COMP_MODE_SP_High (2UL) /*!< High-speed mode */ + +/* Register: COMP_HYST */ +/* Description: Comparator hysteresis enable */ + +/* Bit 0 : Comparator hysteresis */ +#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ +#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ +#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ +#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */ + +/* Register: COMP_ISOURCE */ +/* Description: Current source select on analog input */ + +/* Bits 1..0 : Comparator hysteresis */ +#define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */ +#define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */ +#define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */ +#define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */ +#define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */ +#define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */ + + +/* Peripheral: ECB */ +/* Description: AES ECB Mode Encryption */ + +/* Register: ECB_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */ +#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for ENDECB event */ +#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */ + +/* Register: ECB_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */ +#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for ENDECB event */ +#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */ + +/* Register: ECB_ECBDATAPTR */ +/* Description: ECB block encrypt memory pointers */ + +/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */ +#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */ +#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */ + + +/* Peripheral: EGU */ +/* Description: Event Generator Unit 0 */ + +/* Register: EGU_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */ +#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */ +#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */ +#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */ +#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */ +#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */ +#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */ +#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */ +#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */ +#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */ +#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */ +#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */ +#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */ +#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */ +#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */ +#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */ +#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */ + +/* Register: EGU_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */ +#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */ +#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */ +#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */ +#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */ +#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */ +#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */ +#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */ +#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */ +#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */ +#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */ +#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */ +#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */ +#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */ +#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */ +#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */ +#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */ + +/* Register: EGU_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */ +#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */ +#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */ +#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */ +#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */ +#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */ +#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */ +#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */ +#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */ +#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */ +#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */ +#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */ +#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */ +#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */ +#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */ +#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */ +#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */ + + +/* Peripheral: FICR */ +/* Description: Factory Information Configuration Registers */ + +/* Register: FICR_CODEPAGESIZE */ +/* Description: Code memory page size */ + +/* Bits 31..0 : Code memory page size */ +#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */ +#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */ + +/* Register: FICR_CODESIZE */ +/* Description: Code memory size */ + +/* Bits 31..0 : Code memory size in number of pages */ +#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */ +#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ + +/* Register: FICR_DEVICEID */ +/* Description: Description collection[0]: Device identifier */ + +/* Bits 31..0 : 64 bit unique device identifier */ +#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ +#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ + +/* Register: FICR_ER */ +/* Description: Description collection[0]: Encryption Root, word 0 */ + +/* Bits 31..0 : Encryption Root, word n */ +#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */ +#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */ + +/* Register: FICR_IR */ +/* Description: Description collection[0]: Identity Root, word 0 */ + +/* Bits 31..0 : Identity Root, word n */ +#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */ +#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */ + +/* Register: FICR_DEVICEADDRTYPE */ +/* Description: Device address type */ + +/* Bit 0 : Device address type */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */ + +/* Register: FICR_DEVICEADDR */ +/* Description: Description collection[0]: Device address 0 */ + +/* Bits 31..0 : 48 bit device address */ +#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */ +#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */ + +/* Register: FICR_INFO_PART */ +/* Description: Part code */ + +/* Bits 31..0 : Part code */ +#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ +#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ +#define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */ +#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_VARIANT */ +/* Description: Part Variant, Hardware version and Production configuration */ + +/* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */ +#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ +#define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */ +#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */ +#define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */ +#define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */ +#define FICR_INFO_VARIANT_VARIANT_AAE0 (0x41414530UL) /*!< AAE0 */ +#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_PACKAGE */ +/* Description: Package option */ + +/* Bits 31..0 : Package option */ +#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */ +#define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_CI (0x2002UL) /*!< CIxx - 7x8 WLCSP 56 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_CK (0x2005UL) /*!< CKxx - 7x8 WLCSP 56 balls with backside coating for light protection */ +#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_RAM */ +/* Description: RAM variant */ + +/* Bits 31..0 : RAM variant */ +#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ +#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ +#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */ +#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */ +#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */ +#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_FLASH */ +/* Description: Flash variant */ + +/* Bits 31..0 : Flash variant */ +#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_TEMP_A0 */ +/* Description: Slope definition A0. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A1 */ +/* Description: Slope definition A1. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A2 */ +/* Description: Slope definition A2. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A3 */ +/* Description: Slope definition A3. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A4 */ +/* Description: Slope definition A4. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A5 */ +/* Description: Slope definition A5. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_B0 */ +/* Description: y-intercept B0. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B1 */ +/* Description: y-intercept B1. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B2 */ +/* Description: y-intercept B2. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B3 */ +/* Description: y-intercept B3. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B4 */ +/* Description: y-intercept B4. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B5 */ +/* Description: y-intercept B5. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_T0 */ +/* Description: Segment end T0. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T1 */ +/* Description: Segment end T1. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T2 */ +/* Description: Segment end T2. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T3 */ +/* Description: Segment end T3. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T4 */ +/* Description: Segment end T4. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_NFC_TAGHEADER0 */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 3 */ +#define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */ +#define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */ + +/* Bits 23..16 : Unique identifier byte 2 */ +#define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */ +#define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */ + +/* Bits 15..8 : Unique identifier byte 1 */ +#define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */ +#define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */ + +/* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */ +#define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */ +#define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */ + +/* Register: FICR_NFC_TAGHEADER1 */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 7 */ +#define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */ +#define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */ + +/* Bits 23..16 : Unique identifier byte 6 */ +#define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */ +#define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */ + +/* Bits 15..8 : Unique identifier byte 5 */ +#define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */ +#define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */ + +/* Bits 7..0 : Unique identifier byte 4 */ +#define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */ +#define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */ + +/* Register: FICR_NFC_TAGHEADER2 */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 11 */ +#define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */ +#define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */ + +/* Bits 23..16 : Unique identifier byte 10 */ +#define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */ +#define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */ + +/* Bits 15..8 : Unique identifier byte 9 */ +#define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */ +#define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */ + +/* Bits 7..0 : Unique identifier byte 8 */ +#define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */ +#define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */ + +/* Register: FICR_NFC_TAGHEADER3 */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 15 */ +#define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */ +#define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */ + +/* Bits 23..16 : Unique identifier byte 14 */ +#define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */ +#define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */ + +/* Bits 15..8 : Unique identifier byte 13 */ +#define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */ +#define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */ + +/* Bits 7..0 : Unique identifier byte 12 */ +#define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */ +#define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */ + + +/* Peripheral: GPIOTE */ +/* Description: GPIO Tasks and Events */ + +/* Register: GPIOTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 31 : Write '1' to Enable interrupt for PORT event */ +#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for IN[7] event */ +#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for IN[6] event */ +#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for IN[5] event */ +#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for IN[4] event */ +#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for IN[3] event */ +#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for IN[2] event */ +#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for IN[1] event */ +#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for IN[0] event */ +#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */ + +/* Register: GPIOTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 31 : Write '1' to Disable interrupt for PORT event */ +#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for IN[7] event */ +#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for IN[6] event */ +#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for IN[5] event */ +#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for IN[4] event */ +#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for IN[3] event */ +#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for IN[2] event */ +#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for IN[1] event */ +#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for IN[0] event */ +#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ + +/* Register: GPIOTE_CONFIG */ +/* Description: Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ + +/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ +#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */ +#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */ + +/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */ +#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */ +#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ + +/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */ +#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ +#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ + +/* Bits 1..0 : Mode */ +#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */ +#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */ +#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */ + + +/* Peripheral: I2S */ +/* Description: Inter-IC Sound */ + +/* Register: I2S_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 5 : Enable or disable interrupt for TXPTRUPD event */ +#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for STOPPED event */ +#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for RXPTRUPD event */ +#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */ + +/* Register: I2S_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */ +#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for STOPPED event */ +#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */ +#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */ + +/* Register: I2S_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */ +#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for STOPPED event */ +#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */ +#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */ + +/* Register: I2S_ENABLE */ +/* Description: Enable I2S module. */ + +/* Bit 0 : Enable I2S module. */ +#define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: I2S_CONFIG_MODE */ +/* Description: I2S mode. */ + +/* Bit 0 : I2S mode. */ +#define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */ +#define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */ + +/* Register: I2S_CONFIG_RXEN */ +/* Description: Reception (RX) enable. */ + +/* Bit 0 : Reception (RX) enable. */ +#define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */ +#define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */ +#define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */ +#define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */ + +/* Register: I2S_CONFIG_TXEN */ +/* Description: Transmission (TX) enable. */ + +/* Bit 0 : Transmission (TX) enable. */ +#define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */ +#define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */ +#define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */ +#define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */ + +/* Register: I2S_CONFIG_MCKEN */ +/* Description: Master clock generator enable. */ + +/* Bit 0 : Master clock generator enable. */ +#define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */ +#define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */ +#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */ +#define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */ + +/* Register: I2S_CONFIG_MCKFREQ */ +/* Description: Master clock generator frequency. */ + +/* Bits 31..0 : Master clock generator frequency. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */ + +/* Register: I2S_CONFIG_RATIO */ +/* Description: MCK / LRCK ratio. */ + +/* Bits 3..0 : MCK / LRCK ratio. */ +#define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ +#define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ +#define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */ +#define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */ +#define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */ +#define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */ +#define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */ +#define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */ +#define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */ +#define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */ +#define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */ + +/* Register: I2S_CONFIG_SWIDTH */ +/* Description: Sample width. */ + +/* Bits 1..0 : Sample width. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */ + +/* Register: I2S_CONFIG_ALIGN */ +/* Description: Alignment of sample within a frame. */ + +/* Bit 0 : Alignment of sample within a frame. */ +#define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */ +#define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */ +#define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */ +#define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */ + +/* Register: I2S_CONFIG_FORMAT */ +/* Description: Frame format. */ + +/* Bit 0 : Frame format. */ +#define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */ +#define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */ +#define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */ +#define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */ + +/* Register: I2S_CONFIG_CHANNELS */ +/* Description: Enable channels. */ + +/* Bits 1..0 : Enable channels. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */ + +/* Register: I2S_RXD_PTR */ +/* Description: Receive buffer RAM start address. */ + +/* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */ +#define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: I2S_TXD_PTR */ +/* Description: Transmit buffer RAM start address. */ + +/* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */ +#define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: I2S_RXTXD_MAXCNT */ +/* Description: Size of RXD and TXD buffers. */ + +/* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */ +#define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: I2S_PSEL_MCK */ +/* Description: Pin select for MCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SCK */ +/* Description: Pin select for SCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_LRCK */ +/* Description: Pin select for LRCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SDIN */ +/* Description: Pin select for SDIN signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SDOUT */ +/* Description: Pin select for SDOUT signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */ + + +/* Peripheral: LPCOMP */ +/* Description: Low Power Comparator */ + +/* Register: LPCOMP_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between CROSS event and STOP task */ +#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ +#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ +#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between UP event and STOP task */ +#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ +#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ +#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between DOWN event and STOP task */ +#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ +#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ +#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between READY event and STOP task */ +#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ +#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ +#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between READY event and SAMPLE task */ +#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: LPCOMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 3 : Write '1' to Enable interrupt for CROSS event */ +#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for UP event */ +#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ +#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ +#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for DOWN event */ +#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for READY event */ +#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: LPCOMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 3 : Write '1' to Disable interrupt for CROSS event */ +#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for UP event */ +#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ +#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ +#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for DOWN event */ +#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for READY event */ +#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: LPCOMP_RESULT */ +/* Description: Compare result */ + +/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ +#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ +#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */ +#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-). */ + +/* Register: LPCOMP_ENABLE */ +/* Description: Enable LPCOMP */ + +/* Bits 1..0 : Enable or disable LPCOMP */ +#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: LPCOMP_PSEL */ +/* Description: Input pin select */ + +/* Bits 2..0 : Analog pin select */ +#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ +#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */ + +/* Register: LPCOMP_REFSEL */ +/* Description: Reference select */ + +/* Bits 3..0 : Reference select */ +#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ +#define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */ +#define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */ + +/* Register: LPCOMP_EXTREFSEL */ +/* Description: External reference select */ + +/* Bit 0 : External analog reference select */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ + +/* Register: LPCOMP_ANADETECT */ +/* Description: Analog detect configuration */ + +/* Bits 1..0 : Analog detect configuration */ +#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */ +#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */ +#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */ +#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */ +#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */ + +/* Register: LPCOMP_HYST */ +/* Description: Comparator hysteresis enable */ + +/* Bit 0 : Comparator hysteresis enable */ +#define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ +#define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ +#define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ +#define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */ + + +/* Peripheral: MWU */ +/* Description: Memory Watch Unit */ + +/* Register: MWU_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */ +#define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */ +#define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */ +#define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */ +#define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for REGION[3].RA event */ +#define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for REGION[3].WA event */ +#define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for REGION[2].RA event */ +#define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for REGION[2].WA event */ +#define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for REGION[1].RA event */ +#define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for REGION[1].WA event */ +#define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for REGION[0].RA event */ +#define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for REGION[0].WA event */ +#define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */ + +/* Register: MWU_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */ +#define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */ +#define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */ +#define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */ +#define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */ +#define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */ +#define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */ +#define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */ +#define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */ +#define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */ +#define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */ +#define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */ +#define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */ + +/* Register: MWU_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */ +#define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */ +#define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */ +#define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */ +#define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */ +#define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */ +#define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */ +#define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */ +#define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */ +#define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */ +#define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */ +#define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */ +#define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */ + +/* Register: MWU_NMIEN */ +/* Description: Enable or disable non-maskable interrupt */ + +/* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */ +#define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */ +#define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */ +#define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */ +#define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */ +#define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */ +#define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */ +#define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */ +#define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */ +#define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */ +#define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */ +#define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */ +#define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */ + +/* Register: MWU_NMIENSET */ +/* Description: Enable non-maskable interrupt */ + +/* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */ +#define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */ +#define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */ +#define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */ +#define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */ +#define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */ +#define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */ +#define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */ +#define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */ +#define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */ +#define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */ +#define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */ +#define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */ + +/* Register: MWU_NMIENCLR */ +/* Description: Disable non-maskable interrupt */ + +/* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */ +#define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */ +#define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */ +#define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */ +#define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */ +#define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */ +#define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */ +#define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */ +#define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */ +#define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */ +#define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */ +#define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */ +#define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */ + +/* Register: MWU_PERREGION_SUBSTATWA */ +/* Description: Description cluster[0]: Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */ + +/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */ +#define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */ +#define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */ +#define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */ +#define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */ +#define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */ +#define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */ +#define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */ +#define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */ +#define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */ +#define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */ +#define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */ +#define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */ +#define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */ +#define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */ +#define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */ +#define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */ +#define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */ +#define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */ +#define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */ +#define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */ +#define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */ +#define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */ +#define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */ +#define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */ +#define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */ +#define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */ +#define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */ +#define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */ +#define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */ +#define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */ +#define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */ +#define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */ +#define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */ +#define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */ +#define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */ +#define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */ +#define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */ +#define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */ +#define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */ +#define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */ +#define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */ +#define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */ +#define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */ +#define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */ +#define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */ +#define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */ +#define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */ +#define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */ +#define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */ +#define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */ +#define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */ +#define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */ +#define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */ +#define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */ +#define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */ +#define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */ +#define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */ +#define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */ +#define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */ +#define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */ +#define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */ +#define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */ +#define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */ +#define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Register: MWU_PERREGION_SUBSTATRA */ +/* Description: Description cluster[0]: Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */ + +/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */ +#define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */ +#define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */ +#define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */ +#define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */ +#define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */ +#define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */ +#define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */ +#define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */ +#define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */ +#define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */ +#define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */ +#define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */ +#define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */ +#define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */ +#define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */ +#define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */ +#define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */ +#define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */ +#define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */ +#define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */ +#define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */ +#define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */ +#define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */ +#define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */ +#define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */ +#define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */ +#define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */ +#define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */ +#define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */ +#define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */ +#define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */ +#define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */ +#define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */ +#define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */ +#define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */ +#define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */ +#define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */ +#define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */ +#define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */ +#define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */ +#define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */ +#define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */ +#define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */ +#define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */ +#define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */ +#define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */ +#define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */ +#define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */ +#define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */ +#define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */ +#define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */ +#define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */ +#define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */ +#define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */ +#define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */ +#define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */ +#define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */ +#define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */ +#define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */ +#define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */ +#define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */ +#define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */ +#define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */ +#define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Register: MWU_REGIONEN */ +/* Description: Enable/disable regions watch */ + +/* Bit 27 : Enable/disable read access watch in PREGION[1] */ +#define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ +#define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ +#define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */ +#define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 26 : Enable/disable write access watch in PREGION[1] */ +#define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ +#define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ +#define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */ +#define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 25 : Enable/disable read access watch in PREGION[0] */ +#define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ +#define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ +#define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */ +#define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 24 : Enable/disable write access watch in PREGION[0] */ +#define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ +#define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ +#define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */ +#define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 7 : Enable/disable read access watch in region[3] */ +#define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ +#define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ +#define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 6 : Enable/disable write access watch in region[3] */ +#define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ +#define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ +#define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Bit 5 : Enable/disable read access watch in region[2] */ +#define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ +#define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ +#define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 4 : Enable/disable write access watch in region[2] */ +#define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ +#define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ +#define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Bit 3 : Enable/disable read access watch in region[1] */ +#define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ +#define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ +#define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 2 : Enable/disable write access watch in region[1] */ +#define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ +#define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ +#define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Bit 1 : Enable/disable read access watch in region[0] */ +#define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ +#define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ +#define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 0 : Enable/disable write access watch in region[0] */ +#define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ +#define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ +#define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Register: MWU_REGIONENSET */ +/* Description: Enable regions watch */ + +/* Bit 27 : Enable read access watch in PREGION[1] */ +#define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ +#define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ +#define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 26 : Enable write access watch in PREGION[1] */ +#define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ +#define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ +#define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 25 : Enable read access watch in PREGION[0] */ +#define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ +#define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ +#define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 24 : Enable write access watch in PREGION[0] */ +#define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ +#define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ +#define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 7 : Enable read access watch in region[3] */ +#define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ +#define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ +#define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 6 : Enable write access watch in region[3] */ +#define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ +#define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ +#define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Bit 5 : Enable read access watch in region[2] */ +#define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ +#define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ +#define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 4 : Enable write access watch in region[2] */ +#define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ +#define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ +#define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Bit 3 : Enable read access watch in region[1] */ +#define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ +#define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ +#define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 2 : Enable write access watch in region[1] */ +#define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ +#define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ +#define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Bit 1 : Enable read access watch in region[0] */ +#define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ +#define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ +#define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 0 : Enable write access watch in region[0] */ +#define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ +#define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ +#define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Register: MWU_REGIONENCLR */ +/* Description: Disable regions watch */ + +/* Bit 27 : Disable read access watch in PREGION[1] */ +#define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ +#define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ +#define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */ + +/* Bit 26 : Disable write access watch in PREGION[1] */ +#define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ +#define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ +#define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */ + +/* Bit 25 : Disable read access watch in PREGION[0] */ +#define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ +#define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ +#define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */ + +/* Bit 24 : Disable write access watch in PREGION[0] */ +#define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ +#define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ +#define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */ + +/* Bit 7 : Disable read access watch in region[3] */ +#define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ +#define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ +#define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 6 : Disable write access watch in region[3] */ +#define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ +#define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ +#define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Bit 5 : Disable read access watch in region[2] */ +#define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ +#define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ +#define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 4 : Disable write access watch in region[2] */ +#define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ +#define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ +#define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Bit 3 : Disable read access watch in region[1] */ +#define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ +#define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ +#define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 2 : Disable write access watch in region[1] */ +#define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ +#define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ +#define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Bit 1 : Disable read access watch in region[0] */ +#define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ +#define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ +#define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 0 : Disable write access watch in region[0] */ +#define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ +#define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ +#define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Register: MWU_REGION_START */ +/* Description: Description cluster[0]: Start address for region 0 */ + +/* Bits 31..0 : Start address for region */ +#define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */ +#define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */ + +/* Register: MWU_REGION_END */ +/* Description: Description cluster[0]: End address of region 0 */ + +/* Bits 31..0 : End address of region. */ +#define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */ +#define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */ + +/* Register: MWU_PREGION_START */ +/* Description: Description cluster[0]: Reserved for future use */ + +/* Bits 31..0 : Reserved for future use */ +#define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */ +#define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */ + +/* Register: MWU_PREGION_END */ +/* Description: Description cluster[0]: Reserved for future use */ + +/* Bits 31..0 : Reserved for future use */ +#define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */ +#define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */ + +/* Register: MWU_PREGION_SUBS */ +/* Description: Description cluster[0]: Subregions of region 0 */ + +/* Bit 31 : Include or exclude subregion 31 in region */ +#define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */ +#define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */ +#define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */ + +/* Bit 30 : Include or exclude subregion 30 in region */ +#define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */ +#define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */ +#define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */ + +/* Bit 29 : Include or exclude subregion 29 in region */ +#define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */ +#define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */ +#define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */ + +/* Bit 28 : Include or exclude subregion 28 in region */ +#define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */ +#define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */ +#define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */ + +/* Bit 27 : Include or exclude subregion 27 in region */ +#define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */ +#define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */ +#define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */ + +/* Bit 26 : Include or exclude subregion 26 in region */ +#define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */ +#define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */ +#define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */ + +/* Bit 25 : Include or exclude subregion 25 in region */ +#define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */ +#define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */ +#define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */ + +/* Bit 24 : Include or exclude subregion 24 in region */ +#define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */ +#define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */ +#define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */ + +/* Bit 23 : Include or exclude subregion 23 in region */ +#define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */ +#define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */ +#define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */ + +/* Bit 22 : Include or exclude subregion 22 in region */ +#define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */ +#define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */ +#define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */ + +/* Bit 21 : Include or exclude subregion 21 in region */ +#define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */ +#define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */ +#define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */ + +/* Bit 20 : Include or exclude subregion 20 in region */ +#define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */ +#define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */ +#define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */ + +/* Bit 19 : Include or exclude subregion 19 in region */ +#define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */ +#define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */ +#define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */ + +/* Bit 18 : Include or exclude subregion 18 in region */ +#define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */ +#define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */ +#define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */ + +/* Bit 17 : Include or exclude subregion 17 in region */ +#define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */ +#define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */ +#define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */ + +/* Bit 16 : Include or exclude subregion 16 in region */ +#define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */ +#define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */ +#define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */ + +/* Bit 15 : Include or exclude subregion 15 in region */ +#define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */ +#define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */ +#define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */ + +/* Bit 14 : Include or exclude subregion 14 in region */ +#define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */ +#define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */ +#define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */ + +/* Bit 13 : Include or exclude subregion 13 in region */ +#define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */ +#define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */ +#define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */ + +/* Bit 12 : Include or exclude subregion 12 in region */ +#define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */ +#define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */ +#define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */ + +/* Bit 11 : Include or exclude subregion 11 in region */ +#define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */ +#define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */ +#define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */ + +/* Bit 10 : Include or exclude subregion 10 in region */ +#define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */ +#define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */ +#define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */ + +/* Bit 9 : Include or exclude subregion 9 in region */ +#define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */ +#define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */ +#define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */ + +/* Bit 8 : Include or exclude subregion 8 in region */ +#define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */ +#define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */ +#define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */ + +/* Bit 7 : Include or exclude subregion 7 in region */ +#define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */ +#define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */ +#define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */ + +/* Bit 6 : Include or exclude subregion 6 in region */ +#define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */ +#define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */ +#define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */ + +/* Bit 5 : Include or exclude subregion 5 in region */ +#define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */ +#define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */ +#define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */ + +/* Bit 4 : Include or exclude subregion 4 in region */ +#define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */ +#define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */ +#define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */ + +/* Bit 3 : Include or exclude subregion 3 in region */ +#define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */ +#define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */ +#define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */ + +/* Bit 2 : Include or exclude subregion 2 in region */ +#define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */ +#define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */ +#define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */ + +/* Bit 1 : Include or exclude subregion 1 in region */ +#define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */ +#define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */ +#define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */ + +/* Bit 0 : Include or exclude subregion 0 in region */ +#define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */ +#define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */ +#define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */ + + +/* Peripheral: NFCT */ +/* Description: NFC-A compatible radio */ + +/* Register: NFCT_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 1 : Shortcut between FIELDLOST event and SENSE task */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: NFCT_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 20 : Enable or disable interrupt for STARTED event */ +#define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */ +#define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for SELECTED event */ +#define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ +#define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for COLLISION event */ +#define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ +#define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ +#define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for ENDTX event */ +#define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ +#define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for ENDRX event */ +#define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ +#define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for RXERROR event */ +#define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ +#define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ +#define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for ERROR event */ +#define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */ +#define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */ +#define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ +#define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ +#define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */ +#define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ +#define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ +#define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */ +#define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ +#define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ +#define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */ +#define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ +#define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ +#define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for FIELDLOST event */ +#define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ +#define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ +#define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */ +#define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ +#define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ +#define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for READY event */ +#define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ +#define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */ +#define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */ + +/* Register: NFCT_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 20 : Write '1' to Enable interrupt for STARTED event */ +#define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */ +#define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for SELECTED event */ +#define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ +#define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for COLLISION event */ +#define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ +#define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ +#define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to Enable interrupt for ENDTX event */ +#define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ +#define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to Enable interrupt for ENDRX event */ +#define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ +#define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to Enable interrupt for RXERROR event */ +#define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ +#define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ +#define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for ERROR event */ +#define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */ +#define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */ +#define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ +#define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ +#define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */ +#define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ +#define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ +#define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */ +#define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ +#define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ +#define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */ +#define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ +#define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ +#define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */ +#define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ +#define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ +#define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */ +#define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ +#define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ +#define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for READY event */ +#define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: NFCT_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 20 : Write '1' to Disable interrupt for STARTED event */ +#define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */ +#define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for SELECTED event */ +#define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ +#define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for COLLISION event */ +#define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ +#define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ +#define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to Disable interrupt for ENDTX event */ +#define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ +#define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to Disable interrupt for ENDRX event */ +#define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ +#define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to Disable interrupt for RXERROR event */ +#define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ +#define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ +#define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for ERROR event */ +#define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */ +#define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */ +#define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ +#define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ +#define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */ +#define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ +#define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ +#define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */ +#define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ +#define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ +#define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */ +#define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ +#define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ +#define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */ +#define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ +#define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ +#define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */ +#define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ +#define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ +#define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for READY event */ +#define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: NFCT_ERRORSTATUS */ +/* Description: NFC Error Status register */ + +/* Bit 3 : Field level is too low at min load resistance */ +#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos (3UL) /*!< Position of NFCFIELDTOOWEAK field. */ +#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos) /*!< Bit mask of NFCFIELDTOOWEAK field. */ + +/* Bit 2 : Field level is too high at max load resistance */ +#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos (2UL) /*!< Position of NFCFIELDTOOSTRONG field. */ +#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos) /*!< Bit mask of NFCFIELDTOOSTRONG field. */ + +/* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */ +#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */ +#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */ + +/* Register: NFCT_FRAMESTATUS_RX */ +/* Description: Result of last incoming frames */ + +/* Bit 3 : Overrun detected */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */ + +/* Bit 2 : Parity status of received frame */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */ + +/* Bit 0 : No valid End of Frame detected */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */ + +/* Register: NFCT_CURRENTLOADCTRL */ +/* Description: Current value driven to the NFC Load Control */ + +/* Bits 5..0 : Current value driven to the NFC Load Control */ +#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos (0UL) /*!< Position of CURRENTLOADCTRL field. */ +#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos) /*!< Bit mask of CURRENTLOADCTRL field. */ + +/* Register: NFCT_FIELDPRESENT */ +/* Description: Indicates the presence or not of a valid field */ + +/* Bit 1 : Indicates if the low level has locked to the field */ +#define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */ +#define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */ +#define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */ +#define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */ + +/* Bit 0 : Indicates the presence or not of a valid field. Available only in the activated state. */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */ + +/* Register: NFCT_FRAMEDELAYMIN */ +/* Description: Minimum frame delay */ + +/* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */ +#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */ +#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */ + +/* Register: NFCT_FRAMEDELAYMAX */ +/* Description: Maximum frame delay */ + +/* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */ +#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */ +#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */ + +/* Register: NFCT_FRAMEDELAYMODE */ +/* Description: Configuration register for the Frame Delay Timer */ + +/* Bits 1..0 : Configuration register for the Frame Delay Timer */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */ + +/* Register: NFCT_PACKETPTR */ +/* Description: Packet pointer for TXD and RXD data storage in Data RAM */ + +/* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. */ +#define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: NFCT_MAXLEN */ +/* Description: Size of allocated for TXD and RXD data storage buffer in Data RAM */ + +/* Bits 8..0 : Size of allocated for TXD and RXD data storage buffer in Data RAM */ +#define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ +#define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + +/* Register: NFCT_TXD_FRAMECONFIG */ +/* Description: Configuration of outgoing frames */ + +/* Bit 4 : CRC mode for outgoing frames */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */ + +/* Bit 2 : Adding SoF or not in TX frames */ +#define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */ +#define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */ +#define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol not added */ +#define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol added */ + +/* Bit 1 : Discarding unused bits in start or at end of a Frame */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits is discarded at end of frame */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits is discarded at start of frame */ + +/* Bit 0 : Adding parity or not in the frame */ +#define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */ +#define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added in TX frames */ +#define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added TX frames */ + +/* Register: NFCT_TXD_AMOUNT */ +/* Description: Size of outgoing frame */ + +/* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */ +#define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */ +#define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */ + +/* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */ +#define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */ +#define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */ + +/* Register: NFCT_RXD_FRAMECONFIG */ +/* Description: Configuration of incoming frames */ + +/* Bit 4 : CRC mode for incoming frames */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */ + +/* Bit 2 : SoF expected or not in RX frames */ +#define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */ +#define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */ +#define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol is not expected in RX frames */ +#define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol is expected in RX frames */ + +/* Bit 0 : Parity expected or not in RX frame */ +#define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */ +#define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */ +#define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */ + +/* Register: NFCT_RXD_AMOUNT */ +/* Description: Size of last incoming frame */ + +/* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */ +#define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */ +#define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */ + +/* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */ +#define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */ +#define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */ + +/* Register: NFCT_NFCID1_LAST */ +/* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */ + +/* Bits 31..24 : NFCID1 byte W */ +#define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */ +#define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */ + +/* Bits 23..16 : NFCID1 byte X */ +#define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */ +#define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */ + +/* Bits 15..8 : NFCID1 byte Y */ +#define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */ +#define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */ + +/* Bits 7..0 : NFCID1 byte Z (very last byte sent) */ +#define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */ +#define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */ + +/* Register: NFCT_NFCID1_2ND_LAST */ +/* Description: Second last NFCID1 part (7 or 10 bytes ID) */ + +/* Bits 23..16 : NFCID1 byte T */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */ + +/* Bits 15..8 : NFCID1 byte U */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */ + +/* Bits 7..0 : NFCID1 byte V */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */ + +/* Register: NFCT_NFCID1_3RD_LAST */ +/* Description: Third last NFCID1 part (10 bytes ID) */ + +/* Bits 23..16 : NFCID1 byte Q */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */ + +/* Bits 15..8 : NFCID1 byte R */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */ + +/* Bits 7..0 : NFCID1 byte S */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */ + +/* Register: NFCT_SENSRES */ +/* Description: NFC-A SENS_RES auto-response settings */ + +/* Bits 15..12 : Reserved for future use. Shall be 0. */ +#define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */ +#define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */ + +/* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +#define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */ +#define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */ + +/* Bits 7..6 : NFCID1 size. This value is used by the Auto collision resolution engine. */ +#define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */ +#define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */ +#define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */ +#define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */ +#define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */ + +/* Bit 5 : Reserved for future use. Shall be 0. */ +#define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */ +#define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */ + +/* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +#define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */ +#define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */ + +/* Register: NFCT_SELRES */ +/* Description: NFC-A SEL_RES auto-response settings */ + +/* Bit 7 : Reserved for future use. Shall be 0. */ +#define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */ +#define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */ + +/* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +#define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */ +#define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */ + +/* Bits 4..3 : Reserved for future use. Shall be 0. */ +#define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */ +#define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */ + +/* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */ +#define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */ +#define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */ +#define NFCT_SELRES_CASCADE_Complete (0UL) /*!< NFCID1 complete */ +#define NFCT_SELRES_CASCADE_NotComplete (1UL) /*!< NFCID1 not complete */ + +/* Bits 1..0 : Reserved for future use. Shall be 0. */ +#define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */ +#define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */ + + +/* Peripheral: NVMC */ +/* Description: Non Volatile Memory Controller */ + +/* Register: NVMC_READY */ +/* Description: Ready flag */ + +/* Bit 0 : NVMC is ready or busy */ +#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ +#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ +#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */ +#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ + +/* Register: NVMC_CONFIG */ +/* Description: Configuration register */ + +/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ +#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ +#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ +#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ +#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */ +#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */ + +/* Register: NVMC_ERASEPAGE */ +/* Description: Register for erasing a page in Code area */ + +/* Bits 31..0 : Register for starting erase of a page in Code area */ +#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */ +#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */ + +/* Register: NVMC_ERASEPCR1 */ +/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ + +/* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ +#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */ +#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */ + +/* Register: NVMC_ERASEALL */ +/* Description: Register for erasing all non-volatile user memory */ + +/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */ +#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ +#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */ + +/* Register: NVMC_ERASEPCR0 */ +/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ + +/* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */ +#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */ +#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */ + +/* Register: NVMC_ERASEUICR */ +/* Description: Register for erasing User Information Configuration Registers */ + +/* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */ +#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */ +#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */ + +/* Register: NVMC_ICACHECNF */ +/* Description: I-Code cache configuration register. */ + +/* Bit 8 : Cache profiling enable */ +#define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */ +#define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */ +#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */ +#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */ + +/* Bit 0 : Cache enable */ +#define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */ +#define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */ +#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */ +#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */ + +/* Register: NVMC_IHIT */ +/* Description: I-Code cache hit counter. */ + +/* Bits 31..0 : Number of cache hits */ +#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */ +#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */ + +/* Register: NVMC_IMISS */ +/* Description: I-Code cache miss counter. */ + +/* Bits 31..0 : Number of cache misses */ +#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */ +#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */ + + +/* Peripheral: GPIO */ +/* Description: GPIO Port 1 */ + +/* Register: GPIO_OUT */ +/* Description: Write GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */ + +/* Register: GPIO_OUTSET */ +/* Description: Set individual bits in GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Register: GPIO_OUTCLR */ +/* Description: Clear individual bits in GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Register: GPIO_IN */ +/* Description: Read GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */ + +/* Bit 30 : Pin 30 */ +#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */ + +/* Bit 29 : Pin 29 */ +#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */ + +/* Bit 28 : Pin 28 */ +#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */ + +/* Bit 27 : Pin 27 */ +#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */ + +/* Bit 26 : Pin 26 */ +#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */ + +/* Bit 25 : Pin 25 */ +#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */ + +/* Bit 24 : Pin 24 */ +#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */ + +/* Bit 23 : Pin 23 */ +#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */ + +/* Bit 22 : Pin 22 */ +#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */ + +/* Bit 21 : Pin 21 */ +#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */ + +/* Bit 20 : Pin 20 */ +#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */ + +/* Bit 19 : Pin 19 */ +#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */ + +/* Bit 18 : Pin 18 */ +#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */ + +/* Bit 17 : Pin 17 */ +#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */ + +/* Bit 16 : Pin 16 */ +#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */ + +/* Bit 15 : Pin 15 */ +#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */ + +/* Bit 14 : Pin 14 */ +#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */ + +/* Bit 13 : Pin 13 */ +#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */ + +/* Bit 12 : Pin 12 */ +#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */ + +/* Bit 11 : Pin 11 */ +#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */ + +/* Bit 10 : Pin 10 */ +#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */ + +/* Bit 9 : Pin 9 */ +#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */ + +/* Bit 8 : Pin 8 */ +#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */ + +/* Bit 7 : Pin 7 */ +#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */ + +/* Bit 6 : Pin 6 */ +#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */ + +/* Bit 5 : Pin 5 */ +#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */ + +/* Bit 4 : Pin 4 */ +#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */ + +/* Bit 3 : Pin 3 */ +#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */ + +/* Bit 2 : Pin 2 */ +#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */ + +/* Bit 1 : Pin 1 */ +#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */ + +/* Bit 0 : Pin 0 */ +#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */ + +/* Register: GPIO_DIR */ +/* Description: Direction of GPIO pins */ + +/* Bit 31 : Pin 31 */ +#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */ + +/* Bit 30 : Pin 30 */ +#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */ + +/* Bit 29 : Pin 29 */ +#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */ + +/* Bit 28 : Pin 28 */ +#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */ + +/* Bit 27 : Pin 27 */ +#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */ + +/* Bit 26 : Pin 26 */ +#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */ + +/* Bit 25 : Pin 25 */ +#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */ + +/* Bit 24 : Pin 24 */ +#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */ + +/* Bit 23 : Pin 23 */ +#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */ + +/* Bit 22 : Pin 22 */ +#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */ + +/* Bit 21 : Pin 21 */ +#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */ + +/* Bit 20 : Pin 20 */ +#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */ + +/* Bit 19 : Pin 19 */ +#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */ + +/* Bit 18 : Pin 18 */ +#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */ + +/* Bit 17 : Pin 17 */ +#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */ + +/* Bit 16 : Pin 16 */ +#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */ + +/* Bit 15 : Pin 15 */ +#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */ + +/* Bit 14 : Pin 14 */ +#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */ + +/* Bit 13 : Pin 13 */ +#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */ + +/* Bit 12 : Pin 12 */ +#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */ + +/* Bit 11 : Pin 11 */ +#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */ + +/* Bit 10 : Pin 10 */ +#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */ + +/* Bit 9 : Pin 9 */ +#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */ + +/* Bit 8 : Pin 8 */ +#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */ + +/* Bit 7 : Pin 7 */ +#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */ + +/* Bit 6 : Pin 6 */ +#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */ + +/* Bit 5 : Pin 5 */ +#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */ + +/* Bit 4 : Pin 4 */ +#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */ + +/* Bit 3 : Pin 3 */ +#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */ + +/* Bit 2 : Pin 2 */ +#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */ + +/* Bit 1 : Pin 1 */ +#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */ + +/* Bit 0 : Pin 0 */ +#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */ + +/* Register: GPIO_DIRSET */ +/* Description: DIR set register */ + +/* Bit 31 : Set as output pin 31 */ +#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 30 : Set as output pin 30 */ +#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 29 : Set as output pin 29 */ +#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 28 : Set as output pin 28 */ +#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 27 : Set as output pin 27 */ +#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 26 : Set as output pin 26 */ +#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 25 : Set as output pin 25 */ +#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 24 : Set as output pin 24 */ +#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 23 : Set as output pin 23 */ +#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 22 : Set as output pin 22 */ +#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 21 : Set as output pin 21 */ +#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 20 : Set as output pin 20 */ +#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 19 : Set as output pin 19 */ +#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 18 : Set as output pin 18 */ +#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 17 : Set as output pin 17 */ +#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 16 : Set as output pin 16 */ +#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 15 : Set as output pin 15 */ +#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 14 : Set as output pin 14 */ +#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 13 : Set as output pin 13 */ +#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 12 : Set as output pin 12 */ +#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 11 : Set as output pin 11 */ +#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 10 : Set as output pin 10 */ +#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 9 : Set as output pin 9 */ +#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 8 : Set as output pin 8 */ +#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 7 : Set as output pin 7 */ +#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 6 : Set as output pin 6 */ +#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 5 : Set as output pin 5 */ +#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 4 : Set as output pin 4 */ +#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 3 : Set as output pin 3 */ +#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 2 : Set as output pin 2 */ +#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 1 : Set as output pin 1 */ +#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 0 : Set as output pin 0 */ +#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Register: GPIO_DIRCLR */ +/* Description: DIR clear register */ + +/* Bit 31 : Set as input pin 31 */ +#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 30 : Set as input pin 30 */ +#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 29 : Set as input pin 29 */ +#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 28 : Set as input pin 28 */ +#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 27 : Set as input pin 27 */ +#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 26 : Set as input pin 26 */ +#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 25 : Set as input pin 25 */ +#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 24 : Set as input pin 24 */ +#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 23 : Set as input pin 23 */ +#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 22 : Set as input pin 22 */ +#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 21 : Set as input pin 21 */ +#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 20 : Set as input pin 20 */ +#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 19 : Set as input pin 19 */ +#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 18 : Set as input pin 18 */ +#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 17 : Set as input pin 17 */ +#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 16 : Set as input pin 16 */ +#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 15 : Set as input pin 15 */ +#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 14 : Set as input pin 14 */ +#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 13 : Set as input pin 13 */ +#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 12 : Set as input pin 12 */ +#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 11 : Set as input pin 11 */ +#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 10 : Set as input pin 10 */ +#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 9 : Set as input pin 9 */ +#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 8 : Set as input pin 8 */ +#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 7 : Set as input pin 7 */ +#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 6 : Set as input pin 6 */ +#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 5 : Set as input pin 5 */ +#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 4 : Set as input pin 4 */ +#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 3 : Set as input pin 3 */ +#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 2 : Set as input pin 2 */ +#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 1 : Set as input pin 1 */ +#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 0 : Set as input pin 0 */ +#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Register: GPIO_LATCH */ +/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ + +/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ + +/* Register: GPIO_DETECTMODE */ +/* Description: Select between default DETECT signal behaviour and LDETECT mode */ + +/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */ +#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ +#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ + +/* Register: GPIO_PIN_CNF */ +/* Description: Description collection[0]: Configuration of GPIO pins */ + +/* Bits 17..16 : Pin sensing mechanism */ +#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */ +#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */ +#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */ + +/* Bits 10..8 : Drive configuration */ +#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */ +#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */ +#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */ +#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */ + +/* Bits 3..2 : Pull configuration */ +#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ +#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ +#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */ +#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */ +#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */ + +/* Bit 1 : Connect or disconnect input buffer */ +#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */ +#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */ + +/* Bit 0 : Pin direction. Same physical register as DIR register */ +#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ +#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ +#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */ +#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */ + + +/* Peripheral: PDM */ +/* Description: Pulse Density Modulation (Digital Microphone) Interface */ + +/* Register: PDM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 2 : Enable or disable interrupt for END event */ +#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for STARTED event */ +#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Register: PDM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to Enable interrupt for END event */ +#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for STARTED event */ +#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Register: PDM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to Disable interrupt for END event */ +#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for STARTED event */ +#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Register: PDM_ENABLE */ +/* Description: PDM module enable register */ + +/* Bit 0 : Enable or disable PDM module */ +#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: PDM_PDMCLKCTRL */ +/* Description: PDM clock generator control */ + +/* Bits 31..0 : PDM_CLK frequency */ +#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */ +#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */ +#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */ +#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */ +#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */ + +/* Register: PDM_MODE */ +/* Description: Defines the routing of the connected PDM microphones' signals */ + +/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */ +#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */ +#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */ +#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ +#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */ + +/* Bit 0 : Mono or stereo operation */ +#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */ +#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */ +#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */ +#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */ + +/* Register: PDM_GAINL */ +/* Description: Left output gain adjustment */ + +/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */ +#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */ +#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */ +#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ +#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ +#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ + +/* Register: PDM_GAINR */ +/* Description: Right output gain adjustment */ + +/* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */ +#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */ +#define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ +#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ +#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ +#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ + +/* Register: PDM_PSEL_CLK */ +/* Description: Pin number configuration for PDM CLK signal */ + +/* Bit 31 : Connection */ +#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */ +#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: PDM_PSEL_DIN */ +/* Description: Pin number configuration for PDM DIN signal */ + +/* Bit 31 : Connection */ +#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */ +#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: PDM_SAMPLE_PTR */ +/* Description: RAM address pointer to write samples to with EasyDMA */ + +/* Bits 31..0 : Address to write PDM samples to over DMA */ +#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */ +#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */ + +/* Register: PDM_SAMPLE_MAXCNT */ +/* Description: Number of samples to allocate memory for in EasyDMA mode */ + +/* Bits 14..0 : Length of DMA RAM allocation in number of samples */ +#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */ +#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */ + + +/* Peripheral: POWER */ +/* Description: Power control */ + +/* Register: POWER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */ +#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */ +#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for POFWARN event */ +#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */ + +/* Register: POWER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */ +#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */ +#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for POFWARN event */ +#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */ + +/* Register: POWER_RESETREAS */ +/* Description: Reset reason */ + +/* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */ +#define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */ +#define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */ +#define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */ + +/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */ +#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ +#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ +#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */ + +/* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */ +#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */ +#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ +#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */ + +/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */ +#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ +#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ +#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */ + +/* Bit 3 : Reset from CPU lock-up detected */ +#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */ + +/* Bit 2 : Reset from soft reset detected */ +#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ +#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ +#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */ + +/* Bit 1 : Reset from watchdog detected */ +#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ +#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ +#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */ + +/* Bit 0 : Reset from pin-reset detected */ +#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */ + +/* Register: POWER_RAMSTATUS */ +/* Description: Deprecated register - RAM status register */ + +/* Bit 3 : RAM block 3 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */ + +/* Bit 2 : RAM block 2 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */ + +/* Bit 1 : RAM block 1 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */ + +/* Bit 0 : RAM block 0 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */ + +/* Register: POWER_SYSTEMOFF */ +/* Description: System OFF register */ + +/* Bit 0 : Enable System OFF mode */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */ + +/* Register: POWER_POFCON */ +/* Description: Power failure comparator configuration */ + +/* Bits 4..1 : Power failure comparator threshold setting */ +#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */ +#define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */ +#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */ +#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */ +#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */ +#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */ +#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */ +#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */ +#define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */ +#define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */ +#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */ +#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */ + +/* Bit 0 : Enable or disable power failure comparator */ +#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ +#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ +#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */ +#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_GPREGRET */ +/* Description: General purpose retention register */ + +/* Bits 7..0 : General purpose retention register */ +#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_GPREGRET2 */ +/* Description: General purpose retention register */ + +/* Bits 7..0 : General purpose retention register */ +#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_RAMON */ +/* Description: Deprecated register - RAM on/off register (this register is retained) */ + +/* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */ +#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */ +#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */ +#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< Off */ +#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM block 0 when RAM block is switched off */ +#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */ +#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */ +#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< Off */ +#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM block 1 on or off in system ON Mode */ +#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */ +#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */ +#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< Off */ +#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM block 0 on or off in system ON Mode */ +#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */ +#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */ +#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< Off */ +#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */ + +/* Register: POWER_RAMONB */ +/* Description: Deprecated register - RAM on/off register (this register is retained) */ + +/* Bit 17 : Keep retention on RAM block 3 when RAM block is switched off */ +#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */ +#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */ +#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< Off */ +#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM block 2 when RAM block is switched off */ +#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */ +#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */ +#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< Off */ +#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM block 3 on or off in system ON Mode */ +#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */ +#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */ +#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< Off */ +#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM block 2 on or off in system ON Mode */ +#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */ +#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */ +#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< Off */ +#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< On */ + +/* Register: POWER_DCDCEN */ +/* Description: DC/DC enable register */ + +/* Bit 0 : Enable or disable DC/DC converter */ +#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */ +#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_RAM_POWER */ +/* Description: Description cluster[0]: RAM0 power control register */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */ +#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */ +#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */ + +/* Register: POWER_RAM_POWERSET */ +/* Description: Description cluster[0]: RAM0 power control set register */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ + +/* Register: POWER_RAM_POWERCLR */ +/* Description: Description cluster[0]: RAM0 power control clear register */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */ + +/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */ + +/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */ + + +/* Peripheral: PPI */ +/* Description: Programmable Peripheral Interconnect */ + +/* Register: PPI_CHEN */ +/* Description: Channel enable register */ + +/* Bit 31 : Enable or disable channel 31 */ +#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */ + +/* Bit 30 : Enable or disable channel 30 */ +#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */ + +/* Bit 29 : Enable or disable channel 29 */ +#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */ + +/* Bit 28 : Enable or disable channel 28 */ +#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */ + +/* Bit 27 : Enable or disable channel 27 */ +#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */ + +/* Bit 26 : Enable or disable channel 26 */ +#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */ + +/* Bit 25 : Enable or disable channel 25 */ +#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */ + +/* Bit 24 : Enable or disable channel 24 */ +#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */ + +/* Bit 23 : Enable or disable channel 23 */ +#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */ + +/* Bit 22 : Enable or disable channel 22 */ +#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */ + +/* Bit 21 : Enable or disable channel 21 */ +#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */ + +/* Bit 20 : Enable or disable channel 20 */ +#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */ + +/* Bit 19 : Enable or disable channel 19 */ +#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */ + +/* Bit 18 : Enable or disable channel 18 */ +#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */ + +/* Bit 17 : Enable or disable channel 17 */ +#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */ + +/* Bit 16 : Enable or disable channel 16 */ +#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */ + +/* Bit 15 : Enable or disable channel 15 */ +#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */ + +/* Bit 14 : Enable or disable channel 14 */ +#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */ + +/* Bit 13 : Enable or disable channel 13 */ +#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */ + +/* Bit 12 : Enable or disable channel 12 */ +#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */ + +/* Bit 11 : Enable or disable channel 11 */ +#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */ + +/* Bit 10 : Enable or disable channel 10 */ +#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */ + +/* Bit 9 : Enable or disable channel 9 */ +#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */ + +/* Bit 8 : Enable or disable channel 8 */ +#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */ + +/* Bit 7 : Enable or disable channel 7 */ +#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */ + +/* Bit 6 : Enable or disable channel 6 */ +#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */ + +/* Bit 5 : Enable or disable channel 5 */ +#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */ + +/* Bit 4 : Enable or disable channel 4 */ +#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */ + +/* Bit 3 : Enable or disable channel 3 */ +#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */ + +/* Bit 2 : Enable or disable channel 2 */ +#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */ + +/* Bit 1 : Enable or disable channel 1 */ +#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */ + +/* Bit 0 : Enable or disable channel 0 */ +#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */ + +/* Register: PPI_CHENSET */ +/* Description: Channel enable set register */ + +/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */ + +/* Register: PPI_CHENCLR */ +/* Description: Channel enable clear register */ + +/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ + +/* Register: PPI_CH_EEP */ +/* Description: Description cluster[0]: Channel 0 event end-point */ + +/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ +#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ +#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ + +/* Register: PPI_CH_TEP */ +/* Description: Description cluster[0]: Channel 0 task end-point */ + +/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ +#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ +#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ + +/* Register: PPI_CHG */ +/* Description: Description collection[0]: Channel group 0 */ + +/* Bit 31 : Include or exclude channel 31 */ +#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH31_Included (1UL) /*!< Include */ + +/* Bit 30 : Include or exclude channel 30 */ +#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH30_Included (1UL) /*!< Include */ + +/* Bit 29 : Include or exclude channel 29 */ +#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH29_Included (1UL) /*!< Include */ + +/* Bit 28 : Include or exclude channel 28 */ +#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH28_Included (1UL) /*!< Include */ + +/* Bit 27 : Include or exclude channel 27 */ +#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH27_Included (1UL) /*!< Include */ + +/* Bit 26 : Include or exclude channel 26 */ +#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH26_Included (1UL) /*!< Include */ + +/* Bit 25 : Include or exclude channel 25 */ +#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH25_Included (1UL) /*!< Include */ + +/* Bit 24 : Include or exclude channel 24 */ +#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH24_Included (1UL) /*!< Include */ + +/* Bit 23 : Include or exclude channel 23 */ +#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH23_Included (1UL) /*!< Include */ + +/* Bit 22 : Include or exclude channel 22 */ +#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH22_Included (1UL) /*!< Include */ + +/* Bit 21 : Include or exclude channel 21 */ +#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH21_Included (1UL) /*!< Include */ + +/* Bit 20 : Include or exclude channel 20 */ +#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH20_Included (1UL) /*!< Include */ + +/* Bit 19 : Include or exclude channel 19 */ +#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH19_Included (1UL) /*!< Include */ + +/* Bit 18 : Include or exclude channel 18 */ +#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH18_Included (1UL) /*!< Include */ + +/* Bit 17 : Include or exclude channel 17 */ +#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH17_Included (1UL) /*!< Include */ + +/* Bit 16 : Include or exclude channel 16 */ +#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH16_Included (1UL) /*!< Include */ + +/* Bit 15 : Include or exclude channel 15 */ +#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH15_Included (1UL) /*!< Include */ + +/* Bit 14 : Include or exclude channel 14 */ +#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH14_Included (1UL) /*!< Include */ + +/* Bit 13 : Include or exclude channel 13 */ +#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH13_Included (1UL) /*!< Include */ + +/* Bit 12 : Include or exclude channel 12 */ +#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH12_Included (1UL) /*!< Include */ + +/* Bit 11 : Include or exclude channel 11 */ +#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH11_Included (1UL) /*!< Include */ + +/* Bit 10 : Include or exclude channel 10 */ +#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH10_Included (1UL) /*!< Include */ + +/* Bit 9 : Include or exclude channel 9 */ +#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH9_Included (1UL) /*!< Include */ + +/* Bit 8 : Include or exclude channel 8 */ +#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH8_Included (1UL) /*!< Include */ + +/* Bit 7 : Include or exclude channel 7 */ +#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH7_Included (1UL) /*!< Include */ + +/* Bit 6 : Include or exclude channel 6 */ +#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH6_Included (1UL) /*!< Include */ + +/* Bit 5 : Include or exclude channel 5 */ +#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH5_Included (1UL) /*!< Include */ + +/* Bit 4 : Include or exclude channel 4 */ +#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH4_Included (1UL) /*!< Include */ + +/* Bit 3 : Include or exclude channel 3 */ +#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH3_Included (1UL) /*!< Include */ + +/* Bit 2 : Include or exclude channel 2 */ +#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH2_Included (1UL) /*!< Include */ + +/* Bit 1 : Include or exclude channel 1 */ +#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH1_Included (1UL) /*!< Include */ + +/* Bit 0 : Include or exclude channel 0 */ +#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH0_Included (1UL) /*!< Include */ + +/* Register: PPI_FORK_TEP */ +/* Description: Description cluster[0]: Channel 0 task end-point */ + +/* Bits 31..0 : Pointer to task register */ +#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ +#define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ + + +/* Peripheral: PWM */ +/* Description: Pulse Width Modulation Unit 0 */ + +/* Register: PWM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between LOOPSDONE event and STOP task */ +#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ +#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ +#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between SEQEND[1] event and STOP task */ +#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ +#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ +#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between SEQEND[0] event and STOP task */ +#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ +#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ +#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: PWM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 7 : Enable or disable interrupt for LOOPSDONE event */ +#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */ +#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for SEQEND[1] event */ +#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for SEQEND[0] event */ +#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */ +#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */ +#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: PWM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */ +#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */ +#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */ +#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */ +#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */ +#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */ +#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: PWM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */ +#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */ +#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */ +#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */ +#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */ +#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */ +#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: PWM_ENABLE */ +/* Description: PWM module enable register */ + +/* Bit 0 : Enable or disable PWM module */ +#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */ +#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: PWM_MODE */ +/* Description: Selects operating mode of the wave counter */ + +/* Bit 0 : Selects up or up and down as wave counter mode */ +#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */ +#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */ +#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */ +#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */ + +/* Register: PWM_COUNTERTOP */ +/* Description: Value up to which the pulse generator counter counts */ + +/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */ +#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */ +#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */ + +/* Register: PWM_PRESCALER */ +/* Description: Configuration for PWM_CLK */ + +/* Bits 2..0 : Pre-scaler of PWM_CLK */ +#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ +#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 ( 8MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 ( 4MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 ( 2MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 ( 1MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 ( 500kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 ( 250kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */ + +/* Register: PWM_DECODER */ +/* Description: Configuration of the decoder */ + +/* Bit 8 : Selects source for advancing the active sequence */ +#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */ +#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */ +#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */ +#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */ + +/* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */ +#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ +#define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ +#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ +#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */ +#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ +#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */ + +/* Register: PWM_LOOP */ +/* Description: Amount of playback of a loop */ + +/* Bits 15..0 : Amount of playback of pattern cycles */ +#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ + +/* Register: PWM_SEQ_PTR */ +/* Description: Description cluster[0]: Beginning address in Data RAM of this sequence */ + +/* Bits 31..0 : Beginning address in Data RAM of this sequence */ +#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: PWM_SEQ_CNT */ +/* Description: Description cluster[0]: Amount of values (duty cycles) in this sequence */ + +/* Bits 14..0 : Amount of values (duty cycles) in this sequence */ +#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ + +/* Register: PWM_SEQ_REFRESH */ +/* Description: Description cluster[0]: Amount of additional PWM periods between samples loaded into compare register */ + +/* Bits 23..0 : Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ +#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ + +/* Register: PWM_SEQ_ENDDELAY */ +/* Description: Description cluster[0]: Time added after the sequence */ + +/* Bits 23..0 : Time added after the sequence in PWM periods */ +#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ + +/* Register: PWM_PSEL_OUT */ +/* Description: Description collection[0]: Output pin select for PWM channel 0 */ + +/* Bit 31 : Connection */ +#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */ +#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */ + + +/* Peripheral: QDEC */ +/* Description: Quadrature Decoder */ + +/* Register: QDEC_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between DBLRDY event and STOP task */ +#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between REPORTRDY event and STOP task */ +#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between SAMPLERDY event and STOP task */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: QDEC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 4 : Write '1' to Enable interrupt for STOPPED event */ +#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */ +#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for ACCOF event */ +#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */ +#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */ +#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */ + +/* Register: QDEC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 4 : Write '1' to Disable interrupt for STOPPED event */ +#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */ +#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for ACCOF event */ +#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */ +#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */ +#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */ + +/* Register: QDEC_ENABLE */ +/* Description: Enable the quadrature decoder */ + +/* Bit 0 : Enable or disable the quadrature decoder */ +#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: QDEC_LEDPOL */ +/* Description: LED output pin polarity */ + +/* Bit 0 : LED output pin polarity */ +#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */ +#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */ + +/* Register: QDEC_SAMPLEPER */ +/* Description: Sample period */ + +/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */ +#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */ + +/* Register: QDEC_SAMPLE */ +/* Description: Motion sample value */ + +/* Bits 31..0 : Last motion sample */ +#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ +#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ + +/* Register: QDEC_REPORTPER */ +/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ + +/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */ +#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */ +#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */ +#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */ +#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */ +#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */ +#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */ +#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */ +#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */ +#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */ + +/* Register: QDEC_ACC */ +/* Description: Register accumulating the valid transitions */ + +/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */ +#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ +#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ + +/* Register: QDEC_ACCREAD */ +/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */ + +/* Bits 31..0 : Snapshot of the ACC register. */ +#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */ +#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */ + +/* Register: QDEC_PSEL_LED */ +/* Description: Pin select for LED signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_A */ +/* Description: Pin select for A signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_B */ +/* Description: Pin select for B signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_DBFEN */ +/* Description: Enable input debounce filters */ + +/* Bit 0 : Enable input debounce filters */ +#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */ +#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */ + +/* Register: QDEC_LEDPRE */ +/* Description: Time period the LED is switched ON prior to sampling */ + +/* Bits 8..0 : Period in us the LED is switched on prior to sampling */ +#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ +#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ + +/* Register: QDEC_ACCDBL */ +/* Description: Register accumulating the number of detected double transitions */ + +/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */ +#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ +#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ + +/* Register: QDEC_ACCDBLREAD */ +/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */ + +/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ + + +/* Peripheral: RADIO */ +/* Description: 2.4 GHz Radio */ + +/* Register: RADIO_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 6 : Shortcut between ADDRESS event and BCSTART task */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between END event and START task */ +#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ +#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between DISABLED event and RXEN task */ +#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between DISABLED event and TXEN task */ +#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between END event and DISABLE task */ +#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between READY event and START task */ +#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ +#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ +#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: RADIO_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */ +#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ +#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to Enable interrupt for CRCOK event */ +#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ +#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ +#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */ +#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */ +#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */ +#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */ +#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for DISABLED event */ +#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for END event */ +#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */ +#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */ +#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for READY event */ +#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: RADIO_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */ +#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ +#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to Disable interrupt for CRCOK event */ +#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ +#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ +#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */ +#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */ +#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */ +#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */ +#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for DISABLED event */ +#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for END event */ +#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */ +#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */ +#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for READY event */ +#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: RADIO_CRCSTATUS */ +/* Description: CRC status */ + +/* Bit 0 : CRC status of packet received */ +#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */ + +/* Register: RADIO_RXMATCH */ +/* Description: Received address */ + +/* Bits 2..0 : Received address */ +#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ +#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ + +/* Register: RADIO_RXCRC */ +/* Description: CRC field of previously received packet */ + +/* Bits 23..0 : CRC field of previously received packet */ +#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ +#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ + +/* Register: RADIO_DAI */ +/* Description: Device address match index */ + +/* Bits 2..0 : Device address match index */ +#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ +#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ + +/* Register: RADIO_PACKETPTR */ +/* Description: Packet pointer */ + +/* Bits 31..0 : Packet pointer */ +#define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */ +#define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */ + +/* Register: RADIO_FREQUENCY */ +/* Description: Frequency */ + +/* Bit 8 : Channel map selection. */ +#define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ +#define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ +#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */ +#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */ + +/* Bits 6..0 : Radio channel frequency */ +#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ + +/* Register: RADIO_TXPOWER */ +/* Description: Output power */ + +/* Bits 7..0 : RADIO output power. */ +#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xFFUL) /*!< Deprecated enumerator - -40 dBm */ + +/* Register: RADIO_MODE */ +/* Description: Data rate and modulation */ + +/* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */ +#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */ +#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s Bluetooth Low Energy */ + +/* Register: RADIO_PCNF0 */ +/* Description: Packet configuration register 0 */ + +/* Bit 24 : Length of preamble on air. Decision point: TASKS_START task */ +#define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */ +#define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */ +#define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */ +#define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */ + +/* Bit 20 : Include or exclude S1 field in RAM */ +#define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */ +#define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */ +#define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ +#define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ + +/* Bits 19..16 : Length on air of S1 field in number of bits. */ +#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ +#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ + +/* Bit 8 : Length on air of S0 field in number of bytes. */ +#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ +#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ + +/* Bits 3..0 : Length on air of LENGTH field in number of bits. */ +#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ +#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ + +/* Register: RADIO_PCNF1 */ +/* Description: Packet configuration register 1 */ + +/* Bit 25 : Enable or disable packet whitening */ +#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */ +#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */ +#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */ +#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ + +/* Bits 18..16 : Base address length in number of bytes */ +#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ +#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ + +/* Bits 15..8 : Static length in number of bytes */ +#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ +#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ + +/* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */ +#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ +#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + +/* Register: RADIO_BASE0 */ +/* Description: Base address 0 */ + +/* Bits 31..0 : Base address 0 */ +#define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */ +#define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */ + +/* Register: RADIO_BASE1 */ +/* Description: Base address 1 */ + +/* Bits 31..0 : Base address 1 */ +#define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */ +#define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */ + +/* Register: RADIO_PREFIX0 */ +/* Description: Prefixes bytes for logical addresses 0-3 */ + +/* Bits 31..24 : Address prefix 3. */ +#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ +#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ + +/* Bits 23..16 : Address prefix 2. */ +#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ +#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ + +/* Bits 15..8 : Address prefix 1. */ +#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ +#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ + +/* Bits 7..0 : Address prefix 0. */ +#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ +#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ + +/* Register: RADIO_PREFIX1 */ +/* Description: Prefixes bytes for logical addresses 4-7 */ + +/* Bits 31..24 : Address prefix 7. */ +#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ +#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ + +/* Bits 23..16 : Address prefix 6. */ +#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ +#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ + +/* Bits 15..8 : Address prefix 5. */ +#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ +#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ + +/* Bits 7..0 : Address prefix 4. */ +#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ +#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ + +/* Register: RADIO_TXADDRESS */ +/* Description: Transmit address select */ + +/* Bits 2..0 : Transmit address select */ +#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ +#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ + +/* Register: RADIO_RXADDRESSES */ +/* Description: Receive address select */ + +/* Bit 7 : Enable or disable reception on logical address 7. */ +#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable reception on logical address 6. */ +#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable reception on logical address 5. */ +#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable reception on logical address 4. */ +#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable reception on logical address 3. */ +#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable reception on logical address 2. */ +#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable reception on logical address 1. */ +#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable reception on logical address 0. */ +#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */ + +/* Register: RADIO_CRCCNF */ +/* Description: CRC configuration */ + +/* Bit 8 : Include or exclude packet address field out of CRC calculation. */ +#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */ +#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ + +/* Bits 1..0 : CRC length in number of bytes. */ +#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ +#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ +#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ +#define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */ +#define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */ +#define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */ + +/* Register: RADIO_CRCPOLY */ +/* Description: CRC polynomial */ + +/* Bits 23..0 : CRC polynomial */ +#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ +#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ + +/* Register: RADIO_CRCINIT */ +/* Description: CRC initial value */ + +/* Bits 23..0 : CRC initial value */ +#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ +#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ + +/* Register: RADIO_TIFS */ +/* Description: Inter Frame Spacing in us */ + +/* Bits 7..0 : Inter Frame Spacing in us */ +#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ +#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ + +/* Register: RADIO_RSSISAMPLE */ +/* Description: RSSI sample */ + +/* Bits 6..0 : RSSI sample */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ + +/* Register: RADIO_STATE */ +/* Description: Current radio state */ + +/* Bits 3..0 : Current radio state */ +#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ +#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ +#define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */ +#define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */ +#define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */ +#define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */ +#define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */ +#define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */ +#define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */ +#define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */ +#define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */ + +/* Register: RADIO_DATAWHITEIV */ +/* Description: Data whitening initial value */ + +/* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ + +/* Register: RADIO_BCC */ +/* Description: Bit counter compare */ + +/* Bits 31..0 : Bit counter compare */ +#define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */ +#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ + +/* Register: RADIO_DAB */ +/* Description: Description collection[0]: Device address base segment 0 */ + +/* Bits 31..0 : Device address base segment 0 */ +#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ +#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ + +/* Register: RADIO_DAP */ +/* Description: Description collection[0]: Device address prefix 0 */ + +/* Bits 15..0 : Device address prefix 0 */ +#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ +#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ + +/* Register: RADIO_DACNF */ +/* Description: Device address match configuration */ + +/* Bit 15 : TxAdd for device address 7 */ +#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ +#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ + +/* Bit 14 : TxAdd for device address 6 */ +#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ +#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ + +/* Bit 13 : TxAdd for device address 5 */ +#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ +#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ + +/* Bit 12 : TxAdd for device address 4 */ +#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ +#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ + +/* Bit 11 : TxAdd for device address 3 */ +#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ +#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ + +/* Bit 10 : TxAdd for device address 2 */ +#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ +#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ + +/* Bit 9 : TxAdd for device address 1 */ +#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ +#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ + +/* Bit 8 : TxAdd for device address 0 */ +#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ +#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ + +/* Bit 7 : Enable or disable device address matching using device address 7 */ +#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ +#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ +#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */ + +/* Bit 6 : Enable or disable device address matching using device address 6 */ +#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ +#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ +#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */ + +/* Bit 5 : Enable or disable device address matching using device address 5 */ +#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ +#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ +#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */ + +/* Bit 4 : Enable or disable device address matching using device address 4 */ +#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ +#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ +#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */ + +/* Bit 3 : Enable or disable device address matching using device address 3 */ +#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ +#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ +#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */ + +/* Bit 2 : Enable or disable device address matching using device address 2 */ +#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ +#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ +#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */ + +/* Bit 1 : Enable or disable device address matching using device address 1 */ +#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ +#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ +#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */ + +/* Bit 0 : Enable or disable device address matching using device address 0 */ +#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ +#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ +#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */ + +/* Register: RADIO_MODECNF0 */ +/* Description: Radio mode configuration register 0 */ + +/* Bits 9..8 : Default TX value */ +#define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */ +#define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */ +#define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */ +#define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */ +#define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */ + +/* Bit 0 : Radio ramp-up time */ +#define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ +#define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ +#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */ +#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */ + +/* Register: RADIO_POWER */ +/* Description: Peripheral power control */ + +/* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */ +#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */ +#define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */ + + +/* Peripheral: RNG */ +/* Description: Random Number Generator */ + +/* Register: RNG_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 0 : Shortcut between VALRDY event and STOP task */ +#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: RNG_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to Enable interrupt for VALRDY event */ +#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ +#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */ +#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */ + +/* Register: RNG_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to Disable interrupt for VALRDY event */ +#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ +#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */ +#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */ + +/* Register: RNG_CONFIG */ +/* Description: Configuration register */ + +/* Bit 0 : Bias correction */ +#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */ +#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */ + +/* Register: RNG_VALUE */ +/* Description: Output random number */ + +/* Bits 7..0 : Generated random number */ +#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ +#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + +/* Peripheral: RTC */ +/* Description: Real time counter 0 */ + +/* Register: RTC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */ +#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */ +#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */ +#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */ +#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */ +#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for TICK event */ +#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */ +#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */ +#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */ +#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */ +#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */ +#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for TICK event */ +#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_EVTEN */ +/* Description: Enable or disable event routing */ + +/* Bit 19 : Enable or disable event routing for COMPARE[3] event */ +#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable event routing for COMPARE[2] event */ +#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable event routing for COMPARE[1] event */ +#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable event routing for COMPARE[0] event */ +#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable event routing for OVRFLW event */ +#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable event routing for TICK event */ +#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */ + +/* Register: RTC_EVTENSET */ +/* Description: Enable event routing */ + +/* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */ +#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */ +#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */ +#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */ +#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable event routing for OVRFLW event */ +#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable event routing for TICK event */ +#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_EVTENCLR */ +/* Description: Disable event routing */ + +/* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */ +#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */ +#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */ +#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */ +#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable event routing for OVRFLW event */ +#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable event routing for TICK event */ +#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_COUNTER */ +/* Description: Current COUNTER value */ + +/* Bits 23..0 : Counter value */ +#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ +#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ + +/* Register: RTC_PRESCALER */ +/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */ + +/* Bits 11..0 : Prescaler value */ +#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: RTC_CC */ +/* Description: Description collection[0]: Compare register 0 */ + +/* Bits 23..0 : Compare value */ +#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ +#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ + + +/* Peripheral: SAADC */ +/* Description: Analog to Digital Converter */ + +/* Register: SAADC_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */ +#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */ +#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */ +#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */ +#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */ +#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */ +#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */ +#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */ +#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */ +#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */ +#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */ +#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */ +#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */ +#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */ +#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */ +#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */ +#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for STOPPED event */ +#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */ +#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for RESULTDONE event */ +#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for DONE event */ +#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for END event */ +#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for STARTED event */ +#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Register: SAADC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */ +#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */ +#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */ +#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */ +#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */ +#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */ +#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */ +#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */ +#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */ +#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */ +#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */ +#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */ +#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */ +#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */ +#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */ +#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */ +#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for STOPPED event */ +#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */ +#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */ +#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for DONE event */ +#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for END event */ +#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for STARTED event */ +#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Register: SAADC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */ +#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */ +#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */ +#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */ +#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */ +#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */ +#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */ +#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */ +#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */ +#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */ +#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */ +#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */ +#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */ +#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */ +#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */ +#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */ +#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for STOPPED event */ +#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */ +#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */ +#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for DONE event */ +#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for END event */ +#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for STARTED event */ +#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Register: SAADC_STATUS */ +/* Description: Status */ + +/* Bit 0 : Status */ +#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */ +#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */ + +/* Register: SAADC_ENABLE */ +/* Description: Enable or disable ADC */ + +/* Bit 0 : Enable or disable ADC */ +#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */ +#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */ + +/* Register: SAADC_CH_PSELP */ +/* Description: Description cluster[0]: Input positive pin selection for CH[0] */ + +/* Bits 4..0 : Analog positive input channel */ +#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ +#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */ +#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */ +#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */ +#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */ + +/* Register: SAADC_CH_PSELN */ +/* Description: Description cluster[0]: Input negative pin selection for CH[0] */ + +/* Bits 4..0 : Analog negative input, enables differential channel */ +#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ +#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */ +#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */ +#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */ +#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */ + +/* Register: SAADC_CH_CONFIG */ +/* Description: Description cluster[0]: Input configuration for CH[0] */ + +/* Bit 24 : Enable burst mode */ +#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ +#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */ +#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */ +#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */ + +/* Bit 20 : Enable differential mode */ +#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */ +#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */ +#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */ + +/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */ +#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */ +#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */ +#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */ +#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */ +#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */ +#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */ +#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */ +#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */ + +/* Bit 12 : Reference control */ +#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */ +#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */ +#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */ + +/* Bits 10..8 : Gain control */ +#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */ +#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */ +#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */ +#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */ +#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */ +#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */ + +/* Bits 5..4 : Negative channel resistor control */ +#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */ +#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */ +#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */ +#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */ + +/* Bits 1..0 : Positive channel resistor control */ +#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */ +#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */ +#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */ +#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */ + +/* Register: SAADC_CH_LIMIT */ +/* Description: Description cluster[0]: High/low limits for event monitoring a channel */ + +/* Bits 31..16 : High level limit */ +#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ +#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */ + +/* Bits 15..0 : Low level limit */ +#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */ +#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */ + +/* Register: SAADC_RESOLUTION */ +/* Description: Resolution configuration */ + +/* Bits 2..0 : Set the resolution */ +#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */ +#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */ +#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */ +#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */ +#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */ +#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */ + +/* Register: SAADC_OVERSAMPLE */ +/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ + +/* Bits 3..0 : Oversample control */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */ + +/* Register: SAADC_SAMPLERATE */ +/* Description: Controls normal or continuous sample rate */ + +/* Bit 12 : Select mode for sample rate control */ +#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */ +#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */ +#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ + +/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */ +#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */ +#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */ + +/* Register: SAADC_RESULT_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SAADC_RESULT_MAXCNT */ +/* Description: Maximum number of buffer words to transfer */ + +/* Bits 14..0 : Maximum number of buffer words to transfer */ +#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SAADC_RESULT_AMOUNT */ +/* Description: Number of buffer words transferred since last START */ + +/* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */ +#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + +/* Peripheral: SPI */ +/* Description: Serial Peripheral Interface 0 */ + +/* Register: SPI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to Enable interrupt for READY event */ +#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: SPI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to Disable interrupt for READY event */ +#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: SPI_ENABLE */ +/* Description: Enable SPI */ + +/* Bits 3..0 : Enable or disable SPI */ +#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */ +#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */ + +/* Register: SPI_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bits 31..0 : Pin number configuration for SPI SCK signal */ +#define SPI_PSEL_SCK_PSELSCK_Pos (0UL) /*!< Position of PSELSCK field. */ +#define SPI_PSEL_SCK_PSELSCK_Msk (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos) /*!< Bit mask of PSELSCK field. */ +#define SPI_PSEL_SCK_PSELSCK_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: SPI_PSEL_MOSI */ +/* Description: Pin select for MOSI */ + +/* Bits 31..0 : Pin number configuration for SPI MOSI signal */ +#define SPI_PSEL_MOSI_PSELMOSI_Pos (0UL) /*!< Position of PSELMOSI field. */ +#define SPI_PSEL_MOSI_PSELMOSI_Msk (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos) /*!< Bit mask of PSELMOSI field. */ +#define SPI_PSEL_MOSI_PSELMOSI_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: SPI_PSEL_MISO */ +/* Description: Pin select for MISO */ + +/* Bits 31..0 : Pin number configuration for SPI MISO signal */ +#define SPI_PSEL_MISO_PSELMISO_Pos (0UL) /*!< Position of PSELMISO field. */ +#define SPI_PSEL_MISO_PSELMISO_Msk (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos) /*!< Bit mask of PSELMISO field. */ +#define SPI_PSEL_MISO_PSELMISO_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: SPI_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RX data received. Double buffered */ +#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: SPI_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TX data to send. Double buffered */ +#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: SPI_FREQUENCY */ +/* Description: SPI frequency */ + +/* Bits 31..0 : SPI master data rate */ +#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ + +/* Register: SPI_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + + +/* Peripheral: SPIM */ +/* Description: Serial Peripheral Interface Master with EasyDMA 0 */ + +/* Register: SPIM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 17 : Shortcut between END event and START task */ +#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ +#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ +#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to Enable interrupt for STARTED event */ +#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */ +#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for END event */ +#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ +#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: SPIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to Disable interrupt for STARTED event */ +#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */ +#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for END event */ +#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ +#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: SPIM_ENABLE */ +/* Description: Enable SPIM */ + +/* Bits 3..0 : Enable or disable SPIM */ +#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */ +#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */ + +/* Register: SPIM_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_FREQUENCY */ +/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : SPI master data rate */ +#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ + +/* Register: SPIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 7..0 : Maximum number of bytes in receive buffer */ +#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction */ +#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 7..0 : Maximum number of bytes in transmit buffer */ +#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction */ +#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIM_ORC */ +/* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */ + +/* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */ +#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: SPIS */ +/* Description: SPI Slave 0 */ + +/* Register: SPIS_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 2 : Shortcut between END event and ACQUIRE task */ +#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ +#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */ +#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ +#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for END event */ +#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Register: SPIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */ +#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ +#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for END event */ +#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Register: SPIS_SEMSTAT */ +/* Description: Semaphore status register */ + +/* Bits 1..0 : Semaphore status */ +#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */ +#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */ +#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */ +#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */ + +/* Register: SPIS_STATUS */ +/* Description: Status from last transaction */ + +/* Bit 1 : RX buffer overflow detected, and prevented */ +#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Bit 0 : TX buffer over-read detected, and prevented */ +#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Register: SPIS_ENABLE */ +/* Description: Enable SPI slave */ + +/* Bits 3..0 : Enable or disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */ + +/* Register: SPIS_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_CSN */ +/* Description: Pin select for CSN signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_RXD_PTR */ +/* Description: RXD data pointer */ + +/* Bits 31..0 : RXD data pointer */ +#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 7..0 : Maximum number of bytes in receive buffer */ +#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_RXD_AMOUNT */ +/* Description: Number of bytes received in last granted transaction */ + +/* Bits 7..0 : Number of bytes received in the last granted transaction */ +#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_TXD_PTR */ +/* Description: TXD data pointer */ + +/* Bits 31..0 : TXD data pointer */ +#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 7..0 : Maximum number of bytes in transmit buffer */ +#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_TXD_AMOUNT */ +/* Description: Number of bytes transmitted in last granted transaction */ + +/* Bits 7..0 : Number of bytes transmitted in last granted transaction */ +#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIS_DEF */ +/* Description: Default character. Character clocked out in case of an ignored transaction. */ + +/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */ +#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ +#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ + +/* Register: SPIS_ORC */ +/* Description: Over-read character */ + +/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */ +#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: TEMP */ +/* Description: Temperature Sensor */ + +/* Register: TEMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to Enable interrupt for DATARDY event */ +#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ +#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */ +#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */ + +/* Register: TEMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to Disable interrupt for DATARDY event */ +#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ +#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */ +#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */ + +/* Register: TEMP_TEMP */ +/* Description: Temperature in degC (0.25deg steps) */ + +/* Bits 31..0 : Temperature in degC (0.25deg steps) */ +#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */ +#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ + +/* Register: TEMP_A0 */ +/* Description: Slope of 1st piece wise linear function */ + +/* Bits 11..0 : Slope of 1st piece wise linear function */ +#define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ +#define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ + +/* Register: TEMP_A1 */ +/* Description: Slope of 2nd piece wise linear function */ + +/* Bits 11..0 : Slope of 2nd piece wise linear function */ +#define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ +#define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ + +/* Register: TEMP_A2 */ +/* Description: Slope of 3rd piece wise linear function */ + +/* Bits 11..0 : Slope of 3rd piece wise linear function */ +#define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ +#define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ + +/* Register: TEMP_A3 */ +/* Description: Slope of 4th piece wise linear function */ + +/* Bits 11..0 : Slope of 4th piece wise linear function */ +#define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ +#define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ + +/* Register: TEMP_A4 */ +/* Description: Slope of 5th piece wise linear function */ + +/* Bits 11..0 : Slope of 5th piece wise linear function */ +#define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ +#define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ + +/* Register: TEMP_A5 */ +/* Description: Slope of 6th piece wise linear function */ + +/* Bits 11..0 : Slope of 6th piece wise linear function */ +#define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ +#define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ + +/* Register: TEMP_B0 */ +/* Description: y-intercept of 1st piece wise linear function */ + +/* Bits 13..0 : y-intercept of 1st piece wise linear function */ +#define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ +#define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ + +/* Register: TEMP_B1 */ +/* Description: y-intercept of 2nd piece wise linear function */ + +/* Bits 13..0 : y-intercept of 2nd piece wise linear function */ +#define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ +#define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ + +/* Register: TEMP_B2 */ +/* Description: y-intercept of 3rd piece wise linear function */ + +/* Bits 13..0 : y-intercept of 3rd piece wise linear function */ +#define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ +#define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ + +/* Register: TEMP_B3 */ +/* Description: y-intercept of 4th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 4th piece wise linear function */ +#define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ +#define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ + +/* Register: TEMP_B4 */ +/* Description: y-intercept of 5th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 5th piece wise linear function */ +#define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ +#define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ + +/* Register: TEMP_B5 */ +/* Description: y-intercept of 6th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 6th piece wise linear function */ +#define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ +#define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ + +/* Register: TEMP_T0 */ +/* Description: End point of 1st piece wise linear function */ + +/* Bits 7..0 : End point of 1st piece wise linear function */ +#define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ +#define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ + +/* Register: TEMP_T1 */ +/* Description: End point of 2nd piece wise linear function */ + +/* Bits 7..0 : End point of 2nd piece wise linear function */ +#define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ +#define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ + +/* Register: TEMP_T2 */ +/* Description: End point of 3rd piece wise linear function */ + +/* Bits 7..0 : End point of 3rd piece wise linear function */ +#define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ +#define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ + +/* Register: TEMP_T3 */ +/* Description: End point of 4th piece wise linear function */ + +/* Bits 7..0 : End point of 4th piece wise linear function */ +#define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ +#define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ + +/* Register: TEMP_T4 */ +/* Description: End point of 5th piece wise linear function */ + +/* Bits 7..0 : End point of 5th piece wise linear function */ +#define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ +#define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ + + +/* Peripheral: TIMER */ +/* Description: Timer/Counter 0 */ + +/* Register: TIMER_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 13 : Shortcut between COMPARE[5] event and STOP task */ +#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 12 : Shortcut between COMPARE[4] event and STOP task */ +#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 11 : Shortcut between COMPARE[3] event and STOP task */ +#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between COMPARE[2] event and STOP task */ +#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between COMPARE[1] event and STOP task */ +#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between COMPARE[0] event and STOP task */ +#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TIMER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */ +#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */ +#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */ +#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */ +#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */ +#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */ +#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Register: TIMER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */ +#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */ +#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */ +#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */ +#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */ +#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */ +#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Register: TIMER_MODE */ +/* Description: Timer mode selection */ + +/* Bits 1..0 : Timer mode */ +#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */ +#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */ +#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */ + +/* Register: TIMER_BITMODE */ +/* Description: Configure the number of bits used by the TIMER */ + +/* Bits 1..0 : Timer bit width */ +#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */ + +/* Register: TIMER_PRESCALER */ +/* Description: Timer prescaler register */ + +/* Bits 3..0 : Prescaler value */ +#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: TIMER_CC */ +/* Description: Description collection[0]: Capture/Compare register 0 */ + +/* Bits 31..0 : Capture/Compare value */ +#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ +#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ + + +/* Peripheral: TWI */ +/* Description: I2C compatible Two-Wire Interface 0 */ + +/* Register: TWI_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 1 : Shortcut between BB event and STOP task */ +#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between BB event and SUSPEND task */ +#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */ +#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for BB event */ +#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */ +#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */ +#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */ +#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for BB event */ +#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */ +#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */ +#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWI_ERRORSRC */ +/* Description: Error source */ + +/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ +#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */ +#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */ +#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Bit 1 : NACK received after sending the address (write '1' to clear) */ +#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */ +#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */ +#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Bit 0 : Overrun error */ +#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ +#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ +#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Register: TWI_ENABLE */ +/* Description: Enable TWI */ + +/* Bits 3..0 : Enable or disable TWI */ +#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */ +#define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */ + +/* Register: TWI_PSELSCL */ +/* Description: Pin select for SCL */ + +/* Bits 31..0 : Pin number configuration for TWI SCL signal */ +#define TWI_PSELSCL_PSELSCL_Pos (0UL) /*!< Position of PSELSCL field. */ +#define TWI_PSELSCL_PSELSCL_Msk (0xFFFFFFFFUL << TWI_PSELSCL_PSELSCL_Pos) /*!< Bit mask of PSELSCL field. */ +#define TWI_PSELSCL_PSELSCL_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: TWI_PSELSDA */ +/* Description: Pin select for SDA */ + +/* Bits 31..0 : Pin number configuration for TWI SDA signal */ +#define TWI_PSELSDA_PSELSDA_Pos (0UL) /*!< Position of PSELSDA field. */ +#define TWI_PSELSDA_PSELSDA_Msk (0xFFFFFFFFUL << TWI_PSELSDA_PSELSDA_Pos) /*!< Bit mask of PSELSDA field. */ +#define TWI_PSELSDA_PSELSDA_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: TWI_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RXD register */ +#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: TWI_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TXD register */ +#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: TWI_FREQUENCY */ +/* Description: TWI frequency */ + +/* Bits 31..0 : TWI master clock frequency */ +#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ +#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */ + +/* Register: TWI_ADDRESS */ +/* Description: Address used in the TWI transfer */ + +/* Bits 6..0 : Address used in the TWI transfer */ +#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* Peripheral: TWIM */ +/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */ + +/* Register: TWIM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 12 : Shortcut between LASTRX event and STOP task */ +#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between LASTRX event and STARTTX task */ +#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between LASTTX event and STOP task */ +#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between LASTTX event and SUSPEND task */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 7 : Shortcut between LASTTX event and STARTRX task */ +#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 24 : Enable or disable interrupt for LASTTX event */ +#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ + +/* Bit 23 : Enable or disable interrupt for LASTRX event */ +#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for SUSPENDED event */ +#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ERROR event */ +#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 24 : Write '1' to Enable interrupt for LASTTX event */ +#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ + +/* Bit 23 : Write '1' to Enable interrupt for LASTRX event */ +#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ +#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ +#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */ +#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 24 : Write '1' to Disable interrupt for LASTTX event */ +#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ + +/* Bit 23 : Write '1' to Disable interrupt for LASTRX event */ +#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ +#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ +#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */ +#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIM_ERRORSRC */ +/* Description: Error source */ + +/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ +#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 1 : NACK received after sending the address (write '1' to clear) */ +#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */ + +/* Bit 0 : Overrun error */ +#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */ + +/* Register: TWIM_ENABLE */ +/* Description: Enable TWIM */ + +/* Bits 3..0 : Enable or disable TWIM */ +#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */ +#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */ + +/* Register: TWIM_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_FREQUENCY */ +/* Description: TWI frequency */ + +/* Bits 31..0 : TWI master clock frequency */ +#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ + +/* Register: TWIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 7..0 : Maximum number of bytes in receive buffer */ +#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 7..0 : Maximum number of bytes in transmit buffer */ +#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_ADDRESS */ +/* Description: Address used in the TWI transfer */ + +/* Bits 6..0 : Address used in the TWI transfer */ +#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* Peripheral: TWIS */ +/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */ + +/* Register: TWIS_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 14 : Shortcut between READ event and SUSPEND task */ +#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 13 : Shortcut between WRITE event and SUSPEND task */ +#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIS_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 26 : Enable or disable interrupt for READ event */ +#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable interrupt for WRITE event */ +#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ERROR event */ +#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 26 : Write '1' to Enable interrupt for READ event */ +#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to Enable interrupt for WRITE event */ +#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ +#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ +#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 26 : Write '1' to Disable interrupt for READ event */ +#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to Disable interrupt for WRITE event */ +#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ +#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ +#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIS_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : TX buffer over-read detected, and prevented */ +#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */ + +/* Bit 2 : NACK sent after receiving a data byte */ +#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 0 : RX buffer overflow detected, and prevented */ +#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */ + +/* Register: TWIS_MATCH */ +/* Description: Status register indicating which address had a match */ + +/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ +#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ +#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + +/* Register: TWIS_ENABLE */ +/* Description: Enable TWIS */ + +/* Bits 3..0 : Enable or disable TWIS */ +#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */ +#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */ + +/* Register: TWIS_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_RXD_PTR */ +/* Description: RXD Data pointer */ + +/* Bits 31..0 : RXD Data pointer */ +#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in RXD buffer */ + +/* Bits 7..0 : Maximum number of bytes in RXD buffer */ +#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last RXD transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last RXD transaction */ +#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_TXD_PTR */ +/* Description: TXD Data pointer */ + +/* Bits 31..0 : TXD Data pointer */ +#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in TXD buffer */ + +/* Bits 7..0 : Maximum number of bytes in TXD buffer */ +#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last TXD transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last TXD transaction */ +#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_ADDRESS */ +/* Description: Description collection[0]: TWI slave address 0 */ + +/* Bits 6..0 : TWI slave address */ +#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + +/* Register: TWIS_CONFIG */ +/* Description: Configuration register for the address match mechanism */ + +/* Bit 1 : Enable or disable address matching on ADDRESS[1] */ +#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */ + +/* Bit 0 : Enable or disable address matching on ADDRESS[0] */ +#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */ + +/* Register: TWIS_ORC */ +/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */ + +/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */ +#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: UART */ +/* Description: Universal Asynchronous Receiver/Transmitter */ + +/* Register: UART_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between NCTS event and STOPRX task */ +#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */ +#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between CTS event and STARTRX task */ +#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: UART_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 17 : Write '1' to Enable interrupt for RXTO event */ +#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */ +#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */ +#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for NCTS event */ +#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for CTS event */ +#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_CTS_Set (1UL) /*!< Enable */ + +/* Register: UART_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 17 : Write '1' to Disable interrupt for RXTO event */ +#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */ +#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */ +#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for NCTS event */ +#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for CTS event */ +#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */ + +/* Register: UART_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : Break condition */ +#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ + +/* Bit 2 : Framing error occurred */ +#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : Parity error */ +#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ + +/* Register: UART_ENABLE */ +/* Description: Enable UART */ + +/* Bits 3..0 : Enable or disable UART */ +#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */ +#define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */ + +/* Register: UART_PSELRTS */ +/* Description: Pin select for RTS */ + +/* Bits 31..0 : Pin number configuration for UART RTS signal */ +#define UART_PSELRTS_PSELRTS_Pos (0UL) /*!< Position of PSELRTS field. */ +#define UART_PSELRTS_PSELRTS_Msk (0xFFFFFFFFUL << UART_PSELRTS_PSELRTS_Pos) /*!< Bit mask of PSELRTS field. */ +#define UART_PSELRTS_PSELRTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: UART_PSELTXD */ +/* Description: Pin select for TXD */ + +/* Bits 31..0 : Pin number configuration for UART TXD signal */ +#define UART_PSELTXD_PSELTXD_Pos (0UL) /*!< Position of PSELTXD field. */ +#define UART_PSELTXD_PSELTXD_Msk (0xFFFFFFFFUL << UART_PSELTXD_PSELTXD_Pos) /*!< Bit mask of PSELTXD field. */ +#define UART_PSELTXD_PSELTXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: UART_PSELCTS */ +/* Description: Pin select for CTS */ + +/* Bits 31..0 : Pin number configuration for UART CTS signal */ +#define UART_PSELCTS_PSELCTS_Pos (0UL) /*!< Position of PSELCTS field. */ +#define UART_PSELCTS_PSELCTS_Msk (0xFFFFFFFFUL << UART_PSELCTS_PSELCTS_Pos) /*!< Bit mask of PSELCTS field. */ +#define UART_PSELCTS_PSELCTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: UART_PSELRXD */ +/* Description: Pin select for RXD */ + +/* Bits 31..0 : Pin number configuration for UART RXD signal */ +#define UART_PSELRXD_PSELRXD_Pos (0UL) /*!< Position of PSELRXD field. */ +#define UART_PSELRXD_PSELRXD_Msk (0xFFFFFFFFUL << UART_PSELRXD_PSELRXD_Pos) /*!< Bit mask of PSELRXD field. */ +#define UART_PSELRXD_PSELRXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: UART_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RX data received in previous transfers, double buffered */ +#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: UART_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TX data to be transferred */ +#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: UART_BAUDRATE */ +/* Description: Baud rate */ + +/* Bits 31..0 : Baud rate */ +#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ +#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ +#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ +#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ +#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */ +#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ +#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */ +#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ +#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */ +#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ +#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */ +#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ +#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */ +#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */ +#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ +#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */ +#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */ +#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ + +/* Register: UART_CONFIG */ +/* Description: Configuration of parity and hardware flow control */ + +/* Bits 3..1 : Parity */ +#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ +#define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */ + +/* Bit 0 : Hardware flow control */ +#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ +#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ + + +/* Peripheral: UARTE */ +/* Description: UART with EasyDMA */ + +/* Register: UARTE_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 6 : Shortcut between ENDRX event and STOPRX task */ +#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between ENDRX event and STARTRX task */ +#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: UARTE_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 22 : Enable or disable interrupt for TXSTOPPED event */ +#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for RXTO event */ +#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ERROR event */ +#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for ENDTX event */ +#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for TXDRDY event */ +#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for ENDRX event */ +#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for RXDRDY event */ +#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for NCTS event */ +#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for CTS event */ +#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */ + +/* Register: UARTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */ +#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ +#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ +#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for RXTO event */ +#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */ +#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */ +#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ +#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */ +#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for NCTS event */ +#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for CTS event */ +#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */ + +/* Register: UARTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */ +#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ +#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ +#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for RXTO event */ +#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */ +#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */ +#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ +#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */ +#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for NCTS event */ +#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for CTS event */ +#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ + +/* Register: UARTE_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : Break condition */ +#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ + +/* Bit 2 : Framing error occurred */ +#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : Parity error */ +#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ + +/* Register: UARTE_ENABLE */ +/* Description: Enable UART */ + +/* Bits 3..0 : Enable or disable UARTE */ +#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */ +#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */ + +/* Register: UARTE_PSEL_RTS */ +/* Description: Pin select for RTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_TXD */ +/* Description: Pin select for TXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_CTS */ +/* Description: Pin select for CTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_RXD */ +/* Description: Pin select for RXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_BAUDRATE */ +/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : Baud rate */ +#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ + +/* Register: UARTE_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 7..0 : Maximum number of bytes in receive buffer */ +#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction */ +#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 7..0 : Maximum number of bytes in transmit buffer */ +#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction */ +#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_CONFIG */ +/* Description: Configuration of parity and hardware flow control */ + +/* Bits 3..1 : Parity */ +#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ +#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */ + +/* Bit 0 : Hardware flow control */ +#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ +#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ + + +/* Peripheral: UICR */ +/* Description: User Information Configuration Registers */ + +/* Register: UICR_NRFFW */ +/* Description: Description collection[0]: Reserved for Nordic firmware design */ + +/* Bits 31..0 : Reserved for Nordic firmware design */ +#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */ +#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */ + +/* Register: UICR_NRFHW */ +/* Description: Description collection[0]: Reserved for Nordic hardware design */ + +/* Bits 31..0 : Reserved for Nordic hardware design */ +#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */ +#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */ + +/* Register: UICR_CUSTOMER */ +/* Description: Description collection[0]: Reserved for customer */ + +/* Bits 31..0 : Reserved for customer */ +#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ +#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ + +/* Register: UICR_PSELRESET */ +/* Description: Description collection[0]: Mapping of the nRESET function (see POWER chapter for details) */ + +/* Bit 31 : Connection */ +#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */ +#define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 5..0 : GPIO number P0.n onto which Reset is exposed */ +#define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UICR_PSELRESET_PIN_Msk (0x3FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UICR_APPROTECT */ +/* Description: Access Port protection */ + +/* Bits 7..0 : Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection. */ +#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ +#define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ +#define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ +#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ + +/* Register: UICR_NFCPINS */ +/* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */ + +/* Bit 0 : Setting of pins dedicated to NFC functionality */ +#define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */ +#define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */ +#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */ +#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */ + + +/* Peripheral: WDT */ +/* Description: Watchdog Timer */ + +/* Register: WDT_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */ +#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */ + +/* Register: WDT_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */ +#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */ + +/* Register: WDT_RUNSTATUS */ +/* Description: Run status */ + +/* Bit 0 : Indicates whether or not the watchdog is running */ +#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */ +#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */ + +/* Register: WDT_REQSTATUS */ +/* Description: Request status */ + +/* Bit 7 : Request status for RR[7] register */ +#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ + +/* Bit 6 : Request status for RR[6] register */ +#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ + +/* Bit 5 : Request status for RR[5] register */ +#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ + +/* Bit 4 : Request status for RR[4] register */ +#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ + +/* Bit 3 : Request status for RR[3] register */ +#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ + +/* Bit 2 : Request status for RR[2] register */ +#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ + +/* Bit 1 : Request status for RR[1] register */ +#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ + +/* Bit 0 : Request status for RR[0] register */ +#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ + +/* Register: WDT_CRV */ +/* Description: Counter reload value */ + +/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */ +#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */ +#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */ + +/* Register: WDT_RREN */ +/* Description: Enable register for reload request registers */ + +/* Bit 7 : Enable or disable RR[7] register */ +#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */ +#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */ + +/* Bit 6 : Enable or disable RR[6] register */ +#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */ +#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */ + +/* Bit 5 : Enable or disable RR[5] register */ +#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */ +#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */ + +/* Bit 4 : Enable or disable RR[4] register */ +#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */ +#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */ + +/* Bit 3 : Enable or disable RR[3] register */ +#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */ +#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */ + +/* Bit 2 : Enable or disable RR[2] register */ +#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */ +#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */ + +/* Bit 1 : Enable or disable RR[1] register */ +#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */ +#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */ + +/* Bit 0 : Enable or disable RR[0] register */ +#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */ +#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */ + +/* Register: WDT_CONFIG */ +/* Description: Configuration register */ + +/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ +#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ +#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ + +/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ + +/* Register: WDT_RR */ +/* Description: Description collection[0]: Reload request 0 */ + +/* Bits 31..0 : Reload request register */ +#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ +#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ +#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */ + + +/*lint --flb "Leave library region" */ +#endif diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_erratas.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_erratas.h new file mode 100644 index 000000000..d6ca9197f --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_erratas.h @@ -0,0 +1,9265 @@ +#ifndef NRF52_ERRATAS_H +#define NRF52_ERRATAS_H + +/* + +Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#include +#include +#include "compiler_abstraction.h" + +static bool nrf52_errata_1(void) __UNUSED; +static bool nrf52_errata_2(void) __UNUSED; +static bool nrf52_errata_3(void) __UNUSED; +static bool nrf52_errata_4(void) __UNUSED; +static bool nrf52_errata_7(void) __UNUSED; +static bool nrf52_errata_8(void) __UNUSED; +static bool nrf52_errata_9(void) __UNUSED; +static bool nrf52_errata_10(void) __UNUSED; +static bool nrf52_errata_11(void) __UNUSED; +static bool nrf52_errata_12(void) __UNUSED; +static bool nrf52_errata_15(void) __UNUSED; +static bool nrf52_errata_16(void) __UNUSED; +static bool nrf52_errata_17(void) __UNUSED; +static bool nrf52_errata_20(void) __UNUSED; +static bool nrf52_errata_23(void) __UNUSED; +static bool nrf52_errata_24(void) __UNUSED; +static bool nrf52_errata_25(void) __UNUSED; +static bool nrf52_errata_26(void) __UNUSED; +static bool nrf52_errata_27(void) __UNUSED; +static bool nrf52_errata_28(void) __UNUSED; +static bool nrf52_errata_29(void) __UNUSED; +static bool nrf52_errata_30(void) __UNUSED; +static bool nrf52_errata_31(void) __UNUSED; +static bool nrf52_errata_32(void) __UNUSED; +static bool nrf52_errata_33(void) __UNUSED; +static bool nrf52_errata_34(void) __UNUSED; +static bool nrf52_errata_35(void) __UNUSED; +static bool nrf52_errata_36(void) __UNUSED; +static bool nrf52_errata_37(void) __UNUSED; +static bool nrf52_errata_38(void) __UNUSED; +static bool nrf52_errata_39(void) __UNUSED; +static bool nrf52_errata_40(void) __UNUSED; +static bool nrf52_errata_41(void) __UNUSED; +static bool nrf52_errata_42(void) __UNUSED; +static bool nrf52_errata_43(void) __UNUSED; +static bool nrf52_errata_44(void) __UNUSED; +static bool nrf52_errata_46(void) __UNUSED; +static bool nrf52_errata_47(void) __UNUSED; +static bool nrf52_errata_48(void) __UNUSED; +static bool nrf52_errata_49(void) __UNUSED; +static bool nrf52_errata_51(void) __UNUSED; +static bool nrf52_errata_54(void) __UNUSED; +static bool nrf52_errata_55(void) __UNUSED; +static bool nrf52_errata_57(void) __UNUSED; +static bool nrf52_errata_58(void) __UNUSED; +static bool nrf52_errata_62(void) __UNUSED; +static bool nrf52_errata_63(void) __UNUSED; +static bool nrf52_errata_64(void) __UNUSED; +static bool nrf52_errata_65(void) __UNUSED; +static bool nrf52_errata_66(void) __UNUSED; +static bool nrf52_errata_67(void) __UNUSED; +static bool nrf52_errata_68(void) __UNUSED; +static bool nrf52_errata_70(void) __UNUSED; +static bool nrf52_errata_71(void) __UNUSED; +static bool nrf52_errata_72(void) __UNUSED; +static bool nrf52_errata_73(void) __UNUSED; +static bool nrf52_errata_74(void) __UNUSED; +static bool nrf52_errata_75(void) __UNUSED; +static bool nrf52_errata_76(void) __UNUSED; +static bool nrf52_errata_77(void) __UNUSED; +static bool nrf52_errata_78(void) __UNUSED; +static bool nrf52_errata_79(void) __UNUSED; +static bool nrf52_errata_81(void) __UNUSED; +static bool nrf52_errata_83(void) __UNUSED; +static bool nrf52_errata_84(void) __UNUSED; +static bool nrf52_errata_86(void) __UNUSED; +static bool nrf52_errata_87(void) __UNUSED; +static bool nrf52_errata_88(void) __UNUSED; +static bool nrf52_errata_89(void) __UNUSED; +static bool nrf52_errata_91(void) __UNUSED; +static bool nrf52_errata_94(void) __UNUSED; +static bool nrf52_errata_96(void) __UNUSED; +static bool nrf52_errata_97(void) __UNUSED; +static bool nrf52_errata_98(void) __UNUSED; +static bool nrf52_errata_101(void) __UNUSED; +static bool nrf52_errata_102(void) __UNUSED; +static bool nrf52_errata_103(void) __UNUSED; +static bool nrf52_errata_104(void) __UNUSED; +static bool nrf52_errata_106(void) __UNUSED; +static bool nrf52_errata_107(void) __UNUSED; +static bool nrf52_errata_108(void) __UNUSED; +static bool nrf52_errata_109(void) __UNUSED; +static bool nrf52_errata_110(void) __UNUSED; +static bool nrf52_errata_111(void) __UNUSED; +static bool nrf52_errata_112(void) __UNUSED; +static bool nrf52_errata_113(void) __UNUSED; +static bool nrf52_errata_115(void) __UNUSED; +static bool nrf52_errata_116(void) __UNUSED; +static bool nrf52_errata_117(void) __UNUSED; +static bool nrf52_errata_118(void) __UNUSED; +static bool nrf52_errata_119(void) __UNUSED; +static bool nrf52_errata_120(void) __UNUSED; +static bool nrf52_errata_121(void) __UNUSED; +static bool nrf52_errata_122(void) __UNUSED; +static bool nrf52_errata_127(void) __UNUSED; +static bool nrf52_errata_128(void) __UNUSED; +static bool nrf52_errata_131(void) __UNUSED; +static bool nrf52_errata_132(void) __UNUSED; +static bool nrf52_errata_133(void) __UNUSED; +static bool nrf52_errata_134(void) __UNUSED; +static bool nrf52_errata_135(void) __UNUSED; +static bool nrf52_errata_136(void) __UNUSED; +static bool nrf52_errata_138(void) __UNUSED; +static bool nrf52_errata_140(void) __UNUSED; +static bool nrf52_errata_141(void) __UNUSED; +static bool nrf52_errata_142(void) __UNUSED; +static bool nrf52_errata_143(void) __UNUSED; +static bool nrf52_errata_144(void) __UNUSED; +static bool nrf52_errata_145(void) __UNUSED; +static bool nrf52_errata_146(void) __UNUSED; +static bool nrf52_errata_147(void) __UNUSED; +static bool nrf52_errata_149(void) __UNUSED; +static bool nrf52_errata_150(void) __UNUSED; +static bool nrf52_errata_151(void) __UNUSED; +static bool nrf52_errata_153(void) __UNUSED; +static bool nrf52_errata_154(void) __UNUSED; +static bool nrf52_errata_155(void) __UNUSED; +static bool nrf52_errata_156(void) __UNUSED; +static bool nrf52_errata_158(void) __UNUSED; +static bool nrf52_errata_160(void) __UNUSED; +static bool nrf52_errata_162(void) __UNUSED; +static bool nrf52_errata_163(void) __UNUSED; +static bool nrf52_errata_164(void) __UNUSED; +static bool nrf52_errata_166(void) __UNUSED; +static bool nrf52_errata_170(void) __UNUSED; +static bool nrf52_errata_171(void) __UNUSED; +static bool nrf52_errata_172(void) __UNUSED; +static bool nrf52_errata_173(void) __UNUSED; +static bool nrf52_errata_174(void) __UNUSED; +static bool nrf52_errata_176(void) __UNUSED; +static bool nrf52_errata_178(void) __UNUSED; +static bool nrf52_errata_179(void) __UNUSED; +static bool nrf52_errata_180(void) __UNUSED; +static bool nrf52_errata_181(void) __UNUSED; +static bool nrf52_errata_182(void) __UNUSED; +static bool nrf52_errata_183(void) __UNUSED; +static bool nrf52_errata_184(void) __UNUSED; +static bool nrf52_errata_186(void) __UNUSED; +static bool nrf52_errata_187(void) __UNUSED; +static bool nrf52_errata_189(void) __UNUSED; +static bool nrf52_errata_190(void) __UNUSED; +static bool nrf52_errata_191(void) __UNUSED; +static bool nrf52_errata_192(void) __UNUSED; +static bool nrf52_errata_193(void) __UNUSED; +static bool nrf52_errata_194(void) __UNUSED; +static bool nrf52_errata_195(void) __UNUSED; +static bool nrf52_errata_196(void) __UNUSED; +static bool nrf52_errata_197(void) __UNUSED; +static bool nrf52_errata_198(void) __UNUSED; +static bool nrf52_errata_199(void) __UNUSED; +static bool nrf52_errata_200(void) __UNUSED; +static bool nrf52_errata_201(void) __UNUSED; +static bool nrf52_errata_202(void) __UNUSED; +static bool nrf52_errata_204(void) __UNUSED; +static bool nrf52_errata_208(void) __UNUSED; +static bool nrf52_errata_209(void) __UNUSED; +static bool nrf52_errata_210(void) __UNUSED; +static bool nrf52_errata_211(void) __UNUSED; +static bool nrf52_errata_212(void) __UNUSED; +static bool nrf52_errata_213(void) __UNUSED; +static bool nrf52_errata_214(void) __UNUSED; +static bool nrf52_errata_215(void) __UNUSED; +static bool nrf52_errata_216(void) __UNUSED; +static bool nrf52_errata_217(void) __UNUSED; +static bool nrf52_errata_218(void) __UNUSED; +static bool nrf52_errata_219(void) __UNUSED; +static bool nrf52_errata_220(void) __UNUSED; +static bool nrf52_errata_223(void) __UNUSED; +static bool nrf52_errata_225(void) __UNUSED; +static bool nrf52_errata_228(void) __UNUSED; +static bool nrf52_errata_230(void) __UNUSED; +static bool nrf52_errata_231(void) __UNUSED; +static bool nrf52_errata_232(void) __UNUSED; +static bool nrf52_errata_233(void) __UNUSED; +static bool nrf52_errata_236(void) __UNUSED; +static bool nrf52_errata_237(void) __UNUSED; +static bool nrf52_errata_248(void) __UNUSED; + +static bool nrf52_errata_1(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_2(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_3(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_4(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_7(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_8(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_9(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_10(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_11(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_12(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_15(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_16(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_17(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_20(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_23(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_24(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_25(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_26(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_27(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_28(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_29(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_30(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_31(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_32(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_33(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_34(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_35(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_36(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_37(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_38(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_39(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_40(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_41(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_42(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_43(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_44(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_46(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_47(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_48(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_49(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_51(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_54(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_55(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_57(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_58(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_62(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_63(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_64(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_65(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_66(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_67(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_68(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_70(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_71(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_72(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_73(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + uint32_t var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return false; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_74(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_75(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_76(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_77(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_78(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_79(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_81(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_83(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_84(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_86(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_87(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_88(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_89(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_91(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_94(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_96(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_97(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_98(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_101(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_102(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_103(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_104(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_106(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_107(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_108(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_109(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_110(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_111(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_112(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_113(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_115(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_116(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_117(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_118(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_119(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_120(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_121(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_122(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_127(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_128(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_131(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_132(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_133(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_134(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_135(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_136(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_138(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_140(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_141(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_142(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_143(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_144(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_145(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_146(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_147(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_149(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_150(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_151(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_153(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_154(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_155(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_156(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_158(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_160(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_162(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_163(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_164(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_166(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_170(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_171(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_172(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_173(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_174(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_176(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_178(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_179(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_180(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_181(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_182(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_183(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_184(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_186(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_187(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_189(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_190(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_191(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_192(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_193(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_194(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_195(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_196(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_197(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_198(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_199(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_200(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_201(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_202(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_204(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_208(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_209(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_210(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_211(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_212(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_213(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_214(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_215(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_216(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_217(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_218(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_219(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_220(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_223(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_225(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_228(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_230(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_231(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_232(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_233(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_236(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_237(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_248(void) +{ + #ifndef NRF52_SERIES + return false; + #else + return false; + #endif +} + +#endif /* NRF52_ERRATAS_H */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_name_change.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_name_change.h new file mode 100644 index 000000000..e3e314219 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_name_change.h @@ -0,0 +1,81 @@ +/* + +Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF52_NAME_CHANGE_H +#define NRF52_NAME_CHANGE_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the updates made to nrf52.h and + * nrf52_bitfields.h. The macros defined in this file were available previously. Do not use these + * macros on purpose. Use the ones defined in nrf52.h and nrf52_bitfields.h instead. + */ + +/* I2S */ +/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */ +#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled +#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled +#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master +#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave +#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled +#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled +#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled +#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled +#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled +#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled +#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit +#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit +#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit +#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left +#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right +#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned +#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo +#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left +#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right + +/* LPCOMP */ +/* Corrected typo in RESULT register. */ +#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below + +/*lint --flb "Leave library region" */ + +#endif /* NRF52_NAME_CHANGE_H */ + diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52810.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52810.h new file mode 100644 index 000000000..917ac519d --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52810.h @@ -0,0 +1,162 @@ +/* + +Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF52_TO_NRF52810_H +#define NRF52_TO_NRF52810_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the name changes between nRF51 or nRF52832 and nRF52810 devices. + * It redefines the old nRF51 or nRF52832 names into the new ones as long as the functionality is still supported. If the + * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros + * from the nrf52_namechange.h file. */ + +/* Differences between latest nRF52 headers and nRF52810 headers. */ + +/* Interrupt service routines handlers. Note that handlers SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler and + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler are not redefined since functionality is not equivalent. */ +#ifndef COMP_LPCOMP_IRQHandler + #define COMP_LPCOMP_IRQHandler COMP_IRQHandler +#endif +#ifndef SWI2_EGU2_IRQHandler + #define SWI2_EGU2_IRQHandler SWI2_IRQHandler +#endif +#ifndef SWI3_EGU3_IRQHandler + #define SWI3_EGU3_IRQHandler SWI3_IRQHandler +#endif +#ifndef SWI4_EGU4_IRQHandler + #define SWI4_EGU4_IRQHandler SWI4_IRQHandler +#endif +#ifndef SWI5_EGU5_IRQHandler + #define SWI5_EGU5_IRQHandler SWI5_IRQHandler +#endif + +/* Interrupt service routines index. Note that indexes SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn and + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn are not redefined since functionality is not equivalent. */ +#ifndef COMP_LPCOMP_IRQn + #define COMP_LPCOMP_IRQn COMP_IRQn +#endif +#ifndef SWI2_EGU2_IRQn + #define SWI2_EGU2_IRQn SWI2_IRQn +#endif +#ifndef SWI3_EGU3_IRQn + #define SWI3_EGU3_IRQn SWI3_IRQn +#endif +#ifndef SWI4_EGU4_IRQn + #define SWI4_EGU4_IRQn SWI4_IRQn +#endif +#ifndef SWI5_EGU5_IRQn + #define SWI5_EGU5_IRQn SWI5_IRQn +#endif + +/* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */ + +/* I2S */ +/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */ +#ifndef I2S_ENABLE_ENABLE_DISABLE + #define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled +#endif +#ifndef I2S_ENABLE_ENABLE_ENABLE + #define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled +#endif +#ifndef I2S_CONFIG_MODE_MODE_MASTER + #define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master +#endif +#ifndef I2S_CONFIG_MODE_MODE_SLAVE + #define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave +#endif +#ifndef I2S_CONFIG_RXEN_RXEN_DISABLE + #define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled +#endif +#ifndef I2S_CONFIG_RXEN_RXEN_ENABLE + #define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled +#endif +#ifndef I2S_CONFIG_TXEN_TXEN_DISABLE + #define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled +#endif +#ifndef I2S_CONFIG_TXEN_TXEN_ENABLE + #define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled +#endif +#ifndef I2S_CONFIG_MCKEN_MCKEN_DISABLE + #define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled +#endif +#ifndef I2S_CONFIG_MCKEN_MCKEN_ENABLE + #define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled +#endif +#ifndef I2S_CONFIG_SWIDTH_SWIDTH_8BIT + #define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit +#endif +#ifndef I2S_CONFIG_SWIDTH_SWIDTH_16BIT + #define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit +#endif +#ifndef I2S_CONFIG_SWIDTH_SWIDTH_24BIT + #define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit +#endif +#ifndef I2S_CONFIG_ALIGN_ALIGN_LEFT + #define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left +#endif +#ifndef I2S_CONFIG_ALIGN_ALIGN_RIGHT + #define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right +#endif +#ifndef I2S_CONFIG_FORMAT_FORMAT_ALIGNED + #define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned +#endif +#ifndef I2S_CONFIG_CHANNELS_CHANNELS_STEREO + #define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo +#endif +#ifndef I2S_CONFIG_CHANNELS_CHANNELS_LEFT + #define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left +#endif +#ifndef I2S_CONFIG_CHANNELS_CHANNELS_RIGHT + #define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right +#endif + +/* LPCOMP */ +/* Corrected typo in RESULT register. */ +#ifndef LPCOMP_RESULT_RESULT_Bellow + #define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below +#endif + + +/*lint --flb "Leave library region" */ + +#endif /* NRF52_TO_NRF52810_H */ + diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52833.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52833.h new file mode 100644 index 000000000..e364cf552 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52833.h @@ -0,0 +1,159 @@ +/* + +Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF52_TO_NRF52833_H +#define NRF52_TO_NRF52833_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the name changes between nRF51 or nRF52832 and nRF52840 devices. + * It redefines the old nRF51 or nRF52832 names into the new ones as long as the functionality is still supported. If the + * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros + * from the nrf52_namechange.h file. */ + +/* Differences between latest nRF52 headers and nRF52840 headers. */ + +/* UART */ +/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */ +#ifndef PSELRTS + #define PSELRTS PSEL.RTS +#endif +#ifndef PSELTXD + #define PSELTXD PSEL.TXD +#endif +#ifndef PSELCTS + #define PSELCTS PSEL.CTS +#endif +#ifndef PSELRXD + #define PSELRXD PSEL.RXD +#endif + +/* TWI */ +/* The registers PSELSCL, PSELSDA were restructured into a struct. */ +#ifndef PSELSCL + #define PSELSCL PSEL.SCL +#endif +#ifndef PSELSDA + #define PSELSDA PSEL.SDA +#endif + +/* LPCOMP */ +/* The hysteresis control enumerated values has changed name for nRF52833 devices. */ +#ifndef LPCOMP_HYST_HYST_NoHyst + #define LPCOMP_HYST_HYST_NoHyst LPCOMP_HYST_HYST_Disabled +#endif +#ifndef LPCOMP_HYST_HYST_Hyst50mV + #define LPCOMP_HYST_HYST_Hyst50mV LPCOMP_HYST_HYST_Enabled +#endif + + +/* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */ + +/* I2S */ +/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */ +#ifndef I2S_ENABLE_ENABLE_DISABLE + #define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled +#endif +#ifndef I2S_ENABLE_ENABLE_ENABLE + #define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled +#endif +#ifndef I2S_CONFIG_MODE_MODE_MASTER + #define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master +#endif +#ifndef I2S_CONFIG_MODE_MODE_SLAVE + #define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave +#endif +#ifndef I2S_CONFIG_RXEN_RXEN_DISABLE + #define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled +#endif +#ifndef I2S_CONFIG_RXEN_RXEN_ENABLE + #define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled +#endif +#ifndef I2S_CONFIG_TXEN_TXEN_DISABLE + #define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled +#endif +#ifndef I2S_CONFIG_TXEN_TXEN_ENABLE + #define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled +#endif +#ifndef I2S_CONFIG_MCKEN_MCKEN_DISABLE + #define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled +#endif +#ifndef I2S_CONFIG_MCKEN_MCKEN_ENABLE + #define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled +#endif +#ifndef I2S_CONFIG_SWIDTH_SWIDTH_8BIT + #define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit +#endif +#ifndef I2S_CONFIG_SWIDTH_SWIDTH_16BIT + #define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit +#endif +#ifndef I2S_CONFIG_SWIDTH_SWIDTH_24BIT + #define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit +#endif +#ifndef I2S_CONFIG_ALIGN_ALIGN_LEFT + #define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left +#endif +#ifndef I2S_CONFIG_ALIGN_ALIGN_RIGHT + #define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right +#endif +#ifndef I2S_CONFIG_FORMAT_FORMAT_ALIGNED + #define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned +#endif +#ifndef I2S_CONFIG_CHANNELS_CHANNELS_STEREO + #define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo +#endif +#ifndef I2S_CONFIG_CHANNELS_CHANNELS_LEFT + #define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left +#endif +#ifndef I2S_CONFIG_CHANNELS_CHANNELS_RIGHT + #define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right +#endif + +/* LPCOMP */ +/* Corrected typo in RESULT register. */ +#ifndef LPCOMP_RESULT_RESULT_Bellow + #define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below +#endif + +/*lint --flb "Leave library region" */ + +#endif /* NRF52_TO_NRF52833_H */ + diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52840.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52840.h new file mode 100644 index 000000000..ae43f5baa --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52840.h @@ -0,0 +1,161 @@ +/* + +Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF52_TO_NRF52840_H +#define NRF52_TO_NRF52840_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the name changes between nRF51 or nRF52832 and nRF52840 devices. + * It redefines the old nRF51 or nRF52832 names into the new ones as long as the functionality is still supported. If the + * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros + * from the nrf52_namechange.h file. */ + +/* Differences between latest nRF52 headers and nRF52840 headers. */ + +/* UART */ +/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */ +#ifndef PSELRTS + #define PSELRTS PSEL.RTS +#endif +#ifndef PSELTXD + #define PSELTXD PSEL.TXD +#endif +#ifndef PSELCTS + #define PSELCTS PSEL.CTS +#endif +#ifndef PSELRXD + #define PSELRXD PSEL.RXD +#endif + +/* TWI */ +/* The registers PSELSCL, PSELSDA were restructured into a struct. */ +#ifndef PSELSCL + #define PSELSCL PSEL.SCL +#endif +#ifndef PSELSDA + #define PSELSDA PSEL.SDA +#endif + + +/* LPCOMP */ +/* The hysteresis control enumerated values has changed name for nRF52840 devices. */ +#ifndef LPCOMP_HYST_HYST_NoHyst + #define LPCOMP_HYST_HYST_NoHyst LPCOMP_HYST_HYST_Disabled +#endif +#ifndef LPCOMP_HYST_HYST_Hyst50mV + #define LPCOMP_HYST_HYST_Hyst50mV LPCOMP_HYST_HYST_Enabled +#endif + + +/* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */ + +/* I2S */ +/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */ +#ifndef I2S_ENABLE_ENABLE_DISABLE + #define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled +#endif +#ifndef I2S_ENABLE_ENABLE_ENABLE + #define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled +#endif +#ifndef I2S_CONFIG_MODE_MODE_MASTER + #define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master +#endif +#ifndef I2S_CONFIG_MODE_MODE_SLAVE + #define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave +#endif +#ifndef I2S_CONFIG_RXEN_RXEN_DISABLE + #define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled +#endif +#ifndef I2S_CONFIG_RXEN_RXEN_ENABLE + #define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled +#endif +#ifndef I2S_CONFIG_TXEN_TXEN_DISABLE + #define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled +#endif +#ifndef I2S_CONFIG_TXEN_TXEN_ENABLE + #define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled +#endif +#ifndef I2S_CONFIG_MCKEN_MCKEN_DISABLE + #define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled +#endif +#ifndef I2S_CONFIG_MCKEN_MCKEN_ENABLE + #define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled +#endif +#ifndef I2S_CONFIG_SWIDTH_SWIDTH_8BIT + #define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit +#endif +#ifndef I2S_CONFIG_SWIDTH_SWIDTH_16BIT + #define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit +#endif +#ifndef I2S_CONFIG_SWIDTH_SWIDTH_24BIT + #define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit +#endif +#ifndef I2S_CONFIG_ALIGN_ALIGN_LEFT + #define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left +#endif +#ifndef I2S_CONFIG_ALIGN_ALIGN_RIGHT + #define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right +#endif +#ifndef I2S_CONFIG_FORMAT_FORMAT_ALIGNED + #define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned +#endif +#ifndef I2S_CONFIG_CHANNELS_CHANNELS_STEREO + #define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo +#endif +#ifndef I2S_CONFIG_CHANNELS_CHANNELS_LEFT + #define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left +#endif +#ifndef I2S_CONFIG_CHANNELS_CHANNELS_RIGHT + #define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right +#endif + +/* LPCOMP */ +/* Corrected typo in RESULT register. */ +#ifndef LPCOMP_RESULT_RESULT_Bellow + #define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below +#endif + + +/*lint --flb "Leave library region" */ + +#endif /* NRF51_TO_NRF52840_H */ + diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf53_erratas.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf53_erratas.h new file mode 100644 index 000000000..5f16f1473 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf53_erratas.h @@ -0,0 +1,2922 @@ +#ifndef NRF53_ERRATAS_H +#define NRF53_ERRATAS_H + +/* + +Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#include +#include +#include "compiler_abstraction.h" + +static bool nrf53_errata_1(void) __UNUSED; +static bool nrf53_errata_2(void) __UNUSED; +static bool nrf53_errata_3(void) __UNUSED; +static bool nrf53_errata_4(void) __UNUSED; +static bool nrf53_errata_5(void) __UNUSED; +static bool nrf53_errata_6(void) __UNUSED; +static bool nrf53_errata_7(void) __UNUSED; +static bool nrf53_errata_8(void) __UNUSED; +static bool nrf53_errata_9(void) __UNUSED; +static bool nrf53_errata_10(void) __UNUSED; +static bool nrf53_errata_11(void) __UNUSED; +static bool nrf53_errata_12(void) __UNUSED; +static bool nrf53_errata_13(void) __UNUSED; +static bool nrf53_errata_14(void) __UNUSED; +static bool nrf53_errata_15(void) __UNUSED; +static bool nrf53_errata_16(void) __UNUSED; +static bool nrf53_errata_18(void) __UNUSED; +static bool nrf53_errata_19(void) __UNUSED; +static bool nrf53_errata_20(void) __UNUSED; +static bool nrf53_errata_21(void) __UNUSED; +static bool nrf53_errata_22(void) __UNUSED; +static bool nrf53_errata_23(void) __UNUSED; +static bool nrf53_errata_26(void) __UNUSED; +static bool nrf53_errata_27(void) __UNUSED; +static bool nrf53_errata_28(void) __UNUSED; +static bool nrf53_errata_29(void) __UNUSED; +static bool nrf53_errata_30(void) __UNUSED; +static bool nrf53_errata_31(void) __UNUSED; +static bool nrf53_errata_32(void) __UNUSED; +static bool nrf53_errata_33(void) __UNUSED; +static bool nrf53_errata_34(void) __UNUSED; +static bool nrf53_errata_36(void) __UNUSED; +static bool nrf53_errata_37(void) __UNUSED; +static bool nrf53_errata_42(void) __UNUSED; +static bool nrf53_errata_43(void) __UNUSED; +static bool nrf53_errata_44(void) __UNUSED; +static bool nrf53_errata_45(void) __UNUSED; +static bool nrf53_errata_46(void) __UNUSED; +static bool nrf53_errata_47(void) __UNUSED; +static bool nrf53_errata_49(void) __UNUSED; +static bool nrf53_errata_50(void) __UNUSED; +static bool nrf53_errata_51(void) __UNUSED; +static bool nrf53_errata_52(void) __UNUSED; +static bool nrf53_errata_53(void) __UNUSED; +static bool nrf53_errata_54(void) __UNUSED; +static bool nrf53_errata_55(void) __UNUSED; +static bool nrf53_errata_57(void) __UNUSED; +static bool nrf53_errata_58(void) __UNUSED; +static bool nrf53_errata_59(void) __UNUSED; +static bool nrf53_errata_62(void) __UNUSED; +static bool nrf53_errata_64(void) __UNUSED; +static bool nrf53_errata_65(void) __UNUSED; +static bool nrf53_errata_66(void) __UNUSED; +static bool nrf53_errata_67(void) __UNUSED; +static bool nrf53_errata_69(void) __UNUSED; +static bool nrf53_errata_70(void) __UNUSED; +static bool nrf53_errata_71(void) __UNUSED; +static bool nrf53_errata_72(void) __UNUSED; +static bool nrf53_errata_73(void) __UNUSED; +static bool nrf53_errata_74(void) __UNUSED; +static bool nrf53_errata_75(void) __UNUSED; +static bool nrf53_errata_76(void) __UNUSED; +static bool nrf53_errata_77(void) __UNUSED; +static bool nrf53_errata_79(void) __UNUSED; +static bool nrf53_errata_80(void) __UNUSED; +static bool nrf53_errata_81(void) __UNUSED; +static bool nrf53_errata_82(void) __UNUSED; +static bool nrf53_errata_83(void) __UNUSED; +static bool nrf53_errata_84(void) __UNUSED; +static bool nrf53_errata_85(void) __UNUSED; +static bool nrf53_errata_86(void) __UNUSED; +static bool nrf53_errata_87(void) __UNUSED; +static bool nrf53_errata_90(void) __UNUSED; +static bool nrf53_errata_91(void) __UNUSED; +static bool nrf53_errata_93(void) __UNUSED; +static bool nrf53_errata_95(void) __UNUSED; +static bool nrf53_errata_97(void) __UNUSED; +static bool nrf53_errata_103(void) __UNUSED; +static bool nrf53_errata_105(void) __UNUSED; +static bool nrf53_errata_106(void) __UNUSED; +static bool nrf53_errata_109(void) __UNUSED; +static bool nrf53_errata_110(void) __UNUSED; +static bool nrf53_errata_113(void) __UNUSED; +static bool nrf53_errata_114(void) __UNUSED; +static bool nrf53_errata_115(void) __UNUSED; +static bool nrf53_errata_116(void) __UNUSED; +static bool nrf53_errata_119(void) __UNUSED; + +static bool nrf53_errata_1(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_2(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_3(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_4(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_5(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_6(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_7(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_8(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_9(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_10(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_11(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_12(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_13(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_14(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_15(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_16(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_18(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_19(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_20(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_21(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_22(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_23(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_26(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_27(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_28(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_29(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_30(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_31(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_32(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_33(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_34(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_36(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_37(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_42(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_43(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_44(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_45(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_46(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_47(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_49(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_50(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_51(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_52(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_53(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_54(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_55(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_57(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_58(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_59(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_62(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_64(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_65(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_66(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_67(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_69(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_70(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_71(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_72(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_73(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_74(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_75(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_76(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_77(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_79(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_80(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_81(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_82(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_83(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_84(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_85(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_86(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_87(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_90(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_91(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_93(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_95(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_97(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_103(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_105(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_106(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_109(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_110(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_113(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_114(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_115(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_116(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_119(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +#endif /* NRF53_ERRATAS_H */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf91_erratas.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf91_erratas.h new file mode 100644 index 000000000..269bb0391 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf91_erratas.h @@ -0,0 +1,750 @@ +#ifndef NRF91_ERRATAS_H +#define NRF91_ERRATAS_H + +/* + +Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#include +#include +#include "compiler_abstraction.h" + +static bool nrf91_errata_1(void) __UNUSED; +static bool nrf91_errata_2(void) __UNUSED; +static bool nrf91_errata_4(void) __UNUSED; +static bool nrf91_errata_6(void) __UNUSED; +static bool nrf91_errata_7(void) __UNUSED; +static bool nrf91_errata_8(void) __UNUSED; +static bool nrf91_errata_9(void) __UNUSED; +static bool nrf91_errata_10(void) __UNUSED; +static bool nrf91_errata_12(void) __UNUSED; +static bool nrf91_errata_14(void) __UNUSED; +static bool nrf91_errata_15(void) __UNUSED; +static bool nrf91_errata_16(void) __UNUSED; +static bool nrf91_errata_17(void) __UNUSED; +static bool nrf91_errata_20(void) __UNUSED; +static bool nrf91_errata_21(void) __UNUSED; +static bool nrf91_errata_23(void) __UNUSED; +static bool nrf91_errata_24(void) __UNUSED; +static bool nrf91_errata_26(void) __UNUSED; +static bool nrf91_errata_27(void) __UNUSED; +static bool nrf91_errata_28(void) __UNUSED; +static bool nrf91_errata_29(void) __UNUSED; +static bool nrf91_errata_30(void) __UNUSED; +static bool nrf91_errata_31(void) __UNUSED; +static bool nrf91_errata_32(void) __UNUSED; +static bool nrf91_errata_33(void) __UNUSED; + +static bool nrf91_errata_1(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_2(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_4(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_6(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_7(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_8(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_9(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return false; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_10(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_12(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_14(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_15(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return false; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_16(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_17(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_20(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_21(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_23(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_24(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_26(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_27(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return false; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_28(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_29(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_30(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_31(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_32(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf91_errata_33(void) +{ + #ifndef NRF91_SERIES + return false; + #else + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + if (var1 == 0x09) + { + switch(var2) + { + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +#endif /* NRF91_ERRATAS_H */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf_erratas.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf_erratas.h new file mode 100644 index 000000000..484b38595 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf_erratas.h @@ -0,0 +1,59 @@ +/* + +Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF_ERRATAS_H +#define NRF_ERRATAS_H + +#include "nrf.h" + +/* Check MDK version to make sure we have the required macros */ +NRF_MDK_VERSION_ASSERT_AT_LEAST(8,34,0); + +/*lint ++flb "Enter library region */ + +#include "nrf51_erratas.h" +#include "nrf52_erratas.h" +#include "nrf53_erratas.h" +#include "nrf91_erratas.h" + +/*lint --flb "Leave library region" */ + +#endif // NRF_ERRATAS_H diff --git a/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52820.c b/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52820.c new file mode 100644 index 000000000..eb09aafc2 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52820.c @@ -0,0 +1,119 @@ +/* + +Copyright (c) 2009-2020 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +/* NOTE: Template files (including this one) are application specific and therefore expected to + be copied into the application project folder prior to its use! */ + +#include +#include +#include "nrf.h" +#include "nrf_erratas.h" +#include "system_nrf52820.h" + +/*lint ++flb "Enter library region" */ + +#define __SYSTEM_CLOCK_64M (64000000UL) + +#if defined ( __CC_ARM ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; +#elif defined ( __ICCARM__ ) + __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M; +#elif defined ( __GNUC__ ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; +#endif + +void SystemCoreClockUpdate(void) +{ + SystemCoreClock = __SYSTEM_CLOCK_64M; +} + +void SystemInit(void) +{ + /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_36()){ + NRF_CLOCK->EVENTS_DONE = 0; + NRF_CLOCK->EVENTS_CTTO = 0; + NRF_CLOCK->CTIV = 0; + } + + /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_66()){ + NRF_TEMP->A0 = NRF_FICR->TEMP.A0; + NRF_TEMP->A1 = NRF_FICR->TEMP.A1; + NRF_TEMP->A2 = NRF_FICR->TEMP.A2; + NRF_TEMP->A3 = NRF_FICR->TEMP.A3; + NRF_TEMP->A4 = NRF_FICR->TEMP.A4; + NRF_TEMP->A5 = NRF_FICR->TEMP.A5; + NRF_TEMP->B0 = NRF_FICR->TEMP.B0; + NRF_TEMP->B1 = NRF_FICR->TEMP.B1; + NRF_TEMP->B2 = NRF_FICR->TEMP.B2; + NRF_TEMP->B3 = NRF_FICR->TEMP.B3; + NRF_TEMP->B4 = NRF_FICR->TEMP.B4; + NRF_TEMP->B5 = NRF_FICR->TEMP.B5; + NRF_TEMP->T0 = NRF_FICR->TEMP.T0; + NRF_TEMP->T1 = NRF_FICR->TEMP.T1; + NRF_TEMP->T2 = NRF_FICR->TEMP.T2; + NRF_TEMP->T3 = NRF_FICR->TEMP.T3; + NRF_TEMP->T4 = NRF_FICR->TEMP.T4; + } + + /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_136()){ + if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){ + NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk; + } + } + + /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the + * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit + * operations are not used in your code. */ + #if (__FPU_USED == 1) + SCB->CPACR |= (3UL << 20) | (3UL << 22); + __DSB(); + __ISB(); + #endif + + /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not + defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be + reserved for PinReset and not available as normal GPIO. */ + #if defined (CONFIG_GPIO_AS_PINRESET) + if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || + ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->PSELRESET[0] = 18; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->PSELRESET[1] = 18; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NVIC_SystemReset(); + } + #endif + + SystemCoreClockUpdate(); +} + +/*lint --flb "Leave library region" */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52820.h b/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52820.h new file mode 100644 index 000000000..a2a326dd1 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52820.h @@ -0,0 +1,61 @@ +/* + +Copyright (c) 2009-2020 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +#ifndef SYSTEM_NRF52820_H +#define SYSTEM_NRF52820_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_NRF52820_H */ diff --git a/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf52820.S b/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf52820.S new file mode 100644 index 000000000..6412cd50a --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf52820.S @@ -0,0 +1,358 @@ +/*********************************************************************************** + * SEGGER Microcontroller GmbH * + * The Embedded Experts * + *********************************************************************************** + * * + * (c) 2014 - 2018 SEGGER Microcontroller GmbH * + * * + * www.segger.com Support: support@segger.com * + * * + *********************************************************************************** + * * + * All rights reserved. * + * * + * Redistribution and use in source and binary forms, with or * + * without modification, are permitted provided that the following * + * conditions are met: * + * * + * - Redistributions of source code must retain the above copyright * + * notice, this list of conditions and the following disclaimer. * + * * + * - Neither the name of SEGGER Microcontroller GmbH * + * nor the names of its contributors may be used to endorse or * + * promote products derived from this software without specific * + * prior written permission. * + * * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * + * DISCLAIMED. * + * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * + * DAMAGE. * + * * + ***********************************************************************************/ + +/************************************************************************************ + * Preprocessor Definitions * + * ------------------------ * + * VECTORS_IN_RAM * + * * + * If defined, an area of RAM will large enough to store the vector table * + * will be reserved. * + * * + ************************************************************************************/ + + .syntax unified + .code 16 + + .section .init, "ax" + .align 0 + +/************************************************************************************ + * Default Exception Handlers * + ************************************************************************************/ + + + .thumb_func + .weak NMI_Handler +NMI_Handler: + b . + + .thumb_func + .weak HardFault_Handler +HardFault_Handler: + b . + + .thumb_func + .weak MemoryManagement_Handler +MemoryManagement_Handler: + b . + + .thumb_func + .weak BusFault_Handler +BusFault_Handler: + b . + + .thumb_func + .weak UsageFault_Handler +UsageFault_Handler: + b . + + .thumb_func + .weak SVC_Handler +SVC_Handler: + b . + + .thumb_func + .weak DebugMon_Handler +DebugMon_Handler: + b . + + .thumb_func + .weak PendSV_Handler +PendSV_Handler: + b . + + .thumb_func + .weak SysTick_Handler +SysTick_Handler: + b . + + .thumb_func + .weak Dummy_Handler +Dummy_Handler: + b . + +/************************************************************************************ + * Default Interrupt Handlers * + ************************************************************************************/ + +.weak POWER_CLOCK_IRQHandler +.thumb_set POWER_CLOCK_IRQHandler, Dummy_Handler + +.weak RADIO_IRQHandler +.thumb_set RADIO_IRQHandler, Dummy_Handler + +.weak UARTE0_UART0_IRQHandler +.thumb_set UARTE0_UART0_IRQHandler, Dummy_Handler + +.weak SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +.thumb_set SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler, Dummy_Handler + +.weak SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +.thumb_set SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler, Dummy_Handler + +.weak GPIOTE_IRQHandler +.thumb_set GPIOTE_IRQHandler, Dummy_Handler + +.weak TIMER0_IRQHandler +.thumb_set TIMER0_IRQHandler, Dummy_Handler + +.weak TIMER1_IRQHandler +.thumb_set TIMER1_IRQHandler, Dummy_Handler + +.weak TIMER2_IRQHandler +.thumb_set TIMER2_IRQHandler, Dummy_Handler + +.weak RTC0_IRQHandler +.thumb_set RTC0_IRQHandler, Dummy_Handler + +.weak TEMP_IRQHandler +.thumb_set TEMP_IRQHandler, Dummy_Handler + +.weak RNG_IRQHandler +.thumb_set RNG_IRQHandler, Dummy_Handler + +.weak ECB_IRQHandler +.thumb_set ECB_IRQHandler, Dummy_Handler + +.weak CCM_AAR_IRQHandler +.thumb_set CCM_AAR_IRQHandler, Dummy_Handler + +.weak WDT_IRQHandler +.thumb_set WDT_IRQHandler, Dummy_Handler + +.weak RTC1_IRQHandler +.thumb_set RTC1_IRQHandler, Dummy_Handler + +.weak QDEC_IRQHandler +.thumb_set QDEC_IRQHandler, Dummy_Handler + +.weak COMP_IRQHandler +.thumb_set COMP_IRQHandler, Dummy_Handler + +.weak SWI0_EGU0_IRQHandler +.thumb_set SWI0_EGU0_IRQHandler, Dummy_Handler + +.weak SWI1_EGU1_IRQHandler +.thumb_set SWI1_EGU1_IRQHandler, Dummy_Handler + +.weak SWI2_EGU2_IRQHandler +.thumb_set SWI2_EGU2_IRQHandler, Dummy_Handler + +.weak SWI3_EGU3_IRQHandler +.thumb_set SWI3_EGU3_IRQHandler, Dummy_Handler + +.weak SWI4_EGU4_IRQHandler +.thumb_set SWI4_EGU4_IRQHandler, Dummy_Handler + +.weak SWI5_EGU5_IRQHandler +.thumb_set SWI5_EGU5_IRQHandler, Dummy_Handler + +.weak TIMER3_IRQHandler +.thumb_set TIMER3_IRQHandler, Dummy_Handler + +.weak USBD_IRQHandler +.thumb_set USBD_IRQHandler, Dummy_Handler + +/************************************************************************************ + * Reset Handler Extensions * + ************************************************************************************/ + + .extern Reset_Handler + .global nRFInitialize + .extern afterInitialize + + .thumb_func +nRFInitialize: + b afterInitialize + + +/************************************************************************************ + * Vector Table * + ************************************************************************************/ + + .section .vectors, "ax" + .align 0 + .global _vectors + .extern __stack_end__ + +_vectors: + .word __stack_end__ + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemoryManagement_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word SVC_Handler + .word DebugMon_Handler + .word 0 /*Reserved */ + .word PendSV_Handler + .word SysTick_Handler + +/* External Interrupts */ + .word POWER_CLOCK_IRQHandler + .word RADIO_IRQHandler + .word UARTE0_UART0_IRQHandler + .word SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler + .word SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler + .word 0 /*Reserved */ + .word GPIOTE_IRQHandler + .word 0 /*Reserved */ + .word TIMER0_IRQHandler + .word TIMER1_IRQHandler + .word TIMER2_IRQHandler + .word RTC0_IRQHandler + .word TEMP_IRQHandler + .word RNG_IRQHandler + .word ECB_IRQHandler + .word CCM_AAR_IRQHandler + .word WDT_IRQHandler + .word RTC1_IRQHandler + .word QDEC_IRQHandler + .word COMP_IRQHandler + .word SWI0_EGU0_IRQHandler + .word SWI1_EGU1_IRQHandler + .word SWI2_EGU2_IRQHandler + .word SWI3_EGU3_IRQHandler + .word SWI4_EGU4_IRQHandler + .word SWI5_EGU5_IRQHandler + .word TIMER3_IRQHandler + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word USBD_IRQHandler + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ +_vectors_end: + +#ifdef VECTORS_IN_RAM + .section .vectors_ram, "ax" + .align 0 + .global _vectors_ram + +_vectors_ram: + .space _vectors_end - _vectors, 0 +#endif diff --git a/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf_common.S b/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf_common.S new file mode 100644 index 000000000..f7ede0a0c --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf_common.S @@ -0,0 +1,193 @@ +/*********************************************************************************** + * SEGGER Microcontroller GmbH * + * The Embedded Experts * + *********************************************************************************** + * * + * (c) 2014 - 2018 SEGGER Microcontroller GmbH * + * * + * www.segger.com Support: support@segger.com * + * * + *********************************************************************************** + * * + * All rights reserved. * + * * + * Redistribution and use in source and binary forms, with or * + * without modification, are permitted provided that the following * + * conditions are met: * + * * + * - Redistributions of source code must retain the above copyright * + * notice, this list of conditions and the following disclaimer. * + * * + * - Neither the name of SEGGER Microcontroller GmbH * + * nor the names of its contributors may be used to endorse or * + * promote products derived from this software without specific * + * prior written permission. * + * * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * + * DISCLAIMED. * + * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * + * DAMAGE. * + * * + *********************************************************************************** + * * + * This file has been modified by Nordic Semiconductor: * + * To separate out device-specific data * + * * + ***********************************************************************************/ + +/************************************************************************************ + * Preprocessor Definitions * + * ------------------------ * + * NO_FPU_ENABLE * + * * + * If defined, FPU will not be enabled. * + * * + * NO_STACK_INIT * + * * + * If defined, the stack pointer will not be initialised. * + * * + * NO_SYSTEM_INIT * + * * + * If defined, the SystemInit() function will not be called. By default * + * SystemInit() is called after reset to enable the clocks and memories to * + * be initialised prior to any C startup initialisation. * + * * + * NO_VTOR_CONFIG * + * * + * If defined, the vector table offset register will not be configured. * + * * + * MEMORY_INIT * + * * + * If defined, the MemoryInit() function will be called. By default * + * MemoryInit() is called after SystemInit() to enable an external memory * + * controller. * + * * + * STACK_INIT_VAL * + * * + * If defined, specifies the initial stack pointer value. If undefined, * + * the stack pointer will be initialised to point to the end of the * + * RAM segment. * + * * + * VECTORS_IN_RAM * + * * + * If defined, the exception vectors will be copied from Flash to RAM. * + * * + ************************************************************************************/ + + .syntax unified + + .global Reset_Handler +#ifdef INITIALIZE_USER_SECTIONS + .global InitializeUserMemorySections +#endif + .extern _vectors + .extern nRFInitialize + .global afterInitialize + + .section .init, "ax" + .thumb_func + + .equ VTOR_REG, 0xE000ED08 + .equ FPU_CPACR_REG, 0xE000ED88 + +#ifndef STACK_INIT_VAL +#define STACK_INIT_VAL __RAM1_segment_end__ +#endif + +Reset_Handler: + + /* Perform prestart tasks. */ + b nRFInitialize + +.thumb_func +afterInitialize: + +#ifndef NO_STACK_INIT + /* Initialise main stack */ + ldr r0, =STACK_INIT_VAL + ldr r1, =0x7 + bics r0, r1 + mov sp, r0 +#endif + +#ifndef NO_SYSTEM_INIT + /* Initialise system */ + ldr r0, =SystemInit + blx r0 +#endif + +#ifdef MEMORY_INIT + ldr r0, =MemoryInit + blx r0 +#endif + +#ifdef VECTORS_IN_RAM + /* Copy exception vectors into RAM */ + ldr r0, =__vectors_start__ + ldr r1, =__vectors_end__ + ldr r2, =__vectors_ram_start__ +1: + cmp r0, r1 + beq 2f + ldr r3, [r0] + str r3, [r2] + adds r0, r0, #4 + adds r2, r2, #4 + b 1b +2: +#endif + +#ifndef NO_VTOR_CONFIG + /* Configure vector table offset register */ + ldr r0, =VTOR_REG +#ifdef VECTORS_IN_RAM + ldr r1, =_vectors_ram +#else + ldr r1, =_vectors +#endif + str r1, [r0] +#endif + +#if (defined(__ARM_ARCH_FPV4_SP_D16__) || defined(__ARM_ARCH_FPV5_D16__)) && !defined(NO_FPU_ENABLE) + /* Enable FPU */ + ldr r0, =FPU_CPACR_REG + ldr r1, [r0] + orr r1, r1, #(0xF << 20) + str r1, [r0] + dsb + isb +#endif + + /* Jump to program start */ + b _start + +#ifdef INITIALIZE_USER_SECTIONS + .thumb_func +InitializeUserMemorySections: + ldr r0, =__start_nrf_sections + ldr r1, =__start_nrf_sections_run + ldr r2, =__end_nrf_sections_run + cmp r0, r1 + beq 2f + subs r2, r2, r1 + beq 2f +1: + ldrb r3, [r0] + adds r0, r0, #1 + strb r3, [r1] + adds r1, r1, #1 + subs r2, r2, #1 + bne 1b +2: + bx lr +#endif \ No newline at end of file diff --git a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config.h b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config.h new file mode 100644 index 000000000..4fc106a87 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config.h @@ -0,0 +1,2245 @@ +#ifndef NRFX_CONFIG_H__ +#define NRFX_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>>\n + +// nRF_Drivers + +// NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver +//========================================================== +#ifndef NRFX_CLOCK_ENABLED +#define NRFX_CLOCK_ENABLED 1 +#endif +// NRFX_CLOCK_CONFIG_LF_SRC - LF Clock Source + +// <0=> RC +// <1=> XTAL +// <2=> Synth +// <131073=> External Low Swing +// <196609=> External Full Swing + +#ifndef NRFX_CLOCK_CONFIG_LF_SRC +#define NRFX_CLOCK_CONFIG_LF_SRC 1 +#endif + +// NRFX_CLOCK_CONFIG_LF_CAL_ENABLED - Enables LF Clock Calibration Support + +#ifndef NRFX_CLOCK_CONFIG_LF_CAL_ENABLED +#define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 +#endif + +// NRFX_CLOCK_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_CLOCK_CONFIG_IRQ_PRIORITY +#define NRFX_CLOCK_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED +#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_CLOCK_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL +#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_CLOCK_CONFIG_INFO_COLOR +#define NRFX_CLOCK_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR +#define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_COMP_ENABLED - nrfx_comp - COMP peripheral driver +//========================================================== +#ifndef NRFX_COMP_ENABLED +#define NRFX_COMP_ENABLED 1 +#endif +// NRFX_COMP_CONFIG_REF - Reference voltage + +// <0=> Internal 1.2V +// <1=> Internal 1.8V +// <2=> Internal 2.4V +// <4=> VDD +// <7=> ARef + +#ifndef NRFX_COMP_CONFIG_REF +#define NRFX_COMP_CONFIG_REF 1 +#endif + +// NRFX_COMP_CONFIG_MAIN_MODE - Main mode + +// <0=> Single ended +// <1=> Differential + +#ifndef NRFX_COMP_CONFIG_MAIN_MODE +#define NRFX_COMP_CONFIG_MAIN_MODE 0 +#endif + +// NRFX_COMP_CONFIG_SPEED_MODE - Speed mode + +// <0=> Low power +// <1=> Normal +// <2=> High speed + +#ifndef NRFX_COMP_CONFIG_SPEED_MODE +#define NRFX_COMP_CONFIG_SPEED_MODE 2 +#endif + +// NRFX_COMP_CONFIG_HYST - Hystheresis + +// <0=> No +// <1=> 50mV + +#ifndef NRFX_COMP_CONFIG_HYST +#define NRFX_COMP_CONFIG_HYST 0 +#endif + +// NRFX_COMP_CONFIG_ISOURCE - Current Source + +// <0=> Off +// <1=> 2.5 uA +// <2=> 5 uA +// <3=> 10 uA + +#ifndef NRFX_COMP_CONFIG_ISOURCE +#define NRFX_COMP_CONFIG_ISOURCE 0 +#endif + +// NRFX_COMP_CONFIG_INPUT - Analog input + +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_COMP_CONFIG_INPUT +#define NRFX_COMP_CONFIG_INPUT 0 +#endif + +// NRFX_COMP_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_COMP_CONFIG_IRQ_PRIORITY +#define NRFX_COMP_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_COMP_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_COMP_CONFIG_LOG_ENABLED +#define NRFX_COMP_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_COMP_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_COMP_CONFIG_LOG_LEVEL +#define NRFX_COMP_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_COMP_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_COMP_CONFIG_INFO_COLOR +#define NRFX_COMP_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_COMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_COMP_CONFIG_DEBUG_COLOR +#define NRFX_COMP_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver +//========================================================== +#ifndef NRFX_GPIOTE_ENABLED +#define NRFX_GPIOTE_ENABLED 1 +#endif +// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS +#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 +#endif + +// NRFX_GPIOTE_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_GPIOTE_CONFIG_IRQ_PRIORITY +#define NRFX_GPIOTE_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED +#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_GPIOTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL +#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR +#define NRFX_GPIOTE_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR +#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_I2S_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_I2S_CONFIG_LOG_ENABLED +#define NRFX_I2S_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_I2S_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_I2S_CONFIG_LOG_LEVEL +#define NRFX_I2S_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_I2S_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_I2S_CONFIG_INFO_COLOR +#define NRFX_I2S_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_I2S_CONFIG_DEBUG_COLOR +#define NRFX_I2S_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver +//========================================================== +#ifndef NRFX_NVMC_ENABLED +#define NRFX_NVMC_ENABLED 1 +#endif + +// + +// NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver +//========================================================== +#ifndef NRFX_POWER_ENABLED +#define NRFX_POWER_ENABLED 1 +#endif +// NRFX_POWER_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_POWER_CONFIG_IRQ_PRIORITY +#define NRFX_POWER_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_POWER_CONFIG_DEFAULT_DCDCEN - The default configuration of main DCDC regulator + + +// This settings means only that components for DCDC regulator are installed and it can be enabled. + +#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCEN +#define NRFX_POWER_CONFIG_DEFAULT_DCDCEN 0 +#endif + +// NRFX_POWER_CONFIG_DEFAULT_DCDCENHV - The default configuration of High Voltage DCDC regulator + + +// This settings means only that components for DCDC regulator are installed and it can be enabled. + +#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCENHV +#define NRFX_POWER_CONFIG_DEFAULT_DCDCENHV 0 +#endif + +// + +// NRFX_PPI_ENABLED - nrfx_ppi - PPI peripheral allocator +//========================================================== +#ifndef NRFX_PPI_ENABLED +#define NRFX_PPI_ENABLED 1 +#endif +// NRFX_PPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PPI_CONFIG_LOG_ENABLED +#define NRFX_PPI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_PPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PPI_CONFIG_LOG_LEVEL +#define NRFX_PPI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_PPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PPI_CONFIG_INFO_COLOR +#define NRFX_PPI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PPI_CONFIG_DEBUG_COLOR +#define NRFX_PPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_PRS_ENABLED - nrfx_prs - Peripheral Resource Sharing module +//========================================================== +#ifndef NRFX_PRS_ENABLED +#define NRFX_PRS_ENABLED 1 +#endif +// NRFX_PRS_BOX_0_ENABLED - Enables box 0 in the module. + + +#ifndef NRFX_PRS_BOX_0_ENABLED +#define NRFX_PRS_BOX_0_ENABLED 1 +#endif + +// NRFX_PRS_BOX_1_ENABLED - Enables box 1 in the module. + + +#ifndef NRFX_PRS_BOX_1_ENABLED +#define NRFX_PRS_BOX_1_ENABLED 1 +#endif + +// NRFX_PRS_BOX_2_ENABLED - Enables box 2 in the module. + + +#ifndef NRFX_PRS_BOX_2_ENABLED +#define NRFX_PRS_BOX_2_ENABLED 1 +#endif + +// NRFX_PRS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PRS_CONFIG_LOG_ENABLED +#define NRFX_PRS_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_PRS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PRS_CONFIG_LOG_LEVEL +#define NRFX_PRS_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_PRS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PRS_CONFIG_INFO_COLOR +#define NRFX_PRS_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_PRS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PRS_CONFIG_DEBUG_COLOR +#define NRFX_PRS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_QDEC_ENABLED - nrfx_qdec - QDEC peripheral driver +//========================================================== +#ifndef NRFX_QDEC_ENABLED +#define NRFX_QDEC_ENABLED 1 +#endif +// NRFX_QDEC_CONFIG_REPORTPER - Report period + +// <0=> 10 Samples +// <1=> 40 Samples +// <2=> 80 Samples +// <3=> 120 Samples +// <4=> 160 Samples +// <5=> 200 Samples +// <6=> 240 Samples +// <7=> 280 Samples + +#ifndef NRFX_QDEC_CONFIG_REPORTPER +#define NRFX_QDEC_CONFIG_REPORTPER 0 +#endif + +// NRFX_QDEC_CONFIG_SAMPLEPER - Sample period + +// <0=> 128 us +// <1=> 256 us +// <2=> 512 us +// <3=> 1024 us +// <4=> 2048 us +// <5=> 4096 us +// <6=> 8192 us +// <7=> 16384 us + +#ifndef NRFX_QDEC_CONFIG_SAMPLEPER +#define NRFX_QDEC_CONFIG_SAMPLEPER 7 +#endif + +// NRFX_QDEC_CONFIG_PIO_A - A pin <0-31> + + +#ifndef NRFX_QDEC_CONFIG_PIO_A +#define NRFX_QDEC_CONFIG_PIO_A 31 +#endif + +// NRFX_QDEC_CONFIG_PIO_B - B pin <0-31> + + +#ifndef NRFX_QDEC_CONFIG_PIO_B +#define NRFX_QDEC_CONFIG_PIO_B 31 +#endif + +// NRFX_QDEC_CONFIG_PIO_LED - LED pin <0-31> + + +#ifndef NRFX_QDEC_CONFIG_PIO_LED +#define NRFX_QDEC_CONFIG_PIO_LED 31 +#endif + +// NRFX_QDEC_CONFIG_LEDPRE - LED pre +#ifndef NRFX_QDEC_CONFIG_LEDPRE +#define NRFX_QDEC_CONFIG_LEDPRE 511 +#endif + +// NRFX_QDEC_CONFIG_LEDPOL - LED polarity + +// <0=> Active low +// <1=> Active high + +#ifndef NRFX_QDEC_CONFIG_LEDPOL +#define NRFX_QDEC_CONFIG_LEDPOL 1 +#endif + +// NRFX_QDEC_CONFIG_DBFEN - Debouncing enable + + +#ifndef NRFX_QDEC_CONFIG_DBFEN +#define NRFX_QDEC_CONFIG_DBFEN 0 +#endif + +// NRFX_QDEC_CONFIG_SAMPLE_INTEN - Sample ready interrupt enable + + +#ifndef NRFX_QDEC_CONFIG_SAMPLE_INTEN +#define NRFX_QDEC_CONFIG_SAMPLE_INTEN 0 +#endif + +// NRFX_QDEC_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_QDEC_CONFIG_IRQ_PRIORITY +#define NRFX_QDEC_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_QDEC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED +#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_QDEC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL +#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_QDEC_CONFIG_INFO_COLOR +#define NRFX_QDEC_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_QDEC_CONFIG_DEBUG_COLOR +#define NRFX_QDEC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_RNG_ENABLED - nrfx_rng - RNG peripheral driver +//========================================================== +#ifndef NRFX_RNG_ENABLED +#define NRFX_RNG_ENABLED 1 +#endif +// NRFX_RNG_CONFIG_ERROR_CORRECTION - Error correction + + +#ifndef NRFX_RNG_CONFIG_ERROR_CORRECTION +#define NRFX_RNG_CONFIG_ERROR_CORRECTION 1 +#endif + +// NRFX_RNG_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_RNG_CONFIG_IRQ_PRIORITY +#define NRFX_RNG_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_RNG_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_RNG_CONFIG_LOG_ENABLED +#define NRFX_RNG_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_RNG_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_RNG_CONFIG_LOG_LEVEL +#define NRFX_RNG_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_RNG_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RNG_CONFIG_INFO_COLOR +#define NRFX_RNG_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_RNG_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RNG_CONFIG_DEBUG_COLOR +#define NRFX_RNG_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver +//========================================================== +#ifndef NRFX_RTC_ENABLED +#define NRFX_RTC_ENABLED 1 +#endif +// NRFX_RTC0_ENABLED - Enable RTC0 instance + + +#ifndef NRFX_RTC0_ENABLED +#define NRFX_RTC0_ENABLED 1 +#endif + +// NRFX_RTC1_ENABLED - Enable RTC1 instance + + +#ifndef NRFX_RTC1_ENABLED +#define NRFX_RTC1_ENABLED 1 +#endif + + +// NRFX_RTC_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt +#ifndef NRFX_RTC_MAXIMUM_LATENCY_US +#define NRFX_RTC_MAXIMUM_LATENCY_US 2000 +#endif + +// NRFX_RTC_DEFAULT_CONFIG_FREQUENCY - Frequency <16-32768> + + +#ifndef NRFX_RTC_DEFAULT_CONFIG_FREQUENCY +#define NRFX_RTC_DEFAULT_CONFIG_FREQUENCY 32768 +#endif + +// NRFX_RTC_DEFAULT_CONFIG_RELIABLE - Ensures safe compare event triggering + + +#ifndef NRFX_RTC_DEFAULT_CONFIG_RELIABLE +#define NRFX_RTC_DEFAULT_CONFIG_RELIABLE 0 +#endif + +// NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_RTC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_RTC_CONFIG_LOG_ENABLED +#define NRFX_RTC_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_RTC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_RTC_CONFIG_LOG_LEVEL +#define NRFX_RTC_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_RTC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RTC_CONFIG_INFO_COLOR +#define NRFX_RTC_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RTC_CONFIG_DEBUG_COLOR +#define NRFX_RTC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver +//========================================================== +#ifndef NRFX_SPIM_ENABLED +#define NRFX_SPIM_ENABLED 1 +#endif +// NRFX_SPIM0_ENABLED - Enable SPIM0 instance + + +#ifndef NRFX_SPIM0_ENABLED +#define NRFX_SPIM0_ENABLED 1 +#endif + +// NRFX_SPIM1_ENABLED - Enable SPIM1 instance + + +#ifndef NRFX_SPIM1_ENABLED +#define NRFX_SPIM1_ENABLED 1 +#endif + +// NRFX_SPIM_MISO_PULL_CFG - MISO pin pull configuration. + +// <0=> NRF_GPIO_PIN_NOPULL +// <1=> NRF_GPIO_PIN_PULLDOWN +// <3=> NRF_GPIO_PIN_PULLUP + +#ifndef NRFX_SPIM_MISO_PULL_CFG +#define NRFX_SPIM_MISO_PULL_CFG 1 +#endif + +// NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_SPIM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED +#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPIM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL +#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPIM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIM_CONFIG_INFO_COLOR +#define NRFX_SPIM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR +#define NRFX_SPIM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver +//========================================================== +#ifndef NRFX_SPIS_ENABLED +#define NRFX_SPIS_ENABLED 1 +#endif +// NRFX_SPIS0_ENABLED - Enable SPIS0 instance + + +#ifndef NRFX_SPIS0_ENABLED +#define NRFX_SPIS0_ENABLED 1 +#endif + +// NRFX_SPIS1_ENABLED - Enable SPIS1 instance + + +#ifndef NRFX_SPIS1_ENABLED +#define NRFX_SPIS1_ENABLED 1 +#endif + +// NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> + + +#ifndef NRFX_SPIS_DEFAULT_DEF +#define NRFX_SPIS_DEFAULT_DEF 255 +#endif + +// NRFX_SPIS_DEFAULT_ORC - SPIS default ORC character <0-255> + + +#ifndef NRFX_SPIS_DEFAULT_ORC +#define NRFX_SPIS_DEFAULT_ORC 255 +#endif + +// NRFX_SPIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED +#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL +#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIS_CONFIG_INFO_COLOR +#define NRFX_SPIS_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR +#define NRFX_SPIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver +//========================================================== +#ifndef NRFX_SPI_ENABLED +#define NRFX_SPI_ENABLED 1 +#endif +// NRFX_SPI0_ENABLED - Enable SPI0 instance + + +#ifndef NRFX_SPI0_ENABLED +#define NRFX_SPI0_ENABLED 1 +#endif + +// NRFX_SPI1_ENABLED - Enable SPI1 instance + + +#ifndef NRFX_SPI1_ENABLED +#define NRFX_SPI1_ENABLED 1 +#endif + +// NRFX_SPI_MISO_PULL_CFG - MISO pin pull configuration. + +// <0=> NRF_GPIO_PIN_NOPULL +// <1=> NRF_GPIO_PIN_PULLDOWN +// <3=> NRF_GPIO_PIN_PULLUP + +#ifndef NRFX_SPI_MISO_PULL_CFG +#define NRFX_SPI_MISO_PULL_CFG 1 +#endif + +// NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_SPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPI_CONFIG_LOG_ENABLED +#define NRFX_SPI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPI_CONFIG_LOG_LEVEL +#define NRFX_SPI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPI_CONFIG_INFO_COLOR +#define NRFX_SPI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPI_CONFIG_DEBUG_COLOR +#define NRFX_SPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SWI_ENABLED - nrfx_swi - SWI/EGU peripheral allocator +//========================================================== +#ifndef NRFX_SWI_ENABLED +#define NRFX_SWI_ENABLED 1 +#endif +// NRFX_EGU_ENABLED - Enable EGU support + + +#ifndef NRFX_EGU_ENABLED +#define NRFX_EGU_ENABLED 1 +#endif + +// NRFX_SWI0_DISABLED - Exclude SWI0 from being utilized by the driver + + +#ifndef NRFX_SWI0_DISABLED +#define NRFX_SWI0_DISABLED 0 +#endif + +// NRFX_SWI1_DISABLED - Exclude SWI1 from being utilized by the driver + + +#ifndef NRFX_SWI1_DISABLED +#define NRFX_SWI1_DISABLED 0 +#endif + +// NRFX_SWI2_DISABLED - Exclude SWI2 from being utilized by the driver + + +#ifndef NRFX_SWI2_DISABLED +#define NRFX_SWI2_DISABLED 0 +#endif + +// NRFX_SWI3_DISABLED - Exclude SWI3 from being utilized by the driver + + +#ifndef NRFX_SWI3_DISABLED +#define NRFX_SWI3_DISABLED 0 +#endif + +// NRFX_SWI4_DISABLED - Exclude SWI4 from being utilized by the driver + + +#ifndef NRFX_SWI4_DISABLED +#define NRFX_SWI4_DISABLED 0 +#endif + +// NRFX_SWI5_DISABLED - Exclude SWI5 from being utilized by the driver + + +#ifndef NRFX_SWI5_DISABLED +#define NRFX_SWI5_DISABLED 0 +#endif + +// NRFX_SWI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SWI_CONFIG_LOG_ENABLED +#define NRFX_SWI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SWI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SWI_CONFIG_LOG_LEVEL +#define NRFX_SWI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SWI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SWI_CONFIG_INFO_COLOR +#define NRFX_SWI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SWI_CONFIG_DEBUG_COLOR +#define NRFX_SWI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SYSTICK_ENABLED - nrfx_systick - ARM(R) SysTick driver + + +#ifndef NRFX_SYSTICK_ENABLED +#define NRFX_SYSTICK_ENABLED 1 +#endif + +// NRFX_TEMP_ENABLED - nrfx_temp - TEMP peripheral driver +//========================================================== +#ifndef NRFX_TEMP_ENABLED +#define NRFX_TEMP_ENABLED 1 +#endif + +// NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// + +// NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver +//========================================================== +#ifndef NRFX_TIMER_ENABLED +#define NRFX_TIMER_ENABLED 1 +#endif +// NRFX_TIMER0_ENABLED - Enable TIMER0 instance + + +#ifndef NRFX_TIMER0_ENABLED +#define NRFX_TIMER0_ENABLED 1 +#endif + +// NRFX_TIMER1_ENABLED - Enable TIMER1 instance + + +#ifndef NRFX_TIMER1_ENABLED +#define NRFX_TIMER1_ENABLED 1 +#endif + +// NRFX_TIMER2_ENABLED - Enable TIMER2 instance + + +#ifndef NRFX_TIMER2_ENABLED +#define NRFX_TIMER2_ENABLED 1 +#endif + +// NRFX_TIMER3_ENABLED - Enable TIMER3 instance + + +#ifndef NRFX_TIMER3_ENABLED +#define NRFX_TIMER3_ENABLED 1 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY - Timer frequency if in Timer mode + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 kHz +// <8=> 62.5 kHz +// <9=> 31.25 kHz + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_MODE - Timer mode or operation + +// <0=> Timer +// <1=> Counter + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_MODE +#define NRFX_TIMER_DEFAULT_CONFIG_MODE 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH - Timer counter bit width + +// <0=> 16 bit +// <1=> 8 bit +// <2=> 24 bit +// <3=> 32 bit + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH +#define NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED +#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TIMER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL +#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TIMER_CONFIG_INFO_COLOR +#define NRFX_TIMER_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR +#define NRFX_TIMER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TWIM_ENABLED - nrfx_twim - TWIM peripheral driver +//========================================================== +#ifndef NRFX_TWIM_ENABLED +#define NRFX_TWIM_ENABLED 1 +#endif +// NRFX_TWIM0_ENABLED - Enable TWIM0 instance + + +#ifndef NRFX_TWIM0_ENABLED +#define NRFX_TWIM0_ENABLED 1 +#endif + +// NRFX_TWIM1_ENABLED - Enable TWIM1 instance + + +#ifndef NRFX_TWIM1_ENABLED +#define NRFX_TWIM1_ENABLED 1 +#endif + +// NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY - Frequency + +// <26738688=> 100k +// <67108864=> 250k +// <104857600=> 400k + +#ifndef NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY 26738688 +#endif + +// NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit + + +#ifndef NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 +#endif + +// NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_TWIM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED +#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWIM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL +#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWIM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIM_CONFIG_INFO_COLOR +#define NRFX_TWIM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR +#define NRFX_TWIM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TWIS_ENABLED - nrfx_twis - TWIS peripheral driver +//========================================================== +#ifndef NRFX_TWIS_ENABLED +#define NRFX_TWIS_ENABLED 1 +#endif +// NRFX_TWIS0_ENABLED - Enable TWIS0 instance + + +#ifndef NRFX_TWIS0_ENABLED +#define NRFX_TWIS0_ENABLED 1 +#endif + +// NRFX_TWIS1_ENABLED - Enable TWIS1 instance + + +#ifndef NRFX_TWIS1_ENABLED +#define NRFX_TWIS1_ENABLED 1 +#endif + +// NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once + + +// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. + +#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +// NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode + + +// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. + +#ifndef NRFX_TWIS_NO_SYNC_MODE +#define NRFX_TWIS_NO_SYNC_MODE 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_ADDR0 - Address0 +#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR0 +#define NRFX_TWIS_DEFAULT_CONFIG_ADDR0 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_ADDR1 - Address1 +#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR1 +#define NRFX_TWIS_DEFAULT_CONFIG_ADDR1 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL - SCL pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL +#define NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL - SDA pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL +#define NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED +#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL +#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIS_CONFIG_INFO_COLOR +#define NRFX_TWIS_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR +#define NRFX_TWIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TWI_ENABLED - nrfx_twi - TWI peripheral driver +//========================================================== +#ifndef NRFX_TWI_ENABLED +#define NRFX_TWI_ENABLED 1 +#endif +// NRFX_TWI0_ENABLED - Enable TWI0 instance + + +#ifndef NRFX_TWI0_ENABLED +#define NRFX_TWI0_ENABLED 1 +#endif + +// NRFX_TWI1_ENABLED - Enable TWI1 instance + + +#ifndef NRFX_TWI1_ENABLED +#define NRFX_TWI1_ENABLED 1 +#endif + +// NRFX_TWI_DEFAULT_CONFIG_FREQUENCY - Frequency + +// <26738688=> 100k +// <67108864=> 250k +// <104857600=> 400k + +#ifndef NRFX_TWI_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TWI_DEFAULT_CONFIG_FREQUENCY 26738688 +#endif + +// NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit + + +#ifndef NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#define NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 +#endif + +// NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_TWI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWI_CONFIG_LOG_ENABLED +#define NRFX_TWI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWI_CONFIG_LOG_LEVEL +#define NRFX_TWI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWI_CONFIG_INFO_COLOR +#define NRFX_TWI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWI_CONFIG_DEBUG_COLOR +#define NRFX_TWI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver +//========================================================== +#ifndef NRFX_UARTE_ENABLED +#define NRFX_UARTE_ENABLED 1 +#endif +// NRFX_UARTE0_ENABLED - Enable UARTE0 instance +#ifndef NRFX_UARTE0_ENABLED +#define NRFX_UARTE0_ENABLED 1 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_HWFC - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_HWFC +#define NRFX_UARTE_DEFAULT_CONFIG_HWFC 0 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_PARITY - Parity + +// <0=> Excluded +// <14=> Included + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_PARITY +#define NRFX_UARTE_DEFAULT_CONFIG_PARITY 0 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3862528=> 14400 baud +// <5152768=> 19200 baud +// <7716864=> 28800 baud +// <8388608=> 31250 baud +// <10289152=> 38400 baud +// <15007744=> 56000 baud +// <15400960=> 57600 baud +// <20615168=> 76800 baud +// <30801920=> 115200 baud +// <61865984=> 230400 baud +// <67108864=> 250000 baud +// <121634816=> 460800 baud +// <251658240=> 921600 baud +// <268435456=> 1000000 baud + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE +#define NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE 30801920 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_UARTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED +#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_UARTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL +#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_UARTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UARTE_CONFIG_INFO_COLOR +#define NRFX_UARTE_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_UARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR +#define NRFX_UARTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_UART_ENABLED - nrfx_uart - UART peripheral driver +//========================================================== +#ifndef NRFX_UART_ENABLED +#define NRFX_UART_ENABLED 1 +#endif +// NRFX_UART0_ENABLED - Enable UART0 instance +#ifndef NRFX_UART0_ENABLED +#define NRFX_UART0_ENABLED 1 +#endif + +// NRFX_UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef NRFX_UART_DEFAULT_CONFIG_HWFC +#define NRFX_UART_DEFAULT_CONFIG_HWFC 0 +#endif + +// NRFX_UART_DEFAULT_CONFIG_PARITY - Parity + +// <0=> Excluded +// <14=> Included + +#ifndef NRFX_UART_DEFAULT_CONFIG_PARITY +#define NRFX_UART_DEFAULT_CONFIG_PARITY 0 +#endif + +// NRFX_UART_DEFAULT_CONFIG_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3866624=> 14400 baud +// <5152768=> 19200 baud +// <7729152=> 28800 baud +// <8388608=> 31250 baud +// <10309632=> 38400 baud +// <15007744=> 56000 baud +// <15462400=> 57600 baud +// <20615168=> 76800 baud +// <30924800=> 115200 baud +// <61845504=> 230400 baud +// <67108864=> 250000 baud +// <123695104=> 460800 baud +// <247386112=> 921600 baud +// <268435456=> 1000000 baud + +#ifndef NRFX_UART_DEFAULT_CONFIG_BAUDRATE +#define NRFX_UART_DEFAULT_CONFIG_BAUDRATE 30924800 +#endif + +// NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_UART_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_UART_CONFIG_LOG_ENABLED +#define NRFX_UART_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_UART_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_UART_CONFIG_LOG_LEVEL +#define NRFX_UART_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_UART_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UART_CONFIG_INFO_COLOR +#define NRFX_UART_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UART_CONFIG_DEBUG_COLOR +#define NRFX_UART_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_USBD_ENABLED - nrfx_usbd - USBD peripheral driver +//========================================================== +#ifndef NRFX_USBD_ENABLED +#define NRFX_USBD_ENABLED 1 +#endif +// NRFX_USBD_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_USBD_CONFIG_IRQ_PRIORITY +#define NRFX_USBD_CONFIG_IRQ_PRIORITY 7 +#endif + +// USBD_CONFIG_DMASCHEDULER_ISO_BOOST - Give priority to isochronous transfers + +// This option gives priority to isochronous transfers. +// Enabling it assures that isochronous transfers are always processed, +// even if multiple other transfers are pending. +// Isochronous endpoints are prioritized before the usbd_dma_scheduler_algorithm +// function is called, so the option is independent of the algorithm chosen. + +#ifndef NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST +#define NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST 1 +#endif + +// USBD_CONFIG_ISO_IN_ZLP - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready + + +// If set, ISO IN endpoint will respond to an IN token with ZLP when no data is ready to be sent. +// Else, there will be no response. + +#ifndef NRFX_USBD_CONFIG_ISO_IN_ZLP +#define NRFX_USBD_CONFIG_ISO_IN_ZLP 0 +#endif + +// NRFX_USBD_CONFIG_LOG_ENABLED - Enable logging in the module +//========================================================== +#ifndef NRFX_USBD_CONFIG_LOG_ENABLED +#define NRFX_USBD_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_USBD_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_USBD_CONFIG_LOG_LEVEL +#define NRFX_USBD_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_USBD_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_USBD_CONFIG_INFO_COLOR +#define NRFX_USBD_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_USBD_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_USBD_CONFIG_DEBUG_COLOR +#define NRFX_USBD_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver +//========================================================== +#ifndef NRFX_WDT_ENABLED +#define NRFX_WDT_ENABLED 1 +#endif +// NRFX_WDT_CONFIG_BEHAVIOUR - WDT behavior in CPU SLEEP or HALT mode + +// <1=> Run in SLEEP, Pause in HALT +// <8=> Pause in SLEEP, Run in HALT +// <9=> Run in SLEEP and HALT +// <0=> Pause in SLEEP and HALT + +#ifndef NRFX_WDT_CONFIG_BEHAVIOUR +#define NRFX_WDT_CONFIG_BEHAVIOUR 1 +#endif + +// NRFX_WDT_CONFIG_RELOAD_VALUE - Reload value <15-4294967295> + + +#ifndef NRFX_WDT_CONFIG_RELOAD_VALUE +#define NRFX_WDT_CONFIG_RELOAD_VALUE 2000 +#endif + +// NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver + +// <0=> Include WDT IRQ handling +// <1=> Remove WDT IRQ handling + +#ifndef NRFX_WDT_CONFIG_NO_IRQ +#define NRFX_WDT_CONFIG_NO_IRQ 0 +#endif + +// NRFX_WDT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_WDT_CONFIG_IRQ_PRIORITY +#define NRFX_WDT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_WDT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_WDT_CONFIG_LOG_ENABLED +#define NRFX_WDT_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_WDT_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_WDT_CONFIG_LOG_LEVEL +#define NRFX_WDT_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_WDT_CONFIG_INFO_COLOR +#define NRFX_WDT_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_WDT_CONFIG_DEBUG_COLOR +#define NRFX_WDT_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// + +#endif // NRFX_CONFIG_H__ From 2dc1f5474db4c0e1fb5c039059a7e728fe8c398a Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 19 Jun 2021 23:55:55 -0500 Subject: [PATCH 399/617] nrf52820_hic: import initial memory map --- source/hic_hal/nordic/nrf52820/daplink_addr.h | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 source/hic_hal/nordic/nrf52820/daplink_addr.h diff --git a/source/hic_hal/nordic/nrf52820/daplink_addr.h b/source/hic_hal/nordic/nrf52820/daplink_addr.h new file mode 100644 index 000000000..a472ac365 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/daplink_addr.h @@ -0,0 +1,76 @@ +/** + * DAPLink Interface Firmware + * Copyright (c) 2021 Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DAPLINK_ADDR_H +#define DAPLINK_ADDR_H + +/* Device sizes */ + +#define DAPLINK_ROM_START 0x00000000 +#define DAPLINK_ROM_SIZE 0x00040000 + +#define DAPLINK_RAM_START 0x20000000 +#define DAPLINK_RAM_SIZE 0x00008000 // 32 KiB + +/* ROM sizes */ + +#define DAPLINK_ROM_BL_START 0x00000000 +#define DAPLINK_ROM_BL_SIZE 0x00010000 // 64 KiB bootloader + +#define DAPLINK_ROM_IF_START 0x00010000 +#define DAPLINK_ROM_IF_SIZE 0x0002F000 + +#define DAPLINK_ROM_CONFIG_USER_START 0x0003F000 +#define DAPLINK_ROM_CONFIG_USER_SIZE 0x00001000 + +/* RAM sizes */ + +#define DAPLINK_RAM_APP_START 0x20000000 +#define DAPLINK_RAM_APP_SIZE 0x00007F00 + +#define DAPLINK_RAM_SHARED_START 0x20007F00 +#define DAPLINK_RAM_SHARED_SIZE 0x00000100 + +/* Flash Programming Info */ + +#define DAPLINK_SECTOR_SIZE 0x00001000 +#define DAPLINK_MIN_WRITE_SIZE 0x00001000 + +/* Current build */ + +#if defined(DAPLINK_BL) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_BL_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_IF_SIZE + +#elif defined(DAPLINK_IF) + +#define DAPLINK_ROM_APP_START DAPLINK_ROM_IF_START +#define DAPLINK_ROM_APP_SIZE DAPLINK_ROM_IF_SIZE +#define DAPLINK_ROM_UPDATE_START DAPLINK_ROM_BL_START +#define DAPLINK_ROM_UPDATE_SIZE DAPLINK_ROM_BL_SIZE + +#else + +#error "Build must be either bootloader or interface" + +#endif + +#endif From 8f04fde4f43218857c8cad65361ba0d855d23e56 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sun, 20 Jun 2021 00:01:12 -0500 Subject: [PATCH 400/617] nrf52820_hic: import empty configuration and function stubs --- source/hic_hal/nordic/nrf52820/DAP_config.h | 456 ++++++++++++++ source/hic_hal/nordic/nrf52820/IO_Config.h | 52 ++ source/hic_hal/nordic/nrf52820/flash.c | 47 ++ source/hic_hal/nordic/nrf52820/gpio.c | 62 ++ source/hic_hal/nordic/nrf52820/read_uid.c | 30 + source/hic_hal/nordic/nrf52820/sdk.c | 29 + source/hic_hal/nordic/nrf52820/uart.c | 58 ++ source/hic_hal/nordic/nrf52820/usb_config.c | 563 ++++++++++++++++++ .../hic_hal/nordic/nrf52820/usbd_nrf52833.c | 343 +++++++++++ 9 files changed, 1640 insertions(+) create mode 100644 source/hic_hal/nordic/nrf52820/DAP_config.h create mode 100644 source/hic_hal/nordic/nrf52820/IO_Config.h create mode 100644 source/hic_hal/nordic/nrf52820/flash.c create mode 100644 source/hic_hal/nordic/nrf52820/gpio.c create mode 100644 source/hic_hal/nordic/nrf52820/read_uid.c create mode 100644 source/hic_hal/nordic/nrf52820/sdk.c create mode 100644 source/hic_hal/nordic/nrf52820/uart.c create mode 100644 source/hic_hal/nordic/nrf52820/usb_config.c create mode 100644 source/hic_hal/nordic/nrf52820/usbd_nrf52833.c diff --git a/source/hic_hal/nordic/nrf52820/DAP_config.h b/source/hic_hal/nordic/nrf52820/DAP_config.h new file mode 100644 index 000000000..59dc79f0c --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/DAP_config.h @@ -0,0 +1,456 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 1. December 2017 + * $Revision: V2.0.0 + * + * Project: CMSIS-DAP Configuration + * Title: DAP_config.h CMSIS-DAP Configuration File (Template) + * + *---------------------------------------------------------------------------*/ + +#ifndef __DAP_CONFIG_H__ +#define __DAP_CONFIG_H__ + + +//************************************************************************************************** +/** +\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information +\ingroup DAP_ConfigIO_gr +@{ +Provides definitions about the hardware and configuration of the Debug Unit. + +This information includes: + - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. + - Debug Unit Identification strings (Vendor, Product, Serial Number). + - Debug Unit communication packet size. + - Debug Access Port supported modes and settings (JTAG/SWD and SWO). + - Optional information about a connected Target Device (for Evaluation Boards). +*/ + +#ifdef _RTE_ +#include "RTE_Components.h" +#include CMSIS_device_header +#else +#include "device.h" // Debug Unit Cortex-M Processor Header File +#endif + +/// Processor Clock of the Cortex-M MCU used in the Debug Unit. +/// This value is used to calculate the SWD/JTAG clock speed. +#define CPU_CLOCK 100000000U ///< Specifies the CPU Clock in Hz. + +/// Number of processor cycles for I/O Port write operations. +/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O +/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors +/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses +/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be +/// required. +#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0. + +/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available. + +/// Indicate that JTAG communication mode is available at the Debug Port. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available. + +/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port. +/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255. +#define DAP_JTAG_DEV_CNT 8U ///< Maximum number of JTAG devices on scan chain. + +/// Default communication mode on the Debug Access Port. +/// Used for the command \ref DAP_Connect when Port Default mode is selected. +#define DAP_DEFAULT_PORT 1U ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG. + +/// Default communication speed on the Debug Access Port for SWD and JTAG mode. +/// Used to initialize the default SWD/JTAG clock frequency. +/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting. +#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz. + +/// Maximum Package Size for Command and Response data. +/// This configuration settings is used to optimize the communication performance with the +/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB, +/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB. +#define DAP_PACKET_SIZE 512U ///< Specifies Packet Size in bytes. + +/// Maximum Package Buffers for Command and Response data. +/// This configuration settings is used to optimize the communication performance with the +/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the +/// setting can be reduced (valid range is 1 .. 255). +#define DAP_PACKET_COUNT 8U ///< Specifies number of packets buffered. + +/// Indicate that UART Serial Wire Output (SWO) trace is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available. + +/// Maximum SWO UART Baudrate. +#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz. + +/// Indicate that Manchester Serial Wire Output (SWO) trace is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available. + +/// SWO Trace Buffer Size. +#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n). + +/// SWO Streaming Trace. +#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available. + +/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. +#define TIMESTAMP_CLOCK 100000000U ///< Timestamp clock in Hz (0 = timestamps not supported). + +/// Debug Unit is connected to fixed Target Device. +/// The Debug Unit may be part of an evaluation board and always connected to a fixed +/// known device. In this case a Device Vendor and Device Name string is stored which +/// may be used by the debugger or IDE to configure device parameters. +#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown; + +#if TARGET_DEVICE_FIXED +#define TARGET_DEVICE_VENDOR "ARM" ///< String indicating the Silicon Vendor +#define TARGET_DEVICE_NAME "Cortex-M4" ///< String indicating the Target Device +#endif + +/** Get Vendor ID string. +\param str Pointer to buffer to store the string. +\return String length. +*/ +__STATIC_INLINE uint8_t DAP_GetVendorString (char *str) { + (void)str; + return (0U); +} + +/** Get Product ID string. +\param str Pointer to buffer to store the string. +\return String length. +*/ +__STATIC_INLINE uint8_t DAP_GetProductString (char *str) { + (void)str; + return (0U); +} + +/** Get Serial Number string. +\param str Pointer to buffer to store the string. +\return String length. +*/ +__STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) { + (void)str; + return (0U); +} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access +\ingroup DAP_ConfigIO_gr +@{ + +Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode +and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug +interface of a device. The following I/O Pins are provided: + +JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode +---------------------------- | -------------------- | --------------------------------------------- +TCK: Test Clock | SWCLK: Clock | Output Push/Pull +TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data) +TDI: Test Data Input | | Output Push/Pull +TDO: Test Data Output | | Input +nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor +nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor + + +DAP Hardware I/O Pin Access Functions +------------------------------------- +The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to +these I/O Pins. + +For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only. +This functions are provided to achieve faster I/O that is possible with some advanced GPIO +peripherals that can independently write/read a single I/O pin without affecting any other pins +of the same I/O port. The following SWDIO I/O Pin functions are provided: + - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware. + - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware. + - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed. + - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed. +*/ + + +// Configure DAP I/O pins ------------------------------ + +/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET. +Configures the DAP Hardware I/O pins for JTAG mode: + - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level. + - TDO to input mode. +*/ +__STATIC_INLINE void PORT_JTAG_SETUP (void) { + ; +} + +/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET. +Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: + - SWCLK, SWDIO, nRESET to output mode and set to default high level. + - TDI, nTRST to HighZ mode (pins are unused in SWD mode). +*/ +__STATIC_INLINE void PORT_SWD_SETUP (void) { + ; +} + +/** Disable JTAG/SWD I/O Pins. +Disables the DAP Hardware I/O pins which configures: + - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode. +*/ +__STATIC_INLINE void PORT_OFF (void) { + ; +} + + +// SWCLK/TCK I/O pin ------------------------------------- + +/** SWCLK/TCK I/O pin: Get Input. +\return Current status of the SWCLK/TCK DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) { + return (0U); +} + +/** SWCLK/TCK I/O pin: Set Output to High. +Set the SWCLK/TCK DAP hardware I/O pin to high level. +*/ +__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) { + ; +} + +/** SWCLK/TCK I/O pin: Set Output to Low. +Set the SWCLK/TCK DAP hardware I/O pin to low level. +*/ +__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) { + ; +} + + +// SWDIO/TMS Pin I/O -------------------------------------- + +/** SWDIO/TMS I/O pin: Get Input. +\return Current status of the SWDIO/TMS DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) { + return (0U); +} + +/** SWDIO/TMS I/O pin: Set Output to High. +Set the SWDIO/TMS DAP hardware I/O pin to high level. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) { + ; +} + +/** SWDIO/TMS I/O pin: Set Output to Low. +Set the SWDIO/TMS DAP hardware I/O pin to low level. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) { + ; +} + +/** SWDIO I/O pin: Get Input (used in SWD mode only). +\return Current status of the SWDIO DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) { + return (0U); +} + +/** SWDIO I/O pin: Set Output (used in SWD mode only). +\param bit Output value for the SWDIO DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit) { + ; +} + +/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only). +Configure the SWDIO DAP hardware I/O pin to output mode. This function is +called prior \ref PIN_SWDIO_OUT function calls. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) { + ; +} + +/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). +Configure the SWDIO DAP hardware I/O pin to input mode. This function is +called prior \ref PIN_SWDIO_IN function calls. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) { + ; +} + + +// TDI Pin I/O --------------------------------------------- + +/** TDI I/O pin: Get Input. +\return Current status of the TDI DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_TDI_IN (void) { + return (0U); +} + +/** TDI I/O pin: Set Output. +\param bit Output value for the TDI DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE void PIN_TDI_OUT (uint32_t bit) { + ; +} + + +// TDO Pin I/O --------------------------------------------- + +/** TDO I/O pin: Get Input. +\return Current status of the TDO DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_TDO_IN (void) { + return (0U); +} + + +// nTRST Pin I/O ------------------------------------------- + +/** nTRST I/O pin: Get Input. +\return Current status of the nTRST DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN (void) { + return (0U); +} + +/** nTRST I/O pin: Set Output. +\param bit JTAG TRST Test Reset pin status: + - 0: issue a JTAG TRST Test Reset. + - 1: release JTAG TRST Test Reset. +*/ +__STATIC_FORCEINLINE void PIN_nTRST_OUT (uint32_t bit) { + ; +} + +// nRESET Pin I/O------------------------------------------ + +/** nRESET I/O pin: Get Input. +\return Current status of the nRESET DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN (void) { + return (0U); +} + +/** nRESET I/O pin: Set Output. +\param bit target device hardware reset pin status: + - 0: issue a device hardware reset. + - 1: release device hardware reset. +*/ +__STATIC_FORCEINLINE void PIN_nRESET_OUT (uint32_t bit) { + ; +} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs +\ingroup DAP_ConfigIO_gr +@{ + +CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit. + +It is recommended to provide the following LEDs for status indication: + - Connect LED: is active when the DAP hardware is connected to a debugger. + - Running LED: is active when the debugger has put the target device into running state. +*/ + +/** Debug Unit: Set status of Connected LED. +\param bit status of the Connect LED. + - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit. + - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit. +*/ +__STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {} + +/** Debug Unit: Set status Target Running LED. +\param bit status of the Target Running LED. + - 1: Target Running LED ON: program execution in target started. + - 0: Target Running LED OFF: program execution in target stopped. +*/ +__STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp +\ingroup DAP_ConfigIO_gr +@{ +Access function for Test Domain Timer. + +The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By +default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK. + +*/ + +/** Get timestamp of Test Domain Timer. +\return Current timestamp value. +*/ +__STATIC_INLINE uint32_t TIMESTAMP_GET (void) { + return (DWT->CYCCNT); +} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization +\ingroup DAP_ConfigIO_gr +@{ + +CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP. +*/ + +/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized). +This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the +Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set: + - I/O clock system enabled. + - all I/O pins: input buffer enabled, output pins are set to HighZ mode. + - for nTRST, nRESET a weak pull-up (if available) is enabled. + - LED output pins are enabled and LEDs are turned off. +*/ +__STATIC_INLINE void DAP_SETUP (void) { + ; +} + +/** Reset Target Device with custom specific I/O pin or command sequence. +This function allows the optional implementation of a device specific reset sequence. +It is called when the command \ref DAP_ResetTarget and is for example required +when a device needs a time-critical unlock sequence that enables the debug port. +\return 0 = no device specific reset sequence is implemented.\n + 1 = a device specific reset sequence is implemented. +*/ +__STATIC_INLINE uint8_t RESET_TARGET (void) { + return (0U); // change to '1' when a device reset sequence is implemented +} + +///@} + + +#endif /* __DAP_CONFIG_H__ */ diff --git a/source/hic_hal/nordic/nrf52820/IO_Config.h b/source/hic_hal/nordic/nrf52820/IO_Config.h new file mode 100644 index 000000000..8fbde42e4 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/IO_Config.h @@ -0,0 +1,52 @@ +/** + * @file IO_Config.h + * @brief IO Configuration for nrf52820 HIC + * + * DAPLink Interface Firmware + * Copyright (c) 2021 Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "device.h" +#include "compiler.h" +#include "daplink.h" + +// This GPIO configuration is only valid for the nrf52820 HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_NRF52820); + +// SWCLK (Output) +#define PIN_SWCDLK_PORT +#define PIN_SWCDLK_BIT + +// SWDIO (Input/Output) +#define PIN_SWDIO_PORT +#define PIN_SWDIO_BIT + +// nRESET Pin +#define PIN_nRESET_PORT +#define PIN_nRESET_BIT + +// Connected LED (Output) +#define LED_CONNECTED_PORT +#define LED_CONNECTED_BIT + +// Target Running LED (Output) +#define LED_RUNNING_PORT +#define LED_RUNNING_BIT + +#endif diff --git a/source/hic_hal/nordic/nrf52820/flash.c b/source/hic_hal/nordic/nrf52820/flash.c new file mode 100644 index 000000000..09328ba13 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/flash.c @@ -0,0 +1,47 @@ +/** + * @file flash.c + * @brief Flash access functions for stm32f723ie HIC + * + * DAPLink Interface Firmware + * Copyright (c) 2021, Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_config.h" + +uint32_t Init(uint32_t adr, uint32_t clk, uint32_t fnc) +{ + return 0; +} + +uint32_t UnInit(uint32_t fnc) +{ + return 0; +} + +uint32_t EraseChip(void) +{ + return 0; +} + +uint32_t EraseSector(uint32_t adr) +{ + return 0; +} + +uint32_t ProgramPage(uint32_t adr, uint32_t sz, uint32_t *buf) +{ + return 0; +} diff --git a/source/hic_hal/nordic/nrf52820/gpio.c b/source/hic_hal/nordic/nrf52820/gpio.c new file mode 100644 index 000000000..26bd055e9 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/gpio.c @@ -0,0 +1,62 @@ +/** + * @file gpio.c + * @brief GPIO access functions for nrf52833 HIC + * + * DAPLink Interface Firmware + * Copyright (c) 2021, Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "gpio.h" + +void gpio_init(void) +{ +} + +void gpio_set_hid_led(gpio_led_state_t state) +{ +} + +void gpio_set_cdc_led(gpio_led_state_t state) +{ +} + +void gpio_set_msc_led(gpio_led_state_t state) +{ +} + +uint8_t gpio_get_reset_btn_no_fwrd(void) +{ + return 0; +} + +uint8_t gpio_get_reset_btn_fwrd(void) +{ + return 0; +} + + +uint8_t GPIOGetButtonState(void) +{ + return 0; +} + +void target_forward_reset(bool assert_reset) +{ +} + +void gpio_set_board_power(bool powerEnabled) +{ +} diff --git a/source/hic_hal/nordic/nrf52820/read_uid.c b/source/hic_hal/nordic/nrf52820/read_uid.c new file mode 100644 index 000000000..74af68d65 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/read_uid.c @@ -0,0 +1,30 @@ +/** + * @file read_uid.c + * @brief UID extraction function for nrf52833 HIC + * + * DAPLink Interface Firmware + * Copyright (c) 2021, Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "read_uid.h" + +void read_unique_id(uint32_t *id) +{ + id[0] = 0; + id[1] = 0; + id[2] = 0; + id[3] = 0; +} diff --git a/source/hic_hal/nordic/nrf52820/sdk.c b/source/hic_hal/nordic/nrf52820/sdk.c new file mode 100644 index 000000000..34fbaef38 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/sdk.c @@ -0,0 +1,29 @@ +/** + * @file sdk.c + * @brief HIC Initialization + * + * DAPLink Interface Firmware + * Copyright (c) 2021, Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "device.h" +#include "DAP_config.h" +#include "daplink.h" +#include "util.h" + +void sdk_init() +{ +} diff --git a/source/hic_hal/nordic/nrf52820/uart.c b/source/hic_hal/nordic/nrf52820/uart.c new file mode 100644 index 000000000..4ec8c6cfb --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/uart.c @@ -0,0 +1,58 @@ +/** + * @file uart.c + * @brief UART Function for nrf52833 HIC + * + * DAPLink Interface Firmware + * Copyright (c) 2021, Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "uart.h" + +int32_t uart_initialize(void) +{ +} + +int32_t uart_uninitialize(void) +{ +} + +int32_t uart_reset(void) +{ +} + +int32_t uart_set_configuration(UART_Configuration *config) +{ +} + +int32_t uart_get_configuration(UART_Configuration *config) +{ +} + +int32_t uart_write_free(void) +{ +} + +int32_t uart_write_data(uint8_t *data, uint16_t size) +{ +} + +int32_t uart_read_data(uint8_t *data, uint16_t size) +{ +} + +void CDC_UART_IRQn_Handler(void) +{ +} diff --git a/source/hic_hal/nordic/nrf52820/usb_config.c b/source/hic_hal/nordic/nrf52820/usb_config.c new file mode 100644 index 000000000..cee7fc314 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/usb_config.c @@ -0,0 +1,563 @@ +/** + * @file usb_config.c + * @brief USB Device Configuration + * + * DAPLink Interface Firmware + * Copyright (c) 2021, Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "util.h" + +// USB Device +// Enable the USB Device functionality +#define USBD_ENABLE 1 +#define USBD_RTX_CORE_STACK 0 +#define USBD_RTX_DEVICE_STACK 0 +#define USBD_RTX_ENDPOINT0_STACK 0 + +// High-speed +// Enable high-speed functionality (if device supports it) +#define USBD_HS_ENABLE 1 +#if (defined(WEBUSB_INTERFACE) || defined(WINUSB_INTERFACE) || defined(BULK_ENDPOINT)) +#define USBD_BOS_ENABLE 1 +#else +#define USBD_BOS_ENABLE 0 +#endif +// Device Settings +// These settings affect Device Descriptor +// Power +// Default Power Setting +// <0=> Bus-powered +// <1=> Self-powered +// Max Endpoint 0 Packet Size +// Maximum packet size for endpoint zero (bMaxPacketSize0) +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes +// Vendor ID <0x0000-0xFFFF> +// Vendor ID assigned by the USB-IF (idVendor) +// Product ID <0x0000-0xFFFF> +// Product ID assigned by the manufacturer (idProduct) +// Device Release Number <0x0000-0xFFFF> +// Device release number in binary-coded decimal (bcdDevice) +// +#define USBD_POWER 0 +#define USBD_MAX_PACKET0 64 +#define USBD_DEVDESC_IDVENDOR 0x0D28 +#define USBD_DEVDESC_IDPRODUCT 0x0204 +#define USBD_DEVDESC_BCDDEVICE 0x1000 //was 0x0100 + +// Configuration Settings +// These settings affect Configuration Descriptor +// Remote Wakeup +// Configuration support for remote wakeup (D5: of bmAttributes) +// Maximum Power Consumption (in mA) <0-510><#/2> +// Maximum power consumption of the USB device +// from the bus in this specific configuration +// when the device is fully operational (bMaxPower) +// +#define USBD_CFGDESC_BMATTRIBUTES 0x80 +#define USBD_CFGDESC_BMAXPOWER 0xFA + +// String Settings +// These settings affect String Descriptor +// Language ID <0x0000-0xFCFF> +// English (United States) = 0x0409 +// Manufacturer String +// String descriptor describing manufacturer +// Product String +// String descriptor describing product +// Serial Number +// Enable serial number string +// If disabled serial number string will not be assigned to the USB Device +// Serial Number String +// String descriptor describing device's serial number +// +// +#define USBD_STRDESC_LANGID 0x0409 +#define USBD_STRDESC_MAN L"Arm" +#ifndef USB_PROD_STR +#define USBD_STRDESC_PROD L"DAPLink CMSIS-DAP" +#else +#define _TOWIDE(x) L ## #x +#define TOWIDE(x) _TOWIDE(x) +#define USBD_STRDESC_PROD TOWIDE(USB_PROD_STR) +#endif +#define USBD_STRDESC_SER_ENABLE 1 +#define USBD_STRDESC_SER L"0001A0000000" + +// Class Support +// Enables USB Device Class specific Requests +#define USBD_CLASS_ENABLE 1 + +// Human Interface Device (HID) +// Enable class support for Human Interface Device (HID) +// Interrupt Endpoint Settings +// Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// Interrupt Out Endpoint Number <0=> Not used <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// If interrupt out endpoint is not used select "Not used" +// Endpoint Settings +// Maximum Endpoint Packet Size (in bytes) <0-64> +// Endpoint polling Interval (in ms) <1-255> +// High-speed +// If high-speed is enabled set endpoint settings for it +// Maximum Endpoint Packet Size (in bytes) <0-1024> +// Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// +// +// +// Human Interface Device Settings +// Device specific settings +// HID Interface String +// Number of Input Reports <1-32> +// Number of Output Reports <1-32> +// Maximum Input Report Size (in bytes) <1-65535> +// Maximum Output Report Size (in bytes) <1-65535> +// Maximum Feature Report Size (in bytes) <1-65535> +// +// +#ifndef HID_ENDPOINT +#define HID_ENDPOINT 0 +#else +#define HID_ENDPOINT 1 +#endif + +#ifndef WEBUSB_INTERFACE +#define WEBUSB_INTERFACE 0 +#else +#define WEBUSB_INTERFACE 1 +#endif + +#ifndef WINUSB_INTERFACE +#define WINUSB_INTERFACE 0 +#else +#define WINUSB_INTERFACE 1 +#endif + +#define USBD_HID_ENABLE HID_ENDPOINT +#ifndef BULK_ENDPOINT //check if bulk endpoint is not enabled +#define USBD_HID_EP_INTIN 1 +#define USBD_HID_EP_INTOUT 1 +#else //if bulk endpoint is enabled remove interrupt endpoints from the hid +#define USBD_HID_EP_INTIN 0 +#define USBD_HID_EP_INTOUT 0 +#endif +#define USBD_HID_EP_INTIN_STACK 0 +#define USBD_HID_WMAXPACKETSIZE 64 +#define USBD_HID_BINTERVAL 1 +#define USBD_HID_HS_ENABLE 1 +#define USBD_HID_HS_WMAXPACKETSIZE 64 +#define USBD_HID_HS_BINTERVAL 1 +#define USBD_HID_STRDESC L"CMSIS-DAP v1" +#define USBD_WEBUSB_STRDESC L"WebUSB: CMSIS-DAP" +#define USBD_HID_INREPORT_NUM 1 +#define USBD_HID_OUTREPORT_NUM 1 +#define USBD_HID_INREPORT_MAX_SZ 64 +#define USBD_HID_OUTREPORT_MAX_SZ 64 +#define USBD_HID_FEATREPORT_MAX_SZ 1 + +// Mass Storage Device (MSC) +// Enable class support for Mass Storage Device (MSC) +// Bulk Endpoint Settings +// Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// Endpoint Settings +// Maximum Packet Size <1-1024> +// High-speed +// If high-speed is enabled set endpoint settings for it +// Maximum Packet Size <1-1024> +// Maximum NAK Rate <0-255> +// +// +// +// Mass Storage Device Settings +// Device specific settings +// MSC Interface String +// Inquiry Data +// Vendor Identification +// Product Identification +// Product Revision Level +// +// +// +#ifndef MSC_ENDPOINT +#define MSC_ENDPOINT 0 +#else +#define MSC_ENDPOINT 1 +#endif +#define USBD_MSC_ENABLE MSC_ENDPOINT +#define USBD_MSC_EP_BULKIN 2 +#define USBD_MSC_EP_BULKOUT 2 +#define USBD_MSC_EP_BULKIN_STACK 0 +#define USBD_MSC_WMAXPACKETSIZE 64 +#define USBD_MSC_HS_ENABLE 1 +#define USBD_MSC_HS_WMAXPACKETSIZE 512 +#define USBD_MSC_HS_BINTERVAL 0 +#define USBD_MSC_STRDESC L"USB_MSC" +// Make sure changes to USBD_MSC_INQUIRY_DATA are coordinated with mbed-ls +// since this is used to detect DAPLink drives +#define USBD_MSC_INQUIRY_DATA "MBED " \ + "VFS " \ + "0.1" + +// Audio Device (ADC) +// Enable class support for Audio Device (ADC) +// Isochronous Endpoint Settings +// Isochronous Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// Endpoint Settings +// Maximum Endpoint Packet Size (in bytes) <0-1024> +// Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// High-speed +// If high-speed is enabled set endpoint settings for it +// Maximum Endpoint Packet Size (in bytes) <0-1024> +// Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// +// +// +// Audio Device Settings +// Device specific settings +// Audio Control Interface String +// Audio Streaming (Zero Bandwidth) Interface String +// Audio Streaming (Operational) Interface String +// Audio Subframe Size (in bytes) <0-255> +// Sample Resolution (in bits) <0-255> +// Sample Frequency (in Hz) <0-16777215> +// Packet Size (in bytes) <1-256> +// Packet Count <1-16> +// +// +#define USBD_ADC_ENABLE 0 +#define USBD_ADC_EP_ISOOUT 3 +#define USBD_ADC_WMAXPACKETSIZE 64 +#define USBD_ADC_BINTERVAL 1 +#define USBD_ADC_HS_ENABLE 0 +#define USBD_ADC_HS_WMAXPACKETSIZE 64 +#define USBD_ADC_CIF_STRDESC L"USB_ADC" +#define USBD_ADC_SIF1_STRDESC L"USB_ADC1" +#define USBD_ADC_SIF2_STRDESC L"USB_ADC2" +#define USBD_ADC_BSUBFRAMESIZE 2 +#define USBD_ADC_BBITRESOLUTION 16 +#define USBD_ADC_TSAMFREQ 32000 +#define USBD_ADC_CFG_P_S 32 +#define USBD_ADC_CFG_P_C 1 + +// Communication Device (CDC) - Abstract Control Model (ACM) +// Enable class support for Communication Device (CDC) - Abstract Control Model (ACM) +// Interrupt Endpoint Settings +// Interrupt In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// Endpoint Settings +// Maximum Endpoint Packet Size (in bytes) <0-1024> +// Endpoint polling Interval (in ms) <0-255> +// High-speed +// If high-speed is enabled set endpoint settings for it +// Maximum Endpoint Packet Size (in bytes) <0-1024> +// Additional transactions per microframe <0=> None <1=> 1 additional <2=> 2 additional +// Endpoint polling Interval (in ms) <1=> 1 <2=> 2 <3=> 4 <4=> 8 +// <5=> 16 <6=> 32 <7=> 64 <8=> 128 +// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048 +// <13=> 4096 <14=> 8192 <15=> 16384 <16=> 32768 +// +// +// +// Bulk Endpoint Settings +// Bulk In Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// Bulk Out Endpoint Number <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// <8=> 8 <9=> 9 <10=> 10 <11=> 11 +// <12=> 12 <13=> 13 <14=> 14 <15=> 15 +// Endpoint Settings +// Maximum Packet Size <1-1024> +// High-speed +// If high-speed is enabled set endpoint settings for it +// Maximum Packet Size <1-1024> +// Maximum NAK Rate <0-255> +// +// +// +// Communication Device Settings +// Device specific settings +// Communication Class Interface String +// Data Class Interface String +// Maximum Communication Device Send Buffer Size +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// Maximum Communication Device Receive Buffer Size +// Minimum size must be as big as maximum packet size for Bulk Out Endpoint +// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes <128=> 128 Bytes +// <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes +// +// + +#ifndef CDC_ENDPOINT +#define CDC_ENDPOINT 0 +#else +#define CDC_ENDPOINT 1 +#endif +#define USBD_CDC_ACM_ENABLE CDC_ENDPOINT +#define USBD_CDC_ACM_EP_INTIN 3 +#define USBD_CDC_ACM_EP_INTIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE 16 +#define USBD_CDC_ACM_BINTERVAL 32 +#define USBD_CDC_ACM_HS_ENABLE 1 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE 64 +#define USBD_CDC_ACM_HS_BINTERVAL 2 +#define USBD_CDC_ACM_EP_BULKIN 4 +#define USBD_CDC_ACM_EP_BULKOUT 4 +#define USBD_CDC_ACM_EP_BULKIN_STACK 0 +#define USBD_CDC_ACM_WMAXPACKETSIZE1 64 +#define USBD_CDC_ACM_HS_ENABLE1 1 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE1 512 +#define USBD_CDC_ACM_HS_BINTERVAL1 1 +#define USBD_CDC_ACM_CIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_DIF_STRDESC L"mbed Serial Port" +#define USBD_CDC_ACM_SENDBUF_SIZE USBD_CDC_ACM_HS_WMAXPACKETSIZE1 +#define USBD_CDC_ACM_RECEIVEBUF_SIZE USBD_CDC_ACM_HS_WMAXPACKETSIZE1 +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_SENDBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Send Buffer size must be larger or equal to Bulk In maximum packet size!" +#endif +#if (((USBD_CDC_ACM_HS_ENABLE1) && (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_HS_WMAXPACKETSIZE1)) || (USBD_CDC_ACM_RECEIVEBUF_SIZE < USBD_CDC_ACM_WMAXPACKETSIZE1)) +#error "Receive Buffer size must be larger or equal to Bulk Out maximum packet size!" +#endif + +// Custom Class Device +// Enables USB Custom Class Requests +// Class IDs: +// 0x00 - Class Reserved ID +// 0x01 - Class Audio ID +// 0x02 - Class Communications ID +// 0x03 - Class Human Interface ID +// 0x04 - Class Monitor ID +// 0x05 - Class Physical Interface ID +// 0x06 - Class Power ID +// 0x07 - Class Printer ID +// 0x08 - Class Storage ID +// 0x09 - Class HUB ID +// 0xEF - Class Miscellaneous ID +// 0xFF - Class Vendor Specific ID +// +#define USBD_CLS_ENABLE 0 + +// WebUSB support +#define USBD_WEBUSB_ENABLE WEBUSB_INTERFACE +#define USBD_WEBUSB_VENDOR_CODE 0x21 +#define USBD_WEBUSB_LANDING_URL "os.mbed.com/webusb/landing-page/?bid=" +#define USBD_WEBUSB_ORIGIN_URL "os.mbed.com/" + +// Microsoft OS Descriptors 2.0 (WinUSB) support +#define USBD_WINUSB_ENABLE WINUSB_INTERFACE +#define USBD_WINUSB_VENDOR_CODE 0x20 +// +// + +#ifndef BULK_ENDPOINT +#define BULK_ENDPOINT 0 +#else +#define BULK_ENDPOINT 1 +#endif +#define USBD_BULK_ENABLE BULK_ENDPOINT +#define USBD_BULK_EP_BULKIN 5 +#define USBD_BULK_EP_BULKOUT 5 +// #define USBD_BULK_EP_BULKIN_SWO 6 +#define USBD_BULK_WMAXPACKETSIZE 64 +#define USBD_BULK_HS_ENABLE 1 +#define USBD_BULK_HS_WMAXPACKETSIZE 512 +#define USBD_BULK_STRDESC L"CMSIS-DAP v2" + + +/* USB Device Calculations ---------------------------------------------------*/ + +#define USBD_IF_NUM_MAX (USBD_BULK_ENABLE+USBD_WEBUSB_ENABLE+USBD_HID_ENABLE+USBD_MSC_ENABLE+(USBD_ADC_ENABLE*2)+(USBD_CDC_ACM_ENABLE*2)+USBD_CLS_ENABLE) +#define USBD_MULTI_IF (USBD_CDC_ACM_ENABLE*(USBD_HID_ENABLE|USBD_MSC_ENABLE|USBD_ADC_ENABLE|USBD_CLS_ENABLE|USBD_WEBUSB_ENABLE|USBD_BULK_ENABLE)) +// #define MAX(x, y) (((x) < (y)) ? (y) : (x)) +#define USBD_EP_NUM_CALC0 MAX((USBD_HID_ENABLE *(USBD_HID_EP_INTIN )), (USBD_HID_ENABLE *(USBD_HID_EP_INTOUT))) +#define USBD_EP_NUM_CALC1 MAX((USBD_MSC_ENABLE *(USBD_MSC_EP_BULKIN )), (USBD_MSC_ENABLE *(USBD_MSC_EP_BULKOUT))) +#define USBD_EP_NUM_CALC2 MAX((USBD_ADC_ENABLE *(USBD_ADC_EP_ISOOUT )), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_INTIN))) +#define USBD_EP_NUM_CALC3 MAX((USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKIN)), (USBD_CDC_ACM_ENABLE*(USBD_CDC_ACM_EP_BULKOUT))) +#define USBD_EP_NUM_CALC4 MAX(USBD_EP_NUM_CALC0, USBD_EP_NUM_CALC1) +#define USBD_EP_NUM_CALC5 MAX(USBD_EP_NUM_CALC2, USBD_EP_NUM_CALC3) +#define USBD_EP_NUM_CALC6 MAX(USBD_EP_NUM_CALC4, USBD_EP_NUM_CALC5) +#define USBD_EP_NUM_CALC7 MAX((USBD_BULK_ENABLE*(USBD_BULK_EP_BULKIN)), (USBD_BULK_ENABLE*(USBD_BULK_EP_BULKOUT))) +#define USBD_EP_NUM MAX(USBD_EP_NUM_CALC6, USBD_EP_NUM_CALC7) + +#if (USBD_HID_ENABLE) +#if (USBD_MSC_ENABLE) +#if ((((USBD_HID_EP_INTIN == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_MSC_EP_BULKOUT))) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_MSC_EP_BULKOUT))) +#error "HID and Mass Storage Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_ADC_ENABLE) +#if ((USBD_HID_EP_INTIN == USBD_ADC_EP_ISOOUT) || \ + ((USBD_HID_EP_INTOUT != 0) && \ + (USBD_HID_EP_INTOUT == USBD_ADC_EP_ISOOUT))) +#error "HID and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (((USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTIN == USBD_CDC_ACM_EP_BULKOUT))|| \ + ((USBD_HID_EP_INTOUT != 0) && \ + ((USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_HID_EP_INTOUT == USBD_CDC_ACM_EP_BULKOUT)))) +#error "HID and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_MSC_ENABLE) +#if (USBD_ADC_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_ADC_EP_ISOOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_ADC_EP_ISOOUT)) +#error "Mass Storage Device and Audio Device Interface can not use same Endpoints!" +#endif +#endif +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKIN == USBD_CDC_ACM_EP_BULKOUT) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_MSC_EP_BULKOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Mass Storage Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#if (USBD_ADC_ENABLE) +#if (USBD_CDC_ACM_ENABLE) +#if ((USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_INTIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKIN) || \ + (USBD_ADC_EP_ISOOUT == USBD_CDC_ACM_EP_BULKOUT)) +#error "Audio Device and Communication Device Interface can not use same Endpoints!" +#endif +#endif +#endif + +#define USBD_ADC_CIF_NUM (0) +#define USBD_ADC_SIF1_NUM (1) +#define USBD_ADC_SIF2_NUM (2) + +#define USBD_ADC_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+0) +#define USBD_ADC_SIF1_STR_NUM (3+USBD_STRDESC_SER_ENABLE+1) +#define USBD_ADC_SIF2_STR_NUM (3+USBD_STRDESC_SER_ENABLE+2) +#define USBD_CDC_ACM_CIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+0) +#define USBD_CDC_ACM_DIF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+1) +#define USBD_HID_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2) +#define USBD_WEBUSB_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE) +#define USBD_MSC_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE) +#define USBD_BULK_IF_STR_NUM (3+USBD_STRDESC_SER_ENABLE+USBD_ADC_ENABLE*3+USBD_CDC_ACM_ENABLE*2+USBD_HID_ENABLE+USBD_WEBUSB_ENABLE+USBD_MSC_ENABLE) + +#if (USBD_HID_ENABLE) +#if (USBD_HID_HS_ENABLE) +#define USBD_HID_MAX_PACKET ((USBD_HID_HS_WMAXPACKETSIZE > USBD_HID_WMAXPACKETSIZE) ? USBD_HID_HS_WMAXPACKETSIZE : USBD_HID_WMAXPACKETSIZE) +#else +#define USBD_HID_MAX_PACKET (USBD_HID_WMAXPACKETSIZE) +#endif +#else +#define USBD_HID_MAX_PACKET (0) +#endif +#if (USBD_MSC_ENABLE) +#if (USBD_MSC_HS_ENABLE) +#define USBD_MSC_MAX_PACKET ((USBD_MSC_HS_WMAXPACKETSIZE > USBD_MSC_WMAXPACKETSIZE) ? USBD_MSC_HS_WMAXPACKETSIZE : USBD_MSC_WMAXPACKETSIZE) +#else +#define USBD_MSC_MAX_PACKET (USBD_MSC_WMAXPACKETSIZE) +#endif +#else +#define USBD_MSC_MAX_PACKET (0) +#endif +#if (USBD_ADC_ENABLE) +#if (USBD_ADC_HS_ENABLE) +#define USBD_ADC_MAX_PACKET ((USBD_ADC_HS_WMAXPACKETSIZE > USBD_ADC_WMAXPACKETSIZE) ? USBD_ADC_HS_WMAXPACKETSIZE : USBD_ADC_WMAXPACKETSIZE) +#else +#define USBD_ADC_MAX_PACKET (USBD_ADC_WMAXPACKETSIZE) +#endif +#else +#define USBD_ADC_MAX_PACKET (0) +#endif +#if (USBD_CDC_ACM_ENABLE) +#if (USBD_CDC_ACM_HS_ENABLE) +#define USBD_CDC_ACM_MAX_PACKET ((USBD_CDC_ACM_HS_WMAXPACKETSIZE > USBD_CDC_ACM_WMAXPACKETSIZE) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE : USBD_CDC_ACM_WMAXPACKETSIZE) +#else +#define USBD_CDC_ACM_MAX_PACKET (USBD_CDC_ACM_WMAXPACKETSIZE) +#endif +#if (USBD_CDC_ACM_HS_ENABLE1) +#define USBD_CDC_ACM_MAX_PACKET1 ((USBD_CDC_ACM_HS_WMAXPACKETSIZE1 > USBD_CDC_ACM_WMAXPACKETSIZE1) ? USBD_CDC_ACM_HS_WMAXPACKETSIZE1 : USBD_CDC_ACM_WMAXPACKETSIZE1) +#else +#define USBD_CDC_ACM_MAX_PACKET1 (USBD_CDC_ACM_WMAXPACKETSIZE1) +#endif +#else +#define USBD_CDC_ACM_MAX_PACKET (0) +#define USBD_CDC_ACM_MAX_PACKET1 (0) +#endif +#if (USBD_BULK_ENABLE) +#if (USBD_BULK_HS_ENABLE) +#define USBD_BULK_MAX_PACKET ((USBD_BULK_HS_WMAXPACKETSIZE > USBD_BULK_WMAXPACKETSIZE) ? USBD_BULK_HS_WMAXPACKETSIZE : USBD_BULK_WMAXPACKETSIZE) +#else +#define USBD_BULK_MAX_PACKET (USBD_BULK_WMAXPACKETSIZE) +#endif +#else +#define USBD_BULK_MAX_PACKET (0) +#endif +#define USBD_MAX_PACKET_CALC0 ((USBD_HID_MAX_PACKET > USBD_HID_MAX_PACKET ) ? (USBD_HID_MAX_PACKET ) : (USBD_HID_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC1 ((USBD_ADC_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET ) ? (USBD_ADC_MAX_PACKET ) : (USBD_CDC_ACM_MAX_PACKET )) +#define USBD_MAX_PACKET_CALC2 ((USBD_MAX_PACKET_CALC0 > USBD_MAX_PACKET_CALC1 ) ? (USBD_MAX_PACKET_CALC0) : (USBD_MAX_PACKET_CALC1 )) +#define USBD_MAX_PACKET_CALC3 ((USBD_BULK_MAX_PACKET > USBD_CDC_ACM_MAX_PACKET1 ) ? (USBD_BULK_MAX_PACKET) : (USBD_CDC_ACM_MAX_PACKET1 )) +#define USBD_MAX_PACKET ((USBD_MAX_PACKET_CALC3 > USBD_MAX_PACKET_CALC2 ) ? (USBD_MAX_PACKET_CALC3) : (USBD_MAX_PACKET_CALC2 )) + + +/*------------------------------------------------------------------------------ + * USB Config Functions + *----------------------------------------------------------------------------*/ + +#ifndef __USB_CONFIG___ +#define __USB_CONFIG__ + +#ifndef __NO_USB_LIB_C +#include "usb_lib.c" +#endif + +#endif /* __USB_CONFIG__ */ diff --git a/source/hic_hal/nordic/nrf52820/usbd_nrf52833.c b/source/hic_hal/nordic/nrf52820/usbd_nrf52833.c new file mode 100644 index 000000000..5fa4c65fb --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/usbd_nrf52833.c @@ -0,0 +1,343 @@ +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "IO_Config.h" +#include "cortex_m.h" +#include "string.h" +#include "device.h" + +#define __NO_USB_LIB_C +#include "usb_config.c" + +/* + * Reset Endpoint + * Parameters: EPNum: Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void EP_Reset(U32 EPNum) +{ +} + + +/* + * Set Endpoint Status + * Parameters: EPNum: Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * stat: New Status + * Return Value: None + */ + +void EP_Status(U32 EPNum, U32 stat) +{ +} + + +/* + * USB Device Interrupt enable + * Called by USBD_Init to enable the USB Interrupt + * Return Value: None + */ + +#ifdef __RTX +void __svc(1) USBD_IntrEna(void); +void __SVC_1(void) +{ +#else +void USBD_IntrEna(void) +{ +#endif +} + + +/* + * USB Device Initialize Function + * Called by the User to initialize USB + * Return Value: None + */ + +void USBD_Init(void) +{ +} + + +/* + * USB Device Connect Function + * Called by the User to Connect/Disconnect USB Device + * Parameters: con: Connect/Disconnect + * Return Value: None + */ + +void USBD_Connect(BOOL con) +{ +} + + +/* + * USB Device Reset Function + * Called automatically on USB Device Reset + * Return Value: None + */ + +void USBD_Reset(void) +{ +} + + +/* + * USB Device Suspend Function + * Called automatically on USB Device Suspend + * Return Value: None + */ + +void USBD_Suspend(void) +{ +} + + +/* + * USB Device Resume Function + * Called automatically on USB Device Resume + * Return Value: None + */ + +void USBD_Resume(void) +{ + /* Performed by Hardware */ +} + + +/* + * USB Device Remote Wakeup Function + * Called automatically on USB Device Remote Wakeup + * Return Value: None + */ + +void USBD_WakeUp(void) +{ +} + + +/* + * USB Device Remote Wakeup Configuration Function + * Parameters: cfg: Device Enable/Disable + * Return Value: None + */ + +void USBD_WakeUpCfg(BOOL cfg) +{ + /* Not needed */ +} + + +/* + * USB Device Set Address Function + * Parameters: adr: USB Device Address + * setup: Called in setup stage (!=0), else after status stage + * Return Value: None + */ + +void USBD_SetAddress(U32 adr, U32 setup) +{ +} + + +/* + * USB Device Configure Function + * Parameters: cfg: Device Configure/Deconfigure + * Return Value: None + */ + +void USBD_Configure(BOOL cfg) +{ +} + + +/* + * Configure USB Device Endpoint according to Descriptor + * Parameters: pEPD: Pointer to Device Endpoint Descriptor + * Return Value: None + */ + +void USBD_ConfigEP(USB_ENDPOINT_DESCRIPTOR *pEPD) +{ +} + + +/* + * Set Direction for USB Device Control Endpoint + * Parameters: dir: Out (dir == 0), In (dir <> 0) + * Return Value: None + */ + +void USBD_DirCtrlEP(U32 dir) +{ + /* Not needed */ +} + + +/* + * Enable USB Device Endpoint + * Parameters: EPNum: Device Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USBD_EnableEP(U32 EPNum) +{ +} + + +/* + * Disable USB Endpoint + * Parameters: EPNum: Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USBD_DisableEP(U32 EPNum) +{ +} + + +/* + * Reset USB Device Endpoint + * Parameters: EPNum: Device Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USBD_ResetEP(U32 EPNum) +{ +} + + +/* + * Set Stall for USB Device Endpoint + * Parameters: EPNum: Device Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USBD_SetStallEP(U32 EPNum) +{ +} + + +/* + * Clear Stall for USB Device Endpoint + * Parameters: EPNum: Device Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USBD_ClrStallEP(U32 EPNum) +{ +} + + +/* + * Clear USB Device Endpoint Buffer + * Parameters: EPNum: Device Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USBD_ClearEPBuf(U32 EPNum) +{ + ; +} + + +/* + * Read USB Device Endpoint Data + * Parameters: EPNum: Device Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * pData: Pointer to Data Buffer + * Return Value: Number of bytes read + */ + +U32 USBD_ReadEP(U32 EPNum, U8 *pData, U32 bufsz) +{ +} + + +/* + * Write USB Device Endpoint Data + * Parameters: EPNum: Device Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * pData: Pointer to Data Buffer + * cnt: Number of bytes to write + * Return Value: Number of bytes written + */ + +U32 USBD_WriteEP(U32 EPNum, U8 *pData, U32 cnt) +{ +} + + +/* + * Get USB Device Last Frame Number + * Parameters: None + * Return Value: Frame Number + */ + +U32 USBD_GetFrame(void) +{ +} + + +#ifdef __RTX +U32 LastError; /* Last Error */ + +/* + * Get USB Last Error Code + * Parameters: None + * Return Value: Error Code + */ + +U32 USBD_GetError(void) +{ + return (LastError); +} +#endif + + +/* + * USB Device Interrupt Service Routine + */ + +void USB_LP_CAN1_RX0_IRQHandler(void) +{ +} + +void USBD_Handler(void) +{ +} From 5458f778860beed87570b43d28f2d84cc4378bfb Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sun, 20 Jun 2021 00:01:57 -0500 Subject: [PATCH 401/617] nrf52820_hic: add nrf52820 HIC to DAPLink --- projects.yaml | 12 +++++++ records/board/nrf52820_bl.yaml | 4 +++ records/hic_hal/nrf52820.yaml | 41 +++++++++++++++++++++ source/board/nrf52820_bl.c | 65 ++++++++++++++++++++++++++++++++++ source/daplink/daplink.h | 1 + source/hic_hal/device.h | 2 ++ 6 files changed, 125 insertions(+) create mode 100644 records/board/nrf52820_bl.yaml create mode 100644 records/hic_hal/nrf52820.yaml create mode 100644 source/board/nrf52820_bl.c diff --git a/projects.yaml b/projects.yaml index ca346c8ff..41cafbb32 100644 --- a/projects.yaml +++ b/projects.yaml @@ -81,6 +81,9 @@ module: hic_m48ssidae: &module_hic_m48ssidae - records/rtos/rtos-cm4.yaml - records/hic_hal/m48ssidae.yaml + hic_nrf52820: &module_hic_nrf52820 + - records/rtos/rtos-cm4.yaml + - records/hic_hal/nrf52820.yaml projects: # HIC bootloaders and all target interfaces @@ -160,6 +163,15 @@ projects: - *module_hic_max32625 - records/family/all_family.yaml - records/usb/usb-bulk.yaml + nrf52820_bl: + - *module_bl + - records/hic_hal/nrf52820.yaml + - records/board/nrf52820_bl.yaml + nrf52820_if: + - *module_if + - *module_hic_nrf52820 + - records/family/all_family.yaml + - records/usb/usb-bulk.yaml sam3u2c_bl: - *module_bl - records/hic_hal/sam3u2c.yaml diff --git a/records/board/nrf52820_bl.yaml b/records/board/nrf52820_bl.yaml new file mode 100644 index 000000000..b7fca7dbe --- /dev/null +++ b/records/board/nrf52820_bl.yaml @@ -0,0 +1,4 @@ +common: + sources: + board: + - source/board/nrf52820_bl.c diff --git a/records/hic_hal/nrf52820.yaml b/records/hic_hal/nrf52820.yaml new file mode 100644 index 000000000..3a3a5e896 --- /dev/null +++ b/records/hic_hal/nrf52820.yaml @@ -0,0 +1,41 @@ +common: + target: + - Cortex-M4 + core: + - Cortex-M4 + macros: + - INTERFACE_NRF52820 + - NRF52820_XXAA + - DAPLINK_HIC_ID=0x6E052820 # DAPLINK_HIC_ID_NRF52820 + - OS_CLOCK=64000000 + - DAPLINK_IF + includes: + - source/hic_hal/nordic/nrf52820 + - source/hic_hal/nordic/nrf52820/cmsis + - source/hic_hal/nordic/nrf52820/nrfx + sources: + hic_hal: + - source/hic_hal/nordic/nrf52820 + - source/hic_hal/nordic/nrf52820/cmsis + - source/hic_hal/nordic/nrf52820/nrfx + +tool_specific: + uvision: + misc: + ld_flags: + - --predefine="-I..\..\..\source\hic_hal\nrf52820\nrfx" + sources: + hic_hal: + - source/hic_hal/nordic/nrf52820/armcc + armcc: + sources: + hic_hal: + - source/hic_hal/nordic/nrf52820/armcc + armclang: + sources: + hic_hal: + - source/hic_hal/nordic/nrf52820/armcc + gcc_arm: + sources: + hic_hal: + - source/hic_hal/nordic/nrf52820/gcc diff --git a/source/board/nrf52820_bl.c b/source/board/nrf52820_bl.c new file mode 100644 index 000000000..a0612ecd3 --- /dev/null +++ b/source/board/nrf52820_bl.c @@ -0,0 +1,65 @@ +/** + * @file nrf52820_bl.c + * @brief board ID and meta-data for HIC based on Nordic Semiconductor nRF52820 + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_config.h" +#include "daplink_addr.h" +#include "compiler.h" +#include "target_board.h" +#include "target_family.h" + +// Warning - changing the interface start will break backwards compatibility +COMPILER_ASSERT(DAPLINK_ROM_IF_START == 0x00010000); +COMPILER_ASSERT(DAPLINK_ROM_IF_SIZE == KB(188)); + +/** +* List of start and size for each size of flash sector +* The size will apply to all sectors between the listed address and the next address +* in the list. +* The last pair in the list will have sectors starting at that address and ending +* at address start + size. +*/ +static const sector_info_t sectors_info[] = { + {DAPLINK_ROM_IF_START, 0x1000}, +}; + +// m48ssidae target information +target_cfg_t target_device = { + .sectors_info = sectors_info, + .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), + .flash_regions[0].start = DAPLINK_ROM_IF_START, + .flash_regions[0].end = DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE, + .flash_regions[0].flags = kRegionIsDefault, + .ram_regions[0].start = DAPLINK_RAM_START, + .ram_regions[0].end = DAPLINK_RAM_START + DAPLINK_RAM_SIZE, + /* .flash_algo not needed for bootloader */ +}; + +// bootloader has no family +const target_family_descriptor_t *g_target_family = NULL; + +const board_info_t g_board_info = { + .info_version = kBoardInfoVersion, + .board_id = "0000", + .daplink_url_name = "HELP_FAQHTM", + .daplink_drive_name = "MAINTENANCE", + .daplink_target_url = "https://mbed.com/daplink", + .target_cfg = &target_device, +}; diff --git a/source/daplink/daplink.h b/source/daplink/daplink.h index f73cc2a78..a8cb441a8 100644 --- a/source/daplink/daplink.h +++ b/source/daplink/daplink.h @@ -67,6 +67,7 @@ COMPILER_ASSERT(DAPLINK_RAM_SHARED_START + DAPLINK_RAM_SHARED_SIZE == DAPLINK_RA #define DAPLINK_HIC_ID_LPC55XX 0x4C504355 // 'LPC\x55' #define DAPLINK_HIC_ID_M48SSIDAE 0x97969921 #define DAPLINK_HIC_ID_PSOC5 0x2E127069 +#define DAPLINK_HIC_ID_NRF52820 0x6E052820 // 'n\x05\x28\x20' //@} #define DAPLINK_INFO_OFFSET 0x20 diff --git a/source/hic_hal/device.h b/source/hic_hal/device.h index 0e21d93c5..0fd4ec096 100644 --- a/source/hic_hal/device.h +++ b/source/hic_hal/device.h @@ -42,6 +42,8 @@ #include "stm32f1xx.h" #elif defined (INTERFACE_M48SSIDAE) #include "M480.h" +#elif defined (INTERFACE_NRF52820) +#include "nrf52820.h" #else #error "CMSIS core headers needed" #endif From c16d12c2d9d2eea8f311e773a6793ac0d26c9273 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sun, 20 Jun 2021 00:07:34 -0500 Subject: [PATCH 402/617] nrf52820_hic: adapt GCC assembly for DAPLink --- .../nrf52820/gcc/ses_startup_nrf52820.S | 25 +++++++++---------- .../nrf52820/gcc/ses_startup_nrf_common.S | 12 ++++----- 2 files changed, 18 insertions(+), 19 deletions(-) diff --git a/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf52820.S b/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf52820.S index 6412cd50a..e0faa3fa2 100644 --- a/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf52820.S +++ b/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf52820.S @@ -55,7 +55,7 @@ .section .init, "ax" .align 0 - + /************************************************************************************ * Default Exception Handlers * ************************************************************************************/ @@ -114,7 +114,7 @@ Dummy_Handler: /************************************************************************************ * Default Interrupt Handlers * ************************************************************************************/ - + .weak POWER_CLOCK_IRQHandler .thumb_set POWER_CLOCK_IRQHandler, Dummy_Handler @@ -204,19 +204,18 @@ Dummy_Handler: .thumb_func nRFInitialize: b afterInitialize - - + + /************************************************************************************ * Vector Table * ************************************************************************************/ - .section .vectors, "ax" + .section .isr_vector, "ax" .align 0 - .global _vectors - .extern __stack_end__ + .global __isr_vector -_vectors: - .word __stack_end__ +__isr_vector: + .word __StackTop .word Reset_Handler .word NMI_Handler .word HardFault_Handler @@ -224,12 +223,12 @@ _vectors: .word BusFault_Handler .word UsageFault_Handler .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ + .word DAPLINK_BUILD_KEY /* Build type - BL/IF*/ + .word DAPLINK_HIC_ID /* Compatibility*/ + .word DAPLINK_VERSION /* Version*/ .word SVC_Handler .word DebugMon_Handler - .word 0 /*Reserved */ + .word g_board_info /* Ptr to Board info, family info other target details*/ .word PendSV_Handler .word SysTick_Handler diff --git a/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf_common.S b/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf_common.S index f7ede0a0c..2db7c9c94 100644 --- a/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf_common.S +++ b/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf_common.S @@ -87,10 +87,10 @@ .syntax unified .global Reset_Handler -#ifdef INITIALIZE_USER_SECTIONS +#ifdef INITIALIZE_USER_SECTIONS .global InitializeUserMemorySections #endif - .extern _vectors + .extern __isr_vector .extern nRFInitialize .global afterInitialize @@ -101,7 +101,7 @@ .equ FPU_CPACR_REG, 0xE000ED88 #ifndef STACK_INIT_VAL -#define STACK_INIT_VAL __RAM1_segment_end__ +#define STACK_INIT_VAL __StackTop #endif Reset_Handler: @@ -111,7 +111,7 @@ Reset_Handler: .thumb_func afterInitialize: - + #ifndef NO_STACK_INIT /* Initialise main stack */ ldr r0, =STACK_INIT_VAL @@ -153,7 +153,7 @@ afterInitialize: #ifdef VECTORS_IN_RAM ldr r1, =_vectors_ram #else - ldr r1, =_vectors + ldr r1, =__isr_vector #endif str r1, [r0] #endif @@ -171,7 +171,7 @@ afterInitialize: /* Jump to program start */ b _start -#ifdef INITIALIZE_USER_SECTIONS +#ifdef INITIALIZE_USER_SECTIONS .thumb_func InitializeUserMemorySections: ldr r0, =__start_nrf_sections From 1b64bb32650608d68438394158a00ff5839b2f50 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sun, 20 Jun 2021 00:15:53 -0500 Subject: [PATCH 403/617] nrf52820_hic: compilation work-around and fixes --- source/daplink/interface/swd_host.c | 5 +- source/daplink/interface/swd_host.h | 2 +- source/family/nordic/target_reset_nrf51.c | 2 +- source/family/nordic/target_reset_nrf52.c | 2 +- .../realtek/target_reset_realtek_rtl8195am.c | 2 +- source/hic_hal/nordic/nrf52820/DAP_config.h | 71 ++++++------------- 6 files changed, 28 insertions(+), 56 deletions(-) diff --git a/source/daplink/interface/swd_host.c b/source/daplink/interface/swd_host.c index ea6d07974..6b10ccb2b 100644 --- a/source/daplink/interface/swd_host.c +++ b/source/daplink/interface/swd_host.c @@ -22,14 +22,13 @@ */ #ifndef TARGET_MCU_CORTEX_A +#include "device.h" #include "cmsis_os2.h" #include "target_config.h" -#include "swd_host.h" -#include "debug_cm.h" #include "DAP_config.h" #include "DAP.h" #include "target_family.h" -#include "device.h" +#include "swd_host.h" // Default NVIC and Core debug base addresses // TODO: Read these addresses from ROM. diff --git a/source/daplink/interface/swd_host.h b/source/daplink/interface/swd_host.h index 4815cb8fc..f3614e4f2 100644 --- a/source/daplink/interface/swd_host.h +++ b/source/daplink/interface/swd_host.h @@ -4,7 +4,7 @@ * * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * Copyright 2019, Cypress Semiconductor Corporation + * Copyright 2019, Cypress Semiconductor Corporation * or a subsidiary of Cypress Semiconductor Corporation. * SPDX-License-Identifier: Apache-2.0 * diff --git a/source/family/nordic/target_reset_nrf51.c b/source/family/nordic/target_reset_nrf51.c index 49d948aad..d93d82bb1 100644 --- a/source/family/nordic/target_reset_nrf51.c +++ b/source/family/nordic/target_reset_nrf51.c @@ -19,10 +19,10 @@ * limitations under the License. */ -#include "swd_host.h" #include "DAP_config.h" #include "target_family.h" #include "target_board.h" +#include "swd_host.h" static void swd_set_target_reset_nrf(uint8_t asserted) { diff --git a/source/family/nordic/target_reset_nrf52.c b/source/family/nordic/target_reset_nrf52.c index f3d515ada..f101372e0 100644 --- a/source/family/nordic/target_reset_nrf52.c +++ b/source/family/nordic/target_reset_nrf52.c @@ -19,10 +19,10 @@ * limitations under the License. */ -#include "swd_host.h" #include "DAP_config.h" #include "target_family.h" #include "target_board.h" +#include "swd_host.h" static void swd_set_target_reset_nrf(uint8_t asserted) { diff --git a/source/family/realtek/target_reset_realtek_rtl8195am.c b/source/family/realtek/target_reset_realtek_rtl8195am.c index 6f6d7dab3..7826185e2 100644 --- a/source/family/realtek/target_reset_realtek_rtl8195am.c +++ b/source/family/realtek/target_reset_realtek_rtl8195am.c @@ -14,9 +14,9 @@ * limitations under the License. */ #include -#include "swd_host.h" #include "DAP_config.h" #include "target_family.h" +#include "swd_host.h" static void swd_set_target_reset_realtek(uint8_t asserted) { diff --git a/source/hic_hal/nordic/nrf52820/DAP_config.h b/source/hic_hal/nordic/nrf52820/DAP_config.h index 59dc79f0c..da34bc434 100644 --- a/source/hic_hal/nordic/nrf52820/DAP_config.h +++ b/source/hic_hal/nordic/nrf52820/DAP_config.h @@ -30,9 +30,9 @@ //************************************************************************************************** -/** +/** \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information -\ingroup DAP_ConfigIO_gr +\ingroup DAP_ConfigIO_gr @{ Provides definitions about the hardware and configuration of the Debug Unit. @@ -59,7 +59,7 @@ This information includes: /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors /// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses -/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be +/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be /// required. #define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0. @@ -127,44 +127,17 @@ This information includes: #define TARGET_DEVICE_NAME "Cortex-M4" ///< String indicating the Target Device #endif -/** Get Vendor ID string. -\param str Pointer to buffer to store the string. -\return String length. -*/ -__STATIC_INLINE uint8_t DAP_GetVendorString (char *str) { - (void)str; - return (0U); -} - -/** Get Product ID string. -\param str Pointer to buffer to store the string. -\return String length. -*/ -__STATIC_INLINE uint8_t DAP_GetProductString (char *str) { - (void)str; - return (0U); -} - -/** Get Serial Number string. -\param str Pointer to buffer to store the string. -\return String length. -*/ -__STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) { - (void)str; - return (0U); -} - ///@} //************************************************************************************************** -/** +/** \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access -\ingroup DAP_ConfigIO_gr +\ingroup DAP_ConfigIO_gr @{ Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode -and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug +and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug interface of a device. The following I/O Pins are provided: JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode @@ -172,19 +145,19 @@ JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mod TCK: Test Clock | SWCLK: Clock | Output Push/Pull TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data) TDI: Test Data Input | | Output Push/Pull -TDO: Test Data Output | | Input +TDO: Test Data Output | | Input nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor DAP Hardware I/O Pin Access Functions ------------------------------------- -The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to -these I/O Pins. +The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to +these I/O Pins. For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only. -This functions are provided to achieve faster I/O that is possible with some advanced GPIO -peripherals that can independently write/read a single I/O pin without affecting any other pins +This functions are provided to achieve faster I/O that is possible with some advanced GPIO +peripherals that can independently write/read a single I/O pin without affecting any other pins of the same I/O port. The following SWDIO I/O Pin functions are provided: - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware. - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware. @@ -199,16 +172,16 @@ of the same I/O port. The following SWDIO I/O Pin functions are provided: Configures the DAP Hardware I/O pins for JTAG mode: - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level. - TDO to input mode. -*/ +*/ __STATIC_INLINE void PORT_JTAG_SETUP (void) { ; } - + /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET. Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: - SWCLK, SWDIO, nRESET to output mode and set to default high level. - TDI, nTRST to HighZ mode (pins are unused in SWD mode). -*/ +*/ __STATIC_INLINE void PORT_SWD_SETUP (void) { ; } @@ -288,7 +261,7 @@ Configure the SWDIO DAP hardware I/O pin to output mode. This function is called prior \ref PIN_SWDIO_OUT function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) { - ; + ; } /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). @@ -342,7 +315,7 @@ __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN (void) { - 1: release JTAG TRST Test Reset. */ __STATIC_FORCEINLINE void PIN_nTRST_OUT (uint32_t bit) { - ; + ; } // nRESET Pin I/O------------------------------------------ @@ -367,7 +340,7 @@ __STATIC_FORCEINLINE void PIN_nRESET_OUT (uint32_t bit) { //************************************************************************************************** -/** +/** \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs \ingroup DAP_ConfigIO_gr @{ @@ -397,13 +370,13 @@ __STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {} //************************************************************************************************** -/** +/** \defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp \ingroup DAP_ConfigIO_gr @{ Access function for Test Domain Timer. -The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By +The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK. */ @@ -419,7 +392,7 @@ __STATIC_INLINE uint32_t TIMESTAMP_GET (void) { //************************************************************************************************** -/** +/** \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization \ingroup DAP_ConfigIO_gr @{ @@ -428,7 +401,7 @@ CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_S */ /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized). -This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the +This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set: - I/O clock system enabled. - all I/O pins: input buffer enabled, output pins are set to HighZ mode. @@ -441,7 +414,7 @@ __STATIC_INLINE void DAP_SETUP (void) { /** Reset Target Device with custom specific I/O pin or command sequence. This function allows the optional implementation of a device specific reset sequence. -It is called when the command \ref DAP_ResetTarget and is for example required +It is called when the command \ref DAP_ResetTarget and is for example required when a device needs a time-critical unlock sequence that enables the debug port. \return 0 = no device specific reset sequence is implemented.\n 1 = a device specific reset sequence is implemented. From 19a5b09919ca697eac15f1994c234379caf67eea Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 14 Jul 2021 01:30:20 +0200 Subject: [PATCH 404/617] nrf52820_hic: start development using nRF52833-DK --- projects.yaml | 11 + records/board/nrf52833_dk.yaml | 5 + records/hic_hal/nrf52820.yaml | 4 + .../override_nrf52833_dk/IO_Config_Override.h | 68 ++ source/hic_hal/nordic/nrf52820/DAP_config.h | 13 +- source/hic_hal/nordic/nrf52820/IO_Config.h | 44 +- source/hic_hal/nordic/nrf52820/flash.c | 2 +- source/hic_hal/nordic/nrf52820/gpio.c | 28 +- .../nrf52820/nrfx/drivers/nrfx_common.h | 342 +++++++ .../nrf52820/nrfx/drivers/nrfx_errors.h | 85 ++ .../nordic/nrf52820/nrfx/hal/nrf_gpio.h | 899 ++++++++++++++++++ .../nrf52820/nrfx/mdk/nrf52820_peripherals.h | 240 +++++ .../nrf52820/nrfx/mdk/nrf_peripherals.h | 79 ++ source/hic_hal/nordic/nrf52820/nrfx/nrfx.h | 49 + .../hic_hal/nordic/nrf52820/nrfx/nrfx_glue.h | 267 ++++++ source/hic_hal/nordic/nrf52820/uart.c | 2 +- .../{usbd_nrf52833.c => usbd_nrf52820.c} | 0 17 files changed, 2110 insertions(+), 28 deletions(-) create mode 100644 records/board/nrf52833_dk.yaml create mode 100644 source/board/override_nrf52833_dk/IO_Config_Override.h create mode 100644 source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_common.h create mode 100644 source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_errors.h create mode 100644 source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_gpio.h create mode 100644 source/hic_hal/nordic/nrf52820/nrfx/mdk/nrf52820_peripherals.h create mode 100644 source/hic_hal/nordic/nrf52820/nrfx/mdk/nrf_peripherals.h create mode 100644 source/hic_hal/nordic/nrf52820/nrfx/nrfx.h create mode 100644 source/hic_hal/nordic/nrf52820/nrfx/nrfx_glue.h rename source/hic_hal/nordic/nrf52820/{usbd_nrf52833.c => usbd_nrf52820.c} (100%) diff --git a/projects.yaml b/projects.yaml index 41cafbb32..795ff3dc1 100644 --- a/projects.yaml +++ b/projects.yaml @@ -172,6 +172,17 @@ projects: - *module_hic_nrf52820 - records/family/all_family.yaml - records/usb/usb-bulk.yaml + nrf52833_dk_bl: + - *module_bl + - records/board/nrf52833_dk.yaml + - records/hic_hal/nrf52820.yaml + - records/board/nrf52820_bl.yaml + nrf52833_dk_if: + - *module_if + - *module_hic_nrf52820 + - records/board/nrf52833_dk.yaml + - records/family/all_family.yaml + - records/usb/usb-bulk.yaml sam3u2c_bl: - *module_bl - records/hic_hal/sam3u2c.yaml diff --git a/records/board/nrf52833_dk.yaml b/records/board/nrf52833_dk.yaml new file mode 100644 index 000000000..9c29104e6 --- /dev/null +++ b/records/board/nrf52833_dk.yaml @@ -0,0 +1,5 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_nrf52833_dk diff --git a/records/hic_hal/nrf52820.yaml b/records/hic_hal/nrf52820.yaml index 3a3a5e896..1b0bfb695 100644 --- a/records/hic_hal/nrf52820.yaml +++ b/records/hic_hal/nrf52820.yaml @@ -13,6 +13,10 @@ common: - source/hic_hal/nordic/nrf52820 - source/hic_hal/nordic/nrf52820/cmsis - source/hic_hal/nordic/nrf52820/nrfx + - source/hic_hal/nordic/nrf52820/nrfx/drivers + - source/hic_hal/nordic/nrf52820/nrfx/drivers/include + - source/hic_hal/nordic/nrf52820/nrfx/hal + - source/hic_hal/nordic/nrf52820/nrfx/mdk sources: hic_hal: - source/hic_hal/nordic/nrf52820 diff --git a/source/board/override_nrf52833_dk/IO_Config_Override.h b/source/board/override_nrf52833_dk/IO_Config_Override.h new file mode 100644 index 000000000..1915e0682 --- /dev/null +++ b/source/board/override_nrf52833_dk/IO_Config_Override.h @@ -0,0 +1,68 @@ +/** + * @file IO_Config_Override.c + * @brief Alternative IO Configuration for nrf52820 HIC + * + * DAPLink Interface Firmware + * Copyright (c) 2021, Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ + +#include "device.h" +#include "compiler.h" +#include "daplink.h" + +#include "nrf_gpio.h" + +// This GPIO configuration is only valid for the nrf52820 HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_NRF52820); + +#define LED_1 NRF_GPIO_PIN_MAP(0, 13) +#define LED_2 NRF_GPIO_PIN_MAP(0, 14) +#define LED_3 NRF_GPIO_PIN_MAP(0, 15) +#define LED_4 NRF_GPIO_PIN_MAP(0, 16) +#define BUTTON_1 NRF_GPIO_PIN_MAP(0, 11) + +// SWDCLK (Output) +#define PIN_SWDCLK NRF_GPIO_PIN_MAP(0, 1) // FIXME: Needs to change + +// SWDIO (Input/Output) +#define PIN_SWDIO NRF_GPIO_PIN_MAP(0, 0) // FIXME: Needs to change + +// nRESET Pin +#define PIN_nRESET NRF_GPIO_PIN_MAP(0, 6) // FIXME: Needs to change + +// Target Running LED (Output) +#define LED_RUNNING LED_1 + +// Connected LED (Output) +#define LED_CONNECTED LED_2 + +// HID LED +#define LED_HID LED_2 + +// MSC LED +#define LED_MSC LED_3 + +// CDC LED +#define LED_CDC LED_4 + +// Reset button +#define RESET_BUTTON BUTTON_1 +#define RESET_BUTTON_PULL NRF_GPIO_PIN_PULLUP + +#endif diff --git a/source/hic_hal/nordic/nrf52820/DAP_config.h b/source/hic_hal/nordic/nrf52820/DAP_config.h index da34bc434..6725c36e7 100644 --- a/source/hic_hal/nordic/nrf52820/DAP_config.h +++ b/source/hic_hal/nordic/nrf52820/DAP_config.h @@ -28,6 +28,7 @@ #ifndef __DAP_CONFIG_H__ #define __DAP_CONFIG_H__ +#include "IO_Config.h" //************************************************************************************************** /** @@ -357,14 +358,22 @@ It is recommended to provide the following LEDs for status indication: - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit. - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit. */ -__STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {} +__STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) { +#ifdef LED_CONNECTED + nrf_gpio_pin_write(LED_CONNECTED, bit ? 0 : 1); +#endif +} /** Debug Unit: Set status Target Running LED. \param bit status of the Target Running LED. - 1: Target Running LED ON: program execution in target started. - 0: Target Running LED OFF: program execution in target stopped. */ -__STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {} +__STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) { +#ifdef LED_RUNNING + nrf_gpio_pin_write(LED_RUNNING, bit ? 0 : 1); +#endif +} ///@} diff --git a/source/hic_hal/nordic/nrf52820/IO_Config.h b/source/hic_hal/nordic/nrf52820/IO_Config.h index 8fbde42e4..44c1cb9f2 100644 --- a/source/hic_hal/nordic/nrf52820/IO_Config.h +++ b/source/hic_hal/nordic/nrf52820/IO_Config.h @@ -3,7 +3,7 @@ * @brief IO Configuration for nrf52820 HIC * * DAPLink Interface Firmware - * Copyright (c) 2021 Arm Limited, All Rights Reserved + * Copyright (c) 2021, Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -19,6 +19,14 @@ * limitations under the License. */ +// Override all defines if IO_CONFIG_OVERRIDE is defined +#ifdef IO_CONFIG_OVERRIDE +#include "IO_Config_Override.h" +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ +#endif +#endif + #ifndef __IO_CONFIG_H__ #define __IO_CONFIG_H__ @@ -26,27 +34,37 @@ #include "compiler.h" #include "daplink.h" +#include "nrf_gpio.h" + // This GPIO configuration is only valid for the nrf52820 HIC COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_NRF52820); -// SWCLK (Output) -#define PIN_SWCDLK_PORT -#define PIN_SWCDLK_BIT +// SWDCLK (Output) +#define PIN_SWDCLK NRF_GPIO_PIN_MAP(0, 1) // SWDIO (Input/Output) -#define PIN_SWDIO_PORT -#define PIN_SWDIO_BIT +#define PIN_SWDIO NRF_GPIO_PIN_MAP(0, 0) // nRESET Pin -#define PIN_nRESET_PORT -#define PIN_nRESET_BIT +#undef PIN_nRESET + +// Target Running LED (Output) +#undef LED_RUNNING // Connected LED (Output) -#define LED_CONNECTED_PORT -#define LED_CONNECTED_BIT +#undef LED_CONNECTED -// Target Running LED (Output) -#define LED_RUNNING_PORT -#define LED_RUNNING_BIT +// HID LED +#define LED_HID NRF_GPIO_PIN_MAP(0, 7) + +// MSC LED +#define LED_MSC NRF_GPIO_PIN_MAP(0, 7) + +// CDC LED +#define LED_CDC NRF_GPIO_PIN_MAP(0, 7) + +// Reset button (SW_RESET) +#define RESET_BUTTON NRF_GPIO_PIN_MAP(0, 6) +#define RESET_BUTTON_PULL NRF_GPIO_PIN_PULLUP #endif diff --git a/source/hic_hal/nordic/nrf52820/flash.c b/source/hic_hal/nordic/nrf52820/flash.c index 09328ba13..788494dae 100644 --- a/source/hic_hal/nordic/nrf52820/flash.c +++ b/source/hic_hal/nordic/nrf52820/flash.c @@ -1,6 +1,6 @@ /** * @file flash.c - * @brief Flash access functions for stm32f723ie HIC + * @brief Flash access functions for nrf52833 HIC * * DAPLink Interface Firmware * Copyright (c) 2021, Arm Limited, All Rights Reserved diff --git a/source/hic_hal/nordic/nrf52820/gpio.c b/source/hic_hal/nordic/nrf52820/gpio.c index 26bd055e9..135deeef3 100644 --- a/source/hic_hal/nordic/nrf52820/gpio.c +++ b/source/hic_hal/nordic/nrf52820/gpio.c @@ -21,20 +21,36 @@ #include "gpio.h" +#include "IO_config.h" + void gpio_init(void) { +#ifdef LED_CONNECTED + nrf_gpio_cfg_output(LED_CONNECTED); +#endif +#ifdef LED_RUNNING + nrf_gpio_cfg_output(LED_RUNNING); +#endif + nrf_gpio_cfg_output(LED_HID); + nrf_gpio_cfg_output(LED_MSC); + nrf_gpio_cfg_output(LED_CDC); + + nrf_gpio_cfg_input(RESET_BUTTON, RESET_BUTTON_PULL); } void gpio_set_hid_led(gpio_led_state_t state) { + nrf_gpio_pin_write(LED_HID, state ? 0 : 1); } void gpio_set_cdc_led(gpio_led_state_t state) { + nrf_gpio_pin_write(LED_CDC, state ? 0 : 1); } void gpio_set_msc_led(gpio_led_state_t state) { + nrf_gpio_pin_write(LED_MSC, state ? 0 : 1); } uint8_t gpio_get_reset_btn_no_fwrd(void) @@ -44,17 +60,7 @@ uint8_t gpio_get_reset_btn_no_fwrd(void) uint8_t gpio_get_reset_btn_fwrd(void) { - return 0; -} - - -uint8_t GPIOGetButtonState(void) -{ - return 0; -} - -void target_forward_reset(bool assert_reset) -{ + return nrf_gpio_pin_read(RESET_BUTTON) ? 0 : 1; } void gpio_set_board_power(bool powerEnabled) diff --git a/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_common.h b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_common.h new file mode 100644 index 000000000..58ea22180 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_common.h @@ -0,0 +1,342 @@ +/** + * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_COMMON_H__ +#define NRFX_COMMON_H__ + +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_common Common module + * @{ + * @ingroup nrfx + * @brief Common module. + */ + +/** + * @brief Macro for checking if the specified identifier is defined and it has + * a non-zero value. + * + * Normally, preprocessors treat all undefined identifiers as having the value + * zero. However, some tools, like static code analyzers, can issue a warning + * when such identifier is evaluated. This macro gives the possibility to suppress + * such warnings only in places where this macro is used for evaluation, not in + * the whole analyzed code. + */ +#define NRFX_CHECK(module_enabled) (module_enabled) + +/** + * @brief Macro for concatenating two tokens in macro expansion. + * + * @note This macro is expanded in two steps so that tokens given as macros + * themselves are fully expanded before they are merged. + * + * @param[in] p1 First token. + * @param[in] p2 Second token. + * + * @return The two tokens merged into one, unless they cannot together form + * a valid token (in such case, the preprocessor issues a warning and + * does not perform the concatenation). + * + * @sa NRFX_CONCAT_3 + */ +#define NRFX_CONCAT_2(p1, p2) NRFX_CONCAT_2_(p1, p2) + +/** @brief Internal macro used by @ref NRFX_CONCAT_2 to perform the expansion in two steps. */ +#define NRFX_CONCAT_2_(p1, p2) p1 ## p2 + +/** + * @brief Macro for concatenating three tokens in macro expansion. + * + * @note This macro is expanded in two steps so that tokens given as macros + * themselves are fully expanded before they are merged. + * + * @param[in] p1 First token. + * @param[in] p2 Second token. + * @param[in] p3 Third token. + * + * @return The three tokens merged into one, unless they cannot together form + * a valid token (in such case, the preprocessor issues a warning and + * does not perform the concatenation). + * + * @sa NRFX_CONCAT_2 + */ +#define NRFX_CONCAT_3(p1, p2, p3) NRFX_CONCAT_3_(p1, p2, p3) + +/** @brief Internal macro used by @ref NRFX_CONCAT_3 to perform the expansion in two steps. */ +#define NRFX_CONCAT_3_(p1, p2, p3) p1 ## p2 ## p3 + +/** + * @brief Macro for performing rounded integer division (as opposed to + * truncating the result). + * + * @param[in] a Numerator. + * @param[in] b Denominator. + * + * @return Rounded (integer) result of dividing @c a by @c b. + */ +#define NRFX_ROUNDED_DIV(a, b) (((a) + ((b) / 2)) / (b)) + +/** + * @brief Macro for performing integer division, making sure the result is rounded up. + * + * @details A typical use case for this macro is to compute the number of objects + * with size @c b required to hold @c a number of bytes. + * + * @param[in] a Numerator. + * @param[in] b Denominator. + * + * @return Integer result of dividing @c a by @c b, rounded up. + */ +#define NRFX_CEIL_DIV(a, b) ((((a) - 1) / (b)) + 1) + +/** + * @brief Macro for getting the number of elements in an array. + * + * @param[in] array Name of the array. + * + * @return Array element count. + */ +#define NRFX_ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0])) + +/** + * @brief Macro for getting the offset (in bytes) from the beginning of a structure + * of the specified type to its specified member. + * + * @param[in] type Structure type. + * @param[in] member Structure member whose offset is searched for. + * + * @return Member offset in bytes. + */ +#define NRFX_OFFSETOF(type, member) ((size_t)&(((type *)0)->member)) + +/**@brief Macro for checking if given lengths of EasyDMA transfers do not exceed + * the limit of the specified peripheral. + * + * @param[in] peripheral Peripheral to check the lengths against. + * @param[in] length1 First length to be checked. + * @param[in] length2 Second length to be checked (pass 0 if not needed). + * + * @retval true The length of buffers does not exceed the limit of the specified peripheral. + * @retval false The length of buffers exceeds the limit of the specified peripheral. + */ +#define NRFX_EASYDMA_LENGTH_VALIDATE(peripheral, length1, length2) \ + (((length1) < (1U << NRFX_CONCAT_2(peripheral, _EASYDMA_MAXCNT_SIZE))) && \ + ((length2) < (1U << NRFX_CONCAT_2(peripheral, _EASYDMA_MAXCNT_SIZE)))) + +/** + * @brief Macro for waiting until condition is met. + * + * @param[in] condition Condition to meet. + * @param[in] attempts Maximum number of condition checks. Must not be 0. + * @param[in] delay_us Delay between consecutive checks, in microseconds. + * @param[out] result Boolean variable to store the result of the wait process. + * Set to true if the condition is met or false otherwise. + */ +#define NRFX_WAIT_FOR(condition, attempts, delay_us, result) \ +do { \ + result = false; \ + uint32_t remaining_attempts = (attempts); \ + do { \ + if (condition) \ + { \ + result = true; \ + break; \ + } \ + NRFX_DELAY_US(delay_us); \ + } while (--remaining_attempts); \ +} while(0) + +/** + * @brief Macro for getting the ID number of the specified peripheral. + * + * For peripherals in Nordic SoCs, there is a direct relationship between their + * ID numbers and their base addresses. See the chapter "Peripheral interface" + * (section "Peripheral ID") in the Product Specification. + * + * @param[in] base_addr Peripheral base address or pointer. + * + * @return ID number associated with the specified peripheral. + */ +#define NRFX_PERIPHERAL_ID_GET(base_addr) (uint8_t)((uint32_t)(base_addr) >> 12) + +/** + * @brief Macro for getting the interrupt number assigned to a specific + * peripheral. + * + * For peripherals in Nordic SoCs, the IRQ number assigned to a peripheral is + * equal to its ID number. See the chapter "Peripheral interface" (sections + * "Peripheral ID" and "Interrupts") in the Product Specification. + * + * @param[in] base_addr Peripheral base address or pointer. + * + * @return Interrupt number associated with the specified peripheral. + */ +#define NRFX_IRQ_NUMBER_GET(base_addr) NRFX_PERIPHERAL_ID_GET(base_addr) + +/** @brief IRQ handler type. */ +typedef void (* nrfx_irq_handler_t)(void); + +/** @brief Driver state. */ +typedef enum +{ + NRFX_DRV_STATE_UNINITIALIZED, ///< Uninitialized. + NRFX_DRV_STATE_INITIALIZED, ///< Initialized but powered off. + NRFX_DRV_STATE_POWERED_ON, ///< Initialized and powered on. +} nrfx_drv_state_t; + + +/** + * @brief Function for checking if an object is placed in the Data RAM region. + * + * Several peripherals (the ones using EasyDMA) require the transfer buffers + * to be placed in the Data RAM region. This function can be used to check if + * this condition is met. + * + * @param[in] p_object Pointer to an object whose location is to be checked. + * + * @retval true The pointed object is located in the Data RAM region. + * @retval false The pointed object is not located in the Data RAM region. + */ +__STATIC_INLINE bool nrfx_is_in_ram(void const * p_object); + +/** + * @brief Function for checking if an object is aligned to a 32-bit word + * + * Several peripherals (the ones using EasyDMA) require the transfer buffers + * to be aligned to a 32-bit word. This function can be used to check if + * this condition is met. + * + * @param[in] p_object Pointer to an object whose location is to be checked. + * + * @retval true The pointed object is aligned to a 32-bit word. + * @retval false The pointed object is not aligned to a 32-bit word. + */ +__STATIC_INLINE bool nrfx_is_word_aligned(void const * p_object); + +/** + * @brief Function for getting the interrupt number for the specified peripheral. + * + * @param[in] p_reg Peripheral base pointer. + * + * @return Interrupt number associated with the pointed peripheral. + */ +__STATIC_INLINE IRQn_Type nrfx_get_irq_number(void const * p_reg); + +/** + * @brief Function for converting an INTEN register bit position to the + * corresponding event identifier. + * + * The event identifier is the offset between the event register address and + * the peripheral base address, and is equal (thus, can be directly cast) to + * the corresponding value of the enumerated type from HAL (nrf_*_event_t). + * + * @param[in] bit INTEN register bit position. + * + * @return Event identifier. + * + * @sa nrfx_event_to_bitpos + */ +__STATIC_INLINE uint32_t nrfx_bitpos_to_event(uint32_t bit); + +/** + * @brief Function for converting an event identifier to the corresponding + * INTEN register bit position. + * + * The event identifier is the offset between the event register address and + * the peripheral base address, and is equal (thus, can be directly cast) to + * the corresponding value of the enumerated type from HAL (nrf_*_event_t). + * + * @param[in] event Event identifier. + * + * @return INTEN register bit position. + * + * @sa nrfx_bitpos_to_event + */ +__STATIC_INLINE uint32_t nrfx_event_to_bitpos(uint32_t event); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE bool nrfx_is_in_ram(void const * p_object) +{ + return ((((uint32_t)p_object) & 0xE0000000u) == 0x20000000u); +} + +__STATIC_INLINE bool nrfx_is_word_aligned(void const * p_object) +{ + return ((((uint32_t)p_object) & 0x3u) == 0u); +} + +__STATIC_INLINE IRQn_Type nrfx_get_irq_number(void const * p_reg) +{ + return (IRQn_Type)NRFX_IRQ_NUMBER_GET(p_reg); +} + +__STATIC_INLINE uint32_t nrfx_bitpos_to_event(uint32_t bit) +{ + static const uint32_t event_reg_offset = 0x100u; + return event_reg_offset + (bit * sizeof(uint32_t)); +} + +__STATIC_INLINE uint32_t nrfx_event_to_bitpos(uint32_t event) +{ + static const uint32_t event_reg_offset = 0x100u; + return (event - event_reg_offset) / sizeof(uint32_t); +} + +#endif + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_COMMON_H__ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_errors.h b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_errors.h new file mode 100644 index 000000000..012af9c4f --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_errors.h @@ -0,0 +1,85 @@ +/** + * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_ERRORS_H__ +#define NRFX_ERRORS_H__ + +#if !NRFX_CHECK(NRFX_CUSTOM_ERROR_CODES) + +/** + * @defgroup nrfx_error_codes Global Error Codes + * @{ + * @ingroup nrfx + * + * @brief Global error code definitions. + */ + +/** @brief Base number of error codes. */ +#define NRFX_ERROR_BASE_NUM 0x0BAD0000 + +/** @brief Base number of driver error codes. */ +#define NRFX_ERROR_DRIVERS_BASE_NUM (NRFX_ERROR_BASE_NUM + 0x10000) + +/** @brief Enumerated type for error codes. */ +typedef enum { + NRFX_SUCCESS = (NRFX_ERROR_BASE_NUM + 0), ///< Operation performed successfully. + NRFX_ERROR_INTERNAL = (NRFX_ERROR_BASE_NUM + 1), ///< Internal error. + NRFX_ERROR_NO_MEM = (NRFX_ERROR_BASE_NUM + 2), ///< No memory for operation. + NRFX_ERROR_NOT_SUPPORTED = (NRFX_ERROR_BASE_NUM + 3), ///< Not supported. + NRFX_ERROR_INVALID_PARAM = (NRFX_ERROR_BASE_NUM + 4), ///< Invalid parameter. + NRFX_ERROR_INVALID_STATE = (NRFX_ERROR_BASE_NUM + 5), ///< Invalid state, operation disallowed in this state. + NRFX_ERROR_INVALID_LENGTH = (NRFX_ERROR_BASE_NUM + 6), ///< Invalid length. + NRFX_ERROR_TIMEOUT = (NRFX_ERROR_BASE_NUM + 7), ///< Operation timed out. + NRFX_ERROR_FORBIDDEN = (NRFX_ERROR_BASE_NUM + 8), ///< Operation is forbidden. + NRFX_ERROR_NULL = (NRFX_ERROR_BASE_NUM + 9), ///< Null pointer. + NRFX_ERROR_INVALID_ADDR = (NRFX_ERROR_BASE_NUM + 10), ///< Bad memory address. + NRFX_ERROR_BUSY = (NRFX_ERROR_BASE_NUM + 11), ///< Busy. + NRFX_ERROR_ALREADY_INITIALIZED = (NRFX_ERROR_BASE_NUM + 12), ///< Module already initialized. + + NRFX_ERROR_DRV_TWI_ERR_OVERRUN = (NRFX_ERROR_DRIVERS_BASE_NUM + 0), ///< TWI error: Overrun. + NRFX_ERROR_DRV_TWI_ERR_ANACK = (NRFX_ERROR_DRIVERS_BASE_NUM + 1), ///< TWI error: Address not acknowledged. + NRFX_ERROR_DRV_TWI_ERR_DNACK = (NRFX_ERROR_DRIVERS_BASE_NUM + 2) ///< TWI error: Data not acknowledged. +} nrfx_err_t; + +/** @} */ + +#endif // !NRFX_CHECK(NRFX_CUSTOM_ERROR_CODES) + +#endif // NRFX_ERRORS_H__ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_gpio.h b/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_gpio.h new file mode 100644 index 000000000..7811eeb4c --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_gpio.h @@ -0,0 +1,899 @@ +/** + * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_GPIO_H__ +#define NRF_GPIO_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef NRF_P0 +#define NRF_P0 NRF_GPIO +#endif + +#if (GPIO_COUNT == 1) +#define NUMBER_OF_PINS (P0_PIN_NUM) +#define GPIO_REG_LIST {NRF_P0} +#elif (GPIO_COUNT == 2) +#define NUMBER_OF_PINS (P0_PIN_NUM + P1_PIN_NUM) +#define GPIO_REG_LIST {NRF_P0, NRF_P1} +#else +#error "Not supported." +#endif + +#if defined(NRF52820_XXAA) +#include +#endif + +/** + * @defgroup nrf_gpio_hal GPIO HAL + * @{ + * @ingroup nrf_gpio + * @brief Hardware access layer for managing the GPIO peripheral. + */ + +#if defined(GPIO_LATCH_PIN0_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether the functionality of latching GPIO state change is present. */ +#define NRF_GPIO_LATCH_PRESENT +#endif + +/** @brief Macro for mapping port and pin numbers to values understandable for nrf_gpio functions. */ +#define NRF_GPIO_PIN_MAP(port, pin) (((port) << 5) | ((pin) & 0x1F)) + + +/** @brief Pin direction definitions. */ +typedef enum +{ + NRF_GPIO_PIN_DIR_INPUT = GPIO_PIN_CNF_DIR_Input, ///< Input. + NRF_GPIO_PIN_DIR_OUTPUT = GPIO_PIN_CNF_DIR_Output ///< Output. +} nrf_gpio_pin_dir_t; + +/** @brief Connection of input buffer. */ +typedef enum +{ + NRF_GPIO_PIN_INPUT_CONNECT = GPIO_PIN_CNF_INPUT_Connect, ///< Connect input buffer. + NRF_GPIO_PIN_INPUT_DISCONNECT = GPIO_PIN_CNF_INPUT_Disconnect ///< Disconnect input buffer. +} nrf_gpio_pin_input_t; + +/** + * @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin + * configuration. + */ +typedef enum +{ + NRF_GPIO_PIN_NOPULL = GPIO_PIN_CNF_PULL_Disabled, ///< Pin pull-up resistor disabled. + NRF_GPIO_PIN_PULLDOWN = GPIO_PIN_CNF_PULL_Pulldown, ///< Pin pull-down resistor enabled. + NRF_GPIO_PIN_PULLUP = GPIO_PIN_CNF_PULL_Pullup, ///< Pin pull-up resistor enabled. +} nrf_gpio_pin_pull_t; + +/** @brief Enumerator used for selecting output drive mode. */ +typedef enum +{ + NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< !< Standard '0', standard '1'. + NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< !< High-drive '0', standard '1'. + NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< !< Standard '0', high-drive '1'. + NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< !< High drive '0', high-drive '1'. + NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< !< Disconnect '0' standard '1'. + NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< !< Disconnect '0', high-drive '1'. + NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< !< Standard '0', disconnect '1'. + NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< !< High-drive '0', disconnect '1'. +} nrf_gpio_pin_drive_t; + +/** @brief Enumerator used for selecting the pin to sense high or low level on the pin input. */ +typedef enum +{ + NRF_GPIO_PIN_NOSENSE = GPIO_PIN_CNF_SENSE_Disabled, ///< Pin sense level disabled. + NRF_GPIO_PIN_SENSE_LOW = GPIO_PIN_CNF_SENSE_Low, ///< Pin sense low level. + NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High, ///< Pin sense high level. +} nrf_gpio_pin_sense_t; + + +/** + * @brief Function for configuring the GPIO pin range as output pins with normal drive strength. + * This function can be used to configure pin range as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases). + * + * @note For configuring only one pin as output, use @ref nrf_gpio_cfg_output. + * Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output. + * + * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). + * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). + */ +__STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end); + +/** + * @brief Function for configuring the GPIO pin range as input pins with given initial value set, hiding inner details. + * This function can be used to configure pin range as simple input. + * + * @note For configuring only one pin as input, use @ref nrf_gpio_cfg_input. + * Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable. + * + * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). + * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). + * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high). + */ +__STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, + uint32_t pin_range_end, + nrf_gpio_pin_pull_t pull_config); + +/** + * @brief Pin configuration function. + * + * The main pin configuration function. + * This function allows to set any aspect in PIN_CNF register. + * + * @param pin_number Specifies the pin number. + * @param dir Pin direction. + * @param input Connect or disconnect the input buffer. + * @param pull Pull configuration. + * @param drive Drive configuration. + * @param sense Pin sensing mechanism. + */ +__STATIC_INLINE void nrf_gpio_cfg( + uint32_t pin_number, + nrf_gpio_pin_dir_t dir, + nrf_gpio_pin_input_t input, + nrf_gpio_pin_pull_t pull, + nrf_gpio_pin_drive_t drive, + nrf_gpio_pin_sense_t sense); + +/** + * @brief Function for configuring the given GPIO pin number as output, hiding inner details. + * This function can be used to configure a pin as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases). + * + * @note Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output. + * + * @param pin_number Specifies the pin number. + */ +__STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number); + +/** + * @brief Function for configuring the given GPIO pin number as input, hiding inner details. + * This function can be used to configure a pin as simple input. + * + * @note Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable. + * + * @param pin_number Specifies the pin number. + * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high). + */ +__STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config); + +/** + * @brief Function for resetting pin configuration to its default state. + * + * @param pin_number Specifies the pin number. + */ +__STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number); + +/** + * @brief Function for configuring the given GPIO pin number as a watcher. Only input is connected. + * + * @param pin_number Specifies the pin number. + * + */ +__STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number); + +/** + * @brief Function for disconnecting input for the given GPIO. + * + * @param pin_number Specifies the pin number. + */ +__STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number); + +/** + * @brief Function for configuring the given GPIO pin number as input, hiding inner details. + * This function can be used to configure pin range as simple input. + * Sense capability on the pin is configurable and input is connected to buffer so that the GPIO->IN register is readable. + * + * @param pin_number Specifies the pin number. + * @param pull_config State of the pin pull resistor (no pull, pulled down, or pulled high). + * @param sense_config Sense level of the pin (no sense, sense low, or sense high). + */ +__STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, + nrf_gpio_pin_pull_t pull_config, + nrf_gpio_pin_sense_t sense_config); + +/** + * @brief Function for configuring sense level for the given GPIO. + * + * @param pin_number Specifies the pin number. + * @param sense_config Sense configuration. + */ +__STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config); + +/** + * @brief Function for setting the direction for a GPIO pin. + * + * @param pin_number Specifies the pin number for which to set the direction. + * @param direction Specifies the direction. + */ +__STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction); + +/** + * @brief Function for setting a GPIO pin. + * + * For this function to have any effect, the pin must be configured as an output. + * + * @param pin_number Specifies the pin number to be set. + */ +__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number); + +/** + * @brief Function for clearing a GPIO pin. + * + * For this function to have any effect, the pin must be configured as an output. + * + * @param pin_number Specifies the pin number to clear. + */ +__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number); + +/** + * @brief Function for toggling a GPIO pin. + * + * For this function to have any effect, the pin must be configured as an output. + * + * @param pin_number Specifies the pin number to toggle. + */ +__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number); + +/** + * @brief Function for writing a value to a GPIO pin. + * + * For this function to have any effect, the pin must be configured as an output. + * + * @param pin_number Specifies the pin number to write. + * @param value Specifies the value to be written to the pin. + * @arg 0 Clears the pin. + * @arg >=1 Sets the pin. + */ +__STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value); + +/** + * @brief Function for reading the input level of a GPIO pin. + * + * If the value returned by this function is to be valid, the pin's input buffer must be connected. + * + * @param pin_number Specifies the pin number to read. + * + * @return 0 if the pin input level is low. Positive value if the pin is high. + */ +__STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number); + +/** + * @brief Function for reading the output level of a GPIO pin. + * + * @param pin_number Specifies the pin number to read. + * + * @return 0 if the pin output level is low. Positive value if pin output is high. + */ +__STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number); + +/** + * @brief Function for reading the sense configuration of a GPIO pin. + * + * @param pin_number Specifies the pin number to read. + * + * @return Sense configuration. + */ +__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number); + +/** + * @brief Function for reading the direction configuration of a GPIO pin. + * + * @param pin_number Specifies the pin number to read. + * + * @return Direction configuration. + */ +__STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number); + +/** + * @brief Function for reading the status of GPIO pin input buffer. + * + * @param pin_number Pin number to be read. + * + * @retval Input buffer configuration. + */ +__STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number); + +/** + * @brief Function for reading the pull configuration of a GPIO pin. + * + * @param pin_number Specifies the pin number to read. + * + * @retval Pull configuration. + */ +__STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number); + +/** + * @brief Function for setting output direction on the selected pins on the given port. + * + * @param p_reg Pointer to the structure of registers of the peripheral. + * @param out_mask Mask specifying the pins to set as output. + */ +__STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask); + +/** + * @brief Function for setting input direction on selected pins on a given port. + * + * @param p_reg Pointer to the structure of registers of the peripheral. + * @param in_mask Mask that specifies the pins to be set as input. + */ +__STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask); + +/** + * @brief Function for writing the direction configuration of the GPIO pins in the given port. + * + * @param p_reg Pointer to the structure of registers of the peripheral. + * @param dir_mask Mask that specifies the direction of pins. Bit set means that the given pin is configured as output. + */ +__STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t dir_mask); + +/** + * @brief Function for reading the direction configuration of a GPIO port. + * + * @param p_reg Pointer to the structure of registers of the peripheral. + * + * @return Pin configuration of the current direction settings. Bit set means that the given pin is configured as output. + */ +__STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg); + +/** + * @brief Function for reading the input signals of the GPIO pins on the given port. + * + * @param p_reg Pointer to the peripheral registers structure. + * + * @return Port input values. + */ +__STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg); + +/** + * @brief Function for reading the output signals of the GPIO pins on the given port. + * + * @param p_reg Pointer to the peripheral registers structure. + * + * @return Port output values. + */ +__STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg); + +/** + * @brief Function for writing the GPIO pins output on a given port. + * + * @param p_reg Pointer to the structure of registers of the peripheral. + * @param value Output port mask. + */ +__STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value); + +/** + * @brief Function for setting high level on selected the GPIO pins on the given port. + * + * @param p_reg Pointer to the structure of registers of the peripheral. + * @param set_mask Mask with pins to be set as logical high level. + */ +__STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask); + +/** + * @brief Function for setting low level on selected the GPIO pins on the given port. + * + * @param p_reg Pointer to the structure of registers of the peripheral. + * @param clr_mask Mask with pins to be set as logical low level. + */ +__STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask); + +/** + * @brief Function for reading pin state of multiple consecutive ports. + * + * @param start_port Index of the first port to read. + * @param length Number of ports to read. + * @param p_masks Pointer to output array where port states will be stored. + */ +__STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, uint32_t * p_masks); + +#if defined(NRF_GPIO_LATCH_PRESENT) +/** + * @brief Function for reading latch state of multiple consecutive ports. + * + * @param start_port Index of the first port to read. + * @param length Number of ports to read. + * @param p_masks Pointer to output array where latch states will be stored. + */ +__STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, + uint32_t length, + uint32_t * p_masks); + +/** + * @brief Function for reading and immediate clearing latch state of multiple consecutive ports. + * + * @param start_port Index of the first port to read and clear. + * @param length Number of ports to read and clear. + * @param p_masks Pointer to output array where latch states will be stored. + */ +__STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port, + uint32_t length, + uint32_t * p_masks); + +/** + * @brief Function for reading latch state of single pin. + * + * @param pin_number Pin number. + * + * @return 0 if latch is not set. Positive value otherwise. + */ +__STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number); + +/** + * @brief Function for clearing latch state of a single pin. + * + * @param pin_number Pin number. + */ +__STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number); +#endif // defined(NRF_GPIO_LATCH_PRESENT) + +/** + * @brief Function for checking if provided pin is present on the MCU. + * + * @param[in] pin_number Number of the pin to be checked. + * + * @retval true Pin is present. + * @retval false Pin is not present. + */ +__STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +/** + * @brief Function for extracting port and the relative pin number from the absolute pin number. + * + * @param[in,out] p_pin Pointer to the absolute pin number overriden by the pin number that is relative to the port. + * + * @return Pointer to port register set. + */ +__STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin) +{ + NRFX_ASSERT(nrf_gpio_pin_present_check(*p_pin)); +#if (GPIO_COUNT == 1) + return NRF_P0; +#else + if (*p_pin < P0_PIN_NUM) + { + return NRF_P0; + } + else + { + *p_pin = *p_pin & 0x1F; + return NRF_P1; + } +#endif +} + + +__STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end) +{ + /*lint -e{845} // A zero has been given as right argument to operator '|'" */ + for (; pin_range_start <= pin_range_end; pin_range_start++) + { + nrf_gpio_cfg_output(pin_range_start); + } +} + + +__STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, + uint32_t pin_range_end, + nrf_gpio_pin_pull_t pull_config) +{ + /*lint -e{845} // A zero has been given as right argument to operator '|'" */ + for (; pin_range_start <= pin_range_end; pin_range_start++) + { + nrf_gpio_cfg_input(pin_range_start, pull_config); + } +} + + +__STATIC_INLINE void nrf_gpio_cfg( + uint32_t pin_number, + nrf_gpio_pin_dir_t dir, + nrf_gpio_pin_input_t input, + nrf_gpio_pin_pull_t pull, + nrf_gpio_pin_drive_t drive, + nrf_gpio_pin_sense_t sense) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos) + | ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) + | ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos) + | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) + | ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos); +} + + +__STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number) +{ + nrf_gpio_cfg( + pin_number, + NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); +} + + +__STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config) +{ + nrf_gpio_cfg( + pin_number, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + pull_config, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); +} + + +__STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number) +{ + nrf_gpio_cfg( + pin_number, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); +} + + +__STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + /*lint -e{845} // A zero has been given as right argument to operator '|'" */ + uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk; + + reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos); +} + + +__STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + /*lint -e{845} // A zero has been given as right argument to operator '|'" */ + uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk; + + reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos); +} + + +__STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, + nrf_gpio_pin_pull_t pull_config, + nrf_gpio_pin_sense_t sense_config) +{ + nrf_gpio_cfg( + pin_number, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + pull_config, + NRF_GPIO_PIN_S0S1, + sense_config); +} + + +__STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + /*lint -e{845} // A zero has been given as right argument to operator '|'" */ + reg->PIN_CNF[pin_number] &= ~GPIO_PIN_CNF_SENSE_Msk; + reg->PIN_CNF[pin_number] |= (sense_config << GPIO_PIN_CNF_SENSE_Pos); +} + + +__STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction) +{ + if (direction == NRF_GPIO_PIN_DIR_INPUT) + { + nrf_gpio_cfg( + pin_number, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); + } + else + { + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + reg->DIRSET = (1UL << pin_number); + } +} + + +__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + nrf_gpio_port_out_set(reg, 1UL << pin_number); +} + + +__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + nrf_gpio_port_out_clear(reg, 1UL << pin_number); +} + + +__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + uint32_t pins_state = reg->OUT; + + reg->OUTSET = (~pins_state & (1UL << pin_number)); + reg->OUTCLR = (pins_state & (1UL << pin_number)); +} + + +__STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value) +{ + if (value == 0) + { + nrf_gpio_pin_clear(pin_number); + } + else + { + nrf_gpio_pin_set(pin_number); + } +} + + +__STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL); +} + + +__STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + return ((nrf_gpio_port_out_read(reg) >> pin_number) & 1UL); +} + + +__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] & + GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos); +} + + +__STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] & + GPIO_PIN_CNF_DIR_Msk) >> GPIO_PIN_CNF_DIR_Pos); +} + +__STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + return (nrf_gpio_pin_input_t)((reg->PIN_CNF[pin_number] & + GPIO_PIN_CNF_INPUT_Msk) >> GPIO_PIN_CNF_INPUT_Pos); +} + +__STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + return (nrf_gpio_pin_pull_t)((reg->PIN_CNF[pin_number] & + GPIO_PIN_CNF_PULL_Msk) >> GPIO_PIN_CNF_PULL_Pos); +} + + +__STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask) +{ + p_reg->DIRSET = out_mask; +} + + +__STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask) +{ + p_reg->DIRCLR = in_mask; +} + + +__STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t value) +{ + p_reg->DIR = value; +} + + +__STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg) +{ + return p_reg->DIR; +} + + +__STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg) +{ + return p_reg->IN; +} + + +__STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg) +{ + return p_reg->OUT; +} + + +__STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value) +{ + p_reg->OUT = value; +} + + +__STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask) +{ + p_reg->OUTSET = set_mask; +} + + +__STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask) +{ + p_reg->OUTCLR = clr_mask; +} + + +__STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, uint32_t * p_masks) +{ + NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST; + + NRFX_ASSERT(start_port + length <= GPIO_COUNT); + uint32_t i; + + for (i = start_port; i < (start_port + length); i++) + { + *p_masks = nrf_gpio_port_in_read(gpio_regs[i]); + p_masks++; + } +} + + +#if defined(NRF_GPIO_LATCH_PRESENT) +__STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, + uint32_t length, + uint32_t * p_masks) +{ + NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST; + uint32_t i; + + for (i = start_port; i < (start_port + length); i++) + { + *p_masks = gpio_regs[i]->LATCH; + p_masks++; + } +} + +__STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port, + uint32_t length, + uint32_t * p_masks) +{ + NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST; + uint32_t i; + + for (i = start_port; i < (start_port + length); i++) + { + *p_masks = gpio_regs[i]->LATCH; + + // The LATCH register is cleared by writing a '1' to the bit that shall be cleared. + gpio_regs[i]->LATCH = *p_masks; + + p_masks++; + } +} + +__STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + return (reg->LATCH & (1 << pin_number)) ? 1 : 0; +} + + +__STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + reg->LATCH = (1 << pin_number); +} +#endif // defined(NRF_GPIO_LATCH_PRESENT) + +__STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number) +{ + uint32_t port = pin_number >> 5; + uint32_t mask = 0; + + switch (port) + { +#ifdef P0_FEATURE_PINS_PRESENT + case 0: + mask = P0_FEATURE_PINS_PRESENT; +#if defined(NRF52820_XXAA) && defined(DEVELOP_IN_NRF52833) + /* Allow use of the following additional GPIOs that are connected to LEDs and buttons + * on the nRF52833 DK: + * - P0.11 - Button 1 + * - P0.12 - Button 2 + * - P0.13 - LED 1 + * - P0.24 - Button 3 + * - P0.25 - Button 4 + */ + mask |= 0x03003800; +#endif // defined(NRF52820_XXAA) && defined(DEVELOP_IN_NRF52833) + break; +#endif +#ifdef P1_FEATURE_PINS_PRESENT + case 1: + mask = P1_FEATURE_PINS_PRESENT; + break; +#endif + } + + pin_number &= 0x1F; + + return (mask & (1UL << pin_number)) ? true : false; +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_GPIO_H__ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/mdk/nrf52820_peripherals.h b/source/hic_hal/nordic/nrf52820/nrfx/mdk/nrf52820_peripherals.h new file mode 100644 index 000000000..0dd2dcba0 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx/mdk/nrf52820_peripherals.h @@ -0,0 +1,240 @@ +/* + +Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef _NRF52820_PERIPHERALS_H +#define _NRF52820_PERIPHERALS_H + +/* Clock Peripheral */ +#define CLOCK_PRESENT +#define CLOCK_COUNT 1 + +/* Power Peripheral */ +#define POWER_PRESENT +#define POWER_COUNT 1 + +#define POWER_FEATURE_RAM_REGISTERS_PRESENT +#define POWER_FEATURE_RAM_REGISTERS_COUNT 4 + +#define POWER_FEATURE_VDDH_PRESENT + +/* Non-Volatile Memory Controller */ +#define NVMC_PRESENT +#define NVMC_COUNT 1 + +/* Systick timer */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 + +/* Software Interrupts */ +#define SWI_PRESENT +#define SWI_COUNT 6 + +/* GPIO */ +#define GPIO_PRESENT +#define GPIO_COUNT 1 + +#define P0_PIN_NUM (18) +#define P0_FEATURE_PINS_PRESENT (nrf52_errata_230() ? 0xF0168E3Ful : 0x7017C1FFul) + +/* ACL */ +#define ACL_PRESENT + +#define ACL_REGIONS_COUNT 8 + +/* Radio */ +#define RADIO_PRESENT +#define RADIO_COUNT 1 + +#define RADIO_EASYDMA_MAXCNT_SIZE 16 +#define RADIO_FEATURE_IEEE_802_15_4_PRESENT + +#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos8dBm + +/* Accelerated Address Resolver */ +#define AAR_PRESENT +#define AAR_COUNT 1 + +#define AAR_MAX_IRK_NUM 16 + +/* AES Electronic CodeBook mode encryption */ +#define ECB_PRESENT +#define ECB_COUNT 1 + +/* AES CCM mode encryption */ +#define CCM_PRESENT +#define CCM_COUNT 1 + +/* Peripheral to Peripheral Interconnect */ +#define PPI_PRESENT +#define PPI_COUNT 1 + +#define PPI_CH_NUM 20 +#define PPI_FIXED_CH_NUM 12 +#define PPI_GROUP_NUM 6 +#define PPI_FEATURE_FORKS_PRESENT + +/* Event Generator Unit */ +#define EGU_PRESENT +#define EGU_COUNT 6 + +#define EGU0_CH_NUM 16 +#define EGU1_CH_NUM 16 +#define EGU2_CH_NUM 16 +#define EGU3_CH_NUM 16 +#define EGU4_CH_NUM 16 +#define EGU5_CH_NUM 16 + +/* Timer/Counter */ +#define TIMER_PRESENT +#define TIMER_COUNT 4 + +#define TIMER0_MAX_SIZE 32 +#define TIMER1_MAX_SIZE 32 +#define TIMER2_MAX_SIZE 32 +#define TIMER3_MAX_SIZE 32 + +#define TIMER0_CC_NUM 4 +#define TIMER1_CC_NUM 4 +#define TIMER2_CC_NUM 4 +#define TIMER3_CC_NUM 6 + +/* Real Time Counter */ +#define RTC_PRESENT +#define RTC_COUNT 2 + +#define RTC0_CC_NUM 3 +#define RTC1_CC_NUM 4 + +/* RNG */ +#define RNG_PRESENT +#define RNG_COUNT 1 + +/* Watchdog Timer */ +#define WDT_PRESENT +#define WDT_COUNT 1 + +/* Temperature Sensor */ +#define TEMP_PRESENT +#define TEMP_COUNT 1 + +/* Serial Peripheral Interface Master */ +#define SPI_PRESENT +#define SPI_COUNT 2 + +/* Serial Peripheral Interface Master with DMA */ +#define SPIM_PRESENT +#define SPIM_COUNT 2 + +#define SPIM0_MAX_DATARATE 8 +#define SPIM1_MAX_DATARATE 8 + +#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0 +#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0 + +#define SPIM0_FEATURE_DCX_PRESENT 0 +#define SPIM1_FEATURE_DCX_PRESENT 0 + +#define SPIM0_FEATURE_RXDELAY_PRESENT 0 +#define SPIM1_FEATURE_RXDELAY_PRESENT 0 + +#define SPIM0_EASYDMA_MAXCNT_SIZE 16 +#define SPIM1_EASYDMA_MAXCNT_SIZE 16 + +/* Serial Peripheral Interface Slave with DMA*/ +#define SPIS_PRESENT +#define SPIS_COUNT 2 + +#define SPIS0_EASYDMA_MAXCNT_SIZE 16 +#define SPIS1_EASYDMA_MAXCNT_SIZE 16 + +/* Two Wire Interface Master */ +#define TWI_PRESENT +#define TWI_COUNT 2 + +/* Two Wire Interface Master with DMA */ +#define TWIM_PRESENT +#define TWIM_COUNT 2 + +#define TWIM0_EASYDMA_MAXCNT_SIZE 16 +#define TWIM1_EASYDMA_MAXCNT_SIZE 16 + +/* Two Wire Interface Slave with DMA */ +#define TWIS_PRESENT +#define TWIS_COUNT 2 + +#define TWIS0_EASYDMA_MAXCNT_SIZE 16 +#define TWIS1_EASYDMA_MAXCNT_SIZE 16 + +/* Universal Asynchronous Receiver-Transmitter */ +#define UART_PRESENT +#define UART_COUNT 1 + +/* Universal Asynchronous Receiver-Transmitter with DMA */ +#define UARTE_PRESENT +#define UARTE_COUNT 1 + +#define UARTE0_EASYDMA_MAXCNT_SIZE 16 + +/* Quadrature Decoder */ +#define QDEC_PRESENT +#define QDEC_COUNT 1 + +/* GPIO Tasks and Events */ +#define GPIOTE_PRESENT +#define GPIOTE_COUNT 1 + +#define GPIOTE_CH_NUM 8 + +#define GPIOTE_FEATURE_SET_PRESENT +#define GPIOTE_FEATURE_CLR_PRESENT + +/* Comparator */ +#define COMP_PRESENT +#define COMP_COUNT 1 + + +/* Universal Serial Bus Device */ +#define USBD_PRESENT +#define USBD_COUNT 1 + +#define USBD_EASYDMA_MAXCNT_SIZE 7 + +#endif // _NRF52820_PERIPHERALS_H diff --git a/source/hic_hal/nordic/nrf52820/nrfx/mdk/nrf_peripherals.h b/source/hic_hal/nordic/nrf52820/nrfx/mdk/nrf_peripherals.h new file mode 100644 index 000000000..3f9e7b7a2 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx/mdk/nrf_peripherals.h @@ -0,0 +1,79 @@ +/* + +Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF_PERIPHERALS_H__ +#define NRF_PERIPHERALS_H__ + +/*lint ++flb "Enter library region */ + +#if defined(NRF51) + #include "nrf51_peripherals.h" + +#elif defined (NRF52805_XXAA) + #include "nrf52805_peripherals.h" +#elif defined(NRF52810_XXAA) + #include "nrf52810_peripherals.h" +#elif defined(NRF52811_XXAA) + #include "nrf52811_peripherals.h" +#elif defined(NRF52820_XXAA) + #include "nrf52820_peripherals.h" +#elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB) + #include "nrf52832_peripherals.h" +#elif defined (NRF52833_XXAA) + #include "nrf52833_peripherals.h" +#elif defined(NRF52840_XXAA) + #include "nrf52840_peripherals.h" + +#elif defined (NRF5340_XXAA_APPLICATION) + #include "nrf5340_application_peripherals.h" +#elif defined (NRF5340_XXAA_NETWORK) + #include "nrf5340_network_peripherals.h" + +#elif defined(NRF9160_XXAA) + #include "nrf9160_peripherals.h" + +#else + #error "Device must be defined. See nrf.h." +#endif + +/*lint --flb "Leave library region" */ + +#endif // NRF_PERIPHERALS_H__ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/nrfx.h b/source/hic_hal/nordic/nrf52820/nrfx/nrfx.h new file mode 100644 index 000000000..575b7d9a5 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx/nrfx.h @@ -0,0 +1,49 @@ +/** + * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_H__ +#define NRFX_H__ + +#include +#include +#include +#include + +#endif // NRFX_H__ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_glue.h b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_glue.h new file mode 100644 index 000000000..e496b46e8 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_glue.h @@ -0,0 +1,267 @@ +/** + * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_GLUE_H__ +#define NRFX_GLUE_H__ + +// THIS IS A TEMPLATE FILE. +// It should be copied to a suitable location within the host environment into +// which nrfx is integrated, and the following macros should be provided with +// appropriate implementations. +// And this comment should be removed from the customized file. + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_glue nrfx_glue.h + * @{ + * @ingroup nrfx + * + * @brief This file contains macros that should be implemented according to + * the needs of the host environment into which @em nrfx is integrated. + */ + +// Uncomment this line to use the standard MDK way of binding IRQ handlers +// at linking time. +//#include + +//------------------------------------------------------------------------------ + +/** + * @brief Macro for placing a runtime assertion. + * + * @param expression Expression to be evaluated. + */ +#define NRFX_ASSERT(expression) + +/** + * @brief Macro for placing a compile time assertion. + * + * @param expression Expression to be evaluated. + */ +#define NRFX_STATIC_ASSERT(expression) + +//------------------------------------------------------------------------------ + +/** + * @brief Macro for setting the priority of a specific IRQ. + * + * @param irq_number IRQ number. + * @param priority Priority to be set. + */ +#define NRFX_IRQ_PRIORITY_SET(irq_number, priority) + +/** + * @brief Macro for enabling a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_ENABLE(irq_number) + +/** + * @brief Macro for checking if a specific IRQ is enabled. + * + * @param irq_number IRQ number. + * + * @retval true If the IRQ is enabled. + * @retval false Otherwise. + */ +#define NRFX_IRQ_IS_ENABLED(irq_number) + +/** + * @brief Macro for disabling a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_DISABLE(irq_number) + +/** + * @brief Macro for setting a specific IRQ as pending. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_PENDING_SET(irq_number) + +/** + * @brief Macro for clearing the pending status of a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_PENDING_CLEAR(irq_number) + +/** + * @brief Macro for checking the pending status of a specific IRQ. + * + * @retval true If the IRQ is pending. + * @retval false Otherwise. + */ +#define NRFX_IRQ_IS_PENDING(irq_number) + +/** @brief Macro for entering into a critical section. */ +#define NRFX_CRITICAL_SECTION_ENTER() + +/** @brief Macro for exiting from a critical section. */ +#define NRFX_CRITICAL_SECTION_EXIT() + +//------------------------------------------------------------------------------ + +/** + * @brief When set to a non-zero value, this macro specifies that + * @ref nrfx_coredep_delay_us uses a precise DWT-based solution. + * A compilation error is generated if the DWT unit is not present + * in the SoC used. + */ +#define NRFX_DELAY_DWT_BASED 0 + +/** + * @brief Macro for delaying the code execution for at least the specified time. + * + * @param us_time Number of microseconds to wait. + */ +#define NRFX_DELAY_US(us_time) + +//------------------------------------------------------------------------------ + +/** @brief Atomic 32-bit unsigned type. */ +#define nrfx_atomic_t + +/** + * @brief Macro for storing a value to an atomic object and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value to store. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_STORE(p_data, value) + +/** + * @brief Macro for running a bitwise OR operation on an atomic object and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the OR operation. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_OR(p_data, value) + +/** + * @brief Macro for running a bitwise AND operation on an atomic object + * and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the AND operation. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_AND(p_data, value) + +/** + * @brief Macro for running a bitwise XOR operation on an atomic object + * and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the XOR operation. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_XOR(p_data, value) + +/** + * @brief Macro for running an addition operation on an atomic object + * and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the ADD operation. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_ADD(p_data, value) + +/** + * @brief Macro for running a subtraction operation on an atomic object + * and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the SUB operation. + * + * @return Previous value of the atomic object. + */ +#define NRFX_ATOMIC_FETCH_SUB(p_data, value) + +//------------------------------------------------------------------------------ + +/** + * @brief When set to a non-zero value, this macro specifies that the + * @ref nrfx_error_codes and the @ref nrfx_err_t type itself are defined + * in a customized way and the default definitions from @c + * should not be used. + */ +#define NRFX_CUSTOM_ERROR_CODES 0 + +//------------------------------------------------------------------------------ + +/** @brief Bitmask that defines DPPI channels that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI_CHANNELS_USED 0 + +/** @brief Bitmask that defines DPPI groups that are reserved for use outside of the nrfx library. */ +#define NRFX_DPPI_GROUPS_USED 0 + +/** @brief Bitmask that defines PPI channels that are reserved for use outside of the nrfx library. */ +#define NRFX_PPI_CHANNELS_USED 0 + +/** @brief Bitmask that defines PPI groups that are reserved for use outside of the nrfx library. */ +#define NRFX_PPI_GROUPS_USED 0 + +/** @brief Bitmask that defines SWI instances that are reserved for use outside of the nrfx library. */ +#define NRFX_SWI_USED 0 + +/** @brief Bitmask that defines TIMER instances that are reserved for use outside of the nrfx library. */ +#define NRFX_TIMERS_USED 0 + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_GLUE_H__ diff --git a/source/hic_hal/nordic/nrf52820/uart.c b/source/hic_hal/nordic/nrf52820/uart.c index 4ec8c6cfb..e488410b5 100644 --- a/source/hic_hal/nordic/nrf52820/uart.c +++ b/source/hic_hal/nordic/nrf52820/uart.c @@ -1,6 +1,6 @@ /** * @file uart.c - * @brief UART Function for nrf52833 HIC + * @brief UART Function for nrf52820 HIC * * DAPLink Interface Firmware * Copyright (c) 2021, Arm Limited, All Rights Reserved diff --git a/source/hic_hal/nordic/nrf52820/usbd_nrf52833.c b/source/hic_hal/nordic/nrf52820/usbd_nrf52820.c similarity index 100% rename from source/hic_hal/nordic/nrf52820/usbd_nrf52833.c rename to source/hic_hal/nordic/nrf52820/usbd_nrf52820.c From 9baf055e702817d6bdafff4ee777b9d4f8c08cc1 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 14 Jul 2021 07:08:26 -0500 Subject: [PATCH 405/617] nrf52820_hic: import nRF528xx RL-USB module --- .../hic_hal/nordic/nrf52820/usbd_nRF528xx.c | 821 ++++++++++++++++++ .../hic_hal/nordic/nrf52820/usbd_nrf52820.c | 343 -------- 2 files changed, 821 insertions(+), 343 deletions(-) create mode 100644 source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c delete mode 100644 source/hic_hal/nordic/nrf52820/usbd_nrf52820.c diff --git a/source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c b/source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c new file mode 100644 index 000000000..91fd9fe47 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c @@ -0,0 +1,821 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 14. July 2021 + * $Revision: V1.0 + * + * Project: USB Device Hardware Layer module for RL-USB v4.70 for + * Nordic Semiconductor nRF528xx Device Series + * -------------------------------------------------------------------------- + * Defines used for driver configuration (at compile time): + * + * USBD_EP_NUM_MAX: defines maximum number of IN/OUT Endpoint pairs + * that driver will support with Control Endpoint 0 + * included, this value impacts driver memory + * requirements + * - default value: 8 + * - maximum value: 8 + * + * __DAPLINK: compatible with DAPLink + * -------------------------------------------------------------------------- + * Notes: + * - this driver does not implement Isochronous Endpoint due to limitation + * that only Endpoint 8 is available for Isochronous Endpoint + * -------------------------------------------------------------------------- */ + +/* History: + * Version 1.0 + * Initial release + */ + +#include + +#ifdef __DAPLINK +#include "usb.h" +#else +#include +#endif +#include "rl_usb.h" + +#include "nrf.h" /* Device header */ +#include "nrf52_erratas.h" + +#define __NO_USB_LIB_C +#include "usb_config.c" + +/* Definition for overriding maximum number of endpoints supported by + this driver, used for reducing RAM memory consumption. */ +#ifndef USBD_EP_NUM_MAX +#define USBD_EP_NUM_MAX (8) +#elif (USBD_EP_NUM_MAX == 0) +#error Maximum endpoints cannot be 0! Please increase USBD_EP_NUM_MAX! +#elif (USBD_EP_NUM_MAX > 8) +#error Maximum endpoints supported is 8! Please reduce USBD_EP_NUM_MAX! +#endif + + +/* Typedefs */ +typedef struct { /* Endpoint configuration */ + uint16_t max_packet_size; +} ep_config_t; + + +/* Local variables */ +#ifdef __RTX +static OS_MUT usbd_hw_mutex; +#endif +static uint32_t setup_packet_available; +static uint32_t ep0_dir; +static ep_config_t ep_config[2][USBD_EP_NUM_MAX]; +static uint32_t ep_buf [2][USBD_EP_NUM_MAX][64/4]; + + +/* Helper functions */ + +/* Enable USB Device */ +void usbd_enable (void) { + uint32_t i; + + if (nrf52_errata_187()) { /* If errata [187] (USBD: USB cannot be enabled) is present */ + *(volatile uint32_t *)0x4006EC00 = 0x00009375; + *(volatile uint32_t *)0x4006ED14 = 0x00000003; + *(volatile uint32_t *)0x4006EC00 = 0x00009375; + } + + /* Enable the peripheral */ + NRF_USBD->ENABLE = USBD_ENABLE_ENABLE_Enabled << USBD_ENABLE_ENABLE_Pos; + + /* Waiting for peripheral to enable (max 10 ms), this should take a few µs */ + for (i = 160000U; i != 0U; i--) { + if ((NRF_USBD->EVENTCAUSE & USBD_EVENTCAUSE_READY_Msk) != 0U) { + break; + } + } + + /* Enable ready event */ + NRF_USBD->EVENTCAUSE &= ~USBD_EVENTCAUSE_READY_Msk; + + if (nrf52_errata_187()) { /* If errata [187] (USBD: USB cannot be enabled) is present */ + *(volatile uint32_t *)0x4006EC00 = 0x00009375; + *(volatile uint32_t *)0x4006ED14 = 0x00000000; + *(volatile uint32_t *)0x4006EC00 = 0x00009375; + } +} + +/* Disable USB Device */ +void usbd_disable (void) { + NRF_USBD->ENABLE = USBD_ENABLE_ENABLE_Disabled << USBD_ENABLE_ENABLE_Pos; +} + +/* Do EasyDMA transfer to/from USB controller's internal buffer */ +void usbd_dma (uint32_t EPNum, uint32_t *buf, uint32_t cnt) { + uint8_t ep_dir, ep_num; + uint16_t len, ep_max_len; + + ep_dir = (EPNum & USB_ENDPOINT_DIRECTION_MASK) >> 7; + ep_num = EPNum & ~USB_ENDPOINT_DIRECTION_MASK; + ep_max_len = ep_config[ep_dir][ep_num].max_packet_size; + len = cnt; + + if (ep_num >= USBD_EP_NUM_MAX) { /* If ep_num is not available */ + return; + } + + if (len > ep_max_len) { + len = ep_max_len; + } + +#ifdef __RTX + os_mut_wait(&usbd_hw_mutex, 0xFFFFU); +#endif + + if (ep_dir != 0U) { /* If IN endpoint */ + if ((ep_num == 0U) && (cnt == 0U)) { + /* Status stage send ZLP IN */ + NRF_USBD->TASKS_EP0STATUS = USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger; + } else { + NRF_USBD->EPIN[ep_num].PTR = (uint32_t)buf; + NRF_USBD->EPIN[ep_num].MAXCNT = len; + NRF_USBD->TASKS_STARTEPIN[ep_num] = USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Trigger; + while (NRF_USBD->EVENTS_ENDEPIN[ep_num] == 0U); + NRF_USBD->EVENTS_ENDEPIN[ep_num] = 0U; + } + } else { /* If OUT endpoint */ + if ((ep_num == 0U) && (cnt == 0U)) { + /* Status stage receive ZLP OUT */ + NRF_USBD->TASKS_EP0STATUS = USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger; + } else { + NRF_USBD->EPOUT[ep_num].PTR = (uint32_t)buf; + NRF_USBD->EPOUT[ep_num].MAXCNT = len; + NRF_USBD->TASKS_STARTEPOUT[ep_num]= USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Trigger; + while (NRF_USBD->EVENTS_ENDEPOUT[ep_num] == 0U); + NRF_USBD->EVENTS_ENDEPOUT[ep_num] = 0U; + if ((ep_num == 0U) && (ep0_dir == 0U)) { + /* Allow OUT data stage on Control Endpoint 0 */ + NRF_USBD->TASKS_EP0RCVOUT = USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Msk; + NRF_USBD->TASKS_EP0STATUS = USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger; + } + } + } + +#ifdef __RTX + os_mut_release(&usbd_hw_mutex); +#endif +} + + +/* Driver functions */ + +/* + * USB Device Initialize Function + * Called by the User to initialize USB Device + * Return Value: None + */ + +void USBD_Init (void) { + +#ifdef __RTX + os_mut_init(&usbd_hw_mutex); +#endif + + if (nrf52_errata_223()) { /* If errata [223] (USBD: Unexpected behavior after reset) is present */ + usbd_enable(); + usbd_disable(); + } + + usbd_enable(); + + /* Enable only USB Reset interrupt */ + NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk; + + NVIC_ClearPendingIRQ(USBD_IRQn); + NVIC_EnableIRQ(USBD_IRQn); +} + + +/* + * USB Device Connect Function + * Called by the User to Connect/Disconnect USB Device + * Parameters: con: Connect/Disconnect + * Return Value: None + */ + +void USBD_Connect (uint32_t con) { + if (con != 0U) { /* Connect */ + NRF_USBD->USBPULLUP |= USBD_USBPULLUP_CONNECT_Msk; + } else { /* Disconnect */ + NRF_USBD->USBPULLUP &= ~USBD_USBPULLUP_CONNECT_Msk; + } +} + + +/* + * USB Device Reset Function + * Called automatically on USB Device Reset + * Return Value: None + */ + +void USBD_Reset (void) { + + /* Disable interrupts */ + NRF_USBD->INTENCLR = 0xFFFFFFFFU; + + /* Clear variables */ + setup_packet_available = 0U; + ep0_dir = 1U; + memset(ep_config, 0, sizeof(ep_config)); + + /* Endpoint 0 is ready for SETUP packet reception when USB is ENABLED, + set maximum packet size to 8 bytes */ + ep_config[0][0].max_packet_size = USBD_MAX_PACKET0; + ep_config[1][0].max_packet_size = USBD_MAX_PACKET0; + + /* Enable relevant interrupts (USB Reset and Control Endpoint 0) */ + NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk | + USBD_INTEN_EPDATA_Msk | + USBD_INTEN_EP0SETUP_Msk | + USBD_INTEN_EP0DATADONE_Msk ; +} + + +/* + * USB Device Suspend Function + * Called automatically on USB Device Suspend + * Return Value: None + */ + +void USBD_Suspend (void) { + /* Performed by Hardware */ +} + + +/* + * USB Device Resume Function + * Called automatically on USB Device Resume + * Return Value: None + */ + +void USBD_Resume (void) { + /* Performed by Hardware */ +} + + +/* + * USB Device Remote Wakeup Function + * Called automatically on USB Device Remote Wakeup + * Return Value: None + */ + +void USBD_WakeUp (void) { + NRF_USBD->LOWPOWER = USBD_LOWPOWER_LOWPOWER_ForceNormal; + NRF_USBD->DPDMVALUE = USBD_DPDMVALUE_STATE_Resume; + NRF_USBD->TASKS_DPDMDRIVE = USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Trigger; +} + + +/* + * USB Device Remote Wakeup Configuration Function + * Parameters: cfg: Device Enable/Disable + * Return Value: None + */ + +void USBD_WakeUpCfg (uint32_t cfg) { + /* Not needed */ +} + + +/* + * USB Device Set Address Function + * Parameters: adr: USB Device Address + * Return Value: None + */ + +void USBD_SetAddress (uint32_t adr, uint32_t setup) { + /* Performed by Hardware */ +} + + +/* + * USB Device Configure Function + * Parameters: cfg: Device Configure/Deconfigure + * Return Value: None + */ + +void USBD_Configure (uint32_t cfg) { + /* Not needed */ +} + + +/* + * Configure USB Device Endpoint according to Descriptor + * Parameters: pEPD: Pointer to Device Endpoint Descriptor + * Return Value: None + */ + +void USBD_ConfigEP (USB_ENDPOINT_DESCRIPTOR *pEPD) { + uint8_t ep_dir, ep_num, ep_type; + uint16_t ep_max_len; + + ep_dir = (pEPD->bEndpointAddress & USB_ENDPOINT_DIRECTION_MASK) >> 7; + ep_num = pEPD->bEndpointAddress & ~USB_ENDPOINT_DIRECTION_MASK; + ep_type = pEPD->bmAttributes & USB_ENDPOINT_TYPE_MASK; + ep_max_len = pEPD->wMaxPacketSize; + + if (ep_num >= USBD_EP_NUM_MAX) { /* If ep_num is not available */ + return; + } + if (ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + /* Isochronous Endpoint is not supported */ + return; + } + + if (ep_max_len > 64U) { + ep_max_len = 64U; /* Maximum packet size is 64 */ + } + + /* Store maximum packet size information into ep_config */ + ep_config[ep_dir][ep_num].max_packet_size = ep_max_len; +} + + +/* + * Set Direction for USB Device Control Endpoint + * Parameters: dir: Out (dir == 0), In (dir <> 0) + * Return Value: None + */ + +void USBD_DirCtrlEP (uint32_t dir) { + if (dir == 0U) { + ep0_dir = 0U; + NRF_USBD->TASKS_EP0RCVOUT = USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Msk; + } +} + + +/* + * Enable USB Device Endpoint + * Parameters: EPNum: Device Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USBD_EnableEP (uint32_t EPNum) { + uint8_t ep_dir, ep_num; + + ep_dir = (EPNum & USB_ENDPOINT_DIRECTION_MASK) >> 7; + ep_num = EPNum & ~USB_ENDPOINT_DIRECTION_MASK; + + if (ep_num >= USBD_EP_NUM_MAX) { /* If ep_num is not available */ + return; + } + + if (ep_dir != 0U) { /* If IN endpoint */ + /* Enable Endpoint */ + NRF_USBD->EPINEN |= USBD_EPINEN_IN0_Msk << ep_num; + } else { /* If OUT endpoint */ + /* Enable Endpoint */ + NRF_USBD->EPOUTEN |= USBD_EPOUTEN_OUT0_Msk << ep_num; + } +} + + +/* + * Disable USB Device Endpoint + * Parameters: EPNum: Device Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USBD_DisableEP (uint32_t EPNum) { + uint8_t ep_dir, ep_num; + + ep_dir = (EPNum & USB_ENDPOINT_DIRECTION_MASK) >> 7; + ep_num = EPNum & ~USB_ENDPOINT_DIRECTION_MASK; + + if (ep_num >= USBD_EP_NUM_MAX) { /* If ep_num is not available */ + return; + } + + if (ep_dir != 0U) { /* If IN endpoint */ + /* Disable Endpoint interrupt */ + NRF_USBD->INTENCLR = USBD_INTEN_ENDEPIN0_Msk << ep_num; + + /* Disable Endpoint */ + NRF_USBD->EPINEN &= ~(USBD_EPINEN_IN0_Msk << ep_num); + } else { /* If OUT endpoint */ + /* Disable Endpoint interrupt */ + NRF_USBD->INTENCLR = USBD_INTEN_ENDEPIN0_Msk << ep_num; + + /* Disable Endpoint */ + NRF_USBD->EPINEN &= ~(USBD_EPOUTEN_OUT0_Msk << ep_num); + } +} + + +/* + * Reset USB Device Endpoint + * Parameters: EPNum: Device Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USBD_ResetEP (uint32_t EPNum) { + uint8_t ep_dir, ep_num; + + ep_dir = (EPNum & USB_ENDPOINT_DIRECTION_MASK) >> 7; + ep_num = EPNum & ~USB_ENDPOINT_DIRECTION_MASK; + + if (ep_num >= USBD_EP_NUM_MAX) { /* If ep_num is not available */ + return; + } + + /* Reset data toggle to DATA0 */ + if (ep_num != 0U) { + if (ep_dir != 0U) { /* If IN endpoint */ + NRF_USBD->DTOGGLE = ((USBD_DTOGGLE_VALUE_Nop << USBD_DTOGGLE_VALUE_Pos) & USBD_DTOGGLE_VALUE_Msk) | ep_num | USBD_DTOGGLE_IO_Msk; + NRF_USBD->DTOGGLE = ((USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) & USBD_DTOGGLE_VALUE_Msk) | ep_num | USBD_DTOGGLE_IO_Msk; + } else { /* If OUT endpoint */ + NRF_USBD->DTOGGLE = ((USBD_DTOGGLE_VALUE_Nop << USBD_DTOGGLE_VALUE_Pos) & USBD_DTOGGLE_VALUE_Msk) | ep_num; + NRF_USBD->DTOGGLE = ((USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) & USBD_DTOGGLE_VALUE_Msk) | ep_num; + } + } + + if (ep_dir ==0U) { + /* Start OUT transfer (Receive data to USB controller's internal buffer) */ + NRF_USBD->SIZE.EPOUT[ep_num] = 0U; + } +} + + +/* + * Set Stall for USB Device Endpoint + * Parameters: EPNum: Device Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USBD_SetStallEP (uint32_t EPNum) { + uint8_t ep_dir, ep_num; + + ep_dir = (EPNum & USB_ENDPOINT_DIRECTION_MASK) >> 7; + ep_num = EPNum & ~USB_ENDPOINT_DIRECTION_MASK; + + if (ep_num >= USBD_EP_NUM_MAX) { /* If ep_num is not available */ + return; + } + + if (ep_num == 0U) { /* If Control Endpoint 0 */ + NRF_USBD->TASKS_EP0STALL = USBD_TASKS_EP0STALL_TASKS_EP0STALL_Trigger; + } else { /* If any other Endpoint */ + /* Set stall */ + if (ep_dir != 0U) { /* If IN endpoint */ + NRF_USBD->EPSTALL = USBD_EPSTALL_STALL_Msk | ep_num | USBD_EPSTALL_IO_Msk; + } else { /* If OUT endpoint */ + NRF_USBD->EPSTALL = USBD_EPSTALL_STALL_Msk | ep_num; + } + } +} + + +/* + * Clear Stall for USB Device Endpoint + * Parameters: EPNum: Device Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USBD_ClrStallEP (uint32_t EPNum) { + uint8_t ep_dir, ep_num; + + ep_dir = (EPNum & USB_ENDPOINT_DIRECTION_MASK) >> 7; + ep_num = EPNum & ~USB_ENDPOINT_DIRECTION_MASK; + + if (ep_num >= USBD_EP_NUM_MAX) { /* If ep_num is not available */ + return; + } + + /* Clear stall */ + if (ep_dir != 0U) { /* If IN endpoint */ + NRF_USBD->EPSTALL = ep_num | USBD_EPSTALL_IO_Msk; + } else { /* If OUT endpoint */ + NRF_USBD->EPSTALL = ep_num; + } + USBD_ResetEP(EPNum); +} + + +/* + * Clear USB Device Endpoint Buffer + * Parameters: EPNum: Device Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * Return Value: None + */ + +void USBD_ClearEPBuf (uint32_t EPNum) { + /* Not needed */ +} + + +/* + * Read USB Device Endpoint Data + * Parameters: EPNum: Device Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * pData: Pointer to Data Buffer + * Return Value: Number of bytes read + */ + +#ifdef __DAPLINK +uint32_t USBD_ReadEP (uint32_t EPNum, uint8_t *pData, U32 size) { +#else +uint32_t USBD_ReadEP (uint32_t EPNum, uint8_t *pData) { +#endif + uint8_t ep_dir, ep_num; + uint16_t len; + + ep_dir = (EPNum & USB_ENDPOINT_DIRECTION_MASK) >> 7; + ep_num = EPNum & ~USB_ENDPOINT_DIRECTION_MASK; + + if (ep_num >= USBD_EP_NUM_MAX) { /* If ep_num is not available */ + return 0U; + } + if (ep_dir != 0U) { /* If not OUT Endpoint */ + return 0U; + } + + if ((ep_num == 0U) && (setup_packet_available != 0U)) { + setup_packet_available = 0U; + + /* If reading Endpoint 0 and Setup Packet is available */ + pData[0] = NRF_USBD->BMREQUESTTYPE; + pData[1] = NRF_USBD->BREQUEST; + pData[2] = NRF_USBD->WVALUEL; + pData[3] = NRF_USBD->WVALUEH; + pData[4] = NRF_USBD->WINDEXL; + pData[5] = NRF_USBD->WINDEXH; + pData[6] = NRF_USBD->WLENGTHL; + pData[7] = NRF_USBD->WLENGTHH; + len = 8U; + } else { + len = NRF_USBD->SIZE.EPOUT[ep_num]; + +#ifdef __DAPLINK + if (len > size) { + len = size; + } +#endif + + /* Read received data from USB controller's internal buffer to ep_buf. + ep_buf is used to satisfy required 32-bit alignment, and size multiple of 4. */ + usbd_dma(EPNum, &ep_buf[ep_dir][ep_num][0], ((len+3U)/4U)*4U); + + /* Copy data received to requested pData */ + memcpy((void *)pData, (const void *)&ep_buf[ep_dir][ep_num][0], len); + } + + /* Start OUT transfer (Receive data to USB controller's internal buffer) */ + NRF_USBD->SIZE.EPOUT[ep_num] = 0U; + + return len; +} + + +/* + * Write USB Device Endpoint Data + * Parameters: EPNum: Endpoint Number + * EPNum.0..3: Address + * EPNum.7: Dir + * pData: Pointer to Data Buffer + * cnt: Number of bytes to write + * Return Value: Number of bytes written + */ + +uint32_t USBD_WriteEP (uint32_t EPNum, uint8_t *pData, uint32_t cnt) { + uint8_t ep_dir, ep_num; + uint16_t len, ep_max_len; + + ep_dir = (EPNum & USB_ENDPOINT_DIRECTION_MASK) >> 7; + ep_num = EPNum & ~USB_ENDPOINT_DIRECTION_MASK; + len = cnt; + + if (ep_num >= USBD_EP_NUM_MAX) { /* If ep_num is not available */ + return 0U; + } + if (ep_dir == 0U) { /* If not IN Endpoint */ + return 0U; + } + + ep_max_len = ep_config[ep_dir][ep_num].max_packet_size; + + if (len > ep_max_len) { + len = ep_max_len; + } + + /* Copy data to be sent to ep_buf */ + memcpy((void *)&ep_buf[ep_dir][ep_num][0], (const void *)pData, len); + + /* Do DMA transfer of data from ep_buf to USB controller's internal buffer */ + usbd_dma(EPNum, &ep_buf[ep_dir][ep_num][0], len); + + /* After data is sent EP0DATADONE/EPDATA event will happen and be processed by IRQ */ + + return len; +} + + +/* + * Get USB Device Last Frame Number + * Parameters: None + * Return Value: Frame Number + */ + +uint32_t USBD_GetFrame (void) { + return NRF_USBD->FRAMECNTR; +} + + +/* + * Get USB Device Last Error Code + * Parameters: None + * Return Value: Error Code + */ + +uint32_t USBD_GetError (void) { + return 0U; +} + + +/* + * USB Device Interrupt Service Routine + */ +#ifdef __DAPLINK +void USBD_IRQHandler (void) { + NVIC_DisableIRQ(USBD_IRQn); + USBD_SignalHandler(); +} + +void USB_Handler (void) { +#else +void USBD_IRQHandler (void) { +#endif + uint32_t eventcause, epdatastatus, ep_num; + + /* Check USB Reset event */ + if (NRF_USBD->EVENTS_USBRESET != 0U) { + NRF_USBD->EVENTS_USBRESET = 0U; + USBD_Reset(); + usbd_reset_core(); +#ifdef __RTX + if (USBD_RTX_DevTask) { + isr_evt_set(USBD_EVT_RESET, USBD_RTX_DevTask); + } +#else + if (USBD_P_Reset_Event) { + USBD_P_Reset_Event(); + } +#endif + } + + /* Check USB Suspend/Resume events */ + if (NRF_USBD->EVENTS_USBEVENT != 0U) { + eventcause = NRF_USBD->EVENTCAUSE; + NRF_USBD->EVENTCAUSE = 0U; + NRF_USBD->EVENTS_USBEVENT = 0U; + if ((eventcause & USBD_EVENTCAUSE_SUSPEND_Msk) != 0U) { + USBD_Suspend(); +#ifdef __RTX + if (USBD_RTX_DevTask) { + isr_evt_set(USBD_EVT_SUSPEND, USBD_RTX_DevTask); + } +#else + if (USBD_P_Suspend_Event) { + USBD_P_Suspend_Event(); + } +#endif + } + if ((eventcause & USBD_EVENTCAUSE_RESUME_Msk) != 0U) { + USBD_Resume(); +#ifdef __RTX + if (USBD_RTX_DevTask) { + isr_evt_set(USBD_EVT_RESUME, USBD_RTX_DevTask); + } +#else + if (USBD_P_Resume_Event) { + USBD_P_Resume_Event(); + } +#endif + } + } + + /* Check USB SOF event */ + if (NRF_USBD->EVENTS_SOF != 0U) { + NRF_USBD->EVENTS_SOF = 0U; +#ifdef __RTX + if (USBD_RTX_DevTask) { + isr_evt_set(USBD_EVT_SOF, USBD_RTX_DevTask); + } +#else + if (USBD_P_SOF_Event) { + USBD_P_SOF_Event(); + } +#endif + } + + /* Check Endpoint 0 Setup Packet received event */ + if (NRF_USBD->EVENTS_EP0SETUP != 0U) { + setup_packet_available = 1U; + NRF_USBD->EVENTS_EP0SETUP = 0U; +#ifdef __RTX + if (USBD_RTX_EPTask[0]) { + isr_evt_set(USBD_EVT_SETUP, USBD_RTX_EPTask[0]); + } +#else + if (USBD_P_EP[0]) { + USBD_P_EP[0](USBD_EVT_SETUP); + } +#endif + } + + /* Check Endpoint 0 Data Packet sent/received event */ + if (NRF_USBD->EVENTS_EP0DATADONE != 0U) { + NRF_USBD->EVENTS_EP0DATADONE = 0U; +#ifdef __RTX + if (USBD_RTX_EPTask[0]) { + if (ep0_dir != 0U) { + isr_evt_set(USBD_EVT_IN, USBD_RTX_EPTask[0]); + } else { + isr_evt_set(USBD_EVT_OUT, USBD_RTX_EPTask[0]); + } + } +#else + if (USBD_P_EP[0]) { + if (ep0_dir != 0U) { + USBD_P_EP[0](USBD_EVT_IN); + } else { + USBD_P_EP[0](USBD_EVT_OUT); + } + } +#endif + /* Enable Status stage */ + NRF_USBD->TASKS_EP0STATUS = USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Msk; + } + + /* Check Endpoint sent/received event */ + if (NRF_USBD->EVENTS_EPDATA != 0U) { + epdatastatus = NRF_USBD->EPDATASTATUS; + NRF_USBD->EVENTS_EPDATA = 0U; + NRF_USBD->EPDATASTATUS = epdatastatus; + for (ep_num = 1U; ep_num < USBD_EP_NUM_MAX; ep_num++) { + if ((epdatastatus & (1U << ep_num)) != 0U) { +#ifdef __RTX + if (USBD_RTX_EPTask[ep_num]) { + isr_evt_set(USBD_EVT_IN, USBD_RTX_EPTask[ep_num]); + } +#else + if (USBD_P_EP[ep_num]) { + USBD_P_EP[ep_num](USBD_EVT_IN); + } +#endif + } + } + + for (ep_num = 1U; ep_num < USBD_EP_NUM_MAX; ep_num++) { + if ((epdatastatus & ((1U << 16) << ep_num)) != 0U) { +#ifdef __RTX + if (USBD_RTX_EPTask[ep_num]) { + isr_evt_set(USBD_EVT_OUT, USBD_RTX_EPTask[ep_num]); + } +#else + if (USBD_P_EP[ep_num]) { + USBD_P_EP[ep_num](USBD_EVT_OUT); + } +#endif + } + } + } + +#ifdef __DAPLINK + NVIC_EnableIRQ(USBD_IRQn); +#endif +} diff --git a/source/hic_hal/nordic/nrf52820/usbd_nrf52820.c b/source/hic_hal/nordic/nrf52820/usbd_nrf52820.c deleted file mode 100644 index 5fa4c65fb..000000000 --- a/source/hic_hal/nordic/nrf52820/usbd_nrf52820.c +++ /dev/null @@ -1,343 +0,0 @@ -/* - * Copyright (c) 2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include "IO_Config.h" -#include "cortex_m.h" -#include "string.h" -#include "device.h" - -#define __NO_USB_LIB_C -#include "usb_config.c" - -/* - * Reset Endpoint - * Parameters: EPNum: Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * Return Value: None - */ - -void EP_Reset(U32 EPNum) -{ -} - - -/* - * Set Endpoint Status - * Parameters: EPNum: Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * stat: New Status - * Return Value: None - */ - -void EP_Status(U32 EPNum, U32 stat) -{ -} - - -/* - * USB Device Interrupt enable - * Called by USBD_Init to enable the USB Interrupt - * Return Value: None - */ - -#ifdef __RTX -void __svc(1) USBD_IntrEna(void); -void __SVC_1(void) -{ -#else -void USBD_IntrEna(void) -{ -#endif -} - - -/* - * USB Device Initialize Function - * Called by the User to initialize USB - * Return Value: None - */ - -void USBD_Init(void) -{ -} - - -/* - * USB Device Connect Function - * Called by the User to Connect/Disconnect USB Device - * Parameters: con: Connect/Disconnect - * Return Value: None - */ - -void USBD_Connect(BOOL con) -{ -} - - -/* - * USB Device Reset Function - * Called automatically on USB Device Reset - * Return Value: None - */ - -void USBD_Reset(void) -{ -} - - -/* - * USB Device Suspend Function - * Called automatically on USB Device Suspend - * Return Value: None - */ - -void USBD_Suspend(void) -{ -} - - -/* - * USB Device Resume Function - * Called automatically on USB Device Resume - * Return Value: None - */ - -void USBD_Resume(void) -{ - /* Performed by Hardware */ -} - - -/* - * USB Device Remote Wakeup Function - * Called automatically on USB Device Remote Wakeup - * Return Value: None - */ - -void USBD_WakeUp(void) -{ -} - - -/* - * USB Device Remote Wakeup Configuration Function - * Parameters: cfg: Device Enable/Disable - * Return Value: None - */ - -void USBD_WakeUpCfg(BOOL cfg) -{ - /* Not needed */ -} - - -/* - * USB Device Set Address Function - * Parameters: adr: USB Device Address - * setup: Called in setup stage (!=0), else after status stage - * Return Value: None - */ - -void USBD_SetAddress(U32 adr, U32 setup) -{ -} - - -/* - * USB Device Configure Function - * Parameters: cfg: Device Configure/Deconfigure - * Return Value: None - */ - -void USBD_Configure(BOOL cfg) -{ -} - - -/* - * Configure USB Device Endpoint according to Descriptor - * Parameters: pEPD: Pointer to Device Endpoint Descriptor - * Return Value: None - */ - -void USBD_ConfigEP(USB_ENDPOINT_DESCRIPTOR *pEPD) -{ -} - - -/* - * Set Direction for USB Device Control Endpoint - * Parameters: dir: Out (dir == 0), In (dir <> 0) - * Return Value: None - */ - -void USBD_DirCtrlEP(U32 dir) -{ - /* Not needed */ -} - - -/* - * Enable USB Device Endpoint - * Parameters: EPNum: Device Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * Return Value: None - */ - -void USBD_EnableEP(U32 EPNum) -{ -} - - -/* - * Disable USB Endpoint - * Parameters: EPNum: Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * Return Value: None - */ - -void USBD_DisableEP(U32 EPNum) -{ -} - - -/* - * Reset USB Device Endpoint - * Parameters: EPNum: Device Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * Return Value: None - */ - -void USBD_ResetEP(U32 EPNum) -{ -} - - -/* - * Set Stall for USB Device Endpoint - * Parameters: EPNum: Device Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * Return Value: None - */ - -void USBD_SetStallEP(U32 EPNum) -{ -} - - -/* - * Clear Stall for USB Device Endpoint - * Parameters: EPNum: Device Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * Return Value: None - */ - -void USBD_ClrStallEP(U32 EPNum) -{ -} - - -/* - * Clear USB Device Endpoint Buffer - * Parameters: EPNum: Device Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * Return Value: None - */ - -void USBD_ClearEPBuf(U32 EPNum) -{ - ; -} - - -/* - * Read USB Device Endpoint Data - * Parameters: EPNum: Device Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * pData: Pointer to Data Buffer - * Return Value: Number of bytes read - */ - -U32 USBD_ReadEP(U32 EPNum, U8 *pData, U32 bufsz) -{ -} - - -/* - * Write USB Device Endpoint Data - * Parameters: EPNum: Device Endpoint Number - * EPNum.0..3: Address - * EPNum.7: Dir - * pData: Pointer to Data Buffer - * cnt: Number of bytes to write - * Return Value: Number of bytes written - */ - -U32 USBD_WriteEP(U32 EPNum, U8 *pData, U32 cnt) -{ -} - - -/* - * Get USB Device Last Frame Number - * Parameters: None - * Return Value: Frame Number - */ - -U32 USBD_GetFrame(void) -{ -} - - -#ifdef __RTX -U32 LastError; /* Last Error */ - -/* - * Get USB Last Error Code - * Parameters: None - * Return Value: Error Code - */ - -U32 USBD_GetError(void) -{ - return (LastError); -} -#endif - - -/* - * USB Device Interrupt Service Routine - */ - -void USB_LP_CAN1_RX0_IRQHandler(void) -{ -} - -void USBD_Handler(void) -{ -} From 2a03fa41a9384b59c4343b1035d5c05e2c5fd6f4 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 14 Jul 2021 07:19:30 -0500 Subject: [PATCH 406/617] nrf52820_hic: compilation fixes --- records/hic_hal/nrf52820.yaml | 2 +- source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c | 15 +++++++++++++-- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/records/hic_hal/nrf52820.yaml b/records/hic_hal/nrf52820.yaml index 1b0bfb695..911424bfd 100644 --- a/records/hic_hal/nrf52820.yaml +++ b/records/hic_hal/nrf52820.yaml @@ -8,7 +8,7 @@ common: - NRF52820_XXAA - DAPLINK_HIC_ID=0x6E052820 # DAPLINK_HIC_ID_NRF52820 - OS_CLOCK=64000000 - - DAPLINK_IF + - __DAPLINK includes: - source/hic_hal/nordic/nrf52820 - source/hic_hal/nordic/nrf52820/cmsis diff --git a/source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c b/source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c index 91fd9fe47..0dba8c3d6 100644 --- a/source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c +++ b/source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c @@ -215,7 +215,11 @@ void USBD_Init (void) { * Return Value: None */ +#ifdef __DAPLINK +void USBD_Connect (BOOL con) { +#else void USBD_Connect (uint32_t con) { +#endif if (con != 0U) { /* Connect */ NRF_USBD->USBPULLUP |= USBD_USBPULLUP_CONNECT_Msk; } else { /* Disconnect */ @@ -294,7 +298,11 @@ void USBD_WakeUp (void) { * Return Value: None */ +#ifdef __DAPLINK +void USBD_WakeUpCfg (BOOL cfg) { +#else void USBD_WakeUpCfg (uint32_t cfg) { +#endif /* Not needed */ } @@ -315,8 +323,11 @@ void USBD_SetAddress (uint32_t adr, uint32_t setup) { * Parameters: cfg: Device Configure/Deconfigure * Return Value: None */ - +#ifdef __DAPLINK +void USBD_Configure (BOOL cfg) { +#else void USBD_Configure (uint32_t cfg) { +#endif /* Not needed */ } @@ -675,7 +686,7 @@ void USBD_IRQHandler (void) { USBD_SignalHandler(); } -void USB_Handler (void) { +void USBD_Handler (void) { #else void USBD_IRQHandler (void) { #endif From c5572ed82b0848a4fdf4174842d02f868c80898c Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 14 Jul 2021 15:55:40 +0200 Subject: [PATCH 407/617] nrf52820_hic: copy memory for GCC --- .../nrf52820/gcc/ses_startup_nrf_common.S | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf_common.S b/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf_common.S index 2db7c9c94..1b09f39c7 100644 --- a/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf_common.S +++ b/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf_common.S @@ -168,6 +168,23 @@ afterInitialize: isb #endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 + /* Jump to program start */ b _start From a420a2bfd5f28ede217fe28b332d434b582d2048 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 14 Jul 2021 09:58:45 -0500 Subject: [PATCH 408/617] nrf52820_hic: fix armcc startup --- .../nordic/nrf52820/armcc/arm_startup_nrf52820.s | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/source/hic_hal/nordic/nrf52820/armcc/arm_startup_nrf52820.s b/source/hic_hal/nordic/nrf52820/armcc/arm_startup_nrf52820.s index 02d9a3b39..d4b71f88a 100644 --- a/source/hic_hal/nordic/nrf52820/armcc/arm_startup_nrf52820.s +++ b/source/hic_hal/nordic/nrf52820/armcc/arm_startup_nrf52820.s @@ -65,7 +65,7 @@ __heap_limit EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size - + IMPORT g_board_info __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler DCD NMI_Handler @@ -74,12 +74,12 @@ __Vectors DCD __initial_sp ; Top of Stack DCD BusFault_Handler DCD UsageFault_Handler DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved + DCD DAPLINK_BUILD_KEY ; Build type - BL/IF + DCD DAPLINK_HIC_ID ; Compatibility + DCD DAPLINK_VERSION ; Version DCD SVC_Handler DCD DebugMon_Handler - DCD 0 ; Reserved + DCD g_board_info ; Ptr to Board info, family info other target details DCD PendSV_Handler DCD SysTick_Handler From 6e07315f90a8d3e7e1f044e17090dd67eea8c939 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 15 Jul 2021 08:20:49 +0200 Subject: [PATCH 409/617] nrf52820_hic: fix gcc startup --- .../nrf52820/gcc/gcc_startup_nrf52820.S | 350 +++++++++++++++++ .../nrf52820/gcc/ses_startup_nrf52820.S | 357 ------------------ .../nrf52820/gcc/ses_startup_nrf_common.S | 210 ----------- 3 files changed, 350 insertions(+), 567 deletions(-) create mode 100644 source/hic_hal/nordic/nrf52820/gcc/gcc_startup_nrf52820.S delete mode 100644 source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf52820.S delete mode 100644 source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf_common.S diff --git a/source/hic_hal/nordic/nrf52820/gcc/gcc_startup_nrf52820.S b/source/hic_hal/nordic/nrf52820/gcc/gcc_startup_nrf52820.S new file mode 100644 index 000000000..3b406ce86 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/gcc/gcc_startup_nrf52820.S @@ -0,0 +1,350 @@ +/* + +Copyright (c) 2009-2021 Arm Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + https://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. +NOTICE: This file has been modified for DAPLink + +*/ + + .syntax unified + .arch armv7e-m + + .section .isr_vector, "ax" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 /*Reserved */ + .long DAPLINK_BUILD_KEY /* Build type - BL/IF */ + .long DAPLINK_HIC_ID /* Compatibility */ + .long DAPLINK_VERSION /* Version */ + .long SVC_Handler + .long DebugMon_Handler + .long g_board_info /* Ptr to Board info, family info other target details */ + .long PendSV_Handler + .long SysTick_Handler + + /* External Interrupts */ + .long POWER_CLOCK_IRQHandler + .long RADIO_IRQHandler + .long UARTE0_UART0_IRQHandler + .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler + .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler + .long 0 /*Reserved */ + .long GPIOTE_IRQHandler + .long 0 /*Reserved */ + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long RTC0_IRQHandler + .long TEMP_IRQHandler + .long RNG_IRQHandler + .long ECB_IRQHandler + .long CCM_AAR_IRQHandler + .long WDT_IRQHandler + .long RTC1_IRQHandler + .long QDEC_IRQHandler + .long COMP_IRQHandler + .long SWI0_EGU0_IRQHandler + .long SWI1_EGU1_IRQHandler + .long SWI2_EGU2_IRQHandler + .long SWI3_EGU3_IRQHandler + .long SWI4_EGU4_IRQHandler + .long SWI5_EGU5_IRQHandler + .long TIMER3_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long USBD_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + + .size __isr_vector, . - __isr_vector + +/* Reset Handler */ + + + .text + .thumb + .thumb_func + .align 1 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + + +/* Loop to copy data from read only memory to RAM. + * The ranges of copy from/to are specified by following symbols: + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to. + * __data_end__: VMA of end of the section to copy to. + * + * All addresses must be aligned to 4 bytes boundary. + */ +#ifndef __STARTUP_SKIP_ETEXT + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: +#endif + +/* This part of work usually is done in C library startup code. Otherwise, + * define __STARTUP_CLEAR_BSS to enable it in this startup. This section + * clears the RAM where BSS data is located. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * All addresses must be aligned to 4 bytes boundary. + */ +#ifdef __STARTUP_CLEAR_BSS + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, r2, #4 + str r0, [r1, r2] + bgt .L_loop3 + +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS */ + +/* Execute SystemInit function. */ + bl SystemInit + +/* Call _start function provided by libraries. + * If those libraries are not accessible, define __START as your entry point. + */ +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler,.-Reset_Handler + + .section ".text" + + +/* Dummy Exception Handlers (infinite loops which can be modified) */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + b . + .size NMI_Handler, . - NMI_Handler + + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + b . + .size HardFault_Handler, . - HardFault_Handler + + + .weak MemoryManagement_Handler + .type MemoryManagement_Handler, %function +MemoryManagement_Handler: + b . + .size MemoryManagement_Handler, . - MemoryManagement_Handler + + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + b . + .size BusFault_Handler, . - BusFault_Handler + + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + b . + .size UsageFault_Handler, . - UsageFault_Handler + + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + b . + .size SVC_Handler, . - SVC_Handler + + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + b . + .size DebugMon_Handler, . - DebugMon_Handler + + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + b . + .size PendSV_Handler, . - PendSV_Handler + + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + b . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ POWER_CLOCK_IRQHandler + IRQ RADIO_IRQHandler + IRQ UARTE0_UART0_IRQHandler + IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler + IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler + IRQ GPIOTE_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ RTC0_IRQHandler + IRQ TEMP_IRQHandler + IRQ RNG_IRQHandler + IRQ ECB_IRQHandler + IRQ CCM_AAR_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC1_IRQHandler + IRQ QDEC_IRQHandler + IRQ COMP_IRQHandler + IRQ SWI0_EGU0_IRQHandler + IRQ SWI1_EGU1_IRQHandler + IRQ SWI2_EGU2_IRQHandler + IRQ SWI3_EGU3_IRQHandler + IRQ SWI4_EGU4_IRQHandler + IRQ SWI5_EGU5_IRQHandler + IRQ TIMER3_IRQHandler + IRQ USBD_IRQHandler + + .end diff --git a/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf52820.S b/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf52820.S deleted file mode 100644 index e0faa3fa2..000000000 --- a/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf52820.S +++ /dev/null @@ -1,357 +0,0 @@ -/*********************************************************************************** - * SEGGER Microcontroller GmbH * - * The Embedded Experts * - *********************************************************************************** - * * - * (c) 2014 - 2018 SEGGER Microcontroller GmbH * - * * - * www.segger.com Support: support@segger.com * - * * - *********************************************************************************** - * * - * All rights reserved. * - * * - * Redistribution and use in source and binary forms, with or * - * without modification, are permitted provided that the following * - * conditions are met: * - * * - * - Redistributions of source code must retain the above copyright * - * notice, this list of conditions and the following disclaimer. * - * * - * - Neither the name of SEGGER Microcontroller GmbH * - * nor the names of its contributors may be used to endorse or * - * promote products derived from this software without specific * - * prior written permission. * - * * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * - * DISCLAIMED. * - * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * - * DAMAGE. * - * * - ***********************************************************************************/ - -/************************************************************************************ - * Preprocessor Definitions * - * ------------------------ * - * VECTORS_IN_RAM * - * * - * If defined, an area of RAM will large enough to store the vector table * - * will be reserved. * - * * - ************************************************************************************/ - - .syntax unified - .code 16 - - .section .init, "ax" - .align 0 - -/************************************************************************************ - * Default Exception Handlers * - ************************************************************************************/ - - - .thumb_func - .weak NMI_Handler -NMI_Handler: - b . - - .thumb_func - .weak HardFault_Handler -HardFault_Handler: - b . - - .thumb_func - .weak MemoryManagement_Handler -MemoryManagement_Handler: - b . - - .thumb_func - .weak BusFault_Handler -BusFault_Handler: - b . - - .thumb_func - .weak UsageFault_Handler -UsageFault_Handler: - b . - - .thumb_func - .weak SVC_Handler -SVC_Handler: - b . - - .thumb_func - .weak DebugMon_Handler -DebugMon_Handler: - b . - - .thumb_func - .weak PendSV_Handler -PendSV_Handler: - b . - - .thumb_func - .weak SysTick_Handler -SysTick_Handler: - b . - - .thumb_func - .weak Dummy_Handler -Dummy_Handler: - b . - -/************************************************************************************ - * Default Interrupt Handlers * - ************************************************************************************/ - -.weak POWER_CLOCK_IRQHandler -.thumb_set POWER_CLOCK_IRQHandler, Dummy_Handler - -.weak RADIO_IRQHandler -.thumb_set RADIO_IRQHandler, Dummy_Handler - -.weak UARTE0_UART0_IRQHandler -.thumb_set UARTE0_UART0_IRQHandler, Dummy_Handler - -.weak SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler -.thumb_set SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler, Dummy_Handler - -.weak SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler -.thumb_set SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler, Dummy_Handler - -.weak GPIOTE_IRQHandler -.thumb_set GPIOTE_IRQHandler, Dummy_Handler - -.weak TIMER0_IRQHandler -.thumb_set TIMER0_IRQHandler, Dummy_Handler - -.weak TIMER1_IRQHandler -.thumb_set TIMER1_IRQHandler, Dummy_Handler - -.weak TIMER2_IRQHandler -.thumb_set TIMER2_IRQHandler, Dummy_Handler - -.weak RTC0_IRQHandler -.thumb_set RTC0_IRQHandler, Dummy_Handler - -.weak TEMP_IRQHandler -.thumb_set TEMP_IRQHandler, Dummy_Handler - -.weak RNG_IRQHandler -.thumb_set RNG_IRQHandler, Dummy_Handler - -.weak ECB_IRQHandler -.thumb_set ECB_IRQHandler, Dummy_Handler - -.weak CCM_AAR_IRQHandler -.thumb_set CCM_AAR_IRQHandler, Dummy_Handler - -.weak WDT_IRQHandler -.thumb_set WDT_IRQHandler, Dummy_Handler - -.weak RTC1_IRQHandler -.thumb_set RTC1_IRQHandler, Dummy_Handler - -.weak QDEC_IRQHandler -.thumb_set QDEC_IRQHandler, Dummy_Handler - -.weak COMP_IRQHandler -.thumb_set COMP_IRQHandler, Dummy_Handler - -.weak SWI0_EGU0_IRQHandler -.thumb_set SWI0_EGU0_IRQHandler, Dummy_Handler - -.weak SWI1_EGU1_IRQHandler -.thumb_set SWI1_EGU1_IRQHandler, Dummy_Handler - -.weak SWI2_EGU2_IRQHandler -.thumb_set SWI2_EGU2_IRQHandler, Dummy_Handler - -.weak SWI3_EGU3_IRQHandler -.thumb_set SWI3_EGU3_IRQHandler, Dummy_Handler - -.weak SWI4_EGU4_IRQHandler -.thumb_set SWI4_EGU4_IRQHandler, Dummy_Handler - -.weak SWI5_EGU5_IRQHandler -.thumb_set SWI5_EGU5_IRQHandler, Dummy_Handler - -.weak TIMER3_IRQHandler -.thumb_set TIMER3_IRQHandler, Dummy_Handler - -.weak USBD_IRQHandler -.thumb_set USBD_IRQHandler, Dummy_Handler - -/************************************************************************************ - * Reset Handler Extensions * - ************************************************************************************/ - - .extern Reset_Handler - .global nRFInitialize - .extern afterInitialize - - .thumb_func -nRFInitialize: - b afterInitialize - - -/************************************************************************************ - * Vector Table * - ************************************************************************************/ - - .section .isr_vector, "ax" - .align 0 - .global __isr_vector - -__isr_vector: - .word __StackTop - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemoryManagement_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 /*Reserved */ - .word DAPLINK_BUILD_KEY /* Build type - BL/IF*/ - .word DAPLINK_HIC_ID /* Compatibility*/ - .word DAPLINK_VERSION /* Version*/ - .word SVC_Handler - .word DebugMon_Handler - .word g_board_info /* Ptr to Board info, family info other target details*/ - .word PendSV_Handler - .word SysTick_Handler - -/* External Interrupts */ - .word POWER_CLOCK_IRQHandler - .word RADIO_IRQHandler - .word UARTE0_UART0_IRQHandler - .word SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - .word SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - .word 0 /*Reserved */ - .word GPIOTE_IRQHandler - .word 0 /*Reserved */ - .word TIMER0_IRQHandler - .word TIMER1_IRQHandler - .word TIMER2_IRQHandler - .word RTC0_IRQHandler - .word TEMP_IRQHandler - .word RNG_IRQHandler - .word ECB_IRQHandler - .word CCM_AAR_IRQHandler - .word WDT_IRQHandler - .word RTC1_IRQHandler - .word QDEC_IRQHandler - .word COMP_IRQHandler - .word SWI0_EGU0_IRQHandler - .word SWI1_EGU1_IRQHandler - .word SWI2_EGU2_IRQHandler - .word SWI3_EGU3_IRQHandler - .word SWI4_EGU4_IRQHandler - .word SWI5_EGU5_IRQHandler - .word TIMER3_IRQHandler - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word USBD_IRQHandler - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ - .word 0 /*Reserved */ -_vectors_end: - -#ifdef VECTORS_IN_RAM - .section .vectors_ram, "ax" - .align 0 - .global _vectors_ram - -_vectors_ram: - .space _vectors_end - _vectors, 0 -#endif diff --git a/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf_common.S b/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf_common.S deleted file mode 100644 index 1b09f39c7..000000000 --- a/source/hic_hal/nordic/nrf52820/gcc/ses_startup_nrf_common.S +++ /dev/null @@ -1,210 +0,0 @@ -/*********************************************************************************** - * SEGGER Microcontroller GmbH * - * The Embedded Experts * - *********************************************************************************** - * * - * (c) 2014 - 2018 SEGGER Microcontroller GmbH * - * * - * www.segger.com Support: support@segger.com * - * * - *********************************************************************************** - * * - * All rights reserved. * - * * - * Redistribution and use in source and binary forms, with or * - * without modification, are permitted provided that the following * - * conditions are met: * - * * - * - Redistributions of source code must retain the above copyright * - * notice, this list of conditions and the following disclaimer. * - * * - * - Neither the name of SEGGER Microcontroller GmbH * - * nor the names of its contributors may be used to endorse or * - * promote products derived from this software without specific * - * prior written permission. * - * * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * - * DISCLAIMED. * - * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * - * DAMAGE. * - * * - *********************************************************************************** - * * - * This file has been modified by Nordic Semiconductor: * - * To separate out device-specific data * - * * - ***********************************************************************************/ - -/************************************************************************************ - * Preprocessor Definitions * - * ------------------------ * - * NO_FPU_ENABLE * - * * - * If defined, FPU will not be enabled. * - * * - * NO_STACK_INIT * - * * - * If defined, the stack pointer will not be initialised. * - * * - * NO_SYSTEM_INIT * - * * - * If defined, the SystemInit() function will not be called. By default * - * SystemInit() is called after reset to enable the clocks and memories to * - * be initialised prior to any C startup initialisation. * - * * - * NO_VTOR_CONFIG * - * * - * If defined, the vector table offset register will not be configured. * - * * - * MEMORY_INIT * - * * - * If defined, the MemoryInit() function will be called. By default * - * MemoryInit() is called after SystemInit() to enable an external memory * - * controller. * - * * - * STACK_INIT_VAL * - * * - * If defined, specifies the initial stack pointer value. If undefined, * - * the stack pointer will be initialised to point to the end of the * - * RAM segment. * - * * - * VECTORS_IN_RAM * - * * - * If defined, the exception vectors will be copied from Flash to RAM. * - * * - ************************************************************************************/ - - .syntax unified - - .global Reset_Handler -#ifdef INITIALIZE_USER_SECTIONS - .global InitializeUserMemorySections -#endif - .extern __isr_vector - .extern nRFInitialize - .global afterInitialize - - .section .init, "ax" - .thumb_func - - .equ VTOR_REG, 0xE000ED08 - .equ FPU_CPACR_REG, 0xE000ED88 - -#ifndef STACK_INIT_VAL -#define STACK_INIT_VAL __StackTop -#endif - -Reset_Handler: - - /* Perform prestart tasks. */ - b nRFInitialize - -.thumb_func -afterInitialize: - -#ifndef NO_STACK_INIT - /* Initialise main stack */ - ldr r0, =STACK_INIT_VAL - ldr r1, =0x7 - bics r0, r1 - mov sp, r0 -#endif - -#ifndef NO_SYSTEM_INIT - /* Initialise system */ - ldr r0, =SystemInit - blx r0 -#endif - -#ifdef MEMORY_INIT - ldr r0, =MemoryInit - blx r0 -#endif - -#ifdef VECTORS_IN_RAM - /* Copy exception vectors into RAM */ - ldr r0, =__vectors_start__ - ldr r1, =__vectors_end__ - ldr r2, =__vectors_ram_start__ -1: - cmp r0, r1 - beq 2f - ldr r3, [r0] - str r3, [r2] - adds r0, r0, #4 - adds r2, r2, #4 - b 1b -2: -#endif - -#ifndef NO_VTOR_CONFIG - /* Configure vector table offset register */ - ldr r0, =VTOR_REG -#ifdef VECTORS_IN_RAM - ldr r1, =_vectors_ram -#else - ldr r1, =__isr_vector -#endif - str r1, [r0] -#endif - -#if (defined(__ARM_ARCH_FPV4_SP_D16__) || defined(__ARM_ARCH_FPV5_D16__)) && !defined(NO_FPU_ENABLE) - /* Enable FPU */ - ldr r0, =FPU_CPACR_REG - ldr r1, [r0] - orr r1, r1, #(0xF << 20) - str r1, [r0] - dsb - isb -#endif - -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ -.LC0: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .LC0 - - /* Jump to program start */ - b _start - -#ifdef INITIALIZE_USER_SECTIONS - .thumb_func -InitializeUserMemorySections: - ldr r0, =__start_nrf_sections - ldr r1, =__start_nrf_sections_run - ldr r2, =__end_nrf_sections_run - cmp r0, r1 - beq 2f - subs r2, r2, r1 - beq 2f -1: - ldrb r3, [r0] - adds r0, r0, #1 - strb r3, [r1] - adds r1, r1, #1 - subs r2, r2, #1 - bne 1b -2: - bx lr -#endif \ No newline at end of file From dfb59de1db4858dc8c6b91d54054ee5dade99ba5 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 15 Jul 2021 02:44:30 -0500 Subject: [PATCH 410/617] nrf52820_hic: update to nRF_DeviceFamilyPack version 8.38.0 - define DEVELOP_IN_NRF52833 - disable JTAG and SWO --- records/board/nrf52833_dk.yaml | 1 + source/hic_hal/nordic/nrf52820/DAP_config.h | 4 +- .../nrf52820/cmsis/compiler_abstraction.h | 78 +- source/hic_hal/nordic/nrf52820/cmsis/nrf.h | 110 +- .../nordic/nrf52820/cmsis/nrf51_erratas.h | 1007 ++++- .../nordic/nrf52820/cmsis/nrf51_to_nrf52.h | 41 +- source/hic_hal/nordic/nrf52820/cmsis/nrf52.h | 47 +- .../hic_hal/nordic/nrf52820/cmsis/nrf52820.h | 47 +- .../nrf52820/cmsis/nrf52820_bitfields.h | 41 +- .../nrf52820/cmsis/nrf52820_peripherals.h | 61 +- .../nrf52820/cmsis/nrf52833_to_nrf52820.h | 41 +- .../nordic/nrf52820/cmsis/nrf52_bitfields.h | 41 +- .../nordic/nrf52820/cmsis/nrf52_erratas.h | 3459 ++++++++++++++++- .../nordic/nrf52820/cmsis/nrf52_name_change.h | 41 +- .../nordic/nrf52820/cmsis/nrf52_to_nrf52810.h | 41 +- .../nordic/nrf52820/cmsis/nrf52_to_nrf52833.h | 41 +- .../nordic/nrf52820/cmsis/nrf52_to_nrf52840.h | 41 +- .../nordic/nrf52820/cmsis/nrf53_erratas.h | 2074 +++++++++- .../nordic/nrf52820/cmsis/nrf91_erratas.h | 316 +- .../nordic/nrf52820/cmsis/nrf_erratas.h | 41 +- .../nordic/nrf52820/cmsis/system_nrf52.c | 316 ++ .../nordic/nrf52820/cmsis/system_nrf52.h | 61 + .../nordic/nrf52820/cmsis/system_nrf52820.c | 119 - .../nordic/nrf52820/cmsis/system_nrf52820.h | 2 +- 24 files changed, 7321 insertions(+), 750 deletions(-) create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/system_nrf52.c create mode 100644 source/hic_hal/nordic/nrf52820/cmsis/system_nrf52.h delete mode 100644 source/hic_hal/nordic/nrf52820/cmsis/system_nrf52820.c diff --git a/records/board/nrf52833_dk.yaml b/records/board/nrf52833_dk.yaml index 9c29104e6..54fcd1bbd 100644 --- a/records/board/nrf52833_dk.yaml +++ b/records/board/nrf52833_dk.yaml @@ -1,5 +1,6 @@ common: macros: - IO_CONFIG_OVERRIDE + - DEVELOP_IN_NRF52833 includes: - source/board/override_nrf52833_dk diff --git a/source/hic_hal/nordic/nrf52820/DAP_config.h b/source/hic_hal/nordic/nrf52820/DAP_config.h index 6725c36e7..d1f53766e 100644 --- a/source/hic_hal/nordic/nrf52820/DAP_config.h +++ b/source/hic_hal/nordic/nrf52820/DAP_config.h @@ -70,7 +70,7 @@ This information includes: /// Indicate that JTAG communication mode is available at the Debug Port. /// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available. +#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available. /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port. /// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255. @@ -99,7 +99,7 @@ This information includes: /// Indicate that UART Serial Wire Output (SWO) trace is available. /// This information is returned by the command \ref DAP_Info as part of Capabilities. -#define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available. +#define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available. /// Maximum SWO UART Baudrate. #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz. diff --git a/source/hic_hal/nordic/nrf52820/cmsis/compiler_abstraction.h b/source/hic_hal/nordic/nrf52820/cmsis/compiler_abstraction.h index cf750ce55..c239fd11c 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/compiler_abstraction.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/compiler_abstraction.h @@ -1,41 +1,32 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. */ @@ -50,11 +41,6 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef NRF_STRING_CONCATENATE #define NRF_STRING_CONCATENATE(lhs, rhs) NRF_STRING_CONCATENATE_IMPL(lhs, rhs) #endif -#if __LINT__ == 1 - #ifndef NRF_STATIC_ASSERT - #define NRF_STATIC_ASSERT(cond, msg) - #endif -#endif #if defined ( __CC_ARM ) @@ -118,6 +104,11 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define GET_SP() __current_sp() #ifndef NRF_STATIC_ASSERT + #ifdef __cplusplus + #ifndef _Static_assert + #define _Static_assert static_assert + #endif + #endif #define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg) #endif @@ -135,13 +126,23 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define __WEAK __weak #endif - #ifndef __ALIGN - #define STRING_PRAGMA(x) _Pragma(#x) - #define __ALIGN(n) STRING_PRAGMA(data_alignment = n) - #endif + #if (__VER__ >= 8000000) + #ifndef __ALIGN + #define __ALIGN(n) __attribute__((aligned(x))) + #endif - #ifndef __PACKED - #define __PACKED __packed + #ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) + #endif + #else + #ifndef __ALIGN + #define STRING_PRAGMA(x) _Pragma(#x) + #define __ALIGN(n) STRING_PRAGMA(data_alignment = n) + #endif + + #ifndef __PACKED + #define __PACKED __packed + #endif #endif #ifndef __UNUSED @@ -190,6 +191,11 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. } #ifndef NRF_STATIC_ASSERT + #ifdef __cplusplus + #ifndef _Static_assert + #define _Static_assert static_assert + #endif + #endif #define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg) #endif diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf.h index 7d639fb0a..6f47bd421 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf.h @@ -1,41 +1,32 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. */ @@ -44,9 +35,41 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* MDK version */ #define MDK_MAJOR_VERSION 8 -#define MDK_MINOR_VERSION 35 +#define MDK_MINOR_VERSION 38 #define MDK_MICRO_VERSION 0 + +/* Define coprocessor domains */ +#if defined (NRF5340_XXAA_APPLICATION) || defined (NRF5340_XXAA_NETWORK) + #ifndef NRF5340_XXAA + #define NRF5340_XXAA + #endif +#endif +#if defined (NRF5340_XXAA_APPLICATION) + #ifndef NRF_APPLICATION + #define NRF_APPLICATION + #endif +#endif +#if defined (NRF5340_XXAA_NETWORK) + #ifndef NRF_NETWORK + #define NRF_NETWORK + #endif +#endif + +/* Apply compatibility macros for old nRF5340 macros */ +#if defined(NRF5340_XXAA) + #if defined (NRF_APPLICATION) + #ifndef NRF5340_XXAA_APPLICATION + #define NRF5340_XXAA_APPLICATION + #endif + #endif + #if defined (NRF_NETWORK) + #ifndef NRF5340_XXAA_NETWORK + #define NRF5340_XXAA_NETWORK + #endif + #endif +#endif + /* Define NRF51_SERIES for common use in nRF51 series devices. Only if not previously defined. */ #if defined (NRF51) ||\ defined (NRF51422_XXAA) ||\ @@ -81,7 +104,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #endif /* Define NRF53_SERIES for common use in nRF53 series devices. */ -#if defined (NRF5340_XXAA_APPLICATION) || defined (NRF5340_XXAA_NETWORK) +#if defined (NRF5340_XXAA) #ifndef NRF53_SERIES #define NRF53_SERIES #endif @@ -93,37 +116,6 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define NRF91_SERIES #endif #endif - -/* Define coprocessor domains */ -#if defined (NRF5340_XXAA_APPLICATION) || defined (NRF5340_XXAA_NETWORK) - #ifndef NRF5340_XXAA - #define NRF5340_XXAA - #endif -#endif -#if defined (NRF5340_XXAA_APPLICATION) - #ifndef NRF_APPLICATION - #define NRF_APPLICATION - #endif -#endif -#if defined (NRF5340_XXAA_NETWORK) - #ifndef NRF_NETWORK - #define NRF_NETWORK - #endif -#endif - -/* Apply compatibility macros for old nRF5340 macros */ -#if defined(NRF5340_XXAA) - #if defined (NRF_APPLICATION) - #ifndef NRF5340_XXAA_APPLICATION - #define NRF5340_XXAA_APPLICATION - #endif - #endif - #if defined (NRF_NETWORK) - #ifndef NRF5340_XXAA_NETWORK - #define NRF5340_XXAA_NETWORK - #endif - #endif -#endif /* Device selection for device includes. */ #if defined (NRF51) @@ -175,9 +167,11 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #if defined(NRF_APPLICATION) #include "nrf5340_application.h" #include "nrf5340_application_bitfields.h" + #include "nrf5340_application_name_change.h" #elif defined (NRF_NETWORK) #include "nrf5340_network.h" #include "nrf5340_network_bitfields.h" + #include "nrf5340_network_name_change.h" #endif #elif defined (NRF9160_XXAA) diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf51_erratas.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf51_erratas.h index 3882dfd0c..aad134a42 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf51_erratas.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf51_erratas.h @@ -3,42 +3,33 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. */ @@ -125,6 +116,19 @@ static bool nrf51_errata_76(void) __UNUSED; static bool nrf51_errata_77(void) __UNUSED; static bool nrf51_errata_78(void) __UNUSED; +/* ========= Errata 1 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_1_PRESENT 1 +#else + #define NRF51_ERRATA_1_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_1_ENABLE_WORKAROUND + #define NRF51_ERRATA_1_ENABLE_WORKAROUND NRF51_ERRATA_1_PRESENT +#endif + static bool nrf51_errata_1(void) { #ifndef NRF51_SERIES @@ -176,6 +180,19 @@ static bool nrf51_errata_1(void) #endif } +/* ========= Errata 2 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_2_PRESENT 1 +#else + #define NRF51_ERRATA_2_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_2_ENABLE_WORKAROUND + #define NRF51_ERRATA_2_ENABLE_WORKAROUND NRF51_ERRATA_2_PRESENT +#endif + static bool nrf51_errata_2(void) { #ifndef NRF51_SERIES @@ -227,6 +244,19 @@ static bool nrf51_errata_2(void) #endif } +/* ========= Errata 3 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_3_PRESENT 1 +#else + #define NRF51_ERRATA_3_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_3_ENABLE_WORKAROUND + #define NRF51_ERRATA_3_ENABLE_WORKAROUND NRF51_ERRATA_3_PRESENT +#endif + static bool nrf51_errata_3(void) { #ifndef NRF51_SERIES @@ -278,6 +308,13 @@ static bool nrf51_errata_3(void) #endif } +/* ========= Errata 4 ========= */ +#define NRF51_ERRATA_4_PRESENT 0 + +#ifndef NRF51_ERRATA_4_ENABLE_WORKAROUND + #define NRF51_ERRATA_4_ENABLE_WORKAROUND NRF51_ERRATA_4_PRESENT +#endif + static bool nrf51_errata_4(void) { #ifndef NRF51_SERIES @@ -287,6 +324,13 @@ static bool nrf51_errata_4(void) #endif } +/* ========= Errata 5 ========= */ +#define NRF51_ERRATA_5_PRESENT 0 + +#ifndef NRF51_ERRATA_5_ENABLE_WORKAROUND + #define NRF51_ERRATA_5_ENABLE_WORKAROUND NRF51_ERRATA_5_PRESENT +#endif + static bool nrf51_errata_5(void) { #ifndef NRF51_SERIES @@ -296,6 +340,19 @@ static bool nrf51_errata_5(void) #endif } +/* ========= Errata 6 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_6_PRESENT 1 +#else + #define NRF51_ERRATA_6_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_6_ENABLE_WORKAROUND + #define NRF51_ERRATA_6_ENABLE_WORKAROUND NRF51_ERRATA_6_PRESENT +#endif + static bool nrf51_errata_6(void) { #ifndef NRF51_SERIES @@ -347,6 +404,19 @@ static bool nrf51_errata_6(void) #endif } +/* ========= Errata 7 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_7_PRESENT 1 +#else + #define NRF51_ERRATA_7_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_7_ENABLE_WORKAROUND + #define NRF51_ERRATA_7_ENABLE_WORKAROUND NRF51_ERRATA_7_PRESENT +#endif + static bool nrf51_errata_7(void) { #ifndef NRF51_SERIES @@ -398,6 +468,19 @@ static bool nrf51_errata_7(void) #endif } +/* ========= Errata 8 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_8_PRESENT 1 +#else + #define NRF51_ERRATA_8_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_8_ENABLE_WORKAROUND + #define NRF51_ERRATA_8_ENABLE_WORKAROUND NRF51_ERRATA_8_PRESENT +#endif + static bool nrf51_errata_8(void) { #ifndef NRF51_SERIES @@ -449,6 +532,19 @@ static bool nrf51_errata_8(void) #endif } +/* ========= Errata 9 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_9_PRESENT 1 +#else + #define NRF51_ERRATA_9_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_9_ENABLE_WORKAROUND + #define NRF51_ERRATA_9_ENABLE_WORKAROUND NRF51_ERRATA_9_PRESENT +#endif + static bool nrf51_errata_9(void) { #ifndef NRF51_SERIES @@ -500,6 +596,19 @@ static bool nrf51_errata_9(void) #endif } +/* ========= Errata 10 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_10_PRESENT 1 +#else + #define NRF51_ERRATA_10_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_10_ENABLE_WORKAROUND + #define NRF51_ERRATA_10_ENABLE_WORKAROUND NRF51_ERRATA_10_PRESENT +#endif + static bool nrf51_errata_10(void) { #ifndef NRF51_SERIES @@ -551,6 +660,19 @@ static bool nrf51_errata_10(void) #endif } +/* ========= Errata 11 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_11_PRESENT 1 +#else + #define NRF51_ERRATA_11_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_11_ENABLE_WORKAROUND + #define NRF51_ERRATA_11_ENABLE_WORKAROUND NRF51_ERRATA_11_PRESENT +#endif + static bool nrf51_errata_11(void) { #ifndef NRF51_SERIES @@ -602,6 +724,19 @@ static bool nrf51_errata_11(void) #endif } +/* ========= Errata 12 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_12_PRESENT 1 +#else + #define NRF51_ERRATA_12_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_12_ENABLE_WORKAROUND + #define NRF51_ERRATA_12_ENABLE_WORKAROUND NRF51_ERRATA_12_PRESENT +#endif + static bool nrf51_errata_12(void) { #ifndef NRF51_SERIES @@ -653,6 +788,19 @@ static bool nrf51_errata_12(void) #endif } +/* ========= Errata 13 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_13_PRESENT 1 +#else + #define NRF51_ERRATA_13_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_13_ENABLE_WORKAROUND + #define NRF51_ERRATA_13_ENABLE_WORKAROUND NRF51_ERRATA_13_PRESENT +#endif + static bool nrf51_errata_13(void) { #ifndef NRF51_SERIES @@ -704,6 +852,19 @@ static bool nrf51_errata_13(void) #endif } +/* ========= Errata 14 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_14_PRESENT 1 +#else + #define NRF51_ERRATA_14_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_14_ENABLE_WORKAROUND + #define NRF51_ERRATA_14_ENABLE_WORKAROUND NRF51_ERRATA_14_PRESENT +#endif + static bool nrf51_errata_14(void) { #ifndef NRF51_SERIES @@ -755,6 +916,19 @@ static bool nrf51_errata_14(void) #endif } +/* ========= Errata 15 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_15_PRESENT 1 +#else + #define NRF51_ERRATA_15_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_15_ENABLE_WORKAROUND + #define NRF51_ERRATA_15_ENABLE_WORKAROUND NRF51_ERRATA_15_PRESENT +#endif + static bool nrf51_errata_15(void) { #ifndef NRF51_SERIES @@ -806,6 +980,19 @@ static bool nrf51_errata_15(void) #endif } +/* ========= Errata 16 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_16_PRESENT 1 +#else + #define NRF51_ERRATA_16_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_16_ENABLE_WORKAROUND + #define NRF51_ERRATA_16_ENABLE_WORKAROUND NRF51_ERRATA_16_PRESENT +#endif + static bool nrf51_errata_16(void) { #ifndef NRF51_SERIES @@ -857,6 +1044,19 @@ static bool nrf51_errata_16(void) #endif } +/* ========= Errata 17 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_17_PRESENT 1 +#else + #define NRF51_ERRATA_17_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_17_ENABLE_WORKAROUND + #define NRF51_ERRATA_17_ENABLE_WORKAROUND NRF51_ERRATA_17_PRESENT +#endif + static bool nrf51_errata_17(void) { #ifndef NRF51_SERIES @@ -908,6 +1108,19 @@ static bool nrf51_errata_17(void) #endif } +/* ========= Errata 18 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_18_PRESENT 1 +#else + #define NRF51_ERRATA_18_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_18_ENABLE_WORKAROUND + #define NRF51_ERRATA_18_ENABLE_WORKAROUND NRF51_ERRATA_18_PRESENT +#endif + static bool nrf51_errata_18(void) { #ifndef NRF51_SERIES @@ -959,6 +1172,19 @@ static bool nrf51_errata_18(void) #endif } +/* ========= Errata 19 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_19_PRESENT 1 +#else + #define NRF51_ERRATA_19_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_19_ENABLE_WORKAROUND + #define NRF51_ERRATA_19_ENABLE_WORKAROUND NRF51_ERRATA_19_PRESENT +#endif + static bool nrf51_errata_19(void) { #ifndef NRF51_SERIES @@ -1010,6 +1236,19 @@ static bool nrf51_errata_19(void) #endif } +/* ========= Errata 20 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_20_PRESENT 1 +#else + #define NRF51_ERRATA_20_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_20_ENABLE_WORKAROUND + #define NRF51_ERRATA_20_ENABLE_WORKAROUND NRF51_ERRATA_20_PRESENT +#endif + static bool nrf51_errata_20(void) { #ifndef NRF51_SERIES @@ -1061,6 +1300,19 @@ static bool nrf51_errata_20(void) #endif } +/* ========= Errata 21 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_21_PRESENT 1 +#else + #define NRF51_ERRATA_21_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_21_ENABLE_WORKAROUND + #define NRF51_ERRATA_21_ENABLE_WORKAROUND NRF51_ERRATA_21_PRESENT +#endif + static bool nrf51_errata_21(void) { #ifndef NRF51_SERIES @@ -1112,6 +1364,19 @@ static bool nrf51_errata_21(void) #endif } +/* ========= Errata 22 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_22_PRESENT 1 +#else + #define NRF51_ERRATA_22_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_22_ENABLE_WORKAROUND + #define NRF51_ERRATA_22_ENABLE_WORKAROUND NRF51_ERRATA_22_PRESENT +#endif + static bool nrf51_errata_22(void) { #ifndef NRF51_SERIES @@ -1163,6 +1428,19 @@ static bool nrf51_errata_22(void) #endif } +/* ========= Errata 23 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_23_PRESENT 1 +#else + #define NRF51_ERRATA_23_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_23_ENABLE_WORKAROUND + #define NRF51_ERRATA_23_ENABLE_WORKAROUND NRF51_ERRATA_23_PRESENT +#endif + static bool nrf51_errata_23(void) { #ifndef NRF51_SERIES @@ -1214,6 +1492,19 @@ static bool nrf51_errata_23(void) #endif } +/* ========= Errata 24 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_24_PRESENT 1 +#else + #define NRF51_ERRATA_24_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_24_ENABLE_WORKAROUND + #define NRF51_ERRATA_24_ENABLE_WORKAROUND NRF51_ERRATA_24_PRESENT +#endif + static bool nrf51_errata_24(void) { #ifndef NRF51_SERIES @@ -1265,6 +1556,19 @@ static bool nrf51_errata_24(void) #endif } +/* ========= Errata 25 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_25_PRESENT 1 +#else + #define NRF51_ERRATA_25_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_25_ENABLE_WORKAROUND + #define NRF51_ERRATA_25_ENABLE_WORKAROUND NRF51_ERRATA_25_PRESENT +#endif + static bool nrf51_errata_25(void) { #ifndef NRF51_SERIES @@ -1316,6 +1620,19 @@ static bool nrf51_errata_25(void) #endif } +/* ========= Errata 26 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_26_PRESENT 1 +#else + #define NRF51_ERRATA_26_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_26_ENABLE_WORKAROUND + #define NRF51_ERRATA_26_ENABLE_WORKAROUND NRF51_ERRATA_26_PRESENT +#endif + static bool nrf51_errata_26(void) { #ifndef NRF51_SERIES @@ -1367,6 +1684,19 @@ static bool nrf51_errata_26(void) #endif } +/* ========= Errata 27 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_27_PRESENT 1 +#else + #define NRF51_ERRATA_27_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_27_ENABLE_WORKAROUND + #define NRF51_ERRATA_27_ENABLE_WORKAROUND NRF51_ERRATA_27_PRESENT +#endif + static bool nrf51_errata_27(void) { #ifndef NRF51_SERIES @@ -1418,6 +1748,19 @@ static bool nrf51_errata_27(void) #endif } +/* ========= Errata 28 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_28_PRESENT 1 +#else + #define NRF51_ERRATA_28_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_28_ENABLE_WORKAROUND + #define NRF51_ERRATA_28_ENABLE_WORKAROUND NRF51_ERRATA_28_PRESENT +#endif + static bool nrf51_errata_28(void) { #ifndef NRF51_SERIES @@ -1469,6 +1812,19 @@ static bool nrf51_errata_28(void) #endif } +/* ========= Errata 29 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_29_PRESENT 1 +#else + #define NRF51_ERRATA_29_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_29_ENABLE_WORKAROUND + #define NRF51_ERRATA_29_ENABLE_WORKAROUND NRF51_ERRATA_29_PRESENT +#endif + static bool nrf51_errata_29(void) { #ifndef NRF51_SERIES @@ -1520,6 +1876,19 @@ static bool nrf51_errata_29(void) #endif } +/* ========= Errata 30 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_30_PRESENT 1 +#else + #define NRF51_ERRATA_30_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_30_ENABLE_WORKAROUND + #define NRF51_ERRATA_30_ENABLE_WORKAROUND NRF51_ERRATA_30_PRESENT +#endif + static bool nrf51_errata_30(void) { #ifndef NRF51_SERIES @@ -1571,6 +1940,19 @@ static bool nrf51_errata_30(void) #endif } +/* ========= Errata 31 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_31_PRESENT 1 +#else + #define NRF51_ERRATA_31_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_31_ENABLE_WORKAROUND + #define NRF51_ERRATA_31_ENABLE_WORKAROUND NRF51_ERRATA_31_PRESENT +#endif + static bool nrf51_errata_31(void) { #ifndef NRF51_SERIES @@ -1622,6 +2004,19 @@ static bool nrf51_errata_31(void) #endif } +/* ========= Errata 32 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_32_PRESENT 1 +#else + #define NRF51_ERRATA_32_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_32_ENABLE_WORKAROUND + #define NRF51_ERRATA_32_ENABLE_WORKAROUND NRF51_ERRATA_32_PRESENT +#endif + static bool nrf51_errata_32(void) { #ifndef NRF51_SERIES @@ -1673,6 +2068,19 @@ static bool nrf51_errata_32(void) #endif } +/* ========= Errata 33 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_33_PRESENT 1 +#else + #define NRF51_ERRATA_33_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_33_ENABLE_WORKAROUND + #define NRF51_ERRATA_33_ENABLE_WORKAROUND NRF51_ERRATA_33_PRESENT +#endif + static bool nrf51_errata_33(void) { #ifndef NRF51_SERIES @@ -1724,6 +2132,19 @@ static bool nrf51_errata_33(void) #endif } +/* ========= Errata 34 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_34_PRESENT 1 +#else + #define NRF51_ERRATA_34_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_34_ENABLE_WORKAROUND + #define NRF51_ERRATA_34_ENABLE_WORKAROUND NRF51_ERRATA_34_PRESENT +#endif + static bool nrf51_errata_34(void) { #ifndef NRF51_SERIES @@ -1775,6 +2196,19 @@ static bool nrf51_errata_34(void) #endif } +/* ========= Errata 35 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_35_PRESENT 1 +#else + #define NRF51_ERRATA_35_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_35_ENABLE_WORKAROUND + #define NRF51_ERRATA_35_ENABLE_WORKAROUND NRF51_ERRATA_35_PRESENT +#endif + static bool nrf51_errata_35(void) { #ifndef NRF51_SERIES @@ -1826,6 +2260,19 @@ static bool nrf51_errata_35(void) #endif } +/* ========= Errata 36 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_36_PRESENT 1 +#else + #define NRF51_ERRATA_36_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_36_ENABLE_WORKAROUND + #define NRF51_ERRATA_36_ENABLE_WORKAROUND NRF51_ERRATA_36_PRESENT +#endif + static bool nrf51_errata_36(void) { #ifndef NRF51_SERIES @@ -1877,6 +2324,19 @@ static bool nrf51_errata_36(void) #endif } +/* ========= Errata 37 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_37_PRESENT 1 +#else + #define NRF51_ERRATA_37_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_37_ENABLE_WORKAROUND + #define NRF51_ERRATA_37_ENABLE_WORKAROUND NRF51_ERRATA_37_PRESENT +#endif + static bool nrf51_errata_37(void) { #ifndef NRF51_SERIES @@ -1928,6 +2388,19 @@ static bool nrf51_errata_37(void) #endif } +/* ========= Errata 38 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_38_PRESENT 1 +#else + #define NRF51_ERRATA_38_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_38_ENABLE_WORKAROUND + #define NRF51_ERRATA_38_ENABLE_WORKAROUND NRF51_ERRATA_38_PRESENT +#endif + static bool nrf51_errata_38(void) { #ifndef NRF51_SERIES @@ -1979,6 +2452,19 @@ static bool nrf51_errata_38(void) #endif } +/* ========= Errata 39 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_39_PRESENT 1 +#else + #define NRF51_ERRATA_39_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_39_ENABLE_WORKAROUND + #define NRF51_ERRATA_39_ENABLE_WORKAROUND NRF51_ERRATA_39_PRESENT +#endif + static bool nrf51_errata_39(void) { #ifndef NRF51_SERIES @@ -2030,6 +2516,19 @@ static bool nrf51_errata_39(void) #endif } +/* ========= Errata 40 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_40_PRESENT 1 +#else + #define NRF51_ERRATA_40_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_40_ENABLE_WORKAROUND + #define NRF51_ERRATA_40_ENABLE_WORKAROUND NRF51_ERRATA_40_PRESENT +#endif + static bool nrf51_errata_40(void) { #ifndef NRF51_SERIES @@ -2081,6 +2580,19 @@ static bool nrf51_errata_40(void) #endif } +/* ========= Errata 41 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_41_PRESENT 1 +#else + #define NRF51_ERRATA_41_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_41_ENABLE_WORKAROUND + #define NRF51_ERRATA_41_ENABLE_WORKAROUND NRF51_ERRATA_41_PRESENT +#endif + static bool nrf51_errata_41(void) { #ifndef NRF51_SERIES @@ -2132,6 +2644,19 @@ static bool nrf51_errata_41(void) #endif } +/* ========= Errata 42 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_42_PRESENT 1 +#else + #define NRF51_ERRATA_42_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_42_ENABLE_WORKAROUND + #define NRF51_ERRATA_42_ENABLE_WORKAROUND NRF51_ERRATA_42_PRESENT +#endif + static bool nrf51_errata_42(void) { #ifndef NRF51_SERIES @@ -2183,6 +2708,19 @@ static bool nrf51_errata_42(void) #endif } +/* ========= Errata 43 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_43_PRESENT 1 +#else + #define NRF51_ERRATA_43_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_43_ENABLE_WORKAROUND + #define NRF51_ERRATA_43_ENABLE_WORKAROUND NRF51_ERRATA_43_PRESENT +#endif + static bool nrf51_errata_43(void) { #ifndef NRF51_SERIES @@ -2234,6 +2772,19 @@ static bool nrf51_errata_43(void) #endif } +/* ========= Errata 44 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_44_PRESENT 1 +#else + #define NRF51_ERRATA_44_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_44_ENABLE_WORKAROUND + #define NRF51_ERRATA_44_ENABLE_WORKAROUND NRF51_ERRATA_44_PRESENT +#endif + static bool nrf51_errata_44(void) { #ifndef NRF51_SERIES @@ -2285,6 +2836,19 @@ static bool nrf51_errata_44(void) #endif } +/* ========= Errata 45 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_45_PRESENT 1 +#else + #define NRF51_ERRATA_45_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_45_ENABLE_WORKAROUND + #define NRF51_ERRATA_45_ENABLE_WORKAROUND NRF51_ERRATA_45_PRESENT +#endif + static bool nrf51_errata_45(void) { #ifndef NRF51_SERIES @@ -2336,6 +2900,19 @@ static bool nrf51_errata_45(void) #endif } +/* ========= Errata 46 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_46_PRESENT 1 +#else + #define NRF51_ERRATA_46_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_46_ENABLE_WORKAROUND + #define NRF51_ERRATA_46_ENABLE_WORKAROUND NRF51_ERRATA_46_PRESENT +#endif + static bool nrf51_errata_46(void) { #ifndef NRF51_SERIES @@ -2387,6 +2964,19 @@ static bool nrf51_errata_46(void) #endif } +/* ========= Errata 47 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_47_PRESENT 1 +#else + #define NRF51_ERRATA_47_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_47_ENABLE_WORKAROUND + #define NRF51_ERRATA_47_ENABLE_WORKAROUND NRF51_ERRATA_47_PRESENT +#endif + static bool nrf51_errata_47(void) { #ifndef NRF51_SERIES @@ -2438,6 +3028,19 @@ static bool nrf51_errata_47(void) #endif } +/* ========= Errata 48 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_48_PRESENT 1 +#else + #define NRF51_ERRATA_48_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_48_ENABLE_WORKAROUND + #define NRF51_ERRATA_48_ENABLE_WORKAROUND NRF51_ERRATA_48_PRESENT +#endif + static bool nrf51_errata_48(void) { #ifndef NRF51_SERIES @@ -2489,6 +3092,19 @@ static bool nrf51_errata_48(void) #endif } +/* ========= Errata 49 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_49_PRESENT 1 +#else + #define NRF51_ERRATA_49_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_49_ENABLE_WORKAROUND + #define NRF51_ERRATA_49_ENABLE_WORKAROUND NRF51_ERRATA_49_PRESENT +#endif + static bool nrf51_errata_49(void) { #ifndef NRF51_SERIES @@ -2540,6 +3156,13 @@ static bool nrf51_errata_49(void) #endif } +/* ========= Errata 50 ========= */ +#define NRF51_ERRATA_50_PRESENT 0 + +#ifndef NRF51_ERRATA_50_ENABLE_WORKAROUND + #define NRF51_ERRATA_50_ENABLE_WORKAROUND NRF51_ERRATA_50_PRESENT +#endif + static bool nrf51_errata_50(void) { #ifndef NRF51_SERIES @@ -2549,6 +3172,13 @@ static bool nrf51_errata_50(void) #endif } +/* ========= Errata 51 ========= */ +#define NRF51_ERRATA_51_PRESENT 0 + +#ifndef NRF51_ERRATA_51_ENABLE_WORKAROUND + #define NRF51_ERRATA_51_ENABLE_WORKAROUND NRF51_ERRATA_51_PRESENT +#endif + static bool nrf51_errata_51(void) { #ifndef NRF51_SERIES @@ -2558,6 +3188,13 @@ static bool nrf51_errata_51(void) #endif } +/* ========= Errata 52 ========= */ +#define NRF51_ERRATA_52_PRESENT 0 + +#ifndef NRF51_ERRATA_52_ENABLE_WORKAROUND + #define NRF51_ERRATA_52_ENABLE_WORKAROUND NRF51_ERRATA_52_PRESENT +#endif + static bool nrf51_errata_52(void) { #ifndef NRF51_SERIES @@ -2567,6 +3204,13 @@ static bool nrf51_errata_52(void) #endif } +/* ========= Errata 53 ========= */ +#define NRF51_ERRATA_53_PRESENT 0 + +#ifndef NRF51_ERRATA_53_ENABLE_WORKAROUND + #define NRF51_ERRATA_53_ENABLE_WORKAROUND NRF51_ERRATA_53_PRESENT +#endif + static bool nrf51_errata_53(void) { #ifndef NRF51_SERIES @@ -2576,6 +3220,13 @@ static bool nrf51_errata_53(void) #endif } +/* ========= Errata 54 ========= */ +#define NRF51_ERRATA_54_PRESENT 0 + +#ifndef NRF51_ERRATA_54_ENABLE_WORKAROUND + #define NRF51_ERRATA_54_ENABLE_WORKAROUND NRF51_ERRATA_54_PRESENT +#endif + static bool nrf51_errata_54(void) { #ifndef NRF51_SERIES @@ -2585,6 +3236,19 @@ static bool nrf51_errata_54(void) #endif } +/* ========= Errata 55 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_55_PRESENT 1 +#else + #define NRF51_ERRATA_55_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_55_ENABLE_WORKAROUND + #define NRF51_ERRATA_55_ENABLE_WORKAROUND NRF51_ERRATA_55_PRESENT +#endif + static bool nrf51_errata_55(void) { #ifndef NRF51_SERIES @@ -2636,6 +3300,19 @@ static bool nrf51_errata_55(void) #endif } +/* ========= Errata 56 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_56_PRESENT 1 +#else + #define NRF51_ERRATA_56_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_56_ENABLE_WORKAROUND + #define NRF51_ERRATA_56_ENABLE_WORKAROUND NRF51_ERRATA_56_PRESENT +#endif + static bool nrf51_errata_56(void) { #ifndef NRF51_SERIES @@ -2687,6 +3364,19 @@ static bool nrf51_errata_56(void) #endif } +/* ========= Errata 57 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_57_PRESENT 1 +#else + #define NRF51_ERRATA_57_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_57_ENABLE_WORKAROUND + #define NRF51_ERRATA_57_ENABLE_WORKAROUND NRF51_ERRATA_57_PRESENT +#endif + static bool nrf51_errata_57(void) { #ifndef NRF51_SERIES @@ -2738,6 +3428,19 @@ static bool nrf51_errata_57(void) #endif } +/* ========= Errata 58 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_58_PRESENT 1 +#else + #define NRF51_ERRATA_58_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_58_ENABLE_WORKAROUND + #define NRF51_ERRATA_58_ENABLE_WORKAROUND NRF51_ERRATA_58_PRESENT +#endif + static bool nrf51_errata_58(void) { #ifndef NRF51_SERIES @@ -2789,6 +3492,19 @@ static bool nrf51_errata_58(void) #endif } +/* ========= Errata 59 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_59_PRESENT 1 +#else + #define NRF51_ERRATA_59_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_59_ENABLE_WORKAROUND + #define NRF51_ERRATA_59_ENABLE_WORKAROUND NRF51_ERRATA_59_PRESENT +#endif + static bool nrf51_errata_59(void) { #ifndef NRF51_SERIES @@ -2840,6 +3556,19 @@ static bool nrf51_errata_59(void) #endif } +/* ========= Errata 60 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_60_PRESENT 1 +#else + #define NRF51_ERRATA_60_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_60_ENABLE_WORKAROUND + #define NRF51_ERRATA_60_ENABLE_WORKAROUND NRF51_ERRATA_60_PRESENT +#endif + static bool nrf51_errata_60(void) { #ifndef NRF51_SERIES @@ -2891,6 +3620,19 @@ static bool nrf51_errata_60(void) #endif } +/* ========= Errata 61 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_61_PRESENT 1 +#else + #define NRF51_ERRATA_61_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_61_ENABLE_WORKAROUND + #define NRF51_ERRATA_61_ENABLE_WORKAROUND NRF51_ERRATA_61_PRESENT +#endif + static bool nrf51_errata_61(void) { #ifndef NRF51_SERIES @@ -2942,6 +3684,19 @@ static bool nrf51_errata_61(void) #endif } +/* ========= Errata 62 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_62_PRESENT 1 +#else + #define NRF51_ERRATA_62_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_62_ENABLE_WORKAROUND + #define NRF51_ERRATA_62_ENABLE_WORKAROUND NRF51_ERRATA_62_PRESENT +#endif + static bool nrf51_errata_62(void) { #ifndef NRF51_SERIES @@ -2993,6 +3748,19 @@ static bool nrf51_errata_62(void) #endif } +/* ========= Errata 63 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_63_PRESENT 1 +#else + #define NRF51_ERRATA_63_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_63_ENABLE_WORKAROUND + #define NRF51_ERRATA_63_ENABLE_WORKAROUND NRF51_ERRATA_63_PRESENT +#endif + static bool nrf51_errata_63(void) { #ifndef NRF51_SERIES @@ -3044,6 +3812,19 @@ static bool nrf51_errata_63(void) #endif } +/* ========= Errata 64 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_64_PRESENT 1 +#else + #define NRF51_ERRATA_64_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_64_ENABLE_WORKAROUND + #define NRF51_ERRATA_64_ENABLE_WORKAROUND NRF51_ERRATA_64_PRESENT +#endif + static bool nrf51_errata_64(void) { #ifndef NRF51_SERIES @@ -3095,6 +3876,19 @@ static bool nrf51_errata_64(void) #endif } +/* ========= Errata 65 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_65_PRESENT 1 +#else + #define NRF51_ERRATA_65_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_65_ENABLE_WORKAROUND + #define NRF51_ERRATA_65_ENABLE_WORKAROUND NRF51_ERRATA_65_PRESENT +#endif + static bool nrf51_errata_65(void) { #ifndef NRF51_SERIES @@ -3146,6 +3940,19 @@ static bool nrf51_errata_65(void) #endif } +/* ========= Errata 66 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_66_PRESENT 1 +#else + #define NRF51_ERRATA_66_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_66_ENABLE_WORKAROUND + #define NRF51_ERRATA_66_ENABLE_WORKAROUND NRF51_ERRATA_66_PRESENT +#endif + static bool nrf51_errata_66(void) { #ifndef NRF51_SERIES @@ -3197,6 +4004,19 @@ static bool nrf51_errata_66(void) #endif } +/* ========= Errata 67 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_67_PRESENT 1 +#else + #define NRF51_ERRATA_67_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_67_ENABLE_WORKAROUND + #define NRF51_ERRATA_67_ENABLE_WORKAROUND NRF51_ERRATA_67_PRESENT +#endif + static bool nrf51_errata_67(void) { #ifndef NRF51_SERIES @@ -3248,6 +4068,19 @@ static bool nrf51_errata_67(void) #endif } +/* ========= Errata 68 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_68_PRESENT 1 +#else + #define NRF51_ERRATA_68_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_68_ENABLE_WORKAROUND + #define NRF51_ERRATA_68_ENABLE_WORKAROUND NRF51_ERRATA_68_PRESENT +#endif + static bool nrf51_errata_68(void) { #ifndef NRF51_SERIES @@ -3299,6 +4132,19 @@ static bool nrf51_errata_68(void) #endif } +/* ========= Errata 69 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_69_PRESENT 1 +#else + #define NRF51_ERRATA_69_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_69_ENABLE_WORKAROUND + #define NRF51_ERRATA_69_ENABLE_WORKAROUND NRF51_ERRATA_69_PRESENT +#endif + static bool nrf51_errata_69(void) { #ifndef NRF51_SERIES @@ -3350,6 +4196,19 @@ static bool nrf51_errata_69(void) #endif } +/* ========= Errata 70 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_70_PRESENT 1 +#else + #define NRF51_ERRATA_70_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_70_ENABLE_WORKAROUND + #define NRF51_ERRATA_70_ENABLE_WORKAROUND NRF51_ERRATA_70_PRESENT +#endif + static bool nrf51_errata_70(void) { #ifndef NRF51_SERIES @@ -3401,6 +4260,19 @@ static bool nrf51_errata_70(void) #endif } +/* ========= Errata 71 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_71_PRESENT 1 +#else + #define NRF51_ERRATA_71_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_71_ENABLE_WORKAROUND + #define NRF51_ERRATA_71_ENABLE_WORKAROUND NRF51_ERRATA_71_PRESENT +#endif + static bool nrf51_errata_71(void) { #ifndef NRF51_SERIES @@ -3452,6 +4324,19 @@ static bool nrf51_errata_71(void) #endif } +/* ========= Errata 72 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_72_PRESENT 1 +#else + #define NRF51_ERRATA_72_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_72_ENABLE_WORKAROUND + #define NRF51_ERRATA_72_ENABLE_WORKAROUND NRF51_ERRATA_72_PRESENT +#endif + static bool nrf51_errata_72(void) { #ifndef NRF51_SERIES @@ -3503,6 +4388,19 @@ static bool nrf51_errata_72(void) #endif } +/* ========= Errata 73 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_73_PRESENT 1 +#else + #define NRF51_ERRATA_73_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_73_ENABLE_WORKAROUND + #define NRF51_ERRATA_73_ENABLE_WORKAROUND NRF51_ERRATA_73_PRESENT +#endif + static bool nrf51_errata_73(void) { #ifndef NRF51_SERIES @@ -3554,6 +4452,19 @@ static bool nrf51_errata_73(void) #endif } +/* ========= Errata 74 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_74_PRESENT 1 +#else + #define NRF51_ERRATA_74_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_74_ENABLE_WORKAROUND + #define NRF51_ERRATA_74_ENABLE_WORKAROUND NRF51_ERRATA_74_PRESENT +#endif + static bool nrf51_errata_74(void) { #ifndef NRF51_SERIES @@ -3605,6 +4516,19 @@ static bool nrf51_errata_74(void) #endif } +/* ========= Errata 75 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_75_PRESENT 1 +#else + #define NRF51_ERRATA_75_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_75_ENABLE_WORKAROUND + #define NRF51_ERRATA_75_ENABLE_WORKAROUND NRF51_ERRATA_75_PRESENT +#endif + static bool nrf51_errata_75(void) { #ifndef NRF51_SERIES @@ -3656,6 +4580,19 @@ static bool nrf51_errata_75(void) #endif } +/* ========= Errata 76 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_76_PRESENT 1 +#else + #define NRF51_ERRATA_76_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_76_ENABLE_WORKAROUND + #define NRF51_ERRATA_76_ENABLE_WORKAROUND NRF51_ERRATA_76_PRESENT +#endif + static bool nrf51_errata_76(void) { #ifndef NRF51_SERIES @@ -3707,6 +4644,13 @@ static bool nrf51_errata_76(void) #endif } +/* ========= Errata 77 ========= */ +#define NRF51_ERRATA_77_PRESENT 0 + +#ifndef NRF51_ERRATA_77_ENABLE_WORKAROUND + #define NRF51_ERRATA_77_ENABLE_WORKAROUND NRF51_ERRATA_77_PRESENT +#endif + static bool nrf51_errata_77(void) { #ifndef NRF51_SERIES @@ -3716,6 +4660,19 @@ static bool nrf51_errata_77(void) #endif } +/* ========= Errata 78 ========= */ +#if defined (NRF51422_XXAA) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAB) || defined (DEVELOP_IN_NRF51422) \ + || defined (NRF51422_XXAC) || defined (DEVELOP_IN_NRF51422) + #define NRF51_ERRATA_78_PRESENT 1 +#else + #define NRF51_ERRATA_78_PRESENT 0 +#endif + +#ifndef NRF51_ERRATA_78_ENABLE_WORKAROUND + #define NRF51_ERRATA_78_ENABLE_WORKAROUND NRF51_ERRATA_78_PRESENT +#endif + static bool nrf51_errata_78(void) { #ifndef NRF51_SERIES diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf51_to_nrf52.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf51_to_nrf52.h index 49eeb1c98..2168fb44c 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf51_to_nrf52.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf51_to_nrf52.h @@ -1,41 +1,32 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52.h index 2e8c7b09c..28f759663 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52.h @@ -1,48 +1,39 @@ /* - * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * * 3. Neither the name of Nordic Semiconductor ASA nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. * * @file nrf52.h * @brief CMSIS HeaderFile * @version 1 - * @date 14. August 2020 - * @note Generated by SVDConv V3.3.35 on Friday, 14.08.2020 15:04:39 + * @date 15. January 2021 + * @note Generated by SVDConv V3.3.35 on Friday, 15.01.2021 17:02:05 * from File 'nrf52.svd', - * last modified on Friday, 14.08.2020 13:04:32 + * last modified on Friday, 15.01.2021 16:02:00 */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52820.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52820.h index 5ba199743..8f1ab8801 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52820.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52820.h @@ -1,48 +1,39 @@ /* - * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * * 3. Neither the name of Nordic Semiconductor ASA nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. * * @file nrf52820.h * @brief CMSIS HeaderFile * @version 1 - * @date 14. August 2020 - * @note Generated by SVDConv V3.3.35 on Friday, 14.08.2020 15:04:39 + * @date 15. January 2021 + * @note Generated by SVDConv V3.3.35 on Friday, 15.01.2021 17:02:04 * from File 'nrf52820.svd', - * last modified on Friday, 14.08.2020 13:04:32 + * last modified on Friday, 15.01.2021 16:02:00 */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_bitfields.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_bitfields.h index 827b8f376..c9156f9da 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_bitfields.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_bitfields.h @@ -1,41 +1,32 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_peripherals.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_peripherals.h index 0dd2dcba0..cd392e693 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_peripherals.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_peripherals.h @@ -1,41 +1,32 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. */ @@ -83,7 +74,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define RADIO_PRESENT #define RADIO_COUNT 1 -#define RADIO_EASYDMA_MAXCNT_SIZE 16 +#define RADIO_EASYDMA_MAXCNT_SIZE 14 #define RADIO_FEATURE_IEEE_802_15_4_PRESENT #define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos8dBm @@ -175,15 +166,15 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define SPIM0_FEATURE_RXDELAY_PRESENT 0 #define SPIM1_FEATURE_RXDELAY_PRESENT 0 -#define SPIM0_EASYDMA_MAXCNT_SIZE 16 -#define SPIM1_EASYDMA_MAXCNT_SIZE 16 +#define SPIM0_EASYDMA_MAXCNT_SIZE 15 +#define SPIM1_EASYDMA_MAXCNT_SIZE 15 /* Serial Peripheral Interface Slave with DMA*/ #define SPIS_PRESENT #define SPIS_COUNT 2 -#define SPIS0_EASYDMA_MAXCNT_SIZE 16 -#define SPIS1_EASYDMA_MAXCNT_SIZE 16 +#define SPIS0_EASYDMA_MAXCNT_SIZE 15 +#define SPIS1_EASYDMA_MAXCNT_SIZE 15 /* Two Wire Interface Master */ #define TWI_PRESENT @@ -193,15 +184,15 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define TWIM_PRESENT #define TWIM_COUNT 2 -#define TWIM0_EASYDMA_MAXCNT_SIZE 16 -#define TWIM1_EASYDMA_MAXCNT_SIZE 16 +#define TWIM0_EASYDMA_MAXCNT_SIZE 15 +#define TWIM1_EASYDMA_MAXCNT_SIZE 15 /* Two Wire Interface Slave with DMA */ #define TWIS_PRESENT #define TWIS_COUNT 2 -#define TWIS0_EASYDMA_MAXCNT_SIZE 16 -#define TWIS1_EASYDMA_MAXCNT_SIZE 16 +#define TWIS0_EASYDMA_MAXCNT_SIZE 15 +#define TWIS1_EASYDMA_MAXCNT_SIZE 15 /* Universal Asynchronous Receiver-Transmitter */ #define UART_PRESENT @@ -211,7 +202,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define UARTE_PRESENT #define UARTE_COUNT 1 -#define UARTE0_EASYDMA_MAXCNT_SIZE 16 +#define UARTE0_EASYDMA_MAXCNT_SIZE 15 /* Quadrature Decoder */ #define QDEC_PRESENT diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52833_to_nrf52820.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52833_to_nrf52820.h index 09777aeca..93f798396 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52833_to_nrf52820.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52833_to_nrf52820.h @@ -1,41 +1,32 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_bitfields.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_bitfields.h index 70672e800..035e7e451 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_bitfields.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_bitfields.h @@ -1,41 +1,32 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_erratas.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_erratas.h index d6ca9197f..a1d5e9100 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_erratas.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_erratas.h @@ -3,42 +3,33 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. */ @@ -222,7 +213,26 @@ static bool nrf52_errata_232(void) __UNUSED; static bool nrf52_errata_233(void) __UNUSED; static bool nrf52_errata_236(void) __UNUSED; static bool nrf52_errata_237(void) __UNUSED; +static bool nrf52_errata_242(void) __UNUSED; +static bool nrf52_errata_243(void) __UNUSED; +static bool nrf52_errata_244(void) __UNUSED; +static bool nrf52_errata_245(void) __UNUSED; +static bool nrf52_errata_246(void) __UNUSED; static bool nrf52_errata_248(void) __UNUSED; +static bool nrf52_errata_249(void) __UNUSED; +static bool nrf52_errata_250(void) __UNUSED; + +/* ========= Errata 1 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_1_PRESENT 1 +#else + #define NRF52_ERRATA_1_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_1_ENABLE_WORKAROUND + #define NRF52_ERRATA_1_ENABLE_WORKAROUND NRF52_ERRATA_1_PRESENT +#endif static bool nrf52_errata_1(void) { @@ -257,6 +267,18 @@ static bool nrf52_errata_1(void) #endif } +/* ========= Errata 2 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_2_PRESENT 1 +#else + #define NRF52_ERRATA_2_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_2_ENABLE_WORKAROUND + #define NRF52_ERRATA_2_ENABLE_WORKAROUND NRF52_ERRATA_2_PRESENT +#endif + static bool nrf52_errata_2(void) { #ifndef NRF52_SERIES @@ -290,6 +312,18 @@ static bool nrf52_errata_2(void) #endif } +/* ========= Errata 3 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_3_PRESENT 1 +#else + #define NRF52_ERRATA_3_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_3_ENABLE_WORKAROUND + #define NRF52_ERRATA_3_ENABLE_WORKAROUND NRF52_ERRATA_3_PRESENT +#endif + static bool nrf52_errata_3(void) { #ifndef NRF52_SERIES @@ -323,6 +357,18 @@ static bool nrf52_errata_3(void) #endif } +/* ========= Errata 4 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_4_PRESENT 1 +#else + #define NRF52_ERRATA_4_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_4_ENABLE_WORKAROUND + #define NRF52_ERRATA_4_ENABLE_WORKAROUND NRF52_ERRATA_4_PRESENT +#endif + static bool nrf52_errata_4(void) { #ifndef NRF52_SERIES @@ -356,6 +402,18 @@ static bool nrf52_errata_4(void) #endif } +/* ========= Errata 7 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_7_PRESENT 1 +#else + #define NRF52_ERRATA_7_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_7_ENABLE_WORKAROUND + #define NRF52_ERRATA_7_ENABLE_WORKAROUND NRF52_ERRATA_7_PRESENT +#endif + static bool nrf52_errata_7(void) { #ifndef NRF52_SERIES @@ -389,6 +447,18 @@ static bool nrf52_errata_7(void) #endif } +/* ========= Errata 8 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_8_PRESENT 1 +#else + #define NRF52_ERRATA_8_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_8_ENABLE_WORKAROUND + #define NRF52_ERRATA_8_ENABLE_WORKAROUND NRF52_ERRATA_8_PRESENT +#endif + static bool nrf52_errata_8(void) { #ifndef NRF52_SERIES @@ -422,6 +492,18 @@ static bool nrf52_errata_8(void) #endif } +/* ========= Errata 9 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_9_PRESENT 1 +#else + #define NRF52_ERRATA_9_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_9_ENABLE_WORKAROUND + #define NRF52_ERRATA_9_ENABLE_WORKAROUND NRF52_ERRATA_9_PRESENT +#endif + static bool nrf52_errata_9(void) { #ifndef NRF52_SERIES @@ -455,6 +537,18 @@ static bool nrf52_errata_9(void) #endif } +/* ========= Errata 10 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_10_PRESENT 1 +#else + #define NRF52_ERRATA_10_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_10_ENABLE_WORKAROUND + #define NRF52_ERRATA_10_ENABLE_WORKAROUND NRF52_ERRATA_10_PRESENT +#endif + static bool nrf52_errata_10(void) { #ifndef NRF52_SERIES @@ -488,6 +582,18 @@ static bool nrf52_errata_10(void) #endif } +/* ========= Errata 11 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_11_PRESENT 1 +#else + #define NRF52_ERRATA_11_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_11_ENABLE_WORKAROUND + #define NRF52_ERRATA_11_ENABLE_WORKAROUND NRF52_ERRATA_11_PRESENT +#endif + static bool nrf52_errata_11(void) { #ifndef NRF52_SERIES @@ -521,6 +627,18 @@ static bool nrf52_errata_11(void) #endif } +/* ========= Errata 12 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_12_PRESENT 1 +#else + #define NRF52_ERRATA_12_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_12_ENABLE_WORKAROUND + #define NRF52_ERRATA_12_ENABLE_WORKAROUND NRF52_ERRATA_12_PRESENT +#endif + static bool nrf52_errata_12(void) { #ifndef NRF52_SERIES @@ -565,6 +683,22 @@ static bool nrf52_errata_12(void) #endif } +/* ========= Errata 15 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_15_PRESENT 1 +#else + #define NRF52_ERRATA_15_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_15_ENABLE_WORKAROUND + #define NRF52_ERRATA_15_ENABLE_WORKAROUND NRF52_ERRATA_15_PRESENT +#endif + static bool nrf52_errata_15(void) { #ifndef NRF52_SERIES @@ -624,6 +758,10 @@ static bool nrf52_errata_15(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -671,6 +809,18 @@ static bool nrf52_errata_15(void) #endif } +/* ========= Errata 16 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_16_PRESENT 1 +#else + #define NRF52_ERRATA_16_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_16_ENABLE_WORKAROUND + #define NRF52_ERRATA_16_ENABLE_WORKAROUND NRF52_ERRATA_16_PRESENT +#endif + static bool nrf52_errata_16(void) { #ifndef NRF52_SERIES @@ -704,6 +854,18 @@ static bool nrf52_errata_16(void) #endif } +/* ========= Errata 17 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_17_PRESENT 1 +#else + #define NRF52_ERRATA_17_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_17_ENABLE_WORKAROUND + #define NRF52_ERRATA_17_ENABLE_WORKAROUND NRF52_ERRATA_17_PRESENT +#endif + static bool nrf52_errata_17(void) { #ifndef NRF52_SERIES @@ -737,6 +899,24 @@ static bool nrf52_errata_17(void) #endif } +/* ========= Errata 20 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_20_PRESENT 1 +#else + #define NRF52_ERRATA_20_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_20_ENABLE_WORKAROUND + #define NRF52_ERRATA_20_ENABLE_WORKAROUND NRF52_ERRATA_20_PRESENT +#endif + static bool nrf52_errata_20(void) { #ifndef NRF52_SERIES @@ -798,8 +978,12 @@ static bool nrf52_errata_20(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -875,6 +1059,18 @@ static bool nrf52_errata_20(void) #endif } +/* ========= Errata 23 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_23_PRESENT 1 +#else + #define NRF52_ERRATA_23_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_23_ENABLE_WORKAROUND + #define NRF52_ERRATA_23_ENABLE_WORKAROUND NRF52_ERRATA_23_PRESENT +#endif + static bool nrf52_errata_23(void) { #ifndef NRF52_SERIES @@ -908,6 +1104,18 @@ static bool nrf52_errata_23(void) #endif } +/* ========= Errata 24 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_24_PRESENT 1 +#else + #define NRF52_ERRATA_24_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_24_ENABLE_WORKAROUND + #define NRF52_ERRATA_24_ENABLE_WORKAROUND NRF52_ERRATA_24_PRESENT +#endif + static bool nrf52_errata_24(void) { #ifndef NRF52_SERIES @@ -941,6 +1149,18 @@ static bool nrf52_errata_24(void) #endif } +/* ========= Errata 25 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_25_PRESENT 1 +#else + #define NRF52_ERRATA_25_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_25_ENABLE_WORKAROUND + #define NRF52_ERRATA_25_ENABLE_WORKAROUND NRF52_ERRATA_25_PRESENT +#endif + static bool nrf52_errata_25(void) { #ifndef NRF52_SERIES @@ -974,6 +1194,18 @@ static bool nrf52_errata_25(void) #endif } +/* ========= Errata 26 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_26_PRESENT 1 +#else + #define NRF52_ERRATA_26_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_26_ENABLE_WORKAROUND + #define NRF52_ERRATA_26_ENABLE_WORKAROUND NRF52_ERRATA_26_PRESENT +#endif + static bool nrf52_errata_26(void) { #ifndef NRF52_SERIES @@ -1007,6 +1239,18 @@ static bool nrf52_errata_26(void) #endif } +/* ========= Errata 27 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_27_PRESENT 1 +#else + #define NRF52_ERRATA_27_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_27_ENABLE_WORKAROUND + #define NRF52_ERRATA_27_ENABLE_WORKAROUND NRF52_ERRATA_27_PRESENT +#endif + static bool nrf52_errata_27(void) { #ifndef NRF52_SERIES @@ -1040,6 +1284,18 @@ static bool nrf52_errata_27(void) #endif } +/* ========= Errata 28 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_28_PRESENT 1 +#else + #define NRF52_ERRATA_28_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_28_ENABLE_WORKAROUND + #define NRF52_ERRATA_28_ENABLE_WORKAROUND NRF52_ERRATA_28_PRESENT +#endif + static bool nrf52_errata_28(void) { #ifndef NRF52_SERIES @@ -1073,6 +1329,18 @@ static bool nrf52_errata_28(void) #endif } +/* ========= Errata 29 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_29_PRESENT 1 +#else + #define NRF52_ERRATA_29_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_29_ENABLE_WORKAROUND + #define NRF52_ERRATA_29_ENABLE_WORKAROUND NRF52_ERRATA_29_PRESENT +#endif + static bool nrf52_errata_29(void) { #ifndef NRF52_SERIES @@ -1106,6 +1374,18 @@ static bool nrf52_errata_29(void) #endif } +/* ========= Errata 30 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_30_PRESENT 1 +#else + #define NRF52_ERRATA_30_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_30_ENABLE_WORKAROUND + #define NRF52_ERRATA_30_ENABLE_WORKAROUND NRF52_ERRATA_30_PRESENT +#endif + static bool nrf52_errata_30(void) { #ifndef NRF52_SERIES @@ -1139,6 +1419,21 @@ static bool nrf52_errata_30(void) #endif } +/* ========= Errata 31 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_31_PRESENT 1 +#else + #define NRF52_ERRATA_31_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_31_ENABLE_WORKAROUND + #define NRF52_ERRATA_31_ENABLE_WORKAROUND NRF52_ERRATA_31_PRESENT +#endif + static bool nrf52_errata_31(void) { #ifndef NRF52_SERIES @@ -1226,6 +1521,18 @@ static bool nrf52_errata_31(void) #endif } +/* ========= Errata 32 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_32_PRESENT 1 +#else + #define NRF52_ERRATA_32_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_32_ENABLE_WORKAROUND + #define NRF52_ERRATA_32_ENABLE_WORKAROUND NRF52_ERRATA_32_PRESENT +#endif + static bool nrf52_errata_32(void) { #ifndef NRF52_SERIES @@ -1259,6 +1566,18 @@ static bool nrf52_errata_32(void) #endif } +/* ========= Errata 33 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_33_PRESENT 1 +#else + #define NRF52_ERRATA_33_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_33_ENABLE_WORKAROUND + #define NRF52_ERRATA_33_ENABLE_WORKAROUND NRF52_ERRATA_33_PRESENT +#endif + static bool nrf52_errata_33(void) { #ifndef NRF52_SERIES @@ -1292,6 +1611,18 @@ static bool nrf52_errata_33(void) #endif } +/* ========= Errata 34 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_34_PRESENT 1 +#else + #define NRF52_ERRATA_34_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_34_ENABLE_WORKAROUND + #define NRF52_ERRATA_34_ENABLE_WORKAROUND NRF52_ERRATA_34_PRESENT +#endif + static bool nrf52_errata_34(void) { #ifndef NRF52_SERIES @@ -1325,6 +1656,18 @@ static bool nrf52_errata_34(void) #endif } +/* ========= Errata 35 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_35_PRESENT 1 +#else + #define NRF52_ERRATA_35_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_35_ENABLE_WORKAROUND + #define NRF52_ERRATA_35_ENABLE_WORKAROUND NRF52_ERRATA_35_PRESENT +#endif + static bool nrf52_errata_35(void) { #ifndef NRF52_SERIES @@ -1358,6 +1701,24 @@ static bool nrf52_errata_35(void) #endif } +/* ========= Errata 36 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_36_PRESENT 1 +#else + #define NRF52_ERRATA_36_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_36_ENABLE_WORKAROUND + #define NRF52_ERRATA_36_ENABLE_WORKAROUND NRF52_ERRATA_36_PRESENT +#endif + static bool nrf52_errata_36(void) { #ifndef NRF52_SERIES @@ -1419,8 +1780,12 @@ static bool nrf52_errata_36(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -1496,6 +1861,18 @@ static bool nrf52_errata_36(void) #endif } +/* ========= Errata 37 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_37_PRESENT 1 +#else + #define NRF52_ERRATA_37_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_37_ENABLE_WORKAROUND + #define NRF52_ERRATA_37_ENABLE_WORKAROUND NRF52_ERRATA_37_PRESENT +#endif + static bool nrf52_errata_37(void) { #ifndef NRF52_SERIES @@ -1529,6 +1906,18 @@ static bool nrf52_errata_37(void) #endif } +/* ========= Errata 38 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_38_PRESENT 1 +#else + #define NRF52_ERRATA_38_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_38_ENABLE_WORKAROUND + #define NRF52_ERRATA_38_ENABLE_WORKAROUND NRF52_ERRATA_38_PRESENT +#endif + static bool nrf52_errata_38(void) { #ifndef NRF52_SERIES @@ -1562,6 +1951,18 @@ static bool nrf52_errata_38(void) #endif } +/* ========= Errata 39 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_39_PRESENT 1 +#else + #define NRF52_ERRATA_39_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_39_ENABLE_WORKAROUND + #define NRF52_ERRATA_39_ENABLE_WORKAROUND NRF52_ERRATA_39_PRESENT +#endif + static bool nrf52_errata_39(void) { #ifndef NRF52_SERIES @@ -1595,6 +1996,18 @@ static bool nrf52_errata_39(void) #endif } +/* ========= Errata 40 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_40_PRESENT 1 +#else + #define NRF52_ERRATA_40_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_40_ENABLE_WORKAROUND + #define NRF52_ERRATA_40_ENABLE_WORKAROUND NRF52_ERRATA_40_PRESENT +#endif + static bool nrf52_errata_40(void) { #ifndef NRF52_SERIES @@ -1628,6 +2041,18 @@ static bool nrf52_errata_40(void) #endif } +/* ========= Errata 41 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_41_PRESENT 1 +#else + #define NRF52_ERRATA_41_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_41_ENABLE_WORKAROUND + #define NRF52_ERRATA_41_ENABLE_WORKAROUND NRF52_ERRATA_41_PRESENT +#endif + static bool nrf52_errata_41(void) { #ifndef NRF52_SERIES @@ -1661,6 +2086,18 @@ static bool nrf52_errata_41(void) #endif } +/* ========= Errata 42 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_42_PRESENT 1 +#else + #define NRF52_ERRATA_42_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_42_ENABLE_WORKAROUND + #define NRF52_ERRATA_42_ENABLE_WORKAROUND NRF52_ERRATA_42_PRESENT +#endif + static bool nrf52_errata_42(void) { #ifndef NRF52_SERIES @@ -1694,6 +2131,18 @@ static bool nrf52_errata_42(void) #endif } +/* ========= Errata 43 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_43_PRESENT 1 +#else + #define NRF52_ERRATA_43_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_43_ENABLE_WORKAROUND + #define NRF52_ERRATA_43_ENABLE_WORKAROUND NRF52_ERRATA_43_PRESENT +#endif + static bool nrf52_errata_43(void) { #ifndef NRF52_SERIES @@ -1727,6 +2176,18 @@ static bool nrf52_errata_43(void) #endif } +/* ========= Errata 44 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_44_PRESENT 1 +#else + #define NRF52_ERRATA_44_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_44_ENABLE_WORKAROUND + #define NRF52_ERRATA_44_ENABLE_WORKAROUND NRF52_ERRATA_44_PRESENT +#endif + static bool nrf52_errata_44(void) { #ifndef NRF52_SERIES @@ -1760,6 +2221,18 @@ static bool nrf52_errata_44(void) #endif } +/* ========= Errata 46 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_46_PRESENT 1 +#else + #define NRF52_ERRATA_46_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_46_ENABLE_WORKAROUND + #define NRF52_ERRATA_46_ENABLE_WORKAROUND NRF52_ERRATA_46_PRESENT +#endif + static bool nrf52_errata_46(void) { #ifndef NRF52_SERIES @@ -1793,6 +2266,18 @@ static bool nrf52_errata_46(void) #endif } +/* ========= Errata 47 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_47_PRESENT 1 +#else + #define NRF52_ERRATA_47_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_47_ENABLE_WORKAROUND + #define NRF52_ERRATA_47_ENABLE_WORKAROUND NRF52_ERRATA_47_PRESENT +#endif + static bool nrf52_errata_47(void) { #ifndef NRF52_SERIES @@ -1826,6 +2311,18 @@ static bool nrf52_errata_47(void) #endif } +/* ========= Errata 48 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_48_PRESENT 1 +#else + #define NRF52_ERRATA_48_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_48_ENABLE_WORKAROUND + #define NRF52_ERRATA_48_ENABLE_WORKAROUND NRF52_ERRATA_48_PRESENT +#endif + static bool nrf52_errata_48(void) { #ifndef NRF52_SERIES @@ -1859,6 +2356,18 @@ static bool nrf52_errata_48(void) #endif } +/* ========= Errata 49 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_49_PRESENT 1 +#else + #define NRF52_ERRATA_49_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_49_ENABLE_WORKAROUND + #define NRF52_ERRATA_49_ENABLE_WORKAROUND NRF52_ERRATA_49_PRESENT +#endif + static bool nrf52_errata_49(void) { #ifndef NRF52_SERIES @@ -1892,6 +2401,18 @@ static bool nrf52_errata_49(void) #endif } +/* ========= Errata 51 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_51_PRESENT 1 +#else + #define NRF52_ERRATA_51_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_51_ENABLE_WORKAROUND + #define NRF52_ERRATA_51_ENABLE_WORKAROUND NRF52_ERRATA_51_PRESENT +#endif + static bool nrf52_errata_51(void) { #ifndef NRF52_SERIES @@ -1936,6 +2457,19 @@ static bool nrf52_errata_51(void) #endif } +/* ========= Errata 54 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_54_PRESENT 1 +#else + #define NRF52_ERRATA_54_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_54_ENABLE_WORKAROUND + #define NRF52_ERRATA_54_ENABLE_WORKAROUND NRF52_ERRATA_54_PRESENT +#endif + static bool nrf52_errata_54(void) { #ifndef NRF52_SERIES @@ -1992,6 +2526,10 @@ static bool nrf52_errata_54(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2001,6 +2539,21 @@ static bool nrf52_errata_54(void) #endif } +/* ========= Errata 55 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_55_PRESENT 1 +#else + #define NRF52_ERRATA_55_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_55_ENABLE_WORKAROUND + #define NRF52_ERRATA_55_ENABLE_WORKAROUND NRF52_ERRATA_55_PRESENT +#endif + static bool nrf52_errata_55(void) { #ifndef NRF52_SERIES @@ -2059,8 +2612,12 @@ static bool nrf52_errata_55(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -2098,6 +2655,18 @@ static bool nrf52_errata_55(void) #endif } +/* ========= Errata 57 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_57_PRESENT 1 +#else + #define NRF52_ERRATA_57_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_57_ENABLE_WORKAROUND + #define NRF52_ERRATA_57_ENABLE_WORKAROUND NRF52_ERRATA_57_PRESENT +#endif + static bool nrf52_errata_57(void) { #ifndef NRF52_SERIES @@ -2131,6 +2700,19 @@ static bool nrf52_errata_57(void) #endif } +/* ========= Errata 58 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_58_PRESENT 1 +#else + #define NRF52_ERRATA_58_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_58_ENABLE_WORKAROUND + #define NRF52_ERRATA_58_ENABLE_WORKAROUND NRF52_ERRATA_58_PRESENT +#endif + static bool nrf52_errata_58(void) { #ifndef NRF52_SERIES @@ -2187,6 +2769,10 @@ static bool nrf52_errata_58(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2196,6 +2782,18 @@ static bool nrf52_errata_58(void) #endif } +/* ========= Errata 62 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_62_PRESENT 1 +#else + #define NRF52_ERRATA_62_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_62_ENABLE_WORKAROUND + #define NRF52_ERRATA_62_ENABLE_WORKAROUND NRF52_ERRATA_62_PRESENT +#endif + static bool nrf52_errata_62(void) { #ifndef NRF52_SERIES @@ -2229,6 +2827,18 @@ static bool nrf52_errata_62(void) #endif } +/* ========= Errata 63 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_63_PRESENT 1 +#else + #define NRF52_ERRATA_63_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_63_ENABLE_WORKAROUND + #define NRF52_ERRATA_63_ENABLE_WORKAROUND NRF52_ERRATA_63_PRESENT +#endif + static bool nrf52_errata_63(void) { #ifndef NRF52_SERIES @@ -2262,6 +2872,18 @@ static bool nrf52_errata_63(void) #endif } +/* ========= Errata 64 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_64_PRESENT 1 +#else + #define NRF52_ERRATA_64_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_64_ENABLE_WORKAROUND + #define NRF52_ERRATA_64_ENABLE_WORKAROUND NRF52_ERRATA_64_PRESENT +#endif + static bool nrf52_errata_64(void) { #ifndef NRF52_SERIES @@ -2306,6 +2928,18 @@ static bool nrf52_errata_64(void) #endif } +/* ========= Errata 65 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_65_PRESENT 1 +#else + #define NRF52_ERRATA_65_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_65_ENABLE_WORKAROUND + #define NRF52_ERRATA_65_ENABLE_WORKAROUND NRF52_ERRATA_65_PRESENT +#endif + static bool nrf52_errata_65(void) { #ifndef NRF52_SERIES @@ -2339,6 +2973,24 @@ static bool nrf52_errata_65(void) #endif } +/* ========= Errata 66 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_66_PRESENT 1 +#else + #define NRF52_ERRATA_66_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_66_ENABLE_WORKAROUND + #define NRF52_ERRATA_66_ENABLE_WORKAROUND NRF52_ERRATA_66_PRESENT +#endif + static bool nrf52_errata_66(void) { #ifndef NRF52_SERIES @@ -2400,8 +3052,12 @@ static bool nrf52_errata_66(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -2477,6 +3133,18 @@ static bool nrf52_errata_66(void) #endif } +/* ========= Errata 67 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_67_PRESENT 1 +#else + #define NRF52_ERRATA_67_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_67_ENABLE_WORKAROUND + #define NRF52_ERRATA_67_ENABLE_WORKAROUND NRF52_ERRATA_67_PRESENT +#endif + static bool nrf52_errata_67(void) { #ifndef NRF52_SERIES @@ -2521,6 +3189,22 @@ static bool nrf52_errata_67(void) #endif } +/* ========= Errata 68 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_68_PRESENT 1 +#else + #define NRF52_ERRATA_68_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_68_ENABLE_WORKAROUND + #define NRF52_ERRATA_68_ENABLE_WORKAROUND NRF52_ERRATA_68_PRESENT +#endif + static bool nrf52_errata_68(void) { #ifndef NRF52_SERIES @@ -2580,6 +3264,10 @@ static bool nrf52_errata_68(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2627,6 +3315,18 @@ static bool nrf52_errata_68(void) #endif } +/* ========= Errata 70 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_70_PRESENT 1 +#else + #define NRF52_ERRATA_70_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_70_ENABLE_WORKAROUND + #define NRF52_ERRATA_70_ENABLE_WORKAROUND NRF52_ERRATA_70_PRESENT +#endif + static bool nrf52_errata_70(void) { #ifndef NRF52_SERIES @@ -2660,6 +3360,18 @@ static bool nrf52_errata_70(void) #endif } +/* ========= Errata 71 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_71_PRESENT 1 +#else + #define NRF52_ERRATA_71_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_71_ENABLE_WORKAROUND + #define NRF52_ERRATA_71_ENABLE_WORKAROUND NRF52_ERRATA_71_PRESENT +#endif + static bool nrf52_errata_71(void) { #ifndef NRF52_SERIES @@ -2693,6 +3405,18 @@ static bool nrf52_errata_71(void) #endif } +/* ========= Errata 72 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_72_PRESENT 1 +#else + #define NRF52_ERRATA_72_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_72_ENABLE_WORKAROUND + #define NRF52_ERRATA_72_ENABLE_WORKAROUND NRF52_ERRATA_72_PRESENT +#endif + static bool nrf52_errata_72(void) { #ifndef NRF52_SERIES @@ -2737,6 +3461,18 @@ static bool nrf52_errata_72(void) #endif } +/* ========= Errata 73 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_73_PRESENT 1 +#else + #define NRF52_ERRATA_73_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_73_ENABLE_WORKAROUND + #define NRF52_ERRATA_73_ENABLE_WORKAROUND NRF52_ERRATA_73_PRESENT +#endif + static bool nrf52_errata_73(void) { #ifndef NRF52_SERIES @@ -2770,6 +3506,18 @@ static bool nrf52_errata_73(void) #endif } +/* ========= Errata 74 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_74_PRESENT 1 +#else + #define NRF52_ERRATA_74_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_74_ENABLE_WORKAROUND + #define NRF52_ERRATA_74_ENABLE_WORKAROUND NRF52_ERRATA_74_PRESENT +#endif + static bool nrf52_errata_74(void) { #ifndef NRF52_SERIES @@ -2814,6 +3562,18 @@ static bool nrf52_errata_74(void) #endif } +/* ========= Errata 75 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_75_PRESENT 1 +#else + #define NRF52_ERRATA_75_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_75_ENABLE_WORKAROUND + #define NRF52_ERRATA_75_ENABLE_WORKAROUND NRF52_ERRATA_75_PRESENT +#endif + static bool nrf52_errata_75(void) { #ifndef NRF52_SERIES @@ -2858,6 +3618,18 @@ static bool nrf52_errata_75(void) #endif } +/* ========= Errata 76 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_76_PRESENT 1 +#else + #define NRF52_ERRATA_76_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_76_ENABLE_WORKAROUND + #define NRF52_ERRATA_76_ENABLE_WORKAROUND NRF52_ERRATA_76_PRESENT +#endif + static bool nrf52_errata_76(void) { #ifndef NRF52_SERIES @@ -2902,6 +3674,21 @@ static bool nrf52_errata_76(void) #endif } +/* ========= Errata 77 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_77_PRESENT 1 +#else + #define NRF52_ERRATA_77_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_77_ENABLE_WORKAROUND + #define NRF52_ERRATA_77_ENABLE_WORKAROUND NRF52_ERRATA_77_PRESENT +#endif + static bool nrf52_errata_77(void) { #ifndef NRF52_SERIES @@ -2989,6 +3776,24 @@ static bool nrf52_errata_77(void) #endif } +/* ========= Errata 78 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_78_PRESENT 1 +#else + #define NRF52_ERRATA_78_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_78_ENABLE_WORKAROUND + #define NRF52_ERRATA_78_ENABLE_WORKAROUND NRF52_ERRATA_78_PRESENT +#endif + static bool nrf52_errata_78(void) { #ifndef NRF52_SERIES @@ -3050,8 +3855,12 @@ static bool nrf52_errata_78(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -3127,6 +3936,18 @@ static bool nrf52_errata_78(void) #endif } +/* ========= Errata 79 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_79_PRESENT 1 +#else + #define NRF52_ERRATA_79_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_79_ENABLE_WORKAROUND + #define NRF52_ERRATA_79_ENABLE_WORKAROUND NRF52_ERRATA_79_PRESENT +#endif + static bool nrf52_errata_79(void) { #ifndef NRF52_SERIES @@ -3171,6 +3992,22 @@ static bool nrf52_errata_79(void) #endif } +/* ========= Errata 81 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_81_PRESENT 1 +#else + #define NRF52_ERRATA_81_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_81_ENABLE_WORKAROUND + #define NRF52_ERRATA_81_ENABLE_WORKAROUND NRF52_ERRATA_81_PRESENT +#endif + static bool nrf52_errata_81(void) { #ifndef NRF52_SERIES @@ -3230,8 +4067,12 @@ static bool nrf52_errata_81(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -3277,6 +4118,22 @@ static bool nrf52_errata_81(void) #endif } +/* ========= Errata 83 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_83_PRESENT 1 +#else + #define NRF52_ERRATA_83_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_83_ENABLE_WORKAROUND + #define NRF52_ERRATA_83_ENABLE_WORKAROUND NRF52_ERRATA_83_PRESENT +#endif + static bool nrf52_errata_83(void) { #ifndef NRF52_SERIES @@ -3336,6 +4193,10 @@ static bool nrf52_errata_83(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -3383,6 +4244,18 @@ static bool nrf52_errata_83(void) #endif } +/* ========= Errata 84 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_84_PRESENT 1 +#else + #define NRF52_ERRATA_84_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_84_ENABLE_WORKAROUND + #define NRF52_ERRATA_84_ENABLE_WORKAROUND NRF52_ERRATA_84_PRESENT +#endif + static bool nrf52_errata_84(void) { #ifndef NRF52_SERIES @@ -3427,6 +4300,18 @@ static bool nrf52_errata_84(void) #endif } +/* ========= Errata 86 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_86_PRESENT 1 +#else + #define NRF52_ERRATA_86_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_86_ENABLE_WORKAROUND + #define NRF52_ERRATA_86_ENABLE_WORKAROUND NRF52_ERRATA_86_PRESENT +#endif + static bool nrf52_errata_86(void) { #ifndef NRF52_SERIES @@ -3471,6 +4356,21 @@ static bool nrf52_errata_86(void) #endif } +/* ========= Errata 87 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_87_PRESENT 1 +#else + #define NRF52_ERRATA_87_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_87_ENABLE_WORKAROUND + #define NRF52_ERRATA_87_ENABLE_WORKAROUND NRF52_ERRATA_87_PRESENT +#endif + static bool nrf52_errata_87(void) { #ifndef NRF52_SERIES @@ -3529,8 +4429,12 @@ static bool nrf52_errata_87(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -3558,9 +4462,9 @@ static bool nrf52_errata_87(void) case 0x01ul: return true; case 0x02ul: - return true; + return false; default: - return true; + return false; } } #endif @@ -3568,6 +4472,21 @@ static bool nrf52_errata_87(void) #endif } +/* ========= Errata 88 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_88_PRESENT 1 +#else + #define NRF52_ERRATA_88_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_88_ENABLE_WORKAROUND + #define NRF52_ERRATA_88_ENABLE_WORKAROUND NRF52_ERRATA_88_PRESENT +#endif + static bool nrf52_errata_88(void) { #ifndef NRF52_SERIES @@ -3655,6 +4574,19 @@ static bool nrf52_errata_88(void) #endif } +/* ========= Errata 89 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_89_PRESENT 1 +#else + #define NRF52_ERRATA_89_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_89_ENABLE_WORKAROUND + #define NRF52_ERRATA_89_ENABLE_WORKAROUND NRF52_ERRATA_89_PRESENT +#endif + static bool nrf52_errata_89(void) { #ifndef NRF52_SERIES @@ -3711,6 +4643,10 @@ static bool nrf52_errata_89(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -3720,6 +4656,18 @@ static bool nrf52_errata_89(void) #endif } +/* ========= Errata 91 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_91_PRESENT 1 +#else + #define NRF52_ERRATA_91_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_91_ENABLE_WORKAROUND + #define NRF52_ERRATA_91_ENABLE_WORKAROUND NRF52_ERRATA_91_PRESENT +#endif + static bool nrf52_errata_91(void) { #ifndef NRF52_SERIES @@ -3764,6 +4712,17 @@ static bool nrf52_errata_91(void) #endif } +/* ========= Errata 94 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_94_PRESENT 1 +#else + #define NRF52_ERRATA_94_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_94_ENABLE_WORKAROUND + #define NRF52_ERRATA_94_ENABLE_WORKAROUND NRF52_ERRATA_94_PRESENT +#endif + static bool nrf52_errata_94(void) { #ifndef NRF52_SERIES @@ -3786,6 +4745,10 @@ static bool nrf52_errata_94(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -3795,6 +4758,17 @@ static bool nrf52_errata_94(void) #endif } +/* ========= Errata 96 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_96_PRESENT 1 +#else + #define NRF52_ERRATA_96_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_96_ENABLE_WORKAROUND + #define NRF52_ERRATA_96_ENABLE_WORKAROUND NRF52_ERRATA_96_PRESENT +#endif + static bool nrf52_errata_96(void) { #ifndef NRF52_SERIES @@ -3817,6 +4791,10 @@ static bool nrf52_errata_96(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -3826,6 +4804,19 @@ static bool nrf52_errata_96(void) #endif } +/* ========= Errata 97 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_97_PRESENT 1 +#else + #define NRF52_ERRATA_97_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_97_ENABLE_WORKAROUND + #define NRF52_ERRATA_97_ENABLE_WORKAROUND NRF52_ERRATA_97_PRESENT +#endif + static bool nrf52_errata_97(void) { #ifndef NRF52_SERIES @@ -3882,6 +4873,10 @@ static bool nrf52_errata_97(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -3891,6 +4886,17 @@ static bool nrf52_errata_97(void) #endif } +/* ========= Errata 98 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_98_PRESENT 1 +#else + #define NRF52_ERRATA_98_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_98_ENABLE_WORKAROUND + #define NRF52_ERRATA_98_ENABLE_WORKAROUND NRF52_ERRATA_98_PRESENT +#endif + static bool nrf52_errata_98(void) { #ifndef NRF52_SERIES @@ -3913,6 +4919,10 @@ static bool nrf52_errata_98(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -3922,6 +4932,18 @@ static bool nrf52_errata_98(void) #endif } +/* ========= Errata 101 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_101_PRESENT 1 +#else + #define NRF52_ERRATA_101_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_101_ENABLE_WORKAROUND + #define NRF52_ERRATA_101_ENABLE_WORKAROUND NRF52_ERRATA_101_PRESENT +#endif + static bool nrf52_errata_101(void) { #ifndef NRF52_SERIES @@ -3966,6 +4988,18 @@ static bool nrf52_errata_101(void) #endif } +/* ========= Errata 102 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_102_PRESENT 1 +#else + #define NRF52_ERRATA_102_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_102_ENABLE_WORKAROUND + #define NRF52_ERRATA_102_ENABLE_WORKAROUND NRF52_ERRATA_102_PRESENT +#endif + static bool nrf52_errata_102(void) { #ifndef NRF52_SERIES @@ -4010,6 +5044,17 @@ static bool nrf52_errata_102(void) #endif } +/* ========= Errata 103 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_103_PRESENT 1 +#else + #define NRF52_ERRATA_103_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_103_ENABLE_WORKAROUND + #define NRF52_ERRATA_103_ENABLE_WORKAROUND NRF52_ERRATA_103_PRESENT +#endif + static bool nrf52_errata_103(void) { #ifndef NRF52_SERIES @@ -4032,6 +5077,10 @@ static bool nrf52_errata_103(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -4041,6 +5090,17 @@ static bool nrf52_errata_103(void) #endif } +/* ========= Errata 104 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_104_PRESENT 1 +#else + #define NRF52_ERRATA_104_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_104_ENABLE_WORKAROUND + #define NRF52_ERRATA_104_ENABLE_WORKAROUND NRF52_ERRATA_104_PRESENT +#endif + static bool nrf52_errata_104(void) { #ifndef NRF52_SERIES @@ -4063,6 +5123,10 @@ static bool nrf52_errata_104(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -4072,6 +5136,18 @@ static bool nrf52_errata_104(void) #endif } +/* ========= Errata 106 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_106_PRESENT 1 +#else + #define NRF52_ERRATA_106_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_106_ENABLE_WORKAROUND + #define NRF52_ERRATA_106_ENABLE_WORKAROUND NRF52_ERRATA_106_PRESENT +#endif + static bool nrf52_errata_106(void) { #ifndef NRF52_SERIES @@ -4116,7 +5192,19 @@ static bool nrf52_errata_106(void) #endif } -static bool nrf52_errata_107(void) +/* ========= Errata 107 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_107_PRESENT 1 +#else + #define NRF52_ERRATA_107_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_107_ENABLE_WORKAROUND + #define NRF52_ERRATA_107_ENABLE_WORKAROUND NRF52_ERRATA_107_PRESENT +#endif + +static bool nrf52_errata_107(void) { #ifndef NRF52_SERIES return false; @@ -4160,6 +5248,18 @@ static bool nrf52_errata_107(void) #endif } +/* ========= Errata 108 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_108_PRESENT 1 +#else + #define NRF52_ERRATA_108_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_108_ENABLE_WORKAROUND + #define NRF52_ERRATA_108_ENABLE_WORKAROUND NRF52_ERRATA_108_PRESENT +#endif + static bool nrf52_errata_108(void) { #ifndef NRF52_SERIES @@ -4204,6 +5304,18 @@ static bool nrf52_errata_108(void) #endif } +/* ========= Errata 109 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_109_PRESENT 1 +#else + #define NRF52_ERRATA_109_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_109_ENABLE_WORKAROUND + #define NRF52_ERRATA_109_ENABLE_WORKAROUND NRF52_ERRATA_109_PRESENT +#endif + static bool nrf52_errata_109(void) { #ifndef NRF52_SERIES @@ -4248,6 +5360,17 @@ static bool nrf52_errata_109(void) #endif } +/* ========= Errata 110 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_110_PRESENT 1 +#else + #define NRF52_ERRATA_110_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_110_ENABLE_WORKAROUND + #define NRF52_ERRATA_110_ENABLE_WORKAROUND NRF52_ERRATA_110_PRESENT +#endif + static bool nrf52_errata_110(void) { #ifndef NRF52_SERIES @@ -4270,6 +5393,10 @@ static bool nrf52_errata_110(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -4279,6 +5406,17 @@ static bool nrf52_errata_110(void) #endif } +/* ========= Errata 111 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_111_PRESENT 1 +#else + #define NRF52_ERRATA_111_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_111_ENABLE_WORKAROUND + #define NRF52_ERRATA_111_ENABLE_WORKAROUND NRF52_ERRATA_111_PRESENT +#endif + static bool nrf52_errata_111(void) { #ifndef NRF52_SERIES @@ -4301,6 +5439,10 @@ static bool nrf52_errata_111(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -4310,6 +5452,17 @@ static bool nrf52_errata_111(void) #endif } +/* ========= Errata 112 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_112_PRESENT 1 +#else + #define NRF52_ERRATA_112_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_112_ENABLE_WORKAROUND + #define NRF52_ERRATA_112_ENABLE_WORKAROUND NRF52_ERRATA_112_PRESENT +#endif + static bool nrf52_errata_112(void) { #ifndef NRF52_SERIES @@ -4332,6 +5485,10 @@ static bool nrf52_errata_112(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -4341,6 +5498,19 @@ static bool nrf52_errata_112(void) #endif } +/* ========= Errata 113 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_113_PRESENT 1 +#else + #define NRF52_ERRATA_113_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_113_ENABLE_WORKAROUND + #define NRF52_ERRATA_113_ENABLE_WORKAROUND NRF52_ERRATA_113_PRESENT +#endif + static bool nrf52_errata_113(void) { #ifndef NRF52_SERIES @@ -4397,6 +5567,10 @@ static bool nrf52_errata_113(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -4406,6 +5580,17 @@ static bool nrf52_errata_113(void) #endif } +/* ========= Errata 115 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_115_PRESENT 1 +#else + #define NRF52_ERRATA_115_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_115_ENABLE_WORKAROUND + #define NRF52_ERRATA_115_ENABLE_WORKAROUND NRF52_ERRATA_115_PRESENT +#endif + static bool nrf52_errata_115(void) { #ifndef NRF52_SERIES @@ -4428,6 +5613,10 @@ static bool nrf52_errata_115(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -4437,6 +5626,17 @@ static bool nrf52_errata_115(void) #endif } +/* ========= Errata 116 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_116_PRESENT 1 +#else + #define NRF52_ERRATA_116_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_116_ENABLE_WORKAROUND + #define NRF52_ERRATA_116_ENABLE_WORKAROUND NRF52_ERRATA_116_PRESENT +#endif + static bool nrf52_errata_116(void) { #ifndef NRF52_SERIES @@ -4459,6 +5659,10 @@ static bool nrf52_errata_116(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -4468,6 +5672,17 @@ static bool nrf52_errata_116(void) #endif } +/* ========= Errata 117 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_117_PRESENT 1 +#else + #define NRF52_ERRATA_117_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_117_ENABLE_WORKAROUND + #define NRF52_ERRATA_117_ENABLE_WORKAROUND NRF52_ERRATA_117_PRESENT +#endif + static bool nrf52_errata_117(void) { #ifndef NRF52_SERIES @@ -4490,6 +5705,10 @@ static bool nrf52_errata_117(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -4499,6 +5718,17 @@ static bool nrf52_errata_117(void) #endif } +/* ========= Errata 118 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_118_PRESENT 1 +#else + #define NRF52_ERRATA_118_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_118_ENABLE_WORKAROUND + #define NRF52_ERRATA_118_ENABLE_WORKAROUND NRF52_ERRATA_118_PRESENT +#endif + static bool nrf52_errata_118(void) { #ifndef NRF52_SERIES @@ -4521,6 +5751,10 @@ static bool nrf52_errata_118(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -4530,6 +5764,17 @@ static bool nrf52_errata_118(void) #endif } +/* ========= Errata 119 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_119_PRESENT 1 +#else + #define NRF52_ERRATA_119_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_119_ENABLE_WORKAROUND + #define NRF52_ERRATA_119_ENABLE_WORKAROUND NRF52_ERRATA_119_PRESENT +#endif + static bool nrf52_errata_119(void) { #ifndef NRF52_SERIES @@ -4552,6 +5797,10 @@ static bool nrf52_errata_119(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -4561,6 +5810,17 @@ static bool nrf52_errata_119(void) #endif } +/* ========= Errata 120 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_120_PRESENT 1 +#else + #define NRF52_ERRATA_120_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_120_ENABLE_WORKAROUND + #define NRF52_ERRATA_120_ENABLE_WORKAROUND NRF52_ERRATA_120_PRESENT +#endif + static bool nrf52_errata_120(void) { #ifndef NRF52_SERIES @@ -4583,6 +5843,10 @@ static bool nrf52_errata_120(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -4592,6 +5856,17 @@ static bool nrf52_errata_120(void) #endif } +/* ========= Errata 121 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_121_PRESENT 1 +#else + #define NRF52_ERRATA_121_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_121_ENABLE_WORKAROUND + #define NRF52_ERRATA_121_ENABLE_WORKAROUND NRF52_ERRATA_121_PRESENT +#endif + static bool nrf52_errata_121(void) { #ifndef NRF52_SERIES @@ -4614,6 +5889,10 @@ static bool nrf52_errata_121(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -4623,6 +5902,17 @@ static bool nrf52_errata_121(void) #endif } +/* ========= Errata 122 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_122_PRESENT 1 +#else + #define NRF52_ERRATA_122_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_122_ENABLE_WORKAROUND + #define NRF52_ERRATA_122_ENABLE_WORKAROUND NRF52_ERRATA_122_PRESENT +#endif + static bool nrf52_errata_122(void) { #ifndef NRF52_SERIES @@ -4645,8 +5935,12 @@ static bool nrf52_errata_122(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -4654,6 +5948,17 @@ static bool nrf52_errata_122(void) #endif } +/* ========= Errata 127 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_127_PRESENT 1 +#else + #define NRF52_ERRATA_127_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_127_ENABLE_WORKAROUND + #define NRF52_ERRATA_127_ENABLE_WORKAROUND NRF52_ERRATA_127_PRESENT +#endif + static bool nrf52_errata_127(void) { #ifndef NRF52_SERIES @@ -4676,6 +5981,10 @@ static bool nrf52_errata_127(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -4685,6 +5994,17 @@ static bool nrf52_errata_127(void) #endif } +/* ========= Errata 128 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_128_PRESENT 1 +#else + #define NRF52_ERRATA_128_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_128_ENABLE_WORKAROUND + #define NRF52_ERRATA_128_ENABLE_WORKAROUND NRF52_ERRATA_128_PRESENT +#endif + static bool nrf52_errata_128(void) { #ifndef NRF52_SERIES @@ -4707,6 +6027,10 @@ static bool nrf52_errata_128(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -4716,6 +6040,17 @@ static bool nrf52_errata_128(void) #endif } +/* ========= Errata 131 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_131_PRESENT 1 +#else + #define NRF52_ERRATA_131_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_131_ENABLE_WORKAROUND + #define NRF52_ERRATA_131_ENABLE_WORKAROUND NRF52_ERRATA_131_PRESENT +#endif + static bool nrf52_errata_131(void) { #ifndef NRF52_SERIES @@ -4738,6 +6073,10 @@ static bool nrf52_errata_131(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -4747,6 +6086,18 @@ static bool nrf52_errata_131(void) #endif } +/* ========= Errata 132 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_132_PRESENT 1 +#else + #define NRF52_ERRATA_132_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_132_ENABLE_WORKAROUND + #define NRF52_ERRATA_132_ENABLE_WORKAROUND NRF52_ERRATA_132_PRESENT +#endif + static bool nrf52_errata_132(void) { #ifndef NRF52_SERIES @@ -4791,6 +6142,17 @@ static bool nrf52_errata_132(void) #endif } +/* ========= Errata 133 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_133_PRESENT 1 +#else + #define NRF52_ERRATA_133_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_133_ENABLE_WORKAROUND + #define NRF52_ERRATA_133_ENABLE_WORKAROUND NRF52_ERRATA_133_PRESENT +#endif + static bool nrf52_errata_133(void) { #ifndef NRF52_SERIES @@ -4813,6 +6175,10 @@ static bool nrf52_errata_133(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -4822,6 +6188,17 @@ static bool nrf52_errata_133(void) #endif } +/* ========= Errata 134 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_134_PRESENT 1 +#else + #define NRF52_ERRATA_134_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_134_ENABLE_WORKAROUND + #define NRF52_ERRATA_134_ENABLE_WORKAROUND NRF52_ERRATA_134_PRESENT +#endif + static bool nrf52_errata_134(void) { #ifndef NRF52_SERIES @@ -4844,6 +6221,10 @@ static bool nrf52_errata_134(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -4853,6 +6234,17 @@ static bool nrf52_errata_134(void) #endif } +/* ========= Errata 135 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_135_PRESENT 1 +#else + #define NRF52_ERRATA_135_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_135_ENABLE_WORKAROUND + #define NRF52_ERRATA_135_ENABLE_WORKAROUND NRF52_ERRATA_135_PRESENT +#endif + static bool nrf52_errata_135(void) { #ifndef NRF52_SERIES @@ -4875,6 +6267,10 @@ static bool nrf52_errata_135(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -4884,6 +6280,24 @@ static bool nrf52_errata_135(void) #endif } +/* ========= Errata 136 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_136_PRESENT 1 +#else + #define NRF52_ERRATA_136_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_136_ENABLE_WORKAROUND + #define NRF52_ERRATA_136_ENABLE_WORKAROUND NRF52_ERRATA_136_PRESENT +#endif + static bool nrf52_errata_136(void) { #ifndef NRF52_SERIES @@ -4945,8 +6359,12 @@ static bool nrf52_errata_136(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -5022,6 +6440,18 @@ static bool nrf52_errata_136(void) #endif } +/* ========= Errata 138 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_138_PRESENT 1 +#else + #define NRF52_ERRATA_138_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_138_ENABLE_WORKAROUND + #define NRF52_ERRATA_138_ENABLE_WORKAROUND NRF52_ERRATA_138_PRESENT +#endif + static bool nrf52_errata_138(void) { #ifndef NRF52_SERIES @@ -5066,6 +6496,17 @@ static bool nrf52_errata_138(void) #endif } +/* ========= Errata 140 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_140_PRESENT 1 +#else + #define NRF52_ERRATA_140_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_140_ENABLE_WORKAROUND + #define NRF52_ERRATA_140_ENABLE_WORKAROUND NRF52_ERRATA_140_PRESENT +#endif + static bool nrf52_errata_140(void) { #ifndef NRF52_SERIES @@ -5088,6 +6529,10 @@ static bool nrf52_errata_140(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -5097,6 +6542,18 @@ static bool nrf52_errata_140(void) #endif } +/* ========= Errata 141 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_141_PRESENT 1 +#else + #define NRF52_ERRATA_141_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_141_ENABLE_WORKAROUND + #define NRF52_ERRATA_141_ENABLE_WORKAROUND NRF52_ERRATA_141_PRESENT +#endif + static bool nrf52_errata_141(void) { #ifndef NRF52_SERIES @@ -5141,6 +6598,17 @@ static bool nrf52_errata_141(void) #endif } +/* ========= Errata 142 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_142_PRESENT 1 +#else + #define NRF52_ERRATA_142_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_142_ENABLE_WORKAROUND + #define NRF52_ERRATA_142_ENABLE_WORKAROUND NRF52_ERRATA_142_PRESENT +#endif + static bool nrf52_errata_142(void) { #ifndef NRF52_SERIES @@ -5163,6 +6631,10 @@ static bool nrf52_errata_142(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -5172,6 +6644,19 @@ static bool nrf52_errata_142(void) #endif } +/* ========= Errata 143 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_143_PRESENT 1 +#else + #define NRF52_ERRATA_143_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_143_ENABLE_WORKAROUND + #define NRF52_ERRATA_143_ENABLE_WORKAROUND NRF52_ERRATA_143_PRESENT +#endif + static bool nrf52_errata_143(void) { #ifndef NRF52_SERIES @@ -5228,6 +6713,10 @@ static bool nrf52_errata_143(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -5237,6 +6726,17 @@ static bool nrf52_errata_143(void) #endif } +/* ========= Errata 144 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_144_PRESENT 1 +#else + #define NRF52_ERRATA_144_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_144_ENABLE_WORKAROUND + #define NRF52_ERRATA_144_ENABLE_WORKAROUND NRF52_ERRATA_144_PRESENT +#endif + static bool nrf52_errata_144(void) { #ifndef NRF52_SERIES @@ -5259,6 +6759,10 @@ static bool nrf52_errata_144(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -5268,6 +6772,17 @@ static bool nrf52_errata_144(void) #endif } +/* ========= Errata 145 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_145_PRESENT 1 +#else + #define NRF52_ERRATA_145_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_145_ENABLE_WORKAROUND + #define NRF52_ERRATA_145_ENABLE_WORKAROUND NRF52_ERRATA_145_PRESENT +#endif + static bool nrf52_errata_145(void) { #ifndef NRF52_SERIES @@ -5290,6 +6805,10 @@ static bool nrf52_errata_145(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -5299,6 +6818,18 @@ static bool nrf52_errata_145(void) #endif } +/* ========= Errata 146 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_146_PRESENT 1 +#else + #define NRF52_ERRATA_146_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_146_ENABLE_WORKAROUND + #define NRF52_ERRATA_146_ENABLE_WORKAROUND NRF52_ERRATA_146_PRESENT +#endif + static bool nrf52_errata_146(void) { #ifndef NRF52_SERIES @@ -5343,6 +6874,17 @@ static bool nrf52_errata_146(void) #endif } +/* ========= Errata 147 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_147_PRESENT 1 +#else + #define NRF52_ERRATA_147_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_147_ENABLE_WORKAROUND + #define NRF52_ERRATA_147_ENABLE_WORKAROUND NRF52_ERRATA_147_PRESENT +#endif + static bool nrf52_errata_147(void) { #ifndef NRF52_SERIES @@ -5365,6 +6907,10 @@ static bool nrf52_errata_147(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -5374,6 +6920,18 @@ static bool nrf52_errata_147(void) #endif } +/* ========= Errata 149 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_149_PRESENT 1 +#else + #define NRF52_ERRATA_149_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_149_ENABLE_WORKAROUND + #define NRF52_ERRATA_149_ENABLE_WORKAROUND NRF52_ERRATA_149_PRESENT +#endif + static bool nrf52_errata_149(void) { #ifndef NRF52_SERIES @@ -5418,6 +6976,20 @@ static bool nrf52_errata_149(void) #endif } +/* ========= Errata 150 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_150_PRESENT 1 +#else + #define NRF52_ERRATA_150_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_150_ENABLE_WORKAROUND + #define NRF52_ERRATA_150_ENABLE_WORKAROUND NRF52_ERRATA_150_PRESENT +#endif + static bool nrf52_errata_150(void) { #ifndef NRF52_SERIES @@ -5475,6 +7047,10 @@ static bool nrf52_errata_150(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -5498,6 +7074,17 @@ static bool nrf52_errata_150(void) #endif } +/* ========= Errata 151 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_151_PRESENT 1 +#else + #define NRF52_ERRATA_151_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_151_ENABLE_WORKAROUND + #define NRF52_ERRATA_151_ENABLE_WORKAROUND NRF52_ERRATA_151_PRESENT +#endif + static bool nrf52_errata_151(void) { #ifndef NRF52_SERIES @@ -5520,6 +7107,10 @@ static bool nrf52_errata_151(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -5529,6 +7120,17 @@ static bool nrf52_errata_151(void) #endif } +/* ========= Errata 153 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_153_PRESENT 1 +#else + #define NRF52_ERRATA_153_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_153_ENABLE_WORKAROUND + #define NRF52_ERRATA_153_ENABLE_WORKAROUND NRF52_ERRATA_153_PRESENT +#endif + static bool nrf52_errata_153(void) { #ifndef NRF52_SERIES @@ -5551,8 +7153,12 @@ static bool nrf52_errata_153(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -5560,6 +7166,17 @@ static bool nrf52_errata_153(void) #endif } +/* ========= Errata 154 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_154_PRESENT 1 +#else + #define NRF52_ERRATA_154_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_154_ENABLE_WORKAROUND + #define NRF52_ERRATA_154_ENABLE_WORKAROUND NRF52_ERRATA_154_PRESENT +#endif + static bool nrf52_errata_154(void) { #ifndef NRF52_SERIES @@ -5582,6 +7199,10 @@ static bool nrf52_errata_154(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -5591,6 +7212,22 @@ static bool nrf52_errata_154(void) #endif } +/* ========= Errata 155 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_155_PRESENT 1 +#else + #define NRF52_ERRATA_155_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_155_ENABLE_WORKAROUND + #define NRF52_ERRATA_155_ENABLE_WORKAROUND NRF52_ERRATA_155_PRESENT +#endif + static bool nrf52_errata_155(void) { #ifndef NRF52_SERIES @@ -5650,8 +7287,12 @@ static bool nrf52_errata_155(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -5697,6 +7338,22 @@ static bool nrf52_errata_155(void) #endif } +/* ========= Errata 156 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_156_PRESENT 1 +#else + #define NRF52_ERRATA_156_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_156_ENABLE_WORKAROUND + #define NRF52_ERRATA_156_ENABLE_WORKAROUND NRF52_ERRATA_156_PRESENT +#endif + static bool nrf52_errata_156(void) { #ifndef NRF52_SERIES @@ -5756,6 +7413,10 @@ static bool nrf52_errata_156(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -5803,6 +7464,17 @@ static bool nrf52_errata_156(void) #endif } +/* ========= Errata 158 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_158_PRESENT 1 +#else + #define NRF52_ERRATA_158_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_158_ENABLE_WORKAROUND + #define NRF52_ERRATA_158_ENABLE_WORKAROUND NRF52_ERRATA_158_PRESENT +#endif + static bool nrf52_errata_158(void) { #ifndef NRF52_SERIES @@ -5825,6 +7497,10 @@ static bool nrf52_errata_158(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -5834,6 +7510,17 @@ static bool nrf52_errata_158(void) #endif } +/* ========= Errata 160 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_160_PRESENT 1 +#else + #define NRF52_ERRATA_160_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_160_ENABLE_WORKAROUND + #define NRF52_ERRATA_160_ENABLE_WORKAROUND NRF52_ERRATA_160_PRESENT +#endif + static bool nrf52_errata_160(void) { #ifndef NRF52_SERIES @@ -5856,6 +7543,10 @@ static bool nrf52_errata_160(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -5865,6 +7556,17 @@ static bool nrf52_errata_160(void) #endif } +/* ========= Errata 162 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_162_PRESENT 1 +#else + #define NRF52_ERRATA_162_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_162_ENABLE_WORKAROUND + #define NRF52_ERRATA_162_ENABLE_WORKAROUND NRF52_ERRATA_162_PRESENT +#endif + static bool nrf52_errata_162(void) { #ifndef NRF52_SERIES @@ -5887,6 +7589,10 @@ static bool nrf52_errata_162(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -5896,6 +7602,18 @@ static bool nrf52_errata_162(void) #endif } +/* ========= Errata 163 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_163_PRESENT 1 +#else + #define NRF52_ERRATA_163_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_163_ENABLE_WORKAROUND + #define NRF52_ERRATA_163_ENABLE_WORKAROUND NRF52_ERRATA_163_PRESENT +#endif + static bool nrf52_errata_163(void) { #ifndef NRF52_SERIES @@ -5940,6 +7658,17 @@ static bool nrf52_errata_163(void) #endif } +/* ========= Errata 164 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_164_PRESENT 1 +#else + #define NRF52_ERRATA_164_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_164_ENABLE_WORKAROUND + #define NRF52_ERRATA_164_ENABLE_WORKAROUND NRF52_ERRATA_164_PRESENT +#endif + static bool nrf52_errata_164(void) { #ifndef NRF52_SERIES @@ -5962,6 +7691,10 @@ static bool nrf52_errata_164(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -5971,6 +7704,17 @@ static bool nrf52_errata_164(void) #endif } +/* ========= Errata 166 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_166_PRESENT 1 +#else + #define NRF52_ERRATA_166_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_166_ENABLE_WORKAROUND + #define NRF52_ERRATA_166_ENABLE_WORKAROUND NRF52_ERRATA_166_PRESENT +#endif + static bool nrf52_errata_166(void) { #ifndef NRF52_SERIES @@ -5993,8 +7737,12 @@ static bool nrf52_errata_166(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -6002,6 +7750,19 @@ static bool nrf52_errata_166(void) #endif } +/* ========= Errata 170 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_170_PRESENT 1 +#else + #define NRF52_ERRATA_170_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_170_ENABLE_WORKAROUND + #define NRF52_ERRATA_170_ENABLE_WORKAROUND NRF52_ERRATA_170_PRESENT +#endif + static bool nrf52_errata_170(void) { #ifndef NRF52_SERIES @@ -6026,8 +7787,12 @@ static bool nrf52_errata_170(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -6065,6 +7830,17 @@ static bool nrf52_errata_170(void) #endif } +/* ========= Errata 171 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_171_PRESENT 1 +#else + #define NRF52_ERRATA_171_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_171_ENABLE_WORKAROUND + #define NRF52_ERRATA_171_ENABLE_WORKAROUND NRF52_ERRATA_171_PRESENT +#endif + static bool nrf52_errata_171(void) { #ifndef NRF52_SERIES @@ -6087,8 +7863,12 @@ static bool nrf52_errata_171(void) return true; case 0x03ul: return true; - default: - return true; + case 0x04ul: + return false; + case 0x05ul: + return false; + default: + return false; } } #endif @@ -6096,6 +7876,17 @@ static bool nrf52_errata_171(void) #endif } +/* ========= Errata 172 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_172_PRESENT 1 +#else + #define NRF52_ERRATA_172_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_172_ENABLE_WORKAROUND + #define NRF52_ERRATA_172_ENABLE_WORKAROUND NRF52_ERRATA_172_PRESENT +#endif + static bool nrf52_errata_172(void) { #ifndef NRF52_SERIES @@ -6118,8 +7909,12 @@ static bool nrf52_errata_172(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -6127,6 +7922,24 @@ static bool nrf52_errata_172(void) #endif } +/* ========= Errata 173 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_173_PRESENT 1 +#else + #define NRF52_ERRATA_173_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_173_ENABLE_WORKAROUND + #define NRF52_ERRATA_173_ENABLE_WORKAROUND NRF52_ERRATA_173_PRESENT +#endif + static bool nrf52_errata_173(void) { #ifndef NRF52_SERIES @@ -6188,8 +8001,12 @@ static bool nrf52_errata_173(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -6265,6 +8082,17 @@ static bool nrf52_errata_173(void) #endif } +/* ========= Errata 174 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_174_PRESENT 1 +#else + #define NRF52_ERRATA_174_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_174_ENABLE_WORKAROUND + #define NRF52_ERRATA_174_ENABLE_WORKAROUND NRF52_ERRATA_174_PRESENT +#endif + static bool nrf52_errata_174(void) { #ifndef NRF52_SERIES @@ -6287,8 +8115,12 @@ static bool nrf52_errata_174(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -6296,6 +8128,24 @@ static bool nrf52_errata_174(void) #endif } +/* ========= Errata 176 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_176_PRESENT 1 +#else + #define NRF52_ERRATA_176_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_176_ENABLE_WORKAROUND + #define NRF52_ERRATA_176_ENABLE_WORKAROUND NRF52_ERRATA_176_PRESENT +#endif + static bool nrf52_errata_176(void) { #ifndef NRF52_SERIES @@ -6357,8 +8207,12 @@ static bool nrf52_errata_176(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -6434,6 +8288,18 @@ static bool nrf52_errata_176(void) #endif } +/* ========= Errata 178 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_178_PRESENT 1 +#else + #define NRF52_ERRATA_178_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_178_ENABLE_WORKAROUND + #define NRF52_ERRATA_178_ENABLE_WORKAROUND NRF52_ERRATA_178_PRESENT +#endif + static bool nrf52_errata_178(void) { #ifndef NRF52_SERIES @@ -6478,6 +8344,22 @@ static bool nrf52_errata_178(void) #endif } +/* ========= Errata 179 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_179_PRESENT 1 +#else + #define NRF52_ERRATA_179_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_179_ENABLE_WORKAROUND + #define NRF52_ERRATA_179_ENABLE_WORKAROUND NRF52_ERRATA_179_PRESENT +#endif + static bool nrf52_errata_179(void) { #ifndef NRF52_SERIES @@ -6537,8 +8419,12 @@ static bool nrf52_errata_179(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -6584,6 +8470,17 @@ static bool nrf52_errata_179(void) #endif } +/* ========= Errata 180 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_180_PRESENT 1 +#else + #define NRF52_ERRATA_180_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_180_ENABLE_WORKAROUND + #define NRF52_ERRATA_180_ENABLE_WORKAROUND NRF52_ERRATA_180_PRESENT +#endif + static bool nrf52_errata_180(void) { #ifndef NRF52_SERIES @@ -6606,6 +8503,10 @@ static bool nrf52_errata_180(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -6615,6 +8516,19 @@ static bool nrf52_errata_180(void) #endif } +/* ========= Errata 181 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_181_PRESENT 1 +#else + #define NRF52_ERRATA_181_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_181_ENABLE_WORKAROUND + #define NRF52_ERRATA_181_ENABLE_WORKAROUND NRF52_ERRATA_181_PRESENT +#endif + static bool nrf52_errata_181(void) { #ifndef NRF52_SERIES @@ -6671,6 +8585,10 @@ static bool nrf52_errata_181(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -6680,6 +8598,18 @@ static bool nrf52_errata_181(void) #endif } +/* ========= Errata 182 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_182_PRESENT 1 +#else + #define NRF52_ERRATA_182_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_182_ENABLE_WORKAROUND + #define NRF52_ERRATA_182_ENABLE_WORKAROUND NRF52_ERRATA_182_PRESENT +#endif + static bool nrf52_errata_182(void) { #ifndef NRF52_SERIES @@ -6713,6 +8643,23 @@ static bool nrf52_errata_182(void) #endif } +/* ========= Errata 183 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_183_PRESENT 1 +#else + #define NRF52_ERRATA_183_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_183_ENABLE_WORKAROUND + #define NRF52_ERRATA_183_ENABLE_WORKAROUND NRF52_ERRATA_183_PRESENT +#endif + static bool nrf52_errata_183(void) { #ifndef NRF52_SERIES @@ -6773,8 +8720,12 @@ static bool nrf52_errata_183(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -6838,6 +8789,22 @@ static bool nrf52_errata_183(void) #endif } +/* ========= Errata 184 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_184_PRESENT 1 +#else + #define NRF52_ERRATA_184_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_184_ENABLE_WORKAROUND + #define NRF52_ERRATA_184_ENABLE_WORKAROUND NRF52_ERRATA_184_PRESENT +#endif + static bool nrf52_errata_184(void) { #ifndef NRF52_SERIES @@ -6865,8 +8832,12 @@ static bool nrf52_errata_184(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -6942,6 +8913,17 @@ static bool nrf52_errata_184(void) #endif } +/* ========= Errata 186 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_186_PRESENT 1 +#else + #define NRF52_ERRATA_186_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_186_ENABLE_WORKAROUND + #define NRF52_ERRATA_186_ENABLE_WORKAROUND NRF52_ERRATA_186_PRESENT +#endif + static bool nrf52_errata_186(void) { #ifndef NRF52_SERIES @@ -6964,6 +8946,10 @@ static bool nrf52_errata_186(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -6973,6 +8959,19 @@ static bool nrf52_errata_186(void) #endif } +/* ========= Errata 187 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_187_PRESENT 1 +#else + #define NRF52_ERRATA_187_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_187_ENABLE_WORKAROUND + #define NRF52_ERRATA_187_ENABLE_WORKAROUND NRF52_ERRATA_187_PRESENT +#endif + static bool nrf52_errata_187(void) { #ifndef NRF52_SERIES @@ -6997,8 +8996,12 @@ static bool nrf52_errata_187(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -7036,6 +9039,17 @@ static bool nrf52_errata_187(void) #endif } +/* ========= Errata 189 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_189_PRESENT 1 +#else + #define NRF52_ERRATA_189_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_189_ENABLE_WORKAROUND + #define NRF52_ERRATA_189_ENABLE_WORKAROUND NRF52_ERRATA_189_PRESENT +#endif + static bool nrf52_errata_189(void) { #ifndef NRF52_SERIES @@ -7058,6 +9072,10 @@ static bool nrf52_errata_189(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -7067,6 +9085,19 @@ static bool nrf52_errata_189(void) #endif } +/* ========= Errata 190 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_190_PRESENT 1 +#else + #define NRF52_ERRATA_190_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_190_ENABLE_WORKAROUND + #define NRF52_ERRATA_190_ENABLE_WORKAROUND NRF52_ERRATA_190_PRESENT +#endif + static bool nrf52_errata_190(void) { #ifndef NRF52_SERIES @@ -7091,8 +9122,12 @@ static bool nrf52_errata_190(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -7130,6 +9165,17 @@ static bool nrf52_errata_190(void) #endif } +/* ========= Errata 191 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_191_PRESENT 1 +#else + #define NRF52_ERRATA_191_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_191_ENABLE_WORKAROUND + #define NRF52_ERRATA_191_ENABLE_WORKAROUND NRF52_ERRATA_191_PRESENT +#endif + static bool nrf52_errata_191(void) { #ifndef NRF52_SERIES @@ -7152,8 +9198,12 @@ static bool nrf52_errata_191(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -7161,6 +9211,20 @@ static bool nrf52_errata_191(void) #endif } +/* ========= Errata 192 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_192_PRESENT 1 +#else + #define NRF52_ERRATA_192_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_192_ENABLE_WORKAROUND + #define NRF52_ERRATA_192_ENABLE_WORKAROUND NRF52_ERRATA_192_PRESENT +#endif + static bool nrf52_errata_192(void) { #ifndef NRF52_SERIES @@ -7218,6 +9282,10 @@ static bool nrf52_errata_192(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -7241,6 +9309,17 @@ static bool nrf52_errata_192(void) #endif } +/* ========= Errata 193 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_193_PRESENT 1 +#else + #define NRF52_ERRATA_193_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_193_ENABLE_WORKAROUND + #define NRF52_ERRATA_193_ENABLE_WORKAROUND NRF52_ERRATA_193_PRESENT +#endif + static bool nrf52_errata_193(void) { #ifndef NRF52_SERIES @@ -7263,8 +9342,12 @@ static bool nrf52_errata_193(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -7272,6 +9355,21 @@ static bool nrf52_errata_193(void) #endif } +/* ========= Errata 194 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_194_PRESENT 1 +#else + #define NRF52_ERRATA_194_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_194_ENABLE_WORKAROUND + #define NRF52_ERRATA_194_ENABLE_WORKAROUND NRF52_ERRATA_194_PRESENT +#endif + static bool nrf52_errata_194(void) { #ifndef NRF52_SERIES @@ -7330,8 +9428,12 @@ static bool nrf52_errata_194(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -7369,6 +9471,17 @@ static bool nrf52_errata_194(void) #endif } +/* ========= Errata 195 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_195_PRESENT 1 +#else + #define NRF52_ERRATA_195_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_195_ENABLE_WORKAROUND + #define NRF52_ERRATA_195_ENABLE_WORKAROUND NRF52_ERRATA_195_PRESENT +#endif + static bool nrf52_errata_195(void) { #ifndef NRF52_SERIES @@ -7391,8 +9504,12 @@ static bool nrf52_errata_195(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -7400,6 +9517,21 @@ static bool nrf52_errata_195(void) #endif } +/* ========= Errata 196 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_196_PRESENT 1 +#else + #define NRF52_ERRATA_196_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_196_ENABLE_WORKAROUND + #define NRF52_ERRATA_196_ENABLE_WORKAROUND NRF52_ERRATA_196_PRESENT +#endif + static bool nrf52_errata_196(void) { #ifndef NRF52_SERIES @@ -7458,8 +9590,12 @@ static bool nrf52_errata_196(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -7497,6 +9633,17 @@ static bool nrf52_errata_196(void) #endif } +/* ========= Errata 197 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_197_PRESENT 1 +#else + #define NRF52_ERRATA_197_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_197_ENABLE_WORKAROUND + #define NRF52_ERRATA_197_ENABLE_WORKAROUND NRF52_ERRATA_197_PRESENT +#endif + static bool nrf52_errata_197(void) { #ifndef NRF52_SERIES @@ -7519,6 +9666,10 @@ static bool nrf52_errata_197(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -7528,6 +9679,17 @@ static bool nrf52_errata_197(void) #endif } +/* ========= Errata 198 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_198_PRESENT 1 +#else + #define NRF52_ERRATA_198_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_198_ENABLE_WORKAROUND + #define NRF52_ERRATA_198_ENABLE_WORKAROUND NRF52_ERRATA_198_PRESENT +#endif + static bool nrf52_errata_198(void) { #ifndef NRF52_SERIES @@ -7550,8 +9712,12 @@ static bool nrf52_errata_198(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -7559,6 +9725,17 @@ static bool nrf52_errata_198(void) #endif } +/* ========= Errata 199 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_199_PRESENT 1 +#else + #define NRF52_ERRATA_199_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_199_ENABLE_WORKAROUND + #define NRF52_ERRATA_199_ENABLE_WORKAROUND NRF52_ERRATA_199_PRESENT +#endif + static bool nrf52_errata_199(void) { #ifndef NRF52_SERIES @@ -7581,8 +9758,12 @@ static bool nrf52_errata_199(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -7590,6 +9771,17 @@ static bool nrf52_errata_199(void) #endif } +/* ========= Errata 200 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_200_PRESENT 1 +#else + #define NRF52_ERRATA_200_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_200_ENABLE_WORKAROUND + #define NRF52_ERRATA_200_ENABLE_WORKAROUND NRF52_ERRATA_200_PRESENT +#endif + static bool nrf52_errata_200(void) { #ifndef NRF52_SERIES @@ -7612,6 +9804,10 @@ static bool nrf52_errata_200(void) return false; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -7621,6 +9817,20 @@ static bool nrf52_errata_200(void) #endif } +/* ========= Errata 201 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_201_PRESENT 1 +#else + #define NRF52_ERRATA_201_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_201_ENABLE_WORKAROUND + #define NRF52_ERRATA_201_ENABLE_WORKAROUND NRF52_ERRATA_201_PRESENT +#endif + static bool nrf52_errata_201(void) { #ifndef NRF52_SERIES @@ -7678,6 +9888,10 @@ static bool nrf52_errata_201(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -7701,6 +9915,17 @@ static bool nrf52_errata_201(void) #endif } +/* ========= Errata 202 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_202_PRESENT 1 +#else + #define NRF52_ERRATA_202_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_202_ENABLE_WORKAROUND + #define NRF52_ERRATA_202_ENABLE_WORKAROUND NRF52_ERRATA_202_PRESENT +#endif + static bool nrf52_errata_202(void) { #ifndef NRF52_SERIES @@ -7723,6 +9948,10 @@ static bool nrf52_errata_202(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -7732,6 +9961,20 @@ static bool nrf52_errata_202(void) #endif } +/* ========= Errata 204 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_204_PRESENT 1 +#else + #define NRF52_ERRATA_204_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_204_ENABLE_WORKAROUND + #define NRF52_ERRATA_204_ENABLE_WORKAROUND NRF52_ERRATA_204_PRESENT +#endif + static bool nrf52_errata_204(void) { #ifndef NRF52_SERIES @@ -7789,8 +10032,12 @@ static bool nrf52_errata_204(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -7812,6 +10059,17 @@ static bool nrf52_errata_204(void) #endif } +/* ========= Errata 208 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_208_PRESENT 1 +#else + #define NRF52_ERRATA_208_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_208_ENABLE_WORKAROUND + #define NRF52_ERRATA_208_ENABLE_WORKAROUND NRF52_ERRATA_208_PRESENT +#endif + static bool nrf52_errata_208(void) { #ifndef NRF52_SERIES @@ -7834,8 +10092,12 @@ static bool nrf52_errata_208(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -7843,6 +10105,17 @@ static bool nrf52_errata_208(void) #endif } +/* ========= Errata 209 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_209_PRESENT 1 +#else + #define NRF52_ERRATA_209_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_209_ENABLE_WORKAROUND + #define NRF52_ERRATA_209_ENABLE_WORKAROUND NRF52_ERRATA_209_PRESENT +#endif + static bool nrf52_errata_209(void) { #ifndef NRF52_SERIES @@ -7865,8 +10138,12 @@ static bool nrf52_errata_209(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -7874,6 +10151,24 @@ static bool nrf52_errata_209(void) #endif } +/* ========= Errata 210 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_210_PRESENT 1 +#else + #define NRF52_ERRATA_210_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_210_ENABLE_WORKAROUND + #define NRF52_ERRATA_210_ENABLE_WORKAROUND NRF52_ERRATA_210_PRESENT +#endif + static bool nrf52_errata_210(void) { #ifndef NRF52_SERIES @@ -7935,8 +10230,12 @@ static bool nrf52_errata_210(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -8012,6 +10311,19 @@ static bool nrf52_errata_210(void) #endif } +/* ========= Errata 211 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_211_PRESENT 1 +#else + #define NRF52_ERRATA_211_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_211_ENABLE_WORKAROUND + #define NRF52_ERRATA_211_ENABLE_WORKAROUND 0 +#endif + static bool nrf52_errata_211(void) { #ifndef NRF52_SERIES @@ -8036,8 +10348,12 @@ static bool nrf52_errata_211(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -8075,6 +10391,24 @@ static bool nrf52_errata_211(void) #endif } +/* ========= Errata 212 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_212_PRESENT 1 +#else + #define NRF52_ERRATA_212_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_212_ENABLE_WORKAROUND + #define NRF52_ERRATA_212_ENABLE_WORKAROUND NRF52_ERRATA_212_PRESENT +#endif + static bool nrf52_errata_212(void) { #ifndef NRF52_SERIES @@ -8136,8 +10470,12 @@ static bool nrf52_errata_212(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -8213,6 +10551,21 @@ static bool nrf52_errata_212(void) #endif } +/* ========= Errata 213 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_213_PRESENT 1 +#else + #define NRF52_ERRATA_213_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_213_ENABLE_WORKAROUND + #define NRF52_ERRATA_213_ENABLE_WORKAROUND NRF52_ERRATA_213_PRESENT +#endif + static bool nrf52_errata_213(void) { #ifndef NRF52_SERIES @@ -8271,8 +10624,12 @@ static bool nrf52_errata_213(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -8306,6 +10663,17 @@ static bool nrf52_errata_213(void) #endif } +/* ========= Errata 214 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_214_PRESENT 1 +#else + #define NRF52_ERRATA_214_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_214_ENABLE_WORKAROUND + #define NRF52_ERRATA_214_ENABLE_WORKAROUND NRF52_ERRATA_214_PRESENT +#endif + static bool nrf52_errata_214(void) { #ifndef NRF52_SERIES @@ -8328,8 +10696,12 @@ static bool nrf52_errata_214(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -8337,6 +10709,17 @@ static bool nrf52_errata_214(void) #endif } +/* ========= Errata 215 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_215_PRESENT 1 +#else + #define NRF52_ERRATA_215_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_215_ENABLE_WORKAROUND + #define NRF52_ERRATA_215_ENABLE_WORKAROUND NRF52_ERRATA_215_PRESENT +#endif + static bool nrf52_errata_215(void) { #ifndef NRF52_SERIES @@ -8359,8 +10742,12 @@ static bool nrf52_errata_215(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -8368,6 +10755,17 @@ static bool nrf52_errata_215(void) #endif } +/* ========= Errata 216 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_216_PRESENT 1 +#else + #define NRF52_ERRATA_216_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_216_ENABLE_WORKAROUND + #define NRF52_ERRATA_216_ENABLE_WORKAROUND NRF52_ERRATA_216_PRESENT +#endif + static bool nrf52_errata_216(void) { #ifndef NRF52_SERIES @@ -8390,8 +10788,12 @@ static bool nrf52_errata_216(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -8399,6 +10801,19 @@ static bool nrf52_errata_216(void) #endif } +/* ========= Errata 217 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + #define NRF52_ERRATA_217_PRESENT 1 +#else + #define NRF52_ERRATA_217_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_217_ENABLE_WORKAROUND + #define NRF52_ERRATA_217_ENABLE_WORKAROUND NRF52_ERRATA_217_PRESENT +#endif + static bool nrf52_errata_217(void) { #ifndef NRF52_SERIES @@ -8452,6 +10867,21 @@ static bool nrf52_errata_217(void) #endif } +/* ========= Errata 218 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_218_PRESENT 1 +#else + #define NRF52_ERRATA_218_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_218_ENABLE_WORKAROUND + #define NRF52_ERRATA_218_ENABLE_WORKAROUND NRF52_ERRATA_218_PRESENT +#endif + static bool nrf52_errata_218(void) { #ifndef NRF52_SERIES @@ -8510,8 +10940,12 @@ static bool nrf52_errata_218(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -8549,6 +10983,24 @@ static bool nrf52_errata_218(void) #endif } +/* ========= Errata 219 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_219_PRESENT 1 +#else + #define NRF52_ERRATA_219_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_219_ENABLE_WORKAROUND + #define NRF52_ERRATA_219_ENABLE_WORKAROUND NRF52_ERRATA_219_PRESENT +#endif + static bool nrf52_errata_219(void) { #ifndef NRF52_SERIES @@ -8610,8 +11062,12 @@ static bool nrf52_errata_219(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -8687,6 +11143,18 @@ static bool nrf52_errata_219(void) #endif } +/* ========= Errata 220 ========= */ +#if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + #define NRF52_ERRATA_220_PRESENT 1 +#else + #define NRF52_ERRATA_220_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_220_ENABLE_WORKAROUND + #define NRF52_ERRATA_220_ENABLE_WORKAROUND NRF52_ERRATA_220_PRESENT +#endif + static bool nrf52_errata_220(void) { #ifndef NRF52_SERIES @@ -8731,6 +11199,18 @@ static bool nrf52_errata_220(void) #endif } +/* ========= Errata 223 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #define NRF52_ERRATA_223_PRESENT 1 +#else + #define NRF52_ERRATA_223_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_223_ENABLE_WORKAROUND + #define NRF52_ERRATA_223_ENABLE_WORKAROUND NRF52_ERRATA_223_PRESENT +#endif + static bool nrf52_errata_223(void) { #ifndef NRF52_SERIES @@ -8775,6 +11255,18 @@ static bool nrf52_errata_223(void) #endif } +/* ========= Errata 225 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #define NRF52_ERRATA_225_PRESENT 1 +#else + #define NRF52_ERRATA_225_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_225_ENABLE_WORKAROUND + #define NRF52_ERRATA_225_ENABLE_WORKAROUND NRF52_ERRATA_225_PRESENT +#endif + static bool nrf52_errata_225(void) { #ifndef NRF52_SERIES @@ -8819,6 +11311,21 @@ static bool nrf52_errata_225(void) #endif } +/* ========= Errata 228 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_228_PRESENT 1 +#else + #define NRF52_ERRATA_228_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_228_ENABLE_WORKAROUND + #define NRF52_ERRATA_228_ENABLE_WORKAROUND NRF52_ERRATA_228_PRESENT +#endif + static bool nrf52_errata_228(void) { #ifndef NRF52_SERIES @@ -8845,8 +11352,12 @@ static bool nrf52_errata_228(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -8910,6 +11421,17 @@ static bool nrf52_errata_228(void) #endif } +/* ========= Errata 230 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + #define NRF52_ERRATA_230_PRESENT 1 +#else + #define NRF52_ERRATA_230_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_230_ENABLE_WORKAROUND + #define NRF52_ERRATA_230_ENABLE_WORKAROUND NRF52_ERRATA_230_PRESENT +#endif + static bool nrf52_errata_230(void) { #ifndef NRF52_SERIES @@ -8939,6 +11461,17 @@ static bool nrf52_errata_230(void) #endif } +/* ========= Errata 231 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + #define NRF52_ERRATA_231_PRESENT 1 +#else + #define NRF52_ERRATA_231_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_231_ENABLE_WORKAROUND + #define NRF52_ERRATA_231_ENABLE_WORKAROUND NRF52_ERRATA_231_PRESENT +#endif + static bool nrf52_errata_231(void) { #ifndef NRF52_SERIES @@ -8968,6 +11501,18 @@ static bool nrf52_errata_231(void) #endif } +/* ========= Errata 232 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + #define NRF52_ERRATA_232_PRESENT 1 +#else + #define NRF52_ERRATA_232_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_232_ENABLE_WORKAROUND + #define NRF52_ERRATA_232_ENABLE_WORKAROUND NRF52_ERRATA_232_PRESENT +#endif + static bool nrf52_errata_232(void) { #ifndef NRF52_SERIES @@ -9008,6 +11553,19 @@ static bool nrf52_errata_232(void) #endif } +/* ========= Errata 233 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_233_PRESENT 1 +#else + #define NRF52_ERRATA_233_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_233_ENABLE_WORKAROUND + #define NRF52_ERRATA_233_ENABLE_WORKAROUND NRF52_ERRATA_233_PRESENT +#endif + static bool nrf52_errata_233(void) { #ifndef NRF52_SERIES @@ -9032,8 +11590,12 @@ static bool nrf52_errata_233(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -9061,9 +11623,9 @@ static bool nrf52_errata_233(void) case 0x01ul: return true; case 0x02ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -9071,6 +11633,21 @@ static bool nrf52_errata_233(void) #endif } +/* ========= Errata 236 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_236_PRESENT 1 +#else + #define NRF52_ERRATA_236_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_236_ENABLE_WORKAROUND + #define NRF52_ERRATA_236_ENABLE_WORKAROUND NRF52_ERRATA_236_PRESENT +#endif + static bool nrf52_errata_236(void) { #ifndef NRF52_SERIES @@ -9097,8 +11674,12 @@ static bool nrf52_errata_236(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -9162,6 +11743,21 @@ static bool nrf52_errata_236(void) #endif } +/* ========= Errata 237 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_237_PRESENT 1 +#else + #define NRF52_ERRATA_237_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_237_ENABLE_WORKAROUND + #define NRF52_ERRATA_237_ENABLE_WORKAROUND NRF52_ERRATA_237_PRESENT +#endif + static bool nrf52_errata_237(void) { #ifndef NRF52_SERIES @@ -9188,8 +11784,12 @@ static bool nrf52_errata_237(void) return true; case 0x03ul: return true; + case 0x04ul: + return false; + case 0x05ul: + return false; default: - return true; + return false; } } #endif @@ -9253,11 +11853,714 @@ static bool nrf52_errata_237(void) #endif } -static bool nrf52_errata_248(void) +/* ========= Errata 242 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_242_PRESENT 1 +#else + #define NRF52_ERRATA_242_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_242_ENABLE_WORKAROUND + #define NRF52_ERRATA_242_ENABLE_WORKAROUND NRF52_ERRATA_242_PRESENT +#endif + +static bool nrf52_errata_242(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 243 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_243_PRESENT 1 +#else + #define NRF52_ERRATA_243_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_243_ENABLE_WORKAROUND + #define NRF52_ERRATA_243_ENABLE_WORKAROUND NRF52_ERRATA_243_PRESENT +#endif + +static bool nrf52_errata_243(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 244 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_244_PRESENT 1 +#else + #define NRF52_ERRATA_244_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_244_ENABLE_WORKAROUND + #define NRF52_ERRATA_244_ENABLE_WORKAROUND NRF52_ERRATA_244_PRESENT +#endif + +static bool nrf52_errata_244(void) { #ifndef NRF52_SERIES return false; #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 245 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_245_PRESENT 1 +#else + #define NRF52_ERRATA_245_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_245_ENABLE_WORKAROUND + #define NRF52_ERRATA_245_ENABLE_WORKAROUND 0 +#endif + +static bool nrf52_errata_245(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 246 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_246_PRESENT 1 +#else + #define NRF52_ERRATA_246_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_246_ENABLE_WORKAROUND + #define NRF52_ERRATA_246_ENABLE_WORKAROUND NRF52_ERRATA_246_PRESENT +#endif + +static bool nrf52_errata_246(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 248 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_248_PRESENT 1 +#else + #define NRF52_ERRATA_248_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_248_ENABLE_WORKAROUND + #define NRF52_ERRATA_248_ENABLE_WORKAROUND NRF52_ERRATA_248_PRESENT +#endif + +static bool nrf52_errata_248(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 249 ========= */ +#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_249_PRESENT 1 +#else + #define NRF52_ERRATA_249_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_249_ENABLE_WORKAROUND + #define NRF52_ERRATA_249_ENABLE_WORKAROUND NRF52_ERRATA_249_PRESENT +#endif + +static bool nrf52_errata_249(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 250 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #define NRF52_ERRATA_250_PRESENT 1 +#else + #define NRF52_ERRATA_250_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_250_ENABLE_WORKAROUND + #define NRF52_ERRATA_250_ENABLE_WORKAROUND NRF52_ERRATA_250_PRESENT +#endif + +static bool nrf52_errata_250(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif return false; #endif } diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_name_change.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_name_change.h index e3e314219..004d8e2fe 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_name_change.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_name_change.h @@ -1,41 +1,32 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52810.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52810.h index 917ac519d..c6bdecabe 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52810.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52810.h @@ -1,41 +1,32 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52833.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52833.h index e364cf552..4c3643636 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52833.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52833.h @@ -1,41 +1,32 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52840.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52840.h index ae43f5baa..d65a26a7f 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52840.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52840.h @@ -1,41 +1,32 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf53_erratas.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf53_erratas.h index 5f16f1473..79d834d46 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf53_erratas.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf53_erratas.h @@ -3,42 +3,33 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. */ @@ -123,16 +114,37 @@ static bool nrf53_errata_91(void) __UNUSED; static bool nrf53_errata_93(void) __UNUSED; static bool nrf53_errata_95(void) __UNUSED; static bool nrf53_errata_97(void) __UNUSED; +static bool nrf53_errata_99(void) __UNUSED; static bool nrf53_errata_103(void) __UNUSED; static bool nrf53_errata_105(void) __UNUSED; static bool nrf53_errata_106(void) __UNUSED; +static bool nrf53_errata_107(void) __UNUSED; static bool nrf53_errata_109(void) __UNUSED; static bool nrf53_errata_110(void) __UNUSED; +static bool nrf53_errata_112(void) __UNUSED; static bool nrf53_errata_113(void) __UNUSED; static bool nrf53_errata_114(void) __UNUSED; static bool nrf53_errata_115(void) __UNUSED; static bool nrf53_errata_116(void) __UNUSED; +static bool nrf53_errata_117(void) __UNUSED; static bool nrf53_errata_119(void) __UNUSED; +static bool nrf53_errata_121(void) __UNUSED; +static bool nrf53_errata_122(void) __UNUSED; + +/* ========= Errata 1 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_1_PRESENT 1 + #else + #define NRF53_ERRATA_1_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_1_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_1_ENABLE_WORKAROUND + #define NRF53_ERRATA_1_ENABLE_WORKAROUND NRF53_ERRATA_1_PRESENT +#endif static bool nrf53_errata_1(void) { @@ -155,6 +167,10 @@ static bool nrf53_errata_1(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -165,6 +181,21 @@ static bool nrf53_errata_1(void) #endif } +/* ========= Errata 2 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_2_PRESENT 1 + #else + #define NRF53_ERRATA_2_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_2_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_2_ENABLE_WORKAROUND + #define NRF53_ERRATA_2_ENABLE_WORKAROUND NRF53_ERRATA_2_PRESENT +#endif + static bool nrf53_errata_2(void) { #ifndef NRF53_SERIES @@ -186,6 +217,10 @@ static bool nrf53_errata_2(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -196,6 +231,21 @@ static bool nrf53_errata_2(void) #endif } +/* ========= Errata 3 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_3_PRESENT 1 + #else + #define NRF53_ERRATA_3_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_3_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_3_ENABLE_WORKAROUND + #define NRF53_ERRATA_3_ENABLE_WORKAROUND NRF53_ERRATA_3_PRESENT +#endif + static bool nrf53_errata_3(void) { #ifndef NRF53_SERIES @@ -217,6 +267,10 @@ static bool nrf53_errata_3(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -227,6 +281,21 @@ static bool nrf53_errata_3(void) #endif } +/* ========= Errata 4 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_4_PRESENT 1 + #else + #define NRF53_ERRATA_4_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_4_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_4_ENABLE_WORKAROUND + #define NRF53_ERRATA_4_ENABLE_WORKAROUND NRF53_ERRATA_4_PRESENT +#endif + static bool nrf53_errata_4(void) { #ifndef NRF53_SERIES @@ -248,6 +317,10 @@ static bool nrf53_errata_4(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -258,6 +331,21 @@ static bool nrf53_errata_4(void) #endif } +/* ========= Errata 5 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_5_PRESENT 1 + #else + #define NRF53_ERRATA_5_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_5_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_5_ENABLE_WORKAROUND + #define NRF53_ERRATA_5_ENABLE_WORKAROUND NRF53_ERRATA_5_PRESENT +#endif + static bool nrf53_errata_5(void) { #ifndef NRF53_SERIES @@ -279,6 +367,10 @@ static bool nrf53_errata_5(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -289,6 +381,21 @@ static bool nrf53_errata_5(void) #endif } +/* ========= Errata 6 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_6_PRESENT 1 + #else + #define NRF53_ERRATA_6_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_6_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_6_ENABLE_WORKAROUND + #define NRF53_ERRATA_6_ENABLE_WORKAROUND NRF53_ERRATA_6_PRESENT +#endif + static bool nrf53_errata_6(void) { #ifndef NRF53_SERIES @@ -309,9 +416,13 @@ static bool nrf53_errata_6(void) case 0x02ul: return true; case 0x03ul: - return false; + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; default: - return false; + return true; } } #endif @@ -320,6 +431,21 @@ static bool nrf53_errata_6(void) #endif } +/* ========= Errata 7 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_7_PRESENT 1 + #else + #define NRF53_ERRATA_7_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_7_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_7_ENABLE_WORKAROUND + #define NRF53_ERRATA_7_ENABLE_WORKAROUND NRF53_ERRATA_7_PRESENT +#endif + static bool nrf53_errata_7(void) { #ifndef NRF53_SERIES @@ -341,6 +467,10 @@ static bool nrf53_errata_7(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -351,6 +481,21 @@ static bool nrf53_errata_7(void) #endif } +/* ========= Errata 8 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_8_PRESENT 1 + #else + #define NRF53_ERRATA_8_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_8_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_8_ENABLE_WORKAROUND + #define NRF53_ERRATA_8_ENABLE_WORKAROUND NRF53_ERRATA_8_PRESENT +#endif + static bool nrf53_errata_8(void) { #ifndef NRF53_SERIES @@ -372,6 +517,10 @@ static bool nrf53_errata_8(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -382,6 +531,21 @@ static bool nrf53_errata_8(void) #endif } +/* ========= Errata 9 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_9_PRESENT 1 + #else + #define NRF53_ERRATA_9_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_9_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_9_ENABLE_WORKAROUND + #define NRF53_ERRATA_9_ENABLE_WORKAROUND NRF53_ERRATA_9_PRESENT +#endif + static bool nrf53_errata_9(void) { #ifndef NRF53_SERIES @@ -403,6 +567,10 @@ static bool nrf53_errata_9(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -413,6 +581,21 @@ static bool nrf53_errata_9(void) #endif } +/* ========= Errata 10 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_10_PRESENT 1 + #else + #define NRF53_ERRATA_10_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_10_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_10_ENABLE_WORKAROUND + #define NRF53_ERRATA_10_ENABLE_WORKAROUND NRF53_ERRATA_10_PRESENT +#endif + static bool nrf53_errata_10(void) { #ifndef NRF53_SERIES @@ -434,6 +617,10 @@ static bool nrf53_errata_10(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -444,6 +631,21 @@ static bool nrf53_errata_10(void) #endif } +/* ========= Errata 11 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_11_PRESENT 1 + #else + #define NRF53_ERRATA_11_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_11_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_11_ENABLE_WORKAROUND + #define NRF53_ERRATA_11_ENABLE_WORKAROUND NRF53_ERRATA_11_PRESENT +#endif + static bool nrf53_errata_11(void) { #ifndef NRF53_SERIES @@ -464,6 +666,10 @@ static bool nrf53_errata_11(void) case 0x02ul: return true; case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: return false; default: return false; @@ -475,6 +681,21 @@ static bool nrf53_errata_11(void) #endif } +/* ========= Errata 12 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_12_PRESENT 1 + #else + #define NRF53_ERRATA_12_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_12_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_12_ENABLE_WORKAROUND + #define NRF53_ERRATA_12_ENABLE_WORKAROUND NRF53_ERRATA_12_PRESENT +#endif + static bool nrf53_errata_12(void) { #ifndef NRF53_SERIES @@ -495,6 +716,10 @@ static bool nrf53_errata_12(void) case 0x02ul: return true; case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: return false; default: return false; @@ -506,6 +731,22 @@ static bool nrf53_errata_12(void) #endif } +/* ========= Errata 13 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_13_PRESENT 1 + #else + #define NRF53_ERRATA_13_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_13_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_13_ENABLE_WORKAROUND + #define NRF53_ERRATA_13_ENABLE_WORKAROUND NRF53_ERRATA_13_PRESENT +#endif + static bool nrf53_errata_13(void) { #ifndef NRF53_SERIES @@ -531,6 +772,10 @@ static bool nrf53_errata_13(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -541,6 +786,21 @@ static bool nrf53_errata_13(void) #endif } +/* ========= Errata 14 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_14_PRESENT 1 + #else + #define NRF53_ERRATA_14_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_14_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_14_ENABLE_WORKAROUND + #define NRF53_ERRATA_14_ENABLE_WORKAROUND NRF53_ERRATA_14_PRESENT +#endif + static bool nrf53_errata_14(void) { #ifndef NRF53_SERIES @@ -562,6 +822,10 @@ static bool nrf53_errata_14(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -572,6 +836,22 @@ static bool nrf53_errata_14(void) #endif } +/* ========= Errata 15 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_15_PRESENT 1 + #else + #define NRF53_ERRATA_15_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_15_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_15_ENABLE_WORKAROUND + #define NRF53_ERRATA_15_ENABLE_WORKAROUND NRF53_ERRATA_15_PRESENT +#endif + static bool nrf53_errata_15(void) { #ifndef NRF53_SERIES @@ -597,6 +877,10 @@ static bool nrf53_errata_15(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -607,6 +891,21 @@ static bool nrf53_errata_15(void) #endif } +/* ========= Errata 16 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_16_PRESENT 1 + #else + #define NRF53_ERRATA_16_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_16_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_16_ENABLE_WORKAROUND + #define NRF53_ERRATA_16_ENABLE_WORKAROUND NRF53_ERRATA_16_PRESENT +#endif + static bool nrf53_errata_16(void) { #ifndef NRF53_SERIES @@ -628,6 +927,10 @@ static bool nrf53_errata_16(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -638,6 +941,21 @@ static bool nrf53_errata_16(void) #endif } +/* ========= Errata 18 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_18_PRESENT 1 + #else + #define NRF53_ERRATA_18_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_18_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_18_ENABLE_WORKAROUND + #define NRF53_ERRATA_18_ENABLE_WORKAROUND NRF53_ERRATA_18_PRESENT +#endif + static bool nrf53_errata_18(void) { #ifndef NRF53_SERIES @@ -659,6 +977,10 @@ static bool nrf53_errata_18(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -669,6 +991,21 @@ static bool nrf53_errata_18(void) #endif } +/* ========= Errata 19 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_19_PRESENT 1 + #else + #define NRF53_ERRATA_19_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_19_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_19_ENABLE_WORKAROUND + #define NRF53_ERRATA_19_ENABLE_WORKAROUND NRF53_ERRATA_19_PRESENT +#endif + static bool nrf53_errata_19(void) { #ifndef NRF53_SERIES @@ -690,6 +1027,10 @@ static bool nrf53_errata_19(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -700,6 +1041,22 @@ static bool nrf53_errata_19(void) #endif } +/* ========= Errata 20 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_20_PRESENT 1 + #else + #define NRF53_ERRATA_20_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_20_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_20_ENABLE_WORKAROUND + #define NRF53_ERRATA_20_ENABLE_WORKAROUND NRF53_ERRATA_20_PRESENT +#endif + static bool nrf53_errata_20(void) { #ifndef NRF53_SERIES @@ -725,6 +1082,10 @@ static bool nrf53_errata_20(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -735,6 +1096,22 @@ static bool nrf53_errata_20(void) #endif } +/* ========= Errata 21 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_21_PRESENT 1 + #else + #define NRF53_ERRATA_21_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_21_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_21_ENABLE_WORKAROUND + #define NRF53_ERRATA_21_ENABLE_WORKAROUND NRF53_ERRATA_21_PRESENT +#endif + static bool nrf53_errata_21(void) { #ifndef NRF53_SERIES @@ -759,6 +1136,10 @@ static bool nrf53_errata_21(void) case 0x02ul: return true; case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: return false; default: return false; @@ -770,6 +1151,21 @@ static bool nrf53_errata_21(void) #endif } +/* ========= Errata 22 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_22_PRESENT 1 + #else + #define NRF53_ERRATA_22_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_22_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_22_ENABLE_WORKAROUND + #define NRF53_ERRATA_22_ENABLE_WORKAROUND NRF53_ERRATA_22_PRESENT +#endif + static bool nrf53_errata_22(void) { #ifndef NRF53_SERIES @@ -791,6 +1187,10 @@ static bool nrf53_errata_22(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -801,6 +1201,21 @@ static bool nrf53_errata_22(void) #endif } +/* ========= Errata 23 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_23_PRESENT 1 + #else + #define NRF53_ERRATA_23_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_23_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_23_ENABLE_WORKAROUND + #define NRF53_ERRATA_23_ENABLE_WORKAROUND NRF53_ERRATA_23_PRESENT +#endif + static bool nrf53_errata_23(void) { #ifndef NRF53_SERIES @@ -822,6 +1237,10 @@ static bool nrf53_errata_23(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -832,6 +1251,22 @@ static bool nrf53_errata_23(void) #endif } +/* ========= Errata 26 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_26_PRESENT 1 + #else + #define NRF53_ERRATA_26_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_26_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_26_ENABLE_WORKAROUND + #define NRF53_ERRATA_26_ENABLE_WORKAROUND NRF53_ERRATA_26_PRESENT +#endif + static bool nrf53_errata_26(void) { #ifndef NRF53_SERIES @@ -857,6 +1292,10 @@ static bool nrf53_errata_26(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -867,6 +1306,22 @@ static bool nrf53_errata_26(void) #endif } +/* ========= Errata 27 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_27_PRESENT 1 + #else + #define NRF53_ERRATA_27_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_27_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_27_ENABLE_WORKAROUND + #define NRF53_ERRATA_27_ENABLE_WORKAROUND NRF53_ERRATA_27_PRESENT +#endif + static bool nrf53_errata_27(void) { #ifndef NRF53_SERIES @@ -892,6 +1347,10 @@ static bool nrf53_errata_27(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -902,6 +1361,22 @@ static bool nrf53_errata_27(void) #endif } +/* ========= Errata 28 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_28_PRESENT 1 + #else + #define NRF53_ERRATA_28_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_28_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_28_ENABLE_WORKAROUND + #define NRF53_ERRATA_28_ENABLE_WORKAROUND NRF53_ERRATA_28_PRESENT +#endif + static bool nrf53_errata_28(void) { #ifndef NRF53_SERIES @@ -927,6 +1402,10 @@ static bool nrf53_errata_28(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -937,6 +1416,21 @@ static bool nrf53_errata_28(void) #endif } +/* ========= Errata 29 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_29_PRESENT 1 + #else + #define NRF53_ERRATA_29_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_29_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_29_ENABLE_WORKAROUND + #define NRF53_ERRATA_29_ENABLE_WORKAROUND NRF53_ERRATA_29_PRESENT +#endif + static bool nrf53_errata_29(void) { #ifndef NRF53_SERIES @@ -958,6 +1452,10 @@ static bool nrf53_errata_29(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -968,6 +1466,21 @@ static bool nrf53_errata_29(void) #endif } +/* ========= Errata 30 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_30_PRESENT 1 + #else + #define NRF53_ERRATA_30_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_30_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_30_ENABLE_WORKAROUND + #define NRF53_ERRATA_30_ENABLE_WORKAROUND NRF53_ERRATA_30_PRESENT +#endif + static bool nrf53_errata_30(void) { #ifndef NRF53_SERIES @@ -989,6 +1502,10 @@ static bool nrf53_errata_30(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -999,6 +1516,22 @@ static bool nrf53_errata_30(void) #endif } +/* ========= Errata 31 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_31_PRESENT 1 + #else + #define NRF53_ERRATA_31_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_31_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_31_ENABLE_WORKAROUND + #define NRF53_ERRATA_31_ENABLE_WORKAROUND NRF53_ERRATA_31_PRESENT +#endif + static bool nrf53_errata_31(void) { #ifndef NRF53_SERIES @@ -1024,6 +1557,10 @@ static bool nrf53_errata_31(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -1034,6 +1571,21 @@ static bool nrf53_errata_31(void) #endif } +/* ========= Errata 32 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_32_PRESENT 1 + #else + #define NRF53_ERRATA_32_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_32_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_32_ENABLE_WORKAROUND + #define NRF53_ERRATA_32_ENABLE_WORKAROUND NRF53_ERRATA_32_PRESENT +#endif + static bool nrf53_errata_32(void) { #ifndef NRF53_SERIES @@ -1055,6 +1607,10 @@ static bool nrf53_errata_32(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -1065,6 +1621,21 @@ static bool nrf53_errata_32(void) #endif } +/* ========= Errata 33 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_33_PRESENT 1 + #else + #define NRF53_ERRATA_33_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_33_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_33_ENABLE_WORKAROUND + #define NRF53_ERRATA_33_ENABLE_WORKAROUND NRF53_ERRATA_33_PRESENT +#endif + static bool nrf53_errata_33(void) { #ifndef NRF53_SERIES @@ -1086,6 +1657,10 @@ static bool nrf53_errata_33(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -1096,6 +1671,21 @@ static bool nrf53_errata_33(void) #endif } +/* ========= Errata 34 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_34_PRESENT 1 + #else + #define NRF53_ERRATA_34_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_34_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_34_ENABLE_WORKAROUND + #define NRF53_ERRATA_34_ENABLE_WORKAROUND NRF53_ERRATA_34_PRESENT +#endif + static bool nrf53_errata_34(void) { #ifndef NRF53_SERIES @@ -1117,6 +1707,10 @@ static bool nrf53_errata_34(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -1127,6 +1721,21 @@ static bool nrf53_errata_34(void) #endif } +/* ========= Errata 36 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_36_PRESENT 1 + #else + #define NRF53_ERRATA_36_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_36_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_36_ENABLE_WORKAROUND + #define NRF53_ERRATA_36_ENABLE_WORKAROUND NRF53_ERRATA_36_PRESENT +#endif + static bool nrf53_errata_36(void) { #ifndef NRF53_SERIES @@ -1148,6 +1757,10 @@ static bool nrf53_errata_36(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -1158,41 +1771,37 @@ static bool nrf53_errata_36(void) #endif } +/* ========= Errata 37 ========= */ +#define NRF53_ERRATA_37_PRESENT 0 + +#ifndef NRF53_ERRATA_37_ENABLE_WORKAROUND + #define NRF53_ERRATA_37_ENABLE_WORKAROUND NRF53_ERRATA_37_PRESENT +#endif + static bool nrf53_errata_37(void) { #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) - #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; - #elif defined(NRF_NETWORK) - uint32_t var1 = *(uint32_t *)0x01FF0130ul; - uint32_t var2 = *(uint32_t *)0x01FF0134ul; - #endif - #endif - #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) - #if defined (NRF_APPLICATION)\ - || defined (NRF_NETWORK) - if (var1 == 0x07) - { - switch(var2) - { - case 0x02ul: - return true; - case 0x03ul: - return false; - default: - return false; - } - } - #endif - #endif return false; #endif } +/* ========= Errata 42 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_42_PRESENT 1 + #else + #define NRF53_ERRATA_42_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_42_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_42_ENABLE_WORKAROUND + #define NRF53_ERRATA_42_ENABLE_WORKAROUND NRF53_ERRATA_42_PRESENT +#endif + static bool nrf53_errata_42(void) { #ifndef NRF53_SERIES @@ -1214,6 +1823,10 @@ static bool nrf53_errata_42(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -1224,6 +1837,21 @@ static bool nrf53_errata_42(void) #endif } +/* ========= Errata 43 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_43_PRESENT 1 + #else + #define NRF53_ERRATA_43_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_43_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_43_ENABLE_WORKAROUND + #define NRF53_ERRATA_43_ENABLE_WORKAROUND NRF53_ERRATA_43_PRESENT +#endif + static bool nrf53_errata_43(void) { #ifndef NRF53_SERIES @@ -1244,9 +1872,13 @@ static bool nrf53_errata_43(void) case 0x02ul: return true; case 0x03ul: - return false; + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; default: - return false; + return true; } } #endif @@ -1255,6 +1887,22 @@ static bool nrf53_errata_43(void) #endif } +/* ========= Errata 44 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_44_PRESENT 1 + #else + #define NRF53_ERRATA_44_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_44_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_44_ENABLE_WORKAROUND + #define NRF53_ERRATA_44_ENABLE_WORKAROUND NRF53_ERRATA_44_PRESENT +#endif + static bool nrf53_errata_44(void) { #ifndef NRF53_SERIES @@ -1279,9 +1927,13 @@ static bool nrf53_errata_44(void) case 0x02ul: return true; case 0x03ul: - return false; + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; default: - return false; + return true; } } #endif @@ -1290,9 +1942,24 @@ static bool nrf53_errata_44(void) #endif } -static bool nrf53_errata_45(void) -{ - #ifndef NRF53_SERIES +/* ========= Errata 45 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_45_PRESENT 1 + #else + #define NRF53_ERRATA_45_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_45_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_45_ENABLE_WORKAROUND + #define NRF53_ERRATA_45_ENABLE_WORKAROUND NRF53_ERRATA_45_PRESENT +#endif + +static bool nrf53_errata_45(void) +{ + #ifndef NRF53_SERIES return false; #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -1311,6 +1978,10 @@ static bool nrf53_errata_45(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -1321,6 +1992,21 @@ static bool nrf53_errata_45(void) #endif } +/* ========= Errata 46 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_46_PRESENT 1 + #else + #define NRF53_ERRATA_46_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_46_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_46_ENABLE_WORKAROUND + #define NRF53_ERRATA_46_ENABLE_WORKAROUND NRF53_ERRATA_46_PRESENT +#endif + static bool nrf53_errata_46(void) { #ifndef NRF53_SERIES @@ -1341,6 +2027,10 @@ static bool nrf53_errata_46(void) case 0x02ul: return true; case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: return false; default: return false; @@ -1352,6 +2042,22 @@ static bool nrf53_errata_46(void) #endif } +/* ========= Errata 47 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_47_PRESENT 1 + #else + #define NRF53_ERRATA_47_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_47_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_47_ENABLE_WORKAROUND + #define NRF53_ERRATA_47_ENABLE_WORKAROUND NRF53_ERRATA_47_PRESENT +#endif + static bool nrf53_errata_47(void) { #ifndef NRF53_SERIES @@ -1376,9 +2082,13 @@ static bool nrf53_errata_47(void) case 0x02ul: return true; case 0x03ul: - return false; + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; default: - return false; + return true; } } #endif @@ -1387,6 +2097,22 @@ static bool nrf53_errata_47(void) #endif } +/* ========= Errata 49 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_49_PRESENT 1 + #else + #define NRF53_ERRATA_49_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_49_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_49_ENABLE_WORKAROUND + #define NRF53_ERRATA_49_ENABLE_WORKAROUND NRF53_ERRATA_49_PRESENT +#endif + static bool nrf53_errata_49(void) { #ifndef NRF53_SERIES @@ -1412,6 +2138,10 @@ static bool nrf53_errata_49(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -1422,6 +2152,21 @@ static bool nrf53_errata_49(void) #endif } +/* ========= Errata 50 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_50_PRESENT 1 + #else + #define NRF53_ERRATA_50_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_50_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_50_ENABLE_WORKAROUND + #define NRF53_ERRATA_50_ENABLE_WORKAROUND NRF53_ERRATA_50_PRESENT +#endif + static bool nrf53_errata_50(void) { #ifndef NRF53_SERIES @@ -1443,6 +2188,10 @@ static bool nrf53_errata_50(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -1453,6 +2202,21 @@ static bool nrf53_errata_50(void) #endif } +/* ========= Errata 51 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_51_PRESENT 1 + #else + #define NRF53_ERRATA_51_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_51_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_51_ENABLE_WORKAROUND + #define NRF53_ERRATA_51_ENABLE_WORKAROUND NRF53_ERRATA_51_PRESENT +#endif + static bool nrf53_errata_51(void) { #ifndef NRF53_SERIES @@ -1474,6 +2238,10 @@ static bool nrf53_errata_51(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -1484,6 +2252,22 @@ static bool nrf53_errata_51(void) #endif } +/* ========= Errata 52 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_52_PRESENT 1 + #else + #define NRF53_ERRATA_52_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_52_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_52_ENABLE_WORKAROUND + #define NRF53_ERRATA_52_ENABLE_WORKAROUND NRF53_ERRATA_52_PRESENT +#endif + static bool nrf53_errata_52(void) { #ifndef NRF53_SERIES @@ -1509,6 +2293,10 @@ static bool nrf53_errata_52(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -1519,6 +2307,21 @@ static bool nrf53_errata_52(void) #endif } +/* ========= Errata 53 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_53_PRESENT 1 + #else + #define NRF53_ERRATA_53_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_53_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_53_ENABLE_WORKAROUND + #define NRF53_ERRATA_53_ENABLE_WORKAROUND NRF53_ERRATA_53_PRESENT +#endif + static bool nrf53_errata_53(void) { #ifndef NRF53_SERIES @@ -1540,6 +2343,10 @@ static bool nrf53_errata_53(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -1550,6 +2357,21 @@ static bool nrf53_errata_53(void) #endif } +/* ========= Errata 54 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_54_PRESENT 1 + #else + #define NRF53_ERRATA_54_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_54_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_54_ENABLE_WORKAROUND + #define NRF53_ERRATA_54_ENABLE_WORKAROUND NRF53_ERRATA_54_PRESENT +#endif + static bool nrf53_errata_54(void) { #ifndef NRF53_SERIES @@ -1571,6 +2393,10 @@ static bool nrf53_errata_54(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -1581,6 +2407,22 @@ static bool nrf53_errata_54(void) #endif } +/* ========= Errata 55 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_55_PRESENT 1 + #else + #define NRF53_ERRATA_55_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_55_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_55_ENABLE_WORKAROUND + #define NRF53_ERRATA_55_ENABLE_WORKAROUND NRF53_ERRATA_55_PRESENT +#endif + static bool nrf53_errata_55(void) { #ifndef NRF53_SERIES @@ -1605,9 +2447,13 @@ static bool nrf53_errata_55(void) case 0x02ul: return true; case 0x03ul: - return false; + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; default: - return false; + return true; } } #endif @@ -1616,6 +2462,21 @@ static bool nrf53_errata_55(void) #endif } +/* ========= Errata 57 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_57_PRESENT 1 + #else + #define NRF53_ERRATA_57_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_57_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_57_ENABLE_WORKAROUND + #define NRF53_ERRATA_57_ENABLE_WORKAROUND NRF53_ERRATA_57_PRESENT +#endif + static bool nrf53_errata_57(void) { #ifndef NRF53_SERIES @@ -1637,6 +2498,10 @@ static bool nrf53_errata_57(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -1647,6 +2512,21 @@ static bool nrf53_errata_57(void) #endif } +/* ========= Errata 58 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_58_PRESENT 1 + #else + #define NRF53_ERRATA_58_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_58_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_58_ENABLE_WORKAROUND + #define NRF53_ERRATA_58_ENABLE_WORKAROUND NRF53_ERRATA_58_PRESENT +#endif + static bool nrf53_errata_58(void) { #ifndef NRF53_SERIES @@ -1668,6 +2548,10 @@ static bool nrf53_errata_58(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -1678,6 +2562,21 @@ static bool nrf53_errata_58(void) #endif } +/* ========= Errata 59 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_59_PRESENT 1 + #else + #define NRF53_ERRATA_59_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_59_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_59_ENABLE_WORKAROUND + #define NRF53_ERRATA_59_ENABLE_WORKAROUND NRF53_ERRATA_59_PRESENT +#endif + static bool nrf53_errata_59(void) { #ifndef NRF53_SERIES @@ -1699,6 +2598,10 @@ static bool nrf53_errata_59(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -1709,6 +2612,22 @@ static bool nrf53_errata_59(void) #endif } +/* ========= Errata 62 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_62_PRESENT 1 + #else + #define NRF53_ERRATA_62_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_62_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_62_ENABLE_WORKAROUND + #define NRF53_ERRATA_62_ENABLE_WORKAROUND NRF53_ERRATA_62_PRESENT +#endif + static bool nrf53_errata_62(void) { #ifndef NRF53_SERIES @@ -1734,6 +2653,10 @@ static bool nrf53_errata_62(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -1744,6 +2667,21 @@ static bool nrf53_errata_62(void) #endif } +/* ========= Errata 64 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_64_PRESENT 1 + #else + #define NRF53_ERRATA_64_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_64_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_64_ENABLE_WORKAROUND + #define NRF53_ERRATA_64_ENABLE_WORKAROUND NRF53_ERRATA_64_PRESENT +#endif + static bool nrf53_errata_64(void) { #ifndef NRF53_SERIES @@ -1753,14 +2691,10 @@ static bool nrf53_errata_64(void) #if defined(NRF_APPLICATION) uint32_t var1 = *(uint32_t *)0x00FF0130ul; uint32_t var2 = *(uint32_t *)0x00FF0134ul; - #elif defined(NRF_NETWORK) - uint32_t var1 = *(uint32_t *)0x01FF0130ul; - uint32_t var2 = *(uint32_t *)0x01FF0134ul; #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) - #if defined (NRF_APPLICATION)\ - || defined (NRF_NETWORK) + #if defined (NRF_APPLICATION) if (var1 == 0x07) { switch(var2) @@ -1769,6 +2703,10 @@ static bool nrf53_errata_64(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -1779,6 +2717,21 @@ static bool nrf53_errata_64(void) #endif } +/* ========= Errata 65 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_65_PRESENT 1 + #else + #define NRF53_ERRATA_65_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_65_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_65_ENABLE_WORKAROUND + #define NRF53_ERRATA_65_ENABLE_WORKAROUND NRF53_ERRATA_65_PRESENT +#endif + static bool nrf53_errata_65(void) { #ifndef NRF53_SERIES @@ -1799,9 +2752,13 @@ static bool nrf53_errata_65(void) case 0x02ul: return true; case 0x03ul: - return false; + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; default: - return false; + return true; } } #endif @@ -1810,6 +2767,21 @@ static bool nrf53_errata_65(void) #endif } +/* ========= Errata 66 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_66_PRESENT 1 + #else + #define NRF53_ERRATA_66_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_66_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_66_ENABLE_WORKAROUND + #define NRF53_ERRATA_66_ENABLE_WORKAROUND NRF53_ERRATA_66_PRESENT +#endif + static bool nrf53_errata_66(void) { #ifndef NRF53_SERIES @@ -1831,6 +2803,10 @@ static bool nrf53_errata_66(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -1841,6 +2817,22 @@ static bool nrf53_errata_66(void) #endif } +/* ========= Errata 67 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_67_PRESENT 1 + #else + #define NRF53_ERRATA_67_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_67_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_67_ENABLE_WORKAROUND + #define NRF53_ERRATA_67_ENABLE_WORKAROUND NRF53_ERRATA_67_PRESENT +#endif + static bool nrf53_errata_67(void) { #ifndef NRF53_SERIES @@ -1865,6 +2857,10 @@ static bool nrf53_errata_67(void) case 0x02ul: return true; case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: return false; default: return false; @@ -1876,6 +2872,21 @@ static bool nrf53_errata_67(void) #endif } +/* ========= Errata 69 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_69_PRESENT 1 + #else + #define NRF53_ERRATA_69_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_69_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_69_ENABLE_WORKAROUND + #define NRF53_ERRATA_69_ENABLE_WORKAROUND NRF53_ERRATA_69_PRESENT +#endif + static bool nrf53_errata_69(void) { #ifndef NRF53_SERIES @@ -1897,6 +2908,10 @@ static bool nrf53_errata_69(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -1907,6 +2922,21 @@ static bool nrf53_errata_69(void) #endif } +/* ========= Errata 70 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_70_PRESENT 1 + #else + #define NRF53_ERRATA_70_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_70_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_70_ENABLE_WORKAROUND + #define NRF53_ERRATA_70_ENABLE_WORKAROUND NRF53_ERRATA_70_PRESENT +#endif + static bool nrf53_errata_70(void) { #ifndef NRF53_SERIES @@ -1927,9 +2957,13 @@ static bool nrf53_errata_70(void) case 0x02ul: return true; case 0x03ul: - return false; + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; default: - return false; + return true; } } #endif @@ -1938,6 +2972,21 @@ static bool nrf53_errata_70(void) #endif } +/* ========= Errata 71 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_71_PRESENT 1 + #else + #define NRF53_ERRATA_71_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_71_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_71_ENABLE_WORKAROUND + #define NRF53_ERRATA_71_ENABLE_WORKAROUND NRF53_ERRATA_71_PRESENT +#endif + static bool nrf53_errata_71(void) { #ifndef NRF53_SERIES @@ -1958,9 +3007,13 @@ static bool nrf53_errata_71(void) case 0x02ul: return true; case 0x03ul: - return false; + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; default: - return false; + return true; } } #endif @@ -1969,6 +3022,21 @@ static bool nrf53_errata_71(void) #endif } +/* ========= Errata 72 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_72_PRESENT 1 + #else + #define NRF53_ERRATA_72_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_72_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_72_ENABLE_WORKAROUND + #define NRF53_ERRATA_72_ENABLE_WORKAROUND NRF53_ERRATA_72_PRESENT +#endif + static bool nrf53_errata_72(void) { #ifndef NRF53_SERIES @@ -1990,6 +3058,10 @@ static bool nrf53_errata_72(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2000,6 +3072,22 @@ static bool nrf53_errata_72(void) #endif } +/* ========= Errata 73 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_73_PRESENT 1 + #else + #define NRF53_ERRATA_73_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_73_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_73_ENABLE_WORKAROUND + #define NRF53_ERRATA_73_ENABLE_WORKAROUND NRF53_ERRATA_73_PRESENT +#endif + static bool nrf53_errata_73(void) { #ifndef NRF53_SERIES @@ -2025,6 +3113,10 @@ static bool nrf53_errata_73(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2035,6 +3127,22 @@ static bool nrf53_errata_73(void) #endif } +/* ========= Errata 74 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_74_PRESENT 1 + #else + #define NRF53_ERRATA_74_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_74_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_74_ENABLE_WORKAROUND + #define NRF53_ERRATA_74_ENABLE_WORKAROUND NRF53_ERRATA_74_PRESENT +#endif + static bool nrf53_errata_74(void) { #ifndef NRF53_SERIES @@ -2060,6 +3168,10 @@ static bool nrf53_errata_74(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2070,6 +3182,21 @@ static bool nrf53_errata_74(void) #endif } +/* ========= Errata 75 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_75_PRESENT 1 + #else + #define NRF53_ERRATA_75_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_75_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_75_ENABLE_WORKAROUND + #define NRF53_ERRATA_75_ENABLE_WORKAROUND NRF53_ERRATA_75_PRESENT +#endif + static bool nrf53_errata_75(void) { #ifndef NRF53_SERIES @@ -2090,9 +3217,13 @@ static bool nrf53_errata_75(void) case 0x02ul: return true; case 0x03ul: - return false; + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; default: - return false; + return true; } } #endif @@ -2101,6 +3232,21 @@ static bool nrf53_errata_75(void) #endif } +/* ========= Errata 76 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_76_PRESENT 1 + #else + #define NRF53_ERRATA_76_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_76_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_76_ENABLE_WORKAROUND + #define NRF53_ERRATA_76_ENABLE_WORKAROUND NRF53_ERRATA_76_PRESENT +#endif + static bool nrf53_errata_76(void) { #ifndef NRF53_SERIES @@ -2121,9 +3267,13 @@ static bool nrf53_errata_76(void) case 0x02ul: return true; case 0x03ul: - return false; + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; default: - return false; + return true; } } #endif @@ -2132,6 +3282,22 @@ static bool nrf53_errata_76(void) #endif } +/* ========= Errata 77 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_77_PRESENT 1 + #else + #define NRF53_ERRATA_77_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_77_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_77_ENABLE_WORKAROUND + #define NRF53_ERRATA_77_ENABLE_WORKAROUND NRF53_ERRATA_77_PRESENT +#endif + static bool nrf53_errata_77(void) { #ifndef NRF53_SERIES @@ -2157,6 +3323,10 @@ static bool nrf53_errata_77(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2167,6 +3337,21 @@ static bool nrf53_errata_77(void) #endif } +/* ========= Errata 79 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_79_PRESENT 1 + #else + #define NRF53_ERRATA_79_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_79_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_79_ENABLE_WORKAROUND + #define NRF53_ERRATA_79_ENABLE_WORKAROUND NRF53_ERRATA_79_PRESENT +#endif + static bool nrf53_errata_79(void) { #ifndef NRF53_SERIES @@ -2188,6 +3373,10 @@ static bool nrf53_errata_79(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2198,6 +3387,21 @@ static bool nrf53_errata_79(void) #endif } +/* ========= Errata 80 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_80_PRESENT 1 + #else + #define NRF53_ERRATA_80_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_80_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_80_ENABLE_WORKAROUND + #define NRF53_ERRATA_80_ENABLE_WORKAROUND NRF53_ERRATA_80_PRESENT +#endif + static bool nrf53_errata_80(void) { #ifndef NRF53_SERIES @@ -2219,6 +3423,10 @@ static bool nrf53_errata_80(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2229,6 +3437,21 @@ static bool nrf53_errata_80(void) #endif } +/* ========= Errata 81 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_81_PRESENT 1 + #else + #define NRF53_ERRATA_81_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_81_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_81_ENABLE_WORKAROUND + #define NRF53_ERRATA_81_ENABLE_WORKAROUND NRF53_ERRATA_81_PRESENT +#endif + static bool nrf53_errata_81(void) { #ifndef NRF53_SERIES @@ -2250,6 +3473,10 @@ static bool nrf53_errata_81(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2260,6 +3487,21 @@ static bool nrf53_errata_81(void) #endif } +/* ========= Errata 82 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_82_PRESENT 1 + #else + #define NRF53_ERRATA_82_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_82_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_82_ENABLE_WORKAROUND + #define NRF53_ERRATA_82_ENABLE_WORKAROUND NRF53_ERRATA_82_PRESENT +#endif + static bool nrf53_errata_82(void) { #ifndef NRF53_SERIES @@ -2281,6 +3523,10 @@ static bool nrf53_errata_82(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2291,6 +3537,21 @@ static bool nrf53_errata_82(void) #endif } +/* ========= Errata 83 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_83_PRESENT 1 + #else + #define NRF53_ERRATA_83_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_83_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_83_ENABLE_WORKAROUND + #define NRF53_ERRATA_83_ENABLE_WORKAROUND NRF53_ERRATA_83_PRESENT +#endif + static bool nrf53_errata_83(void) { #ifndef NRF53_SERIES @@ -2312,6 +3573,10 @@ static bool nrf53_errata_83(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2322,6 +3587,21 @@ static bool nrf53_errata_83(void) #endif } +/* ========= Errata 84 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_84_PRESENT 1 + #else + #define NRF53_ERRATA_84_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_84_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_84_ENABLE_WORKAROUND + #define NRF53_ERRATA_84_ENABLE_WORKAROUND NRF53_ERRATA_84_PRESENT +#endif + static bool nrf53_errata_84(void) { #ifndef NRF53_SERIES @@ -2343,6 +3623,10 @@ static bool nrf53_errata_84(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2353,6 +3637,21 @@ static bool nrf53_errata_84(void) #endif } +/* ========= Errata 85 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_85_PRESENT 1 + #else + #define NRF53_ERRATA_85_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_85_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_85_ENABLE_WORKAROUND + #define NRF53_ERRATA_85_ENABLE_WORKAROUND NRF53_ERRATA_85_PRESENT +#endif + static bool nrf53_errata_85(void) { #ifndef NRF53_SERIES @@ -2374,6 +3673,10 @@ static bool nrf53_errata_85(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2384,6 +3687,22 @@ static bool nrf53_errata_85(void) #endif } +/* ========= Errata 86 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_86_PRESENT 1 + #else + #define NRF53_ERRATA_86_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_86_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_86_ENABLE_WORKAROUND + #define NRF53_ERRATA_86_ENABLE_WORKAROUND NRF53_ERRATA_86_PRESENT +#endif + static bool nrf53_errata_86(void) { #ifndef NRF53_SERIES @@ -2409,6 +3728,10 @@ static bool nrf53_errata_86(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2419,6 +3742,21 @@ static bool nrf53_errata_86(void) #endif } +/* ========= Errata 87 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_87_PRESENT 1 + #else + #define NRF53_ERRATA_87_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_87_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_87_ENABLE_WORKAROUND + #define NRF53_ERRATA_87_ENABLE_WORKAROUND NRF53_ERRATA_87_PRESENT +#endif + static bool nrf53_errata_87(void) { #ifndef NRF53_SERIES @@ -2439,9 +3777,13 @@ static bool nrf53_errata_87(void) case 0x02ul: return true; case 0x03ul: - return false; + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; default: - return false; + return true; } } #endif @@ -2450,6 +3792,21 @@ static bool nrf53_errata_87(void) #endif } +/* ========= Errata 90 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_90_PRESENT 1 + #else + #define NRF53_ERRATA_90_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_90_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_90_ENABLE_WORKAROUND + #define NRF53_ERRATA_90_ENABLE_WORKAROUND NRF53_ERRATA_90_PRESENT +#endif + static bool nrf53_errata_90(void) { #ifndef NRF53_SERIES @@ -2471,6 +3828,10 @@ static bool nrf53_errata_90(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2481,6 +3842,21 @@ static bool nrf53_errata_90(void) #endif } +/* ========= Errata 91 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_91_PRESENT 1 + #else + #define NRF53_ERRATA_91_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_91_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_91_ENABLE_WORKAROUND + #define NRF53_ERRATA_91_ENABLE_WORKAROUND NRF53_ERRATA_91_PRESENT +#endif + static bool nrf53_errata_91(void) { #ifndef NRF53_SERIES @@ -2502,6 +3878,10 @@ static bool nrf53_errata_91(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2512,6 +3892,21 @@ static bool nrf53_errata_91(void) #endif } +/* ========= Errata 93 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_93_PRESENT 1 + #else + #define NRF53_ERRATA_93_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_93_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_93_ENABLE_WORKAROUND + #define NRF53_ERRATA_93_ENABLE_WORKAROUND NRF53_ERRATA_93_PRESENT +#endif + static bool nrf53_errata_93(void) { #ifndef NRF53_SERIES @@ -2533,6 +3928,10 @@ static bool nrf53_errata_93(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2543,6 +3942,21 @@ static bool nrf53_errata_93(void) #endif } +/* ========= Errata 95 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_95_PRESENT 1 + #else + #define NRF53_ERRATA_95_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_95_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_95_ENABLE_WORKAROUND + #define NRF53_ERRATA_95_ENABLE_WORKAROUND NRF53_ERRATA_95_PRESENT +#endif + static bool nrf53_errata_95(void) { #ifndef NRF53_SERIES @@ -2564,6 +3978,10 @@ static bool nrf53_errata_95(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2574,6 +3992,22 @@ static bool nrf53_errata_95(void) #endif } +/* ========= Errata 97 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_97_PRESENT 1 + #else + #define NRF53_ERRATA_97_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_97_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_97_ENABLE_WORKAROUND + #define NRF53_ERRATA_97_ENABLE_WORKAROUND NRF53_ERRATA_97_PRESENT +#endif + static bool nrf53_errata_97(void) { #ifndef NRF53_SERIES @@ -2599,6 +4033,10 @@ static bool nrf53_errata_97(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2609,19 +4047,100 @@ static bool nrf53_errata_97(void) #endif } +/* ========= Errata 99 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_99_PRESENT 1 + #else + #define NRF53_ERRATA_99_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_99_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_99_ENABLE_WORKAROUND + #define NRF53_ERRATA_99_ENABLE_WORKAROUND NRF53_ERRATA_99_PRESENT +#endif + +static bool nrf53_errata_99(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 103 ========= */ +#define NRF53_ERRATA_103_PRESENT 0 + +#ifndef NRF53_ERRATA_103_ENABLE_WORKAROUND + #define NRF53_ERRATA_103_ENABLE_WORKAROUND NRF53_ERRATA_103_PRESENT +#endif + static bool nrf53_errata_103(void) +{ + #ifndef NRF53_SERIES + return false; + #else + return false; + #endif +} + +/* ========= Errata 105 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_105_PRESENT 1 + #else + #define NRF53_ERRATA_105_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_105_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_105_ENABLE_WORKAROUND + #define NRF53_ERRATA_105_ENABLE_WORKAROUND NRF53_ERRATA_105_PRESENT +#endif + +static bool nrf53_errata_105(void) { #ifndef NRF53_SERIES return false; #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) - #if defined(NRF_NETWORK) - uint32_t var1 = *(uint32_t *)0x01FF0130ul; - uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) - #if defined (NRF_NETWORK) + #if defined (NRF_APPLICATION) if (var1 == 0x07) { switch(var2) @@ -2630,6 +4149,10 @@ static bool nrf53_errata_103(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2640,7 +4163,22 @@ static bool nrf53_errata_103(void) #endif } -static bool nrf53_errata_105(void) +/* ========= Errata 106 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_106_PRESENT 1 + #else + #define NRF53_ERRATA_106_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_106_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_106_ENABLE_WORKAROUND + #define NRF53_ERRATA_106_ENABLE_WORKAROUND NRF53_ERRATA_106_PRESENT +#endif + +static bool nrf53_errata_106(void) { #ifndef NRF53_SERIES return false; @@ -2661,6 +4199,10 @@ static bool nrf53_errata_105(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2671,7 +4213,22 @@ static bool nrf53_errata_105(void) #endif } -static bool nrf53_errata_106(void) +/* ========= Errata 107 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_107_PRESENT 1 + #else + #define NRF53_ERRATA_107_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_107_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_107_ENABLE_WORKAROUND + #define NRF53_ERRATA_107_ENABLE_WORKAROUND NRF53_ERRATA_107_PRESENT +#endif + +static bool nrf53_errata_107(void) { #ifndef NRF53_SERIES return false; @@ -2689,8 +4246,12 @@ static bool nrf53_errata_106(void) switch(var2) { case 0x02ul: - return true; + return false; case 0x03ul: + return true; + case 0x04ul: + return false; + case 0x05ul: return false; default: return false; @@ -2702,6 +4263,21 @@ static bool nrf53_errata_106(void) #endif } +/* ========= Errata 109 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_109_PRESENT 1 + #else + #define NRF53_ERRATA_109_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_109_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_109_ENABLE_WORKAROUND + #define NRF53_ERRATA_109_ENABLE_WORKAROUND NRF53_ERRATA_109_PRESENT +#endif + static bool nrf53_errata_109(void) { #ifndef NRF53_SERIES @@ -2723,6 +4299,10 @@ static bool nrf53_errata_109(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2733,6 +4313,21 @@ static bool nrf53_errata_109(void) #endif } +/* ========= Errata 110 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_110_PRESENT 1 + #else + #define NRF53_ERRATA_110_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_110_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_110_ENABLE_WORKAROUND + #define NRF53_ERRATA_110_ENABLE_WORKAROUND NRF53_ERRATA_110_PRESENT +#endif + static bool nrf53_errata_110(void) { #ifndef NRF53_SERIES @@ -2754,6 +4349,10 @@ static bool nrf53_errata_110(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2764,6 +4363,71 @@ static bool nrf53_errata_110(void) #endif } +/* ========= Errata 112 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_112_PRESENT 1 + #else + #define NRF53_ERRATA_112_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_112_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_112_ENABLE_WORKAROUND + #define NRF53_ERRATA_112_ENABLE_WORKAROUND NRF53_ERRATA_112_PRESENT +#endif + +static bool nrf53_errata_112(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 113 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_113_PRESENT 1 + #else + #define NRF53_ERRATA_113_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_113_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_113_ENABLE_WORKAROUND + #define NRF53_ERRATA_113_ENABLE_WORKAROUND NRF53_ERRATA_113_PRESENT +#endif + static bool nrf53_errata_113(void) { #ifndef NRF53_SERIES @@ -2784,9 +4448,13 @@ static bool nrf53_errata_113(void) case 0x02ul: return true; case 0x03ul: - return false; + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; default: - return false; + return true; } } #endif @@ -2795,6 +4463,21 @@ static bool nrf53_errata_113(void) #endif } +/* ========= Errata 114 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_114_PRESENT 1 + #else + #define NRF53_ERRATA_114_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_114_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_114_ENABLE_WORKAROUND + #define NRF53_ERRATA_114_ENABLE_WORKAROUND NRF53_ERRATA_114_PRESENT +#endif + static bool nrf53_errata_114(void) { #ifndef NRF53_SERIES @@ -2816,6 +4499,10 @@ static bool nrf53_errata_114(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2826,6 +4513,21 @@ static bool nrf53_errata_114(void) #endif } +/* ========= Errata 115 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_115_PRESENT 1 + #else + #define NRF53_ERRATA_115_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_115_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_115_ENABLE_WORKAROUND + #define NRF53_ERRATA_115_ENABLE_WORKAROUND NRF53_ERRATA_115_PRESENT +#endif + static bool nrf53_errata_115(void) { #ifndef NRF53_SERIES @@ -2847,6 +4549,10 @@ static bool nrf53_errata_115(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2857,6 +4563,21 @@ static bool nrf53_errata_115(void) #endif } +/* ========= Errata 116 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_116_PRESENT 1 + #else + #define NRF53_ERRATA_116_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_116_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_116_ENABLE_WORKAROUND + #define NRF53_ERRATA_116_ENABLE_WORKAROUND NRF53_ERRATA_116_PRESENT +#endif + static bool nrf53_errata_116(void) { #ifndef NRF53_SERIES @@ -2878,6 +4599,10 @@ static bool nrf53_errata_116(void) return true; case 0x03ul: return false; + case 0x04ul: + return false; + case 0x05ul: + return false; default: return false; } @@ -2888,6 +4613,71 @@ static bool nrf53_errata_116(void) #endif } +/* ========= Errata 117 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_117_PRESENT 1 + #else + #define NRF53_ERRATA_117_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_117_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_117_ENABLE_WORKAROUND + #define NRF53_ERRATA_117_ENABLE_WORKAROUND NRF53_ERRATA_117_PRESENT +#endif + +static bool nrf53_errata_117(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 119 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_119_PRESENT 1 + #else + #define NRF53_ERRATA_119_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_119_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_119_ENABLE_WORKAROUND + #define NRF53_ERRATA_119_ENABLE_WORKAROUND NRF53_ERRATA_119_PRESENT +#endif + static bool nrf53_errata_119(void) { #ifndef NRF53_SERIES @@ -2908,9 +4698,113 @@ static bool nrf53_errata_119(void) case 0x02ul: return true; case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 121 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #define NRF53_ERRATA_121_PRESENT 1 + #else + #define NRF53_ERRATA_121_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_121_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_121_ENABLE_WORKAROUND + #define NRF53_ERRATA_121_ENABLE_WORKAROUND NRF53_ERRATA_121_PRESENT +#endif + +static bool nrf53_errata_121(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: return false; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 122 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_122_PRESENT 1 + #else + #define NRF53_ERRATA_122_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_122_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_122_ENABLE_WORKAROUND + #define NRF53_ERRATA_122_ENABLE_WORKAROUND NRF53_ERRATA_122_PRESENT +#endif + +static bool nrf53_errata_122(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; } } #endif diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf91_erratas.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf91_erratas.h index 269bb0391..074b126c9 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf91_erratas.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf91_erratas.h @@ -3,42 +3,33 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. */ @@ -72,6 +63,17 @@ static bool nrf91_errata_31(void) __UNUSED; static bool nrf91_errata_32(void) __UNUSED; static bool nrf91_errata_33(void) __UNUSED; +/* ========= Errata 1 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_1_PRESENT 1 +#else + #define NRF91_ERRATA_1_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_1_ENABLE_WORKAROUND + #define NRF91_ERRATA_1_ENABLE_WORKAROUND NRF91_ERRATA_1_PRESENT +#endif + static bool nrf91_errata_1(void) { #ifndef NRF91_SERIES @@ -99,6 +101,17 @@ static bool nrf91_errata_1(void) #endif } +/* ========= Errata 2 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_2_PRESENT 1 +#else + #define NRF91_ERRATA_2_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_2_ENABLE_WORKAROUND + #define NRF91_ERRATA_2_ENABLE_WORKAROUND NRF91_ERRATA_2_PRESENT +#endif + static bool nrf91_errata_2(void) { #ifndef NRF91_SERIES @@ -126,6 +139,17 @@ static bool nrf91_errata_2(void) #endif } +/* ========= Errata 4 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_4_PRESENT 1 +#else + #define NRF91_ERRATA_4_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_4_ENABLE_WORKAROUND + #define NRF91_ERRATA_4_ENABLE_WORKAROUND NRF91_ERRATA_4_PRESENT +#endif + static bool nrf91_errata_4(void) { #ifndef NRF91_SERIES @@ -153,6 +177,17 @@ static bool nrf91_errata_4(void) #endif } +/* ========= Errata 6 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_6_PRESENT 1 +#else + #define NRF91_ERRATA_6_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_6_ENABLE_WORKAROUND + #define NRF91_ERRATA_6_ENABLE_WORKAROUND NRF91_ERRATA_6_PRESENT +#endif + static bool nrf91_errata_6(void) { #ifndef NRF91_SERIES @@ -180,6 +215,17 @@ static bool nrf91_errata_6(void) #endif } +/* ========= Errata 7 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_7_PRESENT 1 +#else + #define NRF91_ERRATA_7_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_7_ENABLE_WORKAROUND + #define NRF91_ERRATA_7_ENABLE_WORKAROUND NRF91_ERRATA_7_PRESENT +#endif + static bool nrf91_errata_7(void) { #ifndef NRF91_SERIES @@ -207,6 +253,17 @@ static bool nrf91_errata_7(void) #endif } +/* ========= Errata 8 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_8_PRESENT 1 +#else + #define NRF91_ERRATA_8_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_8_ENABLE_WORKAROUND + #define NRF91_ERRATA_8_ENABLE_WORKAROUND NRF91_ERRATA_8_PRESENT +#endif + static bool nrf91_errata_8(void) { #ifndef NRF91_SERIES @@ -234,6 +291,17 @@ static bool nrf91_errata_8(void) #endif } +/* ========= Errata 9 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_9_PRESENT 1 +#else + #define NRF91_ERRATA_9_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_9_ENABLE_WORKAROUND + #define NRF91_ERRATA_9_ENABLE_WORKAROUND NRF91_ERRATA_9_PRESENT +#endif + static bool nrf91_errata_9(void) { #ifndef NRF91_SERIES @@ -261,6 +329,17 @@ static bool nrf91_errata_9(void) #endif } +/* ========= Errata 10 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_10_PRESENT 1 +#else + #define NRF91_ERRATA_10_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_10_ENABLE_WORKAROUND + #define NRF91_ERRATA_10_ENABLE_WORKAROUND NRF91_ERRATA_10_PRESENT +#endif + static bool nrf91_errata_10(void) { #ifndef NRF91_SERIES @@ -288,6 +367,17 @@ static bool nrf91_errata_10(void) #endif } +/* ========= Errata 12 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_12_PRESENT 1 +#else + #define NRF91_ERRATA_12_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_12_ENABLE_WORKAROUND + #define NRF91_ERRATA_12_ENABLE_WORKAROUND NRF91_ERRATA_12_PRESENT +#endif + static bool nrf91_errata_12(void) { #ifndef NRF91_SERIES @@ -315,6 +405,17 @@ static bool nrf91_errata_12(void) #endif } +/* ========= Errata 14 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_14_PRESENT 1 +#else + #define NRF91_ERRATA_14_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_14_ENABLE_WORKAROUND + #define NRF91_ERRATA_14_ENABLE_WORKAROUND NRF91_ERRATA_14_PRESENT +#endif + static bool nrf91_errata_14(void) { #ifndef NRF91_SERIES @@ -342,6 +443,17 @@ static bool nrf91_errata_14(void) #endif } +/* ========= Errata 15 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_15_PRESENT 1 +#else + #define NRF91_ERRATA_15_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_15_ENABLE_WORKAROUND + #define NRF91_ERRATA_15_ENABLE_WORKAROUND NRF91_ERRATA_15_PRESENT +#endif + static bool nrf91_errata_15(void) { #ifndef NRF91_SERIES @@ -369,6 +481,17 @@ static bool nrf91_errata_15(void) #endif } +/* ========= Errata 16 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_16_PRESENT 1 +#else + #define NRF91_ERRATA_16_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_16_ENABLE_WORKAROUND + #define NRF91_ERRATA_16_ENABLE_WORKAROUND NRF91_ERRATA_16_PRESENT +#endif + static bool nrf91_errata_16(void) { #ifndef NRF91_SERIES @@ -396,6 +519,17 @@ static bool nrf91_errata_16(void) #endif } +/* ========= Errata 17 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_17_PRESENT 1 +#else + #define NRF91_ERRATA_17_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_17_ENABLE_WORKAROUND + #define NRF91_ERRATA_17_ENABLE_WORKAROUND NRF91_ERRATA_17_PRESENT +#endif + static bool nrf91_errata_17(void) { #ifndef NRF91_SERIES @@ -423,6 +557,17 @@ static bool nrf91_errata_17(void) #endif } +/* ========= Errata 20 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_20_PRESENT 1 +#else + #define NRF91_ERRATA_20_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_20_ENABLE_WORKAROUND + #define NRF91_ERRATA_20_ENABLE_WORKAROUND NRF91_ERRATA_20_PRESENT +#endif + static bool nrf91_errata_20(void) { #ifndef NRF91_SERIES @@ -450,6 +595,17 @@ static bool nrf91_errata_20(void) #endif } +/* ========= Errata 21 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_21_PRESENT 1 +#else + #define NRF91_ERRATA_21_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_21_ENABLE_WORKAROUND + #define NRF91_ERRATA_21_ENABLE_WORKAROUND NRF91_ERRATA_21_PRESENT +#endif + static bool nrf91_errata_21(void) { #ifndef NRF91_SERIES @@ -477,6 +633,17 @@ static bool nrf91_errata_21(void) #endif } +/* ========= Errata 23 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_23_PRESENT 1 +#else + #define NRF91_ERRATA_23_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_23_ENABLE_WORKAROUND + #define NRF91_ERRATA_23_ENABLE_WORKAROUND NRF91_ERRATA_23_PRESENT +#endif + static bool nrf91_errata_23(void) { #ifndef NRF91_SERIES @@ -504,6 +671,17 @@ static bool nrf91_errata_23(void) #endif } +/* ========= Errata 24 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_24_PRESENT 1 +#else + #define NRF91_ERRATA_24_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_24_ENABLE_WORKAROUND + #define NRF91_ERRATA_24_ENABLE_WORKAROUND NRF91_ERRATA_24_PRESENT +#endif + static bool nrf91_errata_24(void) { #ifndef NRF91_SERIES @@ -531,6 +709,17 @@ static bool nrf91_errata_24(void) #endif } +/* ========= Errata 26 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_26_PRESENT 1 +#else + #define NRF91_ERRATA_26_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_26_ENABLE_WORKAROUND + #define NRF91_ERRATA_26_ENABLE_WORKAROUND NRF91_ERRATA_26_PRESENT +#endif + static bool nrf91_errata_26(void) { #ifndef NRF91_SERIES @@ -558,6 +747,17 @@ static bool nrf91_errata_26(void) #endif } +/* ========= Errata 27 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_27_PRESENT 1 +#else + #define NRF91_ERRATA_27_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_27_ENABLE_WORKAROUND + #define NRF91_ERRATA_27_ENABLE_WORKAROUND NRF91_ERRATA_27_PRESENT +#endif + static bool nrf91_errata_27(void) { #ifndef NRF91_SERIES @@ -585,6 +785,17 @@ static bool nrf91_errata_27(void) #endif } +/* ========= Errata 28 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_28_PRESENT 1 +#else + #define NRF91_ERRATA_28_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_28_ENABLE_WORKAROUND + #define NRF91_ERRATA_28_ENABLE_WORKAROUND NRF91_ERRATA_28_PRESENT +#endif + static bool nrf91_errata_28(void) { #ifndef NRF91_SERIES @@ -612,6 +823,17 @@ static bool nrf91_errata_28(void) #endif } +/* ========= Errata 29 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_29_PRESENT 1 +#else + #define NRF91_ERRATA_29_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_29_ENABLE_WORKAROUND + #define NRF91_ERRATA_29_ENABLE_WORKAROUND NRF91_ERRATA_29_PRESENT +#endif + static bool nrf91_errata_29(void) { #ifndef NRF91_SERIES @@ -639,6 +861,17 @@ static bool nrf91_errata_29(void) #endif } +/* ========= Errata 30 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_30_PRESENT 1 +#else + #define NRF91_ERRATA_30_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_30_ENABLE_WORKAROUND + #define NRF91_ERRATA_30_ENABLE_WORKAROUND NRF91_ERRATA_30_PRESENT +#endif + static bool nrf91_errata_30(void) { #ifndef NRF91_SERIES @@ -666,6 +899,17 @@ static bool nrf91_errata_30(void) #endif } +/* ========= Errata 31 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_31_PRESENT 1 +#else + #define NRF91_ERRATA_31_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_31_ENABLE_WORKAROUND + #define NRF91_ERRATA_31_ENABLE_WORKAROUND NRF91_ERRATA_31_PRESENT +#endif + static bool nrf91_errata_31(void) { #ifndef NRF91_SERIES @@ -693,6 +937,17 @@ static bool nrf91_errata_31(void) #endif } +/* ========= Errata 32 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_32_PRESENT 1 +#else + #define NRF91_ERRATA_32_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_32_ENABLE_WORKAROUND + #define NRF91_ERRATA_32_ENABLE_WORKAROUND NRF91_ERRATA_32_PRESENT +#endif + static bool nrf91_errata_32(void) { #ifndef NRF91_SERIES @@ -720,6 +975,17 @@ static bool nrf91_errata_32(void) #endif } +/* ========= Errata 33 ========= */ +#if defined (NRF9160_XXAA) || defined (DEVELOP_IN_NRF9160) + #define NRF91_ERRATA_33_PRESENT 1 +#else + #define NRF91_ERRATA_33_PRESENT 0 +#endif + +#ifndef NRF91_ERRATA_33_ENABLE_WORKAROUND + #define NRF91_ERRATA_33_ENABLE_WORKAROUND NRF91_ERRATA_33_PRESENT +#endif + static bool nrf91_errata_33(void) { #ifndef NRF91_SERIES diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf_erratas.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf_erratas.h index 484b38595..83f4bcf89 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf_erratas.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf_erratas.h @@ -1,41 +1,32 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52.c b/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52.c new file mode 100644 index 000000000..9ae86795d --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52.c @@ -0,0 +1,316 @@ +/* + +Copyright (c) 2009-2021 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +/* NOTE: Template files (including this one) are application specific and therefore expected to + be copied into the application project folder prior to its use! */ + +#include +#include +#include "nrf.h" +#include "nrf_peripherals.h" +#include "nrf_erratas.h" +#include "system_nrf52.h" + +#define __SYSTEM_CLOCK_64M (64000000UL) + + +#if defined ( __CC_ARM ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; +#elif defined ( __ICCARM__ ) + __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M; +#elif defined ( __GNUC__ ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; +#endif + +/* Select correct reset pin */ +/* Handle DEVELOP_IN-targets first as they take precedence over the later macros */ +#if defined (DEVELOP_IN_NRF52805) \ + || defined (DEVELOP_IN_NRF52810) \ + || defined (DEVELOP_IN_NRF52811) \ + || defined (DEVELOP_IN_NRF52832) + #define RESET_PIN 21 +#elif defined (DEVELOP_IN_NRF52820) \ + || defined (DEVELOP_IN_NRF52833) \ + || defined (DEVELOP_IN_NRF52840) + #define RESET_PIN 18 +#elif defined (NRF52805_XXAA) \ + || defined (NRF52810_XXAA) \ + || defined (NRF52811_XXAA) \ + || defined (NRF52832_XXAA) \ + || defined (NRF52832_XXAB) + #define RESET_PIN 21 +#elif defined (NRF52820_XXAA) \ + || defined (NRF52833_XXAA) \ + || defined (NRF52840_XXAA) + #define RESET_PIN 18 +#else + #error "A supported device macro must be defined." +#endif + +/* -- NVMC utility functions -- */ +/* Waits until NVMC is done with the current pending action */ +void nvmc_wait(void) +{ + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} +} + +/* Configure the NVMC to "mode". + Mode must be an enumerator of field NVMC_CONFIG_WEN */ +void nvmc_config(uint32_t mode) +{ + NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos; + nvmc_wait(); +} + +void SystemCoreClockUpdate(void) +{ + SystemCoreClock = __SYSTEM_CLOCK_64M; +} + +void SystemInit(void) +{ + /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product + Specification to see which one). */ + #if defined (ENABLE_SWO) && defined(CLOCK_TRACECONFIG_TRACEMUX_Pos) + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; + NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + #endif + + /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product + Specification to see which ones). */ + #if defined (ENABLE_TRACE) && defined(CLOCK_TRACECONFIG_TRACEMUX_Pos) + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos; + NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + #endif + + #if NRF52_ERRATA_12_ENABLE_WORKAROUND + /* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_12()){ + *(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8; + } + #endif + + #if NRF52_ERRATA_16_ENABLE_WORKAROUND + /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_16()){ + *(volatile uint32_t *)0x4007C074 = 3131961357ul; + } + #endif + + #if NRF52_ERRATA_31_ENABLE_WORKAROUND + /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_31()){ + *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13; + } + #endif + + #if NRF52_ERRATA_32_ENABLE_WORKAROUND + /* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_32()){ + CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; + } + #endif + + #if NRF52_ERRATA_36_ENABLE_WORKAROUND + /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_36()){ + NRF_CLOCK->EVENTS_DONE = 0; + NRF_CLOCK->EVENTS_CTTO = 0; + NRF_CLOCK->CTIV = 0; + } + #endif + + #if NRF52_ERRATA_37_ENABLE_WORKAROUND + /* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_37()){ + *(volatile uint32_t *)0x400005A0 = 0x3; + } + #endif + + #if NRF52_ERRATA_57_ENABLE_WORKAROUND + /* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_57()){ + *(volatile uint32_t *)0x40005610 = 0x00000005; + *(volatile uint32_t *)0x40005688 = 0x00000001; + *(volatile uint32_t *)0x40005618 = 0x00000000; + *(volatile uint32_t *)0x40005614 = 0x0000003F; + } + #endif + + #if NRF52_ERRATA_66_ENABLE_WORKAROUND + /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_66()){ + NRF_TEMP->A0 = NRF_FICR->TEMP.A0; + NRF_TEMP->A1 = NRF_FICR->TEMP.A1; + NRF_TEMP->A2 = NRF_FICR->TEMP.A2; + NRF_TEMP->A3 = NRF_FICR->TEMP.A3; + NRF_TEMP->A4 = NRF_FICR->TEMP.A4; + NRF_TEMP->A5 = NRF_FICR->TEMP.A5; + NRF_TEMP->B0 = NRF_FICR->TEMP.B0; + NRF_TEMP->B1 = NRF_FICR->TEMP.B1; + NRF_TEMP->B2 = NRF_FICR->TEMP.B2; + NRF_TEMP->B3 = NRF_FICR->TEMP.B3; + NRF_TEMP->B4 = NRF_FICR->TEMP.B4; + NRF_TEMP->B5 = NRF_FICR->TEMP.B5; + NRF_TEMP->T0 = NRF_FICR->TEMP.T0; + NRF_TEMP->T1 = NRF_FICR->TEMP.T1; + NRF_TEMP->T2 = NRF_FICR->TEMP.T2; + NRF_TEMP->T3 = NRF_FICR->TEMP.T3; + NRF_TEMP->T4 = NRF_FICR->TEMP.T4; + } + #endif + + #if NRF52_ERRATA_98_ENABLE_WORKAROUND + /* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_98()){ + *(volatile uint32_t *)0x4000568Cul = 0x00038148ul; + } + #endif + + #if NRF52_ERRATA_103_ENABLE_WORKAROUND && defined(CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) + /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_103()){ + NRF_CCM->MAXPACKETSIZE = 0xFBul; + } + #endif + + #if NRF52_ERRATA_108_ENABLE_WORKAROUND + /* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_108()){ + *(volatile uint32_t *)0x40000EE4ul = *(volatile uint32_t *)0x10000258ul & 0x0000004Ful; + } + #endif + + #if NRF52_ERRATA_115_ENABLE_WORKAROUND + /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_115()){ + *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F); + } + #endif + + #if NRF52_ERRATA_120_ENABLE_WORKAROUND + /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_120()){ + *(volatile uint32_t *)0x40029640ul = 0x200ul; + } + #endif + + #if NRF52_ERRATA_136_ENABLE_WORKAROUND + /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_136()){ + if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){ + NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk; + } + } + #endif + + #if NRF52_ERRATA_182_ENABLE_WORKAROUND + /* Workaround for Errata 182 "RADIO: Fixes for anomalies #102, #106, and #107 do not take effect" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_182()){ + *(volatile uint32_t *) 0x4000173C |= (0x1 << 10); + } + #endif + + #if NRF52_ERRATA_217_ENABLE_WORKAROUND + /* Workaround for Errata 217 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf52_errata_217()){ + *(volatile uint32_t *)0x40000EE4ul |= 0x0000000Ful; + } + #endif + + /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the + * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit + * operations are not used in your code. */ + #if (__FPU_USED == 1) + SCB->CPACR |= (3UL << 20) | (3UL << 22); + __DSB(); + __ISB(); + #endif + + /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, + two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as + normal GPIOs. */ + #if defined (CONFIG_NFCT_PINS_AS_GPIOS) && defined(NFCT_PRESENT) + if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){ + nvmc_config(NVMC_CONFIG_WEN_Wen); + NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk; + nvmc_wait(); + nvmc_config(NVMC_CONFIG_WEN_Ren); + NVIC_SystemReset(); + } + #endif + + /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not + defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be + reserved for PinReset and not available as normal GPIO. */ + #if defined (CONFIG_GPIO_AS_PINRESET) + if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || + ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ + nvmc_config(NVMC_CONFIG_WEN_Wen); + NRF_UICR->PSELRESET[0] = RESET_PIN; + nvmc_wait(); + NRF_UICR->PSELRESET[1] = RESET_PIN; + nvmc_wait(); + nvmc_config(NVMC_CONFIG_WEN_Ren); + NVIC_SystemReset(); + } + #endif + + /* When developing for nRF52810 on an nRF52832, or nRF52811 on an nRF52840, + make sure NFC pins are mapped as GPIO. */ + #if defined (DEVELOP_IN_NRF52832) && defined(NRF52810_XXAA) \ + || defined (DEVELOP_IN_NRF52840) && defined(NRF52811_XXAA) + if (((*((uint32_t *)0x10001200) & (1 << 0)) != 0) || ((*((uint32_t *)0x10001204) & (1 << 0)) != 0)){ + nvmc_config(NVMC_CONFIG_WEN_Wen); + *((uint32_t *)0x10001200) = 0; + nvmc_wait(); + *((uint32_t *)0x10001204) = 0; + nvmc_wait(); + nvmc_config(NVMC_CONFIG_WEN_Ren); + NVIC_SystemReset(); + } + #endif + + SystemCoreClockUpdate(); +} diff --git a/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52.h b/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52.h new file mode 100644 index 000000000..bd3919cb0 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52.h @@ -0,0 +1,61 @@ +/* + +Copyright (c) 2009-2021 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +#ifndef SYSTEM_NRF52_H +#define SYSTEM_NRF52_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_NRF52_H */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52820.c b/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52820.c deleted file mode 100644 index eb09aafc2..000000000 --- a/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52820.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - -Copyright (c) 2009-2020 ARM Limited. All rights reserved. - - SPDX-License-Identifier: Apache-2.0 - -Licensed under the Apache License, Version 2.0 (the License); you may -not use this file except in compliance with the License. -You may obtain a copy of the License at - - www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an AS IS BASIS, WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -NOTICE: This file has been modified by Nordic Semiconductor ASA. - -*/ - -/* NOTE: Template files (including this one) are application specific and therefore expected to - be copied into the application project folder prior to its use! */ - -#include -#include -#include "nrf.h" -#include "nrf_erratas.h" -#include "system_nrf52820.h" - -/*lint ++flb "Enter library region" */ - -#define __SYSTEM_CLOCK_64M (64000000UL) - -#if defined ( __CC_ARM ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; -#elif defined ( __ICCARM__ ) - __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M; -#elif defined ( __GNUC__ ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; -#endif - -void SystemCoreClockUpdate(void) -{ - SystemCoreClock = __SYSTEM_CLOCK_64M; -} - -void SystemInit(void) -{ - /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf52_errata_36()){ - NRF_CLOCK->EVENTS_DONE = 0; - NRF_CLOCK->EVENTS_CTTO = 0; - NRF_CLOCK->CTIV = 0; - } - - /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf52_errata_66()){ - NRF_TEMP->A0 = NRF_FICR->TEMP.A0; - NRF_TEMP->A1 = NRF_FICR->TEMP.A1; - NRF_TEMP->A2 = NRF_FICR->TEMP.A2; - NRF_TEMP->A3 = NRF_FICR->TEMP.A3; - NRF_TEMP->A4 = NRF_FICR->TEMP.A4; - NRF_TEMP->A5 = NRF_FICR->TEMP.A5; - NRF_TEMP->B0 = NRF_FICR->TEMP.B0; - NRF_TEMP->B1 = NRF_FICR->TEMP.B1; - NRF_TEMP->B2 = NRF_FICR->TEMP.B2; - NRF_TEMP->B3 = NRF_FICR->TEMP.B3; - NRF_TEMP->B4 = NRF_FICR->TEMP.B4; - NRF_TEMP->B5 = NRF_FICR->TEMP.B5; - NRF_TEMP->T0 = NRF_FICR->TEMP.T0; - NRF_TEMP->T1 = NRF_FICR->TEMP.T1; - NRF_TEMP->T2 = NRF_FICR->TEMP.T2; - NRF_TEMP->T3 = NRF_FICR->TEMP.T3; - NRF_TEMP->T4 = NRF_FICR->TEMP.T4; - } - - /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf52_errata_136()){ - if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){ - NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk; - } - } - - /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the - * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit - * operations are not used in your code. */ - #if (__FPU_USED == 1) - SCB->CPACR |= (3UL << 20) | (3UL << 22); - __DSB(); - __ISB(); - #endif - - /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not - defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be - reserved for PinReset and not available as normal GPIO. */ - #if defined (CONFIG_GPIO_AS_PINRESET) - if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || - ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_UICR->PSELRESET[0] = 18; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_UICR->PSELRESET[1] = 18; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NVIC_SystemReset(); - } - #endif - - SystemCoreClockUpdate(); -} - -/*lint --flb "Leave library region" */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52820.h b/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52820.h index a2a326dd1..5b5b77dd2 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52820.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52820.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 From 0dffdbd93d5f692ac32bffe337fe4878d5cd6365 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 15 Jul 2021 06:39:35 -0500 Subject: [PATCH 411/617] nrf52820_hic: change bl size to 32 KB and total flash to 128 KB --- source/board/nrf52820_bl.c | 4 ++-- source/hic_hal/nordic/nrf52820/daplink_addr.h | 13 +++++++------ 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/source/board/nrf52820_bl.c b/source/board/nrf52820_bl.c index a0612ecd3..01aa1422a 100644 --- a/source/board/nrf52820_bl.c +++ b/source/board/nrf52820_bl.c @@ -26,8 +26,8 @@ #include "target_family.h" // Warning - changing the interface start will break backwards compatibility -COMPILER_ASSERT(DAPLINK_ROM_IF_START == 0x00010000); -COMPILER_ASSERT(DAPLINK_ROM_IF_SIZE == KB(188)); +COMPILER_ASSERT(DAPLINK_ROM_IF_START == 0x00008000); +COMPILER_ASSERT(DAPLINK_ROM_IF_SIZE == KB(92)); /** * List of start and size for each size of flash sector diff --git a/source/hic_hal/nordic/nrf52820/daplink_addr.h b/source/hic_hal/nordic/nrf52820/daplink_addr.h index a472ac365..561fd26b2 100644 --- a/source/hic_hal/nordic/nrf52820/daplink_addr.h +++ b/source/hic_hal/nordic/nrf52820/daplink_addr.h @@ -22,7 +22,8 @@ /* Device sizes */ #define DAPLINK_ROM_START 0x00000000 -#define DAPLINK_ROM_SIZE 0x00040000 +#define DAPLINK_ROM_SIZE 0x00020000 // Limit to 128 KiB + #define DAPLINK_RAM_START 0x20000000 #define DAPLINK_RAM_SIZE 0x00008000 // 32 KiB @@ -30,12 +31,12 @@ /* ROM sizes */ #define DAPLINK_ROM_BL_START 0x00000000 -#define DAPLINK_ROM_BL_SIZE 0x00010000 // 64 KiB bootloader +#define DAPLINK_ROM_BL_SIZE 0x00008000 // 32 KiB bootloader -#define DAPLINK_ROM_IF_START 0x00010000 -#define DAPLINK_ROM_IF_SIZE 0x0002F000 +#define DAPLINK_ROM_IF_START 0x00008000 +#define DAPLINK_ROM_IF_SIZE 0x00017000 -#define DAPLINK_ROM_CONFIG_USER_START 0x0003F000 +#define DAPLINK_ROM_CONFIG_USER_START 0x0001F000 #define DAPLINK_ROM_CONFIG_USER_SIZE 0x00001000 /* RAM sizes */ @@ -49,7 +50,7 @@ /* Flash Programming Info */ #define DAPLINK_SECTOR_SIZE 0x00001000 -#define DAPLINK_MIN_WRITE_SIZE 0x00001000 +#define DAPLINK_MIN_WRITE_SIZE 0x00000100 /* Current build */ From 7c8b9d0106686e6220d73b2a469668c5a01e3f18 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 15 Jul 2021 06:40:20 -0500 Subject: [PATCH 412/617] nrf52820_hic: implement bootloader flashing --- records/hic_hal/nrf52820.yaml | 1 + source/hic_hal/nordic/nrf52820/flash.c | 12 +- .../nordic/nrf52820/nrfx/hal/nrf_nvmc.c | 133 +++++ .../nordic/nrf52820/nrfx/hal/nrf_nvmc.h | 460 ++++++++++++++++++ 4 files changed, 602 insertions(+), 4 deletions(-) create mode 100644 source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_nvmc.c create mode 100644 source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_nvmc.h diff --git a/records/hic_hal/nrf52820.yaml b/records/hic_hal/nrf52820.yaml index 911424bfd..6a6ba92b8 100644 --- a/records/hic_hal/nrf52820.yaml +++ b/records/hic_hal/nrf52820.yaml @@ -22,6 +22,7 @@ common: - source/hic_hal/nordic/nrf52820 - source/hic_hal/nordic/nrf52820/cmsis - source/hic_hal/nordic/nrf52820/nrfx + - source/hic_hal/nordic/nrf52820/nrfx/hal tool_specific: uvision: diff --git a/source/hic_hal/nordic/nrf52820/flash.c b/source/hic_hal/nordic/nrf52820/flash.c index 788494dae..120b4304d 100644 --- a/source/hic_hal/nordic/nrf52820/flash.c +++ b/source/hic_hal/nordic/nrf52820/flash.c @@ -1,6 +1,6 @@ /** * @file flash.c - * @brief Flash access functions for nrf52833 HIC + * @brief Flash access functions for nrf52820 HIC * * DAPLink Interface Firmware * Copyright (c) 2021, Arm Limited, All Rights Reserved @@ -21,27 +21,31 @@ #include "target_config.h" +#include "nrf_nvmc.h" + uint32_t Init(uint32_t adr, uint32_t clk, uint32_t fnc) { - return 0; + return 0; // Not needed } uint32_t UnInit(uint32_t fnc) { - return 0; + return 0; // Not needed } uint32_t EraseChip(void) { - return 0; + return 0; // Not used in DAPLink } uint32_t EraseSector(uint32_t adr) { + nrf_nvmc_page_erase(adr); return 0; } uint32_t ProgramPage(uint32_t adr, uint32_t sz, uint32_t *buf) { + nrf_nvmc_write_words(adr, buf, sz / 4); return 0; } diff --git a/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_nvmc.c b/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_nvmc.c new file mode 100644 index 000000000..601b74e34 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_nvmc.c @@ -0,0 +1,133 @@ +/** + * Copyright (c) 2012 - 2020, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/** + *@file + *@brief NMVC driver implementation + */ + +#include +#include "nrf_nvmc.h" + +static inline void wait_for_flash_ready(void) +{ + while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {;} +} + +void nrf_nvmc_page_erase(uint32_t address) +{ + // Enable erase. + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Een; + __ISB(); + __DSB(); + + // Erase the page + NRF_NVMC->ERASEPAGE = address; + wait_for_flash_ready(); + + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren; + __ISB(); + __DSB(); +} + + +void nrf_nvmc_write_byte(uint32_t address, uint8_t value) +{ + uint32_t byte_shift = address & (uint32_t)0x03; + uint32_t address32 = address & ~byte_shift; // Address to the word this byte is in. + uint32_t value32 = (*(uint32_t*)address32 & ~((uint32_t)0xFF << (byte_shift << (uint32_t)3))); + value32 = value32 + ((uint32_t)value << (byte_shift << 3)); + + // Enable write. + NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos); + __ISB(); + __DSB(); + + *(uint32_t*)address32 = value32; + wait_for_flash_ready(); + + NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos); + __ISB(); + __DSB(); +} + +void nrf_nvmc_write_word(uint32_t address, uint32_t value) +{ + // Enable write. + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen; + __ISB(); + __DSB(); + + *(uint32_t*)address = value; + wait_for_flash_ready(); + + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren; + __ISB(); + __DSB(); +} + +void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes) +{ + uint32_t i; + for (i = 0; i < num_bytes; i++) + { + nrf_nvmc_write_byte(address + i,src[i]); + } +} + +void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words) +{ + uint32_t i; + + // Enable write. + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen; + __ISB(); + __DSB(); + + for (i = 0; i < num_words; i++) + { + ((uint32_t*)address)[i] = src[i]; + wait_for_flash_ready(); + } + + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren; + __ISB(); + __DSB(); +} + diff --git a/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_nvmc.h b/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_nvmc.h new file mode 100644 index 000000000..605972ccb --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_nvmc.h @@ -0,0 +1,460 @@ +/** + * Copyright (c) 2012 - 2020, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_NVMC_H__ +#define NRF_NVMC_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_nvmc_hal_deprecated NVMC HAL (deprecated) + * @{ + * @ingroup nrf_nvmc + * @brief Hardware access layer (HAL) for managing the Non-Volatile Memory Controller (NVMC) peripheral. + * + * This driver allows writing to the non-volatile memory (NVM) regions + * of the chip. To write to NVM, the controller must be powered + * on and the relevant page must be erased. + */ + +/** + * @brief Erase a page in flash. This is required before writing to any address in the page. + * + * @param address Start address of the page. + */ +void nrf_nvmc_page_erase(uint32_t address); + +/** + * @brief Write a single byte to flash. + * + * The function reads the word containing the byte, and then rewrites the entire word. + * + * @param address Address to write to. + * @param value Value to write. + */ +void nrf_nvmc_write_byte(uint32_t address , uint8_t value); + +/** + * @brief Write a 32-bit word to flash. + * + * @param address Address to write to. + * @param value Value to write. + */ +void nrf_nvmc_write_word(uint32_t address, uint32_t value); + +/** + * @brief Write consecutive bytes to flash. + * + * @param address Address to write to. + * @param src Pointer to data to copy from. + * @param num_bytes Number of bytes in src to write. + */ +void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes); + +/** + * @brief Write consecutive words to flash. + * + * @param address Address to write to. + * @param src Pointer to data to copy from. + * @param num_words Number of words in src to write. + */ +void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words); + +/** @} */ + +/** + * @defgroup nrf_nvmc_hal NVMC HAL + * @{ + * @ingroup nrf_nvmc + * @brief Hardware access layer (HAL) for managing the Non-Volatile Memory Controller (NVMC) peripheral. + */ + +#if defined(NVMC_ICACHECNF_CACHEEN_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether Instruction Cache (ICache) is present. */ +#define NRF_NVMC_ICACHE_PRESENT +#endif + +#if defined(NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether the option of page partial erase is present. */ +#define NRF_NVMC_PARTIAL_ERASE_PRESENT +#endif + +/** @brief NVMC modes. */ +typedef enum +{ + NRF_NVMC_MODE_READONLY = NVMC_CONFIG_WEN_Ren, ///< NVMC in read-only mode. + NRF_NVMC_MODE_WRITE = NVMC_CONFIG_WEN_Wen, ///< NVMC in read and write mode. + NRF_NVMC_MODE_ERASE = NVMC_CONFIG_WEN_Een, ///< NVMC in read and erase mode. +#if defined(NVMC_CONFIG_WEN_PEen) + NRF_NVMC_MODE_PARTIAL_ERASE = NVMC_CONFIG_WEN_PEen ///< NVMC in read and partial erase mode. +#endif +} nrf_nvmc_mode_t; + +#if defined(NVMC_CONFIGNS_WEN_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Non-secure NVMC modes. */ +typedef enum +{ + NRF_NVMC_NS_MODE_READONLY = NVMC_CONFIGNS_WEN_Ren, ///< Non-secure NVMC in read-only mode. + NRF_NVMC_NS_MODE_WRITE = NVMC_CONFIGNS_WEN_Wen, ///< Non-secure NVMC in read and write mode. + NRF_NVMC_NS_MODE_ERASE = NVMC_CONFIGNS_WEN_Een, ///< Non-secure NVMC in read and erase mode. +} nrf_nvmc_ns_mode_t; +#endif + +#if defined(NRF_NVMC_ICACHE_PRESENT) +/** @brief NVMC ICache configuration. */ +typedef enum +{ + NRF_NVMC_ICACHE_DISABLE = NVMC_ICACHECNF_CACHEEN_Disabled, ///< Instruction Cache disabled. + NRF_NVMC_ICACHE_ENABLE = NVMC_ICACHECNF_CACHEEN_Enabled, ///< Instruction Cache enabled. + NRF_NVMC_ICACHE_ENABLE_WITH_PROFILING = NVMC_ICACHECNF_CACHEEN_Enabled | ///< Instruction Cache with cache profiling enabled. + NVMC_ICACHECNF_CACHEPROFEN_Msk +} nrf_nvmc_icache_config_t; +#endif // defined(NRF_NVMC_ICACHE_PRESENT) + +/** + * @brief Function for checking if NVMC is ready to perform write or erase operation. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval true NVMC can perform write or erase. + * @retval false NVMC is busy and cannot perform next operation yet. + */ +__STATIC_INLINE bool nrf_nvmc_ready_check(NRF_NVMC_Type const * p_reg); + +#if defined(NVMC_READYNEXT_READYNEXT_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for checking if NVMC is ready to accept the next write operation. + * + * NVM writing time can be reduced by using this function. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval true NVMC can accept the next write. It will be buffered and will be taken + * into account as soon as the ongoing write operation is completed. + * @retval false NVMC is busy and cannot accept the next write yet. + */ +__STATIC_INLINE bool nrf_nvmc_write_ready_check(NRF_NVMC_Type const * p_reg); +#endif // defined(NVMC_READYNEXT_READYNEXT_Msk) || defined(__NRFX_DOXYGEN__) + +/** + * @brief Function for setting the NVMC mode. + * + * Only activate erase and write modes when they are actively used. + * If Instruction Cache (ICache) is present, enabling write or erase will + * invalidate the cache and keep it invalidated. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mode Desired operating mode for NVMC. + */ +__STATIC_INLINE void nrf_nvmc_mode_set(NRF_NVMC_Type * p_reg, + nrf_nvmc_mode_t mode); + +#if defined(NVMC_CONFIGNS_WEN_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for setting the NVMC mode for non-secure Flash page operations. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mode Desired operating mode for NVMC. + */ +__STATIC_INLINE void nrf_nvmc_nonsecure_mode_set(NRF_NVMC_Type * p_reg, + nrf_nvmc_ns_mode_t mode); +#endif + +/** + * @brief Function for starting a single page erase in the Flash memory. + * + * The NVMC mode must be correctly configured with @ref nrf_nvmc_mode_set + * before starting the erase operation. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] page_addr Address of the first word of the page to erase. + */ +__STATIC_INLINE void nrf_nvmc_page_erase_start(NRF_NVMC_Type * p_reg, + uint32_t page_addr); + +#if defined(NVMC_ERASEUICR_ERASEUICR_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for starting the user information configuration registers (UICR) erase. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + */ +__STATIC_INLINE void nrf_nvmc_uicr_erase_start(NRF_NVMC_Type * p_reg); +#endif + +/** + * @brief Function for starting the erase of the whole NVM, including UICR. + * + * This function purges all user code. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + */ +__STATIC_INLINE void nrf_nvmc_erase_all_start(NRF_NVMC_Type * p_reg); + +#if defined(NRF_NVMC_PARTIAL_ERASE_PRESENT) +/** + * @brief Function for configuring the page partial erase duration in milliseconds. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] duration_ms Page partial erase duration in milliseconds. + */ +__STATIC_INLINE void nrf_nvmc_partial_erase_duration_set(NRF_NVMC_Type * p_reg, + uint32_t duration_ms); + +/** + * @brief Function for getting the current setting for the page partial erase duration. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval Interval duration setting in milliseconds. + */ +__STATIC_INLINE uint32_t nrf_nvmc_partial_erase_duration_get(NRF_NVMC_Type const * p_reg); + +/** + * @brief Function for starting a partial erase operation. + * + * It must be called successively until the page erase time is reached. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] page_addr Address of the first word of the page to erase. + */ +__STATIC_INLINE void nrf_nvmc_page_partial_erase_start(NRF_NVMC_Type * p_reg, + uint32_t page_addr); +#endif // defined(NRF_NVMC_PARTIAL_ERASE_PRESENT) + +#if defined(NRF_NVMC_ICACHE_PRESENT) +/** + * @brief Function for applying the Instruction Cache (ICache) configuration. + * + * Enabling the cache can increase CPU performance and reduce power + * consumption by reducing the number of wait cycles and the number + * of flash accesses. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] config ICache configuration. + */ +__STATIC_INLINE void nrf_nvmc_icache_config_set(NRF_NVMC_Type * p_reg, + nrf_nvmc_icache_config_t config); + +/** + * @brief Function for checking if ICache is enabled. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval true ICache enabled. + * @retval false ICache disabled. + */ +__STATIC_INLINE bool nrf_nvmc_icache_enable_check(NRF_NVMC_Type const * p_reg); + +/** + * @brief Function for checking if the ICache profiling option is enabled. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval true ICache profiling enabled. + * @retval false ICache profiling disabled. + */ +__STATIC_INLINE bool nrf_nvmc_icache_profiling_enable_check(NRF_NVMC_Type const * p_reg); + +/** + * @brief Function for getting the number of ICache hits. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval Number of the ICache hits. + */ +__STATIC_INLINE uint32_t nrf_nvmc_icache_hit_get(NRF_NVMC_Type const * p_reg); + +/** + * @brief Function for getting the number of ICache misses. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval Number of the ICache misses. + */ +__STATIC_INLINE uint32_t nrf_nvmc_icache_miss_get(NRF_NVMC_Type const * p_reg); + +/** + * @brief Function for resetting the ICache hit and miss counters. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + */ + __STATIC_INLINE void nrf_nvmc_icache_hit_miss_reset(NRF_NVMC_Type * p_reg); +#endif // defined(NRF_NVMC_ICACHE_PRESENT) + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE bool nrf_nvmc_ready_check(NRF_NVMC_Type const * p_reg) +{ + return (bool)(p_reg->READY & NVMC_READY_READY_Msk); +} + +#if defined(NVMC_READYNEXT_READYNEXT_Msk) +__STATIC_INLINE bool nrf_nvmc_write_ready_check(NRF_NVMC_Type const * p_reg) +{ + return (bool)(p_reg->READYNEXT & NVMC_READYNEXT_READYNEXT_Msk); +} +#endif + +__STATIC_INLINE void nrf_nvmc_mode_set(NRF_NVMC_Type * p_reg, + nrf_nvmc_mode_t mode) +{ + p_reg->CONFIG = (uint32_t)mode; +} + +#if defined(NVMC_CONFIGNS_WEN_Msk) +__STATIC_INLINE void nrf_nvmc_nonsecure_mode_set(NRF_NVMC_Type * p_reg, + nrf_nvmc_ns_mode_t mode) +{ + p_reg->CONFIGNS = (uint32_t)mode; +} +#endif + +__STATIC_INLINE void nrf_nvmc_page_erase_start(NRF_NVMC_Type * p_reg, + uint32_t page_addr) +{ +#if defined(NRF51) + /* On nRF51, the code area can be divided into two regions: CR0 and CR1. + * The length of CR0 is specified in the CLENR0 register of UICR. + * If CLENR0 contains the 0xFFFFFFFF value, CR0 is not set. + * Moreover, the page from CR0 can be written or erased only from code + * running in CR0.*/ + uint32_t cr0_len = NRF_UICR->CLENR0 == 0xFFFFFFFF ? 0 : NRF_UICR->CLENR0; + if (page_addr < cr0_len) + { + p_reg->ERASEPCR0 = page_addr; + } + else + { + p_reg->ERASEPCR1 = page_addr; + } +#elif defined(NRF52_SERIES) + p_reg->ERASEPAGE = page_addr; +#elif defined(NRF9160_XXAA) + *(volatile uint32_t *)page_addr = 0xFFFFFFFF; + (void)p_reg; +#else + #error "Unknown device." +#endif +} + +#if defined(NVMC_ERASEUICR_ERASEUICR_Msk) +__STATIC_INLINE void nrf_nvmc_uicr_erase_start(NRF_NVMC_Type * p_reg) +{ + p_reg->ERASEUICR = 1; +} +#endif + +__STATIC_INLINE void nrf_nvmc_erase_all_start(NRF_NVMC_Type * p_reg) +{ + p_reg->ERASEALL = 1; +} + +#if defined(NRF_NVMC_PARTIAL_ERASE_PRESENT) +__STATIC_INLINE void nrf_nvmc_partial_erase_duration_set(NRF_NVMC_Type * p_reg, + uint32_t duration_ms) +{ + p_reg->ERASEPAGEPARTIALCFG = duration_ms; +} + +__STATIC_INLINE uint32_t nrf_nvmc_partial_erase_duration_get(NRF_NVMC_Type const * p_reg) +{ + return p_reg->ERASEPAGEPARTIALCFG; +} + +__STATIC_INLINE void nrf_nvmc_page_partial_erase_start(NRF_NVMC_Type * p_reg, + uint32_t page_addr) +{ +#if defined(NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Msk) + p_reg->ERASEPAGEPARTIAL = page_addr; +#elif defined(NRF9160_XXAA) + nrf_nvmc_page_erase_start(p_reg, page_addr); +#else + #error "Unknown device." +#endif +} +#endif // defined(NRF_NVMC_PARTIAL_ERASE_PRESENT) + +#if defined(NRF_NVMC_ICACHE_PRESENT) +__STATIC_INLINE void nrf_nvmc_icache_config_set(NRF_NVMC_Type * p_reg, + nrf_nvmc_icache_config_t config) +{ + p_reg->ICACHECNF = (uint32_t)config; +} + +__STATIC_INLINE bool nrf_nvmc_icache_enable_check(NRF_NVMC_Type const * p_reg) +{ + return (bool)(p_reg->ICACHECNF & NVMC_ICACHECNF_CACHEEN_Msk); +} + +__STATIC_INLINE bool nrf_nvmc_icache_profiling_enable_check(NRF_NVMC_Type const * p_reg) +{ + return (bool)(p_reg->ICACHECNF & NVMC_ICACHECNF_CACHEPROFEN_Msk); +} + +__STATIC_INLINE uint32_t nrf_nvmc_icache_hit_get(NRF_NVMC_Type const * p_reg) +{ + return p_reg->IHIT; +} + +__STATIC_INLINE uint32_t nrf_nvmc_icache_miss_get(NRF_NVMC_Type const * p_reg) +{ + return p_reg->IMISS; +} + +__STATIC_INLINE void nrf_nvmc_icache_hit_miss_reset(NRF_NVMC_Type * p_reg) +{ + p_reg->IHIT = 0; + p_reg->IMISS = 0; +} +#endif // defined(NRF_NVMC_ICACHE_PRESENT) + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_NVMC_H__ From b750ec8b1ba722a61f41655e4f425c2b0eaa3506 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 15 Jul 2021 06:43:47 -0500 Subject: [PATCH 413/617] nrf52820_hic: nrf52xx interface projects --- projects.yaml | 4 +- records/board/nrf52820_if.yaml | 11 ++++ source/board/nrf52820_if.c | 55 +++++++++++++++++++ .../nrf52820/gcc/gcc_startup_nrf52820.S | 2 +- 4 files changed, 69 insertions(+), 3 deletions(-) create mode 100644 records/board/nrf52820_if.yaml create mode 100644 source/board/nrf52820_if.c diff --git a/projects.yaml b/projects.yaml index 795ff3dc1..bb5f0731e 100644 --- a/projects.yaml +++ b/projects.yaml @@ -174,14 +174,14 @@ projects: - records/usb/usb-bulk.yaml nrf52833_dk_bl: - *module_bl - - records/board/nrf52833_dk.yaml - records/hic_hal/nrf52820.yaml - records/board/nrf52820_bl.yaml + - records/board/nrf52833_dk.yaml nrf52833_dk_if: - *module_if - *module_hic_nrf52820 + - records/board/nrf52820_if.yaml - records/board/nrf52833_dk.yaml - - records/family/all_family.yaml - records/usb/usb-bulk.yaml sam3u2c_bl: - *module_bl diff --git a/records/board/nrf52820_if.yaml b/records/board/nrf52820_if.yaml new file mode 100644 index 000000000..14c135567 --- /dev/null +++ b/records/board/nrf52820_if.yaml @@ -0,0 +1,11 @@ +common: + macros: + # - TARGET_NRF52 + # - TARGET_NRF52_64 + - TARGET_NRF52840 + sources: + board: + - source/board/nrf52820_if.c + target: + - source/family/nordic/nrf5x/target.c + - source/family/nordic/target_reset_nrf52.c diff --git a/source/board/nrf52820_if.c b/source/board/nrf52820_if.c new file mode 100644 index 000000000..64274e02d --- /dev/null +++ b/source/board/nrf52820_if.c @@ -0,0 +1,55 @@ +/** + * @file nrf52820_if.c + * @brief board ID for nrf528xx on nrf52820 + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2021, Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_family.h" +#include "target_board.h" + +const char * const board_id_nrf52 = "FF01"; +const char * const board_id_nrf52_64 = "FF02"; +const char * const board_id_nrf52840 = "FF03"; + +extern target_cfg_t target_device_nrf52; +extern target_cfg_t target_device_nrf52_64; +extern target_cfg_t target_device_nrf52840; + +static void nrf_prerun_board_config(void) { +#if defined(TARGET_NRF52) + target_device = target_device_nrf52; + target_device.rt_board_id = board_id_nrf52; +#elif defined(TARGET_NRF52_64) + target_device = target_device_nrf52_64; + target_device.rt_board_id = board_id_nrf52_64; +#elif defined(TARGET_NRF52840) + target_device = target_device_nrf52840; + target_device.rt_board_id = board_id_nrf52840; +#else +#error "No target defined" +#endif +} + +const board_info_t g_board_info = { + .info_version = kBoardInfoVersion, + .family_id = kNordic_Nrf52_FamilyID, + .info_version = kBoardInfoVersion, + .flags = kEnablePageErase, + .prerun_board_config = nrf_prerun_board_config, + .target_cfg = &target_device, +}; diff --git a/source/hic_hal/nordic/nrf52820/gcc/gcc_startup_nrf52820.S b/source/hic_hal/nordic/nrf52820/gcc/gcc_startup_nrf52820.S index 3b406ce86..812dec8b9 100644 --- a/source/hic_hal/nordic/nrf52820/gcc/gcc_startup_nrf52820.S +++ b/source/hic_hal/nordic/nrf52820/gcc/gcc_startup_nrf52820.S @@ -8,7 +8,7 @@ Licensed under the Apache License, Version 2.0 (the License); you may not use this file except in compliance with the License. You may obtain a copy of the License at - https://www.apache.org/licenses/LICENSE-2.0 + http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an AS IS BASIS, WITHOUT From 4eba499081f88e78d49b0372db026cc2efdf1243 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 15 Jul 2021 17:57:20 +0200 Subject: [PATCH 414/617] nrf52820_hic: fix uvision compilation --- records/hic_hal/nrf52820.yaml | 2 +- source/board/nrf52820_bl.c | 2 +- source/hic_hal/nordic/nrf52820/sdk.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/records/hic_hal/nrf52820.yaml b/records/hic_hal/nrf52820.yaml index 6a6ba92b8..1394cacef 100644 --- a/records/hic_hal/nrf52820.yaml +++ b/records/hic_hal/nrf52820.yaml @@ -28,7 +28,7 @@ tool_specific: uvision: misc: ld_flags: - - --predefine="-I..\..\..\source\hic_hal\nrf52820\nrfx" + - --predefine="-I..\..\..\source\hic_hal\nordic\nrf52820" sources: hic_hal: - source/hic_hal/nordic/nrf52820/armcc diff --git a/source/board/nrf52820_bl.c b/source/board/nrf52820_bl.c index 01aa1422a..ed4d007fb 100644 --- a/source/board/nrf52820_bl.c +++ b/source/board/nrf52820_bl.c @@ -40,7 +40,7 @@ static const sector_info_t sectors_info[] = { {DAPLINK_ROM_IF_START, 0x1000}, }; -// m48ssidae target information +// nrf52820 target information target_cfg_t target_device = { .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), diff --git a/source/hic_hal/nordic/nrf52820/sdk.c b/source/hic_hal/nordic/nrf52820/sdk.c index 34fbaef38..035295c62 100644 --- a/source/hic_hal/nordic/nrf52820/sdk.c +++ b/source/hic_hal/nordic/nrf52820/sdk.c @@ -20,7 +20,7 @@ */ #include "device.h" -#include "DAP_config.h" +#include "IO_config.h" #include "daplink.h" #include "util.h" From eb18bf528df16ef1bb34b916840fcc0a678286c4 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 16 Jul 2021 13:53:37 +0200 Subject: [PATCH 415/617] Initial attempt at DAP_config.h, alternate pin mapping and documentation --- docs/hic/nrf52820.md | 58 +++++++++++++++++++ .../override_nrf52833_dk/IO_Config_Override.h | 15 ++++- source/hic_hal/nordic/nrf52820/IO_Config.h | 4 ++ .../nrf52820/armcc/arm_startup_nrf52820.s | 20 +++---- .../nrf52820/gcc/gcc_startup_nrf52820.S | 8 +-- 5 files changed, 88 insertions(+), 17 deletions(-) create mode 100644 docs/hic/nrf52820.md diff --git a/docs/hic/nrf52820.md b/docs/hic/nrf52820.md new file mode 100644 index 000000000..b22033385 --- /dev/null +++ b/docs/hic/nrf52820.md @@ -0,0 +1,58 @@ +# nrf52820 HIC + +Based on Nordic [nRF52820](https://www.nordicsemi.com/Products/nRF52820): +- Cortex-M4 64 MHz +-256 KB Flash +- 32 KB RAM +- Full-speed USB 2.0 device controller +- QFN40 packaging + +## Memory Map + +| Region | Size | Start | End | +|----------|--------|-------------|-------------| +| Flash | 128 KB | 0x0000_0000 | 0x0002_0000 | +| SRAM | 32 KB | 0x2000_0000 | 0x2000_8000 | + +Bootloader size is 32 KB +Limiting flash usage to 128 KB + + +## DAPLink default pin assignment + +| Signal | I/O | Symbol | Pin | +|-------------|:---:|---------|:---:| +| SWD | +| SWCLK | O | P0.00 | 3 | +| SWDIO | I/O | P0.01 | 2 | +| UART | +| UART RX | I | P0.08 | 31 | +| UART TX | O | P0.29 | 32 | +| Button | +| F-RST But. | I | P0.06 | 6 | +| LEDs | +| HID LED | O | P0.07 | 7 | +| MSD LED | O | P0.07 | 7 | +| CDC LED | O | P0.07 | 7 | + +## nRF52833-DK pin assignment + +For development on [nRF52833-DK](https://www.nordicsemi.com/Products/Development-hardware/nRF52833-DK). + +| Signal | I/O | Symbol | Pin | Connection | +|-------------|:---:|---------|:----:|:----------:| +| SWD | +| SWCLK | O | P1.06 | R24 | Arduino D5 | +| SWDIO | I/O | P1.07 | P23 | Arduino D6 | +| nRESET | O | P1.08 | N2 | Arduino D7 | +| UART | +| UART RX | I | P0.08 | N1 | J-Link TX | +| UART TX | O | P0.06 | L1 | J-Link RX | +| Button | +| F-RST But. | I | P0.11 | T2 | BUTTON_1 | +| LEDs | +| RUN LED | O | P0.13 | AD8 | LED_1 | +| CON LED | O | P0.14 | AC9 | LED_2 | +| HID LED | O | P0.14 | AC9 | LED_2 | +| MSD LED | O | P0.15 | AD10 | LED_3 | +| CDC LED | O | P0.16 | AC11 | LED_4 | diff --git a/source/board/override_nrf52833_dk/IO_Config_Override.h b/source/board/override_nrf52833_dk/IO_Config_Override.h index 1915e0682..4de92d005 100644 --- a/source/board/override_nrf52833_dk/IO_Config_Override.h +++ b/source/board/override_nrf52833_dk/IO_Config_Override.h @@ -38,13 +38,13 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_NRF52820); #define BUTTON_1 NRF_GPIO_PIN_MAP(0, 11) // SWDCLK (Output) -#define PIN_SWDCLK NRF_GPIO_PIN_MAP(0, 1) // FIXME: Needs to change +#define PIN_SWDCLK NRF_GPIO_PIN_MAP(1, 6) // Arduino D5 // SWDIO (Input/Output) -#define PIN_SWDIO NRF_GPIO_PIN_MAP(0, 0) // FIXME: Needs to change +#define PIN_SWDIO NRF_GPIO_PIN_MAP(1, 7) // Arduino D6 // nRESET Pin -#define PIN_nRESET NRF_GPIO_PIN_MAP(0, 6) // FIXME: Needs to change +#define PIN_nRESET NRF_GPIO_PIN_MAP(1, 8) // Arduino D7 // Target Running LED (Output) #define LED_RUNNING LED_1 @@ -65,4 +65,13 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_NRF52820); #define RESET_BUTTON BUTTON_1 #define RESET_BUTTON_PULL NRF_GPIO_PIN_PULLUP +// UART +// This is connected to J-Link +#define UART_RX NRF_GPIO_PIN_MAP(0, 8) // RxD P0.08 +#define UART_TX NRF_GPIO_PIN_MAP(0, 6) // TxD P0.06 + +// Alternative connected to Arduino D0 / D1 +// #define UART_RX NRF_GPIO_PIN_MAP(1, 1) +// #define UART_TX NRF_GPIO_PIN_MAP(1, 2) + #endif diff --git a/source/hic_hal/nordic/nrf52820/IO_Config.h b/source/hic_hal/nordic/nrf52820/IO_Config.h index 44c1cb9f2..3b5241eb7 100644 --- a/source/hic_hal/nordic/nrf52820/IO_Config.h +++ b/source/hic_hal/nordic/nrf52820/IO_Config.h @@ -67,4 +67,8 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_NRF52820); #define RESET_BUTTON NRF_GPIO_PIN_MAP(0, 6) #define RESET_BUTTON_PULL NRF_GPIO_PIN_PULLUP +// UART +#define UART_TX NRF_GPIO_PIN_MAP(0, 8) // From IMCU to target +#define UART_RX NRF_GPIO_PIN_MAP(0, 29) // From target to IMCU + #endif diff --git a/source/hic_hal/nordic/nrf52820/armcc/arm_startup_nrf52820.s b/source/hic_hal/nordic/nrf52820/armcc/arm_startup_nrf52820.s index d4b71f88a..ff8572aef 100644 --- a/source/hic_hal/nordic/nrf52820/armcc/arm_startup_nrf52820.s +++ b/source/hic_hal/nordic/nrf52820/armcc/arm_startup_nrf52820.s @@ -1,19 +1,19 @@ ; Copyright (c) 2009-2020 ARM Limited. All rights reserved. -; +; ; SPDX-License-Identifier: Apache-2.0 -; +; ; Licensed under the Apache License, Version 2.0 (the License); you may ; not use this file except in compliance with the License. ; You may obtain a copy of the License at -; +; ; www.apache.org/licenses/LICENSE-2.0 -; +; ; Unless required by applicable law or agreed to in writing, software ; distributed under the License is distributed on an AS IS BASIS, WITHOUT ; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ; See the License for the specific language governing permissions and ; limitations under the License. -; +; ; NOTICE: This file has been modified by Nordic Semiconductor ASA. IF :DEF: __STARTUP_CONFIG @@ -32,7 +32,7 @@ Stack_Size EQU __STACK_SIZE ELSE Stack_Size EQU 2048 ENDIF - + IF :DEF: __STARTUP_CONFIG Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT ELSE @@ -74,12 +74,12 @@ __Vectors DCD __initial_sp ; Top of Stack DCD BusFault_Handler DCD UsageFault_Handler DCD 0 ; Reserved - DCD DAPLINK_BUILD_KEY ; Build type - BL/IF - DCD DAPLINK_HIC_ID ; Compatibility - DCD DAPLINK_VERSION ; Version + DCD DAPLINK_BUILD_KEY ; DAPLINK: Build type (BL/IF) + DCD DAPLINK_HIC_ID ; DAPLINK: Compatibility + DCD DAPLINK_VERSION ; DAPLINK: Version DCD SVC_Handler DCD DebugMon_Handler - DCD g_board_info ; Ptr to Board info, family info other target details + DCD g_board_info ; DAPLINK: Pointer to board/family/target info DCD PendSV_Handler DCD SysTick_Handler diff --git a/source/hic_hal/nordic/nrf52820/gcc/gcc_startup_nrf52820.S b/source/hic_hal/nordic/nrf52820/gcc/gcc_startup_nrf52820.S index 812dec8b9..05d328597 100644 --- a/source/hic_hal/nordic/nrf52820/gcc/gcc_startup_nrf52820.S +++ b/source/hic_hal/nordic/nrf52820/gcc/gcc_startup_nrf52820.S @@ -36,12 +36,12 @@ __isr_vector: .long BusFault_Handler .long UsageFault_Handler .long 0 /*Reserved */ - .long DAPLINK_BUILD_KEY /* Build type - BL/IF */ - .long DAPLINK_HIC_ID /* Compatibility */ - .long DAPLINK_VERSION /* Version */ + .long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF) */ + .long DAPLINK_HIC_ID /* DAPLINK: Compatibility */ + .long DAPLINK_VERSION /* DAPLINK: Version */ .long SVC_Handler .long DebugMon_Handler - .long g_board_info /* Ptr to Board info, family info other target details */ + .long g_board_info /* DAPLINK: Pointer to board/family/target info */ .long PendSV_Handler .long SysTick_Handler From 628185a7dc194f45ac2e6049750cf8b02c76f561 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 20 Jul 2021 05:30:02 -0500 Subject: [PATCH 416/617] nrf52820_hic: import USART CMSIS Driver --- source/hic_hal/nordic/nrf52820/RTE_Device.h | 56 ++ .../hic_hal/nordic/nrf52820/USART_nRF52820.c | 865 ++++++++++++++++++ .../hic_hal/nordic/nrf52820/USART_nRF52820.h | 49 + 3 files changed, 970 insertions(+) create mode 100644 source/hic_hal/nordic/nrf52820/RTE_Device.h create mode 100644 source/hic_hal/nordic/nrf52820/USART_nRF52820.c create mode 100644 source/hic_hal/nordic/nrf52820/USART_nRF52820.h diff --git a/source/hic_hal/nordic/nrf52820/RTE_Device.h b/source/hic_hal/nordic/nrf52820/RTE_Device.h new file mode 100644 index 000000000..26bbf5ee9 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/RTE_Device.h @@ -0,0 +1,56 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2021 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 16. July 2021 + * $Revision: V1.0 + * + * Project: RTE Device Configuration for Nordic Semiconductor nRF52820 + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART +#define RTE_USART0 1 + +// TX Pin +// Pin number +#define RTE_USART0_TX_EN 1 +#define RTE_USART0_TX_PIN_NUM 6 +// +// RX Pin +// Pin number +#define RTE_USART0_RX_EN 1 +#define RTE_USART0_RX_PIN_NUM 8 +// +// CTS Pin +// Pin number +#define RTE_USART0_CTS_EN 1 +#define RTE_USART0_CTS_PIN_NUM 7 +// +// RTS Pin +// Pin number +#define RTE_USART0_RTS_EN 1 +#define RTE_USART0_RTS_PIN_NUM 5 +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/source/hic_hal/nordic/nrf52820/USART_nRF52820.c b/source/hic_hal/nordic/nrf52820/USART_nRF52820.c new file mode 100644 index 000000000..04792d7b9 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/USART_nRF52820.c @@ -0,0 +1,865 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2021 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 16. July 2021 + * $Revision: V1.0 + * + * Driver: Driver_USART0 + * Configured: via RTE_Device.h configuration file + * Project: USART Driver definitions for Nordic Semiconductor nRF52820 + * -------------------------------------------------------------------------- + * Use the following configuration settings in the middleware component + * to connect to this driver. + * + * Configuration Setting Value UART Interface + * --------------------- ----- -------------- + * Connect to hardware via Driver_USART# = 0 use USART0 + * -------------------------------------------------------------------------- + * Notes: + * - this driver does not implement CTS change detection because it would + * require usage of GPIOTE peripheral and IRQ shared between all pins + * -------------------------------------------------------------------------- */ + +/* History: + * Version 1.0 + * Initial release + */ + + +#include "USART_nRF52820.h" + +#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */ + +/* Driver Version */ +static const ARM_DRIVER_VERSION driver_version = { + ARM_USART_API_VERSION, + ARM_USART_DRV_VERSION +}; + +/* Driver Capabilities */ +static const ARM_USART_CAPABILITIES driver_capabilities = { + 1U, /* supports UART (Asynchronous) mode */ + 0U, /* supports Synchronous Master mode */ + 0U, /* supports Synchronous Slave mode */ + 0U, /* supports UART Single-wire mode */ + 0U, /* supports UART IrDA mode */ + 0U, /* supports UART Smart Card mode */ + 0U, /* Smart Card Clock generator available */ + (RTE_USART0_RTS_EN != 0U) ? 1U : 0U, /* RTS Flow Control support */ + (RTE_USART0_CTS_EN != 0U) ? 1U : 0U, /* CTS Flow Control support */ + 1U, /* Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE */ + 1U, /* Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT */ + (RTE_USART0_RTS_EN != 0U) ? 1U : 0U, /* RTS Line: 0=not available, 1=available */ + (RTE_USART0_CTS_EN != 0U) ? 1U : 0U, /* CTS Line: 0=not available, 1=available */ + 0U, /* DTR Line: 0=not available, 1=available */ + 0U, /* DSR Line: 0=not available, 1=available */ + 0U, /* DCD Line: 0=not available, 1=available */ + 0U, /* RI Line: 0=not available, 1=available */ + 0U, /* Signal CTS change event: \ref ARM_USART_EVENT_CTS */ + 0U, /* Signal DSR change event: \ref ARM_USART_EVENT_DSR */ + 0U, /* Signal DCD change event: \ref ARM_USART_EVENT_DCD */ + 0U, /* Signal RI change event: \ref ARM_USART_EVENT_RI */ + 0U /* Reserved (must be zero) */ +}; + +static ARM_USART_SignalEvent_t fn_signal_event = NULL; // Event callback +static ARM_USART_STATUS usart_status; + +static uint32_t driver_state = 0U; // Driver state +static uint32_t flow_control = 0U; // Flow control mode +static uint32_t rts_gpio_cnf = 0U; // Index of RTS gpio cnf + 1 (0 = unconfigured) +static uint32_t cts_gpio_cnf = 0U; // Index of CTS gpio cnf + 1 (0 = unconfigured) + +static void *ptr_tx_data = NULL; // Pointer to data for transmission +static uint32_t tx_num = 0U; // Number of bytes requested for transmission +static uint32_t rx_num = 0U; // Number of bytes requested for reception +static uint32_t tx_cnt = 0U; // Number of transmitted bytes +static uint32_t tx_buf[32/4]; // Intermediate RAM buffer for transmission + // (EasyDMA cannot transmit from flash directly) + +/* Function prototypes */ +static ARM_DRIVER_VERSION USART_GetVersion (void); +static ARM_USART_CAPABILITIES USART_GetCapabilities (void); +static int32_t USART_Initialize (ARM_USART_SignalEvent_t cb_event); +static int32_t USART_Uninitialize (void); +static int32_t USART_PowerControl (ARM_POWER_STATE state); +static int32_t USART_Send (const void *data, uint32_t num); +static int32_t USART_Receive ( void *data, uint32_t num); +static int32_t USART_Transfer (const void *data_out, void *data_in, uint32_t num); +static uint32_t USART_GetTxCount (void); +static uint32_t USART_GetRxCount (void); +static int32_t USART_Control (uint32_t control, uint32_t arg); +static ARM_USART_STATUS USART_GetStatus (void); +static int32_t USART_SetModemControl (ARM_USART_MODEM_CONTROL control); +static ARM_USART_MODEM_STATUS USART_GetModemStatus (void); + + +/* Helper functions */ + +/* Start EasyDMA transfer Tx/Rx*/ +void usart_dma_start (uint32_t dir, void *data, uint32_t num) { + + if (dir == RX_DIR) { + NRF_UARTE0->RXD.PTR = (uint32_t)data; + NRF_UARTE0->RXD.MAXCNT = num; + NRF_UARTE0->TASKS_STARTRX = UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger; + NRF_UARTE0->INTENSET = UARTE_INTENSET_ENDRX_Msk; + } else { + NRF_UARTE0->TXD.PTR = (uint32_t)data; + NRF_UARTE0->TXD.MAXCNT = num; + NRF_UARTE0->TASKS_STARTTX = UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger; + NRF_UARTE0->INTENSET = UARTE_INTENSET_ENDTX_Msk; + } +} + + +/* Driver functions */ + +/** + \fn ARM_DRIVER_VERSION USART_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION +*/ +static ARM_DRIVER_VERSION USART_GetVersion (void) { + return driver_version; +} + +/** + \fn ARM_USART_CAPABILITIES USART_GetCapabilities (void) + \brief Get driver capabilities + \return \ref ARM_USART_CAPABILITIES +*/ +static ARM_USART_CAPABILITIES USART_GetCapabilities (void) { + return driver_capabilities; +} + +/** + \fn int32_t USART_Initialize (ARM_USART_SignalEvent_t cb_event) + \brief Initialize USART Interface. + \param[in] cb_event Pointer to \ref ARM_USART_SignalEvent + \return \ref execution_status +*/ +static int32_t USART_Initialize (ARM_USART_SignalEvent_t cb_event) { + + fn_signal_event = cb_event; /* Register callback event function */ + + if ((driver_state & USART_FLAG_INITIALIZED) != 0U) { + // If Driver is already initialized + return ARM_DRIVER_OK; + } + + driver_state = USART_FLAG_INITIALIZED; + + return ARM_DRIVER_OK; +} + +/** + \fn int32_t USART_Uninitialize (void) + \brief De-initialize USART Interface. + \return \ref execution_status +*/ +static int32_t USART_Uninitialize (void) { + + if ((driver_state & USART_FLAG_POWERED) != 0U) { + // If peripheral is powered, power-off the peripheral + (void)USART_PowerControl(ARM_POWER_OFF); + } + + /* Uninitialize pins */ +#if (RTE_USART0_TX_EN != 0U) /* If Tx Pin is enabled in config file */ + /* Disconnect TXD */ + NRF_UARTE0->PSEL.TXD = RTE_USART0_TX_PIN_NUM | UARTE_PSEL_TXD_CONNECT_Msk; + + /* Configure Tx pin as GPIO with configuration as after reset */ + NRF_GPIO->PIN_CNF[RTE_USART0_TX_PIN_NUM] = 2U; +#endif +#if (RTE_USART0_RX_EN != 0U) /* If Rx Pin is enabled in config file */ + /* Disconnect RXD */ + NRF_UARTE0->PSEL.RXD = RTE_USART0_RX_PIN_NUM | UARTE_PSEL_RXD_CONNECT_Msk; + + /* Configure Rx pin as GPIO with configuration as after reset */ + NRF_GPIO->PIN_CNF[RTE_USART0_RX_PIN_NUM] = 2U; +#endif +#if (RTE_USART0_CTS_EN != 0U) /* If CTS Pin is enabled in config file */ + /* Disconnect CTS */ + NRF_UARTE0->PSEL.CTS = RTE_USART0_CTS_PIN_NUM | UARTE_PSEL_CTS_CONNECT_Msk; + + /* Configure CTS pin as GPIO with configuration as after reset */ + NRF_GPIO->PIN_CNF[RTE_USART0_CTS_PIN_NUM] = 2U; +#endif +#if (RTE_USART0_RTS_EN != 0U) /* If RTS Pin is enabled in config file */ + /* Disconnect RTS */ + NRF_UARTE0->PSEL.RTS = RTE_USART0_RTS_PIN_NUM | UARTE_PSEL_RTS_CONNECT_Msk; + + /* Configure RTS pin as GPIO with configuration as after reset */ + NRF_GPIO->PIN_CNF[RTE_USART0_RTS_PIN_NUM] = 2U; +#endif + + driver_state = 0U; + + fn_signal_event = NULL; + + return ARM_DRIVER_OK; +} + +/** + \fn int32_t USART_PowerControl (ARM_POWER_STATE state) + \brief Control USART Interface Power. + \param[in] state Power state + \return \ref execution_status +*/ +static int32_t USART_PowerControl (ARM_POWER_STATE state) { + + if ((driver_state & USART_FLAG_INITIALIZED) == 0U) { + return ARM_DRIVER_ERROR; + } + + if ((state != ARM_POWER_OFF) && + (state != ARM_POWER_FULL) && + (state != ARM_POWER_LOW)) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + switch (state) { + case ARM_POWER_OFF: + if (usart_status.tx_busy != 0U) { + (void)USART_Control(ARM_USART_ABORT_SEND, 0U); + } + if (usart_status.rx_busy != 0U) { + (void)USART_Control(ARM_USART_ABORT_RECEIVE, 0U); + } + + /* Disable USARTE peripheral */ + NRF_UARTE0->ENABLE = UARTE_ENABLE_ENABLE_Disabled; + + NVIC_DisableIRQ(UARTE0_UART0_IRQn); + + USART_Control(ARM_USART_ABORT_SEND, 0U); + USART_Control(ARM_USART_ABORT_RECEIVE, 0U); + + /* Clear variables */ + memset(&usart_status, 0, sizeof(ARM_USART_STATUS)); + ptr_tx_data = NULL; + tx_num = 0U; + rx_num = 0U; + tx_cnt = 0U; + memset(tx_buf, 0, sizeof(tx_buf)); + + driver_state &= ~USART_FLAG_POWERED; + break; + + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + + case ARM_POWER_FULL: + if ((driver_state & USART_FLAG_POWERED) != 0U) { + return ARM_DRIVER_OK; + } + + /* Clear variables */ + memset(&usart_status, 0, sizeof(ARM_USART_STATUS)); + ptr_tx_data = NULL; + tx_num = 0U; + rx_num = 0U; + tx_cnt = 0U; + memset(tx_buf, 0, sizeof(tx_buf)); + + /* Enable USARTE peripheral */ + NRF_UARTE0->ENABLE = UARTE_ENABLE_ENABLE_Enabled; + + driver_state |= USART_FLAG_POWERED; + + NVIC_ClearPendingIRQ(UARTE0_UART0_IRQn); + NVIC_EnableIRQ(UARTE0_UART0_IRQn); + break; + } + + return ARM_DRIVER_OK; +} + +/** + \fn int32_t USART_Send (const void *data, uint32_t num) + \brief Start sending data to USART transmitter. + \param[in] data Pointer to buffer with data to send to USART transmitter + \param[in] num Number of data items to send + \return \ref execution_status +*/ +static int32_t USART_Send (const void *data, uint32_t num) { + uint32_t num_local; + + if (usart_status.tx_busy != 0U) { + return ARM_DRIVER_ERROR_BUSY; + } + + usart_status.tx_busy = 1U; + + num_local = num; + if (num > sizeof(tx_buf)) { + num_local = sizeof(tx_buf); + } + + /* Set auxiliary variables used for transmission */ + ptr_tx_data = (void *)data; + tx_num = num; + tx_cnt = 0U; + + /* Copy data to intermediate Tx buffer (up to intermediate Tx buffer size) */ + memcpy(tx_buf, data, num_local); + + /* Start transmission from intermediate Tx buffer */ + usart_dma_start(TX_DIR, tx_buf, num_local); + + return ARM_DRIVER_OK; +} + +/** + \fn int32_t USART_Receive (void *data, uint32_t num) + \brief Start receiving data from USART receiver. + \param[out] data Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to receive + \return \ref execution_status +*/ +static int32_t USART_Receive (void *data, uint32_t num) { + + if (usart_status.rx_busy != 0U) { + return ARM_DRIVER_ERROR_BUSY; + } + + usart_status.rx_busy = 1U; + + /* Start reception */ + usart_dma_start(RX_DIR, data, num); + + return ARM_DRIVER_OK; +} + +/** + \fn int32_t USART_Transfer (const void *data_out, void *data_in, uint32_t num) + \brief Start sending/receiving data to/from USART transmitter/receiver. + \param[in] data_out Pointer to buffer with data to send to USART transmitter + \param[out] data_in Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to transfer + \return \ref execution_status +*/ +static int32_t USART_Transfer (const void *data_out, void *data_in, uint32_t num) { + + /* This USART Controller does not support Synchronous mode */ + return ARM_DRIVER_ERROR; +} + +/** + \fn uint32_t USART_GetTxCount (void) + \brief Get transmitted data count. + \return number of data items transmitted +*/ +static uint32_t USART_GetTxCount (void) { + return tx_cnt; +} + +/** + \fn uint32_t USART_GetRxCount (void) + \brief Get received data count. + \return number of data items received +*/ +static uint32_t USART_GetRxCount (void) { + if (rx_num != 0U) { + return NRF_UARTE0->RXD.AMOUNT; + } + + return 0U; +} + +/** + \fn int32_t USART_Control (uint32_t control, uint32_t arg) + \brief Control USART Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \return common \ref execution_status and driver specific \ref usart_execution_status +*/ +static int32_t USART_Control (uint32_t control, uint32_t arg) { + uint32_t cnt; + + switch (control & ARM_USART_CONTROL_Msk) { + case ARM_USART_MODE_ASYNCHRONOUS: + /* Only Asynchronous mode is supported */ + + /* Configure data bits */ + switch (control & ARM_USART_DATA_BITS_Msk) { + case ARM_USART_DATA_BITS_8: + break; + case ARM_USART_DATA_BITS_5: + case ARM_USART_DATA_BITS_6: + case ARM_USART_DATA_BITS_7: + case ARM_USART_DATA_BITS_9: + default: + return ARM_USART_ERROR_DATA_BITS; + } + + /* Configure parity */ + switch (control & ARM_USART_PARITY_Msk) { + case ARM_USART_PARITY_NONE: + NRF_UARTE0->CONFIG &= ~UARTE_CONFIG_PARITY_Msk; + break; + case ARM_USART_PARITY_EVEN: + NRF_UARTE0->CONFIG &= ~UARTE_CONFIG_PARITYTYPE_Msk; + NRF_UARTE0->CONFIG &= ~UARTE_CONFIG_PARITY_Msk; + break; + case ARM_USART_PARITY_ODD: + NRF_UARTE0->CONFIG |= UARTE_CONFIG_PARITYTYPE_Msk; + NRF_UARTE0->CONFIG &= ~UARTE_CONFIG_PARITY_Msk; + break; + default: + return ARM_USART_ERROR_PARITY; + } + + /* Configure stop bits */ + switch (control & ARM_USART_STOP_BITS_Msk) { + case ARM_USART_STOP_BITS_1: + NRF_UARTE0->CONFIG &= ~UARTE_CONFIG_STOP_Msk; + break; + case ARM_USART_STOP_BITS_2: + NRF_UARTE0->CONFIG |= UARTE_CONFIG_STOP_Msk; + break; + case ARM_USART_STOP_BITS_1_5: + case ARM_USART_STOP_BITS_0_5: + default: + return ARM_USART_ERROR_STOP_BITS; + } + + /* Configure flow control */ + switch (control & ARM_USART_FLOW_CONTROL_Msk) { + case ARM_USART_FLOW_CONTROL_NONE: +#if (RTE_USART0_CTS_EN != 0U) /* If CTS Pin is enabled in config file */ + /* Disconnect CTS */ + NRF_UARTE0->PSEL.CTS = RTE_USART0_CTS_PIN_NUM | UARTE_PSEL_CTS_CONNECT_Msk; + + /* Configure CTS pin as GPIO input with pull-up */ + NRF_GPIO->PIN_CNF[RTE_USART0_CTS_PIN_NUM] = GPIO_PIN_CNF_PULL_Msk; +#endif +#if (RTE_USART0_RTS_EN != 0U) /* If RTS Pin is enabled in config file */ + /* Disconnect RTS */ + NRF_UARTE0->PSEL.RTS = RTE_USART0_RTS_PIN_NUM | UARTE_PSEL_RTS_CONNECT_Msk; + + /* Configure RTS pin as GPIO output with pull-up */ + NRF_GPIO->PIN_CNF[RTE_USART0_RTS_PIN_NUM] = GPIO_PIN_CNF_PULL_Msk | GPIO_PIN_CNF_DIR_Output | GPIO_PIN_CNF_INPUT_Msk; +#endif + /* Disable hardware flow control */ + NRF_UARTE0->CONFIG &= ~UARTE_CONFIG_HWFC_Msk; + break; + case ARM_USART_FLOW_CONTROL_RTS_CTS: +#if (RTE_USART0_CTS_EN != 0U) /* If CTS Pin is enabled in config file */ + /* Configure CTS pin as GPIO input with pull-up */ + NRF_GPIO->PIN_CNF[RTE_USART0_CTS_PIN_NUM] = GPIO_PIN_CNF_PULL_Msk; + + /* Connect CTS */ + NRF_UARTE0->PSEL.CTS = RTE_USART0_CTS_PIN_NUM; +#endif +#if (RTE_USART0_RTS_EN != 0U) /* If RTS Pin is enabled in config file */ + /* Configure RTS pin as GPIO output with pull-up */ + NRF_GPIO->PIN_CNF[RTE_USART0_RTS_PIN_NUM] = GPIO_PIN_CNF_PULL_Msk | GPIO_PIN_CNF_DIR_Output | GPIO_PIN_CNF_INPUT_Msk; + + /* Connect RTS */ + NRF_UARTE0->PSEL.RTS = RTE_USART0_RTS_PIN_NUM; +#endif + /* Enable hardware flow control */ + NRF_UARTE0->CONFIG |= UARTE_CONFIG_HWFC_Msk; + break; + case ARM_USART_FLOW_CONTROL_CTS: + case ARM_USART_FLOW_CONTROL_RTS: + default: + return ARM_USART_ERROR_FLOW_CONTROL; + } + + /* Ignore clock polarity and clock phase setting */ + + /* Configure baudrate */ + switch (arg) { + case 1200: + NRF_UARTE0->BAUDRATE = UARTE_BAUDRATE_BAUDRATE_Baud1200; + break; + case 2400: + NRF_UARTE0->BAUDRATE = UARTE_BAUDRATE_BAUDRATE_Baud2400; + break; + case 4800: + NRF_UARTE0->BAUDRATE = UARTE_BAUDRATE_BAUDRATE_Baud4800; + break; + case 9600: + NRF_UARTE0->BAUDRATE = UARTE_BAUDRATE_BAUDRATE_Baud9600; + break; + case 14400: + NRF_UARTE0->BAUDRATE = UARTE_BAUDRATE_BAUDRATE_Baud14400; + break; + case 19200: + NRF_UARTE0->BAUDRATE = UARTE_BAUDRATE_BAUDRATE_Baud19200; + break; + case 28800: + NRF_UARTE0->BAUDRATE = UARTE_BAUDRATE_BAUDRATE_Baud28800; + break; + case 31250: + NRF_UARTE0->BAUDRATE = UARTE_BAUDRATE_BAUDRATE_Baud31250; + break; + case 38400: + NRF_UARTE0->BAUDRATE = UARTE_BAUDRATE_BAUDRATE_Baud38400; + break; + case 56000: + NRF_UARTE0->BAUDRATE = UARTE_BAUDRATE_BAUDRATE_Baud56000; + break; + case 57600: + NRF_UARTE0->BAUDRATE = UARTE_BAUDRATE_BAUDRATE_Baud57600; + break; + case 76800: + NRF_UARTE0->BAUDRATE = UARTE_BAUDRATE_BAUDRATE_Baud76800; + break; + case 115200: + NRF_UARTE0->BAUDRATE = UARTE_BAUDRATE_BAUDRATE_Baud115200; + break; + case 230400: + NRF_UARTE0->BAUDRATE = UARTE_BAUDRATE_BAUDRATE_Baud230400; + break; + case 250000: + NRF_UARTE0->BAUDRATE = UARTE_BAUDRATE_BAUDRATE_Baud250000; + break; + case 460800: + NRF_UARTE0->BAUDRATE = UARTE_BAUDRATE_BAUDRATE_Baud460800; + break; + case 921600: + NRF_UARTE0->BAUDRATE = UARTE_BAUDRATE_BAUDRATE_Baud921600; + break; + case 1000000: + NRF_UARTE0->BAUDRATE = UARTE_BAUDRATE_BAUDRATE_Baud1M; + break; + default: + return ARM_USART_ERROR_BAUDRATE; + } + break; + + case ARM_USART_CONTROL_TX: +#if (RTE_USART0_TX_EN != 0U) /* If Tx Pin is enabled in config file */ + switch (arg) { + case 0: /* Disable transmitter */ + /* Disconnect TXD */ + NRF_UARTE0->PSEL.TXD = RTE_USART0_TX_PIN_NUM | UARTE_PSEL_TXD_CONNECT_Msk; + + /* Leave pull-up */ + break; + case 1: /* Enable transmitter */ + /* Configure Tx pin as GPIO output with pull-up */ + NRF_GPIO->PIN_CNF[RTE_USART0_TX_PIN_NUM] = GPIO_PIN_CNF_PULL_Msk | GPIO_PIN_CNF_DIR_Output | GPIO_PIN_CNF_INPUT_Msk; + + /* Connect TXD */ + NRF_UARTE0->PSEL.TXD = RTE_USART0_TX_PIN_NUM; + break; + default: + return ARM_DRIVER_ERROR_PARAMETER; + } + break; +#elif + return ARM_DRIVER_ERROR_UNSUPPORTED; +#endif + + case ARM_USART_CONTROL_RX: +#if (RTE_USART0_RX_EN != 0U) /* If Rx Pin is enabled in config file */ + switch (arg) { + case 0: /* Disable receiver */ + /* Disconnect RXD */ + NRF_UARTE0->PSEL.RXD = RTE_USART0_RX_PIN_NUM | UARTE_PSEL_RXD_CONNECT_Msk; + + /* Leave pull-up */ + + /* Disable Rx timeout and error event detection */ + NRF_UARTE0->INTENCLR = UARTE_INTENCLR_RXTO_Msk | UARTE_INTENCLR_ERROR_Msk; + break; + case 1: /* Enable receiver */ + /* Configure Rx pin as GPIO input with pull-up */ + NRF_GPIO->PIN_CNF[RTE_USART0_RX_PIN_NUM] = GPIO_PIN_CNF_PULL_Msk; + + /* Connect RXD */ + NRF_UARTE0->PSEL.RXD = RTE_USART0_RX_PIN_NUM; + + /* Enable Rx timeout and error event detection */ + NRF_UARTE0->INTENSET = UARTE_INTENSET_RXTO_Msk | UARTE_INTENSET_ERROR_Msk; + break; + default: + return ARM_DRIVER_ERROR_PARAMETER; + } + break; +#elif + return ARM_DRIVER_ERROR_UNSUPPORTED; +#endif + + case ARM_USART_ABORT_SEND: + /* Disable TXSTOPPED and ENDTX interrupt */ + NRF_UARTE0->INTENCLR = UARTE_INTENCLR_TXSTOPPED_Msk | UARTE_INTENCLR_ENDTX_Msk; + + /* Stop Tx */ + NRF_UARTE0->TASKS_STOPTX = UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger; + for (cnt = 160000U; cnt != 0U; cnt--) { + if (NRF_UARTE0->EVENTS_TXSTOPPED == 1U) { + usart_status.tx_busy = 0U; + break; + } + } + if (cnt == 0U) { /* If timeout */ + return ARM_DRIVER_ERROR_TIMEOUT; + } + break; + + case ARM_USART_ABORT_RECEIVE: + /* Disable RXTO and ENDRX interrupts */ + NRF_UARTE0->INTENCLR = UARTE_INTENCLR_RXTO_Msk | UARTE_INTENCLR_ENDRX_Msk; + + /* Stop Rx */ + NRF_UARTE0->TASKS_STOPRX = UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger; + for (cnt = 160000U; cnt != 0U; cnt--) { + if (NRF_UARTE0->EVENTS_RXTO == 1U) { + usart_status.rx_busy = 0U; + break; + } + } + if (cnt == 0U) { /* If timeout */ + return ARM_DRIVER_ERROR_TIMEOUT; + } + + /* Flush Rx FIFO to Rx buffer */ + NRF_UARTE0->TASKS_FLUSHRX = UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger; + for (cnt = 160000U; cnt != 0U; cnt--) { + if (NRF_UARTE0->EVENTS_ENDRX == 1U) { + break; + } + } + if (cnt == 0U) { /* If timeout */ + return ARM_DRIVER_ERROR_TIMEOUT; + } + break; + + /* Unsupported modes */ + case ARM_USART_MODE_SYNCHRONOUS_MASTER: + case ARM_USART_MODE_SYNCHRONOUS_SLAVE: + case ARM_USART_MODE_SINGLE_WIRE: + case ARM_USART_MODE_IRDA: + case ARM_USART_MODE_SMART_CARD: + return ARM_USART_ERROR_MODE; + + /* Unsupported miscellaneous operations */ + case ARM_USART_SET_DEFAULT_TX_VALUE: + case ARM_USART_SET_IRDA_PULSE: + case ARM_USART_SET_SMART_CARD_GUARD_TIME: + case ARM_USART_SET_SMART_CARD_CLOCK: + case ARM_USART_CONTROL_SMART_CARD_NACK: + case ARM_USART_CONTROL_BREAK: + case ARM_USART_ABORT_TRANSFER: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +/** + \fn ARM_USART_STATUS USART_GetStatus (void) + \brief Get USART status. + \return USART status \ref ARM_USART_STATUS +*/ +static ARM_USART_STATUS USART_GetStatus (void) { + return usart_status; +} + +/** + \fn int32_t USART_SetModemControl (ARM_USART_MODEM_CONTROL control) + \brief Set USART Modem Control line state. + \param[in] control \ref ARM_USART_MODEM_CONTROL + \return \ref execution_status +*/ +static int32_t USART_SetModemControl (ARM_USART_MODEM_CONTROL control) { + + switch (control) { + case ARM_USART_RTS_CLEAR: + if ((flow_control == ARM_USART_FLOW_CONTROL_NONE) || + (flow_control == ARM_USART_FLOW_CONTROL_CTS)) { +#if (RTE_USART0_RTS_EN != 0U) + if ((rts_gpio_cnf == 0U) || + (rts_gpio_cnf > 328U) || + ((NRF_GPIOTE->CONFIG[rts_gpio_cnf-1U] & 1) != 1U)) { + /* If RTS pin is not configured as GPIO Output */ + return ARM_DRIVER_ERROR; + } + NRF_GPIO->OUTSET = (1U << RTE_USART0_RTS_PIN_NUM); +#else + return ARM_DRIVER_ERROR; +#endif + } else { + /* Hardware controlled RTS */ + return ARM_DRIVER_ERROR; + } + break; + case ARM_USART_RTS_SET: + if ((flow_control == ARM_USART_FLOW_CONTROL_NONE) || + (flow_control == ARM_USART_FLOW_CONTROL_CTS)) { +#if (RTE_USART0_RTS_EN != 0U) + if ((rts_gpio_cnf == 0U) || + (rts_gpio_cnf > 328U) || + ((NRF_GPIOTE->CONFIG[rts_gpio_cnf-1U] & 1) != 1U)) { + /* If RTS pin is not configured as GPIO Output */ + return ARM_DRIVER_ERROR; + } + NRF_GPIO->OUTCLR = (1U << RTE_USART0_RTS_PIN_NUM); +#else + return ARM_DRIVER_ERROR; +#endif + } else { + /* Hardware controlled RTS */ + return ARM_DRIVER_ERROR; + } + break; + case ARM_USART_DTR_CLEAR: + case ARM_USART_DTR_SET: + return ARM_DRIVER_ERROR_UNSUPPORTED; + default: + return ARM_DRIVER_ERROR_PARAMETER; + } + + return ARM_DRIVER_OK; +} + +/** + \fn ARM_USART_MODEM_STATUS USART_GetModemStatus (void) + \brief Get USART Modem Status lines state. + \return modem status \ref ARM_USART_MODEM_STATUS +*/ +static ARM_USART_MODEM_STATUS USART_GetModemStatus (void) { + ARM_USART_MODEM_STATUS modem_status; + + modem_status.cts = 0U; + if ((flow_control == ARM_USART_FLOW_CONTROL_NONE) || + (flow_control == ARM_USART_FLOW_CONTROL_RTS)) { +#if (RTE_USART0_CTS_EN != 0U) + if ((cts_gpio_cnf != 0U) || + (cts_gpio_cnf <= 32U) || + ((NRF_GPIOTE->CONFIG[cts_gpio_cnf-1U] & 3) == 0U)) { + /* If CTS pin is configured as GPIO Input */ + if ((NRF_GPIO->IN & (1U << RTE_USART0_RTS_PIN_NUM)) == 0U) { + modem_status.cts = 1U; + } + } +#endif + } + modem_status.dsr = 0U; + modem_status.dcd = 0U; + modem_status.ri = 0U; + modem_status.reserved = 0U; + + return modem_status; +} + + +/** + \fn void UARTE0_UART0_IRQHandler (void) + \brief USART Interrupt handler. +*/ +void UARTE0_UART0_IRQHandler (void) { + uint32_t events, error_src, num_to_send, num_sent; + + events = 0U; + + /* Handle transmission interrupt */ + if (NRF_UARTE0->EVENTS_ENDTX != 0U) { + NRF_UARTE0->EVENTS_ENDTX = 0U; + num_sent = NRF_UARTE0->TXD.AMOUNT; + tx_cnt += num_sent; + ptr_tx_data += num_sent; + if (tx_cnt < tx_num) { + num_to_send = tx_num - tx_cnt; + if (num_to_send > sizeof(tx_buf)) { + num_to_send = sizeof(tx_buf); + } + + /* Still data to transmit, continue transmission */ + /* Copy data to intermediate Tx buffer (up to intermediate Tx buffer size) */ + memcpy(tx_buf, ptr_tx_data, num_to_send); + + /* Start transmission from intermediate Tx buffer */ + usart_dma_start(TX_DIR, tx_buf, num_to_send); + } else { + /* Disable ENDTX interrupt */ + NRF_UARTE0->INTENCLR = UARTE_INTENCLR_ENDTX_Msk; + + usart_status.tx_busy = 0U; + + events = ARM_USART_EVENT_SEND_COMPLETE | ARM_USART_EVENT_TX_COMPLETE; + } + } + + /* Handle reception interrupt */ + if (NRF_UARTE0->EVENTS_ENDRX != 0U) { + NRF_UARTE0->EVENTS_ENDRX = 0U; + NRF_UARTE0->INTENCLR = UARTE_INTENCLR_ENDRX_Msk; + usart_status.rx_busy = 0U; + events |= ARM_USART_EVENT_RECEIVE_COMPLETE; + } + + /* Handle reception timeout */ + if (NRF_UARTE0->EVENTS_RXTO != 0U) { + NRF_UARTE0->EVENTS_RXTO = 0U; + events |= ARM_USART_EVENT_RX_TIMEOUT; + } + + /* Handle break and error events */ + if (NRF_UARTE0->EVENTS_ERROR != 0U) { + error_src = NRF_UARTE0->ERRORSRC; + NRF_UARTE0->ERRORSRC = error_src; + NRF_UARTE0->EVENTS_ERROR = 0U; + if ((error_src & UART_ERRORSRC_BREAK_Msk) != 0U) { + events |= ARM_USART_EVENT_RX_BREAK; + } + if ((error_src & UART_ERRORSRC_FRAMING_Msk) != 0U) { + events |= ARM_USART_EVENT_RX_FRAMING_ERROR; + } + if ((error_src & UART_ERRORSRC_PARITY_Msk) != 0U) { + events |= ARM_USART_EVENT_RX_PARITY_ERROR; + } + if ((error_src & UART_ERRORSRC_OVERRUN_Msk) != 0U) { + events |= ARM_USART_EVENT_RX_OVERFLOW; + } + } + + /* Call SignalEvent function */ + if (fn_signal_event != NULL) { + fn_signal_event(events); + } +} + + +// USART0 Driver Control Block +extern \ +ARM_DRIVER_USART Driver_USART0; +ARM_DRIVER_USART Driver_USART0 = { + USART_GetVersion, + USART_GetCapabilities, + USART_Initialize, + USART_Uninitialize, + USART_PowerControl, + USART_Send, + USART_Receive, + USART_Transfer, + USART_GetTxCount, + USART_GetRxCount, + USART_Control, + USART_GetStatus, + USART_SetModemControl, + USART_GetModemStatus +}; diff --git a/source/hic_hal/nordic/nrf52820/USART_nRF52820.h b/source/hic_hal/nordic/nrf52820/USART_nRF52820.h new file mode 100644 index 000000000..491dde9b1 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/USART_nRF52820.h @@ -0,0 +1,49 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2021 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 16. July 2021 + * $Revision: V1.0 + * + * Project: USART Driver definitions for Nordic Semiconductor nRF52820 + * -------------------------------------------------------------------------- */ + +#ifndef __USART_nRF52820_H +#define __USART_nRF52820_H + +#include +#include +#include + +#include "Driver_USART.h" + +#include "nrf.h" // Device header +#include "nrf52_erratas.h" + +#include "RTE_Device.h" + +// USART flags +#define USART_FLAG_INITIALIZED (1U) +#define USART_FLAG_POWERED (1U << 1) +#define USART_FLAG_CONFIGURED (1U << 2) + +// USART direction +#define RX_DIR (0U) +#define TX_DIR (1U) + +#endif /* __USART_nRF52820_H */ From 8362c5ddafc2d204bf9e2e39d65ad44ed660d242 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 20 Jul 2021 12:40:18 +0200 Subject: [PATCH 417/617] nrf52820_hic: add CMSIS Driver headers + gcc compilation fix --- .../hic_hal/nordic/nrf52820/Driver_Common.h | 69 ++++ source/hic_hal/nordic/nrf52820/Driver_USART.h | 341 ++++++++++++++++++ .../hic_hal/nordic/nrf52820/USART_nRF52820.c | 36 +- 3 files changed, 428 insertions(+), 18 deletions(-) create mode 100644 source/hic_hal/nordic/nrf52820/Driver_Common.h create mode 100644 source/hic_hal/nordic/nrf52820/Driver_USART.h diff --git a/source/hic_hal/nordic/nrf52820/Driver_Common.h b/source/hic_hal/nordic/nrf52820/Driver_Common.h new file mode 100644 index 000000000..59d5b759c --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/Driver_Common.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 2. Feb 2017 + * $Revision: V2.0 + * + * Project: Common Driver definitions + */ + +/* History: + * Version 2.0 + * Changed prefix ARM_DRV -> ARM_DRIVER + * Added General return codes definitions + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.00 + * Initial release + */ + +#ifndef DRIVER_COMMON_H_ +#define DRIVER_COMMON_H_ + +#include +#include +#include + +#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor)) + +/** +\brief Driver Version +*/ +typedef struct _ARM_DRIVER_VERSION { + uint16_t api; ///< API version + uint16_t drv; ///< Driver version +} ARM_DRIVER_VERSION; + +/* General return codes */ +#define ARM_DRIVER_OK 0 ///< Operation succeeded +#define ARM_DRIVER_ERROR -1 ///< Unspecified error +#define ARM_DRIVER_ERROR_BUSY -2 ///< Driver is busy +#define ARM_DRIVER_ERROR_TIMEOUT -3 ///< Timeout occurred +#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported +#define ARM_DRIVER_ERROR_PARAMETER -5 ///< Parameter error +#define ARM_DRIVER_ERROR_SPECIFIC -6 ///< Start of driver specific errors + +/** +\brief General power states +*/ +typedef enum _ARM_POWER_STATE { + ARM_POWER_OFF, ///< Power off: no operation possible + ARM_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events + ARM_POWER_FULL ///< Power on: full operation at maximum performance +} ARM_POWER_STATE; + +#endif /* DRIVER_COMMON_H_ */ diff --git a/source/hic_hal/nordic/nrf52820/Driver_USART.h b/source/hic_hal/nordic/nrf52820/Driver_USART.h new file mode 100644 index 000000000..e60bf51a3 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/Driver_USART.h @@ -0,0 +1,341 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 2. Feb 2017 + * $Revision: V2.3 + * + * Project: USART (Universal Synchronous Asynchronous Receiver Transmitter) + * Driver definitions + */ + +/* History: + * Version 2.3 + * ARM_USART_STATUS and ARM_USART_MODEM_STATUS made volatile + * Version 2.2 + * Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions + * Version 2.1 + * Removed optional argument parameter from Signal Event + * Version 2.0 + * New simplified driver: + * complexity moved to upper layer (especially data handling) + * more unified API for different communication interfaces + * renamed driver UART -> USART (Asynchronous & Synchronous) + * Added modes: + * Synchronous + * Single-wire + * IrDA + * Smart Card + * Changed prefix ARM_DRV -> ARM_DRIVER + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.01 + * Added events: + * ARM_UART_EVENT_TX_EMPTY, ARM_UART_EVENT_RX_TIMEOUT + * ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD + * Added functions: SetTxThreshold, SetRxThreshold + * Added "rx_timeout_event" to capabilities + * Version 1.00 + * Initial release + */ + +#ifndef DRIVER_USART_H_ +#define DRIVER_USART_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "Driver_Common.h" + +#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */ + + +/****** USART Control Codes *****/ + +#define ARM_USART_CONTROL_Pos 0 +#define ARM_USART_CONTROL_Msk (0xFFUL << ARM_USART_CONTROL_Pos) + +/*----- USART Control Codes: Mode -----*/ +#define ARM_USART_MODE_ASYNCHRONOUS (0x01UL << ARM_USART_CONTROL_Pos) ///< UART (Asynchronous); arg = Baudrate +#define ARM_USART_MODE_SYNCHRONOUS_MASTER (0x02UL << ARM_USART_CONTROL_Pos) ///< Synchronous Master (generates clock signal); arg = Baudrate +#define ARM_USART_MODE_SYNCHRONOUS_SLAVE (0x03UL << ARM_USART_CONTROL_Pos) ///< Synchronous Slave (external clock signal) +#define ARM_USART_MODE_SINGLE_WIRE (0x04UL << ARM_USART_CONTROL_Pos) ///< UART Single-wire (half-duplex); arg = Baudrate +#define ARM_USART_MODE_IRDA (0x05UL << ARM_USART_CONTROL_Pos) ///< UART IrDA; arg = Baudrate +#define ARM_USART_MODE_SMART_CARD (0x06UL << ARM_USART_CONTROL_Pos) ///< UART Smart Card; arg = Baudrate + +/*----- USART Control Codes: Mode Parameters: Data Bits -----*/ +#define ARM_USART_DATA_BITS_Pos 8 +#define ARM_USART_DATA_BITS_Msk (7UL << ARM_USART_DATA_BITS_Pos) +#define ARM_USART_DATA_BITS_5 (5UL << ARM_USART_DATA_BITS_Pos) ///< 5 Data bits +#define ARM_USART_DATA_BITS_6 (6UL << ARM_USART_DATA_BITS_Pos) ///< 6 Data bit +#define ARM_USART_DATA_BITS_7 (7UL << ARM_USART_DATA_BITS_Pos) ///< 7 Data bits +#define ARM_USART_DATA_BITS_8 (0UL << ARM_USART_DATA_BITS_Pos) ///< 8 Data bits (default) +#define ARM_USART_DATA_BITS_9 (1UL << ARM_USART_DATA_BITS_Pos) ///< 9 Data bits + +/*----- USART Control Codes: Mode Parameters: Parity -----*/ +#define ARM_USART_PARITY_Pos 12 +#define ARM_USART_PARITY_Msk (3UL << ARM_USART_PARITY_Pos) +#define ARM_USART_PARITY_NONE (0UL << ARM_USART_PARITY_Pos) ///< No Parity (default) +#define ARM_USART_PARITY_EVEN (1UL << ARM_USART_PARITY_Pos) ///< Even Parity +#define ARM_USART_PARITY_ODD (2UL << ARM_USART_PARITY_Pos) ///< Odd Parity + +/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/ +#define ARM_USART_STOP_BITS_Pos 14 +#define ARM_USART_STOP_BITS_Msk (3UL << ARM_USART_STOP_BITS_Pos) +#define ARM_USART_STOP_BITS_1 (0UL << ARM_USART_STOP_BITS_Pos) ///< 1 Stop bit (default) +#define ARM_USART_STOP_BITS_2 (1UL << ARM_USART_STOP_BITS_Pos) ///< 2 Stop bits +#define ARM_USART_STOP_BITS_1_5 (2UL << ARM_USART_STOP_BITS_Pos) ///< 1.5 Stop bits +#define ARM_USART_STOP_BITS_0_5 (3UL << ARM_USART_STOP_BITS_Pos) ///< 0.5 Stop bits + +/*----- USART Control Codes: Mode Parameters: Flow Control -----*/ +#define ARM_USART_FLOW_CONTROL_Pos 16 +#define ARM_USART_FLOW_CONTROL_Msk (3UL << ARM_USART_FLOW_CONTROL_Pos) +#define ARM_USART_FLOW_CONTROL_NONE (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default) +#define ARM_USART_FLOW_CONTROL_RTS (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control +#define ARM_USART_FLOW_CONTROL_CTS (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control +#define ARM_USART_FLOW_CONTROL_RTS_CTS (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control + +/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/ +#define ARM_USART_CPOL_Pos 18 +#define ARM_USART_CPOL_Msk (1UL << ARM_USART_CPOL_Pos) +#define ARM_USART_CPOL0 (0UL << ARM_USART_CPOL_Pos) ///< CPOL = 0 (default) +#define ARM_USART_CPOL1 (1UL << ARM_USART_CPOL_Pos) ///< CPOL = 1 + +/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/ +#define ARM_USART_CPHA_Pos 19 +#define ARM_USART_CPHA_Msk (1UL << ARM_USART_CPHA_Pos) +#define ARM_USART_CPHA0 (0UL << ARM_USART_CPHA_Pos) ///< CPHA = 0 (default) +#define ARM_USART_CPHA1 (1UL << ARM_USART_CPHA_Pos) ///< CPHA = 1 + + +/*----- USART Control Codes: Miscellaneous Controls -----*/ +#define ARM_USART_SET_DEFAULT_TX_VALUE (0x10UL << ARM_USART_CONTROL_Pos) ///< Set default Transmit value (Synchronous Receive only); arg = value +#define ARM_USART_SET_IRDA_PULSE (0x11UL << ARM_USART_CONTROL_Pos) ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period +#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Guard Time; arg = number of bit periods +#define ARM_USART_SET_SMART_CARD_CLOCK (0x13UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated +#define ARM_USART_CONTROL_SMART_CARD_NACK (0x14UL << ARM_USART_CONTROL_Pos) ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled +#define ARM_USART_CONTROL_TX (0x15UL << ARM_USART_CONTROL_Pos) ///< Transmitter; arg: 0=disabled, 1=enabled +#define ARM_USART_CONTROL_RX (0x16UL << ARM_USART_CONTROL_Pos) ///< Receiver; arg: 0=disabled, 1=enabled +#define ARM_USART_CONTROL_BREAK (0x17UL << ARM_USART_CONTROL_Pos) ///< Continuous Break transmission; arg: 0=disabled, 1=enabled +#define ARM_USART_ABORT_SEND (0x18UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Send +#define ARM_USART_ABORT_RECEIVE (0x19UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Receive +#define ARM_USART_ABORT_TRANSFER (0x1AUL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Transfer + + + +/****** USART specific error codes *****/ +#define ARM_USART_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported +#define ARM_USART_ERROR_BAUDRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified baudrate not supported +#define ARM_USART_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported +#define ARM_USART_ERROR_PARITY (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Parity not supported +#define ARM_USART_ERROR_STOP_BITS (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified number of Stop bits not supported +#define ARM_USART_ERROR_FLOW_CONTROL (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Flow Control not supported +#define ARM_USART_ERROR_CPOL (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock Polarity not supported +#define ARM_USART_ERROR_CPHA (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Clock Phase not supported + + +/** +\brief USART Status +*/ +typedef volatile struct _ARM_USART_STATUS { + uint32_t tx_busy : 1; ///< Transmitter busy flag + uint32_t rx_busy : 1; ///< Receiver busy flag + uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation) + uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation) + uint32_t rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation) + uint32_t rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation) + uint32_t rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation) + uint32_t reserved : 25; +} ARM_USART_STATUS; + +/** +\brief USART Modem Control +*/ +typedef enum _ARM_USART_MODEM_CONTROL { + ARM_USART_RTS_CLEAR, ///< Deactivate RTS + ARM_USART_RTS_SET, ///< Activate RTS + ARM_USART_DTR_CLEAR, ///< Deactivate DTR + ARM_USART_DTR_SET ///< Activate DTR +} ARM_USART_MODEM_CONTROL; + +/** +\brief USART Modem Status +*/ +typedef volatile struct _ARM_USART_MODEM_STATUS { + uint32_t cts : 1; ///< CTS state: 1=Active, 0=Inactive + uint32_t dsr : 1; ///< DSR state: 1=Active, 0=Inactive + uint32_t dcd : 1; ///< DCD state: 1=Active, 0=Inactive + uint32_t ri : 1; ///< RI state: 1=Active, 0=Inactive + uint32_t reserved : 28; +} ARM_USART_MODEM_STATUS; + + +/****** USART Event *****/ +#define ARM_USART_EVENT_SEND_COMPLETE (1UL << 0) ///< Send completed; however USART may still transmit data +#define ARM_USART_EVENT_RECEIVE_COMPLETE (1UL << 1) ///< Receive completed +#define ARM_USART_EVENT_TRANSFER_COMPLETE (1UL << 2) ///< Transfer completed +#define ARM_USART_EVENT_TX_COMPLETE (1UL << 3) ///< Transmit completed (optional) +#define ARM_USART_EVENT_TX_UNDERFLOW (1UL << 4) ///< Transmit data not available (Synchronous Slave) +#define ARM_USART_EVENT_RX_OVERFLOW (1UL << 5) ///< Receive data overflow +#define ARM_USART_EVENT_RX_TIMEOUT (1UL << 6) ///< Receive character timeout (optional) +#define ARM_USART_EVENT_RX_BREAK (1UL << 7) ///< Break detected on receive +#define ARM_USART_EVENT_RX_FRAMING_ERROR (1UL << 8) ///< Framing error detected on receive +#define ARM_USART_EVENT_RX_PARITY_ERROR (1UL << 9) ///< Parity error detected on receive +#define ARM_USART_EVENT_CTS (1UL << 10) ///< CTS state changed (optional) +#define ARM_USART_EVENT_DSR (1UL << 11) ///< DSR state changed (optional) +#define ARM_USART_EVENT_DCD (1UL << 12) ///< DCD state changed (optional) +#define ARM_USART_EVENT_RI (1UL << 13) ///< RI state changed (optional) + + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_USART_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION + + \fn ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void) + \brief Get driver capabilities + \return \ref ARM_USART_CAPABILITIES + + \fn int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event) + \brief Initialize USART Interface. + \param[in] cb_event Pointer to \ref ARM_USART_SignalEvent + \return \ref execution_status + + \fn int32_t ARM_USART_Uninitialize (void) + \brief De-initialize USART Interface. + \return \ref execution_status + + \fn int32_t ARM_USART_PowerControl (ARM_POWER_STATE state) + \brief Control USART Interface Power. + \param[in] state Power state + \return \ref execution_status + + \fn int32_t ARM_USART_Send (const void *data, uint32_t num) + \brief Start sending data to USART transmitter. + \param[in] data Pointer to buffer with data to send to USART transmitter + \param[in] num Number of data items to send + \return \ref execution_status + + \fn int32_t ARM_USART_Receive (void *data, uint32_t num) + \brief Start receiving data from USART receiver. + \param[out] data Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to receive + \return \ref execution_status + + \fn int32_t ARM_USART_Transfer (const void *data_out, + void *data_in, + uint32_t num) + \brief Start sending/receiving data to/from USART transmitter/receiver. + \param[in] data_out Pointer to buffer with data to send to USART transmitter + \param[out] data_in Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to transfer + \return \ref execution_status + + \fn uint32_t ARM_USART_GetTxCount (void) + \brief Get transmitted data count. + \return number of data items transmitted + + \fn uint32_t ARM_USART_GetRxCount (void) + \brief Get received data count. + \return number of data items received + + \fn int32_t ARM_USART_Control (uint32_t control, uint32_t arg) + \brief Control USART Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \return common \ref execution_status and driver specific \ref usart_execution_status + + \fn ARM_USART_STATUS ARM_USART_GetStatus (void) + \brief Get USART status. + \return USART status \ref ARM_USART_STATUS + + \fn int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control) + \brief Set USART Modem Control line state. + \param[in] control \ref ARM_USART_MODEM_CONTROL + \return \ref execution_status + + \fn ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void) + \brief Get USART Modem Status lines state. + \return modem status \ref ARM_USART_MODEM_STATUS + + \fn void ARM_USART_SignalEvent (uint32_t event) + \brief Signal USART Events. + \param[in] event \ref USART_events notification mask + \return none +*/ + +typedef void (*ARM_USART_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event. + + +/** +\brief USART Device Driver Capabilities. +*/ +typedef struct _ARM_USART_CAPABILITIES { + uint32_t asynchronous : 1; ///< supports UART (Asynchronous) mode + uint32_t synchronous_master : 1; ///< supports Synchronous Master mode + uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode + uint32_t single_wire : 1; ///< supports UART Single-wire mode + uint32_t irda : 1; ///< supports UART IrDA mode + uint32_t smart_card : 1; ///< supports UART Smart Card mode + uint32_t smart_card_clock : 1; ///< Smart Card Clock generator available + uint32_t flow_control_rts : 1; ///< RTS Flow Control available + uint32_t flow_control_cts : 1; ///< CTS Flow Control available + uint32_t event_tx_complete : 1; ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE + uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT + uint32_t rts : 1; ///< RTS Line: 0=not available, 1=available + uint32_t cts : 1; ///< CTS Line: 0=not available, 1=available + uint32_t dtr : 1; ///< DTR Line: 0=not available, 1=available + uint32_t dsr : 1; ///< DSR Line: 0=not available, 1=available + uint32_t dcd : 1; ///< DCD Line: 0=not available, 1=available + uint32_t ri : 1; ///< RI Line: 0=not available, 1=available + uint32_t event_cts : 1; ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS + uint32_t event_dsr : 1; ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR + uint32_t event_dcd : 1; ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD + uint32_t event_ri : 1; ///< Signal RI change event: \ref ARM_USART_EVENT_RI + uint32_t reserved : 11; ///< Reserved (must be zero) +} ARM_USART_CAPABILITIES; + + +/** +\brief Access structure of the USART Driver. +*/ +typedef struct _ARM_DRIVER_USART { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USART_GetVersion : Get driver version. + ARM_USART_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_USART_SignalEvent_t cb_event); ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power. + int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter. + int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver. + int32_t (*Transfer) (const void *data_out, + void *data_in, + uint32_t num); ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART. + uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count. + uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count. + int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_USART_Control : Control USART Interface. + ARM_USART_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_USART_GetStatus : Get USART status. + int32_t (*SetModemControl) (ARM_USART_MODEM_CONTROL control); ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state. + ARM_USART_MODEM_STATUS (*GetModemStatus) (void); ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state. +} const ARM_DRIVER_USART; + +#ifdef __cplusplus +} +#endif + +#endif /* DRIVER_USART_H_ */ diff --git a/source/hic_hal/nordic/nrf52820/USART_nRF52820.c b/source/hic_hal/nordic/nrf52820/USART_nRF52820.c index 04792d7b9..444c7683d 100644 --- a/source/hic_hal/nordic/nrf52820/USART_nRF52820.c +++ b/source/hic_hal/nordic/nrf52820/USART_nRF52820.c @@ -1,5 +1,5 @@ /* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2021 Arm Limited (or its affiliates). All + * Copyright (c) 2013-2021 Arm Limited (or its affiliates). All * rights reserved. * * SPDX-License-Identifier: Apache-2.0 @@ -47,7 +47,7 @@ #define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */ /* Driver Version */ -static const ARM_DRIVER_VERSION driver_version = { +static const ARM_DRIVER_VERSION driver_version = { ARM_USART_API_VERSION, ARM_USART_DRV_VERSION }; @@ -90,7 +90,7 @@ static void *ptr_tx_data = NULL; // Pointer to data for transmission static uint32_t tx_num = 0U; // Number of bytes requested for transmission static uint32_t rx_num = 0U; // Number of bytes requested for reception static uint32_t tx_cnt = 0U; // Number of transmitted bytes -static uint32_t tx_buf[32/4]; // Intermediate RAM buffer for transmission +static uint32_t tx_buf[32/4]; // Intermediate RAM buffer for transmission // (EasyDMA cannot transmit from flash directly) /* Function prototypes */ @@ -230,8 +230,8 @@ static int32_t USART_PowerControl (ARM_POWER_STATE state) { return ARM_DRIVER_ERROR; } - if ((state != ARM_POWER_OFF) && - (state != ARM_POWER_FULL) && + if ((state != ARM_POWER_OFF) && + (state != ARM_POWER_FULL) && (state != ARM_POWER_LOW)) { return ARM_DRIVER_ERROR_PARAMETER; } @@ -254,7 +254,7 @@ static int32_t USART_PowerControl (ARM_POWER_STATE state) { USART_Control(ARM_USART_ABORT_RECEIVE, 0U); /* Clear variables */ - memset(&usart_status, 0, sizeof(ARM_USART_STATUS)); + memset((void *) &usart_status, 0, sizeof(ARM_USART_STATUS)); ptr_tx_data = NULL; tx_num = 0U; rx_num = 0U; @@ -273,7 +273,7 @@ static int32_t USART_PowerControl (ARM_POWER_STATE state) { } /* Clear variables */ - memset(&usart_status, 0, sizeof(ARM_USART_STATUS)); + memset((void *) &usart_status, 0, sizeof(ARM_USART_STATUS)); ptr_tx_data = NULL; tx_num = 0U; rx_num = 0U; @@ -408,7 +408,7 @@ static int32_t USART_Control (uint32_t control, uint32_t arg) { case ARM_USART_DATA_BITS_7: case ARM_USART_DATA_BITS_9: default: - return ARM_USART_ERROR_DATA_BITS; + return ARM_USART_ERROR_DATA_BITS; } /* Configure parity */ @@ -425,7 +425,7 @@ static int32_t USART_Control (uint32_t control, uint32_t arg) { NRF_UARTE0->CONFIG &= ~UARTE_CONFIG_PARITY_Msk; break; default: - return ARM_USART_ERROR_PARITY; + return ARM_USART_ERROR_PARITY; } /* Configure stop bits */ @@ -439,7 +439,7 @@ static int32_t USART_Control (uint32_t control, uint32_t arg) { case ARM_USART_STOP_BITS_1_5: case ARM_USART_STOP_BITS_0_5: default: - return ARM_USART_ERROR_STOP_BITS; + return ARM_USART_ERROR_STOP_BITS; } /* Configure flow control */ @@ -483,7 +483,7 @@ static int32_t USART_Control (uint32_t control, uint32_t arg) { case ARM_USART_FLOW_CONTROL_CTS: case ARM_USART_FLOW_CONTROL_RTS: default: - return ARM_USART_ERROR_FLOW_CONTROL; + return ARM_USART_ERROR_FLOW_CONTROL; } /* Ignore clock polarity and clock phase setting */ @@ -692,8 +692,8 @@ static int32_t USART_SetModemControl (ARM_USART_MODEM_CONTROL control) { if ((flow_control == ARM_USART_FLOW_CONTROL_NONE) || (flow_control == ARM_USART_FLOW_CONTROL_CTS)) { #if (RTE_USART0_RTS_EN != 0U) - if ((rts_gpio_cnf == 0U) || - (rts_gpio_cnf > 328U) || + if ((rts_gpio_cnf == 0U) || + (rts_gpio_cnf > 328U) || ((NRF_GPIOTE->CONFIG[rts_gpio_cnf-1U] & 1) != 1U)) { /* If RTS pin is not configured as GPIO Output */ return ARM_DRIVER_ERROR; @@ -711,8 +711,8 @@ static int32_t USART_SetModemControl (ARM_USART_MODEM_CONTROL control) { if ((flow_control == ARM_USART_FLOW_CONTROL_NONE) || (flow_control == ARM_USART_FLOW_CONTROL_CTS)) { #if (RTE_USART0_RTS_EN != 0U) - if ((rts_gpio_cnf == 0U) || - (rts_gpio_cnf > 328U) || + if ((rts_gpio_cnf == 0U) || + (rts_gpio_cnf > 328U) || ((NRF_GPIOTE->CONFIG[rts_gpio_cnf-1U] & 1) != 1U)) { /* If RTS pin is not configured as GPIO Output */ return ARM_DRIVER_ERROR; @@ -748,8 +748,8 @@ static ARM_USART_MODEM_STATUS USART_GetModemStatus (void) { if ((flow_control == ARM_USART_FLOW_CONTROL_NONE) || (flow_control == ARM_USART_FLOW_CONTROL_RTS)) { #if (RTE_USART0_CTS_EN != 0U) - if ((cts_gpio_cnf != 0U) || - (cts_gpio_cnf <= 32U) || + if ((cts_gpio_cnf != 0U) || + (cts_gpio_cnf <= 32U) || ((NRF_GPIOTE->CONFIG[cts_gpio_cnf-1U] & 3) == 0U)) { /* If CTS pin is configured as GPIO Input */ if ((NRF_GPIO->IN & (1U << RTE_USART0_RTS_PIN_NUM)) == 0U) { @@ -757,7 +757,7 @@ static ARM_USART_MODEM_STATUS USART_GetModemStatus (void) { } } #endif - } + } modem_status.dsr = 0U; modem_status.dcd = 0U; modem_status.ri = 0U; From f6a9df13112a3e189687e5c085989a42f89eb9b9 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 20 Jul 2021 12:47:17 +0200 Subject: [PATCH 418/617] nrf52820_hic: connect CMSIS Driver to DAPLink UART Based on lpc55xx code --- source/hic_hal/nordic/nrf52820/uart.c | 167 +++++++++++++++++++++++++- 1 file changed, 165 insertions(+), 2 deletions(-) diff --git a/source/hic_hal/nordic/nrf52820/uart.c b/source/hic_hal/nordic/nrf52820/uart.c index e488410b5..2504700da 100644 --- a/source/hic_hal/nordic/nrf52820/uart.c +++ b/source/hic_hal/nordic/nrf52820/uart.c @@ -19,40 +19,203 @@ * limitations under the License. */ +#include "string.h" +#include "Driver_USART.h" #include "uart.h" +#include "util.h" +#include "cortex_m.h" +#include "circ_buf.h" +#include "settings.h" // for config_get_overflow_detect + +#define USART_INSTANCE (Driver_USART0) +#define USART_IRQ (UARTE0_UART0_IRQn) + +extern ARM_DRIVER_USART USART_INSTANCE; +extern uint32_t SystemCoreClock; + +static void clear_buffers(void); + +#define RX_OVRF_MSG "\n" +#define RX_OVRF_MSG_SIZE (sizeof(RX_OVRF_MSG) - 1) +#define BUFFER_SIZE (512) + +circ_buf_t write_buffer; +uint8_t write_buffer_data[BUFFER_SIZE]; +circ_buf_t read_buffer; +uint8_t read_buffer_data[BUFFER_SIZE]; + +struct { + uint8_t rx; + uint8_t tx; +} cb_buf; + +void uart_handler(uint32_t event); + +void clear_buffers(void) +{ + circ_buf_init(&write_buffer, write_buffer_data, sizeof(write_buffer_data)); + circ_buf_init(&read_buffer, read_buffer_data, sizeof(read_buffer_data)); +} int32_t uart_initialize(void) { + clear_buffers(); + Driver_USART0.Initialize(uart_handler); + + return 1; } int32_t uart_uninitialize(void) { + USART_INSTANCE.Control(ARM_USART_CONTROL_RX, 0); + Driver_USART0.Uninitialize(); + clear_buffers(); + + return 1; } int32_t uart_reset(void) { + // disable interrupt + NVIC_DisableIRQ(USART_IRQ); + clear_buffers(); + // enable interrupt + NVIC_EnableIRQ(USART_IRQ); + + return 1; } int32_t uart_set_configuration(UART_Configuration *config) { + uint32_t control = ARM_USART_MODE_ASYNCHRONOUS; + + switch (config->DataBits) { + case UART_DATA_BITS_5: + control |= UART_DATA_BITS_5; + break; + + case UART_DATA_BITS_6: + control |= ARM_USART_DATA_BITS_6; + break; + + case UART_DATA_BITS_7: + control |= ARM_USART_DATA_BITS_6; + break; + + case UART_DATA_BITS_8: /* fallthrough */ + default: + control |= ARM_USART_DATA_BITS_8; + break; + } + + switch (config->Parity) { + case UART_PARITY_EVEN: + control |= ARM_USART_PARITY_EVEN; + break; + + case UART_PARITY_ODD: + control |= ARM_USART_PARITY_ODD; + break; + + case UART_PARITY_NONE: /* fallthrough */ + default: + control |= ARM_USART_PARITY_NONE; + break; + } + + switch (config->StopBits) { + case UART_STOP_BITS_1: /* fallthrough */ + default: + control |= ARM_USART_STOP_BITS_1; + break; + + case UART_STOP_BITS_1_5: + control |= ARM_USART_STOP_BITS_1_5; + break; + + case UART_STOP_BITS_2: + control |= ARM_USART_STOP_BITS_2; + break; + } + + switch (config->FlowControl) { + case UART_FLOW_CONTROL_NONE: /* fallthrough */ + default: + control |= ARM_USART_FLOW_CONTROL_NONE; + break; + + case UART_FLOW_CONTROL_RTS_CTS: + control |= ARM_USART_FLOW_CONTROL_RTS_CTS; + break; + } + + NVIC_DisableIRQ(USART_IRQ); + clear_buffers(); + uint32_t r = USART_INSTANCE.Control(control, config->Baudrate); + if (r != ARM_DRIVER_OK) { + return 0; + } + USART_INSTANCE.Control(ARM_USART_CONTROL_TX, 1); + USART_INSTANCE.Control(ARM_USART_CONTROL_RX, 1); + USART_INSTANCE.Receive(&(cb_buf.rx), 1); + + NVIC_ClearPendingIRQ(USART_IRQ); + NVIC_EnableIRQ(USART_IRQ); + + return 1; } int32_t uart_get_configuration(UART_Configuration *config) { + return 1; } int32_t uart_write_free(void) { + return circ_buf_count_free(&write_buffer); } int32_t uart_write_data(uint8_t *data, uint16_t size) { + if (size == 0) { + return 0; + } + + uint32_t cnt = 0; + if (circ_buf_count_used(&write_buffer) > 0) { + cb_buf.tx = circ_buf_pop(&write_buffer); + cnt = circ_buf_write(&write_buffer, data, size); + } else { + cb_buf.tx = data[0]; + cnt = circ_buf_write(&write_buffer, data + 1, size - 1) + 1; + } + USART_INSTANCE.Send(&(cb_buf.tx), 1); + + return cnt; } int32_t uart_read_data(uint8_t *data, uint16_t size) { + return circ_buf_read(&read_buffer, data, size); } -void CDC_UART_IRQn_Handler(void) -{ +void uart_handler(uint32_t event) { + if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) { + uint32_t free = circ_buf_count_free(&read_buffer); + if (free > RX_OVRF_MSG_SIZE) { + circ_buf_push(&read_buffer, cb_buf.rx); + } else if ((RX_OVRF_MSG_SIZE == free) && config_get_overflow_detect()) { + circ_buf_write(&read_buffer, (uint8_t*)RX_OVRF_MSG, RX_OVRF_MSG_SIZE); + } else { + // Drop character + } + USART_INSTANCE.Receive(&(cb_buf.rx), 1); + } + + if (event & ARM_USART_EVENT_SEND_COMPLETE) { + if (circ_buf_count_used(&write_buffer) > 0) { + cb_buf.tx = circ_buf_pop(&write_buffer); + USART_INSTANCE.Send(&(cb_buf.tx), 1); + } + } } From 8ac72740519881db51e32ac88aab081e48f9144b Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 20 Jul 2021 12:49:31 +0200 Subject: [PATCH 419/617] nrf52820_hic: Add missing DAP_config.h changes --- source/hic_hal/nordic/nrf52820/DAP_config.h | 45 +++++++++++++++------ 1 file changed, 33 insertions(+), 12 deletions(-) diff --git a/source/hic_hal/nordic/nrf52820/DAP_config.h b/source/hic_hal/nordic/nrf52820/DAP_config.h index d1f53766e..7996d7708 100644 --- a/source/hic_hal/nordic/nrf52820/DAP_config.h +++ b/source/hic_hal/nordic/nrf52820/DAP_config.h @@ -184,7 +184,20 @@ Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: - TDI, nTRST to HighZ mode (pins are unused in SWD mode). */ __STATIC_INLINE void PORT_SWD_SETUP (void) { - ; + nrf_gpio_cfg(PIN_SWDCLK, NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); + nrf_gpio_pin_set(PIN_SWDCLK); + nrf_gpio_cfg(PIN_SWDIO, NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); + nrf_gpio_pin_set(PIN_SWDIO); +#ifdef PIN_nRESET + nrf_gpio_cfg(PIN_nRESET, NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); + nrf_gpio_pin_set(PIN_nRESET); +#endif } /** Disable JTAG/SWD I/O Pins. @@ -192,7 +205,11 @@ Disables the DAP Hardware I/O pins which configures: - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode. */ __STATIC_INLINE void PORT_OFF (void) { - ; + nrf_gpio_cfg_input(PIN_SWDCLK, NRF_GPIO_PIN_NOPULL); + nrf_gpio_cfg_input(PIN_SWDIO, NRF_GPIO_PIN_NOPULL); +#ifdef PIN_nRESET + nrf_gpio_cfg_input(PIN_nRESET, NRF_GPIO_PIN_NOPULL); +#endif } @@ -202,21 +219,21 @@ __STATIC_INLINE void PORT_OFF (void) { \return Current status of the SWCLK/TCK DAP hardware I/O pin. */ __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) { - return (0U); + return nrf_gpio_pin_out_read(PIN_SWDCLK); } /** SWCLK/TCK I/O pin: Set Output to High. Set the SWCLK/TCK DAP hardware I/O pin to high level. */ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) { - ; + nrf_gpio_pin_set(PIN_SWDCLK); } /** SWCLK/TCK I/O pin: Set Output to Low. Set the SWCLK/TCK DAP hardware I/O pin to low level. */ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) { - ; + nrf_gpio_pin_clear(PIN_SWDCLK); } @@ -226,35 +243,39 @@ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) { \return Current status of the SWDIO/TMS DAP hardware I/O pin. */ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) { - return (0U); + return nrf_gpio_pin_read(PIN_SWDIO) & 0x1; } /** SWDIO/TMS I/O pin: Set Output to High. Set the SWDIO/TMS DAP hardware I/O pin to high level. */ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) { - ; + nrf_gpio_pin_set(PIN_SWDIO); } /** SWDIO/TMS I/O pin: Set Output to Low. Set the SWDIO/TMS DAP hardware I/O pin to low level. */ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) { - ; + nrf_gpio_pin_clear(PIN_SWDIO); } /** SWDIO I/O pin: Get Input (used in SWD mode only). \return Current status of the SWDIO DAP hardware I/O pin. */ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) { - return (0U); + return nrf_gpio_pin_read(PIN_SWDIO) & 0x1; } /** SWDIO I/O pin: Set Output (used in SWD mode only). \param bit Output value for the SWDIO DAP hardware I/O pin. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit) { - ; + if (bit & 0x1) { + nrf_gpio_pin_set(PIN_SWDIO); + } else { + nrf_gpio_pin_clear(PIN_SWDIO); + } } /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only). @@ -262,7 +283,7 @@ Configure the SWDIO DAP hardware I/O pin to output mode. This function is called prior \ref PIN_SWDIO_OUT function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) { - ; + nrf_gpio_pin_dir_set(PIN_SWDIO, NRF_GPIO_PIN_DIR_OUTPUT); } /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). @@ -270,7 +291,7 @@ Configure the SWDIO DAP hardware I/O pin to input mode. This function is called prior \ref PIN_SWDIO_IN function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) { - ; + nrf_gpio_pin_dir_set(PIN_SWDIO, NRF_GPIO_PIN_DIR_INPUT); } From d414d4300810e8db57482a2bf28842a91dd2fdf9 Mon Sep 17 00:00:00 2001 From: Russ Butler Date: Wed, 21 Jul 2021 17:34:57 -0500 Subject: [PATCH 420/617] Fix several USB bugs Major bugs are described below: - Control IN requests after a control OUT request are incorrectly handled as Control OUT. This is because 'ep0_dir', used to indicate if a control request is IN or OUT is latched to 0 in USBD_DirCtrlEP. This is fixed by always setting 'ep0_dir' in USBD_DirCtrlEP rather than latching it. - Control Device-To-Host transfers with more than than 63 bytes fail. This is because those transfers require multiple IN packets to be sent, but the status stage is entered after the first packet is sent. This is fixed by starting the status stage for control Device-To-Host transfers only after the last IN packet has been sent. The transmission of the last IN packet is known when the EVENTS_EP0DATADONE occurs after the variable 'ep0_status_next' has been set to 1. - Descriptor which have a size that are a multiple of 64 cause a stall when read. This is because data that is a multiple of 64 must be terminated with a ZLP (zero lenght packet), and the code in 'usbd_dma' incorrectly treats a ZLP as the status stage. This is fixed by starting the status stage of a control request without a data stage based on wlength being 0 rather than the size of a write. Additional Changes: - Ignore calls to USBD_WriteEP and USBD_ReadEP to start the control status stage. On the nrf52xxx this does not work. Instead it needs to be done with USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger. - Remove code in USBD_DirCtrlEP which started TASKS_EP0RCVOUT. This wasn't not having any effect. - Repalce USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Msk with USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger for consistency. These have the same value so this is only cosmetic. --- .../hic_hal/nordic/nrf52820/usbd_nRF528xx.c | 66 ++++++++++++++----- 1 file changed, 49 insertions(+), 17 deletions(-) diff --git a/source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c b/source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c index 0dba8c3d6..b4149616c 100644 --- a/source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c +++ b/source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c @@ -80,6 +80,8 @@ typedef struct { /* Endpoint configuration */ static OS_MUT usbd_hw_mutex; #endif static uint32_t setup_packet_available; +static uint32_t ep0_no_data_stage; +static uint32_t ep0_status_next; static uint32_t ep0_dir; static ep_config_t ep_config[2][USBD_EP_NUM_MAX]; static uint32_t ep_buf [2][USBD_EP_NUM_MAX][64/4]; @@ -145,32 +147,17 @@ void usbd_dma (uint32_t EPNum, uint32_t *buf, uint32_t cnt) { #endif if (ep_dir != 0U) { /* If IN endpoint */ - if ((ep_num == 0U) && (cnt == 0U)) { - /* Status stage send ZLP IN */ - NRF_USBD->TASKS_EP0STATUS = USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger; - } else { NRF_USBD->EPIN[ep_num].PTR = (uint32_t)buf; NRF_USBD->EPIN[ep_num].MAXCNT = len; NRF_USBD->TASKS_STARTEPIN[ep_num] = USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Trigger; while (NRF_USBD->EVENTS_ENDEPIN[ep_num] == 0U); NRF_USBD->EVENTS_ENDEPIN[ep_num] = 0U; - } } else { /* If OUT endpoint */ - if ((ep_num == 0U) && (cnt == 0U)) { - /* Status stage receive ZLP OUT */ - NRF_USBD->TASKS_EP0STATUS = USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger; - } else { NRF_USBD->EPOUT[ep_num].PTR = (uint32_t)buf; NRF_USBD->EPOUT[ep_num].MAXCNT = len; NRF_USBD->TASKS_STARTEPOUT[ep_num]= USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Trigger; while (NRF_USBD->EVENTS_ENDEPOUT[ep_num] == 0U); NRF_USBD->EVENTS_ENDEPOUT[ep_num] = 0U; - if ((ep_num == 0U) && (ep0_dir == 0U)) { - /* Allow OUT data stage on Control Endpoint 0 */ - NRF_USBD->TASKS_EP0RCVOUT = USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Msk; - NRF_USBD->TASKS_EP0STATUS = USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger; - } - } } #ifdef __RTX @@ -373,7 +360,8 @@ void USBD_ConfigEP (USB_ENDPOINT_DESCRIPTOR *pEPD) { void USBD_DirCtrlEP (uint32_t dir) { if (dir == 0U) { ep0_dir = 0U; - NRF_USBD->TASKS_EP0RCVOUT = USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Msk; + } else { + ep0_dir = 1U; } } @@ -574,8 +562,14 @@ uint32_t USBD_ReadEP (uint32_t EPNum, uint8_t *pData) { if (ep_dir != 0U) { /* If not OUT Endpoint */ return 0U; } + if ((ep_num == 0U) && (setup_packet_available == 0U) && (ep0_dir != 0)) { + /* Status stage of Device-to-Host handled in USBD_WriteEP */ + /* Note - ep0_dir is set only after the setup packet has been read */ + return 0U; + } if ((ep_num == 0U) && (setup_packet_available != 0U)) { + uint16_t wlength; setup_packet_available = 0U; /* If reading Endpoint 0 and Setup Packet is available */ @@ -588,6 +582,18 @@ uint32_t USBD_ReadEP (uint32_t EPNum, uint8_t *pData) { pData[6] = NRF_USBD->WLENGTHL; pData[7] = NRF_USBD->WLENGTHH; len = 8U; + + /* Start status stage immediately if there is no data stage */ + wlength = (pData[7] << 8) | (pData[6] << 0); + if (wlength == 0) { + ep0_no_data_stage = 1; + NRF_USBD->TASKS_EP0STATUS = USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger; + } else { + ep0_no_data_stage = 0; + } + } else if ((ep_num == 0U) && (ep0_no_data_stage != 0)) { + /* There isn't a data stage so don't try to read data */ + len = 0; } else { len = NRF_USBD->SIZE.EPOUT[ep_num]; @@ -603,6 +609,14 @@ uint32_t USBD_ReadEP (uint32_t EPNum, uint8_t *pData) { /* Copy data received to requested pData */ memcpy((void *)pData, (const void *)&ep_buf[ep_dir][ep_num][0], len); + + /* Start the status stage if endpoint 0 */ + if (ep_num == 0U) { + /* TODO - Only start the status stage after reading the last OUT packet. + Until that is done control Host-To-Device transfers consisting + of multiple OUT packets likely won't work. */ + NRF_USBD->TASKS_EP0STATUS = USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger; + } } /* Start OUT transfer (Receive data to USB controller's internal buffer) */ @@ -636,6 +650,14 @@ uint32_t USBD_WriteEP (uint32_t EPNum, uint8_t *pData, uint32_t cnt) { if (ep_dir == 0U) { /* If not IN Endpoint */ return 0U; } + if ((ep_num == 0U) && (ep0_no_data_stage != 0)) { + /* There isn't a data stage so don't try to write data */ + return 0U; + } + if ((ep_num == 0U) && (ep0_dir == 0)) { + /* Status stage of Host-to-Device handled elsewhere */ + return 0U; + } ep_max_len = ep_config[ep_dir][ep_num].max_packet_size; @@ -643,6 +665,12 @@ uint32_t USBD_WriteEP (uint32_t EPNum, uint8_t *pData, uint32_t cnt) { len = ep_max_len; } + /* If this is a short packet on endpoint 0 then it is the last packet + of the transfer. Start the status stage after it is sent (the next IN event) */ + if ((ep_num == 0U) && (len < ep_max_len)) { + ep0_status_next = 1U; + } + /* Copy data to be sent to ep_buf */ memcpy((void *)&ep_buf[ep_dir][ep_num][0], (const void *)pData, len); @@ -756,6 +784,7 @@ void USBD_IRQHandler (void) { /* Check Endpoint 0 Setup Packet received event */ if (NRF_USBD->EVENTS_EP0SETUP != 0U) { setup_packet_available = 1U; + ep0_status_next = 0U; NRF_USBD->EVENTS_EP0SETUP = 0U; #ifdef __RTX if (USBD_RTX_EPTask[0]) { @@ -770,6 +799,7 @@ void USBD_IRQHandler (void) { /* Check Endpoint 0 Data Packet sent/received event */ if (NRF_USBD->EVENTS_EP0DATADONE != 0U) { + uint32_t local_ep0_status_next = ep0_status_next; NRF_USBD->EVENTS_EP0DATADONE = 0U; #ifdef __RTX if (USBD_RTX_EPTask[0]) { @@ -789,7 +819,9 @@ void USBD_IRQHandler (void) { } #endif /* Enable Status stage */ - NRF_USBD->TASKS_EP0STATUS = USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Msk; + if (local_ep0_status_next) { + NRF_USBD->TASKS_EP0STATUS = USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger; + } } /* Check Endpoint sent/received event */ From 3d67cd0e690549622d259d6f37287df889e84fdc Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 21 Jul 2021 23:46:20 -0500 Subject: [PATCH 421/617] nrf52820_hic: UART fix from @c1728p9 --- source/hic_hal/nordic/nrf52820/uart.c | 1 + 1 file changed, 1 insertion(+) diff --git a/source/hic_hal/nordic/nrf52820/uart.c b/source/hic_hal/nordic/nrf52820/uart.c index 2504700da..ce85b15f9 100644 --- a/source/hic_hal/nordic/nrf52820/uart.c +++ b/source/hic_hal/nordic/nrf52820/uart.c @@ -61,6 +61,7 @@ int32_t uart_initialize(void) { clear_buffers(); Driver_USART0.Initialize(uart_handler); + Driver_USART0.PowerControl(ARM_POWER_FULL); return 1; } From 25d5ee2582109505c3304b5232de2ef91df79d9a Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 22 Jul 2021 00:02:09 -0500 Subject: [PATCH 422/617] nrf52820_hic: connect USART driver configuration, disable CTS/RTS --- .../override_nrf52833_dk/IO_Config_Override.h | 12 +++++++----- source/hic_hal/nordic/nrf52820/RTE_Device.h | 14 ++++++++------ 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/source/board/override_nrf52833_dk/IO_Config_Override.h b/source/board/override_nrf52833_dk/IO_Config_Override.h index 4de92d005..a654903ce 100644 --- a/source/board/override_nrf52833_dk/IO_Config_Override.h +++ b/source/board/override_nrf52833_dk/IO_Config_Override.h @@ -66,12 +66,14 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_NRF52820); #define RESET_BUTTON_PULL NRF_GPIO_PIN_PULLUP // UART +#ifndef UART_ARDUINO // This is connected to J-Link -#define UART_RX NRF_GPIO_PIN_MAP(0, 8) // RxD P0.08 -#define UART_TX NRF_GPIO_PIN_MAP(0, 6) // TxD P0.06 - +#define UART_RX_PIN NRF_GPIO_PIN_MAP(0, 8) // RxD P0.08 +#define UART_TX_PIN NRF_GPIO_PIN_MAP(0, 6) // TxD P0.06 +#else // Alternative connected to Arduino D0 / D1 -// #define UART_RX NRF_GPIO_PIN_MAP(1, 1) -// #define UART_TX NRF_GPIO_PIN_MAP(1, 2) +#define UART_RX_PIN NRF_GPIO_PIN_MAP(1, 1) +#define UART_TX_PIN NRF_GPIO_PIN_MAP(1, 2) +#endif #endif diff --git a/source/hic_hal/nordic/nrf52820/RTE_Device.h b/source/hic_hal/nordic/nrf52820/RTE_Device.h index 26bbf5ee9..04c1ea598 100644 --- a/source/hic_hal/nordic/nrf52820/RTE_Device.h +++ b/source/hic_hal/nordic/nrf52820/RTE_Device.h @@ -27,6 +27,8 @@ #ifndef __RTE_DEVICE_H #define __RTE_DEVICE_H +#include "IO_Config.h" + // USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] // Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART #define RTE_USART0 1 @@ -34,22 +36,22 @@ // TX Pin // Pin number #define RTE_USART0_TX_EN 1 -#define RTE_USART0_TX_PIN_NUM 6 +#define RTE_USART0_TX_PIN_NUM UART_TX_PIN // // RX Pin // Pin number #define RTE_USART0_RX_EN 1 -#define RTE_USART0_RX_PIN_NUM 8 +#define RTE_USART0_RX_PIN_NUM UART_RX_PIN // // CTS Pin // Pin number -#define RTE_USART0_CTS_EN 1 -#define RTE_USART0_CTS_PIN_NUM 7 +#define RTE_USART0_CTS_EN 0 +#define RTE_USART0_CTS_PIN_NUM 0 /* N/A */ // // RTS Pin // Pin number -#define RTE_USART0_RTS_EN 1 -#define RTE_USART0_RTS_PIN_NUM 5 +#define RTE_USART0_RTS_EN 0 +#define RTE_USART0_RTS_PIN_NUM 0 /* N/A */ // From 05d0f6c90bc7dcaadba2a7e7fdd416100fd4dd4e Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 22 Jul 2021 00:18:55 -0500 Subject: [PATCH 423/617] nrf52820_hic: support dynamic pin assignment for nRF52833 --- docs/hic/nrf52820.md | 31 ++++++++++++++++---- source/hic_hal/nordic/nrf52820/IO_Config.h | 33 ++++++++++++++++------ source/hic_hal/nordic/nrf52820/sdk.c | 22 +++++++++++++++ 3 files changed, 73 insertions(+), 13 deletions(-) diff --git a/docs/hic/nrf52820.md b/docs/hic/nrf52820.md index b22033385..1beb42eb1 100644 --- a/docs/hic/nrf52820.md +++ b/docs/hic/nrf52820.md @@ -17,17 +17,18 @@ Based on Nordic [nRF52820](https://www.nordicsemi.com/Products/nRF52820): Bootloader size is 32 KB Limiting flash usage to 128 KB - ## DAPLink default pin assignment +# nrf52820 + | Signal | I/O | Symbol | Pin | |-------------|:---:|---------|:---:| | SWD | -| SWCLK | O | P0.00 | 3 | -| SWDIO | I/O | P0.01 | 2 | +| SWCLK | O | P0.01 | 3 | +| SWDIO | I/O | P0.00 | 2 | | UART | -| UART RX | I | P0.08 | 31 | -| UART TX | O | P0.29 | 32 | +| UART TX | I | P0.08 | 31 | +| UART RX | O | P0.29 | 32 | | Button | | F-RST But. | I | P0.06 | 6 | | LEDs | @@ -35,6 +36,23 @@ Limiting flash usage to 128 KB | MSD LED | O | P0.07 | 7 | | CDC LED | O | P0.07 | 7 | +# nrf52833 + +| Signal | I/O | Symbol | Pin | +|-------------|:---:|---------|:---:| +| SWD | +| SWCLK | O | P0.01 | 3 | +| SWDIO | I/O | P0.00 | 2 | +| UART | +| UART TX | I | P0.03 | 31 | +| UART RX | O | P0.02 | 32 | +| Button | +| F-RST But. | I | P1.09 | 6 | +| LEDs | +| HID LED | O | P0.11 | 7 | +| MSD LED | O | P0.11 | 7 | +| CDC LED | O | P0.11 | 7 | + ## nRF52833-DK pin assignment For development on [nRF52833-DK](https://www.nordicsemi.com/Products/Development-hardware/nRF52833-DK). @@ -48,6 +66,9 @@ For development on [nRF52833-DK](https://www.nordicsemi.com/Products/Development | UART | | UART RX | I | P0.08 | N1 | J-Link TX | | UART TX | O | P0.06 | L1 | J-Link RX | +| UART (alt) | +| UART RX | I | P1.01 | Y23 | Arduino D0 | +| UART TX | O | P1.02 | W24 | Arduino D1 | | Button | | F-RST But. | I | P0.11 | T2 | BUTTON_1 | | LEDs | diff --git a/source/hic_hal/nordic/nrf52820/IO_Config.h b/source/hic_hal/nordic/nrf52820/IO_Config.h index 3b5241eb7..74f73cff2 100644 --- a/source/hic_hal/nordic/nrf52820/IO_Config.h +++ b/source/hic_hal/nordic/nrf52820/IO_Config.h @@ -39,11 +39,18 @@ // This GPIO configuration is only valid for the nrf52820 HIC COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_NRF52820); +#define NRF52820_DYNAMIC_PIN + +extern uint32_t uart_tx_pin; +extern uint32_t uart_rx_pin; +extern uint32_t sw_reset_pin; +extern uint32_t led_usb_pin; + // SWDCLK (Output) -#define PIN_SWDCLK NRF_GPIO_PIN_MAP(0, 1) +#define PIN_SWDCLK NRF_GPIO_PIN_MAP(0, 1) // SWDIO (Input/Output) -#define PIN_SWDIO NRF_GPIO_PIN_MAP(0, 0) +#define PIN_SWDIO NRF_GPIO_PIN_MAP(0, 0) // nRESET Pin #undef PIN_nRESET @@ -55,20 +62,30 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_NRF52820); #undef LED_CONNECTED // HID LED -#define LED_HID NRF_GPIO_PIN_MAP(0, 7) +#define LED_HID led_usb_pin // MSC LED -#define LED_MSC NRF_GPIO_PIN_MAP(0, 7) +#define LED_MSC led_usb_pin // CDC LED -#define LED_CDC NRF_GPIO_PIN_MAP(0, 7) +#define LED_CDC led_usb_pin // Reset button (SW_RESET) -#define RESET_BUTTON NRF_GPIO_PIN_MAP(0, 6) +#define RESET_BUTTON sw_reset_pin #define RESET_BUTTON_PULL NRF_GPIO_PIN_PULLUP // UART -#define UART_TX NRF_GPIO_PIN_MAP(0, 8) // From IMCU to target -#define UART_RX NRF_GPIO_PIN_MAP(0, 29) // From target to IMCU +#define UART_TX_PIN uart_tx_pin +#define UART_RX_PIN uart_rx_pin + +#define NRF52820_RESET_PIN NRF_GPIO_PIN_MAP(0, 6) +#define NRF52820_LED_PIN NRF_GPIO_PIN_MAP(0, 7) +#define NRF52820_UART_TX_PIN NRF_GPIO_PIN_MAP(0, 8) // From IMCU to target +#define NRF52820_UART_RX_PIN NRF_GPIO_PIN_MAP(0, 29) // From target to IMCU + +#define NRF52833_RESET_PIN NRF_GPIO_PIN_MAP(1, 9) +#define NRF52833_LED_PIN NRF_GPIO_PIN_MAP(0, 11) +#define NRF52833_UART_TX_PIN NRF_GPIO_PIN_MAP(0, 3) // From IMCU to target +#define NRF52833_UART_RX_PIN NRF_GPIO_PIN_MAP(0, 2) // From target to IMCU #endif diff --git a/source/hic_hal/nordic/nrf52820/sdk.c b/source/hic_hal/nordic/nrf52820/sdk.c index 035295c62..7e4c0d291 100644 --- a/source/hic_hal/nordic/nrf52820/sdk.c +++ b/source/hic_hal/nordic/nrf52820/sdk.c @@ -24,6 +24,28 @@ #include "daplink.h" #include "util.h" +#ifdef NRF52820_DYNAMIC_PIN +uint32_t uart_tx_pin; +uint32_t uart_rx_pin; +uint32_t sw_reset_pin; +uint32_t led_usb_pin; +#endif + void sdk_init() { +#ifdef NRF52820_DYNAMIC_PIN + if (NRF_FICR->INFO.PART == 0x52833) { + // nRF52833 + sw_reset_pin = NRF52833_RESET_PIN; + led_usb_pin = NRF52833_LED_PIN; + uart_tx_pin = NRF52833_UART_TX_PIN; + uart_rx_pin = NRF52833_UART_RX_PIN; + } else { + // nRF52820 + sw_reset_pin = NRF52820_RESET_PIN; + led_usb_pin = NRF52820_LED_PIN; + uart_tx_pin = NRF52820_UART_TX_PIN; + uart_rx_pin = NRF52820_UART_RX_PIN; + } +#endif } From f23b4e5b016a38c81d6eae4fb9b8a9ff654163a2 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 22 Jul 2021 08:59:59 -0500 Subject: [PATCH 424/617] nrf52820_hic: fix LED pin assignments and active state, add power LED --- docs/hic/nrf52820.md | 23 ++++++++++++++++------ source/hic_hal/nordic/nrf52820/IO_Config.h | 11 +++++++++-- source/hic_hal/nordic/nrf52820/gpio.c | 16 ++++++++++++--- source/hic_hal/nordic/nrf52820/sdk.c | 7 +++++-- 4 files changed, 44 insertions(+), 13 deletions(-) diff --git a/docs/hic/nrf52820.md b/docs/hic/nrf52820.md index 1beb42eb1..4a1202ffa 100644 --- a/docs/hic/nrf52820.md +++ b/docs/hic/nrf52820.md @@ -32,9 +32,13 @@ Limiting flash usage to 128 KB | Button | | F-RST But. | I | P0.06 | 6 | | LEDs | -| HID LED | O | P0.07 | 7 | -| MSD LED | O | P0.07 | 7 | -| CDC LED | O | P0.07 | 7 | +| HID LED | O | P0.14 | 14 | +| MSD LED | O | P0.14 | 14 | +| CDC LED | O | P0.14 | 14 | +| POWER LED | O | P0.15 | 15 | + +Note: +- LEDs have active state high. # nrf52833 @@ -49,9 +53,13 @@ Limiting flash usage to 128 KB | Button | | F-RST But. | I | P1.09 | 6 | | LEDs | -| HID LED | O | P0.11 | 7 | -| MSD LED | O | P0.11 | 7 | -| CDC LED | O | P0.11 | 7 | +| HID LED | O | P0.15 | 14 | +| MSD LED | O | P0.15 | 14 | +| CDC LED | O | P0.15 | 14 | +| POWER LED | O | P0.17 | 15 | + +Note: +- LEDs have active state high. ## nRF52833-DK pin assignment @@ -77,3 +85,6 @@ For development on [nRF52833-DK](https://www.nordicsemi.com/Products/Development | HID LED | O | P0.14 | AC9 | LED_2 | | MSD LED | O | P0.15 | AD10 | LED_3 | | CDC LED | O | P0.16 | AC11 | LED_4 | + +Note: +- LEDs have active state low. diff --git a/source/hic_hal/nordic/nrf52820/IO_Config.h b/source/hic_hal/nordic/nrf52820/IO_Config.h index 74f73cff2..815658f54 100644 --- a/source/hic_hal/nordic/nrf52820/IO_Config.h +++ b/source/hic_hal/nordic/nrf52820/IO_Config.h @@ -40,11 +40,13 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_NRF52820); #define NRF52820_DYNAMIC_PIN +#define GPIO_LED_ACTIVE_STATE 1 extern uint32_t uart_tx_pin; extern uint32_t uart_rx_pin; extern uint32_t sw_reset_pin; extern uint32_t led_usb_pin; +extern uint32_t led_pwr_pin; // SWDCLK (Output) #define PIN_SWDCLK NRF_GPIO_PIN_MAP(0, 1) @@ -70,6 +72,9 @@ extern uint32_t led_usb_pin; // CDC LED #define LED_CDC led_usb_pin +// POWER LED +#define LED_PWR led_pwr_pin + // Reset button (SW_RESET) #define RESET_BUTTON sw_reset_pin #define RESET_BUTTON_PULL NRF_GPIO_PIN_PULLUP @@ -79,12 +84,14 @@ extern uint32_t led_usb_pin; #define UART_RX_PIN uart_rx_pin #define NRF52820_RESET_PIN NRF_GPIO_PIN_MAP(0, 6) -#define NRF52820_LED_PIN NRF_GPIO_PIN_MAP(0, 7) +#define NRF52820_USB_LED_PIN NRF_GPIO_PIN_MAP(0, 14) +#define NRF52820_PWR_LED_PIN NRF_GPIO_PIN_MAP(0, 15) #define NRF52820_UART_TX_PIN NRF_GPIO_PIN_MAP(0, 8) // From IMCU to target #define NRF52820_UART_RX_PIN NRF_GPIO_PIN_MAP(0, 29) // From target to IMCU #define NRF52833_RESET_PIN NRF_GPIO_PIN_MAP(1, 9) -#define NRF52833_LED_PIN NRF_GPIO_PIN_MAP(0, 11) +#define NRF52833_USB_LED_PIN NRF_GPIO_PIN_MAP(0, 15) +#define NRF52833_PWR_LED_PIN NRF_GPIO_PIN_MAP(0, 17) #define NRF52833_UART_TX_PIN NRF_GPIO_PIN_MAP(0, 3) // From IMCU to target #define NRF52833_UART_RX_PIN NRF_GPIO_PIN_MAP(0, 2) // From target to IMCU diff --git a/source/hic_hal/nordic/nrf52820/gpio.c b/source/hic_hal/nordic/nrf52820/gpio.c index 135deeef3..417c440a1 100644 --- a/source/hic_hal/nordic/nrf52820/gpio.c +++ b/source/hic_hal/nordic/nrf52820/gpio.c @@ -23,8 +23,18 @@ #include "IO_config.h" +#if (defined(GPIO_LED_ACTIVE_STATE) && (GPIO_LED_ACTIVE_STATE == 1)) +#define GPIO_LED_STATE(state) (state ? 1 : 0) +#else +#define GPIO_LED_STATE(state) (state ? 0 : 1) +#endif + void gpio_init(void) { +#ifdef LED_PWR + nrf_gpio_cfg_output(LED_PWR); + nrf_gpio_pin_write(LED_PWR, GPIO_LED_STATE(1)); +#endif #ifdef LED_CONNECTED nrf_gpio_cfg_output(LED_CONNECTED); #endif @@ -40,17 +50,17 @@ void gpio_init(void) void gpio_set_hid_led(gpio_led_state_t state) { - nrf_gpio_pin_write(LED_HID, state ? 0 : 1); + nrf_gpio_pin_write(LED_HID, GPIO_LED_STATE(state)); } void gpio_set_cdc_led(gpio_led_state_t state) { - nrf_gpio_pin_write(LED_CDC, state ? 0 : 1); + nrf_gpio_pin_write(LED_CDC, GPIO_LED_STATE(state)); } void gpio_set_msc_led(gpio_led_state_t state) { - nrf_gpio_pin_write(LED_MSC, state ? 0 : 1); + nrf_gpio_pin_write(LED_MSC, GPIO_LED_STATE(state)); } uint8_t gpio_get_reset_btn_no_fwrd(void) diff --git a/source/hic_hal/nordic/nrf52820/sdk.c b/source/hic_hal/nordic/nrf52820/sdk.c index 7e4c0d291..98ac8ce5f 100644 --- a/source/hic_hal/nordic/nrf52820/sdk.c +++ b/source/hic_hal/nordic/nrf52820/sdk.c @@ -29,6 +29,7 @@ uint32_t uart_tx_pin; uint32_t uart_rx_pin; uint32_t sw_reset_pin; uint32_t led_usb_pin; +uint32_t led_pwr_pin; #endif void sdk_init() @@ -37,13 +38,15 @@ void sdk_init() if (NRF_FICR->INFO.PART == 0x52833) { // nRF52833 sw_reset_pin = NRF52833_RESET_PIN; - led_usb_pin = NRF52833_LED_PIN; + led_usb_pin = NRF52833_USB_LED_PIN; + led_pwr_pin = NRF52833_PWR_LED_PIN; uart_tx_pin = NRF52833_UART_TX_PIN; uart_rx_pin = NRF52833_UART_RX_PIN; } else { // nRF52820 sw_reset_pin = NRF52820_RESET_PIN; - led_usb_pin = NRF52820_LED_PIN; + led_usb_pin = NRF52820_USB_LED_PIN; + led_pwr_pin = NRF52820_PWR_LED_PIN; uart_tx_pin = NRF52820_UART_TX_PIN; uart_rx_pin = NRF52820_UART_RX_PIN; } From 48a513a14ec88001602178b86c9ca7edb4961a75 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 22 Jul 2021 09:18:40 -0500 Subject: [PATCH 425/617] nrf52820_hic: fix CPU clock in DAP_Config.h --- source/hic_hal/nordic/nrf52820/DAP_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/hic_hal/nordic/nrf52820/DAP_config.h b/source/hic_hal/nordic/nrf52820/DAP_config.h index 7996d7708..bbb50f307 100644 --- a/source/hic_hal/nordic/nrf52820/DAP_config.h +++ b/source/hic_hal/nordic/nrf52820/DAP_config.h @@ -54,7 +54,7 @@ This information includes: /// Processor Clock of the Cortex-M MCU used in the Debug Unit. /// This value is used to calculate the SWD/JTAG clock speed. -#define CPU_CLOCK 100000000U ///< Specifies the CPU Clock in Hz. +#define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz. /// Number of processor cycles for I/O Port write operations. /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O From d7b36af693eb1a135575584f4aa7797d49b10952 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 22 Jul 2021 09:48:14 -0500 Subject: [PATCH 426/617] nrf52820_hic: implement read_unique_id() --- source/board/nrf52820_if.c | 6 +++--- source/hic_hal/nordic/nrf52820/gpio.c | 2 +- source/hic_hal/nordic/nrf52820/read_uid.c | 9 +++++---- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/source/board/nrf52820_if.c b/source/board/nrf52820_if.c index 64274e02d..a8724917c 100644 --- a/source/board/nrf52820_if.c +++ b/source/board/nrf52820_if.c @@ -22,9 +22,9 @@ #include "target_family.h" #include "target_board.h" -const char * const board_id_nrf52 = "FF01"; -const char * const board_id_nrf52_64 = "FF02"; -const char * const board_id_nrf52840 = "FF03"; +const char * const board_id_nrf52 = "ff01"; +const char * const board_id_nrf52_64 = "ff02"; +const char * const board_id_nrf52840 = "ff03"; extern target_cfg_t target_device_nrf52; extern target_cfg_t target_device_nrf52_64; diff --git a/source/hic_hal/nordic/nrf52820/gpio.c b/source/hic_hal/nordic/nrf52820/gpio.c index 417c440a1..a0f555f03 100644 --- a/source/hic_hal/nordic/nrf52820/gpio.c +++ b/source/hic_hal/nordic/nrf52820/gpio.c @@ -1,6 +1,6 @@ /** * @file gpio.c - * @brief GPIO access functions for nrf52833 HIC + * @brief GPIO access functions for nrf52820 HIC * * DAPLink Interface Firmware * Copyright (c) 2021, Arm Limited, All Rights Reserved diff --git a/source/hic_hal/nordic/nrf52820/read_uid.c b/source/hic_hal/nordic/nrf52820/read_uid.c index 74af68d65..99f26576c 100644 --- a/source/hic_hal/nordic/nrf52820/read_uid.c +++ b/source/hic_hal/nordic/nrf52820/read_uid.c @@ -1,6 +1,6 @@ /** * @file read_uid.c - * @brief UID extraction function for nrf52833 HIC + * @brief UID extraction function for nrf52820 HIC * * DAPLink Interface Firmware * Copyright (c) 2021, Arm Limited, All Rights Reserved @@ -20,11 +20,12 @@ */ #include "read_uid.h" +#include "device.h" void read_unique_id(uint32_t *id) { - id[0] = 0; - id[1] = 0; - id[2] = 0; + id[0] = NRF_FICR->INFO.PART; + id[1] = NRF_FICR->DEVICEID[0]; + id[2] = NRF_FICR->DEVICEID[1]; id[3] = 0; } From bcd8e4d071cfac69736c64a4fcd613405074da03 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 22 Jul 2021 19:07:55 +0200 Subject: [PATCH 427/617] nrf52820_hic: change pins on nRF52833-DK to be compatible with nRF52820 GPIOs --- docs/hic/nrf52820.md | 30 +++++++++---------- .../override_nrf52833_dk/IO_Config_Override.h | 15 +++++----- 2 files changed, 23 insertions(+), 22 deletions(-) diff --git a/docs/hic/nrf52820.md b/docs/hic/nrf52820.md index 4a1202ffa..0abc0b7f8 100644 --- a/docs/hic/nrf52820.md +++ b/docs/hic/nrf52820.md @@ -65,26 +65,26 @@ Note: For development on [nRF52833-DK](https://www.nordicsemi.com/Products/Development-hardware/nRF52833-DK). -| Signal | I/O | Symbol | Pin | Connection | -|-------------|:---:|---------|:----:|:----------:| +| Signal | I/O | Symbol | Connection | +|-------------|:---:|---------|:----------:| | SWD | -| SWCLK | O | P1.06 | R24 | Arduino D5 | -| SWDIO | I/O | P1.07 | P23 | Arduino D6 | -| nRESET | O | P1.08 | N2 | Arduino D7 | +| SWCLK | O | P0.04 | | +| SWDIO | I/O | P0.05 | | +| nRESET | O | P0.07 | | | UART | -| UART RX | I | P0.08 | N1 | J-Link TX | -| UART TX | O | P0.06 | L1 | J-Link RX | +| UART RX | I | P0.08 | J-Link TX | +| UART TX | O | P0.06 | J-Link RX | | UART (alt) | -| UART RX | I | P1.01 | Y23 | Arduino D0 | -| UART TX | O | P1.02 | W24 | Arduino D1 | +| UART RX | I | P0.29 | | +| UART TX | O | P0.30 | | | Button | -| F-RST But. | I | P0.11 | T2 | BUTTON_1 | +| F-RST But. | I | P0.11 | BUTTON_1 | | LEDs | -| RUN LED | O | P0.13 | AD8 | LED_1 | -| CON LED | O | P0.14 | AC9 | LED_2 | -| HID LED | O | P0.14 | AC9 | LED_2 | -| MSD LED | O | P0.15 | AD10 | LED_3 | -| CDC LED | O | P0.16 | AC11 | LED_4 | +| RUN LED | O | P0.13 | LED_1 | +| CON LED | O | P0.14 | LED_2 | +| HID LED | O | P0.14 | LED_2 | +| MSD LED | O | P0.15 | LED_3 | +| CDC LED | O | P0.16 | LED_4 | Note: - LEDs have active state low. diff --git a/source/board/override_nrf52833_dk/IO_Config_Override.h b/source/board/override_nrf52833_dk/IO_Config_Override.h index a654903ce..ed5757014 100644 --- a/source/board/override_nrf52833_dk/IO_Config_Override.h +++ b/source/board/override_nrf52833_dk/IO_Config_Override.h @@ -38,13 +38,14 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_NRF52820); #define BUTTON_1 NRF_GPIO_PIN_MAP(0, 11) // SWDCLK (Output) -#define PIN_SWDCLK NRF_GPIO_PIN_MAP(1, 6) // Arduino D5 +#define PIN_SWDCLK NRF_GPIO_PIN_MAP(0, 4) // SWDIO (Input/Output) -#define PIN_SWDIO NRF_GPIO_PIN_MAP(1, 7) // Arduino D6 +#define PIN_SWDIO NRF_GPIO_PIN_MAP(0, 5) // nRESET Pin -#define PIN_nRESET NRF_GPIO_PIN_MAP(1, 8) // Arduino D7 +#undef PIN_nRESET +// #define PIN_nRESET NRF_GPIO_PIN_MAP(0, 7) // Target Running LED (Output) #define LED_RUNNING LED_1 @@ -66,14 +67,14 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_NRF52820); #define RESET_BUTTON_PULL NRF_GPIO_PIN_PULLUP // UART -#ifndef UART_ARDUINO +#ifndef UART_EXTERNAL // This is connected to J-Link #define UART_RX_PIN NRF_GPIO_PIN_MAP(0, 8) // RxD P0.08 #define UART_TX_PIN NRF_GPIO_PIN_MAP(0, 6) // TxD P0.06 #else -// Alternative connected to Arduino D0 / D1 -#define UART_RX_PIN NRF_GPIO_PIN_MAP(1, 1) -#define UART_TX_PIN NRF_GPIO_PIN_MAP(1, 2) +// Alternative pin out +#define UART_RX_PIN NRF_GPIO_PIN_MAP(0, 29) +#define UART_TX_PIN NRF_GPIO_PIN_MAP(0, 30) #endif #endif From da075b14d6a4bc1e1dd931b6752c93b4e002cefc Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 26 Jul 2021 18:31:38 +0200 Subject: [PATCH 428/617] nrf52820_hic: fix SWCLK typo --- .../board/override_nrf52833_dk/IO_Config_Override.h | 2 +- source/hic_hal/nordic/nrf52820/DAP_config.h | 12 ++++++------ source/hic_hal/nordic/nrf52820/IO_Config.h | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/source/board/override_nrf52833_dk/IO_Config_Override.h b/source/board/override_nrf52833_dk/IO_Config_Override.h index ed5757014..43271dcad 100644 --- a/source/board/override_nrf52833_dk/IO_Config_Override.h +++ b/source/board/override_nrf52833_dk/IO_Config_Override.h @@ -38,7 +38,7 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_NRF52820); #define BUTTON_1 NRF_GPIO_PIN_MAP(0, 11) // SWDCLK (Output) -#define PIN_SWDCLK NRF_GPIO_PIN_MAP(0, 4) +#define PIN_SWCLK NRF_GPIO_PIN_MAP(0, 4) // SWDIO (Input/Output) #define PIN_SWDIO NRF_GPIO_PIN_MAP(0, 5) diff --git a/source/hic_hal/nordic/nrf52820/DAP_config.h b/source/hic_hal/nordic/nrf52820/DAP_config.h index bbb50f307..96ad71ea8 100644 --- a/source/hic_hal/nordic/nrf52820/DAP_config.h +++ b/source/hic_hal/nordic/nrf52820/DAP_config.h @@ -184,10 +184,10 @@ Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: - TDI, nTRST to HighZ mode (pins are unused in SWD mode). */ __STATIC_INLINE void PORT_SWD_SETUP (void) { - nrf_gpio_cfg(PIN_SWDCLK, NRF_GPIO_PIN_DIR_OUTPUT, + nrf_gpio_cfg(PIN_SWCLK, NRF_GPIO_PIN_DIR_OUTPUT, NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); - nrf_gpio_pin_set(PIN_SWDCLK); + nrf_gpio_pin_set(PIN_SWCLK); nrf_gpio_cfg(PIN_SWDIO, NRF_GPIO_PIN_DIR_OUTPUT, NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); @@ -205,7 +205,7 @@ Disables the DAP Hardware I/O pins which configures: - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode. */ __STATIC_INLINE void PORT_OFF (void) { - nrf_gpio_cfg_input(PIN_SWDCLK, NRF_GPIO_PIN_NOPULL); + nrf_gpio_cfg_input(PIN_SWCLK, NRF_GPIO_PIN_NOPULL); nrf_gpio_cfg_input(PIN_SWDIO, NRF_GPIO_PIN_NOPULL); #ifdef PIN_nRESET nrf_gpio_cfg_input(PIN_nRESET, NRF_GPIO_PIN_NOPULL); @@ -219,21 +219,21 @@ __STATIC_INLINE void PORT_OFF (void) { \return Current status of the SWCLK/TCK DAP hardware I/O pin. */ __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) { - return nrf_gpio_pin_out_read(PIN_SWDCLK); + return nrf_gpio_pin_out_read(PIN_SWCLK); } /** SWCLK/TCK I/O pin: Set Output to High. Set the SWCLK/TCK DAP hardware I/O pin to high level. */ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) { - nrf_gpio_pin_set(PIN_SWDCLK); + nrf_gpio_pin_set(PIN_SWCLK); } /** SWCLK/TCK I/O pin: Set Output to Low. Set the SWCLK/TCK DAP hardware I/O pin to low level. */ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) { - nrf_gpio_pin_clear(PIN_SWDCLK); + nrf_gpio_pin_clear(PIN_SWCLK); } diff --git a/source/hic_hal/nordic/nrf52820/IO_Config.h b/source/hic_hal/nordic/nrf52820/IO_Config.h index 815658f54..8cbbf74d9 100644 --- a/source/hic_hal/nordic/nrf52820/IO_Config.h +++ b/source/hic_hal/nordic/nrf52820/IO_Config.h @@ -49,7 +49,7 @@ extern uint32_t led_usb_pin; extern uint32_t led_pwr_pin; // SWDCLK (Output) -#define PIN_SWDCLK NRF_GPIO_PIN_MAP(0, 1) +#define PIN_SWCLK NRF_GPIO_PIN_MAP(0, 1) // SWDIO (Input/Output) #define PIN_SWDIO NRF_GPIO_PIN_MAP(0, 0) From dfee1a5fef6abd7805c040cec312801572a8fd1d Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 26 Jul 2021 23:21:03 +0200 Subject: [PATCH 429/617] nrf52820_hic: implement fast GPIO version --- records/hic_hal/nrf52820.yaml | 1 + source/hic_hal/nordic/nrf52820/DAP_config.h | 119 ++++++++++++++++++++ source/hic_hal/nordic/nrf52820/gpio.c | 7 ++ 3 files changed, 127 insertions(+) diff --git a/records/hic_hal/nrf52820.yaml b/records/hic_hal/nrf52820.yaml index 1394cacef..eef4eba89 100644 --- a/records/hic_hal/nrf52820.yaml +++ b/records/hic_hal/nrf52820.yaml @@ -5,6 +5,7 @@ common: - Cortex-M4 macros: - INTERFACE_NRF52820 + # - FAST_GPIO - NRF52820_XXAA - DAPLINK_HIC_ID=0x6E052820 # DAPLINK_HIC_ID_NRF52820 - OS_CLOCK=64000000 diff --git a/source/hic_hal/nordic/nrf52820/DAP_config.h b/source/hic_hal/nordic/nrf52820/DAP_config.h index 96ad71ea8..42c58a3b0 100644 --- a/source/hic_hal/nordic/nrf52820/DAP_config.h +++ b/source/hic_hal/nordic/nrf52820/DAP_config.h @@ -178,12 +178,84 @@ __STATIC_INLINE void PORT_JTAG_SETUP (void) { ; } +#ifdef FAST_GPIO + +extern NRF_GPIO_Type *pin_swclk_reg; +extern NRF_GPIO_Type *pin_swdio_reg; +extern uint32_t pin_swclk_idx; +extern uint32_t pin_swdio_idx; + +#if (GPIO_COUNT == 1) +#define INIT_PIN(id, pin) \ + { \ + NRFX_ASSERT(nrf_gpio_pin_present_check(pin)); \ + id##_reg = NRF_P0; \ + id##_idx = pin; \ + } +#else +#define INIT_PIN(id, pin) \ + { \ + NRFX_ASSERT(nrf_gpio_pin_present_check(pin)); \ + if (pin < P0_PIN_NUM) { \ + id##_reg = NRF_P0; \ + id##_idx = pin; \ + } else { \ + id##_reg = NRF_P1; \ + id##_idx = pin & 0x1F; \ + } \ + } +#endif + +__STATIC_INLINE void gpio_config( + NRF_GPIO_Type *reg, + uint32_t idx, + nrf_gpio_pin_dir_t dir, + nrf_gpio_pin_input_t input, + nrf_gpio_pin_pull_t pull, + nrf_gpio_pin_drive_t drive, + nrf_gpio_pin_sense_t sense) +{ + reg->PIN_CNF[idx] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos) + | ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) + | ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos) + | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) + | ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos); +} + +#define CONFIG_PIN(pin, dir, input, pull, drive, sense) \ + gpio_config(pin##_reg, pin##_idx, dir, input, pull, drive, sense) + +#define SET_PIN(pin) \ + pin##_reg->OUTSET = (1UL << pin##_idx) +#define CLEAR_PIN(pin) \ + pin##_reg->OUTCLR = (1UL << pin##_idx) +#define READ_PIN(pin) \ + (((pin##_reg->IN) >> pin##_idx) & 1UL) +#define READ_PIN_OUT(pin) \ + (((pin##_reg->OUT) >> pin##_idx) & 1UL) +#define SET_OUTPUT_DIR(pin) \ + pin##_reg->DIRSET = (1UL << pin##_idx) + +#endif + /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET. Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: - SWCLK, SWDIO, nRESET to output mode and set to default high level. - TDI, nTRST to HighZ mode (pins are unused in SWD mode). */ __STATIC_INLINE void PORT_SWD_SETUP (void) { +#ifdef FAST_GPIO + INIT_PIN(pin_swclk, PIN_SWCLK); + INIT_PIN(pin_swdio, PIN_SWDIO); + CONFIG_PIN(pin_swclk, NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); + SET_PIN(pin_swclk); + CONFIG_PIN(pin_swdio, NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); + SET_PIN(pin_swdio); +#else nrf_gpio_cfg(PIN_SWCLK, NRF_GPIO_PIN_DIR_OUTPUT, NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); @@ -198,6 +270,7 @@ __STATIC_INLINE void PORT_SWD_SETUP (void) { NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); nrf_gpio_pin_set(PIN_nRESET); #endif +#endif } /** Disable JTAG/SWD I/O Pins. @@ -219,21 +292,33 @@ __STATIC_INLINE void PORT_OFF (void) { \return Current status of the SWCLK/TCK DAP hardware I/O pin. */ __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) { +#ifdef FAST_GPIO + return READ_PIN_OUT(pin_swclk); +#else return nrf_gpio_pin_out_read(PIN_SWCLK); +#endif } /** SWCLK/TCK I/O pin: Set Output to High. Set the SWCLK/TCK DAP hardware I/O pin to high level. */ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) { +#ifdef FAST_GPIO + SET_PIN(pin_swclk); +#else nrf_gpio_pin_set(PIN_SWCLK); +#endif } /** SWCLK/TCK I/O pin: Set Output to Low. Set the SWCLK/TCK DAP hardware I/O pin to low level. */ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) { +#ifdef FAST_GPIO + CLEAR_PIN(pin_swclk); +#else nrf_gpio_pin_clear(PIN_SWCLK); +#endif } @@ -243,39 +328,63 @@ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) { \return Current status of the SWDIO/TMS DAP hardware I/O pin. */ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) { +#ifdef FAST_GPIO1 + READ_PIN(pin_swdio); +#else return nrf_gpio_pin_read(PIN_SWDIO) & 0x1; +#endif } /** SWDIO/TMS I/O pin: Set Output to High. Set the SWDIO/TMS DAP hardware I/O pin to high level. */ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) { +#ifdef FAST_GPIO + SET_PIN(pin_swdio); +#else nrf_gpio_pin_set(PIN_SWDIO); +#endif } /** SWDIO/TMS I/O pin: Set Output to Low. Set the SWDIO/TMS DAP hardware I/O pin to low level. */ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) { +#ifdef FAST_GPIO + CLEAR_PIN(pin_swdio); +#else nrf_gpio_pin_clear(PIN_SWDIO); +#endif } /** SWDIO I/O pin: Get Input (used in SWD mode only). \return Current status of the SWDIO DAP hardware I/O pin. */ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) { +#ifdef FAST_GPIO + return READ_PIN(pin_swdio); +#else return nrf_gpio_pin_read(PIN_SWDIO) & 0x1; +#endif } /** SWDIO I/O pin: Set Output (used in SWD mode only). \param bit Output value for the SWDIO DAP hardware I/O pin. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit) { +#ifdef FAST_GPIO + if (bit & 0x1) { + SET_PIN(pin_swdio); + } else { + CLEAR_PIN(pin_swdio); + } +#else if (bit & 0x1) { nrf_gpio_pin_set(PIN_SWDIO); } else { nrf_gpio_pin_clear(PIN_SWDIO); } +#endif } /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only). @@ -283,7 +392,11 @@ Configure the SWDIO DAP hardware I/O pin to output mode. This function is called prior \ref PIN_SWDIO_OUT function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) { +#ifdef FAST_GPIO + SET_OUTPUT_DIR(pin_swdio); +#else nrf_gpio_pin_dir_set(PIN_SWDIO, NRF_GPIO_PIN_DIR_OUTPUT); +#endif } /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). @@ -291,7 +404,13 @@ Configure the SWDIO DAP hardware I/O pin to input mode. This function is called prior \ref PIN_SWDIO_IN function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) { +#ifdef FAST_GPIO + CONFIG_PIN(pin_swdio, NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); +#else nrf_gpio_pin_dir_set(PIN_SWDIO, NRF_GPIO_PIN_DIR_INPUT); +#endif } diff --git a/source/hic_hal/nordic/nrf52820/gpio.c b/source/hic_hal/nordic/nrf52820/gpio.c index a0f555f03..1b316867f 100644 --- a/source/hic_hal/nordic/nrf52820/gpio.c +++ b/source/hic_hal/nordic/nrf52820/gpio.c @@ -23,6 +23,13 @@ #include "IO_config.h" +#ifdef FAST_GPIO +NRF_GPIO_Type *pin_swclk_reg; +NRF_GPIO_Type *pin_swdio_reg; +uint32_t pin_swclk_idx; +uint32_t pin_swdio_idx; +#endif + #if (defined(GPIO_LED_ACTIVE_STATE) && (GPIO_LED_ACTIVE_STATE == 1)) #define GPIO_LED_STATE(state) (state ? 1 : 0) #else From 29b06319c709509bc8efa9cbcfaa8616a41686f2 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 19 Oct 2021 22:12:31 -0500 Subject: [PATCH 430/617] nrf52820_hic: re-use existing board IDs for pyocd auto-detection --- projects.yaml | 3 +-- source/board/nrf52820_if.c | 6 +++--- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/projects.yaml b/projects.yaml index bb5f0731e..6e1f50f01 100644 --- a/projects.yaml +++ b/projects.yaml @@ -84,6 +84,7 @@ module: hic_nrf52820: &module_hic_nrf52820 - records/rtos/rtos-cm4.yaml - records/hic_hal/nrf52820.yaml + - records/usb/usb-bulk.yaml projects: # HIC bootloaders and all target interfaces @@ -171,7 +172,6 @@ projects: - *module_if - *module_hic_nrf52820 - records/family/all_family.yaml - - records/usb/usb-bulk.yaml nrf52833_dk_bl: - *module_bl - records/hic_hal/nrf52820.yaml @@ -182,7 +182,6 @@ projects: - *module_hic_nrf52820 - records/board/nrf52820_if.yaml - records/board/nrf52833_dk.yaml - - records/usb/usb-bulk.yaml sam3u2c_bl: - *module_bl - records/hic_hal/sam3u2c.yaml diff --git a/source/board/nrf52820_if.c b/source/board/nrf52820_if.c index a8724917c..66ab4be84 100644 --- a/source/board/nrf52820_if.c +++ b/source/board/nrf52820_if.c @@ -22,9 +22,9 @@ #include "target_family.h" #include "target_board.h" -const char * const board_id_nrf52 = "ff01"; -const char * const board_id_nrf52_64 = "ff02"; -const char * const board_id_nrf52840 = "ff03"; +const char * const board_id_nrf52 = "1101"; +const char * const board_id_nrf52_64 = "9903"; +const char * const board_id_nrf52840 = "1102"; extern target_cfg_t target_device_nrf52; extern target_cfg_t target_device_nrf52_64; From 5609892f778499bee4995052d2fd78fc7de75788 Mon Sep 17 00:00:00 2001 From: Russ Butler Date: Tue, 27 Jul 2021 12:54:35 -0500 Subject: [PATCH 431/617] Fix uv5 compilation for Nordic Change the #elif defines without a condition to #else to fix nordic compilation with uvision. --- source/hic_hal/nordic/nrf52820/USART_nRF52820.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/source/hic_hal/nordic/nrf52820/USART_nRF52820.c b/source/hic_hal/nordic/nrf52820/USART_nRF52820.c index 444c7683d..036276c4a 100644 --- a/source/hic_hal/nordic/nrf52820/USART_nRF52820.c +++ b/source/hic_hal/nordic/nrf52820/USART_nRF52820.c @@ -569,7 +569,7 @@ static int32_t USART_Control (uint32_t control, uint32_t arg) { return ARM_DRIVER_ERROR_PARAMETER; } break; -#elif +#else return ARM_DRIVER_ERROR_UNSUPPORTED; #endif @@ -599,7 +599,7 @@ static int32_t USART_Control (uint32_t control, uint32_t arg) { return ARM_DRIVER_ERROR_PARAMETER; } break; -#elif +#else return ARM_DRIVER_ERROR_UNSUPPORTED; #endif From ca4dc47a611c23fe9647abad27c9237354cc6b81 Mon Sep 17 00:00:00 2001 From: Russ Butler Date: Tue, 27 Jul 2021 13:02:36 -0500 Subject: [PATCH 432/617] Fix CMSIS v1 USB Interface The CMSIS v1 USB interface requires an interrupt IN endpoint to work. This patch enables the IN endpoint by removing the `#ifndef BULK_ENDPOINT` in usb_config.c. The nrf52840 has enough free endpoints that CMSIS v2 endpoints (BULK) and CMSIS v1 endpoionts (HID) can be enabled at the same time. This patch also sets the max DAP packet size to 64 as this is the maximum allows by full speed HID. Without this pyOCD does not work with CMSIS v1. --- source/hic_hal/nordic/nrf52820/DAP_config.h | 2 +- source/hic_hal/nordic/nrf52820/usb_config.c | 5 ----- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/source/hic_hal/nordic/nrf52820/DAP_config.h b/source/hic_hal/nordic/nrf52820/DAP_config.h index 42c58a3b0..529eece34 100644 --- a/source/hic_hal/nordic/nrf52820/DAP_config.h +++ b/source/hic_hal/nordic/nrf52820/DAP_config.h @@ -89,7 +89,7 @@ This information includes: /// This configuration settings is used to optimize the communication performance with the /// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB, /// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB. -#define DAP_PACKET_SIZE 512U ///< Specifies Packet Size in bytes. +#define DAP_PACKET_SIZE 64U ///< Specifies Packet Size in bytes. /// Maximum Package Buffers for Command and Response data. /// This configuration settings is used to optimize the communication performance with the diff --git a/source/hic_hal/nordic/nrf52820/usb_config.c b/source/hic_hal/nordic/nrf52820/usb_config.c index cee7fc314..bbb5b0c8f 100644 --- a/source/hic_hal/nordic/nrf52820/usb_config.c +++ b/source/hic_hal/nordic/nrf52820/usb_config.c @@ -156,13 +156,8 @@ #endif #define USBD_HID_ENABLE HID_ENDPOINT -#ifndef BULK_ENDPOINT //check if bulk endpoint is not enabled #define USBD_HID_EP_INTIN 1 #define USBD_HID_EP_INTOUT 1 -#else //if bulk endpoint is enabled remove interrupt endpoints from the hid -#define USBD_HID_EP_INTIN 0 -#define USBD_HID_EP_INTOUT 0 -#endif #define USBD_HID_EP_INTIN_STACK 0 #define USBD_HID_WMAXPACKETSIZE 64 #define USBD_HID_BINTERVAL 1 From 42f47c0b92947096156603d43de5a668f4a70b32 Mon Sep 17 00:00:00 2001 From: Russ Butler Date: Tue, 27 Jul 2021 13:12:56 -0500 Subject: [PATCH 433/617] Disable HS USB for nrf52840 The nrf52840 does not support high speed USB so this patch disables it. --- source/hic_hal/nordic/nrf52820/usb_config.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/source/hic_hal/nordic/nrf52820/usb_config.c b/source/hic_hal/nordic/nrf52820/usb_config.c index bbb5b0c8f..6233b8f77 100644 --- a/source/hic_hal/nordic/nrf52820/usb_config.c +++ b/source/hic_hal/nordic/nrf52820/usb_config.c @@ -30,7 +30,7 @@ // High-speed // Enable high-speed functionality (if device supports it) -#define USBD_HS_ENABLE 1 +#define USBD_HS_ENABLE 0 #if (defined(WEBUSB_INTERFACE) || defined(WINUSB_INTERFACE) || defined(BULK_ENDPOINT)) #define USBD_BOS_ENABLE 1 #else @@ -161,7 +161,7 @@ #define USBD_HID_EP_INTIN_STACK 0 #define USBD_HID_WMAXPACKETSIZE 64 #define USBD_HID_BINTERVAL 1 -#define USBD_HID_HS_ENABLE 1 +#define USBD_HID_HS_ENABLE 0 #define USBD_HID_HS_WMAXPACKETSIZE 64 #define USBD_HID_HS_BINTERVAL 1 #define USBD_HID_STRDESC L"CMSIS-DAP v1" @@ -212,7 +212,7 @@ #define USBD_MSC_EP_BULKOUT 2 #define USBD_MSC_EP_BULKIN_STACK 0 #define USBD_MSC_WMAXPACKETSIZE 64 -#define USBD_MSC_HS_ENABLE 1 +#define USBD_MSC_HS_ENABLE 0 #define USBD_MSC_HS_WMAXPACKETSIZE 512 #define USBD_MSC_HS_BINTERVAL 0 #define USBD_MSC_STRDESC L"USB_MSC" @@ -332,7 +332,7 @@ #define USBD_CDC_ACM_EP_INTIN_STACK 0 #define USBD_CDC_ACM_WMAXPACKETSIZE 16 #define USBD_CDC_ACM_BINTERVAL 32 -#define USBD_CDC_ACM_HS_ENABLE 1 +#define USBD_CDC_ACM_HS_ENABLE 0 #define USBD_CDC_ACM_HS_WMAXPACKETSIZE 64 #define USBD_CDC_ACM_HS_BINTERVAL 2 #define USBD_CDC_ACM_EP_BULKIN 4 @@ -393,7 +393,7 @@ #define USBD_BULK_EP_BULKOUT 5 // #define USBD_BULK_EP_BULKIN_SWO 6 #define USBD_BULK_WMAXPACKETSIZE 64 -#define USBD_BULK_HS_ENABLE 1 +#define USBD_BULK_HS_ENABLE 0 #define USBD_BULK_HS_WMAXPACKETSIZE 512 #define USBD_BULK_STRDESC L"CMSIS-DAP v2" From 00895da4f02396521bbef6ef5b071c6199aedf1b Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 28 Jul 2021 10:45:12 +0200 Subject: [PATCH 434/617] nrf52820_hic: alternate optimized GPIO for DAP --- source/hic_hal/nordic/nrf52820/DAP_config.h | 135 ++++++++++++++++---- 1 file changed, 110 insertions(+), 25 deletions(-) diff --git a/source/hic_hal/nordic/nrf52820/DAP_config.h b/source/hic_hal/nordic/nrf52820/DAP_config.h index 529eece34..4e25424b8 100644 --- a/source/hic_hal/nordic/nrf52820/DAP_config.h +++ b/source/hic_hal/nordic/nrf52820/DAP_config.h @@ -178,7 +178,7 @@ __STATIC_INLINE void PORT_JTAG_SETUP (void) { ; } -#ifdef FAST_GPIO +#if defined(FAST_GPIO) || defined(FAST_GPIO2) extern NRF_GPIO_Type *pin_swclk_reg; extern NRF_GPIO_Type *pin_swdio_reg; @@ -206,6 +206,20 @@ extern uint32_t pin_swdio_idx; } #endif +#define CONFIG_PIN(pin, dir, input, pull, drive, sense) \ + gpio_config(pin##_reg, pin##_idx, dir, input, pull, drive, sense) + +#define SET_PIN(pin) \ + pin##_reg->OUTSET = (1UL << pin##_idx) +#define CLEAR_PIN(pin) \ + pin##_reg->OUTCLR = (1UL << pin##_idx) +#define READ_PIN(pin) \ + (((pin##_reg->IN) >> pin##_idx) & 1UL) +#define READ_PIN_OUT(pin) \ + (((pin##_reg->OUT) >> pin##_idx) & 1UL) +#define SET_OUTPUT_DIR(pin) \ + pin##_reg->DIRSET = (1UL << pin##_idx) + __STATIC_INLINE void gpio_config( NRF_GPIO_Type *reg, uint32_t idx, @@ -222,19 +236,39 @@ __STATIC_INLINE void gpio_config( | ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos); } -#define CONFIG_PIN(pin, dir, input, pull, drive, sense) \ - gpio_config(pin##_reg, pin##_idx, dir, input, pull, drive, sense) +__STATIC_INLINE void gpio_set(NRF_GPIO_Type *reg, uint32_t idx) +{ + reg->OUTSET = (1UL << idx); +} + +__STATIC_INLINE void gpio_clear(NRF_GPIO_Type *reg, uint32_t idx) +{ + reg->OUTCLR = (1UL << idx); +} + +__STATIC_INLINE uint32_t gpio_read(NRF_GPIO_Type *reg, uint32_t idx) +{ + return ((reg->IN >> idx) & 1UL); +} + +__STATIC_INLINE uint32_t gpio_out_read(NRF_GPIO_Type *reg, uint32_t idx) +{ + return ((reg->OUT >> idx) & 1UL); +} + +__STATIC_INLINE void gpio_set_output_dir(NRF_GPIO_Type *reg, uint32_t idx) +{ + reg->DIRSET = (1UL << idx); +} + +#if (GPIO_COUNT == 1) +#define GPIO_REG(pin) NRF_P0 +#define GPIO_IDX(pin) (pin) +#else +#define GPIO_REG(pin) (((pin) < P0_PIN_NUM) ? NRF_P0 : NRF_P1) +#define GPIO_IDX(pin) (((pin) < P0_PIN_NUM) ? (pin) : ((pin) & 0x1F)) +#endif -#define SET_PIN(pin) \ - pin##_reg->OUTSET = (1UL << pin##_idx) -#define CLEAR_PIN(pin) \ - pin##_reg->OUTCLR = (1UL << pin##_idx) -#define READ_PIN(pin) \ - (((pin##_reg->IN) >> pin##_idx) & 1UL) -#define READ_PIN_OUT(pin) \ - (((pin##_reg->OUT) >> pin##_idx) & 1UL) -#define SET_OUTPUT_DIR(pin) \ - pin##_reg->DIRSET = (1UL << pin##_idx) #endif @@ -244,7 +278,7 @@ Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: - TDI, nTRST to HighZ mode (pins are unused in SWD mode). */ __STATIC_INLINE void PORT_SWD_SETUP (void) { -#ifdef FAST_GPIO +#if defined(FAST_GPIO) INIT_PIN(pin_swclk, PIN_SWCLK); INIT_PIN(pin_swdio, PIN_SWDIO); CONFIG_PIN(pin_swclk, NRF_GPIO_PIN_DIR_OUTPUT, @@ -255,6 +289,15 @@ __STATIC_INLINE void PORT_SWD_SETUP (void) { NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); SET_PIN(pin_swdio); +#elif defined(FAST_GPIO2) + gpio_config(GPIO_REG(PIN_SWCLK), GPIO_IDX(PIN_SWCLK), + NRF_GPIO_PIN_DIR_OUTPUT, NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); + gpio_set(GPIO_REG(PIN_SWCLK), GPIO_IDX(PIN_SWCLK)); + gpio_config(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO), + NRF_GPIO_PIN_DIR_OUTPUT, NRF_GPIO_PIN_INPUT_CONNECT, + NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); + gpio_set(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); #else nrf_gpio_cfg(PIN_SWCLK, NRF_GPIO_PIN_DIR_OUTPUT, NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL, @@ -278,11 +321,27 @@ Disables the DAP Hardware I/O pins which configures: - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode. */ __STATIC_INLINE void PORT_OFF (void) { +#if defined(FAST_GPIO) + CONFIG_PIN(pin_swclk, NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); + CONFIG_PIN(pin_swdio, NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); +#elif defined(FAST_GPIO2) + gpio_config(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO), + NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, + NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); + gpio_config(GPIO_REG(PIN_SWCLK), GPIO_IDX(PIN_SWCLK), + NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, + NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); +#else nrf_gpio_cfg_input(PIN_SWCLK, NRF_GPIO_PIN_NOPULL); nrf_gpio_cfg_input(PIN_SWDIO, NRF_GPIO_PIN_NOPULL); #ifdef PIN_nRESET nrf_gpio_cfg_input(PIN_nRESET, NRF_GPIO_PIN_NOPULL); #endif +#endif } @@ -292,8 +351,10 @@ __STATIC_INLINE void PORT_OFF (void) { \return Current status of the SWCLK/TCK DAP hardware I/O pin. */ __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) { -#ifdef FAST_GPIO +#if defined(FAST_GPIO) return READ_PIN_OUT(pin_swclk); +#elif defined(FAST_GPIO2) + return gpio_out_read(GPIO_REG(PIN_SWCLK), GPIO_IDX(PIN_SWCLK)); #else return nrf_gpio_pin_out_read(PIN_SWCLK); #endif @@ -303,8 +364,10 @@ __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) { Set the SWCLK/TCK DAP hardware I/O pin to high level. */ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) { -#ifdef FAST_GPIO +#if defined(FAST_GPIO) SET_PIN(pin_swclk); +#elif defined(FAST_GPIO2) + gpio_set(GPIO_REG(PIN_SWCLK), GPIO_IDX(PIN_SWCLK)); #else nrf_gpio_pin_set(PIN_SWCLK); #endif @@ -314,8 +377,10 @@ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) { Set the SWCLK/TCK DAP hardware I/O pin to low level. */ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) { -#ifdef FAST_GPIO +#if defined(FAST_GPIO) CLEAR_PIN(pin_swclk); +#elif defined(FAST_GPIO2) + gpio_clear(GPIO_REG(PIN_SWCLK), GPIO_IDX(PIN_SWCLK)); #else nrf_gpio_pin_clear(PIN_SWCLK); #endif @@ -328,8 +393,10 @@ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) { \return Current status of the SWDIO/TMS DAP hardware I/O pin. */ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) { -#ifdef FAST_GPIO1 - READ_PIN(pin_swdio); +#if defined(FAST_GPIO) + return READ_PIN(pin_swdio); +#elif defined(FAST_GPIO2) + return gpio_read(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); #else return nrf_gpio_pin_read(PIN_SWDIO) & 0x1; #endif @@ -339,8 +406,10 @@ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) { Set the SWDIO/TMS DAP hardware I/O pin to high level. */ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) { -#ifdef FAST_GPIO +#if defined(FAST_GPIO) SET_PIN(pin_swdio); +#elif defined(FAST_GPIO2) + gpio_set(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); #else nrf_gpio_pin_set(PIN_SWDIO); #endif @@ -350,8 +419,10 @@ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) { Set the SWDIO/TMS DAP hardware I/O pin to low level. */ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) { -#ifdef FAST_GPIO +#if defined(FAST_GPIO) CLEAR_PIN(pin_swdio); +#elif defined(FAST_GPIO2) + gpio_clear(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); #else nrf_gpio_pin_clear(PIN_SWDIO); #endif @@ -361,8 +432,10 @@ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) { \return Current status of the SWDIO DAP hardware I/O pin. */ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) { -#ifdef FAST_GPIO +#if defined(FAST_GPIO) return READ_PIN(pin_swdio); +#elif defined(FAST_GPIO2) + return gpio_read(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); #else return nrf_gpio_pin_read(PIN_SWDIO) & 0x1; #endif @@ -372,12 +445,18 @@ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) { \param bit Output value for the SWDIO DAP hardware I/O pin. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit) { -#ifdef FAST_GPIO +#if defined(FAST_GPIO) if (bit & 0x1) { SET_PIN(pin_swdio); } else { CLEAR_PIN(pin_swdio); } +#elif defined(FAST_GPIO2) + if (bit & 0x1) { + gpio_set(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); + } else { + gpio_clear(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); + } #else if (bit & 0x1) { nrf_gpio_pin_set(PIN_SWDIO); @@ -392,8 +471,10 @@ Configure the SWDIO DAP hardware I/O pin to output mode. This function is called prior \ref PIN_SWDIO_OUT function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) { -#ifdef FAST_GPIO +#if defined(FAST_GPIO) SET_OUTPUT_DIR(pin_swdio); +#elif defined(FAST_GPIO2) + gpio_set_output_dir(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); #else nrf_gpio_pin_dir_set(PIN_SWDIO, NRF_GPIO_PIN_DIR_OUTPUT); #endif @@ -404,10 +485,14 @@ Configure the SWDIO DAP hardware I/O pin to input mode. This function is called prior \ref PIN_SWDIO_IN function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) { -#ifdef FAST_GPIO +#if defined(FAST_GPIO) CONFIG_PIN(pin_swdio, NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); +#elif defined(FAST_GPIO2) + gpio_config(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO), + NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, + NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); #else nrf_gpio_pin_dir_set(PIN_SWDIO, NRF_GPIO_PIN_DIR_INPUT); #endif From c26bafb7f2b3ae663f0dc8129d4a85c806f4923b Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 28 Jul 2021 12:22:50 +0200 Subject: [PATCH 435/617] nrf52820_hic: switch all GPIO to DAPLink version of Nordic HAL --- records/hic_hal/nrf52820.yaml | 2 +- .../override_nrf52833_dk/IO_Config_Override.h | 2 +- source/hic_hal/nordic/nrf52820/DAP_config.h | 168 +++--------------- source/hic_hal/nordic/nrf52820/IO_Config.h | 4 +- source/hic_hal/nordic/nrf52820/dl_nrf_gpio.h | 135 ++++++++++++++ source/hic_hal/nordic/nrf52820/gpio.c | 41 ++++- source/hic_hal/nordic/nrf52820/sdk.c | 27 ++- 7 files changed, 218 insertions(+), 161 deletions(-) create mode 100644 source/hic_hal/nordic/nrf52820/dl_nrf_gpio.h diff --git a/records/hic_hal/nrf52820.yaml b/records/hic_hal/nrf52820.yaml index eef4eba89..e0ec88a0e 100644 --- a/records/hic_hal/nrf52820.yaml +++ b/records/hic_hal/nrf52820.yaml @@ -5,7 +5,7 @@ common: - Cortex-M4 macros: - INTERFACE_NRF52820 - # - FAST_GPIO + - FAST_GPIO - NRF52820_XXAA - DAPLINK_HIC_ID=0x6E052820 # DAPLINK_HIC_ID_NRF52820 - OS_CLOCK=64000000 diff --git a/source/board/override_nrf52833_dk/IO_Config_Override.h b/source/board/override_nrf52833_dk/IO_Config_Override.h index 43271dcad..760836875 100644 --- a/source/board/override_nrf52833_dk/IO_Config_Override.h +++ b/source/board/override_nrf52833_dk/IO_Config_Override.h @@ -26,7 +26,7 @@ #include "compiler.h" #include "daplink.h" -#include "nrf_gpio.h" +#include "dl_nrf_gpio.h" // This GPIO configuration is only valid for the nrf52820 HIC COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_NRF52820); diff --git a/source/hic_hal/nordic/nrf52820/DAP_config.h b/source/hic_hal/nordic/nrf52820/DAP_config.h index 4e25424b8..8e49de5b2 100644 --- a/source/hic_hal/nordic/nrf52820/DAP_config.h +++ b/source/hic_hal/nordic/nrf52820/DAP_config.h @@ -178,100 +178,6 @@ __STATIC_INLINE void PORT_JTAG_SETUP (void) { ; } -#if defined(FAST_GPIO) || defined(FAST_GPIO2) - -extern NRF_GPIO_Type *pin_swclk_reg; -extern NRF_GPIO_Type *pin_swdio_reg; -extern uint32_t pin_swclk_idx; -extern uint32_t pin_swdio_idx; - -#if (GPIO_COUNT == 1) -#define INIT_PIN(id, pin) \ - { \ - NRFX_ASSERT(nrf_gpio_pin_present_check(pin)); \ - id##_reg = NRF_P0; \ - id##_idx = pin; \ - } -#else -#define INIT_PIN(id, pin) \ - { \ - NRFX_ASSERT(nrf_gpio_pin_present_check(pin)); \ - if (pin < P0_PIN_NUM) { \ - id##_reg = NRF_P0; \ - id##_idx = pin; \ - } else { \ - id##_reg = NRF_P1; \ - id##_idx = pin & 0x1F; \ - } \ - } -#endif - -#define CONFIG_PIN(pin, dir, input, pull, drive, sense) \ - gpio_config(pin##_reg, pin##_idx, dir, input, pull, drive, sense) - -#define SET_PIN(pin) \ - pin##_reg->OUTSET = (1UL << pin##_idx) -#define CLEAR_PIN(pin) \ - pin##_reg->OUTCLR = (1UL << pin##_idx) -#define READ_PIN(pin) \ - (((pin##_reg->IN) >> pin##_idx) & 1UL) -#define READ_PIN_OUT(pin) \ - (((pin##_reg->OUT) >> pin##_idx) & 1UL) -#define SET_OUTPUT_DIR(pin) \ - pin##_reg->DIRSET = (1UL << pin##_idx) - -__STATIC_INLINE void gpio_config( - NRF_GPIO_Type *reg, - uint32_t idx, - nrf_gpio_pin_dir_t dir, - nrf_gpio_pin_input_t input, - nrf_gpio_pin_pull_t pull, - nrf_gpio_pin_drive_t drive, - nrf_gpio_pin_sense_t sense) -{ - reg->PIN_CNF[idx] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos) - | ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) - | ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos) - | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) - | ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos); -} - -__STATIC_INLINE void gpio_set(NRF_GPIO_Type *reg, uint32_t idx) -{ - reg->OUTSET = (1UL << idx); -} - -__STATIC_INLINE void gpio_clear(NRF_GPIO_Type *reg, uint32_t idx) -{ - reg->OUTCLR = (1UL << idx); -} - -__STATIC_INLINE uint32_t gpio_read(NRF_GPIO_Type *reg, uint32_t idx) -{ - return ((reg->IN >> idx) & 1UL); -} - -__STATIC_INLINE uint32_t gpio_out_read(NRF_GPIO_Type *reg, uint32_t idx) -{ - return ((reg->OUT >> idx) & 1UL); -} - -__STATIC_INLINE void gpio_set_output_dir(NRF_GPIO_Type *reg, uint32_t idx) -{ - reg->DIRSET = (1UL << idx); -} - -#if (GPIO_COUNT == 1) -#define GPIO_REG(pin) NRF_P0 -#define GPIO_IDX(pin) (pin) -#else -#define GPIO_REG(pin) (((pin) < P0_PIN_NUM) ? NRF_P0 : NRF_P1) -#define GPIO_IDX(pin) (((pin) < P0_PIN_NUM) ? (pin) : ((pin) & 0x1F)) -#endif - - -#endif - /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET. Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: - SWCLK, SWDIO, nRESET to output mode and set to default high level. @@ -279,22 +185,13 @@ Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: */ __STATIC_INLINE void PORT_SWD_SETUP (void) { #if defined(FAST_GPIO) - INIT_PIN(pin_swclk, PIN_SWCLK); - INIT_PIN(pin_swdio, PIN_SWDIO); - CONFIG_PIN(pin_swclk, NRF_GPIO_PIN_DIR_OUTPUT, - NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); - SET_PIN(pin_swclk); - CONFIG_PIN(pin_swdio, NRF_GPIO_PIN_DIR_OUTPUT, - NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); - SET_PIN(pin_swdio); -#elif defined(FAST_GPIO2) - gpio_config(GPIO_REG(PIN_SWCLK), GPIO_IDX(PIN_SWCLK), + COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(PIN_SWCLK)); + COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(PIN_SWDIO)); + gpio_cfg(GPIO_REG(PIN_SWCLK), GPIO_IDX(PIN_SWCLK), NRF_GPIO_PIN_DIR_OUTPUT, NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); gpio_set(GPIO_REG(PIN_SWCLK), GPIO_IDX(PIN_SWCLK)); - gpio_config(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO), + gpio_cfg(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO), NRF_GPIO_PIN_DIR_OUTPUT, NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); gpio_set(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); @@ -322,24 +219,17 @@ Disables the DAP Hardware I/O pins which configures: */ __STATIC_INLINE void PORT_OFF (void) { #if defined(FAST_GPIO) - CONFIG_PIN(pin_swclk, NRF_GPIO_PIN_DIR_INPUT, - NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); - CONFIG_PIN(pin_swdio, NRF_GPIO_PIN_DIR_INPUT, - NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); -#elif defined(FAST_GPIO2) - gpio_config(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO), - NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, + gpio_cfg(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO), + NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); - gpio_config(GPIO_REG(PIN_SWCLK), GPIO_IDX(PIN_SWCLK), - NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, + gpio_cfg(GPIO_REG(PIN_SWCLK), GPIO_IDX(PIN_SWCLK), + NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); #else - nrf_gpio_cfg_input(PIN_SWCLK, NRF_GPIO_PIN_NOPULL); - nrf_gpio_cfg_input(PIN_SWDIO, NRF_GPIO_PIN_NOPULL); + nrf_gpio_cfg_default(PIN_SWCLK); + nrf_gpio_cfg_default(PIN_SWDIO); #ifdef PIN_nRESET - nrf_gpio_cfg_input(PIN_nRESET, NRF_GPIO_PIN_NOPULL); + nrf_gpio_cfg_default(PIN_nRESET); #endif #endif } @@ -352,8 +242,6 @@ __STATIC_INLINE void PORT_OFF (void) { */ __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) { #if defined(FAST_GPIO) - return READ_PIN_OUT(pin_swclk); -#elif defined(FAST_GPIO2) return gpio_out_read(GPIO_REG(PIN_SWCLK), GPIO_IDX(PIN_SWCLK)); #else return nrf_gpio_pin_out_read(PIN_SWCLK); @@ -365,8 +253,6 @@ Set the SWCLK/TCK DAP hardware I/O pin to high level. */ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) { #if defined(FAST_GPIO) - SET_PIN(pin_swclk); -#elif defined(FAST_GPIO2) gpio_set(GPIO_REG(PIN_SWCLK), GPIO_IDX(PIN_SWCLK)); #else nrf_gpio_pin_set(PIN_SWCLK); @@ -378,8 +264,6 @@ Set the SWCLK/TCK DAP hardware I/O pin to low level. */ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) { #if defined(FAST_GPIO) - CLEAR_PIN(pin_swclk); -#elif defined(FAST_GPIO2) gpio_clear(GPIO_REG(PIN_SWCLK), GPIO_IDX(PIN_SWCLK)); #else nrf_gpio_pin_clear(PIN_SWCLK); @@ -394,8 +278,6 @@ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) { */ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) { #if defined(FAST_GPIO) - return READ_PIN(pin_swdio); -#elif defined(FAST_GPIO2) return gpio_read(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); #else return nrf_gpio_pin_read(PIN_SWDIO) & 0x1; @@ -407,8 +289,6 @@ Set the SWDIO/TMS DAP hardware I/O pin to high level. */ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) { #if defined(FAST_GPIO) - SET_PIN(pin_swdio); -#elif defined(FAST_GPIO2) gpio_set(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); #else nrf_gpio_pin_set(PIN_SWDIO); @@ -420,8 +300,6 @@ Set the SWDIO/TMS DAP hardware I/O pin to low level. */ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) { #if defined(FAST_GPIO) - CLEAR_PIN(pin_swdio); -#elif defined(FAST_GPIO2) gpio_clear(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); #else nrf_gpio_pin_clear(PIN_SWDIO); @@ -433,8 +311,6 @@ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) { */ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) { #if defined(FAST_GPIO) - return READ_PIN(pin_swdio); -#elif defined(FAST_GPIO2) return gpio_read(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); #else return nrf_gpio_pin_read(PIN_SWDIO) & 0x1; @@ -446,12 +322,6 @@ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) { */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit) { #if defined(FAST_GPIO) - if (bit & 0x1) { - SET_PIN(pin_swdio); - } else { - CLEAR_PIN(pin_swdio); - } -#elif defined(FAST_GPIO2) if (bit & 0x1) { gpio_set(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); } else { @@ -472,8 +342,6 @@ called prior \ref PIN_SWDIO_OUT function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) { #if defined(FAST_GPIO) - SET_OUTPUT_DIR(pin_swdio); -#elif defined(FAST_GPIO2) gpio_set_output_dir(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); #else nrf_gpio_pin_dir_set(PIN_SWDIO, NRF_GPIO_PIN_DIR_OUTPUT); @@ -486,11 +354,7 @@ called prior \ref PIN_SWDIO_IN function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) { #if defined(FAST_GPIO) - CONFIG_PIN(pin_swdio, NRF_GPIO_PIN_DIR_INPUT, - NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); -#elif defined(FAST_GPIO2) - gpio_config(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO), + gpio_cfg(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO), NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); #else @@ -585,8 +449,12 @@ It is recommended to provide the following LEDs for status indication: */ __STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) { #ifdef LED_CONNECTED +#if defined(FAST_GPIO) + gpio_write(GPIO_REG(LED_CONNECTED), GPIO_IDX(LED_CONNECTED), bit ? 0 : 1); +#else nrf_gpio_pin_write(LED_CONNECTED, bit ? 0 : 1); #endif +#endif } /** Debug Unit: Set status Target Running LED. @@ -596,8 +464,12 @@ __STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) { */ __STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) { #ifdef LED_RUNNING +#if defined(FAST_GPIO) + gpio_write(GPIO_REG(LED_RUNNING), GPIO_IDX(LED_RUNNING), bit ? 0 : 1); +#else nrf_gpio_pin_write(LED_RUNNING, bit ? 0 : 1); #endif +#endif } ///@} diff --git a/source/hic_hal/nordic/nrf52820/IO_Config.h b/source/hic_hal/nordic/nrf52820/IO_Config.h index 8cbbf74d9..b80f4799c 100644 --- a/source/hic_hal/nordic/nrf52820/IO_Config.h +++ b/source/hic_hal/nordic/nrf52820/IO_Config.h @@ -34,12 +34,12 @@ #include "compiler.h" #include "daplink.h" -#include "nrf_gpio.h" +#include "dl_nrf_gpio.h" // This GPIO configuration is only valid for the nrf52820 HIC COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_NRF52820); -#define NRF52820_DYNAMIC_PIN +#define NRF528XX_DYNAMIC_PIN #define GPIO_LED_ACTIVE_STATE 1 extern uint32_t uart_tx_pin; diff --git a/source/hic_hal/nordic/nrf52820/dl_nrf_gpio.h b/source/hic_hal/nordic/nrf52820/dl_nrf_gpio.h new file mode 100644 index 000000000..bd63c962d --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/dl_nrf_gpio.h @@ -0,0 +1,135 @@ +/** + * @file dl_nrf_gpio.h + * @brief DAPLink GPIO access functions for nrf52820/nrf52833 + * + * DAPLink Interface Firmware + * Copyright (c) 2021, Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DAPLINK_NRF_GPIO_H__ +#define __DAPLINK_NRF_GPIO_H__ + +/* This file provides alternate functions to nrf_gpio.h to support + * dynamically nRF52820 and nRF52833. + * For nRF52820 (modules/nrfx/mdk/nrf52820_peripherals.h): + * #define GPIO_COUNT 1 + * #define P0_FEATURE_PINS_PRESENT \ + * (nrf52_errata_230() ? 0xF0168E3Ful : 0x7017C1FFul) + * For nRF52833 (modules/nrfx/mdk/nrf52833_peripherals.h): + * #define GPIO_COUNT 2 + * #define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL + * #define P1_FEATURE_PINS_PRESENT 0x000003FFUL + */ + +#include "nrf_gpio.h" + +#ifndef NRF_P1 +#define NRF_P1_BASE 0x50000300UL +#define NRF_P1 ((NRF_GPIO_Type*) NRF_P1_BASE) +#endif + +#define GPIO_REG(pin) (((pin) < 32) ? NRF_P0 : NRF_P1) +#define GPIO_IDX(pin) (((pin) < 32) ? (pin) : ((pin) & 0x1F)) + +/* + * 0xF0168E3FUL // 11110000000101101000111000111111 + * 0x7017C1FFUL // 01110000000101111100000111111111 + */ + +/* Assuming nrf52_errata_230() returns false */ +#define NRF52820_P0_PINS (0x7017C1FFUL) + +#if defined(DEVELOP_IN_NRF52833) +#define NRF52820_P0_MASK (NRF52820_P0_PINS | 0x03003800) +#else +#define NRF52820_P0_MASK (NRF52820_P0_PINS) +#endif + +#define GPIO_CHECK_PRESENT_NRF52820(pin) \ + ((((pin) >> 5) == 0) ? ((NRF52820_P0_MASK & (1 << ((pin) & 0x1F))) ? 1 : 0) : 0) + +#define NRF52833_P0_PINS 0xFFFFFFFFUL +#define NRF52833_P1_PINS 0x000003FFUL + +#define GPIO_CHECK_PRESENT_NRF52833(pin) \ + (((pin) >> 5) == 0) ? ((NRF52833_P0_PINS & (1 << ((pin) & 0x1F))) ? 1 : 0) : \ + ((((pin) >> 5) == 1) ? ((NRF52833_P1_PINS & (1 << ((pin) & 0x1F))) ? 1 : 0) : 0) + +/** @brief Pin configuration function */ +__STATIC_INLINE \ +void gpio_cfg(NRF_GPIO_Type *reg, uint32_t idx, + nrf_gpio_pin_dir_t dir, nrf_gpio_pin_input_t input, + nrf_gpio_pin_pull_t pull, nrf_gpio_pin_drive_t drive, + nrf_gpio_pin_sense_t sense) +{ + reg->PIN_CNF[idx] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos) + | ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) + | ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos) + | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) + | ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos); +} + +/** @brief Pin configuration as output */ +__STATIC_INLINE void gpio_cfg_output(NRF_GPIO_Type *reg, uint32_t idx) +{ + gpio_cfg(reg, idx, NRF_GPIO_PIN_DIR_OUTPUT, NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); +} + +/** @brief Pin configuration as input */ +__STATIC_INLINE void gpio_cfg_input(NRF_GPIO_Type *reg, uint32_t idx, + nrf_gpio_pin_pull_t pull_config) +{ + gpio_cfg(reg, idx, NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, + pull_config, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); +} + +/** @brief Pin configuration as input */ +__STATIC_INLINE void gpio_set(NRF_GPIO_Type *reg, uint32_t idx) +{ + reg->OUTSET = (1UL << idx); +} + +__STATIC_INLINE void gpio_clear(NRF_GPIO_Type *reg, uint32_t idx) +{ + reg->OUTCLR = (1UL << idx); +} + +__STATIC_INLINE uint32_t gpio_read(NRF_GPIO_Type *reg, uint32_t idx) +{ + return ((reg->IN >> idx) & 1UL); +} + +__STATIC_INLINE uint32_t gpio_out_read(NRF_GPIO_Type *reg, uint32_t idx) +{ + return ((reg->OUT >> idx) & 1UL); +} + +__STATIC_INLINE void gpio_set_output_dir(NRF_GPIO_Type *reg, uint32_t idx) +{ + reg->DIRSET = (1UL << idx); +} + +__STATIC_INLINE void gpio_write(NRF_GPIO_Type *reg, uint32_t idx, uint32_t value) +{ + if (value == 0) { + gpio_clear(reg, idx); + } else { + gpio_set(reg, idx); + } +} + +#endif diff --git a/source/hic_hal/nordic/nrf52820/gpio.c b/source/hic_hal/nordic/nrf52820/gpio.c index 1b316867f..0d807f327 100644 --- a/source/hic_hal/nordic/nrf52820/gpio.c +++ b/source/hic_hal/nordic/nrf52820/gpio.c @@ -23,13 +23,6 @@ #include "IO_config.h" -#ifdef FAST_GPIO -NRF_GPIO_Type *pin_swclk_reg; -NRF_GPIO_Type *pin_swdio_reg; -uint32_t pin_swclk_idx; -uint32_t pin_swdio_idx; -#endif - #if (defined(GPIO_LED_ACTIVE_STATE) && (GPIO_LED_ACTIVE_STATE == 1)) #define GPIO_LED_STATE(state) (state ? 1 : 0) #else @@ -38,6 +31,23 @@ uint32_t pin_swdio_idx; void gpio_init(void) { +#if defined(FAST_GPIO) +#ifdef LED_PWR + gpio_cfg_output(GPIO_REG(LED_PWR), GPIO_IDX(LED_PWR)); + gpio_write(GPIO_REG(LED_PWR), GPIO_IDX(LED_PWR), GPIO_LED_STATE(1)); +#endif +#ifdef LED_CONNECTED + gpio_cfg_output(GPIO_REG(LED_CONNECTED), GPIO_IDX(LED_CONNECTED)); +#endif +#ifdef LED_RUNNING + gpio_cfg_output(GPIO_REG(LED_RUNNING), GPIO_IDX(LED_RUNNING)); +#endif + gpio_cfg_output(GPIO_REG(LED_HID), GPIO_IDX(LED_HID)); + gpio_cfg_output(GPIO_REG(LED_MSC), GPIO_IDX(LED_MSC)); + gpio_cfg_output(GPIO_REG(LED_CDC), GPIO_IDX(LED_CDC)); + + gpio_cfg_input(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON), RESET_BUTTON_PULL); +#else #ifdef LED_PWR nrf_gpio_cfg_output(LED_PWR); nrf_gpio_pin_write(LED_PWR, GPIO_LED_STATE(1)); @@ -53,21 +63,34 @@ void gpio_init(void) nrf_gpio_cfg_output(LED_CDC); nrf_gpio_cfg_input(RESET_BUTTON, RESET_BUTTON_PULL); +#endif } void gpio_set_hid_led(gpio_led_state_t state) { +#if defined(FAST_GPIO) + gpio_write(GPIO_REG(LED_HID), GPIO_IDX(LED_HID), GPIO_LED_STATE(state)); +#else nrf_gpio_pin_write(LED_HID, GPIO_LED_STATE(state)); +#endif } void gpio_set_cdc_led(gpio_led_state_t state) { +#if defined(FAST_GPIO) + gpio_write(GPIO_REG(LED_CDC), GPIO_IDX(LED_CDC), GPIO_LED_STATE(state)); +#else nrf_gpio_pin_write(LED_CDC, GPIO_LED_STATE(state)); +#endif } void gpio_set_msc_led(gpio_led_state_t state) { +#if defined(FAST_GPIO) + gpio_write(GPIO_REG(LED_MSC), GPIO_IDX(LED_MSC), GPIO_LED_STATE(state)); +#else nrf_gpio_pin_write(LED_MSC, GPIO_LED_STATE(state)); +#endif } uint8_t gpio_get_reset_btn_no_fwrd(void) @@ -77,7 +100,11 @@ uint8_t gpio_get_reset_btn_no_fwrd(void) uint8_t gpio_get_reset_btn_fwrd(void) { +#if defined(FAST_GPIO) + return gpio_read(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON)) ? 0 : 1; +#else return nrf_gpio_pin_read(RESET_BUTTON) ? 0 : 1; +#endif } void gpio_set_board_power(bool powerEnabled) diff --git a/source/hic_hal/nordic/nrf52820/sdk.c b/source/hic_hal/nordic/nrf52820/sdk.c index 98ac8ce5f..663e11458 100644 --- a/source/hic_hal/nordic/nrf52820/sdk.c +++ b/source/hic_hal/nordic/nrf52820/sdk.c @@ -22,19 +22,42 @@ #include "device.h" #include "IO_config.h" #include "daplink.h" +#include "compiler.h" #include "util.h" -#ifdef NRF52820_DYNAMIC_PIN +#ifdef NRF528XX_DYNAMIC_PIN uint32_t uart_tx_pin; uint32_t uart_rx_pin; uint32_t sw_reset_pin; uint32_t led_usb_pin; uint32_t led_pwr_pin; + +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52833(NRF52833_RESET_PIN)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52833(NRF52833_USB_LED_PIN)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52833(NRF52833_PWR_LED_PIN)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52833(NRF52833_UART_TX_PIN)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52833(NRF52833_UART_RX_PIN)); + +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_RESET_PIN)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_USB_LED_PIN)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_PWR_LED_PIN)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_UART_TX_PIN)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_UART_RX_PIN)); +#else +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(UART_RX_PIN)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(UART_TX_PIN)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(RESET_BUTTON)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(LED_HID)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(LED_MSC)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(LED_CDC)); +#ifdef LED_PWR +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(LED_PWR)); +#endif #endif void sdk_init() { -#ifdef NRF52820_DYNAMIC_PIN +#ifdef NRF528XX_DYNAMIC_PIN if (NRF_FICR->INFO.PART == 0x52833) { // nRF52833 sw_reset_pin = NRF52833_RESET_PIN; From 14bc677e1e6e5230aae51264332504bdd04593bd Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 28 Jul 2021 12:33:26 +0200 Subject: [PATCH 436/617] nrf52820_hic: remove old GPIO implementation --- records/hic_hal/nrf52820.yaml | 1 - source/hic_hal/nordic/nrf52820/DAP_config.h | 81 +-------------------- source/hic_hal/nordic/nrf52820/gpio.c | 34 --------- 3 files changed, 4 insertions(+), 112 deletions(-) diff --git a/records/hic_hal/nrf52820.yaml b/records/hic_hal/nrf52820.yaml index e0ec88a0e..1394cacef 100644 --- a/records/hic_hal/nrf52820.yaml +++ b/records/hic_hal/nrf52820.yaml @@ -5,7 +5,6 @@ common: - Cortex-M4 macros: - INTERFACE_NRF52820 - - FAST_GPIO - NRF52820_XXAA - DAPLINK_HIC_ID=0x6E052820 # DAPLINK_HIC_ID_NRF52820 - OS_CLOCK=64000000 diff --git a/source/hic_hal/nordic/nrf52820/DAP_config.h b/source/hic_hal/nordic/nrf52820/DAP_config.h index 8e49de5b2..84b59eded 100644 --- a/source/hic_hal/nordic/nrf52820/DAP_config.h +++ b/source/hic_hal/nordic/nrf52820/DAP_config.h @@ -178,13 +178,16 @@ __STATIC_INLINE void PORT_JTAG_SETUP (void) { ; } +#ifdef PIN_nRESET +#error "Reset PIN not supported" +#endif + /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET. Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: - SWCLK, SWDIO, nRESET to output mode and set to default high level. - TDI, nTRST to HighZ mode (pins are unused in SWD mode). */ __STATIC_INLINE void PORT_SWD_SETUP (void) { -#if defined(FAST_GPIO) COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(PIN_SWCLK)); COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(PIN_SWDIO)); gpio_cfg(GPIO_REG(PIN_SWCLK), GPIO_IDX(PIN_SWCLK), @@ -195,22 +198,6 @@ __STATIC_INLINE void PORT_SWD_SETUP (void) { NRF_GPIO_PIN_DIR_OUTPUT, NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); gpio_set(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); -#else - nrf_gpio_cfg(PIN_SWCLK, NRF_GPIO_PIN_DIR_OUTPUT, - NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); - nrf_gpio_pin_set(PIN_SWCLK); - nrf_gpio_cfg(PIN_SWDIO, NRF_GPIO_PIN_DIR_OUTPUT, - NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); - nrf_gpio_pin_set(PIN_SWDIO); -#ifdef PIN_nRESET - nrf_gpio_cfg(PIN_nRESET, NRF_GPIO_PIN_DIR_OUTPUT, - NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); - nrf_gpio_pin_set(PIN_nRESET); -#endif -#endif } /** Disable JTAG/SWD I/O Pins. @@ -218,20 +205,12 @@ Disables the DAP Hardware I/O pins which configures: - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode. */ __STATIC_INLINE void PORT_OFF (void) { -#if defined(FAST_GPIO) gpio_cfg(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO), NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); gpio_cfg(GPIO_REG(PIN_SWCLK), GPIO_IDX(PIN_SWCLK), NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); -#else - nrf_gpio_cfg_default(PIN_SWCLK); - nrf_gpio_cfg_default(PIN_SWDIO); -#ifdef PIN_nRESET - nrf_gpio_cfg_default(PIN_nRESET); -#endif -#endif } @@ -241,33 +220,21 @@ __STATIC_INLINE void PORT_OFF (void) { \return Current status of the SWCLK/TCK DAP hardware I/O pin. */ __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) { -#if defined(FAST_GPIO) return gpio_out_read(GPIO_REG(PIN_SWCLK), GPIO_IDX(PIN_SWCLK)); -#else - return nrf_gpio_pin_out_read(PIN_SWCLK); -#endif } /** SWCLK/TCK I/O pin: Set Output to High. Set the SWCLK/TCK DAP hardware I/O pin to high level. */ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) { -#if defined(FAST_GPIO) gpio_set(GPIO_REG(PIN_SWCLK), GPIO_IDX(PIN_SWCLK)); -#else - nrf_gpio_pin_set(PIN_SWCLK); -#endif } /** SWCLK/TCK I/O pin: Set Output to Low. Set the SWCLK/TCK DAP hardware I/O pin to low level. */ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) { -#if defined(FAST_GPIO) gpio_clear(GPIO_REG(PIN_SWCLK), GPIO_IDX(PIN_SWCLK)); -#else - nrf_gpio_pin_clear(PIN_SWCLK); -#endif } @@ -277,63 +244,39 @@ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) { \return Current status of the SWDIO/TMS DAP hardware I/O pin. */ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) { -#if defined(FAST_GPIO) return gpio_read(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); -#else - return nrf_gpio_pin_read(PIN_SWDIO) & 0x1; -#endif } /** SWDIO/TMS I/O pin: Set Output to High. Set the SWDIO/TMS DAP hardware I/O pin to high level. */ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) { -#if defined(FAST_GPIO) gpio_set(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); -#else - nrf_gpio_pin_set(PIN_SWDIO); -#endif } /** SWDIO/TMS I/O pin: Set Output to Low. Set the SWDIO/TMS DAP hardware I/O pin to low level. */ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) { -#if defined(FAST_GPIO) gpio_clear(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); -#else - nrf_gpio_pin_clear(PIN_SWDIO); -#endif } /** SWDIO I/O pin: Get Input (used in SWD mode only). \return Current status of the SWDIO DAP hardware I/O pin. */ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) { -#if defined(FAST_GPIO) return gpio_read(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); -#else - return nrf_gpio_pin_read(PIN_SWDIO) & 0x1; -#endif } /** SWDIO I/O pin: Set Output (used in SWD mode only). \param bit Output value for the SWDIO DAP hardware I/O pin. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit) { -#if defined(FAST_GPIO) if (bit & 0x1) { gpio_set(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); } else { gpio_clear(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); } -#else - if (bit & 0x1) { - nrf_gpio_pin_set(PIN_SWDIO); - } else { - nrf_gpio_pin_clear(PIN_SWDIO); - } -#endif } /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only). @@ -341,11 +284,7 @@ Configure the SWDIO DAP hardware I/O pin to output mode. This function is called prior \ref PIN_SWDIO_OUT function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) { -#if defined(FAST_GPIO) gpio_set_output_dir(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO)); -#else - nrf_gpio_pin_dir_set(PIN_SWDIO, NRF_GPIO_PIN_DIR_OUTPUT); -#endif } /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). @@ -353,13 +292,9 @@ Configure the SWDIO DAP hardware I/O pin to input mode. This function is called prior \ref PIN_SWDIO_IN function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) { -#if defined(FAST_GPIO) gpio_cfg(GPIO_REG(PIN_SWDIO), GPIO_IDX(PIN_SWDIO), NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); -#else - nrf_gpio_pin_dir_set(PIN_SWDIO, NRF_GPIO_PIN_DIR_INPUT); -#endif } @@ -449,11 +384,7 @@ It is recommended to provide the following LEDs for status indication: */ __STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) { #ifdef LED_CONNECTED -#if defined(FAST_GPIO) gpio_write(GPIO_REG(LED_CONNECTED), GPIO_IDX(LED_CONNECTED), bit ? 0 : 1); -#else - nrf_gpio_pin_write(LED_CONNECTED, bit ? 0 : 1); -#endif #endif } @@ -464,11 +395,7 @@ __STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) { */ __STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) { #ifdef LED_RUNNING -#if defined(FAST_GPIO) gpio_write(GPIO_REG(LED_RUNNING), GPIO_IDX(LED_RUNNING), bit ? 0 : 1); -#else - nrf_gpio_pin_write(LED_RUNNING, bit ? 0 : 1); -#endif #endif } diff --git a/source/hic_hal/nordic/nrf52820/gpio.c b/source/hic_hal/nordic/nrf52820/gpio.c index 0d807f327..6162aff26 100644 --- a/source/hic_hal/nordic/nrf52820/gpio.c +++ b/source/hic_hal/nordic/nrf52820/gpio.c @@ -31,7 +31,6 @@ void gpio_init(void) { -#if defined(FAST_GPIO) #ifdef LED_PWR gpio_cfg_output(GPIO_REG(LED_PWR), GPIO_IDX(LED_PWR)); gpio_write(GPIO_REG(LED_PWR), GPIO_IDX(LED_PWR), GPIO_LED_STATE(1)); @@ -47,50 +46,21 @@ void gpio_init(void) gpio_cfg_output(GPIO_REG(LED_CDC), GPIO_IDX(LED_CDC)); gpio_cfg_input(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON), RESET_BUTTON_PULL); -#else -#ifdef LED_PWR - nrf_gpio_cfg_output(LED_PWR); - nrf_gpio_pin_write(LED_PWR, GPIO_LED_STATE(1)); -#endif -#ifdef LED_CONNECTED - nrf_gpio_cfg_output(LED_CONNECTED); -#endif -#ifdef LED_RUNNING - nrf_gpio_cfg_output(LED_RUNNING); -#endif - nrf_gpio_cfg_output(LED_HID); - nrf_gpio_cfg_output(LED_MSC); - nrf_gpio_cfg_output(LED_CDC); - - nrf_gpio_cfg_input(RESET_BUTTON, RESET_BUTTON_PULL); -#endif } void gpio_set_hid_led(gpio_led_state_t state) { -#if defined(FAST_GPIO) gpio_write(GPIO_REG(LED_HID), GPIO_IDX(LED_HID), GPIO_LED_STATE(state)); -#else - nrf_gpio_pin_write(LED_HID, GPIO_LED_STATE(state)); -#endif } void gpio_set_cdc_led(gpio_led_state_t state) { -#if defined(FAST_GPIO) gpio_write(GPIO_REG(LED_CDC), GPIO_IDX(LED_CDC), GPIO_LED_STATE(state)); -#else - nrf_gpio_pin_write(LED_CDC, GPIO_LED_STATE(state)); -#endif } void gpio_set_msc_led(gpio_led_state_t state) { -#if defined(FAST_GPIO) gpio_write(GPIO_REG(LED_MSC), GPIO_IDX(LED_MSC), GPIO_LED_STATE(state)); -#else - nrf_gpio_pin_write(LED_MSC, GPIO_LED_STATE(state)); -#endif } uint8_t gpio_get_reset_btn_no_fwrd(void) @@ -100,11 +70,7 @@ uint8_t gpio_get_reset_btn_no_fwrd(void) uint8_t gpio_get_reset_btn_fwrd(void) { -#if defined(FAST_GPIO) return gpio_read(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON)) ? 0 : 1; -#else - return nrf_gpio_pin_read(RESET_BUTTON) ? 0 : 1; -#endif } void gpio_set_board_power(bool powerEnabled) From 2f8d5ee62d814f92c4e0ce3e56d1471e2beccc79 Mon Sep 17 00:00:00 2001 From: Russ Butler Date: Fri, 30 Jul 2021 11:10:23 -0500 Subject: [PATCH 437/617] Enable SOF events on nRF52840 to fix USB latency CDC device-to-host transmission is started on the SOF interrupt. Without this interrupt CDC device-to-host transmission only start if the is an unrelated USB interrupt to start transmission. This adds a delay when sending data. This patch enables the SOF interrupt so CDC device-to-host transmissions are deterministically started on the next USB frame. --- source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c b/source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c index b4149616c..77159bc0a 100644 --- a/source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c +++ b/source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c @@ -240,6 +240,7 @@ void USBD_Reset (void) { NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk | USBD_INTEN_EPDATA_Msk | USBD_INTEN_EP0SETUP_Msk | + USBD_INTEN_SOF_Msk | USBD_INTEN_EP0DATADONE_Msk ; } From f2b57264308ab9c12828ce8f242966503d440fd9 Mon Sep 17 00:00:00 2001 From: Russ Butler Date: Fri, 30 Jul 2021 11:31:07 -0500 Subject: [PATCH 438/617] Fix dropped uart TX data on nRF52840 If uart data is being transmitted and uart_write_data is called it will start a new transfer and clobber the currently transmitting data. This patch prevents that by only starting a transfer if there is not one occurring already. Additionally to prevent race conditions between interrupt and non-interrupt code, this patch only starts TX from the uart interrupt handler. --- source/hic_hal/nordic/nrf52820/uart.c | 22 +++++++--------------- 1 file changed, 7 insertions(+), 15 deletions(-) diff --git a/source/hic_hal/nordic/nrf52820/uart.c b/source/hic_hal/nordic/nrf52820/uart.c index ce85b15f9..bc3631ab9 100644 --- a/source/hic_hal/nordic/nrf52820/uart.c +++ b/source/hic_hal/nordic/nrf52820/uart.c @@ -47,6 +47,7 @@ uint8_t read_buffer_data[BUFFER_SIZE]; struct { uint8_t rx; uint8_t tx; + uint8_t tx_active; } cb_buf; void uart_handler(uint32_t event); @@ -178,20 +179,8 @@ int32_t uart_write_free(void) int32_t uart_write_data(uint8_t *data, uint16_t size) { - if (size == 0) { - return 0; - } - - uint32_t cnt = 0; - if (circ_buf_count_used(&write_buffer) > 0) { - cb_buf.tx = circ_buf_pop(&write_buffer); - cnt = circ_buf_write(&write_buffer, data, size); - } else { - cb_buf.tx = data[0]; - cnt = circ_buf_write(&write_buffer, data + 1, size - 1) + 1; - } - USART_INSTANCE.Send(&(cb_buf.tx), 1); - + uint32_t cnt = circ_buf_write(&write_buffer, data, size); + NVIC_SetPendingIRQ(USART_IRQ); return cnt; } @@ -213,10 +202,13 @@ void uart_handler(uint32_t event) { USART_INSTANCE.Receive(&(cb_buf.rx), 1); } - if (event & ARM_USART_EVENT_SEND_COMPLETE) { + if ((event & ARM_USART_EVENT_SEND_COMPLETE) || !cb_buf.tx_active) { if (circ_buf_count_used(&write_buffer) > 0) { + cb_buf.tx_active = true; cb_buf.tx = circ_buf_pop(&write_buffer); USART_INSTANCE.Send(&(cb_buf.tx), 1); + } else { + cb_buf.tx_active = false; } } } From 3dc2b470a06b1d6b4ea68a9c509011c7e8ca9de5 Mon Sep 17 00:00:00 2001 From: Russ Butler Date: Tue, 10 Aug 2021 15:18:08 -0500 Subject: [PATCH 439/617] Correct UART pins on the nrf528xx Flip TX and RX so the UART is setup correctly. --- source/hic_hal/nordic/nrf52820/IO_Config.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/source/hic_hal/nordic/nrf52820/IO_Config.h b/source/hic_hal/nordic/nrf52820/IO_Config.h index b80f4799c..6a1ba54fe 100644 --- a/source/hic_hal/nordic/nrf52820/IO_Config.h +++ b/source/hic_hal/nordic/nrf52820/IO_Config.h @@ -86,13 +86,13 @@ extern uint32_t led_pwr_pin; #define NRF52820_RESET_PIN NRF_GPIO_PIN_MAP(0, 6) #define NRF52820_USB_LED_PIN NRF_GPIO_PIN_MAP(0, 14) #define NRF52820_PWR_LED_PIN NRF_GPIO_PIN_MAP(0, 15) -#define NRF52820_UART_TX_PIN NRF_GPIO_PIN_MAP(0, 8) // From IMCU to target -#define NRF52820_UART_RX_PIN NRF_GPIO_PIN_MAP(0, 29) // From target to IMCU +#define NRF52820_UART_TX_PIN NRF_GPIO_PIN_MAP(0, 29) // From IMCU to target +#define NRF52820_UART_RX_PIN NRF_GPIO_PIN_MAP(0, 8) // From target to IMCU #define NRF52833_RESET_PIN NRF_GPIO_PIN_MAP(1, 9) #define NRF52833_USB_LED_PIN NRF_GPIO_PIN_MAP(0, 15) #define NRF52833_PWR_LED_PIN NRF_GPIO_PIN_MAP(0, 17) -#define NRF52833_UART_TX_PIN NRF_GPIO_PIN_MAP(0, 3) // From IMCU to target -#define NRF52833_UART_RX_PIN NRF_GPIO_PIN_MAP(0, 2) // From target to IMCU +#define NRF52833_UART_TX_PIN NRF_GPIO_PIN_MAP(0, 2) // From IMCU to target +#define NRF52833_UART_RX_PIN NRF_GPIO_PIN_MAP(0, 3) // From target to IMCU #endif From 6c0908542e7b09e9eb242f7185747c46910f60ea Mon Sep 17 00:00:00 2001 From: Russ Butler Date: Tue, 10 Aug 2021 15:42:16 -0500 Subject: [PATCH 440/617] Correct UART pins on the nrf528xx docs Flip TX and RX in the nrf528xx docs to match the code. --- docs/hic/nrf52820.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/hic/nrf52820.md b/docs/hic/nrf52820.md index 0abc0b7f8..30af3ab26 100644 --- a/docs/hic/nrf52820.md +++ b/docs/hic/nrf52820.md @@ -27,8 +27,8 @@ Limiting flash usage to 128 KB | SWCLK | O | P0.01 | 3 | | SWDIO | I/O | P0.00 | 2 | | UART | -| UART TX | I | P0.08 | 31 | -| UART RX | O | P0.29 | 32 | +| UART TX | I | P0.29 | 32 | +| UART RX | O | P0.08 | 31 | | Button | | F-RST But. | I | P0.06 | 6 | | LEDs | @@ -48,8 +48,8 @@ Note: | SWCLK | O | P0.01 | 3 | | SWDIO | I/O | P0.00 | 2 | | UART | -| UART TX | I | P0.03 | 31 | -| UART RX | O | P0.02 | 32 | +| UART TX | I | P0.02 | 32 | +| UART RX | O | P0.03 | 31 | | Button | | F-RST But. | I | P1.09 | 6 | | LEDs | From 05bcb0614345aeb8fa50aa8336c9ec41a220c08e Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 28 Jul 2021 23:54:48 +0200 Subject: [PATCH 441/617] nrf52820_hic: add dynamic pin test for nRF52833-DK --- records/board/nrf52833_dk.yaml | 2 + .../override_nrf52833_dk/IO_Config_Override.h | 58 ++++++++++++++++++- 2 files changed, 59 insertions(+), 1 deletion(-) diff --git a/records/board/nrf52833_dk.yaml b/records/board/nrf52833_dk.yaml index 54fcd1bbd..e353e082d 100644 --- a/records/board/nrf52833_dk.yaml +++ b/records/board/nrf52833_dk.yaml @@ -2,5 +2,7 @@ common: macros: - IO_CONFIG_OVERRIDE - DEVELOP_IN_NRF52833 + # - NRF528XX_DYNAMIC_PIN + - UART_EXTERNAL includes: - source/board/override_nrf52833_dk diff --git a/source/board/override_nrf52833_dk/IO_Config_Override.h b/source/board/override_nrf52833_dk/IO_Config_Override.h index 760836875..fb56f3af1 100644 --- a/source/board/override_nrf52833_dk/IO_Config_Override.h +++ b/source/board/override_nrf52833_dk/IO_Config_Override.h @@ -39,13 +39,17 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_NRF52820); // SWDCLK (Output) #define PIN_SWCLK NRF_GPIO_PIN_MAP(0, 4) +// #define PIN_SWCLK NRF_GPIO_PIN_MAP(0, 30) // SWDIO (Input/Output) #define PIN_SWDIO NRF_GPIO_PIN_MAP(0, 5) +// #define PIN_SWDIO NRF_GPIO_PIN_MAP(0, 31) // nRESET Pin #undef PIN_nRESET -// #define PIN_nRESET NRF_GPIO_PIN_MAP(0, 7) + + +#ifndef NRF528XX_DYNAMIC_PIN // Target Running LED (Output) #define LED_RUNNING LED_1 @@ -77,4 +81,56 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_NRF52820); #define UART_TX_PIN NRF_GPIO_PIN_MAP(0, 30) #endif +#else + +/* Use dynamic pin-mapping */ + +extern uint32_t uart_tx_pin; +extern uint32_t uart_rx_pin; +extern uint32_t sw_reset_pin; +extern uint32_t led_usb_pin; +extern uint32_t led_pwr_pin; + +// HID LED +#define LED_HID led_usb_pin + +// MSC LED +#define LED_MSC led_usb_pin + +// CDC LED +#define LED_CDC led_usb_pin + +// POWER LED +#define LED_PWR led_pwr_pin + +// Reset button (SW_RESET) +#define RESET_BUTTON sw_reset_pin +#define RESET_BUTTON_PULL NRF_GPIO_PIN_PULLUP + +// UART +#define UART_TX_PIN uart_tx_pin +#define UART_RX_PIN uart_rx_pin + +/* Use defaults for nRF52820 */ +#define NRF52820_RESET_PIN NRF_GPIO_PIN_MAP(0, 6) +#define NRF52820_USB_LED_PIN NRF_GPIO_PIN_MAP(0, 14) +#define NRF52820_PWR_LED_PIN NRF_GPIO_PIN_MAP(0, 15) +#define NRF52820_UART_TX_PIN NRF_GPIO_PIN_MAP(0, 8) // From IMCU to target +#define NRF52820_UART_RX_PIN NRF_GPIO_PIN_MAP(0, 29) // From target to IMCU + +#define NRF52833_RESET_PIN BUTTON_1 +#define NRF52833_USB_LED_PIN LED_4 +#define NRF52833_PWR_LED_PIN LED_3 +#ifndef UART_EXTERNAL +// This is connected to J-Link +#define NRF52833_UART_TX_PIN NRF_GPIO_PIN_MAP(0, 8) // RxD P0.08 +#define NRF52833_UART_RX_PIN NRF_GPIO_PIN_MAP(0, 6) // TxD P0.06 +#else +// Alternative pin out +#define NRF52833_UART_TX_PIN NRF_GPIO_PIN_MAP(0, 29) // From IMCU to target +#define NRF52833_UART_RX_PIN NRF_GPIO_PIN_MAP(0, 30) // From target to IMCU +#endif + +#endif + #endif From 92aa6783f2362503a0965f90ac9b8d3f39430476 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 17 Aug 2021 10:15:35 -0500 Subject: [PATCH 442/617] nrf52820_hic: Import CMSIS I2C driver --- records/hic_hal/nrf52820.yaml | 1 + .../override_nrf52833_dk/IO_Config_Override.h | 12 + source/hic_hal/nordic/nrf52820/Driver_I2C.h | 223 +++++ .../nordic/nrf52820/I2C_Slave_nRF52820.c | 486 ++++++++++ .../nordic/nrf52820/I2C_Slave_nRF52820.h | 68 ++ source/hic_hal/nordic/nrf52820/IO_Config.h | 10 + source/hic_hal/nordic/nrf52820/RTE_Device.h | 11 + .../nordic/nrf52820/nrfx/drivers/nrfx_twis.c | 857 ++++++++++++++++++ .../nordic/nrf52820/nrfx/drivers/nrfx_twis.h | 403 ++++++++ .../nrf52820/nrfx/drivers/prs/nrfx_prs.h | 155 ++++ .../nordic/nrf52820/nrfx/hal/nrf_twis.h | 745 +++++++++++++++ .../nordic/nrf52820/nrfx/nrfx_config.h | 2 +- .../hic_hal/nordic/nrf52820/nrfx/nrfx_glue.h | 14 +- .../hic_hal/nordic/nrf52820/nrfx/nrfx_log.h | 144 +++ source/hic_hal/nordic/nrf52820/sdk.c | 6 + 15 files changed, 3129 insertions(+), 8 deletions(-) create mode 100644 source/hic_hal/nordic/nrf52820/Driver_I2C.h create mode 100644 source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.c create mode 100644 source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.h create mode 100644 source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_twis.c create mode 100644 source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_twis.h create mode 100644 source/hic_hal/nordic/nrf52820/nrfx/drivers/prs/nrfx_prs.h create mode 100644 source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_twis.h create mode 100644 source/hic_hal/nordic/nrf52820/nrfx/nrfx_log.h diff --git a/records/hic_hal/nrf52820.yaml b/records/hic_hal/nrf52820.yaml index 1394cacef..3e70724cc 100644 --- a/records/hic_hal/nrf52820.yaml +++ b/records/hic_hal/nrf52820.yaml @@ -22,6 +22,7 @@ common: - source/hic_hal/nordic/nrf52820 - source/hic_hal/nordic/nrf52820/cmsis - source/hic_hal/nordic/nrf52820/nrfx + - source/hic_hal/nordic/nrf52820/nrfx/drivers - source/hic_hal/nordic/nrf52820/nrfx/hal tool_specific: diff --git a/source/board/override_nrf52833_dk/IO_Config_Override.h b/source/board/override_nrf52833_dk/IO_Config_Override.h index fb56f3af1..789209f1c 100644 --- a/source/board/override_nrf52833_dk/IO_Config_Override.h +++ b/source/board/override_nrf52833_dk/IO_Config_Override.h @@ -81,6 +81,10 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_NRF52820); #define UART_TX_PIN NRF_GPIO_PIN_MAP(0, 30) #endif +// I2C +#define I2C_SCL_PIN NRF_GPIO_PIN_MAP(0, 27) +#define I2C_SDA_PIN NRF_GPIO_PIN_MAP(0, 26) + #else /* Use dynamic pin-mapping */ @@ -90,6 +94,8 @@ extern uint32_t uart_rx_pin; extern uint32_t sw_reset_pin; extern uint32_t led_usb_pin; extern uint32_t led_pwr_pin; +extern uint32_t i2c_scl_pin; +extern uint32_t i2c_sda_pin; // HID LED #define LED_HID led_usb_pin @@ -110,6 +116,9 @@ extern uint32_t led_pwr_pin; // UART #define UART_TX_PIN uart_tx_pin #define UART_RX_PIN uart_rx_pin +// I2C +#define I2C_SCL_PIN i2c_scl_pin +#define I2C_SDA_PIN i2c_sda_pin /* Use defaults for nRF52820 */ #define NRF52820_RESET_PIN NRF_GPIO_PIN_MAP(0, 6) @@ -131,6 +140,9 @@ extern uint32_t led_pwr_pin; #define NRF52833_UART_RX_PIN NRF_GPIO_PIN_MAP(0, 30) // From target to IMCU #endif +#define NRF52833_I2C_SCL_PIN NRF_GPIO_PIN_MAP(0, 27) +#define NRF52833_I2C_SDA_PIN NRF_GPIO_PIN_MAP(0, 26) + #endif #endif diff --git a/source/hic_hal/nordic/nrf52820/Driver_I2C.h b/source/hic_hal/nordic/nrf52820/Driver_I2C.h new file mode 100644 index 000000000..8ed095a94 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/Driver_I2C.h @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2013-2020 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 31. March 2020 + * $Revision: V2.4 + * + * Project: I2C (Inter-Integrated Circuit) Driver definitions + */ + +/* History: + * Version 2.4 + * Removed volatile from ARM_I2C_STATUS + * Version 2.3 + * ARM_I2C_STATUS made volatile + * Version 2.2 + * Removed function ARM_I2C_MasterTransfer in order to simplify drivers + * and added back parameter "xfer_pending" to functions + * ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive + * Version 2.1 + * Added function ARM_I2C_MasterTransfer and removed parameter "xfer_pending" + * from functions ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive + * Added function ARM_I2C_GetDataCount + * Removed flag "address_nack" from ARM_I2C_STATUS + * Replaced events ARM_I2C_EVENT_MASTER_DONE and ARM_I2C_EVENT_SLAVE_DONE + * with event ARM_I2C_EVENT_TRANSFER_DONE + * Added event ARM_I2C_EVENT_TRANSFER_INCOMPLETE + * Removed parameter "arg" from function ARM_I2C_SignalEvent + * Version 2.0 + * New simplified driver: + * complexity moved to upper layer (especially data handling) + * more unified API for different communication interfaces + * Added: + * Slave Mode + * Changed prefix ARM_DRV -> ARM_DRIVER + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.00 + * Initial release + */ + +#ifndef DRIVER_I2C_H_ +#define DRIVER_I2C_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "Driver_Common.h" + +#define ARM_I2C_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4) /* API version */ + + +#define _ARM_Driver_I2C_(n) Driver_I2C##n +#define ARM_Driver_I2C_(n) _ARM_Driver_I2C_(n) + + +/****** I2C Control Codes *****/ + +#define ARM_I2C_OWN_ADDRESS (0x01UL) ///< Set Own Slave Address; arg = address +#define ARM_I2C_BUS_SPEED (0x02UL) ///< Set Bus Speed; arg = speed +#define ARM_I2C_BUS_CLEAR (0x03UL) ///< Execute Bus clear: send nine clock pulses +#define ARM_I2C_ABORT_TRANSFER (0x04UL) ///< Abort Master/Slave Transmit/Receive + +/*----- I2C Bus Speed -----*/ +#define ARM_I2C_BUS_SPEED_STANDARD (0x01UL) ///< Standard Speed (100kHz) +#define ARM_I2C_BUS_SPEED_FAST (0x02UL) ///< Fast Speed (400kHz) +#define ARM_I2C_BUS_SPEED_FAST_PLUS (0x03UL) ///< Fast+ Speed ( 1MHz) +#define ARM_I2C_BUS_SPEED_HIGH (0x04UL) ///< High Speed (3.4MHz) + + +/****** I2C Address Flags *****/ + +#define ARM_I2C_ADDRESS_10BIT (0x0400UL) ///< 10-bit address flag +#define ARM_I2C_ADDRESS_GC (0x8000UL) ///< General Call flag + + +/** +\brief I2C Status +*/ +typedef struct _ARM_I2C_STATUS { + uint32_t busy : 1; ///< Busy flag + uint32_t mode : 1; ///< Mode: 0=Slave, 1=Master + uint32_t direction : 1; ///< Direction: 0=Transmitter, 1=Receiver + uint32_t general_call : 1; ///< General Call indication (cleared on start of next Slave operation) + uint32_t arbitration_lost : 1; ///< Master lost arbitration (cleared on start of next Master operation) + uint32_t bus_error : 1; ///< Bus error detected (cleared on start of next Master/Slave operation) + uint32_t reserved : 26; +} ARM_I2C_STATUS; + + +/****** I2C Event *****/ +#define ARM_I2C_EVENT_TRANSFER_DONE (1UL << 0) ///< Master/Slave Transmit/Receive finished +#define ARM_I2C_EVENT_TRANSFER_INCOMPLETE (1UL << 1) ///< Master/Slave Transmit/Receive incomplete transfer +#define ARM_I2C_EVENT_SLAVE_TRANSMIT (1UL << 2) ///< Addressed as Slave Transmitter but transmit operation is not set. +#define ARM_I2C_EVENT_SLAVE_RECEIVE (1UL << 3) ///< Addressed as Slave Receiver but receive operation is not set. +#define ARM_I2C_EVENT_ADDRESS_NACK (1UL << 4) ///< Address not acknowledged from Slave +#define ARM_I2C_EVENT_GENERAL_CALL (1UL << 5) ///< Slave addressed with general call address +#define ARM_I2C_EVENT_ARBITRATION_LOST (1UL << 6) ///< Master lost arbitration +#define ARM_I2C_EVENT_BUS_ERROR (1UL << 7) ///< Bus error detected (START/STOP at illegal position) +#define ARM_I2C_EVENT_BUS_CLEAR (1UL << 8) ///< Bus clear finished + + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_I2C_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION + + \fn ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities (void) + \brief Get driver capabilities. + \return \ref ARM_I2C_CAPABILITIES + + \fn int32_t ARM_I2C_Initialize (ARM_I2C_SignalEvent_t cb_event) + \brief Initialize I2C Interface. + \param[in] cb_event Pointer to \ref ARM_I2C_SignalEvent + \return \ref execution_status + + \fn int32_t ARM_I2C_Uninitialize (void) + \brief De-initialize I2C Interface. + \return \ref execution_status + + \fn int32_t ARM_I2C_PowerControl (ARM_POWER_STATE state) + \brief Control I2C Interface Power. + \param[in] state Power state + \return \ref execution_status + + \fn int32_t ARM_I2C_MasterTransmit (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) + \brief Start transmitting data as I2C Master. + \param[in] addr Slave address (7-bit or 10-bit) + \param[in] data Pointer to buffer with data to transmit to I2C Slave + \param[in] num Number of data bytes to transmit + \param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated + \return \ref execution_status + + \fn int32_t ARM_I2C_MasterReceive (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) + \brief Start receiving data as I2C Master. + \param[in] addr Slave address (7-bit or 10-bit) + \param[out] data Pointer to buffer for data to receive from I2C Slave + \param[in] num Number of data bytes to receive + \param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated + \return \ref execution_status + + \fn int32_t ARM_I2C_SlaveTransmit (const uint8_t *data, uint32_t num) + \brief Start transmitting data as I2C Slave. + \param[in] data Pointer to buffer with data to transmit to I2C Master + \param[in] num Number of data bytes to transmit + \return \ref execution_status + + \fn int32_t ARM_I2C_SlaveReceive (uint8_t *data, uint32_t num) + \brief Start receiving data as I2C Slave. + \param[out] data Pointer to buffer for data to receive from I2C Master + \param[in] num Number of data bytes to receive + \return \ref execution_status + + \fn int32_t ARM_I2C_GetDataCount (void) + \brief Get transferred data count. + \return number of data bytes transferred; -1 when Slave is not addressed by Master + + \fn int32_t ARM_I2C_Control (uint32_t control, uint32_t arg) + \brief Control I2C Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \return \ref execution_status + + \fn ARM_I2C_STATUS ARM_I2C_GetStatus (void) + \brief Get I2C status. + \return I2C status \ref ARM_I2C_STATUS + + \fn void ARM_I2C_SignalEvent (uint32_t event) + \brief Signal I2C Events. + \param[in] event \ref I2C_events notification mask +*/ + +typedef void (*ARM_I2C_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_I2C_SignalEvent : Signal I2C Event. + + +/** +\brief I2C Driver Capabilities. +*/ +typedef struct _ARM_I2C_CAPABILITIES { + uint32_t address_10_bit : 1; ///< supports 10-bit addressing + uint32_t reserved : 31; ///< Reserved (must be zero) +} ARM_I2C_CAPABILITIES; + + +/** +\brief Access structure of the I2C Driver. +*/ +typedef struct _ARM_DRIVER_I2C { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_I2C_GetVersion : Get driver version. + ARM_I2C_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_I2C_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_I2C_SignalEvent_t cb_event); ///< Pointer to \ref ARM_I2C_Initialize : Initialize I2C Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_I2C_Uninitialize : De-initialize I2C Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_I2C_PowerControl : Control I2C Interface Power. + int32_t (*MasterTransmit) (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterTransmit : Start transmitting data as I2C Master. + int32_t (*MasterReceive) (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterReceive : Start receiving data as I2C Master. + int32_t (*SlaveTransmit) ( const uint8_t *data, uint32_t num); ///< Pointer to \ref ARM_I2C_SlaveTransmit : Start transmitting data as I2C Slave. + int32_t (*SlaveReceive) ( uint8_t *data, uint32_t num); ///< Pointer to \ref ARM_I2C_SlaveReceive : Start receiving data as I2C Slave. + int32_t (*GetDataCount) (void); ///< Pointer to \ref ARM_I2C_GetDataCount : Get transferred data count. + int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_I2C_Control : Control I2C Interface. + ARM_I2C_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_I2C_GetStatus : Get I2C status. +} const ARM_DRIVER_I2C; + +#ifdef __cplusplus +} +#endif + +#endif /* DRIVER_I2C_H_ */ diff --git a/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.c b/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.c new file mode 100644 index 000000000..3f19f6f19 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.c @@ -0,0 +1,486 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2021 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 23. July 2021 + * $Revision: V1.0 + * + * Driver: Driver_I2C1 + * Configured: via RTE_Device.h configuration file + * Project: I2C Slave Driver for Nordic Semiconductor nRF52820 + * -------------------------------------------------------------------------- + * Use the following configuration settings in the middleware component + * to connect to this driver. + * + * Configuration Setting Value I2C Interface + * --------------------- ----- ------------- + * Connect to hardware via Driver_I2C# = 1 use TWIS1 + * -------------------------------------------------------------------------- + * Note: + * Only slave implementation + * -------------------------------------------------------------------------- */ + +/* History: + * Version 1.0 + * Initial release + */ + +#include "I2C_Slave_nRF52820.h" + +#define ARM_I2C_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) /* driver version */ + +/* Driver Version */ +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_I2C_API_VERSION, + ARM_I2C_DRV_VERSION +}; + +/* Driver Capabilities */ +static const ARM_I2C_CAPABILITIES DriverCapabilities = { + 0U // Does not support 10-bit addressing +#if (defined(ARM_I2C_API_VERSION) && (ARM_I2C_API_VERSION >= 0x203U)) +, 0U // Reserved bits +#endif +}; + +/* TWIS0 */ +#if RTE_TWIS0 +static I2C_INFO I2C0_Info; +static void TWIS0_event_handler (nrfx_twis_evt_t const * p_event); + +static I2C_RESOURCES I2C0_Resources = { + // nrfx_twis + {NRF_TWIS0, 0}, + TWIS0_event_handler, + &I2C0_Info +}; + +extern void nrfx_twis_0_irq_handler(void); + +void SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler (void) { + nrfx_twis_0_irq_handler(); +} +#endif + +// Function prototypes +static int32_t I2C_PowerControl (ARM_POWER_STATE state, I2C_RESOURCES *i2c); + +// Local functions +static void twis_event_handler (nrfx_twis_evt_t const * p_event, I2C_RESOURCES *i2c) { + uint32_t event = 0U; + + switch (p_event->type) { + case NRFX_TWIS_EVT_READ_REQ: + if (nrfx_twis_is_waiting_tx_buff(&i2c->nrfx_twis)) { + event |= ARM_I2C_EVENT_SLAVE_TRANSMIT; + } + break; + case NRFX_TWIS_EVT_WRITE_REQ: + if (nrfx_twis_is_waiting_rx_buff(&i2c->nrfx_twis)) { + event |= ARM_I2C_EVENT_SLAVE_RECEIVE; + } + break; + case NRFX_TWIS_EVT_READ_DONE: + if (i2c->info->tx_num < nrfx_twis_tx_amount(&i2c->nrfx_twis)) { + event |= ARM_I2C_EVENT_TRANSFER_INCOMPLETE; + } + event |= ARM_I2C_EVENT_TRANSFER_DONE; + break; + case NRFX_TWIS_EVT_WRITE_DONE: + if (i2c->info->rx_num < nrfx_twis_rx_amount(&i2c->nrfx_twis)) { + event |= ARM_I2C_EVENT_TRANSFER_INCOMPLETE; + } + event |= ARM_I2C_EVENT_TRANSFER_DONE; + break; + + case NRFX_TWIS_EVT_READ_ERROR: + case NRFX_TWIS_EVT_WRITE_ERROR: + case NRFX_TWIS_EVT_GENERAL_ERROR: + i2c->info->err = 1U; + nrfx_twis_error_get_and_clear (&i2c->nrfx_twis); + event |= ARM_I2C_EVENT_BUS_ERROR; + break; + default: + break; + } + + if (i2c->info->cb_event != NULL) { + i2c->info->cb_event (event); + } +} + +/** + \fn ARM_DRV_VERSION I2C_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRV_VERSION +*/ +static ARM_DRIVER_VERSION I2CX_GetVersion (void) { + return DriverVersion; +} + + +/** + \fn ARM_I2C_CAPABILITIES I2C_GetCapabilities (void) + \brief Get driver capabilities. + \return \ref ARM_I2C_CAPABILITIES +*/ +static ARM_I2C_CAPABILITIES I2CX_GetCapabilities (void) { + return DriverCapabilities; +} + + +/** + \fn int32_t I2C_Initialize (ARM_I2C_SignalEvent_t cb_event, I2C_RESOURCES *i2c) + \brief Initialize I2C Interface. + \param[in] cb_event Pointer to \ref ARM_I2C_SignalEvent + \param[in] i2c Pointer to I2C resources + \return \ref ARM_I2C_STATUS +*/ +static int32_t I2C_Initialize (ARM_I2C_SignalEvent_t cb_event, I2C_RESOURCES *i2c) { + nrfx_err_t err; + int32_t ret = ARM_DRIVER_ERROR; + + memset (i2c->info, 0, sizeof(I2C_INFO)); + i2c->info->cb_event = cb_event; + + if ((i2c->info->state & I2C_INITIALIZED) != 0U) { + // If Driver is already initialized + return ARM_DRIVER_OK; + } + + // TWIS Configuration + i2c->info->config.addr[0] = NRFX_TWIS_DEFAULT_CONFIG_ADDR0; + i2c->info->config.addr[1] = NRFX_TWIS_DEFAULT_CONFIG_ADDR1; + i2c->info->config.scl = RTE_TWIS0_SCL_PIN_NUM; + i2c->info->config.scl_pull = NRF_GPIO_PIN_NOPULL; + i2c->info->config.sda = RTE_TWIS0_SDA_PIN_NUM; + i2c->info->config.sda_pull = NRF_GPIO_PIN_NOPULL; + i2c->info->config.interrupt_priority = NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY; + + err = nrfx_twis_init (&i2c->nrfx_twis, + &i2c->info->config, + i2c->twis_event_handler); + + if (err == NRFX_SUCCESS) { + i2c->info->state = I2C_INITIALIZED; + ret = ARM_DRIVER_OK; + } + + return ret; +} + + +/** + \fn int32_t I2C_Uninitialize (I2C_RESOURCES *i2c) + \brief De-initialize I2C Interface. + \param[in] i2c Pointer to I2C resources + \return \ref execution_status +*/ +static int32_t I2C_Uninitialize (I2C_RESOURCES *i2c) { + + if ((i2c->info->state & I2C_POWERED) != 0U) { + // If peripheral is powered, power-off the peripheral + (void)I2C_PowerControl(ARM_POWER_OFF, i2c); + } + + nrfx_twis_uninit (&i2c->nrfx_twis); + + return ARM_DRIVER_OK; +} + + +/** + \fn int32_t ARM_I2C_PowerControl (ARM_POWER_STATE state, I2C_RESOURCES *i2c) + \brief Control I2C Interface Power. + \param[in] state Power state + \param[in] i2c Pointer to I2C resources + \return \ref execution_status +*/ +static int32_t I2C_PowerControl (ARM_POWER_STATE state, I2C_RESOURCES *i2c) { + + if ((i2c->info->state & I2C_INITIALIZED) == 0U) { + return ARM_DRIVER_ERROR; + } + + if ((state != ARM_POWER_OFF) && + (state != ARM_POWER_FULL) && + (state != ARM_POWER_LOW)) { + return ARM_DRIVER_ERROR_PARAMETER; + } + switch (state) { + case ARM_POWER_OFF: + nrfx_twis_disable (&i2c->nrfx_twis); + i2c->info->state &= ~I2C_POWERED; + break; + + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + + case ARM_POWER_FULL: + if ((i2c->info->state & I2C_POWERED) != 0U) { + return ARM_DRIVER_OK; + } + nrfx_twis_enable (&i2c->nrfx_twis); + i2c->info->state |= I2C_POWERED; + + break; + } + + return ARM_DRIVER_OK; +} + + +/** + \fn int32_t I2C_MasterTransmit (uint32_t addr, + const uint8_t *data, + uint32_t num, + bool xfer_pending, + I2C_RESOURCES *i2c) + \brief Start transmitting data as I2C Master. + \param[in] addr Slave address (7-bit or 10-bit) + \param[in] data Pointer to buffer with data to send to I2C Slave + \param[in] num Number of data bytes to send + \param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated + \param[in] i2c Pointer to I2C resources + \return \ref execution_status +*/ +static int32_t I2C_MasterTransmit (uint32_t addr, + const uint8_t *data, + uint32_t num, + bool xfer_pending, + I2C_RESOURCES *i2c) { + + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + + +/** + \fn int32_t I2C_MasterReceive (uint32_t addr, + uint8_t *data, + uint32_t num, + bool xfer_pending, + I2C_RESOURCES *i2c) + \brief Start receiving data as I2C Master. + \param[in] addr Slave address (7-bit or 10-bit) + \param[out] data Pointer to buffer for data to receive from I2C Slave + \param[in] num Number of data bytes to receive + \param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated + \param[in] i2c Pointer to I2C resources + \return \ref execution_status +*/ +static int32_t I2C_MasterReceive (uint32_t addr, + uint8_t *data, + uint32_t num, + bool xfer_pending, + I2C_RESOURCES *i2c) { + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + + +/** + \fn int32_t I2C_SlaveTransmit (const uint8_t *data, uint32_t num, I2C_RESOURCES *i2c) + \brief Start transmitting data as I2C Slave. + \param[in] data Pointer to buffer with data to send to I2C Master + \param[in] num Number of data bytes to send + \param[in] i2c Pointer to I2C resources + \return \ref execution_status +*/ +static int32_t I2C_SlaveTransmit (const uint8_t *data, uint32_t num, I2C_RESOURCES *i2c) { + nrfx_err_t err; + int32_t ret = ARM_DRIVER_ERROR; + + if ((data == NULL) || (num == 0U)) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + i2c->info->err = 0U; + err = nrfx_twis_tx_prepare (&i2c->nrfx_twis, data, num); + if (err == NRFX_SUCCESS) { + i2c->info->dir = I2C_DIR_TX; + i2c->info->tx_num = num; + ret = ARM_DRIVER_OK; + } + + return ret; +} + + +/** + \fn int32_t I2C_SlaveReceive (uint8_t *data, uint32_t num, I2C_RESOURCES *i2c) + \brief Start receiving data as I2C Slave. + \param[out] data Pointer to buffer for data to receive from I2C Master + \param[in] num Number of data bytes to receive + \param[in] i2c Pointer to I2C resources + \return \ref execution_status +*/ +static int32_t I2C_SlaveReceive (uint8_t *data, uint32_t num, I2C_RESOURCES *i2c) { + nrfx_err_t err; + int32_t ret = ARM_DRIVER_ERROR; + + if ((data == NULL) || (num == 0U)) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + i2c->info->err = 0U; + err = nrfx_twis_rx_prepare (&i2c->nrfx_twis, data, num); + if (err == NRFX_SUCCESS) { + i2c->info->dir = I2C_DIR_RX; + i2c->info->rx_num = num; + ret = ARM_DRIVER_OK; + } + + return ret; +} + + +/** + \fn int32_t I2C_GetDataCount (void) + \brief Get transferred data count. + \return number of data bytes transferred; -1 when Slave is not addressed by Master +*/ +static int32_t I2C_GetDataCount (I2C_RESOURCES *i2c) { + int32_t val = 0U; + + if (i2c->info->dir == I2C_DIR_TX) { + val = nrfx_twis_tx_amount(&i2c->nrfx_twis); + } else { + val = nrfx_twis_rx_amount(&i2c->nrfx_twis); + } + return (val); +} + + +/** + \fn int32_t I2C_Control (uint32_t control, uint32_t arg, I2C_RESOURCES *i2c) + \brief Control I2C Interface. + \param[in] control operation + \param[in] arg argument of operation (optional) + \param[in] i2c pointer to I2C resources + \return \ref execution_status +*/ +static int32_t I2C_Control (uint32_t control, uint32_t arg, I2C_RESOURCES *i2c) { + nrfx_err_t err; + int32_t ret = ARM_DRIVER_ERROR; + + if ((i2c->info->state & I2C_POWERED) == 0U) { + /* I2C not powered */ + return ARM_DRIVER_ERROR; + } + + switch (control) { + case ARM_I2C_OWN_ADDRESS: + nrfx_twis_disable (&i2c->nrfx_twis); + nrfx_twis_uninit (&i2c->nrfx_twis); + + i2c->info->config.addr[0] = arg; + i2c->info->config.addr[1] = 0U; + + err = nrfx_twis_init (&i2c->nrfx_twis, + &i2c->info->config, + i2c->twis_event_handler); + + if (err == NRFX_SUCCESS) { + i2c->info->state = I2C_INITIALIZED; + nrfx_twis_enable (&i2c->nrfx_twis); + ret = ARM_DRIVER_OK; + } + break; + + case ARM_I2C_BUS_SPEED: + break; + + case ARM_I2C_ABORT_TRANSFER: + break; + + default: return ARM_DRIVER_ERROR; + } + return ARM_DRIVER_OK; +} + + +/** + \fn ARM_I2C_STATUS I2C_GetStatus (I2C_RESOURCES *i2c) + \brief Get I2C status. + \param[in] i2c pointer to I2C resources + \return I2C status \ref ARM_I2C_STATUS +*/ +static ARM_I2C_STATUS I2C_GetStatus (I2C_RESOURCES *i2c) { + ARM_I2C_STATUS status; + + memset(&status, 0U, sizeof(ARM_I2C_STATUS)); + if (nrfx_twis_is_busy(&i2c->nrfx_twis)) { + status.busy = 1U; + } + status.direction = i2c->info->dir; + status.bus_error = i2c->info->err; + + return (status); +} + +#if defined(RTE_TWIS0) +/* I2C1 Driver wrapper functions */ +static int32_t I2C0_Initialize (ARM_I2C_SignalEvent_t cb_event) { + return I2C_Initialize(cb_event, &I2C0_Resources); +} +static int32_t I2C0_Uninitialize (void) { + return I2C_Uninitialize(&I2C0_Resources); +} +static int32_t I2C0_PowerControl (ARM_POWER_STATE state) { + return I2C_PowerControl(state, &I2C0_Resources); +} +static int32_t I2C0_MasterTransmit (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) { + return I2C_MasterTransmit(addr, data, num, xfer_pending, &I2C0_Resources); +} +static int32_t I2C0_MasterReceive (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) { + return I2C_MasterReceive(addr, data, num, xfer_pending, &I2C0_Resources); +} +static int32_t I2C0_SlaveTransmit (const uint8_t *data, uint32_t num) { + return I2C_SlaveTransmit(data, num, &I2C0_Resources); +} +static int32_t I2C0_SlaveReceive (uint8_t *data, uint32_t num) { + return I2C_SlaveReceive(data, num, &I2C0_Resources); +} +static int32_t I2C0_GetDataCount (void) { + return I2C_GetDataCount(&I2C0_Resources); +} +static int32_t I2C0_Control (uint32_t control, uint32_t arg) { + return I2C_Control(control, arg, &I2C0_Resources); +} +static ARM_I2C_STATUS I2C0_GetStatus (void) { + return I2C_GetStatus(&I2C0_Resources); +} +static void TWIS0_event_handler (nrfx_twis_evt_t const * p_event) { + return twis_event_handler (p_event, &I2C0_Resources); +} + +/* I2C0 Driver Control Block */ +ARM_DRIVER_I2C Driver_I2C0 = { + I2CX_GetVersion, + I2CX_GetCapabilities, + I2C0_Initialize, + I2C0_Uninitialize, + I2C0_PowerControl, + I2C0_MasterTransmit, + I2C0_MasterReceive, + I2C0_SlaveTransmit, + I2C0_SlaveReceive, + I2C0_GetDataCount, + I2C0_Control, + I2C0_GetStatus +}; +#endif diff --git a/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.h b/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.h new file mode 100644 index 000000000..6c875e425 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.h @@ -0,0 +1,68 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2021 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 23. July 2021 + * $Revision: V1.0 + * + * Project: I2C Slave Driver Definitions for Nordic Semiconductor nRF52820 + * -------------------------------------------------------------------------- */ + +#ifndef __I2C_SLAVE_nRF52820_H +#define __I2C_SLAVE_nRF52820_H + +#include +#include +#include + +#include "Driver_I2C.h" + +//#include "config.h" +#include "nrfx_twis.h" +//#include "nrfx_gpio.h" + +#include "RTE_Device.h" + +// I2C Driver states +#define I2C_INITIALIZED (1U) +#define I2C_POWERED (1U << 1) + +// I2C Direction +#define I2C_DIR_TX (0U) +#define I2C_DIR_RX (1U) + +/* I2C Information (Run-Time) */ +typedef struct { + ARM_I2C_SignalEvent_t cb_event; // Event Callback + nrfx_twis_config_t config; + uint32_t state; + uint32_t tx_num; + uint32_t rx_num; + uint8_t dir; + uint8_t err; +} I2C_INFO; + +/* I2C Resources definition */ +typedef struct { + nrfx_twis_t nrfx_twis; + nrfx_twis_event_handler_t twis_event_handler; + I2C_INFO *info; // Run-Time information +} const I2C_RESOURCES; + + +#endif /* __I2C_SLAVE_nRF52820_H */ diff --git a/source/hic_hal/nordic/nrf52820/IO_Config.h b/source/hic_hal/nordic/nrf52820/IO_Config.h index 6a1ba54fe..817b3bc40 100644 --- a/source/hic_hal/nordic/nrf52820/IO_Config.h +++ b/source/hic_hal/nordic/nrf52820/IO_Config.h @@ -47,6 +47,8 @@ extern uint32_t uart_rx_pin; extern uint32_t sw_reset_pin; extern uint32_t led_usb_pin; extern uint32_t led_pwr_pin; +extern uint32_t i2c_scl_pin; +extern uint32_t i2c_sda_pin; // SWDCLK (Output) #define PIN_SWCLK NRF_GPIO_PIN_MAP(0, 1) @@ -83,16 +85,24 @@ extern uint32_t led_pwr_pin; #define UART_TX_PIN uart_tx_pin #define UART_RX_PIN uart_rx_pin +// I2C +#define I2C_SCL_PIN i2c_scl_pin +#define I2C_SDA_PIN i2c_sda_pin + #define NRF52820_RESET_PIN NRF_GPIO_PIN_MAP(0, 6) #define NRF52820_USB_LED_PIN NRF_GPIO_PIN_MAP(0, 14) #define NRF52820_PWR_LED_PIN NRF_GPIO_PIN_MAP(0, 15) #define NRF52820_UART_TX_PIN NRF_GPIO_PIN_MAP(0, 29) // From IMCU to target #define NRF52820_UART_RX_PIN NRF_GPIO_PIN_MAP(0, 8) // From target to IMCU +#define NRF52820_I2C_SCL_PIN NRF_GPIO_PIN_MAP(0, 28) +#define NRF52820_I2C_SDA_PIN NRF_GPIO_PIN_MAP(0, 30) #define NRF52833_RESET_PIN NRF_GPIO_PIN_MAP(1, 9) #define NRF52833_USB_LED_PIN NRF_GPIO_PIN_MAP(0, 15) #define NRF52833_PWR_LED_PIN NRF_GPIO_PIN_MAP(0, 17) #define NRF52833_UART_TX_PIN NRF_GPIO_PIN_MAP(0, 2) // From IMCU to target #define NRF52833_UART_RX_PIN NRF_GPIO_PIN_MAP(0, 3) // From target to IMCU +#define NRF52833_I2C_SCL_PIN NRF_GPIO_PIN_MAP(0, 29) +#define NRF52833_I2C_SDA_PIN NRF_GPIO_PIN_MAP(0, 28) #endif diff --git a/source/hic_hal/nordic/nrf52820/RTE_Device.h b/source/hic_hal/nordic/nrf52820/RTE_Device.h index 04c1ea598..96198ad61 100644 --- a/source/hic_hal/nordic/nrf52820/RTE_Device.h +++ b/source/hic_hal/nordic/nrf52820/RTE_Device.h @@ -54,5 +54,16 @@ #define RTE_USART0_RTS_PIN_NUM 0 /* N/A */ // +// TWIS0 ( I2C compatible two-wire interface) [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::CMSIS Driver:I2C +#define RTE_TWIS0 1 + +// SCL Pin number +#define RTE_TWIS0_SCL_PIN_NUM I2C_SCL_PIN + +// SDA Pin number +#define RTE_TWIS0_SDA_PIN_NUM I2C_SDA_PIN +// + #endif /* __RTE_DEVICE_H */ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_twis.c b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_twis.c new file mode 100644 index 000000000..932741183 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_twis.c @@ -0,0 +1,857 @@ +/** + * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include + +#if NRFX_CHECK(NRFX_TWIS_ENABLED) + +#if !(NRFX_CHECK(NRFX_TWIS0_ENABLED) || \ + NRFX_CHECK(NRFX_TWIS1_ENABLED) || \ + NRFX_CHECK(NRFX_TWIS2_ENABLED) || \ + NRFX_CHECK(NRFX_TWIS3_ENABLED)) +#error "No enabled TWIS instances. Check ." +#endif + +#include +#include "prs/nrfx_prs.h" + +#define NRFX_LOG_MODULE TWIS +#include + +#define EVT_TO_STR(event) \ + (event == NRF_TWIS_EVENT_STOPPED ? "NRF_TWIS_EVENT_STOPPED" : \ + (event == NRF_TWIS_EVENT_ERROR ? "NRF_TWIS_EVENT_ERROR" : \ + (event == NRF_TWIS_EVENT_RXSTARTED ? "NRF_TWIS_EVENT_RXSTARTED" : \ + (event == NRF_TWIS_EVENT_TXSTARTED ? "NRF_TWIS_EVENT_TXSTARTED" : \ + (event == NRF_TWIS_EVENT_WRITE ? "NRF_TWIS_EVENT_WRITE" : \ + (event == NRF_TWIS_EVENT_READ ? "NRF_TWIS_EVENT_READ" : \ + "UNKNOWN EVENT")))))) + + +/** + * @brief Actual state of internal state machine + * + * Current substate of powered on state. + */ +typedef enum +{ + NRFX_TWIS_SUBSTATE_IDLE, ///< No ongoing transmission + NRFX_TWIS_SUBSTATE_READ_WAITING, ///< Read request received, waiting for data + NRFX_TWIS_SUBSTATE_READ_PENDING, ///< Reading is actually pending (data sending) + NRFX_TWIS_SUBSTATE_WRITE_WAITING, ///< Write request received, waiting for data buffer + NRFX_TWIS_SUBSTATE_WRITE_PENDING, ///< Writing is actually pending (data receiving) +} nrfx_twis_substate_t; + +// Control block - driver instance local data. +typedef struct +{ + nrfx_twis_event_handler_t ev_handler; + // Internal copy of hardware errors flags merged with specific internal + // driver errors flags. + // This value can be changed in the interrupt and cleared in the main program. + // Always use Atomic load-store when updating this value in main loop. + volatile uint32_t error; + nrfx_drv_state_t state; + volatile nrfx_twis_substate_t substate; + + volatile bool semaphore; +} twis_control_block_t; +static twis_control_block_t m_cb[NRFX_TWIS_ENABLED_COUNT]; + +/** + * @brief Used interrupts mask + * + * Mask for all interrupts used by this library + */ +static const uint32_t m_used_ints_mask = NRF_TWIS_INT_STOPPED_MASK | + NRF_TWIS_INT_ERROR_MASK | + NRF_TWIS_INT_RXSTARTED_MASK | + NRF_TWIS_INT_TXSTARTED_MASK | + NRF_TWIS_INT_WRITE_MASK | + NRF_TWIS_INT_READ_MASK; + +/** + * @brief Clear all events + * + * Function clears all actually pending events + */ +static void nrfx_twis_clear_all_events(NRF_TWIS_Type * const p_reg) +{ + /* Clear all events */ + nrf_twis_event_clear(p_reg, NRF_TWIS_EVENT_STOPPED); + nrf_twis_event_clear(p_reg, NRF_TWIS_EVENT_ERROR); + nrf_twis_event_clear(p_reg, NRF_TWIS_EVENT_RXSTARTED); + nrf_twis_event_clear(p_reg, NRF_TWIS_EVENT_TXSTARTED); + nrf_twis_event_clear(p_reg, NRF_TWIS_EVENT_WRITE); + nrf_twis_event_clear(p_reg, NRF_TWIS_EVENT_READ); +} + +/** + * @brief Reset all the registers to known state + * + * This function clears all registers that requires it to known state. + * TWIS is left disabled after this function. + * All events are cleared. + * @param[out] p_reg TWIS to reset register address + */ +static inline void nrfx_twis_swreset(NRF_TWIS_Type * p_reg) +{ + /* Disable TWIS */ + nrf_twis_disable(p_reg); + + /* Disconnect pins */ + nrf_twis_pins_set(p_reg, ~0U, ~0U); + + /* Disable interrupt global for the instance */ + NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_reg)); + + /* Disable interrupts */ + nrf_twis_int_disable(p_reg, ~0U); +} + +/** + * @brief Configure pin + * + * Function configures selected for work as SDA or SCL. + * @param pin Pin number to configure + */ +static inline void nrfx_twis_config_pin(uint32_t pin, nrf_gpio_pin_pull_t pull) +{ + nrf_gpio_cfg(pin, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + pull, + NRF_GPIO_PIN_S0D1, + NRF_GPIO_PIN_NOSENSE); +} + +/** + * @brief Auxiliary function for getting event state on right bit possition + * + * This function calls @ref nrf_twis_event_get function but the the result + * is shifted to match INTEN register scheme. + * + * @param[in,out] p_reg TWIS to read event from + * @param ev Event code + * + * @return Selected event state shifted by @ref nrfx_event_to_bitpos + * + * @sa nrf_twis_event_get + * @sa nrfx_event_to_bitpos + */ +static inline uint32_t nrfx_twis_event_bit_get(NRF_TWIS_Type * p_reg, + nrf_twis_event_t ev) +{ + return (uint32_t)nrf_twis_event_get_and_clear(p_reg, ev) << nrfx_event_to_bitpos(ev); +} + +/** + * @brief Auxiliary function for checking event bit inside given flags value + * + * Function used here to check presence of the event inside given flags value. + * It transforms given event to bit possition and then checks if in given variable it is cleared. + * + * @param flags Flags to test + * @param ev Event code + * + * @retval true Flag for selected event is set + * @retval false Flag for selected event is cleared + */ +static inline bool nrfx_twis_check_bit(uint32_t flags, + nrf_twis_event_t ev) +{ + return 0 != (flags & (1U << nrfx_event_to_bitpos(ev))); +} + +/** + * @brief Auxiliary function for clearing event bit in given flags value + * + * Function used to clear selected event bit. + * + * @param flags Flags to process + * @param ev Event code to clear + * + * @return Value @em flags with cleared event bit that matches given @em ev + */ +static inline uint32_t nrfx_twis_clear_bit(uint32_t flags, + nrf_twis_event_t ev) +{ + return flags & ~(1U << nrfx_event_to_bitpos(ev)); +} + +static void call_event_handler(twis_control_block_t const * p_cb, + nrfx_twis_evt_t const * p_evt) +{ + nrfx_twis_event_handler_t handler = p_cb->ev_handler; + if (handler != NULL) + { + handler(p_evt); + } +} + +/** + * @brief Auxiliary function for error processing + * + * Function called when in current substate the event apears and it cannot be processed. + * It should be called also on ERROR event. + * If given @em error parameter has zero value the @ref NRFX_TWIS_ERROR_UNEXPECTED_EVENT + * would be set. + * + * @param p_cb Pointer to the driver instance control block. + * @param evt What error event raport to event handler + * @param error Error flags + */ +static inline void nrfx_twis_process_error(twis_control_block_t * p_cb, + nrfx_twis_evt_type_t evt, + uint32_t error) +{ + if (0 == error) + { + error = NRFX_TWIS_ERROR_UNEXPECTED_EVENT; + } + nrfx_twis_evt_t evdata; + evdata.type = evt; + evdata.data.error = error; + + p_cb->error |= error; + + call_event_handler(p_cb, &evdata); +} + +static void nrfx_twis_state_machine(NRF_TWIS_Type * p_reg, + twis_control_block_t * p_cb) +{ + if (!NRFX_TWIS_NO_SYNC_MODE) + { + /* Exclude parallel processing of this function */ + if (p_cb->semaphore) + { + return; + } + p_cb->semaphore = 1; + } + + /* Event data structure to be passed into event handler */ + nrfx_twis_evt_t evdata; + /* Current substate copy */ + nrfx_twis_substate_t substate = p_cb->substate; + /* Event flags */ + uint32_t ev = 0; + + /* Get all events */ + ev |= nrfx_twis_event_bit_get(p_reg, NRF_TWIS_EVENT_STOPPED); + ev |= nrfx_twis_event_bit_get(p_reg, NRF_TWIS_EVENT_ERROR); + ev |= nrfx_twis_event_bit_get(p_reg, NRF_TWIS_EVENT_RXSTARTED); + ev |= nrfx_twis_event_bit_get(p_reg, NRF_TWIS_EVENT_TXSTARTED); + ev |= nrfx_twis_event_bit_get(p_reg, NRF_TWIS_EVENT_WRITE); + ev |= nrfx_twis_event_bit_get(p_reg, NRF_TWIS_EVENT_READ); + + /* State machine */ + while (0 != ev) + { + switch (substate) + { + case NRFX_TWIS_SUBSTATE_IDLE: + if (nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_STOPPED)) + { + /* Stopped event is always allowed in IDLE state - just ignore */ + ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_STOPPED); + } + else if (nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_READ)) + { + evdata.type = NRFX_TWIS_EVT_READ_REQ; + if (nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_TXSTARTED)) + { + substate = NRFX_TWIS_SUBSTATE_READ_PENDING; + evdata.data.buf_req = false; + } + else + { + substate = NRFX_TWIS_SUBSTATE_READ_WAITING; + evdata.data.buf_req = true; + } + call_event_handler(p_cb, &evdata); + ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_READ); + ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_TXSTARTED); + ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_WRITE); + ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_RXSTARTED); + } + else if (nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_WRITE)) + { + evdata.type = NRFX_TWIS_EVT_WRITE_REQ; + if (nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_RXSTARTED)) + { + substate = NRFX_TWIS_SUBSTATE_WRITE_PENDING; + evdata.data.buf_req = false; + } + else + { + substate = NRFX_TWIS_SUBSTATE_WRITE_WAITING; + evdata.data.buf_req = true; + } + call_event_handler(p_cb, &evdata); + ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_READ); + ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_TXSTARTED); + ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_WRITE); + ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_RXSTARTED); + } + else + { + nrfx_twis_process_error(p_cb, + NRFX_TWIS_EVT_GENERAL_ERROR, + nrf_twis_error_source_get_and_clear(p_reg)); + ev = 0; + } + break; + case NRFX_TWIS_SUBSTATE_READ_WAITING: + if (nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_TXSTARTED) || + nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_WRITE) || + nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_READ) || + nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_STOPPED)) + { + substate = NRFX_TWIS_SUBSTATE_READ_PENDING; + /* Any other bits requires further processing in PENDING substate */ + ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_TXSTARTED); + } + else + { + nrfx_twis_process_error(p_cb, + NRFX_TWIS_EVT_READ_ERROR, + nrf_twis_error_source_get_and_clear(p_reg)); + substate = NRFX_TWIS_SUBSTATE_IDLE; + ev = 0; + } + break; + case NRFX_TWIS_SUBSTATE_READ_PENDING: + if (nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_WRITE) || + nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_READ) || + nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_STOPPED)) + { + evdata.type = NRFX_TWIS_EVT_READ_DONE; + evdata.data.tx_amount = nrf_twis_tx_amount_get(p_reg); + NRFX_LOG_INFO("Transfer tx_len:%d", evdata.data.tx_amount); + NRFX_LOG_DEBUG("Tx data:"); + NRFX_LOG_HEXDUMP_DEBUG((uint8_t const *)p_reg->TXD.PTR, + evdata.data.tx_amount * sizeof(uint8_t)); + call_event_handler(p_cb, &evdata); + /* Go to idle and repeat the state machine if READ or WRITE events detected. + * This time READ or WRITE would be started */ + substate = NRFX_TWIS_SUBSTATE_IDLE; + ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_STOPPED); + } + else + { + nrfx_twis_process_error(p_cb, + NRFX_TWIS_EVT_READ_ERROR, + nrf_twis_error_source_get_and_clear(p_reg)); + substate = NRFX_TWIS_SUBSTATE_IDLE; + ev = 0; + } + break; + case NRFX_TWIS_SUBSTATE_WRITE_WAITING: + if (nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_RXSTARTED) || + nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_WRITE) || + nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_READ) || + nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_STOPPED)) + { + substate = NRFX_TWIS_SUBSTATE_WRITE_PENDING; + /* Any other bits requires further processing in PENDING substate */ + ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_RXSTARTED); + } + else + { + nrfx_twis_process_error(p_cb, + NRFX_TWIS_EVT_WRITE_ERROR, + nrf_twis_error_source_get_and_clear(p_reg)); + substate = NRFX_TWIS_SUBSTATE_IDLE; + ev = 0; + } + break; + case NRFX_TWIS_SUBSTATE_WRITE_PENDING: + if (nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_WRITE) || + nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_READ) || + nrfx_twis_check_bit(ev, NRF_TWIS_EVENT_STOPPED)) + { + evdata.type = NRFX_TWIS_EVT_WRITE_DONE; + evdata.data.rx_amount = nrf_twis_rx_amount_get(p_reg); + call_event_handler(p_cb, &evdata); + /* Go to idle and repeat the state machine if READ or WRITE events detected. + * This time READ or WRITE would be started */ + substate = NRFX_TWIS_SUBSTATE_IDLE; + ev = nrfx_twis_clear_bit(ev, NRF_TWIS_EVENT_STOPPED); + } + else + { + nrfx_twis_process_error(p_cb, + NRFX_TWIS_EVT_WRITE_ERROR, + nrf_twis_error_source_get_and_clear(p_reg)); + substate = NRFX_TWIS_SUBSTATE_IDLE; + ev = 0; + } + break; + default: + substate = NRFX_TWIS_SUBSTATE_IDLE; + /* Do not clear any events and repeat the machine */ + break; + } + } + + p_cb->substate = substate; + if (!NRFX_TWIS_NO_SYNC_MODE) + { + p_cb->semaphore = 0; + } +} + + +static inline void nrfx_twis_preprocess_status(nrfx_twis_t const * p_instance) +{ + if (!NRFX_TWIS_NO_SYNC_MODE) + { + NRF_TWIS_Type * p_reg = p_instance->p_reg; + twis_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + if (NULL == p_cb->ev_handler) + { + nrfx_twis_state_machine(p_reg, p_cb); + } + } +} + + +/* ------------------------------------------------------------------------- + * Implementation of interface functions + * + */ + + +nrfx_err_t nrfx_twis_init(nrfx_twis_t const * p_instance, + nrfx_twis_config_t const * p_config, + nrfx_twis_event_handler_t event_handler) +{ + NRFX_ASSERT(p_config); + NRFX_ASSERT(p_config->scl != p_config->sda); + nrfx_err_t err_code; + + NRF_TWIS_Type * p_reg = p_instance->p_reg; + twis_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + + if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) + { + err_code = NRFX_ERROR_INVALID_STATE; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + +#if NRFX_CHECK(NRFX_PRS_ENABLED) + static nrfx_irq_handler_t const irq_handlers[NRFX_TWIS_ENABLED_COUNT] = { + #if NRFX_CHECK(NRFX_TWIS0_ENABLED) + nrfx_twis_0_irq_handler, + #endif + #if NRFX_CHECK(NRFX_TWIS1_ENABLED) + nrfx_twis_1_irq_handler, + #endif + #if NRFX_CHECK(NRFX_TWIS2_ENABLED) + nrfx_twis_2_irq_handler, + #endif + #if NRFX_CHECK(NRFX_TWIS3_ENABLED) + nrfx_twis_3_irq_handler, + #endif + }; + if (nrfx_prs_acquire(p_reg, + irq_handlers[p_instance->drv_inst_idx]) != NRFX_SUCCESS) + { + err_code = NRFX_ERROR_BUSY; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } +#endif // NRFX_CHECK(NRFX_PRS_ENABLED) + + if (!NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY) + { + nrfx_twis_swreset(p_reg); + } + + nrfx_twis_config_pin(p_config->scl, p_config->scl_pull); + nrfx_twis_config_pin(p_config->sda, p_config->sda_pull); + + nrf_twis_config_addr_mask_t addr_mask = (nrf_twis_config_addr_mask_t)0; + if (0 == (p_config->addr[0] | p_config->addr[1])) + { + addr_mask = NRF_TWIS_CONFIG_ADDRESS0_MASK; + } + else + { + if (0 != p_config->addr[0]) + { + addr_mask |= NRF_TWIS_CONFIG_ADDRESS0_MASK; + } + if (0 != p_config->addr[1]) + { + addr_mask |= NRF_TWIS_CONFIG_ADDRESS1_MASK; + } + } + + /* Peripheral interrupt configure + * (note - interrupts still needs to be configured in INTEN register. + * This is done in enable function) */ + NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_reg), + p_config->interrupt_priority); + NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_reg)); + + /* Configure */ + nrf_twis_pins_set (p_reg, p_config->scl, p_config->sda); + nrf_twis_address_set (p_reg, 0, p_config->addr[0]); + nrf_twis_address_set (p_reg, 1, p_config->addr[1]); + nrf_twis_config_address_set(p_reg, addr_mask); + + /* Clear semaphore */ + if (!NRFX_TWIS_NO_SYNC_MODE) + { + p_cb->semaphore = 0; + } + /* Set internal instance variables */ + p_cb->substate = NRFX_TWIS_SUBSTATE_IDLE; + p_cb->ev_handler = event_handler; + p_cb->state = NRFX_DRV_STATE_INITIALIZED; + err_code = NRFX_SUCCESS; + NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; +} + + +void nrfx_twis_uninit(nrfx_twis_t const * p_instance) +{ + NRF_TWIS_Type * p_reg = p_instance->p_reg; + twis_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); + + TWIS_PSEL_Type psel = p_reg->PSEL; + + nrfx_twis_swreset(p_reg); + + /* Clear pins state if */ + if (!(TWIS_PSEL_SCL_CONNECT_Msk & psel.SCL)) + { + nrf_gpio_cfg_default(psel.SCL); + } + if (!(TWIS_PSEL_SDA_CONNECT_Msk & psel.SDA)) + { + nrf_gpio_cfg_default(psel.SDA); + } + +#if NRFX_CHECK(NRFX_PRS_ENABLED) + nrfx_prs_release(p_reg); +#endif + + /* Clear variables */ + p_cb->ev_handler = NULL; + p_cb->state = NRFX_DRV_STATE_UNINITIALIZED; +} + + +void nrfx_twis_enable(nrfx_twis_t const * p_instance) +{ + NRF_TWIS_Type * p_reg = p_instance->p_reg; + twis_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + NRFX_ASSERT(p_cb->state == NRFX_DRV_STATE_INITIALIZED); + + nrfx_twis_clear_all_events(p_reg); + + /* Enable interrupts */ + if (NULL != p_cb->ev_handler) + { + nrf_twis_int_enable(p_reg, m_used_ints_mask); + } + + nrf_twis_enable(p_reg); + p_cb->error = 0; + p_cb->state = NRFX_DRV_STATE_POWERED_ON; + p_cb->substate = NRFX_TWIS_SUBSTATE_IDLE; +} + + +void nrfx_twis_disable(nrfx_twis_t const * p_instance) +{ + NRF_TWIS_Type * p_reg = p_instance->p_reg; + twis_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); + + nrf_twis_int_disable(p_reg, m_used_ints_mask); + + nrf_twis_disable(p_reg); + p_cb->state = NRFX_DRV_STATE_INITIALIZED; +} + +/* ARM recommends not using the LDREX and STREX instructions in C code. + * This is because the compiler might generate loads and stores between + * LDREX and STREX, potentially clearing the exclusive monitor set by LDREX. + * This recommendation also applies to the byte, halfword, and doubleword + * variants LDREXB, STREXB, LDREXH, STREXH, LDREXD, and STREXD. + * + * This is the reason for the function below to be implemented in assembly. + */ +//lint -save -e578 +#if defined (__CC_ARM ) +static __ASM uint32_t nrfx_twis_error_get_and_clear_internal(uint32_t volatile * perror) +{ + mov r3, r0 + mov r1, #0 +nrfx_twis_error_get_and_clear_internal_try + ldrex r0, [r3] + strex r2, r1, [r3] + cmp r2, r1 /* did this succeed? */ + bne nrfx_twis_error_get_and_clear_internal_try /* no - try again */ + bx lr +} +#elif defined ( __GNUC__ ) +static uint32_t nrfx_twis_error_get_and_clear_internal(uint32_t volatile * perror) +{ + uint32_t ret; + uint32_t temp; + __ASM volatile( + " .syntax unified \n" + "nrfx_twis_error_get_and_clear_internal_try: \n" + " ldrex %[ret], [%[perror]] \n" + " strex %[temp], %[zero], [%[perror]] \n" + " cmp %[temp], %[zero] \n" + " bne nrfx_twis_error_get_and_clear_internal_try \n" + : /* Output */ + [ret]"=&l"(ret), + [temp]"=&l"(temp) + : /* Input */ + [zero]"l"(0), + [perror]"l"(perror) + ); + (void)temp; + return ret; +} +#elif defined ( __ICCARM__ ) +static uint32_t nrfx_twis_error_get_and_clear_internal(uint32_t volatile * perror) +{ + uint32_t ret; + uint32_t temp; + __ASM volatile( + "1: \n" + " ldrex %[ret], [%[perror]] \n" + " strex %[temp], %[zero], [%[perror]] \n" + " cmp %[temp], %[zero] \n" + " bne.n 1b \n" + : /* Output */ + [ret]"=&l"(ret), + [temp]"=&l"(temp) + : /* Input */ + [zero]"l"(0), + [perror]"l"(perror) + ); + (void)temp; + return ret; +} +#else + #error Unknown compiler +#endif +//lint -restore + +uint32_t nrfx_twis_error_get_and_clear(nrfx_twis_t const * p_instance) +{ + nrfx_twis_preprocess_status(p_instance); + /* Make sure that access to error member is atomic + * so there is no bit that is cleared if it is not copied to local variable already. */ + twis_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + return nrfx_twis_error_get_and_clear_internal(&p_cb->error); +} + + +nrfx_err_t nrfx_twis_tx_prepare(nrfx_twis_t const * p_instance, + void const * p_buf, + size_t size) +{ + nrfx_err_t err_code; + twis_control_block_t const * p_cb = &m_cb[p_instance->drv_inst_idx]; + + /* Check power state*/ + if (p_cb->state != NRFX_DRV_STATE_POWERED_ON) + { + err_code = NRFX_ERROR_INVALID_STATE; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + /* Check data address */ + if (!nrfx_is_in_ram(p_buf)) + { + err_code = NRFX_ERROR_INVALID_ADDR; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + /* Check data size */ + if ((size & TWIS_TXD_MAXCNT_MAXCNT_Msk) != size) + { + err_code = NRFX_ERROR_INVALID_LENGTH; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + + nrf_twis_tx_prepare(p_instance->p_reg, + (uint8_t const *)p_buf, + size); + err_code = NRFX_SUCCESS; + NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; +} + + +nrfx_err_t nrfx_twis_rx_prepare(nrfx_twis_t const * p_instance, + void * p_buf, + size_t size) +{ + nrfx_err_t err_code; + twis_control_block_t const * p_cb = &m_cb[p_instance->drv_inst_idx]; + + /* Check power state*/ + if (p_cb->state != NRFX_DRV_STATE_POWERED_ON) + { + err_code = NRFX_ERROR_INVALID_STATE; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + /* Check data address */ + if (!nrfx_is_in_ram(p_buf)) + { + err_code = NRFX_ERROR_INVALID_ADDR; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + /* Check data size */ + if ((size & TWIS_RXD_MAXCNT_MAXCNT_Msk) != size) + { + err_code = NRFX_ERROR_INVALID_LENGTH; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + + nrf_twis_rx_prepare(p_instance->p_reg, + (uint8_t *)p_buf, + size); + err_code = NRFX_SUCCESS; + NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; +} + + +bool nrfx_twis_is_busy(nrfx_twis_t const * p_instance) +{ + nrfx_twis_preprocess_status(p_instance); + twis_control_block_t const * p_cb = &m_cb[p_instance->drv_inst_idx]; + return NRFX_TWIS_SUBSTATE_IDLE != p_cb->substate; +} + +bool nrfx_twis_is_waiting_tx_buff(nrfx_twis_t const * p_instance) +{ + nrfx_twis_preprocess_status(p_instance); + twis_control_block_t const * p_cb = &m_cb[p_instance->drv_inst_idx]; + return NRFX_TWIS_SUBSTATE_READ_WAITING == p_cb->substate; +} + +bool nrfx_twis_is_waiting_rx_buff(nrfx_twis_t const * p_instance) +{ + nrfx_twis_preprocess_status(p_instance); + twis_control_block_t const * p_cb = &m_cb[p_instance->drv_inst_idx]; + return NRFX_TWIS_SUBSTATE_WRITE_WAITING == p_cb->substate; +} + +bool nrfx_twis_is_pending_tx(nrfx_twis_t const * p_instance) +{ + nrfx_twis_preprocess_status(p_instance); + twis_control_block_t const * p_cb = &m_cb[p_instance->drv_inst_idx]; + return NRFX_TWIS_SUBSTATE_READ_PENDING == p_cb->substate; +} + +bool nrfx_twis_is_pending_rx(nrfx_twis_t const * p_instance) +{ + nrfx_twis_preprocess_status(p_instance); + twis_control_block_t const * p_cb = &m_cb[p_instance->drv_inst_idx]; + return NRFX_TWIS_SUBSTATE_WRITE_PENDING == p_cb->substate; +} + + +#if NRFX_CHECK(NRFX_TWIS0_ENABLED) +void nrfx_twis_0_irq_handler(void) +{ + nrfx_twis_state_machine(NRF_TWIS0, &m_cb[NRFX_TWIS0_INST_IDX]); +} +#endif + +#if NRFX_CHECK(NRFX_TWIS1_ENABLED) +void nrfx_twis_1_irq_handler(void) +{ + nrfx_twis_state_machine(NRF_TWIS1, &m_cb[NRFX_TWIS1_INST_IDX]); +} +#endif + +#if NRFX_CHECK(NRFX_TWIS2_ENABLED) +void nrfx_twis_2_irq_handler(void) +{ + nrfx_twis_state_machine(NRF_TWIS2, &m_cb[NRFX_TWIS2_INST_IDX]); +} +#endif + +#if NRFX_CHECK(NRFX_TWIS3_ENABLED) +void nrfx_twis_3_irq_handler(void) +{ + nrfx_twis_state_machine(NRF_TWIS3, &m_cb[NRFX_TWIS3_INST_IDX]); +} +#endif + +#endif // NRFX_CHECK(NRFX_TWIS_ENABLED) diff --git a/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_twis.h b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_twis.h new file mode 100644 index 000000000..0134b3a99 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_twis.h @@ -0,0 +1,403 @@ +/** + * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_TWIS_H__ +#define NRFX_TWIS_H__ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_twis TWIS driver + * @{ + * @ingroup nrf_twis + * @brief Two Wire Interface Slave with EasyDMA (TWIS) peripheral driver. + */ + +/** @brief TWIS driver instance data structure. */ +typedef struct +{ + NRF_TWIS_Type * p_reg; ///< Pointer to a structure with TWIS registers. + uint8_t drv_inst_idx; ///< Index of the driver instance. For internal use only. +} nrfx_twis_t; + +#ifndef __NRFX_DOXYGEN__ +enum { +#if NRFX_CHECK(NRFX_TWIS0_ENABLED) + NRFX_TWIS0_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_TWIS1_ENABLED) + NRFX_TWIS1_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_TWIS2_ENABLED) + NRFX_TWIS2_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_TWIS3_ENABLED) + NRFX_TWIS3_INST_IDX, +#endif + NRFX_TWIS_ENABLED_COUNT +}; +#endif + +/** @brief Macro for creating a TWIS driver instance. */ +#define NRFX_TWIS_INSTANCE(id) \ +{ \ + .p_reg = NRFX_CONCAT_2(NRF_TWIS, id), \ + .drv_inst_idx = NRFX_CONCAT_3(NRFX_TWIS, id, _INST_IDX), \ +} + +/** @brief Event callback function event definitions. */ +typedef enum +{ + NRFX_TWIS_EVT_READ_REQ, ///< Read request detected. + /**< If there is no buffer prepared, buf_req flag in the even will be set. + Call then @ref nrfx_twis_tx_prepare to give parameters for buffer. + */ + NRFX_TWIS_EVT_READ_DONE, ///< Read request finished - free any data. + NRFX_TWIS_EVT_READ_ERROR, ///< Read request finished with error. + NRFX_TWIS_EVT_WRITE_REQ, ///< Write request detected. + /**< If there is no buffer prepared, buf_req flag in the even will be set. + Call then @ref nrfx_twis_rx_prepare to give parameters for buffer. + */ + NRFX_TWIS_EVT_WRITE_DONE, ///< Write request finished - process data. + NRFX_TWIS_EVT_WRITE_ERROR, ///< Write request finished with error. + NRFX_TWIS_EVT_GENERAL_ERROR ///< Error that happens not inside WRITE or READ transaction. +} nrfx_twis_evt_type_t; + +/** + * @brief Possible error sources. + * + * This is flag enum - values from this enum can be connected using logical or operator. + * @note + * You can use directly @ref nrf_twis_error_t. Error type enum is redefined here because + * of possible future extension (eg. supporting timeouts and synchronous mode). + */ +typedef enum +{ + NRFX_TWIS_ERROR_OVERFLOW = NRF_TWIS_ERROR_OVERFLOW, /**< RX buffer overflow detected, and prevented. */ + NRFX_TWIS_ERROR_DATA_NACK = NRF_TWIS_ERROR_DATA_NACK, /**< NACK sent after receiving a data byte. */ + NRFX_TWIS_ERROR_OVERREAD = NRF_TWIS_ERROR_OVERREAD, /**< TX buffer over-read detected, and prevented. */ + NRFX_TWIS_ERROR_UNEXPECTED_EVENT = 1 << 8 /**< Unexpected event detected by state machine. */ +} nrfx_twis_error_t; + +/** @brief TWIS driver event structure. */ +typedef struct +{ + nrfx_twis_evt_type_t type; ///< Event type. + union + { + bool buf_req; ///< Flag for @ref NRFX_TWIS_EVT_READ_REQ and @ref NRFX_TWIS_EVT_WRITE_REQ. + /**< Information if transmission buffer requires to be prepared. */ + uint32_t tx_amount; ///< Data for @ref NRFX_TWIS_EVT_READ_DONE. + uint32_t rx_amount; ///< Data for @ref NRFX_TWIS_EVT_WRITE_DONE. + uint32_t error; ///< Data for @ref NRFX_TWIS_EVT_GENERAL_ERROR. + } data; ///< Union to store event data. +} nrfx_twis_evt_t; + +/** + * @brief TWI slave event callback function type. + * + * @param[in] p_event Event information structure. + */ +typedef void (*nrfx_twis_event_handler_t)(nrfx_twis_evt_t const * p_event); + +/** @brief Structure for TWIS configuration. */ +typedef struct +{ + uint32_t addr[2]; //!< Set addresses that this slave should respond. Set 0 to disable. + uint32_t scl; //!< SCL pin number. + uint32_t sda; //!< SDA pin number. + nrf_gpio_pin_pull_t scl_pull; //!< SCL pin pull. + nrf_gpio_pin_pull_t sda_pull; //!< SDA pin pull. + uint8_t interrupt_priority; //!< The priority of interrupt for the module to be set. +} nrfx_twis_config_t; + +/** @brief Generate the default configuration for the TWIS driver instance. */ +#define NRFX_TWIS_DEFAULT_CONFIG \ +{ \ + .addr = { NRFX_TWIS_DEFAULT_CONFIG_ADDR0, \ + NRFX_TWIS_DEFAULT_CONFIG_ADDR1 }, \ + .scl = 31, \ + .sda = 31, \ + .scl_pull = (nrf_gpio_pin_pull_t)NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL, \ + .sda_pull = (nrf_gpio_pin_pull_t)NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL, \ + .interrupt_priority = NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY \ +} + +/** + * @brief Function for initializing the TWIS driver instance. + * + * Function initializes and enables the TWIS driver. + * @attention After driver initialization enable it with @ref nrfx_twis_enable. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @attention @em p_instance has to be global object. + * It will be used by interrupts so make it sure that object + * is not destroyed when function is leaving. + * @param[in] p_config Pointer to the structure with the initial configuration. + * @param[in] event_handler Event handler provided by the user. + * + * @retval NRFX_SUCCESS Initialization is successful. + * @retval NRFX_ERROR_INVALID_STATE The driver is already initialized. + * @retval NRFX_ERROR_BUSY Some other peripheral with the same + * instance ID is already in use. This is + * possible only if NRFX_PRS_ENABLED + * is set to a value other than zero. + */ +nrfx_err_t nrfx_twis_init(nrfx_twis_t const * p_instance, + nrfx_twis_config_t const * p_config, + nrfx_twis_event_handler_t event_handler); + +/** + * @brief Function for uninitializing the TWIS driver instance. + * + * Function uninitializes the peripheral and resets all registers to default values. + * + * @note + * It is safe to call nrfx_twis_uninit even before initialization. + * Actually, @ref nrfx_twis_init function calls this function to + * make sure that TWIS state is known. + * @note + * If TWIS driver was in uninitialized state before calling this function, + * the selected pins would not be reset to default configuration. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_twis_uninit(nrfx_twis_t const * p_instance); + +/** + * @brief Function for enabling the TWIS instance. + * + * This function enables the TWIS instance. + * Function defined if there is need for dynamically enabling and disabling the peripheral. + * Use @ref nrfx_twis_enable and @ref nrfx_twis_disable functions. + * They do not change any configuration registers. + * + * @param p_instance Pointer to the driver instance structure. + */ +void nrfx_twis_enable(nrfx_twis_t const * p_instance); + +/** + * @brief Function for disabling the TWIS instance. + * + * This function disables the TWIS instance, which gives possibility to turn off the TWIS while + * holding configuration done by @ref nrfx_twis_init. + * + * @param p_instance Pointer to the driver instance structure. + */ +void nrfx_twis_disable(nrfx_twis_t const * p_instance); + +/** + * @brief Function for getting and clearing the last error flags. + * + * This function gets the information about errors. + * This is also the only possibility to exit from the error substate of the internal state machine. + * @attention + * This function clears error state and flags. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @return Error flags defined in @ref nrfx_twis_error_t. + */ +uint32_t nrfx_twis_error_get_and_clear(nrfx_twis_t const * p_instance); + +/** + * @brief Function for preparing the data for sending. + * + * This function is to be used in response to the @ref NRFX_TWIS_EVT_READ_REQ event. + * + * @note Peripherals using EasyDMA (including TWIS) require the transfer buffers + * to be placed in the Data RAM region. If this condition is not met, + * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. + * @attention Transmission buffer must be placed in RAM. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_buf Transmission buffer. + * @param[in] size Maximum number of bytes that master may read from buffer given. + * + * @retval NRFX_SUCCESS The preparation finished properly. + * @retval NRFX_ERROR_INVALID_ADDR The given @em p_buf is not placed inside the RAM. + * @retval NRFX_ERROR_INVALID_LENGTH There is a wrong value in the @em size parameter. + * @retval NRFX_ERROR_INVALID_STATE The module is not initialized or not enabled. + */ +nrfx_err_t nrfx_twis_tx_prepare(nrfx_twis_t const * p_instance, + void const * p_buf, + size_t size); + +/** + * @brief Function for getting the number of transmitted bytes. + * + * This function returns the number of bytes sent. + * This function can be called after @ref NRFX_TWIS_EVT_READ_DONE or @ref NRFX_TWIS_EVT_READ_ERROR events. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @return Number of bytes sent. + */ +__STATIC_INLINE size_t nrfx_twis_tx_amount(nrfx_twis_t const * p_instance); + +/** + * @brief Function for preparing the data for receiving. + * + * This function must be used in response to the @ref NRFX_TWIS_EVT_WRITE_REQ event. + * + * @note Peripherals using EasyDMA (including TWIS) require the transfer buffers + * to be placed in the Data RAM region. If this condition is not met, + * this function fails with the error code NRFX_ERROR_INVALID_ADDR. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_buf Buffer that is to be filled with received data. + * @param[in] size Size of the buffer (maximum amount of data to receive). + * + * @retval NRFX_SUCCESS The preparation finished properly. + * @retval NRFX_ERROR_INVALID_ADDR The given @em p_buf is not placed inside the RAM. + * @retval NRFX_ERROR_INVALID_LENGTH There is a wrong value in the @em size parameter. + * @retval NRFX_ERROR_INVALID_STATE The module is not initialized or not enabled. + */ +nrfx_err_t nrfx_twis_rx_prepare(nrfx_twis_t const * p_instance, + void * p_buf, + size_t size); + +/** + * @brief Function for getting the number of received bytes. + * + * This function returns number of bytes received. + * It can be called after @ref NRFX_TWIS_EVT_WRITE_DONE or @ref NRFX_TWIS_EVT_WRITE_ERROR events. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @return Number of bytes received. + */ +__STATIC_INLINE size_t nrfx_twis_rx_amount(nrfx_twis_t const * p_instance); + +/** + * @brief Function for checking if the driver is busy right now. + * + * This function tests the actual driver substate. + * If the driver is in any other state than IDLE or ERROR, this function returns true. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval true The driver is in state other than ERROR or IDLE. + * @retval false There is no transmission pending. + */ +bool nrfx_twis_is_busy(nrfx_twis_t const * p_instance); + +/** + * @brief Function for checking if the driver is waiting for a TX buffer. + * + * If this function returns true, the driver is stalled expecting + * of the @ref nrfx_twis_tx_prepare function call. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval true The driver is waiting for @ref nrfx_twis_tx_prepare. + * @retval false The driver is not in the state where it is waiting for preparing a TX buffer. + */ +bool nrfx_twis_is_waiting_tx_buff(nrfx_twis_t const * p_instance); + +/** + * @brief Function for checking if the driver is waiting for an RX buffer. + * + * If this function returns true, the driver is stalled expecting + * of the @ref nrfx_twis_rx_prepare function call. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval true The driver is waiting for @ref nrfx_twis_rx_prepare. + * @retval false The driver is not in the state where it is waiting for preparing an RX buffer. + */ +bool nrfx_twis_is_waiting_rx_buff(nrfx_twis_t const * p_instance); + +/** + * @brief Function for checking if the driver is sending data. + * + * If this function returns true, there is an ongoing output transmission. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval true There is an ongoing output transmission. + * @retval false The driver is in other state. + */ +bool nrfx_twis_is_pending_tx(nrfx_twis_t const * p_instance); + +/** + * @brief Function for checking if the driver is receiving data. + * + * If this function returns true, there is an ongoing input transmission. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval true There is an ongoing input transmission. + * @retval false The driver is in other state. + */ +bool nrfx_twis_is_pending_rx(nrfx_twis_t const * p_instance); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE size_t nrfx_twis_tx_amount(nrfx_twis_t const * p_instance) +{ + return nrf_twis_tx_amount_get(p_instance->p_reg); +} + +__STATIC_INLINE size_t nrfx_twis_rx_amount(nrfx_twis_t const * p_instance) +{ + return nrf_twis_rx_amount_get(p_instance->p_reg); +} +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + + +void nrfx_twis_0_irq_handler(void); +void nrfx_twis_1_irq_handler(void); +void nrfx_twis_2_irq_handler(void); +void nrfx_twis_3_irq_handler(void); + + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_TWIS_H__ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/drivers/prs/nrfx_prs.h b/source/hic_hal/nordic/nrf52820/nrfx/drivers/prs/nrfx_prs.h new file mode 100644 index 000000000..7759c7e0a --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx/drivers/prs/nrfx_prs.h @@ -0,0 +1,155 @@ +/** + * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_PRS_H__ +#define NRFX_PRS_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_prs Peripheral Resource Sharing (PRS) + * @{ + * @ingroup nrfx + * + * @brief Peripheral Resource Sharing interface (PRS). + */ + +#if defined(NRF51) + // SPI0, TWI0 + #define NRFX_PRS_BOX_0_ADDR NRF_SPI0 + // SPI1, SPIS1, TWI1 + #define NRFX_PRS_BOX_1_ADDR NRF_SPI1 +#elif defined(NRF52810_XXAA) + // TWIM0, TWIS0, TWI0 + #define NRFX_PRS_BOX_0_ADDR NRF_TWIM0 + // SPIM0, SPIS0, SPI0 + #define NRFX_PRS_BOX_1_ADDR NRF_SPIM0 + // UARTE0, UART0 + #define NRFX_PRS_BOX_2_ADDR NRF_UARTE0 +#elif defined(NRF52811_XXAA) + // TWIM0, TWIS0, TWI0, SPIM1, SPIS1, SPI1 + #define NRFX_PRS_BOX_0_ADDR NRF_TWIM0 + // SPIM0, SPIS0, SPI0 + #define NRFX_PRS_BOX_1_ADDR NRF_SPIM0 + // UART0, UARTE0 + #define NRFX_PRS_BOX_2_ADDR NRF_UART0 +#elif defined(NRF52820_XXAA) + // SPIM0, SPIS0, TWIM0, TWIS0, SPI0, TWI0 + #define NRFX_PRS_BOX_0_ADDR NRF_SPIM0 + // SPIM1, SPIS1, TWIM1, TWIS1, SPI1, TWI1 + #define NRFX_PRS_BOX_1_ADDR NRF_SPIM1 + // UARTE0, UART0 + #define NRFX_PRS_BOX_2_ADDR NRF_UARTE0 +#elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \ + defined(NRF52833_XXAA) || defined(NRF52840_XXAA) + // SPIM0, SPIS0, TWIM0, TWIS0, SPI0, TWI0 + #define NRFX_PRS_BOX_0_ADDR NRF_SPIM0 + // SPIM1, SPIS1, TWIM1, TWIS1, SPI1, TWI1 + #define NRFX_PRS_BOX_1_ADDR NRF_SPIM1 + // SPIM2, SPIS2, SPI2 + #define NRFX_PRS_BOX_2_ADDR NRF_SPIM2 + // COMP, LPCOMP + #define NRFX_PRS_BOX_3_ADDR NRF_COMP + // UARTE0, UART0 + #define NRFX_PRS_BOX_4_ADDR NRF_UARTE0 +#elif defined(NRF9160_XXAA) + // UARTE0, SPIM0, SPIS0, TWIM0, TWIS0 + #define NRFX_PRS_BOX_0_ADDR NRF_UARTE0 + // UARTE1, SPIM1, SPIS1, TWIM1, TWIS1 + #define NRFX_PRS_BOX_1_ADDR NRF_UARTE1 + // UARTE2, SPIM2, SPIS2, TWIM2, TWIS2 + #define NRFX_PRS_BOX_2_ADDR NRF_UARTE2 + // UARTE3, SPIM3, SPIS3, TWIM3, TWIS3 + #define NRFX_PRS_BOX_3_ADDR NRF_UARTE3 +#else + #error "Unknown device." +#endif + +/** + * @brief Function for acquiring shared peripheral resources associated with + * the specified peripheral. + * + * Certain resources and registers are shared among peripherals that have + * the same ID (for example: SPI0, SPIM0, SPIS0, TWI0, TWIM0, and TWIS0 in + * nRF52832). Only one of them can be utilized at a given time. This function + * reserves proper resources to be used by the specified peripheral. + * If NRFX_PRS_ENABLED is set to a non-zero value, IRQ handlers for peripherals + * that are sharing resources with others are implemented by the @ref nrfx_prs + * module instead of individual drivers. The drivers must then specify their + * interrupt handling routines and register them by using this function. + * + * @param[in] p_base_addr Requested peripheral base pointer. + * @param[in] irq_handler Interrupt handler to register. + * + * @retval NRFX_SUCCESS If resources were acquired successfully or the + * specified peripheral is not handled by the PRS + * subsystem and there is no need to acquire resources + * for it. + * @retval NRFX_ERROR_BUSY If resources were already acquired. + */ +nrfx_err_t nrfx_prs_acquire(void const * p_base_addr, + nrfx_irq_handler_t irq_handler); + +/** + * @brief Function for releasing shared resources reserved previously by + * @ref nrfx_prs_acquire() for the specified peripheral. + * + * @param[in] p_base_addr Released peripheral base pointer. + */ +void nrfx_prs_release(void const * p_base_addr); + +/** @} */ + +void nrfx_prs_box_0_irq_handler(void); +void nrfx_prs_box_1_irq_handler(void); +void nrfx_prs_box_2_irq_handler(void); +void nrfx_prs_box_3_irq_handler(void); +void nrfx_prs_box_4_irq_handler(void); + + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_PRS_H__ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_twis.h b/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_twis.h new file mode 100644 index 000000000..c1c66ec98 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_twis.h @@ -0,0 +1,745 @@ +/** + * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_TWIS_H__ +#define NRF_TWIS_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_twis_hal TWIS HAL + * @{ + * @ingroup nrf_twis + * @brief Hardware access layer for managing the Two Wire Interface Slave with EasyDMA + * (TWIS) peripheral. + */ + +/** @brief TWIS tasks. */ +typedef enum +{ + NRF_TWIS_TASK_STOP = offsetof(NRF_TWIS_Type, TASKS_STOP), /**< Stop TWIS transaction. */ + NRF_TWIS_TASK_SUSPEND = offsetof(NRF_TWIS_Type, TASKS_SUSPEND), /**< Suspend TWIS transaction. */ + NRF_TWIS_TASK_RESUME = offsetof(NRF_TWIS_Type, TASKS_RESUME), /**< Resume TWIS transaction. */ + NRF_TWIS_TASK_PREPARERX = offsetof(NRF_TWIS_Type, TASKS_PREPARERX), /**< Prepare the TWIS slave to respond to a write command. */ + NRF_TWIS_TASK_PREPARETX = offsetof(NRF_TWIS_Type, TASKS_PREPARETX) /**< Prepare the TWIS slave to respond to a read command. */ +} nrf_twis_task_t; + +/** @brief TWIS events. */ +typedef enum +{ + NRF_TWIS_EVENT_STOPPED = offsetof(NRF_TWIS_Type, EVENTS_STOPPED), /**< TWIS stopped. */ + NRF_TWIS_EVENT_ERROR = offsetof(NRF_TWIS_Type, EVENTS_ERROR), /**< TWIS error. */ + NRF_TWIS_EVENT_RXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_RXSTARTED), /**< Receive sequence started. */ + NRF_TWIS_EVENT_TXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_TXSTARTED), /**< Transmit sequence started. */ + NRF_TWIS_EVENT_WRITE = offsetof(NRF_TWIS_Type, EVENTS_WRITE), /**< Write command received. */ + NRF_TWIS_EVENT_READ = offsetof(NRF_TWIS_Type, EVENTS_READ) /**< Read command received. */ +} nrf_twis_event_t; + +/** @brief TWIS shortcuts. */ +typedef enum +{ + NRF_TWIS_SHORT_WRITE_SUSPEND_MASK = TWIS_SHORTS_WRITE_SUSPEND_Msk, /**< Shortcut between WRITE event and SUSPEND task. */ + NRF_TWIS_SHORT_READ_SUSPEND_MASK = TWIS_SHORTS_READ_SUSPEND_Msk, /**< Shortcut between READ event and SUSPEND task. */ +} nrf_twis_short_mask_t; + +/** @brief TWIS interrupts. */ +typedef enum +{ + NRF_TWIS_INT_STOPPED_MASK = TWIS_INTEN_STOPPED_Msk, /**< Interrupt on STOPPED event. */ + NRF_TWIS_INT_ERROR_MASK = TWIS_INTEN_ERROR_Msk, /**< Interrupt on ERROR event. */ + NRF_TWIS_INT_RXSTARTED_MASK = TWIS_INTEN_RXSTARTED_Msk, /**< Interrupt on RXSTARTED event. */ + NRF_TWIS_INT_TXSTARTED_MASK = TWIS_INTEN_TXSTARTED_Msk, /**< Interrupt on TXSTARTED event. */ + NRF_TWIS_INT_WRITE_MASK = TWIS_INTEN_WRITE_Msk, /**< Interrupt on WRITE event. */ + NRF_TWIS_INT_READ_MASK = TWIS_INTEN_READ_Msk, /**< Interrupt on READ event. */ +} nrf_twis_int_mask_t; + +/** @brief TWIS error source. */ +typedef enum +{ + NRF_TWIS_ERROR_OVERFLOW = TWIS_ERRORSRC_OVERFLOW_Msk, /**< RX buffer overflow detected, and prevented. */ + NRF_TWIS_ERROR_DATA_NACK = TWIS_ERRORSRC_DNACK_Msk, /**< NACK sent after receiving a data byte. */ + NRF_TWIS_ERROR_OVERREAD = TWIS_ERRORSRC_OVERREAD_Msk /**< TX buffer over-read detected, and prevented. */ +} nrf_twis_error_t; + +/** @brief TWIS address matching configuration. */ +typedef enum +{ + NRF_TWIS_CONFIG_ADDRESS0_MASK = TWIS_CONFIG_ADDRESS0_Msk, /**< Enable or disable address matching on ADDRESS[0]. */ + NRF_TWIS_CONFIG_ADDRESS1_MASK = TWIS_CONFIG_ADDRESS1_Msk, /**< Enable or disable address matching on ADDRESS[1]. */ + NRF_TWIS_CONFIG_ADDRESS01_MASK = TWIS_CONFIG_ADDRESS0_Msk | TWIS_CONFIG_ADDRESS1_Msk /**< Enable both address matching. */ +} nrf_twis_config_addr_mask_t; + +/** + * @brief Variable type to hold the amount of data for EasyDMA. + * + * Variable of the minimum size that can hold the amount of data to transfer. + * + * @note Defined to make it simple to change if EasyDMA is updated to support more data in + * the future devices. + */ +typedef uint8_t nrf_twis_amount_t; + +/** + * @brief Smallest variable type to hold the TWI address. + * + * Variable of the minimum size that can hold a single TWI address. + * + * @note Defined to make it simple to change if the new TWI supports for example + * 10 bit addressing mode. + */ +typedef uint8_t nrf_twis_address_t; + + +/** + * @brief Function for activating the specified TWIS task. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] task Task to be activated. + */ +__STATIC_INLINE void nrf_twis_task_trigger(NRF_TWIS_Type * p_reg, nrf_twis_task_t task); + +/** + * @brief Function for returning the address of the specified TWIS task register. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] task The specified task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrf_twis_task_address_get(NRF_TWIS_Type const * p_reg, + nrf_twis_task_t task); + +/** + * @brief Function for clearing the specified event. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] event The specified event. + */ +__STATIC_INLINE void nrf_twis_event_clear(NRF_TWIS_Type * p_reg, + nrf_twis_event_t event); + +/** + * @brief Function for retrieving the state of the TWIS event. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] event Event to be checked. + * + * @retval true The event has been generated. + * @retval false The event has not been generated. + */ +__STATIC_INLINE bool nrf_twis_event_check(NRF_TWIS_Type const * p_reg, + nrf_twis_event_t event); + +/** + * @brief Function for getting and clearing the state of the specified event. + * + * This function checks the state of the event and clears it. + * + * @param[in,out] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] event Event. + * + * @retval true The event was set. + * @retval false The event was not set. + */ +__STATIC_INLINE bool nrf_twis_event_get_and_clear(NRF_TWIS_Type * p_reg, + nrf_twis_event_t event); + +/** + * @brief Function for returning the address of the specified TWIS event register. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] event Event. + * + * @return Address. + */ +__STATIC_INLINE uint32_t nrf_twis_event_address_get(NRF_TWIS_Type const * p_reg, + nrf_twis_event_t event); + +/** + * @brief Function for setting a shortcut. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mask Mask of shortcuts to be enabled. + */ +__STATIC_INLINE void nrf_twis_shorts_enable(NRF_TWIS_Type * p_reg, uint32_t mask); + +/** + * @brief Function for clearing shortcuts. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mask Mask of shortcuts to be disabled. + */ +__STATIC_INLINE void nrf_twis_shorts_disable(NRF_TWIS_Type * p_reg, uint32_t mask); + +/** + * @brief Function for getting the shorts mask. + * + * Function returns shorts register. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Flags of currently enabled shortcuts + */ +__STATIC_INLINE uint32_t nrf_twis_shorts_get(NRF_TWIS_Type const * p_reg); + +/** + * @brief Function for enabling the specified interrupts. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mask Mask of interrupts to be enabled. + */ +__STATIC_INLINE void nrf_twis_int_enable(NRF_TWIS_Type * p_reg, uint32_t mask); + +/** + * @brief Function for retrieving the state of the specified interrupts. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mask Mask of interrupts to be checked. + * + * @retval true Any of the specified interrupts is enabled. + * @retval false None of the specified interrupts is enabled. + */ +__STATIC_INLINE bool nrf_twis_int_enable_check(NRF_TWIS_Type const * p_reg, uint32_t mask); + +/** + * @brief Function for disabling the specified interrupts. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mask Mask of interrupts to be disabled. + */ +__STATIC_INLINE void nrf_twis_int_disable(NRF_TWIS_Type * p_reg, uint32_t mask); + +#if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for setting the subscribe configuration for a given + * TWIS task. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] task Task for which to set the configuration. + * @param[in] channel Channel through which to subscribe events. + */ +__STATIC_INLINE void nrf_twis_subscribe_set(NRF_TWIS_Type * p_reg, + nrf_twis_task_t task, + uint8_t channel); + +/** + * @brief Function for clearing the subscribe configuration for a given + * TWIS task. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] task Task for which to clear the configuration. + */ +__STATIC_INLINE void nrf_twis_subscribe_clear(NRF_TWIS_Type * p_reg, + nrf_twis_task_t task); + +/** + * @brief Function for setting the publish configuration for a given + * TWIS event. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] event Event for which to set the configuration. + * @param[in] channel Channel through which to publish the event. + */ +__STATIC_INLINE void nrf_twis_publish_set(NRF_TWIS_Type * p_reg, + nrf_twis_event_t event, + uint8_t channel); + +/** + * @brief Function for clearing the publish configuration for a given + * TWIS event. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] event Event for which to clear the configuration. + */ +__STATIC_INLINE void nrf_twis_publish_clear(NRF_TWIS_Type * p_reg, + nrf_twis_event_t event); +#endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__) + +/** + * @brief Function for retrieving and clearing the TWIS error source. + * + * @attention Error sources are cleared after read. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Error source mask with values from @ref nrf_twis_error_t. + */ +__STATIC_INLINE uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * const p_reg); + +/** + * @brief Function for getting information about which of the addresses matched. + * + * Function returns index in the address table + * that points to the address that already matched. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Index of matched address. + */ +__STATIC_INLINE uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_reg); + +/** + * @brief Function for enabling TWIS. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + */ +__STATIC_INLINE void nrf_twis_enable(NRF_TWIS_Type * p_reg); + +/** + * @brief Function for disabling TWIS. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + */ +__STATIC_INLINE void nrf_twis_disable(NRF_TWIS_Type * p_reg); + +/** + * @brief Function for configuring TWIS pins. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] scl SCL pin number. + * @param[in] sda SDA pin number. + */ +__STATIC_INLINE void nrf_twis_pins_set(NRF_TWIS_Type * p_reg, uint32_t scl, uint32_t sda); + +/** + * @brief Function for setting the receive buffer. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] p_buf Pointer to the buffer for received data. + * @param[in] length Maximum number of data bytes to receive. + */ +__STATIC_INLINE void nrf_twis_rx_buffer_set(NRF_TWIS_Type * p_reg, + uint8_t * p_buf, + size_t length); + +/** + * @brief Function that prepares TWIS for receiving + * + * This function sets receive buffer and then sets NRF_TWIS_TASK_PREPARERX task. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] p_buf Pointer to the buffer for received data. + * @param[in] length Maximum number of data bytes to receive. + */ +__STATIC_INLINE void nrf_twis_rx_prepare(NRF_TWIS_Type * p_reg, + uint8_t * p_buf, + size_t length); + +/** + * @brief Function for getting number of bytes received in the last transaction. + * + * @param[in] p_reg TWIS instance. + * + * @return Amount of bytes received. + * */ +__STATIC_INLINE size_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * p_reg); + +/** + * @brief Function for setting the transmit buffer. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] p_buf Pointer to the buffer with data to send. + * @param[in] length Maximum number of data bytes to transmit. + */ +__STATIC_INLINE void nrf_twis_tx_buffer_set(NRF_TWIS_Type * p_reg, + uint8_t const * p_buf, + size_t length); + +/** + * @brief Function for preparing TWIS for transmitting. + * + * This function sets transmit buffer and then sets NRF_TWIS_TASK_PREPARETX task. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] p_buf Pointer to the buffer with data to send. + * @param[in] length Maximum number of data bytes to transmit. + */ +__STATIC_INLINE void nrf_twis_tx_prepare(NRF_TWIS_Type * p_reg, + uint8_t const * p_buf, + size_t length); + +/** + * @brief Function for getting the number of bytes transmitted in the last transaction. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Amount of bytes transmitted. + */ +__STATIC_INLINE size_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * p_reg); + +/** + * @brief Function for setting the slave address. + * + * Function sets the selected address for this TWI interface. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] n Index of address to be set. + * @param[in] addr Addres to be set. + * + * @sa nrf_twis_config_address_set + * @sa nrf_twis_config_address_get + */ +__STATIC_INLINE void nrf_twis_address_set(NRF_TWIS_Type * p_reg, + uint_fast8_t n, + nrf_twis_address_t addr); + +/** + * @brief Function for retrieving configured slave address. + * + * Function gets the selected address for this TWI interface. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] n Index of address to get. + * + * @return Configured slave address. + */ +__STATIC_INLINE nrf_twis_address_t nrf_twis_address_get(NRF_TWIS_Type const * p_reg, + uint_fast8_t n); + +/** + * @brief Function for setting the device address configuration. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] addr_mask Mask of address indexes of what device should answer to. + * + * @sa nrf_twis_address_set + */ +__STATIC_INLINE void nrf_twis_config_address_set(NRF_TWIS_Type * p_reg, + nrf_twis_config_addr_mask_t addr_mask); + +/** + * @brief Function for retrieving the device address configuration. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Mask of address indexes of what device should answer to. + */ +__STATIC_INLINE nrf_twis_config_addr_mask_t nrf_twis_config_address_get( + NRF_TWIS_Type const * p_reg); + +/** + * @brief Function for setting the over-read character. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] orc Over-read character. Character clocked out in case of + * over-read of the TXD buffer. + */ +__STATIC_INLINE void nrf_twis_orc_set(NRF_TWIS_Type * p_reg, + uint8_t orc); + +/** + * @brief Function for setting the over-read character. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Over-read character configured for selected instance. + */ +__STATIC_INLINE uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * p_reg); + + +/** @} */ /* End of nrf_twis_hal */ + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +/* ------------------------------------------------------------------------------------------------ + * Internal functions + */ + +/** + * @internal + * @brief Internal function for getting task or event register address. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] offset Offset of the register from the beginning of the instance. + * + * @attention Offset must be modulo 4 value. In other case, hardware fault can occur. + * @return Pointer to the register. + */ +__STATIC_INLINE volatile uint32_t* nrf_twis_getRegPtr(NRF_TWIS_Type const * p_reg, uint32_t offset) +{ + return (volatile uint32_t*)((uint8_t *)p_reg + (uint32_t)offset); +} + +/** + * @internal + * @brief Internal function for getting task/event register address - constant version. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] offset Offset of the register from the beginning of the instance. + * + * @attention Offset must be modulo 4 value. In other case, hardware fault can occur. + * @return Pointer to the register. + */ +__STATIC_INLINE volatile const uint32_t* nrf_twis_getRegPtr_c(NRF_TWIS_Type const * p_reg, + uint32_t offset) +{ + return (volatile const uint32_t*)((uint8_t *)p_reg + (uint32_t)offset); +} + + +/* ------------------------------------------------------------------------------------------------ + * Interface functions definitions + */ + + +__STATIC_INLINE void nrf_twis_task_trigger(NRF_TWIS_Type * p_reg, nrf_twis_task_t task) +{ + *(nrf_twis_getRegPtr(p_reg, (uint32_t)task)) = 1UL; +} + +__STATIC_INLINE uint32_t nrf_twis_task_address_get(NRF_TWIS_Type const * p_reg, + nrf_twis_task_t task) +{ + return (uint32_t)nrf_twis_getRegPtr_c(p_reg, (uint32_t)task); +} + +__STATIC_INLINE void nrf_twis_event_clear(NRF_TWIS_Type * p_reg, nrf_twis_event_t event) +{ + *(nrf_twis_getRegPtr(p_reg, (uint32_t)event)) = 0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); + (void)dummy; +#endif +} + +__STATIC_INLINE bool nrf_twis_event_check(NRF_TWIS_Type const * p_reg, nrf_twis_event_t event) +{ + return (bool)*nrf_twis_getRegPtr_c(p_reg, (uint32_t)event); +} + +__STATIC_INLINE bool nrf_twis_event_get_and_clear(NRF_TWIS_Type * p_reg, nrf_twis_event_t event) +{ + bool ret = nrf_twis_event_check(p_reg, event); + if (ret) + { + nrf_twis_event_clear(p_reg, event); + } + return ret; +} + +__STATIC_INLINE uint32_t nrf_twis_event_address_get(NRF_TWIS_Type const * p_reg, + nrf_twis_event_t event) +{ + return (uint32_t)nrf_twis_getRegPtr_c(p_reg, (uint32_t)event); +} + +__STATIC_INLINE void nrf_twis_shorts_enable(NRF_TWIS_Type * p_reg, uint32_t mask) +{ + p_reg->SHORTS |= mask; +} + +__STATIC_INLINE void nrf_twis_shorts_disable(NRF_TWIS_Type * p_reg, uint32_t mask) +{ + if (~0U == mask) + { + /* Optimized version for "disable all" */ + p_reg->SHORTS = 0; + } + else + { + p_reg->SHORTS &= ~mask; + } +} + +__STATIC_INLINE uint32_t nrf_twis_shorts_get(NRF_TWIS_Type const * p_reg) +{ + return p_reg->SHORTS; +} + +__STATIC_INLINE void nrf_twis_int_enable(NRF_TWIS_Type * p_reg, uint32_t mask) +{ + p_reg->INTENSET = mask; +} + +__STATIC_INLINE bool nrf_twis_int_enable_check(NRF_TWIS_Type const * p_reg, uint32_t mask) +{ + return (bool)(p_reg->INTENSET & mask); +} + +__STATIC_INLINE void nrf_twis_int_disable(NRF_TWIS_Type * const p_reg, uint32_t mask) +{ + p_reg->INTENCLR = mask; +} + +#if defined(DPPI_PRESENT) +__STATIC_INLINE void nrf_twis_subscribe_set(NRF_TWIS_Type * p_reg, + nrf_twis_task_t task, + uint8_t channel) +{ + *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = + ((uint32_t)channel | TWIS_SUBSCRIBE_STOP_EN_Msk); +} + +__STATIC_INLINE void nrf_twis_subscribe_clear(NRF_TWIS_Type * p_reg, + nrf_twis_task_t task) +{ + *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0; +} + +__STATIC_INLINE void nrf_twis_publish_set(NRF_TWIS_Type * p_reg, + nrf_twis_event_t event, + uint8_t channel) +{ + *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = + ((uint32_t)channel | TWIS_PUBLISH_STOPPED_EN_Msk); +} + +__STATIC_INLINE void nrf_twis_publish_clear(NRF_TWIS_Type * p_reg, + nrf_twis_event_t event) +{ + *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0; +} +#endif // defined(DPPI_PRESENT) + +__STATIC_INLINE uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * p_reg) +{ + uint32_t ret = p_reg->ERRORSRC; + p_reg->ERRORSRC = ret; + return ret; +} + +__STATIC_INLINE uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_reg) +{ + return (uint_fast8_t)p_reg->MATCH; +} + +__STATIC_INLINE void nrf_twis_enable(NRF_TWIS_Type * p_reg) +{ + p_reg->ENABLE = (TWIS_ENABLE_ENABLE_Enabled << TWIS_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_twis_disable(NRF_TWIS_Type * p_reg) +{ + p_reg->ENABLE = (TWIS_ENABLE_ENABLE_Disabled << TWIS_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_twis_pins_set(NRF_TWIS_Type * p_reg, uint32_t scl, uint32_t sda) +{ + p_reg->PSEL.SCL = scl; + p_reg->PSEL.SDA = sda; +} + +__STATIC_INLINE void nrf_twis_rx_buffer_set(NRF_TWIS_Type * p_reg, + uint8_t * p_buf, + size_t length) +{ + p_reg->RXD.PTR = (uint32_t)p_buf; + p_reg->RXD.MAXCNT = length; +} + +__STATIC_INLINE void nrf_twis_rx_prepare(NRF_TWIS_Type * p_reg, + uint8_t * p_buf, + size_t length) +{ + nrf_twis_rx_buffer_set(p_reg, p_buf, length); + nrf_twis_task_trigger(p_reg, NRF_TWIS_TASK_PREPARERX); +} + +__STATIC_INLINE size_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * p_reg) +{ + return p_reg->RXD.AMOUNT; +} + +__STATIC_INLINE void nrf_twis_tx_buffer_set(NRF_TWIS_Type * p_reg, + uint8_t const * p_buf, + size_t length) +{ + p_reg->TXD.PTR = (uint32_t)p_buf; + p_reg->TXD.MAXCNT = length; +} + +__STATIC_INLINE void nrf_twis_tx_prepare(NRF_TWIS_Type * p_reg, + uint8_t const * p_buf, + size_t length) +{ + nrf_twis_tx_buffer_set(p_reg, p_buf, length); + nrf_twis_task_trigger(p_reg, NRF_TWIS_TASK_PREPARETX); +} + +__STATIC_INLINE size_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * p_reg) +{ + return p_reg->TXD.AMOUNT; +} + +__STATIC_INLINE void nrf_twis_address_set(NRF_TWIS_Type * p_reg, + uint_fast8_t n, + nrf_twis_address_t addr) +{ + p_reg->ADDRESS[n] = addr; +} + +__STATIC_INLINE nrf_twis_address_t nrf_twis_address_get(NRF_TWIS_Type const * p_reg, uint_fast8_t n) +{ + return (nrf_twis_address_t)p_reg->ADDRESS[n]; +} +__STATIC_INLINE void nrf_twis_config_address_set(NRF_TWIS_Type * p_reg, + nrf_twis_config_addr_mask_t addr_mask) +{ + /* This is the only configuration in TWIS - just write it without masking */ + p_reg->CONFIG = addr_mask; +} + +__STATIC_INLINE nrf_twis_config_addr_mask_t nrf_twis_config_address_get(NRF_TWIS_Type const * p_reg) +{ + return (nrf_twis_config_addr_mask_t)(p_reg->CONFIG & TWIS_ADDRESS_ADDRESS_Msk); +} + +__STATIC_INLINE void nrf_twis_orc_set(NRF_TWIS_Type * p_reg, uint8_t orc) +{ + p_reg->ORC = orc; +} + +__STATIC_INLINE uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * p_reg) +{ + return (uint8_t)p_reg->ORC; +} + +#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ + + +#ifdef __cplusplus +} +#endif + +#endif /* NRF_TWIS_H__ */ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config.h b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config.h index 4fc106a87..8b39f4fd2 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config.h +++ b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config.h @@ -475,7 +475,7 @@ // NRFX_PRS_ENABLED - nrfx_prs - Peripheral Resource Sharing module //========================================================== #ifndef NRFX_PRS_ENABLED -#define NRFX_PRS_ENABLED 1 +#define NRFX_PRS_ENABLED 0 #endif // NRFX_PRS_BOX_0_ENABLED - Enables box 0 in the module. diff --git a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_glue.h b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_glue.h index e496b46e8..2bbb7b8aa 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_glue.h +++ b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_glue.h @@ -88,14 +88,14 @@ extern "C" { * @param irq_number IRQ number. * @param priority Priority to be set. */ -#define NRFX_IRQ_PRIORITY_SET(irq_number, priority) +#define NRFX_IRQ_PRIORITY_SET(irq_number, priority) NVIC_SetPriority(irq_number, priority) /** * @brief Macro for enabling a specific IRQ. * * @param irq_number IRQ number. */ -#define NRFX_IRQ_ENABLE(irq_number) +#define NRFX_IRQ_ENABLE(irq_number) NVIC_EnableIRQ(irq_number) /** * @brief Macro for checking if a specific IRQ is enabled. @@ -105,28 +105,28 @@ extern "C" { * @retval true If the IRQ is enabled. * @retval false Otherwise. */ -#define NRFX_IRQ_IS_ENABLED(irq_number) +#define NRFX_IRQ_IS_ENABLED(irq_number) NVIC_GetEnableIRQ(irq_number) /** * @brief Macro for disabling a specific IRQ. * * @param irq_number IRQ number. */ -#define NRFX_IRQ_DISABLE(irq_number) +#define NRFX_IRQ_DISABLE(irq_number) NVIC_DisableIRQ(irq_number) /** * @brief Macro for setting a specific IRQ as pending. * * @param irq_number IRQ number. */ -#define NRFX_IRQ_PENDING_SET(irq_number) +#define NRFX_IRQ_PENDING_SET(irq_number) NVIC_SetPendingIRQ(irq_number) /** * @brief Macro for clearing the pending status of a specific IRQ. * * @param irq_number IRQ number. */ -#define NRFX_IRQ_PENDING_CLEAR(irq_number) +#define NRFX_IRQ_PENDING_CLEAR(irq_number) NVIC_ClearPendingIRQ(irq_number) /** * @brief Macro for checking the pending status of a specific IRQ. @@ -134,7 +134,7 @@ extern "C" { * @retval true If the IRQ is pending. * @retval false Otherwise. */ -#define NRFX_IRQ_IS_PENDING(irq_number) +#define NRFX_IRQ_IS_PENDING(irq_number) NVIC_GetPendingIRQ(irq_number) /** @brief Macro for entering into a critical section. */ #define NRFX_CRITICAL_SECTION_ENTER() diff --git a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_log.h b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_log.h new file mode 100644 index 000000000..a3b079420 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_log.h @@ -0,0 +1,144 @@ +/** + * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_LOG_H__ +#define NRFX_LOG_H__ + +// THIS IS A TEMPLATE FILE. +// It should be copied to a suitable location within the host environment into +// which nrfx is integrated, and the following macros should be provided with +// appropriate implementations. +// And this comment should be removed from the customized file. + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_log nrfx_log.h + * @{ + * @ingroup nrfx + * + * @brief This file contains macros that should be implemented according to + * the needs of the host environment into which @em nrfx is integrated. + */ + +/** + * @brief Macro for logging a message with the severity level ERROR. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_ERROR(format, ...) + +/** + * @brief Macro for logging a message with the severity level WARNING. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_WARNING(format, ...) + +/** + * @brief Macro for logging a message with the severity level INFO. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_INFO(format, ...) + +/** + * @brief Macro for logging a message with the severity level DEBUG. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_DEBUG(format, ...) + + +/** + * @brief Macro for logging a memory dump with the severity level ERROR. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level WARNING. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level INFO. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_INFO(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level DEBUG. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length) + + +/** + * @brief Macro for getting the textual representation of a given error code. + * + * @param[in] error_code Error code. + * + * @return String containing the textual representation of the error code. + */ +#define NRFX_LOG_ERROR_STRING_GET(error_code) + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_LOG_H__ diff --git a/source/hic_hal/nordic/nrf52820/sdk.c b/source/hic_hal/nordic/nrf52820/sdk.c index 663e11458..980da8156 100644 --- a/source/hic_hal/nordic/nrf52820/sdk.c +++ b/source/hic_hal/nordic/nrf52820/sdk.c @@ -31,6 +31,8 @@ uint32_t uart_rx_pin; uint32_t sw_reset_pin; uint32_t led_usb_pin; uint32_t led_pwr_pin; +uint32_t i2c_scl_pin; +uint32_t i2c_sda_pin; COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52833(NRF52833_RESET_PIN)); COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52833(NRF52833_USB_LED_PIN)); @@ -65,6 +67,8 @@ void sdk_init() led_pwr_pin = NRF52833_PWR_LED_PIN; uart_tx_pin = NRF52833_UART_TX_PIN; uart_rx_pin = NRF52833_UART_RX_PIN; + i2c_scl_pin = NRF52833_I2C_SCL_PIN; + i2c_sda_pin = NRF52833_I2C_SDA_PIN; } else { // nRF52820 sw_reset_pin = NRF52820_RESET_PIN; @@ -72,6 +76,8 @@ void sdk_init() led_pwr_pin = NRF52820_PWR_LED_PIN; uart_tx_pin = NRF52820_UART_TX_PIN; uart_rx_pin = NRF52820_UART_RX_PIN; + i2c_scl_pin = NRF52820_I2C_SCL_PIN; + i2c_sda_pin = NRF52820_I2C_SDA_PIN; } #endif } From 2c4cfe1165500f69bbccf1d3176872212eb1fa2a Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 20 Aug 2021 11:46:51 -0500 Subject: [PATCH 443/617] nrf52820_hic: Port #840 and #842 UART fixes to nrf52820 --- source/hic_hal/nordic/nrf52820/uart.c | 60 ++++++++++++++++++++++----- 1 file changed, 49 insertions(+), 11 deletions(-) diff --git a/source/hic_hal/nordic/nrf52820/uart.c b/source/hic_hal/nordic/nrf52820/uart.c index bc3631ab9..280b0793c 100644 --- a/source/hic_hal/nordic/nrf52820/uart.c +++ b/source/hic_hal/nordic/nrf52820/uart.c @@ -45,9 +45,11 @@ circ_buf_t read_buffer; uint8_t read_buffer_data[BUFFER_SIZE]; struct { + // Number of bytes pending to be transferred. This is 0 if there is no + // ongoing transfer and the uart_handler processed the last transfer. + volatile uint32_t tx_size; + uint8_t rx; - uint8_t tx; - uint8_t tx_active; } cb_buf; void uart_handler(uint32_t event); @@ -61,6 +63,7 @@ void clear_buffers(void) int32_t uart_initialize(void) { clear_buffers(); + cb_buf.tx_size = 0; Driver_USART0.Initialize(uart_handler); Driver_USART0.PowerControl(ARM_POWER_FULL); @@ -70,8 +73,11 @@ int32_t uart_initialize(void) int32_t uart_uninitialize(void) { USART_INSTANCE.Control(ARM_USART_CONTROL_RX, 0); + USART_INSTANCE.Control(ARM_USART_ABORT_RECEIVE, 0U); + Driver_USART0.PowerControl(ARM_POWER_OFF); Driver_USART0.Uninitialize(); clear_buffers(); + cb_buf.tx_size = 0; return 1; } @@ -153,6 +159,11 @@ int32_t uart_set_configuration(UART_Configuration *config) NVIC_DisableIRQ(USART_IRQ); clear_buffers(); + + // If there was no Receive() call in progress aborting it is harmless. + USART_INSTANCE.Control(ARM_USART_CONTROL_RX, 0U); + USART_INSTANCE.Control(ARM_USART_ABORT_RECEIVE, 0U); + uint32_t r = USART_INSTANCE.Control(control, config->Baudrate); if (r != ARM_DRIVER_OK) { return 0; @@ -177,10 +188,42 @@ int32_t uart_write_free(void) return circ_buf_count_free(&write_buffer); } +// Start a new TX transfer if there are bytes pending to be transferred on the +// write_buffer buffer. The transferred bytes are not removed from the circular +// by this function, only the event handler will remove them once the transfer +// is done. +static void uart_start_tx_transfer() { + uint32_t tx_size = 0; + const uint8_t* buf = circ_buf_peek(&write_buffer, &tx_size); + if (tx_size > BUFFER_SIZE / 4) { + // The bytes being transferred remain on the circular buffer memory + // until the transfer is done. Limiting the UART transfer size + // allows the uart_handler to clear those bytes earlier. + tx_size = BUFFER_SIZE / 4; + } + cb_buf.tx_size = tx_size; + if (tx_size) { + USART_INSTANCE.Send(buf, tx_size); + } +} + int32_t uart_write_data(uint8_t *data, uint16_t size) { + if (size == 0) { + return 0; + } + uint32_t cnt = circ_buf_write(&write_buffer, data, size); - NVIC_SetPendingIRQ(USART_IRQ); + if (cb_buf.tx_size == 0) { + // There's no pending transfer and the value of cb_buf.tx_size will not + // change to non-zero by the event handler once it is zero. Note that it + // is entirely possible that we transferred all the bytes we added to + // the circular buffer in this function by the time we are in this + // branch, in that case uart_start_tx_transfer() would not schedule any + // transfer. + uart_start_tx_transfer(); + } + return cnt; } @@ -202,13 +245,8 @@ void uart_handler(uint32_t event) { USART_INSTANCE.Receive(&(cb_buf.rx), 1); } - if ((event & ARM_USART_EVENT_SEND_COMPLETE) || !cb_buf.tx_active) { - if (circ_buf_count_used(&write_buffer) > 0) { - cb_buf.tx_active = true; - cb_buf.tx = circ_buf_pop(&write_buffer); - USART_INSTANCE.Send(&(cb_buf.tx), 1); - } else { - cb_buf.tx_active = false; - } + if (event & ARM_USART_EVENT_SEND_COMPLETE) { + circ_buf_pop_n(&write_buffer, cb_buf.tx_size); + uart_start_tx_transfer(); } } From dc4a5a3944ac5af2206b5484a1cef7485ee1ed03 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 9 Sep 2021 21:25:11 -0500 Subject: [PATCH 444/617] nrf52820_hic: bump default SWD frequency to 8 MHz --- source/hic_hal/nordic/nrf52820/DAP_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/hic_hal/nordic/nrf52820/DAP_config.h b/source/hic_hal/nordic/nrf52820/DAP_config.h index 84b59eded..ebca8f88e 100644 --- a/source/hic_hal/nordic/nrf52820/DAP_config.h +++ b/source/hic_hal/nordic/nrf52820/DAP_config.h @@ -83,7 +83,7 @@ This information includes: /// Default communication speed on the Debug Access Port for SWD and JTAG mode. /// Used to initialize the default SWD/JTAG clock frequency. /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting. -#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz. +#define DAP_DEFAULT_SWJ_CLOCK 8000000U ///< Default SWD/JTAG clock frequency in Hz. /// Maximum Package Size for Command and Response data. /// This configuration settings is used to optimize the communication performance with the From b3daa082b2f37939d36b9d1f42ce07166090fdf1 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 22 Sep 2021 00:15:49 -0500 Subject: [PATCH 445/617] nrf52820_hic: support for case-sensitive file-system and compilation with armclang --- records/hic_hal/nrf52820.yaml | 3 +++ source/hic_hal/nordic/nrf52820/gpio.c | 2 +- source/hic_hal/nordic/nrf52820/sdk.c | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/records/hic_hal/nrf52820.yaml b/records/hic_hal/nrf52820.yaml index 3e70724cc..d4c5447e4 100644 --- a/records/hic_hal/nrf52820.yaml +++ b/records/hic_hal/nrf52820.yaml @@ -38,6 +38,9 @@ tool_specific: hic_hal: - source/hic_hal/nordic/nrf52820/armcc armclang: + misc: + common_flags: + - -mfpu=none sources: hic_hal: - source/hic_hal/nordic/nrf52820/armcc diff --git a/source/hic_hal/nordic/nrf52820/gpio.c b/source/hic_hal/nordic/nrf52820/gpio.c index 6162aff26..88b500893 100644 --- a/source/hic_hal/nordic/nrf52820/gpio.c +++ b/source/hic_hal/nordic/nrf52820/gpio.c @@ -21,7 +21,7 @@ #include "gpio.h" -#include "IO_config.h" +#include "IO_Config.h" #if (defined(GPIO_LED_ACTIVE_STATE) && (GPIO_LED_ACTIVE_STATE == 1)) #define GPIO_LED_STATE(state) (state ? 1 : 0) diff --git a/source/hic_hal/nordic/nrf52820/sdk.c b/source/hic_hal/nordic/nrf52820/sdk.c index 980da8156..a35e38109 100644 --- a/source/hic_hal/nordic/nrf52820/sdk.c +++ b/source/hic_hal/nordic/nrf52820/sdk.c @@ -20,7 +20,7 @@ */ #include "device.h" -#include "IO_config.h" +#include "IO_Config.h" #include "daplink.h" #include "compiler.h" #include "util.h" From 96a3108a8310ba00a5c8f16d43cc7905134b0e43 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 30 Sep 2021 22:46:56 -0500 Subject: [PATCH 446/617] nrf52820_hic: update to nrfx v2.5.0 (1/3) From https://github.com/NordicSemiconductor/nrfx at tag 'v2.5.0' --- records/board/nrf52820_if.yaml | 2 +- source/board/nrf52820_if.c | 3 +- .../nrf52820/cmsis/compiler_abstraction.h | 2 + source/hic_hal/nordic/nrf52820/cmsis/nrf.h | 6 +- .../nordic/nrf52820/cmsis/nrf51_erratas.h | 2 + .../nordic/nrf52820/cmsis/nrf51_to_nrf52.h | 2 + source/hic_hal/nordic/nrf52820/cmsis/nrf52.h | 32 +- .../hic_hal/nordic/nrf52820/cmsis/nrf52820.h | 94 ++- .../nrf52820/cmsis/nrf52820_bitfields.h | 642 +++++++-------- .../nrf52820/cmsis/nrf52820_peripherals.h | 2 + .../nrf52820/cmsis/nrf52833_to_nrf52820.h | 2 + .../nordic/nrf52820/cmsis/nrf52_bitfields.h | 33 +- .../nordic/nrf52820/cmsis/nrf52_erratas.h | 729 ++++++++++++++---- .../nordic/nrf52820/cmsis/nrf52_name_change.h | 2 + .../nordic/nrf52820/cmsis/nrf52_to_nrf52810.h | 2 + .../nordic/nrf52820/cmsis/nrf52_to_nrf52833.h | 2 + .../nordic/nrf52820/cmsis/nrf52_to_nrf52840.h | 2 + .../nordic/nrf52820/cmsis/nrf53_erratas.h | 2 + .../nordic/nrf52820/cmsis/nrf91_erratas.h | 2 + .../nordic/nrf52820/cmsis/nrf_erratas.h | 2 + .../nordic/nrf52820/cmsis/system_nrf52.c | 9 +- .../nrf52820/nrfx/drivers/nrfx_common.h | 87 ++- .../nrf52820/nrfx/drivers/nrfx_errors.h | 47 +- .../nrf52820/nrfx/drivers/prs/nrfx_prs.h | 63 +- .../nordic/nrf52820/nrfx/hal/nrf_common.h | 62 ++ .../nordic/nrf52820/nrfx/hal/nrf_gpio.h | 380 +++++---- .../nrf52820/nrfx/mdk/nrf52820_peripherals.h | 61 +- .../nrf52820/nrfx/mdk/nrf_peripherals.h | 41 +- .../nrfx/mdk/system_nrf52_approtect.h | 65 ++ source/hic_hal/nordic/nrf52820/nrfx/nrfx.h | 48 +- .../hic_hal/nordic/nrf52820/nrfx/nrfx_glue.h | 73 +- .../hic_hal/nordic/nrf52820/nrfx/nrfx_log.h | 47 +- 32 files changed, 1646 insertions(+), 902 deletions(-) create mode 100644 source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_common.h create mode 100644 source/hic_hal/nordic/nrf52820/nrfx/mdk/system_nrf52_approtect.h diff --git a/records/board/nrf52820_if.yaml b/records/board/nrf52820_if.yaml index 14c135567..e1020ec12 100644 --- a/records/board/nrf52820_if.yaml +++ b/records/board/nrf52820_if.yaml @@ -7,5 +7,5 @@ common: board: - source/board/nrf52820_if.c target: - - source/family/nordic/nrf5x/target.c + - source/family/nordic/nrf52/target.c - source/family/nordic/target_reset_nrf52.c diff --git a/source/board/nrf52820_if.c b/source/board/nrf52820_if.c index 66ab4be84..630a5e725 100644 --- a/source/board/nrf52820_if.c +++ b/source/board/nrf52820_if.c @@ -26,9 +26,10 @@ const char * const board_id_nrf52 = "1101"; const char * const board_id_nrf52_64 = "9903"; const char * const board_id_nrf52840 = "1102"; -extern target_cfg_t target_device_nrf52; +extern target_cfg_t target_device_nrf51822_32; extern target_cfg_t target_device_nrf52_64; extern target_cfg_t target_device_nrf52840; +target_cfg_t target_device; static void nrf_prerun_board_config(void) { #if defined(TARGET_NRF52) diff --git a/source/hic_hal/nordic/nrf52820/cmsis/compiler_abstraction.h b/source/hic_hal/nordic/nrf52820/cmsis/compiler_abstraction.h index c239fd11c..b687bfabe 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/compiler_abstraction.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/compiler_abstraction.h @@ -2,6 +2,8 @@ Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. +SPDX-License-Identifier: BSD-3-Clause + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf.h index 6f47bd421..8a122273d 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf.h @@ -2,6 +2,8 @@ Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. +SPDX-License-Identifier: BSD-3-Clause + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -35,8 +37,8 @@ POSSIBILITY OF SUCH DAMAGE. /* MDK version */ #define MDK_MAJOR_VERSION 8 -#define MDK_MINOR_VERSION 38 -#define MDK_MICRO_VERSION 0 +#define MDK_MINOR_VERSION 40 +#define MDK_MICRO_VERSION 2 /* Define coprocessor domains */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf51_erratas.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf51_erratas.h index aad134a42..931ed62fa 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf51_erratas.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf51_erratas.h @@ -5,6 +5,8 @@ Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. +SPDX-License-Identifier: BSD-3-Clause + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf51_to_nrf52.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf51_to_nrf52.h index 2168fb44c..77a7588e7 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf51_to_nrf52.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf51_to_nrf52.h @@ -2,6 +2,8 @@ Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. +SPDX-License-Identifier: BSD-3-Clause + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52.h index 28f759663..6aab0ea8b 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52.h @@ -1,6 +1,8 @@ /* * Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -30,10 +32,10 @@ * @file nrf52.h * @brief CMSIS HeaderFile * @version 1 - * @date 15. January 2021 - * @note Generated by SVDConv V3.3.35 on Friday, 15.01.2021 17:02:05 + * @date 29. April 2021 + * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:45 * from File 'nrf52.svd', - * last modified on Friday, 15.01.2021 16:02:00 + * last modified on Thursday, 29.04.2021 10:43:40 */ @@ -752,13 +754,33 @@ typedef struct { /*!< (@ 0x10001000) UICR Structu __IM uint32_t RESERVED1[64]; __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[0]: Mapping of the nRESET function (see POWER chapter for details) */ - __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access Port protection */ + __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */ } NRF_UICR_Type; /*!< Size = 528 (0x210) */ +/* =========================================================================================================================== */ +/* ================ APPROTECT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Access Port Protection (APPROTECT) + */ + +typedef struct { /*!< (@ 0x40000000) APPROTECT Structure */ + __IM uint32_t RESERVED[340]; + __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000550) Software force enable APPROTECT mechanism until + next reset. This register can only be written + once. */ + __IM uint32_t RESERVED1; + __IOM uint32_t DISABLE; /*!< (@ 0x00000558) Software disable APPROTECT mechanism */ +} NRF_APPROTECT_Type; /*!< Size = 1372 (0x55c) */ + + + /* =========================================================================================================================== */ /* ================ BPROT ================ */ /* =========================================================================================================================== */ @@ -2268,6 +2290,7 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure #define NRF_FICR_BASE 0x10000000UL #define NRF_UICR_BASE 0x10001000UL +#define NRF_APPROTECT_BASE 0x40000000UL #define NRF_BPROT_BASE 0x40000000UL #define NRF_POWER_BASE 0x40000000UL #define NRF_CLOCK_BASE 0x40000000UL @@ -2346,6 +2369,7 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) +#define NRF_APPROTECT ((NRF_APPROTECT_Type*) NRF_APPROTECT_BASE) #define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52820.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52820.h index 8f1ab8801..b2c42a12d 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52820.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52820.h @@ -1,6 +1,8 @@ /* * Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -30,10 +32,10 @@ * @file nrf52820.h * @brief CMSIS HeaderFile * @version 1 - * @date 15. January 2021 - * @note Generated by SVDConv V3.3.35 on Friday, 15.01.2021 17:02:04 + * @date 29. April 2021 + * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:44 * from File 'nrf52820.svd', - * last modified on Friday, 15.01.2021 16:02:00 + * last modified on Thursday, 29.04.2021 10:43:41 */ @@ -470,8 +472,8 @@ typedef struct { * @brief PPI_CH [CH] (PPI Channel) */ typedef struct { - __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event end-point */ - __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task end-point */ + __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event endpoint */ + __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task endpoint */ } PPI_CH_Type; /*!< Size = 8 (0x8) */ @@ -479,7 +481,7 @@ typedef struct { * @brief PPI_FORK [FORK] (Fork) */ typedef struct { - __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task end-point */ + __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task endpoint */ } PPI_FORK_Type; /*!< Size = 4 (0x4) */ @@ -627,11 +629,30 @@ typedef struct { /*!< (@ 0x10001000) UICR Structu __IM uint32_t RESERVED4[60]; __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) Output voltage from REG0 regulator stage. The maximum output voltage from this stage is - given as VDDH - VREG0DROP. */ + given as VDDH - V_VDDH-VDD. */ } NRF_UICR_Type; /*!< Size = 776 (0x308) */ +/* =========================================================================================================================== */ +/* ================ APPROTECT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Access Port Protection (APPROTECT) + */ + +typedef struct { /*!< (@ 0x40000000) APPROTECT Structure */ + __IM uint32_t RESERVED[340]; + __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000550) Software force enable APPROTECT mechanism until + next reset. */ + __IM uint32_t RESERVED1; + __IOM uint32_t DISABLE; /*!< (@ 0x00000558) Software disable APPROTECT mechanism */ +} NRF_APPROTECT_Type; /*!< Size = 1372 (0x55c) */ + + + /* =========================================================================================================================== */ /* ================ CLOCK ================ */ /* =========================================================================================================================== */ @@ -755,7 +776,7 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ - __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour + __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behavior and LDETECT mode */ __IM uint32_t RESERVED1[118]; __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO @@ -809,7 +830,7 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new ED sample is ready for readout from the - RADIO.EDSAMPLE register */ + RADIO.EDSAMPLE register. */ __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ @@ -989,8 +1010,8 @@ typedef struct { /*!< (@ 0x40002000) UARTE0 Struc __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t RESERVED9[93]; - __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write - one to clear. */ + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one + to clear. */ __IM uint32_t RESERVED10[31]; __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ __IM uint32_t RESERVED11; @@ -1212,9 +1233,8 @@ typedef struct { /*!< (@ 0x40003000) TWIM0 Struct __IM uint32_t RESERVED4[7]; __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ __IM uint32_t RESERVED5[8]; - __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND - task has been issued, TWI traffic is now - suspended. */ + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is + now suspended. */ __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ __IM uint32_t RESERVED6[2]; @@ -1406,8 +1426,8 @@ typedef struct { /*!< (@ 0x4000B000) RTC0 Structu __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ __IM uint32_t RESERVED4[110]; __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ - __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu - t be written when RTC is stopped */ + __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). + Must be written when RTC is stopped. */ __IM uint32_t RESERVED5[13]; __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ @@ -1434,25 +1454,25 @@ typedef struct { /*!< (@ 0x4000C000) TEMP Structu __IM uint32_t RESERVED2[127]; __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ __IM uint32_t RESERVED3[5]; - __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ - __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ - __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ - __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ - __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ - __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ + __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of first piecewise linear function */ + __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of second piecewise linear function */ + __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of third piecewise linear function */ + __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of fourth piecewise linear function */ + __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of fifth piecewise linear function */ + __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of sixth piecewise linear function */ __IM uint32_t RESERVED4[2]; - __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ - __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ - __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ - __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ - __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ - __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ + __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of first piecewise linear function */ + __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of second piecewise linear function */ + __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of third piecewise linear function */ + __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of fourth piecewise linear function */ + __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of fifth piecewise linear function */ + __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of sixth piecewise linear function */ __IM uint32_t RESERVED5[2]; - __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ - __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ - __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ - __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ - __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ + __IOM uint32_t T0; /*!< (@ 0x00000560) End point of first piecewise linear function */ + __IOM uint32_t T1; /*!< (@ 0x00000564) End point of second piecewise linear function */ + __IOM uint32_t T2; /*!< (@ 0x00000568) End point of third piecewise linear function */ + __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of fourth piecewise linear function */ + __IOM uint32_t T4; /*!< (@ 0x00000570) End point of fifth piecewise linear function */ } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ @@ -1553,7 +1573,7 @@ typedef struct { /*!< (@ 0x4000F000) AAR Structur */ typedef struct { /*!< (@ 0x4000F000) CCM Structure */ - __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation + __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. This operation will stop by itself when completed. */ __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will stop by itself when completed. */ @@ -1562,7 +1582,7 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ __IM uint32_t RESERVED[60]; - __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ + __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation complete */ __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ __IM uint32_t RESERVED1[61]; @@ -1580,7 +1600,7 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ - __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of key-stream generated when MODE.LENGTH + __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH = Extended. */ __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ } NRF_CCM_Type; /*!< Size = 1312 (0x520) */ @@ -1949,6 +1969,7 @@ typedef struct { /*!< (@ 0x40027000) USBD Structu #define NRF_FICR_BASE 0x10000000UL #define NRF_UICR_BASE 0x10001000UL +#define NRF_APPROTECT_BASE 0x40000000UL #define NRF_CLOCK_BASE 0x40000000UL #define NRF_POWER_BASE 0x40000000UL #define NRF_P0_BASE 0x50000000UL @@ -2013,6 +2034,7 @@ typedef struct { /*!< (@ 0x40027000) USBD Structu #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) +#define NRF_APPROTECT ((NRF_APPROTECT_Type*) NRF_APPROTECT_BASE) #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_bitfields.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_bitfields.h index c9156f9da..3c0d24d3e 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_bitfields.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_bitfields.h @@ -2,6 +2,8 @@ Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. +SPDX-License-Identifier: BSD-3-Clause + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -148,7 +150,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: AAR_NIRK */ /* Description: Number of IRKs */ -/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */ +/* Bits 4..0 : Number of Identity Root Keys available in the IRK data structure */ #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ @@ -207,13 +209,33 @@ POSSIBILITY OF SUCH DAMAGE. #define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n */ +/* Peripheral: APPROTECT */ +/* Description: Access Port Protection */ + +/* Register: APPROTECT_FORCEPROTECT */ +/* Description: Software force enable APPROTECT mechanism until next reset. */ + +/* Bits 7..0 : Write 0x0 to force enable APPROTECT mechanism */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (0UL) /*!< Position of FORCEPROTECT field. */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0xFFUL << APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x0UL) /*!< Software force enable APPROTECT mechanism */ + +/* Register: APPROTECT_DISABLE */ +/* Description: Software disable APPROTECT mechanism */ + +/* Bits 7..0 : Software disable APPROTECT mechanism */ +#define APPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */ +#define APPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */ +#define APPROTECT_DISABLE_DISABLE_SwDisable (0x5AUL) /*!< Software disable APPROTECT mechanism */ + + /* Peripheral: CCM */ /* Description: AES CCM Mode Encryption */ /* Register: CCM_TASKS_KSGEN */ -/* Description: Start generation of key-stream. This operation will stop by itself when completed. */ +/* Description: Start generation of keystream. This operation will stop by itself when completed. */ -/* Bit 0 : Start generation of key-stream. This operation will stop by itself when completed. */ +/* Bit 0 : Start generation of keystream. This operation will stop by itself when completed. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */ @@ -243,9 +265,9 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_EVENTS_ENDKSGEN */ -/* Description: Key-stream generation complete */ +/* Description: Keystream generation complete */ -/* Bit 0 : Key-stream generation complete */ +/* Bit 0 : Keystream generation complete */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */ @@ -350,8 +372,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 24 : Packet length configuration */ #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ -#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. */ -#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ +#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. */ +#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ /* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */ #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ @@ -391,15 +413,15 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_SCRATCHPTR */ /* Description: Pointer to data area used for temporary storage */ -/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during keystream generation, MIC generation and encryption/decryption. */ #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ /* Register: CCM_MAXPACKETSIZE */ -/* Description: Length of key-stream generated when MODE.LENGTH = Extended. */ +/* Description: Length of keystream generated when MODE.LENGTH = Extended. */ -/* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ +/* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */ @@ -1501,6 +1523,9 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ +#define FICR_INFO_VARIANT_VARIANT_AABC (0x41414243UL) /*!< AABC */ +#define FICR_INFO_VARIANT_VARIANT_AAC0 (0x41414330UL) /*!< AAC0 */ +#define FICR_INFO_VARIANT_VARIANT_AAC1 (0x41414331UL) /*!< AAC1 */ #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_PACKAGE */ @@ -1509,7 +1534,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Package option */ #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ -#define FICR_INFO_PACKAGE_PACKAGE_QD (0x2007UL) /*!< QDxx - 40-pin QFN */ +#define FICR_INFO_PACKAGE_PACKAGE_QD (0x2007UL) /*!< QDxx - 5x5 40-pin QFN */ #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_RAM */ @@ -2164,224 +2189,224 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 30 : Pin 30 */ #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 29 : Pin 29 */ #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 28 : Pin 28 */ #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 27 : Pin 27 */ #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 26 : Pin 26 */ #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 25 : Pin 25 */ #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 24 : Pin 24 */ #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 23 : Pin 23 */ #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 22 : Pin 22 */ #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 21 : Pin 21 */ #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 20 : Pin 20 */ #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 19 : Pin 19 */ #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 18 : Pin 18 */ #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 17 : Pin 17 */ #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 16 : Pin 16 */ #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 15 : Pin 15 */ #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 14 : Pin 14 */ #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 13 : Pin 13 */ #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 12 : Pin 12 */ #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 11 : Pin 11 */ #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 10 : Pin 10 */ #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 9 : Pin 9 */ #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 8 : Pin 8 */ #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 7 : Pin 7 */ #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 6 : Pin 6 */ #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 5 : Pin 5 */ #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 4 : Pin 4 */ #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 3 : Pin 3 */ #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 2 : Pin 2 */ #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 1 : Pin 1 */ #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 0 : Pin 0 */ #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Register: GPIO_OUTCLR */ /* Description: Clear individual bits in GPIO port */ @@ -2391,224 +2416,224 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 30 : Pin 30 */ #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 29 : Pin 29 */ #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 28 : Pin 28 */ #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 27 : Pin 27 */ #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 26 : Pin 26 */ #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 25 : Pin 25 */ #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 24 : Pin 24 */ #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 23 : Pin 23 */ #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 22 : Pin 22 */ #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 21 : Pin 21 */ #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 20 : Pin 20 */ #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 19 : Pin 19 */ #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 18 : Pin 18 */ #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 17 : Pin 17 */ #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 16 : Pin 16 */ #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 15 : Pin 15 */ #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 14 : Pin 14 */ #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 13 : Pin 13 */ #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 12 : Pin 12 */ #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 11 : Pin 11 */ #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 10 : Pin 10 */ #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 9 : Pin 9 */ #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 8 : Pin 8 */ #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 7 : Pin 7 */ #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 6 : Pin 6 */ #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 5 : Pin 5 */ #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 4 : Pin 4 */ #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 3 : Pin 3 */ #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 2 : Pin 2 */ #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 1 : Pin 1 */ #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 0 : Pin 0 */ #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Register: GPIO_IN */ /* Description: Read GPIO port */ @@ -3008,224 +3033,224 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 30 : Set as output pin 30 */ #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 29 : Set as output pin 29 */ #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 28 : Set as output pin 28 */ #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 27 : Set as output pin 27 */ #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 26 : Set as output pin 26 */ #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 25 : Set as output pin 25 */ #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 24 : Set as output pin 24 */ #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 23 : Set as output pin 23 */ #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 22 : Set as output pin 22 */ #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 21 : Set as output pin 21 */ #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 20 : Set as output pin 20 */ #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 19 : Set as output pin 19 */ #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 18 : Set as output pin 18 */ #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 17 : Set as output pin 17 */ #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 16 : Set as output pin 16 */ #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 15 : Set as output pin 15 */ #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 14 : Set as output pin 14 */ #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 13 : Set as output pin 13 */ #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 12 : Set as output pin 12 */ #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 11 : Set as output pin 11 */ #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 10 : Set as output pin 10 */ #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 9 : Set as output pin 9 */ #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 8 : Set as output pin 8 */ #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 7 : Set as output pin 7 */ #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 6 : Set as output pin 6 */ #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 5 : Set as output pin 5 */ #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 4 : Set as output pin 4 */ #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 3 : Set as output pin 3 */ #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 2 : Set as output pin 2 */ #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 1 : Set as output pin 1 */ #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 0 : Set as output pin 0 */ #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Register: GPIO_DIRCLR */ /* Description: DIR clear register */ @@ -3235,224 +3260,224 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 30 : Set as input pin 30 */ #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 29 : Set as input pin 29 */ #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 28 : Set as input pin 28 */ #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 27 : Set as input pin 27 */ #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 26 : Set as input pin 26 */ #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 25 : Set as input pin 25 */ #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 24 : Set as input pin 24 */ #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 23 : Set as input pin 23 */ #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 22 : Set as input pin 22 */ #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 21 : Set as input pin 21 */ #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 20 : Set as input pin 20 */ #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 19 : Set as input pin 19 */ #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 18 : Set as input pin 18 */ #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 17 : Set as input pin 17 */ #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 16 : Set as input pin 16 */ #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 15 : Set as input pin 15 */ #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 14 : Set as input pin 14 */ #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 13 : Set as input pin 13 */ #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 12 : Set as input pin 12 */ #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 11 : Set as input pin 11 */ #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 10 : Set as input pin 10 */ #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 9 : Set as input pin 9 */ #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 8 : Set as input pin 8 */ #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 7 : Set as input pin 7 */ #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 6 : Set as input pin 6 */ #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 5 : Set as input pin 5 */ #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 4 : Set as input pin 4 */ #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 3 : Set as input pin 3 */ #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 2 : Set as input pin 2 */ #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 1 : Set as input pin 1 */ #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 0 : Set as input pin 0 */ #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Register: GPIO_LATCH */ /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ @@ -3650,13 +3675,13 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ /* Register: GPIO_DETECTMODE */ -/* Description: Select between default DETECT signal behaviour and LDETECT mode */ +/* Description: Select between default DETECT signal behavior and LDETECT mode */ -/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */ +/* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */ #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ -#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ +#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */ /* Register: GPIO_PIN_CNF */ /* Description: Description collection: Configuration of GPIO pins */ @@ -4314,224 +4339,224 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PPI_CHENSET */ /* Description: Channel enable set register */ -/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */ +/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ -/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */ +/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */ -/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */ +/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */ -/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */ +/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */ -/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */ +/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */ -/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */ +/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */ -/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */ +/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */ -/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */ +/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */ -/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */ +/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */ -/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */ +/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */ -/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */ +/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */ -/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */ +/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */ -/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */ +/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ #define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */ -/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */ +/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ #define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */ -/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */ +/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ #define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */ -/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */ +/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ #define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */ -/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */ +/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ -/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */ +/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ -/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */ +/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ -/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */ +/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ -/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */ +/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ -/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */ +/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ -/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */ +/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ -/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */ +/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ -/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */ +/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ -/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */ +/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ -/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */ +/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ -/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */ +/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ -/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */ +/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ -/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */ +/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ -/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */ +/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ -/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */ +/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */ @@ -4541,224 +4566,224 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PPI_CHENCLR */ /* Description: Channel enable clear register */ -/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */ +/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */ -/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */ +/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */ -/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */ +/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */ -/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */ +/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */ -/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */ +/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */ -/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */ +/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */ -/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */ +/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */ -/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */ +/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */ -/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */ +/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */ -/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */ +/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */ -/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */ +/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */ -/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */ +/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */ -/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */ +/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ #define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */ -/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */ +/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ #define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */ -/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */ +/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ #define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */ -/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */ +/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ #define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */ -/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */ +/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */ -/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */ +/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */ -/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */ +/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */ -/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */ +/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */ -/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */ +/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */ -/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */ +/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */ -/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */ +/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */ -/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */ +/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */ -/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */ +/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */ -/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */ +/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */ -/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */ +/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */ -/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */ +/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */ -/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */ +/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */ -/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */ +/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */ -/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */ +/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */ -/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */ +/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */ @@ -4766,14 +4791,14 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ /* Register: PPI_CH_EEP */ -/* Description: Description cluster: Channel n event end-point */ +/* Description: Description cluster: Channel n event endpoint */ /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ /* Register: PPI_CH_TEP */ -/* Description: Description cluster: Channel n task end-point */ +/* Description: Description cluster: Channel n task endpoint */ /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ @@ -4975,7 +5000,7 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHG_CH0_Included (1UL) /*!< Include */ /* Register: PPI_FORK_TEP */ -/* Description: Description cluster: Channel n task end-point */ +/* Description: Description cluster: Channel n task endpoint */ /* Bits 31..0 : Pointer to task register */ #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ @@ -5237,23 +5262,23 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_REPORTPER */ /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ -/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */ +/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. */ #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ -#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */ -#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */ -#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */ -#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */ -#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */ -#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */ -#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */ -#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */ -#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */ +#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples/report */ +#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples/report */ +#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples/report */ +#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples/report */ +#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples/report */ +#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples/report */ +#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples/report */ +#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples/report */ +#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample/report */ /* Register: QDEC_ACC */ /* Description: Register accumulating the valid transitions */ -/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */ +/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register. */ #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ @@ -5550,9 +5575,9 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_EDEND */ -/* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register */ +/* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ -/* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register */ +/* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL) /*!< Event not generated */ @@ -6205,7 +6230,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_FREQUENCY */ /* Description: Frequency */ -/* Bit 8 : Channel map selection. */ +/* Bit 8 : Channel map selection */ #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */ @@ -6282,15 +6307,15 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ -/* Bits 19..16 : Length on air of S1 field in number of bits. */ +/* Bits 19..16 : Length on air of S1 field in number of bits */ #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ -/* Bit 8 : Length on air of S0 field in number of bytes. */ +/* Bit 8 : Length on air of S0 field in number of bytes */ #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ -/* Bits 3..0 : Length on air of LENGTH field in number of bits. */ +/* Bits 3..0 : Length on air of LENGTH field in number of bits */ #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ @@ -6441,7 +6466,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ #define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after length field. */ -/* Bits 1..0 : CRC length in number of bytes. */ +/* Bits 1..0 : CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported */ #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ @@ -6466,14 +6491,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_TIFS */ /* Description: Interframe spacing in us */ -/* Bits 9..0 : Interframe spacing in us */ +/* Bits 9..0 : Interframe spacing in us. */ #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ /* Register: RADIO_RSSISAMPLE */ /* Description: RSSI sample */ -/* Bits 6..0 : RSSI sample */ +/* Bits 6..0 : RSSI sample. */ #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ @@ -6632,7 +6657,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */ -#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information */ +#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information */ /* Register: RADIO_SFD */ /* Description: IEEE 802.15.4 start of frame delimiter */ @@ -6700,32 +6725,32 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_CTEINLINECONF_S0CONF_Pos (16UL) /*!< Position of S0CONF field. */ #define RADIO_CTEINLINECONF_S0CONF_Msk (0xFFUL << RADIO_CTEINLINECONF_S0CONF_Pos) /*!< Bit mask of S0CONF field. */ -/* Bits 15..13 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */ +/* Bits 15..13 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */ #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos (13UL) /*!< Position of CTEINLINERXMODE2US field. */ #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos) /*!< Bit mask of CTEINLINERXMODE2US field. */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (1UL) /*!< 4us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (2UL) /*!< 2us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (3UL) /*!< 1us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (4UL) /*!< 0.5us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (5UL) /*!< 0.25us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (6UL) /*!< 0.125us */ - -/* Bits 12..10 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (1UL) /*!< 4 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (2UL) /*!< 2 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (3UL) /*!< 1 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (4UL) /*!< 0.5 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (5UL) /*!< 0.25 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (6UL) /*!< 0.125 us */ + +/* Bits 12..10 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */ #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos (10UL) /*!< Position of CTEINLINERXMODE1US field. */ #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos) /*!< Bit mask of CTEINLINERXMODE1US field. */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (1UL) /*!< 4us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (2UL) /*!< 2us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (3UL) /*!< 1us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (4UL) /*!< 0.5us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (5UL) /*!< 0.25us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (6UL) /*!< 0.125us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (1UL) /*!< 4 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (2UL) /*!< 2 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (3UL) /*!< 1 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (4UL) /*!< 0.5 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (5UL) /*!< 0.25 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (6UL) /*!< 0.125 us */ /* Bits 7..6 : Max range of CTETime */ #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos (6UL) /*!< Position of CTETIMEVALIDRANGE field. */ #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Msk (0x3UL << RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos) /*!< Bit mask of CTETIMEVALIDRANGE field. */ -#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0UL) /*!< 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20 */ -#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (1UL) /*!< 31 in 8us unit */ -#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (2UL) /*!< 63 in 8us unit */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0UL) /*!< 20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20 */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (1UL) /*!< 31 in 8 us unit */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (2UL) /*!< 63 in 8 us unit */ /* Bit 4 : Sampling/switching if CRC is not OK */ #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos (4UL) /*!< Position of CTEERRORHANDLING field. */ @@ -6760,12 +6785,12 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 18..16 : Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 */ #define RADIO_DFECTRL1_TSAMPLESPACING_Pos (16UL) /*!< Position of TSAMPLESPACING field. */ #define RADIO_DFECTRL1_TSAMPLESPACING_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACING_Pos) /*!< Bit mask of TSAMPLESPACING field. */ -#define RADIO_DFECTRL1_TSAMPLESPACING_4us (1UL) /*!< 4us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_2us (2UL) /*!< 2us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_1us (3UL) /*!< 1us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_500ns (4UL) /*!< 0.5us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_250ns (5UL) /*!< 0.25us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_125ns (6UL) /*!< 0.125us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_4us (1UL) /*!< 4 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_2us (2UL) /*!< 2 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_1us (3UL) /*!< 1 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_500ns (4UL) /*!< 0.5 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_250ns (5UL) /*!< 0.25 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_125ns (6UL) /*!< 0.125 us */ /* Bit 15 : Whether to sample I/Q or magnitude/phase */ #define RADIO_DFECTRL1_SAMPLETYPE_Pos (15UL) /*!< Position of SAMPLETYPE field. */ @@ -6776,19 +6801,19 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 14..12 : Interval between samples in the REFERENCE period */ #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos (12UL) /*!< Position of TSAMPLESPACINGREF field. */ #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos) /*!< Bit mask of TSAMPLESPACINGREF field. */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (1UL) /*!< 4us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (2UL) /*!< 2us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (3UL) /*!< 1us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (4UL) /*!< 0.5us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (5UL) /*!< 0.25us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (6UL) /*!< 0.125us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (1UL) /*!< 4 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (2UL) /*!< 2 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (3UL) /*!< 1 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (4UL) /*!< 0.5 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (5UL) /*!< 0.25 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (6UL) /*!< 0.125 us */ /* Bits 10..8 : Interval between every time the antenna is changed in the SWITCHING state */ #define RADIO_DFECTRL1_TSWITCHSPACING_Pos (8UL) /*!< Position of TSWITCHSPACING field. */ #define RADIO_DFECTRL1_TSWITCHSPACING_Msk (0x7UL << RADIO_DFECTRL1_TSWITCHSPACING_Pos) /*!< Bit mask of TSWITCHSPACING field. */ -#define RADIO_DFECTRL1_TSWITCHSPACING_4us (1UL) /*!< 4us */ -#define RADIO_DFECTRL1_TSWITCHSPACING_2us (2UL) /*!< 2us */ -#define RADIO_DFECTRL1_TSWITCHSPACING_1us (3UL) /*!< 1us */ +#define RADIO_DFECTRL1_TSWITCHSPACING_4us (1UL) /*!< 4 us */ +#define RADIO_DFECTRL1_TSWITCHSPACING_2us (2UL) /*!< 2 us */ +#define RADIO_DFECTRL1_TSWITCHSPACING_1us (3UL) /*!< 1 us */ /* Bit 7 : Add CTE extension and do antenna switching/sampling in this extension */ #define RADIO_DFECTRL1_DFEINEXTENSION_Pos (7UL) /*!< Position of DFEINEXTENSION field. */ @@ -6814,7 +6839,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_SWITCHPATTERN */ /* Description: GPIO patterns to be used for each antenna */ -/* Bits 7..0 : Fill array of GPIO patterns for antenna control */ +/* Bits 7..0 : Fill array of GPIO patterns for antenna control. */ #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos (0UL) /*!< Position of SWITCHPATTERN field. */ #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Msk (0xFFUL << RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos) /*!< Bit mask of SWITCHPATTERN field. */ @@ -7233,7 +7258,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ /* Register: RTC_PRESCALER */ -/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */ +/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. */ /* Bits 11..0 : Prescaler value */ #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ @@ -7337,7 +7362,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPI_TXD */ /* Description: TXD register */ -/* Bits 7..0 : TX data to send. Double buffered */ +/* Bits 7..0 : TX data to send. Double buffered. */ #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ @@ -8037,121 +8062,121 @@ POSSIBILITY OF SUCH DAMAGE. #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ /* Register: TEMP_A0 */ -/* Description: Slope of 1st piece wise linear function */ +/* Description: Slope of first piecewise linear function */ -/* Bits 11..0 : Slope of 1st piece wise linear function */ +/* Bits 11..0 : Slope of first piecewise linear function */ #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ /* Register: TEMP_A1 */ -/* Description: Slope of 2nd piece wise linear function */ +/* Description: Slope of second piecewise linear function */ -/* Bits 11..0 : Slope of 2nd piece wise linear function */ +/* Bits 11..0 : Slope of second piecewise linear function */ #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ /* Register: TEMP_A2 */ -/* Description: Slope of 3rd piece wise linear function */ +/* Description: Slope of third piecewise linear function */ -/* Bits 11..0 : Slope of 3rd piece wise linear function */ +/* Bits 11..0 : Slope of third piecewise linear function */ #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ /* Register: TEMP_A3 */ -/* Description: Slope of 4th piece wise linear function */ +/* Description: Slope of fourth piecewise linear function */ -/* Bits 11..0 : Slope of 4th piece wise linear function */ +/* Bits 11..0 : Slope of fourth piecewise linear function */ #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ /* Register: TEMP_A4 */ -/* Description: Slope of 5th piece wise linear function */ +/* Description: Slope of fifth piecewise linear function */ -/* Bits 11..0 : Slope of 5th piece wise linear function */ +/* Bits 11..0 : Slope of fifth piecewise linear function */ #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ /* Register: TEMP_A5 */ -/* Description: Slope of 6th piece wise linear function */ +/* Description: Slope of sixth piecewise linear function */ -/* Bits 11..0 : Slope of 6th piece wise linear function */ +/* Bits 11..0 : Slope of sixth piecewise linear function */ #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ /* Register: TEMP_B0 */ -/* Description: y-intercept of 1st piece wise linear function */ +/* Description: y-intercept of first piecewise linear function */ -/* Bits 13..0 : y-intercept of 1st piece wise linear function */ +/* Bits 13..0 : y-intercept of first piecewise linear function */ #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ #define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ /* Register: TEMP_B1 */ -/* Description: y-intercept of 2nd piece wise linear function */ +/* Description: y-intercept of second piecewise linear function */ -/* Bits 13..0 : y-intercept of 2nd piece wise linear function */ +/* Bits 13..0 : y-intercept of second piecewise linear function */ #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ #define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ /* Register: TEMP_B2 */ -/* Description: y-intercept of 3rd piece wise linear function */ +/* Description: y-intercept of third piecewise linear function */ -/* Bits 13..0 : y-intercept of 3rd piece wise linear function */ +/* Bits 13..0 : y-intercept of third piecewise linear function */ #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ #define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ /* Register: TEMP_B3 */ -/* Description: y-intercept of 4th piece wise linear function */ +/* Description: y-intercept of fourth piecewise linear function */ -/* Bits 13..0 : y-intercept of 4th piece wise linear function */ +/* Bits 13..0 : y-intercept of fourth piecewise linear function */ #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ #define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ /* Register: TEMP_B4 */ -/* Description: y-intercept of 5th piece wise linear function */ +/* Description: y-intercept of fifth piecewise linear function */ -/* Bits 13..0 : y-intercept of 5th piece wise linear function */ +/* Bits 13..0 : y-intercept of fifth piecewise linear function */ #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ #define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ /* Register: TEMP_B5 */ -/* Description: y-intercept of 6th piece wise linear function */ +/* Description: y-intercept of sixth piecewise linear function */ -/* Bits 13..0 : y-intercept of 6th piece wise linear function */ +/* Bits 13..0 : y-intercept of sixth piecewise linear function */ #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ /* Register: TEMP_T0 */ -/* Description: End point of 1st piece wise linear function */ +/* Description: End point of first piecewise linear function */ -/* Bits 7..0 : End point of 1st piece wise linear function */ +/* Bits 7..0 : End point of first piecewise linear function */ #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ /* Register: TEMP_T1 */ -/* Description: End point of 2nd piece wise linear function */ +/* Description: End point of second piecewise linear function */ -/* Bits 7..0 : End point of 2nd piece wise linear function */ +/* Bits 7..0 : End point of second piecewise linear function */ #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ /* Register: TEMP_T2 */ -/* Description: End point of 3rd piece wise linear function */ +/* Description: End point of third piecewise linear function */ -/* Bits 7..0 : End point of 3rd piece wise linear function */ +/* Bits 7..0 : End point of third piecewise linear function */ #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ /* Register: TEMP_T3 */ -/* Description: End point of 4th piece wise linear function */ +/* Description: End point of fourth piecewise linear function */ -/* Bits 7..0 : End point of 4th piece wise linear function */ +/* Bits 7..0 : End point of fourth piecewise linear function */ #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ /* Register: TEMP_T4 */ -/* Description: End point of 5th piece wise linear function */ +/* Description: End point of fifth piecewise linear function */ -/* Bits 7..0 : End point of 5th piece wise linear function */ +/* Bits 7..0 : End point of fifth piecewise linear function */ #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ @@ -8769,9 +8794,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_SUSPENDED */ -/* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ +/* Description: SUSPEND task has been issued, TWI traffic is now suspended. */ -/* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ +/* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ @@ -9400,7 +9425,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_MATCH */ /* Description: Status register indicating which address had a match */ -/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ +/* Bit 0 : Indication of which address in {ADDRESS} that matched the incoming address */ #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ @@ -10273,7 +10298,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ /* Register: UARTE_ERRORSRC */ -/* Description: Error source Note : this register is read / write one to clear. */ +/* Description: Error source This register is read/write one to clear. */ /* Bit 3 : Break condition */ #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ @@ -10383,7 +10408,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */ /* Register: UARTE_RXD_PTR */ /* Description: Data pointer */ @@ -10499,7 +10524,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ -#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ +#define UICR_APPROTECT_PALL_HwDisabled (0x5AUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware and software */ +#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware */ /* Register: UICR_DEBUGCTRL */ /* Description: Processor debug control */ @@ -10511,7 +10537,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_DEBUGCTRL_CPUFPBEN_Enabled (0xFFUL) /*!< Enable CPU FPB unit (default behavior) */ /* Register: UICR_REGOUT0 */ -/* Description: Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VREG0DROP. */ +/* Description: Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD. */ /* Bits 2..0 : Output voltage from REG0 regulator stage. */ #define UICR_REGOUT0_VOUT_Pos (0UL) /*!< Position of VOUT field. */ @@ -11788,7 +11814,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 15..0 : Controls the split of ISO buffers */ #define USBD_ISOSPLIT_SPLIT_Pos (0UL) /*!< Position of SPLIT field. */ #define USBD_ISOSPLIT_SPLIT_Msk (0xFFFFUL << USBD_ISOSPLIT_SPLIT_Pos) /*!< Bit mask of SPLIT field. */ -#define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either iso IN or OUT */ +#define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either ISO IN or OUT */ #define USBD_ISOSPLIT_SPLIT_HalfIN (0x0080UL) /*!< Lower half for IN, upper half for OUT */ /* Register: USBD_FRAMECNTR */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_peripherals.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_peripherals.h index cd392e693..72c28333c 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_peripherals.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52820_peripherals.h @@ -2,6 +2,8 @@ Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. +SPDX-License-Identifier: BSD-3-Clause + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52833_to_nrf52820.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52833_to_nrf52820.h index 93f798396..a7835d1ec 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52833_to_nrf52820.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52833_to_nrf52820.h @@ -2,6 +2,8 @@ Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. +SPDX-License-Identifier: BSD-3-Clause + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_bitfields.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_bitfields.h index 035e7e451..220ada67e 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_bitfields.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_bitfields.h @@ -2,6 +2,8 @@ Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. +SPDX-License-Identifier: BSD-3-Clause + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -131,6 +133,26 @@ POSSIBILITY OF SUCH DAMAGE. #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ +/* Peripheral: APPROTECT */ +/* Description: Access Port Protection */ + +/* Register: APPROTECT_FORCEPROTECT */ +/* Description: Software force enable APPROTECT mechanism until next reset. This register can only be written once. */ + +/* Bits 7..0 : Write 0x0 to force enable APPROTECT mechanism */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (0UL) /*!< Position of FORCEPROTECT field. */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0xFFUL << APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x0UL) /*!< Software force enable APPROTECT mechanism */ + +/* Register: APPROTECT_DISABLE */ +/* Description: Software disable APPROTECT mechanism */ + +/* Bits 7..0 : Software disable APPROTECT mechanism */ +#define APPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */ +#define APPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */ +#define APPROTECT_DISABLE_DISABLE_SwDisable (0x5AUL) /*!< Software disable APPROTECT mechanism */ + + /* Peripheral: BPROT */ /* Description: Block Protect */ @@ -12467,13 +12489,14 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_PSELRESET_PIN_Msk (0x3FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ /* Register: UICR_APPROTECT */ -/* Description: Access Port protection */ +/* Description: Access port protection */ -/* Bits 7..0 : Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection. */ +/* Bits 7..0 : Enable or disable access port protection. */ #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ -#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ +#define UICR_APPROTECT_PALL_HwDisabled (0x5AUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware and software */ +#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware */ /* Register: UICR_NFCPINS */ /* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */ @@ -12481,8 +12504,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Setting of pins dedicated to NFC functionality */ #define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */ #define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */ -#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */ -#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */ +#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins. */ +#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation. */ /* Peripheral: WDT */ diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_erratas.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_erratas.h index a1d5e9100..e05d5678b 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_erratas.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_erratas.h @@ -5,6 +5,8 @@ Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. +SPDX-License-Identifier: BSD-3-Clause + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -258,6 +260,8 @@ static bool nrf52_errata_1(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -303,6 +307,8 @@ static bool nrf52_errata_2(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -348,6 +354,8 @@ static bool nrf52_errata_3(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -393,6 +401,8 @@ static bool nrf52_errata_4(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -438,6 +448,8 @@ static bool nrf52_errata_7(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -483,6 +495,8 @@ static bool nrf52_errata_8(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -528,6 +542,8 @@ static bool nrf52_errata_9(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -573,6 +589,8 @@ static bool nrf52_errata_10(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -618,6 +636,8 @@ static bool nrf52_errata_11(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -674,6 +694,8 @@ static bool nrf52_errata_12(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -740,6 +762,8 @@ static bool nrf52_errata_15(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -845,6 +869,8 @@ static bool nrf52_errata_16(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -890,6 +916,8 @@ static bool nrf52_errata_17(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -960,6 +988,8 @@ static bool nrf52_errata_20(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -979,11 +1009,11 @@ static bool nrf52_errata_20(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -1010,6 +1040,8 @@ static bool nrf52_errata_20(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -1050,6 +1082,8 @@ static bool nrf52_errata_20(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -1095,6 +1129,8 @@ static bool nrf52_errata_23(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1140,6 +1176,8 @@ static bool nrf52_errata_24(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1185,6 +1223,8 @@ static bool nrf52_errata_25(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1230,6 +1270,8 @@ static bool nrf52_errata_26(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1275,6 +1317,8 @@ static bool nrf52_errata_27(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1320,6 +1364,8 @@ static bool nrf52_errata_28(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1365,6 +1411,8 @@ static bool nrf52_errata_29(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1410,6 +1458,8 @@ static bool nrf52_errata_30(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1474,6 +1524,8 @@ static bool nrf52_errata_31(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -1557,6 +1609,8 @@ static bool nrf52_errata_32(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1602,6 +1656,8 @@ static bool nrf52_errata_33(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1647,6 +1703,8 @@ static bool nrf52_errata_34(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1692,6 +1750,8 @@ static bool nrf52_errata_35(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1762,6 +1822,8 @@ static bool nrf52_errata_36(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -1781,11 +1843,11 @@ static bool nrf52_errata_36(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -1812,6 +1874,8 @@ static bool nrf52_errata_36(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -1852,6 +1916,8 @@ static bool nrf52_errata_36(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -1897,6 +1963,8 @@ static bool nrf52_errata_37(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1942,6 +2010,8 @@ static bool nrf52_errata_38(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1987,6 +2057,8 @@ static bool nrf52_errata_39(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2032,6 +2104,8 @@ static bool nrf52_errata_40(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2077,6 +2151,8 @@ static bool nrf52_errata_41(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2122,6 +2198,8 @@ static bool nrf52_errata_42(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2167,6 +2245,8 @@ static bool nrf52_errata_43(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2212,6 +2292,8 @@ static bool nrf52_errata_44(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2257,6 +2339,8 @@ static bool nrf52_errata_46(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2302,6 +2386,8 @@ static bool nrf52_errata_47(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2347,6 +2433,8 @@ static bool nrf52_errata_48(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2392,6 +2480,8 @@ static bool nrf52_errata_49(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2448,6 +2538,8 @@ static bool nrf52_errata_51(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -2508,6 +2600,8 @@ static bool nrf52_errata_54(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -2594,6 +2688,8 @@ static bool nrf52_errata_55(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -2613,11 +2709,11 @@ static bool nrf52_errata_55(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -2630,6 +2726,8 @@ static bool nrf52_errata_55(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -2646,6 +2744,8 @@ static bool nrf52_errata_55(void) return true; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -2691,6 +2791,8 @@ static bool nrf52_errata_57(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2751,6 +2853,8 @@ static bool nrf52_errata_58(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -2818,6 +2922,8 @@ static bool nrf52_errata_62(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2863,6 +2969,8 @@ static bool nrf52_errata_63(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2919,6 +3027,8 @@ static bool nrf52_errata_64(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -2964,6 +3074,8 @@ static bool nrf52_errata_65(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -3034,6 +3146,8 @@ static bool nrf52_errata_66(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -3053,11 +3167,11 @@ static bool nrf52_errata_66(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -3084,6 +3198,8 @@ static bool nrf52_errata_66(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -3124,6 +3240,8 @@ static bool nrf52_errata_66(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -3180,6 +3298,8 @@ static bool nrf52_errata_67(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -3246,6 +3366,8 @@ static bool nrf52_errata_68(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -3351,6 +3473,8 @@ static bool nrf52_errata_70(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -3396,6 +3520,8 @@ static bool nrf52_errata_71(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -3452,6 +3578,8 @@ static bool nrf52_errata_72(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -3497,6 +3625,8 @@ static bool nrf52_errata_73(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -3553,6 +3683,8 @@ static bool nrf52_errata_74(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -3609,6 +3741,8 @@ static bool nrf52_errata_75(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -3665,6 +3799,8 @@ static bool nrf52_errata_76(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -3729,6 +3865,8 @@ static bool nrf52_errata_77(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -3837,6 +3975,8 @@ static bool nrf52_errata_78(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -3856,11 +3996,11 @@ static bool nrf52_errata_78(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -3887,6 +4027,8 @@ static bool nrf52_errata_78(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -3927,6 +4069,8 @@ static bool nrf52_errata_78(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -3983,6 +4127,8 @@ static bool nrf52_errata_79(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -4049,6 +4195,8 @@ static bool nrf52_errata_81(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -4068,11 +4216,11 @@ static bool nrf52_errata_81(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -4175,6 +4323,8 @@ static bool nrf52_errata_83(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -4291,6 +4441,8 @@ static bool nrf52_errata_84(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -4347,6 +4499,8 @@ static bool nrf52_errata_86(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -4411,6 +4565,8 @@ static bool nrf52_errata_87(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -4430,11 +4586,11 @@ static bool nrf52_errata_87(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -4447,6 +4603,8 @@ static bool nrf52_errata_87(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -4463,6 +4621,8 @@ static bool nrf52_errata_87(void) return true; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -4527,6 +4687,8 @@ static bool nrf52_errata_88(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -4625,6 +4787,8 @@ static bool nrf52_errata_89(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -4703,8 +4867,10 @@ static bool nrf52_errata_91(void) return true; case 0x06ul: return true; + case 0x07ul: + return false; default: - return true; + return false; } } #endif @@ -4855,6 +5021,8 @@ static bool nrf52_errata_97(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -4979,6 +5147,8 @@ static bool nrf52_errata_101(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -5035,6 +5205,8 @@ static bool nrf52_errata_102(void) return true; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -5183,6 +5355,8 @@ static bool nrf52_errata_106(void) return true; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -5239,6 +5413,8 @@ static bool nrf52_errata_107(void) return true; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -5295,6 +5471,8 @@ static bool nrf52_errata_108(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -5351,6 +5529,8 @@ static bool nrf52_errata_109(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -5549,6 +5729,8 @@ static bool nrf52_errata_113(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -5936,11 +6118,11 @@ static bool nrf52_errata_122(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -6133,6 +6315,8 @@ static bool nrf52_errata_132(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -6341,6 +6525,8 @@ static bool nrf52_errata_136(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -6360,11 +6546,11 @@ static bool nrf52_errata_136(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -6391,6 +6577,8 @@ static bool nrf52_errata_136(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -6431,6 +6619,8 @@ static bool nrf52_errata_136(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -6487,6 +6677,8 @@ static bool nrf52_errata_138(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -6589,6 +6781,8 @@ static bool nrf52_errata_141(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -6695,6 +6889,8 @@ static bool nrf52_errata_143(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -6865,6 +7061,8 @@ static bool nrf52_errata_146(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -6967,6 +7165,8 @@ static bool nrf52_errata_149(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -7029,6 +7229,8 @@ static bool nrf52_errata_150(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -7121,7 +7323,9 @@ static bool nrf52_errata_151(void) } /* ========= Errata 153 ========= */ -#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) #define NRF52_ERRATA_153_PRESENT 1 #else #define NRF52_ERRATA_153_PRESENT 0 @@ -7136,7 +7340,9 @@ static bool nrf52_errata_153(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) uint32_t var1 = *(uint32_t *)0x10000130ul; uint32_t var2 = *(uint32_t *)0x10000134ul; #endif @@ -7154,11 +7360,37 @@ static bool nrf52_errata_153(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: return false; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; } } #endif @@ -7269,6 +7501,8 @@ static bool nrf52_errata_155(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -7288,11 +7522,11 @@ static bool nrf52_errata_155(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -7395,6 +7629,8 @@ static bool nrf52_errata_156(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -7649,6 +7885,8 @@ static bool nrf52_errata_163(void) return true; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -7738,11 +7976,11 @@ static bool nrf52_errata_166(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -7788,11 +8026,11 @@ static bool nrf52_errata_170(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -7805,6 +8043,8 @@ static bool nrf52_errata_170(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -7821,6 +8061,8 @@ static bool nrf52_errata_170(void) return true; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -7864,11 +8106,11 @@ static bool nrf52_errata_171(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -7910,11 +8152,11 @@ static bool nrf52_errata_172(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -7983,6 +8225,8 @@ static bool nrf52_errata_173(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -8002,11 +8246,11 @@ static bool nrf52_errata_173(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -8033,6 +8277,8 @@ static bool nrf52_errata_173(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -8073,7 +8319,9 @@ static bool nrf52_errata_173(void) return true; case 0x02ul: return true; - default: + case 0x03ul: + return true; + default: return true; } } @@ -8116,11 +8364,11 @@ static bool nrf52_errata_174(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -8189,6 +8437,8 @@ static bool nrf52_errata_176(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -8208,11 +8458,11 @@ static bool nrf52_errata_176(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -8239,6 +8489,8 @@ static bool nrf52_errata_176(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -8279,6 +8531,8 @@ static bool nrf52_errata_176(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -8335,6 +8589,8 @@ static bool nrf52_errata_178(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -8401,6 +8657,8 @@ static bool nrf52_errata_179(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -8420,11 +8678,11 @@ static bool nrf52_errata_179(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -8567,6 +8825,8 @@ static bool nrf52_errata_181(void) return true; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -8634,6 +8894,8 @@ static bool nrf52_errata_182(void) return false; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -8702,6 +8964,8 @@ static bool nrf52_errata_183(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -8721,11 +8985,11 @@ static bool nrf52_errata_183(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -8752,6 +9016,8 @@ static bool nrf52_errata_183(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -8780,6 +9046,8 @@ static bool nrf52_errata_183(void) return true; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -8833,11 +9101,11 @@ static bool nrf52_errata_184(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -8864,6 +9132,8 @@ static bool nrf52_errata_184(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -8904,6 +9174,8 @@ static bool nrf52_errata_184(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -8997,11 +9269,11 @@ static bool nrf52_errata_187(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -9014,6 +9286,8 @@ static bool nrf52_errata_187(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -9030,6 +9304,8 @@ static bool nrf52_errata_187(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -9123,11 +9399,11 @@ static bool nrf52_errata_190(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -9140,6 +9416,8 @@ static bool nrf52_errata_190(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -9156,6 +9434,8 @@ static bool nrf52_errata_190(void) return true; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -9199,11 +9479,11 @@ static bool nrf52_errata_191(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -9264,6 +9544,8 @@ static bool nrf52_errata_192(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -9343,11 +9625,11 @@ static bool nrf52_errata_193(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -9410,6 +9692,8 @@ static bool nrf52_errata_194(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -9429,11 +9713,11 @@ static bool nrf52_errata_194(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -9446,6 +9730,8 @@ static bool nrf52_errata_194(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -9462,6 +9748,8 @@ static bool nrf52_errata_194(void) return true; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -9505,11 +9793,11 @@ static bool nrf52_errata_195(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -9572,6 +9860,8 @@ static bool nrf52_errata_196(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -9591,11 +9881,11 @@ static bool nrf52_errata_196(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -9608,6 +9898,8 @@ static bool nrf52_errata_196(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -9624,6 +9916,8 @@ static bool nrf52_errata_196(void) return true; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -9713,11 +10007,11 @@ static bool nrf52_errata_198(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -9759,11 +10053,11 @@ static bool nrf52_errata_199(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -9870,6 +10164,8 @@ static bool nrf52_errata_201(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -10014,6 +10310,8 @@ static bool nrf52_errata_204(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -10033,11 +10331,11 @@ static bool nrf52_errata_204(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10093,11 +10391,11 @@ static bool nrf52_errata_208(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10139,11 +10437,11 @@ static bool nrf52_errata_209(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10212,6 +10510,8 @@ static bool nrf52_errata_210(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -10231,11 +10531,11 @@ static bool nrf52_errata_210(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10262,6 +10562,8 @@ static bool nrf52_errata_210(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -10302,6 +10604,8 @@ static bool nrf52_errata_210(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -10349,11 +10653,11 @@ static bool nrf52_errata_211(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10366,6 +10670,8 @@ static bool nrf52_errata_211(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -10382,6 +10688,8 @@ static bool nrf52_errata_211(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -10452,6 +10760,8 @@ static bool nrf52_errata_212(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -10471,11 +10781,11 @@ static bool nrf52_errata_212(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10502,6 +10812,8 @@ static bool nrf52_errata_212(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -10542,6 +10854,8 @@ static bool nrf52_errata_212(void) return true; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -10606,6 +10920,8 @@ static bool nrf52_errata_213(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -10625,11 +10941,11 @@ static bool nrf52_errata_213(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10697,11 +11013,11 @@ static bool nrf52_errata_214(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10743,11 +11059,11 @@ static bool nrf52_errata_215(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10789,11 +11105,11 @@ static bool nrf52_errata_216(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10922,6 +11238,8 @@ static bool nrf52_errata_218(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -10941,11 +11259,11 @@ static bool nrf52_errata_218(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10958,6 +11276,8 @@ static bool nrf52_errata_218(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -10974,6 +11294,8 @@ static bool nrf52_errata_218(void) return true; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -11044,6 +11366,8 @@ static bool nrf52_errata_219(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -11063,11 +11387,11 @@ static bool nrf52_errata_219(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -11094,6 +11418,8 @@ static bool nrf52_errata_219(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -11134,6 +11460,8 @@ static bool nrf52_errata_219(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -11190,6 +11518,8 @@ static bool nrf52_errata_220(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -11230,6 +11560,8 @@ static bool nrf52_errata_223(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -11246,6 +11578,8 @@ static bool nrf52_errata_223(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -11286,6 +11620,8 @@ static bool nrf52_errata_225(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -11302,6 +11638,8 @@ static bool nrf52_errata_225(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -11353,11 +11691,11 @@ static bool nrf52_errata_228(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -11384,6 +11722,8 @@ static bool nrf52_errata_228(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -11412,6 +11752,8 @@ static bool nrf52_errata_228(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -11452,6 +11794,8 @@ static bool nrf52_errata_230(void) return false; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -11492,6 +11836,8 @@ static bool nrf52_errata_231(void) return false; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -11591,11 +11937,11 @@ static bool nrf52_errata_233(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -11608,6 +11954,8 @@ static bool nrf52_errata_233(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -11624,6 +11972,8 @@ static bool nrf52_errata_233(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -11675,11 +12025,11 @@ static bool nrf52_errata_236(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -11706,6 +12056,8 @@ static bool nrf52_errata_236(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -11734,6 +12086,8 @@ static bool nrf52_errata_236(void) return true; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -11785,11 +12139,11 @@ static bool nrf52_errata_237(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -11816,6 +12170,8 @@ static bool nrf52_errata_237(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -11844,6 +12200,8 @@ static bool nrf52_errata_237(void) return true; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -11998,6 +12356,8 @@ static bool nrf52_errata_243(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -12014,6 +12374,8 @@ static bool nrf52_errata_243(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -12130,6 +12492,8 @@ static bool nrf52_errata_245(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -12180,6 +12544,8 @@ static bool nrf52_errata_245(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -12220,6 +12586,8 @@ static bool nrf52_errata_245(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -12304,6 +12672,8 @@ static bool nrf52_errata_246(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -12344,6 +12714,8 @@ static bool nrf52_errata_246(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -12426,6 +12798,8 @@ static bool nrf52_errata_248(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -12454,6 +12828,8 @@ static bool nrf52_errata_248(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -12464,7 +12840,11 @@ static bool nrf52_errata_248(void) } /* ========= Errata 249 ========= */ -#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) #define NRF52_ERRATA_249_PRESENT 1 #else #define NRF52_ERRATA_249_PRESENT 0 @@ -12479,10 +12859,35 @@ static bool nrf52_errata_249(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) uint32_t var1 = *(uint32_t *)0x10000130ul; uint32_t var2 = *(uint32_t *)0x10000134ul; #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) if (var1 == 0x08) { @@ -12505,6 +12910,40 @@ static bool nrf52_errata_249(void) } } #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return true; + default: + return true; + } + } + #endif return false; #endif } @@ -12540,6 +12979,8 @@ static bool nrf52_errata_250(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -12556,6 +12997,8 @@ static bool nrf52_errata_250(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_name_change.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_name_change.h index 004d8e2fe..6b1d66648 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_name_change.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_name_change.h @@ -2,6 +2,8 @@ Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. +SPDX-License-Identifier: BSD-3-Clause + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52810.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52810.h index c6bdecabe..1b3e43115 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52810.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52810.h @@ -2,6 +2,8 @@ Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. +SPDX-License-Identifier: BSD-3-Clause + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52833.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52833.h index 4c3643636..15944c34a 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52833.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52833.h @@ -2,6 +2,8 @@ Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. +SPDX-License-Identifier: BSD-3-Clause + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52840.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52840.h index d65a26a7f..01bf9e535 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52840.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_to_nrf52840.h @@ -2,6 +2,8 @@ Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. +SPDX-License-Identifier: BSD-3-Clause + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf53_erratas.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf53_erratas.h index 79d834d46..4efda5778 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf53_erratas.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf53_erratas.h @@ -5,6 +5,8 @@ Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. +SPDX-License-Identifier: BSD-3-Clause + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf91_erratas.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf91_erratas.h index 074b126c9..b58d58e08 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf91_erratas.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf91_erratas.h @@ -5,6 +5,8 @@ Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. +SPDX-License-Identifier: BSD-3-Clause + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf_erratas.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf_erratas.h index 83f4bcf89..bcf4026bd 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf_erratas.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf_erratas.h @@ -2,6 +2,8 @@ Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. +SPDX-License-Identifier: BSD-3-Clause + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52.c b/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52.c index 9ae86795d..c86045fa4 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52.c +++ b/source/hic_hal/nordic/nrf52820/cmsis/system_nrf52.c @@ -29,6 +29,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #include "nrf_peripherals.h" #include "nrf_erratas.h" #include "system_nrf52.h" +#include "system_nrf52_approtect.h" #define __SYSTEM_CLOCK_64M (64000000UL) @@ -268,6 +269,8 @@ void SystemInit(void) __ISB(); #endif + nrf52_handle_approtect(); + /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as normal GPIOs. */ @@ -301,11 +304,9 @@ void SystemInit(void) make sure NFC pins are mapped as GPIO. */ #if defined (DEVELOP_IN_NRF52832) && defined(NRF52810_XXAA) \ || defined (DEVELOP_IN_NRF52840) && defined(NRF52811_XXAA) - if (((*((uint32_t *)0x10001200) & (1 << 0)) != 0) || ((*((uint32_t *)0x10001204) & (1 << 0)) != 0)){ + if ((*((uint32_t *)0x1000120C) & (1 << 0)) != 0){ nvmc_config(NVMC_CONFIG_WEN_Wen); - *((uint32_t *)0x10001200) = 0; - nvmc_wait(); - *((uint32_t *)0x10001204) = 0; + *((uint32_t *)0x1000120C) = 0; nvmc_wait(); nvmc_config(NVMC_CONFIG_WEN_Ren); NVIC_SystemReset(); diff --git a/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_common.h b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_common.h index 58ea22180..b6d86ca3c 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_common.h +++ b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_common.h @@ -1,41 +1,34 @@ -/** - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA - * +/* + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_COMMON_H__ @@ -52,6 +45,22 @@ extern "C" { #endif +#ifndef NRFX_STATIC_INLINE +#ifdef NRFX_DECLARE_ONLY +#define NRFX_STATIC_INLINE +#else +#define NRFX_STATIC_INLINE __STATIC_INLINE +#endif +#endif // NRFX_STATIC_INLINE + +#ifndef NRF_STATIC_INLINE +#ifdef NRF_DECLARE_ONLY +#define NRF_STATIC_INLINE +#else +#define NRF_STATIC_INLINE __STATIC_INLINE +#endif +#endif // NRF_STATIC_INLINE + /** * @defgroup nrfx_common Common module * @{ @@ -244,7 +253,7 @@ typedef enum * @retval true The pointed object is located in the Data RAM region. * @retval false The pointed object is not located in the Data RAM region. */ -__STATIC_INLINE bool nrfx_is_in_ram(void const * p_object); +NRF_STATIC_INLINE bool nrfx_is_in_ram(void const * p_object); /** * @brief Function for checking if an object is aligned to a 32-bit word @@ -258,7 +267,7 @@ __STATIC_INLINE bool nrfx_is_in_ram(void const * p_object); * @retval true The pointed object is aligned to a 32-bit word. * @retval false The pointed object is not aligned to a 32-bit word. */ -__STATIC_INLINE bool nrfx_is_word_aligned(void const * p_object); +NRF_STATIC_INLINE bool nrfx_is_word_aligned(void const * p_object); /** * @brief Function for getting the interrupt number for the specified peripheral. @@ -267,7 +276,7 @@ __STATIC_INLINE bool nrfx_is_word_aligned(void const * p_object); * * @return Interrupt number associated with the pointed peripheral. */ -__STATIC_INLINE IRQn_Type nrfx_get_irq_number(void const * p_reg); +NRF_STATIC_INLINE IRQn_Type nrfx_get_irq_number(void const * p_reg); /** * @brief Function for converting an INTEN register bit position to the @@ -283,7 +292,7 @@ __STATIC_INLINE IRQn_Type nrfx_get_irq_number(void const * p_reg); * * @sa nrfx_event_to_bitpos */ -__STATIC_INLINE uint32_t nrfx_bitpos_to_event(uint32_t bit); +NRF_STATIC_INLINE uint32_t nrfx_bitpos_to_event(uint32_t bit); /** * @brief Function for converting an event identifier to the corresponding @@ -299,39 +308,39 @@ __STATIC_INLINE uint32_t nrfx_bitpos_to_event(uint32_t bit); * * @sa nrfx_bitpos_to_event */ -__STATIC_INLINE uint32_t nrfx_event_to_bitpos(uint32_t event); +NRF_STATIC_INLINE uint32_t nrfx_event_to_bitpos(uint32_t event); -#ifndef SUPPRESS_INLINE_IMPLEMENTATION +#ifndef NRF_DECLARE_ONLY -__STATIC_INLINE bool nrfx_is_in_ram(void const * p_object) +NRF_STATIC_INLINE bool nrfx_is_in_ram(void const * p_object) { return ((((uint32_t)p_object) & 0xE0000000u) == 0x20000000u); } -__STATIC_INLINE bool nrfx_is_word_aligned(void const * p_object) +NRF_STATIC_INLINE bool nrfx_is_word_aligned(void const * p_object) { return ((((uint32_t)p_object) & 0x3u) == 0u); } -__STATIC_INLINE IRQn_Type nrfx_get_irq_number(void const * p_reg) +NRF_STATIC_INLINE IRQn_Type nrfx_get_irq_number(void const * p_reg) { return (IRQn_Type)NRFX_IRQ_NUMBER_GET(p_reg); } -__STATIC_INLINE uint32_t nrfx_bitpos_to_event(uint32_t bit) +NRF_STATIC_INLINE uint32_t nrfx_bitpos_to_event(uint32_t bit) { static const uint32_t event_reg_offset = 0x100u; return event_reg_offset + (bit * sizeof(uint32_t)); } -__STATIC_INLINE uint32_t nrfx_event_to_bitpos(uint32_t event) +NRF_STATIC_INLINE uint32_t nrfx_event_to_bitpos(uint32_t event) { static const uint32_t event_reg_offset = 0x100u; return (event - event_reg_offset) / sizeof(uint32_t); } -#endif +#endif // NRF_DECLARE_ONLY /** @} */ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_errors.h b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_errors.h index 012af9c4f..26f3f4a20 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_errors.h +++ b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_errors.h @@ -1,41 +1,34 @@ -/** - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA - * +/* + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_ERRORS_H__ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/drivers/prs/nrfx_prs.h b/source/hic_hal/nordic/nrf52820/nrfx/drivers/prs/nrfx_prs.h index 7759c7e0a..47ab8909f 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/drivers/prs/nrfx_prs.h +++ b/source/hic_hal/nordic/nrf52820/nrfx/drivers/prs/nrfx_prs.h @@ -1,41 +1,34 @@ -/** - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA - * +/* + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_PRS_H__ @@ -60,7 +53,7 @@ extern "C" { #define NRFX_PRS_BOX_0_ADDR NRF_SPI0 // SPI1, SPIS1, TWI1 #define NRFX_PRS_BOX_1_ADDR NRF_SPI1 -#elif defined(NRF52810_XXAA) +#elif defined(NRF52805_XXAA) || defined(NRF52810_XXAA) // TWIM0, TWIS0, TWI0 #define NRFX_PRS_BOX_0_ADDR NRF_TWIM0 // SPIM0, SPIS0, SPI0 @@ -93,6 +86,20 @@ extern "C" { #define NRFX_PRS_BOX_3_ADDR NRF_COMP // UARTE0, UART0 #define NRFX_PRS_BOX_4_ADDR NRF_UARTE0 +#elif defined(NRF5340_XXAA_APPLICATION) + // SPIM0, SPIS0, TWIM0, TWIS0, UARTE0 + #define NRFX_PRS_BOX_0_ADDR NRF_UARTE0 + // SPIM1, SPIS1, TWIM1, TWIS1, UARTE1 + #define NRFX_PRS_BOX_1_ADDR NRF_UARTE1 + // SPIM2, SPIS2, TWIM2, TWIS2, UARTE2 + #define NRFX_PRS_BOX_2_ADDR NRF_UARTE2 + // SPIM3, SPIS3, TWIM3, TWIS3, UARTE3 + #define NRFX_PRS_BOX_3_ADDR NRF_UARTE3 + // COMP, LPCOMP + #define NRFX_PRS_BOX_4_ADDR NRF_COMP +#elif defined(NRF5340_XXAA_NETWORK) + // SPIM0, SPIS0, TWIM0, TWIS0, UARTE0 + #define NRFX_PRS_BOX_0_ADDR NRF_UARTE0 #elif defined(NRF9160_XXAA) // UARTE0, SPIM0, SPIS0, TWIM0, TWIS0 #define NRFX_PRS_BOX_0_ADDR NRF_UARTE0 diff --git a/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_common.h b/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_common.h new file mode 100644 index 000000000..7f0dd3d77 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_common.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2020 - 2021, Nordic Semiconductor ASA + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_COMMON_H__ +#define NRF_COMMON_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef NRFX_EVENT_READBACK_ENABLED +#define NRFX_EVENT_READBACK_ENABLED 1 +#endif + +#ifndef NRF_DECLARE_ONLY + +NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg) +{ +#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51) + (void)*((volatile uint32_t *)(p_event_reg)); +#else + (void)p_event_reg; +#endif +} + +#endif // NRF_DECLARE_ONLY + +#ifdef __cplusplus +} +#endif + +#endif // NRF_COMMON_H__ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_gpio.h b/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_gpio.h index 7811eeb4c..0364b6da4 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_gpio.h +++ b/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_gpio.h @@ -1,41 +1,34 @@ -/** - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA - * +/* + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_GPIO_H__ @@ -109,14 +102,35 @@ typedef enum /** @brief Enumerator used for selecting output drive mode. */ typedef enum { - NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< !< Standard '0', standard '1'. - NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< !< High-drive '0', standard '1'. - NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< !< Standard '0', high-drive '1'. - NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< !< High drive '0', high-drive '1'. - NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< !< Disconnect '0' standard '1'. - NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< !< Disconnect '0', high-drive '1'. - NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< !< Standard '0', disconnect '1'. - NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< !< High-drive '0', disconnect '1'. + NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< Standard '0', standard '1'. + NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< High drive '0', standard '1'. + NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< Standard '0', high drive '1'. + NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< High drive '0', high drive '1'. + NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< Disconnect '0' standard '1'. + NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< Disconnect '0', high drive '1'. + NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< Standard '0', disconnect '1'. + NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< High drive '0', disconnect '1'. +#if defined(GPIO_PIN_CNF_DRIVE_E0S1) || defined(__NRFX_DOXYGEN__) + NRF_GPIO_PIN_E0S1 = GPIO_PIN_CNF_DRIVE_E0S1, ///< Extra high drive '0', standard '1'. +#endif +#if defined(GPIO_PIN_CNF_DRIVE_S0E1) || defined(__NRFX_DOXYGEN__) + NRF_GPIO_PIN_S0E1 = GPIO_PIN_CNF_DRIVE_S0E1, ///< Standard '0', extra high drive '1'. +#endif +#if defined(GPIO_PIN_CNF_DRIVE_E0E1) || defined(__NRFX_DOXYGEN__) + NRF_GPIO_PIN_E0E1 = GPIO_PIN_CNF_DRIVE_E0E1, ///< Extra high drive '0', extra high drive '1'. +#endif +#if defined(GPIO_PIN_CNF_DRIVE_E0H1) || defined(__NRFX_DOXYGEN__) + NRF_GPIO_PIN_E0H1 = GPIO_PIN_CNF_DRIVE_E0H1, ///< Extra high drive '0', high drive '1'. +#endif +#if defined(GPIO_PIN_CNF_DRIVE_H0E1) || defined(__NRFX_DOXYGEN__) + NRF_GPIO_PIN_H0E1 = GPIO_PIN_CNF_DRIVE_H0E1, ///< High drive '0', extra high drive '1'. +#endif +#if defined(GPIO_PIN_CNF_DRIVE_D0E1) || defined(__NRFX_DOXYGEN__) + NRF_GPIO_PIN_D0E1 = GPIO_PIN_CNF_DRIVE_D0E1, ///< Disconnect '0', extra high drive '1'. +#endif +#if defined(GPIO_PIN_CNF_DRIVE_E0D1) || defined(__NRFX_DOXYGEN__) + NRF_GPIO_PIN_E0D1 = GPIO_PIN_CNF_DRIVE_E0D1, ///< Extra high drive '0', disconnect '1'. +#endif } nrf_gpio_pin_drive_t; /** @brief Enumerator used for selecting the pin to sense high or low level on the pin input. */ @@ -127,6 +141,16 @@ typedef enum NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High, ///< Pin sense high level. } nrf_gpio_pin_sense_t; +#if defined(GPIO_PIN_CNF_MCUSEL_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Enumerator used for selecting the MCU/Subsystem to control the specified pin. */ +typedef enum +{ + NRF_GPIO_PIN_MCUSEL_APP = GPIO_PIN_CNF_MCUSEL_AppMCU, ///< Pin controlled by Application MCU. + NRF_GPIO_PIN_MCUSEL_NETWORK = GPIO_PIN_CNF_MCUSEL_NetworkMCU, ///< Pin controlled by Network MCU. + NRF_GPIO_PIN_MCUSEL_PERIPHERAL = GPIO_PIN_CNF_MCUSEL_Peripheral, ///< Pin controlled by dedicated peripheral. + NRF_GPIO_PIN_MCUSEL_TND = GPIO_PIN_CNF_MCUSEL_TND, ///< Pin controlled by Trace and Debug Subsystem. +} nrf_gpio_pin_mcusel_t; +#endif /** * @brief Function for configuring the GPIO pin range as output pins with normal drive strength. @@ -138,7 +162,7 @@ typedef enum * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). */ -__STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end); +NRF_STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end); /** * @brief Function for configuring the GPIO pin range as input pins with given initial value set, hiding inner details. @@ -151,9 +175,9 @@ __STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_ * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high). */ -__STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, - uint32_t pin_range_end, - nrf_gpio_pin_pull_t pull_config); +NRF_STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, + uint32_t pin_range_end, + nrf_gpio_pin_pull_t pull_config); /** * @brief Pin configuration function. @@ -168,7 +192,7 @@ __STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_star * @param drive Drive configuration. * @param sense Pin sensing mechanism. */ -__STATIC_INLINE void nrf_gpio_cfg( +NRF_STATIC_INLINE void nrf_gpio_cfg( uint32_t pin_number, nrf_gpio_pin_dir_t dir, nrf_gpio_pin_input_t input, @@ -184,7 +208,7 @@ __STATIC_INLINE void nrf_gpio_cfg( * * @param pin_number Specifies the pin number. */ -__STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number); +NRF_STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number); /** * @brief Function for configuring the given GPIO pin number as input, hiding inner details. @@ -195,14 +219,14 @@ __STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number); * @param pin_number Specifies the pin number. * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high). */ -__STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config); +NRF_STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config); /** * @brief Function for resetting pin configuration to its default state. * * @param pin_number Specifies the pin number. */ -__STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number); +NRF_STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number); /** * @brief Function for configuring the given GPIO pin number as a watcher. Only input is connected. @@ -210,14 +234,14 @@ __STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number); * @param pin_number Specifies the pin number. * */ -__STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number); +NRF_STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number); /** * @brief Function for disconnecting input for the given GPIO. * * @param pin_number Specifies the pin number. */ -__STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number); +NRF_STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number); /** * @brief Function for configuring the given GPIO pin number as input, hiding inner details. @@ -228,9 +252,9 @@ __STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number); * @param pull_config State of the pin pull resistor (no pull, pulled down, or pulled high). * @param sense_config Sense level of the pin (no sense, sense low, or sense high). */ -__STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, - nrf_gpio_pin_pull_t pull_config, - nrf_gpio_pin_sense_t sense_config); +NRF_STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, + nrf_gpio_pin_pull_t pull_config, + nrf_gpio_pin_sense_t sense_config); /** * @brief Function for configuring sense level for the given GPIO. @@ -238,7 +262,8 @@ __STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, * @param pin_number Specifies the pin number. * @param sense_config Sense configuration. */ -__STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config); +NRF_STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, + nrf_gpio_pin_sense_t sense_config); /** * @brief Function for setting the direction for a GPIO pin. @@ -246,46 +271,38 @@ __STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_se * @param pin_number Specifies the pin number for which to set the direction. * @param direction Specifies the direction. */ -__STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction); +NRF_STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction); /** * @brief Function for setting a GPIO pin. * - * For this function to have any effect, the pin must be configured as an output. - * * @param pin_number Specifies the pin number to be set. */ -__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number); +NRF_STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number); /** * @brief Function for clearing a GPIO pin. * - * For this function to have any effect, the pin must be configured as an output. - * * @param pin_number Specifies the pin number to clear. */ -__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number); +NRF_STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number); /** * @brief Function for toggling a GPIO pin. * - * For this function to have any effect, the pin must be configured as an output. - * * @param pin_number Specifies the pin number to toggle. */ -__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number); +NRF_STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number); /** * @brief Function for writing a value to a GPIO pin. * - * For this function to have any effect, the pin must be configured as an output. - * * @param pin_number Specifies the pin number to write. * @param value Specifies the value to be written to the pin. * @arg 0 Clears the pin. * @arg >=1 Sets the pin. */ -__STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value); +NRF_STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value); /** * @brief Function for reading the input level of a GPIO pin. @@ -296,7 +313,7 @@ __STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value); * * @return 0 if the pin input level is low. Positive value if the pin is high. */ -__STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number); +NRF_STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number); /** * @brief Function for reading the output level of a GPIO pin. @@ -305,7 +322,7 @@ __STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number); * * @return 0 if the pin output level is low. Positive value if pin output is high. */ -__STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number); +NRF_STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number); /** * @brief Function for reading the sense configuration of a GPIO pin. @@ -314,7 +331,7 @@ __STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number); * * @return Sense configuration. */ -__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number); +NRF_STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number); /** * @brief Function for reading the direction configuration of a GPIO pin. @@ -323,7 +340,7 @@ __STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number) * * @return Direction configuration. */ -__STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number); +NRF_STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number); /** * @brief Function for reading the status of GPIO pin input buffer. @@ -332,7 +349,7 @@ __STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number); * * @retval Input buffer configuration. */ -__STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number); +NRF_STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number); /** * @brief Function for reading the pull configuration of a GPIO pin. @@ -341,7 +358,7 @@ __STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number) * * @retval Pull configuration. */ -__STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number); +NRF_STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number); /** * @brief Function for setting output direction on the selected pins on the given port. @@ -349,7 +366,7 @@ __STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number); * @param p_reg Pointer to the structure of registers of the peripheral. * @param out_mask Mask specifying the pins to set as output. */ -__STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask); +NRF_STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask); /** * @brief Function for setting input direction on selected pins on a given port. @@ -357,7 +374,7 @@ __STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_ * @param p_reg Pointer to the structure of registers of the peripheral. * @param in_mask Mask that specifies the pins to be set as input. */ -__STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask); +NRF_STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask); /** * @brief Function for writing the direction configuration of the GPIO pins in the given port. @@ -365,7 +382,7 @@ __STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t * @param p_reg Pointer to the structure of registers of the peripheral. * @param dir_mask Mask that specifies the direction of pins. Bit set means that the given pin is configured as output. */ -__STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t dir_mask); +NRF_STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t dir_mask); /** * @brief Function for reading the direction configuration of a GPIO port. @@ -374,7 +391,7 @@ __STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t dir * * @return Pin configuration of the current direction settings. Bit set means that the given pin is configured as output. */ -__STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg); +NRF_STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg); /** * @brief Function for reading the input signals of the GPIO pins on the given port. @@ -383,7 +400,7 @@ __STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg); * * @return Port input values. */ -__STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg); +NRF_STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg); /** * @brief Function for reading the output signals of the GPIO pins on the given port. @@ -392,7 +409,7 @@ __STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg); * * @return Port output values. */ -__STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg); +NRF_STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg); /** * @brief Function for writing the GPIO pins output on a given port. @@ -400,7 +417,7 @@ __STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg); * @param p_reg Pointer to the structure of registers of the peripheral. * @param value Output port mask. */ -__STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value); +NRF_STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value); /** * @brief Function for setting high level on selected the GPIO pins on the given port. @@ -408,7 +425,7 @@ __STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t val * @param p_reg Pointer to the structure of registers of the peripheral. * @param set_mask Mask with pins to be set as logical high level. */ -__STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask); +NRF_STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask); /** * @brief Function for setting low level on selected the GPIO pins on the given port. @@ -416,7 +433,7 @@ __STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_m * @param p_reg Pointer to the structure of registers of the peripheral. * @param clr_mask Mask with pins to be set as logical low level. */ -__STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask); +NRF_STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask); /** * @brief Function for reading pin state of multiple consecutive ports. @@ -425,7 +442,9 @@ __STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr * @param length Number of ports to read. * @param p_masks Pointer to output array where port states will be stored. */ -__STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, uint32_t * p_masks); +NRF_STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, + uint32_t length, + uint32_t * p_masks); #if defined(NRF_GPIO_LATCH_PRESENT) /** @@ -435,9 +454,9 @@ __STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, u * @param length Number of ports to read. * @param p_masks Pointer to output array where latch states will be stored. */ -__STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, - uint32_t length, - uint32_t * p_masks); +NRF_STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, + uint32_t length, + uint32_t * p_masks); /** * @brief Function for reading and immediate clearing latch state of multiple consecutive ports. @@ -446,9 +465,9 @@ __STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, * @param length Number of ports to read and clear. * @param p_masks Pointer to output array where latch states will be stored. */ -__STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port, - uint32_t length, - uint32_t * p_masks); +NRF_STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port, + uint32_t length, + uint32_t * p_masks); /** * @brief Function for reading latch state of single pin. @@ -457,16 +476,26 @@ __STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port, * * @return 0 if latch is not set. Positive value otherwise. */ -__STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number); +NRF_STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number); /** * @brief Function for clearing latch state of a single pin. * * @param pin_number Pin number. */ -__STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number); +NRF_STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number); #endif // defined(NRF_GPIO_LATCH_PRESENT) +#if defined(GPIO_PIN_CNF_MCUSEL_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for selecting the MCU to control a GPIO pin. + * + * @param pin_number Pin_number. + * @param mcu MCU to control the pin. + */ +NRF_STATIC_INLINE void nrf_gpio_pin_mcu_select(uint32_t pin_number, nrf_gpio_pin_mcusel_t mcu); +#endif + /** * @brief Function for checking if provided pin is present on the MCU. * @@ -475,40 +504,51 @@ __STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number); * @retval true Pin is present. * @retval false Pin is not present. */ -__STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number); +NRF_STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number); +/** + * @brief Function for extracting port number and the relative pin number + * from the absolute pin number. + * + * @param[in,out] p_pin Pointer to the absolute pin number overridden by the pin number + * that is relative to the port. + * + * @return Port number. +*/ +NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin); -#ifndef SUPPRESS_INLINE_IMPLEMENTATION +#ifndef NRF_DECLARE_ONLY /** * @brief Function for extracting port and the relative pin number from the absolute pin number. * - * @param[in,out] p_pin Pointer to the absolute pin number overriden by the pin number that is relative to the port. + * @param[in,out] p_pin Pointer to the absolute pin number overridden by the pin number + * that is relative to the port. * * @return Pointer to port register set. */ -__STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin) +NRF_STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin) { NRFX_ASSERT(nrf_gpio_pin_present_check(*p_pin)); -#if (GPIO_COUNT == 1) - return NRF_P0; -#else - if (*p_pin < P0_PIN_NUM) - { - return NRF_P0; - } - else + + switch (nrf_gpio_pin_port_number_extract(p_pin)) { - *p_pin = *p_pin & 0x1F; - return NRF_P1; - } + default: + NRFX_ASSERT(0); +#if defined(P0_FEATURE_PINS_PRESENT) + /* FALLTHROUGH */ + case 0: return NRF_P0; #endif +#if defined(P1_FEATURE_PINS_PRESENT) + /* FALLTHROUGH */ + case 1: return NRF_P1; +#endif + } } -__STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end) +NRF_STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end) { - /*lint -e{845} // A zero has been given as right argument to operator '|'" */ for (; pin_range_start <= pin_range_end; pin_range_start++) { nrf_gpio_cfg_output(pin_range_start); @@ -516,11 +556,10 @@ __STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_ } -__STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, - uint32_t pin_range_end, - nrf_gpio_pin_pull_t pull_config) +NRF_STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, + uint32_t pin_range_end, + nrf_gpio_pin_pull_t pull_config) { - /*lint -e{845} // A zero has been given as right argument to operator '|'" */ for (; pin_range_start <= pin_range_end; pin_range_start++) { nrf_gpio_cfg_input(pin_range_start, pull_config); @@ -528,7 +567,7 @@ __STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_star } -__STATIC_INLINE void nrf_gpio_cfg( +NRF_STATIC_INLINE void nrf_gpio_cfg( uint32_t pin_number, nrf_gpio_pin_dir_t dir, nrf_gpio_pin_input_t input, @@ -538,15 +577,23 @@ __STATIC_INLINE void nrf_gpio_cfg( { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos) - | ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) - | ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos) - | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) - | ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos); +#if defined(GPIO_PIN_CNF_MCUSEL_Msk) + /* Preserve MCUSEL setting. */ + uint32_t cnf = reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_MCUSEL_Msk; +#else + uint32_t cnf = 0; +#endif + cnf |= ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos) | + ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) | + ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos) | + ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) | + ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos); + + reg->PIN_CNF[pin_number] = cnf; } -__STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number) +NRF_STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number) { nrf_gpio_cfg( pin_number, @@ -558,7 +605,7 @@ __STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number) } -__STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config) +NRF_STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config) { nrf_gpio_cfg( pin_number, @@ -570,7 +617,7 @@ __STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t } -__STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number) +NRF_STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number) { nrf_gpio_cfg( pin_number, @@ -582,29 +629,27 @@ __STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number) } -__STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number) +NRF_STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - /*lint -e{845} // A zero has been given as right argument to operator '|'" */ uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk; reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos); } -__STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number) +NRF_STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - /*lint -e{845} // A zero has been given as right argument to operator '|'" */ uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk; reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos); } -__STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, - nrf_gpio_pin_pull_t pull_config, - nrf_gpio_pin_sense_t sense_config) +NRF_STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, + nrf_gpio_pin_pull_t pull_config, + nrf_gpio_pin_sense_t sense_config) { nrf_gpio_cfg( pin_number, @@ -616,17 +661,17 @@ __STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, } -__STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config) +NRF_STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, + nrf_gpio_pin_sense_t sense_config) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk; - /*lint -e{845} // A zero has been given as right argument to operator '|'" */ - reg->PIN_CNF[pin_number] &= ~GPIO_PIN_CNF_SENSE_Msk; - reg->PIN_CNF[pin_number] |= (sense_config << GPIO_PIN_CNF_SENSE_Pos); + reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos); } -__STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction) +NRF_STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction) { if (direction == NRF_GPIO_PIN_DIR_INPUT) { @@ -646,7 +691,7 @@ __STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_ } -__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number) +NRF_STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); @@ -654,7 +699,7 @@ __STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number) } -__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number) +NRF_STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); @@ -662,7 +707,7 @@ __STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number) } -__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number) +NRF_STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); uint32_t pins_state = reg->OUT; @@ -672,7 +717,7 @@ __STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number) } -__STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value) +NRF_STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value) { if (value == 0) { @@ -685,7 +730,7 @@ __STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value) } -__STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number) +NRF_STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); @@ -693,7 +738,7 @@ __STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number) } -__STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number) +NRF_STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); @@ -701,7 +746,7 @@ __STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number) } -__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number) +NRF_STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); @@ -710,7 +755,7 @@ __STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number) } -__STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number) +NRF_STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); @@ -718,7 +763,7 @@ __STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number) GPIO_PIN_CNF_DIR_Msk) >> GPIO_PIN_CNF_DIR_Pos); } -__STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number) +NRF_STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); @@ -726,7 +771,7 @@ __STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number) GPIO_PIN_CNF_INPUT_Msk) >> GPIO_PIN_CNF_INPUT_Pos); } -__STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number) +NRF_STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); @@ -735,61 +780,63 @@ __STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number) } -__STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask) +NRF_STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask) { p_reg->DIRSET = out_mask; } -__STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask) +NRF_STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask) { p_reg->DIRCLR = in_mask; } -__STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t value) +NRF_STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t value) { p_reg->DIR = value; } -__STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg) +NRF_STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg) { return p_reg->DIR; } -__STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg) +NRF_STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg) { return p_reg->IN; } -__STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg) +NRF_STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg) { return p_reg->OUT; } -__STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value) +NRF_STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value) { p_reg->OUT = value; } -__STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask) +NRF_STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask) { p_reg->OUTSET = set_mask; } -__STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask) +NRF_STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask) { p_reg->OUTCLR = clr_mask; } -__STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, uint32_t * p_masks) +NRF_STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, + uint32_t length, + uint32_t * p_masks) { NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST; @@ -805,9 +852,9 @@ __STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, u #if defined(NRF_GPIO_LATCH_PRESENT) -__STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, - uint32_t length, - uint32_t * p_masks) +NRF_STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, + uint32_t length, + uint32_t * p_masks) { NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST; uint32_t i; @@ -819,9 +866,9 @@ __STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, } } -__STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port, - uint32_t length, - uint32_t * p_masks) +NRF_STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port, + uint32_t length, + uint32_t * p_masks) { NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST; uint32_t i; @@ -837,7 +884,7 @@ __STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port, } } -__STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number) +NRF_STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); @@ -845,7 +892,7 @@ __STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number) } -__STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number) +NRF_STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); @@ -853,7 +900,16 @@ __STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number) } #endif // defined(NRF_GPIO_LATCH_PRESENT) -__STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number) +#if defined(GPIO_PIN_CNF_MCUSEL_Msk) +NRF_STATIC_INLINE void nrf_gpio_pin_mcu_select(uint32_t pin_number, nrf_gpio_pin_mcusel_t mcu) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_MCUSEL_Msk; + reg->PIN_CNF[pin_number] = cnf | (mcu << GPIO_PIN_CNF_MCUSEL_Pos); +} +#endif + +NRF_STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number) { uint32_t port = pin_number >> 5; uint32_t mask = 0; @@ -888,7 +944,15 @@ __STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number) return (mask & (1UL << pin_number)) ? true : false; } -#endif // SUPPRESS_INLINE_IMPLEMENTATION +NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin) +{ + uint32_t pin_number = *p_pin; + *p_pin = pin_number & 0x1F; + + return pin_number >> 5; +} + +#endif // NRF_DECLARE_ONLY /** @} */ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/mdk/nrf52820_peripherals.h b/source/hic_hal/nordic/nrf52820/nrfx/mdk/nrf52820_peripherals.h index 0dd2dcba0..72c28333c 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/mdk/nrf52820_peripherals.h +++ b/source/hic_hal/nordic/nrf52820/nrfx/mdk/nrf52820_peripherals.h @@ -1,41 +1,34 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. -All rights reserved. +SPDX-License-Identifier: BSD-3-Clause -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. */ @@ -83,7 +76,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define RADIO_PRESENT #define RADIO_COUNT 1 -#define RADIO_EASYDMA_MAXCNT_SIZE 16 +#define RADIO_EASYDMA_MAXCNT_SIZE 14 #define RADIO_FEATURE_IEEE_802_15_4_PRESENT #define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos8dBm @@ -175,15 +168,15 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define SPIM0_FEATURE_RXDELAY_PRESENT 0 #define SPIM1_FEATURE_RXDELAY_PRESENT 0 -#define SPIM0_EASYDMA_MAXCNT_SIZE 16 -#define SPIM1_EASYDMA_MAXCNT_SIZE 16 +#define SPIM0_EASYDMA_MAXCNT_SIZE 15 +#define SPIM1_EASYDMA_MAXCNT_SIZE 15 /* Serial Peripheral Interface Slave with DMA*/ #define SPIS_PRESENT #define SPIS_COUNT 2 -#define SPIS0_EASYDMA_MAXCNT_SIZE 16 -#define SPIS1_EASYDMA_MAXCNT_SIZE 16 +#define SPIS0_EASYDMA_MAXCNT_SIZE 15 +#define SPIS1_EASYDMA_MAXCNT_SIZE 15 /* Two Wire Interface Master */ #define TWI_PRESENT @@ -193,15 +186,15 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define TWIM_PRESENT #define TWIM_COUNT 2 -#define TWIM0_EASYDMA_MAXCNT_SIZE 16 -#define TWIM1_EASYDMA_MAXCNT_SIZE 16 +#define TWIM0_EASYDMA_MAXCNT_SIZE 15 +#define TWIM1_EASYDMA_MAXCNT_SIZE 15 /* Two Wire Interface Slave with DMA */ #define TWIS_PRESENT #define TWIS_COUNT 2 -#define TWIS0_EASYDMA_MAXCNT_SIZE 16 -#define TWIS1_EASYDMA_MAXCNT_SIZE 16 +#define TWIS0_EASYDMA_MAXCNT_SIZE 15 +#define TWIS1_EASYDMA_MAXCNT_SIZE 15 /* Universal Asynchronous Receiver-Transmitter */ #define UART_PRESENT @@ -211,7 +204,7 @@ OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define UARTE_PRESENT #define UARTE_COUNT 1 -#define UARTE0_EASYDMA_MAXCNT_SIZE 16 +#define UARTE0_EASYDMA_MAXCNT_SIZE 15 /* Quadrature Decoder */ #define QDEC_PRESENT diff --git a/source/hic_hal/nordic/nrf52820/nrfx/mdk/nrf_peripherals.h b/source/hic_hal/nordic/nrf52820/nrfx/mdk/nrf_peripherals.h index 3f9e7b7a2..3f982920d 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/mdk/nrf_peripherals.h +++ b/source/hic_hal/nordic/nrf52820/nrfx/mdk/nrf_peripherals.h @@ -1,41 +1,34 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. -All rights reserved. +SPDX-License-Identifier: BSD-3-Clause -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form, except as embedded into a Nordic - Semiconductor ASA integrated circuit in a product or a software update for - such product, must reproduce the above copyright notice, this list of - conditions and the following disclaimer in the documentation and/or other - materials provided with the distribution. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. -4. This software, with or without modification, must only be used with a - Nordic Semiconductor ASA integrated circuit. - -5. Any software provided in binary form under this license must not be reverse - engineered, decompiled, modified and/or disassembled. - -THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS -OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. */ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/mdk/system_nrf52_approtect.h b/source/hic_hal/nordic/nrf52820/nrfx/mdk/system_nrf52_approtect.h new file mode 100644 index 000000000..86a8b65b4 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx/mdk/system_nrf52_approtect.h @@ -0,0 +1,65 @@ +/* + +Copyright (c) 2009-2021 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +#ifndef SYSTEM_NRF52_APPROTECT_H +#define SYSTEM_NRF52_APPROTECT_H + +#include "nrf.h" +#include "nrf_erratas.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Function that handles firmware-driven enabling or disabling of APPROTECT on devices where it is supported. + If ENABLE_APPROTECT is defined, the FW will lock the fw branch of the APPROTECT mechanism, + preventing it from being opened. + Otherwise, the fw branch state is loaded from UICR, emulating the legacy APPROTECT behavior. + + The same mechanism is implemented for SECURE APPROTECT, with the macros + ENABLE_SECURE_APPROTECT and ENABLE_SECURE_APPROTECT_USER_HANDLING. */ +static inline void nrf52_handle_approtect(void) +{ + #if NRF52_ERRATA_249_PRESENT + #if defined (ENABLE_APPROTECT) + if (nrf52_errata_249()) + { + /* Prevent processor from unlocking APPROTECT soft branch after this point. */ + NRF_APPROTECT->FORCEPROTECT = APPROTECT_FORCEPROTECT_FORCEPROTECT_Force; + } + #else + if (nrf52_errata_249()) + { + /* Load APPROTECT soft branch from UICR. + If UICR->APPROTECT is disabled, POWER->APPROTECT will be disabled. */ + NRF_APPROTECT->DISABLE = NRF_UICR->APPROTECT; + } + #endif + #endif +} + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_NRF52_APPROTECT_H */ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/nrfx.h b/source/hic_hal/nordic/nrf52820/nrfx/nrfx.h index 575b7d9a5..e5bda3765 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/nrfx.h +++ b/source/hic_hal/nordic/nrf52820/nrfx/nrfx.h @@ -1,41 +1,34 @@ -/** - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA - * +/* + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_H__ @@ -44,6 +37,7 @@ #include #include #include +#include #include #endif // NRFX_H__ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_glue.h b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_glue.h index 2bbb7b8aa..a19ab37b8 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_glue.h +++ b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_glue.h @@ -1,41 +1,34 @@ -/** - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA - * +/* + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_GLUE_H__ @@ -240,23 +233,35 @@ extern "C" { //------------------------------------------------------------------------------ +/** + * @brief When set to a non-zero value, this macro specifies that inside HALs + * the event registers are read back after clearing, on devices that + * otherwise could defer the actual register modification. + */ +#define NRFX_EVENT_READBACK_ENABLED 1 + +//------------------------------------------------------------------------------ + /** @brief Bitmask that defines DPPI channels that are reserved for use outside of the nrfx library. */ -#define NRFX_DPPI_CHANNELS_USED 0 +#define NRFX_DPPI_CHANNELS_USED 0 /** @brief Bitmask that defines DPPI groups that are reserved for use outside of the nrfx library. */ -#define NRFX_DPPI_GROUPS_USED 0 +#define NRFX_DPPI_GROUPS_USED 0 /** @brief Bitmask that defines PPI channels that are reserved for use outside of the nrfx library. */ -#define NRFX_PPI_CHANNELS_USED 0 +#define NRFX_PPI_CHANNELS_USED 0 /** @brief Bitmask that defines PPI groups that are reserved for use outside of the nrfx library. */ -#define NRFX_PPI_GROUPS_USED 0 +#define NRFX_PPI_GROUPS_USED 0 + +/** @brief Bitmask that defines GPIOTE channels that are reserved for use outside of the nrfx library. */ +#define NRFX_GPIOTE_CHANNELS_USED 0 -/** @brief Bitmask that defines SWI instances that are reserved for use outside of the nrfx library. */ -#define NRFX_SWI_USED 0 +/** @brief Bitmask that defines EGU instances that are reserved for use outside of the nrfx library. */ +#define NRFX_EGUS_USED 0 /** @brief Bitmask that defines TIMER instances that are reserved for use outside of the nrfx library. */ -#define NRFX_TIMERS_USED 0 +#define NRFX_TIMERS_USED 0 /** @} */ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_log.h b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_log.h index a3b079420..cbbb2f9eb 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_log.h +++ b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_log.h @@ -1,41 +1,34 @@ -/** - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA - * +/* + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_LOG_H__ From d650147ce075b3838ea947e97ae978a444427dfb Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 30 Sep 2021 22:48:24 -0500 Subject: [PATCH 447/617] nrf52820_hic: update to nrfx v2.5.0 (2/3) Update flash.c to new nrf_nmvc API --- source/hic_hal/nordic/nrf52820/flash.c | 19 +- .../nordic/nrf52820/nrfx/hal/nrf_nvmc.c | 133 ---------- .../nordic/nrf52820/nrfx/hal/nrf_nvmc.h | 234 +++++++----------- 3 files changed, 107 insertions(+), 279 deletions(-) delete mode 100644 source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_nvmc.c diff --git a/source/hic_hal/nordic/nrf52820/flash.c b/source/hic_hal/nordic/nrf52820/flash.c index 120b4304d..5b4ffad7c 100644 --- a/source/hic_hal/nordic/nrf52820/flash.c +++ b/source/hic_hal/nordic/nrf52820/flash.c @@ -20,7 +20,6 @@ */ #include "target_config.h" - #include "nrf_nvmc.h" uint32_t Init(uint32_t adr, uint32_t clk, uint32_t fnc) @@ -40,12 +39,26 @@ uint32_t EraseChip(void) uint32_t EraseSector(uint32_t adr) { - nrf_nvmc_page_erase(adr); + nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_ERASE); + nrf_nvmc_page_erase_start(NRF_NVMC, adr); + while (!nrf_nvmc_ready_check(NRF_NVMC)) { + // Wait for controller to be ready + } + nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_READONLY); + return 0; } uint32_t ProgramPage(uint32_t adr, uint32_t sz, uint32_t *buf) { - nrf_nvmc_write_words(adr, buf, sz / 4); + nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_WRITE); + for (uint32_t i = 0; i < sz / 4; i++) { + ((volatile uint32_t *)adr)[i] = buf[i]; + while (!nrf_nvmc_ready_check(NRF_NVMC)) { + // Wait for controller to be ready + } + } + nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_READONLY); + return 0; } diff --git a/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_nvmc.c b/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_nvmc.c deleted file mode 100644 index 601b74e34..000000000 --- a/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_nvmc.c +++ /dev/null @@ -1,133 +0,0 @@ -/** - * Copyright (c) 2012 - 2020, Nordic Semiconductor ASA - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -/** - *@file - *@brief NMVC driver implementation - */ - -#include -#include "nrf_nvmc.h" - -static inline void wait_for_flash_ready(void) -{ - while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {;} -} - -void nrf_nvmc_page_erase(uint32_t address) -{ - // Enable erase. - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Een; - __ISB(); - __DSB(); - - // Erase the page - NRF_NVMC->ERASEPAGE = address; - wait_for_flash_ready(); - - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren; - __ISB(); - __DSB(); -} - - -void nrf_nvmc_write_byte(uint32_t address, uint8_t value) -{ - uint32_t byte_shift = address & (uint32_t)0x03; - uint32_t address32 = address & ~byte_shift; // Address to the word this byte is in. - uint32_t value32 = (*(uint32_t*)address32 & ~((uint32_t)0xFF << (byte_shift << (uint32_t)3))); - value32 = value32 + ((uint32_t)value << (byte_shift << 3)); - - // Enable write. - NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos); - __ISB(); - __DSB(); - - *(uint32_t*)address32 = value32; - wait_for_flash_ready(); - - NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos); - __ISB(); - __DSB(); -} - -void nrf_nvmc_write_word(uint32_t address, uint32_t value) -{ - // Enable write. - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen; - __ISB(); - __DSB(); - - *(uint32_t*)address = value; - wait_for_flash_ready(); - - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren; - __ISB(); - __DSB(); -} - -void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes) -{ - uint32_t i; - for (i = 0; i < num_bytes; i++) - { - nrf_nvmc_write_byte(address + i,src[i]); - } -} - -void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words) -{ - uint32_t i; - - // Enable write. - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen; - __ISB(); - __DSB(); - - for (i = 0; i < num_words; i++) - { - ((uint32_t*)address)[i] = src[i]; - wait_for_flash_ready(); - } - - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren; - __ISB(); - __DSB(); -} - diff --git a/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_nvmc.h b/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_nvmc.h index 605972ccb..d9d16a274 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_nvmc.h +++ b/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_nvmc.h @@ -1,41 +1,34 @@ -/** - * Copyright (c) 2012 - 2020, Nordic Semiconductor ASA - * +/* + * Copyright (c) 2012 - 2021, Nordic Semiconductor ASA * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_NVMC_H__ @@ -47,62 +40,6 @@ extern "C" { #endif -/** - * @defgroup nrf_nvmc_hal_deprecated NVMC HAL (deprecated) - * @{ - * @ingroup nrf_nvmc - * @brief Hardware access layer (HAL) for managing the Non-Volatile Memory Controller (NVMC) peripheral. - * - * This driver allows writing to the non-volatile memory (NVM) regions - * of the chip. To write to NVM, the controller must be powered - * on and the relevant page must be erased. - */ - -/** - * @brief Erase a page in flash. This is required before writing to any address in the page. - * - * @param address Start address of the page. - */ -void nrf_nvmc_page_erase(uint32_t address); - -/** - * @brief Write a single byte to flash. - * - * The function reads the word containing the byte, and then rewrites the entire word. - * - * @param address Address to write to. - * @param value Value to write. - */ -void nrf_nvmc_write_byte(uint32_t address , uint8_t value); - -/** - * @brief Write a 32-bit word to flash. - * - * @param address Address to write to. - * @param value Value to write. - */ -void nrf_nvmc_write_word(uint32_t address, uint32_t value); - -/** - * @brief Write consecutive bytes to flash. - * - * @param address Address to write to. - * @param src Pointer to data to copy from. - * @param num_bytes Number of bytes in src to write. - */ -void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes); - -/** - * @brief Write consecutive words to flash. - * - * @param address Address to write to. - * @param src Pointer to data to copy from. - * @param num_words Number of words in src to write. - */ -void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words); - -/** @} */ - /** * @defgroup nrf_nvmc_hal NVMC HAL * @{ @@ -110,11 +47,6 @@ void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_w * @brief Hardware access layer (HAL) for managing the Non-Volatile Memory Controller (NVMC) peripheral. */ -#if defined(NVMC_ICACHECNF_CACHEEN_Msk) || defined(__NRFX_DOXYGEN__) -/** @brief Symbol indicating whether Instruction Cache (ICache) is present. */ -#define NRF_NVMC_ICACHE_PRESENT -#endif - #if defined(NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk) || defined(__NRFX_DOXYGEN__) /** @brief Symbol indicating whether the option of page partial erase is present. */ #define NRF_NVMC_PARTIAL_ERASE_PRESENT @@ -141,7 +73,7 @@ typedef enum } nrf_nvmc_ns_mode_t; #endif -#if defined(NRF_NVMC_ICACHE_PRESENT) +#if defined(NVMC_FEATURE_CACHE_PRESENT) /** @brief NVMC ICache configuration. */ typedef enum { @@ -150,7 +82,7 @@ typedef enum NRF_NVMC_ICACHE_ENABLE_WITH_PROFILING = NVMC_ICACHECNF_CACHEEN_Enabled | ///< Instruction Cache with cache profiling enabled. NVMC_ICACHECNF_CACHEPROFEN_Msk } nrf_nvmc_icache_config_t; -#endif // defined(NRF_NVMC_ICACHE_PRESENT) +#endif // defined(NVMC_FEATURE_CACHE_PRESENT) /** * @brief Function for checking if NVMC is ready to perform write or erase operation. @@ -160,7 +92,7 @@ typedef enum * @retval true NVMC can perform write or erase. * @retval false NVMC is busy and cannot perform next operation yet. */ -__STATIC_INLINE bool nrf_nvmc_ready_check(NRF_NVMC_Type const * p_reg); +NRF_STATIC_INLINE bool nrf_nvmc_ready_check(NRF_NVMC_Type const * p_reg); #if defined(NVMC_READYNEXT_READYNEXT_Msk) || defined(__NRFX_DOXYGEN__) /** @@ -174,7 +106,7 @@ __STATIC_INLINE bool nrf_nvmc_ready_check(NRF_NVMC_Type const * p_reg); * into account as soon as the ongoing write operation is completed. * @retval false NVMC is busy and cannot accept the next write yet. */ -__STATIC_INLINE bool nrf_nvmc_write_ready_check(NRF_NVMC_Type const * p_reg); +NRF_STATIC_INLINE bool nrf_nvmc_write_ready_check(NRF_NVMC_Type const * p_reg); #endif // defined(NVMC_READYNEXT_READYNEXT_Msk) || defined(__NRFX_DOXYGEN__) /** @@ -187,8 +119,8 @@ __STATIC_INLINE bool nrf_nvmc_write_ready_check(NRF_NVMC_Type const * p_reg); * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] mode Desired operating mode for NVMC. */ -__STATIC_INLINE void nrf_nvmc_mode_set(NRF_NVMC_Type * p_reg, - nrf_nvmc_mode_t mode); +NRF_STATIC_INLINE void nrf_nvmc_mode_set(NRF_NVMC_Type * p_reg, + nrf_nvmc_mode_t mode); #if defined(NVMC_CONFIGNS_WEN_Msk) || defined(__NRFX_DOXYGEN__) /** @@ -197,8 +129,8 @@ __STATIC_INLINE void nrf_nvmc_mode_set(NRF_NVMC_Type * p_reg, * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] mode Desired operating mode for NVMC. */ -__STATIC_INLINE void nrf_nvmc_nonsecure_mode_set(NRF_NVMC_Type * p_reg, - nrf_nvmc_ns_mode_t mode); +NRF_STATIC_INLINE void nrf_nvmc_nonsecure_mode_set(NRF_NVMC_Type * p_reg, + nrf_nvmc_ns_mode_t mode); #endif /** @@ -210,8 +142,8 @@ __STATIC_INLINE void nrf_nvmc_nonsecure_mode_set(NRF_NVMC_Type * p_reg, * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] page_addr Address of the first word of the page to erase. */ -__STATIC_INLINE void nrf_nvmc_page_erase_start(NRF_NVMC_Type * p_reg, - uint32_t page_addr); +NRF_STATIC_INLINE void nrf_nvmc_page_erase_start(NRF_NVMC_Type * p_reg, + uint32_t page_addr); #if defined(NVMC_ERASEUICR_ERASEUICR_Msk) || defined(__NRFX_DOXYGEN__) /** @@ -219,7 +151,7 @@ __STATIC_INLINE void nrf_nvmc_page_erase_start(NRF_NVMC_Type * p_reg, * * @param[in] p_reg Pointer to the structure of registers of the peripheral. */ -__STATIC_INLINE void nrf_nvmc_uicr_erase_start(NRF_NVMC_Type * p_reg); +NRF_STATIC_INLINE void nrf_nvmc_uicr_erase_start(NRF_NVMC_Type * p_reg); #endif /** @@ -229,7 +161,7 @@ __STATIC_INLINE void nrf_nvmc_uicr_erase_start(NRF_NVMC_Type * p_reg); * * @param[in] p_reg Pointer to the structure of registers of the peripheral. */ -__STATIC_INLINE void nrf_nvmc_erase_all_start(NRF_NVMC_Type * p_reg); +NRF_STATIC_INLINE void nrf_nvmc_erase_all_start(NRF_NVMC_Type * p_reg); #if defined(NRF_NVMC_PARTIAL_ERASE_PRESENT) /** @@ -238,8 +170,8 @@ __STATIC_INLINE void nrf_nvmc_erase_all_start(NRF_NVMC_Type * p_reg); * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] duration_ms Page partial erase duration in milliseconds. */ -__STATIC_INLINE void nrf_nvmc_partial_erase_duration_set(NRF_NVMC_Type * p_reg, - uint32_t duration_ms); +NRF_STATIC_INLINE void nrf_nvmc_partial_erase_duration_set(NRF_NVMC_Type * p_reg, + uint32_t duration_ms); /** * @brief Function for getting the current setting for the page partial erase duration. @@ -248,7 +180,7 @@ __STATIC_INLINE void nrf_nvmc_partial_erase_duration_set(NRF_NVMC_Type * p_reg, * * @retval Interval duration setting in milliseconds. */ -__STATIC_INLINE uint32_t nrf_nvmc_partial_erase_duration_get(NRF_NVMC_Type const * p_reg); +NRF_STATIC_INLINE uint32_t nrf_nvmc_partial_erase_duration_get(NRF_NVMC_Type const * p_reg); /** * @brief Function for starting a partial erase operation. @@ -258,11 +190,11 @@ __STATIC_INLINE uint32_t nrf_nvmc_partial_erase_duration_get(NRF_NVMC_Type const * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] page_addr Address of the first word of the page to erase. */ -__STATIC_INLINE void nrf_nvmc_page_partial_erase_start(NRF_NVMC_Type * p_reg, - uint32_t page_addr); +NRF_STATIC_INLINE void nrf_nvmc_page_partial_erase_start(NRF_NVMC_Type * p_reg, + uint32_t page_addr); #endif // defined(NRF_NVMC_PARTIAL_ERASE_PRESENT) -#if defined(NRF_NVMC_ICACHE_PRESENT) +#if defined(NVMC_FEATURE_CACHE_PRESENT) /** * @brief Function for applying the Instruction Cache (ICache) configuration. * @@ -273,8 +205,8 @@ __STATIC_INLINE void nrf_nvmc_page_partial_erase_start(NRF_NVMC_Type * p_reg, * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] config ICache configuration. */ -__STATIC_INLINE void nrf_nvmc_icache_config_set(NRF_NVMC_Type * p_reg, - nrf_nvmc_icache_config_t config); +NRF_STATIC_INLINE void nrf_nvmc_icache_config_set(NRF_NVMC_Type * p_reg, + nrf_nvmc_icache_config_t config); /** * @brief Function for checking if ICache is enabled. @@ -284,7 +216,7 @@ __STATIC_INLINE void nrf_nvmc_icache_config_set(NRF_NVMC_Type * p_reg, * @retval true ICache enabled. * @retval false ICache disabled. */ -__STATIC_INLINE bool nrf_nvmc_icache_enable_check(NRF_NVMC_Type const * p_reg); +NRF_STATIC_INLINE bool nrf_nvmc_icache_enable_check(NRF_NVMC_Type const * p_reg); /** * @brief Function for checking if the ICache profiling option is enabled. @@ -294,7 +226,7 @@ __STATIC_INLINE bool nrf_nvmc_icache_enable_check(NRF_NVMC_Type const * p_reg); * @retval true ICache profiling enabled. * @retval false ICache profiling disabled. */ -__STATIC_INLINE bool nrf_nvmc_icache_profiling_enable_check(NRF_NVMC_Type const * p_reg); +NRF_STATIC_INLINE bool nrf_nvmc_icache_profiling_enable_check(NRF_NVMC_Type const * p_reg); /** * @brief Function for getting the number of ICache hits. @@ -303,7 +235,7 @@ __STATIC_INLINE bool nrf_nvmc_icache_profiling_enable_check(NRF_NVMC_Type const * * @retval Number of the ICache hits. */ -__STATIC_INLINE uint32_t nrf_nvmc_icache_hit_get(NRF_NVMC_Type const * p_reg); +NRF_STATIC_INLINE uint32_t nrf_nvmc_icache_hit_get(NRF_NVMC_Type const * p_reg); /** * @brief Function for getting the number of ICache misses. @@ -312,46 +244,46 @@ __STATIC_INLINE uint32_t nrf_nvmc_icache_hit_get(NRF_NVMC_Type const * p_reg); * * @retval Number of the ICache misses. */ -__STATIC_INLINE uint32_t nrf_nvmc_icache_miss_get(NRF_NVMC_Type const * p_reg); +NRF_STATIC_INLINE uint32_t nrf_nvmc_icache_miss_get(NRF_NVMC_Type const * p_reg); /** * @brief Function for resetting the ICache hit and miss counters. * * @param[in] p_reg Pointer to the structure of registers of the peripheral. */ - __STATIC_INLINE void nrf_nvmc_icache_hit_miss_reset(NRF_NVMC_Type * p_reg); -#endif // defined(NRF_NVMC_ICACHE_PRESENT) + NRF_STATIC_INLINE void nrf_nvmc_icache_hit_miss_reset(NRF_NVMC_Type * p_reg); +#endif // defined(NVMC_FEATURE_CACHE_PRESENT) -#ifndef SUPPRESS_INLINE_IMPLEMENTATION +#ifndef NRF_DECLARE_ONLY -__STATIC_INLINE bool nrf_nvmc_ready_check(NRF_NVMC_Type const * p_reg) +NRF_STATIC_INLINE bool nrf_nvmc_ready_check(NRF_NVMC_Type const * p_reg) { return (bool)(p_reg->READY & NVMC_READY_READY_Msk); } #if defined(NVMC_READYNEXT_READYNEXT_Msk) -__STATIC_INLINE bool nrf_nvmc_write_ready_check(NRF_NVMC_Type const * p_reg) +NRF_STATIC_INLINE bool nrf_nvmc_write_ready_check(NRF_NVMC_Type const * p_reg) { return (bool)(p_reg->READYNEXT & NVMC_READYNEXT_READYNEXT_Msk); } #endif -__STATIC_INLINE void nrf_nvmc_mode_set(NRF_NVMC_Type * p_reg, - nrf_nvmc_mode_t mode) +NRF_STATIC_INLINE void nrf_nvmc_mode_set(NRF_NVMC_Type * p_reg, + nrf_nvmc_mode_t mode) { p_reg->CONFIG = (uint32_t)mode; } #if defined(NVMC_CONFIGNS_WEN_Msk) -__STATIC_INLINE void nrf_nvmc_nonsecure_mode_set(NRF_NVMC_Type * p_reg, - nrf_nvmc_ns_mode_t mode) +NRF_STATIC_INLINE void nrf_nvmc_nonsecure_mode_set(NRF_NVMC_Type * p_reg, + nrf_nvmc_ns_mode_t mode) { p_reg->CONFIGNS = (uint32_t)mode; } #endif -__STATIC_INLINE void nrf_nvmc_page_erase_start(NRF_NVMC_Type * p_reg, - uint32_t page_addr) +NRF_STATIC_INLINE void nrf_nvmc_page_erase_start(NRF_NVMC_Type * p_reg, + uint32_t page_addr) { #if defined(NRF51) /* On nRF51, the code area can be divided into two regions: CR0 and CR1. @@ -370,7 +302,7 @@ __STATIC_INLINE void nrf_nvmc_page_erase_start(NRF_NVMC_Type * p_reg, } #elif defined(NRF52_SERIES) p_reg->ERASEPAGE = page_addr; -#elif defined(NRF9160_XXAA) +#elif defined(NRF9160_XXAA) || defined(NRF5340_XXAA_APPLICATION) || defined(NRF5340_XXAA_NETWORK) *(volatile uint32_t *)page_addr = 0xFFFFFFFF; (void)p_reg; #else @@ -379,35 +311,35 @@ __STATIC_INLINE void nrf_nvmc_page_erase_start(NRF_NVMC_Type * p_reg, } #if defined(NVMC_ERASEUICR_ERASEUICR_Msk) -__STATIC_INLINE void nrf_nvmc_uicr_erase_start(NRF_NVMC_Type * p_reg) +NRF_STATIC_INLINE void nrf_nvmc_uicr_erase_start(NRF_NVMC_Type * p_reg) { p_reg->ERASEUICR = 1; } #endif -__STATIC_INLINE void nrf_nvmc_erase_all_start(NRF_NVMC_Type * p_reg) +NRF_STATIC_INLINE void nrf_nvmc_erase_all_start(NRF_NVMC_Type * p_reg) { p_reg->ERASEALL = 1; } #if defined(NRF_NVMC_PARTIAL_ERASE_PRESENT) -__STATIC_INLINE void nrf_nvmc_partial_erase_duration_set(NRF_NVMC_Type * p_reg, - uint32_t duration_ms) +NRF_STATIC_INLINE void nrf_nvmc_partial_erase_duration_set(NRF_NVMC_Type * p_reg, + uint32_t duration_ms) { p_reg->ERASEPAGEPARTIALCFG = duration_ms; } -__STATIC_INLINE uint32_t nrf_nvmc_partial_erase_duration_get(NRF_NVMC_Type const * p_reg) +NRF_STATIC_INLINE uint32_t nrf_nvmc_partial_erase_duration_get(NRF_NVMC_Type const * p_reg) { return p_reg->ERASEPAGEPARTIALCFG; } -__STATIC_INLINE void nrf_nvmc_page_partial_erase_start(NRF_NVMC_Type * p_reg, - uint32_t page_addr) +NRF_STATIC_INLINE void nrf_nvmc_page_partial_erase_start(NRF_NVMC_Type * p_reg, + uint32_t page_addr) { #if defined(NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Msk) p_reg->ERASEPAGEPARTIAL = page_addr; -#elif defined(NRF9160_XXAA) +#elif defined(NRF9160_XXAA) || defined(NRF5340_XXAA_APPLICATION) || defined(NRF5340_XXAA_NETWORK) nrf_nvmc_page_erase_start(p_reg, page_addr); #else #error "Unknown device." @@ -415,41 +347,57 @@ __STATIC_INLINE void nrf_nvmc_page_partial_erase_start(NRF_NVMC_Type * p_reg, } #endif // defined(NRF_NVMC_PARTIAL_ERASE_PRESENT) -#if defined(NRF_NVMC_ICACHE_PRESENT) -__STATIC_INLINE void nrf_nvmc_icache_config_set(NRF_NVMC_Type * p_reg, - nrf_nvmc_icache_config_t config) +#if defined(NVMC_FEATURE_CACHE_PRESENT) +NRF_STATIC_INLINE void nrf_nvmc_icache_config_set(NRF_NVMC_Type * p_reg, + nrf_nvmc_icache_config_t config) { - p_reg->ICACHECNF = (uint32_t)config; +#if defined(NRF5340_XXAA_NETWORK) || defined(NRF9160_XXAA) + // Apply workaround for the anomalies: + // - 6 for the nRF5340. + // - 21 for the nRF9160. + if (config == NRF_NVMC_ICACHE_DISABLE) + { + NRFX_CRITICAL_SECTION_ENTER(); + __ISB(); + p_reg->ICACHECNF = (uint32_t)NRF_NVMC_ICACHE_DISABLE; + __ISB(); + NRFX_CRITICAL_SECTION_EXIT(); + } + else +#endif + { + p_reg->ICACHECNF = (uint32_t)config; + } } -__STATIC_INLINE bool nrf_nvmc_icache_enable_check(NRF_NVMC_Type const * p_reg) +NRF_STATIC_INLINE bool nrf_nvmc_icache_enable_check(NRF_NVMC_Type const * p_reg) { return (bool)(p_reg->ICACHECNF & NVMC_ICACHECNF_CACHEEN_Msk); } -__STATIC_INLINE bool nrf_nvmc_icache_profiling_enable_check(NRF_NVMC_Type const * p_reg) +NRF_STATIC_INLINE bool nrf_nvmc_icache_profiling_enable_check(NRF_NVMC_Type const * p_reg) { return (bool)(p_reg->ICACHECNF & NVMC_ICACHECNF_CACHEPROFEN_Msk); } -__STATIC_INLINE uint32_t nrf_nvmc_icache_hit_get(NRF_NVMC_Type const * p_reg) +NRF_STATIC_INLINE uint32_t nrf_nvmc_icache_hit_get(NRF_NVMC_Type const * p_reg) { return p_reg->IHIT; } -__STATIC_INLINE uint32_t nrf_nvmc_icache_miss_get(NRF_NVMC_Type const * p_reg) +NRF_STATIC_INLINE uint32_t nrf_nvmc_icache_miss_get(NRF_NVMC_Type const * p_reg) { return p_reg->IMISS; } -__STATIC_INLINE void nrf_nvmc_icache_hit_miss_reset(NRF_NVMC_Type * p_reg) +NRF_STATIC_INLINE void nrf_nvmc_icache_hit_miss_reset(NRF_NVMC_Type * p_reg) { p_reg->IHIT = 0; p_reg->IMISS = 0; } -#endif // defined(NRF_NVMC_ICACHE_PRESENT) +#endif // defined(NVMC_FEATURE_CACHE_PRESENT) -#endif // SUPPRESS_INLINE_IMPLEMENTATION +#endif // NRF_DECLARE_ONLY /** @} */ From 603ff020a9ee55645e94322f4dddc2ad69874229 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 30 Sep 2021 23:03:24 -0500 Subject: [PATCH 448/617] nrf52820_hic: update to nrfx v2.5.0 (3/3) nrf(x)_twis and configuration changes --- .../nordic/nrf52820/nrfx/drivers/nrfx_twis.c | 67 ++- .../nordic/nrf52820/nrfx/drivers/nrfx_twis.h | 89 ++-- .../nordic/nrf52820/nrfx/hal/nrf_twis.h | 384 ++++++++++-------- .../{nrfx_config.h => nrfx_config_nrf52820.h} | 41 +- source/hic_hal/nordic/nrf52820/nrfx_config.h | 63 +++ 5 files changed, 398 insertions(+), 246 deletions(-) rename source/hic_hal/nordic/nrf52820/nrfx/{nrfx_config.h => nrfx_config_nrf52820.h} (96%) create mode 100644 source/hic_hal/nordic/nrf52820/nrfx_config.h diff --git a/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_twis.c b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_twis.c index 932741183..b4f865066 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_twis.c +++ b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_twis.c @@ -1,41 +1,34 @@ -/** - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA - * +/* + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include @@ -515,7 +508,7 @@ nrfx_err_t nrfx_twis_init(nrfx_twis_t const * p_instance, nrfx_twis_config_pin(p_config->scl, p_config->scl_pull); nrfx_twis_config_pin(p_config->sda, p_config->sda_pull); - nrf_twis_config_addr_mask_t addr_mask = (nrf_twis_config_addr_mask_t)0; + uint32_t addr_mask = 0; if (0 == (p_config->addr[0] | p_config->addr[1])) { addr_mask = NRF_TWIS_CONFIG_ADDRESS0_MASK; @@ -543,7 +536,7 @@ nrfx_err_t nrfx_twis_init(nrfx_twis_t const * p_instance, nrf_twis_pins_set (p_reg, p_config->scl, p_config->sda); nrf_twis_address_set (p_reg, 0, p_config->addr[0]); nrf_twis_address_set (p_reg, 1, p_config->addr[1]); - nrf_twis_config_address_set(p_reg, addr_mask); + nrf_twis_config_address_set(p_reg, (nrf_twis_config_addr_mask_t)addr_mask); /* Clear semaphore */ if (!NRFX_TWIS_NO_SYNC_MODE) @@ -566,19 +559,13 @@ void nrfx_twis_uninit(nrfx_twis_t const * p_instance) twis_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); - TWIS_PSEL_Type psel = p_reg->PSEL; + uint32_t scl_pin = nrf_twis_scl_pin_get(p_reg); + uint32_t sda_pin = nrf_twis_sda_pin_get(p_reg); nrfx_twis_swreset(p_reg); - /* Clear pins state if */ - if (!(TWIS_PSEL_SCL_CONNECT_Msk & psel.SCL)) - { - nrf_gpio_cfg_default(psel.SCL); - } - if (!(TWIS_PSEL_SDA_CONNECT_Msk & psel.SDA)) - { - nrf_gpio_cfg_default(psel.SDA); - } + nrf_gpio_cfg_default(scl_pin); + nrf_gpio_cfg_default(sda_pin); #if NRFX_CHECK(NRFX_PRS_ENABLED) nrfx_prs_release(p_reg); @@ -631,7 +618,6 @@ void nrfx_twis_disable(nrfx_twis_t const * p_instance) * * This is the reason for the function below to be implemented in assembly. */ -//lint -save -e578 #if defined (__CC_ARM ) static __ASM uint32_t nrfx_twis_error_get_and_clear_internal(uint32_t volatile * perror) { @@ -690,7 +676,6 @@ static uint32_t nrfx_twis_error_get_and_clear_internal(uint32_t volatile * perro #else #error Unknown compiler #endif -//lint -restore uint32_t nrfx_twis_error_get_and_clear(nrfx_twis_t const * p_instance) { diff --git a/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_twis.h b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_twis.h index 0134b3a99..69782dc68 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_twis.h +++ b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_twis.h @@ -1,41 +1,34 @@ -/** - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA - * +/* + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRFX_TWIS_H__ @@ -154,16 +147,26 @@ typedef struct uint8_t interrupt_priority; //!< The priority of interrupt for the module to be set. } nrfx_twis_config_t; -/** @brief Generate the default configuration for the TWIS driver instance. */ -#define NRFX_TWIS_DEFAULT_CONFIG \ -{ \ - .addr = { NRFX_TWIS_DEFAULT_CONFIG_ADDR0, \ - NRFX_TWIS_DEFAULT_CONFIG_ADDR1 }, \ - .scl = 31, \ - .sda = 31, \ - .scl_pull = (nrf_gpio_pin_pull_t)NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL, \ - .sda_pull = (nrf_gpio_pin_pull_t)NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL, \ - .interrupt_priority = NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY \ +/** + * @brief TWIS driver default configuration. + * + * This configuration sets up TWIS with the following options: + * - second slave address disabled + * - SCL pull-up disabled + * - SDA pull-up disabled + * + * @param[in] _pin_scl SCL pin. + * @param[in] _pin_sda SDA pin. + * @param[in] _addr Slave address on TWI bus. + */ +#define NRFX_TWIS_DEFAULT_CONFIG(_pin_scl, _pin_sda, _addr) \ +{ \ + .addr = { _addr, 0x00 }, \ + .scl = _pin_scl, \ + .sda = _pin_sda, \ + .scl_pull = NRF_GPIO_PIN_NOPULL, \ + .sda_pull = NRF_GPIO_PIN_NOPULL, \ + .interrupt_priority = NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY \ } /** @@ -276,7 +279,7 @@ nrfx_err_t nrfx_twis_tx_prepare(nrfx_twis_t const * p_instance, * * @return Number of bytes sent. */ -__STATIC_INLINE size_t nrfx_twis_tx_amount(nrfx_twis_t const * p_instance); +NRFX_STATIC_INLINE size_t nrfx_twis_tx_amount(nrfx_twis_t const * p_instance); /** * @brief Function for preparing the data for receiving. @@ -310,7 +313,7 @@ nrfx_err_t nrfx_twis_rx_prepare(nrfx_twis_t const * p_instance, * * @return Number of bytes received. */ -__STATIC_INLINE size_t nrfx_twis_rx_amount(nrfx_twis_t const * p_instance); +NRFX_STATIC_INLINE size_t nrfx_twis_rx_amount(nrfx_twis_t const * p_instance); /** * @brief Function for checking if the driver is busy right now. @@ -375,17 +378,17 @@ bool nrfx_twis_is_pending_tx(nrfx_twis_t const * p_instance); */ bool nrfx_twis_is_pending_rx(nrfx_twis_t const * p_instance); -#ifndef SUPPRESS_INLINE_IMPLEMENTATION -__STATIC_INLINE size_t nrfx_twis_tx_amount(nrfx_twis_t const * p_instance) +#ifndef NRFX_DECLARE_ONLY +NRFX_STATIC_INLINE size_t nrfx_twis_tx_amount(nrfx_twis_t const * p_instance) { return nrf_twis_tx_amount_get(p_instance->p_reg); } -__STATIC_INLINE size_t nrfx_twis_rx_amount(nrfx_twis_t const * p_instance) +NRFX_STATIC_INLINE size_t nrfx_twis_rx_amount(nrfx_twis_t const * p_instance) { return nrf_twis_rx_amount_get(p_instance->p_reg); } -#endif // SUPPRESS_INLINE_IMPLEMENTATION +#endif // NRFX_DECLARE_ONLY /** @} */ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_twis.h b/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_twis.h index c1c66ec98..45f295494 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_twis.h +++ b/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_twis.h @@ -1,41 +1,34 @@ -/** - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA - * +/* + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * 2. Redistributions in binary form, except as embedded into a Nordic - * Semiconductor ASA integrated circuit in a product or a software update for - * such product, must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef NRF_TWIS_H__ @@ -110,16 +103,6 @@ typedef enum NRF_TWIS_CONFIG_ADDRESS01_MASK = TWIS_CONFIG_ADDRESS0_Msk | TWIS_CONFIG_ADDRESS1_Msk /**< Enable both address matching. */ } nrf_twis_config_addr_mask_t; -/** - * @brief Variable type to hold the amount of data for EasyDMA. - * - * Variable of the minimum size that can hold the amount of data to transfer. - * - * @note Defined to make it simple to change if EasyDMA is updated to support more data in - * the future devices. - */ -typedef uint8_t nrf_twis_amount_t; - /** * @brief Smallest variable type to hold the TWI address. * @@ -130,14 +113,13 @@ typedef uint8_t nrf_twis_amount_t; */ typedef uint8_t nrf_twis_address_t; - /** * @brief Function for activating the specified TWIS task. * * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] task Task to be activated. */ -__STATIC_INLINE void nrf_twis_task_trigger(NRF_TWIS_Type * p_reg, nrf_twis_task_t task); +NRF_STATIC_INLINE void nrf_twis_task_trigger(NRF_TWIS_Type * p_reg, nrf_twis_task_t task); /** * @brief Function for returning the address of the specified TWIS task register. @@ -147,8 +129,8 @@ __STATIC_INLINE void nrf_twis_task_trigger(NRF_TWIS_Type * p_reg, nrf_twis_task_ * * @return Task address. */ -__STATIC_INLINE uint32_t nrf_twis_task_address_get(NRF_TWIS_Type const * p_reg, - nrf_twis_task_t task); +NRF_STATIC_INLINE uint32_t nrf_twis_task_address_get(NRF_TWIS_Type const * p_reg, + nrf_twis_task_t task); /** * @brief Function for clearing the specified event. @@ -156,8 +138,8 @@ __STATIC_INLINE uint32_t nrf_twis_task_address_get(NRF_TWIS_Type const * p_reg, * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] event The specified event. */ -__STATIC_INLINE void nrf_twis_event_clear(NRF_TWIS_Type * p_reg, - nrf_twis_event_t event); +NRF_STATIC_INLINE void nrf_twis_event_clear(NRF_TWIS_Type * p_reg, + nrf_twis_event_t event); /** * @brief Function for retrieving the state of the TWIS event. @@ -168,8 +150,8 @@ __STATIC_INLINE void nrf_twis_event_clear(NRF_TWIS_Type * p_reg, * @retval true The event has been generated. * @retval false The event has not been generated. */ -__STATIC_INLINE bool nrf_twis_event_check(NRF_TWIS_Type const * p_reg, - nrf_twis_event_t event); +NRF_STATIC_INLINE bool nrf_twis_event_check(NRF_TWIS_Type const * p_reg, + nrf_twis_event_t event); /** * @brief Function for getting and clearing the state of the specified event. @@ -182,8 +164,8 @@ __STATIC_INLINE bool nrf_twis_event_check(NRF_TWIS_Type const * p_reg, * @retval true The event was set. * @retval false The event was not set. */ -__STATIC_INLINE bool nrf_twis_event_get_and_clear(NRF_TWIS_Type * p_reg, - nrf_twis_event_t event); +NRF_STATIC_INLINE bool nrf_twis_event_get_and_clear(NRF_TWIS_Type * p_reg, + nrf_twis_event_t event); /** * @brief Function for returning the address of the specified TWIS event register. @@ -193,8 +175,8 @@ __STATIC_INLINE bool nrf_twis_event_get_and_clear(NRF_TWIS_Type * p_reg, * * @return Address. */ -__STATIC_INLINE uint32_t nrf_twis_event_address_get(NRF_TWIS_Type const * p_reg, - nrf_twis_event_t event); +NRF_STATIC_INLINE uint32_t nrf_twis_event_address_get(NRF_TWIS_Type const * p_reg, + nrf_twis_event_t event); /** * @brief Function for setting a shortcut. @@ -202,7 +184,7 @@ __STATIC_INLINE uint32_t nrf_twis_event_address_get(NRF_TWIS_Type const * p_reg, * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] mask Mask of shortcuts to be enabled. */ -__STATIC_INLINE void nrf_twis_shorts_enable(NRF_TWIS_Type * p_reg, uint32_t mask); +NRF_STATIC_INLINE void nrf_twis_shorts_enable(NRF_TWIS_Type * p_reg, uint32_t mask); /** * @brief Function for clearing shortcuts. @@ -210,7 +192,7 @@ __STATIC_INLINE void nrf_twis_shorts_enable(NRF_TWIS_Type * p_reg, uint32_t mask * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] mask Mask of shortcuts to be disabled. */ -__STATIC_INLINE void nrf_twis_shorts_disable(NRF_TWIS_Type * p_reg, uint32_t mask); +NRF_STATIC_INLINE void nrf_twis_shorts_disable(NRF_TWIS_Type * p_reg, uint32_t mask); /** * @brief Function for getting the shorts mask. @@ -221,7 +203,7 @@ __STATIC_INLINE void nrf_twis_shorts_disable(NRF_TWIS_Type * p_reg, uint32_t mas * * @return Flags of currently enabled shortcuts */ -__STATIC_INLINE uint32_t nrf_twis_shorts_get(NRF_TWIS_Type const * p_reg); +NRF_STATIC_INLINE uint32_t nrf_twis_shorts_get(NRF_TWIS_Type const * p_reg); /** * @brief Function for enabling the specified interrupts. @@ -229,18 +211,17 @@ __STATIC_INLINE uint32_t nrf_twis_shorts_get(NRF_TWIS_Type const * p_reg); * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] mask Mask of interrupts to be enabled. */ -__STATIC_INLINE void nrf_twis_int_enable(NRF_TWIS_Type * p_reg, uint32_t mask); +NRF_STATIC_INLINE void nrf_twis_int_enable(NRF_TWIS_Type * p_reg, uint32_t mask); /** - * @brief Function for retrieving the state of the specified interrupts. + * @brief Function for checking if the specified interrupts are enabled. * * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] mask Mask of interrupts to be checked. * - * @retval true Any of the specified interrupts is enabled. - * @retval false None of the specified interrupts is enabled. + * @return Mask of enabled interrupts. */ -__STATIC_INLINE bool nrf_twis_int_enable_check(NRF_TWIS_Type const * p_reg, uint32_t mask); +NRF_STATIC_INLINE uint32_t nrf_twis_int_enable_check(NRF_TWIS_Type const * p_reg, uint32_t mask); /** * @brief Function for disabling the specified interrupts. @@ -248,7 +229,7 @@ __STATIC_INLINE bool nrf_twis_int_enable_check(NRF_TWIS_Type const * p_reg, uint * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] mask Mask of interrupts to be disabled. */ -__STATIC_INLINE void nrf_twis_int_disable(NRF_TWIS_Type * p_reg, uint32_t mask); +NRF_STATIC_INLINE void nrf_twis_int_disable(NRF_TWIS_Type * p_reg, uint32_t mask); #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__) /** @@ -259,9 +240,9 @@ __STATIC_INLINE void nrf_twis_int_disable(NRF_TWIS_Type * p_reg, uint32_t mask); * @param[in] task Task for which to set the configuration. * @param[in] channel Channel through which to subscribe events. */ -__STATIC_INLINE void nrf_twis_subscribe_set(NRF_TWIS_Type * p_reg, - nrf_twis_task_t task, - uint8_t channel); +NRF_STATIC_INLINE void nrf_twis_subscribe_set(NRF_TWIS_Type * p_reg, + nrf_twis_task_t task, + uint8_t channel); /** * @brief Function for clearing the subscribe configuration for a given @@ -270,8 +251,8 @@ __STATIC_INLINE void nrf_twis_subscribe_set(NRF_TWIS_Type * p_reg, * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] task Task for which to clear the configuration. */ -__STATIC_INLINE void nrf_twis_subscribe_clear(NRF_TWIS_Type * p_reg, - nrf_twis_task_t task); +NRF_STATIC_INLINE void nrf_twis_subscribe_clear(NRF_TWIS_Type * p_reg, + nrf_twis_task_t task); /** * @brief Function for setting the publish configuration for a given @@ -281,9 +262,9 @@ __STATIC_INLINE void nrf_twis_subscribe_clear(NRF_TWIS_Type * p_reg, * @param[in] event Event for which to set the configuration. * @param[in] channel Channel through which to publish the event. */ -__STATIC_INLINE void nrf_twis_publish_set(NRF_TWIS_Type * p_reg, - nrf_twis_event_t event, - uint8_t channel); +NRF_STATIC_INLINE void nrf_twis_publish_set(NRF_TWIS_Type * p_reg, + nrf_twis_event_t event, + uint8_t channel); /** * @brief Function for clearing the publish configuration for a given @@ -292,8 +273,8 @@ __STATIC_INLINE void nrf_twis_publish_set(NRF_TWIS_Type * p_reg, * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] event Event for which to clear the configuration. */ -__STATIC_INLINE void nrf_twis_publish_clear(NRF_TWIS_Type * p_reg, - nrf_twis_event_t event); +NRF_STATIC_INLINE void nrf_twis_publish_clear(NRF_TWIS_Type * p_reg, + nrf_twis_event_t event); #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__) /** @@ -305,7 +286,7 @@ __STATIC_INLINE void nrf_twis_publish_clear(NRF_TWIS_Type * p_reg, * * @return Error source mask with values from @ref nrf_twis_error_t. */ -__STATIC_INLINE uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * const p_reg); +NRF_STATIC_INLINE uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * p_reg); /** * @brief Function for getting information about which of the addresses matched. @@ -317,21 +298,21 @@ __STATIC_INLINE uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * con * * @return Index of matched address. */ -__STATIC_INLINE uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_reg); +NRF_STATIC_INLINE uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_reg); /** * @brief Function for enabling TWIS. * * @param[in] p_reg Pointer to the structure of registers of the peripheral. */ -__STATIC_INLINE void nrf_twis_enable(NRF_TWIS_Type * p_reg); +NRF_STATIC_INLINE void nrf_twis_enable(NRF_TWIS_Type * p_reg); /** * @brief Function for disabling TWIS. * * @param[in] p_reg Pointer to the structure of registers of the peripheral. */ -__STATIC_INLINE void nrf_twis_disable(NRF_TWIS_Type * p_reg); +NRF_STATIC_INLINE void nrf_twis_disable(NRF_TWIS_Type * p_reg); /** * @brief Function for configuring TWIS pins. @@ -340,7 +321,25 @@ __STATIC_INLINE void nrf_twis_disable(NRF_TWIS_Type * p_reg); * @param[in] scl SCL pin number. * @param[in] sda SDA pin number. */ -__STATIC_INLINE void nrf_twis_pins_set(NRF_TWIS_Type * p_reg, uint32_t scl, uint32_t sda); +NRF_STATIC_INLINE void nrf_twis_pins_set(NRF_TWIS_Type * p_reg, uint32_t scl, uint32_t sda); + +/** + * @brief Function for retrieving the SCL pin selection. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return SCL pin selection. + */ +NRF_STATIC_INLINE uint32_t nrf_twis_scl_pin_get(NRF_TWIS_Type const * p_reg); + +/** + * @brief Function for retrieving the SDA pin selection. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return SDA pin selection. + */ +NRF_STATIC_INLINE uint32_t nrf_twis_sda_pin_get(NRF_TWIS_Type const * p_reg); /** * @brief Function for setting the receive buffer. @@ -349,9 +348,9 @@ __STATIC_INLINE void nrf_twis_pins_set(NRF_TWIS_Type * p_reg, uint32_t scl, uint * @param[in] p_buf Pointer to the buffer for received data. * @param[in] length Maximum number of data bytes to receive. */ -__STATIC_INLINE void nrf_twis_rx_buffer_set(NRF_TWIS_Type * p_reg, - uint8_t * p_buf, - size_t length); +NRF_STATIC_INLINE void nrf_twis_rx_buffer_set(NRF_TWIS_Type * p_reg, + uint8_t * p_buf, + size_t length); /** * @brief Function that prepares TWIS for receiving @@ -362,9 +361,9 @@ __STATIC_INLINE void nrf_twis_rx_buffer_set(NRF_TWIS_Type * p_reg, * @param[in] p_buf Pointer to the buffer for received data. * @param[in] length Maximum number of data bytes to receive. */ -__STATIC_INLINE void nrf_twis_rx_prepare(NRF_TWIS_Type * p_reg, - uint8_t * p_buf, - size_t length); +NRF_STATIC_INLINE void nrf_twis_rx_prepare(NRF_TWIS_Type * p_reg, + uint8_t * p_buf, + size_t length); /** * @brief Function for getting number of bytes received in the last transaction. @@ -373,7 +372,7 @@ __STATIC_INLINE void nrf_twis_rx_prepare(NRF_TWIS_Type * p_reg, * * @return Amount of bytes received. * */ -__STATIC_INLINE size_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * p_reg); +NRF_STATIC_INLINE size_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * p_reg); /** * @brief Function for setting the transmit buffer. @@ -382,9 +381,9 @@ __STATIC_INLINE size_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * p_reg); * @param[in] p_buf Pointer to the buffer with data to send. * @param[in] length Maximum number of data bytes to transmit. */ -__STATIC_INLINE void nrf_twis_tx_buffer_set(NRF_TWIS_Type * p_reg, - uint8_t const * p_buf, - size_t length); +NRF_STATIC_INLINE void nrf_twis_tx_buffer_set(NRF_TWIS_Type * p_reg, + uint8_t const * p_buf, + size_t length); /** * @brief Function for preparing TWIS for transmitting. @@ -395,9 +394,9 @@ __STATIC_INLINE void nrf_twis_tx_buffer_set(NRF_TWIS_Type * p_reg, * @param[in] p_buf Pointer to the buffer with data to send. * @param[in] length Maximum number of data bytes to transmit. */ -__STATIC_INLINE void nrf_twis_tx_prepare(NRF_TWIS_Type * p_reg, - uint8_t const * p_buf, - size_t length); +NRF_STATIC_INLINE void nrf_twis_tx_prepare(NRF_TWIS_Type * p_reg, + uint8_t const * p_buf, + size_t length); /** * @brief Function for getting the number of bytes transmitted in the last transaction. @@ -406,7 +405,7 @@ __STATIC_INLINE void nrf_twis_tx_prepare(NRF_TWIS_Type * p_reg, * * @return Amount of bytes transmitted. */ -__STATIC_INLINE size_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * p_reg); +NRF_STATIC_INLINE size_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * p_reg); /** * @brief Function for setting the slave address. @@ -420,9 +419,9 @@ __STATIC_INLINE size_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * p_reg); * @sa nrf_twis_config_address_set * @sa nrf_twis_config_address_get */ -__STATIC_INLINE void nrf_twis_address_set(NRF_TWIS_Type * p_reg, - uint_fast8_t n, - nrf_twis_address_t addr); +NRF_STATIC_INLINE void nrf_twis_address_set(NRF_TWIS_Type * p_reg, + uint_fast8_t n, + nrf_twis_address_t addr); /** * @brief Function for retrieving configured slave address. @@ -434,8 +433,8 @@ __STATIC_INLINE void nrf_twis_address_set(NRF_TWIS_Type * p_reg, * * @return Configured slave address. */ -__STATIC_INLINE nrf_twis_address_t nrf_twis_address_get(NRF_TWIS_Type const * p_reg, - uint_fast8_t n); +NRF_STATIC_INLINE nrf_twis_address_t nrf_twis_address_get(NRF_TWIS_Type const * p_reg, + uint_fast8_t n); /** * @brief Function for setting the device address configuration. @@ -445,8 +444,8 @@ __STATIC_INLINE nrf_twis_address_t nrf_twis_address_get(NRF_TWIS_Type const * p_ * * @sa nrf_twis_address_set */ -__STATIC_INLINE void nrf_twis_config_address_set(NRF_TWIS_Type * p_reg, - nrf_twis_config_addr_mask_t addr_mask); +NRF_STATIC_INLINE void nrf_twis_config_address_set(NRF_TWIS_Type * p_reg, + nrf_twis_config_addr_mask_t addr_mask); /** * @brief Function for retrieving the device address configuration. @@ -455,7 +454,7 @@ __STATIC_INLINE void nrf_twis_config_address_set(NRF_TWIS_Type * p_r * * @return Mask of address indexes of what device should answer to. */ -__STATIC_INLINE nrf_twis_config_addr_mask_t nrf_twis_config_address_get( +NRF_STATIC_INLINE nrf_twis_config_addr_mask_t nrf_twis_config_address_get( NRF_TWIS_Type const * p_reg); /** @@ -465,8 +464,8 @@ __STATIC_INLINE nrf_twis_config_addr_mask_t nrf_twis_config_address_get( * @param[in] orc Over-read character. Character clocked out in case of * over-read of the TXD buffer. */ -__STATIC_INLINE void nrf_twis_orc_set(NRF_TWIS_Type * p_reg, - uint8_t orc); +NRF_STATIC_INLINE void nrf_twis_orc_set(NRF_TWIS_Type * p_reg, + uint8_t orc); /** * @brief Function for setting the over-read character. @@ -475,12 +474,43 @@ __STATIC_INLINE void nrf_twis_orc_set(NRF_TWIS_Type * p_reg, * * @return Over-read character configured for selected instance. */ -__STATIC_INLINE uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * p_reg); +NRF_STATIC_INLINE uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * p_reg); +#if defined(TWIS_TXD_LIST_LIST_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for enabling the TX list feature. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + */ +NRF_STATIC_INLINE void nrf_twis_tx_list_enable(NRF_TWIS_Type * p_reg); + +/** + * @brief Function for disabling the TX list feature. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + */ +NRF_STATIC_INLINE void nrf_twis_tx_list_disable(NRF_TWIS_Type * p_reg); +#endif // defined(TWIS_TXD_LIST_LIST_Msk) || defined(__NRFX_DOXYGEN__) + +#if defined(TWIS_RXD_LIST_LIST_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for enabling the RX list feature. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + */ +NRF_STATIC_INLINE void nrf_twis_rx_list_enable(NRF_TWIS_Type * p_reg); + +/** + * @brief Function for disabling the RX list feature. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + */ +NRF_STATIC_INLINE void nrf_twis_rx_list_disable(NRF_TWIS_Type * p_reg); +#endif // defined(TWIS_RXD_LIST_LIST_Msk) || defined(__NRFX_DOXYGEN__) /** @} */ /* End of nrf_twis_hal */ -#ifndef SUPPRESS_INLINE_IMPLEMENTATION +#ifndef NRF_DECLARE_ONLY /* ------------------------------------------------------------------------------------------------ * Internal functions @@ -496,7 +526,7 @@ __STATIC_INLINE uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * p_reg); * @attention Offset must be modulo 4 value. In other case, hardware fault can occur. * @return Pointer to the register. */ -__STATIC_INLINE volatile uint32_t* nrf_twis_getRegPtr(NRF_TWIS_Type const * p_reg, uint32_t offset) +NRF_STATIC_INLINE volatile uint32_t* nrf_twis_getRegPtr(NRF_TWIS_Type * p_reg, uint32_t offset) { return (volatile uint32_t*)((uint8_t *)p_reg + (uint32_t)offset); } @@ -511,8 +541,8 @@ __STATIC_INLINE volatile uint32_t* nrf_twis_getRegPtr(NRF_TWIS_Type const * p_re * @attention Offset must be modulo 4 value. In other case, hardware fault can occur. * @return Pointer to the register. */ -__STATIC_INLINE volatile const uint32_t* nrf_twis_getRegPtr_c(NRF_TWIS_Type const * p_reg, - uint32_t offset) +NRF_STATIC_INLINE volatile const uint32_t* nrf_twis_getRegPtr_c(NRF_TWIS_Type const * p_reg, + uint32_t offset) { return (volatile const uint32_t*)((uint8_t *)p_reg + (uint32_t)offset); } @@ -523,32 +553,29 @@ __STATIC_INLINE volatile const uint32_t* nrf_twis_getRegPtr_c(NRF_TWIS_Type cons */ -__STATIC_INLINE void nrf_twis_task_trigger(NRF_TWIS_Type * p_reg, nrf_twis_task_t task) +NRF_STATIC_INLINE void nrf_twis_task_trigger(NRF_TWIS_Type * p_reg, nrf_twis_task_t task) { *(nrf_twis_getRegPtr(p_reg, (uint32_t)task)) = 1UL; } -__STATIC_INLINE uint32_t nrf_twis_task_address_get(NRF_TWIS_Type const * p_reg, - nrf_twis_task_t task) +NRF_STATIC_INLINE uint32_t nrf_twis_task_address_get(NRF_TWIS_Type const * p_reg, + nrf_twis_task_t task) { return (uint32_t)nrf_twis_getRegPtr_c(p_reg, (uint32_t)task); } -__STATIC_INLINE void nrf_twis_event_clear(NRF_TWIS_Type * p_reg, nrf_twis_event_t event) +NRF_STATIC_INLINE void nrf_twis_event_clear(NRF_TWIS_Type * p_reg, nrf_twis_event_t event) { *(nrf_twis_getRegPtr(p_reg, (uint32_t)event)) = 0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } -__STATIC_INLINE bool nrf_twis_event_check(NRF_TWIS_Type const * p_reg, nrf_twis_event_t event) +NRF_STATIC_INLINE bool nrf_twis_event_check(NRF_TWIS_Type const * p_reg, nrf_twis_event_t event) { return (bool)*nrf_twis_getRegPtr_c(p_reg, (uint32_t)event); } -__STATIC_INLINE bool nrf_twis_event_get_and_clear(NRF_TWIS_Type * p_reg, nrf_twis_event_t event) +NRF_STATIC_INLINE bool nrf_twis_event_get_and_clear(NRF_TWIS_Type * p_reg, nrf_twis_event_t event) { bool ret = nrf_twis_event_check(p_reg, event); if (ret) @@ -558,18 +585,18 @@ __STATIC_INLINE bool nrf_twis_event_get_and_clear(NRF_TWIS_Type * p_reg, nrf_tw return ret; } -__STATIC_INLINE uint32_t nrf_twis_event_address_get(NRF_TWIS_Type const * p_reg, - nrf_twis_event_t event) +NRF_STATIC_INLINE uint32_t nrf_twis_event_address_get(NRF_TWIS_Type const * p_reg, + nrf_twis_event_t event) { return (uint32_t)nrf_twis_getRegPtr_c(p_reg, (uint32_t)event); } -__STATIC_INLINE void nrf_twis_shorts_enable(NRF_TWIS_Type * p_reg, uint32_t mask) +NRF_STATIC_INLINE void nrf_twis_shorts_enable(NRF_TWIS_Type * p_reg, uint32_t mask) { p_reg->SHORTS |= mask; } -__STATIC_INLINE void nrf_twis_shorts_disable(NRF_TWIS_Type * p_reg, uint32_t mask) +NRF_STATIC_INLINE void nrf_twis_shorts_disable(NRF_TWIS_Type * p_reg, uint32_t mask) { if (~0U == mask) { @@ -582,160 +609,197 @@ __STATIC_INLINE void nrf_twis_shorts_disable(NRF_TWIS_Type * p_reg, uint32_t mas } } -__STATIC_INLINE uint32_t nrf_twis_shorts_get(NRF_TWIS_Type const * p_reg) +NRF_STATIC_INLINE uint32_t nrf_twis_shorts_get(NRF_TWIS_Type const * p_reg) { return p_reg->SHORTS; } -__STATIC_INLINE void nrf_twis_int_enable(NRF_TWIS_Type * p_reg, uint32_t mask) +NRF_STATIC_INLINE void nrf_twis_int_enable(NRF_TWIS_Type * p_reg, uint32_t mask) { p_reg->INTENSET = mask; } -__STATIC_INLINE bool nrf_twis_int_enable_check(NRF_TWIS_Type const * p_reg, uint32_t mask) +NRF_STATIC_INLINE uint32_t nrf_twis_int_enable_check(NRF_TWIS_Type const * p_reg, uint32_t mask) { - return (bool)(p_reg->INTENSET & mask); + return p_reg->INTENSET & mask; } -__STATIC_INLINE void nrf_twis_int_disable(NRF_TWIS_Type * const p_reg, uint32_t mask) +NRF_STATIC_INLINE void nrf_twis_int_disable(NRF_TWIS_Type * p_reg, uint32_t mask) { p_reg->INTENCLR = mask; } #if defined(DPPI_PRESENT) -__STATIC_INLINE void nrf_twis_subscribe_set(NRF_TWIS_Type * p_reg, - nrf_twis_task_t task, - uint8_t channel) +NRF_STATIC_INLINE void nrf_twis_subscribe_set(NRF_TWIS_Type * p_reg, + nrf_twis_task_t task, + uint8_t channel) { *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = ((uint32_t)channel | TWIS_SUBSCRIBE_STOP_EN_Msk); } -__STATIC_INLINE void nrf_twis_subscribe_clear(NRF_TWIS_Type * p_reg, - nrf_twis_task_t task) +NRF_STATIC_INLINE void nrf_twis_subscribe_clear(NRF_TWIS_Type * p_reg, + nrf_twis_task_t task) { *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0; } -__STATIC_INLINE void nrf_twis_publish_set(NRF_TWIS_Type * p_reg, - nrf_twis_event_t event, - uint8_t channel) +NRF_STATIC_INLINE void nrf_twis_publish_set(NRF_TWIS_Type * p_reg, + nrf_twis_event_t event, + uint8_t channel) { *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = ((uint32_t)channel | TWIS_PUBLISH_STOPPED_EN_Msk); } -__STATIC_INLINE void nrf_twis_publish_clear(NRF_TWIS_Type * p_reg, - nrf_twis_event_t event) +NRF_STATIC_INLINE void nrf_twis_publish_clear(NRF_TWIS_Type * p_reg, + nrf_twis_event_t event) { *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0; } #endif // defined(DPPI_PRESENT) -__STATIC_INLINE uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * p_reg) +NRF_STATIC_INLINE uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * p_reg) { uint32_t ret = p_reg->ERRORSRC; p_reg->ERRORSRC = ret; return ret; } -__STATIC_INLINE uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_reg) +NRF_STATIC_INLINE uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_reg) { return (uint_fast8_t)p_reg->MATCH; } -__STATIC_INLINE void nrf_twis_enable(NRF_TWIS_Type * p_reg) +NRF_STATIC_INLINE void nrf_twis_enable(NRF_TWIS_Type * p_reg) { p_reg->ENABLE = (TWIS_ENABLE_ENABLE_Enabled << TWIS_ENABLE_ENABLE_Pos); } -__STATIC_INLINE void nrf_twis_disable(NRF_TWIS_Type * p_reg) +NRF_STATIC_INLINE void nrf_twis_disable(NRF_TWIS_Type * p_reg) { p_reg->ENABLE = (TWIS_ENABLE_ENABLE_Disabled << TWIS_ENABLE_ENABLE_Pos); } -__STATIC_INLINE void nrf_twis_pins_set(NRF_TWIS_Type * p_reg, uint32_t scl, uint32_t sda) +NRF_STATIC_INLINE void nrf_twis_pins_set(NRF_TWIS_Type * p_reg, uint32_t scl, uint32_t sda) { p_reg->PSEL.SCL = scl; p_reg->PSEL.SDA = sda; } -__STATIC_INLINE void nrf_twis_rx_buffer_set(NRF_TWIS_Type * p_reg, - uint8_t * p_buf, - size_t length) +NRF_STATIC_INLINE uint32_t nrf_twis_scl_pin_get(NRF_TWIS_Type const * p_reg) +{ + return p_reg->PSEL.SCL; +} + +NRF_STATIC_INLINE uint32_t nrf_twis_sda_pin_get(NRF_TWIS_Type const * p_reg) +{ + return p_reg->PSEL.SDA; +} + +NRF_STATIC_INLINE void nrf_twis_rx_buffer_set(NRF_TWIS_Type * p_reg, + uint8_t * p_buf, + size_t length) { p_reg->RXD.PTR = (uint32_t)p_buf; p_reg->RXD.MAXCNT = length; } -__STATIC_INLINE void nrf_twis_rx_prepare(NRF_TWIS_Type * p_reg, - uint8_t * p_buf, - size_t length) +NRF_STATIC_INLINE void nrf_twis_rx_prepare(NRF_TWIS_Type * p_reg, + uint8_t * p_buf, + size_t length) { nrf_twis_rx_buffer_set(p_reg, p_buf, length); nrf_twis_task_trigger(p_reg, NRF_TWIS_TASK_PREPARERX); } -__STATIC_INLINE size_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * p_reg) +NRF_STATIC_INLINE size_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * p_reg) { return p_reg->RXD.AMOUNT; } -__STATIC_INLINE void nrf_twis_tx_buffer_set(NRF_TWIS_Type * p_reg, - uint8_t const * p_buf, - size_t length) +NRF_STATIC_INLINE void nrf_twis_tx_buffer_set(NRF_TWIS_Type * p_reg, + uint8_t const * p_buf, + size_t length) { p_reg->TXD.PTR = (uint32_t)p_buf; p_reg->TXD.MAXCNT = length; } -__STATIC_INLINE void nrf_twis_tx_prepare(NRF_TWIS_Type * p_reg, - uint8_t const * p_buf, - size_t length) +NRF_STATIC_INLINE void nrf_twis_tx_prepare(NRF_TWIS_Type * p_reg, + uint8_t const * p_buf, + size_t length) { nrf_twis_tx_buffer_set(p_reg, p_buf, length); nrf_twis_task_trigger(p_reg, NRF_TWIS_TASK_PREPARETX); } -__STATIC_INLINE size_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * p_reg) +NRF_STATIC_INLINE size_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * p_reg) { return p_reg->TXD.AMOUNT; } -__STATIC_INLINE void nrf_twis_address_set(NRF_TWIS_Type * p_reg, - uint_fast8_t n, - nrf_twis_address_t addr) +NRF_STATIC_INLINE void nrf_twis_address_set(NRF_TWIS_Type * p_reg, + uint_fast8_t n, + nrf_twis_address_t addr) { p_reg->ADDRESS[n] = addr; } -__STATIC_INLINE nrf_twis_address_t nrf_twis_address_get(NRF_TWIS_Type const * p_reg, uint_fast8_t n) +NRF_STATIC_INLINE nrf_twis_address_t nrf_twis_address_get(NRF_TWIS_Type const * p_reg, + uint_fast8_t n) { return (nrf_twis_address_t)p_reg->ADDRESS[n]; } -__STATIC_INLINE void nrf_twis_config_address_set(NRF_TWIS_Type * p_reg, - nrf_twis_config_addr_mask_t addr_mask) +NRF_STATIC_INLINE void nrf_twis_config_address_set(NRF_TWIS_Type * p_reg, + nrf_twis_config_addr_mask_t addr_mask) { /* This is the only configuration in TWIS - just write it without masking */ p_reg->CONFIG = addr_mask; } -__STATIC_INLINE nrf_twis_config_addr_mask_t nrf_twis_config_address_get(NRF_TWIS_Type const * p_reg) +NRF_STATIC_INLINE nrf_twis_config_addr_mask_t nrf_twis_config_address_get( + NRF_TWIS_Type const * p_reg) { return (nrf_twis_config_addr_mask_t)(p_reg->CONFIG & TWIS_ADDRESS_ADDRESS_Msk); } -__STATIC_INLINE void nrf_twis_orc_set(NRF_TWIS_Type * p_reg, uint8_t orc) +NRF_STATIC_INLINE void nrf_twis_orc_set(NRF_TWIS_Type * p_reg, uint8_t orc) { p_reg->ORC = orc; } -__STATIC_INLINE uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * p_reg) +NRF_STATIC_INLINE uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * p_reg) { return (uint8_t)p_reg->ORC; } -#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ +#if defined(TWIS_TXD_LIST_LIST_Msk) +NRF_STATIC_INLINE void nrf_twis_tx_list_enable(NRF_TWIS_Type * p_reg) +{ + p_reg->TXD.LIST = TWIS_TXD_LIST_LIST_ArrayList << TWIS_TXD_LIST_LIST_Pos; +} + +NRF_STATIC_INLINE void nrf_twis_tx_list_disable(NRF_TWIS_Type * p_reg) +{ + p_reg->TXD.LIST = TWIS_TXD_LIST_LIST_Disabled << TWIS_TXD_LIST_LIST_Pos; +} + +#endif // defined(TWIS_TXD_LIST_LIST_Msk) + +#if defined(TWIS_RXD_LIST_LIST_Msk) +NRF_STATIC_INLINE void nrf_twis_rx_list_enable(NRF_TWIS_Type * p_reg) +{ + p_reg->RXD.LIST = TWIS_RXD_LIST_LIST_ArrayList << TWIS_RXD_LIST_LIST_Pos; +} + +NRF_STATIC_INLINE void nrf_twis_rx_list_disable(NRF_TWIS_Type * p_reg) +{ + p_reg->RXD.LIST = TWIS_RXD_LIST_LIST_Disabled << TWIS_RXD_LIST_LIST_Pos; +} +#endif // defined(TWIS_RXD_LIST_LIST_Msk) + +#endif /* NRF_DECLARE_ONLY */ #ifdef __cplusplus diff --git a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config.h b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h similarity index 96% rename from source/hic_hal/nordic/nrf52820/nrfx/nrfx_config.h rename to source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h index 8b39f4fd2..c525ced2b 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config.h +++ b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h @@ -1,5 +1,42 @@ +/* + * Copyright (c) 2020 - 2021, Nordic Semiconductor ASA + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_CONFIG_NRF52820_H__ +#define NRFX_CONFIG_NRF52820_H__ + #ifndef NRFX_CONFIG_H__ -#define NRFX_CONFIG_H__ +#error "This file should not be included directly. Include nrfx_config.h instead." +#endif // <<< Use Configuration Wizard in Context Menu >>>\n @@ -2242,4 +2279,4 @@ // -#endif // NRFX_CONFIG_H__ +#endif // NRFX_CONFIG_NRF52820_H__ diff --git a/source/hic_hal/nordic/nrf52820/nrfx_config.h b/source/hic_hal/nordic/nrf52820/nrfx_config.h new file mode 100644 index 000000000..dccf675dc --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx_config.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_CONFIG_H__ +#define NRFX_CONFIG_H__ + +#if defined(NRF51) + #include +#elif defined(NRF52805_XXAA) + #include +#elif defined(NRF52810_XXAA) + #include +#elif defined(NRF52811_XXAA) + #include +#elif defined(NRF52820_XXAA) + #include +#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB) + #include +#elif defined(NRF52833_XXAA) + #include +#elif defined(NRF52840_XXAA) + #include +#elif defined(NRF5340_XXAA_APPLICATION) + #include +#elif defined(NRF5340_XXAA_NETWORK) + #include +#elif defined(NRF9160_XXAA) + #include +#else + #error "Unknown device." +#endif + +#endif // NRFX_CONFIG_H__ From f966882429a8633adcc99a9ed0223a063fbd8d02 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 30 Sep 2021 23:10:44 -0500 Subject: [PATCH 449/617] nrf52820_hic: configuration clean-ups after nrfx update nrfx_config_nrf52820.h is converging with default template and reflect usage through nrfx --- records/hic_hal/nrf52820.yaml | 2 - .../nordic/nrf52820/{ => nrfx}/nrfx_config.h | 0 .../nrf52820/nrfx/nrfx_config_nrf52820.h | 771 ++++-------------- 3 files changed, 143 insertions(+), 630 deletions(-) rename source/hic_hal/nordic/nrf52820/{ => nrfx}/nrfx_config.h (100%) diff --git a/records/hic_hal/nrf52820.yaml b/records/hic_hal/nrf52820.yaml index d4c5447e4..a91ff3801 100644 --- a/records/hic_hal/nrf52820.yaml +++ b/records/hic_hal/nrf52820.yaml @@ -21,9 +21,7 @@ common: hic_hal: - source/hic_hal/nordic/nrf52820 - source/hic_hal/nordic/nrf52820/cmsis - - source/hic_hal/nordic/nrf52820/nrfx - source/hic_hal/nordic/nrf52820/nrfx/drivers - - source/hic_hal/nordic/nrf52820/nrfx/hal tool_specific: uvision: diff --git a/source/hic_hal/nordic/nrf52820/nrfx_config.h b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config.h similarity index 100% rename from source/hic_hal/nordic/nrf52820/nrfx_config.h rename to source/hic_hal/nordic/nrf52820/nrfx/nrfx_config.h diff --git a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h index c525ced2b..c4d5e53dc 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h +++ b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h @@ -45,7 +45,7 @@ // NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver //========================================================== #ifndef NRFX_CLOCK_ENABLED -#define NRFX_CLOCK_ENABLED 1 +#define NRFX_CLOCK_ENABLED 0 #endif // NRFX_CLOCK_CONFIG_LF_SRC - LF Clock Source @@ -65,7 +65,18 @@ #define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 #endif -// NRFX_CLOCK_CONFIG_IRQ_PRIORITY - Interrupt priority +// NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure + +// If set to a non-zero value, LFRC will be started before LFXO and corresponding +// event will be generated. It means that CPU will be woken up when LFRC +// oscillator starts, but user callback will be invoked only after LFXO +// finally starts. + +#ifndef NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED +#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 0 +#endif + +// NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority // <0=> 0 (highest) // <1=> 1 @@ -76,8 +87,8 @@ // <6=> 6 // <7=> 7 -#ifndef NRFX_CLOCK_CONFIG_IRQ_PRIORITY -#define NRFX_CLOCK_CONFIG_IRQ_PRIORITY 7 +#ifndef NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7 #endif // NRFX_CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module. @@ -136,75 +147,10 @@ // NRFX_COMP_ENABLED - nrfx_comp - COMP peripheral driver //========================================================== #ifndef NRFX_COMP_ENABLED -#define NRFX_COMP_ENABLED 1 -#endif -// NRFX_COMP_CONFIG_REF - Reference voltage - -// <0=> Internal 1.2V -// <1=> Internal 1.8V -// <2=> Internal 2.4V -// <4=> VDD -// <7=> ARef - -#ifndef NRFX_COMP_CONFIG_REF -#define NRFX_COMP_CONFIG_REF 1 -#endif - -// NRFX_COMP_CONFIG_MAIN_MODE - Main mode - -// <0=> Single ended -// <1=> Differential - -#ifndef NRFX_COMP_CONFIG_MAIN_MODE -#define NRFX_COMP_CONFIG_MAIN_MODE 0 -#endif - -// NRFX_COMP_CONFIG_SPEED_MODE - Speed mode - -// <0=> Low power -// <1=> Normal -// <2=> High speed - -#ifndef NRFX_COMP_CONFIG_SPEED_MODE -#define NRFX_COMP_CONFIG_SPEED_MODE 2 -#endif - -// NRFX_COMP_CONFIG_HYST - Hystheresis - -// <0=> No -// <1=> 50mV - -#ifndef NRFX_COMP_CONFIG_HYST -#define NRFX_COMP_CONFIG_HYST 0 -#endif - -// NRFX_COMP_CONFIG_ISOURCE - Current Source - -// <0=> Off -// <1=> 2.5 uA -// <2=> 5 uA -// <3=> 10 uA - -#ifndef NRFX_COMP_CONFIG_ISOURCE -#define NRFX_COMP_CONFIG_ISOURCE 0 +#define NRFX_COMP_ENABLED 0 #endif -// NRFX_COMP_CONFIG_INPUT - Analog input - -// <0=> 0 -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 - -#ifndef NRFX_COMP_CONFIG_INPUT -#define NRFX_COMP_CONFIG_INPUT 0 -#endif - -// NRFX_COMP_CONFIG_IRQ_PRIORITY - Interrupt priority +// NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority // <0=> 0 (highest) // <1=> 1 @@ -215,8 +161,8 @@ // <6=> 6 // <7=> 7 -#ifndef NRFX_COMP_CONFIG_IRQ_PRIORITY -#define NRFX_COMP_CONFIG_IRQ_PRIORITY 7 +#ifndef NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY 7 #endif // NRFX_COMP_CONFIG_LOG_ENABLED - Enables logging in the module. @@ -272,17 +218,76 @@ // +// NRFX_EGU_ENABLED - nrfx_egu - EGU peripheral driver. +//========================================================== +#ifndef NRFX_EGU_ENABLED +#define NRFX_EGU_ENABLED 0 +#endif + +// NRFX_EGU0_ENABLED - Enable EGU0 instance. + +#ifndef NRFX_EGU0_ENABLED +#define NRFX_EGU0_ENABLED 0 +#endif + +// NRFX_EGU1_ENABLED - Enable EGU1 instance. + +#ifndef NRFX_EGU1_ENABLED +#define NRFX_EGU1_ENABLED 0 +#endif + +// NRFX_EGU2_ENABLED - Enable EGU2 instance. + +#ifndef NRFX_EGU2_ENABLED +#define NRFX_EGU2_ENABLED 0 +#endif + +// NRFX_EGU3_ENABLED - Enable EGU3 instance. + +#ifndef NRFX_EGU3_ENABLED +#define NRFX_EGU3_ENABLED 0 +#endif + +// NRFX_EGU4_ENABLED - Enable EGU4 instance. + +#ifndef NRFX_EGU4_ENABLED +#define NRFX_EGU4_ENABLED 0 +#endif + +// NRFX_EGU5_ENABLED - Enable EGU5 instance. + +#ifndef NRFX_EGU5_ENABLED +#define NRFX_EGU5_ENABLED 0 +#endif + +// NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// + // NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver //========================================================== #ifndef NRFX_GPIOTE_ENABLED -#define NRFX_GPIOTE_ENABLED 1 +#define NRFX_GPIOTE_ENABLED 0 #endif // NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins #ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS #define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 #endif -// NRFX_GPIOTE_CONFIG_IRQ_PRIORITY - Interrupt priority +// NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority // <0=> 0 (highest) // <1=> 1 @@ -293,8 +298,8 @@ // <6=> 6 // <7=> 7 -#ifndef NRFX_GPIOTE_CONFIG_IRQ_PRIORITY -#define NRFX_GPIOTE_CONFIG_IRQ_PRIORITY 7 +#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY 7 #endif // NRFX_GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module. @@ -350,63 +355,10 @@ // -// NRFX_I2S_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_I2S_CONFIG_LOG_ENABLED -#define NRFX_I2S_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_I2S_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_I2S_CONFIG_LOG_LEVEL -#define NRFX_I2S_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_I2S_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_I2S_CONFIG_INFO_COLOR -#define NRFX_I2S_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_I2S_CONFIG_DEBUG_COLOR -#define NRFX_I2S_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - // NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver //========================================================== #ifndef NRFX_NVMC_ENABLED -#define NRFX_NVMC_ENABLED 1 +#define NRFX_NVMC_ENABLED 0 #endif // @@ -414,9 +366,9 @@ // NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver //========================================================== #ifndef NRFX_POWER_ENABLED -#define NRFX_POWER_ENABLED 1 +#define NRFX_POWER_ENABLED 0 #endif -// NRFX_POWER_CONFIG_IRQ_PRIORITY - Interrupt priority +// NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority // <0=> 0 (highest) // <1=> 1 @@ -427,26 +379,8 @@ // <6=> 6 // <7=> 7 -#ifndef NRFX_POWER_CONFIG_IRQ_PRIORITY -#define NRFX_POWER_CONFIG_IRQ_PRIORITY 7 -#endif - -// NRFX_POWER_CONFIG_DEFAULT_DCDCEN - The default configuration of main DCDC regulator - - -// This settings means only that components for DCDC regulator are installed and it can be enabled. - -#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCEN -#define NRFX_POWER_CONFIG_DEFAULT_DCDCEN 0 -#endif - -// NRFX_POWER_CONFIG_DEFAULT_DCDCENHV - The default configuration of High Voltage DCDC regulator - - -// This settings means only that components for DCDC regulator are installed and it can be enabled. - -#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCENHV -#define NRFX_POWER_CONFIG_DEFAULT_DCDCENHV 0 +#ifndef NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7 #endif // @@ -454,7 +388,7 @@ // NRFX_PPI_ENABLED - nrfx_ppi - PPI peripheral allocator //========================================================== #ifndef NRFX_PPI_ENABLED -#define NRFX_PPI_ENABLED 1 +#define NRFX_PPI_ENABLED 0 #endif // NRFX_PPI_CONFIG_LOG_ENABLED - Enables logging in the module. //========================================================== @@ -518,21 +452,21 @@ #ifndef NRFX_PRS_BOX_0_ENABLED -#define NRFX_PRS_BOX_0_ENABLED 1 +#define NRFX_PRS_BOX_0_ENABLED 0 #endif // NRFX_PRS_BOX_1_ENABLED - Enables box 1 in the module. #ifndef NRFX_PRS_BOX_1_ENABLED -#define NRFX_PRS_BOX_1_ENABLED 1 +#define NRFX_PRS_BOX_1_ENABLED 0 #endif // NRFX_PRS_BOX_2_ENABLED - Enables box 2 in the module. #ifndef NRFX_PRS_BOX_2_ENABLED -#define NRFX_PRS_BOX_2_ENABLED 1 +#define NRFX_PRS_BOX_2_ENABLED 0 #endif // NRFX_PRS_CONFIG_LOG_ENABLED - Enables logging in the module. @@ -591,88 +525,10 @@ // NRFX_QDEC_ENABLED - nrfx_qdec - QDEC peripheral driver //========================================================== #ifndef NRFX_QDEC_ENABLED -#define NRFX_QDEC_ENABLED 1 -#endif -// NRFX_QDEC_CONFIG_REPORTPER - Report period - -// <0=> 10 Samples -// <1=> 40 Samples -// <2=> 80 Samples -// <3=> 120 Samples -// <4=> 160 Samples -// <5=> 200 Samples -// <6=> 240 Samples -// <7=> 280 Samples - -#ifndef NRFX_QDEC_CONFIG_REPORTPER -#define NRFX_QDEC_CONFIG_REPORTPER 0 -#endif - -// NRFX_QDEC_CONFIG_SAMPLEPER - Sample period - -// <0=> 128 us -// <1=> 256 us -// <2=> 512 us -// <3=> 1024 us -// <4=> 2048 us -// <5=> 4096 us -// <6=> 8192 us -// <7=> 16384 us - -#ifndef NRFX_QDEC_CONFIG_SAMPLEPER -#define NRFX_QDEC_CONFIG_SAMPLEPER 7 -#endif - -// NRFX_QDEC_CONFIG_PIO_A - A pin <0-31> - - -#ifndef NRFX_QDEC_CONFIG_PIO_A -#define NRFX_QDEC_CONFIG_PIO_A 31 -#endif - -// NRFX_QDEC_CONFIG_PIO_B - B pin <0-31> - - -#ifndef NRFX_QDEC_CONFIG_PIO_B -#define NRFX_QDEC_CONFIG_PIO_B 31 -#endif - -// NRFX_QDEC_CONFIG_PIO_LED - LED pin <0-31> - - -#ifndef NRFX_QDEC_CONFIG_PIO_LED -#define NRFX_QDEC_CONFIG_PIO_LED 31 -#endif - -// NRFX_QDEC_CONFIG_LEDPRE - LED pre -#ifndef NRFX_QDEC_CONFIG_LEDPRE -#define NRFX_QDEC_CONFIG_LEDPRE 511 -#endif - -// NRFX_QDEC_CONFIG_LEDPOL - LED polarity - -// <0=> Active low -// <1=> Active high - -#ifndef NRFX_QDEC_CONFIG_LEDPOL -#define NRFX_QDEC_CONFIG_LEDPOL 1 +#define NRFX_QDEC_ENABLED 0 #endif -// NRFX_QDEC_CONFIG_DBFEN - Debouncing enable - - -#ifndef NRFX_QDEC_CONFIG_DBFEN -#define NRFX_QDEC_CONFIG_DBFEN 0 -#endif - -// NRFX_QDEC_CONFIG_SAMPLE_INTEN - Sample ready interrupt enable - - -#ifndef NRFX_QDEC_CONFIG_SAMPLE_INTEN -#define NRFX_QDEC_CONFIG_SAMPLE_INTEN 0 -#endif - -// NRFX_QDEC_CONFIG_IRQ_PRIORITY - Interrupt priority +// NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority // <0=> 0 (highest) // <1=> 1 @@ -683,8 +539,8 @@ // <6=> 6 // <7=> 7 -#ifndef NRFX_QDEC_CONFIG_IRQ_PRIORITY -#define NRFX_QDEC_CONFIG_IRQ_PRIORITY 7 +#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY 7 #endif // NRFX_QDEC_CONFIG_LOG_ENABLED - Enables logging in the module. @@ -743,16 +599,10 @@ // NRFX_RNG_ENABLED - nrfx_rng - RNG peripheral driver //========================================================== #ifndef NRFX_RNG_ENABLED -#define NRFX_RNG_ENABLED 1 -#endif -// NRFX_RNG_CONFIG_ERROR_CORRECTION - Error correction - - -#ifndef NRFX_RNG_CONFIG_ERROR_CORRECTION -#define NRFX_RNG_CONFIG_ERROR_CORRECTION 1 +#define NRFX_RNG_ENABLED 0 #endif -// NRFX_RNG_CONFIG_IRQ_PRIORITY - Interrupt priority +// NRFX_RNG_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority // <0=> 0 (highest) // <1=> 1 @@ -763,8 +613,8 @@ // <6=> 6 // <7=> 7 -#ifndef NRFX_RNG_CONFIG_IRQ_PRIORITY -#define NRFX_RNG_CONFIG_IRQ_PRIORITY 7 +#ifndef NRFX_RNG_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_RNG_DEFAULT_CONFIG_IRQ_PRIORITY 7 #endif // NRFX_RNG_CONFIG_LOG_ENABLED - Enables logging in the module. @@ -823,40 +673,18 @@ // NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver //========================================================== #ifndef NRFX_RTC_ENABLED -#define NRFX_RTC_ENABLED 1 +#define NRFX_RTC_ENABLED 0 #endif // NRFX_RTC0_ENABLED - Enable RTC0 instance - #ifndef NRFX_RTC0_ENABLED -#define NRFX_RTC0_ENABLED 1 +#define NRFX_RTC0_ENABLED 0 #endif // NRFX_RTC1_ENABLED - Enable RTC1 instance - #ifndef NRFX_RTC1_ENABLED -#define NRFX_RTC1_ENABLED 1 -#endif - - -// NRFX_RTC_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt -#ifndef NRFX_RTC_MAXIMUM_LATENCY_US -#define NRFX_RTC_MAXIMUM_LATENCY_US 2000 -#endif - -// NRFX_RTC_DEFAULT_CONFIG_FREQUENCY - Frequency <16-32768> - - -#ifndef NRFX_RTC_DEFAULT_CONFIG_FREQUENCY -#define NRFX_RTC_DEFAULT_CONFIG_FREQUENCY 32768 -#endif - -// NRFX_RTC_DEFAULT_CONFIG_RELIABLE - Ensures safe compare event triggering - - -#ifndef NRFX_RTC_DEFAULT_CONFIG_RELIABLE -#define NRFX_RTC_DEFAULT_CONFIG_RELIABLE 0 +#define NRFX_RTC1_ENABLED 0 #endif // NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority @@ -930,30 +758,20 @@ // NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver //========================================================== #ifndef NRFX_SPIM_ENABLED -#define NRFX_SPIM_ENABLED 1 +#define NRFX_SPIM_ENABLED 0 #endif // NRFX_SPIM0_ENABLED - Enable SPIM0 instance #ifndef NRFX_SPIM0_ENABLED -#define NRFX_SPIM0_ENABLED 1 +#define NRFX_SPIM0_ENABLED 0 #endif // NRFX_SPIM1_ENABLED - Enable SPIM1 instance #ifndef NRFX_SPIM1_ENABLED -#define NRFX_SPIM1_ENABLED 1 -#endif - -// NRFX_SPIM_MISO_PULL_CFG - MISO pin pull configuration. - -// <0=> NRF_GPIO_PIN_NOPULL -// <1=> NRF_GPIO_PIN_PULLDOWN -// <3=> NRF_GPIO_PIN_PULLUP - -#ifndef NRFX_SPIM_MISO_PULL_CFG -#define NRFX_SPIM_MISO_PULL_CFG 1 +#define NRFX_SPIM1_ENABLED 0 #endif // NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority @@ -1027,20 +845,20 @@ // NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver //========================================================== #ifndef NRFX_SPIS_ENABLED -#define NRFX_SPIS_ENABLED 1 +#define NRFX_SPIS_ENABLED 0 #endif // NRFX_SPIS0_ENABLED - Enable SPIS0 instance #ifndef NRFX_SPIS0_ENABLED -#define NRFX_SPIS0_ENABLED 1 +#define NRFX_SPIS0_ENABLED 0 #endif // NRFX_SPIS1_ENABLED - Enable SPIS1 instance #ifndef NRFX_SPIS1_ENABLED -#define NRFX_SPIS1_ENABLED 1 +#define NRFX_SPIS1_ENABLED 0 #endif // NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority @@ -1058,20 +876,6 @@ #define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 #endif -// NRFX_SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> - - -#ifndef NRFX_SPIS_DEFAULT_DEF -#define NRFX_SPIS_DEFAULT_DEF 255 -#endif - -// NRFX_SPIS_DEFAULT_ORC - SPIS default ORC character <0-255> - - -#ifndef NRFX_SPIS_DEFAULT_ORC -#define NRFX_SPIS_DEFAULT_ORC 255 -#endif - // NRFX_SPIS_CONFIG_LOG_ENABLED - Enables logging in the module. //========================================================== #ifndef NRFX_SPIS_CONFIG_LOG_ENABLED @@ -1128,30 +932,20 @@ // NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver //========================================================== #ifndef NRFX_SPI_ENABLED -#define NRFX_SPI_ENABLED 1 +#define NRFX_SPI_ENABLED 0 #endif // NRFX_SPI0_ENABLED - Enable SPI0 instance #ifndef NRFX_SPI0_ENABLED -#define NRFX_SPI0_ENABLED 1 +#define NRFX_SPI0_ENABLED 0 #endif // NRFX_SPI1_ENABLED - Enable SPI1 instance #ifndef NRFX_SPI1_ENABLED -#define NRFX_SPI1_ENABLED 1 -#endif - -// NRFX_SPI_MISO_PULL_CFG - MISO pin pull configuration. - -// <0=> NRF_GPIO_PIN_NOPULL -// <1=> NRF_GPIO_PIN_PULLDOWN -// <3=> NRF_GPIO_PIN_PULLUP - -#ifndef NRFX_SPI_MISO_PULL_CFG -#define NRFX_SPI_MISO_PULL_CFG 1 +#define NRFX_SPI1_ENABLED 0 #endif // NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority @@ -1222,124 +1016,17 @@ // -// NRFX_SWI_ENABLED - nrfx_swi - SWI/EGU peripheral allocator -//========================================================== -#ifndef NRFX_SWI_ENABLED -#define NRFX_SWI_ENABLED 1 -#endif -// NRFX_EGU_ENABLED - Enable EGU support - - -#ifndef NRFX_EGU_ENABLED -#define NRFX_EGU_ENABLED 1 -#endif - -// NRFX_SWI0_DISABLED - Exclude SWI0 from being utilized by the driver - - -#ifndef NRFX_SWI0_DISABLED -#define NRFX_SWI0_DISABLED 0 -#endif - -// NRFX_SWI1_DISABLED - Exclude SWI1 from being utilized by the driver - - -#ifndef NRFX_SWI1_DISABLED -#define NRFX_SWI1_DISABLED 0 -#endif - -// NRFX_SWI2_DISABLED - Exclude SWI2 from being utilized by the driver - - -#ifndef NRFX_SWI2_DISABLED -#define NRFX_SWI2_DISABLED 0 -#endif - -// NRFX_SWI3_DISABLED - Exclude SWI3 from being utilized by the driver - - -#ifndef NRFX_SWI3_DISABLED -#define NRFX_SWI3_DISABLED 0 -#endif - -// NRFX_SWI4_DISABLED - Exclude SWI4 from being utilized by the driver - - -#ifndef NRFX_SWI4_DISABLED -#define NRFX_SWI4_DISABLED 0 -#endif - -// NRFX_SWI5_DISABLED - Exclude SWI5 from being utilized by the driver - - -#ifndef NRFX_SWI5_DISABLED -#define NRFX_SWI5_DISABLED 0 -#endif - -// NRFX_SWI_CONFIG_LOG_ENABLED - Enables logging in the module. -//========================================================== -#ifndef NRFX_SWI_CONFIG_LOG_ENABLED -#define NRFX_SWI_CONFIG_LOG_ENABLED 0 -#endif -// NRFX_SWI_CONFIG_LOG_LEVEL - Default Severity level - -// <0=> Off -// <1=> Error -// <2=> Warning -// <3=> Info -// <4=> Debug - -#ifndef NRFX_SWI_CONFIG_LOG_LEVEL -#define NRFX_SWI_CONFIG_LOG_LEVEL 3 -#endif - -// NRFX_SWI_CONFIG_INFO_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SWI_CONFIG_INFO_COLOR -#define NRFX_SWI_CONFIG_INFO_COLOR 0 -#endif - -// NRFX_SWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. - -// <0=> Default -// <1=> Black -// <2=> Red -// <3=> Green -// <4=> Yellow -// <5=> Blue -// <6=> Magenta -// <7=> Cyan -// <8=> White - -#ifndef NRFX_SWI_CONFIG_DEBUG_COLOR -#define NRFX_SWI_CONFIG_DEBUG_COLOR 0 -#endif - -// - -// - // NRFX_SYSTICK_ENABLED - nrfx_systick - ARM(R) SysTick driver #ifndef NRFX_SYSTICK_ENABLED -#define NRFX_SYSTICK_ENABLED 1 +#define NRFX_SYSTICK_ENABLED 0 #endif // NRFX_TEMP_ENABLED - nrfx_temp - TEMP peripheral driver //========================================================== #ifndef NRFX_TEMP_ENABLED -#define NRFX_TEMP_ENABLED 1 +#define NRFX_TEMP_ENABLED 0 #endif // NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority @@ -1362,71 +1049,31 @@ // NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver //========================================================== #ifndef NRFX_TIMER_ENABLED -#define NRFX_TIMER_ENABLED 1 +#define NRFX_TIMER_ENABLED 0 #endif -// NRFX_TIMER0_ENABLED - Enable TIMER0 instance +// NRFX_TIMER0_ENABLED - Enable TIMER0 instance #ifndef NRFX_TIMER0_ENABLED -#define NRFX_TIMER0_ENABLED 1 +#define NRFX_TIMER0_ENABLED 0 #endif // NRFX_TIMER1_ENABLED - Enable TIMER1 instance - #ifndef NRFX_TIMER1_ENABLED -#define NRFX_TIMER1_ENABLED 1 +#define NRFX_TIMER1_ENABLED 0 #endif // NRFX_TIMER2_ENABLED - Enable TIMER2 instance - #ifndef NRFX_TIMER2_ENABLED -#define NRFX_TIMER2_ENABLED 1 +#define NRFX_TIMER2_ENABLED 0 #endif // NRFX_TIMER3_ENABLED - Enable TIMER3 instance - #ifndef NRFX_TIMER3_ENABLED -#define NRFX_TIMER3_ENABLED 1 -#endif - -// NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY - Timer frequency if in Timer mode - -// <0=> 16 MHz -// <1=> 8 MHz -// <2=> 4 MHz -// <3=> 2 MHz -// <4=> 1 MHz -// <5=> 500 kHz -// <6=> 250 kHz -// <7=> 125 kHz -// <8=> 62.5 kHz -// <9=> 31.25 kHz - -#ifndef NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY -#define NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY 0 -#endif - -// NRFX_TIMER_DEFAULT_CONFIG_MODE - Timer mode or operation - -// <0=> Timer -// <1=> Counter - -#ifndef NRFX_TIMER_DEFAULT_CONFIG_MODE -#define NRFX_TIMER_DEFAULT_CONFIG_MODE 0 -#endif - -// NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH - Timer counter bit width - -// <0=> 16 bit -// <1=> 8 bit -// <2=> 24 bit -// <3=> 32 bit - -#ifndef NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH -#define NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH 0 +#define NRFX_TIMER3_ENABLED 0 #endif // NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority @@ -1500,37 +1147,19 @@ // NRFX_TWIM_ENABLED - nrfx_twim - TWIM peripheral driver //========================================================== #ifndef NRFX_TWIM_ENABLED -#define NRFX_TWIM_ENABLED 1 +#define NRFX_TWIM_ENABLED 0 #endif -// NRFX_TWIM0_ENABLED - Enable TWIM0 instance +// NRFX_TWIM0_ENABLED - Enable TWIM0 instance #ifndef NRFX_TWIM0_ENABLED -#define NRFX_TWIM0_ENABLED 1 +#define NRFX_TWIM0_ENABLED 0 #endif // NRFX_TWIM1_ENABLED - Enable TWIM1 instance - #ifndef NRFX_TWIM1_ENABLED -#define NRFX_TWIM1_ENABLED 1 -#endif - -// NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY - Frequency - -// <26738688=> 100k -// <67108864=> 250k -// <104857600=> 400k - -#ifndef NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY -#define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY 26738688 -#endif - -// NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit - - -#ifndef NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT -#define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 +#define NRFX_TWIM1_ENABLED 0 #endif // NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority @@ -1615,14 +1244,12 @@ // NRFX_TWIS1_ENABLED - Enable TWIS1 instance - #ifndef NRFX_TWIS1_ENABLED -#define NRFX_TWIS1_ENABLED 1 +#define NRFX_TWIS1_ENABLED 0 #endif // NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once - // Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. #ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY @@ -1631,7 +1258,6 @@ // NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode - // Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. #ifndef NRFX_TWIS_NO_SYNC_MODE @@ -1739,37 +1365,19 @@ // NRFX_TWI_ENABLED - nrfx_twi - TWI peripheral driver //========================================================== #ifndef NRFX_TWI_ENABLED -#define NRFX_TWI_ENABLED 1 +#define NRFX_TWI_ENABLED 0 #endif -// NRFX_TWI0_ENABLED - Enable TWI0 instance +// NRFX_TWI0_ENABLED - Enable TWI0 instance #ifndef NRFX_TWI0_ENABLED -#define NRFX_TWI0_ENABLED 1 +#define NRFX_TWI0_ENABLED 0 #endif // NRFX_TWI1_ENABLED - Enable TWI1 instance - #ifndef NRFX_TWI1_ENABLED -#define NRFX_TWI1_ENABLED 1 -#endif - -// NRFX_TWI_DEFAULT_CONFIG_FREQUENCY - Frequency - -// <26738688=> 100k -// <67108864=> 250k -// <104857600=> 400k - -#ifndef NRFX_TWI_DEFAULT_CONFIG_FREQUENCY -#define NRFX_TWI_DEFAULT_CONFIG_FREQUENCY 26738688 -#endif - -// NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit - - -#ifndef NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT -#define NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 +#define NRFX_TWI1_ENABLED 0 #endif // NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority @@ -1843,54 +1451,13 @@ // NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver //========================================================== #ifndef NRFX_UARTE_ENABLED -#define NRFX_UARTE_ENABLED 1 +#define NRFX_UARTE_ENABLED 0 #endif -// NRFX_UARTE0_ENABLED - Enable UARTE0 instance -#ifndef NRFX_UARTE0_ENABLED -#define NRFX_UARTE0_ENABLED 1 -#endif - -// NRFX_UARTE_DEFAULT_CONFIG_HWFC - Hardware Flow Control -// <0=> Disabled -// <1=> Enabled - -#ifndef NRFX_UARTE_DEFAULT_CONFIG_HWFC -#define NRFX_UARTE_DEFAULT_CONFIG_HWFC 0 -#endif - -// NRFX_UARTE_DEFAULT_CONFIG_PARITY - Parity - -// <0=> Excluded -// <14=> Included - -#ifndef NRFX_UARTE_DEFAULT_CONFIG_PARITY -#define NRFX_UARTE_DEFAULT_CONFIG_PARITY 0 -#endif - -// NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE - Default Baudrate - -// <323584=> 1200 baud -// <643072=> 2400 baud -// <1290240=> 4800 baud -// <2576384=> 9600 baud -// <3862528=> 14400 baud -// <5152768=> 19200 baud -// <7716864=> 28800 baud -// <8388608=> 31250 baud -// <10289152=> 38400 baud -// <15007744=> 56000 baud -// <15400960=> 57600 baud -// <20615168=> 76800 baud -// <30801920=> 115200 baud -// <61865984=> 230400 baud -// <67108864=> 250000 baud -// <121634816=> 460800 baud -// <251658240=> 921600 baud -// <268435456=> 1000000 baud +// NRFX_UARTE0_ENABLED - Enable UARTE0 instance -#ifndef NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE -#define NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE 30801920 +#ifndef NRFX_UARTE0_ENABLED +#define NRFX_UARTE0_ENABLED 0 #endif // NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority @@ -1964,54 +1531,13 @@ // NRFX_UART_ENABLED - nrfx_uart - UART peripheral driver //========================================================== #ifndef NRFX_UART_ENABLED -#define NRFX_UART_ENABLED 1 -#endif -// NRFX_UART0_ENABLED - Enable UART0 instance -#ifndef NRFX_UART0_ENABLED -#define NRFX_UART0_ENABLED 1 -#endif - -// NRFX_UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control - -// <0=> Disabled -// <1=> Enabled - -#ifndef NRFX_UART_DEFAULT_CONFIG_HWFC -#define NRFX_UART_DEFAULT_CONFIG_HWFC 0 -#endif - -// NRFX_UART_DEFAULT_CONFIG_PARITY - Parity - -// <0=> Excluded -// <14=> Included - -#ifndef NRFX_UART_DEFAULT_CONFIG_PARITY -#define NRFX_UART_DEFAULT_CONFIG_PARITY 0 +#define NRFX_UART_ENABLED 0 #endif -// NRFX_UART_DEFAULT_CONFIG_BAUDRATE - Default Baudrate - -// <323584=> 1200 baud -// <643072=> 2400 baud -// <1290240=> 4800 baud -// <2576384=> 9600 baud -// <3866624=> 14400 baud -// <5152768=> 19200 baud -// <7729152=> 28800 baud -// <8388608=> 31250 baud -// <10309632=> 38400 baud -// <15007744=> 56000 baud -// <15462400=> 57600 baud -// <20615168=> 76800 baud -// <30924800=> 115200 baud -// <61845504=> 230400 baud -// <67108864=> 250000 baud -// <123695104=> 460800 baud -// <247386112=> 921600 baud -// <268435456=> 1000000 baud +// NRFX_UART0_ENABLED - Enable UART0 instance -#ifndef NRFX_UART_DEFAULT_CONFIG_BAUDRATE -#define NRFX_UART_DEFAULT_CONFIG_BAUDRATE 30924800 +#ifndef NRFX_UART0_ENABLED +#define NRFX_UART0_ENABLED 0 #endif // NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority @@ -2180,24 +1706,13 @@ // NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver //========================================================== #ifndef NRFX_WDT_ENABLED -#define NRFX_WDT_ENABLED 1 +#define NRFX_WDT_ENABLED 0 #endif -// NRFX_WDT_CONFIG_BEHAVIOUR - WDT behavior in CPU SLEEP or HALT mode - -// <1=> Run in SLEEP, Pause in HALT -// <8=> Pause in SLEEP, Run in HALT -// <9=> Run in SLEEP and HALT -// <0=> Pause in SLEEP and HALT - -#ifndef NRFX_WDT_CONFIG_BEHAVIOUR -#define NRFX_WDT_CONFIG_BEHAVIOUR 1 -#endif - -// NRFX_WDT_CONFIG_RELOAD_VALUE - Reload value <15-4294967295> +// NRFX_WDT0_ENABLED - Enable WDT0 instance -#ifndef NRFX_WDT_CONFIG_RELOAD_VALUE -#define NRFX_WDT_CONFIG_RELOAD_VALUE 2000 +#ifndef NRFX_WDT0_ENABLED +#define NRFX_WDT0_ENABLED 0 #endif // NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver @@ -2209,7 +1724,7 @@ #define NRFX_WDT_CONFIG_NO_IRQ 0 #endif -// NRFX_WDT_CONFIG_IRQ_PRIORITY - Interrupt priority +// NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority // <0=> 0 (highest) // <1=> 1 @@ -2220,8 +1735,8 @@ // <6=> 6 // <7=> 7 -#ifndef NRFX_WDT_CONFIG_IRQ_PRIORITY -#define NRFX_WDT_CONFIG_IRQ_PRIORITY 7 +#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY 7 #endif // NRFX_WDT_CONFIG_LOG_ENABLED - Enables logging in the module. From 8f1ab86dd2334d39c2fca95ef4875cd10c22a62b Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 30 Sep 2021 23:20:12 -0500 Subject: [PATCH 450/617] nrf52820_hic: I2C address configuration to RTE_Device.h --- .../nordic/nrf52820/I2C_Slave_nRF52820.c | 12 +++--- source/hic_hal/nordic/nrf52820/RTE_Device.h | 4 +- .../nrf52820/nrfx/nrfx_config_nrf52820.h | 38 ++----------------- 3 files changed, 13 insertions(+), 41 deletions(-) diff --git a/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.c b/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.c index 3f19f6f19..a84dcee7c 100644 --- a/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.c +++ b/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.c @@ -1,5 +1,5 @@ /* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2021 Arm Limited (or its affiliates). All + * Copyright (c) 2013-2021 Arm Limited (or its affiliates). All * rights reserved. * * SPDX-License-Identifier: Apache-2.0 @@ -51,7 +51,7 @@ static const ARM_DRIVER_VERSION DriverVersion = { }; /* Driver Capabilities */ -static const ARM_I2C_CAPABILITIES DriverCapabilities = { +static const ARM_I2C_CAPABILITIES DriverCapabilities = { 0U // Does not support 10-bit addressing #if (defined(ARM_I2C_API_VERSION) && (ARM_I2C_API_VERSION >= 0x203U)) , 0U // Reserved bits @@ -164,8 +164,8 @@ static int32_t I2C_Initialize (ARM_I2C_SignalEvent_t cb_event, I2C_RESOURCES *i2 } // TWIS Configuration - i2c->info->config.addr[0] = NRFX_TWIS_DEFAULT_CONFIG_ADDR0; - i2c->info->config.addr[1] = NRFX_TWIS_DEFAULT_CONFIG_ADDR1; + i2c->info->config.addr[0] = RTE_TWIS0_ADDR0; + i2c->info->config.addr[1] = RTE_TWIS0_ADDR1; i2c->info->config.scl = RTE_TWIS0_SCL_PIN_NUM; i2c->info->config.scl_pull = NRF_GPIO_PIN_NOPULL; i2c->info->config.sda = RTE_TWIS0_SDA_PIN_NUM; @@ -217,8 +217,8 @@ static int32_t I2C_PowerControl (ARM_POWER_STATE state, I2C_RESOURCES *i2c) { return ARM_DRIVER_ERROR; } - if ((state != ARM_POWER_OFF) && - (state != ARM_POWER_FULL) && + if ((state != ARM_POWER_OFF) && + (state != ARM_POWER_FULL) && (state != ARM_POWER_LOW)) { return ARM_DRIVER_ERROR_PARAMETER; } diff --git a/source/hic_hal/nordic/nrf52820/RTE_Device.h b/source/hic_hal/nordic/nrf52820/RTE_Device.h index 96198ad61..58646845a 100644 --- a/source/hic_hal/nordic/nrf52820/RTE_Device.h +++ b/source/hic_hal/nordic/nrf52820/RTE_Device.h @@ -1,5 +1,5 @@ /* ----------------------------------------------------------------------------- - * Copyright (c) 2013-2021 Arm Limited (or its affiliates). All + * Copyright (c) 2013-2021 Arm Limited (or its affiliates). All * rights reserved. * * SPDX-License-Identifier: Apache-2.0 @@ -65,5 +65,7 @@ #define RTE_TWIS0_SDA_PIN_NUM I2C_SDA_PIN // +#define RTE_TWIS0_ADDR0 0x70 +#define RTE_TWIS0_ADDR1 0x72 #endif /* __RTE_DEVICE_H */ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h index c4d5e53dc..54058b24d 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h +++ b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h @@ -1264,36 +1264,6 @@ #define NRFX_TWIS_NO_SYNC_MODE 0 #endif -// NRFX_TWIS_DEFAULT_CONFIG_ADDR0 - Address0 -#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR0 -#define NRFX_TWIS_DEFAULT_CONFIG_ADDR0 0 -#endif - -// NRFX_TWIS_DEFAULT_CONFIG_ADDR1 - Address1 -#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR1 -#define NRFX_TWIS_DEFAULT_CONFIG_ADDR1 0 -#endif - -// NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL - SCL pin pull configuration - -// <0=> Disabled -// <1=> Pull down -// <3=> Pull up - -#ifndef NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL -#define NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL 0 -#endif - -// NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL - SDA pin pull configuration - -// <0=> Disabled -// <1=> Pull down -// <3=> Pull up - -#ifndef NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL -#define NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL 0 -#endif - // NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority // <0=> 0 (highest) @@ -1611,9 +1581,9 @@ // NRFX_USBD_ENABLED - nrfx_usbd - USBD peripheral driver //========================================================== #ifndef NRFX_USBD_ENABLED -#define NRFX_USBD_ENABLED 1 +#define NRFX_USBD_ENABLED 0 #endif -// NRFX_USBD_CONFIG_IRQ_PRIORITY - Interrupt priority +// NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority // <0=> 0 (highest) // <1=> 1 @@ -1624,8 +1594,8 @@ // <6=> 6 // <7=> 7 -#ifndef NRFX_USBD_CONFIG_IRQ_PRIORITY -#define NRFX_USBD_CONFIG_IRQ_PRIORITY 7 +#ifndef NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY 7 #endif // USBD_CONFIG_DMASCHEDULER_ISO_BOOST - Give priority to isochronous transfers From b48b6229b449b82fafe8fd42bf9495d0dc72d250 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 19 Oct 2021 22:26:28 -0500 Subject: [PATCH 451/617] nrf52820_hic: update DAP_config.h for CMSIS-DAP 2.1 --- source/hic_hal/nordic/nrf52820/DAP_config.h | 37 +++++++++++++++------ 1 file changed, 26 insertions(+), 11 deletions(-) diff --git a/source/hic_hal/nordic/nrf52820/DAP_config.h b/source/hic_hal/nordic/nrf52820/DAP_config.h index ebca8f88e..95b5f1fb0 100644 --- a/source/hic_hal/nordic/nrf52820/DAP_config.h +++ b/source/hic_hal/nordic/nrf52820/DAP_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * Copyright (c) 2013-2021 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -17,8 +17,8 @@ * * ---------------------------------------------------------------------- * - * $Date: 1. December 2017 - * $Revision: V2.0.0 + * $Date: 16. June 2021 + * $Revision: V2.1.0 * * Project: CMSIS-DAP Configuration * Title: DAP_config.h CMSIS-DAP Configuration File (Template) @@ -101,6 +101,9 @@ This information includes: /// This information is returned by the command \ref DAP_Info as part of Capabilities. #define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available. +/// USART Driver instance number for the UART SWO. +#define SWO_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#). + /// Maximum SWO UART Baudrate. #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz. @@ -117,16 +120,28 @@ This information includes: /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. #define TIMESTAMP_CLOCK 100000000U ///< Timestamp clock in Hz (0 = timestamps not supported). +/// Indicate that UART Communication Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART 0 ///< DAP UART: 1 = available, 0 = not available. + +/// USART Driver instance number for the UART Communication Port. +#define DAP_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#). + +/// UART Receive Buffer Size. +#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n). + +/// UART Transmit Buffer Size. +#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n). + +/// Indicate that UART Communication via USB COM Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available. + /// Debug Unit is connected to fixed Target Device. /// The Debug Unit may be part of an evaluation board and always connected to a fixed -/// known device. In this case a Device Vendor and Device Name string is stored which -/// may be used by the debugger or IDE to configure device parameters. -#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown; - -#if TARGET_DEVICE_FIXED -#define TARGET_DEVICE_VENDOR "ARM" ///< String indicating the Silicon Vendor -#define TARGET_DEVICE_NAME "Cortex-M4" ///< String indicating the Target Device -#endif +/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings +/// are stored and may be used by the debugger or IDE to configure device parameters. +#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown; ///@} From 2e833c0232b4a62ee69c36de49d5b5a8bd77048e Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 21 Oct 2021 20:12:48 -0500 Subject: [PATCH 452/617] nrf52820_hic: remove the old nrf52833_dk projects used for early development --- projects.yaml | 28 ++-- records/board/nrf52820_if.yaml | 11 -- records/board/nrf52833_dk.yaml | 8 - source/board/nrf52820_if.c | 56 ------- .../override_nrf52833_dk/IO_Config_Override.h | 148 ------------------ test/info.py | 2 + 6 files changed, 11 insertions(+), 242 deletions(-) delete mode 100644 records/board/nrf52820_if.yaml delete mode 100644 records/board/nrf52833_dk.yaml delete mode 100644 source/board/nrf52820_if.c delete mode 100644 source/board/override_nrf52833_dk/IO_Config_Override.h diff --git a/projects.yaml b/projects.yaml index 6e1f50f01..69d217c44 100644 --- a/projects.yaml +++ b/projects.yaml @@ -66,25 +66,25 @@ module: - records/rtos/rtos-cm33.yaml - records/hic_hal/lpc55s69.yaml - records/usb/usb-bulk.yaml - hic_sam3u2c: &module_hic_sam3u2c - - records/rtos/rtos-cm3.yaml - - records/hic_hal/sam3u2c.yaml - hic_stm32f103xb: &module_hic_stm32f103xb - - records/rtos/rtos-cm3.yaml - - records/hic_hal/stm32f103xb.yaml + hic_m48ssidae: &module_hic_m48ssidae + - records/rtos/rtos-cm4.yaml + - records/hic_hal/m48ssidae.yaml hic_max32620: &module_hic_max32620 - records/rtos/rtos-cm4.yaml - records/hic_hal/max32620.yaml hic_max32625: &module_hic_max32625 - records/rtos/rtos-cm4.yaml - records/hic_hal/max32625.yaml - hic_m48ssidae: &module_hic_m48ssidae - - records/rtos/rtos-cm4.yaml - - records/hic_hal/m48ssidae.yaml hic_nrf52820: &module_hic_nrf52820 - records/rtos/rtos-cm4.yaml - records/hic_hal/nrf52820.yaml - records/usb/usb-bulk.yaml + hic_sam3u2c: &module_hic_sam3u2c + - records/rtos/rtos-cm3.yaml + - records/hic_hal/sam3u2c.yaml + hic_stm32f103xb: &module_hic_stm32f103xb + - records/rtos/rtos-cm3.yaml + - records/hic_hal/stm32f103xb.yaml projects: # HIC bootloaders and all target interfaces @@ -172,16 +172,6 @@ projects: - *module_if - *module_hic_nrf52820 - records/family/all_family.yaml - nrf52833_dk_bl: - - *module_bl - - records/hic_hal/nrf52820.yaml - - records/board/nrf52820_bl.yaml - - records/board/nrf52833_dk.yaml - nrf52833_dk_if: - - *module_if - - *module_hic_nrf52820 - - records/board/nrf52820_if.yaml - - records/board/nrf52833_dk.yaml sam3u2c_bl: - *module_bl - records/hic_hal/sam3u2c.yaml diff --git a/records/board/nrf52820_if.yaml b/records/board/nrf52820_if.yaml deleted file mode 100644 index e1020ec12..000000000 --- a/records/board/nrf52820_if.yaml +++ /dev/null @@ -1,11 +0,0 @@ -common: - macros: - # - TARGET_NRF52 - # - TARGET_NRF52_64 - - TARGET_NRF52840 - sources: - board: - - source/board/nrf52820_if.c - target: - - source/family/nordic/nrf52/target.c - - source/family/nordic/target_reset_nrf52.c diff --git a/records/board/nrf52833_dk.yaml b/records/board/nrf52833_dk.yaml deleted file mode 100644 index e353e082d..000000000 --- a/records/board/nrf52833_dk.yaml +++ /dev/null @@ -1,8 +0,0 @@ -common: - macros: - - IO_CONFIG_OVERRIDE - - DEVELOP_IN_NRF52833 - # - NRF528XX_DYNAMIC_PIN - - UART_EXTERNAL - includes: - - source/board/override_nrf52833_dk diff --git a/source/board/nrf52820_if.c b/source/board/nrf52820_if.c deleted file mode 100644 index 630a5e725..000000000 --- a/source/board/nrf52820_if.c +++ /dev/null @@ -1,56 +0,0 @@ -/** - * @file nrf52820_if.c - * @brief board ID for nrf528xx on nrf52820 - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2021, Arm Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_family.h" -#include "target_board.h" - -const char * const board_id_nrf52 = "1101"; -const char * const board_id_nrf52_64 = "9903"; -const char * const board_id_nrf52840 = "1102"; - -extern target_cfg_t target_device_nrf51822_32; -extern target_cfg_t target_device_nrf52_64; -extern target_cfg_t target_device_nrf52840; -target_cfg_t target_device; - -static void nrf_prerun_board_config(void) { -#if defined(TARGET_NRF52) - target_device = target_device_nrf52; - target_device.rt_board_id = board_id_nrf52; -#elif defined(TARGET_NRF52_64) - target_device = target_device_nrf52_64; - target_device.rt_board_id = board_id_nrf52_64; -#elif defined(TARGET_NRF52840) - target_device = target_device_nrf52840; - target_device.rt_board_id = board_id_nrf52840; -#else -#error "No target defined" -#endif -} - -const board_info_t g_board_info = { - .info_version = kBoardInfoVersion, - .family_id = kNordic_Nrf52_FamilyID, - .info_version = kBoardInfoVersion, - .flags = kEnablePageErase, - .prerun_board_config = nrf_prerun_board_config, - .target_cfg = &target_device, -}; diff --git a/source/board/override_nrf52833_dk/IO_Config_Override.h b/source/board/override_nrf52833_dk/IO_Config_Override.h deleted file mode 100644 index 789209f1c..000000000 --- a/source/board/override_nrf52833_dk/IO_Config_Override.h +++ /dev/null @@ -1,148 +0,0 @@ -/** - * @file IO_Config_Override.c - * @brief Alternative IO Configuration for nrf52820 HIC - * - * DAPLink Interface Firmware - * Copyright (c) 2021, Arm Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __IO_CONFIG_H__ -#define __IO_CONFIG_H__ - -#include "device.h" -#include "compiler.h" -#include "daplink.h" - -#include "dl_nrf_gpio.h" - -// This GPIO configuration is only valid for the nrf52820 HIC -COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_NRF52820); - -#define LED_1 NRF_GPIO_PIN_MAP(0, 13) -#define LED_2 NRF_GPIO_PIN_MAP(0, 14) -#define LED_3 NRF_GPIO_PIN_MAP(0, 15) -#define LED_4 NRF_GPIO_PIN_MAP(0, 16) -#define BUTTON_1 NRF_GPIO_PIN_MAP(0, 11) - -// SWDCLK (Output) -#define PIN_SWCLK NRF_GPIO_PIN_MAP(0, 4) -// #define PIN_SWCLK NRF_GPIO_PIN_MAP(0, 30) - -// SWDIO (Input/Output) -#define PIN_SWDIO NRF_GPIO_PIN_MAP(0, 5) -// #define PIN_SWDIO NRF_GPIO_PIN_MAP(0, 31) - -// nRESET Pin -#undef PIN_nRESET - - -#ifndef NRF528XX_DYNAMIC_PIN - -// Target Running LED (Output) -#define LED_RUNNING LED_1 - -// Connected LED (Output) -#define LED_CONNECTED LED_2 - -// HID LED -#define LED_HID LED_2 - -// MSC LED -#define LED_MSC LED_3 - -// CDC LED -#define LED_CDC LED_4 - -// Reset button -#define RESET_BUTTON BUTTON_1 -#define RESET_BUTTON_PULL NRF_GPIO_PIN_PULLUP - -// UART -#ifndef UART_EXTERNAL -// This is connected to J-Link -#define UART_RX_PIN NRF_GPIO_PIN_MAP(0, 8) // RxD P0.08 -#define UART_TX_PIN NRF_GPIO_PIN_MAP(0, 6) // TxD P0.06 -#else -// Alternative pin out -#define UART_RX_PIN NRF_GPIO_PIN_MAP(0, 29) -#define UART_TX_PIN NRF_GPIO_PIN_MAP(0, 30) -#endif - -// I2C -#define I2C_SCL_PIN NRF_GPIO_PIN_MAP(0, 27) -#define I2C_SDA_PIN NRF_GPIO_PIN_MAP(0, 26) - -#else - -/* Use dynamic pin-mapping */ - -extern uint32_t uart_tx_pin; -extern uint32_t uart_rx_pin; -extern uint32_t sw_reset_pin; -extern uint32_t led_usb_pin; -extern uint32_t led_pwr_pin; -extern uint32_t i2c_scl_pin; -extern uint32_t i2c_sda_pin; - -// HID LED -#define LED_HID led_usb_pin - -// MSC LED -#define LED_MSC led_usb_pin - -// CDC LED -#define LED_CDC led_usb_pin - -// POWER LED -#define LED_PWR led_pwr_pin - -// Reset button (SW_RESET) -#define RESET_BUTTON sw_reset_pin -#define RESET_BUTTON_PULL NRF_GPIO_PIN_PULLUP - -// UART -#define UART_TX_PIN uart_tx_pin -#define UART_RX_PIN uart_rx_pin -// I2C -#define I2C_SCL_PIN i2c_scl_pin -#define I2C_SDA_PIN i2c_sda_pin - -/* Use defaults for nRF52820 */ -#define NRF52820_RESET_PIN NRF_GPIO_PIN_MAP(0, 6) -#define NRF52820_USB_LED_PIN NRF_GPIO_PIN_MAP(0, 14) -#define NRF52820_PWR_LED_PIN NRF_GPIO_PIN_MAP(0, 15) -#define NRF52820_UART_TX_PIN NRF_GPIO_PIN_MAP(0, 8) // From IMCU to target -#define NRF52820_UART_RX_PIN NRF_GPIO_PIN_MAP(0, 29) // From target to IMCU - -#define NRF52833_RESET_PIN BUTTON_1 -#define NRF52833_USB_LED_PIN LED_4 -#define NRF52833_PWR_LED_PIN LED_3 -#ifndef UART_EXTERNAL -// This is connected to J-Link -#define NRF52833_UART_TX_PIN NRF_GPIO_PIN_MAP(0, 8) // RxD P0.08 -#define NRF52833_UART_RX_PIN NRF_GPIO_PIN_MAP(0, 6) // TxD P0.06 -#else -// Alternative pin out -#define NRF52833_UART_TX_PIN NRF_GPIO_PIN_MAP(0, 29) // From IMCU to target -#define NRF52833_UART_RX_PIN NRF_GPIO_PIN_MAP(0, 30) // From target to IMCU -#endif - -#define NRF52833_I2C_SCL_PIN NRF_GPIO_PIN_MAP(0, 27) -#define NRF52833_I2C_SDA_PIN NRF_GPIO_PIN_MAP(0, 26) - -#endif - -#endif diff --git a/test/info.py b/test/info.py index a831e5d4b..22e9b9d94 100644 --- a/test/info.py +++ b/test/info.py @@ -101,6 +101,7 @@ ('lpc55s69_if', False, 0x10000, "bin" ), ('max32620_if', False, 0x0000, "bin" ), ('max32625_if', False, 0x0000, "bin" ), + ('nrf52820_if', False, 0x0000, "bin" ), ('sam3u2c_if', False, 0x0000, "bin" ), ('stm32f103xb_if', False, 0x0000, "bin" ), } @@ -222,6 +223,7 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'lpc55s69_if', None, None ), ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'max32620_if', None, None ), ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'max32625_if', None, None ), + ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'nrf52820_if', None, None ), ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'sam3u2c_if', None, None ), ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_if', None, None ), ] From e6bc062f67354248468b15254aed22c0a07b0f74 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 22 Oct 2021 00:13:58 -0500 Subject: [PATCH 453/617] nrf52820_hic: remove CMSIS headers and minor clean-ups --- docs/hic/nrf52820.md | 30 +- source/board/nrf52820_bl.c | 2 +- .../hic_hal/nordic/nrf52820/Driver_Common.h | 69 ---- source/hic_hal/nordic/nrf52820/Driver_USART.h | 341 ------------------ 4 files changed, 2 insertions(+), 440 deletions(-) delete mode 100644 source/hic_hal/nordic/nrf52820/Driver_Common.h delete mode 100644 source/hic_hal/nordic/nrf52820/Driver_USART.h diff --git a/docs/hic/nrf52820.md b/docs/hic/nrf52820.md index 30af3ab26..3ef417af7 100644 --- a/docs/hic/nrf52820.md +++ b/docs/hic/nrf52820.md @@ -2,7 +2,7 @@ Based on Nordic [nRF52820](https://www.nordicsemi.com/Products/nRF52820): - Cortex-M4 64 MHz --256 KB Flash +- 256 KB Flash - 32 KB RAM - Full-speed USB 2.0 device controller - QFN40 packaging @@ -60,31 +60,3 @@ Note: Note: - LEDs have active state high. - -## nRF52833-DK pin assignment - -For development on [nRF52833-DK](https://www.nordicsemi.com/Products/Development-hardware/nRF52833-DK). - -| Signal | I/O | Symbol | Connection | -|-------------|:---:|---------|:----------:| -| SWD | -| SWCLK | O | P0.04 | | -| SWDIO | I/O | P0.05 | | -| nRESET | O | P0.07 | | -| UART | -| UART RX | I | P0.08 | J-Link TX | -| UART TX | O | P0.06 | J-Link RX | -| UART (alt) | -| UART RX | I | P0.29 | | -| UART TX | O | P0.30 | | -| Button | -| F-RST But. | I | P0.11 | BUTTON_1 | -| LEDs | -| RUN LED | O | P0.13 | LED_1 | -| CON LED | O | P0.14 | LED_2 | -| HID LED | O | P0.14 | LED_2 | -| MSD LED | O | P0.15 | LED_3 | -| CDC LED | O | P0.16 | LED_4 | - -Note: -- LEDs have active state low. diff --git a/source/board/nrf52820_bl.c b/source/board/nrf52820_bl.c index ed4d007fb..012bbfbb4 100644 --- a/source/board/nrf52820_bl.c +++ b/source/board/nrf52820_bl.c @@ -3,7 +3,7 @@ * @brief board ID and meta-data for HIC based on Nordic Semiconductor nRF52820 * * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2021, Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may diff --git a/source/hic_hal/nordic/nrf52820/Driver_Common.h b/source/hic_hal/nordic/nrf52820/Driver_Common.h deleted file mode 100644 index 59d5b759c..000000000 --- a/source/hic_hal/nordic/nrf52820/Driver_Common.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 2. Feb 2017 - * $Revision: V2.0 - * - * Project: Common Driver definitions - */ - -/* History: - * Version 2.0 - * Changed prefix ARM_DRV -> ARM_DRIVER - * Added General return codes definitions - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.00 - * Initial release - */ - -#ifndef DRIVER_COMMON_H_ -#define DRIVER_COMMON_H_ - -#include -#include -#include - -#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor)) - -/** -\brief Driver Version -*/ -typedef struct _ARM_DRIVER_VERSION { - uint16_t api; ///< API version - uint16_t drv; ///< Driver version -} ARM_DRIVER_VERSION; - -/* General return codes */ -#define ARM_DRIVER_OK 0 ///< Operation succeeded -#define ARM_DRIVER_ERROR -1 ///< Unspecified error -#define ARM_DRIVER_ERROR_BUSY -2 ///< Driver is busy -#define ARM_DRIVER_ERROR_TIMEOUT -3 ///< Timeout occurred -#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported -#define ARM_DRIVER_ERROR_PARAMETER -5 ///< Parameter error -#define ARM_DRIVER_ERROR_SPECIFIC -6 ///< Start of driver specific errors - -/** -\brief General power states -*/ -typedef enum _ARM_POWER_STATE { - ARM_POWER_OFF, ///< Power off: no operation possible - ARM_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events - ARM_POWER_FULL ///< Power on: full operation at maximum performance -} ARM_POWER_STATE; - -#endif /* DRIVER_COMMON_H_ */ diff --git a/source/hic_hal/nordic/nrf52820/Driver_USART.h b/source/hic_hal/nordic/nrf52820/Driver_USART.h deleted file mode 100644 index e60bf51a3..000000000 --- a/source/hic_hal/nordic/nrf52820/Driver_USART.h +++ /dev/null @@ -1,341 +0,0 @@ -/* - * Copyright (c) 2013-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * $Date: 2. Feb 2017 - * $Revision: V2.3 - * - * Project: USART (Universal Synchronous Asynchronous Receiver Transmitter) - * Driver definitions - */ - -/* History: - * Version 2.3 - * ARM_USART_STATUS and ARM_USART_MODEM_STATUS made volatile - * Version 2.2 - * Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions - * Version 2.1 - * Removed optional argument parameter from Signal Event - * Version 2.0 - * New simplified driver: - * complexity moved to upper layer (especially data handling) - * more unified API for different communication interfaces - * renamed driver UART -> USART (Asynchronous & Synchronous) - * Added modes: - * Synchronous - * Single-wire - * IrDA - * Smart Card - * Changed prefix ARM_DRV -> ARM_DRIVER - * Version 1.10 - * Namespace prefix ARM_ added - * Version 1.01 - * Added events: - * ARM_UART_EVENT_TX_EMPTY, ARM_UART_EVENT_RX_TIMEOUT - * ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD - * Added functions: SetTxThreshold, SetRxThreshold - * Added "rx_timeout_event" to capabilities - * Version 1.00 - * Initial release - */ - -#ifndef DRIVER_USART_H_ -#define DRIVER_USART_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "Driver_Common.h" - -#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */ - - -/****** USART Control Codes *****/ - -#define ARM_USART_CONTROL_Pos 0 -#define ARM_USART_CONTROL_Msk (0xFFUL << ARM_USART_CONTROL_Pos) - -/*----- USART Control Codes: Mode -----*/ -#define ARM_USART_MODE_ASYNCHRONOUS (0x01UL << ARM_USART_CONTROL_Pos) ///< UART (Asynchronous); arg = Baudrate -#define ARM_USART_MODE_SYNCHRONOUS_MASTER (0x02UL << ARM_USART_CONTROL_Pos) ///< Synchronous Master (generates clock signal); arg = Baudrate -#define ARM_USART_MODE_SYNCHRONOUS_SLAVE (0x03UL << ARM_USART_CONTROL_Pos) ///< Synchronous Slave (external clock signal) -#define ARM_USART_MODE_SINGLE_WIRE (0x04UL << ARM_USART_CONTROL_Pos) ///< UART Single-wire (half-duplex); arg = Baudrate -#define ARM_USART_MODE_IRDA (0x05UL << ARM_USART_CONTROL_Pos) ///< UART IrDA; arg = Baudrate -#define ARM_USART_MODE_SMART_CARD (0x06UL << ARM_USART_CONTROL_Pos) ///< UART Smart Card; arg = Baudrate - -/*----- USART Control Codes: Mode Parameters: Data Bits -----*/ -#define ARM_USART_DATA_BITS_Pos 8 -#define ARM_USART_DATA_BITS_Msk (7UL << ARM_USART_DATA_BITS_Pos) -#define ARM_USART_DATA_BITS_5 (5UL << ARM_USART_DATA_BITS_Pos) ///< 5 Data bits -#define ARM_USART_DATA_BITS_6 (6UL << ARM_USART_DATA_BITS_Pos) ///< 6 Data bit -#define ARM_USART_DATA_BITS_7 (7UL << ARM_USART_DATA_BITS_Pos) ///< 7 Data bits -#define ARM_USART_DATA_BITS_8 (0UL << ARM_USART_DATA_BITS_Pos) ///< 8 Data bits (default) -#define ARM_USART_DATA_BITS_9 (1UL << ARM_USART_DATA_BITS_Pos) ///< 9 Data bits - -/*----- USART Control Codes: Mode Parameters: Parity -----*/ -#define ARM_USART_PARITY_Pos 12 -#define ARM_USART_PARITY_Msk (3UL << ARM_USART_PARITY_Pos) -#define ARM_USART_PARITY_NONE (0UL << ARM_USART_PARITY_Pos) ///< No Parity (default) -#define ARM_USART_PARITY_EVEN (1UL << ARM_USART_PARITY_Pos) ///< Even Parity -#define ARM_USART_PARITY_ODD (2UL << ARM_USART_PARITY_Pos) ///< Odd Parity - -/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/ -#define ARM_USART_STOP_BITS_Pos 14 -#define ARM_USART_STOP_BITS_Msk (3UL << ARM_USART_STOP_BITS_Pos) -#define ARM_USART_STOP_BITS_1 (0UL << ARM_USART_STOP_BITS_Pos) ///< 1 Stop bit (default) -#define ARM_USART_STOP_BITS_2 (1UL << ARM_USART_STOP_BITS_Pos) ///< 2 Stop bits -#define ARM_USART_STOP_BITS_1_5 (2UL << ARM_USART_STOP_BITS_Pos) ///< 1.5 Stop bits -#define ARM_USART_STOP_BITS_0_5 (3UL << ARM_USART_STOP_BITS_Pos) ///< 0.5 Stop bits - -/*----- USART Control Codes: Mode Parameters: Flow Control -----*/ -#define ARM_USART_FLOW_CONTROL_Pos 16 -#define ARM_USART_FLOW_CONTROL_Msk (3UL << ARM_USART_FLOW_CONTROL_Pos) -#define ARM_USART_FLOW_CONTROL_NONE (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default) -#define ARM_USART_FLOW_CONTROL_RTS (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control -#define ARM_USART_FLOW_CONTROL_CTS (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control -#define ARM_USART_FLOW_CONTROL_RTS_CTS (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control - -/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/ -#define ARM_USART_CPOL_Pos 18 -#define ARM_USART_CPOL_Msk (1UL << ARM_USART_CPOL_Pos) -#define ARM_USART_CPOL0 (0UL << ARM_USART_CPOL_Pos) ///< CPOL = 0 (default) -#define ARM_USART_CPOL1 (1UL << ARM_USART_CPOL_Pos) ///< CPOL = 1 - -/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/ -#define ARM_USART_CPHA_Pos 19 -#define ARM_USART_CPHA_Msk (1UL << ARM_USART_CPHA_Pos) -#define ARM_USART_CPHA0 (0UL << ARM_USART_CPHA_Pos) ///< CPHA = 0 (default) -#define ARM_USART_CPHA1 (1UL << ARM_USART_CPHA_Pos) ///< CPHA = 1 - - -/*----- USART Control Codes: Miscellaneous Controls -----*/ -#define ARM_USART_SET_DEFAULT_TX_VALUE (0x10UL << ARM_USART_CONTROL_Pos) ///< Set default Transmit value (Synchronous Receive only); arg = value -#define ARM_USART_SET_IRDA_PULSE (0x11UL << ARM_USART_CONTROL_Pos) ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period -#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Guard Time; arg = number of bit periods -#define ARM_USART_SET_SMART_CARD_CLOCK (0x13UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated -#define ARM_USART_CONTROL_SMART_CARD_NACK (0x14UL << ARM_USART_CONTROL_Pos) ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled -#define ARM_USART_CONTROL_TX (0x15UL << ARM_USART_CONTROL_Pos) ///< Transmitter; arg: 0=disabled, 1=enabled -#define ARM_USART_CONTROL_RX (0x16UL << ARM_USART_CONTROL_Pos) ///< Receiver; arg: 0=disabled, 1=enabled -#define ARM_USART_CONTROL_BREAK (0x17UL << ARM_USART_CONTROL_Pos) ///< Continuous Break transmission; arg: 0=disabled, 1=enabled -#define ARM_USART_ABORT_SEND (0x18UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Send -#define ARM_USART_ABORT_RECEIVE (0x19UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Receive -#define ARM_USART_ABORT_TRANSFER (0x1AUL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Transfer - - - -/****** USART specific error codes *****/ -#define ARM_USART_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported -#define ARM_USART_ERROR_BAUDRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified baudrate not supported -#define ARM_USART_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported -#define ARM_USART_ERROR_PARITY (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Parity not supported -#define ARM_USART_ERROR_STOP_BITS (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified number of Stop bits not supported -#define ARM_USART_ERROR_FLOW_CONTROL (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Flow Control not supported -#define ARM_USART_ERROR_CPOL (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock Polarity not supported -#define ARM_USART_ERROR_CPHA (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Clock Phase not supported - - -/** -\brief USART Status -*/ -typedef volatile struct _ARM_USART_STATUS { - uint32_t tx_busy : 1; ///< Transmitter busy flag - uint32_t rx_busy : 1; ///< Receiver busy flag - uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation) - uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation) - uint32_t rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation) - uint32_t rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation) - uint32_t rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation) - uint32_t reserved : 25; -} ARM_USART_STATUS; - -/** -\brief USART Modem Control -*/ -typedef enum _ARM_USART_MODEM_CONTROL { - ARM_USART_RTS_CLEAR, ///< Deactivate RTS - ARM_USART_RTS_SET, ///< Activate RTS - ARM_USART_DTR_CLEAR, ///< Deactivate DTR - ARM_USART_DTR_SET ///< Activate DTR -} ARM_USART_MODEM_CONTROL; - -/** -\brief USART Modem Status -*/ -typedef volatile struct _ARM_USART_MODEM_STATUS { - uint32_t cts : 1; ///< CTS state: 1=Active, 0=Inactive - uint32_t dsr : 1; ///< DSR state: 1=Active, 0=Inactive - uint32_t dcd : 1; ///< DCD state: 1=Active, 0=Inactive - uint32_t ri : 1; ///< RI state: 1=Active, 0=Inactive - uint32_t reserved : 28; -} ARM_USART_MODEM_STATUS; - - -/****** USART Event *****/ -#define ARM_USART_EVENT_SEND_COMPLETE (1UL << 0) ///< Send completed; however USART may still transmit data -#define ARM_USART_EVENT_RECEIVE_COMPLETE (1UL << 1) ///< Receive completed -#define ARM_USART_EVENT_TRANSFER_COMPLETE (1UL << 2) ///< Transfer completed -#define ARM_USART_EVENT_TX_COMPLETE (1UL << 3) ///< Transmit completed (optional) -#define ARM_USART_EVENT_TX_UNDERFLOW (1UL << 4) ///< Transmit data not available (Synchronous Slave) -#define ARM_USART_EVENT_RX_OVERFLOW (1UL << 5) ///< Receive data overflow -#define ARM_USART_EVENT_RX_TIMEOUT (1UL << 6) ///< Receive character timeout (optional) -#define ARM_USART_EVENT_RX_BREAK (1UL << 7) ///< Break detected on receive -#define ARM_USART_EVENT_RX_FRAMING_ERROR (1UL << 8) ///< Framing error detected on receive -#define ARM_USART_EVENT_RX_PARITY_ERROR (1UL << 9) ///< Parity error detected on receive -#define ARM_USART_EVENT_CTS (1UL << 10) ///< CTS state changed (optional) -#define ARM_USART_EVENT_DSR (1UL << 11) ///< DSR state changed (optional) -#define ARM_USART_EVENT_DCD (1UL << 12) ///< DCD state changed (optional) -#define ARM_USART_EVENT_RI (1UL << 13) ///< RI state changed (optional) - - -// Function documentation -/** - \fn ARM_DRIVER_VERSION ARM_USART_GetVersion (void) - \brief Get driver version. - \return \ref ARM_DRIVER_VERSION - - \fn ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void) - \brief Get driver capabilities - \return \ref ARM_USART_CAPABILITIES - - \fn int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event) - \brief Initialize USART Interface. - \param[in] cb_event Pointer to \ref ARM_USART_SignalEvent - \return \ref execution_status - - \fn int32_t ARM_USART_Uninitialize (void) - \brief De-initialize USART Interface. - \return \ref execution_status - - \fn int32_t ARM_USART_PowerControl (ARM_POWER_STATE state) - \brief Control USART Interface Power. - \param[in] state Power state - \return \ref execution_status - - \fn int32_t ARM_USART_Send (const void *data, uint32_t num) - \brief Start sending data to USART transmitter. - \param[in] data Pointer to buffer with data to send to USART transmitter - \param[in] num Number of data items to send - \return \ref execution_status - - \fn int32_t ARM_USART_Receive (void *data, uint32_t num) - \brief Start receiving data from USART receiver. - \param[out] data Pointer to buffer for data to receive from USART receiver - \param[in] num Number of data items to receive - \return \ref execution_status - - \fn int32_t ARM_USART_Transfer (const void *data_out, - void *data_in, - uint32_t num) - \brief Start sending/receiving data to/from USART transmitter/receiver. - \param[in] data_out Pointer to buffer with data to send to USART transmitter - \param[out] data_in Pointer to buffer for data to receive from USART receiver - \param[in] num Number of data items to transfer - \return \ref execution_status - - \fn uint32_t ARM_USART_GetTxCount (void) - \brief Get transmitted data count. - \return number of data items transmitted - - \fn uint32_t ARM_USART_GetRxCount (void) - \brief Get received data count. - \return number of data items received - - \fn int32_t ARM_USART_Control (uint32_t control, uint32_t arg) - \brief Control USART Interface. - \param[in] control Operation - \param[in] arg Argument of operation (optional) - \return common \ref execution_status and driver specific \ref usart_execution_status - - \fn ARM_USART_STATUS ARM_USART_GetStatus (void) - \brief Get USART status. - \return USART status \ref ARM_USART_STATUS - - \fn int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control) - \brief Set USART Modem Control line state. - \param[in] control \ref ARM_USART_MODEM_CONTROL - \return \ref execution_status - - \fn ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void) - \brief Get USART Modem Status lines state. - \return modem status \ref ARM_USART_MODEM_STATUS - - \fn void ARM_USART_SignalEvent (uint32_t event) - \brief Signal USART Events. - \param[in] event \ref USART_events notification mask - \return none -*/ - -typedef void (*ARM_USART_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event. - - -/** -\brief USART Device Driver Capabilities. -*/ -typedef struct _ARM_USART_CAPABILITIES { - uint32_t asynchronous : 1; ///< supports UART (Asynchronous) mode - uint32_t synchronous_master : 1; ///< supports Synchronous Master mode - uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode - uint32_t single_wire : 1; ///< supports UART Single-wire mode - uint32_t irda : 1; ///< supports UART IrDA mode - uint32_t smart_card : 1; ///< supports UART Smart Card mode - uint32_t smart_card_clock : 1; ///< Smart Card Clock generator available - uint32_t flow_control_rts : 1; ///< RTS Flow Control available - uint32_t flow_control_cts : 1; ///< CTS Flow Control available - uint32_t event_tx_complete : 1; ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE - uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT - uint32_t rts : 1; ///< RTS Line: 0=not available, 1=available - uint32_t cts : 1; ///< CTS Line: 0=not available, 1=available - uint32_t dtr : 1; ///< DTR Line: 0=not available, 1=available - uint32_t dsr : 1; ///< DSR Line: 0=not available, 1=available - uint32_t dcd : 1; ///< DCD Line: 0=not available, 1=available - uint32_t ri : 1; ///< RI Line: 0=not available, 1=available - uint32_t event_cts : 1; ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS - uint32_t event_dsr : 1; ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR - uint32_t event_dcd : 1; ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD - uint32_t event_ri : 1; ///< Signal RI change event: \ref ARM_USART_EVENT_RI - uint32_t reserved : 11; ///< Reserved (must be zero) -} ARM_USART_CAPABILITIES; - - -/** -\brief Access structure of the USART Driver. -*/ -typedef struct _ARM_DRIVER_USART { - ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USART_GetVersion : Get driver version. - ARM_USART_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities. - int32_t (*Initialize) (ARM_USART_SignalEvent_t cb_event); ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface. - int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface. - int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power. - int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter. - int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver. - int32_t (*Transfer) (const void *data_out, - void *data_in, - uint32_t num); ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART. - uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count. - uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count. - int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_USART_Control : Control USART Interface. - ARM_USART_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_USART_GetStatus : Get USART status. - int32_t (*SetModemControl) (ARM_USART_MODEM_CONTROL control); ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state. - ARM_USART_MODEM_STATUS (*GetModemStatus) (void); ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state. -} const ARM_DRIVER_USART; - -#ifdef __cplusplus -} -#endif - -#endif /* DRIVER_USART_H_ */ From 3df6695ab26c9254471b3da3c3efa31b7927dbe3 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 23 Oct 2021 00:49:32 -0500 Subject: [PATCH 454/617] nrf52820_hic: add nrf52820.md to index --- docs/hic/README.md | 2 +- docs/hic/nrf52820.md | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/docs/hic/README.md b/docs/hic/README.md index 2b49b72f7..5b097759e 100644 --- a/docs/hic/README.md +++ b/docs/hic/README.md @@ -10,6 +10,6 @@ | [lpc4322](lpc4322.md) | M4 | 96 MHz | 256 KB | 256 KB | HS | | [lpc55xx](lpc55xx.md) | M33 | 150 MHz | 272 KB | 320 KB | HS | | [max32625](max32625.md) | M4 | 96 MHz | 160 KB | 512 KB | FS | +| [nrf52820](nrf52820.md) | M4 | 64 MHz | 32 KB | 256 KB | FS | | [sam3u2c](sam3u2c.md) | M3 | 96 MHz | 32 KB | 128 KB | HS | | [stm32f103xb](stm32f103xb.md) | M3 | 72 Mhz | 20 KB | 128 KB | FS | - diff --git a/docs/hic/nrf52820.md b/docs/hic/nrf52820.md index 3ef417af7..81477a81f 100644 --- a/docs/hic/nrf52820.md +++ b/docs/hic/nrf52820.md @@ -1,6 +1,7 @@ # nrf52820 HIC -Based on Nordic [nRF52820](https://www.nordicsemi.com/Products/nRF52820): +Based on Nordic [nRF52820](https://www.nordicsemi.com/Products/nRF52820) +and [nRF52833](https://www.nordicsemi.com/Products/nRF52833): - Cortex-M4 64 MHz - 256 KB Flash - 32 KB RAM From f872aa45cd24e8c048c76c40509a6f70c02fbcc3 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 19 Oct 2021 22:32:44 -0500 Subject: [PATCH 455/617] nrf52820_hic: add nrf52820_microbit_if --- projects.yaml | 4 ++++ records/board/microbitv2_nrf52820.yaml | 17 +++++++++++++++++ source/board/microbitv2/microbitv2.c | 26 ++++++++++++++++++++++++-- 3 files changed, 45 insertions(+), 2 deletions(-) create mode 100644 records/board/microbitv2_nrf52820.yaml diff --git a/projects.yaml b/projects.yaml index 69d217c44..2510a4fb7 100644 --- a/projects.yaml +++ b/projects.yaml @@ -498,6 +498,10 @@ projects: - *module_if - *module_hic_max32625 - records/board/max78000fthr.yaml + nrf52820_microbit_if: + - *module_if + - *module_hic_nrf52820 + - records/board/microbitv2_nrf52820.yaml sam3u2c_mkit_dk_dongle_nrf5x_if: - *module_if - *module_hic_sam3u2c diff --git a/records/board/microbitv2_nrf52820.yaml b/records/board/microbitv2_nrf52820.yaml new file mode 100644 index 000000000..cbbd0f7e7 --- /dev/null +++ b/records/board/microbitv2_nrf52820.yaml @@ -0,0 +1,17 @@ +common: + macros: + - HID_LED_DEF=GPIO_LED_ON + - CDC_LED_DEF=GPIO_LED_ON + - MSC_LED_DEF=GPIO_LED_ON + - USB_PROD_STR="BBC micro:bit CMSIS-DAP" + # - DELAY_FAST_CYCLES=2U # Fast delay needed to reach 8MHz SWD clock speed + # - DAP_DEFAULT_SWJ_CLOCK=8000000 + - BOARD_EXTRA_BUFFER=100 + # includes: + # - source/board/microbitv2 + sources: + board: + - source/board/microbitv2/microbitv2.c + target: + - source/family/nordic/nrf5x/target.c + - source/family/nordic/target_reset_nrf52.c diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index b8c69fa98..7daab28e7 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -19,12 +19,15 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - -#include "fsl_device_registers.h" + #include "IO_Config.h" #include "DAP.h" #include "target_family.h" #include "target_board.h" + +#if defined(INTERFACE_KL27Z) + +#include "fsl_device_registers.h" #include "flexio_pwm.h" #include "gpio.h" #include "power.h" @@ -582,6 +585,25 @@ uint8_t board_detect_incompatible_image(const uint8_t *data, uint32_t size) return result == 0; } +#elif defined(INTERFACE_NRF52820) +#include "device.h" + +const char * const board_id_mb_2_0 = "9903"; +const char * const board_id_mb_2_0x = "9905"; +extern target_cfg_t target_device_nrf52_64; + +static void prerun_board_config(void) +{ + target_device = target_device_nrf52_64; + target_device.rt_board_id = board_id_mb_2_0; + if (NRF_FICR->INFO.PART == 0x52833) { + target_device.rt_board_id = board_id_mb_2_0x; // nRF52833 + } else { + target_device.rt_board_id = board_id_mb_2_0; // nRF52820 + } +} +#endif + // USB HID override function return 1 if the activity is trivial or response is null uint8_t usbd_hid_no_activity(uint8_t *buf) { From 9b361a2f4195706a23472828342e4875d2a50e42 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Wed, 15 Sep 2021 19:44:43 +0100 Subject: [PATCH 456/617] nrf52820_hic: Update board IDs used. --- source/board/microbitv2/microbitv2.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 7daab28e7..0a30b9f12 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -588,18 +588,19 @@ uint8_t board_detect_incompatible_image(const uint8_t *data, uint32_t size) #elif defined(INTERFACE_NRF52820) #include "device.h" -const char * const board_id_mb_2_0 = "9903"; -const char * const board_id_mb_2_0x = "9905"; +const char * const board_id_mb_2_0_default = "9903"; +const char * const board_id_mb_2_2_833 = "9905"; +const char * const board_id_mb_2_2_820 = "9906"; extern target_cfg_t target_device_nrf52_64; static void prerun_board_config(void) { target_device = target_device_nrf52_64; - target_device.rt_board_id = board_id_mb_2_0; + target_device.rt_board_id = board_id_mb_2_0_default; if (NRF_FICR->INFO.PART == 0x52833) { - target_device.rt_board_id = board_id_mb_2_0x; // nRF52833 - } else { - target_device.rt_board_id = board_id_mb_2_0; // nRF52820 + target_device.rt_board_id = board_id_mb_2_2_833; // nRF52833 + } else if (NRF_FICR->INFO.PART == 0x52820) { + target_device.rt_board_id = board_id_mb_2_2_820; // nRF52820 } } #endif From e2a2e47ab24c8d254d616eaf9a858d0195ad6805 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 21 Sep 2021 00:11:46 -0500 Subject: [PATCH 457/617] nrf52820_hic: fix microbit board after rebase --- records/board/microbitv2_nrf52820.yaml | 2 +- source/board/microbitv2/microbitv2.c | 9 ++++----- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/records/board/microbitv2_nrf52820.yaml b/records/board/microbitv2_nrf52820.yaml index cbbd0f7e7..dfecfa05e 100644 --- a/records/board/microbitv2_nrf52820.yaml +++ b/records/board/microbitv2_nrf52820.yaml @@ -13,5 +13,5 @@ common: board: - source/board/microbitv2/microbitv2.c target: - - source/family/nordic/nrf5x/target.c + - source/family/nordic/nrf52/target.c - source/family/nordic/target_reset_nrf52.c diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 0a30b9f12..c0740ab30 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -591,16 +591,15 @@ uint8_t board_detect_incompatible_image(const uint8_t *data, uint32_t size) const char * const board_id_mb_2_0_default = "9903"; const char * const board_id_mb_2_2_833 = "9905"; const char * const board_id_mb_2_2_820 = "9906"; -extern target_cfg_t target_device_nrf52_64; +extern target_cfg_t target_device_nrf52833; static void prerun_board_config(void) { - target_device = target_device_nrf52_64; - target_device.rt_board_id = board_id_mb_2_0_default; + g_board_info.target_cfg->rt_board_id = board_id_mb_2_0_default; if (NRF_FICR->INFO.PART == 0x52833) { - target_device.rt_board_id = board_id_mb_2_2_833; // nRF52833 + g_board_info.target_cfg->rt_board_id = board_id_mb_2_2_833; // nRF52833 } else if (NRF_FICR->INFO.PART == 0x52820) { - target_device.rt_board_id = board_id_mb_2_2_820; // nRF52820 + g_board_info.target_cfg->rt_board_id = board_id_mb_2_2_820; // nRF52820 } } #endif From 9cf30c4ccbfcff581932de3287a27bf3e90dfeec Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 22 Sep 2021 01:07:33 -0500 Subject: [PATCH 458/617] nrf52820_hic: enable uhex support for microbitv2 on nrf52820 --- source/board/microbitv2/microbitv2.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index c0740ab30..ebb5d02a2 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -25,6 +25,9 @@ #include "target_family.h" #include "target_board.h" +uint16_t board_id_hex_min = 0x9903; +uint16_t board_id_hex = 0; + #if defined(INTERFACE_KL27Z) #include "fsl_device_registers.h" @@ -54,9 +57,6 @@ const char * const board_id_mb_2_0 = "9903"; const char * const board_id_mb_2_1 = "9904"; -uint16_t board_id_hex_min = 0x9903; -uint16_t board_id_hex = 0; - volatile uint8_t wake_from_reset = 0; volatile uint8_t wake_from_usb = 0; volatile bool usb_pc_connected = false; @@ -596,10 +596,13 @@ extern target_cfg_t target_device_nrf52833; static void prerun_board_config(void) { g_board_info.target_cfg->rt_board_id = board_id_mb_2_0_default; + board_id_hex = 0x9903; if (NRF_FICR->INFO.PART == 0x52833) { g_board_info.target_cfg->rt_board_id = board_id_mb_2_2_833; // nRF52833 + board_id_hex = 0x9905; } else if (NRF_FICR->INFO.PART == 0x52820) { g_board_info.target_cfg->rt_board_id = board_id_mb_2_2_820; // nRF52820 + board_id_hex = 0x9906; } } #endif From 587a39539624a1dfb40c5d6c4affc7e7cf7d8fb2 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Fri, 24 Sep 2021 18:36:01 +0100 Subject: [PATCH 459/617] nrf52820_hic: Combine microbit board ID configuration. --- source/board/microbitv2/microbitv2.c | 100 +++++++++++++++----------- source/daplink/drag-n-drop/intelhex.c | 4 +- 2 files changed, 60 insertions(+), 44 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index ebb5d02a2..dbc5e5b43 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -25,9 +25,6 @@ #include "target_family.h" #include "target_board.h" -uint16_t board_id_hex_min = 0x9903; -uint16_t board_id_hex = 0; - #if defined(INTERFACE_KL27Z) #include "fsl_device_registers.h" @@ -54,9 +51,30 @@ uint16_t board_id_hex = 0; #include "flash_intf.h" #endif -const char * const board_id_mb_2_0 = "9903"; -const char * const board_id_mb_2_1 = "9904"; +#elif defined(INTERFACE_NRF52820) + +#include "device.h" + +#endif + +const char * const board_id_mb_2_default = "9903"; +const char * const board_id_mb_2_0 = "9904"; +const char * const board_id_mb_2_2_833 = "9905"; +const char * const board_id_mb_2_2_820 = "9906"; + +typedef enum { + BOARD_VERSION_2_DEF = 0x9903, + BOARD_VERSION_2_0 = 0x9904, + BOARD_VERSION_2_2_833 = 0x9905, + BOARD_VERSION_2_2_820 = 0x9906, +} mb_version_t; +uint16_t board_id_hex_default = BOARD_VERSION_2_DEF; +uint16_t board_id_hex = BOARD_VERSION_2_DEF; + +extern target_cfg_t target_device_nrf52833; + +#if defined(INTERFACE_KL27Z) volatile uint8_t wake_from_reset = 0; volatile uint8_t wake_from_usb = 0; volatile bool usb_pc_connected = false; @@ -78,12 +96,6 @@ flashConfig_t gflashConfig = { .fileEncWindowEnd = 0, }; -typedef enum { - BOARD_VERSION_2_0 = 0, - BOARD_VERSION_2_1 = 1, -} mb_version_t; - -extern target_cfg_t target_device_nrf52833; extern main_usb_connect_t usb_state; extern bool go_to_sleep; extern i2c_slave_handle_t g_s_handle; @@ -105,12 +117,12 @@ static uint8_t reset_pressed = 0; // Board Rev ID detection. Reads BRD_REV_ID voltage // Depends on gpio_init() to have been executed already -static mb_version_t read_brd_rev_id_pin(void) { +static mb_version_t read_brd_rev_id(void) { gpio_pin_config_t pin_config = { .pinDirection = kGPIO_DigitalOutput, .outputLogic = 0U }; - mb_version_t board_version = BOARD_VERSION_2_0; + mb_version_t board_version = BOARD_VERSION_2_DEF; uint32_t board_rev_id_adc = 0; uint32_t board_rev_id_mv = 0; @@ -152,27 +164,47 @@ static mb_version_t read_brd_rev_id_pin(void) { // 5. Identify board ID depending on voltage if ( board_rev_id_mv > BRD_ID_1_LOWER_THR_V && board_rev_id_mv < BRD_ID_1_UPPER_THR_V) { - board_version = BOARD_VERSION_2_1; - } else { board_version = BOARD_VERSION_2_0; + } else { + board_version = BOARD_VERSION_2_DEF; } return board_version; } +#elif defined(INTERFACE_NRF52820) + +#include "device.h" + +static mb_version_t read_brd_rev_id(void) +{ + switch (NRF_FICR->INFO.PART) { + case 0x52833: return BOARD_VERSION_2_2_833; + case 0x52820: return BOARD_VERSION_2_2_820; + default: return BOARD_VERSION_2_DEF; + } +} +#endif + static void set_board_id(mb_version_t board_version) { switch (board_version) { case BOARD_VERSION_2_0: g_board_info.target_cfg->rt_board_id = board_id_mb_2_0; - board_id_hex = 0x9903; + board_id_hex = BOARD_VERSION_2_0; + break; + case BOARD_VERSION_2_2_833: + g_board_info.target_cfg->rt_board_id = board_id_mb_2_2_833; + board_id_hex = BOARD_VERSION_2_2_833; break; - case BOARD_VERSION_2_1: - g_board_info.target_cfg->rt_board_id = board_id_mb_2_1; - board_id_hex = 0x9904; + case BOARD_VERSION_2_2_820: + g_board_info.target_cfg->rt_board_id = board_id_mb_2_2_820; + board_id_hex = BOARD_VERSION_2_2_820; break; + case BOARD_VERSION_2_DEF: + /* Intentional fall-through */ default: - g_board_info.target_cfg->rt_board_id = board_id_mb_2_0; - board_id_hex = 0x9903; + g_board_info.target_cfg->rt_board_id = board_id_mb_2_default; + board_id_hex = BOARD_VERSION_2_DEF; break; } } @@ -187,9 +219,13 @@ static inline uint8_t get_led_gamma(uint8_t brightness) { // Called in main_task() to init before USB and files are configured static void prerun_board_config(void) { - mb_version_t board_version = read_brd_rev_id_pin(); + mb_version_t board_version = read_brd_rev_id(); set_board_id(board_version); +#if defined(INTERFACE_NRF52820) +} +#elif defined(INTERFACE_KL27Z) + // init power monitoring power_init(); pwr_mon_init(); @@ -585,26 +621,6 @@ uint8_t board_detect_incompatible_image(const uint8_t *data, uint32_t size) return result == 0; } -#elif defined(INTERFACE_NRF52820) -#include "device.h" - -const char * const board_id_mb_2_0_default = "9903"; -const char * const board_id_mb_2_2_833 = "9905"; -const char * const board_id_mb_2_2_820 = "9906"; -extern target_cfg_t target_device_nrf52833; - -static void prerun_board_config(void) -{ - g_board_info.target_cfg->rt_board_id = board_id_mb_2_0_default; - board_id_hex = 0x9903; - if (NRF_FICR->INFO.PART == 0x52833) { - g_board_info.target_cfg->rt_board_id = board_id_mb_2_2_833; // nRF52833 - board_id_hex = 0x9905; - } else if (NRF_FICR->INFO.PART == 0x52820) { - g_board_info.target_cfg->rt_board_id = board_id_mb_2_2_820; // nRF52820 - board_id_hex = 0x9906; - } -} #endif // USB HID override function return 1 if the activity is trivial or response is null diff --git a/source/daplink/drag-n-drop/intelhex.c b/source/daplink/drag-n-drop/intelhex.c index 3bf059cbb..5a20ef2d4 100644 --- a/source/daplink/drag-n-drop/intelhex.c +++ b/source/daplink/drag-n-drop/intelhex.c @@ -87,7 +87,7 @@ static uint32_t next_address_to_write = 0; static uint8_t low_nibble = 0, idx = 0, record_processed = 0, load_unaligned_record = 0, skip_until_aligned = 0; static uint16_t binary_version = 0; uint16_t board_id_hex __WEAK; -uint16_t board_id_hex_min __WEAK; +uint16_t board_id_hex_default __WEAK; void reset_hex_parser(void) { @@ -170,7 +170,7 @@ hexfile_parse_status_t parse_hex_blob(const uint8_t *hex_blob, const uint32_t he case DATA_RECORD: case CUSTOM_DATA_RECORD: - if (binary_version == 0 || (binary_version >= board_id_hex_min && binary_version <= board_id_hex)){ + if (binary_version == 0 || binary_version == board_id_hex_default || binary_version == board_id_hex) { // Only save data from the correct binary // verify this is a continous block of memory or need to exit and dump if (((next_address_to_write & 0xffff0000) | line.address) != next_address_to_write) { From 1954fa46a3d6a23edf90af1ab5d410c37b17f1e0 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Tue, 28 Sep 2021 12:11:32 +0100 Subject: [PATCH 460/617] nrf52820_hic: Separate sources for different micro:bit V2 interface uC. Rename the flex_pwm.h to a more generic pwm.h. Remove Kl27 specific parts from power.h. Move KL27 .c files into a new freescale subdirectory. Created a new subdirectory for nordic. --- records/board/microbitv2.yaml | 4 +- records/board/microbitv2_nrf52820.yaml | 7 +- source/board/microbitv2/i2c_commands.c | 10 ++- source/board/microbitv2/i2c_commands.h | 3 +- .../{ => kl27z}/IO_Config_Override.h | 0 .../board/microbitv2/{ => kl27z}/flexio_pwm.c | 12 +-- source/board/microbitv2/{ => kl27z}/power.c | 24 +++++- source/board/microbitv2/{ => kl27z}/pwr_mon.c | 0 source/board/microbitv2/microbitv2.c | 76 +++++++++---------- .../microbitv2/nrf52820/i2c_commands_empty.c | 27 +++++++ source/board/microbitv2/nrf52820/power.c | 37 +++++++++ source/board/microbitv2/nrf52820/pwm.c | 42 ++++++++++ source/board/microbitv2/nrf52820/pwr_mon.c | 45 +++++++++++ source/board/microbitv2/power.h | 29 +++---- .../board/microbitv2/{flexio_pwm.h => pwm.h} | 16 ++-- 15 files changed, 248 insertions(+), 84 deletions(-) rename source/board/microbitv2/{ => kl27z}/IO_Config_Override.h (100%) rename source/board/microbitv2/{ => kl27z}/flexio_pwm.c (96%) rename source/board/microbitv2/{ => kl27z}/power.c (91%) rename source/board/microbitv2/{ => kl27z}/pwr_mon.c (100%) create mode 100644 source/board/microbitv2/nrf52820/i2c_commands_empty.c create mode 100644 source/board/microbitv2/nrf52820/power.c create mode 100644 source/board/microbitv2/nrf52820/pwm.c create mode 100644 source/board/microbitv2/nrf52820/pwr_mon.c rename source/board/microbitv2/{flexio_pwm.h => pwm.h} (76%) diff --git a/records/board/microbitv2.yaml b/records/board/microbitv2.yaml index 2207c733f..03faed711 100644 --- a/records/board/microbitv2.yaml +++ b/records/board/microbitv2.yaml @@ -10,10 +10,12 @@ common: - BOARD_USB_BMAXPOWER=0x96 - BOARD_EXTRA_BUFFER=100 includes: - - source/board/microbitv2 + - source/board/microbitv2/ + - source/board/microbitv2/kl27z/ sources: board: - source/board/microbitv2/ + - source/board/microbitv2/kl27z/ target: - source/family/nordic/nrf52/target.c - source/family/nordic/target_reset_nrf52.c diff --git a/records/board/microbitv2_nrf52820.yaml b/records/board/microbitv2_nrf52820.yaml index dfecfa05e..ce8b3e31c 100644 --- a/records/board/microbitv2_nrf52820.yaml +++ b/records/board/microbitv2_nrf52820.yaml @@ -7,11 +7,12 @@ common: # - DELAY_FAST_CYCLES=2U # Fast delay needed to reach 8MHz SWD clock speed # - DAP_DEFAULT_SWJ_CLOCK=8000000 - BOARD_EXTRA_BUFFER=100 - # includes: - # - source/board/microbitv2 + includes: + - source/board/microbitv2/ sources: board: - - source/board/microbitv2/microbitv2.c + - source/board/microbitv2/ + - source/board/microbitv2/nrf52820/ target: - source/family/nordic/nrf52/target.c - source/family/nordic/target_reset_nrf52.c diff --git a/source/board/microbitv2/i2c_commands.c b/source/board/microbitv2/i2c_commands.c index d34c05bde..086ff55b3 100644 --- a/source/board/microbitv2/i2c_commands.c +++ b/source/board/microbitv2/i2c_commands.c @@ -19,6 +19,8 @@ * limitations under the License. */ +#if defined(INTERFACE_KL27Z) + #include "i2c_commands.h" #include "fsl_i2c.h" #include "fsl_clock.h" @@ -61,7 +63,7 @@ extern bool i2c_allow_sleep; extern uint16_t board_id_hex; extern power_source_t power_source; extern main_usb_connect_t usb_state; -extern app_power_mode_t interface_power_mode; +extern microbit_if_power_mode_t interface_power_mode; extern bool power_led_sleep_state_on; extern bool automatic_sleep_on; extern main_shutdown_state_t main_shutdown_state; @@ -359,8 +361,8 @@ static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { break; case gPowerMode_c: if (pI2cCommand->cmdData.writeReqCmd.dataSize == 1) { - if (pI2cCommand->cmdData.writeReqCmd.data[0] == kAPP_PowerModeVlls0) { - interface_power_mode = kAPP_PowerModeVlls0; + if (pI2cCommand->cmdData.writeReqCmd.data[0] == MB_POWER_DOWN) { + interface_power_mode = MB_POWER_DOWN; i2cResponse.cmdId = gWriteResponse_c; i2cResponse.cmdData.writeRspCmd.propertyId = pI2cCommand->cmdData.writeReqCmd.propertyId; } else { @@ -743,3 +745,5 @@ static void i2c_read_flash_callback(uint8_t* pData, uint8_t size) { // Release COMBINED_SENSOR_INT PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); } + +#endif diff --git a/source/board/microbitv2/i2c_commands.h b/source/board/microbitv2/i2c_commands.h index 5f975cca6..816ef1bfd 100644 --- a/source/board/microbitv2/i2c_commands.h +++ b/source/board/microbitv2/i2c_commands.h @@ -26,7 +26,8 @@ #include "cmsis_compiler.h" #include "virtual_fs.h" -#include "fsl_common.h" +// #include "fsl_common.h" +typedef int32_t status_t; #ifdef __cplusplus extern "C" { diff --git a/source/board/microbitv2/IO_Config_Override.h b/source/board/microbitv2/kl27z/IO_Config_Override.h similarity index 100% rename from source/board/microbitv2/IO_Config_Override.h rename to source/board/microbitv2/kl27z/IO_Config_Override.h diff --git a/source/board/microbitv2/flexio_pwm.c b/source/board/microbitv2/kl27z/flexio_pwm.c similarity index 96% rename from source/board/microbitv2/flexio_pwm.c rename to source/board/microbitv2/kl27z/flexio_pwm.c index b0450d359..b15ec75ca 100644 --- a/source/board/microbitv2/flexio_pwm.c +++ b/source/board/microbitv2/kl27z/flexio_pwm.c @@ -22,7 +22,7 @@ #include "fsl_flexio.h" #include "fsl_common.h" #include "fsl_port.h" -#include "flexio_pwm.h" +#include "pwm.h" /******************************************************************************* * Definitions @@ -45,7 +45,7 @@ /******************************************************************************* * Code ******************************************************************************/ -void flexio_pwm_init(void) +void pwm_init(void) { flexio_config_t fxioUserConfig; @@ -69,7 +69,7 @@ void flexio_pwm_init(void) FLEXIO_Init(DEMO_FLEXIO_BASEADDR, &fxioUserConfig); } -void flexio_pwm_set_dutycycle(uint8_t duty) +void pwm_set_dutycycle(uint8_t duty) { uint32_t freq_Hz = DEMO_FLEXIO_FREQUENCY; @@ -96,7 +96,7 @@ void flexio_pwm_set_dutycycle(uint8_t duty) PORT_SetPinMux(PIN_RED_LED_PORT, PIN_RED_LED_BIT, kPORT_MuxAsGpio); } else { - flexio_pwm_init_pins(); + pwm_init_pins(); } /* Configure the timer DEMO_FLEXIO_TIMER_CH for generating PWM */ @@ -132,12 +132,12 @@ void flexio_pwm_set_dutycycle(uint8_t duty) DEMO_FLEXIO_BASEADDR->TIMCTL[DEMO_FLEXIO_TIMER_CH] |= FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitPWM); } -void flexio_pwm_init_pins(void) +void pwm_init_pins(void) { PORT_SetPinMux(PIN_RED_LED_PORT, PIN_RED_LED_BIT, kPORT_MuxAlt6); } -void flexio_pwm_deinit_pins(void) +void pwm_deinit_pins(void) { PORT_SetPinMux(PIN_RED_LED_PORT, PIN_RED_LED_BIT, kPORT_PinDisabledOrAnalog); } diff --git a/source/board/microbitv2/power.c b/source/board/microbitv2/kl27z/power.c similarity index 91% rename from source/board/microbitv2/power.c rename to source/board/microbitv2/kl27z/power.c index 1ee666670..73afa4786 100644 --- a/source/board/microbitv2/power.c +++ b/source/board/microbitv2/kl27z/power.c @@ -34,6 +34,26 @@ #include "i2c_commands.h" #include "rl_usb.h" +/******************************************************************************* + * Enums and macros + ******************************************************************************/ +/* Power mode definition used in application. */ +typedef enum _app_power_mode +{ + kAPP_PowerModeMin = 0, + kAPP_PowerModeRun, /* Normal RUN mode */ + kAPP_PowerModeWait, /* WAIT mode. */ + kAPP_PowerModeStop, /* STOP mode. */ + kAPP_PowerModeVlpr, /* VLPR mode. */ + kAPP_PowerModeVlpw, /* VLPW mode. */ + kAPP_PowerModeVlps, /* VLPS mode. */ + kAPP_PowerModeLls, /* LLS mode. */ + kAPP_PowerModeVlls0, /* VLLS0 mode. */ + kAPP_PowerModeVlls1, /* VLLS1 mode. */ + kAPP_PowerModeVlls3, /* VLLS3 mode. */ + kAPP_PowerModeMax +} app_power_mode_t; + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -124,12 +144,12 @@ void power_init(void) NVIC_EnableIRQ(PORTC_PORTD_IRQn); } -void power_enter_VLLS0() +void power_down() { power_enter_mode(kAPP_PowerModeVlls0); } -void power_enter_VLPS() +void power_sleep() { power_enter_mode(kAPP_PowerModeVlps); } diff --git a/source/board/microbitv2/pwr_mon.c b/source/board/microbitv2/kl27z/pwr_mon.c similarity index 100% rename from source/board/microbitv2/pwr_mon.c rename to source/board/microbitv2/kl27z/pwr_mon.c diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index dbc5e5b43..9b8fc9caa 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -19,42 +19,38 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + #include "IO_Config.h" #include "DAP.h" #include "target_family.h" #include "target_board.h" - -#if defined(INTERFACE_KL27Z) - -#include "fsl_device_registers.h" -#include "flexio_pwm.h" #include "gpio.h" -#include "power.h" #include "rl_usb.h" -#include "pwr_mon.h" +#include "flash_manager.h" +#include "virtual_fs.h" +#include "vfs_manager.h" +#include "device.h" #include "main_interface.h" + +#include "microbitv2.h" +#include "pwm.h" +#include "power.h" +#include "pwr_mon.h" #include "i2c_commands.h" +#include "led_error_app.h" + +#if defined(INTERFACE_KL27Z) + #include "adc.h" #include "fsl_port.h" #include "fsl_gpio.h" #include "fsl_i2c.h" -#include "led_error_app.h" -#include "flash_manager.h" -#include "virtual_fs.h" -#include "vfs_manager.h" -#include "cortex_m.h" #include "fsl_flash.h" -#include "microbitv2.h" -#ifdef DRAG_N_DROP_SUPPORT -#include "flash_intf.h" #endif -#elif defined(INTERFACE_NRF52820) - -#include "device.h" - +#ifdef DRAG_N_DROP_SUPPORT +#include "flash_intf.h" #endif const char * const board_id_mb_2_default = "9903"; @@ -74,19 +70,19 @@ uint16_t board_id_hex = BOARD_VERSION_2_DEF; extern target_cfg_t target_device_nrf52833; -#if defined(INTERFACE_KL27Z) volatile uint8_t wake_from_reset = 0; volatile uint8_t wake_from_usb = 0; volatile bool usb_pc_connected = false; uint8_t i2c_wake_timeout = 0; bool i2c_allow_sleep = true; power_source_t power_source; -app_power_mode_t interface_power_mode = kAPP_PowerModeVlls0; +microbit_if_power_mode_t interface_power_mode = MB_POWER_DOWN; bool power_led_sleep_state_on = PWR_LED_SLEEP_STATE_DEFAULT; bool automatic_sleep_on = AUTOMATIC_SLEEP_DEFAULT; main_shutdown_state_t main_shutdown_state = MAIN_SHUTDOWN_WAITING; bool do_remount = false; +#if defined(INTERFACE_KL27Z) flashConfig_t gflashConfig = { .key = CFG_KEY, .fileName = FLASH_CFG_FILENAME, @@ -100,6 +96,7 @@ extern main_usb_connect_t usb_state; extern bool go_to_sleep; extern i2c_slave_handle_t g_s_handle; extern flash_config_t g_flash; +#endif extern void main_powerdown_event(void); @@ -115,6 +112,7 @@ static uint16_t gpio_reset_count = 0; // button state static uint8_t reset_pressed = 0; +#if defined(INTERFACE_KL27Z) // Board Rev ID detection. Reads BRD_REV_ID voltage // Depends on gpio_init() to have been executed already static mb_version_t read_brd_rev_id(void) { @@ -174,8 +172,6 @@ static mb_version_t read_brd_rev_id(void) { #elif defined(INTERFACE_NRF52820) -#include "device.h" - static mb_version_t read_brd_rev_id(void) { switch (NRF_FICR->INFO.PART) { @@ -222,18 +218,14 @@ static void prerun_board_config(void) mb_version_t board_version = read_brd_rev_id(); set_board_id(board_version); -#if defined(INTERFACE_NRF52820) -} -#elif defined(INTERFACE_KL27Z) - // init power monitoring power_init(); pwr_mon_init(); power_source = pwr_mon_get_power_source(); - flexio_pwm_init(); - flexio_pwm_init_pins(); + pwm_init(); + pwm_init_pins(); if (power_source == PWR_BATT_ONLY){ // Turn on the red LED with low duty cycle to conserve power. @@ -244,10 +236,14 @@ static void prerun_board_config(void) power_led_max_duty_cycle = PWR_LED_ON_MAX_BRIGHTNESS; } uint8_t gamma_led_dc = get_led_gamma(power_led_max_duty_cycle); - flexio_pwm_set_dutycycle(gamma_led_dc); + pwm_set_dutycycle(gamma_led_dc); i2c_initialize(); +#if defined(INTERFACE_NRF52820) +} +#elif defined(INTERFACE_KL27Z) + gpio_pin_config_t pin_config = { .pinDirection = kGPIO_DigitalOutput, .outputLogic = 0U @@ -356,7 +352,7 @@ void board_30ms_hook() // Enter light sleep if USB is not enumerated and main_shutdown_state is idle if (usb_state == USB_DISCONNECTED && !usb_pc_connected && main_shutdown_state == MAIN_SHUTDOWN_WAITING && automatic_sleep_on == true && g_s_handle.isBusy == false && i2c_wake_timeout == 0 && i2c_allow_sleep) { - interface_power_mode = kAPP_PowerModeVlps; + interface_power_mode = MB_POWER_SLEEP; main_shutdown_state = MAIN_SHUTDOWN_REQUESTED; } @@ -419,9 +415,9 @@ void board_30ms_hook() // In VLLS0, set the LED either ON or LOW, depending on power_led_sleep_state_on // When the duty cycle is 0% or 100%, the FlexIO driver will configure the pin as GPIO - if (power_led_sleep_state_on == true && interface_power_mode == kAPP_PowerModeVlls0) { + if (power_led_sleep_state_on == true && interface_power_mode == MB_POWER_DOWN) { shutdown_led_dc = PWR_LED_ON_MAX_BRIGHTNESS; - } else if (power_led_sleep_state_on == true && interface_power_mode == kAPP_PowerModeVlps) { + } else if (power_led_sleep_state_on == true && interface_power_mode == MB_POWER_SLEEP) { shutdown_led_dc = PWR_LED_ON_BATT_BRIGHTNESS; } else { @@ -481,9 +477,9 @@ void board_30ms_hook() // Use gamma curve except in final fade if (main_shutdown_state != MAIN_SHUTDOWN_REACHED_FADE) { uint8_t gamma_led_dc = get_led_gamma(shutdown_led_dc); - flexio_pwm_set_dutycycle(gamma_led_dc); + pwm_set_dutycycle(gamma_led_dc); } else { - flexio_pwm_set_dutycycle(final_fade_led_dc); + pwm_set_dutycycle(final_fade_led_dc); } // Remount if requested. @@ -496,11 +492,11 @@ void board_30ms_hook() void board_handle_powerdown() { switch(interface_power_mode){ - case kAPP_PowerModeVlps: - power_enter_VLPS(); + case MB_POWER_SLEEP: + power_sleep(); break; - case kAPP_PowerModeVlls0: - power_enter_VLLS0(); + case MB_POWER_DOWN: + power_down(); break; default: break; diff --git a/source/board/microbitv2/nrf52820/i2c_commands_empty.c b/source/board/microbitv2/nrf52820/i2c_commands_empty.c new file mode 100644 index 000000000..26b6e7f94 --- /dev/null +++ b/source/board/microbitv2/nrf52820/i2c_commands_empty.c @@ -0,0 +1,27 @@ +/** + * @file i2c_commands.c + * @brief + * + * DAPLink Interface Firmware + * Copyright 2021 Micro:bit Educational Foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "i2c_commands.h" + +void i2c_initialize() +{ + // TODO +} diff --git a/source/board/microbitv2/nrf52820/power.c b/source/board/microbitv2/nrf52820/power.c new file mode 100644 index 000000000..916cd1d37 --- /dev/null +++ b/source/board/microbitv2/nrf52820/power.c @@ -0,0 +1,37 @@ +/** + * @file power.c + * @brief + * + * DAPLink Interface Firmware + * Copyright 2021 Micro:bit Educational Foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "power.h" + +void power_init() +{ + // TODO +} + +void power_down() +{ + // TODO +} + +void power_sleep() +{ + // TODO +} diff --git a/source/board/microbitv2/nrf52820/pwm.c b/source/board/microbitv2/nrf52820/pwm.c new file mode 100644 index 000000000..6efe01c3d --- /dev/null +++ b/source/board/microbitv2/nrf52820/pwm.c @@ -0,0 +1,42 @@ +/** + * @file pwm.c + * @brief + * + * DAPLink Interface Firmware + * Copyright 2021 Micro:bit Educational Foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "pwm.h" + +void pwm_init() +{ + // TODO +} + +void pwm_init_pins() +{ + // TODO +} + +void pwm_deinit_pins() +{ + // TODO +} + +void pwm_set_dutycycle(uint8_t duty) +{ + // TODO +} diff --git a/source/board/microbitv2/nrf52820/pwr_mon.c b/source/board/microbitv2/nrf52820/pwr_mon.c new file mode 100644 index 000000000..a2d97c6e3 --- /dev/null +++ b/source/board/microbitv2/nrf52820/pwr_mon.c @@ -0,0 +1,45 @@ +/** + * @file pwr_mon.c + * @brief + * + * DAPLink Interface Firmware + * Copyright 2021 Micro:bit Educational Foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "pwr_mon.h" + +void pwr_mon_init() +{ + // TODO +} + +power_source_t pwr_mon_get_power_source() +{ + // TODO + return PWR_SOURCE_NONE; +} + +uint32_t pwr_mon_get_vin_mv() +{ + // TODO + return 0; +} + +uint32_t pwr_mon_get_vbat_mv() +{ + // TODO + return 0; +} diff --git a/source/board/microbitv2/power.h b/source/board/microbitv2/power.h index e16035ecc..ca89834af 100644 --- a/source/board/microbitv2/power.h +++ b/source/board/microbitv2/power.h @@ -22,32 +22,21 @@ #ifndef POWER_H_ #define POWER_H_ -#include "fsl_common.h" -#include "fsl_smc.h" - -/* Power mode definition used in application. */ -typedef enum _app_power_mode +typedef enum _microbit_power_mode_t { - kAPP_PowerModeMin = 0, - kAPP_PowerModeRun, /* Normal RUN mode */ - kAPP_PowerModeWait, /* WAIT mode. */ - kAPP_PowerModeStop, /* STOP mode. */ - kAPP_PowerModeVlpr, /* VLPR mode. */ - kAPP_PowerModeVlpw, /* VLPW mode. */ - kAPP_PowerModeVlps, /* VLPS mode. */ - kAPP_PowerModeLls, /* LLS mode. */ - kAPP_PowerModeVlls0, /* VLLS0 mode. */ - kAPP_PowerModeVlls1, /* VLLS1 mode. */ - kAPP_PowerModeVlls3, /* VLLS3 mode. */ - kAPP_PowerModeMax -} app_power_mode_t; + MB_POWER_RUNNING = 0x01, + MB_POWER_SLEEP = 0x06, // VLPS + MB_POWER_DOWN = 0x08, // VLLS0 +} microbit_if_power_mode_t; void power_init(void); /* Lowest power mode available in KL27*/ -void power_enter_VLLS0(void); +//void power_enter_VLLS0(void); +void power_down(void); /* Lowest power mode that allows I2C operation with address match wakeup */ -void power_enter_VLPS(void); +//void power_enter_VLPS(void); +void power_sleep(void); #endif /* POWER_H_ */ diff --git a/source/board/microbitv2/flexio_pwm.h b/source/board/microbitv2/pwm.h similarity index 76% rename from source/board/microbitv2/flexio_pwm.h rename to source/board/microbitv2/pwm.h index d4cd36708..b53ef6b6c 100644 --- a/source/board/microbitv2/flexio_pwm.h +++ b/source/board/microbitv2/pwm.h @@ -1,5 +1,5 @@ /** - * @file flexio_pwm.h + * @file pwm.h * @brief * * DAPLink Interface Firmware @@ -19,8 +19,8 @@ * limitations under the License. */ -#ifndef FLEXIO_PWM_H_ -#define FLEXIO_PWM_H_ +#ifndef PWM_H_ +#define PWM_H_ #include "IO_Config.h" @@ -28,13 +28,13 @@ extern "C" { #endif -void flexio_pwm_init(void); -void flexio_pwm_init_pins(void); -void flexio_pwm_deinit_pins(void); -void flexio_pwm_set_dutycycle(uint8_t duty); +void pwm_init(void); +void pwm_init_pins(void); +void pwm_deinit_pins(void); +void pwm_set_dutycycle(uint8_t duty); #ifdef __cplusplus } #endif -#endif /* FLEXIO_PWM_H_ */ +#endif /* PWM_H_ */ From 580d45845fa002b6b79daf60449fd2b1fbddab72 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Mon, 11 Oct 2021 21:10:45 +0100 Subject: [PATCH 461/617] nrf52820_hic: Extract I2C code from i2c_commands. --- source/board/microbitv2/i2c.h | 54 +++ source/board/microbitv2/i2c_commands.c | 340 ++---------------- source/board/microbitv2/i2c_commands.h | 23 +- source/board/microbitv2/kl27z/i2c.c | 266 ++++++++++++++ source/board/microbitv2/kl27z/power.c | 2 +- source/board/microbitv2/kl27z/storage.c | 61 ++++ source/board/microbitv2/microbitv2.c | 7 +- source/board/microbitv2/nrf52820/i2c.c | 52 +++ .../microbitv2/nrf52820/i2c_commands_empty.c | 2 +- source/board/microbitv2/nrf52820/storage.c | 42 +++ source/board/microbitv2/storage.h | 40 +++ 11 files changed, 563 insertions(+), 326 deletions(-) create mode 100644 source/board/microbitv2/i2c.h create mode 100644 source/board/microbitv2/kl27z/i2c.c create mode 100644 source/board/microbitv2/kl27z/storage.c create mode 100644 source/board/microbitv2/nrf52820/i2c.c create mode 100644 source/board/microbitv2/nrf52820/storage.c create mode 100644 source/board/microbitv2/storage.h diff --git a/source/board/microbitv2/i2c.h b/source/board/microbitv2/i2c.h new file mode 100644 index 000000000..184ecd1df --- /dev/null +++ b/source/board/microbitv2/i2c.h @@ -0,0 +1,54 @@ +/** + * @file i2c.h + * @brief + * + * DAPLink Interface Firmware + * Copyright 2020 NXP + * Copyright 2021 Micro:bit Educational Foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef I2C_H_ +#define I2C_H_ + +#include + +/*! i2c Write Callback prototype */ +typedef void (*i2cWriteCallback_t) +( + uint8_t* pData, + uint8_t size +); + +/*! i2c Read Callback prototype */ +typedef void (*i2cReadCallback_t) +( + uint8_t* pData, + uint8_t size +); + +typedef enum { + I2C_STATUS_SUCCESS = 0, + I2C_STATUS_FAIL +} i2c_status_t; + +void i2c_initialize(void); +void i2c_deinitialize(void); +i2c_status_t i2c_registerWriteCallback(i2cWriteCallback_t writeCallback, uint8_t slaveAddress); +i2c_status_t i2c_registerReadCallback(i2cReadCallback_t readCallback, uint8_t slaveAddress); +void i2c_clearBuffer(void); +void i2c_fillBuffer(uint8_t* data, uint32_t position, uint32_t size); + +#endif /* I2C_H_ */ diff --git a/source/board/microbitv2/i2c_commands.c b/source/board/microbitv2/i2c_commands.c index 086ff55b3..b1a6cdb46 100644 --- a/source/board/microbitv2/i2c_commands.c +++ b/source/board/microbitv2/i2c_commands.c @@ -1,6 +1,6 @@ /** * @file i2c_commands.c - * @brief Microbit appliation layer for I2C operations + * @brief Microbit application layer for I2C operations * * DAPLink Interface Firmware * Copyright 2020 NXP @@ -22,44 +22,15 @@ #if defined(INTERFACE_KL27Z) #include "i2c_commands.h" -#include "fsl_i2c.h" -#include "fsl_clock.h" +#include "i2c.h" #include "fsl_port.h" -#include "fsl_flash.h" -#include "settings.h" // for config_get_overflow_detect #include "main_interface.h" #include "pwr_mon.h" #include "power.h" +#include "storage.h" #include "microbitv2.h" -/* I2C source clock */ -#define I2C_SLAVE_BASEADDR I2C1 -#define I2C_SLAVE_CLK_SRC I2C1_CLK_SRC -#define I2C_SLAVE_CLK_FREQ CLOCK_GetFreq(I2C1_CLK_SRC) - -#define I2C_SLAVE_LOWER_ADDR_7BIT (0x70U) -#define I2C_SLAVE_UPPER_ADDR_7BIT (0x72U) -#define I2C_DATA_LENGTH (1024U + 8U) - - -static uint8_t g_slave_TX_buff[I2C_DATA_LENGTH]; -static uint8_t g_slave_RX_buff[I2C_DATA_LENGTH]; -i2c_slave_handle_t g_s_handle; -static volatile bool g_SlaveCompletionFlag = false; -static volatile bool g_SlaveRxFlag = false; -static uint8_t address_match = 0; -static uint32_t transferredCount = 0; -static const uint8_t g_slave_busy_error_buff[] = {gErrorResponse_c, gErrorBusy_c}; -static uint8_t g_slave_TX_buff_ready = 0; -static uint8_t g_slave_busy = 0; - -static i2cWriteCallback_t pfWriteCommsCallback = NULL; -static i2cReadCallback_t pfReadCommsCallback = NULL; -static i2cWriteCallback_t pfWriteFlashCallback = NULL; -static i2cReadCallback_t pfReadFlashCallback = NULL; - -extern uint8_t i2c_wake_timeout; -extern bool i2c_allow_sleep; + extern uint16_t board_id_hex; extern power_source_t power_source; extern main_usb_connect_t usb_state; @@ -69,7 +40,6 @@ extern bool automatic_sleep_on; extern main_shutdown_state_t main_shutdown_state; extern bool do_remount; extern flashConfig_t gflashConfig; -extern flash_config_t g_flash; static void i2c_write_comms_callback(uint8_t* pData, uint8_t size); @@ -77,220 +47,6 @@ static void i2c_read_comms_callback(uint8_t* pData, uint8_t size); static void i2c_write_flash_callback(uint8_t* pData, uint8_t size); static void i2c_read_flash_callback(uint8_t* pData, uint8_t size); -static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData) { - i2cCommand_t i2cResponse = {0}; - - switch (xfer->event) - { - /* Address match event */ - case kI2C_SlaveAddressMatchEvent: - xfer->data = NULL; - xfer->dataSize = 0; - // fsl_i2c.c IRQ updated in fsl_i2c_mod.c to include I2C D register - address_match = *(uint8_t*)userData >> 1; - i2c_wake_timeout = 3; // 3 * 30ms tick = 90ms timeout - break; - /* Transmit request */ - case kI2C_SlaveTransmitEvent: - /* Update information for transmit process */ - // Send response if the buffer is ready, otherwise send busy error - if (g_slave_TX_buff_ready) { - xfer->data = g_slave_TX_buff; - xfer->dataSize = I2C_DATA_LENGTH; - } else { - xfer->data = (uint8_t*)g_slave_busy_error_buff; - xfer->dataSize = sizeof(g_slave_busy_error_buff); - g_slave_busy = 1; - } - g_SlaveRxFlag = false; - break; - - /* Receive request */ - case kI2C_SlaveReceiveEvent: - /* Update information for received process */ - // We don't need to clear g_slave_RX_buff because we also have the - // transferredCount to know what data is valid - xfer->data = g_slave_RX_buff; - xfer->dataSize = I2C_DATA_LENGTH; - - // Hack: Default driver can't differentiate between RX or TX on - // completion event, so we set a flag here. Can't process more - // than I2C_DATA_LENGTH bytes on RX - g_SlaveRxFlag = true; - - break; - - /* Transfer done */ - case kI2C_SlaveCompletionEvent: - g_SlaveCompletionFlag = true; - xfer->data = NULL; - xfer->dataSize = 0; - transferredCount = xfer->transferredCount; - - // Default driver couldn't differentiate between RX or TX completion - // Check flag set in kI2C_SlaveReceiveEvent - - // Ignore NOP cmd in I2C Write - if (!(g_SlaveRxFlag && g_slave_RX_buff[0] == 0x00)) { - // Only process events if the busy error was not read - if (!g_slave_busy) { - main_board_event(); - } else { - g_slave_busy = 0; - } - } - - // Buffer with response is not ready after an I2C Write inside the IRQ - // It will be ready when the task attends the I2C event - if(g_SlaveRxFlag) { - g_slave_TX_buff_ready = 0; - } - - i2c_allow_sleep = false; - break; - - default: - g_SlaveCompletionFlag = false; - break; - } -} -// Hook function executed in the main task -void board_custom_event() { - - if (g_SlaveRxFlag) { - i2c_clearBuffer(); - if (pfWriteCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { - pfWriteCommsCallback(&g_slave_RX_buff[0], transferredCount); - } - if (pfWriteFlashCallback && address_match == I2C_SLAVE_FLASH) { - pfWriteFlashCallback(&g_slave_RX_buff[0], transferredCount); - } - } else { - if (pfReadCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { - pfReadCommsCallback(&g_slave_TX_buff[0], transferredCount); - } - if (pfReadFlashCallback && address_match == I2C_SLAVE_FLASH) { - pfReadFlashCallback(&g_slave_TX_buff[0], transferredCount); - } - } - i2c_allow_sleep = true; -} - -static void i2c_init_pins(void) { - /* Port C Clock Gate Control: Clock enabled */ - CLOCK_EnableClock(kCLOCK_PortC); - - /* PORTC1 is configured as I2C1_SCL */ - PORT_SetPinMux(PORTC, 1U, kPORT_MuxAlt2); - - /* PORTC2 is configured as I2C1_SDA */ - PORT_SetPinMux(PORTC, 2U, kPORT_MuxAlt2); -} - -static int32_t i2c_start_transfer(void) { - memset(&g_s_handle, 0, sizeof(g_s_handle)); - - I2C_SlaveTransferCreateHandle(I2C_SLAVE_BASEADDR, &g_s_handle, - i2c_slave_callback, &address_match); - - /* Set up slave transfer. */ - I2C_SlaveTransferNonBlocking(I2C_SLAVE_BASEADDR, &g_s_handle, - kI2C_SlaveCompletionEvent | kI2C_SlaveAddressMatchEvent); - - // i2c handle will be busy until an address match - g_s_handle.isBusy = false; - - return 1; -} - -void i2c_initialize(void) { - i2c_slave_config_t slaveConfig; - - i2c_init_pins(); - - I2C_SlaveGetDefaultConfig(&slaveConfig); - - slaveConfig.addressingMode = kI2C_RangeMatch; - slaveConfig.slaveAddress = I2C_SLAVE_LOWER_ADDR_7BIT; - slaveConfig.upperAddress = I2C_SLAVE_UPPER_ADDR_7BIT; - slaveConfig.enableWakeUp = true; - - I2C_SlaveInit(I2C_SLAVE_BASEADDR, &slaveConfig, I2C_SLAVE_CLK_FREQ); - - NVIC_SetPriority(I2C1_IRQn, 0x00); /* set highest priority */ - - i2c_start_transfer(); - - i2c_registerWriteCallback(i2c_write_comms_callback, I2C_SLAVE_NRF_KL_COMMS); - i2c_registerReadCallback(i2c_read_comms_callback, I2C_SLAVE_NRF_KL_COMMS); - i2c_registerWriteCallback(i2c_write_flash_callback, I2C_SLAVE_FLASH); - i2c_registerReadCallback(i2c_read_flash_callback, I2C_SLAVE_FLASH); - - return; -} - -void i2c_deinitialize(void) { - I2C_SlaveDeinit(I2C_SLAVE_BASEADDR); - return ; -} - -status_t i2c_registerWriteCallback(i2cWriteCallback_t writeCallback, uint8_t slaveAddress) -{ - status_t status = kStatus_Success; - - switch (slaveAddress){ - case I2C_SLAVE_NRF_KL_COMMS: - pfWriteCommsCallback = writeCallback; - break; - case I2C_SLAVE_HID: - break; - case I2C_SLAVE_FLASH: - pfWriteFlashCallback = writeCallback; - break; - default: - status = kStatus_Fail; - break; - } - - return status; -} - -status_t i2c_registerReadCallback(i2cReadCallback_t readCallback, uint8_t slaveAddress) -{ - status_t status = kStatus_Success; - - switch (slaveAddress) { - case I2C_SLAVE_NRF_KL_COMMS: - pfReadCommsCallback = readCallback; - break; - case I2C_SLAVE_HID: - break; - case I2C_SLAVE_FLASH: - pfReadFlashCallback = readCallback; - break; - default: - status = kStatus_Fail; - break; - } - - return status; -} - -void i2c_clearBuffer (void) { - memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); -} - -void i2c_fillBuffer (uint8_t* data, uint32_t position, uint32_t size) { - if ((position + size) > I2C_DATA_LENGTH) { - return; - } - - for (uint32_t i = 0; i < size; i++) { - g_slave_TX_buff[position + i] = data[i]; - } - g_slave_TX_buff_ready = 1; -} - static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { i2cCommand_t* pI2cCommand = (i2cCommand_t*) pData; i2cCommand_t i2cResponse = {0}; @@ -365,7 +121,7 @@ static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { interface_power_mode = MB_POWER_DOWN; i2cResponse.cmdId = gWriteResponse_c; i2cResponse.cmdData.writeRspCmd.propertyId = pI2cCommand->cmdData.writeReqCmd.propertyId; - } else { + } else { i2cResponse.cmdId = gErrorResponse_c; i2cResponse.cmdData.errorRspCmd.errorCode = gErrorWriteFail_c; } @@ -422,7 +178,7 @@ static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { i2cResponse.cmdData.errorRspCmd.errorCode = gErrorUnknownCommand_c; break; } - + if (assert_interrupt) { i2c_fillBuffer((uint8_t*) &i2cResponse, 0, sizeof(i2cResponse)); // Response ready, assert COMBINED_SENSOR_INT @@ -442,7 +198,7 @@ static void i2c_read_comms_callback(uint8_t* pData, uint8_t size) { } break; } - + // Release COMBINED_SENSOR_INT PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); } @@ -469,51 +225,25 @@ static bool file_extension_allowed(const vfs_filename_t filename) return false; } -static uint32_t erase_storage_sector(uint32_t adr) -{ - int status = FLASH_Erase(&g_flash, adr, g_flash.PFlashSectorSize, kFLASH_apiEraseKey); - if (status == kStatus_Success) - { - status = FLASH_VerifyErase(&g_flash, adr, g_flash.PFlashSectorSize, kFLASH_marginValueNormal); - } - return status; -} - -static uint32_t program_storage_page(uint32_t adr, uint32_t sz, uint8_t *buf) -{ - /* Verify data is word aligned */ - util_assert(!((uint32_t)buf & 0x3)); - - int status = FLASH_Program(&g_flash, adr, (uint32_t *) buf, sz); - if (status == kStatus_Success) - { - // Must use kFlashMargin_User, or kFlashMargin_Factory for verify program - status = FLASH_VerifyProgram(&g_flash, adr, sz, - (uint32_t *) buf, kFLASH_marginValueUser, - NULL, NULL); - } - return status; -} - static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { i2cFlashCmd_t* pI2cCommand = (i2cFlashCmd_t*) pData; - + uint32_t status = 0; - + uint32_t storage_address = pI2cCommand->cmdData.write.addr2 << 16 | pI2cCommand->cmdData.write.addr1 << 8 | pI2cCommand->cmdData.write.addr0 << 0; uint32_t address = storage_address + FLASH_STORAGE_ADDRESS; uint32_t length = __REV(pI2cCommand->cmdData.write.length); uint32_t data = (uint32_t) pI2cCommand->cmdData.write.data; - + switch (pI2cCommand->cmdId) { case gFlashDataWrite_c: /* Validate length field matches with I2C Write data */ - if (size == length + 8) { - /* Address range and alignment validation done inside program_storage_page() */ - status = program_storage_page(address, length, (uint8_t *) data); - + if (size == length + 8) { + /* Address range and alignment validation done inside storage_program_page() */ + status = storage_program_page(address, length, (uint8_t *) data); + if (0 != status) { pI2cCommand->cmdId = gFlashError_c; i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); @@ -534,7 +264,7 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { if (address + length > (FLASH_CONFIG_ADDRESS + FLASH_INTERFACE_SIZE)) { pI2cCommand->cmdId = gFlashError_c; i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - } else { + } else { /* Fill TX Buffer with received command args */ i2c_fillBuffer((uint8_t*) pI2cCommand, 0, sizeof(i2cFlashCmd_t) - 1024); /* Fill TX Buffer with Flash Data Read */ @@ -547,12 +277,12 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { pI2cCommand->cmdData.erase.sAddr1 << 8 | pI2cCommand->cmdData.erase.sAddr0 << 0; uint32_t start_addr = address + FLASH_STORAGE_ADDRESS; - + address = pI2cCommand->cmdData.erase.eAddr2 << 16 | pI2cCommand->cmdData.erase.eAddr1 << 8 | pI2cCommand->cmdData.erase.eAddr0 << 0; uint32_t end_addr = address + FLASH_STORAGE_ADDRESS; - + /* Do address range validation */ if (start_addr % DAPLINK_SECTOR_SIZE == 0 && end_addr % DAPLINK_SECTOR_SIZE == 0 && @@ -560,9 +290,9 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { start_addr < (FLASH_CONFIG_ADDRESS + FLASH_INTERFACE_SIZE) && end_addr < (FLASH_CONFIG_ADDRESS + FLASH_INTERFACE_SIZE)) { for (uint32_t addr = start_addr; addr <= end_addr && status == 0; addr += DAPLINK_SECTOR_SIZE) { - status = erase_storage_sector(addr); + status = storage_erase_sector(addr); } - + if (status != 0) { pI2cCommand->cmdId = gFlashError_c; } @@ -573,7 +303,7 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { } break; - case gFlashCfgFileName_c: + case gFlashCfgFileName_c: if (size == 1) { /* If size is 1 (only cmd id), this means it's a read */ i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); @@ -587,14 +317,14 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { memcpy(gflashConfig.fileName, pI2cCommand->cmdData.data, 11); } // If disallowed extension is requested, .bin will be used - else { + else { memcpy(gflashConfig.fileName, pI2cCommand->cmdData.data, 8); memcpy(&gflashConfig.fileName[8], "BIN", 3); } i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); i2c_fillBuffer((uint8_t*) &gflashConfig.fileName, 1, sizeof(gflashConfig.fileName)); } - else { + else { // Send error if invalid filename pI2cCommand->cmdId = gFlashError_c; i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); @@ -604,7 +334,7 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); } break; - case gFlashCfgFileSize_c: + case gFlashCfgFileSize_c: if (size == 1) { /* If size is 1 (only cmd id), this means it's a read */ uint32_t tempFileSize = __REV(gflashConfig.fileSize); @@ -616,7 +346,7 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { pI2cCommand->cmdData.data[1] << 16 | pI2cCommand->cmdData.data[2] << 8 | pI2cCommand->cmdData.data[3] << 0; - + /* Validate file size */ if (tempFileSize <= (FLASH_INTERFACE_SIZE - FLASH_CONFIG_SIZE)) { gflashConfig.fileSize = tempFileSize; @@ -650,14 +380,14 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { pI2cCommand->cmdData.data[5] << 16 | pI2cCommand->cmdData.data[6] << 8 | pI2cCommand->cmdData.data[7] << 0; - + /* Validate encoding window */ if (tempFileEncWindowStart <= tempFileEncWindowEnd) { gflashConfig.fileEncWindowStart = tempFileEncWindowStart; tempFileEncWindowStart = __REV(gflashConfig.fileEncWindowStart); gflashConfig.fileEncWindowEnd = tempFileEncWindowEnd; tempFileEncWindowEnd = __REV(gflashConfig.fileEncWindowEnd); - + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); i2c_fillBuffer((uint8_t*) &tempFileEncWindowStart, 1, sizeof(gflashConfig.fileEncWindowStart)); i2c_fillBuffer((uint8_t*) &tempFileEncWindowEnd, 5, sizeof(gflashConfig.fileEncWindowEnd)); @@ -689,21 +419,21 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { // Check first is config is already present in flash // If differences are found, erase and write new config if (0 != memcmp(&gflashConfig, (void *)FLASH_CONFIG_ADDRESS, sizeof(flashConfig_t))) { - status = erase_storage_sector(FLASH_CONFIG_ADDRESS); + status = storage_erase_sector(FLASH_CONFIG_ADDRESS); if (status != 0) { pI2cCommand->cmdId = gFlashError_c; } else { - status = program_storage_page(FLASH_CONFIG_ADDRESS, sizeof(flashConfig_t), (uint8_t *) &gflashConfig); + status = storage_program_page(FLASH_CONFIG_ADDRESS, sizeof(flashConfig_t), (uint8_t *) &gflashConfig); } } i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); break; case gFlashCfgErase_c: // Erase flash sector containing flash config - status = erase_storage_sector(FLASH_CONFIG_ADDRESS); - + status = storage_erase_sector(FLASH_CONFIG_ADDRESS); + if (status != 0) { pI2cCommand->cmdId = gFlashError_c; } @@ -736,7 +466,7 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); break; } - + // Response ready, assert COMBINED_SENSOR_INT PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_MuxAsGpio); } @@ -746,4 +476,12 @@ static void i2c_read_flash_callback(uint8_t* pData, uint8_t size) { PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); } +void i2c_cmds_init() { + i2c_initialize(); + i2c_registerWriteCallback(i2c_write_comms_callback, I2C_SLAVE_NRF_KL_COMMS); + i2c_registerReadCallback(i2c_read_comms_callback, I2C_SLAVE_NRF_KL_COMMS); + i2c_registerWriteCallback(i2c_write_flash_callback, I2C_SLAVE_FLASH); + i2c_registerReadCallback(i2c_read_flash_callback, I2C_SLAVE_FLASH); +} + #endif diff --git a/source/board/microbitv2/i2c_commands.h b/source/board/microbitv2/i2c_commands.h index 816ef1bfd..05f2f07c4 100644 --- a/source/board/microbitv2/i2c_commands.h +++ b/source/board/microbitv2/i2c_commands.h @@ -22,6 +22,7 @@ #ifndef I2C_COMMANDS_H #define I2C_COMMANDS_H +#include #include #include "cmsis_compiler.h" @@ -33,6 +34,7 @@ typedef int32_t status_t; extern "C" { #endif +/* 7-bit addresses */ #define I2C_SLAVE_NRF_KL_COMMS (0x70U) #define I2C_SLAVE_HID (0x71U) #define I2C_SLAVE_FLASH (0x72U) @@ -175,26 +177,7 @@ typedef __PACKED_STRUCT i2cFlashCmd_tag { } cmdData; } i2cFlashCmd_t; -/*! i2c Write Callback prototype */ -typedef void (*i2cWriteCallback_t) -( - uint8_t* pData, - uint8_t size -); - -/*! i2c Read Callback prototype */ -typedef void (*i2cReadCallback_t) -( - uint8_t* pData, - uint8_t size -); - -void i2c_initialize(void); -void i2c_deinitialize(void); -status_t i2c_registerWriteCallback(i2cWriteCallback_t writeCallback, uint8_t slaveAddress); -status_t i2c_registerReadCallback(i2cReadCallback_t readCallback, uint8_t slaveAddress); -void i2c_clearBuffer(void); -void i2c_fillBuffer(uint8_t* data, uint32_t position, uint32_t size); +void i2c_cmds_init(void); #ifdef __cplusplus } diff --git a/source/board/microbitv2/kl27z/i2c.c b/source/board/microbitv2/kl27z/i2c.c new file mode 100644 index 000000000..2f0c44977 --- /dev/null +++ b/source/board/microbitv2/kl27z/i2c.c @@ -0,0 +1,266 @@ +/** + * @file i2c.c + * @brief + * + * DAPLink Interface Firmware + * Copyright 2020 NXP + * Copyright 2021 Micro:bit Educational foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "i2c.h" +#include "i2c_commands.h" + +#include "main_interface.h" + +#include "fsl_i2c.h" +#include "fsl_clock.h" +#include "fsl_port.h" + +/* I2C source clock */ +#define I2C_SLAVE_BASEADDR I2C1 +#define I2C_SLAVE_CLK_SRC I2C1_CLK_SRC +#define I2C_SLAVE_CLK_FREQ CLOCK_GetFreq(I2C1_CLK_SRC) + +#define I2C_SLAVE_LOWER_ADDR_7BIT (0x70U) +#define I2C_SLAVE_UPPER_ADDR_7BIT (0x72U) +#define I2C_DATA_LENGTH (1024U + 8U) +static uint8_t g_slave_TX_buff[I2C_DATA_LENGTH]; +static uint8_t g_slave_RX_buff[I2C_DATA_LENGTH]; + +i2c_slave_handle_t g_s_handle; +static volatile bool g_SlaveCompletionFlag = false; +static volatile bool g_SlaveRxFlag = false; +static uint8_t address_match = 0; +static uint32_t transferredCount = 0; +static const uint8_t g_slave_busy_error_buff[] = {gErrorResponse_c, gErrorBusy_c}; +static uint8_t g_slave_TX_buff_ready = 0; +static uint8_t g_slave_busy = 0; + +static i2cWriteCallback_t pfWriteCommsCallback = NULL; +static i2cReadCallback_t pfReadCommsCallback = NULL; +static i2cWriteCallback_t pfWriteFlashCallback = NULL; +static i2cReadCallback_t pfReadFlashCallback = NULL; + +extern uint8_t i2c_wake_timeout; +extern bool i2c_allow_sleep; + +static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData) { + i2cCommand_t i2cResponse = {0}; + + switch (xfer->event) + { + /* Address match event */ + case kI2C_SlaveAddressMatchEvent: + xfer->data = NULL; + xfer->dataSize = 0; + // fsl_i2c.c IRQ updated in fsl_i2c_mod.c to include I2C D register + address_match = *(uint8_t*)userData >> 1; + i2c_wake_timeout = 3; // 3 * 30ms tick = 90ms timeout + break; + /* Transmit request */ + case kI2C_SlaveTransmitEvent: + /* Update information for transmit process */ + // Send response if the buffer is ready, otherwise send busy error + if (g_slave_TX_buff_ready) { + xfer->data = g_slave_TX_buff; + xfer->dataSize = I2C_DATA_LENGTH; + } else { + xfer->data = (uint8_t*)g_slave_busy_error_buff; + xfer->dataSize = sizeof(g_slave_busy_error_buff); + g_slave_busy = 1; + } + g_SlaveRxFlag = false; + break; + + /* Receive request */ + case kI2C_SlaveReceiveEvent: + /* Update information for received process */ + // We don't need to clear g_slave_RX_buff because we also have the + // transferredCount to know what data is valid + xfer->data = g_slave_RX_buff; + xfer->dataSize = I2C_DATA_LENGTH; + + // Hack: Default driver can't differentiate between RX or TX on + // completion event, so we set a flag here. Can't process more + // than I2C_DATA_LENGTH bytes on RX + g_SlaveRxFlag = true; + + break; + + /* Transfer done */ + case kI2C_SlaveCompletionEvent: + g_SlaveCompletionFlag = true; + xfer->data = NULL; + xfer->dataSize = 0; + transferredCount = xfer->transferredCount; + + // Default driver couldn't differentiate between RX or TX completion + // Check flag set in kI2C_SlaveReceiveEvent + + // Ignore NOP cmd in I2C Write + if (!(g_SlaveRxFlag && g_slave_RX_buff[0] == 0x00)) { + // Only process events if the busy error was not read + if (!g_slave_busy) { + main_board_event(); + } else { + g_slave_busy = 0; + } + } + + // Buffer with response is not ready after an I2C Write inside the IRQ + // It will be ready when the task attends the I2C event + if(g_SlaveRxFlag) { + g_slave_TX_buff_ready = 0; + } + + i2c_allow_sleep = false; + break; + + default: + g_SlaveCompletionFlag = false; + break; + } +} +// Hook function executed in the main task +void board_custom_event() { + if (g_SlaveRxFlag) { + i2c_clearBuffer(); + if (pfWriteCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { + pfWriteCommsCallback(&g_slave_RX_buff[0], transferredCount); + } + if (pfWriteFlashCallback && address_match == I2C_SLAVE_FLASH) { + pfWriteFlashCallback(&g_slave_RX_buff[0], transferredCount); + } + } else { + if (pfReadCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { + pfReadCommsCallback(&g_slave_TX_buff[0], transferredCount); + } + if (pfReadFlashCallback && address_match == I2C_SLAVE_FLASH) { + pfReadFlashCallback(&g_slave_TX_buff[0], transferredCount); + } + } + i2c_allow_sleep = true; +} + +static void i2c_init_pins(void) { + /* Port C Clock Gate Control: Clock enabled */ + CLOCK_EnableClock(kCLOCK_PortC); + + /* PORTC1 is configured as I2C1_SCL */ + PORT_SetPinMux(PORTC, 1U, kPORT_MuxAlt2); + + /* PORTC2 is configured as I2C1_SDA */ + PORT_SetPinMux(PORTC, 2U, kPORT_MuxAlt2); +} + +static int32_t i2c_start_transfer(void) { + memset(&g_s_handle, 0, sizeof(g_s_handle)); + + I2C_SlaveTransferCreateHandle(I2C_SLAVE_BASEADDR, &g_s_handle, + i2c_slave_callback, &address_match); + + /* Set up slave transfer. */ + I2C_SlaveTransferNonBlocking(I2C_SLAVE_BASEADDR, &g_s_handle, + kI2C_SlaveCompletionEvent | kI2C_SlaveAddressMatchEvent); + + // i2c handle will be busy until an address match + g_s_handle.isBusy = false; + + return 1; +} + +void i2c_initialize() { + i2c_slave_config_t slaveConfig; + + i2c_init_pins(); + + I2C_SlaveGetDefaultConfig(&slaveConfig); + + slaveConfig.addressingMode = kI2C_RangeMatch; + slaveConfig.slaveAddress = I2C_SLAVE_NRF_KL_COMMS; + slaveConfig.upperAddress = I2C_SLAVE_FLASH; + slaveConfig.enableWakeUp = true; + + I2C_SlaveInit(I2C_SLAVE_BASEADDR, &slaveConfig, I2C_SLAVE_CLK_FREQ); + + NVIC_SetPriority(I2C1_IRQn, 0x00); /* set highest priority */ + + i2c_start_transfer(); + + return; +} + +void i2c_deinitialize(void) { + I2C_SlaveDeinit(I2C_SLAVE_BASEADDR); + return ; +} + +i2c_status_t i2c_registerWriteCallback(i2cWriteCallback_t writeCallback, uint8_t slaveAddress) +{ + i2c_status_t status = I2C_STATUS_SUCCESS; + + switch (slaveAddress){ + case I2C_SLAVE_NRF_KL_COMMS: + pfWriteCommsCallback = writeCallback; + break; + case I2C_SLAVE_HID: + break; + case I2C_SLAVE_FLASH: + pfWriteFlashCallback = writeCallback; + break; + default: + status = I2C_STATUS_FAIL; + break; + } + + return status; +} + +i2c_status_t i2c_registerReadCallback(i2cReadCallback_t readCallback, uint8_t slaveAddress) +{ + i2c_status_t status = I2C_STATUS_SUCCESS; + + switch (slaveAddress) { + case I2C_SLAVE_NRF_KL_COMMS: + pfReadCommsCallback = readCallback; + break; + case I2C_SLAVE_HID: + break; + case I2C_SLAVE_FLASH: + pfReadFlashCallback = readCallback; + break; + default: + status = I2C_STATUS_FAIL; + break; + } + + return status; +} + +void i2c_clearBuffer (void) { + memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); +} + +void i2c_fillBuffer (uint8_t* data, uint32_t position, uint32_t size) { + if ((position + size) > I2C_DATA_LENGTH) { + return; + } + + for (uint32_t i = 0; i < size; i++) { + g_slave_TX_buff[position + i] = data[i]; + } + g_slave_TX_buff_ready = 1; +} diff --git a/source/board/microbitv2/kl27z/power.c b/source/board/microbitv2/kl27z/power.c index 73afa4786..5e33f88af 100644 --- a/source/board/microbitv2/kl27z/power.c +++ b/source/board/microbitv2/kl27z/power.c @@ -31,7 +31,7 @@ #include "pwr_mon.h" #include "IO_Config.h" #include "uart.h" -#include "i2c_commands.h" +#include "i2c.h" #include "rl_usb.h" /******************************************************************************* diff --git a/source/board/microbitv2/kl27z/storage.c b/source/board/microbitv2/kl27z/storage.c new file mode 100644 index 000000000..3411535ae --- /dev/null +++ b/source/board/microbitv2/kl27z/storage.c @@ -0,0 +1,61 @@ +/** + * @file storage.c + * @brief + * + * DAPLink Interface Firmware + * Copyright 2020 NXP + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "storage.h" + +#include "microbitv2.h" + +#include "fsl_flash.h" + +extern flash_config_t g_flash; + +uint32_t storage_program_page(uint32_t adr, uint32_t sz, uint8_t *buf) +{ + /* Verify data is word aligned */ + util_assert(!((uint32_t)buf & 0x3)); + + int status = FLASH_Program(&g_flash, adr, (uint32_t *) buf, sz); + if (status == kStatus_Success) + { + // Must use kFlashMargin_User, or kFlashMargin_Factory for verify program + status = FLASH_VerifyProgram(&g_flash, adr, sz, + (uint32_t *) buf, kFLASH_marginValueUser, + NULL, NULL); + } + return status; +} + +uint32_t storage_erase_sector(uint32_t adr) +{ + int status = FLASH_Erase(&g_flash, adr, g_flash.PFlashSectorSize, kFLASH_apiEraseKey); + if (status == kStatus_Success) + { + status = FLASH_VerifyErase(&g_flash, adr, g_flash.PFlashSectorSize, kFLASH_marginValueNormal); + } + return status; +} + +uint32_t storage_erase_all() +{ + int status = FLASH_Erase(&g_flash, FLASH_CONFIG_ADDRESS, g_flash.PFlashTotalSize / g_flash.PFlashBlockCount, kFLASH_apiEraseKey); + // TODO: Should we verify erase? + return status; +} diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 9b8fc9caa..11701af24 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -37,7 +37,9 @@ #include "power.h" #include "pwr_mon.h" #include "i2c_commands.h" +#include "i2c.h" #include "led_error_app.h" +#include "storage.h" #if defined(INTERFACE_KL27Z) @@ -95,7 +97,6 @@ flashConfig_t gflashConfig = { extern main_usb_connect_t usb_state; extern bool go_to_sleep; extern i2c_slave_handle_t g_s_handle; -extern flash_config_t g_flash; #endif extern void main_powerdown_event(void); @@ -238,7 +239,7 @@ static void prerun_board_config(void) uint8_t gamma_led_dc = get_led_gamma(power_led_max_duty_cycle); pwm_set_dutycycle(gamma_led_dc); - i2c_initialize(); + i2c_cmds_init(); #if defined(INTERFACE_NRF52820) } @@ -528,7 +529,7 @@ bool vfs_user_magic_file_hook(const vfs_filename_t filename, bool *do_remount) { if (!memcmp(filename, "ERASE ACT", sizeof(vfs_filename_t))) { // Erase last 128KB flash block - FLASH_Erase(&g_flash, FLASH_CONFIG_ADDRESS, g_flash.PFlashTotalSize / g_flash.PFlashBlockCount, kFLASH_apiEraseKey); + storage_erase_all(); } return false; diff --git a/source/board/microbitv2/nrf52820/i2c.c b/source/board/microbitv2/nrf52820/i2c.c new file mode 100644 index 000000000..a45a4e745 --- /dev/null +++ b/source/board/microbitv2/nrf52820/i2c.c @@ -0,0 +1,52 @@ +/** + * @file i2c.c + * @brief + * + * DAPLink Interface Firmware + * Copyright 2021 Micro:bit Educational Foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "i2c.h" + +void i2c_initialize() +{ + // TODO +} + +void i2c_deinitialize() +{ + // TODO +} + +i2c_status_t i2c_registerWriteCallback(i2cWriteCallback_t writeCallback, uint8_t slaveAddress) +{ + // TODO +} + +i2c_status_t i2c_registerReadCallback(i2cReadCallback_t readCallback, uint8_t slaveAddress) +{ + // TODO +} + +void i2c_clearBuffer() +{ + // TODO +} + +void i2c_fillBuffer(uint8_t* data, uint32_t position, uint32_t size) +{ + // TODO +} diff --git a/source/board/microbitv2/nrf52820/i2c_commands_empty.c b/source/board/microbitv2/nrf52820/i2c_commands_empty.c index 26b6e7f94..2c23d6411 100644 --- a/source/board/microbitv2/nrf52820/i2c_commands_empty.c +++ b/source/board/microbitv2/nrf52820/i2c_commands_empty.c @@ -21,7 +21,7 @@ #include "i2c_commands.h" -void i2c_initialize() +void i2c_cmds_init() { // TODO } diff --git a/source/board/microbitv2/nrf52820/storage.c b/source/board/microbitv2/nrf52820/storage.c new file mode 100644 index 000000000..f27c45a9d --- /dev/null +++ b/source/board/microbitv2/nrf52820/storage.c @@ -0,0 +1,42 @@ +/** + * @file storage.c + * @brief + * + * DAPLink Interface Firmware + * Copyright 2021 Micro:bit Educational Foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "storage.h" + +#include "microbitv2.h" + +uint32_t storage_program_page(uint32_t adr, uint32_t sz, uint8_t *buf) +{ + // TODO: Implement this + return 0; +} + +uint32_t storage_erase_sector(uint32_t adr) +{ + // TODO: Implement this + return 0; +} + +uint32_t storage_erase_all() +{ + // TODO: Implement this + return 0; +} diff --git a/source/board/microbitv2/storage.h b/source/board/microbitv2/storage.h new file mode 100644 index 000000000..ea2d21db5 --- /dev/null +++ b/source/board/microbitv2/storage.h @@ -0,0 +1,40 @@ +/** + * @file storage.h + * @brief + * + * DAPLink Interface Firmware + * Copyright 2020 NXP + * Copyright 2021 Micro:bit Educational foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef STORAGE_H_ +#define STORAGE_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t storage_program_page(uint32_t adr, uint32_t sz, uint8_t *buf); +uint32_t storage_erase_sector(uint32_t adr); +uint32_t storage_erase_all(void); + +#ifdef __cplusplus +} +#endif + +#endif /* STORAGE_H_ */ From 63fdc2ce7e0a3658d53476bd6b2d97d003b3b4d6 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Tue, 28 Sep 2021 19:07:42 +0100 Subject: [PATCH 462/617] nrf52820_hic: Extract platform-specific gpio code from microbitv2.c. --- source/board/microbitv2/gpio_extra.h | 42 +++++++++ source/board/microbitv2/i2c_commands.c | 9 +- .../microbitv2/kl27z/IO_Config_Override.h | 5 -- source/board/microbitv2/kl27z/gpio_extra.c | 62 ++++++++++++++ source/board/microbitv2/microbitv2.c | 21 ++--- source/board/microbitv2/nrf52820/gpio_extra.c | 85 +++++++++++++++++++ source/board/microbitv2/nrf52820/pwm.c | 9 +- 7 files changed, 209 insertions(+), 24 deletions(-) create mode 100644 source/board/microbitv2/gpio_extra.h create mode 100644 source/board/microbitv2/kl27z/gpio_extra.c create mode 100644 source/board/microbitv2/nrf52820/gpio_extra.c diff --git a/source/board/microbitv2/gpio_extra.h b/source/board/microbitv2/gpio_extra.h new file mode 100644 index 000000000..327c30fff --- /dev/null +++ b/source/board/microbitv2/gpio_extra.h @@ -0,0 +1,42 @@ +/** + * @file gpio_extra.h + * @brief + * + * DAPLink Interface Firmware + * Copyright 2021 Micro:bit Educational Foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef GPIO_EXTRA_H +#define GPIO_EXTRA_H + +#include "gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void gpio_enable_hid_led(void); +void gpio_disable_hid_led(void); + +void gpio_init_combined_int(void); +void gpio_disable_combined_int(void); +void gpio_assert_combined_int(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/source/board/microbitv2/i2c_commands.c b/source/board/microbitv2/i2c_commands.c index b1a6cdb46..4a0e97ba4 100644 --- a/source/board/microbitv2/i2c_commands.c +++ b/source/board/microbitv2/i2c_commands.c @@ -28,6 +28,7 @@ #include "pwr_mon.h" #include "power.h" #include "storage.h" +#include "gpio_extra.h" #include "microbitv2.h" @@ -182,7 +183,7 @@ static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { if (assert_interrupt) { i2c_fillBuffer((uint8_t*) &i2cResponse, 0, sizeof(i2cResponse)); // Response ready, assert COMBINED_SENSOR_INT - PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_MuxAsGpio); + gpio_assert_combined_int(); } } @@ -200,7 +201,7 @@ static void i2c_read_comms_callback(uint8_t* pData, uint8_t size) { } // Release COMBINED_SENSOR_INT - PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); + gpio_disable_combined_int(); } static bool file_extension_allowed(const vfs_filename_t filename) @@ -468,12 +469,12 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { } // Response ready, assert COMBINED_SENSOR_INT - PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_MuxAsGpio); + gpio_assert_combined_int(); } static void i2c_read_flash_callback(uint8_t* pData, uint8_t size) { // Release COMBINED_SENSOR_INT - PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); + gpio_disable_combined_int(); } void i2c_cmds_init() { diff --git a/source/board/microbitv2/kl27z/IO_Config_Override.h b/source/board/microbitv2/kl27z/IO_Config_Override.h index 2859c5eb1..519246bb8 100644 --- a/source/board/microbitv2/kl27z/IO_Config_Override.h +++ b/source/board/microbitv2/kl27z/IO_Config_Override.h @@ -137,11 +137,6 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_KL27Z); #define PIN_BOARD_REV_ID_ADC_CH (7) #define PIN_BOARD_REV_ID_ADC_MUX (1) -// COMBINED_SENSOR_INT PTA1 -#define COMBINED_SENSOR_INT_PORT PORTA -#define COMBINED_SENSOR_INT_GPIO GPIOA -#define COMBINED_SENSOR_INT_PIN (1) - // Connected LED Not available // Target Running LED Not available diff --git a/source/board/microbitv2/kl27z/gpio_extra.c b/source/board/microbitv2/kl27z/gpio_extra.c new file mode 100644 index 000000000..d1e47b659 --- /dev/null +++ b/source/board/microbitv2/kl27z/gpio_extra.c @@ -0,0 +1,62 @@ +/** + * @file gpio_extra.c + * @brief + * + * DAPLink Interface Firmware + * Copyright 2021 Micro:bit Educational Foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "gpio_extra.h" + +#include "fsl_port.h" +#include "fsl_gpio.h" + +// COMBINED_SENSOR_INT PTA1 +#define COMBINED_SENSOR_INT_PORT PORTA +#define COMBINED_SENSOR_INT_GPIO GPIOA +#define COMBINED_SENSOR_INT_PIN (1) + +void gpio_enable_hid_led() +{ + PIN_HID_LED_PORT->PCR[PIN_HID_LED_BIT] = PORT_PCR_MUX(1); +} + +void gpio_disable_hid_led() +{ + PIN_HID_LED_PORT->PCR[PIN_HID_LED_BIT] = PORT_PCR_MUX(0); +} + +void gpio_init_combined_int() +{ + gpio_pin_config_t pin_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 0U + }; + /* COMBINED_SENSOR_INT pin mux ALT0 (Disabled High-Z) */ + PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); + /* COMBINED_SENSOR_INT as output default low when pin mux ALT1 */ + GPIO_PinInit(COMBINED_SENSOR_INT_GPIO, COMBINED_SENSOR_INT_PIN, &pin_config); +} + +void gpio_disable_combined_int() +{ + PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); +} + +void gpio_assert_combined_int() +{ + PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_MuxAsGpio); +} diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 11701af24..66b3fd00d 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -40,6 +40,7 @@ #include "i2c.h" #include "led_error_app.h" #include "storage.h" +#include "gpio_extra.h" #if defined(INTERFACE_KL27Z) @@ -245,15 +246,7 @@ static void prerun_board_config(void) } #elif defined(INTERFACE_KL27Z) - gpio_pin_config_t pin_config = { - .pinDirection = kGPIO_DigitalOutput, - .outputLogic = 0U - }; - - /* COMBINED_SENSOR_INT pin mux ALT0 (Disabled High-Z) */ - PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); - /* COMBINED_SENSOR_INT as output default low when pin mux ALT1 */ - GPIO_PinInit(COMBINED_SENSOR_INT_GPIO, COMBINED_SENSOR_INT_PIN, &pin_config); + gpio_init_combined_int(); // Load Config from Flash if present flashConfig_t * pflashConfigROM; @@ -329,12 +322,12 @@ void board_30ms_hook() if (usb_state == USB_CONNECTED) { // configure pin as GPIO - PIN_HID_LED_PORT->PCR[PIN_HID_LED_BIT] = PORT_PCR_MUX(1); + gpio_enable_hid_led(); power_led_max_duty_cycle = PWR_LED_ON_MAX_BRIGHTNESS; } else if (usb_state == USB_DISCONNECTED) { // Disable pin - PIN_HID_LED_PORT->PCR[PIN_HID_LED_BIT] = PORT_PCR_MUX(0); + gpio_disable_hid_led(); power_led_max_duty_cycle = PWR_LED_ON_BATT_BRIGHTNESS; } @@ -385,7 +378,7 @@ void board_30ms_hook() case MAIN_USER_EVENT: { // Release COMBINED_SENSOR_INT in case it was previously asserted - PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); + gpio_disable_combined_int(); // Prepare I2C response i2cCommand_t i2cResponse = {0}; @@ -404,7 +397,7 @@ void board_30ms_hook() i2c_fillBuffer((uint8_t*) &i2cResponse, 0, sizeof(i2cResponse)); // Response ready, assert COMBINED_SENSOR_INT - PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_MuxAsGpio); + gpio_assert_combined_int(); // Return LED to ON after release of long press main_shutdown_state = MAIN_SHUTDOWN_WAITING; @@ -522,7 +515,7 @@ void board_vfs_stream_closed_hook() i2c_clearBuffer(); // Release COMBINED_SENSOR_INT - PORT_SetPinMux(COMBINED_SENSOR_INT_PORT, COMBINED_SENSOR_INT_PIN, kPORT_PinDisabledOrAnalog); + gpio_disable_combined_int(); } bool vfs_user_magic_file_hook(const vfs_filename_t filename, bool *do_remount) diff --git a/source/board/microbitv2/nrf52820/gpio_extra.c b/source/board/microbitv2/nrf52820/gpio_extra.c new file mode 100644 index 000000000..5234342da --- /dev/null +++ b/source/board/microbitv2/nrf52820/gpio_extra.c @@ -0,0 +1,85 @@ +/** + * @file gpio_extra.c + * @brief + * + * DAPLink Interface Firmware + * Copyright 2021 Micro:bit Educational Foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "gpio_extra.h" +#include "compiler.h" +#include "dl_nrf_gpio.h" + +#define NRF52833_COMBINED_SENSOR_INT_PIN NRF_GPIO_PIN_MAP(0, 9) +#define NRF52820_COMBINED_SENSOR_INT_PIN NRF_GPIO_PIN_MAP(0, 16) + +#ifdef NRF528XX_DYNAMIC_PIN +static uint32_t COMBINED_SENSOR_INT_PIN; +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52833(NRF52833_COMBINED_SENSOR_INT_PIN)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_COMBINED_SENSOR_INT_PIN)); +#else +static const uint32_t COMBINED_SENSOR_INT_PIN = NRF52820_COMBINED_SENSOR_INT_PIN; +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_COMBINED_SENSOR_INT_PIN)); +#endif + +void gpio_enable_hid_led() +{ + gpio_cfg_output(GPIO_REG(LED_HID), GPIO_IDX(LED_HID)); +} + +void gpio_disable_hid_led() +{ + gpio_cfg(GPIO_REG(LED_HID), + GPIO_IDX(LED_HID), + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); +} + +void gpio_init_combined_int() +{ +#ifdef NRF528XX_DYNAMIC_PIN + if (NRF_FICR->INFO.PART == 0x52833) { + // nRF52833 + COMBINED_SENSOR_INT_PIN = NRF52833_COMBINED_SENSOR_INT_PIN; + } else { + // nRF52820 + COMBINED_SENSOR_INT_PIN = NRF52820_COMBINED_SENSOR_INT_PIN; + } +#endif + gpio_disable_combined_int(); +} + +void gpio_disable_combined_int() +{ + gpio_cfg(GPIO_REG(COMBINED_SENSOR_INT_PIN), + GPIO_IDX(COMBINED_SENSOR_INT_PIN), + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); +} + +void gpio_assert_combined_int() +{ + gpio_cfg_output(GPIO_REG(COMBINED_SENSOR_INT_PIN), + GPIO_IDX(COMBINED_SENSOR_INT_PIN)); + gpio_clear(GPIO_REG(COMBINED_SENSOR_INT_PIN), + GPIO_IDX(COMBINED_SENSOR_INT_PIN)); +} diff --git a/source/board/microbitv2/nrf52820/pwm.c b/source/board/microbitv2/nrf52820/pwm.c index 6efe01c3d..169d2c2fc 100644 --- a/source/board/microbitv2/nrf52820/pwm.c +++ b/source/board/microbitv2/nrf52820/pwm.c @@ -20,6 +20,7 @@ */ #include "pwm.h" +#include "gpio.h" void pwm_init() { @@ -38,5 +39,11 @@ void pwm_deinit_pins() void pwm_set_dutycycle(uint8_t duty) { - // TODO + // This is just a hack to turn off the LED when the duty cycle is low enough + // TODO: Actually implement this + if (duty < 10) { + gpio_clear(GPIO_REG(LED_PWR), GPIO_IDX(LED_PWR)); + } else { + gpio_set(GPIO_REG(LED_PWR), GPIO_IDX(LED_PWR)); + } } From 2dfb2b5a4ad407ce44560588d230f59bf3b74a88 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Fri, 8 Oct 2021 18:37:53 +0100 Subject: [PATCH 463/617] nrf52820_hic: Enable all features in microbitv2.c. A lot of the nRF code in the platform specific files is not implemented yet, but all the platform specific features should have been abstracted at this point. --- source/board/microbitv2/i2c.h | 2 ++ source/board/microbitv2/kl27z/IO_Config_Override.h | 7 ------- source/board/microbitv2/kl27z/i2c.c | 5 +++++ source/board/microbitv2/microbitv2.c | 13 +------------ source/board/microbitv2/microbitv2.h | 6 ++++++ source/board/microbitv2/nrf52820/i2c.c | 6 ++++++ 6 files changed, 20 insertions(+), 19 deletions(-) diff --git a/source/board/microbitv2/i2c.h b/source/board/microbitv2/i2c.h index 184ecd1df..9a15239a7 100644 --- a/source/board/microbitv2/i2c.h +++ b/source/board/microbitv2/i2c.h @@ -24,6 +24,7 @@ #define I2C_H_ #include +#include /*! i2c Write Callback prototype */ typedef void (*i2cWriteCallback_t) @@ -50,5 +51,6 @@ i2c_status_t i2c_registerWriteCallback(i2cWriteCallback_t writeCallback, uint8_t i2c_status_t i2c_registerReadCallback(i2cReadCallback_t readCallback, uint8_t slaveAddress); void i2c_clearBuffer(void); void i2c_fillBuffer(uint8_t* data, uint32_t position, uint32_t size); +bool i2c_isBusy(void); #endif /* I2C_H_ */ diff --git a/source/board/microbitv2/kl27z/IO_Config_Override.h b/source/board/microbitv2/kl27z/IO_Config_Override.h index 519246bb8..7e8599aaa 100644 --- a/source/board/microbitv2/kl27z/IO_Config_Override.h +++ b/source/board/microbitv2/kl27z/IO_Config_Override.h @@ -122,13 +122,6 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_KL27Z); #define PIN_RED_LED_BIT (7) #define PIN_RED_LED (1< Date: Mon, 11 Oct 2021 23:34:44 +0100 Subject: [PATCH 464/617] nrf52820_hic: Initial steps for I2C integration. Basic non-flash commands should be working, although not all functionality has been implemented yet, so some commands will return zeros. --- source/board/microbitv2/i2c.h | 3 + source/board/microbitv2/i2c_commands.c | 5 +- source/board/microbitv2/kl27z/i2c.c | 3 - source/board/microbitv2/nrf52820/i2c.c | 128 +++++++++++++++++- .../microbitv2/nrf52820/i2c_commands_empty.c | 27 ---- .../nordic/nrf52820/I2C_Slave_nRF52820.c | 8 +- 6 files changed, 131 insertions(+), 43 deletions(-) delete mode 100644 source/board/microbitv2/nrf52820/i2c_commands_empty.c diff --git a/source/board/microbitv2/i2c.h b/source/board/microbitv2/i2c.h index 9a15239a7..50251e94d 100644 --- a/source/board/microbitv2/i2c.h +++ b/source/board/microbitv2/i2c.h @@ -45,6 +45,9 @@ typedef enum { I2C_STATUS_FAIL } i2c_status_t; +/* TX and RX buffer size */ +#define I2C_DATA_LENGTH (1024U + 8U) + void i2c_initialize(void); void i2c_deinitialize(void); i2c_status_t i2c_registerWriteCallback(i2cWriteCallback_t writeCallback, uint8_t slaveAddress); diff --git a/source/board/microbitv2/i2c_commands.c b/source/board/microbitv2/i2c_commands.c index 4a0e97ba4..913c5cf83 100644 --- a/source/board/microbitv2/i2c_commands.c +++ b/source/board/microbitv2/i2c_commands.c @@ -19,11 +19,10 @@ * limitations under the License. */ -#if defined(INTERFACE_KL27Z) +#include #include "i2c_commands.h" #include "i2c.h" -#include "fsl_port.h" #include "main_interface.h" #include "pwr_mon.h" #include "power.h" @@ -484,5 +483,3 @@ void i2c_cmds_init() { i2c_registerWriteCallback(i2c_write_flash_callback, I2C_SLAVE_FLASH); i2c_registerReadCallback(i2c_read_flash_callback, I2C_SLAVE_FLASH); } - -#endif diff --git a/source/board/microbitv2/kl27z/i2c.c b/source/board/microbitv2/kl27z/i2c.c index 4368a3c9f..a11c0f357 100644 --- a/source/board/microbitv2/kl27z/i2c.c +++ b/source/board/microbitv2/kl27z/i2c.c @@ -34,9 +34,6 @@ #define I2C_SLAVE_CLK_SRC I2C1_CLK_SRC #define I2C_SLAVE_CLK_FREQ CLOCK_GetFreq(I2C1_CLK_SRC) -#define I2C_SLAVE_LOWER_ADDR_7BIT (0x70U) -#define I2C_SLAVE_UPPER_ADDR_7BIT (0x72U) -#define I2C_DATA_LENGTH (1024U + 8U) static uint8_t g_slave_TX_buff[I2C_DATA_LENGTH]; static uint8_t g_slave_RX_buff[I2C_DATA_LENGTH]; diff --git a/source/board/microbitv2/nrf52820/i2c.c b/source/board/microbitv2/nrf52820/i2c.c index f69f8d23d..c443da2aa 100644 --- a/source/board/microbitv2/nrf52820/i2c.c +++ b/source/board/microbitv2/nrf52820/i2c.c @@ -19,11 +19,86 @@ * limitations under the License. */ +#include + #include "i2c.h" +#include "i2c_commands.h" + +#include "Driver_I2C.h" + +// Set to 1 to enable debugging +#define DEBUG_I2C 0 + +#if DEBUG_I2C +#include "daplink_debug.h" +#define debug_i2c_printf debug_msg +#define debug_i2c_data debug_data +#else +#define debug_i2c_printf(...) +#define debug_i2c_data(...) +#endif + +extern ARM_DRIVER_I2C Driver_I2C0; +static ARM_DRIVER_I2C *I2Cdrv = &Driver_I2C0; + +static uint8_t g_slave_TX_buff[I2C_DATA_LENGTH] = { 0 }; +static uint8_t g_slave_RX_buff[I2C_DATA_LENGTH] = { 0 }; + +static i2cWriteCallback_t pfWriteCommsCallback = NULL; +static i2cReadCallback_t pfReadCommsCallback = NULL; +static i2cWriteCallback_t pfWriteFlashCallback = NULL; +static i2cReadCallback_t pfReadFlashCallback = NULL; + +static void I2C_SignalEvent(uint32_t event) { + static uint32_t prev_event = 0; + + debug_i2c_printf("evt[%d] ", event); + + if ((event & ARM_I2C_EVENT_TRANSFER_INCOMPLETE) || /* Less data was transferred than requested */ + (event & ARM_I2C_EVENT_ADDRESS_NACK) || /* Slave address was not acknowledged */ + (event & ARM_I2C_EVENT_ARBITRATION_LOST) || /* Master lost bus arbitration */ + (event & ARM_I2C_EVENT_BUS_CLEAR)) { /* Bus clear operation completed */ + // TODO: Deal with errors + debug_i2c_printf("? %d", event); + } + + if (event & ARM_I2C_EVENT_TRANSFER_DONE) { + debug_i2c_data((uint8_t *)"d ", 1); + if (prev_event & ARM_I2C_EVENT_SLAVE_RECEIVE) { + debug_i2c_printf("[rx] %02x %02x ", g_slave_RX_buff[0], g_slave_RX_buff[1]); + pfWriteCommsCallback(&g_slave_RX_buff[0], I2Cdrv->GetDataCount()); + } else if (prev_event & ARM_I2C_EVENT_SLAVE_TRANSMIT) { + debug_i2c_data((uint8_t *)"[tx] ", 5); + for (int i = 0; i < 5; i++) debug_i2c_printf("%02x ", g_slave_TX_buff[i]); + pfReadCommsCallback(&g_slave_TX_buff[0], I2Cdrv->GetDataCount()); + } + } + if (event & ARM_I2C_EVENT_BUS_ERROR) { + /* Invalid start/stop position detected */ + debug_i2c_data((uint8_t *)"E", 1); + } + if (event & ARM_I2C_EVENT_GENERAL_CALL) { + /* Slave was addressed with a general call address */ + debug_i2c_data((uint8_t *)"g", 1); + } + if (event & ARM_I2C_EVENT_SLAVE_RECEIVE) { + int32_t ret = I2Cdrv->SlaveReceive(&g_slave_RX_buff[0], 2 /*I2C_DATA_LENGTH*/); + debug_i2c_printf("rx[%d] ", ret); + } + if (event & ARM_I2C_EVENT_SLAVE_TRANSMIT) { + int32_t ret = I2Cdrv->SlaveTransmit(g_slave_TX_buff, 10 /*I2C_DATA_LENGTH*/); + debug_i2c_printf("tx[%d] ", ret); + } + debug_i2c_data((uint8_t *)".\n", 2); + prev_event = event; +} void i2c_initialize() { - // TODO + i2c_clearBuffer(); + I2Cdrv->Initialize(I2C_SignalEvent); + I2Cdrv->PowerControl(ARM_POWER_FULL); + I2Cdrv->Control(ARM_I2C_OWN_ADDRESS, I2C_SLAVE_NRF_KL_COMMS); } void i2c_deinitialize() @@ -33,26 +108,65 @@ void i2c_deinitialize() i2c_status_t i2c_registerWriteCallback(i2cWriteCallback_t writeCallback, uint8_t slaveAddress) { - // TODO + i2c_status_t status = I2C_STATUS_SUCCESS; + + switch (slaveAddress){ + case I2C_SLAVE_NRF_KL_COMMS: + pfWriteCommsCallback = writeCallback; + break; + case I2C_SLAVE_HID: + break; + case I2C_SLAVE_FLASH: + pfWriteFlashCallback = writeCallback; + break; + default: + status = I2C_STATUS_FAIL; + break; + } + + return status; } i2c_status_t i2c_registerReadCallback(i2cReadCallback_t readCallback, uint8_t slaveAddress) { - // TODO + i2c_status_t status = I2C_STATUS_SUCCESS; + + switch (slaveAddress) { + case I2C_SLAVE_NRF_KL_COMMS: + pfReadCommsCallback = readCallback; + break; + case I2C_SLAVE_HID: + break; + case I2C_SLAVE_FLASH: + pfReadFlashCallback = readCallback; + break; + default: + status = I2C_STATUS_FAIL; + break; + } + + return status; } void i2c_clearBuffer() { - // TODO + // TODO: Clean all buffers? KL27 code only clear this one + memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); } void i2c_fillBuffer(uint8_t* data, uint32_t position, uint32_t size) { - // TODO + if ((position + size) > I2C_DATA_LENGTH) { + return; + } + // TODO: Taken from KL27 code, replace with memcpy? + for (uint32_t i = 0; i < size; i++) { + g_slave_TX_buff[position + i] = data[i]; + } } bool i2c_isBusy() { - // TODO - return false; + ARM_I2C_STATUS status = I2Cdrv->GetStatus(); + return status.busy; } diff --git a/source/board/microbitv2/nrf52820/i2c_commands_empty.c b/source/board/microbitv2/nrf52820/i2c_commands_empty.c deleted file mode 100644 index 2c23d6411..000000000 --- a/source/board/microbitv2/nrf52820/i2c_commands_empty.c +++ /dev/null @@ -1,27 +0,0 @@ -/** - * @file i2c_commands.c - * @brief - * - * DAPLink Interface Firmware - * Copyright 2021 Micro:bit Educational Foundation - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "i2c_commands.h" - -void i2c_cmds_init() -{ - // TODO -} diff --git a/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.c b/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.c index a84dcee7c..35164fb2f 100644 --- a/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.c +++ b/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.c @@ -86,12 +86,16 @@ static void twis_event_handler (nrfx_twis_evt_t const * p_event, I2C_RESOURCES * switch (p_event->type) { case NRFX_TWIS_EVT_READ_REQ: - if (nrfx_twis_is_waiting_tx_buff(&i2c->nrfx_twis)) { + // TODO: Check if this fix is correct + // if (nrfx_twis_is_waiting_tx_buff(&i2c->nrfx_twis)) { + if (p_event->data.buf_req) { event |= ARM_I2C_EVENT_SLAVE_TRANSMIT; } break; case NRFX_TWIS_EVT_WRITE_REQ: - if (nrfx_twis_is_waiting_rx_buff(&i2c->nrfx_twis)) { + // TODO: Check if this fix is correct + // if (nrfx_twis_is_waiting_rx_buff(&i2c->nrfx_twis)) { + if (p_event->data.buf_req) { event |= ARM_I2C_EVENT_SLAVE_RECEIVE; } break; From 2f3482e1018996a2adaaca5639d06a8613bbed21 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Wed, 13 Oct 2021 15:32:05 +0100 Subject: [PATCH 465/617] nrf52820_hic: Add docstrings to power.h & pwr_mon.h. --- source/board/microbitv2/i2c_commands.h | 2 -- source/board/microbitv2/power.h | 23 +++++++++++++++++------ source/board/microbitv2/pwr_mon.h | 16 ++++++++++++++++ 3 files changed, 33 insertions(+), 8 deletions(-) diff --git a/source/board/microbitv2/i2c_commands.h b/source/board/microbitv2/i2c_commands.h index 05f2f07c4..94dab07b9 100644 --- a/source/board/microbitv2/i2c_commands.h +++ b/source/board/microbitv2/i2c_commands.h @@ -27,8 +27,6 @@ #include "cmsis_compiler.h" #include "virtual_fs.h" -// #include "fsl_common.h" -typedef int32_t status_t; #ifdef __cplusplus extern "C" { diff --git a/source/board/microbitv2/power.h b/source/board/microbitv2/power.h index ca89834af..67e68533d 100644 --- a/source/board/microbitv2/power.h +++ b/source/board/microbitv2/power.h @@ -25,18 +25,29 @@ typedef enum _microbit_power_mode_t { MB_POWER_RUNNING = 0x01, - MB_POWER_SLEEP = 0x06, // VLPS - MB_POWER_DOWN = 0x08, // VLLS0 + MB_POWER_SLEEP = 0x06, // KL27 VLPS + MB_POWER_DOWN = 0x08, // KL27 VLLS0 } microbit_if_power_mode_t; +/** + * Initialises the required resources to switch between different power modes. + */ void power_init(void); -/* Lowest power mode available in KL27*/ -//void power_enter_VLLS0(void); +/** + * Lowest power mode available in the Interface MCU. + * Wakes up via reset button press or falling edge of VBUS_ABSENT (previously + * named WAKE_ON_EDGE). + * + */ void power_down(void); -/* Lowest power mode that allows I2C operation with address match wakeup */ -//void power_enter_VLPS(void); +/** + * Lowest power mode that wakes up on I2C operation with address match wakeup. + * Also wakes up via reset button, VBUS_ABSENT (previously named WAKE_ON_EDGE). + * Does not wake up on UART traffic. + * Resumes operation on wake up. + */ void power_sleep(void); #endif /* POWER_H_ */ diff --git a/source/board/microbitv2/pwr_mon.h b/source/board/microbitv2/pwr_mon.h index 7ed5f7efe..3f15b9af8 100644 --- a/source/board/microbitv2/pwr_mon.h +++ b/source/board/microbitv2/pwr_mon.h @@ -36,8 +36,24 @@ typedef enum { } power_source_t; void pwr_mon_init(void); + +/** + * Based on the volatages in VBAT_SENSE and the MCU Vin it determines what + * power sources are active. + * @return Active power source via power_source_t enum. + */ power_source_t pwr_mon_get_power_source(void); + +/** + * Measures the Vin voltage. + * @return Interface MCU Vin voltage in millivolts. + */ uint32_t pwr_mon_get_vin_mv(void); + +/** + * Measures the VBAT_SENSE voltage. + * @return VBAT_SENSE voltage in millivolts. + */ uint32_t pwr_mon_get_vbat_mv(void); From 3617bc74ef0b220a147a17daf0ab1a9937a2ba23 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Mon, 18 Oct 2021 00:14:13 +0100 Subject: [PATCH 466/617] nrf52820_hic: Add matched I2C address to each event. --- source/board/microbitv2/nrf52820/i2c.c | 18 ++++++++++++++---- source/hic_hal/nordic/nrf52820/Driver_I2C.h | 8 +++++++- .../nordic/nrf52820/I2C_Slave_nRF52820.c | 6 ++++++ 3 files changed, 27 insertions(+), 5 deletions(-) diff --git a/source/board/microbitv2/nrf52820/i2c.c b/source/board/microbitv2/nrf52820/i2c.c index c443da2aa..0aabd65f0 100644 --- a/source/board/microbitv2/nrf52820/i2c.c +++ b/source/board/microbitv2/nrf52820/i2c.c @@ -63,14 +63,24 @@ static void I2C_SignalEvent(uint32_t event) { } if (event & ARM_I2C_EVENT_TRANSFER_DONE) { - debug_i2c_data((uint8_t *)"d ", 1); + debug_i2c_data((uint8_t *)"d ", 1); if (prev_event & ARM_I2C_EVENT_SLAVE_RECEIVE) { debug_i2c_printf("[rx] %02x %02x ", g_slave_RX_buff[0], g_slave_RX_buff[1]); - pfWriteCommsCallback(&g_slave_RX_buff[0], I2Cdrv->GetDataCount()); + + if (event & EXTENSION_I2C_EVENT_SLAVE_ADDR_0) { + pfWriteCommsCallback(&g_slave_RX_buff[0], I2Cdrv->GetDataCount()); + } else if (event & EXTENSION_I2C_EVENT_SLAVE_ADDR_1) { + pfWriteFlashCallback(&g_slave_RX_buff[0], I2Cdrv->GetDataCount()); + } } else if (prev_event & ARM_I2C_EVENT_SLAVE_TRANSMIT) { debug_i2c_data((uint8_t *)"[tx] ", 5); for (int i = 0; i < 5; i++) debug_i2c_printf("%02x ", g_slave_TX_buff[i]); - pfReadCommsCallback(&g_slave_TX_buff[0], I2Cdrv->GetDataCount()); + + if (event & EXTENSION_I2C_EVENT_SLAVE_ADDR_0) { + pfReadCommsCallback(&g_slave_TX_buff[0], I2Cdrv->GetDataCount()); + } else if (event & EXTENSION_I2C_EVENT_SLAVE_ADDR_1) { + pfReadFlashCallback(&g_slave_TX_buff[0], I2Cdrv->GetDataCount()); + } } } if (event & ARM_I2C_EVENT_BUS_ERROR) { @@ -96,9 +106,9 @@ static void I2C_SignalEvent(uint32_t event) { void i2c_initialize() { i2c_clearBuffer(); + // I2C addresses configured via default values from RTE_Device.h I2Cdrv->Initialize(I2C_SignalEvent); I2Cdrv->PowerControl(ARM_POWER_FULL); - I2Cdrv->Control(ARM_I2C_OWN_ADDRESS, I2C_SLAVE_NRF_KL_COMMS); } void i2c_deinitialize() diff --git a/source/hic_hal/nordic/nrf52820/Driver_I2C.h b/source/hic_hal/nordic/nrf52820/Driver_I2C.h index 8ed095a94..53e54f2d6 100644 --- a/source/hic_hal/nordic/nrf52820/Driver_I2C.h +++ b/source/hic_hal/nordic/nrf52820/Driver_I2C.h @@ -16,12 +16,14 @@ * limitations under the License. * * $Date: 31. March 2020 - * $Revision: V2.4 + * $Revision: V2.4.DAPLinkMod * * Project: I2C (Inter-Integrated Circuit) Driver definitions */ /* History: + * Version 2.4.DAPLinkMod + * Added extra I2C event flags to match slave address * Version 2.4 * Removed volatile from ARM_I2C_STATUS * Version 2.3 @@ -114,6 +116,10 @@ typedef struct _ARM_I2C_STATUS { #define ARM_I2C_EVENT_BUS_ERROR (1UL << 7) ///< Bus error detected (START/STOP at illegal position) #define ARM_I2C_EVENT_BUS_CLEAR (1UL << 8) ///< Bus clear finished +/* DAPLink modification: Extending the event flags to include slave address match */ +#define EXTENSION_I2C_EVENT_SLAVE_ADDR_1 (1UL << 14) ///< Transaction on slave address 1 match +#define EXTENSION_I2C_EVENT_SLAVE_ADDR_0 (1UL << 15) ///< Transaction on slave address 0 match + // Function documentation /** diff --git a/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.c b/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.c index 35164fb2f..4954684b5 100644 --- a/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.c +++ b/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.c @@ -124,6 +124,12 @@ static void twis_event_handler (nrfx_twis_evt_t const * p_event, I2C_RESOURCES * } if (i2c->info->cb_event != NULL) { + uint8_t address = nrf_twis_match_get(i2c->nrfx_twis.p_reg); + if (address == 0) { + event |= EXTENSION_I2C_EVENT_SLAVE_ADDR_0; + } else if (address == 1) { + event |= EXTENSION_I2C_EVENT_SLAVE_ADDR_1; + } i2c->info->cb_event (event); } } From 09705b78aab2a3ecdf0cca120a4417ece3909cf7 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Mon, 18 Oct 2021 01:27:33 +0100 Subject: [PATCH 467/617] nrf52820_hic: Refactor storage defines & add nRF implementation. --- records/board/microbitv2_nrf52820.yaml | 1 + source/board/microbitv2/i2c_commands.c | 30 +++++++++--------- source/board/microbitv2/kl27z/storage.c | 6 ++-- .../board/microbitv2/kl27z/storage_config.h | 29 +++++++++++++++++ source/board/microbitv2/microbitv2.c | 14 ++++----- source/board/microbitv2/microbitv2.h | 8 ----- source/board/microbitv2/nrf52820/storage.c | 31 ++++++++++++++++--- .../microbitv2/nrf52820/storage_config.h | 29 +++++++++++++++++ source/board/microbitv2/storage.h | 22 +++++++++++++ 9 files changed, 132 insertions(+), 38 deletions(-) create mode 100644 source/board/microbitv2/kl27z/storage_config.h create mode 100644 source/board/microbitv2/nrf52820/storage_config.h diff --git a/records/board/microbitv2_nrf52820.yaml b/records/board/microbitv2_nrf52820.yaml index ce8b3e31c..b8f318778 100644 --- a/records/board/microbitv2_nrf52820.yaml +++ b/records/board/microbitv2_nrf52820.yaml @@ -9,6 +9,7 @@ common: - BOARD_EXTRA_BUFFER=100 includes: - source/board/microbitv2/ + - source/board/microbitv2/nrf52820/ sources: board: - source/board/microbitv2/ diff --git a/source/board/microbitv2/i2c_commands.c b/source/board/microbitv2/i2c_commands.c index 913c5cf83..3ba7a86f1 100644 --- a/source/board/microbitv2/i2c_commands.c +++ b/source/board/microbitv2/i2c_commands.c @@ -233,7 +233,7 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { uint32_t storage_address = pI2cCommand->cmdData.write.addr2 << 16 | pI2cCommand->cmdData.write.addr1 << 8 | pI2cCommand->cmdData.write.addr0 << 0; - uint32_t address = storage_address + FLASH_STORAGE_ADDRESS; + uint32_t address = storage_address + STORAGE_ADDRESS_START; uint32_t length = __REV(pI2cCommand->cmdData.write.length); uint32_t data = (uint32_t) pI2cCommand->cmdData.write.data; @@ -261,7 +261,7 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { break; case gFlashDataRead_c: { /* Do address range validation */ - if (address + length > (FLASH_CONFIG_ADDRESS + FLASH_INTERFACE_SIZE)) { + if (address + length > STORAGE_ADDRESS_END) { pI2cCommand->cmdId = gFlashError_c; i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); } else { @@ -276,19 +276,19 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { uint32_t address = pI2cCommand->cmdData.erase.sAddr2 << 16 | pI2cCommand->cmdData.erase.sAddr1 << 8 | pI2cCommand->cmdData.erase.sAddr0 << 0; - uint32_t start_addr = address + FLASH_STORAGE_ADDRESS; + uint32_t start_addr = address + STORAGE_ADDRESS_START; address = pI2cCommand->cmdData.erase.eAddr2 << 16 | pI2cCommand->cmdData.erase.eAddr1 << 8 | pI2cCommand->cmdData.erase.eAddr0 << 0; - uint32_t end_addr = address + FLASH_STORAGE_ADDRESS; + uint32_t end_addr = address + STORAGE_ADDRESS_START; /* Do address range validation */ if (start_addr % DAPLINK_SECTOR_SIZE == 0 && end_addr % DAPLINK_SECTOR_SIZE == 0 && start_addr <= end_addr && - start_addr < (FLASH_CONFIG_ADDRESS + FLASH_INTERFACE_SIZE) && - end_addr < (FLASH_CONFIG_ADDRESS + FLASH_INTERFACE_SIZE)) { + start_addr < STORAGE_ADDRESS_END && + end_addr < STORAGE_ADDRESS_END) { for (uint32_t addr = start_addr; addr <= end_addr && status == 0; addr += DAPLINK_SECTOR_SIZE) { status = storage_erase_sector(addr); } @@ -348,7 +348,7 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { pI2cCommand->cmdData.data[3] << 0; /* Validate file size */ - if (tempFileSize <= (FLASH_INTERFACE_SIZE - FLASH_CONFIG_SIZE)) { + if (tempFileSize <= STORAGE_SIZE) { gflashConfig.fileSize = tempFileSize; tempFileSize = __REV(gflashConfig.fileSize); i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); @@ -418,21 +418,21 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { case gFlashCfgWrite_c: // Check first is config is already present in flash // If differences are found, erase and write new config - if (0 != memcmp(&gflashConfig, (void *)FLASH_CONFIG_ADDRESS, sizeof(flashConfig_t))) { - status = storage_erase_sector(FLASH_CONFIG_ADDRESS); + if (0 != memcmp(&gflashConfig, (void *)STORAGE_CONFIG_ADDRESS, sizeof(flashConfig_t))) { + status = storage_erase_sector(STORAGE_CONFIG_ADDRESS); if (status != 0) { pI2cCommand->cmdId = gFlashError_c; } else { - status = storage_program_page(FLASH_CONFIG_ADDRESS, sizeof(flashConfig_t), (uint8_t *) &gflashConfig); + status = storage_program_page(STORAGE_CONFIG_ADDRESS, sizeof(flashConfig_t), (uint8_t *) &gflashConfig); } } i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); break; case gFlashCfgErase_c: // Erase flash sector containing flash config - status = storage_erase_sector(FLASH_CONFIG_ADDRESS); + status = storage_erase_sector(STORAGE_CONFIG_ADDRESS); if (status != 0) { pI2cCommand->cmdId = gFlashError_c; @@ -440,16 +440,16 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { else { // Return flash config (RAM) to default values gflashConfig.key = CFG_KEY; - memcpy(gflashConfig.fileName, FLASH_CFG_FILENAME, 11); - gflashConfig.fileSize = FLASH_CFG_FILESIZE; - gflashConfig.fileVisible = FLASH_CFG_FILEVISIBLE; + memcpy(gflashConfig.fileName, STORAGE_CFG_FILENAME, 11); + gflashConfig.fileSize = STORAGE_CFG_FILESIZE; + gflashConfig.fileVisible = STORAGE_CFG_FILEVISIBLE; gflashConfig.fileEncWindowStart = 0; gflashConfig.fileEncWindowEnd = 0; } i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); break; case gFlashStorageSize_c: - pI2cCommand->cmdData.data[0] = (FLASH_INTERFACE_SIZE - FLASH_CONFIG_SIZE)/1024; + pI2cCommand->cmdData.data[0] = STORAGE_SECTOR_COUNT; i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 2); break; case gFlashSectorSize_c: diff --git a/source/board/microbitv2/kl27z/storage.c b/source/board/microbitv2/kl27z/storage.c index 3411535ae..8d7a6d01a 100644 --- a/source/board/microbitv2/kl27z/storage.c +++ b/source/board/microbitv2/kl27z/storage.c @@ -21,8 +21,6 @@ #include "storage.h" -#include "microbitv2.h" - #include "fsl_flash.h" extern flash_config_t g_flash; @@ -55,7 +53,7 @@ uint32_t storage_erase_sector(uint32_t adr) uint32_t storage_erase_all() { - int status = FLASH_Erase(&g_flash, FLASH_CONFIG_ADDRESS, g_flash.PFlashTotalSize / g_flash.PFlashBlockCount, kFLASH_apiEraseKey); - // TODO: Should we verify erase? + int status = FLASH_Erase(&g_flash, STORAGE_CONFIG_ADDRESS, g_flash.PFlashTotalSize / g_flash.PFlashBlockCount, kFLASH_apiEraseKey); + // TODO: Should we verify erase? Might be slow return status; } diff --git a/source/board/microbitv2/kl27z/storage_config.h b/source/board/microbitv2/kl27z/storage_config.h new file mode 100644 index 000000000..366bb9319 --- /dev/null +++ b/source/board/microbitv2/kl27z/storage_config.h @@ -0,0 +1,29 @@ +/** + * @file storage_config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright 2021 Micro:bit Educational foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef STORAGE_CONFIG_H_ +#define STORAGE_CONFIG_H_ + +#define STORAGE_FLASH_ADDRESS_START (0x00020000) +#define STORAGE_FLASH_ADDRESS_END (0x00040000) +#define STORAGE_SECTOR_SIZE (0x00000400) + +#endif /* STORAGE_CONFIG_H_ */ diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index b6eda8a8b..51fc4fb61 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -85,9 +85,9 @@ bool do_remount = false; flashConfig_t gflashConfig = { .key = CFG_KEY, - .fileName = FLASH_CFG_FILENAME, - .fileSize = FLASH_CFG_FILESIZE, - .fileVisible = FLASH_CFG_FILEVISIBLE, + .fileName = STORAGE_CFG_FILENAME, + .fileSize = STORAGE_CFG_FILESIZE, + .fileVisible = STORAGE_CFG_FILEVISIBLE, .fileEncWindowStart = 0, .fileEncWindowEnd = 0, }; @@ -241,7 +241,7 @@ static void prerun_board_config(void) // Load Config from Flash if present flashConfig_t * pflashConfigROM; - pflashConfigROM = (void *)FLASH_CONFIG_ADDRESS; + pflashConfigROM = (void *)STORAGE_CONFIG_ADDRESS; if (CFG_KEY == pflashConfigROM->key) { memcpy(&gflashConfig, pflashConfigROM, sizeof(flashConfig_t)); @@ -560,18 +560,18 @@ void vfs_user_build_filesystem_hook() { // File callback to be used with vfs_add_file to return file contents static uint32_t read_file_data_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors) { - uint32_t read_address = FLASH_STORAGE_ADDRESS + (VFS_SECTOR_SIZE * sector_offset); + uint32_t read_address = STORAGE_ADDRESS_START + (VFS_SECTOR_SIZE * sector_offset); uint32_t encoded_data_offset = (gflashConfig.fileEncWindowEnd - gflashConfig.fileEncWindowStart); // Ignore out of bound reads - if ( read_address < (FLASH_CONFIG_ADDRESS + FLASH_INTERFACE_SIZE + encoded_data_offset) ) { + if ( read_address < (STORAGE_ADDRESS_END + encoded_data_offset) ) { for (uint32_t i = 0; i < VFS_SECTOR_SIZE; i++) { if (i + (VFS_SECTOR_SIZE * sector_offset) < gflashConfig.fileEncWindowStart) { // If data is before encoding window, no offset is needed data[i] = *(uint8_t *) (read_address + i); } else if(i + (VFS_SECTOR_SIZE * sector_offset) < (gflashConfig.fileEncWindowStart + encoded_data_offset * 2)) { // Data inside encoding window needs to consider encoding window start and size - uint8_t enc_byte = *(uint8_t *) (FLASH_STORAGE_ADDRESS + ((VFS_SECTOR_SIZE * sector_offset) + gflashConfig.fileEncWindowStart + i ) / 2); + uint8_t enc_byte = *(uint8_t *) (STORAGE_ADDRESS_START + ((VFS_SECTOR_SIZE * sector_offset) + gflashConfig.fileEncWindowStart + i ) / 2); if (i % 2 == 0) { // High nibble enc_byte = 0x0F & (enc_byte >> 4); diff --git a/source/board/microbitv2/microbitv2.h b/source/board/microbitv2/microbitv2.h index 26fd94810..4a94273b5 100644 --- a/source/board/microbitv2/microbitv2.h +++ b/source/board/microbitv2/microbitv2.h @@ -41,14 +41,6 @@ #define RESET_LONG_PRESS 120 // x 30ms debounce time = 3600ms #define RESET_MAX_LENGTH_PRESS RESET_LONG_PRESS -#define FLASH_CONFIG_ADDRESS (0x00020000) -#define FLASH_CONFIG_SIZE (0x00000400) -#define FLASH_INTERFACE_SIZE (128*1024) -#define FLASH_STORAGE_ADDRESS (0x00020400) -#define FLASH_CFG_FILENAME "DATA BIN" -#define FLASH_CFG_FILESIZE (126*1024) -#define FLASH_CFG_FILEVISIBLE false - // 'kvld' in hex - key valid #define CFG_KEY 0x6b766c64 diff --git a/source/board/microbitv2/nrf52820/storage.c b/source/board/microbitv2/nrf52820/storage.c index f27c45a9d..d2b697525 100644 --- a/source/board/microbitv2/nrf52820/storage.c +++ b/source/board/microbitv2/nrf52820/storage.c @@ -21,22 +21,45 @@ #include "storage.h" -#include "microbitv2.h" +#include "nrf_nvmc.h" uint32_t storage_program_page(uint32_t adr, uint32_t sz, uint8_t *buf) { - // TODO: Implement this + uint32_t *buf_32 = (uint32_t *)buf; + nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_WRITE); + for (uint32_t i = 0; i < sz / 4; i++) { + ((volatile uint32_t *)adr)[i] = buf_32[i]; + while (!nrf_nvmc_ready_check(NRF_NVMC)) { + // Wait for controller to be ready + } + } + nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_READONLY); + return 0; } uint32_t storage_erase_sector(uint32_t adr) { - // TODO: Implement this + nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_ERASE); + nrf_nvmc_page_erase_start(NRF_NVMC, adr); + while (!nrf_nvmc_ready_check(NRF_NVMC)) { + // Wait for controller to be ready + } + nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_READONLY); + return 0; } uint32_t storage_erase_all() { - // TODO: Implement this + nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_ERASE); + for (uint32_t adr = STORAGE_FLASH_ADDRESS_START; adr < STORAGE_FLASH_ADDRESS_END; adr += STORAGE_SECTOR_SIZE) { + nrf_nvmc_page_erase_start(NRF_NVMC, adr); + while (!nrf_nvmc_ready_check(NRF_NVMC)) { + // Wait for controller to be ready + } + } + nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_READONLY); + return 0; } diff --git a/source/board/microbitv2/nrf52820/storage_config.h b/source/board/microbitv2/nrf52820/storage_config.h new file mode 100644 index 000000000..e482528fa --- /dev/null +++ b/source/board/microbitv2/nrf52820/storage_config.h @@ -0,0 +1,29 @@ +/** + * @file storage_config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright 2021 Micro:bit Educational foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef STORAGE_CONFIG_H_ +#define STORAGE_CONFIG_H_ + +#define STORAGE_FLASH_ADDRESS_START (0x00020000) +#define STORAGE_FLASH_ADDRESS_END (0x00040000) +#define STORAGE_SECTOR_SIZE (0x00001000) + +#endif /* STORAGE_CONFIG_H_ */ diff --git a/source/board/microbitv2/storage.h b/source/board/microbitv2/storage.h index ea2d21db5..908280bb6 100644 --- a/source/board/microbitv2/storage.h +++ b/source/board/microbitv2/storage.h @@ -24,11 +24,33 @@ #define STORAGE_H_ #include +#include "storage_config.h" #ifdef __cplusplus extern "C" { #endif +/** + * For more information viisit the full spec: + * https://github.com/microbit-foundation/spec-i2c-protocol/blob/main/spec/index.md#i2c-flash-interface + * + * ↓ Flash start address for storage ↓ Flash end address + * ↓ ↓ Next flash page ↓ + * ┌---------┬----------------------------------------------┠+ * |[config] |[data.bin ] | + * └---------┴----------------------------------------------┘ + * ↑ storage address 0x0000 ↑ storage address set by file size + */ +#define STORAGE_CONFIG_ADDRESS STORAGE_FLASH_ADDRESS_START +#define STORAGE_CONFIG_SIZE STORAGE_SECTOR_SIZE +#define STORAGE_ADDRESS_START (STORAGE_CONFIG_ADDRESS + STORAGE_CONFIG_SIZE) +#define STORAGE_ADDRESS_END STORAGE_FLASH_ADDRESS_END +#define STORAGE_SIZE (STORAGE_ADDRESS_END - STORAGE_ADDRESS_START) +#define STORAGE_SECTOR_COUNT (STORAGE_SIZE / STORAGE_SECTOR_SIZE) +#define STORAGE_CFG_FILENAME "DATA BIN" +#define STORAGE_CFG_FILEVISIBLE false +#define STORAGE_CFG_FILESIZE (STORAGE_SIZE - STORAGE_SECTOR_SIZE) + uint32_t storage_program_page(uint32_t adr, uint32_t sz, uint8_t *buf); uint32_t storage_erase_sector(uint32_t adr); uint32_t storage_erase_all(void); From f18f9633e0dffad0291475c321e52377d60d5c86 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Mon, 1 Nov 2021 00:58:43 +0000 Subject: [PATCH 468/617] nrf52820_hic: Fix I2C issues caused by leftover debugging code. --- source/board/microbitv2/nrf52820/i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/source/board/microbitv2/nrf52820/i2c.c b/source/board/microbitv2/nrf52820/i2c.c index 0aabd65f0..c6d9446a4 100644 --- a/source/board/microbitv2/nrf52820/i2c.c +++ b/source/board/microbitv2/nrf52820/i2c.c @@ -92,11 +92,11 @@ static void I2C_SignalEvent(uint32_t event) { debug_i2c_data((uint8_t *)"g", 1); } if (event & ARM_I2C_EVENT_SLAVE_RECEIVE) { - int32_t ret = I2Cdrv->SlaveReceive(&g_slave_RX_buff[0], 2 /*I2C_DATA_LENGTH*/); + int32_t ret = I2Cdrv->SlaveReceive(&g_slave_RX_buff[0], I2C_DATA_LENGTH); debug_i2c_printf("rx[%d] ", ret); } if (event & ARM_I2C_EVENT_SLAVE_TRANSMIT) { - int32_t ret = I2Cdrv->SlaveTransmit(g_slave_TX_buff, 10 /*I2C_DATA_LENGTH*/); + int32_t ret = I2Cdrv->SlaveTransmit(&g_slave_TX_buff[0], I2C_DATA_LENGTH); debug_i2c_printf("tx[%d] ", ret); } debug_i2c_data((uint8_t *)".\n", 2); From 409da1290274b2954f718247aee9d5797e108613 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Tue, 2 Nov 2021 23:47:20 +0000 Subject: [PATCH 469/617] nrf52820_hic: Configure NFC pins as GPIO in nRF52833. --- source/board/microbitv2/nrf52820/gpio_extra.c | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/source/board/microbitv2/nrf52820/gpio_extra.c b/source/board/microbitv2/nrf52820/gpio_extra.c index 5234342da..9e852c0e3 100644 --- a/source/board/microbitv2/nrf52820/gpio_extra.c +++ b/source/board/microbitv2/nrf52820/gpio_extra.c @@ -21,6 +21,7 @@ #include "gpio_extra.h" #include "compiler.h" +#include "nrf_nvmc.h" #include "dl_nrf_gpio.h" #define NRF52833_COMBINED_SENSOR_INT_PIN NRF_GPIO_PIN_MAP(0, 9) @@ -35,6 +36,15 @@ static const uint32_t COMBINED_SENSOR_INT_PIN = NRF52820_COMBINED_SENSOR_INT_PIN COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_COMBINED_SENSOR_INT_PIN)); #endif +/* NFC configuration in the User UICR area, needed to configure NFC pins as GPIO */ +#define NRF52833_UICR_NFCPINS_OFFSET (0x20CUL) +#define NRF52833_UCIR_NFCPINS_ADDRESS (NRF_UICR_BASE + NRF52833_UICR_NFCPINS_OFFSET) +#define NRF52833_UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */ +#define NRF52833_UICR_NFCPINS_PROTECT_Msk (0x1UL << NRF52833_UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */ +#define NRF52833_UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins. */ +#define NRF52833_UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation. */ + + void gpio_enable_hid_led() { gpio_cfg_output(GPIO_REG(LED_HID), GPIO_IDX(LED_HID)); @@ -57,6 +67,18 @@ void gpio_init_combined_int() if (NRF_FICR->INFO.PART == 0x52833) { // nRF52833 COMBINED_SENSOR_INT_PIN = NRF52833_COMBINED_SENSOR_INT_PIN; + + // Configure the NFC pins as GPIO in the UICR if not done already + volatile uint32_t* const nrf_uicr_nfcpins = (uint32_t *) NRF52833_UCIR_NFCPINS_ADDRESS; + if ((*nrf_uicr_nfcpins & NRF52833_UICR_NFCPINS_PROTECT_Msk) == + (NRF52833_UICR_NFCPINS_PROTECT_NFC << NRF52833_UICR_NFCPINS_PROTECT_Pos)) { + nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_WRITE); + *nrf_uicr_nfcpins &= ~NRF52833_UICR_NFCPINS_PROTECT_Msk; + while (!nrf_nvmc_ready_check(NRF_NVMC)); + nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_READONLY); + // Changes only take effect after a system reset + NVIC_SystemReset(); + } } else { // nRF52820 COMBINED_SENSOR_INT_PIN = NRF52820_COMBINED_SENSOR_INT_PIN; From 1fa5cfac12ee98b563dccb88dfbff403c5258021 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Wed, 3 Nov 2021 19:46:46 +0000 Subject: [PATCH 470/617] nrf52820_hic: Add base for custom micro:bit bootloader. --- projects.yaml | 4 ++ records/board/nrf52820_microbit_bl.yaml | 4 ++ source/board/nrf52820_microbit_bl.c | 67 +++++++++++++++++++++++++ 3 files changed, 75 insertions(+) create mode 100644 records/board/nrf52820_microbit_bl.yaml create mode 100644 source/board/nrf52820_microbit_bl.c diff --git a/projects.yaml b/projects.yaml index 2510a4fb7..c16b78e50 100644 --- a/projects.yaml +++ b/projects.yaml @@ -498,6 +498,10 @@ projects: - *module_if - *module_hic_max32625 - records/board/max78000fthr.yaml + nrf52820_microbit_bl: + - *module_bl + - records/hic_hal/nrf52820.yaml + - records/board/nrf52820_microbit_bl.yaml nrf52820_microbit_if: - *module_if - *module_hic_nrf52820 diff --git a/records/board/nrf52820_microbit_bl.yaml b/records/board/nrf52820_microbit_bl.yaml new file mode 100644 index 000000000..4bd996c64 --- /dev/null +++ b/records/board/nrf52820_microbit_bl.yaml @@ -0,0 +1,4 @@ +common: + sources: + board: + - source/board/nrf52820_microbit_bl.c diff --git a/source/board/nrf52820_microbit_bl.c b/source/board/nrf52820_microbit_bl.c new file mode 100644 index 000000000..55147c55a --- /dev/null +++ b/source/board/nrf52820_microbit_bl.c @@ -0,0 +1,67 @@ +/** + * @file nrf52820_bl.c + * @brief board ID, meta-data, and additional configuration for micro:bit + * nRF52820 HIC + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2021, ARM Limited, All Rights Reserved + * Copyright (c) 2021 Micro:bit Educational Foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_config.h" +#include "daplink_addr.h" +#include "compiler.h" +#include "target_board.h" +#include "target_family.h" + +// Warning - changing the interface start will break backwards compatibility +COMPILER_ASSERT(DAPLINK_ROM_IF_START == 0x00008000); +COMPILER_ASSERT(DAPLINK_ROM_IF_SIZE == KB(92)); + +/** +* List of start and size for each size of flash sector +* The size will apply to all sectors between the listed address and the next address +* in the list. +* The last pair in the list will have sectors starting at that address and ending +* at address start + size. +*/ +static const sector_info_t sectors_info[] = { + {DAPLINK_ROM_IF_START, 0x1000}, +}; + +// nrf52820 target information +target_cfg_t target_device = { + .sectors_info = sectors_info, + .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), + .flash_regions[0].start = DAPLINK_ROM_IF_START, + .flash_regions[0].end = DAPLINK_ROM_IF_START + DAPLINK_ROM_IF_SIZE, + .flash_regions[0].flags = kRegionIsDefault, + .ram_regions[0].start = DAPLINK_RAM_START, + .ram_regions[0].end = DAPLINK_RAM_START + DAPLINK_RAM_SIZE, + /* .flash_algo not needed for bootloader */ +}; + +// bootloader has no family +const target_family_descriptor_t *g_target_family = NULL; + +const board_info_t g_board_info = { + .info_version = kBoardInfoVersion, + .board_id = "0000", + .daplink_url_name = "HELP_FAQHTM", + .daplink_drive_name = "MAINTENANCE", + .daplink_target_url = "https://microbit.org/device/?id=@B&v=@V&bl=1", + .target_cfg = &target_device, +}; From 58b917c9e20bd84625eed48e1b2424e5ea371a6a Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Wed, 3 Nov 2021 23:10:00 +0000 Subject: [PATCH 471/617] nrf52820_hic: Don't stay in micro:bit bootloader if waken up with reset button. --- source/board/microbitv2/nrf52820/gpio_extra.c | 1 + source/board/nrf52820_microbit_bl.c | 15 +++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/source/board/microbitv2/nrf52820/gpio_extra.c b/source/board/microbitv2/nrf52820/gpio_extra.c index 9e852c0e3..00b9f427c 100644 --- a/source/board/microbitv2/nrf52820/gpio_extra.c +++ b/source/board/microbitv2/nrf52820/gpio_extra.c @@ -77,6 +77,7 @@ void gpio_init_combined_int() while (!nrf_nvmc_ready_check(NRF_NVMC)); nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_READONLY); // Changes only take effect after a system reset + // TODO: This does not seem to reset the system correctly, it hangs somewhere NVIC_SystemReset(); } } else { diff --git a/source/board/nrf52820_microbit_bl.c b/source/board/nrf52820_microbit_bl.c index 55147c55a..377b9548b 100644 --- a/source/board/nrf52820_microbit_bl.c +++ b/source/board/nrf52820_microbit_bl.c @@ -26,6 +26,8 @@ #include "compiler.h" #include "target_board.h" #include "target_family.h" +#include "device.h" +#include "gpio.h" // Warning - changing the interface start will break backwards compatibility COMPILER_ASSERT(DAPLINK_ROM_IF_START == 0x00008000); @@ -65,3 +67,16 @@ const board_info_t g_board_info = { .daplink_target_url = "https://microbit.org/device/?id=@B&v=@V&bl=1", .target_cfg = &target_device, }; + +bool reset_button_pressed() +{ + bool btn_pressed = false; + // Bypass button check if we are waking from System OFF via GPIO (reset button) + if (NRF_POWER->RESETREAS & POWER_RESETREAS_OFF_Msk) { + // Do not clear the flag as it might be needed in the DAPlink interface + btn_pressed = false; + } else { + btn_pressed = gpio_get_reset_btn(); + } + return btn_pressed; +} From e39531b7ad8e94fed3e768f5bac4c46dce0739a6 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Fri, 5 Nov 2021 11:54:27 +0000 Subject: [PATCH 472/617] nrf52820_hic: Move microbit's gflashConfig structure into i2c_commands. --- source/board/microbitv2/i2c_commands.c | 23 ++++++++++++++++- source/board/microbitv2/i2c_commands.h | 1 + source/board/microbitv2/microbitv2.c | 34 +++++++------------------- source/board/microbitv2/microbitv2.h | 3 --- 4 files changed, 32 insertions(+), 29 deletions(-) diff --git a/source/board/microbitv2/i2c_commands.c b/source/board/microbitv2/i2c_commands.c index 3ba7a86f1..817ea5f6a 100644 --- a/source/board/microbitv2/i2c_commands.c +++ b/source/board/microbitv2/i2c_commands.c @@ -39,7 +39,18 @@ extern bool power_led_sleep_state_on; extern bool automatic_sleep_on; extern main_shutdown_state_t main_shutdown_state; extern bool do_remount; -extern flashConfig_t gflashConfig; + +// 'kvld' in hex - key valid +#define CFG_KEY 0x6b766c64 + +flashConfig_t gflashConfig = { + .key = CFG_KEY, + .fileName = STORAGE_CFG_FILENAME, + .fileSize = STORAGE_CFG_FILESIZE, + .fileVisible = STORAGE_CFG_FILEVISIBLE, + .fileEncWindowStart = 0, + .fileEncWindowEnd = 0, +}; static void i2c_write_comms_callback(uint8_t* pData, uint8_t size); @@ -477,9 +488,19 @@ static void i2c_read_flash_callback(uint8_t* pData, uint8_t size) { } void i2c_cmds_init() { + // Load Config from Flash if present + flashConfig_t *pflashConfigROM = (flashConfig_t *) STORAGE_CONFIG_ADDRESS; + if (CFG_KEY == pflashConfigROM->key) { + memcpy(&gflashConfig, pflashConfigROM, sizeof(flashConfig_t)); + } + i2c_initialize(); i2c_registerWriteCallback(i2c_write_comms_callback, I2C_SLAVE_NRF_KL_COMMS); i2c_registerReadCallback(i2c_read_comms_callback, I2C_SLAVE_NRF_KL_COMMS); i2c_registerWriteCallback(i2c_write_flash_callback, I2C_SLAVE_FLASH); i2c_registerReadCallback(i2c_read_flash_callback, I2C_SLAVE_FLASH); } + +flashConfig_t* i2c_cmds_get_storage_config() { + return &gflashConfig; +} diff --git a/source/board/microbitv2/i2c_commands.h b/source/board/microbitv2/i2c_commands.h index 94dab07b9..b3f276e83 100644 --- a/source/board/microbitv2/i2c_commands.h +++ b/source/board/microbitv2/i2c_commands.h @@ -176,6 +176,7 @@ typedef __PACKED_STRUCT i2cFlashCmd_tag { } i2cFlashCmd_t; void i2c_cmds_init(void); +flashConfig_t* i2c_cmds_get_storage_config(void); #ifdef __cplusplus } diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 51fc4fb61..86f7eda80 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -83,15 +83,6 @@ bool automatic_sleep_on = AUTOMATIC_SLEEP_DEFAULT; main_shutdown_state_t main_shutdown_state = MAIN_SHUTDOWN_WAITING; bool do_remount = false; -flashConfig_t gflashConfig = { - .key = CFG_KEY, - .fileName = STORAGE_CFG_FILENAME, - .fileSize = STORAGE_CFG_FILESIZE, - .fileVisible = STORAGE_CFG_FILEVISIBLE, - .fileEncWindowStart = 0, - .fileEncWindowEnd = 0, -}; - extern main_usb_connect_t usb_state; extern bool go_to_sleep; @@ -238,14 +229,6 @@ static void prerun_board_config(void) i2c_cmds_init(); gpio_init_combined_int(); - - // Load Config from Flash if present - flashConfig_t * pflashConfigROM; - pflashConfigROM = (void *)STORAGE_CONFIG_ADDRESS; - - if (CFG_KEY == pflashConfigROM->key) { - memcpy(&gflashConfig, pflashConfigROM, sizeof(flashConfig_t)); - } } // Handle the reset button behavior, this function is called in the main task every 30ms @@ -549,11 +532,11 @@ void vfs_user_build_filesystem_hook() { } } - // Add encoding window file size. 1B encoded into 2B ASCII - file_size = gflashConfig.fileSize + (gflashConfig.fileEncWindowEnd - gflashConfig.fileEncWindowStart); + flashConfig_t* storage_cgf = i2c_cmds_get_storage_config(); + file_size = storage_cgf->fileSize + (storage_cgf->fileEncWindowEnd - storage_cgf->fileEncWindowStart); - if (gflashConfig.fileVisible) { - vfs_create_file(gflashConfig.fileName, read_file_data_txt, 0, file_size); + if (storage_cgf->fileVisible) { + vfs_create_file(storage_cgf->fileName, read_file_data_txt, 0, file_size); } } @@ -561,17 +544,18 @@ void vfs_user_build_filesystem_hook() { static uint32_t read_file_data_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors) { uint32_t read_address = STORAGE_ADDRESS_START + (VFS_SECTOR_SIZE * sector_offset); - uint32_t encoded_data_offset = (gflashConfig.fileEncWindowEnd - gflashConfig.fileEncWindowStart); + flashConfig_t* storage_cgf = i2c_cmds_get_storage_config(); + uint32_t encoded_data_offset = (storage_cgf->fileEncWindowEnd - storage_cgf->fileEncWindowStart); // Ignore out of bound reads if ( read_address < (STORAGE_ADDRESS_END + encoded_data_offset) ) { for (uint32_t i = 0; i < VFS_SECTOR_SIZE; i++) { - if (i + (VFS_SECTOR_SIZE * sector_offset) < gflashConfig.fileEncWindowStart) { + if (i + (VFS_SECTOR_SIZE * sector_offset) < storage_cgf->fileEncWindowStart) { // If data is before encoding window, no offset is needed data[i] = *(uint8_t *) (read_address + i); - } else if(i + (VFS_SECTOR_SIZE * sector_offset) < (gflashConfig.fileEncWindowStart + encoded_data_offset * 2)) { + } else if(i + (VFS_SECTOR_SIZE * sector_offset) < (storage_cgf->fileEncWindowStart + encoded_data_offset * 2)) { // Data inside encoding window needs to consider encoding window start and size - uint8_t enc_byte = *(uint8_t *) (STORAGE_ADDRESS_START + ((VFS_SECTOR_SIZE * sector_offset) + gflashConfig.fileEncWindowStart + i ) / 2); + uint8_t enc_byte = *(uint8_t *) (STORAGE_ADDRESS_START + ((VFS_SECTOR_SIZE * sector_offset) + storage_cgf->fileEncWindowStart + i ) / 2); if (i % 2 == 0) { // High nibble enc_byte = 0x0F & (enc_byte >> 4); diff --git a/source/board/microbitv2/microbitv2.h b/source/board/microbitv2/microbitv2.h index 4a94273b5..e744eef86 100644 --- a/source/board/microbitv2/microbitv2.h +++ b/source/board/microbitv2/microbitv2.h @@ -41,9 +41,6 @@ #define RESET_LONG_PRESS 120 // x 30ms debounce time = 3600ms #define RESET_MAX_LENGTH_PRESS RESET_LONG_PRESS -// 'kvld' in hex - key valid -#define CFG_KEY 0x6b766c64 - typedef enum main_shutdown_state { MAIN_SHUTDOWN_WAITING = 0, MAIN_SHUTDOWN_WAITING_OFF, From ee4870656ba048b335fd28984efee0ebcc1d461a Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Sun, 7 Nov 2021 23:27:02 +0000 Subject: [PATCH 473/617] nrf52820_hic: Reset storage settings in RAM with erase.act When the erase.act file is used it should delete all the storage data and settings. Before this fix the drive would remount and still load the old settings from RAM. --- source/board/microbitv2/i2c_commands.c | 9 +++++++++ source/board/microbitv2/i2c_commands.h | 1 + source/board/microbitv2/microbitv2.c | 1 + 3 files changed, 11 insertions(+) diff --git a/source/board/microbitv2/i2c_commands.c b/source/board/microbitv2/i2c_commands.c index 817ea5f6a..9eb019024 100644 --- a/source/board/microbitv2/i2c_commands.c +++ b/source/board/microbitv2/i2c_commands.c @@ -504,3 +504,12 @@ void i2c_cmds_init() { flashConfig_t* i2c_cmds_get_storage_config() { return &gflashConfig; } + +void i2c_cmds_reset_storate_config() { + gflashConfig = (flashConfig_t) { + .key = CFG_KEY, + .fileName = STORAGE_CFG_FILENAME, + .fileSize = STORAGE_CFG_FILESIZE, + .fileVisible = STORAGE_CFG_FILEVISIBLE, + }; +} diff --git a/source/board/microbitv2/i2c_commands.h b/source/board/microbitv2/i2c_commands.h index b3f276e83..d8002e882 100644 --- a/source/board/microbitv2/i2c_commands.h +++ b/source/board/microbitv2/i2c_commands.h @@ -177,6 +177,7 @@ typedef __PACKED_STRUCT i2cFlashCmd_tag { void i2c_cmds_init(void); flashConfig_t* i2c_cmds_get_storage_config(void); +void i2c_cmds_reset_storate_config(void); #ifdef __cplusplus } diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 86f7eda80..af3aec292 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -497,6 +497,7 @@ bool vfs_user_magic_file_hook(const vfs_filename_t filename, bool *do_remount) if (!memcmp(filename, "ERASE ACT", sizeof(vfs_filename_t))) { // Erase last 128KB flash block storage_erase_all(); + i2c_cmds_reset_storate_config(); } return false; From f73a44a12e645408679faa2bc6fd02f02b0e9253 Mon Sep 17 00:00:00 2001 From: Martin Williams Date: Wed, 20 Oct 2021 10:52:35 +0100 Subject: [PATCH 474/617] Implement nRF52820 power.c --- source/board/microbitv2/nrf52820/power.c | 180 ++++++++++++++++++++++- 1 file changed, 177 insertions(+), 3 deletions(-) diff --git a/source/board/microbitv2/nrf52820/power.c b/source/board/microbitv2/nrf52820/power.c index 916cd1d37..ddf9d8ea2 100644 --- a/source/board/microbitv2/nrf52820/power.c +++ b/source/board/microbitv2/nrf52820/power.c @@ -19,19 +19,193 @@ * limitations under the License. */ +#include "nrf.h" + +#include "gpio.h" +#include "gpio_extra.h" +#include "main_interface.h" +#include "pwr_mon.h" +#include "IO_Config.h" +#include "DAP_config.h" +#include "uart.h" +#include "i2c.h" +#include "rl_usb.h" + #include "power.h" + +static void power_systemoff(); +static void power_wfi(); + +extern volatile uint8_t wake_from_reset; +extern volatile uint8_t wake_from_usb; +extern volatile bool usb_pc_connected; +extern main_usb_connect_t usb_state; +extern power_source_t power_source; + + +uint8_t power_in_WFI; +uint8_t power_gpiote_enabled; +uint32_t power_gpiote_intenset; + + void power_init() { - // TODO + power_in_WFI = 0; + + gpio_cfg_input(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON), RESET_BUTTON_PULL); + + // Enable NRF_POWER interrupt for USB removed/detected + NRF_POWER->INTENSET = POWER_INTENSET_USBREMOVED_Msk + | POWER_INTENSET_USBDETECTED_Msk; + NVIC_EnableIRQ(POWER_CLOCK_IRQn); } void power_down() { - // TODO + power_systemoff(); } void power_sleep() { - // TODO + power_wfi(); +} + + +static void power_before(bool systemoff) +{ + // TODO - wait for USB transmit to computer to finish? + /* Wait for debug console output finished. */ + // while (!(LPUART_STAT_TC_MASK & UART->STAT)) + // { + // } + + uart_uninitialize(); + + // TODO - I think maybe uart_uninitialize does this in USART_Uninitialize + /* Disable pins to lower current leakage */ + // PORT_SetPinMux(UART_PORT, PIN_UART_RX_BIT, kPORT_PinDisabledOrAnalog); + // PORT_SetPinMux(UART_PORT, PIN_UART_TX_BIT, kPORT_PinDisabledOrAnalog); + + gpio_disable_hid_led(); + + /* Disable I/O pin SWCLK, SWDIO */ + PORT_OFF(); + + if (systemoff) + { + i2c_deinitialize(); + // TODO - should i2c_deinitialize call I2Cdrv->Uninitialize() + // so I2C1_SCL & I2C1_SDA get defaulted in nrfx_twis_uninit + + // /* PORTC1 is configured as I2C1_SCL */ + // PORT_SetPinMux(PORTC, 1U, kPORT_PinDisabledOrAnalog); + // /* PORTC2 is configured as I2C1_SDA */ + // PORT_SetPinMux(PORTC, 2U, kPORT_PinDisabledOrAnalog); + } + + // Store NRF_GPIOTE state + power_gpiote_enabled = NVIC_GetEnableIRQ(GPIOTE_IRQn); + power_gpiote_intenset = NRF_GPIOTE->INTENSET; + NRF_GPIOTE->INTENCLR = NRF_GPIOTE->INTENSET; + + // Enable IRQ from RESET_BUTTON + gpio_cfg(GPIO_REG(RESET_BUTTON), + GPIO_IDX(RESET_BUTTON), + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + RESET_BUTTON_PULL, + NRF_GPIO_PIN_S0S1, + RESET_BUTTON_PULL == NRF_GPIO_PIN_PULLUP ? GPIO_PIN_CNF_SENSE_Low : GPIO_PIN_CNF_SENSE_High); + NRF_GPIOTE->INTENSET = power_gpiote_intenset | ( GPIOTE_INTENSET_PORT_Set << GPIOTE_INTENSET_PORT_Pos); + NVIC_EnableIRQ(GPIOTE_IRQn); + + wake_from_usb = 0; + wake_from_reset = 0; +} + +static void power_after() +{ + // Restore GPIOTE state + if (!power_gpiote_enabled) + { + NVIC_DisableIRQ(GPIOTE_IRQn); + } + NRF_GPIOTE->INTENSET = power_gpiote_intenset; + + // Disable RESET_BUTTON edge events + gpio_cfg_input(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON), RESET_BUTTON_PULL); + + /* Configure I/O pin SWCLK, SWDIO */ + PORT_SWD_SETUP(); + + // TODO - done by uart_initialize? + // /* re-configure pinmux of disabled pins */ + // PORT_SetPinMux(UART_PORT, PIN_UART_RX_BIT, (port_mux_t)PIN_UART_RX_MUX_ALT); + // PORT_SetPinMux(UART_PORT, PIN_UART_TX_BIT, (port_mux_t)PIN_UART_TX_MUX_ALT); + + uart_initialize(); + i2c_deinitialize(); + i2c_initialize(); +} + + +static void power_systemoff() +{ + power_before(true /*systemoff*/); + NRF_POWER->SYSTEMOFF = 1; + //never get here +} + +static void power_wfi() +{ + power_before(false /*systemoff*/); + power_in_WFI = 1; + __WFI(); + power_in_WFI = 0; + power_after( false /*systemoff*/); +} + +// TODO - It feels wrong to call pwr_mon_get_power_source() and the USB functions in the IRQ handler +void POWER_CLOCK_IRQHandler(void) +{ + if (NRF_POWER->EVENTS_USBDETECTED) + { + NRF_POWER->EVENTS_USBDETECTED = 0; + power_source = pwr_mon_get_power_source(); + if (power_in_WFI) + { + wake_from_usb = 1; + } + usb_pc_connected = true; + } + + if (NRF_POWER->EVENTS_USBREMOVED) + { + NRF_POWER->EVENTS_USBREMOVED = 0; + power_source = pwr_mon_get_power_source(); + if (power_in_WFI) + { + wake_from_usb = 1; + } + /* Reset USB on cable detach (VBUS falling edge) */ + USBD_Reset(); + usbd_reset_core(); + usb_pc_connected = false; + usb_state = USB_DISCONNECTED; + } +} + + +void GPIOTE_IRQHandler(void) +{ + if (NRF_GPIOTE->EVENTS_PORT) + { + NRF_GPIOTE->EVENTS_PORT = 0; + + if (power_in_WFI && GPIO_REG(RESET_BUTTON)->LATCH & (1 << GPIO_IDX(RESET_BUTTON))) + { + wake_from_reset = 1; + } + } } From 1e87c5d80b41fdf531d016e1f79b9dc67674f3c8 Mon Sep 17 00:00:00 2001 From: Martin Williams Date: Wed, 20 Oct 2021 14:53:12 +0100 Subject: [PATCH 475/617] nRF52820 power.c - update for contributing guidelines --- source/board/microbitv2/nrf52820/power.c | 49 +++++++++++------------- 1 file changed, 23 insertions(+), 26 deletions(-) diff --git a/source/board/microbitv2/nrf52820/power.c b/source/board/microbitv2/nrf52820/power.c index ddf9d8ea2..922029872 100644 --- a/source/board/microbitv2/nrf52820/power.c +++ b/source/board/microbitv2/nrf52820/power.c @@ -34,9 +34,15 @@ #include "power.h" +static void power_before(bool systemoff); +static void power_after(); static void power_systemoff(); static void power_wfi(); +void POWER_CLOCK_IRQHandler(void); +void GPIOTE_IRQHandler(void); + + extern volatile uint8_t wake_from_reset; extern volatile uint8_t wake_from_usb; extern volatile bool usb_pc_connected; @@ -44,20 +50,19 @@ extern main_usb_connect_t usb_state; extern power_source_t power_source; -uint8_t power_in_WFI; +uint8_t power_in_wfi; uint8_t power_gpiote_enabled; uint32_t power_gpiote_intenset; void power_init() { - power_in_WFI = 0; + power_in_wfi = 0; gpio_cfg_input(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON), RESET_BUTTON_PULL); - + // Enable NRF_POWER interrupt for USB removed/detected - NRF_POWER->INTENSET = POWER_INTENSET_USBREMOVED_Msk - | POWER_INTENSET_USBDETECTED_Msk; + NRF_POWER->INTENSET = POWER_INTENSET_USBREMOVED_Msk | POWER_INTENSET_USBDETECTED_Msk; NVIC_EnableIRQ(POWER_CLOCK_IRQn); } @@ -92,8 +97,7 @@ static void power_before(bool systemoff) /* Disable I/O pin SWCLK, SWDIO */ PORT_OFF(); - if (systemoff) - { + if (systemoff) { i2c_deinitialize(); // TODO - should i2c_deinitialize call I2Cdrv->Uninitialize() // so I2C1_SCL & I2C1_SDA get defaulted in nrfx_twis_uninit @@ -117,6 +121,7 @@ static void power_before(bool systemoff) RESET_BUTTON_PULL, NRF_GPIO_PIN_S0S1, RESET_BUTTON_PULL == NRF_GPIO_PIN_PULLUP ? GPIO_PIN_CNF_SENSE_Low : GPIO_PIN_CNF_SENSE_High); + NRF_GPIOTE->INTENSET = power_gpiote_intenset | ( GPIOTE_INTENSET_PORT_Set << GPIOTE_INTENSET_PORT_Pos); NVIC_EnableIRQ(GPIOTE_IRQn); @@ -127,8 +132,7 @@ static void power_before(bool systemoff) static void power_after() { // Restore GPIOTE state - if (!power_gpiote_enabled) - { + if (!power_gpiote_enabled) { NVIC_DisableIRQ(GPIOTE_IRQn); } NRF_GPIOTE->INTENSET = power_gpiote_intenset; @@ -160,32 +164,29 @@ static void power_systemoff() static void power_wfi() { power_before(false /*systemoff*/); - power_in_WFI = 1; + power_in_wfi = 1; __WFI(); - power_in_WFI = 0; - power_after( false /*systemoff*/); + power_in_wfi = 0; + power_after(false /*systemoff*/); } + // TODO - It feels wrong to call pwr_mon_get_power_source() and the USB functions in the IRQ handler void POWER_CLOCK_IRQHandler(void) { - if (NRF_POWER->EVENTS_USBDETECTED) - { + if (NRF_POWER->EVENTS_USBDETECTED) { NRF_POWER->EVENTS_USBDETECTED = 0; power_source = pwr_mon_get_power_source(); - if (power_in_WFI) - { + if (power_in_wfi) { wake_from_usb = 1; } usb_pc_connected = true; } - if (NRF_POWER->EVENTS_USBREMOVED) - { + if (NRF_POWER->EVENTS_USBREMOVED) { NRF_POWER->EVENTS_USBREMOVED = 0; power_source = pwr_mon_get_power_source(); - if (power_in_WFI) - { + if (power_in_wfi) { wake_from_usb = 1; } /* Reset USB on cable detach (VBUS falling edge) */ @@ -196,15 +197,11 @@ void POWER_CLOCK_IRQHandler(void) } } - void GPIOTE_IRQHandler(void) { - if (NRF_GPIOTE->EVENTS_PORT) - { + if (NRF_GPIOTE->EVENTS_PORT) { NRF_GPIOTE->EVENTS_PORT = 0; - - if (power_in_WFI && GPIO_REG(RESET_BUTTON)->LATCH & (1 << GPIO_IDX(RESET_BUTTON))) - { + if (power_in_wfi && (GPIO_REG(RESET_BUTTON)->LATCH & (1 << GPIO_IDX(RESET_BUTTON)))) { wake_from_reset = 1; } } From d37d7bf07d9c0225b8b5dfbfd2a44d81f12f89c6 Mon Sep 17 00:00:00 2001 From: Martin Williams Date: Wed, 20 Oct 2021 20:42:54 +0100 Subject: [PATCH 476/617] nRF52820 pwm.c implemented --- source/board/microbitv2/nrf52820/pwm.c | 93 +++++++++++++++++++++++--- 1 file changed, 85 insertions(+), 8 deletions(-) diff --git a/source/board/microbitv2/nrf52820/pwm.c b/source/board/microbitv2/nrf52820/pwm.c index 169d2c2fc..23d7f57f8 100644 --- a/source/board/microbitv2/nrf52820/pwm.c +++ b/source/board/microbitv2/nrf52820/pwm.c @@ -19,31 +19,108 @@ * limitations under the License. */ -#include "pwm.h" +#include "nrf.h" + #include "gpio.h" +#include "IO_Config.h" + +#include "pwm.h" + + +static void pwm_stop(); +static void pwm_start(); +static void pwm_configure(); +static void pwm_mark255(uint8_t duty); + +#define PWM_TIMER NRF_TIMER3 +#define PWM_IRQ TIMER3_IRQn +#define PWM_CC_END 0 +#define PWM_CC_MARK 1 + +#define PWM_GPIOTE_CH 0 + +#define PWM_PPI_CLR 0 +#define PWM_PPI_SET 1 + +// Timer frequency = 16MHz / (2 ^ prescaler) +// prescaler 7 => frequency 125000Hz => 8us per tick +// 2550 ticks = 20,400us +#define PWM_PRESCALER 7 +#define PWM_FREQUENCY 125000 +#define PWM_USPERTICK 8 +#define PWM_COUNT_MAX 2550 +#define PWM_DUTY_TO_COUNT(duty) ((uint32_t)(duty) * 10) + void pwm_init() { - // TODO + pwm_configure(); } void pwm_init_pins() { - // TODO + gpio_cfg_output(GPIO_REG(LED_PWR), GPIO_IDX(LED_PWR)); } void pwm_deinit_pins() { - // TODO + gpio_cfg(GPIO_REG(LED_PWR), + GPIO_IDX(LED_PWR), + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); } void pwm_set_dutycycle(uint8_t duty) { - // This is just a hack to turn off the LED when the duty cycle is low enough - // TODO: Actually implement this - if (duty < 10) { + if (duty == 0) { + pwm_stop(); gpio_clear(GPIO_REG(LED_PWR), GPIO_IDX(LED_PWR)); - } else { + } else if (duty == 255) { + pwm_stop(); gpio_set(GPIO_REG(LED_PWR), GPIO_IDX(LED_PWR)); + } else { + PWM_TIMER->CC[PWM_CC_MARK] = PWM_DUTY_TO_COUNT(duty); + pwm_start(); } } + + +static void pwm_stop() +{ + NVIC_DisableIRQ(PWM_IRQ); + NRF_PPI->CHENCLR = NRF_PPI->CHENSET; + PWM_TIMER->TASKS_STOP = 1; +} + +static void pwm_start() +{ + NVIC_EnableIRQ(PWM_IRQ); + NRF_PPI->CHENSET = (1 << PWM_PPI_CLR) | (1 << PWM_PPI_SET); + PWM_TIMER->TASKS_START = 1; +} + +static void pwm_configure() +{ + pwm_stop(); + + PWM_TIMER->BITMODE = TIMER_BITMODE_BITMODE_32Bit << TIMER_BITMODE_BITMODE_Pos; + PWM_TIMER->PRESCALER = PWM_PRESCALER; + PWM_TIMER->SHORTS = TIMER_SHORTS_COMPARE0_CLEAR_Msk << PWM_CC_END; + PWM_TIMER->MODE = TIMER_MODE_MODE_Timer << TIMER_MODE_MODE_Pos; + PWM_TIMER->CC[PWM_CC_MARK] = 1; + PWM_TIMER->CC[PWM_CC_END] = PWM_COUNT_MAX; + + NRF_GPIOTE->CONFIG[PWM_GPIOTE_CH] = LED_PWR << GPIOTE_CONFIG_PSEL_Pos | + GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos | + GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos | + GPIOTE_CONFIG_OUTINIT_High << GPIOTE_CONFIG_OUTINIT_Pos; + + NRF_PPI->CH[PWM_PPI_CLR].EEP = (uint32_t)&PWM_TIMER->EVENTS_COMPARE[PWM_CC_MARK]; + NRF_PPI->CH[PWM_PPI_CLR].TEP = (uint32_t)&NRF_GPIOTE->TASKS_CLR[PWM_GPIOTE_CH]; + + NRF_PPI->CH[PWM_PPI_SET].EEP = (uint32_t)&PWM_TIMER->EVENTS_COMPARE[PWM_CC_END]; + NRF_PPI->CH[PWM_PPI_SET].TEP = (uint32_t)&NRF_GPIOTE->TASKS_SET[PWM_GPIOTE_CH]; +} From 62b4fd0494ed7c8c040829206d49f3aeeb1befe5 Mon Sep 17 00:00:00 2001 From: Martin Williams Date: Wed, 20 Oct 2021 21:34:56 +0100 Subject: [PATCH 477/617] nRF52820 implement i2c_deinitialize() --- source/board/microbitv2/nrf52820/i2c.c | 2 +- source/board/microbitv2/nrf52820/power.c | 9 +-------- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/source/board/microbitv2/nrf52820/i2c.c b/source/board/microbitv2/nrf52820/i2c.c index c6d9446a4..5fa74a695 100644 --- a/source/board/microbitv2/nrf52820/i2c.c +++ b/source/board/microbitv2/nrf52820/i2c.c @@ -113,7 +113,7 @@ void i2c_initialize() void i2c_deinitialize() { - // TODO + I2Cdrv->Uninitialize(); } i2c_status_t i2c_registerWriteCallback(i2cWriteCallback_t writeCallback, uint8_t slaveAddress) diff --git a/source/board/microbitv2/nrf52820/power.c b/source/board/microbitv2/nrf52820/power.c index 922029872..44d33af49 100644 --- a/source/board/microbitv2/nrf52820/power.c +++ b/source/board/microbitv2/nrf52820/power.c @@ -98,14 +98,7 @@ static void power_before(bool systemoff) PORT_OFF(); if (systemoff) { - i2c_deinitialize(); - // TODO - should i2c_deinitialize call I2Cdrv->Uninitialize() - // so I2C1_SCL & I2C1_SDA get defaulted in nrfx_twis_uninit - - // /* PORTC1 is configured as I2C1_SCL */ - // PORT_SetPinMux(PORTC, 1U, kPORT_PinDisabledOrAnalog); - // /* PORTC2 is configured as I2C1_SDA */ - // PORT_SetPinMux(PORTC, 2U, kPORT_PinDisabledOrAnalog); + i2c_deinitialize(); // disables I2C SCL & SDA } // Store NRF_GPIOTE state From 053100245c28dcf92e47269959e250c4531d5451 Mon Sep 17 00:00:00 2001 From: Martin Williams Date: Wed, 20 Oct 2021 22:14:32 +0100 Subject: [PATCH 478/617] nRF52820 power.c - no need to configure UART pins --- source/board/microbitv2/nrf52820/power.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/source/board/microbitv2/nrf52820/power.c b/source/board/microbitv2/nrf52820/power.c index 44d33af49..5e80eaac6 100644 --- a/source/board/microbitv2/nrf52820/power.c +++ b/source/board/microbitv2/nrf52820/power.c @@ -85,12 +85,7 @@ static void power_before(bool systemoff) // { // } - uart_uninitialize(); - - // TODO - I think maybe uart_uninitialize does this in USART_Uninitialize - /* Disable pins to lower current leakage */ - // PORT_SetPinMux(UART_PORT, PIN_UART_RX_BIT, kPORT_PinDisabledOrAnalog); - // PORT_SetPinMux(UART_PORT, PIN_UART_TX_BIT, kPORT_PinDisabledOrAnalog); + uart_uninitialize(); // disables RX and TX pins gpio_disable_hid_led(); @@ -136,11 +131,6 @@ static void power_after() /* Configure I/O pin SWCLK, SWDIO */ PORT_SWD_SETUP(); - // TODO - done by uart_initialize? - // /* re-configure pinmux of disabled pins */ - // PORT_SetPinMux(UART_PORT, PIN_UART_RX_BIT, (port_mux_t)PIN_UART_RX_MUX_ALT); - // PORT_SetPinMux(UART_PORT, PIN_UART_TX_BIT, (port_mux_t)PIN_UART_TX_MUX_ALT); - uart_initialize(); i2c_deinitialize(); i2c_initialize(); From af98cf6b34177e43d61191da23ccb640b2180f63 Mon Sep 17 00:00:00 2001 From: Martin Williams Date: Wed, 27 Oct 2021 17:28:12 +0100 Subject: [PATCH 479/617] nRF52820 power_mon.c with nRF52833 pwr_mon_adc.c&.h --- source/board/microbitv2/nrf52820/pwr_mon.c | 356 +++++++++++++++++- .../board/microbitv2/nrf52820/pwr_mon_adc.c | 125 ++++++ .../board/microbitv2/nrf52820/pwr_mon_adc.h | 41 ++ 3 files changed, 511 insertions(+), 11 deletions(-) create mode 100644 source/board/microbitv2/nrf52820/pwr_mon_adc.c create mode 100644 source/board/microbitv2/nrf52820/pwr_mon_adc.h diff --git a/source/board/microbitv2/nrf52820/pwr_mon.c b/source/board/microbitv2/nrf52820/pwr_mon.c index a2d97c6e3..9a0a2e90f 100644 --- a/source/board/microbitv2/nrf52820/pwr_mon.c +++ b/source/board/microbitv2/nrf52820/pwr_mon.c @@ -19,27 +19,361 @@ * limitations under the License. */ +#include "nrf.h" + +#include "IO_Config.h" + +#include "pwr_mon_adc.h" #include "pwr_mon.h" -void pwr_mon_init() +// Define to enable debugging +//#define PWR_MON_DEBUG 1 + +#ifdef PWR_MON_DEBUG + +#define MSC_DEBUG 1 +#include "daplink_debug.h" + +uint32_t bat_lo = 0xFFFFFFFF; +uint32_t bat_hi = 0; + +uint32_t vin_lo = 0xFFFFFFFF; +uint32_t vin_hi = 0; + +uint32_t nousb_vin = 0; +uint32_t nousb_bat = 0; + +uint32_t low_vin = 0; +uint32_t low_bat = 0; + +uint32_t dbg_bat[50]; +uint32_t dbg_cc[50]; +uint32_t dbg_count; + +uint32_t dbg_bat_nousb[50]; +uint32_t dbg_cc_nousb[50]; +uint32_t dbg_count_nousb; +#endif // PWR_MON_DEBUG + + +static void power_pins_init(); +uint32_t pwr_mon_get_vbat_mv_imp(); +static uint32_t pwr_mon_comp_mv(uint32_t psel, uint32_t vref, uint32_t *comps_count); + + +// Volatge monitor pins +// RUN_VBAT_SENSE Enable Battery Voltage monitor +// VBAT_SENSE Battery Voltage monitor +// VBUS_ABSENT High when USB power is not connected (WAKE_ON_EDGE) + +#define NRF52833_PIN_RUN_VBAT_SENSE NRF_GPIO_PIN_MAP(0, 31) +#define NRF52833_PIN_VBAT_SENSE NRF_GPIO_PIN_MAP(0, 30) +#define NRF52833_PIN_VBAT_SENSE_COMP 6 //COMP_PSEL_PSEL_AnalogInput6 +#define NRF52833_PIN_VIN_COMP 0 //Not available +#define NRF52833_PIN_VBUS_ABSENT NRF_GPIO_PIN_MAP(0, 11) + +#define NRF52820_PIN_RUN_VBAT_SENSE NRF_GPIO_PIN_MAP(0, 2) +#define NRF52820_PIN_VBAT_SENSE NRF_GPIO_PIN_MAP(0, 3) +#define NRF52820_PIN_VBAT_SENSE_COMP COMP_PSEL_PSEL_AnalogInput1 +#define NRF52820_PIN_VIN_COMP COMP_PSEL_PSEL_VddhDiv5 +#define NRF52820_PIN_VBUS_ABSENT NRF_GPIO_PIN_MAP(0, 7) + +#ifdef NRF528XX_DYNAMIC_PIN + +uint32_t pin_run_vbat_sense; +uint32_t pin_vbat_sense; +uint32_t pin_vbat_sense_comp; +uint32_t pin_vin_comp; +uint32_t pin_vbus_absent; + +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52833(NRF52833_PIN_RUN_VBAT_SENSE)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52833(NRF52833_PIN_VBAT_SENSE)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52833(NRF52833_PIN_VBUS_ABSENT)); + +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_PIN_RUN_VBAT_SENSE)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_PIN_VBAT_SENSE)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_PIN_VBUS_ABSENT)); +#else +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_PIN_RUN_VBAT_SENSE)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_PIN_VBAT_SENSE)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_PIN_VBUS_ABSENT)); +#endif + +#ifdef NRF528XX_DYNAMIC_PIN +#define PIN_RUN_VBAT_SENSE pin_run_vbat_sense +#define PIN_VBAT_SENSE pin_vbat_sense +#define PIN_VBAT_SENSE_COMP pin_vbat_sense_comp +#define PIN_VIN_COMP pin_vin_comp +#define PIN_VBUS_ABSENT pin_vbus_absent +#else +#define PIN_RUN_VBAT_SENSE NRF52820_PIN_RUN_VBAT_SENSE +#define PIN_VBAT_SENSE NRF52820_PIN_VBAT_SENSE +#define PIN_VBAT_SENSE_COMP NRF52820_PIN_VBAT_SENSE_COMP +#define PIN_VIN_COMP NRF52820_PIN_VIN_COMP +#define PIN_VBUS_ABSENT NRF52820_PIN_VBUS_ABSENT +#endif + +static void power_pins_init() +{ +#ifdef NRF528XX_DYNAMIC_PIN + if (NRF_FICR->INFO.PART == 0x52833) { + // nRF52833 + pin_run_vbat_sense = NRF52833_PIN_RUN_VBAT_SENSE; + pin_vbat_sense = NRF52833_PIN_VBAT_SENSE; + pin_vbat_sense_comp = NRF52833_PIN_VBAT_SENSE_COMP; + pin_vin_comp = NRF52833_PIN_VIN_COMP; + pin_vbus_absent = NRF52833_PIN_VBUS_ABSENT; + } else { + // nRF52820 + pin_run_vbat_sense = NRF52820_PIN_RUN_VBAT_SENSE; + pin_vbat_sense = NRF52820_PIN_VBAT_SENSE; + pin_vbat_sense_comp = NRF52820_PIN_VBAT_SENSE_COMP; + pin_vin_comp = NRF52820_PIN_VIN_COMP; + pin_vbus_absent = NRF52820_PIN_VBUS_ABSENT; + } +#endif +} + + +void pwr_mon_init(void) +{ + power_pins_init(); + + // Configure VMON_BAT and RUN_VBAT_SENSE + gpio_cfg_output(GPIO_REG(PIN_RUN_VBAT_SENSE), GPIO_IDX(PIN_RUN_VBAT_SENSE)); + gpio_cfg_input(GPIO_REG(PIN_VBAT_SENSE), GPIO_IDX(PIN_VBAT_SENSE), NRF_GPIO_PIN_NOPULL); + gpio_cfg_input(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT), NRF_GPIO_PIN_NOPULL); +} + + +power_source_t pwr_mon_get_power_source(void) +{ + uint32_t bat_min_voltage = 1550; + uint32_t bat_voltage_mv = 0; + uint32_t vin_voltage_mv = 0; + power_source_t power_source = PWR_SOURCE_NONE; + + // Read VBUS_ABSENT (WAKE_ON_EDGE) pin for detecting if board is USB powered + bool usb_on = gpio_read(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT)) ? false : true; + + // Read battery voltage + // Allow ~3ms for the 100nF capacitors to charge to about 3*RC. + // The voltage should reach bat_min_voltage within 3ms if a battery is present + bat_voltage_mv = pwr_mon_get_vbat_mv_imp( 3000, bat_min_voltage); + + // Read Vin voltage + //vin_voltage_mv = pwr_mon_get_vin_mv(); + + // Get power source based on battery and USB + if (usb_on) { + power_source = bat_voltage_mv < bat_min_voltage ? PWR_USB_ONLY : PWR_USB_AND_BATT; + } else if (bat_voltage_mv >= bat_min_voltage) { + power_source = PWR_BATT_ONLY; + // TODO? If battery voltage is greater than Vin, it means the battery is used + // With nRF52820, bat values after 3ms are much less than vin. The max is reached after 11-13ms + // bat values are greater with battery + USB or EC than battery alone + // if (bat_voltage_mv + 250 > vin_voltage_mv) { + // power_source = PWR_BATT_ONLY; + // } + } + +#ifdef PWR_MON_DEBUG + if (gpio_read(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT))) { + nousb_vin = vin_voltage_mv; + nousb_bat = bat_voltage_mv; + if (bat_voltage_mv < bat_min_voltage) { + low_vin = vin_voltage_mv; + low_bat = bat_voltage_mv; + } + } + debug_msg("PIN_VBUS_ABSENT %d usb_on %d\n", (int) PIN_VBUS_ABSENT, usb_on ? 1 : 0); + debug_msg("vin %d bat %d nousb vin %d bat %d low vin %d bat %d\n", (int) vin_voltage_mv, (int) bat_voltage_mv, (int) nousb_vin, (int) nousb_bat, (int) low_vin, (int) low_bat); +#endif // PWR_MON_DEBUG + + return power_source; +} + +uint32_t pwr_mon_get_vin_mv(void) { - // TODO + uint32_t vin; + + if (NRF_FICR->INFO.PART == 0x52833) { + // nRF52833 +#ifdef PWR_MON_DEBUG + debug_msg("pwr_mon_adc_vin\n"); +#endif // PWR_MON_DEBUG + vin = pwr_mon_adc_vin(); + } else { +#ifdef PWR_MON_DEBUG + debug_msg("pwr_mon_comp_mv(%d)\n", (int) PIN_VIN_COMP); +#endif // PWR_MON_DEBUG + vin = pwr_mon_comp_mv(PIN_VIN_COMP, COMP_REFSEL_REFSEL_Int1V2, NULL); + } + +#ifdef PWR_MON_DEBUG + if ( gpio_read(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT))) { + if ( vin_lo > vin) vin_lo = vin; + if ( vin_hi < vin) vin_hi = vin; + } + debug_msg("vin %d low vin %d bat %d\n", (int) vin, (int) low_vin, (int) low_bat); +#endif // PWR_MON_DEBUG + + return vin; } -power_source_t pwr_mon_get_power_source() +uint32_t pwr_mon_get_vbat_mv(void) { - // TODO - return PWR_SOURCE_NONE; + uint32_t bat = pwr_mon_get_vbat_mv_imp( 11100, 3300); + +#ifdef PWR_MON_DEBUG + debug_msg("bat %d\n", (int) bat); +#endif // PWR_MON_DEBUG + return bat; } -uint32_t pwr_mon_get_vin_mv() + +/** + * Measures VBAT_SENSE voltage + * @param max_us Approximate maximum time to wait in microseconds + * @param max_mv Stop when detected voltage is at least this value. Zero for no maximum. + * @return Voltage in millivolts. + */ +uint32_t pwr_mon_get_vbat_mv_imp( uint32_t max_us, uint32_t max_mv) { - // TODO - return 0; + uint32_t max_comps = (max_us + 49) / 50; // Each COMP typically takes >50us + uint32_t bat; + uint32_t comps_count = 0; + +#ifdef PWR_MON_DEBUG + dbg_count = 0; + debug_msg("\n"); + debug_msg("pwr_mon_get_vbat_mv_imp(%d,%d) run %d comp %d\n", (int) max_us, (int) max_mv, (int) PIN_RUN_VBAT_SENSE, (int) PIN_VBAT_SENSE_COMP); +#endif // PWR_MON_DEBUG + + // Enable voltage divider to take measurement + gpio_write(GPIO_REG(PIN_RUN_VBAT_SENSE), GPIO_IDX(PIN_RUN_VBAT_SENSE), 1); + + while (true) { + bat = pwr_mon_comp_mv(PIN_VBAT_SENSE_COMP, COMP_REFSEL_REFSEL_Int1V2, &comps_count); + // Compensate for voltage divider + bat = 4017 * bat / 1000; + +#ifdef PWR_MON_DEBUG + if ( dbg_count < 50) { + dbg_bat[dbg_count] = bat; + dbg_cc[dbg_count] = comps_count; + dbg_count++; + } +#endif // PWR_MON_DEBUG + + if ( comps_count >= max_comps) { + break; + } + + if ( max_mv > 0 && bat >= max_mv) { + break; + } + } + + // Disable voltage divider + gpio_write(GPIO_REG(PIN_RUN_VBAT_SENSE), GPIO_IDX(PIN_RUN_VBAT_SENSE), 0); + +#ifdef PWR_MON_DEBUG + if ( gpio_read(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT))) { + for (int i = 0; i < dbg_count; i++) { + dbg_bat_nousb[i] = dbg_bat[i]; + dbg_cc_nousb[i] = dbg_cc[i]; + } + dbg_count_nousb = dbg_count; + } + + if ( gpio_read(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT))) { + if ( bat_lo > bat) bat_lo = bat; + if ( bat_hi < bat) bat_hi = bat; + } + + // int num = dbg_count_nousb >= 50 ? 50 : dbg_count_nousb; + // for (int i = 0; i < num; i++) { + // debug_msg("%d,%d\n", (int) dbg_cc_nousb[dbg_count_nousb - num + i], (int) dbg_bat_nousb[dbg_count_nousb - num + i]); + // } + + // int numnum = dbg_count >= 50 ? 50 : dbg_count; + // for (int i = 0; i < numnum; i++) { + // debug_msg("%d,%d\n", (int) dbg_cc[dbg_count - numnum + i], (int) dbg_bat[dbg_count - numnum + i]); + // } + + //debug_msg("vin lo %d hi %d bat lo %d hi %d\n", (int) vin_lo, (int) vin_hi, (int) bat_lo, (int) bat_hi); +#endif // PWR_MON_DEBUG + + return bat; } -uint32_t pwr_mon_get_vbat_mv() + +/** + * Measures a voltage using COMP peripheral + * @param psel NRF_COMP PSEL value + * @param vref NRF_COMP internal REFSEL value + * @param comps_count Pointer to integer to be incremented for each COMP sample. May be NULL. + * @return Voltage in millivolts. + */ +static uint32_t pwr_mon_comp_mv(uint32_t psel, uint32_t vref, uint32_t *comps_count) { - // TODO - return 0; + uint32_t comps = comps_count ? *comps_count : 0; + uint32_t mv = 0; + int th0 = 0; + int th1 = 63; + int thmax = 0; + int th; + + NRF_COMP->TASKS_STOP = 1; + NRF_COMP->ENABLE = COMP_ENABLE_ENABLE_Disabled << COMP_ENABLE_ENABLE_Pos; + NRF_COMP->SHORTS = 0; + NRF_COMP->INTENCLR = NRF_COMP->INTENSET; + NRF_COMP->HYST = COMP_HYST_HYST_NoHyst << COMP_HYST_HYST_Pos; + NRF_COMP->REFSEL = (vref << COMP_REFSEL_REFSEL_Pos); + NRF_COMP->PSEL = psel << COMP_PSEL_PSEL_Pos; + NRF_COMP->MODE = (COMP_MODE_MAIN_SE << COMP_MODE_MAIN_Pos) | (COMP_MODE_SP_Normal << COMP_MODE_SP_Pos); // TODO COMP_MODE_SP_Low? + + while ( th1 - th0 > 0) { + th = (th0 + th1 + 1) / 2; + NRF_COMP->TH = ((uint32_t) th << COMP_TH_THUP_Pos) | ((uint32_t) th << COMP_TH_THDOWN_Pos); + NRF_COMP->ENABLE = COMP_ENABLE_ENABLE_Enabled << COMP_ENABLE_ENABLE_Pos; + NRF_COMP->EVENTS_READY = 0; + + NRF_COMP->TASKS_START = 1; + while( !NRF_COMP->EVENTS_READY) /*wait*/; + NRF_COMP->TASKS_SAMPLE = 1; + uint32_t above = NRF_COMP->RESULT; + + NRF_COMP->TASKS_STOP = 1; + NRF_COMP->ENABLE = COMP_ENABLE_ENABLE_Disabled << COMP_ENABLE_ENABLE_Pos; + + if (above) { + th0 = th; + thmax = th; + } else { + th1 = th - 1; + } + + comps++; + } + + if (comps_count) { + *comps_count = comps; + } + + switch (vref) { + case COMP_REFSEL_REFSEL_Int1V2: mv = 1200; break; + case COMP_REFSEL_REFSEL_Int1V8: mv = 1800; break; + case COMP_REFSEL_REFSEL_Int2V4: mv = 2400; break; + } + + mv = mv * thmax / 64; + +#ifdef COMP_PSEL_PSEL_VddhDiv5 + if (psel == COMP_PSEL_PSEL_VddhDiv5) { + return 5 * mv; + } +#endif + return mv; } diff --git a/source/board/microbitv2/nrf52820/pwr_mon_adc.c b/source/board/microbitv2/nrf52820/pwr_mon_adc.c new file mode 100644 index 000000000..fc2413860 --- /dev/null +++ b/source/board/microbitv2/nrf52820/pwr_mon_adc.c @@ -0,0 +1,125 @@ +/** + * @file pwr_mon_adc.c + * @brief + * + * DAPLink Interface Firmware + * Copyright 2021 Micro:bit Educational Foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "nrf52.h" + +#include "pwr_mon_adc.h" + + +static uint32_t pwr_mon_saadc(uint32_t pselp); + +#ifndef __NRF52833_BITS_H + +#define SAADC_CH_PSELP_PSELP_VDDHDIV5 (0x0DUL) +#define SAADC_CH_CONFIG_TACQ_3us (0UL) +#define SAADC_CH_CONFIG_TACQ_10us (2UL) +#define SAADC_RESOLUTION_VAL_14bit (3UL) +#define SAADC_RESOLUTION_VAL_Pos (0UL) +#define SAADC_SAMPLERATE_MODE_Task (0UL) +#define SAADC_SAMPLERATE_MODE_Pos (12UL) +#define SAADC_CH_CONFIG_RESP_Bypass (0UL) +#define SAADC_CH_CONFIG_RESP_Pos (0UL) +#define SAADC_CH_CONFIG_RESN_Bypass (0UL) +#define SAADC_CH_CONFIG_RESN_Pos (4UL) +#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) +#define SAADC_CH_CONFIG_GAIN_Pos (8UL) +#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) +#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) +#define SAADC_CH_CONFIG_TACQ_Pos (16UL) +#define SAADC_CH_CONFIG_MODE_SE (0UL) +#define SAADC_CH_CONFIG_MODE_Pos (20UL) +#define SAADC_CH_CONFIG_BURST_Disabled (0UL) +#define SAADC_CH_CONFIG_BURST_Pos (24UL) +#define SAADC_CH_PSELP_PSELP_Pos (0UL) +#define SAADC_CH_PSELN_PSELN_NC (0UL) +#define SAADC_CH_PSELN_PSELN_Pos (0UL) +#define SAADC_CH_PSELP_PSELP_NC (0UL) + +#endif // __NRF52833_BITS_H + + + +uint32_t pwr_mon_adc_vin() { + return pwr_mon_saadc(SAADC_CH_PSELP_PSELP_VDDHDIV5); +} + + +static uint32_t pwr_mon_saadc(uint32_t pselp) { + volatile int16_t buffer[1]; + uint32_t tacq = pselp == SAADC_CH_PSELP_PSELP_VDDHDIV5 ? SAADC_CH_CONFIG_TACQ_10us : SAADC_CH_CONFIG_TACQ_3us; + + NRF_SAADC->ENABLE = 0; + + NRF_SAADC->RESOLUTION = SAADC_RESOLUTION_VAL_14bit << SAADC_RESOLUTION_VAL_Pos; + NRF_SAADC->SAMPLERATE = SAADC_SAMPLERATE_MODE_Task << SAADC_SAMPLERATE_MODE_Pos; + NRF_SAADC->OVERSAMPLE = 0; + + NRF_SAADC->RESULT.MAXCNT = 1; + NRF_SAADC->RESULT.PTR = (uint32_t) buffer; + + // Input range = REFERENCE/GAIN = 0.6/(1/6) = 3.6V + NRF_SAADC->CH[0].CONFIG = (SAADC_CH_CONFIG_RESP_Bypass << SAADC_CH_CONFIG_RESP_Pos) | + (SAADC_CH_CONFIG_RESN_Bypass << SAADC_CH_CONFIG_RESN_Pos) | + (SAADC_CH_CONFIG_GAIN_Gain1_6 << SAADC_CH_CONFIG_GAIN_Pos) | + (SAADC_CH_CONFIG_REFSEL_Internal << SAADC_CH_CONFIG_REFSEL_Pos) | + (tacq << SAADC_CH_CONFIG_TACQ_Pos) | + (SAADC_CH_CONFIG_MODE_SE << SAADC_CH_CONFIG_MODE_Pos) | + (SAADC_CH_CONFIG_BURST_Disabled << SAADC_CH_CONFIG_BURST_Pos); + + NRF_SAADC->CH[0].PSELP = pselp << SAADC_CH_PSELP_PSELP_Pos; + NRF_SAADC->CH[0].PSELN = SAADC_CH_PSELN_PSELN_NC << SAADC_CH_PSELN_PSELN_Pos; + + for ( int i = 1; i < 8; i++) { + NRF_SAADC->CH[i].CONFIG = NRF_SAADC->CH[0].CONFIG; + NRF_SAADC->CH[i].PSELP = SAADC_CH_PSELP_PSELP_NC << SAADC_CH_PSELP_PSELP_Pos; + NRF_SAADC->CH[i].PSELN = SAADC_CH_PSELN_PSELN_NC << SAADC_CH_PSELN_PSELN_Pos; + } + + NRF_SAADC->ENABLE = 1; + NRF_SAADC->TASKS_START = 1; + while (!NRF_SAADC->EVENTS_STARTED) /*wait*/; + NRF_SAADC->EVENTS_STARTED = 0; + + NRF_SAADC->TASKS_SAMPLE = 1; + while (!NRF_SAADC->EVENTS_END) /*wait*/; + NRF_SAADC->EVENTS_END = 0; + + NRF_SAADC->TASKS_STOP = 1; + while (!NRF_SAADC->EVENTS_STOPPED) /*wait*/; + NRF_SAADC->EVENTS_STOPPED = 0; + + int16_t adc = buffer[0]; + if ( adc < 0) { + adc = 0; + } + + // adc = V * (GAIN/REFERENCE) * (2^RESOLUTION) + // V = (REFERENCE/GAIN) * adc / (2^RESOLUTION) + // V = 3.6 * adc / 16384 + // mV = 3600 * adc / 16384 + // mV = 225 * adc / 1024 + uint32_t mv = 225 * (uint32_t) adc / 1024; + if ( pselp == SAADC_CH_PSELP_PSELP_VDDHDIV5) { + mv *= 5; + } + + return mv; +} diff --git a/source/board/microbitv2/nrf52820/pwr_mon_adc.h b/source/board/microbitv2/nrf52820/pwr_mon_adc.h new file mode 100644 index 000000000..edf6b5365 --- /dev/null +++ b/source/board/microbitv2/nrf52820/pwr_mon_adc.h @@ -0,0 +1,41 @@ +/** + * @file storage_config.h + * @brief + * + * DAPLink Interface Firmware + * Copyright 2021 Micro:bit Educational foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PWR_MON_ADC_H +#define PWR_MON_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * Measures VDDH voltage using SAADC peripheral + * @return Voltage in millivolts. + */ +uint32_t pwr_mon_adc_vin(); + + +#ifdef __cplusplus +} +#endif + +#endif /* PWR_MON_ADC_H_ */ From cf6d35f5fe119abff46277db0e3de8a870f6e068 Mon Sep 17 00:00:00 2001 From: Martin Williams Date: Mon, 1 Nov 2021 18:41:34 +0000 Subject: [PATCH 480/617] nRF52820 limit battery check to 3ms --- source/board/microbitv2/nrf52820/pwm.c | 2 ++ source/board/microbitv2/nrf52820/pwr_mon.c | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/source/board/microbitv2/nrf52820/pwm.c b/source/board/microbitv2/nrf52820/pwm.c index 23d7f57f8..2d97397e8 100644 --- a/source/board/microbitv2/nrf52820/pwm.c +++ b/source/board/microbitv2/nrf52820/pwm.c @@ -93,6 +93,8 @@ static void pwm_stop() NVIC_DisableIRQ(PWM_IRQ); NRF_PPI->CHENCLR = NRF_PPI->CHENSET; PWM_TIMER->TASKS_STOP = 1; + //https://infocenter.nordicsemi.com/topic/errata_nRF52820_Rev3/ERR/nRF52820/Rev3/latest/anomaly_820_78.html + PWM_TIMER->TASKS_SHUTDOWN = 1; } static void pwm_start() diff --git a/source/board/microbitv2/nrf52820/pwr_mon.c b/source/board/microbitv2/nrf52820/pwr_mon.c index 9a0a2e90f..7afab31f0 100644 --- a/source/board/microbitv2/nrf52820/pwr_mon.c +++ b/source/board/microbitv2/nrf52820/pwr_mon.c @@ -223,7 +223,8 @@ uint32_t pwr_mon_get_vin_mv(void) uint32_t pwr_mon_get_vbat_mv(void) { - uint32_t bat = pwr_mon_get_vbat_mv_imp( 11100, 3300); + // CODAL needs a reply within 5ms + uint32_t bat = pwr_mon_get_vbat_mv_imp( 3000, 3300); #ifdef PWR_MON_DEBUG debug_msg("bat %d\n", (int) bat); From 41a0930806def2cceb49d77c1f28ee653e0ad62f Mon Sep 17 00:00:00 2001 From: Martin Williams Date: Fri, 5 Nov 2021 06:33:45 +0000 Subject: [PATCH 481/617] Use VBUS_ABSENT instead of POWER USBREMOVED/USBDETECTED --- .../microbitv2/nrf52820/microbitv2_pins.c | 57 ++++++ .../microbitv2/nrf52820/microbitv2_pins.h | 83 ++++++++ source/board/microbitv2/nrf52820/power.c | 122 +++++++----- source/board/microbitv2/nrf52820/pwr_mon.c | 181 +----------------- 4 files changed, 222 insertions(+), 221 deletions(-) create mode 100644 source/board/microbitv2/nrf52820/microbitv2_pins.c create mode 100644 source/board/microbitv2/nrf52820/microbitv2_pins.h diff --git a/source/board/microbitv2/nrf52820/microbitv2_pins.c b/source/board/microbitv2/nrf52820/microbitv2_pins.c new file mode 100644 index 000000000..bd39df079 --- /dev/null +++ b/source/board/microbitv2/nrf52820/microbitv2_pins.c @@ -0,0 +1,57 @@ +/** + * @file pwr_mon.c + * @brief + * + * DAPLink Interface Firmware + * Copyright 2021 Micro:bit Educational Foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "nrf.h" + +#include "microbitv2_pins.h" + + +#ifdef NRF528XX_DYNAMIC_PIN + +uint32_t pin_run_vbat_sense; +uint32_t pin_vbat_sense; +uint32_t pin_vbat_sense_comp; +uint32_t pin_vin_comp; +uint32_t pin_vbus_absent; + +#endif + + +void microbitv2_pins_init() +{ +#ifdef NRF528XX_DYNAMIC_PIN + if (NRF_FICR->INFO.PART == 0x52833) { + // nRF52833 + pin_run_vbat_sense = NRF52833_PIN_RUN_VBAT_SENSE; + pin_vbat_sense = NRF52833_PIN_VBAT_SENSE; + pin_vbat_sense_comp = NRF52833_PIN_VBAT_SENSE_COMP; + pin_vin_comp = NRF52833_PIN_VIN_COMP; + pin_vbus_absent = NRF52833_PIN_VBUS_ABSENT; + } else { + // nRF52820 + pin_run_vbat_sense = NRF52820_PIN_RUN_VBAT_SENSE; + pin_vbat_sense = NRF52820_PIN_VBAT_SENSE; + pin_vbat_sense_comp = NRF52820_PIN_VBAT_SENSE_COMP; + pin_vin_comp = NRF52820_PIN_VIN_COMP; + pin_vbus_absent = NRF52820_PIN_VBUS_ABSENT; + } +#endif +} diff --git a/source/board/microbitv2/nrf52820/microbitv2_pins.h b/source/board/microbitv2/nrf52820/microbitv2_pins.h new file mode 100644 index 000000000..3420c99b9 --- /dev/null +++ b/source/board/microbitv2/nrf52820/microbitv2_pins.h @@ -0,0 +1,83 @@ +/** + * @file nrf52_pins.h + * @brief + * + * DAPLink Interface Firmware + * Copyright 2021 Micro:bit Educational foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MICROBITV2_PINS_H_ +#define MICROBITV2_PINS_H_ + +#include "IO_Config.h" + + +// Volatge monitor pins +// RUN_VBAT_SENSE Enable Battery Voltage monitor +// VBAT_SENSE Battery Voltage monitor +// VBUS_ABSENT High when USB power is not connected (WAKE_ON_EDGE) + +#define NRF52833_PIN_RUN_VBAT_SENSE NRF_GPIO_PIN_MAP(0, 31) +#define NRF52833_PIN_VBAT_SENSE NRF_GPIO_PIN_MAP(0, 30) +#define NRF52833_PIN_VBAT_SENSE_COMP 6 //COMP_PSEL_PSEL_AnalogInput6 +#define NRF52833_PIN_VIN_COMP 0 //Not available +#define NRF52833_PIN_VBUS_ABSENT NRF_GPIO_PIN_MAP(0, 11) + +#define NRF52820_PIN_RUN_VBAT_SENSE NRF_GPIO_PIN_MAP(0, 2) +#define NRF52820_PIN_VBAT_SENSE NRF_GPIO_PIN_MAP(0, 3) +#define NRF52820_PIN_VBAT_SENSE_COMP COMP_PSEL_PSEL_AnalogInput1 +#define NRF52820_PIN_VIN_COMP COMP_PSEL_PSEL_VddhDiv5 +#define NRF52820_PIN_VBUS_ABSENT NRF_GPIO_PIN_MAP(0, 7) + +#ifdef NRF528XX_DYNAMIC_PIN + +extern uint32_t pin_run_vbat_sense; +extern uint32_t pin_vbat_sense; +extern uint32_t pin_vbat_sense_comp; +extern uint32_t pin_vin_comp; +extern uint32_t pin_vbus_absent; + +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52833(NRF52833_PIN_RUN_VBAT_SENSE)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52833(NRF52833_PIN_VBAT_SENSE)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52833(NRF52833_PIN_VBUS_ABSENT)); + +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_PIN_RUN_VBAT_SENSE)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_PIN_VBAT_SENSE)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_PIN_VBUS_ABSENT)); +#else +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_PIN_RUN_VBAT_SENSE)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_PIN_VBAT_SENSE)); +COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_PIN_VBUS_ABSENT)); +#endif + +#ifdef NRF528XX_DYNAMIC_PIN +#define PIN_RUN_VBAT_SENSE pin_run_vbat_sense +#define PIN_VBAT_SENSE pin_vbat_sense +#define PIN_VBAT_SENSE_COMP pin_vbat_sense_comp +#define PIN_VIN_COMP pin_vin_comp +#define PIN_VBUS_ABSENT pin_vbus_absent +#else +#define PIN_RUN_VBAT_SENSE NRF52820_PIN_RUN_VBAT_SENSE +#define PIN_VBAT_SENSE NRF52820_PIN_VBAT_SENSE +#define PIN_VBAT_SENSE_COMP NRF52820_PIN_VBAT_SENSE_COMP +#define PIN_VIN_COMP NRF52820_PIN_VIN_COMP +#define PIN_VBUS_ABSENT NRF52820_PIN_VBUS_ABSENT +#endif + + +void microbitv2_pins_init(); + +#endif /* MICROBITV2_PINS_H_ */ diff --git a/source/board/microbitv2/nrf52820/power.c b/source/board/microbitv2/nrf52820/power.c index 5e80eaac6..ca81b0400 100644 --- a/source/board/microbitv2/nrf52820/power.c +++ b/source/board/microbitv2/nrf52820/power.c @@ -30,6 +30,7 @@ #include "uart.h" #include "i2c.h" #include "rl_usb.h" +#include "microbitv2_pins.h" #include "power.h" @@ -50,20 +51,32 @@ extern main_usb_connect_t usb_state; extern power_source_t power_source; -uint8_t power_in_wfi; uint8_t power_gpiote_enabled; uint32_t power_gpiote_intenset; void power_init() { - power_in_wfi = 0; + microbitv2_pins_init(); - gpio_cfg_input(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON), RESET_BUTTON_PULL); + // Store NRF_GPIOTE state + power_gpiote_intenset = NRF_GPIOTE->INTENSET; + NRF_GPIOTE->INTENCLR = NRF_GPIOTE->INTENSET; + + // Override hic_hal gpio_init() RESET_BUTTON_PULL (=NRF_GPIO_PIN_PULLUP) + gpio_cfg_input(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON), NRF_GPIO_PIN_NOPULL); + + // Configure VBUS_ABSENT (WAKE_ON_EDGE) pin to detect USB attach/detach */ + gpio_cfg(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT), + NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, + GPIO_PIN_CNF_SENSE_Low | GPIO_PIN_CNF_SENSE_High); - // Enable NRF_POWER interrupt for USB removed/detected - NRF_POWER->INTENSET = POWER_INTENSET_USBREMOVED_Msk | POWER_INTENSET_USBDETECTED_Msk; - NVIC_EnableIRQ(POWER_CLOCK_IRQn); + NRF_GPIOTE->INTENSET = power_gpiote_intenset | ( GPIOTE_INTENSET_PORT_Set << GPIOTE_INTENSET_PORT_Pos); + NVIC_EnableIRQ(GPIOTE_IRQn); + + // // Enable NRF_POWER interrupt for USB removed/detected + // NRF_POWER->INTENSET = POWER_INTENSET_USBREMOVED_Msk | POWER_INTENSET_USBDETECTED_Msk; + // NVIC_EnableIRQ(POWER_CLOCK_IRQn); } void power_down() @@ -101,20 +114,20 @@ static void power_before(bool systemoff) power_gpiote_intenset = NRF_GPIOTE->INTENSET; NRF_GPIOTE->INTENCLR = NRF_GPIOTE->INTENSET; + // Configure VBUS_ABSENT (WAKE_ON_EDGE) pin to detect USB attach */ + gpio_cfg(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT), + NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, + GPIO_PIN_CNF_SENSE_Low); + // Enable IRQ from RESET_BUTTON - gpio_cfg(GPIO_REG(RESET_BUTTON), - GPIO_IDX(RESET_BUTTON), - NRF_GPIO_PIN_DIR_INPUT, - NRF_GPIO_PIN_INPUT_CONNECT, - RESET_BUTTON_PULL, - NRF_GPIO_PIN_S0S1, - RESET_BUTTON_PULL == NRF_GPIO_PIN_PULLUP ? GPIO_PIN_CNF_SENSE_Low : GPIO_PIN_CNF_SENSE_High); + gpio_cfg(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON), + NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, + GPIO_PIN_CNF_SENSE_Low); NRF_GPIOTE->INTENSET = power_gpiote_intenset | ( GPIOTE_INTENSET_PORT_Set << GPIOTE_INTENSET_PORT_Pos); NVIC_EnableIRQ(GPIOTE_IRQn); wake_from_usb = 0; - wake_from_reset = 0; } static void power_after() @@ -125,8 +138,13 @@ static void power_after() } NRF_GPIOTE->INTENSET = power_gpiote_intenset; + // Configure VBUS_ABSENT (WAKE_ON_EDGE) pin to detect USB attach/detach */ + gpio_cfg(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT), + NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, + GPIO_PIN_CNF_SENSE_Low | GPIO_PIN_CNF_SENSE_High); + // Disable RESET_BUTTON edge events - gpio_cfg_input(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON), RESET_BUTTON_PULL); + gpio_cfg_input(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON), NRF_GPIO_PIN_NOPULL); /* Configure I/O pin SWCLK, SWDIO */ PORT_SWD_SETUP(); @@ -147,45 +165,63 @@ static void power_systemoff() static void power_wfi() { power_before(false /*systemoff*/); - power_in_wfi = 1; __WFI(); - power_in_wfi = 0; power_after(false /*systemoff*/); } -// TODO - It feels wrong to call pwr_mon_get_power_source() and the USB functions in the IRQ handler -void POWER_CLOCK_IRQHandler(void) -{ - if (NRF_POWER->EVENTS_USBDETECTED) { - NRF_POWER->EVENTS_USBDETECTED = 0; - power_source = pwr_mon_get_power_source(); - if (power_in_wfi) { - wake_from_usb = 1; - } - usb_pc_connected = true; - } - - if (NRF_POWER->EVENTS_USBREMOVED) { - NRF_POWER->EVENTS_USBREMOVED = 0; - power_source = pwr_mon_get_power_source(); - if (power_in_wfi) { - wake_from_usb = 1; - } - /* Reset USB on cable detach (VBUS falling edge) */ - USBD_Reset(); - usbd_reset_core(); - usb_pc_connected = false; - usb_state = USB_DISCONNECTED; - } -} +// // TODO - It feels wrong to call pwr_mon_get_power_source() and the USB functions in the IRQ handler +// void POWER_CLOCK_IRQHandler(void) +// { +// if (NRF_POWER->EVENTS_USBDETECTED) { +// NRF_POWER->EVENTS_USBDETECTED = 0; +// power_source = pwr_mon_get_power_source(); +// if (power_in_wfi) { +// wake_from_usb = 1; +// } +// usb_pc_connected = true; +// } + +// if (NRF_POWER->EVENTS_USBREMOVED) { +// NRF_POWER->EVENTS_USBREMOVED = 0; +// power_source = pwr_mon_get_power_source(); +// if (power_in_wfi) { +// wake_from_usb = 1; +// } +// /* Reset USB on cable detach (VBUS falling edge) */ +// USBD_Reset(); +// usbd_reset_core(); +// usb_pc_connected = false; +// usb_state = USB_DISCONNECTED; +// } +// } void GPIOTE_IRQHandler(void) { if (NRF_GPIOTE->EVENTS_PORT) { NRF_GPIOTE->EVENTS_PORT = 0; - if (power_in_wfi && (GPIO_REG(RESET_BUTTON)->LATCH & (1 << GPIO_IDX(RESET_BUTTON)))) { + + if (GPIO_REG(RESET_BUTTON)->LATCH & (1 << GPIO_IDX(RESET_BUTTON))) { + GPIO_REG(RESET_BUTTON)->LATCH &= ~(1 << GPIO_IDX(RESET_BUTTON)); + // Disable RESET_BUTTON edge events + gpio_cfg_input(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON), NRF_GPIO_PIN_NOPULL); wake_from_reset = 1; } + + if (GPIO_REG(PIN_VBUS_ABSENT)->LATCH & (1 << GPIO_IDX(PIN_VBUS_ABSENT))) { + GPIO_REG(PIN_VBUS_ABSENT)->LATCH &= ~(1 << GPIO_IDX(PIN_VBUS_ABSENT)); + + // Read VBUS_ABSENT (WAKE_ON_EDGE) pin for detecting if board is USB powered + if ( gpio_read(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT))) { + /* Reset USB on cable detach (VBUS falling edge) */ + USBD_Reset(); + usbd_reset_core(); + usb_pc_connected = false; + usb_state = USB_DISCONNECTED; + } else { + // Cable inserted + wake_from_usb = 1; + } + } } } diff --git a/source/board/microbitv2/nrf52820/pwr_mon.c b/source/board/microbitv2/nrf52820/pwr_mon.c index 7afab31f0..5a74f3329 100644 --- a/source/board/microbitv2/nrf52820/pwr_mon.c +++ b/source/board/microbitv2/nrf52820/pwr_mon.c @@ -23,121 +23,18 @@ #include "IO_Config.h" +#include "microbitv2_pins.h" #include "pwr_mon_adc.h" #include "pwr_mon.h" -// Define to enable debugging -//#define PWR_MON_DEBUG 1 -#ifdef PWR_MON_DEBUG - -#define MSC_DEBUG 1 -#include "daplink_debug.h" - -uint32_t bat_lo = 0xFFFFFFFF; -uint32_t bat_hi = 0; - -uint32_t vin_lo = 0xFFFFFFFF; -uint32_t vin_hi = 0; - -uint32_t nousb_vin = 0; -uint32_t nousb_bat = 0; - -uint32_t low_vin = 0; -uint32_t low_bat = 0; - -uint32_t dbg_bat[50]; -uint32_t dbg_cc[50]; -uint32_t dbg_count; - -uint32_t dbg_bat_nousb[50]; -uint32_t dbg_cc_nousb[50]; -uint32_t dbg_count_nousb; -#endif // PWR_MON_DEBUG - - -static void power_pins_init(); uint32_t pwr_mon_get_vbat_mv_imp(); static uint32_t pwr_mon_comp_mv(uint32_t psel, uint32_t vref, uint32_t *comps_count); -// Volatge monitor pins -// RUN_VBAT_SENSE Enable Battery Voltage monitor -// VBAT_SENSE Battery Voltage monitor -// VBUS_ABSENT High when USB power is not connected (WAKE_ON_EDGE) - -#define NRF52833_PIN_RUN_VBAT_SENSE NRF_GPIO_PIN_MAP(0, 31) -#define NRF52833_PIN_VBAT_SENSE NRF_GPIO_PIN_MAP(0, 30) -#define NRF52833_PIN_VBAT_SENSE_COMP 6 //COMP_PSEL_PSEL_AnalogInput6 -#define NRF52833_PIN_VIN_COMP 0 //Not available -#define NRF52833_PIN_VBUS_ABSENT NRF_GPIO_PIN_MAP(0, 11) - -#define NRF52820_PIN_RUN_VBAT_SENSE NRF_GPIO_PIN_MAP(0, 2) -#define NRF52820_PIN_VBAT_SENSE NRF_GPIO_PIN_MAP(0, 3) -#define NRF52820_PIN_VBAT_SENSE_COMP COMP_PSEL_PSEL_AnalogInput1 -#define NRF52820_PIN_VIN_COMP COMP_PSEL_PSEL_VddhDiv5 -#define NRF52820_PIN_VBUS_ABSENT NRF_GPIO_PIN_MAP(0, 7) - -#ifdef NRF528XX_DYNAMIC_PIN - -uint32_t pin_run_vbat_sense; -uint32_t pin_vbat_sense; -uint32_t pin_vbat_sense_comp; -uint32_t pin_vin_comp; -uint32_t pin_vbus_absent; - -COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52833(NRF52833_PIN_RUN_VBAT_SENSE)); -COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52833(NRF52833_PIN_VBAT_SENSE)); -COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52833(NRF52833_PIN_VBUS_ABSENT)); - -COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_PIN_RUN_VBAT_SENSE)); -COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_PIN_VBAT_SENSE)); -COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_PIN_VBUS_ABSENT)); -#else -COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_PIN_RUN_VBAT_SENSE)); -COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_PIN_VBAT_SENSE)); -COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_PIN_VBUS_ABSENT)); -#endif - -#ifdef NRF528XX_DYNAMIC_PIN -#define PIN_RUN_VBAT_SENSE pin_run_vbat_sense -#define PIN_VBAT_SENSE pin_vbat_sense -#define PIN_VBAT_SENSE_COMP pin_vbat_sense_comp -#define PIN_VIN_COMP pin_vin_comp -#define PIN_VBUS_ABSENT pin_vbus_absent -#else -#define PIN_RUN_VBAT_SENSE NRF52820_PIN_RUN_VBAT_SENSE -#define PIN_VBAT_SENSE NRF52820_PIN_VBAT_SENSE -#define PIN_VBAT_SENSE_COMP NRF52820_PIN_VBAT_SENSE_COMP -#define PIN_VIN_COMP NRF52820_PIN_VIN_COMP -#define PIN_VBUS_ABSENT NRF52820_PIN_VBUS_ABSENT -#endif - -static void power_pins_init() -{ -#ifdef NRF528XX_DYNAMIC_PIN - if (NRF_FICR->INFO.PART == 0x52833) { - // nRF52833 - pin_run_vbat_sense = NRF52833_PIN_RUN_VBAT_SENSE; - pin_vbat_sense = NRF52833_PIN_VBAT_SENSE; - pin_vbat_sense_comp = NRF52833_PIN_VBAT_SENSE_COMP; - pin_vin_comp = NRF52833_PIN_VIN_COMP; - pin_vbus_absent = NRF52833_PIN_VBUS_ABSENT; - } else { - // nRF52820 - pin_run_vbat_sense = NRF52820_PIN_RUN_VBAT_SENSE; - pin_vbat_sense = NRF52820_PIN_VBAT_SENSE; - pin_vbat_sense_comp = NRF52820_PIN_VBAT_SENSE_COMP; - pin_vin_comp = NRF52820_PIN_VIN_COMP; - pin_vbus_absent = NRF52820_PIN_VBUS_ABSENT; - } -#endif -} - - void pwr_mon_init(void) { - power_pins_init(); + microbitv2_pins_init(); // Configure VMON_BAT and RUN_VBAT_SENSE gpio_cfg_output(GPIO_REG(PIN_RUN_VBAT_SENSE), GPIO_IDX(PIN_RUN_VBAT_SENSE)); @@ -177,19 +74,6 @@ power_source_t pwr_mon_get_power_source(void) // } } -#ifdef PWR_MON_DEBUG - if (gpio_read(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT))) { - nousb_vin = vin_voltage_mv; - nousb_bat = bat_voltage_mv; - if (bat_voltage_mv < bat_min_voltage) { - low_vin = vin_voltage_mv; - low_bat = bat_voltage_mv; - } - } - debug_msg("PIN_VBUS_ABSENT %d usb_on %d\n", (int) PIN_VBUS_ABSENT, usb_on ? 1 : 0); - debug_msg("vin %d bat %d nousb vin %d bat %d low vin %d bat %d\n", (int) vin_voltage_mv, (int) bat_voltage_mv, (int) nousb_vin, (int) nousb_bat, (int) low_vin, (int) low_bat); -#endif // PWR_MON_DEBUG - return power_source; } @@ -199,36 +83,18 @@ uint32_t pwr_mon_get_vin_mv(void) if (NRF_FICR->INFO.PART == 0x52833) { // nRF52833 -#ifdef PWR_MON_DEBUG - debug_msg("pwr_mon_adc_vin\n"); -#endif // PWR_MON_DEBUG vin = pwr_mon_adc_vin(); } else { -#ifdef PWR_MON_DEBUG - debug_msg("pwr_mon_comp_mv(%d)\n", (int) PIN_VIN_COMP); -#endif // PWR_MON_DEBUG vin = pwr_mon_comp_mv(PIN_VIN_COMP, COMP_REFSEL_REFSEL_Int1V2, NULL); } -#ifdef PWR_MON_DEBUG - if ( gpio_read(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT))) { - if ( vin_lo > vin) vin_lo = vin; - if ( vin_hi < vin) vin_hi = vin; - } - debug_msg("vin %d low vin %d bat %d\n", (int) vin, (int) low_vin, (int) low_bat); -#endif // PWR_MON_DEBUG - return vin; } uint32_t pwr_mon_get_vbat_mv(void) { // CODAL needs a reply within 5ms - uint32_t bat = pwr_mon_get_vbat_mv_imp( 3000, 3300); - -#ifdef PWR_MON_DEBUG - debug_msg("bat %d\n", (int) bat); -#endif // PWR_MON_DEBUG + uint32_t bat = pwr_mon_get_vbat_mv_imp(3000, 3300); return bat; } @@ -245,12 +111,6 @@ uint32_t pwr_mon_get_vbat_mv_imp( uint32_t max_us, uint32_t max_mv) uint32_t bat; uint32_t comps_count = 0; -#ifdef PWR_MON_DEBUG - dbg_count = 0; - debug_msg("\n"); - debug_msg("pwr_mon_get_vbat_mv_imp(%d,%d) run %d comp %d\n", (int) max_us, (int) max_mv, (int) PIN_RUN_VBAT_SENSE, (int) PIN_VBAT_SENSE_COMP); -#endif // PWR_MON_DEBUG - // Enable voltage divider to take measurement gpio_write(GPIO_REG(PIN_RUN_VBAT_SENSE), GPIO_IDX(PIN_RUN_VBAT_SENSE), 1); @@ -259,14 +119,6 @@ uint32_t pwr_mon_get_vbat_mv_imp( uint32_t max_us, uint32_t max_mv) // Compensate for voltage divider bat = 4017 * bat / 1000; -#ifdef PWR_MON_DEBUG - if ( dbg_count < 50) { - dbg_bat[dbg_count] = bat; - dbg_cc[dbg_count] = comps_count; - dbg_count++; - } -#endif // PWR_MON_DEBUG - if ( comps_count >= max_comps) { break; } @@ -279,33 +131,6 @@ uint32_t pwr_mon_get_vbat_mv_imp( uint32_t max_us, uint32_t max_mv) // Disable voltage divider gpio_write(GPIO_REG(PIN_RUN_VBAT_SENSE), GPIO_IDX(PIN_RUN_VBAT_SENSE), 0); -#ifdef PWR_MON_DEBUG - if ( gpio_read(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT))) { - for (int i = 0; i < dbg_count; i++) { - dbg_bat_nousb[i] = dbg_bat[i]; - dbg_cc_nousb[i] = dbg_cc[i]; - } - dbg_count_nousb = dbg_count; - } - - if ( gpio_read(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT))) { - if ( bat_lo > bat) bat_lo = bat; - if ( bat_hi < bat) bat_hi = bat; - } - - // int num = dbg_count_nousb >= 50 ? 50 : dbg_count_nousb; - // for (int i = 0; i < num; i++) { - // debug_msg("%d,%d\n", (int) dbg_cc_nousb[dbg_count_nousb - num + i], (int) dbg_bat_nousb[dbg_count_nousb - num + i]); - // } - - // int numnum = dbg_count >= 50 ? 50 : dbg_count; - // for (int i = 0; i < numnum; i++) { - // debug_msg("%d,%d\n", (int) dbg_cc[dbg_count - numnum + i], (int) dbg_bat[dbg_count - numnum + i]); - // } - - //debug_msg("vin lo %d hi %d bat lo %d hi %d\n", (int) vin_lo, (int) vin_hi, (int) bat_lo, (int) bat_hi); -#endif // PWR_MON_DEBUG - return bat; } From 07ed49caf4a6a987c880447c04ed97c8e1201e14 Mon Sep 17 00:00:00 2001 From: Martin Williams Date: Mon, 8 Nov 2021 17:15:15 +0000 Subject: [PATCH 482/617] Fix PWM and remove power debug code --- source/board/microbitv2/i2c_commands.c | 4 ++ source/board/microbitv2/nrf52820/power.c | 31 --------- source/board/microbitv2/nrf52820/pwm.c | 89 ++++++++++++++---------- 3 files changed, 56 insertions(+), 68 deletions(-) diff --git a/source/board/microbitv2/i2c_commands.c b/source/board/microbitv2/i2c_commands.c index 9eb019024..1b27addaf 100644 --- a/source/board/microbitv2/i2c_commands.c +++ b/source/board/microbitv2/i2c_commands.c @@ -63,6 +63,10 @@ static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { i2cCommand_t i2cResponse = {0}; bool assert_interrupt = true; + if (size < 1) { + return; + } + switch (pI2cCommand->cmdId) { case gReadRequest_c: i2cResponse.cmdId = gReadResponse_c; diff --git a/source/board/microbitv2/nrf52820/power.c b/source/board/microbitv2/nrf52820/power.c index ca81b0400..276b378bc 100644 --- a/source/board/microbitv2/nrf52820/power.c +++ b/source/board/microbitv2/nrf52820/power.c @@ -40,7 +40,6 @@ static void power_after(); static void power_systemoff(); static void power_wfi(); -void POWER_CLOCK_IRQHandler(void); void GPIOTE_IRQHandler(void); @@ -73,10 +72,6 @@ void power_init() NRF_GPIOTE->INTENSET = power_gpiote_intenset | ( GPIOTE_INTENSET_PORT_Set << GPIOTE_INTENSET_PORT_Pos); NVIC_EnableIRQ(GPIOTE_IRQn); - - // // Enable NRF_POWER interrupt for USB removed/detected - // NRF_POWER->INTENSET = POWER_INTENSET_USBREMOVED_Msk | POWER_INTENSET_USBDETECTED_Msk; - // NVIC_EnableIRQ(POWER_CLOCK_IRQn); } void power_down() @@ -170,32 +165,6 @@ static void power_wfi() } -// // TODO - It feels wrong to call pwr_mon_get_power_source() and the USB functions in the IRQ handler -// void POWER_CLOCK_IRQHandler(void) -// { -// if (NRF_POWER->EVENTS_USBDETECTED) { -// NRF_POWER->EVENTS_USBDETECTED = 0; -// power_source = pwr_mon_get_power_source(); -// if (power_in_wfi) { -// wake_from_usb = 1; -// } -// usb_pc_connected = true; -// } - -// if (NRF_POWER->EVENTS_USBREMOVED) { -// NRF_POWER->EVENTS_USBREMOVED = 0; -// power_source = pwr_mon_get_power_source(); -// if (power_in_wfi) { -// wake_from_usb = 1; -// } -// /* Reset USB on cable detach (VBUS falling edge) */ -// USBD_Reset(); -// usbd_reset_core(); -// usb_pc_connected = false; -// usb_state = USB_DISCONNECTED; -// } -// } - void GPIOTE_IRQHandler(void) { if (NRF_GPIOTE->EVENTS_PORT) { diff --git a/source/board/microbitv2/nrf52820/pwm.c b/source/board/microbitv2/nrf52820/pwm.c index 2d97397e8..782e342ac 100644 --- a/source/board/microbitv2/nrf52820/pwm.c +++ b/source/board/microbitv2/nrf52820/pwm.c @@ -51,10 +51,11 @@ static void pwm_mark255(uint8_t duty); #define PWM_COUNT_MAX 2550 #define PWM_DUTY_TO_COUNT(duty) ((uint32_t)(duty) * 10) +static uint8_t pwm_duty = 0; + void pwm_init() { - pwm_configure(); } void pwm_init_pins() @@ -75,54 +76,68 @@ void pwm_deinit_pins() void pwm_set_dutycycle(uint8_t duty) { - if (duty == 0) { - pwm_stop(); - gpio_clear(GPIO_REG(LED_PWR), GPIO_IDX(LED_PWR)); - } else if (duty == 255) { - pwm_stop(); - gpio_set(GPIO_REG(LED_PWR), GPIO_IDX(LED_PWR)); - } else { - PWM_TIMER->CC[PWM_CC_MARK] = PWM_DUTY_TO_COUNT(duty); - pwm_start(); + if (pwm_duty != duty) { + if (duty == 0) { + pwm_stop(); + gpio_clear(GPIO_REG(LED_PWR), GPIO_IDX(LED_PWR)); + } else if (duty == 255) { + pwm_stop(); + gpio_set(GPIO_REG(LED_PWR), GPIO_IDX(LED_PWR)); + } else { + pwm_configure(); + PWM_TIMER->CC[PWM_CC_MARK] = PWM_DUTY_TO_COUNT(duty); + pwm_start(); + } + pwm_duty = duty; } } static void pwm_stop() { - NVIC_DisableIRQ(PWM_IRQ); - NRF_PPI->CHENCLR = NRF_PPI->CHENSET; - PWM_TIMER->TASKS_STOP = 1; - //https://infocenter.nordicsemi.com/topic/errata_nRF52820_Rev3/ERR/nRF52820/Rev3/latest/anomaly_820_78.html - PWM_TIMER->TASKS_SHUTDOWN = 1; + if (pwm_duty != 0 && pwm_duty != 255) { + NVIC_DisableIRQ(PWM_IRQ); + NRF_PPI->CHENCLR = NRF_PPI->CHENSET; + PWM_TIMER->TASKS_STOP = 1; + //https://infocenter.nordicsemi.com/topic/errata_nRF52820_Rev3/ERR/nRF52820/Rev3/latest/anomaly_820_78.html + PWM_TIMER->TASKS_SHUTDOWN = 1; + NRF_GPIOTE->CONFIG[PWM_GPIOTE_CH] = GPIOTE_CONFIG_MODE_Disabled << GPIOTE_CONFIG_MODE_Pos; + NRF_PPI->CH[PWM_PPI_CLR].EEP = 0; + NRF_PPI->CH[PWM_PPI_CLR].TEP = 0; + NRF_PPI->CH[PWM_PPI_SET].EEP = 0; + NRF_PPI->CH[PWM_PPI_SET].TEP = 0; + } } static void pwm_start() { - NVIC_EnableIRQ(PWM_IRQ); - NRF_PPI->CHENSET = (1 << PWM_PPI_CLR) | (1 << PWM_PPI_SET); - PWM_TIMER->TASKS_START = 1; + if (pwm_duty == 0 || pwm_duty == 255) { + NVIC_EnableIRQ(PWM_IRQ); + NRF_PPI->CHENSET = (1 << PWM_PPI_CLR) | (1 << PWM_PPI_SET); + PWM_TIMER->TASKS_CLEAR = 1; + PWM_TIMER->TASKS_START = 1; + } } static void pwm_configure() { - pwm_stop(); - - PWM_TIMER->BITMODE = TIMER_BITMODE_BITMODE_32Bit << TIMER_BITMODE_BITMODE_Pos; - PWM_TIMER->PRESCALER = PWM_PRESCALER; - PWM_TIMER->SHORTS = TIMER_SHORTS_COMPARE0_CLEAR_Msk << PWM_CC_END; - PWM_TIMER->MODE = TIMER_MODE_MODE_Timer << TIMER_MODE_MODE_Pos; - PWM_TIMER->CC[PWM_CC_MARK] = 1; - PWM_TIMER->CC[PWM_CC_END] = PWM_COUNT_MAX; - - NRF_GPIOTE->CONFIG[PWM_GPIOTE_CH] = LED_PWR << GPIOTE_CONFIG_PSEL_Pos | - GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos | - GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos | - GPIOTE_CONFIG_OUTINIT_High << GPIOTE_CONFIG_OUTINIT_Pos; - - NRF_PPI->CH[PWM_PPI_CLR].EEP = (uint32_t)&PWM_TIMER->EVENTS_COMPARE[PWM_CC_MARK]; - NRF_PPI->CH[PWM_PPI_CLR].TEP = (uint32_t)&NRF_GPIOTE->TASKS_CLR[PWM_GPIOTE_CH]; - - NRF_PPI->CH[PWM_PPI_SET].EEP = (uint32_t)&PWM_TIMER->EVENTS_COMPARE[PWM_CC_END]; - NRF_PPI->CH[PWM_PPI_SET].TEP = (uint32_t)&NRF_GPIOTE->TASKS_SET[PWM_GPIOTE_CH]; + if (pwm_duty == 0 || pwm_duty == 255) { + PWM_TIMER->BITMODE = TIMER_BITMODE_BITMODE_32Bit << TIMER_BITMODE_BITMODE_Pos; + PWM_TIMER->PRESCALER = PWM_PRESCALER; + PWM_TIMER->SHORTS = TIMER_SHORTS_COMPARE0_CLEAR_Msk << PWM_CC_END; + PWM_TIMER->MODE = TIMER_MODE_MODE_Timer << TIMER_MODE_MODE_Pos; + PWM_TIMER->CC[PWM_CC_MARK] = 1; + PWM_TIMER->CC[PWM_CC_END] = PWM_COUNT_MAX; + + NRF_GPIOTE->CONFIG[PWM_GPIOTE_CH] = LED_PWR << GPIOTE_CONFIG_PSEL_Pos | + GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos | + GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos | + GPIOTE_CONFIG_OUTINIT_High << GPIOTE_CONFIG_OUTINIT_Pos; + + NRF_PPI->CH[PWM_PPI_CLR].EEP = (uint32_t)&PWM_TIMER->EVENTS_COMPARE[PWM_CC_MARK]; + NRF_PPI->CH[PWM_PPI_CLR].TEP = (uint32_t)&NRF_GPIOTE->TASKS_CLR[PWM_GPIOTE_CH]; + + NRF_PPI->CH[PWM_PPI_SET].EEP = (uint32_t)&PWM_TIMER->EVENTS_COMPARE[PWM_CC_END]; + NRF_PPI->CH[PWM_PPI_SET].TEP = (uint32_t)&NRF_GPIOTE->TASKS_SET[PWM_GPIOTE_CH]; + } } From 6efa98e6bf93b46cb259c50a212caff3690793c0 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Mon, 8 Nov 2021 22:41:34 +0000 Subject: [PATCH 483/617] nrf52820_microbit: Add fileEncWindowStart and fileEncWindowEnd to i2c_cmds_reset_storate_config(). --- source/board/microbitv2/i2c_commands.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/source/board/microbitv2/i2c_commands.c b/source/board/microbitv2/i2c_commands.c index 1b27addaf..7292a0a3a 100644 --- a/source/board/microbitv2/i2c_commands.c +++ b/source/board/microbitv2/i2c_commands.c @@ -515,5 +515,7 @@ void i2c_cmds_reset_storate_config() { .fileName = STORAGE_CFG_FILENAME, .fileSize = STORAGE_CFG_FILESIZE, .fileVisible = STORAGE_CFG_FILEVISIBLE, + .fileEncWindowStart = 0, + .fileEncWindowEnd = 0, }; } From 2c6f6e08c19a74415c9030ddd7e613f884398d5e Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 8 Nov 2021 23:05:23 -0600 Subject: [PATCH 484/617] Fix a few typos in lpc55xx/uart.c (#888) Some spotted by @tarokajya in #887 --- source/hic_hal/nxp/lpc55xx/uart.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/source/hic_hal/nxp/lpc55xx/uart.c b/source/hic_hal/nxp/lpc55xx/uart.c index f69648d1d..b8b45c6d9 100644 --- a/source/hic_hal/nxp/lpc55xx/uart.c +++ b/source/hic_hal/nxp/lpc55xx/uart.c @@ -64,8 +64,8 @@ int32_t uart_initialize(void) { clear_buffers(); cb_buf.tx_size = 0; - Driver_USART0.Initialize(uart_handler); - Driver_USART0.PowerControl(ARM_POWER_FULL); + USART_INSTANCE.Initialize(uart_handler); + USART_INSTANCE.PowerControl(ARM_POWER_FULL); return 1; } @@ -74,8 +74,8 @@ int32_t uart_uninitialize(void) { USART_INSTANCE.Control(ARM_USART_CONTROL_RX, 0); USART_INSTANCE.Control(ARM_USART_ABORT_RECEIVE, 0U); - Driver_USART0.PowerControl(ARM_POWER_OFF); - Driver_USART0.Uninitialize(); + USART_INSTANCE.PowerControl(ARM_POWER_OFF); + USART_INSTANCE.Uninitialize(); clear_buffers(); cb_buf.tx_size = 0; @@ -99,7 +99,7 @@ int32_t uart_set_configuration(UART_Configuration *config) switch (config->DataBits) { case UART_DATA_BITS_5: - control |= UART_DATA_BITS_5; + control |= ARM_USART_DATA_BITS_5; break; case UART_DATA_BITS_6: @@ -107,7 +107,7 @@ int32_t uart_set_configuration(UART_Configuration *config) break; case UART_DATA_BITS_7: - control |= ARM_USART_DATA_BITS_6; + control |= ARM_USART_DATA_BITS_7; break; case UART_DATA_BITS_8: /* fallthrough */ @@ -250,4 +250,3 @@ void uart_handler(uint32_t event) { uart_start_tx_transfer(); } } - From 465003f16ac6d068731e53acd75ffd8174ed475f Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 9 Nov 2021 00:54:22 -0600 Subject: [PATCH 485/617] lpc55xx_hic: change memory map to support LPC552x models (#895) --- docs/hic/lpc55xx.md | 8 ++++---- source/hic_hal/nxp/lpc55xx/daplink_addr.h | 21 +++++++++------------ 2 files changed, 13 insertions(+), 16 deletions(-) diff --git a/docs/hic/lpc55xx.md b/docs/hic/lpc55xx.md index 7fc951021..046a98ecf 100644 --- a/docs/hic/lpc55xx.md +++ b/docs/hic/lpc55xx.md @@ -8,19 +8,19 @@ Based on LPC55S69JBD64 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet - HTQFP64 packaging In order to support other MCUs from the LPC5500 family, the HIC limits usage -to one core, 320 KB Flash and 256 KB RAM. +to one core, 256 KB Flash and 96 KB RAM. ## Memory Map | Region | Size | Start | End | |----------|--------|-------------|-------------| -| Flash | 320 KB | 0x0000_0000 | 0x0005_1000 | -| SRAM | 256 KB | 0x2000_0000 | 0x2004_0000 | +| Flash | 256 KB | 0x0000_0000 | 0x0004_0000 | +| SRAM | 96 KB | 0x2000_0000 | 0x2004_0000 | | USB RAM | 16 KB | 0x4010_0000 | 0x4010_4000 | Bootloader size is 64 KB -## DAPLink default pin assignment +## DAPLink default pin assignment Reference design is based on [MCU-Link](https://www.nxp.com/design/development-boards/lpcxpresso-boards/mcu-link-debug-probe:MCU-LINK). diff --git a/source/hic_hal/nxp/lpc55xx/daplink_addr.h b/source/hic_hal/nxp/lpc55xx/daplink_addr.h index 8b17669da..737fdc823 100644 --- a/source/hic_hal/nxp/lpc55xx/daplink_addr.h +++ b/source/hic_hal/nxp/lpc55xx/daplink_addr.h @@ -22,8 +22,8 @@ // Flash layout: // // [ 0x0000_0000 - 0x0000_FFFF ]: 64 kB - bootloader -// [ 0x0001_0000 - 0x0004_FFFF ]: 256 kB - interface -// [ 0x0005_0000 - 0x0005_0FFF ]: 4 kB - persistent config (cfgrom) +// [ 0x0001_0000 - 0x0003_FBFF ]: 191 kB - interface +// [ 0x0003_FC00 - 0x0003_FFFF ]: 1 kB - persistent config (cfgrom) // // Notes: // 1. The interface does not extend to the end of flash because that makes the binary @@ -34,31 +34,28 @@ /* Device sizes */ #define DAPLINK_ROM_START 0x00000000 // NS alias -#define DAPLINK_ROM_SIZE 0x00051000 // 64 kB BL + 256 kB IF + 4 kB config +#define DAPLINK_ROM_SIZE 0x00040000 // 64 kB BL + 191 kB IF + 1 kB config #define DAPLINK_RAM_START 0x20000000 // NS alias -#define DAPLINK_RAM_SIZE 0x00040000 // SRAM 0-3 +#define DAPLINK_RAM_SIZE 0x00018000 // SRAM 0-1 /* ROM sizes */ #define DAPLINK_ROM_BL_START 0x00000000 #define DAPLINK_ROM_BL_SIZE 0x00010000 // 64 kB bootloader -#define DAPLINK_ROM_CONFIG_ADMIN_START 0x00010000 -#define DAPLINK_ROM_CONFIG_ADMIN_SIZE 0x00000000 - #define DAPLINK_ROM_IF_START 0x00010000 -#define DAPLINK_ROM_IF_SIZE 0x00040000 +#define DAPLINK_ROM_IF_SIZE 0x0002FC00 // 191 kB interface -#define DAPLINK_ROM_CONFIG_USER_START 0x00050000 -#define DAPLINK_ROM_CONFIG_USER_SIZE 0x00001000 +#define DAPLINK_ROM_CONFIG_USER_START 0x0003FC00 +#define DAPLINK_ROM_CONFIG_USER_SIZE 0x00000400 // 1 kB config /* RAM sizes */ #define DAPLINK_RAM_APP_START 0x20000000 -#define DAPLINK_RAM_APP_SIZE 0x0003FF00 +#define DAPLINK_RAM_APP_SIZE 0x00017F00 -#define DAPLINK_RAM_SHARED_START 0x2003FF00 +#define DAPLINK_RAM_SHARED_START 0x20017F00 #define DAPLINK_RAM_SHARED_SIZE 0x00000100 /* Flash Programming Info */ From dcc39aa0f26a54cd97e26c21dad767737370b598 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Wed, 10 Nov 2021 10:58:07 +0000 Subject: [PATCH 486/617] nrf52820_hic: Update nrf52_erratas.h to be applied to nRF52833 on nRF52820 builds. The micro:bit builds are configured for nRF52820, but will be run in nRF52833 MCUs as well. This file checked UICR register reserved for Nordic, which are different between the two MCUs, so we need to make sure the values for nRF52833 are also check in nRF52820 builds. --- .../nordic/nrf52820/cmsis/nrf52_erratas.h | 132 +++++++++++++----- 1 file changed, 99 insertions(+), 33 deletions(-) diff --git a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_erratas.h b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_erratas.h index e05d5678b..d9e9a7ff0 100644 --- a/source/hic_hal/nordic/nrf52820/cmsis/nrf52_erratas.h +++ b/source/hic_hal/nordic/nrf52820/cmsis/nrf52_erratas.h @@ -1031,7 +1031,9 @@ static bool nrf52_errata_20(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -1865,7 +1867,9 @@ static bool nrf52_errata_36(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -2717,7 +2721,9 @@ static bool nrf52_errata_55(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -3189,7 +3195,9 @@ static bool nrf52_errata_66(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -4018,7 +4026,9 @@ static bool nrf52_errata_78(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -4594,7 +4604,9 @@ static bool nrf52_errata_87(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -6568,7 +6580,9 @@ static bool nrf52_errata_136(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -8034,7 +8048,9 @@ static bool nrf52_errata_170(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -8268,7 +8284,9 @@ static bool nrf52_errata_173(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -8480,7 +8498,9 @@ static bool nrf52_errata_176(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -9007,7 +9027,9 @@ static bool nrf52_errata_183(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -9123,7 +9145,9 @@ static bool nrf52_errata_184(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -9277,7 +9301,9 @@ static bool nrf52_errata_187(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -9407,7 +9433,9 @@ static bool nrf52_errata_190(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -9721,7 +9749,9 @@ static bool nrf52_errata_194(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -9889,7 +9919,9 @@ static bool nrf52_errata_196(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -10553,7 +10585,9 @@ static bool nrf52_errata_210(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -10661,7 +10695,9 @@ static bool nrf52_errata_211(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -10803,7 +10839,9 @@ static bool nrf52_errata_212(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -11267,7 +11305,9 @@ static bool nrf52_errata_218(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -11409,7 +11449,9 @@ static bool nrf52_errata_219(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -11551,7 +11593,9 @@ static bool nrf52_errata_223(void) uint32_t var1 = *(uint32_t *)0x10000130ul; uint32_t var2 = *(uint32_t *)0x10000134ul; #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -11611,7 +11655,9 @@ static bool nrf52_errata_225(void) uint32_t var1 = *(uint32_t *)0x10000130ul; uint32_t var2 = *(uint32_t *)0x10000134ul; #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -11713,7 +11759,9 @@ static bool nrf52_errata_228(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -11945,7 +11993,9 @@ static bool nrf52_errata_233(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -12047,7 +12097,9 @@ static bool nrf52_errata_236(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -12161,7 +12213,9 @@ static bool nrf52_errata_237(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -12347,7 +12401,9 @@ static bool nrf52_errata_243(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -12535,7 +12591,9 @@ static bool nrf52_errata_245(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -12663,7 +12721,9 @@ static bool nrf52_errata_246(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -12789,7 +12849,9 @@ static bool nrf52_errata_248(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -12910,7 +12972,9 @@ static bool nrf52_errata_249(void) } } #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) @@ -12970,7 +13034,9 @@ static bool nrf52_errata_250(void) uint32_t var1 = *(uint32_t *)0x10000130ul; uint32_t var2 = *(uint32_t *)0x10000134ul; #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + // DAPLink change: Ensure the nRF52833 check is performed in nRF52820 builds as well + // #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #if defined (NRF52833_XXAA) || defined (NRF52820_XXAA) if (var1 == 0x0D) { switch(var2) From bf6237ed08d127e714bec2a2c7088309f0e758cc Mon Sep 17 00:00:00 2001 From: Martin Williams Date: Wed, 10 Nov 2021 13:29:16 +0000 Subject: [PATCH 487/617] nrf52820_microbit: HID LED initially off (#9) --- source/board/microbitv2/microbitv2.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index af3aec292..35bcd91a3 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -203,6 +203,11 @@ static inline uint8_t get_led_gamma(uint8_t brightness) { // Called in main_task() to init before USB and files are configured static void prerun_board_config(void) { + // HID_LED_DEF is on so the resting state of the orange LED after flashing is on + // but turn it off here so it's initially off, then stays off when on battery, + // and comes on only when USB enumerates + gpio_set_hid_led(GPIO_LED_OFF); + mb_version_t board_version = read_brd_rev_id(); set_board_id(board_version); From edf3af8c392097b27c2477895b4c45c6d72fd48b Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Wed, 10 Nov 2021 13:31:08 +0000 Subject: [PATCH 488/617] nrf52820_microbit: Set the power red LED off by default. This is specially important for the bootloader, as we only want the red LED to be ON in the interface. The pwm driver turns the red LED ON during startup in the IF. --- source/hic_hal/nordic/nrf52820/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/hic_hal/nordic/nrf52820/gpio.c b/source/hic_hal/nordic/nrf52820/gpio.c index 88b500893..dc348be7c 100644 --- a/source/hic_hal/nordic/nrf52820/gpio.c +++ b/source/hic_hal/nordic/nrf52820/gpio.c @@ -33,7 +33,7 @@ void gpio_init(void) { #ifdef LED_PWR gpio_cfg_output(GPIO_REG(LED_PWR), GPIO_IDX(LED_PWR)); - gpio_write(GPIO_REG(LED_PWR), GPIO_IDX(LED_PWR), GPIO_LED_STATE(1)); + gpio_write(GPIO_REG(LED_PWR), GPIO_IDX(LED_PWR), GPIO_LED_STATE(0)); #endif #ifdef LED_CONNECTED gpio_cfg_output(GPIO_REG(LED_CONNECTED), GPIO_IDX(LED_CONNECTED)); From 6813d5aa6b9414e47c9294f9acda9c27a5672406 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Wed, 10 Nov 2021 22:26:38 +0000 Subject: [PATCH 489/617] nrf52820_microbit: Execute the I2C callbacks in the main task, not the interrupt. --- source/board/microbitv2/i2c.h | 18 ++--- source/board/microbitv2/kl27z/i2c.c | 37 ++++++--- source/board/microbitv2/microbitv2.c | 6 +- source/board/microbitv2/nrf52820/i2c.c | 101 ++++++++++++++++++++----- 4 files changed, 118 insertions(+), 44 deletions(-) diff --git a/source/board/microbitv2/i2c.h b/source/board/microbitv2/i2c.h index 50251e94d..1f9df9392 100644 --- a/source/board/microbitv2/i2c.h +++ b/source/board/microbitv2/i2c.h @@ -26,15 +26,8 @@ #include #include -/*! i2c Write Callback prototype */ -typedef void (*i2cWriteCallback_t) -( - uint8_t* pData, - uint8_t size -); - -/*! i2c Read Callback prototype */ -typedef void (*i2cReadCallback_t) +/*! i2c Read/Write Callback prototype */ +typedef void (*i2cCallback_t) ( uint8_t* pData, uint8_t size @@ -50,10 +43,11 @@ typedef enum { void i2c_initialize(void); void i2c_deinitialize(void); -i2c_status_t i2c_registerWriteCallback(i2cWriteCallback_t writeCallback, uint8_t slaveAddress); -i2c_status_t i2c_registerReadCallback(i2cReadCallback_t readCallback, uint8_t slaveAddress); -void i2c_clearBuffer(void); +i2c_status_t i2c_registerWriteCallback(i2cCallback_t writeCallback, uint8_t slaveAddress); +i2c_status_t i2c_registerReadCallback(i2cCallback_t readCallback, uint8_t slaveAddress); +void i2c_clearBuffers(void); void i2c_fillBuffer(uint8_t* data, uint32_t position, uint32_t size); bool i2c_isBusy(void); +bool i2c_canSleep(void); #endif /* I2C_H_ */ diff --git a/source/board/microbitv2/kl27z/i2c.c b/source/board/microbitv2/kl27z/i2c.c index a11c0f357..845211ff9 100644 --- a/source/board/microbitv2/kl27z/i2c.c +++ b/source/board/microbitv2/kl27z/i2c.c @@ -46,13 +46,16 @@ static const uint8_t g_slave_busy_error_buff[] = {gErrorResponse_c, gErrorBusy_c static uint8_t g_slave_TX_buff_ready = 0; static uint8_t g_slave_busy = 0; -static i2cWriteCallback_t pfWriteCommsCallback = NULL; -static i2cReadCallback_t pfReadCommsCallback = NULL; -static i2cWriteCallback_t pfWriteFlashCallback = NULL; -static i2cReadCallback_t pfReadFlashCallback = NULL; +static i2cCallback_t pfWriteCommsCallback = NULL; +static i2cCallback_t pfReadCommsCallback = NULL; +static i2cCallback_t pfWriteFlashCallback = NULL; +static i2cCallback_t pfReadFlashCallback = NULL; extern uint8_t i2c_wake_timeout; -extern bool i2c_allow_sleep; +static bool i2c_allow_sleep; + +static void i2c_clearTxBuffer(void); + static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData) { i2cCommand_t i2cResponse = {0}; @@ -108,7 +111,7 @@ static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void // Check flag set in kI2C_SlaveReceiveEvent // Ignore NOP cmd in I2C Write - if (!(g_SlaveRxFlag && g_slave_RX_buff[0] == 0x00)) { + if (!(g_SlaveRxFlag && g_slave_RX_buff[0] == gNopCmd_c)) { // Only process events if the busy error was not read if (!g_slave_busy) { main_board_event(); @@ -134,7 +137,7 @@ static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void // Hook function executed in the main task void board_custom_event() { if (g_SlaveRxFlag) { - i2c_clearBuffer(); + i2c_clearTxBuffer(); if (pfWriteCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { pfWriteCommsCallback(&g_slave_RX_buff[0], transferredCount); } @@ -184,6 +187,8 @@ void i2c_initialize() { i2c_init_pins(); + i2c_clearBuffers(); + I2C_SlaveGetDefaultConfig(&slaveConfig); slaveConfig.addressingMode = kI2C_RangeMatch; @@ -205,7 +210,7 @@ void i2c_deinitialize(void) { return ; } -i2c_status_t i2c_registerWriteCallback(i2cWriteCallback_t writeCallback, uint8_t slaveAddress) +i2c_status_t i2c_registerWriteCallback(i2cCallback_t writeCallback, uint8_t slaveAddress) { i2c_status_t status = I2C_STATUS_SUCCESS; @@ -226,7 +231,7 @@ i2c_status_t i2c_registerWriteCallback(i2cWriteCallback_t writeCallback, uint8_t return status; } -i2c_status_t i2c_registerReadCallback(i2cReadCallback_t readCallback, uint8_t slaveAddress) +i2c_status_t i2c_registerReadCallback(i2cCallback_t readCallback, uint8_t slaveAddress) { i2c_status_t status = I2C_STATUS_SUCCESS; @@ -247,7 +252,14 @@ i2c_status_t i2c_registerReadCallback(i2cReadCallback_t readCallback, uint8_t sl return status; } -void i2c_clearBuffer (void) { +void i2c_clearBuffers(void) +{ + memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); + memset(&g_slave_RX_buff, 0, sizeof(g_slave_RX_buff)); +} + +void i2c_clearTxBuffer(void) +{ memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); } @@ -266,3 +278,8 @@ bool i2c_isBusy() { return g_s_handle.isBusy; } + +bool i2c_canSleep() +{ + return i2c_allow_sleep; +} diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 35bcd91a3..8ae801f8a 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -75,7 +75,6 @@ volatile uint8_t wake_from_reset = 0; volatile uint8_t wake_from_usb = 0; volatile bool usb_pc_connected = false; uint8_t i2c_wake_timeout = 0; -bool i2c_allow_sleep = true; power_source_t power_source; microbit_if_power_mode_t interface_power_mode = MB_POWER_DOWN; bool power_led_sleep_state_on = PWR_LED_SLEEP_STATE_DEFAULT; @@ -84,7 +83,6 @@ main_shutdown_state_t main_shutdown_state = MAIN_SHUTDOWN_WAITING; bool do_remount = false; extern main_usb_connect_t usb_state; -extern bool go_to_sleep; extern void main_powerdown_event(void); @@ -324,7 +322,7 @@ void board_30ms_hook() // Enter light sleep if USB is not enumerated and main_shutdown_state is idle if (usb_state == USB_DISCONNECTED && !usb_pc_connected && main_shutdown_state == MAIN_SHUTDOWN_WAITING - && automatic_sleep_on == true && i2c_isBusy() == false && i2c_wake_timeout == 0 && i2c_allow_sleep) { + && automatic_sleep_on == true && i2c_isBusy() == false && i2c_wake_timeout == 0 && i2c_canSleep()) { interface_power_mode = MB_POWER_SLEEP; main_shutdown_state = MAIN_SHUTDOWN_REQUESTED; } @@ -491,7 +489,7 @@ void board_vfs_stream_closed_hook() main_shutdown_state = MAIN_SHUTDOWN_WAITING; // Clear any pending I2C response - i2c_clearBuffer(); + i2c_clearBuffers(); // Release COMBINED_SENSOR_INT gpio_disable_combined_int(); diff --git a/source/board/microbitv2/nrf52820/i2c.c b/source/board/microbitv2/nrf52820/i2c.c index 5fa74a695..0af49440e 100644 --- a/source/board/microbitv2/nrf52820/i2c.c +++ b/source/board/microbitv2/nrf52820/i2c.c @@ -21,6 +21,8 @@ #include +#include "main_interface.h" + #include "i2c.h" #include "i2c_commands.h" @@ -44,10 +46,60 @@ static ARM_DRIVER_I2C *I2Cdrv = &Driver_I2C0; static uint8_t g_slave_TX_buff[I2C_DATA_LENGTH] = { 0 }; static uint8_t g_slave_RX_buff[I2C_DATA_LENGTH] = { 0 }; -static i2cWriteCallback_t pfWriteCommsCallback = NULL; -static i2cReadCallback_t pfReadCommsCallback = NULL; -static i2cWriteCallback_t pfWriteFlashCallback = NULL; -static i2cReadCallback_t pfReadFlashCallback = NULL; +static i2cCallback_t pfWriteCommsCallback = NULL; +static i2cCallback_t pfReadCommsCallback = NULL; +static i2cCallback_t pfWriteFlashCallback = NULL; +static i2cCallback_t pfReadFlashCallback = NULL; +typedef struct callbackToExecute_s { + i2cCallback_t pfCallback; + uint8_t* pData; + uint8_t size; +} callbackToExecute_t; +static callbackToExecute_t callbackToExecute = { + .pfCallback = NULL, + .pData = NULL, + .size = 0, +}; + +static bool scheduleClearTxBuffer = false; + +static bool i2c_allow_sleep = true; + + +static i2c_status_t scheduleCallback(i2cCallback_t callback, uint8_t* pData, uint8_t size) +{ + if (callbackToExecute.pfCallback != NULL) { + return I2C_STATUS_FAIL; + } + callbackToExecute.pfCallback = callback; + callbackToExecute.pData = pData; + callbackToExecute.size = size; + + // Raise event so that `board_custom_event()` gets called in the main task + main_board_event(); + + return I2C_STATUS_SUCCESS; +} + +// Hook function executed in the main task +void board_custom_event() +{ + if (scheduleClearTxBuffer) { + debug_i2c_data((uint8_t *)"[clTxBf]\n", 9); + memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); + scheduleClearTxBuffer = false; + } + + if (callbackToExecute.pfCallback != NULL) { + debug_i2c_data((uint8_t *)"[clbk]\n", 7); + callbackToExecute.pfCallback(callbackToExecute.pData, callbackToExecute.size); + } + callbackToExecute.pfCallback = NULL; + callbackToExecute.pData = NULL; + callbackToExecute.size = 0; + + i2c_allow_sleep = true; +} static void I2C_SignalEvent(uint32_t event) { static uint32_t prev_event = 0; @@ -64,22 +116,30 @@ static void I2C_SignalEvent(uint32_t event) { if (event & ARM_I2C_EVENT_TRANSFER_DONE) { debug_i2c_data((uint8_t *)"d ", 1); - if (prev_event & ARM_I2C_EVENT_SLAVE_RECEIVE) { - debug_i2c_printf("[rx] %02x %02x ", g_slave_RX_buff[0], g_slave_RX_buff[1]); + i2c_allow_sleep = false; - if (event & EXTENSION_I2C_EVENT_SLAVE_ADDR_0) { - pfWriteCommsCallback(&g_slave_RX_buff[0], I2Cdrv->GetDataCount()); - } else if (event & EXTENSION_I2C_EVENT_SLAVE_ADDR_1) { - pfWriteFlashCallback(&g_slave_RX_buff[0], I2Cdrv->GetDataCount()); + if (prev_event & ARM_I2C_EVENT_SLAVE_RECEIVE) { + int32_t data_count = I2Cdrv->GetDataCount(); + debug_i2c_printf("[rx][%d] %02x %02x ", data_count, g_slave_RX_buff[0], g_slave_RX_buff[1]); + + // Ignore NOP commands and 0 length transmissions + if ((data_count != 0) && (g_slave_RX_buff[0] != gNopCmd_c)) { + scheduleClearTxBuffer = true; + if (event & EXTENSION_I2C_EVENT_SLAVE_ADDR_0) { + scheduleCallback(pfWriteCommsCallback, &g_slave_RX_buff[0], data_count); + } else if (event & EXTENSION_I2C_EVENT_SLAVE_ADDR_1) { + scheduleCallback(pfWriteFlashCallback, &g_slave_RX_buff[0], data_count); + } } } else if (prev_event & ARM_I2C_EVENT_SLAVE_TRANSMIT) { - debug_i2c_data((uint8_t *)"[tx] ", 5); + int32_t data_count = I2Cdrv->GetDataCount(); + debug_i2c_printf("[tx][%d] ", data_count); for (int i = 0; i < 5; i++) debug_i2c_printf("%02x ", g_slave_TX_buff[i]); if (event & EXTENSION_I2C_EVENT_SLAVE_ADDR_0) { - pfReadCommsCallback(&g_slave_TX_buff[0], I2Cdrv->GetDataCount()); + scheduleCallback(pfReadCommsCallback, &g_slave_TX_buff[0], data_count); } else if (event & EXTENSION_I2C_EVENT_SLAVE_ADDR_1) { - pfReadFlashCallback(&g_slave_TX_buff[0], I2Cdrv->GetDataCount()); + scheduleCallback(pfReadFlashCallback, &g_slave_TX_buff[0], data_count); } } } @@ -105,7 +165,7 @@ static void I2C_SignalEvent(uint32_t event) { void i2c_initialize() { - i2c_clearBuffer(); + i2c_clearBuffers(); // I2C addresses configured via default values from RTE_Device.h I2Cdrv->Initialize(I2C_SignalEvent); I2Cdrv->PowerControl(ARM_POWER_FULL); @@ -116,7 +176,7 @@ void i2c_deinitialize() I2Cdrv->Uninitialize(); } -i2c_status_t i2c_registerWriteCallback(i2cWriteCallback_t writeCallback, uint8_t slaveAddress) +i2c_status_t i2c_registerWriteCallback(i2cCallback_t writeCallback, uint8_t slaveAddress) { i2c_status_t status = I2C_STATUS_SUCCESS; @@ -137,7 +197,7 @@ i2c_status_t i2c_registerWriteCallback(i2cWriteCallback_t writeCallback, uint8_t return status; } -i2c_status_t i2c_registerReadCallback(i2cReadCallback_t readCallback, uint8_t slaveAddress) +i2c_status_t i2c_registerReadCallback(i2cCallback_t readCallback, uint8_t slaveAddress) { i2c_status_t status = I2C_STATUS_SUCCESS; @@ -158,10 +218,10 @@ i2c_status_t i2c_registerReadCallback(i2cReadCallback_t readCallback, uint8_t sl return status; } -void i2c_clearBuffer() +void i2c_clearBuffers() { - // TODO: Clean all buffers? KL27 code only clear this one memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); + memset(&g_slave_RX_buff, 0, sizeof(g_slave_RX_buff)); } void i2c_fillBuffer(uint8_t* data, uint32_t position, uint32_t size) @@ -180,3 +240,8 @@ bool i2c_isBusy() ARM_I2C_STATUS status = I2Cdrv->GetStatus(); return status.busy; } + +bool i2c_canSleep() +{ + return i2c_allow_sleep; +} From ff5d63ae41f0a9fb8aa33d00caef8a5d45b36f49 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Thu, 11 Nov 2021 10:56:52 +0000 Subject: [PATCH 490/617] nrf52820_microbit: Minor (inconsequential) fixes and clarifications. --- source/board/microbitv2/i2c_commands.c | 2 +- source/board/microbitv2/i2c_commands.h | 2 ++ source/board/microbitv2/nrf52820/i2c.c | 22 +++++++++++----------- source/board/microbitv2/nrf52820/storage.c | 1 + source/hic_hal/nordic/nrf52820/uart.c | 13 ++++++------- 5 files changed, 21 insertions(+), 19 deletions(-) diff --git a/source/board/microbitv2/i2c_commands.c b/source/board/microbitv2/i2c_commands.c index 7292a0a3a..1413035f3 100644 --- a/source/board/microbitv2/i2c_commands.c +++ b/source/board/microbitv2/i2c_commands.c @@ -77,7 +77,7 @@ static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { memcpy(&i2cResponse.cmdData.readRspCmd.data, &board_id_hex, sizeof(board_id_hex)); break; case gI2CProtocolVersion_c: { - uint16_t i2c_version = 2; + uint16_t i2c_version = I2C_PROTOCOL_VERSION; i2cResponse.cmdData.readRspCmd.dataSize = sizeof(i2c_version); memcpy(&i2cResponse.cmdData.readRspCmd.data, &i2c_version, sizeof(i2c_version)); } diff --git a/source/board/microbitv2/i2c_commands.h b/source/board/microbitv2/i2c_commands.h index d8002e882..2c4bcf1f0 100644 --- a/source/board/microbitv2/i2c_commands.h +++ b/source/board/microbitv2/i2c_commands.h @@ -37,6 +37,8 @@ extern "C" { #define I2C_SLAVE_HID (0x71U) #define I2C_SLAVE_FLASH (0x72U) +#define I2C_PROTOCOL_VERSION (0x02) + /*! i2c command Id type enumeration */ typedef enum cmdId_tag { gNopCmd_c = 0x00, diff --git a/source/board/microbitv2/nrf52820/i2c.c b/source/board/microbitv2/nrf52820/i2c.c index 0af49440e..22afe79c2 100644 --- a/source/board/microbitv2/nrf52820/i2c.c +++ b/source/board/microbitv2/nrf52820/i2c.c @@ -61,12 +61,12 @@ static callbackToExecute_t callbackToExecute = { .size = 0, }; -static bool scheduleClearTxBuffer = false; +static bool g_schedule_clear_tx_buffer = false; static bool i2c_allow_sleep = true; -static i2c_status_t scheduleCallback(i2cCallback_t callback, uint8_t* pData, uint8_t size) +static i2c_status_t i2c_scheduleCallback(i2cCallback_t callback, uint8_t* pData, uint8_t size) { if (callbackToExecute.pfCallback != NULL) { return I2C_STATUS_FAIL; @@ -84,10 +84,10 @@ static i2c_status_t scheduleCallback(i2cCallback_t callback, uint8_t* pData, uin // Hook function executed in the main task void board_custom_event() { - if (scheduleClearTxBuffer) { + if (g_schedule_clear_tx_buffer) { debug_i2c_data((uint8_t *)"[clTxBf]\n", 9); memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); - scheduleClearTxBuffer = false; + g_schedule_clear_tx_buffer = false; } if (callbackToExecute.pfCallback != NULL) { @@ -101,7 +101,7 @@ void board_custom_event() i2c_allow_sleep = true; } -static void I2C_SignalEvent(uint32_t event) { +static void i2c_signalEvent(uint32_t event) { static uint32_t prev_event = 0; debug_i2c_printf("evt[%d] ", event); @@ -124,11 +124,11 @@ static void I2C_SignalEvent(uint32_t event) { // Ignore NOP commands and 0 length transmissions if ((data_count != 0) && (g_slave_RX_buff[0] != gNopCmd_c)) { - scheduleClearTxBuffer = true; + g_schedule_clear_tx_buffer = true; if (event & EXTENSION_I2C_EVENT_SLAVE_ADDR_0) { - scheduleCallback(pfWriteCommsCallback, &g_slave_RX_buff[0], data_count); + i2c_scheduleCallback(pfWriteCommsCallback, &g_slave_RX_buff[0], data_count); } else if (event & EXTENSION_I2C_EVENT_SLAVE_ADDR_1) { - scheduleCallback(pfWriteFlashCallback, &g_slave_RX_buff[0], data_count); + i2c_scheduleCallback(pfWriteFlashCallback, &g_slave_RX_buff[0], data_count); } } } else if (prev_event & ARM_I2C_EVENT_SLAVE_TRANSMIT) { @@ -137,9 +137,9 @@ static void I2C_SignalEvent(uint32_t event) { for (int i = 0; i < 5; i++) debug_i2c_printf("%02x ", g_slave_TX_buff[i]); if (event & EXTENSION_I2C_EVENT_SLAVE_ADDR_0) { - scheduleCallback(pfReadCommsCallback, &g_slave_TX_buff[0], data_count); + i2c_scheduleCallback(pfReadCommsCallback, &g_slave_TX_buff[0], data_count); } else if (event & EXTENSION_I2C_EVENT_SLAVE_ADDR_1) { - scheduleCallback(pfReadFlashCallback, &g_slave_TX_buff[0], data_count); + i2c_scheduleCallback(pfReadFlashCallback, &g_slave_TX_buff[0], data_count); } } } @@ -167,7 +167,7 @@ void i2c_initialize() { i2c_clearBuffers(); // I2C addresses configured via default values from RTE_Device.h - I2Cdrv->Initialize(I2C_SignalEvent); + I2Cdrv->Initialize(i2c_signalEvent); I2Cdrv->PowerControl(ARM_POWER_FULL); } diff --git a/source/board/microbitv2/nrf52820/storage.c b/source/board/microbitv2/nrf52820/storage.c index d2b697525..76cbd1d4d 100644 --- a/source/board/microbitv2/nrf52820/storage.c +++ b/source/board/microbitv2/nrf52820/storage.c @@ -40,6 +40,7 @@ uint32_t storage_program_page(uint32_t adr, uint32_t sz, uint8_t *buf) uint32_t storage_erase_sector(uint32_t adr) { + // This operation can take up to 87.5ms nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_ERASE); nrf_nvmc_page_erase_start(NRF_NVMC, adr); while (!nrf_nvmc_ready_check(NRF_NVMC)) { diff --git a/source/hic_hal/nordic/nrf52820/uart.c b/source/hic_hal/nordic/nrf52820/uart.c index 280b0793c..cdc3512fd 100644 --- a/source/hic_hal/nordic/nrf52820/uart.c +++ b/source/hic_hal/nordic/nrf52820/uart.c @@ -31,7 +31,6 @@ #define USART_IRQ (UARTE0_UART0_IRQn) extern ARM_DRIVER_USART USART_INSTANCE; -extern uint32_t SystemCoreClock; static void clear_buffers(void); @@ -64,8 +63,8 @@ int32_t uart_initialize(void) { clear_buffers(); cb_buf.tx_size = 0; - Driver_USART0.Initialize(uart_handler); - Driver_USART0.PowerControl(ARM_POWER_FULL); + USART_INSTANCE.Initialize(uart_handler); + USART_INSTANCE.PowerControl(ARM_POWER_FULL); return 1; } @@ -74,8 +73,8 @@ int32_t uart_uninitialize(void) { USART_INSTANCE.Control(ARM_USART_CONTROL_RX, 0); USART_INSTANCE.Control(ARM_USART_ABORT_RECEIVE, 0U); - Driver_USART0.PowerControl(ARM_POWER_OFF); - Driver_USART0.Uninitialize(); + USART_INSTANCE.PowerControl(ARM_POWER_OFF); + USART_INSTANCE.Uninitialize(); clear_buffers(); cb_buf.tx_size = 0; @@ -99,7 +98,7 @@ int32_t uart_set_configuration(UART_Configuration *config) switch (config->DataBits) { case UART_DATA_BITS_5: - control |= UART_DATA_BITS_5; + control |= ARM_USART_DATA_BITS_5; break; case UART_DATA_BITS_6: @@ -107,7 +106,7 @@ int32_t uart_set_configuration(UART_Configuration *config) break; case UART_DATA_BITS_7: - control |= ARM_USART_DATA_BITS_6; + control |= ARM_USART_DATA_BITS_7; break; case UART_DATA_BITS_8: /* fallthrough */ From 9175005941a424b499782024052ff0b81f468b4a Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Thu, 11 Nov 2021 11:01:33 +0000 Subject: [PATCH 491/617] nrf52820_microbit: Set up USB, UART and I2C interrupt priorities. --- source/hic_hal/nordic/nrf52820/USART_nRF52820.c | 1 + source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h | 6 +++--- source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c | 4 +++- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/source/hic_hal/nordic/nrf52820/USART_nRF52820.c b/source/hic_hal/nordic/nrf52820/USART_nRF52820.c index 036276c4a..b9575e8e7 100644 --- a/source/hic_hal/nordic/nrf52820/USART_nRF52820.c +++ b/source/hic_hal/nordic/nrf52820/USART_nRF52820.c @@ -285,6 +285,7 @@ static int32_t USART_PowerControl (ARM_POWER_STATE state) { driver_state |= USART_FLAG_POWERED; + NVIC_SetPriority(UARTE0_UART0_IRQn, NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY); NVIC_ClearPendingIRQ(UARTE0_UART0_IRQn); NVIC_EnableIRQ(UARTE0_UART0_IRQn); break; diff --git a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h index 54058b24d..c01c25248 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h +++ b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h @@ -1276,7 +1276,7 @@ // <7=> 7 #ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 2 #endif // NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module. @@ -1442,7 +1442,7 @@ // <7=> 7 #ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 3 #endif // NRFX_UARTE_CONFIG_LOG_ENABLED - Enables logging in the module. @@ -1595,7 +1595,7 @@ // <7=> 7 #ifndef NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#define NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY 1 #endif // USBD_CONFIG_DMASCHEDULER_ISO_BOOST - Give priority to isochronous transfers diff --git a/source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c b/source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c index 77159bc0a..6c7b9d26c 100644 --- a/source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c +++ b/source/hic_hal/nordic/nrf52820/usbd_nRF528xx.c @@ -53,6 +53,7 @@ #include "rl_usb.h" #include "nrf.h" /* Device header */ +#include "nrfx.h" #include "nrf52_erratas.h" #define __NO_USB_LIB_C @@ -102,7 +103,7 @@ void usbd_enable (void) { /* Enable the peripheral */ NRF_USBD->ENABLE = USBD_ENABLE_ENABLE_Enabled << USBD_ENABLE_ENABLE_Pos; - /* Waiting for peripheral to enable (max 10 ms), this should take a few µs */ + /* Waiting for peripheral to enable (max 10 ms), this should take a few �s */ for (i = 160000U; i != 0U; i--) { if ((NRF_USBD->EVENTCAUSE & USBD_EVENTCAUSE_READY_Msk) != 0U) { break; @@ -190,6 +191,7 @@ void USBD_Init (void) { /* Enable only USB Reset interrupt */ NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk; + NVIC_SetPriority(USBD_IRQn, NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY); NVIC_ClearPendingIRQ(USBD_IRQn); NVIC_EnableIRQ(USBD_IRQn); } From a2de1661815f3f6da88e4c8211cfdf3b1bac7321 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Thu, 11 Nov 2021 12:05:54 +0000 Subject: [PATCH 492/617] nrf52820_microbit: Add i2c_wake_timeout to nRF i2c.c. --- source/board/microbitv2/nrf52820/i2c.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/source/board/microbitv2/nrf52820/i2c.c b/source/board/microbitv2/nrf52820/i2c.c index 22afe79c2..9fb219020 100644 --- a/source/board/microbitv2/nrf52820/i2c.c +++ b/source/board/microbitv2/nrf52820/i2c.c @@ -63,6 +63,8 @@ static callbackToExecute_t callbackToExecute = { static bool g_schedule_clear_tx_buffer = false; +// TODO: This can probably be combined with the busy state for simpler sleep config +extern uint8_t i2c_wake_timeout; static bool i2c_allow_sleep = true; @@ -153,10 +155,12 @@ static void i2c_signalEvent(uint32_t event) { } if (event & ARM_I2C_EVENT_SLAVE_RECEIVE) { int32_t ret = I2Cdrv->SlaveReceive(&g_slave_RX_buff[0], I2C_DATA_LENGTH); + i2c_wake_timeout = 4; // 4 * 30ms tick = 120ms timeout debug_i2c_printf("rx[%d] ", ret); } if (event & ARM_I2C_EVENT_SLAVE_TRANSMIT) { int32_t ret = I2Cdrv->SlaveTransmit(&g_slave_TX_buff[0], I2C_DATA_LENGTH); + i2c_wake_timeout = 4; // 4 * 30ms tick = 120ms timeout debug_i2c_printf("tx[%d] ", ret); } debug_i2c_data((uint8_t *)".\n", 2); @@ -166,6 +170,12 @@ static void i2c_signalEvent(uint32_t event) { void i2c_initialize() { i2c_clearBuffers(); + callbackToExecute.pfCallback = NULL; + callbackToExecute.pData = NULL; + callbackToExecute.size = 0; + g_schedule_clear_tx_buffer = false; + i2c_allow_sleep = true; + // I2C addresses configured via default values from RTE_Device.h I2Cdrv->Initialize(i2c_signalEvent); I2Cdrv->PowerControl(ARM_POWER_FULL); From 172ab04f1bf13941965899609eb02ffaa9ba0c59 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 4 Nov 2021 00:18:41 -0500 Subject: [PATCH 493/617] lpc55xx_hic: add support for MCU-LINK-PRO and nRESET - Support for nRESET as reset button - Detect MCU-LINK-PRO and support additional LEDs --- source/hic_hal/nxp/lpc55xx/DAP_config.h | 5 +- source/hic_hal/nxp/lpc55xx/IO_Config.h | 88 ++++++++++++++++++++++- source/hic_hal/nxp/lpc55xx/gpio.c | 92 ++++++++++++++++++++++--- 3 files changed, 169 insertions(+), 16 deletions(-) diff --git a/source/hic_hal/nxp/lpc55xx/DAP_config.h b/source/hic_hal/nxp/lpc55xx/DAP_config.h index c5da0b66e..4b6b9c067 100644 --- a/source/hic_hal/nxp/lpc55xx/DAP_config.h +++ b/source/hic_hal/nxp/lpc55xx/DAP_config.h @@ -24,6 +24,7 @@ #include "IO_Config.h" #include "fsl_iocon.h" +#include "gpio.h" //************************************************************************************************** /** @@ -452,7 +453,7 @@ It is recommended to provide the following LEDs for status indication: */ __STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit) { -// BITBAND_REG(LED_CONNECTED_GPIO->PDOR, LED_CONNECTED_BIT) = ~bit; + gpio_set_leds(LED_T_CONNECTED, bit ? GPIO_LED_ON : GPIO_LED_OFF); } /** Debug Unit: Set status Target Running LED. @@ -462,7 +463,7 @@ __STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit) */ __STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit) { - ; // Not available + gpio_set_leds(LED_T_RUNNING, bit ? GPIO_LED_ON : GPIO_LED_OFF); } ///@} diff --git a/source/hic_hal/nxp/lpc55xx/IO_Config.h b/source/hic_hal/nxp/lpc55xx/IO_Config.h index 64d4e4bac..15cf5e229 100644 --- a/source/hic_hal/nxp/lpc55xx/IO_Config.h +++ b/source/hic_hal/nxp/lpc55xx/IO_Config.h @@ -114,8 +114,90 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC55XX); // (PIO0_5-ISP_EN-LED1_CTRL) // active low // port always has pull-up and digital input (DIGIMODE) enabled (UM11126, section 15.5.1, table 312) -#define LED_CONNECTED (5U) -#define LED_CONNECTED_MASK (1U << LED_CONNECTED) - +#define LED_A_PORT (0U) +#define LED_A_PIN (5U) +#define LED_A_MASK (1U << LED_A_PIN) + +////////////////////////////////////////////////////////////////////////////////////////////////// +// Additional configuration for MCU-LINK-PRO support +////////////////////////////////////////////////////////////////////////////////////////////////// + +//// MCU-LINK / OB (for reference) +// +// HW_VER_6 PIO0_18 GPI (pullup required) VCOM disabled when low (J4) +// HW_VER_7 PIO0_27 GPI (pullup required) SWD debug disabled when low (J5) +// DBGIF_RESET PIO0_19 GPIO +// +// LED_A: ISP_EN-LED_SWD_ACT PIO0_5 GPO (LED1 Red) Status +// + +//// MCU-LINK-PRO +// +// HW_VER_0 PIO1_27 GPI (pullup required) USB power negotiation when low +// HW_VER_1 PIO1_28 GPI (pullup required) 1-bit board id code +// HW_VER_2 PIO1_30 GPI (pullup required) Disable USB-SIO bridge when low (J15) +// HW_VER_3 PIO1_4 GPI (pullup required) OB(0) or Pro (1) id +// HW_VER_4 PIO1_5 GPI (pullup required) Board id code is valid when low +// HW_VER_5 PIO1_6 GPI (pullup required) Power measurement enabled when low +// HW_VER_6 PIO0_18 GPI (pullup required) VCOM disabled when low (J14) +// HW_VER_7 PIO0_27 GPI (pullup required) SWD debug disabled when low (J13) +// DBGIF_RESET PIO0_19 GPIO (SW1) +// +// LED_A: ISP_EN-LED_SWD_ACT PIO0_5 GPO (LED3 Red) Status +// LED_B: LED_OPT1 PIO1_17 GPO (LED6 Green) SIO activity +// LED_C: LED_SWO_ACT PIO1_13 GPO (LED2 Green) SWO activity +// LED_D: LED_OPT2 PIO1_18 GPO (LED7 Green) NRG (Energy) +// LED_E: LED_VCOM_ACT PIO1_15 GPO (LED4 Green) VCOM activity +// LED_F: LED_USB_COMM PIO1_12 GPO (LED1 Green) USB communication +// LED_G: LED_HEARTBEAT PIO1_16 GPO (LED5 Green) FUNC + +#define LED_B_PORT (1U) +#define LED_B_PIN (17U) +#define LED_B_MASK (1U << LED_B_PIN) + +#define LED_C_PORT (1U) +#define LED_C_PIN (13U) +#define LED_C_MASK (1U << LED_C_PIN) + +#define LED_D_PORT (1U) +#define LED_D_PIN (18U) +#define LED_D_MASK (1U << LED_D_PIN) + +#define LED_E_PORT (1U) +#define LED_E_PIN (15U) +#define LED_E_MASK (1U << LED_E_PIN) + +#define LED_F_PORT (1U) +#define LED_F_PIN (12U) +#define LED_F_MASK (1U << LED_F_PIN) + +#define LED_G_PORT (1U) +#define LED_G_PIN (16U) +#define LED_G_MASK (1U << LED_G_PIN) + +// HW Version 3 Pin PIO1_4 (I, pullup) +// (HW_VERS_3) +#define PIN_HW_VERS_3_PORT (1U) +#define PIN_HW_VERS_3 (4U) +#define PIN_HW_VERS_3_MASK (1U << PIN_HW_VERS_3) + +// HW Version 4 Pin PIO1_5 (I, pullup) +// (HW_VERS_4) +#define PIN_HW_VERS_4_PORT (1U) +#define PIN_HW_VERS_4 (5U) +#define PIN_HW_VERS_4_MASK (1U << PIN_HW_VERS_4) + +typedef enum led_types { + LED_T_CONNECTED = 1 << 0, + LED_T_RUNNING = 1 << 1, + LED_T_HID = 1 << 2, + LED_T_CDC = 1 << 3, + LED_T_MSC = 1 << 4, + LED_T_EXTRA1 = 1 << 5, + LED_T_EXTRA2 = 1 << 6, +} led_types_t; + +typedef enum led_state gpio_led_state_t; +void gpio_set_leds(uint32_t leds, gpio_led_state_t state); #endif diff --git a/source/hic_hal/nxp/lpc55xx/gpio.c b/source/hic_hal/nxp/lpc55xx/gpio.c index 385533bc3..5012cefdd 100644 --- a/source/hic_hal/nxp/lpc55xx/gpio.c +++ b/source/hic_hal/nxp/lpc55xx/gpio.c @@ -1,6 +1,6 @@ /** * @file gpio.c - * @brief + * @brief GPIO handling for LPC55xx HIC, MCU-LINK and MCU-LINK-PRO * * DAPLink Interface Firmware * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved @@ -29,6 +29,8 @@ #include "fsl_iocon.h" #include "fsl_reset.h" +static bool mcu_link_pro = false; + void gpio_init(void) { // Enable hardfault on unaligned access for the interface only. @@ -40,28 +42,67 @@ void gpio_init(void) // Ensure clocks are enabled. SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_IOCON_MASK - | SYSCON_AHBCLKCTRL0_GPIO0_MASK; + | SYSCON_AHBCLKCTRL0_GPIO0_MASK + | SYSCON_AHBCLKCTRL0_GPIO1_MASK; SYSCON->AHBCLKCTRLSET[1] = SYSCON_AHBCLKCTRL1_FC0_MASK | SYSCON_AHBCLKCTRL1_FC3_MASK; // Reset peripherals. RESET_PeripheralReset(kIOCON_RST_SHIFT_RSTn); RESET_PeripheralReset(kGPIO0_RST_SHIFT_RSTn); + RESET_PeripheralReset(kGPIO1_RST_SHIFT_RSTn); RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn); RESET_PeripheralReset(kFC3_RST_SHIFT_RSTn); + // Configure pins for board detection + IOCON->PIO[PIN_HW_VERS_3_PORT][PIN_HW_VERS_3] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; + IOCON->PIO[PIN_HW_VERS_4_PORT][PIN_HW_VERS_4] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; + GPIO->DIRCLR[PIN_HW_VERS_3_PORT] = PIN_HW_VERS_3_MASK; + GPIO->DIRCLR[PIN_HW_VERS_4_PORT] = PIN_HW_VERS_4_MASK; + if (GPIO->B[PIN_HW_VERS_4_PORT][PIN_HW_VERS_4] == 0 && GPIO->B[PIN_HW_VERS_3_PORT][PIN_HW_VERS_3] != 0) { + mcu_link_pro = true; + } + // Configure pins. - IOCON->PIO[PIN_PIO_PORT][LED_CONNECTED] = IOCON_FUNC0 | IOCON_DIGITAL_EN; + IOCON->PIO[LED_A_PORT][LED_A_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; + IOCON->PIO[PIN_PIO_PORT][PIN_RESET] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; IOCON->PIO[PIN_PIO_PORT][PIN_HW_VERS_6] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; IOCON->PIO[PIN_PIO_PORT][PIN_HW_VERS_7] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; + if (mcu_link_pro) { + IOCON->PIO[LED_B_PORT][LED_B_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; + IOCON->PIO[LED_C_PORT][LED_C_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; + IOCON->PIO[LED_D_PORT][LED_D_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; + IOCON->PIO[LED_E_PORT][LED_E_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; + IOCON->PIO[LED_F_PORT][LED_F_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; + IOCON->PIO[LED_G_PORT][LED_G_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; + } // Turn off LED. - GPIO->B[PIN_PIO_PORT][LED_CONNECTED] = 1; + GPIO->B[LED_A_PORT][LED_A_PIN] = 1; + if (mcu_link_pro) { + GPIO->B[LED_B_PORT][LED_B_PIN] = 1; + GPIO->B[LED_C_PORT][LED_C_PIN] = 1; + GPIO->B[LED_D_PORT][LED_D_PIN] = 1; + GPIO->B[LED_E_PORT][LED_E_PIN] = 1; + GPIO->B[LED_F_PORT][LED_F_PIN] = 1; + GPIO->B[LED_G_PORT][LED_G_PIN] = 1; + } + // Set LED to output. - GPIO->DIRSET[PIN_PIO_PORT] = LED_CONNECTED_MASK; + GPIO->DIRSET[LED_A_PORT] = LED_A_MASK; + if (mcu_link_pro) { + GPIO->DIRSET[LED_B_PORT] = LED_B_MASK; + GPIO->DIRSET[LED_C_PORT] = LED_C_MASK; + GPIO->DIRSET[LED_D_PORT] = LED_D_MASK; + GPIO->DIRSET[LED_E_PORT] = LED_E_MASK; + GPIO->DIRSET[LED_F_PORT] = LED_F_MASK; + GPIO->DIRSET[LED_G_PORT] = LED_G_MASK; + } + // Turn on LED. - GPIO->B[PIN_PIO_PORT][LED_CONNECTED] = 1; + GPIO->B[LED_A_PORT][LED_A_PIN] = 0; + GPIO->DIRCLR[PIN_PIO_PORT] = PIN_RESET_MASK; GPIO->DIRCLR[PIN_PIO_PORT] = PIN_HW_VERS_6_MASK; GPIO->DIRCLR[PIN_PIO_PORT] = PIN_HW_VERS_7_MASK; } @@ -71,25 +112,54 @@ void gpio_set_board_power(bool powerEnabled) // No target power control in this circuit. } -void gpio_set_hid_led(gpio_led_state_t state) +void gpio_set_leds(uint32_t leds, gpio_led_state_t state) { // LED is active low, so set to inverse of the enum value. - GPIO->B[PIN_PIO_PORT][LED_CONNECTED] = !(uint8_t)state; + if(mcu_link_pro) { + if(leds & LED_T_CONNECTED) { + GPIO->B[LED_A_PORT][LED_A_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); + } + if(leds & LED_T_RUNNING) { + GPIO->B[LED_B_PORT][LED_B_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); + } + if(leds & LED_T_HID) { + GPIO->B[LED_C_PORT][LED_C_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); + } + if(leds & LED_T_CDC) { + GPIO->B[LED_D_PORT][LED_D_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); + } + if(leds & LED_T_MSC) { + GPIO->B[LED_E_PORT][LED_E_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); + } + if(leds & LED_T_EXTRA1) { + GPIO->B[LED_F_PORT][LED_F_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); + } + if(leds & LED_T_EXTRA2) { + GPIO->B[LED_G_PORT][LED_G_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); + } + } else if(leds & (LED_T_CONNECTED | LED_T_HID | LED_T_CDC | LED_T_MSC)) { + GPIO->B[LED_A_PORT][LED_A_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); + } +} + +void gpio_set_hid_led(gpio_led_state_t state) +{ + gpio_set_leds(LED_T_HID, state); } void gpio_set_cdc_led(gpio_led_state_t state) { - gpio_set_hid_led(state); + gpio_set_leds(LED_T_CDC, state); } void gpio_set_msc_led(gpio_led_state_t state) { - gpio_set_hid_led(state); + gpio_set_leds(LED_T_MSC, state); } uint8_t gpio_get_reset_btn_no_fwrd(void) { - return GPIO->B[PIN_PIO_PORT][PIN_HW_VERS_6] ? 0 : 1; + return (PIN_nRESET_IN() && GPIO->B[PIN_PIO_PORT][PIN_HW_VERS_6]) ? 0 : 1; } uint8_t gpio_get_reset_btn_fwrd(void) From 04cdbcd3f43cd036a5f6a496f37e4700bcf0e7b7 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 8 Nov 2021 22:12:46 -0600 Subject: [PATCH 494/617] lpc55xx_hic: move MCU-LINK feature to specific images --- projects.yaml | 9 +++ records/board/mcu_link.yaml | 4 + source/hic_hal/nxp/lpc55xx/gpio.c | 120 ++++++++++++++++++++---------- 3 files changed, 92 insertions(+), 41 deletions(-) create mode 100644 records/board/mcu_link.yaml diff --git a/projects.yaml b/projects.yaml index ca346c8ff..f7990b128 100644 --- a/projects.yaml +++ b/projects.yaml @@ -446,6 +446,15 @@ projects: - *module_if - *module_hic_lpc4322 - records/board/lpc55S69xpresso.yaml + lpc55s69_mculink_bl: + - *module_bl + - records/hic_hal/lpc55s69.yaml + - records/board/lpc55s69_bl.yaml + - records/board/mcu_link.yaml + lpc55s69_mculink_if: + - *module_if + - *module_hic_lpc55s69 + - records/board/mcu_link.yaml m48ssidae_numaker_iot_m263a_if: - *module_if - *module_hic_m48ssidae diff --git a/records/board/mcu_link.yaml b/records/board/mcu_link.yaml new file mode 100644 index 000000000..8a7620305 --- /dev/null +++ b/records/board/mcu_link.yaml @@ -0,0 +1,4 @@ +common: + macros: + - MCU_LINK_SUPPORT + - MCU_LINK_PRO_GREETING diff --git a/source/hic_hal/nxp/lpc55xx/gpio.c b/source/hic_hal/nxp/lpc55xx/gpio.c index 5012cefdd..9b1b0ffc0 100644 --- a/source/hic_hal/nxp/lpc55xx/gpio.c +++ b/source/hic_hal/nxp/lpc55xx/gpio.c @@ -28,8 +28,11 @@ #include "fsl_clock.h" #include "fsl_iocon.h" #include "fsl_reset.h" +#include "cmsis_os2.h" -static bool mcu_link_pro = false; +#ifdef MCU_LINK_SUPPORT +static bool s_mcu_link_pro = false; +#endif void gpio_init(void) { @@ -43,68 +46,89 @@ void gpio_init(void) // Ensure clocks are enabled. SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_IOCON_MASK | SYSCON_AHBCLKCTRL0_GPIO0_MASK - | SYSCON_AHBCLKCTRL0_GPIO1_MASK; +#ifdef MCU_LINK_SUPPORT + | SYSCON_AHBCLKCTRL0_GPIO1_MASK +#endif + ; SYSCON->AHBCLKCTRLSET[1] = SYSCON_AHBCLKCTRL1_FC0_MASK | SYSCON_AHBCLKCTRL1_FC3_MASK; // Reset peripherals. RESET_PeripheralReset(kIOCON_RST_SHIFT_RSTn); RESET_PeripheralReset(kGPIO0_RST_SHIFT_RSTn); - RESET_PeripheralReset(kGPIO1_RST_SHIFT_RSTn); RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn); RESET_PeripheralReset(kFC3_RST_SHIFT_RSTn); + // Configure pins. + IOCON->PIO[LED_A_PORT][LED_A_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; + IOCON->PIO[PIN_PIO_PORT][PIN_RESET] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; + + // Turn off LED. + GPIO->B[LED_A_PORT][LED_A_PIN] = 1; + + // Set LED to output. + GPIO->DIRSET[LED_A_PORT] = LED_A_MASK; + + // Turn on LED. + GPIO->B[LED_A_PORT][LED_A_PIN] = 0; + + // Set RESET to input + GPIO->DIRCLR[PIN_PIO_PORT] = PIN_RESET_MASK; + + +#ifdef MCU_LINK_SUPPORT + RESET_PeripheralReset(kGPIO1_RST_SHIFT_RSTn); + + // Configure additonal + IOCON->PIO[PIN_PIO_PORT][PIN_HW_VERS_6] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; + IOCON->PIO[PIN_PIO_PORT][PIN_HW_VERS_7] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; // Configure pins for board detection IOCON->PIO[PIN_HW_VERS_3_PORT][PIN_HW_VERS_3] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; IOCON->PIO[PIN_HW_VERS_4_PORT][PIN_HW_VERS_4] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; + GPIO->DIRCLR[PIN_HW_VERS_3_PORT] = PIN_HW_VERS_3_MASK; GPIO->DIRCLR[PIN_HW_VERS_4_PORT] = PIN_HW_VERS_4_MASK; + GPIO->DIRCLR[PIN_PIO_PORT] = PIN_HW_VERS_6_MASK; + GPIO->DIRCLR[PIN_PIO_PORT] = PIN_HW_VERS_7_MASK; + if (GPIO->B[PIN_HW_VERS_4_PORT][PIN_HW_VERS_4] == 0 && GPIO->B[PIN_HW_VERS_3_PORT][PIN_HW_VERS_3] != 0) { - mcu_link_pro = true; - } + s_mcu_link_pro = true; - // Configure pins. - IOCON->PIO[LED_A_PORT][LED_A_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; - IOCON->PIO[PIN_PIO_PORT][PIN_RESET] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; - IOCON->PIO[PIN_PIO_PORT][PIN_HW_VERS_6] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; - IOCON->PIO[PIN_PIO_PORT][PIN_HW_VERS_7] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; - if (mcu_link_pro) { IOCON->PIO[LED_B_PORT][LED_B_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; IOCON->PIO[LED_C_PORT][LED_C_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; IOCON->PIO[LED_D_PORT][LED_D_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; IOCON->PIO[LED_E_PORT][LED_E_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; IOCON->PIO[LED_F_PORT][LED_F_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; IOCON->PIO[LED_G_PORT][LED_G_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; - } - // Turn off LED. - GPIO->B[LED_A_PORT][LED_A_PIN] = 1; - if (mcu_link_pro) { - GPIO->B[LED_B_PORT][LED_B_PIN] = 1; - GPIO->B[LED_C_PORT][LED_C_PIN] = 1; - GPIO->B[LED_D_PORT][LED_D_PIN] = 1; - GPIO->B[LED_E_PORT][LED_E_PIN] = 1; - GPIO->B[LED_F_PORT][LED_F_PIN] = 1; - GPIO->B[LED_G_PORT][LED_G_PIN] = 1; - } - - // Set LED to output. - GPIO->DIRSET[LED_A_PORT] = LED_A_MASK; - if (mcu_link_pro) { GPIO->DIRSET[LED_B_PORT] = LED_B_MASK; GPIO->DIRSET[LED_C_PORT] = LED_C_MASK; GPIO->DIRSET[LED_D_PORT] = LED_D_MASK; GPIO->DIRSET[LED_E_PORT] = LED_E_MASK; GPIO->DIRSET[LED_F_PORT] = LED_F_MASK; GPIO->DIRSET[LED_G_PORT] = LED_G_MASK; - } - // Turn on LED. - GPIO->B[LED_A_PORT][LED_A_PIN] = 0; + GPIO->B[LED_B_PORT][LED_B_PIN] = 1; + GPIO->B[LED_C_PORT][LED_C_PIN] = 1; + GPIO->B[LED_D_PORT][LED_D_PIN] = 1; + GPIO->B[LED_E_PORT][LED_E_PIN] = 1; + GPIO->B[LED_F_PORT][LED_F_PIN] = 1; + GPIO->B[LED_G_PORT][LED_G_PIN] = 1; - GPIO->DIRCLR[PIN_PIO_PORT] = PIN_RESET_MASK; - GPIO->DIRCLR[PIN_PIO_PORT] = PIN_HW_VERS_6_MASK; - GPIO->DIRCLR[PIN_PIO_PORT] = PIN_HW_VERS_7_MASK; +#if defined(DAPLINK_IF) && defined(MCU_LINK_PRO_GREETING) + uint8_t j = 0; + for (uint8_t i = 0; i < 7; i++) { + osDelay(15); + j = (j << 1 | 1); + gpio_set_leds(j, GPIO_LED_ON); + } + osDelay(15); + gpio_set_leds(j, GPIO_LED_OFF); +#endif + } else { + // Disable GPIO1 clock? + } +#endif } void gpio_set_board_power(bool powerEnabled) @@ -115,31 +139,37 @@ void gpio_set_board_power(bool powerEnabled) void gpio_set_leds(uint32_t leds, gpio_led_state_t state) { // LED is active low, so set to inverse of the enum value. - if(mcu_link_pro) { - if(leds & LED_T_CONNECTED) { +#ifdef MCU_LINK_SUPPORT + if (s_mcu_link_pro) { + if (leds & LED_T_CONNECTED) { GPIO->B[LED_A_PORT][LED_A_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); } - if(leds & LED_T_RUNNING) { + if (leds & LED_T_RUNNING) { GPIO->B[LED_B_PORT][LED_B_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); } - if(leds & LED_T_HID) { + if (leds & LED_T_HID) { GPIO->B[LED_C_PORT][LED_C_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); } - if(leds & LED_T_CDC) { + if (leds & LED_T_CDC) { GPIO->B[LED_D_PORT][LED_D_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); } - if(leds & LED_T_MSC) { + if (leds & LED_T_MSC) { GPIO->B[LED_E_PORT][LED_E_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); } - if(leds & LED_T_EXTRA1) { + if (leds & LED_T_EXTRA1) { GPIO->B[LED_F_PORT][LED_F_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); } - if(leds & LED_T_EXTRA2) { + if (leds & LED_T_EXTRA2) { GPIO->B[LED_G_PORT][LED_G_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); } - } else if(leds & (LED_T_CONNECTED | LED_T_HID | LED_T_CDC | LED_T_MSC)) { + } else if (leds & (LED_T_CONNECTED | LED_T_HID | LED_T_CDC | LED_T_MSC)) { + GPIO->B[LED_A_PORT][LED_A_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); + } +#else + if (leds & (LED_T_CONNECTED | LED_T_HID | LED_T_CDC | LED_T_MSC)) { GPIO->B[LED_A_PORT][LED_A_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); } +#endif } void gpio_set_hid_led(gpio_led_state_t state) @@ -159,10 +189,18 @@ void gpio_set_msc_led(gpio_led_state_t state) uint8_t gpio_get_reset_btn_no_fwrd(void) { +#ifdef MCU_LINK_SUPPORT return (PIN_nRESET_IN() && GPIO->B[PIN_PIO_PORT][PIN_HW_VERS_6]) ? 0 : 1; +#else + return PIN_nRESET_IN() ? 0 : 1; +#endif } uint8_t gpio_get_reset_btn_fwrd(void) { +#ifdef MCU_LINK_SUPPORT return GPIO->B[PIN_PIO_PORT][PIN_HW_VERS_7] ? 0 : 1; +#else + return 0; +#endif } From d0890af9d00a378ba1086f3aab2e78583f5a0050 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 8 Nov 2021 22:33:34 -0600 Subject: [PATCH 495/617] lpc55xx_hic: move MCU-LINK support out of HIC source --- records/board/mcu_link.yaml | 3 + source/board/mcu-link.c | 126 ++++++++++++++++++++++++++++++ source/hic_hal/nxp/lpc55xx/gpio.c | 119 +++------------------------- 3 files changed, 142 insertions(+), 106 deletions(-) create mode 100644 source/board/mcu-link.c diff --git a/records/board/mcu_link.yaml b/records/board/mcu_link.yaml index 8a7620305..36750ef10 100644 --- a/records/board/mcu_link.yaml +++ b/records/board/mcu_link.yaml @@ -2,3 +2,6 @@ common: macros: - MCU_LINK_SUPPORT - MCU_LINK_PRO_GREETING + sources: + board: + - source/board/mcu-link.c diff --git a/source/board/mcu-link.c b/source/board/mcu-link.c new file mode 100644 index 000000000..a2790b849 --- /dev/null +++ b/source/board/mcu-link.c @@ -0,0 +1,126 @@ +/** + * @file mcu-link.c + * @brief MCU-LINK and MCU-LINK-PRO support + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2021, Arm Limited, All Rights Reserved + * Copyright (c) 2021 Mathias Brossard + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "fsl_device_registers.h" +#include "DAP_config.h" +#include "gpio.h" +#include "cmsis_os2.h" + +static bool s_mcu_link_pro = false; + +void board_gpio_init() +{ + // Ensure GPIO1 clocks are enabled. + SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_IOCON_MASK + | SYSCON_AHBCLKCTRL0_GPIO0_MASK + | SYSCON_AHBCLKCTRL0_GPIO1_MASK; + RESET_PeripheralReset(kGPIO1_RST_SHIFT_RSTn); + + // Configure additonal reset pins + IOCON->PIO[PIN_PIO_PORT][PIN_HW_VERS_6] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; + IOCON->PIO[PIN_PIO_PORT][PIN_HW_VERS_7] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; + GPIO->DIRCLR[PIN_PIO_PORT] = PIN_HW_VERS_6_MASK; + GPIO->DIRCLR[PIN_PIO_PORT] = PIN_HW_VERS_7_MASK; + + // Configure pins for board detection + IOCON->PIO[PIN_HW_VERS_3_PORT][PIN_HW_VERS_3] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; + IOCON->PIO[PIN_HW_VERS_4_PORT][PIN_HW_VERS_4] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; + GPIO->DIRCLR[PIN_HW_VERS_3_PORT] = PIN_HW_VERS_3_MASK; + GPIO->DIRCLR[PIN_HW_VERS_4_PORT] = PIN_HW_VERS_4_MASK; + + if (GPIO->B[PIN_HW_VERS_4_PORT][PIN_HW_VERS_4] == 0 && GPIO->B[PIN_HW_VERS_3_PORT][PIN_HW_VERS_3] != 0) { + s_mcu_link_pro = true; + + GPIO->B[LED_B_PORT][LED_B_PIN] = 1; + GPIO->B[LED_C_PORT][LED_C_PIN] = 1; + GPIO->B[LED_D_PORT][LED_D_PIN] = 1; + GPIO->B[LED_E_PORT][LED_E_PIN] = 1; + GPIO->B[LED_F_PORT][LED_F_PIN] = 1; + GPIO->B[LED_G_PORT][LED_G_PIN] = 1; + + IOCON->PIO[LED_B_PORT][LED_B_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; + IOCON->PIO[LED_C_PORT][LED_C_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; + IOCON->PIO[LED_D_PORT][LED_D_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; + IOCON->PIO[LED_E_PORT][LED_E_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; + IOCON->PIO[LED_F_PORT][LED_F_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; + IOCON->PIO[LED_G_PORT][LED_G_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; + + GPIO->DIRSET[LED_B_PORT] = LED_B_MASK; + GPIO->DIRSET[LED_C_PORT] = LED_C_MASK; + GPIO->DIRSET[LED_D_PORT] = LED_D_MASK; + GPIO->DIRSET[LED_E_PORT] = LED_E_MASK; + GPIO->DIRSET[LED_F_PORT] = LED_F_MASK; + GPIO->DIRSET[LED_G_PORT] = LED_G_MASK; + +#if defined(DAPLINK_IF) && defined(MCU_LINK_PRO_GREETING) + uint8_t j = 0; + for (uint8_t i = 0; i < 7; i++) { + osDelay(15); + j = (j << 1 | 1); + gpio_set_leds(j, GPIO_LED_ON); + } + osDelay(15); + gpio_set_leds(j, GPIO_LED_OFF); +#endif + } +} + +__WEAK void gpio_set_leds(uint32_t leds, gpio_led_state_t state) +{ + // LED is active low, so set to inverse of the enum value. + if (s_mcu_link_pro) { + if (leds & LED_T_CONNECTED) { + GPIO->B[LED_A_PORT][LED_A_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); + } + if (leds & LED_T_RUNNING) { + GPIO->B[LED_B_PORT][LED_B_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); + } + if (leds & LED_T_HID) { + GPIO->B[LED_C_PORT][LED_C_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); + } + if (leds & LED_T_CDC) { + GPIO->B[LED_D_PORT][LED_D_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); + } + if (leds & LED_T_MSC) { + GPIO->B[LED_E_PORT][LED_E_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); + } + if (leds & LED_T_EXTRA1) { + GPIO->B[LED_F_PORT][LED_F_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); + } + if (leds & LED_T_EXTRA2) { + GPIO->B[LED_G_PORT][LED_G_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); + } + } else if (leds & (LED_T_CONNECTED | LED_T_HID | LED_T_CDC | LED_T_MSC)) { + GPIO->B[LED_A_PORT][LED_A_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); + } +} + + +uint8_t gpio_get_reset_btn_no_fwrd(void) +{ + return (PIN_nRESET_IN() && GPIO->B[PIN_PIO_PORT][PIN_HW_VERS_6]) ? 0 : 1; +} + +uint8_t gpio_get_reset_btn_fwrd(void) +{ + return GPIO->B[PIN_PIO_PORT][PIN_HW_VERS_7] ? 0 : 1; +} diff --git a/source/hic_hal/nxp/lpc55xx/gpio.c b/source/hic_hal/nxp/lpc55xx/gpio.c index 9b1b0ffc0..c351c0459 100644 --- a/source/hic_hal/nxp/lpc55xx/gpio.c +++ b/source/hic_hal/nxp/lpc55xx/gpio.c @@ -1,6 +1,6 @@ /** * @file gpio.c - * @brief GPIO handling for LPC55xx HIC, MCU-LINK and MCU-LINK-PRO + * @brief GPIO handling for LPC55xx * * DAPLink Interface Firmware * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved @@ -28,11 +28,11 @@ #include "fsl_clock.h" #include "fsl_iocon.h" #include "fsl_reset.h" -#include "cmsis_os2.h" -#ifdef MCU_LINK_SUPPORT -static bool s_mcu_link_pro = false; -#endif +__WEAK void board_gpio_init(void) +{ + // Nothing by default +} void gpio_init(void) { @@ -45,11 +45,7 @@ void gpio_init(void) // Ensure clocks are enabled. SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_IOCON_MASK - | SYSCON_AHBCLKCTRL0_GPIO0_MASK -#ifdef MCU_LINK_SUPPORT - | SYSCON_AHBCLKCTRL0_GPIO1_MASK -#endif - ; + | SYSCON_AHBCLKCTRL0_GPIO0_MASK; SYSCON->AHBCLKCTRLSET[1] = SYSCON_AHBCLKCTRL1_FC0_MASK | SYSCON_AHBCLKCTRL1_FC3_MASK; @@ -63,6 +59,9 @@ void gpio_init(void) IOCON->PIO[LED_A_PORT][LED_A_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; IOCON->PIO[PIN_PIO_PORT][PIN_RESET] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; + // Set RESET to input + GPIO->DIRCLR[PIN_PIO_PORT] = PIN_RESET_MASK; + // Turn off LED. GPIO->B[LED_A_PORT][LED_A_PIN] = 1; @@ -72,63 +71,7 @@ void gpio_init(void) // Turn on LED. GPIO->B[LED_A_PORT][LED_A_PIN] = 0; - // Set RESET to input - GPIO->DIRCLR[PIN_PIO_PORT] = PIN_RESET_MASK; - - -#ifdef MCU_LINK_SUPPORT - RESET_PeripheralReset(kGPIO1_RST_SHIFT_RSTn); - - // Configure additonal - IOCON->PIO[PIN_PIO_PORT][PIN_HW_VERS_6] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; - IOCON->PIO[PIN_PIO_PORT][PIN_HW_VERS_7] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; - // Configure pins for board detection - IOCON->PIO[PIN_HW_VERS_3_PORT][PIN_HW_VERS_3] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; - IOCON->PIO[PIN_HW_VERS_4_PORT][PIN_HW_VERS_4] = IOCON_FUNC0 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_OPENDRAIN_EN; - - GPIO->DIRCLR[PIN_HW_VERS_3_PORT] = PIN_HW_VERS_3_MASK; - GPIO->DIRCLR[PIN_HW_VERS_4_PORT] = PIN_HW_VERS_4_MASK; - GPIO->DIRCLR[PIN_PIO_PORT] = PIN_HW_VERS_6_MASK; - GPIO->DIRCLR[PIN_PIO_PORT] = PIN_HW_VERS_7_MASK; - - if (GPIO->B[PIN_HW_VERS_4_PORT][PIN_HW_VERS_4] == 0 && GPIO->B[PIN_HW_VERS_3_PORT][PIN_HW_VERS_3] != 0) { - s_mcu_link_pro = true; - - IOCON->PIO[LED_B_PORT][LED_B_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; - IOCON->PIO[LED_C_PORT][LED_C_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; - IOCON->PIO[LED_D_PORT][LED_D_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; - IOCON->PIO[LED_E_PORT][LED_E_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; - IOCON->PIO[LED_F_PORT][LED_F_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; - IOCON->PIO[LED_G_PORT][LED_G_PIN] = IOCON_FUNC0 | IOCON_DIGITAL_EN; - - GPIO->DIRSET[LED_B_PORT] = LED_B_MASK; - GPIO->DIRSET[LED_C_PORT] = LED_C_MASK; - GPIO->DIRSET[LED_D_PORT] = LED_D_MASK; - GPIO->DIRSET[LED_E_PORT] = LED_E_MASK; - GPIO->DIRSET[LED_F_PORT] = LED_F_MASK; - GPIO->DIRSET[LED_G_PORT] = LED_G_MASK; - - GPIO->B[LED_B_PORT][LED_B_PIN] = 1; - GPIO->B[LED_C_PORT][LED_C_PIN] = 1; - GPIO->B[LED_D_PORT][LED_D_PIN] = 1; - GPIO->B[LED_E_PORT][LED_E_PIN] = 1; - GPIO->B[LED_F_PORT][LED_F_PIN] = 1; - GPIO->B[LED_G_PORT][LED_G_PIN] = 1; - -#if defined(DAPLINK_IF) && defined(MCU_LINK_PRO_GREETING) - uint8_t j = 0; - for (uint8_t i = 0; i < 7; i++) { - osDelay(15); - j = (j << 1 | 1); - gpio_set_leds(j, GPIO_LED_ON); - } - osDelay(15); - gpio_set_leds(j, GPIO_LED_OFF); -#endif - } else { - // Disable GPIO1 clock? - } -#endif + board_gpio_init(); } void gpio_set_board_power(bool powerEnabled) @@ -136,40 +79,12 @@ void gpio_set_board_power(bool powerEnabled) // No target power control in this circuit. } -void gpio_set_leds(uint32_t leds, gpio_led_state_t state) +__WEAK void gpio_set_leds(uint32_t leds, gpio_led_state_t state) { // LED is active low, so set to inverse of the enum value. -#ifdef MCU_LINK_SUPPORT - if (s_mcu_link_pro) { - if (leds & LED_T_CONNECTED) { - GPIO->B[LED_A_PORT][LED_A_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); - } - if (leds & LED_T_RUNNING) { - GPIO->B[LED_B_PORT][LED_B_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); - } - if (leds & LED_T_HID) { - GPIO->B[LED_C_PORT][LED_C_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); - } - if (leds & LED_T_CDC) { - GPIO->B[LED_D_PORT][LED_D_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); - } - if (leds & LED_T_MSC) { - GPIO->B[LED_E_PORT][LED_E_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); - } - if (leds & LED_T_EXTRA1) { - GPIO->B[LED_F_PORT][LED_F_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); - } - if (leds & LED_T_EXTRA2) { - GPIO->B[LED_G_PORT][LED_G_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); - } - } else if (leds & (LED_T_CONNECTED | LED_T_HID | LED_T_CDC | LED_T_MSC)) { - GPIO->B[LED_A_PORT][LED_A_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); - } -#else if (leds & (LED_T_CONNECTED | LED_T_HID | LED_T_CDC | LED_T_MSC)) { GPIO->B[LED_A_PORT][LED_A_PIN] = (uint8_t)((state == GPIO_LED_ON) ? 0 : 1); } -#endif } void gpio_set_hid_led(gpio_led_state_t state) @@ -187,20 +102,12 @@ void gpio_set_msc_led(gpio_led_state_t state) gpio_set_leds(LED_T_MSC, state); } -uint8_t gpio_get_reset_btn_no_fwrd(void) +__WEAK uint8_t gpio_get_reset_btn_no_fwrd(void) { -#ifdef MCU_LINK_SUPPORT - return (PIN_nRESET_IN() && GPIO->B[PIN_PIO_PORT][PIN_HW_VERS_6]) ? 0 : 1; -#else return PIN_nRESET_IN() ? 0 : 1; -#endif } -uint8_t gpio_get_reset_btn_fwrd(void) +__WEAK uint8_t gpio_get_reset_btn_fwrd(void) { -#ifdef MCU_LINK_SUPPORT - return GPIO->B[PIN_PIO_PORT][PIN_HW_VERS_7] ? 0 : 1; -#else return 0; -#endif } From b46200320aee3ebaacf3dc805ea973b43b7313fd Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 9 Nov 2021 00:25:21 -0600 Subject: [PATCH 496/617] lpc55xx_hic: Add documentation for MCU-LINK and MCU-LINK-PRO support --- docs/hic/lpc55xx.md | 51 +++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 47 insertions(+), 4 deletions(-) diff --git a/docs/hic/lpc55xx.md b/docs/hic/lpc55xx.md index 046a98ecf..b9b59a78b 100644 --- a/docs/hic/lpc55xx.md +++ b/docs/hic/lpc55xx.md @@ -31,17 +31,60 @@ Reference design is based on [MCU-Link](https://www.nxp.com/design/development-b | SWDIO / TMS | I/O | PIO0_2 | 52 | | SWO / TDO | I | PIO0_3 | 53 | | TDI | O | PIO0_1 | 2 | -| nRESET | O | PIO0_19 | 58 | +| nRESET | I/O | PIO0_19 | 58 | | GNDDetect | I | PIO0_22 | 50 | | UART | | UART RX | I | PIO0_24 | 45 | | UART TX | O | PIO0_25 | 51 | -| Button | -| NF-RST But. | I | PIO0_18 | 38 | -| F-RST But. | I | PIO1_27 | 18 | | LEDs | | Con. LED | O | PIO0_5 | 56 | Additional pins are used to drive external circuitry: - SWDIO TX Enable (PIO0_28, pin 44) - nRESET Output Enable (PIO0_13, pin 46) + +## MCU-LINK and MCU-LINK-PRO support + +The `lpc55s69_mculink_bl` and `lpc55s69_mculink_if` images support both +MCU-LINK and MCU-LINK-PRO boards. Installation of the bootloader can be +done by putting the board in firmware update mode and using the NXP +`blhost` tool: + +``` +$ blhost --usb 0x1fc9,0x0021 flash-image lpc55s69_mculink_bl_crc.hex erase +``` + +### MCU-LINK "Buttoms" + +The MCU-LINK does not have amy buttons, but both board have "Disable VCOM" +and "Disable SWD" respectively mapped to non-forwarding reset and +forwarding reset functionality in DAPLink. + +| Signal | I/O | Symbol | Pin | +|-------------|:---:|---------|:---:| +| Button | +| NF-RST But. | I | PIO0_18 | 38 | +| F-RST But. | I | PIO0_27 | 18 | + +### MCU-LINK-PRO detection and LEDs + +The [MCU-LINK-PRO](https://www.nxp.com/design/microcontrollers-developer-resources/mcu-link-pro-debug-probe:MCU-LINK-PRO) +defines board type detection using `HW_VER_4` and `HW_VER_3`. When +`HW_VER_4` and `HW_VER_3` are respectively low and high, we determine that +the board is a MCU-LINK-PRO, otherwise we assume the board is a MCU-LINK. +MCU-LINK only has one red activity LED. MCU-LINK-PRO has 7 LEDs (1 red +and 6 green), 5 are currently used by DAPLink (see table below). + +| Signal | I/O | Symbol | +|---------------|:---:|---------| +| Detection | +| HW_VER_4 | I | PIO1_5 | +| HW_VER_3 | I | PIO1_4 | +| LEDs | +| Con. LED (r) | O | PIO0_5 | +| Run. LED (g) | O | PIO1_17 | +| HID LED (g) | O | PIO1_13 | +| CDC LED (g) | O | PIO1_18 | +| MSC LED (g) | O | PIO1_15 | +| N/A LED 1 (g) | O | PIO1_12 | +| N/A LED 2 (g) | O | PIO1_12 | From 2a58bbb8597bbf71a0a537b5c8edfaf235a21136 Mon Sep 17 00:00:00 2001 From: Martin Williams Date: Fri, 12 Nov 2021 07:11:02 +0000 Subject: [PATCH 497/617] Improved power IRQ handling --- source/board/microbitv2/nrf52820/power.c | 72 ++++++++++++++-------- source/board/microbitv2/nrf52820/pwr_mon.c | 1 - 2 files changed, 48 insertions(+), 25 deletions(-) diff --git a/source/board/microbitv2/nrf52820/power.c b/source/board/microbitv2/nrf52820/power.c index 276b378bc..814f3501a 100644 --- a/source/board/microbitv2/nrf52820/power.c +++ b/source/board/microbitv2/nrf52820/power.c @@ -40,6 +40,10 @@ static void power_after(); static void power_systemoff(); static void power_wfi(); +static void power_gpio_set_sense(NRF_GPIO_Type *reg, uint32_t idx, nrf_gpio_pin_sense_t sense); + +static void power_gpio_set_sense_from_read(NRF_GPIO_Type *reg, uint32_t idx); + void GPIOTE_IRQHandler(void); @@ -66,10 +70,10 @@ void power_init() gpio_cfg_input(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON), NRF_GPIO_PIN_NOPULL); // Configure VBUS_ABSENT (WAKE_ON_EDGE) pin to detect USB attach/detach */ - gpio_cfg(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT), - NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, - GPIO_PIN_CNF_SENSE_Low | GPIO_PIN_CNF_SENSE_High); + gpio_cfg_input(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT), NRF_GPIO_PIN_NOPULL); + power_gpio_set_sense_from_read(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT)); + NRF_GPIOTE->EVENTS_PORT = 0; NRF_GPIOTE->INTENSET = power_gpiote_intenset | ( GPIOTE_INTENSET_PORT_Set << GPIOTE_INTENSET_PORT_Pos); NVIC_EnableIRQ(GPIOTE_IRQn); } @@ -110,19 +114,14 @@ static void power_before(bool systemoff) NRF_GPIOTE->INTENCLR = NRF_GPIOTE->INTENSET; // Configure VBUS_ABSENT (WAKE_ON_EDGE) pin to detect USB attach */ - gpio_cfg(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT), - NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, - GPIO_PIN_CNF_SENSE_Low); + power_gpio_set_sense(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT), NRF_GPIO_PIN_SENSE_LOW); // Enable IRQ from RESET_BUTTON - gpio_cfg(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON), - NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, - GPIO_PIN_CNF_SENSE_Low); + power_gpio_set_sense(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON), NRF_GPIO_PIN_SENSE_LOW); + NRF_GPIOTE->EVENTS_PORT = 0; NRF_GPIOTE->INTENSET = power_gpiote_intenset | ( GPIOTE_INTENSET_PORT_Set << GPIOTE_INTENSET_PORT_Pos); NVIC_EnableIRQ(GPIOTE_IRQn); - - wake_from_usb = 0; } static void power_after() @@ -131,22 +130,26 @@ static void power_after() if (!power_gpiote_enabled) { NVIC_DisableIRQ(GPIOTE_IRQn); } - NRF_GPIOTE->INTENSET = power_gpiote_intenset; + NRF_GPIOTE->INTENCLR = NRF_GPIOTE->INTENSET; // Configure VBUS_ABSENT (WAKE_ON_EDGE) pin to detect USB attach/detach */ - gpio_cfg(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT), - NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, - GPIO_PIN_CNF_SENSE_Low | GPIO_PIN_CNF_SENSE_High); + power_gpio_set_sense_from_read(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT)); // Disable RESET_BUTTON edge events - gpio_cfg_input(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON), NRF_GPIO_PIN_NOPULL); + power_gpio_set_sense(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON), NRF_GPIO_PIN_NOSENSE); + + NRF_GPIOTE->EVENTS_PORT = 0; + NRF_GPIOTE->INTENSET = power_gpiote_intenset; + if (power_gpiote_enabled) { + NVIC_EnableIRQ(GPIOTE_IRQn); + } /* Configure I/O pin SWCLK, SWDIO */ PORT_SWD_SETUP(); uart_initialize(); - i2c_deinitialize(); - i2c_initialize(); + // i2c_deinitialize(); + // i2c_initialize(); } @@ -165,23 +168,44 @@ static void power_wfi() } +static void power_gpio_set_sense(NRF_GPIO_Type *reg, uint32_t idx, nrf_gpio_pin_sense_t sense) { + reg->PIN_CNF[idx] = ( reg->PIN_CNF[idx] & ~GPIO_PIN_CNF_SENSE_Msk) | ( sense << GPIO_PIN_CNF_SENSE_Pos); + reg->LATCH = 1 << idx; +} + +static void power_gpio_set_sense_from_read(NRF_GPIO_Type *reg, uint32_t idx) { + uint32_t sense = gpio_read(reg, idx) ? NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH; + reg->PIN_CNF[idx] = ( reg->PIN_CNF[idx] & ~GPIO_PIN_CNF_SENSE_Msk) | ( sense << GPIO_PIN_CNF_SENSE_Pos); + reg->LATCH = 1 << idx; +} + void GPIOTE_IRQHandler(void) { if (NRF_GPIOTE->EVENTS_PORT) { NRF_GPIOTE->EVENTS_PORT = 0; - if (GPIO_REG(RESET_BUTTON)->LATCH & (1 << GPIO_IDX(RESET_BUTTON))) { - GPIO_REG(RESET_BUTTON)->LATCH &= ~(1 << GPIO_IDX(RESET_BUTTON)); + NRF_GPIO_Type *reg = GPIO_REG(RESET_BUTTON); + uint32_t idx = GPIO_IDX(RESET_BUTTON); + if (reg->LATCH & (1 << idx)) { + reg->LATCH = 1 << idx; // Disable RESET_BUTTON edge events - gpio_cfg_input(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON), NRF_GPIO_PIN_NOPULL); + power_gpio_set_sense(reg, idx, NRF_GPIO_PIN_NOSENSE); wake_from_reset = 1; } - if (GPIO_REG(PIN_VBUS_ABSENT)->LATCH & (1 << GPIO_IDX(PIN_VBUS_ABSENT))) { - GPIO_REG(PIN_VBUS_ABSENT)->LATCH &= ~(1 << GPIO_IDX(PIN_VBUS_ABSENT)); + reg = GPIO_REG(PIN_VBUS_ABSENT); + idx = GPIO_IDX(PIN_VBUS_ABSENT); + if (reg->LATCH & (1 << idx)) { + reg->LATCH = 1 << idx; + + bool absent = NRF_GPIO_PIN_SENSE_HIGH == ((reg->PIN_CNF[idx] & GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos); + + power_gpio_set_sense(reg, idx, absent ? NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH); + + power_source = pwr_mon_get_power_source(); // Read VBUS_ABSENT (WAKE_ON_EDGE) pin for detecting if board is USB powered - if ( gpio_read(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT))) { + if (absent) { /* Reset USB on cable detach (VBUS falling edge) */ USBD_Reset(); usbd_reset_core(); diff --git a/source/board/microbitv2/nrf52820/pwr_mon.c b/source/board/microbitv2/nrf52820/pwr_mon.c index 5a74f3329..7bafe64be 100644 --- a/source/board/microbitv2/nrf52820/pwr_mon.c +++ b/source/board/microbitv2/nrf52820/pwr_mon.c @@ -39,7 +39,6 @@ void pwr_mon_init(void) // Configure VMON_BAT and RUN_VBAT_SENSE gpio_cfg_output(GPIO_REG(PIN_RUN_VBAT_SENSE), GPIO_IDX(PIN_RUN_VBAT_SENSE)); gpio_cfg_input(GPIO_REG(PIN_VBAT_SENSE), GPIO_IDX(PIN_VBAT_SENSE), NRF_GPIO_PIN_NOPULL); - gpio_cfg_input(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT), NRF_GPIO_PIN_NOPULL); } From 7210e1dada8391072d2d6ab1fcadde733de20b52 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Fri, 12 Nov 2021 10:28:27 +0000 Subject: [PATCH 498/617] nrf52820_microbit: Protect the bootloader flash on every bootloader startup. The ACL module only protects the flash until the next reset, so this bit of code needs to run on every startup. --- source/board/nrf52820_microbit_bl.c | 11 +++++++++++ source/daplink/bootloader/main_bootloader.c | 7 +++++++ 2 files changed, 18 insertions(+) diff --git a/source/board/nrf52820_microbit_bl.c b/source/board/nrf52820_microbit_bl.c index 377b9548b..43de342a9 100644 --- a/source/board/nrf52820_microbit_bl.c +++ b/source/board/nrf52820_microbit_bl.c @@ -28,6 +28,7 @@ #include "target_family.h" #include "device.h" #include "gpio.h" +#include "nrf.h" // Warning - changing the interface start will break backwards compatibility COMPILER_ASSERT(DAPLINK_ROM_IF_START == 0x00008000); @@ -80,3 +81,13 @@ bool reset_button_pressed() } return btn_pressed; } + +bool board_bootloader_init() +{ + // Lock the bootloader flash, only protects until reset, + // so needs to be executed in the bootloader on every startup + uint8_t acl_region = 0; + NRF_ACL->ACL[acl_region].ADDR = DAPLINK_ROM_BL_START; + NRF_ACL->ACL[acl_region].SIZE = DAPLINK_ROM_BL_SIZE; + NRF_ACL->ACL[acl_region].PERM = ACL_ACL_PERM_WRITE_Disable << ACL_ACL_PERM_WRITE_Pos; +} diff --git a/source/daplink/bootloader/main_bootloader.c b/source/daplink/bootloader/main_bootloader.c index 74eeb85ca..385a0c5cc 100644 --- a/source/daplink/bootloader/main_bootloader.c +++ b/source/daplink/bootloader/main_bootloader.c @@ -105,6 +105,11 @@ __WEAK bool reset_button_pressed() return gpio_get_reset_btn(); } +__WEAK void board_bootloader_init() +{ + return; +} + // Timer task, set flags every 30mS and 90mS void timer_task_30mS(void * arg) { @@ -264,6 +269,8 @@ int main(void) gpio_init(); // init settings config_init(); + // Hook for custom boards initialisation + board_bootloader_init(); // check for invalid app image or rst button press. Should be checksum or CRC but NVIC validation is better than nothing. // If the interface has set the hold in bootloader setting don't jump to app From 9576326dabe46f34a9c020bf23da5c039036c91f Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Fri, 12 Nov 2021 14:20:03 +0000 Subject: [PATCH 499/617] nrf52820_microbit: Update func declaration args to remove compiler warnings. --- source/board/microbitv2/nrf52820/microbitv2_pins.h | 2 +- source/board/microbitv2/nrf52820/power.c | 8 ++++---- source/board/microbitv2/nrf52820/pwm.c | 7 +++---- source/board/microbitv2/nrf52820/pwr_mon.c | 2 +- source/board/microbitv2/nrf52820/pwr_mon_adc.h | 2 +- 5 files changed, 10 insertions(+), 11 deletions(-) diff --git a/source/board/microbitv2/nrf52820/microbitv2_pins.h b/source/board/microbitv2/nrf52820/microbitv2_pins.h index 3420c99b9..b0966b69c 100644 --- a/source/board/microbitv2/nrf52820/microbitv2_pins.h +++ b/source/board/microbitv2/nrf52820/microbitv2_pins.h @@ -78,6 +78,6 @@ COMPILER_ASSERT(GPIO_CHECK_PRESENT_NRF52820(NRF52820_PIN_VBUS_ABSENT)); #endif -void microbitv2_pins_init(); +void microbitv2_pins_init(void); #endif /* MICROBITV2_PINS_H_ */ diff --git a/source/board/microbitv2/nrf52820/power.c b/source/board/microbitv2/nrf52820/power.c index 814f3501a..f61d5eea6 100644 --- a/source/board/microbitv2/nrf52820/power.c +++ b/source/board/microbitv2/nrf52820/power.c @@ -36,9 +36,9 @@ static void power_before(bool systemoff); -static void power_after(); -static void power_systemoff(); -static void power_wfi(); +static void power_after(void); +static void power_systemoff(void); +static void power_wfi(void); static void power_gpio_set_sense(NRF_GPIO_Type *reg, uint32_t idx, nrf_gpio_pin_sense_t sense); @@ -164,7 +164,7 @@ static void power_wfi() { power_before(false /*systemoff*/); __WFI(); - power_after(false /*systemoff*/); + power_after(); } diff --git a/source/board/microbitv2/nrf52820/pwm.c b/source/board/microbitv2/nrf52820/pwm.c index 782e342ac..911654586 100644 --- a/source/board/microbitv2/nrf52820/pwm.c +++ b/source/board/microbitv2/nrf52820/pwm.c @@ -27,10 +27,9 @@ #include "pwm.h" -static void pwm_stop(); -static void pwm_start(); -static void pwm_configure(); -static void pwm_mark255(uint8_t duty); +static void pwm_stop(void); +static void pwm_start(void); +static void pwm_configure(void); #define PWM_TIMER NRF_TIMER3 #define PWM_IRQ TIMER3_IRQn diff --git a/source/board/microbitv2/nrf52820/pwr_mon.c b/source/board/microbitv2/nrf52820/pwr_mon.c index 7bafe64be..b1d898ce3 100644 --- a/source/board/microbitv2/nrf52820/pwr_mon.c +++ b/source/board/microbitv2/nrf52820/pwr_mon.c @@ -28,7 +28,7 @@ #include "pwr_mon.h" -uint32_t pwr_mon_get_vbat_mv_imp(); +uint32_t pwr_mon_get_vbat_mv_imp(uint32_t max_us, uint32_t max_mv); static uint32_t pwr_mon_comp_mv(uint32_t psel, uint32_t vref, uint32_t *comps_count); diff --git a/source/board/microbitv2/nrf52820/pwr_mon_adc.h b/source/board/microbitv2/nrf52820/pwr_mon_adc.h index edf6b5365..3e1def697 100644 --- a/source/board/microbitv2/nrf52820/pwr_mon_adc.h +++ b/source/board/microbitv2/nrf52820/pwr_mon_adc.h @@ -31,7 +31,7 @@ extern "C" { * Measures VDDH voltage using SAADC peripheral * @return Voltage in millivolts. */ -uint32_t pwr_mon_adc_vin(); +uint32_t pwr_mon_adc_vin(void); #ifdef __cplusplus From 33cd494878defe9e615464d5418dea41d552cc10 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Sat, 13 Nov 2021 00:03:23 +0000 Subject: [PATCH 500/617] nrf52820_microbit: Improve I2C buffer clearing and sleep scheduling. When the TX buffer is filled to send the "reset button long press" user event to the target, the device was going to sleep and that somehow affected the target being able to do the I2C read from the IF. Adding the `i2c_allow_sleep = false` in `i2c_fillBuffer()` fixes that. --- source/board/microbitv2/microbitv2.c | 4 +- source/board/microbitv2/nrf52820/i2c.c | 65 +++++++++++++------------- 2 files changed, 36 insertions(+), 33 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 8ae801f8a..fb53ac1d8 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -153,7 +153,8 @@ static mb_version_t read_brd_rev_id(void) { board_version = BOARD_VERSION_2_DEF; } - return board_version; + return BOARD_VERSION_2_0; + //return board_version; } #elif defined(INTERFACE_NRF52820) @@ -245,6 +246,7 @@ void handle_reset_button() if (!reset_pressed && (gpio_get_reset_btn_fwrd() || wake_from_reset)) { // Reset button pressed target_set_state(RESET_PROGRAM); + i2c_clearBuffers(); reset_pressed = 1; gpio_reset_count = 0; wake_from_reset = 0; diff --git a/source/board/microbitv2/nrf52820/i2c.c b/source/board/microbitv2/nrf52820/i2c.c index 9fb219020..e6c58a70b 100644 --- a/source/board/microbitv2/nrf52820/i2c.c +++ b/source/board/microbitv2/nrf52820/i2c.c @@ -61,52 +61,51 @@ static callbackToExecute_t callbackToExecute = { .size = 0, }; -static bool g_schedule_clear_tx_buffer = false; - // TODO: This can probably be combined with the busy state for simpler sleep config extern uint8_t i2c_wake_timeout; static bool i2c_allow_sleep = true; -static i2c_status_t i2c_scheduleCallback(i2cCallback_t callback, uint8_t* pData, uint8_t size) +static void i2c_scheduleCallback(i2cCallback_t callback, uint8_t* pData, uint8_t size) { - if (callbackToExecute.pfCallback != NULL) { - return I2C_STATUS_FAIL; - } callbackToExecute.pfCallback = callback; callbackToExecute.pData = pData; callbackToExecute.size = size; // Raise event so that `board_custom_event()` gets called in the main task main_board_event(); - - return I2C_STATUS_SUCCESS; } // Hook function executed in the main task void board_custom_event() { - if (g_schedule_clear_tx_buffer) { - debug_i2c_data((uint8_t *)"[clTxBf]\n", 9); - memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); - g_schedule_clear_tx_buffer = false; - } + i2cCallback_t evtCallback = NULL; if (callbackToExecute.pfCallback != NULL) { debug_i2c_data((uint8_t *)"[clbk]\n", 7); callbackToExecute.pfCallback(callbackToExecute.pData, callbackToExecute.size); + + // Clear the callback data + evtCallback = callbackToExecute.pfCallback; // Save for later + callbackToExecute.pfCallback = NULL; + callbackToExecute.pData = NULL; + callbackToExecute.size = 0; + + i2c_allow_sleep = true; } - callbackToExecute.pfCallback = NULL; - callbackToExecute.pData = NULL; - callbackToExecute.size = 0; - i2c_allow_sleep = true; + // Clear TX buffer after a TX callback + if ((pfReadCommsCallback != NULL && evtCallback == pfReadCommsCallback) || + (pfReadFlashCallback != NULL && evtCallback == pfReadFlashCallback)) { + debug_i2c_data((uint8_t *)"[clrTx]\n", 8); + memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); + } } static void i2c_signalEvent(uint32_t event) { static uint32_t prev_event = 0; - debug_i2c_printf("evt[%d] ", event); + // debug_i2c_printf("evt[%d] ", event); if ((event & ARM_I2C_EVENT_TRANSFER_INCOMPLETE) || /* Less data was transferred than requested */ (event & ARM_I2C_EVENT_ADDRESS_NACK) || /* Slave address was not acknowledged */ @@ -117,16 +116,17 @@ static void i2c_signalEvent(uint32_t event) { } if (event & ARM_I2C_EVENT_TRANSFER_DONE) { - debug_i2c_data((uint8_t *)"d ", 1); + // debug_i2c_data((uint8_t *)"[d", 2); i2c_allow_sleep = false; if (prev_event & ARM_I2C_EVENT_SLAVE_RECEIVE) { int32_t data_count = I2Cdrv->GetDataCount(); - debug_i2c_printf("[rx][%d] %02x %02x ", data_count, g_slave_RX_buff[0], g_slave_RX_buff[1]); + debug_i2c_printf("[rx][%d] ", data_count); + // for (int i = 0; i < data_count; i++) debug_i2c_printf("%02x ", g_slave_RX_buff[i]); + debug_i2c_data((uint8_t *)"\n", 1); // Ignore NOP commands and 0 length transmissions if ((data_count != 0) && (g_slave_RX_buff[0] != gNopCmd_c)) { - g_schedule_clear_tx_buffer = true; if (event & EXTENSION_I2C_EVENT_SLAVE_ADDR_0) { i2c_scheduleCallback(pfWriteCommsCallback, &g_slave_RX_buff[0], data_count); } else if (event & EXTENSION_I2C_EVENT_SLAVE_ADDR_1) { @@ -136,7 +136,8 @@ static void i2c_signalEvent(uint32_t event) { } else if (prev_event & ARM_I2C_EVENT_SLAVE_TRANSMIT) { int32_t data_count = I2Cdrv->GetDataCount(); debug_i2c_printf("[tx][%d] ", data_count); - for (int i = 0; i < 5; i++) debug_i2c_printf("%02x ", g_slave_TX_buff[i]); + // for (int i = 0; i < 5; i++) debug_i2c_printf("%02x ", g_slave_TX_buff[i]); + debug_i2c_data((uint8_t *)"\n", 1); if (event & EXTENSION_I2C_EVENT_SLAVE_ADDR_0) { i2c_scheduleCallback(pfReadCommsCallback, &g_slave_TX_buff[0], data_count); @@ -147,34 +148,29 @@ static void i2c_signalEvent(uint32_t event) { } if (event & ARM_I2C_EVENT_BUS_ERROR) { /* Invalid start/stop position detected */ - debug_i2c_data((uint8_t *)"E", 1); + debug_i2c_data((uint8_t *)"E\n", 2); } if (event & ARM_I2C_EVENT_GENERAL_CALL) { /* Slave was addressed with a general call address */ - debug_i2c_data((uint8_t *)"g", 1); + debug_i2c_data((uint8_t *)"g\n", 2); } if (event & ARM_I2C_EVENT_SLAVE_RECEIVE) { int32_t ret = I2Cdrv->SlaveReceive(&g_slave_RX_buff[0], I2C_DATA_LENGTH); i2c_wake_timeout = 4; // 4 * 30ms tick = 120ms timeout - debug_i2c_printf("rx[%d] ", ret); + // debug_i2c_printf("rx[%d]\n", ret); } if (event & ARM_I2C_EVENT_SLAVE_TRANSMIT) { int32_t ret = I2Cdrv->SlaveTransmit(&g_slave_TX_buff[0], I2C_DATA_LENGTH); i2c_wake_timeout = 4; // 4 * 30ms tick = 120ms timeout - debug_i2c_printf("tx[%d] ", ret); + // debug_i2c_printf("tx[%d]\n", ret); } - debug_i2c_data((uint8_t *)".\n", 2); + prev_event = event; } void i2c_initialize() { i2c_clearBuffers(); - callbackToExecute.pfCallback = NULL; - callbackToExecute.pData = NULL; - callbackToExecute.size = 0; - g_schedule_clear_tx_buffer = false; - i2c_allow_sleep = true; // I2C addresses configured via default values from RTE_Device.h I2Cdrv->Initialize(i2c_signalEvent); @@ -232,6 +228,10 @@ void i2c_clearBuffers() { memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); memset(&g_slave_RX_buff, 0, sizeof(g_slave_RX_buff)); + callbackToExecute.pfCallback = NULL; + callbackToExecute.pData = NULL; + callbackToExecute.size = 0; + i2c_allow_sleep = true; } void i2c_fillBuffer(uint8_t* data, uint32_t position, uint32_t size) @@ -243,6 +243,7 @@ void i2c_fillBuffer(uint8_t* data, uint32_t position, uint32_t size) for (uint32_t i = 0; i < size; i++) { g_slave_TX_buff[position + i] = data[i]; } + i2c_allow_sleep = false; } bool i2c_isBusy() From ca591a435eee00f3493fe7da6c86abc714f0348f Mon Sep 17 00:00:00 2001 From: djix123 Date: Fri, 12 Nov 2021 22:50:54 -0500 Subject: [PATCH 501/617] Add support for Pitaya Link probe (#896) Add support for Pitaya Link probe - copied over from makerdiary fork Co-authored-by: Jonathan Giles --- projects.yaml | 4 ++++ records/board/pitaya_link.yaml | 7 +++++++ source/board/pitaya_link.c | 37 ++++++++++++++++++++++++++++++++++ test/info.py | 2 ++ 4 files changed, 50 insertions(+) create mode 100644 records/board/pitaya_link.yaml create mode 100644 source/board/pitaya_link.c diff --git a/projects.yaml b/projects.yaml index ef3a94360..b834358fa 100644 --- a/projects.yaml +++ b/projects.yaml @@ -418,6 +418,10 @@ projects: - *module_if - *module_hic_lpc11u35 - records/board/nz32_sc151.yaml + lpc11u35_pitaya_link_if: + - *module_if + - *module_hic_lpc11u35 + - records/board/pitaya_link.yaml lpc11u35_rtl8195am_if: - *module_if - *module_hic_lpc11u35 diff --git a/records/board/pitaya_link.yaml b/records/board/pitaya_link.yaml new file mode 100644 index 000000000..708297501 --- /dev/null +++ b/records/board/pitaya_link.yaml @@ -0,0 +1,7 @@ +common: + sources: + board: + - source/board/pitaya_link.c + family: + - source/family/nordic/nrf52/target.c + - source/family/nordic/target_reset_nrf52.c diff --git a/source/board/pitaya_link.c b/source/board/pitaya_link.c new file mode 100644 index 000000000..0d9e06f42 --- /dev/null +++ b/source/board/pitaya_link.c @@ -0,0 +1,37 @@ +/** + * @file pitaya_link.c + * @brief board file for Pitaya-Link targeting nRF52 SoC + * + * DAPLink Interface Firmware + * Copyright (c) 2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_family.h" +#include "target_board.h" + +extern target_cfg_t target_device_nrf52840; + +const board_info_t g_board_info = { + .info_version = kBoardInfoVersion, + .board_id = "1028", + .family_id = kNordic_Nrf52_FamilyID, + .daplink_url_name = "PRODINFOHTM", + .daplink_drive_name = "PITAYA-LINK", + .daplink_target_url = "https://wiki.makerdiary.com/pitaya-link/", + .target_cfg = &target_device_nrf52840, + .board_vendor = "makerdiary", + .board_name = "Pitaya-Link", +}; diff --git a/test/info.py b/test/info.py index 22e9b9d94..683b35fe4 100644 --- a/test/info.py +++ b/test/info.py @@ -104,6 +104,7 @@ ('nrf52820_if', False, 0x0000, "bin" ), ('sam3u2c_if', False, 0x0000, "bin" ), ('stm32f103xb_if', False, 0x0000, "bin" ), + ('lpc11u35_pitaya_link_if', False, 0x0000, "bin" ), } # Add new HICs here @@ -174,6 +175,7 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x1018, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_ssci824_if', None, 'Switch-Science-mbed-LPC824' ), ( 0x1019, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_sscity_if', None, 'Switch-Science-mbed-TY51822r3' ), ( 0x1021, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_ssci_chibi_if', None, None ), # TODO - set target to 'SSCI-MBIT' when mbed-os supports this + ( 0x1028, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_pitaya_link_if', None, None ), ( 0x1050, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_lpc812xpresso_if', None, 'NXP-LPC800-MAX' ), ( 0x1054, VENDOR_TO_FAMILY('Stub', 1), 'lpc4322_lpc54114xpresso_if', 'lpc4322_bl', 'LPCXpresso54114' ), ( 0x1056, VENDOR_TO_FAMILY('Stub', 1), 'lpc4322_lpc54608xpresso_if', 'lpc4322_bl', 'LPCXpresso54608' ), From 35919e93679c949e5ff0760a227bbdfff21a04ef Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 22 Nov 2021 18:44:57 -0600 Subject: [PATCH 502/617] settings: restore zero_init attribute for config_ram (#901) --- source/daplink/settings/settings.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/source/daplink/settings/settings.c b/source/daplink/settings/settings.c index c51c85085..6553e18f6 100644 --- a/source/daplink/settings/settings.c +++ b/source/daplink/settings/settings.c @@ -66,7 +66,12 @@ typedef struct __attribute__((__packed__)) cfg_ram { COMPILER_ASSERT((offsetof(cfg_ram_t, hexdump) % sizeof(uint32_t)) == 0); // Configuration RAM +#if defined(__ARMCC) +static cfg_ram_t config_ram __attribute__((section("cfgram"), zero_init)); +#else static cfg_ram_t config_ram __attribute__((section("cfgram"))); +#endif + // Ram copy of RAM config static cfg_ram_t config_ram_copy; From 8df64c34d626b86256117a66f4435c4a3abd648f Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 23 Nov 2021 09:53:39 -0600 Subject: [PATCH 503/617] debug: add RTT output support (#899) --- source/daplink/daplink_debug.c | 90 + source/daplink/daplink_debug.h | 62 +- source/daplink/debug/LICENSE.md | 36 + source/daplink/debug/SEGGER_RTT.c | 2085 ++++++++++++++++++++++++ source/daplink/debug/SEGGER_RTT.h | 488 ++++++ source/daplink/debug/SEGGER_RTT_Conf.h | 424 +++++ 6 files changed, 3131 insertions(+), 54 deletions(-) create mode 100644 source/daplink/daplink_debug.c create mode 100644 source/daplink/debug/LICENSE.md create mode 100644 source/daplink/debug/SEGGER_RTT.c create mode 100644 source/daplink/debug/SEGGER_RTT.h create mode 100644 source/daplink/debug/SEGGER_RTT_Conf.h diff --git a/source/daplink/daplink_debug.c b/source/daplink/daplink_debug.c new file mode 100644 index 000000000..22c330ff8 --- /dev/null +++ b/source/daplink/daplink_debug.c @@ -0,0 +1,90 @@ +/** + * @file daplink_debug.c + * @brief optional trace messages useful in development + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2021, Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include +#include "cmsis_os2.h" +#include "rl_usb.h" +#include "util.h" + +#if defined (DAPLINK_DEBUG) + +#if defined (DAPLINK_DEBUG_RTT) + +#include "debug/SEGGER_RTT.c" + +uint32_t daplink_debug(uint8_t *buf, uint32_t size) +{ + return SEGGER_RTT_Write(0, buf, size); +} + +#else + +static const char error_msg[] = "\r\n\r\n"; + +uint32_t daplink_debug(uint8_t *buf, uint32_t size) +{ + uint32_t total_free; + uint32_t write_free; + uint32_t error_len = strlen(error_msg); + total_free = USBD_CDC_ACM_DataFree(); + + if (total_free < error_len) { + // No space + return 0; + } + + // Size available for writing + write_free = total_free - error_len; + size = MIN(write_free, size); + USBD_CDC_ACM_DataSend(buf, size); + + if (write_free == size) { + USBD_CDC_ACM_DataSend((uint8_t *)error_msg, error_len); + } + + return size; +} +#endif + +static char daplink_debug_buf[128] = {0}; +uint32_t daplink_debug_print(const char *format, ...) +{ + uint32_t ret; + int32_t r = 0; + va_list arg; + ret = 1; + va_start(arg, format); + r = vsnprintf(daplink_debug_buf, sizeof(daplink_debug_buf), format, arg); + + if (r >= sizeof(daplink_debug_buf)) { + r = snprintf(daplink_debug_buf, sizeof(daplink_debug_buf), "\r\n", r); + ret = 0; + } + + va_end(arg); + daplink_debug((uint8_t *)daplink_debug_buf, r); + return ret; +} + +#endif \ No newline at end of file diff --git a/source/daplink/daplink_debug.h b/source/daplink/daplink_debug.h index 3fa67aec0..ed8a7055d 100644 --- a/source/daplink/daplink_debug.h +++ b/source/daplink/daplink_debug.h @@ -3,7 +3,7 @@ * @brief optional trace messages useful in development * * DAPLink Interface Firmware - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2021, Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -26,65 +26,19 @@ #include #include #include -#include "cmsis_os2.h" -#include "rl_usb.h" -#include "util.h" #ifdef __cplusplus extern "C" { #endif -#ifndef MSC_DEBUG -//#define MSC_DEBUG +#ifndef DAPLINK_DEBUG +// #define DAPLINK_DEBUG #endif -#if defined (MSC_DEBUG) +#if defined (DAPLINK_DEBUG) -static const char error_msg[] = "\r\n\r\n"; - -static inline uint32_t daplink_debug(uint8_t *buf, uint32_t size) -{ - uint32_t total_free; - uint32_t write_free; - uint32_t error_len = strlen(error_msg); - total_free = USBD_CDC_ACM_DataFree(); - - if (total_free < error_len) { - // No space - return 0; - } - - // Size available for writing - write_free = total_free - error_len; - size = MIN(write_free, size); - USBD_CDC_ACM_DataSend(buf, size); - - if (write_free == size) { - USBD_CDC_ACM_DataSend((uint8_t *)error_msg, error_len); - } - - return size; -} - -static char daplink_debug_buf[128] = {0}; -static inline uint32_t daplink_debug_print(const char *format, ...) -{ - uint32_t ret; - int32_t r = 0; - va_list arg; - ret = 1; - va_start(arg, format); - r = vsnprintf(daplink_debug_buf, sizeof(daplink_debug_buf), format, arg); - - if (r >= sizeof(daplink_debug_buf)) { - r = snprintf(daplink_debug_buf, sizeof(daplink_debug_buf), "\r\n", r); - ret = 0; - } - - va_end(arg); - daplink_debug((uint8_t *)daplink_debug_buf, r); - return ret; -} +uint32_t daplink_debug_print(const char *format, ...); +uint32_t daplink_debug(uint8_t *data, uint32_t size); #else @@ -103,8 +57,8 @@ static inline uint32_t daplink_debug(uint8_t *data, uint32_t size) #define debug_msg(fmt, args...) daplink_debug_print(fmt, ## args); #define debug_data(buf, size) daplink_debug(buf, size); -#ifdef __cplusplus -} #endif +#ifdef __cplusplus +} #endif diff --git a/source/daplink/debug/LICENSE.md b/source/daplink/debug/LICENSE.md new file mode 100644 index 000000000..14881c29b --- /dev/null +++ b/source/daplink/debug/LICENSE.md @@ -0,0 +1,36 @@ + + SEGGER Microcontroller GmbH + The Embedded Experts + + (c) 1995 - 2021 SEGGER Microcontroller GmbH + www.segger.com Support: support@segger.com + + SEGGER RTT Real Time Transfer for embedded targets + + + All rights reserved. + + SEGGER strongly recommends to not make any changes + to or modify the source code of this software in order to stay + compatible with the RTT protocol and J-Link. + + Redistribution and use in source and binary forms, with or + without modification, are permitted provided that the following + condition is met: + + - Redistributions of source code must retain the above copyright + notice, this condition and the following disclaimer. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR + ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + DAMAGE. diff --git a/source/daplink/debug/SEGGER_RTT.c b/source/daplink/debug/SEGGER_RTT.c new file mode 100644 index 000000000..de31ec84f --- /dev/null +++ b/source/daplink/debug/SEGGER_RTT.c @@ -0,0 +1,2085 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 1995 - 2019 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the RTT protocol and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT.c +Purpose : Implementation of SEGGER real-time transfer (RTT) which + allows real-time communication on targets which support + debugger memory accesses while the CPU is running. +Revision: $Rev: 24715 $ + +Additional information: + Type "int" is assumed to be 32-bits in size + H->T Host to target communication + T->H Target to host communication + + RTT channel 0 is always present and reserved for Terminal usage. + Name is fixed to "Terminal" + + Effective buffer size: SizeOfBuffer - 1 + + WrOff == RdOff: Buffer is empty + WrOff == (RdOff - 1): Buffer is full + WrOff > RdOff: Free space includes wrap-around + WrOff < RdOff: Used space includes wrap-around + (WrOff == (SizeOfBuffer - 1)) && (RdOff == 0): + Buffer full and wrap-around after next byte + + +---------------------------------------------------------------------- +*/ + +#include "SEGGER_RTT.h" + +#include // for memcpy + +/********************************************************************* +* +* Configuration, default values +* +********************************************************************** +*/ + +#if SEGGER_RTT_CPU_CACHE_LINE_SIZE + #ifdef SEGGER_RTT_CB_ALIGN + #error "Custom SEGGER_RTT_CB_ALIGN() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" + #endif + #ifdef SEGGER_RTT_BUFFER_ALIGN + #error "Custom SEGGER_RTT_BUFFER_ALIGN() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" + #endif + #ifdef SEGGER_RTT_PUT_CB_SECTION + #error "Custom SEGGER_RTT_PUT_CB_SECTION() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" + #endif + #ifdef SEGGER_RTT_PUT_BUFFER_SECTION + #error "Custom SEGGER_RTT_PUT_BUFFER_SECTION() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" + #endif + #ifdef SEGGER_RTT_BUFFER_ALIGNMENT + #error "Custom SEGGER_RTT_BUFFER_ALIGNMENT is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" + #endif + #ifdef SEGGER_RTT_ALIGNMENT + #error "Custom SEGGER_RTT_ALIGNMENT is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" + #endif +#endif + +#ifndef BUFFER_SIZE_UP + #define BUFFER_SIZE_UP 1024 // Size of the buffer for terminal output of target, up to host +#endif + +#ifndef BUFFER_SIZE_DOWN + #define BUFFER_SIZE_DOWN 16 // Size of the buffer for terminal input to target from host (Usually keyboard input) +#endif + +#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS + #define SEGGER_RTT_MAX_NUM_UP_BUFFERS 2 // Number of up-buffers (T->H) available on this target +#endif + +#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS + #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS 2 // Number of down-buffers (H->T) available on this target +#endif + +#ifndef SEGGER_RTT_BUFFER_SECTION + #if defined(SEGGER_RTT_SECTION) + #define SEGGER_RTT_BUFFER_SECTION SEGGER_RTT_SECTION + #endif +#endif + +#ifndef SEGGER_RTT_ALIGNMENT + #define SEGGER_RTT_ALIGNMENT SEGGER_RTT_CPU_CACHE_LINE_SIZE +#endif + +#ifndef SEGGER_RTT_BUFFER_ALIGNMENT + #define SEGGER_RTT_BUFFER_ALIGNMENT SEGGER_RTT_CPU_CACHE_LINE_SIZE +#endif + +#ifndef SEGGER_RTT_MODE_DEFAULT + #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP +#endif + +#ifndef SEGGER_RTT_LOCK + #define SEGGER_RTT_LOCK() +#endif + +#ifndef SEGGER_RTT_UNLOCK + #define SEGGER_RTT_UNLOCK() +#endif + +#ifndef STRLEN + #define STRLEN(a) strlen((a)) +#endif + +#ifndef STRCPY + #define STRCPY(pDest, pSrc) strcpy((pDest), (pSrc)) +#endif + +#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP + #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 +#endif + +#ifndef SEGGER_RTT_MEMCPY + #ifdef MEMCPY + #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) MEMCPY((pDest), (pSrc), (NumBytes)) + #else + #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) memcpy((pDest), (pSrc), (NumBytes)) + #endif +#endif + +#ifndef MIN + #define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef MAX + #define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +// +// For some environments, NULL may not be defined until certain headers are included +// +#ifndef NULL + #define NULL 0 +#endif + +/********************************************************************* +* +* Defines, fixed +* +********************************************************************** +*/ +#if (defined __ICCARM__) || (defined __ICCRX__) + #define RTT_PRAGMA(P) _Pragma(#P) +#endif + +#if SEGGER_RTT_ALIGNMENT || SEGGER_RTT_BUFFER_ALIGNMENT + #if ((defined __GNUC__) || (defined __clang__)) + #define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__ ((aligned (Alignment))) + #elif (defined __ICCARM__) || (defined __ICCRX__) + #define PRAGMA(A) _Pragma(#A) +#define SEGGER_RTT_ALIGN(Var, Alignment) RTT_PRAGMA(data_alignment=Alignment) \ + Var + #elif (defined __CC_ARM) + #define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__ ((aligned (Alignment))) + #else + #error "Alignment not supported for this compiler." + #endif +#else + #define SEGGER_RTT_ALIGN(Var, Alignment) Var +#endif + +#if defined(SEGGER_RTT_SECTION) || defined (SEGGER_RTT_BUFFER_SECTION) + #if ((defined __GNUC__) || (defined __clang__)) + #define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__ ((section (Section))) Var + #elif (defined __ICCARM__) || (defined __ICCRX__) +#define SEGGER_RTT_PUT_SECTION(Var, Section) RTT_PRAGMA(location=Section) \ + Var + #elif (defined __CC_ARM) + #define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__ ((section (Section), zero_init)) Var + #else + #error "Section placement not supported for this compiler." + #endif +#else + #define SEGGER_RTT_PUT_SECTION(Var, Section) Var +#endif + +#if SEGGER_RTT_ALIGNMENT + #define SEGGER_RTT_CB_ALIGN(Var) SEGGER_RTT_ALIGN(Var, SEGGER_RTT_ALIGNMENT) +#else + #define SEGGER_RTT_CB_ALIGN(Var) Var +#endif + +#if SEGGER_RTT_BUFFER_ALIGNMENT + #define SEGGER_RTT_BUFFER_ALIGN(Var) SEGGER_RTT_ALIGN(Var, SEGGER_RTT_BUFFER_ALIGNMENT) +#else + #define SEGGER_RTT_BUFFER_ALIGN(Var) Var +#endif + + +#if defined(SEGGER_RTT_SECTION) + #define SEGGER_RTT_PUT_CB_SECTION(Var) SEGGER_RTT_PUT_SECTION(Var, SEGGER_RTT_SECTION) +#else + #define SEGGER_RTT_PUT_CB_SECTION(Var) Var +#endif + +#if defined(SEGGER_RTT_BUFFER_SECTION) + #define SEGGER_RTT_PUT_BUFFER_SECTION(Var) SEGGER_RTT_PUT_SECTION(Var, SEGGER_RTT_BUFFER_SECTION) +#else + #define SEGGER_RTT_PUT_BUFFER_SECTION(Var) Var +#endif + +/********************************************************************* +* +* Static const data +* +********************************************************************** +*/ + +static unsigned char _aTerminalId[16] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' }; + +/********************************************************************* +* +* Static data +* +********************************************************************** +*/ + +// +// RTT Control Block and allocate buffers for channel 0 +// +#if SEGGER_RTT_CPU_CACHE_LINE_SIZE + #if ((defined __GNUC__) || (defined __clang__)) + SEGGER_RTT_CB _SEGGER_RTT __attribute__ ((aligned (SEGGER_RTT_CPU_CACHE_LINE_SIZE))); + static char _acUpBuffer [SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_UP)] __attribute__ ((aligned (SEGGER_RTT_CPU_CACHE_LINE_SIZE))); + static char _acDownBuffer[SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_DOWN)] __attribute__ ((aligned (SEGGER_RTT_CPU_CACHE_LINE_SIZE))); + #else + #error "Don't know how to place _SEGGER_RTT, _acUpBuffer, _acDownBuffer cache-line aligned" + #endif +#else + SEGGER_RTT_PUT_CB_SECTION(SEGGER_RTT_CB_ALIGN(SEGGER_RTT_CB _SEGGER_RTT)); + SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acUpBuffer [BUFFER_SIZE_UP])); + SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acDownBuffer[BUFFER_SIZE_DOWN])); +#endif + +static unsigned char _ActiveTerminal; + +/********************************************************************* +* +* Static functions +* +********************************************************************** +*/ + +/********************************************************************* +* +* _DoInit() +* +* Function description +* Initializes the control block an buffers. +* May only be called via INIT() to avoid overriding settings. +* +*/ +#define INIT() { \ + volatile SEGGER_RTT_CB* pRTTCBInit; \ + pRTTCBInit = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); \ + do { \ + if (pRTTCBInit->acID[0] == '\0') { \ + _DoInit(); \ + } \ + } while (0); \ + } + +static void _DoInit(void) { + volatile SEGGER_RTT_CB* p; // Volatile to make sure that compiler cannot change the order of accesses to the control block + static const char _aInitStr[] = "\0\0\0\0\0\0TTR REGGES"; // Init complete ID string to make sure that things also work if RTT is linked to a no-init memory area + unsigned i; + // + // Initialize control block + // + p = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly + memset((SEGGER_RTT_CB*)p, 0, sizeof(_SEGGER_RTT)); // Make sure that the RTT CB is always zero initialized. + p->MaxNumUpBuffers = SEGGER_RTT_MAX_NUM_UP_BUFFERS; + p->MaxNumDownBuffers = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS; + // + // Initialize up buffer 0 + // + p->aUp[0].sName = "Terminal"; + p->aUp[0].pBuffer = _acUpBuffer; + p->aUp[0].SizeOfBuffer = BUFFER_SIZE_UP; + p->aUp[0].RdOff = 0u; + p->aUp[0].WrOff = 0u; + p->aUp[0].Flags = SEGGER_RTT_MODE_DEFAULT; + // + // Initialize down buffer 0 + // + p->aDown[0].sName = "Terminal"; + p->aDown[0].pBuffer = _acDownBuffer; + p->aDown[0].SizeOfBuffer = BUFFER_SIZE_DOWN; + p->aDown[0].RdOff = 0u; + p->aDown[0].WrOff = 0u; + p->aDown[0].Flags = SEGGER_RTT_MODE_DEFAULT; + // + // Finish initialization of the control block. + // Copy Id string backwards to make sure that "SEGGER RTT" is not found in initializer memory (usually flash), + // as this would cause J-Link to "find" the control block at a wrong address. + // + RTT__DMB(); // Force order of memory accesses for cores that may perform out-of-order memory accesses + for (i = 0; i < sizeof(_aInitStr) - 1; ++i) { + p->acID[i] = _aInitStr[sizeof(_aInitStr) - 2 - i]; // Skip terminating \0 at the end of the array + } + RTT__DMB(); // Force order of memory accesses for cores that may perform out-of-order memory accesses +} + +/********************************************************************* +* +* _WriteBlocking() +* +* Function description +* Stores a specified number of characters in SEGGER RTT ring buffer +* and updates the associated write pointer which is periodically +* read by the host. +* The caller is responsible for managing the write chunk sizes as +* _WriteBlocking() will block until all data has been posted successfully. +* +* Parameters +* pRing Ring buffer to post to. +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* >= 0 - Number of bytes written into buffer. +*/ +static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer, unsigned NumBytes) { + unsigned NumBytesToWrite; + unsigned NumBytesWritten; + unsigned RdOff; + unsigned WrOff; + volatile char* pDst; + // + // Write data to buffer and handle wrap-around if necessary + // + NumBytesWritten = 0u; + WrOff = pRing->WrOff; + do { + RdOff = pRing->RdOff; // May be changed by host (debug probe) in the meantime + if (RdOff > WrOff) { + NumBytesToWrite = RdOff - WrOff - 1u; + } else { + NumBytesToWrite = pRing->SizeOfBuffer - (WrOff - RdOff + 1u); + } + NumBytesToWrite = MIN(NumBytesToWrite, (pRing->SizeOfBuffer - WrOff)); // Number of bytes that can be written until buffer wrap-around + NumBytesToWrite = MIN(NumBytesToWrite, NumBytes); + pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + NumBytesWritten += NumBytesToWrite; + NumBytes -= NumBytesToWrite; + WrOff += NumBytesToWrite; + while (NumBytesToWrite--) { + *pDst++ = *pBuffer++; + }; +#else + SEGGER_RTT_MEMCPY((void*)pDst, pBuffer, NumBytesToWrite); + NumBytesWritten += NumBytesToWrite; + pBuffer += NumBytesToWrite; + NumBytes -= NumBytesToWrite; + WrOff += NumBytesToWrite; +#endif + if (WrOff == pRing->SizeOfBuffer) { + WrOff = 0u; + } + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = WrOff; + } while (NumBytes); + return NumBytesWritten; +} + +/********************************************************************* +* +* _WriteNoCheck() +* +* Function description +* Stores a specified number of characters in SEGGER RTT ring buffer +* and updates the associated write pointer which is periodically +* read by the host. +* It is callers responsibility to make sure data actually fits in buffer. +* +* Parameters +* pRing Ring buffer to post to. +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Notes +* (1) If there might not be enough space in the "Up"-buffer, call _WriteBlocking +*/ +static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsigned NumBytes) { + unsigned NumBytesAtOnce; + unsigned WrOff; + unsigned Rem; + volatile char* pDst; + + WrOff = pRing->WrOff; + Rem = pRing->SizeOfBuffer - WrOff; + if (Rem > NumBytes) { + // + // All data fits before wrap around + // + pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + WrOff += NumBytes; + while (NumBytes--) { + *pDst++ = *pData++; + }; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = WrOff; +#else + SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytes); + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = WrOff + NumBytes; +#endif + } else { + // + // We reach the end of the buffer, so need to wrap around + // +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; + NumBytesAtOnce = Rem; + while (NumBytesAtOnce--) { + *pDst++ = *pData++; + }; + pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF; + NumBytesAtOnce = NumBytes - Rem; + while (NumBytesAtOnce--) { + *pDst++ = *pData++; + }; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = NumBytes - Rem; +#else + NumBytesAtOnce = Rem; + pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; + SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytesAtOnce); + NumBytesAtOnce = NumBytes - Rem; + pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF; + SEGGER_RTT_MEMCPY((void*)pDst, pData + Rem, NumBytesAtOnce); + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = NumBytesAtOnce; +#endif + } +} + +/********************************************************************* +* +* _PostTerminalSwitch() +* +* Function description +* Switch terminal to the given terminal ID. It is the caller's +* responsibility to ensure the terminal ID is correct and there is +* enough space in the buffer for this to complete successfully. +* +* Parameters +* pRing Ring buffer to post to. +* TerminalId Terminal ID to switch to. +*/ +static void _PostTerminalSwitch(SEGGER_RTT_BUFFER_UP* pRing, unsigned char TerminalId) { + unsigned char ac[2]; + + ac[0] = 0xFFu; + ac[1] = _aTerminalId[TerminalId]; // Caller made already sure that TerminalId does not exceed our terminal limit + _WriteBlocking(pRing, (const char*)ac, 2u); +} + +/********************************************************************* +* +* _GetAvailWriteSpace() +* +* Function description +* Returns the number of bytes that can be written to the ring +* buffer without blocking. +* +* Parameters +* pRing Ring buffer to check. +* +* Return value +* Number of bytes that are free in the buffer. +*/ +static unsigned _GetAvailWriteSpace(SEGGER_RTT_BUFFER_UP* pRing) { + unsigned RdOff; + unsigned WrOff; + unsigned r; + // + // Avoid warnings regarding volatile access order. It's not a problem + // in this case, but dampen compiler enthusiasm. + // + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + if (RdOff <= WrOff) { + r = pRing->SizeOfBuffer - 1u - WrOff + RdOff; + } else { + r = RdOff - WrOff - 1u; + } + return r; +} + +/********************************************************************* +* +* Public code +* +********************************************************************** +*/ + +/********************************************************************* +* +* SEGGER_RTT_ReadUpBufferNoLock() +* +* Function description +* Reads characters from SEGGER real-time-terminal control block +* which have been previously stored by the application. +* Do not lock against interrupts and multiple access. +* Used to do the same operation that J-Link does, to transfer +* RTT data via other channels, such as TCP/IP or UART. +* +* Parameters +* BufferIndex Index of Up-buffer to be used. +* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-up-buffer to. +* BufferSize Size of the target application buffer. +* +* Return value +* Number of bytes that have been read. +* +* Additional information +* This function must not be called when J-Link might also do RTT. +*/ +unsigned SEGGER_RTT_ReadUpBufferNoLock(unsigned BufferIndex, void* pData, unsigned BufferSize) { + unsigned NumBytesRem; + unsigned NumBytesRead; + unsigned RdOff; + unsigned WrOff; + unsigned char* pBuffer; + SEGGER_RTT_BUFFER_UP* pRing; + volatile char* pSrc; + + INIT(); + pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + pBuffer = (unsigned char*)pData; + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + NumBytesRead = 0u; + // + // Read from current read position to wrap-around of buffer, first + // + if (RdOff > WrOff) { + NumBytesRem = pRing->SizeOfBuffer - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); + pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + NumBytesRead += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + while (NumBytesRem--) { + *pBuffer++ = *pSrc++; + }; +#else + SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; +#endif + // + // Handle wrap-around of buffer + // + if (RdOff == pRing->SizeOfBuffer) { + RdOff = 0u; + } + } + // + // Read remaining items of buffer + // + NumBytesRem = WrOff - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); + if (NumBytesRem > 0u) { + pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + NumBytesRead += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + while (NumBytesRem--) { + *pBuffer++ = *pSrc++; + }; +#else + SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; +#endif + } + // + // Update read offset of buffer + // + if (NumBytesRead) { + pRing->RdOff = RdOff; + } + // + return NumBytesRead; +} + +/********************************************************************* +* +* SEGGER_RTT_ReadNoLock() +* +* Function description +* Reads characters from SEGGER real-time-terminal control block +* which have been previously stored by the host. +* Do not lock against interrupts and multiple access. +* +* Parameters +* BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. +* BufferSize Size of the target application buffer. +* +* Return value +* Number of bytes that have been read. +*/ +unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned BufferSize) { + unsigned NumBytesRem; + unsigned NumBytesRead; + unsigned RdOff; + unsigned WrOff; + unsigned char* pBuffer; + SEGGER_RTT_BUFFER_DOWN* pRing; + volatile char* pSrc; + // + INIT(); + pRing = (SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + pBuffer = (unsigned char*)pData; + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + NumBytesRead = 0u; + // + // Read from current read position to wrap-around of buffer, first + // + if (RdOff > WrOff) { + NumBytesRem = pRing->SizeOfBuffer - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); + pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + NumBytesRead += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + while (NumBytesRem--) { + *pBuffer++ = *pSrc++; + }; +#else + SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; +#endif + // + // Handle wrap-around of buffer + // + if (RdOff == pRing->SizeOfBuffer) { + RdOff = 0u; + } + } + // + // Read remaining items of buffer + // + NumBytesRem = WrOff - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); + if (NumBytesRem > 0u) { + pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + NumBytesRead += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + while (NumBytesRem--) { + *pBuffer++ = *pSrc++; + }; +#else + SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; +#endif + } + if (NumBytesRead) { + pRing->RdOff = RdOff; + } + // + return NumBytesRead; +} + +/********************************************************************* +* +* SEGGER_RTT_ReadUpBuffer +* +* Function description +* Reads characters from SEGGER real-time-terminal control block +* which have been previously stored by the application. +* Used to do the same operation that J-Link does, to transfer +* RTT data via other channels, such as TCP/IP or UART. +* +* Parameters +* BufferIndex Index of Up-buffer to be used. +* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-up-buffer to. +* BufferSize Size of the target application buffer. +* +* Return value +* Number of bytes that have been read. +* +* Additional information +* This function must not be called when J-Link might also do RTT. +* This function locks against all other RTT operations. I.e. during +* the read operation, writing is also locked. +* If only one consumer reads from the up buffer, +* call sEGGER_RTT_ReadUpBufferNoLock() instead. +*/ +unsigned SEGGER_RTT_ReadUpBuffer(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) { + unsigned NumBytesRead; + + SEGGER_RTT_LOCK(); + // + // Call the non-locking read function + // + NumBytesRead = SEGGER_RTT_ReadUpBufferNoLock(BufferIndex, pBuffer, BufferSize); + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + // + return NumBytesRead; +} + +/********************************************************************* +* +* SEGGER_RTT_Read +* +* Function description +* Reads characters from SEGGER real-time-terminal control block +* which have been previously stored by the host. +* +* Parameters +* BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. +* BufferSize Size of the target application buffer. +* +* Return value +* Number of bytes that have been read. +*/ +unsigned SEGGER_RTT_Read(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) { + unsigned NumBytesRead; + + SEGGER_RTT_LOCK(); + // + // Call the non-locking read function + // + NumBytesRead = SEGGER_RTT_ReadNoLock(BufferIndex, pBuffer, BufferSize); + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + // + return NumBytesRead; +} + +/********************************************************************* +* +* SEGGER_RTT_WriteWithOverwriteNoLock +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block. +* SEGGER_RTT_WriteWithOverwriteNoLock does not lock the application +* and overwrites data if the data does not fit into the buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, data is overwritten. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +* (3) Do not use SEGGER_RTT_WriteWithOverwriteNoLock if a J-Link +* connection reads RTT data. +*/ +void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + const char* pData; + SEGGER_RTT_BUFFER_UP* pRing; + unsigned Avail; + volatile char* pDst; + // + // Get "to-host" ring buffer and copy some elements into local variables. + // + pData = (const char *)pBuffer; + pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + // + // Check if we will overwrite data and need to adjust the RdOff. + // + if (pRing->WrOff == pRing->RdOff) { + Avail = pRing->SizeOfBuffer - 1u; + } else if ( pRing->WrOff < pRing->RdOff) { + Avail = pRing->RdOff - pRing->WrOff - 1u; + } else { + Avail = pRing->RdOff - pRing->WrOff - 1u + pRing->SizeOfBuffer; + } + if (NumBytes > Avail) { + pRing->RdOff += (NumBytes - Avail); + while (pRing->RdOff >= pRing->SizeOfBuffer) { + pRing->RdOff -= pRing->SizeOfBuffer; + } + } + // + // Write all data, no need to check the RdOff, but possibly handle multiple wrap-arounds + // + Avail = pRing->SizeOfBuffer - pRing->WrOff; + do { + if (Avail > NumBytes) { + // + // Last round + // + pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + Avail = NumBytes; + while (NumBytes--) { + *pDst++ = *pData++; + }; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff += Avail; +#else + SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytes); + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff += NumBytes; +#endif + break; + } else { + // + // Wrap-around necessary, write until wrap-around and reset WrOff + // + pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + NumBytes -= Avail; + while (Avail--) { + *pDst++ = *pData++; + }; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = 0; +#else + SEGGER_RTT_MEMCPY((void*)pDst, pData, Avail); + pData += Avail; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = 0; + NumBytes -= Avail; +#endif + Avail = (pRing->SizeOfBuffer - 1); + } + } while (NumBytes); +} + +/********************************************************************* +* +* SEGGER_RTT_WriteSkipNoLock +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block which is then read by the host. +* SEGGER_RTT_WriteSkipNoLock does not lock the application and +* skips all data, if the data does not fit into the buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* MUST be > 0!!! +* This is done for performance reasons, so no initial check has do be done. +* +* Return value +* 1: Data has been copied +* 0: No space, data has not been copied +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, all data is dropped. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +*/ +#if (RTT_USE_ASM == 0) +unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + const char* pData; + SEGGER_RTT_BUFFER_UP* pRing; + unsigned Avail; + unsigned RdOff; + unsigned WrOff; + unsigned Rem; + volatile char* pDst; + // + // Cases: + // 1) RdOff <= WrOff => Space until wrap-around is sufficient + // 2) RdOff <= WrOff => Space after wrap-around needed (copy in 2 chunks) + // 3) RdOff < WrOff => No space in buf + // 4) RdOff > WrOff => Space is sufficient + // 5) RdOff > WrOff => No space in buf + // + // 1) is the most common case for large buffers and assuming that J-Link reads the data fast enough + // + pData = (const char *)pBuffer; + pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + if (RdOff <= WrOff) { // Case 1), 2) or 3) + Avail = pRing->SizeOfBuffer - WrOff - 1u; // Space until wrap-around (assume 1 byte not usable for case that RdOff == 0) + if (Avail >= NumBytes) { // Case 1)? +CopyStraight: + pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; + memcpy((void*)pDst, pData, NumBytes); + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = WrOff + NumBytes; + return 1; + } + Avail += RdOff; // Space incl. wrap-around + if (Avail >= NumBytes) { // Case 2? => If not, we have case 3) (does not fit) + Rem = pRing->SizeOfBuffer - WrOff; // Space until end of buffer + pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; + memcpy((void*)pDst, pData, Rem); // Copy 1st chunk + NumBytes -= Rem; + // + // Special case: First check that assumed RdOff == 0 calculated that last element before wrap-around could not be used + // But 2nd check (considering space until wrap-around and until RdOff) revealed that RdOff is not 0, so we can use the last element + // In this case, we may use a copy straight until buffer end anyway without needing to copy 2 chunks + // Therefore, check if 2nd memcpy is necessary at all + // + if (NumBytes) { + pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF; + memcpy((void*)pDst, pData + Rem, NumBytes); + } + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = NumBytes; + return 1; + } + } else { // Potential case 4) + Avail = RdOff - WrOff - 1u; + if (Avail >= NumBytes) { // Case 4)? => If not, we have case 5) (does not fit) + goto CopyStraight; + } + } + return 0; // No space in buffer +} +#endif + +/********************************************************************* +* +* SEGGER_RTT_WriteDownBufferNoLock +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block inside a buffer. +* SEGGER_RTT_WriteDownBufferNoLock does not lock the application. +* Used to do the same operation that J-Link does, to transfer +* RTT data from other channels, such as TCP/IP or UART. +* +* Parameters +* BufferIndex Index of "Down"-buffer to be used. +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* Number of bytes which have been stored in the "Down"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +* +* Additional information +* This function must not be called when J-Link might also do RTT. +*/ +unsigned SEGGER_RTT_WriteDownBufferNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + unsigned Status; + unsigned Avail; + const char* pData; + SEGGER_RTT_BUFFER_UP* pRing; + // + // Get "to-target" ring buffer. + // It is save to cast that to a "to-host" buffer. Up and Down buffer differ in volatility of offsets that might be modified by J-Link. + // + pData = (const char *)pBuffer; + pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + // + // How we output depends upon the mode... + // + switch (pRing->Flags) { + case SEGGER_RTT_MODE_NO_BLOCK_SKIP: + // + // If we are in skip mode and there is no space for the whole + // of this output, don't bother. + // + Avail = _GetAvailWriteSpace(pRing); + if (Avail < NumBytes) { + Status = 0u; + } else { + Status = NumBytes; + _WriteNoCheck(pRing, pData, NumBytes); + } + break; + case SEGGER_RTT_MODE_NO_BLOCK_TRIM: + // + // If we are in trim mode, trim to what we can output without blocking. + // + Avail = _GetAvailWriteSpace(pRing); + Status = Avail < NumBytes ? Avail : NumBytes; + _WriteNoCheck(pRing, pData, Status); + break; + case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: + // + // If we are in blocking mode, output everything. + // + Status = _WriteBlocking(pRing, pData, NumBytes); + break; + default: + Status = 0u; + break; + } + // + // Finish up. + // + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_WriteNoLock +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block which is then read by the host. +* SEGGER_RTT_WriteNoLock does not lock the application. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +*/ +unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + unsigned Status; + unsigned Avail; + const char* pData; + SEGGER_RTT_BUFFER_UP* pRing; + // + // Get "to-host" ring buffer. + // + pData = (const char *)pBuffer; + pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + // + // How we output depends upon the mode... + // + switch (pRing->Flags) { + case SEGGER_RTT_MODE_NO_BLOCK_SKIP: + // + // If we are in skip mode and there is no space for the whole + // of this output, don't bother. + // + Avail = _GetAvailWriteSpace(pRing); + if (Avail < NumBytes) { + Status = 0u; + } else { + Status = NumBytes; + _WriteNoCheck(pRing, pData, NumBytes); + } + break; + case SEGGER_RTT_MODE_NO_BLOCK_TRIM: + // + // If we are in trim mode, trim to what we can output without blocking. + // + Avail = _GetAvailWriteSpace(pRing); + Status = Avail < NumBytes ? Avail : NumBytes; + _WriteNoCheck(pRing, pData, Status); + break; + case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: + // + // If we are in blocking mode, output everything. + // + Status = _WriteBlocking(pRing, pData, NumBytes); + break; + default: + Status = 0u; + break; + } + // + // Finish up. + // + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_WriteDownBuffer +* +* Function description +* Stores a specified number of characters in SEGGER RTT control block in a buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* Number of bytes which have been stored in the "Down"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +* +* Additional information +* This function must not be called when J-Link might also do RTT. +* This function locks against all other RTT operations. I.e. during +* the write operation, writing from the application is also locked. +* If only one consumer writes to the down buffer, +* call SEGGER_RTT_WriteDownBufferNoLock() instead. +*/ +unsigned SEGGER_RTT_WriteDownBuffer(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + unsigned Status; + + INIT(); + SEGGER_RTT_LOCK(); + Status = SEGGER_RTT_WriteDownBufferNoLock(BufferIndex, pBuffer, NumBytes); // Call the non-locking write function + SEGGER_RTT_UNLOCK(); + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_Write +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block which is then read by the host. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +*/ +unsigned SEGGER_RTT_Write(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + unsigned Status; + + INIT(); + SEGGER_RTT_LOCK(); + Status = SEGGER_RTT_WriteNoLock(BufferIndex, pBuffer, NumBytes); // Call the non-locking write function + SEGGER_RTT_UNLOCK(); + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_WriteString +* +* Function description +* Stores string in SEGGER RTT control block. +* This data is read by the host. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* s Pointer to string. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +* (2) String passed to this function has to be \0 terminated +* (3) \0 termination character is *not* stored in RTT buffer +*/ +unsigned SEGGER_RTT_WriteString(unsigned BufferIndex, const char* s) { + unsigned Len; + + Len = STRLEN(s); + return SEGGER_RTT_Write(BufferIndex, s, Len); +} + +/********************************************************************* +* +* SEGGER_RTT_PutCharSkipNoLock +* +* Function description +* Stores a single character/byte in SEGGER RTT buffer. +* SEGGER_RTT_PutCharSkipNoLock does not lock the application and +* skips the byte, if it does not fit into the buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* c Byte to be stored. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, the character is dropped. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +*/ + +unsigned SEGGER_RTT_PutCharSkipNoLock(unsigned BufferIndex, char c) { + SEGGER_RTT_BUFFER_UP* pRing; + unsigned WrOff; + unsigned Status; + volatile char* pDst; + // + // Get "to-host" ring buffer. + // + pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + // + // Get write position and handle wrap-around if necessary + // + WrOff = pRing->WrOff + 1; + if (WrOff == pRing->SizeOfBuffer) { + WrOff = 0; + } + // + // Output byte if free space is available + // + if (WrOff != pRing->RdOff) { + pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; + *pDst = c; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = WrOff; + Status = 1; + } else { + Status = 0; + } + // + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_PutCharSkip +* +* Function description +* Stores a single character/byte in SEGGER RTT buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* c Byte to be stored. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, the character is dropped. +*/ + +unsigned SEGGER_RTT_PutCharSkip(unsigned BufferIndex, char c) { + SEGGER_RTT_BUFFER_UP* pRing; + unsigned WrOff; + unsigned Status; + volatile char* pDst; + // + // Prepare + // + INIT(); + SEGGER_RTT_LOCK(); + // + // Get "to-host" ring buffer. + // + pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + // + // Get write position and handle wrap-around if necessary + // + WrOff = pRing->WrOff + 1; + if (WrOff == pRing->SizeOfBuffer) { + WrOff = 0; + } + // + // Output byte if free space is available + // + if (WrOff != pRing->RdOff) { + pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; + *pDst = c; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = WrOff; + Status = 1; + } else { + Status = 0; + } + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + // + return Status; +} + + /********************************************************************* +* +* SEGGER_RTT_PutChar +* +* Function description +* Stores a single character/byte in SEGGER RTT buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* c Byte to be stored. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +*/ + +unsigned SEGGER_RTT_PutChar(unsigned BufferIndex, char c) { + SEGGER_RTT_BUFFER_UP* pRing; + unsigned WrOff; + unsigned Status; + volatile char* pDst; + // + // Prepare + // + INIT(); + SEGGER_RTT_LOCK(); + // + // Get "to-host" ring buffer. + // + pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + // + // Get write position and handle wrap-around if necessary + // + WrOff = pRing->WrOff + 1; + if (WrOff == pRing->SizeOfBuffer) { + WrOff = 0; + } + // + // Wait for free space if mode is set to blocking + // + if (pRing->Flags == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) { + while (WrOff == pRing->RdOff) { + ; + } + } + // + // Output byte if free space is available + // + if (WrOff != pRing->RdOff) { + pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; + *pDst = c; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = WrOff; + Status = 1; + } else { + Status = 0; + } + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_GetKey +* +* Function description +* Reads one character from the SEGGER RTT buffer. +* Host has previously stored data there. +* +* Return value +* < 0 - No character available (buffer empty). +* >= 0 - Character which has been read. (Possible values: 0 - 255) +* +* Notes +* (1) This function is only specified for accesses to RTT buffer 0. +*/ +int SEGGER_RTT_GetKey(void) { + char c; + int r; + + r = (int)SEGGER_RTT_Read(0u, &c, 1u); + if (r == 1) { + r = (int)(unsigned char)c; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_WaitKey +* +* Function description +* Waits until at least one character is avaible in the SEGGER RTT buffer. +* Once a character is available, it is read and this function returns. +* +* Return value +* >=0 - Character which has been read. +* +* Notes +* (1) This function is only specified for accesses to RTT buffer 0 +* (2) This function is blocking if no character is present in RTT buffer +*/ +int SEGGER_RTT_WaitKey(void) { + int r; + + do { + r = SEGGER_RTT_GetKey(); + } while (r < 0); + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_HasKey +* +* Function description +* Checks if at least one character for reading is available in the SEGGER RTT buffer. +* +* Return value +* == 0 - No characters are available to read. +* == 1 - At least one character is available. +* +* Notes +* (1) This function is only specified for accesses to RTT buffer 0 +*/ +int SEGGER_RTT_HasKey(void) { + SEGGER_RTT_BUFFER_DOWN* pRing; + unsigned RdOff; + int r; + + INIT(); + pRing = (SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[0] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + RdOff = pRing->RdOff; + if (RdOff != pRing->WrOff) { + r = 1; + } else { + r = 0; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_HasData +* +* Function description +* Check if there is data from the host in the given buffer. +* +* Return value: +* ==0: No data +* !=0: Data in buffer +* +*/ +unsigned SEGGER_RTT_HasData(unsigned BufferIndex) { + SEGGER_RTT_BUFFER_DOWN* pRing; + unsigned v; + + pRing = (SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + v = pRing->WrOff; + return v - pRing->RdOff; +} + +/********************************************************************* +* +* SEGGER_RTT_HasDataUp +* +* Function description +* Check if there is data remaining to be sent in the given buffer. +* +* Return value: +* ==0: No data +* !=0: Data in buffer +* +*/ +unsigned SEGGER_RTT_HasDataUp(unsigned BufferIndex) { + SEGGER_RTT_BUFFER_UP* pRing; + unsigned v; + + pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + v = pRing->RdOff; + return pRing->WrOff - v; +} + +/********************************************************************* +* +* SEGGER_RTT_AllocDownBuffer +* +* Function description +* Run-time configuration of the next down-buffer (H->T). +* The next buffer, which is not used yet is configured. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* +* Return value +* >= 0 - O.K. Buffer Index +* < 0 - Error +*/ +int SEGGER_RTT_AllocDownBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int BufferIndex; + volatile SEGGER_RTT_CB* pRTTCB; + + INIT(); + SEGGER_RTT_LOCK(); + pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + BufferIndex = 0; + do { + if (pRTTCB->aDown[BufferIndex].pBuffer == NULL) { + break; + } + BufferIndex++; + } while (BufferIndex < pRTTCB->MaxNumDownBuffers); + if (BufferIndex < pRTTCB->MaxNumDownBuffers) { + pRTTCB->aDown[BufferIndex].sName = sName; + pRTTCB->aDown[BufferIndex].pBuffer = (char*)pBuffer; + pRTTCB->aDown[BufferIndex].SizeOfBuffer = BufferSize; + pRTTCB->aDown[BufferIndex].RdOff = 0u; + pRTTCB->aDown[BufferIndex].WrOff = 0u; + pRTTCB->aDown[BufferIndex].Flags = Flags; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + } else { + BufferIndex = -1; + } + SEGGER_RTT_UNLOCK(); + return BufferIndex; +} + +/********************************************************************* +* +* SEGGER_RTT_AllocUpBuffer +* +* Function description +* Run-time configuration of the next up-buffer (T->H). +* The next buffer, which is not used yet is configured. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* +* Return value +* >= 0 - O.K. Buffer Index +* < 0 - Error +*/ +int SEGGER_RTT_AllocUpBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int BufferIndex; + volatile SEGGER_RTT_CB* pRTTCB; + + INIT(); + SEGGER_RTT_LOCK(); + pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + BufferIndex = 0; + do { + if (pRTTCB->aUp[BufferIndex].pBuffer == NULL) { + break; + } + BufferIndex++; + } while (BufferIndex < pRTTCB->MaxNumUpBuffers); + if (BufferIndex < pRTTCB->MaxNumUpBuffers) { + pRTTCB->aUp[BufferIndex].sName = sName; + pRTTCB->aUp[BufferIndex].pBuffer = (char*)pBuffer; + pRTTCB->aUp[BufferIndex].SizeOfBuffer = BufferSize; + pRTTCB->aUp[BufferIndex].RdOff = 0u; + pRTTCB->aUp[BufferIndex].WrOff = 0u; + pRTTCB->aUp[BufferIndex].Flags = Flags; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + } else { + BufferIndex = -1; + } + SEGGER_RTT_UNLOCK(); + return BufferIndex; +} + +/********************************************************************* +* +* SEGGER_RTT_ConfigUpBuffer +* +* Function description +* Run-time configuration of a specific up-buffer (T->H). +* Buffer to be configured is specified by index. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* BufferIndex Index of the buffer to configure. +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* +* Return value +* >= 0 - O.K. +* < 0 - Error +* +* Additional information +* Buffer 0 is configured on compile-time. +* May only be called once per buffer. +* Buffer name and flags can be reconfigured using the appropriate functions. +*/ +int SEGGER_RTT_ConfigUpBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int r; + volatile SEGGER_RTT_CB* pRTTCB; + volatile SEGGER_RTT_BUFFER_UP* pUp; + + INIT(); + pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) { + SEGGER_RTT_LOCK(); + pUp = &pRTTCB->aUp[BufferIndex]; + if (BufferIndex) { + pUp->sName = sName; + pUp->pBuffer = (char*)pBuffer; + pUp->SizeOfBuffer = BufferSize; + pUp->RdOff = 0u; + pUp->WrOff = 0u; + } + pUp->Flags = Flags; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_ConfigDownBuffer +* +* Function description +* Run-time configuration of a specific down-buffer (H->T). +* Buffer to be configured is specified by index. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* BufferIndex Index of the buffer to configure. +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* +* Return value +* >= 0 O.K. +* < 0 Error +* +* Additional information +* Buffer 0 is configured on compile-time. +* May only be called once per buffer. +* Buffer name and flags can be reconfigured using the appropriate functions. +*/ +int SEGGER_RTT_ConfigDownBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int r; + volatile SEGGER_RTT_CB* pRTTCB; + volatile SEGGER_RTT_BUFFER_DOWN* pDown; + + INIT(); + pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) { + SEGGER_RTT_LOCK(); + pDown = &pRTTCB->aDown[BufferIndex]; + if (BufferIndex) { + pDown->sName = sName; + pDown->pBuffer = (char*)pBuffer; + pDown->SizeOfBuffer = BufferSize; + pDown->RdOff = 0u; + pDown->WrOff = 0u; + } + pDown->Flags = Flags; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetNameUpBuffer +* +* Function description +* Run-time configuration of a specific up-buffer name (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer to renamed. +* sName Pointer to a constant name string. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetNameUpBuffer(unsigned BufferIndex, const char* sName) { + int r; + volatile SEGGER_RTT_CB* pRTTCB; + volatile SEGGER_RTT_BUFFER_UP* pUp; + + INIT(); + pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) { + SEGGER_RTT_LOCK(); + pUp = &pRTTCB->aUp[BufferIndex]; + pUp->sName = sName; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetNameDownBuffer +* +* Function description +* Run-time configuration of a specific Down-buffer name (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer to renamed. +* sName Pointer to a constant name string. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName) { + int r; + volatile SEGGER_RTT_CB* pRTTCB; + volatile SEGGER_RTT_BUFFER_DOWN* pDown; + + INIT(); + pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) { + SEGGER_RTT_LOCK(); + pDown = &pRTTCB->aDown[BufferIndex]; + pDown->sName = sName; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetFlagsUpBuffer +* +* Function description +* Run-time configuration of specific up-buffer flags (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer. +* Flags Flags to set for the buffer. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetFlagsUpBuffer(unsigned BufferIndex, unsigned Flags) { + int r; + volatile SEGGER_RTT_CB* pRTTCB; + volatile SEGGER_RTT_BUFFER_UP* pUp; + + INIT(); + pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) { + SEGGER_RTT_LOCK(); + pUp = &pRTTCB->aUp[BufferIndex]; + pUp->Flags = Flags; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetFlagsDownBuffer +* +* Function description +* Run-time configuration of specific Down-buffer flags (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer to renamed. +* Flags Flags to set for the buffer. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetFlagsDownBuffer(unsigned BufferIndex, unsigned Flags) { + int r; + volatile SEGGER_RTT_CB* pRTTCB; + volatile SEGGER_RTT_BUFFER_DOWN* pDown; + + INIT(); + pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) { + SEGGER_RTT_LOCK(); + pDown = &pRTTCB->aDown[BufferIndex]; + pDown->Flags = Flags; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_Init +* +* Function description +* Initializes the RTT Control Block. +* Should be used in RAM targets, at start of the application. +* +*/ +void SEGGER_RTT_Init (void) { + _DoInit(); +} + +/********************************************************************* +* +* SEGGER_RTT_SetTerminal +* +* Function description +* Sets the terminal to be used for output on channel 0. +* +* Parameters +* TerminalId Index of the terminal. +* +* Return value +* >= 0 O.K. +* < 0 Error (e.g. if RTT is configured for non-blocking mode and there was no space in the buffer to set the new terminal Id) +* +* Notes +* (1) Buffer 0 is always reserved for terminal I/O, so we can use index 0 here, fixed +*/ +int SEGGER_RTT_SetTerminal (unsigned char TerminalId) { + unsigned char ac[2]; + SEGGER_RTT_BUFFER_UP* pRing; + unsigned Avail; + int r; + + INIT(); + r = 0; + ac[0] = 0xFFu; + if (TerminalId < sizeof(_aTerminalId)) { // We only support a certain number of channels + ac[1] = _aTerminalId[TerminalId]; + pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[0] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + SEGGER_RTT_LOCK(); // Lock to make sure that no other task is writing into buffer, while we are and number of free bytes in buffer does not change downwards after checking and before writing + if ((pRing->Flags & SEGGER_RTT_MODE_MASK) == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) { + _ActiveTerminal = TerminalId; + _WriteBlocking(pRing, (const char*)ac, 2u); + } else { // Skipping mode or trim mode? => We cannot trim this command so handling is the same for both modes + Avail = _GetAvailWriteSpace(pRing); + if (Avail >= 2) { + _ActiveTerminal = TerminalId; // Only change active terminal in case of success + _WriteNoCheck(pRing, (const char*)ac, 2u); + } else { + r = -1; + } + } + SEGGER_RTT_UNLOCK(); + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_TerminalOut +* +* Function description +* Writes a string to the given terminal +* without changing the terminal for channel 0. +* +* Parameters +* TerminalId Index of the terminal. +* s String to be printed on the terminal. +* +* Return value +* >= 0 - Number of bytes written. +* < 0 - Error. +* +*/ +int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s) { + int Status; + unsigned FragLen; + unsigned Avail; + SEGGER_RTT_BUFFER_UP* pRing; + // + INIT(); + // + // Validate terminal ID. + // + if (TerminalId < (char)sizeof(_aTerminalId)) { // We only support a certain number of channels + // + // Get "to-host" ring buffer. + // + pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[0] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + // + // Need to be able to change terminal, write data, change back. + // Compute the fixed and variable sizes. + // + FragLen = STRLEN(s); + // + // How we output depends upon the mode... + // + SEGGER_RTT_LOCK(); + Avail = _GetAvailWriteSpace(pRing); + switch (pRing->Flags & SEGGER_RTT_MODE_MASK) { + case SEGGER_RTT_MODE_NO_BLOCK_SKIP: + // + // If we are in skip mode and there is no space for the whole + // of this output, don't bother switching terminals at all. + // + if (Avail < (FragLen + 4u)) { + Status = 0; + } else { + _PostTerminalSwitch(pRing, TerminalId); + Status = (int)_WriteBlocking(pRing, s, FragLen); + _PostTerminalSwitch(pRing, _ActiveTerminal); + } + break; + case SEGGER_RTT_MODE_NO_BLOCK_TRIM: + // + // If we are in trim mode and there is not enough space for everything, + // trim the output but always include the terminal switch. If no room + // for terminal switch, skip that totally. + // + if (Avail < 4u) { + Status = -1; + } else { + _PostTerminalSwitch(pRing, TerminalId); + Status = (int)_WriteBlocking(pRing, s, (FragLen < (Avail - 4u)) ? FragLen : (Avail - 4u)); + _PostTerminalSwitch(pRing, _ActiveTerminal); + } + break; + case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: + // + // If we are in blocking mode, output everything. + // + _PostTerminalSwitch(pRing, TerminalId); + Status = (int)_WriteBlocking(pRing, s, FragLen); + _PostTerminalSwitch(pRing, _ActiveTerminal); + break; + default: + Status = -1; + break; + } + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + } else { + Status = -1; + } + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_GetAvailWriteSpace +* +* Function description +* Returns the number of bytes available in the ring buffer. +* +* Parameters +* BufferIndex Index of the up buffer. +* +* Return value +* Number of bytes that are free in the selected up buffer. +*/ +unsigned SEGGER_RTT_GetAvailWriteSpace (unsigned BufferIndex) { + SEGGER_RTT_BUFFER_UP* pRing; + + pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + return _GetAvailWriteSpace(pRing); +} + + +/********************************************************************* +* +* SEGGER_RTT_GetBytesInBuffer() +* +* Function description +* Returns the number of bytes currently used in the up buffer. +* +* Parameters +* BufferIndex Index of the up buffer. +* +* Return value +* Number of bytes that are used in the buffer. +*/ +unsigned SEGGER_RTT_GetBytesInBuffer(unsigned BufferIndex) { + unsigned RdOff; + unsigned WrOff; + unsigned r; + volatile SEGGER_RTT_CB* pRTTCB; + // + // Avoid warnings regarding volatile access order. It's not a problem + // in this case, but dampen compiler enthusiasm. + // + pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + RdOff = pRTTCB->aUp[BufferIndex].RdOff; + WrOff = pRTTCB->aUp[BufferIndex].WrOff; + if (RdOff <= WrOff) { + r = WrOff - RdOff; + } else { + r = pRTTCB->aUp[BufferIndex].SizeOfBuffer - (WrOff - RdOff); + } + return r; +} + +/*************************** End of file ****************************/ diff --git a/source/daplink/debug/SEGGER_RTT.h b/source/daplink/debug/SEGGER_RTT.h new file mode 100644 index 000000000..7d26dfe39 --- /dev/null +++ b/source/daplink/debug/SEGGER_RTT.h @@ -0,0 +1,488 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 1995 - 2019 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the RTT protocol and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT.h +Purpose : Implementation of SEGGER real-time transfer which allows + real-time communication on targets which support debugger + memory accesses while the CPU is running. +Revision: $Rev: 24346 $ +---------------------------------------------------------------------- +*/ + +#ifndef SEGGER_RTT_H +#define SEGGER_RTT_H + +#include "SEGGER_RTT_Conf.h" + +/********************************************************************* +* +* Defines, defaults +* +********************************************************************** +*/ + +#ifndef RTT_USE_ASM + // + // Some cores support out-of-order memory accesses (reordering of memory accesses in the core) + // For such cores, we need to define a memory barrier to guarantee the order of certain accesses to the RTT ring buffers. + // Needed for: + // Cortex-M7 (ARMv7-M) + // Cortex-M23 (ARM-v8M) + // Cortex-M33 (ARM-v8M) + // Cortex-A/R (ARM-v7A/R) + // + // We do not explicitly check for "Embedded Studio" as the compiler in use determines what we support. + // You can use an external toolchain like IAR inside ES. So there is no point in checking for "Embedded Studio" + // + #if (defined __CROSSWORKS_ARM) // Rowley Crossworks + #define _CC_HAS_RTT_ASM_SUPPORT 1 + #if (defined __ARM_ARCH_7M__) // Cortex-M3 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23 + #define _CORE_HAS_RTT_ASM_SUPPORT 0 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #else + #define _CORE_HAS_RTT_ASM_SUPPORT 0 + #endif + #elif (defined __ARMCC_VERSION) + // + // ARM compiler + // ARM compiler V6.0 and later is clang based. + // Our ASM part is compatible to clang. + // + #if (__ARMCC_VERSION >= 6000000) + #define _CC_HAS_RTT_ASM_SUPPORT 1 + #else + #define _CC_HAS_RTT_ASM_SUPPORT 0 + #endif + #if (defined __ARM_ARCH_6M__) // Cortex-M0 / M1 + #define _CORE_HAS_RTT_ASM_SUPPORT 0 // No ASM support for this architecture + #elif (defined __ARM_ARCH_7M__) // Cortex-M3 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23 + #define _CORE_HAS_RTT_ASM_SUPPORT 0 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #elif ((defined __ARM_ARCH_7A__) || (defined __ARM_ARCH_7R__)) // Cortex-A/R 32-bit ARMv7-A/R + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #else + #define _CORE_HAS_RTT_ASM_SUPPORT 0 + #endif + #elif ((defined __GNUC__) || (defined __clang__)) + // + // GCC / Clang + // + #define _CC_HAS_RTT_ASM_SUPPORT 1 + // ARM 7/9: __ARM_ARCH_5__ / __ARM_ARCH_5E__ / __ARM_ARCH_5T__ / __ARM_ARCH_5T__ / __ARM_ARCH_5TE__ + #if (defined __ARM_ARCH_7M__) // Cortex-M3 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 // Only Cortex-M7 needs a DMB but we cannot distinguish M4 and M7 here... + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23 + #define _CORE_HAS_RTT_ASM_SUPPORT 0 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #elif ((defined __ARM_ARCH_7A__) || (defined __ARM_ARCH_7R__)) // Cortex-A/R 32-bit ARMv7-A/R + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #else + #define _CORE_HAS_RTT_ASM_SUPPORT 0 + #endif + #elif ((defined __IASMARM__) || (defined __ICCARM__)) + // + // IAR assembler/compiler + // + #define _CC_HAS_RTT_ASM_SUPPORT 1 + #if (__VER__ < 6300000) + #define VOLATILE + #else + #define VOLATILE volatile + #endif + #if (defined __ARM7M__) // Needed for old versions that do not know the define yet + #if (__CORE__ == __ARM7M__) // Cortex-M3 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #endif + #endif + #if (defined __ARM7EM__) + #if (__CORE__ == __ARM7EM__) // Cortex-M4/M7 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() asm VOLATILE ("DMB"); + #endif + #endif + #if (defined __ARM8M_BASELINE__) + #if (__CORE__ == __ARM8M_BASELINE__) // Cortex-M23 + #define _CORE_HAS_RTT_ASM_SUPPORT 0 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() asm VOLATILE ("DMB"); + #endif + #endif + #if (defined __ARM8M_MAINLINE__) + #if (__CORE__ == __ARM8M_MAINLINE__) // Cortex-M33 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() asm VOLATILE ("DMB"); + #endif + #endif + #if (defined __ARM8EM_MAINLINE__) + #if (__CORE__ == __ARM8EM_MAINLINE__) // Cortex-??? + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() asm VOLATILE ("DMB"); + #endif + #endif + #if (defined __ARM7A__) + #if (__CORE__ == __ARM7A__) // Cortex-A 32-bit ARMv7-A + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() asm VOLATILE ("DMB"); + #endif + #endif + #if (defined __ARM7R__) + #if (__CORE__ == __ARM7R__) // Cortex-R 32-bit ARMv7-R + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() asm VOLATILE ("DMB"); + #endif + #endif +// TBD: __ARM8A__ => Cortex-A 64-bit ARMv8-A +// TBD: __ARM8R__ => Cortex-R 64-bit ARMv8-R + #else + // + // Other compilers + // + #define _CC_HAS_RTT_ASM_SUPPORT 0 + #define _CORE_HAS_RTT_ASM_SUPPORT 0 + #endif + // + // If IDE and core support the ASM version, enable ASM version by default + // + #ifndef _CORE_HAS_RTT_ASM_SUPPORT + #define _CORE_HAS_RTT_ASM_SUPPORT 0 // Default for unknown cores + #endif + #if (_CC_HAS_RTT_ASM_SUPPORT && _CORE_HAS_RTT_ASM_SUPPORT) + #define RTT_USE_ASM (1) + #else + #define RTT_USE_ASM (0) + #endif +#endif + +#ifndef _CORE_NEEDS_DMB + #define _CORE_NEEDS_DMB 0 +#endif + +#ifndef RTT__DMB + #if _CORE_NEEDS_DMB + #error "Don't know how to place inline assembly for DMB" + #else + #define RTT__DMB() + #endif +#endif + +#ifndef SEGGER_RTT_CPU_CACHE_LINE_SIZE + #define SEGGER_RTT_CPU_CACHE_LINE_SIZE (0) // On most target systems where RTT is used, we do not have a CPU cache, therefore 0 is a good default here +#endif + +#ifndef SEGGER_RTT_UNCACHED_OFF + #if SEGGER_RTT_CPU_CACHE_LINE_SIZE + #error "SEGGER_RTT_UNCACHED_OFF must be defined when setting SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" + #else + #define SEGGER_RTT_UNCACHED_OFF (0) + #endif +#endif +#if RTT_USE_ASM + #if SEGGER_RTT_CPU_CACHE_LINE_SIZE + #error "RTT_USE_ASM is not available if SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" + #endif +#endif + +#ifndef SEGGER_RTT_ASM // defined when SEGGER_RTT.h is included from assembly file +#include +#include + +/********************************************************************* +* +* Defines, fixed +* +********************************************************************** +*/ + +// +// Determine how much we must pad the control block to make it a multiple of a cache line in size +// Assuming: U8 = 1B +// U16 = 2B +// U32 = 4B +// U8/U16/U32* = 4B +// +#if SEGGER_RTT_CPU_CACHE_LINE_SIZE // Avoid division by zero in case we do not have any cache + #define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) (((NumBytes + SEGGER_RTT_CPU_CACHE_LINE_SIZE - 1) / SEGGER_RTT_CPU_CACHE_LINE_SIZE) * SEGGER_RTT_CPU_CACHE_LINE_SIZE) +#else + #define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) (NumBytes) +#endif +#define SEGGER_RTT__CB_SIZE (16 + 4 + 4 + (SEGGER_RTT_MAX_NUM_UP_BUFFERS * 24) + (SEGGER_RTT_MAX_NUM_DOWN_BUFFERS * 24)) +#define SEGGER_RTT__CB_PADDING (SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(SEGGER_RTT__CB_SIZE) - SEGGER_RTT__CB_SIZE) + +/********************************************************************* +* +* Types +* +********************************************************************** +*/ + +// +// Description for a circular buffer (also called "ring buffer") +// which is used as up-buffer (T->H) +// +typedef struct { + const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" + char* pBuffer; // Pointer to start of buffer + unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. + unsigned WrOff; // Position of next item to be written by either target. + volatile unsigned RdOff; // Position of next item to be read by host. Must be volatile since it may be modified by host. + unsigned Flags; // Contains configuration flags +} SEGGER_RTT_BUFFER_UP; + +// +// Description for a circular buffer (also called "ring buffer") +// which is used as down-buffer (H->T) +// +typedef struct { + const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" + char* pBuffer; // Pointer to start of buffer + unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. + volatile unsigned WrOff; // Position of next item to be written by host. Must be volatile since it may be modified by host. + unsigned RdOff; // Position of next item to be read by target (down-buffer). + unsigned Flags; // Contains configuration flags +} SEGGER_RTT_BUFFER_DOWN; + +// +// RTT control block which describes the number of buffers available +// as well as the configuration for each buffer +// +// +typedef struct { + char acID[16]; // Initialized to "SEGGER RTT" + int MaxNumUpBuffers; // Initialized to SEGGER_RTT_MAX_NUM_UP_BUFFERS (type. 2) + int MaxNumDownBuffers; // Initialized to SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (type. 2) + SEGGER_RTT_BUFFER_UP aUp[SEGGER_RTT_MAX_NUM_UP_BUFFERS]; // Up buffers, transferring information up from target via debug probe to host + SEGGER_RTT_BUFFER_DOWN aDown[SEGGER_RTT_MAX_NUM_DOWN_BUFFERS]; // Down buffers, transferring information down from host via debug probe to target +#if SEGGER_RTT__CB_PADDING + unsigned char aDummy[SEGGER_RTT__CB_PADDING]; +#endif +} SEGGER_RTT_CB; + +/********************************************************************* +* +* Global data +* +********************************************************************** +*/ +extern SEGGER_RTT_CB _SEGGER_RTT; + +/********************************************************************* +* +* RTT API functions +* +********************************************************************** +*/ +#ifdef __cplusplus + extern "C" { +#endif +int SEGGER_RTT_AllocDownBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_AllocUpBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_ConfigUpBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_ConfigDownBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_GetKey (void); +unsigned SEGGER_RTT_HasData (unsigned BufferIndex); +int SEGGER_RTT_HasKey (void); +unsigned SEGGER_RTT_HasDataUp (unsigned BufferIndex); +void SEGGER_RTT_Init (void); +unsigned SEGGER_RTT_Read (unsigned BufferIndex, void* pBuffer, unsigned BufferSize); +unsigned SEGGER_RTT_ReadNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize); +int SEGGER_RTT_SetNameDownBuffer (unsigned BufferIndex, const char* sName); +int SEGGER_RTT_SetNameUpBuffer (unsigned BufferIndex, const char* sName); +int SEGGER_RTT_SetFlagsDownBuffer (unsigned BufferIndex, unsigned Flags); +int SEGGER_RTT_SetFlagsUpBuffer (unsigned BufferIndex, unsigned Flags); +int SEGGER_RTT_WaitKey (void); +unsigned SEGGER_RTT_Write (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_ASM_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteString (unsigned BufferIndex, const char* s); +void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_PutChar (unsigned BufferIndex, char c); +unsigned SEGGER_RTT_PutCharSkip (unsigned BufferIndex, char c); +unsigned SEGGER_RTT_PutCharSkipNoLock (unsigned BufferIndex, char c); +unsigned SEGGER_RTT_GetAvailWriteSpace (unsigned BufferIndex); +unsigned SEGGER_RTT_GetBytesInBuffer (unsigned BufferIndex); +// +// Function macro for performance optimization +// +#define SEGGER_RTT_HASDATA(n) (((SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff) + +#if RTT_USE_ASM + #define SEGGER_RTT_WriteSkipNoLock SEGGER_RTT_ASM_WriteSkipNoLock +#endif + +/********************************************************************* +* +* RTT transfer functions to send RTT data via other channels. +* +********************************************************************** +*/ +unsigned SEGGER_RTT_ReadUpBuffer (unsigned BufferIndex, void* pBuffer, unsigned BufferSize); +unsigned SEGGER_RTT_ReadUpBufferNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize); +unsigned SEGGER_RTT_WriteDownBuffer (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteDownBufferNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); + +#define SEGGER_RTT_HASDATA_UP(n) (((SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff) // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + +/********************************************************************* +* +* RTT "Terminal" API functions +* +********************************************************************** +*/ +int SEGGER_RTT_SetTerminal (unsigned char TerminalId); +int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s); + +/********************************************************************* +* +* RTT printf functions (require SEGGER_RTT_printf.c) +* +********************************************************************** +*/ +int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...); +int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList); + +#ifdef __cplusplus + } +#endif + +#endif // ifndef(SEGGER_RTT_ASM) + +/********************************************************************* +* +* Defines +* +********************************************************************** +*/ + +// +// Operating modes. Define behavior if buffer is full (not enough space for entire message) +// +#define SEGGER_RTT_MODE_NO_BLOCK_SKIP (0) // Skip. Do not block, output nothing. (Default) +#define SEGGER_RTT_MODE_NO_BLOCK_TRIM (1) // Trim: Do not block, output as much as fits. +#define SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL (2) // Block: Wait until there is space in the buffer. +#define SEGGER_RTT_MODE_MASK (3) + +// +// Control sequences, based on ANSI. +// Can be used to control color, and clear the screen +// +#define RTT_CTRL_RESET "\x1B[0m" // Reset to default colors +#define RTT_CTRL_CLEAR "\x1B[2J" // Clear screen, reposition cursor to top left + +#define RTT_CTRL_TEXT_BLACK "\x1B[2;30m" +#define RTT_CTRL_TEXT_RED "\x1B[2;31m" +#define RTT_CTRL_TEXT_GREEN "\x1B[2;32m" +#define RTT_CTRL_TEXT_YELLOW "\x1B[2;33m" +#define RTT_CTRL_TEXT_BLUE "\x1B[2;34m" +#define RTT_CTRL_TEXT_MAGENTA "\x1B[2;35m" +#define RTT_CTRL_TEXT_CYAN "\x1B[2;36m" +#define RTT_CTRL_TEXT_WHITE "\x1B[2;37m" + +#define RTT_CTRL_TEXT_BRIGHT_BLACK "\x1B[1;30m" +#define RTT_CTRL_TEXT_BRIGHT_RED "\x1B[1;31m" +#define RTT_CTRL_TEXT_BRIGHT_GREEN "\x1B[1;32m" +#define RTT_CTRL_TEXT_BRIGHT_YELLOW "\x1B[1;33m" +#define RTT_CTRL_TEXT_BRIGHT_BLUE "\x1B[1;34m" +#define RTT_CTRL_TEXT_BRIGHT_MAGENTA "\x1B[1;35m" +#define RTT_CTRL_TEXT_BRIGHT_CYAN "\x1B[1;36m" +#define RTT_CTRL_TEXT_BRIGHT_WHITE "\x1B[1;37m" + +#define RTT_CTRL_BG_BLACK "\x1B[24;40m" +#define RTT_CTRL_BG_RED "\x1B[24;41m" +#define RTT_CTRL_BG_GREEN "\x1B[24;42m" +#define RTT_CTRL_BG_YELLOW "\x1B[24;43m" +#define RTT_CTRL_BG_BLUE "\x1B[24;44m" +#define RTT_CTRL_BG_MAGENTA "\x1B[24;45m" +#define RTT_CTRL_BG_CYAN "\x1B[24;46m" +#define RTT_CTRL_BG_WHITE "\x1B[24;47m" + +#define RTT_CTRL_BG_BRIGHT_BLACK "\x1B[4;40m" +#define RTT_CTRL_BG_BRIGHT_RED "\x1B[4;41m" +#define RTT_CTRL_BG_BRIGHT_GREEN "\x1B[4;42m" +#define RTT_CTRL_BG_BRIGHT_YELLOW "\x1B[4;43m" +#define RTT_CTRL_BG_BRIGHT_BLUE "\x1B[4;44m" +#define RTT_CTRL_BG_BRIGHT_MAGENTA "\x1B[4;45m" +#define RTT_CTRL_BG_BRIGHT_CYAN "\x1B[4;46m" +#define RTT_CTRL_BG_BRIGHT_WHITE "\x1B[4;47m" + + +#endif + +/*************************** End of file ****************************/ diff --git a/source/daplink/debug/SEGGER_RTT_Conf.h b/source/daplink/debug/SEGGER_RTT_Conf.h new file mode 100644 index 000000000..3ac38dcf1 --- /dev/null +++ b/source/daplink/debug/SEGGER_RTT_Conf.h @@ -0,0 +1,424 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 1995 - 2020 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the RTT protocol and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT_Conf.h +Purpose : Implementation of SEGGER real-time transfer (RTT) which + allows real-time communication on targets which support + debugger memory accesses while the CPU is running. +Revision: $Rev: 24316 $ + +*/ + +#ifndef SEGGER_RTT_CONF_H +#define SEGGER_RTT_CONF_H + +#ifdef __IAR_SYSTEMS_ICC__ + #include +#endif + +/********************************************************************* +* +* Defines, configurable +* +********************************************************************** +*/ + +// +// Take in and set to correct values for Cortex-A systems with CPU cache +// +//#define SEGGER_RTT_CPU_CACHE_LINE_SIZE (32) // Largest cache line size (in bytes) in the current system +//#define SEGGER_RTT_UNCACHED_OFF (0xFB000000) // Address alias where RTT CB and buffers can be accessed uncached +// +// Most common case: +// Up-channel 0: RTT +// Up-channel 1: SystemView +// +#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS + #define SEGGER_RTT_MAX_NUM_UP_BUFFERS (3) // Max. number of up-buffers (T->H) available on this target (Default: 3) +#endif +// +// Most common case: +// Down-channel 0: RTT +// Down-channel 1: SystemView +// +#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS + #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3) +#endif + +#ifndef BUFFER_SIZE_UP + #define BUFFER_SIZE_UP (1024) // Size of the buffer for terminal output of target, up to host (Default: 1k) +#endif + +#ifndef BUFFER_SIZE_DOWN + #define BUFFER_SIZE_DOWN (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) +#endif + +#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE + #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) +#endif + +#ifndef SEGGER_RTT_MODE_DEFAULT + #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0) +#endif + +/********************************************************************* +* +* RTT memcpy configuration +* +* memcpy() is good for large amounts of data, +* but the overhead is big for small amounts, which are usually stored via RTT. +* With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. +* +* SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. +* This is may be required with memory access restrictions, +* such as on Cortex-A devices with MMU. +*/ +#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP + #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop +#endif +// +// Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets +// +//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) +// #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes)) +//#endif + +// +// Target is not allowed to perform other RTT operations while string still has not been stored completely. +// Otherwise we would probably end up with a mixed string in the buffer. +// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here. +// +// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4. +// Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches. +// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly. +// (Higher priority = lower priority number) +// Default value for embOS: 128u +// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +// In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC +// or define SEGGER_RTT_LOCK() to completely disable interrupts. +// +#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) +#endif + +/********************************************************************* +* +* RTT lock configuration for SEGGER Embedded Studio, +* Rowley CrossStudio and GCC +*/ +#if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32)) + #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs %0, primask \n\t" \ + "movs r1, #1 \n\t" \ + "msr primask, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : \ + ); \ + } + #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs %0, basepri \n\t" \ + "mov r1, %1 \n\t" \ + "msr basepri, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : \ + ); \ + } + + #elif (defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "r0", "r1", "cc" \ + ); \ + } + #elif defined(__riscv) || defined(__riscv_xlen) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("csrr %0, mstatus \n\t" \ + "csrci mstatus, 8 \n\t" \ + "andi %0, %0, 8 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \ + "or %0, %0, a1 \n\t" \ + "csrs mstatus, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "a1" \ + ); \ + } + #else + #define SEGGER_RTT_LOCK() + #define SEGGER_RTT_UNLOCK() + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for IAR EWARM +*/ +#ifdef __ICCARM__ + #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) || \ + (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + + #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ + } + #elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \ + (defined (__ARM7M__) && (__CORE__ == __ARM7M__)) || \ + (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ + (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_BASEPRI(); \ + __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + + #define SEGGER_RTT_UNLOCK() __set_BASEPRI(_SEGGER_RTT__LockState); \ + } + #elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__)) || \ + (defined (__ARM7R__) && (__CORE__ == __ARM7R__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "r0", "r1", "cc" \ + ); \ + } + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for IAR RX +*/ +#ifdef __ICCRX__ + #define SEGGER_RTT_LOCK() { \ + unsigned long _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_interrupt_state(); \ + __disable_interrupt(); + + #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration for IAR RL78 +*/ +#ifdef __ICCRL78__ + #define SEGGER_RTT_LOCK() { \ + __istate_t _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_interrupt_state(); \ + __disable_interrupt(); + + #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration for KEIL ARM +*/ +#ifdef __CC_ARM + #if (defined __TARGET_ARCH_6S_M) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask"); \ + _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \ + _SEGGER_RTT__PRIMASK = 1u; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \ + __schedule_barrier(); \ + } + #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + register unsigned char BASEPRI __asm( "basepri"); \ + _SEGGER_RTT__LockState = BASEPRI; \ + BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() BASEPRI = _SEGGER_RTT__LockState; \ + __schedule_barrier(); \ + } + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for TI ARM +*/ +#ifdef __TI_ARM__ + #if defined (__TI_ARM_V6M0__) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + + #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ + } + #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + + #define SEGGER_RTT_UNLOCK() _set_interrupt_priority(_SEGGER_RTT__LockState); \ + } + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for CCRX +*/ +#ifdef __RX + #include + #define SEGGER_RTT_LOCK() { \ + unsigned long _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = get_psw() & 0x010000; \ + clrpsw_i(); + + #define SEGGER_RTT_UNLOCK() set_psw(get_psw() | _SEGGER_RTT__LockState); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration for embOS Simulation on Windows +* (Can also be used for generic RTT locking with embOS) +*/ +#if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS) + +void OS_SIM_EnterCriticalSection(void); +void OS_SIM_LeaveCriticalSection(void); + +#define SEGGER_RTT_LOCK() { \ + OS_SIM_EnterCriticalSection(); + +#define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration fallback +*/ +#ifndef SEGGER_RTT_LOCK + #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) +#endif + +#ifndef SEGGER_RTT_UNLOCK + #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) +#endif + +#endif +/*************************** End of file ****************************/ From 752ab302f99b416e1d7969e15e8609301e3587b7 Mon Sep 17 00:00:00 2001 From: Martin Williams Date: Tue, 23 Nov 2021 19:31:41 +0000 Subject: [PATCH 504/617] nrf52820_microbit: Detect USB insertion via USB_DETECTED IRQ instead of VBUS_ABSENT GPIOTE From PR https://github.com/mathias-arm/DAPLink/pull/14 --- source/board/microbitv2/nrf52820/power.c | 68 +++++++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/source/board/microbitv2/nrf52820/power.c b/source/board/microbitv2/nrf52820/power.c index f61d5eea6..2e08fde1e 100644 --- a/source/board/microbitv2/nrf52820/power.c +++ b/source/board/microbitv2/nrf52820/power.c @@ -57,9 +57,22 @@ extern power_source_t power_source; uint8_t power_gpiote_enabled; uint32_t power_gpiote_intenset; +// Define one of these +// Using USBDETECTED for wake-up from SYSTEMOFF +// results in different values in NRF_POWER->RESETREAS +// for reset button and USB wake-ups +#define POWER_IRQ_USBDETECTED 1 +//#define POWER_IRQ_VBUS_ABSENT 1 void power_init() { + if (NRF_POWER->RESETREAS & POWER_RESETREAS_VBUS_Msk) { + wake_from_usb = 1; + } + if (NRF_POWER->RESETREAS & POWER_RESETREAS_OFF_Msk) { + wake_from_reset = 1; + } + microbitv2_pins_init(); // Store NRF_GPIOTE state @@ -69,13 +82,24 @@ void power_init() // Override hic_hal gpio_init() RESET_BUTTON_PULL (=NRF_GPIO_PIN_PULLUP) gpio_cfg_input(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON), NRF_GPIO_PIN_NOPULL); - // Configure VBUS_ABSENT (WAKE_ON_EDGE) pin to detect USB attach/detach */ + // Configure VBUS_ABSENT (WAKE_ON_EDGE) pin as input */ gpio_cfg_input(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT), NRF_GPIO_PIN_NOPULL); + +#ifdef POWER_IRQ_VBUS_ABSENT + // Configure VBUS_ABSENT (WAKE_ON_EDGE) pin to detect USB attach/detach */ power_gpio_set_sense_from_read(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT)); +#endif // POWER_IRQ_VBUS_ABSENT NRF_GPIOTE->EVENTS_PORT = 0; NRF_GPIOTE->INTENSET = power_gpiote_intenset | ( GPIOTE_INTENSET_PORT_Set << GPIOTE_INTENSET_PORT_Pos); NVIC_EnableIRQ(GPIOTE_IRQn); + +#ifdef POWER_IRQ_USBDETECTED + // Enable NRF_POWER interrupt for USB detected/removed + NRF_POWER->INTENCLR = NRF_POWER->INTENSET; + NRF_POWER->INTENSET = POWER_INTENSET_USBDETECTED_Msk | POWER_INTENSET_USBREMOVED_Msk; + NVIC_EnableIRQ(POWER_CLOCK_IRQn); +#endif // POWER_IRQ_USBDETECTED } void power_down() @@ -113,8 +137,10 @@ static void power_before(bool systemoff) power_gpiote_intenset = NRF_GPIOTE->INTENSET; NRF_GPIOTE->INTENCLR = NRF_GPIOTE->INTENSET; +#ifdef POWER_IRQ_VBUS_ABSENT // Configure VBUS_ABSENT (WAKE_ON_EDGE) pin to detect USB attach */ power_gpio_set_sense(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT), NRF_GPIO_PIN_SENSE_LOW); +#endif // POWER_IRQ_VBUS_ABSENT // Enable IRQ from RESET_BUTTON power_gpio_set_sense(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON), NRF_GPIO_PIN_SENSE_LOW); @@ -122,18 +148,34 @@ static void power_before(bool systemoff) NRF_GPIOTE->EVENTS_PORT = 0; NRF_GPIOTE->INTENSET = power_gpiote_intenset | ( GPIOTE_INTENSET_PORT_Set << GPIOTE_INTENSET_PORT_Pos); NVIC_EnableIRQ(GPIOTE_IRQn); + +#ifdef POWER_IRQ_USBDETECTED + // Enable NRF_POWER interrupt for USB detected/removed + NRF_POWER->INTENCLR = NRF_POWER->INTENSET; + NRF_POWER->INTENSET = POWER_INTENSET_USBDETECTED_Msk; + NVIC_EnableIRQ(POWER_CLOCK_IRQn); +#endif // POWER_IRQ_USBDETECTED } static void power_after() { +#ifdef POWER_IRQ_USBDETECTED + // Enable NRF_POWER interrupt for USB detected/removed + NRF_POWER->INTENCLR = NRF_POWER->INTENSET; + NRF_POWER->INTENSET = POWER_INTENSET_USBDETECTED_Msk | POWER_INTENSET_USBREMOVED_Msk; + NVIC_EnableIRQ(POWER_CLOCK_IRQn); +#endif // POWER_IRQ_USBDETECTED + // Restore GPIOTE state if (!power_gpiote_enabled) { NVIC_DisableIRQ(GPIOTE_IRQn); } NRF_GPIOTE->INTENCLR = NRF_GPIOTE->INTENSET; +#ifdef POWER_IRQ_VBUS_ABSENT // Configure VBUS_ABSENT (WAKE_ON_EDGE) pin to detect USB attach/detach */ power_gpio_set_sense_from_read(GPIO_REG(PIN_VBUS_ABSENT), GPIO_IDX(PIN_VBUS_ABSENT)); +#endif // POWER_IRQ_VBUS_ABSENT // Disable RESET_BUTTON edge events power_gpio_set_sense(GPIO_REG(RESET_BUTTON), GPIO_IDX(RESET_BUTTON), NRF_GPIO_PIN_NOSENSE); @@ -193,6 +235,7 @@ void GPIOTE_IRQHandler(void) wake_from_reset = 1; } +#ifdef POWER_IRQ_VBUS_ABSENT reg = GPIO_REG(PIN_VBUS_ABSENT); idx = GPIO_IDX(PIN_VBUS_ABSENT); if (reg->LATCH & (1 << idx)) { @@ -216,5 +259,28 @@ void GPIOTE_IRQHandler(void) wake_from_usb = 1; } } +#endif // POWER_IRQ_VBUS_ABSENT + } +} + + +#ifdef POWER_IRQ_USBDETECTED +void POWER_CLOCK_IRQHandler(void) +{ + if (NRF_POWER->EVENTS_USBDETECTED) { + NRF_POWER->EVENTS_USBDETECTED = 0; + power_source = pwr_mon_get_power_source(); + wake_from_usb = 1; + } + + if (NRF_POWER->EVENTS_USBREMOVED) { + NRF_POWER->EVENTS_USBREMOVED = 0; + power_source = pwr_mon_get_power_source(); + /* Reset USB on cable detach (VBUS falling edge) */ + USBD_Reset(); + usbd_reset_core(); + usb_pc_connected = false; + usb_state = USB_DISCONNECTED; } } +#endif // POWER_IRQ_USBDETECTED From 1b8a6f985c44f58f26c4213860b8f4fbf2572c34 Mon Sep 17 00:00:00 2001 From: Martin Williams Date: Wed, 24 Nov 2021 14:14:44 +0000 Subject: [PATCH 505/617] nrf52820_microbitv2: Use BOOTMODE pin to disable bootloader protection (#13) PR https://github.com/mathias-arm/DAPLink/pull/13 * microbit nRF528XX bootloader checks BOOTMODE pin * Ensure NFC pins are GPIO; prep to test TP1 * Remove debug code * Apply the flash protection if the NFC pins are not configured as GPIO * nrf52820_microbitv2: Remove unused macro in nrf52820_microbit_bl.c Co-authored-by: Carlos Pereira Atencio --- source/board/nrf52820_microbit_bl.c | 52 +++++++++++++++++++++++++---- 1 file changed, 46 insertions(+), 6 deletions(-) diff --git a/source/board/nrf52820_microbit_bl.c b/source/board/nrf52820_microbit_bl.c index 43de342a9..31f95db94 100644 --- a/source/board/nrf52820_microbit_bl.c +++ b/source/board/nrf52820_microbit_bl.c @@ -29,6 +29,14 @@ #include "device.h" #include "gpio.h" #include "nrf.h" +#include "nrf_nvmc.h" + +/* NFC configuration in the User UICR area, needed to configure NFC pins as GPIO */ +#define NRF52833_UICR_NFCPINS_OFFSET (0x20CUL) +#define NRF52833_UCIR_NFCPINS_ADDRESS (NRF_UICR_BASE + NRF52833_UICR_NFCPINS_OFFSET) +#define NRF52833_UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */ +#define NRF52833_UICR_NFCPINS_PROTECT_Msk (0x1UL << NRF52833_UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */ +#define NRF52833_UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation. */ // Warning - changing the interface start will break backwards compatibility COMPILER_ASSERT(DAPLINK_ROM_IF_START == 0x00008000); @@ -84,10 +92,42 @@ bool reset_button_pressed() bool board_bootloader_init() { - // Lock the bootloader flash, only protects until reset, - // so needs to be executed in the bootloader on every startup - uint8_t acl_region = 0; - NRF_ACL->ACL[acl_region].ADDR = DAPLINK_ROM_BL_START; - NRF_ACL->ACL[acl_region].SIZE = DAPLINK_ROM_BL_SIZE; - NRF_ACL->ACL[acl_region].PERM = ACL_ACL_PERM_WRITE_Disable << ACL_ACL_PERM_WRITE_Pos; + uint32_t apply_protection = 0; + + if (NRF_FICR->INFO.PART == 0x52833) { + // nRF52833 + // Apply the flash protection if the NFC pins are not configured as GPIO + volatile uint32_t* const nrf_uicr_nfcpins = (uint32_t *) NRF52833_UCIR_NFCPINS_ADDRESS; + if ((*nrf_uicr_nfcpins & NRF52833_UICR_NFCPINS_PROTECT_Msk) == + (NRF52833_UICR_NFCPINS_PROTECT_NFC << NRF52833_UICR_NFCPINS_PROTECT_Pos)) { + apply_protection = 1; + } + } + + if (!apply_protection) { + uint32_t pin_bootmode; + if (NRF_FICR->INFO.PART == 0x52833) { + // nRF52833 + pin_bootmode = NRF_GPIO_PIN_MAP(0, 10); + } else { + // nRF52820 + pin_bootmode = NRF_GPIO_PIN_MAP(0, 17); + } + + NRF_GPIO_Type *reg = GPIO_REG(pin_bootmode); + uint32_t idx = GPIO_IDX(pin_bootmode); + gpio_cfg_input(reg, idx, NRF_GPIO_PIN_PULLUP); + apply_protection = gpio_read(reg, idx); + gpio_cfg(reg, idx, NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); + } + + if (apply_protection) { + // Lock the bootloader flash, only protects until reset, + // so needs to be executed in the bootloader on every startup + uint8_t acl_region = 0; + NRF_ACL->ACL[acl_region].ADDR = DAPLINK_ROM_BL_START; + NRF_ACL->ACL[acl_region].SIZE = DAPLINK_ROM_BL_SIZE; + NRF_ACL->ACL[acl_region].PERM = ACL_ACL_PERM_WRITE_Disable << ACL_ACL_PERM_WRITE_Pos; + } } From 2f467bd05ed1e36128faf10d9ba8709ba5e3758d Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 24 Nov 2021 12:35:54 -0600 Subject: [PATCH 506/617] nrf52820_hic: ignore duplicate configuration calls --- source/hic_hal/nordic/nrf52820/uart.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/source/hic_hal/nordic/nrf52820/uart.c b/source/hic_hal/nordic/nrf52820/uart.c index cdc3512fd..2e14a93c7 100644 --- a/source/hic_hal/nordic/nrf52820/uart.c +++ b/source/hic_hal/nordic/nrf52820/uart.c @@ -42,6 +42,8 @@ circ_buf_t write_buffer; uint8_t write_buffer_data[BUFFER_SIZE]; circ_buf_t read_buffer; uint8_t read_buffer_data[BUFFER_SIZE]; +uint32_t cur_control; +uint32_t cur_baud; struct { // Number of bytes pending to be transferred. This is 0 if there is no @@ -65,6 +67,8 @@ int32_t uart_initialize(void) cb_buf.tx_size = 0; USART_INSTANCE.Initialize(uart_handler); USART_INSTANCE.PowerControl(ARM_POWER_FULL); + cur_control = 0; + cur_baud = 0; return 1; } @@ -156,6 +160,12 @@ int32_t uart_set_configuration(UART_Configuration *config) break; } + if ((control == cur_control) && (config->Baudrate == cur_baud)) { + return 1; + } + cur_control = control; + cur_baud = config->Baudrate; + NVIC_DisableIRQ(USART_IRQ); clear_buffers(); From 86f443497d603c4bd6f19a9abcd6b74c82e30801 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 16 Nov 2021 00:32:30 -0600 Subject: [PATCH 507/617] nrf52820_hic: Add call to nrfx_clock_enable() --- .../nordic/nrf52820/nrfx/drivers/nrfx_clock.c | 620 ++++++++++ .../nordic/nrf52820/nrfx/drivers/nrfx_clock.h | 367 ++++++ .../nrf52820/nrfx/drivers/nrfx_power_clock.h | 80 ++ .../nordic/nrf52820/nrfx/hal/nrf_clock.h | 1090 +++++++++++++++++ .../nrf52820/nrfx/nrfx_config_nrf52820.h | 2 +- source/hic_hal/nordic/nrf52820/sdk.c | 3 + 6 files changed, 2161 insertions(+), 1 deletion(-) create mode 100644 source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_clock.c create mode 100644 source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_clock.h create mode 100644 source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_power_clock.h create mode 100644 source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_clock.h diff --git a/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_clock.c b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_clock.c new file mode 100644 index 000000000..26ffc1bb3 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_clock.c @@ -0,0 +1,620 @@ +/* + * Copyright (c) 2016 - 2021, Nordic Semiconductor ASA + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#if NRFX_CHECK(NRFX_CLOCK_ENABLED) + +#include +#include + +#define NRFX_LOG_MODULE CLOCK +#include + +#if NRFX_CHECK(NRFX_POWER_ENABLED) +extern bool nrfx_power_irq_enabled; +#endif + +#if defined(CLOCK_LFCLKSRC_SRC_RC) || defined(__NRFX_DOXYGEN__) + #define LF_SRC_RC CLOCK_LFCLKSRC_SRC_RC +#else + #define LF_SRC_RC CLOCK_LFCLKSRC_SRC_LFRC +#endif + +#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) + #if (NRF_CLOCK_HAS_CALIBRATION == 0) + #error "Calibration is not available in the SoC that is used." + #endif + #if (NRFX_CLOCK_CONFIG_LF_SRC != LF_SRC_RC) + #error "Calibration can be performed only for the RC Oscillator." + #endif +#endif + +#if !defined(USE_WORKAROUND_FOR_ANOMALY_132) && \ + (defined(NRF52832_XXAA) || defined(NRF52832_XXAB)) + // ANOMALY 132 - LFCLK needs to avoid frame from 66us to 138us after LFCLK stop. This solution + // applies delay of 138us before starting LFCLK. + #define USE_WORKAROUND_FOR_ANOMALY_132 1 + + // Convert time to cycles (nRF52832 is clocked with 64 MHz, use delay of 138 us). + #define ANOMALY_132_DELAY_CYCLES (64UL * 138) +#endif + +#if !defined(USE_WORKAROUND_FOR_ANOMALY_192) && \ + (defined(NRF52810_XXAA) || \ + defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \ + defined(NRF52840_XXAA)) + // Enable workaround for nRF52 anomaly 192 (LFRC oscillator frequency is wrong + // after calibration, exceeding 500 ppm). + #define USE_WORKAROUND_FOR_ANOMALY_192 1 +#endif + +#if !defined(USE_WORKAROUND_FOR_ANOMALY_201) && \ + (defined(NRF52810_XXAA) || \ + defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \ + defined(NRF52840_XXAA)) + // Enable workaround for nRF52 anomaly 201 (EVENTS_HFCLKSTARTED might be generated twice). + #define USE_WORKAROUND_FOR_ANOMALY_201 1 +#endif + +#if defined(CLOCK_LFCLKSRC_SRC_Xtal) + #define LF_SRC_LFXO CLOCK_LFCLKSRC_SRC_Xtal +#else + #define LF_SRC_LFXO CLOCK_LFCLKSRC_SRC_LFXO +#endif + +#if defined(NRF_CLOCK_USE_EXTERNAL_LFCLK_SOURCES) + #define LF_SRC_XTAL_LOW (CLOCK_LFCLKSRC_SRC_Xtal | \ + (CLOCK_LFCLKSRC_EXTERNAL_Enabled << CLOCK_LFCLKSRC_EXTERNAL_Pos)) + #define LF_SRC_XTAL_FULL (CLOCK_LFCLKSRC_SRC_Xtal | \ + (CLOCK_LFCLKSRC_BYPASS_Enabled << CLOCK_LFCLKSRC_BYPASS_Pos) | \ + (CLOCK_LFCLKSRC_EXTERNAL_Enabled << CLOCK_LFCLKSRC_EXTERNAL_Pos)) +#else + #define LF_SRC_XTAL_LOW LF_SRC_LFXO + #define LF_SRC_XTAL_FULL LF_SRC_LFXO +#endif + +#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED) && \ + NRFX_CLOCK_CONFIG_LF_SRC != LF_SRC_LFXO && \ + NRFX_CLOCK_CONFIG_LF_SRC != LF_SRC_XTAL_LOW && \ + NRFX_CLOCK_CONFIG_LF_SRC != LF_SRC_XTAL_FULL + #error "Two-stage LFXO start procedure enabled but LFCLK source is not set to LFXO!" +#endif + +#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) +typedef enum +{ + CAL_STATE_IDLE, + CAL_STATE_CAL +} nrfx_clock_cal_state_t; +#endif + +/**@brief CLOCK control block. */ +typedef struct +{ + nrfx_clock_event_handler_t event_handler; + bool module_initialized; /*< Indicate the state of module */ +#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_201) + bool hfclk_started; /*< Anomaly 201 workaround. */ +#endif + +#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) + volatile nrfx_clock_cal_state_t cal_state; +#endif +} nrfx_clock_cb_t; + +static nrfx_clock_cb_t m_clock_cb; + +/** + * This variable is used to check whether common POWER_CLOCK common interrupt + * should be disabled or not if @ref nrfx_power tries to disable the interrupt. + */ +#if NRFX_CHECK(NRFX_POWER_ENABLED) +bool nrfx_clock_irq_enabled; +#endif + +#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_132) +/** + * @brief Function for applying delay of 138us before starting LFCLK. + */ +static void nrfx_clock_anomaly_132(void) +{ + uint32_t cyccnt_inital; + uint32_t core_debug; + uint32_t dwt_ctrl; + + // Preserve DEMCR register to do not influence into its configuration. Enable the trace and + // debug blocks. It is required to read and write data to DWT block. + core_debug = CoreDebug->DEMCR; + CoreDebug->DEMCR = core_debug | CoreDebug_DEMCR_TRCENA_Msk; + + // Preserve CTRL register in DWT block to do not influence into its configuration. Make sure + // that cycle counter is enabled. + dwt_ctrl = DWT->CTRL; + DWT->CTRL = dwt_ctrl | DWT_CTRL_CYCCNTENA_Msk; + + // Store start value of cycle counter. + cyccnt_inital = DWT->CYCCNT; + + // Delay required time. + while ((DWT->CYCCNT - cyccnt_inital) < ANOMALY_132_DELAY_CYCLES) + {} + + // Restore preserved registers. + DWT->CTRL = dwt_ctrl; + CoreDebug->DEMCR = core_debug; +} +#endif // NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_132) + +nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler) +{ + NRFX_ASSERT(event_handler); + + nrfx_err_t err_code = NRFX_SUCCESS; + if (m_clock_cb.module_initialized) + { + err_code = NRFX_ERROR_ALREADY_INITIALIZED; + } + else + { +#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) + m_clock_cb.cal_state = CAL_STATE_IDLE; +#endif + m_clock_cb.event_handler = event_handler; + m_clock_cb.module_initialized = true; +#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_201) + m_clock_cb.hfclk_started = false; +#endif + } + + NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; +} + +void nrfx_clock_enable(void) +{ + NRFX_ASSERT(m_clock_cb.module_initialized); + nrfx_power_clock_irq_init(); +#if !NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED) + nrf_clock_lf_src_set(NRF_CLOCK, (nrf_clock_lfclk_t)NRFX_CLOCK_CONFIG_LF_SRC); +#endif +#if NRF_CLOCK_HAS_HFCLKSRC + nrf_clock_hf_src_set(NRF_CLOCK, NRF_CLOCK_HFCLK_HIGH_ACCURACY); +#endif +#if NRF_CLOCK_HAS_HFCLK192M + nrf_clock_hfclk192m_src_set(NRF_CLOCK, (nrf_clock_hfclk_t)NRFX_CLOCK_CONFIG_HFCLK192M_SRC); +#endif +#if NRFX_CHECK(NRFX_POWER_ENABLED) + nrfx_clock_irq_enabled = true; +#endif + + NRFX_LOG_INFO("Module enabled."); +} + +void nrfx_clock_disable(void) +{ + NRFX_ASSERT(m_clock_cb.module_initialized); +#if NRFX_CHECK(NRFX_POWER_ENABLED) + NRFX_ASSERT(nrfx_clock_irq_enabled); + if (!nrfx_power_irq_enabled) +#endif + { + NRFX_IRQ_DISABLE(nrfx_get_irq_number(NRF_CLOCK)); + } + nrf_clock_int_disable(NRF_CLOCK, CLOCK_INTENSET_HFCLKSTARTED_Msk | + CLOCK_INTENSET_LFCLKSTARTED_Msk | +#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) + CLOCK_INTENSET_DONE_Msk | +#if NRF_HAS_CALIBRATION_TIMER + CLOCK_INTENSET_CTTO_Msk | +#endif +#endif // NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) + 0); +#if NRFX_CHECK(NRFX_POWER_ENABLED) + nrfx_clock_irq_enabled = false; +#endif + NRFX_LOG_INFO("Module disabled."); +} + +void nrfx_clock_uninit(void) +{ + NRFX_ASSERT(m_clock_cb.module_initialized); + nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK); + nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK); +#if NRF_CLOCK_HAS_HFCLK192M + nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK192M); +#endif +#if NRF_CLOCK_HAS_HFCLKAUDIO + nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLKAUDIO); +#endif + m_clock_cb.module_initialized = false; + NRFX_LOG_INFO("Uninitialized."); +} + +void nrfx_clock_start(nrf_clock_domain_t domain) +{ + NRFX_ASSERT(m_clock_cb.module_initialized); + switch (domain) + { + case NRF_CLOCK_DOMAIN_LFCLK: +#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED) + { + nrf_clock_lfclk_t lfclksrc; + if (nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc) && + lfclksrc == NRFX_CLOCK_CONFIG_LF_SRC) + { + // If the two-stage LFXO procedure has finished already + // use the configured LF clock source. + nrf_clock_lf_src_set(NRF_CLOCK, (nrf_clock_lfclk_t)NRFX_CLOCK_CONFIG_LF_SRC); + } + else + { + // If the two-stage LFXO procedure hasn't started yet + // or the RC stage is in progress, + // use the RC oscillator as LF clock source. + nrf_clock_lf_src_set(NRF_CLOCK, NRF_CLOCK_LFCLK_RC); + } + } +#endif // NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED) + nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED); + nrf_clock_int_enable(NRF_CLOCK, NRF_CLOCK_INT_LF_STARTED_MASK); +#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_132) + nrfx_clock_anomaly_132(); +#endif + nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_LFCLKSTART); + break; + case NRF_CLOCK_DOMAIN_HFCLK: + nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED); + nrf_clock_int_enable(NRF_CLOCK, NRF_CLOCK_INT_HF_STARTED_MASK); + nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTART); + break; +#if NRF_CLOCK_HAS_HFCLK192M + case NRF_CLOCK_DOMAIN_HFCLK192M: + nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLK192MSTARTED); + nrf_clock_int_enable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK); + nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLK192MSTART); + break; +#endif +#if NRF_CLOCK_HAS_HFCLKAUDIO + case NRF_CLOCK_DOMAIN_HFCLKAUDIO: + nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED); + nrf_clock_int_enable(NRF_CLOCK, NRF_CLOCK_INT_HFAUDIO_STARTED_MASK); + nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKAUDIOSTART); + break; +#endif + default: + NRFX_ASSERT(0); + break; + } +} + +void nrfx_clock_stop(nrf_clock_domain_t domain) +{ + NRFX_ASSERT(m_clock_cb.module_initialized); + switch (domain) + { + case NRF_CLOCK_DOMAIN_LFCLK: + nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_LF_STARTED_MASK); + nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED); + nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_LFCLKSTOP); + break; + case NRF_CLOCK_DOMAIN_HFCLK: + nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF_STARTED_MASK); + nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED); + nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTOP); + break; +#if NRF_CLOCK_HAS_HFCLK192M + case NRF_CLOCK_DOMAIN_HFCLK192M: + nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK); + nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLK192MSTARTED); + nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLK192MSTOP); + break; +#endif +#if NRF_CLOCK_HAS_HFCLKAUDIO + case NRF_CLOCK_DOMAIN_HFCLKAUDIO: + nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HFAUDIO_STARTED_MASK); + nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED); + nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKAUDIOSTOP); + break; +#endif + default: + NRFX_ASSERT(0); + return; + } + + bool stopped; + if (domain == NRF_CLOCK_DOMAIN_HFCLK) + { + nrf_clock_hfclk_t clk_src = NRF_CLOCK_HFCLK_HIGH_ACCURACY; + NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, &clk_src) || + (clk_src != NRF_CLOCK_HFCLK_HIGH_ACCURACY)), 10000, 1, stopped); + } + else + { + NRFX_WAIT_FOR(!nrfx_clock_is_running(domain, NULL), 10000, 1, stopped); + } + + if (!stopped) + { + NRFX_LOG_ERROR("Failed to stop clock domain: %d.", domain); + } + +#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_201) + if (domain == NRF_CLOCK_DOMAIN_HFCLK) + { + m_clock_cb.hfclk_started = false; + } +#endif +} + +nrfx_err_t nrfx_clock_calibration_start(void) +{ + nrfx_err_t err_code = NRFX_SUCCESS; + +#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) + nrf_clock_hfclk_t clk_src; + if (!nrfx_clock_is_running(NRF_CLOCK_DOMAIN_HFCLK, &clk_src)) + { + return NRFX_ERROR_INVALID_STATE; + } + + if (clk_src != NRF_CLOCK_HFCLK_HIGH_ACCURACY) + { + return NRFX_ERROR_INVALID_STATE; + } + + if (!nrfx_clock_is_running(NRF_CLOCK_DOMAIN_LFCLK, NULL)) + { + return NRFX_ERROR_INVALID_STATE; + } + + if (m_clock_cb.cal_state == CAL_STATE_IDLE) + { + nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_DONE); + nrf_clock_int_enable(NRF_CLOCK, NRF_CLOCK_INT_DONE_MASK); + m_clock_cb.cal_state = CAL_STATE_CAL; +#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_192) + *(volatile uint32_t *)0x40000C34 = 0x00000002; +#endif + nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_CAL); + } + else + { + err_code = NRFX_ERROR_BUSY; + } +#endif // NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) + + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; +} + +nrfx_err_t nrfx_clock_is_calibrating(void) +{ +#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) + if (m_clock_cb.cal_state == CAL_STATE_CAL) + { + return NRFX_ERROR_BUSY; + } +#endif + return NRFX_SUCCESS; +} + +void nrfx_clock_calibration_timer_start(uint8_t interval) +{ +#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) && NRF_CLOCK_HAS_CALIBRATION_TIMER + nrf_clock_cal_timer_timeout_set(NRF_CLOCK, interval); + nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_CTTO); + nrf_clock_int_enable(NRF_CLOCK, NRF_CLOCK_INT_CTTO_MASK); + nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_CTSTART); +#else + (void)interval; +#endif +} + +void nrfx_clock_calibration_timer_stop(void) +{ +#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) && NRF_CLOCK_HAS_CALIBRATION_TIMER + nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_CTTO_MASK); + nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_CTSTOP); +#endif +} + +#if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) || NRF_CLOCK_HAS_HFCLK192M +nrfx_err_t nrfx_clock_divider_set(nrf_clock_domain_t domain, + nrf_clock_hfclk_div_t div) +{ + switch(domain) + { +#if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) + case NRF_CLOCK_DOMAIN_HFCLK: + switch (div) + { + case NRF_CLOCK_HFCLK_DIV_2: +#if !defined(NRF_TRUSTZONE_NONSECURE) + if (nrf53_errata_4()) + { + NRFX_CRITICAL_SECTION_ENTER(); + __DSB(); + + nrf_clock_hfclk_div_set(NRF_CLOCK, div); + + *(volatile uint32_t *)0x5084450C = 0x0; + *(volatile uint32_t *)0x50026548 = 0x0; + *(volatile uint32_t *)0x50081EE4 = 0x0D; + + NRFX_CRITICAL_SECTION_EXIT(); + } + else +#endif + { + nrf_clock_hfclk_div_set(NRF_CLOCK, div); + } + break; + case NRF_CLOCK_HFCLK_DIV_1: +#if !defined(NRF_TRUSTZONE_NONSECURE) + if (nrf53_errata_4()) + { + NRFX_CRITICAL_SECTION_ENTER(); + __DSB(); + + *(volatile uint32_t *)0x5084450C = 0x4040; + *(volatile uint32_t *)0x50026548 = 0x40; + *(volatile uint32_t *)0x50081EE4 = 0x4D; + + nrf_clock_hfclk_div_set(NRF_CLOCK, div); + + NRFX_CRITICAL_SECTION_EXIT(); + } + else +#endif + { + nrf_clock_hfclk_div_set(NRF_CLOCK, div); + } + break; + default: + return NRFX_ERROR_INVALID_PARAM; + } + SystemCoreClockUpdate(); + return NRFX_SUCCESS; +#endif +#if NRF_CLOCK_HAS_HFCLK192M + case NRF_CLOCK_DOMAIN_HFCLK192M: + if (div > NRF_CLOCK_HFCLK_DIV_4) + { + return NRFX_ERROR_INVALID_PARAM; + } + else + { + nrf_clock_hfclk192m_div_set(NRF_CLOCK, div); + } + return NRFX_SUCCESS; +#endif + default: + NRFX_ASSERT(0); + return NRFX_ERROR_NOT_SUPPORTED; + } +} +#endif + +void nrfx_clock_irq_handler(void) +{ + if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED)) + { + nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED); + NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_HFCLKSTARTED"); + nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF_STARTED_MASK); + +#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_201) + if (!m_clock_cb.hfclk_started) + { + m_clock_cb.hfclk_started = true; + m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED); + } +#else + m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK_STARTED); +#endif + } + if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED)) + { + nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED); + NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED"); + +#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED) + nrf_clock_lfclk_t lfclksrc; + (void)nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc); + if (lfclksrc == NRF_CLOCK_LFCLK_RC) + { + // After the LFRC oscillator start switch to external source. + nrf_clock_lf_src_set(NRF_CLOCK, (nrf_clock_lfclk_t)NRFX_CLOCK_CONFIG_LF_SRC); + nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_LFCLKSTART); + } + else +#endif + { + // After the LF clock external source start invoke user callback. + nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_LF_STARTED_MASK); + m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED); + } + } + +#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) +#if NRF_CLOCK_HAS_CALIBRATION_TIMER + if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_CTTO)) + { + nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_CTTO); + NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_CTTO"); + nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_CTTO_MASK); + + m_clock_cb.event_handler(NRFX_CLOCK_EVT_CTTO); + } +#endif // NRF_CLOCK_HAS_CALIBRATION_TIMER + + if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_DONE)) + { +#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_192) + *(volatile uint32_t *)0x40000C34 = 0x00000000; +#endif + nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_DONE); + NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_DONE"); + nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_DONE_MASK); + m_clock_cb.cal_state = CAL_STATE_IDLE; + m_clock_cb.event_handler(NRFX_CLOCK_EVT_CAL_DONE); + } +#endif // NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) + +#if NRF_CLOCK_HAS_HFCLKAUDIO + if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED)) + { + nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED); + NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED"); + nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HFAUDIO_STARTED_MASK); + + m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLKAUDIO_STARTED); + } +#endif + +#if NRF_CLOCK_HAS_HFCLK192M + if (nrf_clock_event_check(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLK192MSTARTED)) + { + nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLK192MSTARTED); + NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_HFCLK192MSTARTED"); + nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK); + + m_clock_cb.event_handler(NRFX_CLOCK_EVT_HFCLK192M_STARTED); + } +#endif +} + +#endif // NRFX_CHECK(NRFX_CLOCK_ENABLED) diff --git a/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_clock.h b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_clock.h new file mode 100644 index 000000000..294fa5a30 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_clock.h @@ -0,0 +1,367 @@ +/* + * Copyright (c) 2016 - 2021, Nordic Semiconductor ASA + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_CLOCK_H__ +#define NRFX_CLOCK_H__ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_clock CLOCK driver + * @{ + * @ingroup nrf_clock + * @brief CLOCK peripheral driver. + */ + +/** @brief Clock events. */ +typedef enum +{ + NRFX_CLOCK_EVT_HFCLK_STARTED, ///< HFCLK has been started. + NRFX_CLOCK_EVT_LFCLK_STARTED, ///< LFCLK has been started. + NRFX_CLOCK_EVT_CTTO, ///< Calibration timeout. + NRFX_CLOCK_EVT_CAL_DONE, ///< Calibration has been done. + NRFX_CLOCK_EVT_HFCLKAUDIO_STARTED, ///< HFCLKAUDIO has been started. + NRFX_CLOCK_EVT_HFCLK192M_STARTED, ///< HFCLK192M has been started. +} nrfx_clock_evt_type_t; + +/** + * @brief Clock event handler. + * + * @param[in] event Event. + */ +typedef void (*nrfx_clock_event_handler_t)(nrfx_clock_evt_type_t event); + +/** + * @brief Function for initializing internal structures in the nrfx_clock module. + * + * After initialization, the module is in power off state (clocks are not started). + * + * @param[in] event_handler Event handler provided by the user. + * Must not be NULL. + * + * @retval NRFX_SUCCESS The procedure is successful. + * @retval NRFX_ERROR_ALREADY_INITIALIZED The driver is already initialized. + */ +nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler); + +/** @brief Function for enabling interrupts in the clock module. */ +void nrfx_clock_enable(void); + +/** @brief Function for disabling interrupts in the clock module. */ +void nrfx_clock_disable(void); + +/** @brief Function for uninitializing the clock module. */ +void nrfx_clock_uninit(void); + +/** + * @brief Function for starting the specified clock domain. + * + * @param[in] domain Clock domain. + */ +void nrfx_clock_start(nrf_clock_domain_t domain); + +/** + * @brief Function for stopping the specified clock domain. + * + * @param[in] domain Clock domain. + */ +void nrfx_clock_stop(nrf_clock_domain_t domain); + +/** + * @brief Function for checking the specified clock domain state. + * + * XTAL source is assumed for domains with multiple sources. + * + * @param[in] domain Clock domain. + * @param[out] p_clk_src Pointer to a clock source that is running. Set to NULL if not needed. + * Ignored for HFCLKAUDIO domain. Variable pointed by @p p_clk_src + * must be of either @ref nrf_clock_lfclk_t type for LFCLK + * or @ref nrf_clock_hfclk_t type for HFCLK and HFCLK192M. + * + * @retval true The clock domain is running. + * @retval false The clock domain is not running. + */ +NRFX_STATIC_INLINE bool nrfx_clock_is_running(nrf_clock_domain_t domain, void * p_clk_src); + +#if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) || NRF_CLOCK_HAS_HFCLK_192M +/** + * @brief Function for setting the specified clock domain divider. + * + * @param[in] domain Clock domain. + * @param[in] div New divider for the clock domain. + * + * @retval NRFX_SUCCESS Divider successfully set. + * @retval NRFX_ERROR_NOT_SUPPORTED Domain does not support setting the divider. + * @retval NRFX_ERROR_INVALID_PARAM Divider not supported by the specified domain. + */ +nrfx_err_t nrfx_clock_divider_set(nrf_clock_domain_t domain, + nrf_clock_hfclk_div_t div); + +/** + * @brief Function for getting the specified clock domain divider. + * + * @param[in] domain Clock domain. + * + * @return Current divider for the specified clock domain. + */ + +NRFX_STATIC_INLINE nrf_clock_hfclk_div_t nrfx_clock_divider_get(nrf_clock_domain_t domain); +#endif + +/** + * @brief Function for starting the LFCLK. + * + * @note This function is deprecated. Use @ref nrfx_clock_start instead. + */ +NRFX_STATIC_INLINE void nrfx_clock_lfclk_start(void); + +/** + * @brief Function for stopping the LFCLK. + * + * @note This function is deprecated. Use @ref nrfx_clock_stop instead. + */ +NRFX_STATIC_INLINE void nrfx_clock_lfclk_stop(void); + +/** + * @brief Function for checking the LFCLK state. + * + * @note This function is deprecated. Use @ref nrfx_clock_is_running instead. + * + * @retval true The LFCLK is running. + * @retval false The LFCLK is not running. + */ +NRFX_STATIC_INLINE bool nrfx_clock_lfclk_is_running(void); + +/** + * @brief Function for starting the high-accuracy source HFCLK. + * + * @note This function is deprecated. Use @ref nrfx_clock_start instead. + */ +NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void); + +/** + * @brief Function for stopping the external high-accuracy source HFCLK. + * + * @note This function is deprecated. Use @ref nrfx_clock_stop instead. + */ +NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void); + +/** + * @brief Function for checking the HFCLK state. + * + * @note This function is deprecated. Use @ref nrfx_clock_is_running instead. + * + * @retval true The HFCLK is running (XTAL source). + * @retval false The HFCLK is not running. + */ +NRFX_STATIC_INLINE bool nrfx_clock_hfclk_is_running(void); + + +#if NRF_CLOCK_HAS_HFCLKAUDIO +/** + * @brief Function for setting the HFCLKAUDIO configuration. + * + * The frequency of HFCLKAUDIO ranges from 10.666 MHz to 13.333 MHz in 40.7 Hz steps. + * To calculate @p freq_value corresponding to the chosen frequency, use the following equation: + * FREQ_VALUE = 2^16 * ((12 * f_out / 32M) - 4) + * + * @warning Chosen frequency must fit in 11.176 MHz - 11.402 MHz or 12.165 MHz - 12.411 MHz + * frequency bands. + * + * @param[in] freq_value New FREQ_VALUE for HFCLKAUDIO. + */ +NRFX_STATIC_INLINE void nrfx_clock_hfclkaudio_config_set(uint16_t freq_value); + +/** + * @brief Function for getting the HFCLKAUDIO configuration. + * + * The frequency of HFCLKAUDIO ranges from 10.666 MHz to 13.333 MHz in 40.7 Hz steps. + * To calculate frequency corresponding to the returned FREQ_VALUE, use the following equation: + * f_out = 32M * (4 + FREQ_VALUE * 2^(-16))/12 + * + * @return Current value of FREQ_VALUE for HFCLKAUDIO. + */ +NRFX_STATIC_INLINE uint16_t nrfx_clock_hfclkaudio_config_get(void); + +#endif + +/** + * @brief Function for starting the calibration of internal LFCLK. + * + * This function starts the calibration process. The process cannot be aborted. LFCLK and HFCLK + * must be running before this function is called. + * + * @retval NRFX_SUCCESS The procedure is successful. + * @retval NRFX_ERROR_INVALID_STATE The low-frequency of high-frequency clock is off. + * @retval NRFX_ERROR_BUSY Clock is in the calibration phase. + */ +nrfx_err_t nrfx_clock_calibration_start(void); + +/** + * @brief Function for checking if calibration is in progress. + * + * This function indicates that the system is in calibration phase. + * + * @retval NRFX_SUCCESS The procedure is successful. + * @retval NRFX_ERROR_BUSY Clock is in the calibration phase. + */ +nrfx_err_t nrfx_clock_is_calibrating(void); + +/** + * @brief Function for starting calibration timer. + * + * @param[in] interval Time after which the CTTO event and interrupt will be generated (in 0.25 s units). + */ +void nrfx_clock_calibration_timer_start(uint8_t interval); + +/** @brief Function for stopping the calibration timer. */ +void nrfx_clock_calibration_timer_stop(void); + +/**@brief Function for returning a requested task address for the clock driver module. + * + * @param[in] task One of the peripheral tasks. + * + * @return Task address. + */ +NRFX_STATIC_INLINE uint32_t nrfx_clock_ppi_task_addr(nrf_clock_task_t task); + +/**@brief Function for returning a requested event address for the clock driver module. + * + * @param[in] event One of the peripheral events. + * + * @return Event address. + */ +NRFX_STATIC_INLINE uint32_t nrfx_clock_ppi_event_addr(nrf_clock_event_t event); + +#ifndef NRFX_DECLARE_ONLY + +#if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) || NRF_CLOCK_HAS_HFCLK_192M +NRFX_STATIC_INLINE nrf_clock_hfclk_div_t nrfx_clock_divider_get(nrf_clock_domain_t domain) +{ + switch (domain) + { +#if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) + case NRF_CLOCK_DOMAIN_HFCLK: + return nrf_clock_hfclk_div_get(NRF_CLOCK); +#endif +#if NRF_CLOCK_HAS_HFCLK192M + case NRF_CLOCK_DOMAIN_HFCLK192M: + return nrf_clock_hfclk192m_div_get(NRF_CLOCK); +#endif + default: + NRFX_ASSERT(0); + return (nrf_clock_hfclk_div_t)0; + } +} +#endif // defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) || NRF_CLOCK_HAS_HFCLK_192M + +NRFX_STATIC_INLINE void nrfx_clock_lfclk_start(void) +{ + nrfx_clock_start(NRF_CLOCK_DOMAIN_LFCLK); +} + +NRFX_STATIC_INLINE void nrfx_clock_lfclk_stop(void) +{ + nrfx_clock_stop(NRF_CLOCK_DOMAIN_LFCLK); +} + +NRFX_STATIC_INLINE void nrfx_clock_hfclk_start(void) +{ + nrfx_clock_start(NRF_CLOCK_DOMAIN_HFCLK); +} + +NRFX_STATIC_INLINE void nrfx_clock_hfclk_stop(void) +{ + nrfx_clock_stop(NRF_CLOCK_DOMAIN_HFCLK); +} + +NRFX_STATIC_INLINE uint32_t nrfx_clock_ppi_task_addr(nrf_clock_task_t task) +{ + return nrf_clock_task_address_get(NRF_CLOCK, task); +} + +NRFX_STATIC_INLINE uint32_t nrfx_clock_ppi_event_addr(nrf_clock_event_t event) +{ + return nrf_clock_event_address_get(NRF_CLOCK, event); +} + +NRFX_STATIC_INLINE bool nrfx_clock_is_running(nrf_clock_domain_t domain, void * p_clk_src) +{ + return nrf_clock_is_running(NRF_CLOCK, domain, p_clk_src); +} + +NRFX_STATIC_INLINE bool nrfx_clock_hfclk_is_running(void) +{ + nrf_clock_hfclk_t clk_src; + bool ret = nrfx_clock_is_running(NRF_CLOCK_DOMAIN_HFCLK, &clk_src); + return (ret && (clk_src == NRF_CLOCK_HFCLK_HIGH_ACCURACY)); +} + +NRFX_STATIC_INLINE bool nrfx_clock_lfclk_is_running(void) +{ + return nrfx_clock_is_running(NRF_CLOCK_DOMAIN_LFCLK, NULL); +} + +#if NRF_CLOCK_HAS_HFCLKAUDIO + +NRFX_STATIC_INLINE void nrfx_clock_hfclkaudio_config_set(uint16_t freq_value) +{ + nrf_clock_hfclkaudio_config_set(NRF_CLOCK, freq_value); +} + +NRFX_STATIC_INLINE uint16_t nrfx_clock_hfclkaudio_config_get(void) +{ + return nrf_clock_hfclkaudio_config_get(NRF_CLOCK); +} + +#endif + +#endif // NRFX_DECLARE_ONLY + +/** @} */ + + +void nrfx_clock_irq_handler(void); + + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_CLOCK_H__ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_power_clock.h b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_power_clock.h new file mode 100644 index 000000000..ad6fbfed1 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx/drivers/nrfx_power_clock.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_POWER_CLOCK_H__ +#define NRFX_POWER_CLOCK_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +__STATIC_INLINE void nrfx_power_clock_irq_init(void) +{ + uint8_t priority; +#if NRFX_CHECK(NRFX_POWER_ENABLED) && NRFX_CHECK(NRFX_CLOCK_ENABLED) + #if NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY != NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY + #error "IRQ priorities for POWER and CLOCK must be the same. Check ." + #endif + priority = NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY; +#elif NRFX_CHECK(NRFX_POWER_ENABLED) + priority = NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY; +#elif NRFX_CHECK(NRFX_CLOCK_ENABLED) + priority = NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY; +#else + #error "This code is not supposed to be compiled when neither POWER nor CLOCK is enabled." +#endif + + if (!NRFX_IRQ_IS_ENABLED(nrfx_get_irq_number(NRF_CLOCK))) + { + NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_CLOCK), priority); + NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_CLOCK)); + } +} + +#if NRFX_CHECK(NRFX_POWER_ENABLED) && NRFX_CHECK(NRFX_CLOCK_ENABLED) +void nrfx_power_clock_irq_handler(void); +#elif NRFX_CHECK(NRFX_POWER_ENABLED) +#define nrfx_power_irq_handler nrfx_power_clock_irq_handler +#elif NRFX_CHECK(NRFX_CLOCK_ENABLED) +#define nrfx_clock_irq_handler nrfx_power_clock_irq_handler +#endif + + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_POWER_CLOCK_H__ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_clock.h b/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_clock.h new file mode 100644 index 000000000..3a934d7a1 --- /dev/null +++ b/source/hic_hal/nordic/nrf52820/nrfx/hal/nrf_clock.h @@ -0,0 +1,1090 @@ +/* + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_CLOCK_H__ +#define NRF_CLOCK_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_clock_hal Clock HAL + * @{ + * @ingroup nrf_clock + * @brief Hardware access layer for managing the CLOCK peripheral. + * + * This code can be used to manage low-frequency clock (LFCLK), high-frequency clock (HFCLK), + * high-frequency 192 MHz clock (HFCLK192M) and high-frequency audio clock (HFCLKAUDIO) + * settings. + */ + +#if defined(CLOCK_LFCLKSRC_BYPASS_Msk) && defined(CLOCK_LFCLKSRC_EXTERNAL_Msk) +// Enable support for external LFCLK sources. Read more in the Product Specification. +#define NRF_CLOCK_USE_EXTERNAL_LFCLK_SOURCES +#endif + +#if defined(CLOCK_INTENSET_DONE_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Presence of the Low Frequency Clock calibration. */ +#define NRF_CLOCK_HAS_CALIBRATION 1 +#else +#define NRF_CLOCK_HAS_CALIBRATION 0 +#endif + +#if defined(CLOCK_CTIV_CTIV_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Presence of the Low Frequency Clock calibration timer. */ +#define NRF_CLOCK_HAS_CALIBRATION_TIMER 1 +#else +#define NRF_CLOCK_HAS_CALIBRATION_TIMER 0 +#endif + +#if (defined(CLOCK_INTENSET_HFCLK192MSTARTED_Msk) && !defined(NRF5340_XXAA_NETWORK)) \ + || defined(__NRFX_DOXYGEN__) +/** @brief Presence of the 192 MHz clock. */ +#define NRF_CLOCK_HAS_HFCLK192M 1 +#else +#define NRF_CLOCK_HAS_HFCLK192M 0 +#endif + +#if (defined(CLOCK_INTENSET_HFCLKAUDIOSTARTED_Msk) && !defined(NRF5340_XXAA_NETWORK)) \ + || defined(__NRFX_DOXYGEN__) +/** @brief Presence of the Audio clock. */ +#define NRF_CLOCK_HAS_HFCLKAUDIO 1 +#else +#define NRF_CLOCK_HAS_HFCLKAUDIO 0 +#endif + +#if defined(CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Presence of ALWAYSRUN registers. */ +#define NRF_CLOCK_HAS_ALWAYSRUN 1 +#else +#define NRF_CLOCK_HAS_ALWAYSRUN 0 +#endif + +#if defined(CLOCK_HFCLKSRC_SRC_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Presence of HFCLKSRC register. */ +#define NRF_CLOCK_HAS_HFCLKSRC 1 +#else +#define NRF_CLOCK_HAS_HFCLKSRC 0 +#endif + +/** + * @brief Low-frequency clock sources. + * @details Used by LFCLKSRC, LFCLKSTAT, and LFCLKSRCCOPY registers. + */ +typedef enum +{ +#if defined(CLOCK_LFCLKSRC_SRC_LFULP) || defined(__NRFX_DOXYGEN__) + NRF_CLOCK_LFCLK_LFULP = CLOCK_LFCLKSRC_SRC_LFULP, /**< Internal 32 kHz Ultra-low power oscillator. */ +#endif + +#if defined(CLOCK_LFCLKSRC_SRC_RC) || defined(__NRFX_DOXYGEN__) + NRF_CLOCK_LFCLK_RC = CLOCK_LFCLKSRC_SRC_RC, /**< Internal 32 kHz RC oscillator. */ +#else + NRF_CLOCK_LFCLK_RC = CLOCK_LFCLKSRC_SRC_LFRC, /**< Internal 32 kHz RC oscillator. */ +#endif + +#if defined(CLOCK_LFCLKSRC_SRC_Xtal) || defined(__NRFX_DOXYGEN__) + NRF_CLOCK_LFCLK_Xtal = CLOCK_LFCLKSRC_SRC_Xtal, /**< External 32 kHz crystal. */ +#else + NRF_CLOCK_LFCLK_Xtal = CLOCK_LFCLKSRC_SRC_LFXO, /**< External 32 kHz crystal. */ +#endif + +#if defined(CLOCK_LFCLKSRC_SRC_Synth) || defined(__NRFX_DOXYGEN__) + NRF_CLOCK_LFCLK_Synth = CLOCK_LFCLKSRC_SRC_Synth, /**< Internal 32 kHz synthesized from HFCLK system clock. */ +#elif defined(CLOCK_LFCLKSRC_SRC_LFSYNT) + NRF_CLOCK_LFCLK_Synth = CLOCK_LFCLKSRC_SRC_LFSYNT, /**< Internal 32 kHz synthesized from HFCLK system clock. */ +#endif + +#if defined(NRF_CLOCK_USE_EXTERNAL_LFCLK_SOURCES) || defined(__NRFX_DOXYGEN__) + /** + * External 32 kHz low swing signal. Used only with the LFCLKSRC register. + * For the others @ref NRF_CLOCK_LFCLK_Xtal is returned for this setting. + */ + NRF_CLOCK_LFCLK_Xtal_Low_Swing = (CLOCK_LFCLKSRC_SRC_Xtal | + (CLOCK_LFCLKSRC_EXTERNAL_Enabled << CLOCK_LFCLKSRC_EXTERNAL_Pos)), + /** + * External 32 kHz full swing signal. Used only with the LFCLKSRC register. + * For the others @ref NRF_CLOCK_LFCLK_Xtal is returned for this setting. + */ + NRF_CLOCK_LFCLK_Xtal_Full_Swing = (CLOCK_LFCLKSRC_SRC_Xtal | + (CLOCK_LFCLKSRC_BYPASS_Enabled << CLOCK_LFCLKSRC_BYPASS_Pos) | + (CLOCK_LFCLKSRC_EXTERNAL_Enabled << CLOCK_LFCLKSRC_EXTERNAL_Pos)), +#endif // defined(NRF_CLOCK_USE_EXTERNAL_LFCLK_SOURCES) || defined(__NRFX_DOXYGEN__) +} nrf_clock_lfclk_t; + +/** + * @brief High-frequency clock sources. + * @details Used by HFCLKSTAT and HFCLK192MSTAT registers. + */ +typedef enum +{ +#if defined(CLOCK_HFCLKSTAT_SRC_RC) || defined(__NRFX_DOXYGEN__) + NRF_CLOCK_HFCLK_LOW_ACCURACY = CLOCK_HFCLKSTAT_SRC_RC, /**< Internal 16 MHz RC oscillator. */ +#elif defined(CLOCK_HFCLKSTAT_SRC_HFINT) + NRF_CLOCK_HFCLK_LOW_ACCURACY = CLOCK_HFCLKSTAT_SRC_HFINT, /**< Internal 16 MHz RC oscillator. */ +#endif +#if defined(CLOCK_HFCLKSTAT_SRC_Xtal) || defined(__NRFX_DOXYGEN__) + NRF_CLOCK_HFCLK_HIGH_ACCURACY = CLOCK_HFCLKSTAT_SRC_Xtal /**< External 16 MHz/32 MHz crystal oscillator. */ +#else + NRF_CLOCK_HFCLK_HIGH_ACCURACY = CLOCK_HFCLKSTAT_SRC_HFXO /**< External 32 MHz crystal oscillator. */ +#endif +} nrf_clock_hfclk_t; + +/** @brief Clock domains. */ +typedef enum +{ + NRF_CLOCK_DOMAIN_LFCLK, + NRF_CLOCK_DOMAIN_HFCLK, +#if NRF_CLOCK_HAS_HFCLK192M + NRF_CLOCK_DOMAIN_HFCLK192M, +#endif +#if NRF_CLOCK_HAS_HFCLKAUDIO + NRF_CLOCK_DOMAIN_HFCLKAUDIO, +#endif +} nrf_clock_domain_t; + +#if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) || NRF_CLOCK_HAS_HFCLK192M +/** + * @brief High-frequency clock frequency configuration. + * @details Used by HFCLKCTRL and HFCLK192MCTRL registers. + */ +typedef enum +{ + NRF_CLOCK_HFCLK_DIV_1 = CLOCK_HFCLKCTRL_HCLK_Div1, /**< Divide HFCLK/HFCLK192M by 1 */ + NRF_CLOCK_HFCLK_DIV_2 = CLOCK_HFCLKCTRL_HCLK_Div2, /**< Divide HFCLK/HFCLK192M by 2 */ +#if NRF_CLOCK_HAS_HFCLK192M + NRF_CLOCK_HFCLK_DIV_4 = CLOCK_HFCLK192MCTRL_HCLK192M_Div4, /**< Divide HFCLK192M by 4 */ +#endif +} nrf_clock_hfclk_div_t; +#endif // defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) || NRF_CLOCK_HAS_HFCLK192M + +/** + * @brief Trigger status of task LFCLKSTART/HFCLKSTART. + * + * @note This enum is deprecated. + * + * @details Used by LFCLKRUN and HFCLKRUN registers. + */ +typedef enum +{ + NRF_CLOCK_START_TASK_NOT_TRIGGERED = CLOCK_LFCLKRUN_STATUS_NotTriggered, /**< Task LFCLKSTART/HFCLKSTART has not been triggered. */ + NRF_CLOCK_START_TASK_TRIGGERED = CLOCK_LFCLKRUN_STATUS_Triggered /**< Task LFCLKSTART/HFCLKSTART has been triggered. */ +} nrf_clock_start_task_status_t; + +/** @brief Interrupts. */ +typedef enum +{ + NRF_CLOCK_INT_HF_STARTED_MASK = CLOCK_INTENSET_HFCLKSTARTED_Msk, /**< Interrupt on HFCLKSTARTED event. */ + NRF_CLOCK_INT_LF_STARTED_MASK = CLOCK_INTENSET_LFCLKSTARTED_Msk, /**< Interrupt on LFCLKSTARTED event. */ +#if NRF_CLOCK_HAS_CALIBRATION + NRF_CLOCK_INT_DONE_MASK = CLOCK_INTENSET_DONE_Msk, /**< Interrupt on DONE event. */ +#endif +#if NRF_CLOCK_HAS_CALIBRATION_TIMER + NRF_CLOCK_INT_CTTO_MASK = CLOCK_INTENSET_CTTO_Msk, /**< Interrupt on CTTO event. */ +#endif +#if defined(CLOCK_INTENSET_CTSTARTED_Msk) || defined(__NRFX_DOXYGEN__) + NRF_CLOCK_INT_CTSTARTED_MASK = CLOCK_INTENSET_CTSTARTED_Msk, /**< Interrupt on CTSTARTED event. */ + NRF_CLOCK_INT_CTSTOPPED_MASK = CLOCK_INTENSET_CTSTOPPED_Msk /**< Interrupt on CTSTOPPED event. */ +#endif +#if NRF_CLOCK_HAS_HFCLKAUDIO + NRF_CLOCK_INT_HFAUDIO_STARTED_MASK = CLOCK_INTENSET_HFCLKAUDIOSTARTED_Msk, /**< Interrupt on HFCLKAUDIOSTARTED event. */ +#endif + +#if NRF_CLOCK_HAS_HFCLK192M + NRF_CLOCK_INT_HF192M_STARTED_MASK = CLOCK_INTENSET_HFCLK192MSTARTED_Msk, /**< Interrupt on HFCLK192MSTARTED event. */ +#endif +} nrf_clock_int_mask_t; + +/** + * @brief Tasks. + * + * @details The NRF_CLOCK_TASK_LFCLKSTOP task cannot be set when the low-frequency clock is not running. + * The NRF_CLOCK_TASK_HFCLKSTOP task cannot be set when the high-frequency clock is not running. + */ +typedef enum +{ + NRF_CLOCK_TASK_HFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTART), /**< Start HFCLK clock source. */ + NRF_CLOCK_TASK_HFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTOP), /**< Stop HFCLK clock source. */ + NRF_CLOCK_TASK_LFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTART), /**< Start LFCLK clock source. */ + NRF_CLOCK_TASK_LFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTOP), /**< Stop LFCLK clock source. */ +#if NRF_CLOCK_HAS_CALIBRATION + NRF_CLOCK_TASK_CAL = offsetof(NRF_CLOCK_Type, TASKS_CAL), /**< Start calibration of LFCLK RC oscillator. */ +#endif +#if NRF_CLOCK_HAS_CALIBRATION_TIMER + NRF_CLOCK_TASK_CTSTART = offsetof(NRF_CLOCK_Type, TASKS_CTSTART), /**< Start calibration timer. */ + NRF_CLOCK_TASK_CTSTOP = offsetof(NRF_CLOCK_Type, TASKS_CTSTOP) /**< Stop calibration timer. */ +#endif +#if NRF_CLOCK_HAS_HFCLKAUDIO + NRF_CLOCK_TASK_HFCLKAUDIOSTART = offsetof(NRF_CLOCK_Type, TASKS_HFCLKAUDIOSTART), /**< Start HFCLKAUDIO clock source. */ + NRF_CLOCK_TASK_HFCLKAUDIOSTOP = offsetof(NRF_CLOCK_Type, TASKS_HFCLKAUDIOSTOP), /**< Stop HFCLKAUDIO clock source. */ +#endif +#if NRF_CLOCK_HAS_HFCLK192M + NRF_CLOCK_TASK_HFCLK192MSTART = offsetof(NRF_CLOCK_Type, TASKS_HFCLK192MSTART), /**< Start HFCLK192M clock source. */ + NRF_CLOCK_TASK_HFCLK192MSTOP = offsetof(NRF_CLOCK_Type, TASKS_HFCLK192MSTOP), /**< Stop HFCLK192M clock source. */ +#endif +} nrf_clock_task_t; + +/** @brief Events. */ +typedef enum +{ + NRF_CLOCK_EVENT_HFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_HFCLKSTARTED), /**< HFCLK oscillator started. */ + NRF_CLOCK_EVENT_LFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_LFCLKSTARTED), /**< LFCLK oscillator started. */ +#if NRF_CLOCK_HAS_CALIBRATION + NRF_CLOCK_EVENT_DONE = offsetof(NRF_CLOCK_Type, EVENTS_DONE), /**< Calibration of LFCLK RC oscillator completed. */ +#endif +#if NRF_CLOCK_HAS_CALIBRATION_TIMER + NRF_CLOCK_EVENT_CTTO = offsetof(NRF_CLOCK_Type, EVENTS_CTTO), /**< Calibration timer time-out. */ +#endif +#if defined(CLOCK_INTENSET_CTSTARTED_Msk) || defined(__NRFX_DOXYGEN__) + NRF_CLOCK_EVENT_CTSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_CTSTARTED), /**< Calibration timer started. */ + NRF_CLOCK_EVENT_CTSTOPPED = offsetof(NRF_CLOCK_Type, EVENTS_CTSTOPPED) /**< Calibration timer stopped. */ +#endif +#if NRF_CLOCK_HAS_HFCLKAUDIO + NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_HFCLKAUDIOSTARTED), /**< HFCLKAUDIO oscillator started. */ +#endif +#if NRF_CLOCK_HAS_HFCLK192M + NRF_CLOCK_EVENT_HFCLK192MSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_HFCLK192MSTARTED), /**< HFCLK192M oscillator started. */ +#endif +} nrf_clock_event_t; + +/** + * @brief Function for enabling the specified interrupt. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mask Mask of interrupts to be enabled. + */ +NRF_STATIC_INLINE void nrf_clock_int_enable(NRF_CLOCK_Type * p_reg, uint32_t mask); + +/** + * @brief Function for disabling the specified interrupt. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mask Mask of interrupts to be disabled. + */ +NRF_STATIC_INLINE void nrf_clock_int_disable(NRF_CLOCK_Type * p_reg, uint32_t mask); + +/** + * @brief Function for checking if the specified interrupts are enabled. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mask Mask of interrupts to be checked. + * + * @return Mask of enabled interrupts. + */ +NRF_STATIC_INLINE uint32_t nrf_clock_int_enable_check(NRF_CLOCK_Type const * p_reg, uint32_t mask); + +/** + * @brief Function for retrieving the address of the specified task. + * @details This function can be used by the PPI module. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] task CLOCK Task. + * + * @return Address of the requested task register. + */ +NRF_STATIC_INLINE uint32_t nrf_clock_task_address_get(NRF_CLOCK_Type const * p_reg, + nrf_clock_task_t task); + +/** + * @brief Function for setting the specified task. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] task Task to be activated. + */ +NRF_STATIC_INLINE void nrf_clock_task_trigger(NRF_CLOCK_Type * p_reg, nrf_clock_task_t task); + +/** + * @brief Function for retrieving the address of the specified event. + * @details This function can be used by the PPI module. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] event CLOCK Event. + * + * @return Address of the specified event register. + */ +NRF_STATIC_INLINE uint32_t nrf_clock_event_address_get(NRF_CLOCK_Type const * p_reg, + nrf_clock_event_t event); + +/** + * @brief Function for clearing the specified event. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] event Event to clear. + */ +NRF_STATIC_INLINE void nrf_clock_event_clear(NRF_CLOCK_Type * p_reg, nrf_clock_event_t event); + +/** + * @brief Function for retrieving the state of the specified event. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] event Event to be checked. + * + * @retval true The event has been generated. + * @retval false The event has not been generated. + */ +NRF_STATIC_INLINE bool nrf_clock_event_check(NRF_CLOCK_Type const * p_reg, nrf_clock_event_t event); + +/** + * @brief Function for retrieving the trigger status of the task START for given domain. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] domain Clock domain. + * + * @retval false The task START for the given domain has not been triggered. + * @retval true The task START for the given domain has been triggered. + */ +NRF_STATIC_INLINE bool nrf_clock_start_task_check(NRF_CLOCK_Type const * p_reg, + nrf_clock_domain_t domain); + +/** + * @brief Function for retrieving the state of the clock. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] domain Clock domain. + * @param[out] p_clk_src Pointer to clock source that is running. Set to NULL if not needed. + * Ignored for HFCLKAUDIO domain. Variable pointed by @p p_clk_src + * must be of either @ref nrf_clock_lfclk_t type for LFCLK + * or @ref nrf_clock_hfclk_t type for HFCLK and HFCLK192M. + * + * @retval false The clock is not running. + * @retval true The clock is running. + */ +NRF_STATIC_INLINE bool nrf_clock_is_running(NRF_CLOCK_Type const * p_reg, + nrf_clock_domain_t domain, + void * p_clk_src); + +/** + * @brief Function for changing the low-frequency clock source. + * @details Check in Product Specification if this function can be called when + * the low-frequency clock is running. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] source New low-frequency clock source. + */ +NRF_STATIC_INLINE void nrf_clock_lf_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_lfclk_t source); + +/** + * @brief Function for retrieving the selected source for the low-frequency clock. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval NRF_CLOCK_LFCLK_RC The internal 32 kHz RC oscillator + * is the selected source for the low-frequency clock. + * @retval NRF_CLOCK_LFCLK_Xtal An external 32 kHz crystal oscillator + * is the selected source for the low-frequency clock. + * @retval NRF_CLOCK_LFCLK_Synth The internal 32 kHz synthesized from + * the HFCLK is the selected source for the low-frequency clock. + */ +NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(NRF_CLOCK_Type const * p_reg); + +/** + * @brief Function for retrieving the active source of the low-frequency clock. + * + * @note This function is deprecated. Use @ref nrf_clock_is_running instead. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval NRF_CLOCK_LFCLK_RC The internal 32 kHz RC oscillator + * is the active source of the low-frequency clock. + * @retval NRF_CLOCK_LFCLK_Xtal An external 32 kHz crystal oscillator + * is the active source of the low-frequency clock. + * @retval NRF_CLOCK_LFCLK_Synth The internal 32 kHz synthesized from + * the HFCLK is the active source of the low-frequency clock. + */ +NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(NRF_CLOCK_Type const * p_reg); + +/** + * @brief Function for retrieving the clock source for the LFCLK clock when + * the task LKCLKSTART is triggered. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval NRF_CLOCK_LFCLK_RC The internal 32 kHz RC oscillator + * is running and generating the LFCLK clock. + * @retval NRF_CLOCK_LFCLK_Xtal An external 32 kHz crystal oscillator + * is running and generating the LFCLK clock. + * @retval NRF_CLOCK_LFCLK_Synth The internal 32 kHz synthesized from + * the HFCLK is running and generating the LFCLK clock. + */ +NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg); + +/** + * @brief Function for retrieving the state of the LFCLK clock. + * + * @note This function is deprecated. Use @ref nrf_clock_is_running instead. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval false The LFCLK clock is not running. + * @retval true The LFCLK clock is running. + */ +NRF_STATIC_INLINE bool nrf_clock_lf_is_running(NRF_CLOCK_Type const * p_reg); + +/** + * @brief Function for retrieving the trigger status of the task LFCLKSTART. + * + * @note This function is deprecated. Use @ref nrf_clock_start_task_check instead. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED The task LFCLKSTART has not been triggered. + * @retval NRF_CLOCK_START_TASK_TRIGGERED The task LFCLKSTART has been triggered. + */ +NRF_STATIC_INLINE +nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(NRF_CLOCK_Type const * p_reg); + +#if NRF_CLOCK_HAS_HFCLKSRC +/** + * @brief Function for changing the high-frequency clock source. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] source New high-frequency clock source. + */ +NRF_STATIC_INLINE void nrf_clock_hf_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_t source); +#endif + +/** + * @brief Function for retrieving the selected source of the high-frequency clock. + * + * For SoCs not featuring the HFCLKSRC register, this is always also the active source + * of the high-frequency clock. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval NRF_CLOCK_HFCLK_LOW_ACCURACY The internal RC oscillator is the selected + * source of the high-frequency clock. + * @retval NRF_CLOCK_HFCLK_HIGH_ACCURACY An external crystal oscillator is the selected + * source of the high-frequency clock. + */ +NRF_STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(NRF_CLOCK_Type const * p_reg); + +/** + * @brief Function for retrieving the state of the HFCLK clock. + * + * @note This function is deprecated. Use @ref nrf_clock_is_running instead. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] clk_src Clock source to be checked. + * + * @retval false The HFCLK clock is not running. + * @retval true The HFCLK clock is running. + */ +NRF_STATIC_INLINE bool nrf_clock_hf_is_running(NRF_CLOCK_Type const * p_reg, + nrf_clock_hfclk_t clk_src); + +/** + * @brief Function for retrieving the trigger status of the task HFCLKSTART. + * + * @note This function is deprecated. Use @ref nrf_clock_start_task_check instead. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED The task HFCLKSTART has not been triggered. + * @retval NRF_CLOCK_START_TASK_TRIGGERED The task HFCLKSTART has been triggered. + */ +NRF_STATIC_INLINE +nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(NRF_CLOCK_Type const * p_reg); + +#if NRF_CLOCK_HAS_HFCLKAUDIO +/** + * @brief Function for changing the Audio clock FREQ_VALUE. + * + * The frequency of HFCLKAUDIO ranges from 10.666 MHz to 13.333 MHz in 40.7 Hz steps. + * To calculate @p freq_value corresponding to the chosen frequency, use the following equation: + * FREQ_VALUE = 2^16 * ((12 * f_out / 32M) - 4) + * + * @warning Chosen frequency must fit in 11.176 MHz - 11.402 MHz or 12.165 MHz - 12.411 MHz frequency bands. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] freq_value New FREQ_VALUE + */ +NRF_STATIC_INLINE +void nrf_clock_hfclkaudio_config_set(NRF_CLOCK_Type * p_reg, uint16_t freq_value); + +/** + * @brief Function for retrieving the Audio clock FREQ_VALUE. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * The frequency of HFCLKAUDIO ranges from 10.666 MHz to 13.333 MHz in 40.7 Hz steps. + * To calculate frequency corresponding to the returned FREQ_VALUE, use the following equation: + * f_out = 32M * (4 + FREQ_VALUE * 2^(-16))/12 + + * @return FREQ_VALUE of the Audio clock. + */ +NRF_STATIC_INLINE +uint16_t nrf_clock_hfclkaudio_config_get(NRF_CLOCK_Type const * p_reg); +#endif + +#if NRF_CLOCK_HAS_CALIBRATION_TIMER +/** + * @brief Function for changing the calibration timer interval. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] interval New calibration timer interval in 0.25 s resolution + * (range: 0.25 seconds to 31.75 seconds). + */ +NRF_STATIC_INLINE void nrf_clock_cal_timer_timeout_set(NRF_CLOCK_Type * p_reg, uint32_t interval); +#endif + +#if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) +/** + * @brief Function for changing the HFCLK frequency divider. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] divider New HFCLK divider. + */ +NRF_STATIC_INLINE void nrf_clock_hfclk_div_set(NRF_CLOCK_Type * p_reg, + nrf_clock_hfclk_div_t divider); + +/** + * @brief Function for retrieving the HFCLK frequency divider. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return HFCLK frequency divider. + */ +NRF_STATIC_INLINE nrf_clock_hfclk_div_t nrf_clock_hfclk_div_get(NRF_CLOCK_Type const * p_reg); +#endif + +#if NRF_CLOCK_HAS_HFCLK192M +/** + * @brief Function for changing the HFCLK192M frequency divider. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] divider New HFCLK192M divider. + */ +NRF_STATIC_INLINE void nrf_clock_hfclk192m_div_set(NRF_CLOCK_Type * p_reg, + nrf_clock_hfclk_div_t divider); + +/** + * @brief Function for retrieving the HFCLK192M frequency divider. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return HFCLK192M frequency divider. + */ +NRF_STATIC_INLINE nrf_clock_hfclk_div_t nrf_clock_hfclk192m_div_get(NRF_CLOCK_Type const * p_reg); + +/** + * @brief Function for changing the HFCLK192M source. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] source New HFCLK192M source. + */ +NRF_STATIC_INLINE void nrf_clock_hfclk192m_src_set(NRF_CLOCK_Type * p_reg, + nrf_clock_hfclk_t source); + +/** + * @brief Function for retrieving the selected source of the HFCLK192M. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval NRF_CLOCK_HFCLK_LOW_ACCURACY The internal RC oscillator is the selected + * source of the HFCLK192M. + * @retval NRF_CLOCK_HFCLK_HIGH_ACCURACY An external crystal oscillator is the selected + * source of the HFCLK192M. + */ +NRF_STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hfclk192m_src_get(NRF_CLOCK_Type const * p_reg); +#endif // NRF_CLOCK_HAS_HFCLK192M + +#if NRF_CLOCK_HAS_ALWAYSRUN +/** + * @brief Function for setting the clock domain to always run. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] domain Clock domain. + * @param[in] alwaysrun Ensure the clock is always running. + */ +NRF_STATIC_INLINE void nrf_clock_alwaysrun_set(NRF_CLOCK_Type * p_reg, + nrf_clock_domain_t domain, + bool alwaysrun); +/** + * @brief Function for checking if the clock domain is configured to always run. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] domain Clock domain. + * + * @retval true The clock domain is configured to always run. + * @retval false The clock domain is not configured to always run. + */ +NRF_STATIC_INLINE bool nrf_clock_alwaysrun_get(NRF_CLOCK_Type const * p_reg, + nrf_clock_domain_t domain); +/** + * @brief Function for checking if the clock domain always run setting is active. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] domain Clock domain. + * + * @retval true The clock domain always run setting is active. + * @retval false The clock domain always run setting is not active. + */ +NRF_STATIC_INLINE bool nrf_clock_alwaysrun_active_get(NRF_CLOCK_Type const * p_reg, + nrf_clock_domain_t domain); +#endif + +#if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for setting the subscribe configuration for a given + * CLOCK task. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] task Task for which to set the configuration. + * @param[in] channel Channel through which to subscribe events. + */ +NRF_STATIC_INLINE void nrf_clock_subscribe_set(NRF_CLOCK_Type * p_reg, + nrf_clock_task_t task, + uint8_t channel); + +/** + * @brief Function for clearing the subscribe configuration for a given + * CLOCK task. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] task Task for which to clear the configuration. + */ +NRF_STATIC_INLINE void nrf_clock_subscribe_clear(NRF_CLOCK_Type * p_reg, nrf_clock_task_t task); + +/** + * @brief Function for setting the publish configuration for a given + * CLOCK event. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] event Event for which to set the configuration. + * @param[in] channel Channel through which to publish the event. + */ +NRF_STATIC_INLINE void nrf_clock_publish_set(NRF_CLOCK_Type * p_reg, + nrf_clock_event_t event, + uint8_t channel); + +/** + * @brief Function for clearing the publish configuration for a given + * CLOCK event. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] event Event for which to clear the configuration. + */ +NRF_STATIC_INLINE void nrf_clock_publish_clear(NRF_CLOCK_Type * p_reg, nrf_clock_event_t event); +#endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__) + +#ifndef NRF_DECLARE_ONLY + +NRF_STATIC_INLINE void nrf_clock_int_enable(NRF_CLOCK_Type * p_reg, uint32_t mask) +{ + p_reg->INTENSET = mask; +} + +NRF_STATIC_INLINE void nrf_clock_int_disable(NRF_CLOCK_Type * p_reg, uint32_t mask) +{ + p_reg->INTENCLR = mask; +} + +NRF_STATIC_INLINE uint32_t nrf_clock_int_enable_check(NRF_CLOCK_Type const * p_reg, uint32_t mask) +{ + return p_reg->INTENSET & mask; +} + +NRF_STATIC_INLINE uint32_t nrf_clock_task_address_get(NRF_CLOCK_Type const * p_reg, + nrf_clock_task_t task) +{ + return (uint32_t)((uint8_t *)p_reg + (uint32_t)task); +} + +NRF_STATIC_INLINE void nrf_clock_task_trigger(NRF_CLOCK_Type * p_reg, nrf_clock_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; +} + +NRF_STATIC_INLINE uint32_t nrf_clock_event_address_get(NRF_CLOCK_Type const * p_reg, + nrf_clock_event_t event) +{ + return (uint32_t)((uint8_t *)p_reg + (uint32_t)event); +} + +NRF_STATIC_INLINE void nrf_clock_event_clear(NRF_CLOCK_Type * p_reg, nrf_clock_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); +} + +NRF_STATIC_INLINE bool nrf_clock_event_check(NRF_CLOCK_Type const * p_reg, nrf_clock_event_t event) +{ + return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + event)); +} + +NRF_STATIC_INLINE bool nrf_clock_start_task_check(NRF_CLOCK_Type const * p_reg, + nrf_clock_domain_t domain) +{ + switch (domain) + { + case NRF_CLOCK_DOMAIN_LFCLK: + return ((p_reg->LFCLKRUN & CLOCK_LFCLKRUN_STATUS_Msk) + >> CLOCK_LFCLKRUN_STATUS_Pos); + case NRF_CLOCK_DOMAIN_HFCLK: + return ((p_reg->HFCLKRUN & CLOCK_HFCLKRUN_STATUS_Msk) + >> CLOCK_HFCLKRUN_STATUS_Pos); +#if NRF_CLOCK_HAS_HFCLK192M + case NRF_CLOCK_DOMAIN_HFCLK192M: + return ((p_reg->HFCLK192MRUN & CLOCK_HFCLK192MRUN_STATUS_Msk) + >> CLOCK_HFCLK192MRUN_STATUS_Pos); +#endif +#if NRF_CLOCK_HAS_HFCLKAUDIO + case NRF_CLOCK_DOMAIN_HFCLKAUDIO: + return ((p_reg->HFCLKAUDIORUN & CLOCK_HFCLKAUDIORUN_STATUS_Msk) + >> CLOCK_HFCLKAUDIORUN_STATUS_Pos); +#endif + default: + NRFX_ASSERT(0); + return false; + } +} + +NRF_STATIC_INLINE bool nrf_clock_is_running(NRF_CLOCK_Type const * p_reg, + nrf_clock_domain_t domain, + void * p_clk_src) +{ + switch (domain) + { + case NRF_CLOCK_DOMAIN_LFCLK: + if (p_clk_src != NULL) + { + (*(nrf_clock_lfclk_t *)p_clk_src) = + (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk) + >> CLOCK_LFCLKSTAT_SRC_Pos); + } + if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk) + >> CLOCK_LFCLKSTAT_STATE_Pos) + { + return true; + } + break; + case NRF_CLOCK_DOMAIN_HFCLK: + if (p_clk_src != NULL) + { + (*(nrf_clock_hfclk_t *)p_clk_src) = + (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk) + >> CLOCK_HFCLKSTAT_SRC_Pos); + } + if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk) + >> CLOCK_HFCLKSTAT_STATE_Pos) + { + return true; + } + break; +#if NRF_CLOCK_HAS_HFCLK192M + case NRF_CLOCK_DOMAIN_HFCLK192M: + if (p_clk_src != NULL) + { + (*(nrf_clock_hfclk_t *)p_clk_src) = + (nrf_clock_hfclk_t)((p_reg->HFCLK192MSTAT & CLOCK_HFCLK192MSTAT_SRC_Msk) + >> CLOCK_HFCLK192MSTAT_SRC_Pos); + } + if ((p_reg->HFCLK192MSTAT & CLOCK_HFCLK192MSTAT_STATE_Msk) + >> CLOCK_HFCLK192MSTAT_STATE_Pos) + { + return true; + } + break; +#endif +#if NRF_CLOCK_HAS_HFCLKAUDIO + case NRF_CLOCK_DOMAIN_HFCLKAUDIO: + return (p_reg->HFCLKAUDIOSTAT & CLOCK_HFCLKAUDIOSTAT_STATE_Msk) == + CLOCK_HFCLKAUDIOSTAT_STATE_Msk; +#endif + default: + NRFX_ASSERT(0); + return false; + } + return false; +} + +NRF_STATIC_INLINE void nrf_clock_lf_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_lfclk_t source) +{ + p_reg->LFCLKSRC = (uint32_t)(source); +} + +NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(NRF_CLOCK_Type const * p_reg) +{ + return (nrf_clock_lfclk_t)(p_reg->LFCLKSRC); +} + +NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(NRF_CLOCK_Type const * p_reg) +{ + nrf_clock_lfclk_t clk_src; + (void)nrf_clock_is_running(p_reg, NRF_CLOCK_DOMAIN_LFCLK, &clk_src); + return clk_src; +} + +NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg) +{ + return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk) + >> CLOCK_LFCLKSRCCOPY_SRC_Pos); +} + +NRF_STATIC_INLINE bool nrf_clock_lf_is_running(NRF_CLOCK_Type const * p_reg) +{ + return nrf_clock_is_running(p_reg, NRF_CLOCK_DOMAIN_LFCLK, NULL); +} + +NRF_STATIC_INLINE +nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(NRF_CLOCK_Type const * p_reg) +{ + return (nrf_clock_start_task_status_t)nrf_clock_start_task_check(p_reg, + NRF_CLOCK_DOMAIN_LFCLK); +} + +#if NRF_CLOCK_HAS_HFCLKSRC +NRF_STATIC_INLINE void nrf_clock_hf_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_t source) +{ + p_reg->HFCLKSRC = (uint32_t)(source); +} +#endif + +NRF_STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(NRF_CLOCK_Type const * p_reg) +{ +#if NRF_CLOCK_HAS_HFCLKSRC + return (nrf_clock_hfclk_t)(p_reg->HFCLKSRC); +#else + return (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk) + >> CLOCK_HFCLKSTAT_SRC_Pos); +#endif +} + +NRF_STATIC_INLINE bool nrf_clock_hf_is_running(NRF_CLOCK_Type const * p_reg, + nrf_clock_hfclk_t clk_src) +{ + nrf_clock_hfclk_t active_clk_src; + bool ret = nrf_clock_is_running(p_reg, NRF_CLOCK_DOMAIN_HFCLK, &active_clk_src); + return (ret && (active_clk_src == clk_src)); +} + +NRF_STATIC_INLINE +nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(NRF_CLOCK_Type const * p_reg) +{ + return (nrf_clock_start_task_status_t)nrf_clock_start_task_check(p_reg, + NRF_CLOCK_DOMAIN_HFCLK); +} + +#if NRF_CLOCK_HAS_HFCLKAUDIO +NRF_STATIC_INLINE +void nrf_clock_hfclkaudio_config_set(NRF_CLOCK_Type * p_reg, uint16_t freq_value) +{ + p_reg->HFCLKAUDIO.FREQUENCY = freq_value; +} + +NRF_STATIC_INLINE +uint16_t nrf_clock_hfclkaudio_config_get(NRF_CLOCK_Type const * p_reg) +{ + return (uint16_t)(p_reg->HFCLKAUDIO.FREQUENCY); +} +#endif + +#if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) +NRF_STATIC_INLINE +void nrf_clock_hfclk_div_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_div_t divider) +{ + p_reg->HFCLKCTRL = (((uint8_t)(divider) << CLOCK_HFCLKCTRL_HCLK_Pos) & + CLOCK_HFCLKCTRL_HCLK_Msk); +} + +NRF_STATIC_INLINE nrf_clock_hfclk_div_t nrf_clock_hfclk_div_get(NRF_CLOCK_Type const * p_reg) +{ + return (nrf_clock_hfclk_div_t)((p_reg->HFCLKCTRL & CLOCK_HFCLKCTRL_HCLK_Msk) + >> CLOCK_HFCLKCTRL_HCLK_Pos); +} +#endif + +#if NRF_CLOCK_HAS_HFCLK192M +NRF_STATIC_INLINE +void nrf_clock_hfclk192m_div_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_div_t divider) +{ + p_reg->HFCLK192MCTRL = (((uint8_t)(divider) << CLOCK_HFCLK192MCTRL_HCLK192M_Pos) & + CLOCK_HFCLK192MCTRL_HCLK192M_Msk); +} + +NRF_STATIC_INLINE nrf_clock_hfclk_div_t nrf_clock_hfclk192m_div_get(NRF_CLOCK_Type const * p_reg) +{ + return (nrf_clock_hfclk_div_t)((p_reg->HFCLK192MCTRL & CLOCK_HFCLK192MCTRL_HCLK192M_Msk) + >> CLOCK_HFCLK192MCTRL_HCLK192M_Pos); +} + +NRF_STATIC_INLINE void nrf_clock_hfclk192m_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_t source) +{ + p_reg->HFCLK192MSRC = (uint32_t)(source); +} + +NRF_STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hfclk192m_src_get(NRF_CLOCK_Type const * p_reg) +{ + return (nrf_clock_hfclk_t)(p_reg->HFCLK192MSRC); +} +#endif + +#if NRF_CLOCK_HAS_CALIBRATION_TIMER +NRF_STATIC_INLINE void nrf_clock_cal_timer_timeout_set(NRF_CLOCK_Type * p_reg, uint32_t interval) +{ + p_reg->CTIV = ((interval << CLOCK_CTIV_CTIV_Pos) & CLOCK_CTIV_CTIV_Msk); +} +#endif + +#if NRF_CLOCK_HAS_ALWAYSRUN +NRF_STATIC_INLINE void nrf_clock_alwaysrun_set(NRF_CLOCK_Type * p_reg, + nrf_clock_domain_t domain, + bool alwaysrun) +{ + switch (domain) + { + case NRF_CLOCK_DOMAIN_LFCLK: + p_reg->LFCLKALWAYSRUN = + ((alwaysrun << CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos) + & CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk); + break; + case NRF_CLOCK_DOMAIN_HFCLK: + p_reg->HFCLKALWAYSRUN = + ((alwaysrun << CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos) + & CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Msk); + break; +#if NRF_CLOCK_HAS_HFCLK192M + case NRF_CLOCK_DOMAIN_HFCLK192M: + p_reg->HFCLK192MALWAYSRUN = + ((alwaysrun << CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Pos) + & CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Msk); + break; +#endif +#if NRF_CLOCK_HAS_HFCLKAUDIO + case NRF_CLOCK_DOMAIN_HFCLKAUDIO: + p_reg->HFCLKAUDIOALWAYSRUN = + ((alwaysrun << CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Pos) + & CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Msk); + break; +#endif + default: + NRFX_ASSERT(0); + break; + } +} + +NRF_STATIC_INLINE bool nrf_clock_alwaysrun_get(NRF_CLOCK_Type const * p_reg, + nrf_clock_domain_t domain) +{ + switch (domain) + { + case NRF_CLOCK_DOMAIN_LFCLK: + return ((p_reg->LFCLKALWAYSRUN & CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk) + >> CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos); + case NRF_CLOCK_DOMAIN_HFCLK: + return ((p_reg->HFCLKALWAYSRUN & CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Msk) + >> CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos); +#if NRF_CLOCK_HAS_HFCLK192M + case NRF_CLOCK_DOMAIN_HFCLK192M: + return ((p_reg->HFCLK192MALWAYSRUN & CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Msk) + >> CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Pos); +#endif +#if NRF_CLOCK_HAS_HFCLKAUDIO + case NRF_CLOCK_DOMAIN_HFCLKAUDIO: + return ((p_reg->HFCLKAUDIOALWAYSRUN & CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Msk) + >> CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Pos); +#endif + default: + NRFX_ASSERT(0); + return false; + } +} + +NRF_STATIC_INLINE bool nrf_clock_alwaysrun_active_get(NRF_CLOCK_Type const * p_reg, + nrf_clock_domain_t domain) +{ + switch (domain) + { + case NRF_CLOCK_DOMAIN_LFCLK: + return ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_ALWAYSRUNNING_Msk) + >> CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos); + case NRF_CLOCK_DOMAIN_HFCLK: + return ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_ALWAYSRUNNING_Msk) + >> CLOCK_HFCLKSTAT_ALWAYSRUNNING_Pos); +#if NRF_CLOCK_HAS_HFCLK192M + case NRF_CLOCK_DOMAIN_HFCLK192M: + return ((p_reg->HFCLK192MSTAT & CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Msk) + >> CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Pos); +#endif +#if NRF_CLOCK_HAS_HFCLKAUDIO + case NRF_CLOCK_DOMAIN_HFCLKAUDIO: + return ((p_reg->HFCLKAUDIOSTAT & CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Msk) + >> CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Pos); +#endif + default: + NRFX_ASSERT(0); + return false; + } +} +#endif // NRF_CLOCK_HAS_ALWAYSRUN + +#if defined(DPPI_PRESENT) +NRF_STATIC_INLINE void nrf_clock_subscribe_set(NRF_CLOCK_Type * p_reg, + nrf_clock_task_t task, + uint8_t channel) +{ + *((volatile uint32_t *) ((uint8_t *)p_reg+ (uint32_t)task + 0x80uL)) = + ((uint32_t)channel | CLOCK_SUBSCRIBE_HFCLKSTART_EN_Msk); +} + +NRF_STATIC_INLINE void nrf_clock_subscribe_clear(NRF_CLOCK_Type * p_reg, nrf_clock_task_t task) +{ + *((volatile uint32_t *) ((uint8_t *)p_reg + (uint32_t)task + 0x80uL)) = 0; +} + +NRF_STATIC_INLINE void nrf_clock_publish_set(NRF_CLOCK_Type * p_reg, + nrf_clock_event_t event, + uint8_t channel) +{ + *((volatile uint32_t *) ((uint8_t *)p_reg + (uint32_t)event + 0x80uL)) = + ((uint32_t)channel | CLOCK_PUBLISH_HFCLKSTARTED_EN_Msk); +} + +NRF_STATIC_INLINE void nrf_clock_publish_clear(NRF_CLOCK_Type * p_reg, nrf_clock_event_t event) +{ + *((volatile uint32_t *) ((uint8_t *)p_reg + (uint32_t)event + 0x80uL)) = 0; +} +#endif // defined(DPPI_PRESENT) + +#endif // NRF_DECLARE_ONLY + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_CLOCK_H__ diff --git a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h index c01c25248..7c2435160 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h +++ b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h @@ -45,7 +45,7 @@ // NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver //========================================================== #ifndef NRFX_CLOCK_ENABLED -#define NRFX_CLOCK_ENABLED 0 +#define NRFX_CLOCK_ENABLED 1 #endif // NRFX_CLOCK_CONFIG_LF_SRC - LF Clock Source diff --git a/source/hic_hal/nordic/nrf52820/sdk.c b/source/hic_hal/nordic/nrf52820/sdk.c index a35e38109..a0c3e5dee 100644 --- a/source/hic_hal/nordic/nrf52820/sdk.c +++ b/source/hic_hal/nordic/nrf52820/sdk.c @@ -24,6 +24,7 @@ #include "daplink.h" #include "compiler.h" #include "util.h" +#include "nrfx_clock.h" #ifdef NRF528XX_DYNAMIC_PIN uint32_t uart_tx_pin; @@ -80,4 +81,6 @@ void sdk_init() i2c_sda_pin = NRF52820_I2C_SDA_PIN; } #endif + + nrfx_clock_enable(); } From fa85278da5845ba04a265a8fe1467d43fbe7c7c7 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 19 Nov 2021 14:37:01 -0600 Subject: [PATCH 508/617] uart: forward control line state to HIC UART --- source/daplink/usb2uart/usbd_user_cdc_acm.c | 1 + source/hic_hal/freescale/k20dx/uart.c | 4 ++++ source/hic_hal/freescale/k26f/uart.c | 4 ++++ source/hic_hal/freescale/kl26z/uart.c | 4 ++++ source/hic_hal/freescale/kl27z/uart.c | 4 ++++ source/hic_hal/nordic/nrf52820/uart.c | 4 ++++ source/hic_hal/nuvoton/m48ssidae/uart.c | 4 ++++ source/hic_hal/nxp/lpc11u35/uart.c | 4 ++++ source/hic_hal/nxp/lpc4322/uart.c | 6 +++++- source/hic_hal/nxp/lpc55xx/uart.c | 4 ++++ source/hic_hal/stm32/stm32f103xb/uart.c | 4 ++++ 11 files changed, 42 insertions(+), 1 deletion(-) diff --git a/source/daplink/usb2uart/usbd_user_cdc_acm.c b/source/daplink/usb2uart/usbd_user_cdc_acm.c index 7201aa044..7e3709355 100644 --- a/source/daplink/usb2uart/usbd_user_cdc_acm.c +++ b/source/daplink/usb2uart/usbd_user_cdc_acm.c @@ -149,6 +149,7 @@ int32_t USBD_CDC_ACM_SendBreak(uint16_t dur) */ int32_t USBD_CDC_ACM_PortSetControlLineState(uint16_t ctrl_bmp) { + uart_set_control_line_state(ctrl_bmp); return (1); } diff --git a/source/hic_hal/freescale/k20dx/uart.c b/source/hic_hal/freescale/k20dx/uart.c index d24a36b5d..cdb2e69f1 100644 --- a/source/hic_hal/freescale/k20dx/uart.c +++ b/source/hic_hal/freescale/k20dx/uart.c @@ -159,6 +159,10 @@ int32_t uart_get_configuration(UART_Configuration *config) return 1; } +void uart_set_control_line_state(uint16_t ctrl_bmp) +{ +} + int32_t uart_write_free(void) { return circ_buf_count_free(&write_buffer); diff --git a/source/hic_hal/freescale/k26f/uart.c b/source/hic_hal/freescale/k26f/uart.c index 1c6832b6d..269d89b4b 100644 --- a/source/hic_hal/freescale/k26f/uart.c +++ b/source/hic_hal/freescale/k26f/uart.c @@ -165,6 +165,10 @@ int32_t uart_get_configuration(UART_Configuration *config) return 1; } +void uart_set_control_line_state(uint16_t ctrl_bmp) +{ +} + int32_t uart_write_free(void) { return circ_buf_count_free(&write_buffer); diff --git a/source/hic_hal/freescale/kl26z/uart.c b/source/hic_hal/freescale/kl26z/uart.c index e502aa3d9..211cdc998 100644 --- a/source/hic_hal/freescale/kl26z/uart.c +++ b/source/hic_hal/freescale/kl26z/uart.c @@ -206,6 +206,10 @@ int32_t uart_read_data(uint8_t *data, uint16_t size) return circ_buf_read(&read_buffer, data, size); } +void uart_set_control_line_state(uint16_t ctrl_bmp) +{ +} + void uart_enable_flow_control(bool enabled) { // Flow control not implemented for this platform diff --git a/source/hic_hal/freescale/kl27z/uart.c b/source/hic_hal/freescale/kl27z/uart.c index 080d51379..b109d182f 100644 --- a/source/hic_hal/freescale/kl27z/uart.c +++ b/source/hic_hal/freescale/kl27z/uart.c @@ -189,6 +189,10 @@ int32_t uart_get_configuration(UART_Configuration *config) return 1; } +void uart_set_control_line_state(uint16_t ctrl_bmp) +{ +} + int32_t uart_write_free(void) { return circ_buf_count_free(&write_buffer); diff --git a/source/hic_hal/nordic/nrf52820/uart.c b/source/hic_hal/nordic/nrf52820/uart.c index 2e14a93c7..5e3d149fc 100644 --- a/source/hic_hal/nordic/nrf52820/uart.c +++ b/source/hic_hal/nordic/nrf52820/uart.c @@ -192,6 +192,10 @@ int32_t uart_get_configuration(UART_Configuration *config) return 1; } +void uart_set_control_line_state(uint16_t ctrl_bmp) +{ +} + int32_t uart_write_free(void) { return circ_buf_count_free(&write_buffer); diff --git a/source/hic_hal/nuvoton/m48ssidae/uart.c b/source/hic_hal/nuvoton/m48ssidae/uart.c index 5479a4276..937ef306a 100644 --- a/source/hic_hal/nuvoton/m48ssidae/uart.c +++ b/source/hic_hal/nuvoton/m48ssidae/uart.c @@ -146,6 +146,10 @@ int32_t uart_get_configuration(UART_Configuration *config) return 1; } +void uart_set_control_line_state(uint16_t ctrl_bmp) +{ +} + int32_t uart_write_free(void) { return circ_buf_count_free(&write_buffer); diff --git a/source/hic_hal/nxp/lpc11u35/uart.c b/source/hic_hal/nxp/lpc11u35/uart.c index 7c7f11993..8c4b2b5e0 100644 --- a/source/hic_hal/nxp/lpc11u35/uart.c +++ b/source/hic_hal/nxp/lpc11u35/uart.c @@ -260,6 +260,10 @@ int32_t uart_get_configuration(UART_Configuration *config) return 1; } +void uart_set_control_line_state(uint16_t ctrl_bmp) +{ +} + int32_t uart_write_free(void) { return circ_buf_count_free(&write_buffer); diff --git a/source/hic_hal/nxp/lpc4322/uart.c b/source/hic_hal/nxp/lpc4322/uart.c index 6557e060f..92b62d4e5 100644 --- a/source/hic_hal/nxp/lpc4322/uart.c +++ b/source/hic_hal/nxp/lpc4322/uart.c @@ -257,7 +257,11 @@ int32_t uart_get_configuration(UART_Configuration *config) return 1; } -int32_t uart_write_free(void) +void uart_set_control_line_state(uint16_t ctrl_bmp) +{ +} + +OAint32_t uart_write_free(void) { return circ_buf_count_free(&write_buffer); } diff --git a/source/hic_hal/nxp/lpc55xx/uart.c b/source/hic_hal/nxp/lpc55xx/uart.c index f69648d1d..7f55f2e04 100644 --- a/source/hic_hal/nxp/lpc55xx/uart.c +++ b/source/hic_hal/nxp/lpc55xx/uart.c @@ -183,6 +183,10 @@ int32_t uart_get_configuration(UART_Configuration *config) return 1; } +void uart_set_control_line_state(uint16_t ctrl_bmp) +{ +} + int32_t uart_write_free(void) { return circ_buf_count_free(&write_buffer); diff --git a/source/hic_hal/stm32/stm32f103xb/uart.c b/source/hic_hal/stm32/stm32f103xb/uart.c index a75a1099d..d982be84f 100644 --- a/source/hic_hal/stm32/stm32f103xb/uart.c +++ b/source/hic_hal/stm32/stm32f103xb/uart.c @@ -214,6 +214,10 @@ int32_t uart_get_configuration(UART_Configuration *config) return 1; } +void uart_set_control_line_state(uint16_t ctrl_bmp) +{ +} + int32_t uart_write_free(void) { return circ_buf_count_free(&write_buffer); From e3f8eea3d05436eb244e1149f0591e6ab087e4ed Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 24 Nov 2021 12:42:45 -0600 Subject: [PATCH 509/617] uart: make default UART rate configurable --- source/usb/cdc/usbd_cdc_acm.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/source/usb/cdc/usbd_cdc_acm.c b/source/usb/cdc/usbd_cdc_acm.c index df28107b3..acd2a8bb4 100644 --- a/source/usb/cdc/usbd_cdc_acm.c +++ b/source/usb/cdc/usbd_cdc_acm.c @@ -24,6 +24,9 @@ #include "rl_usb.h" #include "usb_for_lib.h" +#ifndef CDC_ACM_DEFAULT_BAUDRATE +#define CDC_ACM_DEFAULT_BAUDRATE 9600 +#endif /* Module global variables */ @@ -153,7 +156,7 @@ __WEAK int32_t USBD_CDC_ACM_Initialize(void) ptr_data_received = USBD_CDC_ACM_ReceiveBuf; ptr_data_read = USBD_CDC_ACM_ReceiveBuf; control_line_state = 0; - line_coding.dwDTERate = 9600; + line_coding.dwDTERate = CDC_ACM_DEFAULT_BAUDRATE; line_coding.bCharFormat = 0; line_coding.bParityType = 0; line_coding.bDataBits = 8; @@ -205,7 +208,7 @@ __WEAK int32_t USBD_CDC_ACM_Reset(void) ptr_data_read = USBD_CDC_ACM_ReceiveBuf; control_line_state = 0; USBD_CDC_ACM_PortReset(); - line_coding.dwDTERate = 9600; + line_coding.dwDTERate = CDC_ACM_DEFAULT_BAUDRATE; line_coding.bCharFormat = 0; line_coding.bParityType = 0; line_coding.bDataBits = 8; From 6b99c7bb3c45b375c34bf3e00df2a69acb3f540f Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 24 Nov 2021 12:43:18 -0600 Subject: [PATCH 510/617] nrf52820_microbit: set default UART baud rate to 115200 --- records/board/microbitv2_nrf52820.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/records/board/microbitv2_nrf52820.yaml b/records/board/microbitv2_nrf52820.yaml index b8f318778..5aede83c5 100644 --- a/records/board/microbitv2_nrf52820.yaml +++ b/records/board/microbitv2_nrf52820.yaml @@ -7,6 +7,7 @@ common: # - DELAY_FAST_CYCLES=2U # Fast delay needed to reach 8MHz SWD clock speed # - DAP_DEFAULT_SWJ_CLOCK=8000000 - BOARD_EXTRA_BUFFER=100 + - CDC_ACM_DEFAULT_BAUDRATE=115200 includes: - source/board/microbitv2/ - source/board/microbitv2/nrf52820/ From 97c3c32c34baa83554aaa6a809b8fbfd62b91ee0 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 24 Nov 2021 12:52:43 -0600 Subject: [PATCH 511/617] nrf52820_microbit: call uart_reset() when control line state changes --- source/hic_hal/nordic/nrf52820/uart.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/source/hic_hal/nordic/nrf52820/uart.c b/source/hic_hal/nordic/nrf52820/uart.c index 5e3d149fc..467b1330a 100644 --- a/source/hic_hal/nordic/nrf52820/uart.c +++ b/source/hic_hal/nordic/nrf52820/uart.c @@ -42,6 +42,7 @@ circ_buf_t write_buffer; uint8_t write_buffer_data[BUFFER_SIZE]; circ_buf_t read_buffer; uint8_t read_buffer_data[BUFFER_SIZE]; +uint16_t cur_line_state; uint32_t cur_control; uint32_t cur_baud; @@ -67,6 +68,7 @@ int32_t uart_initialize(void) cb_buf.tx_size = 0; USART_INSTANCE.Initialize(uart_handler); USART_INSTANCE.PowerControl(ARM_POWER_FULL); + cur_line_state = 0; cur_control = 0; cur_baud = 0; @@ -194,6 +196,10 @@ int32_t uart_get_configuration(UART_Configuration *config) void uart_set_control_line_state(uint16_t ctrl_bmp) { + if (ctrl_bmp != cur_line_state) { + uart_reset(); + cur_line_state = ctrl_bmp; + } } int32_t uart_write_free(void) From 04cd13fdc8efa9b43b72cb64784826e1309209ba Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Thu, 25 Nov 2021 18:24:30 +0000 Subject: [PATCH 512/617] nrf52820_microbit: Set I2C protocol to v1 until busy flag is implemented. --- source/board/microbitv2/i2c_commands.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/source/board/microbitv2/i2c_commands.h b/source/board/microbitv2/i2c_commands.h index 2c4bcf1f0..5383274f5 100644 --- a/source/board/microbitv2/i2c_commands.h +++ b/source/board/microbitv2/i2c_commands.h @@ -37,7 +37,12 @@ extern "C" { #define I2C_SLAVE_HID (0x71U) #define I2C_SLAVE_FLASH (0x72U) +// Busy flag not yet implemented in nRF52 +#if defined(INTERFACE_NRF52820) +#define I2C_PROTOCOL_VERSION (0x01) +#else #define I2C_PROTOCOL_VERSION (0x02) +#endif /*! i2c command Id type enumeration */ typedef enum cmdId_tag { From acc630acdf036516289a381885c10d7ecafed3b5 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Thu, 25 Nov 2021 19:54:00 +0000 Subject: [PATCH 513/617] nrf52820_microbit: Switch USB & I2C IRQ priorities to reduce I2C issues on USB serial connection. --- source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h index 7c2435160..0b995f0ff 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h +++ b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h @@ -1276,7 +1276,7 @@ // <7=> 7 #ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 2 +#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 1 #endif // NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module. @@ -1595,7 +1595,7 @@ // <7=> 7 #ifndef NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY 1 +#define NRFX_USBD_DEFAULT_CONFIG_IRQ_PRIORITY 2 #endif // USBD_CONFIG_DMASCHEDULER_ISO_BOOST - Give priority to isochronous transfers From 43da44896b256f73d44bb50b75db1b9d369c9c3e Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Thu, 25 Nov 2021 21:11:54 +0000 Subject: [PATCH 514/617] nrf52820_microbit: Start HC xtal & select RC LF clock. nrfx_clock_enable() was removed as it basically enables the clock interrupts which we don't need. --- source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h | 2 +- source/hic_hal/nordic/nrf52820/sdk.c | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h index 0b995f0ff..b245fce60 100644 --- a/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h +++ b/source/hic_hal/nordic/nrf52820/nrfx/nrfx_config_nrf52820.h @@ -56,7 +56,7 @@ // <196609=> External Full Swing #ifndef NRFX_CLOCK_CONFIG_LF_SRC -#define NRFX_CLOCK_CONFIG_LF_SRC 1 +#define NRFX_CLOCK_CONFIG_LF_SRC 0 #endif // NRFX_CLOCK_CONFIG_LF_CAL_ENABLED - Enables LF Clock Calibration Support diff --git a/source/hic_hal/nordic/nrf52820/sdk.c b/source/hic_hal/nordic/nrf52820/sdk.c index a0c3e5dee..f462c40b1 100644 --- a/source/hic_hal/nordic/nrf52820/sdk.c +++ b/source/hic_hal/nordic/nrf52820/sdk.c @@ -82,5 +82,7 @@ void sdk_init() } #endif - nrfx_clock_enable(); + if (!nrfx_clock_hfclk_is_running()) { + nrfx_clock_hfclk_start(); + } } From 5dd23001a7a3199d74870790049d6686e183316c Mon Sep 17 00:00:00 2001 From: Jonathan Austin Date: Fri, 26 Nov 2021 02:24:25 +0000 Subject: [PATCH 515/617] nrf52820_microbit: Reduce CDC buffer size to 64B to reduce WebUSB lost chars. Issue discussion: https://github.com/ARMmbed/DAPLink/issues/903 --- source/hic_hal/nordic/nrf52820/usb_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/hic_hal/nordic/nrf52820/usb_config.c b/source/hic_hal/nordic/nrf52820/usb_config.c index 6233b8f77..1eaae6b77 100644 --- a/source/hic_hal/nordic/nrf52820/usb_config.c +++ b/source/hic_hal/nordic/nrf52820/usb_config.c @@ -340,7 +340,7 @@ #define USBD_CDC_ACM_EP_BULKIN_STACK 0 #define USBD_CDC_ACM_WMAXPACKETSIZE1 64 #define USBD_CDC_ACM_HS_ENABLE1 1 -#define USBD_CDC_ACM_HS_WMAXPACKETSIZE1 512 +#define USBD_CDC_ACM_HS_WMAXPACKETSIZE1 64 #define USBD_CDC_ACM_HS_BINTERVAL1 1 #define USBD_CDC_ACM_CIF_STRDESC L"mbed Serial Port" #define USBD_CDC_ACM_DIF_STRDESC L"mbed Serial Port" From d0d9a71fab0ebb267c1bea872210632513eeaf4a Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Mon, 6 Dec 2021 18:34:52 +0000 Subject: [PATCH 516/617] lpc4322_hic: Fix typo in function return type. --- source/hic_hal/nxp/lpc4322/uart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/hic_hal/nxp/lpc4322/uart.c b/source/hic_hal/nxp/lpc4322/uart.c index 92b62d4e5..f4600c6a9 100644 --- a/source/hic_hal/nxp/lpc4322/uart.c +++ b/source/hic_hal/nxp/lpc4322/uart.c @@ -261,7 +261,7 @@ void uart_set_control_line_state(uint16_t ctrl_bmp) { } -OAint32_t uart_write_free(void) +int32_t uart_write_free(void) { return circ_buf_count_free(&write_buffer); } From 73fc4c221f90460362a9bab278c24ad5d4db4477 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 9 Nov 2021 23:25:41 -0600 Subject: [PATCH 517/617] lpc4322 (core): update startup/system from CMSIS pack From Keil LPC4300_DFP version 2.10.0 --- source/hic_hal/nxp/lpc4322/LPC43xx.h | 58438 +++++++--------- .../nxp/lpc4322/armcc/startup_LPC43xx.s | 375 +- source/hic_hal/nxp/lpc4322/fpu_enable.c | 65 - source/hic_hal/nxp/lpc4322/fpu_enable.h | 33 - source/hic_hal/nxp/lpc4322/system_LPC43xx.c | 760 +- source/hic_hal/nxp/lpc4322/system_LPC43xx.h | 29 +- 6 files changed, 24953 insertions(+), 34747 deletions(-) delete mode 100644 source/hic_hal/nxp/lpc4322/fpu_enable.c delete mode 100644 source/hic_hal/nxp/lpc4322/fpu_enable.h diff --git a/source/hic_hal/nxp/lpc4322/LPC43xx.h b/source/hic_hal/nxp/lpc4322/LPC43xx.h index 1b0006fac..7abea551c 100644 --- a/source/hic_hal/nxp/lpc4322/LPC43xx.h +++ b/source/hic_hal/nxp/lpc4322/LPC43xx.h @@ -2,19 +2,16 @@ /****************************************************************************************************//** * @file LPC43xx.h * - * @status RELEASE + * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for + * LPC43xx from . * - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for - * default LPC43xx Device Series + * @version V9 + * @date 4. September 2013 * - * @version V5 - * @date 9. December 2011 - * - * @note Generated with SVDConv V2.6 Build 6c on Friday, 09.12.2011 13:56:08 - * - * from CMSIS SVD File 'LPC43xxv5.xml' Version 5, - * created on Friday, 09.12.2011 21:56:03, last modified on Friday, 09.12.2011 21:56:04 + * @note Generated with SVDConv V2.80 + * from CMSIS SVD File 'LPC43xx.svd' Version 9, * + * Modified by KEIL *******************************************************************************************************/ @@ -27,144 +24,182 @@ * @{ */ -#ifndef __LPC43XX_H__ -#define __LPC43XX_H__ +#ifndef LPC43XX_H +#define LPC43XX_H #ifdef __cplusplus extern "C" { -#endif - - - -/******************************************** -** Start of section using anonymous unions ** -*********************************************/ - -#if defined(__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma push - #pragma language=extended -#else - #error Not supported compiler type #endif +/* + Following defines are used: + CORE_M4 LPC43xx M4 Application core + CORE_M0 LPC43xx M0 Application core + CORE_M0SUB LPC43xx M0 Subsystem core + */ +#if !defined (CORE_M4) && !defined (CORE_M0) && !defined (CORE_M0SUB) + #define CORE_M4 +#endif - /* Interrupt Number Definition */ +/* ------------------------- Interrupt Number Definition ------------------------ */ typedef enum { -// ------------------------- Cortex-M4 Processor Exceptions Numbers ----------------------------- - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ - BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ - UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -// --------------------------- LPC43xx Specific Interrupt Numbers ------------------------------- - DAC_IRQn = 0, /*!< 0 DAC */ - M0CORE_IRQn = 1, /*!< 1 M0a */ - DMA_IRQn = 2, /*!< 2 DMA */ - RESERVED1_IRQn = 3, /*!< 3 EZH/EDM */ - RESERVED2_IRQn = 4, - ETHERNET_IRQn = 5, /*!< 5 ETHERNET */ - SDIO_IRQn = 6, /*!< 6 SDIO */ - LCD_IRQn = 7, /*!< 7 LCD */ - USB0_IRQn = 8, /*!< 8 USB0 */ - USB1_IRQn = 9, /*!< 9 USB1 */ - SCT_IRQn = 10, /*!< 10 SCT */ - RITIMER_IRQn = 11, /*!< 11 RITIMER */ - TIMER0_IRQn = 12, /*!< 12 TIMER0 */ - TIMER1_IRQn = 13, /*!< 13 TIMER1 */ - TIMER2_IRQn = 14, /*!< 14 TIMER2 */ - TIMER3_IRQn = 15, /*!< 15 TIMER3 */ - MCPWM_IRQn = 16, /*!< 16 MCPWM */ - ADC0_IRQn = 17, /*!< 17 ADC0 */ - I2C0_IRQn = 18, /*!< 18 I2C0 */ - I2C1_IRQn = 19, /*!< 19 I2C1 */ - SPI_INT_IRQn = 20, /*!< 20 SPI_INT */ - ADC1_IRQn = 21, /*!< 21 ADC1 */ - SSP0_IRQn = 22, /*!< 22 SSP0 */ - SSP1_IRQn = 23, /*!< 23 SSP1 */ - USART0_IRQn = 24, /*!< 24 USART0 */ - UART1_IRQn = 25, /*!< 25 UART1 */ - USART2_IRQn = 26, /*!< 26 USART2 */ - USART3_IRQn = 27, /*!< 27 USART3 */ - I2S0_IRQn = 28, /*!< 28 I2S0 */ - I2S1_IRQn = 29, /*!< 29 I2S1 */ - RESERVED4_IRQn = 30, - SGPIO_IINT_IRQn = 31, /*!< 31 SGPIO_IINT */ - PIN_INT0_IRQn = 32, /*!< 32 PIN_INT0 */ - PIN_INT1_IRQn = 33, /*!< 33 PIN_INT1 */ - PIN_INT2_IRQn = 34, /*!< 34 PIN_INT2 */ - PIN_INT3_IRQn = 35, /*!< 35 PIN_INT3 */ - PIN_INT4_IRQn = 36, /*!< 36 PIN_INT4 */ - PIN_INT5_IRQn = 37, /*!< 37 PIN_INT5 */ - PIN_INT6_IRQn = 38, /*!< 38 PIN_INT6 */ - PIN_INT7_IRQn = 39, /*!< 39 PIN_INT7 */ - GINT0_IRQn = 40, /*!< 40 GINT0 */ - GINT1_IRQn = 41, /*!< 41 GINT1 */ - EVENTROUTER_IRQn = 42, /*!< 42 EVENTROUTER */ - C_CAN1_IRQn = 43, /*!< 43 C_CAN1 */ - RESERVED6_IRQn = 44, - VADC_IRQn = 45, /*!< 45 VADC */ - ATIMER_IRQn = 46, /*!< 46 ATIMER */ - RTC_IRQn = 47, /*!< 47 RTC */ - RESERVED8_IRQn = 48, - WWDT_IRQn = 49, /*!< 49 WWDT */ - RESERVED9_IRQn = 50, - C_CAN0_IRQn = 51, /*!< 51 C_CAN0 */ - QEI_IRQn = 52, /*!< 52 QEI */ - -// ------------------------- Cortex-M0 Processor Exceptions Numbers ----------------------------- - M0_Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - M0_NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - M0_HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - M0_SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - M0_DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - M0_PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - M0_SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -// --------------------------- LPC43xx Specific Interrupt Numbers ------------------------------- - M0_RTC_IRQn = 0, /*!< 0 RTC */ - M0_M4CORE_IRQn = 1, /*!< 1 M4 */ - M0_DMA_IRQn = 2, /*!< 2 DMA */ - M0_RESERVED0_IRQn = 3, - M0_RESERVED1_IRQn = 4, - M0_ETHERNET_IRQn = 5, /*!< 5 ETHERNET */ - M0_SDIO_IRQn = 6, /*!< 6 SDIO */ - M0_LCD_IRQn = 7, /*!< 7 LCD */ - M0_USB0_IRQn = 8, /*!< 8 USB0 */ - M0_USB1_IRQn = 9, /*!< 9 USB1 */ - M0_SCT_IRQn = 10, /*!< 10 SCT */ - M0_RITIMER_OR_WWDT_IRQn = 11, /*!< 11 RITIMER_OR_WWDT */ - M0_TIMER0_IRQn = 12, /*!< 12 TIMER0 */ - M0_GINT1_IRQn = 13, /*!< 13 GINT1 */ - M0_TIMER3_IRQn = 15, /*!< 15 TIMER3 */ - M0_RESERVED2_IRQn = 14, - M0_RESERVED3_IRQn = 15, - M0_MCPWM_IRQn = 16, /*!< 16 MCPWM */ - M0_ADC0_IRQn = 17, /*!< 17 ADC0 */ - M0_I2C0_OR_I2C1_IRQn = 18, /*!< 18 I2C0_OR_I2C1 */ - M0_SGPIO_IRQn = 19, /*!< 19 SGPIO */ - M0_SPI_OR_DAC_IRQn = 20, /*!< 20 SPI_OR_DAC */ - M0_ADC1_IRQn = 21, /*!< 21 ADC1 */ - M0_SSP0_OR_SSP1_IRQn = 22, /*!< 22 SSP0_OR_SSP1 */ - M0_EVENTROUTER_IRQn = 23, /*!< 23 EVENTROUTER */ - M0_USART0_IRQn = 24, /*!< 24 USART0 */ - M0_UART1_IRQn = 25, /*!< 25 UART1 */ - M0_USART2_OR_C_CAN1_IRQn = 26, /*!< 26 USART2_OR_C_CAN1 */ - M0_USART3_IRQn = 27, /*!< 27 USART3 */ - M0_I2S0_OR_I2S1_OR_QEI_IRQn = 28, /*!< 28 I2S0_OR_I2S1_OR_QEI */ - M0_C_CAN0_IRQn = 29 /*!< 29 C_CAN0 */ +#ifdef CORE_M4 +/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management */ + BusFault_IRQn = -11, /*!< 5 Bus Fault */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +// --------------------------- LPC43xx/M4 Specific Interrupt Numbers ---------------------------- + DAC_IRQn = 0, /*!< 0 DAC interrupt */ + M0APP_IRQn = 1, /*!< 1 Cortex-M0APP; Latched TXEV; for M4-M0APP communication */ + DMA_IRQn = 2, /*!< 2 DMA interrupt */ + + FLASHEEPROM_IRQn = 4, /*!< 4 flash bank A, flash bank B, EEPROM ORed interrupt */ + ETHERNET_IRQn = 5, /*!< 5 Ethernet interrupt */ + SDIO_IRQn = 6, /*!< 6 SD/MMC interrupt */ + LCD_IRQn = 7, /*!< 7 LCD interrupt */ + USB0_IRQn = 8, /*!< 8 OTG interrupt */ + USB1_IRQn = 9, /*!< 9 USB1 interrupt */ + SCT_IRQn = 10, /*!< 10 SCT combined interrupt */ + RITIMER_IRQn = 11, /*!< 11 RI Timer interrupt */ + TIMER0_IRQn = 12, /*!< 12 Timer 0 interrupt */ + TIMER1_IRQn = 13, /*!< 13 Timer 1 interrupt */ + TIMER2_IRQn = 14, /*!< 14 Timer 2 interrupt */ + TIMER3_IRQn = 15, /*!< 15 Timer 3 interrupt */ + MCPWM_IRQn = 16, /*!< 16 Motor control PWM interrupt */ + ADC0_IRQn = 17, /*!< 17 ADC0 interrupt */ + I2C0_IRQn = 18, /*!< 18 I2C0 interrupt */ + I2C1_IRQn = 19, /*!< 19 I2C1 interrupt */ + SPI_IRQn = 20, /*!< 20 SPI interrupt */ + ADC1_IRQn = 21, /*!< 21 ADC1 interrupt */ + SSP0_IRQn = 22, /*!< 22 SSP0 interrupt */ + SSP1_IRQn = 23, /*!< 23 SSP1 interrupt */ + USART0_IRQn = 24, /*!< 24 USART0 interrupt */ + UART1_IRQn = 25, /*!< 25 Combined UART1, Modem interrupt */ + USART2_IRQn = 26, /*!< 26 USART2 interrupt */ + USART3_IRQn = 27, /*!< 27 Combined USART3, IrDA interrupt */ + I2S0_IRQn = 28, /*!< 28 I2S0 interrupt */ + I2S1_IRQn = 29, /*!< 29 I2S1 interrupt */ + SPIFI_IRQn = 30, /*!< 30 SPISI interrupt */ + SGPIO_IRQn = 31, /*!< 31 SGPIO interrupt */ + PIN_INT0_IRQn = 32, /*!< 32 GPIO pin interrupt 0 */ + PIN_INT1_IRQn = 33, /*!< 33 GPIO pin interrupt 1 */ + PIN_INT2_IRQn = 34, /*!< 34 GPIO pin interrupt 2 */ + PIN_INT3_IRQn = 35, /*!< 35 GPIO pin interrupt 3 */ + PIN_INT4_IRQn = 36, /*!< 36 GPIO pin interrupt 4 */ + PIN_INT5_IRQn = 37, /*!< 37 GPIO pin interrupt 5 */ + PIN_INT6_IRQn = 38, /*!< 38 GPIO pin interrupt 6 */ + PIN_INT7_IRQn = 39, /*!< 39 GPIO pin interrupt 7 */ + GINT0_IRQn = 40, /*!< 40 GPIO global interrupt 0 */ + GINT1_IRQn = 41, /*!< 41 GPIO global interrupt 1 */ + EVENTROUTER_IRQn = 42, /*!< 42 Event router interrupt */ + C_CAN1_IRQn = 43, /*!< 43 C_CAN1 interrupt */ + + ADCHS_IRQn = 45, /*!< 45 ADCHS combined interrupt */ + ATIMER_IRQn = 46, /*!< 46 Alarm timer interrupt */ + RTC_IRQn = 47, /*!< 47 RTC interrupt */ + + WWDT_IRQn = 49, /*!< 49 WWDT interrupt */ + M0SUB_IRQn = 50, /*!< 50 TXEV instruction from the M0 subsystem core interrupt */ + C_CAN0_IRQn = 51, /*!< 51 C_CAN0 interrupt */ + QEI_IRQn = 52, /*!< 52 QEI interrupt */ +#endif +#ifdef CORE_M0 +/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + + + + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +// --------------------------- LPC43xx/M0App Specific Interrupt Numbers ------------------------- + M0_RTC_IRQn = 0, /*!< 0 RTC interrupt */ + M0_M4CORE_IRQn = 1, /*!< 1 M4 core interrupt */ + M0_DMA_IRQn = 2, /*!< 2 DMA interrupt */ + + M0_FLASHEEPROMAT_IRQn = 4, /*!< 4 flash bank A, flash bank B, EEPROM, Atimer ORed interrupt */ + M0_ETHERNET_IRQn = 5, /*!< 5 Ethernet interrupt */ + M0_SDIO_IRQn = 6, /*!< 6 SD/MMC interrupt */ + M0_LCD_IRQn = 7, /*!< 7 LCD interrupt */ + M0_USB0_IRQn = 8, /*!< 8 OTG interrupt */ + M0_USB1_IRQn = 9, /*!< 9 USB1 interrupt */ + M0_SCT_IRQn = 10, /*!< 10 SCT combined interrupt */ + M0_RITIMER_OR_WWDT_IRQn = 11, /*!< 11 RI timer, WWDT ORed interrupt */ + M0_TIMER0_IRQn = 12, /*!< 12 Timer 0 interrupt */ + M0_GINT1_IRQn = 13, /*!< 13 GPIO global interrupt 1 */ + M0_PIN_INT4_IRQn = 14, /*!< 14 GPIO pin interrupt 4 */ + M0_TIMER3_IRQn = 15, /*!< 15 Timer 3 */ + M0_MCPWM_IRQn = 16, /*!< 16 Motor control PWM interrupt */ + M0_ADC0_IRQn = 17, /*!< 17 ADC0 interrupt */ + M0_I2C0_OR_I2C1_IRQn = 18, /*!< 18 I2C0, I2C1 ORed interrupt */ + M0_SGPIO_IRQn = 19, /*!< 19 SGPIO interrupt */ + M0_SPI_OR_DAC_IRQn = 20, /*!< 20 SPI, DAC ORed interrupt */ + M0_ADC1_IRQn = 21, /*!< 21 ADC1 interrupt */ + M0_SSP0_OR_SSP1_IRQn = 22, /*!< 22 SSP0, SSP 1 ORed interrupt */ + M0_EVENTROUTER_IRQn = 23, /*!< 23 Event router interrupt */ + M0_USART0_IRQn = 24, /*!< 24 USART0 interrupt */ + M0_UART1_IRQn = 25, /*!< 25 Modem/UART1 interrupt */ + M0_USART2_OR_C_CAN1_IRQn = 26, /*!< 26 USART2, C_CAN1 ORed interrupt */ + M0_USART3_IRQn = 27, /*!< 27 USART3 interrupt */ + M0_I2S0_OR_I2S1_QEI_IRQn = 28, /*!< 28 I2S0, I2S1, QEI ORed interrupt */ + M0_C_CAN0_IRQn = 29, /*!< 29 C_CAN0 interrupt */ + M0_SPIFI_OR_ADCHS_IRQn = 30, /*!< 30 SPIFI, ADCHS ORed interrupt */ + M0_M0SUB_IRQn = 31, /*!< 31 M0SUB core interrupt */ +#endif +#ifdef CORE_M0SUB +/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + + + + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +// --------------------------- LPC43xx/M0Sub Specific Interrupt Numbers ------------------------- + M0S_RTC_IRQn = 0, /*!< 0 RTC interrupt */ + M0S_M4CORE_IRQn = 1, /*!< 1 M4 core interrupt */ + M0S_DMA_IRQn = 2, /*!< 2 DMA interrupt */ + + M0S_SGPIO_INPUT_IRQn = 4, /*!< 4 SGPIO input bit match interrupt */ + M0S_SGPIO_MATCH_IRQn = 5, /*!< 5 SGPIO pattern match interrupt */ + M0S_SGPIO_SHIFT_IRQn = 6, /*!< 6 SGPIO shift clock interrupt */ + M0S_SGPIO_POS_IRQn = 7, /*!< 7 SGPIO capture clock interrupt */ + M0S_USB0_IRQn = 8, /*!< 8 OTG interrupt */ + M0S_USB1_IRQn = 9, /*!< 9 USB1 interrupt */ + M0S_SCT_IRQn = 10, /*!< 10 SCT combined interrupt */ + M0S_RITIMER_IRQn = 11, /*!< 11 RI timer interrupt */ + M0S_GINT1_IRQn = 12, /*!< 12 GPIO global interrupt 1 */ + M0S_TIMER1_IRQn = 13, /*!< 13 Timer 1 interrupt */ + M0S_TIMER2_IRQn = 14, /*!< 14 Timer 2 interrupt */ + M0S_PIN_INT5_IRQn = 15, /*!< 15 GPIO pin interrupt 5 */ + M0S_MCPWM_IRQn = 16, /*!< 16 Motor control PWM interrupt */ + M0S_ADC0_IRQn = 17, /*!< 17 ADC0 interrupt */ + M0S_I2C0_IRQn = 18, /*!< 18 I2C0 interrupt */ + M0S_I2C1_IRQn = 19, /*!< 19 I2C1 interrupt */ + M0S_SPI_IRQn = 20, /*!< 20 SPI interrupt */ + M0S_ADC1_IRQn = 21, /*!< 21 ADC1 interrupt */ + M0S_SSP0_OR_SSP1_IRQn = 22, /*!< 22 SSP0, SSP1 ORed interrupt */ + M0S_EVENTROUTER_IRQn = 23, /*!< 23 Event router interrupt */ + M0S_USART0_IRQn = 24, /*!< 24 USART0 interrupt */ + M0S_UART1_IRQn = 25, /*!< 25 Modem/UART1 interrupt */ + M0S_USART2_OR_C_CAN1_IRQn = 26, /*!< 26 USART2, C_CAN1 ORed interrupt */ + M0S_USART3_IRQn = 27, /*!< 27 USART3 interrupt */ + M0S_I2S0_OR_I2S1_OR_QEI_IRQn = 28, /*!< 28 I2S0, I2S1, QEI ORed interrupt */ + M0S_C_CAN0_IRQn = 29, /*!< 29 C_CAN0 interrupt */ + M0S_SPIFI_OR_ADCHS_IRQn = 30, /*!< 30 SPIFI, ADCHS ORed interrupt */ + M0S_M0APP_IRQn = 31, /*!< 31 M0APP core interrupt */ +#endif } IRQn_Type; /* Event Router Input (ERI) Number Definitions */ @@ -195,34759 +230,24384 @@ typedef enum { * @{ */ -/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M4 Processor and Core Peripherals */ -#ifdef CORE_M4 -#define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -/** @} */ /* End of group Configuration_of_CMSIS */ +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ -#include /*!< Cortex-M4 processor and core peripherals */ -#else -#ifdef CORE_M0 -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 0 /*!< FPU present or not */ -/** @} */ /* End of group Configuration_of_CMSIS */ +#if defined CORE_M4 +/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ +#define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ -#include /*!< Cortex-M4 processor and core peripherals */ -#else -#error Please #define CORE_M0 or CORE_M4 +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ #endif + +#if defined CORE_M0 || defined CORE_M0SUB +/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 0 /*!< FPU present or not */ + +#include "core_cm0.h" /*!< Cortex-M4 processor and core peripherals */ #endif /** @} */ /* End of group Configuration_of_CMSIS */ -#include "system_LPC43xx.h" /*!< LPC43xx System */ +#include "system_LPC43xx.h" /*!< LPC43xx System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + /** @addtogroup Device_Peripheral_Registers * @{ */ -// ------------------------------------------------------------------------------------------------ -// ----- SCT ----- -// ------------------------------------------------------------------------------------------------ +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + + + +/* ================================================================================ */ +/* ================ SCT ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT) + * @brief State Configurable Timer (SCT) with dither engine (SCT) */ -#define CONFIG_SCT_nEV (16) /* Number of events */ -#define CONFIG_SCT_nRG (16) /* Number of match/compare registers */ -#define CONFIG_SCT_nOU (16) /* Number of outputs */ - -typedef struct -{ - __IO uint32_t CONFIG; /* 0x000 Configuration Register */ - union { - __IO uint32_t CTRL_U; /* 0x004 Control Register */ - struct { - __IO uint16_t CTRL_L; /* 0x004 low control register */ - __IO uint16_t CTRL_H; /* 0x006 high control register */ - }; - }; - __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */ - __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */ - __IO uint16_t HALT_L; /* 0x00C halt register for counter L */ - __IO uint16_t HALT_H; /* 0x00E halt register for counter H */ - __IO uint16_t STOP_L; /* 0x010 stop register for counter L */ - __IO uint16_t STOP_H; /* 0x012 stop register for counter H */ - __IO uint16_t START_L; /* 0x014 start register for counter L */ - __IO uint16_t START_H; /* 0x016 start register for counter H */ - uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */ - union { - __IO uint32_t COUNT_U; /* 0x040 counter register */ - struct { - __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */ - __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */ - }; - }; - __IO uint16_t STATE_L; /* 0x044 state register for counter L */ - __IO uint16_t STATE_H; /* 0x046 state register for counter H */ - __I uint32_t INPUT; /* 0x048 input register */ - __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */ - __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */ - __IO uint32_t OUTPUT; /* 0x050 output register */ - __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */ - __IO uint32_t RES; /* 0x058 conflict resolution register */ - __IO uint32_t DMA0REQUEST; /* 0x05C DMA0 Request Register */ - __IO uint32_t DMA1REQUEST; /* 0x060 DMA1 Request Register */ - uint32_t RESERVED2[35]; /* 0x064-0x0EC reserved */ - __IO uint32_t EVEN; /* 0x0F0 event enable register */ - __IO uint32_t EVFLAG; /* 0x0F4 event flag register */ - __IO uint32_t CONEN; /* 0x0F8 conflict enable register */ - __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */ - - union { - __IO union { /* 0x100-... Match / Capture value */ - uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */ - struct { - uint16_t L; /* SCTMATCH[i].L Access to L value */ - uint16_t H; /* SCTMATCH[i].H Access to H value */ - }; - } MATCH[CONFIG_SCT_nRG]; - __I union { - uint32_t U; /* SCTCAP[i].U Unified 32-bit register */ - struct { - uint16_t L; /* SCTCAP[i].L Access to H value */ - uint16_t H; /* SCTCAP[i].H Access to H value */ - }; - } CAP[CONFIG_SCT_nRG]; - }; - - uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */ - - union { - __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */ - __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */ - }; - uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */ - union { - __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */ - __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */ - }; - uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */ - - union { - __IO union { /* 0x200-... Match Reload / Capture Control value */ - uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */ - struct { - uint16_t L; /* SCTMATCHREL[i].L Access to L value */ - uint16_t H; /* SCTMATCHREL[i].H Access to H value */ - }; - } MATCHREL[CONFIG_SCT_nRG]; - __IO union { - uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */ - struct { - uint16_t L; /* SCTCAPCTRL[i].L Access to H value */ - uint16_t H; /* SCTCAPCTRL[i].H Access to H value */ - }; - } CAPCTRL[CONFIG_SCT_nRG]; - }; - - uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */ - - union { - __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */ - __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */ - }; - uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */ - union { - __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */ - __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */ - }; - uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */ - - __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/ - uint32_t STATE; /* Event State Register */ - uint32_t CTRL; /* Event Control Register */ - } EVENT[CONFIG_SCT_nEV]; - - uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */ - - __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */ - uint32_t SET; /* Output n Set Register */ - uint32_t CLR; /* Output n Clear Register */ - } OUT[CONFIG_SCT_nOU]; - - uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */ - - __I uint32_t MODULECONTENT; /* 0x7FC Module Content */ +typedef struct { /*!< (@ 0x40000000) SCT Structure */ + __IO uint32_t CONFIG; /*!< (@ 0x40000000) SCT configuration register */ + __IO uint32_t CTRL; /*!< (@ 0x40000004) SCT control register */ + __IO uint32_t LIMIT; /*!< (@ 0x40000008) SCT limit register */ + __IO uint32_t HALT; /*!< (@ 0x4000000C) SCT halt condition register */ + __IO uint32_t STOP; /*!< (@ 0x40000010) SCT stop condition register */ + __IO uint32_t START; /*!< (@ 0x40000014) SCT start condition register */ + __IO uint32_t DITHER; /*!< (@ 0x40000018) SCT dither condition register */ + __I uint32_t RESERVED0[9]; + __IO uint32_t COUNT; /*!< (@ 0x40000040) SCT counter register */ + __IO uint32_t STATE; /*!< (@ 0x40000044) SCT state register */ + __I uint32_t INPUT; /*!< (@ 0x40000048) SCT input register */ + __IO uint32_t REGMODE; /*!< (@ 0x4000004C) SCT match/capture registers mode register */ + __IO uint32_t OUTPUT; /*!< (@ 0x40000050) SCT output register */ + __IO uint32_t OUTPUTDIRCTRL; /*!< (@ 0x40000054) SCT output counter direction control register */ + __IO uint32_t RES; /*!< (@ 0x40000058) SCT conflict resolution register */ + __IO uint32_t DMAREQ0; /*!< (@ 0x4000005C) SCT DMA request 0 register */ + __IO uint32_t DMAREQ1; /*!< (@ 0x40000060) SCT DMA request 1 register */ + __I uint32_t RESERVED1[35]; + __IO uint32_t EVEN; /*!< (@ 0x400000F0) SCT event enable register */ + __IO uint32_t EVFLAG; /*!< (@ 0x400000F4) SCT event flag register */ + __IO uint32_t CONEN; /*!< (@ 0x400000F8) SCT conflict enable register */ + __IO uint32_t CONFLAG; /*!< (@ 0x400000FC) SCT conflict flag register */ + + union { + __IO uint32_t CAP0; /*!< (@ 0x40000100) SCT capture register of capture channel 0 to + 15; REGMOD0 to REGMODE15 = 1 */ + __IO uint32_t MATCH0; /*!< (@ 0x40000100) SCT match value register of match channels 0 + to 15; REGMOD0 to REGMODE15 = 0 */ + }; + + union { + __IO uint32_t CAP1; /*!< (@ 0x40000104) SCT capture register of capture channel 0 to + 15; REGMOD0 to REGMODE15 = 1 */ + __IO uint32_t MATCH1; /*!< (@ 0x40000104) SCT match value register of match channels 0 + to 15; REGMOD0 to REGMODE15 = 0 */ + }; + + union { + __IO uint32_t CAP2; /*!< (@ 0x40000108) SCT capture register of capture channel 0 to + 15; REGMOD0 to REGMODE15 = 1 */ + __IO uint32_t MATCH2; /*!< (@ 0x40000108) SCT match value register of match channels 0 + to 15; REGMOD0 to REGMODE15 = 0 */ + }; + + union { + __IO uint32_t CAP3; /*!< (@ 0x4000010C) SCT capture register of capture channel 0 to + 15; REGMOD0 to REGMODE15 = 1 */ + __IO uint32_t MATCH3; /*!< (@ 0x4000010C) SCT match value register of match channels 0 + to 15; REGMOD0 to REGMODE15 = 0 */ + }; + + union { + __IO uint32_t MATCH4; /*!< (@ 0x40000110) SCT match value register of match channels 0 + to 15; REGMOD0 to REGMODE15 = 0 */ + __IO uint32_t CAP4; /*!< (@ 0x40000110) SCT capture register of capture channel 0 to + 15; REGMOD0 to REGMODE15 = 1 */ + }; + + union { + __IO uint32_t CAP5; /*!< (@ 0x40000114) SCT capture register of capture channel 0 to + 15; REGMOD0 to REGMODE15 = 1 */ + __IO uint32_t MATCH5; /*!< (@ 0x40000114) SCT match value register of match channels 0 + to 15; REGMOD0 to REGMODE15 = 0 */ + }; + + union { + __IO uint32_t MATCH6; /*!< (@ 0x40000118) SCT match value register of match channels 0 + to 15; REGMOD0 to REGMODE15 = 0 */ + __IO uint32_t CAP6; /*!< (@ 0x40000118) SCT capture register of capture channel 0 to + 15; REGMOD0 to REGMODE15 = 1 */ + }; + + union { + __IO uint32_t MATCH7; /*!< (@ 0x4000011C) SCT match value register of match channels 0 + to 15; REGMOD0 to REGMODE15 = 0 */ + __IO uint32_t CAP7; /*!< (@ 0x4000011C) SCT capture register of capture channel 0 to + 15; REGMOD0 to REGMODE15 = 1 */ + }; + + union { + __IO uint32_t MATCH8; /*!< (@ 0x40000120) SCT match value register of match channels 0 + to 15; REGMOD0 to REGMODE15 = 0 */ + __IO uint32_t CAP8; /*!< (@ 0x40000120) SCT capture register of capture channel 0 to + 15; REGMOD0 to REGMODE15 = 1 */ + }; + + union { + __IO uint32_t MATCH9; /*!< (@ 0x40000124) SCT match value register of match channels 0 + to 15; REGMOD0 to REGMODE15 = 0 */ + __IO uint32_t CAP9; /*!< (@ 0x40000124) SCT capture register of capture channel 0 to + 15; REGMOD0 to REGMODE15 = 1 */ + }; + + union { + __IO uint32_t MATCH10; /*!< (@ 0x40000128) SCT match value register of match channels 0 + to 15; REGMOD0 to REGMODE15 = 0 */ + __IO uint32_t CAP10; /*!< (@ 0x40000128) SCT capture register of capture channel 0 to + 15; REGMOD0 to REGMODE15 = 1 */ + }; + + union { + __IO uint32_t MATCH11; /*!< (@ 0x4000012C) SCT match value register of match channels 0 + to 15; REGMOD0 to REGMODE15 = 0 */ + __IO uint32_t CAP11; /*!< (@ 0x4000012C) SCT capture register of capture channel 0 to + 15; REGMOD0 to REGMODE15 = 1 */ + }; + + union { + __IO uint32_t MATCH12; /*!< (@ 0x40000130) SCT match value register of match channels 0 + to 15; REGMOD0 to REGMODE15 = 0 */ + __IO uint32_t CAP12; /*!< (@ 0x40000130) SCT capture register of capture channel 0 to + 15; REGMOD0 to REGMODE15 = 1 */ + }; + + union { + __IO uint32_t CAP13; /*!< (@ 0x40000134) SCT capture register of capture channel 0 to + 15; REGMOD0 to REGMODE15 = 1 */ + __IO uint32_t MATCH13; /*!< (@ 0x40000134) SCT match value register of match channels 0 + to 15; REGMOD0 to REGMODE15 = 0 */ + }; + + union { + __IO uint32_t MATCH14; /*!< (@ 0x40000138) SCT match value register of match channels 0 + to 15; REGMOD0 to REGMODE15 = 0 */ + __IO uint32_t CAP14; /*!< (@ 0x40000138) SCT capture register of capture channel 0 to + 15; REGMOD0 to REGMODE15 = 1 */ + }; + + union { + __IO uint32_t CAP15; /*!< (@ 0x4000013C) SCT capture register of capture channel 0 to + 15; REGMOD0 to REGMODE15 = 1 */ + __IO uint32_t MATCH15; /*!< (@ 0x4000013C) SCT match value register of match channels 0 + to 15; REGMOD0 to REGMODE15 = 0 */ + }; + __IO uint32_t FRACMAT0; /*!< (@ 0x40000140) Fractional match registers 0 to 5 for SCT match + value registers 0 to 5. */ + __IO uint32_t FRACMAT1; /*!< (@ 0x40000144) Fractional match registers 0 to 5 for SCT match + value registers 0 to 5. */ + __IO uint32_t FRACMAT2; /*!< (@ 0x40000148) Fractional match registers 0 to 5 for SCT match + value registers 0 to 5. */ + __IO uint32_t FRACMAT3; /*!< (@ 0x4000014C) Fractional match registers 0 to 5 for SCT match + value registers 0 to 5. */ + __IO uint32_t FRACMAT4; /*!< (@ 0x40000150) Fractional match registers 0 to 5 for SCT match + value registers 0 to 5. */ + __IO uint32_t FRACMAT5; /*!< (@ 0x40000154) Fractional match registers 0 to 5 for SCT match + value registers 0 to 5. */ + __I uint32_t RESERVED2[42]; + + union { + __IO uint32_t CAPCTRL0; /*!< (@ 0x40000200) SCT capture control register 0 to 15; REGMOD0 + = 1 to REGMODE15 = 1 */ + __IO uint32_t MATCHREL0; /*!< (@ 0x40000200) SCT match reload value register 0 to 15; REGMOD0 + = 0 to REGMODE15 = 0 */ + }; + + union { + __IO uint32_t MATCHREL1; /*!< (@ 0x40000204) SCT match reload value register 0 to 15; REGMOD0 + = 0 to REGMODE15 = 0 */ + __IO uint32_t CAPCTRL1; /*!< (@ 0x40000204) SCT capture control register 0 to 15; REGMOD0 + = 1 to REGMODE15 = 1 */ + }; + + union { + __IO uint32_t CAPCTRL2; /*!< (@ 0x40000208) SCT capture control register 0 to 15; REGMOD0 + = 1 to REGMODE15 = 1 */ + __IO uint32_t MATCHREL2; /*!< (@ 0x40000208) SCT match reload value register 0 to 15; REGMOD0 + = 0 to REGMODE15 = 0 */ + }; + + union { + __IO uint32_t MATCHREL3; /*!< (@ 0x4000020C) SCT match reload value register 0 to 15; REGMOD0 + = 0 to REGMODE15 = 0 */ + __IO uint32_t CAPCTRL3; /*!< (@ 0x4000020C) SCT capture control register 0 to 15; REGMOD0 + = 1 to REGMODE15 = 1 */ + }; + + union { + __IO uint32_t CAPCTRL4; /*!< (@ 0x40000210) SCT capture control register 0 to 15; REGMOD0 + = 1 to REGMODE15 = 1 */ + __IO uint32_t MATCHREL4; /*!< (@ 0x40000210) SCT match reload value register 0 to 15; REGMOD0 + = 0 to REGMODE15 = 0 */ + }; + + union { + __IO uint32_t CAPCTRL5; /*!< (@ 0x40000214) SCT capture control register 0 to 15; REGMOD0 + = 1 to REGMODE15 = 1 */ + __IO uint32_t MATCHREL5; /*!< (@ 0x40000214) SCT match reload value register 0 to 15; REGMOD0 + = 0 to REGMODE15 = 0 */ + }; + + union { + __IO uint32_t MATCHREL6; /*!< (@ 0x40000218) SCT match reload value register 0 to 15; REGMOD0 + = 0 to REGMODE15 = 0 */ + __IO uint32_t CAPCTRL6; /*!< (@ 0x40000218) SCT capture control register 0 to 15; REGMOD0 + = 1 to REGMODE15 = 1 */ + }; + + union { + __IO uint32_t CAPCTRL7; /*!< (@ 0x4000021C) SCT capture control register 0 to 15; REGMOD0 + = 1 to REGMODE15 = 1 */ + __IO uint32_t MATCHREL7; /*!< (@ 0x4000021C) SCT match reload value register 0 to 15; REGMOD0 + = 0 to REGMODE15 = 0 */ + }; + + union { + __IO uint32_t MATCHREL8; /*!< (@ 0x40000220) SCT match reload value register 0 to 15; REGMOD0 + = 0 to REGMODE15 = 0 */ + __IO uint32_t CAPCTRL8; /*!< (@ 0x40000220) SCT capture control register 0 to 15; REGMOD0 + = 1 to REGMODE15 = 1 */ + }; + + union { + __IO uint32_t CAPCTRL9; /*!< (@ 0x40000224) SCT capture control register 0 to 15; REGMOD0 + = 1 to REGMODE15 = 1 */ + __IO uint32_t MATCHREL9; /*!< (@ 0x40000224) SCT match reload value register 0 to 15; REGMOD0 + = 0 to REGMODE15 = 0 */ + }; + + union { + __IO uint32_t MATCHREL10; /*!< (@ 0x40000228) SCT match reload value register 0 to 15; REGMOD0 + = 0 to REGMODE15 = 0 */ + __IO uint32_t CAPCTRL10; /*!< (@ 0x40000228) SCT capture control register 0 to 15; REGMOD0 + = 1 to REGMODE15 = 1 */ + }; + + union { + __IO uint32_t MATCHREL11; /*!< (@ 0x4000022C) SCT match reload value register 0 to 15; REGMOD0 + = 0 to REGMODE15 = 0 */ + __IO uint32_t CAPCTRL11; /*!< (@ 0x4000022C) SCT capture control register 0 to 15; REGMOD0 + = 1 to REGMODE15 = 1 */ + }; + + union { + __IO uint32_t MATCHREL12; /*!< (@ 0x40000230) SCT match reload value register 0 to 15; REGMOD0 + = 0 to REGMODE15 = 0 */ + __IO uint32_t CAPCTRL12; /*!< (@ 0x40000230) SCT capture control register 0 to 15; REGMOD0 + = 1 to REGMODE15 = 1 */ + }; + + union { + __IO uint32_t CAPCTRL13; /*!< (@ 0x40000234) SCT capture control register 0 to 15; REGMOD0 + = 1 to REGMODE15 = 1 */ + __IO uint32_t MATCHREL13; /*!< (@ 0x40000234) SCT match reload value register 0 to 15; REGMOD0 + = 0 to REGMODE15 = 0 */ + }; + + union { + __IO uint32_t CAPCTRL14; /*!< (@ 0x40000238) SCT capture control register 0 to 15; REGMOD0 + = 1 to REGMODE15 = 1 */ + __IO uint32_t MATCHREL14; /*!< (@ 0x40000238) SCT match reload value register 0 to 15; REGMOD0 + = 0 to REGMODE15 = 0 */ + }; + union { + __IO uint32_t CAPCTRL15; /*!< (@ 0x4000023C) SCT capture control register 0 to 15; REGMOD0 + = 1 to REGMODE15 = 1 */ + __IO uint32_t MATCHREL15; /*!< (@ 0x4000023C) SCT match reload value register 0 to 15; REGMOD0 + = 0 to REGMODE15 = 0 */ + }; + __IO uint32_t FRACMATREL0; /*!< (@ 0x40000240) Fractional match reload registers 0 to 5 for + SCT match value registers 0 to 5. */ + __IO uint32_t FRACMATREL1; /*!< (@ 0x40000244) Fractional match reload registers 0 to 5 for + SCT match value registers 0 to 5. */ + __IO uint32_t FRACMATREL2; /*!< (@ 0x40000248) Fractional match reload registers 0 to 5 for + SCT match value registers 0 to 5. */ + __IO uint32_t FRACMATREL3; /*!< (@ 0x4000024C) Fractional match reload registers 0 to 5 for + SCT match value registers 0 to 5. */ + __IO uint32_t FRACMATREL4; /*!< (@ 0x40000250) Fractional match reload registers 0 to 5 for + SCT match value registers 0 to 5. */ + __IO uint32_t FRACMATREL5; /*!< (@ 0x40000254) Fractional match reload registers 0 to 5 for + SCT match value registers 0 to 5. */ + __I uint32_t RESERVED3[42]; + __IO uint32_t EV0_STATE; /*!< (@ 0x40000300) SCT event state register 0 */ + __IO uint32_t EV0_CTRL; /*!< (@ 0x40000304) SCT event control register 0 */ + __IO uint32_t EV1_STATE; /*!< (@ 0x40000308) SCT event state register 0 */ + __IO uint32_t EV1_CTRL; /*!< (@ 0x4000030C) SCT event control register 0 */ + __IO uint32_t EV2_STATE; /*!< (@ 0x40000310) SCT event state register 0 */ + __IO uint32_t EV2_CTRL; /*!< (@ 0x40000314) SCT event control register 0 */ + __IO uint32_t EV3_STATE; /*!< (@ 0x40000318) SCT event state register 0 */ + __IO uint32_t EV3_CTRL; /*!< (@ 0x4000031C) SCT event control register 0 */ + __IO uint32_t EV4_STATE; /*!< (@ 0x40000320) SCT event state register 0 */ + __IO uint32_t EV4_CTRL; /*!< (@ 0x40000324) SCT event control register 0 */ + __IO uint32_t EV5_STATE; /*!< (@ 0x40000328) SCT event state register 0 */ + __IO uint32_t EV5_CTRL; /*!< (@ 0x4000032C) SCT event control register 0 */ + __IO uint32_t EV6_STATE; /*!< (@ 0x40000330) SCT event state register 0 */ + __IO uint32_t EV6_CTRL; /*!< (@ 0x40000334) SCT event control register 0 */ + __IO uint32_t EV7_STATE; /*!< (@ 0x40000338) SCT event state register 0 */ + __IO uint32_t EV7_CTRL; /*!< (@ 0x4000033C) SCT event control register 0 */ + __IO uint32_t EV8_STATE; /*!< (@ 0x40000340) SCT event state register 0 */ + __IO uint32_t EV8_CTRL; /*!< (@ 0x40000344) SCT event control register 0 */ + __IO uint32_t EV9_STATE; /*!< (@ 0x40000348) SCT event state register 0 */ + __IO uint32_t EV9_CTRL; /*!< (@ 0x4000034C) SCT event control register 0 */ + __IO uint32_t EV10_STATE; /*!< (@ 0x40000350) SCT event state register 0 */ + __IO uint32_t EV10_CTRL; /*!< (@ 0x40000354) SCT event control register 0 */ + __IO uint32_t EV11_STATE; /*!< (@ 0x40000358) SCT event state register 0 */ + __IO uint32_t EV11_CTRL; /*!< (@ 0x4000035C) SCT event control register 0 */ + __IO uint32_t EV12_STATE; /*!< (@ 0x40000360) SCT event state register 0 */ + __IO uint32_t EV12_CTRL; /*!< (@ 0x40000364) SCT event control register 0 */ + __IO uint32_t EV13_STATE; /*!< (@ 0x40000368) SCT event state register 0 */ + __IO uint32_t EV13_CTRL; /*!< (@ 0x4000036C) SCT event control register 0 */ + __IO uint32_t EV14_STATE; /*!< (@ 0x40000370) SCT event state register 0 */ + __IO uint32_t EV14_CTRL; /*!< (@ 0x40000374) SCT event control register 0 */ + __IO uint32_t EV15_STATE; /*!< (@ 0x40000378) SCT event state register 0 */ + __IO uint32_t EV15_CTRL; /*!< (@ 0x4000037C) SCT event control register 0 */ + __I uint32_t RESERVED4[96]; + __IO uint32_t OUT0_SET; /*!< (@ 0x40000500) SCT output 0 set register */ + __IO uint32_t OUT0_CLR; /*!< (@ 0x40000504) SCT output 0 clear register */ + __IO uint32_t OUT1_SET; /*!< (@ 0x40000508) SCT output 0 set register */ + __IO uint32_t OUT1_CLR; /*!< (@ 0x4000050C) SCT output 0 clear register */ + __IO uint32_t OUT2_SET; /*!< (@ 0x40000510) SCT output 0 set register */ + __IO uint32_t OUT2_CLR; /*!< (@ 0x40000514) SCT output 0 clear register */ + __IO uint32_t OUT3_SET; /*!< (@ 0x40000518) SCT output 0 set register */ + __IO uint32_t OUT3_CLR; /*!< (@ 0x4000051C) SCT output 0 clear register */ + __IO uint32_t OUT4_SET; /*!< (@ 0x40000520) SCT output 0 set register */ + __IO uint32_t OUT4_CLR; /*!< (@ 0x40000524) SCT output 0 clear register */ + __IO uint32_t OUT5_SET; /*!< (@ 0x40000528) SCT output 0 set register */ + __IO uint32_t OUT5_CLR; /*!< (@ 0x4000052C) SCT output 0 clear register */ + __IO uint32_t OUT6_SET; /*!< (@ 0x40000530) SCT output 0 set register */ + __IO uint32_t OUT6_CLR; /*!< (@ 0x40000534) SCT output 0 clear register */ + __IO uint32_t OUT7_SET; /*!< (@ 0x40000538) SCT output 0 set register */ + __IO uint32_t OUT7_CLR; /*!< (@ 0x4000053C) SCT output 0 clear register */ + __IO uint32_t OUT8_SET; /*!< (@ 0x40000540) SCT output 0 set register */ + __IO uint32_t OUT8_CLR; /*!< (@ 0x40000544) SCT output 0 clear register */ + __IO uint32_t OUT9_SET; /*!< (@ 0x40000548) SCT output 0 set register */ + __IO uint32_t OUT9_CLR; /*!< (@ 0x4000054C) SCT output 0 clear register */ + __IO uint32_t OUT10_SET; /*!< (@ 0x40000550) SCT output 0 set register */ + __IO uint32_t OUT10_CLR; /*!< (@ 0x40000554) SCT output 0 clear register */ + __IO uint32_t OUT11_SET; /*!< (@ 0x40000558) SCT output 0 set register */ + __IO uint32_t OUT11_CLR; /*!< (@ 0x4000055C) SCT output 0 clear register */ + __IO uint32_t OUT12_SET; /*!< (@ 0x40000560) SCT output 0 set register */ + __IO uint32_t OUT12_CLR; /*!< (@ 0x40000564) SCT output 0 clear register */ + __IO uint32_t OUT13_SET; /*!< (@ 0x40000568) SCT output 0 set register */ + __IO uint32_t OUT13_CLR; /*!< (@ 0x4000056C) SCT output 0 clear register */ + __IO uint32_t OUT14_SET; /*!< (@ 0x40000570) SCT output 0 set register */ + __IO uint32_t OUT14_CLR; /*!< (@ 0x40000574) SCT output 0 clear register */ + __IO uint32_t OUT15_SET; /*!< (@ 0x40000578) SCT output 0 set register */ + __IO uint32_t OUT15_CLR; /*!< (@ 0x4000057C) SCT output 0 clear register */ } LPC_SCT_Type; -// ------------------------------------------------------------------------------------------------ -// ----- GPDMA ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ GPDMA ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx General Purpose DMA (GPDMA) controller Modification date=1/19/2011 Major revision=0 Minor revision=7 (GPDMA) + * @brief General Purpose DMA (GPDMA) (GPDMA) */ -typedef struct { /*!< (@ 0x40002000) GPDMA Structure */ - __I uint32_t INTSTAT; /*!< (@ 0x40002000) DMA Interrupt Status Register */ - __I uint32_t INTTCSTAT; /*!< (@ 0x40002004) DMA Interrupt Terminal Count Request Status Register */ - __O uint32_t INTTCCLEAR; /*!< (@ 0x40002008) DMA Interrupt Terminal Count Request Clear Register */ - __I uint32_t INTERRSTAT; /*!< (@ 0x4000200C) DMA Interrupt Error Status Register */ - __O uint32_t INTERRCLR; /*!< (@ 0x40002010) DMA Interrupt Error Clear Register */ - __I uint32_t RAWINTTCSTAT; /*!< (@ 0x40002014) DMA Raw Interrupt Terminal Count Status Register */ - __I uint32_t RAWINTERRSTAT; /*!< (@ 0x40002018) DMA Raw Error Interrupt Status Register */ - __I uint32_t ENBLDCHNS; /*!< (@ 0x4000201C) DMA Enabled Channel Register */ - __IO uint32_t SOFTBREQ; /*!< (@ 0x40002020) DMA Software Burst Request Register */ - __IO uint32_t SOFTSREQ; /*!< (@ 0x40002024) DMA Software Single Request Register */ - __IO uint32_t SOFTLBREQ; /*!< (@ 0x40002028) DMA Software Last Burst Request Register */ - __IO uint32_t SOFTLSREQ; /*!< (@ 0x4000202C) DMA Software Last Single Request Register */ - __IO uint32_t CONFIG; /*!< (@ 0x40002030) DMA Configuration Register */ - __IO uint32_t SYNC; /*!< (@ 0x40002034) DMA Synchronization Register */ +typedef struct { /*!< (@ 0x40002000) GPDMA Structure */ + __I uint32_t INTSTAT; /*!< (@ 0x40002000) DMA Interrupt Status Register */ + __I uint32_t INTTCSTAT; /*!< (@ 0x40002004) DMA Interrupt Terminal Count Request Status Register */ + __O uint32_t INTTCCLEAR; /*!< (@ 0x40002008) DMA Interrupt Terminal Count Request Clear Register */ + __I uint32_t INTERRSTAT; /*!< (@ 0x4000200C) DMA Interrupt Error Status Register */ + __O uint32_t INTERRCLR; /*!< (@ 0x40002010) DMA Interrupt Error Clear Register */ + __I uint32_t RAWINTTCSTAT; /*!< (@ 0x40002014) DMA Raw Interrupt Terminal Count Status Register */ + __I uint32_t RAWINTERRSTAT; /*!< (@ 0x40002018) DMA Raw Error Interrupt Status Register */ + __I uint32_t ENBLDCHNS; /*!< (@ 0x4000201C) DMA Enabled Channel Register */ + __IO uint32_t SOFTBREQ; /*!< (@ 0x40002020) DMA Software Burst Request Register */ + __IO uint32_t SOFTSREQ; /*!< (@ 0x40002024) DMA Software Single Request Register */ + __IO uint32_t SOFTLBREQ; /*!< (@ 0x40002028) DMA Software Last Burst Request Register */ + __IO uint32_t SOFTLSREQ; /*!< (@ 0x4000202C) DMA Software Last Single Request Register */ + __IO uint32_t CONFIG; /*!< (@ 0x40002030) DMA Configuration Register */ + __IO uint32_t SYNC; /*!< (@ 0x40002034) DMA Synchronization Register */ __I uint32_t RESERVED0[50]; - __IO uint32_t C0SRCADDR; /*!< (@ 0x40002100) DMA Channel Source Address Register */ - __IO uint32_t C0DESTADDR; /*!< (@ 0x40002104) DMA Channel Destination Address Register */ - __IO uint32_t C0LLI; /*!< (@ 0x40002108) DMA Channel Linked List Item Register */ - __IO uint32_t C0CONTROL; /*!< (@ 0x4000210C) DMA Channel Control Register */ - __IO uint32_t C0CONFIG; /*!< (@ 0x40002110) DMA Channel Configuration Register */ + __IO uint32_t C0SRCADDR; /*!< (@ 0x40002100) DMA Channel Source Address Register */ + __IO uint32_t C0DESTADDR; /*!< (@ 0x40002104) DMA Channel Destination Address Register */ + __IO uint32_t C0LLI; /*!< (@ 0x40002108) DMA Channel Linked List Item Register */ + __IO uint32_t C0CONTROL; /*!< (@ 0x4000210C) DMA Channel Control Register */ + __IO uint32_t C0CONFIG; /*!< (@ 0x40002110) DMA Channel Configuration Register */ __I uint32_t RESERVED1[3]; - __IO uint32_t C1SRCADDR; /*!< (@ 0x40002120) DMA Channel Source Address Register */ - __IO uint32_t C1DESTADDR; /*!< (@ 0x40002124) DMA Channel Destination Address Register */ - __IO uint32_t C1LLI; /*!< (@ 0x40002128) DMA Channel Linked List Item Register */ - __IO uint32_t C1CONTROL; /*!< (@ 0x4000212C) DMA Channel Control Register */ - __IO uint32_t C1CONFIG; /*!< (@ 0x40002130) DMA Channel Configuration Register */ + __IO uint32_t C1SRCADDR; /*!< (@ 0x40002120) DMA Channel Source Address Register */ + __IO uint32_t C1DESTADDR; /*!< (@ 0x40002124) DMA Channel Destination Address Register */ + __IO uint32_t C1LLI; /*!< (@ 0x40002128) DMA Channel Linked List Item Register */ + __IO uint32_t C1CONTROL; /*!< (@ 0x4000212C) DMA Channel Control Register */ + __IO uint32_t C1CONFIG; /*!< (@ 0x40002130) DMA Channel Configuration Register */ __I uint32_t RESERVED2[3]; - __IO uint32_t C2SRCADDR; /*!< (@ 0x40002140) DMA Channel Source Address Register */ - __IO uint32_t C2DESTADDR; /*!< (@ 0x40002144) DMA Channel Destination Address Register */ - __IO uint32_t C2LLI; /*!< (@ 0x40002148) DMA Channel Linked List Item Register */ - __IO uint32_t C2CONTROL; /*!< (@ 0x4000214C) DMA Channel Control Register */ - __IO uint32_t C2CONFIG; /*!< (@ 0x40002150) DMA Channel Configuration Register */ + __IO uint32_t C2SRCADDR; /*!< (@ 0x40002140) DMA Channel Source Address Register */ + __IO uint32_t C2DESTADDR; /*!< (@ 0x40002144) DMA Channel Destination Address Register */ + __IO uint32_t C2LLI; /*!< (@ 0x40002148) DMA Channel Linked List Item Register */ + __IO uint32_t C2CONTROL; /*!< (@ 0x4000214C) DMA Channel Control Register */ + __IO uint32_t C2CONFIG; /*!< (@ 0x40002150) DMA Channel Configuration Register */ __I uint32_t RESERVED3[3]; - __IO uint32_t C3SRCADDR; /*!< (@ 0x40002160) DMA Channel Source Address Register */ - __IO uint32_t C3DESTADDR; /*!< (@ 0x40002164) DMA Channel Destination Address Register */ - __IO uint32_t C3LLI; /*!< (@ 0x40002168) DMA Channel Linked List Item Register */ - __IO uint32_t C3CONTROL; /*!< (@ 0x4000216C) DMA Channel Control Register */ - __IO uint32_t C3CONFIG; /*!< (@ 0x40002170) DMA Channel Configuration Register */ + __IO uint32_t C3SRCADDR; /*!< (@ 0x40002160) DMA Channel Source Address Register */ + __IO uint32_t C3DESTADDR; /*!< (@ 0x40002164) DMA Channel Destination Address Register */ + __IO uint32_t C3LLI; /*!< (@ 0x40002168) DMA Channel Linked List Item Register */ + __IO uint32_t C3CONTROL; /*!< (@ 0x4000216C) DMA Channel Control Register */ + __IO uint32_t C3CONFIG; /*!< (@ 0x40002170) DMA Channel Configuration Register */ __I uint32_t RESERVED4[3]; - __IO uint32_t C4SRCADDR; /*!< (@ 0x40002180) DMA Channel Source Address Register */ - __IO uint32_t C4DESTADDR; /*!< (@ 0x40002184) DMA Channel Destination Address Register */ - __IO uint32_t C4LLI; /*!< (@ 0x40002188) DMA Channel Linked List Item Register */ - __IO uint32_t C4CONTROL; /*!< (@ 0x4000218C) DMA Channel Control Register */ - __IO uint32_t C4CONFIG; /*!< (@ 0x40002190) DMA Channel Configuration Register */ + __IO uint32_t C4SRCADDR; /*!< (@ 0x40002180) DMA Channel Source Address Register */ + __IO uint32_t C4DESTADDR; /*!< (@ 0x40002184) DMA Channel Destination Address Register */ + __IO uint32_t C4LLI; /*!< (@ 0x40002188) DMA Channel Linked List Item Register */ + __IO uint32_t C4CONTROL; /*!< (@ 0x4000218C) DMA Channel Control Register */ + __IO uint32_t C4CONFIG; /*!< (@ 0x40002190) DMA Channel Configuration Register */ __I uint32_t RESERVED5[3]; - __IO uint32_t C5SRCADDR; /*!< (@ 0x400021A0) DMA Channel Source Address Register */ - __IO uint32_t C5DESTADDR; /*!< (@ 0x400021A4) DMA Channel Destination Address Register */ - __IO uint32_t C5LLI; /*!< (@ 0x400021A8) DMA Channel Linked List Item Register */ - __IO uint32_t C5CONTROL; /*!< (@ 0x400021AC) DMA Channel Control Register */ - __IO uint32_t C5CONFIG; /*!< (@ 0x400021B0) DMA Channel Configuration Register */ + __IO uint32_t C5SRCADDR; /*!< (@ 0x400021A0) DMA Channel Source Address Register */ + __IO uint32_t C5DESTADDR; /*!< (@ 0x400021A4) DMA Channel Destination Address Register */ + __IO uint32_t C5LLI; /*!< (@ 0x400021A8) DMA Channel Linked List Item Register */ + __IO uint32_t C5CONTROL; /*!< (@ 0x400021AC) DMA Channel Control Register */ + __IO uint32_t C5CONFIG; /*!< (@ 0x400021B0) DMA Channel Configuration Register */ __I uint32_t RESERVED6[3]; - __IO uint32_t C6SRCADDR; /*!< (@ 0x400021C0) DMA Channel Source Address Register */ - __IO uint32_t C6DESTADDR; /*!< (@ 0x400021C4) DMA Channel Destination Address Register */ - __IO uint32_t C6LLI; /*!< (@ 0x400021C8) DMA Channel Linked List Item Register */ - __IO uint32_t C6CONTROL; /*!< (@ 0x400021CC) DMA Channel Control Register */ - __IO uint32_t C6CONFIG; /*!< (@ 0x400021D0) DMA Channel Configuration Register */ + __IO uint32_t C6SRCADDR; /*!< (@ 0x400021C0) DMA Channel Source Address Register */ + __IO uint32_t C6DESTADDR; /*!< (@ 0x400021C4) DMA Channel Destination Address Register */ + __IO uint32_t C6LLI; /*!< (@ 0x400021C8) DMA Channel Linked List Item Register */ + __IO uint32_t C6CONTROL; /*!< (@ 0x400021CC) DMA Channel Control Register */ + __IO uint32_t C6CONFIG; /*!< (@ 0x400021D0) DMA Channel Configuration Register */ __I uint32_t RESERVED7[3]; - __IO uint32_t C7SRCADDR; /*!< (@ 0x400021E0) DMA Channel Source Address Register */ - __IO uint32_t C7DESTADDR; /*!< (@ 0x400021E4) DMA Channel Destination Address Register */ - __IO uint32_t C7LLI; /*!< (@ 0x400021E8) DMA Channel Linked List Item Register */ - __IO uint32_t C7CONTROL; /*!< (@ 0x400021EC) DMA Channel Control Register */ - __IO uint32_t C7CONFIG; /*!< (@ 0x400021F0) DMA Channel Configuration Register */ + __IO uint32_t C7SRCADDR; /*!< (@ 0x400021E0) DMA Channel Source Address Register */ + __IO uint32_t C7DESTADDR; /*!< (@ 0x400021E4) DMA Channel Destination Address Register */ + __IO uint32_t C7LLI; /*!< (@ 0x400021E8) DMA Channel Linked List Item Register */ + __IO uint32_t C7CONTROL; /*!< (@ 0x400021EC) DMA Channel Control Register */ + __IO uint32_t C7CONFIG; /*!< (@ 0x400021F0) DMA Channel Configuration Register */ } LPC_GPDMA_Type; -// ------------------------------------------------------------------------------------------------ -// ----- SDMMC ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ SPIFI ================ */ +/* ================================================================================ */ + + +/** + * @brief SPI Flash Interface (SPIFI) (SPIFI) + */ + +typedef struct { /*!< (@ 0x40003000) SPIFI Structure */ + __IO uint32_t CTRL; /*!< (@ 0x40003000) SPIFI control register */ + __IO uint32_t CMD; /*!< (@ 0x40003004) SPIFI command register */ + __IO uint32_t ADDR; /*!< (@ 0x40003008) SPIFI address register */ + __IO uint32_t IDATA; /*!< (@ 0x4000300C) SPIFI intermediate data register */ + __IO uint32_t CLIMIT; /*!< (@ 0x40003010) SPIFI cache limit register */ + __IO uint32_t DATA; /*!< (@ 0x40003014) SPIFI data register */ + __IO uint32_t MCMD; /*!< (@ 0x40003018) SPIFI memory command register */ + __IO uint32_t STAT; /*!< (@ 0x4000301C) SPIFI status register */ +} LPC_SPIFI_Type; + + +/* ================================================================================ */ +/* ================ SDMMC ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx SD/MMC Modification date=n/a Major revision=n/a Minor revision=n/a (SDMMC) + * @brief SD/MMC (SDMMC) */ -typedef struct { /*!< (@ 0x40004000) SDMMC Structure */ - __IO uint32_t CTRL; /*!< (@ 0x40004000) Control Register */ - __IO uint32_t PWREN; /*!< (@ 0x40004004) Power Enable Register */ - __IO uint32_t CLKDIV; /*!< (@ 0x40004008) Clock Divider Register */ - __IO uint32_t CLKSRC; /*!< (@ 0x4000400C) SD Clock Source Register */ - __IO uint32_t CLKENA; /*!< (@ 0x40004010) Clock Enable Register */ - __IO uint32_t TMOUT; /*!< (@ 0x40004014) Timeout Register */ - __IO uint32_t CTYPE; /*!< (@ 0x40004018) Card Type Register */ - __IO uint32_t BLKSIZ; /*!< (@ 0x4000401C) Block Size Register */ - __IO uint32_t BYTCNT; /*!< (@ 0x40004020) Byte Count Register */ - __IO uint32_t INTMASK; /*!< (@ 0x40004024) Interrupt Mask Register */ - __IO uint32_t CMDARG; /*!< (@ 0x40004028) Command Argument Register */ - __IO uint32_t CMD; /*!< (@ 0x4000402C) Command Register */ - __I uint32_t RESP0; /*!< (@ 0x40004030) Response Register 0 */ - __I uint32_t RESP1; /*!< (@ 0x40004034) Response Register 1 */ - __I uint32_t RESP2; /*!< (@ 0x40004038) Response Register 2 */ - __I uint32_t RESP3; /*!< (@ 0x4000403C) Response Register 3 */ - __I uint32_t MINTSTS; /*!< (@ 0x40004040) Masked Interrupt Status Register */ - __IO uint32_t RINTSTS; /*!< (@ 0x40004044) Raw Interrupt Status Register */ - __I uint32_t STATUS; /*!< (@ 0x40004048) Status Register */ - __IO uint32_t FIFOTH; /*!< (@ 0x4000404C) FIFO Threshold Watermark Register */ - __I uint32_t CDETECT; /*!< (@ 0x40004050) Card Detect Register */ - __I uint32_t WRTPRT; /*!< (@ 0x40004054) Write Protect Register */ - __IO uint32_t GPIO; /*!< (@ 0x40004058) General Purpose Input/Output Register */ - __I uint32_t TCBCNT; /*!< (@ 0x4000405C) Transferred CIU Card Byte Count Register */ - __I uint32_t TBBCNT; /*!< (@ 0x40004060) Transferred Host to BIU-FIFO Byte Count Register */ - __IO uint32_t DEBNCE; /*!< (@ 0x40004064) Debounce Count Register */ - __IO uint32_t USRID; /*!< (@ 0x40004068) User ID Register */ - __I uint32_t VERID; /*!< (@ 0x4000406C) Version ID Register */ +typedef struct { /*!< (@ 0x40004000) SDMMC Structure */ + __IO uint32_t CTRL; /*!< (@ 0x40004000) Control Register */ + __IO uint32_t PWREN; /*!< (@ 0x40004004) Power Enable Register */ + __IO uint32_t CLKDIV; /*!< (@ 0x40004008) Clock Divider Register */ + __IO uint32_t CLKSRC; /*!< (@ 0x4000400C) SD Clock Source Register */ + __IO uint32_t CLKENA; /*!< (@ 0x40004010) Clock Enable Register */ + __IO uint32_t TMOUT; /*!< (@ 0x40004014) Time-out Register */ + __IO uint32_t CTYPE; /*!< (@ 0x40004018) Card Type Register */ + __IO uint32_t BLKSIZ; /*!< (@ 0x4000401C) Block Size Register */ + __IO uint32_t BYTCNT; /*!< (@ 0x40004020) Byte Count Register */ + __IO uint32_t INTMASK; /*!< (@ 0x40004024) Interrupt Mask Register */ + __IO uint32_t CMDARG; /*!< (@ 0x40004028) Command Argument Register */ + __IO uint32_t CMD; /*!< (@ 0x4000402C) Command Register */ + __I uint32_t RESP0; /*!< (@ 0x40004030) Response Register 0 */ + __I uint32_t RESP1; /*!< (@ 0x40004034) Response Register 1 */ + __I uint32_t RESP2; /*!< (@ 0x40004038) Response Register 2 */ + __I uint32_t RESP3; /*!< (@ 0x4000403C) Response Register 3 */ + __I uint32_t MINTSTS; /*!< (@ 0x40004040) Masked Interrupt Status Register */ + __IO uint32_t RINTSTS; /*!< (@ 0x40004044) Raw Interrupt Status Register */ + __I uint32_t STATUS; /*!< (@ 0x40004048) Status Register */ + __IO uint32_t FIFOTH; /*!< (@ 0x4000404C) FIFO Threshold Watermark Register */ + __I uint32_t CDETECT; /*!< (@ 0x40004050) Card Detect Register */ + __I uint32_t WRTPRT; /*!< (@ 0x40004054) Write Protect Register */ __I uint32_t RESERVED0; - __IO uint32_t UHS_REG; /*!< (@ 0x40004074) UHS-1 Register */ - __IO uint32_t RST_N; /*!< (@ 0x40004078) Hardware Reset */ - __I uint32_t RESERVED1; - __IO uint32_t BMOD; /*!< (@ 0x40004080) Bus Mode Register */ - __O uint32_t PLDMND; /*!< (@ 0x40004084) Poll Demand Register */ - __IO uint32_t DBADDR; /*!< (@ 0x40004088) Descriptor List Base Address Register */ - __IO uint32_t IDSTS; /*!< (@ 0x4000408C) Internal DMAC Status Register */ - __IO uint32_t IDINTEN; /*!< (@ 0x40004090) Internal DMAC Interrupt Enable Register */ - __I uint32_t DSCADDR; /*!< (@ 0x40004094) Current Host Descriptor Address Register */ - __I uint32_t BUFADDR; /*!< (@ 0x40004098) Current Buffer Descriptor Address Register */ + __I uint32_t TCBCNT; /*!< (@ 0x4000405C) Transferred CIU Card Byte Count Register */ + __I uint32_t TBBCNT; /*!< (@ 0x40004060) Transferred Host to BIU-FIFO Byte Count Register */ + __IO uint32_t DEBNCE; /*!< (@ 0x40004064) Debounce Count Register */ + __I uint32_t RESERVED1[4]; + __IO uint32_t RST_N; /*!< (@ 0x40004078) Hardware Reset */ + __I uint32_t RESERVED2; + __IO uint32_t BMOD; /*!< (@ 0x40004080) Bus Mode Register */ + __O uint32_t PLDMND; /*!< (@ 0x40004084) Poll Demand Register */ + __IO uint32_t DBADDR; /*!< (@ 0x40004088) Descriptor List Base Address Register */ + __IO uint32_t IDSTS; /*!< (@ 0x4000408C) Internal DMAC Status Register */ + __IO uint32_t IDINTEN; /*!< (@ 0x40004090) Internal DMAC Interrupt Enable Register */ + __I uint32_t DSCADDR; /*!< (@ 0x40004094) Current Host Descriptor Address Register */ + __I uint32_t BUFADDR; /*!< (@ 0x40004098) Current Buffer Descriptor Address Register */ } LPC_SDMMC_Type; -// ------------------------------------------------------------------------------------------------ -// ----- EMC ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ EMC ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx External Memory Controller (EMC) Modification date=1/19/2011 Major revision=0 Minor revision=7 (EMC) + * @brief External Memory Controller (EMC) (EMC) */ -typedef struct { /*!< (@ 0x40005000) EMC Structure */ - __IO uint32_t CONTROL; /*!< (@ 0x40005000) Controls operation of the memory controller. */ - __I uint32_t STATUS; /*!< (@ 0x40005004) Provides EMC status information. */ - __IO uint32_t CONFIG; /*!< (@ 0x40005008) Configures operation of the memory controller. */ +typedef struct { /*!< (@ 0x40005000) EMC Structure */ + __IO uint32_t CONTROL; /*!< (@ 0x40005000) Controls operation of the memory controller. */ + __I uint32_t STATUS; /*!< (@ 0x40005004) Provides EMC status information. */ + __IO uint32_t CONFIG; /*!< (@ 0x40005008) Configures operation of the memory controller. */ __I uint32_t RESERVED0[5]; - __IO uint32_t DYNAMICCONTROL; /*!< (@ 0x40005020) Controls dynamic memory operation. */ - __IO uint32_t DYNAMICREFRESH; /*!< (@ 0x40005024) Configures dynamic memory refresh operation. */ - __IO uint32_t DYNAMICREADCONFIG; /*!< (@ 0x40005028) Configures the dynamic memory read strategy. */ + __IO uint32_t DYNAMICCONTROL; /*!< (@ 0x40005020) Controls dynamic memory operation. */ + __IO uint32_t DYNAMICREFRESH; /*!< (@ 0x40005024) Configures dynamic memory refresh operation. */ + __IO uint32_t DYNAMICREADCONFIG; /*!< (@ 0x40005028) Configures the dynamic memory read strategy. */ __I uint32_t RESERVED1; - __IO uint32_t DYNAMICRP; /*!< (@ 0x40005030) Selects the precharge command period. */ - __IO uint32_t DYNAMICRAS; /*!< (@ 0x40005034) Selects the active to precharge command period. */ - __IO uint32_t DYNAMICSREX; /*!< (@ 0x40005038) Selects the self-refresh exit time. */ - __IO uint32_t DYNAMICAPR; /*!< (@ 0x4000503C) Selects the last-data-out to active command time. */ - __IO uint32_t DYNAMICDAL; /*!< (@ 0x40005040) Selects the data-in to active command time. */ - __IO uint32_t DYNAMICWR; /*!< (@ 0x40005044) Selects the write recovery time. */ - __IO uint32_t DYNAMICRC; /*!< (@ 0x40005048) Selects the active to active command period. */ - __IO uint32_t DYNAMICRFC; /*!< (@ 0x4000504C) Selects the auto-refresh period. */ - __IO uint32_t DYNAMICXSR; /*!< (@ 0x40005050) Selects the exit self-refresh to active command time. */ - __IO uint32_t DYNAMICRRD; /*!< (@ 0x40005054) Selects the active bank A to active bank B latency. */ - __IO uint32_t DYNAMICMRD; /*!< (@ 0x40005058) Selects the load mode register to active command time. */ + __IO uint32_t DYNAMICRP; /*!< (@ 0x40005030) Selects the precharge command period. */ + __IO uint32_t DYNAMICRAS; /*!< (@ 0x40005034) Selects the active to precharge command period. */ + __IO uint32_t DYNAMICSREX; /*!< (@ 0x40005038) Selects the self-refresh exit time. */ + __IO uint32_t DYNAMICAPR; /*!< (@ 0x4000503C) Selects the last-data-out to active command time. */ + __IO uint32_t DYNAMICDAL; /*!< (@ 0x40005040) Selects the data-in to active command time. */ + __IO uint32_t DYNAMICWR; /*!< (@ 0x40005044) Selects the write recovery time. */ + __IO uint32_t DYNAMICRC; /*!< (@ 0x40005048) Selects the active to active command period. */ + __IO uint32_t DYNAMICRFC; /*!< (@ 0x4000504C) Selects the auto-refresh period. */ + __IO uint32_t DYNAMICXSR; /*!< (@ 0x40005050) Selects the exit self-refresh to active command + time. */ + __IO uint32_t DYNAMICRRD; /*!< (@ 0x40005054) Selects the active bank A to active bank B latency. */ + __IO uint32_t DYNAMICMRD; /*!< (@ 0x40005058) Selects the load mode register to active command + time. */ __I uint32_t RESERVED2[9]; - __IO uint32_t STATICEXTENDEDWAIT; /*!< (@ 0x40005080) Selects time for long static memory read and write transfers. */ + __IO uint32_t STATICEXTENDEDWAIT; /*!< (@ 0x40005080) Selects time for long static memory read and + write transfers. */ __I uint32_t RESERVED3[31]; - __IO uint32_t DYNAMICCONFIG0; /*!< (@ 0x40005100) Selects the configuration information for dynamic memory chip select n. */ - __IO uint32_t DYNAMICRASCAS0; /*!< (@ 0x40005104) Selects the RAS and CAS latencies for dynamic memory chip select n. */ + __IO uint32_t DYNAMICCONFIG0; /*!< (@ 0x40005100) Selects the configuration information for dynamic + memory chip select 0. */ + __IO uint32_t DYNAMICRASCAS0; /*!< (@ 0x40005104) Selects the RAS and CAS latencies for dynamic + memory chip select 0. */ __I uint32_t RESERVED4[6]; - __IO uint32_t DYNAMICCONFIG1; /*!< (@ 0x40005120) Selects the configuration information for dynamic memory chip select n. */ - __IO uint32_t DYNAMICRASCAS1; /*!< (@ 0x40005124) Selects the RAS and CAS latencies for dynamic memory chip select n. */ + __IO uint32_t DYNAMICCONFIG1; /*!< (@ 0x40005120) Selects the configuration information for dynamic + memory chip select 0. */ + __IO uint32_t DYNAMICRASCAS1; /*!< (@ 0x40005124) Selects the RAS and CAS latencies for dynamic + memory chip select 0. */ __I uint32_t RESERVED5[6]; - __IO uint32_t DYNAMICCONFIG2; /*!< (@ 0x40005140) Selects the configuration information for dynamic memory chip select n. */ - __IO uint32_t DYNAMICRASCAS2; /*!< (@ 0x40005144) Selects the RAS and CAS latencies for dynamic memory chip select n. */ + __IO uint32_t DYNAMICCONFIG2; /*!< (@ 0x40005140) Selects the configuration information for dynamic + memory chip select 0. */ + __IO uint32_t DYNAMICRASCAS2; /*!< (@ 0x40005144) Selects the RAS and CAS latencies for dynamic + memory chip select 0. */ __I uint32_t RESERVED6[6]; - __IO uint32_t DYNAMICCONFIG3; /*!< (@ 0x40005160) Selects the configuration information for dynamic memory chip select n. */ - __IO uint32_t DYNAMICRASCAS3; /*!< (@ 0x40005164) Selects the RAS and CAS latencies for dynamic memory chip select n. */ + __IO uint32_t DYNAMICCONFIG3; /*!< (@ 0x40005160) Selects the configuration information for dynamic + memory chip select 0. */ + __IO uint32_t DYNAMICRASCAS3; /*!< (@ 0x40005164) Selects the RAS and CAS latencies for dynamic + memory chip select 0. */ __I uint32_t RESERVED7[38]; - __IO uint32_t STATICCONFIG0; /*!< (@ 0x40005200) Selects the memory configuration for static chip select n. */ - __IO uint32_t STATICWAITWEN0; /*!< (@ 0x40005204) Selects the delay from chip select n to write enable. */ - __IO uint32_t STATICWAITOEN0; /*!< (@ 0x40005208) Selects the delay from chip select n or address change, whichever is later, to output enable. */ - __IO uint32_t STATICWAITRD0; /*!< (@ 0x4000520C) Selects the delay from chip select n to a read access. */ - __IO uint32_t STATICWAITPAG0; /*!< (@ 0x40005210) Selects the delay for asynchronous page mode sequential accesses for chip select n. */ - __IO uint32_t STATICWAITWR0; /*!< (@ 0x40005214) Selects the delay from chip select n to a write access. */ - __IO uint32_t STATICWAITTURN0; /*!< (@ 0x40005218) Selects bus turnaround cycles */ + __IO uint32_t STATICCONFIG0; /*!< (@ 0x40005200) Selects the memory configuration for static chip + select 0. */ + __IO uint32_t STATICWAITWEN0; /*!< (@ 0x40005204) Selects the delay from chip select 0 to write + enable. */ + __IO uint32_t STATICWAITOEN0; /*!< (@ 0x40005208) Selects the delay from chip select 0 or address + change, whichever is later, to output enable. */ + __IO uint32_t STATICWAITRD0; /*!< (@ 0x4000520C) Selects the delay from chip select 0 to a read + access. */ + __IO uint32_t STATICWAITPAGE0; /*!< (@ 0x40005210) Selects the delay for asynchronous page mode + sequential accesses for chip select 0. */ + __IO uint32_t STATICWAITWR0; /*!< (@ 0x40005214) Selects the delay from chip select 0 to a write + access. */ + __IO uint32_t STATICWAITTURN0; /*!< (@ 0x40005218) Selects the number of bus turnaround cycles for + chip select 0. */ __I uint32_t RESERVED8; - __IO uint32_t STATICCONFIG1; /*!< (@ 0x40005220) Selects the memory configuration for static chip select n. */ - __IO uint32_t STATICWAITWEN1; /*!< (@ 0x40005224) Selects the delay from chip select n to write enable. */ - __IO uint32_t STATICWAITOEN1; /*!< (@ 0x40005228) Selects the delay from chip select n or address change, whichever is later, to output enable. */ - __IO uint32_t STATICWAITRD1; /*!< (@ 0x4000522C) Selects the delay from chip select n to a read access. */ - __IO uint32_t STATICWAITPAG1; /*!< (@ 0x40005230) Selects the delay for asynchronous page mode sequential accesses for chip select n. */ - __IO uint32_t STATICWAITWR1; /*!< (@ 0x40005234) Selects the delay from chip select n to a write access. */ - __IO uint32_t STATICWAITTURN1; /*!< (@ 0x40005238) Selects bus turnaround cycles */ + __IO uint32_t STATICCONFIG1; /*!< (@ 0x40005220) Selects the memory configuration for static chip + select 0. */ + __IO uint32_t STATICWAITWEN1; /*!< (@ 0x40005224) Selects the delay from chip select 0 to write + enable. */ + __IO uint32_t STATICWAITOEN1; /*!< (@ 0x40005228) Selects the delay from chip select 0 or address + change, whichever is later, to output enable. */ + __IO uint32_t STATICWAITRD1; /*!< (@ 0x4000522C) Selects the delay from chip select 0 to a read + access. */ + __IO uint32_t STATICWAITPAGE1; /*!< (@ 0x40005230) Selects the delay for asynchronous page mode + sequential accesses for chip select 0. */ + __IO uint32_t STATICWAITWR1; /*!< (@ 0x40005234) Selects the delay from chip select 0 to a write + access. */ + __IO uint32_t STATICWAITTURN1; /*!< (@ 0x40005238) Selects the number of bus turnaround cycles for + chip select 0. */ __I uint32_t RESERVED9; - __IO uint32_t STATICCONFIG2; /*!< (@ 0x40005240) Selects the memory configuration for static chip select n. */ - __IO uint32_t STATICWAITWEN2; /*!< (@ 0x40005244) Selects the delay from chip select n to write enable. */ - __IO uint32_t STATICWAITOEN2; /*!< (@ 0x40005248) Selects the delay from chip select n or address change, whichever is later, to output enable. */ - __IO uint32_t STATICWAITRD2; /*!< (@ 0x4000524C) Selects the delay from chip select n to a read access. */ - __IO uint32_t STATICWAITPAG2; /*!< (@ 0x40005250) Selects the delay for asynchronous page mode sequential accesses for chip select n. */ - __IO uint32_t STATICWAITWR2; /*!< (@ 0x40005254) Selects the delay from chip select n to a write access. */ - __IO uint32_t STATICWAITTURN2; /*!< (@ 0x40005258) Selects bus turnaround cycles */ + __IO uint32_t STATICCONFIG2; /*!< (@ 0x40005240) Selects the memory configuration for static chip + select 0. */ + __IO uint32_t STATICWAITWEN2; /*!< (@ 0x40005244) Selects the delay from chip select 0 to write + enable. */ + __IO uint32_t STATICWAITOEN2; /*!< (@ 0x40005248) Selects the delay from chip select 0 or address + change, whichever is later, to output enable. */ + __IO uint32_t STATICWAITRD2; /*!< (@ 0x4000524C) Selects the delay from chip select 0 to a read + access. */ + __IO uint32_t STATICWAITPAGE2; /*!< (@ 0x40005250) Selects the delay for asynchronous page mode + sequential accesses for chip select 0. */ + __IO uint32_t STATICWAITWR2; /*!< (@ 0x40005254) Selects the delay from chip select 0 to a write + access. */ + __IO uint32_t STATICWAITTURN2; /*!< (@ 0x40005258) Selects the number of bus turnaround cycles for + chip select 0. */ __I uint32_t RESERVED10; - __IO uint32_t STATICCONFIG3; /*!< (@ 0x40005260) Selects the memory configuration for static chip select n. */ - __IO uint32_t STATICWAITWEN3; /*!< (@ 0x40005264) Selects the delay from chip select n to write enable. */ - __IO uint32_t STATICWAITOEN3; /*!< (@ 0x40005268) Selects the delay from chip select n or address change, whichever is later, to output enable. */ - __IO uint32_t STATICWAITRD3; /*!< (@ 0x4000526C) Selects the delay from chip select n to a read access. */ - __IO uint32_t STATICWAITPAG3; /*!< (@ 0x40005270) Selects the delay for asynchronous page mode sequential accesses for chip select n. */ - __IO uint32_t STATICWAITWR3; /*!< (@ 0x40005274) Selects the delay from chip select n to a write access. */ - __IO uint32_t STATICWAITTURN3; /*!< (@ 0x40005278) Selects bus turnaround cycles */ + __IO uint32_t STATICCONFIG3; /*!< (@ 0x40005260) Selects the memory configuration for static chip + select 0. */ + __IO uint32_t STATICWAITWEN3; /*!< (@ 0x40005264) Selects the delay from chip select 0 to write + enable. */ + __IO uint32_t STATICWAITOEN3; /*!< (@ 0x40005268) Selects the delay from chip select 0 or address + change, whichever is later, to output enable. */ + __IO uint32_t STATICWAITRD3; /*!< (@ 0x4000526C) Selects the delay from chip select 0 to a read + access. */ + __IO uint32_t STATICWAITPAGE3; /*!< (@ 0x40005270) Selects the delay for asynchronous page mode + sequential accesses for chip select 0. */ + __IO uint32_t STATICWAITWR3; /*!< (@ 0x40005274) Selects the delay from chip select 0 to a write + access. */ + __IO uint32_t STATICWAITTURN3; /*!< (@ 0x40005278) Selects the number of bus turnaround cycles for + chip select 0. */ } LPC_EMC_Type; -// ------------------------------------------------------------------------------------------------ -// ----- USB0 ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ USB0 ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx USB0 Host/Device/OTG controller Modification date=1/19/2011 Major revision=0 Minor revision=7 (USB0) + * @brief USB0 Host/Device/OTG controller (USB0) */ -typedef struct { /*!< (@ 0x40006000) USB0 Structure */ +typedef struct { /*!< (@ 0x40006000) USB0 Structure */ __I uint32_t RESERVED0[64]; - __I uint32_t CAPLENGTH; /*!< (@ 0x40006100) Capability register length */ - __I uint32_t HCSPARAMS; /*!< (@ 0x40006104) Host controller structural parameters */ - __I uint32_t HCCPARAMS; /*!< (@ 0x40006108) Host controller capability parameters */ + __I uint32_t CAPLENGTH; /*!< (@ 0x40006100) Capability register length */ + __I uint32_t HCSPARAMS; /*!< (@ 0x40006104) Host controller structural parameters */ + __I uint32_t HCCPARAMS; /*!< (@ 0x40006108) Host controller capability parameters */ __I uint32_t RESERVED1[5]; - __I uint32_t DCIVERSION; /*!< (@ 0x40006120) Device interface version number */ + __I uint32_t DCIVERSION; /*!< (@ 0x40006120) Device interface version number */ __I uint32_t RESERVED2[7]; - + union { - __IO uint32_t USBCMD_H; /*!< (@ 0x40006140) USB command (host mode) */ - __IO uint32_t USBCMD_D; /*!< (@ 0x40006140) USB command (device mode) */ - } ; - + __IO uint32_t USBCMD_H; /*!< (@ 0x40006140) USB command (host mode) */ + __IO uint32_t USBCMD_D; /*!< (@ 0x40006140) USB command (device mode) */ + }; + union { - __IO uint32_t USBSTS_H; /*!< (@ 0x40006144) USB status (host mode) */ - __IO uint32_t USBSTS_D; /*!< (@ 0x40006144) USB status (device mode) */ - } ; - + __IO uint32_t USBSTS_H; /*!< (@ 0x40006144) USB status (host mode) */ + __IO uint32_t USBSTS_D; /*!< (@ 0x40006144) USB status (device mode) */ + }; + union { - __IO uint32_t USBINTR_H; /*!< (@ 0x40006148) USB interrupt enable (host mode) */ - __IO uint32_t USBINTR_D; /*!< (@ 0x40006148) USB interrupt enable (device mode) */ - } ; - + __IO uint32_t USBINTR_H; /*!< (@ 0x40006148) USB interrupt enable (host mode) */ + __IO uint32_t USBINTR_D; /*!< (@ 0x40006148) USB interrupt enable (device mode) */ + }; + union { - __IO uint32_t FRINDEX_H; /*!< (@ 0x4000614C) USB frame index (host mode) */ - __IO uint32_t FRINDEX_D; /*!< (@ 0x4000614C) USB frame index (device mode) */ - } ; + __IO uint32_t FRINDEX_H; /*!< (@ 0x4000614C) USB frame index (host mode) */ + __IO uint32_t FRINDEX_D; /*!< (@ 0x4000614C) USB frame index (device mode) */ + }; __I uint32_t RESERVED3; - + union { - __IO uint32_t PERIODICLISTBASE; /*!< (@ 0x40006154) Frame list base address (host mode) */ - __IO uint32_t DEVICEADDR; /*!< (@ 0x40006154) USB device address (device mode) */ - } ; - + __IO uint32_t PERIODICLISTBASE; /*!< (@ 0x40006154) Frame list base address (host mode) */ + __IO uint32_t DEVICEADDR; /*!< (@ 0x40006154) USB device address (device mode) */ + }; + union { - __IO uint32_t ASYNCLISTADDR; /*!< (@ 0x40006158) Address of endpoint list in memory */ - __IO uint32_t ENDPOINTLISTADDR; /*!< (@ 0x40006158) Address of endpoint list in memory */ - } ; - __IO uint32_t TTCTRL; /*!< (@ 0x4000615C) Asynchronous buffer status for embedded TT (host mode) */ - __IO uint32_t BURSTSIZE; /*!< (@ 0x40006160) Programmable burst size */ - __IO uint32_t TXFILLTUNING; /*!< (@ 0x40006164) Host transmit pre-buffer packet tuning (host mode) */ + __IO uint32_t ASYNCLISTADDR; /*!< (@ 0x40006158) Address of endpoint list in memory */ + __IO uint32_t ENDPOINTLISTADDR; /*!< (@ 0x40006158) Address of endpoint list in memory */ + }; + __IO uint32_t TTCTRL; /*!< (@ 0x4000615C) Asynchronous buffer status for embedded TT (host + mode) */ + __IO uint32_t BURSTSIZE; /*!< (@ 0x40006160) Programmable burst size */ + __IO uint32_t TXFILLTUNING; /*!< (@ 0x40006164) Host transmit pre-buffer packet tuning (host + mode) */ __I uint32_t RESERVED4[3]; - __IO uint32_t BINTERVAL; /*!< (@ 0x40006174) Length of virtual frame */ - __IO uint32_t ENDPTNAK; /*!< (@ 0x40006178) Endpoint NAK (device mode) */ - __IO uint32_t ENDPTNAKEN; /*!< (@ 0x4000617C) Endpoint NAK Enable (device mode) */ + __IO uint32_t BINTERVAL; /*!< (@ 0x40006174) Length of virtual frame */ + __IO uint32_t ENDPTNAK; /*!< (@ 0x40006178) Endpoint NAK (device mode) */ + __IO uint32_t ENDPTNAKEN; /*!< (@ 0x4000617C) Endpoint NAK Enable (device mode) */ __I uint32_t RESERVED5; - + union { - __IO uint32_t PORTSC1_H; /*!< (@ 0x40006184) Port 1 status/control (host mode) */ - __IO uint32_t PORTSC1_D; /*!< (@ 0x40006184) Port 1 status/control (device mode) */ - } ; + __IO uint32_t PORTSC1_H; /*!< (@ 0x40006184) Port 1 status/control (host mode) */ + __IO uint32_t PORTSC1_D; /*!< (@ 0x40006184) Port 1 status/control (device mode) */ + }; __I uint32_t RESERVED6[7]; - __IO uint32_t OTGSC; /*!< (@ 0x400061A4) OTG status and control */ - + __IO uint32_t OTGSC; /*!< (@ 0x400061A4) OTG status and control */ + union { - __IO uint32_t USBMODE_H; /*!< (@ 0x400061A8) USB mode (host mode) */ - __IO uint32_t USBMODE_D; /*!< (@ 0x400061A8) USB device mode (device mode) */ - } ; - __IO uint32_t ENDPTSETUPSTAT; /*!< (@ 0x400061AC) Endpoint setup status */ - __IO uint32_t ENDPTPRIME; /*!< (@ 0x400061B0) Endpoint initialization */ - __IO uint32_t ENDPTFLUSH; /*!< (@ 0x400061B4) Endpoint de-initialization */ - __I uint32_t ENDPTSTAT; /*!< (@ 0x400061B8) Endpoint status */ - __IO uint32_t ENDPTCOMPLETE; /*!< (@ 0x400061BC) Endpoint complete */ - __IO uint32_t ENDPTCTRL0; /*!< (@ 0x400061C0) Endpoint control 0 */ - __IO uint32_t ENDPTCTRL1; /*!< (@ 0x400061C4) Endpoint control */ - __IO uint32_t ENDPTCTRL2; /*!< (@ 0x400061C8) Endpoint control */ - __IO uint32_t ENDPTCTRL3; /*!< (@ 0x400061CC) Endpoint control */ - __IO uint32_t ENDPTCTRL4; /*!< (@ 0x400061D0) Endpoint control */ - __IO uint32_t ENDPTCTRL5; /*!< (@ 0x400061D4) Endpoint control */ + __IO uint32_t USBMODE_H; /*!< (@ 0x400061A8) USB mode (host mode) */ + __IO uint32_t USBMODE_D; /*!< (@ 0x400061A8) USB device mode (device mode) */ + }; + __IO uint32_t ENDPTSETUPSTAT; /*!< (@ 0x400061AC) Endpoint setup status */ + __IO uint32_t ENDPTPRIME; /*!< (@ 0x400061B0) Endpoint initialization */ + __IO uint32_t ENDPTFLUSH; /*!< (@ 0x400061B4) Endpoint de-initialization */ + __I uint32_t ENDPTSTAT; /*!< (@ 0x400061B8) Endpoint status */ + __IO uint32_t ENDPTCOMPLETE; /*!< (@ 0x400061BC) Endpoint complete */ + __IO uint32_t ENDPTCTRL0; /*!< (@ 0x400061C0) Endpoint control 0 */ + __IO uint32_t ENDPTCTRL1; /*!< (@ 0x400061C4) Endpoint control */ + __IO uint32_t ENDPTCTRL2; /*!< (@ 0x400061C8) Endpoint control */ + __IO uint32_t ENDPTCTRL3; /*!< (@ 0x400061CC) Endpoint control */ + __IO uint32_t ENDPTCTRL4; /*!< (@ 0x400061D0) Endpoint control */ + __IO uint32_t ENDPTCTRL5; /*!< (@ 0x400061D4) Endpoint control */ } LPC_USB0_Type; -// ------------------------------------------------------------------------------------------------ -// ----- USB1 ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ USB1 ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx USB1 Host/Device controller Modification date=1/19/2011 Major revision=0 Minor revision=7 (USB1) + * @brief USB1 Host/Device controller (USB1) */ -typedef struct { /*!< (@ 0x40007000) USB1 Structure */ +typedef struct { /*!< (@ 0x40007000) USB1 Structure */ __I uint32_t RESERVED0[64]; - __I uint32_t CAPLENGTH; /*!< (@ 0x40007100) Capability register length */ - __I uint32_t HCSPARAMS; /*!< (@ 0x40007104) Host controller structural parameters */ - __I uint32_t HCCPARAMS; /*!< (@ 0x40007108) Host controller capability parameters */ + __I uint32_t CAPLENGTH; /*!< (@ 0x40007100) Capability register length */ + __I uint32_t HCSPARAMS; /*!< (@ 0x40007104) Host controller structural parameters */ + __I uint32_t HCCPARAMS; /*!< (@ 0x40007108) Host controller capability parameters */ __I uint32_t RESERVED1[5]; - __I uint32_t DCIVERSION; /*!< (@ 0x40007120) Device interface version number */ + __I uint32_t DCIVERSION; /*!< (@ 0x40007120) Device interface version number */ __I uint32_t RESERVED2[7]; - + union { - __IO uint32_t USBCMD_H; /*!< (@ 0x40007140) USB command (host mode) */ - __IO uint32_t USBCMD_D; /*!< (@ 0x40007140) USB command (device mode) */ - } ; - + __IO uint32_t USBCMD_H; /*!< (@ 0x40007140) USB command (host mode) */ + __IO uint32_t USBCMD_D; /*!< (@ 0x40007140) USB command (device mode) */ + }; + union { - __IO uint32_t USBSTS_H; /*!< (@ 0x40007144) USB status (host mode) */ - __IO uint32_t USBSTS_D; /*!< (@ 0x40007144) USB status (device mode) */ - } ; - + __IO uint32_t USBSTS_H; /*!< (@ 0x40007144) USB status (host mode) */ + __IO uint32_t USBSTS_D; /*!< (@ 0x40007144) USB status (device mode) */ + }; + union { - __IO uint32_t USBINTR_H; /*!< (@ 0x40007148) USB interrupt enable (host mode) */ - __IO uint32_t USBINTR_D; /*!< (@ 0x40007148) USB interrupt enable (device mode) */ - } ; - + __IO uint32_t USBINTR_H; /*!< (@ 0x40007148) USB interrupt enable (host mode) */ + __IO uint32_t USBINTR_D; /*!< (@ 0x40007148) USB interrupt enable (device mode) */ + }; + union { - __IO uint32_t FRINDEX_H; /*!< (@ 0x4000714C) USB frame index (host mode) */ - __I uint32_t FRINDEX_D; /*!< (@ 0x4000714C) USB frame index (device mode) */ - } ; + __IO uint32_t FRINDEX_H; /*!< (@ 0x4000714C) USB frame index (host mode) */ + __I uint32_t FRINDEX_D; /*!< (@ 0x4000714C) USB frame index (device mode) */ + }; __I uint32_t RESERVED3; - + union { - __IO uint32_t PERIODICLISTBASE; /*!< (@ 0x40007154) Frame list base address */ - __IO uint32_t DEVICEADDR; /*!< (@ 0x40007154) USB device address */ - } ; - + __IO uint32_t PERIODICLISTBASE; /*!< (@ 0x40007154) Frame list base address */ + __IO uint32_t DEVICEADDR; /*!< (@ 0x40007154) USB device address */ + }; + union { - __IO uint32_t ASYNCLISTADDR; /*!< (@ 0x40007158) Address of endpoint list in memory (host mode) */ - __IO uint32_t ENDPOINTLISTADDR; /*!< (@ 0x40007158) Address of endpoint list in memory (device mode) */ - } ; - __IO uint32_t TTCTRL; /*!< (@ 0x4000715C) Asynchronous buffer status for embedded TT (host mode) */ - __IO uint32_t BURSTSIZE; /*!< (@ 0x40007160) Programmable burst size */ - __IO uint32_t TXFILLTUNING; /*!< (@ 0x40007164) Host transmit pre-buffer packet tuning (host mode) */ + __IO uint32_t ASYNCLISTADDR; /*!< (@ 0x40007158) Address of endpoint list in memory (host mode) */ + __IO uint32_t ENDPOINTLISTADDR; /*!< (@ 0x40007158) Address of endpoint list in memory (device mode) */ + }; + __IO uint32_t TTCTRL; /*!< (@ 0x4000715C) Asynchronous buffer status for embedded TT (host + mode) */ + __IO uint32_t BURSTSIZE; /*!< (@ 0x40007160) Programmable burst size */ + __IO uint32_t TXFILLTUNING; /*!< (@ 0x40007164) Host transmit pre-buffer packet tuning (host + mode) */ __I uint32_t RESERVED4[2]; - __IO uint32_t ULPIVIEWPORT; /*!< (@ 0x40007170) ULPI viewport */ - __IO uint32_t BINTERVAL; /*!< (@ 0x40007174) Length of virtual frame */ - __IO uint32_t ENDPTNAK; /*!< (@ 0x40007178) Endpoint NAK (device mode) */ - __IO uint32_t ENDPTNAKEN; /*!< (@ 0x4000717C) Endpoint NAK Enable (device mode) */ + __IO uint32_t ULPIVIEWPORT; /*!< (@ 0x40007170) ULPI viewport */ + __IO uint32_t BINTERVAL; /*!< (@ 0x40007174) Length of virtual frame */ + __IO uint32_t ENDPTNAK; /*!< (@ 0x40007178) Endpoint NAK (device mode) */ + __IO uint32_t ENDPTNAKEN; /*!< (@ 0x4000717C) Endpoint NAK Enable (device mode) */ __I uint32_t RESERVED5; - + union { - __IO uint32_t PORTSC1_H; /*!< (@ 0x40007184) Port 1 status/control (host mode) */ - __IO uint32_t PORTSC1_D; /*!< (@ 0x40007184) Port 1 status/control (device mode) */ - } ; + __IO uint32_t PORTSC1_H; /*!< (@ 0x40007184) Port 1 status/control (host mode) */ + __IO uint32_t PORTSC1_D; /*!< (@ 0x40007184) Port 1 status/control (device mode) */ + }; __I uint32_t RESERVED6[8]; - + union { - __IO uint32_t USBMODE_H; /*!< (@ 0x400071A8) USB mode (host mode) */ - __IO uint32_t USBMODE_D; /*!< (@ 0x400071A8) USB mode (device mode) */ - } ; - __IO uint32_t ENDPTSETUPSTAT; /*!< (@ 0x400071AC) Endpoint setup status */ - __IO uint32_t ENDPTPRIME; /*!< (@ 0x400071B0) Endpoint initialization */ - __IO uint32_t ENDPTFLUSH; /*!< (@ 0x400071B4) Endpoint de-initialization */ - __I uint32_t ENDPTSTAT; /*!< (@ 0x400071B8) Endpoint status */ - __IO uint32_t ENDPTCOMPLETE; /*!< (@ 0x400071BC) Endpoint complete */ - __IO uint32_t ENDPTCTRL0; /*!< (@ 0x400071C0) Endpoint control 0 */ - __IO uint32_t ENDPTCTRL1; /*!< (@ 0x400071C4) Endpoint control */ - __IO uint32_t ENDPTCTRL2; /*!< (@ 0x400071C8) Endpoint control */ - __IO uint32_t ENDPTCTRL3; /*!< (@ 0x400071CC) Endpoint control */ + __IO uint32_t USBMODE_H; /*!< (@ 0x400071A8) USB mode (host mode) */ + __IO uint32_t USBMODE_D; /*!< (@ 0x400071A8) USB mode (device mode) */ + }; + __IO uint32_t ENDPTSETUPSTAT; /*!< (@ 0x400071AC) Endpoint setup status */ + __IO uint32_t ENDPTPRIME; /*!< (@ 0x400071B0) Endpoint initialization */ + __IO uint32_t ENDPTFLUSH; /*!< (@ 0x400071B4) Endpoint de-initialization */ + __I uint32_t ENDPTSTAT; /*!< (@ 0x400071B8) Endpoint status */ + __IO uint32_t ENDPTCOMPLETE; /*!< (@ 0x400071BC) Endpoint complete */ + __IO uint32_t ENDPTCTRL0; /*!< (@ 0x400071C0) Endpoint control 0 */ + __IO uint32_t ENDPTCTRL1; /*!< (@ 0x400071C4) Endpoint control */ + __IO uint32_t ENDPTCTRL2; /*!< (@ 0x400071C8) Endpoint control */ + __IO uint32_t ENDPTCTRL3; /*!< (@ 0x400071CC) Endpoint control */ } LPC_USB1_Type; -// ------------------------------------------------------------------------------------------------ -// ----- LCD ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ LCD ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx LCD Modification date=1/19/2011 Major revision=0 Minor revision=7 (LCD) + * @brief LCD controller (LCD) */ -typedef struct { /*!< (@ 0x40008000) LCD Structure */ - __IO uint32_t TIMH; /*!< (@ 0x40008000) Horizontal Timing Control register */ - __IO uint32_t TIMV; /*!< (@ 0x40008004) Vertical Timing Control register */ - __IO uint32_t POL; /*!< (@ 0x40008008) Clock and Signal Polarity Control register */ - __IO uint32_t LE; /*!< (@ 0x4000800C) Line End Control register */ - __IO uint32_t UPBASE; /*!< (@ 0x40008010) Upper Panel Frame Base Address register */ - __IO uint32_t LPBASE; /*!< (@ 0x40008014) Lower Panel Frame Base Address register */ - __IO uint32_t CTRL; /*!< (@ 0x40008018) LCD Control register */ - __IO uint32_t INTMSK; /*!< (@ 0x4000801C) Interrupt Mask register */ - __I uint32_t INTRAW; /*!< (@ 0x40008020) Raw Interrupt Status register */ - __I uint32_t INTSTAT; /*!< (@ 0x40008024) Masked Interrupt Status register */ - __O uint32_t INTCLR; /*!< (@ 0x40008028) Interrupt Clear register */ - __I uint32_t UPCURR; /*!< (@ 0x4000802C) Upper Panel Current Address Value register */ - __I uint32_t LPCURR; /*!< (@ 0x40008030) Lower Panel Current Address Value register */ +typedef struct { /*!< (@ 0x40008000) LCD Structure */ + __IO uint32_t TIMH; /*!< (@ 0x40008000) Horizontal Timing Control register */ + __IO uint32_t TIMV; /*!< (@ 0x40008004) Vertical Timing Control register */ + __IO uint32_t POL; /*!< (@ 0x40008008) Clock and Signal Polarity Control register */ + __IO uint32_t LE; /*!< (@ 0x4000800C) Line End Control register */ + __IO uint32_t UPBASE; /*!< (@ 0x40008010) Upper Panel Frame Base Address register */ + __IO uint32_t LPBASE; /*!< (@ 0x40008014) Lower Panel Frame Base Address register */ + __IO uint32_t CTRL; /*!< (@ 0x40008018) LCD Control register */ + __IO uint32_t INTMSK; /*!< (@ 0x4000801C) Interrupt Mask register */ + __I uint32_t INTRAW; /*!< (@ 0x40008020) Raw Interrupt Status register */ + __I uint32_t INTSTAT; /*!< (@ 0x40008024) Masked Interrupt Status register */ + __O uint32_t INTCLR; /*!< (@ 0x40008028) Interrupt Clear register */ + __I uint32_t UPCURR; /*!< (@ 0x4000802C) Upper Panel Current Address Value register */ + __I uint32_t LPCURR; /*!< (@ 0x40008030) Lower Panel Current Address Value register */ __I uint32_t RESERVED0[115]; - __IO uint32_t PAL[256]; /*!< (@ 0x40008200) 256x16-bit Color Palette registers */ + __IO uint32_t PAL[256]; /*!< (@ 0x40008200) 256x16-bit Color Palette registers */ __I uint32_t RESERVED1[128]; - __IO uint32_t CRSR_IMG[256]; /*!< (@ 0x40008800) Cursor Image registers */ - __IO uint32_t CRSR_CTRL; /*!< (@ 0x40008C00) Cursor Control register */ - __IO uint32_t CRSR_CFG; /*!< (@ 0x40008C04) Cursor Configuration register */ - __IO uint32_t CRSR_PAL0; /*!< (@ 0x40008C08) Cursor Palette register 0 */ - __IO uint32_t CRSR_PAL1; /*!< (@ 0x40008C0C) Cursor Palette register 1 */ - __IO uint32_t CRSR_XY; /*!< (@ 0x40008C10) Cursor XY Position register */ - __IO uint32_t CRSR_CLIP; /*!< (@ 0x40008C14) Cursor Clip Position register */ + __IO uint32_t CRSR_IMG[256]; /*!< (@ 0x40008800) Cursor Image registers */ + __IO uint32_t CRSR_CTRL; /*!< (@ 0x40008C00) Cursor Control register */ + __IO uint32_t CRSR_CFG; /*!< (@ 0x40008C04) Cursor Configuration register */ + __IO uint32_t CRSR_PAL0; /*!< (@ 0x40008C08) Cursor Palette register 0 */ + __IO uint32_t CRSR_PAL1; /*!< (@ 0x40008C0C) Cursor Palette register 1 */ + __IO uint32_t CRSR_XY; /*!< (@ 0x40008C10) Cursor XY Position register */ + __IO uint32_t CRSR_CLIP; /*!< (@ 0x40008C14) Cursor Clip Position register */ __I uint32_t RESERVED2[2]; - __IO uint32_t CRSR_INTMSK; /*!< (@ 0x40008C20) Cursor Interrupt Mask register */ - __O uint32_t CRSR_INTCLR; /*!< (@ 0x40008C24) Cursor Interrupt Clear register */ - __I uint32_t CRSR_INTRAW; /*!< (@ 0x40008C28) Cursor Raw Interrupt Status register */ - __I uint32_t CRSR_INTSTAT; /*!< (@ 0x40008C2C) Cursor Masked Interrupt Status register */ + __IO uint32_t CRSR_INTMSK; /*!< (@ 0x40008C20) Cursor Interrupt Mask register */ + __O uint32_t CRSR_INTCLR; /*!< (@ 0x40008C24) Cursor Interrupt Clear register */ + __I uint32_t CRSR_INTRAW; /*!< (@ 0x40008C28) Cursor Raw Interrupt Status register */ + __I uint32_t CRSR_INTSTAT; /*!< (@ 0x40008C2C) Cursor Masked Interrupt Status register */ } LPC_LCD_Type; -// ------------------------------------------------------------------------------------------------ -// ----- ETHERNET ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ EEPROM ================ */ +/* ================================================================================ */ + + +/** + * @brief EEPROM (EEPROM) + */ + +typedef struct { /*!< (@ 0x4000E000) EEPROM Structure */ + __IO uint32_t CMD; /*!< (@ 0x4000E000) EEPROM command register */ + __I uint32_t RESERVED0; + __IO uint32_t RWSTATE; /*!< (@ 0x4000E008) EEPROM read wait state register */ + __IO uint32_t AUTOPROG; /*!< (@ 0x4000E00C) EEPROM auto programming register */ + __IO uint32_t WSTATE; /*!< (@ 0x4000E010) EEPROM wait state register */ + __IO uint32_t CLKDIV; /*!< (@ 0x4000E014) EEPROM clock divider register */ + __IO uint32_t PWRDWN; /*!< (@ 0x4000E018) EEPROM power-down register */ + __I uint32_t RESERVED1[1007]; + __O uint32_t INTENCLR; /*!< (@ 0x4000EFD8) EEPROM interrupt enable clear */ + __O uint32_t INTENSET; /*!< (@ 0x4000EFDC) EEPROM interrupt enable set */ + __I uint32_t INTSTAT; /*!< (@ 0x4000EFE0) EEPROM interrupt status */ + __I uint32_t INTEN; /*!< (@ 0x4000EFE4) EEPROM interrupt enable */ + __O uint32_t INTSTATCLR; /*!< (@ 0x4000EFE8) EEPROM interrupt status clear */ +} LPC_EEPROM_Type; + + +/* ================================================================================ */ +/* ================ ETHERNET ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx Ethernet Modification date=12/9/2011 Major revision=1.1 Minor revision=not available (ETHERNET) + * @brief Ethernet (ETHERNET) */ -typedef struct { /*!< (@ 0x40010000) ETHERNET Structure */ - __IO uint32_t MAC_CONFIG; /*!< (@ 0x40010000) MAC configuration register */ - __IO uint32_t MAC_FRAME_FILTER; /*!< (@ 0x40010004) MAC frame filter */ - __IO uint32_t MAC_HASHTABLE_HIGH; /*!< (@ 0x40010008) Hash table high register */ - __IO uint32_t MAC_HASHTABLE_LOW; /*!< (@ 0x4001000C) Hash table low register */ - __IO uint32_t MAC_MII_ADDR; /*!< (@ 0x40010010) MII address register */ - __IO uint32_t MAC_MII_DATA; /*!< (@ 0x40010014) MII data register */ - __IO uint32_t MAC_FLOW_CTRL; /*!< (@ 0x40010018) Flow control register */ - __IO uint32_t MAC_VLAN_TAG; /*!< (@ 0x4001001C) VLAN tag register */ +typedef struct { /*!< (@ 0x40010000) ETHERNET Structure */ + __IO uint32_t MAC_CONFIG; /*!< (@ 0x40010000) MAC configuration register */ + __IO uint32_t MAC_FRAME_FILTER; /*!< (@ 0x40010004) MAC frame filter */ + __IO uint32_t MAC_HASHTABLE_HIGH; /*!< (@ 0x40010008) Hash table high register */ + __IO uint32_t MAC_HASHTABLE_LOW; /*!< (@ 0x4001000C) Hash table low register */ + __IO uint32_t MAC_MII_ADDR; /*!< (@ 0x40010010) MII address register */ + __IO uint32_t MAC_MII_DATA; /*!< (@ 0x40010014) MII data register */ + __IO uint32_t MAC_FLOW_CTRL; /*!< (@ 0x40010018) Flow control register */ + __IO uint32_t MAC_VLAN_TAG; /*!< (@ 0x4001001C) VLAN tag register */ __I uint32_t RESERVED0; - __I uint32_t MAC_DEBUG; /*!< (@ 0x40010024) Debug register */ - __IO uint32_t MAC_RWAKE_FRFLT; /*!< (@ 0x40010028) Remote wake-up frame filter */ - __IO uint32_t MAC_PMT_CTRL_STAT; /*!< (@ 0x4001002C) PMT control and status */ + __I uint32_t MAC_DEBUG; /*!< (@ 0x40010024) Debug register */ + __IO uint32_t MAC_RWAKE_FRFLT; /*!< (@ 0x40010028) Remote wake-up frame filter */ + __IO uint32_t MAC_PMT_CTRL_STAT; /*!< (@ 0x4001002C) PMT control and status */ __I uint32_t RESERVED1[2]; - __I uint32_t MAC_INTR; /*!< (@ 0x40010038) Interrupt status register */ - __IO uint32_t MAC_INTR_MASK; /*!< (@ 0x4001003C) Interrupt mask register */ - __IO uint32_t MAC_ADDR0_HIGH; /*!< (@ 0x40010040) MAC address 0 high register */ - __IO uint32_t MAC_ADDR0_LOW; /*!< (@ 0x40010044) MAC address 0 low register */ + __I uint32_t MAC_INTR; /*!< (@ 0x40010038) Interrupt status register */ + __IO uint32_t MAC_INTR_MASK; /*!< (@ 0x4001003C) Interrupt mask register */ + __IO uint32_t MAC_ADDR0_HIGH; /*!< (@ 0x40010040) MAC address 0 high register */ + __IO uint32_t MAC_ADDR0_LOW; /*!< (@ 0x40010044) MAC address 0 low register */ __I uint32_t RESERVED2[430]; - __IO uint32_t MAC_TIMESTP_CTRL; /*!< (@ 0x40010700) Time stamp control register */ - __IO uint32_t SUBSECOND_INCR; /*!< (@ 0x40010704) Sub-second increment register */ - __I uint32_t SECONDS; /*!< (@ 0x40010708) System time seconds register */ - __I uint32_t NANOSECONDS; /*!< (@ 0x4001070C) System time nanoseconds register */ - __IO uint32_t SECONDSUPDATE; /*!< (@ 0x40010710) System time seconds update register */ - __IO uint32_t NANOSECONDSUPDATE; /*!< (@ 0x40010714) System time nanoseconds update register */ - __IO uint32_t ADDEND; /*!< (@ 0x40010718) Time stamp addend register */ - __IO uint32_t TARGETSECONDS; /*!< (@ 0x4001071C) Target time seconds register */ - __IO uint32_t TARGETNANOSECONDS; /*!< (@ 0x40010720) Target time nanoseconds register */ - __IO uint32_t HIGHWORD; /*!< (@ 0x40010724) System time higher word seconds register */ - __I uint32_t TIMESTAMPSTAT; /*!< (@ 0x40010728) Time stamp status register */ - __IO uint32_t PPSCTRL; /*!< (@ 0x4001072C) PPS control register */ - __I uint32_t AUXNANOSECONDS; /*!< (@ 0x40010730) Auxiliary time stamp nanoseconds register */ - __I uint32_t AUXSECONDS; /*!< (@ 0x40010734) Auxiliary time stamp seconds register */ - __I uint32_t RESERVED3[562]; - __IO uint32_t DMA_BUS_MODE; /*!< (@ 0x40011000) Bus Mode Register */ - __IO uint32_t DMA_TRANS_POLL_DEMAND; /*!< (@ 0x40011004) Transmit poll demand register */ - __IO uint32_t DMA_REC_POLL_DEMAND; /*!< (@ 0x40011008) Receive poll demand register */ - __IO uint32_t DMA_REC_DES_ADDR; /*!< (@ 0x4001100C) Receive descriptor list address register */ - __IO uint32_t DMA_TRANS_DES_ADDR; /*!< (@ 0x40011010) Transmit descriptor list address register */ - __IO uint32_t DMA_STAT; /*!< (@ 0x40011014) Status register */ - __IO uint32_t DMA_OP_MODE; /*!< (@ 0x40011018) Operation mode register */ - __IO uint32_t DMA_INT_EN; /*!< (@ 0x4001101C) Interrupt enable register */ - __I uint32_t DMA_MFRM_BUFOF; /*!< (@ 0x40011020) Missed frame and buffer overflow register */ - __IO uint32_t DMA_REC_INT_WDT; /*!< (@ 0x40011024) Receive interrupt watchdog timer register */ + __IO uint32_t MAC_TIMESTP_CTRL; /*!< (@ 0x40010700) Time stamp control register */ + __IO uint32_t SUBSECOND_INCR; /*!< (@ 0x40010704) Sub-second increment register */ + __I uint32_t SECONDS; /*!< (@ 0x40010708) System time seconds register */ + __I uint32_t NANOSECONDS; /*!< (@ 0x4001070C) System time nanoseconds register */ + __IO uint32_t SECONDSUPDATE; /*!< (@ 0x40010710) System time seconds update register */ + __IO uint32_t NANOSECONDSUPDATE; /*!< (@ 0x40010714) System time nanoseconds update register */ + __IO uint32_t ADDEND; /*!< (@ 0x40010718) Time stamp addend register */ + __IO uint32_t TARGETSECONDS; /*!< (@ 0x4001071C) Target time seconds register */ + __IO uint32_t TARGETNANOSECONDS; /*!< (@ 0x40010720) Target time nanoseconds register */ + __IO uint32_t HIGHWORD; /*!< (@ 0x40010724) System time higher word seconds register */ + __I uint32_t TIMESTAMPSTAT; /*!< (@ 0x40010728) Time stamp status register */ + __I uint32_t RESERVED3[565]; + __IO uint32_t DMA_BUS_MODE; /*!< (@ 0x40011000) Bus Mode Register */ + __IO uint32_t DMA_TRANS_POLL_DEMAND; /*!< (@ 0x40011004) Transmit poll demand register */ + __IO uint32_t DMA_REC_POLL_DEMAND; /*!< (@ 0x40011008) Receive poll demand register */ + __IO uint32_t DMA_REC_DES_ADDR; /*!< (@ 0x4001100C) Receive descriptor list address register */ + __IO uint32_t DMA_TRANS_DES_ADDR; /*!< (@ 0x40011010) Transmit descriptor list address register */ + __IO uint32_t DMA_STAT; /*!< (@ 0x40011014) Status register */ + __IO uint32_t DMA_OP_MODE; /*!< (@ 0x40011018) Operation mode register */ + __IO uint32_t DMA_INT_EN; /*!< (@ 0x4001101C) Interrupt enable register */ + __I uint32_t DMA_MFRM_BUFOF; /*!< (@ 0x40011020) Missed frame and buffer overflow register */ + __IO uint32_t DMA_REC_INT_WDT; /*!< (@ 0x40011024) Receive interrupt watchdog timer register */ __I uint32_t RESERVED4[8]; - __I uint32_t DMA_CURHOST_TRANS_DES; /*!< (@ 0x40011048) Current host transmit descriptor register */ - __I uint32_t DMA_CURHOST_REC_DES; /*!< (@ 0x4001104C) Current host receive descriptor register */ - __I uint32_t DMA_CURHOST_TRANS_BUF; /*!< (@ 0x40011050) Current host transmit buffer address register */ - __I uint32_t DMA_CURHOST_REC_BUF; /*!< (@ 0x40011054) Current host receive buffer address register */ + __I uint32_t DMA_CURHOST_TRANS_DES; /*!< (@ 0x40011048) Current host transmit descriptor register */ + __I uint32_t DMA_CURHOST_REC_DES; /*!< (@ 0x4001104C) Current host receive descriptor register */ + __I uint32_t DMA_CURHOST_TRANS_BUF; /*!< (@ 0x40011050) Current host transmit buffer address register */ + __I uint32_t DMA_CURHOST_REC_BUF; /*!< (@ 0x40011054) Current host receive buffer address register */ } LPC_ETHERNET_Type; -// ------------------------------------------------------------------------------------------------ -// ----- ATIMER ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ ATIMER ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx Alarm timer Modification date=1/7/2011 Major revision=0 Minor revision=6 (ATIMER) + * @brief Alarm timer (ATIMER) */ -typedef struct { /*!< (@ 0x40040000) ATIMER Structure */ - __IO uint32_t DOWNCOUNTER; /*!< (@ 0x40040000) Downcounter register */ - __IO uint32_t PRESET; /*!< (@ 0x40040004) Preset value register */ +typedef struct { /*!< (@ 0x40040000) ATIMER Structure */ + __IO uint32_t DOWNCOUNTER; /*!< (@ 0x40040000) Downcounter register */ + __IO uint32_t PRESET; /*!< (@ 0x40040004) Preset value register */ __I uint32_t RESERVED0[1012]; - __O uint32_t CLR_EN; /*!< (@ 0x40040FD8) Interrupt clear enable register */ - __O uint32_t SET_EN; /*!< (@ 0x40040FDC) Interrupt set enable register */ - __I uint32_t STATUS; /*!< (@ 0x40040FE0) Status register */ - __I uint32_t ENABLE; /*!< (@ 0x40040FE4) Enable register */ - __O uint32_t CLR_STAT; /*!< (@ 0x40040FE8) Clear register */ - __O uint32_t SET_STAT; /*!< (@ 0x40040FEC) Set register */ + __O uint32_t CLR_EN; /*!< (@ 0x40040FD8) Interrupt clear enable register */ + __O uint32_t SET_EN; /*!< (@ 0x40040FDC) Interrupt set enable register */ + __I uint32_t STATUS; /*!< (@ 0x40040FE0) Status register */ + __I uint32_t ENABLE; /*!< (@ 0x40040FE4) Enable register */ + __O uint32_t CLR_STAT; /*!< (@ 0x40040FE8) Clear register */ + __O uint32_t SET_STAT; /*!< (@ 0x40040FEC) Set register */ } LPC_ATIMER_Type; -// ------------------------------------------------------------------------------------------------ -// ----- REGFILE ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ REGFILE ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx rtc/REGFILE date=1/20/2011 Major revision=0 Minor revision=7 (REGFILE) + * @brief RTC REGFILE (REGFILE) */ -typedef struct { /*!< (@ 0x40041000) REGFILE Structure */ - __IO uint32_t REGFILE[64]; /*!< (@ 0x40041000) General purpose storage register */ +typedef struct { /*!< (@ 0x40041000) REGFILE Structure */ + __IO uint32_t REGFILE[64]; /*!< (@ 0x40041000) General purpose storage register */ } LPC_REGFILE_Type; -// ------------------------------------------------------------------------------------------------ -// ----- PMC ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ PMC ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx Power Management Controller (PMC) Modification date=1/20/2011 Major revision=0 Minor revision=7 (PMC) + * @brief Power Management Controller (PMC) (PMC) */ -typedef struct { /*!< (@ 0x40042000) PMC Structure */ - __IO uint32_t PD0_SLEEP0_HW_ENA; /*!< (@ 0x40042000) Hardware sleep event enable register */ +typedef struct { /*!< (@ 0x40042000) PMC Structure */ + __IO uint32_t PD0_SLEEP0_HW_ENA; /*!< (@ 0x40042000) Hardware sleep event enable register */ __I uint32_t RESERVED0[6]; - __IO uint32_t PD0_SLEEP0_MODE; /*!< (@ 0x4004201C) Sleep power mode register */ + __IO uint32_t PD0_SLEEP0_MODE; /*!< (@ 0x4004201C) Sleep power mode register */ } LPC_PMC_Type; -// ------------------------------------------------------------------------------------------------ -// ----- CREG ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ CREG ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10503 Chapter title=LPC43xx Configuration Registers (CREG) Modification date=10/7/2011 Major revision=0 Minor revision=3 (CREG) + * @brief Configuration Registers (CREG) (CREG) */ -typedef struct { /*!< (@ 0x40043000) CREG Structure */ - __I uint32_t IRCTRM; /*!< (@ 0x40043000) IRC trim register */ - __IO uint32_t CREG0; /*!< (@ 0x40043004) Chip configuration register 32 kHz oscillator output and BOD control register. */ +typedef struct { /*!< (@ 0x40043000) CREG Structure */ + __I uint32_t RESERVED0; + __IO uint32_t CREG0; /*!< (@ 0x40043004) Chip configuration register 32 kHz oscillator + output and BOD control register. */ __I uint32_t RESERVED1[62]; - __IO uint32_t M4MEMMAP; /*!< (@ 0x40043100) ARM Cortex-M4 memory mapping */ + __IO uint32_t M4MEMMAP; /*!< (@ 0x40043100) ARM Cortex-M4 memory mapping */ __I uint32_t RESERVED2[5]; - __IO uint32_t CREG5; /*!< (@ 0x40043118) Chip configuration register 5. Controls JTAG access. */ - __IO uint32_t DMAMUX; /*!< (@ 0x4004311C) DMA muxing control */ - __I uint32_t RESERVED3[2]; - __IO uint32_t ETBCFG; /*!< (@ 0x40043128) ETB RAM configuration */ - __IO uint32_t CREG6; /*!< (@ 0x4004312C) Chip configuration register 6. */ - __IO uint32_t M4TXEVENT; /*!< (@ 0x40043130) Cortex-M4 TXEV event clear */ - __I uint32_t RESERVED4[51]; - __I uint32_t CHIPID; /*!< (@ 0x40043200) Part ID */ - __I uint32_t RESERVED5[127]; - __IO uint32_t M0TXEVENT; /*!< (@ 0x40043400) Cortex-M0 TXEV event clear */ - __IO uint32_t M0APPMEMMAP; /*!< (@ 0x40043404) ARM Cortex-M0 memory mapping */ + __IO uint32_t CREG5; /*!< (@ 0x40043118) Chip configuration register 5. Controls JTAG + access. */ + __IO uint32_t DMAMUX; /*!< (@ 0x4004311C) DMA mux control */ + __IO uint32_t FLASHCFGA; /*!< (@ 0x40043120) Flash accelerator configuration register for + flash bank A */ + __IO uint32_t FLASHCFGB; /*!< (@ 0x40043124) Flash accelerator configuration register for + flash bank B */ + __IO uint32_t ETBCFG; /*!< (@ 0x40043128) ETB RAM configuration */ + __IO uint32_t CREG6; /*!< (@ 0x4004312C) Chip configuration register 6. Controls multiple + functions : Ethernet interface, SCT output, I2S0/1 inputs, EMC + clock. */ + __IO uint32_t M4TXEVENT; /*!< (@ 0x40043130) Cortex-M4 TXEV event clear */ + __I uint32_t RESERVED3[51]; + __I uint32_t CHIPID; /*!< (@ 0x40043200) Part ID */ + __I uint32_t RESERVED4[65]; + __IO uint32_t M0SUBMEMMAP; /*!< (@ 0x40043308) ARM Cortex-M0SUB memory mapping */ + __I uint32_t RESERVED5[2]; + __IO uint32_t M0SUBTXEVENT; /*!< (@ 0x40043314) Cortex-M0SUB TXEV event clear */ + __I uint32_t RESERVED6[58]; + __IO uint32_t M0APPTXEVENT; /*!< (@ 0x40043400) Cortex-M0APP TXEV event clear */ + __IO uint32_t M0APPMEMMAP; /*!< (@ 0x40043404) ARM Cortex-M0APP memory mapping */ + __I uint32_t RESERVED7[62]; + __IO uint32_t USB0FLADJ; /*!< (@ 0x40043500) USB0 frame length adjust register */ + __I uint32_t RESERVED8[63]; + __IO uint32_t USB1FLADJ; /*!< (@ 0x40043600) USB1 frame length adjust register */ } LPC_CREG_Type; -// ------------------------------------------------------------------------------------------------ -// ----- EVENTROUTER ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ EVENTROUTER ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10503 Chapter title=LPC43xx Event router Modification date=10/7/2011 Major revision=0 Minor revision=3 (EVENTROUTER) + * @brief Event router (EVENTROUTER) */ -typedef struct { /*!< (@ 0x40044000) EVENTROUTER Structure */ - __IO uint32_t HILO; /*!< (@ 0x40044000) Level configuration register */ - __IO uint32_t EDGE; /*!< (@ 0x40044004) Edge configuration */ +typedef struct { /*!< (@ 0x40044000) EVENTROUTER Structure */ + __IO uint32_t HILO; /*!< (@ 0x40044000) Level configuration register */ + __IO uint32_t EDGE; /*!< (@ 0x40044004) Edge configuration */ __I uint32_t RESERVED0[1012]; - __O uint32_t CLR_EN; /*!< (@ 0x40044FD8) Clear event enable register */ - __O uint32_t SET_EN; /*!< (@ 0x40044FDC) Set event enable register */ - __I uint32_t STATUS; /*!< (@ 0x40044FE0) Event Status register */ - __I uint32_t ENABLE; /*!< (@ 0x40044FE4) Event Enable register */ - __O uint32_t CLR_STAT; /*!< (@ 0x40044FE8) Clear event status register */ - __O uint32_t SET_STAT; /*!< (@ 0x40044FEC) Set event status register */ + __O uint32_t CLR_EN; /*!< (@ 0x40044FD8) Clear event enable register */ + __O uint32_t SET_EN; /*!< (@ 0x40044FDC) Set event enable register */ + __I uint32_t STATUS; /*!< (@ 0x40044FE0) Event Status register */ + __I uint32_t ENABLE; /*!< (@ 0x40044FE4) Event Enable register */ + __O uint32_t CLR_STAT; /*!< (@ 0x40044FE8) Clear event status register */ + __O uint32_t SET_STAT; /*!< (@ 0x40044FEC) Set event status register */ } LPC_EVENTROUTER_Type; -// ------------------------------------------------------------------------------------------------ -// ----- RTC ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ RTC ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx Real-Time Clock (RTC) Modification date=1/20/2011 Major revision=0 Minor revision=7 (RTC) + * @brief Real-Time Clock (RTC) and event recorder (RTC) */ -typedef struct { /*!< (@ 0x40046000) RTC Structure */ - __O uint32_t ILR; /*!< (@ 0x40046000) Interrupt Location Register */ +typedef struct { /*!< (@ 0x40046000) RTC Structure */ + __O uint32_t ILR; /*!< (@ 0x40046000) Interrupt Location Register */ __I uint32_t RESERVED0; - __IO uint32_t CCR; /*!< (@ 0x40046008) Clock Control Register */ - __IO uint32_t CIIR; /*!< (@ 0x4004600C) Counter Increment Interrupt Register */ - __IO uint32_t AMR; /*!< (@ 0x40046010) Alarm Mask Register */ - __I uint32_t CTIME0; /*!< (@ 0x40046014) Consolidated Time Register 0 */ - __I uint32_t CTIME1; /*!< (@ 0x40046018) Consolidated Time Register 1 */ - __I uint32_t CTIME2; /*!< (@ 0x4004601C) Consolidated Time Register 2 */ - __IO uint32_t SEC; /*!< (@ 0x40046020) Seconds Register */ - __IO uint32_t MIN; /*!< (@ 0x40046024) Minutes Register */ - __IO uint32_t HRS; /*!< (@ 0x40046028) Hours Register */ - __IO uint32_t DOM; /*!< (@ 0x4004602C) Day of Month Register */ - __IO uint32_t DOW; /*!< (@ 0x40046030) Day of Week Register */ - __IO uint32_t DOY; /*!< (@ 0x40046034) Day of Year Register */ - __IO uint32_t MONTH; /*!< (@ 0x40046038) Months Register */ - __IO uint32_t YEAR; /*!< (@ 0x4004603C) Years Register */ - __IO uint32_t CALIBRATION; /*!< (@ 0x40046040) Calibration Value Register */ + __IO uint32_t CCR; /*!< (@ 0x40046008) Clock Control Register */ + __IO uint32_t CIIR; /*!< (@ 0x4004600C) Counter Increment Interrupt Register */ + __IO uint32_t AMR; /*!< (@ 0x40046010) Alarm Mask Register */ + __I uint32_t CTIME0; /*!< (@ 0x40046014) Consolidated Time Register 0 */ + __I uint32_t CTIME1; /*!< (@ 0x40046018) Consolidated Time Register 1 */ + __I uint32_t CTIME2; /*!< (@ 0x4004601C) Consolidated Time Register 2 */ + __IO uint32_t SEC; /*!< (@ 0x40046020) Seconds Register */ + __IO uint32_t MIN; /*!< (@ 0x40046024) Minutes Register */ + __IO uint32_t HRS; /*!< (@ 0x40046028) Hours Register */ + __IO uint32_t DOM; /*!< (@ 0x4004602C) Day of Month Register */ + __IO uint32_t DOW; /*!< (@ 0x40046030) Day of Week Register */ + __IO uint32_t DOY; /*!< (@ 0x40046034) Day of Year Register */ + __IO uint32_t MONTH; /*!< (@ 0x40046038) Months Register */ + __IO uint32_t YEAR; /*!< (@ 0x4004603C) Years Register */ + __IO uint32_t CALIBRATION; /*!< (@ 0x40046040) Calibration Value Register */ __I uint32_t RESERVED1[7]; - __IO uint32_t ASEC; /*!< (@ 0x40046060) Alarm value for Seconds */ - __IO uint32_t AMIN; /*!< (@ 0x40046064) Alarm value for Minutes */ - __IO uint32_t AHRS; /*!< (@ 0x40046068) Alarm value for Hours */ - __IO uint32_t ADOM; /*!< (@ 0x4004606C) Alarm value for Day of Month */ - __IO uint32_t ADOW; /*!< (@ 0x40046070) Alarm value for Day of Week */ - __IO uint32_t ADOY; /*!< (@ 0x40046074) Alarm value for Day of Year */ - __IO uint32_t AMON; /*!< (@ 0x40046078) Alarm value for Months */ - __IO uint32_t AYRS; /*!< (@ 0x4004607C) Alarm value for Year */ + __IO uint32_t ASEC; /*!< (@ 0x40046060) Alarm value for Seconds */ + __IO uint32_t AMIN; /*!< (@ 0x40046064) Alarm value for Minutes */ + __IO uint32_t AHRS; /*!< (@ 0x40046068) Alarm value for Hours */ + __IO uint32_t ADOM; /*!< (@ 0x4004606C) Alarm value for Day of Month */ + __IO uint32_t ADOW; /*!< (@ 0x40046070) Alarm value for Day of Week */ + __IO uint32_t ADOY; /*!< (@ 0x40046074) Alarm value for Day of Year */ + __IO uint32_t AMON; /*!< (@ 0x40046078) Alarm value for Months */ + __IO uint32_t AYRS; /*!< (@ 0x4004607C) Alarm value for Year */ + __IO uint32_t ERSTATUS; /*!< (@ 0x40046080) Event Monitor/Recorder Status register. Contains + status flags for event channels and other Event Monitor/Recorder + conditions. */ + __IO uint32_t ERCONTRO; /*!< (@ 0x40046084) Event Monitor/Recorder Control register. Contains + bits that control actions for the event channels as well as + for Event Monitor/Recorder setup. */ + __I uint32_t ERCOUNTERS; /*!< (@ 0x40046088) Event Monitor/Recorder Counters register. Allows + reading the counters associated with the event channels. */ + __I uint32_t RESERVED2; + __I uint32_t ERFIRSTSTAMP0; /*!< (@ 0x40046090) Event Monitor/Recorder First Stamp register for + channel 0. Retains the time stamp for the first event on channel + 0. */ + __I uint32_t ERFIRSTSTAMP1; /*!< (@ 0x40046094) Event Monitor/Recorder First Stamp register for + channel 0. Retains the time stamp for the first event on channel + 0. */ + __I uint32_t ERFIRSTSTAMP2; /*!< (@ 0x40046098) Event Monitor/Recorder First Stamp register for + channel 0. Retains the time stamp for the first event on channel + 0. */ + __I uint32_t RESERVED3; + __I uint32_t ERLASTSTAMP0; /*!< (@ 0x400460A0) Event Monitor/Recorder Last Stamp register for + channel 0. Retains the time stamp for the last (i.e. most recent) + event on channel 0. */ + __I uint32_t ERLASTSTAMP1; /*!< (@ 0x400460A4) Event Monitor/Recorder Last Stamp register for + channel 0. Retains the time stamp for the last (i.e. most recent) + event on channel 0. */ + __I uint32_t ERLASTSTAMP2; /*!< (@ 0x400460A8) Event Monitor/Recorder Last Stamp register for + channel 0. Retains the time stamp for the last (i.e. most recent) + event on channel 0. */ } LPC_RTC_Type; -// ------------------------------------------------------------------------------------------------ -// ----- CGU ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ CGU ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10462 Chapter title=LPC18xx Clock Generation Unit (CGU) Modification date=6/1/2011 Major revision=0 Minor revision=1 (CGU) + * @brief Clock Generation Unit (CGU) (CGU) */ -typedef struct { /*!< (@ 0x40050000) CGU Structure */ +typedef struct { /*!< (@ 0x40050000) CGU Structure */ __I uint32_t RESERVED0[5]; - __IO uint32_t FREQ_MON; /*!< (@ 0x40050014) Frequency monitor register */ - __IO uint32_t XTAL_OSC_CTRL; /*!< (@ 0x40050018) Crystal oscillator control register */ - __I uint32_t PLL0USB_STAT; /*!< (@ 0x4005001C) PLL0 (USB) status register */ - __IO uint32_t PLL0USB_CTRL; /*!< (@ 0x40050020) PLL0 (USB) control register */ - __IO uint32_t PLL0USB_MDIV; /*!< (@ 0x40050024) PLL0 (USB) M-divider register */ - __IO uint32_t PLL0USB_NP_DIV; /*!< (@ 0x40050028) PLL0 (USB) N/P-divider register */ - __I uint32_t PLL0AUDIO_STAT; /*!< (@ 0x4005002C) PLL0 (audio) status register */ - __IO uint32_t PLL0AUDIO_CTRL; /*!< (@ 0x40050030) PLL0 (audio) control register */ - __IO uint32_t PLL0AUDIO_MDIV; /*!< (@ 0x40050034) PLL0 (audio) M-divider register */ - __IO uint32_t PLL0AUDIO_NP_DIV; /*!< (@ 0x40050038) PLL0 (audio) N/P-divider register */ - __IO uint32_t PLL0AUDIO_FRAC; /*!< (@ 0x4005003C) PLL0 (audio) */ - __I uint32_t PLL1_STAT; /*!< (@ 0x40050040) PLL1 status register */ - __IO uint32_t PLL1_CTRL; /*!< (@ 0x40050044) PLL1 control register */ - __IO uint32_t IDIVA_CTRL; /*!< (@ 0x40050048) Integer divider A control register */ - __IO uint32_t IDIVB_CTRL; /*!< (@ 0x4005004C) Integer divider B control register */ - __IO uint32_t IDIVC_CTRL; /*!< (@ 0x40050050) Integer divider C control register */ - __IO uint32_t IDIVD_CTRL; /*!< (@ 0x40050054) Integer divider D control register */ - __IO uint32_t IDIVE_CTRL; /*!< (@ 0x40050058) Integer divider E control register */ - __IO uint32_t BASE_SAFE_CLK; /*!< (@ 0x4005005C) Output stage 0 control register for base clock BASE_SAFE_CLK */ - __IO uint32_t BASE_USB0_CLK; /*!< (@ 0x40050060) Output stage 1 control register for base clock BASE_USB0_CLK */ - __IO uint32_t BASE_PERIPH_CLK; /*!< (@ 0x40050064) Output stage 2 control register for base clock BASE_PERIPH_CLK */ - __IO uint32_t BASE_USB1_CLK; /*!< (@ 0x40050068) Output stage 3 control register for base clock BASE_USB1_CLK */ - __IO uint32_t BASE_M4_CLK; /*!< (@ 0x4005006C) Output stage BASE_M4_CLK control register */ - __IO uint32_t BASE_SPIFI_CLK; /*!< (@ 0x40050070) Output stage BASE_SPIFI_CLK control register */ - __IO uint32_t BASE_SPI_CLK; /*!< (@ 0x40050074) Output stage BASE_SPI_CLK control register */ - __IO uint32_t BASE_PHY_RX_CLK; /*!< (@ 0x40050078) Output stage BASE_PHY_RX_CLK control register */ - __IO uint32_t BASE_PHY_TX_CLK; /*!< (@ 0x4005007C) Output stage BASE_PHY_TX_CLK control register */ - __IO uint32_t BASE_APB1_CLK; /*!< (@ 0x40050080) Output stage BASE_APB1_CLK control register */ - __IO uint32_t BASE_APB3_CLK; /*!< (@ 0x40050084) Output stage BASE_APB3_CLK control register */ - __IO uint32_t BASE_LCD_CLK; /*!< (@ 0x40050088) Output stage BASE_LCD_CLK control register */ - __IO uint32_t BASE_VADC_CLK; /*!< (@ 0x4005008C) Output stage BASE_VADC_CLK control register */ - __IO uint32_t BASE_SDIO_CLK; /*!< (@ 0x40050090) Output stage BASE_SDIO_CLK control register */ - __IO uint32_t BASE_SSP0_CLK; /*!< (@ 0x40050094) Output stage BASE_SSP0_CLK control register */ - __IO uint32_t BASE_SSP1_CLK; /*!< (@ 0x40050098) Output stage BASE_SSP1_CLK control register */ - __IO uint32_t BASE_UART0_CLK; /*!< (@ 0x4005009C) Output stage BASE_UART0_CLK control register */ - __IO uint32_t BASE_UART1_CLK; /*!< (@ 0x400500A0) Output stage BASE_UART1_CLK control register */ - __IO uint32_t BASE_UART2_CLK; /*!< (@ 0x400500A4) Output stage BASE_UART2_CLK control register */ - __IO uint32_t BASE_UART3_CLK; /*!< (@ 0x400500A8) Output stage BASE_UART3_CLK control register */ - __IO uint32_t BASE_OUT_CLK; /*!< (@ 0x400500AC) Output stage 20 control register for base clock BASE_OUT_CLK */ - __I uint32_t RESERVED3[4]; - __IO uint32_t BASE_APLL_CLK; /*!< (@ 0x400500C0) Output stage 25 control register for base clock BASE_APLL_CLK */ - __IO uint32_t BASE_CGU_OUT0_CLK; /*!< (@ 0x400500C4) Output stage 25 control register for base clock BASE_CGU_OUT0_CLK */ - __IO uint32_t BASE_CGU_OUT1_CLK; /*!< (@ 0x400500C8) Output stage 25 control register for base clock BASE_CGU_OUT1_CLK */ + __IO uint32_t FREQ_MON; /*!< (@ 0x40050014) Frequency monitor register */ + __IO uint32_t XTAL_OSC_CTRL; /*!< (@ 0x40050018) Crystal oscillator control register */ + __I uint32_t PLL0USB_STAT; /*!< (@ 0x4005001C) PLL0USB status register */ + __IO uint32_t PLL0USB_CTRL; /*!< (@ 0x40050020) PLL0USB control register */ + __IO uint32_t PLL0USB_MDIV; /*!< (@ 0x40050024) PLL0USB M-divider register */ + __IO uint32_t PLL0USB_NP_DIV; /*!< (@ 0x40050028) PLL0USB N/P-divider register */ + __I uint32_t PLL0AUDIO_STAT; /*!< (@ 0x4005002C) PLL0AUDIO status register */ + __IO uint32_t PLL0AUDIO_CTRL; /*!< (@ 0x40050030) PLL0AUDIO control register */ + __IO uint32_t PLL0AUDIO_MDIV; /*!< (@ 0x40050034) PLL0AUDIO M-divider register */ + __IO uint32_t PLL0AUDIO_NP_DIV; /*!< (@ 0x40050038) PLL0AUDIO N/P-divider register */ + __IO uint32_t PLL0AUDIO_FRAC; /*!< (@ 0x4005003C) PLL0AUDIO fractional divider register */ + __I uint32_t PLL1_STAT; /*!< (@ 0x40050040) PLL1 status register */ + __IO uint32_t PLL1_CTRL; /*!< (@ 0x40050044) PLL1 control register */ + __IO uint32_t IDIVA_CTRL; /*!< (@ 0x40050048) Integer divider A control register */ + __IO uint32_t IDIVB_CTRL; /*!< (@ 0x4005004C) Integer divider B control register */ + __IO uint32_t IDIVC_CTRL; /*!< (@ 0x40050050) Integer divider C control register */ + __IO uint32_t IDIVD_CTRL; /*!< (@ 0x40050054) Integer divider D control register */ + __IO uint32_t IDIVE_CTRL; /*!< (@ 0x40050058) Integer divider E control register */ + __I uint32_t BASE_SAFE_CLK; /*!< (@ 0x4005005C) Output stage 0 control register for base clock + BASE_SAFE_CLK */ + __IO uint32_t BASE_USB0_CLK; /*!< (@ 0x40050060) Output stage 1 control register for base clock + BASE_USB0_CLK */ + __IO uint32_t BASE_PERIPH_CLK; /*!< (@ 0x40050064) Output stage 2 control register for base clock + BASE_PERIPH_CLK */ + __IO uint32_t BASE_USB1_CLK; /*!< (@ 0x40050068) Output stage 3 control register for base clock + BASE_USB1_CLK */ + __IO uint32_t BASE_M4_CLK; /*!< (@ 0x4005006C) Output stage BASE_M4_CLK control register */ + __IO uint32_t BASE_SPIFI_CLK; /*!< (@ 0x40050070) Output stage BASE_SPIFI_CLK control register */ + __IO uint32_t BASE_SPI_CLK; /*!< (@ 0x40050074) Output stage BASE_SPI_CLK control register */ + __IO uint32_t BASE_PHY_RX_CLK; /*!< (@ 0x40050078) Output stage BASE_PHY_RX_CLK control register */ + __IO uint32_t BASE_PHY_TX_CLK; /*!< (@ 0x4005007C) Output stage BASE_PHY_TX_CLK control register */ + __IO uint32_t BASE_APB1_CLK; /*!< (@ 0x40050080) Output stage BASE_APB1_CLK control register */ + __IO uint32_t BASE_APB3_CLK; /*!< (@ 0x40050084) Output stage BASE_APB3_CLK control register */ + __IO uint32_t BASE_LCD_CLK; /*!< (@ 0x40050088) Output stage BASE_LCD_CLK control register */ + __I uint32_t RESERVED1; + __IO uint32_t BASE_SDIO_CLK; /*!< (@ 0x40050090) Output stage BASE_SDIO_CLK control register */ + __IO uint32_t BASE_SSP0_CLK; /*!< (@ 0x40050094) Output stage BASE_SSP0_CLK control register */ + __IO uint32_t BASE_SSP1_CLK; /*!< (@ 0x40050098) Output stage BASE_SSP1_CLK control register */ + __IO uint32_t BASE_UART0_CLK; /*!< (@ 0x4005009C) Output stage BASE_UART0_CLK control register */ + __IO uint32_t BASE_UART1_CLK; /*!< (@ 0x400500A0) Output stage BASE_UART1_CLK control register */ + __IO uint32_t BASE_UART2_CLK; /*!< (@ 0x400500A4) Output stage BASE_UART2_CLK control register */ + __IO uint32_t BASE_UART3_CLK; /*!< (@ 0x400500A8) Output stage BASE_UART3_CLK control register */ + __IO uint32_t BASE_OUT_CLK; /*!< (@ 0x400500AC) Output stage 20 control register for base clock + BASE_OUT_CLK */ + __I uint32_t RESERVED2[4]; + __IO uint32_t BASE_APLL_CLK; /*!< (@ 0x400500C0) Output stage 25 control register for base clock + BASE_APLL_CLK */ + __IO uint32_t BASE_CGU_OUT0_CLK; /*!< (@ 0x400500C4) Output stage 25 control register for base clock + BASE_CGU_OUT0_CLK */ + __IO uint32_t BASE_CGU_OUT1_CLK; /*!< (@ 0x400500C8) Output stage 25 control register for base clock + BASE_CGU_OUT1_CLK */ } LPC_CGU_Type; -// ------------------------------------------------------------------------------------------------ -// ----- CCU1 ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ CCU1 ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC43xx Clock Control Unit (CCU) (CCU1) + * @brief Clock Control Unit (CCU) (CCU1) */ -typedef struct { /*!< (@ 0x40051000) CCU1 Structure */ - __IO uint32_t PM; /*!< (@ 0x40051000) CCU1 power mode register */ - __I uint32_t BASE_STAT; /*!< (@ 0x40051004) CCU1 base clocks status register */ +typedef struct { /*!< (@ 0x40051000) CCU1 Structure */ + __IO uint32_t PM; /*!< (@ 0x40051000) CCU1 power mode register */ + __I uint32_t BASE_STAT; /*!< (@ 0x40051004) CCU1 base clocks status register */ __I uint32_t RESERVED0[62]; - __IO uint32_t CLK_APB3_BUS_CFG; /*!< (@ 0x40051100) CLK_APB3_BUS clock configuration register */ - __I uint32_t CLK_APB3_BUS_STAT; /*!< (@ 0x40051104) CLK_APB3_BUS clock status register */ - __IO uint32_t CLK_APB3_I2C1_CFG; /*!< (@ 0x40051108) CLK_APB3_I2C1 clock configuration register */ - __I uint32_t CLK_APB3_I2C1_STAT; /*!< (@ 0x4005110C) CLK_APB3_I2C1 clock status register */ - __IO uint32_t CLK_APB3_DAC_CFG; /*!< (@ 0x40051110) CLK_APB3_DAC clock configuration register */ - __I uint32_t CLK_APB3_DAC_STAT; /*!< (@ 0x40051114) CLK_APB3_DAC clock status register */ - __IO uint32_t CLK_APB3_ADC0_CFG; /*!< (@ 0x40051118) CLK_APB3_ADC0 clock configuration register */ - __I uint32_t CLK_APB3_ADC0_STAT; /*!< (@ 0x4005111C) CLK_APB3_ADC0 clock status register */ - __IO uint32_t CLK_APB3_ADC1_CFG; /*!< (@ 0x40051120) CLK_APB3_ADC1 clock configuration register */ - __I uint32_t CLK_APB3_ADC1_STAT; /*!< (@ 0x40051124) CLK_APB3_ADC1 clock status register */ - __IO uint32_t CLK_APB3_CAN0_CFG; /*!< (@ 0x40051128) CLK_APB3_CAN0 clock configuration register */ - __I uint32_t CLK_APB3_CAN0_STAT; /*!< (@ 0x4005112C) CLK_APB3_CAN0 clock status register */ + __IO uint32_t CLK_APB3_BUS_CFG; /*!< (@ 0x40051100) CLK_APB3_BUS clock configuration register */ + __I uint32_t CLK_APB3_BUS_STAT; /*!< (@ 0x40051104) CLK_APB3_BUS clock status register */ + __IO uint32_t CLK_APB3_I2C1_CFG; /*!< (@ 0x40051108) CLK_APB3_I2C1 clock configuration register */ + __I uint32_t CLK_APB3_I2C1_STAT; /*!< (@ 0x4005110C) CLK_APB3_I2C1 clock status register */ + __IO uint32_t CLK_APB3_DAC_CFG; /*!< (@ 0x40051110) CLK_APB3_DAC clock configuration register */ + __I uint32_t CLK_APB3_DAC_STAT; /*!< (@ 0x40051114) CLK_APB3_DAC clock status register */ + __IO uint32_t CLK_APB3_ADC0_CFG; /*!< (@ 0x40051118) CLK_APB3_ADC0 clock configuration register */ + __I uint32_t CLK_APB3_ADC0_STAT; /*!< (@ 0x4005111C) CLK_APB3_ADC0 clock status register */ + __IO uint32_t CLK_APB3_ADC1_CFG; /*!< (@ 0x40051120) CLK_APB3_ADC1 clock configuration register */ + __I uint32_t CLK_APB3_ADC1_STAT; /*!< (@ 0x40051124) CLK_APB3_ADC1 clock status register */ + __IO uint32_t CLK_APB3_CAN0_CFG; /*!< (@ 0x40051128) CLK_APB3_CAN0 clock configuration register */ + __I uint32_t CLK_APB3_CAN0_STAT; /*!< (@ 0x4005112C) CLK_APB3_CAN0 clock status register */ __I uint32_t RESERVED1[52]; - __IO uint32_t CLK_APB1_BUS_CFG; /*!< (@ 0x40051200) CLK_APB1_BUS clock configuration register */ - __I uint32_t CLK_APB1_BUS_STAT; /*!< (@ 0x40051204) CLK_APB1_BUS clock status register */ - __IO uint32_t CLK_APB1_MOTOCONPWM_CFG; /*!< (@ 0x40051208) CLK_APB1_MOTOCONPWM clock configuration register */ - __I uint32_t CLK_APB1_MOTOCONPWM_STAT; /*!< (@ 0x4005120C) CLK_APB1_MOTOCONPWM clock status register */ - __IO uint32_t CLK_ABP1_I2C0_CFG; /*!< (@ 0x40051210) CLK_ABP1_I2C0 clock configuration register */ - __I uint32_t CLK_APB1_I2C0_STAT; /*!< (@ 0x40051214) CLK_APB1_I2C0 clock status register */ - __IO uint32_t CLK_APB1_I2S_CFG; /*!< (@ 0x40051218) CLK_APB1_I2S clock configuration register */ - __I uint32_t CLK_APB1_I2S_STAT; /*!< (@ 0x4005121C) CLK_APB1_I2S clock status register */ - __IO uint32_t CLK_APB1_CAN1_CFG; /*!< (@ 0x40051220) CLK_APB1_CAN1 clock configuration register */ - __I uint32_t CLK_APB1_CAN1_STAT; /*!< (@ 0x40051224) CLK_APB1_CAN1 clock status register */ + __IO uint32_t CLK_APB1_BUS_CFG; /*!< (@ 0x40051200) CLK_APB1_BUS clock configuration register */ + __I uint32_t CLK_APB1_BUS_STAT; /*!< (@ 0x40051204) CLK_APB1_BUS clock status register */ + __IO uint32_t CLK_APB1_MOTOCONPWM_CFG; /*!< (@ 0x40051208) CLK_APB1_MOTOCONPWM clock configuration register */ + __I uint32_t CLK_APB1_MOTOCONPWM_STAT; /*!< (@ 0x4005120C) CLK_APB1_MOTOCONPWM clock status register */ + __IO uint32_t CLK_APB1_I2C0_CFG; /*!< (@ 0x40051210) CLK_ABP1_I2C0 clock configuration register */ + __I uint32_t CLK_APB1_I2C0_STAT; /*!< (@ 0x40051214) CLK_APB1_I2C0 clock status register */ + __IO uint32_t CLK_APB1_I2S_CFG; /*!< (@ 0x40051218) CLK_APB1_I2S clock configuration register */ + __I uint32_t CLK_APB1_I2S_STAT; /*!< (@ 0x4005121C) CLK_APB1_I2S clock status register */ + __IO uint32_t CLK_APB1_CAN1_CFG; /*!< (@ 0x40051220) CLK_APB1_CAN1 clock configuration register */ + __I uint32_t CLK_APB1_CAN1_STAT; /*!< (@ 0x40051224) CLK_APB1_CAN1 clock status register */ __I uint32_t RESERVED2[54]; - __IO uint32_t CLK_SPIFI_CFG; /*!< (@ 0x40051300) CLK_SPIFI clock configuration register */ - __I uint32_t CLK_SPIFI_STAT; /*!< (@ 0x40051304) CLK_APB1_SPIFI clock status register */ + __IO uint32_t CLK_SPIFI_CFG; /*!< (@ 0x40051300) CLK_SPIFI clock configuration register */ + __I uint32_t CLK_SPIFI_STAT; /*!< (@ 0x40051304) CLK_APB1_SPIFI clock status register */ __I uint32_t RESERVED3[62]; - __IO uint32_t CLK_M4_BUS_CFG; /*!< (@ 0x40051400) CLK_M4_BUS clock configuration register */ - __I uint32_t CLK_M4_BUS_STAT; /*!< (@ 0x40051404) CLK_M4_BUSclock status register */ - __IO uint32_t CLK_M4_SPIFI_CFG; /*!< (@ 0x40051408) CLK_M4_SPIFI clock configuration register */ - __I uint32_t CLK_M4_SPIFI_STAT; /*!< (@ 0x4005140C) CLK_M4_SPIFI clock status register */ - __IO uint32_t CLK_M4_GPIO_CFG; /*!< (@ 0x40051410) CLK_M4_GPIO clock configuration register */ - __I uint32_t CLK_M4_GPIO_STAT; /*!< (@ 0x40051414) CLK_M4_GPIO clock status register */ - __IO uint32_t CLK_M4_LCD_CFG; /*!< (@ 0x40051418) CLK_M4_LCD clock configuration register */ - __I uint32_t CLK_M4_LCD_STAT; /*!< (@ 0x4005141C) CLK_M4_LCD clock status register */ - __IO uint32_t CLK_M4_ETHERNET_CFG; /*!< (@ 0x40051420) CLK_M4_ETHERNET clock configuration register */ - __I uint32_t CLK_M4_ETHERNET_STAT; /*!< (@ 0x40051424) CLK_M4_ETHERNET clock status register */ - __IO uint32_t CLK_M4_USB0_CFG; /*!< (@ 0x40051428) CLK_M4_USB0 clock configuration register */ - __I uint32_t CLK_M4_USB0_STAT; /*!< (@ 0x4005142C) CLK_M4_USB0 clock status register */ - __IO uint32_t CLK_M4_EMC_CFG; /*!< (@ 0x40051430) CLK_M4_EMC clock configuration register */ - __I uint32_t CLK_M4_EMC_STAT; /*!< (@ 0x40051434) CLK_M4_EMC clock status register */ - __IO uint32_t CLK_M4_SDIO_CFG; /*!< (@ 0x40051438) CLK_M4_SDIO clock configuration register */ - __I uint32_t CLK_M4_SDIO_STAT; /*!< (@ 0x4005143C) CLK_M4_SDIO clock status register */ - __IO uint32_t CLK_M4_DMA_CFG; /*!< (@ 0x40051440) CLK_M4_DMA clock configuration register */ - __I uint32_t CLK_M4_DMA_STAT; /*!< (@ 0x40051444) CLK_M4_DMA clock status register */ - __IO uint32_t CLK_M4_M4CORE_CFG; /*!< (@ 0x40051448) CLK_M4_M4CORE clock configuration register */ - __I uint32_t CLK_M4_M3CORE_STAT; /*!< (@ 0x4005144C) CLK_M4_M3CORE clock status register */ + __IO uint32_t CLK_M4_BUS_CFG; /*!< (@ 0x40051400) CLK_M4_BUS clock configuration register */ + __I uint32_t CLK_M4_BUS_STAT; /*!< (@ 0x40051404) CLK_M4_BUSclock status register */ + __IO uint32_t CLK_M4_SPIFI_CFG; /*!< (@ 0x40051408) CLK_M4_SPIFI clock configuration register */ + __I uint32_t CLK_M4_SPIFI_STAT; /*!< (@ 0x4005140C) CLK_M4_SPIFI clock status register */ + __IO uint32_t CLK_M4_GPIO_CFG; /*!< (@ 0x40051410) CLK_M4_GPIO clock configuration register */ + __I uint32_t CLK_M4_GPIO_STAT; /*!< (@ 0x40051414) CLK_M4_GPIO clock status register */ + __IO uint32_t CLK_M4_LCD_CFG; /*!< (@ 0x40051418) CLK_M4_LCD clock configuration register */ + __I uint32_t CLK_M4_LCD_STAT; /*!< (@ 0x4005141C) CLK_M4_LCD clock status register */ + __IO uint32_t CLK_M4_ETHERNET_CFG; /*!< (@ 0x40051420) CLK_M4_ETHERNET clock configuration register */ + __I uint32_t CLK_M4_ETHERNET_STAT; /*!< (@ 0x40051424) CLK_M4_ETHERNET clock status register */ + __IO uint32_t CLK_M4_USB0_CFG; /*!< (@ 0x40051428) CLK_M4_USB0 clock configuration register */ + __I uint32_t CLK_M4_USB0_STAT; /*!< (@ 0x4005142C) CLK_M4_USB0 clock status register */ + __IO uint32_t CLK_M4_EMC_CFG; /*!< (@ 0x40051430) CLK_M4_EMC clock configuration register */ + __I uint32_t CLK_M4_EMC_STAT; /*!< (@ 0x40051434) CLK_M4_EMC clock status register */ + __IO uint32_t CLK_M4_SDIO_CFG; /*!< (@ 0x40051438) CLK_M4_SDIO clock configuration register */ + __I uint32_t CLK_M4_SDIO_STAT; /*!< (@ 0x4005143C) CLK_M4_SDIO clock status register */ + __IO uint32_t CLK_M4_DMA_CFG; /*!< (@ 0x40051440) CLK_M4_DMA clock configuration register */ + __I uint32_t CLK_M4_DMA_STAT; /*!< (@ 0x40051444) CLK_M4_DMA clock status register */ + __IO uint32_t CLK_M4_M4CORE_CFG; /*!< (@ 0x40051448) CLK_M4_M4CORE clock configuration register */ + __I uint32_t CLK_M4_M4CORE_STAT; /*!< (@ 0x4005144C) CLK_M4_M3CORE clock status register */ __I uint32_t RESERVED4[6]; - __IO uint32_t CLK_M4_SCT_CFG; /*!< (@ 0x40051468) CLK_M4_SCT clock configuration register */ - __I uint32_t CLK_M4_SCT_STAT; /*!< (@ 0x4005146C) CLK_M4_SCT clock status register */ - __IO uint32_t CLK_M4_USB1_CFG; /*!< (@ 0x40051470) CLK_M4_USB1 clock configuration register */ - __I uint32_t CLK_M4_USB1_STAT; /*!< (@ 0x40051474) CLK_M4_USB1 clock status register */ - __IO uint32_t CLK_M4_EMCDIV_CFG; /*!< (@ 0x40051478) CLK_M4_EMCDIV clock configuration register */ - __I uint32_t CLK_M4_EMCDIV_STAT; /*!< (@ 0x4005147C) CLK_M4_EMCDIV clock status register */ - __I uint32_t RESERVED5[4]; - __IO uint32_t CLK_M4_M0APP_CFG; /*!< (@ 0x40051490) CLK_M0APP_CFG clock configuration register */ - __I uint32_t CLK_M4_M0APP_STAT; /*!< (@ 0x40051494) CLK_M4_MOAPP clock status register */ - __I uint32_t RESERVED6[26]; - __IO uint32_t CLK_M4_WWDT_CFG; /*!< (@ 0x40051500) CLK_M4_WWDT clock configuration register */ - __I uint32_t CLK_M4_WWDT_STAT; /*!< (@ 0x40051504) CLK_M4_WWDT clock status register */ - __IO uint32_t CLK_M4_USART0_CFG; /*!< (@ 0x40051508) CLK_M4_USART0 clock configuration register */ - __I uint32_t CLK_M4_USART0_STAT; /*!< (@ 0x4005150C) CLK_M4_USART0 clock status register */ - __IO uint32_t CLK_M4_UART1_CFG; /*!< (@ 0x40051510) CLK_M4_UART1 clock configuration register */ - __I uint32_t CLK_M4_UART1_STAT; /*!< (@ 0x40051514) CLK_M4_UART1 clock status register */ - __IO uint32_t CLK_M4_SSP0_CFG; /*!< (@ 0x40051518) CLK_M4_SSP0 clock configuration register */ - __I uint32_t CLK_M4_SSP0_STAT; /*!< (@ 0x4005151C) CLK_M4_SSP0 clock status register */ - __IO uint32_t CLK_M4_TIMER0_CFG; /*!< (@ 0x40051520) CLK_M4_TIMER0 clock configuration register */ - __I uint32_t CLK_M4_TIMER0_STAT; /*!< (@ 0x40051524) CLK_M4_TIMER0 clock status register */ - __IO uint32_t CLK_M4_TIMER1_CFG; /*!< (@ 0x40051528) CLK_M4_TIMER1clock configuration register */ - __I uint32_t CLK_M4_TIMER1_STAT; /*!< (@ 0x4005152C) CLK_M4_TIMER1 clock status register */ - __IO uint32_t CLK_M4_SCU_CFG; /*!< (@ 0x40051530) CLK_M4_SCU clock configuration register */ - __I uint32_t CLK_M4_SCU_STAT; /*!< (@ 0x40051534) CLK_SCU_XXX clock status register */ - __IO uint32_t CLK_M4_CREG_CFG; /*!< (@ 0x40051538) CLK_M4_CREGclock configuration register */ - __I uint32_t CLK_M4_CREG_STAT; /*!< (@ 0x4005153C) CLK_M4_CREG clock status register */ - __I uint32_t RESERVED7[48]; - __IO uint32_t CLK_M4_RITIMER_CFG; /*!< (@ 0x40051600) CLK_M4_RITIMER clock configuration register */ - __I uint32_t CLK_M4_RITIMER_STAT; /*!< (@ 0x40051604) CLK_M4_RITIMER clock status register */ - __IO uint32_t CLK_M4_USART2_CFG; /*!< (@ 0x40051608) CLK_M4_USART2 clock configuration register */ - __I uint32_t CLK_M4_USART2_STAT; /*!< (@ 0x4005160C) CLK_M4_USART2 clock status register */ - __IO uint32_t CLK_M4_USART3_CFG; /*!< (@ 0x40051610) CLK_M4_USART3 clock configuration register */ - __I uint32_t CLK_M4_USART3_STAT; /*!< (@ 0x40051614) CLK_M4_USART3 clock status register */ - __IO uint32_t CLK_M4_TIMER2_CFG; /*!< (@ 0x40051618) CLK_M4_TIMER2 clock configuration register */ - __I uint32_t CLK_M4_TIMER2_STAT; /*!< (@ 0x4005161C) CLK_M4_TIMER2 clock status register */ - __IO uint32_t CLK_M4_TIMER3_CFG; /*!< (@ 0x40051620) CLK_M4_TIMER3 clock configuration register */ - __I uint32_t CLK_M4_TIMER3_STAT; /*!< (@ 0x40051624) CLK_M4_TIMER3 clock status register */ - __IO uint32_t CLK_M4_SSP1_CFG; /*!< (@ 0x40051628) CLK_M4_SSP1 clock configuration register */ - __I uint32_t CLK_M4_SSP1_STAT; /*!< (@ 0x4005162C) CLK_M4_SSP1 clock status register */ - __IO uint32_t CLK_M4_QEI_CFG; /*!< (@ 0x40051630) CLK_M4_QEIclock configuration register */ - __I uint32_t CLK_M4_QEI_STAT; /*!< (@ 0x40051634) CLK_M4_QEI clock status register */ - __I uint32_t RESERVED8[50]; - __IO uint32_t CLK_PERIPH_BUS_CFG; /*!< (@ 0x40051700) CLK_PERIPH_BUS_CFG clock configuration register */ - __I uint32_t CLK_PERIPH_BUS_STAT; /*!< (@ 0x40051704) CLK_PERIPH_BUS_STAT clock status register */ - __I uint32_t RESERVED9[2]; - __IO uint32_t CLK_PERIPH_CORE_CFG; /*!< (@ 0x40051710) CLK_PERIPH_CORE_CFG clock configuration register */ - __I uint32_t CLK_PERIPH_CORE_STAT; /*!< (@ 0x40051714) CLK_CORE_BUS_STAT clock status register */ - __IO uint32_t CLK_PERIPH_SGPIO_CFG; /*!< (@ 0x40051718) CLK_PERIPH_SGPIO_CFG clock configuration register */ - __I uint32_t CLK_PERIPH_SGPIO_STAT; /*!< (@ 0x4005171C) CLK_CORE_SGPIO_STAT clock status register */ - __I uint32_t RESERVED10[56]; - __IO uint32_t CLK_USB0_CFG; /*!< (@ 0x40051800) CLK_M4_USB0 clock configuration register */ - __I uint32_t CLK_USB0_STAT; /*!< (@ 0x40051804) CLK_USB0 clock status register */ + __IO uint32_t CLK_M4_SCT_CFG; /*!< (@ 0x40051468) CLK_M4_SCT clock configuration register */ + __I uint32_t CLK_M4_SCT_STAT; /*!< (@ 0x4005146C) CLK_M4_SCT clock status register */ + __IO uint32_t CLK_M4_USB1_CFG; /*!< (@ 0x40051470) CLK_M4_USB1 clock configuration register */ + __I uint32_t CLK_M4_USB1_STAT; /*!< (@ 0x40051474) CLK_M4_USB1 clock status register */ + __IO uint32_t CLK_M4_EMCDIV_CFG; /*!< (@ 0x40051478) CLK_M4_EMCDIV clock configuration register */ + __I uint32_t CLK_M4_EMCDIV_STAT; /*!< (@ 0x4005147C) CLK_M4_EMCDIV clock status register */ + __IO uint32_t CLK_M4_FLASHA_CFG; /*!< (@ 0x40051480) CLK_M4_FLASHA clock configuration register */ + __I uint32_t CLK_M4_FLASHA_STAT; /*!< (@ 0x40051484) CLK_M4_FLASHA clock status register */ + __IO uint32_t CLK_M4_FLASHB_CFG; /*!< (@ 0x40051488) CLK_M4_FLASHB clock configuration register */ + __I uint32_t CLK_M4_FLASHB_STAT; /*!< (@ 0x4005148C) CLK_M4_FLASHB clock status register */ + __IO uint32_t CLK_M4_M0APP_CFG; /*!< (@ 0x40051490) CLK_M0APP_CFG clock configuration register */ + __I uint32_t CLK_M4_M0APP_STAT; /*!< (@ 0x40051494) CLK_M4_MOAPP clock status register */ + __IO uint32_t CLK_M4_ADCHS_CFG; /*!< (@ 0x40051498) CLK_ADCHS_CFG clock configuration register */ + __I uint32_t CLK_M4_ADCHS_STAT; /*!< (@ 0x4005149C) CLK_M4_ADCHS clock status register */ + __IO uint32_t CLK_M4_EEPROM_CFG; /*!< (@ 0x400514A0) CLK_EEPROM_CFG clock configuration register */ + __I uint32_t CLK_M4_EEPROM_STAT; /*!< (@ 0x400514A4) CLK_M4_EEPROM clock status register */ + __I uint32_t RESERVED5[22]; + __IO uint32_t CLK_M4_WWDT_CFG; /*!< (@ 0x40051500) CLK_M4_WWDT clock configuration register */ + __I uint32_t CLK_M4_WWDT_STAT; /*!< (@ 0x40051504) CLK_M4_WWDT clock status register */ + __IO uint32_t CLK_M4_USART0_CFG; /*!< (@ 0x40051508) CLK_M4_USART0 clock configuration register */ + __I uint32_t CLK_M4_USART0_STAT; /*!< (@ 0x4005150C) CLK_M4_USART0 clock status register */ + __IO uint32_t CLK_M4_UART1_CFG; /*!< (@ 0x40051510) CLK_M4_UART1 clock configuration register */ + __I uint32_t CLK_M4_UART1_STAT; /*!< (@ 0x40051514) CLK_M4_UART1 clock status register */ + __IO uint32_t CLK_M4_SSP0_CFG; /*!< (@ 0x40051518) CLK_M4_SSP0 clock configuration register */ + __I uint32_t CLK_M4_SSP0_STAT; /*!< (@ 0x4005151C) CLK_M4_SSP0 clock status register */ + __IO uint32_t CLK_M4_TIMER0_CFG; /*!< (@ 0x40051520) CLK_M4_TIMER0 clock configuration register */ + __I uint32_t CLK_M4_TIMER0_STAT; /*!< (@ 0x40051524) CLK_M4_TIMER0 clock status register */ + __IO uint32_t CLK_M4_TIMER1_CFG; /*!< (@ 0x40051528) CLK_M4_TIMER1clock configuration register */ + __I uint32_t CLK_M4_TIMER1_STAT; /*!< (@ 0x4005152C) CLK_M4_TIMER1 clock status register */ + __IO uint32_t CLK_M4_SCU_CFG; /*!< (@ 0x40051530) CLK_M4_SCU clock configuration register */ + __I uint32_t CLK_M4_SCU_STAT; /*!< (@ 0x40051534) CLK_SCU_XXX clock status register */ + __IO uint32_t CLK_M4_CREG_CFG; /*!< (@ 0x40051538) CLK_M4_CREGclock configuration register */ + __I uint32_t CLK_M4_CREG_STAT; /*!< (@ 0x4005153C) CLK_M4_CREG clock status register */ + __I uint32_t RESERVED6[48]; + __IO uint32_t CLK_M4_RITIMER_CFG; /*!< (@ 0x40051600) CLK_M4_RITIMER clock configuration register */ + __I uint32_t CLK_M4_RITIMER_STAT; /*!< (@ 0x40051604) CLK_M4_RITIMER clock status register */ + __IO uint32_t CLK_M4_USART2_CFG; /*!< (@ 0x40051608) CLK_M4_USART2 clock configuration register */ + __I uint32_t CLK_M4_USART2_STAT; /*!< (@ 0x4005160C) CLK_M4_USART2 clock status register */ + __IO uint32_t CLK_M4_USART3_CFG; /*!< (@ 0x40051610) CLK_M4_USART3 clock configuration register */ + __I uint32_t CLK_M4_USART3_STAT; /*!< (@ 0x40051614) CLK_M4_USART3 clock status register */ + __IO uint32_t CLK_M4_TIMER2_CFG; /*!< (@ 0x40051618) CLK_M4_TIMER2 clock configuration register */ + __I uint32_t CLK_M4_TIMER2_STAT; /*!< (@ 0x4005161C) CLK_M4_TIMER2 clock status register */ + __IO uint32_t CLK_M4_TIMER3_CFG; /*!< (@ 0x40051620) CLK_M4_TIMER3 clock configuration register */ + __I uint32_t CLK_M4_TIMER3_STAT; /*!< (@ 0x40051624) CLK_M4_TIMER3 clock status register */ + __IO uint32_t CLK_M4_SSP1_CFG; /*!< (@ 0x40051628) CLK_M4_SSP1 clock configuration register */ + __I uint32_t CLK_M4_SSP1_STAT; /*!< (@ 0x4005162C) CLK_M4_SSP1 clock status register */ + __IO uint32_t CLK_M4_QEI_CFG; /*!< (@ 0x40051630) CLK_M4_QEIclock configuration register */ + __I uint32_t CLK_M4_QEI_STAT; /*!< (@ 0x40051634) CLK_M4_QEI clock status register */ + __I uint32_t RESERVED7[50]; + __IO uint32_t CLK_PERIPH_BUS_CFG; /*!< (@ 0x40051700) CLK_PERIPH_BUS_CFG clock configuration register */ + __I uint32_t CLK_PERIPH_BUS_STAT; /*!< (@ 0x40051704) CLK_PERIPH_BUS_STAT clock status register */ + __I uint32_t RESERVED8[2]; + __IO uint32_t CLK_PERIPH_CORE_CFG; /*!< (@ 0x40051710) CLK_PERIPH_CORE_CFG clock configuration register */ + __I uint32_t CLK_PERIPH_CORE_STAT; /*!< (@ 0x40051714) CLK_CORE_BUS_STAT clock status register */ + __IO uint32_t CLK_PERIPH_SGPIO_CFG; /*!< (@ 0x40051718) CLK_PERIPH_SGPIO_CFG clock configuration register */ + __I uint32_t CLK_PERIPH_SGPIO_STAT; /*!< (@ 0x4005171C) CLK_CORE_SGPIO_STAT clock status register */ + __I uint32_t RESERVED9[56]; + __IO uint32_t CLK_USB0_CFG; /*!< (@ 0x40051800) CLK_M4_USB0 clock configuration register */ + __I uint32_t CLK_USB0_STAT; /*!< (@ 0x40051804) CLK_USB0 clock status register */ + __I uint32_t RESERVED10[62]; + __IO uint32_t CLK_USB1_CFG; /*!< (@ 0x40051900) CLK_USB1 clock configuration register */ + __I uint32_t CLK_USB1_STAT; /*!< (@ 0x40051904) CLK_USB1 clock status register */ __I uint32_t RESERVED11[62]; - __IO uint32_t CLK_USB1_CFG; /*!< (@ 0x40051900) CLK_USB1 clock configuration register */ - __I uint32_t CLK_USB1_STAT; /*!< (@ 0x40051904) CLK_USB1 clock status register */ + __IO uint32_t CLK_SPI_CFG; /*!< (@ 0x40051A00) CLK_SPI clock configuration register */ + __I uint32_t CLK_SPI_STAT; /*!< (@ 0x40051A04) CLK_SPI clock status register */ __I uint32_t RESERVED12[62]; - __IO uint32_t CLK_SPI_CFG; /*!< (@ 0x40051A00) CLK_SPI clock configuration register */ - __I uint32_t CLK_SPI_STAT; /*!< (@ 0x40051A04) CLK_SPI clock status register */ - __I uint32_t RESERVED13[62]; - __IO uint32_t CLK_VADC_CFG; /*!< (@ 0x40051B00) CLK_VADC clock configuration register */ - __I uint32_t CLK_VADC_STAT; /*!< (@ 0x40051B04) CLK_VADC clock status register */ + __IO uint32_t CLK_ADCHS_CFG; /*!< (@ 0x40051B00) CLK_ADCHS clock configuration register */ + __I uint32_t CLK_ADCHS_STAT; /*!< (@ 0x40051B04) CLK_ADCHS clock status register */ } LPC_CCU1_Type; -// ------------------------------------------------------------------------------------------------ -// ----- CCU2 ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ CCU2 ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx Clock Control Unit (CCU) Modification date=1/21/2011 Major revision=0 Minor revision=7 (CCU2) + * @brief Clock Control Unit (CCU2) (CCU2) */ -typedef struct { /*!< (@ 0x40052000) CCU2 Structure */ - __IO uint32_t PM; /*!< (@ 0x40052000) Power mode register */ - __I uint32_t BASE_STAT; /*!< (@ 0x40052004) CCU base clocks status register */ +typedef struct { /*!< (@ 0x40052000) CCU2 Structure */ + __IO uint32_t PM; /*!< (@ 0x40052000) Power mode register */ + __I uint32_t BASE_STAT; /*!< (@ 0x40052004) CCU base clocks status register */ __I uint32_t RESERVED0[62]; - __IO uint32_t CLK_APLL_CFG; /*!< (@ 0x40052100) CLK_APLL clock configuration register */ - __I uint32_t CLK_APLL_STAT; /*!< (@ 0x40052104) CLK_APLL clock status register */ + __IO uint32_t CLK_AUDIO_CFG; /*!< (@ 0x40052100) CLK_AUDIO clock configuration register */ + __I uint32_t CLK_AUDIO_STAT; /*!< (@ 0x40052104) CLK_AUDIO clock status register */ __I uint32_t RESERVED1[62]; - __IO uint32_t CLK_APB2_USART3_CFG; /*!< (@ 0x40052200) CLK_APB2_USART3 clock configuration register */ - __I uint32_t CLK_APB2_USART3_STAT; /*!< (@ 0x40052204) CLK_APB2_USART3 clock status register */ + __IO uint32_t CLK_APB2_USART3_CFG; /*!< (@ 0x40052200) CLK_APB2_USART3 clock configuration register */ + __I uint32_t CLK_APB2_USART3_STAT; /*!< (@ 0x40052204) CLK_APB2_USART3 clock status register */ __I uint32_t RESERVED2[62]; - __IO uint32_t CLK_APB2_USART2_CFG; /*!< (@ 0x40052300) CLK_APB2_USART2 clock configuration register */ - __I uint32_t CLK_APB2_USART2_STAT; /*!< (@ 0x40052304) CLK_APB2_USART clock status register */ + __IO uint32_t CLK_APB2_USART2_CFG; /*!< (@ 0x40052300) CLK_APB2_USART2 clock configuration register */ + __I uint32_t CLK_APB2_USART2_STAT; /*!< (@ 0x40052304) CLK_APB2_USART clock status register */ __I uint32_t RESERVED3[62]; - __IO uint32_t CLK_APB0_UART1_CFG; /*!< (@ 0x40052400) CLK_APB2_UART1 clock configuration register */ - __I uint32_t CLK_APB0_UART1_STAT; /*!< (@ 0x40052404) CLK_APB0_UART1 clock status register */ + __IO uint32_t CLK_APB0_UART1_CFG; /*!< (@ 0x40052400) CLK_APB2_UART1 clock configuration register */ + __I uint32_t CLK_APB0_UART1_STAT; /*!< (@ 0x40052404) CLK_APB0_UART1 clock status register */ __I uint32_t RESERVED4[62]; - __IO uint32_t CLK_APB0_USART0_CFG; /*!< (@ 0x40052500) CLK_APB2_USART0 clock configuration register */ - __I uint32_t CLK_APB0_USART0_STAT; /*!< (@ 0x40052504) CLK_APB0_USART0 clock status register */ + __IO uint32_t CLK_APB0_USART0_CFG; /*!< (@ 0x40052500) CLK_APB2_USART0 clock configuration register */ + __I uint32_t CLK_APB0_USART0_STAT; /*!< (@ 0x40052504) CLK_APB0_USART0 clock status register */ __I uint32_t RESERVED5[62]; - __IO uint32_t CLK_APB2_SSP1_CFG; /*!< (@ 0x40052600) CLK_APB2_SSP1 clock configuration register */ - __I uint32_t CLK_APB2_SSP1_STAT; /*!< (@ 0x40052604) CLK_APB2_SSP1 clock status register */ + __IO uint32_t CLK_APB2_SSP1_CFG; /*!< (@ 0x40052600) CLK_APB2_SSP1 clock configuration register */ + __I uint32_t CLK_APB2_SSP1_STAT; /*!< (@ 0x40052604) CLK_APB2_SSP1 clock status register */ __I uint32_t RESERVED6[62]; - __IO uint32_t CLK_APB0_SSP0_CFG; /*!< (@ 0x40052700) CLK_APB0_SSP0 clock configuration register */ - __I uint32_t CLK_APB0_SSP0_STAT; /*!< (@ 0x40052704) CLK_APB0_SSP0 clock status register */ + __IO uint32_t CLK_APB0_SSP0_CFG; /*!< (@ 0x40052700) CLK_APB0_SSP0 clock configuration register */ + __I uint32_t CLK_APB0_SSP0_STAT; /*!< (@ 0x40052704) CLK_APB0_SSP0 clock status register */ __I uint32_t RESERVED7[62]; - __IO uint32_t CLK_SDIO_CFG; /*!< (@ 0x40052800) CLK_SDIO clock configuration register */ - __I uint32_t CLK_SDIO_STAT; /*!< (@ 0x40052804) CLK_SDIO clock status register */ + __IO uint32_t CLK_SDIO_CFG; /*!< (@ 0x40052800) CLK_SDIO clock configuration register */ + __I uint32_t CLK_SDIO_STAT; /*!< (@ 0x40052804) CLK_SDIO clock status register */ } LPC_CCU2_Type; -// ------------------------------------------------------------------------------------------------ -// ----- RGU ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ RGU ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10503 Chapter title=LPC43xx Reset GenerationUnit (RGU) Modification date=7/20/2011 Major revision=0 Minor revision=13 (RGU) + * @brief Reset Generation Unit (RGU) (RGU) */ -typedef struct { /*!< (@ 0x40053000) RGU Structure */ +typedef struct { /*!< (@ 0x40053000) RGU Structure */ __I uint32_t RESERVED0[64]; - __O uint32_t RESET_CTRL0; /*!< (@ 0x40053100) Reset control register 0 */ - __O uint32_t RESET_CTRL1; /*!< (@ 0x40053104) Reset control register 1 */ + __O uint32_t RESET_CTRL0; /*!< (@ 0x40053100) Reset control register 0 */ + __O uint32_t RESET_CTRL1; /*!< (@ 0x40053104) Reset control register 1 */ __I uint32_t RESERVED1[2]; - __IO uint32_t RESET_STATUS0; /*!< (@ 0x40053110) Reset status register 0 */ - __IO uint32_t RESET_STATUS1; /*!< (@ 0x40053114) Reset status register 1 */ - __IO uint32_t RESET_STATUS2; /*!< (@ 0x40053118) Reset status register 2 */ - __IO uint32_t RESET_STATUS3; /*!< (@ 0x4005311C) Reset status register 3 */ + __IO uint32_t RESET_STATUS0; /*!< (@ 0x40053110) Reset status register 0 */ + __IO uint32_t RESET_STATUS1; /*!< (@ 0x40053114) Reset status register 1 */ + __IO uint32_t RESET_STATUS2; /*!< (@ 0x40053118) Reset status register 2 */ + __IO uint32_t RESET_STATUS3; /*!< (@ 0x4005311C) Reset status register 3 */ __I uint32_t RESERVED2[12]; - __I uint32_t RESET_ACTIVE_STATUS0; /*!< (@ 0x40053150) Reset active status register 0 */ - __I uint32_t RESET_ACTIVE_STATUS1; /*!< (@ 0x40053154) Reset active status register 1 */ - __I uint32_t RESERVED3[170]; - __IO uint32_t RESET_EXT_STAT0; /*!< (@ 0x40053400) Reset external status register 0 for CORE_RST */ - __IO uint32_t RESET_EXT_STAT1; /*!< (@ 0x40053404) Reset external status register 1 for PERIPH_RST */ - __IO uint32_t RESET_EXT_STAT2; /*!< (@ 0x40053408) Reset external status register 2 for MASTER_RST */ - __I uint32_t RESERVED4; - __IO uint32_t RESET_EXT_STAT4; /*!< (@ 0x40053410) Reset external status register 4 for WWDT_RST */ - __IO uint32_t RESET_EXT_STAT5; /*!< (@ 0x40053414) Reset external status register 5 for CREG_RST */ + __I uint32_t RESET_ACTIVE_STATUS0; /*!< (@ 0x40053150) Reset active status register 0 */ + __I uint32_t RESET_ACTIVE_STATUS1; /*!< (@ 0x40053154) Reset active status register 1 */ + __I uint32_t RESERVED3[171]; + __IO uint32_t RESET_EXT_STAT1; /*!< (@ 0x40053404) Reset external status register 1 for PERIPH_RST */ + __IO uint32_t RESET_EXT_STAT2; /*!< (@ 0x40053408) Reset external status register 2 for MASTER_RST */ + __I uint32_t RESERVED4[2]; + __IO uint32_t RESET_EXT_STAT5; /*!< (@ 0x40053414) Reset external status register 5 for CREG_RST */ __I uint32_t RESERVED5[2]; - __IO uint32_t RESET_EXT_STAT8; /*!< (@ 0x40053420) Reset external status register */ - __IO uint32_t RESET_EXT_STAT9; /*!< (@ 0x40053424) Reset external status register */ - __I uint32_t RESERVED6[3]; - __IO uint32_t RESET_EXT_STAT13; /*!< (@ 0x40053434) Reset external status register */ + __IO uint32_t RESET_EXT_STAT8; /*!< (@ 0x40053420) Reset external status register */ + __IO uint32_t RESET_EXT_STAT9; /*!< (@ 0x40053424) Reset external status register */ + __I uint32_t RESERVED6[2]; + __IO uint32_t RESET_EXT_STAT12; /*!< (@ 0x40053430) Reset external status register */ + __IO uint32_t RESET_EXT_STAT13; /*!< (@ 0x40053434) Reset external status register */ __I uint32_t RESERVED7[2]; - __IO uint32_t RESET_EXT_STAT16; /*!< (@ 0x40053440) Reset external status register */ - __IO uint32_t RESET_EXT_STAT17; /*!< (@ 0x40053444) Reset external status register */ - __IO uint32_t RESET_EXT_STAT18; /*!< (@ 0x40053448) Reset external status register */ - __IO uint32_t RESET_EXT_STAT19; /*!< (@ 0x4005344C) Reset external status register */ - __IO uint32_t RESET_EXT_STAT20; /*!< (@ 0x40053450) Reset external status register */ - __IO uint32_t RESET_EXT_STAT21; /*!< (@ 0x40053454) Reset external status register */ - __IO uint32_t RESET_EXT_STAT22; /*!< (@ 0x40053458) Reset external status register */ - __IO uint32_t RESET_EXT_STAT23; /*!< (@ 0x4005345C) Reset external status register */ - __I uint32_t RESERVED8[4]; - __IO uint32_t RESET_EXT_STAT28; /*!< (@ 0x40053470) Reset external status register */ - __I uint32_t RESERVED9[3]; - __IO uint32_t RESET_EXT_STAT32; /*!< (@ 0x40053480) Reset external status register */ - __IO uint32_t RESET_EXT_STAT33; /*!< (@ 0x40053484) Reset external status register */ - __IO uint32_t RESET_EXT_STAT34; /*!< (@ 0x40053488) Reset external status register */ - __IO uint32_t RESET_EXT_STAT35; /*!< (@ 0x4005348C) Reset external status register */ - __IO uint32_t RESET_EXT_STAT36; /*!< (@ 0x40053490) Reset external status register */ - __IO uint32_t RESET_EXT_STAT37; /*!< (@ 0x40053494) Reset external status register */ - __IO uint32_t RESET_EXT_STAT38; /*!< (@ 0x40053498) Reset external status register */ - __IO uint32_t RESET_EXT_STAT39; /*!< (@ 0x4005349C) Reset external status register */ - __IO uint32_t RESET_EXT_STAT40; /*!< (@ 0x400534A0) Reset external status register */ - __IO uint32_t RESET_EXT_STAT41; /*!< (@ 0x400534A4) Reset external status register */ - __IO uint32_t RESET_EXT_STAT42; /*!< (@ 0x400534A8) Reset external status register */ - __I uint32_t RESERVED10; - __IO uint32_t RESET_EXT_STAT44; /*!< (@ 0x400534B0) Reset external status register */ - __IO uint32_t RESET_EXT_STAT45; /*!< (@ 0x400534B4) Reset external status register */ - __IO uint32_t RESET_EXT_STAT46; /*!< (@ 0x400534B8) Reset external status register */ - __IO uint32_t RESET_EXT_STAT47; /*!< (@ 0x400534BC) Reset external status register */ - __IO uint32_t RESET_EXT_STAT48; /*!< (@ 0x400534C0) Reset external status register */ - __IO uint32_t RESET_EXT_STAT49; /*!< (@ 0x400534C4) Reset external status register */ - __IO uint32_t RESET_EXT_STAT50; /*!< (@ 0x400534C8) Reset external status register */ - __IO uint32_t RESET_EXT_STAT51; /*!< (@ 0x400534CC) Reset external status register */ - __IO uint32_t RESET_EXT_STAT52; /*!< (@ 0x400534D0) Reset external status register */ - __IO uint32_t RESET_EXT_STAT53; /*!< (@ 0x400534D4) Reset external status register */ - __IO uint32_t RESET_EXT_STAT54; /*!< (@ 0x400534D8) Reset external status register */ - __IO uint32_t RESET_EXT_STAT55; /*!< (@ 0x400534DC) Reset external status register */ - __IO uint32_t RESET_EXT_STAT56; /*!< (@ 0x400534E0) Reset external status register */ - __IO uint32_t RESET_EXT_STAT57; /*!< (@ 0x400534E4) Reset external status register */ - __IO uint32_t RESET_EXT_STAT58; /*!< (@ 0x400534E8) Reset external status register */ - __IO uint32_t RESET_EXT_STAT59; /*!< (@ 0x400534EC) Reserved */ - __IO uint32_t RESET_EXT_STAT60; /*!< (@ 0x400534F0) Reset external status register */ - __IO uint32_t RESET_EXT_STAT61; /*!< (@ 0x400534F4) Reserved */ - __IO uint32_t RESET_EXT_STAT62; /*!< (@ 0x400534F8) Reserved */ - __IO uint32_t RESET_EXT_STAT63; /*!< (@ 0x400534FC) Reserved */ + __IO uint32_t RESET_EXT_STAT16; /*!< (@ 0x40053440) Reset external status register */ + __IO uint32_t RESET_EXT_STAT17; /*!< (@ 0x40053444) Reset external status register */ + __IO uint32_t RESET_EXT_STAT18; /*!< (@ 0x40053448) Reset external status register */ + __IO uint32_t RESET_EXT_STAT19; /*!< (@ 0x4005344C) Reset external status register */ + __IO uint32_t RESET_EXT_STAT20; /*!< (@ 0x40053450) Reset external status register */ + __IO uint32_t RESET_EXT_STAT21; /*!< (@ 0x40053454) Reset external status register */ + __IO uint32_t RESET_EXT_STAT22; /*!< (@ 0x40053458) Reset external status register */ + __I uint32_t RESERVED8[2]; + __IO uint32_t RESET_EXT_STAT25; /*!< (@ 0x40053464) Reset external status register */ + __I uint32_t RESERVED9; + __IO uint32_t RESET_EXT_STAT27; /*!< (@ 0x4005346C) Reset external status register */ + __IO uint32_t RESET_EXT_STAT28; /*!< (@ 0x40053470) Reset external status register */ + __IO uint32_t RESET_EXT_STAT29; /*!< (@ 0x40053474) Reset external status register */ + __I uint32_t RESERVED10[2]; + __IO uint32_t RESET_EXT_STAT32; /*!< (@ 0x40053480) Reset external status register */ + __IO uint32_t RESET_EXT_STAT33; /*!< (@ 0x40053484) Reset external status register */ + __IO uint32_t RESET_EXT_STAT34; /*!< (@ 0x40053488) Reset external status register */ + __IO uint32_t RESET_EXT_STAT35; /*!< (@ 0x4005348C) Reset external status register */ + __IO uint32_t RESET_EXT_STAT36; /*!< (@ 0x40053490) Reset external status register */ + __IO uint32_t RESET_EXT_STAT37; /*!< (@ 0x40053494) Reset external status register */ + __IO uint32_t RESET_EXT_STAT38; /*!< (@ 0x40053498) Reset external status register */ + __IO uint32_t RESET_EXT_STAT39; /*!< (@ 0x4005349C) Reset external status register */ + __IO uint32_t RESET_EXT_STAT40; /*!< (@ 0x400534A0) Reset external status register */ + __IO uint32_t RESET_EXT_STAT41; /*!< (@ 0x400534A4) Reset external status register */ + __IO uint32_t RESET_EXT_STAT42; /*!< (@ 0x400534A8) Reset external status register */ + __I uint32_t RESERVED11; + __IO uint32_t RESET_EXT_STAT44; /*!< (@ 0x400534B0) Reset external status register */ + __IO uint32_t RESET_EXT_STAT45; /*!< (@ 0x400534B4) Reset external status register */ + __IO uint32_t RESET_EXT_STAT46; /*!< (@ 0x400534B8) Reset external status register */ + __IO uint32_t RESET_EXT_STAT47; /*!< (@ 0x400534BC) Reset external status register */ + __IO uint32_t RESET_EXT_STAT48; /*!< (@ 0x400534C0) Reset external status register */ + __IO uint32_t RESET_EXT_STAT49; /*!< (@ 0x400534C4) Reset external status register */ + __IO uint32_t RESET_EXT_STAT50; /*!< (@ 0x400534C8) Reset external status register */ + __IO uint32_t RESET_EXT_STAT51; /*!< (@ 0x400534CC) Reset external status register */ + __IO uint32_t RESET_EXT_STAT52; /*!< (@ 0x400534D0) Reset external status register */ + __IO uint32_t RESET_EXT_STAT53; /*!< (@ 0x400534D4) Reset external status register */ + __IO uint32_t RESET_EXT_STAT54; /*!< (@ 0x400534D8) Reset external status register */ + __IO uint32_t RESET_EXT_STAT55; /*!< (@ 0x400534DC) Reset external status register */ + __IO uint32_t RESET_EXT_STAT56; /*!< (@ 0x400534E0) Reset external status register */ + __IO uint32_t RESET_EXT_STAT57; /*!< (@ 0x400534E4) Reset external status register */ + __IO uint32_t RESET_EXT_STAT58; /*!< (@ 0x400534E8) Reset external status register */ + __I uint32_t RESERVED12; + __IO uint32_t RESET_EXT_STAT60; /*!< (@ 0x400534F0) Reset external status register */ } LPC_RGU_Type; -// ------------------------------------------------------------------------------------------------ -// ----- WWDT ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ WWDT ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx Windowed Watchdog timer (WWDT) Modification date=1/14/2011 Major revision=0 Minor revision=7 (WWDT) + * @brief Windowed Watchdog timer (WWDT) (WWDT) */ -typedef struct { /*!< (@ 0x40080000) WWDT Structure */ - __IO uint32_t MOD; /*!< (@ 0x40080000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ - __IO uint32_t TC; /*!< (@ 0x40080004) Watchdog timer constant register. This register determines the time-out value. */ - __O uint32_t FEED; /*!< (@ 0x40080008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */ - __I uint32_t TV; /*!< (@ 0x4008000C) Watchdog timer value register. This register reads out the current value of the Watchdog timer. */ +typedef struct { /*!< (@ 0x40080000) WWDT Structure */ + __IO uint32_t MOD; /*!< (@ 0x40080000) Watchdog mode register. This register contains + the basic mode and status of the Watchdog Timer. */ + __IO uint32_t TC; /*!< (@ 0x40080004) Watchdog timer constant register. This register + determines the time-out value. */ + __O uint32_t FEED; /*!< (@ 0x40080008) Watchdog feed sequence register. Writing 0xAA + followed by 0x55 to this register reloads the Watchdog timer + with the value contained in WDTC. */ + __I uint32_t TV; /*!< (@ 0x4008000C) Watchdog timer value register. This register + reads out the current value of the Watchdog timer. */ __I uint32_t RESERVED0; - __IO uint32_t WARNINT; /*!< (@ 0x40080014) Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */ - __IO uint32_t WINDOW; /*!< (@ 0x40080018) Watchdog timer window register. This register contains the Watchdog window value. */ + __IO uint32_t WARNINT; /*!< (@ 0x40080014) Watchdog warning interrupt register. This register + contains the Watchdog warning interrupt compare value. */ + __IO uint32_t WINDOW; /*!< (@ 0x40080018) Watchdog timer window register. This register + contains the Watchdog window value. */ } LPC_WWDT_Type; -// ------------------------------------------------------------------------------------------------ -// ----- USARTn ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ USARTn [USART0] ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx USART0_2_3 Modification date=1/14/2011 Major revision=0 Minor revision=7 (USARTn) + * @brief USART0_2_3 (USARTn) */ -typedef struct { /*!< (@ 0x400xx000) USARTn Structure */ - +typedef struct { /*!< (@ 0x40081000) USARTn Structure */ + union { - __IO uint32_t DLL; /*!< (@ 0x400xx000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */ - __O uint32_t THR; /*!< (@ 0x400xx000) Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */ - __I uint32_t RBR; /*!< (@ 0x400xx000) Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */ - } ; - + __IO uint32_t DLL; /*!< (@ 0x40081000) Divisor Latch LSB. Least significant byte of + the baud rate divisor value. The full divisor is used to generate + a baud rate from the fractional rate divider (DLAB = 1). */ + __O uint32_t THR; /*!< (@ 0x40081000) Transmit Holding Register. The next character + to be transmitted is written here (DLAB = 0). */ + __I uint32_t RBR; /*!< (@ 0x40081000) Receiver Buffer Register. Contains the next received + character to be read (DLAB = 0). */ + }; + union { - __IO uint32_t IER; /*!< (@ 0x400xx004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */ - __IO uint32_t DLM; /*!< (@ 0x400xx004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */ - } ; - + __IO uint32_t IER; /*!< (@ 0x40081004) Interrupt Enable Register. Contains individual + interrupt enable bits for the 7 potential USART interrupts (DLAB + = 0). */ + __IO uint32_t DLM; /*!< (@ 0x40081004) Divisor Latch MSB. Most significant byte of the + baud rate divisor value. The full divisor is used to generate + a baud rate from the fractional rate divider (DLAB = 1). */ + }; + union { - __O uint32_t FCR; /*!< (@ 0x400xx008) FIFO Control Register. Controls UART FIFO usage and modes. */ - __I uint32_t IIR; /*!< (@ 0x400xx008) Interrupt ID Register. Identifies which interrupt(s) are pending. */ - } ; - __IO uint32_t LCR; /*!< (@ 0x400xx00C) Line Control Register. Contains controls for frame formatting and break generation. */ - __I uint32_t RESERVED0[1]; - __I uint32_t LSR; /*!< (@ 0x400xx014) Line Status Register. Contains flags for transmit and receive status, including line errors. */ - __I uint32_t RESERVED1[1]; - __IO uint32_t SCR; /*!< (@ 0x400xx01C) Scratch Pad Register. Eight-bit temporary storage for software. */ - __IO uint32_t ACR; /*!< (@ 0x400xx020) Auto-baud Control Register. Contains controls for the auto-baud feature. */ - __IO uint32_t ICR; /*!< (@ 0x400xx024) IrDA control register (UART3 only) */ - __IO uint32_t FDR; /*!< (@ 0x400xx028) Fractional Divider Register. Generates a clock input for the baud rate divider. */ - __IO uint32_t OSR; /*!< (@ 0x400xx02C) Oversampling Register. Controls the degree of oversampling during each bit time. */ + __O uint32_t FCR; /*!< (@ 0x40081008) FIFO Control Register. Controls USART FIFO usage + and modes. */ + __I uint32_t IIR; /*!< (@ 0x40081008) Interrupt ID Register. Identifies which interrupt(s) + are pending. */ + }; + __IO uint32_t LCR; /*!< (@ 0x4008100C) Line Control Register. Contains controls for + frame formatting and break generation. */ + __I uint32_t RESERVED0; + __I uint32_t LSR; /*!< (@ 0x40081014) Line Status Register. Contains flags for transmit + and receive status, including line errors. */ + __I uint32_t RESERVED1; + __IO uint32_t SCR; /*!< (@ 0x4008101C) Scratch Pad Register. Eight-bit temporary storage + for software. */ + __IO uint32_t ACR; /*!< (@ 0x40081020) Auto-baud Control Register. Contains controls + for the auto-baud feature. */ + __IO uint32_t ICR; /*!< (@ 0x40081024) IrDA control register (USART3 only) */ + __IO uint32_t FDR; /*!< (@ 0x40081028) Fractional Divider Register. Generates a clock + input for the baud rate divider. */ + __IO uint32_t OSR; /*!< (@ 0x4008102C) Oversampling Register. Controls the degree of + oversampling during each bit time. */ __I uint32_t RESERVED2[4]; - __IO uint32_t HDEN; /*!< (@ 0x400xx03C) Half-duplex enable Register */ - __I uint32_t RESERVED3[1]; - __IO uint32_t SCICTRL; /*!< (@ 0x400xx048) Smart card interface control register */ - __IO uint32_t RS485CTRL; /*!< (@ 0x400xx04C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */ - __IO uint32_t RS485ADRMATCH; /*!< (@ 0x400xx050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */ - __IO uint32_t RS485DLY; /*!< (@ 0x400xx054) RS-485/EIA-485 direction control delay. */ - __IO uint32_t SYNCCTRL; /*!< (@ 0x400xx058) Synchronous mode control register. */ - __IO uint32_t TER; /*!< (@ 0x400xx05C) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */ + __IO uint32_t HDEN; /*!< (@ 0x40081040) Half-duplex enable Register */ + __I uint32_t RESERVED3; + __IO uint32_t SCICTRL; /*!< (@ 0x40081048) Smart card interface control register */ + __IO uint32_t RS485CTRL; /*!< (@ 0x4008104C) RS-485/EIA-485 Control. Contains controls to + configure various aspects of RS-485/EIA-485 modes. */ + __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40081050) RS-485/EIA-485 address match. Contains the address + match value for RS-485/EIA-485 mode. */ + __IO uint32_t RS485DLY; /*!< (@ 0x40081054) RS-485/EIA-485 direction control delay. */ + __IO uint32_t SYNCCTRL; /*!< (@ 0x40081058) Synchronous mode control register. */ + __IO uint32_t TER; /*!< (@ 0x4008105C) Transmit Enable Register. Turns off USART transmitter + for use with software flow control. */ } LPC_USARTn_Type; -// ------------------------------------------------------------------------------------------------ -// ----- UART1 ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ UART1 ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx UART1 Modification date=1/14/2011 Major revision=0 Minor revision=7 (UART1) + * @brief UART1 (UART1) */ -typedef struct { /*!< (@ 0x40082000) UART1 Structure */ - +typedef struct { /*!< (@ 0x40082000) UART1 Structure */ + union { - __IO uint32_t DLL; /*!< (@ 0x40082000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */ - __O uint32_t THR; /*!< (@ 0x40082000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */ - __I uint32_t RBR; /*!< (@ 0x40082000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */ - } ; - + __IO uint32_t DLL; /*!< (@ 0x40082000) Divisor Latch LSB. Least significant byte of + the baud rate divisor value. The full divisor is used to generate + a baud rate from the fractional rate divider. (DLAB=1) */ + __O uint32_t THR; /*!< (@ 0x40082000) Transmit Holding Register. The next character + to be transmitted is written here. (DLAB=0) */ + __I uint32_t RBR; /*!< (@ 0x40082000) Receiver Buffer Register. Contains the next received + character to be read. (DLAB=0) */ + }; + union { - __IO uint32_t IER; /*!< (@ 0x40082004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0) */ - __IO uint32_t DLM; /*!< (@ 0x40082004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1) */ - } ; - + __IO uint32_t IER; /*!< (@ 0x40082004) Interrupt Enable Register. Contains individual + interrupt enable bits for the 7 potential UART1 interrupts. + (DLAB=0) */ + __IO uint32_t DLM; /*!< (@ 0x40082004) Divisor Latch MSB. Most significant byte of the + baud rate divisor value. The full divisor is used to generate + a baud rate from the fractional rate divider.(DLAB=1) */ + }; + union { - __O uint32_t FCR; /*!< (@ 0x40082008) FIFO Control Register. Controls UART1 FIFO usage and modes. */ - __I uint32_t IIR; /*!< (@ 0x40082008) Interrupt ID Register. Identifies which interrupt(s) are pending. */ - } ; - __IO uint32_t LCR; /*!< (@ 0x4008200C) Line Control Register. Contains controls for frame formatting and break generation. */ - __IO uint32_t MCR; /*!< (@ 0x40082010) Modem Control Register. Contains controls for flow control handshaking and loopback mode. */ - __I uint32_t LSR; /*!< (@ 0x40082014) Line Status Register. Contains flags for transmit and receive status, including line errors. */ - __I uint32_t MSR; /*!< (@ 0x40082018) Modem Status Register. Contains handshake signal status flags. */ - __IO uint32_t SCR; /*!< (@ 0x4008201C) Scratch Pad Register. 8-bit temporary storage for software. */ - __IO uint32_t ACR; /*!< (@ 0x40082020) Auto-baud Control Register. Contains controls for the auto-baud feature. */ + __O uint32_t FCR; /*!< (@ 0x40082008) FIFO Control Register. Controls UART1 FIFO usage + and modes. */ + __I uint32_t IIR; /*!< (@ 0x40082008) Interrupt ID Register. Identifies which interrupt(s) + are pending. */ + }; + __IO uint32_t LCR; /*!< (@ 0x4008200C) Line Control Register. Contains controls for + frame formatting and break generation. */ + __IO uint32_t MCR; /*!< (@ 0x40082010) Modem Control Register. Contains controls for + flow control handshaking and loopback mode. */ + __I uint32_t LSR; /*!< (@ 0x40082014) Line Status Register. Contains flags for transmit + and receive status, including line errors. */ + __I uint32_t MSR; /*!< (@ 0x40082018) Modem Status Register. Contains handshake signal + status flags. */ + __IO uint32_t SCR; /*!< (@ 0x4008201C) Scratch Pad Register. 8-bit temporary storage + for software. */ + __IO uint32_t ACR; /*!< (@ 0x40082020) Auto-baud Control Register. Contains controls + for the auto-baud feature. */ __I uint32_t RESERVED0; - __IO uint32_t FDR; /*!< (@ 0x40082028) Fractional Divider Register. Generates a clock input for the baud rate divider. */ - __I uint32_t RESERVED1; - __IO uint32_t TER; /*!< (@ 0x40082030) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */ - __I uint32_t RESERVED2[6]; - __IO uint32_t RS485CTRL; /*!< (@ 0x4008204C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */ - __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40082050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */ - __IO uint32_t RS485DLY; /*!< (@ 0x40082054) RS-485/EIA-485 direction control delay. */ - __I uint32_t FIFOLVL; /*!< (@ 0x40082058) FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */ + __IO uint32_t FDR; /*!< (@ 0x40082028) Fractional Divider Register. Generates a clock + input for the baud rate divider. */ + __I uint32_t RESERVED1[8]; + __IO uint32_t RS485CTRL; /*!< (@ 0x4008204C) RS-485/EIA-485 Control. Contains controls to + configure various aspects of RS-485/EIA-485 modes. */ + __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40082050) RS-485/EIA-485 address match. Contains the address + match value for RS-485/EIA-485 mode. */ + __IO uint32_t RS485DLY; /*!< (@ 0x40082054) RS-485/EIA-485 direction control delay. */ + __I uint32_t RESERVED2; + __IO uint32_t TER; /*!< (@ 0x4008205C) Transmit Enable Register. Turns off UART transmitter + for use with software flow control. */ } LPC_UART1_Type; -// ------------------------------------------------------------------------------------------------ -// ----- SSPn ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ SSPn [SSP0] ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx SSP0/1 Modification date=1/14/2011 Major revision=0 Minor revision=7 (SSP0) + * @brief SSP0/1 (SSPn) */ -typedef struct { /*!< (@ 0x400xx000) SSPn Structure */ - __IO uint32_t CR0; /*!< (@ 0x400xx000) Control Register 0. Selects the serial clock rate, bus type, and data size. */ - __IO uint32_t CR1; /*!< (@ 0x400xx004) Control Register 1. Selects master/slave and other modes. */ - __IO uint32_t DR; /*!< (@ 0x400xx008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */ - __I uint32_t SR; /*!< (@ 0x400xx00C) Status Register */ - __IO uint32_t CPSR; /*!< (@ 0x400xx010) Clock Prescale Register */ - __IO uint32_t IMSC; /*!< (@ 0x400xx014) Interrupt Mask Set and Clear Register */ - __I uint32_t RIS; /*!< (@ 0x400xx018) Raw Interrupt Status Register */ - __I uint32_t MIS; /*!< (@ 0x400xx01C) Masked Interrupt Status Register */ - __O uint32_t ICR; /*!< (@ 0x400xx020) SSPICR Interrupt Clear Register */ - __IO uint32_t DMACR; /*!< (@ 0x400xx024) SSPn DMA control register */ +typedef struct { /*!< (@ 0x40083000) SSPn Structure */ + __IO uint32_t CR0; /*!< (@ 0x40083000) Control Register 0. Selects the serial clock + rate, bus type, and data size. */ + __IO uint32_t CR1; /*!< (@ 0x40083004) Control Register 1. Selects master/slave and + other modes. */ + __IO uint32_t DR; /*!< (@ 0x40083008) Data Register. Writes fill the transmit FIFO, + and reads empty the receive FIFO. */ + __I uint32_t SR; /*!< (@ 0x4008300C) Status Register */ + __IO uint32_t CPSR; /*!< (@ 0x40083010) Clock Prescale Register */ + __IO uint32_t IMSC; /*!< (@ 0x40083014) Interrupt Mask Set and Clear Register */ + __I uint32_t RIS; /*!< (@ 0x40083018) Raw Interrupt Status Register */ + __I uint32_t MIS; /*!< (@ 0x4008301C) Masked Interrupt Status Register */ + __O uint32_t ICR; /*!< (@ 0x40083020) SSPICR Interrupt Clear Register */ + __IO uint32_t DMACR; /*!< (@ 0x40083024) SSP0 DMA control register */ } LPC_SSPn_Type; -// ------------------------------------------------------------------------------------------------ -// ----- TIMERn ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ TIMERn [TIMER0] ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx Timer0/1/2/3 Modification date=1/14/2011 Major revision=0 Minor revision=7 (TIMERn) + * @brief Timer0/1/2/3 (TIMERn) */ -typedef struct { /*!< (@ 0x400xx000) TIMERn Structure */ - __IO uint32_t IR; /*!< (@ 0x400xx000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ - __IO uint32_t TCR; /*!< (@ 0x400xx004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ - __IO uint32_t TC; /*!< (@ 0x400xx008) Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */ - __IO uint32_t PR; /*!< (@ 0x400xx00C) Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */ - __IO uint32_t PC; /*!< (@ 0x400xx010) Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */ - __IO uint32_t MCR; /*!< (@ 0x400xx014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */ - __IO uint32_t MR[4]; /*!< (@ 0x400xx018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ - __IO uint32_t CCR; /*!< (@ 0x400xx028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ - __IO uint32_t CR[4]; /*!< (@ 0x400xx02C) Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */ - __IO uint32_t EMR; /*!< (@ 0x400xx03C) External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */ +typedef struct { /*!< (@ 0x40084000) TIMERn Structure */ + __IO uint32_t IR; /*!< (@ 0x40084000) Interrupt Register. The IR can be written to + clear interrupts. The IR can be read to identify which of eight + possible interrupt sources are pending. */ + __IO uint32_t TCR; /*!< (@ 0x40084004) Timer Control Register. The TCR is used to control + the Timer Counter functions. The Timer Counter can be disabled + or reset through the TCR. */ + __IO uint32_t TC; /*!< (@ 0x40084008) Timer Counter. The 32 bit TC is incremented every + PR+1 cycles of PCLK. The TC is controlled through the TCR. */ + __IO uint32_t PR; /*!< (@ 0x4008400C) Prescale Register. When the Prescale Counter + (PC) is equal to this value, the next clock increments the TC + and clears the PC. */ + __IO uint32_t PC; /*!< (@ 0x40084010) Prescale Counter. The 32 bit PC is a counter + which is incremented to the value stored in PR. When the value + in PR is reached, the TC is incremented and the PC is cleared. + The PC is observable and controllable through the bus interface. */ + __IO uint32_t MCR; /*!< (@ 0x40084014) Match Control Register. The MCR is used to control + if an interrupt is generated and if the TC is reset when a Match + occurs. */ + __IO uint32_t MR0; /*!< (@ 0x40084018) Match Register 0. MR0 can be enabled through + the MCR to reset the TC, stop both the TC and PC, and/or generate + an interrupt every time MR0 matches the TC. */ + __IO uint32_t MR1; /*!< (@ 0x4008401C) Match Register 0. MR0 can be enabled through + the MCR to reset the TC, stop both the TC and PC, and/or generate + an interrupt every time MR0 matches the TC. */ + __IO uint32_t MR2; /*!< (@ 0x40084020) Match Register 0. MR0 can be enabled through + the MCR to reset the TC, stop both the TC and PC, and/or generate + an interrupt every time MR0 matches the TC. */ + __IO uint32_t MR3; /*!< (@ 0x40084024) Match Register 0. MR0 can be enabled through + the MCR to reset the TC, stop both the TC and PC, and/or generate + an interrupt every time MR0 matches the TC. */ + __IO uint32_t CCR; /*!< (@ 0x40084028) Capture Control Register. The CCR controls which + edges of the capture inputs are used to load the Capture Registers + and whether or not an interrupt is generated when a capture + takes place. */ + __I uint32_t CR0; /*!< (@ 0x4008402C) Capture Register 0. CR0 is loaded with the value + of TC when there is an event on the CAPn.0 input. */ + __I uint32_t CR1; /*!< (@ 0x40084030) Capture Register 0. CR0 is loaded with the value + of TC when there is an event on the CAPn.0 input. */ + __I uint32_t CR2; /*!< (@ 0x40084034) Capture Register 0. CR0 is loaded with the value + of TC when there is an event on the CAPn.0 input. */ + __I uint32_t CR3; /*!< (@ 0x40084038) Capture Register 0. CR0 is loaded with the value + of TC when there is an event on the CAPn.0 input. */ + __IO uint32_t EMR; /*!< (@ 0x4008403C) External Match Register. The EMR controls the + external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */ __I uint32_t RESERVED0[12]; - __IO uint32_t CTCR; /*!< (@ 0x400xx070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ + __IO uint32_t CTCR; /*!< (@ 0x40084070) Count Control Register. The CTCR selects between + Timer and Counter mode, and in Counter mode selects the signal + and edge(s) for counting. */ } LPC_TIMERn_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- SCU ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ SCU ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx System Control Unit (SCU) Modification date=6/8/2011 Major revision=0 Minor revision=10 (SCU) + * @brief System Control Unit (SCU) I/O configuration (SCU) */ -typedef struct { /*!< (@ 0x40086000) SCU Structure */ - __IO uint32_t SFSP0_0; /*!< (@ 0x40086000) Pin configuration register for pins P0 */ - __IO uint32_t SFSP0_1; /*!< (@ 0x40086004) Pin configuration register for pins P0 */ +typedef struct { /*!< (@ 0x40086000) SCU Structure */ + __IO uint32_t SFSP0_0; /*!< (@ 0x40086000) Pin configuration register for pins P0 */ + __IO uint32_t SFSP0_1; /*!< (@ 0x40086004) Pin configuration register for pins P0 */ __I uint32_t RESERVED0[30]; - __IO uint32_t SFSP1_0; /*!< (@ 0x40086080) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_1; /*!< (@ 0x40086084) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_2; /*!< (@ 0x40086088) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_3; /*!< (@ 0x4008608C) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_4; /*!< (@ 0x40086090) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_5; /*!< (@ 0x40086094) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_6; /*!< (@ 0x40086098) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_7; /*!< (@ 0x4008609C) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_8; /*!< (@ 0x400860A0) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_9; /*!< (@ 0x400860A4) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_10; /*!< (@ 0x400860A8) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_11; /*!< (@ 0x400860AC) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_12; /*!< (@ 0x400860B0) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_13; /*!< (@ 0x400860B4) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_14; /*!< (@ 0x400860B8) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_15; /*!< (@ 0x400860BC) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_16; /*!< (@ 0x400860C0) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_17; /*!< (@ 0x400860C4) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_18; /*!< (@ 0x400860C8) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_19; /*!< (@ 0x400860CC) Pin configuration register for pins P1 */ - __IO uint32_t SFSP1_20; /*!< (@ 0x400860D0) Pin configuration register for pins P1 */ + __IO uint32_t SFSP1_0; /*!< (@ 0x40086080) Pin configuration register for pins P1 */ + __IO uint32_t SFSP1_1; /*!< (@ 0x40086084) Pin configuration register for pins P1 */ + __IO uint32_t SFSP1_2; /*!< (@ 0x40086088) Pin configuration register for pins P1 */ + __IO uint32_t SFSP1_3; /*!< (@ 0x4008608C) Pin configuration register for pins P1 */ + __IO uint32_t SFSP1_4; /*!< (@ 0x40086090) Pin configuration register for pins P1 */ + __IO uint32_t SFSP1_5; /*!< (@ 0x40086094) Pin configuration register for pins P1 */ + __IO uint32_t SFSP1_6; /*!< (@ 0x40086098) Pin configuration register for pins P1 */ + __IO uint32_t SFSP1_7; /*!< (@ 0x4008609C) Pin configuration register for pins P1 */ + __IO uint32_t SFSP1_8; /*!< (@ 0x400860A0) Pin configuration register for pins P1 */ + __IO uint32_t SFSP1_9; /*!< (@ 0x400860A4) Pin configuration register for pins P1 */ + __IO uint32_t SFSP1_10; /*!< (@ 0x400860A8) Pin configuration register for pins P1 */ + __IO uint32_t SFSP1_11; /*!< (@ 0x400860AC) Pin configuration register for pins P1 */ + __IO uint32_t SFSP1_12; /*!< (@ 0x400860B0) Pin configuration register for pins P1 */ + __IO uint32_t SFSP1_13; /*!< (@ 0x400860B4) Pin configuration register for pins P1 */ + __IO uint32_t SFSP1_14; /*!< (@ 0x400860B8) Pin configuration register for pins P1 */ + __IO uint32_t SFSP1_15; /*!< (@ 0x400860BC) Pin configuration register for pins P1 */ + __IO uint32_t SFSP1_16; /*!< (@ 0x400860C0) Pin configuration register for pins P1 */ + __IO uint32_t SFSP1_17; /*!< (@ 0x400860C4) Pin configuration register for pins P1_17 */ + __IO uint32_t SFSP1_18; /*!< (@ 0x400860C8) Pin configuration register for pins P1 */ + __IO uint32_t SFSP1_19; /*!< (@ 0x400860CC) Pin configuration register for pins P1 */ + __IO uint32_t SFSP1_20; /*!< (@ 0x400860D0) Pin configuration register for pins P1 */ __I uint32_t RESERVED1[11]; - __IO uint32_t SFSP2_0; /*!< (@ 0x40086100) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_1; /*!< (@ 0x40086104) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_2; /*!< (@ 0x40086108) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_3; /*!< (@ 0x4008610C) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_4; /*!< (@ 0x40086110) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_5; /*!< (@ 0x40086114) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_6; /*!< (@ 0x40086118) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_7; /*!< (@ 0x4008611C) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_8; /*!< (@ 0x40086120) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_9; /*!< (@ 0x40086124) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_10; /*!< (@ 0x40086128) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_11; /*!< (@ 0x4008612C) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_12; /*!< (@ 0x40086130) Pin configuration register for pins P2 */ - __IO uint32_t SFSP2_13; /*!< (@ 0x40086134) Pin configuration register for pins P2 */ + __IO uint32_t SFSP2_0; /*!< (@ 0x40086100) Pin configuration register for pins P2 */ + __IO uint32_t SFSP2_1; /*!< (@ 0x40086104) Pin configuration register for pins P2 */ + __IO uint32_t SFSP2_2; /*!< (@ 0x40086108) Pin configuration register for pins P2 */ + __IO uint32_t SFSP2_3; /*!< (@ 0x4008610C) Pin configuration register for pins P2 */ + __IO uint32_t SFSP2_4; /*!< (@ 0x40086110) Pin configuration register for pins P2 */ + __IO uint32_t SFSP2_5; /*!< (@ 0x40086114) Pin configuration register for pins P2 */ + __IO uint32_t SFSP2_6; /*!< (@ 0x40086118) Pin configuration register for pins P2 */ + __IO uint32_t SFSP2_7; /*!< (@ 0x4008611C) Pin configuration register for pins P2 */ + __IO uint32_t SFSP2_8; /*!< (@ 0x40086120) Pin configuration register for pins P2 */ + __IO uint32_t SFSP2_9; /*!< (@ 0x40086124) Pin configuration register for pins P2 */ + __IO uint32_t SFSP2_10; /*!< (@ 0x40086128) Pin configuration register for pins P2 */ + __IO uint32_t SFSP2_11; /*!< (@ 0x4008612C) Pin configuration register for pins P2 */ + __IO uint32_t SFSP2_12; /*!< (@ 0x40086130) Pin configuration register for pins P2 */ + __IO uint32_t SFSP2_13; /*!< (@ 0x40086134) Pin configuration register for pins P2 */ __I uint32_t RESERVED2[18]; - __IO uint32_t SFSP3_0; /*!< (@ 0x40086180) Pin configuration register for pins P3 */ - __IO uint32_t SFSP3_1; /*!< (@ 0x40086184) Pin configuration register for pins P3 */ - __IO uint32_t SFSP3_2; /*!< (@ 0x40086188) Pin configuration register for pins P3 */ - __IO uint32_t SFSP3_3; /*!< (@ 0x4008618C) Pin configuration register for pins P3 */ - __IO uint32_t SFSP3_4; /*!< (@ 0x40086190) Pin configuration register for pins P3 */ - __IO uint32_t SFSP3_5; /*!< (@ 0x40086194) Pin configuration register for pins P3 */ - __IO uint32_t SFSP3_6; /*!< (@ 0x40086198) Pin configuration register for pins P3 */ - __IO uint32_t SFSP3_7; /*!< (@ 0x4008619C) Pin configuration register for pins P3 */ - __IO uint32_t SFSP3_8; /*!< (@ 0x400861A0) Pin configuration register for pins P3 */ + __IO uint32_t SFSP3_0; /*!< (@ 0x40086180) Pin configuration register for pins P3 */ + __IO uint32_t SFSP3_1; /*!< (@ 0x40086184) Pin configuration register for pins P3 */ + __IO uint32_t SFSP3_2; /*!< (@ 0x40086188) Pin configuration register for pins P3 */ + __IO uint32_t SFSP3_3; /*!< (@ 0x4008618C) Pin configuration register for pins P3 */ + __IO uint32_t SFSP3_4; /*!< (@ 0x40086190) Pin configuration register for pins P3 */ + __IO uint32_t SFSP3_5; /*!< (@ 0x40086194) Pin configuration register for pins P3 */ + __IO uint32_t SFSP3_6; /*!< (@ 0x40086198) Pin configuration register for pins P3 */ + __IO uint32_t SFSP3_7; /*!< (@ 0x4008619C) Pin configuration register for pins P3 */ + __IO uint32_t SFSP3_8; /*!< (@ 0x400861A0) Pin configuration register for pins P3 */ __I uint32_t RESERVED3[23]; - __IO uint32_t SFSP4_0; /*!< (@ 0x40086200) Pin configuration register for pins P4 */ - __IO uint32_t SFSP4_1; /*!< (@ 0x40086204) Pin configuration register for pins P4 */ - __IO uint32_t SFSP4_2; /*!< (@ 0x40086208) Pin configuration register for pins P4 */ - __IO uint32_t SFSP4_3; /*!< (@ 0x4008620C) Pin configuration register for pins P4 */ - __IO uint32_t SFSP4_4; /*!< (@ 0x40086210) Pin configuration register for pins P4 */ - __IO uint32_t SFSP4_5; /*!< (@ 0x40086214) Pin configuration register for pins P4 */ - __IO uint32_t SFSP4_6; /*!< (@ 0x40086218) Pin configuration register for pins P4 */ - __IO uint32_t SFSP4_7; /*!< (@ 0x4008621C) Pin configuration register for pins P4 */ - __IO uint32_t SFSP4_8; /*!< (@ 0x40086220) Pin configuration register for pins P4 */ - __IO uint32_t SFSP4_9; /*!< (@ 0x40086224) Pin configuration register for pins P4 */ - __IO uint32_t SFSP4_10; /*!< (@ 0x40086228) Pin configuration register for pins P4 */ + __IO uint32_t SFSP4_0; /*!< (@ 0x40086200) Pin configuration register for pins P4 */ + __IO uint32_t SFSP4_1; /*!< (@ 0x40086204) Pin configuration register for pins P4 */ + __IO uint32_t SFSP4_2; /*!< (@ 0x40086208) Pin configuration register for pins P4 */ + __IO uint32_t SFSP4_3; /*!< (@ 0x4008620C) Pin configuration register for pins P4 */ + __IO uint32_t SFSP4_4; /*!< (@ 0x40086210) Pin configuration register for pins P4 */ + __IO uint32_t SFSP4_5; /*!< (@ 0x40086214) Pin configuration register for pins P4 */ + __IO uint32_t SFSP4_6; /*!< (@ 0x40086218) Pin configuration register for pins P4 */ + __IO uint32_t SFSP4_7; /*!< (@ 0x4008621C) Pin configuration register for pins P4 */ + __IO uint32_t SFSP4_8; /*!< (@ 0x40086220) Pin configuration register for pins P4 */ + __IO uint32_t SFSP4_9; /*!< (@ 0x40086224) Pin configuration register for pins P4 */ + __IO uint32_t SFSP4_10; /*!< (@ 0x40086228) Pin configuration register for pins P4 */ __I uint32_t RESERVED4[21]; - __IO uint32_t SFSP5_0; /*!< (@ 0x40086280) Pin configuration register for pins P5 */ - __IO uint32_t SFSP5_1; /*!< (@ 0x40086284) Pin configuration register for pins P5 */ - __IO uint32_t SFSP5_2; /*!< (@ 0x40086288) Pin configuration register for pins P5 */ - __IO uint32_t SFSP5_3; /*!< (@ 0x4008628C) Pin configuration register for pins P5 */ - __IO uint32_t SFSP5_4; /*!< (@ 0x40086290) Pin configuration register for pins P5 */ - __IO uint32_t SFSP5_5; /*!< (@ 0x40086294) Pin configuration register for pins P5 */ - __IO uint32_t SFSP5_6; /*!< (@ 0x40086298) Pin configuration register for pins P5 */ - __IO uint32_t SFSP5_7; /*!< (@ 0x4008629C) Pin configuration register for pins P5 */ + __IO uint32_t SFSP5_0; /*!< (@ 0x40086280) Pin configuration register for pins P5 */ + __IO uint32_t SFSP5_1; /*!< (@ 0x40086284) Pin configuration register for pins P5 */ + __IO uint32_t SFSP5_2; /*!< (@ 0x40086288) Pin configuration register for pins P5 */ + __IO uint32_t SFSP5_3; /*!< (@ 0x4008628C) Pin configuration register for pins P5 */ + __IO uint32_t SFSP5_4; /*!< (@ 0x40086290) Pin configuration register for pins P5 */ + __IO uint32_t SFSP5_5; /*!< (@ 0x40086294) Pin configuration register for pins P5 */ + __IO uint32_t SFSP5_6; /*!< (@ 0x40086298) Pin configuration register for pins P5 */ + __IO uint32_t SFSP5_7; /*!< (@ 0x4008629C) Pin configuration register for pins P5 */ __I uint32_t RESERVED5[24]; - __IO uint32_t SFSP6_0; /*!< (@ 0x40086300) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_1; /*!< (@ 0x40086304) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_2; /*!< (@ 0x40086308) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_3; /*!< (@ 0x4008630C) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_4; /*!< (@ 0x40086310) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_5; /*!< (@ 0x40086314) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_6; /*!< (@ 0x40086318) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_7; /*!< (@ 0x4008631C) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_8; /*!< (@ 0x40086320) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_9; /*!< (@ 0x40086324) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_10; /*!< (@ 0x40086328) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_11; /*!< (@ 0x4008632C) Pin configuration register for pins P6 */ - __IO uint32_t SFSP6_12; /*!< (@ 0x40086330) Pin configuration register for pins P6 */ + __IO uint32_t SFSP6_0; /*!< (@ 0x40086300) Pin configuration register for pins P6 */ + __IO uint32_t SFSP6_1; /*!< (@ 0x40086304) Pin configuration register for pins P6 */ + __IO uint32_t SFSP6_2; /*!< (@ 0x40086308) Pin configuration register for pins P6 */ + __IO uint32_t SFSP6_3; /*!< (@ 0x4008630C) Pin configuration register for pins P6 */ + __IO uint32_t SFSP6_4; /*!< (@ 0x40086310) Pin configuration register for pins P6 */ + __IO uint32_t SFSP6_5; /*!< (@ 0x40086314) Pin configuration register for pins P6 */ + __IO uint32_t SFSP6_6; /*!< (@ 0x40086318) Pin configuration register for pins P6 */ + __IO uint32_t SFSP6_7; /*!< (@ 0x4008631C) Pin configuration register for pins P6 */ + __IO uint32_t SFSP6_8; /*!< (@ 0x40086320) Pin configuration register for pins P6 */ + __IO uint32_t SFSP6_9; /*!< (@ 0x40086324) Pin configuration register for pins P6 */ + __IO uint32_t SFSP6_10; /*!< (@ 0x40086328) Pin configuration register for pins P6 */ + __IO uint32_t SFSP6_11; /*!< (@ 0x4008632C) Pin configuration register for pins P6 */ + __IO uint32_t SFSP6_12; /*!< (@ 0x40086330) Pin configuration register for pins P6 */ __I uint32_t RESERVED6[19]; - __IO uint32_t SFSP7_0; /*!< (@ 0x40086380) Pin configuration register for pins P7 */ - __IO uint32_t SFSP7_1; /*!< (@ 0x40086384) Pin configuration register for pins P7 */ - __IO uint32_t SFSP7_2; /*!< (@ 0x40086388) Pin configuration register for pins P7 */ - __IO uint32_t SFSP7_3; /*!< (@ 0x4008638C) Pin configuration register for pins P7 */ - __IO uint32_t SFSP7_4; /*!< (@ 0x40086390) Pin configuration register for pins P7 */ - __IO uint32_t SFSP7_5; /*!< (@ 0x40086394) Pin configuration register for pins P7 */ - __IO uint32_t SFSP7_6; /*!< (@ 0x40086398) Pin configuration register for pins P7 */ - __IO uint32_t SFSP7_7; /*!< (@ 0x4008639C) Pin configuration register for pins P7 */ + __IO uint32_t SFSP7_0; /*!< (@ 0x40086380) Pin configuration register for pins P7 */ + __IO uint32_t SFSP7_1; /*!< (@ 0x40086384) Pin configuration register for pins P7 */ + __IO uint32_t SFSP7_2; /*!< (@ 0x40086388) Pin configuration register for pins P7 */ + __IO uint32_t SFSP7_3; /*!< (@ 0x4008638C) Pin configuration register for pins P7 */ + __IO uint32_t SFSP7_4; /*!< (@ 0x40086390) Pin configuration register for pins P7 */ + __IO uint32_t SFSP7_5; /*!< (@ 0x40086394) Pin configuration register for pins P7 */ + __IO uint32_t SFSP7_6; /*!< (@ 0x40086398) Pin configuration register for pins P7 */ + __IO uint32_t SFSP7_7; /*!< (@ 0x4008639C) Pin configuration register for pins P7 */ __I uint32_t RESERVED7[24]; - __IO uint32_t SFSP8_0; /*!< (@ 0x40086400) Pin configuration register for pins P8 */ - __IO uint32_t SFSP8_1; /*!< (@ 0x40086404) Pin configuration register for pins P8 */ - __IO uint32_t SFSP8_2; /*!< (@ 0x40086408) Pin configuration register for pins P8 */ - __IO uint32_t SFSP8_3; /*!< (@ 0x4008640C) Pin configuration register for pins P8 */ - __IO uint32_t SFSP8_4; /*!< (@ 0x40086410) Pin configuration register for pins P8 */ - __IO uint32_t SFSP8_5; /*!< (@ 0x40086414) Pin configuration register for pins P8 */ - __IO uint32_t SFSP8_6; /*!< (@ 0x40086418) Pin configuration register for pins P8 */ - __IO uint32_t SFSP8_7; /*!< (@ 0x4008641C) Pin configuration register for pins P8 */ - __IO uint32_t SFSP8_8; /*!< (@ 0x40086420) Pin configuration register for pins P8 */ + __IO uint32_t SFSP8_0; /*!< (@ 0x40086400) Pin configuration register for pins P8 */ + __IO uint32_t SFSP8_1; /*!< (@ 0x40086404) Pin configuration register for pins P8 */ + __IO uint32_t SFSP8_2; /*!< (@ 0x40086408) Pin configuration register for pins P8 */ + __IO uint32_t SFSP8_3; /*!< (@ 0x4008640C) Pin configuration register for pins P8 */ + __IO uint32_t SFSP8_4; /*!< (@ 0x40086410) Pin configuration register for pins P8 */ + __IO uint32_t SFSP8_5; /*!< (@ 0x40086414) Pin configuration register for pins P8 */ + __IO uint32_t SFSP8_6; /*!< (@ 0x40086418) Pin configuration register for pins P8 */ + __IO uint32_t SFSP8_7; /*!< (@ 0x4008641C) Pin configuration register for pins P8 */ + __IO uint32_t SFSP8_8; /*!< (@ 0x40086420) Pin configuration register for pins P8 */ __I uint32_t RESERVED8[23]; - __IO uint32_t SFSP9_0; /*!< (@ 0x40086480) Pin configuration register for pins P9 */ - __IO uint32_t SFSP9_1; /*!< (@ 0x40086484) Pin configuration register for pins P9 */ - __IO uint32_t SFSP9_2; /*!< (@ 0x40086488) Pin configuration register for pins P9 */ - __IO uint32_t SFSP9_3; /*!< (@ 0x4008648C) Pin configuration register for pins P9 */ - __IO uint32_t SFSP9_4; /*!< (@ 0x40086490) Pin configuration register for pins P9 */ - __IO uint32_t SFSP9_5; /*!< (@ 0x40086494) Pin configuration register for pins P9 */ - __IO uint32_t SFSP9_6; /*!< (@ 0x40086498) Pin configuration register for pins P9 */ + __IO uint32_t SFSP9_0; /*!< (@ 0x40086480) Pin configuration register for pins P9 */ + __IO uint32_t SFSP9_1; /*!< (@ 0x40086484) Pin configuration register for pins P9 */ + __IO uint32_t SFSP9_2; /*!< (@ 0x40086488) Pin configuration register for pins P9 */ + __IO uint32_t SFSP9_3; /*!< (@ 0x4008648C) Pin configuration register for pins P9 */ + __IO uint32_t SFSP9_4; /*!< (@ 0x40086490) Pin configuration register for pins P9 */ + __IO uint32_t SFSP9_5; /*!< (@ 0x40086494) Pin configuration register for pins P9 */ + __IO uint32_t SFSP9_6; /*!< (@ 0x40086498) Pin configuration register for pins P9 */ __I uint32_t RESERVED9[25]; - __IO uint32_t SFSPA_0; /*!< (@ 0x40086500) Pin configuration register for pins PA */ - __IO uint32_t SFSPA_1; /*!< (@ 0x40086504) Pin configuration register for pins PA */ - __IO uint32_t SFSPA_2; /*!< (@ 0x40086508) Pin configuration register for pins PA */ - __IO uint32_t SFSPA_3; /*!< (@ 0x4008650C) Pin configuration register for pins PA */ - __IO uint32_t SFSPA_4; /*!< (@ 0x40086510) Pin configuration register for pins PA */ + __IO uint32_t SFSPA_0; /*!< (@ 0x40086500) Pin configuration register for pins PA */ + __IO uint32_t SFSPA_1; /*!< (@ 0x40086504) Pin configuration register for pins PA */ + __IO uint32_t SFSPA_2; /*!< (@ 0x40086508) Pin configuration register for pins PA */ + __IO uint32_t SFSPA_3; /*!< (@ 0x4008650C) Pin configuration register for pins PA */ + __IO uint32_t SFSPA_4; /*!< (@ 0x40086510) Pin configuration register for pins PA */ __I uint32_t RESERVED10[27]; - __IO uint32_t SFSPB_0; /*!< (@ 0x40086580) Pin configuration register for pins PB */ - __IO uint32_t SFSPB_1; /*!< (@ 0x40086584) Pin configuration register for pins PB */ - __IO uint32_t SFSPB_2; /*!< (@ 0x40086588) Pin configuration register for pins PB */ - __IO uint32_t SFSPB_3; /*!< (@ 0x4008658C) Pin configuration register for pins PB */ - __IO uint32_t SFSPB_4; /*!< (@ 0x40086590) Pin configuration register for pins PB */ - __IO uint32_t SFSPB_5; /*!< (@ 0x40086594) Pin configuration register for pins PB */ - __IO uint32_t SFSPB_6; /*!< (@ 0x40086598) Pin configuration register for pins PB */ + __IO uint32_t SFSPB_0; /*!< (@ 0x40086580) Pin configuration register for pins PB */ + __IO uint32_t SFSPB_1; /*!< (@ 0x40086584) Pin configuration register for pins PB */ + __IO uint32_t SFSPB_2; /*!< (@ 0x40086588) Pin configuration register for pins PB */ + __IO uint32_t SFSPB_3; /*!< (@ 0x4008658C) Pin configuration register for pins PB */ + __IO uint32_t SFSPB_4; /*!< (@ 0x40086590) Pin configuration register for pins PB */ + __IO uint32_t SFSPB_5; /*!< (@ 0x40086594) Pin configuration register for pins PB */ + __IO uint32_t SFSPB_6; /*!< (@ 0x40086598) Pin configuration register for pins PB */ __I uint32_t RESERVED11[25]; - __IO uint32_t SFSPC_0; /*!< (@ 0x40086600) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_1; /*!< (@ 0x40086604) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_2; /*!< (@ 0x40086608) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_3; /*!< (@ 0x4008660C) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_4; /*!< (@ 0x40086610) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_5; /*!< (@ 0x40086614) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_6; /*!< (@ 0x40086618) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_7; /*!< (@ 0x4008661C) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_8; /*!< (@ 0x40086620) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_9; /*!< (@ 0x40086624) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_10; /*!< (@ 0x40086628) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_11; /*!< (@ 0x4008662C) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_12; /*!< (@ 0x40086630) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_13; /*!< (@ 0x40086634) Pin configuration register for pins PC */ - __IO uint32_t SFSPC_14; /*!< (@ 0x40086638) Pin configuration register for pins PC */ + __IO uint32_t SFSPC_0; /*!< (@ 0x40086600) Pin configuration register for pins PC */ + __IO uint32_t SFSPC_1; /*!< (@ 0x40086604) Pin configuration register for pins PC */ + __IO uint32_t SFSPC_2; /*!< (@ 0x40086608) Pin configuration register for pins PC */ + __IO uint32_t SFSPC_3; /*!< (@ 0x4008660C) Pin configuration register for pins PC */ + __IO uint32_t SFSPC_4; /*!< (@ 0x40086610) Pin configuration register for pins PC */ + __IO uint32_t SFSPC_5; /*!< (@ 0x40086614) Pin configuration register for pins PC */ + __IO uint32_t SFSPC_6; /*!< (@ 0x40086618) Pin configuration register for pins PC */ + __IO uint32_t SFSPC_7; /*!< (@ 0x4008661C) Pin configuration register for pins PC */ + __IO uint32_t SFSPC_8; /*!< (@ 0x40086620) Pin configuration register for pins PC */ + __IO uint32_t SFSPC_9; /*!< (@ 0x40086624) Pin configuration register for pins PC */ + __IO uint32_t SFSPC_10; /*!< (@ 0x40086628) Pin configuration register for pins PC */ + __IO uint32_t SFSPC_11; /*!< (@ 0x4008662C) Pin configuration register for pins PC */ + __IO uint32_t SFSPC_12; /*!< (@ 0x40086630) Pin configuration register for pins PC */ + __IO uint32_t SFSPC_13; /*!< (@ 0x40086634) Pin configuration register for pins PC */ + __IO uint32_t SFSPC_14; /*!< (@ 0x40086638) Pin configuration register for pins PC */ __I uint32_t RESERVED12[17]; - __IO uint32_t SFSPD_0; /*!< (@ 0x40086680) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_1; /*!< (@ 0x40086684) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_2; /*!< (@ 0x40086688) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_3; /*!< (@ 0x4008668C) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_4; /*!< (@ 0x40086690) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_5; /*!< (@ 0x40086694) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_6; /*!< (@ 0x40086698) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_7; /*!< (@ 0x4008669C) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_8; /*!< (@ 0x400866A0) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_9; /*!< (@ 0x400866A4) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_10; /*!< (@ 0x400866A8) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_11; /*!< (@ 0x400866AC) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_12; /*!< (@ 0x400866B0) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_13; /*!< (@ 0x400866B4) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_14; /*!< (@ 0x400866B8) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_15; /*!< (@ 0x400866BC) Pin configuration register for pins PD */ - __IO uint32_t SFSPD_16; /*!< (@ 0x400866C0) Pin configuration register for pins PD */ + __IO uint32_t SFSPD_0; /*!< (@ 0x40086680) Pin configuration register for pins PD */ + __IO uint32_t SFSPD_1; /*!< (@ 0x40086684) Pin configuration register for pins PD */ + __IO uint32_t SFSPD_2; /*!< (@ 0x40086688) Pin configuration register for pins PD */ + __IO uint32_t SFSPD_3; /*!< (@ 0x4008668C) Pin configuration register for pins PD */ + __IO uint32_t SFSPD_4; /*!< (@ 0x40086690) Pin configuration register for pins PD */ + __IO uint32_t SFSPD_5; /*!< (@ 0x40086694) Pin configuration register for pins PD */ + __IO uint32_t SFSPD_6; /*!< (@ 0x40086698) Pin configuration register for pins PD */ + __IO uint32_t SFSPD_7; /*!< (@ 0x4008669C) Pin configuration register for pins PD */ + __IO uint32_t SFSPD_8; /*!< (@ 0x400866A0) Pin configuration register for pins PD */ + __IO uint32_t SFSPD_9; /*!< (@ 0x400866A4) Pin configuration register for pins PD */ + __IO uint32_t SFSPD_10; /*!< (@ 0x400866A8) Pin configuration register for pins PD */ + __IO uint32_t SFSPD_11; /*!< (@ 0x400866AC) Pin configuration register for pins PD */ + __IO uint32_t SFSPD_12; /*!< (@ 0x400866B0) Pin configuration register for pins PD */ + __IO uint32_t SFSPD_13; /*!< (@ 0x400866B4) Pin configuration register for pins PD */ + __IO uint32_t SFSPD_14; /*!< (@ 0x400866B8) Pin configuration register for pins PD */ + __IO uint32_t SFSPD_15; /*!< (@ 0x400866BC) Pin configuration register for pins PD */ + __IO uint32_t SFSPD_16; /*!< (@ 0x400866C0) Pin configuration register for pins PD */ __I uint32_t RESERVED13[15]; - __IO uint32_t SFSPE_0; /*!< (@ 0x40086700) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_1; /*!< (@ 0x40086704) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_2; /*!< (@ 0x40086708) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_3; /*!< (@ 0x4008670C) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_4; /*!< (@ 0x40086710) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_5; /*!< (@ 0x40086714) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_6; /*!< (@ 0x40086718) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_7; /*!< (@ 0x4008671C) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_8; /*!< (@ 0x40086720) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_9; /*!< (@ 0x40086724) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_10; /*!< (@ 0x40086728) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_11; /*!< (@ 0x4008672C) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_12; /*!< (@ 0x40086730) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_13; /*!< (@ 0x40086734) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_14; /*!< (@ 0x40086738) Pin configuration register for pins PE */ - __IO uint32_t SFSPE_15; /*!< (@ 0x4008673C) Pin configuration register for pins PE */ + __IO uint32_t SFSPE_0; /*!< (@ 0x40086700) Pin configuration register for pins PE */ + __IO uint32_t SFSPE_1; /*!< (@ 0x40086704) Pin configuration register for pins PE */ + __IO uint32_t SFSPE_2; /*!< (@ 0x40086708) Pin configuration register for pins PE */ + __IO uint32_t SFSPE_3; /*!< (@ 0x4008670C) Pin configuration register for pins PE */ + __IO uint32_t SFSPE_4; /*!< (@ 0x40086710) Pin configuration register for pins PE */ + __IO uint32_t SFSPE_5; /*!< (@ 0x40086714) Pin configuration register for pins PE */ + __IO uint32_t SFSPE_6; /*!< (@ 0x40086718) Pin configuration register for pins PE */ + __IO uint32_t SFSPE_7; /*!< (@ 0x4008671C) Pin configuration register for pins PE */ + __IO uint32_t SFSPE_8; /*!< (@ 0x40086720) Pin configuration register for pins PE */ + __IO uint32_t SFSPE_9; /*!< (@ 0x40086724) Pin configuration register for pins PE */ + __IO uint32_t SFSPE_10; /*!< (@ 0x40086728) Pin configuration register for pins PE */ + __IO uint32_t SFSPE_11; /*!< (@ 0x4008672C) Pin configuration register for pins PE */ + __IO uint32_t SFSPE_12; /*!< (@ 0x40086730) Pin configuration register for pins PE */ + __IO uint32_t SFSPE_13; /*!< (@ 0x40086734) Pin configuration register for pins PE */ + __IO uint32_t SFSPE_14; /*!< (@ 0x40086738) Pin configuration register for pins PE */ + __IO uint32_t SFSPE_15; /*!< (@ 0x4008673C) Pin configuration register for pins PE */ __I uint32_t RESERVED14[16]; - __IO uint32_t SFSPF_0; /*!< (@ 0x40086780) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_1; /*!< (@ 0x40086784) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_2; /*!< (@ 0x40086788) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_3; /*!< (@ 0x4008678C) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_4; /*!< (@ 0x40086790) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_5; /*!< (@ 0x40086794) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_6; /*!< (@ 0x40086798) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_7; /*!< (@ 0x4008679C) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_8; /*!< (@ 0x400867A0) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_9; /*!< (@ 0x400867A4) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_10; /*!< (@ 0x400867A8) Pin configuration register for pins PF */ - __IO uint32_t SFSPF_11; /*!< (@ 0x400867AC) Pin configuration register for pins PF */ + __IO uint32_t SFSPF_0; /*!< (@ 0x40086780) Pin configuration register for pins PF */ + __IO uint32_t SFSPF_1; /*!< (@ 0x40086784) Pin configuration register for pins PF */ + __IO uint32_t SFSPF_2; /*!< (@ 0x40086788) Pin configuration register for pins PF */ + __IO uint32_t SFSPF_3; /*!< (@ 0x4008678C) Pin configuration register for pins PF */ + __IO uint32_t SFSPF_4; /*!< (@ 0x40086790) Pin configuration register for pins PF */ + __IO uint32_t SFSPF_5; /*!< (@ 0x40086794) Pin configuration register for pins PF */ + __IO uint32_t SFSPF_6; /*!< (@ 0x40086798) Pin configuration register for pins PF */ + __IO uint32_t SFSPF_7; /*!< (@ 0x4008679C) Pin configuration register for pins PF */ + __IO uint32_t SFSPF_8; /*!< (@ 0x400867A0) Pin configuration register for pins PF */ + __IO uint32_t SFSPF_9; /*!< (@ 0x400867A4) Pin configuration register for pins PF */ + __IO uint32_t SFSPF_10; /*!< (@ 0x400867A8) Pin configuration register for pins PF */ + __IO uint32_t SFSPF_11; /*!< (@ 0x400867AC) Pin configuration register for pins PF */ __I uint32_t RESERVED15[276]; - __IO uint32_t SFSCLK_0; /*!< (@ 0x40086C00) Pin configuration register for pin CLK0 */ - __IO uint32_t SFSCLK_1; /*!< (@ 0x40086C04) Pin configuration register for pin CLK1 */ - __IO uint32_t SFSCLK_2; /*!< (@ 0x40086C08) Pin configuration register for pin CLK2 */ - __IO uint32_t SFSCLK_3; /*!< (@ 0x40086C0C) Pin configuration register for pin CLK3 */ + __IO uint32_t SFSCLK_0; /*!< (@ 0x40086C00) Pin configuration register for pins CLK */ + __IO uint32_t SFSCLK_1; /*!< (@ 0x40086C04) Pin configuration register for pins CLK */ + __IO uint32_t SFSCLK_2; /*!< (@ 0x40086C08) Pin configuration register for pins CLK */ + __IO uint32_t SFSCLK_3; /*!< (@ 0x40086C0C) Pin configuration register for pins CLK */ __I uint32_t RESERVED16[28]; - __IO uint32_t SFSUSB; /*!< (@ 0x40086C80) Pin configuration register for */ - __IO uint32_t SFSI2C0; /*!< (@ 0x40086C84) Pin configuration register for I 2C0-bus pins */ - __IO uint32_t ENAIO0; /*!< (@ 0x40086C88) ADC0 function select register */ - __IO uint32_t ENAIO1; /*!< (@ 0x40086C8C) ADC1 function select register */ - __IO uint32_t ENAIO2; /*!< (@ 0x40086C90) Analog function select register */ + __IO uint32_t SFSUSB; /*!< (@ 0x40086C80) Pin configuration register for pins USB1_DM and + USB1_DP */ + __IO uint32_t SFSI2C0; /*!< (@ 0x40086C84) Pin configuration register for I2C0-bus pins */ + __IO uint32_t ENAIO0; /*!< (@ 0x40086C88) ADC0 function select register */ + __IO uint32_t ENAIO1; /*!< (@ 0x40086C8C) ADC1 function select register */ + __IO uint32_t ENAIO2; /*!< (@ 0x40086C90) Analog function select register */ __I uint32_t RESERVED17[27]; - __IO uint32_t EMCDELAYCLK; /*!< (@ 0x40086D00) EMC clock delay register */ - __I uint32_t RESERVED18[63]; - __IO uint32_t PINTSEL0; /*!< (@ 0x40086E00) Pin interrupt select register for pin interrupts 0 to 3. */ - __IO uint32_t PINTSEL1; /*!< (@ 0x40086E04) Pin interrupt select register for pin interrupts 4 to 7. */ + __IO uint32_t EMCDELAYCLK; /*!< (@ 0x40086D00) EMC clock delay register */ + __I uint32_t RESERVED18[31]; + __IO uint32_t SDDELAY; /*!< (@ 0x40086D80) SD/MMC sample and drive delay register */ + __I uint32_t RESERVED19[31]; + __IO uint32_t PINTSEL0; /*!< (@ 0x40086E00) Pin interrupt select register for pin interrupts + 0 to 3. */ + __IO uint32_t PINTSEL1; /*!< (@ 0x40086E04) Pin interrupt select register for pin interrupts + 4 to 7. */ } LPC_SCU_Type; -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_PIN_INT ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ GPIO_PIN_INT ================ */ +/* ================================================================================ */ /** * @brief GPIO pin interrupt (GPIO_PIN_INT) */ -typedef struct { /*!< (@ 0x40087000) GPIO_PIN_INT Structure */ - __IO uint32_t ISEL; /*!< (@ 0x40087000) Pin Interrupt Mode register */ - __IO uint32_t IENR; /*!< (@ 0x40087004) Pin Interrupt Enable (Rising) register */ - __O uint32_t SIENR; /*!< (@ 0x40087008) Set Pin Interrupt Enable (Rising) register */ - __O uint32_t CIENR; /*!< (@ 0x4008700C) Clear Pin Interrupt Enable (Rising) register */ - __IO uint32_t IENF; /*!< (@ 0x40087010) Pin Interrupt Enable Falling Edge / Active Level register */ - __O uint32_t SIENF; /*!< (@ 0x40087014) Set Pin Interrupt Enable Falling Edge / Active Level register */ - __O uint32_t CIENF; /*!< (@ 0x40087018) Clear Pin Interrupt Enable Falling Edge / Active Level address */ - __IO uint32_t RISE; /*!< (@ 0x4008701C) Pin Interrupt Rising Edge register */ - __IO uint32_t FALL; /*!< (@ 0x40087020) Pin Interrupt Falling Edge register */ - __IO uint32_t IST; /*!< (@ 0x40087024) Pin Interrupt Status register */ +typedef struct { /*!< (@ 0x40087000) GPIO_PIN_INT Structure */ + __IO uint32_t ISEL; /*!< (@ 0x40087000) Pin Interrupt Mode register */ + __IO uint32_t IENR; /*!< (@ 0x40087004) Pin Interrupt Enable (Rising) register */ + __O uint32_t SIENR; /*!< (@ 0x40087008) Set Pin Interrupt Enable (Rising) register */ + __O uint32_t CIENR; /*!< (@ 0x4008700C) Clear Pin Interrupt Enable (Rising) register */ + __IO uint32_t IENF; /*!< (@ 0x40087010) Pin Interrupt Enable Falling Edge / Active Level + register */ + __O uint32_t SIENF; /*!< (@ 0x40087014) Set Pin Interrupt Enable Falling Edge / Active + Level register */ + __O uint32_t CIENF; /*!< (@ 0x40087018) Clear Pin Interrupt Enable Falling Edge / Active + Level address */ + __IO uint32_t RISE; /*!< (@ 0x4008701C) Pin Interrupt Rising Edge register */ + __IO uint32_t FALL; /*!< (@ 0x40087020) Pin Interrupt Falling Edge register */ + __IO uint32_t IST; /*!< (@ 0x40087024) Pin Interrupt Status register */ } LPC_GPIO_PIN_INT_Type; -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_GROUP_INTn ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ GPIO_GROUP_INTn [GPIO_GROUP_INT0] ================ */ +/* ================================================================================ */ /** * @brief GPIO group interrupt 0 (GPIO_GROUP_INTn) */ -typedef struct { /*!< (@ 0x40088000) GPIO_GROUP_INTn Structure */ - __IO uint32_t CTRL; /*!< (@ 0x40088000) GPIO grouped interrupt control register */ +typedef struct { /*!< (@ 0x40088000) GPIO_GROUP_INTn Structure */ + __IO uint32_t CTRL; /*!< (@ 0x40088000) GPIO grouped interrupt control register */ __I uint32_t RESERVED0[7]; - __IO uint32_t PORT_POL0; /*!< (@ 0x40088020) GPIO grouped interrupt port polarity register */ - __IO uint32_t PORT_POL1; /*!< (@ 0x40088024) GPIO grouped interrupt port polarity register */ - __IO uint32_t PORT_POL2; /*!< (@ 0x40088028) GPIO grouped interrupt port polarity register */ - __IO uint32_t PORT_POL3; /*!< (@ 0x4008802C) GPIO grouped interrupt port polarity register */ - __IO uint32_t PORT_POL4; /*!< (@ 0x40088030) GPIO grouped interrupt port polarity register */ - __IO uint32_t PORT_POL5; /*!< (@ 0x40088034) GPIO grouped interrupt port polarity register */ - __IO uint32_t PORT_POL6; /*!< (@ 0x40088038) GPIO grouped interrupt port polarity register */ - __IO uint32_t PORT_POL7; /*!< (@ 0x4008803C) GPIO grouped interrupt port polarity register */ - __IO uint32_t PORT_ENA0; /*!< (@ 0x40088040) GPIO grouped interrupt port m enable register */ - __IO uint32_t PORT_ENA1; /*!< (@ 0x40088044) GPIO grouped interrupt port m enable register */ - __IO uint32_t PORT_ENA2; /*!< (@ 0x40088048) GPIO grouped interrupt port m enable register */ - __IO uint32_t PORT_ENA3; /*!< (@ 0x4008804C) GPIO grouped interrupt port m enable register */ - __IO uint32_t PORT_ENA4; /*!< (@ 0x40088050) GPIO grouped interrupt port m enable register */ - __IO uint32_t PORT_ENA5; /*!< (@ 0x40088054) GPIO grouped interrupt port m enable register */ - __IO uint32_t PORT_ENA6; /*!< (@ 0x40088058) GPIO grouped interrupt port m enable register */ - __IO uint32_t PORT_ENA7; /*!< (@ 0x4008805C) GPIO grouped interrupt port m enable register */ + __IO uint32_t PORT_POL0; /*!< (@ 0x40088020) GPIO grouped interrupt port polarity register */ + __IO uint32_t PORT_POL1; /*!< (@ 0x40088024) GPIO grouped interrupt port polarity register */ + __IO uint32_t PORT_POL2; /*!< (@ 0x40088028) GPIO grouped interrupt port polarity register */ + __IO uint32_t PORT_POL3; /*!< (@ 0x4008802C) GPIO grouped interrupt port polarity register */ + __IO uint32_t PORT_POL4; /*!< (@ 0x40088030) GPIO grouped interrupt port polarity register */ + __IO uint32_t PORT_POL5; /*!< (@ 0x40088034) GPIO grouped interrupt port polarity register */ + __IO uint32_t PORT_POL6; /*!< (@ 0x40088038) GPIO grouped interrupt port polarity register */ + __IO uint32_t PORT_POL7; /*!< (@ 0x4008803C) GPIO grouped interrupt port polarity register */ + __IO uint32_t PORT_ENA0; /*!< (@ 0x40088040) GPIO grouped interrupt port m enable register */ + __IO uint32_t PORT_ENA1; /*!< (@ 0x40088044) GPIO grouped interrupt port m enable register */ + __IO uint32_t PORT_ENA2; /*!< (@ 0x40088048) GPIO grouped interrupt port m enable register */ + __IO uint32_t PORT_ENA3; /*!< (@ 0x4008804C) GPIO grouped interrupt port m enable register */ + __IO uint32_t PORT_ENA4; /*!< (@ 0x40088050) GPIO grouped interrupt port m enable register */ + __IO uint32_t PORT_ENA5; /*!< (@ 0x40088054) GPIO grouped interrupt port m enable register */ + __IO uint32_t PORT_ENA6; /*!< (@ 0x40088058) GPIO grouped interrupt port m enable register */ + __IO uint32_t PORT_ENA7; /*!< (@ 0x4008805C) GPIO grouped interrupt port m enable register */ } LPC_GPIO_GROUP_INTn_Type; -// ------------------------------------------------------------------------------------------------ -// ----- MCPWM ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ MCPWM ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx Motor Control PWM (MOTOCONPWM) Modification date=1/14/2011 Major revision=0 Minor revision=7 (MCPWM) + * @brief Motor Control PWM (MOTOCONPWM) (MCPWM) */ -typedef struct { /*!< (@ 0x400A0000) MCPWM Structure */ - __I uint32_t CON; /*!< (@ 0x400A0000) PWM Control read address */ - __O uint32_t CON_SET; /*!< (@ 0x400A0004) PWM Control set address */ - __O uint32_t CON_CLR; /*!< (@ 0x400A0008) PWM Control clear address */ - __I uint32_t CAPCON; /*!< (@ 0x400A000C) Capture Control read address */ - __O uint32_t CAPCON_SET; /*!< (@ 0x400A0010) Capture Control set address */ - __O uint32_t CAPCON_CLR; /*!< (@ 0x400A0014) Event Control clear address */ - __IO uint32_t TC[3]; /*!< (@ 0x400A0018) Timer Counter register */ - __IO uint32_t LIM[3]; /*!< (@ 0x400A0024) Limit register */ - __IO uint32_t MAT[3]; /*!< (@ 0x400A0030) Match register */ - __IO uint32_t DT; /*!< (@ 0x400A003C) Dead time register */ - __IO uint32_t CCP; /*!< (@ 0x400A0040) Communication Pattern register */ - __I uint32_t CAP[3]; /*!< (@ 0x400A0044) Capture register */ - __I uint32_t INTEN; /*!< (@ 0x400A0050) Interrupt Enable read address */ - __O uint32_t INTEN_SET; /*!< (@ 0x400A0054) Interrupt Enable set address */ - __O uint32_t INTEN_CLR; /*!< (@ 0x400A0058) Interrupt Enable clear address */ - __I uint32_t CNTCON; /*!< (@ 0x400A005C) Count Control read address */ - __O uint32_t CNTCON_SET; /*!< (@ 0x400A0060) Count Control set address */ - __O uint32_t CNTCON_CLR; /*!< (@ 0x400A0064) Count Control clear address */ - __I uint32_t INTF; /*!< (@ 0x400A0068) Interrupt flags read address */ - __O uint32_t INTF_SET; /*!< (@ 0x400A006C) Interrupt flags set address */ - __O uint32_t INTF_CLR; /*!< (@ 0x400A0070) Interrupt flags clear address */ - __O uint32_t CAP_CLR; /*!< (@ 0x400A0074) Capture clear address */ +typedef struct { /*!< (@ 0x400A0000) MCPWM Structure */ + __I uint32_t CON; /*!< (@ 0x400A0000) PWM Control read address */ + __O uint32_t CON_SET; /*!< (@ 0x400A0004) PWM Control set address */ + __O uint32_t CON_CLR; /*!< (@ 0x400A0008) PWM Control clear address */ + __I uint32_t CAPCON; /*!< (@ 0x400A000C) Capture Control read address */ + __O uint32_t CAPCON_SET; /*!< (@ 0x400A0010) Capture Control set address */ + __O uint32_t CAPCON_CLR; /*!< (@ 0x400A0014) Event Control clear address */ + __IO uint32_t TC0; /*!< (@ 0x400A0018) Timer Counter register */ + __IO uint32_t TC1; /*!< (@ 0x400A001C) Timer Counter register */ + __IO uint32_t TC2; /*!< (@ 0x400A0020) Timer Counter register */ + __IO uint32_t LIM0; /*!< (@ 0x400A0024) Limit register */ + __IO uint32_t LIM1; /*!< (@ 0x400A0028) Limit register */ + __IO uint32_t LIM2; /*!< (@ 0x400A002C) Limit register */ + __IO uint32_t MAT0; /*!< (@ 0x400A0030) Match register */ + __IO uint32_t MAT1; /*!< (@ 0x400A0034) Match register */ + __IO uint32_t MAT2; /*!< (@ 0x400A0038) Match register */ + __IO uint32_t DT; /*!< (@ 0x400A003C) Dead time register */ + __IO uint32_t CCP; /*!< (@ 0x400A0040) Communication Pattern register */ + __I uint32_t CAP0; /*!< (@ 0x400A0044) Capture register */ + __I uint32_t CAP1; /*!< (@ 0x400A0048) Capture register */ + __I uint32_t CAP2; /*!< (@ 0x400A004C) Capture register */ + __I uint32_t INTEN; /*!< (@ 0x400A0050) Interrupt Enable read address */ + __O uint32_t INTEN_SET; /*!< (@ 0x400A0054) Interrupt Enable set address */ + __O uint32_t INTEN_CLR; /*!< (@ 0x400A0058) Interrupt Enable clear address */ + __I uint32_t CNTCON; /*!< (@ 0x400A005C) Count Control read address */ + __O uint32_t CNTCON_SET; /*!< (@ 0x400A0060) Count Control set address */ + __O uint32_t CNTCON_CLR; /*!< (@ 0x400A0064) Count Control clear address */ + __I uint32_t INTF; /*!< (@ 0x400A0068) Interrupt flags read address */ + __O uint32_t INTF_SET; /*!< (@ 0x400A006C) Interrupt flags set address */ + __O uint32_t INTF_CLR; /*!< (@ 0x400A0070) Interrupt flags clear address */ + __O uint32_t CAP_CLR; /*!< (@ 0x400A0074) Capture clear address */ } LPC_MCPWM_Type; -// ------------------------------------------------------------------------------------------------ -// ----- I2C0 ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ I2Cn [I2C0] ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx I2C-bus interface Modification date=1/14/2011 Major revision=0 Minor revision=7 (I2Cn) + * @brief I2C-bus interface (I2Cn) */ -typedef struct { /*!< (@ 0x400xx000) I2C0 Structure */ - __IO uint32_t CONSET; /*!< (@ 0x400xx000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */ - __I uint32_t STAT; /*!< (@ 0x400xx004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */ - __IO uint32_t DAT; /*!< (@ 0x400xx008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */ - __IO uint32_t ADR0; /*!< (@ 0x400xx00C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ - __IO uint32_t SCLH; /*!< (@ 0x400xx010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */ - __IO uint32_t SCLL; /*!< (@ 0x400xx014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */ - __O uint32_t CONCLR; /*!< (@ 0x400xx018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */ - __IO uint32_t MMCTRL; /*!< (@ 0x400xx01C) Monitor mode control register. */ - __IO uint32_t ADR1; /*!< (@ 0x400xx020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ - __IO uint32_t ADR2; /*!< (@ 0x400xx024) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ - __IO uint32_t ADR3; /*!< (@ 0x400xx028) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ - __I uint32_t DATA_BUFFER; /*!< (@ 0x400xx02C) Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */ - __IO uint32_t MASK[4]; /*!< (@ 0x400xx030) I2C Slave address mask register */ +typedef struct { /*!< (@ 0x400A1000) I2Cn Structure */ + __IO uint32_t CONSET; /*!< (@ 0x400A1000) I2C Control Set Register. When a one is written + to a bit of this register, the corresponding bit in the I2C + control register is set. Writing a zero has no effect on the + corresponding bit in the I2C control register. */ + __I uint32_t STAT; /*!< (@ 0x400A1004) I2C Status Register. During I2C operation, this + register provides detailed status codes that allow software + to determine the next action needed. */ + __IO uint32_t DAT; /*!< (@ 0x400A1008) I2C Data Register. During master or slave transmit + mode, data to be transmitted is written to this register. During + master or slave receive mode, data that has been received may + be read from this register. */ + __IO uint32_t ADR0; /*!< (@ 0x400A100C) I2C Slave Address Register 0. Contains the 7-bit + slave address for operation of the I2C interface in slave mode, + and is not used in master mode. The least significant bit determines + whether a slave responds to the General Call address. */ + __IO uint32_t SCLH; /*!< (@ 0x400A1010) SCH Duty Cycle Register High Half Word. Determines + the high time of the I2C clock. */ + __IO uint32_t SCLL; /*!< (@ 0x400A1014) SCL Duty Cycle Register Low Half Word. Determines + the low time of the I2C clock. SCLL and SCLH together determine + the clock frequency generated by an I2C master and certain times + used in slave mode. */ + __O uint32_t CONCLR; /*!< (@ 0x400A1018) I2C Control Clear Register. When a one is written + to a bit of this register, the corresponding bit in the I2C + control register is cleared. Writing a zero has no effect on + the corresponding bit in the I2C control register. */ + __IO uint32_t MMCTRL; /*!< (@ 0x400A101C) Monitor mode control register. */ + __IO uint32_t ADR1; /*!< (@ 0x400A1020) I2C Slave Address Register. Contains the 7-bit + slave address for operation of the I2C interface in slave mode, + and is not used in master mode. The least significant bit determines + whether a slave responds to the General Call address. */ + __IO uint32_t ADR2; /*!< (@ 0x400A1024) I2C Slave Address Register. Contains the 7-bit + slave address for operation of the I2C interface in slave mode, + and is not used in master mode. The least significant bit determines + whether a slave responds to the General Call address. */ + __IO uint32_t ADR3; /*!< (@ 0x400A1028) I2C Slave Address Register. Contains the 7-bit + slave address for operation of the I2C interface in slave mode, + and is not used in master mode. The least significant bit determines + whether a slave responds to the General Call address. */ + __I uint32_t DATA_BUFFER; /*!< (@ 0x400A102C) Data buffer register. The contents of the 8 MSBs + of the DAT shift register will be transferred to the DATA_BUFFER + automatically after every nine bits (8 bits of data plus ACK + or NACK) has been received on the bus. */ + __IO uint32_t MASK0; /*!< (@ 0x400A1030) I2C Slave address mask register */ + __IO uint32_t MASK1; /*!< (@ 0x400A1034) I2C Slave address mask register */ + __IO uint32_t MASK2; /*!< (@ 0x400A1038) I2C Slave address mask register */ + __IO uint32_t MASK3; /*!< (@ 0x400A103C) I2C Slave address mask register */ } LPC_I2Cn_Type; -// ------------------------------------------------------------------------------------------------ -// ----- I2Sn ----- -// ------------------------------------------------------------------------------------------------ + +/* ================================================================================ */ +/* ================ I2Sn [I2S0] ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx I2S interface Modification date=1/14/2011 Major revision=0 Minor revision=7 (I2Sn) - 0x400A2000 / 0x400A3000 + * @brief I2S interface (I2Sn) */ -typedef struct { /*!< (@ 0x400Ax000) I2S Structure */ - __IO uint32_t DAO; /*!< (@ 0x400Ax000) I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel. */ - __IO uint32_t DAI; /*!< (@ 0x400Ax004) I2S Digital Audio Input Register. Contains control bits for the I2S receive channel. */ - __O uint32_t TXFIFO; /*!< (@ 0x400Ax008) I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. */ - __I uint32_t RXFIFO; /*!< (@ 0x400Ax00C) I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. */ - __I uint32_t STATE; /*!< (@ 0x400Ax010) I2S Status Feedback Register. Contains status information about the I2S interface. */ - __IO uint32_t DMA1; /*!< (@ 0x400Ax014) I2S DMA Configuration Register 1. Contains control information for DMA request 1. */ - __IO uint32_t DMA2; /*!< (@ 0x400Ax018) I2S DMA Configuration Register 2. Contains control information for DMA request 2. */ - __IO uint32_t IRQ; /*!< (@ 0x400Ax01C) I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated. */ - __IO uint32_t TXRATE; /*!< (@ 0x400Ax020) I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */ - __IO uint32_t RXRATE; /*!< (@ 0x400Ax024) I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */ - __IO uint32_t TXBITRATE; /*!< (@ 0x400Ax028) I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock. */ - __IO uint32_t RXBITRATE; /*!< (@ 0x400Ax02C) I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock. */ - __IO uint32_t TXMODE; /*!< (@ 0x400Ax030) I2S Transmit mode control. */ - __IO uint32_t RXMODE; /*!< (@ 0x400Ax034) I2S Receive mode control. */ +typedef struct { /*!< (@ 0x400A2000) I2Sn Structure */ + __IO uint32_t DAO; /*!< (@ 0x400A2000) I2S Digital Audio Output Register. Contains control + bits for the I2S transmit channel. */ + __IO uint32_t DAI; /*!< (@ 0x400A2004) I2S Digital Audio Input Register. Contains control + bits for the I2S receive channel. */ + __O uint32_t TXFIFO; /*!< (@ 0x400A2008) I2S Transmit FIFO. Access register for the 8 + x 32-bit transmitter FIFO. */ + __I uint32_t RXFIFO; /*!< (@ 0x400A200C) I2S Receive FIFO. Access register for the 8 x + 32-bit receiver FIFO. */ + __I uint32_t STATE; /*!< (@ 0x400A2010) I2S Status Feedback Register. Contains status + information about the I2S interface. */ + __IO uint32_t DMA1; /*!< (@ 0x400A2014) I2S DMA Configuration Register 1. Contains control + information for DMA request 1. */ + __IO uint32_t DMA2; /*!< (@ 0x400A2018) I2S DMA Configuration Register 2. Contains control + information for DMA request 2. */ + __IO uint32_t IRQ; /*!< (@ 0x400A201C) I2S Interrupt Request Control Register. Contains + bits that control how the I2S interrupt request is generated. */ + __IO uint32_t TXRATE; /*!< (@ 0x400A2020) I2S Transmit MCLK divider. This register determines + the I2S TX MCLK rate by specifying the value to divide PCLK + by in order to produce MCLK. */ + __IO uint32_t RXRATE; /*!< (@ 0x400A2024) I2S Receive MCLK divider. This register determines + the I2S RX MCLK rate by specifying the value to divide PCLK + by in order to produce MCLK. */ + __IO uint32_t TXBITRATE; /*!< (@ 0x400A2028) I2S Transmit bit rate divider. This register + determines the I2S transmit bit rate by specifying the value + to divide TX_MCLK by in order to produce the transmit bit clock. */ + __IO uint32_t RXBITRATE; /*!< (@ 0x400A202C) I2S Receive bit rate divider. This register determines + the I2S receive bit rate by specifying the value to divide RX_MCLK + by in order to produce the receive bit clock. */ + __IO uint32_t TXMODE; /*!< (@ 0x400A2030) I2S Transmit mode control. */ + __IO uint32_t RXMODE; /*!< (@ 0x400A2034) I2S Receive mode control. */ } LPC_I2Sn_Type; -// ------------------------------------------------------------------------------------------------ -// ----- C_CANn ----- -// ------------------------------------------------------------------------------------------------ + +/* ================================================================================ */ +/* ================ C_CANn [C_CAN1] ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx C_CAN Modification date=1/18/2011 Major revision=0 Minor revision=7 (C_CANn) - 0x400A4000 / 0x400E2000 + * @brief C_CAN (C_CANn) */ -typedef struct { /*!< (@ 0x400E2000) C_CAN Structure */ - __IO uint32_t CNTL; /*!< (@ 0x400E2000) CAN control */ - __IO uint32_t STAT; /*!< (@ 0x400E2004) Status register */ - __I uint32_t EC; /*!< (@ 0x400E2008) Error counter */ - __IO uint32_t BT; /*!< (@ 0x400E200C) Bit timing register */ - __I uint32_t INT; /*!< (@ 0x400E2010) Interrupt register */ - __IO uint32_t TEST; /*!< (@ 0x400E2014) Test register */ - __IO uint32_t BRPE; /*!< (@ 0x400E2018) Baud rate prescaler extension register */ +typedef struct { /*!< (@ 0x400A4000) C_CANn Structure */ + __IO uint32_t CNTL; /*!< (@ 0x400A4000) CAN control */ + __IO uint32_t STAT; /*!< (@ 0x400A4004) Status register */ + __I uint32_t EC; /*!< (@ 0x400A4008) Error counter */ + __IO uint32_t BT; /*!< (@ 0x400A400C) Bit timing register */ + __I uint32_t INT; /*!< (@ 0x400A4010) Interrupt register */ + __IO uint32_t TEST; /*!< (@ 0x400A4014) Test register */ + __IO uint32_t BRPE; /*!< (@ 0x400A4018) Baud rate prescaler extension register */ __I uint32_t RESERVED0; - __IO uint32_t IF1_CMDREQ; /*!< (@ 0x400E2020) Message interface command request */ - + __IO uint32_t IF1_CMDREQ; /*!< (@ 0x400A4020) Message interface command request */ + union { - __IO uint32_t IF1_CMDMSK_R; /*!< (@ 0x400E2024) Message interface command mask (read direction) */ - __IO uint32_t IF1_CMDMSK_W; /*!< (@ 0x400E2024) Message interface command mask (write direction) */ - } ; - __IO uint32_t IF1_MSK1; /*!< (@ 0x400E2028) Message interface mask 1 */ - __IO uint32_t IF1_MSK2; /*!< (@ 0x400E202C) Message interface 1 mask 2 */ - __IO uint32_t IF1_ARB1; /*!< (@ 0x400E2030) Message interface 1 arbitration 1 */ - __IO uint32_t IF1_ARB2; /*!< (@ 0x400E2034) Message interface 1 arbitration 2 */ - __IO uint32_t IF1_MCTRL; /*!< (@ 0x400E2038) Message interface 1 message control */ - __IO uint32_t IF1_DA1; /*!< (@ 0x400E203C) Message interface data A1 */ - __IO uint32_t IF1_DA2; /*!< (@ 0x400E2040) Message interface 1 data A2 */ - __IO uint32_t IF1_DB1; /*!< (@ 0x400E2044) Message interface 1 data B1 */ - __IO uint32_t IF1_DB2; /*!< (@ 0x400E2048) Message interface 1 data B2 */ + __IO uint32_t IF1_CMDMSK_R; /*!< (@ 0x400A4024) Message interface command mask (read direction) */ + __IO uint32_t IF1_CMDMSK_W; /*!< (@ 0x400A4024) Message interface command mask (write direction) */ + }; + __IO uint32_t IF1_MSK1; /*!< (@ 0x400A4028) Message interface mask 1 */ + __IO uint32_t IF1_MSK2; /*!< (@ 0x400A402C) Message interface 1 mask 2 */ + __IO uint32_t IF1_ARB1; /*!< (@ 0x400A4030) Message interface 1 arbitration 1 */ + __IO uint32_t IF1_ARB2; /*!< (@ 0x400A4034) Message interface 1 arbitration 2 */ + __IO uint32_t IF1_MCTRL; /*!< (@ 0x400A4038) Message interface 1 message control */ + __IO uint32_t IF1_DA1; /*!< (@ 0x400A403C) Message interface data A1 */ + __IO uint32_t IF1_DA2; /*!< (@ 0x400A4040) Message interface 1 data A2 */ + __IO uint32_t IF1_DB1; /*!< (@ 0x400A4044) Message interface 1 data B1 */ + __IO uint32_t IF1_DB2; /*!< (@ 0x400A4048) Message interface 1 data B2 */ __I uint32_t RESERVED1[13]; - __IO uint32_t IF2_CMDREQ; /*!< (@ 0x400E2080) Message interface command request */ - + __IO uint32_t IF2_CMDREQ; /*!< (@ 0x400A4080) Message interface command request */ + union { - __IO uint32_t IF2_CMDMSK_R; /*!< (@ 0x400E2084) Message interface command mask (read direction) */ - __IO uint32_t IF2_CMDMSK_W; /*!< (@ 0x400E2084) Message interface command mask (write direction) */ - } ; - __IO uint32_t IF2_MSK1; /*!< (@ 0x400E2088) Message interface mask 1 */ - __IO uint32_t IF2_MSK2; /*!< (@ 0x400E208C) Message interface 1 mask 2 */ - __IO uint32_t IF2_ARB1; /*!< (@ 0x400E2090) Message interface 1 arbitration 1 */ - __IO uint32_t IF2_ARB2; /*!< (@ 0x400E2094) Message interface 1 arbitration 2 */ - __IO uint32_t IF2_MCTRL; /*!< (@ 0x400E2098) Message interface 1 message control */ - __IO uint32_t IF2_DA1; /*!< (@ 0x400E209C) Message interface data A1 */ - __IO uint32_t IF2_DA2; /*!< (@ 0x400E20A0) Message interface 1 data A2 */ - __IO uint32_t IF2_DB1; /*!< (@ 0x400E20A4) Message interface 1 data B1 */ - __IO uint32_t IF2_DB2; /*!< (@ 0x400E20A8) Message interface 1 data B2 */ + __IO uint32_t IF2_CMDMSK_R; /*!< (@ 0x400A4084) Message interface command mask (read direction) */ + __IO uint32_t IF2_CMDMSK_W; /*!< (@ 0x400A4084) Message interface command mask (write direction) */ + }; + __IO uint32_t IF2_MSK1; /*!< (@ 0x400A4088) Message interface mask 1 */ + __IO uint32_t IF2_MSK2; /*!< (@ 0x400A408C) Message interface 1 mask 2 */ + __IO uint32_t IF2_ARB1; /*!< (@ 0x400A4090) Message interface 1 arbitration 1 */ + __IO uint32_t IF2_ARB2; /*!< (@ 0x400A4094) Message interface 1 arbitration 2 */ + __IO uint32_t IF2_MCTRL; /*!< (@ 0x400A4098) Message interface 1 message control */ + __IO uint32_t IF2_DA1; /*!< (@ 0x400A409C) Message interface data A1 */ + __IO uint32_t IF2_DA2; /*!< (@ 0x400A40A0) Message interface 1 data A2 */ + __IO uint32_t IF2_DB1; /*!< (@ 0x400A40A4) Message interface 1 data B1 */ + __IO uint32_t IF2_DB2; /*!< (@ 0x400A40A8) Message interface 1 data B2 */ __I uint32_t RESERVED2[21]; - __I uint32_t TXREQ1; /*!< (@ 0x400E2100) Transmission request 1 */ - __I uint32_t TXREQ2; /*!< (@ 0x400E2104) Transmission request 2 */ + __I uint32_t TXREQ1; /*!< (@ 0x400A4100) Transmission request 1 */ + __I uint32_t TXREQ2; /*!< (@ 0x400A4104) Transmission request 2 */ __I uint32_t RESERVED3[6]; - __I uint32_t ND1; /*!< (@ 0x400E2120) New data 1 */ - __I uint32_t ND2; /*!< (@ 0x400E2124) New data 2 */ + __I uint32_t ND1; /*!< (@ 0x400A4120) New data 1 */ + __I uint32_t ND2; /*!< (@ 0x400A4124) New data 2 */ __I uint32_t RESERVED4[6]; - __I uint32_t IR1; /*!< (@ 0x400E2140) Interrupt pending 1 */ - __I uint32_t IR2; /*!< (@ 0x400E2144) Interrupt pending 2 */ + __I uint32_t IR1; /*!< (@ 0x400A4140) Interrupt pending 1 */ + __I uint32_t IR2; /*!< (@ 0x400A4144) Interrupt pending 2 */ __I uint32_t RESERVED5[6]; - __I uint32_t MSGV1; /*!< (@ 0x400E2160) Message valid 1 */ - __I uint32_t MSGV2; /*!< (@ 0x400E2164) Message valid 2 */ + __I uint32_t MSGV1; /*!< (@ 0x400A4160) Message valid 1 */ + __I uint32_t MSGV2; /*!< (@ 0x400A4164) Message valid 2 */ __I uint32_t RESERVED6[6]; - __IO uint32_t CLKDIV; /*!< (@ 0x400E2180) CAN clock divider register */ + __IO uint32_t CLKDIV; /*!< (@ 0x400A4180) CAN clock divider register */ } LPC_C_CANn_Type; -// ------------------------------------------------------------------------------------------------ -// ----- RITIMER ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ RITIMER ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx Repetitive Interrupt Timer (RIT) Modification date=1/14/2011 Major revision=0 Minor revision=7 (RITIMER) + * @brief Repetitive Interrupt Timer (RIT) (RITIMER) */ -typedef struct { /*!< (@ 0x400C0000) RITIMER Structure */ - __IO uint32_t COMPVAL; /*!< (@ 0x400C0000) Compare register */ - __IO uint32_t MASK; /*!< (@ 0x400C0004) Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */ - __IO uint32_t CTRL; /*!< (@ 0x400C0008) Control register. */ - __IO uint32_t COUNTER; /*!< (@ 0x400C000C) 32-bit counter */ +typedef struct { /*!< (@ 0x400C0000) RITIMER Structure */ + __IO uint32_t COMPVAL; /*!< (@ 0x400C0000) Compare register */ + __IO uint32_t MASK; /*!< (@ 0x400C0004) Mask register. This register holds the 32-bit + mask value. A 1 written to any bit will force a compare on the + corresponding bit of the counter and compare register. */ + __IO uint32_t CTRL; /*!< (@ 0x400C0008) Control register. */ + __IO uint32_t COUNTER; /*!< (@ 0x400C000C) 32-bit counter */ } LPC_RITIMER_Type; -// ------------------------------------------------------------------------------------------------ -// ----- QEI ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ QEI ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx Quadrature Encoder Interface (QEI) Modification date=1/18/2011 Major revision=0 Minor revision=7 (QEI) + * @brief Quadrature Encoder Interface (QEI) (QEI) */ -typedef struct { /*!< (@ 0x400C6000) QEI Structure */ - __O uint32_t CON; /*!< (@ 0x400C6000) Control register */ - __I uint32_t STAT; /*!< (@ 0x400C6004) Encoder status register */ - __IO uint32_t CONF; /*!< (@ 0x400C6008) Configuration register */ - __I uint32_t POS; /*!< (@ 0x400C600C) Position register */ - __IO uint32_t MAXPOS; /*!< (@ 0x400C6010) Maximum position register */ - __IO uint32_t CMPOS0; /*!< (@ 0x400C6014) position compare register 0 */ - __IO uint32_t CMPOS1; /*!< (@ 0x400C6018) position compare register 1 */ - __IO uint32_t CMPOS2; /*!< (@ 0x400C601C) position compare register 2 */ - __I uint32_t INXCNT; /*!< (@ 0x400C6020) Index count register */ - __IO uint32_t INXCMP0; /*!< (@ 0x400C6024) Index compare register 0 */ - __IO uint32_t LOAD; /*!< (@ 0x400C6028) Velocity timer reload register */ - __I uint32_t TIME; /*!< (@ 0x400C602C) Velocity timer register */ - __I uint32_t VEL; /*!< (@ 0x400C6030) Velocity counter register */ - __I uint32_t CAP; /*!< (@ 0x400C6034) Velocity capture register */ - __IO uint32_t VELCOMP; /*!< (@ 0x400C6038) Velocity compare register */ - __IO uint32_t FILTERPHA; /*!< (@ 0x400C603C) Digital filter register on input phase A (QEI_A) */ - __IO uint32_t FILTERPHB; /*!< (@ 0x400C6040) Digital filter register on input phase B (QEI_B) */ - __IO uint32_t FILTERINX; /*!< (@ 0x400C6044) Digital filter register on input index (QEI_IDX) */ - __IO uint32_t WINDOW; /*!< (@ 0x400C6048) Index acceptance window register */ - __IO uint32_t INXCMP1; /*!< (@ 0x400C604C) Index compare register 1 */ - __IO uint32_t INXCMP2; /*!< (@ 0x400C6050) Index compare register 2 */ +typedef struct { /*!< (@ 0x400C6000) QEI Structure */ + __O uint32_t CON; /*!< (@ 0x400C6000) Control register */ + __I uint32_t STAT; /*!< (@ 0x400C6004) Encoder status register */ + __IO uint32_t CONF; /*!< (@ 0x400C6008) Configuration register */ + __I uint32_t POS; /*!< (@ 0x400C600C) Position register */ + __IO uint32_t MAXPOS; /*!< (@ 0x400C6010) Maximum position register */ + __IO uint32_t CMPOS0; /*!< (@ 0x400C6014) position compare register 0 */ + __IO uint32_t CMPOS1; /*!< (@ 0x400C6018) position compare register 1 */ + __IO uint32_t CMPOS2; /*!< (@ 0x400C601C) position compare register 2 */ + __I uint32_t INXCNT; /*!< (@ 0x400C6020) Index count register */ + __IO uint32_t INXCMP0; /*!< (@ 0x400C6024) Index compare register 0 */ + __IO uint32_t LOAD; /*!< (@ 0x400C6028) Velocity timer reload register */ + __I uint32_t TIME; /*!< (@ 0x400C602C) Velocity timer register */ + __I uint32_t VEL; /*!< (@ 0x400C6030) Velocity counter register */ + __I uint32_t CAP; /*!< (@ 0x400C6034) Velocity capture register */ + __IO uint32_t VELCOMP; /*!< (@ 0x400C6038) Velocity compare register */ + __IO uint32_t FILTERPHA; /*!< (@ 0x400C603C) Digital filter register on input phase A (QEI_A) */ + __IO uint32_t FILTERPHB; /*!< (@ 0x400C6040) Digital filter register on input phase B (QEI_B) */ + __IO uint32_t FILTERINX; /*!< (@ 0x400C6044) Digital filter register on input index (QEI_IDX) */ + __IO uint32_t WINDOW; /*!< (@ 0x400C6048) Index acceptance window register */ + __IO uint32_t INXCMP1; /*!< (@ 0x400C604C) Index compare register 1 */ + __IO uint32_t INXCMP2; /*!< (@ 0x400C6050) Index compare register 2 */ __I uint32_t RESERVED0[993]; - __O uint32_t IEC; /*!< (@ 0x400C6FD8) Interrupt enable clear register */ - __O uint32_t IES; /*!< (@ 0x400C6FDC) Interrupt enable set register */ - __I uint32_t INTSTAT; /*!< (@ 0x400C6FE0) Interrupt status register */ - __I uint32_t IE; /*!< (@ 0x400C6FE4) Interrupt enable register */ - __O uint32_t CLR; /*!< (@ 0x400C6FE8) Interrupt status clear register */ - __O uint32_t SET; /*!< (@ 0x400C6FEC) Interrupt status set register */ + __O uint32_t IEC; /*!< (@ 0x400C6FD8) Interrupt enable clear register */ + __O uint32_t IES; /*!< (@ 0x400C6FDC) Interrupt enable set register */ + __I uint32_t INTSTAT; /*!< (@ 0x400C6FE0) Interrupt status register */ + __I uint32_t IE; /*!< (@ 0x400C6FE4) Interrupt enable register */ + __O uint32_t CLR; /*!< (@ 0x400C6FE8) Interrupt status clear register */ + __O uint32_t SET; /*!< (@ 0x400C6FEC) Interrupt status set register */ } LPC_QEI_Type; -// ------------------------------------------------------------------------------------------------ -// ----- GIMA ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ GIMA ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10503 Chapter title=LPC43xx Global Input Multiplexer Array (GIMA) Modification date=10/7/2011 Major revision=0 Minor revision=3 (GIMA) + * @brief Global Input Multiplexer Array (GIMA) (GIMA) */ -typedef struct { /*!< (@ 0x400C7000) GIMA Structure */ - __IO uint32_t CAP0_0_IN; /*!< (@ 0x400C7000) Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */ - __IO uint32_t CAP0_1_IN; /*!< (@ 0x400C7004) Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */ - __IO uint32_t CAP0_2_IN; /*!< (@ 0x400C7008) Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */ - __IO uint32_t CAP0_3_IN; /*!< (@ 0x400C700C) Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) */ - __IO uint32_t CAP1_0_IN; /*!< (@ 0x400C7010) Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) */ - __IO uint32_t CAP1_1_IN; /*!< (@ 0x400C7014) Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) */ - __IO uint32_t CAP1_2_IN; /*!< (@ 0x400C7018) Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) */ - __IO uint32_t CAP1_3_IN; /*!< (@ 0x400C701C) Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) */ - __IO uint32_t CAP2_0_IN; /*!< (@ 0x400C7020) Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) */ - __IO uint32_t CAP2_1_IN; /*!< (@ 0x400C7024) Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) */ - __IO uint32_t CAP2_2_IN; /*!< (@ 0x400C7028) Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) */ - __IO uint32_t CAP2_3_IN; /*!< (@ 0x400C702C) Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) */ - __IO uint32_t CAP3_0_IN; /*!< (@ 0x400C7030) Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) */ - __IO uint32_t CAP3_1_IN; /*!< (@ 0x400C7034) Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) */ - __IO uint32_t CAP3_2_IN; /*!< (@ 0x400C7038) Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */ - __IO uint32_t CAP3_3_IN; /*!< (@ 0x400C703C) Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */ - __IO uint32_t CTIN_0_IN; /*!< (@ 0x400C7040) SCT CTIN_0 capture input multiplexer (GIMA output 16) */ - __IO uint32_t CTIN_1_IN; /*!< (@ 0x400C7044) SCT CTIN_1 capture input multiplexer (GIMA output 17) */ - __IO uint32_t CTIN_2_IN; /*!< (@ 0x400C7048) SCT CTIN_2 capture input multiplexer (GIMA output 18) */ - __IO uint32_t CTIN_3_IN; /*!< (@ 0x400C704C) SCT CTIN_3 capture input multiplexer (GIMA output 19) */ - __IO uint32_t CTIN_4_IN; /*!< (@ 0x400C7050) SCT CTIN_4 capture input multiplexer (GIMA output 20) */ - __IO uint32_t CTIN_5_IN; /*!< (@ 0x400C7054) SCT CTIN_5 capture input multiplexer (GIMA output 21) */ - __IO uint32_t CTIN_6_IN; /*!< (@ 0x400C7058) SCT CTIN_6 capture input multiplexer (GIMA output 22) */ - __IO uint32_t CTIN_7_IN; /*!< (@ 0x400C705C) SCT CTIN_7 capture input multiplexer (GIMA output 23) */ - __IO uint32_t VADC_TRIGGER_IN; /*!< (@ 0x400C7060) VADC trigger input multiplexer (GIMA output 24) */ - __IO uint32_t EVENTROUTER_13_IN; /*!< (@ 0x400C7064) Event router input 13 multiplexer (GIMA output 25) */ - __IO uint32_t EVENTROUTER_14_IN; /*!< (@ 0x400C7068) Event router input 14 multiplexer (GIMA output 26) */ - __IO uint32_t EVENTROUTER_16_IN; /*!< (@ 0x400C706C) Event router input 16 multiplexer (GIMA output 27) */ - __IO uint32_t ADCSTART0_IN; /*!< (@ 0x400C7070) ADC start0 input multiplexer (GIMA output 28) */ - __IO uint32_t ADCSTART1_IN; /*!< (@ 0x400C7074) ADC start1 input multiplexer (GIMA output 29) */ +typedef struct { /*!< (@ 0x400C7000) GIMA Structure */ + __IO uint32_t CAP0_0_IN; /*!< (@ 0x400C7000) Timer 0 CAP0_0 capture input multiplexer (GIMA + output 0) */ + __IO uint32_t CAP0_1_IN; /*!< (@ 0x400C7004) Timer 0 CAP0_1 capture input multiplexer (GIMA + output 1) */ + __IO uint32_t CAP0_2_IN; /*!< (@ 0x400C7008) Timer 0 CAP0_2 capture input multiplexer (GIMA + output 2) */ + __IO uint32_t CAP0_3_IN; /*!< (@ 0x400C700C) Timer 0 CAP0_3 capture input multiplexer (GIMA + output 3) */ + __IO uint32_t CAP1_0_IN; /*!< (@ 0x400C7010) Timer 1 CAP1_0 capture input multiplexer (GIMA + output 4) */ + __IO uint32_t CAP1_1_IN; /*!< (@ 0x400C7014) Timer 1 CAP1_1 capture input multiplexer (GIMA + output 5) */ + __IO uint32_t CAP1_2_IN; /*!< (@ 0x400C7018) Timer 1 CAP1_2 capture input multiplexer (GIMA + output 6) */ + __IO uint32_t CAP1_3_IN; /*!< (@ 0x400C701C) Timer 1 CAP1_3 capture input multiplexer (GIMA + output 7) */ + __IO uint32_t CAP2_0_IN; /*!< (@ 0x400C7020) Timer 2 CAP2_0 capture input multiplexer (GIMA + output 8) */ + __IO uint32_t CAP2_1_IN; /*!< (@ 0x400C7024) Timer 2 CAP2_1 capture input multiplexer (GIMA + output 9) */ + __IO uint32_t CAP2_2_IN; /*!< (@ 0x400C7028) Timer 2 CAP2_2 capture input multiplexer (GIMA + output 10) */ + __IO uint32_t CAP2_3_IN; /*!< (@ 0x400C702C) Timer 2 CAP2_3 capture input multiplexer (GIMA + output 11) */ + __IO uint32_t CAP3_0_IN; /*!< (@ 0x400C7030) Timer 3 CAP3_0 capture input multiplexer (GIMA + output 12) */ + __IO uint32_t CAP3_1_IN; /*!< (@ 0x400C7034) Timer 3 CAP3_1 capture input multiplexer (GIMA + output 13) */ + __IO uint32_t CAP3_2_IN; /*!< (@ 0x400C7038) Timer 3 CAP3_2 capture input multiplexer (GIMA + output 14) */ + __IO uint32_t CAP3_3_IN; /*!< (@ 0x400C703C) Timer 3 CAP3_3 capture input multiplexer (GIMA + output 15) */ + __IO uint32_t CTIN_0_IN; /*!< (@ 0x400C7040) SCT CTIN_0 capture input multiplexer (GIMA output + 16) */ + __IO uint32_t CTIN_1_IN; /*!< (@ 0x400C7044) SCT CTIN_1 capture input multiplexer (GIMA output + 17) */ + __IO uint32_t CTIN_2_IN; /*!< (@ 0x400C7048) SCT CTIN_2 capture input multiplexer (GIMA output + 18) */ + __IO uint32_t CTIN_3_IN; /*!< (@ 0x400C704C) SCT CTIN_3 capture input multiplexer (GIMA output + 19) */ + __IO uint32_t CTIN_4_IN; /*!< (@ 0x400C7050) SCT CTIN_4 capture input multiplexer (GIMA output + 20) */ + __IO uint32_t CTIN_5_IN; /*!< (@ 0x400C7054) SCT CTIN_5 capture input multiplexer (GIMA output + 21) */ + __IO uint32_t CTIN_6_IN; /*!< (@ 0x400C7058) SCT CTIN_6 capture input multiplexer (GIMA output + 22) */ + __IO uint32_t CTIN_7_IN; /*!< (@ 0x400C705C) SCT CTIN_7 capture input multiplexer (GIMA output + 23) */ + __IO uint32_t ADCHS_TRIGGER_IN; /*!< (@ 0x400C7060) ADCHS trigger input multiplexer (GIMA output + 24) */ + __IO uint32_t EVENTROUTER_13_IN; /*!< (@ 0x400C7064) Event router input 13 multiplexer (GIMA output + 25) */ + __IO uint32_t EVENTROUTER_14_IN; /*!< (@ 0x400C7068) Event router input 14 multiplexer (GIMA output + 26) */ + __IO uint32_t EVENTROUTER_16_IN; /*!< (@ 0x400C706C) Event router input 16 multiplexer (GIMA output + 27) */ + __IO uint32_t ADCSTART0_IN; /*!< (@ 0x400C7070) ADC start0 input multiplexer (GIMA output 28) */ + __IO uint32_t ADCSTART1_IN; /*!< (@ 0x400C7074) ADC start1 input multiplexer (GIMA output 29) */ } LPC_GIMA_Type; -// ------------------------------------------------------------------------------------------------ -// ----- DAC ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ DAC ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx DAC Modification date=1/18/2011 Major revision=0 Minor revision=7 (DAC) + * @brief Digital-to-Analog Converter (DAC) (DAC) */ -typedef struct { /*!< (@ 0x400E1000) DAC Structure */ - __IO uint32_t CR; /*!< (@ 0x400E1000) DAC register. Holds the conversion data. */ - __IO uint32_t CTRL; /*!< (@ 0x400E1004) DAC control register. */ - __IO uint32_t CNTVAL; /*!< (@ 0x400E1008) DAC counter value register. */ +typedef struct { /*!< (@ 0x400E1000) DAC Structure */ + __IO uint32_t CR; /*!< (@ 0x400E1000) DAC register. Holds the conversion data. */ + __IO uint32_t CTRL; /*!< (@ 0x400E1004) DAC control register. */ + __IO uint32_t CNTVAL; /*!< (@ 0x400E1008) DAC counter value register. */ } LPC_DAC_Type; - -// ------------------------------------------------------------------------------------------------ -// ----- ADCn ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ ADCn [ADC0] ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10430 Chapter title=LPC18xx 10-bit ADC0/1 Modification date=1/18/2011 Major revision=0 Minor revision=7 (ADCn) - 0x400E3000 / 0x400E4000 + * @brief 10-bit Analog-to-Digital Converter (ADC) (ADCn) */ -typedef struct { /*!< (@ 0x400Ex000) ADCn Structure */ - __IO uint32_t CR; /*!< (@ 0x400Ex000) A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */ - __I uint32_t GDR; /*!< (@ 0x400Ex004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */ +typedef struct { /*!< (@ 0x400E3000) ADCn Structure */ + __IO uint32_t CR; /*!< (@ 0x400E3000) A/D Control Register. The AD0CR register must + be written to select the operating mode before A/D conversion + can occur. */ + __I uint32_t GDR; /*!< (@ 0x400E3004) A/D Global Data Register. Contains the result + of the most recent A/D conversion. */ __I uint32_t RESERVED0; - __IO uint32_t INTEN; /*!< (@ 0x400Ex00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */ - __I uint32_t DR[8]; /*!< (@ 0x400Ex010) A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */ - __I uint32_t STAT; /*!< (@ 0x400Ex030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */ + __IO uint32_t INTEN; /*!< (@ 0x400E300C) A/D Interrupt Enable Register. This register + contains enable bits that allow the DONE flag of each A/D channel + to be included or excluded from contributing to the generation + of an A/D interrupt. */ + __I uint32_t DR[8]; /*!< (@ 0x400E3010) A/D Channel Data Register. This register contains + the result of the most recent conversion completed on channel + n. */ + __I uint32_t STAT; /*!< (@ 0x400E3030) A/D Status Register. This register contains DONE + and OVERRUN flags for all of the A/D channels, as well as the + A/D interrupt flag. */ } LPC_ADCn_Type; -// ------------------------------------------------------------------------------------------------ -// ----- VADC ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ ADCHS ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM????? Chapter title=?????? Modification date=12/11/2012 Major revision=? Minor revision=? (VADC) - 0x400F0000 + * @brief 12-bit Analog-to-Digital Converter High-Speed (ADCHS) (ADCHS) */ -typedef struct { /*!< (@ 0x400F0000) VADC Structure */ - __O uint32_t FLUSH; /*!< (@ 0x400F0000) Flushes FIFO */ - __IO uint32_t DMA_REQ; /*!< (@ 0x400F0004) Set or clear DMA write request */ - __I uint32_t FIFO_STS; /*!< (@ 0x400F0008) Indicates FIFO fullness status */ - __IO uint32_t FIFO_CFG; /*!< (@ 0x400F000C) Configures FIFO fullness level that triggers interrupt and packing 1 or 2 samples per word. */ - __O uint32_t TRIGGER; /*!< (@ 0x400F0010) Enable software trigger to start descriptor processing */ - __IO uint32_t DSCR_STS; /*!< (@ 0x400F0014) Indicates active descriptor table and descriptor entry */ - __IO uint32_t POWER_DOWN; /*!< (@ 0x400F0018) Set or clear power down mode */ - __IO uint32_t CONFIG; /*!< (@ 0x400F001C) Configures external trigger mode, store channel ID in FIFO and wakeup recovery time from power down. */ - __IO uint32_t THR_A; /*!< (@ 0x400F0020) Configures window comparator A levels. */ - __IO uint32_t THR_B; /*!< (@ 0x400F0024) Configures window comparator B levels. */ - __I uint32_t LAST_SAMPLE[6]; /*!< (@ 0x400F0028) Contains last converted sample of input M [M=0..5) and result of window comparator. */ - __I uint32_t RESERVED0[48]; - __IO uint32_t ADC_DEBUG; /*!< (@ 0x400F0100) Reserved (ADC Debug pin inputs) */ - __IO uint32_t ADC_SPEED; /*!< (@ 0x400F0104) ADC speed control */ - __IO uint32_t POWER_CONTROL; /*!< (@ 0x400F0108) Configures ADC power vs. speed, DC-in biasing, output format and power gating. */ - __I uint32_t RESERVED1[61]; - __I uint32_t FIFO_OUTPUT[16]; /*!< (@ 0x400F0200 - 0x400F023C) FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples */ - __I uint32_t RESERVED2[48]; - __IO uint32_t DESCRIPTOR_0[8]; /*!< (@ 0x400F0300) Table0 descriptor n, n= 0 to 7 */ - __IO uint32_t DESCRIPTOR_1[8]; /*!< (@ 0x400F0320) Table1 descriptor n, n= 0 to 7 */ - __I uint32_t RESERVED3[752]; - __O uint32_t CLR_EN0; /*!< (@ 0x400F0F00) Interrupt0 clear mask */ - __O uint32_t SET_EN0; /*!< (@ 0x400F0F04) Interrupt0 set mask */ - __I uint32_t MASK0; /*!< (@ 0x400F0F08) Interrupt0 mask */ - __I uint32_t STATUS0; /*!< (@ 0x400F0F0C) Interrupt0 status. Interrupt0 contains FIFO fullness, descriptor status and ADC range under/overflow */ - __O uint32_t CLR_STAT0; /*!< (@ 0x400F0F10) Interrupt0 clear status */ - __O uint32_t SET_STAT0; /*!< (@ 0x400F0F14) Interrupt0 set status */ - __I uint32_t RESERVED4[2]; - __O uint32_t CLR_EN1; /*!< (@ 0x400F0F20) Interrupt1 mask clear enable. */ - __O uint32_t SET_EN1; /*!< (@ 0x400F0F24) Interrupt1 mask set enable */ - __I uint32_t MASK1; /*!< (@ 0x400F0F28) Interrupt1 mask */ - __I uint32_t STATUS1; /*!< (@ 0x400F0F2C) Interrupt1 status. Interrupt1 contains window comparator results and register last LAST_SAMPLE[M] overrun. */ - __O uint32_t CLR_STAT1; /*!< (@ 0x400F0F30) Interrupt1 clear status */ - __O uint32_t SET_STAT1; /*!< (@ 0x400F0F34) Interrupt1 set status */ -} LPC_VADC_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_PORT ----- -// ------------------------------------------------------------------------------------------------ +typedef struct { /*!< (@ 0x400F0000) ADCHS Structure */ + __O uint32_t FLUSH; /*!< (@ 0x400F0000) Flushes FIFO */ + __IO uint32_t DMA_REQ; /*!< (@ 0x400F0004) Set or clear DMA write request */ + __I uint32_t FIFO_STS; /*!< (@ 0x400F0008) Indicates FIFO fill level status */ + __IO uint32_t FIFO_CFG; /*!< (@ 0x400F000C) Configures FIFO fill level that triggers interrupt + and packing 1 or 2 samples per word. */ + __O uint32_t TRIGGER; /*!< (@ 0x400F0010) Enable software trigger to start descriptor processing */ + __IO uint32_t DSCR_STS; /*!< (@ 0x400F0014) Indicates active descriptor table and descriptor + entry */ + __IO uint32_t POWER_DOWN; /*!< (@ 0x400F0018) Set or clear power down mode */ + __IO uint32_t CONFIG; /*!< (@ 0x400F001C) Configures external trigger mode, store channel + ID in FIFO and walk-up recovery time from power down. */ + __IO uint32_t THR_A; /*!< (@ 0x400F0020) Configures window comparator A levels. */ + __IO uint32_t THR_B; /*!< (@ 0x400F0024) Configures window comparator B levels. */ + __I uint32_t LAST_SAMPLE[6]; /*!< (@ 0x400F0028) Contains last converted sample of input M [M=0..5) + and result of window comparator. */ + __I uint32_t RESERVED0[49]; + __IO uint32_t ADC_SPEED; /*!< (@ 0x400F0104) ADC speed control */ + __IO uint32_t POWER_CONTROL; /*!< (@ 0x400F0108) Configures ADC power vs. speed, DC-in biasing, + output format and power gating. */ + __I uint32_t RESERVED1[61]; + __I uint32_t FIFO_OUTPUT[16]; /*!< (@ 0x400F0200) FIFO output mapped to 16 consecutive address + locations. An output contains the value and input channel ID + of one or two converted samples */ + __I uint32_t RESERVED2[48]; + __IO uint32_t DESCRIPTOR0_[8]; /*!< (@ 0x400F0300) Table 0 descriptor n, n= 0 to 7 */ + __IO uint32_t DESCRIPTOR1_[8]; /*!< (@ 0x400F0320) Table 1 descriptors n, n=0 to 7 */ + __I uint32_t RESERVED3[752]; + __O uint32_t CLR_EN0; /*!< (@ 0x400F0F00) Interrupt 0 clear mask */ + __O uint32_t SET_EN0; /*!< (@ 0x400F0F04) Interrupt 0 set mask */ + __I uint32_t MASK0; /*!< (@ 0x400F0F08) Interrupt 0 mask */ + __I uint32_t STATUS0; /*!< (@ 0x400F0F0C) Interrupt 0 status. Interrupt 0 contains FIFO + fill level, descriptor status and ADC range under/overflow */ + __O uint32_t CLR_STAT0; /*!< (@ 0x400F0F10) Interrupt 0 clear status */ + __O uint32_t SET_STAT0; /*!< (@ 0x400F0F14) Interrupt 0 set status */ + __I uint32_t RESERVED4[2]; + __O uint32_t CLR_EN1; /*!< (@ 0x400F0F20) Interrupt 1 mask clear enable. */ + __O uint32_t SET_EN1; /*!< (@ 0x400F0F24) Interrupt 1 mask set enable */ + __I uint32_t MASK1; /*!< (@ 0x400F0F28) Interrupt 1 mask */ + __I uint32_t STATUS1; /*!< (@ 0x400F0F2C) Interrupt 1 status. Interrupt 1 contains window + comparator results and register last LAST_SAMPLE[M] overrun. */ + __O uint32_t CLR_STAT1; /*!< (@ 0x400F0F30) Interrupt 1 clear status */ + __O uint32_t SET_STAT1; /*!< (@ 0x400F0F34) Interrupt 1 set status */ +} LPC_ADCHS_Type; + + +/* ================================================================================ */ +/* ================ GPIO_PORT ================ */ +/* ================================================================================ */ /** * @brief GPIO port (GPIO_PORT) */ -typedef struct { /*!< (@ 0x400F4000) GPIO_PORT Structure */ - __IO uint8_t B[256]; /*!< (@ 0x400F4000) Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31 */ +typedef struct { /*!< (@ 0x400F4000) GPIO_PORT Structure */ + __IO uint8_t B[256]; /*!< (@ 0x400F4000) Byte pin registers port 0 to 5; pins PIOn_0 to + PIOn_31 */ __I uint32_t RESERVED0[960]; - __IO uint32_t W[256]; /*!< (@ 0x400F5000) Word pin registers port 0 to 5 */ + __IO uint32_t W[256]; /*!< (@ 0x400F5000) Word pin registers port 0 to 5 */ __I uint32_t RESERVED1[768]; - __IO uint32_t DIR[8]; /*!< (@ 0x400F6000) Direction registers port n */ + __IO uint32_t DIR[8]; /*!< (@ 0x400F6000) Direction registers port m */ __I uint32_t RESERVED2[24]; - __IO uint32_t MASK[8]; /*!< (@ 0x400F6080) Mask register port n */ + __IO uint32_t MASK[8]; /*!< (@ 0x400F6080) Mask register port m */ __I uint32_t RESERVED3[24]; - __IO uint32_t PIN[8]; /*!< (@ 0x400F6100) Portpin register port n */ + __IO uint32_t PIN[8]; /*!< (@ 0x400F6100) Port pin register port m */ __I uint32_t RESERVED4[24]; - __IO uint32_t MPIN[8]; /*!< (@ 0x400F6180) Masked port register port n */ + __IO uint32_t MPIN[8]; /*!< (@ 0x400F6180) Masked port register port m */ __I uint32_t RESERVED5[24]; - __IO uint32_t SET[8]; /*!< (@ 0x400F6200) Write: Set register for port n Read: output bits for port n */ + __IO uint32_t SET[8]; /*!< (@ 0x400F6200) Write: Set register for port m Read: output bits + for port m */ __I uint32_t RESERVED6[24]; - __O uint32_t CLR[8]; /*!< (@ 0x400F6280) Clear port n */ + __O uint32_t CLR[8]; /*!< (@ 0x400F6280) Clear port m */ __I uint32_t RESERVED7[24]; - __O uint32_t NOT[8]; /*!< (@ 0x400F6300) Toggle port n */ + __O uint32_t NOT[8]; /*!< (@ 0x400F6300) Toggle port m */ } LPC_GPIO_PORT_Type; -// ------------------------------------------------------------------------------------------------ -// ----- SPI ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ SPI ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10503 Chapter title=LPC43xxSPI Modification date=10/7/2011 Major revision=0 Minor revision=3 (SPI) + * @brief SPI (SPI) */ -typedef struct { /*!< (@ 0x40100000) SPI Structure */ - __IO uint32_t CR; /*!< (@ 0x40100000) SPI Control Register. This register controls the operation of the SPI. */ - __I uint32_t SR; /*!< (@ 0x40100004) SPI Status Register. This register shows the status of the SPI. */ - __IO uint32_t DR; /*!< (@ 0x40100008) SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register. */ - __IO uint32_t CCR; /*!< (@ 0x4010000C) SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */ - __IO uint32_t TCR; /*!< (@ 0x40100010) SPI Test Control register. For functional testing only. */ - __IO uint32_t TSR; /*!< (@ 0x40100014) SPI Test Status register. For functional testing only. */ +typedef struct { /*!< (@ 0x40100000) SPI Structure */ + __IO uint32_t CR; /*!< (@ 0x40100000) SPI Control Register. This register controls + the operation of the SPI. */ + __I uint32_t SR; /*!< (@ 0x40100004) SPI Status Register. This register shows the + status of the SPI. */ + __IO uint32_t DR; /*!< (@ 0x40100008) SPI Data Register. This bi-directional register + provides the transmit and receive data for the SPI. Transmit + data is provided to the SPI0 by writing to this register. Data + received by the SPI0 can be read from this register. */ + __IO uint32_t CCR; /*!< (@ 0x4010000C) SPI Clock Counter Register. This register controls + the frequency of a master's SCK0. */ + __IO uint32_t TCR; /*!< (@ 0x40100010) SPI Test Control register. For functional testing + only. */ + __IO uint32_t TSR; /*!< (@ 0x40100014) SPI Test Status register. For functional testing + only. */ __I uint32_t RESERVED0; - __IO uint32_t INT; /*!< (@ 0x4010001C) SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */ + __IO uint32_t INT; /*!< (@ 0x4010001C) SPI Interrupt Flag. This register contains the + interrupt flag for the SPI interface. */ } LPC_SPI_Type; -// ------------------------------------------------------------------------------------------------ -// ----- SGPIO ----- -// ------------------------------------------------------------------------------------------------ +/* ================================================================================ */ +/* ================ SGPIO ================ */ +/* ================================================================================ */ /** - * @brief Product name title=UM10503 Chapter title=LPC43xx SerialGPIO (SGPIO) Modification date=10/7/2011 Major revision=0 Minor revision=3 (SGPIO) + * @brief Serial GPIO (SGPIO) (SGPIO) */ -typedef struct { /*!< (@ 0x40101000) SGPIO Structure */ - __IO uint32_t OUT_MUX_CFG[16]; /*!< (@ 0x40101000) Pin multiplexer configurationregisters. */ - __IO uint32_t SGPIO_MUX_CFG[16]; /*!< (@ 0x40101040) SGPIO multiplexer configuration registers. */ - __IO uint32_t SLICE_MUX_CFG[16]; /*!< (@ 0x40101080) Slice multiplexer configuration registers. */ - __IO uint32_t REG[16]; /*!< (@ 0x401010C0) Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */ - __IO uint32_t REG_SS[16]; /*!< (@ 0x40101100) Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */ - __IO uint32_t PRESET[16]; /*!< (@ 0x40101140) Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */ - __IO uint32_t COUNT[16]; /*!< (@ 0x40101180) Down counter, counts down each clock cycle. */ - __IO uint32_t POS[16]; /*!< (@ 0x401011C0) Each time COUNT0 reaches 0x0 */ - __IO uint32_t MASK_A; /*!< (@ 0x40101200) Mask for pattern match function of slice A */ - __IO uint32_t MASK_H; /*!< (@ 0x40101204) Mask for pattern match function of slice H */ - __IO uint32_t MASK_I; /*!< (@ 0x40101208) Mask for pattern match function of slice I */ - __IO uint32_t MASK_P; /*!< (@ 0x4010120C) Mask for pattern match function of slice P */ - __I uint32_t GPIO_INREG; /*!< (@ 0x40101210) GPIO input status register */ - __IO uint32_t GPIO_OUTREG; /*!< (@ 0x40101214) GPIO output control register */ - __IO uint32_t GPIO_OENREG; /*!< (@ 0x40101218) GPIO OE control register */ - __IO uint32_t CTRL_ENABLED; /*!< (@ 0x4010121C) Enables the slice COUNT counter */ - __IO uint32_t CTRL_DISABLED; /*!< (@ 0x40101220) Disables the slice COUNT counter */ +typedef struct { /*!< (@ 0x40101000) SGPIO Structure */ + __IO uint32_t OUT_MUX_CFG[16]; /*!< (@ 0x40101000) Pin multiplexer configuration registers. */ + __IO uint32_t SGPIO_MUX_CFG[16]; /*!< (@ 0x40101040) SGPIO multiplexer configuration registers. */ + __IO uint32_t SLICE_MUX_CFG[16]; /*!< (@ 0x40101080) Slice multiplexer configuration registers. */ + __IO uint32_t REG[16]; /*!< (@ 0x401010C0) Slice data registers. Each time COUNT0 reaches + 0x0 the register shifts loading bit 31 with data captured from + DIN(n). DOUT(n) is set to REG(0) */ + __IO uint32_t REG_SS[16]; /*!< (@ 0x40101100) Slice data shadow registers. Each time POS reaches + 0x0 the contents of REG_SS is exchanged with the content of + REG */ + __IO uint32_t PRESET[16]; /*!< (@ 0x40101140) Reload value of COUNT0, loaded when COUNT0 reaches + 0x0 */ + __IO uint32_t COUNT[16]; /*!< (@ 0x40101180) Down counter, counts down each clock cycle. */ + __IO uint32_t POS[16]; /*!< (@ 0x401011C0) Each time COUNT0 reaches 0x0 POS counts down. */ + __IO uint32_t MASK_A; /*!< (@ 0x40101200) Mask for pattern match function of slice A */ + __IO uint32_t MASK_H; /*!< (@ 0x40101204) Mask for pattern match function of slice H */ + __IO uint32_t MASK_I; /*!< (@ 0x40101208) Mask for pattern match function of slice I */ + __IO uint32_t MASK_P; /*!< (@ 0x4010120C) Mask for pattern match function of slice P */ + __I uint32_t GPIO_INREG; /*!< (@ 0x40101210) GPIO input status register */ + __IO uint32_t GPIO_OUTREG; /*!< (@ 0x40101214) GPIO output control register */ + __IO uint32_t GPIO_OENREG; /*!< (@ 0x40101218) GPIO OE control register */ + __IO uint32_t CTRL_ENABLE; /*!< (@ 0x4010121C) Enables the slice COUNT counter */ + __IO uint32_t CTRL_DISABLE; /*!< (@ 0x40101220) Disables the slice POS counter */ __I uint32_t RESERVED0[823]; - __O uint32_t CLR_EN_0; /*!< (@ 0x40101F00) Shift clock interrupt clear mask */ - __O uint32_t SET_EN_0; /*!< (@ 0x40101F04) Shift clock interrupt set mask */ - __I uint32_t ENABLE_0; /*!< (@ 0x40101F08) Shift clock interrupt enable */ - __I uint32_t STATUS_0; /*!< (@ 0x40101F0C) Shift clock interrupt status */ - __O uint32_t CTR_STATUS_0; /*!< (@ 0x40101F10) Shift clock interrupt clear status */ - __O uint32_t SET_STATUS_0; /*!< (@ 0x40101F14) Shift clock interrupt set status */ + __O uint32_t CLR_EN_0; /*!< (@ 0x40101F00) Shift clock interrupt clear mask */ + __O uint32_t SET_EN_0; /*!< (@ 0x40101F04) Shift clock interrupt set mask */ + __I uint32_t ENABLE_0; /*!< (@ 0x40101F08) Shift clock interrupt enable */ + __I uint32_t STATUS_0; /*!< (@ 0x40101F0C) Shift clock interrupt status */ + __O uint32_t CLR_STATUS_0; /*!< (@ 0x40101F10) Shift clock interrupt clear status */ + __O uint32_t SET_STATUS_0; /*!< (@ 0x40101F14) Shift clock interrupt set status */ __I uint32_t RESERVED1[2]; - __O uint32_t CLR_EN_1; /*!< (@ 0x40101F20) Capture clock interrupt clear mask */ - __O uint32_t SET_EN_1; /*!< (@ 0x40101F24) Capture clock interrupt set mask */ - __I uint32_t ENABLE_1; /*!< (@ 0x40101F28) Capture clock interrupt enable */ - __I uint32_t STATUS_1; /*!< (@ 0x40101F2C) Capture clock interrupt status */ - __O uint32_t CTR_STATUS_1; /*!< (@ 0x40101F30) Capture clock interrupt clear status */ - __O uint32_t SET_STATUS_1; /*!< (@ 0x40101F34) Capture clock interrupt set status */ + __O uint32_t CLR_EN_1; /*!< (@ 0x40101F20) Exchange clock interrupt clear mask */ + __O uint32_t SET_EN_1; /*!< (@ 0x40101F24) Exchange clock interrupt set mask */ + __I uint32_t ENABLE_1; /*!< (@ 0x40101F28) Exchange clock interrupt enable */ + __I uint32_t STATUS_1; /*!< (@ 0x40101F2C) Exchange clock interrupt status */ + __O uint32_t CLR_STATUS_1; /*!< (@ 0x40101F30) Exchange clock interrupt clear status */ + __O uint32_t SET_STATUS_1; /*!< (@ 0x40101F34) Exchange clock interrupt set status */ __I uint32_t RESERVED2[2]; - __O uint32_t CLR_EN_2; /*!< (@ 0x40101F40) Pattern match interrupt clear mask */ - __O uint32_t SET_EN_2; /*!< (@ 0x40101F44) Pattern match interrupt set mask */ - __I uint32_t ENABLE_2; /*!< (@ 0x40101F48) Pattern match interrupt enable */ - __I uint32_t STATUS_2; /*!< (@ 0x40101F4C) Pattern match interrupt status */ - __O uint32_t CTR_STATUS_2; /*!< (@ 0x40101F50) Pattern match interrupt clear status */ - __O uint32_t SET_STATUS_2; /*!< (@ 0x40101F54) Pattern match interrupt set status */ + __O uint32_t CLR_EN_2; /*!< (@ 0x40101F40) Pattern match interrupt clear mask */ + __O uint32_t SET_EN_2; /*!< (@ 0x40101F44) Pattern match interrupt set mask */ + __I uint32_t ENABLE_2; /*!< (@ 0x40101F48) Pattern match interrupt enable */ + __I uint32_t STATUS_2; /*!< (@ 0x40101F4C) Pattern match interrupt status */ + __O uint32_t CLR_STATUS_2; /*!< (@ 0x40101F50) Pattern match interrupt clear status */ + __O uint32_t SET_STATUS_2; /*!< (@ 0x40101F54) Pattern match interrupt set status */ __I uint32_t RESERVED3[2]; - __O uint32_t CLR_EN_3; /*!< (@ 0x40101F60) Input interrupt clear mask */ - __O uint32_t SET_EN_3; /*!< (@ 0x40101F64) Input bit match interrupt set mask */ - __I uint32_t ENABLE_3; /*!< (@ 0x40101F68) Input bit match interrupt enable */ - __I uint32_t STATUS_3; /*!< (@ 0x40101F6C) Input bit match interrupt status */ - __O uint32_t CTR_STATUS_3; /*!< (@ 0x40101F70) Input bit match interrupt clear status */ - __O uint32_t SET_STATUS_3; /*!< (@ 0x40101F74) Shift clock interrupt set status */ + __O uint32_t CLR_EN_3; /*!< (@ 0x40101F60) Input interrupt clear mask */ + __O uint32_t SET_EN_3; /*!< (@ 0x40101F64) Input bit match interrupt set mask */ + __I uint32_t ENABLE_3; /*!< (@ 0x40101F68) Input bit match interrupt enable */ + __I uint32_t STATUS_3; /*!< (@ 0x40101F6C) Input bit match interrupt status */ + __O uint32_t CLR_STATUS_3; /*!< (@ 0x40101F70) Input bit match interrupt clear status */ + __O uint32_t SET_STATUS_3; /*!< (@ 0x40101F74) Input bit match interrupt set status */ } LPC_SGPIO_Type; - -/******************************************** -** End of section using anonymous unions ** -*********************************************/ - +/* -------------------- End of section using anonymous unions ------------------- */ #if defined(__CC_ARM) #pragma pop -#elif defined(__CWCC__) - #pragma pop -#elif defined(__GNUC__) +#elif defined(__ICCARM__) /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma pop +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore #else - #error Not supported compiler type + #warning Not supported compiler type #endif #ifdef CMSIS_BITPOSITIONS -// ------------------------------------------------------------------------------------------------ -// ----- SCT Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- SCT_CONFIG ------------------------------------------- -#define SCT_CONFIG_UNIFY_Pos 0 /*!< SCT CONFIG: UNIFY Position */ -#define SCT_CONFIG_UNIFY_Msk (0x01UL << SCT_CONFIG_UNIFY_Pos) /*!< SCT CONFIG: UNIFY Mask */ -#define SCT_CONFIG_CLKMODE_Pos 1 /*!< SCT CONFIG: CLKMODE Position */ -#define SCT_CONFIG_CLKMODE_Msk (0x03UL << SCT_CONFIG_CLKMODE_Pos) /*!< SCT CONFIG: CLKMODE Mask */ -#define SCT_CONFIG_CLKSEL_Pos 3 /*!< SCT CONFIG: CLKSEL Position */ -#define SCT_CONFIG_CLKSEL_Msk (0x0fUL << SCT_CONFIG_CLKSEL_Pos) /*!< SCT CONFIG: CLKSEL Mask */ -#define SCT_CONFIG_NORELAODL_NORELOADU_Pos 7 /*!< SCT CONFIG: NORELAODL_NORELOADU Position */ -#define SCT_CONFIG_NORELAODL_NORELOADU_Msk (0x01UL << SCT_CONFIG_NORELAODL_NORELOADU_Pos) /*!< SCT CONFIG: NORELAODL_NORELOADU Mask */ -#define SCT_CONFIG_NORELOADH_Pos 8 /*!< SCT CONFIG: NORELOADH Position */ -#define SCT_CONFIG_NORELOADH_Msk (0x01UL << SCT_CONFIG_NORELOADH_Pos) /*!< SCT CONFIG: NORELOADH Mask */ -#define SCT_CONFIG_INSYNCn_Pos 9 /*!< SCT CONFIG: INSYNCn Position */ -#define SCT_CONFIG_INSYNCn_Msk (0x000000ffUL << SCT_CONFIG_INSYNCn_Pos) /*!< SCT CONFIG: INSYNCn Mask */ - -// ---------------------------------------- SCT_CTRL -------------------------------------------- -#define SCT_CTRL_DOWN_L_Pos 0 /*!< SCT CTRL: DOWN_L Position */ -#define SCT_CTRL_DOWN_L_Msk (0x01UL << SCT_CTRL_DOWN_L_Pos) /*!< SCT CTRL: DOWN_L Mask */ -#define SCT_CTRL_STOP_L_Pos 1 /*!< SCT CTRL: STOP_L Position */ -#define SCT_CTRL_STOP_L_Msk (0x01UL << SCT_CTRL_STOP_L_Pos) /*!< SCT CTRL: STOP_L Mask */ -#define SCT_CTRL_HALT_L_Pos 2 /*!< SCT CTRL: HALT_L Position */ -#define SCT_CTRL_HALT_L_Msk (0x01UL << SCT_CTRL_HALT_L_Pos) /*!< SCT CTRL: HALT_L Mask */ -#define SCT_CTRL_CLRCTR_L_Pos 3 /*!< SCT CTRL: CLRCTR_L Position */ -#define SCT_CTRL_CLRCTR_L_Msk (0x01UL << SCT_CTRL_CLRCTR_L_Pos) /*!< SCT CTRL: CLRCTR_L Mask */ -#define SCT_CTRL_BIDIR_L_Pos 4 /*!< SCT CTRL: BIDIR_L Position */ -#define SCT_CTRL_BIDIR_L_Msk (0x01UL << SCT_CTRL_BIDIR_L_Pos) /*!< SCT CTRL: BIDIR_L Mask */ -#define SCT_CTRL_PRE_L_Pos 5 /*!< SCT CTRL: PRE_L Position */ -#define SCT_CTRL_PRE_L_Msk (0x000000ffUL << SCT_CTRL_PRE_L_Pos) /*!< SCT CTRL: PRE_L Mask */ -#define SCT_CTRL_DOWN_H_Pos 16 /*!< SCT CTRL: DOWN_H Position */ -#define SCT_CTRL_DOWN_H_Msk (0x01UL << SCT_CTRL_DOWN_H_Pos) /*!< SCT CTRL: DOWN_H Mask */ -#define SCT_CTRL_STOP_H_Pos 17 /*!< SCT CTRL: STOP_H Position */ -#define SCT_CTRL_STOP_H_Msk (0x01UL << SCT_CTRL_STOP_H_Pos) /*!< SCT CTRL: STOP_H Mask */ -#define SCT_CTRL_HALT_H_Pos 18 /*!< SCT CTRL: HALT_H Position */ -#define SCT_CTRL_HALT_H_Msk (0x01UL << SCT_CTRL_HALT_H_Pos) /*!< SCT CTRL: HALT_H Mask */ -#define SCT_CTRL_CLRCTR_H_Pos 19 /*!< SCT CTRL: CLRCTR_H Position */ -#define SCT_CTRL_CLRCTR_H_Msk (0x01UL << SCT_CTRL_CLRCTR_H_Pos) /*!< SCT CTRL: CLRCTR_H Mask */ -#define SCT_CTRL_BIDIR_H_Pos 20 /*!< SCT CTRL: BIDIR_H Position */ -#define SCT_CTRL_BIDIR_H_Msk (0x01UL << SCT_CTRL_BIDIR_H_Pos) /*!< SCT CTRL: BIDIR_H Mask */ -#define SCT_CTRL_PRE_H_Pos 21 /*!< SCT CTRL: PRE_H Position */ -#define SCT_CTRL_PRE_H_Msk (0x000000ffUL << SCT_CTRL_PRE_H_Pos) /*!< SCT CTRL: PRE_H Mask */ - -// ---------------------------------------- SCT_LIMIT ------------------------------------------- -#define SCT_LIMIT_LIMMSK_L_Pos 0 /*!< SCT LIMIT: LIMMSK_L Position */ -#define SCT_LIMIT_LIMMSK_L_Msk (0x0000ffffUL << SCT_LIMIT_LIMMSK_L_Pos) /*!< SCT LIMIT: LIMMSK_L Mask */ -#define SCT_LIMIT_LIMMSK_H_Pos 16 /*!< SCT LIMIT: LIMMSK_H Position */ -#define SCT_LIMIT_LIMMSK_H_Msk (0x0000ffffUL << SCT_LIMIT_LIMMSK_H_Pos) /*!< SCT LIMIT: LIMMSK_H Mask */ - -// ---------------------------------------- SCT_HALT -------------------------------------------- -#define SCT_HALT_HALTMSK_L_Pos 0 /*!< SCT HALT: HALTMSK_L Position */ -#define SCT_HALT_HALTMSK_L_Msk (0x0000ffffUL << SCT_HALT_HALTMSK_L_Pos) /*!< SCT HALT: HALTMSK_L Mask */ -#define SCT_HALT_HALTMSK_H_Pos 16 /*!< SCT HALT: HALTMSK_H Position */ -#define SCT_HALT_HALTMSK_H_Msk (0x0000ffffUL << SCT_HALT_HALTMSK_H_Pos) /*!< SCT HALT: HALTMSK_H Mask */ - -// ---------------------------------------- SCT_STOP -------------------------------------------- -#define SCT_STOP_STOPMSK_L_Pos 0 /*!< SCT STOP: STOPMSK_L Position */ -#define SCT_STOP_STOPMSK_L_Msk (0x0000ffffUL << SCT_STOP_STOPMSK_L_Pos) /*!< SCT STOP: STOPMSK_L Mask */ -#define SCT_STOP_STOPMSK_H_Pos 16 /*!< SCT STOP: STOPMSK_H Position */ -#define SCT_STOP_STOPMSK_H_Msk (0x0000ffffUL << SCT_STOP_STOPMSK_H_Pos) /*!< SCT STOP: STOPMSK_H Mask */ - -// ---------------------------------------- SCT_START ------------------------------------------- -#define SCT_START_STARTMSK_L_Pos 0 /*!< SCT START: STARTMSK_L Position */ -#define SCT_START_STARTMSK_L_Msk (0x0000ffffUL << SCT_START_STARTMSK_L_Pos) /*!< SCT START: STARTMSK_L Mask */ -#define SCT_START_STARTMSK_H_Pos 16 /*!< SCT START: STARTMSK_H Position */ -#define SCT_START_STARTMSK_H_Msk (0x0000ffffUL << SCT_START_STARTMSK_H_Pos) /*!< SCT START: STARTMSK_H Mask */ - -// ---------------------------------------- SCT_COUNT ------------------------------------------- -#define SCT_COUNT_CTR_L_Pos 0 /*!< SCT COUNT: CTR_L Position */ -#define SCT_COUNT_CTR_L_Msk (0x0000ffffUL << SCT_COUNT_CTR_L_Pos) /*!< SCT COUNT: CTR_L Mask */ -#define SCT_COUNT_CTR_H_Pos 16 /*!< SCT COUNT: CTR_H Position */ -#define SCT_COUNT_CTR_H_Msk (0x0000ffffUL << SCT_COUNT_CTR_H_Pos) /*!< SCT COUNT: CTR_H Mask */ - -// ---------------------------------------- SCT_STATE ------------------------------------------- -#define SCT_STATE_STATE_L_Pos 0 /*!< SCT STATE: STATE_L Position */ -#define SCT_STATE_STATE_L_Msk (0x1fUL << SCT_STATE_STATE_L_Pos) /*!< SCT STATE: STATE_L Mask */ -#define SCT_STATE_STATE_H_Pos 16 /*!< SCT STATE: STATE_H Position */ -#define SCT_STATE_STATE_H_Msk (0x1fUL << SCT_STATE_STATE_H_Pos) /*!< SCT STATE: STATE_H Mask */ - -// ---------------------------------------- SCT_INPUT ------------------------------------------- -#define SCT_INPUT_AIN0_Pos 0 /*!< SCT INPUT: AIN0 Position */ -#define SCT_INPUT_AIN0_Msk (0x01UL << SCT_INPUT_AIN0_Pos) /*!< SCT INPUT: AIN0 Mask */ -#define SCT_INPUT_AIN1_Pos 1 /*!< SCT INPUT: AIN1 Position */ -#define SCT_INPUT_AIN1_Msk (0x01UL << SCT_INPUT_AIN1_Pos) /*!< SCT INPUT: AIN1 Mask */ -#define SCT_INPUT_AIN2_Pos 2 /*!< SCT INPUT: AIN2 Position */ -#define SCT_INPUT_AIN2_Msk (0x01UL << SCT_INPUT_AIN2_Pos) /*!< SCT INPUT: AIN2 Mask */ -#define SCT_INPUT_AIN3_Pos 3 /*!< SCT INPUT: AIN3 Position */ -#define SCT_INPUT_AIN3_Msk (0x01UL << SCT_INPUT_AIN3_Pos) /*!< SCT INPUT: AIN3 Mask */ -#define SCT_INPUT_AIN4_Pos 4 /*!< SCT INPUT: AIN4 Position */ -#define SCT_INPUT_AIN4_Msk (0x01UL << SCT_INPUT_AIN4_Pos) /*!< SCT INPUT: AIN4 Mask */ -#define SCT_INPUT_AIN5_Pos 5 /*!< SCT INPUT: AIN5 Position */ -#define SCT_INPUT_AIN5_Msk (0x01UL << SCT_INPUT_AIN5_Pos) /*!< SCT INPUT: AIN5 Mask */ -#define SCT_INPUT_AIN6_Pos 6 /*!< SCT INPUT: AIN6 Position */ -#define SCT_INPUT_AIN6_Msk (0x01UL << SCT_INPUT_AIN6_Pos) /*!< SCT INPUT: AIN6 Mask */ -#define SCT_INPUT_AIN7_Pos 7 /*!< SCT INPUT: AIN7 Position */ -#define SCT_INPUT_AIN7_Msk (0x01UL << SCT_INPUT_AIN7_Pos) /*!< SCT INPUT: AIN7 Mask */ -#define SCT_INPUT_SIN0_Pos 16 /*!< SCT INPUT: SIN0 Position */ -#define SCT_INPUT_SIN0_Msk (0x01UL << SCT_INPUT_SIN0_Pos) /*!< SCT INPUT: SIN0 Mask */ -#define SCT_INPUT_SIN1_Pos 17 /*!< SCT INPUT: SIN1 Position */ -#define SCT_INPUT_SIN1_Msk (0x01UL << SCT_INPUT_SIN1_Pos) /*!< SCT INPUT: SIN1 Mask */ -#define SCT_INPUT_SIN2_Pos 18 /*!< SCT INPUT: SIN2 Position */ -#define SCT_INPUT_SIN2_Msk (0x01UL << SCT_INPUT_SIN2_Pos) /*!< SCT INPUT: SIN2 Mask */ -#define SCT_INPUT_SIN3_Pos 19 /*!< SCT INPUT: SIN3 Position */ -#define SCT_INPUT_SIN3_Msk (0x01UL << SCT_INPUT_SIN3_Pos) /*!< SCT INPUT: SIN3 Mask */ -#define SCT_INPUT_SIN4_Pos 20 /*!< SCT INPUT: SIN4 Position */ -#define SCT_INPUT_SIN4_Msk (0x01UL << SCT_INPUT_SIN4_Pos) /*!< SCT INPUT: SIN4 Mask */ -#define SCT_INPUT_SIN5_Pos 21 /*!< SCT INPUT: SIN5 Position */ -#define SCT_INPUT_SIN5_Msk (0x01UL << SCT_INPUT_SIN5_Pos) /*!< SCT INPUT: SIN5 Mask */ -#define SCT_INPUT_SIN6_Pos 22 /*!< SCT INPUT: SIN6 Position */ -#define SCT_INPUT_SIN6_Msk (0x01UL << SCT_INPUT_SIN6_Pos) /*!< SCT INPUT: SIN6 Mask */ -#define SCT_INPUT_SIN7_Pos 23 /*!< SCT INPUT: SIN7 Position */ -#define SCT_INPUT_SIN7_Msk (0x01UL << SCT_INPUT_SIN7_Pos) /*!< SCT INPUT: SIN7 Mask */ - -// --------------------------------------- SCT_REGMODE ------------------------------------------ -#define SCT_REGMODE_REGMOD_L0_Pos 0 /*!< SCT REGMODE: REGMOD_L0 Position */ -#define SCT_REGMODE_REGMOD_L0_Msk (0x01UL << SCT_REGMODE_REGMOD_L0_Pos) /*!< SCT REGMODE: REGMOD_L0 Mask */ -#define SCT_REGMODE_REGMOD_L1_Pos 1 /*!< SCT REGMODE: REGMOD_L1 Position */ -#define SCT_REGMODE_REGMOD_L1_Msk (0x01UL << SCT_REGMODE_REGMOD_L1_Pos) /*!< SCT REGMODE: REGMOD_L1 Mask */ -#define SCT_REGMODE_REGMOD_L2_Pos 2 /*!< SCT REGMODE: REGMOD_L2 Position */ -#define SCT_REGMODE_REGMOD_L2_Msk (0x01UL << SCT_REGMODE_REGMOD_L2_Pos) /*!< SCT REGMODE: REGMOD_L2 Mask */ -#define SCT_REGMODE_REGMOD_L3_Pos 3 /*!< SCT REGMODE: REGMOD_L3 Position */ -#define SCT_REGMODE_REGMOD_L3_Msk (0x01UL << SCT_REGMODE_REGMOD_L3_Pos) /*!< SCT REGMODE: REGMOD_L3 Mask */ -#define SCT_REGMODE_REGMOD_L4_Pos 4 /*!< SCT REGMODE: REGMOD_L4 Position */ -#define SCT_REGMODE_REGMOD_L4_Msk (0x01UL << SCT_REGMODE_REGMOD_L4_Pos) /*!< SCT REGMODE: REGMOD_L4 Mask */ -#define SCT_REGMODE_REGMOD_L5_Pos 5 /*!< SCT REGMODE: REGMOD_L5 Position */ -#define SCT_REGMODE_REGMOD_L5_Msk (0x01UL << SCT_REGMODE_REGMOD_L5_Pos) /*!< SCT REGMODE: REGMOD_L5 Mask */ -#define SCT_REGMODE_REGMOD_L6_Pos 6 /*!< SCT REGMODE: REGMOD_L6 Position */ -#define SCT_REGMODE_REGMOD_L6_Msk (0x01UL << SCT_REGMODE_REGMOD_L6_Pos) /*!< SCT REGMODE: REGMOD_L6 Mask */ -#define SCT_REGMODE_REGMOD_L7_Pos 7 /*!< SCT REGMODE: REGMOD_L7 Position */ -#define SCT_REGMODE_REGMOD_L7_Msk (0x01UL << SCT_REGMODE_REGMOD_L7_Pos) /*!< SCT REGMODE: REGMOD_L7 Mask */ -#define SCT_REGMODE_REGMOD_L8_Pos 8 /*!< SCT REGMODE: REGMOD_L8 Position */ -#define SCT_REGMODE_REGMOD_L8_Msk (0x01UL << SCT_REGMODE_REGMOD_L8_Pos) /*!< SCT REGMODE: REGMOD_L8 Mask */ -#define SCT_REGMODE_REGMOD_L9_Pos 9 /*!< SCT REGMODE: REGMOD_L9 Position */ -#define SCT_REGMODE_REGMOD_L9_Msk (0x01UL << SCT_REGMODE_REGMOD_L9_Pos) /*!< SCT REGMODE: REGMOD_L9 Mask */ -#define SCT_REGMODE_REGMOD_L10_Pos 10 /*!< SCT REGMODE: REGMOD_L10 Position */ -#define SCT_REGMODE_REGMOD_L10_Msk (0x01UL << SCT_REGMODE_REGMOD_L10_Pos) /*!< SCT REGMODE: REGMOD_L10 Mask */ -#define SCT_REGMODE_REGMOD_L11_Pos 11 /*!< SCT REGMODE: REGMOD_L11 Position */ -#define SCT_REGMODE_REGMOD_L11_Msk (0x01UL << SCT_REGMODE_REGMOD_L11_Pos) /*!< SCT REGMODE: REGMOD_L11 Mask */ -#define SCT_REGMODE_REGMOD_L12_Pos 12 /*!< SCT REGMODE: REGMOD_L12 Position */ -#define SCT_REGMODE_REGMOD_L12_Msk (0x01UL << SCT_REGMODE_REGMOD_L12_Pos) /*!< SCT REGMODE: REGMOD_L12 Mask */ -#define SCT_REGMODE_REGMOD_L13_Pos 13 /*!< SCT REGMODE: REGMOD_L13 Position */ -#define SCT_REGMODE_REGMOD_L13_Msk (0x01UL << SCT_REGMODE_REGMOD_L13_Pos) /*!< SCT REGMODE: REGMOD_L13 Mask */ -#define SCT_REGMODE_REGMOD_L14_Pos 14 /*!< SCT REGMODE: REGMOD_L14 Position */ -#define SCT_REGMODE_REGMOD_L14_Msk (0x01UL << SCT_REGMODE_REGMOD_L14_Pos) /*!< SCT REGMODE: REGMOD_L14 Mask */ -#define SCT_REGMODE_REGMOD_L15_Pos 15 /*!< SCT REGMODE: REGMOD_L15 Position */ -#define SCT_REGMODE_REGMOD_L15_Msk (0x01UL << SCT_REGMODE_REGMOD_L15_Pos) /*!< SCT REGMODE: REGMOD_L15 Mask */ -#define SCT_REGMODE_REGMOD_H16_Pos 16 /*!< SCT REGMODE: REGMOD_H16 Position */ -#define SCT_REGMODE_REGMOD_H16_Msk (0x01UL << SCT_REGMODE_REGMOD_H16_Pos) /*!< SCT REGMODE: REGMOD_H16 Mask */ -#define SCT_REGMODE_REGMOD_H17_Pos 17 /*!< SCT REGMODE: REGMOD_H17 Position */ -#define SCT_REGMODE_REGMOD_H17_Msk (0x01UL << SCT_REGMODE_REGMOD_H17_Pos) /*!< SCT REGMODE: REGMOD_H17 Mask */ -#define SCT_REGMODE_REGMOD_H18_Pos 18 /*!< SCT REGMODE: REGMOD_H18 Position */ -#define SCT_REGMODE_REGMOD_H18_Msk (0x01UL << SCT_REGMODE_REGMOD_H18_Pos) /*!< SCT REGMODE: REGMOD_H18 Mask */ -#define SCT_REGMODE_REGMOD_H19_Pos 19 /*!< SCT REGMODE: REGMOD_H19 Position */ -#define SCT_REGMODE_REGMOD_H19_Msk (0x01UL << SCT_REGMODE_REGMOD_H19_Pos) /*!< SCT REGMODE: REGMOD_H19 Mask */ -#define SCT_REGMODE_REGMOD_H20_Pos 20 /*!< SCT REGMODE: REGMOD_H20 Position */ -#define SCT_REGMODE_REGMOD_H20_Msk (0x01UL << SCT_REGMODE_REGMOD_H20_Pos) /*!< SCT REGMODE: REGMOD_H20 Mask */ -#define SCT_REGMODE_REGMOD_H21_Pos 21 /*!< SCT REGMODE: REGMOD_H21 Position */ -#define SCT_REGMODE_REGMOD_H21_Msk (0x01UL << SCT_REGMODE_REGMOD_H21_Pos) /*!< SCT REGMODE: REGMOD_H21 Mask */ -#define SCT_REGMODE_REGMOD_H22_Pos 22 /*!< SCT REGMODE: REGMOD_H22 Position */ -#define SCT_REGMODE_REGMOD_H22_Msk (0x01UL << SCT_REGMODE_REGMOD_H22_Pos) /*!< SCT REGMODE: REGMOD_H22 Mask */ -#define SCT_REGMODE_REGMOD_H23_Pos 23 /*!< SCT REGMODE: REGMOD_H23 Position */ -#define SCT_REGMODE_REGMOD_H23_Msk (0x01UL << SCT_REGMODE_REGMOD_H23_Pos) /*!< SCT REGMODE: REGMOD_H23 Mask */ -#define SCT_REGMODE_REGMOD_H24_Pos 24 /*!< SCT REGMODE: REGMOD_H24 Position */ -#define SCT_REGMODE_REGMOD_H24_Msk (0x01UL << SCT_REGMODE_REGMOD_H24_Pos) /*!< SCT REGMODE: REGMOD_H24 Mask */ -#define SCT_REGMODE_REGMOD_H25_Pos 25 /*!< SCT REGMODE: REGMOD_H25 Position */ -#define SCT_REGMODE_REGMOD_H25_Msk (0x01UL << SCT_REGMODE_REGMOD_H25_Pos) /*!< SCT REGMODE: REGMOD_H25 Mask */ -#define SCT_REGMODE_REGMOD_H26_Pos 26 /*!< SCT REGMODE: REGMOD_H26 Position */ -#define SCT_REGMODE_REGMOD_H26_Msk (0x01UL << SCT_REGMODE_REGMOD_H26_Pos) /*!< SCT REGMODE: REGMOD_H26 Mask */ -#define SCT_REGMODE_REGMOD_H27_Pos 27 /*!< SCT REGMODE: REGMOD_H27 Position */ -#define SCT_REGMODE_REGMOD_H27_Msk (0x01UL << SCT_REGMODE_REGMOD_H27_Pos) /*!< SCT REGMODE: REGMOD_H27 Mask */ -#define SCT_REGMODE_REGMOD_H28_Pos 28 /*!< SCT REGMODE: REGMOD_H28 Position */ -#define SCT_REGMODE_REGMOD_H28_Msk (0x01UL << SCT_REGMODE_REGMOD_H28_Pos) /*!< SCT REGMODE: REGMOD_H28 Mask */ -#define SCT_REGMODE_REGMOD_H29_Pos 29 /*!< SCT REGMODE: REGMOD_H29 Position */ -#define SCT_REGMODE_REGMOD_H29_Msk (0x01UL << SCT_REGMODE_REGMOD_H29_Pos) /*!< SCT REGMODE: REGMOD_H29 Mask */ -#define SCT_REGMODE_REGMOD_H30_Pos 30 /*!< SCT REGMODE: REGMOD_H30 Position */ -#define SCT_REGMODE_REGMOD_H30_Msk (0x01UL << SCT_REGMODE_REGMOD_H30_Pos) /*!< SCT REGMODE: REGMOD_H30 Mask */ -#define SCT_REGMODE_REGMOD_H31_Pos 31 /*!< SCT REGMODE: REGMOD_H31 Position */ -#define SCT_REGMODE_REGMOD_H31_Msk (0x01UL << SCT_REGMODE_REGMOD_H31_Pos) /*!< SCT REGMODE: REGMOD_H31 Mask */ - -// --------------------------------------- SCT_OUTPUT ------------------------------------------- -#define SCT_OUTPUT_OUT0_Pos 0 /*!< SCT OUTPUT: OUT0 Position */ -#define SCT_OUTPUT_OUT0_Msk (0x01UL << SCT_OUTPUT_OUT0_Pos) /*!< SCT OUTPUT: OUT0 Mask */ -#define SCT_OUTPUT_OUT1_Pos 1 /*!< SCT OUTPUT: OUT1 Position */ -#define SCT_OUTPUT_OUT1_Msk (0x01UL << SCT_OUTPUT_OUT1_Pos) /*!< SCT OUTPUT: OUT1 Mask */ -#define SCT_OUTPUT_OUT2_Pos 2 /*!< SCT OUTPUT: OUT2 Position */ -#define SCT_OUTPUT_OUT2_Msk (0x01UL << SCT_OUTPUT_OUT2_Pos) /*!< SCT OUTPUT: OUT2 Mask */ -#define SCT_OUTPUT_OUT3_Pos 3 /*!< SCT OUTPUT: OUT3 Position */ -#define SCT_OUTPUT_OUT3_Msk (0x01UL << SCT_OUTPUT_OUT3_Pos) /*!< SCT OUTPUT: OUT3 Mask */ -#define SCT_OUTPUT_OUT4_Pos 4 /*!< SCT OUTPUT: OUT4 Position */ -#define SCT_OUTPUT_OUT4_Msk (0x01UL << SCT_OUTPUT_OUT4_Pos) /*!< SCT OUTPUT: OUT4 Mask */ -#define SCT_OUTPUT_OUT5_Pos 5 /*!< SCT OUTPUT: OUT5 Position */ -#define SCT_OUTPUT_OUT5_Msk (0x01UL << SCT_OUTPUT_OUT5_Pos) /*!< SCT OUTPUT: OUT5 Mask */ -#define SCT_OUTPUT_OUT6_Pos 6 /*!< SCT OUTPUT: OUT6 Position */ -#define SCT_OUTPUT_OUT6_Msk (0x01UL << SCT_OUTPUT_OUT6_Pos) /*!< SCT OUTPUT: OUT6 Mask */ -#define SCT_OUTPUT_OUT7_Pos 7 /*!< SCT OUTPUT: OUT7 Position */ -#define SCT_OUTPUT_OUT7_Msk (0x01UL << SCT_OUTPUT_OUT7_Pos) /*!< SCT OUTPUT: OUT7 Mask */ -#define SCT_OUTPUT_OUT8_Pos 8 /*!< SCT OUTPUT: OUT8 Position */ -#define SCT_OUTPUT_OUT8_Msk (0x01UL << SCT_OUTPUT_OUT8_Pos) /*!< SCT OUTPUT: OUT8 Mask */ -#define SCT_OUTPUT_OUT9_Pos 9 /*!< SCT OUTPUT: OUT9 Position */ -#define SCT_OUTPUT_OUT9_Msk (0x01UL << SCT_OUTPUT_OUT9_Pos) /*!< SCT OUTPUT: OUT9 Mask */ -#define SCT_OUTPUT_OUT10_Pos 10 /*!< SCT OUTPUT: OUT10 Position */ -#define SCT_OUTPUT_OUT10_Msk (0x01UL << SCT_OUTPUT_OUT10_Pos) /*!< SCT OUTPUT: OUT10 Mask */ -#define SCT_OUTPUT_OUT11_Pos 11 /*!< SCT OUTPUT: OUT11 Position */ -#define SCT_OUTPUT_OUT11_Msk (0x01UL << SCT_OUTPUT_OUT11_Pos) /*!< SCT OUTPUT: OUT11 Mask */ -#define SCT_OUTPUT_OUT12_Pos 12 /*!< SCT OUTPUT: OUT12 Position */ -#define SCT_OUTPUT_OUT12_Msk (0x01UL << SCT_OUTPUT_OUT12_Pos) /*!< SCT OUTPUT: OUT12 Mask */ -#define SCT_OUTPUT_OUT13_Pos 13 /*!< SCT OUTPUT: OUT13 Position */ -#define SCT_OUTPUT_OUT13_Msk (0x01UL << SCT_OUTPUT_OUT13_Pos) /*!< SCT OUTPUT: OUT13 Mask */ -#define SCT_OUTPUT_OUT14_Pos 14 /*!< SCT OUTPUT: OUT14 Position */ -#define SCT_OUTPUT_OUT14_Msk (0x01UL << SCT_OUTPUT_OUT14_Pos) /*!< SCT OUTPUT: OUT14 Mask */ -#define SCT_OUTPUT_OUT15_Pos 15 /*!< SCT OUTPUT: OUT15 Position */ -#define SCT_OUTPUT_OUT15_Msk (0x01UL << SCT_OUTPUT_OUT15_Pos) /*!< SCT OUTPUT: OUT15 Mask */ - -// ------------------------------------ SCT_OUTPUTDIRCTRL --------------------------------------- -#define SCT_OUTPUTDIRCTRL_SETCLR0_Pos 0 /*!< SCT OUTPUTDIRCTRL: SETCLR0 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR0_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR0_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR0 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR1_Pos 2 /*!< SCT OUTPUTDIRCTRL: SETCLR1 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR1_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR1_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR1 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR2_Pos 4 /*!< SCT OUTPUTDIRCTRL: SETCLR2 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR2_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR2_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR2 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR3_Pos 6 /*!< SCT OUTPUTDIRCTRL: SETCLR3 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR3_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR3_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR3 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR4_Pos 8 /*!< SCT OUTPUTDIRCTRL: SETCLR4 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR4_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR4_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR4 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR5_Pos 10 /*!< SCT OUTPUTDIRCTRL: SETCLR5 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR5_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR5_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR5 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR6_Pos 12 /*!< SCT OUTPUTDIRCTRL: SETCLR6 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR6_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR6_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR6 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR7_Pos 14 /*!< SCT OUTPUTDIRCTRL: SETCLR7 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR7_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR7_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR7 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR8_Pos 16 /*!< SCT OUTPUTDIRCTRL: SETCLR8 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR8_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR8_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR8 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR9_Pos 18 /*!< SCT OUTPUTDIRCTRL: SETCLR9 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR9_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR9_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR9 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR10_Pos 20 /*!< SCT OUTPUTDIRCTRL: SETCLR10 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR10_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR10_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR10 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR11_Pos 22 /*!< SCT OUTPUTDIRCTRL: SETCLR11 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR11_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR11_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR11 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR12_Pos 24 /*!< SCT OUTPUTDIRCTRL: SETCLR12 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR12_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR12_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR12 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR13_Pos 26 /*!< SCT OUTPUTDIRCTRL: SETCLR13 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR13_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR13_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR13 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR14_Pos 28 /*!< SCT OUTPUTDIRCTRL: SETCLR14 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR14_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR14_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR14 Mask */ -#define SCT_OUTPUTDIRCTRL_SETCLR15_Pos 30 /*!< SCT OUTPUTDIRCTRL: SETCLR15 Position */ -#define SCT_OUTPUTDIRCTRL_SETCLR15_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR15_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR15 Mask */ - -// ----------------------------------------- SCT_RES -------------------------------------------- -#define SCT_RES_O0RES_Pos 0 /*!< SCT RES: O0RES Position */ -#define SCT_RES_O0RES_Msk (0x03UL << SCT_RES_O0RES_Pos) /*!< SCT RES: O0RES Mask */ -#define SCT_RES_O1RES_Pos 2 /*!< SCT RES: O1RES Position */ -#define SCT_RES_O1RES_Msk (0x03UL << SCT_RES_O1RES_Pos) /*!< SCT RES: O1RES Mask */ -#define SCT_RES_O2RES_Pos 4 /*!< SCT RES: O2RES Position */ -#define SCT_RES_O2RES_Msk (0x03UL << SCT_RES_O2RES_Pos) /*!< SCT RES: O2RES Mask */ -#define SCT_RES_O3RES_Pos 6 /*!< SCT RES: O3RES Position */ -#define SCT_RES_O3RES_Msk (0x03UL << SCT_RES_O3RES_Pos) /*!< SCT RES: O3RES Mask */ -#define SCT_RES_O4RES_Pos 8 /*!< SCT RES: O4RES Position */ -#define SCT_RES_O4RES_Msk (0x03UL << SCT_RES_O4RES_Pos) /*!< SCT RES: O4RES Mask */ -#define SCT_RES_O5RES_Pos 10 /*!< SCT RES: O5RES Position */ -#define SCT_RES_O5RES_Msk (0x03UL << SCT_RES_O5RES_Pos) /*!< SCT RES: O5RES Mask */ -#define SCT_RES_O6RES_Pos 12 /*!< SCT RES: O6RES Position */ -#define SCT_RES_O6RES_Msk (0x03UL << SCT_RES_O6RES_Pos) /*!< SCT RES: O6RES Mask */ -#define SCT_RES_O7RES_Pos 14 /*!< SCT RES: O7RES Position */ -#define SCT_RES_O7RES_Msk (0x03UL << SCT_RES_O7RES_Pos) /*!< SCT RES: O7RES Mask */ -#define SCT_RES_O8RES_Pos 16 /*!< SCT RES: O8RES Position */ -#define SCT_RES_O8RES_Msk (0x03UL << SCT_RES_O8RES_Pos) /*!< SCT RES: O8RES Mask */ -#define SCT_RES_O9RES_Pos 18 /*!< SCT RES: O9RES Position */ -#define SCT_RES_O9RES_Msk (0x03UL << SCT_RES_O9RES_Pos) /*!< SCT RES: O9RES Mask */ -#define SCT_RES_O10RES_Pos 20 /*!< SCT RES: O10RES Position */ -#define SCT_RES_O10RES_Msk (0x03UL << SCT_RES_O10RES_Pos) /*!< SCT RES: O10RES Mask */ -#define SCT_RES_O11RES_Pos 22 /*!< SCT RES: O11RES Position */ -#define SCT_RES_O11RES_Msk (0x03UL << SCT_RES_O11RES_Pos) /*!< SCT RES: O11RES Mask */ -#define SCT_RES_O12RES_Pos 24 /*!< SCT RES: O12RES Position */ -#define SCT_RES_O12RES_Msk (0x03UL << SCT_RES_O12RES_Pos) /*!< SCT RES: O12RES Mask */ -#define SCT_RES_O13RES_Pos 26 /*!< SCT RES: O13RES Position */ -#define SCT_RES_O13RES_Msk (0x03UL << SCT_RES_O13RES_Pos) /*!< SCT RES: O13RES Mask */ -#define SCT_RES_O14RES_Pos 28 /*!< SCT RES: O14RES Position */ -#define SCT_RES_O14RES_Msk (0x03UL << SCT_RES_O14RES_Pos) /*!< SCT RES: O14RES Mask */ -#define SCT_RES_O15RES_Pos 30 /*!< SCT RES: O15RES Position */ -#define SCT_RES_O15RES_Msk (0x03UL << SCT_RES_O15RES_Pos) /*!< SCT RES: O15RES Mask */ - -// --------------------------------------- SCT_DMAREQ0 ------------------------------------------ -#define SCT_DMAREQ0_DEV_0_0_Pos 0 /*!< SCT DMAREQ0: DEV_0_0 Position */ -#define SCT_DMAREQ0_DEV_0_0_Msk (0x01UL << SCT_DMAREQ0_DEV_0_0_Pos) /*!< SCT DMAREQ0: DEV_0_0 Mask */ -#define SCT_DMAREQ0_DEV_0_1_Pos 1 /*!< SCT DMAREQ0: DEV_0_1 Position */ -#define SCT_DMAREQ0_DEV_0_1_Msk (0x01UL << SCT_DMAREQ0_DEV_0_1_Pos) /*!< SCT DMAREQ0: DEV_0_1 Mask */ -#define SCT_DMAREQ0_DEV_0_2_Pos 2 /*!< SCT DMAREQ0: DEV_0_2 Position */ -#define SCT_DMAREQ0_DEV_0_2_Msk (0x01UL << SCT_DMAREQ0_DEV_0_2_Pos) /*!< SCT DMAREQ0: DEV_0_2 Mask */ -#define SCT_DMAREQ0_DEV_0_3_Pos 3 /*!< SCT DMAREQ0: DEV_0_3 Position */ -#define SCT_DMAREQ0_DEV_0_3_Msk (0x01UL << SCT_DMAREQ0_DEV_0_3_Pos) /*!< SCT DMAREQ0: DEV_0_3 Mask */ -#define SCT_DMAREQ0_DEV_0_4_Pos 4 /*!< SCT DMAREQ0: DEV_0_4 Position */ -#define SCT_DMAREQ0_DEV_0_4_Msk (0x01UL << SCT_DMAREQ0_DEV_0_4_Pos) /*!< SCT DMAREQ0: DEV_0_4 Mask */ -#define SCT_DMAREQ0_DEV_0_5_Pos 5 /*!< SCT DMAREQ0: DEV_0_5 Position */ -#define SCT_DMAREQ0_DEV_0_5_Msk (0x01UL << SCT_DMAREQ0_DEV_0_5_Pos) /*!< SCT DMAREQ0: DEV_0_5 Mask */ -#define SCT_DMAREQ0_DEV_0_6_Pos 6 /*!< SCT DMAREQ0: DEV_0_6 Position */ -#define SCT_DMAREQ0_DEV_0_6_Msk (0x01UL << SCT_DMAREQ0_DEV_0_6_Pos) /*!< SCT DMAREQ0: DEV_0_6 Mask */ -#define SCT_DMAREQ0_DEV_0_7_Pos 7 /*!< SCT DMAREQ0: DEV_0_7 Position */ -#define SCT_DMAREQ0_DEV_0_7_Msk (0x01UL << SCT_DMAREQ0_DEV_0_7_Pos) /*!< SCT DMAREQ0: DEV_0_7 Mask */ -#define SCT_DMAREQ0_DEV_0_8_Pos 8 /*!< SCT DMAREQ0: DEV_0_8 Position */ -#define SCT_DMAREQ0_DEV_0_8_Msk (0x01UL << SCT_DMAREQ0_DEV_0_8_Pos) /*!< SCT DMAREQ0: DEV_0_8 Mask */ -#define SCT_DMAREQ0_DEV_0_9_Pos 9 /*!< SCT DMAREQ0: DEV_0_9 Position */ -#define SCT_DMAREQ0_DEV_0_9_Msk (0x01UL << SCT_DMAREQ0_DEV_0_9_Pos) /*!< SCT DMAREQ0: DEV_0_9 Mask */ -#define SCT_DMAREQ0_DEV_0_10_Pos 10 /*!< SCT DMAREQ0: DEV_0_10 Position */ -#define SCT_DMAREQ0_DEV_0_10_Msk (0x01UL << SCT_DMAREQ0_DEV_0_10_Pos) /*!< SCT DMAREQ0: DEV_0_10 Mask */ -#define SCT_DMAREQ0_DEV_0_11_Pos 11 /*!< SCT DMAREQ0: DEV_0_11 Position */ -#define SCT_DMAREQ0_DEV_0_11_Msk (0x01UL << SCT_DMAREQ0_DEV_0_11_Pos) /*!< SCT DMAREQ0: DEV_0_11 Mask */ -#define SCT_DMAREQ0_DEV_0_12_Pos 12 /*!< SCT DMAREQ0: DEV_0_12 Position */ -#define SCT_DMAREQ0_DEV_0_12_Msk (0x01UL << SCT_DMAREQ0_DEV_0_12_Pos) /*!< SCT DMAREQ0: DEV_0_12 Mask */ -#define SCT_DMAREQ0_DEV_0_13_Pos 13 /*!< SCT DMAREQ0: DEV_0_13 Position */ -#define SCT_DMAREQ0_DEV_0_13_Msk (0x01UL << SCT_DMAREQ0_DEV_0_13_Pos) /*!< SCT DMAREQ0: DEV_0_13 Mask */ -#define SCT_DMAREQ0_DEV_0_14_Pos 14 /*!< SCT DMAREQ0: DEV_0_14 Position */ -#define SCT_DMAREQ0_DEV_0_14_Msk (0x01UL << SCT_DMAREQ0_DEV_0_14_Pos) /*!< SCT DMAREQ0: DEV_0_14 Mask */ -#define SCT_DMAREQ0_DEV_0_15_Pos 15 /*!< SCT DMAREQ0: DEV_0_15 Position */ -#define SCT_DMAREQ0_DEV_0_15_Msk (0x01UL << SCT_DMAREQ0_DEV_0_15_Pos) /*!< SCT DMAREQ0: DEV_0_15 Mask */ -#define SCT_DMAREQ0_DRL0_Pos 30 /*!< SCT DMAREQ0: DRL0 Position */ -#define SCT_DMAREQ0_DRL0_Msk (0x01UL << SCT_DMAREQ0_DRL0_Pos) /*!< SCT DMAREQ0: DRL0 Mask */ -#define SCT_DMAREQ0_DRQ0_Pos 31 /*!< SCT DMAREQ0: DRQ0 Position */ -#define SCT_DMAREQ0_DRQ0_Msk (0x01UL << SCT_DMAREQ0_DRQ0_Pos) /*!< SCT DMAREQ0: DRQ0 Mask */ - -// --------------------------------------- SCT_DMAREQ1 ------------------------------------------ -#define SCT_DMAREQ1_DEV_1_0_Pos 0 /*!< SCT DMAREQ1: DEV_1_0 Position */ -#define SCT_DMAREQ1_DEV_1_0_Msk (0x01UL << SCT_DMAREQ1_DEV_1_0_Pos) /*!< SCT DMAREQ1: DEV_1_0 Mask */ -#define SCT_DMAREQ1_DEV_1_1_Pos 1 /*!< SCT DMAREQ1: DEV_1_1 Position */ -#define SCT_DMAREQ1_DEV_1_1_Msk (0x01UL << SCT_DMAREQ1_DEV_1_1_Pos) /*!< SCT DMAREQ1: DEV_1_1 Mask */ -#define SCT_DMAREQ1_DEV_1_2_Pos 2 /*!< SCT DMAREQ1: DEV_1_2 Position */ -#define SCT_DMAREQ1_DEV_1_2_Msk (0x01UL << SCT_DMAREQ1_DEV_1_2_Pos) /*!< SCT DMAREQ1: DEV_1_2 Mask */ -#define SCT_DMAREQ1_DEV_1_3_Pos 3 /*!< SCT DMAREQ1: DEV_1_3 Position */ -#define SCT_DMAREQ1_DEV_1_3_Msk (0x01UL << SCT_DMAREQ1_DEV_1_3_Pos) /*!< SCT DMAREQ1: DEV_1_3 Mask */ -#define SCT_DMAREQ1_DEV_1_4_Pos 4 /*!< SCT DMAREQ1: DEV_1_4 Position */ -#define SCT_DMAREQ1_DEV_1_4_Msk (0x01UL << SCT_DMAREQ1_DEV_1_4_Pos) /*!< SCT DMAREQ1: DEV_1_4 Mask */ -#define SCT_DMAREQ1_DEV_1_5_Pos 5 /*!< SCT DMAREQ1: DEV_1_5 Position */ -#define SCT_DMAREQ1_DEV_1_5_Msk (0x01UL << SCT_DMAREQ1_DEV_1_5_Pos) /*!< SCT DMAREQ1: DEV_1_5 Mask */ -#define SCT_DMAREQ1_DEV_1_6_Pos 6 /*!< SCT DMAREQ1: DEV_1_6 Position */ -#define SCT_DMAREQ1_DEV_1_6_Msk (0x01UL << SCT_DMAREQ1_DEV_1_6_Pos) /*!< SCT DMAREQ1: DEV_1_6 Mask */ -#define SCT_DMAREQ1_DEV_1_7_Pos 7 /*!< SCT DMAREQ1: DEV_1_7 Position */ -#define SCT_DMAREQ1_DEV_1_7_Msk (0x01UL << SCT_DMAREQ1_DEV_1_7_Pos) /*!< SCT DMAREQ1: DEV_1_7 Mask */ -#define SCT_DMAREQ1_DEV_1_8_Pos 8 /*!< SCT DMAREQ1: DEV_1_8 Position */ -#define SCT_DMAREQ1_DEV_1_8_Msk (0x01UL << SCT_DMAREQ1_DEV_1_8_Pos) /*!< SCT DMAREQ1: DEV_1_8 Mask */ -#define SCT_DMAREQ1_DEV_1_9_Pos 9 /*!< SCT DMAREQ1: DEV_1_9 Position */ -#define SCT_DMAREQ1_DEV_1_9_Msk (0x01UL << SCT_DMAREQ1_DEV_1_9_Pos) /*!< SCT DMAREQ1: DEV_1_9 Mask */ -#define SCT_DMAREQ1_DEV_1_10_Pos 10 /*!< SCT DMAREQ1: DEV_1_10 Position */ -#define SCT_DMAREQ1_DEV_1_10_Msk (0x01UL << SCT_DMAREQ1_DEV_1_10_Pos) /*!< SCT DMAREQ1: DEV_1_10 Mask */ -#define SCT_DMAREQ1_DEV_1_11_Pos 11 /*!< SCT DMAREQ1: DEV_1_11 Position */ -#define SCT_DMAREQ1_DEV_1_11_Msk (0x01UL << SCT_DMAREQ1_DEV_1_11_Pos) /*!< SCT DMAREQ1: DEV_1_11 Mask */ -#define SCT_DMAREQ1_DEV_1_12_Pos 12 /*!< SCT DMAREQ1: DEV_1_12 Position */ -#define SCT_DMAREQ1_DEV_1_12_Msk (0x01UL << SCT_DMAREQ1_DEV_1_12_Pos) /*!< SCT DMAREQ1: DEV_1_12 Mask */ -#define SCT_DMAREQ1_DEV_1_13_Pos 13 /*!< SCT DMAREQ1: DEV_1_13 Position */ -#define SCT_DMAREQ1_DEV_1_13_Msk (0x01UL << SCT_DMAREQ1_DEV_1_13_Pos) /*!< SCT DMAREQ1: DEV_1_13 Mask */ -#define SCT_DMAREQ1_DEV_1_14_Pos 14 /*!< SCT DMAREQ1: DEV_1_14 Position */ -#define SCT_DMAREQ1_DEV_1_14_Msk (0x01UL << SCT_DMAREQ1_DEV_1_14_Pos) /*!< SCT DMAREQ1: DEV_1_14 Mask */ -#define SCT_DMAREQ1_DEV_1_15_Pos 15 /*!< SCT DMAREQ1: DEV_1_15 Position */ -#define SCT_DMAREQ1_DEV_1_15_Msk (0x01UL << SCT_DMAREQ1_DEV_1_15_Pos) /*!< SCT DMAREQ1: DEV_1_15 Mask */ -#define SCT_DMAREQ1_DRL1_Pos 30 /*!< SCT DMAREQ1: DRL1 Position */ -#define SCT_DMAREQ1_DRL1_Msk (0x01UL << SCT_DMAREQ1_DRL1_Pos) /*!< SCT DMAREQ1: DRL1 Mask */ -#define SCT_DMAREQ1_DRQ1_Pos 31 /*!< SCT DMAREQ1: DRQ1 Position */ -#define SCT_DMAREQ1_DRQ1_Msk (0x01UL << SCT_DMAREQ1_DRQ1_Pos) /*!< SCT DMAREQ1: DRQ1 Mask */ - -// ---------------------------------------- SCT_EVEN -------------------------------------------- -#define SCT_EVEN_IEN0_Pos 0 /*!< SCT EVEN: IEN0 Position */ -#define SCT_EVEN_IEN0_Msk (0x01UL << SCT_EVEN_IEN0_Pos) /*!< SCT EVEN: IEN0 Mask */ -#define SCT_EVEN_IEN1_Pos 1 /*!< SCT EVEN: IEN1 Position */ -#define SCT_EVEN_IEN1_Msk (0x01UL << SCT_EVEN_IEN1_Pos) /*!< SCT EVEN: IEN1 Mask */ -#define SCT_EVEN_IEN2_Pos 2 /*!< SCT EVEN: IEN2 Position */ -#define SCT_EVEN_IEN2_Msk (0x01UL << SCT_EVEN_IEN2_Pos) /*!< SCT EVEN: IEN2 Mask */ -#define SCT_EVEN_IEN3_Pos 3 /*!< SCT EVEN: IEN3 Position */ -#define SCT_EVEN_IEN3_Msk (0x01UL << SCT_EVEN_IEN3_Pos) /*!< SCT EVEN: IEN3 Mask */ -#define SCT_EVEN_IEN4_Pos 4 /*!< SCT EVEN: IEN4 Position */ -#define SCT_EVEN_IEN4_Msk (0x01UL << SCT_EVEN_IEN4_Pos) /*!< SCT EVEN: IEN4 Mask */ -#define SCT_EVEN_IEN5_Pos 5 /*!< SCT EVEN: IEN5 Position */ -#define SCT_EVEN_IEN5_Msk (0x01UL << SCT_EVEN_IEN5_Pos) /*!< SCT EVEN: IEN5 Mask */ -#define SCT_EVEN_IEN6_Pos 6 /*!< SCT EVEN: IEN6 Position */ -#define SCT_EVEN_IEN6_Msk (0x01UL << SCT_EVEN_IEN6_Pos) /*!< SCT EVEN: IEN6 Mask */ -#define SCT_EVEN_IEN7_Pos 7 /*!< SCT EVEN: IEN7 Position */ -#define SCT_EVEN_IEN7_Msk (0x01UL << SCT_EVEN_IEN7_Pos) /*!< SCT EVEN: IEN7 Mask */ -#define SCT_EVEN_IEN8_Pos 8 /*!< SCT EVEN: IEN8 Position */ -#define SCT_EVEN_IEN8_Msk (0x01UL << SCT_EVEN_IEN8_Pos) /*!< SCT EVEN: IEN8 Mask */ -#define SCT_EVEN_IEN9_Pos 9 /*!< SCT EVEN: IEN9 Position */ -#define SCT_EVEN_IEN9_Msk (0x01UL << SCT_EVEN_IEN9_Pos) /*!< SCT EVEN: IEN9 Mask */ -#define SCT_EVEN_IEN10_Pos 10 /*!< SCT EVEN: IEN10 Position */ -#define SCT_EVEN_IEN10_Msk (0x01UL << SCT_EVEN_IEN10_Pos) /*!< SCT EVEN: IEN10 Mask */ -#define SCT_EVEN_IEN11_Pos 11 /*!< SCT EVEN: IEN11 Position */ -#define SCT_EVEN_IEN11_Msk (0x01UL << SCT_EVEN_IEN11_Pos) /*!< SCT EVEN: IEN11 Mask */ -#define SCT_EVEN_IEN12_Pos 12 /*!< SCT EVEN: IEN12 Position */ -#define SCT_EVEN_IEN12_Msk (0x01UL << SCT_EVEN_IEN12_Pos) /*!< SCT EVEN: IEN12 Mask */ -#define SCT_EVEN_IEN13_Pos 13 /*!< SCT EVEN: IEN13 Position */ -#define SCT_EVEN_IEN13_Msk (0x01UL << SCT_EVEN_IEN13_Pos) /*!< SCT EVEN: IEN13 Mask */ -#define SCT_EVEN_IEN14_Pos 14 /*!< SCT EVEN: IEN14 Position */ -#define SCT_EVEN_IEN14_Msk (0x01UL << SCT_EVEN_IEN14_Pos) /*!< SCT EVEN: IEN14 Mask */ -#define SCT_EVEN_IEN15_Pos 15 /*!< SCT EVEN: IEN15 Position */ -#define SCT_EVEN_IEN15_Msk (0x01UL << SCT_EVEN_IEN15_Pos) /*!< SCT EVEN: IEN15 Mask */ - -// --------------------------------------- SCT_EVFLAG ------------------------------------------- -#define SCT_EVFLAG_FLAG0_Pos 0 /*!< SCT EVFLAG: FLAG0 Position */ -#define SCT_EVFLAG_FLAG0_Msk (0x01UL << SCT_EVFLAG_FLAG0_Pos) /*!< SCT EVFLAG: FLAG0 Mask */ -#define SCT_EVFLAG_FLAG1_Pos 1 /*!< SCT EVFLAG: FLAG1 Position */ -#define SCT_EVFLAG_FLAG1_Msk (0x01UL << SCT_EVFLAG_FLAG1_Pos) /*!< SCT EVFLAG: FLAG1 Mask */ -#define SCT_EVFLAG_FLAG2_Pos 2 /*!< SCT EVFLAG: FLAG2 Position */ -#define SCT_EVFLAG_FLAG2_Msk (0x01UL << SCT_EVFLAG_FLAG2_Pos) /*!< SCT EVFLAG: FLAG2 Mask */ -#define SCT_EVFLAG_FLAG3_Pos 3 /*!< SCT EVFLAG: FLAG3 Position */ -#define SCT_EVFLAG_FLAG3_Msk (0x01UL << SCT_EVFLAG_FLAG3_Pos) /*!< SCT EVFLAG: FLAG3 Mask */ -#define SCT_EVFLAG_FLAG4_Pos 4 /*!< SCT EVFLAG: FLAG4 Position */ -#define SCT_EVFLAG_FLAG4_Msk (0x01UL << SCT_EVFLAG_FLAG4_Pos) /*!< SCT EVFLAG: FLAG4 Mask */ -#define SCT_EVFLAG_FLAG5_Pos 5 /*!< SCT EVFLAG: FLAG5 Position */ -#define SCT_EVFLAG_FLAG5_Msk (0x01UL << SCT_EVFLAG_FLAG5_Pos) /*!< SCT EVFLAG: FLAG5 Mask */ -#define SCT_EVFLAG_FLAG6_Pos 6 /*!< SCT EVFLAG: FLAG6 Position */ -#define SCT_EVFLAG_FLAG6_Msk (0x01UL << SCT_EVFLAG_FLAG6_Pos) /*!< SCT EVFLAG: FLAG6 Mask */ -#define SCT_EVFLAG_FLAG7_Pos 7 /*!< SCT EVFLAG: FLAG7 Position */ -#define SCT_EVFLAG_FLAG7_Msk (0x01UL << SCT_EVFLAG_FLAG7_Pos) /*!< SCT EVFLAG: FLAG7 Mask */ -#define SCT_EVFLAG_FLAG8_Pos 8 /*!< SCT EVFLAG: FLAG8 Position */ -#define SCT_EVFLAG_FLAG8_Msk (0x01UL << SCT_EVFLAG_FLAG8_Pos) /*!< SCT EVFLAG: FLAG8 Mask */ -#define SCT_EVFLAG_FLAG9_Pos 9 /*!< SCT EVFLAG: FLAG9 Position */ -#define SCT_EVFLAG_FLAG9_Msk (0x01UL << SCT_EVFLAG_FLAG9_Pos) /*!< SCT EVFLAG: FLAG9 Mask */ -#define SCT_EVFLAG_FLAG10_Pos 10 /*!< SCT EVFLAG: FLAG10 Position */ -#define SCT_EVFLAG_FLAG10_Msk (0x01UL << SCT_EVFLAG_FLAG10_Pos) /*!< SCT EVFLAG: FLAG10 Mask */ -#define SCT_EVFLAG_FLAG11_Pos 11 /*!< SCT EVFLAG: FLAG11 Position */ -#define SCT_EVFLAG_FLAG11_Msk (0x01UL << SCT_EVFLAG_FLAG11_Pos) /*!< SCT EVFLAG: FLAG11 Mask */ -#define SCT_EVFLAG_FLAG12_Pos 12 /*!< SCT EVFLAG: FLAG12 Position */ -#define SCT_EVFLAG_FLAG12_Msk (0x01UL << SCT_EVFLAG_FLAG12_Pos) /*!< SCT EVFLAG: FLAG12 Mask */ -#define SCT_EVFLAG_FLAG13_Pos 13 /*!< SCT EVFLAG: FLAG13 Position */ -#define SCT_EVFLAG_FLAG13_Msk (0x01UL << SCT_EVFLAG_FLAG13_Pos) /*!< SCT EVFLAG: FLAG13 Mask */ -#define SCT_EVFLAG_FLAG14_Pos 14 /*!< SCT EVFLAG: FLAG14 Position */ -#define SCT_EVFLAG_FLAG14_Msk (0x01UL << SCT_EVFLAG_FLAG14_Pos) /*!< SCT EVFLAG: FLAG14 Mask */ -#define SCT_EVFLAG_FLAG15_Pos 15 /*!< SCT EVFLAG: FLAG15 Position */ -#define SCT_EVFLAG_FLAG15_Msk (0x01UL << SCT_EVFLAG_FLAG15_Pos) /*!< SCT EVFLAG: FLAG15 Mask */ - -// ---------------------------------------- SCT_CONEN ------------------------------------------- -#define SCT_CONEN_NCEN0_Pos 0 /*!< SCT CONEN: NCEN0 Position */ -#define SCT_CONEN_NCEN0_Msk (0x01UL << SCT_CONEN_NCEN0_Pos) /*!< SCT CONEN: NCEN0 Mask */ -#define SCT_CONEN_NCEN1_Pos 1 /*!< SCT CONEN: NCEN1 Position */ -#define SCT_CONEN_NCEN1_Msk (0x01UL << SCT_CONEN_NCEN1_Pos) /*!< SCT CONEN: NCEN1 Mask */ -#define SCT_CONEN_NCEN2_Pos 2 /*!< SCT CONEN: NCEN2 Position */ -#define SCT_CONEN_NCEN2_Msk (0x01UL << SCT_CONEN_NCEN2_Pos) /*!< SCT CONEN: NCEN2 Mask */ -#define SCT_CONEN_NCEN3_Pos 3 /*!< SCT CONEN: NCEN3 Position */ -#define SCT_CONEN_NCEN3_Msk (0x01UL << SCT_CONEN_NCEN3_Pos) /*!< SCT CONEN: NCEN3 Mask */ -#define SCT_CONEN_NCEN4_Pos 4 /*!< SCT CONEN: NCEN4 Position */ -#define SCT_CONEN_NCEN4_Msk (0x01UL << SCT_CONEN_NCEN4_Pos) /*!< SCT CONEN: NCEN4 Mask */ -#define SCT_CONEN_NCEN5_Pos 5 /*!< SCT CONEN: NCEN5 Position */ -#define SCT_CONEN_NCEN5_Msk (0x01UL << SCT_CONEN_NCEN5_Pos) /*!< SCT CONEN: NCEN5 Mask */ -#define SCT_CONEN_NCEN6_Pos 6 /*!< SCT CONEN: NCEN6 Position */ -#define SCT_CONEN_NCEN6_Msk (0x01UL << SCT_CONEN_NCEN6_Pos) /*!< SCT CONEN: NCEN6 Mask */ -#define SCT_CONEN_NCEN7_Pos 7 /*!< SCT CONEN: NCEN7 Position */ -#define SCT_CONEN_NCEN7_Msk (0x01UL << SCT_CONEN_NCEN7_Pos) /*!< SCT CONEN: NCEN7 Mask */ -#define SCT_CONEN_NCEN8_Pos 8 /*!< SCT CONEN: NCEN8 Position */ -#define SCT_CONEN_NCEN8_Msk (0x01UL << SCT_CONEN_NCEN8_Pos) /*!< SCT CONEN: NCEN8 Mask */ -#define SCT_CONEN_NCEN9_Pos 9 /*!< SCT CONEN: NCEN9 Position */ -#define SCT_CONEN_NCEN9_Msk (0x01UL << SCT_CONEN_NCEN9_Pos) /*!< SCT CONEN: NCEN9 Mask */ -#define SCT_CONEN_NCEN10_Pos 10 /*!< SCT CONEN: NCEN10 Position */ -#define SCT_CONEN_NCEN10_Msk (0x01UL << SCT_CONEN_NCEN10_Pos) /*!< SCT CONEN: NCEN10 Mask */ -#define SCT_CONEN_NCEN11_Pos 11 /*!< SCT CONEN: NCEN11 Position */ -#define SCT_CONEN_NCEN11_Msk (0x01UL << SCT_CONEN_NCEN11_Pos) /*!< SCT CONEN: NCEN11 Mask */ -#define SCT_CONEN_NCEN12_Pos 12 /*!< SCT CONEN: NCEN12 Position */ -#define SCT_CONEN_NCEN12_Msk (0x01UL << SCT_CONEN_NCEN12_Pos) /*!< SCT CONEN: NCEN12 Mask */ -#define SCT_CONEN_NCEN13_Pos 13 /*!< SCT CONEN: NCEN13 Position */ -#define SCT_CONEN_NCEN13_Msk (0x01UL << SCT_CONEN_NCEN13_Pos) /*!< SCT CONEN: NCEN13 Mask */ -#define SCT_CONEN_NCEN14_Pos 14 /*!< SCT CONEN: NCEN14 Position */ -#define SCT_CONEN_NCEN14_Msk (0x01UL << SCT_CONEN_NCEN14_Pos) /*!< SCT CONEN: NCEN14 Mask */ -#define SCT_CONEN_NCEN15_Pos 15 /*!< SCT CONEN: NCEN15 Position */ -#define SCT_CONEN_NCEN15_Msk (0x01UL << SCT_CONEN_NCEN15_Pos) /*!< SCT CONEN: NCEN15 Mask */ - -// --------------------------------------- SCT_CONFLAG ------------------------------------------ -#define SCT_CONFLAG_NCFLAG0_Pos 0 /*!< SCT CONFLAG: NCFLAG0 Position */ -#define SCT_CONFLAG_NCFLAG0_Msk (0x01UL << SCT_CONFLAG_NCFLAG0_Pos) /*!< SCT CONFLAG: NCFLAG0 Mask */ -#define SCT_CONFLAG_NCFLAG1_Pos 1 /*!< SCT CONFLAG: NCFLAG1 Position */ -#define SCT_CONFLAG_NCFLAG1_Msk (0x01UL << SCT_CONFLAG_NCFLAG1_Pos) /*!< SCT CONFLAG: NCFLAG1 Mask */ -#define SCT_CONFLAG_NCFLAG2_Pos 2 /*!< SCT CONFLAG: NCFLAG2 Position */ -#define SCT_CONFLAG_NCFLAG2_Msk (0x01UL << SCT_CONFLAG_NCFLAG2_Pos) /*!< SCT CONFLAG: NCFLAG2 Mask */ -#define SCT_CONFLAG_NCFLAG3_Pos 3 /*!< SCT CONFLAG: NCFLAG3 Position */ -#define SCT_CONFLAG_NCFLAG3_Msk (0x01UL << SCT_CONFLAG_NCFLAG3_Pos) /*!< SCT CONFLAG: NCFLAG3 Mask */ -#define SCT_CONFLAG_NCFLAG4_Pos 4 /*!< SCT CONFLAG: NCFLAG4 Position */ -#define SCT_CONFLAG_NCFLAG4_Msk (0x01UL << SCT_CONFLAG_NCFLAG4_Pos) /*!< SCT CONFLAG: NCFLAG4 Mask */ -#define SCT_CONFLAG_NCFLAG5_Pos 5 /*!< SCT CONFLAG: NCFLAG5 Position */ -#define SCT_CONFLAG_NCFLAG5_Msk (0x01UL << SCT_CONFLAG_NCFLAG5_Pos) /*!< SCT CONFLAG: NCFLAG5 Mask */ -#define SCT_CONFLAG_NCFLAG6_Pos 6 /*!< SCT CONFLAG: NCFLAG6 Position */ -#define SCT_CONFLAG_NCFLAG6_Msk (0x01UL << SCT_CONFLAG_NCFLAG6_Pos) /*!< SCT CONFLAG: NCFLAG6 Mask */ -#define SCT_CONFLAG_NCFLAG7_Pos 7 /*!< SCT CONFLAG: NCFLAG7 Position */ -#define SCT_CONFLAG_NCFLAG7_Msk (0x01UL << SCT_CONFLAG_NCFLAG7_Pos) /*!< SCT CONFLAG: NCFLAG7 Mask */ -#define SCT_CONFLAG_NCFLAG8_Pos 8 /*!< SCT CONFLAG: NCFLAG8 Position */ -#define SCT_CONFLAG_NCFLAG8_Msk (0x01UL << SCT_CONFLAG_NCFLAG8_Pos) /*!< SCT CONFLAG: NCFLAG8 Mask */ -#define SCT_CONFLAG_NCFLAG9_Pos 9 /*!< SCT CONFLAG: NCFLAG9 Position */ -#define SCT_CONFLAG_NCFLAG9_Msk (0x01UL << SCT_CONFLAG_NCFLAG9_Pos) /*!< SCT CONFLAG: NCFLAG9 Mask */ -#define SCT_CONFLAG_NCFLAG10_Pos 10 /*!< SCT CONFLAG: NCFLAG10 Position */ -#define SCT_CONFLAG_NCFLAG10_Msk (0x01UL << SCT_CONFLAG_NCFLAG10_Pos) /*!< SCT CONFLAG: NCFLAG10 Mask */ -#define SCT_CONFLAG_NCFLAG11_Pos 11 /*!< SCT CONFLAG: NCFLAG11 Position */ -#define SCT_CONFLAG_NCFLAG11_Msk (0x01UL << SCT_CONFLAG_NCFLAG11_Pos) /*!< SCT CONFLAG: NCFLAG11 Mask */ -#define SCT_CONFLAG_NCFLAG12_Pos 12 /*!< SCT CONFLAG: NCFLAG12 Position */ -#define SCT_CONFLAG_NCFLAG12_Msk (0x01UL << SCT_CONFLAG_NCFLAG12_Pos) /*!< SCT CONFLAG: NCFLAG12 Mask */ -#define SCT_CONFLAG_NCFLAG13_Pos 13 /*!< SCT CONFLAG: NCFLAG13 Position */ -#define SCT_CONFLAG_NCFLAG13_Msk (0x01UL << SCT_CONFLAG_NCFLAG13_Pos) /*!< SCT CONFLAG: NCFLAG13 Mask */ -#define SCT_CONFLAG_NCFLAG14_Pos 14 /*!< SCT CONFLAG: NCFLAG14 Position */ -#define SCT_CONFLAG_NCFLAG14_Msk (0x01UL << SCT_CONFLAG_NCFLAG14_Pos) /*!< SCT CONFLAG: NCFLAG14 Mask */ -#define SCT_CONFLAG_NCFLAG15_Pos 15 /*!< SCT CONFLAG: NCFLAG15 Position */ -#define SCT_CONFLAG_NCFLAG15_Msk (0x01UL << SCT_CONFLAG_NCFLAG15_Pos) /*!< SCT CONFLAG: NCFLAG15 Mask */ -#define SCT_CONFLAG_BUSERRL_Pos 30 /*!< SCT CONFLAG: BUSERRL Position */ -#define SCT_CONFLAG_BUSERRL_Msk (0x01UL << SCT_CONFLAG_BUSERRL_Pos) /*!< SCT CONFLAG: BUSERRL Mask */ -#define SCT_CONFLAG_BUSERRH_Pos 31 /*!< SCT CONFLAG: BUSERRH Position */ -#define SCT_CONFLAG_BUSERRH_Msk (0x01UL << SCT_CONFLAG_BUSERRH_Pos) /*!< SCT CONFLAG: BUSERRH Mask */ - -// --------------------------------------- SCT_MATCH0 ------------------------------------------- -#define SCT_MATCH0_MATCHn_L_Pos 0 /*!< SCT MATCH0: MATCHn_L Position */ -#define SCT_MATCH0_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH0_MATCHn_L_Pos) /*!< SCT MATCH0: MATCHn_L Mask */ -#define SCT_MATCH0_MATCHn_H_Pos 16 /*!< SCT MATCH0: MATCHn_H Position */ -#define SCT_MATCH0_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH0_MATCHn_H_Pos) /*!< SCT MATCH0: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP0 -------------------------------------------- -#define SCT_CAP0_CAPn_L_Pos 0 /*!< SCT CAP0: CAPn_L Position */ -#define SCT_CAP0_CAPn_L_Msk (0x0000ffffUL << SCT_CAP0_CAPn_L_Pos) /*!< SCT CAP0: CAPn_L Mask */ -#define SCT_CAP0_CAPn_H_Pos 16 /*!< SCT CAP0: CAPn_H Position */ -#define SCT_CAP0_CAPn_H_Msk (0x0000ffffUL << SCT_CAP0_CAPn_H_Pos) /*!< SCT CAP0: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH1 ------------------------------------------- -#define SCT_MATCH1_MATCHn_L_Pos 0 /*!< SCT MATCH1: MATCHn_L Position */ -#define SCT_MATCH1_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH1_MATCHn_L_Pos) /*!< SCT MATCH1: MATCHn_L Mask */ -#define SCT_MATCH1_MATCHn_H_Pos 16 /*!< SCT MATCH1: MATCHn_H Position */ -#define SCT_MATCH1_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH1_MATCHn_H_Pos) /*!< SCT MATCH1: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP1 -------------------------------------------- -#define SCT_CAP1_CAPn_L_Pos 0 /*!< SCT CAP1: CAPn_L Position */ -#define SCT_CAP1_CAPn_L_Msk (0x0000ffffUL << SCT_CAP1_CAPn_L_Pos) /*!< SCT CAP1: CAPn_L Mask */ -#define SCT_CAP1_CAPn_H_Pos 16 /*!< SCT CAP1: CAPn_H Position */ -#define SCT_CAP1_CAPn_H_Msk (0x0000ffffUL << SCT_CAP1_CAPn_H_Pos) /*!< SCT CAP1: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH2 ------------------------------------------- -#define SCT_MATCH2_MATCHn_L_Pos 0 /*!< SCT MATCH2: MATCHn_L Position */ -#define SCT_MATCH2_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH2_MATCHn_L_Pos) /*!< SCT MATCH2: MATCHn_L Mask */ -#define SCT_MATCH2_MATCHn_H_Pos 16 /*!< SCT MATCH2: MATCHn_H Position */ -#define SCT_MATCH2_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH2_MATCHn_H_Pos) /*!< SCT MATCH2: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP2 -------------------------------------------- -#define SCT_CAP2_CAPn_L_Pos 0 /*!< SCT CAP2: CAPn_L Position */ -#define SCT_CAP2_CAPn_L_Msk (0x0000ffffUL << SCT_CAP2_CAPn_L_Pos) /*!< SCT CAP2: CAPn_L Mask */ -#define SCT_CAP2_CAPn_H_Pos 16 /*!< SCT CAP2: CAPn_H Position */ -#define SCT_CAP2_CAPn_H_Msk (0x0000ffffUL << SCT_CAP2_CAPn_H_Pos) /*!< SCT CAP2: CAPn_H Mask */ - -// ---------------------------------------- SCT_CAP3 -------------------------------------------- -#define SCT_CAP3_CAPn_L_Pos 0 /*!< SCT CAP3: CAPn_L Position */ -#define SCT_CAP3_CAPn_L_Msk (0x0000ffffUL << SCT_CAP3_CAPn_L_Pos) /*!< SCT CAP3: CAPn_L Mask */ -#define SCT_CAP3_CAPn_H_Pos 16 /*!< SCT CAP3: CAPn_H Position */ -#define SCT_CAP3_CAPn_H_Msk (0x0000ffffUL << SCT_CAP3_CAPn_H_Pos) /*!< SCT CAP3: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH3 ------------------------------------------- -#define SCT_MATCH3_MATCHn_L_Pos 0 /*!< SCT MATCH3: MATCHn_L Position */ -#define SCT_MATCH3_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH3_MATCHn_L_Pos) /*!< SCT MATCH3: MATCHn_L Mask */ -#define SCT_MATCH3_MATCHn_H_Pos 16 /*!< SCT MATCH3: MATCHn_H Position */ -#define SCT_MATCH3_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH3_MATCHn_H_Pos) /*!< SCT MATCH3: MATCHn_H Mask */ - -// --------------------------------------- SCT_MATCH4 ------------------------------------------- -#define SCT_MATCH4_MATCHn_L_Pos 0 /*!< SCT MATCH4: MATCHn_L Position */ -#define SCT_MATCH4_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH4_MATCHn_L_Pos) /*!< SCT MATCH4: MATCHn_L Mask */ -#define SCT_MATCH4_MATCHn_H_Pos 16 /*!< SCT MATCH4: MATCHn_H Position */ -#define SCT_MATCH4_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH4_MATCHn_H_Pos) /*!< SCT MATCH4: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP4 -------------------------------------------- -#define SCT_CAP4_CAPn_L_Pos 0 /*!< SCT CAP4: CAPn_L Position */ -#define SCT_CAP4_CAPn_L_Msk (0x0000ffffUL << SCT_CAP4_CAPn_L_Pos) /*!< SCT CAP4: CAPn_L Mask */ -#define SCT_CAP4_CAPn_H_Pos 16 /*!< SCT CAP4: CAPn_H Position */ -#define SCT_CAP4_CAPn_H_Msk (0x0000ffffUL << SCT_CAP4_CAPn_H_Pos) /*!< SCT CAP4: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH5 ------------------------------------------- -#define SCT_MATCH5_MATCHn_L_Pos 0 /*!< SCT MATCH5: MATCHn_L Position */ -#define SCT_MATCH5_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH5_MATCHn_L_Pos) /*!< SCT MATCH5: MATCHn_L Mask */ -#define SCT_MATCH5_MATCHn_H_Pos 16 /*!< SCT MATCH5: MATCHn_H Position */ -#define SCT_MATCH5_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH5_MATCHn_H_Pos) /*!< SCT MATCH5: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP5 -------------------------------------------- -#define SCT_CAP5_CAPn_L_Pos 0 /*!< SCT CAP5: CAPn_L Position */ -#define SCT_CAP5_CAPn_L_Msk (0x0000ffffUL << SCT_CAP5_CAPn_L_Pos) /*!< SCT CAP5: CAPn_L Mask */ -#define SCT_CAP5_CAPn_H_Pos 16 /*!< SCT CAP5: CAPn_H Position */ -#define SCT_CAP5_CAPn_H_Msk (0x0000ffffUL << SCT_CAP5_CAPn_H_Pos) /*!< SCT CAP5: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH6 ------------------------------------------- -#define SCT_MATCH6_MATCHn_L_Pos 0 /*!< SCT MATCH6: MATCHn_L Position */ -#define SCT_MATCH6_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH6_MATCHn_L_Pos) /*!< SCT MATCH6: MATCHn_L Mask */ -#define SCT_MATCH6_MATCHn_H_Pos 16 /*!< SCT MATCH6: MATCHn_H Position */ -#define SCT_MATCH6_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH6_MATCHn_H_Pos) /*!< SCT MATCH6: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP6 -------------------------------------------- -#define SCT_CAP6_CAPn_L_Pos 0 /*!< SCT CAP6: CAPn_L Position */ -#define SCT_CAP6_CAPn_L_Msk (0x0000ffffUL << SCT_CAP6_CAPn_L_Pos) /*!< SCT CAP6: CAPn_L Mask */ -#define SCT_CAP6_CAPn_H_Pos 16 /*!< SCT CAP6: CAPn_H Position */ -#define SCT_CAP6_CAPn_H_Msk (0x0000ffffUL << SCT_CAP6_CAPn_H_Pos) /*!< SCT CAP6: CAPn_H Mask */ - -// ---------------------------------------- SCT_CAP7 -------------------------------------------- -#define SCT_CAP7_CAPn_L_Pos 0 /*!< SCT CAP7: CAPn_L Position */ -#define SCT_CAP7_CAPn_L_Msk (0x0000ffffUL << SCT_CAP7_CAPn_L_Pos) /*!< SCT CAP7: CAPn_L Mask */ -#define SCT_CAP7_CAPn_H_Pos 16 /*!< SCT CAP7: CAPn_H Position */ -#define SCT_CAP7_CAPn_H_Msk (0x0000ffffUL << SCT_CAP7_CAPn_H_Pos) /*!< SCT CAP7: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH7 ------------------------------------------- -#define SCT_MATCH7_MATCHn_L_Pos 0 /*!< SCT MATCH7: MATCHn_L Position */ -#define SCT_MATCH7_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH7_MATCHn_L_Pos) /*!< SCT MATCH7: MATCHn_L Mask */ -#define SCT_MATCH7_MATCHn_H_Pos 16 /*!< SCT MATCH7: MATCHn_H Position */ -#define SCT_MATCH7_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH7_MATCHn_H_Pos) /*!< SCT MATCH7: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP8 -------------------------------------------- -#define SCT_CAP8_CAPn_L_Pos 0 /*!< SCT CAP8: CAPn_L Position */ -#define SCT_CAP8_CAPn_L_Msk (0x0000ffffUL << SCT_CAP8_CAPn_L_Pos) /*!< SCT CAP8: CAPn_L Mask */ -#define SCT_CAP8_CAPn_H_Pos 16 /*!< SCT CAP8: CAPn_H Position */ -#define SCT_CAP8_CAPn_H_Msk (0x0000ffffUL << SCT_CAP8_CAPn_H_Pos) /*!< SCT CAP8: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH8 ------------------------------------------- -#define SCT_MATCH8_MATCHn_L_Pos 0 /*!< SCT MATCH8: MATCHn_L Position */ -#define SCT_MATCH8_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH8_MATCHn_L_Pos) /*!< SCT MATCH8: MATCHn_L Mask */ -#define SCT_MATCH8_MATCHn_H_Pos 16 /*!< SCT MATCH8: MATCHn_H Position */ -#define SCT_MATCH8_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH8_MATCHn_H_Pos) /*!< SCT MATCH8: MATCHn_H Mask */ - -// --------------------------------------- SCT_MATCH9 ------------------------------------------- -#define SCT_MATCH9_MATCHn_L_Pos 0 /*!< SCT MATCH9: MATCHn_L Position */ -#define SCT_MATCH9_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH9_MATCHn_L_Pos) /*!< SCT MATCH9: MATCHn_L Mask */ -#define SCT_MATCH9_MATCHn_H_Pos 16 /*!< SCT MATCH9: MATCHn_H Position */ -#define SCT_MATCH9_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH9_MATCHn_H_Pos) /*!< SCT MATCH9: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP9 -------------------------------------------- -#define SCT_CAP9_CAPn_L_Pos 0 /*!< SCT CAP9: CAPn_L Position */ -#define SCT_CAP9_CAPn_L_Msk (0x0000ffffUL << SCT_CAP9_CAPn_L_Pos) /*!< SCT CAP9: CAPn_L Mask */ -#define SCT_CAP9_CAPn_H_Pos 16 /*!< SCT CAP9: CAPn_H Position */ -#define SCT_CAP9_CAPn_H_Msk (0x0000ffffUL << SCT_CAP9_CAPn_H_Pos) /*!< SCT CAP9: CAPn_H Mask */ - -// ---------------------------------------- SCT_CAP10 ------------------------------------------- -#define SCT_CAP10_CAPn_L_Pos 0 /*!< SCT CAP10: CAPn_L Position */ -#define SCT_CAP10_CAPn_L_Msk (0x0000ffffUL << SCT_CAP10_CAPn_L_Pos) /*!< SCT CAP10: CAPn_L Mask */ -#define SCT_CAP10_CAPn_H_Pos 16 /*!< SCT CAP10: CAPn_H Position */ -#define SCT_CAP10_CAPn_H_Msk (0x0000ffffUL << SCT_CAP10_CAPn_H_Pos) /*!< SCT CAP10: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH10 ------------------------------------------ -#define SCT_MATCH10_MATCHn_L_Pos 0 /*!< SCT MATCH10: MATCHn_L Position */ -#define SCT_MATCH10_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH10_MATCHn_L_Pos) /*!< SCT MATCH10: MATCHn_L Mask */ -#define SCT_MATCH10_MATCHn_H_Pos 16 /*!< SCT MATCH10: MATCHn_H Position */ -#define SCT_MATCH10_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH10_MATCHn_H_Pos) /*!< SCT MATCH10: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP11 ------------------------------------------- -#define SCT_CAP11_CAPn_L_Pos 0 /*!< SCT CAP11: CAPn_L Position */ -#define SCT_CAP11_CAPn_L_Msk (0x0000ffffUL << SCT_CAP11_CAPn_L_Pos) /*!< SCT CAP11: CAPn_L Mask */ -#define SCT_CAP11_CAPn_H_Pos 16 /*!< SCT CAP11: CAPn_H Position */ -#define SCT_CAP11_CAPn_H_Msk (0x0000ffffUL << SCT_CAP11_CAPn_H_Pos) /*!< SCT CAP11: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH11 ------------------------------------------ -#define SCT_MATCH11_MATCHn_L_Pos 0 /*!< SCT MATCH11: MATCHn_L Position */ -#define SCT_MATCH11_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH11_MATCHn_L_Pos) /*!< SCT MATCH11: MATCHn_L Mask */ -#define SCT_MATCH11_MATCHn_H_Pos 16 /*!< SCT MATCH11: MATCHn_H Position */ -#define SCT_MATCH11_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH11_MATCHn_H_Pos) /*!< SCT MATCH11: MATCHn_H Mask */ - -// --------------------------------------- SCT_MATCH12 ------------------------------------------ -#define SCT_MATCH12_MATCHn_L_Pos 0 /*!< SCT MATCH12: MATCHn_L Position */ -#define SCT_MATCH12_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH12_MATCHn_L_Pos) /*!< SCT MATCH12: MATCHn_L Mask */ -#define SCT_MATCH12_MATCHn_H_Pos 16 /*!< SCT MATCH12: MATCHn_H Position */ -#define SCT_MATCH12_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH12_MATCHn_H_Pos) /*!< SCT MATCH12: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP12 ------------------------------------------- -#define SCT_CAP12_CAPn_L_Pos 0 /*!< SCT CAP12: CAPn_L Position */ -#define SCT_CAP12_CAPn_L_Msk (0x0000ffffUL << SCT_CAP12_CAPn_L_Pos) /*!< SCT CAP12: CAPn_L Mask */ -#define SCT_CAP12_CAPn_H_Pos 16 /*!< SCT CAP12: CAPn_H Position */ -#define SCT_CAP12_CAPn_H_Msk (0x0000ffffUL << SCT_CAP12_CAPn_H_Pos) /*!< SCT CAP12: CAPn_H Mask */ - -// ---------------------------------------- SCT_CAP13 ------------------------------------------- -#define SCT_CAP13_CAPn_L_Pos 0 /*!< SCT CAP13: CAPn_L Position */ -#define SCT_CAP13_CAPn_L_Msk (0x0000ffffUL << SCT_CAP13_CAPn_L_Pos) /*!< SCT CAP13: CAPn_L Mask */ -#define SCT_CAP13_CAPn_H_Pos 16 /*!< SCT CAP13: CAPn_H Position */ -#define SCT_CAP13_CAPn_H_Msk (0x0000ffffUL << SCT_CAP13_CAPn_H_Pos) /*!< SCT CAP13: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH13 ------------------------------------------ -#define SCT_MATCH13_MATCHn_L_Pos 0 /*!< SCT MATCH13: MATCHn_L Position */ -#define SCT_MATCH13_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH13_MATCHn_L_Pos) /*!< SCT MATCH13: MATCHn_L Mask */ -#define SCT_MATCH13_MATCHn_H_Pos 16 /*!< SCT MATCH13: MATCHn_H Position */ -#define SCT_MATCH13_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH13_MATCHn_H_Pos) /*!< SCT MATCH13: MATCHn_H Mask */ - -// --------------------------------------- SCT_MATCH14 ------------------------------------------ -#define SCT_MATCH14_MATCHn_L_Pos 0 /*!< SCT MATCH14: MATCHn_L Position */ -#define SCT_MATCH14_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH14_MATCHn_L_Pos) /*!< SCT MATCH14: MATCHn_L Mask */ -#define SCT_MATCH14_MATCHn_H_Pos 16 /*!< SCT MATCH14: MATCHn_H Position */ -#define SCT_MATCH14_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH14_MATCHn_H_Pos) /*!< SCT MATCH14: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP14 ------------------------------------------- -#define SCT_CAP14_CAPn_L_Pos 0 /*!< SCT CAP14: CAPn_L Position */ -#define SCT_CAP14_CAPn_L_Msk (0x0000ffffUL << SCT_CAP14_CAPn_L_Pos) /*!< SCT CAP14: CAPn_L Mask */ -#define SCT_CAP14_CAPn_H_Pos 16 /*!< SCT CAP14: CAPn_H Position */ -#define SCT_CAP14_CAPn_H_Msk (0x0000ffffUL << SCT_CAP14_CAPn_H_Pos) /*!< SCT CAP14: CAPn_H Mask */ - -// --------------------------------------- SCT_MATCH15 ------------------------------------------ -#define SCT_MATCH15_MATCHn_L_Pos 0 /*!< SCT MATCH15: MATCHn_L Position */ -#define SCT_MATCH15_MATCHn_L_Msk (0x0000ffffUL << SCT_MATCH15_MATCHn_L_Pos) /*!< SCT MATCH15: MATCHn_L Mask */ -#define SCT_MATCH15_MATCHn_H_Pos 16 /*!< SCT MATCH15: MATCHn_H Position */ -#define SCT_MATCH15_MATCHn_H_Msk (0x0000ffffUL << SCT_MATCH15_MATCHn_H_Pos) /*!< SCT MATCH15: MATCHn_H Mask */ - -// ---------------------------------------- SCT_CAP15 ------------------------------------------- -#define SCT_CAP15_CAPn_L_Pos 0 /*!< SCT CAP15: CAPn_L Position */ -#define SCT_CAP15_CAPn_L_Msk (0x0000ffffUL << SCT_CAP15_CAPn_L_Pos) /*!< SCT CAP15: CAPn_L Mask */ -#define SCT_CAP15_CAPn_H_Pos 16 /*!< SCT CAP15: CAPn_H Position */ -#define SCT_CAP15_CAPn_H_Msk (0x0000ffffUL << SCT_CAP15_CAPn_H_Pos) /*!< SCT CAP15: CAPn_H Mask */ - -// -------------------------------------- SCT_MATCHREL0 ----------------------------------------- -#define SCT_MATCHREL0_RELOADn_L_Pos 0 /*!< SCT MATCHREL0: RELOADn_L Position */ -#define SCT_MATCHREL0_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL0_RELOADn_L_Pos) /*!< SCT MATCHREL0: RELOADn_L Mask */ -#define SCT_MATCHREL0_RELOADn_H_Pos 16 /*!< SCT MATCHREL0: RELOADn_H Position */ -#define SCT_MATCHREL0_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL0_RELOADn_H_Pos) /*!< SCT MATCHREL0: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL0 ------------------------------------------ -#define SCT_CAPCTRL0_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL0: CAPCONn_L0 Position */ -#define SCT_CAPCTRL0_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L0_Pos) /*!< SCT CAPCTRL0: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL0: CAPCONn_L1 Position */ -#define SCT_CAPCTRL0_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L1_Pos) /*!< SCT CAPCTRL0: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL0: CAPCONn_L2 Position */ -#define SCT_CAPCTRL0_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L2_Pos) /*!< SCT CAPCTRL0: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL0: CAPCONn_L3 Position */ -#define SCT_CAPCTRL0_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L3_Pos) /*!< SCT CAPCTRL0: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL0: CAPCONn_L4 Position */ -#define SCT_CAPCTRL0_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L4_Pos) /*!< SCT CAPCTRL0: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL0: CAPCONn_L5 Position */ -#define SCT_CAPCTRL0_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L5_Pos) /*!< SCT CAPCTRL0: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL0: CAPCONn_L6 Position */ -#define SCT_CAPCTRL0_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L6_Pos) /*!< SCT CAPCTRL0: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL0: CAPCONn_L7 Position */ -#define SCT_CAPCTRL0_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L7_Pos) /*!< SCT CAPCTRL0: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL0: CAPCONn_L8 Position */ -#define SCT_CAPCTRL0_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L8_Pos) /*!< SCT CAPCTRL0: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL0: CAPCONn_L9 Position */ -#define SCT_CAPCTRL0_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L9_Pos) /*!< SCT CAPCTRL0: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL0: CAPCONn_L10 Position */ -#define SCT_CAPCTRL0_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L10_Pos) /*!< SCT CAPCTRL0: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL0: CAPCONn_L11 Position */ -#define SCT_CAPCTRL0_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L11_Pos) /*!< SCT CAPCTRL0: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL0: CAPCONn_L12 Position */ -#define SCT_CAPCTRL0_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L12_Pos) /*!< SCT CAPCTRL0: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL0: CAPCONn_L13 Position */ -#define SCT_CAPCTRL0_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L13_Pos) /*!< SCT CAPCTRL0: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL0: CAPCONn_L14 Position */ -#define SCT_CAPCTRL0_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L14_Pos) /*!< SCT CAPCTRL0: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL0_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL0: CAPCONn_L15 Position */ -#define SCT_CAPCTRL0_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL0_CAPCONn_L15_Pos) /*!< SCT CAPCTRL0: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL0_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL0: CAPCONn_H Position */ -#define SCT_CAPCTRL0_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL0_CAPCONn_H_Pos) /*!< SCT CAPCTRL0: CAPCONn_H Mask */ - -// -------------------------------------- SCT_MATCHREL1 ----------------------------------------- -#define SCT_MATCHREL1_RELOADn_L_Pos 0 /*!< SCT MATCHREL1: RELOADn_L Position */ -#define SCT_MATCHREL1_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL1_RELOADn_L_Pos) /*!< SCT MATCHREL1: RELOADn_L Mask */ -#define SCT_MATCHREL1_RELOADn_H_Pos 16 /*!< SCT MATCHREL1: RELOADn_H Position */ -#define SCT_MATCHREL1_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL1_RELOADn_H_Pos) /*!< SCT MATCHREL1: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL1 ------------------------------------------ -#define SCT_CAPCTRL1_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL1: CAPCONn_L0 Position */ -#define SCT_CAPCTRL1_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L0_Pos) /*!< SCT CAPCTRL1: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL1: CAPCONn_L1 Position */ -#define SCT_CAPCTRL1_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L1_Pos) /*!< SCT CAPCTRL1: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL1: CAPCONn_L2 Position */ -#define SCT_CAPCTRL1_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L2_Pos) /*!< SCT CAPCTRL1: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL1: CAPCONn_L3 Position */ -#define SCT_CAPCTRL1_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L3_Pos) /*!< SCT CAPCTRL1: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL1: CAPCONn_L4 Position */ -#define SCT_CAPCTRL1_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L4_Pos) /*!< SCT CAPCTRL1: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL1: CAPCONn_L5 Position */ -#define SCT_CAPCTRL1_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L5_Pos) /*!< SCT CAPCTRL1: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL1: CAPCONn_L6 Position */ -#define SCT_CAPCTRL1_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L6_Pos) /*!< SCT CAPCTRL1: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL1: CAPCONn_L7 Position */ -#define SCT_CAPCTRL1_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L7_Pos) /*!< SCT CAPCTRL1: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL1: CAPCONn_L8 Position */ -#define SCT_CAPCTRL1_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L8_Pos) /*!< SCT CAPCTRL1: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL1: CAPCONn_L9 Position */ -#define SCT_CAPCTRL1_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L9_Pos) /*!< SCT CAPCTRL1: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL1: CAPCONn_L10 Position */ -#define SCT_CAPCTRL1_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L10_Pos) /*!< SCT CAPCTRL1: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL1: CAPCONn_L11 Position */ -#define SCT_CAPCTRL1_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L11_Pos) /*!< SCT CAPCTRL1: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL1: CAPCONn_L12 Position */ -#define SCT_CAPCTRL1_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L12_Pos) /*!< SCT CAPCTRL1: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL1: CAPCONn_L13 Position */ -#define SCT_CAPCTRL1_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L13_Pos) /*!< SCT CAPCTRL1: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL1: CAPCONn_L14 Position */ -#define SCT_CAPCTRL1_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L14_Pos) /*!< SCT CAPCTRL1: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL1_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL1: CAPCONn_L15 Position */ -#define SCT_CAPCTRL1_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL1_CAPCONn_L15_Pos) /*!< SCT CAPCTRL1: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL1_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL1: CAPCONn_H Position */ -#define SCT_CAPCTRL1_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL1_CAPCONn_H_Pos) /*!< SCT CAPCTRL1: CAPCONn_H Mask */ - -// -------------------------------------- SCT_MATCHREL2 ----------------------------------------- -#define SCT_MATCHREL2_RELOADn_L_Pos 0 /*!< SCT MATCHREL2: RELOADn_L Position */ -#define SCT_MATCHREL2_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL2_RELOADn_L_Pos) /*!< SCT MATCHREL2: RELOADn_L Mask */ -#define SCT_MATCHREL2_RELOADn_H_Pos 16 /*!< SCT MATCHREL2: RELOADn_H Position */ -#define SCT_MATCHREL2_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL2_RELOADn_H_Pos) /*!< SCT MATCHREL2: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL2 ------------------------------------------ -#define SCT_CAPCTRL2_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL2: CAPCONn_L0 Position */ -#define SCT_CAPCTRL2_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L0_Pos) /*!< SCT CAPCTRL2: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL2: CAPCONn_L1 Position */ -#define SCT_CAPCTRL2_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L1_Pos) /*!< SCT CAPCTRL2: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL2: CAPCONn_L2 Position */ -#define SCT_CAPCTRL2_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L2_Pos) /*!< SCT CAPCTRL2: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL2: CAPCONn_L3 Position */ -#define SCT_CAPCTRL2_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L3_Pos) /*!< SCT CAPCTRL2: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL2: CAPCONn_L4 Position */ -#define SCT_CAPCTRL2_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L4_Pos) /*!< SCT CAPCTRL2: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL2: CAPCONn_L5 Position */ -#define SCT_CAPCTRL2_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L5_Pos) /*!< SCT CAPCTRL2: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL2: CAPCONn_L6 Position */ -#define SCT_CAPCTRL2_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L6_Pos) /*!< SCT CAPCTRL2: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL2: CAPCONn_L7 Position */ -#define SCT_CAPCTRL2_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L7_Pos) /*!< SCT CAPCTRL2: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL2: CAPCONn_L8 Position */ -#define SCT_CAPCTRL2_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L8_Pos) /*!< SCT CAPCTRL2: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL2: CAPCONn_L9 Position */ -#define SCT_CAPCTRL2_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L9_Pos) /*!< SCT CAPCTRL2: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL2: CAPCONn_L10 Position */ -#define SCT_CAPCTRL2_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L10_Pos) /*!< SCT CAPCTRL2: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL2: CAPCONn_L11 Position */ -#define SCT_CAPCTRL2_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L11_Pos) /*!< SCT CAPCTRL2: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL2: CAPCONn_L12 Position */ -#define SCT_CAPCTRL2_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L12_Pos) /*!< SCT CAPCTRL2: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL2: CAPCONn_L13 Position */ -#define SCT_CAPCTRL2_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L13_Pos) /*!< SCT CAPCTRL2: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL2: CAPCONn_L14 Position */ -#define SCT_CAPCTRL2_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L14_Pos) /*!< SCT CAPCTRL2: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL2_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL2: CAPCONn_L15 Position */ -#define SCT_CAPCTRL2_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL2_CAPCONn_L15_Pos) /*!< SCT CAPCTRL2: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL2_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL2: CAPCONn_H Position */ -#define SCT_CAPCTRL2_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL2_CAPCONn_H_Pos) /*!< SCT CAPCTRL2: CAPCONn_H Mask */ - -// -------------------------------------- SCT_MATCHREL3 ----------------------------------------- -#define SCT_MATCHREL3_RELOADn_L_Pos 0 /*!< SCT MATCHREL3: RELOADn_L Position */ -#define SCT_MATCHREL3_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL3_RELOADn_L_Pos) /*!< SCT MATCHREL3: RELOADn_L Mask */ -#define SCT_MATCHREL3_RELOADn_H_Pos 16 /*!< SCT MATCHREL3: RELOADn_H Position */ -#define SCT_MATCHREL3_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL3_RELOADn_H_Pos) /*!< SCT MATCHREL3: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL3 ------------------------------------------ -#define SCT_CAPCTRL3_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL3: CAPCONn_L0 Position */ -#define SCT_CAPCTRL3_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L0_Pos) /*!< SCT CAPCTRL3: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL3: CAPCONn_L1 Position */ -#define SCT_CAPCTRL3_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L1_Pos) /*!< SCT CAPCTRL3: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL3: CAPCONn_L2 Position */ -#define SCT_CAPCTRL3_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L2_Pos) /*!< SCT CAPCTRL3: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL3: CAPCONn_L3 Position */ -#define SCT_CAPCTRL3_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L3_Pos) /*!< SCT CAPCTRL3: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL3: CAPCONn_L4 Position */ -#define SCT_CAPCTRL3_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L4_Pos) /*!< SCT CAPCTRL3: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL3: CAPCONn_L5 Position */ -#define SCT_CAPCTRL3_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L5_Pos) /*!< SCT CAPCTRL3: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL3: CAPCONn_L6 Position */ -#define SCT_CAPCTRL3_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L6_Pos) /*!< SCT CAPCTRL3: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL3: CAPCONn_L7 Position */ -#define SCT_CAPCTRL3_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L7_Pos) /*!< SCT CAPCTRL3: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL3: CAPCONn_L8 Position */ -#define SCT_CAPCTRL3_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L8_Pos) /*!< SCT CAPCTRL3: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL3: CAPCONn_L9 Position */ -#define SCT_CAPCTRL3_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L9_Pos) /*!< SCT CAPCTRL3: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL3: CAPCONn_L10 Position */ -#define SCT_CAPCTRL3_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L10_Pos) /*!< SCT CAPCTRL3: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL3: CAPCONn_L11 Position */ -#define SCT_CAPCTRL3_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L11_Pos) /*!< SCT CAPCTRL3: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL3: CAPCONn_L12 Position */ -#define SCT_CAPCTRL3_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L12_Pos) /*!< SCT CAPCTRL3: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL3: CAPCONn_L13 Position */ -#define SCT_CAPCTRL3_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L13_Pos) /*!< SCT CAPCTRL3: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL3: CAPCONn_L14 Position */ -#define SCT_CAPCTRL3_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L14_Pos) /*!< SCT CAPCTRL3: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL3_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL3: CAPCONn_L15 Position */ -#define SCT_CAPCTRL3_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL3_CAPCONn_L15_Pos) /*!< SCT CAPCTRL3: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL3_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL3: CAPCONn_H Position */ -#define SCT_CAPCTRL3_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL3_CAPCONn_H_Pos) /*!< SCT CAPCTRL3: CAPCONn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL4 ------------------------------------------ -#define SCT_CAPCTRL4_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL4: CAPCONn_L0 Position */ -#define SCT_CAPCTRL4_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L0_Pos) /*!< SCT CAPCTRL4: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL4: CAPCONn_L1 Position */ -#define SCT_CAPCTRL4_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L1_Pos) /*!< SCT CAPCTRL4: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL4: CAPCONn_L2 Position */ -#define SCT_CAPCTRL4_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L2_Pos) /*!< SCT CAPCTRL4: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL4: CAPCONn_L3 Position */ -#define SCT_CAPCTRL4_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L3_Pos) /*!< SCT CAPCTRL4: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL4: CAPCONn_L4 Position */ -#define SCT_CAPCTRL4_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L4_Pos) /*!< SCT CAPCTRL4: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL4: CAPCONn_L5 Position */ -#define SCT_CAPCTRL4_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L5_Pos) /*!< SCT CAPCTRL4: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL4: CAPCONn_L6 Position */ -#define SCT_CAPCTRL4_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L6_Pos) /*!< SCT CAPCTRL4: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL4: CAPCONn_L7 Position */ -#define SCT_CAPCTRL4_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L7_Pos) /*!< SCT CAPCTRL4: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL4: CAPCONn_L8 Position */ -#define SCT_CAPCTRL4_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L8_Pos) /*!< SCT CAPCTRL4: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL4: CAPCONn_L9 Position */ -#define SCT_CAPCTRL4_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L9_Pos) /*!< SCT CAPCTRL4: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL4: CAPCONn_L10 Position */ -#define SCT_CAPCTRL4_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L10_Pos) /*!< SCT CAPCTRL4: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL4: CAPCONn_L11 Position */ -#define SCT_CAPCTRL4_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L11_Pos) /*!< SCT CAPCTRL4: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL4: CAPCONn_L12 Position */ -#define SCT_CAPCTRL4_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L12_Pos) /*!< SCT CAPCTRL4: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL4: CAPCONn_L13 Position */ -#define SCT_CAPCTRL4_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L13_Pos) /*!< SCT CAPCTRL4: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL4: CAPCONn_L14 Position */ -#define SCT_CAPCTRL4_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L14_Pos) /*!< SCT CAPCTRL4: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL4_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL4: CAPCONn_L15 Position */ -#define SCT_CAPCTRL4_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL4_CAPCONn_L15_Pos) /*!< SCT CAPCTRL4: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL4_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL4: CAPCONn_H Position */ -#define SCT_CAPCTRL4_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL4_CAPCONn_H_Pos) /*!< SCT CAPCTRL4: CAPCONn_H Mask */ - -// -------------------------------------- SCT_MATCHREL4 ----------------------------------------- -#define SCT_MATCHREL4_RELOADn_L_Pos 0 /*!< SCT MATCHREL4: RELOADn_L Position */ -#define SCT_MATCHREL4_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL4_RELOADn_L_Pos) /*!< SCT MATCHREL4: RELOADn_L Mask */ -#define SCT_MATCHREL4_RELOADn_H_Pos 16 /*!< SCT MATCHREL4: RELOADn_H Position */ -#define SCT_MATCHREL4_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL4_RELOADn_H_Pos) /*!< SCT MATCHREL4: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL5 ------------------------------------------ -#define SCT_CAPCTRL5_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL5: CAPCONn_L0 Position */ -#define SCT_CAPCTRL5_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L0_Pos) /*!< SCT CAPCTRL5: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL5: CAPCONn_L1 Position */ -#define SCT_CAPCTRL5_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L1_Pos) /*!< SCT CAPCTRL5: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL5: CAPCONn_L2 Position */ -#define SCT_CAPCTRL5_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L2_Pos) /*!< SCT CAPCTRL5: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL5: CAPCONn_L3 Position */ -#define SCT_CAPCTRL5_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L3_Pos) /*!< SCT CAPCTRL5: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL5: CAPCONn_L4 Position */ -#define SCT_CAPCTRL5_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L4_Pos) /*!< SCT CAPCTRL5: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL5: CAPCONn_L5 Position */ -#define SCT_CAPCTRL5_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L5_Pos) /*!< SCT CAPCTRL5: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL5: CAPCONn_L6 Position */ -#define SCT_CAPCTRL5_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L6_Pos) /*!< SCT CAPCTRL5: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL5: CAPCONn_L7 Position */ -#define SCT_CAPCTRL5_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L7_Pos) /*!< SCT CAPCTRL5: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL5: CAPCONn_L8 Position */ -#define SCT_CAPCTRL5_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L8_Pos) /*!< SCT CAPCTRL5: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL5: CAPCONn_L9 Position */ -#define SCT_CAPCTRL5_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L9_Pos) /*!< SCT CAPCTRL5: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL5: CAPCONn_L10 Position */ -#define SCT_CAPCTRL5_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L10_Pos) /*!< SCT CAPCTRL5: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL5: CAPCONn_L11 Position */ -#define SCT_CAPCTRL5_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L11_Pos) /*!< SCT CAPCTRL5: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL5: CAPCONn_L12 Position */ -#define SCT_CAPCTRL5_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L12_Pos) /*!< SCT CAPCTRL5: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL5: CAPCONn_L13 Position */ -#define SCT_CAPCTRL5_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L13_Pos) /*!< SCT CAPCTRL5: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL5: CAPCONn_L14 Position */ -#define SCT_CAPCTRL5_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L14_Pos) /*!< SCT CAPCTRL5: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL5_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL5: CAPCONn_L15 Position */ -#define SCT_CAPCTRL5_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL5_CAPCONn_L15_Pos) /*!< SCT CAPCTRL5: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL5_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL5: CAPCONn_H Position */ -#define SCT_CAPCTRL5_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL5_CAPCONn_H_Pos) /*!< SCT CAPCTRL5: CAPCONn_H Mask */ - -// -------------------------------------- SCT_MATCHREL5 ----------------------------------------- -#define SCT_MATCHREL5_RELOADn_L_Pos 0 /*!< SCT MATCHREL5: RELOADn_L Position */ -#define SCT_MATCHREL5_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL5_RELOADn_L_Pos) /*!< SCT MATCHREL5: RELOADn_L Mask */ -#define SCT_MATCHREL5_RELOADn_H_Pos 16 /*!< SCT MATCHREL5: RELOADn_H Position */ -#define SCT_MATCHREL5_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL5_RELOADn_H_Pos) /*!< SCT MATCHREL5: RELOADn_H Mask */ - -// -------------------------------------- SCT_MATCHREL6 ----------------------------------------- -#define SCT_MATCHREL6_RELOADn_L_Pos 0 /*!< SCT MATCHREL6: RELOADn_L Position */ -#define SCT_MATCHREL6_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL6_RELOADn_L_Pos) /*!< SCT MATCHREL6: RELOADn_L Mask */ -#define SCT_MATCHREL6_RELOADn_H_Pos 16 /*!< SCT MATCHREL6: RELOADn_H Position */ -#define SCT_MATCHREL6_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL6_RELOADn_H_Pos) /*!< SCT MATCHREL6: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL6 ------------------------------------------ -#define SCT_CAPCTRL6_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL6: CAPCONn_L0 Position */ -#define SCT_CAPCTRL6_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L0_Pos) /*!< SCT CAPCTRL6: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL6: CAPCONn_L1 Position */ -#define SCT_CAPCTRL6_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L1_Pos) /*!< SCT CAPCTRL6: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL6: CAPCONn_L2 Position */ -#define SCT_CAPCTRL6_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L2_Pos) /*!< SCT CAPCTRL6: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL6: CAPCONn_L3 Position */ -#define SCT_CAPCTRL6_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L3_Pos) /*!< SCT CAPCTRL6: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL6: CAPCONn_L4 Position */ -#define SCT_CAPCTRL6_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L4_Pos) /*!< SCT CAPCTRL6: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL6: CAPCONn_L5 Position */ -#define SCT_CAPCTRL6_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L5_Pos) /*!< SCT CAPCTRL6: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL6: CAPCONn_L6 Position */ -#define SCT_CAPCTRL6_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L6_Pos) /*!< SCT CAPCTRL6: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL6: CAPCONn_L7 Position */ -#define SCT_CAPCTRL6_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L7_Pos) /*!< SCT CAPCTRL6: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL6: CAPCONn_L8 Position */ -#define SCT_CAPCTRL6_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L8_Pos) /*!< SCT CAPCTRL6: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL6: CAPCONn_L9 Position */ -#define SCT_CAPCTRL6_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L9_Pos) /*!< SCT CAPCTRL6: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL6: CAPCONn_L10 Position */ -#define SCT_CAPCTRL6_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L10_Pos) /*!< SCT CAPCTRL6: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL6: CAPCONn_L11 Position */ -#define SCT_CAPCTRL6_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L11_Pos) /*!< SCT CAPCTRL6: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL6: CAPCONn_L12 Position */ -#define SCT_CAPCTRL6_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L12_Pos) /*!< SCT CAPCTRL6: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL6: CAPCONn_L13 Position */ -#define SCT_CAPCTRL6_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L13_Pos) /*!< SCT CAPCTRL6: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL6: CAPCONn_L14 Position */ -#define SCT_CAPCTRL6_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L14_Pos) /*!< SCT CAPCTRL6: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL6_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL6: CAPCONn_L15 Position */ -#define SCT_CAPCTRL6_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL6_CAPCONn_L15_Pos) /*!< SCT CAPCTRL6: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL6_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL6: CAPCONn_H Position */ -#define SCT_CAPCTRL6_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL6_CAPCONn_H_Pos) /*!< SCT CAPCTRL6: CAPCONn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL7 ------------------------------------------ -#define SCT_CAPCTRL7_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL7: CAPCONn_L0 Position */ -#define SCT_CAPCTRL7_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L0_Pos) /*!< SCT CAPCTRL7: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL7: CAPCONn_L1 Position */ -#define SCT_CAPCTRL7_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L1_Pos) /*!< SCT CAPCTRL7: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL7: CAPCONn_L2 Position */ -#define SCT_CAPCTRL7_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L2_Pos) /*!< SCT CAPCTRL7: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL7: CAPCONn_L3 Position */ -#define SCT_CAPCTRL7_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L3_Pos) /*!< SCT CAPCTRL7: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL7: CAPCONn_L4 Position */ -#define SCT_CAPCTRL7_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L4_Pos) /*!< SCT CAPCTRL7: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL7: CAPCONn_L5 Position */ -#define SCT_CAPCTRL7_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L5_Pos) /*!< SCT CAPCTRL7: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL7: CAPCONn_L6 Position */ -#define SCT_CAPCTRL7_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L6_Pos) /*!< SCT CAPCTRL7: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL7: CAPCONn_L7 Position */ -#define SCT_CAPCTRL7_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L7_Pos) /*!< SCT CAPCTRL7: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL7: CAPCONn_L8 Position */ -#define SCT_CAPCTRL7_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L8_Pos) /*!< SCT CAPCTRL7: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL7: CAPCONn_L9 Position */ -#define SCT_CAPCTRL7_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L9_Pos) /*!< SCT CAPCTRL7: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL7: CAPCONn_L10 Position */ -#define SCT_CAPCTRL7_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L10_Pos) /*!< SCT CAPCTRL7: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL7: CAPCONn_L11 Position */ -#define SCT_CAPCTRL7_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L11_Pos) /*!< SCT CAPCTRL7: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL7: CAPCONn_L12 Position */ -#define SCT_CAPCTRL7_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L12_Pos) /*!< SCT CAPCTRL7: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL7: CAPCONn_L13 Position */ -#define SCT_CAPCTRL7_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L13_Pos) /*!< SCT CAPCTRL7: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL7: CAPCONn_L14 Position */ -#define SCT_CAPCTRL7_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L14_Pos) /*!< SCT CAPCTRL7: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL7_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL7: CAPCONn_L15 Position */ -#define SCT_CAPCTRL7_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL7_CAPCONn_L15_Pos) /*!< SCT CAPCTRL7: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL7_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL7: CAPCONn_H Position */ -#define SCT_CAPCTRL7_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL7_CAPCONn_H_Pos) /*!< SCT CAPCTRL7: CAPCONn_H Mask */ - -// -------------------------------------- SCT_MATCHREL7 ----------------------------------------- -#define SCT_MATCHREL7_RELOADn_L_Pos 0 /*!< SCT MATCHREL7: RELOADn_L Position */ -#define SCT_MATCHREL7_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL7_RELOADn_L_Pos) /*!< SCT MATCHREL7: RELOADn_L Mask */ -#define SCT_MATCHREL7_RELOADn_H_Pos 16 /*!< SCT MATCHREL7: RELOADn_H Position */ -#define SCT_MATCHREL7_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL7_RELOADn_H_Pos) /*!< SCT MATCHREL7: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL8 ------------------------------------------ -#define SCT_CAPCTRL8_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL8: CAPCONn_L0 Position */ -#define SCT_CAPCTRL8_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L0_Pos) /*!< SCT CAPCTRL8: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL8: CAPCONn_L1 Position */ -#define SCT_CAPCTRL8_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L1_Pos) /*!< SCT CAPCTRL8: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL8: CAPCONn_L2 Position */ -#define SCT_CAPCTRL8_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L2_Pos) /*!< SCT CAPCTRL8: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL8: CAPCONn_L3 Position */ -#define SCT_CAPCTRL8_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L3_Pos) /*!< SCT CAPCTRL8: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL8: CAPCONn_L4 Position */ -#define SCT_CAPCTRL8_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L4_Pos) /*!< SCT CAPCTRL8: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL8: CAPCONn_L5 Position */ -#define SCT_CAPCTRL8_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L5_Pos) /*!< SCT CAPCTRL8: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL8: CAPCONn_L6 Position */ -#define SCT_CAPCTRL8_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L6_Pos) /*!< SCT CAPCTRL8: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL8: CAPCONn_L7 Position */ -#define SCT_CAPCTRL8_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L7_Pos) /*!< SCT CAPCTRL8: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL8: CAPCONn_L8 Position */ -#define SCT_CAPCTRL8_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L8_Pos) /*!< SCT CAPCTRL8: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL8: CAPCONn_L9 Position */ -#define SCT_CAPCTRL8_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L9_Pos) /*!< SCT CAPCTRL8: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL8: CAPCONn_L10 Position */ -#define SCT_CAPCTRL8_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L10_Pos) /*!< SCT CAPCTRL8: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL8: CAPCONn_L11 Position */ -#define SCT_CAPCTRL8_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L11_Pos) /*!< SCT CAPCTRL8: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL8: CAPCONn_L12 Position */ -#define SCT_CAPCTRL8_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L12_Pos) /*!< SCT CAPCTRL8: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL8: CAPCONn_L13 Position */ -#define SCT_CAPCTRL8_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L13_Pos) /*!< SCT CAPCTRL8: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL8: CAPCONn_L14 Position */ -#define SCT_CAPCTRL8_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L14_Pos) /*!< SCT CAPCTRL8: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL8_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL8: CAPCONn_L15 Position */ -#define SCT_CAPCTRL8_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL8_CAPCONn_L15_Pos) /*!< SCT CAPCTRL8: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL8_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL8: CAPCONn_H Position */ -#define SCT_CAPCTRL8_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL8_CAPCONn_H_Pos) /*!< SCT CAPCTRL8: CAPCONn_H Mask */ - -// -------------------------------------- SCT_MATCHREL8 ----------------------------------------- -#define SCT_MATCHREL8_RELOADn_L_Pos 0 /*!< SCT MATCHREL8: RELOADn_L Position */ -#define SCT_MATCHREL8_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL8_RELOADn_L_Pos) /*!< SCT MATCHREL8: RELOADn_L Mask */ -#define SCT_MATCHREL8_RELOADn_H_Pos 16 /*!< SCT MATCHREL8: RELOADn_H Position */ -#define SCT_MATCHREL8_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL8_RELOADn_H_Pos) /*!< SCT MATCHREL8: RELOADn_H Mask */ - -// -------------------------------------- SCT_MATCHREL9 ----------------------------------------- -#define SCT_MATCHREL9_RELOADn_L_Pos 0 /*!< SCT MATCHREL9: RELOADn_L Position */ -#define SCT_MATCHREL9_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL9_RELOADn_L_Pos) /*!< SCT MATCHREL9: RELOADn_L Mask */ -#define SCT_MATCHREL9_RELOADn_H_Pos 16 /*!< SCT MATCHREL9: RELOADn_H Position */ -#define SCT_MATCHREL9_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL9_RELOADn_H_Pos) /*!< SCT MATCHREL9: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL9 ------------------------------------------ -#define SCT_CAPCTRL9_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL9: CAPCONn_L0 Position */ -#define SCT_CAPCTRL9_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L0_Pos) /*!< SCT CAPCTRL9: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL9: CAPCONn_L1 Position */ -#define SCT_CAPCTRL9_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L1_Pos) /*!< SCT CAPCTRL9: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL9: CAPCONn_L2 Position */ -#define SCT_CAPCTRL9_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L2_Pos) /*!< SCT CAPCTRL9: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL9: CAPCONn_L3 Position */ -#define SCT_CAPCTRL9_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L3_Pos) /*!< SCT CAPCTRL9: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL9: CAPCONn_L4 Position */ -#define SCT_CAPCTRL9_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L4_Pos) /*!< SCT CAPCTRL9: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL9: CAPCONn_L5 Position */ -#define SCT_CAPCTRL9_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L5_Pos) /*!< SCT CAPCTRL9: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL9: CAPCONn_L6 Position */ -#define SCT_CAPCTRL9_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L6_Pos) /*!< SCT CAPCTRL9: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL9: CAPCONn_L7 Position */ -#define SCT_CAPCTRL9_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L7_Pos) /*!< SCT CAPCTRL9: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL9: CAPCONn_L8 Position */ -#define SCT_CAPCTRL9_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L8_Pos) /*!< SCT CAPCTRL9: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL9: CAPCONn_L9 Position */ -#define SCT_CAPCTRL9_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L9_Pos) /*!< SCT CAPCTRL9: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL9: CAPCONn_L10 Position */ -#define SCT_CAPCTRL9_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L10_Pos) /*!< SCT CAPCTRL9: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL9: CAPCONn_L11 Position */ -#define SCT_CAPCTRL9_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L11_Pos) /*!< SCT CAPCTRL9: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL9: CAPCONn_L12 Position */ -#define SCT_CAPCTRL9_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L12_Pos) /*!< SCT CAPCTRL9: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL9: CAPCONn_L13 Position */ -#define SCT_CAPCTRL9_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L13_Pos) /*!< SCT CAPCTRL9: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL9: CAPCONn_L14 Position */ -#define SCT_CAPCTRL9_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L14_Pos) /*!< SCT CAPCTRL9: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL9_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL9: CAPCONn_L15 Position */ -#define SCT_CAPCTRL9_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL9_CAPCONn_L15_Pos) /*!< SCT CAPCTRL9: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL9_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL9: CAPCONn_H Position */ -#define SCT_CAPCTRL9_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL9_CAPCONn_H_Pos) /*!< SCT CAPCTRL9: CAPCONn_H Mask */ - -// ------------------------------------- SCT_MATCHREL10 ----------------------------------------- -#define SCT_MATCHREL10_RELOADn_L_Pos 0 /*!< SCT MATCHREL10: RELOADn_L Position */ -#define SCT_MATCHREL10_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL10_RELOADn_L_Pos) /*!< SCT MATCHREL10: RELOADn_L Mask */ -#define SCT_MATCHREL10_RELOADn_H_Pos 16 /*!< SCT MATCHREL10: RELOADn_H Position */ -#define SCT_MATCHREL10_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL10_RELOADn_H_Pos) /*!< SCT MATCHREL10: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL10 ----------------------------------------- -#define SCT_CAPCTRL10_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL10: CAPCONn_L0 Position */ -#define SCT_CAPCTRL10_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L0_Pos) /*!< SCT CAPCTRL10: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL10: CAPCONn_L1 Position */ -#define SCT_CAPCTRL10_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L1_Pos) /*!< SCT CAPCTRL10: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL10: CAPCONn_L2 Position */ -#define SCT_CAPCTRL10_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L2_Pos) /*!< SCT CAPCTRL10: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL10: CAPCONn_L3 Position */ -#define SCT_CAPCTRL10_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L3_Pos) /*!< SCT CAPCTRL10: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL10: CAPCONn_L4 Position */ -#define SCT_CAPCTRL10_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L4_Pos) /*!< SCT CAPCTRL10: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL10: CAPCONn_L5 Position */ -#define SCT_CAPCTRL10_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L5_Pos) /*!< SCT CAPCTRL10: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL10: CAPCONn_L6 Position */ -#define SCT_CAPCTRL10_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L6_Pos) /*!< SCT CAPCTRL10: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL10: CAPCONn_L7 Position */ -#define SCT_CAPCTRL10_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L7_Pos) /*!< SCT CAPCTRL10: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL10: CAPCONn_L8 Position */ -#define SCT_CAPCTRL10_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L8_Pos) /*!< SCT CAPCTRL10: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL10: CAPCONn_L9 Position */ -#define SCT_CAPCTRL10_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L9_Pos) /*!< SCT CAPCTRL10: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL10: CAPCONn_L10 Position */ -#define SCT_CAPCTRL10_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L10_Pos) /*!< SCT CAPCTRL10: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL10: CAPCONn_L11 Position */ -#define SCT_CAPCTRL10_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L11_Pos) /*!< SCT CAPCTRL10: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL10: CAPCONn_L12 Position */ -#define SCT_CAPCTRL10_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L12_Pos) /*!< SCT CAPCTRL10: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL10: CAPCONn_L13 Position */ -#define SCT_CAPCTRL10_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L13_Pos) /*!< SCT CAPCTRL10: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL10: CAPCONn_L14 Position */ -#define SCT_CAPCTRL10_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L14_Pos) /*!< SCT CAPCTRL10: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL10_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL10: CAPCONn_L15 Position */ -#define SCT_CAPCTRL10_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL10_CAPCONn_L15_Pos) /*!< SCT CAPCTRL10: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL10_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL10: CAPCONn_H Position */ -#define SCT_CAPCTRL10_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL10_CAPCONn_H_Pos) /*!< SCT CAPCTRL10: CAPCONn_H Mask */ - -// ------------------------------------- SCT_MATCHREL11 ----------------------------------------- -#define SCT_MATCHREL11_RELOADn_L_Pos 0 /*!< SCT MATCHREL11: RELOADn_L Position */ -#define SCT_MATCHREL11_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL11_RELOADn_L_Pos) /*!< SCT MATCHREL11: RELOADn_L Mask */ -#define SCT_MATCHREL11_RELOADn_H_Pos 16 /*!< SCT MATCHREL11: RELOADn_H Position */ -#define SCT_MATCHREL11_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL11_RELOADn_H_Pos) /*!< SCT MATCHREL11: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL11 ----------------------------------------- -#define SCT_CAPCTRL11_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL11: CAPCONn_L0 Position */ -#define SCT_CAPCTRL11_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L0_Pos) /*!< SCT CAPCTRL11: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL11: CAPCONn_L1 Position */ -#define SCT_CAPCTRL11_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L1_Pos) /*!< SCT CAPCTRL11: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL11: CAPCONn_L2 Position */ -#define SCT_CAPCTRL11_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L2_Pos) /*!< SCT CAPCTRL11: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL11: CAPCONn_L3 Position */ -#define SCT_CAPCTRL11_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L3_Pos) /*!< SCT CAPCTRL11: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL11: CAPCONn_L4 Position */ -#define SCT_CAPCTRL11_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L4_Pos) /*!< SCT CAPCTRL11: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL11: CAPCONn_L5 Position */ -#define SCT_CAPCTRL11_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L5_Pos) /*!< SCT CAPCTRL11: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL11: CAPCONn_L6 Position */ -#define SCT_CAPCTRL11_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L6_Pos) /*!< SCT CAPCTRL11: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL11: CAPCONn_L7 Position */ -#define SCT_CAPCTRL11_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L7_Pos) /*!< SCT CAPCTRL11: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL11: CAPCONn_L8 Position */ -#define SCT_CAPCTRL11_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L8_Pos) /*!< SCT CAPCTRL11: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL11: CAPCONn_L9 Position */ -#define SCT_CAPCTRL11_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L9_Pos) /*!< SCT CAPCTRL11: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL11: CAPCONn_L10 Position */ -#define SCT_CAPCTRL11_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L10_Pos) /*!< SCT CAPCTRL11: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL11: CAPCONn_L11 Position */ -#define SCT_CAPCTRL11_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L11_Pos) /*!< SCT CAPCTRL11: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL11: CAPCONn_L12 Position */ -#define SCT_CAPCTRL11_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L12_Pos) /*!< SCT CAPCTRL11: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL11: CAPCONn_L13 Position */ -#define SCT_CAPCTRL11_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L13_Pos) /*!< SCT CAPCTRL11: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL11: CAPCONn_L14 Position */ -#define SCT_CAPCTRL11_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L14_Pos) /*!< SCT CAPCTRL11: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL11_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL11: CAPCONn_L15 Position */ -#define SCT_CAPCTRL11_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL11_CAPCONn_L15_Pos) /*!< SCT CAPCTRL11: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL11_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL11: CAPCONn_H Position */ -#define SCT_CAPCTRL11_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL11_CAPCONn_H_Pos) /*!< SCT CAPCTRL11: CAPCONn_H Mask */ - -// ------------------------------------- SCT_MATCHREL12 ----------------------------------------- -#define SCT_MATCHREL12_RELOADn_L_Pos 0 /*!< SCT MATCHREL12: RELOADn_L Position */ -#define SCT_MATCHREL12_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL12_RELOADn_L_Pos) /*!< SCT MATCHREL12: RELOADn_L Mask */ -#define SCT_MATCHREL12_RELOADn_H_Pos 16 /*!< SCT MATCHREL12: RELOADn_H Position */ -#define SCT_MATCHREL12_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL12_RELOADn_H_Pos) /*!< SCT MATCHREL12: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL12 ----------------------------------------- -#define SCT_CAPCTRL12_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL12: CAPCONn_L0 Position */ -#define SCT_CAPCTRL12_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L0_Pos) /*!< SCT CAPCTRL12: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL12: CAPCONn_L1 Position */ -#define SCT_CAPCTRL12_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L1_Pos) /*!< SCT CAPCTRL12: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL12: CAPCONn_L2 Position */ -#define SCT_CAPCTRL12_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L2_Pos) /*!< SCT CAPCTRL12: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL12: CAPCONn_L3 Position */ -#define SCT_CAPCTRL12_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L3_Pos) /*!< SCT CAPCTRL12: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL12: CAPCONn_L4 Position */ -#define SCT_CAPCTRL12_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L4_Pos) /*!< SCT CAPCTRL12: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL12: CAPCONn_L5 Position */ -#define SCT_CAPCTRL12_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L5_Pos) /*!< SCT CAPCTRL12: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL12: CAPCONn_L6 Position */ -#define SCT_CAPCTRL12_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L6_Pos) /*!< SCT CAPCTRL12: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL12: CAPCONn_L7 Position */ -#define SCT_CAPCTRL12_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L7_Pos) /*!< SCT CAPCTRL12: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL12: CAPCONn_L8 Position */ -#define SCT_CAPCTRL12_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L8_Pos) /*!< SCT CAPCTRL12: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL12: CAPCONn_L9 Position */ -#define SCT_CAPCTRL12_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L9_Pos) /*!< SCT CAPCTRL12: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL12: CAPCONn_L10 Position */ -#define SCT_CAPCTRL12_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L10_Pos) /*!< SCT CAPCTRL12: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL12: CAPCONn_L11 Position */ -#define SCT_CAPCTRL12_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L11_Pos) /*!< SCT CAPCTRL12: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL12: CAPCONn_L12 Position */ -#define SCT_CAPCTRL12_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L12_Pos) /*!< SCT CAPCTRL12: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL12: CAPCONn_L13 Position */ -#define SCT_CAPCTRL12_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L13_Pos) /*!< SCT CAPCTRL12: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL12: CAPCONn_L14 Position */ -#define SCT_CAPCTRL12_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L14_Pos) /*!< SCT CAPCTRL12: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL12_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL12: CAPCONn_L15 Position */ -#define SCT_CAPCTRL12_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL12_CAPCONn_L15_Pos) /*!< SCT CAPCTRL12: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL12_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL12: CAPCONn_H Position */ -#define SCT_CAPCTRL12_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL12_CAPCONn_H_Pos) /*!< SCT CAPCTRL12: CAPCONn_H Mask */ - -// ------------------------------------- SCT_MATCHREL13 ----------------------------------------- -#define SCT_MATCHREL13_RELOADn_L_Pos 0 /*!< SCT MATCHREL13: RELOADn_L Position */ -#define SCT_MATCHREL13_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL13_RELOADn_L_Pos) /*!< SCT MATCHREL13: RELOADn_L Mask */ -#define SCT_MATCHREL13_RELOADn_H_Pos 16 /*!< SCT MATCHREL13: RELOADn_H Position */ -#define SCT_MATCHREL13_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL13_RELOADn_H_Pos) /*!< SCT MATCHREL13: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL13 ----------------------------------------- -#define SCT_CAPCTRL13_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL13: CAPCONn_L0 Position */ -#define SCT_CAPCTRL13_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L0_Pos) /*!< SCT CAPCTRL13: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL13: CAPCONn_L1 Position */ -#define SCT_CAPCTRL13_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L1_Pos) /*!< SCT CAPCTRL13: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL13: CAPCONn_L2 Position */ -#define SCT_CAPCTRL13_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L2_Pos) /*!< SCT CAPCTRL13: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL13: CAPCONn_L3 Position */ -#define SCT_CAPCTRL13_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L3_Pos) /*!< SCT CAPCTRL13: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL13: CAPCONn_L4 Position */ -#define SCT_CAPCTRL13_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L4_Pos) /*!< SCT CAPCTRL13: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL13: CAPCONn_L5 Position */ -#define SCT_CAPCTRL13_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L5_Pos) /*!< SCT CAPCTRL13: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL13: CAPCONn_L6 Position */ -#define SCT_CAPCTRL13_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L6_Pos) /*!< SCT CAPCTRL13: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL13: CAPCONn_L7 Position */ -#define SCT_CAPCTRL13_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L7_Pos) /*!< SCT CAPCTRL13: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL13: CAPCONn_L8 Position */ -#define SCT_CAPCTRL13_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L8_Pos) /*!< SCT CAPCTRL13: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL13: CAPCONn_L9 Position */ -#define SCT_CAPCTRL13_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L9_Pos) /*!< SCT CAPCTRL13: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL13: CAPCONn_L10 Position */ -#define SCT_CAPCTRL13_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L10_Pos) /*!< SCT CAPCTRL13: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL13: CAPCONn_L11 Position */ -#define SCT_CAPCTRL13_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L11_Pos) /*!< SCT CAPCTRL13: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL13: CAPCONn_L12 Position */ -#define SCT_CAPCTRL13_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L12_Pos) /*!< SCT CAPCTRL13: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL13: CAPCONn_L13 Position */ -#define SCT_CAPCTRL13_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L13_Pos) /*!< SCT CAPCTRL13: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL13: CAPCONn_L14 Position */ -#define SCT_CAPCTRL13_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L14_Pos) /*!< SCT CAPCTRL13: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL13_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL13: CAPCONn_L15 Position */ -#define SCT_CAPCTRL13_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL13_CAPCONn_L15_Pos) /*!< SCT CAPCTRL13: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL13_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL13: CAPCONn_H Position */ -#define SCT_CAPCTRL13_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL13_CAPCONn_H_Pos) /*!< SCT CAPCTRL13: CAPCONn_H Mask */ - -// ------------------------------------- SCT_MATCHREL14 ----------------------------------------- -#define SCT_MATCHREL14_RELOADn_L_Pos 0 /*!< SCT MATCHREL14: RELOADn_L Position */ -#define SCT_MATCHREL14_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL14_RELOADn_L_Pos) /*!< SCT MATCHREL14: RELOADn_L Mask */ -#define SCT_MATCHREL14_RELOADn_H_Pos 16 /*!< SCT MATCHREL14: RELOADn_H Position */ -#define SCT_MATCHREL14_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL14_RELOADn_H_Pos) /*!< SCT MATCHREL14: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL14 ----------------------------------------- -#define SCT_CAPCTRL14_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL14: CAPCONn_L0 Position */ -#define SCT_CAPCTRL14_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L0_Pos) /*!< SCT CAPCTRL14: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL14: CAPCONn_L1 Position */ -#define SCT_CAPCTRL14_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L1_Pos) /*!< SCT CAPCTRL14: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL14: CAPCONn_L2 Position */ -#define SCT_CAPCTRL14_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L2_Pos) /*!< SCT CAPCTRL14: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL14: CAPCONn_L3 Position */ -#define SCT_CAPCTRL14_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L3_Pos) /*!< SCT CAPCTRL14: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL14: CAPCONn_L4 Position */ -#define SCT_CAPCTRL14_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L4_Pos) /*!< SCT CAPCTRL14: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL14: CAPCONn_L5 Position */ -#define SCT_CAPCTRL14_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L5_Pos) /*!< SCT CAPCTRL14: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL14: CAPCONn_L6 Position */ -#define SCT_CAPCTRL14_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L6_Pos) /*!< SCT CAPCTRL14: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL14: CAPCONn_L7 Position */ -#define SCT_CAPCTRL14_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L7_Pos) /*!< SCT CAPCTRL14: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL14: CAPCONn_L8 Position */ -#define SCT_CAPCTRL14_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L8_Pos) /*!< SCT CAPCTRL14: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL14: CAPCONn_L9 Position */ -#define SCT_CAPCTRL14_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L9_Pos) /*!< SCT CAPCTRL14: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL14: CAPCONn_L10 Position */ -#define SCT_CAPCTRL14_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L10_Pos) /*!< SCT CAPCTRL14: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL14: CAPCONn_L11 Position */ -#define SCT_CAPCTRL14_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L11_Pos) /*!< SCT CAPCTRL14: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL14: CAPCONn_L12 Position */ -#define SCT_CAPCTRL14_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L12_Pos) /*!< SCT CAPCTRL14: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL14: CAPCONn_L13 Position */ -#define SCT_CAPCTRL14_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L13_Pos) /*!< SCT CAPCTRL14: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL14: CAPCONn_L14 Position */ -#define SCT_CAPCTRL14_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L14_Pos) /*!< SCT CAPCTRL14: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL14_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL14: CAPCONn_L15 Position */ -#define SCT_CAPCTRL14_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL14_CAPCONn_L15_Pos) /*!< SCT CAPCTRL14: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL14_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL14: CAPCONn_H Position */ -#define SCT_CAPCTRL14_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL14_CAPCONn_H_Pos) /*!< SCT CAPCTRL14: CAPCONn_H Mask */ - -// ------------------------------------- SCT_MATCHREL15 ----------------------------------------- -#define SCT_MATCHREL15_RELOADn_L_Pos 0 /*!< SCT MATCHREL15: RELOADn_L Position */ -#define SCT_MATCHREL15_RELOADn_L_Msk (0x0000ffffUL << SCT_MATCHREL15_RELOADn_L_Pos) /*!< SCT MATCHREL15: RELOADn_L Mask */ -#define SCT_MATCHREL15_RELOADn_H_Pos 16 /*!< SCT MATCHREL15: RELOADn_H Position */ -#define SCT_MATCHREL15_RELOADn_H_Msk (0x0000ffffUL << SCT_MATCHREL15_RELOADn_H_Pos) /*!< SCT MATCHREL15: RELOADn_H Mask */ - -// -------------------------------------- SCT_CAPCTRL15 ----------------------------------------- -#define SCT_CAPCTRL15_CAPCONn_L0_Pos 0 /*!< SCT CAPCTRL15: CAPCONn_L0 Position */ -#define SCT_CAPCTRL15_CAPCONn_L0_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L0_Pos) /*!< SCT CAPCTRL15: CAPCONn_L0 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L1_Pos 1 /*!< SCT CAPCTRL15: CAPCONn_L1 Position */ -#define SCT_CAPCTRL15_CAPCONn_L1_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L1_Pos) /*!< SCT CAPCTRL15: CAPCONn_L1 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L2_Pos 2 /*!< SCT CAPCTRL15: CAPCONn_L2 Position */ -#define SCT_CAPCTRL15_CAPCONn_L2_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L2_Pos) /*!< SCT CAPCTRL15: CAPCONn_L2 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L3_Pos 3 /*!< SCT CAPCTRL15: CAPCONn_L3 Position */ -#define SCT_CAPCTRL15_CAPCONn_L3_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L3_Pos) /*!< SCT CAPCTRL15: CAPCONn_L3 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L4_Pos 4 /*!< SCT CAPCTRL15: CAPCONn_L4 Position */ -#define SCT_CAPCTRL15_CAPCONn_L4_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L4_Pos) /*!< SCT CAPCTRL15: CAPCONn_L4 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L5_Pos 5 /*!< SCT CAPCTRL15: CAPCONn_L5 Position */ -#define SCT_CAPCTRL15_CAPCONn_L5_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L5_Pos) /*!< SCT CAPCTRL15: CAPCONn_L5 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L6_Pos 6 /*!< SCT CAPCTRL15: CAPCONn_L6 Position */ -#define SCT_CAPCTRL15_CAPCONn_L6_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L6_Pos) /*!< SCT CAPCTRL15: CAPCONn_L6 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L7_Pos 7 /*!< SCT CAPCTRL15: CAPCONn_L7 Position */ -#define SCT_CAPCTRL15_CAPCONn_L7_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L7_Pos) /*!< SCT CAPCTRL15: CAPCONn_L7 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L8_Pos 8 /*!< SCT CAPCTRL15: CAPCONn_L8 Position */ -#define SCT_CAPCTRL15_CAPCONn_L8_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L8_Pos) /*!< SCT CAPCTRL15: CAPCONn_L8 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L9_Pos 9 /*!< SCT CAPCTRL15: CAPCONn_L9 Position */ -#define SCT_CAPCTRL15_CAPCONn_L9_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L9_Pos) /*!< SCT CAPCTRL15: CAPCONn_L9 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L10_Pos 10 /*!< SCT CAPCTRL15: CAPCONn_L10 Position */ -#define SCT_CAPCTRL15_CAPCONn_L10_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L10_Pos) /*!< SCT CAPCTRL15: CAPCONn_L10 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L11_Pos 11 /*!< SCT CAPCTRL15: CAPCONn_L11 Position */ -#define SCT_CAPCTRL15_CAPCONn_L11_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L11_Pos) /*!< SCT CAPCTRL15: CAPCONn_L11 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L12_Pos 12 /*!< SCT CAPCTRL15: CAPCONn_L12 Position */ -#define SCT_CAPCTRL15_CAPCONn_L12_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L12_Pos) /*!< SCT CAPCTRL15: CAPCONn_L12 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L13_Pos 13 /*!< SCT CAPCTRL15: CAPCONn_L13 Position */ -#define SCT_CAPCTRL15_CAPCONn_L13_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L13_Pos) /*!< SCT CAPCTRL15: CAPCONn_L13 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L14_Pos 14 /*!< SCT CAPCTRL15: CAPCONn_L14 Position */ -#define SCT_CAPCTRL15_CAPCONn_L14_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L14_Pos) /*!< SCT CAPCTRL15: CAPCONn_L14 Mask */ -#define SCT_CAPCTRL15_CAPCONn_L15_Pos 15 /*!< SCT CAPCTRL15: CAPCONn_L15 Position */ -#define SCT_CAPCTRL15_CAPCONn_L15_Msk (0x01UL << SCT_CAPCTRL15_CAPCONn_L15_Pos) /*!< SCT CAPCTRL15: CAPCONn_L15 Mask */ -#define SCT_CAPCTRL15_CAPCONn_H_Pos 16 /*!< SCT CAPCTRL15: CAPCONn_H Position */ -#define SCT_CAPCTRL15_CAPCONn_H_Msk (0x0000ffffUL << SCT_CAPCTRL15_CAPCONn_H_Pos) /*!< SCT CAPCTRL15: CAPCONn_H Mask */ - -// ------------------------------------- SCT_EVSTATEMSK0 ---------------------------------------- -#define SCT_EVSTATEMSK0_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK0: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK0: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK0: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK0: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK0: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK0: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK0: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK0: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK0: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK0: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK0: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK0: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK0: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK0: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK0: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK0: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK0: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK0: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK0: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK0: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK0: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK0: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK0: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK0: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK0: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK0: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK0: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK0: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK0: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK0: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK0: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK0_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK0: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK0_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK0_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK0: STATEMSKn31 Mask */ - -// --------------------------------------- SCT_EVCTRL0 ------------------------------------------ -#define SCT_EVCTRL0_MATCHSEL_Pos 0 /*!< SCT EVCTRL0: MATCHSEL Position */ -#define SCT_EVCTRL0_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL0_MATCHSEL_Pos) /*!< SCT EVCTRL0: MATCHSEL Mask */ -#define SCT_EVCTRL0_HEVENT_Pos 4 /*!< SCT EVCTRL0: HEVENT Position */ -#define SCT_EVCTRL0_HEVENT_Msk (0x01UL << SCT_EVCTRL0_HEVENT_Pos) /*!< SCT EVCTRL0: HEVENT Mask */ -#define SCT_EVCTRL0_OUTSEL_Pos 5 /*!< SCT EVCTRL0: OUTSEL Position */ -#define SCT_EVCTRL0_OUTSEL_Msk (0x01UL << SCT_EVCTRL0_OUTSEL_Pos) /*!< SCT EVCTRL0: OUTSEL Mask */ -#define SCT_EVCTRL0_IOSEL_Pos 6 /*!< SCT EVCTRL0: IOSEL Position */ -#define SCT_EVCTRL0_IOSEL_Msk (0x0fUL << SCT_EVCTRL0_IOSEL_Pos) /*!< SCT EVCTRL0: IOSEL Mask */ -#define SCT_EVCTRL0_IOCOND_Pos 10 /*!< SCT EVCTRL0: IOCOND Position */ -#define SCT_EVCTRL0_IOCOND_Msk (0x03UL << SCT_EVCTRL0_IOCOND_Pos) /*!< SCT EVCTRL0: IOCOND Mask */ -#define SCT_EVCTRL0_COMBMODE_Pos 12 /*!< SCT EVCTRL0: COMBMODE Position */ -#define SCT_EVCTRL0_COMBMODE_Msk (0x03UL << SCT_EVCTRL0_COMBMODE_Pos) /*!< SCT EVCTRL0: COMBMODE Mask */ -#define SCT_EVCTRL0_STATELD_Pos 14 /*!< SCT EVCTRL0: STATELD Position */ -#define SCT_EVCTRL0_STATELD_Msk (0x01UL << SCT_EVCTRL0_STATELD_Pos) /*!< SCT EVCTRL0: STATELD Mask */ -#define SCT_EVCTRL0_STATEV_Pos 15 /*!< SCT EVCTRL0: STATEV Position */ -#define SCT_EVCTRL0_STATEV_Msk (0x1fUL << SCT_EVCTRL0_STATEV_Pos) /*!< SCT EVCTRL0: STATEV Mask */ - -// ------------------------------------- SCT_EVSTATEMSK1 ---------------------------------------- -#define SCT_EVSTATEMSK1_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK1: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK1: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK1: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK1: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK1: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK1: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK1: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK1: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK1: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK1: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK1: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK1: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK1: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK1: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK1: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK1: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK1: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK1: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK1: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK1: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK1: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK1: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK1: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK1: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK1: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK1: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK1: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK1: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK1: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK1: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK1: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK1_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK1: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK1_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK1_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK1: STATEMSKn31 Mask */ - -// --------------------------------------- SCT_EVCTRL1 ------------------------------------------ -#define SCT_EVCTRL1_MATCHSEL_Pos 0 /*!< SCT EVCTRL1: MATCHSEL Position */ -#define SCT_EVCTRL1_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL1_MATCHSEL_Pos) /*!< SCT EVCTRL1: MATCHSEL Mask */ -#define SCT_EVCTRL1_HEVENT_Pos 4 /*!< SCT EVCTRL1: HEVENT Position */ -#define SCT_EVCTRL1_HEVENT_Msk (0x01UL << SCT_EVCTRL1_HEVENT_Pos) /*!< SCT EVCTRL1: HEVENT Mask */ -#define SCT_EVCTRL1_OUTSEL_Pos 5 /*!< SCT EVCTRL1: OUTSEL Position */ -#define SCT_EVCTRL1_OUTSEL_Msk (0x01UL << SCT_EVCTRL1_OUTSEL_Pos) /*!< SCT EVCTRL1: OUTSEL Mask */ -#define SCT_EVCTRL1_IOSEL_Pos 6 /*!< SCT EVCTRL1: IOSEL Position */ -#define SCT_EVCTRL1_IOSEL_Msk (0x0fUL << SCT_EVCTRL1_IOSEL_Pos) /*!< SCT EVCTRL1: IOSEL Mask */ -#define SCT_EVCTRL1_IOCOND_Pos 10 /*!< SCT EVCTRL1: IOCOND Position */ -#define SCT_EVCTRL1_IOCOND_Msk (0x03UL << SCT_EVCTRL1_IOCOND_Pos) /*!< SCT EVCTRL1: IOCOND Mask */ -#define SCT_EVCTRL1_COMBMODE_Pos 12 /*!< SCT EVCTRL1: COMBMODE Position */ -#define SCT_EVCTRL1_COMBMODE_Msk (0x03UL << SCT_EVCTRL1_COMBMODE_Pos) /*!< SCT EVCTRL1: COMBMODE Mask */ -#define SCT_EVCTRL1_STATELD_Pos 14 /*!< SCT EVCTRL1: STATELD Position */ -#define SCT_EVCTRL1_STATELD_Msk (0x01UL << SCT_EVCTRL1_STATELD_Pos) /*!< SCT EVCTRL1: STATELD Mask */ -#define SCT_EVCTRL1_STATEV_Pos 15 /*!< SCT EVCTRL1: STATEV Position */ -#define SCT_EVCTRL1_STATEV_Msk (0x1fUL << SCT_EVCTRL1_STATEV_Pos) /*!< SCT EVCTRL1: STATEV Mask */ - -// ------------------------------------- SCT_EVSTATEMSK2 ---------------------------------------- -#define SCT_EVSTATEMSK2_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK2: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK2: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK2: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK2: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK2: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK2: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK2: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK2: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK2: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK2: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK2: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK2: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK2: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK2: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK2: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK2: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK2: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK2: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK2: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK2: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK2: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK2: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK2: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK2: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK2: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK2: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK2: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK2: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK2: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK2: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK2: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK2_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK2: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK2_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK2_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK2: STATEMSKn31 Mask */ - -// --------------------------------------- SCT_EVCTRL2 ------------------------------------------ -#define SCT_EVCTRL2_MATCHSEL_Pos 0 /*!< SCT EVCTRL2: MATCHSEL Position */ -#define SCT_EVCTRL2_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL2_MATCHSEL_Pos) /*!< SCT EVCTRL2: MATCHSEL Mask */ -#define SCT_EVCTRL2_HEVENT_Pos 4 /*!< SCT EVCTRL2: HEVENT Position */ -#define SCT_EVCTRL2_HEVENT_Msk (0x01UL << SCT_EVCTRL2_HEVENT_Pos) /*!< SCT EVCTRL2: HEVENT Mask */ -#define SCT_EVCTRL2_OUTSEL_Pos 5 /*!< SCT EVCTRL2: OUTSEL Position */ -#define SCT_EVCTRL2_OUTSEL_Msk (0x01UL << SCT_EVCTRL2_OUTSEL_Pos) /*!< SCT EVCTRL2: OUTSEL Mask */ -#define SCT_EVCTRL2_IOSEL_Pos 6 /*!< SCT EVCTRL2: IOSEL Position */ -#define SCT_EVCTRL2_IOSEL_Msk (0x0fUL << SCT_EVCTRL2_IOSEL_Pos) /*!< SCT EVCTRL2: IOSEL Mask */ -#define SCT_EVCTRL2_IOCOND_Pos 10 /*!< SCT EVCTRL2: IOCOND Position */ -#define SCT_EVCTRL2_IOCOND_Msk (0x03UL << SCT_EVCTRL2_IOCOND_Pos) /*!< SCT EVCTRL2: IOCOND Mask */ -#define SCT_EVCTRL2_COMBMODE_Pos 12 /*!< SCT EVCTRL2: COMBMODE Position */ -#define SCT_EVCTRL2_COMBMODE_Msk (0x03UL << SCT_EVCTRL2_COMBMODE_Pos) /*!< SCT EVCTRL2: COMBMODE Mask */ -#define SCT_EVCTRL2_STATELD_Pos 14 /*!< SCT EVCTRL2: STATELD Position */ -#define SCT_EVCTRL2_STATELD_Msk (0x01UL << SCT_EVCTRL2_STATELD_Pos) /*!< SCT EVCTRL2: STATELD Mask */ -#define SCT_EVCTRL2_STATEV_Pos 15 /*!< SCT EVCTRL2: STATEV Position */ -#define SCT_EVCTRL2_STATEV_Msk (0x1fUL << SCT_EVCTRL2_STATEV_Pos) /*!< SCT EVCTRL2: STATEV Mask */ - -// ------------------------------------- SCT_EVSTATEMSK3 ---------------------------------------- -#define SCT_EVSTATEMSK3_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK3: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK3: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK3: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK3: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK3: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK3: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK3: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK3: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK3: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK3: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK3: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK3: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK3: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK3: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK3: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK3: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK3: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK3: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK3: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK3: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK3: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK3: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK3: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK3: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK3: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK3: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK3: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK3: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK3: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK3: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK3: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK3_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK3: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK3_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK3_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK3: STATEMSKn31 Mask */ - -// --------------------------------------- SCT_EVCTRL3 ------------------------------------------ -#define SCT_EVCTRL3_MATCHSEL_Pos 0 /*!< SCT EVCTRL3: MATCHSEL Position */ -#define SCT_EVCTRL3_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL3_MATCHSEL_Pos) /*!< SCT EVCTRL3: MATCHSEL Mask */ -#define SCT_EVCTRL3_HEVENT_Pos 4 /*!< SCT EVCTRL3: HEVENT Position */ -#define SCT_EVCTRL3_HEVENT_Msk (0x01UL << SCT_EVCTRL3_HEVENT_Pos) /*!< SCT EVCTRL3: HEVENT Mask */ -#define SCT_EVCTRL3_OUTSEL_Pos 5 /*!< SCT EVCTRL3: OUTSEL Position */ -#define SCT_EVCTRL3_OUTSEL_Msk (0x01UL << SCT_EVCTRL3_OUTSEL_Pos) /*!< SCT EVCTRL3: OUTSEL Mask */ -#define SCT_EVCTRL3_IOSEL_Pos 6 /*!< SCT EVCTRL3: IOSEL Position */ -#define SCT_EVCTRL3_IOSEL_Msk (0x0fUL << SCT_EVCTRL3_IOSEL_Pos) /*!< SCT EVCTRL3: IOSEL Mask */ -#define SCT_EVCTRL3_IOCOND_Pos 10 /*!< SCT EVCTRL3: IOCOND Position */ -#define SCT_EVCTRL3_IOCOND_Msk (0x03UL << SCT_EVCTRL3_IOCOND_Pos) /*!< SCT EVCTRL3: IOCOND Mask */ -#define SCT_EVCTRL3_COMBMODE_Pos 12 /*!< SCT EVCTRL3: COMBMODE Position */ -#define SCT_EVCTRL3_COMBMODE_Msk (0x03UL << SCT_EVCTRL3_COMBMODE_Pos) /*!< SCT EVCTRL3: COMBMODE Mask */ -#define SCT_EVCTRL3_STATELD_Pos 14 /*!< SCT EVCTRL3: STATELD Position */ -#define SCT_EVCTRL3_STATELD_Msk (0x01UL << SCT_EVCTRL3_STATELD_Pos) /*!< SCT EVCTRL3: STATELD Mask */ -#define SCT_EVCTRL3_STATEV_Pos 15 /*!< SCT EVCTRL3: STATEV Position */ -#define SCT_EVCTRL3_STATEV_Msk (0x1fUL << SCT_EVCTRL3_STATEV_Pos) /*!< SCT EVCTRL3: STATEV Mask */ - -// ------------------------------------- SCT_EVSTATEMSK4 ---------------------------------------- -#define SCT_EVSTATEMSK4_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK4: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK4: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK4: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK4: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK4: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK4: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK4: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK4: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK4: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK4: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK4: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK4: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK4: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK4: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK4: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK4: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK4: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK4: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK4: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK4: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK4: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK4: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK4: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK4: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK4: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK4: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK4: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK4: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK4: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK4: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK4: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK4_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK4: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK4_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK4_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK4: STATEMSKn31 Mask */ - -// --------------------------------------- SCT_EVCTRL4 ------------------------------------------ -#define SCT_EVCTRL4_MATCHSEL_Pos 0 /*!< SCT EVCTRL4: MATCHSEL Position */ -#define SCT_EVCTRL4_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL4_MATCHSEL_Pos) /*!< SCT EVCTRL4: MATCHSEL Mask */ -#define SCT_EVCTRL4_HEVENT_Pos 4 /*!< SCT EVCTRL4: HEVENT Position */ -#define SCT_EVCTRL4_HEVENT_Msk (0x01UL << SCT_EVCTRL4_HEVENT_Pos) /*!< SCT EVCTRL4: HEVENT Mask */ -#define SCT_EVCTRL4_OUTSEL_Pos 5 /*!< SCT EVCTRL4: OUTSEL Position */ -#define SCT_EVCTRL4_OUTSEL_Msk (0x01UL << SCT_EVCTRL4_OUTSEL_Pos) /*!< SCT EVCTRL4: OUTSEL Mask */ -#define SCT_EVCTRL4_IOSEL_Pos 6 /*!< SCT EVCTRL4: IOSEL Position */ -#define SCT_EVCTRL4_IOSEL_Msk (0x0fUL << SCT_EVCTRL4_IOSEL_Pos) /*!< SCT EVCTRL4: IOSEL Mask */ -#define SCT_EVCTRL4_IOCOND_Pos 10 /*!< SCT EVCTRL4: IOCOND Position */ -#define SCT_EVCTRL4_IOCOND_Msk (0x03UL << SCT_EVCTRL4_IOCOND_Pos) /*!< SCT EVCTRL4: IOCOND Mask */ -#define SCT_EVCTRL4_COMBMODE_Pos 12 /*!< SCT EVCTRL4: COMBMODE Position */ -#define SCT_EVCTRL4_COMBMODE_Msk (0x03UL << SCT_EVCTRL4_COMBMODE_Pos) /*!< SCT EVCTRL4: COMBMODE Mask */ -#define SCT_EVCTRL4_STATELD_Pos 14 /*!< SCT EVCTRL4: STATELD Position */ -#define SCT_EVCTRL4_STATELD_Msk (0x01UL << SCT_EVCTRL4_STATELD_Pos) /*!< SCT EVCTRL4: STATELD Mask */ -#define SCT_EVCTRL4_STATEV_Pos 15 /*!< SCT EVCTRL4: STATEV Position */ -#define SCT_EVCTRL4_STATEV_Msk (0x1fUL << SCT_EVCTRL4_STATEV_Pos) /*!< SCT EVCTRL4: STATEV Mask */ - -// ------------------------------------- SCT_EVSTATEMSK5 ---------------------------------------- -#define SCT_EVSTATEMSK5_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK5: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK5: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK5: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK5: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK5: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK5: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK5: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK5: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK5: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK5: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK5: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK5: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK5: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK5: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK5: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK5: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK5: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK5: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK5: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK5: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK5: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK5: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK5: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK5: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK5: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK5: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK5: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK5: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK5: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK5: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK5: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK5_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK5: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK5_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK5_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK5: STATEMSKn31 Mask */ - -// --------------------------------------- SCT_EVCTRL5 ------------------------------------------ -#define SCT_EVCTRL5_MATCHSEL_Pos 0 /*!< SCT EVCTRL5: MATCHSEL Position */ -#define SCT_EVCTRL5_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL5_MATCHSEL_Pos) /*!< SCT EVCTRL5: MATCHSEL Mask */ -#define SCT_EVCTRL5_HEVENT_Pos 4 /*!< SCT EVCTRL5: HEVENT Position */ -#define SCT_EVCTRL5_HEVENT_Msk (0x01UL << SCT_EVCTRL5_HEVENT_Pos) /*!< SCT EVCTRL5: HEVENT Mask */ -#define SCT_EVCTRL5_OUTSEL_Pos 5 /*!< SCT EVCTRL5: OUTSEL Position */ -#define SCT_EVCTRL5_OUTSEL_Msk (0x01UL << SCT_EVCTRL5_OUTSEL_Pos) /*!< SCT EVCTRL5: OUTSEL Mask */ -#define SCT_EVCTRL5_IOSEL_Pos 6 /*!< SCT EVCTRL5: IOSEL Position */ -#define SCT_EVCTRL5_IOSEL_Msk (0x0fUL << SCT_EVCTRL5_IOSEL_Pos) /*!< SCT EVCTRL5: IOSEL Mask */ -#define SCT_EVCTRL5_IOCOND_Pos 10 /*!< SCT EVCTRL5: IOCOND Position */ -#define SCT_EVCTRL5_IOCOND_Msk (0x03UL << SCT_EVCTRL5_IOCOND_Pos) /*!< SCT EVCTRL5: IOCOND Mask */ -#define SCT_EVCTRL5_COMBMODE_Pos 12 /*!< SCT EVCTRL5: COMBMODE Position */ -#define SCT_EVCTRL5_COMBMODE_Msk (0x03UL << SCT_EVCTRL5_COMBMODE_Pos) /*!< SCT EVCTRL5: COMBMODE Mask */ -#define SCT_EVCTRL5_STATELD_Pos 14 /*!< SCT EVCTRL5: STATELD Position */ -#define SCT_EVCTRL5_STATELD_Msk (0x01UL << SCT_EVCTRL5_STATELD_Pos) /*!< SCT EVCTRL5: STATELD Mask */ -#define SCT_EVCTRL5_STATEV_Pos 15 /*!< SCT EVCTRL5: STATEV Position */ -#define SCT_EVCTRL5_STATEV_Msk (0x1fUL << SCT_EVCTRL5_STATEV_Pos) /*!< SCT EVCTRL5: STATEV Mask */ - -// ------------------------------------- SCT_EVSTATEMSK6 ---------------------------------------- -#define SCT_EVSTATEMSK6_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK6: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK6: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK6: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK6: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK6: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK6: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK6: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK6: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK6: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK6: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK6: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK6: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK6: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK6: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK6: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK6: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK6: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK6: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK6: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK6: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK6: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK6: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK6: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK6: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK6: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK6: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK6: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK6: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK6: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK6: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK6: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK6_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK6: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK6_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK6_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK6: STATEMSKn31 Mask */ - -// --------------------------------------- SCT_EVCTRL6 ------------------------------------------ -#define SCT_EVCTRL6_MATCHSEL_Pos 0 /*!< SCT EVCTRL6: MATCHSEL Position */ -#define SCT_EVCTRL6_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL6_MATCHSEL_Pos) /*!< SCT EVCTRL6: MATCHSEL Mask */ -#define SCT_EVCTRL6_HEVENT_Pos 4 /*!< SCT EVCTRL6: HEVENT Position */ -#define SCT_EVCTRL6_HEVENT_Msk (0x01UL << SCT_EVCTRL6_HEVENT_Pos) /*!< SCT EVCTRL6: HEVENT Mask */ -#define SCT_EVCTRL6_OUTSEL_Pos 5 /*!< SCT EVCTRL6: OUTSEL Position */ -#define SCT_EVCTRL6_OUTSEL_Msk (0x01UL << SCT_EVCTRL6_OUTSEL_Pos) /*!< SCT EVCTRL6: OUTSEL Mask */ -#define SCT_EVCTRL6_IOSEL_Pos 6 /*!< SCT EVCTRL6: IOSEL Position */ -#define SCT_EVCTRL6_IOSEL_Msk (0x0fUL << SCT_EVCTRL6_IOSEL_Pos) /*!< SCT EVCTRL6: IOSEL Mask */ -#define SCT_EVCTRL6_IOCOND_Pos 10 /*!< SCT EVCTRL6: IOCOND Position */ -#define SCT_EVCTRL6_IOCOND_Msk (0x03UL << SCT_EVCTRL6_IOCOND_Pos) /*!< SCT EVCTRL6: IOCOND Mask */ -#define SCT_EVCTRL6_COMBMODE_Pos 12 /*!< SCT EVCTRL6: COMBMODE Position */ -#define SCT_EVCTRL6_COMBMODE_Msk (0x03UL << SCT_EVCTRL6_COMBMODE_Pos) /*!< SCT EVCTRL6: COMBMODE Mask */ -#define SCT_EVCTRL6_STATELD_Pos 14 /*!< SCT EVCTRL6: STATELD Position */ -#define SCT_EVCTRL6_STATELD_Msk (0x01UL << SCT_EVCTRL6_STATELD_Pos) /*!< SCT EVCTRL6: STATELD Mask */ -#define SCT_EVCTRL6_STATEV_Pos 15 /*!< SCT EVCTRL6: STATEV Position */ -#define SCT_EVCTRL6_STATEV_Msk (0x1fUL << SCT_EVCTRL6_STATEV_Pos) /*!< SCT EVCTRL6: STATEV Mask */ - -// ------------------------------------- SCT_EVSTATEMSK7 ---------------------------------------- -#define SCT_EVSTATEMSK7_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK7: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK7: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK7: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK7: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK7: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK7: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK7: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK7: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK7: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK7: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK7: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK7: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK7: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK7: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK7: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK7: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK7: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK7: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK7: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK7: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK7: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK7: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK7: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK7: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK7: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK7: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK7: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK7: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK7: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK7: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK7: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK7_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK7: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK7_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK7_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK7: STATEMSKn31 Mask */ - -// --------------------------------------- SCT_EVCTRL7 ------------------------------------------ -#define SCT_EVCTRL7_MATCHSEL_Pos 0 /*!< SCT EVCTRL7: MATCHSEL Position */ -#define SCT_EVCTRL7_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL7_MATCHSEL_Pos) /*!< SCT EVCTRL7: MATCHSEL Mask */ -#define SCT_EVCTRL7_HEVENT_Pos 4 /*!< SCT EVCTRL7: HEVENT Position */ -#define SCT_EVCTRL7_HEVENT_Msk (0x01UL << SCT_EVCTRL7_HEVENT_Pos) /*!< SCT EVCTRL7: HEVENT Mask */ -#define SCT_EVCTRL7_OUTSEL_Pos 5 /*!< SCT EVCTRL7: OUTSEL Position */ -#define SCT_EVCTRL7_OUTSEL_Msk (0x01UL << SCT_EVCTRL7_OUTSEL_Pos) /*!< SCT EVCTRL7: OUTSEL Mask */ -#define SCT_EVCTRL7_IOSEL_Pos 6 /*!< SCT EVCTRL7: IOSEL Position */ -#define SCT_EVCTRL7_IOSEL_Msk (0x0fUL << SCT_EVCTRL7_IOSEL_Pos) /*!< SCT EVCTRL7: IOSEL Mask */ -#define SCT_EVCTRL7_IOCOND_Pos 10 /*!< SCT EVCTRL7: IOCOND Position */ -#define SCT_EVCTRL7_IOCOND_Msk (0x03UL << SCT_EVCTRL7_IOCOND_Pos) /*!< SCT EVCTRL7: IOCOND Mask */ -#define SCT_EVCTRL7_COMBMODE_Pos 12 /*!< SCT EVCTRL7: COMBMODE Position */ -#define SCT_EVCTRL7_COMBMODE_Msk (0x03UL << SCT_EVCTRL7_COMBMODE_Pos) /*!< SCT EVCTRL7: COMBMODE Mask */ -#define SCT_EVCTRL7_STATELD_Pos 14 /*!< SCT EVCTRL7: STATELD Position */ -#define SCT_EVCTRL7_STATELD_Msk (0x01UL << SCT_EVCTRL7_STATELD_Pos) /*!< SCT EVCTRL7: STATELD Mask */ -#define SCT_EVCTRL7_STATEV_Pos 15 /*!< SCT EVCTRL7: STATEV Position */ -#define SCT_EVCTRL7_STATEV_Msk (0x1fUL << SCT_EVCTRL7_STATEV_Pos) /*!< SCT EVCTRL7: STATEV Mask */ - -// ------------------------------------- SCT_EVSTATEMSK8 ---------------------------------------- -#define SCT_EVSTATEMSK8_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK8: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK8: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK8: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK8: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK8: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK8: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK8: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK8: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK8: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK8: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK8: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK8: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK8: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK8: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK8: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK8: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK8: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK8: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK8: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK8: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK8: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK8: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK8: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK8: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK8: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK8: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK8: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK8: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK8: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK8: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK8: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK8_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK8: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK8_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK8_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK8: STATEMSKn31 Mask */ - -// --------------------------------------- SCT_EVCTRL8 ------------------------------------------ -#define SCT_EVCTRL8_MATCHSEL_Pos 0 /*!< SCT EVCTRL8: MATCHSEL Position */ -#define SCT_EVCTRL8_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL8_MATCHSEL_Pos) /*!< SCT EVCTRL8: MATCHSEL Mask */ -#define SCT_EVCTRL8_HEVENT_Pos 4 /*!< SCT EVCTRL8: HEVENT Position */ -#define SCT_EVCTRL8_HEVENT_Msk (0x01UL << SCT_EVCTRL8_HEVENT_Pos) /*!< SCT EVCTRL8: HEVENT Mask */ -#define SCT_EVCTRL8_OUTSEL_Pos 5 /*!< SCT EVCTRL8: OUTSEL Position */ -#define SCT_EVCTRL8_OUTSEL_Msk (0x01UL << SCT_EVCTRL8_OUTSEL_Pos) /*!< SCT EVCTRL8: OUTSEL Mask */ -#define SCT_EVCTRL8_IOSEL_Pos 6 /*!< SCT EVCTRL8: IOSEL Position */ -#define SCT_EVCTRL8_IOSEL_Msk (0x0fUL << SCT_EVCTRL8_IOSEL_Pos) /*!< SCT EVCTRL8: IOSEL Mask */ -#define SCT_EVCTRL8_IOCOND_Pos 10 /*!< SCT EVCTRL8: IOCOND Position */ -#define SCT_EVCTRL8_IOCOND_Msk (0x03UL << SCT_EVCTRL8_IOCOND_Pos) /*!< SCT EVCTRL8: IOCOND Mask */ -#define SCT_EVCTRL8_COMBMODE_Pos 12 /*!< SCT EVCTRL8: COMBMODE Position */ -#define SCT_EVCTRL8_COMBMODE_Msk (0x03UL << SCT_EVCTRL8_COMBMODE_Pos) /*!< SCT EVCTRL8: COMBMODE Mask */ -#define SCT_EVCTRL8_STATELD_Pos 14 /*!< SCT EVCTRL8: STATELD Position */ -#define SCT_EVCTRL8_STATELD_Msk (0x01UL << SCT_EVCTRL8_STATELD_Pos) /*!< SCT EVCTRL8: STATELD Mask */ -#define SCT_EVCTRL8_STATEV_Pos 15 /*!< SCT EVCTRL8: STATEV Position */ -#define SCT_EVCTRL8_STATEV_Msk (0x1fUL << SCT_EVCTRL8_STATEV_Pos) /*!< SCT EVCTRL8: STATEV Mask */ - -// ------------------------------------- SCT_EVSTATEMSK9 ---------------------------------------- -#define SCT_EVSTATEMSK9_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK9: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK9: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK9: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK9: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK9: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK9: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK9: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK9: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK9: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK9: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK9: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK9: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK9: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK9: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK9: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK9: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK9: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK9: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK9: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK9: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK9: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK9: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK9: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK9: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK9: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK9: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK9: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK9: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK9: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK9: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK9: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK9_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK9: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK9_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK9_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK9: STATEMSKn31 Mask */ - -// --------------------------------------- SCT_EVCTRL9 ------------------------------------------ -#define SCT_EVCTRL9_MATCHSEL_Pos 0 /*!< SCT EVCTRL9: MATCHSEL Position */ -#define SCT_EVCTRL9_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL9_MATCHSEL_Pos) /*!< SCT EVCTRL9: MATCHSEL Mask */ -#define SCT_EVCTRL9_HEVENT_Pos 4 /*!< SCT EVCTRL9: HEVENT Position */ -#define SCT_EVCTRL9_HEVENT_Msk (0x01UL << SCT_EVCTRL9_HEVENT_Pos) /*!< SCT EVCTRL9: HEVENT Mask */ -#define SCT_EVCTRL9_OUTSEL_Pos 5 /*!< SCT EVCTRL9: OUTSEL Position */ -#define SCT_EVCTRL9_OUTSEL_Msk (0x01UL << SCT_EVCTRL9_OUTSEL_Pos) /*!< SCT EVCTRL9: OUTSEL Mask */ -#define SCT_EVCTRL9_IOSEL_Pos 6 /*!< SCT EVCTRL9: IOSEL Position */ -#define SCT_EVCTRL9_IOSEL_Msk (0x0fUL << SCT_EVCTRL9_IOSEL_Pos) /*!< SCT EVCTRL9: IOSEL Mask */ -#define SCT_EVCTRL9_IOCOND_Pos 10 /*!< SCT EVCTRL9: IOCOND Position */ -#define SCT_EVCTRL9_IOCOND_Msk (0x03UL << SCT_EVCTRL9_IOCOND_Pos) /*!< SCT EVCTRL9: IOCOND Mask */ -#define SCT_EVCTRL9_COMBMODE_Pos 12 /*!< SCT EVCTRL9: COMBMODE Position */ -#define SCT_EVCTRL9_COMBMODE_Msk (0x03UL << SCT_EVCTRL9_COMBMODE_Pos) /*!< SCT EVCTRL9: COMBMODE Mask */ -#define SCT_EVCTRL9_STATELD_Pos 14 /*!< SCT EVCTRL9: STATELD Position */ -#define SCT_EVCTRL9_STATELD_Msk (0x01UL << SCT_EVCTRL9_STATELD_Pos) /*!< SCT EVCTRL9: STATELD Mask */ -#define SCT_EVCTRL9_STATEV_Pos 15 /*!< SCT EVCTRL9: STATEV Position */ -#define SCT_EVCTRL9_STATEV_Msk (0x1fUL << SCT_EVCTRL9_STATEV_Pos) /*!< SCT EVCTRL9: STATEV Mask */ - -// ------------------------------------ SCT_EVSTATEMSK10 ---------------------------------------- -#define SCT_EVSTATEMSK10_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK10: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK10: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK10: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK10: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK10: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK10: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK10: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK10: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK10: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK10: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK10: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK10: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK10: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK10: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK10: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK10: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK10: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK10: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK10: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK10: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK10: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK10: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK10: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK10: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK10: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK10: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK10: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK10: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK10: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK10: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK10: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK10_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK10: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK10_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK10_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK10: STATEMSKn31 Mask */ - -// -------------------------------------- SCT_EVCTRL10 ------------------------------------------ -#define SCT_EVCTRL10_MATCHSEL_Pos 0 /*!< SCT EVCTRL10: MATCHSEL Position */ -#define SCT_EVCTRL10_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL10_MATCHSEL_Pos) /*!< SCT EVCTRL10: MATCHSEL Mask */ -#define SCT_EVCTRL10_HEVENT_Pos 4 /*!< SCT EVCTRL10: HEVENT Position */ -#define SCT_EVCTRL10_HEVENT_Msk (0x01UL << SCT_EVCTRL10_HEVENT_Pos) /*!< SCT EVCTRL10: HEVENT Mask */ -#define SCT_EVCTRL10_OUTSEL_Pos 5 /*!< SCT EVCTRL10: OUTSEL Position */ -#define SCT_EVCTRL10_OUTSEL_Msk (0x01UL << SCT_EVCTRL10_OUTSEL_Pos) /*!< SCT EVCTRL10: OUTSEL Mask */ -#define SCT_EVCTRL10_IOSEL_Pos 6 /*!< SCT EVCTRL10: IOSEL Position */ -#define SCT_EVCTRL10_IOSEL_Msk (0x0fUL << SCT_EVCTRL10_IOSEL_Pos) /*!< SCT EVCTRL10: IOSEL Mask */ -#define SCT_EVCTRL10_IOCOND_Pos 10 /*!< SCT EVCTRL10: IOCOND Position */ -#define SCT_EVCTRL10_IOCOND_Msk (0x03UL << SCT_EVCTRL10_IOCOND_Pos) /*!< SCT EVCTRL10: IOCOND Mask */ -#define SCT_EVCTRL10_COMBMODE_Pos 12 /*!< SCT EVCTRL10: COMBMODE Position */ -#define SCT_EVCTRL10_COMBMODE_Msk (0x03UL << SCT_EVCTRL10_COMBMODE_Pos) /*!< SCT EVCTRL10: COMBMODE Mask */ -#define SCT_EVCTRL10_STATELD_Pos 14 /*!< SCT EVCTRL10: STATELD Position */ -#define SCT_EVCTRL10_STATELD_Msk (0x01UL << SCT_EVCTRL10_STATELD_Pos) /*!< SCT EVCTRL10: STATELD Mask */ -#define SCT_EVCTRL10_STATEV_Pos 15 /*!< SCT EVCTRL10: STATEV Position */ -#define SCT_EVCTRL10_STATEV_Msk (0x1fUL << SCT_EVCTRL10_STATEV_Pos) /*!< SCT EVCTRL10: STATEV Mask */ - -// ------------------------------------ SCT_EVSTATEMSK11 ---------------------------------------- -#define SCT_EVSTATEMSK11_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK11: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK11: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK11: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK11: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK11: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK11: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK11: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK11: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK11: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK11: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK11: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK11: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK11: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK11: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK11: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK11: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK11: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK11: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK11: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK11: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK11: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK11: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK11: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK11: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK11: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK11: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK11: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK11: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK11: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK11: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK11: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK11_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK11: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK11_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK11_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK11: STATEMSKn31 Mask */ - -// -------------------------------------- SCT_EVCTRL11 ------------------------------------------ -#define SCT_EVCTRL11_MATCHSEL_Pos 0 /*!< SCT EVCTRL11: MATCHSEL Position */ -#define SCT_EVCTRL11_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL11_MATCHSEL_Pos) /*!< SCT EVCTRL11: MATCHSEL Mask */ -#define SCT_EVCTRL11_HEVENT_Pos 4 /*!< SCT EVCTRL11: HEVENT Position */ -#define SCT_EVCTRL11_HEVENT_Msk (0x01UL << SCT_EVCTRL11_HEVENT_Pos) /*!< SCT EVCTRL11: HEVENT Mask */ -#define SCT_EVCTRL11_OUTSEL_Pos 5 /*!< SCT EVCTRL11: OUTSEL Position */ -#define SCT_EVCTRL11_OUTSEL_Msk (0x01UL << SCT_EVCTRL11_OUTSEL_Pos) /*!< SCT EVCTRL11: OUTSEL Mask */ -#define SCT_EVCTRL11_IOSEL_Pos 6 /*!< SCT EVCTRL11: IOSEL Position */ -#define SCT_EVCTRL11_IOSEL_Msk (0x0fUL << SCT_EVCTRL11_IOSEL_Pos) /*!< SCT EVCTRL11: IOSEL Mask */ -#define SCT_EVCTRL11_IOCOND_Pos 10 /*!< SCT EVCTRL11: IOCOND Position */ -#define SCT_EVCTRL11_IOCOND_Msk (0x03UL << SCT_EVCTRL11_IOCOND_Pos) /*!< SCT EVCTRL11: IOCOND Mask */ -#define SCT_EVCTRL11_COMBMODE_Pos 12 /*!< SCT EVCTRL11: COMBMODE Position */ -#define SCT_EVCTRL11_COMBMODE_Msk (0x03UL << SCT_EVCTRL11_COMBMODE_Pos) /*!< SCT EVCTRL11: COMBMODE Mask */ -#define SCT_EVCTRL11_STATELD_Pos 14 /*!< SCT EVCTRL11: STATELD Position */ -#define SCT_EVCTRL11_STATELD_Msk (0x01UL << SCT_EVCTRL11_STATELD_Pos) /*!< SCT EVCTRL11: STATELD Mask */ -#define SCT_EVCTRL11_STATEV_Pos 15 /*!< SCT EVCTRL11: STATEV Position */ -#define SCT_EVCTRL11_STATEV_Msk (0x1fUL << SCT_EVCTRL11_STATEV_Pos) /*!< SCT EVCTRL11: STATEV Mask */ - -// ------------------------------------ SCT_EVSTATEMSK12 ---------------------------------------- -#define SCT_EVSTATEMSK12_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK12: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK12: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK12: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK12: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK12: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK12: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK12: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK12: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK12: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK12: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK12: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK12: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK12: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK12: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK12: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK12: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK12: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK12: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK12: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK12: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK12: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK12: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK12: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK12: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK12: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK12: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK12: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK12: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK12: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK12: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK12: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK12_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK12: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK12_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK12_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK12: STATEMSKn31 Mask */ - -// -------------------------------------- SCT_EVCTRL12 ------------------------------------------ -#define SCT_EVCTRL12_MATCHSEL_Pos 0 /*!< SCT EVCTRL12: MATCHSEL Position */ -#define SCT_EVCTRL12_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL12_MATCHSEL_Pos) /*!< SCT EVCTRL12: MATCHSEL Mask */ -#define SCT_EVCTRL12_HEVENT_Pos 4 /*!< SCT EVCTRL12: HEVENT Position */ -#define SCT_EVCTRL12_HEVENT_Msk (0x01UL << SCT_EVCTRL12_HEVENT_Pos) /*!< SCT EVCTRL12: HEVENT Mask */ -#define SCT_EVCTRL12_OUTSEL_Pos 5 /*!< SCT EVCTRL12: OUTSEL Position */ -#define SCT_EVCTRL12_OUTSEL_Msk (0x01UL << SCT_EVCTRL12_OUTSEL_Pos) /*!< SCT EVCTRL12: OUTSEL Mask */ -#define SCT_EVCTRL12_IOSEL_Pos 6 /*!< SCT EVCTRL12: IOSEL Position */ -#define SCT_EVCTRL12_IOSEL_Msk (0x0fUL << SCT_EVCTRL12_IOSEL_Pos) /*!< SCT EVCTRL12: IOSEL Mask */ -#define SCT_EVCTRL12_IOCOND_Pos 10 /*!< SCT EVCTRL12: IOCOND Position */ -#define SCT_EVCTRL12_IOCOND_Msk (0x03UL << SCT_EVCTRL12_IOCOND_Pos) /*!< SCT EVCTRL12: IOCOND Mask */ -#define SCT_EVCTRL12_COMBMODE_Pos 12 /*!< SCT EVCTRL12: COMBMODE Position */ -#define SCT_EVCTRL12_COMBMODE_Msk (0x03UL << SCT_EVCTRL12_COMBMODE_Pos) /*!< SCT EVCTRL12: COMBMODE Mask */ -#define SCT_EVCTRL12_STATELD_Pos 14 /*!< SCT EVCTRL12: STATELD Position */ -#define SCT_EVCTRL12_STATELD_Msk (0x01UL << SCT_EVCTRL12_STATELD_Pos) /*!< SCT EVCTRL12: STATELD Mask */ -#define SCT_EVCTRL12_STATEV_Pos 15 /*!< SCT EVCTRL12: STATEV Position */ -#define SCT_EVCTRL12_STATEV_Msk (0x1fUL << SCT_EVCTRL12_STATEV_Pos) /*!< SCT EVCTRL12: STATEV Mask */ - -// ------------------------------------ SCT_EVSTATEMSK13 ---------------------------------------- -#define SCT_EVSTATEMSK13_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK13: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK13: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK13: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK13: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK13: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK13: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK13: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK13: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK13: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK13: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK13: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK13: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK13: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK13: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK13: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK13: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK13: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK13: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK13: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK13: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK13: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK13: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK13: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK13: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK13: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK13: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK13: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK13: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK13: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK13: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK13: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK13_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK13: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK13_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK13_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK13: STATEMSKn31 Mask */ - -// -------------------------------------- SCT_EVCTRL13 ------------------------------------------ -#define SCT_EVCTRL13_MATCHSEL_Pos 0 /*!< SCT EVCTRL13: MATCHSEL Position */ -#define SCT_EVCTRL13_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL13_MATCHSEL_Pos) /*!< SCT EVCTRL13: MATCHSEL Mask */ -#define SCT_EVCTRL13_HEVENT_Pos 4 /*!< SCT EVCTRL13: HEVENT Position */ -#define SCT_EVCTRL13_HEVENT_Msk (0x01UL << SCT_EVCTRL13_HEVENT_Pos) /*!< SCT EVCTRL13: HEVENT Mask */ -#define SCT_EVCTRL13_OUTSEL_Pos 5 /*!< SCT EVCTRL13: OUTSEL Position */ -#define SCT_EVCTRL13_OUTSEL_Msk (0x01UL << SCT_EVCTRL13_OUTSEL_Pos) /*!< SCT EVCTRL13: OUTSEL Mask */ -#define SCT_EVCTRL13_IOSEL_Pos 6 /*!< SCT EVCTRL13: IOSEL Position */ -#define SCT_EVCTRL13_IOSEL_Msk (0x0fUL << SCT_EVCTRL13_IOSEL_Pos) /*!< SCT EVCTRL13: IOSEL Mask */ -#define SCT_EVCTRL13_IOCOND_Pos 10 /*!< SCT EVCTRL13: IOCOND Position */ -#define SCT_EVCTRL13_IOCOND_Msk (0x03UL << SCT_EVCTRL13_IOCOND_Pos) /*!< SCT EVCTRL13: IOCOND Mask */ -#define SCT_EVCTRL13_COMBMODE_Pos 12 /*!< SCT EVCTRL13: COMBMODE Position */ -#define SCT_EVCTRL13_COMBMODE_Msk (0x03UL << SCT_EVCTRL13_COMBMODE_Pos) /*!< SCT EVCTRL13: COMBMODE Mask */ -#define SCT_EVCTRL13_STATELD_Pos 14 /*!< SCT EVCTRL13: STATELD Position */ -#define SCT_EVCTRL13_STATELD_Msk (0x01UL << SCT_EVCTRL13_STATELD_Pos) /*!< SCT EVCTRL13: STATELD Mask */ -#define SCT_EVCTRL13_STATEV_Pos 15 /*!< SCT EVCTRL13: STATEV Position */ -#define SCT_EVCTRL13_STATEV_Msk (0x1fUL << SCT_EVCTRL13_STATEV_Pos) /*!< SCT EVCTRL13: STATEV Mask */ - -// ------------------------------------ SCT_EVSTATEMSK14 ---------------------------------------- -#define SCT_EVSTATEMSK14_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK14: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK14: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK14: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK14: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK14: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK14: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK14: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK14: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK14: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK14: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK14: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK14: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK14: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK14: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK14: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK14: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK14: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK14: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK14: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK14: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK14: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK14: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK14: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK14: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK14: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK14: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK14: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK14: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK14: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK14: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK14: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK14_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK14: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK14_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK14_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK14: STATEMSKn31 Mask */ - -// -------------------------------------- SCT_EVCTRL14 ------------------------------------------ -#define SCT_EVCTRL14_MATCHSEL_Pos 0 /*!< SCT EVCTRL14: MATCHSEL Position */ -#define SCT_EVCTRL14_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL14_MATCHSEL_Pos) /*!< SCT EVCTRL14: MATCHSEL Mask */ -#define SCT_EVCTRL14_HEVENT_Pos 4 /*!< SCT EVCTRL14: HEVENT Position */ -#define SCT_EVCTRL14_HEVENT_Msk (0x01UL << SCT_EVCTRL14_HEVENT_Pos) /*!< SCT EVCTRL14: HEVENT Mask */ -#define SCT_EVCTRL14_OUTSEL_Pos 5 /*!< SCT EVCTRL14: OUTSEL Position */ -#define SCT_EVCTRL14_OUTSEL_Msk (0x01UL << SCT_EVCTRL14_OUTSEL_Pos) /*!< SCT EVCTRL14: OUTSEL Mask */ -#define SCT_EVCTRL14_IOSEL_Pos 6 /*!< SCT EVCTRL14: IOSEL Position */ -#define SCT_EVCTRL14_IOSEL_Msk (0x0fUL << SCT_EVCTRL14_IOSEL_Pos) /*!< SCT EVCTRL14: IOSEL Mask */ -#define SCT_EVCTRL14_IOCOND_Pos 10 /*!< SCT EVCTRL14: IOCOND Position */ -#define SCT_EVCTRL14_IOCOND_Msk (0x03UL << SCT_EVCTRL14_IOCOND_Pos) /*!< SCT EVCTRL14: IOCOND Mask */ -#define SCT_EVCTRL14_COMBMODE_Pos 12 /*!< SCT EVCTRL14: COMBMODE Position */ -#define SCT_EVCTRL14_COMBMODE_Msk (0x03UL << SCT_EVCTRL14_COMBMODE_Pos) /*!< SCT EVCTRL14: COMBMODE Mask */ -#define SCT_EVCTRL14_STATELD_Pos 14 /*!< SCT EVCTRL14: STATELD Position */ -#define SCT_EVCTRL14_STATELD_Msk (0x01UL << SCT_EVCTRL14_STATELD_Pos) /*!< SCT EVCTRL14: STATELD Mask */ -#define SCT_EVCTRL14_STATEV_Pos 15 /*!< SCT EVCTRL14: STATEV Position */ -#define SCT_EVCTRL14_STATEV_Msk (0x1fUL << SCT_EVCTRL14_STATEV_Pos) /*!< SCT EVCTRL14: STATEV Mask */ - -// ------------------------------------ SCT_EVSTATEMSK15 ---------------------------------------- -#define SCT_EVSTATEMSK15_STATEMSKn0_Pos 0 /*!< SCT EVSTATEMSK15: STATEMSKn0 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn0_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn0_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn0 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn1_Pos 1 /*!< SCT EVSTATEMSK15: STATEMSKn1 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn1_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn1_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn1 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn2_Pos 2 /*!< SCT EVSTATEMSK15: STATEMSKn2 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn2_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn2_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn2 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn3_Pos 3 /*!< SCT EVSTATEMSK15: STATEMSKn3 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn3_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn3_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn3 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn4_Pos 4 /*!< SCT EVSTATEMSK15: STATEMSKn4 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn4_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn4_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn4 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn5_Pos 5 /*!< SCT EVSTATEMSK15: STATEMSKn5 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn5_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn5_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn5 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn6_Pos 6 /*!< SCT EVSTATEMSK15: STATEMSKn6 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn6_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn6_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn6 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn7_Pos 7 /*!< SCT EVSTATEMSK15: STATEMSKn7 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn7_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn7_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn7 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn8_Pos 8 /*!< SCT EVSTATEMSK15: STATEMSKn8 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn8_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn8_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn8 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn9_Pos 9 /*!< SCT EVSTATEMSK15: STATEMSKn9 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn9_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn9_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn9 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn10_Pos 10 /*!< SCT EVSTATEMSK15: STATEMSKn10 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn10_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn10_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn10 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn11_Pos 11 /*!< SCT EVSTATEMSK15: STATEMSKn11 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn11_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn11_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn11 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn12_Pos 12 /*!< SCT EVSTATEMSK15: STATEMSKn12 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn12_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn12_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn12 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn13_Pos 13 /*!< SCT EVSTATEMSK15: STATEMSKn13 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn13_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn13_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn13 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn14_Pos 14 /*!< SCT EVSTATEMSK15: STATEMSKn14 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn14_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn14_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn14 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn15_Pos 15 /*!< SCT EVSTATEMSK15: STATEMSKn15 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn15_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn15_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn15 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn16_Pos 16 /*!< SCT EVSTATEMSK15: STATEMSKn16 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn16_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn16_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn16 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn17_Pos 17 /*!< SCT EVSTATEMSK15: STATEMSKn17 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn17_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn17_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn17 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn18_Pos 18 /*!< SCT EVSTATEMSK15: STATEMSKn18 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn18_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn18_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn18 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn19_Pos 19 /*!< SCT EVSTATEMSK15: STATEMSKn19 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn19_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn19_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn19 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn20_Pos 20 /*!< SCT EVSTATEMSK15: STATEMSKn20 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn20_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn20_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn20 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn21_Pos 21 /*!< SCT EVSTATEMSK15: STATEMSKn21 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn21_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn21_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn21 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn22_Pos 22 /*!< SCT EVSTATEMSK15: STATEMSKn22 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn22_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn22_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn22 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn23_Pos 23 /*!< SCT EVSTATEMSK15: STATEMSKn23 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn23_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn23_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn23 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn24_Pos 24 /*!< SCT EVSTATEMSK15: STATEMSKn24 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn24_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn24_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn24 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn25_Pos 25 /*!< SCT EVSTATEMSK15: STATEMSKn25 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn25_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn25_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn25 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn26_Pos 26 /*!< SCT EVSTATEMSK15: STATEMSKn26 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn26_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn26_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn26 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn27_Pos 27 /*!< SCT EVSTATEMSK15: STATEMSKn27 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn27_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn27_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn27 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn28_Pos 28 /*!< SCT EVSTATEMSK15: STATEMSKn28 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn28_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn28_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn28 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn29_Pos 29 /*!< SCT EVSTATEMSK15: STATEMSKn29 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn29_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn29_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn29 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn30_Pos 30 /*!< SCT EVSTATEMSK15: STATEMSKn30 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn30_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn30_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn30 Mask */ -#define SCT_EVSTATEMSK15_STATEMSKn31_Pos 31 /*!< SCT EVSTATEMSK15: STATEMSKn31 Position */ -#define SCT_EVSTATEMSK15_STATEMSKn31_Msk (0x01UL << SCT_EVSTATEMSK15_STATEMSKn31_Pos) /*!< SCT EVSTATEMSK15: STATEMSKn31 Mask */ - -// -------------------------------------- SCT_EVCTRL15 ------------------------------------------ -#define SCT_EVCTRL15_MATCHSEL_Pos 0 /*!< SCT EVCTRL15: MATCHSEL Position */ -#define SCT_EVCTRL15_MATCHSEL_Msk (0x0fUL << SCT_EVCTRL15_MATCHSEL_Pos) /*!< SCT EVCTRL15: MATCHSEL Mask */ -#define SCT_EVCTRL15_HEVENT_Pos 4 /*!< SCT EVCTRL15: HEVENT Position */ -#define SCT_EVCTRL15_HEVENT_Msk (0x01UL << SCT_EVCTRL15_HEVENT_Pos) /*!< SCT EVCTRL15: HEVENT Mask */ -#define SCT_EVCTRL15_OUTSEL_Pos 5 /*!< SCT EVCTRL15: OUTSEL Position */ -#define SCT_EVCTRL15_OUTSEL_Msk (0x01UL << SCT_EVCTRL15_OUTSEL_Pos) /*!< SCT EVCTRL15: OUTSEL Mask */ -#define SCT_EVCTRL15_IOSEL_Pos 6 /*!< SCT EVCTRL15: IOSEL Position */ -#define SCT_EVCTRL15_IOSEL_Msk (0x0fUL << SCT_EVCTRL15_IOSEL_Pos) /*!< SCT EVCTRL15: IOSEL Mask */ -#define SCT_EVCTRL15_IOCOND_Pos 10 /*!< SCT EVCTRL15: IOCOND Position */ -#define SCT_EVCTRL15_IOCOND_Msk (0x03UL << SCT_EVCTRL15_IOCOND_Pos) /*!< SCT EVCTRL15: IOCOND Mask */ -#define SCT_EVCTRL15_COMBMODE_Pos 12 /*!< SCT EVCTRL15: COMBMODE Position */ -#define SCT_EVCTRL15_COMBMODE_Msk (0x03UL << SCT_EVCTRL15_COMBMODE_Pos) /*!< SCT EVCTRL15: COMBMODE Mask */ -#define SCT_EVCTRL15_STATELD_Pos 14 /*!< SCT EVCTRL15: STATELD Position */ -#define SCT_EVCTRL15_STATELD_Msk (0x01UL << SCT_EVCTRL15_STATELD_Pos) /*!< SCT EVCTRL15: STATELD Mask */ -#define SCT_EVCTRL15_STATEV_Pos 15 /*!< SCT EVCTRL15: STATEV Position */ -#define SCT_EVCTRL15_STATEV_Msk (0x1fUL << SCT_EVCTRL15_STATEV_Pos) /*!< SCT EVCTRL15: STATEV Mask */ - -// ------------------------------------- SCT_OUTPUTSET0 ----------------------------------------- -#define SCT_OUTPUTSET0_SETn0_Pos 0 /*!< SCT OUTPUTSET0: SETn0 Position */ -#define SCT_OUTPUTSET0_SETn0_Msk (0x01UL << SCT_OUTPUTSET0_SETn0_Pos) /*!< SCT OUTPUTSET0: SETn0 Mask */ -#define SCT_OUTPUTSET0_SETn1_Pos 1 /*!< SCT OUTPUTSET0: SETn1 Position */ -#define SCT_OUTPUTSET0_SETn1_Msk (0x01UL << SCT_OUTPUTSET0_SETn1_Pos) /*!< SCT OUTPUTSET0: SETn1 Mask */ -#define SCT_OUTPUTSET0_SETn2_Pos 2 /*!< SCT OUTPUTSET0: SETn2 Position */ -#define SCT_OUTPUTSET0_SETn2_Msk (0x01UL << SCT_OUTPUTSET0_SETn2_Pos) /*!< SCT OUTPUTSET0: SETn2 Mask */ -#define SCT_OUTPUTSET0_SETn3_Pos 3 /*!< SCT OUTPUTSET0: SETn3 Position */ -#define SCT_OUTPUTSET0_SETn3_Msk (0x01UL << SCT_OUTPUTSET0_SETn3_Pos) /*!< SCT OUTPUTSET0: SETn3 Mask */ -#define SCT_OUTPUTSET0_SETn4_Pos 4 /*!< SCT OUTPUTSET0: SETn4 Position */ -#define SCT_OUTPUTSET0_SETn4_Msk (0x01UL << SCT_OUTPUTSET0_SETn4_Pos) /*!< SCT OUTPUTSET0: SETn4 Mask */ -#define SCT_OUTPUTSET0_SETn5_Pos 5 /*!< SCT OUTPUTSET0: SETn5 Position */ -#define SCT_OUTPUTSET0_SETn5_Msk (0x01UL << SCT_OUTPUTSET0_SETn5_Pos) /*!< SCT OUTPUTSET0: SETn5 Mask */ -#define SCT_OUTPUTSET0_SETn6_Pos 6 /*!< SCT OUTPUTSET0: SETn6 Position */ -#define SCT_OUTPUTSET0_SETn6_Msk (0x01UL << SCT_OUTPUTSET0_SETn6_Pos) /*!< SCT OUTPUTSET0: SETn6 Mask */ -#define SCT_OUTPUTSET0_SETn7_Pos 7 /*!< SCT OUTPUTSET0: SETn7 Position */ -#define SCT_OUTPUTSET0_SETn7_Msk (0x01UL << SCT_OUTPUTSET0_SETn7_Pos) /*!< SCT OUTPUTSET0: SETn7 Mask */ -#define SCT_OUTPUTSET0_SETn8_Pos 8 /*!< SCT OUTPUTSET0: SETn8 Position */ -#define SCT_OUTPUTSET0_SETn8_Msk (0x01UL << SCT_OUTPUTSET0_SETn8_Pos) /*!< SCT OUTPUTSET0: SETn8 Mask */ -#define SCT_OUTPUTSET0_SETn9_Pos 9 /*!< SCT OUTPUTSET0: SETn9 Position */ -#define SCT_OUTPUTSET0_SETn9_Msk (0x01UL << SCT_OUTPUTSET0_SETn9_Pos) /*!< SCT OUTPUTSET0: SETn9 Mask */ -#define SCT_OUTPUTSET0_SETn10_Pos 10 /*!< SCT OUTPUTSET0: SETn10 Position */ -#define SCT_OUTPUTSET0_SETn10_Msk (0x01UL << SCT_OUTPUTSET0_SETn10_Pos) /*!< SCT OUTPUTSET0: SETn10 Mask */ -#define SCT_OUTPUTSET0_SETn11_Pos 11 /*!< SCT OUTPUTSET0: SETn11 Position */ -#define SCT_OUTPUTSET0_SETn11_Msk (0x01UL << SCT_OUTPUTSET0_SETn11_Pos) /*!< SCT OUTPUTSET0: SETn11 Mask */ -#define SCT_OUTPUTSET0_SETn12_Pos 12 /*!< SCT OUTPUTSET0: SETn12 Position */ -#define SCT_OUTPUTSET0_SETn12_Msk (0x01UL << SCT_OUTPUTSET0_SETn12_Pos) /*!< SCT OUTPUTSET0: SETn12 Mask */ -#define SCT_OUTPUTSET0_SETn13_Pos 13 /*!< SCT OUTPUTSET0: SETn13 Position */ -#define SCT_OUTPUTSET0_SETn13_Msk (0x01UL << SCT_OUTPUTSET0_SETn13_Pos) /*!< SCT OUTPUTSET0: SETn13 Mask */ -#define SCT_OUTPUTSET0_SETn14_Pos 14 /*!< SCT OUTPUTSET0: SETn14 Position */ -#define SCT_OUTPUTSET0_SETn14_Msk (0x01UL << SCT_OUTPUTSET0_SETn14_Pos) /*!< SCT OUTPUTSET0: SETn14 Mask */ -#define SCT_OUTPUTSET0_SETn15_Pos 15 /*!< SCT OUTPUTSET0: SETn15 Position */ -#define SCT_OUTPUTSET0_SETn15_Msk (0x01UL << SCT_OUTPUTSET0_SETn15_Pos) /*!< SCT OUTPUTSET0: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR0 ----------------------------------------- -#define SCT_OUTPUTCLR0_CLRn0_Pos 0 /*!< SCT OUTPUTCLR0: CLRn0 Position */ -#define SCT_OUTPUTCLR0_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn0_Pos) /*!< SCT OUTPUTCLR0: CLRn0 Mask */ -#define SCT_OUTPUTCLR0_CLRn1_Pos 1 /*!< SCT OUTPUTCLR0: CLRn1 Position */ -#define SCT_OUTPUTCLR0_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn1_Pos) /*!< SCT OUTPUTCLR0: CLRn1 Mask */ -#define SCT_OUTPUTCLR0_CLRn2_Pos 2 /*!< SCT OUTPUTCLR0: CLRn2 Position */ -#define SCT_OUTPUTCLR0_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn2_Pos) /*!< SCT OUTPUTCLR0: CLRn2 Mask */ -#define SCT_OUTPUTCLR0_CLRn3_Pos 3 /*!< SCT OUTPUTCLR0: CLRn3 Position */ -#define SCT_OUTPUTCLR0_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn3_Pos) /*!< SCT OUTPUTCLR0: CLRn3 Mask */ -#define SCT_OUTPUTCLR0_CLRn4_Pos 4 /*!< SCT OUTPUTCLR0: CLRn4 Position */ -#define SCT_OUTPUTCLR0_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn4_Pos) /*!< SCT OUTPUTCLR0: CLRn4 Mask */ -#define SCT_OUTPUTCLR0_CLRn5_Pos 5 /*!< SCT OUTPUTCLR0: CLRn5 Position */ -#define SCT_OUTPUTCLR0_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn5_Pos) /*!< SCT OUTPUTCLR0: CLRn5 Mask */ -#define SCT_OUTPUTCLR0_CLRn6_Pos 6 /*!< SCT OUTPUTCLR0: CLRn6 Position */ -#define SCT_OUTPUTCLR0_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn6_Pos) /*!< SCT OUTPUTCLR0: CLRn6 Mask */ -#define SCT_OUTPUTCLR0_CLRn7_Pos 7 /*!< SCT OUTPUTCLR0: CLRn7 Position */ -#define SCT_OUTPUTCLR0_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn7_Pos) /*!< SCT OUTPUTCLR0: CLRn7 Mask */ -#define SCT_OUTPUTCLR0_CLRn8_Pos 8 /*!< SCT OUTPUTCLR0: CLRn8 Position */ -#define SCT_OUTPUTCLR0_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn8_Pos) /*!< SCT OUTPUTCLR0: CLRn8 Mask */ -#define SCT_OUTPUTCLR0_CLRn9_Pos 9 /*!< SCT OUTPUTCLR0: CLRn9 Position */ -#define SCT_OUTPUTCLR0_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn9_Pos) /*!< SCT OUTPUTCLR0: CLRn9 Mask */ -#define SCT_OUTPUTCLR0_CLRn10_Pos 10 /*!< SCT OUTPUTCLR0: CLRn10 Position */ -#define SCT_OUTPUTCLR0_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn10_Pos) /*!< SCT OUTPUTCLR0: CLRn10 Mask */ -#define SCT_OUTPUTCLR0_CLRn11_Pos 11 /*!< SCT OUTPUTCLR0: CLRn11 Position */ -#define SCT_OUTPUTCLR0_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn11_Pos) /*!< SCT OUTPUTCLR0: CLRn11 Mask */ -#define SCT_OUTPUTCLR0_CLRn12_Pos 12 /*!< SCT OUTPUTCLR0: CLRn12 Position */ -#define SCT_OUTPUTCLR0_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn12_Pos) /*!< SCT OUTPUTCLR0: CLRn12 Mask */ -#define SCT_OUTPUTCLR0_CLRn13_Pos 13 /*!< SCT OUTPUTCLR0: CLRn13 Position */ -#define SCT_OUTPUTCLR0_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn13_Pos) /*!< SCT OUTPUTCLR0: CLRn13 Mask */ -#define SCT_OUTPUTCLR0_CLRn14_Pos 14 /*!< SCT OUTPUTCLR0: CLRn14 Position */ -#define SCT_OUTPUTCLR0_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn14_Pos) /*!< SCT OUTPUTCLR0: CLRn14 Mask */ -#define SCT_OUTPUTCLR0_CLRn15_Pos 15 /*!< SCT OUTPUTCLR0: CLRn15 Position */ -#define SCT_OUTPUTCLR0_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR0_CLRn15_Pos) /*!< SCT OUTPUTCLR0: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET1 ----------------------------------------- -#define SCT_OUTPUTSET1_SETn0_Pos 0 /*!< SCT OUTPUTSET1: SETn0 Position */ -#define SCT_OUTPUTSET1_SETn0_Msk (0x01UL << SCT_OUTPUTSET1_SETn0_Pos) /*!< SCT OUTPUTSET1: SETn0 Mask */ -#define SCT_OUTPUTSET1_SETn1_Pos 1 /*!< SCT OUTPUTSET1: SETn1 Position */ -#define SCT_OUTPUTSET1_SETn1_Msk (0x01UL << SCT_OUTPUTSET1_SETn1_Pos) /*!< SCT OUTPUTSET1: SETn1 Mask */ -#define SCT_OUTPUTSET1_SETn2_Pos 2 /*!< SCT OUTPUTSET1: SETn2 Position */ -#define SCT_OUTPUTSET1_SETn2_Msk (0x01UL << SCT_OUTPUTSET1_SETn2_Pos) /*!< SCT OUTPUTSET1: SETn2 Mask */ -#define SCT_OUTPUTSET1_SETn3_Pos 3 /*!< SCT OUTPUTSET1: SETn3 Position */ -#define SCT_OUTPUTSET1_SETn3_Msk (0x01UL << SCT_OUTPUTSET1_SETn3_Pos) /*!< SCT OUTPUTSET1: SETn3 Mask */ -#define SCT_OUTPUTSET1_SETn4_Pos 4 /*!< SCT OUTPUTSET1: SETn4 Position */ -#define SCT_OUTPUTSET1_SETn4_Msk (0x01UL << SCT_OUTPUTSET1_SETn4_Pos) /*!< SCT OUTPUTSET1: SETn4 Mask */ -#define SCT_OUTPUTSET1_SETn5_Pos 5 /*!< SCT OUTPUTSET1: SETn5 Position */ -#define SCT_OUTPUTSET1_SETn5_Msk (0x01UL << SCT_OUTPUTSET1_SETn5_Pos) /*!< SCT OUTPUTSET1: SETn5 Mask */ -#define SCT_OUTPUTSET1_SETn6_Pos 6 /*!< SCT OUTPUTSET1: SETn6 Position */ -#define SCT_OUTPUTSET1_SETn6_Msk (0x01UL << SCT_OUTPUTSET1_SETn6_Pos) /*!< SCT OUTPUTSET1: SETn6 Mask */ -#define SCT_OUTPUTSET1_SETn7_Pos 7 /*!< SCT OUTPUTSET1: SETn7 Position */ -#define SCT_OUTPUTSET1_SETn7_Msk (0x01UL << SCT_OUTPUTSET1_SETn7_Pos) /*!< SCT OUTPUTSET1: SETn7 Mask */ -#define SCT_OUTPUTSET1_SETn8_Pos 8 /*!< SCT OUTPUTSET1: SETn8 Position */ -#define SCT_OUTPUTSET1_SETn8_Msk (0x01UL << SCT_OUTPUTSET1_SETn8_Pos) /*!< SCT OUTPUTSET1: SETn8 Mask */ -#define SCT_OUTPUTSET1_SETn9_Pos 9 /*!< SCT OUTPUTSET1: SETn9 Position */ -#define SCT_OUTPUTSET1_SETn9_Msk (0x01UL << SCT_OUTPUTSET1_SETn9_Pos) /*!< SCT OUTPUTSET1: SETn9 Mask */ -#define SCT_OUTPUTSET1_SETn10_Pos 10 /*!< SCT OUTPUTSET1: SETn10 Position */ -#define SCT_OUTPUTSET1_SETn10_Msk (0x01UL << SCT_OUTPUTSET1_SETn10_Pos) /*!< SCT OUTPUTSET1: SETn10 Mask */ -#define SCT_OUTPUTSET1_SETn11_Pos 11 /*!< SCT OUTPUTSET1: SETn11 Position */ -#define SCT_OUTPUTSET1_SETn11_Msk (0x01UL << SCT_OUTPUTSET1_SETn11_Pos) /*!< SCT OUTPUTSET1: SETn11 Mask */ -#define SCT_OUTPUTSET1_SETn12_Pos 12 /*!< SCT OUTPUTSET1: SETn12 Position */ -#define SCT_OUTPUTSET1_SETn12_Msk (0x01UL << SCT_OUTPUTSET1_SETn12_Pos) /*!< SCT OUTPUTSET1: SETn12 Mask */ -#define SCT_OUTPUTSET1_SETn13_Pos 13 /*!< SCT OUTPUTSET1: SETn13 Position */ -#define SCT_OUTPUTSET1_SETn13_Msk (0x01UL << SCT_OUTPUTSET1_SETn13_Pos) /*!< SCT OUTPUTSET1: SETn13 Mask */ -#define SCT_OUTPUTSET1_SETn14_Pos 14 /*!< SCT OUTPUTSET1: SETn14 Position */ -#define SCT_OUTPUTSET1_SETn14_Msk (0x01UL << SCT_OUTPUTSET1_SETn14_Pos) /*!< SCT OUTPUTSET1: SETn14 Mask */ -#define SCT_OUTPUTSET1_SETn15_Pos 15 /*!< SCT OUTPUTSET1: SETn15 Position */ -#define SCT_OUTPUTSET1_SETn15_Msk (0x01UL << SCT_OUTPUTSET1_SETn15_Pos) /*!< SCT OUTPUTSET1: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR1 ----------------------------------------- -#define SCT_OUTPUTCLR1_CLRn0_Pos 0 /*!< SCT OUTPUTCLR1: CLRn0 Position */ -#define SCT_OUTPUTCLR1_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn0_Pos) /*!< SCT OUTPUTCLR1: CLRn0 Mask */ -#define SCT_OUTPUTCLR1_CLRn1_Pos 1 /*!< SCT OUTPUTCLR1: CLRn1 Position */ -#define SCT_OUTPUTCLR1_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn1_Pos) /*!< SCT OUTPUTCLR1: CLRn1 Mask */ -#define SCT_OUTPUTCLR1_CLRn2_Pos 2 /*!< SCT OUTPUTCLR1: CLRn2 Position */ -#define SCT_OUTPUTCLR1_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn2_Pos) /*!< SCT OUTPUTCLR1: CLRn2 Mask */ -#define SCT_OUTPUTCLR1_CLRn3_Pos 3 /*!< SCT OUTPUTCLR1: CLRn3 Position */ -#define SCT_OUTPUTCLR1_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn3_Pos) /*!< SCT OUTPUTCLR1: CLRn3 Mask */ -#define SCT_OUTPUTCLR1_CLRn4_Pos 4 /*!< SCT OUTPUTCLR1: CLRn4 Position */ -#define SCT_OUTPUTCLR1_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn4_Pos) /*!< SCT OUTPUTCLR1: CLRn4 Mask */ -#define SCT_OUTPUTCLR1_CLRn5_Pos 5 /*!< SCT OUTPUTCLR1: CLRn5 Position */ -#define SCT_OUTPUTCLR1_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn5_Pos) /*!< SCT OUTPUTCLR1: CLRn5 Mask */ -#define SCT_OUTPUTCLR1_CLRn6_Pos 6 /*!< SCT OUTPUTCLR1: CLRn6 Position */ -#define SCT_OUTPUTCLR1_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn6_Pos) /*!< SCT OUTPUTCLR1: CLRn6 Mask */ -#define SCT_OUTPUTCLR1_CLRn7_Pos 7 /*!< SCT OUTPUTCLR1: CLRn7 Position */ -#define SCT_OUTPUTCLR1_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn7_Pos) /*!< SCT OUTPUTCLR1: CLRn7 Mask */ -#define SCT_OUTPUTCLR1_CLRn8_Pos 8 /*!< SCT OUTPUTCLR1: CLRn8 Position */ -#define SCT_OUTPUTCLR1_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn8_Pos) /*!< SCT OUTPUTCLR1: CLRn8 Mask */ -#define SCT_OUTPUTCLR1_CLRn9_Pos 9 /*!< SCT OUTPUTCLR1: CLRn9 Position */ -#define SCT_OUTPUTCLR1_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn9_Pos) /*!< SCT OUTPUTCLR1: CLRn9 Mask */ -#define SCT_OUTPUTCLR1_CLRn10_Pos 10 /*!< SCT OUTPUTCLR1: CLRn10 Position */ -#define SCT_OUTPUTCLR1_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn10_Pos) /*!< SCT OUTPUTCLR1: CLRn10 Mask */ -#define SCT_OUTPUTCLR1_CLRn11_Pos 11 /*!< SCT OUTPUTCLR1: CLRn11 Position */ -#define SCT_OUTPUTCLR1_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn11_Pos) /*!< SCT OUTPUTCLR1: CLRn11 Mask */ -#define SCT_OUTPUTCLR1_CLRn12_Pos 12 /*!< SCT OUTPUTCLR1: CLRn12 Position */ -#define SCT_OUTPUTCLR1_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn12_Pos) /*!< SCT OUTPUTCLR1: CLRn12 Mask */ -#define SCT_OUTPUTCLR1_CLRn13_Pos 13 /*!< SCT OUTPUTCLR1: CLRn13 Position */ -#define SCT_OUTPUTCLR1_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn13_Pos) /*!< SCT OUTPUTCLR1: CLRn13 Mask */ -#define SCT_OUTPUTCLR1_CLRn14_Pos 14 /*!< SCT OUTPUTCLR1: CLRn14 Position */ -#define SCT_OUTPUTCLR1_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn14_Pos) /*!< SCT OUTPUTCLR1: CLRn14 Mask */ -#define SCT_OUTPUTCLR1_CLRn15_Pos 15 /*!< SCT OUTPUTCLR1: CLRn15 Position */ -#define SCT_OUTPUTCLR1_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR1_CLRn15_Pos) /*!< SCT OUTPUTCLR1: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET2 ----------------------------------------- -#define SCT_OUTPUTSET2_SETn0_Pos 0 /*!< SCT OUTPUTSET2: SETn0 Position */ -#define SCT_OUTPUTSET2_SETn0_Msk (0x01UL << SCT_OUTPUTSET2_SETn0_Pos) /*!< SCT OUTPUTSET2: SETn0 Mask */ -#define SCT_OUTPUTSET2_SETn1_Pos 1 /*!< SCT OUTPUTSET2: SETn1 Position */ -#define SCT_OUTPUTSET2_SETn1_Msk (0x01UL << SCT_OUTPUTSET2_SETn1_Pos) /*!< SCT OUTPUTSET2: SETn1 Mask */ -#define SCT_OUTPUTSET2_SETn2_Pos 2 /*!< SCT OUTPUTSET2: SETn2 Position */ -#define SCT_OUTPUTSET2_SETn2_Msk (0x01UL << SCT_OUTPUTSET2_SETn2_Pos) /*!< SCT OUTPUTSET2: SETn2 Mask */ -#define SCT_OUTPUTSET2_SETn3_Pos 3 /*!< SCT OUTPUTSET2: SETn3 Position */ -#define SCT_OUTPUTSET2_SETn3_Msk (0x01UL << SCT_OUTPUTSET2_SETn3_Pos) /*!< SCT OUTPUTSET2: SETn3 Mask */ -#define SCT_OUTPUTSET2_SETn4_Pos 4 /*!< SCT OUTPUTSET2: SETn4 Position */ -#define SCT_OUTPUTSET2_SETn4_Msk (0x01UL << SCT_OUTPUTSET2_SETn4_Pos) /*!< SCT OUTPUTSET2: SETn4 Mask */ -#define SCT_OUTPUTSET2_SETn5_Pos 5 /*!< SCT OUTPUTSET2: SETn5 Position */ -#define SCT_OUTPUTSET2_SETn5_Msk (0x01UL << SCT_OUTPUTSET2_SETn5_Pos) /*!< SCT OUTPUTSET2: SETn5 Mask */ -#define SCT_OUTPUTSET2_SETn6_Pos 6 /*!< SCT OUTPUTSET2: SETn6 Position */ -#define SCT_OUTPUTSET2_SETn6_Msk (0x01UL << SCT_OUTPUTSET2_SETn6_Pos) /*!< SCT OUTPUTSET2: SETn6 Mask */ -#define SCT_OUTPUTSET2_SETn7_Pos 7 /*!< SCT OUTPUTSET2: SETn7 Position */ -#define SCT_OUTPUTSET2_SETn7_Msk (0x01UL << SCT_OUTPUTSET2_SETn7_Pos) /*!< SCT OUTPUTSET2: SETn7 Mask */ -#define SCT_OUTPUTSET2_SETn8_Pos 8 /*!< SCT OUTPUTSET2: SETn8 Position */ -#define SCT_OUTPUTSET2_SETn8_Msk (0x01UL << SCT_OUTPUTSET2_SETn8_Pos) /*!< SCT OUTPUTSET2: SETn8 Mask */ -#define SCT_OUTPUTSET2_SETn9_Pos 9 /*!< SCT OUTPUTSET2: SETn9 Position */ -#define SCT_OUTPUTSET2_SETn9_Msk (0x01UL << SCT_OUTPUTSET2_SETn9_Pos) /*!< SCT OUTPUTSET2: SETn9 Mask */ -#define SCT_OUTPUTSET2_SETn10_Pos 10 /*!< SCT OUTPUTSET2: SETn10 Position */ -#define SCT_OUTPUTSET2_SETn10_Msk (0x01UL << SCT_OUTPUTSET2_SETn10_Pos) /*!< SCT OUTPUTSET2: SETn10 Mask */ -#define SCT_OUTPUTSET2_SETn11_Pos 11 /*!< SCT OUTPUTSET2: SETn11 Position */ -#define SCT_OUTPUTSET2_SETn11_Msk (0x01UL << SCT_OUTPUTSET2_SETn11_Pos) /*!< SCT OUTPUTSET2: SETn11 Mask */ -#define SCT_OUTPUTSET2_SETn12_Pos 12 /*!< SCT OUTPUTSET2: SETn12 Position */ -#define SCT_OUTPUTSET2_SETn12_Msk (0x01UL << SCT_OUTPUTSET2_SETn12_Pos) /*!< SCT OUTPUTSET2: SETn12 Mask */ -#define SCT_OUTPUTSET2_SETn13_Pos 13 /*!< SCT OUTPUTSET2: SETn13 Position */ -#define SCT_OUTPUTSET2_SETn13_Msk (0x01UL << SCT_OUTPUTSET2_SETn13_Pos) /*!< SCT OUTPUTSET2: SETn13 Mask */ -#define SCT_OUTPUTSET2_SETn14_Pos 14 /*!< SCT OUTPUTSET2: SETn14 Position */ -#define SCT_OUTPUTSET2_SETn14_Msk (0x01UL << SCT_OUTPUTSET2_SETn14_Pos) /*!< SCT OUTPUTSET2: SETn14 Mask */ -#define SCT_OUTPUTSET2_SETn15_Pos 15 /*!< SCT OUTPUTSET2: SETn15 Position */ -#define SCT_OUTPUTSET2_SETn15_Msk (0x01UL << SCT_OUTPUTSET2_SETn15_Pos) /*!< SCT OUTPUTSET2: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR2 ----------------------------------------- -#define SCT_OUTPUTCLR2_CLRn0_Pos 0 /*!< SCT OUTPUTCLR2: CLRn0 Position */ -#define SCT_OUTPUTCLR2_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn0_Pos) /*!< SCT OUTPUTCLR2: CLRn0 Mask */ -#define SCT_OUTPUTCLR2_CLRn1_Pos 1 /*!< SCT OUTPUTCLR2: CLRn1 Position */ -#define SCT_OUTPUTCLR2_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn1_Pos) /*!< SCT OUTPUTCLR2: CLRn1 Mask */ -#define SCT_OUTPUTCLR2_CLRn2_Pos 2 /*!< SCT OUTPUTCLR2: CLRn2 Position */ -#define SCT_OUTPUTCLR2_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn2_Pos) /*!< SCT OUTPUTCLR2: CLRn2 Mask */ -#define SCT_OUTPUTCLR2_CLRn3_Pos 3 /*!< SCT OUTPUTCLR2: CLRn3 Position */ -#define SCT_OUTPUTCLR2_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn3_Pos) /*!< SCT OUTPUTCLR2: CLRn3 Mask */ -#define SCT_OUTPUTCLR2_CLRn4_Pos 4 /*!< SCT OUTPUTCLR2: CLRn4 Position */ -#define SCT_OUTPUTCLR2_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn4_Pos) /*!< SCT OUTPUTCLR2: CLRn4 Mask */ -#define SCT_OUTPUTCLR2_CLRn5_Pos 5 /*!< SCT OUTPUTCLR2: CLRn5 Position */ -#define SCT_OUTPUTCLR2_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn5_Pos) /*!< SCT OUTPUTCLR2: CLRn5 Mask */ -#define SCT_OUTPUTCLR2_CLRn6_Pos 6 /*!< SCT OUTPUTCLR2: CLRn6 Position */ -#define SCT_OUTPUTCLR2_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn6_Pos) /*!< SCT OUTPUTCLR2: CLRn6 Mask */ -#define SCT_OUTPUTCLR2_CLRn7_Pos 7 /*!< SCT OUTPUTCLR2: CLRn7 Position */ -#define SCT_OUTPUTCLR2_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn7_Pos) /*!< SCT OUTPUTCLR2: CLRn7 Mask */ -#define SCT_OUTPUTCLR2_CLRn8_Pos 8 /*!< SCT OUTPUTCLR2: CLRn8 Position */ -#define SCT_OUTPUTCLR2_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn8_Pos) /*!< SCT OUTPUTCLR2: CLRn8 Mask */ -#define SCT_OUTPUTCLR2_CLRn9_Pos 9 /*!< SCT OUTPUTCLR2: CLRn9 Position */ -#define SCT_OUTPUTCLR2_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn9_Pos) /*!< SCT OUTPUTCLR2: CLRn9 Mask */ -#define SCT_OUTPUTCLR2_CLRn10_Pos 10 /*!< SCT OUTPUTCLR2: CLRn10 Position */ -#define SCT_OUTPUTCLR2_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn10_Pos) /*!< SCT OUTPUTCLR2: CLRn10 Mask */ -#define SCT_OUTPUTCLR2_CLRn11_Pos 11 /*!< SCT OUTPUTCLR2: CLRn11 Position */ -#define SCT_OUTPUTCLR2_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn11_Pos) /*!< SCT OUTPUTCLR2: CLRn11 Mask */ -#define SCT_OUTPUTCLR2_CLRn12_Pos 12 /*!< SCT OUTPUTCLR2: CLRn12 Position */ -#define SCT_OUTPUTCLR2_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn12_Pos) /*!< SCT OUTPUTCLR2: CLRn12 Mask */ -#define SCT_OUTPUTCLR2_CLRn13_Pos 13 /*!< SCT OUTPUTCLR2: CLRn13 Position */ -#define SCT_OUTPUTCLR2_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn13_Pos) /*!< SCT OUTPUTCLR2: CLRn13 Mask */ -#define SCT_OUTPUTCLR2_CLRn14_Pos 14 /*!< SCT OUTPUTCLR2: CLRn14 Position */ -#define SCT_OUTPUTCLR2_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn14_Pos) /*!< SCT OUTPUTCLR2: CLRn14 Mask */ -#define SCT_OUTPUTCLR2_CLRn15_Pos 15 /*!< SCT OUTPUTCLR2: CLRn15 Position */ -#define SCT_OUTPUTCLR2_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR2_CLRn15_Pos) /*!< SCT OUTPUTCLR2: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET3 ----------------------------------------- -#define SCT_OUTPUTSET3_SETn0_Pos 0 /*!< SCT OUTPUTSET3: SETn0 Position */ -#define SCT_OUTPUTSET3_SETn0_Msk (0x01UL << SCT_OUTPUTSET3_SETn0_Pos) /*!< SCT OUTPUTSET3: SETn0 Mask */ -#define SCT_OUTPUTSET3_SETn1_Pos 1 /*!< SCT OUTPUTSET3: SETn1 Position */ -#define SCT_OUTPUTSET3_SETn1_Msk (0x01UL << SCT_OUTPUTSET3_SETn1_Pos) /*!< SCT OUTPUTSET3: SETn1 Mask */ -#define SCT_OUTPUTSET3_SETn2_Pos 2 /*!< SCT OUTPUTSET3: SETn2 Position */ -#define SCT_OUTPUTSET3_SETn2_Msk (0x01UL << SCT_OUTPUTSET3_SETn2_Pos) /*!< SCT OUTPUTSET3: SETn2 Mask */ -#define SCT_OUTPUTSET3_SETn3_Pos 3 /*!< SCT OUTPUTSET3: SETn3 Position */ -#define SCT_OUTPUTSET3_SETn3_Msk (0x01UL << SCT_OUTPUTSET3_SETn3_Pos) /*!< SCT OUTPUTSET3: SETn3 Mask */ -#define SCT_OUTPUTSET3_SETn4_Pos 4 /*!< SCT OUTPUTSET3: SETn4 Position */ -#define SCT_OUTPUTSET3_SETn4_Msk (0x01UL << SCT_OUTPUTSET3_SETn4_Pos) /*!< SCT OUTPUTSET3: SETn4 Mask */ -#define SCT_OUTPUTSET3_SETn5_Pos 5 /*!< SCT OUTPUTSET3: SETn5 Position */ -#define SCT_OUTPUTSET3_SETn5_Msk (0x01UL << SCT_OUTPUTSET3_SETn5_Pos) /*!< SCT OUTPUTSET3: SETn5 Mask */ -#define SCT_OUTPUTSET3_SETn6_Pos 6 /*!< SCT OUTPUTSET3: SETn6 Position */ -#define SCT_OUTPUTSET3_SETn6_Msk (0x01UL << SCT_OUTPUTSET3_SETn6_Pos) /*!< SCT OUTPUTSET3: SETn6 Mask */ -#define SCT_OUTPUTSET3_SETn7_Pos 7 /*!< SCT OUTPUTSET3: SETn7 Position */ -#define SCT_OUTPUTSET3_SETn7_Msk (0x01UL << SCT_OUTPUTSET3_SETn7_Pos) /*!< SCT OUTPUTSET3: SETn7 Mask */ -#define SCT_OUTPUTSET3_SETn8_Pos 8 /*!< SCT OUTPUTSET3: SETn8 Position */ -#define SCT_OUTPUTSET3_SETn8_Msk (0x01UL << SCT_OUTPUTSET3_SETn8_Pos) /*!< SCT OUTPUTSET3: SETn8 Mask */ -#define SCT_OUTPUTSET3_SETn9_Pos 9 /*!< SCT OUTPUTSET3: SETn9 Position */ -#define SCT_OUTPUTSET3_SETn9_Msk (0x01UL << SCT_OUTPUTSET3_SETn9_Pos) /*!< SCT OUTPUTSET3: SETn9 Mask */ -#define SCT_OUTPUTSET3_SETn10_Pos 10 /*!< SCT OUTPUTSET3: SETn10 Position */ -#define SCT_OUTPUTSET3_SETn10_Msk (0x01UL << SCT_OUTPUTSET3_SETn10_Pos) /*!< SCT OUTPUTSET3: SETn10 Mask */ -#define SCT_OUTPUTSET3_SETn11_Pos 11 /*!< SCT OUTPUTSET3: SETn11 Position */ -#define SCT_OUTPUTSET3_SETn11_Msk (0x01UL << SCT_OUTPUTSET3_SETn11_Pos) /*!< SCT OUTPUTSET3: SETn11 Mask */ -#define SCT_OUTPUTSET3_SETn12_Pos 12 /*!< SCT OUTPUTSET3: SETn12 Position */ -#define SCT_OUTPUTSET3_SETn12_Msk (0x01UL << SCT_OUTPUTSET3_SETn12_Pos) /*!< SCT OUTPUTSET3: SETn12 Mask */ -#define SCT_OUTPUTSET3_SETn13_Pos 13 /*!< SCT OUTPUTSET3: SETn13 Position */ -#define SCT_OUTPUTSET3_SETn13_Msk (0x01UL << SCT_OUTPUTSET3_SETn13_Pos) /*!< SCT OUTPUTSET3: SETn13 Mask */ -#define SCT_OUTPUTSET3_SETn14_Pos 14 /*!< SCT OUTPUTSET3: SETn14 Position */ -#define SCT_OUTPUTSET3_SETn14_Msk (0x01UL << SCT_OUTPUTSET3_SETn14_Pos) /*!< SCT OUTPUTSET3: SETn14 Mask */ -#define SCT_OUTPUTSET3_SETn15_Pos 15 /*!< SCT OUTPUTSET3: SETn15 Position */ -#define SCT_OUTPUTSET3_SETn15_Msk (0x01UL << SCT_OUTPUTSET3_SETn15_Pos) /*!< SCT OUTPUTSET3: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR3 ----------------------------------------- -#define SCT_OUTPUTCLR3_CLRn0_Pos 0 /*!< SCT OUTPUTCLR3: CLRn0 Position */ -#define SCT_OUTPUTCLR3_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn0_Pos) /*!< SCT OUTPUTCLR3: CLRn0 Mask */ -#define SCT_OUTPUTCLR3_CLRn1_Pos 1 /*!< SCT OUTPUTCLR3: CLRn1 Position */ -#define SCT_OUTPUTCLR3_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn1_Pos) /*!< SCT OUTPUTCLR3: CLRn1 Mask */ -#define SCT_OUTPUTCLR3_CLRn2_Pos 2 /*!< SCT OUTPUTCLR3: CLRn2 Position */ -#define SCT_OUTPUTCLR3_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn2_Pos) /*!< SCT OUTPUTCLR3: CLRn2 Mask */ -#define SCT_OUTPUTCLR3_CLRn3_Pos 3 /*!< SCT OUTPUTCLR3: CLRn3 Position */ -#define SCT_OUTPUTCLR3_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn3_Pos) /*!< SCT OUTPUTCLR3: CLRn3 Mask */ -#define SCT_OUTPUTCLR3_CLRn4_Pos 4 /*!< SCT OUTPUTCLR3: CLRn4 Position */ -#define SCT_OUTPUTCLR3_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn4_Pos) /*!< SCT OUTPUTCLR3: CLRn4 Mask */ -#define SCT_OUTPUTCLR3_CLRn5_Pos 5 /*!< SCT OUTPUTCLR3: CLRn5 Position */ -#define SCT_OUTPUTCLR3_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn5_Pos) /*!< SCT OUTPUTCLR3: CLRn5 Mask */ -#define SCT_OUTPUTCLR3_CLRn6_Pos 6 /*!< SCT OUTPUTCLR3: CLRn6 Position */ -#define SCT_OUTPUTCLR3_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn6_Pos) /*!< SCT OUTPUTCLR3: CLRn6 Mask */ -#define SCT_OUTPUTCLR3_CLRn7_Pos 7 /*!< SCT OUTPUTCLR3: CLRn7 Position */ -#define SCT_OUTPUTCLR3_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn7_Pos) /*!< SCT OUTPUTCLR3: CLRn7 Mask */ -#define SCT_OUTPUTCLR3_CLRn8_Pos 8 /*!< SCT OUTPUTCLR3: CLRn8 Position */ -#define SCT_OUTPUTCLR3_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn8_Pos) /*!< SCT OUTPUTCLR3: CLRn8 Mask */ -#define SCT_OUTPUTCLR3_CLRn9_Pos 9 /*!< SCT OUTPUTCLR3: CLRn9 Position */ -#define SCT_OUTPUTCLR3_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn9_Pos) /*!< SCT OUTPUTCLR3: CLRn9 Mask */ -#define SCT_OUTPUTCLR3_CLRn10_Pos 10 /*!< SCT OUTPUTCLR3: CLRn10 Position */ -#define SCT_OUTPUTCLR3_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn10_Pos) /*!< SCT OUTPUTCLR3: CLRn10 Mask */ -#define SCT_OUTPUTCLR3_CLRn11_Pos 11 /*!< SCT OUTPUTCLR3: CLRn11 Position */ -#define SCT_OUTPUTCLR3_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn11_Pos) /*!< SCT OUTPUTCLR3: CLRn11 Mask */ -#define SCT_OUTPUTCLR3_CLRn12_Pos 12 /*!< SCT OUTPUTCLR3: CLRn12 Position */ -#define SCT_OUTPUTCLR3_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn12_Pos) /*!< SCT OUTPUTCLR3: CLRn12 Mask */ -#define SCT_OUTPUTCLR3_CLRn13_Pos 13 /*!< SCT OUTPUTCLR3: CLRn13 Position */ -#define SCT_OUTPUTCLR3_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn13_Pos) /*!< SCT OUTPUTCLR3: CLRn13 Mask */ -#define SCT_OUTPUTCLR3_CLRn14_Pos 14 /*!< SCT OUTPUTCLR3: CLRn14 Position */ -#define SCT_OUTPUTCLR3_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn14_Pos) /*!< SCT OUTPUTCLR3: CLRn14 Mask */ -#define SCT_OUTPUTCLR3_CLRn15_Pos 15 /*!< SCT OUTPUTCLR3: CLRn15 Position */ -#define SCT_OUTPUTCLR3_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR3_CLRn15_Pos) /*!< SCT OUTPUTCLR3: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET4 ----------------------------------------- -#define SCT_OUTPUTSET4_SETn0_Pos 0 /*!< SCT OUTPUTSET4: SETn0 Position */ -#define SCT_OUTPUTSET4_SETn0_Msk (0x01UL << SCT_OUTPUTSET4_SETn0_Pos) /*!< SCT OUTPUTSET4: SETn0 Mask */ -#define SCT_OUTPUTSET4_SETn1_Pos 1 /*!< SCT OUTPUTSET4: SETn1 Position */ -#define SCT_OUTPUTSET4_SETn1_Msk (0x01UL << SCT_OUTPUTSET4_SETn1_Pos) /*!< SCT OUTPUTSET4: SETn1 Mask */ -#define SCT_OUTPUTSET4_SETn2_Pos 2 /*!< SCT OUTPUTSET4: SETn2 Position */ -#define SCT_OUTPUTSET4_SETn2_Msk (0x01UL << SCT_OUTPUTSET4_SETn2_Pos) /*!< SCT OUTPUTSET4: SETn2 Mask */ -#define SCT_OUTPUTSET4_SETn3_Pos 3 /*!< SCT OUTPUTSET4: SETn3 Position */ -#define SCT_OUTPUTSET4_SETn3_Msk (0x01UL << SCT_OUTPUTSET4_SETn3_Pos) /*!< SCT OUTPUTSET4: SETn3 Mask */ -#define SCT_OUTPUTSET4_SETn4_Pos 4 /*!< SCT OUTPUTSET4: SETn4 Position */ -#define SCT_OUTPUTSET4_SETn4_Msk (0x01UL << SCT_OUTPUTSET4_SETn4_Pos) /*!< SCT OUTPUTSET4: SETn4 Mask */ -#define SCT_OUTPUTSET4_SETn5_Pos 5 /*!< SCT OUTPUTSET4: SETn5 Position */ -#define SCT_OUTPUTSET4_SETn5_Msk (0x01UL << SCT_OUTPUTSET4_SETn5_Pos) /*!< SCT OUTPUTSET4: SETn5 Mask */ -#define SCT_OUTPUTSET4_SETn6_Pos 6 /*!< SCT OUTPUTSET4: SETn6 Position */ -#define SCT_OUTPUTSET4_SETn6_Msk (0x01UL << SCT_OUTPUTSET4_SETn6_Pos) /*!< SCT OUTPUTSET4: SETn6 Mask */ -#define SCT_OUTPUTSET4_SETn7_Pos 7 /*!< SCT OUTPUTSET4: SETn7 Position */ -#define SCT_OUTPUTSET4_SETn7_Msk (0x01UL << SCT_OUTPUTSET4_SETn7_Pos) /*!< SCT OUTPUTSET4: SETn7 Mask */ -#define SCT_OUTPUTSET4_SETn8_Pos 8 /*!< SCT OUTPUTSET4: SETn8 Position */ -#define SCT_OUTPUTSET4_SETn8_Msk (0x01UL << SCT_OUTPUTSET4_SETn8_Pos) /*!< SCT OUTPUTSET4: SETn8 Mask */ -#define SCT_OUTPUTSET4_SETn9_Pos 9 /*!< SCT OUTPUTSET4: SETn9 Position */ -#define SCT_OUTPUTSET4_SETn9_Msk (0x01UL << SCT_OUTPUTSET4_SETn9_Pos) /*!< SCT OUTPUTSET4: SETn9 Mask */ -#define SCT_OUTPUTSET4_SETn10_Pos 10 /*!< SCT OUTPUTSET4: SETn10 Position */ -#define SCT_OUTPUTSET4_SETn10_Msk (0x01UL << SCT_OUTPUTSET4_SETn10_Pos) /*!< SCT OUTPUTSET4: SETn10 Mask */ -#define SCT_OUTPUTSET4_SETn11_Pos 11 /*!< SCT OUTPUTSET4: SETn11 Position */ -#define SCT_OUTPUTSET4_SETn11_Msk (0x01UL << SCT_OUTPUTSET4_SETn11_Pos) /*!< SCT OUTPUTSET4: SETn11 Mask */ -#define SCT_OUTPUTSET4_SETn12_Pos 12 /*!< SCT OUTPUTSET4: SETn12 Position */ -#define SCT_OUTPUTSET4_SETn12_Msk (0x01UL << SCT_OUTPUTSET4_SETn12_Pos) /*!< SCT OUTPUTSET4: SETn12 Mask */ -#define SCT_OUTPUTSET4_SETn13_Pos 13 /*!< SCT OUTPUTSET4: SETn13 Position */ -#define SCT_OUTPUTSET4_SETn13_Msk (0x01UL << SCT_OUTPUTSET4_SETn13_Pos) /*!< SCT OUTPUTSET4: SETn13 Mask */ -#define SCT_OUTPUTSET4_SETn14_Pos 14 /*!< SCT OUTPUTSET4: SETn14 Position */ -#define SCT_OUTPUTSET4_SETn14_Msk (0x01UL << SCT_OUTPUTSET4_SETn14_Pos) /*!< SCT OUTPUTSET4: SETn14 Mask */ -#define SCT_OUTPUTSET4_SETn15_Pos 15 /*!< SCT OUTPUTSET4: SETn15 Position */ -#define SCT_OUTPUTSET4_SETn15_Msk (0x01UL << SCT_OUTPUTSET4_SETn15_Pos) /*!< SCT OUTPUTSET4: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR4 ----------------------------------------- -#define SCT_OUTPUTCLR4_CLRn0_Pos 0 /*!< SCT OUTPUTCLR4: CLRn0 Position */ -#define SCT_OUTPUTCLR4_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn0_Pos) /*!< SCT OUTPUTCLR4: CLRn0 Mask */ -#define SCT_OUTPUTCLR4_CLRn1_Pos 1 /*!< SCT OUTPUTCLR4: CLRn1 Position */ -#define SCT_OUTPUTCLR4_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn1_Pos) /*!< SCT OUTPUTCLR4: CLRn1 Mask */ -#define SCT_OUTPUTCLR4_CLRn2_Pos 2 /*!< SCT OUTPUTCLR4: CLRn2 Position */ -#define SCT_OUTPUTCLR4_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn2_Pos) /*!< SCT OUTPUTCLR4: CLRn2 Mask */ -#define SCT_OUTPUTCLR4_CLRn3_Pos 3 /*!< SCT OUTPUTCLR4: CLRn3 Position */ -#define SCT_OUTPUTCLR4_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn3_Pos) /*!< SCT OUTPUTCLR4: CLRn3 Mask */ -#define SCT_OUTPUTCLR4_CLRn4_Pos 4 /*!< SCT OUTPUTCLR4: CLRn4 Position */ -#define SCT_OUTPUTCLR4_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn4_Pos) /*!< SCT OUTPUTCLR4: CLRn4 Mask */ -#define SCT_OUTPUTCLR4_CLRn5_Pos 5 /*!< SCT OUTPUTCLR4: CLRn5 Position */ -#define SCT_OUTPUTCLR4_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn5_Pos) /*!< SCT OUTPUTCLR4: CLRn5 Mask */ -#define SCT_OUTPUTCLR4_CLRn6_Pos 6 /*!< SCT OUTPUTCLR4: CLRn6 Position */ -#define SCT_OUTPUTCLR4_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn6_Pos) /*!< SCT OUTPUTCLR4: CLRn6 Mask */ -#define SCT_OUTPUTCLR4_CLRn7_Pos 7 /*!< SCT OUTPUTCLR4: CLRn7 Position */ -#define SCT_OUTPUTCLR4_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn7_Pos) /*!< SCT OUTPUTCLR4: CLRn7 Mask */ -#define SCT_OUTPUTCLR4_CLRn8_Pos 8 /*!< SCT OUTPUTCLR4: CLRn8 Position */ -#define SCT_OUTPUTCLR4_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn8_Pos) /*!< SCT OUTPUTCLR4: CLRn8 Mask */ -#define SCT_OUTPUTCLR4_CLRn9_Pos 9 /*!< SCT OUTPUTCLR4: CLRn9 Position */ -#define SCT_OUTPUTCLR4_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn9_Pos) /*!< SCT OUTPUTCLR4: CLRn9 Mask */ -#define SCT_OUTPUTCLR4_CLRn10_Pos 10 /*!< SCT OUTPUTCLR4: CLRn10 Position */ -#define SCT_OUTPUTCLR4_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn10_Pos) /*!< SCT OUTPUTCLR4: CLRn10 Mask */ -#define SCT_OUTPUTCLR4_CLRn11_Pos 11 /*!< SCT OUTPUTCLR4: CLRn11 Position */ -#define SCT_OUTPUTCLR4_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn11_Pos) /*!< SCT OUTPUTCLR4: CLRn11 Mask */ -#define SCT_OUTPUTCLR4_CLRn12_Pos 12 /*!< SCT OUTPUTCLR4: CLRn12 Position */ -#define SCT_OUTPUTCLR4_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn12_Pos) /*!< SCT OUTPUTCLR4: CLRn12 Mask */ -#define SCT_OUTPUTCLR4_CLRn13_Pos 13 /*!< SCT OUTPUTCLR4: CLRn13 Position */ -#define SCT_OUTPUTCLR4_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn13_Pos) /*!< SCT OUTPUTCLR4: CLRn13 Mask */ -#define SCT_OUTPUTCLR4_CLRn14_Pos 14 /*!< SCT OUTPUTCLR4: CLRn14 Position */ -#define SCT_OUTPUTCLR4_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn14_Pos) /*!< SCT OUTPUTCLR4: CLRn14 Mask */ -#define SCT_OUTPUTCLR4_CLRn15_Pos 15 /*!< SCT OUTPUTCLR4: CLRn15 Position */ -#define SCT_OUTPUTCLR4_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR4_CLRn15_Pos) /*!< SCT OUTPUTCLR4: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET5 ----------------------------------------- -#define SCT_OUTPUTSET5_SETn0_Pos 0 /*!< SCT OUTPUTSET5: SETn0 Position */ -#define SCT_OUTPUTSET5_SETn0_Msk (0x01UL << SCT_OUTPUTSET5_SETn0_Pos) /*!< SCT OUTPUTSET5: SETn0 Mask */ -#define SCT_OUTPUTSET5_SETn1_Pos 1 /*!< SCT OUTPUTSET5: SETn1 Position */ -#define SCT_OUTPUTSET5_SETn1_Msk (0x01UL << SCT_OUTPUTSET5_SETn1_Pos) /*!< SCT OUTPUTSET5: SETn1 Mask */ -#define SCT_OUTPUTSET5_SETn2_Pos 2 /*!< SCT OUTPUTSET5: SETn2 Position */ -#define SCT_OUTPUTSET5_SETn2_Msk (0x01UL << SCT_OUTPUTSET5_SETn2_Pos) /*!< SCT OUTPUTSET5: SETn2 Mask */ -#define SCT_OUTPUTSET5_SETn3_Pos 3 /*!< SCT OUTPUTSET5: SETn3 Position */ -#define SCT_OUTPUTSET5_SETn3_Msk (0x01UL << SCT_OUTPUTSET5_SETn3_Pos) /*!< SCT OUTPUTSET5: SETn3 Mask */ -#define SCT_OUTPUTSET5_SETn4_Pos 4 /*!< SCT OUTPUTSET5: SETn4 Position */ -#define SCT_OUTPUTSET5_SETn4_Msk (0x01UL << SCT_OUTPUTSET5_SETn4_Pos) /*!< SCT OUTPUTSET5: SETn4 Mask */ -#define SCT_OUTPUTSET5_SETn5_Pos 5 /*!< SCT OUTPUTSET5: SETn5 Position */ -#define SCT_OUTPUTSET5_SETn5_Msk (0x01UL << SCT_OUTPUTSET5_SETn5_Pos) /*!< SCT OUTPUTSET5: SETn5 Mask */ -#define SCT_OUTPUTSET5_SETn6_Pos 6 /*!< SCT OUTPUTSET5: SETn6 Position */ -#define SCT_OUTPUTSET5_SETn6_Msk (0x01UL << SCT_OUTPUTSET5_SETn6_Pos) /*!< SCT OUTPUTSET5: SETn6 Mask */ -#define SCT_OUTPUTSET5_SETn7_Pos 7 /*!< SCT OUTPUTSET5: SETn7 Position */ -#define SCT_OUTPUTSET5_SETn7_Msk (0x01UL << SCT_OUTPUTSET5_SETn7_Pos) /*!< SCT OUTPUTSET5: SETn7 Mask */ -#define SCT_OUTPUTSET5_SETn8_Pos 8 /*!< SCT OUTPUTSET5: SETn8 Position */ -#define SCT_OUTPUTSET5_SETn8_Msk (0x01UL << SCT_OUTPUTSET5_SETn8_Pos) /*!< SCT OUTPUTSET5: SETn8 Mask */ -#define SCT_OUTPUTSET5_SETn9_Pos 9 /*!< SCT OUTPUTSET5: SETn9 Position */ -#define SCT_OUTPUTSET5_SETn9_Msk (0x01UL << SCT_OUTPUTSET5_SETn9_Pos) /*!< SCT OUTPUTSET5: SETn9 Mask */ -#define SCT_OUTPUTSET5_SETn10_Pos 10 /*!< SCT OUTPUTSET5: SETn10 Position */ -#define SCT_OUTPUTSET5_SETn10_Msk (0x01UL << SCT_OUTPUTSET5_SETn10_Pos) /*!< SCT OUTPUTSET5: SETn10 Mask */ -#define SCT_OUTPUTSET5_SETn11_Pos 11 /*!< SCT OUTPUTSET5: SETn11 Position */ -#define SCT_OUTPUTSET5_SETn11_Msk (0x01UL << SCT_OUTPUTSET5_SETn11_Pos) /*!< SCT OUTPUTSET5: SETn11 Mask */ -#define SCT_OUTPUTSET5_SETn12_Pos 12 /*!< SCT OUTPUTSET5: SETn12 Position */ -#define SCT_OUTPUTSET5_SETn12_Msk (0x01UL << SCT_OUTPUTSET5_SETn12_Pos) /*!< SCT OUTPUTSET5: SETn12 Mask */ -#define SCT_OUTPUTSET5_SETn13_Pos 13 /*!< SCT OUTPUTSET5: SETn13 Position */ -#define SCT_OUTPUTSET5_SETn13_Msk (0x01UL << SCT_OUTPUTSET5_SETn13_Pos) /*!< SCT OUTPUTSET5: SETn13 Mask */ -#define SCT_OUTPUTSET5_SETn14_Pos 14 /*!< SCT OUTPUTSET5: SETn14 Position */ -#define SCT_OUTPUTSET5_SETn14_Msk (0x01UL << SCT_OUTPUTSET5_SETn14_Pos) /*!< SCT OUTPUTSET5: SETn14 Mask */ -#define SCT_OUTPUTSET5_SETn15_Pos 15 /*!< SCT OUTPUTSET5: SETn15 Position */ -#define SCT_OUTPUTSET5_SETn15_Msk (0x01UL << SCT_OUTPUTSET5_SETn15_Pos) /*!< SCT OUTPUTSET5: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR5 ----------------------------------------- -#define SCT_OUTPUTCLR5_CLRn0_Pos 0 /*!< SCT OUTPUTCLR5: CLRn0 Position */ -#define SCT_OUTPUTCLR5_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn0_Pos) /*!< SCT OUTPUTCLR5: CLRn0 Mask */ -#define SCT_OUTPUTCLR5_CLRn1_Pos 1 /*!< SCT OUTPUTCLR5: CLRn1 Position */ -#define SCT_OUTPUTCLR5_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn1_Pos) /*!< SCT OUTPUTCLR5: CLRn1 Mask */ -#define SCT_OUTPUTCLR5_CLRn2_Pos 2 /*!< SCT OUTPUTCLR5: CLRn2 Position */ -#define SCT_OUTPUTCLR5_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn2_Pos) /*!< SCT OUTPUTCLR5: CLRn2 Mask */ -#define SCT_OUTPUTCLR5_CLRn3_Pos 3 /*!< SCT OUTPUTCLR5: CLRn3 Position */ -#define SCT_OUTPUTCLR5_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn3_Pos) /*!< SCT OUTPUTCLR5: CLRn3 Mask */ -#define SCT_OUTPUTCLR5_CLRn4_Pos 4 /*!< SCT OUTPUTCLR5: CLRn4 Position */ -#define SCT_OUTPUTCLR5_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn4_Pos) /*!< SCT OUTPUTCLR5: CLRn4 Mask */ -#define SCT_OUTPUTCLR5_CLRn5_Pos 5 /*!< SCT OUTPUTCLR5: CLRn5 Position */ -#define SCT_OUTPUTCLR5_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn5_Pos) /*!< SCT OUTPUTCLR5: CLRn5 Mask */ -#define SCT_OUTPUTCLR5_CLRn6_Pos 6 /*!< SCT OUTPUTCLR5: CLRn6 Position */ -#define SCT_OUTPUTCLR5_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn6_Pos) /*!< SCT OUTPUTCLR5: CLRn6 Mask */ -#define SCT_OUTPUTCLR5_CLRn7_Pos 7 /*!< SCT OUTPUTCLR5: CLRn7 Position */ -#define SCT_OUTPUTCLR5_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn7_Pos) /*!< SCT OUTPUTCLR5: CLRn7 Mask */ -#define SCT_OUTPUTCLR5_CLRn8_Pos 8 /*!< SCT OUTPUTCLR5: CLRn8 Position */ -#define SCT_OUTPUTCLR5_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn8_Pos) /*!< SCT OUTPUTCLR5: CLRn8 Mask */ -#define SCT_OUTPUTCLR5_CLRn9_Pos 9 /*!< SCT OUTPUTCLR5: CLRn9 Position */ -#define SCT_OUTPUTCLR5_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn9_Pos) /*!< SCT OUTPUTCLR5: CLRn9 Mask */ -#define SCT_OUTPUTCLR5_CLRn10_Pos 10 /*!< SCT OUTPUTCLR5: CLRn10 Position */ -#define SCT_OUTPUTCLR5_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn10_Pos) /*!< SCT OUTPUTCLR5: CLRn10 Mask */ -#define SCT_OUTPUTCLR5_CLRn11_Pos 11 /*!< SCT OUTPUTCLR5: CLRn11 Position */ -#define SCT_OUTPUTCLR5_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn11_Pos) /*!< SCT OUTPUTCLR5: CLRn11 Mask */ -#define SCT_OUTPUTCLR5_CLRn12_Pos 12 /*!< SCT OUTPUTCLR5: CLRn12 Position */ -#define SCT_OUTPUTCLR5_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn12_Pos) /*!< SCT OUTPUTCLR5: CLRn12 Mask */ -#define SCT_OUTPUTCLR5_CLRn13_Pos 13 /*!< SCT OUTPUTCLR5: CLRn13 Position */ -#define SCT_OUTPUTCLR5_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn13_Pos) /*!< SCT OUTPUTCLR5: CLRn13 Mask */ -#define SCT_OUTPUTCLR5_CLRn14_Pos 14 /*!< SCT OUTPUTCLR5: CLRn14 Position */ -#define SCT_OUTPUTCLR5_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn14_Pos) /*!< SCT OUTPUTCLR5: CLRn14 Mask */ -#define SCT_OUTPUTCLR5_CLRn15_Pos 15 /*!< SCT OUTPUTCLR5: CLRn15 Position */ -#define SCT_OUTPUTCLR5_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR5_CLRn15_Pos) /*!< SCT OUTPUTCLR5: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET6 ----------------------------------------- -#define SCT_OUTPUTSET6_SETn0_Pos 0 /*!< SCT OUTPUTSET6: SETn0 Position */ -#define SCT_OUTPUTSET6_SETn0_Msk (0x01UL << SCT_OUTPUTSET6_SETn0_Pos) /*!< SCT OUTPUTSET6: SETn0 Mask */ -#define SCT_OUTPUTSET6_SETn1_Pos 1 /*!< SCT OUTPUTSET6: SETn1 Position */ -#define SCT_OUTPUTSET6_SETn1_Msk (0x01UL << SCT_OUTPUTSET6_SETn1_Pos) /*!< SCT OUTPUTSET6: SETn1 Mask */ -#define SCT_OUTPUTSET6_SETn2_Pos 2 /*!< SCT OUTPUTSET6: SETn2 Position */ -#define SCT_OUTPUTSET6_SETn2_Msk (0x01UL << SCT_OUTPUTSET6_SETn2_Pos) /*!< SCT OUTPUTSET6: SETn2 Mask */ -#define SCT_OUTPUTSET6_SETn3_Pos 3 /*!< SCT OUTPUTSET6: SETn3 Position */ -#define SCT_OUTPUTSET6_SETn3_Msk (0x01UL << SCT_OUTPUTSET6_SETn3_Pos) /*!< SCT OUTPUTSET6: SETn3 Mask */ -#define SCT_OUTPUTSET6_SETn4_Pos 4 /*!< SCT OUTPUTSET6: SETn4 Position */ -#define SCT_OUTPUTSET6_SETn4_Msk (0x01UL << SCT_OUTPUTSET6_SETn4_Pos) /*!< SCT OUTPUTSET6: SETn4 Mask */ -#define SCT_OUTPUTSET6_SETn5_Pos 5 /*!< SCT OUTPUTSET6: SETn5 Position */ -#define SCT_OUTPUTSET6_SETn5_Msk (0x01UL << SCT_OUTPUTSET6_SETn5_Pos) /*!< SCT OUTPUTSET6: SETn5 Mask */ -#define SCT_OUTPUTSET6_SETn6_Pos 6 /*!< SCT OUTPUTSET6: SETn6 Position */ -#define SCT_OUTPUTSET6_SETn6_Msk (0x01UL << SCT_OUTPUTSET6_SETn6_Pos) /*!< SCT OUTPUTSET6: SETn6 Mask */ -#define SCT_OUTPUTSET6_SETn7_Pos 7 /*!< SCT OUTPUTSET6: SETn7 Position */ -#define SCT_OUTPUTSET6_SETn7_Msk (0x01UL << SCT_OUTPUTSET6_SETn7_Pos) /*!< SCT OUTPUTSET6: SETn7 Mask */ -#define SCT_OUTPUTSET6_SETn8_Pos 8 /*!< SCT OUTPUTSET6: SETn8 Position */ -#define SCT_OUTPUTSET6_SETn8_Msk (0x01UL << SCT_OUTPUTSET6_SETn8_Pos) /*!< SCT OUTPUTSET6: SETn8 Mask */ -#define SCT_OUTPUTSET6_SETn9_Pos 9 /*!< SCT OUTPUTSET6: SETn9 Position */ -#define SCT_OUTPUTSET6_SETn9_Msk (0x01UL << SCT_OUTPUTSET6_SETn9_Pos) /*!< SCT OUTPUTSET6: SETn9 Mask */ -#define SCT_OUTPUTSET6_SETn10_Pos 10 /*!< SCT OUTPUTSET6: SETn10 Position */ -#define SCT_OUTPUTSET6_SETn10_Msk (0x01UL << SCT_OUTPUTSET6_SETn10_Pos) /*!< SCT OUTPUTSET6: SETn10 Mask */ -#define SCT_OUTPUTSET6_SETn11_Pos 11 /*!< SCT OUTPUTSET6: SETn11 Position */ -#define SCT_OUTPUTSET6_SETn11_Msk (0x01UL << SCT_OUTPUTSET6_SETn11_Pos) /*!< SCT OUTPUTSET6: SETn11 Mask */ -#define SCT_OUTPUTSET6_SETn12_Pos 12 /*!< SCT OUTPUTSET6: SETn12 Position */ -#define SCT_OUTPUTSET6_SETn12_Msk (0x01UL << SCT_OUTPUTSET6_SETn12_Pos) /*!< SCT OUTPUTSET6: SETn12 Mask */ -#define SCT_OUTPUTSET6_SETn13_Pos 13 /*!< SCT OUTPUTSET6: SETn13 Position */ -#define SCT_OUTPUTSET6_SETn13_Msk (0x01UL << SCT_OUTPUTSET6_SETn13_Pos) /*!< SCT OUTPUTSET6: SETn13 Mask */ -#define SCT_OUTPUTSET6_SETn14_Pos 14 /*!< SCT OUTPUTSET6: SETn14 Position */ -#define SCT_OUTPUTSET6_SETn14_Msk (0x01UL << SCT_OUTPUTSET6_SETn14_Pos) /*!< SCT OUTPUTSET6: SETn14 Mask */ -#define SCT_OUTPUTSET6_SETn15_Pos 15 /*!< SCT OUTPUTSET6: SETn15 Position */ -#define SCT_OUTPUTSET6_SETn15_Msk (0x01UL << SCT_OUTPUTSET6_SETn15_Pos) /*!< SCT OUTPUTSET6: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR6 ----------------------------------------- -#define SCT_OUTPUTCLR6_CLRn0_Pos 0 /*!< SCT OUTPUTCLR6: CLRn0 Position */ -#define SCT_OUTPUTCLR6_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn0_Pos) /*!< SCT OUTPUTCLR6: CLRn0 Mask */ -#define SCT_OUTPUTCLR6_CLRn1_Pos 1 /*!< SCT OUTPUTCLR6: CLRn1 Position */ -#define SCT_OUTPUTCLR6_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn1_Pos) /*!< SCT OUTPUTCLR6: CLRn1 Mask */ -#define SCT_OUTPUTCLR6_CLRn2_Pos 2 /*!< SCT OUTPUTCLR6: CLRn2 Position */ -#define SCT_OUTPUTCLR6_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn2_Pos) /*!< SCT OUTPUTCLR6: CLRn2 Mask */ -#define SCT_OUTPUTCLR6_CLRn3_Pos 3 /*!< SCT OUTPUTCLR6: CLRn3 Position */ -#define SCT_OUTPUTCLR6_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn3_Pos) /*!< SCT OUTPUTCLR6: CLRn3 Mask */ -#define SCT_OUTPUTCLR6_CLRn4_Pos 4 /*!< SCT OUTPUTCLR6: CLRn4 Position */ -#define SCT_OUTPUTCLR6_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn4_Pos) /*!< SCT OUTPUTCLR6: CLRn4 Mask */ -#define SCT_OUTPUTCLR6_CLRn5_Pos 5 /*!< SCT OUTPUTCLR6: CLRn5 Position */ -#define SCT_OUTPUTCLR6_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn5_Pos) /*!< SCT OUTPUTCLR6: CLRn5 Mask */ -#define SCT_OUTPUTCLR6_CLRn6_Pos 6 /*!< SCT OUTPUTCLR6: CLRn6 Position */ -#define SCT_OUTPUTCLR6_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn6_Pos) /*!< SCT OUTPUTCLR6: CLRn6 Mask */ -#define SCT_OUTPUTCLR6_CLRn7_Pos 7 /*!< SCT OUTPUTCLR6: CLRn7 Position */ -#define SCT_OUTPUTCLR6_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn7_Pos) /*!< SCT OUTPUTCLR6: CLRn7 Mask */ -#define SCT_OUTPUTCLR6_CLRn8_Pos 8 /*!< SCT OUTPUTCLR6: CLRn8 Position */ -#define SCT_OUTPUTCLR6_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn8_Pos) /*!< SCT OUTPUTCLR6: CLRn8 Mask */ -#define SCT_OUTPUTCLR6_CLRn9_Pos 9 /*!< SCT OUTPUTCLR6: CLRn9 Position */ -#define SCT_OUTPUTCLR6_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn9_Pos) /*!< SCT OUTPUTCLR6: CLRn9 Mask */ -#define SCT_OUTPUTCLR6_CLRn10_Pos 10 /*!< SCT OUTPUTCLR6: CLRn10 Position */ -#define SCT_OUTPUTCLR6_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn10_Pos) /*!< SCT OUTPUTCLR6: CLRn10 Mask */ -#define SCT_OUTPUTCLR6_CLRn11_Pos 11 /*!< SCT OUTPUTCLR6: CLRn11 Position */ -#define SCT_OUTPUTCLR6_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn11_Pos) /*!< SCT OUTPUTCLR6: CLRn11 Mask */ -#define SCT_OUTPUTCLR6_CLRn12_Pos 12 /*!< SCT OUTPUTCLR6: CLRn12 Position */ -#define SCT_OUTPUTCLR6_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn12_Pos) /*!< SCT OUTPUTCLR6: CLRn12 Mask */ -#define SCT_OUTPUTCLR6_CLRn13_Pos 13 /*!< SCT OUTPUTCLR6: CLRn13 Position */ -#define SCT_OUTPUTCLR6_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn13_Pos) /*!< SCT OUTPUTCLR6: CLRn13 Mask */ -#define SCT_OUTPUTCLR6_CLRn14_Pos 14 /*!< SCT OUTPUTCLR6: CLRn14 Position */ -#define SCT_OUTPUTCLR6_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn14_Pos) /*!< SCT OUTPUTCLR6: CLRn14 Mask */ -#define SCT_OUTPUTCLR6_CLRn15_Pos 15 /*!< SCT OUTPUTCLR6: CLRn15 Position */ -#define SCT_OUTPUTCLR6_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR6_CLRn15_Pos) /*!< SCT OUTPUTCLR6: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET7 ----------------------------------------- -#define SCT_OUTPUTSET7_SETn0_Pos 0 /*!< SCT OUTPUTSET7: SETn0 Position */ -#define SCT_OUTPUTSET7_SETn0_Msk (0x01UL << SCT_OUTPUTSET7_SETn0_Pos) /*!< SCT OUTPUTSET7: SETn0 Mask */ -#define SCT_OUTPUTSET7_SETn1_Pos 1 /*!< SCT OUTPUTSET7: SETn1 Position */ -#define SCT_OUTPUTSET7_SETn1_Msk (0x01UL << SCT_OUTPUTSET7_SETn1_Pos) /*!< SCT OUTPUTSET7: SETn1 Mask */ -#define SCT_OUTPUTSET7_SETn2_Pos 2 /*!< SCT OUTPUTSET7: SETn2 Position */ -#define SCT_OUTPUTSET7_SETn2_Msk (0x01UL << SCT_OUTPUTSET7_SETn2_Pos) /*!< SCT OUTPUTSET7: SETn2 Mask */ -#define SCT_OUTPUTSET7_SETn3_Pos 3 /*!< SCT OUTPUTSET7: SETn3 Position */ -#define SCT_OUTPUTSET7_SETn3_Msk (0x01UL << SCT_OUTPUTSET7_SETn3_Pos) /*!< SCT OUTPUTSET7: SETn3 Mask */ -#define SCT_OUTPUTSET7_SETn4_Pos 4 /*!< SCT OUTPUTSET7: SETn4 Position */ -#define SCT_OUTPUTSET7_SETn4_Msk (0x01UL << SCT_OUTPUTSET7_SETn4_Pos) /*!< SCT OUTPUTSET7: SETn4 Mask */ -#define SCT_OUTPUTSET7_SETn5_Pos 5 /*!< SCT OUTPUTSET7: SETn5 Position */ -#define SCT_OUTPUTSET7_SETn5_Msk (0x01UL << SCT_OUTPUTSET7_SETn5_Pos) /*!< SCT OUTPUTSET7: SETn5 Mask */ -#define SCT_OUTPUTSET7_SETn6_Pos 6 /*!< SCT OUTPUTSET7: SETn6 Position */ -#define SCT_OUTPUTSET7_SETn6_Msk (0x01UL << SCT_OUTPUTSET7_SETn6_Pos) /*!< SCT OUTPUTSET7: SETn6 Mask */ -#define SCT_OUTPUTSET7_SETn7_Pos 7 /*!< SCT OUTPUTSET7: SETn7 Position */ -#define SCT_OUTPUTSET7_SETn7_Msk (0x01UL << SCT_OUTPUTSET7_SETn7_Pos) /*!< SCT OUTPUTSET7: SETn7 Mask */ -#define SCT_OUTPUTSET7_SETn8_Pos 8 /*!< SCT OUTPUTSET7: SETn8 Position */ -#define SCT_OUTPUTSET7_SETn8_Msk (0x01UL << SCT_OUTPUTSET7_SETn8_Pos) /*!< SCT OUTPUTSET7: SETn8 Mask */ -#define SCT_OUTPUTSET7_SETn9_Pos 9 /*!< SCT OUTPUTSET7: SETn9 Position */ -#define SCT_OUTPUTSET7_SETn9_Msk (0x01UL << SCT_OUTPUTSET7_SETn9_Pos) /*!< SCT OUTPUTSET7: SETn9 Mask */ -#define SCT_OUTPUTSET7_SETn10_Pos 10 /*!< SCT OUTPUTSET7: SETn10 Position */ -#define SCT_OUTPUTSET7_SETn10_Msk (0x01UL << SCT_OUTPUTSET7_SETn10_Pos) /*!< SCT OUTPUTSET7: SETn10 Mask */ -#define SCT_OUTPUTSET7_SETn11_Pos 11 /*!< SCT OUTPUTSET7: SETn11 Position */ -#define SCT_OUTPUTSET7_SETn11_Msk (0x01UL << SCT_OUTPUTSET7_SETn11_Pos) /*!< SCT OUTPUTSET7: SETn11 Mask */ -#define SCT_OUTPUTSET7_SETn12_Pos 12 /*!< SCT OUTPUTSET7: SETn12 Position */ -#define SCT_OUTPUTSET7_SETn12_Msk (0x01UL << SCT_OUTPUTSET7_SETn12_Pos) /*!< SCT OUTPUTSET7: SETn12 Mask */ -#define SCT_OUTPUTSET7_SETn13_Pos 13 /*!< SCT OUTPUTSET7: SETn13 Position */ -#define SCT_OUTPUTSET7_SETn13_Msk (0x01UL << SCT_OUTPUTSET7_SETn13_Pos) /*!< SCT OUTPUTSET7: SETn13 Mask */ -#define SCT_OUTPUTSET7_SETn14_Pos 14 /*!< SCT OUTPUTSET7: SETn14 Position */ -#define SCT_OUTPUTSET7_SETn14_Msk (0x01UL << SCT_OUTPUTSET7_SETn14_Pos) /*!< SCT OUTPUTSET7: SETn14 Mask */ -#define SCT_OUTPUTSET7_SETn15_Pos 15 /*!< SCT OUTPUTSET7: SETn15 Position */ -#define SCT_OUTPUTSET7_SETn15_Msk (0x01UL << SCT_OUTPUTSET7_SETn15_Pos) /*!< SCT OUTPUTSET7: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR7 ----------------------------------------- -#define SCT_OUTPUTCLR7_CLRn0_Pos 0 /*!< SCT OUTPUTCLR7: CLRn0 Position */ -#define SCT_OUTPUTCLR7_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn0_Pos) /*!< SCT OUTPUTCLR7: CLRn0 Mask */ -#define SCT_OUTPUTCLR7_CLRn1_Pos 1 /*!< SCT OUTPUTCLR7: CLRn1 Position */ -#define SCT_OUTPUTCLR7_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn1_Pos) /*!< SCT OUTPUTCLR7: CLRn1 Mask */ -#define SCT_OUTPUTCLR7_CLRn2_Pos 2 /*!< SCT OUTPUTCLR7: CLRn2 Position */ -#define SCT_OUTPUTCLR7_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn2_Pos) /*!< SCT OUTPUTCLR7: CLRn2 Mask */ -#define SCT_OUTPUTCLR7_CLRn3_Pos 3 /*!< SCT OUTPUTCLR7: CLRn3 Position */ -#define SCT_OUTPUTCLR7_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn3_Pos) /*!< SCT OUTPUTCLR7: CLRn3 Mask */ -#define SCT_OUTPUTCLR7_CLRn4_Pos 4 /*!< SCT OUTPUTCLR7: CLRn4 Position */ -#define SCT_OUTPUTCLR7_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn4_Pos) /*!< SCT OUTPUTCLR7: CLRn4 Mask */ -#define SCT_OUTPUTCLR7_CLRn5_Pos 5 /*!< SCT OUTPUTCLR7: CLRn5 Position */ -#define SCT_OUTPUTCLR7_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn5_Pos) /*!< SCT OUTPUTCLR7: CLRn5 Mask */ -#define SCT_OUTPUTCLR7_CLRn6_Pos 6 /*!< SCT OUTPUTCLR7: CLRn6 Position */ -#define SCT_OUTPUTCLR7_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn6_Pos) /*!< SCT OUTPUTCLR7: CLRn6 Mask */ -#define SCT_OUTPUTCLR7_CLRn7_Pos 7 /*!< SCT OUTPUTCLR7: CLRn7 Position */ -#define SCT_OUTPUTCLR7_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn7_Pos) /*!< SCT OUTPUTCLR7: CLRn7 Mask */ -#define SCT_OUTPUTCLR7_CLRn8_Pos 8 /*!< SCT OUTPUTCLR7: CLRn8 Position */ -#define SCT_OUTPUTCLR7_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn8_Pos) /*!< SCT OUTPUTCLR7: CLRn8 Mask */ -#define SCT_OUTPUTCLR7_CLRn9_Pos 9 /*!< SCT OUTPUTCLR7: CLRn9 Position */ -#define SCT_OUTPUTCLR7_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn9_Pos) /*!< SCT OUTPUTCLR7: CLRn9 Mask */ -#define SCT_OUTPUTCLR7_CLRn10_Pos 10 /*!< SCT OUTPUTCLR7: CLRn10 Position */ -#define SCT_OUTPUTCLR7_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn10_Pos) /*!< SCT OUTPUTCLR7: CLRn10 Mask */ -#define SCT_OUTPUTCLR7_CLRn11_Pos 11 /*!< SCT OUTPUTCLR7: CLRn11 Position */ -#define SCT_OUTPUTCLR7_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn11_Pos) /*!< SCT OUTPUTCLR7: CLRn11 Mask */ -#define SCT_OUTPUTCLR7_CLRn12_Pos 12 /*!< SCT OUTPUTCLR7: CLRn12 Position */ -#define SCT_OUTPUTCLR7_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn12_Pos) /*!< SCT OUTPUTCLR7: CLRn12 Mask */ -#define SCT_OUTPUTCLR7_CLRn13_Pos 13 /*!< SCT OUTPUTCLR7: CLRn13 Position */ -#define SCT_OUTPUTCLR7_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn13_Pos) /*!< SCT OUTPUTCLR7: CLRn13 Mask */ -#define SCT_OUTPUTCLR7_CLRn14_Pos 14 /*!< SCT OUTPUTCLR7: CLRn14 Position */ -#define SCT_OUTPUTCLR7_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn14_Pos) /*!< SCT OUTPUTCLR7: CLRn14 Mask */ -#define SCT_OUTPUTCLR7_CLRn15_Pos 15 /*!< SCT OUTPUTCLR7: CLRn15 Position */ -#define SCT_OUTPUTCLR7_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR7_CLRn15_Pos) /*!< SCT OUTPUTCLR7: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET8 ----------------------------------------- -#define SCT_OUTPUTSET8_SETn0_Pos 0 /*!< SCT OUTPUTSET8: SETn0 Position */ -#define SCT_OUTPUTSET8_SETn0_Msk (0x01UL << SCT_OUTPUTSET8_SETn0_Pos) /*!< SCT OUTPUTSET8: SETn0 Mask */ -#define SCT_OUTPUTSET8_SETn1_Pos 1 /*!< SCT OUTPUTSET8: SETn1 Position */ -#define SCT_OUTPUTSET8_SETn1_Msk (0x01UL << SCT_OUTPUTSET8_SETn1_Pos) /*!< SCT OUTPUTSET8: SETn1 Mask */ -#define SCT_OUTPUTSET8_SETn2_Pos 2 /*!< SCT OUTPUTSET8: SETn2 Position */ -#define SCT_OUTPUTSET8_SETn2_Msk (0x01UL << SCT_OUTPUTSET8_SETn2_Pos) /*!< SCT OUTPUTSET8: SETn2 Mask */ -#define SCT_OUTPUTSET8_SETn3_Pos 3 /*!< SCT OUTPUTSET8: SETn3 Position */ -#define SCT_OUTPUTSET8_SETn3_Msk (0x01UL << SCT_OUTPUTSET8_SETn3_Pos) /*!< SCT OUTPUTSET8: SETn3 Mask */ -#define SCT_OUTPUTSET8_SETn4_Pos 4 /*!< SCT OUTPUTSET8: SETn4 Position */ -#define SCT_OUTPUTSET8_SETn4_Msk (0x01UL << SCT_OUTPUTSET8_SETn4_Pos) /*!< SCT OUTPUTSET8: SETn4 Mask */ -#define SCT_OUTPUTSET8_SETn5_Pos 5 /*!< SCT OUTPUTSET8: SETn5 Position */ -#define SCT_OUTPUTSET8_SETn5_Msk (0x01UL << SCT_OUTPUTSET8_SETn5_Pos) /*!< SCT OUTPUTSET8: SETn5 Mask */ -#define SCT_OUTPUTSET8_SETn6_Pos 6 /*!< SCT OUTPUTSET8: SETn6 Position */ -#define SCT_OUTPUTSET8_SETn6_Msk (0x01UL << SCT_OUTPUTSET8_SETn6_Pos) /*!< SCT OUTPUTSET8: SETn6 Mask */ -#define SCT_OUTPUTSET8_SETn7_Pos 7 /*!< SCT OUTPUTSET8: SETn7 Position */ -#define SCT_OUTPUTSET8_SETn7_Msk (0x01UL << SCT_OUTPUTSET8_SETn7_Pos) /*!< SCT OUTPUTSET8: SETn7 Mask */ -#define SCT_OUTPUTSET8_SETn8_Pos 8 /*!< SCT OUTPUTSET8: SETn8 Position */ -#define SCT_OUTPUTSET8_SETn8_Msk (0x01UL << SCT_OUTPUTSET8_SETn8_Pos) /*!< SCT OUTPUTSET8: SETn8 Mask */ -#define SCT_OUTPUTSET8_SETn9_Pos 9 /*!< SCT OUTPUTSET8: SETn9 Position */ -#define SCT_OUTPUTSET8_SETn9_Msk (0x01UL << SCT_OUTPUTSET8_SETn9_Pos) /*!< SCT OUTPUTSET8: SETn9 Mask */ -#define SCT_OUTPUTSET8_SETn10_Pos 10 /*!< SCT OUTPUTSET8: SETn10 Position */ -#define SCT_OUTPUTSET8_SETn10_Msk (0x01UL << SCT_OUTPUTSET8_SETn10_Pos) /*!< SCT OUTPUTSET8: SETn10 Mask */ -#define SCT_OUTPUTSET8_SETn11_Pos 11 /*!< SCT OUTPUTSET8: SETn11 Position */ -#define SCT_OUTPUTSET8_SETn11_Msk (0x01UL << SCT_OUTPUTSET8_SETn11_Pos) /*!< SCT OUTPUTSET8: SETn11 Mask */ -#define SCT_OUTPUTSET8_SETn12_Pos 12 /*!< SCT OUTPUTSET8: SETn12 Position */ -#define SCT_OUTPUTSET8_SETn12_Msk (0x01UL << SCT_OUTPUTSET8_SETn12_Pos) /*!< SCT OUTPUTSET8: SETn12 Mask */ -#define SCT_OUTPUTSET8_SETn13_Pos 13 /*!< SCT OUTPUTSET8: SETn13 Position */ -#define SCT_OUTPUTSET8_SETn13_Msk (0x01UL << SCT_OUTPUTSET8_SETn13_Pos) /*!< SCT OUTPUTSET8: SETn13 Mask */ -#define SCT_OUTPUTSET8_SETn14_Pos 14 /*!< SCT OUTPUTSET8: SETn14 Position */ -#define SCT_OUTPUTSET8_SETn14_Msk (0x01UL << SCT_OUTPUTSET8_SETn14_Pos) /*!< SCT OUTPUTSET8: SETn14 Mask */ -#define SCT_OUTPUTSET8_SETn15_Pos 15 /*!< SCT OUTPUTSET8: SETn15 Position */ -#define SCT_OUTPUTSET8_SETn15_Msk (0x01UL << SCT_OUTPUTSET8_SETn15_Pos) /*!< SCT OUTPUTSET8: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR8 ----------------------------------------- -#define SCT_OUTPUTCLR8_CLRn0_Pos 0 /*!< SCT OUTPUTCLR8: CLRn0 Position */ -#define SCT_OUTPUTCLR8_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn0_Pos) /*!< SCT OUTPUTCLR8: CLRn0 Mask */ -#define SCT_OUTPUTCLR8_CLRn1_Pos 1 /*!< SCT OUTPUTCLR8: CLRn1 Position */ -#define SCT_OUTPUTCLR8_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn1_Pos) /*!< SCT OUTPUTCLR8: CLRn1 Mask */ -#define SCT_OUTPUTCLR8_CLRn2_Pos 2 /*!< SCT OUTPUTCLR8: CLRn2 Position */ -#define SCT_OUTPUTCLR8_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn2_Pos) /*!< SCT OUTPUTCLR8: CLRn2 Mask */ -#define SCT_OUTPUTCLR8_CLRn3_Pos 3 /*!< SCT OUTPUTCLR8: CLRn3 Position */ -#define SCT_OUTPUTCLR8_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn3_Pos) /*!< SCT OUTPUTCLR8: CLRn3 Mask */ -#define SCT_OUTPUTCLR8_CLRn4_Pos 4 /*!< SCT OUTPUTCLR8: CLRn4 Position */ -#define SCT_OUTPUTCLR8_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn4_Pos) /*!< SCT OUTPUTCLR8: CLRn4 Mask */ -#define SCT_OUTPUTCLR8_CLRn5_Pos 5 /*!< SCT OUTPUTCLR8: CLRn5 Position */ -#define SCT_OUTPUTCLR8_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn5_Pos) /*!< SCT OUTPUTCLR8: CLRn5 Mask */ -#define SCT_OUTPUTCLR8_CLRn6_Pos 6 /*!< SCT OUTPUTCLR8: CLRn6 Position */ -#define SCT_OUTPUTCLR8_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn6_Pos) /*!< SCT OUTPUTCLR8: CLRn6 Mask */ -#define SCT_OUTPUTCLR8_CLRn7_Pos 7 /*!< SCT OUTPUTCLR8: CLRn7 Position */ -#define SCT_OUTPUTCLR8_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn7_Pos) /*!< SCT OUTPUTCLR8: CLRn7 Mask */ -#define SCT_OUTPUTCLR8_CLRn8_Pos 8 /*!< SCT OUTPUTCLR8: CLRn8 Position */ -#define SCT_OUTPUTCLR8_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn8_Pos) /*!< SCT OUTPUTCLR8: CLRn8 Mask */ -#define SCT_OUTPUTCLR8_CLRn9_Pos 9 /*!< SCT OUTPUTCLR8: CLRn9 Position */ -#define SCT_OUTPUTCLR8_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn9_Pos) /*!< SCT OUTPUTCLR8: CLRn9 Mask */ -#define SCT_OUTPUTCLR8_CLRn10_Pos 10 /*!< SCT OUTPUTCLR8: CLRn10 Position */ -#define SCT_OUTPUTCLR8_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn10_Pos) /*!< SCT OUTPUTCLR8: CLRn10 Mask */ -#define SCT_OUTPUTCLR8_CLRn11_Pos 11 /*!< SCT OUTPUTCLR8: CLRn11 Position */ -#define SCT_OUTPUTCLR8_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn11_Pos) /*!< SCT OUTPUTCLR8: CLRn11 Mask */ -#define SCT_OUTPUTCLR8_CLRn12_Pos 12 /*!< SCT OUTPUTCLR8: CLRn12 Position */ -#define SCT_OUTPUTCLR8_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn12_Pos) /*!< SCT OUTPUTCLR8: CLRn12 Mask */ -#define SCT_OUTPUTCLR8_CLRn13_Pos 13 /*!< SCT OUTPUTCLR8: CLRn13 Position */ -#define SCT_OUTPUTCLR8_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn13_Pos) /*!< SCT OUTPUTCLR8: CLRn13 Mask */ -#define SCT_OUTPUTCLR8_CLRn14_Pos 14 /*!< SCT OUTPUTCLR8: CLRn14 Position */ -#define SCT_OUTPUTCLR8_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn14_Pos) /*!< SCT OUTPUTCLR8: CLRn14 Mask */ -#define SCT_OUTPUTCLR8_CLRn15_Pos 15 /*!< SCT OUTPUTCLR8: CLRn15 Position */ -#define SCT_OUTPUTCLR8_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR8_CLRn15_Pos) /*!< SCT OUTPUTCLR8: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET9 ----------------------------------------- -#define SCT_OUTPUTSET9_SETn0_Pos 0 /*!< SCT OUTPUTSET9: SETn0 Position */ -#define SCT_OUTPUTSET9_SETn0_Msk (0x01UL << SCT_OUTPUTSET9_SETn0_Pos) /*!< SCT OUTPUTSET9: SETn0 Mask */ -#define SCT_OUTPUTSET9_SETn1_Pos 1 /*!< SCT OUTPUTSET9: SETn1 Position */ -#define SCT_OUTPUTSET9_SETn1_Msk (0x01UL << SCT_OUTPUTSET9_SETn1_Pos) /*!< SCT OUTPUTSET9: SETn1 Mask */ -#define SCT_OUTPUTSET9_SETn2_Pos 2 /*!< SCT OUTPUTSET9: SETn2 Position */ -#define SCT_OUTPUTSET9_SETn2_Msk (0x01UL << SCT_OUTPUTSET9_SETn2_Pos) /*!< SCT OUTPUTSET9: SETn2 Mask */ -#define SCT_OUTPUTSET9_SETn3_Pos 3 /*!< SCT OUTPUTSET9: SETn3 Position */ -#define SCT_OUTPUTSET9_SETn3_Msk (0x01UL << SCT_OUTPUTSET9_SETn3_Pos) /*!< SCT OUTPUTSET9: SETn3 Mask */ -#define SCT_OUTPUTSET9_SETn4_Pos 4 /*!< SCT OUTPUTSET9: SETn4 Position */ -#define SCT_OUTPUTSET9_SETn4_Msk (0x01UL << SCT_OUTPUTSET9_SETn4_Pos) /*!< SCT OUTPUTSET9: SETn4 Mask */ -#define SCT_OUTPUTSET9_SETn5_Pos 5 /*!< SCT OUTPUTSET9: SETn5 Position */ -#define SCT_OUTPUTSET9_SETn5_Msk (0x01UL << SCT_OUTPUTSET9_SETn5_Pos) /*!< SCT OUTPUTSET9: SETn5 Mask */ -#define SCT_OUTPUTSET9_SETn6_Pos 6 /*!< SCT OUTPUTSET9: SETn6 Position */ -#define SCT_OUTPUTSET9_SETn6_Msk (0x01UL << SCT_OUTPUTSET9_SETn6_Pos) /*!< SCT OUTPUTSET9: SETn6 Mask */ -#define SCT_OUTPUTSET9_SETn7_Pos 7 /*!< SCT OUTPUTSET9: SETn7 Position */ -#define SCT_OUTPUTSET9_SETn7_Msk (0x01UL << SCT_OUTPUTSET9_SETn7_Pos) /*!< SCT OUTPUTSET9: SETn7 Mask */ -#define SCT_OUTPUTSET9_SETn8_Pos 8 /*!< SCT OUTPUTSET9: SETn8 Position */ -#define SCT_OUTPUTSET9_SETn8_Msk (0x01UL << SCT_OUTPUTSET9_SETn8_Pos) /*!< SCT OUTPUTSET9: SETn8 Mask */ -#define SCT_OUTPUTSET9_SETn9_Pos 9 /*!< SCT OUTPUTSET9: SETn9 Position */ -#define SCT_OUTPUTSET9_SETn9_Msk (0x01UL << SCT_OUTPUTSET9_SETn9_Pos) /*!< SCT OUTPUTSET9: SETn9 Mask */ -#define SCT_OUTPUTSET9_SETn10_Pos 10 /*!< SCT OUTPUTSET9: SETn10 Position */ -#define SCT_OUTPUTSET9_SETn10_Msk (0x01UL << SCT_OUTPUTSET9_SETn10_Pos) /*!< SCT OUTPUTSET9: SETn10 Mask */ -#define SCT_OUTPUTSET9_SETn11_Pos 11 /*!< SCT OUTPUTSET9: SETn11 Position */ -#define SCT_OUTPUTSET9_SETn11_Msk (0x01UL << SCT_OUTPUTSET9_SETn11_Pos) /*!< SCT OUTPUTSET9: SETn11 Mask */ -#define SCT_OUTPUTSET9_SETn12_Pos 12 /*!< SCT OUTPUTSET9: SETn12 Position */ -#define SCT_OUTPUTSET9_SETn12_Msk (0x01UL << SCT_OUTPUTSET9_SETn12_Pos) /*!< SCT OUTPUTSET9: SETn12 Mask */ -#define SCT_OUTPUTSET9_SETn13_Pos 13 /*!< SCT OUTPUTSET9: SETn13 Position */ -#define SCT_OUTPUTSET9_SETn13_Msk (0x01UL << SCT_OUTPUTSET9_SETn13_Pos) /*!< SCT OUTPUTSET9: SETn13 Mask */ -#define SCT_OUTPUTSET9_SETn14_Pos 14 /*!< SCT OUTPUTSET9: SETn14 Position */ -#define SCT_OUTPUTSET9_SETn14_Msk (0x01UL << SCT_OUTPUTSET9_SETn14_Pos) /*!< SCT OUTPUTSET9: SETn14 Mask */ -#define SCT_OUTPUTSET9_SETn15_Pos 15 /*!< SCT OUTPUTSET9: SETn15 Position */ -#define SCT_OUTPUTSET9_SETn15_Msk (0x01UL << SCT_OUTPUTSET9_SETn15_Pos) /*!< SCT OUTPUTSET9: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR9 ----------------------------------------- -#define SCT_OUTPUTCLR9_CLRn0_Pos 0 /*!< SCT OUTPUTCLR9: CLRn0 Position */ -#define SCT_OUTPUTCLR9_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn0_Pos) /*!< SCT OUTPUTCLR9: CLRn0 Mask */ -#define SCT_OUTPUTCLR9_CLRn1_Pos 1 /*!< SCT OUTPUTCLR9: CLRn1 Position */ -#define SCT_OUTPUTCLR9_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn1_Pos) /*!< SCT OUTPUTCLR9: CLRn1 Mask */ -#define SCT_OUTPUTCLR9_CLRn2_Pos 2 /*!< SCT OUTPUTCLR9: CLRn2 Position */ -#define SCT_OUTPUTCLR9_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn2_Pos) /*!< SCT OUTPUTCLR9: CLRn2 Mask */ -#define SCT_OUTPUTCLR9_CLRn3_Pos 3 /*!< SCT OUTPUTCLR9: CLRn3 Position */ -#define SCT_OUTPUTCLR9_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn3_Pos) /*!< SCT OUTPUTCLR9: CLRn3 Mask */ -#define SCT_OUTPUTCLR9_CLRn4_Pos 4 /*!< SCT OUTPUTCLR9: CLRn4 Position */ -#define SCT_OUTPUTCLR9_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn4_Pos) /*!< SCT OUTPUTCLR9: CLRn4 Mask */ -#define SCT_OUTPUTCLR9_CLRn5_Pos 5 /*!< SCT OUTPUTCLR9: CLRn5 Position */ -#define SCT_OUTPUTCLR9_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn5_Pos) /*!< SCT OUTPUTCLR9: CLRn5 Mask */ -#define SCT_OUTPUTCLR9_CLRn6_Pos 6 /*!< SCT OUTPUTCLR9: CLRn6 Position */ -#define SCT_OUTPUTCLR9_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn6_Pos) /*!< SCT OUTPUTCLR9: CLRn6 Mask */ -#define SCT_OUTPUTCLR9_CLRn7_Pos 7 /*!< SCT OUTPUTCLR9: CLRn7 Position */ -#define SCT_OUTPUTCLR9_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn7_Pos) /*!< SCT OUTPUTCLR9: CLRn7 Mask */ -#define SCT_OUTPUTCLR9_CLRn8_Pos 8 /*!< SCT OUTPUTCLR9: CLRn8 Position */ -#define SCT_OUTPUTCLR9_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn8_Pos) /*!< SCT OUTPUTCLR9: CLRn8 Mask */ -#define SCT_OUTPUTCLR9_CLRn9_Pos 9 /*!< SCT OUTPUTCLR9: CLRn9 Position */ -#define SCT_OUTPUTCLR9_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn9_Pos) /*!< SCT OUTPUTCLR9: CLRn9 Mask */ -#define SCT_OUTPUTCLR9_CLRn10_Pos 10 /*!< SCT OUTPUTCLR9: CLRn10 Position */ -#define SCT_OUTPUTCLR9_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn10_Pos) /*!< SCT OUTPUTCLR9: CLRn10 Mask */ -#define SCT_OUTPUTCLR9_CLRn11_Pos 11 /*!< SCT OUTPUTCLR9: CLRn11 Position */ -#define SCT_OUTPUTCLR9_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn11_Pos) /*!< SCT OUTPUTCLR9: CLRn11 Mask */ -#define SCT_OUTPUTCLR9_CLRn12_Pos 12 /*!< SCT OUTPUTCLR9: CLRn12 Position */ -#define SCT_OUTPUTCLR9_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn12_Pos) /*!< SCT OUTPUTCLR9: CLRn12 Mask */ -#define SCT_OUTPUTCLR9_CLRn13_Pos 13 /*!< SCT OUTPUTCLR9: CLRn13 Position */ -#define SCT_OUTPUTCLR9_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn13_Pos) /*!< SCT OUTPUTCLR9: CLRn13 Mask */ -#define SCT_OUTPUTCLR9_CLRn14_Pos 14 /*!< SCT OUTPUTCLR9: CLRn14 Position */ -#define SCT_OUTPUTCLR9_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn14_Pos) /*!< SCT OUTPUTCLR9: CLRn14 Mask */ -#define SCT_OUTPUTCLR9_CLRn15_Pos 15 /*!< SCT OUTPUTCLR9: CLRn15 Position */ -#define SCT_OUTPUTCLR9_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR9_CLRn15_Pos) /*!< SCT OUTPUTCLR9: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET10 ---------------------------------------- -#define SCT_OUTPUTSET10_SETn0_Pos 0 /*!< SCT OUTPUTSET10: SETn0 Position */ -#define SCT_OUTPUTSET10_SETn0_Msk (0x01UL << SCT_OUTPUTSET10_SETn0_Pos) /*!< SCT OUTPUTSET10: SETn0 Mask */ -#define SCT_OUTPUTSET10_SETn1_Pos 1 /*!< SCT OUTPUTSET10: SETn1 Position */ -#define SCT_OUTPUTSET10_SETn1_Msk (0x01UL << SCT_OUTPUTSET10_SETn1_Pos) /*!< SCT OUTPUTSET10: SETn1 Mask */ -#define SCT_OUTPUTSET10_SETn2_Pos 2 /*!< SCT OUTPUTSET10: SETn2 Position */ -#define SCT_OUTPUTSET10_SETn2_Msk (0x01UL << SCT_OUTPUTSET10_SETn2_Pos) /*!< SCT OUTPUTSET10: SETn2 Mask */ -#define SCT_OUTPUTSET10_SETn3_Pos 3 /*!< SCT OUTPUTSET10: SETn3 Position */ -#define SCT_OUTPUTSET10_SETn3_Msk (0x01UL << SCT_OUTPUTSET10_SETn3_Pos) /*!< SCT OUTPUTSET10: SETn3 Mask */ -#define SCT_OUTPUTSET10_SETn4_Pos 4 /*!< SCT OUTPUTSET10: SETn4 Position */ -#define SCT_OUTPUTSET10_SETn4_Msk (0x01UL << SCT_OUTPUTSET10_SETn4_Pos) /*!< SCT OUTPUTSET10: SETn4 Mask */ -#define SCT_OUTPUTSET10_SETn5_Pos 5 /*!< SCT OUTPUTSET10: SETn5 Position */ -#define SCT_OUTPUTSET10_SETn5_Msk (0x01UL << SCT_OUTPUTSET10_SETn5_Pos) /*!< SCT OUTPUTSET10: SETn5 Mask */ -#define SCT_OUTPUTSET10_SETn6_Pos 6 /*!< SCT OUTPUTSET10: SETn6 Position */ -#define SCT_OUTPUTSET10_SETn6_Msk (0x01UL << SCT_OUTPUTSET10_SETn6_Pos) /*!< SCT OUTPUTSET10: SETn6 Mask */ -#define SCT_OUTPUTSET10_SETn7_Pos 7 /*!< SCT OUTPUTSET10: SETn7 Position */ -#define SCT_OUTPUTSET10_SETn7_Msk (0x01UL << SCT_OUTPUTSET10_SETn7_Pos) /*!< SCT OUTPUTSET10: SETn7 Mask */ -#define SCT_OUTPUTSET10_SETn8_Pos 8 /*!< SCT OUTPUTSET10: SETn8 Position */ -#define SCT_OUTPUTSET10_SETn8_Msk (0x01UL << SCT_OUTPUTSET10_SETn8_Pos) /*!< SCT OUTPUTSET10: SETn8 Mask */ -#define SCT_OUTPUTSET10_SETn9_Pos 9 /*!< SCT OUTPUTSET10: SETn9 Position */ -#define SCT_OUTPUTSET10_SETn9_Msk (0x01UL << SCT_OUTPUTSET10_SETn9_Pos) /*!< SCT OUTPUTSET10: SETn9 Mask */ -#define SCT_OUTPUTSET10_SETn10_Pos 10 /*!< SCT OUTPUTSET10: SETn10 Position */ -#define SCT_OUTPUTSET10_SETn10_Msk (0x01UL << SCT_OUTPUTSET10_SETn10_Pos) /*!< SCT OUTPUTSET10: SETn10 Mask */ -#define SCT_OUTPUTSET10_SETn11_Pos 11 /*!< SCT OUTPUTSET10: SETn11 Position */ -#define SCT_OUTPUTSET10_SETn11_Msk (0x01UL << SCT_OUTPUTSET10_SETn11_Pos) /*!< SCT OUTPUTSET10: SETn11 Mask */ -#define SCT_OUTPUTSET10_SETn12_Pos 12 /*!< SCT OUTPUTSET10: SETn12 Position */ -#define SCT_OUTPUTSET10_SETn12_Msk (0x01UL << SCT_OUTPUTSET10_SETn12_Pos) /*!< SCT OUTPUTSET10: SETn12 Mask */ -#define SCT_OUTPUTSET10_SETn13_Pos 13 /*!< SCT OUTPUTSET10: SETn13 Position */ -#define SCT_OUTPUTSET10_SETn13_Msk (0x01UL << SCT_OUTPUTSET10_SETn13_Pos) /*!< SCT OUTPUTSET10: SETn13 Mask */ -#define SCT_OUTPUTSET10_SETn14_Pos 14 /*!< SCT OUTPUTSET10: SETn14 Position */ -#define SCT_OUTPUTSET10_SETn14_Msk (0x01UL << SCT_OUTPUTSET10_SETn14_Pos) /*!< SCT OUTPUTSET10: SETn14 Mask */ -#define SCT_OUTPUTSET10_SETn15_Pos 15 /*!< SCT OUTPUTSET10: SETn15 Position */ -#define SCT_OUTPUTSET10_SETn15_Msk (0x01UL << SCT_OUTPUTSET10_SETn15_Pos) /*!< SCT OUTPUTSET10: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR10 ---------------------------------------- -#define SCT_OUTPUTCLR10_CLRn0_Pos 0 /*!< SCT OUTPUTCLR10: CLRn0 Position */ -#define SCT_OUTPUTCLR10_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn0_Pos) /*!< SCT OUTPUTCLR10: CLRn0 Mask */ -#define SCT_OUTPUTCLR10_CLRn1_Pos 1 /*!< SCT OUTPUTCLR10: CLRn1 Position */ -#define SCT_OUTPUTCLR10_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn1_Pos) /*!< SCT OUTPUTCLR10: CLRn1 Mask */ -#define SCT_OUTPUTCLR10_CLRn2_Pos 2 /*!< SCT OUTPUTCLR10: CLRn2 Position */ -#define SCT_OUTPUTCLR10_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn2_Pos) /*!< SCT OUTPUTCLR10: CLRn2 Mask */ -#define SCT_OUTPUTCLR10_CLRn3_Pos 3 /*!< SCT OUTPUTCLR10: CLRn3 Position */ -#define SCT_OUTPUTCLR10_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn3_Pos) /*!< SCT OUTPUTCLR10: CLRn3 Mask */ -#define SCT_OUTPUTCLR10_CLRn4_Pos 4 /*!< SCT OUTPUTCLR10: CLRn4 Position */ -#define SCT_OUTPUTCLR10_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn4_Pos) /*!< SCT OUTPUTCLR10: CLRn4 Mask */ -#define SCT_OUTPUTCLR10_CLRn5_Pos 5 /*!< SCT OUTPUTCLR10: CLRn5 Position */ -#define SCT_OUTPUTCLR10_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn5_Pos) /*!< SCT OUTPUTCLR10: CLRn5 Mask */ -#define SCT_OUTPUTCLR10_CLRn6_Pos 6 /*!< SCT OUTPUTCLR10: CLRn6 Position */ -#define SCT_OUTPUTCLR10_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn6_Pos) /*!< SCT OUTPUTCLR10: CLRn6 Mask */ -#define SCT_OUTPUTCLR10_CLRn7_Pos 7 /*!< SCT OUTPUTCLR10: CLRn7 Position */ -#define SCT_OUTPUTCLR10_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn7_Pos) /*!< SCT OUTPUTCLR10: CLRn7 Mask */ -#define SCT_OUTPUTCLR10_CLRn8_Pos 8 /*!< SCT OUTPUTCLR10: CLRn8 Position */ -#define SCT_OUTPUTCLR10_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn8_Pos) /*!< SCT OUTPUTCLR10: CLRn8 Mask */ -#define SCT_OUTPUTCLR10_CLRn9_Pos 9 /*!< SCT OUTPUTCLR10: CLRn9 Position */ -#define SCT_OUTPUTCLR10_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn9_Pos) /*!< SCT OUTPUTCLR10: CLRn9 Mask */ -#define SCT_OUTPUTCLR10_CLRn10_Pos 10 /*!< SCT OUTPUTCLR10: CLRn10 Position */ -#define SCT_OUTPUTCLR10_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn10_Pos) /*!< SCT OUTPUTCLR10: CLRn10 Mask */ -#define SCT_OUTPUTCLR10_CLRn11_Pos 11 /*!< SCT OUTPUTCLR10: CLRn11 Position */ -#define SCT_OUTPUTCLR10_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn11_Pos) /*!< SCT OUTPUTCLR10: CLRn11 Mask */ -#define SCT_OUTPUTCLR10_CLRn12_Pos 12 /*!< SCT OUTPUTCLR10: CLRn12 Position */ -#define SCT_OUTPUTCLR10_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn12_Pos) /*!< SCT OUTPUTCLR10: CLRn12 Mask */ -#define SCT_OUTPUTCLR10_CLRn13_Pos 13 /*!< SCT OUTPUTCLR10: CLRn13 Position */ -#define SCT_OUTPUTCLR10_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn13_Pos) /*!< SCT OUTPUTCLR10: CLRn13 Mask */ -#define SCT_OUTPUTCLR10_CLRn14_Pos 14 /*!< SCT OUTPUTCLR10: CLRn14 Position */ -#define SCT_OUTPUTCLR10_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn14_Pos) /*!< SCT OUTPUTCLR10: CLRn14 Mask */ -#define SCT_OUTPUTCLR10_CLRn15_Pos 15 /*!< SCT OUTPUTCLR10: CLRn15 Position */ -#define SCT_OUTPUTCLR10_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR10_CLRn15_Pos) /*!< SCT OUTPUTCLR10: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET11 ---------------------------------------- -#define SCT_OUTPUTSET11_SETn0_Pos 0 /*!< SCT OUTPUTSET11: SETn0 Position */ -#define SCT_OUTPUTSET11_SETn0_Msk (0x01UL << SCT_OUTPUTSET11_SETn0_Pos) /*!< SCT OUTPUTSET11: SETn0 Mask */ -#define SCT_OUTPUTSET11_SETn1_Pos 1 /*!< SCT OUTPUTSET11: SETn1 Position */ -#define SCT_OUTPUTSET11_SETn1_Msk (0x01UL << SCT_OUTPUTSET11_SETn1_Pos) /*!< SCT OUTPUTSET11: SETn1 Mask */ -#define SCT_OUTPUTSET11_SETn2_Pos 2 /*!< SCT OUTPUTSET11: SETn2 Position */ -#define SCT_OUTPUTSET11_SETn2_Msk (0x01UL << SCT_OUTPUTSET11_SETn2_Pos) /*!< SCT OUTPUTSET11: SETn2 Mask */ -#define SCT_OUTPUTSET11_SETn3_Pos 3 /*!< SCT OUTPUTSET11: SETn3 Position */ -#define SCT_OUTPUTSET11_SETn3_Msk (0x01UL << SCT_OUTPUTSET11_SETn3_Pos) /*!< SCT OUTPUTSET11: SETn3 Mask */ -#define SCT_OUTPUTSET11_SETn4_Pos 4 /*!< SCT OUTPUTSET11: SETn4 Position */ -#define SCT_OUTPUTSET11_SETn4_Msk (0x01UL << SCT_OUTPUTSET11_SETn4_Pos) /*!< SCT OUTPUTSET11: SETn4 Mask */ -#define SCT_OUTPUTSET11_SETn5_Pos 5 /*!< SCT OUTPUTSET11: SETn5 Position */ -#define SCT_OUTPUTSET11_SETn5_Msk (0x01UL << SCT_OUTPUTSET11_SETn5_Pos) /*!< SCT OUTPUTSET11: SETn5 Mask */ -#define SCT_OUTPUTSET11_SETn6_Pos 6 /*!< SCT OUTPUTSET11: SETn6 Position */ -#define SCT_OUTPUTSET11_SETn6_Msk (0x01UL << SCT_OUTPUTSET11_SETn6_Pos) /*!< SCT OUTPUTSET11: SETn6 Mask */ -#define SCT_OUTPUTSET11_SETn7_Pos 7 /*!< SCT OUTPUTSET11: SETn7 Position */ -#define SCT_OUTPUTSET11_SETn7_Msk (0x01UL << SCT_OUTPUTSET11_SETn7_Pos) /*!< SCT OUTPUTSET11: SETn7 Mask */ -#define SCT_OUTPUTSET11_SETn8_Pos 8 /*!< SCT OUTPUTSET11: SETn8 Position */ -#define SCT_OUTPUTSET11_SETn8_Msk (0x01UL << SCT_OUTPUTSET11_SETn8_Pos) /*!< SCT OUTPUTSET11: SETn8 Mask */ -#define SCT_OUTPUTSET11_SETn9_Pos 9 /*!< SCT OUTPUTSET11: SETn9 Position */ -#define SCT_OUTPUTSET11_SETn9_Msk (0x01UL << SCT_OUTPUTSET11_SETn9_Pos) /*!< SCT OUTPUTSET11: SETn9 Mask */ -#define SCT_OUTPUTSET11_SETn10_Pos 10 /*!< SCT OUTPUTSET11: SETn10 Position */ -#define SCT_OUTPUTSET11_SETn10_Msk (0x01UL << SCT_OUTPUTSET11_SETn10_Pos) /*!< SCT OUTPUTSET11: SETn10 Mask */ -#define SCT_OUTPUTSET11_SETn11_Pos 11 /*!< SCT OUTPUTSET11: SETn11 Position */ -#define SCT_OUTPUTSET11_SETn11_Msk (0x01UL << SCT_OUTPUTSET11_SETn11_Pos) /*!< SCT OUTPUTSET11: SETn11 Mask */ -#define SCT_OUTPUTSET11_SETn12_Pos 12 /*!< SCT OUTPUTSET11: SETn12 Position */ -#define SCT_OUTPUTSET11_SETn12_Msk (0x01UL << SCT_OUTPUTSET11_SETn12_Pos) /*!< SCT OUTPUTSET11: SETn12 Mask */ -#define SCT_OUTPUTSET11_SETn13_Pos 13 /*!< SCT OUTPUTSET11: SETn13 Position */ -#define SCT_OUTPUTSET11_SETn13_Msk (0x01UL << SCT_OUTPUTSET11_SETn13_Pos) /*!< SCT OUTPUTSET11: SETn13 Mask */ -#define SCT_OUTPUTSET11_SETn14_Pos 14 /*!< SCT OUTPUTSET11: SETn14 Position */ -#define SCT_OUTPUTSET11_SETn14_Msk (0x01UL << SCT_OUTPUTSET11_SETn14_Pos) /*!< SCT OUTPUTSET11: SETn14 Mask */ -#define SCT_OUTPUTSET11_SETn15_Pos 15 /*!< SCT OUTPUTSET11: SETn15 Position */ -#define SCT_OUTPUTSET11_SETn15_Msk (0x01UL << SCT_OUTPUTSET11_SETn15_Pos) /*!< SCT OUTPUTSET11: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR11 ---------------------------------------- -#define SCT_OUTPUTCLR11_CLRn0_Pos 0 /*!< SCT OUTPUTCLR11: CLRn0 Position */ -#define SCT_OUTPUTCLR11_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn0_Pos) /*!< SCT OUTPUTCLR11: CLRn0 Mask */ -#define SCT_OUTPUTCLR11_CLRn1_Pos 1 /*!< SCT OUTPUTCLR11: CLRn1 Position */ -#define SCT_OUTPUTCLR11_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn1_Pos) /*!< SCT OUTPUTCLR11: CLRn1 Mask */ -#define SCT_OUTPUTCLR11_CLRn2_Pos 2 /*!< SCT OUTPUTCLR11: CLRn2 Position */ -#define SCT_OUTPUTCLR11_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn2_Pos) /*!< SCT OUTPUTCLR11: CLRn2 Mask */ -#define SCT_OUTPUTCLR11_CLRn3_Pos 3 /*!< SCT OUTPUTCLR11: CLRn3 Position */ -#define SCT_OUTPUTCLR11_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn3_Pos) /*!< SCT OUTPUTCLR11: CLRn3 Mask */ -#define SCT_OUTPUTCLR11_CLRn4_Pos 4 /*!< SCT OUTPUTCLR11: CLRn4 Position */ -#define SCT_OUTPUTCLR11_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn4_Pos) /*!< SCT OUTPUTCLR11: CLRn4 Mask */ -#define SCT_OUTPUTCLR11_CLRn5_Pos 5 /*!< SCT OUTPUTCLR11: CLRn5 Position */ -#define SCT_OUTPUTCLR11_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn5_Pos) /*!< SCT OUTPUTCLR11: CLRn5 Mask */ -#define SCT_OUTPUTCLR11_CLRn6_Pos 6 /*!< SCT OUTPUTCLR11: CLRn6 Position */ -#define SCT_OUTPUTCLR11_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn6_Pos) /*!< SCT OUTPUTCLR11: CLRn6 Mask */ -#define SCT_OUTPUTCLR11_CLRn7_Pos 7 /*!< SCT OUTPUTCLR11: CLRn7 Position */ -#define SCT_OUTPUTCLR11_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn7_Pos) /*!< SCT OUTPUTCLR11: CLRn7 Mask */ -#define SCT_OUTPUTCLR11_CLRn8_Pos 8 /*!< SCT OUTPUTCLR11: CLRn8 Position */ -#define SCT_OUTPUTCLR11_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn8_Pos) /*!< SCT OUTPUTCLR11: CLRn8 Mask */ -#define SCT_OUTPUTCLR11_CLRn9_Pos 9 /*!< SCT OUTPUTCLR11: CLRn9 Position */ -#define SCT_OUTPUTCLR11_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn9_Pos) /*!< SCT OUTPUTCLR11: CLRn9 Mask */ -#define SCT_OUTPUTCLR11_CLRn10_Pos 10 /*!< SCT OUTPUTCLR11: CLRn10 Position */ -#define SCT_OUTPUTCLR11_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn10_Pos) /*!< SCT OUTPUTCLR11: CLRn10 Mask */ -#define SCT_OUTPUTCLR11_CLRn11_Pos 11 /*!< SCT OUTPUTCLR11: CLRn11 Position */ -#define SCT_OUTPUTCLR11_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn11_Pos) /*!< SCT OUTPUTCLR11: CLRn11 Mask */ -#define SCT_OUTPUTCLR11_CLRn12_Pos 12 /*!< SCT OUTPUTCLR11: CLRn12 Position */ -#define SCT_OUTPUTCLR11_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn12_Pos) /*!< SCT OUTPUTCLR11: CLRn12 Mask */ -#define SCT_OUTPUTCLR11_CLRn13_Pos 13 /*!< SCT OUTPUTCLR11: CLRn13 Position */ -#define SCT_OUTPUTCLR11_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn13_Pos) /*!< SCT OUTPUTCLR11: CLRn13 Mask */ -#define SCT_OUTPUTCLR11_CLRn14_Pos 14 /*!< SCT OUTPUTCLR11: CLRn14 Position */ -#define SCT_OUTPUTCLR11_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn14_Pos) /*!< SCT OUTPUTCLR11: CLRn14 Mask */ -#define SCT_OUTPUTCLR11_CLRn15_Pos 15 /*!< SCT OUTPUTCLR11: CLRn15 Position */ -#define SCT_OUTPUTCLR11_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR11_CLRn15_Pos) /*!< SCT OUTPUTCLR11: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET12 ---------------------------------------- -#define SCT_OUTPUTSET12_SETn0_Pos 0 /*!< SCT OUTPUTSET12: SETn0 Position */ -#define SCT_OUTPUTSET12_SETn0_Msk (0x01UL << SCT_OUTPUTSET12_SETn0_Pos) /*!< SCT OUTPUTSET12: SETn0 Mask */ -#define SCT_OUTPUTSET12_SETn1_Pos 1 /*!< SCT OUTPUTSET12: SETn1 Position */ -#define SCT_OUTPUTSET12_SETn1_Msk (0x01UL << SCT_OUTPUTSET12_SETn1_Pos) /*!< SCT OUTPUTSET12: SETn1 Mask */ -#define SCT_OUTPUTSET12_SETn2_Pos 2 /*!< SCT OUTPUTSET12: SETn2 Position */ -#define SCT_OUTPUTSET12_SETn2_Msk (0x01UL << SCT_OUTPUTSET12_SETn2_Pos) /*!< SCT OUTPUTSET12: SETn2 Mask */ -#define SCT_OUTPUTSET12_SETn3_Pos 3 /*!< SCT OUTPUTSET12: SETn3 Position */ -#define SCT_OUTPUTSET12_SETn3_Msk (0x01UL << SCT_OUTPUTSET12_SETn3_Pos) /*!< SCT OUTPUTSET12: SETn3 Mask */ -#define SCT_OUTPUTSET12_SETn4_Pos 4 /*!< SCT OUTPUTSET12: SETn4 Position */ -#define SCT_OUTPUTSET12_SETn4_Msk (0x01UL << SCT_OUTPUTSET12_SETn4_Pos) /*!< SCT OUTPUTSET12: SETn4 Mask */ -#define SCT_OUTPUTSET12_SETn5_Pos 5 /*!< SCT OUTPUTSET12: SETn5 Position */ -#define SCT_OUTPUTSET12_SETn5_Msk (0x01UL << SCT_OUTPUTSET12_SETn5_Pos) /*!< SCT OUTPUTSET12: SETn5 Mask */ -#define SCT_OUTPUTSET12_SETn6_Pos 6 /*!< SCT OUTPUTSET12: SETn6 Position */ -#define SCT_OUTPUTSET12_SETn6_Msk (0x01UL << SCT_OUTPUTSET12_SETn6_Pos) /*!< SCT OUTPUTSET12: SETn6 Mask */ -#define SCT_OUTPUTSET12_SETn7_Pos 7 /*!< SCT OUTPUTSET12: SETn7 Position */ -#define SCT_OUTPUTSET12_SETn7_Msk (0x01UL << SCT_OUTPUTSET12_SETn7_Pos) /*!< SCT OUTPUTSET12: SETn7 Mask */ -#define SCT_OUTPUTSET12_SETn8_Pos 8 /*!< SCT OUTPUTSET12: SETn8 Position */ -#define SCT_OUTPUTSET12_SETn8_Msk (0x01UL << SCT_OUTPUTSET12_SETn8_Pos) /*!< SCT OUTPUTSET12: SETn8 Mask */ -#define SCT_OUTPUTSET12_SETn9_Pos 9 /*!< SCT OUTPUTSET12: SETn9 Position */ -#define SCT_OUTPUTSET12_SETn9_Msk (0x01UL << SCT_OUTPUTSET12_SETn9_Pos) /*!< SCT OUTPUTSET12: SETn9 Mask */ -#define SCT_OUTPUTSET12_SETn10_Pos 10 /*!< SCT OUTPUTSET12: SETn10 Position */ -#define SCT_OUTPUTSET12_SETn10_Msk (0x01UL << SCT_OUTPUTSET12_SETn10_Pos) /*!< SCT OUTPUTSET12: SETn10 Mask */ -#define SCT_OUTPUTSET12_SETn11_Pos 11 /*!< SCT OUTPUTSET12: SETn11 Position */ -#define SCT_OUTPUTSET12_SETn11_Msk (0x01UL << SCT_OUTPUTSET12_SETn11_Pos) /*!< SCT OUTPUTSET12: SETn11 Mask */ -#define SCT_OUTPUTSET12_SETn12_Pos 12 /*!< SCT OUTPUTSET12: SETn12 Position */ -#define SCT_OUTPUTSET12_SETn12_Msk (0x01UL << SCT_OUTPUTSET12_SETn12_Pos) /*!< SCT OUTPUTSET12: SETn12 Mask */ -#define SCT_OUTPUTSET12_SETn13_Pos 13 /*!< SCT OUTPUTSET12: SETn13 Position */ -#define SCT_OUTPUTSET12_SETn13_Msk (0x01UL << SCT_OUTPUTSET12_SETn13_Pos) /*!< SCT OUTPUTSET12: SETn13 Mask */ -#define SCT_OUTPUTSET12_SETn14_Pos 14 /*!< SCT OUTPUTSET12: SETn14 Position */ -#define SCT_OUTPUTSET12_SETn14_Msk (0x01UL << SCT_OUTPUTSET12_SETn14_Pos) /*!< SCT OUTPUTSET12: SETn14 Mask */ -#define SCT_OUTPUTSET12_SETn15_Pos 15 /*!< SCT OUTPUTSET12: SETn15 Position */ -#define SCT_OUTPUTSET12_SETn15_Msk (0x01UL << SCT_OUTPUTSET12_SETn15_Pos) /*!< SCT OUTPUTSET12: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR12 ---------------------------------------- -#define SCT_OUTPUTCLR12_CLRn0_Pos 0 /*!< SCT OUTPUTCLR12: CLRn0 Position */ -#define SCT_OUTPUTCLR12_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn0_Pos) /*!< SCT OUTPUTCLR12: CLRn0 Mask */ -#define SCT_OUTPUTCLR12_CLRn1_Pos 1 /*!< SCT OUTPUTCLR12: CLRn1 Position */ -#define SCT_OUTPUTCLR12_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn1_Pos) /*!< SCT OUTPUTCLR12: CLRn1 Mask */ -#define SCT_OUTPUTCLR12_CLRn2_Pos 2 /*!< SCT OUTPUTCLR12: CLRn2 Position */ -#define SCT_OUTPUTCLR12_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn2_Pos) /*!< SCT OUTPUTCLR12: CLRn2 Mask */ -#define SCT_OUTPUTCLR12_CLRn3_Pos 3 /*!< SCT OUTPUTCLR12: CLRn3 Position */ -#define SCT_OUTPUTCLR12_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn3_Pos) /*!< SCT OUTPUTCLR12: CLRn3 Mask */ -#define SCT_OUTPUTCLR12_CLRn4_Pos 4 /*!< SCT OUTPUTCLR12: CLRn4 Position */ -#define SCT_OUTPUTCLR12_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn4_Pos) /*!< SCT OUTPUTCLR12: CLRn4 Mask */ -#define SCT_OUTPUTCLR12_CLRn5_Pos 5 /*!< SCT OUTPUTCLR12: CLRn5 Position */ -#define SCT_OUTPUTCLR12_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn5_Pos) /*!< SCT OUTPUTCLR12: CLRn5 Mask */ -#define SCT_OUTPUTCLR12_CLRn6_Pos 6 /*!< SCT OUTPUTCLR12: CLRn6 Position */ -#define SCT_OUTPUTCLR12_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn6_Pos) /*!< SCT OUTPUTCLR12: CLRn6 Mask */ -#define SCT_OUTPUTCLR12_CLRn7_Pos 7 /*!< SCT OUTPUTCLR12: CLRn7 Position */ -#define SCT_OUTPUTCLR12_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn7_Pos) /*!< SCT OUTPUTCLR12: CLRn7 Mask */ -#define SCT_OUTPUTCLR12_CLRn8_Pos 8 /*!< SCT OUTPUTCLR12: CLRn8 Position */ -#define SCT_OUTPUTCLR12_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn8_Pos) /*!< SCT OUTPUTCLR12: CLRn8 Mask */ -#define SCT_OUTPUTCLR12_CLRn9_Pos 9 /*!< SCT OUTPUTCLR12: CLRn9 Position */ -#define SCT_OUTPUTCLR12_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn9_Pos) /*!< SCT OUTPUTCLR12: CLRn9 Mask */ -#define SCT_OUTPUTCLR12_CLRn10_Pos 10 /*!< SCT OUTPUTCLR12: CLRn10 Position */ -#define SCT_OUTPUTCLR12_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn10_Pos) /*!< SCT OUTPUTCLR12: CLRn10 Mask */ -#define SCT_OUTPUTCLR12_CLRn11_Pos 11 /*!< SCT OUTPUTCLR12: CLRn11 Position */ -#define SCT_OUTPUTCLR12_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn11_Pos) /*!< SCT OUTPUTCLR12: CLRn11 Mask */ -#define SCT_OUTPUTCLR12_CLRn12_Pos 12 /*!< SCT OUTPUTCLR12: CLRn12 Position */ -#define SCT_OUTPUTCLR12_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn12_Pos) /*!< SCT OUTPUTCLR12: CLRn12 Mask */ -#define SCT_OUTPUTCLR12_CLRn13_Pos 13 /*!< SCT OUTPUTCLR12: CLRn13 Position */ -#define SCT_OUTPUTCLR12_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn13_Pos) /*!< SCT OUTPUTCLR12: CLRn13 Mask */ -#define SCT_OUTPUTCLR12_CLRn14_Pos 14 /*!< SCT OUTPUTCLR12: CLRn14 Position */ -#define SCT_OUTPUTCLR12_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn14_Pos) /*!< SCT OUTPUTCLR12: CLRn14 Mask */ -#define SCT_OUTPUTCLR12_CLRn15_Pos 15 /*!< SCT OUTPUTCLR12: CLRn15 Position */ -#define SCT_OUTPUTCLR12_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR12_CLRn15_Pos) /*!< SCT OUTPUTCLR12: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET13 ---------------------------------------- -#define SCT_OUTPUTSET13_SETn0_Pos 0 /*!< SCT OUTPUTSET13: SETn0 Position */ -#define SCT_OUTPUTSET13_SETn0_Msk (0x01UL << SCT_OUTPUTSET13_SETn0_Pos) /*!< SCT OUTPUTSET13: SETn0 Mask */ -#define SCT_OUTPUTSET13_SETn1_Pos 1 /*!< SCT OUTPUTSET13: SETn1 Position */ -#define SCT_OUTPUTSET13_SETn1_Msk (0x01UL << SCT_OUTPUTSET13_SETn1_Pos) /*!< SCT OUTPUTSET13: SETn1 Mask */ -#define SCT_OUTPUTSET13_SETn2_Pos 2 /*!< SCT OUTPUTSET13: SETn2 Position */ -#define SCT_OUTPUTSET13_SETn2_Msk (0x01UL << SCT_OUTPUTSET13_SETn2_Pos) /*!< SCT OUTPUTSET13: SETn2 Mask */ -#define SCT_OUTPUTSET13_SETn3_Pos 3 /*!< SCT OUTPUTSET13: SETn3 Position */ -#define SCT_OUTPUTSET13_SETn3_Msk (0x01UL << SCT_OUTPUTSET13_SETn3_Pos) /*!< SCT OUTPUTSET13: SETn3 Mask */ -#define SCT_OUTPUTSET13_SETn4_Pos 4 /*!< SCT OUTPUTSET13: SETn4 Position */ -#define SCT_OUTPUTSET13_SETn4_Msk (0x01UL << SCT_OUTPUTSET13_SETn4_Pos) /*!< SCT OUTPUTSET13: SETn4 Mask */ -#define SCT_OUTPUTSET13_SETn5_Pos 5 /*!< SCT OUTPUTSET13: SETn5 Position */ -#define SCT_OUTPUTSET13_SETn5_Msk (0x01UL << SCT_OUTPUTSET13_SETn5_Pos) /*!< SCT OUTPUTSET13: SETn5 Mask */ -#define SCT_OUTPUTSET13_SETn6_Pos 6 /*!< SCT OUTPUTSET13: SETn6 Position */ -#define SCT_OUTPUTSET13_SETn6_Msk (0x01UL << SCT_OUTPUTSET13_SETn6_Pos) /*!< SCT OUTPUTSET13: SETn6 Mask */ -#define SCT_OUTPUTSET13_SETn7_Pos 7 /*!< SCT OUTPUTSET13: SETn7 Position */ -#define SCT_OUTPUTSET13_SETn7_Msk (0x01UL << SCT_OUTPUTSET13_SETn7_Pos) /*!< SCT OUTPUTSET13: SETn7 Mask */ -#define SCT_OUTPUTSET13_SETn8_Pos 8 /*!< SCT OUTPUTSET13: SETn8 Position */ -#define SCT_OUTPUTSET13_SETn8_Msk (0x01UL << SCT_OUTPUTSET13_SETn8_Pos) /*!< SCT OUTPUTSET13: SETn8 Mask */ -#define SCT_OUTPUTSET13_SETn9_Pos 9 /*!< SCT OUTPUTSET13: SETn9 Position */ -#define SCT_OUTPUTSET13_SETn9_Msk (0x01UL << SCT_OUTPUTSET13_SETn9_Pos) /*!< SCT OUTPUTSET13: SETn9 Mask */ -#define SCT_OUTPUTSET13_SETn10_Pos 10 /*!< SCT OUTPUTSET13: SETn10 Position */ -#define SCT_OUTPUTSET13_SETn10_Msk (0x01UL << SCT_OUTPUTSET13_SETn10_Pos) /*!< SCT OUTPUTSET13: SETn10 Mask */ -#define SCT_OUTPUTSET13_SETn11_Pos 11 /*!< SCT OUTPUTSET13: SETn11 Position */ -#define SCT_OUTPUTSET13_SETn11_Msk (0x01UL << SCT_OUTPUTSET13_SETn11_Pos) /*!< SCT OUTPUTSET13: SETn11 Mask */ -#define SCT_OUTPUTSET13_SETn12_Pos 12 /*!< SCT OUTPUTSET13: SETn12 Position */ -#define SCT_OUTPUTSET13_SETn12_Msk (0x01UL << SCT_OUTPUTSET13_SETn12_Pos) /*!< SCT OUTPUTSET13: SETn12 Mask */ -#define SCT_OUTPUTSET13_SETn13_Pos 13 /*!< SCT OUTPUTSET13: SETn13 Position */ -#define SCT_OUTPUTSET13_SETn13_Msk (0x01UL << SCT_OUTPUTSET13_SETn13_Pos) /*!< SCT OUTPUTSET13: SETn13 Mask */ -#define SCT_OUTPUTSET13_SETn14_Pos 14 /*!< SCT OUTPUTSET13: SETn14 Position */ -#define SCT_OUTPUTSET13_SETn14_Msk (0x01UL << SCT_OUTPUTSET13_SETn14_Pos) /*!< SCT OUTPUTSET13: SETn14 Mask */ -#define SCT_OUTPUTSET13_SETn15_Pos 15 /*!< SCT OUTPUTSET13: SETn15 Position */ -#define SCT_OUTPUTSET13_SETn15_Msk (0x01UL << SCT_OUTPUTSET13_SETn15_Pos) /*!< SCT OUTPUTSET13: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR13 ---------------------------------------- -#define SCT_OUTPUTCLR13_CLRn0_Pos 0 /*!< SCT OUTPUTCLR13: CLRn0 Position */ -#define SCT_OUTPUTCLR13_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn0_Pos) /*!< SCT OUTPUTCLR13: CLRn0 Mask */ -#define SCT_OUTPUTCLR13_CLRn1_Pos 1 /*!< SCT OUTPUTCLR13: CLRn1 Position */ -#define SCT_OUTPUTCLR13_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn1_Pos) /*!< SCT OUTPUTCLR13: CLRn1 Mask */ -#define SCT_OUTPUTCLR13_CLRn2_Pos 2 /*!< SCT OUTPUTCLR13: CLRn2 Position */ -#define SCT_OUTPUTCLR13_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn2_Pos) /*!< SCT OUTPUTCLR13: CLRn2 Mask */ -#define SCT_OUTPUTCLR13_CLRn3_Pos 3 /*!< SCT OUTPUTCLR13: CLRn3 Position */ -#define SCT_OUTPUTCLR13_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn3_Pos) /*!< SCT OUTPUTCLR13: CLRn3 Mask */ -#define SCT_OUTPUTCLR13_CLRn4_Pos 4 /*!< SCT OUTPUTCLR13: CLRn4 Position */ -#define SCT_OUTPUTCLR13_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn4_Pos) /*!< SCT OUTPUTCLR13: CLRn4 Mask */ -#define SCT_OUTPUTCLR13_CLRn5_Pos 5 /*!< SCT OUTPUTCLR13: CLRn5 Position */ -#define SCT_OUTPUTCLR13_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn5_Pos) /*!< SCT OUTPUTCLR13: CLRn5 Mask */ -#define SCT_OUTPUTCLR13_CLRn6_Pos 6 /*!< SCT OUTPUTCLR13: CLRn6 Position */ -#define SCT_OUTPUTCLR13_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn6_Pos) /*!< SCT OUTPUTCLR13: CLRn6 Mask */ -#define SCT_OUTPUTCLR13_CLRn7_Pos 7 /*!< SCT OUTPUTCLR13: CLRn7 Position */ -#define SCT_OUTPUTCLR13_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn7_Pos) /*!< SCT OUTPUTCLR13: CLRn7 Mask */ -#define SCT_OUTPUTCLR13_CLRn8_Pos 8 /*!< SCT OUTPUTCLR13: CLRn8 Position */ -#define SCT_OUTPUTCLR13_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn8_Pos) /*!< SCT OUTPUTCLR13: CLRn8 Mask */ -#define SCT_OUTPUTCLR13_CLRn9_Pos 9 /*!< SCT OUTPUTCLR13: CLRn9 Position */ -#define SCT_OUTPUTCLR13_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn9_Pos) /*!< SCT OUTPUTCLR13: CLRn9 Mask */ -#define SCT_OUTPUTCLR13_CLRn10_Pos 10 /*!< SCT OUTPUTCLR13: CLRn10 Position */ -#define SCT_OUTPUTCLR13_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn10_Pos) /*!< SCT OUTPUTCLR13: CLRn10 Mask */ -#define SCT_OUTPUTCLR13_CLRn11_Pos 11 /*!< SCT OUTPUTCLR13: CLRn11 Position */ -#define SCT_OUTPUTCLR13_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn11_Pos) /*!< SCT OUTPUTCLR13: CLRn11 Mask */ -#define SCT_OUTPUTCLR13_CLRn12_Pos 12 /*!< SCT OUTPUTCLR13: CLRn12 Position */ -#define SCT_OUTPUTCLR13_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn12_Pos) /*!< SCT OUTPUTCLR13: CLRn12 Mask */ -#define SCT_OUTPUTCLR13_CLRn13_Pos 13 /*!< SCT OUTPUTCLR13: CLRn13 Position */ -#define SCT_OUTPUTCLR13_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn13_Pos) /*!< SCT OUTPUTCLR13: CLRn13 Mask */ -#define SCT_OUTPUTCLR13_CLRn14_Pos 14 /*!< SCT OUTPUTCLR13: CLRn14 Position */ -#define SCT_OUTPUTCLR13_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn14_Pos) /*!< SCT OUTPUTCLR13: CLRn14 Mask */ -#define SCT_OUTPUTCLR13_CLRn15_Pos 15 /*!< SCT OUTPUTCLR13: CLRn15 Position */ -#define SCT_OUTPUTCLR13_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR13_CLRn15_Pos) /*!< SCT OUTPUTCLR13: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET14 ---------------------------------------- -#define SCT_OUTPUTSET14_SETn0_Pos 0 /*!< SCT OUTPUTSET14: SETn0 Position */ -#define SCT_OUTPUTSET14_SETn0_Msk (0x01UL << SCT_OUTPUTSET14_SETn0_Pos) /*!< SCT OUTPUTSET14: SETn0 Mask */ -#define SCT_OUTPUTSET14_SETn1_Pos 1 /*!< SCT OUTPUTSET14: SETn1 Position */ -#define SCT_OUTPUTSET14_SETn1_Msk (0x01UL << SCT_OUTPUTSET14_SETn1_Pos) /*!< SCT OUTPUTSET14: SETn1 Mask */ -#define SCT_OUTPUTSET14_SETn2_Pos 2 /*!< SCT OUTPUTSET14: SETn2 Position */ -#define SCT_OUTPUTSET14_SETn2_Msk (0x01UL << SCT_OUTPUTSET14_SETn2_Pos) /*!< SCT OUTPUTSET14: SETn2 Mask */ -#define SCT_OUTPUTSET14_SETn3_Pos 3 /*!< SCT OUTPUTSET14: SETn3 Position */ -#define SCT_OUTPUTSET14_SETn3_Msk (0x01UL << SCT_OUTPUTSET14_SETn3_Pos) /*!< SCT OUTPUTSET14: SETn3 Mask */ -#define SCT_OUTPUTSET14_SETn4_Pos 4 /*!< SCT OUTPUTSET14: SETn4 Position */ -#define SCT_OUTPUTSET14_SETn4_Msk (0x01UL << SCT_OUTPUTSET14_SETn4_Pos) /*!< SCT OUTPUTSET14: SETn4 Mask */ -#define SCT_OUTPUTSET14_SETn5_Pos 5 /*!< SCT OUTPUTSET14: SETn5 Position */ -#define SCT_OUTPUTSET14_SETn5_Msk (0x01UL << SCT_OUTPUTSET14_SETn5_Pos) /*!< SCT OUTPUTSET14: SETn5 Mask */ -#define SCT_OUTPUTSET14_SETn6_Pos 6 /*!< SCT OUTPUTSET14: SETn6 Position */ -#define SCT_OUTPUTSET14_SETn6_Msk (0x01UL << SCT_OUTPUTSET14_SETn6_Pos) /*!< SCT OUTPUTSET14: SETn6 Mask */ -#define SCT_OUTPUTSET14_SETn7_Pos 7 /*!< SCT OUTPUTSET14: SETn7 Position */ -#define SCT_OUTPUTSET14_SETn7_Msk (0x01UL << SCT_OUTPUTSET14_SETn7_Pos) /*!< SCT OUTPUTSET14: SETn7 Mask */ -#define SCT_OUTPUTSET14_SETn8_Pos 8 /*!< SCT OUTPUTSET14: SETn8 Position */ -#define SCT_OUTPUTSET14_SETn8_Msk (0x01UL << SCT_OUTPUTSET14_SETn8_Pos) /*!< SCT OUTPUTSET14: SETn8 Mask */ -#define SCT_OUTPUTSET14_SETn9_Pos 9 /*!< SCT OUTPUTSET14: SETn9 Position */ -#define SCT_OUTPUTSET14_SETn9_Msk (0x01UL << SCT_OUTPUTSET14_SETn9_Pos) /*!< SCT OUTPUTSET14: SETn9 Mask */ -#define SCT_OUTPUTSET14_SETn10_Pos 10 /*!< SCT OUTPUTSET14: SETn10 Position */ -#define SCT_OUTPUTSET14_SETn10_Msk (0x01UL << SCT_OUTPUTSET14_SETn10_Pos) /*!< SCT OUTPUTSET14: SETn10 Mask */ -#define SCT_OUTPUTSET14_SETn11_Pos 11 /*!< SCT OUTPUTSET14: SETn11 Position */ -#define SCT_OUTPUTSET14_SETn11_Msk (0x01UL << SCT_OUTPUTSET14_SETn11_Pos) /*!< SCT OUTPUTSET14: SETn11 Mask */ -#define SCT_OUTPUTSET14_SETn12_Pos 12 /*!< SCT OUTPUTSET14: SETn12 Position */ -#define SCT_OUTPUTSET14_SETn12_Msk (0x01UL << SCT_OUTPUTSET14_SETn12_Pos) /*!< SCT OUTPUTSET14: SETn12 Mask */ -#define SCT_OUTPUTSET14_SETn13_Pos 13 /*!< SCT OUTPUTSET14: SETn13 Position */ -#define SCT_OUTPUTSET14_SETn13_Msk (0x01UL << SCT_OUTPUTSET14_SETn13_Pos) /*!< SCT OUTPUTSET14: SETn13 Mask */ -#define SCT_OUTPUTSET14_SETn14_Pos 14 /*!< SCT OUTPUTSET14: SETn14 Position */ -#define SCT_OUTPUTSET14_SETn14_Msk (0x01UL << SCT_OUTPUTSET14_SETn14_Pos) /*!< SCT OUTPUTSET14: SETn14 Mask */ -#define SCT_OUTPUTSET14_SETn15_Pos 15 /*!< SCT OUTPUTSET14: SETn15 Position */ -#define SCT_OUTPUTSET14_SETn15_Msk (0x01UL << SCT_OUTPUTSET14_SETn15_Pos) /*!< SCT OUTPUTSET14: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR14 ---------------------------------------- -#define SCT_OUTPUTCLR14_CLRn0_Pos 0 /*!< SCT OUTPUTCLR14: CLRn0 Position */ -#define SCT_OUTPUTCLR14_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn0_Pos) /*!< SCT OUTPUTCLR14: CLRn0 Mask */ -#define SCT_OUTPUTCLR14_CLRn1_Pos 1 /*!< SCT OUTPUTCLR14: CLRn1 Position */ -#define SCT_OUTPUTCLR14_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn1_Pos) /*!< SCT OUTPUTCLR14: CLRn1 Mask */ -#define SCT_OUTPUTCLR14_CLRn2_Pos 2 /*!< SCT OUTPUTCLR14: CLRn2 Position */ -#define SCT_OUTPUTCLR14_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn2_Pos) /*!< SCT OUTPUTCLR14: CLRn2 Mask */ -#define SCT_OUTPUTCLR14_CLRn3_Pos 3 /*!< SCT OUTPUTCLR14: CLRn3 Position */ -#define SCT_OUTPUTCLR14_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn3_Pos) /*!< SCT OUTPUTCLR14: CLRn3 Mask */ -#define SCT_OUTPUTCLR14_CLRn4_Pos 4 /*!< SCT OUTPUTCLR14: CLRn4 Position */ -#define SCT_OUTPUTCLR14_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn4_Pos) /*!< SCT OUTPUTCLR14: CLRn4 Mask */ -#define SCT_OUTPUTCLR14_CLRn5_Pos 5 /*!< SCT OUTPUTCLR14: CLRn5 Position */ -#define SCT_OUTPUTCLR14_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn5_Pos) /*!< SCT OUTPUTCLR14: CLRn5 Mask */ -#define SCT_OUTPUTCLR14_CLRn6_Pos 6 /*!< SCT OUTPUTCLR14: CLRn6 Position */ -#define SCT_OUTPUTCLR14_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn6_Pos) /*!< SCT OUTPUTCLR14: CLRn6 Mask */ -#define SCT_OUTPUTCLR14_CLRn7_Pos 7 /*!< SCT OUTPUTCLR14: CLRn7 Position */ -#define SCT_OUTPUTCLR14_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn7_Pos) /*!< SCT OUTPUTCLR14: CLRn7 Mask */ -#define SCT_OUTPUTCLR14_CLRn8_Pos 8 /*!< SCT OUTPUTCLR14: CLRn8 Position */ -#define SCT_OUTPUTCLR14_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn8_Pos) /*!< SCT OUTPUTCLR14: CLRn8 Mask */ -#define SCT_OUTPUTCLR14_CLRn9_Pos 9 /*!< SCT OUTPUTCLR14: CLRn9 Position */ -#define SCT_OUTPUTCLR14_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn9_Pos) /*!< SCT OUTPUTCLR14: CLRn9 Mask */ -#define SCT_OUTPUTCLR14_CLRn10_Pos 10 /*!< SCT OUTPUTCLR14: CLRn10 Position */ -#define SCT_OUTPUTCLR14_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn10_Pos) /*!< SCT OUTPUTCLR14: CLRn10 Mask */ -#define SCT_OUTPUTCLR14_CLRn11_Pos 11 /*!< SCT OUTPUTCLR14: CLRn11 Position */ -#define SCT_OUTPUTCLR14_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn11_Pos) /*!< SCT OUTPUTCLR14: CLRn11 Mask */ -#define SCT_OUTPUTCLR14_CLRn12_Pos 12 /*!< SCT OUTPUTCLR14: CLRn12 Position */ -#define SCT_OUTPUTCLR14_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn12_Pos) /*!< SCT OUTPUTCLR14: CLRn12 Mask */ -#define SCT_OUTPUTCLR14_CLRn13_Pos 13 /*!< SCT OUTPUTCLR14: CLRn13 Position */ -#define SCT_OUTPUTCLR14_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn13_Pos) /*!< SCT OUTPUTCLR14: CLRn13 Mask */ -#define SCT_OUTPUTCLR14_CLRn14_Pos 14 /*!< SCT OUTPUTCLR14: CLRn14 Position */ -#define SCT_OUTPUTCLR14_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn14_Pos) /*!< SCT OUTPUTCLR14: CLRn14 Mask */ -#define SCT_OUTPUTCLR14_CLRn15_Pos 15 /*!< SCT OUTPUTCLR14: CLRn15 Position */ -#define SCT_OUTPUTCLR14_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR14_CLRn15_Pos) /*!< SCT OUTPUTCLR14: CLRn15 Mask */ - -// ------------------------------------- SCT_OUTPUTSET15 ---------------------------------------- -#define SCT_OUTPUTSET15_SETn0_Pos 0 /*!< SCT OUTPUTSET15: SETn0 Position */ -#define SCT_OUTPUTSET15_SETn0_Msk (0x01UL << SCT_OUTPUTSET15_SETn0_Pos) /*!< SCT OUTPUTSET15: SETn0 Mask */ -#define SCT_OUTPUTSET15_SETn1_Pos 1 /*!< SCT OUTPUTSET15: SETn1 Position */ -#define SCT_OUTPUTSET15_SETn1_Msk (0x01UL << SCT_OUTPUTSET15_SETn1_Pos) /*!< SCT OUTPUTSET15: SETn1 Mask */ -#define SCT_OUTPUTSET15_SETn2_Pos 2 /*!< SCT OUTPUTSET15: SETn2 Position */ -#define SCT_OUTPUTSET15_SETn2_Msk (0x01UL << SCT_OUTPUTSET15_SETn2_Pos) /*!< SCT OUTPUTSET15: SETn2 Mask */ -#define SCT_OUTPUTSET15_SETn3_Pos 3 /*!< SCT OUTPUTSET15: SETn3 Position */ -#define SCT_OUTPUTSET15_SETn3_Msk (0x01UL << SCT_OUTPUTSET15_SETn3_Pos) /*!< SCT OUTPUTSET15: SETn3 Mask */ -#define SCT_OUTPUTSET15_SETn4_Pos 4 /*!< SCT OUTPUTSET15: SETn4 Position */ -#define SCT_OUTPUTSET15_SETn4_Msk (0x01UL << SCT_OUTPUTSET15_SETn4_Pos) /*!< SCT OUTPUTSET15: SETn4 Mask */ -#define SCT_OUTPUTSET15_SETn5_Pos 5 /*!< SCT OUTPUTSET15: SETn5 Position */ -#define SCT_OUTPUTSET15_SETn5_Msk (0x01UL << SCT_OUTPUTSET15_SETn5_Pos) /*!< SCT OUTPUTSET15: SETn5 Mask */ -#define SCT_OUTPUTSET15_SETn6_Pos 6 /*!< SCT OUTPUTSET15: SETn6 Position */ -#define SCT_OUTPUTSET15_SETn6_Msk (0x01UL << SCT_OUTPUTSET15_SETn6_Pos) /*!< SCT OUTPUTSET15: SETn6 Mask */ -#define SCT_OUTPUTSET15_SETn7_Pos 7 /*!< SCT OUTPUTSET15: SETn7 Position */ -#define SCT_OUTPUTSET15_SETn7_Msk (0x01UL << SCT_OUTPUTSET15_SETn7_Pos) /*!< SCT OUTPUTSET15: SETn7 Mask */ -#define SCT_OUTPUTSET15_SETn8_Pos 8 /*!< SCT OUTPUTSET15: SETn8 Position */ -#define SCT_OUTPUTSET15_SETn8_Msk (0x01UL << SCT_OUTPUTSET15_SETn8_Pos) /*!< SCT OUTPUTSET15: SETn8 Mask */ -#define SCT_OUTPUTSET15_SETn9_Pos 9 /*!< SCT OUTPUTSET15: SETn9 Position */ -#define SCT_OUTPUTSET15_SETn9_Msk (0x01UL << SCT_OUTPUTSET15_SETn9_Pos) /*!< SCT OUTPUTSET15: SETn9 Mask */ -#define SCT_OUTPUTSET15_SETn10_Pos 10 /*!< SCT OUTPUTSET15: SETn10 Position */ -#define SCT_OUTPUTSET15_SETn10_Msk (0x01UL << SCT_OUTPUTSET15_SETn10_Pos) /*!< SCT OUTPUTSET15: SETn10 Mask */ -#define SCT_OUTPUTSET15_SETn11_Pos 11 /*!< SCT OUTPUTSET15: SETn11 Position */ -#define SCT_OUTPUTSET15_SETn11_Msk (0x01UL << SCT_OUTPUTSET15_SETn11_Pos) /*!< SCT OUTPUTSET15: SETn11 Mask */ -#define SCT_OUTPUTSET15_SETn12_Pos 12 /*!< SCT OUTPUTSET15: SETn12 Position */ -#define SCT_OUTPUTSET15_SETn12_Msk (0x01UL << SCT_OUTPUTSET15_SETn12_Pos) /*!< SCT OUTPUTSET15: SETn12 Mask */ -#define SCT_OUTPUTSET15_SETn13_Pos 13 /*!< SCT OUTPUTSET15: SETn13 Position */ -#define SCT_OUTPUTSET15_SETn13_Msk (0x01UL << SCT_OUTPUTSET15_SETn13_Pos) /*!< SCT OUTPUTSET15: SETn13 Mask */ -#define SCT_OUTPUTSET15_SETn14_Pos 14 /*!< SCT OUTPUTSET15: SETn14 Position */ -#define SCT_OUTPUTSET15_SETn14_Msk (0x01UL << SCT_OUTPUTSET15_SETn14_Pos) /*!< SCT OUTPUTSET15: SETn14 Mask */ -#define SCT_OUTPUTSET15_SETn15_Pos 15 /*!< SCT OUTPUTSET15: SETn15 Position */ -#define SCT_OUTPUTSET15_SETn15_Msk (0x01UL << SCT_OUTPUTSET15_SETn15_Pos) /*!< SCT OUTPUTSET15: SETn15 Mask */ - -// ------------------------------------- SCT_OUTPUTCLR15 ---------------------------------------- -#define SCT_OUTPUTCLR15_CLRn0_Pos 0 /*!< SCT OUTPUTCLR15: CLRn0 Position */ -#define SCT_OUTPUTCLR15_CLRn0_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn0_Pos) /*!< SCT OUTPUTCLR15: CLRn0 Mask */ -#define SCT_OUTPUTCLR15_CLRn1_Pos 1 /*!< SCT OUTPUTCLR15: CLRn1 Position */ -#define SCT_OUTPUTCLR15_CLRn1_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn1_Pos) /*!< SCT OUTPUTCLR15: CLRn1 Mask */ -#define SCT_OUTPUTCLR15_CLRn2_Pos 2 /*!< SCT OUTPUTCLR15: CLRn2 Position */ -#define SCT_OUTPUTCLR15_CLRn2_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn2_Pos) /*!< SCT OUTPUTCLR15: CLRn2 Mask */ -#define SCT_OUTPUTCLR15_CLRn3_Pos 3 /*!< SCT OUTPUTCLR15: CLRn3 Position */ -#define SCT_OUTPUTCLR15_CLRn3_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn3_Pos) /*!< SCT OUTPUTCLR15: CLRn3 Mask */ -#define SCT_OUTPUTCLR15_CLRn4_Pos 4 /*!< SCT OUTPUTCLR15: CLRn4 Position */ -#define SCT_OUTPUTCLR15_CLRn4_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn4_Pos) /*!< SCT OUTPUTCLR15: CLRn4 Mask */ -#define SCT_OUTPUTCLR15_CLRn5_Pos 5 /*!< SCT OUTPUTCLR15: CLRn5 Position */ -#define SCT_OUTPUTCLR15_CLRn5_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn5_Pos) /*!< SCT OUTPUTCLR15: CLRn5 Mask */ -#define SCT_OUTPUTCLR15_CLRn6_Pos 6 /*!< SCT OUTPUTCLR15: CLRn6 Position */ -#define SCT_OUTPUTCLR15_CLRn6_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn6_Pos) /*!< SCT OUTPUTCLR15: CLRn6 Mask */ -#define SCT_OUTPUTCLR15_CLRn7_Pos 7 /*!< SCT OUTPUTCLR15: CLRn7 Position */ -#define SCT_OUTPUTCLR15_CLRn7_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn7_Pos) /*!< SCT OUTPUTCLR15: CLRn7 Mask */ -#define SCT_OUTPUTCLR15_CLRn8_Pos 8 /*!< SCT OUTPUTCLR15: CLRn8 Position */ -#define SCT_OUTPUTCLR15_CLRn8_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn8_Pos) /*!< SCT OUTPUTCLR15: CLRn8 Mask */ -#define SCT_OUTPUTCLR15_CLRn9_Pos 9 /*!< SCT OUTPUTCLR15: CLRn9 Position */ -#define SCT_OUTPUTCLR15_CLRn9_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn9_Pos) /*!< SCT OUTPUTCLR15: CLRn9 Mask */ -#define SCT_OUTPUTCLR15_CLRn10_Pos 10 /*!< SCT OUTPUTCLR15: CLRn10 Position */ -#define SCT_OUTPUTCLR15_CLRn10_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn10_Pos) /*!< SCT OUTPUTCLR15: CLRn10 Mask */ -#define SCT_OUTPUTCLR15_CLRn11_Pos 11 /*!< SCT OUTPUTCLR15: CLRn11 Position */ -#define SCT_OUTPUTCLR15_CLRn11_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn11_Pos) /*!< SCT OUTPUTCLR15: CLRn11 Mask */ -#define SCT_OUTPUTCLR15_CLRn12_Pos 12 /*!< SCT OUTPUTCLR15: CLRn12 Position */ -#define SCT_OUTPUTCLR15_CLRn12_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn12_Pos) /*!< SCT OUTPUTCLR15: CLRn12 Mask */ -#define SCT_OUTPUTCLR15_CLRn13_Pos 13 /*!< SCT OUTPUTCLR15: CLRn13 Position */ -#define SCT_OUTPUTCLR15_CLRn13_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn13_Pos) /*!< SCT OUTPUTCLR15: CLRn13 Mask */ -#define SCT_OUTPUTCLR15_CLRn14_Pos 14 /*!< SCT OUTPUTCLR15: CLRn14 Position */ -#define SCT_OUTPUTCLR15_CLRn14_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn14_Pos) /*!< SCT OUTPUTCLR15: CLRn14 Mask */ -#define SCT_OUTPUTCLR15_CLRn15_Pos 15 /*!< SCT OUTPUTCLR15: CLRn15 Position */ -#define SCT_OUTPUTCLR15_CLRn15_Msk (0x01UL << SCT_OUTPUTCLR15_CLRn15_Pos) /*!< SCT OUTPUTCLR15: CLRn15 Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- GPDMA Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// -------------------------------------- GPDMA_INTSTAT ----------------------------------------- -#define GPDMA_INTSTAT_INTSTAT0_Pos 0 /*!< GPDMA INTSTAT: INTSTAT0 Position */ -#define GPDMA_INTSTAT_INTSTAT0_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT0_Pos) /*!< GPDMA INTSTAT: INTSTAT0 Mask */ -#define GPDMA_INTSTAT_INTSTAT1_Pos 1 /*!< GPDMA INTSTAT: INTSTAT1 Position */ -#define GPDMA_INTSTAT_INTSTAT1_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT1_Pos) /*!< GPDMA INTSTAT: INTSTAT1 Mask */ -#define GPDMA_INTSTAT_INTSTAT2_Pos 2 /*!< GPDMA INTSTAT: INTSTAT2 Position */ -#define GPDMA_INTSTAT_INTSTAT2_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT2_Pos) /*!< GPDMA INTSTAT: INTSTAT2 Mask */ -#define GPDMA_INTSTAT_INTSTAT3_Pos 3 /*!< GPDMA INTSTAT: INTSTAT3 Position */ -#define GPDMA_INTSTAT_INTSTAT3_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT3_Pos) /*!< GPDMA INTSTAT: INTSTAT3 Mask */ -#define GPDMA_INTSTAT_INTSTAT4_Pos 4 /*!< GPDMA INTSTAT: INTSTAT4 Position */ -#define GPDMA_INTSTAT_INTSTAT4_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT4_Pos) /*!< GPDMA INTSTAT: INTSTAT4 Mask */ -#define GPDMA_INTSTAT_INTSTAT5_Pos 5 /*!< GPDMA INTSTAT: INTSTAT5 Position */ -#define GPDMA_INTSTAT_INTSTAT5_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT5_Pos) /*!< GPDMA INTSTAT: INTSTAT5 Mask */ -#define GPDMA_INTSTAT_INTSTAT6_Pos 6 /*!< GPDMA INTSTAT: INTSTAT6 Position */ -#define GPDMA_INTSTAT_INTSTAT6_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT6_Pos) /*!< GPDMA INTSTAT: INTSTAT6 Mask */ -#define GPDMA_INTSTAT_INTSTAT7_Pos 7 /*!< GPDMA INTSTAT: INTSTAT7 Position */ -#define GPDMA_INTSTAT_INTSTAT7_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT7_Pos) /*!< GPDMA INTSTAT: INTSTAT7 Mask */ - -// ------------------------------------- GPDMA_INTTCSTAT ---------------------------------------- -#define GPDMA_INTTCSTAT_INTTCSTAT0_Pos 0 /*!< GPDMA INTTCSTAT: INTTCSTAT0 Position */ -#define GPDMA_INTTCSTAT_INTTCSTAT0_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT0_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT0 Mask */ -#define GPDMA_INTTCSTAT_INTTCSTAT1_Pos 1 /*!< GPDMA INTTCSTAT: INTTCSTAT1 Position */ -#define GPDMA_INTTCSTAT_INTTCSTAT1_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT1_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT1 Mask */ -#define GPDMA_INTTCSTAT_INTTCSTAT2_Pos 2 /*!< GPDMA INTTCSTAT: INTTCSTAT2 Position */ -#define GPDMA_INTTCSTAT_INTTCSTAT2_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT2_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT2 Mask */ -#define GPDMA_INTTCSTAT_INTTCSTAT3_Pos 3 /*!< GPDMA INTTCSTAT: INTTCSTAT3 Position */ -#define GPDMA_INTTCSTAT_INTTCSTAT3_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT3_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT3 Mask */ -#define GPDMA_INTTCSTAT_INTTCSTAT4_Pos 4 /*!< GPDMA INTTCSTAT: INTTCSTAT4 Position */ -#define GPDMA_INTTCSTAT_INTTCSTAT4_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT4_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT4 Mask */ -#define GPDMA_INTTCSTAT_INTTCSTAT5_Pos 5 /*!< GPDMA INTTCSTAT: INTTCSTAT5 Position */ -#define GPDMA_INTTCSTAT_INTTCSTAT5_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT5_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT5 Mask */ -#define GPDMA_INTTCSTAT_INTTCSTAT6_Pos 6 /*!< GPDMA INTTCSTAT: INTTCSTAT6 Position */ -#define GPDMA_INTTCSTAT_INTTCSTAT6_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT6_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT6 Mask */ -#define GPDMA_INTTCSTAT_INTTCSTAT7_Pos 7 /*!< GPDMA INTTCSTAT: INTTCSTAT7 Position */ -#define GPDMA_INTTCSTAT_INTTCSTAT7_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT7_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT7 Mask */ - -// ------------------------------------ GPDMA_INTTCCLEAR ---------------------------------------- -#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos 0 /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Position */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Mask */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos 1 /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Position */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Mask */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos 2 /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Position */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Mask */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos 3 /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Position */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Mask */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos 4 /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Position */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Mask */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos 5 /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Position */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Mask */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos 6 /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Position */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Mask */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos 7 /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Position */ -#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Mask */ - -// ------------------------------------ GPDMA_INTERRSTAT ---------------------------------------- -#define GPDMA_INTERRSTAT_INTERRSTAT0_Pos 0 /*!< GPDMA INTERRSTAT: INTERRSTAT0 Position */ -#define GPDMA_INTERRSTAT_INTERRSTAT0_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT0_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT0 Mask */ -#define GPDMA_INTERRSTAT_INTERRSTAT1_Pos 1 /*!< GPDMA INTERRSTAT: INTERRSTAT1 Position */ -#define GPDMA_INTERRSTAT_INTERRSTAT1_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT1_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT1 Mask */ -#define GPDMA_INTERRSTAT_INTERRSTAT2_Pos 2 /*!< GPDMA INTERRSTAT: INTERRSTAT2 Position */ -#define GPDMA_INTERRSTAT_INTERRSTAT2_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT2_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT2 Mask */ -#define GPDMA_INTERRSTAT_INTERRSTAT3_Pos 3 /*!< GPDMA INTERRSTAT: INTERRSTAT3 Position */ -#define GPDMA_INTERRSTAT_INTERRSTAT3_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT3_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT3 Mask */ -#define GPDMA_INTERRSTAT_INTERRSTAT4_Pos 4 /*!< GPDMA INTERRSTAT: INTERRSTAT4 Position */ -#define GPDMA_INTERRSTAT_INTERRSTAT4_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT4_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT4 Mask */ -#define GPDMA_INTERRSTAT_INTERRSTAT5_Pos 5 /*!< GPDMA INTERRSTAT: INTERRSTAT5 Position */ -#define GPDMA_INTERRSTAT_INTERRSTAT5_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT5_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT5 Mask */ -#define GPDMA_INTERRSTAT_INTERRSTAT6_Pos 6 /*!< GPDMA INTERRSTAT: INTERRSTAT6 Position */ -#define GPDMA_INTERRSTAT_INTERRSTAT6_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT6_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT6 Mask */ -#define GPDMA_INTERRSTAT_INTERRSTAT7_Pos 7 /*!< GPDMA INTERRSTAT: INTERRSTAT7 Position */ -#define GPDMA_INTERRSTAT_INTERRSTAT7_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT7_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT7 Mask */ - -// ------------------------------------- GPDMA_INTERRCLR ---------------------------------------- -#define GPDMA_INTERRCLR_INTERRCLR0_Pos 0 /*!< GPDMA INTERRCLR: INTERRCLR0 Position */ -#define GPDMA_INTERRCLR_INTERRCLR0_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR0_Pos) /*!< GPDMA INTERRCLR: INTERRCLR0 Mask */ -#define GPDMA_INTERRCLR_INTERRCLR1_Pos 1 /*!< GPDMA INTERRCLR: INTERRCLR1 Position */ -#define GPDMA_INTERRCLR_INTERRCLR1_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR1_Pos) /*!< GPDMA INTERRCLR: INTERRCLR1 Mask */ -#define GPDMA_INTERRCLR_INTERRCLR2_Pos 2 /*!< GPDMA INTERRCLR: INTERRCLR2 Position */ -#define GPDMA_INTERRCLR_INTERRCLR2_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR2_Pos) /*!< GPDMA INTERRCLR: INTERRCLR2 Mask */ -#define GPDMA_INTERRCLR_INTERRCLR3_Pos 3 /*!< GPDMA INTERRCLR: INTERRCLR3 Position */ -#define GPDMA_INTERRCLR_INTERRCLR3_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR3_Pos) /*!< GPDMA INTERRCLR: INTERRCLR3 Mask */ -#define GPDMA_INTERRCLR_INTERRCLR4_Pos 4 /*!< GPDMA INTERRCLR: INTERRCLR4 Position */ -#define GPDMA_INTERRCLR_INTERRCLR4_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR4_Pos) /*!< GPDMA INTERRCLR: INTERRCLR4 Mask */ -#define GPDMA_INTERRCLR_INTERRCLR5_Pos 5 /*!< GPDMA INTERRCLR: INTERRCLR5 Position */ -#define GPDMA_INTERRCLR_INTERRCLR5_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR5_Pos) /*!< GPDMA INTERRCLR: INTERRCLR5 Mask */ -#define GPDMA_INTERRCLR_INTERRCLR6_Pos 6 /*!< GPDMA INTERRCLR: INTERRCLR6 Position */ -#define GPDMA_INTERRCLR_INTERRCLR6_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR6_Pos) /*!< GPDMA INTERRCLR: INTERRCLR6 Mask */ -#define GPDMA_INTERRCLR_INTERRCLR7_Pos 7 /*!< GPDMA INTERRCLR: INTERRCLR7 Position */ -#define GPDMA_INTERRCLR_INTERRCLR7_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR7_Pos) /*!< GPDMA INTERRCLR: INTERRCLR7 Mask */ - -// ----------------------------------- GPDMA_RAWINTTCSTAT --------------------------------------- -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos 0 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Position */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Mask */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos 1 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Position */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Mask */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos 2 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Position */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Mask */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos 3 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Position */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Mask */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos 4 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Position */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Mask */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos 5 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Position */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Mask */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos 6 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Position */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Mask */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos 7 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Position */ -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Mask */ - -// ----------------------------------- GPDMA_RAWINTERRSTAT -------------------------------------- -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos 0 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Position */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Mask */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos 1 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Position */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Mask */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos 2 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Position */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Mask */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos 3 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Position */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Mask */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos 4 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Position */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Mask */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos 5 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Position */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Mask */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos 6 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Position */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Mask */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos 7 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Position */ -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Mask */ - -// ------------------------------------- GPDMA_ENBLDCHNS ---------------------------------------- -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos 0 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Position */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Mask */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos 1 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Position */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Mask */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos 2 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Position */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Mask */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos 3 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Position */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Mask */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos 4 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Position */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Mask */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos 5 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Position */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Mask */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos 6 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Position */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Mask */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos 7 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Position */ -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Mask */ - -// ------------------------------------- GPDMA_SOFTBREQ ----------------------------------------- -#define GPDMA_SOFTBREQ_SOFTBREQ0_Pos 0 /*!< GPDMA SOFTBREQ: SOFTBREQ0 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ0_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ0_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ0 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ1_Pos 1 /*!< GPDMA SOFTBREQ: SOFTBREQ1 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ1_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ1_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ1 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ2_Pos 2 /*!< GPDMA SOFTBREQ: SOFTBREQ2 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ2_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ2_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ2 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ3_Pos 3 /*!< GPDMA SOFTBREQ: SOFTBREQ3 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ3_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ3_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ3 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ4_Pos 4 /*!< GPDMA SOFTBREQ: SOFTBREQ4 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ4_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ4_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ4 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ5_Pos 5 /*!< GPDMA SOFTBREQ: SOFTBREQ5 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ5_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ5_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ5 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ6_Pos 6 /*!< GPDMA SOFTBREQ: SOFTBREQ6 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ6_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ6_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ6 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ7_Pos 7 /*!< GPDMA SOFTBREQ: SOFTBREQ7 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ7_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ7_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ7 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ8_Pos 8 /*!< GPDMA SOFTBREQ: SOFTBREQ8 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ8_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ8_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ8 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ9_Pos 9 /*!< GPDMA SOFTBREQ: SOFTBREQ9 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ9_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ9_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ9 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ10_Pos 10 /*!< GPDMA SOFTBREQ: SOFTBREQ10 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ10_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ10_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ10 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ11_Pos 11 /*!< GPDMA SOFTBREQ: SOFTBREQ11 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ11_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ11_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ11 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ12_Pos 12 /*!< GPDMA SOFTBREQ: SOFTBREQ12 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ12_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ12_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ12 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ13_Pos 13 /*!< GPDMA SOFTBREQ: SOFTBREQ13 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ13_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ13_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ13 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ14_Pos 14 /*!< GPDMA SOFTBREQ: SOFTBREQ14 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ14_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ14_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ14 Mask */ -#define GPDMA_SOFTBREQ_SOFTBREQ15_Pos 15 /*!< GPDMA SOFTBREQ: SOFTBREQ15 Position */ -#define GPDMA_SOFTBREQ_SOFTBREQ15_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ15_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ15 Mask */ - -// ------------------------------------- GPDMA_SOFTSREQ ----------------------------------------- -#define GPDMA_SOFTSREQ_SOFTSREQ0_Pos 0 /*!< GPDMA SOFTSREQ: SOFTSREQ0 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ0_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ0_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ0 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ1_Pos 1 /*!< GPDMA SOFTSREQ: SOFTSREQ1 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ1_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ1_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ1 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ2_Pos 2 /*!< GPDMA SOFTSREQ: SOFTSREQ2 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ2_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ2_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ2 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ3_Pos 3 /*!< GPDMA SOFTSREQ: SOFTSREQ3 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ3_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ3_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ3 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ4_Pos 4 /*!< GPDMA SOFTSREQ: SOFTSREQ4 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ4_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ4_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ4 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ5_Pos 5 /*!< GPDMA SOFTSREQ: SOFTSREQ5 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ5_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ5_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ5 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ6_Pos 6 /*!< GPDMA SOFTSREQ: SOFTSREQ6 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ6_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ6_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ6 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ7_Pos 7 /*!< GPDMA SOFTSREQ: SOFTSREQ7 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ7_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ7_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ7 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ8_Pos 8 /*!< GPDMA SOFTSREQ: SOFTSREQ8 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ8_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ8_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ8 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ9_Pos 9 /*!< GPDMA SOFTSREQ: SOFTSREQ9 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ9_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ9_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ9 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ10_Pos 10 /*!< GPDMA SOFTSREQ: SOFTSREQ10 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ10_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ10_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ10 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ11_Pos 11 /*!< GPDMA SOFTSREQ: SOFTSREQ11 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ11_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ11_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ11 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ12_Pos 12 /*!< GPDMA SOFTSREQ: SOFTSREQ12 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ12_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ12_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ12 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ13_Pos 13 /*!< GPDMA SOFTSREQ: SOFTSREQ13 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ13_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ13_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ13 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ14_Pos 14 /*!< GPDMA SOFTSREQ: SOFTSREQ14 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ14_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ14_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ14 Mask */ -#define GPDMA_SOFTSREQ_SOFTSREQ15_Pos 15 /*!< GPDMA SOFTSREQ: SOFTSREQ15 Position */ -#define GPDMA_SOFTSREQ_SOFTSREQ15_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ15_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ15 Mask */ - -// ------------------------------------- GPDMA_SOFTLBREQ ---------------------------------------- -#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos 0 /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos 1 /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos 2 /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos 3 /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos 4 /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos 5 /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos 6 /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos 7 /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos 8 /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos 9 /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos 10 /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos 11 /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos 12 /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos 13 /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos 14 /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Mask */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos 15 /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Position */ -#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Mask */ - -// ------------------------------------- GPDMA_SOFTLSREQ ---------------------------------------- -#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos 0 /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos 1 /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos 2 /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos 3 /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos 4 /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos 5 /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos 6 /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos 7 /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos 8 /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos 9 /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos 10 /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos 11 /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos 12 /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos 13 /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos 14 /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Mask */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos 15 /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Position */ -#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Mask */ - -// -------------------------------------- GPDMA_CONFIG ------------------------------------------ -#define GPDMA_CONFIG_E_Pos 0 /*!< GPDMA CONFIG: E Position */ -#define GPDMA_CONFIG_E_Msk (0x01UL << GPDMA_CONFIG_E_Pos) /*!< GPDMA CONFIG: E Mask */ -#define GPDMA_CONFIG_M0_Pos 1 /*!< GPDMA CONFIG: M0 Position */ -#define GPDMA_CONFIG_M0_Msk (0x01UL << GPDMA_CONFIG_M0_Pos) /*!< GPDMA CONFIG: M0 Mask */ -#define GPDMA_CONFIG_M1_Pos 2 /*!< GPDMA CONFIG: M1 Position */ -#define GPDMA_CONFIG_M1_Msk (0x01UL << GPDMA_CONFIG_M1_Pos) /*!< GPDMA CONFIG: M1 Mask */ - -// --------------------------------------- GPDMA_SYNC ------------------------------------------- -#define GPDMA_SYNC_DMACSYNC0_Pos 0 /*!< GPDMA SYNC: DMACSYNC0 Position */ -#define GPDMA_SYNC_DMACSYNC0_Msk (0x01UL << GPDMA_SYNC_DMACSYNC0_Pos) /*!< GPDMA SYNC: DMACSYNC0 Mask */ -#define GPDMA_SYNC_DMACSYNC1_Pos 1 /*!< GPDMA SYNC: DMACSYNC1 Position */ -#define GPDMA_SYNC_DMACSYNC1_Msk (0x01UL << GPDMA_SYNC_DMACSYNC1_Pos) /*!< GPDMA SYNC: DMACSYNC1 Mask */ -#define GPDMA_SYNC_DMACSYNC2_Pos 2 /*!< GPDMA SYNC: DMACSYNC2 Position */ -#define GPDMA_SYNC_DMACSYNC2_Msk (0x01UL << GPDMA_SYNC_DMACSYNC2_Pos) /*!< GPDMA SYNC: DMACSYNC2 Mask */ -#define GPDMA_SYNC_DMACSYNC3_Pos 3 /*!< GPDMA SYNC: DMACSYNC3 Position */ -#define GPDMA_SYNC_DMACSYNC3_Msk (0x01UL << GPDMA_SYNC_DMACSYNC3_Pos) /*!< GPDMA SYNC: DMACSYNC3 Mask */ -#define GPDMA_SYNC_DMACSYNC4_Pos 4 /*!< GPDMA SYNC: DMACSYNC4 Position */ -#define GPDMA_SYNC_DMACSYNC4_Msk (0x01UL << GPDMA_SYNC_DMACSYNC4_Pos) /*!< GPDMA SYNC: DMACSYNC4 Mask */ -#define GPDMA_SYNC_DMACSYNC5_Pos 5 /*!< GPDMA SYNC: DMACSYNC5 Position */ -#define GPDMA_SYNC_DMACSYNC5_Msk (0x01UL << GPDMA_SYNC_DMACSYNC5_Pos) /*!< GPDMA SYNC: DMACSYNC5 Mask */ -#define GPDMA_SYNC_DMACSYNC6_Pos 6 /*!< GPDMA SYNC: DMACSYNC6 Position */ -#define GPDMA_SYNC_DMACSYNC6_Msk (0x01UL << GPDMA_SYNC_DMACSYNC6_Pos) /*!< GPDMA SYNC: DMACSYNC6 Mask */ -#define GPDMA_SYNC_DMACSYNC7_Pos 7 /*!< GPDMA SYNC: DMACSYNC7 Position */ -#define GPDMA_SYNC_DMACSYNC7_Msk (0x01UL << GPDMA_SYNC_DMACSYNC7_Pos) /*!< GPDMA SYNC: DMACSYNC7 Mask */ -#define GPDMA_SYNC_DMACSYNC8_Pos 8 /*!< GPDMA SYNC: DMACSYNC8 Position */ -#define GPDMA_SYNC_DMACSYNC8_Msk (0x01UL << GPDMA_SYNC_DMACSYNC8_Pos) /*!< GPDMA SYNC: DMACSYNC8 Mask */ -#define GPDMA_SYNC_DMACSYNC9_Pos 9 /*!< GPDMA SYNC: DMACSYNC9 Position */ -#define GPDMA_SYNC_DMACSYNC9_Msk (0x01UL << GPDMA_SYNC_DMACSYNC9_Pos) /*!< GPDMA SYNC: DMACSYNC9 Mask */ -#define GPDMA_SYNC_DMACSYNC10_Pos 10 /*!< GPDMA SYNC: DMACSYNC10 Position */ -#define GPDMA_SYNC_DMACSYNC10_Msk (0x01UL << GPDMA_SYNC_DMACSYNC10_Pos) /*!< GPDMA SYNC: DMACSYNC10 Mask */ -#define GPDMA_SYNC_DMACSYNC11_Pos 11 /*!< GPDMA SYNC: DMACSYNC11 Position */ -#define GPDMA_SYNC_DMACSYNC11_Msk (0x01UL << GPDMA_SYNC_DMACSYNC11_Pos) /*!< GPDMA SYNC: DMACSYNC11 Mask */ -#define GPDMA_SYNC_DMACSYNC12_Pos 12 /*!< GPDMA SYNC: DMACSYNC12 Position */ -#define GPDMA_SYNC_DMACSYNC12_Msk (0x01UL << GPDMA_SYNC_DMACSYNC12_Pos) /*!< GPDMA SYNC: DMACSYNC12 Mask */ -#define GPDMA_SYNC_DMACSYNC13_Pos 13 /*!< GPDMA SYNC: DMACSYNC13 Position */ -#define GPDMA_SYNC_DMACSYNC13_Msk (0x01UL << GPDMA_SYNC_DMACSYNC13_Pos) /*!< GPDMA SYNC: DMACSYNC13 Mask */ -#define GPDMA_SYNC_DMACSYNC14_Pos 14 /*!< GPDMA SYNC: DMACSYNC14 Position */ -#define GPDMA_SYNC_DMACSYNC14_Msk (0x01UL << GPDMA_SYNC_DMACSYNC14_Pos) /*!< GPDMA SYNC: DMACSYNC14 Mask */ -#define GPDMA_SYNC_DMACSYNC15_Pos 15 /*!< GPDMA SYNC: DMACSYNC15 Position */ -#define GPDMA_SYNC_DMACSYNC15_Msk (0x01UL << GPDMA_SYNC_DMACSYNC15_Pos) /*!< GPDMA SYNC: DMACSYNC15 Mask */ - -// ------------------------------------- GPDMA_C0SRCADDR ---------------------------------------- -#define GPDMA_C0SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C0SRCADDR: SRCADDR Position */ -#define GPDMA_C0SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C0SRCADDR_SRCADDR_Pos) /*!< GPDMA C0SRCADDR: SRCADDR Mask */ - -// ------------------------------------ GPDMA_C0DESTADDR ---------------------------------------- -#define GPDMA_C0DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C0DESTADDR: DESTADDR Position */ -#define GPDMA_C0DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C0DESTADDR_DESTADDR_Pos) /*!< GPDMA C0DESTADDR: DESTADDR Mask */ - -// --------------------------------------- GPDMA_C0LLI ------------------------------------------ -#define GPDMA_C0LLI_LM_Pos 0 /*!< GPDMA C0LLI: LM Position */ -#define GPDMA_C0LLI_LM_Msk (0x01UL << GPDMA_C0LLI_LM_Pos) /*!< GPDMA C0LLI: LM Mask */ -#define GPDMA_C0LLI_R_Pos 1 /*!< GPDMA C0LLI: R Position */ -#define GPDMA_C0LLI_R_Msk (0x01UL << GPDMA_C0LLI_R_Pos) /*!< GPDMA C0LLI: R Mask */ -#define GPDMA_C0LLI_LLI_Pos 2 /*!< GPDMA C0LLI: LLI Position */ -#define GPDMA_C0LLI_LLI_Msk (0x3fffffffUL << GPDMA_C0LLI_LLI_Pos) /*!< GPDMA C0LLI: LLI Mask */ - -// ------------------------------------- GPDMA_C0CONTROL ---------------------------------------- -#define GPDMA_C0CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C0CONTROL: TRANSFERSIZE Position */ -#define GPDMA_C0CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C0CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C0CONTROL: TRANSFERSIZE Mask */ -#define GPDMA_C0CONTROL_SBSIZE_Pos 12 /*!< GPDMA C0CONTROL: SBSIZE Position */ -#define GPDMA_C0CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C0CONTROL_SBSIZE_Pos) /*!< GPDMA C0CONTROL: SBSIZE Mask */ -#define GPDMA_C0CONTROL_DBSIZE_Pos 15 /*!< GPDMA C0CONTROL: DBSIZE Position */ -#define GPDMA_C0CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C0CONTROL_DBSIZE_Pos) /*!< GPDMA C0CONTROL: DBSIZE Mask */ -#define GPDMA_C0CONTROL_SWIDTH_Pos 18 /*!< GPDMA C0CONTROL: SWIDTH Position */ -#define GPDMA_C0CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C0CONTROL_SWIDTH_Pos) /*!< GPDMA C0CONTROL: SWIDTH Mask */ -#define GPDMA_C0CONTROL_DWIDTH_Pos 21 /*!< GPDMA C0CONTROL: DWIDTH Position */ -#define GPDMA_C0CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C0CONTROL_DWIDTH_Pos) /*!< GPDMA C0CONTROL: DWIDTH Mask */ -#define GPDMA_C0CONTROL_S_Pos 24 /*!< GPDMA C0CONTROL: S Position */ -#define GPDMA_C0CONTROL_S_Msk (0x01UL << GPDMA_C0CONTROL_S_Pos) /*!< GPDMA C0CONTROL: S Mask */ -#define GPDMA_C0CONTROL_D_Pos 25 /*!< GPDMA C0CONTROL: D Position */ -#define GPDMA_C0CONTROL_D_Msk (0x01UL << GPDMA_C0CONTROL_D_Pos) /*!< GPDMA C0CONTROL: D Mask */ -#define GPDMA_C0CONTROL_SI_Pos 26 /*!< GPDMA C0CONTROL: SI Position */ -#define GPDMA_C0CONTROL_SI_Msk (0x01UL << GPDMA_C0CONTROL_SI_Pos) /*!< GPDMA C0CONTROL: SI Mask */ -#define GPDMA_C0CONTROL_DI_Pos 27 /*!< GPDMA C0CONTROL: DI Position */ -#define GPDMA_C0CONTROL_DI_Msk (0x01UL << GPDMA_C0CONTROL_DI_Pos) /*!< GPDMA C0CONTROL: DI Mask */ -#define GPDMA_C0CONTROL_PROT1_Pos 28 /*!< GPDMA C0CONTROL: PROT1 Position */ -#define GPDMA_C0CONTROL_PROT1_Msk (0x01UL << GPDMA_C0CONTROL_PROT1_Pos) /*!< GPDMA C0CONTROL: PROT1 Mask */ -#define GPDMA_C0CONTROL_PROT2_Pos 29 /*!< GPDMA C0CONTROL: PROT2 Position */ -#define GPDMA_C0CONTROL_PROT2_Msk (0x01UL << GPDMA_C0CONTROL_PROT2_Pos) /*!< GPDMA C0CONTROL: PROT2 Mask */ -#define GPDMA_C0CONTROL_PROT3_Pos 30 /*!< GPDMA C0CONTROL: PROT3 Position */ -#define GPDMA_C0CONTROL_PROT3_Msk (0x01UL << GPDMA_C0CONTROL_PROT3_Pos) /*!< GPDMA C0CONTROL: PROT3 Mask */ -#define GPDMA_C0CONTROL_I_Pos 31 /*!< GPDMA C0CONTROL: I Position */ -#define GPDMA_C0CONTROL_I_Msk (0x01UL << GPDMA_C0CONTROL_I_Pos) /*!< GPDMA C0CONTROL: I Mask */ - -// ------------------------------------- GPDMA_C0CONFIG ----------------------------------------- -#define GPDMA_C0CONFIG_E_Pos 0 /*!< GPDMA C0CONFIG: E Position */ -#define GPDMA_C0CONFIG_E_Msk (0x01UL << GPDMA_C0CONFIG_E_Pos) /*!< GPDMA C0CONFIG: E Mask */ -#define GPDMA_C0CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C0CONFIG: SRCPERIPHERAL Position */ -#define GPDMA_C0CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C0CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C0CONFIG: SRCPERIPHERAL Mask */ -#define GPDMA_C0CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C0CONFIG: DESTPERIPHERAL Position */ -#define GPDMA_C0CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C0CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C0CONFIG: DESTPERIPHERAL Mask */ -#define GPDMA_C0CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C0CONFIG: FLOWCNTRL Position */ -#define GPDMA_C0CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C0CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C0CONFIG: FLOWCNTRL Mask */ -#define GPDMA_C0CONFIG_IE_Pos 14 /*!< GPDMA C0CONFIG: IE Position */ -#define GPDMA_C0CONFIG_IE_Msk (0x01UL << GPDMA_C0CONFIG_IE_Pos) /*!< GPDMA C0CONFIG: IE Mask */ -#define GPDMA_C0CONFIG_ITC_Pos 15 /*!< GPDMA C0CONFIG: ITC Position */ -#define GPDMA_C0CONFIG_ITC_Msk (0x01UL << GPDMA_C0CONFIG_ITC_Pos) /*!< GPDMA C0CONFIG: ITC Mask */ -#define GPDMA_C0CONFIG_L_Pos 16 /*!< GPDMA C0CONFIG: L Position */ -#define GPDMA_C0CONFIG_L_Msk (0x01UL << GPDMA_C0CONFIG_L_Pos) /*!< GPDMA C0CONFIG: L Mask */ -#define GPDMA_C0CONFIG_A_Pos 17 /*!< GPDMA C0CONFIG: A Position */ -#define GPDMA_C0CONFIG_A_Msk (0x01UL << GPDMA_C0CONFIG_A_Pos) /*!< GPDMA C0CONFIG: A Mask */ -#define GPDMA_C0CONFIG_H_Pos 18 /*!< GPDMA C0CONFIG: H Position */ -#define GPDMA_C0CONFIG_H_Msk (0x01UL << GPDMA_C0CONFIG_H_Pos) /*!< GPDMA C0CONFIG: H Mask */ - -// ------------------------------------- GPDMA_C1SRCADDR ---------------------------------------- -#define GPDMA_C1SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C1SRCADDR: SRCADDR Position */ -#define GPDMA_C1SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C1SRCADDR_SRCADDR_Pos) /*!< GPDMA C1SRCADDR: SRCADDR Mask */ - -// ------------------------------------ GPDMA_C1DESTADDR ---------------------------------------- -#define GPDMA_C1DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C1DESTADDR: DESTADDR Position */ -#define GPDMA_C1DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C1DESTADDR_DESTADDR_Pos) /*!< GPDMA C1DESTADDR: DESTADDR Mask */ - -// --------------------------------------- GPDMA_C1LLI ------------------------------------------ -#define GPDMA_C1LLI_LM_Pos 0 /*!< GPDMA C1LLI: LM Position */ -#define GPDMA_C1LLI_LM_Msk (0x01UL << GPDMA_C1LLI_LM_Pos) /*!< GPDMA C1LLI: LM Mask */ -#define GPDMA_C1LLI_R_Pos 1 /*!< GPDMA C1LLI: R Position */ -#define GPDMA_C1LLI_R_Msk (0x01UL << GPDMA_C1LLI_R_Pos) /*!< GPDMA C1LLI: R Mask */ -#define GPDMA_C1LLI_LLI_Pos 2 /*!< GPDMA C1LLI: LLI Position */ -#define GPDMA_C1LLI_LLI_Msk (0x3fffffffUL << GPDMA_C1LLI_LLI_Pos) /*!< GPDMA C1LLI: LLI Mask */ - -// ------------------------------------- GPDMA_C1CONTROL ---------------------------------------- -#define GPDMA_C1CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C1CONTROL: TRANSFERSIZE Position */ -#define GPDMA_C1CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C1CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C1CONTROL: TRANSFERSIZE Mask */ -#define GPDMA_C1CONTROL_SBSIZE_Pos 12 /*!< GPDMA C1CONTROL: SBSIZE Position */ -#define GPDMA_C1CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C1CONTROL_SBSIZE_Pos) /*!< GPDMA C1CONTROL: SBSIZE Mask */ -#define GPDMA_C1CONTROL_DBSIZE_Pos 15 /*!< GPDMA C1CONTROL: DBSIZE Position */ -#define GPDMA_C1CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C1CONTROL_DBSIZE_Pos) /*!< GPDMA C1CONTROL: DBSIZE Mask */ -#define GPDMA_C1CONTROL_SWIDTH_Pos 18 /*!< GPDMA C1CONTROL: SWIDTH Position */ -#define GPDMA_C1CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C1CONTROL_SWIDTH_Pos) /*!< GPDMA C1CONTROL: SWIDTH Mask */ -#define GPDMA_C1CONTROL_DWIDTH_Pos 21 /*!< GPDMA C1CONTROL: DWIDTH Position */ -#define GPDMA_C1CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C1CONTROL_DWIDTH_Pos) /*!< GPDMA C1CONTROL: DWIDTH Mask */ -#define GPDMA_C1CONTROL_S_Pos 24 /*!< GPDMA C1CONTROL: S Position */ -#define GPDMA_C1CONTROL_S_Msk (0x01UL << GPDMA_C1CONTROL_S_Pos) /*!< GPDMA C1CONTROL: S Mask */ -#define GPDMA_C1CONTROL_D_Pos 25 /*!< GPDMA C1CONTROL: D Position */ -#define GPDMA_C1CONTROL_D_Msk (0x01UL << GPDMA_C1CONTROL_D_Pos) /*!< GPDMA C1CONTROL: D Mask */ -#define GPDMA_C1CONTROL_SI_Pos 26 /*!< GPDMA C1CONTROL: SI Position */ -#define GPDMA_C1CONTROL_SI_Msk (0x01UL << GPDMA_C1CONTROL_SI_Pos) /*!< GPDMA C1CONTROL: SI Mask */ -#define GPDMA_C1CONTROL_DI_Pos 27 /*!< GPDMA C1CONTROL: DI Position */ -#define GPDMA_C1CONTROL_DI_Msk (0x01UL << GPDMA_C1CONTROL_DI_Pos) /*!< GPDMA C1CONTROL: DI Mask */ -#define GPDMA_C1CONTROL_PROT1_Pos 28 /*!< GPDMA C1CONTROL: PROT1 Position */ -#define GPDMA_C1CONTROL_PROT1_Msk (0x01UL << GPDMA_C1CONTROL_PROT1_Pos) /*!< GPDMA C1CONTROL: PROT1 Mask */ -#define GPDMA_C1CONTROL_PROT2_Pos 29 /*!< GPDMA C1CONTROL: PROT2 Position */ -#define GPDMA_C1CONTROL_PROT2_Msk (0x01UL << GPDMA_C1CONTROL_PROT2_Pos) /*!< GPDMA C1CONTROL: PROT2 Mask */ -#define GPDMA_C1CONTROL_PROT3_Pos 30 /*!< GPDMA C1CONTROL: PROT3 Position */ -#define GPDMA_C1CONTROL_PROT3_Msk (0x01UL << GPDMA_C1CONTROL_PROT3_Pos) /*!< GPDMA C1CONTROL: PROT3 Mask */ -#define GPDMA_C1CONTROL_I_Pos 31 /*!< GPDMA C1CONTROL: I Position */ -#define GPDMA_C1CONTROL_I_Msk (0x01UL << GPDMA_C1CONTROL_I_Pos) /*!< GPDMA C1CONTROL: I Mask */ - -// ------------------------------------- GPDMA_C1CONFIG ----------------------------------------- -#define GPDMA_C1CONFIG_E_Pos 0 /*!< GPDMA C1CONFIG: E Position */ -#define GPDMA_C1CONFIG_E_Msk (0x01UL << GPDMA_C1CONFIG_E_Pos) /*!< GPDMA C1CONFIG: E Mask */ -#define GPDMA_C1CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C1CONFIG: SRCPERIPHERAL Position */ -#define GPDMA_C1CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C1CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C1CONFIG: SRCPERIPHERAL Mask */ -#define GPDMA_C1CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C1CONFIG: DESTPERIPHERAL Position */ -#define GPDMA_C1CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C1CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C1CONFIG: DESTPERIPHERAL Mask */ -#define GPDMA_C1CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C1CONFIG: FLOWCNTRL Position */ -#define GPDMA_C1CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C1CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C1CONFIG: FLOWCNTRL Mask */ -#define GPDMA_C1CONFIG_IE_Pos 14 /*!< GPDMA C1CONFIG: IE Position */ -#define GPDMA_C1CONFIG_IE_Msk (0x01UL << GPDMA_C1CONFIG_IE_Pos) /*!< GPDMA C1CONFIG: IE Mask */ -#define GPDMA_C1CONFIG_ITC_Pos 15 /*!< GPDMA C1CONFIG: ITC Position */ -#define GPDMA_C1CONFIG_ITC_Msk (0x01UL << GPDMA_C1CONFIG_ITC_Pos) /*!< GPDMA C1CONFIG: ITC Mask */ -#define GPDMA_C1CONFIG_L_Pos 16 /*!< GPDMA C1CONFIG: L Position */ -#define GPDMA_C1CONFIG_L_Msk (0x01UL << GPDMA_C1CONFIG_L_Pos) /*!< GPDMA C1CONFIG: L Mask */ -#define GPDMA_C1CONFIG_A_Pos 17 /*!< GPDMA C1CONFIG: A Position */ -#define GPDMA_C1CONFIG_A_Msk (0x01UL << GPDMA_C1CONFIG_A_Pos) /*!< GPDMA C1CONFIG: A Mask */ -#define GPDMA_C1CONFIG_H_Pos 18 /*!< GPDMA C1CONFIG: H Position */ -#define GPDMA_C1CONFIG_H_Msk (0x01UL << GPDMA_C1CONFIG_H_Pos) /*!< GPDMA C1CONFIG: H Mask */ - -// ------------------------------------- GPDMA_C2SRCADDR ---------------------------------------- -#define GPDMA_C2SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C2SRCADDR: SRCADDR Position */ -#define GPDMA_C2SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C2SRCADDR_SRCADDR_Pos) /*!< GPDMA C2SRCADDR: SRCADDR Mask */ - -// ------------------------------------ GPDMA_C2DESTADDR ---------------------------------------- -#define GPDMA_C2DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C2DESTADDR: DESTADDR Position */ -#define GPDMA_C2DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C2DESTADDR_DESTADDR_Pos) /*!< GPDMA C2DESTADDR: DESTADDR Mask */ - -// --------------------------------------- GPDMA_C2LLI ------------------------------------------ -#define GPDMA_C2LLI_LM_Pos 0 /*!< GPDMA C2LLI: LM Position */ -#define GPDMA_C2LLI_LM_Msk (0x01UL << GPDMA_C2LLI_LM_Pos) /*!< GPDMA C2LLI: LM Mask */ -#define GPDMA_C2LLI_R_Pos 1 /*!< GPDMA C2LLI: R Position */ -#define GPDMA_C2LLI_R_Msk (0x01UL << GPDMA_C2LLI_R_Pos) /*!< GPDMA C2LLI: R Mask */ -#define GPDMA_C2LLI_LLI_Pos 2 /*!< GPDMA C2LLI: LLI Position */ -#define GPDMA_C2LLI_LLI_Msk (0x3fffffffUL << GPDMA_C2LLI_LLI_Pos) /*!< GPDMA C2LLI: LLI Mask */ - -// ------------------------------------- GPDMA_C2CONTROL ---------------------------------------- -#define GPDMA_C2CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C2CONTROL: TRANSFERSIZE Position */ -#define GPDMA_C2CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C2CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C2CONTROL: TRANSFERSIZE Mask */ -#define GPDMA_C2CONTROL_SBSIZE_Pos 12 /*!< GPDMA C2CONTROL: SBSIZE Position */ -#define GPDMA_C2CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C2CONTROL_SBSIZE_Pos) /*!< GPDMA C2CONTROL: SBSIZE Mask */ -#define GPDMA_C2CONTROL_DBSIZE_Pos 15 /*!< GPDMA C2CONTROL: DBSIZE Position */ -#define GPDMA_C2CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C2CONTROL_DBSIZE_Pos) /*!< GPDMA C2CONTROL: DBSIZE Mask */ -#define GPDMA_C2CONTROL_SWIDTH_Pos 18 /*!< GPDMA C2CONTROL: SWIDTH Position */ -#define GPDMA_C2CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C2CONTROL_SWIDTH_Pos) /*!< GPDMA C2CONTROL: SWIDTH Mask */ -#define GPDMA_C2CONTROL_DWIDTH_Pos 21 /*!< GPDMA C2CONTROL: DWIDTH Position */ -#define GPDMA_C2CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C2CONTROL_DWIDTH_Pos) /*!< GPDMA C2CONTROL: DWIDTH Mask */ -#define GPDMA_C2CONTROL_S_Pos 24 /*!< GPDMA C2CONTROL: S Position */ -#define GPDMA_C2CONTROL_S_Msk (0x01UL << GPDMA_C2CONTROL_S_Pos) /*!< GPDMA C2CONTROL: S Mask */ -#define GPDMA_C2CONTROL_D_Pos 25 /*!< GPDMA C2CONTROL: D Position */ -#define GPDMA_C2CONTROL_D_Msk (0x01UL << GPDMA_C2CONTROL_D_Pos) /*!< GPDMA C2CONTROL: D Mask */ -#define GPDMA_C2CONTROL_SI_Pos 26 /*!< GPDMA C2CONTROL: SI Position */ -#define GPDMA_C2CONTROL_SI_Msk (0x01UL << GPDMA_C2CONTROL_SI_Pos) /*!< GPDMA C2CONTROL: SI Mask */ -#define GPDMA_C2CONTROL_DI_Pos 27 /*!< GPDMA C2CONTROL: DI Position */ -#define GPDMA_C2CONTROL_DI_Msk (0x01UL << GPDMA_C2CONTROL_DI_Pos) /*!< GPDMA C2CONTROL: DI Mask */ -#define GPDMA_C2CONTROL_PROT1_Pos 28 /*!< GPDMA C2CONTROL: PROT1 Position */ -#define GPDMA_C2CONTROL_PROT1_Msk (0x01UL << GPDMA_C2CONTROL_PROT1_Pos) /*!< GPDMA C2CONTROL: PROT1 Mask */ -#define GPDMA_C2CONTROL_PROT2_Pos 29 /*!< GPDMA C2CONTROL: PROT2 Position */ -#define GPDMA_C2CONTROL_PROT2_Msk (0x01UL << GPDMA_C2CONTROL_PROT2_Pos) /*!< GPDMA C2CONTROL: PROT2 Mask */ -#define GPDMA_C2CONTROL_PROT3_Pos 30 /*!< GPDMA C2CONTROL: PROT3 Position */ -#define GPDMA_C2CONTROL_PROT3_Msk (0x01UL << GPDMA_C2CONTROL_PROT3_Pos) /*!< GPDMA C2CONTROL: PROT3 Mask */ -#define GPDMA_C2CONTROL_I_Pos 31 /*!< GPDMA C2CONTROL: I Position */ -#define GPDMA_C2CONTROL_I_Msk (0x01UL << GPDMA_C2CONTROL_I_Pos) /*!< GPDMA C2CONTROL: I Mask */ - -// ------------------------------------- GPDMA_C2CONFIG ----------------------------------------- -#define GPDMA_C2CONFIG_E_Pos 0 /*!< GPDMA C2CONFIG: E Position */ -#define GPDMA_C2CONFIG_E_Msk (0x01UL << GPDMA_C2CONFIG_E_Pos) /*!< GPDMA C2CONFIG: E Mask */ -#define GPDMA_C2CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C2CONFIG: SRCPERIPHERAL Position */ -#define GPDMA_C2CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C2CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C2CONFIG: SRCPERIPHERAL Mask */ -#define GPDMA_C2CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C2CONFIG: DESTPERIPHERAL Position */ -#define GPDMA_C2CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C2CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C2CONFIG: DESTPERIPHERAL Mask */ -#define GPDMA_C2CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C2CONFIG: FLOWCNTRL Position */ -#define GPDMA_C2CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C2CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C2CONFIG: FLOWCNTRL Mask */ -#define GPDMA_C2CONFIG_IE_Pos 14 /*!< GPDMA C2CONFIG: IE Position */ -#define GPDMA_C2CONFIG_IE_Msk (0x01UL << GPDMA_C2CONFIG_IE_Pos) /*!< GPDMA C2CONFIG: IE Mask */ -#define GPDMA_C2CONFIG_ITC_Pos 15 /*!< GPDMA C2CONFIG: ITC Position */ -#define GPDMA_C2CONFIG_ITC_Msk (0x01UL << GPDMA_C2CONFIG_ITC_Pos) /*!< GPDMA C2CONFIG: ITC Mask */ -#define GPDMA_C2CONFIG_L_Pos 16 /*!< GPDMA C2CONFIG: L Position */ -#define GPDMA_C2CONFIG_L_Msk (0x01UL << GPDMA_C2CONFIG_L_Pos) /*!< GPDMA C2CONFIG: L Mask */ -#define GPDMA_C2CONFIG_A_Pos 17 /*!< GPDMA C2CONFIG: A Position */ -#define GPDMA_C2CONFIG_A_Msk (0x01UL << GPDMA_C2CONFIG_A_Pos) /*!< GPDMA C2CONFIG: A Mask */ -#define GPDMA_C2CONFIG_H_Pos 18 /*!< GPDMA C2CONFIG: H Position */ -#define GPDMA_C2CONFIG_H_Msk (0x01UL << GPDMA_C2CONFIG_H_Pos) /*!< GPDMA C2CONFIG: H Mask */ - -// ------------------------------------- GPDMA_C3SRCADDR ---------------------------------------- -#define GPDMA_C3SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C3SRCADDR: SRCADDR Position */ -#define GPDMA_C3SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C3SRCADDR_SRCADDR_Pos) /*!< GPDMA C3SRCADDR: SRCADDR Mask */ - -// ------------------------------------ GPDMA_C3DESTADDR ---------------------------------------- -#define GPDMA_C3DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C3DESTADDR: DESTADDR Position */ -#define GPDMA_C3DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C3DESTADDR_DESTADDR_Pos) /*!< GPDMA C3DESTADDR: DESTADDR Mask */ - -// --------------------------------------- GPDMA_C3LLI ------------------------------------------ -#define GPDMA_C3LLI_LM_Pos 0 /*!< GPDMA C3LLI: LM Position */ -#define GPDMA_C3LLI_LM_Msk (0x01UL << GPDMA_C3LLI_LM_Pos) /*!< GPDMA C3LLI: LM Mask */ -#define GPDMA_C3LLI_R_Pos 1 /*!< GPDMA C3LLI: R Position */ -#define GPDMA_C3LLI_R_Msk (0x01UL << GPDMA_C3LLI_R_Pos) /*!< GPDMA C3LLI: R Mask */ -#define GPDMA_C3LLI_LLI_Pos 2 /*!< GPDMA C3LLI: LLI Position */ -#define GPDMA_C3LLI_LLI_Msk (0x3fffffffUL << GPDMA_C3LLI_LLI_Pos) /*!< GPDMA C3LLI: LLI Mask */ - -// ------------------------------------- GPDMA_C3CONTROL ---------------------------------------- -#define GPDMA_C3CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C3CONTROL: TRANSFERSIZE Position */ -#define GPDMA_C3CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C3CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C3CONTROL: TRANSFERSIZE Mask */ -#define GPDMA_C3CONTROL_SBSIZE_Pos 12 /*!< GPDMA C3CONTROL: SBSIZE Position */ -#define GPDMA_C3CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C3CONTROL_SBSIZE_Pos) /*!< GPDMA C3CONTROL: SBSIZE Mask */ -#define GPDMA_C3CONTROL_DBSIZE_Pos 15 /*!< GPDMA C3CONTROL: DBSIZE Position */ -#define GPDMA_C3CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C3CONTROL_DBSIZE_Pos) /*!< GPDMA C3CONTROL: DBSIZE Mask */ -#define GPDMA_C3CONTROL_SWIDTH_Pos 18 /*!< GPDMA C3CONTROL: SWIDTH Position */ -#define GPDMA_C3CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C3CONTROL_SWIDTH_Pos) /*!< GPDMA C3CONTROL: SWIDTH Mask */ -#define GPDMA_C3CONTROL_DWIDTH_Pos 21 /*!< GPDMA C3CONTROL: DWIDTH Position */ -#define GPDMA_C3CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C3CONTROL_DWIDTH_Pos) /*!< GPDMA C3CONTROL: DWIDTH Mask */ -#define GPDMA_C3CONTROL_S_Pos 24 /*!< GPDMA C3CONTROL: S Position */ -#define GPDMA_C3CONTROL_S_Msk (0x01UL << GPDMA_C3CONTROL_S_Pos) /*!< GPDMA C3CONTROL: S Mask */ -#define GPDMA_C3CONTROL_D_Pos 25 /*!< GPDMA C3CONTROL: D Position */ -#define GPDMA_C3CONTROL_D_Msk (0x01UL << GPDMA_C3CONTROL_D_Pos) /*!< GPDMA C3CONTROL: D Mask */ -#define GPDMA_C3CONTROL_SI_Pos 26 /*!< GPDMA C3CONTROL: SI Position */ -#define GPDMA_C3CONTROL_SI_Msk (0x01UL << GPDMA_C3CONTROL_SI_Pos) /*!< GPDMA C3CONTROL: SI Mask */ -#define GPDMA_C3CONTROL_DI_Pos 27 /*!< GPDMA C3CONTROL: DI Position */ -#define GPDMA_C3CONTROL_DI_Msk (0x01UL << GPDMA_C3CONTROL_DI_Pos) /*!< GPDMA C3CONTROL: DI Mask */ -#define GPDMA_C3CONTROL_PROT1_Pos 28 /*!< GPDMA C3CONTROL: PROT1 Position */ -#define GPDMA_C3CONTROL_PROT1_Msk (0x01UL << GPDMA_C3CONTROL_PROT1_Pos) /*!< GPDMA C3CONTROL: PROT1 Mask */ -#define GPDMA_C3CONTROL_PROT2_Pos 29 /*!< GPDMA C3CONTROL: PROT2 Position */ -#define GPDMA_C3CONTROL_PROT2_Msk (0x01UL << GPDMA_C3CONTROL_PROT2_Pos) /*!< GPDMA C3CONTROL: PROT2 Mask */ -#define GPDMA_C3CONTROL_PROT3_Pos 30 /*!< GPDMA C3CONTROL: PROT3 Position */ -#define GPDMA_C3CONTROL_PROT3_Msk (0x01UL << GPDMA_C3CONTROL_PROT3_Pos) /*!< GPDMA C3CONTROL: PROT3 Mask */ -#define GPDMA_C3CONTROL_I_Pos 31 /*!< GPDMA C3CONTROL: I Position */ -#define GPDMA_C3CONTROL_I_Msk (0x01UL << GPDMA_C3CONTROL_I_Pos) /*!< GPDMA C3CONTROL: I Mask */ - -// ------------------------------------- GPDMA_C3CONFIG ----------------------------------------- -#define GPDMA_C3CONFIG_E_Pos 0 /*!< GPDMA C3CONFIG: E Position */ -#define GPDMA_C3CONFIG_E_Msk (0x01UL << GPDMA_C3CONFIG_E_Pos) /*!< GPDMA C3CONFIG: E Mask */ -#define GPDMA_C3CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C3CONFIG: SRCPERIPHERAL Position */ -#define GPDMA_C3CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C3CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C3CONFIG: SRCPERIPHERAL Mask */ -#define GPDMA_C3CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C3CONFIG: DESTPERIPHERAL Position */ -#define GPDMA_C3CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C3CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C3CONFIG: DESTPERIPHERAL Mask */ -#define GPDMA_C3CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C3CONFIG: FLOWCNTRL Position */ -#define GPDMA_C3CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C3CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C3CONFIG: FLOWCNTRL Mask */ -#define GPDMA_C3CONFIG_IE_Pos 14 /*!< GPDMA C3CONFIG: IE Position */ -#define GPDMA_C3CONFIG_IE_Msk (0x01UL << GPDMA_C3CONFIG_IE_Pos) /*!< GPDMA C3CONFIG: IE Mask */ -#define GPDMA_C3CONFIG_ITC_Pos 15 /*!< GPDMA C3CONFIG: ITC Position */ -#define GPDMA_C3CONFIG_ITC_Msk (0x01UL << GPDMA_C3CONFIG_ITC_Pos) /*!< GPDMA C3CONFIG: ITC Mask */ -#define GPDMA_C3CONFIG_L_Pos 16 /*!< GPDMA C3CONFIG: L Position */ -#define GPDMA_C3CONFIG_L_Msk (0x01UL << GPDMA_C3CONFIG_L_Pos) /*!< GPDMA C3CONFIG: L Mask */ -#define GPDMA_C3CONFIG_A_Pos 17 /*!< GPDMA C3CONFIG: A Position */ -#define GPDMA_C3CONFIG_A_Msk (0x01UL << GPDMA_C3CONFIG_A_Pos) /*!< GPDMA C3CONFIG: A Mask */ -#define GPDMA_C3CONFIG_H_Pos 18 /*!< GPDMA C3CONFIG: H Position */ -#define GPDMA_C3CONFIG_H_Msk (0x01UL << GPDMA_C3CONFIG_H_Pos) /*!< GPDMA C3CONFIG: H Mask */ - -// ------------------------------------- GPDMA_C4SRCADDR ---------------------------------------- -#define GPDMA_C4SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C4SRCADDR: SRCADDR Position */ -#define GPDMA_C4SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C4SRCADDR_SRCADDR_Pos) /*!< GPDMA C4SRCADDR: SRCADDR Mask */ - -// ------------------------------------ GPDMA_C4DESTADDR ---------------------------------------- -#define GPDMA_C4DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C4DESTADDR: DESTADDR Position */ -#define GPDMA_C4DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C4DESTADDR_DESTADDR_Pos) /*!< GPDMA C4DESTADDR: DESTADDR Mask */ - -// --------------------------------------- GPDMA_C4LLI ------------------------------------------ -#define GPDMA_C4LLI_LM_Pos 0 /*!< GPDMA C4LLI: LM Position */ -#define GPDMA_C4LLI_LM_Msk (0x01UL << GPDMA_C4LLI_LM_Pos) /*!< GPDMA C4LLI: LM Mask */ -#define GPDMA_C4LLI_R_Pos 1 /*!< GPDMA C4LLI: R Position */ -#define GPDMA_C4LLI_R_Msk (0x01UL << GPDMA_C4LLI_R_Pos) /*!< GPDMA C4LLI: R Mask */ -#define GPDMA_C4LLI_LLI_Pos 2 /*!< GPDMA C4LLI: LLI Position */ -#define GPDMA_C4LLI_LLI_Msk (0x3fffffffUL << GPDMA_C4LLI_LLI_Pos) /*!< GPDMA C4LLI: LLI Mask */ - -// ------------------------------------- GPDMA_C4CONTROL ---------------------------------------- -#define GPDMA_C4CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C4CONTROL: TRANSFERSIZE Position */ -#define GPDMA_C4CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C4CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C4CONTROL: TRANSFERSIZE Mask */ -#define GPDMA_C4CONTROL_SBSIZE_Pos 12 /*!< GPDMA C4CONTROL: SBSIZE Position */ -#define GPDMA_C4CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C4CONTROL_SBSIZE_Pos) /*!< GPDMA C4CONTROL: SBSIZE Mask */ -#define GPDMA_C4CONTROL_DBSIZE_Pos 15 /*!< GPDMA C4CONTROL: DBSIZE Position */ -#define GPDMA_C4CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C4CONTROL_DBSIZE_Pos) /*!< GPDMA C4CONTROL: DBSIZE Mask */ -#define GPDMA_C4CONTROL_SWIDTH_Pos 18 /*!< GPDMA C4CONTROL: SWIDTH Position */ -#define GPDMA_C4CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C4CONTROL_SWIDTH_Pos) /*!< GPDMA C4CONTROL: SWIDTH Mask */ -#define GPDMA_C4CONTROL_DWIDTH_Pos 21 /*!< GPDMA C4CONTROL: DWIDTH Position */ -#define GPDMA_C4CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C4CONTROL_DWIDTH_Pos) /*!< GPDMA C4CONTROL: DWIDTH Mask */ -#define GPDMA_C4CONTROL_S_Pos 24 /*!< GPDMA C4CONTROL: S Position */ -#define GPDMA_C4CONTROL_S_Msk (0x01UL << GPDMA_C4CONTROL_S_Pos) /*!< GPDMA C4CONTROL: S Mask */ -#define GPDMA_C4CONTROL_D_Pos 25 /*!< GPDMA C4CONTROL: D Position */ -#define GPDMA_C4CONTROL_D_Msk (0x01UL << GPDMA_C4CONTROL_D_Pos) /*!< GPDMA C4CONTROL: D Mask */ -#define GPDMA_C4CONTROL_SI_Pos 26 /*!< GPDMA C4CONTROL: SI Position */ -#define GPDMA_C4CONTROL_SI_Msk (0x01UL << GPDMA_C4CONTROL_SI_Pos) /*!< GPDMA C4CONTROL: SI Mask */ -#define GPDMA_C4CONTROL_DI_Pos 27 /*!< GPDMA C4CONTROL: DI Position */ -#define GPDMA_C4CONTROL_DI_Msk (0x01UL << GPDMA_C4CONTROL_DI_Pos) /*!< GPDMA C4CONTROL: DI Mask */ -#define GPDMA_C4CONTROL_PROT1_Pos 28 /*!< GPDMA C4CONTROL: PROT1 Position */ -#define GPDMA_C4CONTROL_PROT1_Msk (0x01UL << GPDMA_C4CONTROL_PROT1_Pos) /*!< GPDMA C4CONTROL: PROT1 Mask */ -#define GPDMA_C4CONTROL_PROT2_Pos 29 /*!< GPDMA C4CONTROL: PROT2 Position */ -#define GPDMA_C4CONTROL_PROT2_Msk (0x01UL << GPDMA_C4CONTROL_PROT2_Pos) /*!< GPDMA C4CONTROL: PROT2 Mask */ -#define GPDMA_C4CONTROL_PROT3_Pos 30 /*!< GPDMA C4CONTROL: PROT3 Position */ -#define GPDMA_C4CONTROL_PROT3_Msk (0x01UL << GPDMA_C4CONTROL_PROT3_Pos) /*!< GPDMA C4CONTROL: PROT3 Mask */ -#define GPDMA_C4CONTROL_I_Pos 31 /*!< GPDMA C4CONTROL: I Position */ -#define GPDMA_C4CONTROL_I_Msk (0x01UL << GPDMA_C4CONTROL_I_Pos) /*!< GPDMA C4CONTROL: I Mask */ - -// ------------------------------------- GPDMA_C4CONFIG ----------------------------------------- -#define GPDMA_C4CONFIG_E_Pos 0 /*!< GPDMA C4CONFIG: E Position */ -#define GPDMA_C4CONFIG_E_Msk (0x01UL << GPDMA_C4CONFIG_E_Pos) /*!< GPDMA C4CONFIG: E Mask */ -#define GPDMA_C4CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C4CONFIG: SRCPERIPHERAL Position */ -#define GPDMA_C4CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C4CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C4CONFIG: SRCPERIPHERAL Mask */ -#define GPDMA_C4CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C4CONFIG: DESTPERIPHERAL Position */ -#define GPDMA_C4CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C4CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C4CONFIG: DESTPERIPHERAL Mask */ -#define GPDMA_C4CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C4CONFIG: FLOWCNTRL Position */ -#define GPDMA_C4CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C4CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C4CONFIG: FLOWCNTRL Mask */ -#define GPDMA_C4CONFIG_IE_Pos 14 /*!< GPDMA C4CONFIG: IE Position */ -#define GPDMA_C4CONFIG_IE_Msk (0x01UL << GPDMA_C4CONFIG_IE_Pos) /*!< GPDMA C4CONFIG: IE Mask */ -#define GPDMA_C4CONFIG_ITC_Pos 15 /*!< GPDMA C4CONFIG: ITC Position */ -#define GPDMA_C4CONFIG_ITC_Msk (0x01UL << GPDMA_C4CONFIG_ITC_Pos) /*!< GPDMA C4CONFIG: ITC Mask */ -#define GPDMA_C4CONFIG_L_Pos 16 /*!< GPDMA C4CONFIG: L Position */ -#define GPDMA_C4CONFIG_L_Msk (0x01UL << GPDMA_C4CONFIG_L_Pos) /*!< GPDMA C4CONFIG: L Mask */ -#define GPDMA_C4CONFIG_A_Pos 17 /*!< GPDMA C4CONFIG: A Position */ -#define GPDMA_C4CONFIG_A_Msk (0x01UL << GPDMA_C4CONFIG_A_Pos) /*!< GPDMA C4CONFIG: A Mask */ -#define GPDMA_C4CONFIG_H_Pos 18 /*!< GPDMA C4CONFIG: H Position */ -#define GPDMA_C4CONFIG_H_Msk (0x01UL << GPDMA_C4CONFIG_H_Pos) /*!< GPDMA C4CONFIG: H Mask */ - -// ------------------------------------- GPDMA_C5SRCADDR ---------------------------------------- -#define GPDMA_C5SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C5SRCADDR: SRCADDR Position */ -#define GPDMA_C5SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C5SRCADDR_SRCADDR_Pos) /*!< GPDMA C5SRCADDR: SRCADDR Mask */ - -// ------------------------------------ GPDMA_C5DESTADDR ---------------------------------------- -#define GPDMA_C5DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C5DESTADDR: DESTADDR Position */ -#define GPDMA_C5DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C5DESTADDR_DESTADDR_Pos) /*!< GPDMA C5DESTADDR: DESTADDR Mask */ - -// --------------------------------------- GPDMA_C5LLI ------------------------------------------ -#define GPDMA_C5LLI_LM_Pos 0 /*!< GPDMA C5LLI: LM Position */ -#define GPDMA_C5LLI_LM_Msk (0x01UL << GPDMA_C5LLI_LM_Pos) /*!< GPDMA C5LLI: LM Mask */ -#define GPDMA_C5LLI_R_Pos 1 /*!< GPDMA C5LLI: R Position */ -#define GPDMA_C5LLI_R_Msk (0x01UL << GPDMA_C5LLI_R_Pos) /*!< GPDMA C5LLI: R Mask */ -#define GPDMA_C5LLI_LLI_Pos 2 /*!< GPDMA C5LLI: LLI Position */ -#define GPDMA_C5LLI_LLI_Msk (0x3fffffffUL << GPDMA_C5LLI_LLI_Pos) /*!< GPDMA C5LLI: LLI Mask */ - -// ------------------------------------- GPDMA_C5CONTROL ---------------------------------------- -#define GPDMA_C5CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C5CONTROL: TRANSFERSIZE Position */ -#define GPDMA_C5CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C5CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C5CONTROL: TRANSFERSIZE Mask */ -#define GPDMA_C5CONTROL_SBSIZE_Pos 12 /*!< GPDMA C5CONTROL: SBSIZE Position */ -#define GPDMA_C5CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C5CONTROL_SBSIZE_Pos) /*!< GPDMA C5CONTROL: SBSIZE Mask */ -#define GPDMA_C5CONTROL_DBSIZE_Pos 15 /*!< GPDMA C5CONTROL: DBSIZE Position */ -#define GPDMA_C5CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C5CONTROL_DBSIZE_Pos) /*!< GPDMA C5CONTROL: DBSIZE Mask */ -#define GPDMA_C5CONTROL_SWIDTH_Pos 18 /*!< GPDMA C5CONTROL: SWIDTH Position */ -#define GPDMA_C5CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C5CONTROL_SWIDTH_Pos) /*!< GPDMA C5CONTROL: SWIDTH Mask */ -#define GPDMA_C5CONTROL_DWIDTH_Pos 21 /*!< GPDMA C5CONTROL: DWIDTH Position */ -#define GPDMA_C5CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C5CONTROL_DWIDTH_Pos) /*!< GPDMA C5CONTROL: DWIDTH Mask */ -#define GPDMA_C5CONTROL_S_Pos 24 /*!< GPDMA C5CONTROL: S Position */ -#define GPDMA_C5CONTROL_S_Msk (0x01UL << GPDMA_C5CONTROL_S_Pos) /*!< GPDMA C5CONTROL: S Mask */ -#define GPDMA_C5CONTROL_D_Pos 25 /*!< GPDMA C5CONTROL: D Position */ -#define GPDMA_C5CONTROL_D_Msk (0x01UL << GPDMA_C5CONTROL_D_Pos) /*!< GPDMA C5CONTROL: D Mask */ -#define GPDMA_C5CONTROL_SI_Pos 26 /*!< GPDMA C5CONTROL: SI Position */ -#define GPDMA_C5CONTROL_SI_Msk (0x01UL << GPDMA_C5CONTROL_SI_Pos) /*!< GPDMA C5CONTROL: SI Mask */ -#define GPDMA_C5CONTROL_DI_Pos 27 /*!< GPDMA C5CONTROL: DI Position */ -#define GPDMA_C5CONTROL_DI_Msk (0x01UL << GPDMA_C5CONTROL_DI_Pos) /*!< GPDMA C5CONTROL: DI Mask */ -#define GPDMA_C5CONTROL_PROT1_Pos 28 /*!< GPDMA C5CONTROL: PROT1 Position */ -#define GPDMA_C5CONTROL_PROT1_Msk (0x01UL << GPDMA_C5CONTROL_PROT1_Pos) /*!< GPDMA C5CONTROL: PROT1 Mask */ -#define GPDMA_C5CONTROL_PROT2_Pos 29 /*!< GPDMA C5CONTROL: PROT2 Position */ -#define GPDMA_C5CONTROL_PROT2_Msk (0x01UL << GPDMA_C5CONTROL_PROT2_Pos) /*!< GPDMA C5CONTROL: PROT2 Mask */ -#define GPDMA_C5CONTROL_PROT3_Pos 30 /*!< GPDMA C5CONTROL: PROT3 Position */ -#define GPDMA_C5CONTROL_PROT3_Msk (0x01UL << GPDMA_C5CONTROL_PROT3_Pos) /*!< GPDMA C5CONTROL: PROT3 Mask */ -#define GPDMA_C5CONTROL_I_Pos 31 /*!< GPDMA C5CONTROL: I Position */ -#define GPDMA_C5CONTROL_I_Msk (0x01UL << GPDMA_C5CONTROL_I_Pos) /*!< GPDMA C5CONTROL: I Mask */ - -// ------------------------------------- GPDMA_C5CONFIG ----------------------------------------- -#define GPDMA_C5CONFIG_E_Pos 0 /*!< GPDMA C5CONFIG: E Position */ -#define GPDMA_C5CONFIG_E_Msk (0x01UL << GPDMA_C5CONFIG_E_Pos) /*!< GPDMA C5CONFIG: E Mask */ -#define GPDMA_C5CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C5CONFIG: SRCPERIPHERAL Position */ -#define GPDMA_C5CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C5CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C5CONFIG: SRCPERIPHERAL Mask */ -#define GPDMA_C5CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C5CONFIG: DESTPERIPHERAL Position */ -#define GPDMA_C5CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C5CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C5CONFIG: DESTPERIPHERAL Mask */ -#define GPDMA_C5CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C5CONFIG: FLOWCNTRL Position */ -#define GPDMA_C5CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C5CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C5CONFIG: FLOWCNTRL Mask */ -#define GPDMA_C5CONFIG_IE_Pos 14 /*!< GPDMA C5CONFIG: IE Position */ -#define GPDMA_C5CONFIG_IE_Msk (0x01UL << GPDMA_C5CONFIG_IE_Pos) /*!< GPDMA C5CONFIG: IE Mask */ -#define GPDMA_C5CONFIG_ITC_Pos 15 /*!< GPDMA C5CONFIG: ITC Position */ -#define GPDMA_C5CONFIG_ITC_Msk (0x01UL << GPDMA_C5CONFIG_ITC_Pos) /*!< GPDMA C5CONFIG: ITC Mask */ -#define GPDMA_C5CONFIG_L_Pos 16 /*!< GPDMA C5CONFIG: L Position */ -#define GPDMA_C5CONFIG_L_Msk (0x01UL << GPDMA_C5CONFIG_L_Pos) /*!< GPDMA C5CONFIG: L Mask */ -#define GPDMA_C5CONFIG_A_Pos 17 /*!< GPDMA C5CONFIG: A Position */ -#define GPDMA_C5CONFIG_A_Msk (0x01UL << GPDMA_C5CONFIG_A_Pos) /*!< GPDMA C5CONFIG: A Mask */ -#define GPDMA_C5CONFIG_H_Pos 18 /*!< GPDMA C5CONFIG: H Position */ -#define GPDMA_C5CONFIG_H_Msk (0x01UL << GPDMA_C5CONFIG_H_Pos) /*!< GPDMA C5CONFIG: H Mask */ - -// ------------------------------------- GPDMA_C6SRCADDR ---------------------------------------- -#define GPDMA_C6SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C6SRCADDR: SRCADDR Position */ -#define GPDMA_C6SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C6SRCADDR_SRCADDR_Pos) /*!< GPDMA C6SRCADDR: SRCADDR Mask */ - -// ------------------------------------ GPDMA_C6DESTADDR ---------------------------------------- -#define GPDMA_C6DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C6DESTADDR: DESTADDR Position */ -#define GPDMA_C6DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C6DESTADDR_DESTADDR_Pos) /*!< GPDMA C6DESTADDR: DESTADDR Mask */ - -// --------------------------------------- GPDMA_C6LLI ------------------------------------------ -#define GPDMA_C6LLI_LM_Pos 0 /*!< GPDMA C6LLI: LM Position */ -#define GPDMA_C6LLI_LM_Msk (0x01UL << GPDMA_C6LLI_LM_Pos) /*!< GPDMA C6LLI: LM Mask */ -#define GPDMA_C6LLI_R_Pos 1 /*!< GPDMA C6LLI: R Position */ -#define GPDMA_C6LLI_R_Msk (0x01UL << GPDMA_C6LLI_R_Pos) /*!< GPDMA C6LLI: R Mask */ -#define GPDMA_C6LLI_LLI_Pos 2 /*!< GPDMA C6LLI: LLI Position */ -#define GPDMA_C6LLI_LLI_Msk (0x3fffffffUL << GPDMA_C6LLI_LLI_Pos) /*!< GPDMA C6LLI: LLI Mask */ - -// ------------------------------------- GPDMA_C6CONTROL ---------------------------------------- -#define GPDMA_C6CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C6CONTROL: TRANSFERSIZE Position */ -#define GPDMA_C6CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C6CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C6CONTROL: TRANSFERSIZE Mask */ -#define GPDMA_C6CONTROL_SBSIZE_Pos 12 /*!< GPDMA C6CONTROL: SBSIZE Position */ -#define GPDMA_C6CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C6CONTROL_SBSIZE_Pos) /*!< GPDMA C6CONTROL: SBSIZE Mask */ -#define GPDMA_C6CONTROL_DBSIZE_Pos 15 /*!< GPDMA C6CONTROL: DBSIZE Position */ -#define GPDMA_C6CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C6CONTROL_DBSIZE_Pos) /*!< GPDMA C6CONTROL: DBSIZE Mask */ -#define GPDMA_C6CONTROL_SWIDTH_Pos 18 /*!< GPDMA C6CONTROL: SWIDTH Position */ -#define GPDMA_C6CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C6CONTROL_SWIDTH_Pos) /*!< GPDMA C6CONTROL: SWIDTH Mask */ -#define GPDMA_C6CONTROL_DWIDTH_Pos 21 /*!< GPDMA C6CONTROL: DWIDTH Position */ -#define GPDMA_C6CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C6CONTROL_DWIDTH_Pos) /*!< GPDMA C6CONTROL: DWIDTH Mask */ -#define GPDMA_C6CONTROL_S_Pos 24 /*!< GPDMA C6CONTROL: S Position */ -#define GPDMA_C6CONTROL_S_Msk (0x01UL << GPDMA_C6CONTROL_S_Pos) /*!< GPDMA C6CONTROL: S Mask */ -#define GPDMA_C6CONTROL_D_Pos 25 /*!< GPDMA C6CONTROL: D Position */ -#define GPDMA_C6CONTROL_D_Msk (0x01UL << GPDMA_C6CONTROL_D_Pos) /*!< GPDMA C6CONTROL: D Mask */ -#define GPDMA_C6CONTROL_SI_Pos 26 /*!< GPDMA C6CONTROL: SI Position */ -#define GPDMA_C6CONTROL_SI_Msk (0x01UL << GPDMA_C6CONTROL_SI_Pos) /*!< GPDMA C6CONTROL: SI Mask */ -#define GPDMA_C6CONTROL_DI_Pos 27 /*!< GPDMA C6CONTROL: DI Position */ -#define GPDMA_C6CONTROL_DI_Msk (0x01UL << GPDMA_C6CONTROL_DI_Pos) /*!< GPDMA C6CONTROL: DI Mask */ -#define GPDMA_C6CONTROL_PROT1_Pos 28 /*!< GPDMA C6CONTROL: PROT1 Position */ -#define GPDMA_C6CONTROL_PROT1_Msk (0x01UL << GPDMA_C6CONTROL_PROT1_Pos) /*!< GPDMA C6CONTROL: PROT1 Mask */ -#define GPDMA_C6CONTROL_PROT2_Pos 29 /*!< GPDMA C6CONTROL: PROT2 Position */ -#define GPDMA_C6CONTROL_PROT2_Msk (0x01UL << GPDMA_C6CONTROL_PROT2_Pos) /*!< GPDMA C6CONTROL: PROT2 Mask */ -#define GPDMA_C6CONTROL_PROT3_Pos 30 /*!< GPDMA C6CONTROL: PROT3 Position */ -#define GPDMA_C6CONTROL_PROT3_Msk (0x01UL << GPDMA_C6CONTROL_PROT3_Pos) /*!< GPDMA C6CONTROL: PROT3 Mask */ -#define GPDMA_C6CONTROL_I_Pos 31 /*!< GPDMA C6CONTROL: I Position */ -#define GPDMA_C6CONTROL_I_Msk (0x01UL << GPDMA_C6CONTROL_I_Pos) /*!< GPDMA C6CONTROL: I Mask */ - -// ------------------------------------- GPDMA_C6CONFIG ----------------------------------------- -#define GPDMA_C6CONFIG_E_Pos 0 /*!< GPDMA C6CONFIG: E Position */ -#define GPDMA_C6CONFIG_E_Msk (0x01UL << GPDMA_C6CONFIG_E_Pos) /*!< GPDMA C6CONFIG: E Mask */ -#define GPDMA_C6CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C6CONFIG: SRCPERIPHERAL Position */ -#define GPDMA_C6CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C6CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C6CONFIG: SRCPERIPHERAL Mask */ -#define GPDMA_C6CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C6CONFIG: DESTPERIPHERAL Position */ -#define GPDMA_C6CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C6CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C6CONFIG: DESTPERIPHERAL Mask */ -#define GPDMA_C6CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C6CONFIG: FLOWCNTRL Position */ -#define GPDMA_C6CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C6CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C6CONFIG: FLOWCNTRL Mask */ -#define GPDMA_C6CONFIG_IE_Pos 14 /*!< GPDMA C6CONFIG: IE Position */ -#define GPDMA_C6CONFIG_IE_Msk (0x01UL << GPDMA_C6CONFIG_IE_Pos) /*!< GPDMA C6CONFIG: IE Mask */ -#define GPDMA_C6CONFIG_ITC_Pos 15 /*!< GPDMA C6CONFIG: ITC Position */ -#define GPDMA_C6CONFIG_ITC_Msk (0x01UL << GPDMA_C6CONFIG_ITC_Pos) /*!< GPDMA C6CONFIG: ITC Mask */ -#define GPDMA_C6CONFIG_L_Pos 16 /*!< GPDMA C6CONFIG: L Position */ -#define GPDMA_C6CONFIG_L_Msk (0x01UL << GPDMA_C6CONFIG_L_Pos) /*!< GPDMA C6CONFIG: L Mask */ -#define GPDMA_C6CONFIG_A_Pos 17 /*!< GPDMA C6CONFIG: A Position */ -#define GPDMA_C6CONFIG_A_Msk (0x01UL << GPDMA_C6CONFIG_A_Pos) /*!< GPDMA C6CONFIG: A Mask */ -#define GPDMA_C6CONFIG_H_Pos 18 /*!< GPDMA C6CONFIG: H Position */ -#define GPDMA_C6CONFIG_H_Msk (0x01UL << GPDMA_C6CONFIG_H_Pos) /*!< GPDMA C6CONFIG: H Mask */ - -// ------------------------------------- GPDMA_C7SRCADDR ---------------------------------------- -#define GPDMA_C7SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C7SRCADDR: SRCADDR Position */ -#define GPDMA_C7SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C7SRCADDR_SRCADDR_Pos) /*!< GPDMA C7SRCADDR: SRCADDR Mask */ - -// ------------------------------------ GPDMA_C7DESTADDR ---------------------------------------- -#define GPDMA_C7DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C7DESTADDR: DESTADDR Position */ -#define GPDMA_C7DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C7DESTADDR_DESTADDR_Pos) /*!< GPDMA C7DESTADDR: DESTADDR Mask */ - -// --------------------------------------- GPDMA_C7LLI ------------------------------------------ -#define GPDMA_C7LLI_LM_Pos 0 /*!< GPDMA C7LLI: LM Position */ -#define GPDMA_C7LLI_LM_Msk (0x01UL << GPDMA_C7LLI_LM_Pos) /*!< GPDMA C7LLI: LM Mask */ -#define GPDMA_C7LLI_R_Pos 1 /*!< GPDMA C7LLI: R Position */ -#define GPDMA_C7LLI_R_Msk (0x01UL << GPDMA_C7LLI_R_Pos) /*!< GPDMA C7LLI: R Mask */ -#define GPDMA_C7LLI_LLI_Pos 2 /*!< GPDMA C7LLI: LLI Position */ -#define GPDMA_C7LLI_LLI_Msk (0x3fffffffUL << GPDMA_C7LLI_LLI_Pos) /*!< GPDMA C7LLI: LLI Mask */ - -// ------------------------------------- GPDMA_C7CONTROL ---------------------------------------- -#define GPDMA_C7CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C7CONTROL: TRANSFERSIZE Position */ -#define GPDMA_C7CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C7CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C7CONTROL: TRANSFERSIZE Mask */ -#define GPDMA_C7CONTROL_SBSIZE_Pos 12 /*!< GPDMA C7CONTROL: SBSIZE Position */ -#define GPDMA_C7CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C7CONTROL_SBSIZE_Pos) /*!< GPDMA C7CONTROL: SBSIZE Mask */ -#define GPDMA_C7CONTROL_DBSIZE_Pos 15 /*!< GPDMA C7CONTROL: DBSIZE Position */ -#define GPDMA_C7CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C7CONTROL_DBSIZE_Pos) /*!< GPDMA C7CONTROL: DBSIZE Mask */ -#define GPDMA_C7CONTROL_SWIDTH_Pos 18 /*!< GPDMA C7CONTROL: SWIDTH Position */ -#define GPDMA_C7CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C7CONTROL_SWIDTH_Pos) /*!< GPDMA C7CONTROL: SWIDTH Mask */ -#define GPDMA_C7CONTROL_DWIDTH_Pos 21 /*!< GPDMA C7CONTROL: DWIDTH Position */ -#define GPDMA_C7CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C7CONTROL_DWIDTH_Pos) /*!< GPDMA C7CONTROL: DWIDTH Mask */ -#define GPDMA_C7CONTROL_S_Pos 24 /*!< GPDMA C7CONTROL: S Position */ -#define GPDMA_C7CONTROL_S_Msk (0x01UL << GPDMA_C7CONTROL_S_Pos) /*!< GPDMA C7CONTROL: S Mask */ -#define GPDMA_C7CONTROL_D_Pos 25 /*!< GPDMA C7CONTROL: D Position */ -#define GPDMA_C7CONTROL_D_Msk (0x01UL << GPDMA_C7CONTROL_D_Pos) /*!< GPDMA C7CONTROL: D Mask */ -#define GPDMA_C7CONTROL_SI_Pos 26 /*!< GPDMA C7CONTROL: SI Position */ -#define GPDMA_C7CONTROL_SI_Msk (0x01UL << GPDMA_C7CONTROL_SI_Pos) /*!< GPDMA C7CONTROL: SI Mask */ -#define GPDMA_C7CONTROL_DI_Pos 27 /*!< GPDMA C7CONTROL: DI Position */ -#define GPDMA_C7CONTROL_DI_Msk (0x01UL << GPDMA_C7CONTROL_DI_Pos) /*!< GPDMA C7CONTROL: DI Mask */ -#define GPDMA_C7CONTROL_PROT1_Pos 28 /*!< GPDMA C7CONTROL: PROT1 Position */ -#define GPDMA_C7CONTROL_PROT1_Msk (0x01UL << GPDMA_C7CONTROL_PROT1_Pos) /*!< GPDMA C7CONTROL: PROT1 Mask */ -#define GPDMA_C7CONTROL_PROT2_Pos 29 /*!< GPDMA C7CONTROL: PROT2 Position */ -#define GPDMA_C7CONTROL_PROT2_Msk (0x01UL << GPDMA_C7CONTROL_PROT2_Pos) /*!< GPDMA C7CONTROL: PROT2 Mask */ -#define GPDMA_C7CONTROL_PROT3_Pos 30 /*!< GPDMA C7CONTROL: PROT3 Position */ -#define GPDMA_C7CONTROL_PROT3_Msk (0x01UL << GPDMA_C7CONTROL_PROT3_Pos) /*!< GPDMA C7CONTROL: PROT3 Mask */ -#define GPDMA_C7CONTROL_I_Pos 31 /*!< GPDMA C7CONTROL: I Position */ -#define GPDMA_C7CONTROL_I_Msk (0x01UL << GPDMA_C7CONTROL_I_Pos) /*!< GPDMA C7CONTROL: I Mask */ - -// ------------------------------------- GPDMA_C7CONFIG ----------------------------------------- -#define GPDMA_C7CONFIG_E_Pos 0 /*!< GPDMA C7CONFIG: E Position */ -#define GPDMA_C7CONFIG_E_Msk (0x01UL << GPDMA_C7CONFIG_E_Pos) /*!< GPDMA C7CONFIG: E Mask */ -#define GPDMA_C7CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C7CONFIG: SRCPERIPHERAL Position */ -#define GPDMA_C7CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C7CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C7CONFIG: SRCPERIPHERAL Mask */ -#define GPDMA_C7CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C7CONFIG: DESTPERIPHERAL Position */ -#define GPDMA_C7CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C7CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C7CONFIG: DESTPERIPHERAL Mask */ -#define GPDMA_C7CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C7CONFIG: FLOWCNTRL Position */ -#define GPDMA_C7CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C7CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C7CONFIG: FLOWCNTRL Mask */ -#define GPDMA_C7CONFIG_IE_Pos 14 /*!< GPDMA C7CONFIG: IE Position */ -#define GPDMA_C7CONFIG_IE_Msk (0x01UL << GPDMA_C7CONFIG_IE_Pos) /*!< GPDMA C7CONFIG: IE Mask */ -#define GPDMA_C7CONFIG_ITC_Pos 15 /*!< GPDMA C7CONFIG: ITC Position */ -#define GPDMA_C7CONFIG_ITC_Msk (0x01UL << GPDMA_C7CONFIG_ITC_Pos) /*!< GPDMA C7CONFIG: ITC Mask */ -#define GPDMA_C7CONFIG_L_Pos 16 /*!< GPDMA C7CONFIG: L Position */ -#define GPDMA_C7CONFIG_L_Msk (0x01UL << GPDMA_C7CONFIG_L_Pos) /*!< GPDMA C7CONFIG: L Mask */ -#define GPDMA_C7CONFIG_A_Pos 17 /*!< GPDMA C7CONFIG: A Position */ -#define GPDMA_C7CONFIG_A_Msk (0x01UL << GPDMA_C7CONFIG_A_Pos) /*!< GPDMA C7CONFIG: A Mask */ -#define GPDMA_C7CONFIG_H_Pos 18 /*!< GPDMA C7CONFIG: H Position */ -#define GPDMA_C7CONFIG_H_Msk (0x01UL << GPDMA_C7CONFIG_H_Pos) /*!< GPDMA C7CONFIG: H Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- SDMMC Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- SDMMC_CTRL ------------------------------------------- -#define SDMMC_CTRL_CONTROLLER_RESET_Pos 0 /*!< SDMMC CTRL: CONTROLLER_RESET Position */ -#define SDMMC_CTRL_CONTROLLER_RESET_Msk (0x01UL << SDMMC_CTRL_CONTROLLER_RESET_Pos) /*!< SDMMC CTRL: CONTROLLER_RESET Mask */ -#define SDMMC_CTRL_FIFO_RESET_Pos 1 /*!< SDMMC CTRL: FIFO_RESET Position */ -#define SDMMC_CTRL_FIFO_RESET_Msk (0x01UL << SDMMC_CTRL_FIFO_RESET_Pos) /*!< SDMMC CTRL: FIFO_RESET Mask */ -#define SDMMC_CTRL_DMA_RESET_Pos 2 /*!< SDMMC CTRL: DMA_RESET Position */ -#define SDMMC_CTRL_DMA_RESET_Msk (0x01UL << SDMMC_CTRL_DMA_RESET_Pos) /*!< SDMMC CTRL: DMA_RESET Mask */ -#define SDMMC_CTRL_INT_ENABLE_Pos 4 /*!< SDMMC CTRL: INT_ENABLE Position */ -#define SDMMC_CTRL_INT_ENABLE_Msk (0x01UL << SDMMC_CTRL_INT_ENABLE_Pos) /*!< SDMMC CTRL: INT_ENABLE Mask */ -#define SDMMC_CTRL_DMA_ENABLE_Pos 5 /*!< SDMMC CTRL: DMA_ENABLE Position */ -#define SDMMC_CTRL_DMA_ENABLE_Msk (0x01UL << SDMMC_CTRL_DMA_ENABLE_Pos) /*!< SDMMC CTRL: DMA_ENABLE Mask */ -#define SDMMC_CTRL_READ_WAIT_Pos 6 /*!< SDMMC CTRL: READ_WAIT Position */ -#define SDMMC_CTRL_READ_WAIT_Msk (0x01UL << SDMMC_CTRL_READ_WAIT_Pos) /*!< SDMMC CTRL: READ_WAIT Mask */ -#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos 7 /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Position */ -#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Msk (0x01UL << SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos) /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Mask */ -#define SDMMC_CTRL_ABORT_READ_DATA_Pos 8 /*!< SDMMC CTRL: ABORT_READ_DATA Position */ -#define SDMMC_CTRL_ABORT_READ_DATA_Msk (0x01UL << SDMMC_CTRL_ABORT_READ_DATA_Pos) /*!< SDMMC CTRL: ABORT_READ_DATA Mask */ -#define SDMMC_CTRL_SEND_CCSD_Pos 9 /*!< SDMMC CTRL: SEND_CCSD Position */ -#define SDMMC_CTRL_SEND_CCSD_Msk (0x01UL << SDMMC_CTRL_SEND_CCSD_Pos) /*!< SDMMC CTRL: SEND_CCSD Mask */ -#define SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Pos 10 /*!< SDMMC CTRL: SEND_AUTO_STOP_CCSD Position */ -#define SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Msk (0x01UL << SDMMC_CTRL_SEND_AUTO_STOP_CCSD_Pos) /*!< SDMMC CTRL: SEND_AUTO_STOP_CCSD Mask */ -#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos 11 /*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Position */ -#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Msk (0x01UL << SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos) /*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Mask */ -#define SDMMC_CTRL_CARD_VOLTAGE_A_Pos 16 /*!< SDMMC CTRL: CARD_VOLTAGE_A Position */ -#define SDMMC_CTRL_CARD_VOLTAGE_A_Msk (0x0fUL << SDMMC_CTRL_CARD_VOLTAGE_A_Pos) /*!< SDMMC CTRL: CARD_VOLTAGE_A Mask */ -#define SDMMC_CTRL_CARD_VOLTAGE_B_Pos 20 /*!< SDMMC CTRL: CARD_VOLTAGE_B Position */ -#define SDMMC_CTRL_CARD_VOLTAGE_B_Msk (0x0fUL << SDMMC_CTRL_CARD_VOLTAGE_B_Pos) /*!< SDMMC CTRL: CARD_VOLTAGE_B Mask */ -#define SDMMC_CTRL_ENABLE_OD_PULLUP_Pos 24 /*!< SDMMC CTRL: ENABLE_OD_PULLUP Position */ -#define SDMMC_CTRL_ENABLE_OD_PULLUP_Msk (0x01UL << SDMMC_CTRL_ENABLE_OD_PULLUP_Pos) /*!< SDMMC CTRL: ENABLE_OD_PULLUP Mask */ -#define SDMMC_CTRL_USE_INTERNAL_DMAC_Pos 25 /*!< SDMMC CTRL: USE_INTERNAL_DMAC Position */ -#define SDMMC_CTRL_USE_INTERNAL_DMAC_Msk (0x01UL << SDMMC_CTRL_USE_INTERNAL_DMAC_Pos) /*!< SDMMC CTRL: USE_INTERNAL_DMAC Mask */ - -// --------------------------------------- SDMMC_PWREN ------------------------------------------ -#define SDMMC_PWREN_POWER_ENABLE_Pos 0 /*!< SDMMC PWREN: POWER_ENABLE Position */ -#define SDMMC_PWREN_POWER_ENABLE_Msk (0x3fffffffUL << SDMMC_PWREN_POWER_ENABLE_Pos) /*!< SDMMC PWREN: POWER_ENABLE Mask */ - -// -------------------------------------- SDMMC_CLKDIV ------------------------------------------ -#define SDMMC_CLKDIV_CLK_DIVIDER0_Pos 0 /*!< SDMMC CLKDIV: CLK_DIVIDER0 Position */ -#define SDMMC_CLKDIV_CLK_DIVIDER0_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER0_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER0 Mask */ -#define SDMMC_CLKDIV_CLK_DIVIDER1_Pos 8 /*!< SDMMC CLKDIV: CLK_DIVIDER1 Position */ -#define SDMMC_CLKDIV_CLK_DIVIDER1_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER1_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER1 Mask */ -#define SDMMC_CLKDIV_CLK_DIVIDER2_Pos 16 /*!< SDMMC CLKDIV: CLK_DIVIDER2 Position */ -#define SDMMC_CLKDIV_CLK_DIVIDER2_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER2_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER2 Mask */ -#define SDMMC_CLKDIV_CLK_DIVIDER3_Pos 24 /*!< SDMMC CLKDIV: CLK_DIVIDER3 Position */ -#define SDMMC_CLKDIV_CLK_DIVIDER3_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER3_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER3 Mask */ - -// -------------------------------------- SDMMC_CLKSRC ------------------------------------------ -#define SDMMC_CLKSRC_CLK_SOURCE_Pos 0 /*!< SDMMC CLKSRC: CLK_SOURCE Position */ -#define SDMMC_CLKSRC_CLK_SOURCE_Msk (0xffffffffUL << SDMMC_CLKSRC_CLK_SOURCE_Pos) /*!< SDMMC CLKSRC: CLK_SOURCE Mask */ - -// -------------------------------------- SDMMC_CLKENA ------------------------------------------ -#define SDMMC_CLKENA_CCLK_ENABLE_Pos 0 /*!< SDMMC CLKENA: CCLK_ENABLE Position */ -#define SDMMC_CLKENA_CCLK_ENABLE_Msk (0x0000ffffUL << SDMMC_CLKENA_CCLK_ENABLE_Pos) /*!< SDMMC CLKENA: CCLK_ENABLE Mask */ -#define SDMMC_CLKENA_CCLK_LOW_POWER_Pos 16 /*!< SDMMC CLKENA: CCLK_LOW_POWER Position */ -#define SDMMC_CLKENA_CCLK_LOW_POWER_Msk (0x0000ffffUL << SDMMC_CLKENA_CCLK_LOW_POWER_Pos) /*!< SDMMC CLKENA: CCLK_LOW_POWER Mask */ - -// --------------------------------------- SDMMC_TMOUT ------------------------------------------ -#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos 0 /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Position */ -#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Msk (0x000000ffUL << SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos) /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Mask */ -#define SDMMC_TMOUT_DATA_TIMEOUT_Pos 8 /*!< SDMMC TMOUT: DATA_TIMEOUT Position */ -#define SDMMC_TMOUT_DATA_TIMEOUT_Msk (0x00ffffffUL << SDMMC_TMOUT_DATA_TIMEOUT_Pos) /*!< SDMMC TMOUT: DATA_TIMEOUT Mask */ - -// --------------------------------------- SDMMC_CTYPE ------------------------------------------ -#define SDMMC_CTYPE_CARD_WIDTH0_Pos 0 /*!< SDMMC CTYPE: CARD_WIDTH0 Position */ -#define SDMMC_CTYPE_CARD_WIDTH0_Msk (0x0000ffffUL << SDMMC_CTYPE_CARD_WIDTH0_Pos) /*!< SDMMC CTYPE: CARD_WIDTH0 Mask */ -#define SDMMC_CTYPE_CARD_WIDTH1_Pos 16 /*!< SDMMC CTYPE: CARD_WIDTH1 Position */ -#define SDMMC_CTYPE_CARD_WIDTH1_Msk (0x0000ffffUL << SDMMC_CTYPE_CARD_WIDTH1_Pos) /*!< SDMMC CTYPE: CARD_WIDTH1 Mask */ - -// -------------------------------------- SDMMC_BLKSIZ ------------------------------------------ -#define SDMMC_BLKSIZ_BLOCK_SIZE_Pos 0 /*!< SDMMC BLKSIZ: BLOCK_SIZE Position */ -#define SDMMC_BLKSIZ_BLOCK_SIZE_Msk (0x0000ffffUL << SDMMC_BLKSIZ_BLOCK_SIZE_Pos) /*!< SDMMC BLKSIZ: BLOCK_SIZE Mask */ - -// -------------------------------------- SDMMC_BYTCNT ------------------------------------------ -#define SDMMC_BYTCNT_BYTE_COUNT_Pos 0 /*!< SDMMC BYTCNT: BYTE_COUNT Position */ -#define SDMMC_BYTCNT_BYTE_COUNT_Msk (0xffffffffUL << SDMMC_BYTCNT_BYTE_COUNT_Pos) /*!< SDMMC BYTCNT: BYTE_COUNT Mask */ - -// -------------------------------------- SDMMC_INTMASK ----------------------------------------- -#define SDMMC_INTMASK_CDET_Pos 0 /*!< SDMMC INTMASK: CDET Position */ -#define SDMMC_INTMASK_CDET_Msk (0x01UL << SDMMC_INTMASK_CDET_Pos) /*!< SDMMC INTMASK: CDET Mask */ -#define SDMMC_INTMASK_RE_Pos 1 /*!< SDMMC INTMASK: RE Position */ -#define SDMMC_INTMASK_RE_Msk (0x01UL << SDMMC_INTMASK_RE_Pos) /*!< SDMMC INTMASK: RE Mask */ -#define SDMMC_INTMASK_CDONE_Pos 2 /*!< SDMMC INTMASK: CDONE Position */ -#define SDMMC_INTMASK_CDONE_Msk (0x01UL << SDMMC_INTMASK_CDONE_Pos) /*!< SDMMC INTMASK: CDONE Mask */ -#define SDMMC_INTMASK_DTO_Pos 3 /*!< SDMMC INTMASK: DTO Position */ -#define SDMMC_INTMASK_DTO_Msk (0x01UL << SDMMC_INTMASK_DTO_Pos) /*!< SDMMC INTMASK: DTO Mask */ -#define SDMMC_INTMASK_TXDR_Pos 4 /*!< SDMMC INTMASK: TXDR Position */ -#define SDMMC_INTMASK_TXDR_Msk (0x01UL << SDMMC_INTMASK_TXDR_Pos) /*!< SDMMC INTMASK: TXDR Mask */ -#define SDMMC_INTMASK_RXDR_Pos 5 /*!< SDMMC INTMASK: RXDR Position */ -#define SDMMC_INTMASK_RXDR_Msk (0x01UL << SDMMC_INTMASK_RXDR_Pos) /*!< SDMMC INTMASK: RXDR Mask */ -#define SDMMC_INTMASK_RCRC_Pos 6 /*!< SDMMC INTMASK: RCRC Position */ -#define SDMMC_INTMASK_RCRC_Msk (0x01UL << SDMMC_INTMASK_RCRC_Pos) /*!< SDMMC INTMASK: RCRC Mask */ -#define SDMMC_INTMASK_DCRC_Pos 7 /*!< SDMMC INTMASK: DCRC Position */ -#define SDMMC_INTMASK_DCRC_Msk (0x01UL << SDMMC_INTMASK_DCRC_Pos) /*!< SDMMC INTMASK: DCRC Mask */ -#define SDMMC_INTMASK_RTO_Pos 8 /*!< SDMMC INTMASK: RTO Position */ -#define SDMMC_INTMASK_RTO_Msk (0x01UL << SDMMC_INTMASK_RTO_Pos) /*!< SDMMC INTMASK: RTO Mask */ -#define SDMMC_INTMASK_DRTO_Pos 9 /*!< SDMMC INTMASK: DRTO Position */ -#define SDMMC_INTMASK_DRTO_Msk (0x01UL << SDMMC_INTMASK_DRTO_Pos) /*!< SDMMC INTMASK: DRTO Mask */ -#define SDMMC_INTMASK_HTO_Pos 10 /*!< SDMMC INTMASK: HTO Position */ -#define SDMMC_INTMASK_HTO_Msk (0x01UL << SDMMC_INTMASK_HTO_Pos) /*!< SDMMC INTMASK: HTO Mask */ -#define SDMMC_INTMASK_FRUN_Pos 11 /*!< SDMMC INTMASK: FRUN Position */ -#define SDMMC_INTMASK_FRUN_Msk (0x01UL << SDMMC_INTMASK_FRUN_Pos) /*!< SDMMC INTMASK: FRUN Mask */ -#define SDMMC_INTMASK_HLE_Pos 12 /*!< SDMMC INTMASK: HLE Position */ -#define SDMMC_INTMASK_HLE_Msk (0x01UL << SDMMC_INTMASK_HLE_Pos) /*!< SDMMC INTMASK: HLE Mask */ -#define SDMMC_INTMASK_SBE_Pos 13 /*!< SDMMC INTMASK: SBE Position */ -#define SDMMC_INTMASK_SBE_Msk (0x01UL << SDMMC_INTMASK_SBE_Pos) /*!< SDMMC INTMASK: SBE Mask */ -#define SDMMC_INTMASK_ACD_Pos 14 /*!< SDMMC INTMASK: ACD Position */ -#define SDMMC_INTMASK_ACD_Msk (0x01UL << SDMMC_INTMASK_ACD_Pos) /*!< SDMMC INTMASK: ACD Mask */ -#define SDMMC_INTMASK_EBE_Pos 15 /*!< SDMMC INTMASK: EBE Position */ -#define SDMMC_INTMASK_EBE_Msk (0x01UL << SDMMC_INTMASK_EBE_Pos) /*!< SDMMC INTMASK: EBE Mask */ -#define SDMMC_INTMASK_SDIO_INT_MASK_Pos 16 /*!< SDMMC INTMASK: SDIO_INT_MASK Position */ -#define SDMMC_INTMASK_SDIO_INT_MASK_Msk (0x0000ffffUL << SDMMC_INTMASK_SDIO_INT_MASK_Pos) /*!< SDMMC INTMASK: SDIO_INT_MASK Mask */ - -// -------------------------------------- SDMMC_CMDARG ------------------------------------------ -#define SDMMC_CMDARG_CMD_ARG_Pos 0 /*!< SDMMC CMDARG: CMD_ARG Position */ -#define SDMMC_CMDARG_CMD_ARG_Msk (0xffffffffUL << SDMMC_CMDARG_CMD_ARG_Pos) /*!< SDMMC CMDARG: CMD_ARG Mask */ - -// ---------------------------------------- SDMMC_CMD ------------------------------------------- -#define SDMMC_CMD_CMD_INDEX_Pos 0 /*!< SDMMC CMD: CMD_INDEX Position */ -#define SDMMC_CMD_CMD_INDEX_Msk (0x3fUL << SDMMC_CMD_CMD_INDEX_Pos) /*!< SDMMC CMD: CMD_INDEX Mask */ -#define SDMMC_CMD_RESPONSE_EXPECT_Pos 6 /*!< SDMMC CMD: RESPONSE_EXPECT Position */ -#define SDMMC_CMD_RESPONSE_EXPECT_Msk (0x01UL << SDMMC_CMD_RESPONSE_EXPECT_Pos) /*!< SDMMC CMD: RESPONSE_EXPECT Mask */ -#define SDMMC_CMD_RESPONSE_LENGTH_Pos 7 /*!< SDMMC CMD: RESPONSE_LENGTH Position */ -#define SDMMC_CMD_RESPONSE_LENGTH_Msk (0x01UL << SDMMC_CMD_RESPONSE_LENGTH_Pos) /*!< SDMMC CMD: RESPONSE_LENGTH Mask */ -#define SDMMC_CMD_CHECK_RESPONSE_CRC_Pos 8 /*!< SDMMC CMD: CHECK_RESPONSE_CRC Position */ -#define SDMMC_CMD_CHECK_RESPONSE_CRC_Msk (0x01UL << SDMMC_CMD_CHECK_RESPONSE_CRC_Pos) /*!< SDMMC CMD: CHECK_RESPONSE_CRC Mask */ -#define SDMMC_CMD_DATA_EXPECTED_Pos 9 /*!< SDMMC CMD: DATA_EXPECTED Position */ -#define SDMMC_CMD_DATA_EXPECTED_Msk (0x01UL << SDMMC_CMD_DATA_EXPECTED_Pos) /*!< SDMMC CMD: DATA_EXPECTED Mask */ -#define SDMMC_CMD_READ_WRITE_Pos 10 /*!< SDMMC CMD: READ_WRITE Position */ -#define SDMMC_CMD_READ_WRITE_Msk (0x01UL << SDMMC_CMD_READ_WRITE_Pos) /*!< SDMMC CMD: READ_WRITE Mask */ -#define SDMMC_CMD_TRANSFER_MODE_Pos 11 /*!< SDMMC CMD: TRANSFER_MODE Position */ -#define SDMMC_CMD_TRANSFER_MODE_Msk (0x01UL << SDMMC_CMD_TRANSFER_MODE_Pos) /*!< SDMMC CMD: TRANSFER_MODE Mask */ -#define SDMMC_CMD_SEND_AUTO_STOP_Pos 12 /*!< SDMMC CMD: SEND_AUTO_STOP Position */ -#define SDMMC_CMD_SEND_AUTO_STOP_Msk (0x01UL << SDMMC_CMD_SEND_AUTO_STOP_Pos) /*!< SDMMC CMD: SEND_AUTO_STOP Mask */ -#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos 13 /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Position */ -#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Msk (0x01UL << SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos) /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Mask */ -#define SDMMC_CMD_STOP_ABORT_CMd_Pos 14 /*!< SDMMC CMD: STOP_ABORT_CMd Position */ -#define SDMMC_CMD_STOP_ABORT_CMd_Msk (0x01UL << SDMMC_CMD_STOP_ABORT_CMd_Pos) /*!< SDMMC CMD: STOP_ABORT_CMd Mask */ -#define SDMMC_CMD_SEND_INITIALIZATION_Pos 15 /*!< SDMMC CMD: SEND_INITIALIZATION Position */ -#define SDMMC_CMD_SEND_INITIALIZATION_Msk (0x01UL << SDMMC_CMD_SEND_INITIALIZATION_Pos) /*!< SDMMC CMD: SEND_INITIALIZATION Mask */ -#define SDMMC_CMD_CARD_NUMBER_Pos 16 /*!< SDMMC CMD: CARD_NUMBER Position */ -#define SDMMC_CMD_CARD_NUMBER_Msk (0x1fUL << SDMMC_CMD_CARD_NUMBER_Pos) /*!< SDMMC CMD: CARD_NUMBER Mask */ -#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos 21 /*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Position */ -#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Msk (0x01UL << SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos) /*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Mask */ -#define SDMMC_CMD_READ_CEATA_DEVICE_Pos 22 /*!< SDMMC CMD: READ_CEATA_DEVICE Position */ -#define SDMMC_CMD_READ_CEATA_DEVICE_Msk (0x01UL << SDMMC_CMD_READ_CEATA_DEVICE_Pos) /*!< SDMMC CMD: READ_CEATA_DEVICE Mask */ -#define SDMMC_CMD_CCS_EXPECTED_Pos 23 /*!< SDMMC CMD: CCS_EXPECTED Position */ -#define SDMMC_CMD_CCS_EXPECTED_Msk (0x01UL << SDMMC_CMD_CCS_EXPECTED_Pos) /*!< SDMMC CMD: CCS_EXPECTED Mask */ -#define SDMMC_CMD_ENABLE_BOOT_Pos 24 /*!< SDMMC CMD: ENABLE_BOOT Position */ -#define SDMMC_CMD_ENABLE_BOOT_Msk (0x01UL << SDMMC_CMD_ENABLE_BOOT_Pos) /*!< SDMMC CMD: ENABLE_BOOT Mask */ -#define SDMMC_CMD_EXPECT_BOOT_ACK_Pos 25 /*!< SDMMC CMD: EXPECT_BOOT_ACK Position */ -#define SDMMC_CMD_EXPECT_BOOT_ACK_Msk (0x01UL << SDMMC_CMD_EXPECT_BOOT_ACK_Pos) /*!< SDMMC CMD: EXPECT_BOOT_ACK Mask */ -#define SDMMC_CMD_DISABLE_BOOT_Pos 26 /*!< SDMMC CMD: DISABLE_BOOT Position */ -#define SDMMC_CMD_DISABLE_BOOT_Msk (0x01UL << SDMMC_CMD_DISABLE_BOOT_Pos) /*!< SDMMC CMD: DISABLE_BOOT Mask */ -#define SDMMC_CMD_BOOT_MODE_Pos 27 /*!< SDMMC CMD: BOOT_MODE Position */ -#define SDMMC_CMD_BOOT_MODE_Msk (0x01UL << SDMMC_CMD_BOOT_MODE_Pos) /*!< SDMMC CMD: BOOT_MODE Mask */ -#define SDMMC_CMD_VOLT_SWITCH_Pos 28 /*!< SDMMC CMD: VOLT_SWITCH Position */ -#define SDMMC_CMD_VOLT_SWITCH_Msk (0x01UL << SDMMC_CMD_VOLT_SWITCH_Pos) /*!< SDMMC CMD: VOLT_SWITCH Mask */ -#define SDMMC_CMD_START_CMD_Pos 31 /*!< SDMMC CMD: START_CMD Position */ -#define SDMMC_CMD_START_CMD_Msk (0x01UL << SDMMC_CMD_START_CMD_Pos) /*!< SDMMC CMD: START_CMD Mask */ - -// --------------------------------------- SDMMC_RESP0 ------------------------------------------ -#define SDMMC_RESP0_RESPONSE0_Pos 0 /*!< SDMMC RESP0: RESPONSE0 Position */ -#define SDMMC_RESP0_RESPONSE0_Msk (0xffffffffUL << SDMMC_RESP0_RESPONSE0_Pos) /*!< SDMMC RESP0: RESPONSE0 Mask */ - -// --------------------------------------- SDMMC_RESP1 ------------------------------------------ -#define SDMMC_RESP1_RESPONSE1_Pos 0 /*!< SDMMC RESP1: RESPONSE1 Position */ -#define SDMMC_RESP1_RESPONSE1_Msk (0xffffffffUL << SDMMC_RESP1_RESPONSE1_Pos) /*!< SDMMC RESP1: RESPONSE1 Mask */ - -// --------------------------------------- SDMMC_RESP2 ------------------------------------------ -#define SDMMC_RESP2_RESPONSE2_Pos 0 /*!< SDMMC RESP2: RESPONSE2 Position */ -#define SDMMC_RESP2_RESPONSE2_Msk (0xffffffffUL << SDMMC_RESP2_RESPONSE2_Pos) /*!< SDMMC RESP2: RESPONSE2 Mask */ - -// --------------------------------------- SDMMC_RESP3 ------------------------------------------ -#define SDMMC_RESP3_RESPONSE3_Pos 0 /*!< SDMMC RESP3: RESPONSE3 Position */ -#define SDMMC_RESP3_RESPONSE3_Msk (0xffffffffUL << SDMMC_RESP3_RESPONSE3_Pos) /*!< SDMMC RESP3: RESPONSE3 Mask */ - -// -------------------------------------- SDMMC_MINTSTS ----------------------------------------- -#define SDMMC_MINTSTS_CDET_Pos 0 /*!< SDMMC MINTSTS: CDET Position */ -#define SDMMC_MINTSTS_CDET_Msk (0x01UL << SDMMC_MINTSTS_CDET_Pos) /*!< SDMMC MINTSTS: CDET Mask */ -#define SDMMC_MINTSTS_RE_Pos 1 /*!< SDMMC MINTSTS: RE Position */ -#define SDMMC_MINTSTS_RE_Msk (0x01UL << SDMMC_MINTSTS_RE_Pos) /*!< SDMMC MINTSTS: RE Mask */ -#define SDMMC_MINTSTS_CDONE_Pos 2 /*!< SDMMC MINTSTS: CDONE Position */ -#define SDMMC_MINTSTS_CDONE_Msk (0x01UL << SDMMC_MINTSTS_CDONE_Pos) /*!< SDMMC MINTSTS: CDONE Mask */ -#define SDMMC_MINTSTS_DTO_Pos 3 /*!< SDMMC MINTSTS: DTO Position */ -#define SDMMC_MINTSTS_DTO_Msk (0x01UL << SDMMC_MINTSTS_DTO_Pos) /*!< SDMMC MINTSTS: DTO Mask */ -#define SDMMC_MINTSTS_TXDR_Pos 4 /*!< SDMMC MINTSTS: TXDR Position */ -#define SDMMC_MINTSTS_TXDR_Msk (0x01UL << SDMMC_MINTSTS_TXDR_Pos) /*!< SDMMC MINTSTS: TXDR Mask */ -#define SDMMC_MINTSTS_RXDR_Pos 5 /*!< SDMMC MINTSTS: RXDR Position */ -#define SDMMC_MINTSTS_RXDR_Msk (0x01UL << SDMMC_MINTSTS_RXDR_Pos) /*!< SDMMC MINTSTS: RXDR Mask */ -#define SDMMC_MINTSTS_RCRC_Pos 6 /*!< SDMMC MINTSTS: RCRC Position */ -#define SDMMC_MINTSTS_RCRC_Msk (0x01UL << SDMMC_MINTSTS_RCRC_Pos) /*!< SDMMC MINTSTS: RCRC Mask */ -#define SDMMC_MINTSTS_DCRC_Pos 7 /*!< SDMMC MINTSTS: DCRC Position */ -#define SDMMC_MINTSTS_DCRC_Msk (0x01UL << SDMMC_MINTSTS_DCRC_Pos) /*!< SDMMC MINTSTS: DCRC Mask */ -#define SDMMC_MINTSTS_RTO_Pos 8 /*!< SDMMC MINTSTS: RTO Position */ -#define SDMMC_MINTSTS_RTO_Msk (0x01UL << SDMMC_MINTSTS_RTO_Pos) /*!< SDMMC MINTSTS: RTO Mask */ -#define SDMMC_MINTSTS_DRTO_Pos 9 /*!< SDMMC MINTSTS: DRTO Position */ -#define SDMMC_MINTSTS_DRTO_Msk (0x01UL << SDMMC_MINTSTS_DRTO_Pos) /*!< SDMMC MINTSTS: DRTO Mask */ -#define SDMMC_MINTSTS_HTO_Pos 10 /*!< SDMMC MINTSTS: HTO Position */ -#define SDMMC_MINTSTS_HTO_Msk (0x01UL << SDMMC_MINTSTS_HTO_Pos) /*!< SDMMC MINTSTS: HTO Mask */ -#define SDMMC_MINTSTS_FRUN_Pos 11 /*!< SDMMC MINTSTS: FRUN Position */ -#define SDMMC_MINTSTS_FRUN_Msk (0x01UL << SDMMC_MINTSTS_FRUN_Pos) /*!< SDMMC MINTSTS: FRUN Mask */ -#define SDMMC_MINTSTS_HLE_Pos 12 /*!< SDMMC MINTSTS: HLE Position */ -#define SDMMC_MINTSTS_HLE_Msk (0x01UL << SDMMC_MINTSTS_HLE_Pos) /*!< SDMMC MINTSTS: HLE Mask */ -#define SDMMC_MINTSTS_SBE_Pos 13 /*!< SDMMC MINTSTS: SBE Position */ -#define SDMMC_MINTSTS_SBE_Msk (0x01UL << SDMMC_MINTSTS_SBE_Pos) /*!< SDMMC MINTSTS: SBE Mask */ -#define SDMMC_MINTSTS_ACD_Pos 14 /*!< SDMMC MINTSTS: ACD Position */ -#define SDMMC_MINTSTS_ACD_Msk (0x01UL << SDMMC_MINTSTS_ACD_Pos) /*!< SDMMC MINTSTS: ACD Mask */ -#define SDMMC_MINTSTS_EBE_Pos 15 /*!< SDMMC MINTSTS: EBE Position */ -#define SDMMC_MINTSTS_EBE_Msk (0x01UL << SDMMC_MINTSTS_EBE_Pos) /*!< SDMMC MINTSTS: EBE Mask */ -#define SDMMC_MINTSTS_SDIO_INTERRUPT_Pos 16 /*!< SDMMC MINTSTS: SDIO_INTERRUPT Position */ -#define SDMMC_MINTSTS_SDIO_INTERRUPT_Msk (0x0000ffffUL << SDMMC_MINTSTS_SDIO_INTERRUPT_Pos) /*!< SDMMC MINTSTS: SDIO_INTERRUPT Mask */ - -// -------------------------------------- SDMMC_RINTSTS ----------------------------------------- -#define SDMMC_RINTSTS_CDET_Pos 0 /*!< SDMMC RINTSTS: CDET Position */ -#define SDMMC_RINTSTS_CDET_Msk (0x01UL << SDMMC_RINTSTS_CDET_Pos) /*!< SDMMC RINTSTS: CDET Mask */ -#define SDMMC_RINTSTS_RE_Pos 1 /*!< SDMMC RINTSTS: RE Position */ -#define SDMMC_RINTSTS_RE_Msk (0x01UL << SDMMC_RINTSTS_RE_Pos) /*!< SDMMC RINTSTS: RE Mask */ -#define SDMMC_RINTSTS_CDONE_Pos 2 /*!< SDMMC RINTSTS: CDONE Position */ -#define SDMMC_RINTSTS_CDONE_Msk (0x01UL << SDMMC_RINTSTS_CDONE_Pos) /*!< SDMMC RINTSTS: CDONE Mask */ -#define SDMMC_RINTSTS_DTO_Pos 3 /*!< SDMMC RINTSTS: DTO Position */ -#define SDMMC_RINTSTS_DTO_Msk (0x01UL << SDMMC_RINTSTS_DTO_Pos) /*!< SDMMC RINTSTS: DTO Mask */ -#define SDMMC_RINTSTS_TXDR_Pos 4 /*!< SDMMC RINTSTS: TXDR Position */ -#define SDMMC_RINTSTS_TXDR_Msk (0x01UL << SDMMC_RINTSTS_TXDR_Pos) /*!< SDMMC RINTSTS: TXDR Mask */ -#define SDMMC_RINTSTS_RXDR_Pos 5 /*!< SDMMC RINTSTS: RXDR Position */ -#define SDMMC_RINTSTS_RXDR_Msk (0x01UL << SDMMC_RINTSTS_RXDR_Pos) /*!< SDMMC RINTSTS: RXDR Mask */ -#define SDMMC_RINTSTS_RCRC_Pos 6 /*!< SDMMC RINTSTS: RCRC Position */ -#define SDMMC_RINTSTS_RCRC_Msk (0x01UL << SDMMC_RINTSTS_RCRC_Pos) /*!< SDMMC RINTSTS: RCRC Mask */ -#define SDMMC_RINTSTS_DCRC_Pos 7 /*!< SDMMC RINTSTS: DCRC Position */ -#define SDMMC_RINTSTS_DCRC_Msk (0x01UL << SDMMC_RINTSTS_DCRC_Pos) /*!< SDMMC RINTSTS: DCRC Mask */ -#define SDMMC_RINTSTS_RTO_BAR_Pos 8 /*!< SDMMC RINTSTS: RTO_BAR Position */ -#define SDMMC_RINTSTS_RTO_BAR_Msk (0x01UL << SDMMC_RINTSTS_RTO_BAR_Pos) /*!< SDMMC RINTSTS: RTO_BAR Mask */ -#define SDMMC_RINTSTS_DRTO_BDS_Pos 9 /*!< SDMMC RINTSTS: DRTO_BDS Position */ -#define SDMMC_RINTSTS_DRTO_BDS_Msk (0x01UL << SDMMC_RINTSTS_DRTO_BDS_Pos) /*!< SDMMC RINTSTS: DRTO_BDS Mask */ -#define SDMMC_RINTSTS_HTO_Pos 10 /*!< SDMMC RINTSTS: HTO Position */ -#define SDMMC_RINTSTS_HTO_Msk (0x01UL << SDMMC_RINTSTS_HTO_Pos) /*!< SDMMC RINTSTS: HTO Mask */ -#define SDMMC_RINTSTS_FRUN_Pos 11 /*!< SDMMC RINTSTS: FRUN Position */ -#define SDMMC_RINTSTS_FRUN_Msk (0x01UL << SDMMC_RINTSTS_FRUN_Pos) /*!< SDMMC RINTSTS: FRUN Mask */ -#define SDMMC_RINTSTS_HLE_Pos 12 /*!< SDMMC RINTSTS: HLE Position */ -#define SDMMC_RINTSTS_HLE_Msk (0x01UL << SDMMC_RINTSTS_HLE_Pos) /*!< SDMMC RINTSTS: HLE Mask */ -#define SDMMC_RINTSTS_SBE_Pos 13 /*!< SDMMC RINTSTS: SBE Position */ -#define SDMMC_RINTSTS_SBE_Msk (0x01UL << SDMMC_RINTSTS_SBE_Pos) /*!< SDMMC RINTSTS: SBE Mask */ -#define SDMMC_RINTSTS_ACD_Pos 14 /*!< SDMMC RINTSTS: ACD Position */ -#define SDMMC_RINTSTS_ACD_Msk (0x01UL << SDMMC_RINTSTS_ACD_Pos) /*!< SDMMC RINTSTS: ACD Mask */ -#define SDMMC_RINTSTS_EBE_Pos 15 /*!< SDMMC RINTSTS: EBE Position */ -#define SDMMC_RINTSTS_EBE_Msk (0x01UL << SDMMC_RINTSTS_EBE_Pos) /*!< SDMMC RINTSTS: EBE Mask */ -#define SDMMC_RINTSTS_SDIO_INTERRUPT_Pos 16 /*!< SDMMC RINTSTS: SDIO_INTERRUPT Position */ -#define SDMMC_RINTSTS_SDIO_INTERRUPT_Msk (0x0000ffffUL << SDMMC_RINTSTS_SDIO_INTERRUPT_Pos) /*!< SDMMC RINTSTS: SDIO_INTERRUPT Mask */ - -// -------------------------------------- SDMMC_STATUS ------------------------------------------ -#define SDMMC_STATUS_FIFO_RX_WATERMARK_Pos 0 /*!< SDMMC STATUS: FIFO_RX_WATERMARK Position */ -#define SDMMC_STATUS_FIFO_RX_WATERMARK_Msk (0x01UL << SDMMC_STATUS_FIFO_RX_WATERMARK_Pos) /*!< SDMMC STATUS: FIFO_RX_WATERMARK Mask */ -#define SDMMC_STATUS_FIFO_TX_WATERMARK_Pos 1 /*!< SDMMC STATUS: FIFO_TX_WATERMARK Position */ -#define SDMMC_STATUS_FIFO_TX_WATERMARK_Msk (0x01UL << SDMMC_STATUS_FIFO_TX_WATERMARK_Pos) /*!< SDMMC STATUS: FIFO_TX_WATERMARK Mask */ -#define SDMMC_STATUS_FIFO_EMPTY_Pos 2 /*!< SDMMC STATUS: FIFO_EMPTY Position */ -#define SDMMC_STATUS_FIFO_EMPTY_Msk (0x01UL << SDMMC_STATUS_FIFO_EMPTY_Pos) /*!< SDMMC STATUS: FIFO_EMPTY Mask */ -#define SDMMC_STATUS_FIFO_FULL_Pos 3 /*!< SDMMC STATUS: FIFO_FULL Position */ -#define SDMMC_STATUS_FIFO_FULL_Msk (0x01UL << SDMMC_STATUS_FIFO_FULL_Pos) /*!< SDMMC STATUS: FIFO_FULL Mask */ -#define SDMMC_STATUS_CMDFSMSTATES_Pos 4 /*!< SDMMC STATUS: CMDFSMSTATES Position */ -#define SDMMC_STATUS_CMDFSMSTATES_Msk (0x0fUL << SDMMC_STATUS_CMDFSMSTATES_Pos) /*!< SDMMC STATUS: CMDFSMSTATES Mask */ -#define SDMMC_STATUS_DATA_3_STATUS_Pos 8 /*!< SDMMC STATUS: DATA_3_STATUS Position */ -#define SDMMC_STATUS_DATA_3_STATUS_Msk (0x01UL << SDMMC_STATUS_DATA_3_STATUS_Pos) /*!< SDMMC STATUS: DATA_3_STATUS Mask */ -#define SDMMC_STATUS_DATA_BUSY_Pos 9 /*!< SDMMC STATUS: DATA_BUSY Position */ -#define SDMMC_STATUS_DATA_BUSY_Msk (0x01UL << SDMMC_STATUS_DATA_BUSY_Pos) /*!< SDMMC STATUS: DATA_BUSY Mask */ -#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos 10 /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Position */ -#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Msk (0x01UL << SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos) /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Mask */ -#define SDMMC_STATUS_RESPONSE_INDEX_Pos 11 /*!< SDMMC STATUS: RESPONSE_INDEX Position */ -#define SDMMC_STATUS_RESPONSE_INDEX_Msk (0x3fUL << SDMMC_STATUS_RESPONSE_INDEX_Pos) /*!< SDMMC STATUS: RESPONSE_INDEX Mask */ -#define SDMMC_STATUS_FIFO_COUNT_Pos 17 /*!< SDMMC STATUS: FIFO_COUNT Position */ -#define SDMMC_STATUS_FIFO_COUNT_Msk (0x00001fffUL << SDMMC_STATUS_FIFO_COUNT_Pos) /*!< SDMMC STATUS: FIFO_COUNT Mask */ -#define SDMMC_STATUS_DMA_ACK_Pos 30 /*!< SDMMC STATUS: DMA_ACK Position */ -#define SDMMC_STATUS_DMA_ACK_Msk (0x01UL << SDMMC_STATUS_DMA_ACK_Pos) /*!< SDMMC STATUS: DMA_ACK Mask */ -#define SDMMC_STATUS_DMA_REQ_Pos 31 /*!< SDMMC STATUS: DMA_REQ Position */ -#define SDMMC_STATUS_DMA_REQ_Msk (0x01UL << SDMMC_STATUS_DMA_REQ_Pos) /*!< SDMMC STATUS: DMA_REQ Mask */ - -// -------------------------------------- SDMMC_FIFOTH ------------------------------------------ -#define SDMMC_FIFOTH_TX_WMARK_Pos 0 /*!< SDMMC FIFOTH: TX_WMARK Position */ -#define SDMMC_FIFOTH_TX_WMARK_Msk (0x00000fffUL << SDMMC_FIFOTH_TX_WMARK_Pos) /*!< SDMMC FIFOTH: TX_WMARK Mask */ -#define SDMMC_FIFOTH_RX_WMARK_Pos 16 /*!< SDMMC FIFOTH: RX_WMARK Position */ -#define SDMMC_FIFOTH_RX_WMARK_Msk (0x00000fffUL << SDMMC_FIFOTH_RX_WMARK_Pos) /*!< SDMMC FIFOTH: RX_WMARK Mask */ -#define SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Pos 28 /*!< SDMMC FIFOTH: DW_DMA_MUTIPLE_TRANSACTION_SIZE Position */ -#define SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Msk (0x07UL << SDMMC_FIFOTH_DW_DMA_MUTIPLE_TRANSACTION_SIZE_Pos)/*!< SDMMC FIFOTH: DW_DMA_MUTIPLE_TRANSACTION_SIZE Mask */ - -// -------------------------------------- SDMMC_CDETECT ----------------------------------------- -#define SDMMC_CDETECT_CARD_DETECT_N_Pos 0 /*!< SDMMC CDETECT: CARD_DETECT_N Position */ -#define SDMMC_CDETECT_CARD_DETECT_N_Msk (0x3fffffffUL << SDMMC_CDETECT_CARD_DETECT_N_Pos) /*!< SDMMC CDETECT: CARD_DETECT_N Mask */ - -// -------------------------------------- SDMMC_WRTPRT ------------------------------------------ -#define SDMMC_WRTPRT_WRITE_PROTECT_Pos 0 /*!< SDMMC WRTPRT: WRITE_PROTECT Position */ -#define SDMMC_WRTPRT_WRITE_PROTECT_Msk (0x3fffffffUL << SDMMC_WRTPRT_WRITE_PROTECT_Pos) /*!< SDMMC WRTPRT: WRITE_PROTECT Mask */ - -// --------------------------------------- SDMMC_GPIO ------------------------------------------- -#define SDMMC_GPIO_GPI_Pos 0 /*!< SDMMC GPIO: GPI Position */ -#define SDMMC_GPIO_GPI_Msk (0x000000ffUL << SDMMC_GPIO_GPI_Pos) /*!< SDMMC GPIO: GPI Mask */ -#define SDMMC_GPIO_GPO_Pos 8 /*!< SDMMC GPIO: GPO Position */ -#define SDMMC_GPIO_GPO_Msk (0x0000ffffUL << SDMMC_GPIO_GPO_Pos) /*!< SDMMC GPIO: GPO Mask */ - -// -------------------------------------- SDMMC_TCBCNT ------------------------------------------ -#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos 0 /*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Position */ -#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Msk (0xffffffffUL << SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos) /*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Mask */ - -// -------------------------------------- SDMMC_TBBCNT ------------------------------------------ -#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos 0 /*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Position */ -#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Msk (0xffffffffUL << SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos) /*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Mask */ - -// -------------------------------------- SDMMC_DEBNCE ------------------------------------------ -#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos 0 /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Position */ -#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Msk (0x00ffffffUL << SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos) /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Mask */ - -// --------------------------------------- SDMMC_USRID ------------------------------------------ -#define SDMMC_USRID_USRID_Pos 0 /*!< SDMMC USRID: USRID Position */ -#define SDMMC_USRID_USRID_Msk (0xffffffffUL << SDMMC_USRID_USRID_Pos) /*!< SDMMC USRID: USRID Mask */ - -// --------------------------------------- SDMMC_VERID ------------------------------------------ -#define SDMMC_VERID_VERID_Pos 0 /*!< SDMMC VERID: VERID Position */ -#define SDMMC_VERID_VERID_Msk (0xffffffffUL << SDMMC_VERID_VERID_Pos) /*!< SDMMC VERID: VERID Mask */ - -// -------------------------------------- SDMMC_UHS_REG ----------------------------------------- -#define SDMMC_UHS_REG_VOLT_REG_Pos 0 /*!< SDMMC UHS_REG: VOLT_REG Position */ -#define SDMMC_UHS_REG_VOLT_REG_Msk (0x0000ffffUL << SDMMC_UHS_REG_VOLT_REG_Pos) /*!< SDMMC UHS_REG: VOLT_REG Mask */ -#define SDMMC_UHS_REG_DDR_REG_Pos 16 /*!< SDMMC UHS_REG: DDR_REG Position */ -#define SDMMC_UHS_REG_DDR_REG_Msk (0x0000ffffUL << SDMMC_UHS_REG_DDR_REG_Pos) /*!< SDMMC UHS_REG: DDR_REG Mask */ - -// --------------------------------------- SDMMC_RST_N ------------------------------------------ -#define SDMMC_RST_N_CARD_RESET_Pos 0 /*!< SDMMC RST_N: CARD_RESET Position */ -#define SDMMC_RST_N_CARD_RESET_Msk (0x0000ffffUL << SDMMC_RST_N_CARD_RESET_Pos) /*!< SDMMC RST_N: CARD_RESET Mask */ - -// --------------------------------------- SDMMC_BMOD ------------------------------------------- -#define SDMMC_BMOD_SWR_Pos 0 /*!< SDMMC BMOD: SWR Position */ -#define SDMMC_BMOD_SWR_Msk (0x01UL << SDMMC_BMOD_SWR_Pos) /*!< SDMMC BMOD: SWR Mask */ -#define SDMMC_BMOD_FB_Pos 1 /*!< SDMMC BMOD: FB Position */ -#define SDMMC_BMOD_FB_Msk (0x01UL << SDMMC_BMOD_FB_Pos) /*!< SDMMC BMOD: FB Mask */ -#define SDMMC_BMOD_DSL_Pos 2 /*!< SDMMC BMOD: DSL Position */ -#define SDMMC_BMOD_DSL_Msk (0x1fUL << SDMMC_BMOD_DSL_Pos) /*!< SDMMC BMOD: DSL Mask */ -#define SDMMC_BMOD_DE_Pos 7 /*!< SDMMC BMOD: DE Position */ -#define SDMMC_BMOD_DE_Msk (0x01UL << SDMMC_BMOD_DE_Pos) /*!< SDMMC BMOD: DE Mask */ -#define SDMMC_BMOD_PBL_Pos 8 /*!< SDMMC BMOD: PBL Position */ -#define SDMMC_BMOD_PBL_Msk (0x07UL << SDMMC_BMOD_PBL_Pos) /*!< SDMMC BMOD: PBL Mask */ - -// -------------------------------------- SDMMC_PLDMND ------------------------------------------ -#define SDMMC_PLDMND_PD_Pos 0 /*!< SDMMC PLDMND: PD Position */ -#define SDMMC_PLDMND_PD_Msk (0xffffffffUL << SDMMC_PLDMND_PD_Pos) /*!< SDMMC PLDMND: PD Mask */ - -// -------------------------------------- SDMMC_DBADDR ------------------------------------------ -#define SDMMC_DBADDR_SDL_Pos 0 /*!< SDMMC DBADDR: SDL Position */ -#define SDMMC_DBADDR_SDL_Msk (0xffffffffUL << SDMMC_DBADDR_SDL_Pos) /*!< SDMMC DBADDR: SDL Mask */ - -// --------------------------------------- SDMMC_IDSTS ------------------------------------------ -#define SDMMC_IDSTS_TI_Pos 0 /*!< SDMMC IDSTS: TI Position */ -#define SDMMC_IDSTS_TI_Msk (0x01UL << SDMMC_IDSTS_TI_Pos) /*!< SDMMC IDSTS: TI Mask */ -#define SDMMC_IDSTS_RI_Pos 1 /*!< SDMMC IDSTS: RI Position */ -#define SDMMC_IDSTS_RI_Msk (0x01UL << SDMMC_IDSTS_RI_Pos) /*!< SDMMC IDSTS: RI Mask */ -#define SDMMC_IDSTS_FBE_Pos 2 /*!< SDMMC IDSTS: FBE Position */ -#define SDMMC_IDSTS_FBE_Msk (0x01UL << SDMMC_IDSTS_FBE_Pos) /*!< SDMMC IDSTS: FBE Mask */ -#define SDMMC_IDSTS_DU_Pos 4 /*!< SDMMC IDSTS: DU Position */ -#define SDMMC_IDSTS_DU_Msk (0x01UL << SDMMC_IDSTS_DU_Pos) /*!< SDMMC IDSTS: DU Mask */ -#define SDMMC_IDSTS_CES_Pos 5 /*!< SDMMC IDSTS: CES Position */ -#define SDMMC_IDSTS_CES_Msk (0x01UL << SDMMC_IDSTS_CES_Pos) /*!< SDMMC IDSTS: CES Mask */ -#define SDMMC_IDSTS_NIS_Pos 8 /*!< SDMMC IDSTS: NIS Position */ -#define SDMMC_IDSTS_NIS_Msk (0x01UL << SDMMC_IDSTS_NIS_Pos) /*!< SDMMC IDSTS: NIS Mask */ -#define SDMMC_IDSTS_AIS_Pos 9 /*!< SDMMC IDSTS: AIS Position */ -#define SDMMC_IDSTS_AIS_Msk (0x01UL << SDMMC_IDSTS_AIS_Pos) /*!< SDMMC IDSTS: AIS Mask */ -#define SDMMC_IDSTS_EB_Pos 10 /*!< SDMMC IDSTS: EB Position */ -#define SDMMC_IDSTS_EB_Msk (0x07UL << SDMMC_IDSTS_EB_Pos) /*!< SDMMC IDSTS: EB Mask */ -#define SDMMC_IDSTS_FSM_Pos 13 /*!< SDMMC IDSTS: FSM Position */ -#define SDMMC_IDSTS_FSM_Msk (0x0fUL << SDMMC_IDSTS_FSM_Pos) /*!< SDMMC IDSTS: FSM Mask */ - -// -------------------------------------- SDMMC_IDINTEN ----------------------------------------- -#define SDMMC_IDINTEN_TI_Pos 0 /*!< SDMMC IDINTEN: TI Position */ -#define SDMMC_IDINTEN_TI_Msk (0x01UL << SDMMC_IDINTEN_TI_Pos) /*!< SDMMC IDINTEN: TI Mask */ -#define SDMMC_IDINTEN_RI_Pos 1 /*!< SDMMC IDINTEN: RI Position */ -#define SDMMC_IDINTEN_RI_Msk (0x01UL << SDMMC_IDINTEN_RI_Pos) /*!< SDMMC IDINTEN: RI Mask */ -#define SDMMC_IDINTEN_FBE_Pos 2 /*!< SDMMC IDINTEN: FBE Position */ -#define SDMMC_IDINTEN_FBE_Msk (0x01UL << SDMMC_IDINTEN_FBE_Pos) /*!< SDMMC IDINTEN: FBE Mask */ -#define SDMMC_IDINTEN_DU_Pos 4 /*!< SDMMC IDINTEN: DU Position */ -#define SDMMC_IDINTEN_DU_Msk (0x01UL << SDMMC_IDINTEN_DU_Pos) /*!< SDMMC IDINTEN: DU Mask */ -#define SDMMC_IDINTEN_CES_Pos 5 /*!< SDMMC IDINTEN: CES Position */ -#define SDMMC_IDINTEN_CES_Msk (0x01UL << SDMMC_IDINTEN_CES_Pos) /*!< SDMMC IDINTEN: CES Mask */ -#define SDMMC_IDINTEN_NIS_Pos 8 /*!< SDMMC IDINTEN: NIS Position */ -#define SDMMC_IDINTEN_NIS_Msk (0x01UL << SDMMC_IDINTEN_NIS_Pos) /*!< SDMMC IDINTEN: NIS Mask */ -#define SDMMC_IDINTEN_AIS_Pos 9 /*!< SDMMC IDINTEN: AIS Position */ -#define SDMMC_IDINTEN_AIS_Msk (0x01UL << SDMMC_IDINTEN_AIS_Pos) /*!< SDMMC IDINTEN: AIS Mask */ - -// -------------------------------------- SDMMC_DSCADDR ----------------------------------------- -#define SDMMC_DSCADDR_HDA_Pos 0 /*!< SDMMC DSCADDR: HDA Position */ -#define SDMMC_DSCADDR_HDA_Msk (0xffffffffUL << SDMMC_DSCADDR_HDA_Pos) /*!< SDMMC DSCADDR: HDA Mask */ - -// -------------------------------------- SDMMC_BUFADDR ----------------------------------------- -#define SDMMC_BUFADDR_HBA_Pos 0 /*!< SDMMC BUFADDR: HBA Position */ -#define SDMMC_BUFADDR_HBA_Msk (0xffffffffUL << SDMMC_BUFADDR_HBA_Pos) /*!< SDMMC BUFADDR: HBA Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- EMC Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- EMC_CONTROL ------------------------------------------ -#define EMC_CONTROL_E_Pos 0 /*!< EMC CONTROL: E Position */ -#define EMC_CONTROL_E_Msk (0x01UL << EMC_CONTROL_E_Pos) /*!< EMC CONTROL: E Mask */ -#define EMC_CONTROL_M_Pos 1 /*!< EMC CONTROL: M Position */ -#define EMC_CONTROL_M_Msk (0x01UL << EMC_CONTROL_M_Pos) /*!< EMC CONTROL: M Mask */ -#define EMC_CONTROL_L_Pos 2 /*!< EMC CONTROL: L Position */ -#define EMC_CONTROL_L_Msk (0x01UL << EMC_CONTROL_L_Pos) /*!< EMC CONTROL: L Mask */ - -// --------------------------------------- EMC_STATUS ------------------------------------------- -#define EMC_STATUS_B_Pos 0 /*!< EMC STATUS: B Position */ -#define EMC_STATUS_B_Msk (0x01UL << EMC_STATUS_B_Pos) /*!< EMC STATUS: B Mask */ -#define EMC_STATUS_S_Pos 1 /*!< EMC STATUS: S Position */ -#define EMC_STATUS_S_Msk (0x01UL << EMC_STATUS_S_Pos) /*!< EMC STATUS: S Mask */ -#define EMC_STATUS_SA_Pos 2 /*!< EMC STATUS: SA Position */ -#define EMC_STATUS_SA_Msk (0x01UL << EMC_STATUS_SA_Pos) /*!< EMC STATUS: SA Mask */ - -// --------------------------------------- EMC_CONFIG ------------------------------------------- -#define EMC_CONFIG_EM_Pos 0 /*!< EMC CONFIG: EM Position */ -#define EMC_CONFIG_EM_Msk (0x01UL << EMC_CONFIG_EM_Pos) /*!< EMC CONFIG: EM Mask */ -#define EMC_CONFIG_CR_Pos 8 /*!< EMC CONFIG: CR Position */ -#define EMC_CONFIG_CR_Msk (0x01UL << EMC_CONFIG_CR_Pos) /*!< EMC CONFIG: CR Mask */ - -// ----------------------------------- EMC_DYNAMICCONTROL --------------------------------------- -#define EMC_DYNAMICCONTROL_CE_Pos 0 /*!< EMC DYNAMICCONTROL: CE Position */ -#define EMC_DYNAMICCONTROL_CE_Msk (0x01UL << EMC_DYNAMICCONTROL_CE_Pos) /*!< EMC DYNAMICCONTROL: CE Mask */ -#define EMC_DYNAMICCONTROL_CS_Pos 1 /*!< EMC DYNAMICCONTROL: CS Position */ -#define EMC_DYNAMICCONTROL_CS_Msk (0x01UL << EMC_DYNAMICCONTROL_CS_Pos) /*!< EMC DYNAMICCONTROL: CS Mask */ -#define EMC_DYNAMICCONTROL_SR_Pos 2 /*!< EMC DYNAMICCONTROL: SR Position */ -#define EMC_DYNAMICCONTROL_SR_Msk (0x01UL << EMC_DYNAMICCONTROL_SR_Pos) /*!< EMC DYNAMICCONTROL: SR Mask */ -#define EMC_DYNAMICCONTROL_MMC_Pos 5 /*!< EMC DYNAMICCONTROL: MMC Position */ -#define EMC_DYNAMICCONTROL_MMC_Msk (0x01UL << EMC_DYNAMICCONTROL_MMC_Pos) /*!< EMC DYNAMICCONTROL: MMC Mask */ -#define EMC_DYNAMICCONTROL_I_Pos 7 /*!< EMC DYNAMICCONTROL: I Position */ -#define EMC_DYNAMICCONTROL_I_Msk (0x03UL << EMC_DYNAMICCONTROL_I_Pos) /*!< EMC DYNAMICCONTROL: I Mask */ -#define EMC_DYNAMICCONTROL_DP_Pos 13 /*!< EMC DYNAMICCONTROL: DP Position */ -#define EMC_DYNAMICCONTROL_DP_Msk (0x01UL << EMC_DYNAMICCONTROL_DP_Pos) /*!< EMC DYNAMICCONTROL: DP Mask */ - -// ----------------------------------- EMC_DYNAMICREFRESH --------------------------------------- -#define EMC_DYNAMICREFRESH_REFRESH_Pos 0 /*!< EMC DYNAMICREFRESH: REFRESH Position */ -#define EMC_DYNAMICREFRESH_REFRESH_Msk (0x000007ffUL << EMC_DYNAMICREFRESH_REFRESH_Pos) /*!< EMC DYNAMICREFRESH: REFRESH Mask */ - -// ---------------------------------- EMC_DYNAMICREADCONFIG ------------------------------------- -#define EMC_DYNAMICREADCONFIG_RD_Pos 0 /*!< EMC DYNAMICREADCONFIG: RD Position */ -#define EMC_DYNAMICREADCONFIG_RD_Msk (0x03UL << EMC_DYNAMICREADCONFIG_RD_Pos) /*!< EMC DYNAMICREADCONFIG: RD Mask */ - -// -------------------------------------- EMC_DYNAMICRP ----------------------------------------- -#define EMC_DYNAMICRP_tRP_Pos 0 /*!< EMC DYNAMICRP: tRP Position */ -#define EMC_DYNAMICRP_tRP_Msk (0x0fUL << EMC_DYNAMICRP_tRP_Pos) /*!< EMC DYNAMICRP: tRP Mask */ - -// ------------------------------------- EMC_DYNAMICRAS ----------------------------------------- -#define EMC_DYNAMICRAS_tRAS_Pos 0 /*!< EMC DYNAMICRAS: tRAS Position */ -#define EMC_DYNAMICRAS_tRAS_Msk (0x0fUL << EMC_DYNAMICRAS_tRAS_Pos) /*!< EMC DYNAMICRAS: tRAS Mask */ - -// ------------------------------------- EMC_DYNAMICSREX ---------------------------------------- -#define EMC_DYNAMICSREX_tSREX_Pos 0 /*!< EMC DYNAMICSREX: tSREX Position */ -#define EMC_DYNAMICSREX_tSREX_Msk (0x0fUL << EMC_DYNAMICSREX_tSREX_Pos) /*!< EMC DYNAMICSREX: tSREX Mask */ - -// ------------------------------------- EMC_DYNAMICAPR ----------------------------------------- -#define EMC_DYNAMICAPR_tAPR_Pos 0 /*!< EMC DYNAMICAPR: tAPR Position */ -#define EMC_DYNAMICAPR_tAPR_Msk (0x0fUL << EMC_DYNAMICAPR_tAPR_Pos) /*!< EMC DYNAMICAPR: tAPR Mask */ - -// ------------------------------------- EMC_DYNAMICDAL ----------------------------------------- -#define EMC_DYNAMICDAL_tDAL_Pos 0 /*!< EMC DYNAMICDAL: tDAL Position */ -#define EMC_DYNAMICDAL_tDAL_Msk (0x0fUL << EMC_DYNAMICDAL_tDAL_Pos) /*!< EMC DYNAMICDAL: tDAL Mask */ - -// -------------------------------------- EMC_DYNAMICWR ----------------------------------------- -#define EMC_DYNAMICWR_tWR_Pos 0 /*!< EMC DYNAMICWR: tWR Position */ -#define EMC_DYNAMICWR_tWR_Msk (0x0fUL << EMC_DYNAMICWR_tWR_Pos) /*!< EMC DYNAMICWR: tWR Mask */ - -// -------------------------------------- EMC_DYNAMICRC ----------------------------------------- -#define EMC_DYNAMICRC_tRC_Pos 0 /*!< EMC DYNAMICRC: tRC Position */ -#define EMC_DYNAMICRC_tRC_Msk (0x1fUL << EMC_DYNAMICRC_tRC_Pos) /*!< EMC DYNAMICRC: tRC Mask */ - -// ------------------------------------- EMC_DYNAMICRFC ----------------------------------------- -#define EMC_DYNAMICRFC_tRFC_Pos 0 /*!< EMC DYNAMICRFC: tRFC Position */ -#define EMC_DYNAMICRFC_tRFC_Msk (0x1fUL << EMC_DYNAMICRFC_tRFC_Pos) /*!< EMC DYNAMICRFC: tRFC Mask */ - -// ------------------------------------- EMC_DYNAMICXSR ----------------------------------------- -#define EMC_DYNAMICXSR_tXSR_Pos 0 /*!< EMC DYNAMICXSR: tXSR Position */ -#define EMC_DYNAMICXSR_tXSR_Msk (0x1fUL << EMC_DYNAMICXSR_tXSR_Pos) /*!< EMC DYNAMICXSR: tXSR Mask */ - -// ------------------------------------- EMC_DYNAMICRRD ----------------------------------------- -#define EMC_DYNAMICRRD_tRRD_Pos 0 /*!< EMC DYNAMICRRD: tRRD Position */ -#define EMC_DYNAMICRRD_tRRD_Msk (0x0fUL << EMC_DYNAMICRRD_tRRD_Pos) /*!< EMC DYNAMICRRD: tRRD Mask */ - -// ------------------------------------- EMC_DYNAMICMRD ----------------------------------------- -#define EMC_DYNAMICMRD_tMRD_Pos 0 /*!< EMC DYNAMICMRD: tMRD Position */ -#define EMC_DYNAMICMRD_tMRD_Msk (0x0fUL << EMC_DYNAMICMRD_tMRD_Pos) /*!< EMC DYNAMICMRD: tMRD Mask */ - -// --------------------------------- EMC_STATICEXTENDEDWAIT ------------------------------------- -#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos 0 /*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Position */ -#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Msk (0x000003ffUL << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos) /*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Mask */ - -// ----------------------------------- EMC_DYNAMICCONFIG0 --------------------------------------- -#define EMC_DYNAMICCONFIG0_MD_Pos 3 /*!< EMC DYNAMICCONFIG0: MD Position */ -#define EMC_DYNAMICCONFIG0_MD_Msk (0x03UL << EMC_DYNAMICCONFIG0_MD_Pos) /*!< EMC DYNAMICCONFIG0: MD Mask */ -#define EMC_DYNAMICCONFIG0_AM0_Pos 7 /*!< EMC DYNAMICCONFIG0: AM0 Position */ -#define EMC_DYNAMICCONFIG0_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG0_AM0_Pos) /*!< EMC DYNAMICCONFIG0: AM0 Mask */ -#define EMC_DYNAMICCONFIG0_AM1_Pos 14 /*!< EMC DYNAMICCONFIG0: AM1 Position */ -#define EMC_DYNAMICCONFIG0_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG0_AM1_Pos) /*!< EMC DYNAMICCONFIG0: AM1 Mask */ -#define EMC_DYNAMICCONFIG0_B_Pos 19 /*!< EMC DYNAMICCONFIG0: B Position */ -#define EMC_DYNAMICCONFIG0_B_Msk (0x01UL << EMC_DYNAMICCONFIG0_B_Pos) /*!< EMC DYNAMICCONFIG0: B Mask */ -#define EMC_DYNAMICCONFIG0_P_Pos 20 /*!< EMC DYNAMICCONFIG0: P Position */ -#define EMC_DYNAMICCONFIG0_P_Msk (0x01UL << EMC_DYNAMICCONFIG0_P_Pos) /*!< EMC DYNAMICCONFIG0: P Mask */ - -// ----------------------------------- EMC_DYNAMICRASCAS0 --------------------------------------- -#define EMC_DYNAMICRASCAS0_RAS_Pos 0 /*!< EMC DYNAMICRASCAS0: RAS Position */ -#define EMC_DYNAMICRASCAS0_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS0_RAS_Pos) /*!< EMC DYNAMICRASCAS0: RAS Mask */ -#define EMC_DYNAMICRASCAS0_CAS_Pos 8 /*!< EMC DYNAMICRASCAS0: CAS Position */ -#define EMC_DYNAMICRASCAS0_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS0_CAS_Pos) /*!< EMC DYNAMICRASCAS0: CAS Mask */ - -// ----------------------------------- EMC_DYNAMICCONFIG1 --------------------------------------- -#define EMC_DYNAMICCONFIG1_MD_Pos 3 /*!< EMC DYNAMICCONFIG1: MD Position */ -#define EMC_DYNAMICCONFIG1_MD_Msk (0x03UL << EMC_DYNAMICCONFIG1_MD_Pos) /*!< EMC DYNAMICCONFIG1: MD Mask */ -#define EMC_DYNAMICCONFIG1_AM0_Pos 7 /*!< EMC DYNAMICCONFIG1: AM0 Position */ -#define EMC_DYNAMICCONFIG1_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG1_AM0_Pos) /*!< EMC DYNAMICCONFIG1: AM0 Mask */ -#define EMC_DYNAMICCONFIG1_AM1_Pos 14 /*!< EMC DYNAMICCONFIG1: AM1 Position */ -#define EMC_DYNAMICCONFIG1_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG1_AM1_Pos) /*!< EMC DYNAMICCONFIG1: AM1 Mask */ -#define EMC_DYNAMICCONFIG1_B_Pos 19 /*!< EMC DYNAMICCONFIG1: B Position */ -#define EMC_DYNAMICCONFIG1_B_Msk (0x01UL << EMC_DYNAMICCONFIG1_B_Pos) /*!< EMC DYNAMICCONFIG1: B Mask */ -#define EMC_DYNAMICCONFIG1_P_Pos 20 /*!< EMC DYNAMICCONFIG1: P Position */ -#define EMC_DYNAMICCONFIG1_P_Msk (0x01UL << EMC_DYNAMICCONFIG1_P_Pos) /*!< EMC DYNAMICCONFIG1: P Mask */ - -// ----------------------------------- EMC_DYNAMICRASCAS1 --------------------------------------- -#define EMC_DYNAMICRASCAS1_RAS_Pos 0 /*!< EMC DYNAMICRASCAS1: RAS Position */ -#define EMC_DYNAMICRASCAS1_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS1_RAS_Pos) /*!< EMC DYNAMICRASCAS1: RAS Mask */ -#define EMC_DYNAMICRASCAS1_CAS_Pos 8 /*!< EMC DYNAMICRASCAS1: CAS Position */ -#define EMC_DYNAMICRASCAS1_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS1_CAS_Pos) /*!< EMC DYNAMICRASCAS1: CAS Mask */ - -// ----------------------------------- EMC_DYNAMICCONFIG2 --------------------------------------- -#define EMC_DYNAMICCONFIG2_MD_Pos 3 /*!< EMC DYNAMICCONFIG2: MD Position */ -#define EMC_DYNAMICCONFIG2_MD_Msk (0x03UL << EMC_DYNAMICCONFIG2_MD_Pos) /*!< EMC DYNAMICCONFIG2: MD Mask */ -#define EMC_DYNAMICCONFIG2_AM0_Pos 7 /*!< EMC DYNAMICCONFIG2: AM0 Position */ -#define EMC_DYNAMICCONFIG2_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG2_AM0_Pos) /*!< EMC DYNAMICCONFIG2: AM0 Mask */ -#define EMC_DYNAMICCONFIG2_AM1_Pos 14 /*!< EMC DYNAMICCONFIG2: AM1 Position */ -#define EMC_DYNAMICCONFIG2_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG2_AM1_Pos) /*!< EMC DYNAMICCONFIG2: AM1 Mask */ -#define EMC_DYNAMICCONFIG2_B_Pos 19 /*!< EMC DYNAMICCONFIG2: B Position */ -#define EMC_DYNAMICCONFIG2_B_Msk (0x01UL << EMC_DYNAMICCONFIG2_B_Pos) /*!< EMC DYNAMICCONFIG2: B Mask */ -#define EMC_DYNAMICCONFIG2_P_Pos 20 /*!< EMC DYNAMICCONFIG2: P Position */ -#define EMC_DYNAMICCONFIG2_P_Msk (0x01UL << EMC_DYNAMICCONFIG2_P_Pos) /*!< EMC DYNAMICCONFIG2: P Mask */ - -// ----------------------------------- EMC_DYNAMICRASCAS2 --------------------------------------- -#define EMC_DYNAMICRASCAS2_RAS_Pos 0 /*!< EMC DYNAMICRASCAS2: RAS Position */ -#define EMC_DYNAMICRASCAS2_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS2_RAS_Pos) /*!< EMC DYNAMICRASCAS2: RAS Mask */ -#define EMC_DYNAMICRASCAS2_CAS_Pos 8 /*!< EMC DYNAMICRASCAS2: CAS Position */ -#define EMC_DYNAMICRASCAS2_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS2_CAS_Pos) /*!< EMC DYNAMICRASCAS2: CAS Mask */ - -// ----------------------------------- EMC_DYNAMICCONFIG3 --------------------------------------- -#define EMC_DYNAMICCONFIG3_MD_Pos 3 /*!< EMC DYNAMICCONFIG3: MD Position */ -#define EMC_DYNAMICCONFIG3_MD_Msk (0x03UL << EMC_DYNAMICCONFIG3_MD_Pos) /*!< EMC DYNAMICCONFIG3: MD Mask */ -#define EMC_DYNAMICCONFIG3_AM0_Pos 7 /*!< EMC DYNAMICCONFIG3: AM0 Position */ -#define EMC_DYNAMICCONFIG3_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG3_AM0_Pos) /*!< EMC DYNAMICCONFIG3: AM0 Mask */ -#define EMC_DYNAMICCONFIG3_AM1_Pos 14 /*!< EMC DYNAMICCONFIG3: AM1 Position */ -#define EMC_DYNAMICCONFIG3_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG3_AM1_Pos) /*!< EMC DYNAMICCONFIG3: AM1 Mask */ -#define EMC_DYNAMICCONFIG3_B_Pos 19 /*!< EMC DYNAMICCONFIG3: B Position */ -#define EMC_DYNAMICCONFIG3_B_Msk (0x01UL << EMC_DYNAMICCONFIG3_B_Pos) /*!< EMC DYNAMICCONFIG3: B Mask */ -#define EMC_DYNAMICCONFIG3_P_Pos 20 /*!< EMC DYNAMICCONFIG3: P Position */ -#define EMC_DYNAMICCONFIG3_P_Msk (0x01UL << EMC_DYNAMICCONFIG3_P_Pos) /*!< EMC DYNAMICCONFIG3: P Mask */ - -// ----------------------------------- EMC_DYNAMICRASCAS3 --------------------------------------- -#define EMC_DYNAMICRASCAS3_RAS_Pos 0 /*!< EMC DYNAMICRASCAS3: RAS Position */ -#define EMC_DYNAMICRASCAS3_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS3_RAS_Pos) /*!< EMC DYNAMICRASCAS3: RAS Mask */ -#define EMC_DYNAMICRASCAS3_CAS_Pos 8 /*!< EMC DYNAMICRASCAS3: CAS Position */ -#define EMC_DYNAMICRASCAS3_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS3_CAS_Pos) /*!< EMC DYNAMICRASCAS3: CAS Mask */ - -// ------------------------------------ EMC_STATICCONFIG0 --------------------------------------- -#define EMC_STATICCONFIG0_MW_Pos 0 /*!< EMC STATICCONFIG0: MW Position */ -#define EMC_STATICCONFIG0_MW_Msk (0x03UL << EMC_STATICCONFIG0_MW_Pos) /*!< EMC STATICCONFIG0: MW Mask */ -#define EMC_STATICCONFIG0_PM_Pos 3 /*!< EMC STATICCONFIG0: PM Position */ -#define EMC_STATICCONFIG0_PM_Msk (0x01UL << EMC_STATICCONFIG0_PM_Pos) /*!< EMC STATICCONFIG0: PM Mask */ -#define EMC_STATICCONFIG0_PC_Pos 6 /*!< EMC STATICCONFIG0: PC Position */ -#define EMC_STATICCONFIG0_PC_Msk (0x01UL << EMC_STATICCONFIG0_PC_Pos) /*!< EMC STATICCONFIG0: PC Mask */ -#define EMC_STATICCONFIG0_PB_Pos 7 /*!< EMC STATICCONFIG0: PB Position */ -#define EMC_STATICCONFIG0_PB_Msk (0x01UL << EMC_STATICCONFIG0_PB_Pos) /*!< EMC STATICCONFIG0: PB Mask */ -#define EMC_STATICCONFIG0_EW_Pos 8 /*!< EMC STATICCONFIG0: EW Position */ -#define EMC_STATICCONFIG0_EW_Msk (0x01UL << EMC_STATICCONFIG0_EW_Pos) /*!< EMC STATICCONFIG0: EW Mask */ -#define EMC_STATICCONFIG0_B_Pos 19 /*!< EMC STATICCONFIG0: B Position */ -#define EMC_STATICCONFIG0_B_Msk (0x01UL << EMC_STATICCONFIG0_B_Pos) /*!< EMC STATICCONFIG0: B Mask */ -#define EMC_STATICCONFIG0_P_Pos 20 /*!< EMC STATICCONFIG0: P Position */ -#define EMC_STATICCONFIG0_P_Msk (0x01UL << EMC_STATICCONFIG0_P_Pos) /*!< EMC STATICCONFIG0: P Mask */ - -// ----------------------------------- EMC_STATICWAITWEN0 --------------------------------------- -#define EMC_STATICWAITWEN0_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN0: WAITWEN Position */ -#define EMC_STATICWAITWEN0_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN0_WAITWEN_Pos) /*!< EMC STATICWAITWEN0: WAITWEN Mask */ - -// ----------------------------------- EMC_STATICWAITOEN0 --------------------------------------- -#define EMC_STATICWAITOEN0_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN0: WAITOEN Position */ -#define EMC_STATICWAITOEN0_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN0_WAITOEN_Pos) /*!< EMC STATICWAITOEN0: WAITOEN Mask */ - -// ------------------------------------ EMC_STATICWAITRD0 --------------------------------------- -#define EMC_STATICWAITRD0_WAITRD_Pos 0 /*!< EMC STATICWAITRD0: WAITRD Position */ -#define EMC_STATICWAITRD0_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD0_WAITRD_Pos) /*!< EMC STATICWAITRD0: WAITRD Mask */ - -// ----------------------------------- EMC_STATICWAITPAG0 --------------------------------------- -#define EMC_STATICWAITPAG0_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAG0: WAITPAGE Position */ -#define EMC_STATICWAITPAG0_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAG0_WAITPAGE_Pos) /*!< EMC STATICWAITPAG0: WAITPAGE Mask */ - -// ------------------------------------ EMC_STATICWAITWR0 --------------------------------------- -#define EMC_STATICWAITWR0_WAITWR_Pos 0 /*!< EMC STATICWAITWR0: WAITWR Position */ -#define EMC_STATICWAITWR0_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR0_WAITWR_Pos) /*!< EMC STATICWAITWR0: WAITWR Mask */ - -// ----------------------------------- EMC_STATICWAITTURN0 -------------------------------------- -#define EMC_STATICWAITTURN0_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN0: WAITTURN Position */ -#define EMC_STATICWAITTURN0_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN0_WAITTURN_Pos) /*!< EMC STATICWAITTURN0: WAITTURN Mask */ - -// ------------------------------------ EMC_STATICCONFIG1 --------------------------------------- -#define EMC_STATICCONFIG1_MW_Pos 0 /*!< EMC STATICCONFIG1: MW Position */ -#define EMC_STATICCONFIG1_MW_Msk (0x03UL << EMC_STATICCONFIG1_MW_Pos) /*!< EMC STATICCONFIG1: MW Mask */ -#define EMC_STATICCONFIG1_PM_Pos 3 /*!< EMC STATICCONFIG1: PM Position */ -#define EMC_STATICCONFIG1_PM_Msk (0x01UL << EMC_STATICCONFIG1_PM_Pos) /*!< EMC STATICCONFIG1: PM Mask */ -#define EMC_STATICCONFIG1_PC_Pos 6 /*!< EMC STATICCONFIG1: PC Position */ -#define EMC_STATICCONFIG1_PC_Msk (0x01UL << EMC_STATICCONFIG1_PC_Pos) /*!< EMC STATICCONFIG1: PC Mask */ -#define EMC_STATICCONFIG1_PB_Pos 7 /*!< EMC STATICCONFIG1: PB Position */ -#define EMC_STATICCONFIG1_PB_Msk (0x01UL << EMC_STATICCONFIG1_PB_Pos) /*!< EMC STATICCONFIG1: PB Mask */ -#define EMC_STATICCONFIG1_EW_Pos 8 /*!< EMC STATICCONFIG1: EW Position */ -#define EMC_STATICCONFIG1_EW_Msk (0x01UL << EMC_STATICCONFIG1_EW_Pos) /*!< EMC STATICCONFIG1: EW Mask */ -#define EMC_STATICCONFIG1_B_Pos 19 /*!< EMC STATICCONFIG1: B Position */ -#define EMC_STATICCONFIG1_B_Msk (0x01UL << EMC_STATICCONFIG1_B_Pos) /*!< EMC STATICCONFIG1: B Mask */ -#define EMC_STATICCONFIG1_P_Pos 20 /*!< EMC STATICCONFIG1: P Position */ -#define EMC_STATICCONFIG1_P_Msk (0x01UL << EMC_STATICCONFIG1_P_Pos) /*!< EMC STATICCONFIG1: P Mask */ - -// ----------------------------------- EMC_STATICWAITWEN1 --------------------------------------- -#define EMC_STATICWAITWEN1_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN1: WAITWEN Position */ -#define EMC_STATICWAITWEN1_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN1_WAITWEN_Pos) /*!< EMC STATICWAITWEN1: WAITWEN Mask */ - -// ----------------------------------- EMC_STATICWAITOEN1 --------------------------------------- -#define EMC_STATICWAITOEN1_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN1: WAITOEN Position */ -#define EMC_STATICWAITOEN1_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN1_WAITOEN_Pos) /*!< EMC STATICWAITOEN1: WAITOEN Mask */ - -// ------------------------------------ EMC_STATICWAITRD1 --------------------------------------- -#define EMC_STATICWAITRD1_WAITRD_Pos 0 /*!< EMC STATICWAITRD1: WAITRD Position */ -#define EMC_STATICWAITRD1_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD1_WAITRD_Pos) /*!< EMC STATICWAITRD1: WAITRD Mask */ - -// ----------------------------------- EMC_STATICWAITPAG1 --------------------------------------- -#define EMC_STATICWAITPAG1_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAG1: WAITPAGE Position */ -#define EMC_STATICWAITPAG1_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAG1_WAITPAGE_Pos) /*!< EMC STATICWAITPAG1: WAITPAGE Mask */ - -// ------------------------------------ EMC_STATICWAITWR1 --------------------------------------- -#define EMC_STATICWAITWR1_WAITWR_Pos 0 /*!< EMC STATICWAITWR1: WAITWR Position */ -#define EMC_STATICWAITWR1_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR1_WAITWR_Pos) /*!< EMC STATICWAITWR1: WAITWR Mask */ - -// ----------------------------------- EMC_STATICWAITTURN1 -------------------------------------- -#define EMC_STATICWAITTURN1_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN1: WAITTURN Position */ -#define EMC_STATICWAITTURN1_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN1_WAITTURN_Pos) /*!< EMC STATICWAITTURN1: WAITTURN Mask */ - -// ------------------------------------ EMC_STATICCONFIG2 --------------------------------------- -#define EMC_STATICCONFIG2_MW_Pos 0 /*!< EMC STATICCONFIG2: MW Position */ -#define EMC_STATICCONFIG2_MW_Msk (0x03UL << EMC_STATICCONFIG2_MW_Pos) /*!< EMC STATICCONFIG2: MW Mask */ -#define EMC_STATICCONFIG2_PM_Pos 3 /*!< EMC STATICCONFIG2: PM Position */ -#define EMC_STATICCONFIG2_PM_Msk (0x01UL << EMC_STATICCONFIG2_PM_Pos) /*!< EMC STATICCONFIG2: PM Mask */ -#define EMC_STATICCONFIG2_PC_Pos 6 /*!< EMC STATICCONFIG2: PC Position */ -#define EMC_STATICCONFIG2_PC_Msk (0x01UL << EMC_STATICCONFIG2_PC_Pos) /*!< EMC STATICCONFIG2: PC Mask */ -#define EMC_STATICCONFIG2_PB_Pos 7 /*!< EMC STATICCONFIG2: PB Position */ -#define EMC_STATICCONFIG2_PB_Msk (0x01UL << EMC_STATICCONFIG2_PB_Pos) /*!< EMC STATICCONFIG2: PB Mask */ -#define EMC_STATICCONFIG2_EW_Pos 8 /*!< EMC STATICCONFIG2: EW Position */ -#define EMC_STATICCONFIG2_EW_Msk (0x01UL << EMC_STATICCONFIG2_EW_Pos) /*!< EMC STATICCONFIG2: EW Mask */ -#define EMC_STATICCONFIG2_B_Pos 19 /*!< EMC STATICCONFIG2: B Position */ -#define EMC_STATICCONFIG2_B_Msk (0x01UL << EMC_STATICCONFIG2_B_Pos) /*!< EMC STATICCONFIG2: B Mask */ -#define EMC_STATICCONFIG2_P_Pos 20 /*!< EMC STATICCONFIG2: P Position */ -#define EMC_STATICCONFIG2_P_Msk (0x01UL << EMC_STATICCONFIG2_P_Pos) /*!< EMC STATICCONFIG2: P Mask */ - -// ----------------------------------- EMC_STATICWAITWEN2 --------------------------------------- -#define EMC_STATICWAITWEN2_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN2: WAITWEN Position */ -#define EMC_STATICWAITWEN2_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN2_WAITWEN_Pos) /*!< EMC STATICWAITWEN2: WAITWEN Mask */ - -// ----------------------------------- EMC_STATICWAITOEN2 --------------------------------------- -#define EMC_STATICWAITOEN2_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN2: WAITOEN Position */ -#define EMC_STATICWAITOEN2_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN2_WAITOEN_Pos) /*!< EMC STATICWAITOEN2: WAITOEN Mask */ - -// ------------------------------------ EMC_STATICWAITRD2 --------------------------------------- -#define EMC_STATICWAITRD2_WAITRD_Pos 0 /*!< EMC STATICWAITRD2: WAITRD Position */ -#define EMC_STATICWAITRD2_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD2_WAITRD_Pos) /*!< EMC STATICWAITRD2: WAITRD Mask */ - -// ----------------------------------- EMC_STATICWAITPAG2 --------------------------------------- -#define EMC_STATICWAITPAG2_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAG2: WAITPAGE Position */ -#define EMC_STATICWAITPAG2_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAG2_WAITPAGE_Pos) /*!< EMC STATICWAITPAG2: WAITPAGE Mask */ - -// ------------------------------------ EMC_STATICWAITWR2 --------------------------------------- -#define EMC_STATICWAITWR2_WAITWR_Pos 0 /*!< EMC STATICWAITWR2: WAITWR Position */ -#define EMC_STATICWAITWR2_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR2_WAITWR_Pos) /*!< EMC STATICWAITWR2: WAITWR Mask */ - -// ----------------------------------- EMC_STATICWAITTURN2 -------------------------------------- -#define EMC_STATICWAITTURN2_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN2: WAITTURN Position */ -#define EMC_STATICWAITTURN2_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN2_WAITTURN_Pos) /*!< EMC STATICWAITTURN2: WAITTURN Mask */ - -// ------------------------------------ EMC_STATICCONFIG3 --------------------------------------- -#define EMC_STATICCONFIG3_MW_Pos 0 /*!< EMC STATICCONFIG3: MW Position */ -#define EMC_STATICCONFIG3_MW_Msk (0x03UL << EMC_STATICCONFIG3_MW_Pos) /*!< EMC STATICCONFIG3: MW Mask */ -#define EMC_STATICCONFIG3_PM_Pos 3 /*!< EMC STATICCONFIG3: PM Position */ -#define EMC_STATICCONFIG3_PM_Msk (0x01UL << EMC_STATICCONFIG3_PM_Pos) /*!< EMC STATICCONFIG3: PM Mask */ -#define EMC_STATICCONFIG3_PC_Pos 6 /*!< EMC STATICCONFIG3: PC Position */ -#define EMC_STATICCONFIG3_PC_Msk (0x01UL << EMC_STATICCONFIG3_PC_Pos) /*!< EMC STATICCONFIG3: PC Mask */ -#define EMC_STATICCONFIG3_PB_Pos 7 /*!< EMC STATICCONFIG3: PB Position */ -#define EMC_STATICCONFIG3_PB_Msk (0x01UL << EMC_STATICCONFIG3_PB_Pos) /*!< EMC STATICCONFIG3: PB Mask */ -#define EMC_STATICCONFIG3_EW_Pos 8 /*!< EMC STATICCONFIG3: EW Position */ -#define EMC_STATICCONFIG3_EW_Msk (0x01UL << EMC_STATICCONFIG3_EW_Pos) /*!< EMC STATICCONFIG3: EW Mask */ -#define EMC_STATICCONFIG3_B_Pos 19 /*!< EMC STATICCONFIG3: B Position */ -#define EMC_STATICCONFIG3_B_Msk (0x01UL << EMC_STATICCONFIG3_B_Pos) /*!< EMC STATICCONFIG3: B Mask */ -#define EMC_STATICCONFIG3_P_Pos 20 /*!< EMC STATICCONFIG3: P Position */ -#define EMC_STATICCONFIG3_P_Msk (0x01UL << EMC_STATICCONFIG3_P_Pos) /*!< EMC STATICCONFIG3: P Mask */ - -// ----------------------------------- EMC_STATICWAITWEN3 --------------------------------------- -#define EMC_STATICWAITWEN3_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN3: WAITWEN Position */ -#define EMC_STATICWAITWEN3_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN3_WAITWEN_Pos) /*!< EMC STATICWAITWEN3: WAITWEN Mask */ - -// ----------------------------------- EMC_STATICWAITOEN3 --------------------------------------- -#define EMC_STATICWAITOEN3_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN3: WAITOEN Position */ -#define EMC_STATICWAITOEN3_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN3_WAITOEN_Pos) /*!< EMC STATICWAITOEN3: WAITOEN Mask */ - -// ------------------------------------ EMC_STATICWAITRD3 --------------------------------------- -#define EMC_STATICWAITRD3_WAITRD_Pos 0 /*!< EMC STATICWAITRD3: WAITRD Position */ -#define EMC_STATICWAITRD3_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD3_WAITRD_Pos) /*!< EMC STATICWAITRD3: WAITRD Mask */ - -// ----------------------------------- EMC_STATICWAITPAG3 --------------------------------------- -#define EMC_STATICWAITPAG3_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAG3: WAITPAGE Position */ -#define EMC_STATICWAITPAG3_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAG3_WAITPAGE_Pos) /*!< EMC STATICWAITPAG3: WAITPAGE Mask */ - -// ------------------------------------ EMC_STATICWAITWR3 --------------------------------------- -#define EMC_STATICWAITWR3_WAITWR_Pos 0 /*!< EMC STATICWAITWR3: WAITWR Position */ -#define EMC_STATICWAITWR3_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR3_WAITWR_Pos) /*!< EMC STATICWAITWR3: WAITWR Mask */ - -// ----------------------------------- EMC_STATICWAITTURN3 -------------------------------------- -#define EMC_STATICWAITTURN3_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN3: WAITTURN Position */ -#define EMC_STATICWAITTURN3_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN3_WAITTURN_Pos) /*!< EMC STATICWAITTURN3: WAITTURN Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- USB0 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ------------------------------------- USB0_CAPLENGTH ----------------------------------------- -#define USB0_CAPLENGTH_CAPLENGTH_Pos 0 /*!< USB0 CAPLENGTH: CAPLENGTH Position */ -#define USB0_CAPLENGTH_CAPLENGTH_Msk (0x000000ffUL << USB0_CAPLENGTH_CAPLENGTH_Pos) /*!< USB0 CAPLENGTH: CAPLENGTH Mask */ -#define USB0_CAPLENGTH_HCIVERSION_Pos 8 /*!< USB0 CAPLENGTH: HCIVERSION Position */ -#define USB0_CAPLENGTH_HCIVERSION_Msk (0x0000ffffUL << USB0_CAPLENGTH_HCIVERSION_Pos) /*!< USB0 CAPLENGTH: HCIVERSION Mask */ - -// ------------------------------------- USB0_HCSPARAMS ----------------------------------------- -#define USB0_HCSPARAMS_N_PORTS_Pos 0 /*!< USB0 HCSPARAMS: N_PORTS Position */ -#define USB0_HCSPARAMS_N_PORTS_Msk (0x0fUL << USB0_HCSPARAMS_N_PORTS_Pos) /*!< USB0 HCSPARAMS: N_PORTS Mask */ -#define USB0_HCSPARAMS_PPC_Pos 4 /*!< USB0 HCSPARAMS: PPC Position */ -#define USB0_HCSPARAMS_PPC_Msk (0x01UL << USB0_HCSPARAMS_PPC_Pos) /*!< USB0 HCSPARAMS: PPC Mask */ -#define USB0_HCSPARAMS_N_PCC_Pos 8 /*!< USB0 HCSPARAMS: N_PCC Position */ -#define USB0_HCSPARAMS_N_PCC_Msk (0x0fUL << USB0_HCSPARAMS_N_PCC_Pos) /*!< USB0 HCSPARAMS: N_PCC Mask */ -#define USB0_HCSPARAMS_N_CC_Pos 12 /*!< USB0 HCSPARAMS: N_CC Position */ -#define USB0_HCSPARAMS_N_CC_Msk (0x0fUL << USB0_HCSPARAMS_N_CC_Pos) /*!< USB0 HCSPARAMS: N_CC Mask */ -#define USB0_HCSPARAMS_PI_Pos 16 /*!< USB0 HCSPARAMS: PI Position */ -#define USB0_HCSPARAMS_PI_Msk (0x01UL << USB0_HCSPARAMS_PI_Pos) /*!< USB0 HCSPARAMS: PI Mask */ -#define USB0_HCSPARAMS_N_PTT_Pos 20 /*!< USB0 HCSPARAMS: N_PTT Position */ -#define USB0_HCSPARAMS_N_PTT_Msk (0x0fUL << USB0_HCSPARAMS_N_PTT_Pos) /*!< USB0 HCSPARAMS: N_PTT Mask */ -#define USB0_HCSPARAMS_N_TT_Pos 24 /*!< USB0 HCSPARAMS: N_TT Position */ -#define USB0_HCSPARAMS_N_TT_Msk (0x0fUL << USB0_HCSPARAMS_N_TT_Pos) /*!< USB0 HCSPARAMS: N_TT Mask */ - -// ------------------------------------- USB0_HCCPARAMS ----------------------------------------- -#define USB0_HCCPARAMS_ADC_Pos 0 /*!< USB0 HCCPARAMS: ADC Position */ -#define USB0_HCCPARAMS_ADC_Msk (0x01UL << USB0_HCCPARAMS_ADC_Pos) /*!< USB0 HCCPARAMS: ADC Mask */ -#define USB0_HCCPARAMS_PFL_Pos 1 /*!< USB0 HCCPARAMS: PFL Position */ -#define USB0_HCCPARAMS_PFL_Msk (0x01UL << USB0_HCCPARAMS_PFL_Pos) /*!< USB0 HCCPARAMS: PFL Mask */ -#define USB0_HCCPARAMS_ASP_Pos 2 /*!< USB0 HCCPARAMS: ASP Position */ -#define USB0_HCCPARAMS_ASP_Msk (0x01UL << USB0_HCCPARAMS_ASP_Pos) /*!< USB0 HCCPARAMS: ASP Mask */ -#define USB0_HCCPARAMS_IST_Pos 4 /*!< USB0 HCCPARAMS: IST Position */ -#define USB0_HCCPARAMS_IST_Msk (0x0fUL << USB0_HCCPARAMS_IST_Pos) /*!< USB0 HCCPARAMS: IST Mask */ -#define USB0_HCCPARAMS_EECP_Pos 8 /*!< USB0 HCCPARAMS: EECP Position */ -#define USB0_HCCPARAMS_EECP_Msk (0x000000ffUL << USB0_HCCPARAMS_EECP_Pos) /*!< USB0 HCCPARAMS: EECP Mask */ - -// ------------------------------------- USB0_DCIVERSION ---------------------------------------- -#define USB0_DCIVERSION_DCIVERSION_Pos 0 /*!< USB0 DCIVERSION: DCIVERSION Position */ -#define USB0_DCIVERSION_DCIVERSION_Msk (0x0000ffffUL << USB0_DCIVERSION_DCIVERSION_Pos) /*!< USB0 DCIVERSION: DCIVERSION Mask */ - -// -------------------------------------- USB0_USBCMD_D ----------------------------------------- -#define USB0_USBCMD_D_RS_Pos 0 /*!< USB0 USBCMD_D: RS Position */ -#define USB0_USBCMD_D_RS_Msk (0x01UL << USB0_USBCMD_D_RS_Pos) /*!< USB0 USBCMD_D: RS Mask */ -#define USB0_USBCMD_D_RST_Pos 1 /*!< USB0 USBCMD_D: RST Position */ -#define USB0_USBCMD_D_RST_Msk (0x01UL << USB0_USBCMD_D_RST_Pos) /*!< USB0 USBCMD_D: RST Mask */ -#define USB0_USBCMD_D_SUTW_Pos 13 /*!< USB0 USBCMD_D: SUTW Position */ -#define USB0_USBCMD_D_SUTW_Msk (0x01UL << USB0_USBCMD_D_SUTW_Pos) /*!< USB0 USBCMD_D: SUTW Mask */ -#define USB0_USBCMD_D_ATDTW_Pos 14 /*!< USB0 USBCMD_D: ATDTW Position */ -#define USB0_USBCMD_D_ATDTW_Msk (0x01UL << USB0_USBCMD_D_ATDTW_Pos) /*!< USB0 USBCMD_D: ATDTW Mask */ -#define USB0_USBCMD_D_ITC_Pos 16 /*!< USB0 USBCMD_D: ITC Position */ -#define USB0_USBCMD_D_ITC_Msk (0x000000ffUL << USB0_USBCMD_D_ITC_Pos) /*!< USB0 USBCMD_D: ITC Mask */ - -// -------------------------------------- USB0_USBCMD_H ----------------------------------------- -#define USB0_USBCMD_H_RS_Pos 0 /*!< USB0 USBCMD_H: RS Position */ -#define USB0_USBCMD_H_RS_Msk (0x01UL << USB0_USBCMD_H_RS_Pos) /*!< USB0 USBCMD_H: RS Mask */ -#define USB0_USBCMD_H_RST_Pos 1 /*!< USB0 USBCMD_H: RST Position */ -#define USB0_USBCMD_H_RST_Msk (0x01UL << USB0_USBCMD_H_RST_Pos) /*!< USB0 USBCMD_H: RST Mask */ -#define USB0_USBCMD_H_FS0_Pos 2 /*!< USB0 USBCMD_H: FS0 Position */ -#define USB0_USBCMD_H_FS0_Msk (0x01UL << USB0_USBCMD_H_FS0_Pos) /*!< USB0 USBCMD_H: FS0 Mask */ -#define USB0_USBCMD_H_FS1_Pos 3 /*!< USB0 USBCMD_H: FS1 Position */ -#define USB0_USBCMD_H_FS1_Msk (0x01UL << USB0_USBCMD_H_FS1_Pos) /*!< USB0 USBCMD_H: FS1 Mask */ -#define USB0_USBCMD_H_PSE_Pos 4 /*!< USB0 USBCMD_H: PSE Position */ -#define USB0_USBCMD_H_PSE_Msk (0x01UL << USB0_USBCMD_H_PSE_Pos) /*!< USB0 USBCMD_H: PSE Mask */ -#define USB0_USBCMD_H_ASE_Pos 5 /*!< USB0 USBCMD_H: ASE Position */ -#define USB0_USBCMD_H_ASE_Msk (0x01UL << USB0_USBCMD_H_ASE_Pos) /*!< USB0 USBCMD_H: ASE Mask */ -#define USB0_USBCMD_H_IAA_Pos 6 /*!< USB0 USBCMD_H: IAA Position */ -#define USB0_USBCMD_H_IAA_Msk (0x01UL << USB0_USBCMD_H_IAA_Pos) /*!< USB0 USBCMD_H: IAA Mask */ -#define USB0_USBCMD_H_ASP1_0_Pos 8 /*!< USB0 USBCMD_H: ASP1_0 Position */ -#define USB0_USBCMD_H_ASP1_0_Msk (0x03UL << USB0_USBCMD_H_ASP1_0_Pos) /*!< USB0 USBCMD_H: ASP1_0 Mask */ -#define USB0_USBCMD_H_ASPE_Pos 11 /*!< USB0 USBCMD_H: ASPE Position */ -#define USB0_USBCMD_H_ASPE_Msk (0x01UL << USB0_USBCMD_H_ASPE_Pos) /*!< USB0 USBCMD_H: ASPE Mask */ -#define USB0_USBCMD_H_FS2_Pos 15 /*!< USB0 USBCMD_H: FS2 Position */ -#define USB0_USBCMD_H_FS2_Msk (0x01UL << USB0_USBCMD_H_FS2_Pos) /*!< USB0 USBCMD_H: FS2 Mask */ -#define USB0_USBCMD_H_ITC_Pos 16 /*!< USB0 USBCMD_H: ITC Position */ -#define USB0_USBCMD_H_ITC_Msk (0x000000ffUL << USB0_USBCMD_H_ITC_Pos) /*!< USB0 USBCMD_H: ITC Mask */ - -// -------------------------------------- USB0_USBSTS_D ----------------------------------------- -#define USB0_USBSTS_D_UI_Pos 0 /*!< USB0 USBSTS_D: UI Position */ -#define USB0_USBSTS_D_UI_Msk (0x01UL << USB0_USBSTS_D_UI_Pos) /*!< USB0 USBSTS_D: UI Mask */ -#define USB0_USBSTS_D_UEI_Pos 1 /*!< USB0 USBSTS_D: UEI Position */ -#define USB0_USBSTS_D_UEI_Msk (0x01UL << USB0_USBSTS_D_UEI_Pos) /*!< USB0 USBSTS_D: UEI Mask */ -#define USB0_USBSTS_D_PCI_Pos 2 /*!< USB0 USBSTS_D: PCI Position */ -#define USB0_USBSTS_D_PCI_Msk (0x01UL << USB0_USBSTS_D_PCI_Pos) /*!< USB0 USBSTS_D: PCI Mask */ -#define USB0_USBSTS_D_AAI_Pos 5 /*!< USB0 USBSTS_D: AAI Position */ -#define USB0_USBSTS_D_AAI_Msk (0x01UL << USB0_USBSTS_D_AAI_Pos) /*!< USB0 USBSTS_D: AAI Mask */ -#define USB0_USBSTS_D_URI_Pos 6 /*!< USB0 USBSTS_D: URI Position */ -#define USB0_USBSTS_D_URI_Msk (0x01UL << USB0_USBSTS_D_URI_Pos) /*!< USB0 USBSTS_D: URI Mask */ -#define USB0_USBSTS_D_SRI_Pos 7 /*!< USB0 USBSTS_D: SRI Position */ -#define USB0_USBSTS_D_SRI_Msk (0x01UL << USB0_USBSTS_D_SRI_Pos) /*!< USB0 USBSTS_D: SRI Mask */ -#define USB0_USBSTS_D_SLI_Pos 8 /*!< USB0 USBSTS_D: SLI Position */ -#define USB0_USBSTS_D_SLI_Msk (0x01UL << USB0_USBSTS_D_SLI_Pos) /*!< USB0 USBSTS_D: SLI Mask */ -#define USB0_USBSTS_D_NAKI_Pos 16 /*!< USB0 USBSTS_D: NAKI Position */ -#define USB0_USBSTS_D_NAKI_Msk (0x01UL << USB0_USBSTS_D_NAKI_Pos) /*!< USB0 USBSTS_D: NAKI Mask */ - -// -------------------------------------- USB0_USBSTS_H ----------------------------------------- -#define USB0_USBSTS_H_UI_Pos 0 /*!< USB0 USBSTS_H: UI Position */ -#define USB0_USBSTS_H_UI_Msk (0x01UL << USB0_USBSTS_H_UI_Pos) /*!< USB0 USBSTS_H: UI Mask */ -#define USB0_USBSTS_H_UEI_Pos 1 /*!< USB0 USBSTS_H: UEI Position */ -#define USB0_USBSTS_H_UEI_Msk (0x01UL << USB0_USBSTS_H_UEI_Pos) /*!< USB0 USBSTS_H: UEI Mask */ -#define USB0_USBSTS_H_PCI_Pos 2 /*!< USB0 USBSTS_H: PCI Position */ -#define USB0_USBSTS_H_PCI_Msk (0x01UL << USB0_USBSTS_H_PCI_Pos) /*!< USB0 USBSTS_H: PCI Mask */ -#define USB0_USBSTS_H_FRI_Pos 3 /*!< USB0 USBSTS_H: FRI Position */ -#define USB0_USBSTS_H_FRI_Msk (0x01UL << USB0_USBSTS_H_FRI_Pos) /*!< USB0 USBSTS_H: FRI Mask */ -#define USB0_USBSTS_H_AAI_Pos 5 /*!< USB0 USBSTS_H: AAI Position */ -#define USB0_USBSTS_H_AAI_Msk (0x01UL << USB0_USBSTS_H_AAI_Pos) /*!< USB0 USBSTS_H: AAI Mask */ -#define USB0_USBSTS_H_SRI_Pos 7 /*!< USB0 USBSTS_H: SRI Position */ -#define USB0_USBSTS_H_SRI_Msk (0x01UL << USB0_USBSTS_H_SRI_Pos) /*!< USB0 USBSTS_H: SRI Mask */ -#define USB0_USBSTS_H_HCH_Pos 12 /*!< USB0 USBSTS_H: HCH Position */ -#define USB0_USBSTS_H_HCH_Msk (0x01UL << USB0_USBSTS_H_HCH_Pos) /*!< USB0 USBSTS_H: HCH Mask */ -#define USB0_USBSTS_H_RCL_Pos 13 /*!< USB0 USBSTS_H: RCL Position */ -#define USB0_USBSTS_H_RCL_Msk (0x01UL << USB0_USBSTS_H_RCL_Pos) /*!< USB0 USBSTS_H: RCL Mask */ -#define USB0_USBSTS_H_PS_Pos 14 /*!< USB0 USBSTS_H: PS Position */ -#define USB0_USBSTS_H_PS_Msk (0x01UL << USB0_USBSTS_H_PS_Pos) /*!< USB0 USBSTS_H: PS Mask */ -#define USB0_USBSTS_H_AS_Pos 15 /*!< USB0 USBSTS_H: AS Position */ -#define USB0_USBSTS_H_AS_Msk (0x01UL << USB0_USBSTS_H_AS_Pos) /*!< USB0 USBSTS_H: AS Mask */ -#define USB0_USBSTS_H_UAI_Pos 18 /*!< USB0 USBSTS_H: UAI Position */ -#define USB0_USBSTS_H_UAI_Msk (0x01UL << USB0_USBSTS_H_UAI_Pos) /*!< USB0 USBSTS_H: UAI Mask */ -#define USB0_USBSTS_H_UPI_Pos 19 /*!< USB0 USBSTS_H: UPI Position */ -#define USB0_USBSTS_H_UPI_Msk (0x01UL << USB0_USBSTS_H_UPI_Pos) /*!< USB0 USBSTS_H: UPI Mask */ - -// ------------------------------------- USB0_USBINTR_D ----------------------------------------- -#define USB0_USBINTR_D_UE_Pos 0 /*!< USB0 USBINTR_D: UE Position */ -#define USB0_USBINTR_D_UE_Msk (0x01UL << USB0_USBINTR_D_UE_Pos) /*!< USB0 USBINTR_D: UE Mask */ -#define USB0_USBINTR_D_UEE_Pos 1 /*!< USB0 USBINTR_D: UEE Position */ -#define USB0_USBINTR_D_UEE_Msk (0x01UL << USB0_USBINTR_D_UEE_Pos) /*!< USB0 USBINTR_D: UEE Mask */ -#define USB0_USBINTR_D_PCE_Pos 2 /*!< USB0 USBINTR_D: PCE Position */ -#define USB0_USBINTR_D_PCE_Msk (0x01UL << USB0_USBINTR_D_PCE_Pos) /*!< USB0 USBINTR_D: PCE Mask */ -#define USB0_USBINTR_D_URE_Pos 6 /*!< USB0 USBINTR_D: URE Position */ -#define USB0_USBINTR_D_URE_Msk (0x01UL << USB0_USBINTR_D_URE_Pos) /*!< USB0 USBINTR_D: URE Mask */ -#define USB0_USBINTR_D_SRE_Pos 7 /*!< USB0 USBINTR_D: SRE Position */ -#define USB0_USBINTR_D_SRE_Msk (0x01UL << USB0_USBINTR_D_SRE_Pos) /*!< USB0 USBINTR_D: SRE Mask */ -#define USB0_USBINTR_D_SLE_Pos 8 /*!< USB0 USBINTR_D: SLE Position */ -#define USB0_USBINTR_D_SLE_Msk (0x01UL << USB0_USBINTR_D_SLE_Pos) /*!< USB0 USBINTR_D: SLE Mask */ -#define USB0_USBINTR_D_NAKE_Pos 16 /*!< USB0 USBINTR_D: NAKE Position */ -#define USB0_USBINTR_D_NAKE_Msk (0x01UL << USB0_USBINTR_D_NAKE_Pos) /*!< USB0 USBINTR_D: NAKE Mask */ - -// ------------------------------------- USB0_USBINTR_H ----------------------------------------- -#define USB0_USBINTR_H_UE_Pos 0 /*!< USB0 USBINTR_H: UE Position */ -#define USB0_USBINTR_H_UE_Msk (0x01UL << USB0_USBINTR_H_UE_Pos) /*!< USB0 USBINTR_H: UE Mask */ -#define USB0_USBINTR_H_UEE_Pos 1 /*!< USB0 USBINTR_H: UEE Position */ -#define USB0_USBINTR_H_UEE_Msk (0x01UL << USB0_USBINTR_H_UEE_Pos) /*!< USB0 USBINTR_H: UEE Mask */ -#define USB0_USBINTR_H_PCE_Pos 2 /*!< USB0 USBINTR_H: PCE Position */ -#define USB0_USBINTR_H_PCE_Msk (0x01UL << USB0_USBINTR_H_PCE_Pos) /*!< USB0 USBINTR_H: PCE Mask */ -#define USB0_USBINTR_H_FRE_Pos 3 /*!< USB0 USBINTR_H: FRE Position */ -#define USB0_USBINTR_H_FRE_Msk (0x01UL << USB0_USBINTR_H_FRE_Pos) /*!< USB0 USBINTR_H: FRE Mask */ -#define USB0_USBINTR_H_AAE_Pos 5 /*!< USB0 USBINTR_H: AAE Position */ -#define USB0_USBINTR_H_AAE_Msk (0x01UL << USB0_USBINTR_H_AAE_Pos) /*!< USB0 USBINTR_H: AAE Mask */ -#define USB0_USBINTR_H_SRE_Pos 7 /*!< USB0 USBINTR_H: SRE Position */ -#define USB0_USBINTR_H_SRE_Msk (0x01UL << USB0_USBINTR_H_SRE_Pos) /*!< USB0 USBINTR_H: SRE Mask */ -#define USB0_USBINTR_H_UAIE_Pos 18 /*!< USB0 USBINTR_H: UAIE Position */ -#define USB0_USBINTR_H_UAIE_Msk (0x01UL << USB0_USBINTR_H_UAIE_Pos) /*!< USB0 USBINTR_H: UAIE Mask */ -#define USB0_USBINTR_H_UPIA_Pos 19 /*!< USB0 USBINTR_H: UPIA Position */ -#define USB0_USBINTR_H_UPIA_Msk (0x01UL << USB0_USBINTR_H_UPIA_Pos) /*!< USB0 USBINTR_H: UPIA Mask */ - -// ------------------------------------- USB0_FRINDEX_D ----------------------------------------- -#define USB0_FRINDEX_D_FRINDEX2_0_Pos 0 /*!< USB0 FRINDEX_D: FRINDEX2_0 Position */ -#define USB0_FRINDEX_D_FRINDEX2_0_Msk (0x07UL << USB0_FRINDEX_D_FRINDEX2_0_Pos) /*!< USB0 FRINDEX_D: FRINDEX2_0 Mask */ -#define USB0_FRINDEX_D_FRINDEX13_3_Pos 3 /*!< USB0 FRINDEX_D: FRINDEX13_3 Position */ -#define USB0_FRINDEX_D_FRINDEX13_3_Msk (0x000007ffUL << USB0_FRINDEX_D_FRINDEX13_3_Pos) /*!< USB0 FRINDEX_D: FRINDEX13_3 Mask */ - -// ------------------------------------- USB0_FRINDEX_H ----------------------------------------- -#define USB0_FRINDEX_H_FRINDEX2_0_Pos 0 /*!< USB0 FRINDEX_H: FRINDEX2_0 Position */ -#define USB0_FRINDEX_H_FRINDEX2_0_Msk (0x07UL << USB0_FRINDEX_H_FRINDEX2_0_Pos) /*!< USB0 FRINDEX_H: FRINDEX2_0 Mask */ -#define USB0_FRINDEX_H_FRINDEX12_3_Pos 3 /*!< USB0 FRINDEX_H: FRINDEX12_3 Position */ -#define USB0_FRINDEX_H_FRINDEX12_3_Msk (0x000003ffUL << USB0_FRINDEX_H_FRINDEX12_3_Pos) /*!< USB0 FRINDEX_H: FRINDEX12_3 Mask */ - -// ------------------------------------- USB0_DEVICEADDR ---------------------------------------- -#define USB0_DEVICEADDR_USBADRA_Pos 24 /*!< USB0 DEVICEADDR: USBADRA Position */ -#define USB0_DEVICEADDR_USBADRA_Msk (0x01UL << USB0_DEVICEADDR_USBADRA_Pos) /*!< USB0 DEVICEADDR: USBADRA Mask */ -#define USB0_DEVICEADDR_USBADR_Pos 25 /*!< USB0 DEVICEADDR: USBADR Position */ -#define USB0_DEVICEADDR_USBADR_Msk (0x7fUL << USB0_DEVICEADDR_USBADR_Pos) /*!< USB0 DEVICEADDR: USBADR Mask */ - -// ---------------------------------- USB0_PERIODICLISTBASE ------------------------------------- -#define USB0_PERIODICLISTBASE_PERBASE31_12_Pos 12 /*!< USB0 PERIODICLISTBASE: PERBASE31_12 Position */ -#define USB0_PERIODICLISTBASE_PERBASE31_12_Msk (0x000fffffUL << USB0_PERIODICLISTBASE_PERBASE31_12_Pos) /*!< USB0 PERIODICLISTBASE: PERBASE31_12 Mask */ - -// ---------------------------------- USB0_ENDPOINTLISTADDR ------------------------------------- -#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos 11 /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Position */ -#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Msk (0x001fffffUL << USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos) /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Mask */ - -// ----------------------------------- USB0_ASYNCLISTADDR --------------------------------------- -#define USB0_ASYNCLISTADDR_ASYBASE31_5_Pos 5 /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Position */ -#define USB0_ASYNCLISTADDR_ASYBASE31_5_Msk (0x07ffffffUL << USB0_ASYNCLISTADDR_ASYBASE31_5_Pos) /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Mask */ - -// --------------------------------------- USB0_TTCTRL ------------------------------------------ -#define USB0_TTCTRL_TTHA_Pos 24 /*!< USB0 TTCTRL: TTHA Position */ -#define USB0_TTCTRL_TTHA_Msk (0x7fUL << USB0_TTCTRL_TTHA_Pos) /*!< USB0 TTCTRL: TTHA Mask */ - -// ------------------------------------- USB0_BURSTSIZE ----------------------------------------- -#define USB0_BURSTSIZE_RXPBURST_Pos 0 /*!< USB0 BURSTSIZE: RXPBURST Position */ -#define USB0_BURSTSIZE_RXPBURST_Msk (0x000000ffUL << USB0_BURSTSIZE_RXPBURST_Pos) /*!< USB0 BURSTSIZE: RXPBURST Mask */ -#define USB0_BURSTSIZE_TXPBURST_Pos 8 /*!< USB0 BURSTSIZE: TXPBURST Position */ -#define USB0_BURSTSIZE_TXPBURST_Msk (0x000000ffUL << USB0_BURSTSIZE_TXPBURST_Pos) /*!< USB0 BURSTSIZE: TXPBURST Mask */ - -// ------------------------------------ USB0_TXFILLTUNING --------------------------------------- -#define USB0_TXFILLTUNING_TXSCHOH_Pos 0 /*!< USB0 TXFILLTUNING: TXSCHOH Position */ -#define USB0_TXFILLTUNING_TXSCHOH_Msk (0x000000ffUL << USB0_TXFILLTUNING_TXSCHOH_Pos) /*!< USB0 TXFILLTUNING: TXSCHOH Mask */ -#define USB0_TXFILLTUNING_TXSCHEATLTH_Pos 8 /*!< USB0 TXFILLTUNING: TXSCHEATLTH Position */ -#define USB0_TXFILLTUNING_TXSCHEATLTH_Msk (0x1fUL << USB0_TXFILLTUNING_TXSCHEATLTH_Pos) /*!< USB0 TXFILLTUNING: TXSCHEATLTH Mask */ -#define USB0_TXFILLTUNING_TXFIFOTHRES_Pos 16 /*!< USB0 TXFILLTUNING: TXFIFOTHRES Position */ -#define USB0_TXFILLTUNING_TXFIFOTHRES_Msk (0x3fUL << USB0_TXFILLTUNING_TXFIFOTHRES_Pos) /*!< USB0 TXFILLTUNING: TXFIFOTHRES Mask */ - -// ------------------------------------- USB0_BINTERVAL ----------------------------------------- -#define USB0_BINTERVAL_BINT_Pos 0 /*!< USB0 BINTERVAL: BINT Position */ -#define USB0_BINTERVAL_BINT_Msk (0x0fUL << USB0_BINTERVAL_BINT_Pos) /*!< USB0 BINTERVAL: BINT Mask */ - -// -------------------------------------- USB0_ENDPTNAK ----------------------------------------- -#define USB0_ENDPTNAK_EPRN0_Pos 0 /*!< USB0 ENDPTNAK: EPRN0 Position */ -#define USB0_ENDPTNAK_EPRN0_Msk (0x01UL << USB0_ENDPTNAK_EPRN0_Pos) /*!< USB0 ENDPTNAK: EPRN0 Mask */ -#define USB0_ENDPTNAK_EPRN1_Pos 1 /*!< USB0 ENDPTNAK: EPRN1 Position */ -#define USB0_ENDPTNAK_EPRN1_Msk (0x01UL << USB0_ENDPTNAK_EPRN1_Pos) /*!< USB0 ENDPTNAK: EPRN1 Mask */ -#define USB0_ENDPTNAK_EPRN2_Pos 2 /*!< USB0 ENDPTNAK: EPRN2 Position */ -#define USB0_ENDPTNAK_EPRN2_Msk (0x01UL << USB0_ENDPTNAK_EPRN2_Pos) /*!< USB0 ENDPTNAK: EPRN2 Mask */ -#define USB0_ENDPTNAK_EPRN3_Pos 3 /*!< USB0 ENDPTNAK: EPRN3 Position */ -#define USB0_ENDPTNAK_EPRN3_Msk (0x01UL << USB0_ENDPTNAK_EPRN3_Pos) /*!< USB0 ENDPTNAK: EPRN3 Mask */ -#define USB0_ENDPTNAK_EPRN4_Pos 4 /*!< USB0 ENDPTNAK: EPRN4 Position */ -#define USB0_ENDPTNAK_EPRN4_Msk (0x01UL << USB0_ENDPTNAK_EPRN4_Pos) /*!< USB0 ENDPTNAK: EPRN4 Mask */ -#define USB0_ENDPTNAK_EPRN5_Pos 5 /*!< USB0 ENDPTNAK: EPRN5 Position */ -#define USB0_ENDPTNAK_EPRN5_Msk (0x01UL << USB0_ENDPTNAK_EPRN5_Pos) /*!< USB0 ENDPTNAK: EPRN5 Mask */ -#define USB0_ENDPTNAK_EPTN0_Pos 16 /*!< USB0 ENDPTNAK: EPTN0 Position */ -#define USB0_ENDPTNAK_EPTN0_Msk (0x01UL << USB0_ENDPTNAK_EPTN0_Pos) /*!< USB0 ENDPTNAK: EPTN0 Mask */ -#define USB0_ENDPTNAK_EPTN1_Pos 17 /*!< USB0 ENDPTNAK: EPTN1 Position */ -#define USB0_ENDPTNAK_EPTN1_Msk (0x01UL << USB0_ENDPTNAK_EPTN1_Pos) /*!< USB0 ENDPTNAK: EPTN1 Mask */ -#define USB0_ENDPTNAK_EPTN2_Pos 18 /*!< USB0 ENDPTNAK: EPTN2 Position */ -#define USB0_ENDPTNAK_EPTN2_Msk (0x01UL << USB0_ENDPTNAK_EPTN2_Pos) /*!< USB0 ENDPTNAK: EPTN2 Mask */ -#define USB0_ENDPTNAK_EPTN3_Pos 19 /*!< USB0 ENDPTNAK: EPTN3 Position */ -#define USB0_ENDPTNAK_EPTN3_Msk (0x01UL << USB0_ENDPTNAK_EPTN3_Pos) /*!< USB0 ENDPTNAK: EPTN3 Mask */ -#define USB0_ENDPTNAK_EPTN4_Pos 20 /*!< USB0 ENDPTNAK: EPTN4 Position */ -#define USB0_ENDPTNAK_EPTN4_Msk (0x01UL << USB0_ENDPTNAK_EPTN4_Pos) /*!< USB0 ENDPTNAK: EPTN4 Mask */ -#define USB0_ENDPTNAK_EPTN5_Pos 21 /*!< USB0 ENDPTNAK: EPTN5 Position */ -#define USB0_ENDPTNAK_EPTN5_Msk (0x01UL << USB0_ENDPTNAK_EPTN5_Pos) /*!< USB0 ENDPTNAK: EPTN5 Mask */ - -// ------------------------------------- USB0_ENDPTNAKEN ---------------------------------------- -#define USB0_ENDPTNAKEN_EPRNE0_Pos 0 /*!< USB0 ENDPTNAKEN: EPRNE0 Position */ -#define USB0_ENDPTNAKEN_EPRNE0_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE0_Pos) /*!< USB0 ENDPTNAKEN: EPRNE0 Mask */ -#define USB0_ENDPTNAKEN_EPRNE1_Pos 1 /*!< USB0 ENDPTNAKEN: EPRNE1 Position */ -#define USB0_ENDPTNAKEN_EPRNE1_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE1_Pos) /*!< USB0 ENDPTNAKEN: EPRNE1 Mask */ -#define USB0_ENDPTNAKEN_EPRNE2_Pos 2 /*!< USB0 ENDPTNAKEN: EPRNE2 Position */ -#define USB0_ENDPTNAKEN_EPRNE2_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE2_Pos) /*!< USB0 ENDPTNAKEN: EPRNE2 Mask */ -#define USB0_ENDPTNAKEN_EPRNE3_Pos 3 /*!< USB0 ENDPTNAKEN: EPRNE3 Position */ -#define USB0_ENDPTNAKEN_EPRNE3_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE3_Pos) /*!< USB0 ENDPTNAKEN: EPRNE3 Mask */ -#define USB0_ENDPTNAKEN_EPRNE4_Pos 4 /*!< USB0 ENDPTNAKEN: EPRNE4 Position */ -#define USB0_ENDPTNAKEN_EPRNE4_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE4_Pos) /*!< USB0 ENDPTNAKEN: EPRNE4 Mask */ -#define USB0_ENDPTNAKEN_EPRNE5_Pos 5 /*!< USB0 ENDPTNAKEN: EPRNE5 Position */ -#define USB0_ENDPTNAKEN_EPRNE5_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE5_Pos) /*!< USB0 ENDPTNAKEN: EPRNE5 Mask */ -#define USB0_ENDPTNAKEN_EPTNE0_Pos 16 /*!< USB0 ENDPTNAKEN: EPTNE0 Position */ -#define USB0_ENDPTNAKEN_EPTNE0_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE0_Pos) /*!< USB0 ENDPTNAKEN: EPTNE0 Mask */ -#define USB0_ENDPTNAKEN_EPTNE1_Pos 17 /*!< USB0 ENDPTNAKEN: EPTNE1 Position */ -#define USB0_ENDPTNAKEN_EPTNE1_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE1_Pos) /*!< USB0 ENDPTNAKEN: EPTNE1 Mask */ -#define USB0_ENDPTNAKEN_EPTNE2_Pos 18 /*!< USB0 ENDPTNAKEN: EPTNE2 Position */ -#define USB0_ENDPTNAKEN_EPTNE2_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE2_Pos) /*!< USB0 ENDPTNAKEN: EPTNE2 Mask */ -#define USB0_ENDPTNAKEN_EPTNE3_Pos 19 /*!< USB0 ENDPTNAKEN: EPTNE3 Position */ -#define USB0_ENDPTNAKEN_EPTNE3_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE3_Pos) /*!< USB0 ENDPTNAKEN: EPTNE3 Mask */ -#define USB0_ENDPTNAKEN_EPTNE4_Pos 20 /*!< USB0 ENDPTNAKEN: EPTNE4 Position */ -#define USB0_ENDPTNAKEN_EPTNE4_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE4_Pos) /*!< USB0 ENDPTNAKEN: EPTNE4 Mask */ -#define USB0_ENDPTNAKEN_EPTNE5_Pos 21 /*!< USB0 ENDPTNAKEN: EPTNE5 Position */ -#define USB0_ENDPTNAKEN_EPTNE5_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE5_Pos) /*!< USB0 ENDPTNAKEN: EPTNE5 Mask */ - -// ------------------------------------- USB0_PORTSC1_D ----------------------------------------- -#define USB0_PORTSC1_D_CCS_Pos 0 /*!< USB0 PORTSC1_D: CCS Position */ -#define USB0_PORTSC1_D_CCS_Msk (0x01UL << USB0_PORTSC1_D_CCS_Pos) /*!< USB0 PORTSC1_D: CCS Mask */ -#define USB0_PORTSC1_D_PE_Pos 2 /*!< USB0 PORTSC1_D: PE Position */ -#define USB0_PORTSC1_D_PE_Msk (0x01UL << USB0_PORTSC1_D_PE_Pos) /*!< USB0 PORTSC1_D: PE Mask */ -#define USB0_PORTSC1_D_PEC_Pos 3 /*!< USB0 PORTSC1_D: PEC Position */ -#define USB0_PORTSC1_D_PEC_Msk (0x01UL << USB0_PORTSC1_D_PEC_Pos) /*!< USB0 PORTSC1_D: PEC Mask */ -#define USB0_PORTSC1_D_FPR_Pos 6 /*!< USB0 PORTSC1_D: FPR Position */ -#define USB0_PORTSC1_D_FPR_Msk (0x01UL << USB0_PORTSC1_D_FPR_Pos) /*!< USB0 PORTSC1_D: FPR Mask */ -#define USB0_PORTSC1_D_SUSP_Pos 7 /*!< USB0 PORTSC1_D: SUSP Position */ -#define USB0_PORTSC1_D_SUSP_Msk (0x01UL << USB0_PORTSC1_D_SUSP_Pos) /*!< USB0 PORTSC1_D: SUSP Mask */ -#define USB0_PORTSC1_D_PR_Pos 8 /*!< USB0 PORTSC1_D: PR Position */ -#define USB0_PORTSC1_D_PR_Msk (0x01UL << USB0_PORTSC1_D_PR_Pos) /*!< USB0 PORTSC1_D: PR Mask */ -#define USB0_PORTSC1_D_HSP_Pos 9 /*!< USB0 PORTSC1_D: HSP Position */ -#define USB0_PORTSC1_D_HSP_Msk (0x01UL << USB0_PORTSC1_D_HSP_Pos) /*!< USB0 PORTSC1_D: HSP Mask */ -#define USB0_PORTSC1_D_PIC1_0_Pos 14 /*!< USB0 PORTSC1_D: PIC1_0 Position */ -#define USB0_PORTSC1_D_PIC1_0_Msk (0x03UL << USB0_PORTSC1_D_PIC1_0_Pos) /*!< USB0 PORTSC1_D: PIC1_0 Mask */ -#define USB0_PORTSC1_D_PTC3_0_Pos 16 /*!< USB0 PORTSC1_D: PTC3_0 Position */ -#define USB0_PORTSC1_D_PTC3_0_Msk (0x0fUL << USB0_PORTSC1_D_PTC3_0_Pos) /*!< USB0 PORTSC1_D: PTC3_0 Mask */ -#define USB0_PORTSC1_D_PHCD_Pos 23 /*!< USB0 PORTSC1_D: PHCD Position */ -#define USB0_PORTSC1_D_PHCD_Msk (0x01UL << USB0_PORTSC1_D_PHCD_Pos) /*!< USB0 PORTSC1_D: PHCD Mask */ -#define USB0_PORTSC1_D_PFSC_Pos 24 /*!< USB0 PORTSC1_D: PFSC Position */ -#define USB0_PORTSC1_D_PFSC_Msk (0x01UL << USB0_PORTSC1_D_PFSC_Pos) /*!< USB0 PORTSC1_D: PFSC Mask */ -#define USB0_PORTSC1_D_PSPD_Pos 26 /*!< USB0 PORTSC1_D: PSPD Position */ -#define USB0_PORTSC1_D_PSPD_Msk (0x03UL << USB0_PORTSC1_D_PSPD_Pos) /*!< USB0 PORTSC1_D: PSPD Mask */ - -// ------------------------------------- USB0_PORTSC1_H ----------------------------------------- -#define USB0_PORTSC1_H_CCS_Pos 0 /*!< USB0 PORTSC1_H: CCS Position */ -#define USB0_PORTSC1_H_CCS_Msk (0x01UL << USB0_PORTSC1_H_CCS_Pos) /*!< USB0 PORTSC1_H: CCS Mask */ -#define USB0_PORTSC1_H_CSC_Pos 1 /*!< USB0 PORTSC1_H: CSC Position */ -#define USB0_PORTSC1_H_CSC_Msk (0x01UL << USB0_PORTSC1_H_CSC_Pos) /*!< USB0 PORTSC1_H: CSC Mask */ -#define USB0_PORTSC1_H_PE_Pos 2 /*!< USB0 PORTSC1_H: PE Position */ -#define USB0_PORTSC1_H_PE_Msk (0x01UL << USB0_PORTSC1_H_PE_Pos) /*!< USB0 PORTSC1_H: PE Mask */ -#define USB0_PORTSC1_H_PEC_Pos 3 /*!< USB0 PORTSC1_H: PEC Position */ -#define USB0_PORTSC1_H_PEC_Msk (0x01UL << USB0_PORTSC1_H_PEC_Pos) /*!< USB0 PORTSC1_H: PEC Mask */ -#define USB0_PORTSC1_H_OCA_Pos 4 /*!< USB0 PORTSC1_H: OCA Position */ -#define USB0_PORTSC1_H_OCA_Msk (0x01UL << USB0_PORTSC1_H_OCA_Pos) /*!< USB0 PORTSC1_H: OCA Mask */ -#define USB0_PORTSC1_H_OCC_Pos 5 /*!< USB0 PORTSC1_H: OCC Position */ -#define USB0_PORTSC1_H_OCC_Msk (0x01UL << USB0_PORTSC1_H_OCC_Pos) /*!< USB0 PORTSC1_H: OCC Mask */ -#define USB0_PORTSC1_H_FPR_Pos 6 /*!< USB0 PORTSC1_H: FPR Position */ -#define USB0_PORTSC1_H_FPR_Msk (0x01UL << USB0_PORTSC1_H_FPR_Pos) /*!< USB0 PORTSC1_H: FPR Mask */ -#define USB0_PORTSC1_H_SUSP_Pos 7 /*!< USB0 PORTSC1_H: SUSP Position */ -#define USB0_PORTSC1_H_SUSP_Msk (0x01UL << USB0_PORTSC1_H_SUSP_Pos) /*!< USB0 PORTSC1_H: SUSP Mask */ -#define USB0_PORTSC1_H_PR_Pos 8 /*!< USB0 PORTSC1_H: PR Position */ -#define USB0_PORTSC1_H_PR_Msk (0x01UL << USB0_PORTSC1_H_PR_Pos) /*!< USB0 PORTSC1_H: PR Mask */ -#define USB0_PORTSC1_H_HSP_Pos 9 /*!< USB0 PORTSC1_H: HSP Position */ -#define USB0_PORTSC1_H_HSP_Msk (0x01UL << USB0_PORTSC1_H_HSP_Pos) /*!< USB0 PORTSC1_H: HSP Mask */ -#define USB0_PORTSC1_H_LS_Pos 10 /*!< USB0 PORTSC1_H: LS Position */ -#define USB0_PORTSC1_H_LS_Msk (0x03UL << USB0_PORTSC1_H_LS_Pos) /*!< USB0 PORTSC1_H: LS Mask */ -#define USB0_PORTSC1_H_PP_Pos 12 /*!< USB0 PORTSC1_H: PP Position */ -#define USB0_PORTSC1_H_PP_Msk (0x01UL << USB0_PORTSC1_H_PP_Pos) /*!< USB0 PORTSC1_H: PP Mask */ -#define USB0_PORTSC1_H_PIC1_0_Pos 14 /*!< USB0 PORTSC1_H: PIC1_0 Position */ -#define USB0_PORTSC1_H_PIC1_0_Msk (0x03UL << USB0_PORTSC1_H_PIC1_0_Pos) /*!< USB0 PORTSC1_H: PIC1_0 Mask */ -#define USB0_PORTSC1_H_PTC3_0_Pos 16 /*!< USB0 PORTSC1_H: PTC3_0 Position */ -#define USB0_PORTSC1_H_PTC3_0_Msk (0x0fUL << USB0_PORTSC1_H_PTC3_0_Pos) /*!< USB0 PORTSC1_H: PTC3_0 Mask */ -#define USB0_PORTSC1_H_WKCN_Pos 20 /*!< USB0 PORTSC1_H: WKCN Position */ -#define USB0_PORTSC1_H_WKCN_Msk (0x01UL << USB0_PORTSC1_H_WKCN_Pos) /*!< USB0 PORTSC1_H: WKCN Mask */ -#define USB0_PORTSC1_H_WKDC_Pos 21 /*!< USB0 PORTSC1_H: WKDC Position */ -#define USB0_PORTSC1_H_WKDC_Msk (0x01UL << USB0_PORTSC1_H_WKDC_Pos) /*!< USB0 PORTSC1_H: WKDC Mask */ -#define USB0_PORTSC1_H_WKOC_Pos 22 /*!< USB0 PORTSC1_H: WKOC Position */ -#define USB0_PORTSC1_H_WKOC_Msk (0x01UL << USB0_PORTSC1_H_WKOC_Pos) /*!< USB0 PORTSC1_H: WKOC Mask */ -#define USB0_PORTSC1_H_PHCD_Pos 23 /*!< USB0 PORTSC1_H: PHCD Position */ -#define USB0_PORTSC1_H_PHCD_Msk (0x01UL << USB0_PORTSC1_H_PHCD_Pos) /*!< USB0 PORTSC1_H: PHCD Mask */ -#define USB0_PORTSC1_H_PFSC_Pos 24 /*!< USB0 PORTSC1_H: PFSC Position */ -#define USB0_PORTSC1_H_PFSC_Msk (0x01UL << USB0_PORTSC1_H_PFSC_Pos) /*!< USB0 PORTSC1_H: PFSC Mask */ -#define USB0_PORTSC1_H_PSPD_Pos 26 /*!< USB0 PORTSC1_H: PSPD Position */ -#define USB0_PORTSC1_H_PSPD_Msk (0x03UL << USB0_PORTSC1_H_PSPD_Pos) /*!< USB0 PORTSC1_H: PSPD Mask */ - -// --------------------------------------- USB0_OTGSC ------------------------------------------- -#define USB0_OTGSC_VD_Pos 0 /*!< USB0 OTGSC: VD Position */ -#define USB0_OTGSC_VD_Msk (0x01UL << USB0_OTGSC_VD_Pos) /*!< USB0 OTGSC: VD Mask */ -#define USB0_OTGSC_VC_Pos 1 /*!< USB0 OTGSC: VC Position */ -#define USB0_OTGSC_VC_Msk (0x01UL << USB0_OTGSC_VC_Pos) /*!< USB0 OTGSC: VC Mask */ -#define USB0_OTGSC_HAAR_Pos 2 /*!< USB0 OTGSC: HAAR Position */ -#define USB0_OTGSC_HAAR_Msk (0x01UL << USB0_OTGSC_HAAR_Pos) /*!< USB0 OTGSC: HAAR Mask */ -#define USB0_OTGSC_OT_Pos 3 /*!< USB0 OTGSC: OT Position */ -#define USB0_OTGSC_OT_Msk (0x01UL << USB0_OTGSC_OT_Pos) /*!< USB0 OTGSC: OT Mask */ -#define USB0_OTGSC_DP_Pos 4 /*!< USB0 OTGSC: DP Position */ -#define USB0_OTGSC_DP_Msk (0x01UL << USB0_OTGSC_DP_Pos) /*!< USB0 OTGSC: DP Mask */ -#define USB0_OTGSC_IDPU_Pos 5 /*!< USB0 OTGSC: IDPU Position */ -#define USB0_OTGSC_IDPU_Msk (0x01UL << USB0_OTGSC_IDPU_Pos) /*!< USB0 OTGSC: IDPU Mask */ -#define USB0_OTGSC_HADP_Pos 6 /*!< USB0 OTGSC: HADP Position */ -#define USB0_OTGSC_HADP_Msk (0x01UL << USB0_OTGSC_HADP_Pos) /*!< USB0 OTGSC: HADP Mask */ -#define USB0_OTGSC_HABA_Pos 7 /*!< USB0 OTGSC: HABA Position */ -#define USB0_OTGSC_HABA_Msk (0x01UL << USB0_OTGSC_HABA_Pos) /*!< USB0 OTGSC: HABA Mask */ -#define USB0_OTGSC_ID_Pos 8 /*!< USB0 OTGSC: ID Position */ -#define USB0_OTGSC_ID_Msk (0x01UL << USB0_OTGSC_ID_Pos) /*!< USB0 OTGSC: ID Mask */ -#define USB0_OTGSC_AVV_Pos 9 /*!< USB0 OTGSC: AVV Position */ -#define USB0_OTGSC_AVV_Msk (0x01UL << USB0_OTGSC_AVV_Pos) /*!< USB0 OTGSC: AVV Mask */ -#define USB0_OTGSC_ASV_Pos 10 /*!< USB0 OTGSC: ASV Position */ -#define USB0_OTGSC_ASV_Msk (0x01UL << USB0_OTGSC_ASV_Pos) /*!< USB0 OTGSC: ASV Mask */ -#define USB0_OTGSC_BSV_Pos 11 /*!< USB0 OTGSC: BSV Position */ -#define USB0_OTGSC_BSV_Msk (0x01UL << USB0_OTGSC_BSV_Pos) /*!< USB0 OTGSC: BSV Mask */ -#define USB0_OTGSC_BSE_Pos 12 /*!< USB0 OTGSC: BSE Position */ -#define USB0_OTGSC_BSE_Msk (0x01UL << USB0_OTGSC_BSE_Pos) /*!< USB0 OTGSC: BSE Mask */ -#define USB0_OTGSC_MS1T_Pos 13 /*!< USB0 OTGSC: MS1T Position */ -#define USB0_OTGSC_MS1T_Msk (0x01UL << USB0_OTGSC_MS1T_Pos) /*!< USB0 OTGSC: MS1T Mask */ -#define USB0_OTGSC_DPS_Pos 14 /*!< USB0 OTGSC: DPS Position */ -#define USB0_OTGSC_DPS_Msk (0x01UL << USB0_OTGSC_DPS_Pos) /*!< USB0 OTGSC: DPS Mask */ -#define USB0_OTGSC_IDIS_Pos 16 /*!< USB0 OTGSC: IDIS Position */ -#define USB0_OTGSC_IDIS_Msk (0x01UL << USB0_OTGSC_IDIS_Pos) /*!< USB0 OTGSC: IDIS Mask */ -#define USB0_OTGSC_AVVIS_Pos 17 /*!< USB0 OTGSC: AVVIS Position */ -#define USB0_OTGSC_AVVIS_Msk (0x01UL << USB0_OTGSC_AVVIS_Pos) /*!< USB0 OTGSC: AVVIS Mask */ -#define USB0_OTGSC_ASVIS_Pos 18 /*!< USB0 OTGSC: ASVIS Position */ -#define USB0_OTGSC_ASVIS_Msk (0x01UL << USB0_OTGSC_ASVIS_Pos) /*!< USB0 OTGSC: ASVIS Mask */ -#define USB0_OTGSC_BSVIS_Pos 19 /*!< USB0 OTGSC: BSVIS Position */ -#define USB0_OTGSC_BSVIS_Msk (0x01UL << USB0_OTGSC_BSVIS_Pos) /*!< USB0 OTGSC: BSVIS Mask */ -#define USB0_OTGSC_BSEIS_Pos 20 /*!< USB0 OTGSC: BSEIS Position */ -#define USB0_OTGSC_BSEIS_Msk (0x01UL << USB0_OTGSC_BSEIS_Pos) /*!< USB0 OTGSC: BSEIS Mask */ -#define USB0_OTGSC_ms1S_Pos 21 /*!< USB0 OTGSC: ms1S Position */ -#define USB0_OTGSC_ms1S_Msk (0x01UL << USB0_OTGSC_ms1S_Pos) /*!< USB0 OTGSC: ms1S Mask */ -#define USB0_OTGSC_DPIS_Pos 22 /*!< USB0 OTGSC: DPIS Position */ -#define USB0_OTGSC_DPIS_Msk (0x01UL << USB0_OTGSC_DPIS_Pos) /*!< USB0 OTGSC: DPIS Mask */ -#define USB0_OTGSC_IDIE_Pos 24 /*!< USB0 OTGSC: IDIE Position */ -#define USB0_OTGSC_IDIE_Msk (0x01UL << USB0_OTGSC_IDIE_Pos) /*!< USB0 OTGSC: IDIE Mask */ -#define USB0_OTGSC_AVVIE_Pos 25 /*!< USB0 OTGSC: AVVIE Position */ -#define USB0_OTGSC_AVVIE_Msk (0x01UL << USB0_OTGSC_AVVIE_Pos) /*!< USB0 OTGSC: AVVIE Mask */ -#define USB0_OTGSC_ASVIE_Pos 26 /*!< USB0 OTGSC: ASVIE Position */ -#define USB0_OTGSC_ASVIE_Msk (0x01UL << USB0_OTGSC_ASVIE_Pos) /*!< USB0 OTGSC: ASVIE Mask */ -#define USB0_OTGSC_BSVIE_Pos 27 /*!< USB0 OTGSC: BSVIE Position */ -#define USB0_OTGSC_BSVIE_Msk (0x01UL << USB0_OTGSC_BSVIE_Pos) /*!< USB0 OTGSC: BSVIE Mask */ -#define USB0_OTGSC_BSEIE_Pos 28 /*!< USB0 OTGSC: BSEIE Position */ -#define USB0_OTGSC_BSEIE_Msk (0x01UL << USB0_OTGSC_BSEIE_Pos) /*!< USB0 OTGSC: BSEIE Mask */ -#define USB0_OTGSC_MS1E_Pos 29 /*!< USB0 OTGSC: MS1E Position */ -#define USB0_OTGSC_MS1E_Msk (0x01UL << USB0_OTGSC_MS1E_Pos) /*!< USB0 OTGSC: MS1E Mask */ -#define USB0_OTGSC_DPIE_Pos 30 /*!< USB0 OTGSC: DPIE Position */ -#define USB0_OTGSC_DPIE_Msk (0x01UL << USB0_OTGSC_DPIE_Pos) /*!< USB0 OTGSC: DPIE Mask */ - -// ------------------------------------- USB0_USBMODE_D ----------------------------------------- -#define USB0_USBMODE_D_CM1_0_Pos 0 /*!< USB0 USBMODE_D: CM1_0 Position */ -#define USB0_USBMODE_D_CM1_0_Msk (0x03UL << USB0_USBMODE_D_CM1_0_Pos) /*!< USB0 USBMODE_D: CM1_0 Mask */ -#define USB0_USBMODE_D_ES_Pos 2 /*!< USB0 USBMODE_D: ES Position */ -#define USB0_USBMODE_D_ES_Msk (0x01UL << USB0_USBMODE_D_ES_Pos) /*!< USB0 USBMODE_D: ES Mask */ -#define USB0_USBMODE_D_SLOM_Pos 3 /*!< USB0 USBMODE_D: SLOM Position */ -#define USB0_USBMODE_D_SLOM_Msk (0x01UL << USB0_USBMODE_D_SLOM_Pos) /*!< USB0 USBMODE_D: SLOM Mask */ -#define USB0_USBMODE_D_SDIS_Pos 4 /*!< USB0 USBMODE_D: SDIS Position */ -#define USB0_USBMODE_D_SDIS_Msk (0x01UL << USB0_USBMODE_D_SDIS_Pos) /*!< USB0 USBMODE_D: SDIS Mask */ - -// ------------------------------------- USB0_USBMODE_H ----------------------------------------- -#define USB0_USBMODE_H_CM_Pos 0 /*!< USB0 USBMODE_H: CM Position */ -#define USB0_USBMODE_H_CM_Msk (0x03UL << USB0_USBMODE_H_CM_Pos) /*!< USB0 USBMODE_H: CM Mask */ -#define USB0_USBMODE_H_ES_Pos 2 /*!< USB0 USBMODE_H: ES Position */ -#define USB0_USBMODE_H_ES_Msk (0x01UL << USB0_USBMODE_H_ES_Pos) /*!< USB0 USBMODE_H: ES Mask */ -#define USB0_USBMODE_H_SDIS_Pos 4 /*!< USB0 USBMODE_H: SDIS Position */ -#define USB0_USBMODE_H_SDIS_Msk (0x01UL << USB0_USBMODE_H_SDIS_Pos) /*!< USB0 USBMODE_H: SDIS Mask */ -#define USB0_USBMODE_H_VBPS_Pos 5 /*!< USB0 USBMODE_H: VBPS Position */ -#define USB0_USBMODE_H_VBPS_Msk (0x01UL << USB0_USBMODE_H_VBPS_Pos) /*!< USB0 USBMODE_H: VBPS Mask */ - -// ----------------------------------- USB0_ENDPTSETUPSTAT -------------------------------------- -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos 0 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos 1 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos 2 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos 3 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos 4 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Position */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Mask */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos 5 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Position */ -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Mask */ - -// ------------------------------------- USB0_ENDPTPRIME ---------------------------------------- -#define USB0_ENDPTPRIME_PERB0_Pos 0 /*!< USB0 ENDPTPRIME: PERB0 Position */ -#define USB0_ENDPTPRIME_PERB0_Msk (0x01UL << USB0_ENDPTPRIME_PERB0_Pos) /*!< USB0 ENDPTPRIME: PERB0 Mask */ -#define USB0_ENDPTPRIME_PERB1_Pos 1 /*!< USB0 ENDPTPRIME: PERB1 Position */ -#define USB0_ENDPTPRIME_PERB1_Msk (0x01UL << USB0_ENDPTPRIME_PERB1_Pos) /*!< USB0 ENDPTPRIME: PERB1 Mask */ -#define USB0_ENDPTPRIME_PERB2_Pos 2 /*!< USB0 ENDPTPRIME: PERB2 Position */ -#define USB0_ENDPTPRIME_PERB2_Msk (0x01UL << USB0_ENDPTPRIME_PERB2_Pos) /*!< USB0 ENDPTPRIME: PERB2 Mask */ -#define USB0_ENDPTPRIME_PERB3_Pos 3 /*!< USB0 ENDPTPRIME: PERB3 Position */ -#define USB0_ENDPTPRIME_PERB3_Msk (0x01UL << USB0_ENDPTPRIME_PERB3_Pos) /*!< USB0 ENDPTPRIME: PERB3 Mask */ -#define USB0_ENDPTPRIME_PERB4_Pos 4 /*!< USB0 ENDPTPRIME: PERB4 Position */ -#define USB0_ENDPTPRIME_PERB4_Msk (0x01UL << USB0_ENDPTPRIME_PERB4_Pos) /*!< USB0 ENDPTPRIME: PERB4 Mask */ -#define USB0_ENDPTPRIME_PERB5_Pos 5 /*!< USB0 ENDPTPRIME: PERB5 Position */ -#define USB0_ENDPTPRIME_PERB5_Msk (0x01UL << USB0_ENDPTPRIME_PERB5_Pos) /*!< USB0 ENDPTPRIME: PERB5 Mask */ -#define USB0_ENDPTPRIME_PETB0_Pos 16 /*!< USB0 ENDPTPRIME: PETB0 Position */ -#define USB0_ENDPTPRIME_PETB0_Msk (0x01UL << USB0_ENDPTPRIME_PETB0_Pos) /*!< USB0 ENDPTPRIME: PETB0 Mask */ -#define USB0_ENDPTPRIME_PETB1_Pos 17 /*!< USB0 ENDPTPRIME: PETB1 Position */ -#define USB0_ENDPTPRIME_PETB1_Msk (0x01UL << USB0_ENDPTPRIME_PETB1_Pos) /*!< USB0 ENDPTPRIME: PETB1 Mask */ -#define USB0_ENDPTPRIME_PETB2_Pos 18 /*!< USB0 ENDPTPRIME: PETB2 Position */ -#define USB0_ENDPTPRIME_PETB2_Msk (0x01UL << USB0_ENDPTPRIME_PETB2_Pos) /*!< USB0 ENDPTPRIME: PETB2 Mask */ -#define USB0_ENDPTPRIME_PETB3_Pos 19 /*!< USB0 ENDPTPRIME: PETB3 Position */ -#define USB0_ENDPTPRIME_PETB3_Msk (0x01UL << USB0_ENDPTPRIME_PETB3_Pos) /*!< USB0 ENDPTPRIME: PETB3 Mask */ -#define USB0_ENDPTPRIME_PETB4_Pos 20 /*!< USB0 ENDPTPRIME: PETB4 Position */ -#define USB0_ENDPTPRIME_PETB4_Msk (0x01UL << USB0_ENDPTPRIME_PETB4_Pos) /*!< USB0 ENDPTPRIME: PETB4 Mask */ -#define USB0_ENDPTPRIME_PETB5_Pos 21 /*!< USB0 ENDPTPRIME: PETB5 Position */ -#define USB0_ENDPTPRIME_PETB5_Msk (0x01UL << USB0_ENDPTPRIME_PETB5_Pos) /*!< USB0 ENDPTPRIME: PETB5 Mask */ - -// ------------------------------------- USB0_ENDPTFLUSH ---------------------------------------- -#define USB0_ENDPTFLUSH_FERB0_Pos 0 /*!< USB0 ENDPTFLUSH: FERB0 Position */ -#define USB0_ENDPTFLUSH_FERB0_Msk (0x01UL << USB0_ENDPTFLUSH_FERB0_Pos) /*!< USB0 ENDPTFLUSH: FERB0 Mask */ -#define USB0_ENDPTFLUSH_FERB1_Pos 1 /*!< USB0 ENDPTFLUSH: FERB1 Position */ -#define USB0_ENDPTFLUSH_FERB1_Msk (0x01UL << USB0_ENDPTFLUSH_FERB1_Pos) /*!< USB0 ENDPTFLUSH: FERB1 Mask */ -#define USB0_ENDPTFLUSH_FERB2_Pos 2 /*!< USB0 ENDPTFLUSH: FERB2 Position */ -#define USB0_ENDPTFLUSH_FERB2_Msk (0x01UL << USB0_ENDPTFLUSH_FERB2_Pos) /*!< USB0 ENDPTFLUSH: FERB2 Mask */ -#define USB0_ENDPTFLUSH_FERB3_Pos 3 /*!< USB0 ENDPTFLUSH: FERB3 Position */ -#define USB0_ENDPTFLUSH_FERB3_Msk (0x01UL << USB0_ENDPTFLUSH_FERB3_Pos) /*!< USB0 ENDPTFLUSH: FERB3 Mask */ -#define USB0_ENDPTFLUSH_FERB4_Pos 4 /*!< USB0 ENDPTFLUSH: FERB4 Position */ -#define USB0_ENDPTFLUSH_FERB4_Msk (0x01UL << USB0_ENDPTFLUSH_FERB4_Pos) /*!< USB0 ENDPTFLUSH: FERB4 Mask */ -#define USB0_ENDPTFLUSH_FERB5_Pos 5 /*!< USB0 ENDPTFLUSH: FERB5 Position */ -#define USB0_ENDPTFLUSH_FERB5_Msk (0x01UL << USB0_ENDPTFLUSH_FERB5_Pos) /*!< USB0 ENDPTFLUSH: FERB5 Mask */ -#define USB0_ENDPTFLUSH_FETB0_Pos 16 /*!< USB0 ENDPTFLUSH: FETB0 Position */ -#define USB0_ENDPTFLUSH_FETB0_Msk (0x01UL << USB0_ENDPTFLUSH_FETB0_Pos) /*!< USB0 ENDPTFLUSH: FETB0 Mask */ -#define USB0_ENDPTFLUSH_FETB1_Pos 17 /*!< USB0 ENDPTFLUSH: FETB1 Position */ -#define USB0_ENDPTFLUSH_FETB1_Msk (0x01UL << USB0_ENDPTFLUSH_FETB1_Pos) /*!< USB0 ENDPTFLUSH: FETB1 Mask */ -#define USB0_ENDPTFLUSH_FETB2_Pos 18 /*!< USB0 ENDPTFLUSH: FETB2 Position */ -#define USB0_ENDPTFLUSH_FETB2_Msk (0x01UL << USB0_ENDPTFLUSH_FETB2_Pos) /*!< USB0 ENDPTFLUSH: FETB2 Mask */ -#define USB0_ENDPTFLUSH_FETB3_Pos 19 /*!< USB0 ENDPTFLUSH: FETB3 Position */ -#define USB0_ENDPTFLUSH_FETB3_Msk (0x01UL << USB0_ENDPTFLUSH_FETB3_Pos) /*!< USB0 ENDPTFLUSH: FETB3 Mask */ -#define USB0_ENDPTFLUSH_FETB4_Pos 20 /*!< USB0 ENDPTFLUSH: FETB4 Position */ -#define USB0_ENDPTFLUSH_FETB4_Msk (0x01UL << USB0_ENDPTFLUSH_FETB4_Pos) /*!< USB0 ENDPTFLUSH: FETB4 Mask */ -#define USB0_ENDPTFLUSH_FETB5_Pos 21 /*!< USB0 ENDPTFLUSH: FETB5 Position */ -#define USB0_ENDPTFLUSH_FETB5_Msk (0x01UL << USB0_ENDPTFLUSH_FETB5_Pos) /*!< USB0 ENDPTFLUSH: FETB5 Mask */ - -// ------------------------------------- USB0_ENDPTSTAT ----------------------------------------- -#define USB0_ENDPTSTAT_ERBR0_Pos 0 /*!< USB0 ENDPTSTAT: ERBR0 Position */ -#define USB0_ENDPTSTAT_ERBR0_Msk (0x01UL << USB0_ENDPTSTAT_ERBR0_Pos) /*!< USB0 ENDPTSTAT: ERBR0 Mask */ -#define USB0_ENDPTSTAT_ERBR1_Pos 1 /*!< USB0 ENDPTSTAT: ERBR1 Position */ -#define USB0_ENDPTSTAT_ERBR1_Msk (0x01UL << USB0_ENDPTSTAT_ERBR1_Pos) /*!< USB0 ENDPTSTAT: ERBR1 Mask */ -#define USB0_ENDPTSTAT_ERBR2_Pos 2 /*!< USB0 ENDPTSTAT: ERBR2 Position */ -#define USB0_ENDPTSTAT_ERBR2_Msk (0x01UL << USB0_ENDPTSTAT_ERBR2_Pos) /*!< USB0 ENDPTSTAT: ERBR2 Mask */ -#define USB0_ENDPTSTAT_ERBR3_Pos 3 /*!< USB0 ENDPTSTAT: ERBR3 Position */ -#define USB0_ENDPTSTAT_ERBR3_Msk (0x01UL << USB0_ENDPTSTAT_ERBR3_Pos) /*!< USB0 ENDPTSTAT: ERBR3 Mask */ -#define USB0_ENDPTSTAT_ERBR4_Pos 4 /*!< USB0 ENDPTSTAT: ERBR4 Position */ -#define USB0_ENDPTSTAT_ERBR4_Msk (0x01UL << USB0_ENDPTSTAT_ERBR4_Pos) /*!< USB0 ENDPTSTAT: ERBR4 Mask */ -#define USB0_ENDPTSTAT_ERBR5_Pos 5 /*!< USB0 ENDPTSTAT: ERBR5 Position */ -#define USB0_ENDPTSTAT_ERBR5_Msk (0x01UL << USB0_ENDPTSTAT_ERBR5_Pos) /*!< USB0 ENDPTSTAT: ERBR5 Mask */ -#define USB0_ENDPTSTAT_ETBR0_Pos 16 /*!< USB0 ENDPTSTAT: ETBR0 Position */ -#define USB0_ENDPTSTAT_ETBR0_Msk (0x01UL << USB0_ENDPTSTAT_ETBR0_Pos) /*!< USB0 ENDPTSTAT: ETBR0 Mask */ -#define USB0_ENDPTSTAT_ETBR1_Pos 17 /*!< USB0 ENDPTSTAT: ETBR1 Position */ -#define USB0_ENDPTSTAT_ETBR1_Msk (0x01UL << USB0_ENDPTSTAT_ETBR1_Pos) /*!< USB0 ENDPTSTAT: ETBR1 Mask */ -#define USB0_ENDPTSTAT_ETBR2_Pos 18 /*!< USB0 ENDPTSTAT: ETBR2 Position */ -#define USB0_ENDPTSTAT_ETBR2_Msk (0x01UL << USB0_ENDPTSTAT_ETBR2_Pos) /*!< USB0 ENDPTSTAT: ETBR2 Mask */ -#define USB0_ENDPTSTAT_ETBR3_Pos 19 /*!< USB0 ENDPTSTAT: ETBR3 Position */ -#define USB0_ENDPTSTAT_ETBR3_Msk (0x01UL << USB0_ENDPTSTAT_ETBR3_Pos) /*!< USB0 ENDPTSTAT: ETBR3 Mask */ -#define USB0_ENDPTSTAT_ETBR4_Pos 20 /*!< USB0 ENDPTSTAT: ETBR4 Position */ -#define USB0_ENDPTSTAT_ETBR4_Msk (0x01UL << USB0_ENDPTSTAT_ETBR4_Pos) /*!< USB0 ENDPTSTAT: ETBR4 Mask */ -#define USB0_ENDPTSTAT_ETBR5_Pos 21 /*!< USB0 ENDPTSTAT: ETBR5 Position */ -#define USB0_ENDPTSTAT_ETBR5_Msk (0x01UL << USB0_ENDPTSTAT_ETBR5_Pos) /*!< USB0 ENDPTSTAT: ETBR5 Mask */ - -// ----------------------------------- USB0_ENDPTCOMPLETE --------------------------------------- -#define USB0_ENDPTCOMPLETE_ERCE0_Pos 0 /*!< USB0 ENDPTCOMPLETE: ERCE0 Position */ -#define USB0_ENDPTCOMPLETE_ERCE0_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE0_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE0 Mask */ -#define USB0_ENDPTCOMPLETE_ERCE1_Pos 1 /*!< USB0 ENDPTCOMPLETE: ERCE1 Position */ -#define USB0_ENDPTCOMPLETE_ERCE1_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE1_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE1 Mask */ -#define USB0_ENDPTCOMPLETE_ERCE2_Pos 2 /*!< USB0 ENDPTCOMPLETE: ERCE2 Position */ -#define USB0_ENDPTCOMPLETE_ERCE2_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE2_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE2 Mask */ -#define USB0_ENDPTCOMPLETE_ERCE3_Pos 3 /*!< USB0 ENDPTCOMPLETE: ERCE3 Position */ -#define USB0_ENDPTCOMPLETE_ERCE3_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE3_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE3 Mask */ -#define USB0_ENDPTCOMPLETE_ERCE4_Pos 4 /*!< USB0 ENDPTCOMPLETE: ERCE4 Position */ -#define USB0_ENDPTCOMPLETE_ERCE4_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE4_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE4 Mask */ -#define USB0_ENDPTCOMPLETE_ERCE5_Pos 5 /*!< USB0 ENDPTCOMPLETE: ERCE5 Position */ -#define USB0_ENDPTCOMPLETE_ERCE5_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE5_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE5 Mask */ -#define USB0_ENDPTCOMPLETE_ETCE0_Pos 16 /*!< USB0 ENDPTCOMPLETE: ETCE0 Position */ -#define USB0_ENDPTCOMPLETE_ETCE0_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE0_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE0 Mask */ -#define USB0_ENDPTCOMPLETE_ETCE1_Pos 17 /*!< USB0 ENDPTCOMPLETE: ETCE1 Position */ -#define USB0_ENDPTCOMPLETE_ETCE1_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE1_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE1 Mask */ -#define USB0_ENDPTCOMPLETE_ETCE2_Pos 18 /*!< USB0 ENDPTCOMPLETE: ETCE2 Position */ -#define USB0_ENDPTCOMPLETE_ETCE2_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE2_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE2 Mask */ -#define USB0_ENDPTCOMPLETE_ETCE3_Pos 19 /*!< USB0 ENDPTCOMPLETE: ETCE3 Position */ -#define USB0_ENDPTCOMPLETE_ETCE3_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE3_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE3 Mask */ -#define USB0_ENDPTCOMPLETE_ETCE4_Pos 20 /*!< USB0 ENDPTCOMPLETE: ETCE4 Position */ -#define USB0_ENDPTCOMPLETE_ETCE4_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE4_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE4 Mask */ -#define USB0_ENDPTCOMPLETE_ETCE5_Pos 21 /*!< USB0 ENDPTCOMPLETE: ETCE5 Position */ -#define USB0_ENDPTCOMPLETE_ETCE5_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE5_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE5 Mask */ - -// ------------------------------------- USB0_ENDPTCTRL0 ---------------------------------------- -#define USB0_ENDPTCTRL0_RXS_Pos 0 /*!< USB0 ENDPTCTRL0: RXS Position */ -#define USB0_ENDPTCTRL0_RXS_Msk (0x01UL << USB0_ENDPTCTRL0_RXS_Pos) /*!< USB0 ENDPTCTRL0: RXS Mask */ -#define USB0_ENDPTCTRL0_RXT1_0_Pos 2 /*!< USB0 ENDPTCTRL0: RXT1_0 Position */ -#define USB0_ENDPTCTRL0_RXT1_0_Msk (0x03UL << USB0_ENDPTCTRL0_RXT1_0_Pos) /*!< USB0 ENDPTCTRL0: RXT1_0 Mask */ -#define USB0_ENDPTCTRL0_RXE_Pos 7 /*!< USB0 ENDPTCTRL0: RXE Position */ -#define USB0_ENDPTCTRL0_RXE_Msk (0x01UL << USB0_ENDPTCTRL0_RXE_Pos) /*!< USB0 ENDPTCTRL0: RXE Mask */ -#define USB0_ENDPTCTRL0_TXS_Pos 16 /*!< USB0 ENDPTCTRL0: TXS Position */ -#define USB0_ENDPTCTRL0_TXS_Msk (0x01UL << USB0_ENDPTCTRL0_TXS_Pos) /*!< USB0 ENDPTCTRL0: TXS Mask */ -#define USB0_ENDPTCTRL0_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL0: TXT1_0 Position */ -#define USB0_ENDPTCTRL0_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL0_TXT1_0_Pos) /*!< USB0 ENDPTCTRL0: TXT1_0 Mask */ -#define USB0_ENDPTCTRL0_TXE_Pos 23 /*!< USB0 ENDPTCTRL0: TXE Position */ -#define USB0_ENDPTCTRL0_TXE_Msk (0x01UL << USB0_ENDPTCTRL0_TXE_Pos) /*!< USB0 ENDPTCTRL0: TXE Mask */ - -// ------------------------------------- USB0_ENDPTCTRL1 ---------------------------------------- -#define USB0_ENDPTCTRL1_RXS_Pos 0 /*!< USB0 ENDPTCTRL1: RXS Position */ -#define USB0_ENDPTCTRL1_RXS_Msk (0x01UL << USB0_ENDPTCTRL1_RXS_Pos) /*!< USB0 ENDPTCTRL1: RXS Mask */ -#define USB0_ENDPTCTRL1_RXT_Pos 2 /*!< USB0 ENDPTCTRL1: RXT Position */ -#define USB0_ENDPTCTRL1_RXT_Msk (0x03UL << USB0_ENDPTCTRL1_RXT_Pos) /*!< USB0 ENDPTCTRL1: RXT Mask */ -#define USB0_ENDPTCTRL1_RXI_Pos 5 /*!< USB0 ENDPTCTRL1: RXI Position */ -#define USB0_ENDPTCTRL1_RXI_Msk (0x01UL << USB0_ENDPTCTRL1_RXI_Pos) /*!< USB0 ENDPTCTRL1: RXI Mask */ -#define USB0_ENDPTCTRL1_RXR_Pos 6 /*!< USB0 ENDPTCTRL1: RXR Position */ -#define USB0_ENDPTCTRL1_RXR_Msk (0x01UL << USB0_ENDPTCTRL1_RXR_Pos) /*!< USB0 ENDPTCTRL1: RXR Mask */ -#define USB0_ENDPTCTRL1_RXE_Pos 7 /*!< USB0 ENDPTCTRL1: RXE Position */ -#define USB0_ENDPTCTRL1_RXE_Msk (0x01UL << USB0_ENDPTCTRL1_RXE_Pos) /*!< USB0 ENDPTCTRL1: RXE Mask */ -#define USB0_ENDPTCTRL1_TXS_Pos 16 /*!< USB0 ENDPTCTRL1: TXS Position */ -#define USB0_ENDPTCTRL1_TXS_Msk (0x01UL << USB0_ENDPTCTRL1_TXS_Pos) /*!< USB0 ENDPTCTRL1: TXS Mask */ -#define USB0_ENDPTCTRL1_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL1: TXT1_0 Position */ -#define USB0_ENDPTCTRL1_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL1_TXT1_0_Pos) /*!< USB0 ENDPTCTRL1: TXT1_0 Mask */ -#define USB0_ENDPTCTRL1_TXI_Pos 21 /*!< USB0 ENDPTCTRL1: TXI Position */ -#define USB0_ENDPTCTRL1_TXI_Msk (0x01UL << USB0_ENDPTCTRL1_TXI_Pos) /*!< USB0 ENDPTCTRL1: TXI Mask */ -#define USB0_ENDPTCTRL1_TXR_Pos 22 /*!< USB0 ENDPTCTRL1: TXR Position */ -#define USB0_ENDPTCTRL1_TXR_Msk (0x01UL << USB0_ENDPTCTRL1_TXR_Pos) /*!< USB0 ENDPTCTRL1: TXR Mask */ -#define USB0_ENDPTCTRL1_TXE_Pos 23 /*!< USB0 ENDPTCTRL1: TXE Position */ -#define USB0_ENDPTCTRL1_TXE_Msk (0x01UL << USB0_ENDPTCTRL1_TXE_Pos) /*!< USB0 ENDPTCTRL1: TXE Mask */ - -// ------------------------------------- USB0_ENDPTCTRL2 ---------------------------------------- -#define USB0_ENDPTCTRL2_RXS_Pos 0 /*!< USB0 ENDPTCTRL2: RXS Position */ -#define USB0_ENDPTCTRL2_RXS_Msk (0x01UL << USB0_ENDPTCTRL2_RXS_Pos) /*!< USB0 ENDPTCTRL2: RXS Mask */ -#define USB0_ENDPTCTRL2_RXT_Pos 2 /*!< USB0 ENDPTCTRL2: RXT Position */ -#define USB0_ENDPTCTRL2_RXT_Msk (0x03UL << USB0_ENDPTCTRL2_RXT_Pos) /*!< USB0 ENDPTCTRL2: RXT Mask */ -#define USB0_ENDPTCTRL2_RXI_Pos 5 /*!< USB0 ENDPTCTRL2: RXI Position */ -#define USB0_ENDPTCTRL2_RXI_Msk (0x01UL << USB0_ENDPTCTRL2_RXI_Pos) /*!< USB0 ENDPTCTRL2: RXI Mask */ -#define USB0_ENDPTCTRL2_RXR_Pos 6 /*!< USB0 ENDPTCTRL2: RXR Position */ -#define USB0_ENDPTCTRL2_RXR_Msk (0x01UL << USB0_ENDPTCTRL2_RXR_Pos) /*!< USB0 ENDPTCTRL2: RXR Mask */ -#define USB0_ENDPTCTRL2_RXE_Pos 7 /*!< USB0 ENDPTCTRL2: RXE Position */ -#define USB0_ENDPTCTRL2_RXE_Msk (0x01UL << USB0_ENDPTCTRL2_RXE_Pos) /*!< USB0 ENDPTCTRL2: RXE Mask */ -#define USB0_ENDPTCTRL2_TXS_Pos 16 /*!< USB0 ENDPTCTRL2: TXS Position */ -#define USB0_ENDPTCTRL2_TXS_Msk (0x01UL << USB0_ENDPTCTRL2_TXS_Pos) /*!< USB0 ENDPTCTRL2: TXS Mask */ -#define USB0_ENDPTCTRL2_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL2: TXT1_0 Position */ -#define USB0_ENDPTCTRL2_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL2_TXT1_0_Pos) /*!< USB0 ENDPTCTRL2: TXT1_0 Mask */ -#define USB0_ENDPTCTRL2_TXI_Pos 21 /*!< USB0 ENDPTCTRL2: TXI Position */ -#define USB0_ENDPTCTRL2_TXI_Msk (0x01UL << USB0_ENDPTCTRL2_TXI_Pos) /*!< USB0 ENDPTCTRL2: TXI Mask */ -#define USB0_ENDPTCTRL2_TXR_Pos 22 /*!< USB0 ENDPTCTRL2: TXR Position */ -#define USB0_ENDPTCTRL2_TXR_Msk (0x01UL << USB0_ENDPTCTRL2_TXR_Pos) /*!< USB0 ENDPTCTRL2: TXR Mask */ -#define USB0_ENDPTCTRL2_TXE_Pos 23 /*!< USB0 ENDPTCTRL2: TXE Position */ -#define USB0_ENDPTCTRL2_TXE_Msk (0x01UL << USB0_ENDPTCTRL2_TXE_Pos) /*!< USB0 ENDPTCTRL2: TXE Mask */ - -// ------------------------------------- USB0_ENDPTCTRL3 ---------------------------------------- -#define USB0_ENDPTCTRL3_RXS_Pos 0 /*!< USB0 ENDPTCTRL3: RXS Position */ -#define USB0_ENDPTCTRL3_RXS_Msk (0x01UL << USB0_ENDPTCTRL3_RXS_Pos) /*!< USB0 ENDPTCTRL3: RXS Mask */ -#define USB0_ENDPTCTRL3_RXT_Pos 2 /*!< USB0 ENDPTCTRL3: RXT Position */ -#define USB0_ENDPTCTRL3_RXT_Msk (0x03UL << USB0_ENDPTCTRL3_RXT_Pos) /*!< USB0 ENDPTCTRL3: RXT Mask */ -#define USB0_ENDPTCTRL3_RXI_Pos 5 /*!< USB0 ENDPTCTRL3: RXI Position */ -#define USB0_ENDPTCTRL3_RXI_Msk (0x01UL << USB0_ENDPTCTRL3_RXI_Pos) /*!< USB0 ENDPTCTRL3: RXI Mask */ -#define USB0_ENDPTCTRL3_RXR_Pos 6 /*!< USB0 ENDPTCTRL3: RXR Position */ -#define USB0_ENDPTCTRL3_RXR_Msk (0x01UL << USB0_ENDPTCTRL3_RXR_Pos) /*!< USB0 ENDPTCTRL3: RXR Mask */ -#define USB0_ENDPTCTRL3_RXE_Pos 7 /*!< USB0 ENDPTCTRL3: RXE Position */ -#define USB0_ENDPTCTRL3_RXE_Msk (0x01UL << USB0_ENDPTCTRL3_RXE_Pos) /*!< USB0 ENDPTCTRL3: RXE Mask */ -#define USB0_ENDPTCTRL3_TXS_Pos 16 /*!< USB0 ENDPTCTRL3: TXS Position */ -#define USB0_ENDPTCTRL3_TXS_Msk (0x01UL << USB0_ENDPTCTRL3_TXS_Pos) /*!< USB0 ENDPTCTRL3: TXS Mask */ -#define USB0_ENDPTCTRL3_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL3: TXT1_0 Position */ -#define USB0_ENDPTCTRL3_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL3_TXT1_0_Pos) /*!< USB0 ENDPTCTRL3: TXT1_0 Mask */ -#define USB0_ENDPTCTRL3_TXI_Pos 21 /*!< USB0 ENDPTCTRL3: TXI Position */ -#define USB0_ENDPTCTRL3_TXI_Msk (0x01UL << USB0_ENDPTCTRL3_TXI_Pos) /*!< USB0 ENDPTCTRL3: TXI Mask */ -#define USB0_ENDPTCTRL3_TXR_Pos 22 /*!< USB0 ENDPTCTRL3: TXR Position */ -#define USB0_ENDPTCTRL3_TXR_Msk (0x01UL << USB0_ENDPTCTRL3_TXR_Pos) /*!< USB0 ENDPTCTRL3: TXR Mask */ -#define USB0_ENDPTCTRL3_TXE_Pos 23 /*!< USB0 ENDPTCTRL3: TXE Position */ -#define USB0_ENDPTCTRL3_TXE_Msk (0x01UL << USB0_ENDPTCTRL3_TXE_Pos) /*!< USB0 ENDPTCTRL3: TXE Mask */ - -// ------------------------------------- USB0_ENDPTCTRL4 ---------------------------------------- -#define USB0_ENDPTCTRL4_RXS_Pos 0 /*!< USB0 ENDPTCTRL4: RXS Position */ -#define USB0_ENDPTCTRL4_RXS_Msk (0x01UL << USB0_ENDPTCTRL4_RXS_Pos) /*!< USB0 ENDPTCTRL4: RXS Mask */ -#define USB0_ENDPTCTRL4_RXT_Pos 2 /*!< USB0 ENDPTCTRL4: RXT Position */ -#define USB0_ENDPTCTRL4_RXT_Msk (0x03UL << USB0_ENDPTCTRL4_RXT_Pos) /*!< USB0 ENDPTCTRL4: RXT Mask */ -#define USB0_ENDPTCTRL4_RXI_Pos 5 /*!< USB0 ENDPTCTRL4: RXI Position */ -#define USB0_ENDPTCTRL4_RXI_Msk (0x01UL << USB0_ENDPTCTRL4_RXI_Pos) /*!< USB0 ENDPTCTRL4: RXI Mask */ -#define USB0_ENDPTCTRL4_RXR_Pos 6 /*!< USB0 ENDPTCTRL4: RXR Position */ -#define USB0_ENDPTCTRL4_RXR_Msk (0x01UL << USB0_ENDPTCTRL4_RXR_Pos) /*!< USB0 ENDPTCTRL4: RXR Mask */ -#define USB0_ENDPTCTRL4_RXE_Pos 7 /*!< USB0 ENDPTCTRL4: RXE Position */ -#define USB0_ENDPTCTRL4_RXE_Msk (0x01UL << USB0_ENDPTCTRL4_RXE_Pos) /*!< USB0 ENDPTCTRL4: RXE Mask */ -#define USB0_ENDPTCTRL4_TXS_Pos 16 /*!< USB0 ENDPTCTRL4: TXS Position */ -#define USB0_ENDPTCTRL4_TXS_Msk (0x01UL << USB0_ENDPTCTRL4_TXS_Pos) /*!< USB0 ENDPTCTRL4: TXS Mask */ -#define USB0_ENDPTCTRL4_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL4: TXT1_0 Position */ -#define USB0_ENDPTCTRL4_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL4_TXT1_0_Pos) /*!< USB0 ENDPTCTRL4: TXT1_0 Mask */ -#define USB0_ENDPTCTRL4_TXI_Pos 21 /*!< USB0 ENDPTCTRL4: TXI Position */ -#define USB0_ENDPTCTRL4_TXI_Msk (0x01UL << USB0_ENDPTCTRL4_TXI_Pos) /*!< USB0 ENDPTCTRL4: TXI Mask */ -#define USB0_ENDPTCTRL4_TXR_Pos 22 /*!< USB0 ENDPTCTRL4: TXR Position */ -#define USB0_ENDPTCTRL4_TXR_Msk (0x01UL << USB0_ENDPTCTRL4_TXR_Pos) /*!< USB0 ENDPTCTRL4: TXR Mask */ -#define USB0_ENDPTCTRL4_TXE_Pos 23 /*!< USB0 ENDPTCTRL4: TXE Position */ -#define USB0_ENDPTCTRL4_TXE_Msk (0x01UL << USB0_ENDPTCTRL4_TXE_Pos) /*!< USB0 ENDPTCTRL4: TXE Mask */ - -// ------------------------------------- USB0_ENDPTCTRL5 ---------------------------------------- -#define USB0_ENDPTCTRL5_RXS_Pos 0 /*!< USB0 ENDPTCTRL5: RXS Position */ -#define USB0_ENDPTCTRL5_RXS_Msk (0x01UL << USB0_ENDPTCTRL5_RXS_Pos) /*!< USB0 ENDPTCTRL5: RXS Mask */ -#define USB0_ENDPTCTRL5_RXT_Pos 2 /*!< USB0 ENDPTCTRL5: RXT Position */ -#define USB0_ENDPTCTRL5_RXT_Msk (0x03UL << USB0_ENDPTCTRL5_RXT_Pos) /*!< USB0 ENDPTCTRL5: RXT Mask */ -#define USB0_ENDPTCTRL5_RXI_Pos 5 /*!< USB0 ENDPTCTRL5: RXI Position */ -#define USB0_ENDPTCTRL5_RXI_Msk (0x01UL << USB0_ENDPTCTRL5_RXI_Pos) /*!< USB0 ENDPTCTRL5: RXI Mask */ -#define USB0_ENDPTCTRL5_RXR_Pos 6 /*!< USB0 ENDPTCTRL5: RXR Position */ -#define USB0_ENDPTCTRL5_RXR_Msk (0x01UL << USB0_ENDPTCTRL5_RXR_Pos) /*!< USB0 ENDPTCTRL5: RXR Mask */ -#define USB0_ENDPTCTRL5_RXE_Pos 7 /*!< USB0 ENDPTCTRL5: RXE Position */ -#define USB0_ENDPTCTRL5_RXE_Msk (0x01UL << USB0_ENDPTCTRL5_RXE_Pos) /*!< USB0 ENDPTCTRL5: RXE Mask */ -#define USB0_ENDPTCTRL5_TXS_Pos 16 /*!< USB0 ENDPTCTRL5: TXS Position */ -#define USB0_ENDPTCTRL5_TXS_Msk (0x01UL << USB0_ENDPTCTRL5_TXS_Pos) /*!< USB0 ENDPTCTRL5: TXS Mask */ -#define USB0_ENDPTCTRL5_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL5: TXT1_0 Position */ -#define USB0_ENDPTCTRL5_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL5_TXT1_0_Pos) /*!< USB0 ENDPTCTRL5: TXT1_0 Mask */ -#define USB0_ENDPTCTRL5_TXI_Pos 21 /*!< USB0 ENDPTCTRL5: TXI Position */ -#define USB0_ENDPTCTRL5_TXI_Msk (0x01UL << USB0_ENDPTCTRL5_TXI_Pos) /*!< USB0 ENDPTCTRL5: TXI Mask */ -#define USB0_ENDPTCTRL5_TXR_Pos 22 /*!< USB0 ENDPTCTRL5: TXR Position */ -#define USB0_ENDPTCTRL5_TXR_Msk (0x01UL << USB0_ENDPTCTRL5_TXR_Pos) /*!< USB0 ENDPTCTRL5: TXR Mask */ -#define USB0_ENDPTCTRL5_TXE_Pos 23 /*!< USB0 ENDPTCTRL5: TXE Position */ -#define USB0_ENDPTCTRL5_TXE_Msk (0x01UL << USB0_ENDPTCTRL5_TXE_Pos) /*!< USB0 ENDPTCTRL5: TXE Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- USB1 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ------------------------------------- USB1_CAPLENGTH ----------------------------------------- -#define USB1_CAPLENGTH_CAPLENGTH_Pos 0 /*!< USB1 CAPLENGTH: CAPLENGTH Position */ -#define USB1_CAPLENGTH_CAPLENGTH_Msk (0x000000ffUL << USB1_CAPLENGTH_CAPLENGTH_Pos) /*!< USB1 CAPLENGTH: CAPLENGTH Mask */ -#define USB1_CAPLENGTH_HCIVERSION_Pos 8 /*!< USB1 CAPLENGTH: HCIVERSION Position */ -#define USB1_CAPLENGTH_HCIVERSION_Msk (0x0000ffffUL << USB1_CAPLENGTH_HCIVERSION_Pos) /*!< USB1 CAPLENGTH: HCIVERSION Mask */ - -// ------------------------------------- USB1_HCSPARAMS ----------------------------------------- -#define USB1_HCSPARAMS_N_PORTS_Pos 0 /*!< USB1 HCSPARAMS: N_PORTS Position */ -#define USB1_HCSPARAMS_N_PORTS_Msk (0x0fUL << USB1_HCSPARAMS_N_PORTS_Pos) /*!< USB1 HCSPARAMS: N_PORTS Mask */ -#define USB1_HCSPARAMS_PPC_Pos 4 /*!< USB1 HCSPARAMS: PPC Position */ -#define USB1_HCSPARAMS_PPC_Msk (0x01UL << USB1_HCSPARAMS_PPC_Pos) /*!< USB1 HCSPARAMS: PPC Mask */ -#define USB1_HCSPARAMS_N_PCC_Pos 8 /*!< USB1 HCSPARAMS: N_PCC Position */ -#define USB1_HCSPARAMS_N_PCC_Msk (0x0fUL << USB1_HCSPARAMS_N_PCC_Pos) /*!< USB1 HCSPARAMS: N_PCC Mask */ -#define USB1_HCSPARAMS_N_CC_Pos 12 /*!< USB1 HCSPARAMS: N_CC Position */ -#define USB1_HCSPARAMS_N_CC_Msk (0x0fUL << USB1_HCSPARAMS_N_CC_Pos) /*!< USB1 HCSPARAMS: N_CC Mask */ -#define USB1_HCSPARAMS_PI_Pos 16 /*!< USB1 HCSPARAMS: PI Position */ -#define USB1_HCSPARAMS_PI_Msk (0x01UL << USB1_HCSPARAMS_PI_Pos) /*!< USB1 HCSPARAMS: PI Mask */ -#define USB1_HCSPARAMS_N_PTT_Pos 20 /*!< USB1 HCSPARAMS: N_PTT Position */ -#define USB1_HCSPARAMS_N_PTT_Msk (0x0fUL << USB1_HCSPARAMS_N_PTT_Pos) /*!< USB1 HCSPARAMS: N_PTT Mask */ -#define USB1_HCSPARAMS_N_TT_Pos 24 /*!< USB1 HCSPARAMS: N_TT Position */ -#define USB1_HCSPARAMS_N_TT_Msk (0x0fUL << USB1_HCSPARAMS_N_TT_Pos) /*!< USB1 HCSPARAMS: N_TT Mask */ - -// ------------------------------------- USB1_HCCPARAMS ----------------------------------------- -#define USB1_HCCPARAMS_ADC_Pos 0 /*!< USB1 HCCPARAMS: ADC Position */ -#define USB1_HCCPARAMS_ADC_Msk (0x01UL << USB1_HCCPARAMS_ADC_Pos) /*!< USB1 HCCPARAMS: ADC Mask */ -#define USB1_HCCPARAMS_PFL_Pos 1 /*!< USB1 HCCPARAMS: PFL Position */ -#define USB1_HCCPARAMS_PFL_Msk (0x01UL << USB1_HCCPARAMS_PFL_Pos) /*!< USB1 HCCPARAMS: PFL Mask */ -#define USB1_HCCPARAMS_ASP_Pos 2 /*!< USB1 HCCPARAMS: ASP Position */ -#define USB1_HCCPARAMS_ASP_Msk (0x01UL << USB1_HCCPARAMS_ASP_Pos) /*!< USB1 HCCPARAMS: ASP Mask */ -#define USB1_HCCPARAMS_IST_Pos 4 /*!< USB1 HCCPARAMS: IST Position */ -#define USB1_HCCPARAMS_IST_Msk (0x0fUL << USB1_HCCPARAMS_IST_Pos) /*!< USB1 HCCPARAMS: IST Mask */ -#define USB1_HCCPARAMS_EECP_Pos 8 /*!< USB1 HCCPARAMS: EECP Position */ -#define USB1_HCCPARAMS_EECP_Msk (0x000000ffUL << USB1_HCCPARAMS_EECP_Pos) /*!< USB1 HCCPARAMS: EECP Mask */ - -// ------------------------------------- USB1_DCIVERSION ---------------------------------------- -#define USB1_DCIVERSION_DCIVERSION_Pos 0 /*!< USB1 DCIVERSION: DCIVERSION Position */ -#define USB1_DCIVERSION_DCIVERSION_Msk (0x0000ffffUL << USB1_DCIVERSION_DCIVERSION_Pos) /*!< USB1 DCIVERSION: DCIVERSION Mask */ - -// -------------------------------------- USB1_USBCMD_D ----------------------------------------- -#define USB1_USBCMD_D_RS_Pos 0 /*!< USB1 USBCMD_D: RS Position */ -#define USB1_USBCMD_D_RS_Msk (0x01UL << USB1_USBCMD_D_RS_Pos) /*!< USB1 USBCMD_D: RS Mask */ -#define USB1_USBCMD_D_RST_Pos 1 /*!< USB1 USBCMD_D: RST Position */ -#define USB1_USBCMD_D_RST_Msk (0x01UL << USB1_USBCMD_D_RST_Pos) /*!< USB1 USBCMD_D: RST Mask */ -#define USB1_USBCMD_D_SUTW_Pos 13 /*!< USB1 USBCMD_D: SUTW Position */ -#define USB1_USBCMD_D_SUTW_Msk (0x01UL << USB1_USBCMD_D_SUTW_Pos) /*!< USB1 USBCMD_D: SUTW Mask */ -#define USB1_USBCMD_D_ATDTW_Pos 14 /*!< USB1 USBCMD_D: ATDTW Position */ -#define USB1_USBCMD_D_ATDTW_Msk (0x01UL << USB1_USBCMD_D_ATDTW_Pos) /*!< USB1 USBCMD_D: ATDTW Mask */ -#define USB1_USBCMD_D_FS2_Pos 15 /*!< USB1 USBCMD_D: FS2 Position */ -#define USB1_USBCMD_D_FS2_Msk (0x01UL << USB1_USBCMD_D_FS2_Pos) /*!< USB1 USBCMD_D: FS2 Mask */ -#define USB1_USBCMD_D_ITC_Pos 16 /*!< USB1 USBCMD_D: ITC Position */ -#define USB1_USBCMD_D_ITC_Msk (0x000000ffUL << USB1_USBCMD_D_ITC_Pos) /*!< USB1 USBCMD_D: ITC Mask */ - -// -------------------------------------- USB1_USBCMD_H ----------------------------------------- -#define USB1_USBCMD_H_RS_Pos 0 /*!< USB1 USBCMD_H: RS Position */ -#define USB1_USBCMD_H_RS_Msk (0x01UL << USB1_USBCMD_H_RS_Pos) /*!< USB1 USBCMD_H: RS Mask */ -#define USB1_USBCMD_H_RST_Pos 1 /*!< USB1 USBCMD_H: RST Position */ -#define USB1_USBCMD_H_RST_Msk (0x01UL << USB1_USBCMD_H_RST_Pos) /*!< USB1 USBCMD_H: RST Mask */ -#define USB1_USBCMD_H_FS0_Pos 2 /*!< USB1 USBCMD_H: FS0 Position */ -#define USB1_USBCMD_H_FS0_Msk (0x01UL << USB1_USBCMD_H_FS0_Pos) /*!< USB1 USBCMD_H: FS0 Mask */ -#define USB1_USBCMD_H_FS1_Pos 3 /*!< USB1 USBCMD_H: FS1 Position */ -#define USB1_USBCMD_H_FS1_Msk (0x01UL << USB1_USBCMD_H_FS1_Pos) /*!< USB1 USBCMD_H: FS1 Mask */ -#define USB1_USBCMD_H_PSE_Pos 4 /*!< USB1 USBCMD_H: PSE Position */ -#define USB1_USBCMD_H_PSE_Msk (0x01UL << USB1_USBCMD_H_PSE_Pos) /*!< USB1 USBCMD_H: PSE Mask */ -#define USB1_USBCMD_H_ASE_Pos 5 /*!< USB1 USBCMD_H: ASE Position */ -#define USB1_USBCMD_H_ASE_Msk (0x01UL << USB1_USBCMD_H_ASE_Pos) /*!< USB1 USBCMD_H: ASE Mask */ -#define USB1_USBCMD_H_IAA_Pos 6 /*!< USB1 USBCMD_H: IAA Position */ -#define USB1_USBCMD_H_IAA_Msk (0x01UL << USB1_USBCMD_H_IAA_Pos) /*!< USB1 USBCMD_H: IAA Mask */ -#define USB1_USBCMD_H_ASP1_0_Pos 8 /*!< USB1 USBCMD_H: ASP1_0 Position */ -#define USB1_USBCMD_H_ASP1_0_Msk (0x03UL << USB1_USBCMD_H_ASP1_0_Pos) /*!< USB1 USBCMD_H: ASP1_0 Mask */ -#define USB1_USBCMD_H_ASPE_Pos 11 /*!< USB1 USBCMD_H: ASPE Position */ -#define USB1_USBCMD_H_ASPE_Msk (0x01UL << USB1_USBCMD_H_ASPE_Pos) /*!< USB1 USBCMD_H: ASPE Mask */ -#define USB1_USBCMD_H_FS2_Pos 15 /*!< USB1 USBCMD_H: FS2 Position */ -#define USB1_USBCMD_H_FS2_Msk (0x01UL << USB1_USBCMD_H_FS2_Pos) /*!< USB1 USBCMD_H: FS2 Mask */ -#define USB1_USBCMD_H_ITC_Pos 16 /*!< USB1 USBCMD_H: ITC Position */ -#define USB1_USBCMD_H_ITC_Msk (0x000000ffUL << USB1_USBCMD_H_ITC_Pos) /*!< USB1 USBCMD_H: ITC Mask */ - -// -------------------------------------- USB1_USBSTS_D ----------------------------------------- -#define USB1_USBSTS_D_UI_Pos 0 /*!< USB1 USBSTS_D: UI Position */ -#define USB1_USBSTS_D_UI_Msk (0x01UL << USB1_USBSTS_D_UI_Pos) /*!< USB1 USBSTS_D: UI Mask */ -#define USB1_USBSTS_D_UEI_Pos 1 /*!< USB1 USBSTS_D: UEI Position */ -#define USB1_USBSTS_D_UEI_Msk (0x01UL << USB1_USBSTS_D_UEI_Pos) /*!< USB1 USBSTS_D: UEI Mask */ -#define USB1_USBSTS_D_PCI_Pos 2 /*!< USB1 USBSTS_D: PCI Position */ -#define USB1_USBSTS_D_PCI_Msk (0x01UL << USB1_USBSTS_D_PCI_Pos) /*!< USB1 USBSTS_D: PCI Mask */ -#define USB1_USBSTS_D_URI_Pos 6 /*!< USB1 USBSTS_D: URI Position */ -#define USB1_USBSTS_D_URI_Msk (0x01UL << USB1_USBSTS_D_URI_Pos) /*!< USB1 USBSTS_D: URI Mask */ -#define USB1_USBSTS_D_SRI_Pos 7 /*!< USB1 USBSTS_D: SRI Position */ -#define USB1_USBSTS_D_SRI_Msk (0x01UL << USB1_USBSTS_D_SRI_Pos) /*!< USB1 USBSTS_D: SRI Mask */ -#define USB1_USBSTS_D_SLI_Pos 8 /*!< USB1 USBSTS_D: SLI Position */ -#define USB1_USBSTS_D_SLI_Msk (0x01UL << USB1_USBSTS_D_SLI_Pos) /*!< USB1 USBSTS_D: SLI Mask */ -#define USB1_USBSTS_D_NAKI_Pos 16 /*!< USB1 USBSTS_D: NAKI Position */ -#define USB1_USBSTS_D_NAKI_Msk (0x01UL << USB1_USBSTS_D_NAKI_Pos) /*!< USB1 USBSTS_D: NAKI Mask */ - -// -------------------------------------- USB1_USBSTS_H ----------------------------------------- -#define USB1_USBSTS_H_UI_Pos 0 /*!< USB1 USBSTS_H: UI Position */ -#define USB1_USBSTS_H_UI_Msk (0x01UL << USB1_USBSTS_H_UI_Pos) /*!< USB1 USBSTS_H: UI Mask */ -#define USB1_USBSTS_H_UEI_Pos 1 /*!< USB1 USBSTS_H: UEI Position */ -#define USB1_USBSTS_H_UEI_Msk (0x01UL << USB1_USBSTS_H_UEI_Pos) /*!< USB1 USBSTS_H: UEI Mask */ -#define USB1_USBSTS_H_PCI_Pos 2 /*!< USB1 USBSTS_H: PCI Position */ -#define USB1_USBSTS_H_PCI_Msk (0x01UL << USB1_USBSTS_H_PCI_Pos) /*!< USB1 USBSTS_H: PCI Mask */ -#define USB1_USBSTS_H_FRI_Pos 3 /*!< USB1 USBSTS_H: FRI Position */ -#define USB1_USBSTS_H_FRI_Msk (0x01UL << USB1_USBSTS_H_FRI_Pos) /*!< USB1 USBSTS_H: FRI Mask */ -#define USB1_USBSTS_H_AAI_Pos 5 /*!< USB1 USBSTS_H: AAI Position */ -#define USB1_USBSTS_H_AAI_Msk (0x01UL << USB1_USBSTS_H_AAI_Pos) /*!< USB1 USBSTS_H: AAI Mask */ -#define USB1_USBSTS_H_SRI_Pos 7 /*!< USB1 USBSTS_H: SRI Position */ -#define USB1_USBSTS_H_SRI_Msk (0x01UL << USB1_USBSTS_H_SRI_Pos) /*!< USB1 USBSTS_H: SRI Mask */ -#define USB1_USBSTS_H_SLI_Pos 8 /*!< USB1 USBSTS_H: SLI Position */ -#define USB1_USBSTS_H_SLI_Msk (0x01UL << USB1_USBSTS_H_SLI_Pos) /*!< USB1 USBSTS_H: SLI Mask */ -#define USB1_USBSTS_H_HCH_Pos 12 /*!< USB1 USBSTS_H: HCH Position */ -#define USB1_USBSTS_H_HCH_Msk (0x01UL << USB1_USBSTS_H_HCH_Pos) /*!< USB1 USBSTS_H: HCH Mask */ -#define USB1_USBSTS_H_RCL_Pos 13 /*!< USB1 USBSTS_H: RCL Position */ -#define USB1_USBSTS_H_RCL_Msk (0x01UL << USB1_USBSTS_H_RCL_Pos) /*!< USB1 USBSTS_H: RCL Mask */ -#define USB1_USBSTS_H_PS_Pos 14 /*!< USB1 USBSTS_H: PS Position */ -#define USB1_USBSTS_H_PS_Msk (0x01UL << USB1_USBSTS_H_PS_Pos) /*!< USB1 USBSTS_H: PS Mask */ -#define USB1_USBSTS_H_AS_Pos 15 /*!< USB1 USBSTS_H: AS Position */ -#define USB1_USBSTS_H_AS_Msk (0x01UL << USB1_USBSTS_H_AS_Pos) /*!< USB1 USBSTS_H: AS Mask */ -#define USB1_USBSTS_H_UAI_Pos 18 /*!< USB1 USBSTS_H: UAI Position */ -#define USB1_USBSTS_H_UAI_Msk (0x01UL << USB1_USBSTS_H_UAI_Pos) /*!< USB1 USBSTS_H: UAI Mask */ -#define USB1_USBSTS_H_UPI_Pos 19 /*!< USB1 USBSTS_H: UPI Position */ -#define USB1_USBSTS_H_UPI_Msk (0x01UL << USB1_USBSTS_H_UPI_Pos) /*!< USB1 USBSTS_H: UPI Mask */ - -// ------------------------------------- USB1_USBINTR_D ----------------------------------------- -#define USB1_USBINTR_D_UE_Pos 0 /*!< USB1 USBINTR_D: UE Position */ -#define USB1_USBINTR_D_UE_Msk (0x01UL << USB1_USBINTR_D_UE_Pos) /*!< USB1 USBINTR_D: UE Mask */ -#define USB1_USBINTR_D_UEE_Pos 1 /*!< USB1 USBINTR_D: UEE Position */ -#define USB1_USBINTR_D_UEE_Msk (0x01UL << USB1_USBINTR_D_UEE_Pos) /*!< USB1 USBINTR_D: UEE Mask */ -#define USB1_USBINTR_D_PCE_Pos 2 /*!< USB1 USBINTR_D: PCE Position */ -#define USB1_USBINTR_D_PCE_Msk (0x01UL << USB1_USBINTR_D_PCE_Pos) /*!< USB1 USBINTR_D: PCE Mask */ -#define USB1_USBINTR_D_URE_Pos 6 /*!< USB1 USBINTR_D: URE Position */ -#define USB1_USBINTR_D_URE_Msk (0x01UL << USB1_USBINTR_D_URE_Pos) /*!< USB1 USBINTR_D: URE Mask */ -#define USB1_USBINTR_D_SRE_Pos 7 /*!< USB1 USBINTR_D: SRE Position */ -#define USB1_USBINTR_D_SRE_Msk (0x01UL << USB1_USBINTR_D_SRE_Pos) /*!< USB1 USBINTR_D: SRE Mask */ -#define USB1_USBINTR_D_SLE_Pos 8 /*!< USB1 USBINTR_D: SLE Position */ -#define USB1_USBINTR_D_SLE_Msk (0x01UL << USB1_USBINTR_D_SLE_Pos) /*!< USB1 USBINTR_D: SLE Mask */ -#define USB1_USBINTR_D_NAKE_Pos 16 /*!< USB1 USBINTR_D: NAKE Position */ -#define USB1_USBINTR_D_NAKE_Msk (0x01UL << USB1_USBINTR_D_NAKE_Pos) /*!< USB1 USBINTR_D: NAKE Mask */ -#define USB1_USBINTR_D_UAIE_Pos 18 /*!< USB1 USBINTR_D: UAIE Position */ -#define USB1_USBINTR_D_UAIE_Msk (0x01UL << USB1_USBINTR_D_UAIE_Pos) /*!< USB1 USBINTR_D: UAIE Mask */ -#define USB1_USBINTR_D_UPIA_Pos 19 /*!< USB1 USBINTR_D: UPIA Position */ -#define USB1_USBINTR_D_UPIA_Msk (0x01UL << USB1_USBINTR_D_UPIA_Pos) /*!< USB1 USBINTR_D: UPIA Mask */ - -// ------------------------------------- USB1_USBINTR_H ----------------------------------------- -#define USB1_USBINTR_H_UE_Pos 0 /*!< USB1 USBINTR_H: UE Position */ -#define USB1_USBINTR_H_UE_Msk (0x01UL << USB1_USBINTR_H_UE_Pos) /*!< USB1 USBINTR_H: UE Mask */ -#define USB1_USBINTR_H_UEE_Pos 1 /*!< USB1 USBINTR_H: UEE Position */ -#define USB1_USBINTR_H_UEE_Msk (0x01UL << USB1_USBINTR_H_UEE_Pos) /*!< USB1 USBINTR_H: UEE Mask */ -#define USB1_USBINTR_H_PCE_Pos 2 /*!< USB1 USBINTR_H: PCE Position */ -#define USB1_USBINTR_H_PCE_Msk (0x01UL << USB1_USBINTR_H_PCE_Pos) /*!< USB1 USBINTR_H: PCE Mask */ -#define USB1_USBINTR_H_FRE_Pos 3 /*!< USB1 USBINTR_H: FRE Position */ -#define USB1_USBINTR_H_FRE_Msk (0x01UL << USB1_USBINTR_H_FRE_Pos) /*!< USB1 USBINTR_H: FRE Mask */ -#define USB1_USBINTR_H_AAE_Pos 5 /*!< USB1 USBINTR_H: AAE Position */ -#define USB1_USBINTR_H_AAE_Msk (0x01UL << USB1_USBINTR_H_AAE_Pos) /*!< USB1 USBINTR_H: AAE Mask */ -#define USB1_USBINTR_H_SRE_Pos 7 /*!< USB1 USBINTR_H: SRE Position */ -#define USB1_USBINTR_H_SRE_Msk (0x01UL << USB1_USBINTR_H_SRE_Pos) /*!< USB1 USBINTR_H: SRE Mask */ -#define USB1_USBINTR_H_UAIE_Pos 18 /*!< USB1 USBINTR_H: UAIE Position */ -#define USB1_USBINTR_H_UAIE_Msk (0x01UL << USB1_USBINTR_H_UAIE_Pos) /*!< USB1 USBINTR_H: UAIE Mask */ -#define USB1_USBINTR_H_UPIA_Pos 19 /*!< USB1 USBINTR_H: UPIA Position */ -#define USB1_USBINTR_H_UPIA_Msk (0x01UL << USB1_USBINTR_H_UPIA_Pos) /*!< USB1 USBINTR_H: UPIA Mask */ - -// ------------------------------------- USB1_FRINDEX_D ----------------------------------------- -#define USB1_FRINDEX_D_FRINDEX2_0_Pos 0 /*!< USB1 FRINDEX_D: FRINDEX2_0 Position */ -#define USB1_FRINDEX_D_FRINDEX2_0_Msk (0x07UL << USB1_FRINDEX_D_FRINDEX2_0_Pos) /*!< USB1 FRINDEX_D: FRINDEX2_0 Mask */ -#define USB1_FRINDEX_D_FRINDEX13_3_Pos 3 /*!< USB1 FRINDEX_D: FRINDEX13_3 Position */ -#define USB1_FRINDEX_D_FRINDEX13_3_Msk (0x000007ffUL << USB1_FRINDEX_D_FRINDEX13_3_Pos) /*!< USB1 FRINDEX_D: FRINDEX13_3 Mask */ - -// ------------------------------------- USB1_FRINDEX_H ----------------------------------------- -#define USB1_FRINDEX_H_FRINDEX2_0_Pos 0 /*!< USB1 FRINDEX_H: FRINDEX2_0 Position */ -#define USB1_FRINDEX_H_FRINDEX2_0_Msk (0x07UL << USB1_FRINDEX_H_FRINDEX2_0_Pos) /*!< USB1 FRINDEX_H: FRINDEX2_0 Mask */ -#define USB1_FRINDEX_H_FRINDEX12_3_Pos 3 /*!< USB1 FRINDEX_H: FRINDEX12_3 Position */ -#define USB1_FRINDEX_H_FRINDEX12_3_Msk (0x000003ffUL << USB1_FRINDEX_H_FRINDEX12_3_Pos) /*!< USB1 FRINDEX_H: FRINDEX12_3 Mask */ - -// ------------------------------------- USB1_DEVICEADDR ---------------------------------------- -#define USB1_DEVICEADDR_USBADRA_Pos 24 /*!< USB1 DEVICEADDR: USBADRA Position */ -#define USB1_DEVICEADDR_USBADRA_Msk (0x01UL << USB1_DEVICEADDR_USBADRA_Pos) /*!< USB1 DEVICEADDR: USBADRA Mask */ -#define USB1_DEVICEADDR_USBADR_Pos 25 /*!< USB1 DEVICEADDR: USBADR Position */ -#define USB1_DEVICEADDR_USBADR_Msk (0x7fUL << USB1_DEVICEADDR_USBADR_Pos) /*!< USB1 DEVICEADDR: USBADR Mask */ - -// ---------------------------------- USB1_PERIODICLISTBASE ------------------------------------- -#define USB1_PERIODICLISTBASE_PERBASE31_12_Pos 12 /*!< USB1 PERIODICLISTBASE: PERBASE31_12 Position */ -#define USB1_PERIODICLISTBASE_PERBASE31_12_Msk (0x000fffffUL << USB1_PERIODICLISTBASE_PERBASE31_12_Pos) /*!< USB1 PERIODICLISTBASE: PERBASE31_12 Mask */ - -// ---------------------------------- USB1_ENDPOINTLISTADDR ------------------------------------- -#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos 11 /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Position */ -#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Msk (0x001fffffUL << USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos) /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Mask */ - -// ----------------------------------- USB1_ASYNCLISTADDR --------------------------------------- -#define USB1_ASYNCLISTADDR_ASYBASE31_5_Pos 5 /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Position */ -#define USB1_ASYNCLISTADDR_ASYBASE31_5_Msk (0x07ffffffUL << USB1_ASYNCLISTADDR_ASYBASE31_5_Pos) /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Mask */ - -// --------------------------------------- USB1_TTCTRL ------------------------------------------ -#define USB1_TTCTRL_TTHA_Pos 24 /*!< USB1 TTCTRL: TTHA Position */ -#define USB1_TTCTRL_TTHA_Msk (0x7fUL << USB1_TTCTRL_TTHA_Pos) /*!< USB1 TTCTRL: TTHA Mask */ - -// ------------------------------------- USB1_BURSTSIZE ----------------------------------------- -#define USB1_BURSTSIZE_RXPBURST_Pos 0 /*!< USB1 BURSTSIZE: RXPBURST Position */ -#define USB1_BURSTSIZE_RXPBURST_Msk (0x000000ffUL << USB1_BURSTSIZE_RXPBURST_Pos) /*!< USB1 BURSTSIZE: RXPBURST Mask */ -#define USB1_BURSTSIZE_TXPBURST_Pos 8 /*!< USB1 BURSTSIZE: TXPBURST Position */ -#define USB1_BURSTSIZE_TXPBURST_Msk (0x000000ffUL << USB1_BURSTSIZE_TXPBURST_Pos) /*!< USB1 BURSTSIZE: TXPBURST Mask */ - -// ------------------------------------ USB1_TXFILLTUNING --------------------------------------- -#define USB1_TXFILLTUNING_TXSCHOH_Pos 0 /*!< USB1 TXFILLTUNING: TXSCHOH Position */ -#define USB1_TXFILLTUNING_TXSCHOH_Msk (0x000000ffUL << USB1_TXFILLTUNING_TXSCHOH_Pos) /*!< USB1 TXFILLTUNING: TXSCHOH Mask */ -#define USB1_TXFILLTUNING_TXSCHEATLTH_Pos 8 /*!< USB1 TXFILLTUNING: TXSCHEATLTH Position */ -#define USB1_TXFILLTUNING_TXSCHEATLTH_Msk (0x1fUL << USB1_TXFILLTUNING_TXSCHEATLTH_Pos) /*!< USB1 TXFILLTUNING: TXSCHEATLTH Mask */ -#define USB1_TXFILLTUNING_TXFIFOTHRES_Pos 16 /*!< USB1 TXFILLTUNING: TXFIFOTHRES Position */ -#define USB1_TXFILLTUNING_TXFIFOTHRES_Msk (0x3fUL << USB1_TXFILLTUNING_TXFIFOTHRES_Pos) /*!< USB1 TXFILLTUNING: TXFIFOTHRES Mask */ - -// ------------------------------------ USB1_ULPIVIEWPORT --------------------------------------- -#define USB1_ULPIVIEWPORT_ULPIDATWR_Pos 0 /*!< USB1 ULPIVIEWPORT: ULPIDATWR Position */ -#define USB1_ULPIVIEWPORT_ULPIDATWR_Msk (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATWR_Pos) /*!< USB1 ULPIVIEWPORT: ULPIDATWR Mask */ -#define USB1_ULPIVIEWPORT_ULPIDATRD_Pos 8 /*!< USB1 ULPIVIEWPORT: ULPIDATRD Position */ -#define USB1_ULPIVIEWPORT_ULPIDATRD_Msk (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATRD_Pos) /*!< USB1 ULPIVIEWPORT: ULPIDATRD Mask */ -#define USB1_ULPIVIEWPORT_ULPIADDR_Pos 16 /*!< USB1 ULPIVIEWPORT: ULPIADDR Position */ -#define USB1_ULPIVIEWPORT_ULPIADDR_Msk (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIADDR_Pos) /*!< USB1 ULPIVIEWPORT: ULPIADDR Mask */ -#define USB1_ULPIVIEWPORT_ULPIPORT_Pos 24 /*!< USB1 ULPIVIEWPORT: ULPIPORT Position */ -#define USB1_ULPIVIEWPORT_ULPIPORT_Msk (0x07UL << USB1_ULPIVIEWPORT_ULPIPORT_Pos) /*!< USB1 ULPIVIEWPORT: ULPIPORT Mask */ -#define USB1_ULPIVIEWPORT_ULPISS_Pos 27 /*!< USB1 ULPIVIEWPORT: ULPISS Position */ -#define USB1_ULPIVIEWPORT_ULPISS_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPISS_Pos) /*!< USB1 ULPIVIEWPORT: ULPISS Mask */ -#define USB1_ULPIVIEWPORT_ULPIRW_Pos 29 /*!< USB1 ULPIVIEWPORT: ULPIRW Position */ -#define USB1_ULPIVIEWPORT_ULPIRW_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPIRW_Pos) /*!< USB1 ULPIVIEWPORT: ULPIRW Mask */ -#define USB1_ULPIVIEWPORT_ULPIRUN_Pos 30 /*!< USB1 ULPIVIEWPORT: ULPIRUN Position */ -#define USB1_ULPIVIEWPORT_ULPIRUN_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPIRUN_Pos) /*!< USB1 ULPIVIEWPORT: ULPIRUN Mask */ -#define USB1_ULPIVIEWPORT_ULPIWU_Pos 31 /*!< USB1 ULPIVIEWPORT: ULPIWU Position */ -#define USB1_ULPIVIEWPORT_ULPIWU_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPIWU_Pos) /*!< USB1 ULPIVIEWPORT: ULPIWU Mask */ - -// ------------------------------------- USB1_BINTERVAL ----------------------------------------- -#define USB1_BINTERVAL_BINT_Pos 0 /*!< USB1 BINTERVAL: BINT Position */ -#define USB1_BINTERVAL_BINT_Msk (0x0fUL << USB1_BINTERVAL_BINT_Pos) /*!< USB1 BINTERVAL: BINT Mask */ - -// -------------------------------------- USB1_ENDPTNAK ----------------------------------------- -#define USB1_ENDPTNAK_EPRN0_Pos 0 /*!< USB1 ENDPTNAK: EPRN0 Position */ -#define USB1_ENDPTNAK_EPRN0_Msk (0x01UL << USB1_ENDPTNAK_EPRN0_Pos) /*!< USB1 ENDPTNAK: EPRN0 Mask */ -#define USB1_ENDPTNAK_EPRN1_Pos 1 /*!< USB1 ENDPTNAK: EPRN1 Position */ -#define USB1_ENDPTNAK_EPRN1_Msk (0x01UL << USB1_ENDPTNAK_EPRN1_Pos) /*!< USB1 ENDPTNAK: EPRN1 Mask */ -#define USB1_ENDPTNAK_EPRN2_Pos 2 /*!< USB1 ENDPTNAK: EPRN2 Position */ -#define USB1_ENDPTNAK_EPRN2_Msk (0x01UL << USB1_ENDPTNAK_EPRN2_Pos) /*!< USB1 ENDPTNAK: EPRN2 Mask */ -#define USB1_ENDPTNAK_EPRN3_Pos 3 /*!< USB1 ENDPTNAK: EPRN3 Position */ -#define USB1_ENDPTNAK_EPRN3_Msk (0x01UL << USB1_ENDPTNAK_EPRN3_Pos) /*!< USB1 ENDPTNAK: EPRN3 Mask */ -#define USB1_ENDPTNAK_EPTN16_Pos 16 /*!< USB1 ENDPTNAK: EPTN16 Position */ -#define USB1_ENDPTNAK_EPTN16_Msk (0x01UL << USB1_ENDPTNAK_EPTN16_Pos) /*!< USB1 ENDPTNAK: EPTN16 Mask */ -#define USB1_ENDPTNAK_EPTN17_Pos 17 /*!< USB1 ENDPTNAK: EPTN17 Position */ -#define USB1_ENDPTNAK_EPTN17_Msk (0x01UL << USB1_ENDPTNAK_EPTN17_Pos) /*!< USB1 ENDPTNAK: EPTN17 Mask */ -#define USB1_ENDPTNAK_EPTN18_Pos 18 /*!< USB1 ENDPTNAK: EPTN18 Position */ -#define USB1_ENDPTNAK_EPTN18_Msk (0x01UL << USB1_ENDPTNAK_EPTN18_Pos) /*!< USB1 ENDPTNAK: EPTN18 Mask */ -#define USB1_ENDPTNAK_EPTN19_Pos 19 /*!< USB1 ENDPTNAK: EPTN19 Position */ -#define USB1_ENDPTNAK_EPTN19_Msk (0x01UL << USB1_ENDPTNAK_EPTN19_Pos) /*!< USB1 ENDPTNAK: EPTN19 Mask */ - -// ------------------------------------- USB1_ENDPTNAKEN ---------------------------------------- -#define USB1_ENDPTNAKEN_EPRNE0_Pos 0 /*!< USB1 ENDPTNAKEN: EPRNE0 Position */ -#define USB1_ENDPTNAKEN_EPRNE0_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE0_Pos) /*!< USB1 ENDPTNAKEN: EPRNE0 Mask */ -#define USB1_ENDPTNAKEN_EPRNE1_Pos 1 /*!< USB1 ENDPTNAKEN: EPRNE1 Position */ -#define USB1_ENDPTNAKEN_EPRNE1_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE1_Pos) /*!< USB1 ENDPTNAKEN: EPRNE1 Mask */ -#define USB1_ENDPTNAKEN_EPRNE2_Pos 2 /*!< USB1 ENDPTNAKEN: EPRNE2 Position */ -#define USB1_ENDPTNAKEN_EPRNE2_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE2_Pos) /*!< USB1 ENDPTNAKEN: EPRNE2 Mask */ -#define USB1_ENDPTNAKEN_EPRNE3_Pos 3 /*!< USB1 ENDPTNAKEN: EPRNE3 Position */ -#define USB1_ENDPTNAKEN_EPRNE3_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE3_Pos) /*!< USB1 ENDPTNAKEN: EPRNE3 Mask */ -#define USB1_ENDPTNAKEN_EPTNE16_Pos 16 /*!< USB1 ENDPTNAKEN: EPTNE16 Position */ -#define USB1_ENDPTNAKEN_EPTNE16_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE16_Pos) /*!< USB1 ENDPTNAKEN: EPTNE16 Mask */ -#define USB1_ENDPTNAKEN_EPTNE17_Pos 17 /*!< USB1 ENDPTNAKEN: EPTNE17 Position */ -#define USB1_ENDPTNAKEN_EPTNE17_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE17_Pos) /*!< USB1 ENDPTNAKEN: EPTNE17 Mask */ -#define USB1_ENDPTNAKEN_EPTNE18_Pos 18 /*!< USB1 ENDPTNAKEN: EPTNE18 Position */ -#define USB1_ENDPTNAKEN_EPTNE18_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE18_Pos) /*!< USB1 ENDPTNAKEN: EPTNE18 Mask */ -#define USB1_ENDPTNAKEN_EPTNE19_Pos 19 /*!< USB1 ENDPTNAKEN: EPTNE19 Position */ -#define USB1_ENDPTNAKEN_EPTNE19_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE19_Pos) /*!< USB1 ENDPTNAKEN: EPTNE19 Mask */ - -// ------------------------------------- USB1_PORTSC1_D ----------------------------------------- -#define USB1_PORTSC1_D_CCS_Pos 0 /*!< USB1 PORTSC1_D: CCS Position */ -#define USB1_PORTSC1_D_CCS_Msk (0x01UL << USB1_PORTSC1_D_CCS_Pos) /*!< USB1 PORTSC1_D: CCS Mask */ -#define USB1_PORTSC1_D_CSC_Pos 1 /*!< USB1 PORTSC1_D: CSC Position */ -#define USB1_PORTSC1_D_CSC_Msk (0x01UL << USB1_PORTSC1_D_CSC_Pos) /*!< USB1 PORTSC1_D: CSC Mask */ -#define USB1_PORTSC1_D_PE_Pos 2 /*!< USB1 PORTSC1_D: PE Position */ -#define USB1_PORTSC1_D_PE_Msk (0x01UL << USB1_PORTSC1_D_PE_Pos) /*!< USB1 PORTSC1_D: PE Mask */ -#define USB1_PORTSC1_D_PEC_Pos 3 /*!< USB1 PORTSC1_D: PEC Position */ -#define USB1_PORTSC1_D_PEC_Msk (0x01UL << USB1_PORTSC1_D_PEC_Pos) /*!< USB1 PORTSC1_D: PEC Mask */ -#define USB1_PORTSC1_D_FPR_Pos 6 /*!< USB1 PORTSC1_D: FPR Position */ -#define USB1_PORTSC1_D_FPR_Msk (0x01UL << USB1_PORTSC1_D_FPR_Pos) /*!< USB1 PORTSC1_D: FPR Mask */ -#define USB1_PORTSC1_D_SUSP_Pos 7 /*!< USB1 PORTSC1_D: SUSP Position */ -#define USB1_PORTSC1_D_SUSP_Msk (0x01UL << USB1_PORTSC1_D_SUSP_Pos) /*!< USB1 PORTSC1_D: SUSP Mask */ -#define USB1_PORTSC1_D_PR_Pos 8 /*!< USB1 PORTSC1_D: PR Position */ -#define USB1_PORTSC1_D_PR_Msk (0x01UL << USB1_PORTSC1_D_PR_Pos) /*!< USB1 PORTSC1_D: PR Mask */ -#define USB1_PORTSC1_D_HSP_Pos 9 /*!< USB1 PORTSC1_D: HSP Position */ -#define USB1_PORTSC1_D_HSP_Msk (0x01UL << USB1_PORTSC1_D_HSP_Pos) /*!< USB1 PORTSC1_D: HSP Mask */ -#define USB1_PORTSC1_D_LS_Pos 10 /*!< USB1 PORTSC1_D: LS Position */ -#define USB1_PORTSC1_D_LS_Msk (0x03UL << USB1_PORTSC1_D_LS_Pos) /*!< USB1 PORTSC1_D: LS Mask */ -#define USB1_PORTSC1_D_PP_Pos 12 /*!< USB1 PORTSC1_D: PP Position */ -#define USB1_PORTSC1_D_PP_Msk (0x01UL << USB1_PORTSC1_D_PP_Pos) /*!< USB1 PORTSC1_D: PP Mask */ -#define USB1_PORTSC1_D_PIC1_0_Pos 14 /*!< USB1 PORTSC1_D: PIC1_0 Position */ -#define USB1_PORTSC1_D_PIC1_0_Msk (0x03UL << USB1_PORTSC1_D_PIC1_0_Pos) /*!< USB1 PORTSC1_D: PIC1_0 Mask */ -#define USB1_PORTSC1_D_PTC3_0_Pos 16 /*!< USB1 PORTSC1_D: PTC3_0 Position */ -#define USB1_PORTSC1_D_PTC3_0_Msk (0x0fUL << USB1_PORTSC1_D_PTC3_0_Pos) /*!< USB1 PORTSC1_D: PTC3_0 Mask */ -#define USB1_PORTSC1_D_PHCD_Pos 23 /*!< USB1 PORTSC1_D: PHCD Position */ -#define USB1_PORTSC1_D_PHCD_Msk (0x01UL << USB1_PORTSC1_D_PHCD_Pos) /*!< USB1 PORTSC1_D: PHCD Mask */ -#define USB1_PORTSC1_D_PFSC_Pos 24 /*!< USB1 PORTSC1_D: PFSC Position */ -#define USB1_PORTSC1_D_PFSC_Msk (0x01UL << USB1_PORTSC1_D_PFSC_Pos) /*!< USB1 PORTSC1_D: PFSC Mask */ -#define USB1_PORTSC1_D_PSPD_Pos 26 /*!< USB1 PORTSC1_D: PSPD Position */ -#define USB1_PORTSC1_D_PSPD_Msk (0x03UL << USB1_PORTSC1_D_PSPD_Pos) /*!< USB1 PORTSC1_D: PSPD Mask */ -#define USB1_PORTSC1_D_PTS_Pos 30 /*!< USB1 PORTSC1_D: PTS Position */ -#define USB1_PORTSC1_D_PTS_Msk (0x03UL << USB1_PORTSC1_D_PTS_Pos) /*!< USB1 PORTSC1_D: PTS Mask */ - -// ------------------------------------- USB1_PORTSC1_H ----------------------------------------- -#define USB1_PORTSC1_H_CCS_Pos 0 /*!< USB1 PORTSC1_H: CCS Position */ -#define USB1_PORTSC1_H_CCS_Msk (0x01UL << USB1_PORTSC1_H_CCS_Pos) /*!< USB1 PORTSC1_H: CCS Mask */ -#define USB1_PORTSC1_H_CSC_Pos 1 /*!< USB1 PORTSC1_H: CSC Position */ -#define USB1_PORTSC1_H_CSC_Msk (0x01UL << USB1_PORTSC1_H_CSC_Pos) /*!< USB1 PORTSC1_H: CSC Mask */ -#define USB1_PORTSC1_H_PE_Pos 2 /*!< USB1 PORTSC1_H: PE Position */ -#define USB1_PORTSC1_H_PE_Msk (0x01UL << USB1_PORTSC1_H_PE_Pos) /*!< USB1 PORTSC1_H: PE Mask */ -#define USB1_PORTSC1_H_PEC_Pos 3 /*!< USB1 PORTSC1_H: PEC Position */ -#define USB1_PORTSC1_H_PEC_Msk (0x01UL << USB1_PORTSC1_H_PEC_Pos) /*!< USB1 PORTSC1_H: PEC Mask */ -#define USB1_PORTSC1_H_OCA_Pos 4 /*!< USB1 PORTSC1_H: OCA Position */ -#define USB1_PORTSC1_H_OCA_Msk (0x01UL << USB1_PORTSC1_H_OCA_Pos) /*!< USB1 PORTSC1_H: OCA Mask */ -#define USB1_PORTSC1_H_OCC_Pos 5 /*!< USB1 PORTSC1_H: OCC Position */ -#define USB1_PORTSC1_H_OCC_Msk (0x01UL << USB1_PORTSC1_H_OCC_Pos) /*!< USB1 PORTSC1_H: OCC Mask */ -#define USB1_PORTSC1_H_FPR_Pos 6 /*!< USB1 PORTSC1_H: FPR Position */ -#define USB1_PORTSC1_H_FPR_Msk (0x01UL << USB1_PORTSC1_H_FPR_Pos) /*!< USB1 PORTSC1_H: FPR Mask */ -#define USB1_PORTSC1_H_SUSP_Pos 7 /*!< USB1 PORTSC1_H: SUSP Position */ -#define USB1_PORTSC1_H_SUSP_Msk (0x01UL << USB1_PORTSC1_H_SUSP_Pos) /*!< USB1 PORTSC1_H: SUSP Mask */ -#define USB1_PORTSC1_H_PR_Pos 8 /*!< USB1 PORTSC1_H: PR Position */ -#define USB1_PORTSC1_H_PR_Msk (0x01UL << USB1_PORTSC1_H_PR_Pos) /*!< USB1 PORTSC1_H: PR Mask */ -#define USB1_PORTSC1_H_HSP_Pos 9 /*!< USB1 PORTSC1_H: HSP Position */ -#define USB1_PORTSC1_H_HSP_Msk (0x01UL << USB1_PORTSC1_H_HSP_Pos) /*!< USB1 PORTSC1_H: HSP Mask */ -#define USB1_PORTSC1_H_LS_Pos 10 /*!< USB1 PORTSC1_H: LS Position */ -#define USB1_PORTSC1_H_LS_Msk (0x03UL << USB1_PORTSC1_H_LS_Pos) /*!< USB1 PORTSC1_H: LS Mask */ -#define USB1_PORTSC1_H_PP_Pos 12 /*!< USB1 PORTSC1_H: PP Position */ -#define USB1_PORTSC1_H_PP_Msk (0x01UL << USB1_PORTSC1_H_PP_Pos) /*!< USB1 PORTSC1_H: PP Mask */ -#define USB1_PORTSC1_H_PIC1_0_Pos 14 /*!< USB1 PORTSC1_H: PIC1_0 Position */ -#define USB1_PORTSC1_H_PIC1_0_Msk (0x03UL << USB1_PORTSC1_H_PIC1_0_Pos) /*!< USB1 PORTSC1_H: PIC1_0 Mask */ -#define USB1_PORTSC1_H_PTC3_0_Pos 16 /*!< USB1 PORTSC1_H: PTC3_0 Position */ -#define USB1_PORTSC1_H_PTC3_0_Msk (0x0fUL << USB1_PORTSC1_H_PTC3_0_Pos) /*!< USB1 PORTSC1_H: PTC3_0 Mask */ -#define USB1_PORTSC1_H_WKCN_Pos 20 /*!< USB1 PORTSC1_H: WKCN Position */ -#define USB1_PORTSC1_H_WKCN_Msk (0x01UL << USB1_PORTSC1_H_WKCN_Pos) /*!< USB1 PORTSC1_H: WKCN Mask */ -#define USB1_PORTSC1_H_WKDC_Pos 21 /*!< USB1 PORTSC1_H: WKDC Position */ -#define USB1_PORTSC1_H_WKDC_Msk (0x01UL << USB1_PORTSC1_H_WKDC_Pos) /*!< USB1 PORTSC1_H: WKDC Mask */ -#define USB1_PORTSC1_H_WKOC_Pos 22 /*!< USB1 PORTSC1_H: WKOC Position */ -#define USB1_PORTSC1_H_WKOC_Msk (0x01UL << USB1_PORTSC1_H_WKOC_Pos) /*!< USB1 PORTSC1_H: WKOC Mask */ -#define USB1_PORTSC1_H_PHCD_Pos 23 /*!< USB1 PORTSC1_H: PHCD Position */ -#define USB1_PORTSC1_H_PHCD_Msk (0x01UL << USB1_PORTSC1_H_PHCD_Pos) /*!< USB1 PORTSC1_H: PHCD Mask */ -#define USB1_PORTSC1_H_PFSC_Pos 24 /*!< USB1 PORTSC1_H: PFSC Position */ -#define USB1_PORTSC1_H_PFSC_Msk (0x01UL << USB1_PORTSC1_H_PFSC_Pos) /*!< USB1 PORTSC1_H: PFSC Mask */ -#define USB1_PORTSC1_H_PSPD_Pos 26 /*!< USB1 PORTSC1_H: PSPD Position */ -#define USB1_PORTSC1_H_PSPD_Msk (0x03UL << USB1_PORTSC1_H_PSPD_Pos) /*!< USB1 PORTSC1_H: PSPD Mask */ -#define USB1_PORTSC1_H_PTS_Pos 30 /*!< USB1 PORTSC1_H: PTS Position */ -#define USB1_PORTSC1_H_PTS_Msk (0x03UL << USB1_PORTSC1_H_PTS_Pos) /*!< USB1 PORTSC1_H: PTS Mask */ - -// ------------------------------------- USB1_USBMODE_D ----------------------------------------- -#define USB1_USBMODE_D_CM1_0_Pos 0 /*!< USB1 USBMODE_D: CM1_0 Position */ -#define USB1_USBMODE_D_CM1_0_Msk (0x03UL << USB1_USBMODE_D_CM1_0_Pos) /*!< USB1 USBMODE_D: CM1_0 Mask */ -#define USB1_USBMODE_D_ES_Pos 2 /*!< USB1 USBMODE_D: ES Position */ -#define USB1_USBMODE_D_ES_Msk (0x01UL << USB1_USBMODE_D_ES_Pos) /*!< USB1 USBMODE_D: ES Mask */ -#define USB1_USBMODE_D_SLOM_Pos 3 /*!< USB1 USBMODE_D: SLOM Position */ -#define USB1_USBMODE_D_SLOM_Msk (0x01UL << USB1_USBMODE_D_SLOM_Pos) /*!< USB1 USBMODE_D: SLOM Mask */ -#define USB1_USBMODE_D_SDIS_Pos 4 /*!< USB1 USBMODE_D: SDIS Position */ -#define USB1_USBMODE_D_SDIS_Msk (0x01UL << USB1_USBMODE_D_SDIS_Pos) /*!< USB1 USBMODE_D: SDIS Mask */ - -// ------------------------------------- USB1_USBMODE_H ----------------------------------------- -#define USB1_USBMODE_H_CM1_0_Pos 0 /*!< USB1 USBMODE_H: CM1_0 Position */ -#define USB1_USBMODE_H_CM1_0_Msk (0x03UL << USB1_USBMODE_H_CM1_0_Pos) /*!< USB1 USBMODE_H: CM1_0 Mask */ -#define USB1_USBMODE_H_ES_Pos 2 /*!< USB1 USBMODE_H: ES Position */ -#define USB1_USBMODE_H_ES_Msk (0x01UL << USB1_USBMODE_H_ES_Pos) /*!< USB1 USBMODE_H: ES Mask */ -#define USB1_USBMODE_H_SDIS_Pos 4 /*!< USB1 USBMODE_H: SDIS Position */ -#define USB1_USBMODE_H_SDIS_Msk (0x01UL << USB1_USBMODE_H_SDIS_Pos) /*!< USB1 USBMODE_H: SDIS Mask */ -#define USB1_USBMODE_H_VBPS_Pos 5 /*!< USB1 USBMODE_H: VBPS Position */ -#define USB1_USBMODE_H_VBPS_Msk (0x01UL << USB1_USBMODE_H_VBPS_Pos) /*!< USB1 USBMODE_H: VBPS Mask */ - -// ----------------------------------- USB1_ENDPTSETUPSTAT -------------------------------------- -#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos 0 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */ -#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */ -#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos 1 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */ -#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */ -#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos 2 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */ -#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */ -#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos 3 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */ -#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */ - -// ------------------------------------- USB1_ENDPTPRIME ---------------------------------------- -#define USB1_ENDPTPRIME_PERB0_Pos 0 /*!< USB1 ENDPTPRIME: PERB0 Position */ -#define USB1_ENDPTPRIME_PERB0_Msk (0x01UL << USB1_ENDPTPRIME_PERB0_Pos) /*!< USB1 ENDPTPRIME: PERB0 Mask */ -#define USB1_ENDPTPRIME_PERB1_Pos 1 /*!< USB1 ENDPTPRIME: PERB1 Position */ -#define USB1_ENDPTPRIME_PERB1_Msk (0x01UL << USB1_ENDPTPRIME_PERB1_Pos) /*!< USB1 ENDPTPRIME: PERB1 Mask */ -#define USB1_ENDPTPRIME_PERB2_Pos 2 /*!< USB1 ENDPTPRIME: PERB2 Position */ -#define USB1_ENDPTPRIME_PERB2_Msk (0x01UL << USB1_ENDPTPRIME_PERB2_Pos) /*!< USB1 ENDPTPRIME: PERB2 Mask */ -#define USB1_ENDPTPRIME_PERB3_Pos 3 /*!< USB1 ENDPTPRIME: PERB3 Position */ -#define USB1_ENDPTPRIME_PERB3_Msk (0x01UL << USB1_ENDPTPRIME_PERB3_Pos) /*!< USB1 ENDPTPRIME: PERB3 Mask */ -#define USB1_ENDPTPRIME_PETB0_Pos 16 /*!< USB1 ENDPTPRIME: PETB0 Position */ -#define USB1_ENDPTPRIME_PETB0_Msk (0x01UL << USB1_ENDPTPRIME_PETB0_Pos) /*!< USB1 ENDPTPRIME: PETB0 Mask */ -#define USB1_ENDPTPRIME_PETB1_Pos 17 /*!< USB1 ENDPTPRIME: PETB1 Position */ -#define USB1_ENDPTPRIME_PETB1_Msk (0x01UL << USB1_ENDPTPRIME_PETB1_Pos) /*!< USB1 ENDPTPRIME: PETB1 Mask */ -#define USB1_ENDPTPRIME_PETB2_Pos 18 /*!< USB1 ENDPTPRIME: PETB2 Position */ -#define USB1_ENDPTPRIME_PETB2_Msk (0x01UL << USB1_ENDPTPRIME_PETB2_Pos) /*!< USB1 ENDPTPRIME: PETB2 Mask */ -#define USB1_ENDPTPRIME_PETB3_Pos 19 /*!< USB1 ENDPTPRIME: PETB3 Position */ -#define USB1_ENDPTPRIME_PETB3_Msk (0x01UL << USB1_ENDPTPRIME_PETB3_Pos) /*!< USB1 ENDPTPRIME: PETB3 Mask */ - -// ------------------------------------- USB1_ENDPTFLUSH ---------------------------------------- -#define USB1_ENDPTFLUSH_FERB0_Pos 0 /*!< USB1 ENDPTFLUSH: FERB0 Position */ -#define USB1_ENDPTFLUSH_FERB0_Msk (0x01UL << USB1_ENDPTFLUSH_FERB0_Pos) /*!< USB1 ENDPTFLUSH: FERB0 Mask */ -#define USB1_ENDPTFLUSH_FERB1_Pos 1 /*!< USB1 ENDPTFLUSH: FERB1 Position */ -#define USB1_ENDPTFLUSH_FERB1_Msk (0x01UL << USB1_ENDPTFLUSH_FERB1_Pos) /*!< USB1 ENDPTFLUSH: FERB1 Mask */ -#define USB1_ENDPTFLUSH_FERB2_Pos 2 /*!< USB1 ENDPTFLUSH: FERB2 Position */ -#define USB1_ENDPTFLUSH_FERB2_Msk (0x01UL << USB1_ENDPTFLUSH_FERB2_Pos) /*!< USB1 ENDPTFLUSH: FERB2 Mask */ -#define USB1_ENDPTFLUSH_FERB3_Pos 3 /*!< USB1 ENDPTFLUSH: FERB3 Position */ -#define USB1_ENDPTFLUSH_FERB3_Msk (0x01UL << USB1_ENDPTFLUSH_FERB3_Pos) /*!< USB1 ENDPTFLUSH: FERB3 Mask */ -#define USB1_ENDPTFLUSH_FETB0_Pos 16 /*!< USB1 ENDPTFLUSH: FETB0 Position */ -#define USB1_ENDPTFLUSH_FETB0_Msk (0x01UL << USB1_ENDPTFLUSH_FETB0_Pos) /*!< USB1 ENDPTFLUSH: FETB0 Mask */ -#define USB1_ENDPTFLUSH_FETB1_Pos 17 /*!< USB1 ENDPTFLUSH: FETB1 Position */ -#define USB1_ENDPTFLUSH_FETB1_Msk (0x01UL << USB1_ENDPTFLUSH_FETB1_Pos) /*!< USB1 ENDPTFLUSH: FETB1 Mask */ -#define USB1_ENDPTFLUSH_FETB2_Pos 18 /*!< USB1 ENDPTFLUSH: FETB2 Position */ -#define USB1_ENDPTFLUSH_FETB2_Msk (0x01UL << USB1_ENDPTFLUSH_FETB2_Pos) /*!< USB1 ENDPTFLUSH: FETB2 Mask */ -#define USB1_ENDPTFLUSH_FETB3_Pos 19 /*!< USB1 ENDPTFLUSH: FETB3 Position */ -#define USB1_ENDPTFLUSH_FETB3_Msk (0x01UL << USB1_ENDPTFLUSH_FETB3_Pos) /*!< USB1 ENDPTFLUSH: FETB3 Mask */ - -// ------------------------------------- USB1_ENDPTSTAT ----------------------------------------- -#define USB1_ENDPTSTAT_ERBR0_Pos 0 /*!< USB1 ENDPTSTAT: ERBR0 Position */ -#define USB1_ENDPTSTAT_ERBR0_Msk (0x01UL << USB1_ENDPTSTAT_ERBR0_Pos) /*!< USB1 ENDPTSTAT: ERBR0 Mask */ -#define USB1_ENDPTSTAT_ERBR1_Pos 1 /*!< USB1 ENDPTSTAT: ERBR1 Position */ -#define USB1_ENDPTSTAT_ERBR1_Msk (0x01UL << USB1_ENDPTSTAT_ERBR1_Pos) /*!< USB1 ENDPTSTAT: ERBR1 Mask */ -#define USB1_ENDPTSTAT_ERBR2_Pos 2 /*!< USB1 ENDPTSTAT: ERBR2 Position */ -#define USB1_ENDPTSTAT_ERBR2_Msk (0x01UL << USB1_ENDPTSTAT_ERBR2_Pos) /*!< USB1 ENDPTSTAT: ERBR2 Mask */ -#define USB1_ENDPTSTAT_ERBR3_Pos 3 /*!< USB1 ENDPTSTAT: ERBR3 Position */ -#define USB1_ENDPTSTAT_ERBR3_Msk (0x01UL << USB1_ENDPTSTAT_ERBR3_Pos) /*!< USB1 ENDPTSTAT: ERBR3 Mask */ -#define USB1_ENDPTSTAT_ETBR0_Pos 16 /*!< USB1 ENDPTSTAT: ETBR0 Position */ -#define USB1_ENDPTSTAT_ETBR0_Msk (0x01UL << USB1_ENDPTSTAT_ETBR0_Pos) /*!< USB1 ENDPTSTAT: ETBR0 Mask */ -#define USB1_ENDPTSTAT_ETBR1_Pos 17 /*!< USB1 ENDPTSTAT: ETBR1 Position */ -#define USB1_ENDPTSTAT_ETBR1_Msk (0x01UL << USB1_ENDPTSTAT_ETBR1_Pos) /*!< USB1 ENDPTSTAT: ETBR1 Mask */ -#define USB1_ENDPTSTAT_ETBR2_Pos 18 /*!< USB1 ENDPTSTAT: ETBR2 Position */ -#define USB1_ENDPTSTAT_ETBR2_Msk (0x01UL << USB1_ENDPTSTAT_ETBR2_Pos) /*!< USB1 ENDPTSTAT: ETBR2 Mask */ -#define USB1_ENDPTSTAT_ETBR3_Pos 19 /*!< USB1 ENDPTSTAT: ETBR3 Position */ -#define USB1_ENDPTSTAT_ETBR3_Msk (0x01UL << USB1_ENDPTSTAT_ETBR3_Pos) /*!< USB1 ENDPTSTAT: ETBR3 Mask */ - -// ----------------------------------- USB1_ENDPTCOMPLETE --------------------------------------- -#define USB1_ENDPTCOMPLETE_ERCE0_Pos 0 /*!< USB1 ENDPTCOMPLETE: ERCE0 Position */ -#define USB1_ENDPTCOMPLETE_ERCE0_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE0_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE0 Mask */ -#define USB1_ENDPTCOMPLETE_ERCE1_Pos 1 /*!< USB1 ENDPTCOMPLETE: ERCE1 Position */ -#define USB1_ENDPTCOMPLETE_ERCE1_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE1_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE1 Mask */ -#define USB1_ENDPTCOMPLETE_ERCE2_Pos 2 /*!< USB1 ENDPTCOMPLETE: ERCE2 Position */ -#define USB1_ENDPTCOMPLETE_ERCE2_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE2_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE2 Mask */ -#define USB1_ENDPTCOMPLETE_ERCE3_Pos 3 /*!< USB1 ENDPTCOMPLETE: ERCE3 Position */ -#define USB1_ENDPTCOMPLETE_ERCE3_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE3_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE3 Mask */ -#define USB1_ENDPTCOMPLETE_ETCE0_Pos 16 /*!< USB1 ENDPTCOMPLETE: ETCE0 Position */ -#define USB1_ENDPTCOMPLETE_ETCE0_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE0_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE0 Mask */ -#define USB1_ENDPTCOMPLETE_ETCE1_Pos 17 /*!< USB1 ENDPTCOMPLETE: ETCE1 Position */ -#define USB1_ENDPTCOMPLETE_ETCE1_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE1_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE1 Mask */ -#define USB1_ENDPTCOMPLETE_ETCE2_Pos 18 /*!< USB1 ENDPTCOMPLETE: ETCE2 Position */ -#define USB1_ENDPTCOMPLETE_ETCE2_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE2_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE2 Mask */ -#define USB1_ENDPTCOMPLETE_ETCE3_Pos 19 /*!< USB1 ENDPTCOMPLETE: ETCE3 Position */ -#define USB1_ENDPTCOMPLETE_ETCE3_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE3_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE3 Mask */ - -// ------------------------------------- USB1_ENDPTCTRL0 ---------------------------------------- -#define USB1_ENDPTCTRL0_RXS_Pos 0 /*!< USB1 ENDPTCTRL0: RXS Position */ -#define USB1_ENDPTCTRL0_RXS_Msk (0x01UL << USB1_ENDPTCTRL0_RXS_Pos) /*!< USB1 ENDPTCTRL0: RXS Mask */ -#define USB1_ENDPTCTRL0_RXT_Pos 2 /*!< USB1 ENDPTCTRL0: RXT Position */ -#define USB1_ENDPTCTRL0_RXT_Msk (0x03UL << USB1_ENDPTCTRL0_RXT_Pos) /*!< USB1 ENDPTCTRL0: RXT Mask */ -#define USB1_ENDPTCTRL0_RXE_Pos 7 /*!< USB1 ENDPTCTRL0: RXE Position */ -#define USB1_ENDPTCTRL0_RXE_Msk (0x01UL << USB1_ENDPTCTRL0_RXE_Pos) /*!< USB1 ENDPTCTRL0: RXE Mask */ -#define USB1_ENDPTCTRL0_TXS_Pos 16 /*!< USB1 ENDPTCTRL0: TXS Position */ -#define USB1_ENDPTCTRL0_TXS_Msk (0x01UL << USB1_ENDPTCTRL0_TXS_Pos) /*!< USB1 ENDPTCTRL0: TXS Mask */ -#define USB1_ENDPTCTRL0_TXT_Pos 18 /*!< USB1 ENDPTCTRL0: TXT Position */ -#define USB1_ENDPTCTRL0_TXT_Msk (0x03UL << USB1_ENDPTCTRL0_TXT_Pos) /*!< USB1 ENDPTCTRL0: TXT Mask */ -#define USB1_ENDPTCTRL0_TXE_Pos 23 /*!< USB1 ENDPTCTRL0: TXE Position */ -#define USB1_ENDPTCTRL0_TXE_Msk (0x01UL << USB1_ENDPTCTRL0_TXE_Pos) /*!< USB1 ENDPTCTRL0: TXE Mask */ - -// ------------------------------------- USB1_ENDPTCTRL1 ---------------------------------------- -#define USB1_ENDPTCTRL1_RXS_Pos 0 /*!< USB1 ENDPTCTRL1: RXS Position */ -#define USB1_ENDPTCTRL1_RXS_Msk (0x01UL << USB1_ENDPTCTRL1_RXS_Pos) /*!< USB1 ENDPTCTRL1: RXS Mask */ -#define USB1_ENDPTCTRL1_RXT_Pos 2 /*!< USB1 ENDPTCTRL1: RXT Position */ -#define USB1_ENDPTCTRL1_RXT_Msk (0x03UL << USB1_ENDPTCTRL1_RXT_Pos) /*!< USB1 ENDPTCTRL1: RXT Mask */ -#define USB1_ENDPTCTRL1_RXI_Pos 5 /*!< USB1 ENDPTCTRL1: RXI Position */ -#define USB1_ENDPTCTRL1_RXI_Msk (0x01UL << USB1_ENDPTCTRL1_RXI_Pos) /*!< USB1 ENDPTCTRL1: RXI Mask */ -#define USB1_ENDPTCTRL1_RXR_Pos 6 /*!< USB1 ENDPTCTRL1: RXR Position */ -#define USB1_ENDPTCTRL1_RXR_Msk (0x01UL << USB1_ENDPTCTRL1_RXR_Pos) /*!< USB1 ENDPTCTRL1: RXR Mask */ -#define USB1_ENDPTCTRL1_RXE_Pos 7 /*!< USB1 ENDPTCTRL1: RXE Position */ -#define USB1_ENDPTCTRL1_RXE_Msk (0x01UL << USB1_ENDPTCTRL1_RXE_Pos) /*!< USB1 ENDPTCTRL1: RXE Mask */ -#define USB1_ENDPTCTRL1_TXS_Pos 16 /*!< USB1 ENDPTCTRL1: TXS Position */ -#define USB1_ENDPTCTRL1_TXS_Msk (0x01UL << USB1_ENDPTCTRL1_TXS_Pos) /*!< USB1 ENDPTCTRL1: TXS Mask */ -#define USB1_ENDPTCTRL1_TXT_Pos 18 /*!< USB1 ENDPTCTRL1: TXT Position */ -#define USB1_ENDPTCTRL1_TXT_Msk (0x03UL << USB1_ENDPTCTRL1_TXT_Pos) /*!< USB1 ENDPTCTRL1: TXT Mask */ -#define USB1_ENDPTCTRL1_TXI_Pos 21 /*!< USB1 ENDPTCTRL1: TXI Position */ -#define USB1_ENDPTCTRL1_TXI_Msk (0x01UL << USB1_ENDPTCTRL1_TXI_Pos) /*!< USB1 ENDPTCTRL1: TXI Mask */ -#define USB1_ENDPTCTRL1_TXR_Pos 22 /*!< USB1 ENDPTCTRL1: TXR Position */ -#define USB1_ENDPTCTRL1_TXR_Msk (0x01UL << USB1_ENDPTCTRL1_TXR_Pos) /*!< USB1 ENDPTCTRL1: TXR Mask */ -#define USB1_ENDPTCTRL1_TXE_Pos 23 /*!< USB1 ENDPTCTRL1: TXE Position */ -#define USB1_ENDPTCTRL1_TXE_Msk (0x01UL << USB1_ENDPTCTRL1_TXE_Pos) /*!< USB1 ENDPTCTRL1: TXE Mask */ - -// ------------------------------------- USB1_ENDPTCTRL2 ---------------------------------------- -#define USB1_ENDPTCTRL2_RXS_Pos 0 /*!< USB1 ENDPTCTRL2: RXS Position */ -#define USB1_ENDPTCTRL2_RXS_Msk (0x01UL << USB1_ENDPTCTRL2_RXS_Pos) /*!< USB1 ENDPTCTRL2: RXS Mask */ -#define USB1_ENDPTCTRL2_RXT_Pos 2 /*!< USB1 ENDPTCTRL2: RXT Position */ -#define USB1_ENDPTCTRL2_RXT_Msk (0x03UL << USB1_ENDPTCTRL2_RXT_Pos) /*!< USB1 ENDPTCTRL2: RXT Mask */ -#define USB1_ENDPTCTRL2_RXI_Pos 5 /*!< USB1 ENDPTCTRL2: RXI Position */ -#define USB1_ENDPTCTRL2_RXI_Msk (0x01UL << USB1_ENDPTCTRL2_RXI_Pos) /*!< USB1 ENDPTCTRL2: RXI Mask */ -#define USB1_ENDPTCTRL2_RXR_Pos 6 /*!< USB1 ENDPTCTRL2: RXR Position */ -#define USB1_ENDPTCTRL2_RXR_Msk (0x01UL << USB1_ENDPTCTRL2_RXR_Pos) /*!< USB1 ENDPTCTRL2: RXR Mask */ -#define USB1_ENDPTCTRL2_RXE_Pos 7 /*!< USB1 ENDPTCTRL2: RXE Position */ -#define USB1_ENDPTCTRL2_RXE_Msk (0x01UL << USB1_ENDPTCTRL2_RXE_Pos) /*!< USB1 ENDPTCTRL2: RXE Mask */ -#define USB1_ENDPTCTRL2_TXS_Pos 16 /*!< USB1 ENDPTCTRL2: TXS Position */ -#define USB1_ENDPTCTRL2_TXS_Msk (0x01UL << USB1_ENDPTCTRL2_TXS_Pos) /*!< USB1 ENDPTCTRL2: TXS Mask */ -#define USB1_ENDPTCTRL2_TXT_Pos 18 /*!< USB1 ENDPTCTRL2: TXT Position */ -#define USB1_ENDPTCTRL2_TXT_Msk (0x03UL << USB1_ENDPTCTRL2_TXT_Pos) /*!< USB1 ENDPTCTRL2: TXT Mask */ -#define USB1_ENDPTCTRL2_TXI_Pos 21 /*!< USB1 ENDPTCTRL2: TXI Position */ -#define USB1_ENDPTCTRL2_TXI_Msk (0x01UL << USB1_ENDPTCTRL2_TXI_Pos) /*!< USB1 ENDPTCTRL2: TXI Mask */ -#define USB1_ENDPTCTRL2_TXR_Pos 22 /*!< USB1 ENDPTCTRL2: TXR Position */ -#define USB1_ENDPTCTRL2_TXR_Msk (0x01UL << USB1_ENDPTCTRL2_TXR_Pos) /*!< USB1 ENDPTCTRL2: TXR Mask */ -#define USB1_ENDPTCTRL2_TXE_Pos 23 /*!< USB1 ENDPTCTRL2: TXE Position */ -#define USB1_ENDPTCTRL2_TXE_Msk (0x01UL << USB1_ENDPTCTRL2_TXE_Pos) /*!< USB1 ENDPTCTRL2: TXE Mask */ - -// ------------------------------------- USB1_ENDPTCTRL3 ---------------------------------------- -#define USB1_ENDPTCTRL3_RXS_Pos 0 /*!< USB1 ENDPTCTRL3: RXS Position */ -#define USB1_ENDPTCTRL3_RXS_Msk (0x01UL << USB1_ENDPTCTRL3_RXS_Pos) /*!< USB1 ENDPTCTRL3: RXS Mask */ -#define USB1_ENDPTCTRL3_RXT_Pos 2 /*!< USB1 ENDPTCTRL3: RXT Position */ -#define USB1_ENDPTCTRL3_RXT_Msk (0x03UL << USB1_ENDPTCTRL3_RXT_Pos) /*!< USB1 ENDPTCTRL3: RXT Mask */ -#define USB1_ENDPTCTRL3_RXI_Pos 5 /*!< USB1 ENDPTCTRL3: RXI Position */ -#define USB1_ENDPTCTRL3_RXI_Msk (0x01UL << USB1_ENDPTCTRL3_RXI_Pos) /*!< USB1 ENDPTCTRL3: RXI Mask */ -#define USB1_ENDPTCTRL3_RXR_Pos 6 /*!< USB1 ENDPTCTRL3: RXR Position */ -#define USB1_ENDPTCTRL3_RXR_Msk (0x01UL << USB1_ENDPTCTRL3_RXR_Pos) /*!< USB1 ENDPTCTRL3: RXR Mask */ -#define USB1_ENDPTCTRL3_RXE_Pos 7 /*!< USB1 ENDPTCTRL3: RXE Position */ -#define USB1_ENDPTCTRL3_RXE_Msk (0x01UL << USB1_ENDPTCTRL3_RXE_Pos) /*!< USB1 ENDPTCTRL3: RXE Mask */ -#define USB1_ENDPTCTRL3_TXS_Pos 16 /*!< USB1 ENDPTCTRL3: TXS Position */ -#define USB1_ENDPTCTRL3_TXS_Msk (0x01UL << USB1_ENDPTCTRL3_TXS_Pos) /*!< USB1 ENDPTCTRL3: TXS Mask */ -#define USB1_ENDPTCTRL3_TXT_Pos 18 /*!< USB1 ENDPTCTRL3: TXT Position */ -#define USB1_ENDPTCTRL3_TXT_Msk (0x03UL << USB1_ENDPTCTRL3_TXT_Pos) /*!< USB1 ENDPTCTRL3: TXT Mask */ -#define USB1_ENDPTCTRL3_TXI_Pos 21 /*!< USB1 ENDPTCTRL3: TXI Position */ -#define USB1_ENDPTCTRL3_TXI_Msk (0x01UL << USB1_ENDPTCTRL3_TXI_Pos) /*!< USB1 ENDPTCTRL3: TXI Mask */ -#define USB1_ENDPTCTRL3_TXR_Pos 22 /*!< USB1 ENDPTCTRL3: TXR Position */ -#define USB1_ENDPTCTRL3_TXR_Msk (0x01UL << USB1_ENDPTCTRL3_TXR_Pos) /*!< USB1 ENDPTCTRL3: TXR Mask */ -#define USB1_ENDPTCTRL3_TXE_Pos 23 /*!< USB1 ENDPTCTRL3: TXE Position */ -#define USB1_ENDPTCTRL3_TXE_Msk (0x01UL << USB1_ENDPTCTRL3_TXE_Pos) /*!< USB1 ENDPTCTRL3: TXE Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- LCD Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- LCD_TIMH -------------------------------------------- -#define LCD_TIMH_PPL_Pos 2 /*!< LCD TIMH: PPL Position */ -#define LCD_TIMH_PPL_Msk (0x3fUL << LCD_TIMH_PPL_Pos) /*!< LCD TIMH: PPL Mask */ -#define LCD_TIMH_HSW_Pos 8 /*!< LCD TIMH: HSW Position */ -#define LCD_TIMH_HSW_Msk (0x000000ffUL << LCD_TIMH_HSW_Pos) /*!< LCD TIMH: HSW Mask */ -#define LCD_TIMH_HFP_Pos 16 /*!< LCD TIMH: HFP Position */ -#define LCD_TIMH_HFP_Msk (0x000000ffUL << LCD_TIMH_HFP_Pos) /*!< LCD TIMH: HFP Mask */ -#define LCD_TIMH_HBP_Pos 24 /*!< LCD TIMH: HBP Position */ -#define LCD_TIMH_HBP_Msk (0x000000ffUL << LCD_TIMH_HBP_Pos) /*!< LCD TIMH: HBP Mask */ - -// ---------------------------------------- LCD_TIMV -------------------------------------------- -#define LCD_TIMV_LPP_Pos 0 /*!< LCD TIMV: LPP Position */ -#define LCD_TIMV_LPP_Msk (0x000003ffUL << LCD_TIMV_LPP_Pos) /*!< LCD TIMV: LPP Mask */ -#define LCD_TIMV_VSW_Pos 10 /*!< LCD TIMV: VSW Position */ -#define LCD_TIMV_VSW_Msk (0x3fUL << LCD_TIMV_VSW_Pos) /*!< LCD TIMV: VSW Mask */ -#define LCD_TIMV_VFP_Pos 16 /*!< LCD TIMV: VFP Position */ -#define LCD_TIMV_VFP_Msk (0x000000ffUL << LCD_TIMV_VFP_Pos) /*!< LCD TIMV: VFP Mask */ -#define LCD_TIMV_VBP_Pos 24 /*!< LCD TIMV: VBP Position */ -#define LCD_TIMV_VBP_Msk (0x000000ffUL << LCD_TIMV_VBP_Pos) /*!< LCD TIMV: VBP Mask */ - -// ----------------------------------------- LCD_POL -------------------------------------------- -#define LCD_POL_PCD_LO_Pos 0 /*!< LCD POL: PCD_LO Position */ -#define LCD_POL_PCD_LO_Msk (0x1fUL << LCD_POL_PCD_LO_Pos) /*!< LCD POL: PCD_LO Mask */ -#define LCD_POL_CLKSEL_Pos 5 /*!< LCD POL: CLKSEL Position */ -#define LCD_POL_CLKSEL_Msk (0x01UL << LCD_POL_CLKSEL_Pos) /*!< LCD POL: CLKSEL Mask */ -#define LCD_POL_ACB_Pos 6 /*!< LCD POL: ACB Position */ -#define LCD_POL_ACB_Msk (0x1fUL << LCD_POL_ACB_Pos) /*!< LCD POL: ACB Mask */ -#define LCD_POL_IVS_Pos 11 /*!< LCD POL: IVS Position */ -#define LCD_POL_IVS_Msk (0x01UL << LCD_POL_IVS_Pos) /*!< LCD POL: IVS Mask */ -#define LCD_POL_IHS_Pos 12 /*!< LCD POL: IHS Position */ -#define LCD_POL_IHS_Msk (0x01UL << LCD_POL_IHS_Pos) /*!< LCD POL: IHS Mask */ -#define LCD_POL_IPC_Pos 13 /*!< LCD POL: IPC Position */ -#define LCD_POL_IPC_Msk (0x01UL << LCD_POL_IPC_Pos) /*!< LCD POL: IPC Mask */ -#define LCD_POL_IOE_Pos 14 /*!< LCD POL: IOE Position */ -#define LCD_POL_IOE_Msk (0x01UL << LCD_POL_IOE_Pos) /*!< LCD POL: IOE Mask */ -#define LCD_POL_CPL_Pos 16 /*!< LCD POL: CPL Position */ -#define LCD_POL_CPL_Msk (0x000003ffUL << LCD_POL_CPL_Pos) /*!< LCD POL: CPL Mask */ -#define LCD_POL_BCD_Pos 26 /*!< LCD POL: BCD Position */ -#define LCD_POL_BCD_Msk (0x01UL << LCD_POL_BCD_Pos) /*!< LCD POL: BCD Mask */ -#define LCD_POL_PCD_HI_Pos 27 /*!< LCD POL: PCD_HI Position */ -#define LCD_POL_PCD_HI_Msk (0x1fUL << LCD_POL_PCD_HI_Pos) /*!< LCD POL: PCD_HI Mask */ - -// ----------------------------------------- LCD_LE --------------------------------------------- -#define LCD_LE_LED_Pos 0 /*!< LCD LE: LED Position */ -#define LCD_LE_LED_Msk (0x7fUL << LCD_LE_LED_Pos) /*!< LCD LE: LED Mask */ -#define LCD_LE_LEE_Pos 16 /*!< LCD LE: LEE Position */ -#define LCD_LE_LEE_Msk (0x01UL << LCD_LE_LEE_Pos) /*!< LCD LE: LEE Mask */ - -// --------------------------------------- LCD_UPBASE ------------------------------------------- -#define LCD_UPBASE_LCDUPBASE_Pos 3 /*!< LCD UPBASE: LCDUPBASE Position */ -#define LCD_UPBASE_LCDUPBASE_Msk (0x1fffffffUL << LCD_UPBASE_LCDUPBASE_Pos) /*!< LCD UPBASE: LCDUPBASE Mask */ - -// --------------------------------------- LCD_LPBASE ------------------------------------------- -#define LCD_LPBASE_LCDLPBASE_Pos 3 /*!< LCD LPBASE: LCDLPBASE Position */ -#define LCD_LPBASE_LCDLPBASE_Msk (0x1fffffffUL << LCD_LPBASE_LCDLPBASE_Pos) /*!< LCD LPBASE: LCDLPBASE Mask */ - -// ---------------------------------------- LCD_CTRL -------------------------------------------- -#define LCD_CTRL_LCDEN_Pos 0 /*!< LCD CTRL: LCDEN Position */ -#define LCD_CTRL_LCDEN_Msk (0x01UL << LCD_CTRL_LCDEN_Pos) /*!< LCD CTRL: LCDEN Mask */ -#define LCD_CTRL_LCDBPP_Pos 1 /*!< LCD CTRL: LCDBPP Position */ -#define LCD_CTRL_LCDBPP_Msk (0x07UL << LCD_CTRL_LCDBPP_Pos) /*!< LCD CTRL: LCDBPP Mask */ -#define LCD_CTRL_LCDBW_Pos 4 /*!< LCD CTRL: LCDBW Position */ -#define LCD_CTRL_LCDBW_Msk (0x01UL << LCD_CTRL_LCDBW_Pos) /*!< LCD CTRL: LCDBW Mask */ -#define LCD_CTRL_LCDTFT_Pos 5 /*!< LCD CTRL: LCDTFT Position */ -#define LCD_CTRL_LCDTFT_Msk (0x01UL << LCD_CTRL_LCDTFT_Pos) /*!< LCD CTRL: LCDTFT Mask */ -#define LCD_CTRL_LCDMONO8_Pos 6 /*!< LCD CTRL: LCDMONO8 Position */ -#define LCD_CTRL_LCDMONO8_Msk (0x01UL << LCD_CTRL_LCDMONO8_Pos) /*!< LCD CTRL: LCDMONO8 Mask */ -#define LCD_CTRL_LCDDUAL_Pos 7 /*!< LCD CTRL: LCDDUAL Position */ -#define LCD_CTRL_LCDDUAL_Msk (0x01UL << LCD_CTRL_LCDDUAL_Pos) /*!< LCD CTRL: LCDDUAL Mask */ -#define LCD_CTRL_BGR_Pos 8 /*!< LCD CTRL: BGR Position */ -#define LCD_CTRL_BGR_Msk (0x01UL << LCD_CTRL_BGR_Pos) /*!< LCD CTRL: BGR Mask */ -#define LCD_CTRL_BEBO_Pos 9 /*!< LCD CTRL: BEBO Position */ -#define LCD_CTRL_BEBO_Msk (0x01UL << LCD_CTRL_BEBO_Pos) /*!< LCD CTRL: BEBO Mask */ -#define LCD_CTRL_BEPO_Pos 10 /*!< LCD CTRL: BEPO Position */ -#define LCD_CTRL_BEPO_Msk (0x01UL << LCD_CTRL_BEPO_Pos) /*!< LCD CTRL: BEPO Mask */ -#define LCD_CTRL_LCDPWR_Pos 11 /*!< LCD CTRL: LCDPWR Position */ -#define LCD_CTRL_LCDPWR_Msk (0x01UL << LCD_CTRL_LCDPWR_Pos) /*!< LCD CTRL: LCDPWR Mask */ -#define LCD_CTRL_LCDVCOMP_Pos 12 /*!< LCD CTRL: LCDVCOMP Position */ -#define LCD_CTRL_LCDVCOMP_Msk (0x03UL << LCD_CTRL_LCDVCOMP_Pos) /*!< LCD CTRL: LCDVCOMP Mask */ -#define LCD_CTRL_WATERMARK_Pos 16 /*!< LCD CTRL: WATERMARK Position */ -#define LCD_CTRL_WATERMARK_Msk (0x01UL << LCD_CTRL_WATERMARK_Pos) /*!< LCD CTRL: WATERMARK Mask */ - -// --------------------------------------- LCD_INTMSK ------------------------------------------- -#define LCD_INTMSK_FUFIM_Pos 1 /*!< LCD INTMSK: FUFIM Position */ -#define LCD_INTMSK_FUFIM_Msk (0x01UL << LCD_INTMSK_FUFIM_Pos) /*!< LCD INTMSK: FUFIM Mask */ -#define LCD_INTMSK_LNBUIM_Pos 2 /*!< LCD INTMSK: LNBUIM Position */ -#define LCD_INTMSK_LNBUIM_Msk (0x01UL << LCD_INTMSK_LNBUIM_Pos) /*!< LCD INTMSK: LNBUIM Mask */ -#define LCD_INTMSK_VCOMPIM_Pos 3 /*!< LCD INTMSK: VCOMPIM Position */ -#define LCD_INTMSK_VCOMPIM_Msk (0x01UL << LCD_INTMSK_VCOMPIM_Pos) /*!< LCD INTMSK: VCOMPIM Mask */ -#define LCD_INTMSK_BERIM_Pos 4 /*!< LCD INTMSK: BERIM Position */ -#define LCD_INTMSK_BERIM_Msk (0x01UL << LCD_INTMSK_BERIM_Pos) /*!< LCD INTMSK: BERIM Mask */ - -// --------------------------------------- LCD_INTRAW ------------------------------------------- -#define LCD_INTRAW_FUFRIS_Pos 1 /*!< LCD INTRAW: FUFRIS Position */ -#define LCD_INTRAW_FUFRIS_Msk (0x01UL << LCD_INTRAW_FUFRIS_Pos) /*!< LCD INTRAW: FUFRIS Mask */ -#define LCD_INTRAW_LNBURIS_Pos 2 /*!< LCD INTRAW: LNBURIS Position */ -#define LCD_INTRAW_LNBURIS_Msk (0x01UL << LCD_INTRAW_LNBURIS_Pos) /*!< LCD INTRAW: LNBURIS Mask */ -#define LCD_INTRAW_VCOMPRIS_Pos 3 /*!< LCD INTRAW: VCOMPRIS Position */ -#define LCD_INTRAW_VCOMPRIS_Msk (0x01UL << LCD_INTRAW_VCOMPRIS_Pos) /*!< LCD INTRAW: VCOMPRIS Mask */ -#define LCD_INTRAW_BERRAW_Pos 4 /*!< LCD INTRAW: BERRAW Position */ -#define LCD_INTRAW_BERRAW_Msk (0x01UL << LCD_INTRAW_BERRAW_Pos) /*!< LCD INTRAW: BERRAW Mask */ - -// --------------------------------------- LCD_INTSTAT ------------------------------------------ -#define LCD_INTSTAT_FUFMIS_Pos 1 /*!< LCD INTSTAT: FUFMIS Position */ -#define LCD_INTSTAT_FUFMIS_Msk (0x01UL << LCD_INTSTAT_FUFMIS_Pos) /*!< LCD INTSTAT: FUFMIS Mask */ -#define LCD_INTSTAT_LNBUMIS_Pos 2 /*!< LCD INTSTAT: LNBUMIS Position */ -#define LCD_INTSTAT_LNBUMIS_Msk (0x01UL << LCD_INTSTAT_LNBUMIS_Pos) /*!< LCD INTSTAT: LNBUMIS Mask */ -#define LCD_INTSTAT_VCOMPMIS_Pos 3 /*!< LCD INTSTAT: VCOMPMIS Position */ -#define LCD_INTSTAT_VCOMPMIS_Msk (0x01UL << LCD_INTSTAT_VCOMPMIS_Pos) /*!< LCD INTSTAT: VCOMPMIS Mask */ -#define LCD_INTSTAT_BERMIS_Pos 4 /*!< LCD INTSTAT: BERMIS Position */ -#define LCD_INTSTAT_BERMIS_Msk (0x01UL << LCD_INTSTAT_BERMIS_Pos) /*!< LCD INTSTAT: BERMIS Mask */ - -// --------------------------------------- LCD_INTCLR ------------------------------------------- -#define LCD_INTCLR_FUFIC_Pos 1 /*!< LCD INTCLR: FUFIC Position */ -#define LCD_INTCLR_FUFIC_Msk (0x01UL << LCD_INTCLR_FUFIC_Pos) /*!< LCD INTCLR: FUFIC Mask */ -#define LCD_INTCLR_LNBUIC_Pos 2 /*!< LCD INTCLR: LNBUIC Position */ -#define LCD_INTCLR_LNBUIC_Msk (0x01UL << LCD_INTCLR_LNBUIC_Pos) /*!< LCD INTCLR: LNBUIC Mask */ -#define LCD_INTCLR_VCOMPIC_Pos 3 /*!< LCD INTCLR: VCOMPIC Position */ -#define LCD_INTCLR_VCOMPIC_Msk (0x01UL << LCD_INTCLR_VCOMPIC_Pos) /*!< LCD INTCLR: VCOMPIC Mask */ -#define LCD_INTCLR_BERIC_Pos 4 /*!< LCD INTCLR: BERIC Position */ -#define LCD_INTCLR_BERIC_Msk (0x01UL << LCD_INTCLR_BERIC_Pos) /*!< LCD INTCLR: BERIC Mask */ - -// --------------------------------------- LCD_UPCURR ------------------------------------------- -#define LCD_UPCURR_LCDUPCURR_Pos 0 /*!< LCD UPCURR: LCDUPCURR Position */ -#define LCD_UPCURR_LCDUPCURR_Msk (0xffffffffUL << LCD_UPCURR_LCDUPCURR_Pos) /*!< LCD UPCURR: LCDUPCURR Mask */ - -// --------------------------------------- LCD_LPCURR ------------------------------------------- -#define LCD_LPCURR_LCDLPCURR_Pos 0 /*!< LCD LPCURR: LCDLPCURR Position */ -#define LCD_LPCURR_LCDLPCURR_Msk (0xffffffffUL << LCD_LPCURR_LCDLPCURR_Pos) /*!< LCD LPCURR: LCDLPCURR Mask */ - -// ---------------------------------------- LCD_PAL0 -------------------------------------------- -#define LCD_PAL0_R04_0_Pos 0 /*!< LCD PAL0: R04_0 Position */ -#define LCD_PAL0_R04_0_Msk (0x1fUL << LCD_PAL0_R04_0_Pos) /*!< LCD PAL0: R04_0 Mask */ -#define LCD_PAL0_G04_0_Pos 5 /*!< LCD PAL0: G04_0 Position */ -#define LCD_PAL0_G04_0_Msk (0x1fUL << LCD_PAL0_G04_0_Pos) /*!< LCD PAL0: G04_0 Mask */ -#define LCD_PAL0_B04_0_Pos 10 /*!< LCD PAL0: B04_0 Position */ -#define LCD_PAL0_B04_0_Msk (0x1fUL << LCD_PAL0_B04_0_Pos) /*!< LCD PAL0: B04_0 Mask */ -#define LCD_PAL0_I0_Pos 15 /*!< LCD PAL0: I0 Position */ -#define LCD_PAL0_I0_Msk (0x01UL << LCD_PAL0_I0_Pos) /*!< LCD PAL0: I0 Mask */ -#define LCD_PAL0_R14_0_Pos 16 /*!< LCD PAL0: R14_0 Position */ -#define LCD_PAL0_R14_0_Msk (0x1fUL << LCD_PAL0_R14_0_Pos) /*!< LCD PAL0: R14_0 Mask */ -#define LCD_PAL0_G14_0_Pos 21 /*!< LCD PAL0: G14_0 Position */ -#define LCD_PAL0_G14_0_Msk (0x1fUL << LCD_PAL0_G14_0_Pos) /*!< LCD PAL0: G14_0 Mask */ -#define LCD_PAL0_B14_0_Pos 26 /*!< LCD PAL0: B14_0 Position */ -#define LCD_PAL0_B14_0_Msk (0x1fUL << LCD_PAL0_B14_0_Pos) /*!< LCD PAL0: B14_0 Mask */ -#define LCD_PAL0_I1_Pos 31 /*!< LCD PAL0: I1 Position */ -#define LCD_PAL0_I1_Msk (0x01UL << LCD_PAL0_I1_Pos) /*!< LCD PAL0: I1 Mask */ - -// ---------------------------------------- LCD_PAL1 -------------------------------------------- -#define LCD_PAL1_R04_0_Pos 0 /*!< LCD PAL1: R04_0 Position */ -#define LCD_PAL1_R04_0_Msk (0x1fUL << LCD_PAL1_R04_0_Pos) /*!< LCD PAL1: R04_0 Mask */ -#define LCD_PAL1_G04_0_Pos 5 /*!< LCD PAL1: G04_0 Position */ -#define LCD_PAL1_G04_0_Msk (0x1fUL << LCD_PAL1_G04_0_Pos) /*!< LCD PAL1: G04_0 Mask */ -#define LCD_PAL1_B04_0_Pos 10 /*!< LCD PAL1: B04_0 Position */ -#define LCD_PAL1_B04_0_Msk (0x1fUL << LCD_PAL1_B04_0_Pos) /*!< LCD PAL1: B04_0 Mask */ -#define LCD_PAL1_I0_Pos 15 /*!< LCD PAL1: I0 Position */ -#define LCD_PAL1_I0_Msk (0x01UL << LCD_PAL1_I0_Pos) /*!< LCD PAL1: I0 Mask */ -#define LCD_PAL1_R14_0_Pos 16 /*!< LCD PAL1: R14_0 Position */ -#define LCD_PAL1_R14_0_Msk (0x1fUL << LCD_PAL1_R14_0_Pos) /*!< LCD PAL1: R14_0 Mask */ -#define LCD_PAL1_G14_0_Pos 21 /*!< LCD PAL1: G14_0 Position */ -#define LCD_PAL1_G14_0_Msk (0x1fUL << LCD_PAL1_G14_0_Pos) /*!< LCD PAL1: G14_0 Mask */ -#define LCD_PAL1_B14_0_Pos 26 /*!< LCD PAL1: B14_0 Position */ -#define LCD_PAL1_B14_0_Msk (0x1fUL << LCD_PAL1_B14_0_Pos) /*!< LCD PAL1: B14_0 Mask */ -#define LCD_PAL1_I1_Pos 31 /*!< LCD PAL1: I1 Position */ -#define LCD_PAL1_I1_Msk (0x01UL << LCD_PAL1_I1_Pos) /*!< LCD PAL1: I1 Mask */ - -// ---------------------------------------- LCD_PAL2 -------------------------------------------- -#define LCD_PAL2_R04_0_Pos 0 /*!< LCD PAL2: R04_0 Position */ -#define LCD_PAL2_R04_0_Msk (0x1fUL << LCD_PAL2_R04_0_Pos) /*!< LCD PAL2: R04_0 Mask */ -#define LCD_PAL2_G04_0_Pos 5 /*!< LCD PAL2: G04_0 Position */ -#define LCD_PAL2_G04_0_Msk (0x1fUL << LCD_PAL2_G04_0_Pos) /*!< LCD PAL2: G04_0 Mask */ -#define LCD_PAL2_B04_0_Pos 10 /*!< LCD PAL2: B04_0 Position */ -#define LCD_PAL2_B04_0_Msk (0x1fUL << LCD_PAL2_B04_0_Pos) /*!< LCD PAL2: B04_0 Mask */ -#define LCD_PAL2_I0_Pos 15 /*!< LCD PAL2: I0 Position */ -#define LCD_PAL2_I0_Msk (0x01UL << LCD_PAL2_I0_Pos) /*!< LCD PAL2: I0 Mask */ -#define LCD_PAL2_R14_0_Pos 16 /*!< LCD PAL2: R14_0 Position */ -#define LCD_PAL2_R14_0_Msk (0x1fUL << LCD_PAL2_R14_0_Pos) /*!< LCD PAL2: R14_0 Mask */ -#define LCD_PAL2_G14_0_Pos 21 /*!< LCD PAL2: G14_0 Position */ -#define LCD_PAL2_G14_0_Msk (0x1fUL << LCD_PAL2_G14_0_Pos) /*!< LCD PAL2: G14_0 Mask */ -#define LCD_PAL2_B14_0_Pos 26 /*!< LCD PAL2: B14_0 Position */ -#define LCD_PAL2_B14_0_Msk (0x1fUL << LCD_PAL2_B14_0_Pos) /*!< LCD PAL2: B14_0 Mask */ -#define LCD_PAL2_I1_Pos 31 /*!< LCD PAL2: I1 Position */ -#define LCD_PAL2_I1_Msk (0x01UL << LCD_PAL2_I1_Pos) /*!< LCD PAL2: I1 Mask */ - -// ---------------------------------------- LCD_PAL3 -------------------------------------------- -#define LCD_PAL3_R04_0_Pos 0 /*!< LCD PAL3: R04_0 Position */ -#define LCD_PAL3_R04_0_Msk (0x1fUL << LCD_PAL3_R04_0_Pos) /*!< LCD PAL3: R04_0 Mask */ -#define LCD_PAL3_G04_0_Pos 5 /*!< LCD PAL3: G04_0 Position */ -#define LCD_PAL3_G04_0_Msk (0x1fUL << LCD_PAL3_G04_0_Pos) /*!< LCD PAL3: G04_0 Mask */ -#define LCD_PAL3_B04_0_Pos 10 /*!< LCD PAL3: B04_0 Position */ -#define LCD_PAL3_B04_0_Msk (0x1fUL << LCD_PAL3_B04_0_Pos) /*!< LCD PAL3: B04_0 Mask */ -#define LCD_PAL3_I0_Pos 15 /*!< LCD PAL3: I0 Position */ -#define LCD_PAL3_I0_Msk (0x01UL << LCD_PAL3_I0_Pos) /*!< LCD PAL3: I0 Mask */ -#define LCD_PAL3_R14_0_Pos 16 /*!< LCD PAL3: R14_0 Position */ -#define LCD_PAL3_R14_0_Msk (0x1fUL << LCD_PAL3_R14_0_Pos) /*!< LCD PAL3: R14_0 Mask */ -#define LCD_PAL3_G14_0_Pos 21 /*!< LCD PAL3: G14_0 Position */ -#define LCD_PAL3_G14_0_Msk (0x1fUL << LCD_PAL3_G14_0_Pos) /*!< LCD PAL3: G14_0 Mask */ -#define LCD_PAL3_B14_0_Pos 26 /*!< LCD PAL3: B14_0 Position */ -#define LCD_PAL3_B14_0_Msk (0x1fUL << LCD_PAL3_B14_0_Pos) /*!< LCD PAL3: B14_0 Mask */ -#define LCD_PAL3_I1_Pos 31 /*!< LCD PAL3: I1 Position */ -#define LCD_PAL3_I1_Msk (0x01UL << LCD_PAL3_I1_Pos) /*!< LCD PAL3: I1 Mask */ - -// ---------------------------------------- LCD_PAL4 -------------------------------------------- -#define LCD_PAL4_R04_0_Pos 0 /*!< LCD PAL4: R04_0 Position */ -#define LCD_PAL4_R04_0_Msk (0x1fUL << LCD_PAL4_R04_0_Pos) /*!< LCD PAL4: R04_0 Mask */ -#define LCD_PAL4_G04_0_Pos 5 /*!< LCD PAL4: G04_0 Position */ -#define LCD_PAL4_G04_0_Msk (0x1fUL << LCD_PAL4_G04_0_Pos) /*!< LCD PAL4: G04_0 Mask */ -#define LCD_PAL4_B04_0_Pos 10 /*!< LCD PAL4: B04_0 Position */ -#define LCD_PAL4_B04_0_Msk (0x1fUL << LCD_PAL4_B04_0_Pos) /*!< LCD PAL4: B04_0 Mask */ -#define LCD_PAL4_I0_Pos 15 /*!< LCD PAL4: I0 Position */ -#define LCD_PAL4_I0_Msk (0x01UL << LCD_PAL4_I0_Pos) /*!< LCD PAL4: I0 Mask */ -#define LCD_PAL4_R14_0_Pos 16 /*!< LCD PAL4: R14_0 Position */ -#define LCD_PAL4_R14_0_Msk (0x1fUL << LCD_PAL4_R14_0_Pos) /*!< LCD PAL4: R14_0 Mask */ -#define LCD_PAL4_G14_0_Pos 21 /*!< LCD PAL4: G14_0 Position */ -#define LCD_PAL4_G14_0_Msk (0x1fUL << LCD_PAL4_G14_0_Pos) /*!< LCD PAL4: G14_0 Mask */ -#define LCD_PAL4_B14_0_Pos 26 /*!< LCD PAL4: B14_0 Position */ -#define LCD_PAL4_B14_0_Msk (0x1fUL << LCD_PAL4_B14_0_Pos) /*!< LCD PAL4: B14_0 Mask */ -#define LCD_PAL4_I1_Pos 31 /*!< LCD PAL4: I1 Position */ -#define LCD_PAL4_I1_Msk (0x01UL << LCD_PAL4_I1_Pos) /*!< LCD PAL4: I1 Mask */ - -// ---------------------------------------- LCD_PAL5 -------------------------------------------- -#define LCD_PAL5_R04_0_Pos 0 /*!< LCD PAL5: R04_0 Position */ -#define LCD_PAL5_R04_0_Msk (0x1fUL << LCD_PAL5_R04_0_Pos) /*!< LCD PAL5: R04_0 Mask */ -#define LCD_PAL5_G04_0_Pos 5 /*!< LCD PAL5: G04_0 Position */ -#define LCD_PAL5_G04_0_Msk (0x1fUL << LCD_PAL5_G04_0_Pos) /*!< LCD PAL5: G04_0 Mask */ -#define LCD_PAL5_B04_0_Pos 10 /*!< LCD PAL5: B04_0 Position */ -#define LCD_PAL5_B04_0_Msk (0x1fUL << LCD_PAL5_B04_0_Pos) /*!< LCD PAL5: B04_0 Mask */ -#define LCD_PAL5_I0_Pos 15 /*!< LCD PAL5: I0 Position */ -#define LCD_PAL5_I0_Msk (0x01UL << LCD_PAL5_I0_Pos) /*!< LCD PAL5: I0 Mask */ -#define LCD_PAL5_R14_0_Pos 16 /*!< LCD PAL5: R14_0 Position */ -#define LCD_PAL5_R14_0_Msk (0x1fUL << LCD_PAL5_R14_0_Pos) /*!< LCD PAL5: R14_0 Mask */ -#define LCD_PAL5_G14_0_Pos 21 /*!< LCD PAL5: G14_0 Position */ -#define LCD_PAL5_G14_0_Msk (0x1fUL << LCD_PAL5_G14_0_Pos) /*!< LCD PAL5: G14_0 Mask */ -#define LCD_PAL5_B14_0_Pos 26 /*!< LCD PAL5: B14_0 Position */ -#define LCD_PAL5_B14_0_Msk (0x1fUL << LCD_PAL5_B14_0_Pos) /*!< LCD PAL5: B14_0 Mask */ -#define LCD_PAL5_I1_Pos 31 /*!< LCD PAL5: I1 Position */ -#define LCD_PAL5_I1_Msk (0x01UL << LCD_PAL5_I1_Pos) /*!< LCD PAL5: I1 Mask */ - -// ---------------------------------------- LCD_PAL6 -------------------------------------------- -#define LCD_PAL6_R04_0_Pos 0 /*!< LCD PAL6: R04_0 Position */ -#define LCD_PAL6_R04_0_Msk (0x1fUL << LCD_PAL6_R04_0_Pos) /*!< LCD PAL6: R04_0 Mask */ -#define LCD_PAL6_G04_0_Pos 5 /*!< LCD PAL6: G04_0 Position */ -#define LCD_PAL6_G04_0_Msk (0x1fUL << LCD_PAL6_G04_0_Pos) /*!< LCD PAL6: G04_0 Mask */ -#define LCD_PAL6_B04_0_Pos 10 /*!< LCD PAL6: B04_0 Position */ -#define LCD_PAL6_B04_0_Msk (0x1fUL << LCD_PAL6_B04_0_Pos) /*!< LCD PAL6: B04_0 Mask */ -#define LCD_PAL6_I0_Pos 15 /*!< LCD PAL6: I0 Position */ -#define LCD_PAL6_I0_Msk (0x01UL << LCD_PAL6_I0_Pos) /*!< LCD PAL6: I0 Mask */ -#define LCD_PAL6_R14_0_Pos 16 /*!< LCD PAL6: R14_0 Position */ -#define LCD_PAL6_R14_0_Msk (0x1fUL << LCD_PAL6_R14_0_Pos) /*!< LCD PAL6: R14_0 Mask */ -#define LCD_PAL6_G14_0_Pos 21 /*!< LCD PAL6: G14_0 Position */ -#define LCD_PAL6_G14_0_Msk (0x1fUL << LCD_PAL6_G14_0_Pos) /*!< LCD PAL6: G14_0 Mask */ -#define LCD_PAL6_B14_0_Pos 26 /*!< LCD PAL6: B14_0 Position */ -#define LCD_PAL6_B14_0_Msk (0x1fUL << LCD_PAL6_B14_0_Pos) /*!< LCD PAL6: B14_0 Mask */ -#define LCD_PAL6_I1_Pos 31 /*!< LCD PAL6: I1 Position */ -#define LCD_PAL6_I1_Msk (0x01UL << LCD_PAL6_I1_Pos) /*!< LCD PAL6: I1 Mask */ - -// ---------------------------------------- LCD_PAL7 -------------------------------------------- -#define LCD_PAL7_R04_0_Pos 0 /*!< LCD PAL7: R04_0 Position */ -#define LCD_PAL7_R04_0_Msk (0x1fUL << LCD_PAL7_R04_0_Pos) /*!< LCD PAL7: R04_0 Mask */ -#define LCD_PAL7_G04_0_Pos 5 /*!< LCD PAL7: G04_0 Position */ -#define LCD_PAL7_G04_0_Msk (0x1fUL << LCD_PAL7_G04_0_Pos) /*!< LCD PAL7: G04_0 Mask */ -#define LCD_PAL7_B04_0_Pos 10 /*!< LCD PAL7: B04_0 Position */ -#define LCD_PAL7_B04_0_Msk (0x1fUL << LCD_PAL7_B04_0_Pos) /*!< LCD PAL7: B04_0 Mask */ -#define LCD_PAL7_I0_Pos 15 /*!< LCD PAL7: I0 Position */ -#define LCD_PAL7_I0_Msk (0x01UL << LCD_PAL7_I0_Pos) /*!< LCD PAL7: I0 Mask */ -#define LCD_PAL7_R14_0_Pos 16 /*!< LCD PAL7: R14_0 Position */ -#define LCD_PAL7_R14_0_Msk (0x1fUL << LCD_PAL7_R14_0_Pos) /*!< LCD PAL7: R14_0 Mask */ -#define LCD_PAL7_G14_0_Pos 21 /*!< LCD PAL7: G14_0 Position */ -#define LCD_PAL7_G14_0_Msk (0x1fUL << LCD_PAL7_G14_0_Pos) /*!< LCD PAL7: G14_0 Mask */ -#define LCD_PAL7_B14_0_Pos 26 /*!< LCD PAL7: B14_0 Position */ -#define LCD_PAL7_B14_0_Msk (0x1fUL << LCD_PAL7_B14_0_Pos) /*!< LCD PAL7: B14_0 Mask */ -#define LCD_PAL7_I1_Pos 31 /*!< LCD PAL7: I1 Position */ -#define LCD_PAL7_I1_Msk (0x01UL << LCD_PAL7_I1_Pos) /*!< LCD PAL7: I1 Mask */ - -// ---------------------------------------- LCD_PAL8 -------------------------------------------- -#define LCD_PAL8_R04_0_Pos 0 /*!< LCD PAL8: R04_0 Position */ -#define LCD_PAL8_R04_0_Msk (0x1fUL << LCD_PAL8_R04_0_Pos) /*!< LCD PAL8: R04_0 Mask */ -#define LCD_PAL8_G04_0_Pos 5 /*!< LCD PAL8: G04_0 Position */ -#define LCD_PAL8_G04_0_Msk (0x1fUL << LCD_PAL8_G04_0_Pos) /*!< LCD PAL8: G04_0 Mask */ -#define LCD_PAL8_B04_0_Pos 10 /*!< LCD PAL8: B04_0 Position */ -#define LCD_PAL8_B04_0_Msk (0x1fUL << LCD_PAL8_B04_0_Pos) /*!< LCD PAL8: B04_0 Mask */ -#define LCD_PAL8_I0_Pos 15 /*!< LCD PAL8: I0 Position */ -#define LCD_PAL8_I0_Msk (0x01UL << LCD_PAL8_I0_Pos) /*!< LCD PAL8: I0 Mask */ -#define LCD_PAL8_R14_0_Pos 16 /*!< LCD PAL8: R14_0 Position */ -#define LCD_PAL8_R14_0_Msk (0x1fUL << LCD_PAL8_R14_0_Pos) /*!< LCD PAL8: R14_0 Mask */ -#define LCD_PAL8_G14_0_Pos 21 /*!< LCD PAL8: G14_0 Position */ -#define LCD_PAL8_G14_0_Msk (0x1fUL << LCD_PAL8_G14_0_Pos) /*!< LCD PAL8: G14_0 Mask */ -#define LCD_PAL8_B14_0_Pos 26 /*!< LCD PAL8: B14_0 Position */ -#define LCD_PAL8_B14_0_Msk (0x1fUL << LCD_PAL8_B14_0_Pos) /*!< LCD PAL8: B14_0 Mask */ -#define LCD_PAL8_I1_Pos 31 /*!< LCD PAL8: I1 Position */ -#define LCD_PAL8_I1_Msk (0x01UL << LCD_PAL8_I1_Pos) /*!< LCD PAL8: I1 Mask */ - -// ---------------------------------------- LCD_PAL9 -------------------------------------------- -#define LCD_PAL9_R04_0_Pos 0 /*!< LCD PAL9: R04_0 Position */ -#define LCD_PAL9_R04_0_Msk (0x1fUL << LCD_PAL9_R04_0_Pos) /*!< LCD PAL9: R04_0 Mask */ -#define LCD_PAL9_G04_0_Pos 5 /*!< LCD PAL9: G04_0 Position */ -#define LCD_PAL9_G04_0_Msk (0x1fUL << LCD_PAL9_G04_0_Pos) /*!< LCD PAL9: G04_0 Mask */ -#define LCD_PAL9_B04_0_Pos 10 /*!< LCD PAL9: B04_0 Position */ -#define LCD_PAL9_B04_0_Msk (0x1fUL << LCD_PAL9_B04_0_Pos) /*!< LCD PAL9: B04_0 Mask */ -#define LCD_PAL9_I0_Pos 15 /*!< LCD PAL9: I0 Position */ -#define LCD_PAL9_I0_Msk (0x01UL << LCD_PAL9_I0_Pos) /*!< LCD PAL9: I0 Mask */ -#define LCD_PAL9_R14_0_Pos 16 /*!< LCD PAL9: R14_0 Position */ -#define LCD_PAL9_R14_0_Msk (0x1fUL << LCD_PAL9_R14_0_Pos) /*!< LCD PAL9: R14_0 Mask */ -#define LCD_PAL9_G14_0_Pos 21 /*!< LCD PAL9: G14_0 Position */ -#define LCD_PAL9_G14_0_Msk (0x1fUL << LCD_PAL9_G14_0_Pos) /*!< LCD PAL9: G14_0 Mask */ -#define LCD_PAL9_B14_0_Pos 26 /*!< LCD PAL9: B14_0 Position */ -#define LCD_PAL9_B14_0_Msk (0x1fUL << LCD_PAL9_B14_0_Pos) /*!< LCD PAL9: B14_0 Mask */ -#define LCD_PAL9_I1_Pos 31 /*!< LCD PAL9: I1 Position */ -#define LCD_PAL9_I1_Msk (0x01UL << LCD_PAL9_I1_Pos) /*!< LCD PAL9: I1 Mask */ - -// ---------------------------------------- LCD_PAL10 ------------------------------------------- -#define LCD_PAL10_R04_0_Pos 0 /*!< LCD PAL10: R04_0 Position */ -#define LCD_PAL10_R04_0_Msk (0x1fUL << LCD_PAL10_R04_0_Pos) /*!< LCD PAL10: R04_0 Mask */ -#define LCD_PAL10_G04_0_Pos 5 /*!< LCD PAL10: G04_0 Position */ -#define LCD_PAL10_G04_0_Msk (0x1fUL << LCD_PAL10_G04_0_Pos) /*!< LCD PAL10: G04_0 Mask */ -#define LCD_PAL10_B04_0_Pos 10 /*!< LCD PAL10: B04_0 Position */ -#define LCD_PAL10_B04_0_Msk (0x1fUL << LCD_PAL10_B04_0_Pos) /*!< LCD PAL10: B04_0 Mask */ -#define LCD_PAL10_I0_Pos 15 /*!< LCD PAL10: I0 Position */ -#define LCD_PAL10_I0_Msk (0x01UL << LCD_PAL10_I0_Pos) /*!< LCD PAL10: I0 Mask */ -#define LCD_PAL10_R14_0_Pos 16 /*!< LCD PAL10: R14_0 Position */ -#define LCD_PAL10_R14_0_Msk (0x1fUL << LCD_PAL10_R14_0_Pos) /*!< LCD PAL10: R14_0 Mask */ -#define LCD_PAL10_G14_0_Pos 21 /*!< LCD PAL10: G14_0 Position */ -#define LCD_PAL10_G14_0_Msk (0x1fUL << LCD_PAL10_G14_0_Pos) /*!< LCD PAL10: G14_0 Mask */ -#define LCD_PAL10_B14_0_Pos 26 /*!< LCD PAL10: B14_0 Position */ -#define LCD_PAL10_B14_0_Msk (0x1fUL << LCD_PAL10_B14_0_Pos) /*!< LCD PAL10: B14_0 Mask */ -#define LCD_PAL10_I1_Pos 31 /*!< LCD PAL10: I1 Position */ -#define LCD_PAL10_I1_Msk (0x01UL << LCD_PAL10_I1_Pos) /*!< LCD PAL10: I1 Mask */ - -// ---------------------------------------- LCD_PAL11 ------------------------------------------- -#define LCD_PAL11_R04_0_Pos 0 /*!< LCD PAL11: R04_0 Position */ -#define LCD_PAL11_R04_0_Msk (0x1fUL << LCD_PAL11_R04_0_Pos) /*!< LCD PAL11: R04_0 Mask */ -#define LCD_PAL11_G04_0_Pos 5 /*!< LCD PAL11: G04_0 Position */ -#define LCD_PAL11_G04_0_Msk (0x1fUL << LCD_PAL11_G04_0_Pos) /*!< LCD PAL11: G04_0 Mask */ -#define LCD_PAL11_B04_0_Pos 10 /*!< LCD PAL11: B04_0 Position */ -#define LCD_PAL11_B04_0_Msk (0x1fUL << LCD_PAL11_B04_0_Pos) /*!< LCD PAL11: B04_0 Mask */ -#define LCD_PAL11_I0_Pos 15 /*!< LCD PAL11: I0 Position */ -#define LCD_PAL11_I0_Msk (0x01UL << LCD_PAL11_I0_Pos) /*!< LCD PAL11: I0 Mask */ -#define LCD_PAL11_R14_0_Pos 16 /*!< LCD PAL11: R14_0 Position */ -#define LCD_PAL11_R14_0_Msk (0x1fUL << LCD_PAL11_R14_0_Pos) /*!< LCD PAL11: R14_0 Mask */ -#define LCD_PAL11_G14_0_Pos 21 /*!< LCD PAL11: G14_0 Position */ -#define LCD_PAL11_G14_0_Msk (0x1fUL << LCD_PAL11_G14_0_Pos) /*!< LCD PAL11: G14_0 Mask */ -#define LCD_PAL11_B14_0_Pos 26 /*!< LCD PAL11: B14_0 Position */ -#define LCD_PAL11_B14_0_Msk (0x1fUL << LCD_PAL11_B14_0_Pos) /*!< LCD PAL11: B14_0 Mask */ -#define LCD_PAL11_I1_Pos 31 /*!< LCD PAL11: I1 Position */ -#define LCD_PAL11_I1_Msk (0x01UL << LCD_PAL11_I1_Pos) /*!< LCD PAL11: I1 Mask */ - -// ---------------------------------------- LCD_PAL12 ------------------------------------------- -#define LCD_PAL12_R04_0_Pos 0 /*!< LCD PAL12: R04_0 Position */ -#define LCD_PAL12_R04_0_Msk (0x1fUL << LCD_PAL12_R04_0_Pos) /*!< LCD PAL12: R04_0 Mask */ -#define LCD_PAL12_G04_0_Pos 5 /*!< LCD PAL12: G04_0 Position */ -#define LCD_PAL12_G04_0_Msk (0x1fUL << LCD_PAL12_G04_0_Pos) /*!< LCD PAL12: G04_0 Mask */ -#define LCD_PAL12_B04_0_Pos 10 /*!< LCD PAL12: B04_0 Position */ -#define LCD_PAL12_B04_0_Msk (0x1fUL << LCD_PAL12_B04_0_Pos) /*!< LCD PAL12: B04_0 Mask */ -#define LCD_PAL12_I0_Pos 15 /*!< LCD PAL12: I0 Position */ -#define LCD_PAL12_I0_Msk (0x01UL << LCD_PAL12_I0_Pos) /*!< LCD PAL12: I0 Mask */ -#define LCD_PAL12_R14_0_Pos 16 /*!< LCD PAL12: R14_0 Position */ -#define LCD_PAL12_R14_0_Msk (0x1fUL << LCD_PAL12_R14_0_Pos) /*!< LCD PAL12: R14_0 Mask */ -#define LCD_PAL12_G14_0_Pos 21 /*!< LCD PAL12: G14_0 Position */ -#define LCD_PAL12_G14_0_Msk (0x1fUL << LCD_PAL12_G14_0_Pos) /*!< LCD PAL12: G14_0 Mask */ -#define LCD_PAL12_B14_0_Pos 26 /*!< LCD PAL12: B14_0 Position */ -#define LCD_PAL12_B14_0_Msk (0x1fUL << LCD_PAL12_B14_0_Pos) /*!< LCD PAL12: B14_0 Mask */ -#define LCD_PAL12_I1_Pos 31 /*!< LCD PAL12: I1 Position */ -#define LCD_PAL12_I1_Msk (0x01UL << LCD_PAL12_I1_Pos) /*!< LCD PAL12: I1 Mask */ - -// ---------------------------------------- LCD_PAL13 ------------------------------------------- -#define LCD_PAL13_R04_0_Pos 0 /*!< LCD PAL13: R04_0 Position */ -#define LCD_PAL13_R04_0_Msk (0x1fUL << LCD_PAL13_R04_0_Pos) /*!< LCD PAL13: R04_0 Mask */ -#define LCD_PAL13_G04_0_Pos 5 /*!< LCD PAL13: G04_0 Position */ -#define LCD_PAL13_G04_0_Msk (0x1fUL << LCD_PAL13_G04_0_Pos) /*!< LCD PAL13: G04_0 Mask */ -#define LCD_PAL13_B04_0_Pos 10 /*!< LCD PAL13: B04_0 Position */ -#define LCD_PAL13_B04_0_Msk (0x1fUL << LCD_PAL13_B04_0_Pos) /*!< LCD PAL13: B04_0 Mask */ -#define LCD_PAL13_I0_Pos 15 /*!< LCD PAL13: I0 Position */ -#define LCD_PAL13_I0_Msk (0x01UL << LCD_PAL13_I0_Pos) /*!< LCD PAL13: I0 Mask */ -#define LCD_PAL13_R14_0_Pos 16 /*!< LCD PAL13: R14_0 Position */ -#define LCD_PAL13_R14_0_Msk (0x1fUL << LCD_PAL13_R14_0_Pos) /*!< LCD PAL13: R14_0 Mask */ -#define LCD_PAL13_G14_0_Pos 21 /*!< LCD PAL13: G14_0 Position */ -#define LCD_PAL13_G14_0_Msk (0x1fUL << LCD_PAL13_G14_0_Pos) /*!< LCD PAL13: G14_0 Mask */ -#define LCD_PAL13_B14_0_Pos 26 /*!< LCD PAL13: B14_0 Position */ -#define LCD_PAL13_B14_0_Msk (0x1fUL << LCD_PAL13_B14_0_Pos) /*!< LCD PAL13: B14_0 Mask */ -#define LCD_PAL13_I1_Pos 31 /*!< LCD PAL13: I1 Position */ -#define LCD_PAL13_I1_Msk (0x01UL << LCD_PAL13_I1_Pos) /*!< LCD PAL13: I1 Mask */ - -// ---------------------------------------- LCD_PAL14 ------------------------------------------- -#define LCD_PAL14_R04_0_Pos 0 /*!< LCD PAL14: R04_0 Position */ -#define LCD_PAL14_R04_0_Msk (0x1fUL << LCD_PAL14_R04_0_Pos) /*!< LCD PAL14: R04_0 Mask */ -#define LCD_PAL14_G04_0_Pos 5 /*!< LCD PAL14: G04_0 Position */ -#define LCD_PAL14_G04_0_Msk (0x1fUL << LCD_PAL14_G04_0_Pos) /*!< LCD PAL14: G04_0 Mask */ -#define LCD_PAL14_B04_0_Pos 10 /*!< LCD PAL14: B04_0 Position */ -#define LCD_PAL14_B04_0_Msk (0x1fUL << LCD_PAL14_B04_0_Pos) /*!< LCD PAL14: B04_0 Mask */ -#define LCD_PAL14_I0_Pos 15 /*!< LCD PAL14: I0 Position */ -#define LCD_PAL14_I0_Msk (0x01UL << LCD_PAL14_I0_Pos) /*!< LCD PAL14: I0 Mask */ -#define LCD_PAL14_R14_0_Pos 16 /*!< LCD PAL14: R14_0 Position */ -#define LCD_PAL14_R14_0_Msk (0x1fUL << LCD_PAL14_R14_0_Pos) /*!< LCD PAL14: R14_0 Mask */ -#define LCD_PAL14_G14_0_Pos 21 /*!< LCD PAL14: G14_0 Position */ -#define LCD_PAL14_G14_0_Msk (0x1fUL << LCD_PAL14_G14_0_Pos) /*!< LCD PAL14: G14_0 Mask */ -#define LCD_PAL14_B14_0_Pos 26 /*!< LCD PAL14: B14_0 Position */ -#define LCD_PAL14_B14_0_Msk (0x1fUL << LCD_PAL14_B14_0_Pos) /*!< LCD PAL14: B14_0 Mask */ -#define LCD_PAL14_I1_Pos 31 /*!< LCD PAL14: I1 Position */ -#define LCD_PAL14_I1_Msk (0x01UL << LCD_PAL14_I1_Pos) /*!< LCD PAL14: I1 Mask */ - -// ---------------------------------------- LCD_PAL15 ------------------------------------------- -#define LCD_PAL15_R04_0_Pos 0 /*!< LCD PAL15: R04_0 Position */ -#define LCD_PAL15_R04_0_Msk (0x1fUL << LCD_PAL15_R04_0_Pos) /*!< LCD PAL15: R04_0 Mask */ -#define LCD_PAL15_G04_0_Pos 5 /*!< LCD PAL15: G04_0 Position */ -#define LCD_PAL15_G04_0_Msk (0x1fUL << LCD_PAL15_G04_0_Pos) /*!< LCD PAL15: G04_0 Mask */ -#define LCD_PAL15_B04_0_Pos 10 /*!< LCD PAL15: B04_0 Position */ -#define LCD_PAL15_B04_0_Msk (0x1fUL << LCD_PAL15_B04_0_Pos) /*!< LCD PAL15: B04_0 Mask */ -#define LCD_PAL15_I0_Pos 15 /*!< LCD PAL15: I0 Position */ -#define LCD_PAL15_I0_Msk (0x01UL << LCD_PAL15_I0_Pos) /*!< LCD PAL15: I0 Mask */ -#define LCD_PAL15_R14_0_Pos 16 /*!< LCD PAL15: R14_0 Position */ -#define LCD_PAL15_R14_0_Msk (0x1fUL << LCD_PAL15_R14_0_Pos) /*!< LCD PAL15: R14_0 Mask */ -#define LCD_PAL15_G14_0_Pos 21 /*!< LCD PAL15: G14_0 Position */ -#define LCD_PAL15_G14_0_Msk (0x1fUL << LCD_PAL15_G14_0_Pos) /*!< LCD PAL15: G14_0 Mask */ -#define LCD_PAL15_B14_0_Pos 26 /*!< LCD PAL15: B14_0 Position */ -#define LCD_PAL15_B14_0_Msk (0x1fUL << LCD_PAL15_B14_0_Pos) /*!< LCD PAL15: B14_0 Mask */ -#define LCD_PAL15_I1_Pos 31 /*!< LCD PAL15: I1 Position */ -#define LCD_PAL15_I1_Msk (0x01UL << LCD_PAL15_I1_Pos) /*!< LCD PAL15: I1 Mask */ - -// ---------------------------------------- LCD_PAL16 ------------------------------------------- -#define LCD_PAL16_R04_0_Pos 0 /*!< LCD PAL16: R04_0 Position */ -#define LCD_PAL16_R04_0_Msk (0x1fUL << LCD_PAL16_R04_0_Pos) /*!< LCD PAL16: R04_0 Mask */ -#define LCD_PAL16_G04_0_Pos 5 /*!< LCD PAL16: G04_0 Position */ -#define LCD_PAL16_G04_0_Msk (0x1fUL << LCD_PAL16_G04_0_Pos) /*!< LCD PAL16: G04_0 Mask */ -#define LCD_PAL16_B04_0_Pos 10 /*!< LCD PAL16: B04_0 Position */ -#define LCD_PAL16_B04_0_Msk (0x1fUL << LCD_PAL16_B04_0_Pos) /*!< LCD PAL16: B04_0 Mask */ -#define LCD_PAL16_I0_Pos 15 /*!< LCD PAL16: I0 Position */ -#define LCD_PAL16_I0_Msk (0x01UL << LCD_PAL16_I0_Pos) /*!< LCD PAL16: I0 Mask */ -#define LCD_PAL16_R14_0_Pos 16 /*!< LCD PAL16: R14_0 Position */ -#define LCD_PAL16_R14_0_Msk (0x1fUL << LCD_PAL16_R14_0_Pos) /*!< LCD PAL16: R14_0 Mask */ -#define LCD_PAL16_G14_0_Pos 21 /*!< LCD PAL16: G14_0 Position */ -#define LCD_PAL16_G14_0_Msk (0x1fUL << LCD_PAL16_G14_0_Pos) /*!< LCD PAL16: G14_0 Mask */ -#define LCD_PAL16_B14_0_Pos 26 /*!< LCD PAL16: B14_0 Position */ -#define LCD_PAL16_B14_0_Msk (0x1fUL << LCD_PAL16_B14_0_Pos) /*!< LCD PAL16: B14_0 Mask */ -#define LCD_PAL16_I1_Pos 31 /*!< LCD PAL16: I1 Position */ -#define LCD_PAL16_I1_Msk (0x01UL << LCD_PAL16_I1_Pos) /*!< LCD PAL16: I1 Mask */ - -// ---------------------------------------- LCD_PAL17 ------------------------------------------- -#define LCD_PAL17_R04_0_Pos 0 /*!< LCD PAL17: R04_0 Position */ -#define LCD_PAL17_R04_0_Msk (0x1fUL << LCD_PAL17_R04_0_Pos) /*!< LCD PAL17: R04_0 Mask */ -#define LCD_PAL17_G04_0_Pos 5 /*!< LCD PAL17: G04_0 Position */ -#define LCD_PAL17_G04_0_Msk (0x1fUL << LCD_PAL17_G04_0_Pos) /*!< LCD PAL17: G04_0 Mask */ -#define LCD_PAL17_B04_0_Pos 10 /*!< LCD PAL17: B04_0 Position */ -#define LCD_PAL17_B04_0_Msk (0x1fUL << LCD_PAL17_B04_0_Pos) /*!< LCD PAL17: B04_0 Mask */ -#define LCD_PAL17_I0_Pos 15 /*!< LCD PAL17: I0 Position */ -#define LCD_PAL17_I0_Msk (0x01UL << LCD_PAL17_I0_Pos) /*!< LCD PAL17: I0 Mask */ -#define LCD_PAL17_R14_0_Pos 16 /*!< LCD PAL17: R14_0 Position */ -#define LCD_PAL17_R14_0_Msk (0x1fUL << LCD_PAL17_R14_0_Pos) /*!< LCD PAL17: R14_0 Mask */ -#define LCD_PAL17_G14_0_Pos 21 /*!< LCD PAL17: G14_0 Position */ -#define LCD_PAL17_G14_0_Msk (0x1fUL << LCD_PAL17_G14_0_Pos) /*!< LCD PAL17: G14_0 Mask */ -#define LCD_PAL17_B14_0_Pos 26 /*!< LCD PAL17: B14_0 Position */ -#define LCD_PAL17_B14_0_Msk (0x1fUL << LCD_PAL17_B14_0_Pos) /*!< LCD PAL17: B14_0 Mask */ -#define LCD_PAL17_I1_Pos 31 /*!< LCD PAL17: I1 Position */ -#define LCD_PAL17_I1_Msk (0x01UL << LCD_PAL17_I1_Pos) /*!< LCD PAL17: I1 Mask */ - -// ---------------------------------------- LCD_PAL18 ------------------------------------------- -#define LCD_PAL18_R04_0_Pos 0 /*!< LCD PAL18: R04_0 Position */ -#define LCD_PAL18_R04_0_Msk (0x1fUL << LCD_PAL18_R04_0_Pos) /*!< LCD PAL18: R04_0 Mask */ -#define LCD_PAL18_G04_0_Pos 5 /*!< LCD PAL18: G04_0 Position */ -#define LCD_PAL18_G04_0_Msk (0x1fUL << LCD_PAL18_G04_0_Pos) /*!< LCD PAL18: G04_0 Mask */ -#define LCD_PAL18_B04_0_Pos 10 /*!< LCD PAL18: B04_0 Position */ -#define LCD_PAL18_B04_0_Msk (0x1fUL << LCD_PAL18_B04_0_Pos) /*!< LCD PAL18: B04_0 Mask */ -#define LCD_PAL18_I0_Pos 15 /*!< LCD PAL18: I0 Position */ -#define LCD_PAL18_I0_Msk (0x01UL << LCD_PAL18_I0_Pos) /*!< LCD PAL18: I0 Mask */ -#define LCD_PAL18_R14_0_Pos 16 /*!< LCD PAL18: R14_0 Position */ -#define LCD_PAL18_R14_0_Msk (0x1fUL << LCD_PAL18_R14_0_Pos) /*!< LCD PAL18: R14_0 Mask */ -#define LCD_PAL18_G14_0_Pos 21 /*!< LCD PAL18: G14_0 Position */ -#define LCD_PAL18_G14_0_Msk (0x1fUL << LCD_PAL18_G14_0_Pos) /*!< LCD PAL18: G14_0 Mask */ -#define LCD_PAL18_B14_0_Pos 26 /*!< LCD PAL18: B14_0 Position */ -#define LCD_PAL18_B14_0_Msk (0x1fUL << LCD_PAL18_B14_0_Pos) /*!< LCD PAL18: B14_0 Mask */ -#define LCD_PAL18_I1_Pos 31 /*!< LCD PAL18: I1 Position */ -#define LCD_PAL18_I1_Msk (0x01UL << LCD_PAL18_I1_Pos) /*!< LCD PAL18: I1 Mask */ - -// ---------------------------------------- LCD_PAL19 ------------------------------------------- -#define LCD_PAL19_R04_0_Pos 0 /*!< LCD PAL19: R04_0 Position */ -#define LCD_PAL19_R04_0_Msk (0x1fUL << LCD_PAL19_R04_0_Pos) /*!< LCD PAL19: R04_0 Mask */ -#define LCD_PAL19_G04_0_Pos 5 /*!< LCD PAL19: G04_0 Position */ -#define LCD_PAL19_G04_0_Msk (0x1fUL << LCD_PAL19_G04_0_Pos) /*!< LCD PAL19: G04_0 Mask */ -#define LCD_PAL19_B04_0_Pos 10 /*!< LCD PAL19: B04_0 Position */ -#define LCD_PAL19_B04_0_Msk (0x1fUL << LCD_PAL19_B04_0_Pos) /*!< LCD PAL19: B04_0 Mask */ -#define LCD_PAL19_I0_Pos 15 /*!< LCD PAL19: I0 Position */ -#define LCD_PAL19_I0_Msk (0x01UL << LCD_PAL19_I0_Pos) /*!< LCD PAL19: I0 Mask */ -#define LCD_PAL19_R14_0_Pos 16 /*!< LCD PAL19: R14_0 Position */ -#define LCD_PAL19_R14_0_Msk (0x1fUL << LCD_PAL19_R14_0_Pos) /*!< LCD PAL19: R14_0 Mask */ -#define LCD_PAL19_G14_0_Pos 21 /*!< LCD PAL19: G14_0 Position */ -#define LCD_PAL19_G14_0_Msk (0x1fUL << LCD_PAL19_G14_0_Pos) /*!< LCD PAL19: G14_0 Mask */ -#define LCD_PAL19_B14_0_Pos 26 /*!< LCD PAL19: B14_0 Position */ -#define LCD_PAL19_B14_0_Msk (0x1fUL << LCD_PAL19_B14_0_Pos) /*!< LCD PAL19: B14_0 Mask */ -#define LCD_PAL19_I1_Pos 31 /*!< LCD PAL19: I1 Position */ -#define LCD_PAL19_I1_Msk (0x01UL << LCD_PAL19_I1_Pos) /*!< LCD PAL19: I1 Mask */ - -// ---------------------------------------- LCD_PAL20 ------------------------------------------- -#define LCD_PAL20_R04_0_Pos 0 /*!< LCD PAL20: R04_0 Position */ -#define LCD_PAL20_R04_0_Msk (0x1fUL << LCD_PAL20_R04_0_Pos) /*!< LCD PAL20: R04_0 Mask */ -#define LCD_PAL20_G04_0_Pos 5 /*!< LCD PAL20: G04_0 Position */ -#define LCD_PAL20_G04_0_Msk (0x1fUL << LCD_PAL20_G04_0_Pos) /*!< LCD PAL20: G04_0 Mask */ -#define LCD_PAL20_B04_0_Pos 10 /*!< LCD PAL20: B04_0 Position */ -#define LCD_PAL20_B04_0_Msk (0x1fUL << LCD_PAL20_B04_0_Pos) /*!< LCD PAL20: B04_0 Mask */ -#define LCD_PAL20_I0_Pos 15 /*!< LCD PAL20: I0 Position */ -#define LCD_PAL20_I0_Msk (0x01UL << LCD_PAL20_I0_Pos) /*!< LCD PAL20: I0 Mask */ -#define LCD_PAL20_R14_0_Pos 16 /*!< LCD PAL20: R14_0 Position */ -#define LCD_PAL20_R14_0_Msk (0x1fUL << LCD_PAL20_R14_0_Pos) /*!< LCD PAL20: R14_0 Mask */ -#define LCD_PAL20_G14_0_Pos 21 /*!< LCD PAL20: G14_0 Position */ -#define LCD_PAL20_G14_0_Msk (0x1fUL << LCD_PAL20_G14_0_Pos) /*!< LCD PAL20: G14_0 Mask */ -#define LCD_PAL20_B14_0_Pos 26 /*!< LCD PAL20: B14_0 Position */ -#define LCD_PAL20_B14_0_Msk (0x1fUL << LCD_PAL20_B14_0_Pos) /*!< LCD PAL20: B14_0 Mask */ -#define LCD_PAL20_I1_Pos 31 /*!< LCD PAL20: I1 Position */ -#define LCD_PAL20_I1_Msk (0x01UL << LCD_PAL20_I1_Pos) /*!< LCD PAL20: I1 Mask */ - -// ---------------------------------------- LCD_PAL21 ------------------------------------------- -#define LCD_PAL21_R04_0_Pos 0 /*!< LCD PAL21: R04_0 Position */ -#define LCD_PAL21_R04_0_Msk (0x1fUL << LCD_PAL21_R04_0_Pos) /*!< LCD PAL21: R04_0 Mask */ -#define LCD_PAL21_G04_0_Pos 5 /*!< LCD PAL21: G04_0 Position */ -#define LCD_PAL21_G04_0_Msk (0x1fUL << LCD_PAL21_G04_0_Pos) /*!< LCD PAL21: G04_0 Mask */ -#define LCD_PAL21_B04_0_Pos 10 /*!< LCD PAL21: B04_0 Position */ -#define LCD_PAL21_B04_0_Msk (0x1fUL << LCD_PAL21_B04_0_Pos) /*!< LCD PAL21: B04_0 Mask */ -#define LCD_PAL21_I0_Pos 15 /*!< LCD PAL21: I0 Position */ -#define LCD_PAL21_I0_Msk (0x01UL << LCD_PAL21_I0_Pos) /*!< LCD PAL21: I0 Mask */ -#define LCD_PAL21_R14_0_Pos 16 /*!< LCD PAL21: R14_0 Position */ -#define LCD_PAL21_R14_0_Msk (0x1fUL << LCD_PAL21_R14_0_Pos) /*!< LCD PAL21: R14_0 Mask */ -#define LCD_PAL21_G14_0_Pos 21 /*!< LCD PAL21: G14_0 Position */ -#define LCD_PAL21_G14_0_Msk (0x1fUL << LCD_PAL21_G14_0_Pos) /*!< LCD PAL21: G14_0 Mask */ -#define LCD_PAL21_B14_0_Pos 26 /*!< LCD PAL21: B14_0 Position */ -#define LCD_PAL21_B14_0_Msk (0x1fUL << LCD_PAL21_B14_0_Pos) /*!< LCD PAL21: B14_0 Mask */ -#define LCD_PAL21_I1_Pos 31 /*!< LCD PAL21: I1 Position */ -#define LCD_PAL21_I1_Msk (0x01UL << LCD_PAL21_I1_Pos) /*!< LCD PAL21: I1 Mask */ - -// ---------------------------------------- LCD_PAL22 ------------------------------------------- -#define LCD_PAL22_R04_0_Pos 0 /*!< LCD PAL22: R04_0 Position */ -#define LCD_PAL22_R04_0_Msk (0x1fUL << LCD_PAL22_R04_0_Pos) /*!< LCD PAL22: R04_0 Mask */ -#define LCD_PAL22_G04_0_Pos 5 /*!< LCD PAL22: G04_0 Position */ -#define LCD_PAL22_G04_0_Msk (0x1fUL << LCD_PAL22_G04_0_Pos) /*!< LCD PAL22: G04_0 Mask */ -#define LCD_PAL22_B04_0_Pos 10 /*!< LCD PAL22: B04_0 Position */ -#define LCD_PAL22_B04_0_Msk (0x1fUL << LCD_PAL22_B04_0_Pos) /*!< LCD PAL22: B04_0 Mask */ -#define LCD_PAL22_I0_Pos 15 /*!< LCD PAL22: I0 Position */ -#define LCD_PAL22_I0_Msk (0x01UL << LCD_PAL22_I0_Pos) /*!< LCD PAL22: I0 Mask */ -#define LCD_PAL22_R14_0_Pos 16 /*!< LCD PAL22: R14_0 Position */ -#define LCD_PAL22_R14_0_Msk (0x1fUL << LCD_PAL22_R14_0_Pos) /*!< LCD PAL22: R14_0 Mask */ -#define LCD_PAL22_G14_0_Pos 21 /*!< LCD PAL22: G14_0 Position */ -#define LCD_PAL22_G14_0_Msk (0x1fUL << LCD_PAL22_G14_0_Pos) /*!< LCD PAL22: G14_0 Mask */ -#define LCD_PAL22_B14_0_Pos 26 /*!< LCD PAL22: B14_0 Position */ -#define LCD_PAL22_B14_0_Msk (0x1fUL << LCD_PAL22_B14_0_Pos) /*!< LCD PAL22: B14_0 Mask */ -#define LCD_PAL22_I1_Pos 31 /*!< LCD PAL22: I1 Position */ -#define LCD_PAL22_I1_Msk (0x01UL << LCD_PAL22_I1_Pos) /*!< LCD PAL22: I1 Mask */ - -// ---------------------------------------- LCD_PAL23 ------------------------------------------- -#define LCD_PAL23_R04_0_Pos 0 /*!< LCD PAL23: R04_0 Position */ -#define LCD_PAL23_R04_0_Msk (0x1fUL << LCD_PAL23_R04_0_Pos) /*!< LCD PAL23: R04_0 Mask */ -#define LCD_PAL23_G04_0_Pos 5 /*!< LCD PAL23: G04_0 Position */ -#define LCD_PAL23_G04_0_Msk (0x1fUL << LCD_PAL23_G04_0_Pos) /*!< LCD PAL23: G04_0 Mask */ -#define LCD_PAL23_B04_0_Pos 10 /*!< LCD PAL23: B04_0 Position */ -#define LCD_PAL23_B04_0_Msk (0x1fUL << LCD_PAL23_B04_0_Pos) /*!< LCD PAL23: B04_0 Mask */ -#define LCD_PAL23_I0_Pos 15 /*!< LCD PAL23: I0 Position */ -#define LCD_PAL23_I0_Msk (0x01UL << LCD_PAL23_I0_Pos) /*!< LCD PAL23: I0 Mask */ -#define LCD_PAL23_R14_0_Pos 16 /*!< LCD PAL23: R14_0 Position */ -#define LCD_PAL23_R14_0_Msk (0x1fUL << LCD_PAL23_R14_0_Pos) /*!< LCD PAL23: R14_0 Mask */ -#define LCD_PAL23_G14_0_Pos 21 /*!< LCD PAL23: G14_0 Position */ -#define LCD_PAL23_G14_0_Msk (0x1fUL << LCD_PAL23_G14_0_Pos) /*!< LCD PAL23: G14_0 Mask */ -#define LCD_PAL23_B14_0_Pos 26 /*!< LCD PAL23: B14_0 Position */ -#define LCD_PAL23_B14_0_Msk (0x1fUL << LCD_PAL23_B14_0_Pos) /*!< LCD PAL23: B14_0 Mask */ -#define LCD_PAL23_I1_Pos 31 /*!< LCD PAL23: I1 Position */ -#define LCD_PAL23_I1_Msk (0x01UL << LCD_PAL23_I1_Pos) /*!< LCD PAL23: I1 Mask */ - -// ---------------------------------------- LCD_PAL24 ------------------------------------------- -#define LCD_PAL24_R04_0_Pos 0 /*!< LCD PAL24: R04_0 Position */ -#define LCD_PAL24_R04_0_Msk (0x1fUL << LCD_PAL24_R04_0_Pos) /*!< LCD PAL24: R04_0 Mask */ -#define LCD_PAL24_G04_0_Pos 5 /*!< LCD PAL24: G04_0 Position */ -#define LCD_PAL24_G04_0_Msk (0x1fUL << LCD_PAL24_G04_0_Pos) /*!< LCD PAL24: G04_0 Mask */ -#define LCD_PAL24_B04_0_Pos 10 /*!< LCD PAL24: B04_0 Position */ -#define LCD_PAL24_B04_0_Msk (0x1fUL << LCD_PAL24_B04_0_Pos) /*!< LCD PAL24: B04_0 Mask */ -#define LCD_PAL24_I0_Pos 15 /*!< LCD PAL24: I0 Position */ -#define LCD_PAL24_I0_Msk (0x01UL << LCD_PAL24_I0_Pos) /*!< LCD PAL24: I0 Mask */ -#define LCD_PAL24_R14_0_Pos 16 /*!< LCD PAL24: R14_0 Position */ -#define LCD_PAL24_R14_0_Msk (0x1fUL << LCD_PAL24_R14_0_Pos) /*!< LCD PAL24: R14_0 Mask */ -#define LCD_PAL24_G14_0_Pos 21 /*!< LCD PAL24: G14_0 Position */ -#define LCD_PAL24_G14_0_Msk (0x1fUL << LCD_PAL24_G14_0_Pos) /*!< LCD PAL24: G14_0 Mask */ -#define LCD_PAL24_B14_0_Pos 26 /*!< LCD PAL24: B14_0 Position */ -#define LCD_PAL24_B14_0_Msk (0x1fUL << LCD_PAL24_B14_0_Pos) /*!< LCD PAL24: B14_0 Mask */ -#define LCD_PAL24_I1_Pos 31 /*!< LCD PAL24: I1 Position */ -#define LCD_PAL24_I1_Msk (0x01UL << LCD_PAL24_I1_Pos) /*!< LCD PAL24: I1 Mask */ - -// ---------------------------------------- LCD_PAL25 ------------------------------------------- -#define LCD_PAL25_R04_0_Pos 0 /*!< LCD PAL25: R04_0 Position */ -#define LCD_PAL25_R04_0_Msk (0x1fUL << LCD_PAL25_R04_0_Pos) /*!< LCD PAL25: R04_0 Mask */ -#define LCD_PAL25_G04_0_Pos 5 /*!< LCD PAL25: G04_0 Position */ -#define LCD_PAL25_G04_0_Msk (0x1fUL << LCD_PAL25_G04_0_Pos) /*!< LCD PAL25: G04_0 Mask */ -#define LCD_PAL25_B04_0_Pos 10 /*!< LCD PAL25: B04_0 Position */ -#define LCD_PAL25_B04_0_Msk (0x1fUL << LCD_PAL25_B04_0_Pos) /*!< LCD PAL25: B04_0 Mask */ -#define LCD_PAL25_I0_Pos 15 /*!< LCD PAL25: I0 Position */ -#define LCD_PAL25_I0_Msk (0x01UL << LCD_PAL25_I0_Pos) /*!< LCD PAL25: I0 Mask */ -#define LCD_PAL25_R14_0_Pos 16 /*!< LCD PAL25: R14_0 Position */ -#define LCD_PAL25_R14_0_Msk (0x1fUL << LCD_PAL25_R14_0_Pos) /*!< LCD PAL25: R14_0 Mask */ -#define LCD_PAL25_G14_0_Pos 21 /*!< LCD PAL25: G14_0 Position */ -#define LCD_PAL25_G14_0_Msk (0x1fUL << LCD_PAL25_G14_0_Pos) /*!< LCD PAL25: G14_0 Mask */ -#define LCD_PAL25_B14_0_Pos 26 /*!< LCD PAL25: B14_0 Position */ -#define LCD_PAL25_B14_0_Msk (0x1fUL << LCD_PAL25_B14_0_Pos) /*!< LCD PAL25: B14_0 Mask */ -#define LCD_PAL25_I1_Pos 31 /*!< LCD PAL25: I1 Position */ -#define LCD_PAL25_I1_Msk (0x01UL << LCD_PAL25_I1_Pos) /*!< LCD PAL25: I1 Mask */ - -// ---------------------------------------- LCD_PAL26 ------------------------------------------- -#define LCD_PAL26_R04_0_Pos 0 /*!< LCD PAL26: R04_0 Position */ -#define LCD_PAL26_R04_0_Msk (0x1fUL << LCD_PAL26_R04_0_Pos) /*!< LCD PAL26: R04_0 Mask */ -#define LCD_PAL26_G04_0_Pos 5 /*!< LCD PAL26: G04_0 Position */ -#define LCD_PAL26_G04_0_Msk (0x1fUL << LCD_PAL26_G04_0_Pos) /*!< LCD PAL26: G04_0 Mask */ -#define LCD_PAL26_B04_0_Pos 10 /*!< LCD PAL26: B04_0 Position */ -#define LCD_PAL26_B04_0_Msk (0x1fUL << LCD_PAL26_B04_0_Pos) /*!< LCD PAL26: B04_0 Mask */ -#define LCD_PAL26_I0_Pos 15 /*!< LCD PAL26: I0 Position */ -#define LCD_PAL26_I0_Msk (0x01UL << LCD_PAL26_I0_Pos) /*!< LCD PAL26: I0 Mask */ -#define LCD_PAL26_R14_0_Pos 16 /*!< LCD PAL26: R14_0 Position */ -#define LCD_PAL26_R14_0_Msk (0x1fUL << LCD_PAL26_R14_0_Pos) /*!< LCD PAL26: R14_0 Mask */ -#define LCD_PAL26_G14_0_Pos 21 /*!< LCD PAL26: G14_0 Position */ -#define LCD_PAL26_G14_0_Msk (0x1fUL << LCD_PAL26_G14_0_Pos) /*!< LCD PAL26: G14_0 Mask */ -#define LCD_PAL26_B14_0_Pos 26 /*!< LCD PAL26: B14_0 Position */ -#define LCD_PAL26_B14_0_Msk (0x1fUL << LCD_PAL26_B14_0_Pos) /*!< LCD PAL26: B14_0 Mask */ -#define LCD_PAL26_I1_Pos 31 /*!< LCD PAL26: I1 Position */ -#define LCD_PAL26_I1_Msk (0x01UL << LCD_PAL26_I1_Pos) /*!< LCD PAL26: I1 Mask */ - -// ---------------------------------------- LCD_PAL27 ------------------------------------------- -#define LCD_PAL27_R04_0_Pos 0 /*!< LCD PAL27: R04_0 Position */ -#define LCD_PAL27_R04_0_Msk (0x1fUL << LCD_PAL27_R04_0_Pos) /*!< LCD PAL27: R04_0 Mask */ -#define LCD_PAL27_G04_0_Pos 5 /*!< LCD PAL27: G04_0 Position */ -#define LCD_PAL27_G04_0_Msk (0x1fUL << LCD_PAL27_G04_0_Pos) /*!< LCD PAL27: G04_0 Mask */ -#define LCD_PAL27_B04_0_Pos 10 /*!< LCD PAL27: B04_0 Position */ -#define LCD_PAL27_B04_0_Msk (0x1fUL << LCD_PAL27_B04_0_Pos) /*!< LCD PAL27: B04_0 Mask */ -#define LCD_PAL27_I0_Pos 15 /*!< LCD PAL27: I0 Position */ -#define LCD_PAL27_I0_Msk (0x01UL << LCD_PAL27_I0_Pos) /*!< LCD PAL27: I0 Mask */ -#define LCD_PAL27_R14_0_Pos 16 /*!< LCD PAL27: R14_0 Position */ -#define LCD_PAL27_R14_0_Msk (0x1fUL << LCD_PAL27_R14_0_Pos) /*!< LCD PAL27: R14_0 Mask */ -#define LCD_PAL27_G14_0_Pos 21 /*!< LCD PAL27: G14_0 Position */ -#define LCD_PAL27_G14_0_Msk (0x1fUL << LCD_PAL27_G14_0_Pos) /*!< LCD PAL27: G14_0 Mask */ -#define LCD_PAL27_B14_0_Pos 26 /*!< LCD PAL27: B14_0 Position */ -#define LCD_PAL27_B14_0_Msk (0x1fUL << LCD_PAL27_B14_0_Pos) /*!< LCD PAL27: B14_0 Mask */ -#define LCD_PAL27_I1_Pos 31 /*!< LCD PAL27: I1 Position */ -#define LCD_PAL27_I1_Msk (0x01UL << LCD_PAL27_I1_Pos) /*!< LCD PAL27: I1 Mask */ - -// ---------------------------------------- LCD_PAL28 ------------------------------------------- -#define LCD_PAL28_R04_0_Pos 0 /*!< LCD PAL28: R04_0 Position */ -#define LCD_PAL28_R04_0_Msk (0x1fUL << LCD_PAL28_R04_0_Pos) /*!< LCD PAL28: R04_0 Mask */ -#define LCD_PAL28_G04_0_Pos 5 /*!< LCD PAL28: G04_0 Position */ -#define LCD_PAL28_G04_0_Msk (0x1fUL << LCD_PAL28_G04_0_Pos) /*!< LCD PAL28: G04_0 Mask */ -#define LCD_PAL28_B04_0_Pos 10 /*!< LCD PAL28: B04_0 Position */ -#define LCD_PAL28_B04_0_Msk (0x1fUL << LCD_PAL28_B04_0_Pos) /*!< LCD PAL28: B04_0 Mask */ -#define LCD_PAL28_I0_Pos 15 /*!< LCD PAL28: I0 Position */ -#define LCD_PAL28_I0_Msk (0x01UL << LCD_PAL28_I0_Pos) /*!< LCD PAL28: I0 Mask */ -#define LCD_PAL28_R14_0_Pos 16 /*!< LCD PAL28: R14_0 Position */ -#define LCD_PAL28_R14_0_Msk (0x1fUL << LCD_PAL28_R14_0_Pos) /*!< LCD PAL28: R14_0 Mask */ -#define LCD_PAL28_G14_0_Pos 21 /*!< LCD PAL28: G14_0 Position */ -#define LCD_PAL28_G14_0_Msk (0x1fUL << LCD_PAL28_G14_0_Pos) /*!< LCD PAL28: G14_0 Mask */ -#define LCD_PAL28_B14_0_Pos 26 /*!< LCD PAL28: B14_0 Position */ -#define LCD_PAL28_B14_0_Msk (0x1fUL << LCD_PAL28_B14_0_Pos) /*!< LCD PAL28: B14_0 Mask */ -#define LCD_PAL28_I1_Pos 31 /*!< LCD PAL28: I1 Position */ -#define LCD_PAL28_I1_Msk (0x01UL << LCD_PAL28_I1_Pos) /*!< LCD PAL28: I1 Mask */ - -// ---------------------------------------- LCD_PAL29 ------------------------------------------- -#define LCD_PAL29_R04_0_Pos 0 /*!< LCD PAL29: R04_0 Position */ -#define LCD_PAL29_R04_0_Msk (0x1fUL << LCD_PAL29_R04_0_Pos) /*!< LCD PAL29: R04_0 Mask */ -#define LCD_PAL29_G04_0_Pos 5 /*!< LCD PAL29: G04_0 Position */ -#define LCD_PAL29_G04_0_Msk (0x1fUL << LCD_PAL29_G04_0_Pos) /*!< LCD PAL29: G04_0 Mask */ -#define LCD_PAL29_B04_0_Pos 10 /*!< LCD PAL29: B04_0 Position */ -#define LCD_PAL29_B04_0_Msk (0x1fUL << LCD_PAL29_B04_0_Pos) /*!< LCD PAL29: B04_0 Mask */ -#define LCD_PAL29_I0_Pos 15 /*!< LCD PAL29: I0 Position */ -#define LCD_PAL29_I0_Msk (0x01UL << LCD_PAL29_I0_Pos) /*!< LCD PAL29: I0 Mask */ -#define LCD_PAL29_R14_0_Pos 16 /*!< LCD PAL29: R14_0 Position */ -#define LCD_PAL29_R14_0_Msk (0x1fUL << LCD_PAL29_R14_0_Pos) /*!< LCD PAL29: R14_0 Mask */ -#define LCD_PAL29_G14_0_Pos 21 /*!< LCD PAL29: G14_0 Position */ -#define LCD_PAL29_G14_0_Msk (0x1fUL << LCD_PAL29_G14_0_Pos) /*!< LCD PAL29: G14_0 Mask */ -#define LCD_PAL29_B14_0_Pos 26 /*!< LCD PAL29: B14_0 Position */ -#define LCD_PAL29_B14_0_Msk (0x1fUL << LCD_PAL29_B14_0_Pos) /*!< LCD PAL29: B14_0 Mask */ -#define LCD_PAL29_I1_Pos 31 /*!< LCD PAL29: I1 Position */ -#define LCD_PAL29_I1_Msk (0x01UL << LCD_PAL29_I1_Pos) /*!< LCD PAL29: I1 Mask */ - -// ---------------------------------------- LCD_PAL30 ------------------------------------------- -#define LCD_PAL30_R04_0_Pos 0 /*!< LCD PAL30: R04_0 Position */ -#define LCD_PAL30_R04_0_Msk (0x1fUL << LCD_PAL30_R04_0_Pos) /*!< LCD PAL30: R04_0 Mask */ -#define LCD_PAL30_G04_0_Pos 5 /*!< LCD PAL30: G04_0 Position */ -#define LCD_PAL30_G04_0_Msk (0x1fUL << LCD_PAL30_G04_0_Pos) /*!< LCD PAL30: G04_0 Mask */ -#define LCD_PAL30_B04_0_Pos 10 /*!< LCD PAL30: B04_0 Position */ -#define LCD_PAL30_B04_0_Msk (0x1fUL << LCD_PAL30_B04_0_Pos) /*!< LCD PAL30: B04_0 Mask */ -#define LCD_PAL30_I0_Pos 15 /*!< LCD PAL30: I0 Position */ -#define LCD_PAL30_I0_Msk (0x01UL << LCD_PAL30_I0_Pos) /*!< LCD PAL30: I0 Mask */ -#define LCD_PAL30_R14_0_Pos 16 /*!< LCD PAL30: R14_0 Position */ -#define LCD_PAL30_R14_0_Msk (0x1fUL << LCD_PAL30_R14_0_Pos) /*!< LCD PAL30: R14_0 Mask */ -#define LCD_PAL30_G14_0_Pos 21 /*!< LCD PAL30: G14_0 Position */ -#define LCD_PAL30_G14_0_Msk (0x1fUL << LCD_PAL30_G14_0_Pos) /*!< LCD PAL30: G14_0 Mask */ -#define LCD_PAL30_B14_0_Pos 26 /*!< LCD PAL30: B14_0 Position */ -#define LCD_PAL30_B14_0_Msk (0x1fUL << LCD_PAL30_B14_0_Pos) /*!< LCD PAL30: B14_0 Mask */ -#define LCD_PAL30_I1_Pos 31 /*!< LCD PAL30: I1 Position */ -#define LCD_PAL30_I1_Msk (0x01UL << LCD_PAL30_I1_Pos) /*!< LCD PAL30: I1 Mask */ - -// ---------------------------------------- LCD_PAL31 ------------------------------------------- -#define LCD_PAL31_R04_0_Pos 0 /*!< LCD PAL31: R04_0 Position */ -#define LCD_PAL31_R04_0_Msk (0x1fUL << LCD_PAL31_R04_0_Pos) /*!< LCD PAL31: R04_0 Mask */ -#define LCD_PAL31_G04_0_Pos 5 /*!< LCD PAL31: G04_0 Position */ -#define LCD_PAL31_G04_0_Msk (0x1fUL << LCD_PAL31_G04_0_Pos) /*!< LCD PAL31: G04_0 Mask */ -#define LCD_PAL31_B04_0_Pos 10 /*!< LCD PAL31: B04_0 Position */ -#define LCD_PAL31_B04_0_Msk (0x1fUL << LCD_PAL31_B04_0_Pos) /*!< LCD PAL31: B04_0 Mask */ -#define LCD_PAL31_I0_Pos 15 /*!< LCD PAL31: I0 Position */ -#define LCD_PAL31_I0_Msk (0x01UL << LCD_PAL31_I0_Pos) /*!< LCD PAL31: I0 Mask */ -#define LCD_PAL31_R14_0_Pos 16 /*!< LCD PAL31: R14_0 Position */ -#define LCD_PAL31_R14_0_Msk (0x1fUL << LCD_PAL31_R14_0_Pos) /*!< LCD PAL31: R14_0 Mask */ -#define LCD_PAL31_G14_0_Pos 21 /*!< LCD PAL31: G14_0 Position */ -#define LCD_PAL31_G14_0_Msk (0x1fUL << LCD_PAL31_G14_0_Pos) /*!< LCD PAL31: G14_0 Mask */ -#define LCD_PAL31_B14_0_Pos 26 /*!< LCD PAL31: B14_0 Position */ -#define LCD_PAL31_B14_0_Msk (0x1fUL << LCD_PAL31_B14_0_Pos) /*!< LCD PAL31: B14_0 Mask */ -#define LCD_PAL31_I1_Pos 31 /*!< LCD PAL31: I1 Position */ -#define LCD_PAL31_I1_Msk (0x01UL << LCD_PAL31_I1_Pos) /*!< LCD PAL31: I1 Mask */ - -// ---------------------------------------- LCD_PAL32 ------------------------------------------- -#define LCD_PAL32_R04_0_Pos 0 /*!< LCD PAL32: R04_0 Position */ -#define LCD_PAL32_R04_0_Msk (0x1fUL << LCD_PAL32_R04_0_Pos) /*!< LCD PAL32: R04_0 Mask */ -#define LCD_PAL32_G04_0_Pos 5 /*!< LCD PAL32: G04_0 Position */ -#define LCD_PAL32_G04_0_Msk (0x1fUL << LCD_PAL32_G04_0_Pos) /*!< LCD PAL32: G04_0 Mask */ -#define LCD_PAL32_B04_0_Pos 10 /*!< LCD PAL32: B04_0 Position */ -#define LCD_PAL32_B04_0_Msk (0x1fUL << LCD_PAL32_B04_0_Pos) /*!< LCD PAL32: B04_0 Mask */ -#define LCD_PAL32_I0_Pos 15 /*!< LCD PAL32: I0 Position */ -#define LCD_PAL32_I0_Msk (0x01UL << LCD_PAL32_I0_Pos) /*!< LCD PAL32: I0 Mask */ -#define LCD_PAL32_R14_0_Pos 16 /*!< LCD PAL32: R14_0 Position */ -#define LCD_PAL32_R14_0_Msk (0x1fUL << LCD_PAL32_R14_0_Pos) /*!< LCD PAL32: R14_0 Mask */ -#define LCD_PAL32_G14_0_Pos 21 /*!< LCD PAL32: G14_0 Position */ -#define LCD_PAL32_G14_0_Msk (0x1fUL << LCD_PAL32_G14_0_Pos) /*!< LCD PAL32: G14_0 Mask */ -#define LCD_PAL32_B14_0_Pos 26 /*!< LCD PAL32: B14_0 Position */ -#define LCD_PAL32_B14_0_Msk (0x1fUL << LCD_PAL32_B14_0_Pos) /*!< LCD PAL32: B14_0 Mask */ -#define LCD_PAL32_I1_Pos 31 /*!< LCD PAL32: I1 Position */ -#define LCD_PAL32_I1_Msk (0x01UL << LCD_PAL32_I1_Pos) /*!< LCD PAL32: I1 Mask */ - -// ---------------------------------------- LCD_PAL33 ------------------------------------------- -#define LCD_PAL33_R04_0_Pos 0 /*!< LCD PAL33: R04_0 Position */ -#define LCD_PAL33_R04_0_Msk (0x1fUL << LCD_PAL33_R04_0_Pos) /*!< LCD PAL33: R04_0 Mask */ -#define LCD_PAL33_G04_0_Pos 5 /*!< LCD PAL33: G04_0 Position */ -#define LCD_PAL33_G04_0_Msk (0x1fUL << LCD_PAL33_G04_0_Pos) /*!< LCD PAL33: G04_0 Mask */ -#define LCD_PAL33_B04_0_Pos 10 /*!< LCD PAL33: B04_0 Position */ -#define LCD_PAL33_B04_0_Msk (0x1fUL << LCD_PAL33_B04_0_Pos) /*!< LCD PAL33: B04_0 Mask */ -#define LCD_PAL33_I0_Pos 15 /*!< LCD PAL33: I0 Position */ -#define LCD_PAL33_I0_Msk (0x01UL << LCD_PAL33_I0_Pos) /*!< LCD PAL33: I0 Mask */ -#define LCD_PAL33_R14_0_Pos 16 /*!< LCD PAL33: R14_0 Position */ -#define LCD_PAL33_R14_0_Msk (0x1fUL << LCD_PAL33_R14_0_Pos) /*!< LCD PAL33: R14_0 Mask */ -#define LCD_PAL33_G14_0_Pos 21 /*!< LCD PAL33: G14_0 Position */ -#define LCD_PAL33_G14_0_Msk (0x1fUL << LCD_PAL33_G14_0_Pos) /*!< LCD PAL33: G14_0 Mask */ -#define LCD_PAL33_B14_0_Pos 26 /*!< LCD PAL33: B14_0 Position */ -#define LCD_PAL33_B14_0_Msk (0x1fUL << LCD_PAL33_B14_0_Pos) /*!< LCD PAL33: B14_0 Mask */ -#define LCD_PAL33_I1_Pos 31 /*!< LCD PAL33: I1 Position */ -#define LCD_PAL33_I1_Msk (0x01UL << LCD_PAL33_I1_Pos) /*!< LCD PAL33: I1 Mask */ - -// ---------------------------------------- LCD_PAL34 ------------------------------------------- -#define LCD_PAL34_R04_0_Pos 0 /*!< LCD PAL34: R04_0 Position */ -#define LCD_PAL34_R04_0_Msk (0x1fUL << LCD_PAL34_R04_0_Pos) /*!< LCD PAL34: R04_0 Mask */ -#define LCD_PAL34_G04_0_Pos 5 /*!< LCD PAL34: G04_0 Position */ -#define LCD_PAL34_G04_0_Msk (0x1fUL << LCD_PAL34_G04_0_Pos) /*!< LCD PAL34: G04_0 Mask */ -#define LCD_PAL34_B04_0_Pos 10 /*!< LCD PAL34: B04_0 Position */ -#define LCD_PAL34_B04_0_Msk (0x1fUL << LCD_PAL34_B04_0_Pos) /*!< LCD PAL34: B04_0 Mask */ -#define LCD_PAL34_I0_Pos 15 /*!< LCD PAL34: I0 Position */ -#define LCD_PAL34_I0_Msk (0x01UL << LCD_PAL34_I0_Pos) /*!< LCD PAL34: I0 Mask */ -#define LCD_PAL34_R14_0_Pos 16 /*!< LCD PAL34: R14_0 Position */ -#define LCD_PAL34_R14_0_Msk (0x1fUL << LCD_PAL34_R14_0_Pos) /*!< LCD PAL34: R14_0 Mask */ -#define LCD_PAL34_G14_0_Pos 21 /*!< LCD PAL34: G14_0 Position */ -#define LCD_PAL34_G14_0_Msk (0x1fUL << LCD_PAL34_G14_0_Pos) /*!< LCD PAL34: G14_0 Mask */ -#define LCD_PAL34_B14_0_Pos 26 /*!< LCD PAL34: B14_0 Position */ -#define LCD_PAL34_B14_0_Msk (0x1fUL << LCD_PAL34_B14_0_Pos) /*!< LCD PAL34: B14_0 Mask */ -#define LCD_PAL34_I1_Pos 31 /*!< LCD PAL34: I1 Position */ -#define LCD_PAL34_I1_Msk (0x01UL << LCD_PAL34_I1_Pos) /*!< LCD PAL34: I1 Mask */ - -// ---------------------------------------- LCD_PAL35 ------------------------------------------- -#define LCD_PAL35_R04_0_Pos 0 /*!< LCD PAL35: R04_0 Position */ -#define LCD_PAL35_R04_0_Msk (0x1fUL << LCD_PAL35_R04_0_Pos) /*!< LCD PAL35: R04_0 Mask */ -#define LCD_PAL35_G04_0_Pos 5 /*!< LCD PAL35: G04_0 Position */ -#define LCD_PAL35_G04_0_Msk (0x1fUL << LCD_PAL35_G04_0_Pos) /*!< LCD PAL35: G04_0 Mask */ -#define LCD_PAL35_B04_0_Pos 10 /*!< LCD PAL35: B04_0 Position */ -#define LCD_PAL35_B04_0_Msk (0x1fUL << LCD_PAL35_B04_0_Pos) /*!< LCD PAL35: B04_0 Mask */ -#define LCD_PAL35_I0_Pos 15 /*!< LCD PAL35: I0 Position */ -#define LCD_PAL35_I0_Msk (0x01UL << LCD_PAL35_I0_Pos) /*!< LCD PAL35: I0 Mask */ -#define LCD_PAL35_R14_0_Pos 16 /*!< LCD PAL35: R14_0 Position */ -#define LCD_PAL35_R14_0_Msk (0x1fUL << LCD_PAL35_R14_0_Pos) /*!< LCD PAL35: R14_0 Mask */ -#define LCD_PAL35_G14_0_Pos 21 /*!< LCD PAL35: G14_0 Position */ -#define LCD_PAL35_G14_0_Msk (0x1fUL << LCD_PAL35_G14_0_Pos) /*!< LCD PAL35: G14_0 Mask */ -#define LCD_PAL35_B14_0_Pos 26 /*!< LCD PAL35: B14_0 Position */ -#define LCD_PAL35_B14_0_Msk (0x1fUL << LCD_PAL35_B14_0_Pos) /*!< LCD PAL35: B14_0 Mask */ -#define LCD_PAL35_I1_Pos 31 /*!< LCD PAL35: I1 Position */ -#define LCD_PAL35_I1_Msk (0x01UL << LCD_PAL35_I1_Pos) /*!< LCD PAL35: I1 Mask */ - -// ---------------------------------------- LCD_PAL36 ------------------------------------------- -#define LCD_PAL36_R04_0_Pos 0 /*!< LCD PAL36: R04_0 Position */ -#define LCD_PAL36_R04_0_Msk (0x1fUL << LCD_PAL36_R04_0_Pos) /*!< LCD PAL36: R04_0 Mask */ -#define LCD_PAL36_G04_0_Pos 5 /*!< LCD PAL36: G04_0 Position */ -#define LCD_PAL36_G04_0_Msk (0x1fUL << LCD_PAL36_G04_0_Pos) /*!< LCD PAL36: G04_0 Mask */ -#define LCD_PAL36_B04_0_Pos 10 /*!< LCD PAL36: B04_0 Position */ -#define LCD_PAL36_B04_0_Msk (0x1fUL << LCD_PAL36_B04_0_Pos) /*!< LCD PAL36: B04_0 Mask */ -#define LCD_PAL36_I0_Pos 15 /*!< LCD PAL36: I0 Position */ -#define LCD_PAL36_I0_Msk (0x01UL << LCD_PAL36_I0_Pos) /*!< LCD PAL36: I0 Mask */ -#define LCD_PAL36_R14_0_Pos 16 /*!< LCD PAL36: R14_0 Position */ -#define LCD_PAL36_R14_0_Msk (0x1fUL << LCD_PAL36_R14_0_Pos) /*!< LCD PAL36: R14_0 Mask */ -#define LCD_PAL36_G14_0_Pos 21 /*!< LCD PAL36: G14_0 Position */ -#define LCD_PAL36_G14_0_Msk (0x1fUL << LCD_PAL36_G14_0_Pos) /*!< LCD PAL36: G14_0 Mask */ -#define LCD_PAL36_B14_0_Pos 26 /*!< LCD PAL36: B14_0 Position */ -#define LCD_PAL36_B14_0_Msk (0x1fUL << LCD_PAL36_B14_0_Pos) /*!< LCD PAL36: B14_0 Mask */ -#define LCD_PAL36_I1_Pos 31 /*!< LCD PAL36: I1 Position */ -#define LCD_PAL36_I1_Msk (0x01UL << LCD_PAL36_I1_Pos) /*!< LCD PAL36: I1 Mask */ - -// ---------------------------------------- LCD_PAL37 ------------------------------------------- -#define LCD_PAL37_R04_0_Pos 0 /*!< LCD PAL37: R04_0 Position */ -#define LCD_PAL37_R04_0_Msk (0x1fUL << LCD_PAL37_R04_0_Pos) /*!< LCD PAL37: R04_0 Mask */ -#define LCD_PAL37_G04_0_Pos 5 /*!< LCD PAL37: G04_0 Position */ -#define LCD_PAL37_G04_0_Msk (0x1fUL << LCD_PAL37_G04_0_Pos) /*!< LCD PAL37: G04_0 Mask */ -#define LCD_PAL37_B04_0_Pos 10 /*!< LCD PAL37: B04_0 Position */ -#define LCD_PAL37_B04_0_Msk (0x1fUL << LCD_PAL37_B04_0_Pos) /*!< LCD PAL37: B04_0 Mask */ -#define LCD_PAL37_I0_Pos 15 /*!< LCD PAL37: I0 Position */ -#define LCD_PAL37_I0_Msk (0x01UL << LCD_PAL37_I0_Pos) /*!< LCD PAL37: I0 Mask */ -#define LCD_PAL37_R14_0_Pos 16 /*!< LCD PAL37: R14_0 Position */ -#define LCD_PAL37_R14_0_Msk (0x1fUL << LCD_PAL37_R14_0_Pos) /*!< LCD PAL37: R14_0 Mask */ -#define LCD_PAL37_G14_0_Pos 21 /*!< LCD PAL37: G14_0 Position */ -#define LCD_PAL37_G14_0_Msk (0x1fUL << LCD_PAL37_G14_0_Pos) /*!< LCD PAL37: G14_0 Mask */ -#define LCD_PAL37_B14_0_Pos 26 /*!< LCD PAL37: B14_0 Position */ -#define LCD_PAL37_B14_0_Msk (0x1fUL << LCD_PAL37_B14_0_Pos) /*!< LCD PAL37: B14_0 Mask */ -#define LCD_PAL37_I1_Pos 31 /*!< LCD PAL37: I1 Position */ -#define LCD_PAL37_I1_Msk (0x01UL << LCD_PAL37_I1_Pos) /*!< LCD PAL37: I1 Mask */ - -// ---------------------------------------- LCD_PAL38 ------------------------------------------- -#define LCD_PAL38_R04_0_Pos 0 /*!< LCD PAL38: R04_0 Position */ -#define LCD_PAL38_R04_0_Msk (0x1fUL << LCD_PAL38_R04_0_Pos) /*!< LCD PAL38: R04_0 Mask */ -#define LCD_PAL38_G04_0_Pos 5 /*!< LCD PAL38: G04_0 Position */ -#define LCD_PAL38_G04_0_Msk (0x1fUL << LCD_PAL38_G04_0_Pos) /*!< LCD PAL38: G04_0 Mask */ -#define LCD_PAL38_B04_0_Pos 10 /*!< LCD PAL38: B04_0 Position */ -#define LCD_PAL38_B04_0_Msk (0x1fUL << LCD_PAL38_B04_0_Pos) /*!< LCD PAL38: B04_0 Mask */ -#define LCD_PAL38_I0_Pos 15 /*!< LCD PAL38: I0 Position */ -#define LCD_PAL38_I0_Msk (0x01UL << LCD_PAL38_I0_Pos) /*!< LCD PAL38: I0 Mask */ -#define LCD_PAL38_R14_0_Pos 16 /*!< LCD PAL38: R14_0 Position */ -#define LCD_PAL38_R14_0_Msk (0x1fUL << LCD_PAL38_R14_0_Pos) /*!< LCD PAL38: R14_0 Mask */ -#define LCD_PAL38_G14_0_Pos 21 /*!< LCD PAL38: G14_0 Position */ -#define LCD_PAL38_G14_0_Msk (0x1fUL << LCD_PAL38_G14_0_Pos) /*!< LCD PAL38: G14_0 Mask */ -#define LCD_PAL38_B14_0_Pos 26 /*!< LCD PAL38: B14_0 Position */ -#define LCD_PAL38_B14_0_Msk (0x1fUL << LCD_PAL38_B14_0_Pos) /*!< LCD PAL38: B14_0 Mask */ -#define LCD_PAL38_I1_Pos 31 /*!< LCD PAL38: I1 Position */ -#define LCD_PAL38_I1_Msk (0x01UL << LCD_PAL38_I1_Pos) /*!< LCD PAL38: I1 Mask */ - -// ---------------------------------------- LCD_PAL39 ------------------------------------------- -#define LCD_PAL39_R04_0_Pos 0 /*!< LCD PAL39: R04_0 Position */ -#define LCD_PAL39_R04_0_Msk (0x1fUL << LCD_PAL39_R04_0_Pos) /*!< LCD PAL39: R04_0 Mask */ -#define LCD_PAL39_G04_0_Pos 5 /*!< LCD PAL39: G04_0 Position */ -#define LCD_PAL39_G04_0_Msk (0x1fUL << LCD_PAL39_G04_0_Pos) /*!< LCD PAL39: G04_0 Mask */ -#define LCD_PAL39_B04_0_Pos 10 /*!< LCD PAL39: B04_0 Position */ -#define LCD_PAL39_B04_0_Msk (0x1fUL << LCD_PAL39_B04_0_Pos) /*!< LCD PAL39: B04_0 Mask */ -#define LCD_PAL39_I0_Pos 15 /*!< LCD PAL39: I0 Position */ -#define LCD_PAL39_I0_Msk (0x01UL << LCD_PAL39_I0_Pos) /*!< LCD PAL39: I0 Mask */ -#define LCD_PAL39_R14_0_Pos 16 /*!< LCD PAL39: R14_0 Position */ -#define LCD_PAL39_R14_0_Msk (0x1fUL << LCD_PAL39_R14_0_Pos) /*!< LCD PAL39: R14_0 Mask */ -#define LCD_PAL39_G14_0_Pos 21 /*!< LCD PAL39: G14_0 Position */ -#define LCD_PAL39_G14_0_Msk (0x1fUL << LCD_PAL39_G14_0_Pos) /*!< LCD PAL39: G14_0 Mask */ -#define LCD_PAL39_B14_0_Pos 26 /*!< LCD PAL39: B14_0 Position */ -#define LCD_PAL39_B14_0_Msk (0x1fUL << LCD_PAL39_B14_0_Pos) /*!< LCD PAL39: B14_0 Mask */ -#define LCD_PAL39_I1_Pos 31 /*!< LCD PAL39: I1 Position */ -#define LCD_PAL39_I1_Msk (0x01UL << LCD_PAL39_I1_Pos) /*!< LCD PAL39: I1 Mask */ - -// ---------------------------------------- LCD_PAL40 ------------------------------------------- -#define LCD_PAL40_R04_0_Pos 0 /*!< LCD PAL40: R04_0 Position */ -#define LCD_PAL40_R04_0_Msk (0x1fUL << LCD_PAL40_R04_0_Pos) /*!< LCD PAL40: R04_0 Mask */ -#define LCD_PAL40_G04_0_Pos 5 /*!< LCD PAL40: G04_0 Position */ -#define LCD_PAL40_G04_0_Msk (0x1fUL << LCD_PAL40_G04_0_Pos) /*!< LCD PAL40: G04_0 Mask */ -#define LCD_PAL40_B04_0_Pos 10 /*!< LCD PAL40: B04_0 Position */ -#define LCD_PAL40_B04_0_Msk (0x1fUL << LCD_PAL40_B04_0_Pos) /*!< LCD PAL40: B04_0 Mask */ -#define LCD_PAL40_I0_Pos 15 /*!< LCD PAL40: I0 Position */ -#define LCD_PAL40_I0_Msk (0x01UL << LCD_PAL40_I0_Pos) /*!< LCD PAL40: I0 Mask */ -#define LCD_PAL40_R14_0_Pos 16 /*!< LCD PAL40: R14_0 Position */ -#define LCD_PAL40_R14_0_Msk (0x1fUL << LCD_PAL40_R14_0_Pos) /*!< LCD PAL40: R14_0 Mask */ -#define LCD_PAL40_G14_0_Pos 21 /*!< LCD PAL40: G14_0 Position */ -#define LCD_PAL40_G14_0_Msk (0x1fUL << LCD_PAL40_G14_0_Pos) /*!< LCD PAL40: G14_0 Mask */ -#define LCD_PAL40_B14_0_Pos 26 /*!< LCD PAL40: B14_0 Position */ -#define LCD_PAL40_B14_0_Msk (0x1fUL << LCD_PAL40_B14_0_Pos) /*!< LCD PAL40: B14_0 Mask */ -#define LCD_PAL40_I1_Pos 31 /*!< LCD PAL40: I1 Position */ -#define LCD_PAL40_I1_Msk (0x01UL << LCD_PAL40_I1_Pos) /*!< LCD PAL40: I1 Mask */ - -// ---------------------------------------- LCD_PAL41 ------------------------------------------- -#define LCD_PAL41_R04_0_Pos 0 /*!< LCD PAL41: R04_0 Position */ -#define LCD_PAL41_R04_0_Msk (0x1fUL << LCD_PAL41_R04_0_Pos) /*!< LCD PAL41: R04_0 Mask */ -#define LCD_PAL41_G04_0_Pos 5 /*!< LCD PAL41: G04_0 Position */ -#define LCD_PAL41_G04_0_Msk (0x1fUL << LCD_PAL41_G04_0_Pos) /*!< LCD PAL41: G04_0 Mask */ -#define LCD_PAL41_B04_0_Pos 10 /*!< LCD PAL41: B04_0 Position */ -#define LCD_PAL41_B04_0_Msk (0x1fUL << LCD_PAL41_B04_0_Pos) /*!< LCD PAL41: B04_0 Mask */ -#define LCD_PAL41_I0_Pos 15 /*!< LCD PAL41: I0 Position */ -#define LCD_PAL41_I0_Msk (0x01UL << LCD_PAL41_I0_Pos) /*!< LCD PAL41: I0 Mask */ -#define LCD_PAL41_R14_0_Pos 16 /*!< LCD PAL41: R14_0 Position */ -#define LCD_PAL41_R14_0_Msk (0x1fUL << LCD_PAL41_R14_0_Pos) /*!< LCD PAL41: R14_0 Mask */ -#define LCD_PAL41_G14_0_Pos 21 /*!< LCD PAL41: G14_0 Position */ -#define LCD_PAL41_G14_0_Msk (0x1fUL << LCD_PAL41_G14_0_Pos) /*!< LCD PAL41: G14_0 Mask */ -#define LCD_PAL41_B14_0_Pos 26 /*!< LCD PAL41: B14_0 Position */ -#define LCD_PAL41_B14_0_Msk (0x1fUL << LCD_PAL41_B14_0_Pos) /*!< LCD PAL41: B14_0 Mask */ -#define LCD_PAL41_I1_Pos 31 /*!< LCD PAL41: I1 Position */ -#define LCD_PAL41_I1_Msk (0x01UL << LCD_PAL41_I1_Pos) /*!< LCD PAL41: I1 Mask */ - -// ---------------------------------------- LCD_PAL42 ------------------------------------------- -#define LCD_PAL42_R04_0_Pos 0 /*!< LCD PAL42: R04_0 Position */ -#define LCD_PAL42_R04_0_Msk (0x1fUL << LCD_PAL42_R04_0_Pos) /*!< LCD PAL42: R04_0 Mask */ -#define LCD_PAL42_G04_0_Pos 5 /*!< LCD PAL42: G04_0 Position */ -#define LCD_PAL42_G04_0_Msk (0x1fUL << LCD_PAL42_G04_0_Pos) /*!< LCD PAL42: G04_0 Mask */ -#define LCD_PAL42_B04_0_Pos 10 /*!< LCD PAL42: B04_0 Position */ -#define LCD_PAL42_B04_0_Msk (0x1fUL << LCD_PAL42_B04_0_Pos) /*!< LCD PAL42: B04_0 Mask */ -#define LCD_PAL42_I0_Pos 15 /*!< LCD PAL42: I0 Position */ -#define LCD_PAL42_I0_Msk (0x01UL << LCD_PAL42_I0_Pos) /*!< LCD PAL42: I0 Mask */ -#define LCD_PAL42_R14_0_Pos 16 /*!< LCD PAL42: R14_0 Position */ -#define LCD_PAL42_R14_0_Msk (0x1fUL << LCD_PAL42_R14_0_Pos) /*!< LCD PAL42: R14_0 Mask */ -#define LCD_PAL42_G14_0_Pos 21 /*!< LCD PAL42: G14_0 Position */ -#define LCD_PAL42_G14_0_Msk (0x1fUL << LCD_PAL42_G14_0_Pos) /*!< LCD PAL42: G14_0 Mask */ -#define LCD_PAL42_B14_0_Pos 26 /*!< LCD PAL42: B14_0 Position */ -#define LCD_PAL42_B14_0_Msk (0x1fUL << LCD_PAL42_B14_0_Pos) /*!< LCD PAL42: B14_0 Mask */ -#define LCD_PAL42_I1_Pos 31 /*!< LCD PAL42: I1 Position */ -#define LCD_PAL42_I1_Msk (0x01UL << LCD_PAL42_I1_Pos) /*!< LCD PAL42: I1 Mask */ - -// ---------------------------------------- LCD_PAL43 ------------------------------------------- -#define LCD_PAL43_R04_0_Pos 0 /*!< LCD PAL43: R04_0 Position */ -#define LCD_PAL43_R04_0_Msk (0x1fUL << LCD_PAL43_R04_0_Pos) /*!< LCD PAL43: R04_0 Mask */ -#define LCD_PAL43_G04_0_Pos 5 /*!< LCD PAL43: G04_0 Position */ -#define LCD_PAL43_G04_0_Msk (0x1fUL << LCD_PAL43_G04_0_Pos) /*!< LCD PAL43: G04_0 Mask */ -#define LCD_PAL43_B04_0_Pos 10 /*!< LCD PAL43: B04_0 Position */ -#define LCD_PAL43_B04_0_Msk (0x1fUL << LCD_PAL43_B04_0_Pos) /*!< LCD PAL43: B04_0 Mask */ -#define LCD_PAL43_I0_Pos 15 /*!< LCD PAL43: I0 Position */ -#define LCD_PAL43_I0_Msk (0x01UL << LCD_PAL43_I0_Pos) /*!< LCD PAL43: I0 Mask */ -#define LCD_PAL43_R14_0_Pos 16 /*!< LCD PAL43: R14_0 Position */ -#define LCD_PAL43_R14_0_Msk (0x1fUL << LCD_PAL43_R14_0_Pos) /*!< LCD PAL43: R14_0 Mask */ -#define LCD_PAL43_G14_0_Pos 21 /*!< LCD PAL43: G14_0 Position */ -#define LCD_PAL43_G14_0_Msk (0x1fUL << LCD_PAL43_G14_0_Pos) /*!< LCD PAL43: G14_0 Mask */ -#define LCD_PAL43_B14_0_Pos 26 /*!< LCD PAL43: B14_0 Position */ -#define LCD_PAL43_B14_0_Msk (0x1fUL << LCD_PAL43_B14_0_Pos) /*!< LCD PAL43: B14_0 Mask */ -#define LCD_PAL43_I1_Pos 31 /*!< LCD PAL43: I1 Position */ -#define LCD_PAL43_I1_Msk (0x01UL << LCD_PAL43_I1_Pos) /*!< LCD PAL43: I1 Mask */ - -// ---------------------------------------- LCD_PAL44 ------------------------------------------- -#define LCD_PAL44_R04_0_Pos 0 /*!< LCD PAL44: R04_0 Position */ -#define LCD_PAL44_R04_0_Msk (0x1fUL << LCD_PAL44_R04_0_Pos) /*!< LCD PAL44: R04_0 Mask */ -#define LCD_PAL44_G04_0_Pos 5 /*!< LCD PAL44: G04_0 Position */ -#define LCD_PAL44_G04_0_Msk (0x1fUL << LCD_PAL44_G04_0_Pos) /*!< LCD PAL44: G04_0 Mask */ -#define LCD_PAL44_B04_0_Pos 10 /*!< LCD PAL44: B04_0 Position */ -#define LCD_PAL44_B04_0_Msk (0x1fUL << LCD_PAL44_B04_0_Pos) /*!< LCD PAL44: B04_0 Mask */ -#define LCD_PAL44_I0_Pos 15 /*!< LCD PAL44: I0 Position */ -#define LCD_PAL44_I0_Msk (0x01UL << LCD_PAL44_I0_Pos) /*!< LCD PAL44: I0 Mask */ -#define LCD_PAL44_R14_0_Pos 16 /*!< LCD PAL44: R14_0 Position */ -#define LCD_PAL44_R14_0_Msk (0x1fUL << LCD_PAL44_R14_0_Pos) /*!< LCD PAL44: R14_0 Mask */ -#define LCD_PAL44_G14_0_Pos 21 /*!< LCD PAL44: G14_0 Position */ -#define LCD_PAL44_G14_0_Msk (0x1fUL << LCD_PAL44_G14_0_Pos) /*!< LCD PAL44: G14_0 Mask */ -#define LCD_PAL44_B14_0_Pos 26 /*!< LCD PAL44: B14_0 Position */ -#define LCD_PAL44_B14_0_Msk (0x1fUL << LCD_PAL44_B14_0_Pos) /*!< LCD PAL44: B14_0 Mask */ -#define LCD_PAL44_I1_Pos 31 /*!< LCD PAL44: I1 Position */ -#define LCD_PAL44_I1_Msk (0x01UL << LCD_PAL44_I1_Pos) /*!< LCD PAL44: I1 Mask */ - -// ---------------------------------------- LCD_PAL45 ------------------------------------------- -#define LCD_PAL45_R04_0_Pos 0 /*!< LCD PAL45: R04_0 Position */ -#define LCD_PAL45_R04_0_Msk (0x1fUL << LCD_PAL45_R04_0_Pos) /*!< LCD PAL45: R04_0 Mask */ -#define LCD_PAL45_G04_0_Pos 5 /*!< LCD PAL45: G04_0 Position */ -#define LCD_PAL45_G04_0_Msk (0x1fUL << LCD_PAL45_G04_0_Pos) /*!< LCD PAL45: G04_0 Mask */ -#define LCD_PAL45_B04_0_Pos 10 /*!< LCD PAL45: B04_0 Position */ -#define LCD_PAL45_B04_0_Msk (0x1fUL << LCD_PAL45_B04_0_Pos) /*!< LCD PAL45: B04_0 Mask */ -#define LCD_PAL45_I0_Pos 15 /*!< LCD PAL45: I0 Position */ -#define LCD_PAL45_I0_Msk (0x01UL << LCD_PAL45_I0_Pos) /*!< LCD PAL45: I0 Mask */ -#define LCD_PAL45_R14_0_Pos 16 /*!< LCD PAL45: R14_0 Position */ -#define LCD_PAL45_R14_0_Msk (0x1fUL << LCD_PAL45_R14_0_Pos) /*!< LCD PAL45: R14_0 Mask */ -#define LCD_PAL45_G14_0_Pos 21 /*!< LCD PAL45: G14_0 Position */ -#define LCD_PAL45_G14_0_Msk (0x1fUL << LCD_PAL45_G14_0_Pos) /*!< LCD PAL45: G14_0 Mask */ -#define LCD_PAL45_B14_0_Pos 26 /*!< LCD PAL45: B14_0 Position */ -#define LCD_PAL45_B14_0_Msk (0x1fUL << LCD_PAL45_B14_0_Pos) /*!< LCD PAL45: B14_0 Mask */ -#define LCD_PAL45_I1_Pos 31 /*!< LCD PAL45: I1 Position */ -#define LCD_PAL45_I1_Msk (0x01UL << LCD_PAL45_I1_Pos) /*!< LCD PAL45: I1 Mask */ - -// ---------------------------------------- LCD_PAL46 ------------------------------------------- -#define LCD_PAL46_R04_0_Pos 0 /*!< LCD PAL46: R04_0 Position */ -#define LCD_PAL46_R04_0_Msk (0x1fUL << LCD_PAL46_R04_0_Pos) /*!< LCD PAL46: R04_0 Mask */ -#define LCD_PAL46_G04_0_Pos 5 /*!< LCD PAL46: G04_0 Position */ -#define LCD_PAL46_G04_0_Msk (0x1fUL << LCD_PAL46_G04_0_Pos) /*!< LCD PAL46: G04_0 Mask */ -#define LCD_PAL46_B04_0_Pos 10 /*!< LCD PAL46: B04_0 Position */ -#define LCD_PAL46_B04_0_Msk (0x1fUL << LCD_PAL46_B04_0_Pos) /*!< LCD PAL46: B04_0 Mask */ -#define LCD_PAL46_I0_Pos 15 /*!< LCD PAL46: I0 Position */ -#define LCD_PAL46_I0_Msk (0x01UL << LCD_PAL46_I0_Pos) /*!< LCD PAL46: I0 Mask */ -#define LCD_PAL46_R14_0_Pos 16 /*!< LCD PAL46: R14_0 Position */ -#define LCD_PAL46_R14_0_Msk (0x1fUL << LCD_PAL46_R14_0_Pos) /*!< LCD PAL46: R14_0 Mask */ -#define LCD_PAL46_G14_0_Pos 21 /*!< LCD PAL46: G14_0 Position */ -#define LCD_PAL46_G14_0_Msk (0x1fUL << LCD_PAL46_G14_0_Pos) /*!< LCD PAL46: G14_0 Mask */ -#define LCD_PAL46_B14_0_Pos 26 /*!< LCD PAL46: B14_0 Position */ -#define LCD_PAL46_B14_0_Msk (0x1fUL << LCD_PAL46_B14_0_Pos) /*!< LCD PAL46: B14_0 Mask */ -#define LCD_PAL46_I1_Pos 31 /*!< LCD PAL46: I1 Position */ -#define LCD_PAL46_I1_Msk (0x01UL << LCD_PAL46_I1_Pos) /*!< LCD PAL46: I1 Mask */ - -// ---------------------------------------- LCD_PAL47 ------------------------------------------- -#define LCD_PAL47_R04_0_Pos 0 /*!< LCD PAL47: R04_0 Position */ -#define LCD_PAL47_R04_0_Msk (0x1fUL << LCD_PAL47_R04_0_Pos) /*!< LCD PAL47: R04_0 Mask */ -#define LCD_PAL47_G04_0_Pos 5 /*!< LCD PAL47: G04_0 Position */ -#define LCD_PAL47_G04_0_Msk (0x1fUL << LCD_PAL47_G04_0_Pos) /*!< LCD PAL47: G04_0 Mask */ -#define LCD_PAL47_B04_0_Pos 10 /*!< LCD PAL47: B04_0 Position */ -#define LCD_PAL47_B04_0_Msk (0x1fUL << LCD_PAL47_B04_0_Pos) /*!< LCD PAL47: B04_0 Mask */ -#define LCD_PAL47_I0_Pos 15 /*!< LCD PAL47: I0 Position */ -#define LCD_PAL47_I0_Msk (0x01UL << LCD_PAL47_I0_Pos) /*!< LCD PAL47: I0 Mask */ -#define LCD_PAL47_R14_0_Pos 16 /*!< LCD PAL47: R14_0 Position */ -#define LCD_PAL47_R14_0_Msk (0x1fUL << LCD_PAL47_R14_0_Pos) /*!< LCD PAL47: R14_0 Mask */ -#define LCD_PAL47_G14_0_Pos 21 /*!< LCD PAL47: G14_0 Position */ -#define LCD_PAL47_G14_0_Msk (0x1fUL << LCD_PAL47_G14_0_Pos) /*!< LCD PAL47: G14_0 Mask */ -#define LCD_PAL47_B14_0_Pos 26 /*!< LCD PAL47: B14_0 Position */ -#define LCD_PAL47_B14_0_Msk (0x1fUL << LCD_PAL47_B14_0_Pos) /*!< LCD PAL47: B14_0 Mask */ -#define LCD_PAL47_I1_Pos 31 /*!< LCD PAL47: I1 Position */ -#define LCD_PAL47_I1_Msk (0x01UL << LCD_PAL47_I1_Pos) /*!< LCD PAL47: I1 Mask */ - -// ---------------------------------------- LCD_PAL48 ------------------------------------------- -#define LCD_PAL48_R04_0_Pos 0 /*!< LCD PAL48: R04_0 Position */ -#define LCD_PAL48_R04_0_Msk (0x1fUL << LCD_PAL48_R04_0_Pos) /*!< LCD PAL48: R04_0 Mask */ -#define LCD_PAL48_G04_0_Pos 5 /*!< LCD PAL48: G04_0 Position */ -#define LCD_PAL48_G04_0_Msk (0x1fUL << LCD_PAL48_G04_0_Pos) /*!< LCD PAL48: G04_0 Mask */ -#define LCD_PAL48_B04_0_Pos 10 /*!< LCD PAL48: B04_0 Position */ -#define LCD_PAL48_B04_0_Msk (0x1fUL << LCD_PAL48_B04_0_Pos) /*!< LCD PAL48: B04_0 Mask */ -#define LCD_PAL48_I0_Pos 15 /*!< LCD PAL48: I0 Position */ -#define LCD_PAL48_I0_Msk (0x01UL << LCD_PAL48_I0_Pos) /*!< LCD PAL48: I0 Mask */ -#define LCD_PAL48_R14_0_Pos 16 /*!< LCD PAL48: R14_0 Position */ -#define LCD_PAL48_R14_0_Msk (0x1fUL << LCD_PAL48_R14_0_Pos) /*!< LCD PAL48: R14_0 Mask */ -#define LCD_PAL48_G14_0_Pos 21 /*!< LCD PAL48: G14_0 Position */ -#define LCD_PAL48_G14_0_Msk (0x1fUL << LCD_PAL48_G14_0_Pos) /*!< LCD PAL48: G14_0 Mask */ -#define LCD_PAL48_B14_0_Pos 26 /*!< LCD PAL48: B14_0 Position */ -#define LCD_PAL48_B14_0_Msk (0x1fUL << LCD_PAL48_B14_0_Pos) /*!< LCD PAL48: B14_0 Mask */ -#define LCD_PAL48_I1_Pos 31 /*!< LCD PAL48: I1 Position */ -#define LCD_PAL48_I1_Msk (0x01UL << LCD_PAL48_I1_Pos) /*!< LCD PAL48: I1 Mask */ - -// ---------------------------------------- LCD_PAL49 ------------------------------------------- -#define LCD_PAL49_R04_0_Pos 0 /*!< LCD PAL49: R04_0 Position */ -#define LCD_PAL49_R04_0_Msk (0x1fUL << LCD_PAL49_R04_0_Pos) /*!< LCD PAL49: R04_0 Mask */ -#define LCD_PAL49_G04_0_Pos 5 /*!< LCD PAL49: G04_0 Position */ -#define LCD_PAL49_G04_0_Msk (0x1fUL << LCD_PAL49_G04_0_Pos) /*!< LCD PAL49: G04_0 Mask */ -#define LCD_PAL49_B04_0_Pos 10 /*!< LCD PAL49: B04_0 Position */ -#define LCD_PAL49_B04_0_Msk (0x1fUL << LCD_PAL49_B04_0_Pos) /*!< LCD PAL49: B04_0 Mask */ -#define LCD_PAL49_I0_Pos 15 /*!< LCD PAL49: I0 Position */ -#define LCD_PAL49_I0_Msk (0x01UL << LCD_PAL49_I0_Pos) /*!< LCD PAL49: I0 Mask */ -#define LCD_PAL49_R14_0_Pos 16 /*!< LCD PAL49: R14_0 Position */ -#define LCD_PAL49_R14_0_Msk (0x1fUL << LCD_PAL49_R14_0_Pos) /*!< LCD PAL49: R14_0 Mask */ -#define LCD_PAL49_G14_0_Pos 21 /*!< LCD PAL49: G14_0 Position */ -#define LCD_PAL49_G14_0_Msk (0x1fUL << LCD_PAL49_G14_0_Pos) /*!< LCD PAL49: G14_0 Mask */ -#define LCD_PAL49_B14_0_Pos 26 /*!< LCD PAL49: B14_0 Position */ -#define LCD_PAL49_B14_0_Msk (0x1fUL << LCD_PAL49_B14_0_Pos) /*!< LCD PAL49: B14_0 Mask */ -#define LCD_PAL49_I1_Pos 31 /*!< LCD PAL49: I1 Position */ -#define LCD_PAL49_I1_Msk (0x01UL << LCD_PAL49_I1_Pos) /*!< LCD PAL49: I1 Mask */ - -// ---------------------------------------- LCD_PAL50 ------------------------------------------- -#define LCD_PAL50_R04_0_Pos 0 /*!< LCD PAL50: R04_0 Position */ -#define LCD_PAL50_R04_0_Msk (0x1fUL << LCD_PAL50_R04_0_Pos) /*!< LCD PAL50: R04_0 Mask */ -#define LCD_PAL50_G04_0_Pos 5 /*!< LCD PAL50: G04_0 Position */ -#define LCD_PAL50_G04_0_Msk (0x1fUL << LCD_PAL50_G04_0_Pos) /*!< LCD PAL50: G04_0 Mask */ -#define LCD_PAL50_B04_0_Pos 10 /*!< LCD PAL50: B04_0 Position */ -#define LCD_PAL50_B04_0_Msk (0x1fUL << LCD_PAL50_B04_0_Pos) /*!< LCD PAL50: B04_0 Mask */ -#define LCD_PAL50_I0_Pos 15 /*!< LCD PAL50: I0 Position */ -#define LCD_PAL50_I0_Msk (0x01UL << LCD_PAL50_I0_Pos) /*!< LCD PAL50: I0 Mask */ -#define LCD_PAL50_R14_0_Pos 16 /*!< LCD PAL50: R14_0 Position */ -#define LCD_PAL50_R14_0_Msk (0x1fUL << LCD_PAL50_R14_0_Pos) /*!< LCD PAL50: R14_0 Mask */ -#define LCD_PAL50_G14_0_Pos 21 /*!< LCD PAL50: G14_0 Position */ -#define LCD_PAL50_G14_0_Msk (0x1fUL << LCD_PAL50_G14_0_Pos) /*!< LCD PAL50: G14_0 Mask */ -#define LCD_PAL50_B14_0_Pos 26 /*!< LCD PAL50: B14_0 Position */ -#define LCD_PAL50_B14_0_Msk (0x1fUL << LCD_PAL50_B14_0_Pos) /*!< LCD PAL50: B14_0 Mask */ -#define LCD_PAL50_I1_Pos 31 /*!< LCD PAL50: I1 Position */ -#define LCD_PAL50_I1_Msk (0x01UL << LCD_PAL50_I1_Pos) /*!< LCD PAL50: I1 Mask */ - -// ---------------------------------------- LCD_PAL51 ------------------------------------------- -#define LCD_PAL51_R04_0_Pos 0 /*!< LCD PAL51: R04_0 Position */ -#define LCD_PAL51_R04_0_Msk (0x1fUL << LCD_PAL51_R04_0_Pos) /*!< LCD PAL51: R04_0 Mask */ -#define LCD_PAL51_G04_0_Pos 5 /*!< LCD PAL51: G04_0 Position */ -#define LCD_PAL51_G04_0_Msk (0x1fUL << LCD_PAL51_G04_0_Pos) /*!< LCD PAL51: G04_0 Mask */ -#define LCD_PAL51_B04_0_Pos 10 /*!< LCD PAL51: B04_0 Position */ -#define LCD_PAL51_B04_0_Msk (0x1fUL << LCD_PAL51_B04_0_Pos) /*!< LCD PAL51: B04_0 Mask */ -#define LCD_PAL51_I0_Pos 15 /*!< LCD PAL51: I0 Position */ -#define LCD_PAL51_I0_Msk (0x01UL << LCD_PAL51_I0_Pos) /*!< LCD PAL51: I0 Mask */ -#define LCD_PAL51_R14_0_Pos 16 /*!< LCD PAL51: R14_0 Position */ -#define LCD_PAL51_R14_0_Msk (0x1fUL << LCD_PAL51_R14_0_Pos) /*!< LCD PAL51: R14_0 Mask */ -#define LCD_PAL51_G14_0_Pos 21 /*!< LCD PAL51: G14_0 Position */ -#define LCD_PAL51_G14_0_Msk (0x1fUL << LCD_PAL51_G14_0_Pos) /*!< LCD PAL51: G14_0 Mask */ -#define LCD_PAL51_B14_0_Pos 26 /*!< LCD PAL51: B14_0 Position */ -#define LCD_PAL51_B14_0_Msk (0x1fUL << LCD_PAL51_B14_0_Pos) /*!< LCD PAL51: B14_0 Mask */ -#define LCD_PAL51_I1_Pos 31 /*!< LCD PAL51: I1 Position */ -#define LCD_PAL51_I1_Msk (0x01UL << LCD_PAL51_I1_Pos) /*!< LCD PAL51: I1 Mask */ - -// ---------------------------------------- LCD_PAL52 ------------------------------------------- -#define LCD_PAL52_R04_0_Pos 0 /*!< LCD PAL52: R04_0 Position */ -#define LCD_PAL52_R04_0_Msk (0x1fUL << LCD_PAL52_R04_0_Pos) /*!< LCD PAL52: R04_0 Mask */ -#define LCD_PAL52_G04_0_Pos 5 /*!< LCD PAL52: G04_0 Position */ -#define LCD_PAL52_G04_0_Msk (0x1fUL << LCD_PAL52_G04_0_Pos) /*!< LCD PAL52: G04_0 Mask */ -#define LCD_PAL52_B04_0_Pos 10 /*!< LCD PAL52: B04_0 Position */ -#define LCD_PAL52_B04_0_Msk (0x1fUL << LCD_PAL52_B04_0_Pos) /*!< LCD PAL52: B04_0 Mask */ -#define LCD_PAL52_I0_Pos 15 /*!< LCD PAL52: I0 Position */ -#define LCD_PAL52_I0_Msk (0x01UL << LCD_PAL52_I0_Pos) /*!< LCD PAL52: I0 Mask */ -#define LCD_PAL52_R14_0_Pos 16 /*!< LCD PAL52: R14_0 Position */ -#define LCD_PAL52_R14_0_Msk (0x1fUL << LCD_PAL52_R14_0_Pos) /*!< LCD PAL52: R14_0 Mask */ -#define LCD_PAL52_G14_0_Pos 21 /*!< LCD PAL52: G14_0 Position */ -#define LCD_PAL52_G14_0_Msk (0x1fUL << LCD_PAL52_G14_0_Pos) /*!< LCD PAL52: G14_0 Mask */ -#define LCD_PAL52_B14_0_Pos 26 /*!< LCD PAL52: B14_0 Position */ -#define LCD_PAL52_B14_0_Msk (0x1fUL << LCD_PAL52_B14_0_Pos) /*!< LCD PAL52: B14_0 Mask */ -#define LCD_PAL52_I1_Pos 31 /*!< LCD PAL52: I1 Position */ -#define LCD_PAL52_I1_Msk (0x01UL << LCD_PAL52_I1_Pos) /*!< LCD PAL52: I1 Mask */ - -// ---------------------------------------- LCD_PAL53 ------------------------------------------- -#define LCD_PAL53_R04_0_Pos 0 /*!< LCD PAL53: R04_0 Position */ -#define LCD_PAL53_R04_0_Msk (0x1fUL << LCD_PAL53_R04_0_Pos) /*!< LCD PAL53: R04_0 Mask */ -#define LCD_PAL53_G04_0_Pos 5 /*!< LCD PAL53: G04_0 Position */ -#define LCD_PAL53_G04_0_Msk (0x1fUL << LCD_PAL53_G04_0_Pos) /*!< LCD PAL53: G04_0 Mask */ -#define LCD_PAL53_B04_0_Pos 10 /*!< LCD PAL53: B04_0 Position */ -#define LCD_PAL53_B04_0_Msk (0x1fUL << LCD_PAL53_B04_0_Pos) /*!< LCD PAL53: B04_0 Mask */ -#define LCD_PAL53_I0_Pos 15 /*!< LCD PAL53: I0 Position */ -#define LCD_PAL53_I0_Msk (0x01UL << LCD_PAL53_I0_Pos) /*!< LCD PAL53: I0 Mask */ -#define LCD_PAL53_R14_0_Pos 16 /*!< LCD PAL53: R14_0 Position */ -#define LCD_PAL53_R14_0_Msk (0x1fUL << LCD_PAL53_R14_0_Pos) /*!< LCD PAL53: R14_0 Mask */ -#define LCD_PAL53_G14_0_Pos 21 /*!< LCD PAL53: G14_0 Position */ -#define LCD_PAL53_G14_0_Msk (0x1fUL << LCD_PAL53_G14_0_Pos) /*!< LCD PAL53: G14_0 Mask */ -#define LCD_PAL53_B14_0_Pos 26 /*!< LCD PAL53: B14_0 Position */ -#define LCD_PAL53_B14_0_Msk (0x1fUL << LCD_PAL53_B14_0_Pos) /*!< LCD PAL53: B14_0 Mask */ -#define LCD_PAL53_I1_Pos 31 /*!< LCD PAL53: I1 Position */ -#define LCD_PAL53_I1_Msk (0x01UL << LCD_PAL53_I1_Pos) /*!< LCD PAL53: I1 Mask */ - -// ---------------------------------------- LCD_PAL54 ------------------------------------------- -#define LCD_PAL54_R04_0_Pos 0 /*!< LCD PAL54: R04_0 Position */ -#define LCD_PAL54_R04_0_Msk (0x1fUL << LCD_PAL54_R04_0_Pos) /*!< LCD PAL54: R04_0 Mask */ -#define LCD_PAL54_G04_0_Pos 5 /*!< LCD PAL54: G04_0 Position */ -#define LCD_PAL54_G04_0_Msk (0x1fUL << LCD_PAL54_G04_0_Pos) /*!< LCD PAL54: G04_0 Mask */ -#define LCD_PAL54_B04_0_Pos 10 /*!< LCD PAL54: B04_0 Position */ -#define LCD_PAL54_B04_0_Msk (0x1fUL << LCD_PAL54_B04_0_Pos) /*!< LCD PAL54: B04_0 Mask */ -#define LCD_PAL54_I0_Pos 15 /*!< LCD PAL54: I0 Position */ -#define LCD_PAL54_I0_Msk (0x01UL << LCD_PAL54_I0_Pos) /*!< LCD PAL54: I0 Mask */ -#define LCD_PAL54_R14_0_Pos 16 /*!< LCD PAL54: R14_0 Position */ -#define LCD_PAL54_R14_0_Msk (0x1fUL << LCD_PAL54_R14_0_Pos) /*!< LCD PAL54: R14_0 Mask */ -#define LCD_PAL54_G14_0_Pos 21 /*!< LCD PAL54: G14_0 Position */ -#define LCD_PAL54_G14_0_Msk (0x1fUL << LCD_PAL54_G14_0_Pos) /*!< LCD PAL54: G14_0 Mask */ -#define LCD_PAL54_B14_0_Pos 26 /*!< LCD PAL54: B14_0 Position */ -#define LCD_PAL54_B14_0_Msk (0x1fUL << LCD_PAL54_B14_0_Pos) /*!< LCD PAL54: B14_0 Mask */ -#define LCD_PAL54_I1_Pos 31 /*!< LCD PAL54: I1 Position */ -#define LCD_PAL54_I1_Msk (0x01UL << LCD_PAL54_I1_Pos) /*!< LCD PAL54: I1 Mask */ - -// ---------------------------------------- LCD_PAL55 ------------------------------------------- -#define LCD_PAL55_R04_0_Pos 0 /*!< LCD PAL55: R04_0 Position */ -#define LCD_PAL55_R04_0_Msk (0x1fUL << LCD_PAL55_R04_0_Pos) /*!< LCD PAL55: R04_0 Mask */ -#define LCD_PAL55_G04_0_Pos 5 /*!< LCD PAL55: G04_0 Position */ -#define LCD_PAL55_G04_0_Msk (0x1fUL << LCD_PAL55_G04_0_Pos) /*!< LCD PAL55: G04_0 Mask */ -#define LCD_PAL55_B04_0_Pos 10 /*!< LCD PAL55: B04_0 Position */ -#define LCD_PAL55_B04_0_Msk (0x1fUL << LCD_PAL55_B04_0_Pos) /*!< LCD PAL55: B04_0 Mask */ -#define LCD_PAL55_I0_Pos 15 /*!< LCD PAL55: I0 Position */ -#define LCD_PAL55_I0_Msk (0x01UL << LCD_PAL55_I0_Pos) /*!< LCD PAL55: I0 Mask */ -#define LCD_PAL55_R14_0_Pos 16 /*!< LCD PAL55: R14_0 Position */ -#define LCD_PAL55_R14_0_Msk (0x1fUL << LCD_PAL55_R14_0_Pos) /*!< LCD PAL55: R14_0 Mask */ -#define LCD_PAL55_G14_0_Pos 21 /*!< LCD PAL55: G14_0 Position */ -#define LCD_PAL55_G14_0_Msk (0x1fUL << LCD_PAL55_G14_0_Pos) /*!< LCD PAL55: G14_0 Mask */ -#define LCD_PAL55_B14_0_Pos 26 /*!< LCD PAL55: B14_0 Position */ -#define LCD_PAL55_B14_0_Msk (0x1fUL << LCD_PAL55_B14_0_Pos) /*!< LCD PAL55: B14_0 Mask */ -#define LCD_PAL55_I1_Pos 31 /*!< LCD PAL55: I1 Position */ -#define LCD_PAL55_I1_Msk (0x01UL << LCD_PAL55_I1_Pos) /*!< LCD PAL55: I1 Mask */ - -// ---------------------------------------- LCD_PAL56 ------------------------------------------- -#define LCD_PAL56_R04_0_Pos 0 /*!< LCD PAL56: R04_0 Position */ -#define LCD_PAL56_R04_0_Msk (0x1fUL << LCD_PAL56_R04_0_Pos) /*!< LCD PAL56: R04_0 Mask */ -#define LCD_PAL56_G04_0_Pos 5 /*!< LCD PAL56: G04_0 Position */ -#define LCD_PAL56_G04_0_Msk (0x1fUL << LCD_PAL56_G04_0_Pos) /*!< LCD PAL56: G04_0 Mask */ -#define LCD_PAL56_B04_0_Pos 10 /*!< LCD PAL56: B04_0 Position */ -#define LCD_PAL56_B04_0_Msk (0x1fUL << LCD_PAL56_B04_0_Pos) /*!< LCD PAL56: B04_0 Mask */ -#define LCD_PAL56_I0_Pos 15 /*!< LCD PAL56: I0 Position */ -#define LCD_PAL56_I0_Msk (0x01UL << LCD_PAL56_I0_Pos) /*!< LCD PAL56: I0 Mask */ -#define LCD_PAL56_R14_0_Pos 16 /*!< LCD PAL56: R14_0 Position */ -#define LCD_PAL56_R14_0_Msk (0x1fUL << LCD_PAL56_R14_0_Pos) /*!< LCD PAL56: R14_0 Mask */ -#define LCD_PAL56_G14_0_Pos 21 /*!< LCD PAL56: G14_0 Position */ -#define LCD_PAL56_G14_0_Msk (0x1fUL << LCD_PAL56_G14_0_Pos) /*!< LCD PAL56: G14_0 Mask */ -#define LCD_PAL56_B14_0_Pos 26 /*!< LCD PAL56: B14_0 Position */ -#define LCD_PAL56_B14_0_Msk (0x1fUL << LCD_PAL56_B14_0_Pos) /*!< LCD PAL56: B14_0 Mask */ -#define LCD_PAL56_I1_Pos 31 /*!< LCD PAL56: I1 Position */ -#define LCD_PAL56_I1_Msk (0x01UL << LCD_PAL56_I1_Pos) /*!< LCD PAL56: I1 Mask */ - -// ---------------------------------------- LCD_PAL57 ------------------------------------------- -#define LCD_PAL57_R04_0_Pos 0 /*!< LCD PAL57: R04_0 Position */ -#define LCD_PAL57_R04_0_Msk (0x1fUL << LCD_PAL57_R04_0_Pos) /*!< LCD PAL57: R04_0 Mask */ -#define LCD_PAL57_G04_0_Pos 5 /*!< LCD PAL57: G04_0 Position */ -#define LCD_PAL57_G04_0_Msk (0x1fUL << LCD_PAL57_G04_0_Pos) /*!< LCD PAL57: G04_0 Mask */ -#define LCD_PAL57_B04_0_Pos 10 /*!< LCD PAL57: B04_0 Position */ -#define LCD_PAL57_B04_0_Msk (0x1fUL << LCD_PAL57_B04_0_Pos) /*!< LCD PAL57: B04_0 Mask */ -#define LCD_PAL57_I0_Pos 15 /*!< LCD PAL57: I0 Position */ -#define LCD_PAL57_I0_Msk (0x01UL << LCD_PAL57_I0_Pos) /*!< LCD PAL57: I0 Mask */ -#define LCD_PAL57_R14_0_Pos 16 /*!< LCD PAL57: R14_0 Position */ -#define LCD_PAL57_R14_0_Msk (0x1fUL << LCD_PAL57_R14_0_Pos) /*!< LCD PAL57: R14_0 Mask */ -#define LCD_PAL57_G14_0_Pos 21 /*!< LCD PAL57: G14_0 Position */ -#define LCD_PAL57_G14_0_Msk (0x1fUL << LCD_PAL57_G14_0_Pos) /*!< LCD PAL57: G14_0 Mask */ -#define LCD_PAL57_B14_0_Pos 26 /*!< LCD PAL57: B14_0 Position */ -#define LCD_PAL57_B14_0_Msk (0x1fUL << LCD_PAL57_B14_0_Pos) /*!< LCD PAL57: B14_0 Mask */ -#define LCD_PAL57_I1_Pos 31 /*!< LCD PAL57: I1 Position */ -#define LCD_PAL57_I1_Msk (0x01UL << LCD_PAL57_I1_Pos) /*!< LCD PAL57: I1 Mask */ - -// ---------------------------------------- LCD_PAL58 ------------------------------------------- -#define LCD_PAL58_R04_0_Pos 0 /*!< LCD PAL58: R04_0 Position */ -#define LCD_PAL58_R04_0_Msk (0x1fUL << LCD_PAL58_R04_0_Pos) /*!< LCD PAL58: R04_0 Mask */ -#define LCD_PAL58_G04_0_Pos 5 /*!< LCD PAL58: G04_0 Position */ -#define LCD_PAL58_G04_0_Msk (0x1fUL << LCD_PAL58_G04_0_Pos) /*!< LCD PAL58: G04_0 Mask */ -#define LCD_PAL58_B04_0_Pos 10 /*!< LCD PAL58: B04_0 Position */ -#define LCD_PAL58_B04_0_Msk (0x1fUL << LCD_PAL58_B04_0_Pos) /*!< LCD PAL58: B04_0 Mask */ -#define LCD_PAL58_I0_Pos 15 /*!< LCD PAL58: I0 Position */ -#define LCD_PAL58_I0_Msk (0x01UL << LCD_PAL58_I0_Pos) /*!< LCD PAL58: I0 Mask */ -#define LCD_PAL58_R14_0_Pos 16 /*!< LCD PAL58: R14_0 Position */ -#define LCD_PAL58_R14_0_Msk (0x1fUL << LCD_PAL58_R14_0_Pos) /*!< LCD PAL58: R14_0 Mask */ -#define LCD_PAL58_G14_0_Pos 21 /*!< LCD PAL58: G14_0 Position */ -#define LCD_PAL58_G14_0_Msk (0x1fUL << LCD_PAL58_G14_0_Pos) /*!< LCD PAL58: G14_0 Mask */ -#define LCD_PAL58_B14_0_Pos 26 /*!< LCD PAL58: B14_0 Position */ -#define LCD_PAL58_B14_0_Msk (0x1fUL << LCD_PAL58_B14_0_Pos) /*!< LCD PAL58: B14_0 Mask */ -#define LCD_PAL58_I1_Pos 31 /*!< LCD PAL58: I1 Position */ -#define LCD_PAL58_I1_Msk (0x01UL << LCD_PAL58_I1_Pos) /*!< LCD PAL58: I1 Mask */ - -// ---------------------------------------- LCD_PAL59 ------------------------------------------- -#define LCD_PAL59_R04_0_Pos 0 /*!< LCD PAL59: R04_0 Position */ -#define LCD_PAL59_R04_0_Msk (0x1fUL << LCD_PAL59_R04_0_Pos) /*!< LCD PAL59: R04_0 Mask */ -#define LCD_PAL59_G04_0_Pos 5 /*!< LCD PAL59: G04_0 Position */ -#define LCD_PAL59_G04_0_Msk (0x1fUL << LCD_PAL59_G04_0_Pos) /*!< LCD PAL59: G04_0 Mask */ -#define LCD_PAL59_B04_0_Pos 10 /*!< LCD PAL59: B04_0 Position */ -#define LCD_PAL59_B04_0_Msk (0x1fUL << LCD_PAL59_B04_0_Pos) /*!< LCD PAL59: B04_0 Mask */ -#define LCD_PAL59_I0_Pos 15 /*!< LCD PAL59: I0 Position */ -#define LCD_PAL59_I0_Msk (0x01UL << LCD_PAL59_I0_Pos) /*!< LCD PAL59: I0 Mask */ -#define LCD_PAL59_R14_0_Pos 16 /*!< LCD PAL59: R14_0 Position */ -#define LCD_PAL59_R14_0_Msk (0x1fUL << LCD_PAL59_R14_0_Pos) /*!< LCD PAL59: R14_0 Mask */ -#define LCD_PAL59_G14_0_Pos 21 /*!< LCD PAL59: G14_0 Position */ -#define LCD_PAL59_G14_0_Msk (0x1fUL << LCD_PAL59_G14_0_Pos) /*!< LCD PAL59: G14_0 Mask */ -#define LCD_PAL59_B14_0_Pos 26 /*!< LCD PAL59: B14_0 Position */ -#define LCD_PAL59_B14_0_Msk (0x1fUL << LCD_PAL59_B14_0_Pos) /*!< LCD PAL59: B14_0 Mask */ -#define LCD_PAL59_I1_Pos 31 /*!< LCD PAL59: I1 Position */ -#define LCD_PAL59_I1_Msk (0x01UL << LCD_PAL59_I1_Pos) /*!< LCD PAL59: I1 Mask */ - -// ---------------------------------------- LCD_PAL60 ------------------------------------------- -#define LCD_PAL60_R04_0_Pos 0 /*!< LCD PAL60: R04_0 Position */ -#define LCD_PAL60_R04_0_Msk (0x1fUL << LCD_PAL60_R04_0_Pos) /*!< LCD PAL60: R04_0 Mask */ -#define LCD_PAL60_G04_0_Pos 5 /*!< LCD PAL60: G04_0 Position */ -#define LCD_PAL60_G04_0_Msk (0x1fUL << LCD_PAL60_G04_0_Pos) /*!< LCD PAL60: G04_0 Mask */ -#define LCD_PAL60_B04_0_Pos 10 /*!< LCD PAL60: B04_0 Position */ -#define LCD_PAL60_B04_0_Msk (0x1fUL << LCD_PAL60_B04_0_Pos) /*!< LCD PAL60: B04_0 Mask */ -#define LCD_PAL60_I0_Pos 15 /*!< LCD PAL60: I0 Position */ -#define LCD_PAL60_I0_Msk (0x01UL << LCD_PAL60_I0_Pos) /*!< LCD PAL60: I0 Mask */ -#define LCD_PAL60_R14_0_Pos 16 /*!< LCD PAL60: R14_0 Position */ -#define LCD_PAL60_R14_0_Msk (0x1fUL << LCD_PAL60_R14_0_Pos) /*!< LCD PAL60: R14_0 Mask */ -#define LCD_PAL60_G14_0_Pos 21 /*!< LCD PAL60: G14_0 Position */ -#define LCD_PAL60_G14_0_Msk (0x1fUL << LCD_PAL60_G14_0_Pos) /*!< LCD PAL60: G14_0 Mask */ -#define LCD_PAL60_B14_0_Pos 26 /*!< LCD PAL60: B14_0 Position */ -#define LCD_PAL60_B14_0_Msk (0x1fUL << LCD_PAL60_B14_0_Pos) /*!< LCD PAL60: B14_0 Mask */ -#define LCD_PAL60_I1_Pos 31 /*!< LCD PAL60: I1 Position */ -#define LCD_PAL60_I1_Msk (0x01UL << LCD_PAL60_I1_Pos) /*!< LCD PAL60: I1 Mask */ - -// ---------------------------------------- LCD_PAL61 ------------------------------------------- -#define LCD_PAL61_R04_0_Pos 0 /*!< LCD PAL61: R04_0 Position */ -#define LCD_PAL61_R04_0_Msk (0x1fUL << LCD_PAL61_R04_0_Pos) /*!< LCD PAL61: R04_0 Mask */ -#define LCD_PAL61_G04_0_Pos 5 /*!< LCD PAL61: G04_0 Position */ -#define LCD_PAL61_G04_0_Msk (0x1fUL << LCD_PAL61_G04_0_Pos) /*!< LCD PAL61: G04_0 Mask */ -#define LCD_PAL61_B04_0_Pos 10 /*!< LCD PAL61: B04_0 Position */ -#define LCD_PAL61_B04_0_Msk (0x1fUL << LCD_PAL61_B04_0_Pos) /*!< LCD PAL61: B04_0 Mask */ -#define LCD_PAL61_I0_Pos 15 /*!< LCD PAL61: I0 Position */ -#define LCD_PAL61_I0_Msk (0x01UL << LCD_PAL61_I0_Pos) /*!< LCD PAL61: I0 Mask */ -#define LCD_PAL61_R14_0_Pos 16 /*!< LCD PAL61: R14_0 Position */ -#define LCD_PAL61_R14_0_Msk (0x1fUL << LCD_PAL61_R14_0_Pos) /*!< LCD PAL61: R14_0 Mask */ -#define LCD_PAL61_G14_0_Pos 21 /*!< LCD PAL61: G14_0 Position */ -#define LCD_PAL61_G14_0_Msk (0x1fUL << LCD_PAL61_G14_0_Pos) /*!< LCD PAL61: G14_0 Mask */ -#define LCD_PAL61_B14_0_Pos 26 /*!< LCD PAL61: B14_0 Position */ -#define LCD_PAL61_B14_0_Msk (0x1fUL << LCD_PAL61_B14_0_Pos) /*!< LCD PAL61: B14_0 Mask */ -#define LCD_PAL61_I1_Pos 31 /*!< LCD PAL61: I1 Position */ -#define LCD_PAL61_I1_Msk (0x01UL << LCD_PAL61_I1_Pos) /*!< LCD PAL61: I1 Mask */ - -// ---------------------------------------- LCD_PAL62 ------------------------------------------- -#define LCD_PAL62_R04_0_Pos 0 /*!< LCD PAL62: R04_0 Position */ -#define LCD_PAL62_R04_0_Msk (0x1fUL << LCD_PAL62_R04_0_Pos) /*!< LCD PAL62: R04_0 Mask */ -#define LCD_PAL62_G04_0_Pos 5 /*!< LCD PAL62: G04_0 Position */ -#define LCD_PAL62_G04_0_Msk (0x1fUL << LCD_PAL62_G04_0_Pos) /*!< LCD PAL62: G04_0 Mask */ -#define LCD_PAL62_B04_0_Pos 10 /*!< LCD PAL62: B04_0 Position */ -#define LCD_PAL62_B04_0_Msk (0x1fUL << LCD_PAL62_B04_0_Pos) /*!< LCD PAL62: B04_0 Mask */ -#define LCD_PAL62_I0_Pos 15 /*!< LCD PAL62: I0 Position */ -#define LCD_PAL62_I0_Msk (0x01UL << LCD_PAL62_I0_Pos) /*!< LCD PAL62: I0 Mask */ -#define LCD_PAL62_R14_0_Pos 16 /*!< LCD PAL62: R14_0 Position */ -#define LCD_PAL62_R14_0_Msk (0x1fUL << LCD_PAL62_R14_0_Pos) /*!< LCD PAL62: R14_0 Mask */ -#define LCD_PAL62_G14_0_Pos 21 /*!< LCD PAL62: G14_0 Position */ -#define LCD_PAL62_G14_0_Msk (0x1fUL << LCD_PAL62_G14_0_Pos) /*!< LCD PAL62: G14_0 Mask */ -#define LCD_PAL62_B14_0_Pos 26 /*!< LCD PAL62: B14_0 Position */ -#define LCD_PAL62_B14_0_Msk (0x1fUL << LCD_PAL62_B14_0_Pos) /*!< LCD PAL62: B14_0 Mask */ -#define LCD_PAL62_I1_Pos 31 /*!< LCD PAL62: I1 Position */ -#define LCD_PAL62_I1_Msk (0x01UL << LCD_PAL62_I1_Pos) /*!< LCD PAL62: I1 Mask */ - -// ---------------------------------------- LCD_PAL63 ------------------------------------------- -#define LCD_PAL63_R04_0_Pos 0 /*!< LCD PAL63: R04_0 Position */ -#define LCD_PAL63_R04_0_Msk (0x1fUL << LCD_PAL63_R04_0_Pos) /*!< LCD PAL63: R04_0 Mask */ -#define LCD_PAL63_G04_0_Pos 5 /*!< LCD PAL63: G04_0 Position */ -#define LCD_PAL63_G04_0_Msk (0x1fUL << LCD_PAL63_G04_0_Pos) /*!< LCD PAL63: G04_0 Mask */ -#define LCD_PAL63_B04_0_Pos 10 /*!< LCD PAL63: B04_0 Position */ -#define LCD_PAL63_B04_0_Msk (0x1fUL << LCD_PAL63_B04_0_Pos) /*!< LCD PAL63: B04_0 Mask */ -#define LCD_PAL63_I0_Pos 15 /*!< LCD PAL63: I0 Position */ -#define LCD_PAL63_I0_Msk (0x01UL << LCD_PAL63_I0_Pos) /*!< LCD PAL63: I0 Mask */ -#define LCD_PAL63_R14_0_Pos 16 /*!< LCD PAL63: R14_0 Position */ -#define LCD_PAL63_R14_0_Msk (0x1fUL << LCD_PAL63_R14_0_Pos) /*!< LCD PAL63: R14_0 Mask */ -#define LCD_PAL63_G14_0_Pos 21 /*!< LCD PAL63: G14_0 Position */ -#define LCD_PAL63_G14_0_Msk (0x1fUL << LCD_PAL63_G14_0_Pos) /*!< LCD PAL63: G14_0 Mask */ -#define LCD_PAL63_B14_0_Pos 26 /*!< LCD PAL63: B14_0 Position */ -#define LCD_PAL63_B14_0_Msk (0x1fUL << LCD_PAL63_B14_0_Pos) /*!< LCD PAL63: B14_0 Mask */ -#define LCD_PAL63_I1_Pos 31 /*!< LCD PAL63: I1 Position */ -#define LCD_PAL63_I1_Msk (0x01UL << LCD_PAL63_I1_Pos) /*!< LCD PAL63: I1 Mask */ - -// ---------------------------------------- LCD_PAL64 ------------------------------------------- -#define LCD_PAL64_R04_0_Pos 0 /*!< LCD PAL64: R04_0 Position */ -#define LCD_PAL64_R04_0_Msk (0x1fUL << LCD_PAL64_R04_0_Pos) /*!< LCD PAL64: R04_0 Mask */ -#define LCD_PAL64_G04_0_Pos 5 /*!< LCD PAL64: G04_0 Position */ -#define LCD_PAL64_G04_0_Msk (0x1fUL << LCD_PAL64_G04_0_Pos) /*!< LCD PAL64: G04_0 Mask */ -#define LCD_PAL64_B04_0_Pos 10 /*!< LCD PAL64: B04_0 Position */ -#define LCD_PAL64_B04_0_Msk (0x1fUL << LCD_PAL64_B04_0_Pos) /*!< LCD PAL64: B04_0 Mask */ -#define LCD_PAL64_I0_Pos 15 /*!< LCD PAL64: I0 Position */ -#define LCD_PAL64_I0_Msk (0x01UL << LCD_PAL64_I0_Pos) /*!< LCD PAL64: I0 Mask */ -#define LCD_PAL64_R14_0_Pos 16 /*!< LCD PAL64: R14_0 Position */ -#define LCD_PAL64_R14_0_Msk (0x1fUL << LCD_PAL64_R14_0_Pos) /*!< LCD PAL64: R14_0 Mask */ -#define LCD_PAL64_G14_0_Pos 21 /*!< LCD PAL64: G14_0 Position */ -#define LCD_PAL64_G14_0_Msk (0x1fUL << LCD_PAL64_G14_0_Pos) /*!< LCD PAL64: G14_0 Mask */ -#define LCD_PAL64_B14_0_Pos 26 /*!< LCD PAL64: B14_0 Position */ -#define LCD_PAL64_B14_0_Msk (0x1fUL << LCD_PAL64_B14_0_Pos) /*!< LCD PAL64: B14_0 Mask */ -#define LCD_PAL64_I1_Pos 31 /*!< LCD PAL64: I1 Position */ -#define LCD_PAL64_I1_Msk (0x01UL << LCD_PAL64_I1_Pos) /*!< LCD PAL64: I1 Mask */ - -// ---------------------------------------- LCD_PAL65 ------------------------------------------- -#define LCD_PAL65_R04_0_Pos 0 /*!< LCD PAL65: R04_0 Position */ -#define LCD_PAL65_R04_0_Msk (0x1fUL << LCD_PAL65_R04_0_Pos) /*!< LCD PAL65: R04_0 Mask */ -#define LCD_PAL65_G04_0_Pos 5 /*!< LCD PAL65: G04_0 Position */ -#define LCD_PAL65_G04_0_Msk (0x1fUL << LCD_PAL65_G04_0_Pos) /*!< LCD PAL65: G04_0 Mask */ -#define LCD_PAL65_B04_0_Pos 10 /*!< LCD PAL65: B04_0 Position */ -#define LCD_PAL65_B04_0_Msk (0x1fUL << LCD_PAL65_B04_0_Pos) /*!< LCD PAL65: B04_0 Mask */ -#define LCD_PAL65_I0_Pos 15 /*!< LCD PAL65: I0 Position */ -#define LCD_PAL65_I0_Msk (0x01UL << LCD_PAL65_I0_Pos) /*!< LCD PAL65: I0 Mask */ -#define LCD_PAL65_R14_0_Pos 16 /*!< LCD PAL65: R14_0 Position */ -#define LCD_PAL65_R14_0_Msk (0x1fUL << LCD_PAL65_R14_0_Pos) /*!< LCD PAL65: R14_0 Mask */ -#define LCD_PAL65_G14_0_Pos 21 /*!< LCD PAL65: G14_0 Position */ -#define LCD_PAL65_G14_0_Msk (0x1fUL << LCD_PAL65_G14_0_Pos) /*!< LCD PAL65: G14_0 Mask */ -#define LCD_PAL65_B14_0_Pos 26 /*!< LCD PAL65: B14_0 Position */ -#define LCD_PAL65_B14_0_Msk (0x1fUL << LCD_PAL65_B14_0_Pos) /*!< LCD PAL65: B14_0 Mask */ -#define LCD_PAL65_I1_Pos 31 /*!< LCD PAL65: I1 Position */ -#define LCD_PAL65_I1_Msk (0x01UL << LCD_PAL65_I1_Pos) /*!< LCD PAL65: I1 Mask */ - -// ---------------------------------------- LCD_PAL66 ------------------------------------------- -#define LCD_PAL66_R04_0_Pos 0 /*!< LCD PAL66: R04_0 Position */ -#define LCD_PAL66_R04_0_Msk (0x1fUL << LCD_PAL66_R04_0_Pos) /*!< LCD PAL66: R04_0 Mask */ -#define LCD_PAL66_G04_0_Pos 5 /*!< LCD PAL66: G04_0 Position */ -#define LCD_PAL66_G04_0_Msk (0x1fUL << LCD_PAL66_G04_0_Pos) /*!< LCD PAL66: G04_0 Mask */ -#define LCD_PAL66_B04_0_Pos 10 /*!< LCD PAL66: B04_0 Position */ -#define LCD_PAL66_B04_0_Msk (0x1fUL << LCD_PAL66_B04_0_Pos) /*!< LCD PAL66: B04_0 Mask */ -#define LCD_PAL66_I0_Pos 15 /*!< LCD PAL66: I0 Position */ -#define LCD_PAL66_I0_Msk (0x01UL << LCD_PAL66_I0_Pos) /*!< LCD PAL66: I0 Mask */ -#define LCD_PAL66_R14_0_Pos 16 /*!< LCD PAL66: R14_0 Position */ -#define LCD_PAL66_R14_0_Msk (0x1fUL << LCD_PAL66_R14_0_Pos) /*!< LCD PAL66: R14_0 Mask */ -#define LCD_PAL66_G14_0_Pos 21 /*!< LCD PAL66: G14_0 Position */ -#define LCD_PAL66_G14_0_Msk (0x1fUL << LCD_PAL66_G14_0_Pos) /*!< LCD PAL66: G14_0 Mask */ -#define LCD_PAL66_B14_0_Pos 26 /*!< LCD PAL66: B14_0 Position */ -#define LCD_PAL66_B14_0_Msk (0x1fUL << LCD_PAL66_B14_0_Pos) /*!< LCD PAL66: B14_0 Mask */ -#define LCD_PAL66_I1_Pos 31 /*!< LCD PAL66: I1 Position */ -#define LCD_PAL66_I1_Msk (0x01UL << LCD_PAL66_I1_Pos) /*!< LCD PAL66: I1 Mask */ - -// ---------------------------------------- LCD_PAL67 ------------------------------------------- -#define LCD_PAL67_R04_0_Pos 0 /*!< LCD PAL67: R04_0 Position */ -#define LCD_PAL67_R04_0_Msk (0x1fUL << LCD_PAL67_R04_0_Pos) /*!< LCD PAL67: R04_0 Mask */ -#define LCD_PAL67_G04_0_Pos 5 /*!< LCD PAL67: G04_0 Position */ -#define LCD_PAL67_G04_0_Msk (0x1fUL << LCD_PAL67_G04_0_Pos) /*!< LCD PAL67: G04_0 Mask */ -#define LCD_PAL67_B04_0_Pos 10 /*!< LCD PAL67: B04_0 Position */ -#define LCD_PAL67_B04_0_Msk (0x1fUL << LCD_PAL67_B04_0_Pos) /*!< LCD PAL67: B04_0 Mask */ -#define LCD_PAL67_I0_Pos 15 /*!< LCD PAL67: I0 Position */ -#define LCD_PAL67_I0_Msk (0x01UL << LCD_PAL67_I0_Pos) /*!< LCD PAL67: I0 Mask */ -#define LCD_PAL67_R14_0_Pos 16 /*!< LCD PAL67: R14_0 Position */ -#define LCD_PAL67_R14_0_Msk (0x1fUL << LCD_PAL67_R14_0_Pos) /*!< LCD PAL67: R14_0 Mask */ -#define LCD_PAL67_G14_0_Pos 21 /*!< LCD PAL67: G14_0 Position */ -#define LCD_PAL67_G14_0_Msk (0x1fUL << LCD_PAL67_G14_0_Pos) /*!< LCD PAL67: G14_0 Mask */ -#define LCD_PAL67_B14_0_Pos 26 /*!< LCD PAL67: B14_0 Position */ -#define LCD_PAL67_B14_0_Msk (0x1fUL << LCD_PAL67_B14_0_Pos) /*!< LCD PAL67: B14_0 Mask */ -#define LCD_PAL67_I1_Pos 31 /*!< LCD PAL67: I1 Position */ -#define LCD_PAL67_I1_Msk (0x01UL << LCD_PAL67_I1_Pos) /*!< LCD PAL67: I1 Mask */ - -// ---------------------------------------- LCD_PAL68 ------------------------------------------- -#define LCD_PAL68_R04_0_Pos 0 /*!< LCD PAL68: R04_0 Position */ -#define LCD_PAL68_R04_0_Msk (0x1fUL << LCD_PAL68_R04_0_Pos) /*!< LCD PAL68: R04_0 Mask */ -#define LCD_PAL68_G04_0_Pos 5 /*!< LCD PAL68: G04_0 Position */ -#define LCD_PAL68_G04_0_Msk (0x1fUL << LCD_PAL68_G04_0_Pos) /*!< LCD PAL68: G04_0 Mask */ -#define LCD_PAL68_B04_0_Pos 10 /*!< LCD PAL68: B04_0 Position */ -#define LCD_PAL68_B04_0_Msk (0x1fUL << LCD_PAL68_B04_0_Pos) /*!< LCD PAL68: B04_0 Mask */ -#define LCD_PAL68_I0_Pos 15 /*!< LCD PAL68: I0 Position */ -#define LCD_PAL68_I0_Msk (0x01UL << LCD_PAL68_I0_Pos) /*!< LCD PAL68: I0 Mask */ -#define LCD_PAL68_R14_0_Pos 16 /*!< LCD PAL68: R14_0 Position */ -#define LCD_PAL68_R14_0_Msk (0x1fUL << LCD_PAL68_R14_0_Pos) /*!< LCD PAL68: R14_0 Mask */ -#define LCD_PAL68_G14_0_Pos 21 /*!< LCD PAL68: G14_0 Position */ -#define LCD_PAL68_G14_0_Msk (0x1fUL << LCD_PAL68_G14_0_Pos) /*!< LCD PAL68: G14_0 Mask */ -#define LCD_PAL68_B14_0_Pos 26 /*!< LCD PAL68: B14_0 Position */ -#define LCD_PAL68_B14_0_Msk (0x1fUL << LCD_PAL68_B14_0_Pos) /*!< LCD PAL68: B14_0 Mask */ -#define LCD_PAL68_I1_Pos 31 /*!< LCD PAL68: I1 Position */ -#define LCD_PAL68_I1_Msk (0x01UL << LCD_PAL68_I1_Pos) /*!< LCD PAL68: I1 Mask */ - -// ---------------------------------------- LCD_PAL69 ------------------------------------------- -#define LCD_PAL69_R04_0_Pos 0 /*!< LCD PAL69: R04_0 Position */ -#define LCD_PAL69_R04_0_Msk (0x1fUL << LCD_PAL69_R04_0_Pos) /*!< LCD PAL69: R04_0 Mask */ -#define LCD_PAL69_G04_0_Pos 5 /*!< LCD PAL69: G04_0 Position */ -#define LCD_PAL69_G04_0_Msk (0x1fUL << LCD_PAL69_G04_0_Pos) /*!< LCD PAL69: G04_0 Mask */ -#define LCD_PAL69_B04_0_Pos 10 /*!< LCD PAL69: B04_0 Position */ -#define LCD_PAL69_B04_0_Msk (0x1fUL << LCD_PAL69_B04_0_Pos) /*!< LCD PAL69: B04_0 Mask */ -#define LCD_PAL69_I0_Pos 15 /*!< LCD PAL69: I0 Position */ -#define LCD_PAL69_I0_Msk (0x01UL << LCD_PAL69_I0_Pos) /*!< LCD PAL69: I0 Mask */ -#define LCD_PAL69_R14_0_Pos 16 /*!< LCD PAL69: R14_0 Position */ -#define LCD_PAL69_R14_0_Msk (0x1fUL << LCD_PAL69_R14_0_Pos) /*!< LCD PAL69: R14_0 Mask */ -#define LCD_PAL69_G14_0_Pos 21 /*!< LCD PAL69: G14_0 Position */ -#define LCD_PAL69_G14_0_Msk (0x1fUL << LCD_PAL69_G14_0_Pos) /*!< LCD PAL69: G14_0 Mask */ -#define LCD_PAL69_B14_0_Pos 26 /*!< LCD PAL69: B14_0 Position */ -#define LCD_PAL69_B14_0_Msk (0x1fUL << LCD_PAL69_B14_0_Pos) /*!< LCD PAL69: B14_0 Mask */ -#define LCD_PAL69_I1_Pos 31 /*!< LCD PAL69: I1 Position */ -#define LCD_PAL69_I1_Msk (0x01UL << LCD_PAL69_I1_Pos) /*!< LCD PAL69: I1 Mask */ - -// ---------------------------------------- LCD_PAL70 ------------------------------------------- -#define LCD_PAL70_R04_0_Pos 0 /*!< LCD PAL70: R04_0 Position */ -#define LCD_PAL70_R04_0_Msk (0x1fUL << LCD_PAL70_R04_0_Pos) /*!< LCD PAL70: R04_0 Mask */ -#define LCD_PAL70_G04_0_Pos 5 /*!< LCD PAL70: G04_0 Position */ -#define LCD_PAL70_G04_0_Msk (0x1fUL << LCD_PAL70_G04_0_Pos) /*!< LCD PAL70: G04_0 Mask */ -#define LCD_PAL70_B04_0_Pos 10 /*!< LCD PAL70: B04_0 Position */ -#define LCD_PAL70_B04_0_Msk (0x1fUL << LCD_PAL70_B04_0_Pos) /*!< LCD PAL70: B04_0 Mask */ -#define LCD_PAL70_I0_Pos 15 /*!< LCD PAL70: I0 Position */ -#define LCD_PAL70_I0_Msk (0x01UL << LCD_PAL70_I0_Pos) /*!< LCD PAL70: I0 Mask */ -#define LCD_PAL70_R14_0_Pos 16 /*!< LCD PAL70: R14_0 Position */ -#define LCD_PAL70_R14_0_Msk (0x1fUL << LCD_PAL70_R14_0_Pos) /*!< LCD PAL70: R14_0 Mask */ -#define LCD_PAL70_G14_0_Pos 21 /*!< LCD PAL70: G14_0 Position */ -#define LCD_PAL70_G14_0_Msk (0x1fUL << LCD_PAL70_G14_0_Pos) /*!< LCD PAL70: G14_0 Mask */ -#define LCD_PAL70_B14_0_Pos 26 /*!< LCD PAL70: B14_0 Position */ -#define LCD_PAL70_B14_0_Msk (0x1fUL << LCD_PAL70_B14_0_Pos) /*!< LCD PAL70: B14_0 Mask */ -#define LCD_PAL70_I1_Pos 31 /*!< LCD PAL70: I1 Position */ -#define LCD_PAL70_I1_Msk (0x01UL << LCD_PAL70_I1_Pos) /*!< LCD PAL70: I1 Mask */ - -// ---------------------------------------- LCD_PAL71 ------------------------------------------- -#define LCD_PAL71_R04_0_Pos 0 /*!< LCD PAL71: R04_0 Position */ -#define LCD_PAL71_R04_0_Msk (0x1fUL << LCD_PAL71_R04_0_Pos) /*!< LCD PAL71: R04_0 Mask */ -#define LCD_PAL71_G04_0_Pos 5 /*!< LCD PAL71: G04_0 Position */ -#define LCD_PAL71_G04_0_Msk (0x1fUL << LCD_PAL71_G04_0_Pos) /*!< LCD PAL71: G04_0 Mask */ -#define LCD_PAL71_B04_0_Pos 10 /*!< LCD PAL71: B04_0 Position */ -#define LCD_PAL71_B04_0_Msk (0x1fUL << LCD_PAL71_B04_0_Pos) /*!< LCD PAL71: B04_0 Mask */ -#define LCD_PAL71_I0_Pos 15 /*!< LCD PAL71: I0 Position */ -#define LCD_PAL71_I0_Msk (0x01UL << LCD_PAL71_I0_Pos) /*!< LCD PAL71: I0 Mask */ -#define LCD_PAL71_R14_0_Pos 16 /*!< LCD PAL71: R14_0 Position */ -#define LCD_PAL71_R14_0_Msk (0x1fUL << LCD_PAL71_R14_0_Pos) /*!< LCD PAL71: R14_0 Mask */ -#define LCD_PAL71_G14_0_Pos 21 /*!< LCD PAL71: G14_0 Position */ -#define LCD_PAL71_G14_0_Msk (0x1fUL << LCD_PAL71_G14_0_Pos) /*!< LCD PAL71: G14_0 Mask */ -#define LCD_PAL71_B14_0_Pos 26 /*!< LCD PAL71: B14_0 Position */ -#define LCD_PAL71_B14_0_Msk (0x1fUL << LCD_PAL71_B14_0_Pos) /*!< LCD PAL71: B14_0 Mask */ -#define LCD_PAL71_I1_Pos 31 /*!< LCD PAL71: I1 Position */ -#define LCD_PAL71_I1_Msk (0x01UL << LCD_PAL71_I1_Pos) /*!< LCD PAL71: I1 Mask */ - -// ---------------------------------------- LCD_PAL72 ------------------------------------------- -#define LCD_PAL72_R04_0_Pos 0 /*!< LCD PAL72: R04_0 Position */ -#define LCD_PAL72_R04_0_Msk (0x1fUL << LCD_PAL72_R04_0_Pos) /*!< LCD PAL72: R04_0 Mask */ -#define LCD_PAL72_G04_0_Pos 5 /*!< LCD PAL72: G04_0 Position */ -#define LCD_PAL72_G04_0_Msk (0x1fUL << LCD_PAL72_G04_0_Pos) /*!< LCD PAL72: G04_0 Mask */ -#define LCD_PAL72_B04_0_Pos 10 /*!< LCD PAL72: B04_0 Position */ -#define LCD_PAL72_B04_0_Msk (0x1fUL << LCD_PAL72_B04_0_Pos) /*!< LCD PAL72: B04_0 Mask */ -#define LCD_PAL72_I0_Pos 15 /*!< LCD PAL72: I0 Position */ -#define LCD_PAL72_I0_Msk (0x01UL << LCD_PAL72_I0_Pos) /*!< LCD PAL72: I0 Mask */ -#define LCD_PAL72_R14_0_Pos 16 /*!< LCD PAL72: R14_0 Position */ -#define LCD_PAL72_R14_0_Msk (0x1fUL << LCD_PAL72_R14_0_Pos) /*!< LCD PAL72: R14_0 Mask */ -#define LCD_PAL72_G14_0_Pos 21 /*!< LCD PAL72: G14_0 Position */ -#define LCD_PAL72_G14_0_Msk (0x1fUL << LCD_PAL72_G14_0_Pos) /*!< LCD PAL72: G14_0 Mask */ -#define LCD_PAL72_B14_0_Pos 26 /*!< LCD PAL72: B14_0 Position */ -#define LCD_PAL72_B14_0_Msk (0x1fUL << LCD_PAL72_B14_0_Pos) /*!< LCD PAL72: B14_0 Mask */ -#define LCD_PAL72_I1_Pos 31 /*!< LCD PAL72: I1 Position */ -#define LCD_PAL72_I1_Msk (0x01UL << LCD_PAL72_I1_Pos) /*!< LCD PAL72: I1 Mask */ - -// ---------------------------------------- LCD_PAL73 ------------------------------------------- -#define LCD_PAL73_R04_0_Pos 0 /*!< LCD PAL73: R04_0 Position */ -#define LCD_PAL73_R04_0_Msk (0x1fUL << LCD_PAL73_R04_0_Pos) /*!< LCD PAL73: R04_0 Mask */ -#define LCD_PAL73_G04_0_Pos 5 /*!< LCD PAL73: G04_0 Position */ -#define LCD_PAL73_G04_0_Msk (0x1fUL << LCD_PAL73_G04_0_Pos) /*!< LCD PAL73: G04_0 Mask */ -#define LCD_PAL73_B04_0_Pos 10 /*!< LCD PAL73: B04_0 Position */ -#define LCD_PAL73_B04_0_Msk (0x1fUL << LCD_PAL73_B04_0_Pos) /*!< LCD PAL73: B04_0 Mask */ -#define LCD_PAL73_I0_Pos 15 /*!< LCD PAL73: I0 Position */ -#define LCD_PAL73_I0_Msk (0x01UL << LCD_PAL73_I0_Pos) /*!< LCD PAL73: I0 Mask */ -#define LCD_PAL73_R14_0_Pos 16 /*!< LCD PAL73: R14_0 Position */ -#define LCD_PAL73_R14_0_Msk (0x1fUL << LCD_PAL73_R14_0_Pos) /*!< LCD PAL73: R14_0 Mask */ -#define LCD_PAL73_G14_0_Pos 21 /*!< LCD PAL73: G14_0 Position */ -#define LCD_PAL73_G14_0_Msk (0x1fUL << LCD_PAL73_G14_0_Pos) /*!< LCD PAL73: G14_0 Mask */ -#define LCD_PAL73_B14_0_Pos 26 /*!< LCD PAL73: B14_0 Position */ -#define LCD_PAL73_B14_0_Msk (0x1fUL << LCD_PAL73_B14_0_Pos) /*!< LCD PAL73: B14_0 Mask */ -#define LCD_PAL73_I1_Pos 31 /*!< LCD PAL73: I1 Position */ -#define LCD_PAL73_I1_Msk (0x01UL << LCD_PAL73_I1_Pos) /*!< LCD PAL73: I1 Mask */ - -// ---------------------------------------- LCD_PAL74 ------------------------------------------- -#define LCD_PAL74_R04_0_Pos 0 /*!< LCD PAL74: R04_0 Position */ -#define LCD_PAL74_R04_0_Msk (0x1fUL << LCD_PAL74_R04_0_Pos) /*!< LCD PAL74: R04_0 Mask */ -#define LCD_PAL74_G04_0_Pos 5 /*!< LCD PAL74: G04_0 Position */ -#define LCD_PAL74_G04_0_Msk (0x1fUL << LCD_PAL74_G04_0_Pos) /*!< LCD PAL74: G04_0 Mask */ -#define LCD_PAL74_B04_0_Pos 10 /*!< LCD PAL74: B04_0 Position */ -#define LCD_PAL74_B04_0_Msk (0x1fUL << LCD_PAL74_B04_0_Pos) /*!< LCD PAL74: B04_0 Mask */ -#define LCD_PAL74_I0_Pos 15 /*!< LCD PAL74: I0 Position */ -#define LCD_PAL74_I0_Msk (0x01UL << LCD_PAL74_I0_Pos) /*!< LCD PAL74: I0 Mask */ -#define LCD_PAL74_R14_0_Pos 16 /*!< LCD PAL74: R14_0 Position */ -#define LCD_PAL74_R14_0_Msk (0x1fUL << LCD_PAL74_R14_0_Pos) /*!< LCD PAL74: R14_0 Mask */ -#define LCD_PAL74_G14_0_Pos 21 /*!< LCD PAL74: G14_0 Position */ -#define LCD_PAL74_G14_0_Msk (0x1fUL << LCD_PAL74_G14_0_Pos) /*!< LCD PAL74: G14_0 Mask */ -#define LCD_PAL74_B14_0_Pos 26 /*!< LCD PAL74: B14_0 Position */ -#define LCD_PAL74_B14_0_Msk (0x1fUL << LCD_PAL74_B14_0_Pos) /*!< LCD PAL74: B14_0 Mask */ -#define LCD_PAL74_I1_Pos 31 /*!< LCD PAL74: I1 Position */ -#define LCD_PAL74_I1_Msk (0x01UL << LCD_PAL74_I1_Pos) /*!< LCD PAL74: I1 Mask */ - -// ---------------------------------------- LCD_PAL75 ------------------------------------------- -#define LCD_PAL75_R04_0_Pos 0 /*!< LCD PAL75: R04_0 Position */ -#define LCD_PAL75_R04_0_Msk (0x1fUL << LCD_PAL75_R04_0_Pos) /*!< LCD PAL75: R04_0 Mask */ -#define LCD_PAL75_G04_0_Pos 5 /*!< LCD PAL75: G04_0 Position */ -#define LCD_PAL75_G04_0_Msk (0x1fUL << LCD_PAL75_G04_0_Pos) /*!< LCD PAL75: G04_0 Mask */ -#define LCD_PAL75_B04_0_Pos 10 /*!< LCD PAL75: B04_0 Position */ -#define LCD_PAL75_B04_0_Msk (0x1fUL << LCD_PAL75_B04_0_Pos) /*!< LCD PAL75: B04_0 Mask */ -#define LCD_PAL75_I0_Pos 15 /*!< LCD PAL75: I0 Position */ -#define LCD_PAL75_I0_Msk (0x01UL << LCD_PAL75_I0_Pos) /*!< LCD PAL75: I0 Mask */ -#define LCD_PAL75_R14_0_Pos 16 /*!< LCD PAL75: R14_0 Position */ -#define LCD_PAL75_R14_0_Msk (0x1fUL << LCD_PAL75_R14_0_Pos) /*!< LCD PAL75: R14_0 Mask */ -#define LCD_PAL75_G14_0_Pos 21 /*!< LCD PAL75: G14_0 Position */ -#define LCD_PAL75_G14_0_Msk (0x1fUL << LCD_PAL75_G14_0_Pos) /*!< LCD PAL75: G14_0 Mask */ -#define LCD_PAL75_B14_0_Pos 26 /*!< LCD PAL75: B14_0 Position */ -#define LCD_PAL75_B14_0_Msk (0x1fUL << LCD_PAL75_B14_0_Pos) /*!< LCD PAL75: B14_0 Mask */ -#define LCD_PAL75_I1_Pos 31 /*!< LCD PAL75: I1 Position */ -#define LCD_PAL75_I1_Msk (0x01UL << LCD_PAL75_I1_Pos) /*!< LCD PAL75: I1 Mask */ - -// ---------------------------------------- LCD_PAL76 ------------------------------------------- -#define LCD_PAL76_R04_0_Pos 0 /*!< LCD PAL76: R04_0 Position */ -#define LCD_PAL76_R04_0_Msk (0x1fUL << LCD_PAL76_R04_0_Pos) /*!< LCD PAL76: R04_0 Mask */ -#define LCD_PAL76_G04_0_Pos 5 /*!< LCD PAL76: G04_0 Position */ -#define LCD_PAL76_G04_0_Msk (0x1fUL << LCD_PAL76_G04_0_Pos) /*!< LCD PAL76: G04_0 Mask */ -#define LCD_PAL76_B04_0_Pos 10 /*!< LCD PAL76: B04_0 Position */ -#define LCD_PAL76_B04_0_Msk (0x1fUL << LCD_PAL76_B04_0_Pos) /*!< LCD PAL76: B04_0 Mask */ -#define LCD_PAL76_I0_Pos 15 /*!< LCD PAL76: I0 Position */ -#define LCD_PAL76_I0_Msk (0x01UL << LCD_PAL76_I0_Pos) /*!< LCD PAL76: I0 Mask */ -#define LCD_PAL76_R14_0_Pos 16 /*!< LCD PAL76: R14_0 Position */ -#define LCD_PAL76_R14_0_Msk (0x1fUL << LCD_PAL76_R14_0_Pos) /*!< LCD PAL76: R14_0 Mask */ -#define LCD_PAL76_G14_0_Pos 21 /*!< LCD PAL76: G14_0 Position */ -#define LCD_PAL76_G14_0_Msk (0x1fUL << LCD_PAL76_G14_0_Pos) /*!< LCD PAL76: G14_0 Mask */ -#define LCD_PAL76_B14_0_Pos 26 /*!< LCD PAL76: B14_0 Position */ -#define LCD_PAL76_B14_0_Msk (0x1fUL << LCD_PAL76_B14_0_Pos) /*!< LCD PAL76: B14_0 Mask */ -#define LCD_PAL76_I1_Pos 31 /*!< LCD PAL76: I1 Position */ -#define LCD_PAL76_I1_Msk (0x01UL << LCD_PAL76_I1_Pos) /*!< LCD PAL76: I1 Mask */ - -// ---------------------------------------- LCD_PAL77 ------------------------------------------- -#define LCD_PAL77_R04_0_Pos 0 /*!< LCD PAL77: R04_0 Position */ -#define LCD_PAL77_R04_0_Msk (0x1fUL << LCD_PAL77_R04_0_Pos) /*!< LCD PAL77: R04_0 Mask */ -#define LCD_PAL77_G04_0_Pos 5 /*!< LCD PAL77: G04_0 Position */ -#define LCD_PAL77_G04_0_Msk (0x1fUL << LCD_PAL77_G04_0_Pos) /*!< LCD PAL77: G04_0 Mask */ -#define LCD_PAL77_B04_0_Pos 10 /*!< LCD PAL77: B04_0 Position */ -#define LCD_PAL77_B04_0_Msk (0x1fUL << LCD_PAL77_B04_0_Pos) /*!< LCD PAL77: B04_0 Mask */ -#define LCD_PAL77_I0_Pos 15 /*!< LCD PAL77: I0 Position */ -#define LCD_PAL77_I0_Msk (0x01UL << LCD_PAL77_I0_Pos) /*!< LCD PAL77: I0 Mask */ -#define LCD_PAL77_R14_0_Pos 16 /*!< LCD PAL77: R14_0 Position */ -#define LCD_PAL77_R14_0_Msk (0x1fUL << LCD_PAL77_R14_0_Pos) /*!< LCD PAL77: R14_0 Mask */ -#define LCD_PAL77_G14_0_Pos 21 /*!< LCD PAL77: G14_0 Position */ -#define LCD_PAL77_G14_0_Msk (0x1fUL << LCD_PAL77_G14_0_Pos) /*!< LCD PAL77: G14_0 Mask */ -#define LCD_PAL77_B14_0_Pos 26 /*!< LCD PAL77: B14_0 Position */ -#define LCD_PAL77_B14_0_Msk (0x1fUL << LCD_PAL77_B14_0_Pos) /*!< LCD PAL77: B14_0 Mask */ -#define LCD_PAL77_I1_Pos 31 /*!< LCD PAL77: I1 Position */ -#define LCD_PAL77_I1_Msk (0x01UL << LCD_PAL77_I1_Pos) /*!< LCD PAL77: I1 Mask */ - -// ---------------------------------------- LCD_PAL78 ------------------------------------------- -#define LCD_PAL78_R04_0_Pos 0 /*!< LCD PAL78: R04_0 Position */ -#define LCD_PAL78_R04_0_Msk (0x1fUL << LCD_PAL78_R04_0_Pos) /*!< LCD PAL78: R04_0 Mask */ -#define LCD_PAL78_G04_0_Pos 5 /*!< LCD PAL78: G04_0 Position */ -#define LCD_PAL78_G04_0_Msk (0x1fUL << LCD_PAL78_G04_0_Pos) /*!< LCD PAL78: G04_0 Mask */ -#define LCD_PAL78_B04_0_Pos 10 /*!< LCD PAL78: B04_0 Position */ -#define LCD_PAL78_B04_0_Msk (0x1fUL << LCD_PAL78_B04_0_Pos) /*!< LCD PAL78: B04_0 Mask */ -#define LCD_PAL78_I0_Pos 15 /*!< LCD PAL78: I0 Position */ -#define LCD_PAL78_I0_Msk (0x01UL << LCD_PAL78_I0_Pos) /*!< LCD PAL78: I0 Mask */ -#define LCD_PAL78_R14_0_Pos 16 /*!< LCD PAL78: R14_0 Position */ -#define LCD_PAL78_R14_0_Msk (0x1fUL << LCD_PAL78_R14_0_Pos) /*!< LCD PAL78: R14_0 Mask */ -#define LCD_PAL78_G14_0_Pos 21 /*!< LCD PAL78: G14_0 Position */ -#define LCD_PAL78_G14_0_Msk (0x1fUL << LCD_PAL78_G14_0_Pos) /*!< LCD PAL78: G14_0 Mask */ -#define LCD_PAL78_B14_0_Pos 26 /*!< LCD PAL78: B14_0 Position */ -#define LCD_PAL78_B14_0_Msk (0x1fUL << LCD_PAL78_B14_0_Pos) /*!< LCD PAL78: B14_0 Mask */ -#define LCD_PAL78_I1_Pos 31 /*!< LCD PAL78: I1 Position */ -#define LCD_PAL78_I1_Msk (0x01UL << LCD_PAL78_I1_Pos) /*!< LCD PAL78: I1 Mask */ - -// ---------------------------------------- LCD_PAL79 ------------------------------------------- -#define LCD_PAL79_R04_0_Pos 0 /*!< LCD PAL79: R04_0 Position */ -#define LCD_PAL79_R04_0_Msk (0x1fUL << LCD_PAL79_R04_0_Pos) /*!< LCD PAL79: R04_0 Mask */ -#define LCD_PAL79_G04_0_Pos 5 /*!< LCD PAL79: G04_0 Position */ -#define LCD_PAL79_G04_0_Msk (0x1fUL << LCD_PAL79_G04_0_Pos) /*!< LCD PAL79: G04_0 Mask */ -#define LCD_PAL79_B04_0_Pos 10 /*!< LCD PAL79: B04_0 Position */ -#define LCD_PAL79_B04_0_Msk (0x1fUL << LCD_PAL79_B04_0_Pos) /*!< LCD PAL79: B04_0 Mask */ -#define LCD_PAL79_I0_Pos 15 /*!< LCD PAL79: I0 Position */ -#define LCD_PAL79_I0_Msk (0x01UL << LCD_PAL79_I0_Pos) /*!< LCD PAL79: I0 Mask */ -#define LCD_PAL79_R14_0_Pos 16 /*!< LCD PAL79: R14_0 Position */ -#define LCD_PAL79_R14_0_Msk (0x1fUL << LCD_PAL79_R14_0_Pos) /*!< LCD PAL79: R14_0 Mask */ -#define LCD_PAL79_G14_0_Pos 21 /*!< LCD PAL79: G14_0 Position */ -#define LCD_PAL79_G14_0_Msk (0x1fUL << LCD_PAL79_G14_0_Pos) /*!< LCD PAL79: G14_0 Mask */ -#define LCD_PAL79_B14_0_Pos 26 /*!< LCD PAL79: B14_0 Position */ -#define LCD_PAL79_B14_0_Msk (0x1fUL << LCD_PAL79_B14_0_Pos) /*!< LCD PAL79: B14_0 Mask */ -#define LCD_PAL79_I1_Pos 31 /*!< LCD PAL79: I1 Position */ -#define LCD_PAL79_I1_Msk (0x01UL << LCD_PAL79_I1_Pos) /*!< LCD PAL79: I1 Mask */ - -// ---------------------------------------- LCD_PAL80 ------------------------------------------- -#define LCD_PAL80_R04_0_Pos 0 /*!< LCD PAL80: R04_0 Position */ -#define LCD_PAL80_R04_0_Msk (0x1fUL << LCD_PAL80_R04_0_Pos) /*!< LCD PAL80: R04_0 Mask */ -#define LCD_PAL80_G04_0_Pos 5 /*!< LCD PAL80: G04_0 Position */ -#define LCD_PAL80_G04_0_Msk (0x1fUL << LCD_PAL80_G04_0_Pos) /*!< LCD PAL80: G04_0 Mask */ -#define LCD_PAL80_B04_0_Pos 10 /*!< LCD PAL80: B04_0 Position */ -#define LCD_PAL80_B04_0_Msk (0x1fUL << LCD_PAL80_B04_0_Pos) /*!< LCD PAL80: B04_0 Mask */ -#define LCD_PAL80_I0_Pos 15 /*!< LCD PAL80: I0 Position */ -#define LCD_PAL80_I0_Msk (0x01UL << LCD_PAL80_I0_Pos) /*!< LCD PAL80: I0 Mask */ -#define LCD_PAL80_R14_0_Pos 16 /*!< LCD PAL80: R14_0 Position */ -#define LCD_PAL80_R14_0_Msk (0x1fUL << LCD_PAL80_R14_0_Pos) /*!< LCD PAL80: R14_0 Mask */ -#define LCD_PAL80_G14_0_Pos 21 /*!< LCD PAL80: G14_0 Position */ -#define LCD_PAL80_G14_0_Msk (0x1fUL << LCD_PAL80_G14_0_Pos) /*!< LCD PAL80: G14_0 Mask */ -#define LCD_PAL80_B14_0_Pos 26 /*!< LCD PAL80: B14_0 Position */ -#define LCD_PAL80_B14_0_Msk (0x1fUL << LCD_PAL80_B14_0_Pos) /*!< LCD PAL80: B14_0 Mask */ -#define LCD_PAL80_I1_Pos 31 /*!< LCD PAL80: I1 Position */ -#define LCD_PAL80_I1_Msk (0x01UL << LCD_PAL80_I1_Pos) /*!< LCD PAL80: I1 Mask */ - -// ---------------------------------------- LCD_PAL81 ------------------------------------------- -#define LCD_PAL81_R04_0_Pos 0 /*!< LCD PAL81: R04_0 Position */ -#define LCD_PAL81_R04_0_Msk (0x1fUL << LCD_PAL81_R04_0_Pos) /*!< LCD PAL81: R04_0 Mask */ -#define LCD_PAL81_G04_0_Pos 5 /*!< LCD PAL81: G04_0 Position */ -#define LCD_PAL81_G04_0_Msk (0x1fUL << LCD_PAL81_G04_0_Pos) /*!< LCD PAL81: G04_0 Mask */ -#define LCD_PAL81_B04_0_Pos 10 /*!< LCD PAL81: B04_0 Position */ -#define LCD_PAL81_B04_0_Msk (0x1fUL << LCD_PAL81_B04_0_Pos) /*!< LCD PAL81: B04_0 Mask */ -#define LCD_PAL81_I0_Pos 15 /*!< LCD PAL81: I0 Position */ -#define LCD_PAL81_I0_Msk (0x01UL << LCD_PAL81_I0_Pos) /*!< LCD PAL81: I0 Mask */ -#define LCD_PAL81_R14_0_Pos 16 /*!< LCD PAL81: R14_0 Position */ -#define LCD_PAL81_R14_0_Msk (0x1fUL << LCD_PAL81_R14_0_Pos) /*!< LCD PAL81: R14_0 Mask */ -#define LCD_PAL81_G14_0_Pos 21 /*!< LCD PAL81: G14_0 Position */ -#define LCD_PAL81_G14_0_Msk (0x1fUL << LCD_PAL81_G14_0_Pos) /*!< LCD PAL81: G14_0 Mask */ -#define LCD_PAL81_B14_0_Pos 26 /*!< LCD PAL81: B14_0 Position */ -#define LCD_PAL81_B14_0_Msk (0x1fUL << LCD_PAL81_B14_0_Pos) /*!< LCD PAL81: B14_0 Mask */ -#define LCD_PAL81_I1_Pos 31 /*!< LCD PAL81: I1 Position */ -#define LCD_PAL81_I1_Msk (0x01UL << LCD_PAL81_I1_Pos) /*!< LCD PAL81: I1 Mask */ - -// ---------------------------------------- LCD_PAL82 ------------------------------------------- -#define LCD_PAL82_R04_0_Pos 0 /*!< LCD PAL82: R04_0 Position */ -#define LCD_PAL82_R04_0_Msk (0x1fUL << LCD_PAL82_R04_0_Pos) /*!< LCD PAL82: R04_0 Mask */ -#define LCD_PAL82_G04_0_Pos 5 /*!< LCD PAL82: G04_0 Position */ -#define LCD_PAL82_G04_0_Msk (0x1fUL << LCD_PAL82_G04_0_Pos) /*!< LCD PAL82: G04_0 Mask */ -#define LCD_PAL82_B04_0_Pos 10 /*!< LCD PAL82: B04_0 Position */ -#define LCD_PAL82_B04_0_Msk (0x1fUL << LCD_PAL82_B04_0_Pos) /*!< LCD PAL82: B04_0 Mask */ -#define LCD_PAL82_I0_Pos 15 /*!< LCD PAL82: I0 Position */ -#define LCD_PAL82_I0_Msk (0x01UL << LCD_PAL82_I0_Pos) /*!< LCD PAL82: I0 Mask */ -#define LCD_PAL82_R14_0_Pos 16 /*!< LCD PAL82: R14_0 Position */ -#define LCD_PAL82_R14_0_Msk (0x1fUL << LCD_PAL82_R14_0_Pos) /*!< LCD PAL82: R14_0 Mask */ -#define LCD_PAL82_G14_0_Pos 21 /*!< LCD PAL82: G14_0 Position */ -#define LCD_PAL82_G14_0_Msk (0x1fUL << LCD_PAL82_G14_0_Pos) /*!< LCD PAL82: G14_0 Mask */ -#define LCD_PAL82_B14_0_Pos 26 /*!< LCD PAL82: B14_0 Position */ -#define LCD_PAL82_B14_0_Msk (0x1fUL << LCD_PAL82_B14_0_Pos) /*!< LCD PAL82: B14_0 Mask */ -#define LCD_PAL82_I1_Pos 31 /*!< LCD PAL82: I1 Position */ -#define LCD_PAL82_I1_Msk (0x01UL << LCD_PAL82_I1_Pos) /*!< LCD PAL82: I1 Mask */ - -// ---------------------------------------- LCD_PAL83 ------------------------------------------- -#define LCD_PAL83_R04_0_Pos 0 /*!< LCD PAL83: R04_0 Position */ -#define LCD_PAL83_R04_0_Msk (0x1fUL << LCD_PAL83_R04_0_Pos) /*!< LCD PAL83: R04_0 Mask */ -#define LCD_PAL83_G04_0_Pos 5 /*!< LCD PAL83: G04_0 Position */ -#define LCD_PAL83_G04_0_Msk (0x1fUL << LCD_PAL83_G04_0_Pos) /*!< LCD PAL83: G04_0 Mask */ -#define LCD_PAL83_B04_0_Pos 10 /*!< LCD PAL83: B04_0 Position */ -#define LCD_PAL83_B04_0_Msk (0x1fUL << LCD_PAL83_B04_0_Pos) /*!< LCD PAL83: B04_0 Mask */ -#define LCD_PAL83_I0_Pos 15 /*!< LCD PAL83: I0 Position */ -#define LCD_PAL83_I0_Msk (0x01UL << LCD_PAL83_I0_Pos) /*!< LCD PAL83: I0 Mask */ -#define LCD_PAL83_R14_0_Pos 16 /*!< LCD PAL83: R14_0 Position */ -#define LCD_PAL83_R14_0_Msk (0x1fUL << LCD_PAL83_R14_0_Pos) /*!< LCD PAL83: R14_0 Mask */ -#define LCD_PAL83_G14_0_Pos 21 /*!< LCD PAL83: G14_0 Position */ -#define LCD_PAL83_G14_0_Msk (0x1fUL << LCD_PAL83_G14_0_Pos) /*!< LCD PAL83: G14_0 Mask */ -#define LCD_PAL83_B14_0_Pos 26 /*!< LCD PAL83: B14_0 Position */ -#define LCD_PAL83_B14_0_Msk (0x1fUL << LCD_PAL83_B14_0_Pos) /*!< LCD PAL83: B14_0 Mask */ -#define LCD_PAL83_I1_Pos 31 /*!< LCD PAL83: I1 Position */ -#define LCD_PAL83_I1_Msk (0x01UL << LCD_PAL83_I1_Pos) /*!< LCD PAL83: I1 Mask */ - -// ---------------------------------------- LCD_PAL84 ------------------------------------------- -#define LCD_PAL84_R04_0_Pos 0 /*!< LCD PAL84: R04_0 Position */ -#define LCD_PAL84_R04_0_Msk (0x1fUL << LCD_PAL84_R04_0_Pos) /*!< LCD PAL84: R04_0 Mask */ -#define LCD_PAL84_G04_0_Pos 5 /*!< LCD PAL84: G04_0 Position */ -#define LCD_PAL84_G04_0_Msk (0x1fUL << LCD_PAL84_G04_0_Pos) /*!< LCD PAL84: G04_0 Mask */ -#define LCD_PAL84_B04_0_Pos 10 /*!< LCD PAL84: B04_0 Position */ -#define LCD_PAL84_B04_0_Msk (0x1fUL << LCD_PAL84_B04_0_Pos) /*!< LCD PAL84: B04_0 Mask */ -#define LCD_PAL84_I0_Pos 15 /*!< LCD PAL84: I0 Position */ -#define LCD_PAL84_I0_Msk (0x01UL << LCD_PAL84_I0_Pos) /*!< LCD PAL84: I0 Mask */ -#define LCD_PAL84_R14_0_Pos 16 /*!< LCD PAL84: R14_0 Position */ -#define LCD_PAL84_R14_0_Msk (0x1fUL << LCD_PAL84_R14_0_Pos) /*!< LCD PAL84: R14_0 Mask */ -#define LCD_PAL84_G14_0_Pos 21 /*!< LCD PAL84: G14_0 Position */ -#define LCD_PAL84_G14_0_Msk (0x1fUL << LCD_PAL84_G14_0_Pos) /*!< LCD PAL84: G14_0 Mask */ -#define LCD_PAL84_B14_0_Pos 26 /*!< LCD PAL84: B14_0 Position */ -#define LCD_PAL84_B14_0_Msk (0x1fUL << LCD_PAL84_B14_0_Pos) /*!< LCD PAL84: B14_0 Mask */ -#define LCD_PAL84_I1_Pos 31 /*!< LCD PAL84: I1 Position */ -#define LCD_PAL84_I1_Msk (0x01UL << LCD_PAL84_I1_Pos) /*!< LCD PAL84: I1 Mask */ - -// ---------------------------------------- LCD_PAL85 ------------------------------------------- -#define LCD_PAL85_R04_0_Pos 0 /*!< LCD PAL85: R04_0 Position */ -#define LCD_PAL85_R04_0_Msk (0x1fUL << LCD_PAL85_R04_0_Pos) /*!< LCD PAL85: R04_0 Mask */ -#define LCD_PAL85_G04_0_Pos 5 /*!< LCD PAL85: G04_0 Position */ -#define LCD_PAL85_G04_0_Msk (0x1fUL << LCD_PAL85_G04_0_Pos) /*!< LCD PAL85: G04_0 Mask */ -#define LCD_PAL85_B04_0_Pos 10 /*!< LCD PAL85: B04_0 Position */ -#define LCD_PAL85_B04_0_Msk (0x1fUL << LCD_PAL85_B04_0_Pos) /*!< LCD PAL85: B04_0 Mask */ -#define LCD_PAL85_I0_Pos 15 /*!< LCD PAL85: I0 Position */ -#define LCD_PAL85_I0_Msk (0x01UL << LCD_PAL85_I0_Pos) /*!< LCD PAL85: I0 Mask */ -#define LCD_PAL85_R14_0_Pos 16 /*!< LCD PAL85: R14_0 Position */ -#define LCD_PAL85_R14_0_Msk (0x1fUL << LCD_PAL85_R14_0_Pos) /*!< LCD PAL85: R14_0 Mask */ -#define LCD_PAL85_G14_0_Pos 21 /*!< LCD PAL85: G14_0 Position */ -#define LCD_PAL85_G14_0_Msk (0x1fUL << LCD_PAL85_G14_0_Pos) /*!< LCD PAL85: G14_0 Mask */ -#define LCD_PAL85_B14_0_Pos 26 /*!< LCD PAL85: B14_0 Position */ -#define LCD_PAL85_B14_0_Msk (0x1fUL << LCD_PAL85_B14_0_Pos) /*!< LCD PAL85: B14_0 Mask */ -#define LCD_PAL85_I1_Pos 31 /*!< LCD PAL85: I1 Position */ -#define LCD_PAL85_I1_Msk (0x01UL << LCD_PAL85_I1_Pos) /*!< LCD PAL85: I1 Mask */ - -// ---------------------------------------- LCD_PAL86 ------------------------------------------- -#define LCD_PAL86_R04_0_Pos 0 /*!< LCD PAL86: R04_0 Position */ -#define LCD_PAL86_R04_0_Msk (0x1fUL << LCD_PAL86_R04_0_Pos) /*!< LCD PAL86: R04_0 Mask */ -#define LCD_PAL86_G04_0_Pos 5 /*!< LCD PAL86: G04_0 Position */ -#define LCD_PAL86_G04_0_Msk (0x1fUL << LCD_PAL86_G04_0_Pos) /*!< LCD PAL86: G04_0 Mask */ -#define LCD_PAL86_B04_0_Pos 10 /*!< LCD PAL86: B04_0 Position */ -#define LCD_PAL86_B04_0_Msk (0x1fUL << LCD_PAL86_B04_0_Pos) /*!< LCD PAL86: B04_0 Mask */ -#define LCD_PAL86_I0_Pos 15 /*!< LCD PAL86: I0 Position */ -#define LCD_PAL86_I0_Msk (0x01UL << LCD_PAL86_I0_Pos) /*!< LCD PAL86: I0 Mask */ -#define LCD_PAL86_R14_0_Pos 16 /*!< LCD PAL86: R14_0 Position */ -#define LCD_PAL86_R14_0_Msk (0x1fUL << LCD_PAL86_R14_0_Pos) /*!< LCD PAL86: R14_0 Mask */ -#define LCD_PAL86_G14_0_Pos 21 /*!< LCD PAL86: G14_0 Position */ -#define LCD_PAL86_G14_0_Msk (0x1fUL << LCD_PAL86_G14_0_Pos) /*!< LCD PAL86: G14_0 Mask */ -#define LCD_PAL86_B14_0_Pos 26 /*!< LCD PAL86: B14_0 Position */ -#define LCD_PAL86_B14_0_Msk (0x1fUL << LCD_PAL86_B14_0_Pos) /*!< LCD PAL86: B14_0 Mask */ -#define LCD_PAL86_I1_Pos 31 /*!< LCD PAL86: I1 Position */ -#define LCD_PAL86_I1_Msk (0x01UL << LCD_PAL86_I1_Pos) /*!< LCD PAL86: I1 Mask */ - -// ---------------------------------------- LCD_PAL87 ------------------------------------------- -#define LCD_PAL87_R04_0_Pos 0 /*!< LCD PAL87: R04_0 Position */ -#define LCD_PAL87_R04_0_Msk (0x1fUL << LCD_PAL87_R04_0_Pos) /*!< LCD PAL87: R04_0 Mask */ -#define LCD_PAL87_G04_0_Pos 5 /*!< LCD PAL87: G04_0 Position */ -#define LCD_PAL87_G04_0_Msk (0x1fUL << LCD_PAL87_G04_0_Pos) /*!< LCD PAL87: G04_0 Mask */ -#define LCD_PAL87_B04_0_Pos 10 /*!< LCD PAL87: B04_0 Position */ -#define LCD_PAL87_B04_0_Msk (0x1fUL << LCD_PAL87_B04_0_Pos) /*!< LCD PAL87: B04_0 Mask */ -#define LCD_PAL87_I0_Pos 15 /*!< LCD PAL87: I0 Position */ -#define LCD_PAL87_I0_Msk (0x01UL << LCD_PAL87_I0_Pos) /*!< LCD PAL87: I0 Mask */ -#define LCD_PAL87_R14_0_Pos 16 /*!< LCD PAL87: R14_0 Position */ -#define LCD_PAL87_R14_0_Msk (0x1fUL << LCD_PAL87_R14_0_Pos) /*!< LCD PAL87: R14_0 Mask */ -#define LCD_PAL87_G14_0_Pos 21 /*!< LCD PAL87: G14_0 Position */ -#define LCD_PAL87_G14_0_Msk (0x1fUL << LCD_PAL87_G14_0_Pos) /*!< LCD PAL87: G14_0 Mask */ -#define LCD_PAL87_B14_0_Pos 26 /*!< LCD PAL87: B14_0 Position */ -#define LCD_PAL87_B14_0_Msk (0x1fUL << LCD_PAL87_B14_0_Pos) /*!< LCD PAL87: B14_0 Mask */ -#define LCD_PAL87_I1_Pos 31 /*!< LCD PAL87: I1 Position */ -#define LCD_PAL87_I1_Msk (0x01UL << LCD_PAL87_I1_Pos) /*!< LCD PAL87: I1 Mask */ - -// ---------------------------------------- LCD_PAL88 ------------------------------------------- -#define LCD_PAL88_R04_0_Pos 0 /*!< LCD PAL88: R04_0 Position */ -#define LCD_PAL88_R04_0_Msk (0x1fUL << LCD_PAL88_R04_0_Pos) /*!< LCD PAL88: R04_0 Mask */ -#define LCD_PAL88_G04_0_Pos 5 /*!< LCD PAL88: G04_0 Position */ -#define LCD_PAL88_G04_0_Msk (0x1fUL << LCD_PAL88_G04_0_Pos) /*!< LCD PAL88: G04_0 Mask */ -#define LCD_PAL88_B04_0_Pos 10 /*!< LCD PAL88: B04_0 Position */ -#define LCD_PAL88_B04_0_Msk (0x1fUL << LCD_PAL88_B04_0_Pos) /*!< LCD PAL88: B04_0 Mask */ -#define LCD_PAL88_I0_Pos 15 /*!< LCD PAL88: I0 Position */ -#define LCD_PAL88_I0_Msk (0x01UL << LCD_PAL88_I0_Pos) /*!< LCD PAL88: I0 Mask */ -#define LCD_PAL88_R14_0_Pos 16 /*!< LCD PAL88: R14_0 Position */ -#define LCD_PAL88_R14_0_Msk (0x1fUL << LCD_PAL88_R14_0_Pos) /*!< LCD PAL88: R14_0 Mask */ -#define LCD_PAL88_G14_0_Pos 21 /*!< LCD PAL88: G14_0 Position */ -#define LCD_PAL88_G14_0_Msk (0x1fUL << LCD_PAL88_G14_0_Pos) /*!< LCD PAL88: G14_0 Mask */ -#define LCD_PAL88_B14_0_Pos 26 /*!< LCD PAL88: B14_0 Position */ -#define LCD_PAL88_B14_0_Msk (0x1fUL << LCD_PAL88_B14_0_Pos) /*!< LCD PAL88: B14_0 Mask */ -#define LCD_PAL88_I1_Pos 31 /*!< LCD PAL88: I1 Position */ -#define LCD_PAL88_I1_Msk (0x01UL << LCD_PAL88_I1_Pos) /*!< LCD PAL88: I1 Mask */ - -// ---------------------------------------- LCD_PAL89 ------------------------------------------- -#define LCD_PAL89_R04_0_Pos 0 /*!< LCD PAL89: R04_0 Position */ -#define LCD_PAL89_R04_0_Msk (0x1fUL << LCD_PAL89_R04_0_Pos) /*!< LCD PAL89: R04_0 Mask */ -#define LCD_PAL89_G04_0_Pos 5 /*!< LCD PAL89: G04_0 Position */ -#define LCD_PAL89_G04_0_Msk (0x1fUL << LCD_PAL89_G04_0_Pos) /*!< LCD PAL89: G04_0 Mask */ -#define LCD_PAL89_B04_0_Pos 10 /*!< LCD PAL89: B04_0 Position */ -#define LCD_PAL89_B04_0_Msk (0x1fUL << LCD_PAL89_B04_0_Pos) /*!< LCD PAL89: B04_0 Mask */ -#define LCD_PAL89_I0_Pos 15 /*!< LCD PAL89: I0 Position */ -#define LCD_PAL89_I0_Msk (0x01UL << LCD_PAL89_I0_Pos) /*!< LCD PAL89: I0 Mask */ -#define LCD_PAL89_R14_0_Pos 16 /*!< LCD PAL89: R14_0 Position */ -#define LCD_PAL89_R14_0_Msk (0x1fUL << LCD_PAL89_R14_0_Pos) /*!< LCD PAL89: R14_0 Mask */ -#define LCD_PAL89_G14_0_Pos 21 /*!< LCD PAL89: G14_0 Position */ -#define LCD_PAL89_G14_0_Msk (0x1fUL << LCD_PAL89_G14_0_Pos) /*!< LCD PAL89: G14_0 Mask */ -#define LCD_PAL89_B14_0_Pos 26 /*!< LCD PAL89: B14_0 Position */ -#define LCD_PAL89_B14_0_Msk (0x1fUL << LCD_PAL89_B14_0_Pos) /*!< LCD PAL89: B14_0 Mask */ -#define LCD_PAL89_I1_Pos 31 /*!< LCD PAL89: I1 Position */ -#define LCD_PAL89_I1_Msk (0x01UL << LCD_PAL89_I1_Pos) /*!< LCD PAL89: I1 Mask */ - -// ---------------------------------------- LCD_PAL90 ------------------------------------------- -#define LCD_PAL90_R04_0_Pos 0 /*!< LCD PAL90: R04_0 Position */ -#define LCD_PAL90_R04_0_Msk (0x1fUL << LCD_PAL90_R04_0_Pos) /*!< LCD PAL90: R04_0 Mask */ -#define LCD_PAL90_G04_0_Pos 5 /*!< LCD PAL90: G04_0 Position */ -#define LCD_PAL90_G04_0_Msk (0x1fUL << LCD_PAL90_G04_0_Pos) /*!< LCD PAL90: G04_0 Mask */ -#define LCD_PAL90_B04_0_Pos 10 /*!< LCD PAL90: B04_0 Position */ -#define LCD_PAL90_B04_0_Msk (0x1fUL << LCD_PAL90_B04_0_Pos) /*!< LCD PAL90: B04_0 Mask */ -#define LCD_PAL90_I0_Pos 15 /*!< LCD PAL90: I0 Position */ -#define LCD_PAL90_I0_Msk (0x01UL << LCD_PAL90_I0_Pos) /*!< LCD PAL90: I0 Mask */ -#define LCD_PAL90_R14_0_Pos 16 /*!< LCD PAL90: R14_0 Position */ -#define LCD_PAL90_R14_0_Msk (0x1fUL << LCD_PAL90_R14_0_Pos) /*!< LCD PAL90: R14_0 Mask */ -#define LCD_PAL90_G14_0_Pos 21 /*!< LCD PAL90: G14_0 Position */ -#define LCD_PAL90_G14_0_Msk (0x1fUL << LCD_PAL90_G14_0_Pos) /*!< LCD PAL90: G14_0 Mask */ -#define LCD_PAL90_B14_0_Pos 26 /*!< LCD PAL90: B14_0 Position */ -#define LCD_PAL90_B14_0_Msk (0x1fUL << LCD_PAL90_B14_0_Pos) /*!< LCD PAL90: B14_0 Mask */ -#define LCD_PAL90_I1_Pos 31 /*!< LCD PAL90: I1 Position */ -#define LCD_PAL90_I1_Msk (0x01UL << LCD_PAL90_I1_Pos) /*!< LCD PAL90: I1 Mask */ - -// ---------------------------------------- LCD_PAL91 ------------------------------------------- -#define LCD_PAL91_R04_0_Pos 0 /*!< LCD PAL91: R04_0 Position */ -#define LCD_PAL91_R04_0_Msk (0x1fUL << LCD_PAL91_R04_0_Pos) /*!< LCD PAL91: R04_0 Mask */ -#define LCD_PAL91_G04_0_Pos 5 /*!< LCD PAL91: G04_0 Position */ -#define LCD_PAL91_G04_0_Msk (0x1fUL << LCD_PAL91_G04_0_Pos) /*!< LCD PAL91: G04_0 Mask */ -#define LCD_PAL91_B04_0_Pos 10 /*!< LCD PAL91: B04_0 Position */ -#define LCD_PAL91_B04_0_Msk (0x1fUL << LCD_PAL91_B04_0_Pos) /*!< LCD PAL91: B04_0 Mask */ -#define LCD_PAL91_I0_Pos 15 /*!< LCD PAL91: I0 Position */ -#define LCD_PAL91_I0_Msk (0x01UL << LCD_PAL91_I0_Pos) /*!< LCD PAL91: I0 Mask */ -#define LCD_PAL91_R14_0_Pos 16 /*!< LCD PAL91: R14_0 Position */ -#define LCD_PAL91_R14_0_Msk (0x1fUL << LCD_PAL91_R14_0_Pos) /*!< LCD PAL91: R14_0 Mask */ -#define LCD_PAL91_G14_0_Pos 21 /*!< LCD PAL91: G14_0 Position */ -#define LCD_PAL91_G14_0_Msk (0x1fUL << LCD_PAL91_G14_0_Pos) /*!< LCD PAL91: G14_0 Mask */ -#define LCD_PAL91_B14_0_Pos 26 /*!< LCD PAL91: B14_0 Position */ -#define LCD_PAL91_B14_0_Msk (0x1fUL << LCD_PAL91_B14_0_Pos) /*!< LCD PAL91: B14_0 Mask */ -#define LCD_PAL91_I1_Pos 31 /*!< LCD PAL91: I1 Position */ -#define LCD_PAL91_I1_Msk (0x01UL << LCD_PAL91_I1_Pos) /*!< LCD PAL91: I1 Mask */ - -// ---------------------------------------- LCD_PAL92 ------------------------------------------- -#define LCD_PAL92_R04_0_Pos 0 /*!< LCD PAL92: R04_0 Position */ -#define LCD_PAL92_R04_0_Msk (0x1fUL << LCD_PAL92_R04_0_Pos) /*!< LCD PAL92: R04_0 Mask */ -#define LCD_PAL92_G04_0_Pos 5 /*!< LCD PAL92: G04_0 Position */ -#define LCD_PAL92_G04_0_Msk (0x1fUL << LCD_PAL92_G04_0_Pos) /*!< LCD PAL92: G04_0 Mask */ -#define LCD_PAL92_B04_0_Pos 10 /*!< LCD PAL92: B04_0 Position */ -#define LCD_PAL92_B04_0_Msk (0x1fUL << LCD_PAL92_B04_0_Pos) /*!< LCD PAL92: B04_0 Mask */ -#define LCD_PAL92_I0_Pos 15 /*!< LCD PAL92: I0 Position */ -#define LCD_PAL92_I0_Msk (0x01UL << LCD_PAL92_I0_Pos) /*!< LCD PAL92: I0 Mask */ -#define LCD_PAL92_R14_0_Pos 16 /*!< LCD PAL92: R14_0 Position */ -#define LCD_PAL92_R14_0_Msk (0x1fUL << LCD_PAL92_R14_0_Pos) /*!< LCD PAL92: R14_0 Mask */ -#define LCD_PAL92_G14_0_Pos 21 /*!< LCD PAL92: G14_0 Position */ -#define LCD_PAL92_G14_0_Msk (0x1fUL << LCD_PAL92_G14_0_Pos) /*!< LCD PAL92: G14_0 Mask */ -#define LCD_PAL92_B14_0_Pos 26 /*!< LCD PAL92: B14_0 Position */ -#define LCD_PAL92_B14_0_Msk (0x1fUL << LCD_PAL92_B14_0_Pos) /*!< LCD PAL92: B14_0 Mask */ -#define LCD_PAL92_I1_Pos 31 /*!< LCD PAL92: I1 Position */ -#define LCD_PAL92_I1_Msk (0x01UL << LCD_PAL92_I1_Pos) /*!< LCD PAL92: I1 Mask */ - -// ---------------------------------------- LCD_PAL93 ------------------------------------------- -#define LCD_PAL93_R04_0_Pos 0 /*!< LCD PAL93: R04_0 Position */ -#define LCD_PAL93_R04_0_Msk (0x1fUL << LCD_PAL93_R04_0_Pos) /*!< LCD PAL93: R04_0 Mask */ -#define LCD_PAL93_G04_0_Pos 5 /*!< LCD PAL93: G04_0 Position */ -#define LCD_PAL93_G04_0_Msk (0x1fUL << LCD_PAL93_G04_0_Pos) /*!< LCD PAL93: G04_0 Mask */ -#define LCD_PAL93_B04_0_Pos 10 /*!< LCD PAL93: B04_0 Position */ -#define LCD_PAL93_B04_0_Msk (0x1fUL << LCD_PAL93_B04_0_Pos) /*!< LCD PAL93: B04_0 Mask */ -#define LCD_PAL93_I0_Pos 15 /*!< LCD PAL93: I0 Position */ -#define LCD_PAL93_I0_Msk (0x01UL << LCD_PAL93_I0_Pos) /*!< LCD PAL93: I0 Mask */ -#define LCD_PAL93_R14_0_Pos 16 /*!< LCD PAL93: R14_0 Position */ -#define LCD_PAL93_R14_0_Msk (0x1fUL << LCD_PAL93_R14_0_Pos) /*!< LCD PAL93: R14_0 Mask */ -#define LCD_PAL93_G14_0_Pos 21 /*!< LCD PAL93: G14_0 Position */ -#define LCD_PAL93_G14_0_Msk (0x1fUL << LCD_PAL93_G14_0_Pos) /*!< LCD PAL93: G14_0 Mask */ -#define LCD_PAL93_B14_0_Pos 26 /*!< LCD PAL93: B14_0 Position */ -#define LCD_PAL93_B14_0_Msk (0x1fUL << LCD_PAL93_B14_0_Pos) /*!< LCD PAL93: B14_0 Mask */ -#define LCD_PAL93_I1_Pos 31 /*!< LCD PAL93: I1 Position */ -#define LCD_PAL93_I1_Msk (0x01UL << LCD_PAL93_I1_Pos) /*!< LCD PAL93: I1 Mask */ - -// ---------------------------------------- LCD_PAL94 ------------------------------------------- -#define LCD_PAL94_R04_0_Pos 0 /*!< LCD PAL94: R04_0 Position */ -#define LCD_PAL94_R04_0_Msk (0x1fUL << LCD_PAL94_R04_0_Pos) /*!< LCD PAL94: R04_0 Mask */ -#define LCD_PAL94_G04_0_Pos 5 /*!< LCD PAL94: G04_0 Position */ -#define LCD_PAL94_G04_0_Msk (0x1fUL << LCD_PAL94_G04_0_Pos) /*!< LCD PAL94: G04_0 Mask */ -#define LCD_PAL94_B04_0_Pos 10 /*!< LCD PAL94: B04_0 Position */ -#define LCD_PAL94_B04_0_Msk (0x1fUL << LCD_PAL94_B04_0_Pos) /*!< LCD PAL94: B04_0 Mask */ -#define LCD_PAL94_I0_Pos 15 /*!< LCD PAL94: I0 Position */ -#define LCD_PAL94_I0_Msk (0x01UL << LCD_PAL94_I0_Pos) /*!< LCD PAL94: I0 Mask */ -#define LCD_PAL94_R14_0_Pos 16 /*!< LCD PAL94: R14_0 Position */ -#define LCD_PAL94_R14_0_Msk (0x1fUL << LCD_PAL94_R14_0_Pos) /*!< LCD PAL94: R14_0 Mask */ -#define LCD_PAL94_G14_0_Pos 21 /*!< LCD PAL94: G14_0 Position */ -#define LCD_PAL94_G14_0_Msk (0x1fUL << LCD_PAL94_G14_0_Pos) /*!< LCD PAL94: G14_0 Mask */ -#define LCD_PAL94_B14_0_Pos 26 /*!< LCD PAL94: B14_0 Position */ -#define LCD_PAL94_B14_0_Msk (0x1fUL << LCD_PAL94_B14_0_Pos) /*!< LCD PAL94: B14_0 Mask */ -#define LCD_PAL94_I1_Pos 31 /*!< LCD PAL94: I1 Position */ -#define LCD_PAL94_I1_Msk (0x01UL << LCD_PAL94_I1_Pos) /*!< LCD PAL94: I1 Mask */ - -// ---------------------------------------- LCD_PAL95 ------------------------------------------- -#define LCD_PAL95_R04_0_Pos 0 /*!< LCD PAL95: R04_0 Position */ -#define LCD_PAL95_R04_0_Msk (0x1fUL << LCD_PAL95_R04_0_Pos) /*!< LCD PAL95: R04_0 Mask */ -#define LCD_PAL95_G04_0_Pos 5 /*!< LCD PAL95: G04_0 Position */ -#define LCD_PAL95_G04_0_Msk (0x1fUL << LCD_PAL95_G04_0_Pos) /*!< LCD PAL95: G04_0 Mask */ -#define LCD_PAL95_B04_0_Pos 10 /*!< LCD PAL95: B04_0 Position */ -#define LCD_PAL95_B04_0_Msk (0x1fUL << LCD_PAL95_B04_0_Pos) /*!< LCD PAL95: B04_0 Mask */ -#define LCD_PAL95_I0_Pos 15 /*!< LCD PAL95: I0 Position */ -#define LCD_PAL95_I0_Msk (0x01UL << LCD_PAL95_I0_Pos) /*!< LCD PAL95: I0 Mask */ -#define LCD_PAL95_R14_0_Pos 16 /*!< LCD PAL95: R14_0 Position */ -#define LCD_PAL95_R14_0_Msk (0x1fUL << LCD_PAL95_R14_0_Pos) /*!< LCD PAL95: R14_0 Mask */ -#define LCD_PAL95_G14_0_Pos 21 /*!< LCD PAL95: G14_0 Position */ -#define LCD_PAL95_G14_0_Msk (0x1fUL << LCD_PAL95_G14_0_Pos) /*!< LCD PAL95: G14_0 Mask */ -#define LCD_PAL95_B14_0_Pos 26 /*!< LCD PAL95: B14_0 Position */ -#define LCD_PAL95_B14_0_Msk (0x1fUL << LCD_PAL95_B14_0_Pos) /*!< LCD PAL95: B14_0 Mask */ -#define LCD_PAL95_I1_Pos 31 /*!< LCD PAL95: I1 Position */ -#define LCD_PAL95_I1_Msk (0x01UL << LCD_PAL95_I1_Pos) /*!< LCD PAL95: I1 Mask */ - -// ---------------------------------------- LCD_PAL96 ------------------------------------------- -#define LCD_PAL96_R04_0_Pos 0 /*!< LCD PAL96: R04_0 Position */ -#define LCD_PAL96_R04_0_Msk (0x1fUL << LCD_PAL96_R04_0_Pos) /*!< LCD PAL96: R04_0 Mask */ -#define LCD_PAL96_G04_0_Pos 5 /*!< LCD PAL96: G04_0 Position */ -#define LCD_PAL96_G04_0_Msk (0x1fUL << LCD_PAL96_G04_0_Pos) /*!< LCD PAL96: G04_0 Mask */ -#define LCD_PAL96_B04_0_Pos 10 /*!< LCD PAL96: B04_0 Position */ -#define LCD_PAL96_B04_0_Msk (0x1fUL << LCD_PAL96_B04_0_Pos) /*!< LCD PAL96: B04_0 Mask */ -#define LCD_PAL96_I0_Pos 15 /*!< LCD PAL96: I0 Position */ -#define LCD_PAL96_I0_Msk (0x01UL << LCD_PAL96_I0_Pos) /*!< LCD PAL96: I0 Mask */ -#define LCD_PAL96_R14_0_Pos 16 /*!< LCD PAL96: R14_0 Position */ -#define LCD_PAL96_R14_0_Msk (0x1fUL << LCD_PAL96_R14_0_Pos) /*!< LCD PAL96: R14_0 Mask */ -#define LCD_PAL96_G14_0_Pos 21 /*!< LCD PAL96: G14_0 Position */ -#define LCD_PAL96_G14_0_Msk (0x1fUL << LCD_PAL96_G14_0_Pos) /*!< LCD PAL96: G14_0 Mask */ -#define LCD_PAL96_B14_0_Pos 26 /*!< LCD PAL96: B14_0 Position */ -#define LCD_PAL96_B14_0_Msk (0x1fUL << LCD_PAL96_B14_0_Pos) /*!< LCD PAL96: B14_0 Mask */ -#define LCD_PAL96_I1_Pos 31 /*!< LCD PAL96: I1 Position */ -#define LCD_PAL96_I1_Msk (0x01UL << LCD_PAL96_I1_Pos) /*!< LCD PAL96: I1 Mask */ - -// ---------------------------------------- LCD_PAL97 ------------------------------------------- -#define LCD_PAL97_R04_0_Pos 0 /*!< LCD PAL97: R04_0 Position */ -#define LCD_PAL97_R04_0_Msk (0x1fUL << LCD_PAL97_R04_0_Pos) /*!< LCD PAL97: R04_0 Mask */ -#define LCD_PAL97_G04_0_Pos 5 /*!< LCD PAL97: G04_0 Position */ -#define LCD_PAL97_G04_0_Msk (0x1fUL << LCD_PAL97_G04_0_Pos) /*!< LCD PAL97: G04_0 Mask */ -#define LCD_PAL97_B04_0_Pos 10 /*!< LCD PAL97: B04_0 Position */ -#define LCD_PAL97_B04_0_Msk (0x1fUL << LCD_PAL97_B04_0_Pos) /*!< LCD PAL97: B04_0 Mask */ -#define LCD_PAL97_I0_Pos 15 /*!< LCD PAL97: I0 Position */ -#define LCD_PAL97_I0_Msk (0x01UL << LCD_PAL97_I0_Pos) /*!< LCD PAL97: I0 Mask */ -#define LCD_PAL97_R14_0_Pos 16 /*!< LCD PAL97: R14_0 Position */ -#define LCD_PAL97_R14_0_Msk (0x1fUL << LCD_PAL97_R14_0_Pos) /*!< LCD PAL97: R14_0 Mask */ -#define LCD_PAL97_G14_0_Pos 21 /*!< LCD PAL97: G14_0 Position */ -#define LCD_PAL97_G14_0_Msk (0x1fUL << LCD_PAL97_G14_0_Pos) /*!< LCD PAL97: G14_0 Mask */ -#define LCD_PAL97_B14_0_Pos 26 /*!< LCD PAL97: B14_0 Position */ -#define LCD_PAL97_B14_0_Msk (0x1fUL << LCD_PAL97_B14_0_Pos) /*!< LCD PAL97: B14_0 Mask */ -#define LCD_PAL97_I1_Pos 31 /*!< LCD PAL97: I1 Position */ -#define LCD_PAL97_I1_Msk (0x01UL << LCD_PAL97_I1_Pos) /*!< LCD PAL97: I1 Mask */ - -// ---------------------------------------- LCD_PAL98 ------------------------------------------- -#define LCD_PAL98_R04_0_Pos 0 /*!< LCD PAL98: R04_0 Position */ -#define LCD_PAL98_R04_0_Msk (0x1fUL << LCD_PAL98_R04_0_Pos) /*!< LCD PAL98: R04_0 Mask */ -#define LCD_PAL98_G04_0_Pos 5 /*!< LCD PAL98: G04_0 Position */ -#define LCD_PAL98_G04_0_Msk (0x1fUL << LCD_PAL98_G04_0_Pos) /*!< LCD PAL98: G04_0 Mask */ -#define LCD_PAL98_B04_0_Pos 10 /*!< LCD PAL98: B04_0 Position */ -#define LCD_PAL98_B04_0_Msk (0x1fUL << LCD_PAL98_B04_0_Pos) /*!< LCD PAL98: B04_0 Mask */ -#define LCD_PAL98_I0_Pos 15 /*!< LCD PAL98: I0 Position */ -#define LCD_PAL98_I0_Msk (0x01UL << LCD_PAL98_I0_Pos) /*!< LCD PAL98: I0 Mask */ -#define LCD_PAL98_R14_0_Pos 16 /*!< LCD PAL98: R14_0 Position */ -#define LCD_PAL98_R14_0_Msk (0x1fUL << LCD_PAL98_R14_0_Pos) /*!< LCD PAL98: R14_0 Mask */ -#define LCD_PAL98_G14_0_Pos 21 /*!< LCD PAL98: G14_0 Position */ -#define LCD_PAL98_G14_0_Msk (0x1fUL << LCD_PAL98_G14_0_Pos) /*!< LCD PAL98: G14_0 Mask */ -#define LCD_PAL98_B14_0_Pos 26 /*!< LCD PAL98: B14_0 Position */ -#define LCD_PAL98_B14_0_Msk (0x1fUL << LCD_PAL98_B14_0_Pos) /*!< LCD PAL98: B14_0 Mask */ -#define LCD_PAL98_I1_Pos 31 /*!< LCD PAL98: I1 Position */ -#define LCD_PAL98_I1_Msk (0x01UL << LCD_PAL98_I1_Pos) /*!< LCD PAL98: I1 Mask */ - -// ---------------------------------------- LCD_PAL99 ------------------------------------------- -#define LCD_PAL99_R04_0_Pos 0 /*!< LCD PAL99: R04_0 Position */ -#define LCD_PAL99_R04_0_Msk (0x1fUL << LCD_PAL99_R04_0_Pos) /*!< LCD PAL99: R04_0 Mask */ -#define LCD_PAL99_G04_0_Pos 5 /*!< LCD PAL99: G04_0 Position */ -#define LCD_PAL99_G04_0_Msk (0x1fUL << LCD_PAL99_G04_0_Pos) /*!< LCD PAL99: G04_0 Mask */ -#define LCD_PAL99_B04_0_Pos 10 /*!< LCD PAL99: B04_0 Position */ -#define LCD_PAL99_B04_0_Msk (0x1fUL << LCD_PAL99_B04_0_Pos) /*!< LCD PAL99: B04_0 Mask */ -#define LCD_PAL99_I0_Pos 15 /*!< LCD PAL99: I0 Position */ -#define LCD_PAL99_I0_Msk (0x01UL << LCD_PAL99_I0_Pos) /*!< LCD PAL99: I0 Mask */ -#define LCD_PAL99_R14_0_Pos 16 /*!< LCD PAL99: R14_0 Position */ -#define LCD_PAL99_R14_0_Msk (0x1fUL << LCD_PAL99_R14_0_Pos) /*!< LCD PAL99: R14_0 Mask */ -#define LCD_PAL99_G14_0_Pos 21 /*!< LCD PAL99: G14_0 Position */ -#define LCD_PAL99_G14_0_Msk (0x1fUL << LCD_PAL99_G14_0_Pos) /*!< LCD PAL99: G14_0 Mask */ -#define LCD_PAL99_B14_0_Pos 26 /*!< LCD PAL99: B14_0 Position */ -#define LCD_PAL99_B14_0_Msk (0x1fUL << LCD_PAL99_B14_0_Pos) /*!< LCD PAL99: B14_0 Mask */ -#define LCD_PAL99_I1_Pos 31 /*!< LCD PAL99: I1 Position */ -#define LCD_PAL99_I1_Msk (0x01UL << LCD_PAL99_I1_Pos) /*!< LCD PAL99: I1 Mask */ - -// --------------------------------------- LCD_PAL100 ------------------------------------------- -#define LCD_PAL100_R04_0_Pos 0 /*!< LCD PAL100: R04_0 Position */ -#define LCD_PAL100_R04_0_Msk (0x1fUL << LCD_PAL100_R04_0_Pos) /*!< LCD PAL100: R04_0 Mask */ -#define LCD_PAL100_G04_0_Pos 5 /*!< LCD PAL100: G04_0 Position */ -#define LCD_PAL100_G04_0_Msk (0x1fUL << LCD_PAL100_G04_0_Pos) /*!< LCD PAL100: G04_0 Mask */ -#define LCD_PAL100_B04_0_Pos 10 /*!< LCD PAL100: B04_0 Position */ -#define LCD_PAL100_B04_0_Msk (0x1fUL << LCD_PAL100_B04_0_Pos) /*!< LCD PAL100: B04_0 Mask */ -#define LCD_PAL100_I0_Pos 15 /*!< LCD PAL100: I0 Position */ -#define LCD_PAL100_I0_Msk (0x01UL << LCD_PAL100_I0_Pos) /*!< LCD PAL100: I0 Mask */ -#define LCD_PAL100_R14_0_Pos 16 /*!< LCD PAL100: R14_0 Position */ -#define LCD_PAL100_R14_0_Msk (0x1fUL << LCD_PAL100_R14_0_Pos) /*!< LCD PAL100: R14_0 Mask */ -#define LCD_PAL100_G14_0_Pos 21 /*!< LCD PAL100: G14_0 Position */ -#define LCD_PAL100_G14_0_Msk (0x1fUL << LCD_PAL100_G14_0_Pos) /*!< LCD PAL100: G14_0 Mask */ -#define LCD_PAL100_B14_0_Pos 26 /*!< LCD PAL100: B14_0 Position */ -#define LCD_PAL100_B14_0_Msk (0x1fUL << LCD_PAL100_B14_0_Pos) /*!< LCD PAL100: B14_0 Mask */ -#define LCD_PAL100_I1_Pos 31 /*!< LCD PAL100: I1 Position */ -#define LCD_PAL100_I1_Msk (0x01UL << LCD_PAL100_I1_Pos) /*!< LCD PAL100: I1 Mask */ - -// --------------------------------------- LCD_PAL101 ------------------------------------------- -#define LCD_PAL101_R04_0_Pos 0 /*!< LCD PAL101: R04_0 Position */ -#define LCD_PAL101_R04_0_Msk (0x1fUL << LCD_PAL101_R04_0_Pos) /*!< LCD PAL101: R04_0 Mask */ -#define LCD_PAL101_G04_0_Pos 5 /*!< LCD PAL101: G04_0 Position */ -#define LCD_PAL101_G04_0_Msk (0x1fUL << LCD_PAL101_G04_0_Pos) /*!< LCD PAL101: G04_0 Mask */ -#define LCD_PAL101_B04_0_Pos 10 /*!< LCD PAL101: B04_0 Position */ -#define LCD_PAL101_B04_0_Msk (0x1fUL << LCD_PAL101_B04_0_Pos) /*!< LCD PAL101: B04_0 Mask */ -#define LCD_PAL101_I0_Pos 15 /*!< LCD PAL101: I0 Position */ -#define LCD_PAL101_I0_Msk (0x01UL << LCD_PAL101_I0_Pos) /*!< LCD PAL101: I0 Mask */ -#define LCD_PAL101_R14_0_Pos 16 /*!< LCD PAL101: R14_0 Position */ -#define LCD_PAL101_R14_0_Msk (0x1fUL << LCD_PAL101_R14_0_Pos) /*!< LCD PAL101: R14_0 Mask */ -#define LCD_PAL101_G14_0_Pos 21 /*!< LCD PAL101: G14_0 Position */ -#define LCD_PAL101_G14_0_Msk (0x1fUL << LCD_PAL101_G14_0_Pos) /*!< LCD PAL101: G14_0 Mask */ -#define LCD_PAL101_B14_0_Pos 26 /*!< LCD PAL101: B14_0 Position */ -#define LCD_PAL101_B14_0_Msk (0x1fUL << LCD_PAL101_B14_0_Pos) /*!< LCD PAL101: B14_0 Mask */ -#define LCD_PAL101_I1_Pos 31 /*!< LCD PAL101: I1 Position */ -#define LCD_PAL101_I1_Msk (0x01UL << LCD_PAL101_I1_Pos) /*!< LCD PAL101: I1 Mask */ - -// --------------------------------------- LCD_PAL102 ------------------------------------------- -#define LCD_PAL102_R04_0_Pos 0 /*!< LCD PAL102: R04_0 Position */ -#define LCD_PAL102_R04_0_Msk (0x1fUL << LCD_PAL102_R04_0_Pos) /*!< LCD PAL102: R04_0 Mask */ -#define LCD_PAL102_G04_0_Pos 5 /*!< LCD PAL102: G04_0 Position */ -#define LCD_PAL102_G04_0_Msk (0x1fUL << LCD_PAL102_G04_0_Pos) /*!< LCD PAL102: G04_0 Mask */ -#define LCD_PAL102_B04_0_Pos 10 /*!< LCD PAL102: B04_0 Position */ -#define LCD_PAL102_B04_0_Msk (0x1fUL << LCD_PAL102_B04_0_Pos) /*!< LCD PAL102: B04_0 Mask */ -#define LCD_PAL102_I0_Pos 15 /*!< LCD PAL102: I0 Position */ -#define LCD_PAL102_I0_Msk (0x01UL << LCD_PAL102_I0_Pos) /*!< LCD PAL102: I0 Mask */ -#define LCD_PAL102_R14_0_Pos 16 /*!< LCD PAL102: R14_0 Position */ -#define LCD_PAL102_R14_0_Msk (0x1fUL << LCD_PAL102_R14_0_Pos) /*!< LCD PAL102: R14_0 Mask */ -#define LCD_PAL102_G14_0_Pos 21 /*!< LCD PAL102: G14_0 Position */ -#define LCD_PAL102_G14_0_Msk (0x1fUL << LCD_PAL102_G14_0_Pos) /*!< LCD PAL102: G14_0 Mask */ -#define LCD_PAL102_B14_0_Pos 26 /*!< LCD PAL102: B14_0 Position */ -#define LCD_PAL102_B14_0_Msk (0x1fUL << LCD_PAL102_B14_0_Pos) /*!< LCD PAL102: B14_0 Mask */ -#define LCD_PAL102_I1_Pos 31 /*!< LCD PAL102: I1 Position */ -#define LCD_PAL102_I1_Msk (0x01UL << LCD_PAL102_I1_Pos) /*!< LCD PAL102: I1 Mask */ - -// --------------------------------------- LCD_PAL103 ------------------------------------------- -#define LCD_PAL103_R04_0_Pos 0 /*!< LCD PAL103: R04_0 Position */ -#define LCD_PAL103_R04_0_Msk (0x1fUL << LCD_PAL103_R04_0_Pos) /*!< LCD PAL103: R04_0 Mask */ -#define LCD_PAL103_G04_0_Pos 5 /*!< LCD PAL103: G04_0 Position */ -#define LCD_PAL103_G04_0_Msk (0x1fUL << LCD_PAL103_G04_0_Pos) /*!< LCD PAL103: G04_0 Mask */ -#define LCD_PAL103_B04_0_Pos 10 /*!< LCD PAL103: B04_0 Position */ -#define LCD_PAL103_B04_0_Msk (0x1fUL << LCD_PAL103_B04_0_Pos) /*!< LCD PAL103: B04_0 Mask */ -#define LCD_PAL103_I0_Pos 15 /*!< LCD PAL103: I0 Position */ -#define LCD_PAL103_I0_Msk (0x01UL << LCD_PAL103_I0_Pos) /*!< LCD PAL103: I0 Mask */ -#define LCD_PAL103_R14_0_Pos 16 /*!< LCD PAL103: R14_0 Position */ -#define LCD_PAL103_R14_0_Msk (0x1fUL << LCD_PAL103_R14_0_Pos) /*!< LCD PAL103: R14_0 Mask */ -#define LCD_PAL103_G14_0_Pos 21 /*!< LCD PAL103: G14_0 Position */ -#define LCD_PAL103_G14_0_Msk (0x1fUL << LCD_PAL103_G14_0_Pos) /*!< LCD PAL103: G14_0 Mask */ -#define LCD_PAL103_B14_0_Pos 26 /*!< LCD PAL103: B14_0 Position */ -#define LCD_PAL103_B14_0_Msk (0x1fUL << LCD_PAL103_B14_0_Pos) /*!< LCD PAL103: B14_0 Mask */ -#define LCD_PAL103_I1_Pos 31 /*!< LCD PAL103: I1 Position */ -#define LCD_PAL103_I1_Msk (0x01UL << LCD_PAL103_I1_Pos) /*!< LCD PAL103: I1 Mask */ - -// --------------------------------------- LCD_PAL104 ------------------------------------------- -#define LCD_PAL104_R04_0_Pos 0 /*!< LCD PAL104: R04_0 Position */ -#define LCD_PAL104_R04_0_Msk (0x1fUL << LCD_PAL104_R04_0_Pos) /*!< LCD PAL104: R04_0 Mask */ -#define LCD_PAL104_G04_0_Pos 5 /*!< LCD PAL104: G04_0 Position */ -#define LCD_PAL104_G04_0_Msk (0x1fUL << LCD_PAL104_G04_0_Pos) /*!< LCD PAL104: G04_0 Mask */ -#define LCD_PAL104_B04_0_Pos 10 /*!< LCD PAL104: B04_0 Position */ -#define LCD_PAL104_B04_0_Msk (0x1fUL << LCD_PAL104_B04_0_Pos) /*!< LCD PAL104: B04_0 Mask */ -#define LCD_PAL104_I0_Pos 15 /*!< LCD PAL104: I0 Position */ -#define LCD_PAL104_I0_Msk (0x01UL << LCD_PAL104_I0_Pos) /*!< LCD PAL104: I0 Mask */ -#define LCD_PAL104_R14_0_Pos 16 /*!< LCD PAL104: R14_0 Position */ -#define LCD_PAL104_R14_0_Msk (0x1fUL << LCD_PAL104_R14_0_Pos) /*!< LCD PAL104: R14_0 Mask */ -#define LCD_PAL104_G14_0_Pos 21 /*!< LCD PAL104: G14_0 Position */ -#define LCD_PAL104_G14_0_Msk (0x1fUL << LCD_PAL104_G14_0_Pos) /*!< LCD PAL104: G14_0 Mask */ -#define LCD_PAL104_B14_0_Pos 26 /*!< LCD PAL104: B14_0 Position */ -#define LCD_PAL104_B14_0_Msk (0x1fUL << LCD_PAL104_B14_0_Pos) /*!< LCD PAL104: B14_0 Mask */ -#define LCD_PAL104_I1_Pos 31 /*!< LCD PAL104: I1 Position */ -#define LCD_PAL104_I1_Msk (0x01UL << LCD_PAL104_I1_Pos) /*!< LCD PAL104: I1 Mask */ - -// --------------------------------------- LCD_PAL105 ------------------------------------------- -#define LCD_PAL105_R04_0_Pos 0 /*!< LCD PAL105: R04_0 Position */ -#define LCD_PAL105_R04_0_Msk (0x1fUL << LCD_PAL105_R04_0_Pos) /*!< LCD PAL105: R04_0 Mask */ -#define LCD_PAL105_G04_0_Pos 5 /*!< LCD PAL105: G04_0 Position */ -#define LCD_PAL105_G04_0_Msk (0x1fUL << LCD_PAL105_G04_0_Pos) /*!< LCD PAL105: G04_0 Mask */ -#define LCD_PAL105_B04_0_Pos 10 /*!< LCD PAL105: B04_0 Position */ -#define LCD_PAL105_B04_0_Msk (0x1fUL << LCD_PAL105_B04_0_Pos) /*!< LCD PAL105: B04_0 Mask */ -#define LCD_PAL105_I0_Pos 15 /*!< LCD PAL105: I0 Position */ -#define LCD_PAL105_I0_Msk (0x01UL << LCD_PAL105_I0_Pos) /*!< LCD PAL105: I0 Mask */ -#define LCD_PAL105_R14_0_Pos 16 /*!< LCD PAL105: R14_0 Position */ -#define LCD_PAL105_R14_0_Msk (0x1fUL << LCD_PAL105_R14_0_Pos) /*!< LCD PAL105: R14_0 Mask */ -#define LCD_PAL105_G14_0_Pos 21 /*!< LCD PAL105: G14_0 Position */ -#define LCD_PAL105_G14_0_Msk (0x1fUL << LCD_PAL105_G14_0_Pos) /*!< LCD PAL105: G14_0 Mask */ -#define LCD_PAL105_B14_0_Pos 26 /*!< LCD PAL105: B14_0 Position */ -#define LCD_PAL105_B14_0_Msk (0x1fUL << LCD_PAL105_B14_0_Pos) /*!< LCD PAL105: B14_0 Mask */ -#define LCD_PAL105_I1_Pos 31 /*!< LCD PAL105: I1 Position */ -#define LCD_PAL105_I1_Msk (0x01UL << LCD_PAL105_I1_Pos) /*!< LCD PAL105: I1 Mask */ - -// --------------------------------------- LCD_PAL106 ------------------------------------------- -#define LCD_PAL106_R04_0_Pos 0 /*!< LCD PAL106: R04_0 Position */ -#define LCD_PAL106_R04_0_Msk (0x1fUL << LCD_PAL106_R04_0_Pos) /*!< LCD PAL106: R04_0 Mask */ -#define LCD_PAL106_G04_0_Pos 5 /*!< LCD PAL106: G04_0 Position */ -#define LCD_PAL106_G04_0_Msk (0x1fUL << LCD_PAL106_G04_0_Pos) /*!< LCD PAL106: G04_0 Mask */ -#define LCD_PAL106_B04_0_Pos 10 /*!< LCD PAL106: B04_0 Position */ -#define LCD_PAL106_B04_0_Msk (0x1fUL << LCD_PAL106_B04_0_Pos) /*!< LCD PAL106: B04_0 Mask */ -#define LCD_PAL106_I0_Pos 15 /*!< LCD PAL106: I0 Position */ -#define LCD_PAL106_I0_Msk (0x01UL << LCD_PAL106_I0_Pos) /*!< LCD PAL106: I0 Mask */ -#define LCD_PAL106_R14_0_Pos 16 /*!< LCD PAL106: R14_0 Position */ -#define LCD_PAL106_R14_0_Msk (0x1fUL << LCD_PAL106_R14_0_Pos) /*!< LCD PAL106: R14_0 Mask */ -#define LCD_PAL106_G14_0_Pos 21 /*!< LCD PAL106: G14_0 Position */ -#define LCD_PAL106_G14_0_Msk (0x1fUL << LCD_PAL106_G14_0_Pos) /*!< LCD PAL106: G14_0 Mask */ -#define LCD_PAL106_B14_0_Pos 26 /*!< LCD PAL106: B14_0 Position */ -#define LCD_PAL106_B14_0_Msk (0x1fUL << LCD_PAL106_B14_0_Pos) /*!< LCD PAL106: B14_0 Mask */ -#define LCD_PAL106_I1_Pos 31 /*!< LCD PAL106: I1 Position */ -#define LCD_PAL106_I1_Msk (0x01UL << LCD_PAL106_I1_Pos) /*!< LCD PAL106: I1 Mask */ - -// --------------------------------------- LCD_PAL107 ------------------------------------------- -#define LCD_PAL107_R04_0_Pos 0 /*!< LCD PAL107: R04_0 Position */ -#define LCD_PAL107_R04_0_Msk (0x1fUL << LCD_PAL107_R04_0_Pos) /*!< LCD PAL107: R04_0 Mask */ -#define LCD_PAL107_G04_0_Pos 5 /*!< LCD PAL107: G04_0 Position */ -#define LCD_PAL107_G04_0_Msk (0x1fUL << LCD_PAL107_G04_0_Pos) /*!< LCD PAL107: G04_0 Mask */ -#define LCD_PAL107_B04_0_Pos 10 /*!< LCD PAL107: B04_0 Position */ -#define LCD_PAL107_B04_0_Msk (0x1fUL << LCD_PAL107_B04_0_Pos) /*!< LCD PAL107: B04_0 Mask */ -#define LCD_PAL107_I0_Pos 15 /*!< LCD PAL107: I0 Position */ -#define LCD_PAL107_I0_Msk (0x01UL << LCD_PAL107_I0_Pos) /*!< LCD PAL107: I0 Mask */ -#define LCD_PAL107_R14_0_Pos 16 /*!< LCD PAL107: R14_0 Position */ -#define LCD_PAL107_R14_0_Msk (0x1fUL << LCD_PAL107_R14_0_Pos) /*!< LCD PAL107: R14_0 Mask */ -#define LCD_PAL107_G14_0_Pos 21 /*!< LCD PAL107: G14_0 Position */ -#define LCD_PAL107_G14_0_Msk (0x1fUL << LCD_PAL107_G14_0_Pos) /*!< LCD PAL107: G14_0 Mask */ -#define LCD_PAL107_B14_0_Pos 26 /*!< LCD PAL107: B14_0 Position */ -#define LCD_PAL107_B14_0_Msk (0x1fUL << LCD_PAL107_B14_0_Pos) /*!< LCD PAL107: B14_0 Mask */ -#define LCD_PAL107_I1_Pos 31 /*!< LCD PAL107: I1 Position */ -#define LCD_PAL107_I1_Msk (0x01UL << LCD_PAL107_I1_Pos) /*!< LCD PAL107: I1 Mask */ - -// --------------------------------------- LCD_PAL108 ------------------------------------------- -#define LCD_PAL108_R04_0_Pos 0 /*!< LCD PAL108: R04_0 Position */ -#define LCD_PAL108_R04_0_Msk (0x1fUL << LCD_PAL108_R04_0_Pos) /*!< LCD PAL108: R04_0 Mask */ -#define LCD_PAL108_G04_0_Pos 5 /*!< LCD PAL108: G04_0 Position */ -#define LCD_PAL108_G04_0_Msk (0x1fUL << LCD_PAL108_G04_0_Pos) /*!< LCD PAL108: G04_0 Mask */ -#define LCD_PAL108_B04_0_Pos 10 /*!< LCD PAL108: B04_0 Position */ -#define LCD_PAL108_B04_0_Msk (0x1fUL << LCD_PAL108_B04_0_Pos) /*!< LCD PAL108: B04_0 Mask */ -#define LCD_PAL108_I0_Pos 15 /*!< LCD PAL108: I0 Position */ -#define LCD_PAL108_I0_Msk (0x01UL << LCD_PAL108_I0_Pos) /*!< LCD PAL108: I0 Mask */ -#define LCD_PAL108_R14_0_Pos 16 /*!< LCD PAL108: R14_0 Position */ -#define LCD_PAL108_R14_0_Msk (0x1fUL << LCD_PAL108_R14_0_Pos) /*!< LCD PAL108: R14_0 Mask */ -#define LCD_PAL108_G14_0_Pos 21 /*!< LCD PAL108: G14_0 Position */ -#define LCD_PAL108_G14_0_Msk (0x1fUL << LCD_PAL108_G14_0_Pos) /*!< LCD PAL108: G14_0 Mask */ -#define LCD_PAL108_B14_0_Pos 26 /*!< LCD PAL108: B14_0 Position */ -#define LCD_PAL108_B14_0_Msk (0x1fUL << LCD_PAL108_B14_0_Pos) /*!< LCD PAL108: B14_0 Mask */ -#define LCD_PAL108_I1_Pos 31 /*!< LCD PAL108: I1 Position */ -#define LCD_PAL108_I1_Msk (0x01UL << LCD_PAL108_I1_Pos) /*!< LCD PAL108: I1 Mask */ - -// --------------------------------------- LCD_PAL109 ------------------------------------------- -#define LCD_PAL109_R04_0_Pos 0 /*!< LCD PAL109: R04_0 Position */ -#define LCD_PAL109_R04_0_Msk (0x1fUL << LCD_PAL109_R04_0_Pos) /*!< LCD PAL109: R04_0 Mask */ -#define LCD_PAL109_G04_0_Pos 5 /*!< LCD PAL109: G04_0 Position */ -#define LCD_PAL109_G04_0_Msk (0x1fUL << LCD_PAL109_G04_0_Pos) /*!< LCD PAL109: G04_0 Mask */ -#define LCD_PAL109_B04_0_Pos 10 /*!< LCD PAL109: B04_0 Position */ -#define LCD_PAL109_B04_0_Msk (0x1fUL << LCD_PAL109_B04_0_Pos) /*!< LCD PAL109: B04_0 Mask */ -#define LCD_PAL109_I0_Pos 15 /*!< LCD PAL109: I0 Position */ -#define LCD_PAL109_I0_Msk (0x01UL << LCD_PAL109_I0_Pos) /*!< LCD PAL109: I0 Mask */ -#define LCD_PAL109_R14_0_Pos 16 /*!< LCD PAL109: R14_0 Position */ -#define LCD_PAL109_R14_0_Msk (0x1fUL << LCD_PAL109_R14_0_Pos) /*!< LCD PAL109: R14_0 Mask */ -#define LCD_PAL109_G14_0_Pos 21 /*!< LCD PAL109: G14_0 Position */ -#define LCD_PAL109_G14_0_Msk (0x1fUL << LCD_PAL109_G14_0_Pos) /*!< LCD PAL109: G14_0 Mask */ -#define LCD_PAL109_B14_0_Pos 26 /*!< LCD PAL109: B14_0 Position */ -#define LCD_PAL109_B14_0_Msk (0x1fUL << LCD_PAL109_B14_0_Pos) /*!< LCD PAL109: B14_0 Mask */ -#define LCD_PAL109_I1_Pos 31 /*!< LCD PAL109: I1 Position */ -#define LCD_PAL109_I1_Msk (0x01UL << LCD_PAL109_I1_Pos) /*!< LCD PAL109: I1 Mask */ - -// --------------------------------------- LCD_PAL110 ------------------------------------------- -#define LCD_PAL110_R04_0_Pos 0 /*!< LCD PAL110: R04_0 Position */ -#define LCD_PAL110_R04_0_Msk (0x1fUL << LCD_PAL110_R04_0_Pos) /*!< LCD PAL110: R04_0 Mask */ -#define LCD_PAL110_G04_0_Pos 5 /*!< LCD PAL110: G04_0 Position */ -#define LCD_PAL110_G04_0_Msk (0x1fUL << LCD_PAL110_G04_0_Pos) /*!< LCD PAL110: G04_0 Mask */ -#define LCD_PAL110_B04_0_Pos 10 /*!< LCD PAL110: B04_0 Position */ -#define LCD_PAL110_B04_0_Msk (0x1fUL << LCD_PAL110_B04_0_Pos) /*!< LCD PAL110: B04_0 Mask */ -#define LCD_PAL110_I0_Pos 15 /*!< LCD PAL110: I0 Position */ -#define LCD_PAL110_I0_Msk (0x01UL << LCD_PAL110_I0_Pos) /*!< LCD PAL110: I0 Mask */ -#define LCD_PAL110_R14_0_Pos 16 /*!< LCD PAL110: R14_0 Position */ -#define LCD_PAL110_R14_0_Msk (0x1fUL << LCD_PAL110_R14_0_Pos) /*!< LCD PAL110: R14_0 Mask */ -#define LCD_PAL110_G14_0_Pos 21 /*!< LCD PAL110: G14_0 Position */ -#define LCD_PAL110_G14_0_Msk (0x1fUL << LCD_PAL110_G14_0_Pos) /*!< LCD PAL110: G14_0 Mask */ -#define LCD_PAL110_B14_0_Pos 26 /*!< LCD PAL110: B14_0 Position */ -#define LCD_PAL110_B14_0_Msk (0x1fUL << LCD_PAL110_B14_0_Pos) /*!< LCD PAL110: B14_0 Mask */ -#define LCD_PAL110_I1_Pos 31 /*!< LCD PAL110: I1 Position */ -#define LCD_PAL110_I1_Msk (0x01UL << LCD_PAL110_I1_Pos) /*!< LCD PAL110: I1 Mask */ - -// --------------------------------------- LCD_PAL111 ------------------------------------------- -#define LCD_PAL111_R04_0_Pos 0 /*!< LCD PAL111: R04_0 Position */ -#define LCD_PAL111_R04_0_Msk (0x1fUL << LCD_PAL111_R04_0_Pos) /*!< LCD PAL111: R04_0 Mask */ -#define LCD_PAL111_G04_0_Pos 5 /*!< LCD PAL111: G04_0 Position */ -#define LCD_PAL111_G04_0_Msk (0x1fUL << LCD_PAL111_G04_0_Pos) /*!< LCD PAL111: G04_0 Mask */ -#define LCD_PAL111_B04_0_Pos 10 /*!< LCD PAL111: B04_0 Position */ -#define LCD_PAL111_B04_0_Msk (0x1fUL << LCD_PAL111_B04_0_Pos) /*!< LCD PAL111: B04_0 Mask */ -#define LCD_PAL111_I0_Pos 15 /*!< LCD PAL111: I0 Position */ -#define LCD_PAL111_I0_Msk (0x01UL << LCD_PAL111_I0_Pos) /*!< LCD PAL111: I0 Mask */ -#define LCD_PAL111_R14_0_Pos 16 /*!< LCD PAL111: R14_0 Position */ -#define LCD_PAL111_R14_0_Msk (0x1fUL << LCD_PAL111_R14_0_Pos) /*!< LCD PAL111: R14_0 Mask */ -#define LCD_PAL111_G14_0_Pos 21 /*!< LCD PAL111: G14_0 Position */ -#define LCD_PAL111_G14_0_Msk (0x1fUL << LCD_PAL111_G14_0_Pos) /*!< LCD PAL111: G14_0 Mask */ -#define LCD_PAL111_B14_0_Pos 26 /*!< LCD PAL111: B14_0 Position */ -#define LCD_PAL111_B14_0_Msk (0x1fUL << LCD_PAL111_B14_0_Pos) /*!< LCD PAL111: B14_0 Mask */ -#define LCD_PAL111_I1_Pos 31 /*!< LCD PAL111: I1 Position */ -#define LCD_PAL111_I1_Msk (0x01UL << LCD_PAL111_I1_Pos) /*!< LCD PAL111: I1 Mask */ - -// --------------------------------------- LCD_PAL112 ------------------------------------------- -#define LCD_PAL112_R04_0_Pos 0 /*!< LCD PAL112: R04_0 Position */ -#define LCD_PAL112_R04_0_Msk (0x1fUL << LCD_PAL112_R04_0_Pos) /*!< LCD PAL112: R04_0 Mask */ -#define LCD_PAL112_G04_0_Pos 5 /*!< LCD PAL112: G04_0 Position */ -#define LCD_PAL112_G04_0_Msk (0x1fUL << LCD_PAL112_G04_0_Pos) /*!< LCD PAL112: G04_0 Mask */ -#define LCD_PAL112_B04_0_Pos 10 /*!< LCD PAL112: B04_0 Position */ -#define LCD_PAL112_B04_0_Msk (0x1fUL << LCD_PAL112_B04_0_Pos) /*!< LCD PAL112: B04_0 Mask */ -#define LCD_PAL112_I0_Pos 15 /*!< LCD PAL112: I0 Position */ -#define LCD_PAL112_I0_Msk (0x01UL << LCD_PAL112_I0_Pos) /*!< LCD PAL112: I0 Mask */ -#define LCD_PAL112_R14_0_Pos 16 /*!< LCD PAL112: R14_0 Position */ -#define LCD_PAL112_R14_0_Msk (0x1fUL << LCD_PAL112_R14_0_Pos) /*!< LCD PAL112: R14_0 Mask */ -#define LCD_PAL112_G14_0_Pos 21 /*!< LCD PAL112: G14_0 Position */ -#define LCD_PAL112_G14_0_Msk (0x1fUL << LCD_PAL112_G14_0_Pos) /*!< LCD PAL112: G14_0 Mask */ -#define LCD_PAL112_B14_0_Pos 26 /*!< LCD PAL112: B14_0 Position */ -#define LCD_PAL112_B14_0_Msk (0x1fUL << LCD_PAL112_B14_0_Pos) /*!< LCD PAL112: B14_0 Mask */ -#define LCD_PAL112_I1_Pos 31 /*!< LCD PAL112: I1 Position */ -#define LCD_PAL112_I1_Msk (0x01UL << LCD_PAL112_I1_Pos) /*!< LCD PAL112: I1 Mask */ - -// --------------------------------------- LCD_PAL113 ------------------------------------------- -#define LCD_PAL113_R04_0_Pos 0 /*!< LCD PAL113: R04_0 Position */ -#define LCD_PAL113_R04_0_Msk (0x1fUL << LCD_PAL113_R04_0_Pos) /*!< LCD PAL113: R04_0 Mask */ -#define LCD_PAL113_G04_0_Pos 5 /*!< LCD PAL113: G04_0 Position */ -#define LCD_PAL113_G04_0_Msk (0x1fUL << LCD_PAL113_G04_0_Pos) /*!< LCD PAL113: G04_0 Mask */ -#define LCD_PAL113_B04_0_Pos 10 /*!< LCD PAL113: B04_0 Position */ -#define LCD_PAL113_B04_0_Msk (0x1fUL << LCD_PAL113_B04_0_Pos) /*!< LCD PAL113: B04_0 Mask */ -#define LCD_PAL113_I0_Pos 15 /*!< LCD PAL113: I0 Position */ -#define LCD_PAL113_I0_Msk (0x01UL << LCD_PAL113_I0_Pos) /*!< LCD PAL113: I0 Mask */ -#define LCD_PAL113_R14_0_Pos 16 /*!< LCD PAL113: R14_0 Position */ -#define LCD_PAL113_R14_0_Msk (0x1fUL << LCD_PAL113_R14_0_Pos) /*!< LCD PAL113: R14_0 Mask */ -#define LCD_PAL113_G14_0_Pos 21 /*!< LCD PAL113: G14_0 Position */ -#define LCD_PAL113_G14_0_Msk (0x1fUL << LCD_PAL113_G14_0_Pos) /*!< LCD PAL113: G14_0 Mask */ -#define LCD_PAL113_B14_0_Pos 26 /*!< LCD PAL113: B14_0 Position */ -#define LCD_PAL113_B14_0_Msk (0x1fUL << LCD_PAL113_B14_0_Pos) /*!< LCD PAL113: B14_0 Mask */ -#define LCD_PAL113_I1_Pos 31 /*!< LCD PAL113: I1 Position */ -#define LCD_PAL113_I1_Msk (0x01UL << LCD_PAL113_I1_Pos) /*!< LCD PAL113: I1 Mask */ - -// --------------------------------------- LCD_PAL114 ------------------------------------------- -#define LCD_PAL114_R04_0_Pos 0 /*!< LCD PAL114: R04_0 Position */ -#define LCD_PAL114_R04_0_Msk (0x1fUL << LCD_PAL114_R04_0_Pos) /*!< LCD PAL114: R04_0 Mask */ -#define LCD_PAL114_G04_0_Pos 5 /*!< LCD PAL114: G04_0 Position */ -#define LCD_PAL114_G04_0_Msk (0x1fUL << LCD_PAL114_G04_0_Pos) /*!< LCD PAL114: G04_0 Mask */ -#define LCD_PAL114_B04_0_Pos 10 /*!< LCD PAL114: B04_0 Position */ -#define LCD_PAL114_B04_0_Msk (0x1fUL << LCD_PAL114_B04_0_Pos) /*!< LCD PAL114: B04_0 Mask */ -#define LCD_PAL114_I0_Pos 15 /*!< LCD PAL114: I0 Position */ -#define LCD_PAL114_I0_Msk (0x01UL << LCD_PAL114_I0_Pos) /*!< LCD PAL114: I0 Mask */ -#define LCD_PAL114_R14_0_Pos 16 /*!< LCD PAL114: R14_0 Position */ -#define LCD_PAL114_R14_0_Msk (0x1fUL << LCD_PAL114_R14_0_Pos) /*!< LCD PAL114: R14_0 Mask */ -#define LCD_PAL114_G14_0_Pos 21 /*!< LCD PAL114: G14_0 Position */ -#define LCD_PAL114_G14_0_Msk (0x1fUL << LCD_PAL114_G14_0_Pos) /*!< LCD PAL114: G14_0 Mask */ -#define LCD_PAL114_B14_0_Pos 26 /*!< LCD PAL114: B14_0 Position */ -#define LCD_PAL114_B14_0_Msk (0x1fUL << LCD_PAL114_B14_0_Pos) /*!< LCD PAL114: B14_0 Mask */ -#define LCD_PAL114_I1_Pos 31 /*!< LCD PAL114: I1 Position */ -#define LCD_PAL114_I1_Msk (0x01UL << LCD_PAL114_I1_Pos) /*!< LCD PAL114: I1 Mask */ - -// --------------------------------------- LCD_PAL115 ------------------------------------------- -#define LCD_PAL115_R04_0_Pos 0 /*!< LCD PAL115: R04_0 Position */ -#define LCD_PAL115_R04_0_Msk (0x1fUL << LCD_PAL115_R04_0_Pos) /*!< LCD PAL115: R04_0 Mask */ -#define LCD_PAL115_G04_0_Pos 5 /*!< LCD PAL115: G04_0 Position */ -#define LCD_PAL115_G04_0_Msk (0x1fUL << LCD_PAL115_G04_0_Pos) /*!< LCD PAL115: G04_0 Mask */ -#define LCD_PAL115_B04_0_Pos 10 /*!< LCD PAL115: B04_0 Position */ -#define LCD_PAL115_B04_0_Msk (0x1fUL << LCD_PAL115_B04_0_Pos) /*!< LCD PAL115: B04_0 Mask */ -#define LCD_PAL115_I0_Pos 15 /*!< LCD PAL115: I0 Position */ -#define LCD_PAL115_I0_Msk (0x01UL << LCD_PAL115_I0_Pos) /*!< LCD PAL115: I0 Mask */ -#define LCD_PAL115_R14_0_Pos 16 /*!< LCD PAL115: R14_0 Position */ -#define LCD_PAL115_R14_0_Msk (0x1fUL << LCD_PAL115_R14_0_Pos) /*!< LCD PAL115: R14_0 Mask */ -#define LCD_PAL115_G14_0_Pos 21 /*!< LCD PAL115: G14_0 Position */ -#define LCD_PAL115_G14_0_Msk (0x1fUL << LCD_PAL115_G14_0_Pos) /*!< LCD PAL115: G14_0 Mask */ -#define LCD_PAL115_B14_0_Pos 26 /*!< LCD PAL115: B14_0 Position */ -#define LCD_PAL115_B14_0_Msk (0x1fUL << LCD_PAL115_B14_0_Pos) /*!< LCD PAL115: B14_0 Mask */ -#define LCD_PAL115_I1_Pos 31 /*!< LCD PAL115: I1 Position */ -#define LCD_PAL115_I1_Msk (0x01UL << LCD_PAL115_I1_Pos) /*!< LCD PAL115: I1 Mask */ - -// --------------------------------------- LCD_PAL116 ------------------------------------------- -#define LCD_PAL116_R04_0_Pos 0 /*!< LCD PAL116: R04_0 Position */ -#define LCD_PAL116_R04_0_Msk (0x1fUL << LCD_PAL116_R04_0_Pos) /*!< LCD PAL116: R04_0 Mask */ -#define LCD_PAL116_G04_0_Pos 5 /*!< LCD PAL116: G04_0 Position */ -#define LCD_PAL116_G04_0_Msk (0x1fUL << LCD_PAL116_G04_0_Pos) /*!< LCD PAL116: G04_0 Mask */ -#define LCD_PAL116_B04_0_Pos 10 /*!< LCD PAL116: B04_0 Position */ -#define LCD_PAL116_B04_0_Msk (0x1fUL << LCD_PAL116_B04_0_Pos) /*!< LCD PAL116: B04_0 Mask */ -#define LCD_PAL116_I0_Pos 15 /*!< LCD PAL116: I0 Position */ -#define LCD_PAL116_I0_Msk (0x01UL << LCD_PAL116_I0_Pos) /*!< LCD PAL116: I0 Mask */ -#define LCD_PAL116_R14_0_Pos 16 /*!< LCD PAL116: R14_0 Position */ -#define LCD_PAL116_R14_0_Msk (0x1fUL << LCD_PAL116_R14_0_Pos) /*!< LCD PAL116: R14_0 Mask */ -#define LCD_PAL116_G14_0_Pos 21 /*!< LCD PAL116: G14_0 Position */ -#define LCD_PAL116_G14_0_Msk (0x1fUL << LCD_PAL116_G14_0_Pos) /*!< LCD PAL116: G14_0 Mask */ -#define LCD_PAL116_B14_0_Pos 26 /*!< LCD PAL116: B14_0 Position */ -#define LCD_PAL116_B14_0_Msk (0x1fUL << LCD_PAL116_B14_0_Pos) /*!< LCD PAL116: B14_0 Mask */ -#define LCD_PAL116_I1_Pos 31 /*!< LCD PAL116: I1 Position */ -#define LCD_PAL116_I1_Msk (0x01UL << LCD_PAL116_I1_Pos) /*!< LCD PAL116: I1 Mask */ - -// --------------------------------------- LCD_PAL117 ------------------------------------------- -#define LCD_PAL117_R04_0_Pos 0 /*!< LCD PAL117: R04_0 Position */ -#define LCD_PAL117_R04_0_Msk (0x1fUL << LCD_PAL117_R04_0_Pos) /*!< LCD PAL117: R04_0 Mask */ -#define LCD_PAL117_G04_0_Pos 5 /*!< LCD PAL117: G04_0 Position */ -#define LCD_PAL117_G04_0_Msk (0x1fUL << LCD_PAL117_G04_0_Pos) /*!< LCD PAL117: G04_0 Mask */ -#define LCD_PAL117_B04_0_Pos 10 /*!< LCD PAL117: B04_0 Position */ -#define LCD_PAL117_B04_0_Msk (0x1fUL << LCD_PAL117_B04_0_Pos) /*!< LCD PAL117: B04_0 Mask */ -#define LCD_PAL117_I0_Pos 15 /*!< LCD PAL117: I0 Position */ -#define LCD_PAL117_I0_Msk (0x01UL << LCD_PAL117_I0_Pos) /*!< LCD PAL117: I0 Mask */ -#define LCD_PAL117_R14_0_Pos 16 /*!< LCD PAL117: R14_0 Position */ -#define LCD_PAL117_R14_0_Msk (0x1fUL << LCD_PAL117_R14_0_Pos) /*!< LCD PAL117: R14_0 Mask */ -#define LCD_PAL117_G14_0_Pos 21 /*!< LCD PAL117: G14_0 Position */ -#define LCD_PAL117_G14_0_Msk (0x1fUL << LCD_PAL117_G14_0_Pos) /*!< LCD PAL117: G14_0 Mask */ -#define LCD_PAL117_B14_0_Pos 26 /*!< LCD PAL117: B14_0 Position */ -#define LCD_PAL117_B14_0_Msk (0x1fUL << LCD_PAL117_B14_0_Pos) /*!< LCD PAL117: B14_0 Mask */ -#define LCD_PAL117_I1_Pos 31 /*!< LCD PAL117: I1 Position */ -#define LCD_PAL117_I1_Msk (0x01UL << LCD_PAL117_I1_Pos) /*!< LCD PAL117: I1 Mask */ - -// --------------------------------------- LCD_PAL118 ------------------------------------------- -#define LCD_PAL118_R04_0_Pos 0 /*!< LCD PAL118: R04_0 Position */ -#define LCD_PAL118_R04_0_Msk (0x1fUL << LCD_PAL118_R04_0_Pos) /*!< LCD PAL118: R04_0 Mask */ -#define LCD_PAL118_G04_0_Pos 5 /*!< LCD PAL118: G04_0 Position */ -#define LCD_PAL118_G04_0_Msk (0x1fUL << LCD_PAL118_G04_0_Pos) /*!< LCD PAL118: G04_0 Mask */ -#define LCD_PAL118_B04_0_Pos 10 /*!< LCD PAL118: B04_0 Position */ -#define LCD_PAL118_B04_0_Msk (0x1fUL << LCD_PAL118_B04_0_Pos) /*!< LCD PAL118: B04_0 Mask */ -#define LCD_PAL118_I0_Pos 15 /*!< LCD PAL118: I0 Position */ -#define LCD_PAL118_I0_Msk (0x01UL << LCD_PAL118_I0_Pos) /*!< LCD PAL118: I0 Mask */ -#define LCD_PAL118_R14_0_Pos 16 /*!< LCD PAL118: R14_0 Position */ -#define LCD_PAL118_R14_0_Msk (0x1fUL << LCD_PAL118_R14_0_Pos) /*!< LCD PAL118: R14_0 Mask */ -#define LCD_PAL118_G14_0_Pos 21 /*!< LCD PAL118: G14_0 Position */ -#define LCD_PAL118_G14_0_Msk (0x1fUL << LCD_PAL118_G14_0_Pos) /*!< LCD PAL118: G14_0 Mask */ -#define LCD_PAL118_B14_0_Pos 26 /*!< LCD PAL118: B14_0 Position */ -#define LCD_PAL118_B14_0_Msk (0x1fUL << LCD_PAL118_B14_0_Pos) /*!< LCD PAL118: B14_0 Mask */ -#define LCD_PAL118_I1_Pos 31 /*!< LCD PAL118: I1 Position */ -#define LCD_PAL118_I1_Msk (0x01UL << LCD_PAL118_I1_Pos) /*!< LCD PAL118: I1 Mask */ - -// --------------------------------------- LCD_PAL119 ------------------------------------------- -#define LCD_PAL119_R04_0_Pos 0 /*!< LCD PAL119: R04_0 Position */ -#define LCD_PAL119_R04_0_Msk (0x1fUL << LCD_PAL119_R04_0_Pos) /*!< LCD PAL119: R04_0 Mask */ -#define LCD_PAL119_G04_0_Pos 5 /*!< LCD PAL119: G04_0 Position */ -#define LCD_PAL119_G04_0_Msk (0x1fUL << LCD_PAL119_G04_0_Pos) /*!< LCD PAL119: G04_0 Mask */ -#define LCD_PAL119_B04_0_Pos 10 /*!< LCD PAL119: B04_0 Position */ -#define LCD_PAL119_B04_0_Msk (0x1fUL << LCD_PAL119_B04_0_Pos) /*!< LCD PAL119: B04_0 Mask */ -#define LCD_PAL119_I0_Pos 15 /*!< LCD PAL119: I0 Position */ -#define LCD_PAL119_I0_Msk (0x01UL << LCD_PAL119_I0_Pos) /*!< LCD PAL119: I0 Mask */ -#define LCD_PAL119_R14_0_Pos 16 /*!< LCD PAL119: R14_0 Position */ -#define LCD_PAL119_R14_0_Msk (0x1fUL << LCD_PAL119_R14_0_Pos) /*!< LCD PAL119: R14_0 Mask */ -#define LCD_PAL119_G14_0_Pos 21 /*!< LCD PAL119: G14_0 Position */ -#define LCD_PAL119_G14_0_Msk (0x1fUL << LCD_PAL119_G14_0_Pos) /*!< LCD PAL119: G14_0 Mask */ -#define LCD_PAL119_B14_0_Pos 26 /*!< LCD PAL119: B14_0 Position */ -#define LCD_PAL119_B14_0_Msk (0x1fUL << LCD_PAL119_B14_0_Pos) /*!< LCD PAL119: B14_0 Mask */ -#define LCD_PAL119_I1_Pos 31 /*!< LCD PAL119: I1 Position */ -#define LCD_PAL119_I1_Msk (0x01UL << LCD_PAL119_I1_Pos) /*!< LCD PAL119: I1 Mask */ - -// --------------------------------------- LCD_PAL120 ------------------------------------------- -#define LCD_PAL120_R04_0_Pos 0 /*!< LCD PAL120: R04_0 Position */ -#define LCD_PAL120_R04_0_Msk (0x1fUL << LCD_PAL120_R04_0_Pos) /*!< LCD PAL120: R04_0 Mask */ -#define LCD_PAL120_G04_0_Pos 5 /*!< LCD PAL120: G04_0 Position */ -#define LCD_PAL120_G04_0_Msk (0x1fUL << LCD_PAL120_G04_0_Pos) /*!< LCD PAL120: G04_0 Mask */ -#define LCD_PAL120_B04_0_Pos 10 /*!< LCD PAL120: B04_0 Position */ -#define LCD_PAL120_B04_0_Msk (0x1fUL << LCD_PAL120_B04_0_Pos) /*!< LCD PAL120: B04_0 Mask */ -#define LCD_PAL120_I0_Pos 15 /*!< LCD PAL120: I0 Position */ -#define LCD_PAL120_I0_Msk (0x01UL << LCD_PAL120_I0_Pos) /*!< LCD PAL120: I0 Mask */ -#define LCD_PAL120_R14_0_Pos 16 /*!< LCD PAL120: R14_0 Position */ -#define LCD_PAL120_R14_0_Msk (0x1fUL << LCD_PAL120_R14_0_Pos) /*!< LCD PAL120: R14_0 Mask */ -#define LCD_PAL120_G14_0_Pos 21 /*!< LCD PAL120: G14_0 Position */ -#define LCD_PAL120_G14_0_Msk (0x1fUL << LCD_PAL120_G14_0_Pos) /*!< LCD PAL120: G14_0 Mask */ -#define LCD_PAL120_B14_0_Pos 26 /*!< LCD PAL120: B14_0 Position */ -#define LCD_PAL120_B14_0_Msk (0x1fUL << LCD_PAL120_B14_0_Pos) /*!< LCD PAL120: B14_0 Mask */ -#define LCD_PAL120_I1_Pos 31 /*!< LCD PAL120: I1 Position */ -#define LCD_PAL120_I1_Msk (0x01UL << LCD_PAL120_I1_Pos) /*!< LCD PAL120: I1 Mask */ - -// --------------------------------------- LCD_PAL121 ------------------------------------------- -#define LCD_PAL121_R04_0_Pos 0 /*!< LCD PAL121: R04_0 Position */ -#define LCD_PAL121_R04_0_Msk (0x1fUL << LCD_PAL121_R04_0_Pos) /*!< LCD PAL121: R04_0 Mask */ -#define LCD_PAL121_G04_0_Pos 5 /*!< LCD PAL121: G04_0 Position */ -#define LCD_PAL121_G04_0_Msk (0x1fUL << LCD_PAL121_G04_0_Pos) /*!< LCD PAL121: G04_0 Mask */ -#define LCD_PAL121_B04_0_Pos 10 /*!< LCD PAL121: B04_0 Position */ -#define LCD_PAL121_B04_0_Msk (0x1fUL << LCD_PAL121_B04_0_Pos) /*!< LCD PAL121: B04_0 Mask */ -#define LCD_PAL121_I0_Pos 15 /*!< LCD PAL121: I0 Position */ -#define LCD_PAL121_I0_Msk (0x01UL << LCD_PAL121_I0_Pos) /*!< LCD PAL121: I0 Mask */ -#define LCD_PAL121_R14_0_Pos 16 /*!< LCD PAL121: R14_0 Position */ -#define LCD_PAL121_R14_0_Msk (0x1fUL << LCD_PAL121_R14_0_Pos) /*!< LCD PAL121: R14_0 Mask */ -#define LCD_PAL121_G14_0_Pos 21 /*!< LCD PAL121: G14_0 Position */ -#define LCD_PAL121_G14_0_Msk (0x1fUL << LCD_PAL121_G14_0_Pos) /*!< LCD PAL121: G14_0 Mask */ -#define LCD_PAL121_B14_0_Pos 26 /*!< LCD PAL121: B14_0 Position */ -#define LCD_PAL121_B14_0_Msk (0x1fUL << LCD_PAL121_B14_0_Pos) /*!< LCD PAL121: B14_0 Mask */ -#define LCD_PAL121_I1_Pos 31 /*!< LCD PAL121: I1 Position */ -#define LCD_PAL121_I1_Msk (0x01UL << LCD_PAL121_I1_Pos) /*!< LCD PAL121: I1 Mask */ - -// --------------------------------------- LCD_PAL122 ------------------------------------------- -#define LCD_PAL122_R04_0_Pos 0 /*!< LCD PAL122: R04_0 Position */ -#define LCD_PAL122_R04_0_Msk (0x1fUL << LCD_PAL122_R04_0_Pos) /*!< LCD PAL122: R04_0 Mask */ -#define LCD_PAL122_G04_0_Pos 5 /*!< LCD PAL122: G04_0 Position */ -#define LCD_PAL122_G04_0_Msk (0x1fUL << LCD_PAL122_G04_0_Pos) /*!< LCD PAL122: G04_0 Mask */ -#define LCD_PAL122_B04_0_Pos 10 /*!< LCD PAL122: B04_0 Position */ -#define LCD_PAL122_B04_0_Msk (0x1fUL << LCD_PAL122_B04_0_Pos) /*!< LCD PAL122: B04_0 Mask */ -#define LCD_PAL122_I0_Pos 15 /*!< LCD PAL122: I0 Position */ -#define LCD_PAL122_I0_Msk (0x01UL << LCD_PAL122_I0_Pos) /*!< LCD PAL122: I0 Mask */ -#define LCD_PAL122_R14_0_Pos 16 /*!< LCD PAL122: R14_0 Position */ -#define LCD_PAL122_R14_0_Msk (0x1fUL << LCD_PAL122_R14_0_Pos) /*!< LCD PAL122: R14_0 Mask */ -#define LCD_PAL122_G14_0_Pos 21 /*!< LCD PAL122: G14_0 Position */ -#define LCD_PAL122_G14_0_Msk (0x1fUL << LCD_PAL122_G14_0_Pos) /*!< LCD PAL122: G14_0 Mask */ -#define LCD_PAL122_B14_0_Pos 26 /*!< LCD PAL122: B14_0 Position */ -#define LCD_PAL122_B14_0_Msk (0x1fUL << LCD_PAL122_B14_0_Pos) /*!< LCD PAL122: B14_0 Mask */ -#define LCD_PAL122_I1_Pos 31 /*!< LCD PAL122: I1 Position */ -#define LCD_PAL122_I1_Msk (0x01UL << LCD_PAL122_I1_Pos) /*!< LCD PAL122: I1 Mask */ - -// --------------------------------------- LCD_PAL123 ------------------------------------------- -#define LCD_PAL123_R04_0_Pos 0 /*!< LCD PAL123: R04_0 Position */ -#define LCD_PAL123_R04_0_Msk (0x1fUL << LCD_PAL123_R04_0_Pos) /*!< LCD PAL123: R04_0 Mask */ -#define LCD_PAL123_G04_0_Pos 5 /*!< LCD PAL123: G04_0 Position */ -#define LCD_PAL123_G04_0_Msk (0x1fUL << LCD_PAL123_G04_0_Pos) /*!< LCD PAL123: G04_0 Mask */ -#define LCD_PAL123_B04_0_Pos 10 /*!< LCD PAL123: B04_0 Position */ -#define LCD_PAL123_B04_0_Msk (0x1fUL << LCD_PAL123_B04_0_Pos) /*!< LCD PAL123: B04_0 Mask */ -#define LCD_PAL123_I0_Pos 15 /*!< LCD PAL123: I0 Position */ -#define LCD_PAL123_I0_Msk (0x01UL << LCD_PAL123_I0_Pos) /*!< LCD PAL123: I0 Mask */ -#define LCD_PAL123_R14_0_Pos 16 /*!< LCD PAL123: R14_0 Position */ -#define LCD_PAL123_R14_0_Msk (0x1fUL << LCD_PAL123_R14_0_Pos) /*!< LCD PAL123: R14_0 Mask */ -#define LCD_PAL123_G14_0_Pos 21 /*!< LCD PAL123: G14_0 Position */ -#define LCD_PAL123_G14_0_Msk (0x1fUL << LCD_PAL123_G14_0_Pos) /*!< LCD PAL123: G14_0 Mask */ -#define LCD_PAL123_B14_0_Pos 26 /*!< LCD PAL123: B14_0 Position */ -#define LCD_PAL123_B14_0_Msk (0x1fUL << LCD_PAL123_B14_0_Pos) /*!< LCD PAL123: B14_0 Mask */ -#define LCD_PAL123_I1_Pos 31 /*!< LCD PAL123: I1 Position */ -#define LCD_PAL123_I1_Msk (0x01UL << LCD_PAL123_I1_Pos) /*!< LCD PAL123: I1 Mask */ - -// --------------------------------------- LCD_PAL124 ------------------------------------------- -#define LCD_PAL124_R04_0_Pos 0 /*!< LCD PAL124: R04_0 Position */ -#define LCD_PAL124_R04_0_Msk (0x1fUL << LCD_PAL124_R04_0_Pos) /*!< LCD PAL124: R04_0 Mask */ -#define LCD_PAL124_G04_0_Pos 5 /*!< LCD PAL124: G04_0 Position */ -#define LCD_PAL124_G04_0_Msk (0x1fUL << LCD_PAL124_G04_0_Pos) /*!< LCD PAL124: G04_0 Mask */ -#define LCD_PAL124_B04_0_Pos 10 /*!< LCD PAL124: B04_0 Position */ -#define LCD_PAL124_B04_0_Msk (0x1fUL << LCD_PAL124_B04_0_Pos) /*!< LCD PAL124: B04_0 Mask */ -#define LCD_PAL124_I0_Pos 15 /*!< LCD PAL124: I0 Position */ -#define LCD_PAL124_I0_Msk (0x01UL << LCD_PAL124_I0_Pos) /*!< LCD PAL124: I0 Mask */ -#define LCD_PAL124_R14_0_Pos 16 /*!< LCD PAL124: R14_0 Position */ -#define LCD_PAL124_R14_0_Msk (0x1fUL << LCD_PAL124_R14_0_Pos) /*!< LCD PAL124: R14_0 Mask */ -#define LCD_PAL124_G14_0_Pos 21 /*!< LCD PAL124: G14_0 Position */ -#define LCD_PAL124_G14_0_Msk (0x1fUL << LCD_PAL124_G14_0_Pos) /*!< LCD PAL124: G14_0 Mask */ -#define LCD_PAL124_B14_0_Pos 26 /*!< LCD PAL124: B14_0 Position */ -#define LCD_PAL124_B14_0_Msk (0x1fUL << LCD_PAL124_B14_0_Pos) /*!< LCD PAL124: B14_0 Mask */ -#define LCD_PAL124_I1_Pos 31 /*!< LCD PAL124: I1 Position */ -#define LCD_PAL124_I1_Msk (0x01UL << LCD_PAL124_I1_Pos) /*!< LCD PAL124: I1 Mask */ - -// --------------------------------------- LCD_PAL125 ------------------------------------------- -#define LCD_PAL125_R04_0_Pos 0 /*!< LCD PAL125: R04_0 Position */ -#define LCD_PAL125_R04_0_Msk (0x1fUL << LCD_PAL125_R04_0_Pos) /*!< LCD PAL125: R04_0 Mask */ -#define LCD_PAL125_G04_0_Pos 5 /*!< LCD PAL125: G04_0 Position */ -#define LCD_PAL125_G04_0_Msk (0x1fUL << LCD_PAL125_G04_0_Pos) /*!< LCD PAL125: G04_0 Mask */ -#define LCD_PAL125_B04_0_Pos 10 /*!< LCD PAL125: B04_0 Position */ -#define LCD_PAL125_B04_0_Msk (0x1fUL << LCD_PAL125_B04_0_Pos) /*!< LCD PAL125: B04_0 Mask */ -#define LCD_PAL125_I0_Pos 15 /*!< LCD PAL125: I0 Position */ -#define LCD_PAL125_I0_Msk (0x01UL << LCD_PAL125_I0_Pos) /*!< LCD PAL125: I0 Mask */ -#define LCD_PAL125_R14_0_Pos 16 /*!< LCD PAL125: R14_0 Position */ -#define LCD_PAL125_R14_0_Msk (0x1fUL << LCD_PAL125_R14_0_Pos) /*!< LCD PAL125: R14_0 Mask */ -#define LCD_PAL125_G14_0_Pos 21 /*!< LCD PAL125: G14_0 Position */ -#define LCD_PAL125_G14_0_Msk (0x1fUL << LCD_PAL125_G14_0_Pos) /*!< LCD PAL125: G14_0 Mask */ -#define LCD_PAL125_B14_0_Pos 26 /*!< LCD PAL125: B14_0 Position */ -#define LCD_PAL125_B14_0_Msk (0x1fUL << LCD_PAL125_B14_0_Pos) /*!< LCD PAL125: B14_0 Mask */ -#define LCD_PAL125_I1_Pos 31 /*!< LCD PAL125: I1 Position */ -#define LCD_PAL125_I1_Msk (0x01UL << LCD_PAL125_I1_Pos) /*!< LCD PAL125: I1 Mask */ - -// --------------------------------------- LCD_PAL126 ------------------------------------------- -#define LCD_PAL126_R04_0_Pos 0 /*!< LCD PAL126: R04_0 Position */ -#define LCD_PAL126_R04_0_Msk (0x1fUL << LCD_PAL126_R04_0_Pos) /*!< LCD PAL126: R04_0 Mask */ -#define LCD_PAL126_G04_0_Pos 5 /*!< LCD PAL126: G04_0 Position */ -#define LCD_PAL126_G04_0_Msk (0x1fUL << LCD_PAL126_G04_0_Pos) /*!< LCD PAL126: G04_0 Mask */ -#define LCD_PAL126_B04_0_Pos 10 /*!< LCD PAL126: B04_0 Position */ -#define LCD_PAL126_B04_0_Msk (0x1fUL << LCD_PAL126_B04_0_Pos) /*!< LCD PAL126: B04_0 Mask */ -#define LCD_PAL126_I0_Pos 15 /*!< LCD PAL126: I0 Position */ -#define LCD_PAL126_I0_Msk (0x01UL << LCD_PAL126_I0_Pos) /*!< LCD PAL126: I0 Mask */ -#define LCD_PAL126_R14_0_Pos 16 /*!< LCD PAL126: R14_0 Position */ -#define LCD_PAL126_R14_0_Msk (0x1fUL << LCD_PAL126_R14_0_Pos) /*!< LCD PAL126: R14_0 Mask */ -#define LCD_PAL126_G14_0_Pos 21 /*!< LCD PAL126: G14_0 Position */ -#define LCD_PAL126_G14_0_Msk (0x1fUL << LCD_PAL126_G14_0_Pos) /*!< LCD PAL126: G14_0 Mask */ -#define LCD_PAL126_B14_0_Pos 26 /*!< LCD PAL126: B14_0 Position */ -#define LCD_PAL126_B14_0_Msk (0x1fUL << LCD_PAL126_B14_0_Pos) /*!< LCD PAL126: B14_0 Mask */ -#define LCD_PAL126_I1_Pos 31 /*!< LCD PAL126: I1 Position */ -#define LCD_PAL126_I1_Msk (0x01UL << LCD_PAL126_I1_Pos) /*!< LCD PAL126: I1 Mask */ - -// --------------------------------------- LCD_PAL127 ------------------------------------------- -#define LCD_PAL127_R04_0_Pos 0 /*!< LCD PAL127: R04_0 Position */ -#define LCD_PAL127_R04_0_Msk (0x1fUL << LCD_PAL127_R04_0_Pos) /*!< LCD PAL127: R04_0 Mask */ -#define LCD_PAL127_G04_0_Pos 5 /*!< LCD PAL127: G04_0 Position */ -#define LCD_PAL127_G04_0_Msk (0x1fUL << LCD_PAL127_G04_0_Pos) /*!< LCD PAL127: G04_0 Mask */ -#define LCD_PAL127_B04_0_Pos 10 /*!< LCD PAL127: B04_0 Position */ -#define LCD_PAL127_B04_0_Msk (0x1fUL << LCD_PAL127_B04_0_Pos) /*!< LCD PAL127: B04_0 Mask */ -#define LCD_PAL127_I0_Pos 15 /*!< LCD PAL127: I0 Position */ -#define LCD_PAL127_I0_Msk (0x01UL << LCD_PAL127_I0_Pos) /*!< LCD PAL127: I0 Mask */ -#define LCD_PAL127_R14_0_Pos 16 /*!< LCD PAL127: R14_0 Position */ -#define LCD_PAL127_R14_0_Msk (0x1fUL << LCD_PAL127_R14_0_Pos) /*!< LCD PAL127: R14_0 Mask */ -#define LCD_PAL127_G14_0_Pos 21 /*!< LCD PAL127: G14_0 Position */ -#define LCD_PAL127_G14_0_Msk (0x1fUL << LCD_PAL127_G14_0_Pos) /*!< LCD PAL127: G14_0 Mask */ -#define LCD_PAL127_B14_0_Pos 26 /*!< LCD PAL127: B14_0 Position */ -#define LCD_PAL127_B14_0_Msk (0x1fUL << LCD_PAL127_B14_0_Pos) /*!< LCD PAL127: B14_0 Mask */ -#define LCD_PAL127_I1_Pos 31 /*!< LCD PAL127: I1 Position */ -#define LCD_PAL127_I1_Msk (0x01UL << LCD_PAL127_I1_Pos) /*!< LCD PAL127: I1 Mask */ - -// --------------------------------------- LCD_PAL128 ------------------------------------------- -#define LCD_PAL128_R04_0_Pos 0 /*!< LCD PAL128: R04_0 Position */ -#define LCD_PAL128_R04_0_Msk (0x1fUL << LCD_PAL128_R04_0_Pos) /*!< LCD PAL128: R04_0 Mask */ -#define LCD_PAL128_G04_0_Pos 5 /*!< LCD PAL128: G04_0 Position */ -#define LCD_PAL128_G04_0_Msk (0x1fUL << LCD_PAL128_G04_0_Pos) /*!< LCD PAL128: G04_0 Mask */ -#define LCD_PAL128_B04_0_Pos 10 /*!< LCD PAL128: B04_0 Position */ -#define LCD_PAL128_B04_0_Msk (0x1fUL << LCD_PAL128_B04_0_Pos) /*!< LCD PAL128: B04_0 Mask */ -#define LCD_PAL128_I0_Pos 15 /*!< LCD PAL128: I0 Position */ -#define LCD_PAL128_I0_Msk (0x01UL << LCD_PAL128_I0_Pos) /*!< LCD PAL128: I0 Mask */ -#define LCD_PAL128_R14_0_Pos 16 /*!< LCD PAL128: R14_0 Position */ -#define LCD_PAL128_R14_0_Msk (0x1fUL << LCD_PAL128_R14_0_Pos) /*!< LCD PAL128: R14_0 Mask */ -#define LCD_PAL128_G14_0_Pos 21 /*!< LCD PAL128: G14_0 Position */ -#define LCD_PAL128_G14_0_Msk (0x1fUL << LCD_PAL128_G14_0_Pos) /*!< LCD PAL128: G14_0 Mask */ -#define LCD_PAL128_B14_0_Pos 26 /*!< LCD PAL128: B14_0 Position */ -#define LCD_PAL128_B14_0_Msk (0x1fUL << LCD_PAL128_B14_0_Pos) /*!< LCD PAL128: B14_0 Mask */ -#define LCD_PAL128_I1_Pos 31 /*!< LCD PAL128: I1 Position */ -#define LCD_PAL128_I1_Msk (0x01UL << LCD_PAL128_I1_Pos) /*!< LCD PAL128: I1 Mask */ - -// --------------------------------------- LCD_PAL129 ------------------------------------------- -#define LCD_PAL129_R04_0_Pos 0 /*!< LCD PAL129: R04_0 Position */ -#define LCD_PAL129_R04_0_Msk (0x1fUL << LCD_PAL129_R04_0_Pos) /*!< LCD PAL129: R04_0 Mask */ -#define LCD_PAL129_G04_0_Pos 5 /*!< LCD PAL129: G04_0 Position */ -#define LCD_PAL129_G04_0_Msk (0x1fUL << LCD_PAL129_G04_0_Pos) /*!< LCD PAL129: G04_0 Mask */ -#define LCD_PAL129_B04_0_Pos 10 /*!< LCD PAL129: B04_0 Position */ -#define LCD_PAL129_B04_0_Msk (0x1fUL << LCD_PAL129_B04_0_Pos) /*!< LCD PAL129: B04_0 Mask */ -#define LCD_PAL129_I0_Pos 15 /*!< LCD PAL129: I0 Position */ -#define LCD_PAL129_I0_Msk (0x01UL << LCD_PAL129_I0_Pos) /*!< LCD PAL129: I0 Mask */ -#define LCD_PAL129_R14_0_Pos 16 /*!< LCD PAL129: R14_0 Position */ -#define LCD_PAL129_R14_0_Msk (0x1fUL << LCD_PAL129_R14_0_Pos) /*!< LCD PAL129: R14_0 Mask */ -#define LCD_PAL129_G14_0_Pos 21 /*!< LCD PAL129: G14_0 Position */ -#define LCD_PAL129_G14_0_Msk (0x1fUL << LCD_PAL129_G14_0_Pos) /*!< LCD PAL129: G14_0 Mask */ -#define LCD_PAL129_B14_0_Pos 26 /*!< LCD PAL129: B14_0 Position */ -#define LCD_PAL129_B14_0_Msk (0x1fUL << LCD_PAL129_B14_0_Pos) /*!< LCD PAL129: B14_0 Mask */ -#define LCD_PAL129_I1_Pos 31 /*!< LCD PAL129: I1 Position */ -#define LCD_PAL129_I1_Msk (0x01UL << LCD_PAL129_I1_Pos) /*!< LCD PAL129: I1 Mask */ - -// --------------------------------------- LCD_PAL130 ------------------------------------------- -#define LCD_PAL130_R04_0_Pos 0 /*!< LCD PAL130: R04_0 Position */ -#define LCD_PAL130_R04_0_Msk (0x1fUL << LCD_PAL130_R04_0_Pos) /*!< LCD PAL130: R04_0 Mask */ -#define LCD_PAL130_G04_0_Pos 5 /*!< LCD PAL130: G04_0 Position */ -#define LCD_PAL130_G04_0_Msk (0x1fUL << LCD_PAL130_G04_0_Pos) /*!< LCD PAL130: G04_0 Mask */ -#define LCD_PAL130_B04_0_Pos 10 /*!< LCD PAL130: B04_0 Position */ -#define LCD_PAL130_B04_0_Msk (0x1fUL << LCD_PAL130_B04_0_Pos) /*!< LCD PAL130: B04_0 Mask */ -#define LCD_PAL130_I0_Pos 15 /*!< LCD PAL130: I0 Position */ -#define LCD_PAL130_I0_Msk (0x01UL << LCD_PAL130_I0_Pos) /*!< LCD PAL130: I0 Mask */ -#define LCD_PAL130_R14_0_Pos 16 /*!< LCD PAL130: R14_0 Position */ -#define LCD_PAL130_R14_0_Msk (0x1fUL << LCD_PAL130_R14_0_Pos) /*!< LCD PAL130: R14_0 Mask */ -#define LCD_PAL130_G14_0_Pos 21 /*!< LCD PAL130: G14_0 Position */ -#define LCD_PAL130_G14_0_Msk (0x1fUL << LCD_PAL130_G14_0_Pos) /*!< LCD PAL130: G14_0 Mask */ -#define LCD_PAL130_B14_0_Pos 26 /*!< LCD PAL130: B14_0 Position */ -#define LCD_PAL130_B14_0_Msk (0x1fUL << LCD_PAL130_B14_0_Pos) /*!< LCD PAL130: B14_0 Mask */ -#define LCD_PAL130_I1_Pos 31 /*!< LCD PAL130: I1 Position */ -#define LCD_PAL130_I1_Msk (0x01UL << LCD_PAL130_I1_Pos) /*!< LCD PAL130: I1 Mask */ - -// --------------------------------------- LCD_PAL131 ------------------------------------------- -#define LCD_PAL131_R04_0_Pos 0 /*!< LCD PAL131: R04_0 Position */ -#define LCD_PAL131_R04_0_Msk (0x1fUL << LCD_PAL131_R04_0_Pos) /*!< LCD PAL131: R04_0 Mask */ -#define LCD_PAL131_G04_0_Pos 5 /*!< LCD PAL131: G04_0 Position */ -#define LCD_PAL131_G04_0_Msk (0x1fUL << LCD_PAL131_G04_0_Pos) /*!< LCD PAL131: G04_0 Mask */ -#define LCD_PAL131_B04_0_Pos 10 /*!< LCD PAL131: B04_0 Position */ -#define LCD_PAL131_B04_0_Msk (0x1fUL << LCD_PAL131_B04_0_Pos) /*!< LCD PAL131: B04_0 Mask */ -#define LCD_PAL131_I0_Pos 15 /*!< LCD PAL131: I0 Position */ -#define LCD_PAL131_I0_Msk (0x01UL << LCD_PAL131_I0_Pos) /*!< LCD PAL131: I0 Mask */ -#define LCD_PAL131_R14_0_Pos 16 /*!< LCD PAL131: R14_0 Position */ -#define LCD_PAL131_R14_0_Msk (0x1fUL << LCD_PAL131_R14_0_Pos) /*!< LCD PAL131: R14_0 Mask */ -#define LCD_PAL131_G14_0_Pos 21 /*!< LCD PAL131: G14_0 Position */ -#define LCD_PAL131_G14_0_Msk (0x1fUL << LCD_PAL131_G14_0_Pos) /*!< LCD PAL131: G14_0 Mask */ -#define LCD_PAL131_B14_0_Pos 26 /*!< LCD PAL131: B14_0 Position */ -#define LCD_PAL131_B14_0_Msk (0x1fUL << LCD_PAL131_B14_0_Pos) /*!< LCD PAL131: B14_0 Mask */ -#define LCD_PAL131_I1_Pos 31 /*!< LCD PAL131: I1 Position */ -#define LCD_PAL131_I1_Msk (0x01UL << LCD_PAL131_I1_Pos) /*!< LCD PAL131: I1 Mask */ - -// --------------------------------------- LCD_PAL132 ------------------------------------------- -#define LCD_PAL132_R04_0_Pos 0 /*!< LCD PAL132: R04_0 Position */ -#define LCD_PAL132_R04_0_Msk (0x1fUL << LCD_PAL132_R04_0_Pos) /*!< LCD PAL132: R04_0 Mask */ -#define LCD_PAL132_G04_0_Pos 5 /*!< LCD PAL132: G04_0 Position */ -#define LCD_PAL132_G04_0_Msk (0x1fUL << LCD_PAL132_G04_0_Pos) /*!< LCD PAL132: G04_0 Mask */ -#define LCD_PAL132_B04_0_Pos 10 /*!< LCD PAL132: B04_0 Position */ -#define LCD_PAL132_B04_0_Msk (0x1fUL << LCD_PAL132_B04_0_Pos) /*!< LCD PAL132: B04_0 Mask */ -#define LCD_PAL132_I0_Pos 15 /*!< LCD PAL132: I0 Position */ -#define LCD_PAL132_I0_Msk (0x01UL << LCD_PAL132_I0_Pos) /*!< LCD PAL132: I0 Mask */ -#define LCD_PAL132_R14_0_Pos 16 /*!< LCD PAL132: R14_0 Position */ -#define LCD_PAL132_R14_0_Msk (0x1fUL << LCD_PAL132_R14_0_Pos) /*!< LCD PAL132: R14_0 Mask */ -#define LCD_PAL132_G14_0_Pos 21 /*!< LCD PAL132: G14_0 Position */ -#define LCD_PAL132_G14_0_Msk (0x1fUL << LCD_PAL132_G14_0_Pos) /*!< LCD PAL132: G14_0 Mask */ -#define LCD_PAL132_B14_0_Pos 26 /*!< LCD PAL132: B14_0 Position */ -#define LCD_PAL132_B14_0_Msk (0x1fUL << LCD_PAL132_B14_0_Pos) /*!< LCD PAL132: B14_0 Mask */ -#define LCD_PAL132_I1_Pos 31 /*!< LCD PAL132: I1 Position */ -#define LCD_PAL132_I1_Msk (0x01UL << LCD_PAL132_I1_Pos) /*!< LCD PAL132: I1 Mask */ - -// --------------------------------------- LCD_PAL133 ------------------------------------------- -#define LCD_PAL133_R04_0_Pos 0 /*!< LCD PAL133: R04_0 Position */ -#define LCD_PAL133_R04_0_Msk (0x1fUL << LCD_PAL133_R04_0_Pos) /*!< LCD PAL133: R04_0 Mask */ -#define LCD_PAL133_G04_0_Pos 5 /*!< LCD PAL133: G04_0 Position */ -#define LCD_PAL133_G04_0_Msk (0x1fUL << LCD_PAL133_G04_0_Pos) /*!< LCD PAL133: G04_0 Mask */ -#define LCD_PAL133_B04_0_Pos 10 /*!< LCD PAL133: B04_0 Position */ -#define LCD_PAL133_B04_0_Msk (0x1fUL << LCD_PAL133_B04_0_Pos) /*!< LCD PAL133: B04_0 Mask */ -#define LCD_PAL133_I0_Pos 15 /*!< LCD PAL133: I0 Position */ -#define LCD_PAL133_I0_Msk (0x01UL << LCD_PAL133_I0_Pos) /*!< LCD PAL133: I0 Mask */ -#define LCD_PAL133_R14_0_Pos 16 /*!< LCD PAL133: R14_0 Position */ -#define LCD_PAL133_R14_0_Msk (0x1fUL << LCD_PAL133_R14_0_Pos) /*!< LCD PAL133: R14_0 Mask */ -#define LCD_PAL133_G14_0_Pos 21 /*!< LCD PAL133: G14_0 Position */ -#define LCD_PAL133_G14_0_Msk (0x1fUL << LCD_PAL133_G14_0_Pos) /*!< LCD PAL133: G14_0 Mask */ -#define LCD_PAL133_B14_0_Pos 26 /*!< LCD PAL133: B14_0 Position */ -#define LCD_PAL133_B14_0_Msk (0x1fUL << LCD_PAL133_B14_0_Pos) /*!< LCD PAL133: B14_0 Mask */ -#define LCD_PAL133_I1_Pos 31 /*!< LCD PAL133: I1 Position */ -#define LCD_PAL133_I1_Msk (0x01UL << LCD_PAL133_I1_Pos) /*!< LCD PAL133: I1 Mask */ - -// --------------------------------------- LCD_PAL134 ------------------------------------------- -#define LCD_PAL134_R04_0_Pos 0 /*!< LCD PAL134: R04_0 Position */ -#define LCD_PAL134_R04_0_Msk (0x1fUL << LCD_PAL134_R04_0_Pos) /*!< LCD PAL134: R04_0 Mask */ -#define LCD_PAL134_G04_0_Pos 5 /*!< LCD PAL134: G04_0 Position */ -#define LCD_PAL134_G04_0_Msk (0x1fUL << LCD_PAL134_G04_0_Pos) /*!< LCD PAL134: G04_0 Mask */ -#define LCD_PAL134_B04_0_Pos 10 /*!< LCD PAL134: B04_0 Position */ -#define LCD_PAL134_B04_0_Msk (0x1fUL << LCD_PAL134_B04_0_Pos) /*!< LCD PAL134: B04_0 Mask */ -#define LCD_PAL134_I0_Pos 15 /*!< LCD PAL134: I0 Position */ -#define LCD_PAL134_I0_Msk (0x01UL << LCD_PAL134_I0_Pos) /*!< LCD PAL134: I0 Mask */ -#define LCD_PAL134_R14_0_Pos 16 /*!< LCD PAL134: R14_0 Position */ -#define LCD_PAL134_R14_0_Msk (0x1fUL << LCD_PAL134_R14_0_Pos) /*!< LCD PAL134: R14_0 Mask */ -#define LCD_PAL134_G14_0_Pos 21 /*!< LCD PAL134: G14_0 Position */ -#define LCD_PAL134_G14_0_Msk (0x1fUL << LCD_PAL134_G14_0_Pos) /*!< LCD PAL134: G14_0 Mask */ -#define LCD_PAL134_B14_0_Pos 26 /*!< LCD PAL134: B14_0 Position */ -#define LCD_PAL134_B14_0_Msk (0x1fUL << LCD_PAL134_B14_0_Pos) /*!< LCD PAL134: B14_0 Mask */ -#define LCD_PAL134_I1_Pos 31 /*!< LCD PAL134: I1 Position */ -#define LCD_PAL134_I1_Msk (0x01UL << LCD_PAL134_I1_Pos) /*!< LCD PAL134: I1 Mask */ - -// --------------------------------------- LCD_PAL135 ------------------------------------------- -#define LCD_PAL135_R04_0_Pos 0 /*!< LCD PAL135: R04_0 Position */ -#define LCD_PAL135_R04_0_Msk (0x1fUL << LCD_PAL135_R04_0_Pos) /*!< LCD PAL135: R04_0 Mask */ -#define LCD_PAL135_G04_0_Pos 5 /*!< LCD PAL135: G04_0 Position */ -#define LCD_PAL135_G04_0_Msk (0x1fUL << LCD_PAL135_G04_0_Pos) /*!< LCD PAL135: G04_0 Mask */ -#define LCD_PAL135_B04_0_Pos 10 /*!< LCD PAL135: B04_0 Position */ -#define LCD_PAL135_B04_0_Msk (0x1fUL << LCD_PAL135_B04_0_Pos) /*!< LCD PAL135: B04_0 Mask */ -#define LCD_PAL135_I0_Pos 15 /*!< LCD PAL135: I0 Position */ -#define LCD_PAL135_I0_Msk (0x01UL << LCD_PAL135_I0_Pos) /*!< LCD PAL135: I0 Mask */ -#define LCD_PAL135_R14_0_Pos 16 /*!< LCD PAL135: R14_0 Position */ -#define LCD_PAL135_R14_0_Msk (0x1fUL << LCD_PAL135_R14_0_Pos) /*!< LCD PAL135: R14_0 Mask */ -#define LCD_PAL135_G14_0_Pos 21 /*!< LCD PAL135: G14_0 Position */ -#define LCD_PAL135_G14_0_Msk (0x1fUL << LCD_PAL135_G14_0_Pos) /*!< LCD PAL135: G14_0 Mask */ -#define LCD_PAL135_B14_0_Pos 26 /*!< LCD PAL135: B14_0 Position */ -#define LCD_PAL135_B14_0_Msk (0x1fUL << LCD_PAL135_B14_0_Pos) /*!< LCD PAL135: B14_0 Mask */ -#define LCD_PAL135_I1_Pos 31 /*!< LCD PAL135: I1 Position */ -#define LCD_PAL135_I1_Msk (0x01UL << LCD_PAL135_I1_Pos) /*!< LCD PAL135: I1 Mask */ - -// --------------------------------------- LCD_PAL136 ------------------------------------------- -#define LCD_PAL136_R04_0_Pos 0 /*!< LCD PAL136: R04_0 Position */ -#define LCD_PAL136_R04_0_Msk (0x1fUL << LCD_PAL136_R04_0_Pos) /*!< LCD PAL136: R04_0 Mask */ -#define LCD_PAL136_G04_0_Pos 5 /*!< LCD PAL136: G04_0 Position */ -#define LCD_PAL136_G04_0_Msk (0x1fUL << LCD_PAL136_G04_0_Pos) /*!< LCD PAL136: G04_0 Mask */ -#define LCD_PAL136_B04_0_Pos 10 /*!< LCD PAL136: B04_0 Position */ -#define LCD_PAL136_B04_0_Msk (0x1fUL << LCD_PAL136_B04_0_Pos) /*!< LCD PAL136: B04_0 Mask */ -#define LCD_PAL136_I0_Pos 15 /*!< LCD PAL136: I0 Position */ -#define LCD_PAL136_I0_Msk (0x01UL << LCD_PAL136_I0_Pos) /*!< LCD PAL136: I0 Mask */ -#define LCD_PAL136_R14_0_Pos 16 /*!< LCD PAL136: R14_0 Position */ -#define LCD_PAL136_R14_0_Msk (0x1fUL << LCD_PAL136_R14_0_Pos) /*!< LCD PAL136: R14_0 Mask */ -#define LCD_PAL136_G14_0_Pos 21 /*!< LCD PAL136: G14_0 Position */ -#define LCD_PAL136_G14_0_Msk (0x1fUL << LCD_PAL136_G14_0_Pos) /*!< LCD PAL136: G14_0 Mask */ -#define LCD_PAL136_B14_0_Pos 26 /*!< LCD PAL136: B14_0 Position */ -#define LCD_PAL136_B14_0_Msk (0x1fUL << LCD_PAL136_B14_0_Pos) /*!< LCD PAL136: B14_0 Mask */ -#define LCD_PAL136_I1_Pos 31 /*!< LCD PAL136: I1 Position */ -#define LCD_PAL136_I1_Msk (0x01UL << LCD_PAL136_I1_Pos) /*!< LCD PAL136: I1 Mask */ - -// --------------------------------------- LCD_PAL137 ------------------------------------------- -#define LCD_PAL137_R04_0_Pos 0 /*!< LCD PAL137: R04_0 Position */ -#define LCD_PAL137_R04_0_Msk (0x1fUL << LCD_PAL137_R04_0_Pos) /*!< LCD PAL137: R04_0 Mask */ -#define LCD_PAL137_G04_0_Pos 5 /*!< LCD PAL137: G04_0 Position */ -#define LCD_PAL137_G04_0_Msk (0x1fUL << LCD_PAL137_G04_0_Pos) /*!< LCD PAL137: G04_0 Mask */ -#define LCD_PAL137_B04_0_Pos 10 /*!< LCD PAL137: B04_0 Position */ -#define LCD_PAL137_B04_0_Msk (0x1fUL << LCD_PAL137_B04_0_Pos) /*!< LCD PAL137: B04_0 Mask */ -#define LCD_PAL137_I0_Pos 15 /*!< LCD PAL137: I0 Position */ -#define LCD_PAL137_I0_Msk (0x01UL << LCD_PAL137_I0_Pos) /*!< LCD PAL137: I0 Mask */ -#define LCD_PAL137_R14_0_Pos 16 /*!< LCD PAL137: R14_0 Position */ -#define LCD_PAL137_R14_0_Msk (0x1fUL << LCD_PAL137_R14_0_Pos) /*!< LCD PAL137: R14_0 Mask */ -#define LCD_PAL137_G14_0_Pos 21 /*!< LCD PAL137: G14_0 Position */ -#define LCD_PAL137_G14_0_Msk (0x1fUL << LCD_PAL137_G14_0_Pos) /*!< LCD PAL137: G14_0 Mask */ -#define LCD_PAL137_B14_0_Pos 26 /*!< LCD PAL137: B14_0 Position */ -#define LCD_PAL137_B14_0_Msk (0x1fUL << LCD_PAL137_B14_0_Pos) /*!< LCD PAL137: B14_0 Mask */ -#define LCD_PAL137_I1_Pos 31 /*!< LCD PAL137: I1 Position */ -#define LCD_PAL137_I1_Msk (0x01UL << LCD_PAL137_I1_Pos) /*!< LCD PAL137: I1 Mask */ - -// --------------------------------------- LCD_PAL138 ------------------------------------------- -#define LCD_PAL138_R04_0_Pos 0 /*!< LCD PAL138: R04_0 Position */ -#define LCD_PAL138_R04_0_Msk (0x1fUL << LCD_PAL138_R04_0_Pos) /*!< LCD PAL138: R04_0 Mask */ -#define LCD_PAL138_G04_0_Pos 5 /*!< LCD PAL138: G04_0 Position */ -#define LCD_PAL138_G04_0_Msk (0x1fUL << LCD_PAL138_G04_0_Pos) /*!< LCD PAL138: G04_0 Mask */ -#define LCD_PAL138_B04_0_Pos 10 /*!< LCD PAL138: B04_0 Position */ -#define LCD_PAL138_B04_0_Msk (0x1fUL << LCD_PAL138_B04_0_Pos) /*!< LCD PAL138: B04_0 Mask */ -#define LCD_PAL138_I0_Pos 15 /*!< LCD PAL138: I0 Position */ -#define LCD_PAL138_I0_Msk (0x01UL << LCD_PAL138_I0_Pos) /*!< LCD PAL138: I0 Mask */ -#define LCD_PAL138_R14_0_Pos 16 /*!< LCD PAL138: R14_0 Position */ -#define LCD_PAL138_R14_0_Msk (0x1fUL << LCD_PAL138_R14_0_Pos) /*!< LCD PAL138: R14_0 Mask */ -#define LCD_PAL138_G14_0_Pos 21 /*!< LCD PAL138: G14_0 Position */ -#define LCD_PAL138_G14_0_Msk (0x1fUL << LCD_PAL138_G14_0_Pos) /*!< LCD PAL138: G14_0 Mask */ -#define LCD_PAL138_B14_0_Pos 26 /*!< LCD PAL138: B14_0 Position */ -#define LCD_PAL138_B14_0_Msk (0x1fUL << LCD_PAL138_B14_0_Pos) /*!< LCD PAL138: B14_0 Mask */ -#define LCD_PAL138_I1_Pos 31 /*!< LCD PAL138: I1 Position */ -#define LCD_PAL138_I1_Msk (0x01UL << LCD_PAL138_I1_Pos) /*!< LCD PAL138: I1 Mask */ - -// --------------------------------------- LCD_PAL139 ------------------------------------------- -#define LCD_PAL139_R04_0_Pos 0 /*!< LCD PAL139: R04_0 Position */ -#define LCD_PAL139_R04_0_Msk (0x1fUL << LCD_PAL139_R04_0_Pos) /*!< LCD PAL139: R04_0 Mask */ -#define LCD_PAL139_G04_0_Pos 5 /*!< LCD PAL139: G04_0 Position */ -#define LCD_PAL139_G04_0_Msk (0x1fUL << LCD_PAL139_G04_0_Pos) /*!< LCD PAL139: G04_0 Mask */ -#define LCD_PAL139_B04_0_Pos 10 /*!< LCD PAL139: B04_0 Position */ -#define LCD_PAL139_B04_0_Msk (0x1fUL << LCD_PAL139_B04_0_Pos) /*!< LCD PAL139: B04_0 Mask */ -#define LCD_PAL139_I0_Pos 15 /*!< LCD PAL139: I0 Position */ -#define LCD_PAL139_I0_Msk (0x01UL << LCD_PAL139_I0_Pos) /*!< LCD PAL139: I0 Mask */ -#define LCD_PAL139_R14_0_Pos 16 /*!< LCD PAL139: R14_0 Position */ -#define LCD_PAL139_R14_0_Msk (0x1fUL << LCD_PAL139_R14_0_Pos) /*!< LCD PAL139: R14_0 Mask */ -#define LCD_PAL139_G14_0_Pos 21 /*!< LCD PAL139: G14_0 Position */ -#define LCD_PAL139_G14_0_Msk (0x1fUL << LCD_PAL139_G14_0_Pos) /*!< LCD PAL139: G14_0 Mask */ -#define LCD_PAL139_B14_0_Pos 26 /*!< LCD PAL139: B14_0 Position */ -#define LCD_PAL139_B14_0_Msk (0x1fUL << LCD_PAL139_B14_0_Pos) /*!< LCD PAL139: B14_0 Mask */ -#define LCD_PAL139_I1_Pos 31 /*!< LCD PAL139: I1 Position */ -#define LCD_PAL139_I1_Msk (0x01UL << LCD_PAL139_I1_Pos) /*!< LCD PAL139: I1 Mask */ - -// --------------------------------------- LCD_PAL140 ------------------------------------------- -#define LCD_PAL140_R04_0_Pos 0 /*!< LCD PAL140: R04_0 Position */ -#define LCD_PAL140_R04_0_Msk (0x1fUL << LCD_PAL140_R04_0_Pos) /*!< LCD PAL140: R04_0 Mask */ -#define LCD_PAL140_G04_0_Pos 5 /*!< LCD PAL140: G04_0 Position */ -#define LCD_PAL140_G04_0_Msk (0x1fUL << LCD_PAL140_G04_0_Pos) /*!< LCD PAL140: G04_0 Mask */ -#define LCD_PAL140_B04_0_Pos 10 /*!< LCD PAL140: B04_0 Position */ -#define LCD_PAL140_B04_0_Msk (0x1fUL << LCD_PAL140_B04_0_Pos) /*!< LCD PAL140: B04_0 Mask */ -#define LCD_PAL140_I0_Pos 15 /*!< LCD PAL140: I0 Position */ -#define LCD_PAL140_I0_Msk (0x01UL << LCD_PAL140_I0_Pos) /*!< LCD PAL140: I0 Mask */ -#define LCD_PAL140_R14_0_Pos 16 /*!< LCD PAL140: R14_0 Position */ -#define LCD_PAL140_R14_0_Msk (0x1fUL << LCD_PAL140_R14_0_Pos) /*!< LCD PAL140: R14_0 Mask */ -#define LCD_PAL140_G14_0_Pos 21 /*!< LCD PAL140: G14_0 Position */ -#define LCD_PAL140_G14_0_Msk (0x1fUL << LCD_PAL140_G14_0_Pos) /*!< LCD PAL140: G14_0 Mask */ -#define LCD_PAL140_B14_0_Pos 26 /*!< LCD PAL140: B14_0 Position */ -#define LCD_PAL140_B14_0_Msk (0x1fUL << LCD_PAL140_B14_0_Pos) /*!< LCD PAL140: B14_0 Mask */ -#define LCD_PAL140_I1_Pos 31 /*!< LCD PAL140: I1 Position */ -#define LCD_PAL140_I1_Msk (0x01UL << LCD_PAL140_I1_Pos) /*!< LCD PAL140: I1 Mask */ - -// --------------------------------------- LCD_PAL141 ------------------------------------------- -#define LCD_PAL141_R04_0_Pos 0 /*!< LCD PAL141: R04_0 Position */ -#define LCD_PAL141_R04_0_Msk (0x1fUL << LCD_PAL141_R04_0_Pos) /*!< LCD PAL141: R04_0 Mask */ -#define LCD_PAL141_G04_0_Pos 5 /*!< LCD PAL141: G04_0 Position */ -#define LCD_PAL141_G04_0_Msk (0x1fUL << LCD_PAL141_G04_0_Pos) /*!< LCD PAL141: G04_0 Mask */ -#define LCD_PAL141_B04_0_Pos 10 /*!< LCD PAL141: B04_0 Position */ -#define LCD_PAL141_B04_0_Msk (0x1fUL << LCD_PAL141_B04_0_Pos) /*!< LCD PAL141: B04_0 Mask */ -#define LCD_PAL141_I0_Pos 15 /*!< LCD PAL141: I0 Position */ -#define LCD_PAL141_I0_Msk (0x01UL << LCD_PAL141_I0_Pos) /*!< LCD PAL141: I0 Mask */ -#define LCD_PAL141_R14_0_Pos 16 /*!< LCD PAL141: R14_0 Position */ -#define LCD_PAL141_R14_0_Msk (0x1fUL << LCD_PAL141_R14_0_Pos) /*!< LCD PAL141: R14_0 Mask */ -#define LCD_PAL141_G14_0_Pos 21 /*!< LCD PAL141: G14_0 Position */ -#define LCD_PAL141_G14_0_Msk (0x1fUL << LCD_PAL141_G14_0_Pos) /*!< LCD PAL141: G14_0 Mask */ -#define LCD_PAL141_B14_0_Pos 26 /*!< LCD PAL141: B14_0 Position */ -#define LCD_PAL141_B14_0_Msk (0x1fUL << LCD_PAL141_B14_0_Pos) /*!< LCD PAL141: B14_0 Mask */ -#define LCD_PAL141_I1_Pos 31 /*!< LCD PAL141: I1 Position */ -#define LCD_PAL141_I1_Msk (0x01UL << LCD_PAL141_I1_Pos) /*!< LCD PAL141: I1 Mask */ - -// --------------------------------------- LCD_PAL142 ------------------------------------------- -#define LCD_PAL142_R04_0_Pos 0 /*!< LCD PAL142: R04_0 Position */ -#define LCD_PAL142_R04_0_Msk (0x1fUL << LCD_PAL142_R04_0_Pos) /*!< LCD PAL142: R04_0 Mask */ -#define LCD_PAL142_G04_0_Pos 5 /*!< LCD PAL142: G04_0 Position */ -#define LCD_PAL142_G04_0_Msk (0x1fUL << LCD_PAL142_G04_0_Pos) /*!< LCD PAL142: G04_0 Mask */ -#define LCD_PAL142_B04_0_Pos 10 /*!< LCD PAL142: B04_0 Position */ -#define LCD_PAL142_B04_0_Msk (0x1fUL << LCD_PAL142_B04_0_Pos) /*!< LCD PAL142: B04_0 Mask */ -#define LCD_PAL142_I0_Pos 15 /*!< LCD PAL142: I0 Position */ -#define LCD_PAL142_I0_Msk (0x01UL << LCD_PAL142_I0_Pos) /*!< LCD PAL142: I0 Mask */ -#define LCD_PAL142_R14_0_Pos 16 /*!< LCD PAL142: R14_0 Position */ -#define LCD_PAL142_R14_0_Msk (0x1fUL << LCD_PAL142_R14_0_Pos) /*!< LCD PAL142: R14_0 Mask */ -#define LCD_PAL142_G14_0_Pos 21 /*!< LCD PAL142: G14_0 Position */ -#define LCD_PAL142_G14_0_Msk (0x1fUL << LCD_PAL142_G14_0_Pos) /*!< LCD PAL142: G14_0 Mask */ -#define LCD_PAL142_B14_0_Pos 26 /*!< LCD PAL142: B14_0 Position */ -#define LCD_PAL142_B14_0_Msk (0x1fUL << LCD_PAL142_B14_0_Pos) /*!< LCD PAL142: B14_0 Mask */ -#define LCD_PAL142_I1_Pos 31 /*!< LCD PAL142: I1 Position */ -#define LCD_PAL142_I1_Msk (0x01UL << LCD_PAL142_I1_Pos) /*!< LCD PAL142: I1 Mask */ - -// --------------------------------------- LCD_PAL143 ------------------------------------------- -#define LCD_PAL143_R04_0_Pos 0 /*!< LCD PAL143: R04_0 Position */ -#define LCD_PAL143_R04_0_Msk (0x1fUL << LCD_PAL143_R04_0_Pos) /*!< LCD PAL143: R04_0 Mask */ -#define LCD_PAL143_G04_0_Pos 5 /*!< LCD PAL143: G04_0 Position */ -#define LCD_PAL143_G04_0_Msk (0x1fUL << LCD_PAL143_G04_0_Pos) /*!< LCD PAL143: G04_0 Mask */ -#define LCD_PAL143_B04_0_Pos 10 /*!< LCD PAL143: B04_0 Position */ -#define LCD_PAL143_B04_0_Msk (0x1fUL << LCD_PAL143_B04_0_Pos) /*!< LCD PAL143: B04_0 Mask */ -#define LCD_PAL143_I0_Pos 15 /*!< LCD PAL143: I0 Position */ -#define LCD_PAL143_I0_Msk (0x01UL << LCD_PAL143_I0_Pos) /*!< LCD PAL143: I0 Mask */ -#define LCD_PAL143_R14_0_Pos 16 /*!< LCD PAL143: R14_0 Position */ -#define LCD_PAL143_R14_0_Msk (0x1fUL << LCD_PAL143_R14_0_Pos) /*!< LCD PAL143: R14_0 Mask */ -#define LCD_PAL143_G14_0_Pos 21 /*!< LCD PAL143: G14_0 Position */ -#define LCD_PAL143_G14_0_Msk (0x1fUL << LCD_PAL143_G14_0_Pos) /*!< LCD PAL143: G14_0 Mask */ -#define LCD_PAL143_B14_0_Pos 26 /*!< LCD PAL143: B14_0 Position */ -#define LCD_PAL143_B14_0_Msk (0x1fUL << LCD_PAL143_B14_0_Pos) /*!< LCD PAL143: B14_0 Mask */ -#define LCD_PAL143_I1_Pos 31 /*!< LCD PAL143: I1 Position */ -#define LCD_PAL143_I1_Msk (0x01UL << LCD_PAL143_I1_Pos) /*!< LCD PAL143: I1 Mask */ - -// --------------------------------------- LCD_PAL144 ------------------------------------------- -#define LCD_PAL144_R04_0_Pos 0 /*!< LCD PAL144: R04_0 Position */ -#define LCD_PAL144_R04_0_Msk (0x1fUL << LCD_PAL144_R04_0_Pos) /*!< LCD PAL144: R04_0 Mask */ -#define LCD_PAL144_G04_0_Pos 5 /*!< LCD PAL144: G04_0 Position */ -#define LCD_PAL144_G04_0_Msk (0x1fUL << LCD_PAL144_G04_0_Pos) /*!< LCD PAL144: G04_0 Mask */ -#define LCD_PAL144_B04_0_Pos 10 /*!< LCD PAL144: B04_0 Position */ -#define LCD_PAL144_B04_0_Msk (0x1fUL << LCD_PAL144_B04_0_Pos) /*!< LCD PAL144: B04_0 Mask */ -#define LCD_PAL144_I0_Pos 15 /*!< LCD PAL144: I0 Position */ -#define LCD_PAL144_I0_Msk (0x01UL << LCD_PAL144_I0_Pos) /*!< LCD PAL144: I0 Mask */ -#define LCD_PAL144_R14_0_Pos 16 /*!< LCD PAL144: R14_0 Position */ -#define LCD_PAL144_R14_0_Msk (0x1fUL << LCD_PAL144_R14_0_Pos) /*!< LCD PAL144: R14_0 Mask */ -#define LCD_PAL144_G14_0_Pos 21 /*!< LCD PAL144: G14_0 Position */ -#define LCD_PAL144_G14_0_Msk (0x1fUL << LCD_PAL144_G14_0_Pos) /*!< LCD PAL144: G14_0 Mask */ -#define LCD_PAL144_B14_0_Pos 26 /*!< LCD PAL144: B14_0 Position */ -#define LCD_PAL144_B14_0_Msk (0x1fUL << LCD_PAL144_B14_0_Pos) /*!< LCD PAL144: B14_0 Mask */ -#define LCD_PAL144_I1_Pos 31 /*!< LCD PAL144: I1 Position */ -#define LCD_PAL144_I1_Msk (0x01UL << LCD_PAL144_I1_Pos) /*!< LCD PAL144: I1 Mask */ - -// --------------------------------------- LCD_PAL145 ------------------------------------------- -#define LCD_PAL145_R04_0_Pos 0 /*!< LCD PAL145: R04_0 Position */ -#define LCD_PAL145_R04_0_Msk (0x1fUL << LCD_PAL145_R04_0_Pos) /*!< LCD PAL145: R04_0 Mask */ -#define LCD_PAL145_G04_0_Pos 5 /*!< LCD PAL145: G04_0 Position */ -#define LCD_PAL145_G04_0_Msk (0x1fUL << LCD_PAL145_G04_0_Pos) /*!< LCD PAL145: G04_0 Mask */ -#define LCD_PAL145_B04_0_Pos 10 /*!< LCD PAL145: B04_0 Position */ -#define LCD_PAL145_B04_0_Msk (0x1fUL << LCD_PAL145_B04_0_Pos) /*!< LCD PAL145: B04_0 Mask */ -#define LCD_PAL145_I0_Pos 15 /*!< LCD PAL145: I0 Position */ -#define LCD_PAL145_I0_Msk (0x01UL << LCD_PAL145_I0_Pos) /*!< LCD PAL145: I0 Mask */ -#define LCD_PAL145_R14_0_Pos 16 /*!< LCD PAL145: R14_0 Position */ -#define LCD_PAL145_R14_0_Msk (0x1fUL << LCD_PAL145_R14_0_Pos) /*!< LCD PAL145: R14_0 Mask */ -#define LCD_PAL145_G14_0_Pos 21 /*!< LCD PAL145: G14_0 Position */ -#define LCD_PAL145_G14_0_Msk (0x1fUL << LCD_PAL145_G14_0_Pos) /*!< LCD PAL145: G14_0 Mask */ -#define LCD_PAL145_B14_0_Pos 26 /*!< LCD PAL145: B14_0 Position */ -#define LCD_PAL145_B14_0_Msk (0x1fUL << LCD_PAL145_B14_0_Pos) /*!< LCD PAL145: B14_0 Mask */ -#define LCD_PAL145_I1_Pos 31 /*!< LCD PAL145: I1 Position */ -#define LCD_PAL145_I1_Msk (0x01UL << LCD_PAL145_I1_Pos) /*!< LCD PAL145: I1 Mask */ - -// --------------------------------------- LCD_PAL146 ------------------------------------------- -#define LCD_PAL146_R04_0_Pos 0 /*!< LCD PAL146: R04_0 Position */ -#define LCD_PAL146_R04_0_Msk (0x1fUL << LCD_PAL146_R04_0_Pos) /*!< LCD PAL146: R04_0 Mask */ -#define LCD_PAL146_G04_0_Pos 5 /*!< LCD PAL146: G04_0 Position */ -#define LCD_PAL146_G04_0_Msk (0x1fUL << LCD_PAL146_G04_0_Pos) /*!< LCD PAL146: G04_0 Mask */ -#define LCD_PAL146_B04_0_Pos 10 /*!< LCD PAL146: B04_0 Position */ -#define LCD_PAL146_B04_0_Msk (0x1fUL << LCD_PAL146_B04_0_Pos) /*!< LCD PAL146: B04_0 Mask */ -#define LCD_PAL146_I0_Pos 15 /*!< LCD PAL146: I0 Position */ -#define LCD_PAL146_I0_Msk (0x01UL << LCD_PAL146_I0_Pos) /*!< LCD PAL146: I0 Mask */ -#define LCD_PAL146_R14_0_Pos 16 /*!< LCD PAL146: R14_0 Position */ -#define LCD_PAL146_R14_0_Msk (0x1fUL << LCD_PAL146_R14_0_Pos) /*!< LCD PAL146: R14_0 Mask */ -#define LCD_PAL146_G14_0_Pos 21 /*!< LCD PAL146: G14_0 Position */ -#define LCD_PAL146_G14_0_Msk (0x1fUL << LCD_PAL146_G14_0_Pos) /*!< LCD PAL146: G14_0 Mask */ -#define LCD_PAL146_B14_0_Pos 26 /*!< LCD PAL146: B14_0 Position */ -#define LCD_PAL146_B14_0_Msk (0x1fUL << LCD_PAL146_B14_0_Pos) /*!< LCD PAL146: B14_0 Mask */ -#define LCD_PAL146_I1_Pos 31 /*!< LCD PAL146: I1 Position */ -#define LCD_PAL146_I1_Msk (0x01UL << LCD_PAL146_I1_Pos) /*!< LCD PAL146: I1 Mask */ - -// --------------------------------------- LCD_PAL147 ------------------------------------------- -#define LCD_PAL147_R04_0_Pos 0 /*!< LCD PAL147: R04_0 Position */ -#define LCD_PAL147_R04_0_Msk (0x1fUL << LCD_PAL147_R04_0_Pos) /*!< LCD PAL147: R04_0 Mask */ -#define LCD_PAL147_G04_0_Pos 5 /*!< LCD PAL147: G04_0 Position */ -#define LCD_PAL147_G04_0_Msk (0x1fUL << LCD_PAL147_G04_0_Pos) /*!< LCD PAL147: G04_0 Mask */ -#define LCD_PAL147_B04_0_Pos 10 /*!< LCD PAL147: B04_0 Position */ -#define LCD_PAL147_B04_0_Msk (0x1fUL << LCD_PAL147_B04_0_Pos) /*!< LCD PAL147: B04_0 Mask */ -#define LCD_PAL147_I0_Pos 15 /*!< LCD PAL147: I0 Position */ -#define LCD_PAL147_I0_Msk (0x01UL << LCD_PAL147_I0_Pos) /*!< LCD PAL147: I0 Mask */ -#define LCD_PAL147_R14_0_Pos 16 /*!< LCD PAL147: R14_0 Position */ -#define LCD_PAL147_R14_0_Msk (0x1fUL << LCD_PAL147_R14_0_Pos) /*!< LCD PAL147: R14_0 Mask */ -#define LCD_PAL147_G14_0_Pos 21 /*!< LCD PAL147: G14_0 Position */ -#define LCD_PAL147_G14_0_Msk (0x1fUL << LCD_PAL147_G14_0_Pos) /*!< LCD PAL147: G14_0 Mask */ -#define LCD_PAL147_B14_0_Pos 26 /*!< LCD PAL147: B14_0 Position */ -#define LCD_PAL147_B14_0_Msk (0x1fUL << LCD_PAL147_B14_0_Pos) /*!< LCD PAL147: B14_0 Mask */ -#define LCD_PAL147_I1_Pos 31 /*!< LCD PAL147: I1 Position */ -#define LCD_PAL147_I1_Msk (0x01UL << LCD_PAL147_I1_Pos) /*!< LCD PAL147: I1 Mask */ - -// --------------------------------------- LCD_PAL148 ------------------------------------------- -#define LCD_PAL148_R04_0_Pos 0 /*!< LCD PAL148: R04_0 Position */ -#define LCD_PAL148_R04_0_Msk (0x1fUL << LCD_PAL148_R04_0_Pos) /*!< LCD PAL148: R04_0 Mask */ -#define LCD_PAL148_G04_0_Pos 5 /*!< LCD PAL148: G04_0 Position */ -#define LCD_PAL148_G04_0_Msk (0x1fUL << LCD_PAL148_G04_0_Pos) /*!< LCD PAL148: G04_0 Mask */ -#define LCD_PAL148_B04_0_Pos 10 /*!< LCD PAL148: B04_0 Position */ -#define LCD_PAL148_B04_0_Msk (0x1fUL << LCD_PAL148_B04_0_Pos) /*!< LCD PAL148: B04_0 Mask */ -#define LCD_PAL148_I0_Pos 15 /*!< LCD PAL148: I0 Position */ -#define LCD_PAL148_I0_Msk (0x01UL << LCD_PAL148_I0_Pos) /*!< LCD PAL148: I0 Mask */ -#define LCD_PAL148_R14_0_Pos 16 /*!< LCD PAL148: R14_0 Position */ -#define LCD_PAL148_R14_0_Msk (0x1fUL << LCD_PAL148_R14_0_Pos) /*!< LCD PAL148: R14_0 Mask */ -#define LCD_PAL148_G14_0_Pos 21 /*!< LCD PAL148: G14_0 Position */ -#define LCD_PAL148_G14_0_Msk (0x1fUL << LCD_PAL148_G14_0_Pos) /*!< LCD PAL148: G14_0 Mask */ -#define LCD_PAL148_B14_0_Pos 26 /*!< LCD PAL148: B14_0 Position */ -#define LCD_PAL148_B14_0_Msk (0x1fUL << LCD_PAL148_B14_0_Pos) /*!< LCD PAL148: B14_0 Mask */ -#define LCD_PAL148_I1_Pos 31 /*!< LCD PAL148: I1 Position */ -#define LCD_PAL148_I1_Msk (0x01UL << LCD_PAL148_I1_Pos) /*!< LCD PAL148: I1 Mask */ - -// --------------------------------------- LCD_PAL149 ------------------------------------------- -#define LCD_PAL149_R04_0_Pos 0 /*!< LCD PAL149: R04_0 Position */ -#define LCD_PAL149_R04_0_Msk (0x1fUL << LCD_PAL149_R04_0_Pos) /*!< LCD PAL149: R04_0 Mask */ -#define LCD_PAL149_G04_0_Pos 5 /*!< LCD PAL149: G04_0 Position */ -#define LCD_PAL149_G04_0_Msk (0x1fUL << LCD_PAL149_G04_0_Pos) /*!< LCD PAL149: G04_0 Mask */ -#define LCD_PAL149_B04_0_Pos 10 /*!< LCD PAL149: B04_0 Position */ -#define LCD_PAL149_B04_0_Msk (0x1fUL << LCD_PAL149_B04_0_Pos) /*!< LCD PAL149: B04_0 Mask */ -#define LCD_PAL149_I0_Pos 15 /*!< LCD PAL149: I0 Position */ -#define LCD_PAL149_I0_Msk (0x01UL << LCD_PAL149_I0_Pos) /*!< LCD PAL149: I0 Mask */ -#define LCD_PAL149_R14_0_Pos 16 /*!< LCD PAL149: R14_0 Position */ -#define LCD_PAL149_R14_0_Msk (0x1fUL << LCD_PAL149_R14_0_Pos) /*!< LCD PAL149: R14_0 Mask */ -#define LCD_PAL149_G14_0_Pos 21 /*!< LCD PAL149: G14_0 Position */ -#define LCD_PAL149_G14_0_Msk (0x1fUL << LCD_PAL149_G14_0_Pos) /*!< LCD PAL149: G14_0 Mask */ -#define LCD_PAL149_B14_0_Pos 26 /*!< LCD PAL149: B14_0 Position */ -#define LCD_PAL149_B14_0_Msk (0x1fUL << LCD_PAL149_B14_0_Pos) /*!< LCD PAL149: B14_0 Mask */ -#define LCD_PAL149_I1_Pos 31 /*!< LCD PAL149: I1 Position */ -#define LCD_PAL149_I1_Msk (0x01UL << LCD_PAL149_I1_Pos) /*!< LCD PAL149: I1 Mask */ - -// --------------------------------------- LCD_PAL150 ------------------------------------------- -#define LCD_PAL150_R04_0_Pos 0 /*!< LCD PAL150: R04_0 Position */ -#define LCD_PAL150_R04_0_Msk (0x1fUL << LCD_PAL150_R04_0_Pos) /*!< LCD PAL150: R04_0 Mask */ -#define LCD_PAL150_G04_0_Pos 5 /*!< LCD PAL150: G04_0 Position */ -#define LCD_PAL150_G04_0_Msk (0x1fUL << LCD_PAL150_G04_0_Pos) /*!< LCD PAL150: G04_0 Mask */ -#define LCD_PAL150_B04_0_Pos 10 /*!< LCD PAL150: B04_0 Position */ -#define LCD_PAL150_B04_0_Msk (0x1fUL << LCD_PAL150_B04_0_Pos) /*!< LCD PAL150: B04_0 Mask */ -#define LCD_PAL150_I0_Pos 15 /*!< LCD PAL150: I0 Position */ -#define LCD_PAL150_I0_Msk (0x01UL << LCD_PAL150_I0_Pos) /*!< LCD PAL150: I0 Mask */ -#define LCD_PAL150_R14_0_Pos 16 /*!< LCD PAL150: R14_0 Position */ -#define LCD_PAL150_R14_0_Msk (0x1fUL << LCD_PAL150_R14_0_Pos) /*!< LCD PAL150: R14_0 Mask */ -#define LCD_PAL150_G14_0_Pos 21 /*!< LCD PAL150: G14_0 Position */ -#define LCD_PAL150_G14_0_Msk (0x1fUL << LCD_PAL150_G14_0_Pos) /*!< LCD PAL150: G14_0 Mask */ -#define LCD_PAL150_B14_0_Pos 26 /*!< LCD PAL150: B14_0 Position */ -#define LCD_PAL150_B14_0_Msk (0x1fUL << LCD_PAL150_B14_0_Pos) /*!< LCD PAL150: B14_0 Mask */ -#define LCD_PAL150_I1_Pos 31 /*!< LCD PAL150: I1 Position */ -#define LCD_PAL150_I1_Msk (0x01UL << LCD_PAL150_I1_Pos) /*!< LCD PAL150: I1 Mask */ - -// --------------------------------------- LCD_PAL151 ------------------------------------------- -#define LCD_PAL151_R04_0_Pos 0 /*!< LCD PAL151: R04_0 Position */ -#define LCD_PAL151_R04_0_Msk (0x1fUL << LCD_PAL151_R04_0_Pos) /*!< LCD PAL151: R04_0 Mask */ -#define LCD_PAL151_G04_0_Pos 5 /*!< LCD PAL151: G04_0 Position */ -#define LCD_PAL151_G04_0_Msk (0x1fUL << LCD_PAL151_G04_0_Pos) /*!< LCD PAL151: G04_0 Mask */ -#define LCD_PAL151_B04_0_Pos 10 /*!< LCD PAL151: B04_0 Position */ -#define LCD_PAL151_B04_0_Msk (0x1fUL << LCD_PAL151_B04_0_Pos) /*!< LCD PAL151: B04_0 Mask */ -#define LCD_PAL151_I0_Pos 15 /*!< LCD PAL151: I0 Position */ -#define LCD_PAL151_I0_Msk (0x01UL << LCD_PAL151_I0_Pos) /*!< LCD PAL151: I0 Mask */ -#define LCD_PAL151_R14_0_Pos 16 /*!< LCD PAL151: R14_0 Position */ -#define LCD_PAL151_R14_0_Msk (0x1fUL << LCD_PAL151_R14_0_Pos) /*!< LCD PAL151: R14_0 Mask */ -#define LCD_PAL151_G14_0_Pos 21 /*!< LCD PAL151: G14_0 Position */ -#define LCD_PAL151_G14_0_Msk (0x1fUL << LCD_PAL151_G14_0_Pos) /*!< LCD PAL151: G14_0 Mask */ -#define LCD_PAL151_B14_0_Pos 26 /*!< LCD PAL151: B14_0 Position */ -#define LCD_PAL151_B14_0_Msk (0x1fUL << LCD_PAL151_B14_0_Pos) /*!< LCD PAL151: B14_0 Mask */ -#define LCD_PAL151_I1_Pos 31 /*!< LCD PAL151: I1 Position */ -#define LCD_PAL151_I1_Msk (0x01UL << LCD_PAL151_I1_Pos) /*!< LCD PAL151: I1 Mask */ - -// --------------------------------------- LCD_PAL152 ------------------------------------------- -#define LCD_PAL152_R04_0_Pos 0 /*!< LCD PAL152: R04_0 Position */ -#define LCD_PAL152_R04_0_Msk (0x1fUL << LCD_PAL152_R04_0_Pos) /*!< LCD PAL152: R04_0 Mask */ -#define LCD_PAL152_G04_0_Pos 5 /*!< LCD PAL152: G04_0 Position */ -#define LCD_PAL152_G04_0_Msk (0x1fUL << LCD_PAL152_G04_0_Pos) /*!< LCD PAL152: G04_0 Mask */ -#define LCD_PAL152_B04_0_Pos 10 /*!< LCD PAL152: B04_0 Position */ -#define LCD_PAL152_B04_0_Msk (0x1fUL << LCD_PAL152_B04_0_Pos) /*!< LCD PAL152: B04_0 Mask */ -#define LCD_PAL152_I0_Pos 15 /*!< LCD PAL152: I0 Position */ -#define LCD_PAL152_I0_Msk (0x01UL << LCD_PAL152_I0_Pos) /*!< LCD PAL152: I0 Mask */ -#define LCD_PAL152_R14_0_Pos 16 /*!< LCD PAL152: R14_0 Position */ -#define LCD_PAL152_R14_0_Msk (0x1fUL << LCD_PAL152_R14_0_Pos) /*!< LCD PAL152: R14_0 Mask */ -#define LCD_PAL152_G14_0_Pos 21 /*!< LCD PAL152: G14_0 Position */ -#define LCD_PAL152_G14_0_Msk (0x1fUL << LCD_PAL152_G14_0_Pos) /*!< LCD PAL152: G14_0 Mask */ -#define LCD_PAL152_B14_0_Pos 26 /*!< LCD PAL152: B14_0 Position */ -#define LCD_PAL152_B14_0_Msk (0x1fUL << LCD_PAL152_B14_0_Pos) /*!< LCD PAL152: B14_0 Mask */ -#define LCD_PAL152_I1_Pos 31 /*!< LCD PAL152: I1 Position */ -#define LCD_PAL152_I1_Msk (0x01UL << LCD_PAL152_I1_Pos) /*!< LCD PAL152: I1 Mask */ - -// --------------------------------------- LCD_PAL153 ------------------------------------------- -#define LCD_PAL153_R04_0_Pos 0 /*!< LCD PAL153: R04_0 Position */ -#define LCD_PAL153_R04_0_Msk (0x1fUL << LCD_PAL153_R04_0_Pos) /*!< LCD PAL153: R04_0 Mask */ -#define LCD_PAL153_G04_0_Pos 5 /*!< LCD PAL153: G04_0 Position */ -#define LCD_PAL153_G04_0_Msk (0x1fUL << LCD_PAL153_G04_0_Pos) /*!< LCD PAL153: G04_0 Mask */ -#define LCD_PAL153_B04_0_Pos 10 /*!< LCD PAL153: B04_0 Position */ -#define LCD_PAL153_B04_0_Msk (0x1fUL << LCD_PAL153_B04_0_Pos) /*!< LCD PAL153: B04_0 Mask */ -#define LCD_PAL153_I0_Pos 15 /*!< LCD PAL153: I0 Position */ -#define LCD_PAL153_I0_Msk (0x01UL << LCD_PAL153_I0_Pos) /*!< LCD PAL153: I0 Mask */ -#define LCD_PAL153_R14_0_Pos 16 /*!< LCD PAL153: R14_0 Position */ -#define LCD_PAL153_R14_0_Msk (0x1fUL << LCD_PAL153_R14_0_Pos) /*!< LCD PAL153: R14_0 Mask */ -#define LCD_PAL153_G14_0_Pos 21 /*!< LCD PAL153: G14_0 Position */ -#define LCD_PAL153_G14_0_Msk (0x1fUL << LCD_PAL153_G14_0_Pos) /*!< LCD PAL153: G14_0 Mask */ -#define LCD_PAL153_B14_0_Pos 26 /*!< LCD PAL153: B14_0 Position */ -#define LCD_PAL153_B14_0_Msk (0x1fUL << LCD_PAL153_B14_0_Pos) /*!< LCD PAL153: B14_0 Mask */ -#define LCD_PAL153_I1_Pos 31 /*!< LCD PAL153: I1 Position */ -#define LCD_PAL153_I1_Msk (0x01UL << LCD_PAL153_I1_Pos) /*!< LCD PAL153: I1 Mask */ - -// --------------------------------------- LCD_PAL154 ------------------------------------------- -#define LCD_PAL154_R04_0_Pos 0 /*!< LCD PAL154: R04_0 Position */ -#define LCD_PAL154_R04_0_Msk (0x1fUL << LCD_PAL154_R04_0_Pos) /*!< LCD PAL154: R04_0 Mask */ -#define LCD_PAL154_G04_0_Pos 5 /*!< LCD PAL154: G04_0 Position */ -#define LCD_PAL154_G04_0_Msk (0x1fUL << LCD_PAL154_G04_0_Pos) /*!< LCD PAL154: G04_0 Mask */ -#define LCD_PAL154_B04_0_Pos 10 /*!< LCD PAL154: B04_0 Position */ -#define LCD_PAL154_B04_0_Msk (0x1fUL << LCD_PAL154_B04_0_Pos) /*!< LCD PAL154: B04_0 Mask */ -#define LCD_PAL154_I0_Pos 15 /*!< LCD PAL154: I0 Position */ -#define LCD_PAL154_I0_Msk (0x01UL << LCD_PAL154_I0_Pos) /*!< LCD PAL154: I0 Mask */ -#define LCD_PAL154_R14_0_Pos 16 /*!< LCD PAL154: R14_0 Position */ -#define LCD_PAL154_R14_0_Msk (0x1fUL << LCD_PAL154_R14_0_Pos) /*!< LCD PAL154: R14_0 Mask */ -#define LCD_PAL154_G14_0_Pos 21 /*!< LCD PAL154: G14_0 Position */ -#define LCD_PAL154_G14_0_Msk (0x1fUL << LCD_PAL154_G14_0_Pos) /*!< LCD PAL154: G14_0 Mask */ -#define LCD_PAL154_B14_0_Pos 26 /*!< LCD PAL154: B14_0 Position */ -#define LCD_PAL154_B14_0_Msk (0x1fUL << LCD_PAL154_B14_0_Pos) /*!< LCD PAL154: B14_0 Mask */ -#define LCD_PAL154_I1_Pos 31 /*!< LCD PAL154: I1 Position */ -#define LCD_PAL154_I1_Msk (0x01UL << LCD_PAL154_I1_Pos) /*!< LCD PAL154: I1 Mask */ - -// --------------------------------------- LCD_PAL155 ------------------------------------------- -#define LCD_PAL155_R04_0_Pos 0 /*!< LCD PAL155: R04_0 Position */ -#define LCD_PAL155_R04_0_Msk (0x1fUL << LCD_PAL155_R04_0_Pos) /*!< LCD PAL155: R04_0 Mask */ -#define LCD_PAL155_G04_0_Pos 5 /*!< LCD PAL155: G04_0 Position */ -#define LCD_PAL155_G04_0_Msk (0x1fUL << LCD_PAL155_G04_0_Pos) /*!< LCD PAL155: G04_0 Mask */ -#define LCD_PAL155_B04_0_Pos 10 /*!< LCD PAL155: B04_0 Position */ -#define LCD_PAL155_B04_0_Msk (0x1fUL << LCD_PAL155_B04_0_Pos) /*!< LCD PAL155: B04_0 Mask */ -#define LCD_PAL155_I0_Pos 15 /*!< LCD PAL155: I0 Position */ -#define LCD_PAL155_I0_Msk (0x01UL << LCD_PAL155_I0_Pos) /*!< LCD PAL155: I0 Mask */ -#define LCD_PAL155_R14_0_Pos 16 /*!< LCD PAL155: R14_0 Position */ -#define LCD_PAL155_R14_0_Msk (0x1fUL << LCD_PAL155_R14_0_Pos) /*!< LCD PAL155: R14_0 Mask */ -#define LCD_PAL155_G14_0_Pos 21 /*!< LCD PAL155: G14_0 Position */ -#define LCD_PAL155_G14_0_Msk (0x1fUL << LCD_PAL155_G14_0_Pos) /*!< LCD PAL155: G14_0 Mask */ -#define LCD_PAL155_B14_0_Pos 26 /*!< LCD PAL155: B14_0 Position */ -#define LCD_PAL155_B14_0_Msk (0x1fUL << LCD_PAL155_B14_0_Pos) /*!< LCD PAL155: B14_0 Mask */ -#define LCD_PAL155_I1_Pos 31 /*!< LCD PAL155: I1 Position */ -#define LCD_PAL155_I1_Msk (0x01UL << LCD_PAL155_I1_Pos) /*!< LCD PAL155: I1 Mask */ - -// --------------------------------------- LCD_PAL156 ------------------------------------------- -#define LCD_PAL156_R04_0_Pos 0 /*!< LCD PAL156: R04_0 Position */ -#define LCD_PAL156_R04_0_Msk (0x1fUL << LCD_PAL156_R04_0_Pos) /*!< LCD PAL156: R04_0 Mask */ -#define LCD_PAL156_G04_0_Pos 5 /*!< LCD PAL156: G04_0 Position */ -#define LCD_PAL156_G04_0_Msk (0x1fUL << LCD_PAL156_G04_0_Pos) /*!< LCD PAL156: G04_0 Mask */ -#define LCD_PAL156_B04_0_Pos 10 /*!< LCD PAL156: B04_0 Position */ -#define LCD_PAL156_B04_0_Msk (0x1fUL << LCD_PAL156_B04_0_Pos) /*!< LCD PAL156: B04_0 Mask */ -#define LCD_PAL156_I0_Pos 15 /*!< LCD PAL156: I0 Position */ -#define LCD_PAL156_I0_Msk (0x01UL << LCD_PAL156_I0_Pos) /*!< LCD PAL156: I0 Mask */ -#define LCD_PAL156_R14_0_Pos 16 /*!< LCD PAL156: R14_0 Position */ -#define LCD_PAL156_R14_0_Msk (0x1fUL << LCD_PAL156_R14_0_Pos) /*!< LCD PAL156: R14_0 Mask */ -#define LCD_PAL156_G14_0_Pos 21 /*!< LCD PAL156: G14_0 Position */ -#define LCD_PAL156_G14_0_Msk (0x1fUL << LCD_PAL156_G14_0_Pos) /*!< LCD PAL156: G14_0 Mask */ -#define LCD_PAL156_B14_0_Pos 26 /*!< LCD PAL156: B14_0 Position */ -#define LCD_PAL156_B14_0_Msk (0x1fUL << LCD_PAL156_B14_0_Pos) /*!< LCD PAL156: B14_0 Mask */ -#define LCD_PAL156_I1_Pos 31 /*!< LCD PAL156: I1 Position */ -#define LCD_PAL156_I1_Msk (0x01UL << LCD_PAL156_I1_Pos) /*!< LCD PAL156: I1 Mask */ - -// --------------------------------------- LCD_PAL157 ------------------------------------------- -#define LCD_PAL157_R04_0_Pos 0 /*!< LCD PAL157: R04_0 Position */ -#define LCD_PAL157_R04_0_Msk (0x1fUL << LCD_PAL157_R04_0_Pos) /*!< LCD PAL157: R04_0 Mask */ -#define LCD_PAL157_G04_0_Pos 5 /*!< LCD PAL157: G04_0 Position */ -#define LCD_PAL157_G04_0_Msk (0x1fUL << LCD_PAL157_G04_0_Pos) /*!< LCD PAL157: G04_0 Mask */ -#define LCD_PAL157_B04_0_Pos 10 /*!< LCD PAL157: B04_0 Position */ -#define LCD_PAL157_B04_0_Msk (0x1fUL << LCD_PAL157_B04_0_Pos) /*!< LCD PAL157: B04_0 Mask */ -#define LCD_PAL157_I0_Pos 15 /*!< LCD PAL157: I0 Position */ -#define LCD_PAL157_I0_Msk (0x01UL << LCD_PAL157_I0_Pos) /*!< LCD PAL157: I0 Mask */ -#define LCD_PAL157_R14_0_Pos 16 /*!< LCD PAL157: R14_0 Position */ -#define LCD_PAL157_R14_0_Msk (0x1fUL << LCD_PAL157_R14_0_Pos) /*!< LCD PAL157: R14_0 Mask */ -#define LCD_PAL157_G14_0_Pos 21 /*!< LCD PAL157: G14_0 Position */ -#define LCD_PAL157_G14_0_Msk (0x1fUL << LCD_PAL157_G14_0_Pos) /*!< LCD PAL157: G14_0 Mask */ -#define LCD_PAL157_B14_0_Pos 26 /*!< LCD PAL157: B14_0 Position */ -#define LCD_PAL157_B14_0_Msk (0x1fUL << LCD_PAL157_B14_0_Pos) /*!< LCD PAL157: B14_0 Mask */ -#define LCD_PAL157_I1_Pos 31 /*!< LCD PAL157: I1 Position */ -#define LCD_PAL157_I1_Msk (0x01UL << LCD_PAL157_I1_Pos) /*!< LCD PAL157: I1 Mask */ - -// --------------------------------------- LCD_PAL158 ------------------------------------------- -#define LCD_PAL158_R04_0_Pos 0 /*!< LCD PAL158: R04_0 Position */ -#define LCD_PAL158_R04_0_Msk (0x1fUL << LCD_PAL158_R04_0_Pos) /*!< LCD PAL158: R04_0 Mask */ -#define LCD_PAL158_G04_0_Pos 5 /*!< LCD PAL158: G04_0 Position */ -#define LCD_PAL158_G04_0_Msk (0x1fUL << LCD_PAL158_G04_0_Pos) /*!< LCD PAL158: G04_0 Mask */ -#define LCD_PAL158_B04_0_Pos 10 /*!< LCD PAL158: B04_0 Position */ -#define LCD_PAL158_B04_0_Msk (0x1fUL << LCD_PAL158_B04_0_Pos) /*!< LCD PAL158: B04_0 Mask */ -#define LCD_PAL158_I0_Pos 15 /*!< LCD PAL158: I0 Position */ -#define LCD_PAL158_I0_Msk (0x01UL << LCD_PAL158_I0_Pos) /*!< LCD PAL158: I0 Mask */ -#define LCD_PAL158_R14_0_Pos 16 /*!< LCD PAL158: R14_0 Position */ -#define LCD_PAL158_R14_0_Msk (0x1fUL << LCD_PAL158_R14_0_Pos) /*!< LCD PAL158: R14_0 Mask */ -#define LCD_PAL158_G14_0_Pos 21 /*!< LCD PAL158: G14_0 Position */ -#define LCD_PAL158_G14_0_Msk (0x1fUL << LCD_PAL158_G14_0_Pos) /*!< LCD PAL158: G14_0 Mask */ -#define LCD_PAL158_B14_0_Pos 26 /*!< LCD PAL158: B14_0 Position */ -#define LCD_PAL158_B14_0_Msk (0x1fUL << LCD_PAL158_B14_0_Pos) /*!< LCD PAL158: B14_0 Mask */ -#define LCD_PAL158_I1_Pos 31 /*!< LCD PAL158: I1 Position */ -#define LCD_PAL158_I1_Msk (0x01UL << LCD_PAL158_I1_Pos) /*!< LCD PAL158: I1 Mask */ - -// --------------------------------------- LCD_PAL159 ------------------------------------------- -#define LCD_PAL159_R04_0_Pos 0 /*!< LCD PAL159: R04_0 Position */ -#define LCD_PAL159_R04_0_Msk (0x1fUL << LCD_PAL159_R04_0_Pos) /*!< LCD PAL159: R04_0 Mask */ -#define LCD_PAL159_G04_0_Pos 5 /*!< LCD PAL159: G04_0 Position */ -#define LCD_PAL159_G04_0_Msk (0x1fUL << LCD_PAL159_G04_0_Pos) /*!< LCD PAL159: G04_0 Mask */ -#define LCD_PAL159_B04_0_Pos 10 /*!< LCD PAL159: B04_0 Position */ -#define LCD_PAL159_B04_0_Msk (0x1fUL << LCD_PAL159_B04_0_Pos) /*!< LCD PAL159: B04_0 Mask */ -#define LCD_PAL159_I0_Pos 15 /*!< LCD PAL159: I0 Position */ -#define LCD_PAL159_I0_Msk (0x01UL << LCD_PAL159_I0_Pos) /*!< LCD PAL159: I0 Mask */ -#define LCD_PAL159_R14_0_Pos 16 /*!< LCD PAL159: R14_0 Position */ -#define LCD_PAL159_R14_0_Msk (0x1fUL << LCD_PAL159_R14_0_Pos) /*!< LCD PAL159: R14_0 Mask */ -#define LCD_PAL159_G14_0_Pos 21 /*!< LCD PAL159: G14_0 Position */ -#define LCD_PAL159_G14_0_Msk (0x1fUL << LCD_PAL159_G14_0_Pos) /*!< LCD PAL159: G14_0 Mask */ -#define LCD_PAL159_B14_0_Pos 26 /*!< LCD PAL159: B14_0 Position */ -#define LCD_PAL159_B14_0_Msk (0x1fUL << LCD_PAL159_B14_0_Pos) /*!< LCD PAL159: B14_0 Mask */ -#define LCD_PAL159_I1_Pos 31 /*!< LCD PAL159: I1 Position */ -#define LCD_PAL159_I1_Msk (0x01UL << LCD_PAL159_I1_Pos) /*!< LCD PAL159: I1 Mask */ - -// --------------------------------------- LCD_PAL160 ------------------------------------------- -#define LCD_PAL160_R04_0_Pos 0 /*!< LCD PAL160: R04_0 Position */ -#define LCD_PAL160_R04_0_Msk (0x1fUL << LCD_PAL160_R04_0_Pos) /*!< LCD PAL160: R04_0 Mask */ -#define LCD_PAL160_G04_0_Pos 5 /*!< LCD PAL160: G04_0 Position */ -#define LCD_PAL160_G04_0_Msk (0x1fUL << LCD_PAL160_G04_0_Pos) /*!< LCD PAL160: G04_0 Mask */ -#define LCD_PAL160_B04_0_Pos 10 /*!< LCD PAL160: B04_0 Position */ -#define LCD_PAL160_B04_0_Msk (0x1fUL << LCD_PAL160_B04_0_Pos) /*!< LCD PAL160: B04_0 Mask */ -#define LCD_PAL160_I0_Pos 15 /*!< LCD PAL160: I0 Position */ -#define LCD_PAL160_I0_Msk (0x01UL << LCD_PAL160_I0_Pos) /*!< LCD PAL160: I0 Mask */ -#define LCD_PAL160_R14_0_Pos 16 /*!< LCD PAL160: R14_0 Position */ -#define LCD_PAL160_R14_0_Msk (0x1fUL << LCD_PAL160_R14_0_Pos) /*!< LCD PAL160: R14_0 Mask */ -#define LCD_PAL160_G14_0_Pos 21 /*!< LCD PAL160: G14_0 Position */ -#define LCD_PAL160_G14_0_Msk (0x1fUL << LCD_PAL160_G14_0_Pos) /*!< LCD PAL160: G14_0 Mask */ -#define LCD_PAL160_B14_0_Pos 26 /*!< LCD PAL160: B14_0 Position */ -#define LCD_PAL160_B14_0_Msk (0x1fUL << LCD_PAL160_B14_0_Pos) /*!< LCD PAL160: B14_0 Mask */ -#define LCD_PAL160_I1_Pos 31 /*!< LCD PAL160: I1 Position */ -#define LCD_PAL160_I1_Msk (0x01UL << LCD_PAL160_I1_Pos) /*!< LCD PAL160: I1 Mask */ - -// --------------------------------------- LCD_PAL161 ------------------------------------------- -#define LCD_PAL161_R04_0_Pos 0 /*!< LCD PAL161: R04_0 Position */ -#define LCD_PAL161_R04_0_Msk (0x1fUL << LCD_PAL161_R04_0_Pos) /*!< LCD PAL161: R04_0 Mask */ -#define LCD_PAL161_G04_0_Pos 5 /*!< LCD PAL161: G04_0 Position */ -#define LCD_PAL161_G04_0_Msk (0x1fUL << LCD_PAL161_G04_0_Pos) /*!< LCD PAL161: G04_0 Mask */ -#define LCD_PAL161_B04_0_Pos 10 /*!< LCD PAL161: B04_0 Position */ -#define LCD_PAL161_B04_0_Msk (0x1fUL << LCD_PAL161_B04_0_Pos) /*!< LCD PAL161: B04_0 Mask */ -#define LCD_PAL161_I0_Pos 15 /*!< LCD PAL161: I0 Position */ -#define LCD_PAL161_I0_Msk (0x01UL << LCD_PAL161_I0_Pos) /*!< LCD PAL161: I0 Mask */ -#define LCD_PAL161_R14_0_Pos 16 /*!< LCD PAL161: R14_0 Position */ -#define LCD_PAL161_R14_0_Msk (0x1fUL << LCD_PAL161_R14_0_Pos) /*!< LCD PAL161: R14_0 Mask */ -#define LCD_PAL161_G14_0_Pos 21 /*!< LCD PAL161: G14_0 Position */ -#define LCD_PAL161_G14_0_Msk (0x1fUL << LCD_PAL161_G14_0_Pos) /*!< LCD PAL161: G14_0 Mask */ -#define LCD_PAL161_B14_0_Pos 26 /*!< LCD PAL161: B14_0 Position */ -#define LCD_PAL161_B14_0_Msk (0x1fUL << LCD_PAL161_B14_0_Pos) /*!< LCD PAL161: B14_0 Mask */ -#define LCD_PAL161_I1_Pos 31 /*!< LCD PAL161: I1 Position */ -#define LCD_PAL161_I1_Msk (0x01UL << LCD_PAL161_I1_Pos) /*!< LCD PAL161: I1 Mask */ - -// --------------------------------------- LCD_PAL162 ------------------------------------------- -#define LCD_PAL162_R04_0_Pos 0 /*!< LCD PAL162: R04_0 Position */ -#define LCD_PAL162_R04_0_Msk (0x1fUL << LCD_PAL162_R04_0_Pos) /*!< LCD PAL162: R04_0 Mask */ -#define LCD_PAL162_G04_0_Pos 5 /*!< LCD PAL162: G04_0 Position */ -#define LCD_PAL162_G04_0_Msk (0x1fUL << LCD_PAL162_G04_0_Pos) /*!< LCD PAL162: G04_0 Mask */ -#define LCD_PAL162_B04_0_Pos 10 /*!< LCD PAL162: B04_0 Position */ -#define LCD_PAL162_B04_0_Msk (0x1fUL << LCD_PAL162_B04_0_Pos) /*!< LCD PAL162: B04_0 Mask */ -#define LCD_PAL162_I0_Pos 15 /*!< LCD PAL162: I0 Position */ -#define LCD_PAL162_I0_Msk (0x01UL << LCD_PAL162_I0_Pos) /*!< LCD PAL162: I0 Mask */ -#define LCD_PAL162_R14_0_Pos 16 /*!< LCD PAL162: R14_0 Position */ -#define LCD_PAL162_R14_0_Msk (0x1fUL << LCD_PAL162_R14_0_Pos) /*!< LCD PAL162: R14_0 Mask */ -#define LCD_PAL162_G14_0_Pos 21 /*!< LCD PAL162: G14_0 Position */ -#define LCD_PAL162_G14_0_Msk (0x1fUL << LCD_PAL162_G14_0_Pos) /*!< LCD PAL162: G14_0 Mask */ -#define LCD_PAL162_B14_0_Pos 26 /*!< LCD PAL162: B14_0 Position */ -#define LCD_PAL162_B14_0_Msk (0x1fUL << LCD_PAL162_B14_0_Pos) /*!< LCD PAL162: B14_0 Mask */ -#define LCD_PAL162_I1_Pos 31 /*!< LCD PAL162: I1 Position */ -#define LCD_PAL162_I1_Msk (0x01UL << LCD_PAL162_I1_Pos) /*!< LCD PAL162: I1 Mask */ - -// --------------------------------------- LCD_PAL163 ------------------------------------------- -#define LCD_PAL163_R04_0_Pos 0 /*!< LCD PAL163: R04_0 Position */ -#define LCD_PAL163_R04_0_Msk (0x1fUL << LCD_PAL163_R04_0_Pos) /*!< LCD PAL163: R04_0 Mask */ -#define LCD_PAL163_G04_0_Pos 5 /*!< LCD PAL163: G04_0 Position */ -#define LCD_PAL163_G04_0_Msk (0x1fUL << LCD_PAL163_G04_0_Pos) /*!< LCD PAL163: G04_0 Mask */ -#define LCD_PAL163_B04_0_Pos 10 /*!< LCD PAL163: B04_0 Position */ -#define LCD_PAL163_B04_0_Msk (0x1fUL << LCD_PAL163_B04_0_Pos) /*!< LCD PAL163: B04_0 Mask */ -#define LCD_PAL163_I0_Pos 15 /*!< LCD PAL163: I0 Position */ -#define LCD_PAL163_I0_Msk (0x01UL << LCD_PAL163_I0_Pos) /*!< LCD PAL163: I0 Mask */ -#define LCD_PAL163_R14_0_Pos 16 /*!< LCD PAL163: R14_0 Position */ -#define LCD_PAL163_R14_0_Msk (0x1fUL << LCD_PAL163_R14_0_Pos) /*!< LCD PAL163: R14_0 Mask */ -#define LCD_PAL163_G14_0_Pos 21 /*!< LCD PAL163: G14_0 Position */ -#define LCD_PAL163_G14_0_Msk (0x1fUL << LCD_PAL163_G14_0_Pos) /*!< LCD PAL163: G14_0 Mask */ -#define LCD_PAL163_B14_0_Pos 26 /*!< LCD PAL163: B14_0 Position */ -#define LCD_PAL163_B14_0_Msk (0x1fUL << LCD_PAL163_B14_0_Pos) /*!< LCD PAL163: B14_0 Mask */ -#define LCD_PAL163_I1_Pos 31 /*!< LCD PAL163: I1 Position */ -#define LCD_PAL163_I1_Msk (0x01UL << LCD_PAL163_I1_Pos) /*!< LCD PAL163: I1 Mask */ - -// --------------------------------------- LCD_PAL164 ------------------------------------------- -#define LCD_PAL164_R04_0_Pos 0 /*!< LCD PAL164: R04_0 Position */ -#define LCD_PAL164_R04_0_Msk (0x1fUL << LCD_PAL164_R04_0_Pos) /*!< LCD PAL164: R04_0 Mask */ -#define LCD_PAL164_G04_0_Pos 5 /*!< LCD PAL164: G04_0 Position */ -#define LCD_PAL164_G04_0_Msk (0x1fUL << LCD_PAL164_G04_0_Pos) /*!< LCD PAL164: G04_0 Mask */ -#define LCD_PAL164_B04_0_Pos 10 /*!< LCD PAL164: B04_0 Position */ -#define LCD_PAL164_B04_0_Msk (0x1fUL << LCD_PAL164_B04_0_Pos) /*!< LCD PAL164: B04_0 Mask */ -#define LCD_PAL164_I0_Pos 15 /*!< LCD PAL164: I0 Position */ -#define LCD_PAL164_I0_Msk (0x01UL << LCD_PAL164_I0_Pos) /*!< LCD PAL164: I0 Mask */ -#define LCD_PAL164_R14_0_Pos 16 /*!< LCD PAL164: R14_0 Position */ -#define LCD_PAL164_R14_0_Msk (0x1fUL << LCD_PAL164_R14_0_Pos) /*!< LCD PAL164: R14_0 Mask */ -#define LCD_PAL164_G14_0_Pos 21 /*!< LCD PAL164: G14_0 Position */ -#define LCD_PAL164_G14_0_Msk (0x1fUL << LCD_PAL164_G14_0_Pos) /*!< LCD PAL164: G14_0 Mask */ -#define LCD_PAL164_B14_0_Pos 26 /*!< LCD PAL164: B14_0 Position */ -#define LCD_PAL164_B14_0_Msk (0x1fUL << LCD_PAL164_B14_0_Pos) /*!< LCD PAL164: B14_0 Mask */ -#define LCD_PAL164_I1_Pos 31 /*!< LCD PAL164: I1 Position */ -#define LCD_PAL164_I1_Msk (0x01UL << LCD_PAL164_I1_Pos) /*!< LCD PAL164: I1 Mask */ - -// --------------------------------------- LCD_PAL165 ------------------------------------------- -#define LCD_PAL165_R04_0_Pos 0 /*!< LCD PAL165: R04_0 Position */ -#define LCD_PAL165_R04_0_Msk (0x1fUL << LCD_PAL165_R04_0_Pos) /*!< LCD PAL165: R04_0 Mask */ -#define LCD_PAL165_G04_0_Pos 5 /*!< LCD PAL165: G04_0 Position */ -#define LCD_PAL165_G04_0_Msk (0x1fUL << LCD_PAL165_G04_0_Pos) /*!< LCD PAL165: G04_0 Mask */ -#define LCD_PAL165_B04_0_Pos 10 /*!< LCD PAL165: B04_0 Position */ -#define LCD_PAL165_B04_0_Msk (0x1fUL << LCD_PAL165_B04_0_Pos) /*!< LCD PAL165: B04_0 Mask */ -#define LCD_PAL165_I0_Pos 15 /*!< LCD PAL165: I0 Position */ -#define LCD_PAL165_I0_Msk (0x01UL << LCD_PAL165_I0_Pos) /*!< LCD PAL165: I0 Mask */ -#define LCD_PAL165_R14_0_Pos 16 /*!< LCD PAL165: R14_0 Position */ -#define LCD_PAL165_R14_0_Msk (0x1fUL << LCD_PAL165_R14_0_Pos) /*!< LCD PAL165: R14_0 Mask */ -#define LCD_PAL165_G14_0_Pos 21 /*!< LCD PAL165: G14_0 Position */ -#define LCD_PAL165_G14_0_Msk (0x1fUL << LCD_PAL165_G14_0_Pos) /*!< LCD PAL165: G14_0 Mask */ -#define LCD_PAL165_B14_0_Pos 26 /*!< LCD PAL165: B14_0 Position */ -#define LCD_PAL165_B14_0_Msk (0x1fUL << LCD_PAL165_B14_0_Pos) /*!< LCD PAL165: B14_0 Mask */ -#define LCD_PAL165_I1_Pos 31 /*!< LCD PAL165: I1 Position */ -#define LCD_PAL165_I1_Msk (0x01UL << LCD_PAL165_I1_Pos) /*!< LCD PAL165: I1 Mask */ - -// --------------------------------------- LCD_PAL166 ------------------------------------------- -#define LCD_PAL166_R04_0_Pos 0 /*!< LCD PAL166: R04_0 Position */ -#define LCD_PAL166_R04_0_Msk (0x1fUL << LCD_PAL166_R04_0_Pos) /*!< LCD PAL166: R04_0 Mask */ -#define LCD_PAL166_G04_0_Pos 5 /*!< LCD PAL166: G04_0 Position */ -#define LCD_PAL166_G04_0_Msk (0x1fUL << LCD_PAL166_G04_0_Pos) /*!< LCD PAL166: G04_0 Mask */ -#define LCD_PAL166_B04_0_Pos 10 /*!< LCD PAL166: B04_0 Position */ -#define LCD_PAL166_B04_0_Msk (0x1fUL << LCD_PAL166_B04_0_Pos) /*!< LCD PAL166: B04_0 Mask */ -#define LCD_PAL166_I0_Pos 15 /*!< LCD PAL166: I0 Position */ -#define LCD_PAL166_I0_Msk (0x01UL << LCD_PAL166_I0_Pos) /*!< LCD PAL166: I0 Mask */ -#define LCD_PAL166_R14_0_Pos 16 /*!< LCD PAL166: R14_0 Position */ -#define LCD_PAL166_R14_0_Msk (0x1fUL << LCD_PAL166_R14_0_Pos) /*!< LCD PAL166: R14_0 Mask */ -#define LCD_PAL166_G14_0_Pos 21 /*!< LCD PAL166: G14_0 Position */ -#define LCD_PAL166_G14_0_Msk (0x1fUL << LCD_PAL166_G14_0_Pos) /*!< LCD PAL166: G14_0 Mask */ -#define LCD_PAL166_B14_0_Pos 26 /*!< LCD PAL166: B14_0 Position */ -#define LCD_PAL166_B14_0_Msk (0x1fUL << LCD_PAL166_B14_0_Pos) /*!< LCD PAL166: B14_0 Mask */ -#define LCD_PAL166_I1_Pos 31 /*!< LCD PAL166: I1 Position */ -#define LCD_PAL166_I1_Msk (0x01UL << LCD_PAL166_I1_Pos) /*!< LCD PAL166: I1 Mask */ - -// --------------------------------------- LCD_PAL167 ------------------------------------------- -#define LCD_PAL167_R04_0_Pos 0 /*!< LCD PAL167: R04_0 Position */ -#define LCD_PAL167_R04_0_Msk (0x1fUL << LCD_PAL167_R04_0_Pos) /*!< LCD PAL167: R04_0 Mask */ -#define LCD_PAL167_G04_0_Pos 5 /*!< LCD PAL167: G04_0 Position */ -#define LCD_PAL167_G04_0_Msk (0x1fUL << LCD_PAL167_G04_0_Pos) /*!< LCD PAL167: G04_0 Mask */ -#define LCD_PAL167_B04_0_Pos 10 /*!< LCD PAL167: B04_0 Position */ -#define LCD_PAL167_B04_0_Msk (0x1fUL << LCD_PAL167_B04_0_Pos) /*!< LCD PAL167: B04_0 Mask */ -#define LCD_PAL167_I0_Pos 15 /*!< LCD PAL167: I0 Position */ -#define LCD_PAL167_I0_Msk (0x01UL << LCD_PAL167_I0_Pos) /*!< LCD PAL167: I0 Mask */ -#define LCD_PAL167_R14_0_Pos 16 /*!< LCD PAL167: R14_0 Position */ -#define LCD_PAL167_R14_0_Msk (0x1fUL << LCD_PAL167_R14_0_Pos) /*!< LCD PAL167: R14_0 Mask */ -#define LCD_PAL167_G14_0_Pos 21 /*!< LCD PAL167: G14_0 Position */ -#define LCD_PAL167_G14_0_Msk (0x1fUL << LCD_PAL167_G14_0_Pos) /*!< LCD PAL167: G14_0 Mask */ -#define LCD_PAL167_B14_0_Pos 26 /*!< LCD PAL167: B14_0 Position */ -#define LCD_PAL167_B14_0_Msk (0x1fUL << LCD_PAL167_B14_0_Pos) /*!< LCD PAL167: B14_0 Mask */ -#define LCD_PAL167_I1_Pos 31 /*!< LCD PAL167: I1 Position */ -#define LCD_PAL167_I1_Msk (0x01UL << LCD_PAL167_I1_Pos) /*!< LCD PAL167: I1 Mask */ - -// --------------------------------------- LCD_PAL168 ------------------------------------------- -#define LCD_PAL168_R04_0_Pos 0 /*!< LCD PAL168: R04_0 Position */ -#define LCD_PAL168_R04_0_Msk (0x1fUL << LCD_PAL168_R04_0_Pos) /*!< LCD PAL168: R04_0 Mask */ -#define LCD_PAL168_G04_0_Pos 5 /*!< LCD PAL168: G04_0 Position */ -#define LCD_PAL168_G04_0_Msk (0x1fUL << LCD_PAL168_G04_0_Pos) /*!< LCD PAL168: G04_0 Mask */ -#define LCD_PAL168_B04_0_Pos 10 /*!< LCD PAL168: B04_0 Position */ -#define LCD_PAL168_B04_0_Msk (0x1fUL << LCD_PAL168_B04_0_Pos) /*!< LCD PAL168: B04_0 Mask */ -#define LCD_PAL168_I0_Pos 15 /*!< LCD PAL168: I0 Position */ -#define LCD_PAL168_I0_Msk (0x01UL << LCD_PAL168_I0_Pos) /*!< LCD PAL168: I0 Mask */ -#define LCD_PAL168_R14_0_Pos 16 /*!< LCD PAL168: R14_0 Position */ -#define LCD_PAL168_R14_0_Msk (0x1fUL << LCD_PAL168_R14_0_Pos) /*!< LCD PAL168: R14_0 Mask */ -#define LCD_PAL168_G14_0_Pos 21 /*!< LCD PAL168: G14_0 Position */ -#define LCD_PAL168_G14_0_Msk (0x1fUL << LCD_PAL168_G14_0_Pos) /*!< LCD PAL168: G14_0 Mask */ -#define LCD_PAL168_B14_0_Pos 26 /*!< LCD PAL168: B14_0 Position */ -#define LCD_PAL168_B14_0_Msk (0x1fUL << LCD_PAL168_B14_0_Pos) /*!< LCD PAL168: B14_0 Mask */ -#define LCD_PAL168_I1_Pos 31 /*!< LCD PAL168: I1 Position */ -#define LCD_PAL168_I1_Msk (0x01UL << LCD_PAL168_I1_Pos) /*!< LCD PAL168: I1 Mask */ - -// --------------------------------------- LCD_PAL169 ------------------------------------------- -#define LCD_PAL169_R04_0_Pos 0 /*!< LCD PAL169: R04_0 Position */ -#define LCD_PAL169_R04_0_Msk (0x1fUL << LCD_PAL169_R04_0_Pos) /*!< LCD PAL169: R04_0 Mask */ -#define LCD_PAL169_G04_0_Pos 5 /*!< LCD PAL169: G04_0 Position */ -#define LCD_PAL169_G04_0_Msk (0x1fUL << LCD_PAL169_G04_0_Pos) /*!< LCD PAL169: G04_0 Mask */ -#define LCD_PAL169_B04_0_Pos 10 /*!< LCD PAL169: B04_0 Position */ -#define LCD_PAL169_B04_0_Msk (0x1fUL << LCD_PAL169_B04_0_Pos) /*!< LCD PAL169: B04_0 Mask */ -#define LCD_PAL169_I0_Pos 15 /*!< LCD PAL169: I0 Position */ -#define LCD_PAL169_I0_Msk (0x01UL << LCD_PAL169_I0_Pos) /*!< LCD PAL169: I0 Mask */ -#define LCD_PAL169_R14_0_Pos 16 /*!< LCD PAL169: R14_0 Position */ -#define LCD_PAL169_R14_0_Msk (0x1fUL << LCD_PAL169_R14_0_Pos) /*!< LCD PAL169: R14_0 Mask */ -#define LCD_PAL169_G14_0_Pos 21 /*!< LCD PAL169: G14_0 Position */ -#define LCD_PAL169_G14_0_Msk (0x1fUL << LCD_PAL169_G14_0_Pos) /*!< LCD PAL169: G14_0 Mask */ -#define LCD_PAL169_B14_0_Pos 26 /*!< LCD PAL169: B14_0 Position */ -#define LCD_PAL169_B14_0_Msk (0x1fUL << LCD_PAL169_B14_0_Pos) /*!< LCD PAL169: B14_0 Mask */ -#define LCD_PAL169_I1_Pos 31 /*!< LCD PAL169: I1 Position */ -#define LCD_PAL169_I1_Msk (0x01UL << LCD_PAL169_I1_Pos) /*!< LCD PAL169: I1 Mask */ - -// --------------------------------------- LCD_PAL170 ------------------------------------------- -#define LCD_PAL170_R04_0_Pos 0 /*!< LCD PAL170: R04_0 Position */ -#define LCD_PAL170_R04_0_Msk (0x1fUL << LCD_PAL170_R04_0_Pos) /*!< LCD PAL170: R04_0 Mask */ -#define LCD_PAL170_G04_0_Pos 5 /*!< LCD PAL170: G04_0 Position */ -#define LCD_PAL170_G04_0_Msk (0x1fUL << LCD_PAL170_G04_0_Pos) /*!< LCD PAL170: G04_0 Mask */ -#define LCD_PAL170_B04_0_Pos 10 /*!< LCD PAL170: B04_0 Position */ -#define LCD_PAL170_B04_0_Msk (0x1fUL << LCD_PAL170_B04_0_Pos) /*!< LCD PAL170: B04_0 Mask */ -#define LCD_PAL170_I0_Pos 15 /*!< LCD PAL170: I0 Position */ -#define LCD_PAL170_I0_Msk (0x01UL << LCD_PAL170_I0_Pos) /*!< LCD PAL170: I0 Mask */ -#define LCD_PAL170_R14_0_Pos 16 /*!< LCD PAL170: R14_0 Position */ -#define LCD_PAL170_R14_0_Msk (0x1fUL << LCD_PAL170_R14_0_Pos) /*!< LCD PAL170: R14_0 Mask */ -#define LCD_PAL170_G14_0_Pos 21 /*!< LCD PAL170: G14_0 Position */ -#define LCD_PAL170_G14_0_Msk (0x1fUL << LCD_PAL170_G14_0_Pos) /*!< LCD PAL170: G14_0 Mask */ -#define LCD_PAL170_B14_0_Pos 26 /*!< LCD PAL170: B14_0 Position */ -#define LCD_PAL170_B14_0_Msk (0x1fUL << LCD_PAL170_B14_0_Pos) /*!< LCD PAL170: B14_0 Mask */ -#define LCD_PAL170_I1_Pos 31 /*!< LCD PAL170: I1 Position */ -#define LCD_PAL170_I1_Msk (0x01UL << LCD_PAL170_I1_Pos) /*!< LCD PAL170: I1 Mask */ - -// --------------------------------------- LCD_PAL171 ------------------------------------------- -#define LCD_PAL171_R04_0_Pos 0 /*!< LCD PAL171: R04_0 Position */ -#define LCD_PAL171_R04_0_Msk (0x1fUL << LCD_PAL171_R04_0_Pos) /*!< LCD PAL171: R04_0 Mask */ -#define LCD_PAL171_G04_0_Pos 5 /*!< LCD PAL171: G04_0 Position */ -#define LCD_PAL171_G04_0_Msk (0x1fUL << LCD_PAL171_G04_0_Pos) /*!< LCD PAL171: G04_0 Mask */ -#define LCD_PAL171_B04_0_Pos 10 /*!< LCD PAL171: B04_0 Position */ -#define LCD_PAL171_B04_0_Msk (0x1fUL << LCD_PAL171_B04_0_Pos) /*!< LCD PAL171: B04_0 Mask */ -#define LCD_PAL171_I0_Pos 15 /*!< LCD PAL171: I0 Position */ -#define LCD_PAL171_I0_Msk (0x01UL << LCD_PAL171_I0_Pos) /*!< LCD PAL171: I0 Mask */ -#define LCD_PAL171_R14_0_Pos 16 /*!< LCD PAL171: R14_0 Position */ -#define LCD_PAL171_R14_0_Msk (0x1fUL << LCD_PAL171_R14_0_Pos) /*!< LCD PAL171: R14_0 Mask */ -#define LCD_PAL171_G14_0_Pos 21 /*!< LCD PAL171: G14_0 Position */ -#define LCD_PAL171_G14_0_Msk (0x1fUL << LCD_PAL171_G14_0_Pos) /*!< LCD PAL171: G14_0 Mask */ -#define LCD_PAL171_B14_0_Pos 26 /*!< LCD PAL171: B14_0 Position */ -#define LCD_PAL171_B14_0_Msk (0x1fUL << LCD_PAL171_B14_0_Pos) /*!< LCD PAL171: B14_0 Mask */ -#define LCD_PAL171_I1_Pos 31 /*!< LCD PAL171: I1 Position */ -#define LCD_PAL171_I1_Msk (0x01UL << LCD_PAL171_I1_Pos) /*!< LCD PAL171: I1 Mask */ - -// --------------------------------------- LCD_PAL172 ------------------------------------------- -#define LCD_PAL172_R04_0_Pos 0 /*!< LCD PAL172: R04_0 Position */ -#define LCD_PAL172_R04_0_Msk (0x1fUL << LCD_PAL172_R04_0_Pos) /*!< LCD PAL172: R04_0 Mask */ -#define LCD_PAL172_G04_0_Pos 5 /*!< LCD PAL172: G04_0 Position */ -#define LCD_PAL172_G04_0_Msk (0x1fUL << LCD_PAL172_G04_0_Pos) /*!< LCD PAL172: G04_0 Mask */ -#define LCD_PAL172_B04_0_Pos 10 /*!< LCD PAL172: B04_0 Position */ -#define LCD_PAL172_B04_0_Msk (0x1fUL << LCD_PAL172_B04_0_Pos) /*!< LCD PAL172: B04_0 Mask */ -#define LCD_PAL172_I0_Pos 15 /*!< LCD PAL172: I0 Position */ -#define LCD_PAL172_I0_Msk (0x01UL << LCD_PAL172_I0_Pos) /*!< LCD PAL172: I0 Mask */ -#define LCD_PAL172_R14_0_Pos 16 /*!< LCD PAL172: R14_0 Position */ -#define LCD_PAL172_R14_0_Msk (0x1fUL << LCD_PAL172_R14_0_Pos) /*!< LCD PAL172: R14_0 Mask */ -#define LCD_PAL172_G14_0_Pos 21 /*!< LCD PAL172: G14_0 Position */ -#define LCD_PAL172_G14_0_Msk (0x1fUL << LCD_PAL172_G14_0_Pos) /*!< LCD PAL172: G14_0 Mask */ -#define LCD_PAL172_B14_0_Pos 26 /*!< LCD PAL172: B14_0 Position */ -#define LCD_PAL172_B14_0_Msk (0x1fUL << LCD_PAL172_B14_0_Pos) /*!< LCD PAL172: B14_0 Mask */ -#define LCD_PAL172_I1_Pos 31 /*!< LCD PAL172: I1 Position */ -#define LCD_PAL172_I1_Msk (0x01UL << LCD_PAL172_I1_Pos) /*!< LCD PAL172: I1 Mask */ - -// --------------------------------------- LCD_PAL173 ------------------------------------------- -#define LCD_PAL173_R04_0_Pos 0 /*!< LCD PAL173: R04_0 Position */ -#define LCD_PAL173_R04_0_Msk (0x1fUL << LCD_PAL173_R04_0_Pos) /*!< LCD PAL173: R04_0 Mask */ -#define LCD_PAL173_G04_0_Pos 5 /*!< LCD PAL173: G04_0 Position */ -#define LCD_PAL173_G04_0_Msk (0x1fUL << LCD_PAL173_G04_0_Pos) /*!< LCD PAL173: G04_0 Mask */ -#define LCD_PAL173_B04_0_Pos 10 /*!< LCD PAL173: B04_0 Position */ -#define LCD_PAL173_B04_0_Msk (0x1fUL << LCD_PAL173_B04_0_Pos) /*!< LCD PAL173: B04_0 Mask */ -#define LCD_PAL173_I0_Pos 15 /*!< LCD PAL173: I0 Position */ -#define LCD_PAL173_I0_Msk (0x01UL << LCD_PAL173_I0_Pos) /*!< LCD PAL173: I0 Mask */ -#define LCD_PAL173_R14_0_Pos 16 /*!< LCD PAL173: R14_0 Position */ -#define LCD_PAL173_R14_0_Msk (0x1fUL << LCD_PAL173_R14_0_Pos) /*!< LCD PAL173: R14_0 Mask */ -#define LCD_PAL173_G14_0_Pos 21 /*!< LCD PAL173: G14_0 Position */ -#define LCD_PAL173_G14_0_Msk (0x1fUL << LCD_PAL173_G14_0_Pos) /*!< LCD PAL173: G14_0 Mask */ -#define LCD_PAL173_B14_0_Pos 26 /*!< LCD PAL173: B14_0 Position */ -#define LCD_PAL173_B14_0_Msk (0x1fUL << LCD_PAL173_B14_0_Pos) /*!< LCD PAL173: B14_0 Mask */ -#define LCD_PAL173_I1_Pos 31 /*!< LCD PAL173: I1 Position */ -#define LCD_PAL173_I1_Msk (0x01UL << LCD_PAL173_I1_Pos) /*!< LCD PAL173: I1 Mask */ - -// --------------------------------------- LCD_PAL174 ------------------------------------------- -#define LCD_PAL174_R04_0_Pos 0 /*!< LCD PAL174: R04_0 Position */ -#define LCD_PAL174_R04_0_Msk (0x1fUL << LCD_PAL174_R04_0_Pos) /*!< LCD PAL174: R04_0 Mask */ -#define LCD_PAL174_G04_0_Pos 5 /*!< LCD PAL174: G04_0 Position */ -#define LCD_PAL174_G04_0_Msk (0x1fUL << LCD_PAL174_G04_0_Pos) /*!< LCD PAL174: G04_0 Mask */ -#define LCD_PAL174_B04_0_Pos 10 /*!< LCD PAL174: B04_0 Position */ -#define LCD_PAL174_B04_0_Msk (0x1fUL << LCD_PAL174_B04_0_Pos) /*!< LCD PAL174: B04_0 Mask */ -#define LCD_PAL174_I0_Pos 15 /*!< LCD PAL174: I0 Position */ -#define LCD_PAL174_I0_Msk (0x01UL << LCD_PAL174_I0_Pos) /*!< LCD PAL174: I0 Mask */ -#define LCD_PAL174_R14_0_Pos 16 /*!< LCD PAL174: R14_0 Position */ -#define LCD_PAL174_R14_0_Msk (0x1fUL << LCD_PAL174_R14_0_Pos) /*!< LCD PAL174: R14_0 Mask */ -#define LCD_PAL174_G14_0_Pos 21 /*!< LCD PAL174: G14_0 Position */ -#define LCD_PAL174_G14_0_Msk (0x1fUL << LCD_PAL174_G14_0_Pos) /*!< LCD PAL174: G14_0 Mask */ -#define LCD_PAL174_B14_0_Pos 26 /*!< LCD PAL174: B14_0 Position */ -#define LCD_PAL174_B14_0_Msk (0x1fUL << LCD_PAL174_B14_0_Pos) /*!< LCD PAL174: B14_0 Mask */ -#define LCD_PAL174_I1_Pos 31 /*!< LCD PAL174: I1 Position */ -#define LCD_PAL174_I1_Msk (0x01UL << LCD_PAL174_I1_Pos) /*!< LCD PAL174: I1 Mask */ - -// --------------------------------------- LCD_PAL175 ------------------------------------------- -#define LCD_PAL175_R04_0_Pos 0 /*!< LCD PAL175: R04_0 Position */ -#define LCD_PAL175_R04_0_Msk (0x1fUL << LCD_PAL175_R04_0_Pos) /*!< LCD PAL175: R04_0 Mask */ -#define LCD_PAL175_G04_0_Pos 5 /*!< LCD PAL175: G04_0 Position */ -#define LCD_PAL175_G04_0_Msk (0x1fUL << LCD_PAL175_G04_0_Pos) /*!< LCD PAL175: G04_0 Mask */ -#define LCD_PAL175_B04_0_Pos 10 /*!< LCD PAL175: B04_0 Position */ -#define LCD_PAL175_B04_0_Msk (0x1fUL << LCD_PAL175_B04_0_Pos) /*!< LCD PAL175: B04_0 Mask */ -#define LCD_PAL175_I0_Pos 15 /*!< LCD PAL175: I0 Position */ -#define LCD_PAL175_I0_Msk (0x01UL << LCD_PAL175_I0_Pos) /*!< LCD PAL175: I0 Mask */ -#define LCD_PAL175_R14_0_Pos 16 /*!< LCD PAL175: R14_0 Position */ -#define LCD_PAL175_R14_0_Msk (0x1fUL << LCD_PAL175_R14_0_Pos) /*!< LCD PAL175: R14_0 Mask */ -#define LCD_PAL175_G14_0_Pos 21 /*!< LCD PAL175: G14_0 Position */ -#define LCD_PAL175_G14_0_Msk (0x1fUL << LCD_PAL175_G14_0_Pos) /*!< LCD PAL175: G14_0 Mask */ -#define LCD_PAL175_B14_0_Pos 26 /*!< LCD PAL175: B14_0 Position */ -#define LCD_PAL175_B14_0_Msk (0x1fUL << LCD_PAL175_B14_0_Pos) /*!< LCD PAL175: B14_0 Mask */ -#define LCD_PAL175_I1_Pos 31 /*!< LCD PAL175: I1 Position */ -#define LCD_PAL175_I1_Msk (0x01UL << LCD_PAL175_I1_Pos) /*!< LCD PAL175: I1 Mask */ - -// --------------------------------------- LCD_PAL176 ------------------------------------------- -#define LCD_PAL176_R04_0_Pos 0 /*!< LCD PAL176: R04_0 Position */ -#define LCD_PAL176_R04_0_Msk (0x1fUL << LCD_PAL176_R04_0_Pos) /*!< LCD PAL176: R04_0 Mask */ -#define LCD_PAL176_G04_0_Pos 5 /*!< LCD PAL176: G04_0 Position */ -#define LCD_PAL176_G04_0_Msk (0x1fUL << LCD_PAL176_G04_0_Pos) /*!< LCD PAL176: G04_0 Mask */ -#define LCD_PAL176_B04_0_Pos 10 /*!< LCD PAL176: B04_0 Position */ -#define LCD_PAL176_B04_0_Msk (0x1fUL << LCD_PAL176_B04_0_Pos) /*!< LCD PAL176: B04_0 Mask */ -#define LCD_PAL176_I0_Pos 15 /*!< LCD PAL176: I0 Position */ -#define LCD_PAL176_I0_Msk (0x01UL << LCD_PAL176_I0_Pos) /*!< LCD PAL176: I0 Mask */ -#define LCD_PAL176_R14_0_Pos 16 /*!< LCD PAL176: R14_0 Position */ -#define LCD_PAL176_R14_0_Msk (0x1fUL << LCD_PAL176_R14_0_Pos) /*!< LCD PAL176: R14_0 Mask */ -#define LCD_PAL176_G14_0_Pos 21 /*!< LCD PAL176: G14_0 Position */ -#define LCD_PAL176_G14_0_Msk (0x1fUL << LCD_PAL176_G14_0_Pos) /*!< LCD PAL176: G14_0 Mask */ -#define LCD_PAL176_B14_0_Pos 26 /*!< LCD PAL176: B14_0 Position */ -#define LCD_PAL176_B14_0_Msk (0x1fUL << LCD_PAL176_B14_0_Pos) /*!< LCD PAL176: B14_0 Mask */ -#define LCD_PAL176_I1_Pos 31 /*!< LCD PAL176: I1 Position */ -#define LCD_PAL176_I1_Msk (0x01UL << LCD_PAL176_I1_Pos) /*!< LCD PAL176: I1 Mask */ - -// --------------------------------------- LCD_PAL177 ------------------------------------------- -#define LCD_PAL177_R04_0_Pos 0 /*!< LCD PAL177: R04_0 Position */ -#define LCD_PAL177_R04_0_Msk (0x1fUL << LCD_PAL177_R04_0_Pos) /*!< LCD PAL177: R04_0 Mask */ -#define LCD_PAL177_G04_0_Pos 5 /*!< LCD PAL177: G04_0 Position */ -#define LCD_PAL177_G04_0_Msk (0x1fUL << LCD_PAL177_G04_0_Pos) /*!< LCD PAL177: G04_0 Mask */ -#define LCD_PAL177_B04_0_Pos 10 /*!< LCD PAL177: B04_0 Position */ -#define LCD_PAL177_B04_0_Msk (0x1fUL << LCD_PAL177_B04_0_Pos) /*!< LCD PAL177: B04_0 Mask */ -#define LCD_PAL177_I0_Pos 15 /*!< LCD PAL177: I0 Position */ -#define LCD_PAL177_I0_Msk (0x01UL << LCD_PAL177_I0_Pos) /*!< LCD PAL177: I0 Mask */ -#define LCD_PAL177_R14_0_Pos 16 /*!< LCD PAL177: R14_0 Position */ -#define LCD_PAL177_R14_0_Msk (0x1fUL << LCD_PAL177_R14_0_Pos) /*!< LCD PAL177: R14_0 Mask */ -#define LCD_PAL177_G14_0_Pos 21 /*!< LCD PAL177: G14_0 Position */ -#define LCD_PAL177_G14_0_Msk (0x1fUL << LCD_PAL177_G14_0_Pos) /*!< LCD PAL177: G14_0 Mask */ -#define LCD_PAL177_B14_0_Pos 26 /*!< LCD PAL177: B14_0 Position */ -#define LCD_PAL177_B14_0_Msk (0x1fUL << LCD_PAL177_B14_0_Pos) /*!< LCD PAL177: B14_0 Mask */ -#define LCD_PAL177_I1_Pos 31 /*!< LCD PAL177: I1 Position */ -#define LCD_PAL177_I1_Msk (0x01UL << LCD_PAL177_I1_Pos) /*!< LCD PAL177: I1 Mask */ - -// --------------------------------------- LCD_PAL178 ------------------------------------------- -#define LCD_PAL178_R04_0_Pos 0 /*!< LCD PAL178: R04_0 Position */ -#define LCD_PAL178_R04_0_Msk (0x1fUL << LCD_PAL178_R04_0_Pos) /*!< LCD PAL178: R04_0 Mask */ -#define LCD_PAL178_G04_0_Pos 5 /*!< LCD PAL178: G04_0 Position */ -#define LCD_PAL178_G04_0_Msk (0x1fUL << LCD_PAL178_G04_0_Pos) /*!< LCD PAL178: G04_0 Mask */ -#define LCD_PAL178_B04_0_Pos 10 /*!< LCD PAL178: B04_0 Position */ -#define LCD_PAL178_B04_0_Msk (0x1fUL << LCD_PAL178_B04_0_Pos) /*!< LCD PAL178: B04_0 Mask */ -#define LCD_PAL178_I0_Pos 15 /*!< LCD PAL178: I0 Position */ -#define LCD_PAL178_I0_Msk (0x01UL << LCD_PAL178_I0_Pos) /*!< LCD PAL178: I0 Mask */ -#define LCD_PAL178_R14_0_Pos 16 /*!< LCD PAL178: R14_0 Position */ -#define LCD_PAL178_R14_0_Msk (0x1fUL << LCD_PAL178_R14_0_Pos) /*!< LCD PAL178: R14_0 Mask */ -#define LCD_PAL178_G14_0_Pos 21 /*!< LCD PAL178: G14_0 Position */ -#define LCD_PAL178_G14_0_Msk (0x1fUL << LCD_PAL178_G14_0_Pos) /*!< LCD PAL178: G14_0 Mask */ -#define LCD_PAL178_B14_0_Pos 26 /*!< LCD PAL178: B14_0 Position */ -#define LCD_PAL178_B14_0_Msk (0x1fUL << LCD_PAL178_B14_0_Pos) /*!< LCD PAL178: B14_0 Mask */ -#define LCD_PAL178_I1_Pos 31 /*!< LCD PAL178: I1 Position */ -#define LCD_PAL178_I1_Msk (0x01UL << LCD_PAL178_I1_Pos) /*!< LCD PAL178: I1 Mask */ - -// --------------------------------------- LCD_PAL179 ------------------------------------------- -#define LCD_PAL179_R04_0_Pos 0 /*!< LCD PAL179: R04_0 Position */ -#define LCD_PAL179_R04_0_Msk (0x1fUL << LCD_PAL179_R04_0_Pos) /*!< LCD PAL179: R04_0 Mask */ -#define LCD_PAL179_G04_0_Pos 5 /*!< LCD PAL179: G04_0 Position */ -#define LCD_PAL179_G04_0_Msk (0x1fUL << LCD_PAL179_G04_0_Pos) /*!< LCD PAL179: G04_0 Mask */ -#define LCD_PAL179_B04_0_Pos 10 /*!< LCD PAL179: B04_0 Position */ -#define LCD_PAL179_B04_0_Msk (0x1fUL << LCD_PAL179_B04_0_Pos) /*!< LCD PAL179: B04_0 Mask */ -#define LCD_PAL179_I0_Pos 15 /*!< LCD PAL179: I0 Position */ -#define LCD_PAL179_I0_Msk (0x01UL << LCD_PAL179_I0_Pos) /*!< LCD PAL179: I0 Mask */ -#define LCD_PAL179_R14_0_Pos 16 /*!< LCD PAL179: R14_0 Position */ -#define LCD_PAL179_R14_0_Msk (0x1fUL << LCD_PAL179_R14_0_Pos) /*!< LCD PAL179: R14_0 Mask */ -#define LCD_PAL179_G14_0_Pos 21 /*!< LCD PAL179: G14_0 Position */ -#define LCD_PAL179_G14_0_Msk (0x1fUL << LCD_PAL179_G14_0_Pos) /*!< LCD PAL179: G14_0 Mask */ -#define LCD_PAL179_B14_0_Pos 26 /*!< LCD PAL179: B14_0 Position */ -#define LCD_PAL179_B14_0_Msk (0x1fUL << LCD_PAL179_B14_0_Pos) /*!< LCD PAL179: B14_0 Mask */ -#define LCD_PAL179_I1_Pos 31 /*!< LCD PAL179: I1 Position */ -#define LCD_PAL179_I1_Msk (0x01UL << LCD_PAL179_I1_Pos) /*!< LCD PAL179: I1 Mask */ - -// --------------------------------------- LCD_PAL180 ------------------------------------------- -#define LCD_PAL180_R04_0_Pos 0 /*!< LCD PAL180: R04_0 Position */ -#define LCD_PAL180_R04_0_Msk (0x1fUL << LCD_PAL180_R04_0_Pos) /*!< LCD PAL180: R04_0 Mask */ -#define LCD_PAL180_G04_0_Pos 5 /*!< LCD PAL180: G04_0 Position */ -#define LCD_PAL180_G04_0_Msk (0x1fUL << LCD_PAL180_G04_0_Pos) /*!< LCD PAL180: G04_0 Mask */ -#define LCD_PAL180_B04_0_Pos 10 /*!< LCD PAL180: B04_0 Position */ -#define LCD_PAL180_B04_0_Msk (0x1fUL << LCD_PAL180_B04_0_Pos) /*!< LCD PAL180: B04_0 Mask */ -#define LCD_PAL180_I0_Pos 15 /*!< LCD PAL180: I0 Position */ -#define LCD_PAL180_I0_Msk (0x01UL << LCD_PAL180_I0_Pos) /*!< LCD PAL180: I0 Mask */ -#define LCD_PAL180_R14_0_Pos 16 /*!< LCD PAL180: R14_0 Position */ -#define LCD_PAL180_R14_0_Msk (0x1fUL << LCD_PAL180_R14_0_Pos) /*!< LCD PAL180: R14_0 Mask */ -#define LCD_PAL180_G14_0_Pos 21 /*!< LCD PAL180: G14_0 Position */ -#define LCD_PAL180_G14_0_Msk (0x1fUL << LCD_PAL180_G14_0_Pos) /*!< LCD PAL180: G14_0 Mask */ -#define LCD_PAL180_B14_0_Pos 26 /*!< LCD PAL180: B14_0 Position */ -#define LCD_PAL180_B14_0_Msk (0x1fUL << LCD_PAL180_B14_0_Pos) /*!< LCD PAL180: B14_0 Mask */ -#define LCD_PAL180_I1_Pos 31 /*!< LCD PAL180: I1 Position */ -#define LCD_PAL180_I1_Msk (0x01UL << LCD_PAL180_I1_Pos) /*!< LCD PAL180: I1 Mask */ - -// --------------------------------------- LCD_PAL181 ------------------------------------------- -#define LCD_PAL181_R04_0_Pos 0 /*!< LCD PAL181: R04_0 Position */ -#define LCD_PAL181_R04_0_Msk (0x1fUL << LCD_PAL181_R04_0_Pos) /*!< LCD PAL181: R04_0 Mask */ -#define LCD_PAL181_G04_0_Pos 5 /*!< LCD PAL181: G04_0 Position */ -#define LCD_PAL181_G04_0_Msk (0x1fUL << LCD_PAL181_G04_0_Pos) /*!< LCD PAL181: G04_0 Mask */ -#define LCD_PAL181_B04_0_Pos 10 /*!< LCD PAL181: B04_0 Position */ -#define LCD_PAL181_B04_0_Msk (0x1fUL << LCD_PAL181_B04_0_Pos) /*!< LCD PAL181: B04_0 Mask */ -#define LCD_PAL181_I0_Pos 15 /*!< LCD PAL181: I0 Position */ -#define LCD_PAL181_I0_Msk (0x01UL << LCD_PAL181_I0_Pos) /*!< LCD PAL181: I0 Mask */ -#define LCD_PAL181_R14_0_Pos 16 /*!< LCD PAL181: R14_0 Position */ -#define LCD_PAL181_R14_0_Msk (0x1fUL << LCD_PAL181_R14_0_Pos) /*!< LCD PAL181: R14_0 Mask */ -#define LCD_PAL181_G14_0_Pos 21 /*!< LCD PAL181: G14_0 Position */ -#define LCD_PAL181_G14_0_Msk (0x1fUL << LCD_PAL181_G14_0_Pos) /*!< LCD PAL181: G14_0 Mask */ -#define LCD_PAL181_B14_0_Pos 26 /*!< LCD PAL181: B14_0 Position */ -#define LCD_PAL181_B14_0_Msk (0x1fUL << LCD_PAL181_B14_0_Pos) /*!< LCD PAL181: B14_0 Mask */ -#define LCD_PAL181_I1_Pos 31 /*!< LCD PAL181: I1 Position */ -#define LCD_PAL181_I1_Msk (0x01UL << LCD_PAL181_I1_Pos) /*!< LCD PAL181: I1 Mask */ - -// --------------------------------------- LCD_PAL182 ------------------------------------------- -#define LCD_PAL182_R04_0_Pos 0 /*!< LCD PAL182: R04_0 Position */ -#define LCD_PAL182_R04_0_Msk (0x1fUL << LCD_PAL182_R04_0_Pos) /*!< LCD PAL182: R04_0 Mask */ -#define LCD_PAL182_G04_0_Pos 5 /*!< LCD PAL182: G04_0 Position */ -#define LCD_PAL182_G04_0_Msk (0x1fUL << LCD_PAL182_G04_0_Pos) /*!< LCD PAL182: G04_0 Mask */ -#define LCD_PAL182_B04_0_Pos 10 /*!< LCD PAL182: B04_0 Position */ -#define LCD_PAL182_B04_0_Msk (0x1fUL << LCD_PAL182_B04_0_Pos) /*!< LCD PAL182: B04_0 Mask */ -#define LCD_PAL182_I0_Pos 15 /*!< LCD PAL182: I0 Position */ -#define LCD_PAL182_I0_Msk (0x01UL << LCD_PAL182_I0_Pos) /*!< LCD PAL182: I0 Mask */ -#define LCD_PAL182_R14_0_Pos 16 /*!< LCD PAL182: R14_0 Position */ -#define LCD_PAL182_R14_0_Msk (0x1fUL << LCD_PAL182_R14_0_Pos) /*!< LCD PAL182: R14_0 Mask */ -#define LCD_PAL182_G14_0_Pos 21 /*!< LCD PAL182: G14_0 Position */ -#define LCD_PAL182_G14_0_Msk (0x1fUL << LCD_PAL182_G14_0_Pos) /*!< LCD PAL182: G14_0 Mask */ -#define LCD_PAL182_B14_0_Pos 26 /*!< LCD PAL182: B14_0 Position */ -#define LCD_PAL182_B14_0_Msk (0x1fUL << LCD_PAL182_B14_0_Pos) /*!< LCD PAL182: B14_0 Mask */ -#define LCD_PAL182_I1_Pos 31 /*!< LCD PAL182: I1 Position */ -#define LCD_PAL182_I1_Msk (0x01UL << LCD_PAL182_I1_Pos) /*!< LCD PAL182: I1 Mask */ - -// --------------------------------------- LCD_PAL183 ------------------------------------------- -#define LCD_PAL183_R04_0_Pos 0 /*!< LCD PAL183: R04_0 Position */ -#define LCD_PAL183_R04_0_Msk (0x1fUL << LCD_PAL183_R04_0_Pos) /*!< LCD PAL183: R04_0 Mask */ -#define LCD_PAL183_G04_0_Pos 5 /*!< LCD PAL183: G04_0 Position */ -#define LCD_PAL183_G04_0_Msk (0x1fUL << LCD_PAL183_G04_0_Pos) /*!< LCD PAL183: G04_0 Mask */ -#define LCD_PAL183_B04_0_Pos 10 /*!< LCD PAL183: B04_0 Position */ -#define LCD_PAL183_B04_0_Msk (0x1fUL << LCD_PAL183_B04_0_Pos) /*!< LCD PAL183: B04_0 Mask */ -#define LCD_PAL183_I0_Pos 15 /*!< LCD PAL183: I0 Position */ -#define LCD_PAL183_I0_Msk (0x01UL << LCD_PAL183_I0_Pos) /*!< LCD PAL183: I0 Mask */ -#define LCD_PAL183_R14_0_Pos 16 /*!< LCD PAL183: R14_0 Position */ -#define LCD_PAL183_R14_0_Msk (0x1fUL << LCD_PAL183_R14_0_Pos) /*!< LCD PAL183: R14_0 Mask */ -#define LCD_PAL183_G14_0_Pos 21 /*!< LCD PAL183: G14_0 Position */ -#define LCD_PAL183_G14_0_Msk (0x1fUL << LCD_PAL183_G14_0_Pos) /*!< LCD PAL183: G14_0 Mask */ -#define LCD_PAL183_B14_0_Pos 26 /*!< LCD PAL183: B14_0 Position */ -#define LCD_PAL183_B14_0_Msk (0x1fUL << LCD_PAL183_B14_0_Pos) /*!< LCD PAL183: B14_0 Mask */ -#define LCD_PAL183_I1_Pos 31 /*!< LCD PAL183: I1 Position */ -#define LCD_PAL183_I1_Msk (0x01UL << LCD_PAL183_I1_Pos) /*!< LCD PAL183: I1 Mask */ - -// --------------------------------------- LCD_PAL184 ------------------------------------------- -#define LCD_PAL184_R04_0_Pos 0 /*!< LCD PAL184: R04_0 Position */ -#define LCD_PAL184_R04_0_Msk (0x1fUL << LCD_PAL184_R04_0_Pos) /*!< LCD PAL184: R04_0 Mask */ -#define LCD_PAL184_G04_0_Pos 5 /*!< LCD PAL184: G04_0 Position */ -#define LCD_PAL184_G04_0_Msk (0x1fUL << LCD_PAL184_G04_0_Pos) /*!< LCD PAL184: G04_0 Mask */ -#define LCD_PAL184_B04_0_Pos 10 /*!< LCD PAL184: B04_0 Position */ -#define LCD_PAL184_B04_0_Msk (0x1fUL << LCD_PAL184_B04_0_Pos) /*!< LCD PAL184: B04_0 Mask */ -#define LCD_PAL184_I0_Pos 15 /*!< LCD PAL184: I0 Position */ -#define LCD_PAL184_I0_Msk (0x01UL << LCD_PAL184_I0_Pos) /*!< LCD PAL184: I0 Mask */ -#define LCD_PAL184_R14_0_Pos 16 /*!< LCD PAL184: R14_0 Position */ -#define LCD_PAL184_R14_0_Msk (0x1fUL << LCD_PAL184_R14_0_Pos) /*!< LCD PAL184: R14_0 Mask */ -#define LCD_PAL184_G14_0_Pos 21 /*!< LCD PAL184: G14_0 Position */ -#define LCD_PAL184_G14_0_Msk (0x1fUL << LCD_PAL184_G14_0_Pos) /*!< LCD PAL184: G14_0 Mask */ -#define LCD_PAL184_B14_0_Pos 26 /*!< LCD PAL184: B14_0 Position */ -#define LCD_PAL184_B14_0_Msk (0x1fUL << LCD_PAL184_B14_0_Pos) /*!< LCD PAL184: B14_0 Mask */ -#define LCD_PAL184_I1_Pos 31 /*!< LCD PAL184: I1 Position */ -#define LCD_PAL184_I1_Msk (0x01UL << LCD_PAL184_I1_Pos) /*!< LCD PAL184: I1 Mask */ - -// --------------------------------------- LCD_PAL185 ------------------------------------------- -#define LCD_PAL185_R04_0_Pos 0 /*!< LCD PAL185: R04_0 Position */ -#define LCD_PAL185_R04_0_Msk (0x1fUL << LCD_PAL185_R04_0_Pos) /*!< LCD PAL185: R04_0 Mask */ -#define LCD_PAL185_G04_0_Pos 5 /*!< LCD PAL185: G04_0 Position */ -#define LCD_PAL185_G04_0_Msk (0x1fUL << LCD_PAL185_G04_0_Pos) /*!< LCD PAL185: G04_0 Mask */ -#define LCD_PAL185_B04_0_Pos 10 /*!< LCD PAL185: B04_0 Position */ -#define LCD_PAL185_B04_0_Msk (0x1fUL << LCD_PAL185_B04_0_Pos) /*!< LCD PAL185: B04_0 Mask */ -#define LCD_PAL185_I0_Pos 15 /*!< LCD PAL185: I0 Position */ -#define LCD_PAL185_I0_Msk (0x01UL << LCD_PAL185_I0_Pos) /*!< LCD PAL185: I0 Mask */ -#define LCD_PAL185_R14_0_Pos 16 /*!< LCD PAL185: R14_0 Position */ -#define LCD_PAL185_R14_0_Msk (0x1fUL << LCD_PAL185_R14_0_Pos) /*!< LCD PAL185: R14_0 Mask */ -#define LCD_PAL185_G14_0_Pos 21 /*!< LCD PAL185: G14_0 Position */ -#define LCD_PAL185_G14_0_Msk (0x1fUL << LCD_PAL185_G14_0_Pos) /*!< LCD PAL185: G14_0 Mask */ -#define LCD_PAL185_B14_0_Pos 26 /*!< LCD PAL185: B14_0 Position */ -#define LCD_PAL185_B14_0_Msk (0x1fUL << LCD_PAL185_B14_0_Pos) /*!< LCD PAL185: B14_0 Mask */ -#define LCD_PAL185_I1_Pos 31 /*!< LCD PAL185: I1 Position */ -#define LCD_PAL185_I1_Msk (0x01UL << LCD_PAL185_I1_Pos) /*!< LCD PAL185: I1 Mask */ - -// --------------------------------------- LCD_PAL186 ------------------------------------------- -#define LCD_PAL186_R04_0_Pos 0 /*!< LCD PAL186: R04_0 Position */ -#define LCD_PAL186_R04_0_Msk (0x1fUL << LCD_PAL186_R04_0_Pos) /*!< LCD PAL186: R04_0 Mask */ -#define LCD_PAL186_G04_0_Pos 5 /*!< LCD PAL186: G04_0 Position */ -#define LCD_PAL186_G04_0_Msk (0x1fUL << LCD_PAL186_G04_0_Pos) /*!< LCD PAL186: G04_0 Mask */ -#define LCD_PAL186_B04_0_Pos 10 /*!< LCD PAL186: B04_0 Position */ -#define LCD_PAL186_B04_0_Msk (0x1fUL << LCD_PAL186_B04_0_Pos) /*!< LCD PAL186: B04_0 Mask */ -#define LCD_PAL186_I0_Pos 15 /*!< LCD PAL186: I0 Position */ -#define LCD_PAL186_I0_Msk (0x01UL << LCD_PAL186_I0_Pos) /*!< LCD PAL186: I0 Mask */ -#define LCD_PAL186_R14_0_Pos 16 /*!< LCD PAL186: R14_0 Position */ -#define LCD_PAL186_R14_0_Msk (0x1fUL << LCD_PAL186_R14_0_Pos) /*!< LCD PAL186: R14_0 Mask */ -#define LCD_PAL186_G14_0_Pos 21 /*!< LCD PAL186: G14_0 Position */ -#define LCD_PAL186_G14_0_Msk (0x1fUL << LCD_PAL186_G14_0_Pos) /*!< LCD PAL186: G14_0 Mask */ -#define LCD_PAL186_B14_0_Pos 26 /*!< LCD PAL186: B14_0 Position */ -#define LCD_PAL186_B14_0_Msk (0x1fUL << LCD_PAL186_B14_0_Pos) /*!< LCD PAL186: B14_0 Mask */ -#define LCD_PAL186_I1_Pos 31 /*!< LCD PAL186: I1 Position */ -#define LCD_PAL186_I1_Msk (0x01UL << LCD_PAL186_I1_Pos) /*!< LCD PAL186: I1 Mask */ - -// --------------------------------------- LCD_PAL187 ------------------------------------------- -#define LCD_PAL187_R04_0_Pos 0 /*!< LCD PAL187: R04_0 Position */ -#define LCD_PAL187_R04_0_Msk (0x1fUL << LCD_PAL187_R04_0_Pos) /*!< LCD PAL187: R04_0 Mask */ -#define LCD_PAL187_G04_0_Pos 5 /*!< LCD PAL187: G04_0 Position */ -#define LCD_PAL187_G04_0_Msk (0x1fUL << LCD_PAL187_G04_0_Pos) /*!< LCD PAL187: G04_0 Mask */ -#define LCD_PAL187_B04_0_Pos 10 /*!< LCD PAL187: B04_0 Position */ -#define LCD_PAL187_B04_0_Msk (0x1fUL << LCD_PAL187_B04_0_Pos) /*!< LCD PAL187: B04_0 Mask */ -#define LCD_PAL187_I0_Pos 15 /*!< LCD PAL187: I0 Position */ -#define LCD_PAL187_I0_Msk (0x01UL << LCD_PAL187_I0_Pos) /*!< LCD PAL187: I0 Mask */ -#define LCD_PAL187_R14_0_Pos 16 /*!< LCD PAL187: R14_0 Position */ -#define LCD_PAL187_R14_0_Msk (0x1fUL << LCD_PAL187_R14_0_Pos) /*!< LCD PAL187: R14_0 Mask */ -#define LCD_PAL187_G14_0_Pos 21 /*!< LCD PAL187: G14_0 Position */ -#define LCD_PAL187_G14_0_Msk (0x1fUL << LCD_PAL187_G14_0_Pos) /*!< LCD PAL187: G14_0 Mask */ -#define LCD_PAL187_B14_0_Pos 26 /*!< LCD PAL187: B14_0 Position */ -#define LCD_PAL187_B14_0_Msk (0x1fUL << LCD_PAL187_B14_0_Pos) /*!< LCD PAL187: B14_0 Mask */ -#define LCD_PAL187_I1_Pos 31 /*!< LCD PAL187: I1 Position */ -#define LCD_PAL187_I1_Msk (0x01UL << LCD_PAL187_I1_Pos) /*!< LCD PAL187: I1 Mask */ - -// --------------------------------------- LCD_PAL188 ------------------------------------------- -#define LCD_PAL188_R04_0_Pos 0 /*!< LCD PAL188: R04_0 Position */ -#define LCD_PAL188_R04_0_Msk (0x1fUL << LCD_PAL188_R04_0_Pos) /*!< LCD PAL188: R04_0 Mask */ -#define LCD_PAL188_G04_0_Pos 5 /*!< LCD PAL188: G04_0 Position */ -#define LCD_PAL188_G04_0_Msk (0x1fUL << LCD_PAL188_G04_0_Pos) /*!< LCD PAL188: G04_0 Mask */ -#define LCD_PAL188_B04_0_Pos 10 /*!< LCD PAL188: B04_0 Position */ -#define LCD_PAL188_B04_0_Msk (0x1fUL << LCD_PAL188_B04_0_Pos) /*!< LCD PAL188: B04_0 Mask */ -#define LCD_PAL188_I0_Pos 15 /*!< LCD PAL188: I0 Position */ -#define LCD_PAL188_I0_Msk (0x01UL << LCD_PAL188_I0_Pos) /*!< LCD PAL188: I0 Mask */ -#define LCD_PAL188_R14_0_Pos 16 /*!< LCD PAL188: R14_0 Position */ -#define LCD_PAL188_R14_0_Msk (0x1fUL << LCD_PAL188_R14_0_Pos) /*!< LCD PAL188: R14_0 Mask */ -#define LCD_PAL188_G14_0_Pos 21 /*!< LCD PAL188: G14_0 Position */ -#define LCD_PAL188_G14_0_Msk (0x1fUL << LCD_PAL188_G14_0_Pos) /*!< LCD PAL188: G14_0 Mask */ -#define LCD_PAL188_B14_0_Pos 26 /*!< LCD PAL188: B14_0 Position */ -#define LCD_PAL188_B14_0_Msk (0x1fUL << LCD_PAL188_B14_0_Pos) /*!< LCD PAL188: B14_0 Mask */ -#define LCD_PAL188_I1_Pos 31 /*!< LCD PAL188: I1 Position */ -#define LCD_PAL188_I1_Msk (0x01UL << LCD_PAL188_I1_Pos) /*!< LCD PAL188: I1 Mask */ - -// --------------------------------------- LCD_PAL189 ------------------------------------------- -#define LCD_PAL189_R04_0_Pos 0 /*!< LCD PAL189: R04_0 Position */ -#define LCD_PAL189_R04_0_Msk (0x1fUL << LCD_PAL189_R04_0_Pos) /*!< LCD PAL189: R04_0 Mask */ -#define LCD_PAL189_G04_0_Pos 5 /*!< LCD PAL189: G04_0 Position */ -#define LCD_PAL189_G04_0_Msk (0x1fUL << LCD_PAL189_G04_0_Pos) /*!< LCD PAL189: G04_0 Mask */ -#define LCD_PAL189_B04_0_Pos 10 /*!< LCD PAL189: B04_0 Position */ -#define LCD_PAL189_B04_0_Msk (0x1fUL << LCD_PAL189_B04_0_Pos) /*!< LCD PAL189: B04_0 Mask */ -#define LCD_PAL189_I0_Pos 15 /*!< LCD PAL189: I0 Position */ -#define LCD_PAL189_I0_Msk (0x01UL << LCD_PAL189_I0_Pos) /*!< LCD PAL189: I0 Mask */ -#define LCD_PAL189_R14_0_Pos 16 /*!< LCD PAL189: R14_0 Position */ -#define LCD_PAL189_R14_0_Msk (0x1fUL << LCD_PAL189_R14_0_Pos) /*!< LCD PAL189: R14_0 Mask */ -#define LCD_PAL189_G14_0_Pos 21 /*!< LCD PAL189: G14_0 Position */ -#define LCD_PAL189_G14_0_Msk (0x1fUL << LCD_PAL189_G14_0_Pos) /*!< LCD PAL189: G14_0 Mask */ -#define LCD_PAL189_B14_0_Pos 26 /*!< LCD PAL189: B14_0 Position */ -#define LCD_PAL189_B14_0_Msk (0x1fUL << LCD_PAL189_B14_0_Pos) /*!< LCD PAL189: B14_0 Mask */ -#define LCD_PAL189_I1_Pos 31 /*!< LCD PAL189: I1 Position */ -#define LCD_PAL189_I1_Msk (0x01UL << LCD_PAL189_I1_Pos) /*!< LCD PAL189: I1 Mask */ - -// --------------------------------------- LCD_PAL190 ------------------------------------------- -#define LCD_PAL190_R04_0_Pos 0 /*!< LCD PAL190: R04_0 Position */ -#define LCD_PAL190_R04_0_Msk (0x1fUL << LCD_PAL190_R04_0_Pos) /*!< LCD PAL190: R04_0 Mask */ -#define LCD_PAL190_G04_0_Pos 5 /*!< LCD PAL190: G04_0 Position */ -#define LCD_PAL190_G04_0_Msk (0x1fUL << LCD_PAL190_G04_0_Pos) /*!< LCD PAL190: G04_0 Mask */ -#define LCD_PAL190_B04_0_Pos 10 /*!< LCD PAL190: B04_0 Position */ -#define LCD_PAL190_B04_0_Msk (0x1fUL << LCD_PAL190_B04_0_Pos) /*!< LCD PAL190: B04_0 Mask */ -#define LCD_PAL190_I0_Pos 15 /*!< LCD PAL190: I0 Position */ -#define LCD_PAL190_I0_Msk (0x01UL << LCD_PAL190_I0_Pos) /*!< LCD PAL190: I0 Mask */ -#define LCD_PAL190_R14_0_Pos 16 /*!< LCD PAL190: R14_0 Position */ -#define LCD_PAL190_R14_0_Msk (0x1fUL << LCD_PAL190_R14_0_Pos) /*!< LCD PAL190: R14_0 Mask */ -#define LCD_PAL190_G14_0_Pos 21 /*!< LCD PAL190: G14_0 Position */ -#define LCD_PAL190_G14_0_Msk (0x1fUL << LCD_PAL190_G14_0_Pos) /*!< LCD PAL190: G14_0 Mask */ -#define LCD_PAL190_B14_0_Pos 26 /*!< LCD PAL190: B14_0 Position */ -#define LCD_PAL190_B14_0_Msk (0x1fUL << LCD_PAL190_B14_0_Pos) /*!< LCD PAL190: B14_0 Mask */ -#define LCD_PAL190_I1_Pos 31 /*!< LCD PAL190: I1 Position */ -#define LCD_PAL190_I1_Msk (0x01UL << LCD_PAL190_I1_Pos) /*!< LCD PAL190: I1 Mask */ - -// --------------------------------------- LCD_PAL191 ------------------------------------------- -#define LCD_PAL191_R04_0_Pos 0 /*!< LCD PAL191: R04_0 Position */ -#define LCD_PAL191_R04_0_Msk (0x1fUL << LCD_PAL191_R04_0_Pos) /*!< LCD PAL191: R04_0 Mask */ -#define LCD_PAL191_G04_0_Pos 5 /*!< LCD PAL191: G04_0 Position */ -#define LCD_PAL191_G04_0_Msk (0x1fUL << LCD_PAL191_G04_0_Pos) /*!< LCD PAL191: G04_0 Mask */ -#define LCD_PAL191_B04_0_Pos 10 /*!< LCD PAL191: B04_0 Position */ -#define LCD_PAL191_B04_0_Msk (0x1fUL << LCD_PAL191_B04_0_Pos) /*!< LCD PAL191: B04_0 Mask */ -#define LCD_PAL191_I0_Pos 15 /*!< LCD PAL191: I0 Position */ -#define LCD_PAL191_I0_Msk (0x01UL << LCD_PAL191_I0_Pos) /*!< LCD PAL191: I0 Mask */ -#define LCD_PAL191_R14_0_Pos 16 /*!< LCD PAL191: R14_0 Position */ -#define LCD_PAL191_R14_0_Msk (0x1fUL << LCD_PAL191_R14_0_Pos) /*!< LCD PAL191: R14_0 Mask */ -#define LCD_PAL191_G14_0_Pos 21 /*!< LCD PAL191: G14_0 Position */ -#define LCD_PAL191_G14_0_Msk (0x1fUL << LCD_PAL191_G14_0_Pos) /*!< LCD PAL191: G14_0 Mask */ -#define LCD_PAL191_B14_0_Pos 26 /*!< LCD PAL191: B14_0 Position */ -#define LCD_PAL191_B14_0_Msk (0x1fUL << LCD_PAL191_B14_0_Pos) /*!< LCD PAL191: B14_0 Mask */ -#define LCD_PAL191_I1_Pos 31 /*!< LCD PAL191: I1 Position */ -#define LCD_PAL191_I1_Msk (0x01UL << LCD_PAL191_I1_Pos) /*!< LCD PAL191: I1 Mask */ - -// --------------------------------------- LCD_PAL192 ------------------------------------------- -#define LCD_PAL192_R04_0_Pos 0 /*!< LCD PAL192: R04_0 Position */ -#define LCD_PAL192_R04_0_Msk (0x1fUL << LCD_PAL192_R04_0_Pos) /*!< LCD PAL192: R04_0 Mask */ -#define LCD_PAL192_G04_0_Pos 5 /*!< LCD PAL192: G04_0 Position */ -#define LCD_PAL192_G04_0_Msk (0x1fUL << LCD_PAL192_G04_0_Pos) /*!< LCD PAL192: G04_0 Mask */ -#define LCD_PAL192_B04_0_Pos 10 /*!< LCD PAL192: B04_0 Position */ -#define LCD_PAL192_B04_0_Msk (0x1fUL << LCD_PAL192_B04_0_Pos) /*!< LCD PAL192: B04_0 Mask */ -#define LCD_PAL192_I0_Pos 15 /*!< LCD PAL192: I0 Position */ -#define LCD_PAL192_I0_Msk (0x01UL << LCD_PAL192_I0_Pos) /*!< LCD PAL192: I0 Mask */ -#define LCD_PAL192_R14_0_Pos 16 /*!< LCD PAL192: R14_0 Position */ -#define LCD_PAL192_R14_0_Msk (0x1fUL << LCD_PAL192_R14_0_Pos) /*!< LCD PAL192: R14_0 Mask */ -#define LCD_PAL192_G14_0_Pos 21 /*!< LCD PAL192: G14_0 Position */ -#define LCD_PAL192_G14_0_Msk (0x1fUL << LCD_PAL192_G14_0_Pos) /*!< LCD PAL192: G14_0 Mask */ -#define LCD_PAL192_B14_0_Pos 26 /*!< LCD PAL192: B14_0 Position */ -#define LCD_PAL192_B14_0_Msk (0x1fUL << LCD_PAL192_B14_0_Pos) /*!< LCD PAL192: B14_0 Mask */ -#define LCD_PAL192_I1_Pos 31 /*!< LCD PAL192: I1 Position */ -#define LCD_PAL192_I1_Msk (0x01UL << LCD_PAL192_I1_Pos) /*!< LCD PAL192: I1 Mask */ - -// --------------------------------------- LCD_PAL193 ------------------------------------------- -#define LCD_PAL193_R04_0_Pos 0 /*!< LCD PAL193: R04_0 Position */ -#define LCD_PAL193_R04_0_Msk (0x1fUL << LCD_PAL193_R04_0_Pos) /*!< LCD PAL193: R04_0 Mask */ -#define LCD_PAL193_G04_0_Pos 5 /*!< LCD PAL193: G04_0 Position */ -#define LCD_PAL193_G04_0_Msk (0x1fUL << LCD_PAL193_G04_0_Pos) /*!< LCD PAL193: G04_0 Mask */ -#define LCD_PAL193_B04_0_Pos 10 /*!< LCD PAL193: B04_0 Position */ -#define LCD_PAL193_B04_0_Msk (0x1fUL << LCD_PAL193_B04_0_Pos) /*!< LCD PAL193: B04_0 Mask */ -#define LCD_PAL193_I0_Pos 15 /*!< LCD PAL193: I0 Position */ -#define LCD_PAL193_I0_Msk (0x01UL << LCD_PAL193_I0_Pos) /*!< LCD PAL193: I0 Mask */ -#define LCD_PAL193_R14_0_Pos 16 /*!< LCD PAL193: R14_0 Position */ -#define LCD_PAL193_R14_0_Msk (0x1fUL << LCD_PAL193_R14_0_Pos) /*!< LCD PAL193: R14_0 Mask */ -#define LCD_PAL193_G14_0_Pos 21 /*!< LCD PAL193: G14_0 Position */ -#define LCD_PAL193_G14_0_Msk (0x1fUL << LCD_PAL193_G14_0_Pos) /*!< LCD PAL193: G14_0 Mask */ -#define LCD_PAL193_B14_0_Pos 26 /*!< LCD PAL193: B14_0 Position */ -#define LCD_PAL193_B14_0_Msk (0x1fUL << LCD_PAL193_B14_0_Pos) /*!< LCD PAL193: B14_0 Mask */ -#define LCD_PAL193_I1_Pos 31 /*!< LCD PAL193: I1 Position */ -#define LCD_PAL193_I1_Msk (0x01UL << LCD_PAL193_I1_Pos) /*!< LCD PAL193: I1 Mask */ - -// --------------------------------------- LCD_PAL194 ------------------------------------------- -#define LCD_PAL194_R04_0_Pos 0 /*!< LCD PAL194: R04_0 Position */ -#define LCD_PAL194_R04_0_Msk (0x1fUL << LCD_PAL194_R04_0_Pos) /*!< LCD PAL194: R04_0 Mask */ -#define LCD_PAL194_G04_0_Pos 5 /*!< LCD PAL194: G04_0 Position */ -#define LCD_PAL194_G04_0_Msk (0x1fUL << LCD_PAL194_G04_0_Pos) /*!< LCD PAL194: G04_0 Mask */ -#define LCD_PAL194_B04_0_Pos 10 /*!< LCD PAL194: B04_0 Position */ -#define LCD_PAL194_B04_0_Msk (0x1fUL << LCD_PAL194_B04_0_Pos) /*!< LCD PAL194: B04_0 Mask */ -#define LCD_PAL194_I0_Pos 15 /*!< LCD PAL194: I0 Position */ -#define LCD_PAL194_I0_Msk (0x01UL << LCD_PAL194_I0_Pos) /*!< LCD PAL194: I0 Mask */ -#define LCD_PAL194_R14_0_Pos 16 /*!< LCD PAL194: R14_0 Position */ -#define LCD_PAL194_R14_0_Msk (0x1fUL << LCD_PAL194_R14_0_Pos) /*!< LCD PAL194: R14_0 Mask */ -#define LCD_PAL194_G14_0_Pos 21 /*!< LCD PAL194: G14_0 Position */ -#define LCD_PAL194_G14_0_Msk (0x1fUL << LCD_PAL194_G14_0_Pos) /*!< LCD PAL194: G14_0 Mask */ -#define LCD_PAL194_B14_0_Pos 26 /*!< LCD PAL194: B14_0 Position */ -#define LCD_PAL194_B14_0_Msk (0x1fUL << LCD_PAL194_B14_0_Pos) /*!< LCD PAL194: B14_0 Mask */ -#define LCD_PAL194_I1_Pos 31 /*!< LCD PAL194: I1 Position */ -#define LCD_PAL194_I1_Msk (0x01UL << LCD_PAL194_I1_Pos) /*!< LCD PAL194: I1 Mask */ - -// --------------------------------------- LCD_PAL195 ------------------------------------------- -#define LCD_PAL195_R04_0_Pos 0 /*!< LCD PAL195: R04_0 Position */ -#define LCD_PAL195_R04_0_Msk (0x1fUL << LCD_PAL195_R04_0_Pos) /*!< LCD PAL195: R04_0 Mask */ -#define LCD_PAL195_G04_0_Pos 5 /*!< LCD PAL195: G04_0 Position */ -#define LCD_PAL195_G04_0_Msk (0x1fUL << LCD_PAL195_G04_0_Pos) /*!< LCD PAL195: G04_0 Mask */ -#define LCD_PAL195_B04_0_Pos 10 /*!< LCD PAL195: B04_0 Position */ -#define LCD_PAL195_B04_0_Msk (0x1fUL << LCD_PAL195_B04_0_Pos) /*!< LCD PAL195: B04_0 Mask */ -#define LCD_PAL195_I0_Pos 15 /*!< LCD PAL195: I0 Position */ -#define LCD_PAL195_I0_Msk (0x01UL << LCD_PAL195_I0_Pos) /*!< LCD PAL195: I0 Mask */ -#define LCD_PAL195_R14_0_Pos 16 /*!< LCD PAL195: R14_0 Position */ -#define LCD_PAL195_R14_0_Msk (0x1fUL << LCD_PAL195_R14_0_Pos) /*!< LCD PAL195: R14_0 Mask */ -#define LCD_PAL195_G14_0_Pos 21 /*!< LCD PAL195: G14_0 Position */ -#define LCD_PAL195_G14_0_Msk (0x1fUL << LCD_PAL195_G14_0_Pos) /*!< LCD PAL195: G14_0 Mask */ -#define LCD_PAL195_B14_0_Pos 26 /*!< LCD PAL195: B14_0 Position */ -#define LCD_PAL195_B14_0_Msk (0x1fUL << LCD_PAL195_B14_0_Pos) /*!< LCD PAL195: B14_0 Mask */ -#define LCD_PAL195_I1_Pos 31 /*!< LCD PAL195: I1 Position */ -#define LCD_PAL195_I1_Msk (0x01UL << LCD_PAL195_I1_Pos) /*!< LCD PAL195: I1 Mask */ - -// --------------------------------------- LCD_PAL196 ------------------------------------------- -#define LCD_PAL196_R04_0_Pos 0 /*!< LCD PAL196: R04_0 Position */ -#define LCD_PAL196_R04_0_Msk (0x1fUL << LCD_PAL196_R04_0_Pos) /*!< LCD PAL196: R04_0 Mask */ -#define LCD_PAL196_G04_0_Pos 5 /*!< LCD PAL196: G04_0 Position */ -#define LCD_PAL196_G04_0_Msk (0x1fUL << LCD_PAL196_G04_0_Pos) /*!< LCD PAL196: G04_0 Mask */ -#define LCD_PAL196_B04_0_Pos 10 /*!< LCD PAL196: B04_0 Position */ -#define LCD_PAL196_B04_0_Msk (0x1fUL << LCD_PAL196_B04_0_Pos) /*!< LCD PAL196: B04_0 Mask */ -#define LCD_PAL196_I0_Pos 15 /*!< LCD PAL196: I0 Position */ -#define LCD_PAL196_I0_Msk (0x01UL << LCD_PAL196_I0_Pos) /*!< LCD PAL196: I0 Mask */ -#define LCD_PAL196_R14_0_Pos 16 /*!< LCD PAL196: R14_0 Position */ -#define LCD_PAL196_R14_0_Msk (0x1fUL << LCD_PAL196_R14_0_Pos) /*!< LCD PAL196: R14_0 Mask */ -#define LCD_PAL196_G14_0_Pos 21 /*!< LCD PAL196: G14_0 Position */ -#define LCD_PAL196_G14_0_Msk (0x1fUL << LCD_PAL196_G14_0_Pos) /*!< LCD PAL196: G14_0 Mask */ -#define LCD_PAL196_B14_0_Pos 26 /*!< LCD PAL196: B14_0 Position */ -#define LCD_PAL196_B14_0_Msk (0x1fUL << LCD_PAL196_B14_0_Pos) /*!< LCD PAL196: B14_0 Mask */ -#define LCD_PAL196_I1_Pos 31 /*!< LCD PAL196: I1 Position */ -#define LCD_PAL196_I1_Msk (0x01UL << LCD_PAL196_I1_Pos) /*!< LCD PAL196: I1 Mask */ - -// --------------------------------------- LCD_PAL197 ------------------------------------------- -#define LCD_PAL197_R04_0_Pos 0 /*!< LCD PAL197: R04_0 Position */ -#define LCD_PAL197_R04_0_Msk (0x1fUL << LCD_PAL197_R04_0_Pos) /*!< LCD PAL197: R04_0 Mask */ -#define LCD_PAL197_G04_0_Pos 5 /*!< LCD PAL197: G04_0 Position */ -#define LCD_PAL197_G04_0_Msk (0x1fUL << LCD_PAL197_G04_0_Pos) /*!< LCD PAL197: G04_0 Mask */ -#define LCD_PAL197_B04_0_Pos 10 /*!< LCD PAL197: B04_0 Position */ -#define LCD_PAL197_B04_0_Msk (0x1fUL << LCD_PAL197_B04_0_Pos) /*!< LCD PAL197: B04_0 Mask */ -#define LCD_PAL197_I0_Pos 15 /*!< LCD PAL197: I0 Position */ -#define LCD_PAL197_I0_Msk (0x01UL << LCD_PAL197_I0_Pos) /*!< LCD PAL197: I0 Mask */ -#define LCD_PAL197_R14_0_Pos 16 /*!< LCD PAL197: R14_0 Position */ -#define LCD_PAL197_R14_0_Msk (0x1fUL << LCD_PAL197_R14_0_Pos) /*!< LCD PAL197: R14_0 Mask */ -#define LCD_PAL197_G14_0_Pos 21 /*!< LCD PAL197: G14_0 Position */ -#define LCD_PAL197_G14_0_Msk (0x1fUL << LCD_PAL197_G14_0_Pos) /*!< LCD PAL197: G14_0 Mask */ -#define LCD_PAL197_B14_0_Pos 26 /*!< LCD PAL197: B14_0 Position */ -#define LCD_PAL197_B14_0_Msk (0x1fUL << LCD_PAL197_B14_0_Pos) /*!< LCD PAL197: B14_0 Mask */ -#define LCD_PAL197_I1_Pos 31 /*!< LCD PAL197: I1 Position */ -#define LCD_PAL197_I1_Msk (0x01UL << LCD_PAL197_I1_Pos) /*!< LCD PAL197: I1 Mask */ - -// --------------------------------------- LCD_PAL198 ------------------------------------------- -#define LCD_PAL198_R04_0_Pos 0 /*!< LCD PAL198: R04_0 Position */ -#define LCD_PAL198_R04_0_Msk (0x1fUL << LCD_PAL198_R04_0_Pos) /*!< LCD PAL198: R04_0 Mask */ -#define LCD_PAL198_G04_0_Pos 5 /*!< LCD PAL198: G04_0 Position */ -#define LCD_PAL198_G04_0_Msk (0x1fUL << LCD_PAL198_G04_0_Pos) /*!< LCD PAL198: G04_0 Mask */ -#define LCD_PAL198_B04_0_Pos 10 /*!< LCD PAL198: B04_0 Position */ -#define LCD_PAL198_B04_0_Msk (0x1fUL << LCD_PAL198_B04_0_Pos) /*!< LCD PAL198: B04_0 Mask */ -#define LCD_PAL198_I0_Pos 15 /*!< LCD PAL198: I0 Position */ -#define LCD_PAL198_I0_Msk (0x01UL << LCD_PAL198_I0_Pos) /*!< LCD PAL198: I0 Mask */ -#define LCD_PAL198_R14_0_Pos 16 /*!< LCD PAL198: R14_0 Position */ -#define LCD_PAL198_R14_0_Msk (0x1fUL << LCD_PAL198_R14_0_Pos) /*!< LCD PAL198: R14_0 Mask */ -#define LCD_PAL198_G14_0_Pos 21 /*!< LCD PAL198: G14_0 Position */ -#define LCD_PAL198_G14_0_Msk (0x1fUL << LCD_PAL198_G14_0_Pos) /*!< LCD PAL198: G14_0 Mask */ -#define LCD_PAL198_B14_0_Pos 26 /*!< LCD PAL198: B14_0 Position */ -#define LCD_PAL198_B14_0_Msk (0x1fUL << LCD_PAL198_B14_0_Pos) /*!< LCD PAL198: B14_0 Mask */ -#define LCD_PAL198_I1_Pos 31 /*!< LCD PAL198: I1 Position */ -#define LCD_PAL198_I1_Msk (0x01UL << LCD_PAL198_I1_Pos) /*!< LCD PAL198: I1 Mask */ - -// --------------------------------------- LCD_PAL199 ------------------------------------------- -#define LCD_PAL199_R04_0_Pos 0 /*!< LCD PAL199: R04_0 Position */ -#define LCD_PAL199_R04_0_Msk (0x1fUL << LCD_PAL199_R04_0_Pos) /*!< LCD PAL199: R04_0 Mask */ -#define LCD_PAL199_G04_0_Pos 5 /*!< LCD PAL199: G04_0 Position */ -#define LCD_PAL199_G04_0_Msk (0x1fUL << LCD_PAL199_G04_0_Pos) /*!< LCD PAL199: G04_0 Mask */ -#define LCD_PAL199_B04_0_Pos 10 /*!< LCD PAL199: B04_0 Position */ -#define LCD_PAL199_B04_0_Msk (0x1fUL << LCD_PAL199_B04_0_Pos) /*!< LCD PAL199: B04_0 Mask */ -#define LCD_PAL199_I0_Pos 15 /*!< LCD PAL199: I0 Position */ -#define LCD_PAL199_I0_Msk (0x01UL << LCD_PAL199_I0_Pos) /*!< LCD PAL199: I0 Mask */ -#define LCD_PAL199_R14_0_Pos 16 /*!< LCD PAL199: R14_0 Position */ -#define LCD_PAL199_R14_0_Msk (0x1fUL << LCD_PAL199_R14_0_Pos) /*!< LCD PAL199: R14_0 Mask */ -#define LCD_PAL199_G14_0_Pos 21 /*!< LCD PAL199: G14_0 Position */ -#define LCD_PAL199_G14_0_Msk (0x1fUL << LCD_PAL199_G14_0_Pos) /*!< LCD PAL199: G14_0 Mask */ -#define LCD_PAL199_B14_0_Pos 26 /*!< LCD PAL199: B14_0 Position */ -#define LCD_PAL199_B14_0_Msk (0x1fUL << LCD_PAL199_B14_0_Pos) /*!< LCD PAL199: B14_0 Mask */ -#define LCD_PAL199_I1_Pos 31 /*!< LCD PAL199: I1 Position */ -#define LCD_PAL199_I1_Msk (0x01UL << LCD_PAL199_I1_Pos) /*!< LCD PAL199: I1 Mask */ - -// --------------------------------------- LCD_PAL200 ------------------------------------------- -#define LCD_PAL200_R04_0_Pos 0 /*!< LCD PAL200: R04_0 Position */ -#define LCD_PAL200_R04_0_Msk (0x1fUL << LCD_PAL200_R04_0_Pos) /*!< LCD PAL200: R04_0 Mask */ -#define LCD_PAL200_G04_0_Pos 5 /*!< LCD PAL200: G04_0 Position */ -#define LCD_PAL200_G04_0_Msk (0x1fUL << LCD_PAL200_G04_0_Pos) /*!< LCD PAL200: G04_0 Mask */ -#define LCD_PAL200_B04_0_Pos 10 /*!< LCD PAL200: B04_0 Position */ -#define LCD_PAL200_B04_0_Msk (0x1fUL << LCD_PAL200_B04_0_Pos) /*!< LCD PAL200: B04_0 Mask */ -#define LCD_PAL200_I0_Pos 15 /*!< LCD PAL200: I0 Position */ -#define LCD_PAL200_I0_Msk (0x01UL << LCD_PAL200_I0_Pos) /*!< LCD PAL200: I0 Mask */ -#define LCD_PAL200_R14_0_Pos 16 /*!< LCD PAL200: R14_0 Position */ -#define LCD_PAL200_R14_0_Msk (0x1fUL << LCD_PAL200_R14_0_Pos) /*!< LCD PAL200: R14_0 Mask */ -#define LCD_PAL200_G14_0_Pos 21 /*!< LCD PAL200: G14_0 Position */ -#define LCD_PAL200_G14_0_Msk (0x1fUL << LCD_PAL200_G14_0_Pos) /*!< LCD PAL200: G14_0 Mask */ -#define LCD_PAL200_B14_0_Pos 26 /*!< LCD PAL200: B14_0 Position */ -#define LCD_PAL200_B14_0_Msk (0x1fUL << LCD_PAL200_B14_0_Pos) /*!< LCD PAL200: B14_0 Mask */ -#define LCD_PAL200_I1_Pos 31 /*!< LCD PAL200: I1 Position */ -#define LCD_PAL200_I1_Msk (0x01UL << LCD_PAL200_I1_Pos) /*!< LCD PAL200: I1 Mask */ - -// --------------------------------------- LCD_PAL201 ------------------------------------------- -#define LCD_PAL201_R04_0_Pos 0 /*!< LCD PAL201: R04_0 Position */ -#define LCD_PAL201_R04_0_Msk (0x1fUL << LCD_PAL201_R04_0_Pos) /*!< LCD PAL201: R04_0 Mask */ -#define LCD_PAL201_G04_0_Pos 5 /*!< LCD PAL201: G04_0 Position */ -#define LCD_PAL201_G04_0_Msk (0x1fUL << LCD_PAL201_G04_0_Pos) /*!< LCD PAL201: G04_0 Mask */ -#define LCD_PAL201_B04_0_Pos 10 /*!< LCD PAL201: B04_0 Position */ -#define LCD_PAL201_B04_0_Msk (0x1fUL << LCD_PAL201_B04_0_Pos) /*!< LCD PAL201: B04_0 Mask */ -#define LCD_PAL201_I0_Pos 15 /*!< LCD PAL201: I0 Position */ -#define LCD_PAL201_I0_Msk (0x01UL << LCD_PAL201_I0_Pos) /*!< LCD PAL201: I0 Mask */ -#define LCD_PAL201_R14_0_Pos 16 /*!< LCD PAL201: R14_0 Position */ -#define LCD_PAL201_R14_0_Msk (0x1fUL << LCD_PAL201_R14_0_Pos) /*!< LCD PAL201: R14_0 Mask */ -#define LCD_PAL201_G14_0_Pos 21 /*!< LCD PAL201: G14_0 Position */ -#define LCD_PAL201_G14_0_Msk (0x1fUL << LCD_PAL201_G14_0_Pos) /*!< LCD PAL201: G14_0 Mask */ -#define LCD_PAL201_B14_0_Pos 26 /*!< LCD PAL201: B14_0 Position */ -#define LCD_PAL201_B14_0_Msk (0x1fUL << LCD_PAL201_B14_0_Pos) /*!< LCD PAL201: B14_0 Mask */ -#define LCD_PAL201_I1_Pos 31 /*!< LCD PAL201: I1 Position */ -#define LCD_PAL201_I1_Msk (0x01UL << LCD_PAL201_I1_Pos) /*!< LCD PAL201: I1 Mask */ - -// --------------------------------------- LCD_PAL202 ------------------------------------------- -#define LCD_PAL202_R04_0_Pos 0 /*!< LCD PAL202: R04_0 Position */ -#define LCD_PAL202_R04_0_Msk (0x1fUL << LCD_PAL202_R04_0_Pos) /*!< LCD PAL202: R04_0 Mask */ -#define LCD_PAL202_G04_0_Pos 5 /*!< LCD PAL202: G04_0 Position */ -#define LCD_PAL202_G04_0_Msk (0x1fUL << LCD_PAL202_G04_0_Pos) /*!< LCD PAL202: G04_0 Mask */ -#define LCD_PAL202_B04_0_Pos 10 /*!< LCD PAL202: B04_0 Position */ -#define LCD_PAL202_B04_0_Msk (0x1fUL << LCD_PAL202_B04_0_Pos) /*!< LCD PAL202: B04_0 Mask */ -#define LCD_PAL202_I0_Pos 15 /*!< LCD PAL202: I0 Position */ -#define LCD_PAL202_I0_Msk (0x01UL << LCD_PAL202_I0_Pos) /*!< LCD PAL202: I0 Mask */ -#define LCD_PAL202_R14_0_Pos 16 /*!< LCD PAL202: R14_0 Position */ -#define LCD_PAL202_R14_0_Msk (0x1fUL << LCD_PAL202_R14_0_Pos) /*!< LCD PAL202: R14_0 Mask */ -#define LCD_PAL202_G14_0_Pos 21 /*!< LCD PAL202: G14_0 Position */ -#define LCD_PAL202_G14_0_Msk (0x1fUL << LCD_PAL202_G14_0_Pos) /*!< LCD PAL202: G14_0 Mask */ -#define LCD_PAL202_B14_0_Pos 26 /*!< LCD PAL202: B14_0 Position */ -#define LCD_PAL202_B14_0_Msk (0x1fUL << LCD_PAL202_B14_0_Pos) /*!< LCD PAL202: B14_0 Mask */ -#define LCD_PAL202_I1_Pos 31 /*!< LCD PAL202: I1 Position */ -#define LCD_PAL202_I1_Msk (0x01UL << LCD_PAL202_I1_Pos) /*!< LCD PAL202: I1 Mask */ - -// --------------------------------------- LCD_PAL203 ------------------------------------------- -#define LCD_PAL203_R04_0_Pos 0 /*!< LCD PAL203: R04_0 Position */ -#define LCD_PAL203_R04_0_Msk (0x1fUL << LCD_PAL203_R04_0_Pos) /*!< LCD PAL203: R04_0 Mask */ -#define LCD_PAL203_G04_0_Pos 5 /*!< LCD PAL203: G04_0 Position */ -#define LCD_PAL203_G04_0_Msk (0x1fUL << LCD_PAL203_G04_0_Pos) /*!< LCD PAL203: G04_0 Mask */ -#define LCD_PAL203_B04_0_Pos 10 /*!< LCD PAL203: B04_0 Position */ -#define LCD_PAL203_B04_0_Msk (0x1fUL << LCD_PAL203_B04_0_Pos) /*!< LCD PAL203: B04_0 Mask */ -#define LCD_PAL203_I0_Pos 15 /*!< LCD PAL203: I0 Position */ -#define LCD_PAL203_I0_Msk (0x01UL << LCD_PAL203_I0_Pos) /*!< LCD PAL203: I0 Mask */ -#define LCD_PAL203_R14_0_Pos 16 /*!< LCD PAL203: R14_0 Position */ -#define LCD_PAL203_R14_0_Msk (0x1fUL << LCD_PAL203_R14_0_Pos) /*!< LCD PAL203: R14_0 Mask */ -#define LCD_PAL203_G14_0_Pos 21 /*!< LCD PAL203: G14_0 Position */ -#define LCD_PAL203_G14_0_Msk (0x1fUL << LCD_PAL203_G14_0_Pos) /*!< LCD PAL203: G14_0 Mask */ -#define LCD_PAL203_B14_0_Pos 26 /*!< LCD PAL203: B14_0 Position */ -#define LCD_PAL203_B14_0_Msk (0x1fUL << LCD_PAL203_B14_0_Pos) /*!< LCD PAL203: B14_0 Mask */ -#define LCD_PAL203_I1_Pos 31 /*!< LCD PAL203: I1 Position */ -#define LCD_PAL203_I1_Msk (0x01UL << LCD_PAL203_I1_Pos) /*!< LCD PAL203: I1 Mask */ - -// --------------------------------------- LCD_PAL204 ------------------------------------------- -#define LCD_PAL204_R04_0_Pos 0 /*!< LCD PAL204: R04_0 Position */ -#define LCD_PAL204_R04_0_Msk (0x1fUL << LCD_PAL204_R04_0_Pos) /*!< LCD PAL204: R04_0 Mask */ -#define LCD_PAL204_G04_0_Pos 5 /*!< LCD PAL204: G04_0 Position */ -#define LCD_PAL204_G04_0_Msk (0x1fUL << LCD_PAL204_G04_0_Pos) /*!< LCD PAL204: G04_0 Mask */ -#define LCD_PAL204_B04_0_Pos 10 /*!< LCD PAL204: B04_0 Position */ -#define LCD_PAL204_B04_0_Msk (0x1fUL << LCD_PAL204_B04_0_Pos) /*!< LCD PAL204: B04_0 Mask */ -#define LCD_PAL204_I0_Pos 15 /*!< LCD PAL204: I0 Position */ -#define LCD_PAL204_I0_Msk (0x01UL << LCD_PAL204_I0_Pos) /*!< LCD PAL204: I0 Mask */ -#define LCD_PAL204_R14_0_Pos 16 /*!< LCD PAL204: R14_0 Position */ -#define LCD_PAL204_R14_0_Msk (0x1fUL << LCD_PAL204_R14_0_Pos) /*!< LCD PAL204: R14_0 Mask */ -#define LCD_PAL204_G14_0_Pos 21 /*!< LCD PAL204: G14_0 Position */ -#define LCD_PAL204_G14_0_Msk (0x1fUL << LCD_PAL204_G14_0_Pos) /*!< LCD PAL204: G14_0 Mask */ -#define LCD_PAL204_B14_0_Pos 26 /*!< LCD PAL204: B14_0 Position */ -#define LCD_PAL204_B14_0_Msk (0x1fUL << LCD_PAL204_B14_0_Pos) /*!< LCD PAL204: B14_0 Mask */ -#define LCD_PAL204_I1_Pos 31 /*!< LCD PAL204: I1 Position */ -#define LCD_PAL204_I1_Msk (0x01UL << LCD_PAL204_I1_Pos) /*!< LCD PAL204: I1 Mask */ - -// --------------------------------------- LCD_PAL205 ------------------------------------------- -#define LCD_PAL205_R04_0_Pos 0 /*!< LCD PAL205: R04_0 Position */ -#define LCD_PAL205_R04_0_Msk (0x1fUL << LCD_PAL205_R04_0_Pos) /*!< LCD PAL205: R04_0 Mask */ -#define LCD_PAL205_G04_0_Pos 5 /*!< LCD PAL205: G04_0 Position */ -#define LCD_PAL205_G04_0_Msk (0x1fUL << LCD_PAL205_G04_0_Pos) /*!< LCD PAL205: G04_0 Mask */ -#define LCD_PAL205_B04_0_Pos 10 /*!< LCD PAL205: B04_0 Position */ -#define LCD_PAL205_B04_0_Msk (0x1fUL << LCD_PAL205_B04_0_Pos) /*!< LCD PAL205: B04_0 Mask */ -#define LCD_PAL205_I0_Pos 15 /*!< LCD PAL205: I0 Position */ -#define LCD_PAL205_I0_Msk (0x01UL << LCD_PAL205_I0_Pos) /*!< LCD PAL205: I0 Mask */ -#define LCD_PAL205_R14_0_Pos 16 /*!< LCD PAL205: R14_0 Position */ -#define LCD_PAL205_R14_0_Msk (0x1fUL << LCD_PAL205_R14_0_Pos) /*!< LCD PAL205: R14_0 Mask */ -#define LCD_PAL205_G14_0_Pos 21 /*!< LCD PAL205: G14_0 Position */ -#define LCD_PAL205_G14_0_Msk (0x1fUL << LCD_PAL205_G14_0_Pos) /*!< LCD PAL205: G14_0 Mask */ -#define LCD_PAL205_B14_0_Pos 26 /*!< LCD PAL205: B14_0 Position */ -#define LCD_PAL205_B14_0_Msk (0x1fUL << LCD_PAL205_B14_0_Pos) /*!< LCD PAL205: B14_0 Mask */ -#define LCD_PAL205_I1_Pos 31 /*!< LCD PAL205: I1 Position */ -#define LCD_PAL205_I1_Msk (0x01UL << LCD_PAL205_I1_Pos) /*!< LCD PAL205: I1 Mask */ - -// --------------------------------------- LCD_PAL206 ------------------------------------------- -#define LCD_PAL206_R04_0_Pos 0 /*!< LCD PAL206: R04_0 Position */ -#define LCD_PAL206_R04_0_Msk (0x1fUL << LCD_PAL206_R04_0_Pos) /*!< LCD PAL206: R04_0 Mask */ -#define LCD_PAL206_G04_0_Pos 5 /*!< LCD PAL206: G04_0 Position */ -#define LCD_PAL206_G04_0_Msk (0x1fUL << LCD_PAL206_G04_0_Pos) /*!< LCD PAL206: G04_0 Mask */ -#define LCD_PAL206_B04_0_Pos 10 /*!< LCD PAL206: B04_0 Position */ -#define LCD_PAL206_B04_0_Msk (0x1fUL << LCD_PAL206_B04_0_Pos) /*!< LCD PAL206: B04_0 Mask */ -#define LCD_PAL206_I0_Pos 15 /*!< LCD PAL206: I0 Position */ -#define LCD_PAL206_I0_Msk (0x01UL << LCD_PAL206_I0_Pos) /*!< LCD PAL206: I0 Mask */ -#define LCD_PAL206_R14_0_Pos 16 /*!< LCD PAL206: R14_0 Position */ -#define LCD_PAL206_R14_0_Msk (0x1fUL << LCD_PAL206_R14_0_Pos) /*!< LCD PAL206: R14_0 Mask */ -#define LCD_PAL206_G14_0_Pos 21 /*!< LCD PAL206: G14_0 Position */ -#define LCD_PAL206_G14_0_Msk (0x1fUL << LCD_PAL206_G14_0_Pos) /*!< LCD PAL206: G14_0 Mask */ -#define LCD_PAL206_B14_0_Pos 26 /*!< LCD PAL206: B14_0 Position */ -#define LCD_PAL206_B14_0_Msk (0x1fUL << LCD_PAL206_B14_0_Pos) /*!< LCD PAL206: B14_0 Mask */ -#define LCD_PAL206_I1_Pos 31 /*!< LCD PAL206: I1 Position */ -#define LCD_PAL206_I1_Msk (0x01UL << LCD_PAL206_I1_Pos) /*!< LCD PAL206: I1 Mask */ - -// --------------------------------------- LCD_PAL207 ------------------------------------------- -#define LCD_PAL207_R04_0_Pos 0 /*!< LCD PAL207: R04_0 Position */ -#define LCD_PAL207_R04_0_Msk (0x1fUL << LCD_PAL207_R04_0_Pos) /*!< LCD PAL207: R04_0 Mask */ -#define LCD_PAL207_G04_0_Pos 5 /*!< LCD PAL207: G04_0 Position */ -#define LCD_PAL207_G04_0_Msk (0x1fUL << LCD_PAL207_G04_0_Pos) /*!< LCD PAL207: G04_0 Mask */ -#define LCD_PAL207_B04_0_Pos 10 /*!< LCD PAL207: B04_0 Position */ -#define LCD_PAL207_B04_0_Msk (0x1fUL << LCD_PAL207_B04_0_Pos) /*!< LCD PAL207: B04_0 Mask */ -#define LCD_PAL207_I0_Pos 15 /*!< LCD PAL207: I0 Position */ -#define LCD_PAL207_I0_Msk (0x01UL << LCD_PAL207_I0_Pos) /*!< LCD PAL207: I0 Mask */ -#define LCD_PAL207_R14_0_Pos 16 /*!< LCD PAL207: R14_0 Position */ -#define LCD_PAL207_R14_0_Msk (0x1fUL << LCD_PAL207_R14_0_Pos) /*!< LCD PAL207: R14_0 Mask */ -#define LCD_PAL207_G14_0_Pos 21 /*!< LCD PAL207: G14_0 Position */ -#define LCD_PAL207_G14_0_Msk (0x1fUL << LCD_PAL207_G14_0_Pos) /*!< LCD PAL207: G14_0 Mask */ -#define LCD_PAL207_B14_0_Pos 26 /*!< LCD PAL207: B14_0 Position */ -#define LCD_PAL207_B14_0_Msk (0x1fUL << LCD_PAL207_B14_0_Pos) /*!< LCD PAL207: B14_0 Mask */ -#define LCD_PAL207_I1_Pos 31 /*!< LCD PAL207: I1 Position */ -#define LCD_PAL207_I1_Msk (0x01UL << LCD_PAL207_I1_Pos) /*!< LCD PAL207: I1 Mask */ - -// --------------------------------------- LCD_PAL208 ------------------------------------------- -#define LCD_PAL208_R04_0_Pos 0 /*!< LCD PAL208: R04_0 Position */ -#define LCD_PAL208_R04_0_Msk (0x1fUL << LCD_PAL208_R04_0_Pos) /*!< LCD PAL208: R04_0 Mask */ -#define LCD_PAL208_G04_0_Pos 5 /*!< LCD PAL208: G04_0 Position */ -#define LCD_PAL208_G04_0_Msk (0x1fUL << LCD_PAL208_G04_0_Pos) /*!< LCD PAL208: G04_0 Mask */ -#define LCD_PAL208_B04_0_Pos 10 /*!< LCD PAL208: B04_0 Position */ -#define LCD_PAL208_B04_0_Msk (0x1fUL << LCD_PAL208_B04_0_Pos) /*!< LCD PAL208: B04_0 Mask */ -#define LCD_PAL208_I0_Pos 15 /*!< LCD PAL208: I0 Position */ -#define LCD_PAL208_I0_Msk (0x01UL << LCD_PAL208_I0_Pos) /*!< LCD PAL208: I0 Mask */ -#define LCD_PAL208_R14_0_Pos 16 /*!< LCD PAL208: R14_0 Position */ -#define LCD_PAL208_R14_0_Msk (0x1fUL << LCD_PAL208_R14_0_Pos) /*!< LCD PAL208: R14_0 Mask */ -#define LCD_PAL208_G14_0_Pos 21 /*!< LCD PAL208: G14_0 Position */ -#define LCD_PAL208_G14_0_Msk (0x1fUL << LCD_PAL208_G14_0_Pos) /*!< LCD PAL208: G14_0 Mask */ -#define LCD_PAL208_B14_0_Pos 26 /*!< LCD PAL208: B14_0 Position */ -#define LCD_PAL208_B14_0_Msk (0x1fUL << LCD_PAL208_B14_0_Pos) /*!< LCD PAL208: B14_0 Mask */ -#define LCD_PAL208_I1_Pos 31 /*!< LCD PAL208: I1 Position */ -#define LCD_PAL208_I1_Msk (0x01UL << LCD_PAL208_I1_Pos) /*!< LCD PAL208: I1 Mask */ - -// --------------------------------------- LCD_PAL209 ------------------------------------------- -#define LCD_PAL209_R04_0_Pos 0 /*!< LCD PAL209: R04_0 Position */ -#define LCD_PAL209_R04_0_Msk (0x1fUL << LCD_PAL209_R04_0_Pos) /*!< LCD PAL209: R04_0 Mask */ -#define LCD_PAL209_G04_0_Pos 5 /*!< LCD PAL209: G04_0 Position */ -#define LCD_PAL209_G04_0_Msk (0x1fUL << LCD_PAL209_G04_0_Pos) /*!< LCD PAL209: G04_0 Mask */ -#define LCD_PAL209_B04_0_Pos 10 /*!< LCD PAL209: B04_0 Position */ -#define LCD_PAL209_B04_0_Msk (0x1fUL << LCD_PAL209_B04_0_Pos) /*!< LCD PAL209: B04_0 Mask */ -#define LCD_PAL209_I0_Pos 15 /*!< LCD PAL209: I0 Position */ -#define LCD_PAL209_I0_Msk (0x01UL << LCD_PAL209_I0_Pos) /*!< LCD PAL209: I0 Mask */ -#define LCD_PAL209_R14_0_Pos 16 /*!< LCD PAL209: R14_0 Position */ -#define LCD_PAL209_R14_0_Msk (0x1fUL << LCD_PAL209_R14_0_Pos) /*!< LCD PAL209: R14_0 Mask */ -#define LCD_PAL209_G14_0_Pos 21 /*!< LCD PAL209: G14_0 Position */ -#define LCD_PAL209_G14_0_Msk (0x1fUL << LCD_PAL209_G14_0_Pos) /*!< LCD PAL209: G14_0 Mask */ -#define LCD_PAL209_B14_0_Pos 26 /*!< LCD PAL209: B14_0 Position */ -#define LCD_PAL209_B14_0_Msk (0x1fUL << LCD_PAL209_B14_0_Pos) /*!< LCD PAL209: B14_0 Mask */ -#define LCD_PAL209_I1_Pos 31 /*!< LCD PAL209: I1 Position */ -#define LCD_PAL209_I1_Msk (0x01UL << LCD_PAL209_I1_Pos) /*!< LCD PAL209: I1 Mask */ - -// --------------------------------------- LCD_PAL210 ------------------------------------------- -#define LCD_PAL210_R04_0_Pos 0 /*!< LCD PAL210: R04_0 Position */ -#define LCD_PAL210_R04_0_Msk (0x1fUL << LCD_PAL210_R04_0_Pos) /*!< LCD PAL210: R04_0 Mask */ -#define LCD_PAL210_G04_0_Pos 5 /*!< LCD PAL210: G04_0 Position */ -#define LCD_PAL210_G04_0_Msk (0x1fUL << LCD_PAL210_G04_0_Pos) /*!< LCD PAL210: G04_0 Mask */ -#define LCD_PAL210_B04_0_Pos 10 /*!< LCD PAL210: B04_0 Position */ -#define LCD_PAL210_B04_0_Msk (0x1fUL << LCD_PAL210_B04_0_Pos) /*!< LCD PAL210: B04_0 Mask */ -#define LCD_PAL210_I0_Pos 15 /*!< LCD PAL210: I0 Position */ -#define LCD_PAL210_I0_Msk (0x01UL << LCD_PAL210_I0_Pos) /*!< LCD PAL210: I0 Mask */ -#define LCD_PAL210_R14_0_Pos 16 /*!< LCD PAL210: R14_0 Position */ -#define LCD_PAL210_R14_0_Msk (0x1fUL << LCD_PAL210_R14_0_Pos) /*!< LCD PAL210: R14_0 Mask */ -#define LCD_PAL210_G14_0_Pos 21 /*!< LCD PAL210: G14_0 Position */ -#define LCD_PAL210_G14_0_Msk (0x1fUL << LCD_PAL210_G14_0_Pos) /*!< LCD PAL210: G14_0 Mask */ -#define LCD_PAL210_B14_0_Pos 26 /*!< LCD PAL210: B14_0 Position */ -#define LCD_PAL210_B14_0_Msk (0x1fUL << LCD_PAL210_B14_0_Pos) /*!< LCD PAL210: B14_0 Mask */ -#define LCD_PAL210_I1_Pos 31 /*!< LCD PAL210: I1 Position */ -#define LCD_PAL210_I1_Msk (0x01UL << LCD_PAL210_I1_Pos) /*!< LCD PAL210: I1 Mask */ - -// --------------------------------------- LCD_PAL211 ------------------------------------------- -#define LCD_PAL211_R04_0_Pos 0 /*!< LCD PAL211: R04_0 Position */ -#define LCD_PAL211_R04_0_Msk (0x1fUL << LCD_PAL211_R04_0_Pos) /*!< LCD PAL211: R04_0 Mask */ -#define LCD_PAL211_G04_0_Pos 5 /*!< LCD PAL211: G04_0 Position */ -#define LCD_PAL211_G04_0_Msk (0x1fUL << LCD_PAL211_G04_0_Pos) /*!< LCD PAL211: G04_0 Mask */ -#define LCD_PAL211_B04_0_Pos 10 /*!< LCD PAL211: B04_0 Position */ -#define LCD_PAL211_B04_0_Msk (0x1fUL << LCD_PAL211_B04_0_Pos) /*!< LCD PAL211: B04_0 Mask */ -#define LCD_PAL211_I0_Pos 15 /*!< LCD PAL211: I0 Position */ -#define LCD_PAL211_I0_Msk (0x01UL << LCD_PAL211_I0_Pos) /*!< LCD PAL211: I0 Mask */ -#define LCD_PAL211_R14_0_Pos 16 /*!< LCD PAL211: R14_0 Position */ -#define LCD_PAL211_R14_0_Msk (0x1fUL << LCD_PAL211_R14_0_Pos) /*!< LCD PAL211: R14_0 Mask */ -#define LCD_PAL211_G14_0_Pos 21 /*!< LCD PAL211: G14_0 Position */ -#define LCD_PAL211_G14_0_Msk (0x1fUL << LCD_PAL211_G14_0_Pos) /*!< LCD PAL211: G14_0 Mask */ -#define LCD_PAL211_B14_0_Pos 26 /*!< LCD PAL211: B14_0 Position */ -#define LCD_PAL211_B14_0_Msk (0x1fUL << LCD_PAL211_B14_0_Pos) /*!< LCD PAL211: B14_0 Mask */ -#define LCD_PAL211_I1_Pos 31 /*!< LCD PAL211: I1 Position */ -#define LCD_PAL211_I1_Msk (0x01UL << LCD_PAL211_I1_Pos) /*!< LCD PAL211: I1 Mask */ - -// --------------------------------------- LCD_PAL212 ------------------------------------------- -#define LCD_PAL212_R04_0_Pos 0 /*!< LCD PAL212: R04_0 Position */ -#define LCD_PAL212_R04_0_Msk (0x1fUL << LCD_PAL212_R04_0_Pos) /*!< LCD PAL212: R04_0 Mask */ -#define LCD_PAL212_G04_0_Pos 5 /*!< LCD PAL212: G04_0 Position */ -#define LCD_PAL212_G04_0_Msk (0x1fUL << LCD_PAL212_G04_0_Pos) /*!< LCD PAL212: G04_0 Mask */ -#define LCD_PAL212_B04_0_Pos 10 /*!< LCD PAL212: B04_0 Position */ -#define LCD_PAL212_B04_0_Msk (0x1fUL << LCD_PAL212_B04_0_Pos) /*!< LCD PAL212: B04_0 Mask */ -#define LCD_PAL212_I0_Pos 15 /*!< LCD PAL212: I0 Position */ -#define LCD_PAL212_I0_Msk (0x01UL << LCD_PAL212_I0_Pos) /*!< LCD PAL212: I0 Mask */ -#define LCD_PAL212_R14_0_Pos 16 /*!< LCD PAL212: R14_0 Position */ -#define LCD_PAL212_R14_0_Msk (0x1fUL << LCD_PAL212_R14_0_Pos) /*!< LCD PAL212: R14_0 Mask */ -#define LCD_PAL212_G14_0_Pos 21 /*!< LCD PAL212: G14_0 Position */ -#define LCD_PAL212_G14_0_Msk (0x1fUL << LCD_PAL212_G14_0_Pos) /*!< LCD PAL212: G14_0 Mask */ -#define LCD_PAL212_B14_0_Pos 26 /*!< LCD PAL212: B14_0 Position */ -#define LCD_PAL212_B14_0_Msk (0x1fUL << LCD_PAL212_B14_0_Pos) /*!< LCD PAL212: B14_0 Mask */ -#define LCD_PAL212_I1_Pos 31 /*!< LCD PAL212: I1 Position */ -#define LCD_PAL212_I1_Msk (0x01UL << LCD_PAL212_I1_Pos) /*!< LCD PAL212: I1 Mask */ - -// --------------------------------------- LCD_PAL213 ------------------------------------------- -#define LCD_PAL213_R04_0_Pos 0 /*!< LCD PAL213: R04_0 Position */ -#define LCD_PAL213_R04_0_Msk (0x1fUL << LCD_PAL213_R04_0_Pos) /*!< LCD PAL213: R04_0 Mask */ -#define LCD_PAL213_G04_0_Pos 5 /*!< LCD PAL213: G04_0 Position */ -#define LCD_PAL213_G04_0_Msk (0x1fUL << LCD_PAL213_G04_0_Pos) /*!< LCD PAL213: G04_0 Mask */ -#define LCD_PAL213_B04_0_Pos 10 /*!< LCD PAL213: B04_0 Position */ -#define LCD_PAL213_B04_0_Msk (0x1fUL << LCD_PAL213_B04_0_Pos) /*!< LCD PAL213: B04_0 Mask */ -#define LCD_PAL213_I0_Pos 15 /*!< LCD PAL213: I0 Position */ -#define LCD_PAL213_I0_Msk (0x01UL << LCD_PAL213_I0_Pos) /*!< LCD PAL213: I0 Mask */ -#define LCD_PAL213_R14_0_Pos 16 /*!< LCD PAL213: R14_0 Position */ -#define LCD_PAL213_R14_0_Msk (0x1fUL << LCD_PAL213_R14_0_Pos) /*!< LCD PAL213: R14_0 Mask */ -#define LCD_PAL213_G14_0_Pos 21 /*!< LCD PAL213: G14_0 Position */ -#define LCD_PAL213_G14_0_Msk (0x1fUL << LCD_PAL213_G14_0_Pos) /*!< LCD PAL213: G14_0 Mask */ -#define LCD_PAL213_B14_0_Pos 26 /*!< LCD PAL213: B14_0 Position */ -#define LCD_PAL213_B14_0_Msk (0x1fUL << LCD_PAL213_B14_0_Pos) /*!< LCD PAL213: B14_0 Mask */ -#define LCD_PAL213_I1_Pos 31 /*!< LCD PAL213: I1 Position */ -#define LCD_PAL213_I1_Msk (0x01UL << LCD_PAL213_I1_Pos) /*!< LCD PAL213: I1 Mask */ - -// --------------------------------------- LCD_PAL214 ------------------------------------------- -#define LCD_PAL214_R04_0_Pos 0 /*!< LCD PAL214: R04_0 Position */ -#define LCD_PAL214_R04_0_Msk (0x1fUL << LCD_PAL214_R04_0_Pos) /*!< LCD PAL214: R04_0 Mask */ -#define LCD_PAL214_G04_0_Pos 5 /*!< LCD PAL214: G04_0 Position */ -#define LCD_PAL214_G04_0_Msk (0x1fUL << LCD_PAL214_G04_0_Pos) /*!< LCD PAL214: G04_0 Mask */ -#define LCD_PAL214_B04_0_Pos 10 /*!< LCD PAL214: B04_0 Position */ -#define LCD_PAL214_B04_0_Msk (0x1fUL << LCD_PAL214_B04_0_Pos) /*!< LCD PAL214: B04_0 Mask */ -#define LCD_PAL214_I0_Pos 15 /*!< LCD PAL214: I0 Position */ -#define LCD_PAL214_I0_Msk (0x01UL << LCD_PAL214_I0_Pos) /*!< LCD PAL214: I0 Mask */ -#define LCD_PAL214_R14_0_Pos 16 /*!< LCD PAL214: R14_0 Position */ -#define LCD_PAL214_R14_0_Msk (0x1fUL << LCD_PAL214_R14_0_Pos) /*!< LCD PAL214: R14_0 Mask */ -#define LCD_PAL214_G14_0_Pos 21 /*!< LCD PAL214: G14_0 Position */ -#define LCD_PAL214_G14_0_Msk (0x1fUL << LCD_PAL214_G14_0_Pos) /*!< LCD PAL214: G14_0 Mask */ -#define LCD_PAL214_B14_0_Pos 26 /*!< LCD PAL214: B14_0 Position */ -#define LCD_PAL214_B14_0_Msk (0x1fUL << LCD_PAL214_B14_0_Pos) /*!< LCD PAL214: B14_0 Mask */ -#define LCD_PAL214_I1_Pos 31 /*!< LCD PAL214: I1 Position */ -#define LCD_PAL214_I1_Msk (0x01UL << LCD_PAL214_I1_Pos) /*!< LCD PAL214: I1 Mask */ - -// --------------------------------------- LCD_PAL215 ------------------------------------------- -#define LCD_PAL215_R04_0_Pos 0 /*!< LCD PAL215: R04_0 Position */ -#define LCD_PAL215_R04_0_Msk (0x1fUL << LCD_PAL215_R04_0_Pos) /*!< LCD PAL215: R04_0 Mask */ -#define LCD_PAL215_G04_0_Pos 5 /*!< LCD PAL215: G04_0 Position */ -#define LCD_PAL215_G04_0_Msk (0x1fUL << LCD_PAL215_G04_0_Pos) /*!< LCD PAL215: G04_0 Mask */ -#define LCD_PAL215_B04_0_Pos 10 /*!< LCD PAL215: B04_0 Position */ -#define LCD_PAL215_B04_0_Msk (0x1fUL << LCD_PAL215_B04_0_Pos) /*!< LCD PAL215: B04_0 Mask */ -#define LCD_PAL215_I0_Pos 15 /*!< LCD PAL215: I0 Position */ -#define LCD_PAL215_I0_Msk (0x01UL << LCD_PAL215_I0_Pos) /*!< LCD PAL215: I0 Mask */ -#define LCD_PAL215_R14_0_Pos 16 /*!< LCD PAL215: R14_0 Position */ -#define LCD_PAL215_R14_0_Msk (0x1fUL << LCD_PAL215_R14_0_Pos) /*!< LCD PAL215: R14_0 Mask */ -#define LCD_PAL215_G14_0_Pos 21 /*!< LCD PAL215: G14_0 Position */ -#define LCD_PAL215_G14_0_Msk (0x1fUL << LCD_PAL215_G14_0_Pos) /*!< LCD PAL215: G14_0 Mask */ -#define LCD_PAL215_B14_0_Pos 26 /*!< LCD PAL215: B14_0 Position */ -#define LCD_PAL215_B14_0_Msk (0x1fUL << LCD_PAL215_B14_0_Pos) /*!< LCD PAL215: B14_0 Mask */ -#define LCD_PAL215_I1_Pos 31 /*!< LCD PAL215: I1 Position */ -#define LCD_PAL215_I1_Msk (0x01UL << LCD_PAL215_I1_Pos) /*!< LCD PAL215: I1 Mask */ - -// --------------------------------------- LCD_PAL216 ------------------------------------------- -#define LCD_PAL216_R04_0_Pos 0 /*!< LCD PAL216: R04_0 Position */ -#define LCD_PAL216_R04_0_Msk (0x1fUL << LCD_PAL216_R04_0_Pos) /*!< LCD PAL216: R04_0 Mask */ -#define LCD_PAL216_G04_0_Pos 5 /*!< LCD PAL216: G04_0 Position */ -#define LCD_PAL216_G04_0_Msk (0x1fUL << LCD_PAL216_G04_0_Pos) /*!< LCD PAL216: G04_0 Mask */ -#define LCD_PAL216_B04_0_Pos 10 /*!< LCD PAL216: B04_0 Position */ -#define LCD_PAL216_B04_0_Msk (0x1fUL << LCD_PAL216_B04_0_Pos) /*!< LCD PAL216: B04_0 Mask */ -#define LCD_PAL216_I0_Pos 15 /*!< LCD PAL216: I0 Position */ -#define LCD_PAL216_I0_Msk (0x01UL << LCD_PAL216_I0_Pos) /*!< LCD PAL216: I0 Mask */ -#define LCD_PAL216_R14_0_Pos 16 /*!< LCD PAL216: R14_0 Position */ -#define LCD_PAL216_R14_0_Msk (0x1fUL << LCD_PAL216_R14_0_Pos) /*!< LCD PAL216: R14_0 Mask */ -#define LCD_PAL216_G14_0_Pos 21 /*!< LCD PAL216: G14_0 Position */ -#define LCD_PAL216_G14_0_Msk (0x1fUL << LCD_PAL216_G14_0_Pos) /*!< LCD PAL216: G14_0 Mask */ -#define LCD_PAL216_B14_0_Pos 26 /*!< LCD PAL216: B14_0 Position */ -#define LCD_PAL216_B14_0_Msk (0x1fUL << LCD_PAL216_B14_0_Pos) /*!< LCD PAL216: B14_0 Mask */ -#define LCD_PAL216_I1_Pos 31 /*!< LCD PAL216: I1 Position */ -#define LCD_PAL216_I1_Msk (0x01UL << LCD_PAL216_I1_Pos) /*!< LCD PAL216: I1 Mask */ - -// --------------------------------------- LCD_PAL217 ------------------------------------------- -#define LCD_PAL217_R04_0_Pos 0 /*!< LCD PAL217: R04_0 Position */ -#define LCD_PAL217_R04_0_Msk (0x1fUL << LCD_PAL217_R04_0_Pos) /*!< LCD PAL217: R04_0 Mask */ -#define LCD_PAL217_G04_0_Pos 5 /*!< LCD PAL217: G04_0 Position */ -#define LCD_PAL217_G04_0_Msk (0x1fUL << LCD_PAL217_G04_0_Pos) /*!< LCD PAL217: G04_0 Mask */ -#define LCD_PAL217_B04_0_Pos 10 /*!< LCD PAL217: B04_0 Position */ -#define LCD_PAL217_B04_0_Msk (0x1fUL << LCD_PAL217_B04_0_Pos) /*!< LCD PAL217: B04_0 Mask */ -#define LCD_PAL217_I0_Pos 15 /*!< LCD PAL217: I0 Position */ -#define LCD_PAL217_I0_Msk (0x01UL << LCD_PAL217_I0_Pos) /*!< LCD PAL217: I0 Mask */ -#define LCD_PAL217_R14_0_Pos 16 /*!< LCD PAL217: R14_0 Position */ -#define LCD_PAL217_R14_0_Msk (0x1fUL << LCD_PAL217_R14_0_Pos) /*!< LCD PAL217: R14_0 Mask */ -#define LCD_PAL217_G14_0_Pos 21 /*!< LCD PAL217: G14_0 Position */ -#define LCD_PAL217_G14_0_Msk (0x1fUL << LCD_PAL217_G14_0_Pos) /*!< LCD PAL217: G14_0 Mask */ -#define LCD_PAL217_B14_0_Pos 26 /*!< LCD PAL217: B14_0 Position */ -#define LCD_PAL217_B14_0_Msk (0x1fUL << LCD_PAL217_B14_0_Pos) /*!< LCD PAL217: B14_0 Mask */ -#define LCD_PAL217_I1_Pos 31 /*!< LCD PAL217: I1 Position */ -#define LCD_PAL217_I1_Msk (0x01UL << LCD_PAL217_I1_Pos) /*!< LCD PAL217: I1 Mask */ - -// --------------------------------------- LCD_PAL218 ------------------------------------------- -#define LCD_PAL218_R04_0_Pos 0 /*!< LCD PAL218: R04_0 Position */ -#define LCD_PAL218_R04_0_Msk (0x1fUL << LCD_PAL218_R04_0_Pos) /*!< LCD PAL218: R04_0 Mask */ -#define LCD_PAL218_G04_0_Pos 5 /*!< LCD PAL218: G04_0 Position */ -#define LCD_PAL218_G04_0_Msk (0x1fUL << LCD_PAL218_G04_0_Pos) /*!< LCD PAL218: G04_0 Mask */ -#define LCD_PAL218_B04_0_Pos 10 /*!< LCD PAL218: B04_0 Position */ -#define LCD_PAL218_B04_0_Msk (0x1fUL << LCD_PAL218_B04_0_Pos) /*!< LCD PAL218: B04_0 Mask */ -#define LCD_PAL218_I0_Pos 15 /*!< LCD PAL218: I0 Position */ -#define LCD_PAL218_I0_Msk (0x01UL << LCD_PAL218_I0_Pos) /*!< LCD PAL218: I0 Mask */ -#define LCD_PAL218_R14_0_Pos 16 /*!< LCD PAL218: R14_0 Position */ -#define LCD_PAL218_R14_0_Msk (0x1fUL << LCD_PAL218_R14_0_Pos) /*!< LCD PAL218: R14_0 Mask */ -#define LCD_PAL218_G14_0_Pos 21 /*!< LCD PAL218: G14_0 Position */ -#define LCD_PAL218_G14_0_Msk (0x1fUL << LCD_PAL218_G14_0_Pos) /*!< LCD PAL218: G14_0 Mask */ -#define LCD_PAL218_B14_0_Pos 26 /*!< LCD PAL218: B14_0 Position */ -#define LCD_PAL218_B14_0_Msk (0x1fUL << LCD_PAL218_B14_0_Pos) /*!< LCD PAL218: B14_0 Mask */ -#define LCD_PAL218_I1_Pos 31 /*!< LCD PAL218: I1 Position */ -#define LCD_PAL218_I1_Msk (0x01UL << LCD_PAL218_I1_Pos) /*!< LCD PAL218: I1 Mask */ - -// --------------------------------------- LCD_PAL219 ------------------------------------------- -#define LCD_PAL219_R04_0_Pos 0 /*!< LCD PAL219: R04_0 Position */ -#define LCD_PAL219_R04_0_Msk (0x1fUL << LCD_PAL219_R04_0_Pos) /*!< LCD PAL219: R04_0 Mask */ -#define LCD_PAL219_G04_0_Pos 5 /*!< LCD PAL219: G04_0 Position */ -#define LCD_PAL219_G04_0_Msk (0x1fUL << LCD_PAL219_G04_0_Pos) /*!< LCD PAL219: G04_0 Mask */ -#define LCD_PAL219_B04_0_Pos 10 /*!< LCD PAL219: B04_0 Position */ -#define LCD_PAL219_B04_0_Msk (0x1fUL << LCD_PAL219_B04_0_Pos) /*!< LCD PAL219: B04_0 Mask */ -#define LCD_PAL219_I0_Pos 15 /*!< LCD PAL219: I0 Position */ -#define LCD_PAL219_I0_Msk (0x01UL << LCD_PAL219_I0_Pos) /*!< LCD PAL219: I0 Mask */ -#define LCD_PAL219_R14_0_Pos 16 /*!< LCD PAL219: R14_0 Position */ -#define LCD_PAL219_R14_0_Msk (0x1fUL << LCD_PAL219_R14_0_Pos) /*!< LCD PAL219: R14_0 Mask */ -#define LCD_PAL219_G14_0_Pos 21 /*!< LCD PAL219: G14_0 Position */ -#define LCD_PAL219_G14_0_Msk (0x1fUL << LCD_PAL219_G14_0_Pos) /*!< LCD PAL219: G14_0 Mask */ -#define LCD_PAL219_B14_0_Pos 26 /*!< LCD PAL219: B14_0 Position */ -#define LCD_PAL219_B14_0_Msk (0x1fUL << LCD_PAL219_B14_0_Pos) /*!< LCD PAL219: B14_0 Mask */ -#define LCD_PAL219_I1_Pos 31 /*!< LCD PAL219: I1 Position */ -#define LCD_PAL219_I1_Msk (0x01UL << LCD_PAL219_I1_Pos) /*!< LCD PAL219: I1 Mask */ - -// --------------------------------------- LCD_PAL220 ------------------------------------------- -#define LCD_PAL220_R04_0_Pos 0 /*!< LCD PAL220: R04_0 Position */ -#define LCD_PAL220_R04_0_Msk (0x1fUL << LCD_PAL220_R04_0_Pos) /*!< LCD PAL220: R04_0 Mask */ -#define LCD_PAL220_G04_0_Pos 5 /*!< LCD PAL220: G04_0 Position */ -#define LCD_PAL220_G04_0_Msk (0x1fUL << LCD_PAL220_G04_0_Pos) /*!< LCD PAL220: G04_0 Mask */ -#define LCD_PAL220_B04_0_Pos 10 /*!< LCD PAL220: B04_0 Position */ -#define LCD_PAL220_B04_0_Msk (0x1fUL << LCD_PAL220_B04_0_Pos) /*!< LCD PAL220: B04_0 Mask */ -#define LCD_PAL220_I0_Pos 15 /*!< LCD PAL220: I0 Position */ -#define LCD_PAL220_I0_Msk (0x01UL << LCD_PAL220_I0_Pos) /*!< LCD PAL220: I0 Mask */ -#define LCD_PAL220_R14_0_Pos 16 /*!< LCD PAL220: R14_0 Position */ -#define LCD_PAL220_R14_0_Msk (0x1fUL << LCD_PAL220_R14_0_Pos) /*!< LCD PAL220: R14_0 Mask */ -#define LCD_PAL220_G14_0_Pos 21 /*!< LCD PAL220: G14_0 Position */ -#define LCD_PAL220_G14_0_Msk (0x1fUL << LCD_PAL220_G14_0_Pos) /*!< LCD PAL220: G14_0 Mask */ -#define LCD_PAL220_B14_0_Pos 26 /*!< LCD PAL220: B14_0 Position */ -#define LCD_PAL220_B14_0_Msk (0x1fUL << LCD_PAL220_B14_0_Pos) /*!< LCD PAL220: B14_0 Mask */ -#define LCD_PAL220_I1_Pos 31 /*!< LCD PAL220: I1 Position */ -#define LCD_PAL220_I1_Msk (0x01UL << LCD_PAL220_I1_Pos) /*!< LCD PAL220: I1 Mask */ - -// --------------------------------------- LCD_PAL221 ------------------------------------------- -#define LCD_PAL221_R04_0_Pos 0 /*!< LCD PAL221: R04_0 Position */ -#define LCD_PAL221_R04_0_Msk (0x1fUL << LCD_PAL221_R04_0_Pos) /*!< LCD PAL221: R04_0 Mask */ -#define LCD_PAL221_G04_0_Pos 5 /*!< LCD PAL221: G04_0 Position */ -#define LCD_PAL221_G04_0_Msk (0x1fUL << LCD_PAL221_G04_0_Pos) /*!< LCD PAL221: G04_0 Mask */ -#define LCD_PAL221_B04_0_Pos 10 /*!< LCD PAL221: B04_0 Position */ -#define LCD_PAL221_B04_0_Msk (0x1fUL << LCD_PAL221_B04_0_Pos) /*!< LCD PAL221: B04_0 Mask */ -#define LCD_PAL221_I0_Pos 15 /*!< LCD PAL221: I0 Position */ -#define LCD_PAL221_I0_Msk (0x01UL << LCD_PAL221_I0_Pos) /*!< LCD PAL221: I0 Mask */ -#define LCD_PAL221_R14_0_Pos 16 /*!< LCD PAL221: R14_0 Position */ -#define LCD_PAL221_R14_0_Msk (0x1fUL << LCD_PAL221_R14_0_Pos) /*!< LCD PAL221: R14_0 Mask */ -#define LCD_PAL221_G14_0_Pos 21 /*!< LCD PAL221: G14_0 Position */ -#define LCD_PAL221_G14_0_Msk (0x1fUL << LCD_PAL221_G14_0_Pos) /*!< LCD PAL221: G14_0 Mask */ -#define LCD_PAL221_B14_0_Pos 26 /*!< LCD PAL221: B14_0 Position */ -#define LCD_PAL221_B14_0_Msk (0x1fUL << LCD_PAL221_B14_0_Pos) /*!< LCD PAL221: B14_0 Mask */ -#define LCD_PAL221_I1_Pos 31 /*!< LCD PAL221: I1 Position */ -#define LCD_PAL221_I1_Msk (0x01UL << LCD_PAL221_I1_Pos) /*!< LCD PAL221: I1 Mask */ - -// --------------------------------------- LCD_PAL222 ------------------------------------------- -#define LCD_PAL222_R04_0_Pos 0 /*!< LCD PAL222: R04_0 Position */ -#define LCD_PAL222_R04_0_Msk (0x1fUL << LCD_PAL222_R04_0_Pos) /*!< LCD PAL222: R04_0 Mask */ -#define LCD_PAL222_G04_0_Pos 5 /*!< LCD PAL222: G04_0 Position */ -#define LCD_PAL222_G04_0_Msk (0x1fUL << LCD_PAL222_G04_0_Pos) /*!< LCD PAL222: G04_0 Mask */ -#define LCD_PAL222_B04_0_Pos 10 /*!< LCD PAL222: B04_0 Position */ -#define LCD_PAL222_B04_0_Msk (0x1fUL << LCD_PAL222_B04_0_Pos) /*!< LCD PAL222: B04_0 Mask */ -#define LCD_PAL222_I0_Pos 15 /*!< LCD PAL222: I0 Position */ -#define LCD_PAL222_I0_Msk (0x01UL << LCD_PAL222_I0_Pos) /*!< LCD PAL222: I0 Mask */ -#define LCD_PAL222_R14_0_Pos 16 /*!< LCD PAL222: R14_0 Position */ -#define LCD_PAL222_R14_0_Msk (0x1fUL << LCD_PAL222_R14_0_Pos) /*!< LCD PAL222: R14_0 Mask */ -#define LCD_PAL222_G14_0_Pos 21 /*!< LCD PAL222: G14_0 Position */ -#define LCD_PAL222_G14_0_Msk (0x1fUL << LCD_PAL222_G14_0_Pos) /*!< LCD PAL222: G14_0 Mask */ -#define LCD_PAL222_B14_0_Pos 26 /*!< LCD PAL222: B14_0 Position */ -#define LCD_PAL222_B14_0_Msk (0x1fUL << LCD_PAL222_B14_0_Pos) /*!< LCD PAL222: B14_0 Mask */ -#define LCD_PAL222_I1_Pos 31 /*!< LCD PAL222: I1 Position */ -#define LCD_PAL222_I1_Msk (0x01UL << LCD_PAL222_I1_Pos) /*!< LCD PAL222: I1 Mask */ - -// --------------------------------------- LCD_PAL223 ------------------------------------------- -#define LCD_PAL223_R04_0_Pos 0 /*!< LCD PAL223: R04_0 Position */ -#define LCD_PAL223_R04_0_Msk (0x1fUL << LCD_PAL223_R04_0_Pos) /*!< LCD PAL223: R04_0 Mask */ -#define LCD_PAL223_G04_0_Pos 5 /*!< LCD PAL223: G04_0 Position */ -#define LCD_PAL223_G04_0_Msk (0x1fUL << LCD_PAL223_G04_0_Pos) /*!< LCD PAL223: G04_0 Mask */ -#define LCD_PAL223_B04_0_Pos 10 /*!< LCD PAL223: B04_0 Position */ -#define LCD_PAL223_B04_0_Msk (0x1fUL << LCD_PAL223_B04_0_Pos) /*!< LCD PAL223: B04_0 Mask */ -#define LCD_PAL223_I0_Pos 15 /*!< LCD PAL223: I0 Position */ -#define LCD_PAL223_I0_Msk (0x01UL << LCD_PAL223_I0_Pos) /*!< LCD PAL223: I0 Mask */ -#define LCD_PAL223_R14_0_Pos 16 /*!< LCD PAL223: R14_0 Position */ -#define LCD_PAL223_R14_0_Msk (0x1fUL << LCD_PAL223_R14_0_Pos) /*!< LCD PAL223: R14_0 Mask */ -#define LCD_PAL223_G14_0_Pos 21 /*!< LCD PAL223: G14_0 Position */ -#define LCD_PAL223_G14_0_Msk (0x1fUL << LCD_PAL223_G14_0_Pos) /*!< LCD PAL223: G14_0 Mask */ -#define LCD_PAL223_B14_0_Pos 26 /*!< LCD PAL223: B14_0 Position */ -#define LCD_PAL223_B14_0_Msk (0x1fUL << LCD_PAL223_B14_0_Pos) /*!< LCD PAL223: B14_0 Mask */ -#define LCD_PAL223_I1_Pos 31 /*!< LCD PAL223: I1 Position */ -#define LCD_PAL223_I1_Msk (0x01UL << LCD_PAL223_I1_Pos) /*!< LCD PAL223: I1 Mask */ - -// --------------------------------------- LCD_PAL224 ------------------------------------------- -#define LCD_PAL224_R04_0_Pos 0 /*!< LCD PAL224: R04_0 Position */ -#define LCD_PAL224_R04_0_Msk (0x1fUL << LCD_PAL224_R04_0_Pos) /*!< LCD PAL224: R04_0 Mask */ -#define LCD_PAL224_G04_0_Pos 5 /*!< LCD PAL224: G04_0 Position */ -#define LCD_PAL224_G04_0_Msk (0x1fUL << LCD_PAL224_G04_0_Pos) /*!< LCD PAL224: G04_0 Mask */ -#define LCD_PAL224_B04_0_Pos 10 /*!< LCD PAL224: B04_0 Position */ -#define LCD_PAL224_B04_0_Msk (0x1fUL << LCD_PAL224_B04_0_Pos) /*!< LCD PAL224: B04_0 Mask */ -#define LCD_PAL224_I0_Pos 15 /*!< LCD PAL224: I0 Position */ -#define LCD_PAL224_I0_Msk (0x01UL << LCD_PAL224_I0_Pos) /*!< LCD PAL224: I0 Mask */ -#define LCD_PAL224_R14_0_Pos 16 /*!< LCD PAL224: R14_0 Position */ -#define LCD_PAL224_R14_0_Msk (0x1fUL << LCD_PAL224_R14_0_Pos) /*!< LCD PAL224: R14_0 Mask */ -#define LCD_PAL224_G14_0_Pos 21 /*!< LCD PAL224: G14_0 Position */ -#define LCD_PAL224_G14_0_Msk (0x1fUL << LCD_PAL224_G14_0_Pos) /*!< LCD PAL224: G14_0 Mask */ -#define LCD_PAL224_B14_0_Pos 26 /*!< LCD PAL224: B14_0 Position */ -#define LCD_PAL224_B14_0_Msk (0x1fUL << LCD_PAL224_B14_0_Pos) /*!< LCD PAL224: B14_0 Mask */ -#define LCD_PAL224_I1_Pos 31 /*!< LCD PAL224: I1 Position */ -#define LCD_PAL224_I1_Msk (0x01UL << LCD_PAL224_I1_Pos) /*!< LCD PAL224: I1 Mask */ - -// --------------------------------------- LCD_PAL225 ------------------------------------------- -#define LCD_PAL225_R04_0_Pos 0 /*!< LCD PAL225: R04_0 Position */ -#define LCD_PAL225_R04_0_Msk (0x1fUL << LCD_PAL225_R04_0_Pos) /*!< LCD PAL225: R04_0 Mask */ -#define LCD_PAL225_G04_0_Pos 5 /*!< LCD PAL225: G04_0 Position */ -#define LCD_PAL225_G04_0_Msk (0x1fUL << LCD_PAL225_G04_0_Pos) /*!< LCD PAL225: G04_0 Mask */ -#define LCD_PAL225_B04_0_Pos 10 /*!< LCD PAL225: B04_0 Position */ -#define LCD_PAL225_B04_0_Msk (0x1fUL << LCD_PAL225_B04_0_Pos) /*!< LCD PAL225: B04_0 Mask */ -#define LCD_PAL225_I0_Pos 15 /*!< LCD PAL225: I0 Position */ -#define LCD_PAL225_I0_Msk (0x01UL << LCD_PAL225_I0_Pos) /*!< LCD PAL225: I0 Mask */ -#define LCD_PAL225_R14_0_Pos 16 /*!< LCD PAL225: R14_0 Position */ -#define LCD_PAL225_R14_0_Msk (0x1fUL << LCD_PAL225_R14_0_Pos) /*!< LCD PAL225: R14_0 Mask */ -#define LCD_PAL225_G14_0_Pos 21 /*!< LCD PAL225: G14_0 Position */ -#define LCD_PAL225_G14_0_Msk (0x1fUL << LCD_PAL225_G14_0_Pos) /*!< LCD PAL225: G14_0 Mask */ -#define LCD_PAL225_B14_0_Pos 26 /*!< LCD PAL225: B14_0 Position */ -#define LCD_PAL225_B14_0_Msk (0x1fUL << LCD_PAL225_B14_0_Pos) /*!< LCD PAL225: B14_0 Mask */ -#define LCD_PAL225_I1_Pos 31 /*!< LCD PAL225: I1 Position */ -#define LCD_PAL225_I1_Msk (0x01UL << LCD_PAL225_I1_Pos) /*!< LCD PAL225: I1 Mask */ - -// --------------------------------------- LCD_PAL226 ------------------------------------------- -#define LCD_PAL226_R04_0_Pos 0 /*!< LCD PAL226: R04_0 Position */ -#define LCD_PAL226_R04_0_Msk (0x1fUL << LCD_PAL226_R04_0_Pos) /*!< LCD PAL226: R04_0 Mask */ -#define LCD_PAL226_G04_0_Pos 5 /*!< LCD PAL226: G04_0 Position */ -#define LCD_PAL226_G04_0_Msk (0x1fUL << LCD_PAL226_G04_0_Pos) /*!< LCD PAL226: G04_0 Mask */ -#define LCD_PAL226_B04_0_Pos 10 /*!< LCD PAL226: B04_0 Position */ -#define LCD_PAL226_B04_0_Msk (0x1fUL << LCD_PAL226_B04_0_Pos) /*!< LCD PAL226: B04_0 Mask */ -#define LCD_PAL226_I0_Pos 15 /*!< LCD PAL226: I0 Position */ -#define LCD_PAL226_I0_Msk (0x01UL << LCD_PAL226_I0_Pos) /*!< LCD PAL226: I0 Mask */ -#define LCD_PAL226_R14_0_Pos 16 /*!< LCD PAL226: R14_0 Position */ -#define LCD_PAL226_R14_0_Msk (0x1fUL << LCD_PAL226_R14_0_Pos) /*!< LCD PAL226: R14_0 Mask */ -#define LCD_PAL226_G14_0_Pos 21 /*!< LCD PAL226: G14_0 Position */ -#define LCD_PAL226_G14_0_Msk (0x1fUL << LCD_PAL226_G14_0_Pos) /*!< LCD PAL226: G14_0 Mask */ -#define LCD_PAL226_B14_0_Pos 26 /*!< LCD PAL226: B14_0 Position */ -#define LCD_PAL226_B14_0_Msk (0x1fUL << LCD_PAL226_B14_0_Pos) /*!< LCD PAL226: B14_0 Mask */ -#define LCD_PAL226_I1_Pos 31 /*!< LCD PAL226: I1 Position */ -#define LCD_PAL226_I1_Msk (0x01UL << LCD_PAL226_I1_Pos) /*!< LCD PAL226: I1 Mask */ - -// --------------------------------------- LCD_PAL227 ------------------------------------------- -#define LCD_PAL227_R04_0_Pos 0 /*!< LCD PAL227: R04_0 Position */ -#define LCD_PAL227_R04_0_Msk (0x1fUL << LCD_PAL227_R04_0_Pos) /*!< LCD PAL227: R04_0 Mask */ -#define LCD_PAL227_G04_0_Pos 5 /*!< LCD PAL227: G04_0 Position */ -#define LCD_PAL227_G04_0_Msk (0x1fUL << LCD_PAL227_G04_0_Pos) /*!< LCD PAL227: G04_0 Mask */ -#define LCD_PAL227_B04_0_Pos 10 /*!< LCD PAL227: B04_0 Position */ -#define LCD_PAL227_B04_0_Msk (0x1fUL << LCD_PAL227_B04_0_Pos) /*!< LCD PAL227: B04_0 Mask */ -#define LCD_PAL227_I0_Pos 15 /*!< LCD PAL227: I0 Position */ -#define LCD_PAL227_I0_Msk (0x01UL << LCD_PAL227_I0_Pos) /*!< LCD PAL227: I0 Mask */ -#define LCD_PAL227_R14_0_Pos 16 /*!< LCD PAL227: R14_0 Position */ -#define LCD_PAL227_R14_0_Msk (0x1fUL << LCD_PAL227_R14_0_Pos) /*!< LCD PAL227: R14_0 Mask */ -#define LCD_PAL227_G14_0_Pos 21 /*!< LCD PAL227: G14_0 Position */ -#define LCD_PAL227_G14_0_Msk (0x1fUL << LCD_PAL227_G14_0_Pos) /*!< LCD PAL227: G14_0 Mask */ -#define LCD_PAL227_B14_0_Pos 26 /*!< LCD PAL227: B14_0 Position */ -#define LCD_PAL227_B14_0_Msk (0x1fUL << LCD_PAL227_B14_0_Pos) /*!< LCD PAL227: B14_0 Mask */ -#define LCD_PAL227_I1_Pos 31 /*!< LCD PAL227: I1 Position */ -#define LCD_PAL227_I1_Msk (0x01UL << LCD_PAL227_I1_Pos) /*!< LCD PAL227: I1 Mask */ - -// --------------------------------------- LCD_PAL228 ------------------------------------------- -#define LCD_PAL228_R04_0_Pos 0 /*!< LCD PAL228: R04_0 Position */ -#define LCD_PAL228_R04_0_Msk (0x1fUL << LCD_PAL228_R04_0_Pos) /*!< LCD PAL228: R04_0 Mask */ -#define LCD_PAL228_G04_0_Pos 5 /*!< LCD PAL228: G04_0 Position */ -#define LCD_PAL228_G04_0_Msk (0x1fUL << LCD_PAL228_G04_0_Pos) /*!< LCD PAL228: G04_0 Mask */ -#define LCD_PAL228_B04_0_Pos 10 /*!< LCD PAL228: B04_0 Position */ -#define LCD_PAL228_B04_0_Msk (0x1fUL << LCD_PAL228_B04_0_Pos) /*!< LCD PAL228: B04_0 Mask */ -#define LCD_PAL228_I0_Pos 15 /*!< LCD PAL228: I0 Position */ -#define LCD_PAL228_I0_Msk (0x01UL << LCD_PAL228_I0_Pos) /*!< LCD PAL228: I0 Mask */ -#define LCD_PAL228_R14_0_Pos 16 /*!< LCD PAL228: R14_0 Position */ -#define LCD_PAL228_R14_0_Msk (0x1fUL << LCD_PAL228_R14_0_Pos) /*!< LCD PAL228: R14_0 Mask */ -#define LCD_PAL228_G14_0_Pos 21 /*!< LCD PAL228: G14_0 Position */ -#define LCD_PAL228_G14_0_Msk (0x1fUL << LCD_PAL228_G14_0_Pos) /*!< LCD PAL228: G14_0 Mask */ -#define LCD_PAL228_B14_0_Pos 26 /*!< LCD PAL228: B14_0 Position */ -#define LCD_PAL228_B14_0_Msk (0x1fUL << LCD_PAL228_B14_0_Pos) /*!< LCD PAL228: B14_0 Mask */ -#define LCD_PAL228_I1_Pos 31 /*!< LCD PAL228: I1 Position */ -#define LCD_PAL228_I1_Msk (0x01UL << LCD_PAL228_I1_Pos) /*!< LCD PAL228: I1 Mask */ - -// --------------------------------------- LCD_PAL229 ------------------------------------------- -#define LCD_PAL229_R04_0_Pos 0 /*!< LCD PAL229: R04_0 Position */ -#define LCD_PAL229_R04_0_Msk (0x1fUL << LCD_PAL229_R04_0_Pos) /*!< LCD PAL229: R04_0 Mask */ -#define LCD_PAL229_G04_0_Pos 5 /*!< LCD PAL229: G04_0 Position */ -#define LCD_PAL229_G04_0_Msk (0x1fUL << LCD_PAL229_G04_0_Pos) /*!< LCD PAL229: G04_0 Mask */ -#define LCD_PAL229_B04_0_Pos 10 /*!< LCD PAL229: B04_0 Position */ -#define LCD_PAL229_B04_0_Msk (0x1fUL << LCD_PAL229_B04_0_Pos) /*!< LCD PAL229: B04_0 Mask */ -#define LCD_PAL229_I0_Pos 15 /*!< LCD PAL229: I0 Position */ -#define LCD_PAL229_I0_Msk (0x01UL << LCD_PAL229_I0_Pos) /*!< LCD PAL229: I0 Mask */ -#define LCD_PAL229_R14_0_Pos 16 /*!< LCD PAL229: R14_0 Position */ -#define LCD_PAL229_R14_0_Msk (0x1fUL << LCD_PAL229_R14_0_Pos) /*!< LCD PAL229: R14_0 Mask */ -#define LCD_PAL229_G14_0_Pos 21 /*!< LCD PAL229: G14_0 Position */ -#define LCD_PAL229_G14_0_Msk (0x1fUL << LCD_PAL229_G14_0_Pos) /*!< LCD PAL229: G14_0 Mask */ -#define LCD_PAL229_B14_0_Pos 26 /*!< LCD PAL229: B14_0 Position */ -#define LCD_PAL229_B14_0_Msk (0x1fUL << LCD_PAL229_B14_0_Pos) /*!< LCD PAL229: B14_0 Mask */ -#define LCD_PAL229_I1_Pos 31 /*!< LCD PAL229: I1 Position */ -#define LCD_PAL229_I1_Msk (0x01UL << LCD_PAL229_I1_Pos) /*!< LCD PAL229: I1 Mask */ - -// --------------------------------------- LCD_PAL230 ------------------------------------------- -#define LCD_PAL230_R04_0_Pos 0 /*!< LCD PAL230: R04_0 Position */ -#define LCD_PAL230_R04_0_Msk (0x1fUL << LCD_PAL230_R04_0_Pos) /*!< LCD PAL230: R04_0 Mask */ -#define LCD_PAL230_G04_0_Pos 5 /*!< LCD PAL230: G04_0 Position */ -#define LCD_PAL230_G04_0_Msk (0x1fUL << LCD_PAL230_G04_0_Pos) /*!< LCD PAL230: G04_0 Mask */ -#define LCD_PAL230_B04_0_Pos 10 /*!< LCD PAL230: B04_0 Position */ -#define LCD_PAL230_B04_0_Msk (0x1fUL << LCD_PAL230_B04_0_Pos) /*!< LCD PAL230: B04_0 Mask */ -#define LCD_PAL230_I0_Pos 15 /*!< LCD PAL230: I0 Position */ -#define LCD_PAL230_I0_Msk (0x01UL << LCD_PAL230_I0_Pos) /*!< LCD PAL230: I0 Mask */ -#define LCD_PAL230_R14_0_Pos 16 /*!< LCD PAL230: R14_0 Position */ -#define LCD_PAL230_R14_0_Msk (0x1fUL << LCD_PAL230_R14_0_Pos) /*!< LCD PAL230: R14_0 Mask */ -#define LCD_PAL230_G14_0_Pos 21 /*!< LCD PAL230: G14_0 Position */ -#define LCD_PAL230_G14_0_Msk (0x1fUL << LCD_PAL230_G14_0_Pos) /*!< LCD PAL230: G14_0 Mask */ -#define LCD_PAL230_B14_0_Pos 26 /*!< LCD PAL230: B14_0 Position */ -#define LCD_PAL230_B14_0_Msk (0x1fUL << LCD_PAL230_B14_0_Pos) /*!< LCD PAL230: B14_0 Mask */ -#define LCD_PAL230_I1_Pos 31 /*!< LCD PAL230: I1 Position */ -#define LCD_PAL230_I1_Msk (0x01UL << LCD_PAL230_I1_Pos) /*!< LCD PAL230: I1 Mask */ - -// --------------------------------------- LCD_PAL231 ------------------------------------------- -#define LCD_PAL231_R04_0_Pos 0 /*!< LCD PAL231: R04_0 Position */ -#define LCD_PAL231_R04_0_Msk (0x1fUL << LCD_PAL231_R04_0_Pos) /*!< LCD PAL231: R04_0 Mask */ -#define LCD_PAL231_G04_0_Pos 5 /*!< LCD PAL231: G04_0 Position */ -#define LCD_PAL231_G04_0_Msk (0x1fUL << LCD_PAL231_G04_0_Pos) /*!< LCD PAL231: G04_0 Mask */ -#define LCD_PAL231_B04_0_Pos 10 /*!< LCD PAL231: B04_0 Position */ -#define LCD_PAL231_B04_0_Msk (0x1fUL << LCD_PAL231_B04_0_Pos) /*!< LCD PAL231: B04_0 Mask */ -#define LCD_PAL231_I0_Pos 15 /*!< LCD PAL231: I0 Position */ -#define LCD_PAL231_I0_Msk (0x01UL << LCD_PAL231_I0_Pos) /*!< LCD PAL231: I0 Mask */ -#define LCD_PAL231_R14_0_Pos 16 /*!< LCD PAL231: R14_0 Position */ -#define LCD_PAL231_R14_0_Msk (0x1fUL << LCD_PAL231_R14_0_Pos) /*!< LCD PAL231: R14_0 Mask */ -#define LCD_PAL231_G14_0_Pos 21 /*!< LCD PAL231: G14_0 Position */ -#define LCD_PAL231_G14_0_Msk (0x1fUL << LCD_PAL231_G14_0_Pos) /*!< LCD PAL231: G14_0 Mask */ -#define LCD_PAL231_B14_0_Pos 26 /*!< LCD PAL231: B14_0 Position */ -#define LCD_PAL231_B14_0_Msk (0x1fUL << LCD_PAL231_B14_0_Pos) /*!< LCD PAL231: B14_0 Mask */ -#define LCD_PAL231_I1_Pos 31 /*!< LCD PAL231: I1 Position */ -#define LCD_PAL231_I1_Msk (0x01UL << LCD_PAL231_I1_Pos) /*!< LCD PAL231: I1 Mask */ - -// --------------------------------------- LCD_PAL232 ------------------------------------------- -#define LCD_PAL232_R04_0_Pos 0 /*!< LCD PAL232: R04_0 Position */ -#define LCD_PAL232_R04_0_Msk (0x1fUL << LCD_PAL232_R04_0_Pos) /*!< LCD PAL232: R04_0 Mask */ -#define LCD_PAL232_G04_0_Pos 5 /*!< LCD PAL232: G04_0 Position */ -#define LCD_PAL232_G04_0_Msk (0x1fUL << LCD_PAL232_G04_0_Pos) /*!< LCD PAL232: G04_0 Mask */ -#define LCD_PAL232_B04_0_Pos 10 /*!< LCD PAL232: B04_0 Position */ -#define LCD_PAL232_B04_0_Msk (0x1fUL << LCD_PAL232_B04_0_Pos) /*!< LCD PAL232: B04_0 Mask */ -#define LCD_PAL232_I0_Pos 15 /*!< LCD PAL232: I0 Position */ -#define LCD_PAL232_I0_Msk (0x01UL << LCD_PAL232_I0_Pos) /*!< LCD PAL232: I0 Mask */ -#define LCD_PAL232_R14_0_Pos 16 /*!< LCD PAL232: R14_0 Position */ -#define LCD_PAL232_R14_0_Msk (0x1fUL << LCD_PAL232_R14_0_Pos) /*!< LCD PAL232: R14_0 Mask */ -#define LCD_PAL232_G14_0_Pos 21 /*!< LCD PAL232: G14_0 Position */ -#define LCD_PAL232_G14_0_Msk (0x1fUL << LCD_PAL232_G14_0_Pos) /*!< LCD PAL232: G14_0 Mask */ -#define LCD_PAL232_B14_0_Pos 26 /*!< LCD PAL232: B14_0 Position */ -#define LCD_PAL232_B14_0_Msk (0x1fUL << LCD_PAL232_B14_0_Pos) /*!< LCD PAL232: B14_0 Mask */ -#define LCD_PAL232_I1_Pos 31 /*!< LCD PAL232: I1 Position */ -#define LCD_PAL232_I1_Msk (0x01UL << LCD_PAL232_I1_Pos) /*!< LCD PAL232: I1 Mask */ - -// --------------------------------------- LCD_PAL233 ------------------------------------------- -#define LCD_PAL233_R04_0_Pos 0 /*!< LCD PAL233: R04_0 Position */ -#define LCD_PAL233_R04_0_Msk (0x1fUL << LCD_PAL233_R04_0_Pos) /*!< LCD PAL233: R04_0 Mask */ -#define LCD_PAL233_G04_0_Pos 5 /*!< LCD PAL233: G04_0 Position */ -#define LCD_PAL233_G04_0_Msk (0x1fUL << LCD_PAL233_G04_0_Pos) /*!< LCD PAL233: G04_0 Mask */ -#define LCD_PAL233_B04_0_Pos 10 /*!< LCD PAL233: B04_0 Position */ -#define LCD_PAL233_B04_0_Msk (0x1fUL << LCD_PAL233_B04_0_Pos) /*!< LCD PAL233: B04_0 Mask */ -#define LCD_PAL233_I0_Pos 15 /*!< LCD PAL233: I0 Position */ -#define LCD_PAL233_I0_Msk (0x01UL << LCD_PAL233_I0_Pos) /*!< LCD PAL233: I0 Mask */ -#define LCD_PAL233_R14_0_Pos 16 /*!< LCD PAL233: R14_0 Position */ -#define LCD_PAL233_R14_0_Msk (0x1fUL << LCD_PAL233_R14_0_Pos) /*!< LCD PAL233: R14_0 Mask */ -#define LCD_PAL233_G14_0_Pos 21 /*!< LCD PAL233: G14_0 Position */ -#define LCD_PAL233_G14_0_Msk (0x1fUL << LCD_PAL233_G14_0_Pos) /*!< LCD PAL233: G14_0 Mask */ -#define LCD_PAL233_B14_0_Pos 26 /*!< LCD PAL233: B14_0 Position */ -#define LCD_PAL233_B14_0_Msk (0x1fUL << LCD_PAL233_B14_0_Pos) /*!< LCD PAL233: B14_0 Mask */ -#define LCD_PAL233_I1_Pos 31 /*!< LCD PAL233: I1 Position */ -#define LCD_PAL233_I1_Msk (0x01UL << LCD_PAL233_I1_Pos) /*!< LCD PAL233: I1 Mask */ - -// --------------------------------------- LCD_PAL234 ------------------------------------------- -#define LCD_PAL234_R04_0_Pos 0 /*!< LCD PAL234: R04_0 Position */ -#define LCD_PAL234_R04_0_Msk (0x1fUL << LCD_PAL234_R04_0_Pos) /*!< LCD PAL234: R04_0 Mask */ -#define LCD_PAL234_G04_0_Pos 5 /*!< LCD PAL234: G04_0 Position */ -#define LCD_PAL234_G04_0_Msk (0x1fUL << LCD_PAL234_G04_0_Pos) /*!< LCD PAL234: G04_0 Mask */ -#define LCD_PAL234_B04_0_Pos 10 /*!< LCD PAL234: B04_0 Position */ -#define LCD_PAL234_B04_0_Msk (0x1fUL << LCD_PAL234_B04_0_Pos) /*!< LCD PAL234: B04_0 Mask */ -#define LCD_PAL234_I0_Pos 15 /*!< LCD PAL234: I0 Position */ -#define LCD_PAL234_I0_Msk (0x01UL << LCD_PAL234_I0_Pos) /*!< LCD PAL234: I0 Mask */ -#define LCD_PAL234_R14_0_Pos 16 /*!< LCD PAL234: R14_0 Position */ -#define LCD_PAL234_R14_0_Msk (0x1fUL << LCD_PAL234_R14_0_Pos) /*!< LCD PAL234: R14_0 Mask */ -#define LCD_PAL234_G14_0_Pos 21 /*!< LCD PAL234: G14_0 Position */ -#define LCD_PAL234_G14_0_Msk (0x1fUL << LCD_PAL234_G14_0_Pos) /*!< LCD PAL234: G14_0 Mask */ -#define LCD_PAL234_B14_0_Pos 26 /*!< LCD PAL234: B14_0 Position */ -#define LCD_PAL234_B14_0_Msk (0x1fUL << LCD_PAL234_B14_0_Pos) /*!< LCD PAL234: B14_0 Mask */ -#define LCD_PAL234_I1_Pos 31 /*!< LCD PAL234: I1 Position */ -#define LCD_PAL234_I1_Msk (0x01UL << LCD_PAL234_I1_Pos) /*!< LCD PAL234: I1 Mask */ - -// --------------------------------------- LCD_PAL235 ------------------------------------------- -#define LCD_PAL235_R04_0_Pos 0 /*!< LCD PAL235: R04_0 Position */ -#define LCD_PAL235_R04_0_Msk (0x1fUL << LCD_PAL235_R04_0_Pos) /*!< LCD PAL235: R04_0 Mask */ -#define LCD_PAL235_G04_0_Pos 5 /*!< LCD PAL235: G04_0 Position */ -#define LCD_PAL235_G04_0_Msk (0x1fUL << LCD_PAL235_G04_0_Pos) /*!< LCD PAL235: G04_0 Mask */ -#define LCD_PAL235_B04_0_Pos 10 /*!< LCD PAL235: B04_0 Position */ -#define LCD_PAL235_B04_0_Msk (0x1fUL << LCD_PAL235_B04_0_Pos) /*!< LCD PAL235: B04_0 Mask */ -#define LCD_PAL235_I0_Pos 15 /*!< LCD PAL235: I0 Position */ -#define LCD_PAL235_I0_Msk (0x01UL << LCD_PAL235_I0_Pos) /*!< LCD PAL235: I0 Mask */ -#define LCD_PAL235_R14_0_Pos 16 /*!< LCD PAL235: R14_0 Position */ -#define LCD_PAL235_R14_0_Msk (0x1fUL << LCD_PAL235_R14_0_Pos) /*!< LCD PAL235: R14_0 Mask */ -#define LCD_PAL235_G14_0_Pos 21 /*!< LCD PAL235: G14_0 Position */ -#define LCD_PAL235_G14_0_Msk (0x1fUL << LCD_PAL235_G14_0_Pos) /*!< LCD PAL235: G14_0 Mask */ -#define LCD_PAL235_B14_0_Pos 26 /*!< LCD PAL235: B14_0 Position */ -#define LCD_PAL235_B14_0_Msk (0x1fUL << LCD_PAL235_B14_0_Pos) /*!< LCD PAL235: B14_0 Mask */ -#define LCD_PAL235_I1_Pos 31 /*!< LCD PAL235: I1 Position */ -#define LCD_PAL235_I1_Msk (0x01UL << LCD_PAL235_I1_Pos) /*!< LCD PAL235: I1 Mask */ - -// --------------------------------------- LCD_PAL236 ------------------------------------------- -#define LCD_PAL236_R04_0_Pos 0 /*!< LCD PAL236: R04_0 Position */ -#define LCD_PAL236_R04_0_Msk (0x1fUL << LCD_PAL236_R04_0_Pos) /*!< LCD PAL236: R04_0 Mask */ -#define LCD_PAL236_G04_0_Pos 5 /*!< LCD PAL236: G04_0 Position */ -#define LCD_PAL236_G04_0_Msk (0x1fUL << LCD_PAL236_G04_0_Pos) /*!< LCD PAL236: G04_0 Mask */ -#define LCD_PAL236_B04_0_Pos 10 /*!< LCD PAL236: B04_0 Position */ -#define LCD_PAL236_B04_0_Msk (0x1fUL << LCD_PAL236_B04_0_Pos) /*!< LCD PAL236: B04_0 Mask */ -#define LCD_PAL236_I0_Pos 15 /*!< LCD PAL236: I0 Position */ -#define LCD_PAL236_I0_Msk (0x01UL << LCD_PAL236_I0_Pos) /*!< LCD PAL236: I0 Mask */ -#define LCD_PAL236_R14_0_Pos 16 /*!< LCD PAL236: R14_0 Position */ -#define LCD_PAL236_R14_0_Msk (0x1fUL << LCD_PAL236_R14_0_Pos) /*!< LCD PAL236: R14_0 Mask */ -#define LCD_PAL236_G14_0_Pos 21 /*!< LCD PAL236: G14_0 Position */ -#define LCD_PAL236_G14_0_Msk (0x1fUL << LCD_PAL236_G14_0_Pos) /*!< LCD PAL236: G14_0 Mask */ -#define LCD_PAL236_B14_0_Pos 26 /*!< LCD PAL236: B14_0 Position */ -#define LCD_PAL236_B14_0_Msk (0x1fUL << LCD_PAL236_B14_0_Pos) /*!< LCD PAL236: B14_0 Mask */ -#define LCD_PAL236_I1_Pos 31 /*!< LCD PAL236: I1 Position */ -#define LCD_PAL236_I1_Msk (0x01UL << LCD_PAL236_I1_Pos) /*!< LCD PAL236: I1 Mask */ - -// --------------------------------------- LCD_PAL237 ------------------------------------------- -#define LCD_PAL237_R04_0_Pos 0 /*!< LCD PAL237: R04_0 Position */ -#define LCD_PAL237_R04_0_Msk (0x1fUL << LCD_PAL237_R04_0_Pos) /*!< LCD PAL237: R04_0 Mask */ -#define LCD_PAL237_G04_0_Pos 5 /*!< LCD PAL237: G04_0 Position */ -#define LCD_PAL237_G04_0_Msk (0x1fUL << LCD_PAL237_G04_0_Pos) /*!< LCD PAL237: G04_0 Mask */ -#define LCD_PAL237_B04_0_Pos 10 /*!< LCD PAL237: B04_0 Position */ -#define LCD_PAL237_B04_0_Msk (0x1fUL << LCD_PAL237_B04_0_Pos) /*!< LCD PAL237: B04_0 Mask */ -#define LCD_PAL237_I0_Pos 15 /*!< LCD PAL237: I0 Position */ -#define LCD_PAL237_I0_Msk (0x01UL << LCD_PAL237_I0_Pos) /*!< LCD PAL237: I0 Mask */ -#define LCD_PAL237_R14_0_Pos 16 /*!< LCD PAL237: R14_0 Position */ -#define LCD_PAL237_R14_0_Msk (0x1fUL << LCD_PAL237_R14_0_Pos) /*!< LCD PAL237: R14_0 Mask */ -#define LCD_PAL237_G14_0_Pos 21 /*!< LCD PAL237: G14_0 Position */ -#define LCD_PAL237_G14_0_Msk (0x1fUL << LCD_PAL237_G14_0_Pos) /*!< LCD PAL237: G14_0 Mask */ -#define LCD_PAL237_B14_0_Pos 26 /*!< LCD PAL237: B14_0 Position */ -#define LCD_PAL237_B14_0_Msk (0x1fUL << LCD_PAL237_B14_0_Pos) /*!< LCD PAL237: B14_0 Mask */ -#define LCD_PAL237_I1_Pos 31 /*!< LCD PAL237: I1 Position */ -#define LCD_PAL237_I1_Msk (0x01UL << LCD_PAL237_I1_Pos) /*!< LCD PAL237: I1 Mask */ - -// --------------------------------------- LCD_PAL238 ------------------------------------------- -#define LCD_PAL238_R04_0_Pos 0 /*!< LCD PAL238: R04_0 Position */ -#define LCD_PAL238_R04_0_Msk (0x1fUL << LCD_PAL238_R04_0_Pos) /*!< LCD PAL238: R04_0 Mask */ -#define LCD_PAL238_G04_0_Pos 5 /*!< LCD PAL238: G04_0 Position */ -#define LCD_PAL238_G04_0_Msk (0x1fUL << LCD_PAL238_G04_0_Pos) /*!< LCD PAL238: G04_0 Mask */ -#define LCD_PAL238_B04_0_Pos 10 /*!< LCD PAL238: B04_0 Position */ -#define LCD_PAL238_B04_0_Msk (0x1fUL << LCD_PAL238_B04_0_Pos) /*!< LCD PAL238: B04_0 Mask */ -#define LCD_PAL238_I0_Pos 15 /*!< LCD PAL238: I0 Position */ -#define LCD_PAL238_I0_Msk (0x01UL << LCD_PAL238_I0_Pos) /*!< LCD PAL238: I0 Mask */ -#define LCD_PAL238_R14_0_Pos 16 /*!< LCD PAL238: R14_0 Position */ -#define LCD_PAL238_R14_0_Msk (0x1fUL << LCD_PAL238_R14_0_Pos) /*!< LCD PAL238: R14_0 Mask */ -#define LCD_PAL238_G14_0_Pos 21 /*!< LCD PAL238: G14_0 Position */ -#define LCD_PAL238_G14_0_Msk (0x1fUL << LCD_PAL238_G14_0_Pos) /*!< LCD PAL238: G14_0 Mask */ -#define LCD_PAL238_B14_0_Pos 26 /*!< LCD PAL238: B14_0 Position */ -#define LCD_PAL238_B14_0_Msk (0x1fUL << LCD_PAL238_B14_0_Pos) /*!< LCD PAL238: B14_0 Mask */ -#define LCD_PAL238_I1_Pos 31 /*!< LCD PAL238: I1 Position */ -#define LCD_PAL238_I1_Msk (0x01UL << LCD_PAL238_I1_Pos) /*!< LCD PAL238: I1 Mask */ - -// --------------------------------------- LCD_PAL239 ------------------------------------------- -#define LCD_PAL239_R04_0_Pos 0 /*!< LCD PAL239: R04_0 Position */ -#define LCD_PAL239_R04_0_Msk (0x1fUL << LCD_PAL239_R04_0_Pos) /*!< LCD PAL239: R04_0 Mask */ -#define LCD_PAL239_G04_0_Pos 5 /*!< LCD PAL239: G04_0 Position */ -#define LCD_PAL239_G04_0_Msk (0x1fUL << LCD_PAL239_G04_0_Pos) /*!< LCD PAL239: G04_0 Mask */ -#define LCD_PAL239_B04_0_Pos 10 /*!< LCD PAL239: B04_0 Position */ -#define LCD_PAL239_B04_0_Msk (0x1fUL << LCD_PAL239_B04_0_Pos) /*!< LCD PAL239: B04_0 Mask */ -#define LCD_PAL239_I0_Pos 15 /*!< LCD PAL239: I0 Position */ -#define LCD_PAL239_I0_Msk (0x01UL << LCD_PAL239_I0_Pos) /*!< LCD PAL239: I0 Mask */ -#define LCD_PAL239_R14_0_Pos 16 /*!< LCD PAL239: R14_0 Position */ -#define LCD_PAL239_R14_0_Msk (0x1fUL << LCD_PAL239_R14_0_Pos) /*!< LCD PAL239: R14_0 Mask */ -#define LCD_PAL239_G14_0_Pos 21 /*!< LCD PAL239: G14_0 Position */ -#define LCD_PAL239_G14_0_Msk (0x1fUL << LCD_PAL239_G14_0_Pos) /*!< LCD PAL239: G14_0 Mask */ -#define LCD_PAL239_B14_0_Pos 26 /*!< LCD PAL239: B14_0 Position */ -#define LCD_PAL239_B14_0_Msk (0x1fUL << LCD_PAL239_B14_0_Pos) /*!< LCD PAL239: B14_0 Mask */ -#define LCD_PAL239_I1_Pos 31 /*!< LCD PAL239: I1 Position */ -#define LCD_PAL239_I1_Msk (0x01UL << LCD_PAL239_I1_Pos) /*!< LCD PAL239: I1 Mask */ - -// --------------------------------------- LCD_PAL240 ------------------------------------------- -#define LCD_PAL240_R04_0_Pos 0 /*!< LCD PAL240: R04_0 Position */ -#define LCD_PAL240_R04_0_Msk (0x1fUL << LCD_PAL240_R04_0_Pos) /*!< LCD PAL240: R04_0 Mask */ -#define LCD_PAL240_G04_0_Pos 5 /*!< LCD PAL240: G04_0 Position */ -#define LCD_PAL240_G04_0_Msk (0x1fUL << LCD_PAL240_G04_0_Pos) /*!< LCD PAL240: G04_0 Mask */ -#define LCD_PAL240_B04_0_Pos 10 /*!< LCD PAL240: B04_0 Position */ -#define LCD_PAL240_B04_0_Msk (0x1fUL << LCD_PAL240_B04_0_Pos) /*!< LCD PAL240: B04_0 Mask */ -#define LCD_PAL240_I0_Pos 15 /*!< LCD PAL240: I0 Position */ -#define LCD_PAL240_I0_Msk (0x01UL << LCD_PAL240_I0_Pos) /*!< LCD PAL240: I0 Mask */ -#define LCD_PAL240_R14_0_Pos 16 /*!< LCD PAL240: R14_0 Position */ -#define LCD_PAL240_R14_0_Msk (0x1fUL << LCD_PAL240_R14_0_Pos) /*!< LCD PAL240: R14_0 Mask */ -#define LCD_PAL240_G14_0_Pos 21 /*!< LCD PAL240: G14_0 Position */ -#define LCD_PAL240_G14_0_Msk (0x1fUL << LCD_PAL240_G14_0_Pos) /*!< LCD PAL240: G14_0 Mask */ -#define LCD_PAL240_B14_0_Pos 26 /*!< LCD PAL240: B14_0 Position */ -#define LCD_PAL240_B14_0_Msk (0x1fUL << LCD_PAL240_B14_0_Pos) /*!< LCD PAL240: B14_0 Mask */ -#define LCD_PAL240_I1_Pos 31 /*!< LCD PAL240: I1 Position */ -#define LCD_PAL240_I1_Msk (0x01UL << LCD_PAL240_I1_Pos) /*!< LCD PAL240: I1 Mask */ - -// --------------------------------------- LCD_PAL241 ------------------------------------------- -#define LCD_PAL241_R04_0_Pos 0 /*!< LCD PAL241: R04_0 Position */ -#define LCD_PAL241_R04_0_Msk (0x1fUL << LCD_PAL241_R04_0_Pos) /*!< LCD PAL241: R04_0 Mask */ -#define LCD_PAL241_G04_0_Pos 5 /*!< LCD PAL241: G04_0 Position */ -#define LCD_PAL241_G04_0_Msk (0x1fUL << LCD_PAL241_G04_0_Pos) /*!< LCD PAL241: G04_0 Mask */ -#define LCD_PAL241_B04_0_Pos 10 /*!< LCD PAL241: B04_0 Position */ -#define LCD_PAL241_B04_0_Msk (0x1fUL << LCD_PAL241_B04_0_Pos) /*!< LCD PAL241: B04_0 Mask */ -#define LCD_PAL241_I0_Pos 15 /*!< LCD PAL241: I0 Position */ -#define LCD_PAL241_I0_Msk (0x01UL << LCD_PAL241_I0_Pos) /*!< LCD PAL241: I0 Mask */ -#define LCD_PAL241_R14_0_Pos 16 /*!< LCD PAL241: R14_0 Position */ -#define LCD_PAL241_R14_0_Msk (0x1fUL << LCD_PAL241_R14_0_Pos) /*!< LCD PAL241: R14_0 Mask */ -#define LCD_PAL241_G14_0_Pos 21 /*!< LCD PAL241: G14_0 Position */ -#define LCD_PAL241_G14_0_Msk (0x1fUL << LCD_PAL241_G14_0_Pos) /*!< LCD PAL241: G14_0 Mask */ -#define LCD_PAL241_B14_0_Pos 26 /*!< LCD PAL241: B14_0 Position */ -#define LCD_PAL241_B14_0_Msk (0x1fUL << LCD_PAL241_B14_0_Pos) /*!< LCD PAL241: B14_0 Mask */ -#define LCD_PAL241_I1_Pos 31 /*!< LCD PAL241: I1 Position */ -#define LCD_PAL241_I1_Msk (0x01UL << LCD_PAL241_I1_Pos) /*!< LCD PAL241: I1 Mask */ - -// --------------------------------------- LCD_PAL242 ------------------------------------------- -#define LCD_PAL242_R04_0_Pos 0 /*!< LCD PAL242: R04_0 Position */ -#define LCD_PAL242_R04_0_Msk (0x1fUL << LCD_PAL242_R04_0_Pos) /*!< LCD PAL242: R04_0 Mask */ -#define LCD_PAL242_G04_0_Pos 5 /*!< LCD PAL242: G04_0 Position */ -#define LCD_PAL242_G04_0_Msk (0x1fUL << LCD_PAL242_G04_0_Pos) /*!< LCD PAL242: G04_0 Mask */ -#define LCD_PAL242_B04_0_Pos 10 /*!< LCD PAL242: B04_0 Position */ -#define LCD_PAL242_B04_0_Msk (0x1fUL << LCD_PAL242_B04_0_Pos) /*!< LCD PAL242: B04_0 Mask */ -#define LCD_PAL242_I0_Pos 15 /*!< LCD PAL242: I0 Position */ -#define LCD_PAL242_I0_Msk (0x01UL << LCD_PAL242_I0_Pos) /*!< LCD PAL242: I0 Mask */ -#define LCD_PAL242_R14_0_Pos 16 /*!< LCD PAL242: R14_0 Position */ -#define LCD_PAL242_R14_0_Msk (0x1fUL << LCD_PAL242_R14_0_Pos) /*!< LCD PAL242: R14_0 Mask */ -#define LCD_PAL242_G14_0_Pos 21 /*!< LCD PAL242: G14_0 Position */ -#define LCD_PAL242_G14_0_Msk (0x1fUL << LCD_PAL242_G14_0_Pos) /*!< LCD PAL242: G14_0 Mask */ -#define LCD_PAL242_B14_0_Pos 26 /*!< LCD PAL242: B14_0 Position */ -#define LCD_PAL242_B14_0_Msk (0x1fUL << LCD_PAL242_B14_0_Pos) /*!< LCD PAL242: B14_0 Mask */ -#define LCD_PAL242_I1_Pos 31 /*!< LCD PAL242: I1 Position */ -#define LCD_PAL242_I1_Msk (0x01UL << LCD_PAL242_I1_Pos) /*!< LCD PAL242: I1 Mask */ - -// --------------------------------------- LCD_PAL243 ------------------------------------------- -#define LCD_PAL243_R04_0_Pos 0 /*!< LCD PAL243: R04_0 Position */ -#define LCD_PAL243_R04_0_Msk (0x1fUL << LCD_PAL243_R04_0_Pos) /*!< LCD PAL243: R04_0 Mask */ -#define LCD_PAL243_G04_0_Pos 5 /*!< LCD PAL243: G04_0 Position */ -#define LCD_PAL243_G04_0_Msk (0x1fUL << LCD_PAL243_G04_0_Pos) /*!< LCD PAL243: G04_0 Mask */ -#define LCD_PAL243_B04_0_Pos 10 /*!< LCD PAL243: B04_0 Position */ -#define LCD_PAL243_B04_0_Msk (0x1fUL << LCD_PAL243_B04_0_Pos) /*!< LCD PAL243: B04_0 Mask */ -#define LCD_PAL243_I0_Pos 15 /*!< LCD PAL243: I0 Position */ -#define LCD_PAL243_I0_Msk (0x01UL << LCD_PAL243_I0_Pos) /*!< LCD PAL243: I0 Mask */ -#define LCD_PAL243_R14_0_Pos 16 /*!< LCD PAL243: R14_0 Position */ -#define LCD_PAL243_R14_0_Msk (0x1fUL << LCD_PAL243_R14_0_Pos) /*!< LCD PAL243: R14_0 Mask */ -#define LCD_PAL243_G14_0_Pos 21 /*!< LCD PAL243: G14_0 Position */ -#define LCD_PAL243_G14_0_Msk (0x1fUL << LCD_PAL243_G14_0_Pos) /*!< LCD PAL243: G14_0 Mask */ -#define LCD_PAL243_B14_0_Pos 26 /*!< LCD PAL243: B14_0 Position */ -#define LCD_PAL243_B14_0_Msk (0x1fUL << LCD_PAL243_B14_0_Pos) /*!< LCD PAL243: B14_0 Mask */ -#define LCD_PAL243_I1_Pos 31 /*!< LCD PAL243: I1 Position */ -#define LCD_PAL243_I1_Msk (0x01UL << LCD_PAL243_I1_Pos) /*!< LCD PAL243: I1 Mask */ - -// --------------------------------------- LCD_PAL244 ------------------------------------------- -#define LCD_PAL244_R04_0_Pos 0 /*!< LCD PAL244: R04_0 Position */ -#define LCD_PAL244_R04_0_Msk (0x1fUL << LCD_PAL244_R04_0_Pos) /*!< LCD PAL244: R04_0 Mask */ -#define LCD_PAL244_G04_0_Pos 5 /*!< LCD PAL244: G04_0 Position */ -#define LCD_PAL244_G04_0_Msk (0x1fUL << LCD_PAL244_G04_0_Pos) /*!< LCD PAL244: G04_0 Mask */ -#define LCD_PAL244_B04_0_Pos 10 /*!< LCD PAL244: B04_0 Position */ -#define LCD_PAL244_B04_0_Msk (0x1fUL << LCD_PAL244_B04_0_Pos) /*!< LCD PAL244: B04_0 Mask */ -#define LCD_PAL244_I0_Pos 15 /*!< LCD PAL244: I0 Position */ -#define LCD_PAL244_I0_Msk (0x01UL << LCD_PAL244_I0_Pos) /*!< LCD PAL244: I0 Mask */ -#define LCD_PAL244_R14_0_Pos 16 /*!< LCD PAL244: R14_0 Position */ -#define LCD_PAL244_R14_0_Msk (0x1fUL << LCD_PAL244_R14_0_Pos) /*!< LCD PAL244: R14_0 Mask */ -#define LCD_PAL244_G14_0_Pos 21 /*!< LCD PAL244: G14_0 Position */ -#define LCD_PAL244_G14_0_Msk (0x1fUL << LCD_PAL244_G14_0_Pos) /*!< LCD PAL244: G14_0 Mask */ -#define LCD_PAL244_B14_0_Pos 26 /*!< LCD PAL244: B14_0 Position */ -#define LCD_PAL244_B14_0_Msk (0x1fUL << LCD_PAL244_B14_0_Pos) /*!< LCD PAL244: B14_0 Mask */ -#define LCD_PAL244_I1_Pos 31 /*!< LCD PAL244: I1 Position */ -#define LCD_PAL244_I1_Msk (0x01UL << LCD_PAL244_I1_Pos) /*!< LCD PAL244: I1 Mask */ - -// --------------------------------------- LCD_PAL245 ------------------------------------------- -#define LCD_PAL245_R04_0_Pos 0 /*!< LCD PAL245: R04_0 Position */ -#define LCD_PAL245_R04_0_Msk (0x1fUL << LCD_PAL245_R04_0_Pos) /*!< LCD PAL245: R04_0 Mask */ -#define LCD_PAL245_G04_0_Pos 5 /*!< LCD PAL245: G04_0 Position */ -#define LCD_PAL245_G04_0_Msk (0x1fUL << LCD_PAL245_G04_0_Pos) /*!< LCD PAL245: G04_0 Mask */ -#define LCD_PAL245_B04_0_Pos 10 /*!< LCD PAL245: B04_0 Position */ -#define LCD_PAL245_B04_0_Msk (0x1fUL << LCD_PAL245_B04_0_Pos) /*!< LCD PAL245: B04_0 Mask */ -#define LCD_PAL245_I0_Pos 15 /*!< LCD PAL245: I0 Position */ -#define LCD_PAL245_I0_Msk (0x01UL << LCD_PAL245_I0_Pos) /*!< LCD PAL245: I0 Mask */ -#define LCD_PAL245_R14_0_Pos 16 /*!< LCD PAL245: R14_0 Position */ -#define LCD_PAL245_R14_0_Msk (0x1fUL << LCD_PAL245_R14_0_Pos) /*!< LCD PAL245: R14_0 Mask */ -#define LCD_PAL245_G14_0_Pos 21 /*!< LCD PAL245: G14_0 Position */ -#define LCD_PAL245_G14_0_Msk (0x1fUL << LCD_PAL245_G14_0_Pos) /*!< LCD PAL245: G14_0 Mask */ -#define LCD_PAL245_B14_0_Pos 26 /*!< LCD PAL245: B14_0 Position */ -#define LCD_PAL245_B14_0_Msk (0x1fUL << LCD_PAL245_B14_0_Pos) /*!< LCD PAL245: B14_0 Mask */ -#define LCD_PAL245_I1_Pos 31 /*!< LCD PAL245: I1 Position */ -#define LCD_PAL245_I1_Msk (0x01UL << LCD_PAL245_I1_Pos) /*!< LCD PAL245: I1 Mask */ - -// --------------------------------------- LCD_PAL246 ------------------------------------------- -#define LCD_PAL246_R04_0_Pos 0 /*!< LCD PAL246: R04_0 Position */ -#define LCD_PAL246_R04_0_Msk (0x1fUL << LCD_PAL246_R04_0_Pos) /*!< LCD PAL246: R04_0 Mask */ -#define LCD_PAL246_G04_0_Pos 5 /*!< LCD PAL246: G04_0 Position */ -#define LCD_PAL246_G04_0_Msk (0x1fUL << LCD_PAL246_G04_0_Pos) /*!< LCD PAL246: G04_0 Mask */ -#define LCD_PAL246_B04_0_Pos 10 /*!< LCD PAL246: B04_0 Position */ -#define LCD_PAL246_B04_0_Msk (0x1fUL << LCD_PAL246_B04_0_Pos) /*!< LCD PAL246: B04_0 Mask */ -#define LCD_PAL246_I0_Pos 15 /*!< LCD PAL246: I0 Position */ -#define LCD_PAL246_I0_Msk (0x01UL << LCD_PAL246_I0_Pos) /*!< LCD PAL246: I0 Mask */ -#define LCD_PAL246_R14_0_Pos 16 /*!< LCD PAL246: R14_0 Position */ -#define LCD_PAL246_R14_0_Msk (0x1fUL << LCD_PAL246_R14_0_Pos) /*!< LCD PAL246: R14_0 Mask */ -#define LCD_PAL246_G14_0_Pos 21 /*!< LCD PAL246: G14_0 Position */ -#define LCD_PAL246_G14_0_Msk (0x1fUL << LCD_PAL246_G14_0_Pos) /*!< LCD PAL246: G14_0 Mask */ -#define LCD_PAL246_B14_0_Pos 26 /*!< LCD PAL246: B14_0 Position */ -#define LCD_PAL246_B14_0_Msk (0x1fUL << LCD_PAL246_B14_0_Pos) /*!< LCD PAL246: B14_0 Mask */ -#define LCD_PAL246_I1_Pos 31 /*!< LCD PAL246: I1 Position */ -#define LCD_PAL246_I1_Msk (0x01UL << LCD_PAL246_I1_Pos) /*!< LCD PAL246: I1 Mask */ - -// --------------------------------------- LCD_PAL247 ------------------------------------------- -#define LCD_PAL247_R04_0_Pos 0 /*!< LCD PAL247: R04_0 Position */ -#define LCD_PAL247_R04_0_Msk (0x1fUL << LCD_PAL247_R04_0_Pos) /*!< LCD PAL247: R04_0 Mask */ -#define LCD_PAL247_G04_0_Pos 5 /*!< LCD PAL247: G04_0 Position */ -#define LCD_PAL247_G04_0_Msk (0x1fUL << LCD_PAL247_G04_0_Pos) /*!< LCD PAL247: G04_0 Mask */ -#define LCD_PAL247_B04_0_Pos 10 /*!< LCD PAL247: B04_0 Position */ -#define LCD_PAL247_B04_0_Msk (0x1fUL << LCD_PAL247_B04_0_Pos) /*!< LCD PAL247: B04_0 Mask */ -#define LCD_PAL247_I0_Pos 15 /*!< LCD PAL247: I0 Position */ -#define LCD_PAL247_I0_Msk (0x01UL << LCD_PAL247_I0_Pos) /*!< LCD PAL247: I0 Mask */ -#define LCD_PAL247_R14_0_Pos 16 /*!< LCD PAL247: R14_0 Position */ -#define LCD_PAL247_R14_0_Msk (0x1fUL << LCD_PAL247_R14_0_Pos) /*!< LCD PAL247: R14_0 Mask */ -#define LCD_PAL247_G14_0_Pos 21 /*!< LCD PAL247: G14_0 Position */ -#define LCD_PAL247_G14_0_Msk (0x1fUL << LCD_PAL247_G14_0_Pos) /*!< LCD PAL247: G14_0 Mask */ -#define LCD_PAL247_B14_0_Pos 26 /*!< LCD PAL247: B14_0 Position */ -#define LCD_PAL247_B14_0_Msk (0x1fUL << LCD_PAL247_B14_0_Pos) /*!< LCD PAL247: B14_0 Mask */ -#define LCD_PAL247_I1_Pos 31 /*!< LCD PAL247: I1 Position */ -#define LCD_PAL247_I1_Msk (0x01UL << LCD_PAL247_I1_Pos) /*!< LCD PAL247: I1 Mask */ - -// --------------------------------------- LCD_PAL248 ------------------------------------------- -#define LCD_PAL248_R04_0_Pos 0 /*!< LCD PAL248: R04_0 Position */ -#define LCD_PAL248_R04_0_Msk (0x1fUL << LCD_PAL248_R04_0_Pos) /*!< LCD PAL248: R04_0 Mask */ -#define LCD_PAL248_G04_0_Pos 5 /*!< LCD PAL248: G04_0 Position */ -#define LCD_PAL248_G04_0_Msk (0x1fUL << LCD_PAL248_G04_0_Pos) /*!< LCD PAL248: G04_0 Mask */ -#define LCD_PAL248_B04_0_Pos 10 /*!< LCD PAL248: B04_0 Position */ -#define LCD_PAL248_B04_0_Msk (0x1fUL << LCD_PAL248_B04_0_Pos) /*!< LCD PAL248: B04_0 Mask */ -#define LCD_PAL248_I0_Pos 15 /*!< LCD PAL248: I0 Position */ -#define LCD_PAL248_I0_Msk (0x01UL << LCD_PAL248_I0_Pos) /*!< LCD PAL248: I0 Mask */ -#define LCD_PAL248_R14_0_Pos 16 /*!< LCD PAL248: R14_0 Position */ -#define LCD_PAL248_R14_0_Msk (0x1fUL << LCD_PAL248_R14_0_Pos) /*!< LCD PAL248: R14_0 Mask */ -#define LCD_PAL248_G14_0_Pos 21 /*!< LCD PAL248: G14_0 Position */ -#define LCD_PAL248_G14_0_Msk (0x1fUL << LCD_PAL248_G14_0_Pos) /*!< LCD PAL248: G14_0 Mask */ -#define LCD_PAL248_B14_0_Pos 26 /*!< LCD PAL248: B14_0 Position */ -#define LCD_PAL248_B14_0_Msk (0x1fUL << LCD_PAL248_B14_0_Pos) /*!< LCD PAL248: B14_0 Mask */ -#define LCD_PAL248_I1_Pos 31 /*!< LCD PAL248: I1 Position */ -#define LCD_PAL248_I1_Msk (0x01UL << LCD_PAL248_I1_Pos) /*!< LCD PAL248: I1 Mask */ - -// --------------------------------------- LCD_PAL249 ------------------------------------------- -#define LCD_PAL249_R04_0_Pos 0 /*!< LCD PAL249: R04_0 Position */ -#define LCD_PAL249_R04_0_Msk (0x1fUL << LCD_PAL249_R04_0_Pos) /*!< LCD PAL249: R04_0 Mask */ -#define LCD_PAL249_G04_0_Pos 5 /*!< LCD PAL249: G04_0 Position */ -#define LCD_PAL249_G04_0_Msk (0x1fUL << LCD_PAL249_G04_0_Pos) /*!< LCD PAL249: G04_0 Mask */ -#define LCD_PAL249_B04_0_Pos 10 /*!< LCD PAL249: B04_0 Position */ -#define LCD_PAL249_B04_0_Msk (0x1fUL << LCD_PAL249_B04_0_Pos) /*!< LCD PAL249: B04_0 Mask */ -#define LCD_PAL249_I0_Pos 15 /*!< LCD PAL249: I0 Position */ -#define LCD_PAL249_I0_Msk (0x01UL << LCD_PAL249_I0_Pos) /*!< LCD PAL249: I0 Mask */ -#define LCD_PAL249_R14_0_Pos 16 /*!< LCD PAL249: R14_0 Position */ -#define LCD_PAL249_R14_0_Msk (0x1fUL << LCD_PAL249_R14_0_Pos) /*!< LCD PAL249: R14_0 Mask */ -#define LCD_PAL249_G14_0_Pos 21 /*!< LCD PAL249: G14_0 Position */ -#define LCD_PAL249_G14_0_Msk (0x1fUL << LCD_PAL249_G14_0_Pos) /*!< LCD PAL249: G14_0 Mask */ -#define LCD_PAL249_B14_0_Pos 26 /*!< LCD PAL249: B14_0 Position */ -#define LCD_PAL249_B14_0_Msk (0x1fUL << LCD_PAL249_B14_0_Pos) /*!< LCD PAL249: B14_0 Mask */ -#define LCD_PAL249_I1_Pos 31 /*!< LCD PAL249: I1 Position */ -#define LCD_PAL249_I1_Msk (0x01UL << LCD_PAL249_I1_Pos) /*!< LCD PAL249: I1 Mask */ - -// --------------------------------------- LCD_PAL250 ------------------------------------------- -#define LCD_PAL250_R04_0_Pos 0 /*!< LCD PAL250: R04_0 Position */ -#define LCD_PAL250_R04_0_Msk (0x1fUL << LCD_PAL250_R04_0_Pos) /*!< LCD PAL250: R04_0 Mask */ -#define LCD_PAL250_G04_0_Pos 5 /*!< LCD PAL250: G04_0 Position */ -#define LCD_PAL250_G04_0_Msk (0x1fUL << LCD_PAL250_G04_0_Pos) /*!< LCD PAL250: G04_0 Mask */ -#define LCD_PAL250_B04_0_Pos 10 /*!< LCD PAL250: B04_0 Position */ -#define LCD_PAL250_B04_0_Msk (0x1fUL << LCD_PAL250_B04_0_Pos) /*!< LCD PAL250: B04_0 Mask */ -#define LCD_PAL250_I0_Pos 15 /*!< LCD PAL250: I0 Position */ -#define LCD_PAL250_I0_Msk (0x01UL << LCD_PAL250_I0_Pos) /*!< LCD PAL250: I0 Mask */ -#define LCD_PAL250_R14_0_Pos 16 /*!< LCD PAL250: R14_0 Position */ -#define LCD_PAL250_R14_0_Msk (0x1fUL << LCD_PAL250_R14_0_Pos) /*!< LCD PAL250: R14_0 Mask */ -#define LCD_PAL250_G14_0_Pos 21 /*!< LCD PAL250: G14_0 Position */ -#define LCD_PAL250_G14_0_Msk (0x1fUL << LCD_PAL250_G14_0_Pos) /*!< LCD PAL250: G14_0 Mask */ -#define LCD_PAL250_B14_0_Pos 26 /*!< LCD PAL250: B14_0 Position */ -#define LCD_PAL250_B14_0_Msk (0x1fUL << LCD_PAL250_B14_0_Pos) /*!< LCD PAL250: B14_0 Mask */ -#define LCD_PAL250_I1_Pos 31 /*!< LCD PAL250: I1 Position */ -#define LCD_PAL250_I1_Msk (0x01UL << LCD_PAL250_I1_Pos) /*!< LCD PAL250: I1 Mask */ - -// --------------------------------------- LCD_PAL251 ------------------------------------------- -#define LCD_PAL251_R04_0_Pos 0 /*!< LCD PAL251: R04_0 Position */ -#define LCD_PAL251_R04_0_Msk (0x1fUL << LCD_PAL251_R04_0_Pos) /*!< LCD PAL251: R04_0 Mask */ -#define LCD_PAL251_G04_0_Pos 5 /*!< LCD PAL251: G04_0 Position */ -#define LCD_PAL251_G04_0_Msk (0x1fUL << LCD_PAL251_G04_0_Pos) /*!< LCD PAL251: G04_0 Mask */ -#define LCD_PAL251_B04_0_Pos 10 /*!< LCD PAL251: B04_0 Position */ -#define LCD_PAL251_B04_0_Msk (0x1fUL << LCD_PAL251_B04_0_Pos) /*!< LCD PAL251: B04_0 Mask */ -#define LCD_PAL251_I0_Pos 15 /*!< LCD PAL251: I0 Position */ -#define LCD_PAL251_I0_Msk (0x01UL << LCD_PAL251_I0_Pos) /*!< LCD PAL251: I0 Mask */ -#define LCD_PAL251_R14_0_Pos 16 /*!< LCD PAL251: R14_0 Position */ -#define LCD_PAL251_R14_0_Msk (0x1fUL << LCD_PAL251_R14_0_Pos) /*!< LCD PAL251: R14_0 Mask */ -#define LCD_PAL251_G14_0_Pos 21 /*!< LCD PAL251: G14_0 Position */ -#define LCD_PAL251_G14_0_Msk (0x1fUL << LCD_PAL251_G14_0_Pos) /*!< LCD PAL251: G14_0 Mask */ -#define LCD_PAL251_B14_0_Pos 26 /*!< LCD PAL251: B14_0 Position */ -#define LCD_PAL251_B14_0_Msk (0x1fUL << LCD_PAL251_B14_0_Pos) /*!< LCD PAL251: B14_0 Mask */ -#define LCD_PAL251_I1_Pos 31 /*!< LCD PAL251: I1 Position */ -#define LCD_PAL251_I1_Msk (0x01UL << LCD_PAL251_I1_Pos) /*!< LCD PAL251: I1 Mask */ - -// --------------------------------------- LCD_PAL252 ------------------------------------------- -#define LCD_PAL252_R04_0_Pos 0 /*!< LCD PAL252: R04_0 Position */ -#define LCD_PAL252_R04_0_Msk (0x1fUL << LCD_PAL252_R04_0_Pos) /*!< LCD PAL252: R04_0 Mask */ -#define LCD_PAL252_G04_0_Pos 5 /*!< LCD PAL252: G04_0 Position */ -#define LCD_PAL252_G04_0_Msk (0x1fUL << LCD_PAL252_G04_0_Pos) /*!< LCD PAL252: G04_0 Mask */ -#define LCD_PAL252_B04_0_Pos 10 /*!< LCD PAL252: B04_0 Position */ -#define LCD_PAL252_B04_0_Msk (0x1fUL << LCD_PAL252_B04_0_Pos) /*!< LCD PAL252: B04_0 Mask */ -#define LCD_PAL252_I0_Pos 15 /*!< LCD PAL252: I0 Position */ -#define LCD_PAL252_I0_Msk (0x01UL << LCD_PAL252_I0_Pos) /*!< LCD PAL252: I0 Mask */ -#define LCD_PAL252_R14_0_Pos 16 /*!< LCD PAL252: R14_0 Position */ -#define LCD_PAL252_R14_0_Msk (0x1fUL << LCD_PAL252_R14_0_Pos) /*!< LCD PAL252: R14_0 Mask */ -#define LCD_PAL252_G14_0_Pos 21 /*!< LCD PAL252: G14_0 Position */ -#define LCD_PAL252_G14_0_Msk (0x1fUL << LCD_PAL252_G14_0_Pos) /*!< LCD PAL252: G14_0 Mask */ -#define LCD_PAL252_B14_0_Pos 26 /*!< LCD PAL252: B14_0 Position */ -#define LCD_PAL252_B14_0_Msk (0x1fUL << LCD_PAL252_B14_0_Pos) /*!< LCD PAL252: B14_0 Mask */ -#define LCD_PAL252_I1_Pos 31 /*!< LCD PAL252: I1 Position */ -#define LCD_PAL252_I1_Msk (0x01UL << LCD_PAL252_I1_Pos) /*!< LCD PAL252: I1 Mask */ - -// --------------------------------------- LCD_PAL253 ------------------------------------------- -#define LCD_PAL253_R04_0_Pos 0 /*!< LCD PAL253: R04_0 Position */ -#define LCD_PAL253_R04_0_Msk (0x1fUL << LCD_PAL253_R04_0_Pos) /*!< LCD PAL253: R04_0 Mask */ -#define LCD_PAL253_G04_0_Pos 5 /*!< LCD PAL253: G04_0 Position */ -#define LCD_PAL253_G04_0_Msk (0x1fUL << LCD_PAL253_G04_0_Pos) /*!< LCD PAL253: G04_0 Mask */ -#define LCD_PAL253_B04_0_Pos 10 /*!< LCD PAL253: B04_0 Position */ -#define LCD_PAL253_B04_0_Msk (0x1fUL << LCD_PAL253_B04_0_Pos) /*!< LCD PAL253: B04_0 Mask */ -#define LCD_PAL253_I0_Pos 15 /*!< LCD PAL253: I0 Position */ -#define LCD_PAL253_I0_Msk (0x01UL << LCD_PAL253_I0_Pos) /*!< LCD PAL253: I0 Mask */ -#define LCD_PAL253_R14_0_Pos 16 /*!< LCD PAL253: R14_0 Position */ -#define LCD_PAL253_R14_0_Msk (0x1fUL << LCD_PAL253_R14_0_Pos) /*!< LCD PAL253: R14_0 Mask */ -#define LCD_PAL253_G14_0_Pos 21 /*!< LCD PAL253: G14_0 Position */ -#define LCD_PAL253_G14_0_Msk (0x1fUL << LCD_PAL253_G14_0_Pos) /*!< LCD PAL253: G14_0 Mask */ -#define LCD_PAL253_B14_0_Pos 26 /*!< LCD PAL253: B14_0 Position */ -#define LCD_PAL253_B14_0_Msk (0x1fUL << LCD_PAL253_B14_0_Pos) /*!< LCD PAL253: B14_0 Mask */ -#define LCD_PAL253_I1_Pos 31 /*!< LCD PAL253: I1 Position */ -#define LCD_PAL253_I1_Msk (0x01UL << LCD_PAL253_I1_Pos) /*!< LCD PAL253: I1 Mask */ - -// --------------------------------------- LCD_PAL254 ------------------------------------------- -#define LCD_PAL254_R04_0_Pos 0 /*!< LCD PAL254: R04_0 Position */ -#define LCD_PAL254_R04_0_Msk (0x1fUL << LCD_PAL254_R04_0_Pos) /*!< LCD PAL254: R04_0 Mask */ -#define LCD_PAL254_G04_0_Pos 5 /*!< LCD PAL254: G04_0 Position */ -#define LCD_PAL254_G04_0_Msk (0x1fUL << LCD_PAL254_G04_0_Pos) /*!< LCD PAL254: G04_0 Mask */ -#define LCD_PAL254_B04_0_Pos 10 /*!< LCD PAL254: B04_0 Position */ -#define LCD_PAL254_B04_0_Msk (0x1fUL << LCD_PAL254_B04_0_Pos) /*!< LCD PAL254: B04_0 Mask */ -#define LCD_PAL254_I0_Pos 15 /*!< LCD PAL254: I0 Position */ -#define LCD_PAL254_I0_Msk (0x01UL << LCD_PAL254_I0_Pos) /*!< LCD PAL254: I0 Mask */ -#define LCD_PAL254_R14_0_Pos 16 /*!< LCD PAL254: R14_0 Position */ -#define LCD_PAL254_R14_0_Msk (0x1fUL << LCD_PAL254_R14_0_Pos) /*!< LCD PAL254: R14_0 Mask */ -#define LCD_PAL254_G14_0_Pos 21 /*!< LCD PAL254: G14_0 Position */ -#define LCD_PAL254_G14_0_Msk (0x1fUL << LCD_PAL254_G14_0_Pos) /*!< LCD PAL254: G14_0 Mask */ -#define LCD_PAL254_B14_0_Pos 26 /*!< LCD PAL254: B14_0 Position */ -#define LCD_PAL254_B14_0_Msk (0x1fUL << LCD_PAL254_B14_0_Pos) /*!< LCD PAL254: B14_0 Mask */ -#define LCD_PAL254_I1_Pos 31 /*!< LCD PAL254: I1 Position */ -#define LCD_PAL254_I1_Msk (0x01UL << LCD_PAL254_I1_Pos) /*!< LCD PAL254: I1 Mask */ - -// --------------------------------------- LCD_PAL255 ------------------------------------------- -#define LCD_PAL255_R04_0_Pos 0 /*!< LCD PAL255: R04_0 Position */ -#define LCD_PAL255_R04_0_Msk (0x1fUL << LCD_PAL255_R04_0_Pos) /*!< LCD PAL255: R04_0 Mask */ -#define LCD_PAL255_G04_0_Pos 5 /*!< LCD PAL255: G04_0 Position */ -#define LCD_PAL255_G04_0_Msk (0x1fUL << LCD_PAL255_G04_0_Pos) /*!< LCD PAL255: G04_0 Mask */ -#define LCD_PAL255_B04_0_Pos 10 /*!< LCD PAL255: B04_0 Position */ -#define LCD_PAL255_B04_0_Msk (0x1fUL << LCD_PAL255_B04_0_Pos) /*!< LCD PAL255: B04_0 Mask */ -#define LCD_PAL255_I0_Pos 15 /*!< LCD PAL255: I0 Position */ -#define LCD_PAL255_I0_Msk (0x01UL << LCD_PAL255_I0_Pos) /*!< LCD PAL255: I0 Mask */ -#define LCD_PAL255_R14_0_Pos 16 /*!< LCD PAL255: R14_0 Position */ -#define LCD_PAL255_R14_0_Msk (0x1fUL << LCD_PAL255_R14_0_Pos) /*!< LCD PAL255: R14_0 Mask */ -#define LCD_PAL255_G14_0_Pos 21 /*!< LCD PAL255: G14_0 Position */ -#define LCD_PAL255_G14_0_Msk (0x1fUL << LCD_PAL255_G14_0_Pos) /*!< LCD PAL255: G14_0 Mask */ -#define LCD_PAL255_B14_0_Pos 26 /*!< LCD PAL255: B14_0 Position */ -#define LCD_PAL255_B14_0_Msk (0x1fUL << LCD_PAL255_B14_0_Pos) /*!< LCD PAL255: B14_0 Mask */ -#define LCD_PAL255_I1_Pos 31 /*!< LCD PAL255: I1 Position */ -#define LCD_PAL255_I1_Msk (0x01UL << LCD_PAL255_I1_Pos) /*!< LCD PAL255: I1 Mask */ - -// -------------------------------------- LCD_CRSR_IMG0 ----------------------------------------- -#define LCD_CRSR_IMG0_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG0: CRSR_IMG Position */ -#define LCD_CRSR_IMG0_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG0_CRSR_IMG_Pos) /*!< LCD CRSR_IMG0: CRSR_IMG Mask */ - -// -------------------------------------- LCD_CRSR_IMG1 ----------------------------------------- -#define LCD_CRSR_IMG1_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG1: CRSR_IMG Position */ -#define LCD_CRSR_IMG1_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG1_CRSR_IMG_Pos) /*!< LCD CRSR_IMG1: CRSR_IMG Mask */ - -// -------------------------------------- LCD_CRSR_IMG2 ----------------------------------------- -#define LCD_CRSR_IMG2_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG2: CRSR_IMG Position */ -#define LCD_CRSR_IMG2_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG2_CRSR_IMG_Pos) /*!< LCD CRSR_IMG2: CRSR_IMG Mask */ - -// -------------------------------------- LCD_CRSR_IMG3 ----------------------------------------- -#define LCD_CRSR_IMG3_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG3: CRSR_IMG Position */ -#define LCD_CRSR_IMG3_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG3_CRSR_IMG_Pos) /*!< LCD CRSR_IMG3: CRSR_IMG Mask */ - -// -------------------------------------- LCD_CRSR_IMG4 ----------------------------------------- -#define LCD_CRSR_IMG4_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG4: CRSR_IMG Position */ -#define LCD_CRSR_IMG4_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG4_CRSR_IMG_Pos) /*!< LCD CRSR_IMG4: CRSR_IMG Mask */ - -// -------------------------------------- LCD_CRSR_IMG5 ----------------------------------------- -#define LCD_CRSR_IMG5_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG5: CRSR_IMG Position */ -#define LCD_CRSR_IMG5_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG5_CRSR_IMG_Pos) /*!< LCD CRSR_IMG5: CRSR_IMG Mask */ - -// -------------------------------------- LCD_CRSR_IMG6 ----------------------------------------- -#define LCD_CRSR_IMG6_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG6: CRSR_IMG Position */ -#define LCD_CRSR_IMG6_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG6_CRSR_IMG_Pos) /*!< LCD CRSR_IMG6: CRSR_IMG Mask */ - -// -------------------------------------- LCD_CRSR_IMG7 ----------------------------------------- -#define LCD_CRSR_IMG7_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG7: CRSR_IMG Position */ -#define LCD_CRSR_IMG7_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG7_CRSR_IMG_Pos) /*!< LCD CRSR_IMG7: CRSR_IMG Mask */ - -// -------------------------------------- LCD_CRSR_IMG8 ----------------------------------------- -#define LCD_CRSR_IMG8_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG8: CRSR_IMG Position */ -#define LCD_CRSR_IMG8_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG8_CRSR_IMG_Pos) /*!< LCD CRSR_IMG8: CRSR_IMG Mask */ - -// -------------------------------------- LCD_CRSR_IMG9 ----------------------------------------- -#define LCD_CRSR_IMG9_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG9: CRSR_IMG Position */ -#define LCD_CRSR_IMG9_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG9_CRSR_IMG_Pos) /*!< LCD CRSR_IMG9: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG10 ----------------------------------------- -#define LCD_CRSR_IMG10_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG10: CRSR_IMG Position */ -#define LCD_CRSR_IMG10_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG10_CRSR_IMG_Pos) /*!< LCD CRSR_IMG10: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG11 ----------------------------------------- -#define LCD_CRSR_IMG11_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG11: CRSR_IMG Position */ -#define LCD_CRSR_IMG11_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG11_CRSR_IMG_Pos) /*!< LCD CRSR_IMG11: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG12 ----------------------------------------- -#define LCD_CRSR_IMG12_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG12: CRSR_IMG Position */ -#define LCD_CRSR_IMG12_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG12_CRSR_IMG_Pos) /*!< LCD CRSR_IMG12: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG13 ----------------------------------------- -#define LCD_CRSR_IMG13_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG13: CRSR_IMG Position */ -#define LCD_CRSR_IMG13_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG13_CRSR_IMG_Pos) /*!< LCD CRSR_IMG13: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG14 ----------------------------------------- -#define LCD_CRSR_IMG14_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG14: CRSR_IMG Position */ -#define LCD_CRSR_IMG14_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG14_CRSR_IMG_Pos) /*!< LCD CRSR_IMG14: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG15 ----------------------------------------- -#define LCD_CRSR_IMG15_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG15: CRSR_IMG Position */ -#define LCD_CRSR_IMG15_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG15_CRSR_IMG_Pos) /*!< LCD CRSR_IMG15: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG16 ----------------------------------------- -#define LCD_CRSR_IMG16_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG16: CRSR_IMG Position */ -#define LCD_CRSR_IMG16_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG16_CRSR_IMG_Pos) /*!< LCD CRSR_IMG16: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG17 ----------------------------------------- -#define LCD_CRSR_IMG17_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG17: CRSR_IMG Position */ -#define LCD_CRSR_IMG17_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG17_CRSR_IMG_Pos) /*!< LCD CRSR_IMG17: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG18 ----------------------------------------- -#define LCD_CRSR_IMG18_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG18: CRSR_IMG Position */ -#define LCD_CRSR_IMG18_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG18_CRSR_IMG_Pos) /*!< LCD CRSR_IMG18: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG19 ----------------------------------------- -#define LCD_CRSR_IMG19_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG19: CRSR_IMG Position */ -#define LCD_CRSR_IMG19_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG19_CRSR_IMG_Pos) /*!< LCD CRSR_IMG19: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG20 ----------------------------------------- -#define LCD_CRSR_IMG20_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG20: CRSR_IMG Position */ -#define LCD_CRSR_IMG20_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG20_CRSR_IMG_Pos) /*!< LCD CRSR_IMG20: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG21 ----------------------------------------- -#define LCD_CRSR_IMG21_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG21: CRSR_IMG Position */ -#define LCD_CRSR_IMG21_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG21_CRSR_IMG_Pos) /*!< LCD CRSR_IMG21: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG22 ----------------------------------------- -#define LCD_CRSR_IMG22_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG22: CRSR_IMG Position */ -#define LCD_CRSR_IMG22_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG22_CRSR_IMG_Pos) /*!< LCD CRSR_IMG22: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG23 ----------------------------------------- -#define LCD_CRSR_IMG23_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG23: CRSR_IMG Position */ -#define LCD_CRSR_IMG23_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG23_CRSR_IMG_Pos) /*!< LCD CRSR_IMG23: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG24 ----------------------------------------- -#define LCD_CRSR_IMG24_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG24: CRSR_IMG Position */ -#define LCD_CRSR_IMG24_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG24_CRSR_IMG_Pos) /*!< LCD CRSR_IMG24: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG25 ----------------------------------------- -#define LCD_CRSR_IMG25_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG25: CRSR_IMG Position */ -#define LCD_CRSR_IMG25_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG25_CRSR_IMG_Pos) /*!< LCD CRSR_IMG25: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG26 ----------------------------------------- -#define LCD_CRSR_IMG26_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG26: CRSR_IMG Position */ -#define LCD_CRSR_IMG26_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG26_CRSR_IMG_Pos) /*!< LCD CRSR_IMG26: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG27 ----------------------------------------- -#define LCD_CRSR_IMG27_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG27: CRSR_IMG Position */ -#define LCD_CRSR_IMG27_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG27_CRSR_IMG_Pos) /*!< LCD CRSR_IMG27: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG28 ----------------------------------------- -#define LCD_CRSR_IMG28_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG28: CRSR_IMG Position */ -#define LCD_CRSR_IMG28_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG28_CRSR_IMG_Pos) /*!< LCD CRSR_IMG28: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG29 ----------------------------------------- -#define LCD_CRSR_IMG29_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG29: CRSR_IMG Position */ -#define LCD_CRSR_IMG29_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG29_CRSR_IMG_Pos) /*!< LCD CRSR_IMG29: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG30 ----------------------------------------- -#define LCD_CRSR_IMG30_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG30: CRSR_IMG Position */ -#define LCD_CRSR_IMG30_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG30_CRSR_IMG_Pos) /*!< LCD CRSR_IMG30: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG31 ----------------------------------------- -#define LCD_CRSR_IMG31_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG31: CRSR_IMG Position */ -#define LCD_CRSR_IMG31_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG31_CRSR_IMG_Pos) /*!< LCD CRSR_IMG31: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG32 ----------------------------------------- -#define LCD_CRSR_IMG32_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG32: CRSR_IMG Position */ -#define LCD_CRSR_IMG32_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG32_CRSR_IMG_Pos) /*!< LCD CRSR_IMG32: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG33 ----------------------------------------- -#define LCD_CRSR_IMG33_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG33: CRSR_IMG Position */ -#define LCD_CRSR_IMG33_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG33_CRSR_IMG_Pos) /*!< LCD CRSR_IMG33: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG34 ----------------------------------------- -#define LCD_CRSR_IMG34_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG34: CRSR_IMG Position */ -#define LCD_CRSR_IMG34_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG34_CRSR_IMG_Pos) /*!< LCD CRSR_IMG34: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG35 ----------------------------------------- -#define LCD_CRSR_IMG35_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG35: CRSR_IMG Position */ -#define LCD_CRSR_IMG35_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG35_CRSR_IMG_Pos) /*!< LCD CRSR_IMG35: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG36 ----------------------------------------- -#define LCD_CRSR_IMG36_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG36: CRSR_IMG Position */ -#define LCD_CRSR_IMG36_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG36_CRSR_IMG_Pos) /*!< LCD CRSR_IMG36: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG37 ----------------------------------------- -#define LCD_CRSR_IMG37_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG37: CRSR_IMG Position */ -#define LCD_CRSR_IMG37_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG37_CRSR_IMG_Pos) /*!< LCD CRSR_IMG37: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG38 ----------------------------------------- -#define LCD_CRSR_IMG38_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG38: CRSR_IMG Position */ -#define LCD_CRSR_IMG38_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG38_CRSR_IMG_Pos) /*!< LCD CRSR_IMG38: CRSR_IMG Mask */ +/* ================================================================================ */ +/* ================ struct 'SCT' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- SCT_CONFIG --------------------------------- */ +#define SCT_CONFIG_UNIFY_Pos 0 /*!< SCT CONFIG: UNIFY Position */ +#define SCT_CONFIG_UNIFY_Msk (0x01UL << SCT_CONFIG_UNIFY_Pos) /*!< SCT CONFIG: UNIFY Mask */ +#define SCT_CONFIG_CLKMODE_Pos 1 /*!< SCT CONFIG: CLKMODE Position */ +#define SCT_CONFIG_CLKMODE_Msk (0x03UL << SCT_CONFIG_CLKMODE_Pos) /*!< SCT CONFIG: CLKMODE Mask */ +#define SCT_CONFIG_CKSEL_Pos 3 /*!< SCT CONFIG: CKSEL Position */ +#define SCT_CONFIG_CKSEL_Msk (0x0fUL << SCT_CONFIG_CKSEL_Pos) /*!< SCT CONFIG: CKSEL Mask */ +#define SCT_CONFIG_NORELAOD_L_Pos 7 /*!< SCT CONFIG: NORELAOD_L Position */ +#define SCT_CONFIG_NORELAOD_L_Msk (0x01UL << SCT_CONFIG_NORELAOD_L_Pos) /*!< SCT CONFIG: NORELAOD_L Mask */ +#define SCT_CONFIG_NORELOAD_H_Pos 8 /*!< SCT CONFIG: NORELOAD_H Position */ +#define SCT_CONFIG_NORELOAD_H_Msk (0x01UL << SCT_CONFIG_NORELOAD_H_Pos) /*!< SCT CONFIG: NORELOAD_H Mask */ +#define SCT_CONFIG_INSYNC_Pos 9 /*!< SCT CONFIG: INSYNC Position */ +#define SCT_CONFIG_INSYNC_Msk (0x000000ffUL << SCT_CONFIG_INSYNC_Pos) /*!< SCT CONFIG: INSYNC Mask */ +#define SCT_CONFIG_AUTOLIMIT_L_Pos 17 /*!< SCT CONFIG: AUTOLIMIT_L Position */ +#define SCT_CONFIG_AUTOLIMIT_L_Msk (0x01UL << SCT_CONFIG_AUTOLIMIT_L_Pos) /*!< SCT CONFIG: AUTOLIMIT_L Mask */ +#define SCT_CONFIG_AUTOLIMIT_H_Pos 18 /*!< SCT CONFIG: AUTOLIMIT_H Position */ +#define SCT_CONFIG_AUTOLIMIT_H_Msk (0x01UL << SCT_CONFIG_AUTOLIMIT_H_Pos) /*!< SCT CONFIG: AUTOLIMIT_H Mask */ + +/* ---------------------------------- SCT_CTRL ---------------------------------- */ +#define SCT_CTRL_DOWN_L_Pos 0 /*!< SCT CTRL: DOWN_L Position */ +#define SCT_CTRL_DOWN_L_Msk (0x01UL << SCT_CTRL_DOWN_L_Pos) /*!< SCT CTRL: DOWN_L Mask */ +#define SCT_CTRL_STOP_L_Pos 1 /*!< SCT CTRL: STOP_L Position */ +#define SCT_CTRL_STOP_L_Msk (0x01UL << SCT_CTRL_STOP_L_Pos) /*!< SCT CTRL: STOP_L Mask */ +#define SCT_CTRL_HALT_L_Pos 2 /*!< SCT CTRL: HALT_L Position */ +#define SCT_CTRL_HALT_L_Msk (0x01UL << SCT_CTRL_HALT_L_Pos) /*!< SCT CTRL: HALT_L Mask */ +#define SCT_CTRL_CLRCTR_L_Pos 3 /*!< SCT CTRL: CLRCTR_L Position */ +#define SCT_CTRL_CLRCTR_L_Msk (0x01UL << SCT_CTRL_CLRCTR_L_Pos) /*!< SCT CTRL: CLRCTR_L Mask */ +#define SCT_CTRL_BIDIR_L_Pos 4 /*!< SCT CTRL: BIDIR_L Position */ +#define SCT_CTRL_BIDIR_L_Msk (0x01UL << SCT_CTRL_BIDIR_L_Pos) /*!< SCT CTRL: BIDIR_L Mask */ +#define SCT_CTRL_PRE_L_Pos 5 /*!< SCT CTRL: PRE_L Position */ +#define SCT_CTRL_PRE_L_Msk (0x000000ffUL << SCT_CTRL_PRE_L_Pos) /*!< SCT CTRL: PRE_L Mask */ +#define SCT_CTRL_DOWN_H_Pos 16 /*!< SCT CTRL: DOWN_H Position */ +#define SCT_CTRL_DOWN_H_Msk (0x01UL << SCT_CTRL_DOWN_H_Pos) /*!< SCT CTRL: DOWN_H Mask */ +#define SCT_CTRL_STOP_H_Pos 17 /*!< SCT CTRL: STOP_H Position */ +#define SCT_CTRL_STOP_H_Msk (0x01UL << SCT_CTRL_STOP_H_Pos) /*!< SCT CTRL: STOP_H Mask */ +#define SCT_CTRL_HALT_H_Pos 18 /*!< SCT CTRL: HALT_H Position */ +#define SCT_CTRL_HALT_H_Msk (0x01UL << SCT_CTRL_HALT_H_Pos) /*!< SCT CTRL: HALT_H Mask */ +#define SCT_CTRL_CLRCTR_H_Pos 19 /*!< SCT CTRL: CLRCTR_H Position */ +#define SCT_CTRL_CLRCTR_H_Msk (0x01UL << SCT_CTRL_CLRCTR_H_Pos) /*!< SCT CTRL: CLRCTR_H Mask */ +#define SCT_CTRL_BIDIR_H_Pos 20 /*!< SCT CTRL: BIDIR_H Position */ +#define SCT_CTRL_BIDIR_H_Msk (0x01UL << SCT_CTRL_BIDIR_H_Pos) /*!< SCT CTRL: BIDIR_H Mask */ +#define SCT_CTRL_PRE_H_Pos 21 /*!< SCT CTRL: PRE_H Position */ +#define SCT_CTRL_PRE_H_Msk (0x000000ffUL << SCT_CTRL_PRE_H_Pos) /*!< SCT CTRL: PRE_H Mask */ + +/* ---------------------------------- SCT_LIMIT --------------------------------- */ +#define SCT_LIMIT_LIMMSK_L_Pos 0 /*!< SCT LIMIT: LIMMSK_L Position */ +#define SCT_LIMIT_LIMMSK_L_Msk (0x0000ffffUL << SCT_LIMIT_LIMMSK_L_Pos) /*!< SCT LIMIT: LIMMSK_L Mask */ +#define SCT_LIMIT_LIMMSK_H_Pos 16 /*!< SCT LIMIT: LIMMSK_H Position */ +#define SCT_LIMIT_LIMMSK_H_Msk (0x0000ffffUL << SCT_LIMIT_LIMMSK_H_Pos) /*!< SCT LIMIT: LIMMSK_H Mask */ + +/* ---------------------------------- SCT_HALT ---------------------------------- */ +#define SCT_HALT_HALTMSK_L_Pos 0 /*!< SCT HALT: HALTMSK_L Position */ +#define SCT_HALT_HALTMSK_L_Msk (0x0000ffffUL << SCT_HALT_HALTMSK_L_Pos) /*!< SCT HALT: HALTMSK_L Mask */ +#define SCT_HALT_HALTMSK_H_Pos 16 /*!< SCT HALT: HALTMSK_H Position */ +#define SCT_HALT_HALTMSK_H_Msk (0x0000ffffUL << SCT_HALT_HALTMSK_H_Pos) /*!< SCT HALT: HALTMSK_H Mask */ + +/* ---------------------------------- SCT_STOP ---------------------------------- */ +#define SCT_STOP_STOPMSK_L_Pos 0 /*!< SCT STOP: STOPMSK_L Position */ +#define SCT_STOP_STOPMSK_L_Msk (0x0000ffffUL << SCT_STOP_STOPMSK_L_Pos) /*!< SCT STOP: STOPMSK_L Mask */ +#define SCT_STOP_STOPMSK_H_Pos 16 /*!< SCT STOP: STOPMSK_H Position */ +#define SCT_STOP_STOPMSK_H_Msk (0x0000ffffUL << SCT_STOP_STOPMSK_H_Pos) /*!< SCT STOP: STOPMSK_H Mask */ + +/* ---------------------------------- SCT_START --------------------------------- */ +#define SCT_START_STARTMSK_L_Pos 0 /*!< SCT START: STARTMSK_L Position */ +#define SCT_START_STARTMSK_L_Msk (0x0000ffffUL << SCT_START_STARTMSK_L_Pos) /*!< SCT START: STARTMSK_L Mask */ +#define SCT_START_STARTMSK_H_Pos 16 /*!< SCT START: STARTMSK_H Position */ +#define SCT_START_STARTMSK_H_Msk (0x0000ffffUL << SCT_START_STARTMSK_H_Pos) /*!< SCT START: STARTMSK_H Mask */ + +/* --------------------------------- SCT_DITHER --------------------------------- */ +#define SCT_DITHER_DITHMSK_L_Pos 0 /*!< SCT DITHER: DITHMSK_L Position */ +#define SCT_DITHER_DITHMSK_L_Msk (0x0000ffffUL << SCT_DITHER_DITHMSK_L_Pos) /*!< SCT DITHER: DITHMSK_L Mask */ +#define SCT_DITHER_DITHMSK_H_Pos 16 /*!< SCT DITHER: DITHMSK_H Position */ +#define SCT_DITHER_DITHMSK_H_Msk (0x0000ffffUL << SCT_DITHER_DITHMSK_H_Pos) /*!< SCT DITHER: DITHMSK_H Mask */ + +/* ---------------------------------- SCT_COUNT --------------------------------- */ +#define SCT_COUNT_CTR_L_Pos 0 /*!< SCT COUNT: CTR_L Position */ +#define SCT_COUNT_CTR_L_Msk (0x0000ffffUL << SCT_COUNT_CTR_L_Pos) /*!< SCT COUNT: CTR_L Mask */ +#define SCT_COUNT_CTR_H_Pos 16 /*!< SCT COUNT: CTR_H Position */ +#define SCT_COUNT_CTR_H_Msk (0x0000ffffUL << SCT_COUNT_CTR_H_Pos) /*!< SCT COUNT: CTR_H Mask */ + +/* ---------------------------------- SCT_STATE --------------------------------- */ +#define SCT_STATE_STATE_L_Pos 0 /*!< SCT STATE: STATE_L Position */ +#define SCT_STATE_STATE_L_Msk (0x1fUL << SCT_STATE_STATE_L_Pos) /*!< SCT STATE: STATE_L Mask */ +#define SCT_STATE_STATE_H_Pos 16 /*!< SCT STATE: STATE_H Position */ +#define SCT_STATE_STATE_H_Msk (0x1fUL << SCT_STATE_STATE_H_Pos) /*!< SCT STATE: STATE_H Mask */ + +/* ---------------------------------- SCT_INPUT --------------------------------- */ +#define SCT_INPUT_AIN0_Pos 0 /*!< SCT INPUT: AIN0 Position */ +#define SCT_INPUT_AIN0_Msk (0x01UL << SCT_INPUT_AIN0_Pos) /*!< SCT INPUT: AIN0 Mask */ +#define SCT_INPUT_AIN1_Pos 1 /*!< SCT INPUT: AIN1 Position */ +#define SCT_INPUT_AIN1_Msk (0x01UL << SCT_INPUT_AIN1_Pos) /*!< SCT INPUT: AIN1 Mask */ +#define SCT_INPUT_AIN2_Pos 2 /*!< SCT INPUT: AIN2 Position */ +#define SCT_INPUT_AIN2_Msk (0x01UL << SCT_INPUT_AIN2_Pos) /*!< SCT INPUT: AIN2 Mask */ +#define SCT_INPUT_AIN3_Pos 3 /*!< SCT INPUT: AIN3 Position */ +#define SCT_INPUT_AIN3_Msk (0x01UL << SCT_INPUT_AIN3_Pos) /*!< SCT INPUT: AIN3 Mask */ +#define SCT_INPUT_AIN4_Pos 4 /*!< SCT INPUT: AIN4 Position */ +#define SCT_INPUT_AIN4_Msk (0x01UL << SCT_INPUT_AIN4_Pos) /*!< SCT INPUT: AIN4 Mask */ +#define SCT_INPUT_AIN5_Pos 5 /*!< SCT INPUT: AIN5 Position */ +#define SCT_INPUT_AIN5_Msk (0x01UL << SCT_INPUT_AIN5_Pos) /*!< SCT INPUT: AIN5 Mask */ +#define SCT_INPUT_AIN6_Pos 6 /*!< SCT INPUT: AIN6 Position */ +#define SCT_INPUT_AIN6_Msk (0x01UL << SCT_INPUT_AIN6_Pos) /*!< SCT INPUT: AIN6 Mask */ +#define SCT_INPUT_AIN7_Pos 7 /*!< SCT INPUT: AIN7 Position */ +#define SCT_INPUT_AIN7_Msk (0x01UL << SCT_INPUT_AIN7_Pos) /*!< SCT INPUT: AIN7 Mask */ +#define SCT_INPUT_SIN0_Pos 16 /*!< SCT INPUT: SIN0 Position */ +#define SCT_INPUT_SIN0_Msk (0x01UL << SCT_INPUT_SIN0_Pos) /*!< SCT INPUT: SIN0 Mask */ +#define SCT_INPUT_SIN1_Pos 17 /*!< SCT INPUT: SIN1 Position */ +#define SCT_INPUT_SIN1_Msk (0x01UL << SCT_INPUT_SIN1_Pos) /*!< SCT INPUT: SIN1 Mask */ +#define SCT_INPUT_SIN2_Pos 18 /*!< SCT INPUT: SIN2 Position */ +#define SCT_INPUT_SIN2_Msk (0x01UL << SCT_INPUT_SIN2_Pos) /*!< SCT INPUT: SIN2 Mask */ +#define SCT_INPUT_SIN3_Pos 19 /*!< SCT INPUT: SIN3 Position */ +#define SCT_INPUT_SIN3_Msk (0x01UL << SCT_INPUT_SIN3_Pos) /*!< SCT INPUT: SIN3 Mask */ +#define SCT_INPUT_SIN4_Pos 20 /*!< SCT INPUT: SIN4 Position */ +#define SCT_INPUT_SIN4_Msk (0x01UL << SCT_INPUT_SIN4_Pos) /*!< SCT INPUT: SIN4 Mask */ +#define SCT_INPUT_SIN5_Pos 21 /*!< SCT INPUT: SIN5 Position */ +#define SCT_INPUT_SIN5_Msk (0x01UL << SCT_INPUT_SIN5_Pos) /*!< SCT INPUT: SIN5 Mask */ +#define SCT_INPUT_SIN6_Pos 22 /*!< SCT INPUT: SIN6 Position */ +#define SCT_INPUT_SIN6_Msk (0x01UL << SCT_INPUT_SIN6_Pos) /*!< SCT INPUT: SIN6 Mask */ +#define SCT_INPUT_SIN7_Pos 23 /*!< SCT INPUT: SIN7 Position */ +#define SCT_INPUT_SIN7_Msk (0x01UL << SCT_INPUT_SIN7_Pos) /*!< SCT INPUT: SIN7 Mask */ + +/* --------------------------------- SCT_REGMODE -------------------------------- */ +#define SCT_REGMODE_REGMOD_L_Pos 0 /*!< SCT REGMODE: REGMOD_L Position */ +#define SCT_REGMODE_REGMOD_L_Msk (0x0000ffffUL << SCT_REGMODE_REGMOD_L_Pos) /*!< SCT REGMODE: REGMOD_L Mask */ +#define SCT_REGMODE_REGMOD_H_Pos 16 /*!< SCT REGMODE: REGMOD_H Position */ +#define SCT_REGMODE_REGMOD_H_Msk (0x0000ffffUL << SCT_REGMODE_REGMOD_H_Pos) /*!< SCT REGMODE: REGMOD_H Mask */ + +/* --------------------------------- SCT_OUTPUT --------------------------------- */ +#define SCT_OUTPUT_OUT_Pos 0 /*!< SCT OUTPUT: OUT Position */ +#define SCT_OUTPUT_OUT_Msk (0x0000ffffUL << SCT_OUTPUT_OUT_Pos) /*!< SCT OUTPUT: OUT Mask */ + +/* ------------------------------ SCT_OUTPUTDIRCTRL ----------------------------- */ +#define SCT_OUTPUTDIRCTRL_SETCLR0_Pos 0 /*!< SCT OUTPUTDIRCTRL: SETCLR0 Position */ +#define SCT_OUTPUTDIRCTRL_SETCLR0_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR0_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR0 Mask */ +#define SCT_OUTPUTDIRCTRL_SETCLR1_Pos 2 /*!< SCT OUTPUTDIRCTRL: SETCLR1 Position */ +#define SCT_OUTPUTDIRCTRL_SETCLR1_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR1_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR1 Mask */ +#define SCT_OUTPUTDIRCTRL_SETCLR2_Pos 4 /*!< SCT OUTPUTDIRCTRL: SETCLR2 Position */ +#define SCT_OUTPUTDIRCTRL_SETCLR2_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR2_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR2 Mask */ +#define SCT_OUTPUTDIRCTRL_SETCLR3_Pos 6 /*!< SCT OUTPUTDIRCTRL: SETCLR3 Position */ +#define SCT_OUTPUTDIRCTRL_SETCLR3_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR3_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR3 Mask */ +#define SCT_OUTPUTDIRCTRL_SETCLR4_Pos 8 /*!< SCT OUTPUTDIRCTRL: SETCLR4 Position */ +#define SCT_OUTPUTDIRCTRL_SETCLR4_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR4_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR4 Mask */ +#define SCT_OUTPUTDIRCTRL_SETCLR5_Pos 10 /*!< SCT OUTPUTDIRCTRL: SETCLR5 Position */ +#define SCT_OUTPUTDIRCTRL_SETCLR5_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR5_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR5 Mask */ +#define SCT_OUTPUTDIRCTRL_SETCLR6_Pos 12 /*!< SCT OUTPUTDIRCTRL: SETCLR6 Position */ +#define SCT_OUTPUTDIRCTRL_SETCLR6_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR6_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR6 Mask */ +#define SCT_OUTPUTDIRCTRL_SETCLR7_Pos 14 /*!< SCT OUTPUTDIRCTRL: SETCLR7 Position */ +#define SCT_OUTPUTDIRCTRL_SETCLR7_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR7_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR7 Mask */ +#define SCT_OUTPUTDIRCTRL_SETCLR8_Pos 16 /*!< SCT OUTPUTDIRCTRL: SETCLR8 Position */ +#define SCT_OUTPUTDIRCTRL_SETCLR8_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR8_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR8 Mask */ +#define SCT_OUTPUTDIRCTRL_SETCLR9_Pos 18 /*!< SCT OUTPUTDIRCTRL: SETCLR9 Position */ +#define SCT_OUTPUTDIRCTRL_SETCLR9_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR9_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR9 Mask */ +#define SCT_OUTPUTDIRCTRL_SETCLR10_Pos 20 /*!< SCT OUTPUTDIRCTRL: SETCLR10 Position */ +#define SCT_OUTPUTDIRCTRL_SETCLR10_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR10_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR10 Mask */ +#define SCT_OUTPUTDIRCTRL_SETCLR11_Pos 22 /*!< SCT OUTPUTDIRCTRL: SETCLR11 Position */ +#define SCT_OUTPUTDIRCTRL_SETCLR11_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR11_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR11 Mask */ +#define SCT_OUTPUTDIRCTRL_SETCLR12_Pos 24 /*!< SCT OUTPUTDIRCTRL: SETCLR12 Position */ +#define SCT_OUTPUTDIRCTRL_SETCLR12_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR12_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR12 Mask */ +#define SCT_OUTPUTDIRCTRL_SETCLR13_Pos 26 /*!< SCT OUTPUTDIRCTRL: SETCLR13 Position */ +#define SCT_OUTPUTDIRCTRL_SETCLR13_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR13_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR13 Mask */ +#define SCT_OUTPUTDIRCTRL_SETCLR14_Pos 28 /*!< SCT OUTPUTDIRCTRL: SETCLR14 Position */ +#define SCT_OUTPUTDIRCTRL_SETCLR14_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR14_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR14 Mask */ +#define SCT_OUTPUTDIRCTRL_SETCLR15_Pos 30 /*!< SCT OUTPUTDIRCTRL: SETCLR15 Position */ +#define SCT_OUTPUTDIRCTRL_SETCLR15_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR15_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR15 Mask */ + +/* ----------------------------------- SCT_RES ---------------------------------- */ +#define SCT_RES_O0RES_Pos 0 /*!< SCT RES: O0RES Position */ +#define SCT_RES_O0RES_Msk (0x03UL << SCT_RES_O0RES_Pos) /*!< SCT RES: O0RES Mask */ +#define SCT_RES_O1RES_Pos 2 /*!< SCT RES: O1RES Position */ +#define SCT_RES_O1RES_Msk (0x03UL << SCT_RES_O1RES_Pos) /*!< SCT RES: O1RES Mask */ +#define SCT_RES_O2RES_Pos 4 /*!< SCT RES: O2RES Position */ +#define SCT_RES_O2RES_Msk (0x03UL << SCT_RES_O2RES_Pos) /*!< SCT RES: O2RES Mask */ +#define SCT_RES_O3RES_Pos 6 /*!< SCT RES: O3RES Position */ +#define SCT_RES_O3RES_Msk (0x03UL << SCT_RES_O3RES_Pos) /*!< SCT RES: O3RES Mask */ +#define SCT_RES_O4RES_Pos 8 /*!< SCT RES: O4RES Position */ +#define SCT_RES_O4RES_Msk (0x03UL << SCT_RES_O4RES_Pos) /*!< SCT RES: O4RES Mask */ +#define SCT_RES_O5RES_Pos 10 /*!< SCT RES: O5RES Position */ +#define SCT_RES_O5RES_Msk (0x03UL << SCT_RES_O5RES_Pos) /*!< SCT RES: O5RES Mask */ +#define SCT_RES_O6RES_Pos 12 /*!< SCT RES: O6RES Position */ +#define SCT_RES_O6RES_Msk (0x03UL << SCT_RES_O6RES_Pos) /*!< SCT RES: O6RES Mask */ +#define SCT_RES_O7RES_Pos 14 /*!< SCT RES: O7RES Position */ +#define SCT_RES_O7RES_Msk (0x03UL << SCT_RES_O7RES_Pos) /*!< SCT RES: O7RES Mask */ +#define SCT_RES_O8RES_Pos 16 /*!< SCT RES: O8RES Position */ +#define SCT_RES_O8RES_Msk (0x03UL << SCT_RES_O8RES_Pos) /*!< SCT RES: O8RES Mask */ +#define SCT_RES_O9RES_Pos 18 /*!< SCT RES: O9RES Position */ +#define SCT_RES_O9RES_Msk (0x03UL << SCT_RES_O9RES_Pos) /*!< SCT RES: O9RES Mask */ +#define SCT_RES_O10RES_Pos 20 /*!< SCT RES: O10RES Position */ +#define SCT_RES_O10RES_Msk (0x03UL << SCT_RES_O10RES_Pos) /*!< SCT RES: O10RES Mask */ +#define SCT_RES_O11RES_Pos 22 /*!< SCT RES: O11RES Position */ +#define SCT_RES_O11RES_Msk (0x03UL << SCT_RES_O11RES_Pos) /*!< SCT RES: O11RES Mask */ +#define SCT_RES_O12RES_Pos 24 /*!< SCT RES: O12RES Position */ +#define SCT_RES_O12RES_Msk (0x03UL << SCT_RES_O12RES_Pos) /*!< SCT RES: O12RES Mask */ +#define SCT_RES_O13RES_Pos 26 /*!< SCT RES: O13RES Position */ +#define SCT_RES_O13RES_Msk (0x03UL << SCT_RES_O13RES_Pos) /*!< SCT RES: O13RES Mask */ +#define SCT_RES_O14RES_Pos 28 /*!< SCT RES: O14RES Position */ +#define SCT_RES_O14RES_Msk (0x03UL << SCT_RES_O14RES_Pos) /*!< SCT RES: O14RES Mask */ +#define SCT_RES_O15RES_Pos 30 /*!< SCT RES: O15RES Position */ +#define SCT_RES_O15RES_Msk (0x03UL << SCT_RES_O15RES_Pos) /*!< SCT RES: O15RES Mask */ + +/* --------------------------------- SCT_DMAREQ0 -------------------------------- */ +#define SCT_DMAREQ0_DEV_00_Pos 0 /*!< SCT DMAREQ0: DEV_00 Position */ +#define SCT_DMAREQ0_DEV_00_Msk (0x01UL << SCT_DMAREQ0_DEV_00_Pos) /*!< SCT DMAREQ0: DEV_00 Mask */ +#define SCT_DMAREQ0_DEV_01_Pos 1 /*!< SCT DMAREQ0: DEV_01 Position */ +#define SCT_DMAREQ0_DEV_01_Msk (0x01UL << SCT_DMAREQ0_DEV_01_Pos) /*!< SCT DMAREQ0: DEV_01 Mask */ +#define SCT_DMAREQ0_DEV_02_Pos 2 /*!< SCT DMAREQ0: DEV_02 Position */ +#define SCT_DMAREQ0_DEV_02_Msk (0x01UL << SCT_DMAREQ0_DEV_02_Pos) /*!< SCT DMAREQ0: DEV_02 Mask */ +#define SCT_DMAREQ0_DEV_03_Pos 3 /*!< SCT DMAREQ0: DEV_03 Position */ +#define SCT_DMAREQ0_DEV_03_Msk (0x01UL << SCT_DMAREQ0_DEV_03_Pos) /*!< SCT DMAREQ0: DEV_03 Mask */ +#define SCT_DMAREQ0_DEV_04_Pos 4 /*!< SCT DMAREQ0: DEV_04 Position */ +#define SCT_DMAREQ0_DEV_04_Msk (0x01UL << SCT_DMAREQ0_DEV_04_Pos) /*!< SCT DMAREQ0: DEV_04 Mask */ +#define SCT_DMAREQ0_DEV_05_Pos 5 /*!< SCT DMAREQ0: DEV_05 Position */ +#define SCT_DMAREQ0_DEV_05_Msk (0x01UL << SCT_DMAREQ0_DEV_05_Pos) /*!< SCT DMAREQ0: DEV_05 Mask */ +#define SCT_DMAREQ0_DEV_06_Pos 6 /*!< SCT DMAREQ0: DEV_06 Position */ +#define SCT_DMAREQ0_DEV_06_Msk (0x01UL << SCT_DMAREQ0_DEV_06_Pos) /*!< SCT DMAREQ0: DEV_06 Mask */ +#define SCT_DMAREQ0_DEV_07_Pos 7 /*!< SCT DMAREQ0: DEV_07 Position */ +#define SCT_DMAREQ0_DEV_07_Msk (0x01UL << SCT_DMAREQ0_DEV_07_Pos) /*!< SCT DMAREQ0: DEV_07 Mask */ +#define SCT_DMAREQ0_DEV_08_Pos 8 /*!< SCT DMAREQ0: DEV_08 Position */ +#define SCT_DMAREQ0_DEV_08_Msk (0x01UL << SCT_DMAREQ0_DEV_08_Pos) /*!< SCT DMAREQ0: DEV_08 Mask */ +#define SCT_DMAREQ0_DEV_09_Pos 9 /*!< SCT DMAREQ0: DEV_09 Position */ +#define SCT_DMAREQ0_DEV_09_Msk (0x01UL << SCT_DMAREQ0_DEV_09_Pos) /*!< SCT DMAREQ0: DEV_09 Mask */ +#define SCT_DMAREQ0_DEV_010_Pos 10 /*!< SCT DMAREQ0: DEV_010 Position */ +#define SCT_DMAREQ0_DEV_010_Msk (0x01UL << SCT_DMAREQ0_DEV_010_Pos) /*!< SCT DMAREQ0: DEV_010 Mask */ +#define SCT_DMAREQ0_DEV_011_Pos 11 /*!< SCT DMAREQ0: DEV_011 Position */ +#define SCT_DMAREQ0_DEV_011_Msk (0x01UL << SCT_DMAREQ0_DEV_011_Pos) /*!< SCT DMAREQ0: DEV_011 Mask */ +#define SCT_DMAREQ0_DEV_012_Pos 12 /*!< SCT DMAREQ0: DEV_012 Position */ +#define SCT_DMAREQ0_DEV_012_Msk (0x01UL << SCT_DMAREQ0_DEV_012_Pos) /*!< SCT DMAREQ0: DEV_012 Mask */ +#define SCT_DMAREQ0_DEV_013_Pos 13 /*!< SCT DMAREQ0: DEV_013 Position */ +#define SCT_DMAREQ0_DEV_013_Msk (0x01UL << SCT_DMAREQ0_DEV_013_Pos) /*!< SCT DMAREQ0: DEV_013 Mask */ +#define SCT_DMAREQ0_DEV_014_Pos 14 /*!< SCT DMAREQ0: DEV_014 Position */ +#define SCT_DMAREQ0_DEV_014_Msk (0x01UL << SCT_DMAREQ0_DEV_014_Pos) /*!< SCT DMAREQ0: DEV_014 Mask */ +#define SCT_DMAREQ0_DEV_015_Pos 15 /*!< SCT DMAREQ0: DEV_015 Position */ +#define SCT_DMAREQ0_DEV_015_Msk (0x01UL << SCT_DMAREQ0_DEV_015_Pos) /*!< SCT DMAREQ0: DEV_015 Mask */ +#define SCT_DMAREQ0_DRL0_Pos 30 /*!< SCT DMAREQ0: DRL0 Position */ +#define SCT_DMAREQ0_DRL0_Msk (0x01UL << SCT_DMAREQ0_DRL0_Pos) /*!< SCT DMAREQ0: DRL0 Mask */ +#define SCT_DMAREQ0_DRQ0_Pos 31 /*!< SCT DMAREQ0: DRQ0 Position */ +#define SCT_DMAREQ0_DRQ0_Msk (0x01UL << SCT_DMAREQ0_DRQ0_Pos) /*!< SCT DMAREQ0: DRQ0 Mask */ + +/* --------------------------------- SCT_DMAREQ1 -------------------------------- */ +#define SCT_DMAREQ1_DEV_10_Pos 0 /*!< SCT DMAREQ1: DEV_10 Position */ +#define SCT_DMAREQ1_DEV_10_Msk (0x01UL << SCT_DMAREQ1_DEV_10_Pos) /*!< SCT DMAREQ1: DEV_10 Mask */ +#define SCT_DMAREQ1_DEV_11_Pos 1 /*!< SCT DMAREQ1: DEV_11 Position */ +#define SCT_DMAREQ1_DEV_11_Msk (0x01UL << SCT_DMAREQ1_DEV_11_Pos) /*!< SCT DMAREQ1: DEV_11 Mask */ +#define SCT_DMAREQ1_DEV_12_Pos 2 /*!< SCT DMAREQ1: DEV_12 Position */ +#define SCT_DMAREQ1_DEV_12_Msk (0x01UL << SCT_DMAREQ1_DEV_12_Pos) /*!< SCT DMAREQ1: DEV_12 Mask */ +#define SCT_DMAREQ1_DEV_13_Pos 3 /*!< SCT DMAREQ1: DEV_13 Position */ +#define SCT_DMAREQ1_DEV_13_Msk (0x01UL << SCT_DMAREQ1_DEV_13_Pos) /*!< SCT DMAREQ1: DEV_13 Mask */ +#define SCT_DMAREQ1_DEV_14_Pos 4 /*!< SCT DMAREQ1: DEV_14 Position */ +#define SCT_DMAREQ1_DEV_14_Msk (0x01UL << SCT_DMAREQ1_DEV_14_Pos) /*!< SCT DMAREQ1: DEV_14 Mask */ +#define SCT_DMAREQ1_DEV_15_Pos 5 /*!< SCT DMAREQ1: DEV_15 Position */ +#define SCT_DMAREQ1_DEV_15_Msk (0x01UL << SCT_DMAREQ1_DEV_15_Pos) /*!< SCT DMAREQ1: DEV_15 Mask */ +#define SCT_DMAREQ1_DEV_16_Pos 6 /*!< SCT DMAREQ1: DEV_16 Position */ +#define SCT_DMAREQ1_DEV_16_Msk (0x01UL << SCT_DMAREQ1_DEV_16_Pos) /*!< SCT DMAREQ1: DEV_16 Mask */ +#define SCT_DMAREQ1_DEV_17_Pos 7 /*!< SCT DMAREQ1: DEV_17 Position */ +#define SCT_DMAREQ1_DEV_17_Msk (0x01UL << SCT_DMAREQ1_DEV_17_Pos) /*!< SCT DMAREQ1: DEV_17 Mask */ +#define SCT_DMAREQ1_DEV_18_Pos 8 /*!< SCT DMAREQ1: DEV_18 Position */ +#define SCT_DMAREQ1_DEV_18_Msk (0x01UL << SCT_DMAREQ1_DEV_18_Pos) /*!< SCT DMAREQ1: DEV_18 Mask */ +#define SCT_DMAREQ1_DEV_19_Pos 9 /*!< SCT DMAREQ1: DEV_19 Position */ +#define SCT_DMAREQ1_DEV_19_Msk (0x01UL << SCT_DMAREQ1_DEV_19_Pos) /*!< SCT DMAREQ1: DEV_19 Mask */ +#define SCT_DMAREQ1_DEV_110_Pos 10 /*!< SCT DMAREQ1: DEV_110 Position */ +#define SCT_DMAREQ1_DEV_110_Msk (0x01UL << SCT_DMAREQ1_DEV_110_Pos) /*!< SCT DMAREQ1: DEV_110 Mask */ +#define SCT_DMAREQ1_DEV_111_Pos 11 /*!< SCT DMAREQ1: DEV_111 Position */ +#define SCT_DMAREQ1_DEV_111_Msk (0x01UL << SCT_DMAREQ1_DEV_111_Pos) /*!< SCT DMAREQ1: DEV_111 Mask */ +#define SCT_DMAREQ1_DEV_112_Pos 12 /*!< SCT DMAREQ1: DEV_112 Position */ +#define SCT_DMAREQ1_DEV_112_Msk (0x01UL << SCT_DMAREQ1_DEV_112_Pos) /*!< SCT DMAREQ1: DEV_112 Mask */ +#define SCT_DMAREQ1_DEV_113_Pos 13 /*!< SCT DMAREQ1: DEV_113 Position */ +#define SCT_DMAREQ1_DEV_113_Msk (0x01UL << SCT_DMAREQ1_DEV_113_Pos) /*!< SCT DMAREQ1: DEV_113 Mask */ +#define SCT_DMAREQ1_DEV_114_Pos 14 /*!< SCT DMAREQ1: DEV_114 Position */ +#define SCT_DMAREQ1_DEV_114_Msk (0x01UL << SCT_DMAREQ1_DEV_114_Pos) /*!< SCT DMAREQ1: DEV_114 Mask */ +#define SCT_DMAREQ1_DEV_115_Pos 15 /*!< SCT DMAREQ1: DEV_115 Position */ +#define SCT_DMAREQ1_DEV_115_Msk (0x01UL << SCT_DMAREQ1_DEV_115_Pos) /*!< SCT DMAREQ1: DEV_115 Mask */ +#define SCT_DMAREQ1_DRL1_Pos 30 /*!< SCT DMAREQ1: DRL1 Position */ +#define SCT_DMAREQ1_DRL1_Msk (0x01UL << SCT_DMAREQ1_DRL1_Pos) /*!< SCT DMAREQ1: DRL1 Mask */ +#define SCT_DMAREQ1_DRQ1_Pos 31 /*!< SCT DMAREQ1: DRQ1 Position */ +#define SCT_DMAREQ1_DRQ1_Msk (0x01UL << SCT_DMAREQ1_DRQ1_Pos) /*!< SCT DMAREQ1: DRQ1 Mask */ + +/* ---------------------------------- SCT_EVEN ---------------------------------- */ +#define SCT_EVEN_IEN0_Pos 0 /*!< SCT EVEN: IEN0 Position */ +#define SCT_EVEN_IEN0_Msk (0x01UL << SCT_EVEN_IEN0_Pos) /*!< SCT EVEN: IEN0 Mask */ +#define SCT_EVEN_IEN1_Pos 1 /*!< SCT EVEN: IEN1 Position */ +#define SCT_EVEN_IEN1_Msk (0x01UL << SCT_EVEN_IEN1_Pos) /*!< SCT EVEN: IEN1 Mask */ +#define SCT_EVEN_IEN2_Pos 2 /*!< SCT EVEN: IEN2 Position */ +#define SCT_EVEN_IEN2_Msk (0x01UL << SCT_EVEN_IEN2_Pos) /*!< SCT EVEN: IEN2 Mask */ +#define SCT_EVEN_IEN3_Pos 3 /*!< SCT EVEN: IEN3 Position */ +#define SCT_EVEN_IEN3_Msk (0x01UL << SCT_EVEN_IEN3_Pos) /*!< SCT EVEN: IEN3 Mask */ +#define SCT_EVEN_IEN4_Pos 4 /*!< SCT EVEN: IEN4 Position */ +#define SCT_EVEN_IEN4_Msk (0x01UL << SCT_EVEN_IEN4_Pos) /*!< SCT EVEN: IEN4 Mask */ +#define SCT_EVEN_IEN5_Pos 5 /*!< SCT EVEN: IEN5 Position */ +#define SCT_EVEN_IEN5_Msk (0x01UL << SCT_EVEN_IEN5_Pos) /*!< SCT EVEN: IEN5 Mask */ +#define SCT_EVEN_IEN6_Pos 6 /*!< SCT EVEN: IEN6 Position */ +#define SCT_EVEN_IEN6_Msk (0x01UL << SCT_EVEN_IEN6_Pos) /*!< SCT EVEN: IEN6 Mask */ +#define SCT_EVEN_IEN7_Pos 7 /*!< SCT EVEN: IEN7 Position */ +#define SCT_EVEN_IEN7_Msk (0x01UL << SCT_EVEN_IEN7_Pos) /*!< SCT EVEN: IEN7 Mask */ +#define SCT_EVEN_IEN8_Pos 8 /*!< SCT EVEN: IEN8 Position */ +#define SCT_EVEN_IEN8_Msk (0x01UL << SCT_EVEN_IEN8_Pos) /*!< SCT EVEN: IEN8 Mask */ +#define SCT_EVEN_IEN9_Pos 9 /*!< SCT EVEN: IEN9 Position */ +#define SCT_EVEN_IEN9_Msk (0x01UL << SCT_EVEN_IEN9_Pos) /*!< SCT EVEN: IEN9 Mask */ +#define SCT_EVEN_IEN10_Pos 10 /*!< SCT EVEN: IEN10 Position */ +#define SCT_EVEN_IEN10_Msk (0x01UL << SCT_EVEN_IEN10_Pos) /*!< SCT EVEN: IEN10 Mask */ +#define SCT_EVEN_IEN11_Pos 11 /*!< SCT EVEN: IEN11 Position */ +#define SCT_EVEN_IEN11_Msk (0x01UL << SCT_EVEN_IEN11_Pos) /*!< SCT EVEN: IEN11 Mask */ +#define SCT_EVEN_IEN12_Pos 12 /*!< SCT EVEN: IEN12 Position */ +#define SCT_EVEN_IEN12_Msk (0x01UL << SCT_EVEN_IEN12_Pos) /*!< SCT EVEN: IEN12 Mask */ +#define SCT_EVEN_IEN13_Pos 13 /*!< SCT EVEN: IEN13 Position */ +#define SCT_EVEN_IEN13_Msk (0x01UL << SCT_EVEN_IEN13_Pos) /*!< SCT EVEN: IEN13 Mask */ +#define SCT_EVEN_IEN14_Pos 14 /*!< SCT EVEN: IEN14 Position */ +#define SCT_EVEN_IEN14_Msk (0x01UL << SCT_EVEN_IEN14_Pos) /*!< SCT EVEN: IEN14 Mask */ +#define SCT_EVEN_IEN15_Pos 15 /*!< SCT EVEN: IEN15 Position */ +#define SCT_EVEN_IEN15_Msk (0x01UL << SCT_EVEN_IEN15_Pos) /*!< SCT EVEN: IEN15 Mask */ + +/* --------------------------------- SCT_EVFLAG --------------------------------- */ +#define SCT_EVFLAG_FLAG0_Pos 0 /*!< SCT EVFLAG: FLAG0 Position */ +#define SCT_EVFLAG_FLAG0_Msk (0x01UL << SCT_EVFLAG_FLAG0_Pos) /*!< SCT EVFLAG: FLAG0 Mask */ +#define SCT_EVFLAG_FLAG1_Pos 1 /*!< SCT EVFLAG: FLAG1 Position */ +#define SCT_EVFLAG_FLAG1_Msk (0x01UL << SCT_EVFLAG_FLAG1_Pos) /*!< SCT EVFLAG: FLAG1 Mask */ +#define SCT_EVFLAG_FLAG2_Pos 2 /*!< SCT EVFLAG: FLAG2 Position */ +#define SCT_EVFLAG_FLAG2_Msk (0x01UL << SCT_EVFLAG_FLAG2_Pos) /*!< SCT EVFLAG: FLAG2 Mask */ +#define SCT_EVFLAG_FLAG3_Pos 3 /*!< SCT EVFLAG: FLAG3 Position */ +#define SCT_EVFLAG_FLAG3_Msk (0x01UL << SCT_EVFLAG_FLAG3_Pos) /*!< SCT EVFLAG: FLAG3 Mask */ +#define SCT_EVFLAG_FLAG4_Pos 4 /*!< SCT EVFLAG: FLAG4 Position */ +#define SCT_EVFLAG_FLAG4_Msk (0x01UL << SCT_EVFLAG_FLAG4_Pos) /*!< SCT EVFLAG: FLAG4 Mask */ +#define SCT_EVFLAG_FLAG5_Pos 5 /*!< SCT EVFLAG: FLAG5 Position */ +#define SCT_EVFLAG_FLAG5_Msk (0x01UL << SCT_EVFLAG_FLAG5_Pos) /*!< SCT EVFLAG: FLAG5 Mask */ +#define SCT_EVFLAG_FLAG6_Pos 6 /*!< SCT EVFLAG: FLAG6 Position */ +#define SCT_EVFLAG_FLAG6_Msk (0x01UL << SCT_EVFLAG_FLAG6_Pos) /*!< SCT EVFLAG: FLAG6 Mask */ +#define SCT_EVFLAG_FLAG7_Pos 7 /*!< SCT EVFLAG: FLAG7 Position */ +#define SCT_EVFLAG_FLAG7_Msk (0x01UL << SCT_EVFLAG_FLAG7_Pos) /*!< SCT EVFLAG: FLAG7 Mask */ +#define SCT_EVFLAG_FLAG8_Pos 8 /*!< SCT EVFLAG: FLAG8 Position */ +#define SCT_EVFLAG_FLAG8_Msk (0x01UL << SCT_EVFLAG_FLAG8_Pos) /*!< SCT EVFLAG: FLAG8 Mask */ +#define SCT_EVFLAG_FLAG9_Pos 9 /*!< SCT EVFLAG: FLAG9 Position */ +#define SCT_EVFLAG_FLAG9_Msk (0x01UL << SCT_EVFLAG_FLAG9_Pos) /*!< SCT EVFLAG: FLAG9 Mask */ +#define SCT_EVFLAG_FLAG10_Pos 10 /*!< SCT EVFLAG: FLAG10 Position */ +#define SCT_EVFLAG_FLAG10_Msk (0x01UL << SCT_EVFLAG_FLAG10_Pos) /*!< SCT EVFLAG: FLAG10 Mask */ +#define SCT_EVFLAG_FLAG11_Pos 11 /*!< SCT EVFLAG: FLAG11 Position */ +#define SCT_EVFLAG_FLAG11_Msk (0x01UL << SCT_EVFLAG_FLAG11_Pos) /*!< SCT EVFLAG: FLAG11 Mask */ +#define SCT_EVFLAG_FLAG12_Pos 12 /*!< SCT EVFLAG: FLAG12 Position */ +#define SCT_EVFLAG_FLAG12_Msk (0x01UL << SCT_EVFLAG_FLAG12_Pos) /*!< SCT EVFLAG: FLAG12 Mask */ +#define SCT_EVFLAG_FLAG13_Pos 13 /*!< SCT EVFLAG: FLAG13 Position */ +#define SCT_EVFLAG_FLAG13_Msk (0x01UL << SCT_EVFLAG_FLAG13_Pos) /*!< SCT EVFLAG: FLAG13 Mask */ +#define SCT_EVFLAG_FLAG14_Pos 14 /*!< SCT EVFLAG: FLAG14 Position */ +#define SCT_EVFLAG_FLAG14_Msk (0x01UL << SCT_EVFLAG_FLAG14_Pos) /*!< SCT EVFLAG: FLAG14 Mask */ +#define SCT_EVFLAG_FLAG15_Pos 15 /*!< SCT EVFLAG: FLAG15 Position */ +#define SCT_EVFLAG_FLAG15_Msk (0x01UL << SCT_EVFLAG_FLAG15_Pos) /*!< SCT EVFLAG: FLAG15 Mask */ + +/* ---------------------------------- SCT_CONEN --------------------------------- */ +#define SCT_CONEN_NCEN0_Pos 0 /*!< SCT CONEN: NCEN0 Position */ +#define SCT_CONEN_NCEN0_Msk (0x01UL << SCT_CONEN_NCEN0_Pos) /*!< SCT CONEN: NCEN0 Mask */ +#define SCT_CONEN_NCEN1_Pos 1 /*!< SCT CONEN: NCEN1 Position */ +#define SCT_CONEN_NCEN1_Msk (0x01UL << SCT_CONEN_NCEN1_Pos) /*!< SCT CONEN: NCEN1 Mask */ +#define SCT_CONEN_NCEN2_Pos 2 /*!< SCT CONEN: NCEN2 Position */ +#define SCT_CONEN_NCEN2_Msk (0x01UL << SCT_CONEN_NCEN2_Pos) /*!< SCT CONEN: NCEN2 Mask */ +#define SCT_CONEN_NCEN3_Pos 3 /*!< SCT CONEN: NCEN3 Position */ +#define SCT_CONEN_NCEN3_Msk (0x01UL << SCT_CONEN_NCEN3_Pos) /*!< SCT CONEN: NCEN3 Mask */ +#define SCT_CONEN_NCEN4_Pos 4 /*!< SCT CONEN: NCEN4 Position */ +#define SCT_CONEN_NCEN4_Msk (0x01UL << SCT_CONEN_NCEN4_Pos) /*!< SCT CONEN: NCEN4 Mask */ +#define SCT_CONEN_NCEN5_Pos 5 /*!< SCT CONEN: NCEN5 Position */ +#define SCT_CONEN_NCEN5_Msk (0x01UL << SCT_CONEN_NCEN5_Pos) /*!< SCT CONEN: NCEN5 Mask */ +#define SCT_CONEN_NCEN6_Pos 6 /*!< SCT CONEN: NCEN6 Position */ +#define SCT_CONEN_NCEN6_Msk (0x01UL << SCT_CONEN_NCEN6_Pos) /*!< SCT CONEN: NCEN6 Mask */ +#define SCT_CONEN_NCEN7_Pos 7 /*!< SCT CONEN: NCEN7 Position */ +#define SCT_CONEN_NCEN7_Msk (0x01UL << SCT_CONEN_NCEN7_Pos) /*!< SCT CONEN: NCEN7 Mask */ +#define SCT_CONEN_NCEN8_Pos 8 /*!< SCT CONEN: NCEN8 Position */ +#define SCT_CONEN_NCEN8_Msk (0x01UL << SCT_CONEN_NCEN8_Pos) /*!< SCT CONEN: NCEN8 Mask */ +#define SCT_CONEN_NCEN9_Pos 9 /*!< SCT CONEN: NCEN9 Position */ +#define SCT_CONEN_NCEN9_Msk (0x01UL << SCT_CONEN_NCEN9_Pos) /*!< SCT CONEN: NCEN9 Mask */ +#define SCT_CONEN_NCEN10_Pos 10 /*!< SCT CONEN: NCEN10 Position */ +#define SCT_CONEN_NCEN10_Msk (0x01UL << SCT_CONEN_NCEN10_Pos) /*!< SCT CONEN: NCEN10 Mask */ +#define SCT_CONEN_NCEN11_Pos 11 /*!< SCT CONEN: NCEN11 Position */ +#define SCT_CONEN_NCEN11_Msk (0x01UL << SCT_CONEN_NCEN11_Pos) /*!< SCT CONEN: NCEN11 Mask */ +#define SCT_CONEN_NCEN12_Pos 12 /*!< SCT CONEN: NCEN12 Position */ +#define SCT_CONEN_NCEN12_Msk (0x01UL << SCT_CONEN_NCEN12_Pos) /*!< SCT CONEN: NCEN12 Mask */ +#define SCT_CONEN_NCEN13_Pos 13 /*!< SCT CONEN: NCEN13 Position */ +#define SCT_CONEN_NCEN13_Msk (0x01UL << SCT_CONEN_NCEN13_Pos) /*!< SCT CONEN: NCEN13 Mask */ +#define SCT_CONEN_NCEN14_Pos 14 /*!< SCT CONEN: NCEN14 Position */ +#define SCT_CONEN_NCEN14_Msk (0x01UL << SCT_CONEN_NCEN14_Pos) /*!< SCT CONEN: NCEN14 Mask */ +#define SCT_CONEN_NCEN15_Pos 15 /*!< SCT CONEN: NCEN15 Position */ +#define SCT_CONEN_NCEN15_Msk (0x01UL << SCT_CONEN_NCEN15_Pos) /*!< SCT CONEN: NCEN15 Mask */ + +/* --------------------------------- SCT_CONFLAG -------------------------------- */ +#define SCT_CONFLAG_NCFLAG0_Pos 0 /*!< SCT CONFLAG: NCFLAG0 Position */ +#define SCT_CONFLAG_NCFLAG0_Msk (0x01UL << SCT_CONFLAG_NCFLAG0_Pos) /*!< SCT CONFLAG: NCFLAG0 Mask */ +#define SCT_CONFLAG_NCFLAG1_Pos 1 /*!< SCT CONFLAG: NCFLAG1 Position */ +#define SCT_CONFLAG_NCFLAG1_Msk (0x01UL << SCT_CONFLAG_NCFLAG1_Pos) /*!< SCT CONFLAG: NCFLAG1 Mask */ +#define SCT_CONFLAG_NCFLAG2_Pos 2 /*!< SCT CONFLAG: NCFLAG2 Position */ +#define SCT_CONFLAG_NCFLAG2_Msk (0x01UL << SCT_CONFLAG_NCFLAG2_Pos) /*!< SCT CONFLAG: NCFLAG2 Mask */ +#define SCT_CONFLAG_NCFLAG3_Pos 3 /*!< SCT CONFLAG: NCFLAG3 Position */ +#define SCT_CONFLAG_NCFLAG3_Msk (0x01UL << SCT_CONFLAG_NCFLAG3_Pos) /*!< SCT CONFLAG: NCFLAG3 Mask */ +#define SCT_CONFLAG_NCFLAG4_Pos 4 /*!< SCT CONFLAG: NCFLAG4 Position */ +#define SCT_CONFLAG_NCFLAG4_Msk (0x01UL << SCT_CONFLAG_NCFLAG4_Pos) /*!< SCT CONFLAG: NCFLAG4 Mask */ +#define SCT_CONFLAG_NCFLAG5_Pos 5 /*!< SCT CONFLAG: NCFLAG5 Position */ +#define SCT_CONFLAG_NCFLAG5_Msk (0x01UL << SCT_CONFLAG_NCFLAG5_Pos) /*!< SCT CONFLAG: NCFLAG5 Mask */ +#define SCT_CONFLAG_NCFLAG6_Pos 6 /*!< SCT CONFLAG: NCFLAG6 Position */ +#define SCT_CONFLAG_NCFLAG6_Msk (0x01UL << SCT_CONFLAG_NCFLAG6_Pos) /*!< SCT CONFLAG: NCFLAG6 Mask */ +#define SCT_CONFLAG_NCFLAG7_Pos 7 /*!< SCT CONFLAG: NCFLAG7 Position */ +#define SCT_CONFLAG_NCFLAG7_Msk (0x01UL << SCT_CONFLAG_NCFLAG7_Pos) /*!< SCT CONFLAG: NCFLAG7 Mask */ +#define SCT_CONFLAG_NCFLAG8_Pos 8 /*!< SCT CONFLAG: NCFLAG8 Position */ +#define SCT_CONFLAG_NCFLAG8_Msk (0x01UL << SCT_CONFLAG_NCFLAG8_Pos) /*!< SCT CONFLAG: NCFLAG8 Mask */ +#define SCT_CONFLAG_NCFLAG9_Pos 9 /*!< SCT CONFLAG: NCFLAG9 Position */ +#define SCT_CONFLAG_NCFLAG9_Msk (0x01UL << SCT_CONFLAG_NCFLAG9_Pos) /*!< SCT CONFLAG: NCFLAG9 Mask */ +#define SCT_CONFLAG_NCFLAG10_Pos 10 /*!< SCT CONFLAG: NCFLAG10 Position */ +#define SCT_CONFLAG_NCFLAG10_Msk (0x01UL << SCT_CONFLAG_NCFLAG10_Pos) /*!< SCT CONFLAG: NCFLAG10 Mask */ +#define SCT_CONFLAG_NCFLAG11_Pos 11 /*!< SCT CONFLAG: NCFLAG11 Position */ +#define SCT_CONFLAG_NCFLAG11_Msk (0x01UL << SCT_CONFLAG_NCFLAG11_Pos) /*!< SCT CONFLAG: NCFLAG11 Mask */ +#define SCT_CONFLAG_NCFLAG12_Pos 12 /*!< SCT CONFLAG: NCFLAG12 Position */ +#define SCT_CONFLAG_NCFLAG12_Msk (0x01UL << SCT_CONFLAG_NCFLAG12_Pos) /*!< SCT CONFLAG: NCFLAG12 Mask */ +#define SCT_CONFLAG_NCFLAG13_Pos 13 /*!< SCT CONFLAG: NCFLAG13 Position */ +#define SCT_CONFLAG_NCFLAG13_Msk (0x01UL << SCT_CONFLAG_NCFLAG13_Pos) /*!< SCT CONFLAG: NCFLAG13 Mask */ +#define SCT_CONFLAG_NCFLAG14_Pos 14 /*!< SCT CONFLAG: NCFLAG14 Position */ +#define SCT_CONFLAG_NCFLAG14_Msk (0x01UL << SCT_CONFLAG_NCFLAG14_Pos) /*!< SCT CONFLAG: NCFLAG14 Mask */ +#define SCT_CONFLAG_NCFLAG15_Pos 15 /*!< SCT CONFLAG: NCFLAG15 Position */ +#define SCT_CONFLAG_NCFLAG15_Msk (0x01UL << SCT_CONFLAG_NCFLAG15_Pos) /*!< SCT CONFLAG: NCFLAG15 Mask */ +#define SCT_CONFLAG_BUSERRL_Pos 30 /*!< SCT CONFLAG: BUSERRL Position */ +#define SCT_CONFLAG_BUSERRL_Msk (0x01UL << SCT_CONFLAG_BUSERRL_Pos) /*!< SCT CONFLAG: BUSERRL Mask */ +#define SCT_CONFLAG_BUSERRH_Pos 31 /*!< SCT CONFLAG: BUSERRH Position */ +#define SCT_CONFLAG_BUSERRH_Msk (0x01UL << SCT_CONFLAG_BUSERRH_Pos) /*!< SCT CONFLAG: BUSERRH Mask */ + +/* --------------------------------- SCT_MATCH0 --------------------------------- */ +#define SCT_MATCH0_MATCH_L_Pos 0 /*!< SCT MATCH0: MATCH_L Position */ +#define SCT_MATCH0_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH0_MATCH_L_Pos) /*!< SCT MATCH0: MATCH_L Mask */ +#define SCT_MATCH0_MATCH_H_Pos 16 /*!< SCT MATCH0: MATCH_H Position */ +#define SCT_MATCH0_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH0_MATCH_H_Pos) /*!< SCT MATCH0: MATCH_H Mask */ + +/* ---------------------------------- SCT_CAP0 ---------------------------------- */ +#define SCT_CAP0_CAP_L_Pos 0 /*!< SCT CAP0: CAP_L Position */ +#define SCT_CAP0_CAP_L_Msk (0x0000ffffUL << SCT_CAP0_CAP_L_Pos) /*!< SCT CAP0: CAP_L Mask */ +#define SCT_CAP0_CAP_H_Pos 16 /*!< SCT CAP0: CAP_H Position */ +#define SCT_CAP0_CAP_H_Msk (0x0000ffffUL << SCT_CAP0_CAP_H_Pos) /*!< SCT CAP0: CAP_H Mask */ + +/* --------------------------------- SCT_MATCH1 --------------------------------- */ +#define SCT_MATCH1_MATCH_L_Pos 0 /*!< SCT MATCH1: MATCH_L Position */ +#define SCT_MATCH1_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH1_MATCH_L_Pos) /*!< SCT MATCH1: MATCH_L Mask */ +#define SCT_MATCH1_MATCH_H_Pos 16 /*!< SCT MATCH1: MATCH_H Position */ +#define SCT_MATCH1_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH1_MATCH_H_Pos) /*!< SCT MATCH1: MATCH_H Mask */ + +/* ---------------------------------- SCT_CAP1 ---------------------------------- */ +#define SCT_CAP1_CAP_L_Pos 0 /*!< SCT CAP1: CAP_L Position */ +#define SCT_CAP1_CAP_L_Msk (0x0000ffffUL << SCT_CAP1_CAP_L_Pos) /*!< SCT CAP1: CAP_L Mask */ +#define SCT_CAP1_CAP_H_Pos 16 /*!< SCT CAP1: CAP_H Position */ +#define SCT_CAP1_CAP_H_Msk (0x0000ffffUL << SCT_CAP1_CAP_H_Pos) /*!< SCT CAP1: CAP_H Mask */ + +/* --------------------------------- SCT_MATCH2 --------------------------------- */ +#define SCT_MATCH2_MATCH_L_Pos 0 /*!< SCT MATCH2: MATCH_L Position */ +#define SCT_MATCH2_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH2_MATCH_L_Pos) /*!< SCT MATCH2: MATCH_L Mask */ +#define SCT_MATCH2_MATCH_H_Pos 16 /*!< SCT MATCH2: MATCH_H Position */ +#define SCT_MATCH2_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH2_MATCH_H_Pos) /*!< SCT MATCH2: MATCH_H Mask */ + +/* ---------------------------------- SCT_CAP2 ---------------------------------- */ +#define SCT_CAP2_CAP_L_Pos 0 /*!< SCT CAP2: CAP_L Position */ +#define SCT_CAP2_CAP_L_Msk (0x0000ffffUL << SCT_CAP2_CAP_L_Pos) /*!< SCT CAP2: CAP_L Mask */ +#define SCT_CAP2_CAP_H_Pos 16 /*!< SCT CAP2: CAP_H Position */ +#define SCT_CAP2_CAP_H_Msk (0x0000ffffUL << SCT_CAP2_CAP_H_Pos) /*!< SCT CAP2: CAP_H Mask */ + +/* --------------------------------- SCT_MATCH3 --------------------------------- */ +#define SCT_MATCH3_MATCH_L_Pos 0 /*!< SCT MATCH3: MATCH_L Position */ +#define SCT_MATCH3_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH3_MATCH_L_Pos) /*!< SCT MATCH3: MATCH_L Mask */ +#define SCT_MATCH3_MATCH_H_Pos 16 /*!< SCT MATCH3: MATCH_H Position */ +#define SCT_MATCH3_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH3_MATCH_H_Pos) /*!< SCT MATCH3: MATCH_H Mask */ + +/* ---------------------------------- SCT_CAP3 ---------------------------------- */ +#define SCT_CAP3_CAP_L_Pos 0 /*!< SCT CAP3: CAP_L Position */ +#define SCT_CAP3_CAP_L_Msk (0x0000ffffUL << SCT_CAP3_CAP_L_Pos) /*!< SCT CAP3: CAP_L Mask */ +#define SCT_CAP3_CAP_H_Pos 16 /*!< SCT CAP3: CAP_H Position */ +#define SCT_CAP3_CAP_H_Msk (0x0000ffffUL << SCT_CAP3_CAP_H_Pos) /*!< SCT CAP3: CAP_H Mask */ + +/* ---------------------------------- SCT_CAP4 ---------------------------------- */ +#define SCT_CAP4_CAP_L_Pos 0 /*!< SCT CAP4: CAP_L Position */ +#define SCT_CAP4_CAP_L_Msk (0x0000ffffUL << SCT_CAP4_CAP_L_Pos) /*!< SCT CAP4: CAP_L Mask */ +#define SCT_CAP4_CAP_H_Pos 16 /*!< SCT CAP4: CAP_H Position */ +#define SCT_CAP4_CAP_H_Msk (0x0000ffffUL << SCT_CAP4_CAP_H_Pos) /*!< SCT CAP4: CAP_H Mask */ + +/* --------------------------------- SCT_MATCH4 --------------------------------- */ +#define SCT_MATCH4_MATCH_L_Pos 0 /*!< SCT MATCH4: MATCH_L Position */ +#define SCT_MATCH4_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH4_MATCH_L_Pos) /*!< SCT MATCH4: MATCH_L Mask */ +#define SCT_MATCH4_MATCH_H_Pos 16 /*!< SCT MATCH4: MATCH_H Position */ +#define SCT_MATCH4_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH4_MATCH_H_Pos) /*!< SCT MATCH4: MATCH_H Mask */ + +/* --------------------------------- SCT_MATCH5 --------------------------------- */ +#define SCT_MATCH5_MATCH_L_Pos 0 /*!< SCT MATCH5: MATCH_L Position */ +#define SCT_MATCH5_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH5_MATCH_L_Pos) /*!< SCT MATCH5: MATCH_L Mask */ +#define SCT_MATCH5_MATCH_H_Pos 16 /*!< SCT MATCH5: MATCH_H Position */ +#define SCT_MATCH5_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH5_MATCH_H_Pos) /*!< SCT MATCH5: MATCH_H Mask */ + +/* ---------------------------------- SCT_CAP5 ---------------------------------- */ +#define SCT_CAP5_CAP_L_Pos 0 /*!< SCT CAP5: CAP_L Position */ +#define SCT_CAP5_CAP_L_Msk (0x0000ffffUL << SCT_CAP5_CAP_L_Pos) /*!< SCT CAP5: CAP_L Mask */ +#define SCT_CAP5_CAP_H_Pos 16 /*!< SCT CAP5: CAP_H Position */ +#define SCT_CAP5_CAP_H_Msk (0x0000ffffUL << SCT_CAP5_CAP_H_Pos) /*!< SCT CAP5: CAP_H Mask */ + +/* ---------------------------------- SCT_CAP6 ---------------------------------- */ +#define SCT_CAP6_CAP_L_Pos 0 /*!< SCT CAP6: CAP_L Position */ +#define SCT_CAP6_CAP_L_Msk (0x0000ffffUL << SCT_CAP6_CAP_L_Pos) /*!< SCT CAP6: CAP_L Mask */ +#define SCT_CAP6_CAP_H_Pos 16 /*!< SCT CAP6: CAP_H Position */ +#define SCT_CAP6_CAP_H_Msk (0x0000ffffUL << SCT_CAP6_CAP_H_Pos) /*!< SCT CAP6: CAP_H Mask */ + +/* --------------------------------- SCT_MATCH6 --------------------------------- */ +#define SCT_MATCH6_MATCH_L_Pos 0 /*!< SCT MATCH6: MATCH_L Position */ +#define SCT_MATCH6_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH6_MATCH_L_Pos) /*!< SCT MATCH6: MATCH_L Mask */ +#define SCT_MATCH6_MATCH_H_Pos 16 /*!< SCT MATCH6: MATCH_H Position */ +#define SCT_MATCH6_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH6_MATCH_H_Pos) /*!< SCT MATCH6: MATCH_H Mask */ + +/* ---------------------------------- SCT_CAP7 ---------------------------------- */ +#define SCT_CAP7_CAP_L_Pos 0 /*!< SCT CAP7: CAP_L Position */ +#define SCT_CAP7_CAP_L_Msk (0x0000ffffUL << SCT_CAP7_CAP_L_Pos) /*!< SCT CAP7: CAP_L Mask */ +#define SCT_CAP7_CAP_H_Pos 16 /*!< SCT CAP7: CAP_H Position */ +#define SCT_CAP7_CAP_H_Msk (0x0000ffffUL << SCT_CAP7_CAP_H_Pos) /*!< SCT CAP7: CAP_H Mask */ + +/* --------------------------------- SCT_MATCH7 --------------------------------- */ +#define SCT_MATCH7_MATCH_L_Pos 0 /*!< SCT MATCH7: MATCH_L Position */ +#define SCT_MATCH7_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH7_MATCH_L_Pos) /*!< SCT MATCH7: MATCH_L Mask */ +#define SCT_MATCH7_MATCH_H_Pos 16 /*!< SCT MATCH7: MATCH_H Position */ +#define SCT_MATCH7_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH7_MATCH_H_Pos) /*!< SCT MATCH7: MATCH_H Mask */ + +/* ---------------------------------- SCT_CAP8 ---------------------------------- */ +#define SCT_CAP8_CAP_L_Pos 0 /*!< SCT CAP8: CAP_L Position */ +#define SCT_CAP8_CAP_L_Msk (0x0000ffffUL << SCT_CAP8_CAP_L_Pos) /*!< SCT CAP8: CAP_L Mask */ +#define SCT_CAP8_CAP_H_Pos 16 /*!< SCT CAP8: CAP_H Position */ +#define SCT_CAP8_CAP_H_Msk (0x0000ffffUL << SCT_CAP8_CAP_H_Pos) /*!< SCT CAP8: CAP_H Mask */ + +/* --------------------------------- SCT_MATCH8 --------------------------------- */ +#define SCT_MATCH8_MATCH_L_Pos 0 /*!< SCT MATCH8: MATCH_L Position */ +#define SCT_MATCH8_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH8_MATCH_L_Pos) /*!< SCT MATCH8: MATCH_L Mask */ +#define SCT_MATCH8_MATCH_H_Pos 16 /*!< SCT MATCH8: MATCH_H Position */ +#define SCT_MATCH8_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH8_MATCH_H_Pos) /*!< SCT MATCH8: MATCH_H Mask */ + +/* ---------------------------------- SCT_CAP9 ---------------------------------- */ +#define SCT_CAP9_CAP_L_Pos 0 /*!< SCT CAP9: CAP_L Position */ +#define SCT_CAP9_CAP_L_Msk (0x0000ffffUL << SCT_CAP9_CAP_L_Pos) /*!< SCT CAP9: CAP_L Mask */ +#define SCT_CAP9_CAP_H_Pos 16 /*!< SCT CAP9: CAP_H Position */ +#define SCT_CAP9_CAP_H_Msk (0x0000ffffUL << SCT_CAP9_CAP_H_Pos) /*!< SCT CAP9: CAP_H Mask */ + +/* --------------------------------- SCT_MATCH9 --------------------------------- */ +#define SCT_MATCH9_MATCH_L_Pos 0 /*!< SCT MATCH9: MATCH_L Position */ +#define SCT_MATCH9_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH9_MATCH_L_Pos) /*!< SCT MATCH9: MATCH_L Mask */ +#define SCT_MATCH9_MATCH_H_Pos 16 /*!< SCT MATCH9: MATCH_H Position */ +#define SCT_MATCH9_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH9_MATCH_H_Pos) /*!< SCT MATCH9: MATCH_H Mask */ + +/* ---------------------------------- SCT_CAP10 --------------------------------- */ +#define SCT_CAP10_CAP_L_Pos 0 /*!< SCT CAP10: CAP_L Position */ +#define SCT_CAP10_CAP_L_Msk (0x0000ffffUL << SCT_CAP10_CAP_L_Pos) /*!< SCT CAP10: CAP_L Mask */ +#define SCT_CAP10_CAP_H_Pos 16 /*!< SCT CAP10: CAP_H Position */ +#define SCT_CAP10_CAP_H_Msk (0x0000ffffUL << SCT_CAP10_CAP_H_Pos) /*!< SCT CAP10: CAP_H Mask */ + +/* --------------------------------- SCT_MATCH10 -------------------------------- */ +#define SCT_MATCH10_MATCH_L_Pos 0 /*!< SCT MATCH10: MATCH_L Position */ +#define SCT_MATCH10_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH10_MATCH_L_Pos) /*!< SCT MATCH10: MATCH_L Mask */ +#define SCT_MATCH10_MATCH_H_Pos 16 /*!< SCT MATCH10: MATCH_H Position */ +#define SCT_MATCH10_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH10_MATCH_H_Pos) /*!< SCT MATCH10: MATCH_H Mask */ + +/* ---------------------------------- SCT_CAP11 --------------------------------- */ +#define SCT_CAP11_CAP_L_Pos 0 /*!< SCT CAP11: CAP_L Position */ +#define SCT_CAP11_CAP_L_Msk (0x0000ffffUL << SCT_CAP11_CAP_L_Pos) /*!< SCT CAP11: CAP_L Mask */ +#define SCT_CAP11_CAP_H_Pos 16 /*!< SCT CAP11: CAP_H Position */ +#define SCT_CAP11_CAP_H_Msk (0x0000ffffUL << SCT_CAP11_CAP_H_Pos) /*!< SCT CAP11: CAP_H Mask */ + +/* --------------------------------- SCT_MATCH11 -------------------------------- */ +#define SCT_MATCH11_MATCH_L_Pos 0 /*!< SCT MATCH11: MATCH_L Position */ +#define SCT_MATCH11_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH11_MATCH_L_Pos) /*!< SCT MATCH11: MATCH_L Mask */ +#define SCT_MATCH11_MATCH_H_Pos 16 /*!< SCT MATCH11: MATCH_H Position */ +#define SCT_MATCH11_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH11_MATCH_H_Pos) /*!< SCT MATCH11: MATCH_H Mask */ + +/* ---------------------------------- SCT_CAP12 --------------------------------- */ +#define SCT_CAP12_CAP_L_Pos 0 /*!< SCT CAP12: CAP_L Position */ +#define SCT_CAP12_CAP_L_Msk (0x0000ffffUL << SCT_CAP12_CAP_L_Pos) /*!< SCT CAP12: CAP_L Mask */ +#define SCT_CAP12_CAP_H_Pos 16 /*!< SCT CAP12: CAP_H Position */ +#define SCT_CAP12_CAP_H_Msk (0x0000ffffUL << SCT_CAP12_CAP_H_Pos) /*!< SCT CAP12: CAP_H Mask */ + +/* --------------------------------- SCT_MATCH12 -------------------------------- */ +#define SCT_MATCH12_MATCH_L_Pos 0 /*!< SCT MATCH12: MATCH_L Position */ +#define SCT_MATCH12_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH12_MATCH_L_Pos) /*!< SCT MATCH12: MATCH_L Mask */ +#define SCT_MATCH12_MATCH_H_Pos 16 /*!< SCT MATCH12: MATCH_H Position */ +#define SCT_MATCH12_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH12_MATCH_H_Pos) /*!< SCT MATCH12: MATCH_H Mask */ + +/* --------------------------------- SCT_MATCH13 -------------------------------- */ +#define SCT_MATCH13_MATCH_L_Pos 0 /*!< SCT MATCH13: MATCH_L Position */ +#define SCT_MATCH13_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH13_MATCH_L_Pos) /*!< SCT MATCH13: MATCH_L Mask */ +#define SCT_MATCH13_MATCH_H_Pos 16 /*!< SCT MATCH13: MATCH_H Position */ +#define SCT_MATCH13_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH13_MATCH_H_Pos) /*!< SCT MATCH13: MATCH_H Mask */ + +/* ---------------------------------- SCT_CAP13 --------------------------------- */ +#define SCT_CAP13_CAP_L_Pos 0 /*!< SCT CAP13: CAP_L Position */ +#define SCT_CAP13_CAP_L_Msk (0x0000ffffUL << SCT_CAP13_CAP_L_Pos) /*!< SCT CAP13: CAP_L Mask */ +#define SCT_CAP13_CAP_H_Pos 16 /*!< SCT CAP13: CAP_H Position */ +#define SCT_CAP13_CAP_H_Msk (0x0000ffffUL << SCT_CAP13_CAP_H_Pos) /*!< SCT CAP13: CAP_H Mask */ + +/* ---------------------------------- SCT_CAP14 --------------------------------- */ +#define SCT_CAP14_CAP_L_Pos 0 /*!< SCT CAP14: CAP_L Position */ +#define SCT_CAP14_CAP_L_Msk (0x0000ffffUL << SCT_CAP14_CAP_L_Pos) /*!< SCT CAP14: CAP_L Mask */ +#define SCT_CAP14_CAP_H_Pos 16 /*!< SCT CAP14: CAP_H Position */ +#define SCT_CAP14_CAP_H_Msk (0x0000ffffUL << SCT_CAP14_CAP_H_Pos) /*!< SCT CAP14: CAP_H Mask */ + +/* --------------------------------- SCT_MATCH14 -------------------------------- */ +#define SCT_MATCH14_MATCH_L_Pos 0 /*!< SCT MATCH14: MATCH_L Position */ +#define SCT_MATCH14_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH14_MATCH_L_Pos) /*!< SCT MATCH14: MATCH_L Mask */ +#define SCT_MATCH14_MATCH_H_Pos 16 /*!< SCT MATCH14: MATCH_H Position */ +#define SCT_MATCH14_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH14_MATCH_H_Pos) /*!< SCT MATCH14: MATCH_H Mask */ + +/* --------------------------------- SCT_MATCH15 -------------------------------- */ +#define SCT_MATCH15_MATCH_L_Pos 0 /*!< SCT MATCH15: MATCH_L Position */ +#define SCT_MATCH15_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH15_MATCH_L_Pos) /*!< SCT MATCH15: MATCH_L Mask */ +#define SCT_MATCH15_MATCH_H_Pos 16 /*!< SCT MATCH15: MATCH_H Position */ +#define SCT_MATCH15_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH15_MATCH_H_Pos) /*!< SCT MATCH15: MATCH_H Mask */ + +/* ---------------------------------- SCT_CAP15 --------------------------------- */ +#define SCT_CAP15_CAP_L_Pos 0 /*!< SCT CAP15: CAP_L Position */ +#define SCT_CAP15_CAP_L_Msk (0x0000ffffUL << SCT_CAP15_CAP_L_Pos) /*!< SCT CAP15: CAP_L Mask */ +#define SCT_CAP15_CAP_H_Pos 16 /*!< SCT CAP15: CAP_H Position */ +#define SCT_CAP15_CAP_H_Msk (0x0000ffffUL << SCT_CAP15_CAP_H_Pos) /*!< SCT CAP15: CAP_H Mask */ + +/* -------------------------------- SCT_FRACMAT0 -------------------------------- */ +#define SCT_FRACMAT0_FRACMAT_L_Pos 0 /*!< SCT FRACMAT0: FRACMAT_L Position */ +#define SCT_FRACMAT0_FRACMAT_L_Msk (0x0fUL << SCT_FRACMAT0_FRACMAT_L_Pos) /*!< SCT FRACMAT0: FRACMAT_L Mask */ +#define SCT_FRACMAT0_FRACMAT_H_Pos 16 /*!< SCT FRACMAT0: FRACMAT_H Position */ +#define SCT_FRACMAT0_FRACMAT_H_Msk (0x0fUL << SCT_FRACMAT0_FRACMAT_H_Pos) /*!< SCT FRACMAT0: FRACMAT_H Mask */ + +/* -------------------------------- SCT_FRACMAT1 -------------------------------- */ +#define SCT_FRACMAT1_FRACMAT_L_Pos 0 /*!< SCT FRACMAT1: FRACMAT_L Position */ +#define SCT_FRACMAT1_FRACMAT_L_Msk (0x0fUL << SCT_FRACMAT1_FRACMAT_L_Pos) /*!< SCT FRACMAT1: FRACMAT_L Mask */ +#define SCT_FRACMAT1_FRACMAT_H_Pos 16 /*!< SCT FRACMAT1: FRACMAT_H Position */ +#define SCT_FRACMAT1_FRACMAT_H_Msk (0x0fUL << SCT_FRACMAT1_FRACMAT_H_Pos) /*!< SCT FRACMAT1: FRACMAT_H Mask */ + +/* -------------------------------- SCT_FRACMAT2 -------------------------------- */ +#define SCT_FRACMAT2_FRACMAT_L_Pos 0 /*!< SCT FRACMAT2: FRACMAT_L Position */ +#define SCT_FRACMAT2_FRACMAT_L_Msk (0x0fUL << SCT_FRACMAT2_FRACMAT_L_Pos) /*!< SCT FRACMAT2: FRACMAT_L Mask */ +#define SCT_FRACMAT2_FRACMAT_H_Pos 16 /*!< SCT FRACMAT2: FRACMAT_H Position */ +#define SCT_FRACMAT2_FRACMAT_H_Msk (0x0fUL << SCT_FRACMAT2_FRACMAT_H_Pos) /*!< SCT FRACMAT2: FRACMAT_H Mask */ + +/* -------------------------------- SCT_FRACMAT3 -------------------------------- */ +#define SCT_FRACMAT3_FRACMAT_L_Pos 0 /*!< SCT FRACMAT3: FRACMAT_L Position */ +#define SCT_FRACMAT3_FRACMAT_L_Msk (0x0fUL << SCT_FRACMAT3_FRACMAT_L_Pos) /*!< SCT FRACMAT3: FRACMAT_L Mask */ +#define SCT_FRACMAT3_FRACMAT_H_Pos 16 /*!< SCT FRACMAT3: FRACMAT_H Position */ +#define SCT_FRACMAT3_FRACMAT_H_Msk (0x0fUL << SCT_FRACMAT3_FRACMAT_H_Pos) /*!< SCT FRACMAT3: FRACMAT_H Mask */ + +/* -------------------------------- SCT_FRACMAT4 -------------------------------- */ +#define SCT_FRACMAT4_FRACMAT_L_Pos 0 /*!< SCT FRACMAT4: FRACMAT_L Position */ +#define SCT_FRACMAT4_FRACMAT_L_Msk (0x0fUL << SCT_FRACMAT4_FRACMAT_L_Pos) /*!< SCT FRACMAT4: FRACMAT_L Mask */ +#define SCT_FRACMAT4_FRACMAT_H_Pos 16 /*!< SCT FRACMAT4: FRACMAT_H Position */ +#define SCT_FRACMAT4_FRACMAT_H_Msk (0x0fUL << SCT_FRACMAT4_FRACMAT_H_Pos) /*!< SCT FRACMAT4: FRACMAT_H Mask */ + +/* -------------------------------- SCT_FRACMAT5 -------------------------------- */ +#define SCT_FRACMAT5_FRACMAT_L_Pos 0 /*!< SCT FRACMAT5: FRACMAT_L Position */ +#define SCT_FRACMAT5_FRACMAT_L_Msk (0x0fUL << SCT_FRACMAT5_FRACMAT_L_Pos) /*!< SCT FRACMAT5: FRACMAT_L Mask */ +#define SCT_FRACMAT5_FRACMAT_H_Pos 16 /*!< SCT FRACMAT5: FRACMAT_H Position */ +#define SCT_FRACMAT5_FRACMAT_H_Msk (0x0fUL << SCT_FRACMAT5_FRACMAT_H_Pos) /*!< SCT FRACMAT5: FRACMAT_H Mask */ + +/* -------------------------------- SCT_MATCHREL0 ------------------------------- */ +#define SCT_MATCHREL0_RELOAD_L_Pos 0 /*!< SCT MATCHREL0: RELOAD_L Position */ +#define SCT_MATCHREL0_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL0_RELOAD_L_Pos) /*!< SCT MATCHREL0: RELOAD_L Mask */ +#define SCT_MATCHREL0_RELOAD_H_Pos 16 /*!< SCT MATCHREL0: RELOAD_H Position */ +#define SCT_MATCHREL0_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL0_RELOAD_H_Pos) /*!< SCT MATCHREL0: RELOAD_H Mask */ + +/* -------------------------------- SCT_CAPCTRL0 -------------------------------- */ +#define SCT_CAPCTRL0_CAPCON_L_Pos 0 /*!< SCT CAPCTRL0: CAPCON_L Position */ +#define SCT_CAPCTRL0_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL0_CAPCON_L_Pos) /*!< SCT CAPCTRL0: CAPCON_L Mask */ +#define SCT_CAPCTRL0_CAPCON_H_Pos 16 /*!< SCT CAPCTRL0: CAPCON_H Position */ +#define SCT_CAPCTRL0_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL0_CAPCON_H_Pos) /*!< SCT CAPCTRL0: CAPCON_H Mask */ + +/* -------------------------------- SCT_CAPCTRL1 -------------------------------- */ +#define SCT_CAPCTRL1_CAPCON_L_Pos 0 /*!< SCT CAPCTRL1: CAPCON_L Position */ +#define SCT_CAPCTRL1_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL1_CAPCON_L_Pos) /*!< SCT CAPCTRL1: CAPCON_L Mask */ +#define SCT_CAPCTRL1_CAPCON_H_Pos 16 /*!< SCT CAPCTRL1: CAPCON_H Position */ +#define SCT_CAPCTRL1_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL1_CAPCON_H_Pos) /*!< SCT CAPCTRL1: CAPCON_H Mask */ + +/* -------------------------------- SCT_MATCHREL1 ------------------------------- */ +#define SCT_MATCHREL1_RELOAD_L_Pos 0 /*!< SCT MATCHREL1: RELOAD_L Position */ +#define SCT_MATCHREL1_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL1_RELOAD_L_Pos) /*!< SCT MATCHREL1: RELOAD_L Mask */ +#define SCT_MATCHREL1_RELOAD_H_Pos 16 /*!< SCT MATCHREL1: RELOAD_H Position */ +#define SCT_MATCHREL1_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL1_RELOAD_H_Pos) /*!< SCT MATCHREL1: RELOAD_H Mask */ + +/* -------------------------------- SCT_MATCHREL2 ------------------------------- */ +#define SCT_MATCHREL2_RELOAD_L_Pos 0 /*!< SCT MATCHREL2: RELOAD_L Position */ +#define SCT_MATCHREL2_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL2_RELOAD_L_Pos) /*!< SCT MATCHREL2: RELOAD_L Mask */ +#define SCT_MATCHREL2_RELOAD_H_Pos 16 /*!< SCT MATCHREL2: RELOAD_H Position */ +#define SCT_MATCHREL2_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL2_RELOAD_H_Pos) /*!< SCT MATCHREL2: RELOAD_H Mask */ + +/* -------------------------------- SCT_CAPCTRL2 -------------------------------- */ +#define SCT_CAPCTRL2_CAPCON_L_Pos 0 /*!< SCT CAPCTRL2: CAPCON_L Position */ +#define SCT_CAPCTRL2_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL2_CAPCON_L_Pos) /*!< SCT CAPCTRL2: CAPCON_L Mask */ +#define SCT_CAPCTRL2_CAPCON_H_Pos 16 /*!< SCT CAPCTRL2: CAPCON_H Position */ +#define SCT_CAPCTRL2_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL2_CAPCON_H_Pos) /*!< SCT CAPCTRL2: CAPCON_H Mask */ + +/* -------------------------------- SCT_CAPCTRL3 -------------------------------- */ +#define SCT_CAPCTRL3_CAPCON_L_Pos 0 /*!< SCT CAPCTRL3: CAPCON_L Position */ +#define SCT_CAPCTRL3_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL3_CAPCON_L_Pos) /*!< SCT CAPCTRL3: CAPCON_L Mask */ +#define SCT_CAPCTRL3_CAPCON_H_Pos 16 /*!< SCT CAPCTRL3: CAPCON_H Position */ +#define SCT_CAPCTRL3_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL3_CAPCON_H_Pos) /*!< SCT CAPCTRL3: CAPCON_H Mask */ + +/* -------------------------------- SCT_MATCHREL3 ------------------------------- */ +#define SCT_MATCHREL3_RELOAD_L_Pos 0 /*!< SCT MATCHREL3: RELOAD_L Position */ +#define SCT_MATCHREL3_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL3_RELOAD_L_Pos) /*!< SCT MATCHREL3: RELOAD_L Mask */ +#define SCT_MATCHREL3_RELOAD_H_Pos 16 /*!< SCT MATCHREL3: RELOAD_H Position */ +#define SCT_MATCHREL3_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL3_RELOAD_H_Pos) /*!< SCT MATCHREL3: RELOAD_H Mask */ + +/* -------------------------------- SCT_MATCHREL4 ------------------------------- */ +#define SCT_MATCHREL4_RELOAD_L_Pos 0 /*!< SCT MATCHREL4: RELOAD_L Position */ +#define SCT_MATCHREL4_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL4_RELOAD_L_Pos) /*!< SCT MATCHREL4: RELOAD_L Mask */ +#define SCT_MATCHREL4_RELOAD_H_Pos 16 /*!< SCT MATCHREL4: RELOAD_H Position */ +#define SCT_MATCHREL4_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL4_RELOAD_H_Pos) /*!< SCT MATCHREL4: RELOAD_H Mask */ + +/* -------------------------------- SCT_CAPCTRL4 -------------------------------- */ +#define SCT_CAPCTRL4_CAPCON_L_Pos 0 /*!< SCT CAPCTRL4: CAPCON_L Position */ +#define SCT_CAPCTRL4_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL4_CAPCON_L_Pos) /*!< SCT CAPCTRL4: CAPCON_L Mask */ +#define SCT_CAPCTRL4_CAPCON_H_Pos 16 /*!< SCT CAPCTRL4: CAPCON_H Position */ +#define SCT_CAPCTRL4_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL4_CAPCON_H_Pos) /*!< SCT CAPCTRL4: CAPCON_H Mask */ + +/* -------------------------------- SCT_MATCHREL5 ------------------------------- */ +#define SCT_MATCHREL5_RELOAD_L_Pos 0 /*!< SCT MATCHREL5: RELOAD_L Position */ +#define SCT_MATCHREL5_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL5_RELOAD_L_Pos) /*!< SCT MATCHREL5: RELOAD_L Mask */ +#define SCT_MATCHREL5_RELOAD_H_Pos 16 /*!< SCT MATCHREL5: RELOAD_H Position */ +#define SCT_MATCHREL5_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL5_RELOAD_H_Pos) /*!< SCT MATCHREL5: RELOAD_H Mask */ + +/* -------------------------------- SCT_CAPCTRL5 -------------------------------- */ +#define SCT_CAPCTRL5_CAPCON_L_Pos 0 /*!< SCT CAPCTRL5: CAPCON_L Position */ +#define SCT_CAPCTRL5_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL5_CAPCON_L_Pos) /*!< SCT CAPCTRL5: CAPCON_L Mask */ +#define SCT_CAPCTRL5_CAPCON_H_Pos 16 /*!< SCT CAPCTRL5: CAPCON_H Position */ +#define SCT_CAPCTRL5_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL5_CAPCON_H_Pos) /*!< SCT CAPCTRL5: CAPCON_H Mask */ + +/* -------------------------------- SCT_CAPCTRL6 -------------------------------- */ +#define SCT_CAPCTRL6_CAPCON_L_Pos 0 /*!< SCT CAPCTRL6: CAPCON_L Position */ +#define SCT_CAPCTRL6_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL6_CAPCON_L_Pos) /*!< SCT CAPCTRL6: CAPCON_L Mask */ +#define SCT_CAPCTRL6_CAPCON_H_Pos 16 /*!< SCT CAPCTRL6: CAPCON_H Position */ +#define SCT_CAPCTRL6_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL6_CAPCON_H_Pos) /*!< SCT CAPCTRL6: CAPCON_H Mask */ + +/* -------------------------------- SCT_MATCHREL6 ------------------------------- */ +#define SCT_MATCHREL6_RELOAD_L_Pos 0 /*!< SCT MATCHREL6: RELOAD_L Position */ +#define SCT_MATCHREL6_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL6_RELOAD_L_Pos) /*!< SCT MATCHREL6: RELOAD_L Mask */ +#define SCT_MATCHREL6_RELOAD_H_Pos 16 /*!< SCT MATCHREL6: RELOAD_H Position */ +#define SCT_MATCHREL6_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL6_RELOAD_H_Pos) /*!< SCT MATCHREL6: RELOAD_H Mask */ + +/* -------------------------------- SCT_MATCHREL7 ------------------------------- */ +#define SCT_MATCHREL7_RELOAD_L_Pos 0 /*!< SCT MATCHREL7: RELOAD_L Position */ +#define SCT_MATCHREL7_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL7_RELOAD_L_Pos) /*!< SCT MATCHREL7: RELOAD_L Mask */ +#define SCT_MATCHREL7_RELOAD_H_Pos 16 /*!< SCT MATCHREL7: RELOAD_H Position */ +#define SCT_MATCHREL7_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL7_RELOAD_H_Pos) /*!< SCT MATCHREL7: RELOAD_H Mask */ + +/* -------------------------------- SCT_CAPCTRL7 -------------------------------- */ +#define SCT_CAPCTRL7_CAPCON_L_Pos 0 /*!< SCT CAPCTRL7: CAPCON_L Position */ +#define SCT_CAPCTRL7_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL7_CAPCON_L_Pos) /*!< SCT CAPCTRL7: CAPCON_L Mask */ +#define SCT_CAPCTRL7_CAPCON_H_Pos 16 /*!< SCT CAPCTRL7: CAPCON_H Position */ +#define SCT_CAPCTRL7_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL7_CAPCON_H_Pos) /*!< SCT CAPCTRL7: CAPCON_H Mask */ + +/* -------------------------------- SCT_CAPCTRL8 -------------------------------- */ +#define SCT_CAPCTRL8_CAPCON_L_Pos 0 /*!< SCT CAPCTRL8: CAPCON_L Position */ +#define SCT_CAPCTRL8_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL8_CAPCON_L_Pos) /*!< SCT CAPCTRL8: CAPCON_L Mask */ +#define SCT_CAPCTRL8_CAPCON_H_Pos 16 /*!< SCT CAPCTRL8: CAPCON_H Position */ +#define SCT_CAPCTRL8_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL8_CAPCON_H_Pos) /*!< SCT CAPCTRL8: CAPCON_H Mask */ + +/* -------------------------------- SCT_MATCHREL8 ------------------------------- */ +#define SCT_MATCHREL8_RELOAD_L_Pos 0 /*!< SCT MATCHREL8: RELOAD_L Position */ +#define SCT_MATCHREL8_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL8_RELOAD_L_Pos) /*!< SCT MATCHREL8: RELOAD_L Mask */ +#define SCT_MATCHREL8_RELOAD_H_Pos 16 /*!< SCT MATCHREL8: RELOAD_H Position */ +#define SCT_MATCHREL8_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL8_RELOAD_H_Pos) /*!< SCT MATCHREL8: RELOAD_H Mask */ + +/* -------------------------------- SCT_MATCHREL9 ------------------------------- */ +#define SCT_MATCHREL9_RELOAD_L_Pos 0 /*!< SCT MATCHREL9: RELOAD_L Position */ +#define SCT_MATCHREL9_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL9_RELOAD_L_Pos) /*!< SCT MATCHREL9: RELOAD_L Mask */ +#define SCT_MATCHREL9_RELOAD_H_Pos 16 /*!< SCT MATCHREL9: RELOAD_H Position */ +#define SCT_MATCHREL9_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL9_RELOAD_H_Pos) /*!< SCT MATCHREL9: RELOAD_H Mask */ + +/* -------------------------------- SCT_CAPCTRL9 -------------------------------- */ +#define SCT_CAPCTRL9_CAPCON_L_Pos 0 /*!< SCT CAPCTRL9: CAPCON_L Position */ +#define SCT_CAPCTRL9_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL9_CAPCON_L_Pos) /*!< SCT CAPCTRL9: CAPCON_L Mask */ +#define SCT_CAPCTRL9_CAPCON_H_Pos 16 /*!< SCT CAPCTRL9: CAPCON_H Position */ +#define SCT_CAPCTRL9_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL9_CAPCON_H_Pos) /*!< SCT CAPCTRL9: CAPCON_H Mask */ + +/* -------------------------------- SCT_CAPCTRL10 ------------------------------- */ +#define SCT_CAPCTRL10_CAPCON_L_Pos 0 /*!< SCT CAPCTRL10: CAPCON_L Position */ +#define SCT_CAPCTRL10_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL10_CAPCON_L_Pos) /*!< SCT CAPCTRL10: CAPCON_L Mask */ +#define SCT_CAPCTRL10_CAPCON_H_Pos 16 /*!< SCT CAPCTRL10: CAPCON_H Position */ +#define SCT_CAPCTRL10_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL10_CAPCON_H_Pos) /*!< SCT CAPCTRL10: CAPCON_H Mask */ + +/* ------------------------------- SCT_MATCHREL10 ------------------------------- */ +#define SCT_MATCHREL10_RELOAD_L_Pos 0 /*!< SCT MATCHREL10: RELOAD_L Position */ +#define SCT_MATCHREL10_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL10_RELOAD_L_Pos) /*!< SCT MATCHREL10: RELOAD_L Mask */ +#define SCT_MATCHREL10_RELOAD_H_Pos 16 /*!< SCT MATCHREL10: RELOAD_H Position */ +#define SCT_MATCHREL10_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL10_RELOAD_H_Pos) /*!< SCT MATCHREL10: RELOAD_H Mask */ + +/* -------------------------------- SCT_CAPCTRL11 ------------------------------- */ +#define SCT_CAPCTRL11_CAPCON_L_Pos 0 /*!< SCT CAPCTRL11: CAPCON_L Position */ +#define SCT_CAPCTRL11_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL11_CAPCON_L_Pos) /*!< SCT CAPCTRL11: CAPCON_L Mask */ +#define SCT_CAPCTRL11_CAPCON_H_Pos 16 /*!< SCT CAPCTRL11: CAPCON_H Position */ +#define SCT_CAPCTRL11_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL11_CAPCON_H_Pos) /*!< SCT CAPCTRL11: CAPCON_H Mask */ + +/* ------------------------------- SCT_MATCHREL11 ------------------------------- */ +#define SCT_MATCHREL11_RELOAD_L_Pos 0 /*!< SCT MATCHREL11: RELOAD_L Position */ +#define SCT_MATCHREL11_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL11_RELOAD_L_Pos) /*!< SCT MATCHREL11: RELOAD_L Mask */ +#define SCT_MATCHREL11_RELOAD_H_Pos 16 /*!< SCT MATCHREL11: RELOAD_H Position */ +#define SCT_MATCHREL11_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL11_RELOAD_H_Pos) /*!< SCT MATCHREL11: RELOAD_H Mask */ + +/* -------------------------------- SCT_CAPCTRL12 ------------------------------- */ +#define SCT_CAPCTRL12_CAPCON_L_Pos 0 /*!< SCT CAPCTRL12: CAPCON_L Position */ +#define SCT_CAPCTRL12_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL12_CAPCON_L_Pos) /*!< SCT CAPCTRL12: CAPCON_L Mask */ +#define SCT_CAPCTRL12_CAPCON_H_Pos 16 /*!< SCT CAPCTRL12: CAPCON_H Position */ +#define SCT_CAPCTRL12_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL12_CAPCON_H_Pos) /*!< SCT CAPCTRL12: CAPCON_H Mask */ + +/* ------------------------------- SCT_MATCHREL12 ------------------------------- */ +#define SCT_MATCHREL12_RELOAD_L_Pos 0 /*!< SCT MATCHREL12: RELOAD_L Position */ +#define SCT_MATCHREL12_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL12_RELOAD_L_Pos) /*!< SCT MATCHREL12: RELOAD_L Mask */ +#define SCT_MATCHREL12_RELOAD_H_Pos 16 /*!< SCT MATCHREL12: RELOAD_H Position */ +#define SCT_MATCHREL12_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL12_RELOAD_H_Pos) /*!< SCT MATCHREL12: RELOAD_H Mask */ + +/* ------------------------------- SCT_MATCHREL13 ------------------------------- */ +#define SCT_MATCHREL13_RELOAD_L_Pos 0 /*!< SCT MATCHREL13: RELOAD_L Position */ +#define SCT_MATCHREL13_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL13_RELOAD_L_Pos) /*!< SCT MATCHREL13: RELOAD_L Mask */ +#define SCT_MATCHREL13_RELOAD_H_Pos 16 /*!< SCT MATCHREL13: RELOAD_H Position */ +#define SCT_MATCHREL13_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL13_RELOAD_H_Pos) /*!< SCT MATCHREL13: RELOAD_H Mask */ + +/* -------------------------------- SCT_CAPCTRL13 ------------------------------- */ +#define SCT_CAPCTRL13_CAPCON_L_Pos 0 /*!< SCT CAPCTRL13: CAPCON_L Position */ +#define SCT_CAPCTRL13_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL13_CAPCON_L_Pos) /*!< SCT CAPCTRL13: CAPCON_L Mask */ +#define SCT_CAPCTRL13_CAPCON_H_Pos 16 /*!< SCT CAPCTRL13: CAPCON_H Position */ +#define SCT_CAPCTRL13_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL13_CAPCON_H_Pos) /*!< SCT CAPCTRL13: CAPCON_H Mask */ + +/* ------------------------------- SCT_MATCHREL14 ------------------------------- */ +#define SCT_MATCHREL14_RELOAD_L_Pos 0 /*!< SCT MATCHREL14: RELOAD_L Position */ +#define SCT_MATCHREL14_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL14_RELOAD_L_Pos) /*!< SCT MATCHREL14: RELOAD_L Mask */ +#define SCT_MATCHREL14_RELOAD_H_Pos 16 /*!< SCT MATCHREL14: RELOAD_H Position */ +#define SCT_MATCHREL14_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL14_RELOAD_H_Pos) /*!< SCT MATCHREL14: RELOAD_H Mask */ + +/* -------------------------------- SCT_CAPCTRL14 ------------------------------- */ +#define SCT_CAPCTRL14_CAPCON_L_Pos 0 /*!< SCT CAPCTRL14: CAPCON_L Position */ +#define SCT_CAPCTRL14_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL14_CAPCON_L_Pos) /*!< SCT CAPCTRL14: CAPCON_L Mask */ +#define SCT_CAPCTRL14_CAPCON_H_Pos 16 /*!< SCT CAPCTRL14: CAPCON_H Position */ +#define SCT_CAPCTRL14_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL14_CAPCON_H_Pos) /*!< SCT CAPCTRL14: CAPCON_H Mask */ + +/* ------------------------------- SCT_MATCHREL15 ------------------------------- */ +#define SCT_MATCHREL15_RELOAD_L_Pos 0 /*!< SCT MATCHREL15: RELOAD_L Position */ +#define SCT_MATCHREL15_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL15_RELOAD_L_Pos) /*!< SCT MATCHREL15: RELOAD_L Mask */ +#define SCT_MATCHREL15_RELOAD_H_Pos 16 /*!< SCT MATCHREL15: RELOAD_H Position */ +#define SCT_MATCHREL15_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL15_RELOAD_H_Pos) /*!< SCT MATCHREL15: RELOAD_H Mask */ + +/* -------------------------------- SCT_CAPCTRL15 ------------------------------- */ +#define SCT_CAPCTRL15_CAPCON_L_Pos 0 /*!< SCT CAPCTRL15: CAPCON_L Position */ +#define SCT_CAPCTRL15_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL15_CAPCON_L_Pos) /*!< SCT CAPCTRL15: CAPCON_L Mask */ +#define SCT_CAPCTRL15_CAPCON_H_Pos 16 /*!< SCT CAPCTRL15: CAPCON_H Position */ +#define SCT_CAPCTRL15_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL15_CAPCON_H_Pos) /*!< SCT CAPCTRL15: CAPCON_H Mask */ + +/* ------------------------------- SCT_FRACMATREL0 ------------------------------ */ +#define SCT_FRACMATREL0_RELFRAC_L_Pos 0 /*!< SCT FRACMATREL0: RELFRAC_L Position */ +#define SCT_FRACMATREL0_RELFRAC_L_Msk (0x0fUL << SCT_FRACMATREL0_RELFRAC_L_Pos) /*!< SCT FRACMATREL0: RELFRAC_L Mask */ +#define SCT_FRACMATREL0_RELFRAC_H_Pos 16 /*!< SCT FRACMATREL0: RELFRAC_H Position */ +#define SCT_FRACMATREL0_RELFRAC_H_Msk (0x0fUL << SCT_FRACMATREL0_RELFRAC_H_Pos) /*!< SCT FRACMATREL0: RELFRAC_H Mask */ + +/* ------------------------------- SCT_FRACMATREL1 ------------------------------ */ +#define SCT_FRACMATREL1_RELFRAC_L_Pos 0 /*!< SCT FRACMATREL1: RELFRAC_L Position */ +#define SCT_FRACMATREL1_RELFRAC_L_Msk (0x0fUL << SCT_FRACMATREL1_RELFRAC_L_Pos) /*!< SCT FRACMATREL1: RELFRAC_L Mask */ +#define SCT_FRACMATREL1_RELFRAC_H_Pos 16 /*!< SCT FRACMATREL1: RELFRAC_H Position */ +#define SCT_FRACMATREL1_RELFRAC_H_Msk (0x0fUL << SCT_FRACMATREL1_RELFRAC_H_Pos) /*!< SCT FRACMATREL1: RELFRAC_H Mask */ + +/* ------------------------------- SCT_FRACMATREL2 ------------------------------ */ +#define SCT_FRACMATREL2_RELFRAC_L_Pos 0 /*!< SCT FRACMATREL2: RELFRAC_L Position */ +#define SCT_FRACMATREL2_RELFRAC_L_Msk (0x0fUL << SCT_FRACMATREL2_RELFRAC_L_Pos) /*!< SCT FRACMATREL2: RELFRAC_L Mask */ +#define SCT_FRACMATREL2_RELFRAC_H_Pos 16 /*!< SCT FRACMATREL2: RELFRAC_H Position */ +#define SCT_FRACMATREL2_RELFRAC_H_Msk (0x0fUL << SCT_FRACMATREL2_RELFRAC_H_Pos) /*!< SCT FRACMATREL2: RELFRAC_H Mask */ + +/* ------------------------------- SCT_FRACMATREL3 ------------------------------ */ +#define SCT_FRACMATREL3_RELFRAC_L_Pos 0 /*!< SCT FRACMATREL3: RELFRAC_L Position */ +#define SCT_FRACMATREL3_RELFRAC_L_Msk (0x0fUL << SCT_FRACMATREL3_RELFRAC_L_Pos) /*!< SCT FRACMATREL3: RELFRAC_L Mask */ +#define SCT_FRACMATREL3_RELFRAC_H_Pos 16 /*!< SCT FRACMATREL3: RELFRAC_H Position */ +#define SCT_FRACMATREL3_RELFRAC_H_Msk (0x0fUL << SCT_FRACMATREL3_RELFRAC_H_Pos) /*!< SCT FRACMATREL3: RELFRAC_H Mask */ + +/* ------------------------------- SCT_FRACMATREL4 ------------------------------ */ +#define SCT_FRACMATREL4_RELFRAC_L_Pos 0 /*!< SCT FRACMATREL4: RELFRAC_L Position */ +#define SCT_FRACMATREL4_RELFRAC_L_Msk (0x0fUL << SCT_FRACMATREL4_RELFRAC_L_Pos) /*!< SCT FRACMATREL4: RELFRAC_L Mask */ +#define SCT_FRACMATREL4_RELFRAC_H_Pos 16 /*!< SCT FRACMATREL4: RELFRAC_H Position */ +#define SCT_FRACMATREL4_RELFRAC_H_Msk (0x0fUL << SCT_FRACMATREL4_RELFRAC_H_Pos) /*!< SCT FRACMATREL4: RELFRAC_H Mask */ + +/* ------------------------------- SCT_FRACMATREL5 ------------------------------ */ +#define SCT_FRACMATREL5_RELFRAC_L_Pos 0 /*!< SCT FRACMATREL5: RELFRAC_L Position */ +#define SCT_FRACMATREL5_RELFRAC_L_Msk (0x0fUL << SCT_FRACMATREL5_RELFRAC_L_Pos) /*!< SCT FRACMATREL5: RELFRAC_L Mask */ +#define SCT_FRACMATREL5_RELFRAC_H_Pos 16 /*!< SCT FRACMATREL5: RELFRAC_H Position */ +#define SCT_FRACMATREL5_RELFRAC_H_Msk (0x0fUL << SCT_FRACMATREL5_RELFRAC_H_Pos) /*!< SCT FRACMATREL5: RELFRAC_H Mask */ + +/* -------------------------------- SCT_EV0_STATE ------------------------------- */ +#define SCT_EV0_STATE_STATEMSK0_Pos 0 /*!< SCT EV0_STATE: STATEMSK0 Position */ +#define SCT_EV0_STATE_STATEMSK0_Msk (0x01UL << SCT_EV0_STATE_STATEMSK0_Pos) /*!< SCT EV0_STATE: STATEMSK0 Mask */ +#define SCT_EV0_STATE_STATEMSK1_Pos 1 /*!< SCT EV0_STATE: STATEMSK1 Position */ +#define SCT_EV0_STATE_STATEMSK1_Msk (0x01UL << SCT_EV0_STATE_STATEMSK1_Pos) /*!< SCT EV0_STATE: STATEMSK1 Mask */ +#define SCT_EV0_STATE_STATEMSK2_Pos 2 /*!< SCT EV0_STATE: STATEMSK2 Position */ +#define SCT_EV0_STATE_STATEMSK2_Msk (0x01UL << SCT_EV0_STATE_STATEMSK2_Pos) /*!< SCT EV0_STATE: STATEMSK2 Mask */ +#define SCT_EV0_STATE_STATEMSK3_Pos 3 /*!< SCT EV0_STATE: STATEMSK3 Position */ +#define SCT_EV0_STATE_STATEMSK3_Msk (0x01UL << SCT_EV0_STATE_STATEMSK3_Pos) /*!< SCT EV0_STATE: STATEMSK3 Mask */ +#define SCT_EV0_STATE_STATEMSK4_Pos 4 /*!< SCT EV0_STATE: STATEMSK4 Position */ +#define SCT_EV0_STATE_STATEMSK4_Msk (0x01UL << SCT_EV0_STATE_STATEMSK4_Pos) /*!< SCT EV0_STATE: STATEMSK4 Mask */ +#define SCT_EV0_STATE_STATEMSK5_Pos 5 /*!< SCT EV0_STATE: STATEMSK5 Position */ +#define SCT_EV0_STATE_STATEMSK5_Msk (0x01UL << SCT_EV0_STATE_STATEMSK5_Pos) /*!< SCT EV0_STATE: STATEMSK5 Mask */ +#define SCT_EV0_STATE_STATEMSK6_Pos 6 /*!< SCT EV0_STATE: STATEMSK6 Position */ +#define SCT_EV0_STATE_STATEMSK6_Msk (0x01UL << SCT_EV0_STATE_STATEMSK6_Pos) /*!< SCT EV0_STATE: STATEMSK6 Mask */ +#define SCT_EV0_STATE_STATEMSK7_Pos 7 /*!< SCT EV0_STATE: STATEMSK7 Position */ +#define SCT_EV0_STATE_STATEMSK7_Msk (0x01UL << SCT_EV0_STATE_STATEMSK7_Pos) /*!< SCT EV0_STATE: STATEMSK7 Mask */ +#define SCT_EV0_STATE_STATEMSK8_Pos 8 /*!< SCT EV0_STATE: STATEMSK8 Position */ +#define SCT_EV0_STATE_STATEMSK8_Msk (0x01UL << SCT_EV0_STATE_STATEMSK8_Pos) /*!< SCT EV0_STATE: STATEMSK8 Mask */ +#define SCT_EV0_STATE_STATEMSK9_Pos 9 /*!< SCT EV0_STATE: STATEMSK9 Position */ +#define SCT_EV0_STATE_STATEMSK9_Msk (0x01UL << SCT_EV0_STATE_STATEMSK9_Pos) /*!< SCT EV0_STATE: STATEMSK9 Mask */ +#define SCT_EV0_STATE_STATEMSK10_Pos 10 /*!< SCT EV0_STATE: STATEMSK10 Position */ +#define SCT_EV0_STATE_STATEMSK10_Msk (0x01UL << SCT_EV0_STATE_STATEMSK10_Pos) /*!< SCT EV0_STATE: STATEMSK10 Mask */ +#define SCT_EV0_STATE_STATEMSK11_Pos 11 /*!< SCT EV0_STATE: STATEMSK11 Position */ +#define SCT_EV0_STATE_STATEMSK11_Msk (0x01UL << SCT_EV0_STATE_STATEMSK11_Pos) /*!< SCT EV0_STATE: STATEMSK11 Mask */ +#define SCT_EV0_STATE_STATEMSK12_Pos 12 /*!< SCT EV0_STATE: STATEMSK12 Position */ +#define SCT_EV0_STATE_STATEMSK12_Msk (0x01UL << SCT_EV0_STATE_STATEMSK12_Pos) /*!< SCT EV0_STATE: STATEMSK12 Mask */ +#define SCT_EV0_STATE_STATEMSK13_Pos 13 /*!< SCT EV0_STATE: STATEMSK13 Position */ +#define SCT_EV0_STATE_STATEMSK13_Msk (0x01UL << SCT_EV0_STATE_STATEMSK13_Pos) /*!< SCT EV0_STATE: STATEMSK13 Mask */ +#define SCT_EV0_STATE_STATEMSK14_Pos 14 /*!< SCT EV0_STATE: STATEMSK14 Position */ +#define SCT_EV0_STATE_STATEMSK14_Msk (0x01UL << SCT_EV0_STATE_STATEMSK14_Pos) /*!< SCT EV0_STATE: STATEMSK14 Mask */ +#define SCT_EV0_STATE_STATEMSK15_Pos 15 /*!< SCT EV0_STATE: STATEMSK15 Position */ +#define SCT_EV0_STATE_STATEMSK15_Msk (0x01UL << SCT_EV0_STATE_STATEMSK15_Pos) /*!< SCT EV0_STATE: STATEMSK15 Mask */ +#define SCT_EV0_STATE_STATEMSK16_Pos 16 /*!< SCT EV0_STATE: STATEMSK16 Position */ +#define SCT_EV0_STATE_STATEMSK16_Msk (0x01UL << SCT_EV0_STATE_STATEMSK16_Pos) /*!< SCT EV0_STATE: STATEMSK16 Mask */ +#define SCT_EV0_STATE_STATEMSK17_Pos 17 /*!< SCT EV0_STATE: STATEMSK17 Position */ +#define SCT_EV0_STATE_STATEMSK17_Msk (0x01UL << SCT_EV0_STATE_STATEMSK17_Pos) /*!< SCT EV0_STATE: STATEMSK17 Mask */ +#define SCT_EV0_STATE_STATEMSK18_Pos 18 /*!< SCT EV0_STATE: STATEMSK18 Position */ +#define SCT_EV0_STATE_STATEMSK18_Msk (0x01UL << SCT_EV0_STATE_STATEMSK18_Pos) /*!< SCT EV0_STATE: STATEMSK18 Mask */ +#define SCT_EV0_STATE_STATEMSK19_Pos 19 /*!< SCT EV0_STATE: STATEMSK19 Position */ +#define SCT_EV0_STATE_STATEMSK19_Msk (0x01UL << SCT_EV0_STATE_STATEMSK19_Pos) /*!< SCT EV0_STATE: STATEMSK19 Mask */ +#define SCT_EV0_STATE_STATEMSK20_Pos 20 /*!< SCT EV0_STATE: STATEMSK20 Position */ +#define SCT_EV0_STATE_STATEMSK20_Msk (0x01UL << SCT_EV0_STATE_STATEMSK20_Pos) /*!< SCT EV0_STATE: STATEMSK20 Mask */ +#define SCT_EV0_STATE_STATEMSK21_Pos 21 /*!< SCT EV0_STATE: STATEMSK21 Position */ +#define SCT_EV0_STATE_STATEMSK21_Msk (0x01UL << SCT_EV0_STATE_STATEMSK21_Pos) /*!< SCT EV0_STATE: STATEMSK21 Mask */ +#define SCT_EV0_STATE_STATEMSK22_Pos 22 /*!< SCT EV0_STATE: STATEMSK22 Position */ +#define SCT_EV0_STATE_STATEMSK22_Msk (0x01UL << SCT_EV0_STATE_STATEMSK22_Pos) /*!< SCT EV0_STATE: STATEMSK22 Mask */ +#define SCT_EV0_STATE_STATEMSK23_Pos 23 /*!< SCT EV0_STATE: STATEMSK23 Position */ +#define SCT_EV0_STATE_STATEMSK23_Msk (0x01UL << SCT_EV0_STATE_STATEMSK23_Pos) /*!< SCT EV0_STATE: STATEMSK23 Mask */ +#define SCT_EV0_STATE_STATEMSK24_Pos 24 /*!< SCT EV0_STATE: STATEMSK24 Position */ +#define SCT_EV0_STATE_STATEMSK24_Msk (0x01UL << SCT_EV0_STATE_STATEMSK24_Pos) /*!< SCT EV0_STATE: STATEMSK24 Mask */ +#define SCT_EV0_STATE_STATEMSK25_Pos 25 /*!< SCT EV0_STATE: STATEMSK25 Position */ +#define SCT_EV0_STATE_STATEMSK25_Msk (0x01UL << SCT_EV0_STATE_STATEMSK25_Pos) /*!< SCT EV0_STATE: STATEMSK25 Mask */ +#define SCT_EV0_STATE_STATEMSK26_Pos 26 /*!< SCT EV0_STATE: STATEMSK26 Position */ +#define SCT_EV0_STATE_STATEMSK26_Msk (0x01UL << SCT_EV0_STATE_STATEMSK26_Pos) /*!< SCT EV0_STATE: STATEMSK26 Mask */ +#define SCT_EV0_STATE_STATEMSK27_Pos 27 /*!< SCT EV0_STATE: STATEMSK27 Position */ +#define SCT_EV0_STATE_STATEMSK27_Msk (0x01UL << SCT_EV0_STATE_STATEMSK27_Pos) /*!< SCT EV0_STATE: STATEMSK27 Mask */ +#define SCT_EV0_STATE_STATEMSK28_Pos 28 /*!< SCT EV0_STATE: STATEMSK28 Position */ +#define SCT_EV0_STATE_STATEMSK28_Msk (0x01UL << SCT_EV0_STATE_STATEMSK28_Pos) /*!< SCT EV0_STATE: STATEMSK28 Mask */ +#define SCT_EV0_STATE_STATEMSK29_Pos 29 /*!< SCT EV0_STATE: STATEMSK29 Position */ +#define SCT_EV0_STATE_STATEMSK29_Msk (0x01UL << SCT_EV0_STATE_STATEMSK29_Pos) /*!< SCT EV0_STATE: STATEMSK29 Mask */ +#define SCT_EV0_STATE_STATEMSK30_Pos 30 /*!< SCT EV0_STATE: STATEMSK30 Position */ +#define SCT_EV0_STATE_STATEMSK30_Msk (0x01UL << SCT_EV0_STATE_STATEMSK30_Pos) /*!< SCT EV0_STATE: STATEMSK30 Mask */ +#define SCT_EV0_STATE_STATEMSK31_Pos 31 /*!< SCT EV0_STATE: STATEMSK31 Position */ +#define SCT_EV0_STATE_STATEMSK31_Msk (0x01UL << SCT_EV0_STATE_STATEMSK31_Pos) /*!< SCT EV0_STATE: STATEMSK31 Mask */ + +/* -------------------------------- SCT_EV0_CTRL -------------------------------- */ +#define SCT_EV0_CTRL_MATCHSEL_Pos 0 /*!< SCT EV0_CTRL: MATCHSEL Position */ +#define SCT_EV0_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV0_CTRL_MATCHSEL_Pos) /*!< SCT EV0_CTRL: MATCHSEL Mask */ +#define SCT_EV0_CTRL_HEVENT_Pos 4 /*!< SCT EV0_CTRL: HEVENT Position */ +#define SCT_EV0_CTRL_HEVENT_Msk (0x01UL << SCT_EV0_CTRL_HEVENT_Pos) /*!< SCT EV0_CTRL: HEVENT Mask */ +#define SCT_EV0_CTRL_OUTSEL_Pos 5 /*!< SCT EV0_CTRL: OUTSEL Position */ +#define SCT_EV0_CTRL_OUTSEL_Msk (0x01UL << SCT_EV0_CTRL_OUTSEL_Pos) /*!< SCT EV0_CTRL: OUTSEL Mask */ +#define SCT_EV0_CTRL_IOSEL_Pos 6 /*!< SCT EV0_CTRL: IOSEL Position */ +#define SCT_EV0_CTRL_IOSEL_Msk (0x0fUL << SCT_EV0_CTRL_IOSEL_Pos) /*!< SCT EV0_CTRL: IOSEL Mask */ +#define SCT_EV0_CTRL_IOCOND_Pos 10 /*!< SCT EV0_CTRL: IOCOND Position */ +#define SCT_EV0_CTRL_IOCOND_Msk (0x03UL << SCT_EV0_CTRL_IOCOND_Pos) /*!< SCT EV0_CTRL: IOCOND Mask */ +#define SCT_EV0_CTRL_COMBMODE_Pos 12 /*!< SCT EV0_CTRL: COMBMODE Position */ +#define SCT_EV0_CTRL_COMBMODE_Msk (0x03UL << SCT_EV0_CTRL_COMBMODE_Pos) /*!< SCT EV0_CTRL: COMBMODE Mask */ +#define SCT_EV0_CTRL_STATELD_Pos 14 /*!< SCT EV0_CTRL: STATELD Position */ +#define SCT_EV0_CTRL_STATELD_Msk (0x01UL << SCT_EV0_CTRL_STATELD_Pos) /*!< SCT EV0_CTRL: STATELD Mask */ +#define SCT_EV0_CTRL_STATEV_Pos 15 /*!< SCT EV0_CTRL: STATEV Position */ +#define SCT_EV0_CTRL_STATEV_Msk (0x1fUL << SCT_EV0_CTRL_STATEV_Pos) /*!< SCT EV0_CTRL: STATEV Mask */ +#define SCT_EV0_CTRL_MATCHMEM_Pos 20 /*!< SCT EV0_CTRL: MATCHMEM Position */ +#define SCT_EV0_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV0_CTRL_MATCHMEM_Pos) /*!< SCT EV0_CTRL: MATCHMEM Mask */ +#define SCT_EV0_CTRL_DIRECTION_Pos 21 /*!< SCT EV0_CTRL: DIRECTION Position */ +#define SCT_EV0_CTRL_DIRECTION_Msk (0x03UL << SCT_EV0_CTRL_DIRECTION_Pos) /*!< SCT EV0_CTRL: DIRECTION Mask */ + +/* -------------------------------- SCT_EV1_STATE ------------------------------- */ +#define SCT_EV1_STATE_STATEMSK0_Pos 0 /*!< SCT EV1_STATE: STATEMSK0 Position */ +#define SCT_EV1_STATE_STATEMSK0_Msk (0x01UL << SCT_EV1_STATE_STATEMSK0_Pos) /*!< SCT EV1_STATE: STATEMSK0 Mask */ +#define SCT_EV1_STATE_STATEMSK1_Pos 1 /*!< SCT EV1_STATE: STATEMSK1 Position */ +#define SCT_EV1_STATE_STATEMSK1_Msk (0x01UL << SCT_EV1_STATE_STATEMSK1_Pos) /*!< SCT EV1_STATE: STATEMSK1 Mask */ +#define SCT_EV1_STATE_STATEMSK2_Pos 2 /*!< SCT EV1_STATE: STATEMSK2 Position */ +#define SCT_EV1_STATE_STATEMSK2_Msk (0x01UL << SCT_EV1_STATE_STATEMSK2_Pos) /*!< SCT EV1_STATE: STATEMSK2 Mask */ +#define SCT_EV1_STATE_STATEMSK3_Pos 3 /*!< SCT EV1_STATE: STATEMSK3 Position */ +#define SCT_EV1_STATE_STATEMSK3_Msk (0x01UL << SCT_EV1_STATE_STATEMSK3_Pos) /*!< SCT EV1_STATE: STATEMSK3 Mask */ +#define SCT_EV1_STATE_STATEMSK4_Pos 4 /*!< SCT EV1_STATE: STATEMSK4 Position */ +#define SCT_EV1_STATE_STATEMSK4_Msk (0x01UL << SCT_EV1_STATE_STATEMSK4_Pos) /*!< SCT EV1_STATE: STATEMSK4 Mask */ +#define SCT_EV1_STATE_STATEMSK5_Pos 5 /*!< SCT EV1_STATE: STATEMSK5 Position */ +#define SCT_EV1_STATE_STATEMSK5_Msk (0x01UL << SCT_EV1_STATE_STATEMSK5_Pos) /*!< SCT EV1_STATE: STATEMSK5 Mask */ +#define SCT_EV1_STATE_STATEMSK6_Pos 6 /*!< SCT EV1_STATE: STATEMSK6 Position */ +#define SCT_EV1_STATE_STATEMSK6_Msk (0x01UL << SCT_EV1_STATE_STATEMSK6_Pos) /*!< SCT EV1_STATE: STATEMSK6 Mask */ +#define SCT_EV1_STATE_STATEMSK7_Pos 7 /*!< SCT EV1_STATE: STATEMSK7 Position */ +#define SCT_EV1_STATE_STATEMSK7_Msk (0x01UL << SCT_EV1_STATE_STATEMSK7_Pos) /*!< SCT EV1_STATE: STATEMSK7 Mask */ +#define SCT_EV1_STATE_STATEMSK8_Pos 8 /*!< SCT EV1_STATE: STATEMSK8 Position */ +#define SCT_EV1_STATE_STATEMSK8_Msk (0x01UL << SCT_EV1_STATE_STATEMSK8_Pos) /*!< SCT EV1_STATE: STATEMSK8 Mask */ +#define SCT_EV1_STATE_STATEMSK9_Pos 9 /*!< SCT EV1_STATE: STATEMSK9 Position */ +#define SCT_EV1_STATE_STATEMSK9_Msk (0x01UL << SCT_EV1_STATE_STATEMSK9_Pos) /*!< SCT EV1_STATE: STATEMSK9 Mask */ +#define SCT_EV1_STATE_STATEMSK10_Pos 10 /*!< SCT EV1_STATE: STATEMSK10 Position */ +#define SCT_EV1_STATE_STATEMSK10_Msk (0x01UL << SCT_EV1_STATE_STATEMSK10_Pos) /*!< SCT EV1_STATE: STATEMSK10 Mask */ +#define SCT_EV1_STATE_STATEMSK11_Pos 11 /*!< SCT EV1_STATE: STATEMSK11 Position */ +#define SCT_EV1_STATE_STATEMSK11_Msk (0x01UL << SCT_EV1_STATE_STATEMSK11_Pos) /*!< SCT EV1_STATE: STATEMSK11 Mask */ +#define SCT_EV1_STATE_STATEMSK12_Pos 12 /*!< SCT EV1_STATE: STATEMSK12 Position */ +#define SCT_EV1_STATE_STATEMSK12_Msk (0x01UL << SCT_EV1_STATE_STATEMSK12_Pos) /*!< SCT EV1_STATE: STATEMSK12 Mask */ +#define SCT_EV1_STATE_STATEMSK13_Pos 13 /*!< SCT EV1_STATE: STATEMSK13 Position */ +#define SCT_EV1_STATE_STATEMSK13_Msk (0x01UL << SCT_EV1_STATE_STATEMSK13_Pos) /*!< SCT EV1_STATE: STATEMSK13 Mask */ +#define SCT_EV1_STATE_STATEMSK14_Pos 14 /*!< SCT EV1_STATE: STATEMSK14 Position */ +#define SCT_EV1_STATE_STATEMSK14_Msk (0x01UL << SCT_EV1_STATE_STATEMSK14_Pos) /*!< SCT EV1_STATE: STATEMSK14 Mask */ +#define SCT_EV1_STATE_STATEMSK15_Pos 15 /*!< SCT EV1_STATE: STATEMSK15 Position */ +#define SCT_EV1_STATE_STATEMSK15_Msk (0x01UL << SCT_EV1_STATE_STATEMSK15_Pos) /*!< SCT EV1_STATE: STATEMSK15 Mask */ +#define SCT_EV1_STATE_STATEMSK16_Pos 16 /*!< SCT EV1_STATE: STATEMSK16 Position */ +#define SCT_EV1_STATE_STATEMSK16_Msk (0x01UL << SCT_EV1_STATE_STATEMSK16_Pos) /*!< SCT EV1_STATE: STATEMSK16 Mask */ +#define SCT_EV1_STATE_STATEMSK17_Pos 17 /*!< SCT EV1_STATE: STATEMSK17 Position */ +#define SCT_EV1_STATE_STATEMSK17_Msk (0x01UL << SCT_EV1_STATE_STATEMSK17_Pos) /*!< SCT EV1_STATE: STATEMSK17 Mask */ +#define SCT_EV1_STATE_STATEMSK18_Pos 18 /*!< SCT EV1_STATE: STATEMSK18 Position */ +#define SCT_EV1_STATE_STATEMSK18_Msk (0x01UL << SCT_EV1_STATE_STATEMSK18_Pos) /*!< SCT EV1_STATE: STATEMSK18 Mask */ +#define SCT_EV1_STATE_STATEMSK19_Pos 19 /*!< SCT EV1_STATE: STATEMSK19 Position */ +#define SCT_EV1_STATE_STATEMSK19_Msk (0x01UL << SCT_EV1_STATE_STATEMSK19_Pos) /*!< SCT EV1_STATE: STATEMSK19 Mask */ +#define SCT_EV1_STATE_STATEMSK20_Pos 20 /*!< SCT EV1_STATE: STATEMSK20 Position */ +#define SCT_EV1_STATE_STATEMSK20_Msk (0x01UL << SCT_EV1_STATE_STATEMSK20_Pos) /*!< SCT EV1_STATE: STATEMSK20 Mask */ +#define SCT_EV1_STATE_STATEMSK21_Pos 21 /*!< SCT EV1_STATE: STATEMSK21 Position */ +#define SCT_EV1_STATE_STATEMSK21_Msk (0x01UL << SCT_EV1_STATE_STATEMSK21_Pos) /*!< SCT EV1_STATE: STATEMSK21 Mask */ +#define SCT_EV1_STATE_STATEMSK22_Pos 22 /*!< SCT EV1_STATE: STATEMSK22 Position */ +#define SCT_EV1_STATE_STATEMSK22_Msk (0x01UL << SCT_EV1_STATE_STATEMSK22_Pos) /*!< SCT EV1_STATE: STATEMSK22 Mask */ +#define SCT_EV1_STATE_STATEMSK23_Pos 23 /*!< SCT EV1_STATE: STATEMSK23 Position */ +#define SCT_EV1_STATE_STATEMSK23_Msk (0x01UL << SCT_EV1_STATE_STATEMSK23_Pos) /*!< SCT EV1_STATE: STATEMSK23 Mask */ +#define SCT_EV1_STATE_STATEMSK24_Pos 24 /*!< SCT EV1_STATE: STATEMSK24 Position */ +#define SCT_EV1_STATE_STATEMSK24_Msk (0x01UL << SCT_EV1_STATE_STATEMSK24_Pos) /*!< SCT EV1_STATE: STATEMSK24 Mask */ +#define SCT_EV1_STATE_STATEMSK25_Pos 25 /*!< SCT EV1_STATE: STATEMSK25 Position */ +#define SCT_EV1_STATE_STATEMSK25_Msk (0x01UL << SCT_EV1_STATE_STATEMSK25_Pos) /*!< SCT EV1_STATE: STATEMSK25 Mask */ +#define SCT_EV1_STATE_STATEMSK26_Pos 26 /*!< SCT EV1_STATE: STATEMSK26 Position */ +#define SCT_EV1_STATE_STATEMSK26_Msk (0x01UL << SCT_EV1_STATE_STATEMSK26_Pos) /*!< SCT EV1_STATE: STATEMSK26 Mask */ +#define SCT_EV1_STATE_STATEMSK27_Pos 27 /*!< SCT EV1_STATE: STATEMSK27 Position */ +#define SCT_EV1_STATE_STATEMSK27_Msk (0x01UL << SCT_EV1_STATE_STATEMSK27_Pos) /*!< SCT EV1_STATE: STATEMSK27 Mask */ +#define SCT_EV1_STATE_STATEMSK28_Pos 28 /*!< SCT EV1_STATE: STATEMSK28 Position */ +#define SCT_EV1_STATE_STATEMSK28_Msk (0x01UL << SCT_EV1_STATE_STATEMSK28_Pos) /*!< SCT EV1_STATE: STATEMSK28 Mask */ +#define SCT_EV1_STATE_STATEMSK29_Pos 29 /*!< SCT EV1_STATE: STATEMSK29 Position */ +#define SCT_EV1_STATE_STATEMSK29_Msk (0x01UL << SCT_EV1_STATE_STATEMSK29_Pos) /*!< SCT EV1_STATE: STATEMSK29 Mask */ +#define SCT_EV1_STATE_STATEMSK30_Pos 30 /*!< SCT EV1_STATE: STATEMSK30 Position */ +#define SCT_EV1_STATE_STATEMSK30_Msk (0x01UL << SCT_EV1_STATE_STATEMSK30_Pos) /*!< SCT EV1_STATE: STATEMSK30 Mask */ +#define SCT_EV1_STATE_STATEMSK31_Pos 31 /*!< SCT EV1_STATE: STATEMSK31 Position */ +#define SCT_EV1_STATE_STATEMSK31_Msk (0x01UL << SCT_EV1_STATE_STATEMSK31_Pos) /*!< SCT EV1_STATE: STATEMSK31 Mask */ + +/* -------------------------------- SCT_EV1_CTRL -------------------------------- */ +#define SCT_EV1_CTRL_MATCHSEL_Pos 0 /*!< SCT EV1_CTRL: MATCHSEL Position */ +#define SCT_EV1_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV1_CTRL_MATCHSEL_Pos) /*!< SCT EV1_CTRL: MATCHSEL Mask */ +#define SCT_EV1_CTRL_HEVENT_Pos 4 /*!< SCT EV1_CTRL: HEVENT Position */ +#define SCT_EV1_CTRL_HEVENT_Msk (0x01UL << SCT_EV1_CTRL_HEVENT_Pos) /*!< SCT EV1_CTRL: HEVENT Mask */ +#define SCT_EV1_CTRL_OUTSEL_Pos 5 /*!< SCT EV1_CTRL: OUTSEL Position */ +#define SCT_EV1_CTRL_OUTSEL_Msk (0x01UL << SCT_EV1_CTRL_OUTSEL_Pos) /*!< SCT EV1_CTRL: OUTSEL Mask */ +#define SCT_EV1_CTRL_IOSEL_Pos 6 /*!< SCT EV1_CTRL: IOSEL Position */ +#define SCT_EV1_CTRL_IOSEL_Msk (0x0fUL << SCT_EV1_CTRL_IOSEL_Pos) /*!< SCT EV1_CTRL: IOSEL Mask */ +#define SCT_EV1_CTRL_IOCOND_Pos 10 /*!< SCT EV1_CTRL: IOCOND Position */ +#define SCT_EV1_CTRL_IOCOND_Msk (0x03UL << SCT_EV1_CTRL_IOCOND_Pos) /*!< SCT EV1_CTRL: IOCOND Mask */ +#define SCT_EV1_CTRL_COMBMODE_Pos 12 /*!< SCT EV1_CTRL: COMBMODE Position */ +#define SCT_EV1_CTRL_COMBMODE_Msk (0x03UL << SCT_EV1_CTRL_COMBMODE_Pos) /*!< SCT EV1_CTRL: COMBMODE Mask */ +#define SCT_EV1_CTRL_STATELD_Pos 14 /*!< SCT EV1_CTRL: STATELD Position */ +#define SCT_EV1_CTRL_STATELD_Msk (0x01UL << SCT_EV1_CTRL_STATELD_Pos) /*!< SCT EV1_CTRL: STATELD Mask */ +#define SCT_EV1_CTRL_STATEV_Pos 15 /*!< SCT EV1_CTRL: STATEV Position */ +#define SCT_EV1_CTRL_STATEV_Msk (0x1fUL << SCT_EV1_CTRL_STATEV_Pos) /*!< SCT EV1_CTRL: STATEV Mask */ +#define SCT_EV1_CTRL_MATCHMEM_Pos 20 /*!< SCT EV1_CTRL: MATCHMEM Position */ +#define SCT_EV1_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV1_CTRL_MATCHMEM_Pos) /*!< SCT EV1_CTRL: MATCHMEM Mask */ +#define SCT_EV1_CTRL_DIRECTION_Pos 21 /*!< SCT EV1_CTRL: DIRECTION Position */ +#define SCT_EV1_CTRL_DIRECTION_Msk (0x03UL << SCT_EV1_CTRL_DIRECTION_Pos) /*!< SCT EV1_CTRL: DIRECTION Mask */ + +/* -------------------------------- SCT_EV2_STATE ------------------------------- */ +#define SCT_EV2_STATE_STATEMSK0_Pos 0 /*!< SCT EV2_STATE: STATEMSK0 Position */ +#define SCT_EV2_STATE_STATEMSK0_Msk (0x01UL << SCT_EV2_STATE_STATEMSK0_Pos) /*!< SCT EV2_STATE: STATEMSK0 Mask */ +#define SCT_EV2_STATE_STATEMSK1_Pos 1 /*!< SCT EV2_STATE: STATEMSK1 Position */ +#define SCT_EV2_STATE_STATEMSK1_Msk (0x01UL << SCT_EV2_STATE_STATEMSK1_Pos) /*!< SCT EV2_STATE: STATEMSK1 Mask */ +#define SCT_EV2_STATE_STATEMSK2_Pos 2 /*!< SCT EV2_STATE: STATEMSK2 Position */ +#define SCT_EV2_STATE_STATEMSK2_Msk (0x01UL << SCT_EV2_STATE_STATEMSK2_Pos) /*!< SCT EV2_STATE: STATEMSK2 Mask */ +#define SCT_EV2_STATE_STATEMSK3_Pos 3 /*!< SCT EV2_STATE: STATEMSK3 Position */ +#define SCT_EV2_STATE_STATEMSK3_Msk (0x01UL << SCT_EV2_STATE_STATEMSK3_Pos) /*!< SCT EV2_STATE: STATEMSK3 Mask */ +#define SCT_EV2_STATE_STATEMSK4_Pos 4 /*!< SCT EV2_STATE: STATEMSK4 Position */ +#define SCT_EV2_STATE_STATEMSK4_Msk (0x01UL << SCT_EV2_STATE_STATEMSK4_Pos) /*!< SCT EV2_STATE: STATEMSK4 Mask */ +#define SCT_EV2_STATE_STATEMSK5_Pos 5 /*!< SCT EV2_STATE: STATEMSK5 Position */ +#define SCT_EV2_STATE_STATEMSK5_Msk (0x01UL << SCT_EV2_STATE_STATEMSK5_Pos) /*!< SCT EV2_STATE: STATEMSK5 Mask */ +#define SCT_EV2_STATE_STATEMSK6_Pos 6 /*!< SCT EV2_STATE: STATEMSK6 Position */ +#define SCT_EV2_STATE_STATEMSK6_Msk (0x01UL << SCT_EV2_STATE_STATEMSK6_Pos) /*!< SCT EV2_STATE: STATEMSK6 Mask */ +#define SCT_EV2_STATE_STATEMSK7_Pos 7 /*!< SCT EV2_STATE: STATEMSK7 Position */ +#define SCT_EV2_STATE_STATEMSK7_Msk (0x01UL << SCT_EV2_STATE_STATEMSK7_Pos) /*!< SCT EV2_STATE: STATEMSK7 Mask */ +#define SCT_EV2_STATE_STATEMSK8_Pos 8 /*!< SCT EV2_STATE: STATEMSK8 Position */ +#define SCT_EV2_STATE_STATEMSK8_Msk (0x01UL << SCT_EV2_STATE_STATEMSK8_Pos) /*!< SCT EV2_STATE: STATEMSK8 Mask */ +#define SCT_EV2_STATE_STATEMSK9_Pos 9 /*!< SCT EV2_STATE: STATEMSK9 Position */ +#define SCT_EV2_STATE_STATEMSK9_Msk (0x01UL << SCT_EV2_STATE_STATEMSK9_Pos) /*!< SCT EV2_STATE: STATEMSK9 Mask */ +#define SCT_EV2_STATE_STATEMSK10_Pos 10 /*!< SCT EV2_STATE: STATEMSK10 Position */ +#define SCT_EV2_STATE_STATEMSK10_Msk (0x01UL << SCT_EV2_STATE_STATEMSK10_Pos) /*!< SCT EV2_STATE: STATEMSK10 Mask */ +#define SCT_EV2_STATE_STATEMSK11_Pos 11 /*!< SCT EV2_STATE: STATEMSK11 Position */ +#define SCT_EV2_STATE_STATEMSK11_Msk (0x01UL << SCT_EV2_STATE_STATEMSK11_Pos) /*!< SCT EV2_STATE: STATEMSK11 Mask */ +#define SCT_EV2_STATE_STATEMSK12_Pos 12 /*!< SCT EV2_STATE: STATEMSK12 Position */ +#define SCT_EV2_STATE_STATEMSK12_Msk (0x01UL << SCT_EV2_STATE_STATEMSK12_Pos) /*!< SCT EV2_STATE: STATEMSK12 Mask */ +#define SCT_EV2_STATE_STATEMSK13_Pos 13 /*!< SCT EV2_STATE: STATEMSK13 Position */ +#define SCT_EV2_STATE_STATEMSK13_Msk (0x01UL << SCT_EV2_STATE_STATEMSK13_Pos) /*!< SCT EV2_STATE: STATEMSK13 Mask */ +#define SCT_EV2_STATE_STATEMSK14_Pos 14 /*!< SCT EV2_STATE: STATEMSK14 Position */ +#define SCT_EV2_STATE_STATEMSK14_Msk (0x01UL << SCT_EV2_STATE_STATEMSK14_Pos) /*!< SCT EV2_STATE: STATEMSK14 Mask */ +#define SCT_EV2_STATE_STATEMSK15_Pos 15 /*!< SCT EV2_STATE: STATEMSK15 Position */ +#define SCT_EV2_STATE_STATEMSK15_Msk (0x01UL << SCT_EV2_STATE_STATEMSK15_Pos) /*!< SCT EV2_STATE: STATEMSK15 Mask */ +#define SCT_EV2_STATE_STATEMSK16_Pos 16 /*!< SCT EV2_STATE: STATEMSK16 Position */ +#define SCT_EV2_STATE_STATEMSK16_Msk (0x01UL << SCT_EV2_STATE_STATEMSK16_Pos) /*!< SCT EV2_STATE: STATEMSK16 Mask */ +#define SCT_EV2_STATE_STATEMSK17_Pos 17 /*!< SCT EV2_STATE: STATEMSK17 Position */ +#define SCT_EV2_STATE_STATEMSK17_Msk (0x01UL << SCT_EV2_STATE_STATEMSK17_Pos) /*!< SCT EV2_STATE: STATEMSK17 Mask */ +#define SCT_EV2_STATE_STATEMSK18_Pos 18 /*!< SCT EV2_STATE: STATEMSK18 Position */ +#define SCT_EV2_STATE_STATEMSK18_Msk (0x01UL << SCT_EV2_STATE_STATEMSK18_Pos) /*!< SCT EV2_STATE: STATEMSK18 Mask */ +#define SCT_EV2_STATE_STATEMSK19_Pos 19 /*!< SCT EV2_STATE: STATEMSK19 Position */ +#define SCT_EV2_STATE_STATEMSK19_Msk (0x01UL << SCT_EV2_STATE_STATEMSK19_Pos) /*!< SCT EV2_STATE: STATEMSK19 Mask */ +#define SCT_EV2_STATE_STATEMSK20_Pos 20 /*!< SCT EV2_STATE: STATEMSK20 Position */ +#define SCT_EV2_STATE_STATEMSK20_Msk (0x01UL << SCT_EV2_STATE_STATEMSK20_Pos) /*!< SCT EV2_STATE: STATEMSK20 Mask */ +#define SCT_EV2_STATE_STATEMSK21_Pos 21 /*!< SCT EV2_STATE: STATEMSK21 Position */ +#define SCT_EV2_STATE_STATEMSK21_Msk (0x01UL << SCT_EV2_STATE_STATEMSK21_Pos) /*!< SCT EV2_STATE: STATEMSK21 Mask */ +#define SCT_EV2_STATE_STATEMSK22_Pos 22 /*!< SCT EV2_STATE: STATEMSK22 Position */ +#define SCT_EV2_STATE_STATEMSK22_Msk (0x01UL << SCT_EV2_STATE_STATEMSK22_Pos) /*!< SCT EV2_STATE: STATEMSK22 Mask */ +#define SCT_EV2_STATE_STATEMSK23_Pos 23 /*!< SCT EV2_STATE: STATEMSK23 Position */ +#define SCT_EV2_STATE_STATEMSK23_Msk (0x01UL << SCT_EV2_STATE_STATEMSK23_Pos) /*!< SCT EV2_STATE: STATEMSK23 Mask */ +#define SCT_EV2_STATE_STATEMSK24_Pos 24 /*!< SCT EV2_STATE: STATEMSK24 Position */ +#define SCT_EV2_STATE_STATEMSK24_Msk (0x01UL << SCT_EV2_STATE_STATEMSK24_Pos) /*!< SCT EV2_STATE: STATEMSK24 Mask */ +#define SCT_EV2_STATE_STATEMSK25_Pos 25 /*!< SCT EV2_STATE: STATEMSK25 Position */ +#define SCT_EV2_STATE_STATEMSK25_Msk (0x01UL << SCT_EV2_STATE_STATEMSK25_Pos) /*!< SCT EV2_STATE: STATEMSK25 Mask */ +#define SCT_EV2_STATE_STATEMSK26_Pos 26 /*!< SCT EV2_STATE: STATEMSK26 Position */ +#define SCT_EV2_STATE_STATEMSK26_Msk (0x01UL << SCT_EV2_STATE_STATEMSK26_Pos) /*!< SCT EV2_STATE: STATEMSK26 Mask */ +#define SCT_EV2_STATE_STATEMSK27_Pos 27 /*!< SCT EV2_STATE: STATEMSK27 Position */ +#define SCT_EV2_STATE_STATEMSK27_Msk (0x01UL << SCT_EV2_STATE_STATEMSK27_Pos) /*!< SCT EV2_STATE: STATEMSK27 Mask */ +#define SCT_EV2_STATE_STATEMSK28_Pos 28 /*!< SCT EV2_STATE: STATEMSK28 Position */ +#define SCT_EV2_STATE_STATEMSK28_Msk (0x01UL << SCT_EV2_STATE_STATEMSK28_Pos) /*!< SCT EV2_STATE: STATEMSK28 Mask */ +#define SCT_EV2_STATE_STATEMSK29_Pos 29 /*!< SCT EV2_STATE: STATEMSK29 Position */ +#define SCT_EV2_STATE_STATEMSK29_Msk (0x01UL << SCT_EV2_STATE_STATEMSK29_Pos) /*!< SCT EV2_STATE: STATEMSK29 Mask */ +#define SCT_EV2_STATE_STATEMSK30_Pos 30 /*!< SCT EV2_STATE: STATEMSK30 Position */ +#define SCT_EV2_STATE_STATEMSK30_Msk (0x01UL << SCT_EV2_STATE_STATEMSK30_Pos) /*!< SCT EV2_STATE: STATEMSK30 Mask */ +#define SCT_EV2_STATE_STATEMSK31_Pos 31 /*!< SCT EV2_STATE: STATEMSK31 Position */ +#define SCT_EV2_STATE_STATEMSK31_Msk (0x01UL << SCT_EV2_STATE_STATEMSK31_Pos) /*!< SCT EV2_STATE: STATEMSK31 Mask */ + +/* -------------------------------- SCT_EV2_CTRL -------------------------------- */ +#define SCT_EV2_CTRL_MATCHSEL_Pos 0 /*!< SCT EV2_CTRL: MATCHSEL Position */ +#define SCT_EV2_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV2_CTRL_MATCHSEL_Pos) /*!< SCT EV2_CTRL: MATCHSEL Mask */ +#define SCT_EV2_CTRL_HEVENT_Pos 4 /*!< SCT EV2_CTRL: HEVENT Position */ +#define SCT_EV2_CTRL_HEVENT_Msk (0x01UL << SCT_EV2_CTRL_HEVENT_Pos) /*!< SCT EV2_CTRL: HEVENT Mask */ +#define SCT_EV2_CTRL_OUTSEL_Pos 5 /*!< SCT EV2_CTRL: OUTSEL Position */ +#define SCT_EV2_CTRL_OUTSEL_Msk (0x01UL << SCT_EV2_CTRL_OUTSEL_Pos) /*!< SCT EV2_CTRL: OUTSEL Mask */ +#define SCT_EV2_CTRL_IOSEL_Pos 6 /*!< SCT EV2_CTRL: IOSEL Position */ +#define SCT_EV2_CTRL_IOSEL_Msk (0x0fUL << SCT_EV2_CTRL_IOSEL_Pos) /*!< SCT EV2_CTRL: IOSEL Mask */ +#define SCT_EV2_CTRL_IOCOND_Pos 10 /*!< SCT EV2_CTRL: IOCOND Position */ +#define SCT_EV2_CTRL_IOCOND_Msk (0x03UL << SCT_EV2_CTRL_IOCOND_Pos) /*!< SCT EV2_CTRL: IOCOND Mask */ +#define SCT_EV2_CTRL_COMBMODE_Pos 12 /*!< SCT EV2_CTRL: COMBMODE Position */ +#define SCT_EV2_CTRL_COMBMODE_Msk (0x03UL << SCT_EV2_CTRL_COMBMODE_Pos) /*!< SCT EV2_CTRL: COMBMODE Mask */ +#define SCT_EV2_CTRL_STATELD_Pos 14 /*!< SCT EV2_CTRL: STATELD Position */ +#define SCT_EV2_CTRL_STATELD_Msk (0x01UL << SCT_EV2_CTRL_STATELD_Pos) /*!< SCT EV2_CTRL: STATELD Mask */ +#define SCT_EV2_CTRL_STATEV_Pos 15 /*!< SCT EV2_CTRL: STATEV Position */ +#define SCT_EV2_CTRL_STATEV_Msk (0x1fUL << SCT_EV2_CTRL_STATEV_Pos) /*!< SCT EV2_CTRL: STATEV Mask */ +#define SCT_EV2_CTRL_MATCHMEM_Pos 20 /*!< SCT EV2_CTRL: MATCHMEM Position */ +#define SCT_EV2_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV2_CTRL_MATCHMEM_Pos) /*!< SCT EV2_CTRL: MATCHMEM Mask */ +#define SCT_EV2_CTRL_DIRECTION_Pos 21 /*!< SCT EV2_CTRL: DIRECTION Position */ +#define SCT_EV2_CTRL_DIRECTION_Msk (0x03UL << SCT_EV2_CTRL_DIRECTION_Pos) /*!< SCT EV2_CTRL: DIRECTION Mask */ + +/* -------------------------------- SCT_EV3_STATE ------------------------------- */ +#define SCT_EV3_STATE_STATEMSK0_Pos 0 /*!< SCT EV3_STATE: STATEMSK0 Position */ +#define SCT_EV3_STATE_STATEMSK0_Msk (0x01UL << SCT_EV3_STATE_STATEMSK0_Pos) /*!< SCT EV3_STATE: STATEMSK0 Mask */ +#define SCT_EV3_STATE_STATEMSK1_Pos 1 /*!< SCT EV3_STATE: STATEMSK1 Position */ +#define SCT_EV3_STATE_STATEMSK1_Msk (0x01UL << SCT_EV3_STATE_STATEMSK1_Pos) /*!< SCT EV3_STATE: STATEMSK1 Mask */ +#define SCT_EV3_STATE_STATEMSK2_Pos 2 /*!< SCT EV3_STATE: STATEMSK2 Position */ +#define SCT_EV3_STATE_STATEMSK2_Msk (0x01UL << SCT_EV3_STATE_STATEMSK2_Pos) /*!< SCT EV3_STATE: STATEMSK2 Mask */ +#define SCT_EV3_STATE_STATEMSK3_Pos 3 /*!< SCT EV3_STATE: STATEMSK3 Position */ +#define SCT_EV3_STATE_STATEMSK3_Msk (0x01UL << SCT_EV3_STATE_STATEMSK3_Pos) /*!< SCT EV3_STATE: STATEMSK3 Mask */ +#define SCT_EV3_STATE_STATEMSK4_Pos 4 /*!< SCT EV3_STATE: STATEMSK4 Position */ +#define SCT_EV3_STATE_STATEMSK4_Msk (0x01UL << SCT_EV3_STATE_STATEMSK4_Pos) /*!< SCT EV3_STATE: STATEMSK4 Mask */ +#define SCT_EV3_STATE_STATEMSK5_Pos 5 /*!< SCT EV3_STATE: STATEMSK5 Position */ +#define SCT_EV3_STATE_STATEMSK5_Msk (0x01UL << SCT_EV3_STATE_STATEMSK5_Pos) /*!< SCT EV3_STATE: STATEMSK5 Mask */ +#define SCT_EV3_STATE_STATEMSK6_Pos 6 /*!< SCT EV3_STATE: STATEMSK6 Position */ +#define SCT_EV3_STATE_STATEMSK6_Msk (0x01UL << SCT_EV3_STATE_STATEMSK6_Pos) /*!< SCT EV3_STATE: STATEMSK6 Mask */ +#define SCT_EV3_STATE_STATEMSK7_Pos 7 /*!< SCT EV3_STATE: STATEMSK7 Position */ +#define SCT_EV3_STATE_STATEMSK7_Msk (0x01UL << SCT_EV3_STATE_STATEMSK7_Pos) /*!< SCT EV3_STATE: STATEMSK7 Mask */ +#define SCT_EV3_STATE_STATEMSK8_Pos 8 /*!< SCT EV3_STATE: STATEMSK8 Position */ +#define SCT_EV3_STATE_STATEMSK8_Msk (0x01UL << SCT_EV3_STATE_STATEMSK8_Pos) /*!< SCT EV3_STATE: STATEMSK8 Mask */ +#define SCT_EV3_STATE_STATEMSK9_Pos 9 /*!< SCT EV3_STATE: STATEMSK9 Position */ +#define SCT_EV3_STATE_STATEMSK9_Msk (0x01UL << SCT_EV3_STATE_STATEMSK9_Pos) /*!< SCT EV3_STATE: STATEMSK9 Mask */ +#define SCT_EV3_STATE_STATEMSK10_Pos 10 /*!< SCT EV3_STATE: STATEMSK10 Position */ +#define SCT_EV3_STATE_STATEMSK10_Msk (0x01UL << SCT_EV3_STATE_STATEMSK10_Pos) /*!< SCT EV3_STATE: STATEMSK10 Mask */ +#define SCT_EV3_STATE_STATEMSK11_Pos 11 /*!< SCT EV3_STATE: STATEMSK11 Position */ +#define SCT_EV3_STATE_STATEMSK11_Msk (0x01UL << SCT_EV3_STATE_STATEMSK11_Pos) /*!< SCT EV3_STATE: STATEMSK11 Mask */ +#define SCT_EV3_STATE_STATEMSK12_Pos 12 /*!< SCT EV3_STATE: STATEMSK12 Position */ +#define SCT_EV3_STATE_STATEMSK12_Msk (0x01UL << SCT_EV3_STATE_STATEMSK12_Pos) /*!< SCT EV3_STATE: STATEMSK12 Mask */ +#define SCT_EV3_STATE_STATEMSK13_Pos 13 /*!< SCT EV3_STATE: STATEMSK13 Position */ +#define SCT_EV3_STATE_STATEMSK13_Msk (0x01UL << SCT_EV3_STATE_STATEMSK13_Pos) /*!< SCT EV3_STATE: STATEMSK13 Mask */ +#define SCT_EV3_STATE_STATEMSK14_Pos 14 /*!< SCT EV3_STATE: STATEMSK14 Position */ +#define SCT_EV3_STATE_STATEMSK14_Msk (0x01UL << SCT_EV3_STATE_STATEMSK14_Pos) /*!< SCT EV3_STATE: STATEMSK14 Mask */ +#define SCT_EV3_STATE_STATEMSK15_Pos 15 /*!< SCT EV3_STATE: STATEMSK15 Position */ +#define SCT_EV3_STATE_STATEMSK15_Msk (0x01UL << SCT_EV3_STATE_STATEMSK15_Pos) /*!< SCT EV3_STATE: STATEMSK15 Mask */ +#define SCT_EV3_STATE_STATEMSK16_Pos 16 /*!< SCT EV3_STATE: STATEMSK16 Position */ +#define SCT_EV3_STATE_STATEMSK16_Msk (0x01UL << SCT_EV3_STATE_STATEMSK16_Pos) /*!< SCT EV3_STATE: STATEMSK16 Mask */ +#define SCT_EV3_STATE_STATEMSK17_Pos 17 /*!< SCT EV3_STATE: STATEMSK17 Position */ +#define SCT_EV3_STATE_STATEMSK17_Msk (0x01UL << SCT_EV3_STATE_STATEMSK17_Pos) /*!< SCT EV3_STATE: STATEMSK17 Mask */ +#define SCT_EV3_STATE_STATEMSK18_Pos 18 /*!< SCT EV3_STATE: STATEMSK18 Position */ +#define SCT_EV3_STATE_STATEMSK18_Msk (0x01UL << SCT_EV3_STATE_STATEMSK18_Pos) /*!< SCT EV3_STATE: STATEMSK18 Mask */ +#define SCT_EV3_STATE_STATEMSK19_Pos 19 /*!< SCT EV3_STATE: STATEMSK19 Position */ +#define SCT_EV3_STATE_STATEMSK19_Msk (0x01UL << SCT_EV3_STATE_STATEMSK19_Pos) /*!< SCT EV3_STATE: STATEMSK19 Mask */ +#define SCT_EV3_STATE_STATEMSK20_Pos 20 /*!< SCT EV3_STATE: STATEMSK20 Position */ +#define SCT_EV3_STATE_STATEMSK20_Msk (0x01UL << SCT_EV3_STATE_STATEMSK20_Pos) /*!< SCT EV3_STATE: STATEMSK20 Mask */ +#define SCT_EV3_STATE_STATEMSK21_Pos 21 /*!< SCT EV3_STATE: STATEMSK21 Position */ +#define SCT_EV3_STATE_STATEMSK21_Msk (0x01UL << SCT_EV3_STATE_STATEMSK21_Pos) /*!< SCT EV3_STATE: STATEMSK21 Mask */ +#define SCT_EV3_STATE_STATEMSK22_Pos 22 /*!< SCT EV3_STATE: STATEMSK22 Position */ +#define SCT_EV3_STATE_STATEMSK22_Msk (0x01UL << SCT_EV3_STATE_STATEMSK22_Pos) /*!< SCT EV3_STATE: STATEMSK22 Mask */ +#define SCT_EV3_STATE_STATEMSK23_Pos 23 /*!< SCT EV3_STATE: STATEMSK23 Position */ +#define SCT_EV3_STATE_STATEMSK23_Msk (0x01UL << SCT_EV3_STATE_STATEMSK23_Pos) /*!< SCT EV3_STATE: STATEMSK23 Mask */ +#define SCT_EV3_STATE_STATEMSK24_Pos 24 /*!< SCT EV3_STATE: STATEMSK24 Position */ +#define SCT_EV3_STATE_STATEMSK24_Msk (0x01UL << SCT_EV3_STATE_STATEMSK24_Pos) /*!< SCT EV3_STATE: STATEMSK24 Mask */ +#define SCT_EV3_STATE_STATEMSK25_Pos 25 /*!< SCT EV3_STATE: STATEMSK25 Position */ +#define SCT_EV3_STATE_STATEMSK25_Msk (0x01UL << SCT_EV3_STATE_STATEMSK25_Pos) /*!< SCT EV3_STATE: STATEMSK25 Mask */ +#define SCT_EV3_STATE_STATEMSK26_Pos 26 /*!< SCT EV3_STATE: STATEMSK26 Position */ +#define SCT_EV3_STATE_STATEMSK26_Msk (0x01UL << SCT_EV3_STATE_STATEMSK26_Pos) /*!< SCT EV3_STATE: STATEMSK26 Mask */ +#define SCT_EV3_STATE_STATEMSK27_Pos 27 /*!< SCT EV3_STATE: STATEMSK27 Position */ +#define SCT_EV3_STATE_STATEMSK27_Msk (0x01UL << SCT_EV3_STATE_STATEMSK27_Pos) /*!< SCT EV3_STATE: STATEMSK27 Mask */ +#define SCT_EV3_STATE_STATEMSK28_Pos 28 /*!< SCT EV3_STATE: STATEMSK28 Position */ +#define SCT_EV3_STATE_STATEMSK28_Msk (0x01UL << SCT_EV3_STATE_STATEMSK28_Pos) /*!< SCT EV3_STATE: STATEMSK28 Mask */ +#define SCT_EV3_STATE_STATEMSK29_Pos 29 /*!< SCT EV3_STATE: STATEMSK29 Position */ +#define SCT_EV3_STATE_STATEMSK29_Msk (0x01UL << SCT_EV3_STATE_STATEMSK29_Pos) /*!< SCT EV3_STATE: STATEMSK29 Mask */ +#define SCT_EV3_STATE_STATEMSK30_Pos 30 /*!< SCT EV3_STATE: STATEMSK30 Position */ +#define SCT_EV3_STATE_STATEMSK30_Msk (0x01UL << SCT_EV3_STATE_STATEMSK30_Pos) /*!< SCT EV3_STATE: STATEMSK30 Mask */ +#define SCT_EV3_STATE_STATEMSK31_Pos 31 /*!< SCT EV3_STATE: STATEMSK31 Position */ +#define SCT_EV3_STATE_STATEMSK31_Msk (0x01UL << SCT_EV3_STATE_STATEMSK31_Pos) /*!< SCT EV3_STATE: STATEMSK31 Mask */ + +/* -------------------------------- SCT_EV3_CTRL -------------------------------- */ +#define SCT_EV3_CTRL_MATCHSEL_Pos 0 /*!< SCT EV3_CTRL: MATCHSEL Position */ +#define SCT_EV3_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV3_CTRL_MATCHSEL_Pos) /*!< SCT EV3_CTRL: MATCHSEL Mask */ +#define SCT_EV3_CTRL_HEVENT_Pos 4 /*!< SCT EV3_CTRL: HEVENT Position */ +#define SCT_EV3_CTRL_HEVENT_Msk (0x01UL << SCT_EV3_CTRL_HEVENT_Pos) /*!< SCT EV3_CTRL: HEVENT Mask */ +#define SCT_EV3_CTRL_OUTSEL_Pos 5 /*!< SCT EV3_CTRL: OUTSEL Position */ +#define SCT_EV3_CTRL_OUTSEL_Msk (0x01UL << SCT_EV3_CTRL_OUTSEL_Pos) /*!< SCT EV3_CTRL: OUTSEL Mask */ +#define SCT_EV3_CTRL_IOSEL_Pos 6 /*!< SCT EV3_CTRL: IOSEL Position */ +#define SCT_EV3_CTRL_IOSEL_Msk (0x0fUL << SCT_EV3_CTRL_IOSEL_Pos) /*!< SCT EV3_CTRL: IOSEL Mask */ +#define SCT_EV3_CTRL_IOCOND_Pos 10 /*!< SCT EV3_CTRL: IOCOND Position */ +#define SCT_EV3_CTRL_IOCOND_Msk (0x03UL << SCT_EV3_CTRL_IOCOND_Pos) /*!< SCT EV3_CTRL: IOCOND Mask */ +#define SCT_EV3_CTRL_COMBMODE_Pos 12 /*!< SCT EV3_CTRL: COMBMODE Position */ +#define SCT_EV3_CTRL_COMBMODE_Msk (0x03UL << SCT_EV3_CTRL_COMBMODE_Pos) /*!< SCT EV3_CTRL: COMBMODE Mask */ +#define SCT_EV3_CTRL_STATELD_Pos 14 /*!< SCT EV3_CTRL: STATELD Position */ +#define SCT_EV3_CTRL_STATELD_Msk (0x01UL << SCT_EV3_CTRL_STATELD_Pos) /*!< SCT EV3_CTRL: STATELD Mask */ +#define SCT_EV3_CTRL_STATEV_Pos 15 /*!< SCT EV3_CTRL: STATEV Position */ +#define SCT_EV3_CTRL_STATEV_Msk (0x1fUL << SCT_EV3_CTRL_STATEV_Pos) /*!< SCT EV3_CTRL: STATEV Mask */ +#define SCT_EV3_CTRL_MATCHMEM_Pos 20 /*!< SCT EV3_CTRL: MATCHMEM Position */ +#define SCT_EV3_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV3_CTRL_MATCHMEM_Pos) /*!< SCT EV3_CTRL: MATCHMEM Mask */ +#define SCT_EV3_CTRL_DIRECTION_Pos 21 /*!< SCT EV3_CTRL: DIRECTION Position */ +#define SCT_EV3_CTRL_DIRECTION_Msk (0x03UL << SCT_EV3_CTRL_DIRECTION_Pos) /*!< SCT EV3_CTRL: DIRECTION Mask */ + +/* -------------------------------- SCT_EV4_STATE ------------------------------- */ +#define SCT_EV4_STATE_STATEMSK0_Pos 0 /*!< SCT EV4_STATE: STATEMSK0 Position */ +#define SCT_EV4_STATE_STATEMSK0_Msk (0x01UL << SCT_EV4_STATE_STATEMSK0_Pos) /*!< SCT EV4_STATE: STATEMSK0 Mask */ +#define SCT_EV4_STATE_STATEMSK1_Pos 1 /*!< SCT EV4_STATE: STATEMSK1 Position */ +#define SCT_EV4_STATE_STATEMSK1_Msk (0x01UL << SCT_EV4_STATE_STATEMSK1_Pos) /*!< SCT EV4_STATE: STATEMSK1 Mask */ +#define SCT_EV4_STATE_STATEMSK2_Pos 2 /*!< SCT EV4_STATE: STATEMSK2 Position */ +#define SCT_EV4_STATE_STATEMSK2_Msk (0x01UL << SCT_EV4_STATE_STATEMSK2_Pos) /*!< SCT EV4_STATE: STATEMSK2 Mask */ +#define SCT_EV4_STATE_STATEMSK3_Pos 3 /*!< SCT EV4_STATE: STATEMSK3 Position */ +#define SCT_EV4_STATE_STATEMSK3_Msk (0x01UL << SCT_EV4_STATE_STATEMSK3_Pos) /*!< SCT EV4_STATE: STATEMSK3 Mask */ +#define SCT_EV4_STATE_STATEMSK4_Pos 4 /*!< SCT EV4_STATE: STATEMSK4 Position */ +#define SCT_EV4_STATE_STATEMSK4_Msk (0x01UL << SCT_EV4_STATE_STATEMSK4_Pos) /*!< SCT EV4_STATE: STATEMSK4 Mask */ +#define SCT_EV4_STATE_STATEMSK5_Pos 5 /*!< SCT EV4_STATE: STATEMSK5 Position */ +#define SCT_EV4_STATE_STATEMSK5_Msk (0x01UL << SCT_EV4_STATE_STATEMSK5_Pos) /*!< SCT EV4_STATE: STATEMSK5 Mask */ +#define SCT_EV4_STATE_STATEMSK6_Pos 6 /*!< SCT EV4_STATE: STATEMSK6 Position */ +#define SCT_EV4_STATE_STATEMSK6_Msk (0x01UL << SCT_EV4_STATE_STATEMSK6_Pos) /*!< SCT EV4_STATE: STATEMSK6 Mask */ +#define SCT_EV4_STATE_STATEMSK7_Pos 7 /*!< SCT EV4_STATE: STATEMSK7 Position */ +#define SCT_EV4_STATE_STATEMSK7_Msk (0x01UL << SCT_EV4_STATE_STATEMSK7_Pos) /*!< SCT EV4_STATE: STATEMSK7 Mask */ +#define SCT_EV4_STATE_STATEMSK8_Pos 8 /*!< SCT EV4_STATE: STATEMSK8 Position */ +#define SCT_EV4_STATE_STATEMSK8_Msk (0x01UL << SCT_EV4_STATE_STATEMSK8_Pos) /*!< SCT EV4_STATE: STATEMSK8 Mask */ +#define SCT_EV4_STATE_STATEMSK9_Pos 9 /*!< SCT EV4_STATE: STATEMSK9 Position */ +#define SCT_EV4_STATE_STATEMSK9_Msk (0x01UL << SCT_EV4_STATE_STATEMSK9_Pos) /*!< SCT EV4_STATE: STATEMSK9 Mask */ +#define SCT_EV4_STATE_STATEMSK10_Pos 10 /*!< SCT EV4_STATE: STATEMSK10 Position */ +#define SCT_EV4_STATE_STATEMSK10_Msk (0x01UL << SCT_EV4_STATE_STATEMSK10_Pos) /*!< SCT EV4_STATE: STATEMSK10 Mask */ +#define SCT_EV4_STATE_STATEMSK11_Pos 11 /*!< SCT EV4_STATE: STATEMSK11 Position */ +#define SCT_EV4_STATE_STATEMSK11_Msk (0x01UL << SCT_EV4_STATE_STATEMSK11_Pos) /*!< SCT EV4_STATE: STATEMSK11 Mask */ +#define SCT_EV4_STATE_STATEMSK12_Pos 12 /*!< SCT EV4_STATE: STATEMSK12 Position */ +#define SCT_EV4_STATE_STATEMSK12_Msk (0x01UL << SCT_EV4_STATE_STATEMSK12_Pos) /*!< SCT EV4_STATE: STATEMSK12 Mask */ +#define SCT_EV4_STATE_STATEMSK13_Pos 13 /*!< SCT EV4_STATE: STATEMSK13 Position */ +#define SCT_EV4_STATE_STATEMSK13_Msk (0x01UL << SCT_EV4_STATE_STATEMSK13_Pos) /*!< SCT EV4_STATE: STATEMSK13 Mask */ +#define SCT_EV4_STATE_STATEMSK14_Pos 14 /*!< SCT EV4_STATE: STATEMSK14 Position */ +#define SCT_EV4_STATE_STATEMSK14_Msk (0x01UL << SCT_EV4_STATE_STATEMSK14_Pos) /*!< SCT EV4_STATE: STATEMSK14 Mask */ +#define SCT_EV4_STATE_STATEMSK15_Pos 15 /*!< SCT EV4_STATE: STATEMSK15 Position */ +#define SCT_EV4_STATE_STATEMSK15_Msk (0x01UL << SCT_EV4_STATE_STATEMSK15_Pos) /*!< SCT EV4_STATE: STATEMSK15 Mask */ +#define SCT_EV4_STATE_STATEMSK16_Pos 16 /*!< SCT EV4_STATE: STATEMSK16 Position */ +#define SCT_EV4_STATE_STATEMSK16_Msk (0x01UL << SCT_EV4_STATE_STATEMSK16_Pos) /*!< SCT EV4_STATE: STATEMSK16 Mask */ +#define SCT_EV4_STATE_STATEMSK17_Pos 17 /*!< SCT EV4_STATE: STATEMSK17 Position */ +#define SCT_EV4_STATE_STATEMSK17_Msk (0x01UL << SCT_EV4_STATE_STATEMSK17_Pos) /*!< SCT EV4_STATE: STATEMSK17 Mask */ +#define SCT_EV4_STATE_STATEMSK18_Pos 18 /*!< SCT EV4_STATE: STATEMSK18 Position */ +#define SCT_EV4_STATE_STATEMSK18_Msk (0x01UL << SCT_EV4_STATE_STATEMSK18_Pos) /*!< SCT EV4_STATE: STATEMSK18 Mask */ +#define SCT_EV4_STATE_STATEMSK19_Pos 19 /*!< SCT EV4_STATE: STATEMSK19 Position */ +#define SCT_EV4_STATE_STATEMSK19_Msk (0x01UL << SCT_EV4_STATE_STATEMSK19_Pos) /*!< SCT EV4_STATE: STATEMSK19 Mask */ +#define SCT_EV4_STATE_STATEMSK20_Pos 20 /*!< SCT EV4_STATE: STATEMSK20 Position */ +#define SCT_EV4_STATE_STATEMSK20_Msk (0x01UL << SCT_EV4_STATE_STATEMSK20_Pos) /*!< SCT EV4_STATE: STATEMSK20 Mask */ +#define SCT_EV4_STATE_STATEMSK21_Pos 21 /*!< SCT EV4_STATE: STATEMSK21 Position */ +#define SCT_EV4_STATE_STATEMSK21_Msk (0x01UL << SCT_EV4_STATE_STATEMSK21_Pos) /*!< SCT EV4_STATE: STATEMSK21 Mask */ +#define SCT_EV4_STATE_STATEMSK22_Pos 22 /*!< SCT EV4_STATE: STATEMSK22 Position */ +#define SCT_EV4_STATE_STATEMSK22_Msk (0x01UL << SCT_EV4_STATE_STATEMSK22_Pos) /*!< SCT EV4_STATE: STATEMSK22 Mask */ +#define SCT_EV4_STATE_STATEMSK23_Pos 23 /*!< SCT EV4_STATE: STATEMSK23 Position */ +#define SCT_EV4_STATE_STATEMSK23_Msk (0x01UL << SCT_EV4_STATE_STATEMSK23_Pos) /*!< SCT EV4_STATE: STATEMSK23 Mask */ +#define SCT_EV4_STATE_STATEMSK24_Pos 24 /*!< SCT EV4_STATE: STATEMSK24 Position */ +#define SCT_EV4_STATE_STATEMSK24_Msk (0x01UL << SCT_EV4_STATE_STATEMSK24_Pos) /*!< SCT EV4_STATE: STATEMSK24 Mask */ +#define SCT_EV4_STATE_STATEMSK25_Pos 25 /*!< SCT EV4_STATE: STATEMSK25 Position */ +#define SCT_EV4_STATE_STATEMSK25_Msk (0x01UL << SCT_EV4_STATE_STATEMSK25_Pos) /*!< SCT EV4_STATE: STATEMSK25 Mask */ +#define SCT_EV4_STATE_STATEMSK26_Pos 26 /*!< SCT EV4_STATE: STATEMSK26 Position */ +#define SCT_EV4_STATE_STATEMSK26_Msk (0x01UL << SCT_EV4_STATE_STATEMSK26_Pos) /*!< SCT EV4_STATE: STATEMSK26 Mask */ +#define SCT_EV4_STATE_STATEMSK27_Pos 27 /*!< SCT EV4_STATE: STATEMSK27 Position */ +#define SCT_EV4_STATE_STATEMSK27_Msk (0x01UL << SCT_EV4_STATE_STATEMSK27_Pos) /*!< SCT EV4_STATE: STATEMSK27 Mask */ +#define SCT_EV4_STATE_STATEMSK28_Pos 28 /*!< SCT EV4_STATE: STATEMSK28 Position */ +#define SCT_EV4_STATE_STATEMSK28_Msk (0x01UL << SCT_EV4_STATE_STATEMSK28_Pos) /*!< SCT EV4_STATE: STATEMSK28 Mask */ +#define SCT_EV4_STATE_STATEMSK29_Pos 29 /*!< SCT EV4_STATE: STATEMSK29 Position */ +#define SCT_EV4_STATE_STATEMSK29_Msk (0x01UL << SCT_EV4_STATE_STATEMSK29_Pos) /*!< SCT EV4_STATE: STATEMSK29 Mask */ +#define SCT_EV4_STATE_STATEMSK30_Pos 30 /*!< SCT EV4_STATE: STATEMSK30 Position */ +#define SCT_EV4_STATE_STATEMSK30_Msk (0x01UL << SCT_EV4_STATE_STATEMSK30_Pos) /*!< SCT EV4_STATE: STATEMSK30 Mask */ +#define SCT_EV4_STATE_STATEMSK31_Pos 31 /*!< SCT EV4_STATE: STATEMSK31 Position */ +#define SCT_EV4_STATE_STATEMSK31_Msk (0x01UL << SCT_EV4_STATE_STATEMSK31_Pos) /*!< SCT EV4_STATE: STATEMSK31 Mask */ + +/* -------------------------------- SCT_EV4_CTRL -------------------------------- */ +#define SCT_EV4_CTRL_MATCHSEL_Pos 0 /*!< SCT EV4_CTRL: MATCHSEL Position */ +#define SCT_EV4_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV4_CTRL_MATCHSEL_Pos) /*!< SCT EV4_CTRL: MATCHSEL Mask */ +#define SCT_EV4_CTRL_HEVENT_Pos 4 /*!< SCT EV4_CTRL: HEVENT Position */ +#define SCT_EV4_CTRL_HEVENT_Msk (0x01UL << SCT_EV4_CTRL_HEVENT_Pos) /*!< SCT EV4_CTRL: HEVENT Mask */ +#define SCT_EV4_CTRL_OUTSEL_Pos 5 /*!< SCT EV4_CTRL: OUTSEL Position */ +#define SCT_EV4_CTRL_OUTSEL_Msk (0x01UL << SCT_EV4_CTRL_OUTSEL_Pos) /*!< SCT EV4_CTRL: OUTSEL Mask */ +#define SCT_EV4_CTRL_IOSEL_Pos 6 /*!< SCT EV4_CTRL: IOSEL Position */ +#define SCT_EV4_CTRL_IOSEL_Msk (0x0fUL << SCT_EV4_CTRL_IOSEL_Pos) /*!< SCT EV4_CTRL: IOSEL Mask */ +#define SCT_EV4_CTRL_IOCOND_Pos 10 /*!< SCT EV4_CTRL: IOCOND Position */ +#define SCT_EV4_CTRL_IOCOND_Msk (0x03UL << SCT_EV4_CTRL_IOCOND_Pos) /*!< SCT EV4_CTRL: IOCOND Mask */ +#define SCT_EV4_CTRL_COMBMODE_Pos 12 /*!< SCT EV4_CTRL: COMBMODE Position */ +#define SCT_EV4_CTRL_COMBMODE_Msk (0x03UL << SCT_EV4_CTRL_COMBMODE_Pos) /*!< SCT EV4_CTRL: COMBMODE Mask */ +#define SCT_EV4_CTRL_STATELD_Pos 14 /*!< SCT EV4_CTRL: STATELD Position */ +#define SCT_EV4_CTRL_STATELD_Msk (0x01UL << SCT_EV4_CTRL_STATELD_Pos) /*!< SCT EV4_CTRL: STATELD Mask */ +#define SCT_EV4_CTRL_STATEV_Pos 15 /*!< SCT EV4_CTRL: STATEV Position */ +#define SCT_EV4_CTRL_STATEV_Msk (0x1fUL << SCT_EV4_CTRL_STATEV_Pos) /*!< SCT EV4_CTRL: STATEV Mask */ +#define SCT_EV4_CTRL_MATCHMEM_Pos 20 /*!< SCT EV4_CTRL: MATCHMEM Position */ +#define SCT_EV4_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV4_CTRL_MATCHMEM_Pos) /*!< SCT EV4_CTRL: MATCHMEM Mask */ +#define SCT_EV4_CTRL_DIRECTION_Pos 21 /*!< SCT EV4_CTRL: DIRECTION Position */ +#define SCT_EV4_CTRL_DIRECTION_Msk (0x03UL << SCT_EV4_CTRL_DIRECTION_Pos) /*!< SCT EV4_CTRL: DIRECTION Mask */ + +/* -------------------------------- SCT_EV5_STATE ------------------------------- */ +#define SCT_EV5_STATE_STATEMSK0_Pos 0 /*!< SCT EV5_STATE: STATEMSK0 Position */ +#define SCT_EV5_STATE_STATEMSK0_Msk (0x01UL << SCT_EV5_STATE_STATEMSK0_Pos) /*!< SCT EV5_STATE: STATEMSK0 Mask */ +#define SCT_EV5_STATE_STATEMSK1_Pos 1 /*!< SCT EV5_STATE: STATEMSK1 Position */ +#define SCT_EV5_STATE_STATEMSK1_Msk (0x01UL << SCT_EV5_STATE_STATEMSK1_Pos) /*!< SCT EV5_STATE: STATEMSK1 Mask */ +#define SCT_EV5_STATE_STATEMSK2_Pos 2 /*!< SCT EV5_STATE: STATEMSK2 Position */ +#define SCT_EV5_STATE_STATEMSK2_Msk (0x01UL << SCT_EV5_STATE_STATEMSK2_Pos) /*!< SCT EV5_STATE: STATEMSK2 Mask */ +#define SCT_EV5_STATE_STATEMSK3_Pos 3 /*!< SCT EV5_STATE: STATEMSK3 Position */ +#define SCT_EV5_STATE_STATEMSK3_Msk (0x01UL << SCT_EV5_STATE_STATEMSK3_Pos) /*!< SCT EV5_STATE: STATEMSK3 Mask */ +#define SCT_EV5_STATE_STATEMSK4_Pos 4 /*!< SCT EV5_STATE: STATEMSK4 Position */ +#define SCT_EV5_STATE_STATEMSK4_Msk (0x01UL << SCT_EV5_STATE_STATEMSK4_Pos) /*!< SCT EV5_STATE: STATEMSK4 Mask */ +#define SCT_EV5_STATE_STATEMSK5_Pos 5 /*!< SCT EV5_STATE: STATEMSK5 Position */ +#define SCT_EV5_STATE_STATEMSK5_Msk (0x01UL << SCT_EV5_STATE_STATEMSK5_Pos) /*!< SCT EV5_STATE: STATEMSK5 Mask */ +#define SCT_EV5_STATE_STATEMSK6_Pos 6 /*!< SCT EV5_STATE: STATEMSK6 Position */ +#define SCT_EV5_STATE_STATEMSK6_Msk (0x01UL << SCT_EV5_STATE_STATEMSK6_Pos) /*!< SCT EV5_STATE: STATEMSK6 Mask */ +#define SCT_EV5_STATE_STATEMSK7_Pos 7 /*!< SCT EV5_STATE: STATEMSK7 Position */ +#define SCT_EV5_STATE_STATEMSK7_Msk (0x01UL << SCT_EV5_STATE_STATEMSK7_Pos) /*!< SCT EV5_STATE: STATEMSK7 Mask */ +#define SCT_EV5_STATE_STATEMSK8_Pos 8 /*!< SCT EV5_STATE: STATEMSK8 Position */ +#define SCT_EV5_STATE_STATEMSK8_Msk (0x01UL << SCT_EV5_STATE_STATEMSK8_Pos) /*!< SCT EV5_STATE: STATEMSK8 Mask */ +#define SCT_EV5_STATE_STATEMSK9_Pos 9 /*!< SCT EV5_STATE: STATEMSK9 Position */ +#define SCT_EV5_STATE_STATEMSK9_Msk (0x01UL << SCT_EV5_STATE_STATEMSK9_Pos) /*!< SCT EV5_STATE: STATEMSK9 Mask */ +#define SCT_EV5_STATE_STATEMSK10_Pos 10 /*!< SCT EV5_STATE: STATEMSK10 Position */ +#define SCT_EV5_STATE_STATEMSK10_Msk (0x01UL << SCT_EV5_STATE_STATEMSK10_Pos) /*!< SCT EV5_STATE: STATEMSK10 Mask */ +#define SCT_EV5_STATE_STATEMSK11_Pos 11 /*!< SCT EV5_STATE: STATEMSK11 Position */ +#define SCT_EV5_STATE_STATEMSK11_Msk (0x01UL << SCT_EV5_STATE_STATEMSK11_Pos) /*!< SCT EV5_STATE: STATEMSK11 Mask */ +#define SCT_EV5_STATE_STATEMSK12_Pos 12 /*!< SCT EV5_STATE: STATEMSK12 Position */ +#define SCT_EV5_STATE_STATEMSK12_Msk (0x01UL << SCT_EV5_STATE_STATEMSK12_Pos) /*!< SCT EV5_STATE: STATEMSK12 Mask */ +#define SCT_EV5_STATE_STATEMSK13_Pos 13 /*!< SCT EV5_STATE: STATEMSK13 Position */ +#define SCT_EV5_STATE_STATEMSK13_Msk (0x01UL << SCT_EV5_STATE_STATEMSK13_Pos) /*!< SCT EV5_STATE: STATEMSK13 Mask */ +#define SCT_EV5_STATE_STATEMSK14_Pos 14 /*!< SCT EV5_STATE: STATEMSK14 Position */ +#define SCT_EV5_STATE_STATEMSK14_Msk (0x01UL << SCT_EV5_STATE_STATEMSK14_Pos) /*!< SCT EV5_STATE: STATEMSK14 Mask */ +#define SCT_EV5_STATE_STATEMSK15_Pos 15 /*!< SCT EV5_STATE: STATEMSK15 Position */ +#define SCT_EV5_STATE_STATEMSK15_Msk (0x01UL << SCT_EV5_STATE_STATEMSK15_Pos) /*!< SCT EV5_STATE: STATEMSK15 Mask */ +#define SCT_EV5_STATE_STATEMSK16_Pos 16 /*!< SCT EV5_STATE: STATEMSK16 Position */ +#define SCT_EV5_STATE_STATEMSK16_Msk (0x01UL << SCT_EV5_STATE_STATEMSK16_Pos) /*!< SCT EV5_STATE: STATEMSK16 Mask */ +#define SCT_EV5_STATE_STATEMSK17_Pos 17 /*!< SCT EV5_STATE: STATEMSK17 Position */ +#define SCT_EV5_STATE_STATEMSK17_Msk (0x01UL << SCT_EV5_STATE_STATEMSK17_Pos) /*!< SCT EV5_STATE: STATEMSK17 Mask */ +#define SCT_EV5_STATE_STATEMSK18_Pos 18 /*!< SCT EV5_STATE: STATEMSK18 Position */ +#define SCT_EV5_STATE_STATEMSK18_Msk (0x01UL << SCT_EV5_STATE_STATEMSK18_Pos) /*!< SCT EV5_STATE: STATEMSK18 Mask */ +#define SCT_EV5_STATE_STATEMSK19_Pos 19 /*!< SCT EV5_STATE: STATEMSK19 Position */ +#define SCT_EV5_STATE_STATEMSK19_Msk (0x01UL << SCT_EV5_STATE_STATEMSK19_Pos) /*!< SCT EV5_STATE: STATEMSK19 Mask */ +#define SCT_EV5_STATE_STATEMSK20_Pos 20 /*!< SCT EV5_STATE: STATEMSK20 Position */ +#define SCT_EV5_STATE_STATEMSK20_Msk (0x01UL << SCT_EV5_STATE_STATEMSK20_Pos) /*!< SCT EV5_STATE: STATEMSK20 Mask */ +#define SCT_EV5_STATE_STATEMSK21_Pos 21 /*!< SCT EV5_STATE: STATEMSK21 Position */ +#define SCT_EV5_STATE_STATEMSK21_Msk (0x01UL << SCT_EV5_STATE_STATEMSK21_Pos) /*!< SCT EV5_STATE: STATEMSK21 Mask */ +#define SCT_EV5_STATE_STATEMSK22_Pos 22 /*!< SCT EV5_STATE: STATEMSK22 Position */ +#define SCT_EV5_STATE_STATEMSK22_Msk (0x01UL << SCT_EV5_STATE_STATEMSK22_Pos) /*!< SCT EV5_STATE: STATEMSK22 Mask */ +#define SCT_EV5_STATE_STATEMSK23_Pos 23 /*!< SCT EV5_STATE: STATEMSK23 Position */ +#define SCT_EV5_STATE_STATEMSK23_Msk (0x01UL << SCT_EV5_STATE_STATEMSK23_Pos) /*!< SCT EV5_STATE: STATEMSK23 Mask */ +#define SCT_EV5_STATE_STATEMSK24_Pos 24 /*!< SCT EV5_STATE: STATEMSK24 Position */ +#define SCT_EV5_STATE_STATEMSK24_Msk (0x01UL << SCT_EV5_STATE_STATEMSK24_Pos) /*!< SCT EV5_STATE: STATEMSK24 Mask */ +#define SCT_EV5_STATE_STATEMSK25_Pos 25 /*!< SCT EV5_STATE: STATEMSK25 Position */ +#define SCT_EV5_STATE_STATEMSK25_Msk (0x01UL << SCT_EV5_STATE_STATEMSK25_Pos) /*!< SCT EV5_STATE: STATEMSK25 Mask */ +#define SCT_EV5_STATE_STATEMSK26_Pos 26 /*!< SCT EV5_STATE: STATEMSK26 Position */ +#define SCT_EV5_STATE_STATEMSK26_Msk (0x01UL << SCT_EV5_STATE_STATEMSK26_Pos) /*!< SCT EV5_STATE: STATEMSK26 Mask */ +#define SCT_EV5_STATE_STATEMSK27_Pos 27 /*!< SCT EV5_STATE: STATEMSK27 Position */ +#define SCT_EV5_STATE_STATEMSK27_Msk (0x01UL << SCT_EV5_STATE_STATEMSK27_Pos) /*!< SCT EV5_STATE: STATEMSK27 Mask */ +#define SCT_EV5_STATE_STATEMSK28_Pos 28 /*!< SCT EV5_STATE: STATEMSK28 Position */ +#define SCT_EV5_STATE_STATEMSK28_Msk (0x01UL << SCT_EV5_STATE_STATEMSK28_Pos) /*!< SCT EV5_STATE: STATEMSK28 Mask */ +#define SCT_EV5_STATE_STATEMSK29_Pos 29 /*!< SCT EV5_STATE: STATEMSK29 Position */ +#define SCT_EV5_STATE_STATEMSK29_Msk (0x01UL << SCT_EV5_STATE_STATEMSK29_Pos) /*!< SCT EV5_STATE: STATEMSK29 Mask */ +#define SCT_EV5_STATE_STATEMSK30_Pos 30 /*!< SCT EV5_STATE: STATEMSK30 Position */ +#define SCT_EV5_STATE_STATEMSK30_Msk (0x01UL << SCT_EV5_STATE_STATEMSK30_Pos) /*!< SCT EV5_STATE: STATEMSK30 Mask */ +#define SCT_EV5_STATE_STATEMSK31_Pos 31 /*!< SCT EV5_STATE: STATEMSK31 Position */ +#define SCT_EV5_STATE_STATEMSK31_Msk (0x01UL << SCT_EV5_STATE_STATEMSK31_Pos) /*!< SCT EV5_STATE: STATEMSK31 Mask */ + +/* -------------------------------- SCT_EV5_CTRL -------------------------------- */ +#define SCT_EV5_CTRL_MATCHSEL_Pos 0 /*!< SCT EV5_CTRL: MATCHSEL Position */ +#define SCT_EV5_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV5_CTRL_MATCHSEL_Pos) /*!< SCT EV5_CTRL: MATCHSEL Mask */ +#define SCT_EV5_CTRL_HEVENT_Pos 4 /*!< SCT EV5_CTRL: HEVENT Position */ +#define SCT_EV5_CTRL_HEVENT_Msk (0x01UL << SCT_EV5_CTRL_HEVENT_Pos) /*!< SCT EV5_CTRL: HEVENT Mask */ +#define SCT_EV5_CTRL_OUTSEL_Pos 5 /*!< SCT EV5_CTRL: OUTSEL Position */ +#define SCT_EV5_CTRL_OUTSEL_Msk (0x01UL << SCT_EV5_CTRL_OUTSEL_Pos) /*!< SCT EV5_CTRL: OUTSEL Mask */ +#define SCT_EV5_CTRL_IOSEL_Pos 6 /*!< SCT EV5_CTRL: IOSEL Position */ +#define SCT_EV5_CTRL_IOSEL_Msk (0x0fUL << SCT_EV5_CTRL_IOSEL_Pos) /*!< SCT EV5_CTRL: IOSEL Mask */ +#define SCT_EV5_CTRL_IOCOND_Pos 10 /*!< SCT EV5_CTRL: IOCOND Position */ +#define SCT_EV5_CTRL_IOCOND_Msk (0x03UL << SCT_EV5_CTRL_IOCOND_Pos) /*!< SCT EV5_CTRL: IOCOND Mask */ +#define SCT_EV5_CTRL_COMBMODE_Pos 12 /*!< SCT EV5_CTRL: COMBMODE Position */ +#define SCT_EV5_CTRL_COMBMODE_Msk (0x03UL << SCT_EV5_CTRL_COMBMODE_Pos) /*!< SCT EV5_CTRL: COMBMODE Mask */ +#define SCT_EV5_CTRL_STATELD_Pos 14 /*!< SCT EV5_CTRL: STATELD Position */ +#define SCT_EV5_CTRL_STATELD_Msk (0x01UL << SCT_EV5_CTRL_STATELD_Pos) /*!< SCT EV5_CTRL: STATELD Mask */ +#define SCT_EV5_CTRL_STATEV_Pos 15 /*!< SCT EV5_CTRL: STATEV Position */ +#define SCT_EV5_CTRL_STATEV_Msk (0x1fUL << SCT_EV5_CTRL_STATEV_Pos) /*!< SCT EV5_CTRL: STATEV Mask */ +#define SCT_EV5_CTRL_MATCHMEM_Pos 20 /*!< SCT EV5_CTRL: MATCHMEM Position */ +#define SCT_EV5_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV5_CTRL_MATCHMEM_Pos) /*!< SCT EV5_CTRL: MATCHMEM Mask */ +#define SCT_EV5_CTRL_DIRECTION_Pos 21 /*!< SCT EV5_CTRL: DIRECTION Position */ +#define SCT_EV5_CTRL_DIRECTION_Msk (0x03UL << SCT_EV5_CTRL_DIRECTION_Pos) /*!< SCT EV5_CTRL: DIRECTION Mask */ + +/* -------------------------------- SCT_EV6_STATE ------------------------------- */ +#define SCT_EV6_STATE_STATEMSK0_Pos 0 /*!< SCT EV6_STATE: STATEMSK0 Position */ +#define SCT_EV6_STATE_STATEMSK0_Msk (0x01UL << SCT_EV6_STATE_STATEMSK0_Pos) /*!< SCT EV6_STATE: STATEMSK0 Mask */ +#define SCT_EV6_STATE_STATEMSK1_Pos 1 /*!< SCT EV6_STATE: STATEMSK1 Position */ +#define SCT_EV6_STATE_STATEMSK1_Msk (0x01UL << SCT_EV6_STATE_STATEMSK1_Pos) /*!< SCT EV6_STATE: STATEMSK1 Mask */ +#define SCT_EV6_STATE_STATEMSK2_Pos 2 /*!< SCT EV6_STATE: STATEMSK2 Position */ +#define SCT_EV6_STATE_STATEMSK2_Msk (0x01UL << SCT_EV6_STATE_STATEMSK2_Pos) /*!< SCT EV6_STATE: STATEMSK2 Mask */ +#define SCT_EV6_STATE_STATEMSK3_Pos 3 /*!< SCT EV6_STATE: STATEMSK3 Position */ +#define SCT_EV6_STATE_STATEMSK3_Msk (0x01UL << SCT_EV6_STATE_STATEMSK3_Pos) /*!< SCT EV6_STATE: STATEMSK3 Mask */ +#define SCT_EV6_STATE_STATEMSK4_Pos 4 /*!< SCT EV6_STATE: STATEMSK4 Position */ +#define SCT_EV6_STATE_STATEMSK4_Msk (0x01UL << SCT_EV6_STATE_STATEMSK4_Pos) /*!< SCT EV6_STATE: STATEMSK4 Mask */ +#define SCT_EV6_STATE_STATEMSK5_Pos 5 /*!< SCT EV6_STATE: STATEMSK5 Position */ +#define SCT_EV6_STATE_STATEMSK5_Msk (0x01UL << SCT_EV6_STATE_STATEMSK5_Pos) /*!< SCT EV6_STATE: STATEMSK5 Mask */ +#define SCT_EV6_STATE_STATEMSK6_Pos 6 /*!< SCT EV6_STATE: STATEMSK6 Position */ +#define SCT_EV6_STATE_STATEMSK6_Msk (0x01UL << SCT_EV6_STATE_STATEMSK6_Pos) /*!< SCT EV6_STATE: STATEMSK6 Mask */ +#define SCT_EV6_STATE_STATEMSK7_Pos 7 /*!< SCT EV6_STATE: STATEMSK7 Position */ +#define SCT_EV6_STATE_STATEMSK7_Msk (0x01UL << SCT_EV6_STATE_STATEMSK7_Pos) /*!< SCT EV6_STATE: STATEMSK7 Mask */ +#define SCT_EV6_STATE_STATEMSK8_Pos 8 /*!< SCT EV6_STATE: STATEMSK8 Position */ +#define SCT_EV6_STATE_STATEMSK8_Msk (0x01UL << SCT_EV6_STATE_STATEMSK8_Pos) /*!< SCT EV6_STATE: STATEMSK8 Mask */ +#define SCT_EV6_STATE_STATEMSK9_Pos 9 /*!< SCT EV6_STATE: STATEMSK9 Position */ +#define SCT_EV6_STATE_STATEMSK9_Msk (0x01UL << SCT_EV6_STATE_STATEMSK9_Pos) /*!< SCT EV6_STATE: STATEMSK9 Mask */ +#define SCT_EV6_STATE_STATEMSK10_Pos 10 /*!< SCT EV6_STATE: STATEMSK10 Position */ +#define SCT_EV6_STATE_STATEMSK10_Msk (0x01UL << SCT_EV6_STATE_STATEMSK10_Pos) /*!< SCT EV6_STATE: STATEMSK10 Mask */ +#define SCT_EV6_STATE_STATEMSK11_Pos 11 /*!< SCT EV6_STATE: STATEMSK11 Position */ +#define SCT_EV6_STATE_STATEMSK11_Msk (0x01UL << SCT_EV6_STATE_STATEMSK11_Pos) /*!< SCT EV6_STATE: STATEMSK11 Mask */ +#define SCT_EV6_STATE_STATEMSK12_Pos 12 /*!< SCT EV6_STATE: STATEMSK12 Position */ +#define SCT_EV6_STATE_STATEMSK12_Msk (0x01UL << SCT_EV6_STATE_STATEMSK12_Pos) /*!< SCT EV6_STATE: STATEMSK12 Mask */ +#define SCT_EV6_STATE_STATEMSK13_Pos 13 /*!< SCT EV6_STATE: STATEMSK13 Position */ +#define SCT_EV6_STATE_STATEMSK13_Msk (0x01UL << SCT_EV6_STATE_STATEMSK13_Pos) /*!< SCT EV6_STATE: STATEMSK13 Mask */ +#define SCT_EV6_STATE_STATEMSK14_Pos 14 /*!< SCT EV6_STATE: STATEMSK14 Position */ +#define SCT_EV6_STATE_STATEMSK14_Msk (0x01UL << SCT_EV6_STATE_STATEMSK14_Pos) /*!< SCT EV6_STATE: STATEMSK14 Mask */ +#define SCT_EV6_STATE_STATEMSK15_Pos 15 /*!< SCT EV6_STATE: STATEMSK15 Position */ +#define SCT_EV6_STATE_STATEMSK15_Msk (0x01UL << SCT_EV6_STATE_STATEMSK15_Pos) /*!< SCT EV6_STATE: STATEMSK15 Mask */ +#define SCT_EV6_STATE_STATEMSK16_Pos 16 /*!< SCT EV6_STATE: STATEMSK16 Position */ +#define SCT_EV6_STATE_STATEMSK16_Msk (0x01UL << SCT_EV6_STATE_STATEMSK16_Pos) /*!< SCT EV6_STATE: STATEMSK16 Mask */ +#define SCT_EV6_STATE_STATEMSK17_Pos 17 /*!< SCT EV6_STATE: STATEMSK17 Position */ +#define SCT_EV6_STATE_STATEMSK17_Msk (0x01UL << SCT_EV6_STATE_STATEMSK17_Pos) /*!< SCT EV6_STATE: STATEMSK17 Mask */ +#define SCT_EV6_STATE_STATEMSK18_Pos 18 /*!< SCT EV6_STATE: STATEMSK18 Position */ +#define SCT_EV6_STATE_STATEMSK18_Msk (0x01UL << SCT_EV6_STATE_STATEMSK18_Pos) /*!< SCT EV6_STATE: STATEMSK18 Mask */ +#define SCT_EV6_STATE_STATEMSK19_Pos 19 /*!< SCT EV6_STATE: STATEMSK19 Position */ +#define SCT_EV6_STATE_STATEMSK19_Msk (0x01UL << SCT_EV6_STATE_STATEMSK19_Pos) /*!< SCT EV6_STATE: STATEMSK19 Mask */ +#define SCT_EV6_STATE_STATEMSK20_Pos 20 /*!< SCT EV6_STATE: STATEMSK20 Position */ +#define SCT_EV6_STATE_STATEMSK20_Msk (0x01UL << SCT_EV6_STATE_STATEMSK20_Pos) /*!< SCT EV6_STATE: STATEMSK20 Mask */ +#define SCT_EV6_STATE_STATEMSK21_Pos 21 /*!< SCT EV6_STATE: STATEMSK21 Position */ +#define SCT_EV6_STATE_STATEMSK21_Msk (0x01UL << SCT_EV6_STATE_STATEMSK21_Pos) /*!< SCT EV6_STATE: STATEMSK21 Mask */ +#define SCT_EV6_STATE_STATEMSK22_Pos 22 /*!< SCT EV6_STATE: STATEMSK22 Position */ +#define SCT_EV6_STATE_STATEMSK22_Msk (0x01UL << SCT_EV6_STATE_STATEMSK22_Pos) /*!< SCT EV6_STATE: STATEMSK22 Mask */ +#define SCT_EV6_STATE_STATEMSK23_Pos 23 /*!< SCT EV6_STATE: STATEMSK23 Position */ +#define SCT_EV6_STATE_STATEMSK23_Msk (0x01UL << SCT_EV6_STATE_STATEMSK23_Pos) /*!< SCT EV6_STATE: STATEMSK23 Mask */ +#define SCT_EV6_STATE_STATEMSK24_Pos 24 /*!< SCT EV6_STATE: STATEMSK24 Position */ +#define SCT_EV6_STATE_STATEMSK24_Msk (0x01UL << SCT_EV6_STATE_STATEMSK24_Pos) /*!< SCT EV6_STATE: STATEMSK24 Mask */ +#define SCT_EV6_STATE_STATEMSK25_Pos 25 /*!< SCT EV6_STATE: STATEMSK25 Position */ +#define SCT_EV6_STATE_STATEMSK25_Msk (0x01UL << SCT_EV6_STATE_STATEMSK25_Pos) /*!< SCT EV6_STATE: STATEMSK25 Mask */ +#define SCT_EV6_STATE_STATEMSK26_Pos 26 /*!< SCT EV6_STATE: STATEMSK26 Position */ +#define SCT_EV6_STATE_STATEMSK26_Msk (0x01UL << SCT_EV6_STATE_STATEMSK26_Pos) /*!< SCT EV6_STATE: STATEMSK26 Mask */ +#define SCT_EV6_STATE_STATEMSK27_Pos 27 /*!< SCT EV6_STATE: STATEMSK27 Position */ +#define SCT_EV6_STATE_STATEMSK27_Msk (0x01UL << SCT_EV6_STATE_STATEMSK27_Pos) /*!< SCT EV6_STATE: STATEMSK27 Mask */ +#define SCT_EV6_STATE_STATEMSK28_Pos 28 /*!< SCT EV6_STATE: STATEMSK28 Position */ +#define SCT_EV6_STATE_STATEMSK28_Msk (0x01UL << SCT_EV6_STATE_STATEMSK28_Pos) /*!< SCT EV6_STATE: STATEMSK28 Mask */ +#define SCT_EV6_STATE_STATEMSK29_Pos 29 /*!< SCT EV6_STATE: STATEMSK29 Position */ +#define SCT_EV6_STATE_STATEMSK29_Msk (0x01UL << SCT_EV6_STATE_STATEMSK29_Pos) /*!< SCT EV6_STATE: STATEMSK29 Mask */ +#define SCT_EV6_STATE_STATEMSK30_Pos 30 /*!< SCT EV6_STATE: STATEMSK30 Position */ +#define SCT_EV6_STATE_STATEMSK30_Msk (0x01UL << SCT_EV6_STATE_STATEMSK30_Pos) /*!< SCT EV6_STATE: STATEMSK30 Mask */ +#define SCT_EV6_STATE_STATEMSK31_Pos 31 /*!< SCT EV6_STATE: STATEMSK31 Position */ +#define SCT_EV6_STATE_STATEMSK31_Msk (0x01UL << SCT_EV6_STATE_STATEMSK31_Pos) /*!< SCT EV6_STATE: STATEMSK31 Mask */ + +/* -------------------------------- SCT_EV6_CTRL -------------------------------- */ +#define SCT_EV6_CTRL_MATCHSEL_Pos 0 /*!< SCT EV6_CTRL: MATCHSEL Position */ +#define SCT_EV6_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV6_CTRL_MATCHSEL_Pos) /*!< SCT EV6_CTRL: MATCHSEL Mask */ +#define SCT_EV6_CTRL_HEVENT_Pos 4 /*!< SCT EV6_CTRL: HEVENT Position */ +#define SCT_EV6_CTRL_HEVENT_Msk (0x01UL << SCT_EV6_CTRL_HEVENT_Pos) /*!< SCT EV6_CTRL: HEVENT Mask */ +#define SCT_EV6_CTRL_OUTSEL_Pos 5 /*!< SCT EV6_CTRL: OUTSEL Position */ +#define SCT_EV6_CTRL_OUTSEL_Msk (0x01UL << SCT_EV6_CTRL_OUTSEL_Pos) /*!< SCT EV6_CTRL: OUTSEL Mask */ +#define SCT_EV6_CTRL_IOSEL_Pos 6 /*!< SCT EV6_CTRL: IOSEL Position */ +#define SCT_EV6_CTRL_IOSEL_Msk (0x0fUL << SCT_EV6_CTRL_IOSEL_Pos) /*!< SCT EV6_CTRL: IOSEL Mask */ +#define SCT_EV6_CTRL_IOCOND_Pos 10 /*!< SCT EV6_CTRL: IOCOND Position */ +#define SCT_EV6_CTRL_IOCOND_Msk (0x03UL << SCT_EV6_CTRL_IOCOND_Pos) /*!< SCT EV6_CTRL: IOCOND Mask */ +#define SCT_EV6_CTRL_COMBMODE_Pos 12 /*!< SCT EV6_CTRL: COMBMODE Position */ +#define SCT_EV6_CTRL_COMBMODE_Msk (0x03UL << SCT_EV6_CTRL_COMBMODE_Pos) /*!< SCT EV6_CTRL: COMBMODE Mask */ +#define SCT_EV6_CTRL_STATELD_Pos 14 /*!< SCT EV6_CTRL: STATELD Position */ +#define SCT_EV6_CTRL_STATELD_Msk (0x01UL << SCT_EV6_CTRL_STATELD_Pos) /*!< SCT EV6_CTRL: STATELD Mask */ +#define SCT_EV6_CTRL_STATEV_Pos 15 /*!< SCT EV6_CTRL: STATEV Position */ +#define SCT_EV6_CTRL_STATEV_Msk (0x1fUL << SCT_EV6_CTRL_STATEV_Pos) /*!< SCT EV6_CTRL: STATEV Mask */ +#define SCT_EV6_CTRL_MATCHMEM_Pos 20 /*!< SCT EV6_CTRL: MATCHMEM Position */ +#define SCT_EV6_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV6_CTRL_MATCHMEM_Pos) /*!< SCT EV6_CTRL: MATCHMEM Mask */ +#define SCT_EV6_CTRL_DIRECTION_Pos 21 /*!< SCT EV6_CTRL: DIRECTION Position */ +#define SCT_EV6_CTRL_DIRECTION_Msk (0x03UL << SCT_EV6_CTRL_DIRECTION_Pos) /*!< SCT EV6_CTRL: DIRECTION Mask */ + +/* -------------------------------- SCT_EV7_STATE ------------------------------- */ +#define SCT_EV7_STATE_STATEMSK0_Pos 0 /*!< SCT EV7_STATE: STATEMSK0 Position */ +#define SCT_EV7_STATE_STATEMSK0_Msk (0x01UL << SCT_EV7_STATE_STATEMSK0_Pos) /*!< SCT EV7_STATE: STATEMSK0 Mask */ +#define SCT_EV7_STATE_STATEMSK1_Pos 1 /*!< SCT EV7_STATE: STATEMSK1 Position */ +#define SCT_EV7_STATE_STATEMSK1_Msk (0x01UL << SCT_EV7_STATE_STATEMSK1_Pos) /*!< SCT EV7_STATE: STATEMSK1 Mask */ +#define SCT_EV7_STATE_STATEMSK2_Pos 2 /*!< SCT EV7_STATE: STATEMSK2 Position */ +#define SCT_EV7_STATE_STATEMSK2_Msk (0x01UL << SCT_EV7_STATE_STATEMSK2_Pos) /*!< SCT EV7_STATE: STATEMSK2 Mask */ +#define SCT_EV7_STATE_STATEMSK3_Pos 3 /*!< SCT EV7_STATE: STATEMSK3 Position */ +#define SCT_EV7_STATE_STATEMSK3_Msk (0x01UL << SCT_EV7_STATE_STATEMSK3_Pos) /*!< SCT EV7_STATE: STATEMSK3 Mask */ +#define SCT_EV7_STATE_STATEMSK4_Pos 4 /*!< SCT EV7_STATE: STATEMSK4 Position */ +#define SCT_EV7_STATE_STATEMSK4_Msk (0x01UL << SCT_EV7_STATE_STATEMSK4_Pos) /*!< SCT EV7_STATE: STATEMSK4 Mask */ +#define SCT_EV7_STATE_STATEMSK5_Pos 5 /*!< SCT EV7_STATE: STATEMSK5 Position */ +#define SCT_EV7_STATE_STATEMSK5_Msk (0x01UL << SCT_EV7_STATE_STATEMSK5_Pos) /*!< SCT EV7_STATE: STATEMSK5 Mask */ +#define SCT_EV7_STATE_STATEMSK6_Pos 6 /*!< SCT EV7_STATE: STATEMSK6 Position */ +#define SCT_EV7_STATE_STATEMSK6_Msk (0x01UL << SCT_EV7_STATE_STATEMSK6_Pos) /*!< SCT EV7_STATE: STATEMSK6 Mask */ +#define SCT_EV7_STATE_STATEMSK7_Pos 7 /*!< SCT EV7_STATE: STATEMSK7 Position */ +#define SCT_EV7_STATE_STATEMSK7_Msk (0x01UL << SCT_EV7_STATE_STATEMSK7_Pos) /*!< SCT EV7_STATE: STATEMSK7 Mask */ +#define SCT_EV7_STATE_STATEMSK8_Pos 8 /*!< SCT EV7_STATE: STATEMSK8 Position */ +#define SCT_EV7_STATE_STATEMSK8_Msk (0x01UL << SCT_EV7_STATE_STATEMSK8_Pos) /*!< SCT EV7_STATE: STATEMSK8 Mask */ +#define SCT_EV7_STATE_STATEMSK9_Pos 9 /*!< SCT EV7_STATE: STATEMSK9 Position */ +#define SCT_EV7_STATE_STATEMSK9_Msk (0x01UL << SCT_EV7_STATE_STATEMSK9_Pos) /*!< SCT EV7_STATE: STATEMSK9 Mask */ +#define SCT_EV7_STATE_STATEMSK10_Pos 10 /*!< SCT EV7_STATE: STATEMSK10 Position */ +#define SCT_EV7_STATE_STATEMSK10_Msk (0x01UL << SCT_EV7_STATE_STATEMSK10_Pos) /*!< SCT EV7_STATE: STATEMSK10 Mask */ +#define SCT_EV7_STATE_STATEMSK11_Pos 11 /*!< SCT EV7_STATE: STATEMSK11 Position */ +#define SCT_EV7_STATE_STATEMSK11_Msk (0x01UL << SCT_EV7_STATE_STATEMSK11_Pos) /*!< SCT EV7_STATE: STATEMSK11 Mask */ +#define SCT_EV7_STATE_STATEMSK12_Pos 12 /*!< SCT EV7_STATE: STATEMSK12 Position */ +#define SCT_EV7_STATE_STATEMSK12_Msk (0x01UL << SCT_EV7_STATE_STATEMSK12_Pos) /*!< SCT EV7_STATE: STATEMSK12 Mask */ +#define SCT_EV7_STATE_STATEMSK13_Pos 13 /*!< SCT EV7_STATE: STATEMSK13 Position */ +#define SCT_EV7_STATE_STATEMSK13_Msk (0x01UL << SCT_EV7_STATE_STATEMSK13_Pos) /*!< SCT EV7_STATE: STATEMSK13 Mask */ +#define SCT_EV7_STATE_STATEMSK14_Pos 14 /*!< SCT EV7_STATE: STATEMSK14 Position */ +#define SCT_EV7_STATE_STATEMSK14_Msk (0x01UL << SCT_EV7_STATE_STATEMSK14_Pos) /*!< SCT EV7_STATE: STATEMSK14 Mask */ +#define SCT_EV7_STATE_STATEMSK15_Pos 15 /*!< SCT EV7_STATE: STATEMSK15 Position */ +#define SCT_EV7_STATE_STATEMSK15_Msk (0x01UL << SCT_EV7_STATE_STATEMSK15_Pos) /*!< SCT EV7_STATE: STATEMSK15 Mask */ +#define SCT_EV7_STATE_STATEMSK16_Pos 16 /*!< SCT EV7_STATE: STATEMSK16 Position */ +#define SCT_EV7_STATE_STATEMSK16_Msk (0x01UL << SCT_EV7_STATE_STATEMSK16_Pos) /*!< SCT EV7_STATE: STATEMSK16 Mask */ +#define SCT_EV7_STATE_STATEMSK17_Pos 17 /*!< SCT EV7_STATE: STATEMSK17 Position */ +#define SCT_EV7_STATE_STATEMSK17_Msk (0x01UL << SCT_EV7_STATE_STATEMSK17_Pos) /*!< SCT EV7_STATE: STATEMSK17 Mask */ +#define SCT_EV7_STATE_STATEMSK18_Pos 18 /*!< SCT EV7_STATE: STATEMSK18 Position */ +#define SCT_EV7_STATE_STATEMSK18_Msk (0x01UL << SCT_EV7_STATE_STATEMSK18_Pos) /*!< SCT EV7_STATE: STATEMSK18 Mask */ +#define SCT_EV7_STATE_STATEMSK19_Pos 19 /*!< SCT EV7_STATE: STATEMSK19 Position */ +#define SCT_EV7_STATE_STATEMSK19_Msk (0x01UL << SCT_EV7_STATE_STATEMSK19_Pos) /*!< SCT EV7_STATE: STATEMSK19 Mask */ +#define SCT_EV7_STATE_STATEMSK20_Pos 20 /*!< SCT EV7_STATE: STATEMSK20 Position */ +#define SCT_EV7_STATE_STATEMSK20_Msk (0x01UL << SCT_EV7_STATE_STATEMSK20_Pos) /*!< SCT EV7_STATE: STATEMSK20 Mask */ +#define SCT_EV7_STATE_STATEMSK21_Pos 21 /*!< SCT EV7_STATE: STATEMSK21 Position */ +#define SCT_EV7_STATE_STATEMSK21_Msk (0x01UL << SCT_EV7_STATE_STATEMSK21_Pos) /*!< SCT EV7_STATE: STATEMSK21 Mask */ +#define SCT_EV7_STATE_STATEMSK22_Pos 22 /*!< SCT EV7_STATE: STATEMSK22 Position */ +#define SCT_EV7_STATE_STATEMSK22_Msk (0x01UL << SCT_EV7_STATE_STATEMSK22_Pos) /*!< SCT EV7_STATE: STATEMSK22 Mask */ +#define SCT_EV7_STATE_STATEMSK23_Pos 23 /*!< SCT EV7_STATE: STATEMSK23 Position */ +#define SCT_EV7_STATE_STATEMSK23_Msk (0x01UL << SCT_EV7_STATE_STATEMSK23_Pos) /*!< SCT EV7_STATE: STATEMSK23 Mask */ +#define SCT_EV7_STATE_STATEMSK24_Pos 24 /*!< SCT EV7_STATE: STATEMSK24 Position */ +#define SCT_EV7_STATE_STATEMSK24_Msk (0x01UL << SCT_EV7_STATE_STATEMSK24_Pos) /*!< SCT EV7_STATE: STATEMSK24 Mask */ +#define SCT_EV7_STATE_STATEMSK25_Pos 25 /*!< SCT EV7_STATE: STATEMSK25 Position */ +#define SCT_EV7_STATE_STATEMSK25_Msk (0x01UL << SCT_EV7_STATE_STATEMSK25_Pos) /*!< SCT EV7_STATE: STATEMSK25 Mask */ +#define SCT_EV7_STATE_STATEMSK26_Pos 26 /*!< SCT EV7_STATE: STATEMSK26 Position */ +#define SCT_EV7_STATE_STATEMSK26_Msk (0x01UL << SCT_EV7_STATE_STATEMSK26_Pos) /*!< SCT EV7_STATE: STATEMSK26 Mask */ +#define SCT_EV7_STATE_STATEMSK27_Pos 27 /*!< SCT EV7_STATE: STATEMSK27 Position */ +#define SCT_EV7_STATE_STATEMSK27_Msk (0x01UL << SCT_EV7_STATE_STATEMSK27_Pos) /*!< SCT EV7_STATE: STATEMSK27 Mask */ +#define SCT_EV7_STATE_STATEMSK28_Pos 28 /*!< SCT EV7_STATE: STATEMSK28 Position */ +#define SCT_EV7_STATE_STATEMSK28_Msk (0x01UL << SCT_EV7_STATE_STATEMSK28_Pos) /*!< SCT EV7_STATE: STATEMSK28 Mask */ +#define SCT_EV7_STATE_STATEMSK29_Pos 29 /*!< SCT EV7_STATE: STATEMSK29 Position */ +#define SCT_EV7_STATE_STATEMSK29_Msk (0x01UL << SCT_EV7_STATE_STATEMSK29_Pos) /*!< SCT EV7_STATE: STATEMSK29 Mask */ +#define SCT_EV7_STATE_STATEMSK30_Pos 30 /*!< SCT EV7_STATE: STATEMSK30 Position */ +#define SCT_EV7_STATE_STATEMSK30_Msk (0x01UL << SCT_EV7_STATE_STATEMSK30_Pos) /*!< SCT EV7_STATE: STATEMSK30 Mask */ +#define SCT_EV7_STATE_STATEMSK31_Pos 31 /*!< SCT EV7_STATE: STATEMSK31 Position */ +#define SCT_EV7_STATE_STATEMSK31_Msk (0x01UL << SCT_EV7_STATE_STATEMSK31_Pos) /*!< SCT EV7_STATE: STATEMSK31 Mask */ + +/* -------------------------------- SCT_EV7_CTRL -------------------------------- */ +#define SCT_EV7_CTRL_MATCHSEL_Pos 0 /*!< SCT EV7_CTRL: MATCHSEL Position */ +#define SCT_EV7_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV7_CTRL_MATCHSEL_Pos) /*!< SCT EV7_CTRL: MATCHSEL Mask */ +#define SCT_EV7_CTRL_HEVENT_Pos 4 /*!< SCT EV7_CTRL: HEVENT Position */ +#define SCT_EV7_CTRL_HEVENT_Msk (0x01UL << SCT_EV7_CTRL_HEVENT_Pos) /*!< SCT EV7_CTRL: HEVENT Mask */ +#define SCT_EV7_CTRL_OUTSEL_Pos 5 /*!< SCT EV7_CTRL: OUTSEL Position */ +#define SCT_EV7_CTRL_OUTSEL_Msk (0x01UL << SCT_EV7_CTRL_OUTSEL_Pos) /*!< SCT EV7_CTRL: OUTSEL Mask */ +#define SCT_EV7_CTRL_IOSEL_Pos 6 /*!< SCT EV7_CTRL: IOSEL Position */ +#define SCT_EV7_CTRL_IOSEL_Msk (0x0fUL << SCT_EV7_CTRL_IOSEL_Pos) /*!< SCT EV7_CTRL: IOSEL Mask */ +#define SCT_EV7_CTRL_IOCOND_Pos 10 /*!< SCT EV7_CTRL: IOCOND Position */ +#define SCT_EV7_CTRL_IOCOND_Msk (0x03UL << SCT_EV7_CTRL_IOCOND_Pos) /*!< SCT EV7_CTRL: IOCOND Mask */ +#define SCT_EV7_CTRL_COMBMODE_Pos 12 /*!< SCT EV7_CTRL: COMBMODE Position */ +#define SCT_EV7_CTRL_COMBMODE_Msk (0x03UL << SCT_EV7_CTRL_COMBMODE_Pos) /*!< SCT EV7_CTRL: COMBMODE Mask */ +#define SCT_EV7_CTRL_STATELD_Pos 14 /*!< SCT EV7_CTRL: STATELD Position */ +#define SCT_EV7_CTRL_STATELD_Msk (0x01UL << SCT_EV7_CTRL_STATELD_Pos) /*!< SCT EV7_CTRL: STATELD Mask */ +#define SCT_EV7_CTRL_STATEV_Pos 15 /*!< SCT EV7_CTRL: STATEV Position */ +#define SCT_EV7_CTRL_STATEV_Msk (0x1fUL << SCT_EV7_CTRL_STATEV_Pos) /*!< SCT EV7_CTRL: STATEV Mask */ +#define SCT_EV7_CTRL_MATCHMEM_Pos 20 /*!< SCT EV7_CTRL: MATCHMEM Position */ +#define SCT_EV7_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV7_CTRL_MATCHMEM_Pos) /*!< SCT EV7_CTRL: MATCHMEM Mask */ +#define SCT_EV7_CTRL_DIRECTION_Pos 21 /*!< SCT EV7_CTRL: DIRECTION Position */ +#define SCT_EV7_CTRL_DIRECTION_Msk (0x03UL << SCT_EV7_CTRL_DIRECTION_Pos) /*!< SCT EV7_CTRL: DIRECTION Mask */ + +/* -------------------------------- SCT_EV8_STATE ------------------------------- */ +#define SCT_EV8_STATE_STATEMSK0_Pos 0 /*!< SCT EV8_STATE: STATEMSK0 Position */ +#define SCT_EV8_STATE_STATEMSK0_Msk (0x01UL << SCT_EV8_STATE_STATEMSK0_Pos) /*!< SCT EV8_STATE: STATEMSK0 Mask */ +#define SCT_EV8_STATE_STATEMSK1_Pos 1 /*!< SCT EV8_STATE: STATEMSK1 Position */ +#define SCT_EV8_STATE_STATEMSK1_Msk (0x01UL << SCT_EV8_STATE_STATEMSK1_Pos) /*!< SCT EV8_STATE: STATEMSK1 Mask */ +#define SCT_EV8_STATE_STATEMSK2_Pos 2 /*!< SCT EV8_STATE: STATEMSK2 Position */ +#define SCT_EV8_STATE_STATEMSK2_Msk (0x01UL << SCT_EV8_STATE_STATEMSK2_Pos) /*!< SCT EV8_STATE: STATEMSK2 Mask */ +#define SCT_EV8_STATE_STATEMSK3_Pos 3 /*!< SCT EV8_STATE: STATEMSK3 Position */ +#define SCT_EV8_STATE_STATEMSK3_Msk (0x01UL << SCT_EV8_STATE_STATEMSK3_Pos) /*!< SCT EV8_STATE: STATEMSK3 Mask */ +#define SCT_EV8_STATE_STATEMSK4_Pos 4 /*!< SCT EV8_STATE: STATEMSK4 Position */ +#define SCT_EV8_STATE_STATEMSK4_Msk (0x01UL << SCT_EV8_STATE_STATEMSK4_Pos) /*!< SCT EV8_STATE: STATEMSK4 Mask */ +#define SCT_EV8_STATE_STATEMSK5_Pos 5 /*!< SCT EV8_STATE: STATEMSK5 Position */ +#define SCT_EV8_STATE_STATEMSK5_Msk (0x01UL << SCT_EV8_STATE_STATEMSK5_Pos) /*!< SCT EV8_STATE: STATEMSK5 Mask */ +#define SCT_EV8_STATE_STATEMSK6_Pos 6 /*!< SCT EV8_STATE: STATEMSK6 Position */ +#define SCT_EV8_STATE_STATEMSK6_Msk (0x01UL << SCT_EV8_STATE_STATEMSK6_Pos) /*!< SCT EV8_STATE: STATEMSK6 Mask */ +#define SCT_EV8_STATE_STATEMSK7_Pos 7 /*!< SCT EV8_STATE: STATEMSK7 Position */ +#define SCT_EV8_STATE_STATEMSK7_Msk (0x01UL << SCT_EV8_STATE_STATEMSK7_Pos) /*!< SCT EV8_STATE: STATEMSK7 Mask */ +#define SCT_EV8_STATE_STATEMSK8_Pos 8 /*!< SCT EV8_STATE: STATEMSK8 Position */ +#define SCT_EV8_STATE_STATEMSK8_Msk (0x01UL << SCT_EV8_STATE_STATEMSK8_Pos) /*!< SCT EV8_STATE: STATEMSK8 Mask */ +#define SCT_EV8_STATE_STATEMSK9_Pos 9 /*!< SCT EV8_STATE: STATEMSK9 Position */ +#define SCT_EV8_STATE_STATEMSK9_Msk (0x01UL << SCT_EV8_STATE_STATEMSK9_Pos) /*!< SCT EV8_STATE: STATEMSK9 Mask */ +#define SCT_EV8_STATE_STATEMSK10_Pos 10 /*!< SCT EV8_STATE: STATEMSK10 Position */ +#define SCT_EV8_STATE_STATEMSK10_Msk (0x01UL << SCT_EV8_STATE_STATEMSK10_Pos) /*!< SCT EV8_STATE: STATEMSK10 Mask */ +#define SCT_EV8_STATE_STATEMSK11_Pos 11 /*!< SCT EV8_STATE: STATEMSK11 Position */ +#define SCT_EV8_STATE_STATEMSK11_Msk (0x01UL << SCT_EV8_STATE_STATEMSK11_Pos) /*!< SCT EV8_STATE: STATEMSK11 Mask */ +#define SCT_EV8_STATE_STATEMSK12_Pos 12 /*!< SCT EV8_STATE: STATEMSK12 Position */ +#define SCT_EV8_STATE_STATEMSK12_Msk (0x01UL << SCT_EV8_STATE_STATEMSK12_Pos) /*!< SCT EV8_STATE: STATEMSK12 Mask */ +#define SCT_EV8_STATE_STATEMSK13_Pos 13 /*!< SCT EV8_STATE: STATEMSK13 Position */ +#define SCT_EV8_STATE_STATEMSK13_Msk (0x01UL << SCT_EV8_STATE_STATEMSK13_Pos) /*!< SCT EV8_STATE: STATEMSK13 Mask */ +#define SCT_EV8_STATE_STATEMSK14_Pos 14 /*!< SCT EV8_STATE: STATEMSK14 Position */ +#define SCT_EV8_STATE_STATEMSK14_Msk (0x01UL << SCT_EV8_STATE_STATEMSK14_Pos) /*!< SCT EV8_STATE: STATEMSK14 Mask */ +#define SCT_EV8_STATE_STATEMSK15_Pos 15 /*!< SCT EV8_STATE: STATEMSK15 Position */ +#define SCT_EV8_STATE_STATEMSK15_Msk (0x01UL << SCT_EV8_STATE_STATEMSK15_Pos) /*!< SCT EV8_STATE: STATEMSK15 Mask */ +#define SCT_EV8_STATE_STATEMSK16_Pos 16 /*!< SCT EV8_STATE: STATEMSK16 Position */ +#define SCT_EV8_STATE_STATEMSK16_Msk (0x01UL << SCT_EV8_STATE_STATEMSK16_Pos) /*!< SCT EV8_STATE: STATEMSK16 Mask */ +#define SCT_EV8_STATE_STATEMSK17_Pos 17 /*!< SCT EV8_STATE: STATEMSK17 Position */ +#define SCT_EV8_STATE_STATEMSK17_Msk (0x01UL << SCT_EV8_STATE_STATEMSK17_Pos) /*!< SCT EV8_STATE: STATEMSK17 Mask */ +#define SCT_EV8_STATE_STATEMSK18_Pos 18 /*!< SCT EV8_STATE: STATEMSK18 Position */ +#define SCT_EV8_STATE_STATEMSK18_Msk (0x01UL << SCT_EV8_STATE_STATEMSK18_Pos) /*!< SCT EV8_STATE: STATEMSK18 Mask */ +#define SCT_EV8_STATE_STATEMSK19_Pos 19 /*!< SCT EV8_STATE: STATEMSK19 Position */ +#define SCT_EV8_STATE_STATEMSK19_Msk (0x01UL << SCT_EV8_STATE_STATEMSK19_Pos) /*!< SCT EV8_STATE: STATEMSK19 Mask */ +#define SCT_EV8_STATE_STATEMSK20_Pos 20 /*!< SCT EV8_STATE: STATEMSK20 Position */ +#define SCT_EV8_STATE_STATEMSK20_Msk (0x01UL << SCT_EV8_STATE_STATEMSK20_Pos) /*!< SCT EV8_STATE: STATEMSK20 Mask */ +#define SCT_EV8_STATE_STATEMSK21_Pos 21 /*!< SCT EV8_STATE: STATEMSK21 Position */ +#define SCT_EV8_STATE_STATEMSK21_Msk (0x01UL << SCT_EV8_STATE_STATEMSK21_Pos) /*!< SCT EV8_STATE: STATEMSK21 Mask */ +#define SCT_EV8_STATE_STATEMSK22_Pos 22 /*!< SCT EV8_STATE: STATEMSK22 Position */ +#define SCT_EV8_STATE_STATEMSK22_Msk (0x01UL << SCT_EV8_STATE_STATEMSK22_Pos) /*!< SCT EV8_STATE: STATEMSK22 Mask */ +#define SCT_EV8_STATE_STATEMSK23_Pos 23 /*!< SCT EV8_STATE: STATEMSK23 Position */ +#define SCT_EV8_STATE_STATEMSK23_Msk (0x01UL << SCT_EV8_STATE_STATEMSK23_Pos) /*!< SCT EV8_STATE: STATEMSK23 Mask */ +#define SCT_EV8_STATE_STATEMSK24_Pos 24 /*!< SCT EV8_STATE: STATEMSK24 Position */ +#define SCT_EV8_STATE_STATEMSK24_Msk (0x01UL << SCT_EV8_STATE_STATEMSK24_Pos) /*!< SCT EV8_STATE: STATEMSK24 Mask */ +#define SCT_EV8_STATE_STATEMSK25_Pos 25 /*!< SCT EV8_STATE: STATEMSK25 Position */ +#define SCT_EV8_STATE_STATEMSK25_Msk (0x01UL << SCT_EV8_STATE_STATEMSK25_Pos) /*!< SCT EV8_STATE: STATEMSK25 Mask */ +#define SCT_EV8_STATE_STATEMSK26_Pos 26 /*!< SCT EV8_STATE: STATEMSK26 Position */ +#define SCT_EV8_STATE_STATEMSK26_Msk (0x01UL << SCT_EV8_STATE_STATEMSK26_Pos) /*!< SCT EV8_STATE: STATEMSK26 Mask */ +#define SCT_EV8_STATE_STATEMSK27_Pos 27 /*!< SCT EV8_STATE: STATEMSK27 Position */ +#define SCT_EV8_STATE_STATEMSK27_Msk (0x01UL << SCT_EV8_STATE_STATEMSK27_Pos) /*!< SCT EV8_STATE: STATEMSK27 Mask */ +#define SCT_EV8_STATE_STATEMSK28_Pos 28 /*!< SCT EV8_STATE: STATEMSK28 Position */ +#define SCT_EV8_STATE_STATEMSK28_Msk (0x01UL << SCT_EV8_STATE_STATEMSK28_Pos) /*!< SCT EV8_STATE: STATEMSK28 Mask */ +#define SCT_EV8_STATE_STATEMSK29_Pos 29 /*!< SCT EV8_STATE: STATEMSK29 Position */ +#define SCT_EV8_STATE_STATEMSK29_Msk (0x01UL << SCT_EV8_STATE_STATEMSK29_Pos) /*!< SCT EV8_STATE: STATEMSK29 Mask */ +#define SCT_EV8_STATE_STATEMSK30_Pos 30 /*!< SCT EV8_STATE: STATEMSK30 Position */ +#define SCT_EV8_STATE_STATEMSK30_Msk (0x01UL << SCT_EV8_STATE_STATEMSK30_Pos) /*!< SCT EV8_STATE: STATEMSK30 Mask */ +#define SCT_EV8_STATE_STATEMSK31_Pos 31 /*!< SCT EV8_STATE: STATEMSK31 Position */ +#define SCT_EV8_STATE_STATEMSK31_Msk (0x01UL << SCT_EV8_STATE_STATEMSK31_Pos) /*!< SCT EV8_STATE: STATEMSK31 Mask */ + +/* -------------------------------- SCT_EV8_CTRL -------------------------------- */ +#define SCT_EV8_CTRL_MATCHSEL_Pos 0 /*!< SCT EV8_CTRL: MATCHSEL Position */ +#define SCT_EV8_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV8_CTRL_MATCHSEL_Pos) /*!< SCT EV8_CTRL: MATCHSEL Mask */ +#define SCT_EV8_CTRL_HEVENT_Pos 4 /*!< SCT EV8_CTRL: HEVENT Position */ +#define SCT_EV8_CTRL_HEVENT_Msk (0x01UL << SCT_EV8_CTRL_HEVENT_Pos) /*!< SCT EV8_CTRL: HEVENT Mask */ +#define SCT_EV8_CTRL_OUTSEL_Pos 5 /*!< SCT EV8_CTRL: OUTSEL Position */ +#define SCT_EV8_CTRL_OUTSEL_Msk (0x01UL << SCT_EV8_CTRL_OUTSEL_Pos) /*!< SCT EV8_CTRL: OUTSEL Mask */ +#define SCT_EV8_CTRL_IOSEL_Pos 6 /*!< SCT EV8_CTRL: IOSEL Position */ +#define SCT_EV8_CTRL_IOSEL_Msk (0x0fUL << SCT_EV8_CTRL_IOSEL_Pos) /*!< SCT EV8_CTRL: IOSEL Mask */ +#define SCT_EV8_CTRL_IOCOND_Pos 10 /*!< SCT EV8_CTRL: IOCOND Position */ +#define SCT_EV8_CTRL_IOCOND_Msk (0x03UL << SCT_EV8_CTRL_IOCOND_Pos) /*!< SCT EV8_CTRL: IOCOND Mask */ +#define SCT_EV8_CTRL_COMBMODE_Pos 12 /*!< SCT EV8_CTRL: COMBMODE Position */ +#define SCT_EV8_CTRL_COMBMODE_Msk (0x03UL << SCT_EV8_CTRL_COMBMODE_Pos) /*!< SCT EV8_CTRL: COMBMODE Mask */ +#define SCT_EV8_CTRL_STATELD_Pos 14 /*!< SCT EV8_CTRL: STATELD Position */ +#define SCT_EV8_CTRL_STATELD_Msk (0x01UL << SCT_EV8_CTRL_STATELD_Pos) /*!< SCT EV8_CTRL: STATELD Mask */ +#define SCT_EV8_CTRL_STATEV_Pos 15 /*!< SCT EV8_CTRL: STATEV Position */ +#define SCT_EV8_CTRL_STATEV_Msk (0x1fUL << SCT_EV8_CTRL_STATEV_Pos) /*!< SCT EV8_CTRL: STATEV Mask */ +#define SCT_EV8_CTRL_MATCHMEM_Pos 20 /*!< SCT EV8_CTRL: MATCHMEM Position */ +#define SCT_EV8_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV8_CTRL_MATCHMEM_Pos) /*!< SCT EV8_CTRL: MATCHMEM Mask */ +#define SCT_EV8_CTRL_DIRECTION_Pos 21 /*!< SCT EV8_CTRL: DIRECTION Position */ +#define SCT_EV8_CTRL_DIRECTION_Msk (0x03UL << SCT_EV8_CTRL_DIRECTION_Pos) /*!< SCT EV8_CTRL: DIRECTION Mask */ + +/* -------------------------------- SCT_EV9_STATE ------------------------------- */ +#define SCT_EV9_STATE_STATEMSK0_Pos 0 /*!< SCT EV9_STATE: STATEMSK0 Position */ +#define SCT_EV9_STATE_STATEMSK0_Msk (0x01UL << SCT_EV9_STATE_STATEMSK0_Pos) /*!< SCT EV9_STATE: STATEMSK0 Mask */ +#define SCT_EV9_STATE_STATEMSK1_Pos 1 /*!< SCT EV9_STATE: STATEMSK1 Position */ +#define SCT_EV9_STATE_STATEMSK1_Msk (0x01UL << SCT_EV9_STATE_STATEMSK1_Pos) /*!< SCT EV9_STATE: STATEMSK1 Mask */ +#define SCT_EV9_STATE_STATEMSK2_Pos 2 /*!< SCT EV9_STATE: STATEMSK2 Position */ +#define SCT_EV9_STATE_STATEMSK2_Msk (0x01UL << SCT_EV9_STATE_STATEMSK2_Pos) /*!< SCT EV9_STATE: STATEMSK2 Mask */ +#define SCT_EV9_STATE_STATEMSK3_Pos 3 /*!< SCT EV9_STATE: STATEMSK3 Position */ +#define SCT_EV9_STATE_STATEMSK3_Msk (0x01UL << SCT_EV9_STATE_STATEMSK3_Pos) /*!< SCT EV9_STATE: STATEMSK3 Mask */ +#define SCT_EV9_STATE_STATEMSK4_Pos 4 /*!< SCT EV9_STATE: STATEMSK4 Position */ +#define SCT_EV9_STATE_STATEMSK4_Msk (0x01UL << SCT_EV9_STATE_STATEMSK4_Pos) /*!< SCT EV9_STATE: STATEMSK4 Mask */ +#define SCT_EV9_STATE_STATEMSK5_Pos 5 /*!< SCT EV9_STATE: STATEMSK5 Position */ +#define SCT_EV9_STATE_STATEMSK5_Msk (0x01UL << SCT_EV9_STATE_STATEMSK5_Pos) /*!< SCT EV9_STATE: STATEMSK5 Mask */ +#define SCT_EV9_STATE_STATEMSK6_Pos 6 /*!< SCT EV9_STATE: STATEMSK6 Position */ +#define SCT_EV9_STATE_STATEMSK6_Msk (0x01UL << SCT_EV9_STATE_STATEMSK6_Pos) /*!< SCT EV9_STATE: STATEMSK6 Mask */ +#define SCT_EV9_STATE_STATEMSK7_Pos 7 /*!< SCT EV9_STATE: STATEMSK7 Position */ +#define SCT_EV9_STATE_STATEMSK7_Msk (0x01UL << SCT_EV9_STATE_STATEMSK7_Pos) /*!< SCT EV9_STATE: STATEMSK7 Mask */ +#define SCT_EV9_STATE_STATEMSK8_Pos 8 /*!< SCT EV9_STATE: STATEMSK8 Position */ +#define SCT_EV9_STATE_STATEMSK8_Msk (0x01UL << SCT_EV9_STATE_STATEMSK8_Pos) /*!< SCT EV9_STATE: STATEMSK8 Mask */ +#define SCT_EV9_STATE_STATEMSK9_Pos 9 /*!< SCT EV9_STATE: STATEMSK9 Position */ +#define SCT_EV9_STATE_STATEMSK9_Msk (0x01UL << SCT_EV9_STATE_STATEMSK9_Pos) /*!< SCT EV9_STATE: STATEMSK9 Mask */ +#define SCT_EV9_STATE_STATEMSK10_Pos 10 /*!< SCT EV9_STATE: STATEMSK10 Position */ +#define SCT_EV9_STATE_STATEMSK10_Msk (0x01UL << SCT_EV9_STATE_STATEMSK10_Pos) /*!< SCT EV9_STATE: STATEMSK10 Mask */ +#define SCT_EV9_STATE_STATEMSK11_Pos 11 /*!< SCT EV9_STATE: STATEMSK11 Position */ +#define SCT_EV9_STATE_STATEMSK11_Msk (0x01UL << SCT_EV9_STATE_STATEMSK11_Pos) /*!< SCT EV9_STATE: STATEMSK11 Mask */ +#define SCT_EV9_STATE_STATEMSK12_Pos 12 /*!< SCT EV9_STATE: STATEMSK12 Position */ +#define SCT_EV9_STATE_STATEMSK12_Msk (0x01UL << SCT_EV9_STATE_STATEMSK12_Pos) /*!< SCT EV9_STATE: STATEMSK12 Mask */ +#define SCT_EV9_STATE_STATEMSK13_Pos 13 /*!< SCT EV9_STATE: STATEMSK13 Position */ +#define SCT_EV9_STATE_STATEMSK13_Msk (0x01UL << SCT_EV9_STATE_STATEMSK13_Pos) /*!< SCT EV9_STATE: STATEMSK13 Mask */ +#define SCT_EV9_STATE_STATEMSK14_Pos 14 /*!< SCT EV9_STATE: STATEMSK14 Position */ +#define SCT_EV9_STATE_STATEMSK14_Msk (0x01UL << SCT_EV9_STATE_STATEMSK14_Pos) /*!< SCT EV9_STATE: STATEMSK14 Mask */ +#define SCT_EV9_STATE_STATEMSK15_Pos 15 /*!< SCT EV9_STATE: STATEMSK15 Position */ +#define SCT_EV9_STATE_STATEMSK15_Msk (0x01UL << SCT_EV9_STATE_STATEMSK15_Pos) /*!< SCT EV9_STATE: STATEMSK15 Mask */ +#define SCT_EV9_STATE_STATEMSK16_Pos 16 /*!< SCT EV9_STATE: STATEMSK16 Position */ +#define SCT_EV9_STATE_STATEMSK16_Msk (0x01UL << SCT_EV9_STATE_STATEMSK16_Pos) /*!< SCT EV9_STATE: STATEMSK16 Mask */ +#define SCT_EV9_STATE_STATEMSK17_Pos 17 /*!< SCT EV9_STATE: STATEMSK17 Position */ +#define SCT_EV9_STATE_STATEMSK17_Msk (0x01UL << SCT_EV9_STATE_STATEMSK17_Pos) /*!< SCT EV9_STATE: STATEMSK17 Mask */ +#define SCT_EV9_STATE_STATEMSK18_Pos 18 /*!< SCT EV9_STATE: STATEMSK18 Position */ +#define SCT_EV9_STATE_STATEMSK18_Msk (0x01UL << SCT_EV9_STATE_STATEMSK18_Pos) /*!< SCT EV9_STATE: STATEMSK18 Mask */ +#define SCT_EV9_STATE_STATEMSK19_Pos 19 /*!< SCT EV9_STATE: STATEMSK19 Position */ +#define SCT_EV9_STATE_STATEMSK19_Msk (0x01UL << SCT_EV9_STATE_STATEMSK19_Pos) /*!< SCT EV9_STATE: STATEMSK19 Mask */ +#define SCT_EV9_STATE_STATEMSK20_Pos 20 /*!< SCT EV9_STATE: STATEMSK20 Position */ +#define SCT_EV9_STATE_STATEMSK20_Msk (0x01UL << SCT_EV9_STATE_STATEMSK20_Pos) /*!< SCT EV9_STATE: STATEMSK20 Mask */ +#define SCT_EV9_STATE_STATEMSK21_Pos 21 /*!< SCT EV9_STATE: STATEMSK21 Position */ +#define SCT_EV9_STATE_STATEMSK21_Msk (0x01UL << SCT_EV9_STATE_STATEMSK21_Pos) /*!< SCT EV9_STATE: STATEMSK21 Mask */ +#define SCT_EV9_STATE_STATEMSK22_Pos 22 /*!< SCT EV9_STATE: STATEMSK22 Position */ +#define SCT_EV9_STATE_STATEMSK22_Msk (0x01UL << SCT_EV9_STATE_STATEMSK22_Pos) /*!< SCT EV9_STATE: STATEMSK22 Mask */ +#define SCT_EV9_STATE_STATEMSK23_Pos 23 /*!< SCT EV9_STATE: STATEMSK23 Position */ +#define SCT_EV9_STATE_STATEMSK23_Msk (0x01UL << SCT_EV9_STATE_STATEMSK23_Pos) /*!< SCT EV9_STATE: STATEMSK23 Mask */ +#define SCT_EV9_STATE_STATEMSK24_Pos 24 /*!< SCT EV9_STATE: STATEMSK24 Position */ +#define SCT_EV9_STATE_STATEMSK24_Msk (0x01UL << SCT_EV9_STATE_STATEMSK24_Pos) /*!< SCT EV9_STATE: STATEMSK24 Mask */ +#define SCT_EV9_STATE_STATEMSK25_Pos 25 /*!< SCT EV9_STATE: STATEMSK25 Position */ +#define SCT_EV9_STATE_STATEMSK25_Msk (0x01UL << SCT_EV9_STATE_STATEMSK25_Pos) /*!< SCT EV9_STATE: STATEMSK25 Mask */ +#define SCT_EV9_STATE_STATEMSK26_Pos 26 /*!< SCT EV9_STATE: STATEMSK26 Position */ +#define SCT_EV9_STATE_STATEMSK26_Msk (0x01UL << SCT_EV9_STATE_STATEMSK26_Pos) /*!< SCT EV9_STATE: STATEMSK26 Mask */ +#define SCT_EV9_STATE_STATEMSK27_Pos 27 /*!< SCT EV9_STATE: STATEMSK27 Position */ +#define SCT_EV9_STATE_STATEMSK27_Msk (0x01UL << SCT_EV9_STATE_STATEMSK27_Pos) /*!< SCT EV9_STATE: STATEMSK27 Mask */ +#define SCT_EV9_STATE_STATEMSK28_Pos 28 /*!< SCT EV9_STATE: STATEMSK28 Position */ +#define SCT_EV9_STATE_STATEMSK28_Msk (0x01UL << SCT_EV9_STATE_STATEMSK28_Pos) /*!< SCT EV9_STATE: STATEMSK28 Mask */ +#define SCT_EV9_STATE_STATEMSK29_Pos 29 /*!< SCT EV9_STATE: STATEMSK29 Position */ +#define SCT_EV9_STATE_STATEMSK29_Msk (0x01UL << SCT_EV9_STATE_STATEMSK29_Pos) /*!< SCT EV9_STATE: STATEMSK29 Mask */ +#define SCT_EV9_STATE_STATEMSK30_Pos 30 /*!< SCT EV9_STATE: STATEMSK30 Position */ +#define SCT_EV9_STATE_STATEMSK30_Msk (0x01UL << SCT_EV9_STATE_STATEMSK30_Pos) /*!< SCT EV9_STATE: STATEMSK30 Mask */ +#define SCT_EV9_STATE_STATEMSK31_Pos 31 /*!< SCT EV9_STATE: STATEMSK31 Position */ +#define SCT_EV9_STATE_STATEMSK31_Msk (0x01UL << SCT_EV9_STATE_STATEMSK31_Pos) /*!< SCT EV9_STATE: STATEMSK31 Mask */ + +/* -------------------------------- SCT_EV9_CTRL -------------------------------- */ +#define SCT_EV9_CTRL_MATCHSEL_Pos 0 /*!< SCT EV9_CTRL: MATCHSEL Position */ +#define SCT_EV9_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV9_CTRL_MATCHSEL_Pos) /*!< SCT EV9_CTRL: MATCHSEL Mask */ +#define SCT_EV9_CTRL_HEVENT_Pos 4 /*!< SCT EV9_CTRL: HEVENT Position */ +#define SCT_EV9_CTRL_HEVENT_Msk (0x01UL << SCT_EV9_CTRL_HEVENT_Pos) /*!< SCT EV9_CTRL: HEVENT Mask */ +#define SCT_EV9_CTRL_OUTSEL_Pos 5 /*!< SCT EV9_CTRL: OUTSEL Position */ +#define SCT_EV9_CTRL_OUTSEL_Msk (0x01UL << SCT_EV9_CTRL_OUTSEL_Pos) /*!< SCT EV9_CTRL: OUTSEL Mask */ +#define SCT_EV9_CTRL_IOSEL_Pos 6 /*!< SCT EV9_CTRL: IOSEL Position */ +#define SCT_EV9_CTRL_IOSEL_Msk (0x0fUL << SCT_EV9_CTRL_IOSEL_Pos) /*!< SCT EV9_CTRL: IOSEL Mask */ +#define SCT_EV9_CTRL_IOCOND_Pos 10 /*!< SCT EV9_CTRL: IOCOND Position */ +#define SCT_EV9_CTRL_IOCOND_Msk (0x03UL << SCT_EV9_CTRL_IOCOND_Pos) /*!< SCT EV9_CTRL: IOCOND Mask */ +#define SCT_EV9_CTRL_COMBMODE_Pos 12 /*!< SCT EV9_CTRL: COMBMODE Position */ +#define SCT_EV9_CTRL_COMBMODE_Msk (0x03UL << SCT_EV9_CTRL_COMBMODE_Pos) /*!< SCT EV9_CTRL: COMBMODE Mask */ +#define SCT_EV9_CTRL_STATELD_Pos 14 /*!< SCT EV9_CTRL: STATELD Position */ +#define SCT_EV9_CTRL_STATELD_Msk (0x01UL << SCT_EV9_CTRL_STATELD_Pos) /*!< SCT EV9_CTRL: STATELD Mask */ +#define SCT_EV9_CTRL_STATEV_Pos 15 /*!< SCT EV9_CTRL: STATEV Position */ +#define SCT_EV9_CTRL_STATEV_Msk (0x1fUL << SCT_EV9_CTRL_STATEV_Pos) /*!< SCT EV9_CTRL: STATEV Mask */ +#define SCT_EV9_CTRL_MATCHMEM_Pos 20 /*!< SCT EV9_CTRL: MATCHMEM Position */ +#define SCT_EV9_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV9_CTRL_MATCHMEM_Pos) /*!< SCT EV9_CTRL: MATCHMEM Mask */ +#define SCT_EV9_CTRL_DIRECTION_Pos 21 /*!< SCT EV9_CTRL: DIRECTION Position */ +#define SCT_EV9_CTRL_DIRECTION_Msk (0x03UL << SCT_EV9_CTRL_DIRECTION_Pos) /*!< SCT EV9_CTRL: DIRECTION Mask */ + +/* ------------------------------- SCT_EV10_STATE ------------------------------- */ +#define SCT_EV10_STATE_STATEMSK0_Pos 0 /*!< SCT EV10_STATE: STATEMSK0 Position */ +#define SCT_EV10_STATE_STATEMSK0_Msk (0x01UL << SCT_EV10_STATE_STATEMSK0_Pos) /*!< SCT EV10_STATE: STATEMSK0 Mask */ +#define SCT_EV10_STATE_STATEMSK1_Pos 1 /*!< SCT EV10_STATE: STATEMSK1 Position */ +#define SCT_EV10_STATE_STATEMSK1_Msk (0x01UL << SCT_EV10_STATE_STATEMSK1_Pos) /*!< SCT EV10_STATE: STATEMSK1 Mask */ +#define SCT_EV10_STATE_STATEMSK2_Pos 2 /*!< SCT EV10_STATE: STATEMSK2 Position */ +#define SCT_EV10_STATE_STATEMSK2_Msk (0x01UL << SCT_EV10_STATE_STATEMSK2_Pos) /*!< SCT EV10_STATE: STATEMSK2 Mask */ +#define SCT_EV10_STATE_STATEMSK3_Pos 3 /*!< SCT EV10_STATE: STATEMSK3 Position */ +#define SCT_EV10_STATE_STATEMSK3_Msk (0x01UL << SCT_EV10_STATE_STATEMSK3_Pos) /*!< SCT EV10_STATE: STATEMSK3 Mask */ +#define SCT_EV10_STATE_STATEMSK4_Pos 4 /*!< SCT EV10_STATE: STATEMSK4 Position */ +#define SCT_EV10_STATE_STATEMSK4_Msk (0x01UL << SCT_EV10_STATE_STATEMSK4_Pos) /*!< SCT EV10_STATE: STATEMSK4 Mask */ +#define SCT_EV10_STATE_STATEMSK5_Pos 5 /*!< SCT EV10_STATE: STATEMSK5 Position */ +#define SCT_EV10_STATE_STATEMSK5_Msk (0x01UL << SCT_EV10_STATE_STATEMSK5_Pos) /*!< SCT EV10_STATE: STATEMSK5 Mask */ +#define SCT_EV10_STATE_STATEMSK6_Pos 6 /*!< SCT EV10_STATE: STATEMSK6 Position */ +#define SCT_EV10_STATE_STATEMSK6_Msk (0x01UL << SCT_EV10_STATE_STATEMSK6_Pos) /*!< SCT EV10_STATE: STATEMSK6 Mask */ +#define SCT_EV10_STATE_STATEMSK7_Pos 7 /*!< SCT EV10_STATE: STATEMSK7 Position */ +#define SCT_EV10_STATE_STATEMSK7_Msk (0x01UL << SCT_EV10_STATE_STATEMSK7_Pos) /*!< SCT EV10_STATE: STATEMSK7 Mask */ +#define SCT_EV10_STATE_STATEMSK8_Pos 8 /*!< SCT EV10_STATE: STATEMSK8 Position */ +#define SCT_EV10_STATE_STATEMSK8_Msk (0x01UL << SCT_EV10_STATE_STATEMSK8_Pos) /*!< SCT EV10_STATE: STATEMSK8 Mask */ +#define SCT_EV10_STATE_STATEMSK9_Pos 9 /*!< SCT EV10_STATE: STATEMSK9 Position */ +#define SCT_EV10_STATE_STATEMSK9_Msk (0x01UL << SCT_EV10_STATE_STATEMSK9_Pos) /*!< SCT EV10_STATE: STATEMSK9 Mask */ +#define SCT_EV10_STATE_STATEMSK10_Pos 10 /*!< SCT EV10_STATE: STATEMSK10 Position */ +#define SCT_EV10_STATE_STATEMSK10_Msk (0x01UL << SCT_EV10_STATE_STATEMSK10_Pos) /*!< SCT EV10_STATE: STATEMSK10 Mask */ +#define SCT_EV10_STATE_STATEMSK11_Pos 11 /*!< SCT EV10_STATE: STATEMSK11 Position */ +#define SCT_EV10_STATE_STATEMSK11_Msk (0x01UL << SCT_EV10_STATE_STATEMSK11_Pos) /*!< SCT EV10_STATE: STATEMSK11 Mask */ +#define SCT_EV10_STATE_STATEMSK12_Pos 12 /*!< SCT EV10_STATE: STATEMSK12 Position */ +#define SCT_EV10_STATE_STATEMSK12_Msk (0x01UL << SCT_EV10_STATE_STATEMSK12_Pos) /*!< SCT EV10_STATE: STATEMSK12 Mask */ +#define SCT_EV10_STATE_STATEMSK13_Pos 13 /*!< SCT EV10_STATE: STATEMSK13 Position */ +#define SCT_EV10_STATE_STATEMSK13_Msk (0x01UL << SCT_EV10_STATE_STATEMSK13_Pos) /*!< SCT EV10_STATE: STATEMSK13 Mask */ +#define SCT_EV10_STATE_STATEMSK14_Pos 14 /*!< SCT EV10_STATE: STATEMSK14 Position */ +#define SCT_EV10_STATE_STATEMSK14_Msk (0x01UL << SCT_EV10_STATE_STATEMSK14_Pos) /*!< SCT EV10_STATE: STATEMSK14 Mask */ +#define SCT_EV10_STATE_STATEMSK15_Pos 15 /*!< SCT EV10_STATE: STATEMSK15 Position */ +#define SCT_EV10_STATE_STATEMSK15_Msk (0x01UL << SCT_EV10_STATE_STATEMSK15_Pos) /*!< SCT EV10_STATE: STATEMSK15 Mask */ +#define SCT_EV10_STATE_STATEMSK16_Pos 16 /*!< SCT EV10_STATE: STATEMSK16 Position */ +#define SCT_EV10_STATE_STATEMSK16_Msk (0x01UL << SCT_EV10_STATE_STATEMSK16_Pos) /*!< SCT EV10_STATE: STATEMSK16 Mask */ +#define SCT_EV10_STATE_STATEMSK17_Pos 17 /*!< SCT EV10_STATE: STATEMSK17 Position */ +#define SCT_EV10_STATE_STATEMSK17_Msk (0x01UL << SCT_EV10_STATE_STATEMSK17_Pos) /*!< SCT EV10_STATE: STATEMSK17 Mask */ +#define SCT_EV10_STATE_STATEMSK18_Pos 18 /*!< SCT EV10_STATE: STATEMSK18 Position */ +#define SCT_EV10_STATE_STATEMSK18_Msk (0x01UL << SCT_EV10_STATE_STATEMSK18_Pos) /*!< SCT EV10_STATE: STATEMSK18 Mask */ +#define SCT_EV10_STATE_STATEMSK19_Pos 19 /*!< SCT EV10_STATE: STATEMSK19 Position */ +#define SCT_EV10_STATE_STATEMSK19_Msk (0x01UL << SCT_EV10_STATE_STATEMSK19_Pos) /*!< SCT EV10_STATE: STATEMSK19 Mask */ +#define SCT_EV10_STATE_STATEMSK20_Pos 20 /*!< SCT EV10_STATE: STATEMSK20 Position */ +#define SCT_EV10_STATE_STATEMSK20_Msk (0x01UL << SCT_EV10_STATE_STATEMSK20_Pos) /*!< SCT EV10_STATE: STATEMSK20 Mask */ +#define SCT_EV10_STATE_STATEMSK21_Pos 21 /*!< SCT EV10_STATE: STATEMSK21 Position */ +#define SCT_EV10_STATE_STATEMSK21_Msk (0x01UL << SCT_EV10_STATE_STATEMSK21_Pos) /*!< SCT EV10_STATE: STATEMSK21 Mask */ +#define SCT_EV10_STATE_STATEMSK22_Pos 22 /*!< SCT EV10_STATE: STATEMSK22 Position */ +#define SCT_EV10_STATE_STATEMSK22_Msk (0x01UL << SCT_EV10_STATE_STATEMSK22_Pos) /*!< SCT EV10_STATE: STATEMSK22 Mask */ +#define SCT_EV10_STATE_STATEMSK23_Pos 23 /*!< SCT EV10_STATE: STATEMSK23 Position */ +#define SCT_EV10_STATE_STATEMSK23_Msk (0x01UL << SCT_EV10_STATE_STATEMSK23_Pos) /*!< SCT EV10_STATE: STATEMSK23 Mask */ +#define SCT_EV10_STATE_STATEMSK24_Pos 24 /*!< SCT EV10_STATE: STATEMSK24 Position */ +#define SCT_EV10_STATE_STATEMSK24_Msk (0x01UL << SCT_EV10_STATE_STATEMSK24_Pos) /*!< SCT EV10_STATE: STATEMSK24 Mask */ +#define SCT_EV10_STATE_STATEMSK25_Pos 25 /*!< SCT EV10_STATE: STATEMSK25 Position */ +#define SCT_EV10_STATE_STATEMSK25_Msk (0x01UL << SCT_EV10_STATE_STATEMSK25_Pos) /*!< SCT EV10_STATE: STATEMSK25 Mask */ +#define SCT_EV10_STATE_STATEMSK26_Pos 26 /*!< SCT EV10_STATE: STATEMSK26 Position */ +#define SCT_EV10_STATE_STATEMSK26_Msk (0x01UL << SCT_EV10_STATE_STATEMSK26_Pos) /*!< SCT EV10_STATE: STATEMSK26 Mask */ +#define SCT_EV10_STATE_STATEMSK27_Pos 27 /*!< SCT EV10_STATE: STATEMSK27 Position */ +#define SCT_EV10_STATE_STATEMSK27_Msk (0x01UL << SCT_EV10_STATE_STATEMSK27_Pos) /*!< SCT EV10_STATE: STATEMSK27 Mask */ +#define SCT_EV10_STATE_STATEMSK28_Pos 28 /*!< SCT EV10_STATE: STATEMSK28 Position */ +#define SCT_EV10_STATE_STATEMSK28_Msk (0x01UL << SCT_EV10_STATE_STATEMSK28_Pos) /*!< SCT EV10_STATE: STATEMSK28 Mask */ +#define SCT_EV10_STATE_STATEMSK29_Pos 29 /*!< SCT EV10_STATE: STATEMSK29 Position */ +#define SCT_EV10_STATE_STATEMSK29_Msk (0x01UL << SCT_EV10_STATE_STATEMSK29_Pos) /*!< SCT EV10_STATE: STATEMSK29 Mask */ +#define SCT_EV10_STATE_STATEMSK30_Pos 30 /*!< SCT EV10_STATE: STATEMSK30 Position */ +#define SCT_EV10_STATE_STATEMSK30_Msk (0x01UL << SCT_EV10_STATE_STATEMSK30_Pos) /*!< SCT EV10_STATE: STATEMSK30 Mask */ +#define SCT_EV10_STATE_STATEMSK31_Pos 31 /*!< SCT EV10_STATE: STATEMSK31 Position */ +#define SCT_EV10_STATE_STATEMSK31_Msk (0x01UL << SCT_EV10_STATE_STATEMSK31_Pos) /*!< SCT EV10_STATE: STATEMSK31 Mask */ + +/* -------------------------------- SCT_EV10_CTRL ------------------------------- */ +#define SCT_EV10_CTRL_MATCHSEL_Pos 0 /*!< SCT EV10_CTRL: MATCHSEL Position */ +#define SCT_EV10_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV10_CTRL_MATCHSEL_Pos) /*!< SCT EV10_CTRL: MATCHSEL Mask */ +#define SCT_EV10_CTRL_HEVENT_Pos 4 /*!< SCT EV10_CTRL: HEVENT Position */ +#define SCT_EV10_CTRL_HEVENT_Msk (0x01UL << SCT_EV10_CTRL_HEVENT_Pos) /*!< SCT EV10_CTRL: HEVENT Mask */ +#define SCT_EV10_CTRL_OUTSEL_Pos 5 /*!< SCT EV10_CTRL: OUTSEL Position */ +#define SCT_EV10_CTRL_OUTSEL_Msk (0x01UL << SCT_EV10_CTRL_OUTSEL_Pos) /*!< SCT EV10_CTRL: OUTSEL Mask */ +#define SCT_EV10_CTRL_IOSEL_Pos 6 /*!< SCT EV10_CTRL: IOSEL Position */ +#define SCT_EV10_CTRL_IOSEL_Msk (0x0fUL << SCT_EV10_CTRL_IOSEL_Pos) /*!< SCT EV10_CTRL: IOSEL Mask */ +#define SCT_EV10_CTRL_IOCOND_Pos 10 /*!< SCT EV10_CTRL: IOCOND Position */ +#define SCT_EV10_CTRL_IOCOND_Msk (0x03UL << SCT_EV10_CTRL_IOCOND_Pos) /*!< SCT EV10_CTRL: IOCOND Mask */ +#define SCT_EV10_CTRL_COMBMODE_Pos 12 /*!< SCT EV10_CTRL: COMBMODE Position */ +#define SCT_EV10_CTRL_COMBMODE_Msk (0x03UL << SCT_EV10_CTRL_COMBMODE_Pos) /*!< SCT EV10_CTRL: COMBMODE Mask */ +#define SCT_EV10_CTRL_STATELD_Pos 14 /*!< SCT EV10_CTRL: STATELD Position */ +#define SCT_EV10_CTRL_STATELD_Msk (0x01UL << SCT_EV10_CTRL_STATELD_Pos) /*!< SCT EV10_CTRL: STATELD Mask */ +#define SCT_EV10_CTRL_STATEV_Pos 15 /*!< SCT EV10_CTRL: STATEV Position */ +#define SCT_EV10_CTRL_STATEV_Msk (0x1fUL << SCT_EV10_CTRL_STATEV_Pos) /*!< SCT EV10_CTRL: STATEV Mask */ +#define SCT_EV10_CTRL_MATCHMEM_Pos 20 /*!< SCT EV10_CTRL: MATCHMEM Position */ +#define SCT_EV10_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV10_CTRL_MATCHMEM_Pos) /*!< SCT EV10_CTRL: MATCHMEM Mask */ +#define SCT_EV10_CTRL_DIRECTION_Pos 21 /*!< SCT EV10_CTRL: DIRECTION Position */ +#define SCT_EV10_CTRL_DIRECTION_Msk (0x03UL << SCT_EV10_CTRL_DIRECTION_Pos) /*!< SCT EV10_CTRL: DIRECTION Mask */ + +/* ------------------------------- SCT_EV11_STATE ------------------------------- */ +#define SCT_EV11_STATE_STATEMSK0_Pos 0 /*!< SCT EV11_STATE: STATEMSK0 Position */ +#define SCT_EV11_STATE_STATEMSK0_Msk (0x01UL << SCT_EV11_STATE_STATEMSK0_Pos) /*!< SCT EV11_STATE: STATEMSK0 Mask */ +#define SCT_EV11_STATE_STATEMSK1_Pos 1 /*!< SCT EV11_STATE: STATEMSK1 Position */ +#define SCT_EV11_STATE_STATEMSK1_Msk (0x01UL << SCT_EV11_STATE_STATEMSK1_Pos) /*!< SCT EV11_STATE: STATEMSK1 Mask */ +#define SCT_EV11_STATE_STATEMSK2_Pos 2 /*!< SCT EV11_STATE: STATEMSK2 Position */ +#define SCT_EV11_STATE_STATEMSK2_Msk (0x01UL << SCT_EV11_STATE_STATEMSK2_Pos) /*!< SCT EV11_STATE: STATEMSK2 Mask */ +#define SCT_EV11_STATE_STATEMSK3_Pos 3 /*!< SCT EV11_STATE: STATEMSK3 Position */ +#define SCT_EV11_STATE_STATEMSK3_Msk (0x01UL << SCT_EV11_STATE_STATEMSK3_Pos) /*!< SCT EV11_STATE: STATEMSK3 Mask */ +#define SCT_EV11_STATE_STATEMSK4_Pos 4 /*!< SCT EV11_STATE: STATEMSK4 Position */ +#define SCT_EV11_STATE_STATEMSK4_Msk (0x01UL << SCT_EV11_STATE_STATEMSK4_Pos) /*!< SCT EV11_STATE: STATEMSK4 Mask */ +#define SCT_EV11_STATE_STATEMSK5_Pos 5 /*!< SCT EV11_STATE: STATEMSK5 Position */ +#define SCT_EV11_STATE_STATEMSK5_Msk (0x01UL << SCT_EV11_STATE_STATEMSK5_Pos) /*!< SCT EV11_STATE: STATEMSK5 Mask */ +#define SCT_EV11_STATE_STATEMSK6_Pos 6 /*!< SCT EV11_STATE: STATEMSK6 Position */ +#define SCT_EV11_STATE_STATEMSK6_Msk (0x01UL << SCT_EV11_STATE_STATEMSK6_Pos) /*!< SCT EV11_STATE: STATEMSK6 Mask */ +#define SCT_EV11_STATE_STATEMSK7_Pos 7 /*!< SCT EV11_STATE: STATEMSK7 Position */ +#define SCT_EV11_STATE_STATEMSK7_Msk (0x01UL << SCT_EV11_STATE_STATEMSK7_Pos) /*!< SCT EV11_STATE: STATEMSK7 Mask */ +#define SCT_EV11_STATE_STATEMSK8_Pos 8 /*!< SCT EV11_STATE: STATEMSK8 Position */ +#define SCT_EV11_STATE_STATEMSK8_Msk (0x01UL << SCT_EV11_STATE_STATEMSK8_Pos) /*!< SCT EV11_STATE: STATEMSK8 Mask */ +#define SCT_EV11_STATE_STATEMSK9_Pos 9 /*!< SCT EV11_STATE: STATEMSK9 Position */ +#define SCT_EV11_STATE_STATEMSK9_Msk (0x01UL << SCT_EV11_STATE_STATEMSK9_Pos) /*!< SCT EV11_STATE: STATEMSK9 Mask */ +#define SCT_EV11_STATE_STATEMSK10_Pos 10 /*!< SCT EV11_STATE: STATEMSK10 Position */ +#define SCT_EV11_STATE_STATEMSK10_Msk (0x01UL << SCT_EV11_STATE_STATEMSK10_Pos) /*!< SCT EV11_STATE: STATEMSK10 Mask */ +#define SCT_EV11_STATE_STATEMSK11_Pos 11 /*!< SCT EV11_STATE: STATEMSK11 Position */ +#define SCT_EV11_STATE_STATEMSK11_Msk (0x01UL << SCT_EV11_STATE_STATEMSK11_Pos) /*!< SCT EV11_STATE: STATEMSK11 Mask */ +#define SCT_EV11_STATE_STATEMSK12_Pos 12 /*!< SCT EV11_STATE: STATEMSK12 Position */ +#define SCT_EV11_STATE_STATEMSK12_Msk (0x01UL << SCT_EV11_STATE_STATEMSK12_Pos) /*!< SCT EV11_STATE: STATEMSK12 Mask */ +#define SCT_EV11_STATE_STATEMSK13_Pos 13 /*!< SCT EV11_STATE: STATEMSK13 Position */ +#define SCT_EV11_STATE_STATEMSK13_Msk (0x01UL << SCT_EV11_STATE_STATEMSK13_Pos) /*!< SCT EV11_STATE: STATEMSK13 Mask */ +#define SCT_EV11_STATE_STATEMSK14_Pos 14 /*!< SCT EV11_STATE: STATEMSK14 Position */ +#define SCT_EV11_STATE_STATEMSK14_Msk (0x01UL << SCT_EV11_STATE_STATEMSK14_Pos) /*!< SCT EV11_STATE: STATEMSK14 Mask */ +#define SCT_EV11_STATE_STATEMSK15_Pos 15 /*!< SCT EV11_STATE: STATEMSK15 Position */ +#define SCT_EV11_STATE_STATEMSK15_Msk (0x01UL << SCT_EV11_STATE_STATEMSK15_Pos) /*!< SCT EV11_STATE: STATEMSK15 Mask */ +#define SCT_EV11_STATE_STATEMSK16_Pos 16 /*!< SCT EV11_STATE: STATEMSK16 Position */ +#define SCT_EV11_STATE_STATEMSK16_Msk (0x01UL << SCT_EV11_STATE_STATEMSK16_Pos) /*!< SCT EV11_STATE: STATEMSK16 Mask */ +#define SCT_EV11_STATE_STATEMSK17_Pos 17 /*!< SCT EV11_STATE: STATEMSK17 Position */ +#define SCT_EV11_STATE_STATEMSK17_Msk (0x01UL << SCT_EV11_STATE_STATEMSK17_Pos) /*!< SCT EV11_STATE: STATEMSK17 Mask */ +#define SCT_EV11_STATE_STATEMSK18_Pos 18 /*!< SCT EV11_STATE: STATEMSK18 Position */ +#define SCT_EV11_STATE_STATEMSK18_Msk (0x01UL << SCT_EV11_STATE_STATEMSK18_Pos) /*!< SCT EV11_STATE: STATEMSK18 Mask */ +#define SCT_EV11_STATE_STATEMSK19_Pos 19 /*!< SCT EV11_STATE: STATEMSK19 Position */ +#define SCT_EV11_STATE_STATEMSK19_Msk (0x01UL << SCT_EV11_STATE_STATEMSK19_Pos) /*!< SCT EV11_STATE: STATEMSK19 Mask */ +#define SCT_EV11_STATE_STATEMSK20_Pos 20 /*!< SCT EV11_STATE: STATEMSK20 Position */ +#define SCT_EV11_STATE_STATEMSK20_Msk (0x01UL << SCT_EV11_STATE_STATEMSK20_Pos) /*!< SCT EV11_STATE: STATEMSK20 Mask */ +#define SCT_EV11_STATE_STATEMSK21_Pos 21 /*!< SCT EV11_STATE: STATEMSK21 Position */ +#define SCT_EV11_STATE_STATEMSK21_Msk (0x01UL << SCT_EV11_STATE_STATEMSK21_Pos) /*!< SCT EV11_STATE: STATEMSK21 Mask */ +#define SCT_EV11_STATE_STATEMSK22_Pos 22 /*!< SCT EV11_STATE: STATEMSK22 Position */ +#define SCT_EV11_STATE_STATEMSK22_Msk (0x01UL << SCT_EV11_STATE_STATEMSK22_Pos) /*!< SCT EV11_STATE: STATEMSK22 Mask */ +#define SCT_EV11_STATE_STATEMSK23_Pos 23 /*!< SCT EV11_STATE: STATEMSK23 Position */ +#define SCT_EV11_STATE_STATEMSK23_Msk (0x01UL << SCT_EV11_STATE_STATEMSK23_Pos) /*!< SCT EV11_STATE: STATEMSK23 Mask */ +#define SCT_EV11_STATE_STATEMSK24_Pos 24 /*!< SCT EV11_STATE: STATEMSK24 Position */ +#define SCT_EV11_STATE_STATEMSK24_Msk (0x01UL << SCT_EV11_STATE_STATEMSK24_Pos) /*!< SCT EV11_STATE: STATEMSK24 Mask */ +#define SCT_EV11_STATE_STATEMSK25_Pos 25 /*!< SCT EV11_STATE: STATEMSK25 Position */ +#define SCT_EV11_STATE_STATEMSK25_Msk (0x01UL << SCT_EV11_STATE_STATEMSK25_Pos) /*!< SCT EV11_STATE: STATEMSK25 Mask */ +#define SCT_EV11_STATE_STATEMSK26_Pos 26 /*!< SCT EV11_STATE: STATEMSK26 Position */ +#define SCT_EV11_STATE_STATEMSK26_Msk (0x01UL << SCT_EV11_STATE_STATEMSK26_Pos) /*!< SCT EV11_STATE: STATEMSK26 Mask */ +#define SCT_EV11_STATE_STATEMSK27_Pos 27 /*!< SCT EV11_STATE: STATEMSK27 Position */ +#define SCT_EV11_STATE_STATEMSK27_Msk (0x01UL << SCT_EV11_STATE_STATEMSK27_Pos) /*!< SCT EV11_STATE: STATEMSK27 Mask */ +#define SCT_EV11_STATE_STATEMSK28_Pos 28 /*!< SCT EV11_STATE: STATEMSK28 Position */ +#define SCT_EV11_STATE_STATEMSK28_Msk (0x01UL << SCT_EV11_STATE_STATEMSK28_Pos) /*!< SCT EV11_STATE: STATEMSK28 Mask */ +#define SCT_EV11_STATE_STATEMSK29_Pos 29 /*!< SCT EV11_STATE: STATEMSK29 Position */ +#define SCT_EV11_STATE_STATEMSK29_Msk (0x01UL << SCT_EV11_STATE_STATEMSK29_Pos) /*!< SCT EV11_STATE: STATEMSK29 Mask */ +#define SCT_EV11_STATE_STATEMSK30_Pos 30 /*!< SCT EV11_STATE: STATEMSK30 Position */ +#define SCT_EV11_STATE_STATEMSK30_Msk (0x01UL << SCT_EV11_STATE_STATEMSK30_Pos) /*!< SCT EV11_STATE: STATEMSK30 Mask */ +#define SCT_EV11_STATE_STATEMSK31_Pos 31 /*!< SCT EV11_STATE: STATEMSK31 Position */ +#define SCT_EV11_STATE_STATEMSK31_Msk (0x01UL << SCT_EV11_STATE_STATEMSK31_Pos) /*!< SCT EV11_STATE: STATEMSK31 Mask */ + +/* -------------------------------- SCT_EV11_CTRL ------------------------------- */ +#define SCT_EV11_CTRL_MATCHSEL_Pos 0 /*!< SCT EV11_CTRL: MATCHSEL Position */ +#define SCT_EV11_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV11_CTRL_MATCHSEL_Pos) /*!< SCT EV11_CTRL: MATCHSEL Mask */ +#define SCT_EV11_CTRL_HEVENT_Pos 4 /*!< SCT EV11_CTRL: HEVENT Position */ +#define SCT_EV11_CTRL_HEVENT_Msk (0x01UL << SCT_EV11_CTRL_HEVENT_Pos) /*!< SCT EV11_CTRL: HEVENT Mask */ +#define SCT_EV11_CTRL_OUTSEL_Pos 5 /*!< SCT EV11_CTRL: OUTSEL Position */ +#define SCT_EV11_CTRL_OUTSEL_Msk (0x01UL << SCT_EV11_CTRL_OUTSEL_Pos) /*!< SCT EV11_CTRL: OUTSEL Mask */ +#define SCT_EV11_CTRL_IOSEL_Pos 6 /*!< SCT EV11_CTRL: IOSEL Position */ +#define SCT_EV11_CTRL_IOSEL_Msk (0x0fUL << SCT_EV11_CTRL_IOSEL_Pos) /*!< SCT EV11_CTRL: IOSEL Mask */ +#define SCT_EV11_CTRL_IOCOND_Pos 10 /*!< SCT EV11_CTRL: IOCOND Position */ +#define SCT_EV11_CTRL_IOCOND_Msk (0x03UL << SCT_EV11_CTRL_IOCOND_Pos) /*!< SCT EV11_CTRL: IOCOND Mask */ +#define SCT_EV11_CTRL_COMBMODE_Pos 12 /*!< SCT EV11_CTRL: COMBMODE Position */ +#define SCT_EV11_CTRL_COMBMODE_Msk (0x03UL << SCT_EV11_CTRL_COMBMODE_Pos) /*!< SCT EV11_CTRL: COMBMODE Mask */ +#define SCT_EV11_CTRL_STATELD_Pos 14 /*!< SCT EV11_CTRL: STATELD Position */ +#define SCT_EV11_CTRL_STATELD_Msk (0x01UL << SCT_EV11_CTRL_STATELD_Pos) /*!< SCT EV11_CTRL: STATELD Mask */ +#define SCT_EV11_CTRL_STATEV_Pos 15 /*!< SCT EV11_CTRL: STATEV Position */ +#define SCT_EV11_CTRL_STATEV_Msk (0x1fUL << SCT_EV11_CTRL_STATEV_Pos) /*!< SCT EV11_CTRL: STATEV Mask */ +#define SCT_EV11_CTRL_MATCHMEM_Pos 20 /*!< SCT EV11_CTRL: MATCHMEM Position */ +#define SCT_EV11_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV11_CTRL_MATCHMEM_Pos) /*!< SCT EV11_CTRL: MATCHMEM Mask */ +#define SCT_EV11_CTRL_DIRECTION_Pos 21 /*!< SCT EV11_CTRL: DIRECTION Position */ +#define SCT_EV11_CTRL_DIRECTION_Msk (0x03UL << SCT_EV11_CTRL_DIRECTION_Pos) /*!< SCT EV11_CTRL: DIRECTION Mask */ + +/* ------------------------------- SCT_EV12_STATE ------------------------------- */ +#define SCT_EV12_STATE_STATEMSK0_Pos 0 /*!< SCT EV12_STATE: STATEMSK0 Position */ +#define SCT_EV12_STATE_STATEMSK0_Msk (0x01UL << SCT_EV12_STATE_STATEMSK0_Pos) /*!< SCT EV12_STATE: STATEMSK0 Mask */ +#define SCT_EV12_STATE_STATEMSK1_Pos 1 /*!< SCT EV12_STATE: STATEMSK1 Position */ +#define SCT_EV12_STATE_STATEMSK1_Msk (0x01UL << SCT_EV12_STATE_STATEMSK1_Pos) /*!< SCT EV12_STATE: STATEMSK1 Mask */ +#define SCT_EV12_STATE_STATEMSK2_Pos 2 /*!< SCT EV12_STATE: STATEMSK2 Position */ +#define SCT_EV12_STATE_STATEMSK2_Msk (0x01UL << SCT_EV12_STATE_STATEMSK2_Pos) /*!< SCT EV12_STATE: STATEMSK2 Mask */ +#define SCT_EV12_STATE_STATEMSK3_Pos 3 /*!< SCT EV12_STATE: STATEMSK3 Position */ +#define SCT_EV12_STATE_STATEMSK3_Msk (0x01UL << SCT_EV12_STATE_STATEMSK3_Pos) /*!< SCT EV12_STATE: STATEMSK3 Mask */ +#define SCT_EV12_STATE_STATEMSK4_Pos 4 /*!< SCT EV12_STATE: STATEMSK4 Position */ +#define SCT_EV12_STATE_STATEMSK4_Msk (0x01UL << SCT_EV12_STATE_STATEMSK4_Pos) /*!< SCT EV12_STATE: STATEMSK4 Mask */ +#define SCT_EV12_STATE_STATEMSK5_Pos 5 /*!< SCT EV12_STATE: STATEMSK5 Position */ +#define SCT_EV12_STATE_STATEMSK5_Msk (0x01UL << SCT_EV12_STATE_STATEMSK5_Pos) /*!< SCT EV12_STATE: STATEMSK5 Mask */ +#define SCT_EV12_STATE_STATEMSK6_Pos 6 /*!< SCT EV12_STATE: STATEMSK6 Position */ +#define SCT_EV12_STATE_STATEMSK6_Msk (0x01UL << SCT_EV12_STATE_STATEMSK6_Pos) /*!< SCT EV12_STATE: STATEMSK6 Mask */ +#define SCT_EV12_STATE_STATEMSK7_Pos 7 /*!< SCT EV12_STATE: STATEMSK7 Position */ +#define SCT_EV12_STATE_STATEMSK7_Msk (0x01UL << SCT_EV12_STATE_STATEMSK7_Pos) /*!< SCT EV12_STATE: STATEMSK7 Mask */ +#define SCT_EV12_STATE_STATEMSK8_Pos 8 /*!< SCT EV12_STATE: STATEMSK8 Position */ +#define SCT_EV12_STATE_STATEMSK8_Msk (0x01UL << SCT_EV12_STATE_STATEMSK8_Pos) /*!< SCT EV12_STATE: STATEMSK8 Mask */ +#define SCT_EV12_STATE_STATEMSK9_Pos 9 /*!< SCT EV12_STATE: STATEMSK9 Position */ +#define SCT_EV12_STATE_STATEMSK9_Msk (0x01UL << SCT_EV12_STATE_STATEMSK9_Pos) /*!< SCT EV12_STATE: STATEMSK9 Mask */ +#define SCT_EV12_STATE_STATEMSK10_Pos 10 /*!< SCT EV12_STATE: STATEMSK10 Position */ +#define SCT_EV12_STATE_STATEMSK10_Msk (0x01UL << SCT_EV12_STATE_STATEMSK10_Pos) /*!< SCT EV12_STATE: STATEMSK10 Mask */ +#define SCT_EV12_STATE_STATEMSK11_Pos 11 /*!< SCT EV12_STATE: STATEMSK11 Position */ +#define SCT_EV12_STATE_STATEMSK11_Msk (0x01UL << SCT_EV12_STATE_STATEMSK11_Pos) /*!< SCT EV12_STATE: STATEMSK11 Mask */ +#define SCT_EV12_STATE_STATEMSK12_Pos 12 /*!< SCT EV12_STATE: STATEMSK12 Position */ +#define SCT_EV12_STATE_STATEMSK12_Msk (0x01UL << SCT_EV12_STATE_STATEMSK12_Pos) /*!< SCT EV12_STATE: STATEMSK12 Mask */ +#define SCT_EV12_STATE_STATEMSK13_Pos 13 /*!< SCT EV12_STATE: STATEMSK13 Position */ +#define SCT_EV12_STATE_STATEMSK13_Msk (0x01UL << SCT_EV12_STATE_STATEMSK13_Pos) /*!< SCT EV12_STATE: STATEMSK13 Mask */ +#define SCT_EV12_STATE_STATEMSK14_Pos 14 /*!< SCT EV12_STATE: STATEMSK14 Position */ +#define SCT_EV12_STATE_STATEMSK14_Msk (0x01UL << SCT_EV12_STATE_STATEMSK14_Pos) /*!< SCT EV12_STATE: STATEMSK14 Mask */ +#define SCT_EV12_STATE_STATEMSK15_Pos 15 /*!< SCT EV12_STATE: STATEMSK15 Position */ +#define SCT_EV12_STATE_STATEMSK15_Msk (0x01UL << SCT_EV12_STATE_STATEMSK15_Pos) /*!< SCT EV12_STATE: STATEMSK15 Mask */ +#define SCT_EV12_STATE_STATEMSK16_Pos 16 /*!< SCT EV12_STATE: STATEMSK16 Position */ +#define SCT_EV12_STATE_STATEMSK16_Msk (0x01UL << SCT_EV12_STATE_STATEMSK16_Pos) /*!< SCT EV12_STATE: STATEMSK16 Mask */ +#define SCT_EV12_STATE_STATEMSK17_Pos 17 /*!< SCT EV12_STATE: STATEMSK17 Position */ +#define SCT_EV12_STATE_STATEMSK17_Msk (0x01UL << SCT_EV12_STATE_STATEMSK17_Pos) /*!< SCT EV12_STATE: STATEMSK17 Mask */ +#define SCT_EV12_STATE_STATEMSK18_Pos 18 /*!< SCT EV12_STATE: STATEMSK18 Position */ +#define SCT_EV12_STATE_STATEMSK18_Msk (0x01UL << SCT_EV12_STATE_STATEMSK18_Pos) /*!< SCT EV12_STATE: STATEMSK18 Mask */ +#define SCT_EV12_STATE_STATEMSK19_Pos 19 /*!< SCT EV12_STATE: STATEMSK19 Position */ +#define SCT_EV12_STATE_STATEMSK19_Msk (0x01UL << SCT_EV12_STATE_STATEMSK19_Pos) /*!< SCT EV12_STATE: STATEMSK19 Mask */ +#define SCT_EV12_STATE_STATEMSK20_Pos 20 /*!< SCT EV12_STATE: STATEMSK20 Position */ +#define SCT_EV12_STATE_STATEMSK20_Msk (0x01UL << SCT_EV12_STATE_STATEMSK20_Pos) /*!< SCT EV12_STATE: STATEMSK20 Mask */ +#define SCT_EV12_STATE_STATEMSK21_Pos 21 /*!< SCT EV12_STATE: STATEMSK21 Position */ +#define SCT_EV12_STATE_STATEMSK21_Msk (0x01UL << SCT_EV12_STATE_STATEMSK21_Pos) /*!< SCT EV12_STATE: STATEMSK21 Mask */ +#define SCT_EV12_STATE_STATEMSK22_Pos 22 /*!< SCT EV12_STATE: STATEMSK22 Position */ +#define SCT_EV12_STATE_STATEMSK22_Msk (0x01UL << SCT_EV12_STATE_STATEMSK22_Pos) /*!< SCT EV12_STATE: STATEMSK22 Mask */ +#define SCT_EV12_STATE_STATEMSK23_Pos 23 /*!< SCT EV12_STATE: STATEMSK23 Position */ +#define SCT_EV12_STATE_STATEMSK23_Msk (0x01UL << SCT_EV12_STATE_STATEMSK23_Pos) /*!< SCT EV12_STATE: STATEMSK23 Mask */ +#define SCT_EV12_STATE_STATEMSK24_Pos 24 /*!< SCT EV12_STATE: STATEMSK24 Position */ +#define SCT_EV12_STATE_STATEMSK24_Msk (0x01UL << SCT_EV12_STATE_STATEMSK24_Pos) /*!< SCT EV12_STATE: STATEMSK24 Mask */ +#define SCT_EV12_STATE_STATEMSK25_Pos 25 /*!< SCT EV12_STATE: STATEMSK25 Position */ +#define SCT_EV12_STATE_STATEMSK25_Msk (0x01UL << SCT_EV12_STATE_STATEMSK25_Pos) /*!< SCT EV12_STATE: STATEMSK25 Mask */ +#define SCT_EV12_STATE_STATEMSK26_Pos 26 /*!< SCT EV12_STATE: STATEMSK26 Position */ +#define SCT_EV12_STATE_STATEMSK26_Msk (0x01UL << SCT_EV12_STATE_STATEMSK26_Pos) /*!< SCT EV12_STATE: STATEMSK26 Mask */ +#define SCT_EV12_STATE_STATEMSK27_Pos 27 /*!< SCT EV12_STATE: STATEMSK27 Position */ +#define SCT_EV12_STATE_STATEMSK27_Msk (0x01UL << SCT_EV12_STATE_STATEMSK27_Pos) /*!< SCT EV12_STATE: STATEMSK27 Mask */ +#define SCT_EV12_STATE_STATEMSK28_Pos 28 /*!< SCT EV12_STATE: STATEMSK28 Position */ +#define SCT_EV12_STATE_STATEMSK28_Msk (0x01UL << SCT_EV12_STATE_STATEMSK28_Pos) /*!< SCT EV12_STATE: STATEMSK28 Mask */ +#define SCT_EV12_STATE_STATEMSK29_Pos 29 /*!< SCT EV12_STATE: STATEMSK29 Position */ +#define SCT_EV12_STATE_STATEMSK29_Msk (0x01UL << SCT_EV12_STATE_STATEMSK29_Pos) /*!< SCT EV12_STATE: STATEMSK29 Mask */ +#define SCT_EV12_STATE_STATEMSK30_Pos 30 /*!< SCT EV12_STATE: STATEMSK30 Position */ +#define SCT_EV12_STATE_STATEMSK30_Msk (0x01UL << SCT_EV12_STATE_STATEMSK30_Pos) /*!< SCT EV12_STATE: STATEMSK30 Mask */ +#define SCT_EV12_STATE_STATEMSK31_Pos 31 /*!< SCT EV12_STATE: STATEMSK31 Position */ +#define SCT_EV12_STATE_STATEMSK31_Msk (0x01UL << SCT_EV12_STATE_STATEMSK31_Pos) /*!< SCT EV12_STATE: STATEMSK31 Mask */ + +/* -------------------------------- SCT_EV12_CTRL ------------------------------- */ +#define SCT_EV12_CTRL_MATCHSEL_Pos 0 /*!< SCT EV12_CTRL: MATCHSEL Position */ +#define SCT_EV12_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV12_CTRL_MATCHSEL_Pos) /*!< SCT EV12_CTRL: MATCHSEL Mask */ +#define SCT_EV12_CTRL_HEVENT_Pos 4 /*!< SCT EV12_CTRL: HEVENT Position */ +#define SCT_EV12_CTRL_HEVENT_Msk (0x01UL << SCT_EV12_CTRL_HEVENT_Pos) /*!< SCT EV12_CTRL: HEVENT Mask */ +#define SCT_EV12_CTRL_OUTSEL_Pos 5 /*!< SCT EV12_CTRL: OUTSEL Position */ +#define SCT_EV12_CTRL_OUTSEL_Msk (0x01UL << SCT_EV12_CTRL_OUTSEL_Pos) /*!< SCT EV12_CTRL: OUTSEL Mask */ +#define SCT_EV12_CTRL_IOSEL_Pos 6 /*!< SCT EV12_CTRL: IOSEL Position */ +#define SCT_EV12_CTRL_IOSEL_Msk (0x0fUL << SCT_EV12_CTRL_IOSEL_Pos) /*!< SCT EV12_CTRL: IOSEL Mask */ +#define SCT_EV12_CTRL_IOCOND_Pos 10 /*!< SCT EV12_CTRL: IOCOND Position */ +#define SCT_EV12_CTRL_IOCOND_Msk (0x03UL << SCT_EV12_CTRL_IOCOND_Pos) /*!< SCT EV12_CTRL: IOCOND Mask */ +#define SCT_EV12_CTRL_COMBMODE_Pos 12 /*!< SCT EV12_CTRL: COMBMODE Position */ +#define SCT_EV12_CTRL_COMBMODE_Msk (0x03UL << SCT_EV12_CTRL_COMBMODE_Pos) /*!< SCT EV12_CTRL: COMBMODE Mask */ +#define SCT_EV12_CTRL_STATELD_Pos 14 /*!< SCT EV12_CTRL: STATELD Position */ +#define SCT_EV12_CTRL_STATELD_Msk (0x01UL << SCT_EV12_CTRL_STATELD_Pos) /*!< SCT EV12_CTRL: STATELD Mask */ +#define SCT_EV12_CTRL_STATEV_Pos 15 /*!< SCT EV12_CTRL: STATEV Position */ +#define SCT_EV12_CTRL_STATEV_Msk (0x1fUL << SCT_EV12_CTRL_STATEV_Pos) /*!< SCT EV12_CTRL: STATEV Mask */ +#define SCT_EV12_CTRL_MATCHMEM_Pos 20 /*!< SCT EV12_CTRL: MATCHMEM Position */ +#define SCT_EV12_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV12_CTRL_MATCHMEM_Pos) /*!< SCT EV12_CTRL: MATCHMEM Mask */ +#define SCT_EV12_CTRL_DIRECTION_Pos 21 /*!< SCT EV12_CTRL: DIRECTION Position */ +#define SCT_EV12_CTRL_DIRECTION_Msk (0x03UL << SCT_EV12_CTRL_DIRECTION_Pos) /*!< SCT EV12_CTRL: DIRECTION Mask */ + +/* ------------------------------- SCT_EV13_STATE ------------------------------- */ +#define SCT_EV13_STATE_STATEMSK0_Pos 0 /*!< SCT EV13_STATE: STATEMSK0 Position */ +#define SCT_EV13_STATE_STATEMSK0_Msk (0x01UL << SCT_EV13_STATE_STATEMSK0_Pos) /*!< SCT EV13_STATE: STATEMSK0 Mask */ +#define SCT_EV13_STATE_STATEMSK1_Pos 1 /*!< SCT EV13_STATE: STATEMSK1 Position */ +#define SCT_EV13_STATE_STATEMSK1_Msk (0x01UL << SCT_EV13_STATE_STATEMSK1_Pos) /*!< SCT EV13_STATE: STATEMSK1 Mask */ +#define SCT_EV13_STATE_STATEMSK2_Pos 2 /*!< SCT EV13_STATE: STATEMSK2 Position */ +#define SCT_EV13_STATE_STATEMSK2_Msk (0x01UL << SCT_EV13_STATE_STATEMSK2_Pos) /*!< SCT EV13_STATE: STATEMSK2 Mask */ +#define SCT_EV13_STATE_STATEMSK3_Pos 3 /*!< SCT EV13_STATE: STATEMSK3 Position */ +#define SCT_EV13_STATE_STATEMSK3_Msk (0x01UL << SCT_EV13_STATE_STATEMSK3_Pos) /*!< SCT EV13_STATE: STATEMSK3 Mask */ +#define SCT_EV13_STATE_STATEMSK4_Pos 4 /*!< SCT EV13_STATE: STATEMSK4 Position */ +#define SCT_EV13_STATE_STATEMSK4_Msk (0x01UL << SCT_EV13_STATE_STATEMSK4_Pos) /*!< SCT EV13_STATE: STATEMSK4 Mask */ +#define SCT_EV13_STATE_STATEMSK5_Pos 5 /*!< SCT EV13_STATE: STATEMSK5 Position */ +#define SCT_EV13_STATE_STATEMSK5_Msk (0x01UL << SCT_EV13_STATE_STATEMSK5_Pos) /*!< SCT EV13_STATE: STATEMSK5 Mask */ +#define SCT_EV13_STATE_STATEMSK6_Pos 6 /*!< SCT EV13_STATE: STATEMSK6 Position */ +#define SCT_EV13_STATE_STATEMSK6_Msk (0x01UL << SCT_EV13_STATE_STATEMSK6_Pos) /*!< SCT EV13_STATE: STATEMSK6 Mask */ +#define SCT_EV13_STATE_STATEMSK7_Pos 7 /*!< SCT EV13_STATE: STATEMSK7 Position */ +#define SCT_EV13_STATE_STATEMSK7_Msk (0x01UL << SCT_EV13_STATE_STATEMSK7_Pos) /*!< SCT EV13_STATE: STATEMSK7 Mask */ +#define SCT_EV13_STATE_STATEMSK8_Pos 8 /*!< SCT EV13_STATE: STATEMSK8 Position */ +#define SCT_EV13_STATE_STATEMSK8_Msk (0x01UL << SCT_EV13_STATE_STATEMSK8_Pos) /*!< SCT EV13_STATE: STATEMSK8 Mask */ +#define SCT_EV13_STATE_STATEMSK9_Pos 9 /*!< SCT EV13_STATE: STATEMSK9 Position */ +#define SCT_EV13_STATE_STATEMSK9_Msk (0x01UL << SCT_EV13_STATE_STATEMSK9_Pos) /*!< SCT EV13_STATE: STATEMSK9 Mask */ +#define SCT_EV13_STATE_STATEMSK10_Pos 10 /*!< SCT EV13_STATE: STATEMSK10 Position */ +#define SCT_EV13_STATE_STATEMSK10_Msk (0x01UL << SCT_EV13_STATE_STATEMSK10_Pos) /*!< SCT EV13_STATE: STATEMSK10 Mask */ +#define SCT_EV13_STATE_STATEMSK11_Pos 11 /*!< SCT EV13_STATE: STATEMSK11 Position */ +#define SCT_EV13_STATE_STATEMSK11_Msk (0x01UL << SCT_EV13_STATE_STATEMSK11_Pos) /*!< SCT EV13_STATE: STATEMSK11 Mask */ +#define SCT_EV13_STATE_STATEMSK12_Pos 12 /*!< SCT EV13_STATE: STATEMSK12 Position */ +#define SCT_EV13_STATE_STATEMSK12_Msk (0x01UL << SCT_EV13_STATE_STATEMSK12_Pos) /*!< SCT EV13_STATE: STATEMSK12 Mask */ +#define SCT_EV13_STATE_STATEMSK13_Pos 13 /*!< SCT EV13_STATE: STATEMSK13 Position */ +#define SCT_EV13_STATE_STATEMSK13_Msk (0x01UL << SCT_EV13_STATE_STATEMSK13_Pos) /*!< SCT EV13_STATE: STATEMSK13 Mask */ +#define SCT_EV13_STATE_STATEMSK14_Pos 14 /*!< SCT EV13_STATE: STATEMSK14 Position */ +#define SCT_EV13_STATE_STATEMSK14_Msk (0x01UL << SCT_EV13_STATE_STATEMSK14_Pos) /*!< SCT EV13_STATE: STATEMSK14 Mask */ +#define SCT_EV13_STATE_STATEMSK15_Pos 15 /*!< SCT EV13_STATE: STATEMSK15 Position */ +#define SCT_EV13_STATE_STATEMSK15_Msk (0x01UL << SCT_EV13_STATE_STATEMSK15_Pos) /*!< SCT EV13_STATE: STATEMSK15 Mask */ +#define SCT_EV13_STATE_STATEMSK16_Pos 16 /*!< SCT EV13_STATE: STATEMSK16 Position */ +#define SCT_EV13_STATE_STATEMSK16_Msk (0x01UL << SCT_EV13_STATE_STATEMSK16_Pos) /*!< SCT EV13_STATE: STATEMSK16 Mask */ +#define SCT_EV13_STATE_STATEMSK17_Pos 17 /*!< SCT EV13_STATE: STATEMSK17 Position */ +#define SCT_EV13_STATE_STATEMSK17_Msk (0x01UL << SCT_EV13_STATE_STATEMSK17_Pos) /*!< SCT EV13_STATE: STATEMSK17 Mask */ +#define SCT_EV13_STATE_STATEMSK18_Pos 18 /*!< SCT EV13_STATE: STATEMSK18 Position */ +#define SCT_EV13_STATE_STATEMSK18_Msk (0x01UL << SCT_EV13_STATE_STATEMSK18_Pos) /*!< SCT EV13_STATE: STATEMSK18 Mask */ +#define SCT_EV13_STATE_STATEMSK19_Pos 19 /*!< SCT EV13_STATE: STATEMSK19 Position */ +#define SCT_EV13_STATE_STATEMSK19_Msk (0x01UL << SCT_EV13_STATE_STATEMSK19_Pos) /*!< SCT EV13_STATE: STATEMSK19 Mask */ +#define SCT_EV13_STATE_STATEMSK20_Pos 20 /*!< SCT EV13_STATE: STATEMSK20 Position */ +#define SCT_EV13_STATE_STATEMSK20_Msk (0x01UL << SCT_EV13_STATE_STATEMSK20_Pos) /*!< SCT EV13_STATE: STATEMSK20 Mask */ +#define SCT_EV13_STATE_STATEMSK21_Pos 21 /*!< SCT EV13_STATE: STATEMSK21 Position */ +#define SCT_EV13_STATE_STATEMSK21_Msk (0x01UL << SCT_EV13_STATE_STATEMSK21_Pos) /*!< SCT EV13_STATE: STATEMSK21 Mask */ +#define SCT_EV13_STATE_STATEMSK22_Pos 22 /*!< SCT EV13_STATE: STATEMSK22 Position */ +#define SCT_EV13_STATE_STATEMSK22_Msk (0x01UL << SCT_EV13_STATE_STATEMSK22_Pos) /*!< SCT EV13_STATE: STATEMSK22 Mask */ +#define SCT_EV13_STATE_STATEMSK23_Pos 23 /*!< SCT EV13_STATE: STATEMSK23 Position */ +#define SCT_EV13_STATE_STATEMSK23_Msk (0x01UL << SCT_EV13_STATE_STATEMSK23_Pos) /*!< SCT EV13_STATE: STATEMSK23 Mask */ +#define SCT_EV13_STATE_STATEMSK24_Pos 24 /*!< SCT EV13_STATE: STATEMSK24 Position */ +#define SCT_EV13_STATE_STATEMSK24_Msk (0x01UL << SCT_EV13_STATE_STATEMSK24_Pos) /*!< SCT EV13_STATE: STATEMSK24 Mask */ +#define SCT_EV13_STATE_STATEMSK25_Pos 25 /*!< SCT EV13_STATE: STATEMSK25 Position */ +#define SCT_EV13_STATE_STATEMSK25_Msk (0x01UL << SCT_EV13_STATE_STATEMSK25_Pos) /*!< SCT EV13_STATE: STATEMSK25 Mask */ +#define SCT_EV13_STATE_STATEMSK26_Pos 26 /*!< SCT EV13_STATE: STATEMSK26 Position */ +#define SCT_EV13_STATE_STATEMSK26_Msk (0x01UL << SCT_EV13_STATE_STATEMSK26_Pos) /*!< SCT EV13_STATE: STATEMSK26 Mask */ +#define SCT_EV13_STATE_STATEMSK27_Pos 27 /*!< SCT EV13_STATE: STATEMSK27 Position */ +#define SCT_EV13_STATE_STATEMSK27_Msk (0x01UL << SCT_EV13_STATE_STATEMSK27_Pos) /*!< SCT EV13_STATE: STATEMSK27 Mask */ +#define SCT_EV13_STATE_STATEMSK28_Pos 28 /*!< SCT EV13_STATE: STATEMSK28 Position */ +#define SCT_EV13_STATE_STATEMSK28_Msk (0x01UL << SCT_EV13_STATE_STATEMSK28_Pos) /*!< SCT EV13_STATE: STATEMSK28 Mask */ +#define SCT_EV13_STATE_STATEMSK29_Pos 29 /*!< SCT EV13_STATE: STATEMSK29 Position */ +#define SCT_EV13_STATE_STATEMSK29_Msk (0x01UL << SCT_EV13_STATE_STATEMSK29_Pos) /*!< SCT EV13_STATE: STATEMSK29 Mask */ +#define SCT_EV13_STATE_STATEMSK30_Pos 30 /*!< SCT EV13_STATE: STATEMSK30 Position */ +#define SCT_EV13_STATE_STATEMSK30_Msk (0x01UL << SCT_EV13_STATE_STATEMSK30_Pos) /*!< SCT EV13_STATE: STATEMSK30 Mask */ +#define SCT_EV13_STATE_STATEMSK31_Pos 31 /*!< SCT EV13_STATE: STATEMSK31 Position */ +#define SCT_EV13_STATE_STATEMSK31_Msk (0x01UL << SCT_EV13_STATE_STATEMSK31_Pos) /*!< SCT EV13_STATE: STATEMSK31 Mask */ + +/* -------------------------------- SCT_EV13_CTRL ------------------------------- */ +#define SCT_EV13_CTRL_MATCHSEL_Pos 0 /*!< SCT EV13_CTRL: MATCHSEL Position */ +#define SCT_EV13_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV13_CTRL_MATCHSEL_Pos) /*!< SCT EV13_CTRL: MATCHSEL Mask */ +#define SCT_EV13_CTRL_HEVENT_Pos 4 /*!< SCT EV13_CTRL: HEVENT Position */ +#define SCT_EV13_CTRL_HEVENT_Msk (0x01UL << SCT_EV13_CTRL_HEVENT_Pos) /*!< SCT EV13_CTRL: HEVENT Mask */ +#define SCT_EV13_CTRL_OUTSEL_Pos 5 /*!< SCT EV13_CTRL: OUTSEL Position */ +#define SCT_EV13_CTRL_OUTSEL_Msk (0x01UL << SCT_EV13_CTRL_OUTSEL_Pos) /*!< SCT EV13_CTRL: OUTSEL Mask */ +#define SCT_EV13_CTRL_IOSEL_Pos 6 /*!< SCT EV13_CTRL: IOSEL Position */ +#define SCT_EV13_CTRL_IOSEL_Msk (0x0fUL << SCT_EV13_CTRL_IOSEL_Pos) /*!< SCT EV13_CTRL: IOSEL Mask */ +#define SCT_EV13_CTRL_IOCOND_Pos 10 /*!< SCT EV13_CTRL: IOCOND Position */ +#define SCT_EV13_CTRL_IOCOND_Msk (0x03UL << SCT_EV13_CTRL_IOCOND_Pos) /*!< SCT EV13_CTRL: IOCOND Mask */ +#define SCT_EV13_CTRL_COMBMODE_Pos 12 /*!< SCT EV13_CTRL: COMBMODE Position */ +#define SCT_EV13_CTRL_COMBMODE_Msk (0x03UL << SCT_EV13_CTRL_COMBMODE_Pos) /*!< SCT EV13_CTRL: COMBMODE Mask */ +#define SCT_EV13_CTRL_STATELD_Pos 14 /*!< SCT EV13_CTRL: STATELD Position */ +#define SCT_EV13_CTRL_STATELD_Msk (0x01UL << SCT_EV13_CTRL_STATELD_Pos) /*!< SCT EV13_CTRL: STATELD Mask */ +#define SCT_EV13_CTRL_STATEV_Pos 15 /*!< SCT EV13_CTRL: STATEV Position */ +#define SCT_EV13_CTRL_STATEV_Msk (0x1fUL << SCT_EV13_CTRL_STATEV_Pos) /*!< SCT EV13_CTRL: STATEV Mask */ +#define SCT_EV13_CTRL_MATCHMEM_Pos 20 /*!< SCT EV13_CTRL: MATCHMEM Position */ +#define SCT_EV13_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV13_CTRL_MATCHMEM_Pos) /*!< SCT EV13_CTRL: MATCHMEM Mask */ +#define SCT_EV13_CTRL_DIRECTION_Pos 21 /*!< SCT EV13_CTRL: DIRECTION Position */ +#define SCT_EV13_CTRL_DIRECTION_Msk (0x03UL << SCT_EV13_CTRL_DIRECTION_Pos) /*!< SCT EV13_CTRL: DIRECTION Mask */ + +/* ------------------------------- SCT_EV14_STATE ------------------------------- */ +#define SCT_EV14_STATE_STATEMSK0_Pos 0 /*!< SCT EV14_STATE: STATEMSK0 Position */ +#define SCT_EV14_STATE_STATEMSK0_Msk (0x01UL << SCT_EV14_STATE_STATEMSK0_Pos) /*!< SCT EV14_STATE: STATEMSK0 Mask */ +#define SCT_EV14_STATE_STATEMSK1_Pos 1 /*!< SCT EV14_STATE: STATEMSK1 Position */ +#define SCT_EV14_STATE_STATEMSK1_Msk (0x01UL << SCT_EV14_STATE_STATEMSK1_Pos) /*!< SCT EV14_STATE: STATEMSK1 Mask */ +#define SCT_EV14_STATE_STATEMSK2_Pos 2 /*!< SCT EV14_STATE: STATEMSK2 Position */ +#define SCT_EV14_STATE_STATEMSK2_Msk (0x01UL << SCT_EV14_STATE_STATEMSK2_Pos) /*!< SCT EV14_STATE: STATEMSK2 Mask */ +#define SCT_EV14_STATE_STATEMSK3_Pos 3 /*!< SCT EV14_STATE: STATEMSK3 Position */ +#define SCT_EV14_STATE_STATEMSK3_Msk (0x01UL << SCT_EV14_STATE_STATEMSK3_Pos) /*!< SCT EV14_STATE: STATEMSK3 Mask */ +#define SCT_EV14_STATE_STATEMSK4_Pos 4 /*!< SCT EV14_STATE: STATEMSK4 Position */ +#define SCT_EV14_STATE_STATEMSK4_Msk (0x01UL << SCT_EV14_STATE_STATEMSK4_Pos) /*!< SCT EV14_STATE: STATEMSK4 Mask */ +#define SCT_EV14_STATE_STATEMSK5_Pos 5 /*!< SCT EV14_STATE: STATEMSK5 Position */ +#define SCT_EV14_STATE_STATEMSK5_Msk (0x01UL << SCT_EV14_STATE_STATEMSK5_Pos) /*!< SCT EV14_STATE: STATEMSK5 Mask */ +#define SCT_EV14_STATE_STATEMSK6_Pos 6 /*!< SCT EV14_STATE: STATEMSK6 Position */ +#define SCT_EV14_STATE_STATEMSK6_Msk (0x01UL << SCT_EV14_STATE_STATEMSK6_Pos) /*!< SCT EV14_STATE: STATEMSK6 Mask */ +#define SCT_EV14_STATE_STATEMSK7_Pos 7 /*!< SCT EV14_STATE: STATEMSK7 Position */ +#define SCT_EV14_STATE_STATEMSK7_Msk (0x01UL << SCT_EV14_STATE_STATEMSK7_Pos) /*!< SCT EV14_STATE: STATEMSK7 Mask */ +#define SCT_EV14_STATE_STATEMSK8_Pos 8 /*!< SCT EV14_STATE: STATEMSK8 Position */ +#define SCT_EV14_STATE_STATEMSK8_Msk (0x01UL << SCT_EV14_STATE_STATEMSK8_Pos) /*!< SCT EV14_STATE: STATEMSK8 Mask */ +#define SCT_EV14_STATE_STATEMSK9_Pos 9 /*!< SCT EV14_STATE: STATEMSK9 Position */ +#define SCT_EV14_STATE_STATEMSK9_Msk (0x01UL << SCT_EV14_STATE_STATEMSK9_Pos) /*!< SCT EV14_STATE: STATEMSK9 Mask */ +#define SCT_EV14_STATE_STATEMSK10_Pos 10 /*!< SCT EV14_STATE: STATEMSK10 Position */ +#define SCT_EV14_STATE_STATEMSK10_Msk (0x01UL << SCT_EV14_STATE_STATEMSK10_Pos) /*!< SCT EV14_STATE: STATEMSK10 Mask */ +#define SCT_EV14_STATE_STATEMSK11_Pos 11 /*!< SCT EV14_STATE: STATEMSK11 Position */ +#define SCT_EV14_STATE_STATEMSK11_Msk (0x01UL << SCT_EV14_STATE_STATEMSK11_Pos) /*!< SCT EV14_STATE: STATEMSK11 Mask */ +#define SCT_EV14_STATE_STATEMSK12_Pos 12 /*!< SCT EV14_STATE: STATEMSK12 Position */ +#define SCT_EV14_STATE_STATEMSK12_Msk (0x01UL << SCT_EV14_STATE_STATEMSK12_Pos) /*!< SCT EV14_STATE: STATEMSK12 Mask */ +#define SCT_EV14_STATE_STATEMSK13_Pos 13 /*!< SCT EV14_STATE: STATEMSK13 Position */ +#define SCT_EV14_STATE_STATEMSK13_Msk (0x01UL << SCT_EV14_STATE_STATEMSK13_Pos) /*!< SCT EV14_STATE: STATEMSK13 Mask */ +#define SCT_EV14_STATE_STATEMSK14_Pos 14 /*!< SCT EV14_STATE: STATEMSK14 Position */ +#define SCT_EV14_STATE_STATEMSK14_Msk (0x01UL << SCT_EV14_STATE_STATEMSK14_Pos) /*!< SCT EV14_STATE: STATEMSK14 Mask */ +#define SCT_EV14_STATE_STATEMSK15_Pos 15 /*!< SCT EV14_STATE: STATEMSK15 Position */ +#define SCT_EV14_STATE_STATEMSK15_Msk (0x01UL << SCT_EV14_STATE_STATEMSK15_Pos) /*!< SCT EV14_STATE: STATEMSK15 Mask */ +#define SCT_EV14_STATE_STATEMSK16_Pos 16 /*!< SCT EV14_STATE: STATEMSK16 Position */ +#define SCT_EV14_STATE_STATEMSK16_Msk (0x01UL << SCT_EV14_STATE_STATEMSK16_Pos) /*!< SCT EV14_STATE: STATEMSK16 Mask */ +#define SCT_EV14_STATE_STATEMSK17_Pos 17 /*!< SCT EV14_STATE: STATEMSK17 Position */ +#define SCT_EV14_STATE_STATEMSK17_Msk (0x01UL << SCT_EV14_STATE_STATEMSK17_Pos) /*!< SCT EV14_STATE: STATEMSK17 Mask */ +#define SCT_EV14_STATE_STATEMSK18_Pos 18 /*!< SCT EV14_STATE: STATEMSK18 Position */ +#define SCT_EV14_STATE_STATEMSK18_Msk (0x01UL << SCT_EV14_STATE_STATEMSK18_Pos) /*!< SCT EV14_STATE: STATEMSK18 Mask */ +#define SCT_EV14_STATE_STATEMSK19_Pos 19 /*!< SCT EV14_STATE: STATEMSK19 Position */ +#define SCT_EV14_STATE_STATEMSK19_Msk (0x01UL << SCT_EV14_STATE_STATEMSK19_Pos) /*!< SCT EV14_STATE: STATEMSK19 Mask */ +#define SCT_EV14_STATE_STATEMSK20_Pos 20 /*!< SCT EV14_STATE: STATEMSK20 Position */ +#define SCT_EV14_STATE_STATEMSK20_Msk (0x01UL << SCT_EV14_STATE_STATEMSK20_Pos) /*!< SCT EV14_STATE: STATEMSK20 Mask */ +#define SCT_EV14_STATE_STATEMSK21_Pos 21 /*!< SCT EV14_STATE: STATEMSK21 Position */ +#define SCT_EV14_STATE_STATEMSK21_Msk (0x01UL << SCT_EV14_STATE_STATEMSK21_Pos) /*!< SCT EV14_STATE: STATEMSK21 Mask */ +#define SCT_EV14_STATE_STATEMSK22_Pos 22 /*!< SCT EV14_STATE: STATEMSK22 Position */ +#define SCT_EV14_STATE_STATEMSK22_Msk (0x01UL << SCT_EV14_STATE_STATEMSK22_Pos) /*!< SCT EV14_STATE: STATEMSK22 Mask */ +#define SCT_EV14_STATE_STATEMSK23_Pos 23 /*!< SCT EV14_STATE: STATEMSK23 Position */ +#define SCT_EV14_STATE_STATEMSK23_Msk (0x01UL << SCT_EV14_STATE_STATEMSK23_Pos) /*!< SCT EV14_STATE: STATEMSK23 Mask */ +#define SCT_EV14_STATE_STATEMSK24_Pos 24 /*!< SCT EV14_STATE: STATEMSK24 Position */ +#define SCT_EV14_STATE_STATEMSK24_Msk (0x01UL << SCT_EV14_STATE_STATEMSK24_Pos) /*!< SCT EV14_STATE: STATEMSK24 Mask */ +#define SCT_EV14_STATE_STATEMSK25_Pos 25 /*!< SCT EV14_STATE: STATEMSK25 Position */ +#define SCT_EV14_STATE_STATEMSK25_Msk (0x01UL << SCT_EV14_STATE_STATEMSK25_Pos) /*!< SCT EV14_STATE: STATEMSK25 Mask */ +#define SCT_EV14_STATE_STATEMSK26_Pos 26 /*!< SCT EV14_STATE: STATEMSK26 Position */ +#define SCT_EV14_STATE_STATEMSK26_Msk (0x01UL << SCT_EV14_STATE_STATEMSK26_Pos) /*!< SCT EV14_STATE: STATEMSK26 Mask */ +#define SCT_EV14_STATE_STATEMSK27_Pos 27 /*!< SCT EV14_STATE: STATEMSK27 Position */ +#define SCT_EV14_STATE_STATEMSK27_Msk (0x01UL << SCT_EV14_STATE_STATEMSK27_Pos) /*!< SCT EV14_STATE: STATEMSK27 Mask */ +#define SCT_EV14_STATE_STATEMSK28_Pos 28 /*!< SCT EV14_STATE: STATEMSK28 Position */ +#define SCT_EV14_STATE_STATEMSK28_Msk (0x01UL << SCT_EV14_STATE_STATEMSK28_Pos) /*!< SCT EV14_STATE: STATEMSK28 Mask */ +#define SCT_EV14_STATE_STATEMSK29_Pos 29 /*!< SCT EV14_STATE: STATEMSK29 Position */ +#define SCT_EV14_STATE_STATEMSK29_Msk (0x01UL << SCT_EV14_STATE_STATEMSK29_Pos) /*!< SCT EV14_STATE: STATEMSK29 Mask */ +#define SCT_EV14_STATE_STATEMSK30_Pos 30 /*!< SCT EV14_STATE: STATEMSK30 Position */ +#define SCT_EV14_STATE_STATEMSK30_Msk (0x01UL << SCT_EV14_STATE_STATEMSK30_Pos) /*!< SCT EV14_STATE: STATEMSK30 Mask */ +#define SCT_EV14_STATE_STATEMSK31_Pos 31 /*!< SCT EV14_STATE: STATEMSK31 Position */ +#define SCT_EV14_STATE_STATEMSK31_Msk (0x01UL << SCT_EV14_STATE_STATEMSK31_Pos) /*!< SCT EV14_STATE: STATEMSK31 Mask */ + +/* -------------------------------- SCT_EV14_CTRL ------------------------------- */ +#define SCT_EV14_CTRL_MATCHSEL_Pos 0 /*!< SCT EV14_CTRL: MATCHSEL Position */ +#define SCT_EV14_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV14_CTRL_MATCHSEL_Pos) /*!< SCT EV14_CTRL: MATCHSEL Mask */ +#define SCT_EV14_CTRL_HEVENT_Pos 4 /*!< SCT EV14_CTRL: HEVENT Position */ +#define SCT_EV14_CTRL_HEVENT_Msk (0x01UL << SCT_EV14_CTRL_HEVENT_Pos) /*!< SCT EV14_CTRL: HEVENT Mask */ +#define SCT_EV14_CTRL_OUTSEL_Pos 5 /*!< SCT EV14_CTRL: OUTSEL Position */ +#define SCT_EV14_CTRL_OUTSEL_Msk (0x01UL << SCT_EV14_CTRL_OUTSEL_Pos) /*!< SCT EV14_CTRL: OUTSEL Mask */ +#define SCT_EV14_CTRL_IOSEL_Pos 6 /*!< SCT EV14_CTRL: IOSEL Position */ +#define SCT_EV14_CTRL_IOSEL_Msk (0x0fUL << SCT_EV14_CTRL_IOSEL_Pos) /*!< SCT EV14_CTRL: IOSEL Mask */ +#define SCT_EV14_CTRL_IOCOND_Pos 10 /*!< SCT EV14_CTRL: IOCOND Position */ +#define SCT_EV14_CTRL_IOCOND_Msk (0x03UL << SCT_EV14_CTRL_IOCOND_Pos) /*!< SCT EV14_CTRL: IOCOND Mask */ +#define SCT_EV14_CTRL_COMBMODE_Pos 12 /*!< SCT EV14_CTRL: COMBMODE Position */ +#define SCT_EV14_CTRL_COMBMODE_Msk (0x03UL << SCT_EV14_CTRL_COMBMODE_Pos) /*!< SCT EV14_CTRL: COMBMODE Mask */ +#define SCT_EV14_CTRL_STATELD_Pos 14 /*!< SCT EV14_CTRL: STATELD Position */ +#define SCT_EV14_CTRL_STATELD_Msk (0x01UL << SCT_EV14_CTRL_STATELD_Pos) /*!< SCT EV14_CTRL: STATELD Mask */ +#define SCT_EV14_CTRL_STATEV_Pos 15 /*!< SCT EV14_CTRL: STATEV Position */ +#define SCT_EV14_CTRL_STATEV_Msk (0x1fUL << SCT_EV14_CTRL_STATEV_Pos) /*!< SCT EV14_CTRL: STATEV Mask */ +#define SCT_EV14_CTRL_MATCHMEM_Pos 20 /*!< SCT EV14_CTRL: MATCHMEM Position */ +#define SCT_EV14_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV14_CTRL_MATCHMEM_Pos) /*!< SCT EV14_CTRL: MATCHMEM Mask */ +#define SCT_EV14_CTRL_DIRECTION_Pos 21 /*!< SCT EV14_CTRL: DIRECTION Position */ +#define SCT_EV14_CTRL_DIRECTION_Msk (0x03UL << SCT_EV14_CTRL_DIRECTION_Pos) /*!< SCT EV14_CTRL: DIRECTION Mask */ + +/* ------------------------------- SCT_EV15_STATE ------------------------------- */ +#define SCT_EV15_STATE_STATEMSK0_Pos 0 /*!< SCT EV15_STATE: STATEMSK0 Position */ +#define SCT_EV15_STATE_STATEMSK0_Msk (0x01UL << SCT_EV15_STATE_STATEMSK0_Pos) /*!< SCT EV15_STATE: STATEMSK0 Mask */ +#define SCT_EV15_STATE_STATEMSK1_Pos 1 /*!< SCT EV15_STATE: STATEMSK1 Position */ +#define SCT_EV15_STATE_STATEMSK1_Msk (0x01UL << SCT_EV15_STATE_STATEMSK1_Pos) /*!< SCT EV15_STATE: STATEMSK1 Mask */ +#define SCT_EV15_STATE_STATEMSK2_Pos 2 /*!< SCT EV15_STATE: STATEMSK2 Position */ +#define SCT_EV15_STATE_STATEMSK2_Msk (0x01UL << SCT_EV15_STATE_STATEMSK2_Pos) /*!< SCT EV15_STATE: STATEMSK2 Mask */ +#define SCT_EV15_STATE_STATEMSK3_Pos 3 /*!< SCT EV15_STATE: STATEMSK3 Position */ +#define SCT_EV15_STATE_STATEMSK3_Msk (0x01UL << SCT_EV15_STATE_STATEMSK3_Pos) /*!< SCT EV15_STATE: STATEMSK3 Mask */ +#define SCT_EV15_STATE_STATEMSK4_Pos 4 /*!< SCT EV15_STATE: STATEMSK4 Position */ +#define SCT_EV15_STATE_STATEMSK4_Msk (0x01UL << SCT_EV15_STATE_STATEMSK4_Pos) /*!< SCT EV15_STATE: STATEMSK4 Mask */ +#define SCT_EV15_STATE_STATEMSK5_Pos 5 /*!< SCT EV15_STATE: STATEMSK5 Position */ +#define SCT_EV15_STATE_STATEMSK5_Msk (0x01UL << SCT_EV15_STATE_STATEMSK5_Pos) /*!< SCT EV15_STATE: STATEMSK5 Mask */ +#define SCT_EV15_STATE_STATEMSK6_Pos 6 /*!< SCT EV15_STATE: STATEMSK6 Position */ +#define SCT_EV15_STATE_STATEMSK6_Msk (0x01UL << SCT_EV15_STATE_STATEMSK6_Pos) /*!< SCT EV15_STATE: STATEMSK6 Mask */ +#define SCT_EV15_STATE_STATEMSK7_Pos 7 /*!< SCT EV15_STATE: STATEMSK7 Position */ +#define SCT_EV15_STATE_STATEMSK7_Msk (0x01UL << SCT_EV15_STATE_STATEMSK7_Pos) /*!< SCT EV15_STATE: STATEMSK7 Mask */ +#define SCT_EV15_STATE_STATEMSK8_Pos 8 /*!< SCT EV15_STATE: STATEMSK8 Position */ +#define SCT_EV15_STATE_STATEMSK8_Msk (0x01UL << SCT_EV15_STATE_STATEMSK8_Pos) /*!< SCT EV15_STATE: STATEMSK8 Mask */ +#define SCT_EV15_STATE_STATEMSK9_Pos 9 /*!< SCT EV15_STATE: STATEMSK9 Position */ +#define SCT_EV15_STATE_STATEMSK9_Msk (0x01UL << SCT_EV15_STATE_STATEMSK9_Pos) /*!< SCT EV15_STATE: STATEMSK9 Mask */ +#define SCT_EV15_STATE_STATEMSK10_Pos 10 /*!< SCT EV15_STATE: STATEMSK10 Position */ +#define SCT_EV15_STATE_STATEMSK10_Msk (0x01UL << SCT_EV15_STATE_STATEMSK10_Pos) /*!< SCT EV15_STATE: STATEMSK10 Mask */ +#define SCT_EV15_STATE_STATEMSK11_Pos 11 /*!< SCT EV15_STATE: STATEMSK11 Position */ +#define SCT_EV15_STATE_STATEMSK11_Msk (0x01UL << SCT_EV15_STATE_STATEMSK11_Pos) /*!< SCT EV15_STATE: STATEMSK11 Mask */ +#define SCT_EV15_STATE_STATEMSK12_Pos 12 /*!< SCT EV15_STATE: STATEMSK12 Position */ +#define SCT_EV15_STATE_STATEMSK12_Msk (0x01UL << SCT_EV15_STATE_STATEMSK12_Pos) /*!< SCT EV15_STATE: STATEMSK12 Mask */ +#define SCT_EV15_STATE_STATEMSK13_Pos 13 /*!< SCT EV15_STATE: STATEMSK13 Position */ +#define SCT_EV15_STATE_STATEMSK13_Msk (0x01UL << SCT_EV15_STATE_STATEMSK13_Pos) /*!< SCT EV15_STATE: STATEMSK13 Mask */ +#define SCT_EV15_STATE_STATEMSK14_Pos 14 /*!< SCT EV15_STATE: STATEMSK14 Position */ +#define SCT_EV15_STATE_STATEMSK14_Msk (0x01UL << SCT_EV15_STATE_STATEMSK14_Pos) /*!< SCT EV15_STATE: STATEMSK14 Mask */ +#define SCT_EV15_STATE_STATEMSK15_Pos 15 /*!< SCT EV15_STATE: STATEMSK15 Position */ +#define SCT_EV15_STATE_STATEMSK15_Msk (0x01UL << SCT_EV15_STATE_STATEMSK15_Pos) /*!< SCT EV15_STATE: STATEMSK15 Mask */ +#define SCT_EV15_STATE_STATEMSK16_Pos 16 /*!< SCT EV15_STATE: STATEMSK16 Position */ +#define SCT_EV15_STATE_STATEMSK16_Msk (0x01UL << SCT_EV15_STATE_STATEMSK16_Pos) /*!< SCT EV15_STATE: STATEMSK16 Mask */ +#define SCT_EV15_STATE_STATEMSK17_Pos 17 /*!< SCT EV15_STATE: STATEMSK17 Position */ +#define SCT_EV15_STATE_STATEMSK17_Msk (0x01UL << SCT_EV15_STATE_STATEMSK17_Pos) /*!< SCT EV15_STATE: STATEMSK17 Mask */ +#define SCT_EV15_STATE_STATEMSK18_Pos 18 /*!< SCT EV15_STATE: STATEMSK18 Position */ +#define SCT_EV15_STATE_STATEMSK18_Msk (0x01UL << SCT_EV15_STATE_STATEMSK18_Pos) /*!< SCT EV15_STATE: STATEMSK18 Mask */ +#define SCT_EV15_STATE_STATEMSK19_Pos 19 /*!< SCT EV15_STATE: STATEMSK19 Position */ +#define SCT_EV15_STATE_STATEMSK19_Msk (0x01UL << SCT_EV15_STATE_STATEMSK19_Pos) /*!< SCT EV15_STATE: STATEMSK19 Mask */ +#define SCT_EV15_STATE_STATEMSK20_Pos 20 /*!< SCT EV15_STATE: STATEMSK20 Position */ +#define SCT_EV15_STATE_STATEMSK20_Msk (0x01UL << SCT_EV15_STATE_STATEMSK20_Pos) /*!< SCT EV15_STATE: STATEMSK20 Mask */ +#define SCT_EV15_STATE_STATEMSK21_Pos 21 /*!< SCT EV15_STATE: STATEMSK21 Position */ +#define SCT_EV15_STATE_STATEMSK21_Msk (0x01UL << SCT_EV15_STATE_STATEMSK21_Pos) /*!< SCT EV15_STATE: STATEMSK21 Mask */ +#define SCT_EV15_STATE_STATEMSK22_Pos 22 /*!< SCT EV15_STATE: STATEMSK22 Position */ +#define SCT_EV15_STATE_STATEMSK22_Msk (0x01UL << SCT_EV15_STATE_STATEMSK22_Pos) /*!< SCT EV15_STATE: STATEMSK22 Mask */ +#define SCT_EV15_STATE_STATEMSK23_Pos 23 /*!< SCT EV15_STATE: STATEMSK23 Position */ +#define SCT_EV15_STATE_STATEMSK23_Msk (0x01UL << SCT_EV15_STATE_STATEMSK23_Pos) /*!< SCT EV15_STATE: STATEMSK23 Mask */ +#define SCT_EV15_STATE_STATEMSK24_Pos 24 /*!< SCT EV15_STATE: STATEMSK24 Position */ +#define SCT_EV15_STATE_STATEMSK24_Msk (0x01UL << SCT_EV15_STATE_STATEMSK24_Pos) /*!< SCT EV15_STATE: STATEMSK24 Mask */ +#define SCT_EV15_STATE_STATEMSK25_Pos 25 /*!< SCT EV15_STATE: STATEMSK25 Position */ +#define SCT_EV15_STATE_STATEMSK25_Msk (0x01UL << SCT_EV15_STATE_STATEMSK25_Pos) /*!< SCT EV15_STATE: STATEMSK25 Mask */ +#define SCT_EV15_STATE_STATEMSK26_Pos 26 /*!< SCT EV15_STATE: STATEMSK26 Position */ +#define SCT_EV15_STATE_STATEMSK26_Msk (0x01UL << SCT_EV15_STATE_STATEMSK26_Pos) /*!< SCT EV15_STATE: STATEMSK26 Mask */ +#define SCT_EV15_STATE_STATEMSK27_Pos 27 /*!< SCT EV15_STATE: STATEMSK27 Position */ +#define SCT_EV15_STATE_STATEMSK27_Msk (0x01UL << SCT_EV15_STATE_STATEMSK27_Pos) /*!< SCT EV15_STATE: STATEMSK27 Mask */ +#define SCT_EV15_STATE_STATEMSK28_Pos 28 /*!< SCT EV15_STATE: STATEMSK28 Position */ +#define SCT_EV15_STATE_STATEMSK28_Msk (0x01UL << SCT_EV15_STATE_STATEMSK28_Pos) /*!< SCT EV15_STATE: STATEMSK28 Mask */ +#define SCT_EV15_STATE_STATEMSK29_Pos 29 /*!< SCT EV15_STATE: STATEMSK29 Position */ +#define SCT_EV15_STATE_STATEMSK29_Msk (0x01UL << SCT_EV15_STATE_STATEMSK29_Pos) /*!< SCT EV15_STATE: STATEMSK29 Mask */ +#define SCT_EV15_STATE_STATEMSK30_Pos 30 /*!< SCT EV15_STATE: STATEMSK30 Position */ +#define SCT_EV15_STATE_STATEMSK30_Msk (0x01UL << SCT_EV15_STATE_STATEMSK30_Pos) /*!< SCT EV15_STATE: STATEMSK30 Mask */ +#define SCT_EV15_STATE_STATEMSK31_Pos 31 /*!< SCT EV15_STATE: STATEMSK31 Position */ +#define SCT_EV15_STATE_STATEMSK31_Msk (0x01UL << SCT_EV15_STATE_STATEMSK31_Pos) /*!< SCT EV15_STATE: STATEMSK31 Mask */ + +/* -------------------------------- SCT_EV15_CTRL ------------------------------- */ +#define SCT_EV15_CTRL_MATCHSEL_Pos 0 /*!< SCT EV15_CTRL: MATCHSEL Position */ +#define SCT_EV15_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV15_CTRL_MATCHSEL_Pos) /*!< SCT EV15_CTRL: MATCHSEL Mask */ +#define SCT_EV15_CTRL_HEVENT_Pos 4 /*!< SCT EV15_CTRL: HEVENT Position */ +#define SCT_EV15_CTRL_HEVENT_Msk (0x01UL << SCT_EV15_CTRL_HEVENT_Pos) /*!< SCT EV15_CTRL: HEVENT Mask */ +#define SCT_EV15_CTRL_OUTSEL_Pos 5 /*!< SCT EV15_CTRL: OUTSEL Position */ +#define SCT_EV15_CTRL_OUTSEL_Msk (0x01UL << SCT_EV15_CTRL_OUTSEL_Pos) /*!< SCT EV15_CTRL: OUTSEL Mask */ +#define SCT_EV15_CTRL_IOSEL_Pos 6 /*!< SCT EV15_CTRL: IOSEL Position */ +#define SCT_EV15_CTRL_IOSEL_Msk (0x0fUL << SCT_EV15_CTRL_IOSEL_Pos) /*!< SCT EV15_CTRL: IOSEL Mask */ +#define SCT_EV15_CTRL_IOCOND_Pos 10 /*!< SCT EV15_CTRL: IOCOND Position */ +#define SCT_EV15_CTRL_IOCOND_Msk (0x03UL << SCT_EV15_CTRL_IOCOND_Pos) /*!< SCT EV15_CTRL: IOCOND Mask */ +#define SCT_EV15_CTRL_COMBMODE_Pos 12 /*!< SCT EV15_CTRL: COMBMODE Position */ +#define SCT_EV15_CTRL_COMBMODE_Msk (0x03UL << SCT_EV15_CTRL_COMBMODE_Pos) /*!< SCT EV15_CTRL: COMBMODE Mask */ +#define SCT_EV15_CTRL_STATELD_Pos 14 /*!< SCT EV15_CTRL: STATELD Position */ +#define SCT_EV15_CTRL_STATELD_Msk (0x01UL << SCT_EV15_CTRL_STATELD_Pos) /*!< SCT EV15_CTRL: STATELD Mask */ +#define SCT_EV15_CTRL_STATEV_Pos 15 /*!< SCT EV15_CTRL: STATEV Position */ +#define SCT_EV15_CTRL_STATEV_Msk (0x1fUL << SCT_EV15_CTRL_STATEV_Pos) /*!< SCT EV15_CTRL: STATEV Mask */ +#define SCT_EV15_CTRL_MATCHMEM_Pos 20 /*!< SCT EV15_CTRL: MATCHMEM Position */ +#define SCT_EV15_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV15_CTRL_MATCHMEM_Pos) /*!< SCT EV15_CTRL: MATCHMEM Mask */ +#define SCT_EV15_CTRL_DIRECTION_Pos 21 /*!< SCT EV15_CTRL: DIRECTION Position */ +#define SCT_EV15_CTRL_DIRECTION_Msk (0x03UL << SCT_EV15_CTRL_DIRECTION_Pos) /*!< SCT EV15_CTRL: DIRECTION Mask */ + +/* -------------------------------- SCT_OUT0_SET -------------------------------- */ +#define SCT_OUT0_SET_SET0_Pos 0 /*!< SCT OUT0_SET: SET0 Position */ +#define SCT_OUT0_SET_SET0_Msk (0x01UL << SCT_OUT0_SET_SET0_Pos) /*!< SCT OUT0_SET: SET0 Mask */ +#define SCT_OUT0_SET_SET1_Pos 1 /*!< SCT OUT0_SET: SET1 Position */ +#define SCT_OUT0_SET_SET1_Msk (0x01UL << SCT_OUT0_SET_SET1_Pos) /*!< SCT OUT0_SET: SET1 Mask */ +#define SCT_OUT0_SET_SET2_Pos 2 /*!< SCT OUT0_SET: SET2 Position */ +#define SCT_OUT0_SET_SET2_Msk (0x01UL << SCT_OUT0_SET_SET2_Pos) /*!< SCT OUT0_SET: SET2 Mask */ +#define SCT_OUT0_SET_SET3_Pos 3 /*!< SCT OUT0_SET: SET3 Position */ +#define SCT_OUT0_SET_SET3_Msk (0x01UL << SCT_OUT0_SET_SET3_Pos) /*!< SCT OUT0_SET: SET3 Mask */ +#define SCT_OUT0_SET_SET4_Pos 4 /*!< SCT OUT0_SET: SET4 Position */ +#define SCT_OUT0_SET_SET4_Msk (0x01UL << SCT_OUT0_SET_SET4_Pos) /*!< SCT OUT0_SET: SET4 Mask */ +#define SCT_OUT0_SET_SET5_Pos 5 /*!< SCT OUT0_SET: SET5 Position */ +#define SCT_OUT0_SET_SET5_Msk (0x01UL << SCT_OUT0_SET_SET5_Pos) /*!< SCT OUT0_SET: SET5 Mask */ +#define SCT_OUT0_SET_SET6_Pos 6 /*!< SCT OUT0_SET: SET6 Position */ +#define SCT_OUT0_SET_SET6_Msk (0x01UL << SCT_OUT0_SET_SET6_Pos) /*!< SCT OUT0_SET: SET6 Mask */ +#define SCT_OUT0_SET_SET7_Pos 7 /*!< SCT OUT0_SET: SET7 Position */ +#define SCT_OUT0_SET_SET7_Msk (0x01UL << SCT_OUT0_SET_SET7_Pos) /*!< SCT OUT0_SET: SET7 Mask */ +#define SCT_OUT0_SET_SET8_Pos 8 /*!< SCT OUT0_SET: SET8 Position */ +#define SCT_OUT0_SET_SET8_Msk (0x01UL << SCT_OUT0_SET_SET8_Pos) /*!< SCT OUT0_SET: SET8 Mask */ +#define SCT_OUT0_SET_SET9_Pos 9 /*!< SCT OUT0_SET: SET9 Position */ +#define SCT_OUT0_SET_SET9_Msk (0x01UL << SCT_OUT0_SET_SET9_Pos) /*!< SCT OUT0_SET: SET9 Mask */ +#define SCT_OUT0_SET_SET10_Pos 10 /*!< SCT OUT0_SET: SET10 Position */ +#define SCT_OUT0_SET_SET10_Msk (0x01UL << SCT_OUT0_SET_SET10_Pos) /*!< SCT OUT0_SET: SET10 Mask */ +#define SCT_OUT0_SET_SET11_Pos 11 /*!< SCT OUT0_SET: SET11 Position */ +#define SCT_OUT0_SET_SET11_Msk (0x01UL << SCT_OUT0_SET_SET11_Pos) /*!< SCT OUT0_SET: SET11 Mask */ +#define SCT_OUT0_SET_SET12_Pos 12 /*!< SCT OUT0_SET: SET12 Position */ +#define SCT_OUT0_SET_SET12_Msk (0x01UL << SCT_OUT0_SET_SET12_Pos) /*!< SCT OUT0_SET: SET12 Mask */ +#define SCT_OUT0_SET_SET13_Pos 13 /*!< SCT OUT0_SET: SET13 Position */ +#define SCT_OUT0_SET_SET13_Msk (0x01UL << SCT_OUT0_SET_SET13_Pos) /*!< SCT OUT0_SET: SET13 Mask */ +#define SCT_OUT0_SET_SET14_Pos 14 /*!< SCT OUT0_SET: SET14 Position */ +#define SCT_OUT0_SET_SET14_Msk (0x01UL << SCT_OUT0_SET_SET14_Pos) /*!< SCT OUT0_SET: SET14 Mask */ +#define SCT_OUT0_SET_SET15_Pos 15 /*!< SCT OUT0_SET: SET15 Position */ +#define SCT_OUT0_SET_SET15_Msk (0x01UL << SCT_OUT0_SET_SET15_Pos) /*!< SCT OUT0_SET: SET15 Mask */ + +/* -------------------------------- SCT_OUT0_CLR -------------------------------- */ +#define SCT_OUT0_CLR_CLR0_Pos 0 /*!< SCT OUT0_CLR: CLR0 Position */ +#define SCT_OUT0_CLR_CLR0_Msk (0x01UL << SCT_OUT0_CLR_CLR0_Pos) /*!< SCT OUT0_CLR: CLR0 Mask */ +#define SCT_OUT0_CLR_CLR1_Pos 1 /*!< SCT OUT0_CLR: CLR1 Position */ +#define SCT_OUT0_CLR_CLR1_Msk (0x01UL << SCT_OUT0_CLR_CLR1_Pos) /*!< SCT OUT0_CLR: CLR1 Mask */ +#define SCT_OUT0_CLR_CLR2_Pos 2 /*!< SCT OUT0_CLR: CLR2 Position */ +#define SCT_OUT0_CLR_CLR2_Msk (0x01UL << SCT_OUT0_CLR_CLR2_Pos) /*!< SCT OUT0_CLR: CLR2 Mask */ +#define SCT_OUT0_CLR_CLR3_Pos 3 /*!< SCT OUT0_CLR: CLR3 Position */ +#define SCT_OUT0_CLR_CLR3_Msk (0x01UL << SCT_OUT0_CLR_CLR3_Pos) /*!< SCT OUT0_CLR: CLR3 Mask */ +#define SCT_OUT0_CLR_CLR4_Pos 4 /*!< SCT OUT0_CLR: CLR4 Position */ +#define SCT_OUT0_CLR_CLR4_Msk (0x01UL << SCT_OUT0_CLR_CLR4_Pos) /*!< SCT OUT0_CLR: CLR4 Mask */ +#define SCT_OUT0_CLR_CLR5_Pos 5 /*!< SCT OUT0_CLR: CLR5 Position */ +#define SCT_OUT0_CLR_CLR5_Msk (0x01UL << SCT_OUT0_CLR_CLR5_Pos) /*!< SCT OUT0_CLR: CLR5 Mask */ +#define SCT_OUT0_CLR_CLR6_Pos 6 /*!< SCT OUT0_CLR: CLR6 Position */ +#define SCT_OUT0_CLR_CLR6_Msk (0x01UL << SCT_OUT0_CLR_CLR6_Pos) /*!< SCT OUT0_CLR: CLR6 Mask */ +#define SCT_OUT0_CLR_CLR7_Pos 7 /*!< SCT OUT0_CLR: CLR7 Position */ +#define SCT_OUT0_CLR_CLR7_Msk (0x01UL << SCT_OUT0_CLR_CLR7_Pos) /*!< SCT OUT0_CLR: CLR7 Mask */ +#define SCT_OUT0_CLR_CLR8_Pos 8 /*!< SCT OUT0_CLR: CLR8 Position */ +#define SCT_OUT0_CLR_CLR8_Msk (0x01UL << SCT_OUT0_CLR_CLR8_Pos) /*!< SCT OUT0_CLR: CLR8 Mask */ +#define SCT_OUT0_CLR_CLR9_Pos 9 /*!< SCT OUT0_CLR: CLR9 Position */ +#define SCT_OUT0_CLR_CLR9_Msk (0x01UL << SCT_OUT0_CLR_CLR9_Pos) /*!< SCT OUT0_CLR: CLR9 Mask */ +#define SCT_OUT0_CLR_CLR10_Pos 10 /*!< SCT OUT0_CLR: CLR10 Position */ +#define SCT_OUT0_CLR_CLR10_Msk (0x01UL << SCT_OUT0_CLR_CLR10_Pos) /*!< SCT OUT0_CLR: CLR10 Mask */ +#define SCT_OUT0_CLR_CLR11_Pos 11 /*!< SCT OUT0_CLR: CLR11 Position */ +#define SCT_OUT0_CLR_CLR11_Msk (0x01UL << SCT_OUT0_CLR_CLR11_Pos) /*!< SCT OUT0_CLR: CLR11 Mask */ +#define SCT_OUT0_CLR_CLR12_Pos 12 /*!< SCT OUT0_CLR: CLR12 Position */ +#define SCT_OUT0_CLR_CLR12_Msk (0x01UL << SCT_OUT0_CLR_CLR12_Pos) /*!< SCT OUT0_CLR: CLR12 Mask */ +#define SCT_OUT0_CLR_CLR13_Pos 13 /*!< SCT OUT0_CLR: CLR13 Position */ +#define SCT_OUT0_CLR_CLR13_Msk (0x01UL << SCT_OUT0_CLR_CLR13_Pos) /*!< SCT OUT0_CLR: CLR13 Mask */ +#define SCT_OUT0_CLR_CLR14_Pos 14 /*!< SCT OUT0_CLR: CLR14 Position */ +#define SCT_OUT0_CLR_CLR14_Msk (0x01UL << SCT_OUT0_CLR_CLR14_Pos) /*!< SCT OUT0_CLR: CLR14 Mask */ +#define SCT_OUT0_CLR_CLR15_Pos 15 /*!< SCT OUT0_CLR: CLR15 Position */ +#define SCT_OUT0_CLR_CLR15_Msk (0x01UL << SCT_OUT0_CLR_CLR15_Pos) /*!< SCT OUT0_CLR: CLR15 Mask */ + +/* -------------------------------- SCT_OUT1_SET -------------------------------- */ +#define SCT_OUT1_SET_SET0_Pos 0 /*!< SCT OUT1_SET: SET0 Position */ +#define SCT_OUT1_SET_SET0_Msk (0x01UL << SCT_OUT1_SET_SET0_Pos) /*!< SCT OUT1_SET: SET0 Mask */ +#define SCT_OUT1_SET_SET1_Pos 1 /*!< SCT OUT1_SET: SET1 Position */ +#define SCT_OUT1_SET_SET1_Msk (0x01UL << SCT_OUT1_SET_SET1_Pos) /*!< SCT OUT1_SET: SET1 Mask */ +#define SCT_OUT1_SET_SET2_Pos 2 /*!< SCT OUT1_SET: SET2 Position */ +#define SCT_OUT1_SET_SET2_Msk (0x01UL << SCT_OUT1_SET_SET2_Pos) /*!< SCT OUT1_SET: SET2 Mask */ +#define SCT_OUT1_SET_SET3_Pos 3 /*!< SCT OUT1_SET: SET3 Position */ +#define SCT_OUT1_SET_SET3_Msk (0x01UL << SCT_OUT1_SET_SET3_Pos) /*!< SCT OUT1_SET: SET3 Mask */ +#define SCT_OUT1_SET_SET4_Pos 4 /*!< SCT OUT1_SET: SET4 Position */ +#define SCT_OUT1_SET_SET4_Msk (0x01UL << SCT_OUT1_SET_SET4_Pos) /*!< SCT OUT1_SET: SET4 Mask */ +#define SCT_OUT1_SET_SET5_Pos 5 /*!< SCT OUT1_SET: SET5 Position */ +#define SCT_OUT1_SET_SET5_Msk (0x01UL << SCT_OUT1_SET_SET5_Pos) /*!< SCT OUT1_SET: SET5 Mask */ +#define SCT_OUT1_SET_SET6_Pos 6 /*!< SCT OUT1_SET: SET6 Position */ +#define SCT_OUT1_SET_SET6_Msk (0x01UL << SCT_OUT1_SET_SET6_Pos) /*!< SCT OUT1_SET: SET6 Mask */ +#define SCT_OUT1_SET_SET7_Pos 7 /*!< SCT OUT1_SET: SET7 Position */ +#define SCT_OUT1_SET_SET7_Msk (0x01UL << SCT_OUT1_SET_SET7_Pos) /*!< SCT OUT1_SET: SET7 Mask */ +#define SCT_OUT1_SET_SET8_Pos 8 /*!< SCT OUT1_SET: SET8 Position */ +#define SCT_OUT1_SET_SET8_Msk (0x01UL << SCT_OUT1_SET_SET8_Pos) /*!< SCT OUT1_SET: SET8 Mask */ +#define SCT_OUT1_SET_SET9_Pos 9 /*!< SCT OUT1_SET: SET9 Position */ +#define SCT_OUT1_SET_SET9_Msk (0x01UL << SCT_OUT1_SET_SET9_Pos) /*!< SCT OUT1_SET: SET9 Mask */ +#define SCT_OUT1_SET_SET10_Pos 10 /*!< SCT OUT1_SET: SET10 Position */ +#define SCT_OUT1_SET_SET10_Msk (0x01UL << SCT_OUT1_SET_SET10_Pos) /*!< SCT OUT1_SET: SET10 Mask */ +#define SCT_OUT1_SET_SET11_Pos 11 /*!< SCT OUT1_SET: SET11 Position */ +#define SCT_OUT1_SET_SET11_Msk (0x01UL << SCT_OUT1_SET_SET11_Pos) /*!< SCT OUT1_SET: SET11 Mask */ +#define SCT_OUT1_SET_SET12_Pos 12 /*!< SCT OUT1_SET: SET12 Position */ +#define SCT_OUT1_SET_SET12_Msk (0x01UL << SCT_OUT1_SET_SET12_Pos) /*!< SCT OUT1_SET: SET12 Mask */ +#define SCT_OUT1_SET_SET13_Pos 13 /*!< SCT OUT1_SET: SET13 Position */ +#define SCT_OUT1_SET_SET13_Msk (0x01UL << SCT_OUT1_SET_SET13_Pos) /*!< SCT OUT1_SET: SET13 Mask */ +#define SCT_OUT1_SET_SET14_Pos 14 /*!< SCT OUT1_SET: SET14 Position */ +#define SCT_OUT1_SET_SET14_Msk (0x01UL << SCT_OUT1_SET_SET14_Pos) /*!< SCT OUT1_SET: SET14 Mask */ +#define SCT_OUT1_SET_SET15_Pos 15 /*!< SCT OUT1_SET: SET15 Position */ +#define SCT_OUT1_SET_SET15_Msk (0x01UL << SCT_OUT1_SET_SET15_Pos) /*!< SCT OUT1_SET: SET15 Mask */ + +/* -------------------------------- SCT_OUT1_CLR -------------------------------- */ +#define SCT_OUT1_CLR_CLR0_Pos 0 /*!< SCT OUT1_CLR: CLR0 Position */ +#define SCT_OUT1_CLR_CLR0_Msk (0x01UL << SCT_OUT1_CLR_CLR0_Pos) /*!< SCT OUT1_CLR: CLR0 Mask */ +#define SCT_OUT1_CLR_CLR1_Pos 1 /*!< SCT OUT1_CLR: CLR1 Position */ +#define SCT_OUT1_CLR_CLR1_Msk (0x01UL << SCT_OUT1_CLR_CLR1_Pos) /*!< SCT OUT1_CLR: CLR1 Mask */ +#define SCT_OUT1_CLR_CLR2_Pos 2 /*!< SCT OUT1_CLR: CLR2 Position */ +#define SCT_OUT1_CLR_CLR2_Msk (0x01UL << SCT_OUT1_CLR_CLR2_Pos) /*!< SCT OUT1_CLR: CLR2 Mask */ +#define SCT_OUT1_CLR_CLR3_Pos 3 /*!< SCT OUT1_CLR: CLR3 Position */ +#define SCT_OUT1_CLR_CLR3_Msk (0x01UL << SCT_OUT1_CLR_CLR3_Pos) /*!< SCT OUT1_CLR: CLR3 Mask */ +#define SCT_OUT1_CLR_CLR4_Pos 4 /*!< SCT OUT1_CLR: CLR4 Position */ +#define SCT_OUT1_CLR_CLR4_Msk (0x01UL << SCT_OUT1_CLR_CLR4_Pos) /*!< SCT OUT1_CLR: CLR4 Mask */ +#define SCT_OUT1_CLR_CLR5_Pos 5 /*!< SCT OUT1_CLR: CLR5 Position */ +#define SCT_OUT1_CLR_CLR5_Msk (0x01UL << SCT_OUT1_CLR_CLR5_Pos) /*!< SCT OUT1_CLR: CLR5 Mask */ +#define SCT_OUT1_CLR_CLR6_Pos 6 /*!< SCT OUT1_CLR: CLR6 Position */ +#define SCT_OUT1_CLR_CLR6_Msk (0x01UL << SCT_OUT1_CLR_CLR6_Pos) /*!< SCT OUT1_CLR: CLR6 Mask */ +#define SCT_OUT1_CLR_CLR7_Pos 7 /*!< SCT OUT1_CLR: CLR7 Position */ +#define SCT_OUT1_CLR_CLR7_Msk (0x01UL << SCT_OUT1_CLR_CLR7_Pos) /*!< SCT OUT1_CLR: CLR7 Mask */ +#define SCT_OUT1_CLR_CLR8_Pos 8 /*!< SCT OUT1_CLR: CLR8 Position */ +#define SCT_OUT1_CLR_CLR8_Msk (0x01UL << SCT_OUT1_CLR_CLR8_Pos) /*!< SCT OUT1_CLR: CLR8 Mask */ +#define SCT_OUT1_CLR_CLR9_Pos 9 /*!< SCT OUT1_CLR: CLR9 Position */ +#define SCT_OUT1_CLR_CLR9_Msk (0x01UL << SCT_OUT1_CLR_CLR9_Pos) /*!< SCT OUT1_CLR: CLR9 Mask */ +#define SCT_OUT1_CLR_CLR10_Pos 10 /*!< SCT OUT1_CLR: CLR10 Position */ +#define SCT_OUT1_CLR_CLR10_Msk (0x01UL << SCT_OUT1_CLR_CLR10_Pos) /*!< SCT OUT1_CLR: CLR10 Mask */ +#define SCT_OUT1_CLR_CLR11_Pos 11 /*!< SCT OUT1_CLR: CLR11 Position */ +#define SCT_OUT1_CLR_CLR11_Msk (0x01UL << SCT_OUT1_CLR_CLR11_Pos) /*!< SCT OUT1_CLR: CLR11 Mask */ +#define SCT_OUT1_CLR_CLR12_Pos 12 /*!< SCT OUT1_CLR: CLR12 Position */ +#define SCT_OUT1_CLR_CLR12_Msk (0x01UL << SCT_OUT1_CLR_CLR12_Pos) /*!< SCT OUT1_CLR: CLR12 Mask */ +#define SCT_OUT1_CLR_CLR13_Pos 13 /*!< SCT OUT1_CLR: CLR13 Position */ +#define SCT_OUT1_CLR_CLR13_Msk (0x01UL << SCT_OUT1_CLR_CLR13_Pos) /*!< SCT OUT1_CLR: CLR13 Mask */ +#define SCT_OUT1_CLR_CLR14_Pos 14 /*!< SCT OUT1_CLR: CLR14 Position */ +#define SCT_OUT1_CLR_CLR14_Msk (0x01UL << SCT_OUT1_CLR_CLR14_Pos) /*!< SCT OUT1_CLR: CLR14 Mask */ +#define SCT_OUT1_CLR_CLR15_Pos 15 /*!< SCT OUT1_CLR: CLR15 Position */ +#define SCT_OUT1_CLR_CLR15_Msk (0x01UL << SCT_OUT1_CLR_CLR15_Pos) /*!< SCT OUT1_CLR: CLR15 Mask */ + +/* -------------------------------- SCT_OUT2_SET -------------------------------- */ +#define SCT_OUT2_SET_SET0_Pos 0 /*!< SCT OUT2_SET: SET0 Position */ +#define SCT_OUT2_SET_SET0_Msk (0x01UL << SCT_OUT2_SET_SET0_Pos) /*!< SCT OUT2_SET: SET0 Mask */ +#define SCT_OUT2_SET_SET1_Pos 1 /*!< SCT OUT2_SET: SET1 Position */ +#define SCT_OUT2_SET_SET1_Msk (0x01UL << SCT_OUT2_SET_SET1_Pos) /*!< SCT OUT2_SET: SET1 Mask */ +#define SCT_OUT2_SET_SET2_Pos 2 /*!< SCT OUT2_SET: SET2 Position */ +#define SCT_OUT2_SET_SET2_Msk (0x01UL << SCT_OUT2_SET_SET2_Pos) /*!< SCT OUT2_SET: SET2 Mask */ +#define SCT_OUT2_SET_SET3_Pos 3 /*!< SCT OUT2_SET: SET3 Position */ +#define SCT_OUT2_SET_SET3_Msk (0x01UL << SCT_OUT2_SET_SET3_Pos) /*!< SCT OUT2_SET: SET3 Mask */ +#define SCT_OUT2_SET_SET4_Pos 4 /*!< SCT OUT2_SET: SET4 Position */ +#define SCT_OUT2_SET_SET4_Msk (0x01UL << SCT_OUT2_SET_SET4_Pos) /*!< SCT OUT2_SET: SET4 Mask */ +#define SCT_OUT2_SET_SET5_Pos 5 /*!< SCT OUT2_SET: SET5 Position */ +#define SCT_OUT2_SET_SET5_Msk (0x01UL << SCT_OUT2_SET_SET5_Pos) /*!< SCT OUT2_SET: SET5 Mask */ +#define SCT_OUT2_SET_SET6_Pos 6 /*!< SCT OUT2_SET: SET6 Position */ +#define SCT_OUT2_SET_SET6_Msk (0x01UL << SCT_OUT2_SET_SET6_Pos) /*!< SCT OUT2_SET: SET6 Mask */ +#define SCT_OUT2_SET_SET7_Pos 7 /*!< SCT OUT2_SET: SET7 Position */ +#define SCT_OUT2_SET_SET7_Msk (0x01UL << SCT_OUT2_SET_SET7_Pos) /*!< SCT OUT2_SET: SET7 Mask */ +#define SCT_OUT2_SET_SET8_Pos 8 /*!< SCT OUT2_SET: SET8 Position */ +#define SCT_OUT2_SET_SET8_Msk (0x01UL << SCT_OUT2_SET_SET8_Pos) /*!< SCT OUT2_SET: SET8 Mask */ +#define SCT_OUT2_SET_SET9_Pos 9 /*!< SCT OUT2_SET: SET9 Position */ +#define SCT_OUT2_SET_SET9_Msk (0x01UL << SCT_OUT2_SET_SET9_Pos) /*!< SCT OUT2_SET: SET9 Mask */ +#define SCT_OUT2_SET_SET10_Pos 10 /*!< SCT OUT2_SET: SET10 Position */ +#define SCT_OUT2_SET_SET10_Msk (0x01UL << SCT_OUT2_SET_SET10_Pos) /*!< SCT OUT2_SET: SET10 Mask */ +#define SCT_OUT2_SET_SET11_Pos 11 /*!< SCT OUT2_SET: SET11 Position */ +#define SCT_OUT2_SET_SET11_Msk (0x01UL << SCT_OUT2_SET_SET11_Pos) /*!< SCT OUT2_SET: SET11 Mask */ +#define SCT_OUT2_SET_SET12_Pos 12 /*!< SCT OUT2_SET: SET12 Position */ +#define SCT_OUT2_SET_SET12_Msk (0x01UL << SCT_OUT2_SET_SET12_Pos) /*!< SCT OUT2_SET: SET12 Mask */ +#define SCT_OUT2_SET_SET13_Pos 13 /*!< SCT OUT2_SET: SET13 Position */ +#define SCT_OUT2_SET_SET13_Msk (0x01UL << SCT_OUT2_SET_SET13_Pos) /*!< SCT OUT2_SET: SET13 Mask */ +#define SCT_OUT2_SET_SET14_Pos 14 /*!< SCT OUT2_SET: SET14 Position */ +#define SCT_OUT2_SET_SET14_Msk (0x01UL << SCT_OUT2_SET_SET14_Pos) /*!< SCT OUT2_SET: SET14 Mask */ +#define SCT_OUT2_SET_SET15_Pos 15 /*!< SCT OUT2_SET: SET15 Position */ +#define SCT_OUT2_SET_SET15_Msk (0x01UL << SCT_OUT2_SET_SET15_Pos) /*!< SCT OUT2_SET: SET15 Mask */ + +/* -------------------------------- SCT_OUT2_CLR -------------------------------- */ +#define SCT_OUT2_CLR_CLR0_Pos 0 /*!< SCT OUT2_CLR: CLR0 Position */ +#define SCT_OUT2_CLR_CLR0_Msk (0x01UL << SCT_OUT2_CLR_CLR0_Pos) /*!< SCT OUT2_CLR: CLR0 Mask */ +#define SCT_OUT2_CLR_CLR1_Pos 1 /*!< SCT OUT2_CLR: CLR1 Position */ +#define SCT_OUT2_CLR_CLR1_Msk (0x01UL << SCT_OUT2_CLR_CLR1_Pos) /*!< SCT OUT2_CLR: CLR1 Mask */ +#define SCT_OUT2_CLR_CLR2_Pos 2 /*!< SCT OUT2_CLR: CLR2 Position */ +#define SCT_OUT2_CLR_CLR2_Msk (0x01UL << SCT_OUT2_CLR_CLR2_Pos) /*!< SCT OUT2_CLR: CLR2 Mask */ +#define SCT_OUT2_CLR_CLR3_Pos 3 /*!< SCT OUT2_CLR: CLR3 Position */ +#define SCT_OUT2_CLR_CLR3_Msk (0x01UL << SCT_OUT2_CLR_CLR3_Pos) /*!< SCT OUT2_CLR: CLR3 Mask */ +#define SCT_OUT2_CLR_CLR4_Pos 4 /*!< SCT OUT2_CLR: CLR4 Position */ +#define SCT_OUT2_CLR_CLR4_Msk (0x01UL << SCT_OUT2_CLR_CLR4_Pos) /*!< SCT OUT2_CLR: CLR4 Mask */ +#define SCT_OUT2_CLR_CLR5_Pos 5 /*!< SCT OUT2_CLR: CLR5 Position */ +#define SCT_OUT2_CLR_CLR5_Msk (0x01UL << SCT_OUT2_CLR_CLR5_Pos) /*!< SCT OUT2_CLR: CLR5 Mask */ +#define SCT_OUT2_CLR_CLR6_Pos 6 /*!< SCT OUT2_CLR: CLR6 Position */ +#define SCT_OUT2_CLR_CLR6_Msk (0x01UL << SCT_OUT2_CLR_CLR6_Pos) /*!< SCT OUT2_CLR: CLR6 Mask */ +#define SCT_OUT2_CLR_CLR7_Pos 7 /*!< SCT OUT2_CLR: CLR7 Position */ +#define SCT_OUT2_CLR_CLR7_Msk (0x01UL << SCT_OUT2_CLR_CLR7_Pos) /*!< SCT OUT2_CLR: CLR7 Mask */ +#define SCT_OUT2_CLR_CLR8_Pos 8 /*!< SCT OUT2_CLR: CLR8 Position */ +#define SCT_OUT2_CLR_CLR8_Msk (0x01UL << SCT_OUT2_CLR_CLR8_Pos) /*!< SCT OUT2_CLR: CLR8 Mask */ +#define SCT_OUT2_CLR_CLR9_Pos 9 /*!< SCT OUT2_CLR: CLR9 Position */ +#define SCT_OUT2_CLR_CLR9_Msk (0x01UL << SCT_OUT2_CLR_CLR9_Pos) /*!< SCT OUT2_CLR: CLR9 Mask */ +#define SCT_OUT2_CLR_CLR10_Pos 10 /*!< SCT OUT2_CLR: CLR10 Position */ +#define SCT_OUT2_CLR_CLR10_Msk (0x01UL << SCT_OUT2_CLR_CLR10_Pos) /*!< SCT OUT2_CLR: CLR10 Mask */ +#define SCT_OUT2_CLR_CLR11_Pos 11 /*!< SCT OUT2_CLR: CLR11 Position */ +#define SCT_OUT2_CLR_CLR11_Msk (0x01UL << SCT_OUT2_CLR_CLR11_Pos) /*!< SCT OUT2_CLR: CLR11 Mask */ +#define SCT_OUT2_CLR_CLR12_Pos 12 /*!< SCT OUT2_CLR: CLR12 Position */ +#define SCT_OUT2_CLR_CLR12_Msk (0x01UL << SCT_OUT2_CLR_CLR12_Pos) /*!< SCT OUT2_CLR: CLR12 Mask */ +#define SCT_OUT2_CLR_CLR13_Pos 13 /*!< SCT OUT2_CLR: CLR13 Position */ +#define SCT_OUT2_CLR_CLR13_Msk (0x01UL << SCT_OUT2_CLR_CLR13_Pos) /*!< SCT OUT2_CLR: CLR13 Mask */ +#define SCT_OUT2_CLR_CLR14_Pos 14 /*!< SCT OUT2_CLR: CLR14 Position */ +#define SCT_OUT2_CLR_CLR14_Msk (0x01UL << SCT_OUT2_CLR_CLR14_Pos) /*!< SCT OUT2_CLR: CLR14 Mask */ +#define SCT_OUT2_CLR_CLR15_Pos 15 /*!< SCT OUT2_CLR: CLR15 Position */ +#define SCT_OUT2_CLR_CLR15_Msk (0x01UL << SCT_OUT2_CLR_CLR15_Pos) /*!< SCT OUT2_CLR: CLR15 Mask */ + +/* -------------------------------- SCT_OUT3_SET -------------------------------- */ +#define SCT_OUT3_SET_SET0_Pos 0 /*!< SCT OUT3_SET: SET0 Position */ +#define SCT_OUT3_SET_SET0_Msk (0x01UL << SCT_OUT3_SET_SET0_Pos) /*!< SCT OUT3_SET: SET0 Mask */ +#define SCT_OUT3_SET_SET1_Pos 1 /*!< SCT OUT3_SET: SET1 Position */ +#define SCT_OUT3_SET_SET1_Msk (0x01UL << SCT_OUT3_SET_SET1_Pos) /*!< SCT OUT3_SET: SET1 Mask */ +#define SCT_OUT3_SET_SET2_Pos 2 /*!< SCT OUT3_SET: SET2 Position */ +#define SCT_OUT3_SET_SET2_Msk (0x01UL << SCT_OUT3_SET_SET2_Pos) /*!< SCT OUT3_SET: SET2 Mask */ +#define SCT_OUT3_SET_SET3_Pos 3 /*!< SCT OUT3_SET: SET3 Position */ +#define SCT_OUT3_SET_SET3_Msk (0x01UL << SCT_OUT3_SET_SET3_Pos) /*!< SCT OUT3_SET: SET3 Mask */ +#define SCT_OUT3_SET_SET4_Pos 4 /*!< SCT OUT3_SET: SET4 Position */ +#define SCT_OUT3_SET_SET4_Msk (0x01UL << SCT_OUT3_SET_SET4_Pos) /*!< SCT OUT3_SET: SET4 Mask */ +#define SCT_OUT3_SET_SET5_Pos 5 /*!< SCT OUT3_SET: SET5 Position */ +#define SCT_OUT3_SET_SET5_Msk (0x01UL << SCT_OUT3_SET_SET5_Pos) /*!< SCT OUT3_SET: SET5 Mask */ +#define SCT_OUT3_SET_SET6_Pos 6 /*!< SCT OUT3_SET: SET6 Position */ +#define SCT_OUT3_SET_SET6_Msk (0x01UL << SCT_OUT3_SET_SET6_Pos) /*!< SCT OUT3_SET: SET6 Mask */ +#define SCT_OUT3_SET_SET7_Pos 7 /*!< SCT OUT3_SET: SET7 Position */ +#define SCT_OUT3_SET_SET7_Msk (0x01UL << SCT_OUT3_SET_SET7_Pos) /*!< SCT OUT3_SET: SET7 Mask */ +#define SCT_OUT3_SET_SET8_Pos 8 /*!< SCT OUT3_SET: SET8 Position */ +#define SCT_OUT3_SET_SET8_Msk (0x01UL << SCT_OUT3_SET_SET8_Pos) /*!< SCT OUT3_SET: SET8 Mask */ +#define SCT_OUT3_SET_SET9_Pos 9 /*!< SCT OUT3_SET: SET9 Position */ +#define SCT_OUT3_SET_SET9_Msk (0x01UL << SCT_OUT3_SET_SET9_Pos) /*!< SCT OUT3_SET: SET9 Mask */ +#define SCT_OUT3_SET_SET10_Pos 10 /*!< SCT OUT3_SET: SET10 Position */ +#define SCT_OUT3_SET_SET10_Msk (0x01UL << SCT_OUT3_SET_SET10_Pos) /*!< SCT OUT3_SET: SET10 Mask */ +#define SCT_OUT3_SET_SET11_Pos 11 /*!< SCT OUT3_SET: SET11 Position */ +#define SCT_OUT3_SET_SET11_Msk (0x01UL << SCT_OUT3_SET_SET11_Pos) /*!< SCT OUT3_SET: SET11 Mask */ +#define SCT_OUT3_SET_SET12_Pos 12 /*!< SCT OUT3_SET: SET12 Position */ +#define SCT_OUT3_SET_SET12_Msk (0x01UL << SCT_OUT3_SET_SET12_Pos) /*!< SCT OUT3_SET: SET12 Mask */ +#define SCT_OUT3_SET_SET13_Pos 13 /*!< SCT OUT3_SET: SET13 Position */ +#define SCT_OUT3_SET_SET13_Msk (0x01UL << SCT_OUT3_SET_SET13_Pos) /*!< SCT OUT3_SET: SET13 Mask */ +#define SCT_OUT3_SET_SET14_Pos 14 /*!< SCT OUT3_SET: SET14 Position */ +#define SCT_OUT3_SET_SET14_Msk (0x01UL << SCT_OUT3_SET_SET14_Pos) /*!< SCT OUT3_SET: SET14 Mask */ +#define SCT_OUT3_SET_SET15_Pos 15 /*!< SCT OUT3_SET: SET15 Position */ +#define SCT_OUT3_SET_SET15_Msk (0x01UL << SCT_OUT3_SET_SET15_Pos) /*!< SCT OUT3_SET: SET15 Mask */ + +/* -------------------------------- SCT_OUT3_CLR -------------------------------- */ +#define SCT_OUT3_CLR_CLR0_Pos 0 /*!< SCT OUT3_CLR: CLR0 Position */ +#define SCT_OUT3_CLR_CLR0_Msk (0x01UL << SCT_OUT3_CLR_CLR0_Pos) /*!< SCT OUT3_CLR: CLR0 Mask */ +#define SCT_OUT3_CLR_CLR1_Pos 1 /*!< SCT OUT3_CLR: CLR1 Position */ +#define SCT_OUT3_CLR_CLR1_Msk (0x01UL << SCT_OUT3_CLR_CLR1_Pos) /*!< SCT OUT3_CLR: CLR1 Mask */ +#define SCT_OUT3_CLR_CLR2_Pos 2 /*!< SCT OUT3_CLR: CLR2 Position */ +#define SCT_OUT3_CLR_CLR2_Msk (0x01UL << SCT_OUT3_CLR_CLR2_Pos) /*!< SCT OUT3_CLR: CLR2 Mask */ +#define SCT_OUT3_CLR_CLR3_Pos 3 /*!< SCT OUT3_CLR: CLR3 Position */ +#define SCT_OUT3_CLR_CLR3_Msk (0x01UL << SCT_OUT3_CLR_CLR3_Pos) /*!< SCT OUT3_CLR: CLR3 Mask */ +#define SCT_OUT3_CLR_CLR4_Pos 4 /*!< SCT OUT3_CLR: CLR4 Position */ +#define SCT_OUT3_CLR_CLR4_Msk (0x01UL << SCT_OUT3_CLR_CLR4_Pos) /*!< SCT OUT3_CLR: CLR4 Mask */ +#define SCT_OUT3_CLR_CLR5_Pos 5 /*!< SCT OUT3_CLR: CLR5 Position */ +#define SCT_OUT3_CLR_CLR5_Msk (0x01UL << SCT_OUT3_CLR_CLR5_Pos) /*!< SCT OUT3_CLR: CLR5 Mask */ +#define SCT_OUT3_CLR_CLR6_Pos 6 /*!< SCT OUT3_CLR: CLR6 Position */ +#define SCT_OUT3_CLR_CLR6_Msk (0x01UL << SCT_OUT3_CLR_CLR6_Pos) /*!< SCT OUT3_CLR: CLR6 Mask */ +#define SCT_OUT3_CLR_CLR7_Pos 7 /*!< SCT OUT3_CLR: CLR7 Position */ +#define SCT_OUT3_CLR_CLR7_Msk (0x01UL << SCT_OUT3_CLR_CLR7_Pos) /*!< SCT OUT3_CLR: CLR7 Mask */ +#define SCT_OUT3_CLR_CLR8_Pos 8 /*!< SCT OUT3_CLR: CLR8 Position */ +#define SCT_OUT3_CLR_CLR8_Msk (0x01UL << SCT_OUT3_CLR_CLR8_Pos) /*!< SCT OUT3_CLR: CLR8 Mask */ +#define SCT_OUT3_CLR_CLR9_Pos 9 /*!< SCT OUT3_CLR: CLR9 Position */ +#define SCT_OUT3_CLR_CLR9_Msk (0x01UL << SCT_OUT3_CLR_CLR9_Pos) /*!< SCT OUT3_CLR: CLR9 Mask */ +#define SCT_OUT3_CLR_CLR10_Pos 10 /*!< SCT OUT3_CLR: CLR10 Position */ +#define SCT_OUT3_CLR_CLR10_Msk (0x01UL << SCT_OUT3_CLR_CLR10_Pos) /*!< SCT OUT3_CLR: CLR10 Mask */ +#define SCT_OUT3_CLR_CLR11_Pos 11 /*!< SCT OUT3_CLR: CLR11 Position */ +#define SCT_OUT3_CLR_CLR11_Msk (0x01UL << SCT_OUT3_CLR_CLR11_Pos) /*!< SCT OUT3_CLR: CLR11 Mask */ +#define SCT_OUT3_CLR_CLR12_Pos 12 /*!< SCT OUT3_CLR: CLR12 Position */ +#define SCT_OUT3_CLR_CLR12_Msk (0x01UL << SCT_OUT3_CLR_CLR12_Pos) /*!< SCT OUT3_CLR: CLR12 Mask */ +#define SCT_OUT3_CLR_CLR13_Pos 13 /*!< SCT OUT3_CLR: CLR13 Position */ +#define SCT_OUT3_CLR_CLR13_Msk (0x01UL << SCT_OUT3_CLR_CLR13_Pos) /*!< SCT OUT3_CLR: CLR13 Mask */ +#define SCT_OUT3_CLR_CLR14_Pos 14 /*!< SCT OUT3_CLR: CLR14 Position */ +#define SCT_OUT3_CLR_CLR14_Msk (0x01UL << SCT_OUT3_CLR_CLR14_Pos) /*!< SCT OUT3_CLR: CLR14 Mask */ +#define SCT_OUT3_CLR_CLR15_Pos 15 /*!< SCT OUT3_CLR: CLR15 Position */ +#define SCT_OUT3_CLR_CLR15_Msk (0x01UL << SCT_OUT3_CLR_CLR15_Pos) /*!< SCT OUT3_CLR: CLR15 Mask */ + +/* -------------------------------- SCT_OUT4_SET -------------------------------- */ +#define SCT_OUT4_SET_SET0_Pos 0 /*!< SCT OUT4_SET: SET0 Position */ +#define SCT_OUT4_SET_SET0_Msk (0x01UL << SCT_OUT4_SET_SET0_Pos) /*!< SCT OUT4_SET: SET0 Mask */ +#define SCT_OUT4_SET_SET1_Pos 1 /*!< SCT OUT4_SET: SET1 Position */ +#define SCT_OUT4_SET_SET1_Msk (0x01UL << SCT_OUT4_SET_SET1_Pos) /*!< SCT OUT4_SET: SET1 Mask */ +#define SCT_OUT4_SET_SET2_Pos 2 /*!< SCT OUT4_SET: SET2 Position */ +#define SCT_OUT4_SET_SET2_Msk (0x01UL << SCT_OUT4_SET_SET2_Pos) /*!< SCT OUT4_SET: SET2 Mask */ +#define SCT_OUT4_SET_SET3_Pos 3 /*!< SCT OUT4_SET: SET3 Position */ +#define SCT_OUT4_SET_SET3_Msk (0x01UL << SCT_OUT4_SET_SET3_Pos) /*!< SCT OUT4_SET: SET3 Mask */ +#define SCT_OUT4_SET_SET4_Pos 4 /*!< SCT OUT4_SET: SET4 Position */ +#define SCT_OUT4_SET_SET4_Msk (0x01UL << SCT_OUT4_SET_SET4_Pos) /*!< SCT OUT4_SET: SET4 Mask */ +#define SCT_OUT4_SET_SET5_Pos 5 /*!< SCT OUT4_SET: SET5 Position */ +#define SCT_OUT4_SET_SET5_Msk (0x01UL << SCT_OUT4_SET_SET5_Pos) /*!< SCT OUT4_SET: SET5 Mask */ +#define SCT_OUT4_SET_SET6_Pos 6 /*!< SCT OUT4_SET: SET6 Position */ +#define SCT_OUT4_SET_SET6_Msk (0x01UL << SCT_OUT4_SET_SET6_Pos) /*!< SCT OUT4_SET: SET6 Mask */ +#define SCT_OUT4_SET_SET7_Pos 7 /*!< SCT OUT4_SET: SET7 Position */ +#define SCT_OUT4_SET_SET7_Msk (0x01UL << SCT_OUT4_SET_SET7_Pos) /*!< SCT OUT4_SET: SET7 Mask */ +#define SCT_OUT4_SET_SET8_Pos 8 /*!< SCT OUT4_SET: SET8 Position */ +#define SCT_OUT4_SET_SET8_Msk (0x01UL << SCT_OUT4_SET_SET8_Pos) /*!< SCT OUT4_SET: SET8 Mask */ +#define SCT_OUT4_SET_SET9_Pos 9 /*!< SCT OUT4_SET: SET9 Position */ +#define SCT_OUT4_SET_SET9_Msk (0x01UL << SCT_OUT4_SET_SET9_Pos) /*!< SCT OUT4_SET: SET9 Mask */ +#define SCT_OUT4_SET_SET10_Pos 10 /*!< SCT OUT4_SET: SET10 Position */ +#define SCT_OUT4_SET_SET10_Msk (0x01UL << SCT_OUT4_SET_SET10_Pos) /*!< SCT OUT4_SET: SET10 Mask */ +#define SCT_OUT4_SET_SET11_Pos 11 /*!< SCT OUT4_SET: SET11 Position */ +#define SCT_OUT4_SET_SET11_Msk (0x01UL << SCT_OUT4_SET_SET11_Pos) /*!< SCT OUT4_SET: SET11 Mask */ +#define SCT_OUT4_SET_SET12_Pos 12 /*!< SCT OUT4_SET: SET12 Position */ +#define SCT_OUT4_SET_SET12_Msk (0x01UL << SCT_OUT4_SET_SET12_Pos) /*!< SCT OUT4_SET: SET12 Mask */ +#define SCT_OUT4_SET_SET13_Pos 13 /*!< SCT OUT4_SET: SET13 Position */ +#define SCT_OUT4_SET_SET13_Msk (0x01UL << SCT_OUT4_SET_SET13_Pos) /*!< SCT OUT4_SET: SET13 Mask */ +#define SCT_OUT4_SET_SET14_Pos 14 /*!< SCT OUT4_SET: SET14 Position */ +#define SCT_OUT4_SET_SET14_Msk (0x01UL << SCT_OUT4_SET_SET14_Pos) /*!< SCT OUT4_SET: SET14 Mask */ +#define SCT_OUT4_SET_SET15_Pos 15 /*!< SCT OUT4_SET: SET15 Position */ +#define SCT_OUT4_SET_SET15_Msk (0x01UL << SCT_OUT4_SET_SET15_Pos) /*!< SCT OUT4_SET: SET15 Mask */ + +/* -------------------------------- SCT_OUT4_CLR -------------------------------- */ +#define SCT_OUT4_CLR_CLR0_Pos 0 /*!< SCT OUT4_CLR: CLR0 Position */ +#define SCT_OUT4_CLR_CLR0_Msk (0x01UL << SCT_OUT4_CLR_CLR0_Pos) /*!< SCT OUT4_CLR: CLR0 Mask */ +#define SCT_OUT4_CLR_CLR1_Pos 1 /*!< SCT OUT4_CLR: CLR1 Position */ +#define SCT_OUT4_CLR_CLR1_Msk (0x01UL << SCT_OUT4_CLR_CLR1_Pos) /*!< SCT OUT4_CLR: CLR1 Mask */ +#define SCT_OUT4_CLR_CLR2_Pos 2 /*!< SCT OUT4_CLR: CLR2 Position */ +#define SCT_OUT4_CLR_CLR2_Msk (0x01UL << SCT_OUT4_CLR_CLR2_Pos) /*!< SCT OUT4_CLR: CLR2 Mask */ +#define SCT_OUT4_CLR_CLR3_Pos 3 /*!< SCT OUT4_CLR: CLR3 Position */ +#define SCT_OUT4_CLR_CLR3_Msk (0x01UL << SCT_OUT4_CLR_CLR3_Pos) /*!< SCT OUT4_CLR: CLR3 Mask */ +#define SCT_OUT4_CLR_CLR4_Pos 4 /*!< SCT OUT4_CLR: CLR4 Position */ +#define SCT_OUT4_CLR_CLR4_Msk (0x01UL << SCT_OUT4_CLR_CLR4_Pos) /*!< SCT OUT4_CLR: CLR4 Mask */ +#define SCT_OUT4_CLR_CLR5_Pos 5 /*!< SCT OUT4_CLR: CLR5 Position */ +#define SCT_OUT4_CLR_CLR5_Msk (0x01UL << SCT_OUT4_CLR_CLR5_Pos) /*!< SCT OUT4_CLR: CLR5 Mask */ +#define SCT_OUT4_CLR_CLR6_Pos 6 /*!< SCT OUT4_CLR: CLR6 Position */ +#define SCT_OUT4_CLR_CLR6_Msk (0x01UL << SCT_OUT4_CLR_CLR6_Pos) /*!< SCT OUT4_CLR: CLR6 Mask */ +#define SCT_OUT4_CLR_CLR7_Pos 7 /*!< SCT OUT4_CLR: CLR7 Position */ +#define SCT_OUT4_CLR_CLR7_Msk (0x01UL << SCT_OUT4_CLR_CLR7_Pos) /*!< SCT OUT4_CLR: CLR7 Mask */ +#define SCT_OUT4_CLR_CLR8_Pos 8 /*!< SCT OUT4_CLR: CLR8 Position */ +#define SCT_OUT4_CLR_CLR8_Msk (0x01UL << SCT_OUT4_CLR_CLR8_Pos) /*!< SCT OUT4_CLR: CLR8 Mask */ +#define SCT_OUT4_CLR_CLR9_Pos 9 /*!< SCT OUT4_CLR: CLR9 Position */ +#define SCT_OUT4_CLR_CLR9_Msk (0x01UL << SCT_OUT4_CLR_CLR9_Pos) /*!< SCT OUT4_CLR: CLR9 Mask */ +#define SCT_OUT4_CLR_CLR10_Pos 10 /*!< SCT OUT4_CLR: CLR10 Position */ +#define SCT_OUT4_CLR_CLR10_Msk (0x01UL << SCT_OUT4_CLR_CLR10_Pos) /*!< SCT OUT4_CLR: CLR10 Mask */ +#define SCT_OUT4_CLR_CLR11_Pos 11 /*!< SCT OUT4_CLR: CLR11 Position */ +#define SCT_OUT4_CLR_CLR11_Msk (0x01UL << SCT_OUT4_CLR_CLR11_Pos) /*!< SCT OUT4_CLR: CLR11 Mask */ +#define SCT_OUT4_CLR_CLR12_Pos 12 /*!< SCT OUT4_CLR: CLR12 Position */ +#define SCT_OUT4_CLR_CLR12_Msk (0x01UL << SCT_OUT4_CLR_CLR12_Pos) /*!< SCT OUT4_CLR: CLR12 Mask */ +#define SCT_OUT4_CLR_CLR13_Pos 13 /*!< SCT OUT4_CLR: CLR13 Position */ +#define SCT_OUT4_CLR_CLR13_Msk (0x01UL << SCT_OUT4_CLR_CLR13_Pos) /*!< SCT OUT4_CLR: CLR13 Mask */ +#define SCT_OUT4_CLR_CLR14_Pos 14 /*!< SCT OUT4_CLR: CLR14 Position */ +#define SCT_OUT4_CLR_CLR14_Msk (0x01UL << SCT_OUT4_CLR_CLR14_Pos) /*!< SCT OUT4_CLR: CLR14 Mask */ +#define SCT_OUT4_CLR_CLR15_Pos 15 /*!< SCT OUT4_CLR: CLR15 Position */ +#define SCT_OUT4_CLR_CLR15_Msk (0x01UL << SCT_OUT4_CLR_CLR15_Pos) /*!< SCT OUT4_CLR: CLR15 Mask */ + +/* -------------------------------- SCT_OUT5_SET -------------------------------- */ +#define SCT_OUT5_SET_SET0_Pos 0 /*!< SCT OUT5_SET: SET0 Position */ +#define SCT_OUT5_SET_SET0_Msk (0x01UL << SCT_OUT5_SET_SET0_Pos) /*!< SCT OUT5_SET: SET0 Mask */ +#define SCT_OUT5_SET_SET1_Pos 1 /*!< SCT OUT5_SET: SET1 Position */ +#define SCT_OUT5_SET_SET1_Msk (0x01UL << SCT_OUT5_SET_SET1_Pos) /*!< SCT OUT5_SET: SET1 Mask */ +#define SCT_OUT5_SET_SET2_Pos 2 /*!< SCT OUT5_SET: SET2 Position */ +#define SCT_OUT5_SET_SET2_Msk (0x01UL << SCT_OUT5_SET_SET2_Pos) /*!< SCT OUT5_SET: SET2 Mask */ +#define SCT_OUT5_SET_SET3_Pos 3 /*!< SCT OUT5_SET: SET3 Position */ +#define SCT_OUT5_SET_SET3_Msk (0x01UL << SCT_OUT5_SET_SET3_Pos) /*!< SCT OUT5_SET: SET3 Mask */ +#define SCT_OUT5_SET_SET4_Pos 4 /*!< SCT OUT5_SET: SET4 Position */ +#define SCT_OUT5_SET_SET4_Msk (0x01UL << SCT_OUT5_SET_SET4_Pos) /*!< SCT OUT5_SET: SET4 Mask */ +#define SCT_OUT5_SET_SET5_Pos 5 /*!< SCT OUT5_SET: SET5 Position */ +#define SCT_OUT5_SET_SET5_Msk (0x01UL << SCT_OUT5_SET_SET5_Pos) /*!< SCT OUT5_SET: SET5 Mask */ +#define SCT_OUT5_SET_SET6_Pos 6 /*!< SCT OUT5_SET: SET6 Position */ +#define SCT_OUT5_SET_SET6_Msk (0x01UL << SCT_OUT5_SET_SET6_Pos) /*!< SCT OUT5_SET: SET6 Mask */ +#define SCT_OUT5_SET_SET7_Pos 7 /*!< SCT OUT5_SET: SET7 Position */ +#define SCT_OUT5_SET_SET7_Msk (0x01UL << SCT_OUT5_SET_SET7_Pos) /*!< SCT OUT5_SET: SET7 Mask */ +#define SCT_OUT5_SET_SET8_Pos 8 /*!< SCT OUT5_SET: SET8 Position */ +#define SCT_OUT5_SET_SET8_Msk (0x01UL << SCT_OUT5_SET_SET8_Pos) /*!< SCT OUT5_SET: SET8 Mask */ +#define SCT_OUT5_SET_SET9_Pos 9 /*!< SCT OUT5_SET: SET9 Position */ +#define SCT_OUT5_SET_SET9_Msk (0x01UL << SCT_OUT5_SET_SET9_Pos) /*!< SCT OUT5_SET: SET9 Mask */ +#define SCT_OUT5_SET_SET10_Pos 10 /*!< SCT OUT5_SET: SET10 Position */ +#define SCT_OUT5_SET_SET10_Msk (0x01UL << SCT_OUT5_SET_SET10_Pos) /*!< SCT OUT5_SET: SET10 Mask */ +#define SCT_OUT5_SET_SET11_Pos 11 /*!< SCT OUT5_SET: SET11 Position */ +#define SCT_OUT5_SET_SET11_Msk (0x01UL << SCT_OUT5_SET_SET11_Pos) /*!< SCT OUT5_SET: SET11 Mask */ +#define SCT_OUT5_SET_SET12_Pos 12 /*!< SCT OUT5_SET: SET12 Position */ +#define SCT_OUT5_SET_SET12_Msk (0x01UL << SCT_OUT5_SET_SET12_Pos) /*!< SCT OUT5_SET: SET12 Mask */ +#define SCT_OUT5_SET_SET13_Pos 13 /*!< SCT OUT5_SET: SET13 Position */ +#define SCT_OUT5_SET_SET13_Msk (0x01UL << SCT_OUT5_SET_SET13_Pos) /*!< SCT OUT5_SET: SET13 Mask */ +#define SCT_OUT5_SET_SET14_Pos 14 /*!< SCT OUT5_SET: SET14 Position */ +#define SCT_OUT5_SET_SET14_Msk (0x01UL << SCT_OUT5_SET_SET14_Pos) /*!< SCT OUT5_SET: SET14 Mask */ +#define SCT_OUT5_SET_SET15_Pos 15 /*!< SCT OUT5_SET: SET15 Position */ +#define SCT_OUT5_SET_SET15_Msk (0x01UL << SCT_OUT5_SET_SET15_Pos) /*!< SCT OUT5_SET: SET15 Mask */ + +/* -------------------------------- SCT_OUT5_CLR -------------------------------- */ +#define SCT_OUT5_CLR_CLR0_Pos 0 /*!< SCT OUT5_CLR: CLR0 Position */ +#define SCT_OUT5_CLR_CLR0_Msk (0x01UL << SCT_OUT5_CLR_CLR0_Pos) /*!< SCT OUT5_CLR: CLR0 Mask */ +#define SCT_OUT5_CLR_CLR1_Pos 1 /*!< SCT OUT5_CLR: CLR1 Position */ +#define SCT_OUT5_CLR_CLR1_Msk (0x01UL << SCT_OUT5_CLR_CLR1_Pos) /*!< SCT OUT5_CLR: CLR1 Mask */ +#define SCT_OUT5_CLR_CLR2_Pos 2 /*!< SCT OUT5_CLR: CLR2 Position */ +#define SCT_OUT5_CLR_CLR2_Msk (0x01UL << SCT_OUT5_CLR_CLR2_Pos) /*!< SCT OUT5_CLR: CLR2 Mask */ +#define SCT_OUT5_CLR_CLR3_Pos 3 /*!< SCT OUT5_CLR: CLR3 Position */ +#define SCT_OUT5_CLR_CLR3_Msk (0x01UL << SCT_OUT5_CLR_CLR3_Pos) /*!< SCT OUT5_CLR: CLR3 Mask */ +#define SCT_OUT5_CLR_CLR4_Pos 4 /*!< SCT OUT5_CLR: CLR4 Position */ +#define SCT_OUT5_CLR_CLR4_Msk (0x01UL << SCT_OUT5_CLR_CLR4_Pos) /*!< SCT OUT5_CLR: CLR4 Mask */ +#define SCT_OUT5_CLR_CLR5_Pos 5 /*!< SCT OUT5_CLR: CLR5 Position */ +#define SCT_OUT5_CLR_CLR5_Msk (0x01UL << SCT_OUT5_CLR_CLR5_Pos) /*!< SCT OUT5_CLR: CLR5 Mask */ +#define SCT_OUT5_CLR_CLR6_Pos 6 /*!< SCT OUT5_CLR: CLR6 Position */ +#define SCT_OUT5_CLR_CLR6_Msk (0x01UL << SCT_OUT5_CLR_CLR6_Pos) /*!< SCT OUT5_CLR: CLR6 Mask */ +#define SCT_OUT5_CLR_CLR7_Pos 7 /*!< SCT OUT5_CLR: CLR7 Position */ +#define SCT_OUT5_CLR_CLR7_Msk (0x01UL << SCT_OUT5_CLR_CLR7_Pos) /*!< SCT OUT5_CLR: CLR7 Mask */ +#define SCT_OUT5_CLR_CLR8_Pos 8 /*!< SCT OUT5_CLR: CLR8 Position */ +#define SCT_OUT5_CLR_CLR8_Msk (0x01UL << SCT_OUT5_CLR_CLR8_Pos) /*!< SCT OUT5_CLR: CLR8 Mask */ +#define SCT_OUT5_CLR_CLR9_Pos 9 /*!< SCT OUT5_CLR: CLR9 Position */ +#define SCT_OUT5_CLR_CLR9_Msk (0x01UL << SCT_OUT5_CLR_CLR9_Pos) /*!< SCT OUT5_CLR: CLR9 Mask */ +#define SCT_OUT5_CLR_CLR10_Pos 10 /*!< SCT OUT5_CLR: CLR10 Position */ +#define SCT_OUT5_CLR_CLR10_Msk (0x01UL << SCT_OUT5_CLR_CLR10_Pos) /*!< SCT OUT5_CLR: CLR10 Mask */ +#define SCT_OUT5_CLR_CLR11_Pos 11 /*!< SCT OUT5_CLR: CLR11 Position */ +#define SCT_OUT5_CLR_CLR11_Msk (0x01UL << SCT_OUT5_CLR_CLR11_Pos) /*!< SCT OUT5_CLR: CLR11 Mask */ +#define SCT_OUT5_CLR_CLR12_Pos 12 /*!< SCT OUT5_CLR: CLR12 Position */ +#define SCT_OUT5_CLR_CLR12_Msk (0x01UL << SCT_OUT5_CLR_CLR12_Pos) /*!< SCT OUT5_CLR: CLR12 Mask */ +#define SCT_OUT5_CLR_CLR13_Pos 13 /*!< SCT OUT5_CLR: CLR13 Position */ +#define SCT_OUT5_CLR_CLR13_Msk (0x01UL << SCT_OUT5_CLR_CLR13_Pos) /*!< SCT OUT5_CLR: CLR13 Mask */ +#define SCT_OUT5_CLR_CLR14_Pos 14 /*!< SCT OUT5_CLR: CLR14 Position */ +#define SCT_OUT5_CLR_CLR14_Msk (0x01UL << SCT_OUT5_CLR_CLR14_Pos) /*!< SCT OUT5_CLR: CLR14 Mask */ +#define SCT_OUT5_CLR_CLR15_Pos 15 /*!< SCT OUT5_CLR: CLR15 Position */ +#define SCT_OUT5_CLR_CLR15_Msk (0x01UL << SCT_OUT5_CLR_CLR15_Pos) /*!< SCT OUT5_CLR: CLR15 Mask */ + +/* -------------------------------- SCT_OUT6_SET -------------------------------- */ +#define SCT_OUT6_SET_SET0_Pos 0 /*!< SCT OUT6_SET: SET0 Position */ +#define SCT_OUT6_SET_SET0_Msk (0x01UL << SCT_OUT6_SET_SET0_Pos) /*!< SCT OUT6_SET: SET0 Mask */ +#define SCT_OUT6_SET_SET1_Pos 1 /*!< SCT OUT6_SET: SET1 Position */ +#define SCT_OUT6_SET_SET1_Msk (0x01UL << SCT_OUT6_SET_SET1_Pos) /*!< SCT OUT6_SET: SET1 Mask */ +#define SCT_OUT6_SET_SET2_Pos 2 /*!< SCT OUT6_SET: SET2 Position */ +#define SCT_OUT6_SET_SET2_Msk (0x01UL << SCT_OUT6_SET_SET2_Pos) /*!< SCT OUT6_SET: SET2 Mask */ +#define SCT_OUT6_SET_SET3_Pos 3 /*!< SCT OUT6_SET: SET3 Position */ +#define SCT_OUT6_SET_SET3_Msk (0x01UL << SCT_OUT6_SET_SET3_Pos) /*!< SCT OUT6_SET: SET3 Mask */ +#define SCT_OUT6_SET_SET4_Pos 4 /*!< SCT OUT6_SET: SET4 Position */ +#define SCT_OUT6_SET_SET4_Msk (0x01UL << SCT_OUT6_SET_SET4_Pos) /*!< SCT OUT6_SET: SET4 Mask */ +#define SCT_OUT6_SET_SET5_Pos 5 /*!< SCT OUT6_SET: SET5 Position */ +#define SCT_OUT6_SET_SET5_Msk (0x01UL << SCT_OUT6_SET_SET5_Pos) /*!< SCT OUT6_SET: SET5 Mask */ +#define SCT_OUT6_SET_SET6_Pos 6 /*!< SCT OUT6_SET: SET6 Position */ +#define SCT_OUT6_SET_SET6_Msk (0x01UL << SCT_OUT6_SET_SET6_Pos) /*!< SCT OUT6_SET: SET6 Mask */ +#define SCT_OUT6_SET_SET7_Pos 7 /*!< SCT OUT6_SET: SET7 Position */ +#define SCT_OUT6_SET_SET7_Msk (0x01UL << SCT_OUT6_SET_SET7_Pos) /*!< SCT OUT6_SET: SET7 Mask */ +#define SCT_OUT6_SET_SET8_Pos 8 /*!< SCT OUT6_SET: SET8 Position */ +#define SCT_OUT6_SET_SET8_Msk (0x01UL << SCT_OUT6_SET_SET8_Pos) /*!< SCT OUT6_SET: SET8 Mask */ +#define SCT_OUT6_SET_SET9_Pos 9 /*!< SCT OUT6_SET: SET9 Position */ +#define SCT_OUT6_SET_SET9_Msk (0x01UL << SCT_OUT6_SET_SET9_Pos) /*!< SCT OUT6_SET: SET9 Mask */ +#define SCT_OUT6_SET_SET10_Pos 10 /*!< SCT OUT6_SET: SET10 Position */ +#define SCT_OUT6_SET_SET10_Msk (0x01UL << SCT_OUT6_SET_SET10_Pos) /*!< SCT OUT6_SET: SET10 Mask */ +#define SCT_OUT6_SET_SET11_Pos 11 /*!< SCT OUT6_SET: SET11 Position */ +#define SCT_OUT6_SET_SET11_Msk (0x01UL << SCT_OUT6_SET_SET11_Pos) /*!< SCT OUT6_SET: SET11 Mask */ +#define SCT_OUT6_SET_SET12_Pos 12 /*!< SCT OUT6_SET: SET12 Position */ +#define SCT_OUT6_SET_SET12_Msk (0x01UL << SCT_OUT6_SET_SET12_Pos) /*!< SCT OUT6_SET: SET12 Mask */ +#define SCT_OUT6_SET_SET13_Pos 13 /*!< SCT OUT6_SET: SET13 Position */ +#define SCT_OUT6_SET_SET13_Msk (0x01UL << SCT_OUT6_SET_SET13_Pos) /*!< SCT OUT6_SET: SET13 Mask */ +#define SCT_OUT6_SET_SET14_Pos 14 /*!< SCT OUT6_SET: SET14 Position */ +#define SCT_OUT6_SET_SET14_Msk (0x01UL << SCT_OUT6_SET_SET14_Pos) /*!< SCT OUT6_SET: SET14 Mask */ +#define SCT_OUT6_SET_SET15_Pos 15 /*!< SCT OUT6_SET: SET15 Position */ +#define SCT_OUT6_SET_SET15_Msk (0x01UL << SCT_OUT6_SET_SET15_Pos) /*!< SCT OUT6_SET: SET15 Mask */ + +/* -------------------------------- SCT_OUT6_CLR -------------------------------- */ +#define SCT_OUT6_CLR_CLR0_Pos 0 /*!< SCT OUT6_CLR: CLR0 Position */ +#define SCT_OUT6_CLR_CLR0_Msk (0x01UL << SCT_OUT6_CLR_CLR0_Pos) /*!< SCT OUT6_CLR: CLR0 Mask */ +#define SCT_OUT6_CLR_CLR1_Pos 1 /*!< SCT OUT6_CLR: CLR1 Position */ +#define SCT_OUT6_CLR_CLR1_Msk (0x01UL << SCT_OUT6_CLR_CLR1_Pos) /*!< SCT OUT6_CLR: CLR1 Mask */ +#define SCT_OUT6_CLR_CLR2_Pos 2 /*!< SCT OUT6_CLR: CLR2 Position */ +#define SCT_OUT6_CLR_CLR2_Msk (0x01UL << SCT_OUT6_CLR_CLR2_Pos) /*!< SCT OUT6_CLR: CLR2 Mask */ +#define SCT_OUT6_CLR_CLR3_Pos 3 /*!< SCT OUT6_CLR: CLR3 Position */ +#define SCT_OUT6_CLR_CLR3_Msk (0x01UL << SCT_OUT6_CLR_CLR3_Pos) /*!< SCT OUT6_CLR: CLR3 Mask */ +#define SCT_OUT6_CLR_CLR4_Pos 4 /*!< SCT OUT6_CLR: CLR4 Position */ +#define SCT_OUT6_CLR_CLR4_Msk (0x01UL << SCT_OUT6_CLR_CLR4_Pos) /*!< SCT OUT6_CLR: CLR4 Mask */ +#define SCT_OUT6_CLR_CLR5_Pos 5 /*!< SCT OUT6_CLR: CLR5 Position */ +#define SCT_OUT6_CLR_CLR5_Msk (0x01UL << SCT_OUT6_CLR_CLR5_Pos) /*!< SCT OUT6_CLR: CLR5 Mask */ +#define SCT_OUT6_CLR_CLR6_Pos 6 /*!< SCT OUT6_CLR: CLR6 Position */ +#define SCT_OUT6_CLR_CLR6_Msk (0x01UL << SCT_OUT6_CLR_CLR6_Pos) /*!< SCT OUT6_CLR: CLR6 Mask */ +#define SCT_OUT6_CLR_CLR7_Pos 7 /*!< SCT OUT6_CLR: CLR7 Position */ +#define SCT_OUT6_CLR_CLR7_Msk (0x01UL << SCT_OUT6_CLR_CLR7_Pos) /*!< SCT OUT6_CLR: CLR7 Mask */ +#define SCT_OUT6_CLR_CLR8_Pos 8 /*!< SCT OUT6_CLR: CLR8 Position */ +#define SCT_OUT6_CLR_CLR8_Msk (0x01UL << SCT_OUT6_CLR_CLR8_Pos) /*!< SCT OUT6_CLR: CLR8 Mask */ +#define SCT_OUT6_CLR_CLR9_Pos 9 /*!< SCT OUT6_CLR: CLR9 Position */ +#define SCT_OUT6_CLR_CLR9_Msk (0x01UL << SCT_OUT6_CLR_CLR9_Pos) /*!< SCT OUT6_CLR: CLR9 Mask */ +#define SCT_OUT6_CLR_CLR10_Pos 10 /*!< SCT OUT6_CLR: CLR10 Position */ +#define SCT_OUT6_CLR_CLR10_Msk (0x01UL << SCT_OUT6_CLR_CLR10_Pos) /*!< SCT OUT6_CLR: CLR10 Mask */ +#define SCT_OUT6_CLR_CLR11_Pos 11 /*!< SCT OUT6_CLR: CLR11 Position */ +#define SCT_OUT6_CLR_CLR11_Msk (0x01UL << SCT_OUT6_CLR_CLR11_Pos) /*!< SCT OUT6_CLR: CLR11 Mask */ +#define SCT_OUT6_CLR_CLR12_Pos 12 /*!< SCT OUT6_CLR: CLR12 Position */ +#define SCT_OUT6_CLR_CLR12_Msk (0x01UL << SCT_OUT6_CLR_CLR12_Pos) /*!< SCT OUT6_CLR: CLR12 Mask */ +#define SCT_OUT6_CLR_CLR13_Pos 13 /*!< SCT OUT6_CLR: CLR13 Position */ +#define SCT_OUT6_CLR_CLR13_Msk (0x01UL << SCT_OUT6_CLR_CLR13_Pos) /*!< SCT OUT6_CLR: CLR13 Mask */ +#define SCT_OUT6_CLR_CLR14_Pos 14 /*!< SCT OUT6_CLR: CLR14 Position */ +#define SCT_OUT6_CLR_CLR14_Msk (0x01UL << SCT_OUT6_CLR_CLR14_Pos) /*!< SCT OUT6_CLR: CLR14 Mask */ +#define SCT_OUT6_CLR_CLR15_Pos 15 /*!< SCT OUT6_CLR: CLR15 Position */ +#define SCT_OUT6_CLR_CLR15_Msk (0x01UL << SCT_OUT6_CLR_CLR15_Pos) /*!< SCT OUT6_CLR: CLR15 Mask */ + +/* -------------------------------- SCT_OUT7_SET -------------------------------- */ +#define SCT_OUT7_SET_SET0_Pos 0 /*!< SCT OUT7_SET: SET0 Position */ +#define SCT_OUT7_SET_SET0_Msk (0x01UL << SCT_OUT7_SET_SET0_Pos) /*!< SCT OUT7_SET: SET0 Mask */ +#define SCT_OUT7_SET_SET1_Pos 1 /*!< SCT OUT7_SET: SET1 Position */ +#define SCT_OUT7_SET_SET1_Msk (0x01UL << SCT_OUT7_SET_SET1_Pos) /*!< SCT OUT7_SET: SET1 Mask */ +#define SCT_OUT7_SET_SET2_Pos 2 /*!< SCT OUT7_SET: SET2 Position */ +#define SCT_OUT7_SET_SET2_Msk (0x01UL << SCT_OUT7_SET_SET2_Pos) /*!< SCT OUT7_SET: SET2 Mask */ +#define SCT_OUT7_SET_SET3_Pos 3 /*!< SCT OUT7_SET: SET3 Position */ +#define SCT_OUT7_SET_SET3_Msk (0x01UL << SCT_OUT7_SET_SET3_Pos) /*!< SCT OUT7_SET: SET3 Mask */ +#define SCT_OUT7_SET_SET4_Pos 4 /*!< SCT OUT7_SET: SET4 Position */ +#define SCT_OUT7_SET_SET4_Msk (0x01UL << SCT_OUT7_SET_SET4_Pos) /*!< SCT OUT7_SET: SET4 Mask */ +#define SCT_OUT7_SET_SET5_Pos 5 /*!< SCT OUT7_SET: SET5 Position */ +#define SCT_OUT7_SET_SET5_Msk (0x01UL << SCT_OUT7_SET_SET5_Pos) /*!< SCT OUT7_SET: SET5 Mask */ +#define SCT_OUT7_SET_SET6_Pos 6 /*!< SCT OUT7_SET: SET6 Position */ +#define SCT_OUT7_SET_SET6_Msk (0x01UL << SCT_OUT7_SET_SET6_Pos) /*!< SCT OUT7_SET: SET6 Mask */ +#define SCT_OUT7_SET_SET7_Pos 7 /*!< SCT OUT7_SET: SET7 Position */ +#define SCT_OUT7_SET_SET7_Msk (0x01UL << SCT_OUT7_SET_SET7_Pos) /*!< SCT OUT7_SET: SET7 Mask */ +#define SCT_OUT7_SET_SET8_Pos 8 /*!< SCT OUT7_SET: SET8 Position */ +#define SCT_OUT7_SET_SET8_Msk (0x01UL << SCT_OUT7_SET_SET8_Pos) /*!< SCT OUT7_SET: SET8 Mask */ +#define SCT_OUT7_SET_SET9_Pos 9 /*!< SCT OUT7_SET: SET9 Position */ +#define SCT_OUT7_SET_SET9_Msk (0x01UL << SCT_OUT7_SET_SET9_Pos) /*!< SCT OUT7_SET: SET9 Mask */ +#define SCT_OUT7_SET_SET10_Pos 10 /*!< SCT OUT7_SET: SET10 Position */ +#define SCT_OUT7_SET_SET10_Msk (0x01UL << SCT_OUT7_SET_SET10_Pos) /*!< SCT OUT7_SET: SET10 Mask */ +#define SCT_OUT7_SET_SET11_Pos 11 /*!< SCT OUT7_SET: SET11 Position */ +#define SCT_OUT7_SET_SET11_Msk (0x01UL << SCT_OUT7_SET_SET11_Pos) /*!< SCT OUT7_SET: SET11 Mask */ +#define SCT_OUT7_SET_SET12_Pos 12 /*!< SCT OUT7_SET: SET12 Position */ +#define SCT_OUT7_SET_SET12_Msk (0x01UL << SCT_OUT7_SET_SET12_Pos) /*!< SCT OUT7_SET: SET12 Mask */ +#define SCT_OUT7_SET_SET13_Pos 13 /*!< SCT OUT7_SET: SET13 Position */ +#define SCT_OUT7_SET_SET13_Msk (0x01UL << SCT_OUT7_SET_SET13_Pos) /*!< SCT OUT7_SET: SET13 Mask */ +#define SCT_OUT7_SET_SET14_Pos 14 /*!< SCT OUT7_SET: SET14 Position */ +#define SCT_OUT7_SET_SET14_Msk (0x01UL << SCT_OUT7_SET_SET14_Pos) /*!< SCT OUT7_SET: SET14 Mask */ +#define SCT_OUT7_SET_SET15_Pos 15 /*!< SCT OUT7_SET: SET15 Position */ +#define SCT_OUT7_SET_SET15_Msk (0x01UL << SCT_OUT7_SET_SET15_Pos) /*!< SCT OUT7_SET: SET15 Mask */ + +/* -------------------------------- SCT_OUT7_CLR -------------------------------- */ +#define SCT_OUT7_CLR_CLR0_Pos 0 /*!< SCT OUT7_CLR: CLR0 Position */ +#define SCT_OUT7_CLR_CLR0_Msk (0x01UL << SCT_OUT7_CLR_CLR0_Pos) /*!< SCT OUT7_CLR: CLR0 Mask */ +#define SCT_OUT7_CLR_CLR1_Pos 1 /*!< SCT OUT7_CLR: CLR1 Position */ +#define SCT_OUT7_CLR_CLR1_Msk (0x01UL << SCT_OUT7_CLR_CLR1_Pos) /*!< SCT OUT7_CLR: CLR1 Mask */ +#define SCT_OUT7_CLR_CLR2_Pos 2 /*!< SCT OUT7_CLR: CLR2 Position */ +#define SCT_OUT7_CLR_CLR2_Msk (0x01UL << SCT_OUT7_CLR_CLR2_Pos) /*!< SCT OUT7_CLR: CLR2 Mask */ +#define SCT_OUT7_CLR_CLR3_Pos 3 /*!< SCT OUT7_CLR: CLR3 Position */ +#define SCT_OUT7_CLR_CLR3_Msk (0x01UL << SCT_OUT7_CLR_CLR3_Pos) /*!< SCT OUT7_CLR: CLR3 Mask */ +#define SCT_OUT7_CLR_CLR4_Pos 4 /*!< SCT OUT7_CLR: CLR4 Position */ +#define SCT_OUT7_CLR_CLR4_Msk (0x01UL << SCT_OUT7_CLR_CLR4_Pos) /*!< SCT OUT7_CLR: CLR4 Mask */ +#define SCT_OUT7_CLR_CLR5_Pos 5 /*!< SCT OUT7_CLR: CLR5 Position */ +#define SCT_OUT7_CLR_CLR5_Msk (0x01UL << SCT_OUT7_CLR_CLR5_Pos) /*!< SCT OUT7_CLR: CLR5 Mask */ +#define SCT_OUT7_CLR_CLR6_Pos 6 /*!< SCT OUT7_CLR: CLR6 Position */ +#define SCT_OUT7_CLR_CLR6_Msk (0x01UL << SCT_OUT7_CLR_CLR6_Pos) /*!< SCT OUT7_CLR: CLR6 Mask */ +#define SCT_OUT7_CLR_CLR7_Pos 7 /*!< SCT OUT7_CLR: CLR7 Position */ +#define SCT_OUT7_CLR_CLR7_Msk (0x01UL << SCT_OUT7_CLR_CLR7_Pos) /*!< SCT OUT7_CLR: CLR7 Mask */ +#define SCT_OUT7_CLR_CLR8_Pos 8 /*!< SCT OUT7_CLR: CLR8 Position */ +#define SCT_OUT7_CLR_CLR8_Msk (0x01UL << SCT_OUT7_CLR_CLR8_Pos) /*!< SCT OUT7_CLR: CLR8 Mask */ +#define SCT_OUT7_CLR_CLR9_Pos 9 /*!< SCT OUT7_CLR: CLR9 Position */ +#define SCT_OUT7_CLR_CLR9_Msk (0x01UL << SCT_OUT7_CLR_CLR9_Pos) /*!< SCT OUT7_CLR: CLR9 Mask */ +#define SCT_OUT7_CLR_CLR10_Pos 10 /*!< SCT OUT7_CLR: CLR10 Position */ +#define SCT_OUT7_CLR_CLR10_Msk (0x01UL << SCT_OUT7_CLR_CLR10_Pos) /*!< SCT OUT7_CLR: CLR10 Mask */ +#define SCT_OUT7_CLR_CLR11_Pos 11 /*!< SCT OUT7_CLR: CLR11 Position */ +#define SCT_OUT7_CLR_CLR11_Msk (0x01UL << SCT_OUT7_CLR_CLR11_Pos) /*!< SCT OUT7_CLR: CLR11 Mask */ +#define SCT_OUT7_CLR_CLR12_Pos 12 /*!< SCT OUT7_CLR: CLR12 Position */ +#define SCT_OUT7_CLR_CLR12_Msk (0x01UL << SCT_OUT7_CLR_CLR12_Pos) /*!< SCT OUT7_CLR: CLR12 Mask */ +#define SCT_OUT7_CLR_CLR13_Pos 13 /*!< SCT OUT7_CLR: CLR13 Position */ +#define SCT_OUT7_CLR_CLR13_Msk (0x01UL << SCT_OUT7_CLR_CLR13_Pos) /*!< SCT OUT7_CLR: CLR13 Mask */ +#define SCT_OUT7_CLR_CLR14_Pos 14 /*!< SCT OUT7_CLR: CLR14 Position */ +#define SCT_OUT7_CLR_CLR14_Msk (0x01UL << SCT_OUT7_CLR_CLR14_Pos) /*!< SCT OUT7_CLR: CLR14 Mask */ +#define SCT_OUT7_CLR_CLR15_Pos 15 /*!< SCT OUT7_CLR: CLR15 Position */ +#define SCT_OUT7_CLR_CLR15_Msk (0x01UL << SCT_OUT7_CLR_CLR15_Pos) /*!< SCT OUT7_CLR: CLR15 Mask */ + +/* -------------------------------- SCT_OUT8_SET -------------------------------- */ +#define SCT_OUT8_SET_SET0_Pos 0 /*!< SCT OUT8_SET: SET0 Position */ +#define SCT_OUT8_SET_SET0_Msk (0x01UL << SCT_OUT8_SET_SET0_Pos) /*!< SCT OUT8_SET: SET0 Mask */ +#define SCT_OUT8_SET_SET1_Pos 1 /*!< SCT OUT8_SET: SET1 Position */ +#define SCT_OUT8_SET_SET1_Msk (0x01UL << SCT_OUT8_SET_SET1_Pos) /*!< SCT OUT8_SET: SET1 Mask */ +#define SCT_OUT8_SET_SET2_Pos 2 /*!< SCT OUT8_SET: SET2 Position */ +#define SCT_OUT8_SET_SET2_Msk (0x01UL << SCT_OUT8_SET_SET2_Pos) /*!< SCT OUT8_SET: SET2 Mask */ +#define SCT_OUT8_SET_SET3_Pos 3 /*!< SCT OUT8_SET: SET3 Position */ +#define SCT_OUT8_SET_SET3_Msk (0x01UL << SCT_OUT8_SET_SET3_Pos) /*!< SCT OUT8_SET: SET3 Mask */ +#define SCT_OUT8_SET_SET4_Pos 4 /*!< SCT OUT8_SET: SET4 Position */ +#define SCT_OUT8_SET_SET4_Msk (0x01UL << SCT_OUT8_SET_SET4_Pos) /*!< SCT OUT8_SET: SET4 Mask */ +#define SCT_OUT8_SET_SET5_Pos 5 /*!< SCT OUT8_SET: SET5 Position */ +#define SCT_OUT8_SET_SET5_Msk (0x01UL << SCT_OUT8_SET_SET5_Pos) /*!< SCT OUT8_SET: SET5 Mask */ +#define SCT_OUT8_SET_SET6_Pos 6 /*!< SCT OUT8_SET: SET6 Position */ +#define SCT_OUT8_SET_SET6_Msk (0x01UL << SCT_OUT8_SET_SET6_Pos) /*!< SCT OUT8_SET: SET6 Mask */ +#define SCT_OUT8_SET_SET7_Pos 7 /*!< SCT OUT8_SET: SET7 Position */ +#define SCT_OUT8_SET_SET7_Msk (0x01UL << SCT_OUT8_SET_SET7_Pos) /*!< SCT OUT8_SET: SET7 Mask */ +#define SCT_OUT8_SET_SET8_Pos 8 /*!< SCT OUT8_SET: SET8 Position */ +#define SCT_OUT8_SET_SET8_Msk (0x01UL << SCT_OUT8_SET_SET8_Pos) /*!< SCT OUT8_SET: SET8 Mask */ +#define SCT_OUT8_SET_SET9_Pos 9 /*!< SCT OUT8_SET: SET9 Position */ +#define SCT_OUT8_SET_SET9_Msk (0x01UL << SCT_OUT8_SET_SET9_Pos) /*!< SCT OUT8_SET: SET9 Mask */ +#define SCT_OUT8_SET_SET10_Pos 10 /*!< SCT OUT8_SET: SET10 Position */ +#define SCT_OUT8_SET_SET10_Msk (0x01UL << SCT_OUT8_SET_SET10_Pos) /*!< SCT OUT8_SET: SET10 Mask */ +#define SCT_OUT8_SET_SET11_Pos 11 /*!< SCT OUT8_SET: SET11 Position */ +#define SCT_OUT8_SET_SET11_Msk (0x01UL << SCT_OUT8_SET_SET11_Pos) /*!< SCT OUT8_SET: SET11 Mask */ +#define SCT_OUT8_SET_SET12_Pos 12 /*!< SCT OUT8_SET: SET12 Position */ +#define SCT_OUT8_SET_SET12_Msk (0x01UL << SCT_OUT8_SET_SET12_Pos) /*!< SCT OUT8_SET: SET12 Mask */ +#define SCT_OUT8_SET_SET13_Pos 13 /*!< SCT OUT8_SET: SET13 Position */ +#define SCT_OUT8_SET_SET13_Msk (0x01UL << SCT_OUT8_SET_SET13_Pos) /*!< SCT OUT8_SET: SET13 Mask */ +#define SCT_OUT8_SET_SET14_Pos 14 /*!< SCT OUT8_SET: SET14 Position */ +#define SCT_OUT8_SET_SET14_Msk (0x01UL << SCT_OUT8_SET_SET14_Pos) /*!< SCT OUT8_SET: SET14 Mask */ +#define SCT_OUT8_SET_SET15_Pos 15 /*!< SCT OUT8_SET: SET15 Position */ +#define SCT_OUT8_SET_SET15_Msk (0x01UL << SCT_OUT8_SET_SET15_Pos) /*!< SCT OUT8_SET: SET15 Mask */ + +/* -------------------------------- SCT_OUT8_CLR -------------------------------- */ +#define SCT_OUT8_CLR_CLR0_Pos 0 /*!< SCT OUT8_CLR: CLR0 Position */ +#define SCT_OUT8_CLR_CLR0_Msk (0x01UL << SCT_OUT8_CLR_CLR0_Pos) /*!< SCT OUT8_CLR: CLR0 Mask */ +#define SCT_OUT8_CLR_CLR1_Pos 1 /*!< SCT OUT8_CLR: CLR1 Position */ +#define SCT_OUT8_CLR_CLR1_Msk (0x01UL << SCT_OUT8_CLR_CLR1_Pos) /*!< SCT OUT8_CLR: CLR1 Mask */ +#define SCT_OUT8_CLR_CLR2_Pos 2 /*!< SCT OUT8_CLR: CLR2 Position */ +#define SCT_OUT8_CLR_CLR2_Msk (0x01UL << SCT_OUT8_CLR_CLR2_Pos) /*!< SCT OUT8_CLR: CLR2 Mask */ +#define SCT_OUT8_CLR_CLR3_Pos 3 /*!< SCT OUT8_CLR: CLR3 Position */ +#define SCT_OUT8_CLR_CLR3_Msk (0x01UL << SCT_OUT8_CLR_CLR3_Pos) /*!< SCT OUT8_CLR: CLR3 Mask */ +#define SCT_OUT8_CLR_CLR4_Pos 4 /*!< SCT OUT8_CLR: CLR4 Position */ +#define SCT_OUT8_CLR_CLR4_Msk (0x01UL << SCT_OUT8_CLR_CLR4_Pos) /*!< SCT OUT8_CLR: CLR4 Mask */ +#define SCT_OUT8_CLR_CLR5_Pos 5 /*!< SCT OUT8_CLR: CLR5 Position */ +#define SCT_OUT8_CLR_CLR5_Msk (0x01UL << SCT_OUT8_CLR_CLR5_Pos) /*!< SCT OUT8_CLR: CLR5 Mask */ +#define SCT_OUT8_CLR_CLR6_Pos 6 /*!< SCT OUT8_CLR: CLR6 Position */ +#define SCT_OUT8_CLR_CLR6_Msk (0x01UL << SCT_OUT8_CLR_CLR6_Pos) /*!< SCT OUT8_CLR: CLR6 Mask */ +#define SCT_OUT8_CLR_CLR7_Pos 7 /*!< SCT OUT8_CLR: CLR7 Position */ +#define SCT_OUT8_CLR_CLR7_Msk (0x01UL << SCT_OUT8_CLR_CLR7_Pos) /*!< SCT OUT8_CLR: CLR7 Mask */ +#define SCT_OUT8_CLR_CLR8_Pos 8 /*!< SCT OUT8_CLR: CLR8 Position */ +#define SCT_OUT8_CLR_CLR8_Msk (0x01UL << SCT_OUT8_CLR_CLR8_Pos) /*!< SCT OUT8_CLR: CLR8 Mask */ +#define SCT_OUT8_CLR_CLR9_Pos 9 /*!< SCT OUT8_CLR: CLR9 Position */ +#define SCT_OUT8_CLR_CLR9_Msk (0x01UL << SCT_OUT8_CLR_CLR9_Pos) /*!< SCT OUT8_CLR: CLR9 Mask */ +#define SCT_OUT8_CLR_CLR10_Pos 10 /*!< SCT OUT8_CLR: CLR10 Position */ +#define SCT_OUT8_CLR_CLR10_Msk (0x01UL << SCT_OUT8_CLR_CLR10_Pos) /*!< SCT OUT8_CLR: CLR10 Mask */ +#define SCT_OUT8_CLR_CLR11_Pos 11 /*!< SCT OUT8_CLR: CLR11 Position */ +#define SCT_OUT8_CLR_CLR11_Msk (0x01UL << SCT_OUT8_CLR_CLR11_Pos) /*!< SCT OUT8_CLR: CLR11 Mask */ +#define SCT_OUT8_CLR_CLR12_Pos 12 /*!< SCT OUT8_CLR: CLR12 Position */ +#define SCT_OUT8_CLR_CLR12_Msk (0x01UL << SCT_OUT8_CLR_CLR12_Pos) /*!< SCT OUT8_CLR: CLR12 Mask */ +#define SCT_OUT8_CLR_CLR13_Pos 13 /*!< SCT OUT8_CLR: CLR13 Position */ +#define SCT_OUT8_CLR_CLR13_Msk (0x01UL << SCT_OUT8_CLR_CLR13_Pos) /*!< SCT OUT8_CLR: CLR13 Mask */ +#define SCT_OUT8_CLR_CLR14_Pos 14 /*!< SCT OUT8_CLR: CLR14 Position */ +#define SCT_OUT8_CLR_CLR14_Msk (0x01UL << SCT_OUT8_CLR_CLR14_Pos) /*!< SCT OUT8_CLR: CLR14 Mask */ +#define SCT_OUT8_CLR_CLR15_Pos 15 /*!< SCT OUT8_CLR: CLR15 Position */ +#define SCT_OUT8_CLR_CLR15_Msk (0x01UL << SCT_OUT8_CLR_CLR15_Pos) /*!< SCT OUT8_CLR: CLR15 Mask */ + +/* -------------------------------- SCT_OUT9_SET -------------------------------- */ +#define SCT_OUT9_SET_SET0_Pos 0 /*!< SCT OUT9_SET: SET0 Position */ +#define SCT_OUT9_SET_SET0_Msk (0x01UL << SCT_OUT9_SET_SET0_Pos) /*!< SCT OUT9_SET: SET0 Mask */ +#define SCT_OUT9_SET_SET1_Pos 1 /*!< SCT OUT9_SET: SET1 Position */ +#define SCT_OUT9_SET_SET1_Msk (0x01UL << SCT_OUT9_SET_SET1_Pos) /*!< SCT OUT9_SET: SET1 Mask */ +#define SCT_OUT9_SET_SET2_Pos 2 /*!< SCT OUT9_SET: SET2 Position */ +#define SCT_OUT9_SET_SET2_Msk (0x01UL << SCT_OUT9_SET_SET2_Pos) /*!< SCT OUT9_SET: SET2 Mask */ +#define SCT_OUT9_SET_SET3_Pos 3 /*!< SCT OUT9_SET: SET3 Position */ +#define SCT_OUT9_SET_SET3_Msk (0x01UL << SCT_OUT9_SET_SET3_Pos) /*!< SCT OUT9_SET: SET3 Mask */ +#define SCT_OUT9_SET_SET4_Pos 4 /*!< SCT OUT9_SET: SET4 Position */ +#define SCT_OUT9_SET_SET4_Msk (0x01UL << SCT_OUT9_SET_SET4_Pos) /*!< SCT OUT9_SET: SET4 Mask */ +#define SCT_OUT9_SET_SET5_Pos 5 /*!< SCT OUT9_SET: SET5 Position */ +#define SCT_OUT9_SET_SET5_Msk (0x01UL << SCT_OUT9_SET_SET5_Pos) /*!< SCT OUT9_SET: SET5 Mask */ +#define SCT_OUT9_SET_SET6_Pos 6 /*!< SCT OUT9_SET: SET6 Position */ +#define SCT_OUT9_SET_SET6_Msk (0x01UL << SCT_OUT9_SET_SET6_Pos) /*!< SCT OUT9_SET: SET6 Mask */ +#define SCT_OUT9_SET_SET7_Pos 7 /*!< SCT OUT9_SET: SET7 Position */ +#define SCT_OUT9_SET_SET7_Msk (0x01UL << SCT_OUT9_SET_SET7_Pos) /*!< SCT OUT9_SET: SET7 Mask */ +#define SCT_OUT9_SET_SET8_Pos 8 /*!< SCT OUT9_SET: SET8 Position */ +#define SCT_OUT9_SET_SET8_Msk (0x01UL << SCT_OUT9_SET_SET8_Pos) /*!< SCT OUT9_SET: SET8 Mask */ +#define SCT_OUT9_SET_SET9_Pos 9 /*!< SCT OUT9_SET: SET9 Position */ +#define SCT_OUT9_SET_SET9_Msk (0x01UL << SCT_OUT9_SET_SET9_Pos) /*!< SCT OUT9_SET: SET9 Mask */ +#define SCT_OUT9_SET_SET10_Pos 10 /*!< SCT OUT9_SET: SET10 Position */ +#define SCT_OUT9_SET_SET10_Msk (0x01UL << SCT_OUT9_SET_SET10_Pos) /*!< SCT OUT9_SET: SET10 Mask */ +#define SCT_OUT9_SET_SET11_Pos 11 /*!< SCT OUT9_SET: SET11 Position */ +#define SCT_OUT9_SET_SET11_Msk (0x01UL << SCT_OUT9_SET_SET11_Pos) /*!< SCT OUT9_SET: SET11 Mask */ +#define SCT_OUT9_SET_SET12_Pos 12 /*!< SCT OUT9_SET: SET12 Position */ +#define SCT_OUT9_SET_SET12_Msk (0x01UL << SCT_OUT9_SET_SET12_Pos) /*!< SCT OUT9_SET: SET12 Mask */ +#define SCT_OUT9_SET_SET13_Pos 13 /*!< SCT OUT9_SET: SET13 Position */ +#define SCT_OUT9_SET_SET13_Msk (0x01UL << SCT_OUT9_SET_SET13_Pos) /*!< SCT OUT9_SET: SET13 Mask */ +#define SCT_OUT9_SET_SET14_Pos 14 /*!< SCT OUT9_SET: SET14 Position */ +#define SCT_OUT9_SET_SET14_Msk (0x01UL << SCT_OUT9_SET_SET14_Pos) /*!< SCT OUT9_SET: SET14 Mask */ +#define SCT_OUT9_SET_SET15_Pos 15 /*!< SCT OUT9_SET: SET15 Position */ +#define SCT_OUT9_SET_SET15_Msk (0x01UL << SCT_OUT9_SET_SET15_Pos) /*!< SCT OUT9_SET: SET15 Mask */ + +/* -------------------------------- SCT_OUT9_CLR -------------------------------- */ +#define SCT_OUT9_CLR_CLR0_Pos 0 /*!< SCT OUT9_CLR: CLR0 Position */ +#define SCT_OUT9_CLR_CLR0_Msk (0x01UL << SCT_OUT9_CLR_CLR0_Pos) /*!< SCT OUT9_CLR: CLR0 Mask */ +#define SCT_OUT9_CLR_CLR1_Pos 1 /*!< SCT OUT9_CLR: CLR1 Position */ +#define SCT_OUT9_CLR_CLR1_Msk (0x01UL << SCT_OUT9_CLR_CLR1_Pos) /*!< SCT OUT9_CLR: CLR1 Mask */ +#define SCT_OUT9_CLR_CLR2_Pos 2 /*!< SCT OUT9_CLR: CLR2 Position */ +#define SCT_OUT9_CLR_CLR2_Msk (0x01UL << SCT_OUT9_CLR_CLR2_Pos) /*!< SCT OUT9_CLR: CLR2 Mask */ +#define SCT_OUT9_CLR_CLR3_Pos 3 /*!< SCT OUT9_CLR: CLR3 Position */ +#define SCT_OUT9_CLR_CLR3_Msk (0x01UL << SCT_OUT9_CLR_CLR3_Pos) /*!< SCT OUT9_CLR: CLR3 Mask */ +#define SCT_OUT9_CLR_CLR4_Pos 4 /*!< SCT OUT9_CLR: CLR4 Position */ +#define SCT_OUT9_CLR_CLR4_Msk (0x01UL << SCT_OUT9_CLR_CLR4_Pos) /*!< SCT OUT9_CLR: CLR4 Mask */ +#define SCT_OUT9_CLR_CLR5_Pos 5 /*!< SCT OUT9_CLR: CLR5 Position */ +#define SCT_OUT9_CLR_CLR5_Msk (0x01UL << SCT_OUT9_CLR_CLR5_Pos) /*!< SCT OUT9_CLR: CLR5 Mask */ +#define SCT_OUT9_CLR_CLR6_Pos 6 /*!< SCT OUT9_CLR: CLR6 Position */ +#define SCT_OUT9_CLR_CLR6_Msk (0x01UL << SCT_OUT9_CLR_CLR6_Pos) /*!< SCT OUT9_CLR: CLR6 Mask */ +#define SCT_OUT9_CLR_CLR7_Pos 7 /*!< SCT OUT9_CLR: CLR7 Position */ +#define SCT_OUT9_CLR_CLR7_Msk (0x01UL << SCT_OUT9_CLR_CLR7_Pos) /*!< SCT OUT9_CLR: CLR7 Mask */ +#define SCT_OUT9_CLR_CLR8_Pos 8 /*!< SCT OUT9_CLR: CLR8 Position */ +#define SCT_OUT9_CLR_CLR8_Msk (0x01UL << SCT_OUT9_CLR_CLR8_Pos) /*!< SCT OUT9_CLR: CLR8 Mask */ +#define SCT_OUT9_CLR_CLR9_Pos 9 /*!< SCT OUT9_CLR: CLR9 Position */ +#define SCT_OUT9_CLR_CLR9_Msk (0x01UL << SCT_OUT9_CLR_CLR9_Pos) /*!< SCT OUT9_CLR: CLR9 Mask */ +#define SCT_OUT9_CLR_CLR10_Pos 10 /*!< SCT OUT9_CLR: CLR10 Position */ +#define SCT_OUT9_CLR_CLR10_Msk (0x01UL << SCT_OUT9_CLR_CLR10_Pos) /*!< SCT OUT9_CLR: CLR10 Mask */ +#define SCT_OUT9_CLR_CLR11_Pos 11 /*!< SCT OUT9_CLR: CLR11 Position */ +#define SCT_OUT9_CLR_CLR11_Msk (0x01UL << SCT_OUT9_CLR_CLR11_Pos) /*!< SCT OUT9_CLR: CLR11 Mask */ +#define SCT_OUT9_CLR_CLR12_Pos 12 /*!< SCT OUT9_CLR: CLR12 Position */ +#define SCT_OUT9_CLR_CLR12_Msk (0x01UL << SCT_OUT9_CLR_CLR12_Pos) /*!< SCT OUT9_CLR: CLR12 Mask */ +#define SCT_OUT9_CLR_CLR13_Pos 13 /*!< SCT OUT9_CLR: CLR13 Position */ +#define SCT_OUT9_CLR_CLR13_Msk (0x01UL << SCT_OUT9_CLR_CLR13_Pos) /*!< SCT OUT9_CLR: CLR13 Mask */ +#define SCT_OUT9_CLR_CLR14_Pos 14 /*!< SCT OUT9_CLR: CLR14 Position */ +#define SCT_OUT9_CLR_CLR14_Msk (0x01UL << SCT_OUT9_CLR_CLR14_Pos) /*!< SCT OUT9_CLR: CLR14 Mask */ +#define SCT_OUT9_CLR_CLR15_Pos 15 /*!< SCT OUT9_CLR: CLR15 Position */ +#define SCT_OUT9_CLR_CLR15_Msk (0x01UL << SCT_OUT9_CLR_CLR15_Pos) /*!< SCT OUT9_CLR: CLR15 Mask */ + +/* -------------------------------- SCT_OUT10_SET ------------------------------- */ +#define SCT_OUT10_SET_SET0_Pos 0 /*!< SCT OUT10_SET: SET0 Position */ +#define SCT_OUT10_SET_SET0_Msk (0x01UL << SCT_OUT10_SET_SET0_Pos) /*!< SCT OUT10_SET: SET0 Mask */ +#define SCT_OUT10_SET_SET1_Pos 1 /*!< SCT OUT10_SET: SET1 Position */ +#define SCT_OUT10_SET_SET1_Msk (0x01UL << SCT_OUT10_SET_SET1_Pos) /*!< SCT OUT10_SET: SET1 Mask */ +#define SCT_OUT10_SET_SET2_Pos 2 /*!< SCT OUT10_SET: SET2 Position */ +#define SCT_OUT10_SET_SET2_Msk (0x01UL << SCT_OUT10_SET_SET2_Pos) /*!< SCT OUT10_SET: SET2 Mask */ +#define SCT_OUT10_SET_SET3_Pos 3 /*!< SCT OUT10_SET: SET3 Position */ +#define SCT_OUT10_SET_SET3_Msk (0x01UL << SCT_OUT10_SET_SET3_Pos) /*!< SCT OUT10_SET: SET3 Mask */ +#define SCT_OUT10_SET_SET4_Pos 4 /*!< SCT OUT10_SET: SET4 Position */ +#define SCT_OUT10_SET_SET4_Msk (0x01UL << SCT_OUT10_SET_SET4_Pos) /*!< SCT OUT10_SET: SET4 Mask */ +#define SCT_OUT10_SET_SET5_Pos 5 /*!< SCT OUT10_SET: SET5 Position */ +#define SCT_OUT10_SET_SET5_Msk (0x01UL << SCT_OUT10_SET_SET5_Pos) /*!< SCT OUT10_SET: SET5 Mask */ +#define SCT_OUT10_SET_SET6_Pos 6 /*!< SCT OUT10_SET: SET6 Position */ +#define SCT_OUT10_SET_SET6_Msk (0x01UL << SCT_OUT10_SET_SET6_Pos) /*!< SCT OUT10_SET: SET6 Mask */ +#define SCT_OUT10_SET_SET7_Pos 7 /*!< SCT OUT10_SET: SET7 Position */ +#define SCT_OUT10_SET_SET7_Msk (0x01UL << SCT_OUT10_SET_SET7_Pos) /*!< SCT OUT10_SET: SET7 Mask */ +#define SCT_OUT10_SET_SET8_Pos 8 /*!< SCT OUT10_SET: SET8 Position */ +#define SCT_OUT10_SET_SET8_Msk (0x01UL << SCT_OUT10_SET_SET8_Pos) /*!< SCT OUT10_SET: SET8 Mask */ +#define SCT_OUT10_SET_SET9_Pos 9 /*!< SCT OUT10_SET: SET9 Position */ +#define SCT_OUT10_SET_SET9_Msk (0x01UL << SCT_OUT10_SET_SET9_Pos) /*!< SCT OUT10_SET: SET9 Mask */ +#define SCT_OUT10_SET_SET10_Pos 10 /*!< SCT OUT10_SET: SET10 Position */ +#define SCT_OUT10_SET_SET10_Msk (0x01UL << SCT_OUT10_SET_SET10_Pos) /*!< SCT OUT10_SET: SET10 Mask */ +#define SCT_OUT10_SET_SET11_Pos 11 /*!< SCT OUT10_SET: SET11 Position */ +#define SCT_OUT10_SET_SET11_Msk (0x01UL << SCT_OUT10_SET_SET11_Pos) /*!< SCT OUT10_SET: SET11 Mask */ +#define SCT_OUT10_SET_SET12_Pos 12 /*!< SCT OUT10_SET: SET12 Position */ +#define SCT_OUT10_SET_SET12_Msk (0x01UL << SCT_OUT10_SET_SET12_Pos) /*!< SCT OUT10_SET: SET12 Mask */ +#define SCT_OUT10_SET_SET13_Pos 13 /*!< SCT OUT10_SET: SET13 Position */ +#define SCT_OUT10_SET_SET13_Msk (0x01UL << SCT_OUT10_SET_SET13_Pos) /*!< SCT OUT10_SET: SET13 Mask */ +#define SCT_OUT10_SET_SET14_Pos 14 /*!< SCT OUT10_SET: SET14 Position */ +#define SCT_OUT10_SET_SET14_Msk (0x01UL << SCT_OUT10_SET_SET14_Pos) /*!< SCT OUT10_SET: SET14 Mask */ +#define SCT_OUT10_SET_SET15_Pos 15 /*!< SCT OUT10_SET: SET15 Position */ +#define SCT_OUT10_SET_SET15_Msk (0x01UL << SCT_OUT10_SET_SET15_Pos) /*!< SCT OUT10_SET: SET15 Mask */ + +/* -------------------------------- SCT_OUT10_CLR ------------------------------- */ +#define SCT_OUT10_CLR_CLR0_Pos 0 /*!< SCT OUT10_CLR: CLR0 Position */ +#define SCT_OUT10_CLR_CLR0_Msk (0x01UL << SCT_OUT10_CLR_CLR0_Pos) /*!< SCT OUT10_CLR: CLR0 Mask */ +#define SCT_OUT10_CLR_CLR1_Pos 1 /*!< SCT OUT10_CLR: CLR1 Position */ +#define SCT_OUT10_CLR_CLR1_Msk (0x01UL << SCT_OUT10_CLR_CLR1_Pos) /*!< SCT OUT10_CLR: CLR1 Mask */ +#define SCT_OUT10_CLR_CLR2_Pos 2 /*!< SCT OUT10_CLR: CLR2 Position */ +#define SCT_OUT10_CLR_CLR2_Msk (0x01UL << SCT_OUT10_CLR_CLR2_Pos) /*!< SCT OUT10_CLR: CLR2 Mask */ +#define SCT_OUT10_CLR_CLR3_Pos 3 /*!< SCT OUT10_CLR: CLR3 Position */ +#define SCT_OUT10_CLR_CLR3_Msk (0x01UL << SCT_OUT10_CLR_CLR3_Pos) /*!< SCT OUT10_CLR: CLR3 Mask */ +#define SCT_OUT10_CLR_CLR4_Pos 4 /*!< SCT OUT10_CLR: CLR4 Position */ +#define SCT_OUT10_CLR_CLR4_Msk (0x01UL << SCT_OUT10_CLR_CLR4_Pos) /*!< SCT OUT10_CLR: CLR4 Mask */ +#define SCT_OUT10_CLR_CLR5_Pos 5 /*!< SCT OUT10_CLR: CLR5 Position */ +#define SCT_OUT10_CLR_CLR5_Msk (0x01UL << SCT_OUT10_CLR_CLR5_Pos) /*!< SCT OUT10_CLR: CLR5 Mask */ +#define SCT_OUT10_CLR_CLR6_Pos 6 /*!< SCT OUT10_CLR: CLR6 Position */ +#define SCT_OUT10_CLR_CLR6_Msk (0x01UL << SCT_OUT10_CLR_CLR6_Pos) /*!< SCT OUT10_CLR: CLR6 Mask */ +#define SCT_OUT10_CLR_CLR7_Pos 7 /*!< SCT OUT10_CLR: CLR7 Position */ +#define SCT_OUT10_CLR_CLR7_Msk (0x01UL << SCT_OUT10_CLR_CLR7_Pos) /*!< SCT OUT10_CLR: CLR7 Mask */ +#define SCT_OUT10_CLR_CLR8_Pos 8 /*!< SCT OUT10_CLR: CLR8 Position */ +#define SCT_OUT10_CLR_CLR8_Msk (0x01UL << SCT_OUT10_CLR_CLR8_Pos) /*!< SCT OUT10_CLR: CLR8 Mask */ +#define SCT_OUT10_CLR_CLR9_Pos 9 /*!< SCT OUT10_CLR: CLR9 Position */ +#define SCT_OUT10_CLR_CLR9_Msk (0x01UL << SCT_OUT10_CLR_CLR9_Pos) /*!< SCT OUT10_CLR: CLR9 Mask */ +#define SCT_OUT10_CLR_CLR10_Pos 10 /*!< SCT OUT10_CLR: CLR10 Position */ +#define SCT_OUT10_CLR_CLR10_Msk (0x01UL << SCT_OUT10_CLR_CLR10_Pos) /*!< SCT OUT10_CLR: CLR10 Mask */ +#define SCT_OUT10_CLR_CLR11_Pos 11 /*!< SCT OUT10_CLR: CLR11 Position */ +#define SCT_OUT10_CLR_CLR11_Msk (0x01UL << SCT_OUT10_CLR_CLR11_Pos) /*!< SCT OUT10_CLR: CLR11 Mask */ +#define SCT_OUT10_CLR_CLR12_Pos 12 /*!< SCT OUT10_CLR: CLR12 Position */ +#define SCT_OUT10_CLR_CLR12_Msk (0x01UL << SCT_OUT10_CLR_CLR12_Pos) /*!< SCT OUT10_CLR: CLR12 Mask */ +#define SCT_OUT10_CLR_CLR13_Pos 13 /*!< SCT OUT10_CLR: CLR13 Position */ +#define SCT_OUT10_CLR_CLR13_Msk (0x01UL << SCT_OUT10_CLR_CLR13_Pos) /*!< SCT OUT10_CLR: CLR13 Mask */ +#define SCT_OUT10_CLR_CLR14_Pos 14 /*!< SCT OUT10_CLR: CLR14 Position */ +#define SCT_OUT10_CLR_CLR14_Msk (0x01UL << SCT_OUT10_CLR_CLR14_Pos) /*!< SCT OUT10_CLR: CLR14 Mask */ +#define SCT_OUT10_CLR_CLR15_Pos 15 /*!< SCT OUT10_CLR: CLR15 Position */ +#define SCT_OUT10_CLR_CLR15_Msk (0x01UL << SCT_OUT10_CLR_CLR15_Pos) /*!< SCT OUT10_CLR: CLR15 Mask */ + +/* -------------------------------- SCT_OUT11_SET ------------------------------- */ +#define SCT_OUT11_SET_SET0_Pos 0 /*!< SCT OUT11_SET: SET0 Position */ +#define SCT_OUT11_SET_SET0_Msk (0x01UL << SCT_OUT11_SET_SET0_Pos) /*!< SCT OUT11_SET: SET0 Mask */ +#define SCT_OUT11_SET_SET1_Pos 1 /*!< SCT OUT11_SET: SET1 Position */ +#define SCT_OUT11_SET_SET1_Msk (0x01UL << SCT_OUT11_SET_SET1_Pos) /*!< SCT OUT11_SET: SET1 Mask */ +#define SCT_OUT11_SET_SET2_Pos 2 /*!< SCT OUT11_SET: SET2 Position */ +#define SCT_OUT11_SET_SET2_Msk (0x01UL << SCT_OUT11_SET_SET2_Pos) /*!< SCT OUT11_SET: SET2 Mask */ +#define SCT_OUT11_SET_SET3_Pos 3 /*!< SCT OUT11_SET: SET3 Position */ +#define SCT_OUT11_SET_SET3_Msk (0x01UL << SCT_OUT11_SET_SET3_Pos) /*!< SCT OUT11_SET: SET3 Mask */ +#define SCT_OUT11_SET_SET4_Pos 4 /*!< SCT OUT11_SET: SET4 Position */ +#define SCT_OUT11_SET_SET4_Msk (0x01UL << SCT_OUT11_SET_SET4_Pos) /*!< SCT OUT11_SET: SET4 Mask */ +#define SCT_OUT11_SET_SET5_Pos 5 /*!< SCT OUT11_SET: SET5 Position */ +#define SCT_OUT11_SET_SET5_Msk (0x01UL << SCT_OUT11_SET_SET5_Pos) /*!< SCT OUT11_SET: SET5 Mask */ +#define SCT_OUT11_SET_SET6_Pos 6 /*!< SCT OUT11_SET: SET6 Position */ +#define SCT_OUT11_SET_SET6_Msk (0x01UL << SCT_OUT11_SET_SET6_Pos) /*!< SCT OUT11_SET: SET6 Mask */ +#define SCT_OUT11_SET_SET7_Pos 7 /*!< SCT OUT11_SET: SET7 Position */ +#define SCT_OUT11_SET_SET7_Msk (0x01UL << SCT_OUT11_SET_SET7_Pos) /*!< SCT OUT11_SET: SET7 Mask */ +#define SCT_OUT11_SET_SET8_Pos 8 /*!< SCT OUT11_SET: SET8 Position */ +#define SCT_OUT11_SET_SET8_Msk (0x01UL << SCT_OUT11_SET_SET8_Pos) /*!< SCT OUT11_SET: SET8 Mask */ +#define SCT_OUT11_SET_SET9_Pos 9 /*!< SCT OUT11_SET: SET9 Position */ +#define SCT_OUT11_SET_SET9_Msk (0x01UL << SCT_OUT11_SET_SET9_Pos) /*!< SCT OUT11_SET: SET9 Mask */ +#define SCT_OUT11_SET_SET10_Pos 10 /*!< SCT OUT11_SET: SET10 Position */ +#define SCT_OUT11_SET_SET10_Msk (0x01UL << SCT_OUT11_SET_SET10_Pos) /*!< SCT OUT11_SET: SET10 Mask */ +#define SCT_OUT11_SET_SET11_Pos 11 /*!< SCT OUT11_SET: SET11 Position */ +#define SCT_OUT11_SET_SET11_Msk (0x01UL << SCT_OUT11_SET_SET11_Pos) /*!< SCT OUT11_SET: SET11 Mask */ +#define SCT_OUT11_SET_SET12_Pos 12 /*!< SCT OUT11_SET: SET12 Position */ +#define SCT_OUT11_SET_SET12_Msk (0x01UL << SCT_OUT11_SET_SET12_Pos) /*!< SCT OUT11_SET: SET12 Mask */ +#define SCT_OUT11_SET_SET13_Pos 13 /*!< SCT OUT11_SET: SET13 Position */ +#define SCT_OUT11_SET_SET13_Msk (0x01UL << SCT_OUT11_SET_SET13_Pos) /*!< SCT OUT11_SET: SET13 Mask */ +#define SCT_OUT11_SET_SET14_Pos 14 /*!< SCT OUT11_SET: SET14 Position */ +#define SCT_OUT11_SET_SET14_Msk (0x01UL << SCT_OUT11_SET_SET14_Pos) /*!< SCT OUT11_SET: SET14 Mask */ +#define SCT_OUT11_SET_SET15_Pos 15 /*!< SCT OUT11_SET: SET15 Position */ +#define SCT_OUT11_SET_SET15_Msk (0x01UL << SCT_OUT11_SET_SET15_Pos) /*!< SCT OUT11_SET: SET15 Mask */ + +/* -------------------------------- SCT_OUT11_CLR ------------------------------- */ +#define SCT_OUT11_CLR_CLR0_Pos 0 /*!< SCT OUT11_CLR: CLR0 Position */ +#define SCT_OUT11_CLR_CLR0_Msk (0x01UL << SCT_OUT11_CLR_CLR0_Pos) /*!< SCT OUT11_CLR: CLR0 Mask */ +#define SCT_OUT11_CLR_CLR1_Pos 1 /*!< SCT OUT11_CLR: CLR1 Position */ +#define SCT_OUT11_CLR_CLR1_Msk (0x01UL << SCT_OUT11_CLR_CLR1_Pos) /*!< SCT OUT11_CLR: CLR1 Mask */ +#define SCT_OUT11_CLR_CLR2_Pos 2 /*!< SCT OUT11_CLR: CLR2 Position */ +#define SCT_OUT11_CLR_CLR2_Msk (0x01UL << SCT_OUT11_CLR_CLR2_Pos) /*!< SCT OUT11_CLR: CLR2 Mask */ +#define SCT_OUT11_CLR_CLR3_Pos 3 /*!< SCT OUT11_CLR: CLR3 Position */ +#define SCT_OUT11_CLR_CLR3_Msk (0x01UL << SCT_OUT11_CLR_CLR3_Pos) /*!< SCT OUT11_CLR: CLR3 Mask */ +#define SCT_OUT11_CLR_CLR4_Pos 4 /*!< SCT OUT11_CLR: CLR4 Position */ +#define SCT_OUT11_CLR_CLR4_Msk (0x01UL << SCT_OUT11_CLR_CLR4_Pos) /*!< SCT OUT11_CLR: CLR4 Mask */ +#define SCT_OUT11_CLR_CLR5_Pos 5 /*!< SCT OUT11_CLR: CLR5 Position */ +#define SCT_OUT11_CLR_CLR5_Msk (0x01UL << SCT_OUT11_CLR_CLR5_Pos) /*!< SCT OUT11_CLR: CLR5 Mask */ +#define SCT_OUT11_CLR_CLR6_Pos 6 /*!< SCT OUT11_CLR: CLR6 Position */ +#define SCT_OUT11_CLR_CLR6_Msk (0x01UL << SCT_OUT11_CLR_CLR6_Pos) /*!< SCT OUT11_CLR: CLR6 Mask */ +#define SCT_OUT11_CLR_CLR7_Pos 7 /*!< SCT OUT11_CLR: CLR7 Position */ +#define SCT_OUT11_CLR_CLR7_Msk (0x01UL << SCT_OUT11_CLR_CLR7_Pos) /*!< SCT OUT11_CLR: CLR7 Mask */ +#define SCT_OUT11_CLR_CLR8_Pos 8 /*!< SCT OUT11_CLR: CLR8 Position */ +#define SCT_OUT11_CLR_CLR8_Msk (0x01UL << SCT_OUT11_CLR_CLR8_Pos) /*!< SCT OUT11_CLR: CLR8 Mask */ +#define SCT_OUT11_CLR_CLR9_Pos 9 /*!< SCT OUT11_CLR: CLR9 Position */ +#define SCT_OUT11_CLR_CLR9_Msk (0x01UL << SCT_OUT11_CLR_CLR9_Pos) /*!< SCT OUT11_CLR: CLR9 Mask */ +#define SCT_OUT11_CLR_CLR10_Pos 10 /*!< SCT OUT11_CLR: CLR10 Position */ +#define SCT_OUT11_CLR_CLR10_Msk (0x01UL << SCT_OUT11_CLR_CLR10_Pos) /*!< SCT OUT11_CLR: CLR10 Mask */ +#define SCT_OUT11_CLR_CLR11_Pos 11 /*!< SCT OUT11_CLR: CLR11 Position */ +#define SCT_OUT11_CLR_CLR11_Msk (0x01UL << SCT_OUT11_CLR_CLR11_Pos) /*!< SCT OUT11_CLR: CLR11 Mask */ +#define SCT_OUT11_CLR_CLR12_Pos 12 /*!< SCT OUT11_CLR: CLR12 Position */ +#define SCT_OUT11_CLR_CLR12_Msk (0x01UL << SCT_OUT11_CLR_CLR12_Pos) /*!< SCT OUT11_CLR: CLR12 Mask */ +#define SCT_OUT11_CLR_CLR13_Pos 13 /*!< SCT OUT11_CLR: CLR13 Position */ +#define SCT_OUT11_CLR_CLR13_Msk (0x01UL << SCT_OUT11_CLR_CLR13_Pos) /*!< SCT OUT11_CLR: CLR13 Mask */ +#define SCT_OUT11_CLR_CLR14_Pos 14 /*!< SCT OUT11_CLR: CLR14 Position */ +#define SCT_OUT11_CLR_CLR14_Msk (0x01UL << SCT_OUT11_CLR_CLR14_Pos) /*!< SCT OUT11_CLR: CLR14 Mask */ +#define SCT_OUT11_CLR_CLR15_Pos 15 /*!< SCT OUT11_CLR: CLR15 Position */ +#define SCT_OUT11_CLR_CLR15_Msk (0x01UL << SCT_OUT11_CLR_CLR15_Pos) /*!< SCT OUT11_CLR: CLR15 Mask */ + +/* -------------------------------- SCT_OUT12_SET ------------------------------- */ +#define SCT_OUT12_SET_SET0_Pos 0 /*!< SCT OUT12_SET: SET0 Position */ +#define SCT_OUT12_SET_SET0_Msk (0x01UL << SCT_OUT12_SET_SET0_Pos) /*!< SCT OUT12_SET: SET0 Mask */ +#define SCT_OUT12_SET_SET1_Pos 1 /*!< SCT OUT12_SET: SET1 Position */ +#define SCT_OUT12_SET_SET1_Msk (0x01UL << SCT_OUT12_SET_SET1_Pos) /*!< SCT OUT12_SET: SET1 Mask */ +#define SCT_OUT12_SET_SET2_Pos 2 /*!< SCT OUT12_SET: SET2 Position */ +#define SCT_OUT12_SET_SET2_Msk (0x01UL << SCT_OUT12_SET_SET2_Pos) /*!< SCT OUT12_SET: SET2 Mask */ +#define SCT_OUT12_SET_SET3_Pos 3 /*!< SCT OUT12_SET: SET3 Position */ +#define SCT_OUT12_SET_SET3_Msk (0x01UL << SCT_OUT12_SET_SET3_Pos) /*!< SCT OUT12_SET: SET3 Mask */ +#define SCT_OUT12_SET_SET4_Pos 4 /*!< SCT OUT12_SET: SET4 Position */ +#define SCT_OUT12_SET_SET4_Msk (0x01UL << SCT_OUT12_SET_SET4_Pos) /*!< SCT OUT12_SET: SET4 Mask */ +#define SCT_OUT12_SET_SET5_Pos 5 /*!< SCT OUT12_SET: SET5 Position */ +#define SCT_OUT12_SET_SET5_Msk (0x01UL << SCT_OUT12_SET_SET5_Pos) /*!< SCT OUT12_SET: SET5 Mask */ +#define SCT_OUT12_SET_SET6_Pos 6 /*!< SCT OUT12_SET: SET6 Position */ +#define SCT_OUT12_SET_SET6_Msk (0x01UL << SCT_OUT12_SET_SET6_Pos) /*!< SCT OUT12_SET: SET6 Mask */ +#define SCT_OUT12_SET_SET7_Pos 7 /*!< SCT OUT12_SET: SET7 Position */ +#define SCT_OUT12_SET_SET7_Msk (0x01UL << SCT_OUT12_SET_SET7_Pos) /*!< SCT OUT12_SET: SET7 Mask */ +#define SCT_OUT12_SET_SET8_Pos 8 /*!< SCT OUT12_SET: SET8 Position */ +#define SCT_OUT12_SET_SET8_Msk (0x01UL << SCT_OUT12_SET_SET8_Pos) /*!< SCT OUT12_SET: SET8 Mask */ +#define SCT_OUT12_SET_SET9_Pos 9 /*!< SCT OUT12_SET: SET9 Position */ +#define SCT_OUT12_SET_SET9_Msk (0x01UL << SCT_OUT12_SET_SET9_Pos) /*!< SCT OUT12_SET: SET9 Mask */ +#define SCT_OUT12_SET_SET10_Pos 10 /*!< SCT OUT12_SET: SET10 Position */ +#define SCT_OUT12_SET_SET10_Msk (0x01UL << SCT_OUT12_SET_SET10_Pos) /*!< SCT OUT12_SET: SET10 Mask */ +#define SCT_OUT12_SET_SET11_Pos 11 /*!< SCT OUT12_SET: SET11 Position */ +#define SCT_OUT12_SET_SET11_Msk (0x01UL << SCT_OUT12_SET_SET11_Pos) /*!< SCT OUT12_SET: SET11 Mask */ +#define SCT_OUT12_SET_SET12_Pos 12 /*!< SCT OUT12_SET: SET12 Position */ +#define SCT_OUT12_SET_SET12_Msk (0x01UL << SCT_OUT12_SET_SET12_Pos) /*!< SCT OUT12_SET: SET12 Mask */ +#define SCT_OUT12_SET_SET13_Pos 13 /*!< SCT OUT12_SET: SET13 Position */ +#define SCT_OUT12_SET_SET13_Msk (0x01UL << SCT_OUT12_SET_SET13_Pos) /*!< SCT OUT12_SET: SET13 Mask */ +#define SCT_OUT12_SET_SET14_Pos 14 /*!< SCT OUT12_SET: SET14 Position */ +#define SCT_OUT12_SET_SET14_Msk (0x01UL << SCT_OUT12_SET_SET14_Pos) /*!< SCT OUT12_SET: SET14 Mask */ +#define SCT_OUT12_SET_SET15_Pos 15 /*!< SCT OUT12_SET: SET15 Position */ +#define SCT_OUT12_SET_SET15_Msk (0x01UL << SCT_OUT12_SET_SET15_Pos) /*!< SCT OUT12_SET: SET15 Mask */ + +/* -------------------------------- SCT_OUT12_CLR ------------------------------- */ +#define SCT_OUT12_CLR_CLR0_Pos 0 /*!< SCT OUT12_CLR: CLR0 Position */ +#define SCT_OUT12_CLR_CLR0_Msk (0x01UL << SCT_OUT12_CLR_CLR0_Pos) /*!< SCT OUT12_CLR: CLR0 Mask */ +#define SCT_OUT12_CLR_CLR1_Pos 1 /*!< SCT OUT12_CLR: CLR1 Position */ +#define SCT_OUT12_CLR_CLR1_Msk (0x01UL << SCT_OUT12_CLR_CLR1_Pos) /*!< SCT OUT12_CLR: CLR1 Mask */ +#define SCT_OUT12_CLR_CLR2_Pos 2 /*!< SCT OUT12_CLR: CLR2 Position */ +#define SCT_OUT12_CLR_CLR2_Msk (0x01UL << SCT_OUT12_CLR_CLR2_Pos) /*!< SCT OUT12_CLR: CLR2 Mask */ +#define SCT_OUT12_CLR_CLR3_Pos 3 /*!< SCT OUT12_CLR: CLR3 Position */ +#define SCT_OUT12_CLR_CLR3_Msk (0x01UL << SCT_OUT12_CLR_CLR3_Pos) /*!< SCT OUT12_CLR: CLR3 Mask */ +#define SCT_OUT12_CLR_CLR4_Pos 4 /*!< SCT OUT12_CLR: CLR4 Position */ +#define SCT_OUT12_CLR_CLR4_Msk (0x01UL << SCT_OUT12_CLR_CLR4_Pos) /*!< SCT OUT12_CLR: CLR4 Mask */ +#define SCT_OUT12_CLR_CLR5_Pos 5 /*!< SCT OUT12_CLR: CLR5 Position */ +#define SCT_OUT12_CLR_CLR5_Msk (0x01UL << SCT_OUT12_CLR_CLR5_Pos) /*!< SCT OUT12_CLR: CLR5 Mask */ +#define SCT_OUT12_CLR_CLR6_Pos 6 /*!< SCT OUT12_CLR: CLR6 Position */ +#define SCT_OUT12_CLR_CLR6_Msk (0x01UL << SCT_OUT12_CLR_CLR6_Pos) /*!< SCT OUT12_CLR: CLR6 Mask */ +#define SCT_OUT12_CLR_CLR7_Pos 7 /*!< SCT OUT12_CLR: CLR7 Position */ +#define SCT_OUT12_CLR_CLR7_Msk (0x01UL << SCT_OUT12_CLR_CLR7_Pos) /*!< SCT OUT12_CLR: CLR7 Mask */ +#define SCT_OUT12_CLR_CLR8_Pos 8 /*!< SCT OUT12_CLR: CLR8 Position */ +#define SCT_OUT12_CLR_CLR8_Msk (0x01UL << SCT_OUT12_CLR_CLR8_Pos) /*!< SCT OUT12_CLR: CLR8 Mask */ +#define SCT_OUT12_CLR_CLR9_Pos 9 /*!< SCT OUT12_CLR: CLR9 Position */ +#define SCT_OUT12_CLR_CLR9_Msk (0x01UL << SCT_OUT12_CLR_CLR9_Pos) /*!< SCT OUT12_CLR: CLR9 Mask */ +#define SCT_OUT12_CLR_CLR10_Pos 10 /*!< SCT OUT12_CLR: CLR10 Position */ +#define SCT_OUT12_CLR_CLR10_Msk (0x01UL << SCT_OUT12_CLR_CLR10_Pos) /*!< SCT OUT12_CLR: CLR10 Mask */ +#define SCT_OUT12_CLR_CLR11_Pos 11 /*!< SCT OUT12_CLR: CLR11 Position */ +#define SCT_OUT12_CLR_CLR11_Msk (0x01UL << SCT_OUT12_CLR_CLR11_Pos) /*!< SCT OUT12_CLR: CLR11 Mask */ +#define SCT_OUT12_CLR_CLR12_Pos 12 /*!< SCT OUT12_CLR: CLR12 Position */ +#define SCT_OUT12_CLR_CLR12_Msk (0x01UL << SCT_OUT12_CLR_CLR12_Pos) /*!< SCT OUT12_CLR: CLR12 Mask */ +#define SCT_OUT12_CLR_CLR13_Pos 13 /*!< SCT OUT12_CLR: CLR13 Position */ +#define SCT_OUT12_CLR_CLR13_Msk (0x01UL << SCT_OUT12_CLR_CLR13_Pos) /*!< SCT OUT12_CLR: CLR13 Mask */ +#define SCT_OUT12_CLR_CLR14_Pos 14 /*!< SCT OUT12_CLR: CLR14 Position */ +#define SCT_OUT12_CLR_CLR14_Msk (0x01UL << SCT_OUT12_CLR_CLR14_Pos) /*!< SCT OUT12_CLR: CLR14 Mask */ +#define SCT_OUT12_CLR_CLR15_Pos 15 /*!< SCT OUT12_CLR: CLR15 Position */ +#define SCT_OUT12_CLR_CLR15_Msk (0x01UL << SCT_OUT12_CLR_CLR15_Pos) /*!< SCT OUT12_CLR: CLR15 Mask */ + +/* -------------------------------- SCT_OUT13_SET ------------------------------- */ +#define SCT_OUT13_SET_SET0_Pos 0 /*!< SCT OUT13_SET: SET0 Position */ +#define SCT_OUT13_SET_SET0_Msk (0x01UL << SCT_OUT13_SET_SET0_Pos) /*!< SCT OUT13_SET: SET0 Mask */ +#define SCT_OUT13_SET_SET1_Pos 1 /*!< SCT OUT13_SET: SET1 Position */ +#define SCT_OUT13_SET_SET1_Msk (0x01UL << SCT_OUT13_SET_SET1_Pos) /*!< SCT OUT13_SET: SET1 Mask */ +#define SCT_OUT13_SET_SET2_Pos 2 /*!< SCT OUT13_SET: SET2 Position */ +#define SCT_OUT13_SET_SET2_Msk (0x01UL << SCT_OUT13_SET_SET2_Pos) /*!< SCT OUT13_SET: SET2 Mask */ +#define SCT_OUT13_SET_SET3_Pos 3 /*!< SCT OUT13_SET: SET3 Position */ +#define SCT_OUT13_SET_SET3_Msk (0x01UL << SCT_OUT13_SET_SET3_Pos) /*!< SCT OUT13_SET: SET3 Mask */ +#define SCT_OUT13_SET_SET4_Pos 4 /*!< SCT OUT13_SET: SET4 Position */ +#define SCT_OUT13_SET_SET4_Msk (0x01UL << SCT_OUT13_SET_SET4_Pos) /*!< SCT OUT13_SET: SET4 Mask */ +#define SCT_OUT13_SET_SET5_Pos 5 /*!< SCT OUT13_SET: SET5 Position */ +#define SCT_OUT13_SET_SET5_Msk (0x01UL << SCT_OUT13_SET_SET5_Pos) /*!< SCT OUT13_SET: SET5 Mask */ +#define SCT_OUT13_SET_SET6_Pos 6 /*!< SCT OUT13_SET: SET6 Position */ +#define SCT_OUT13_SET_SET6_Msk (0x01UL << SCT_OUT13_SET_SET6_Pos) /*!< SCT OUT13_SET: SET6 Mask */ +#define SCT_OUT13_SET_SET7_Pos 7 /*!< SCT OUT13_SET: SET7 Position */ +#define SCT_OUT13_SET_SET7_Msk (0x01UL << SCT_OUT13_SET_SET7_Pos) /*!< SCT OUT13_SET: SET7 Mask */ +#define SCT_OUT13_SET_SET8_Pos 8 /*!< SCT OUT13_SET: SET8 Position */ +#define SCT_OUT13_SET_SET8_Msk (0x01UL << SCT_OUT13_SET_SET8_Pos) /*!< SCT OUT13_SET: SET8 Mask */ +#define SCT_OUT13_SET_SET9_Pos 9 /*!< SCT OUT13_SET: SET9 Position */ +#define SCT_OUT13_SET_SET9_Msk (0x01UL << SCT_OUT13_SET_SET9_Pos) /*!< SCT OUT13_SET: SET9 Mask */ +#define SCT_OUT13_SET_SET10_Pos 10 /*!< SCT OUT13_SET: SET10 Position */ +#define SCT_OUT13_SET_SET10_Msk (0x01UL << SCT_OUT13_SET_SET10_Pos) /*!< SCT OUT13_SET: SET10 Mask */ +#define SCT_OUT13_SET_SET11_Pos 11 /*!< SCT OUT13_SET: SET11 Position */ +#define SCT_OUT13_SET_SET11_Msk (0x01UL << SCT_OUT13_SET_SET11_Pos) /*!< SCT OUT13_SET: SET11 Mask */ +#define SCT_OUT13_SET_SET12_Pos 12 /*!< SCT OUT13_SET: SET12 Position */ +#define SCT_OUT13_SET_SET12_Msk (0x01UL << SCT_OUT13_SET_SET12_Pos) /*!< SCT OUT13_SET: SET12 Mask */ +#define SCT_OUT13_SET_SET13_Pos 13 /*!< SCT OUT13_SET: SET13 Position */ +#define SCT_OUT13_SET_SET13_Msk (0x01UL << SCT_OUT13_SET_SET13_Pos) /*!< SCT OUT13_SET: SET13 Mask */ +#define SCT_OUT13_SET_SET14_Pos 14 /*!< SCT OUT13_SET: SET14 Position */ +#define SCT_OUT13_SET_SET14_Msk (0x01UL << SCT_OUT13_SET_SET14_Pos) /*!< SCT OUT13_SET: SET14 Mask */ +#define SCT_OUT13_SET_SET15_Pos 15 /*!< SCT OUT13_SET: SET15 Position */ +#define SCT_OUT13_SET_SET15_Msk (0x01UL << SCT_OUT13_SET_SET15_Pos) /*!< SCT OUT13_SET: SET15 Mask */ + +/* -------------------------------- SCT_OUT13_CLR ------------------------------- */ +#define SCT_OUT13_CLR_CLR0_Pos 0 /*!< SCT OUT13_CLR: CLR0 Position */ +#define SCT_OUT13_CLR_CLR0_Msk (0x01UL << SCT_OUT13_CLR_CLR0_Pos) /*!< SCT OUT13_CLR: CLR0 Mask */ +#define SCT_OUT13_CLR_CLR1_Pos 1 /*!< SCT OUT13_CLR: CLR1 Position */ +#define SCT_OUT13_CLR_CLR1_Msk (0x01UL << SCT_OUT13_CLR_CLR1_Pos) /*!< SCT OUT13_CLR: CLR1 Mask */ +#define SCT_OUT13_CLR_CLR2_Pos 2 /*!< SCT OUT13_CLR: CLR2 Position */ +#define SCT_OUT13_CLR_CLR2_Msk (0x01UL << SCT_OUT13_CLR_CLR2_Pos) /*!< SCT OUT13_CLR: CLR2 Mask */ +#define SCT_OUT13_CLR_CLR3_Pos 3 /*!< SCT OUT13_CLR: CLR3 Position */ +#define SCT_OUT13_CLR_CLR3_Msk (0x01UL << SCT_OUT13_CLR_CLR3_Pos) /*!< SCT OUT13_CLR: CLR3 Mask */ +#define SCT_OUT13_CLR_CLR4_Pos 4 /*!< SCT OUT13_CLR: CLR4 Position */ +#define SCT_OUT13_CLR_CLR4_Msk (0x01UL << SCT_OUT13_CLR_CLR4_Pos) /*!< SCT OUT13_CLR: CLR4 Mask */ +#define SCT_OUT13_CLR_CLR5_Pos 5 /*!< SCT OUT13_CLR: CLR5 Position */ +#define SCT_OUT13_CLR_CLR5_Msk (0x01UL << SCT_OUT13_CLR_CLR5_Pos) /*!< SCT OUT13_CLR: CLR5 Mask */ +#define SCT_OUT13_CLR_CLR6_Pos 6 /*!< SCT OUT13_CLR: CLR6 Position */ +#define SCT_OUT13_CLR_CLR6_Msk (0x01UL << SCT_OUT13_CLR_CLR6_Pos) /*!< SCT OUT13_CLR: CLR6 Mask */ +#define SCT_OUT13_CLR_CLR7_Pos 7 /*!< SCT OUT13_CLR: CLR7 Position */ +#define SCT_OUT13_CLR_CLR7_Msk (0x01UL << SCT_OUT13_CLR_CLR7_Pos) /*!< SCT OUT13_CLR: CLR7 Mask */ +#define SCT_OUT13_CLR_CLR8_Pos 8 /*!< SCT OUT13_CLR: CLR8 Position */ +#define SCT_OUT13_CLR_CLR8_Msk (0x01UL << SCT_OUT13_CLR_CLR8_Pos) /*!< SCT OUT13_CLR: CLR8 Mask */ +#define SCT_OUT13_CLR_CLR9_Pos 9 /*!< SCT OUT13_CLR: CLR9 Position */ +#define SCT_OUT13_CLR_CLR9_Msk (0x01UL << SCT_OUT13_CLR_CLR9_Pos) /*!< SCT OUT13_CLR: CLR9 Mask */ +#define SCT_OUT13_CLR_CLR10_Pos 10 /*!< SCT OUT13_CLR: CLR10 Position */ +#define SCT_OUT13_CLR_CLR10_Msk (0x01UL << SCT_OUT13_CLR_CLR10_Pos) /*!< SCT OUT13_CLR: CLR10 Mask */ +#define SCT_OUT13_CLR_CLR11_Pos 11 /*!< SCT OUT13_CLR: CLR11 Position */ +#define SCT_OUT13_CLR_CLR11_Msk (0x01UL << SCT_OUT13_CLR_CLR11_Pos) /*!< SCT OUT13_CLR: CLR11 Mask */ +#define SCT_OUT13_CLR_CLR12_Pos 12 /*!< SCT OUT13_CLR: CLR12 Position */ +#define SCT_OUT13_CLR_CLR12_Msk (0x01UL << SCT_OUT13_CLR_CLR12_Pos) /*!< SCT OUT13_CLR: CLR12 Mask */ +#define SCT_OUT13_CLR_CLR13_Pos 13 /*!< SCT OUT13_CLR: CLR13 Position */ +#define SCT_OUT13_CLR_CLR13_Msk (0x01UL << SCT_OUT13_CLR_CLR13_Pos) /*!< SCT OUT13_CLR: CLR13 Mask */ +#define SCT_OUT13_CLR_CLR14_Pos 14 /*!< SCT OUT13_CLR: CLR14 Position */ +#define SCT_OUT13_CLR_CLR14_Msk (0x01UL << SCT_OUT13_CLR_CLR14_Pos) /*!< SCT OUT13_CLR: CLR14 Mask */ +#define SCT_OUT13_CLR_CLR15_Pos 15 /*!< SCT OUT13_CLR: CLR15 Position */ +#define SCT_OUT13_CLR_CLR15_Msk (0x01UL << SCT_OUT13_CLR_CLR15_Pos) /*!< SCT OUT13_CLR: CLR15 Mask */ + +/* -------------------------------- SCT_OUT14_SET ------------------------------- */ +#define SCT_OUT14_SET_SET0_Pos 0 /*!< SCT OUT14_SET: SET0 Position */ +#define SCT_OUT14_SET_SET0_Msk (0x01UL << SCT_OUT14_SET_SET0_Pos) /*!< SCT OUT14_SET: SET0 Mask */ +#define SCT_OUT14_SET_SET1_Pos 1 /*!< SCT OUT14_SET: SET1 Position */ +#define SCT_OUT14_SET_SET1_Msk (0x01UL << SCT_OUT14_SET_SET1_Pos) /*!< SCT OUT14_SET: SET1 Mask */ +#define SCT_OUT14_SET_SET2_Pos 2 /*!< SCT OUT14_SET: SET2 Position */ +#define SCT_OUT14_SET_SET2_Msk (0x01UL << SCT_OUT14_SET_SET2_Pos) /*!< SCT OUT14_SET: SET2 Mask */ +#define SCT_OUT14_SET_SET3_Pos 3 /*!< SCT OUT14_SET: SET3 Position */ +#define SCT_OUT14_SET_SET3_Msk (0x01UL << SCT_OUT14_SET_SET3_Pos) /*!< SCT OUT14_SET: SET3 Mask */ +#define SCT_OUT14_SET_SET4_Pos 4 /*!< SCT OUT14_SET: SET4 Position */ +#define SCT_OUT14_SET_SET4_Msk (0x01UL << SCT_OUT14_SET_SET4_Pos) /*!< SCT OUT14_SET: SET4 Mask */ +#define SCT_OUT14_SET_SET5_Pos 5 /*!< SCT OUT14_SET: SET5 Position */ +#define SCT_OUT14_SET_SET5_Msk (0x01UL << SCT_OUT14_SET_SET5_Pos) /*!< SCT OUT14_SET: SET5 Mask */ +#define SCT_OUT14_SET_SET6_Pos 6 /*!< SCT OUT14_SET: SET6 Position */ +#define SCT_OUT14_SET_SET6_Msk (0x01UL << SCT_OUT14_SET_SET6_Pos) /*!< SCT OUT14_SET: SET6 Mask */ +#define SCT_OUT14_SET_SET7_Pos 7 /*!< SCT OUT14_SET: SET7 Position */ +#define SCT_OUT14_SET_SET7_Msk (0x01UL << SCT_OUT14_SET_SET7_Pos) /*!< SCT OUT14_SET: SET7 Mask */ +#define SCT_OUT14_SET_SET8_Pos 8 /*!< SCT OUT14_SET: SET8 Position */ +#define SCT_OUT14_SET_SET8_Msk (0x01UL << SCT_OUT14_SET_SET8_Pos) /*!< SCT OUT14_SET: SET8 Mask */ +#define SCT_OUT14_SET_SET9_Pos 9 /*!< SCT OUT14_SET: SET9 Position */ +#define SCT_OUT14_SET_SET9_Msk (0x01UL << SCT_OUT14_SET_SET9_Pos) /*!< SCT OUT14_SET: SET9 Mask */ +#define SCT_OUT14_SET_SET10_Pos 10 /*!< SCT OUT14_SET: SET10 Position */ +#define SCT_OUT14_SET_SET10_Msk (0x01UL << SCT_OUT14_SET_SET10_Pos) /*!< SCT OUT14_SET: SET10 Mask */ +#define SCT_OUT14_SET_SET11_Pos 11 /*!< SCT OUT14_SET: SET11 Position */ +#define SCT_OUT14_SET_SET11_Msk (0x01UL << SCT_OUT14_SET_SET11_Pos) /*!< SCT OUT14_SET: SET11 Mask */ +#define SCT_OUT14_SET_SET12_Pos 12 /*!< SCT OUT14_SET: SET12 Position */ +#define SCT_OUT14_SET_SET12_Msk (0x01UL << SCT_OUT14_SET_SET12_Pos) /*!< SCT OUT14_SET: SET12 Mask */ +#define SCT_OUT14_SET_SET13_Pos 13 /*!< SCT OUT14_SET: SET13 Position */ +#define SCT_OUT14_SET_SET13_Msk (0x01UL << SCT_OUT14_SET_SET13_Pos) /*!< SCT OUT14_SET: SET13 Mask */ +#define SCT_OUT14_SET_SET14_Pos 14 /*!< SCT OUT14_SET: SET14 Position */ +#define SCT_OUT14_SET_SET14_Msk (0x01UL << SCT_OUT14_SET_SET14_Pos) /*!< SCT OUT14_SET: SET14 Mask */ +#define SCT_OUT14_SET_SET15_Pos 15 /*!< SCT OUT14_SET: SET15 Position */ +#define SCT_OUT14_SET_SET15_Msk (0x01UL << SCT_OUT14_SET_SET15_Pos) /*!< SCT OUT14_SET: SET15 Mask */ + +/* -------------------------------- SCT_OUT14_CLR ------------------------------- */ +#define SCT_OUT14_CLR_CLR0_Pos 0 /*!< SCT OUT14_CLR: CLR0 Position */ +#define SCT_OUT14_CLR_CLR0_Msk (0x01UL << SCT_OUT14_CLR_CLR0_Pos) /*!< SCT OUT14_CLR: CLR0 Mask */ +#define SCT_OUT14_CLR_CLR1_Pos 1 /*!< SCT OUT14_CLR: CLR1 Position */ +#define SCT_OUT14_CLR_CLR1_Msk (0x01UL << SCT_OUT14_CLR_CLR1_Pos) /*!< SCT OUT14_CLR: CLR1 Mask */ +#define SCT_OUT14_CLR_CLR2_Pos 2 /*!< SCT OUT14_CLR: CLR2 Position */ +#define SCT_OUT14_CLR_CLR2_Msk (0x01UL << SCT_OUT14_CLR_CLR2_Pos) /*!< SCT OUT14_CLR: CLR2 Mask */ +#define SCT_OUT14_CLR_CLR3_Pos 3 /*!< SCT OUT14_CLR: CLR3 Position */ +#define SCT_OUT14_CLR_CLR3_Msk (0x01UL << SCT_OUT14_CLR_CLR3_Pos) /*!< SCT OUT14_CLR: CLR3 Mask */ +#define SCT_OUT14_CLR_CLR4_Pos 4 /*!< SCT OUT14_CLR: CLR4 Position */ +#define SCT_OUT14_CLR_CLR4_Msk (0x01UL << SCT_OUT14_CLR_CLR4_Pos) /*!< SCT OUT14_CLR: CLR4 Mask */ +#define SCT_OUT14_CLR_CLR5_Pos 5 /*!< SCT OUT14_CLR: CLR5 Position */ +#define SCT_OUT14_CLR_CLR5_Msk (0x01UL << SCT_OUT14_CLR_CLR5_Pos) /*!< SCT OUT14_CLR: CLR5 Mask */ +#define SCT_OUT14_CLR_CLR6_Pos 6 /*!< SCT OUT14_CLR: CLR6 Position */ +#define SCT_OUT14_CLR_CLR6_Msk (0x01UL << SCT_OUT14_CLR_CLR6_Pos) /*!< SCT OUT14_CLR: CLR6 Mask */ +#define SCT_OUT14_CLR_CLR7_Pos 7 /*!< SCT OUT14_CLR: CLR7 Position */ +#define SCT_OUT14_CLR_CLR7_Msk (0x01UL << SCT_OUT14_CLR_CLR7_Pos) /*!< SCT OUT14_CLR: CLR7 Mask */ +#define SCT_OUT14_CLR_CLR8_Pos 8 /*!< SCT OUT14_CLR: CLR8 Position */ +#define SCT_OUT14_CLR_CLR8_Msk (0x01UL << SCT_OUT14_CLR_CLR8_Pos) /*!< SCT OUT14_CLR: CLR8 Mask */ +#define SCT_OUT14_CLR_CLR9_Pos 9 /*!< SCT OUT14_CLR: CLR9 Position */ +#define SCT_OUT14_CLR_CLR9_Msk (0x01UL << SCT_OUT14_CLR_CLR9_Pos) /*!< SCT OUT14_CLR: CLR9 Mask */ +#define SCT_OUT14_CLR_CLR10_Pos 10 /*!< SCT OUT14_CLR: CLR10 Position */ +#define SCT_OUT14_CLR_CLR10_Msk (0x01UL << SCT_OUT14_CLR_CLR10_Pos) /*!< SCT OUT14_CLR: CLR10 Mask */ +#define SCT_OUT14_CLR_CLR11_Pos 11 /*!< SCT OUT14_CLR: CLR11 Position */ +#define SCT_OUT14_CLR_CLR11_Msk (0x01UL << SCT_OUT14_CLR_CLR11_Pos) /*!< SCT OUT14_CLR: CLR11 Mask */ +#define SCT_OUT14_CLR_CLR12_Pos 12 /*!< SCT OUT14_CLR: CLR12 Position */ +#define SCT_OUT14_CLR_CLR12_Msk (0x01UL << SCT_OUT14_CLR_CLR12_Pos) /*!< SCT OUT14_CLR: CLR12 Mask */ +#define SCT_OUT14_CLR_CLR13_Pos 13 /*!< SCT OUT14_CLR: CLR13 Position */ +#define SCT_OUT14_CLR_CLR13_Msk (0x01UL << SCT_OUT14_CLR_CLR13_Pos) /*!< SCT OUT14_CLR: CLR13 Mask */ +#define SCT_OUT14_CLR_CLR14_Pos 14 /*!< SCT OUT14_CLR: CLR14 Position */ +#define SCT_OUT14_CLR_CLR14_Msk (0x01UL << SCT_OUT14_CLR_CLR14_Pos) /*!< SCT OUT14_CLR: CLR14 Mask */ +#define SCT_OUT14_CLR_CLR15_Pos 15 /*!< SCT OUT14_CLR: CLR15 Position */ +#define SCT_OUT14_CLR_CLR15_Msk (0x01UL << SCT_OUT14_CLR_CLR15_Pos) /*!< SCT OUT14_CLR: CLR15 Mask */ + +/* -------------------------------- SCT_OUT15_SET ------------------------------- */ +#define SCT_OUT15_SET_SET0_Pos 0 /*!< SCT OUT15_SET: SET0 Position */ +#define SCT_OUT15_SET_SET0_Msk (0x01UL << SCT_OUT15_SET_SET0_Pos) /*!< SCT OUT15_SET: SET0 Mask */ +#define SCT_OUT15_SET_SET1_Pos 1 /*!< SCT OUT15_SET: SET1 Position */ +#define SCT_OUT15_SET_SET1_Msk (0x01UL << SCT_OUT15_SET_SET1_Pos) /*!< SCT OUT15_SET: SET1 Mask */ +#define SCT_OUT15_SET_SET2_Pos 2 /*!< SCT OUT15_SET: SET2 Position */ +#define SCT_OUT15_SET_SET2_Msk (0x01UL << SCT_OUT15_SET_SET2_Pos) /*!< SCT OUT15_SET: SET2 Mask */ +#define SCT_OUT15_SET_SET3_Pos 3 /*!< SCT OUT15_SET: SET3 Position */ +#define SCT_OUT15_SET_SET3_Msk (0x01UL << SCT_OUT15_SET_SET3_Pos) /*!< SCT OUT15_SET: SET3 Mask */ +#define SCT_OUT15_SET_SET4_Pos 4 /*!< SCT OUT15_SET: SET4 Position */ +#define SCT_OUT15_SET_SET4_Msk (0x01UL << SCT_OUT15_SET_SET4_Pos) /*!< SCT OUT15_SET: SET4 Mask */ +#define SCT_OUT15_SET_SET5_Pos 5 /*!< SCT OUT15_SET: SET5 Position */ +#define SCT_OUT15_SET_SET5_Msk (0x01UL << SCT_OUT15_SET_SET5_Pos) /*!< SCT OUT15_SET: SET5 Mask */ +#define SCT_OUT15_SET_SET6_Pos 6 /*!< SCT OUT15_SET: SET6 Position */ +#define SCT_OUT15_SET_SET6_Msk (0x01UL << SCT_OUT15_SET_SET6_Pos) /*!< SCT OUT15_SET: SET6 Mask */ +#define SCT_OUT15_SET_SET7_Pos 7 /*!< SCT OUT15_SET: SET7 Position */ +#define SCT_OUT15_SET_SET7_Msk (0x01UL << SCT_OUT15_SET_SET7_Pos) /*!< SCT OUT15_SET: SET7 Mask */ +#define SCT_OUT15_SET_SET8_Pos 8 /*!< SCT OUT15_SET: SET8 Position */ +#define SCT_OUT15_SET_SET8_Msk (0x01UL << SCT_OUT15_SET_SET8_Pos) /*!< SCT OUT15_SET: SET8 Mask */ +#define SCT_OUT15_SET_SET9_Pos 9 /*!< SCT OUT15_SET: SET9 Position */ +#define SCT_OUT15_SET_SET9_Msk (0x01UL << SCT_OUT15_SET_SET9_Pos) /*!< SCT OUT15_SET: SET9 Mask */ +#define SCT_OUT15_SET_SET10_Pos 10 /*!< SCT OUT15_SET: SET10 Position */ +#define SCT_OUT15_SET_SET10_Msk (0x01UL << SCT_OUT15_SET_SET10_Pos) /*!< SCT OUT15_SET: SET10 Mask */ +#define SCT_OUT15_SET_SET11_Pos 11 /*!< SCT OUT15_SET: SET11 Position */ +#define SCT_OUT15_SET_SET11_Msk (0x01UL << SCT_OUT15_SET_SET11_Pos) /*!< SCT OUT15_SET: SET11 Mask */ +#define SCT_OUT15_SET_SET12_Pos 12 /*!< SCT OUT15_SET: SET12 Position */ +#define SCT_OUT15_SET_SET12_Msk (0x01UL << SCT_OUT15_SET_SET12_Pos) /*!< SCT OUT15_SET: SET12 Mask */ +#define SCT_OUT15_SET_SET13_Pos 13 /*!< SCT OUT15_SET: SET13 Position */ +#define SCT_OUT15_SET_SET13_Msk (0x01UL << SCT_OUT15_SET_SET13_Pos) /*!< SCT OUT15_SET: SET13 Mask */ +#define SCT_OUT15_SET_SET14_Pos 14 /*!< SCT OUT15_SET: SET14 Position */ +#define SCT_OUT15_SET_SET14_Msk (0x01UL << SCT_OUT15_SET_SET14_Pos) /*!< SCT OUT15_SET: SET14 Mask */ +#define SCT_OUT15_SET_SET15_Pos 15 /*!< SCT OUT15_SET: SET15 Position */ +#define SCT_OUT15_SET_SET15_Msk (0x01UL << SCT_OUT15_SET_SET15_Pos) /*!< SCT OUT15_SET: SET15 Mask */ + +/* -------------------------------- SCT_OUT15_CLR ------------------------------- */ +#define SCT_OUT15_CLR_CLR0_Pos 0 /*!< SCT OUT15_CLR: CLR0 Position */ +#define SCT_OUT15_CLR_CLR0_Msk (0x01UL << SCT_OUT15_CLR_CLR0_Pos) /*!< SCT OUT15_CLR: CLR0 Mask */ +#define SCT_OUT15_CLR_CLR1_Pos 1 /*!< SCT OUT15_CLR: CLR1 Position */ +#define SCT_OUT15_CLR_CLR1_Msk (0x01UL << SCT_OUT15_CLR_CLR1_Pos) /*!< SCT OUT15_CLR: CLR1 Mask */ +#define SCT_OUT15_CLR_CLR2_Pos 2 /*!< SCT OUT15_CLR: CLR2 Position */ +#define SCT_OUT15_CLR_CLR2_Msk (0x01UL << SCT_OUT15_CLR_CLR2_Pos) /*!< SCT OUT15_CLR: CLR2 Mask */ +#define SCT_OUT15_CLR_CLR3_Pos 3 /*!< SCT OUT15_CLR: CLR3 Position */ +#define SCT_OUT15_CLR_CLR3_Msk (0x01UL << SCT_OUT15_CLR_CLR3_Pos) /*!< SCT OUT15_CLR: CLR3 Mask */ +#define SCT_OUT15_CLR_CLR4_Pos 4 /*!< SCT OUT15_CLR: CLR4 Position */ +#define SCT_OUT15_CLR_CLR4_Msk (0x01UL << SCT_OUT15_CLR_CLR4_Pos) /*!< SCT OUT15_CLR: CLR4 Mask */ +#define SCT_OUT15_CLR_CLR5_Pos 5 /*!< SCT OUT15_CLR: CLR5 Position */ +#define SCT_OUT15_CLR_CLR5_Msk (0x01UL << SCT_OUT15_CLR_CLR5_Pos) /*!< SCT OUT15_CLR: CLR5 Mask */ +#define SCT_OUT15_CLR_CLR6_Pos 6 /*!< SCT OUT15_CLR: CLR6 Position */ +#define SCT_OUT15_CLR_CLR6_Msk (0x01UL << SCT_OUT15_CLR_CLR6_Pos) /*!< SCT OUT15_CLR: CLR6 Mask */ +#define SCT_OUT15_CLR_CLR7_Pos 7 /*!< SCT OUT15_CLR: CLR7 Position */ +#define SCT_OUT15_CLR_CLR7_Msk (0x01UL << SCT_OUT15_CLR_CLR7_Pos) /*!< SCT OUT15_CLR: CLR7 Mask */ +#define SCT_OUT15_CLR_CLR8_Pos 8 /*!< SCT OUT15_CLR: CLR8 Position */ +#define SCT_OUT15_CLR_CLR8_Msk (0x01UL << SCT_OUT15_CLR_CLR8_Pos) /*!< SCT OUT15_CLR: CLR8 Mask */ +#define SCT_OUT15_CLR_CLR9_Pos 9 /*!< SCT OUT15_CLR: CLR9 Position */ +#define SCT_OUT15_CLR_CLR9_Msk (0x01UL << SCT_OUT15_CLR_CLR9_Pos) /*!< SCT OUT15_CLR: CLR9 Mask */ +#define SCT_OUT15_CLR_CLR10_Pos 10 /*!< SCT OUT15_CLR: CLR10 Position */ +#define SCT_OUT15_CLR_CLR10_Msk (0x01UL << SCT_OUT15_CLR_CLR10_Pos) /*!< SCT OUT15_CLR: CLR10 Mask */ +#define SCT_OUT15_CLR_CLR11_Pos 11 /*!< SCT OUT15_CLR: CLR11 Position */ +#define SCT_OUT15_CLR_CLR11_Msk (0x01UL << SCT_OUT15_CLR_CLR11_Pos) /*!< SCT OUT15_CLR: CLR11 Mask */ +#define SCT_OUT15_CLR_CLR12_Pos 12 /*!< SCT OUT15_CLR: CLR12 Position */ +#define SCT_OUT15_CLR_CLR12_Msk (0x01UL << SCT_OUT15_CLR_CLR12_Pos) /*!< SCT OUT15_CLR: CLR12 Mask */ +#define SCT_OUT15_CLR_CLR13_Pos 13 /*!< SCT OUT15_CLR: CLR13 Position */ +#define SCT_OUT15_CLR_CLR13_Msk (0x01UL << SCT_OUT15_CLR_CLR13_Pos) /*!< SCT OUT15_CLR: CLR13 Mask */ +#define SCT_OUT15_CLR_CLR14_Pos 14 /*!< SCT OUT15_CLR: CLR14 Position */ +#define SCT_OUT15_CLR_CLR14_Msk (0x01UL << SCT_OUT15_CLR_CLR14_Pos) /*!< SCT OUT15_CLR: CLR14 Mask */ +#define SCT_OUT15_CLR_CLR15_Pos 15 /*!< SCT OUT15_CLR: CLR15 Position */ +#define SCT_OUT15_CLR_CLR15_Msk (0x01UL << SCT_OUT15_CLR_CLR15_Pos) /*!< SCT OUT15_CLR: CLR15 Mask */ + + +/* ================================================================================ */ +/* ================ struct 'GPDMA' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- GPDMA_INTSTAT ------------------------------- */ +#define GPDMA_INTSTAT_INTSTAT0_Pos 0 /*!< GPDMA INTSTAT: INTSTAT0 Position */ +#define GPDMA_INTSTAT_INTSTAT0_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT0_Pos) /*!< GPDMA INTSTAT: INTSTAT0 Mask */ +#define GPDMA_INTSTAT_INTSTAT1_Pos 1 /*!< GPDMA INTSTAT: INTSTAT1 Position */ +#define GPDMA_INTSTAT_INTSTAT1_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT1_Pos) /*!< GPDMA INTSTAT: INTSTAT1 Mask */ +#define GPDMA_INTSTAT_INTSTAT2_Pos 2 /*!< GPDMA INTSTAT: INTSTAT2 Position */ +#define GPDMA_INTSTAT_INTSTAT2_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT2_Pos) /*!< GPDMA INTSTAT: INTSTAT2 Mask */ +#define GPDMA_INTSTAT_INTSTAT3_Pos 3 /*!< GPDMA INTSTAT: INTSTAT3 Position */ +#define GPDMA_INTSTAT_INTSTAT3_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT3_Pos) /*!< GPDMA INTSTAT: INTSTAT3 Mask */ +#define GPDMA_INTSTAT_INTSTAT4_Pos 4 /*!< GPDMA INTSTAT: INTSTAT4 Position */ +#define GPDMA_INTSTAT_INTSTAT4_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT4_Pos) /*!< GPDMA INTSTAT: INTSTAT4 Mask */ +#define GPDMA_INTSTAT_INTSTAT5_Pos 5 /*!< GPDMA INTSTAT: INTSTAT5 Position */ +#define GPDMA_INTSTAT_INTSTAT5_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT5_Pos) /*!< GPDMA INTSTAT: INTSTAT5 Mask */ +#define GPDMA_INTSTAT_INTSTAT6_Pos 6 /*!< GPDMA INTSTAT: INTSTAT6 Position */ +#define GPDMA_INTSTAT_INTSTAT6_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT6_Pos) /*!< GPDMA INTSTAT: INTSTAT6 Mask */ +#define GPDMA_INTSTAT_INTSTAT7_Pos 7 /*!< GPDMA INTSTAT: INTSTAT7 Position */ +#define GPDMA_INTSTAT_INTSTAT7_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT7_Pos) /*!< GPDMA INTSTAT: INTSTAT7 Mask */ + +/* ------------------------------- GPDMA_INTTCSTAT ------------------------------ */ +#define GPDMA_INTTCSTAT_INTTCSTAT0_Pos 0 /*!< GPDMA INTTCSTAT: INTTCSTAT0 Position */ +#define GPDMA_INTTCSTAT_INTTCSTAT0_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT0_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT0 Mask */ +#define GPDMA_INTTCSTAT_INTTCSTAT1_Pos 1 /*!< GPDMA INTTCSTAT: INTTCSTAT1 Position */ +#define GPDMA_INTTCSTAT_INTTCSTAT1_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT1_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT1 Mask */ +#define GPDMA_INTTCSTAT_INTTCSTAT2_Pos 2 /*!< GPDMA INTTCSTAT: INTTCSTAT2 Position */ +#define GPDMA_INTTCSTAT_INTTCSTAT2_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT2_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT2 Mask */ +#define GPDMA_INTTCSTAT_INTTCSTAT3_Pos 3 /*!< GPDMA INTTCSTAT: INTTCSTAT3 Position */ +#define GPDMA_INTTCSTAT_INTTCSTAT3_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT3_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT3 Mask */ +#define GPDMA_INTTCSTAT_INTTCSTAT4_Pos 4 /*!< GPDMA INTTCSTAT: INTTCSTAT4 Position */ +#define GPDMA_INTTCSTAT_INTTCSTAT4_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT4_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT4 Mask */ +#define GPDMA_INTTCSTAT_INTTCSTAT5_Pos 5 /*!< GPDMA INTTCSTAT: INTTCSTAT5 Position */ +#define GPDMA_INTTCSTAT_INTTCSTAT5_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT5_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT5 Mask */ +#define GPDMA_INTTCSTAT_INTTCSTAT6_Pos 6 /*!< GPDMA INTTCSTAT: INTTCSTAT6 Position */ +#define GPDMA_INTTCSTAT_INTTCSTAT6_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT6_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT6 Mask */ +#define GPDMA_INTTCSTAT_INTTCSTAT7_Pos 7 /*!< GPDMA INTTCSTAT: INTTCSTAT7 Position */ +#define GPDMA_INTTCSTAT_INTTCSTAT7_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT7_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT7 Mask */ + +/* ------------------------------ GPDMA_INTTCCLEAR ------------------------------ */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos 0 /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Position */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Mask */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos 1 /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Position */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Mask */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos 2 /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Position */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Mask */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos 3 /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Position */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Mask */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos 4 /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Position */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Mask */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos 5 /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Position */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Mask */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos 6 /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Position */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Mask */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos 7 /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Position */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Mask */ + +/* ------------------------------ GPDMA_INTERRSTAT ------------------------------ */ +#define GPDMA_INTERRSTAT_INTERRSTAT0_Pos 0 /*!< GPDMA INTERRSTAT: INTERRSTAT0 Position */ +#define GPDMA_INTERRSTAT_INTERRSTAT0_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT0_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT0 Mask */ +#define GPDMA_INTERRSTAT_INTERRSTAT1_Pos 1 /*!< GPDMA INTERRSTAT: INTERRSTAT1 Position */ +#define GPDMA_INTERRSTAT_INTERRSTAT1_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT1_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT1 Mask */ +#define GPDMA_INTERRSTAT_INTERRSTAT2_Pos 2 /*!< GPDMA INTERRSTAT: INTERRSTAT2 Position */ +#define GPDMA_INTERRSTAT_INTERRSTAT2_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT2_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT2 Mask */ +#define GPDMA_INTERRSTAT_INTERRSTAT3_Pos 3 /*!< GPDMA INTERRSTAT: INTERRSTAT3 Position */ +#define GPDMA_INTERRSTAT_INTERRSTAT3_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT3_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT3 Mask */ +#define GPDMA_INTERRSTAT_INTERRSTAT4_Pos 4 /*!< GPDMA INTERRSTAT: INTERRSTAT4 Position */ +#define GPDMA_INTERRSTAT_INTERRSTAT4_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT4_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT4 Mask */ +#define GPDMA_INTERRSTAT_INTERRSTAT5_Pos 5 /*!< GPDMA INTERRSTAT: INTERRSTAT5 Position */ +#define GPDMA_INTERRSTAT_INTERRSTAT5_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT5_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT5 Mask */ +#define GPDMA_INTERRSTAT_INTERRSTAT6_Pos 6 /*!< GPDMA INTERRSTAT: INTERRSTAT6 Position */ +#define GPDMA_INTERRSTAT_INTERRSTAT6_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT6_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT6 Mask */ +#define GPDMA_INTERRSTAT_INTERRSTAT7_Pos 7 /*!< GPDMA INTERRSTAT: INTERRSTAT7 Position */ +#define GPDMA_INTERRSTAT_INTERRSTAT7_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT7_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT7 Mask */ + +/* ------------------------------- GPDMA_INTERRCLR ------------------------------ */ +#define GPDMA_INTERRCLR_INTERRCLR0_Pos 0 /*!< GPDMA INTERRCLR: INTERRCLR0 Position */ +#define GPDMA_INTERRCLR_INTERRCLR0_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR0_Pos) /*!< GPDMA INTERRCLR: INTERRCLR0 Mask */ +#define GPDMA_INTERRCLR_INTERRCLR1_Pos 1 /*!< GPDMA INTERRCLR: INTERRCLR1 Position */ +#define GPDMA_INTERRCLR_INTERRCLR1_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR1_Pos) /*!< GPDMA INTERRCLR: INTERRCLR1 Mask */ +#define GPDMA_INTERRCLR_INTERRCLR2_Pos 2 /*!< GPDMA INTERRCLR: INTERRCLR2 Position */ +#define GPDMA_INTERRCLR_INTERRCLR2_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR2_Pos) /*!< GPDMA INTERRCLR: INTERRCLR2 Mask */ +#define GPDMA_INTERRCLR_INTERRCLR3_Pos 3 /*!< GPDMA INTERRCLR: INTERRCLR3 Position */ +#define GPDMA_INTERRCLR_INTERRCLR3_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR3_Pos) /*!< GPDMA INTERRCLR: INTERRCLR3 Mask */ +#define GPDMA_INTERRCLR_INTERRCLR4_Pos 4 /*!< GPDMA INTERRCLR: INTERRCLR4 Position */ +#define GPDMA_INTERRCLR_INTERRCLR4_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR4_Pos) /*!< GPDMA INTERRCLR: INTERRCLR4 Mask */ +#define GPDMA_INTERRCLR_INTERRCLR5_Pos 5 /*!< GPDMA INTERRCLR: INTERRCLR5 Position */ +#define GPDMA_INTERRCLR_INTERRCLR5_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR5_Pos) /*!< GPDMA INTERRCLR: INTERRCLR5 Mask */ +#define GPDMA_INTERRCLR_INTERRCLR6_Pos 6 /*!< GPDMA INTERRCLR: INTERRCLR6 Position */ +#define GPDMA_INTERRCLR_INTERRCLR6_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR6_Pos) /*!< GPDMA INTERRCLR: INTERRCLR6 Mask */ +#define GPDMA_INTERRCLR_INTERRCLR7_Pos 7 /*!< GPDMA INTERRCLR: INTERRCLR7 Position */ +#define GPDMA_INTERRCLR_INTERRCLR7_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR7_Pos) /*!< GPDMA INTERRCLR: INTERRCLR7 Mask */ + +/* ----------------------------- GPDMA_RAWINTTCSTAT ----------------------------- */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos 0 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Position */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Mask */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos 1 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Position */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Mask */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos 2 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Position */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Mask */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos 3 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Position */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Mask */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos 4 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Position */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Mask */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos 5 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Position */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Mask */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos 6 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Position */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Mask */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos 7 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Position */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Mask */ + +/* ----------------------------- GPDMA_RAWINTERRSTAT ---------------------------- */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos 0 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Position */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Mask */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos 1 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Position */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Mask */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos 2 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Position */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Mask */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos 3 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Position */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Mask */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos 4 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Position */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Mask */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos 5 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Position */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Mask */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos 6 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Position */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Mask */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos 7 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Position */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Mask */ + +/* ------------------------------- GPDMA_ENBLDCHNS ------------------------------ */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos 0 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Position */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Mask */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos 1 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Position */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Mask */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos 2 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Position */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Mask */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos 3 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Position */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Mask */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos 4 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Position */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Mask */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos 5 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Position */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Mask */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos 6 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Position */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Mask */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos 7 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Position */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Mask */ + +/* ------------------------------- GPDMA_SOFTBREQ ------------------------------- */ +#define GPDMA_SOFTBREQ_SOFTBREQ0_Pos 0 /*!< GPDMA SOFTBREQ: SOFTBREQ0 Position */ +#define GPDMA_SOFTBREQ_SOFTBREQ0_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ0_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ0 Mask */ +#define GPDMA_SOFTBREQ_SOFTBREQ1_Pos 1 /*!< GPDMA SOFTBREQ: SOFTBREQ1 Position */ +#define GPDMA_SOFTBREQ_SOFTBREQ1_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ1_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ1 Mask */ +#define GPDMA_SOFTBREQ_SOFTBREQ2_Pos 2 /*!< GPDMA SOFTBREQ: SOFTBREQ2 Position */ +#define GPDMA_SOFTBREQ_SOFTBREQ2_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ2_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ2 Mask */ +#define GPDMA_SOFTBREQ_SOFTBREQ3_Pos 3 /*!< GPDMA SOFTBREQ: SOFTBREQ3 Position */ +#define GPDMA_SOFTBREQ_SOFTBREQ3_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ3_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ3 Mask */ +#define GPDMA_SOFTBREQ_SOFTBREQ4_Pos 4 /*!< GPDMA SOFTBREQ: SOFTBREQ4 Position */ +#define GPDMA_SOFTBREQ_SOFTBREQ4_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ4_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ4 Mask */ +#define GPDMA_SOFTBREQ_SOFTBREQ5_Pos 5 /*!< GPDMA SOFTBREQ: SOFTBREQ5 Position */ +#define GPDMA_SOFTBREQ_SOFTBREQ5_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ5_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ5 Mask */ +#define GPDMA_SOFTBREQ_SOFTBREQ6_Pos 6 /*!< GPDMA SOFTBREQ: SOFTBREQ6 Position */ +#define GPDMA_SOFTBREQ_SOFTBREQ6_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ6_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ6 Mask */ +#define GPDMA_SOFTBREQ_SOFTBREQ7_Pos 7 /*!< GPDMA SOFTBREQ: SOFTBREQ7 Position */ +#define GPDMA_SOFTBREQ_SOFTBREQ7_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ7_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ7 Mask */ +#define GPDMA_SOFTBREQ_SOFTBREQ8_Pos 8 /*!< GPDMA SOFTBREQ: SOFTBREQ8 Position */ +#define GPDMA_SOFTBREQ_SOFTBREQ8_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ8_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ8 Mask */ +#define GPDMA_SOFTBREQ_SOFTBREQ9_Pos 9 /*!< GPDMA SOFTBREQ: SOFTBREQ9 Position */ +#define GPDMA_SOFTBREQ_SOFTBREQ9_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ9_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ9 Mask */ +#define GPDMA_SOFTBREQ_SOFTBREQ10_Pos 10 /*!< GPDMA SOFTBREQ: SOFTBREQ10 Position */ +#define GPDMA_SOFTBREQ_SOFTBREQ10_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ10_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ10 Mask */ +#define GPDMA_SOFTBREQ_SOFTBREQ11_Pos 11 /*!< GPDMA SOFTBREQ: SOFTBREQ11 Position */ +#define GPDMA_SOFTBREQ_SOFTBREQ11_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ11_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ11 Mask */ +#define GPDMA_SOFTBREQ_SOFTBREQ12_Pos 12 /*!< GPDMA SOFTBREQ: SOFTBREQ12 Position */ +#define GPDMA_SOFTBREQ_SOFTBREQ12_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ12_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ12 Mask */ +#define GPDMA_SOFTBREQ_SOFTBREQ13_Pos 13 /*!< GPDMA SOFTBREQ: SOFTBREQ13 Position */ +#define GPDMA_SOFTBREQ_SOFTBREQ13_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ13_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ13 Mask */ +#define GPDMA_SOFTBREQ_SOFTBREQ14_Pos 14 /*!< GPDMA SOFTBREQ: SOFTBREQ14 Position */ +#define GPDMA_SOFTBREQ_SOFTBREQ14_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ14_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ14 Mask */ +#define GPDMA_SOFTBREQ_SOFTBREQ15_Pos 15 /*!< GPDMA SOFTBREQ: SOFTBREQ15 Position */ +#define GPDMA_SOFTBREQ_SOFTBREQ15_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ15_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ15 Mask */ + +/* ------------------------------- GPDMA_SOFTSREQ ------------------------------- */ +#define GPDMA_SOFTSREQ_SOFTSREQ0_Pos 0 /*!< GPDMA SOFTSREQ: SOFTSREQ0 Position */ +#define GPDMA_SOFTSREQ_SOFTSREQ0_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ0_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ0 Mask */ +#define GPDMA_SOFTSREQ_SOFTSREQ1_Pos 1 /*!< GPDMA SOFTSREQ: SOFTSREQ1 Position */ +#define GPDMA_SOFTSREQ_SOFTSREQ1_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ1_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ1 Mask */ +#define GPDMA_SOFTSREQ_SOFTSREQ2_Pos 2 /*!< GPDMA SOFTSREQ: SOFTSREQ2 Position */ +#define GPDMA_SOFTSREQ_SOFTSREQ2_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ2_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ2 Mask */ +#define GPDMA_SOFTSREQ_SOFTSREQ3_Pos 3 /*!< GPDMA SOFTSREQ: SOFTSREQ3 Position */ +#define GPDMA_SOFTSREQ_SOFTSREQ3_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ3_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ3 Mask */ +#define GPDMA_SOFTSREQ_SOFTSREQ4_Pos 4 /*!< GPDMA SOFTSREQ: SOFTSREQ4 Position */ +#define GPDMA_SOFTSREQ_SOFTSREQ4_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ4_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ4 Mask */ +#define GPDMA_SOFTSREQ_SOFTSREQ5_Pos 5 /*!< GPDMA SOFTSREQ: SOFTSREQ5 Position */ +#define GPDMA_SOFTSREQ_SOFTSREQ5_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ5_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ5 Mask */ +#define GPDMA_SOFTSREQ_SOFTSREQ6_Pos 6 /*!< GPDMA SOFTSREQ: SOFTSREQ6 Position */ +#define GPDMA_SOFTSREQ_SOFTSREQ6_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ6_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ6 Mask */ +#define GPDMA_SOFTSREQ_SOFTSREQ7_Pos 7 /*!< GPDMA SOFTSREQ: SOFTSREQ7 Position */ +#define GPDMA_SOFTSREQ_SOFTSREQ7_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ7_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ7 Mask */ +#define GPDMA_SOFTSREQ_SOFTSREQ8_Pos 8 /*!< GPDMA SOFTSREQ: SOFTSREQ8 Position */ +#define GPDMA_SOFTSREQ_SOFTSREQ8_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ8_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ8 Mask */ +#define GPDMA_SOFTSREQ_SOFTSREQ9_Pos 9 /*!< GPDMA SOFTSREQ: SOFTSREQ9 Position */ +#define GPDMA_SOFTSREQ_SOFTSREQ9_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ9_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ9 Mask */ +#define GPDMA_SOFTSREQ_SOFTSREQ10_Pos 10 /*!< GPDMA SOFTSREQ: SOFTSREQ10 Position */ +#define GPDMA_SOFTSREQ_SOFTSREQ10_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ10_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ10 Mask */ +#define GPDMA_SOFTSREQ_SOFTSREQ11_Pos 11 /*!< GPDMA SOFTSREQ: SOFTSREQ11 Position */ +#define GPDMA_SOFTSREQ_SOFTSREQ11_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ11_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ11 Mask */ +#define GPDMA_SOFTSREQ_SOFTSREQ12_Pos 12 /*!< GPDMA SOFTSREQ: SOFTSREQ12 Position */ +#define GPDMA_SOFTSREQ_SOFTSREQ12_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ12_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ12 Mask */ +#define GPDMA_SOFTSREQ_SOFTSREQ13_Pos 13 /*!< GPDMA SOFTSREQ: SOFTSREQ13 Position */ +#define GPDMA_SOFTSREQ_SOFTSREQ13_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ13_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ13 Mask */ +#define GPDMA_SOFTSREQ_SOFTSREQ14_Pos 14 /*!< GPDMA SOFTSREQ: SOFTSREQ14 Position */ +#define GPDMA_SOFTSREQ_SOFTSREQ14_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ14_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ14 Mask */ +#define GPDMA_SOFTSREQ_SOFTSREQ15_Pos 15 /*!< GPDMA SOFTSREQ: SOFTSREQ15 Position */ +#define GPDMA_SOFTSREQ_SOFTSREQ15_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ15_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ15 Mask */ + +/* ------------------------------- GPDMA_SOFTLBREQ ------------------------------ */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos 0 /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Position */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Mask */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos 1 /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Position */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Mask */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos 2 /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Position */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Mask */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos 3 /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Position */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Mask */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos 4 /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Position */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Mask */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos 5 /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Position */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Mask */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos 6 /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Position */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Mask */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos 7 /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Position */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Mask */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos 8 /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Position */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Mask */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos 9 /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Position */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Mask */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos 10 /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Position */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Mask */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos 11 /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Position */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Mask */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos 12 /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Position */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Mask */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos 13 /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Position */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Mask */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos 14 /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Position */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Mask */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos 15 /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Position */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Mask */ + +/* ------------------------------- GPDMA_SOFTLSREQ ------------------------------ */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos 0 /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Position */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Mask */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos 1 /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Position */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Mask */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos 2 /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Position */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Mask */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos 3 /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Position */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Mask */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos 4 /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Position */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Mask */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos 5 /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Position */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Mask */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos 6 /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Position */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Mask */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos 7 /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Position */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Mask */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos 8 /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Position */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Mask */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos 9 /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Position */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Mask */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos 10 /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Position */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Mask */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos 11 /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Position */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Mask */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos 12 /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Position */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Mask */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos 13 /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Position */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Mask */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos 14 /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Position */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Mask */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos 15 /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Position */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Mask */ + +/* -------------------------------- GPDMA_CONFIG -------------------------------- */ +#define GPDMA_CONFIG_E_Pos 0 /*!< GPDMA CONFIG: E Position */ +#define GPDMA_CONFIG_E_Msk (0x01UL << GPDMA_CONFIG_E_Pos) /*!< GPDMA CONFIG: E Mask */ +#define GPDMA_CONFIG_M0_Pos 1 /*!< GPDMA CONFIG: M0 Position */ +#define GPDMA_CONFIG_M0_Msk (0x01UL << GPDMA_CONFIG_M0_Pos) /*!< GPDMA CONFIG: M0 Mask */ +#define GPDMA_CONFIG_M1_Pos 2 /*!< GPDMA CONFIG: M1 Position */ +#define GPDMA_CONFIG_M1_Msk (0x01UL << GPDMA_CONFIG_M1_Pos) /*!< GPDMA CONFIG: M1 Mask */ + +/* --------------------------------- GPDMA_SYNC --------------------------------- */ +#define GPDMA_SYNC_DMACSYNC0_Pos 0 /*!< GPDMA SYNC: DMACSYNC0 Position */ +#define GPDMA_SYNC_DMACSYNC0_Msk (0x01UL << GPDMA_SYNC_DMACSYNC0_Pos) /*!< GPDMA SYNC: DMACSYNC0 Mask */ +#define GPDMA_SYNC_DMACSYNC1_Pos 1 /*!< GPDMA SYNC: DMACSYNC1 Position */ +#define GPDMA_SYNC_DMACSYNC1_Msk (0x01UL << GPDMA_SYNC_DMACSYNC1_Pos) /*!< GPDMA SYNC: DMACSYNC1 Mask */ +#define GPDMA_SYNC_DMACSYNC2_Pos 2 /*!< GPDMA SYNC: DMACSYNC2 Position */ +#define GPDMA_SYNC_DMACSYNC2_Msk (0x01UL << GPDMA_SYNC_DMACSYNC2_Pos) /*!< GPDMA SYNC: DMACSYNC2 Mask */ +#define GPDMA_SYNC_DMACSYNC3_Pos 3 /*!< GPDMA SYNC: DMACSYNC3 Position */ +#define GPDMA_SYNC_DMACSYNC3_Msk (0x01UL << GPDMA_SYNC_DMACSYNC3_Pos) /*!< GPDMA SYNC: DMACSYNC3 Mask */ +#define GPDMA_SYNC_DMACSYNC4_Pos 4 /*!< GPDMA SYNC: DMACSYNC4 Position */ +#define GPDMA_SYNC_DMACSYNC4_Msk (0x01UL << GPDMA_SYNC_DMACSYNC4_Pos) /*!< GPDMA SYNC: DMACSYNC4 Mask */ +#define GPDMA_SYNC_DMACSYNC5_Pos 5 /*!< GPDMA SYNC: DMACSYNC5 Position */ +#define GPDMA_SYNC_DMACSYNC5_Msk (0x01UL << GPDMA_SYNC_DMACSYNC5_Pos) /*!< GPDMA SYNC: DMACSYNC5 Mask */ +#define GPDMA_SYNC_DMACSYNC6_Pos 6 /*!< GPDMA SYNC: DMACSYNC6 Position */ +#define GPDMA_SYNC_DMACSYNC6_Msk (0x01UL << GPDMA_SYNC_DMACSYNC6_Pos) /*!< GPDMA SYNC: DMACSYNC6 Mask */ +#define GPDMA_SYNC_DMACSYNC7_Pos 7 /*!< GPDMA SYNC: DMACSYNC7 Position */ +#define GPDMA_SYNC_DMACSYNC7_Msk (0x01UL << GPDMA_SYNC_DMACSYNC7_Pos) /*!< GPDMA SYNC: DMACSYNC7 Mask */ +#define GPDMA_SYNC_DMACSYNC8_Pos 8 /*!< GPDMA SYNC: DMACSYNC8 Position */ +#define GPDMA_SYNC_DMACSYNC8_Msk (0x01UL << GPDMA_SYNC_DMACSYNC8_Pos) /*!< GPDMA SYNC: DMACSYNC8 Mask */ +#define GPDMA_SYNC_DMACSYNC9_Pos 9 /*!< GPDMA SYNC: DMACSYNC9 Position */ +#define GPDMA_SYNC_DMACSYNC9_Msk (0x01UL << GPDMA_SYNC_DMACSYNC9_Pos) /*!< GPDMA SYNC: DMACSYNC9 Mask */ +#define GPDMA_SYNC_DMACSYNC10_Pos 10 /*!< GPDMA SYNC: DMACSYNC10 Position */ +#define GPDMA_SYNC_DMACSYNC10_Msk (0x01UL << GPDMA_SYNC_DMACSYNC10_Pos) /*!< GPDMA SYNC: DMACSYNC10 Mask */ +#define GPDMA_SYNC_DMACSYNC11_Pos 11 /*!< GPDMA SYNC: DMACSYNC11 Position */ +#define GPDMA_SYNC_DMACSYNC11_Msk (0x01UL << GPDMA_SYNC_DMACSYNC11_Pos) /*!< GPDMA SYNC: DMACSYNC11 Mask */ +#define GPDMA_SYNC_DMACSYNC12_Pos 12 /*!< GPDMA SYNC: DMACSYNC12 Position */ +#define GPDMA_SYNC_DMACSYNC12_Msk (0x01UL << GPDMA_SYNC_DMACSYNC12_Pos) /*!< GPDMA SYNC: DMACSYNC12 Mask */ +#define GPDMA_SYNC_DMACSYNC13_Pos 13 /*!< GPDMA SYNC: DMACSYNC13 Position */ +#define GPDMA_SYNC_DMACSYNC13_Msk (0x01UL << GPDMA_SYNC_DMACSYNC13_Pos) /*!< GPDMA SYNC: DMACSYNC13 Mask */ +#define GPDMA_SYNC_DMACSYNC14_Pos 14 /*!< GPDMA SYNC: DMACSYNC14 Position */ +#define GPDMA_SYNC_DMACSYNC14_Msk (0x01UL << GPDMA_SYNC_DMACSYNC14_Pos) /*!< GPDMA SYNC: DMACSYNC14 Mask */ +#define GPDMA_SYNC_DMACSYNC15_Pos 15 /*!< GPDMA SYNC: DMACSYNC15 Position */ +#define GPDMA_SYNC_DMACSYNC15_Msk (0x01UL << GPDMA_SYNC_DMACSYNC15_Pos) /*!< GPDMA SYNC: DMACSYNC15 Mask */ + +/* ------------------------------- GPDMA_C0SRCADDR ------------------------------ */ +#define GPDMA_C0SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C0SRCADDR: SRCADDR Position */ +#define GPDMA_C0SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C0SRCADDR_SRCADDR_Pos) /*!< GPDMA C0SRCADDR: SRCADDR Mask */ + +/* ------------------------------ GPDMA_C0DESTADDR ------------------------------ */ +#define GPDMA_C0DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C0DESTADDR: DESTADDR Position */ +#define GPDMA_C0DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C0DESTADDR_DESTADDR_Pos) /*!< GPDMA C0DESTADDR: DESTADDR Mask */ + +/* --------------------------------- GPDMA_C0LLI -------------------------------- */ +#define GPDMA_C0LLI_LM_Pos 0 /*!< GPDMA C0LLI: LM Position */ +#define GPDMA_C0LLI_LM_Msk (0x01UL << GPDMA_C0LLI_LM_Pos) /*!< GPDMA C0LLI: LM Mask */ +#define GPDMA_C0LLI_R_Pos 1 /*!< GPDMA C0LLI: R Position */ +#define GPDMA_C0LLI_R_Msk (0x01UL << GPDMA_C0LLI_R_Pos) /*!< GPDMA C0LLI: R Mask */ +#define GPDMA_C0LLI_LLI_Pos 2 /*!< GPDMA C0LLI: LLI Position */ +#define GPDMA_C0LLI_LLI_Msk (0x3fffffffUL << GPDMA_C0LLI_LLI_Pos) /*!< GPDMA C0LLI: LLI Mask */ + +/* ------------------------------- GPDMA_C0CONTROL ------------------------------ */ +#define GPDMA_C0CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C0CONTROL: TRANSFERSIZE Position */ +#define GPDMA_C0CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C0CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C0CONTROL: TRANSFERSIZE Mask */ +#define GPDMA_C0CONTROL_SBSIZE_Pos 12 /*!< GPDMA C0CONTROL: SBSIZE Position */ +#define GPDMA_C0CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C0CONTROL_SBSIZE_Pos) /*!< GPDMA C0CONTROL: SBSIZE Mask */ +#define GPDMA_C0CONTROL_DBSIZE_Pos 15 /*!< GPDMA C0CONTROL: DBSIZE Position */ +#define GPDMA_C0CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C0CONTROL_DBSIZE_Pos) /*!< GPDMA C0CONTROL: DBSIZE Mask */ +#define GPDMA_C0CONTROL_SWIDTH_Pos 18 /*!< GPDMA C0CONTROL: SWIDTH Position */ +#define GPDMA_C0CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C0CONTROL_SWIDTH_Pos) /*!< GPDMA C0CONTROL: SWIDTH Mask */ +#define GPDMA_C0CONTROL_DWIDTH_Pos 21 /*!< GPDMA C0CONTROL: DWIDTH Position */ +#define GPDMA_C0CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C0CONTROL_DWIDTH_Pos) /*!< GPDMA C0CONTROL: DWIDTH Mask */ +#define GPDMA_C0CONTROL_S_Pos 24 /*!< GPDMA C0CONTROL: S Position */ +#define GPDMA_C0CONTROL_S_Msk (0x01UL << GPDMA_C0CONTROL_S_Pos) /*!< GPDMA C0CONTROL: S Mask */ +#define GPDMA_C0CONTROL_D_Pos 25 /*!< GPDMA C0CONTROL: D Position */ +#define GPDMA_C0CONTROL_D_Msk (0x01UL << GPDMA_C0CONTROL_D_Pos) /*!< GPDMA C0CONTROL: D Mask */ +#define GPDMA_C0CONTROL_SI_Pos 26 /*!< GPDMA C0CONTROL: SI Position */ +#define GPDMA_C0CONTROL_SI_Msk (0x01UL << GPDMA_C0CONTROL_SI_Pos) /*!< GPDMA C0CONTROL: SI Mask */ +#define GPDMA_C0CONTROL_DI_Pos 27 /*!< GPDMA C0CONTROL: DI Position */ +#define GPDMA_C0CONTROL_DI_Msk (0x01UL << GPDMA_C0CONTROL_DI_Pos) /*!< GPDMA C0CONTROL: DI Mask */ +#define GPDMA_C0CONTROL_PROT1_Pos 28 /*!< GPDMA C0CONTROL: PROT1 Position */ +#define GPDMA_C0CONTROL_PROT1_Msk (0x01UL << GPDMA_C0CONTROL_PROT1_Pos) /*!< GPDMA C0CONTROL: PROT1 Mask */ +#define GPDMA_C0CONTROL_PROT2_Pos 29 /*!< GPDMA C0CONTROL: PROT2 Position */ +#define GPDMA_C0CONTROL_PROT2_Msk (0x01UL << GPDMA_C0CONTROL_PROT2_Pos) /*!< GPDMA C0CONTROL: PROT2 Mask */ +#define GPDMA_C0CONTROL_PROT3_Pos 30 /*!< GPDMA C0CONTROL: PROT3 Position */ +#define GPDMA_C0CONTROL_PROT3_Msk (0x01UL << GPDMA_C0CONTROL_PROT3_Pos) /*!< GPDMA C0CONTROL: PROT3 Mask */ +#define GPDMA_C0CONTROL_I_Pos 31 /*!< GPDMA C0CONTROL: I Position */ +#define GPDMA_C0CONTROL_I_Msk (0x01UL << GPDMA_C0CONTROL_I_Pos) /*!< GPDMA C0CONTROL: I Mask */ + +/* ------------------------------- GPDMA_C0CONFIG ------------------------------- */ +#define GPDMA_C0CONFIG_E_Pos 0 /*!< GPDMA C0CONFIG: E Position */ +#define GPDMA_C0CONFIG_E_Msk (0x01UL << GPDMA_C0CONFIG_E_Pos) /*!< GPDMA C0CONFIG: E Mask */ +#define GPDMA_C0CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C0CONFIG: SRCPERIPHERAL Position */ +#define GPDMA_C0CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C0CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C0CONFIG: SRCPERIPHERAL Mask */ +#define GPDMA_C0CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C0CONFIG: DESTPERIPHERAL Position */ +#define GPDMA_C0CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C0CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C0CONFIG: DESTPERIPHERAL Mask */ +#define GPDMA_C0CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C0CONFIG: FLOWCNTRL Position */ +#define GPDMA_C0CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C0CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C0CONFIG: FLOWCNTRL Mask */ +#define GPDMA_C0CONFIG_IE_Pos 14 /*!< GPDMA C0CONFIG: IE Position */ +#define GPDMA_C0CONFIG_IE_Msk (0x01UL << GPDMA_C0CONFIG_IE_Pos) /*!< GPDMA C0CONFIG: IE Mask */ +#define GPDMA_C0CONFIG_ITC_Pos 15 /*!< GPDMA C0CONFIG: ITC Position */ +#define GPDMA_C0CONFIG_ITC_Msk (0x01UL << GPDMA_C0CONFIG_ITC_Pos) /*!< GPDMA C0CONFIG: ITC Mask */ +#define GPDMA_C0CONFIG_L_Pos 16 /*!< GPDMA C0CONFIG: L Position */ +#define GPDMA_C0CONFIG_L_Msk (0x01UL << GPDMA_C0CONFIG_L_Pos) /*!< GPDMA C0CONFIG: L Mask */ +#define GPDMA_C0CONFIG_A_Pos 17 /*!< GPDMA C0CONFIG: A Position */ +#define GPDMA_C0CONFIG_A_Msk (0x01UL << GPDMA_C0CONFIG_A_Pos) /*!< GPDMA C0CONFIG: A Mask */ +#define GPDMA_C0CONFIG_H_Pos 18 /*!< GPDMA C0CONFIG: H Position */ +#define GPDMA_C0CONFIG_H_Msk (0x01UL << GPDMA_C0CONFIG_H_Pos) /*!< GPDMA C0CONFIG: H Mask */ + +/* ------------------------------- GPDMA_C1SRCADDR ------------------------------ */ +#define GPDMA_C1SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C1SRCADDR: SRCADDR Position */ +#define GPDMA_C1SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C1SRCADDR_SRCADDR_Pos) /*!< GPDMA C1SRCADDR: SRCADDR Mask */ + +/* ------------------------------ GPDMA_C1DESTADDR ------------------------------ */ +#define GPDMA_C1DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C1DESTADDR: DESTADDR Position */ +#define GPDMA_C1DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C1DESTADDR_DESTADDR_Pos) /*!< GPDMA C1DESTADDR: DESTADDR Mask */ + +/* --------------------------------- GPDMA_C1LLI -------------------------------- */ +#define GPDMA_C1LLI_LM_Pos 0 /*!< GPDMA C1LLI: LM Position */ +#define GPDMA_C1LLI_LM_Msk (0x01UL << GPDMA_C1LLI_LM_Pos) /*!< GPDMA C1LLI: LM Mask */ +#define GPDMA_C1LLI_R_Pos 1 /*!< GPDMA C1LLI: R Position */ +#define GPDMA_C1LLI_R_Msk (0x01UL << GPDMA_C1LLI_R_Pos) /*!< GPDMA C1LLI: R Mask */ +#define GPDMA_C1LLI_LLI_Pos 2 /*!< GPDMA C1LLI: LLI Position */ +#define GPDMA_C1LLI_LLI_Msk (0x3fffffffUL << GPDMA_C1LLI_LLI_Pos) /*!< GPDMA C1LLI: LLI Mask */ + +/* ------------------------------- GPDMA_C1CONTROL ------------------------------ */ +#define GPDMA_C1CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C1CONTROL: TRANSFERSIZE Position */ +#define GPDMA_C1CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C1CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C1CONTROL: TRANSFERSIZE Mask */ +#define GPDMA_C1CONTROL_SBSIZE_Pos 12 /*!< GPDMA C1CONTROL: SBSIZE Position */ +#define GPDMA_C1CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C1CONTROL_SBSIZE_Pos) /*!< GPDMA C1CONTROL: SBSIZE Mask */ +#define GPDMA_C1CONTROL_DBSIZE_Pos 15 /*!< GPDMA C1CONTROL: DBSIZE Position */ +#define GPDMA_C1CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C1CONTROL_DBSIZE_Pos) /*!< GPDMA C1CONTROL: DBSIZE Mask */ +#define GPDMA_C1CONTROL_SWIDTH_Pos 18 /*!< GPDMA C1CONTROL: SWIDTH Position */ +#define GPDMA_C1CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C1CONTROL_SWIDTH_Pos) /*!< GPDMA C1CONTROL: SWIDTH Mask */ +#define GPDMA_C1CONTROL_DWIDTH_Pos 21 /*!< GPDMA C1CONTROL: DWIDTH Position */ +#define GPDMA_C1CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C1CONTROL_DWIDTH_Pos) /*!< GPDMA C1CONTROL: DWIDTH Mask */ +#define GPDMA_C1CONTROL_S_Pos 24 /*!< GPDMA C1CONTROL: S Position */ +#define GPDMA_C1CONTROL_S_Msk (0x01UL << GPDMA_C1CONTROL_S_Pos) /*!< GPDMA C1CONTROL: S Mask */ +#define GPDMA_C1CONTROL_D_Pos 25 /*!< GPDMA C1CONTROL: D Position */ +#define GPDMA_C1CONTROL_D_Msk (0x01UL << GPDMA_C1CONTROL_D_Pos) /*!< GPDMA C1CONTROL: D Mask */ +#define GPDMA_C1CONTROL_SI_Pos 26 /*!< GPDMA C1CONTROL: SI Position */ +#define GPDMA_C1CONTROL_SI_Msk (0x01UL << GPDMA_C1CONTROL_SI_Pos) /*!< GPDMA C1CONTROL: SI Mask */ +#define GPDMA_C1CONTROL_DI_Pos 27 /*!< GPDMA C1CONTROL: DI Position */ +#define GPDMA_C1CONTROL_DI_Msk (0x01UL << GPDMA_C1CONTROL_DI_Pos) /*!< GPDMA C1CONTROL: DI Mask */ +#define GPDMA_C1CONTROL_PROT1_Pos 28 /*!< GPDMA C1CONTROL: PROT1 Position */ +#define GPDMA_C1CONTROL_PROT1_Msk (0x01UL << GPDMA_C1CONTROL_PROT1_Pos) /*!< GPDMA C1CONTROL: PROT1 Mask */ +#define GPDMA_C1CONTROL_PROT2_Pos 29 /*!< GPDMA C1CONTROL: PROT2 Position */ +#define GPDMA_C1CONTROL_PROT2_Msk (0x01UL << GPDMA_C1CONTROL_PROT2_Pos) /*!< GPDMA C1CONTROL: PROT2 Mask */ +#define GPDMA_C1CONTROL_PROT3_Pos 30 /*!< GPDMA C1CONTROL: PROT3 Position */ +#define GPDMA_C1CONTROL_PROT3_Msk (0x01UL << GPDMA_C1CONTROL_PROT3_Pos) /*!< GPDMA C1CONTROL: PROT3 Mask */ +#define GPDMA_C1CONTROL_I_Pos 31 /*!< GPDMA C1CONTROL: I Position */ +#define GPDMA_C1CONTROL_I_Msk (0x01UL << GPDMA_C1CONTROL_I_Pos) /*!< GPDMA C1CONTROL: I Mask */ + +/* ------------------------------- GPDMA_C1CONFIG ------------------------------- */ +#define GPDMA_C1CONFIG_E_Pos 0 /*!< GPDMA C1CONFIG: E Position */ +#define GPDMA_C1CONFIG_E_Msk (0x01UL << GPDMA_C1CONFIG_E_Pos) /*!< GPDMA C1CONFIG: E Mask */ +#define GPDMA_C1CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C1CONFIG: SRCPERIPHERAL Position */ +#define GPDMA_C1CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C1CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C1CONFIG: SRCPERIPHERAL Mask */ +#define GPDMA_C1CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C1CONFIG: DESTPERIPHERAL Position */ +#define GPDMA_C1CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C1CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C1CONFIG: DESTPERIPHERAL Mask */ +#define GPDMA_C1CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C1CONFIG: FLOWCNTRL Position */ +#define GPDMA_C1CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C1CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C1CONFIG: FLOWCNTRL Mask */ +#define GPDMA_C1CONFIG_IE_Pos 14 /*!< GPDMA C1CONFIG: IE Position */ +#define GPDMA_C1CONFIG_IE_Msk (0x01UL << GPDMA_C1CONFIG_IE_Pos) /*!< GPDMA C1CONFIG: IE Mask */ +#define GPDMA_C1CONFIG_ITC_Pos 15 /*!< GPDMA C1CONFIG: ITC Position */ +#define GPDMA_C1CONFIG_ITC_Msk (0x01UL << GPDMA_C1CONFIG_ITC_Pos) /*!< GPDMA C1CONFIG: ITC Mask */ +#define GPDMA_C1CONFIG_L_Pos 16 /*!< GPDMA C1CONFIG: L Position */ +#define GPDMA_C1CONFIG_L_Msk (0x01UL << GPDMA_C1CONFIG_L_Pos) /*!< GPDMA C1CONFIG: L Mask */ +#define GPDMA_C1CONFIG_A_Pos 17 /*!< GPDMA C1CONFIG: A Position */ +#define GPDMA_C1CONFIG_A_Msk (0x01UL << GPDMA_C1CONFIG_A_Pos) /*!< GPDMA C1CONFIG: A Mask */ +#define GPDMA_C1CONFIG_H_Pos 18 /*!< GPDMA C1CONFIG: H Position */ +#define GPDMA_C1CONFIG_H_Msk (0x01UL << GPDMA_C1CONFIG_H_Pos) /*!< GPDMA C1CONFIG: H Mask */ + +/* ------------------------------- GPDMA_C2SRCADDR ------------------------------ */ +#define GPDMA_C2SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C2SRCADDR: SRCADDR Position */ +#define GPDMA_C2SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C2SRCADDR_SRCADDR_Pos) /*!< GPDMA C2SRCADDR: SRCADDR Mask */ + +/* ------------------------------ GPDMA_C2DESTADDR ------------------------------ */ +#define GPDMA_C2DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C2DESTADDR: DESTADDR Position */ +#define GPDMA_C2DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C2DESTADDR_DESTADDR_Pos) /*!< GPDMA C2DESTADDR: DESTADDR Mask */ + +/* --------------------------------- GPDMA_C2LLI -------------------------------- */ +#define GPDMA_C2LLI_LM_Pos 0 /*!< GPDMA C2LLI: LM Position */ +#define GPDMA_C2LLI_LM_Msk (0x01UL << GPDMA_C2LLI_LM_Pos) /*!< GPDMA C2LLI: LM Mask */ +#define GPDMA_C2LLI_R_Pos 1 /*!< GPDMA C2LLI: R Position */ +#define GPDMA_C2LLI_R_Msk (0x01UL << GPDMA_C2LLI_R_Pos) /*!< GPDMA C2LLI: R Mask */ +#define GPDMA_C2LLI_LLI_Pos 2 /*!< GPDMA C2LLI: LLI Position */ +#define GPDMA_C2LLI_LLI_Msk (0x3fffffffUL << GPDMA_C2LLI_LLI_Pos) /*!< GPDMA C2LLI: LLI Mask */ + +/* ------------------------------- GPDMA_C2CONTROL ------------------------------ */ +#define GPDMA_C2CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C2CONTROL: TRANSFERSIZE Position */ +#define GPDMA_C2CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C2CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C2CONTROL: TRANSFERSIZE Mask */ +#define GPDMA_C2CONTROL_SBSIZE_Pos 12 /*!< GPDMA C2CONTROL: SBSIZE Position */ +#define GPDMA_C2CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C2CONTROL_SBSIZE_Pos) /*!< GPDMA C2CONTROL: SBSIZE Mask */ +#define GPDMA_C2CONTROL_DBSIZE_Pos 15 /*!< GPDMA C2CONTROL: DBSIZE Position */ +#define GPDMA_C2CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C2CONTROL_DBSIZE_Pos) /*!< GPDMA C2CONTROL: DBSIZE Mask */ +#define GPDMA_C2CONTROL_SWIDTH_Pos 18 /*!< GPDMA C2CONTROL: SWIDTH Position */ +#define GPDMA_C2CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C2CONTROL_SWIDTH_Pos) /*!< GPDMA C2CONTROL: SWIDTH Mask */ +#define GPDMA_C2CONTROL_DWIDTH_Pos 21 /*!< GPDMA C2CONTROL: DWIDTH Position */ +#define GPDMA_C2CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C2CONTROL_DWIDTH_Pos) /*!< GPDMA C2CONTROL: DWIDTH Mask */ +#define GPDMA_C2CONTROL_S_Pos 24 /*!< GPDMA C2CONTROL: S Position */ +#define GPDMA_C2CONTROL_S_Msk (0x01UL << GPDMA_C2CONTROL_S_Pos) /*!< GPDMA C2CONTROL: S Mask */ +#define GPDMA_C2CONTROL_D_Pos 25 /*!< GPDMA C2CONTROL: D Position */ +#define GPDMA_C2CONTROL_D_Msk (0x01UL << GPDMA_C2CONTROL_D_Pos) /*!< GPDMA C2CONTROL: D Mask */ +#define GPDMA_C2CONTROL_SI_Pos 26 /*!< GPDMA C2CONTROL: SI Position */ +#define GPDMA_C2CONTROL_SI_Msk (0x01UL << GPDMA_C2CONTROL_SI_Pos) /*!< GPDMA C2CONTROL: SI Mask */ +#define GPDMA_C2CONTROL_DI_Pos 27 /*!< GPDMA C2CONTROL: DI Position */ +#define GPDMA_C2CONTROL_DI_Msk (0x01UL << GPDMA_C2CONTROL_DI_Pos) /*!< GPDMA C2CONTROL: DI Mask */ +#define GPDMA_C2CONTROL_PROT1_Pos 28 /*!< GPDMA C2CONTROL: PROT1 Position */ +#define GPDMA_C2CONTROL_PROT1_Msk (0x01UL << GPDMA_C2CONTROL_PROT1_Pos) /*!< GPDMA C2CONTROL: PROT1 Mask */ +#define GPDMA_C2CONTROL_PROT2_Pos 29 /*!< GPDMA C2CONTROL: PROT2 Position */ +#define GPDMA_C2CONTROL_PROT2_Msk (0x01UL << GPDMA_C2CONTROL_PROT2_Pos) /*!< GPDMA C2CONTROL: PROT2 Mask */ +#define GPDMA_C2CONTROL_PROT3_Pos 30 /*!< GPDMA C2CONTROL: PROT3 Position */ +#define GPDMA_C2CONTROL_PROT3_Msk (0x01UL << GPDMA_C2CONTROL_PROT3_Pos) /*!< GPDMA C2CONTROL: PROT3 Mask */ +#define GPDMA_C2CONTROL_I_Pos 31 /*!< GPDMA C2CONTROL: I Position */ +#define GPDMA_C2CONTROL_I_Msk (0x01UL << GPDMA_C2CONTROL_I_Pos) /*!< GPDMA C2CONTROL: I Mask */ + +/* ------------------------------- GPDMA_C2CONFIG ------------------------------- */ +#define GPDMA_C2CONFIG_E_Pos 0 /*!< GPDMA C2CONFIG: E Position */ +#define GPDMA_C2CONFIG_E_Msk (0x01UL << GPDMA_C2CONFIG_E_Pos) /*!< GPDMA C2CONFIG: E Mask */ +#define GPDMA_C2CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C2CONFIG: SRCPERIPHERAL Position */ +#define GPDMA_C2CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C2CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C2CONFIG: SRCPERIPHERAL Mask */ +#define GPDMA_C2CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C2CONFIG: DESTPERIPHERAL Position */ +#define GPDMA_C2CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C2CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C2CONFIG: DESTPERIPHERAL Mask */ +#define GPDMA_C2CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C2CONFIG: FLOWCNTRL Position */ +#define GPDMA_C2CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C2CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C2CONFIG: FLOWCNTRL Mask */ +#define GPDMA_C2CONFIG_IE_Pos 14 /*!< GPDMA C2CONFIG: IE Position */ +#define GPDMA_C2CONFIG_IE_Msk (0x01UL << GPDMA_C2CONFIG_IE_Pos) /*!< GPDMA C2CONFIG: IE Mask */ +#define GPDMA_C2CONFIG_ITC_Pos 15 /*!< GPDMA C2CONFIG: ITC Position */ +#define GPDMA_C2CONFIG_ITC_Msk (0x01UL << GPDMA_C2CONFIG_ITC_Pos) /*!< GPDMA C2CONFIG: ITC Mask */ +#define GPDMA_C2CONFIG_L_Pos 16 /*!< GPDMA C2CONFIG: L Position */ +#define GPDMA_C2CONFIG_L_Msk (0x01UL << GPDMA_C2CONFIG_L_Pos) /*!< GPDMA C2CONFIG: L Mask */ +#define GPDMA_C2CONFIG_A_Pos 17 /*!< GPDMA C2CONFIG: A Position */ +#define GPDMA_C2CONFIG_A_Msk (0x01UL << GPDMA_C2CONFIG_A_Pos) /*!< GPDMA C2CONFIG: A Mask */ +#define GPDMA_C2CONFIG_H_Pos 18 /*!< GPDMA C2CONFIG: H Position */ +#define GPDMA_C2CONFIG_H_Msk (0x01UL << GPDMA_C2CONFIG_H_Pos) /*!< GPDMA C2CONFIG: H Mask */ + +/* ------------------------------- GPDMA_C3SRCADDR ------------------------------ */ +#define GPDMA_C3SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C3SRCADDR: SRCADDR Position */ +#define GPDMA_C3SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C3SRCADDR_SRCADDR_Pos) /*!< GPDMA C3SRCADDR: SRCADDR Mask */ + +/* ------------------------------ GPDMA_C3DESTADDR ------------------------------ */ +#define GPDMA_C3DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C3DESTADDR: DESTADDR Position */ +#define GPDMA_C3DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C3DESTADDR_DESTADDR_Pos) /*!< GPDMA C3DESTADDR: DESTADDR Mask */ + +/* --------------------------------- GPDMA_C3LLI -------------------------------- */ +#define GPDMA_C3LLI_LM_Pos 0 /*!< GPDMA C3LLI: LM Position */ +#define GPDMA_C3LLI_LM_Msk (0x01UL << GPDMA_C3LLI_LM_Pos) /*!< GPDMA C3LLI: LM Mask */ +#define GPDMA_C3LLI_R_Pos 1 /*!< GPDMA C3LLI: R Position */ +#define GPDMA_C3LLI_R_Msk (0x01UL << GPDMA_C3LLI_R_Pos) /*!< GPDMA C3LLI: R Mask */ +#define GPDMA_C3LLI_LLI_Pos 2 /*!< GPDMA C3LLI: LLI Position */ +#define GPDMA_C3LLI_LLI_Msk (0x3fffffffUL << GPDMA_C3LLI_LLI_Pos) /*!< GPDMA C3LLI: LLI Mask */ + +/* ------------------------------- GPDMA_C3CONTROL ------------------------------ */ +#define GPDMA_C3CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C3CONTROL: TRANSFERSIZE Position */ +#define GPDMA_C3CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C3CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C3CONTROL: TRANSFERSIZE Mask */ +#define GPDMA_C3CONTROL_SBSIZE_Pos 12 /*!< GPDMA C3CONTROL: SBSIZE Position */ +#define GPDMA_C3CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C3CONTROL_SBSIZE_Pos) /*!< GPDMA C3CONTROL: SBSIZE Mask */ +#define GPDMA_C3CONTROL_DBSIZE_Pos 15 /*!< GPDMA C3CONTROL: DBSIZE Position */ +#define GPDMA_C3CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C3CONTROL_DBSIZE_Pos) /*!< GPDMA C3CONTROL: DBSIZE Mask */ +#define GPDMA_C3CONTROL_SWIDTH_Pos 18 /*!< GPDMA C3CONTROL: SWIDTH Position */ +#define GPDMA_C3CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C3CONTROL_SWIDTH_Pos) /*!< GPDMA C3CONTROL: SWIDTH Mask */ +#define GPDMA_C3CONTROL_DWIDTH_Pos 21 /*!< GPDMA C3CONTROL: DWIDTH Position */ +#define GPDMA_C3CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C3CONTROL_DWIDTH_Pos) /*!< GPDMA C3CONTROL: DWIDTH Mask */ +#define GPDMA_C3CONTROL_S_Pos 24 /*!< GPDMA C3CONTROL: S Position */ +#define GPDMA_C3CONTROL_S_Msk (0x01UL << GPDMA_C3CONTROL_S_Pos) /*!< GPDMA C3CONTROL: S Mask */ +#define GPDMA_C3CONTROL_D_Pos 25 /*!< GPDMA C3CONTROL: D Position */ +#define GPDMA_C3CONTROL_D_Msk (0x01UL << GPDMA_C3CONTROL_D_Pos) /*!< GPDMA C3CONTROL: D Mask */ +#define GPDMA_C3CONTROL_SI_Pos 26 /*!< GPDMA C3CONTROL: SI Position */ +#define GPDMA_C3CONTROL_SI_Msk (0x01UL << GPDMA_C3CONTROL_SI_Pos) /*!< GPDMA C3CONTROL: SI Mask */ +#define GPDMA_C3CONTROL_DI_Pos 27 /*!< GPDMA C3CONTROL: DI Position */ +#define GPDMA_C3CONTROL_DI_Msk (0x01UL << GPDMA_C3CONTROL_DI_Pos) /*!< GPDMA C3CONTROL: DI Mask */ +#define GPDMA_C3CONTROL_PROT1_Pos 28 /*!< GPDMA C3CONTROL: PROT1 Position */ +#define GPDMA_C3CONTROL_PROT1_Msk (0x01UL << GPDMA_C3CONTROL_PROT1_Pos) /*!< GPDMA C3CONTROL: PROT1 Mask */ +#define GPDMA_C3CONTROL_PROT2_Pos 29 /*!< GPDMA C3CONTROL: PROT2 Position */ +#define GPDMA_C3CONTROL_PROT2_Msk (0x01UL << GPDMA_C3CONTROL_PROT2_Pos) /*!< GPDMA C3CONTROL: PROT2 Mask */ +#define GPDMA_C3CONTROL_PROT3_Pos 30 /*!< GPDMA C3CONTROL: PROT3 Position */ +#define GPDMA_C3CONTROL_PROT3_Msk (0x01UL << GPDMA_C3CONTROL_PROT3_Pos) /*!< GPDMA C3CONTROL: PROT3 Mask */ +#define GPDMA_C3CONTROL_I_Pos 31 /*!< GPDMA C3CONTROL: I Position */ +#define GPDMA_C3CONTROL_I_Msk (0x01UL << GPDMA_C3CONTROL_I_Pos) /*!< GPDMA C3CONTROL: I Mask */ + +/* ------------------------------- GPDMA_C3CONFIG ------------------------------- */ +#define GPDMA_C3CONFIG_E_Pos 0 /*!< GPDMA C3CONFIG: E Position */ +#define GPDMA_C3CONFIG_E_Msk (0x01UL << GPDMA_C3CONFIG_E_Pos) /*!< GPDMA C3CONFIG: E Mask */ +#define GPDMA_C3CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C3CONFIG: SRCPERIPHERAL Position */ +#define GPDMA_C3CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C3CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C3CONFIG: SRCPERIPHERAL Mask */ +#define GPDMA_C3CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C3CONFIG: DESTPERIPHERAL Position */ +#define GPDMA_C3CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C3CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C3CONFIG: DESTPERIPHERAL Mask */ +#define GPDMA_C3CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C3CONFIG: FLOWCNTRL Position */ +#define GPDMA_C3CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C3CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C3CONFIG: FLOWCNTRL Mask */ +#define GPDMA_C3CONFIG_IE_Pos 14 /*!< GPDMA C3CONFIG: IE Position */ +#define GPDMA_C3CONFIG_IE_Msk (0x01UL << GPDMA_C3CONFIG_IE_Pos) /*!< GPDMA C3CONFIG: IE Mask */ +#define GPDMA_C3CONFIG_ITC_Pos 15 /*!< GPDMA C3CONFIG: ITC Position */ +#define GPDMA_C3CONFIG_ITC_Msk (0x01UL << GPDMA_C3CONFIG_ITC_Pos) /*!< GPDMA C3CONFIG: ITC Mask */ +#define GPDMA_C3CONFIG_L_Pos 16 /*!< GPDMA C3CONFIG: L Position */ +#define GPDMA_C3CONFIG_L_Msk (0x01UL << GPDMA_C3CONFIG_L_Pos) /*!< GPDMA C3CONFIG: L Mask */ +#define GPDMA_C3CONFIG_A_Pos 17 /*!< GPDMA C3CONFIG: A Position */ +#define GPDMA_C3CONFIG_A_Msk (0x01UL << GPDMA_C3CONFIG_A_Pos) /*!< GPDMA C3CONFIG: A Mask */ +#define GPDMA_C3CONFIG_H_Pos 18 /*!< GPDMA C3CONFIG: H Position */ +#define GPDMA_C3CONFIG_H_Msk (0x01UL << GPDMA_C3CONFIG_H_Pos) /*!< GPDMA C3CONFIG: H Mask */ + +/* ------------------------------- GPDMA_C4SRCADDR ------------------------------ */ +#define GPDMA_C4SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C4SRCADDR: SRCADDR Position */ +#define GPDMA_C4SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C4SRCADDR_SRCADDR_Pos) /*!< GPDMA C4SRCADDR: SRCADDR Mask */ + +/* ------------------------------ GPDMA_C4DESTADDR ------------------------------ */ +#define GPDMA_C4DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C4DESTADDR: DESTADDR Position */ +#define GPDMA_C4DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C4DESTADDR_DESTADDR_Pos) /*!< GPDMA C4DESTADDR: DESTADDR Mask */ + +/* --------------------------------- GPDMA_C4LLI -------------------------------- */ +#define GPDMA_C4LLI_LM_Pos 0 /*!< GPDMA C4LLI: LM Position */ +#define GPDMA_C4LLI_LM_Msk (0x01UL << GPDMA_C4LLI_LM_Pos) /*!< GPDMA C4LLI: LM Mask */ +#define GPDMA_C4LLI_R_Pos 1 /*!< GPDMA C4LLI: R Position */ +#define GPDMA_C4LLI_R_Msk (0x01UL << GPDMA_C4LLI_R_Pos) /*!< GPDMA C4LLI: R Mask */ +#define GPDMA_C4LLI_LLI_Pos 2 /*!< GPDMA C4LLI: LLI Position */ +#define GPDMA_C4LLI_LLI_Msk (0x3fffffffUL << GPDMA_C4LLI_LLI_Pos) /*!< GPDMA C4LLI: LLI Mask */ + +/* ------------------------------- GPDMA_C4CONTROL ------------------------------ */ +#define GPDMA_C4CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C4CONTROL: TRANSFERSIZE Position */ +#define GPDMA_C4CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C4CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C4CONTROL: TRANSFERSIZE Mask */ +#define GPDMA_C4CONTROL_SBSIZE_Pos 12 /*!< GPDMA C4CONTROL: SBSIZE Position */ +#define GPDMA_C4CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C4CONTROL_SBSIZE_Pos) /*!< GPDMA C4CONTROL: SBSIZE Mask */ +#define GPDMA_C4CONTROL_DBSIZE_Pos 15 /*!< GPDMA C4CONTROL: DBSIZE Position */ +#define GPDMA_C4CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C4CONTROL_DBSIZE_Pos) /*!< GPDMA C4CONTROL: DBSIZE Mask */ +#define GPDMA_C4CONTROL_SWIDTH_Pos 18 /*!< GPDMA C4CONTROL: SWIDTH Position */ +#define GPDMA_C4CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C4CONTROL_SWIDTH_Pos) /*!< GPDMA C4CONTROL: SWIDTH Mask */ +#define GPDMA_C4CONTROL_DWIDTH_Pos 21 /*!< GPDMA C4CONTROL: DWIDTH Position */ +#define GPDMA_C4CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C4CONTROL_DWIDTH_Pos) /*!< GPDMA C4CONTROL: DWIDTH Mask */ +#define GPDMA_C4CONTROL_S_Pos 24 /*!< GPDMA C4CONTROL: S Position */ +#define GPDMA_C4CONTROL_S_Msk (0x01UL << GPDMA_C4CONTROL_S_Pos) /*!< GPDMA C4CONTROL: S Mask */ +#define GPDMA_C4CONTROL_D_Pos 25 /*!< GPDMA C4CONTROL: D Position */ +#define GPDMA_C4CONTROL_D_Msk (0x01UL << GPDMA_C4CONTROL_D_Pos) /*!< GPDMA C4CONTROL: D Mask */ +#define GPDMA_C4CONTROL_SI_Pos 26 /*!< GPDMA C4CONTROL: SI Position */ +#define GPDMA_C4CONTROL_SI_Msk (0x01UL << GPDMA_C4CONTROL_SI_Pos) /*!< GPDMA C4CONTROL: SI Mask */ +#define GPDMA_C4CONTROL_DI_Pos 27 /*!< GPDMA C4CONTROL: DI Position */ +#define GPDMA_C4CONTROL_DI_Msk (0x01UL << GPDMA_C4CONTROL_DI_Pos) /*!< GPDMA C4CONTROL: DI Mask */ +#define GPDMA_C4CONTROL_PROT1_Pos 28 /*!< GPDMA C4CONTROL: PROT1 Position */ +#define GPDMA_C4CONTROL_PROT1_Msk (0x01UL << GPDMA_C4CONTROL_PROT1_Pos) /*!< GPDMA C4CONTROL: PROT1 Mask */ +#define GPDMA_C4CONTROL_PROT2_Pos 29 /*!< GPDMA C4CONTROL: PROT2 Position */ +#define GPDMA_C4CONTROL_PROT2_Msk (0x01UL << GPDMA_C4CONTROL_PROT2_Pos) /*!< GPDMA C4CONTROL: PROT2 Mask */ +#define GPDMA_C4CONTROL_PROT3_Pos 30 /*!< GPDMA C4CONTROL: PROT3 Position */ +#define GPDMA_C4CONTROL_PROT3_Msk (0x01UL << GPDMA_C4CONTROL_PROT3_Pos) /*!< GPDMA C4CONTROL: PROT3 Mask */ +#define GPDMA_C4CONTROL_I_Pos 31 /*!< GPDMA C4CONTROL: I Position */ +#define GPDMA_C4CONTROL_I_Msk (0x01UL << GPDMA_C4CONTROL_I_Pos) /*!< GPDMA C4CONTROL: I Mask */ + +/* ------------------------------- GPDMA_C4CONFIG ------------------------------- */ +#define GPDMA_C4CONFIG_E_Pos 0 /*!< GPDMA C4CONFIG: E Position */ +#define GPDMA_C4CONFIG_E_Msk (0x01UL << GPDMA_C4CONFIG_E_Pos) /*!< GPDMA C4CONFIG: E Mask */ +#define GPDMA_C4CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C4CONFIG: SRCPERIPHERAL Position */ +#define GPDMA_C4CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C4CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C4CONFIG: SRCPERIPHERAL Mask */ +#define GPDMA_C4CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C4CONFIG: DESTPERIPHERAL Position */ +#define GPDMA_C4CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C4CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C4CONFIG: DESTPERIPHERAL Mask */ +#define GPDMA_C4CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C4CONFIG: FLOWCNTRL Position */ +#define GPDMA_C4CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C4CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C4CONFIG: FLOWCNTRL Mask */ +#define GPDMA_C4CONFIG_IE_Pos 14 /*!< GPDMA C4CONFIG: IE Position */ +#define GPDMA_C4CONFIG_IE_Msk (0x01UL << GPDMA_C4CONFIG_IE_Pos) /*!< GPDMA C4CONFIG: IE Mask */ +#define GPDMA_C4CONFIG_ITC_Pos 15 /*!< GPDMA C4CONFIG: ITC Position */ +#define GPDMA_C4CONFIG_ITC_Msk (0x01UL << GPDMA_C4CONFIG_ITC_Pos) /*!< GPDMA C4CONFIG: ITC Mask */ +#define GPDMA_C4CONFIG_L_Pos 16 /*!< GPDMA C4CONFIG: L Position */ +#define GPDMA_C4CONFIG_L_Msk (0x01UL << GPDMA_C4CONFIG_L_Pos) /*!< GPDMA C4CONFIG: L Mask */ +#define GPDMA_C4CONFIG_A_Pos 17 /*!< GPDMA C4CONFIG: A Position */ +#define GPDMA_C4CONFIG_A_Msk (0x01UL << GPDMA_C4CONFIG_A_Pos) /*!< GPDMA C4CONFIG: A Mask */ +#define GPDMA_C4CONFIG_H_Pos 18 /*!< GPDMA C4CONFIG: H Position */ +#define GPDMA_C4CONFIG_H_Msk (0x01UL << GPDMA_C4CONFIG_H_Pos) /*!< GPDMA C4CONFIG: H Mask */ + +/* ------------------------------- GPDMA_C5SRCADDR ------------------------------ */ +#define GPDMA_C5SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C5SRCADDR: SRCADDR Position */ +#define GPDMA_C5SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C5SRCADDR_SRCADDR_Pos) /*!< GPDMA C5SRCADDR: SRCADDR Mask */ + +/* ------------------------------ GPDMA_C5DESTADDR ------------------------------ */ +#define GPDMA_C5DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C5DESTADDR: DESTADDR Position */ +#define GPDMA_C5DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C5DESTADDR_DESTADDR_Pos) /*!< GPDMA C5DESTADDR: DESTADDR Mask */ + +/* --------------------------------- GPDMA_C5LLI -------------------------------- */ +#define GPDMA_C5LLI_LM_Pos 0 /*!< GPDMA C5LLI: LM Position */ +#define GPDMA_C5LLI_LM_Msk (0x01UL << GPDMA_C5LLI_LM_Pos) /*!< GPDMA C5LLI: LM Mask */ +#define GPDMA_C5LLI_R_Pos 1 /*!< GPDMA C5LLI: R Position */ +#define GPDMA_C5LLI_R_Msk (0x01UL << GPDMA_C5LLI_R_Pos) /*!< GPDMA C5LLI: R Mask */ +#define GPDMA_C5LLI_LLI_Pos 2 /*!< GPDMA C5LLI: LLI Position */ +#define GPDMA_C5LLI_LLI_Msk (0x3fffffffUL << GPDMA_C5LLI_LLI_Pos) /*!< GPDMA C5LLI: LLI Mask */ + +/* ------------------------------- GPDMA_C5CONTROL ------------------------------ */ +#define GPDMA_C5CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C5CONTROL: TRANSFERSIZE Position */ +#define GPDMA_C5CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C5CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C5CONTROL: TRANSFERSIZE Mask */ +#define GPDMA_C5CONTROL_SBSIZE_Pos 12 /*!< GPDMA C5CONTROL: SBSIZE Position */ +#define GPDMA_C5CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C5CONTROL_SBSIZE_Pos) /*!< GPDMA C5CONTROL: SBSIZE Mask */ +#define GPDMA_C5CONTROL_DBSIZE_Pos 15 /*!< GPDMA C5CONTROL: DBSIZE Position */ +#define GPDMA_C5CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C5CONTROL_DBSIZE_Pos) /*!< GPDMA C5CONTROL: DBSIZE Mask */ +#define GPDMA_C5CONTROL_SWIDTH_Pos 18 /*!< GPDMA C5CONTROL: SWIDTH Position */ +#define GPDMA_C5CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C5CONTROL_SWIDTH_Pos) /*!< GPDMA C5CONTROL: SWIDTH Mask */ +#define GPDMA_C5CONTROL_DWIDTH_Pos 21 /*!< GPDMA C5CONTROL: DWIDTH Position */ +#define GPDMA_C5CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C5CONTROL_DWIDTH_Pos) /*!< GPDMA C5CONTROL: DWIDTH Mask */ +#define GPDMA_C5CONTROL_S_Pos 24 /*!< GPDMA C5CONTROL: S Position */ +#define GPDMA_C5CONTROL_S_Msk (0x01UL << GPDMA_C5CONTROL_S_Pos) /*!< GPDMA C5CONTROL: S Mask */ +#define GPDMA_C5CONTROL_D_Pos 25 /*!< GPDMA C5CONTROL: D Position */ +#define GPDMA_C5CONTROL_D_Msk (0x01UL << GPDMA_C5CONTROL_D_Pos) /*!< GPDMA C5CONTROL: D Mask */ +#define GPDMA_C5CONTROL_SI_Pos 26 /*!< GPDMA C5CONTROL: SI Position */ +#define GPDMA_C5CONTROL_SI_Msk (0x01UL << GPDMA_C5CONTROL_SI_Pos) /*!< GPDMA C5CONTROL: SI Mask */ +#define GPDMA_C5CONTROL_DI_Pos 27 /*!< GPDMA C5CONTROL: DI Position */ +#define GPDMA_C5CONTROL_DI_Msk (0x01UL << GPDMA_C5CONTROL_DI_Pos) /*!< GPDMA C5CONTROL: DI Mask */ +#define GPDMA_C5CONTROL_PROT1_Pos 28 /*!< GPDMA C5CONTROL: PROT1 Position */ +#define GPDMA_C5CONTROL_PROT1_Msk (0x01UL << GPDMA_C5CONTROL_PROT1_Pos) /*!< GPDMA C5CONTROL: PROT1 Mask */ +#define GPDMA_C5CONTROL_PROT2_Pos 29 /*!< GPDMA C5CONTROL: PROT2 Position */ +#define GPDMA_C5CONTROL_PROT2_Msk (0x01UL << GPDMA_C5CONTROL_PROT2_Pos) /*!< GPDMA C5CONTROL: PROT2 Mask */ +#define GPDMA_C5CONTROL_PROT3_Pos 30 /*!< GPDMA C5CONTROL: PROT3 Position */ +#define GPDMA_C5CONTROL_PROT3_Msk (0x01UL << GPDMA_C5CONTROL_PROT3_Pos) /*!< GPDMA C5CONTROL: PROT3 Mask */ +#define GPDMA_C5CONTROL_I_Pos 31 /*!< GPDMA C5CONTROL: I Position */ +#define GPDMA_C5CONTROL_I_Msk (0x01UL << GPDMA_C5CONTROL_I_Pos) /*!< GPDMA C5CONTROL: I Mask */ + +/* ------------------------------- GPDMA_C5CONFIG ------------------------------- */ +#define GPDMA_C5CONFIG_E_Pos 0 /*!< GPDMA C5CONFIG: E Position */ +#define GPDMA_C5CONFIG_E_Msk (0x01UL << GPDMA_C5CONFIG_E_Pos) /*!< GPDMA C5CONFIG: E Mask */ +#define GPDMA_C5CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C5CONFIG: SRCPERIPHERAL Position */ +#define GPDMA_C5CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C5CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C5CONFIG: SRCPERIPHERAL Mask */ +#define GPDMA_C5CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C5CONFIG: DESTPERIPHERAL Position */ +#define GPDMA_C5CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C5CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C5CONFIG: DESTPERIPHERAL Mask */ +#define GPDMA_C5CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C5CONFIG: FLOWCNTRL Position */ +#define GPDMA_C5CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C5CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C5CONFIG: FLOWCNTRL Mask */ +#define GPDMA_C5CONFIG_IE_Pos 14 /*!< GPDMA C5CONFIG: IE Position */ +#define GPDMA_C5CONFIG_IE_Msk (0x01UL << GPDMA_C5CONFIG_IE_Pos) /*!< GPDMA C5CONFIG: IE Mask */ +#define GPDMA_C5CONFIG_ITC_Pos 15 /*!< GPDMA C5CONFIG: ITC Position */ +#define GPDMA_C5CONFIG_ITC_Msk (0x01UL << GPDMA_C5CONFIG_ITC_Pos) /*!< GPDMA C5CONFIG: ITC Mask */ +#define GPDMA_C5CONFIG_L_Pos 16 /*!< GPDMA C5CONFIG: L Position */ +#define GPDMA_C5CONFIG_L_Msk (0x01UL << GPDMA_C5CONFIG_L_Pos) /*!< GPDMA C5CONFIG: L Mask */ +#define GPDMA_C5CONFIG_A_Pos 17 /*!< GPDMA C5CONFIG: A Position */ +#define GPDMA_C5CONFIG_A_Msk (0x01UL << GPDMA_C5CONFIG_A_Pos) /*!< GPDMA C5CONFIG: A Mask */ +#define GPDMA_C5CONFIG_H_Pos 18 /*!< GPDMA C5CONFIG: H Position */ +#define GPDMA_C5CONFIG_H_Msk (0x01UL << GPDMA_C5CONFIG_H_Pos) /*!< GPDMA C5CONFIG: H Mask */ + +/* ------------------------------- GPDMA_C6SRCADDR ------------------------------ */ +#define GPDMA_C6SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C6SRCADDR: SRCADDR Position */ +#define GPDMA_C6SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C6SRCADDR_SRCADDR_Pos) /*!< GPDMA C6SRCADDR: SRCADDR Mask */ + +/* ------------------------------ GPDMA_C6DESTADDR ------------------------------ */ +#define GPDMA_C6DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C6DESTADDR: DESTADDR Position */ +#define GPDMA_C6DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C6DESTADDR_DESTADDR_Pos) /*!< GPDMA C6DESTADDR: DESTADDR Mask */ + +/* --------------------------------- GPDMA_C6LLI -------------------------------- */ +#define GPDMA_C6LLI_LM_Pos 0 /*!< GPDMA C6LLI: LM Position */ +#define GPDMA_C6LLI_LM_Msk (0x01UL << GPDMA_C6LLI_LM_Pos) /*!< GPDMA C6LLI: LM Mask */ +#define GPDMA_C6LLI_R_Pos 1 /*!< GPDMA C6LLI: R Position */ +#define GPDMA_C6LLI_R_Msk (0x01UL << GPDMA_C6LLI_R_Pos) /*!< GPDMA C6LLI: R Mask */ +#define GPDMA_C6LLI_LLI_Pos 2 /*!< GPDMA C6LLI: LLI Position */ +#define GPDMA_C6LLI_LLI_Msk (0x3fffffffUL << GPDMA_C6LLI_LLI_Pos) /*!< GPDMA C6LLI: LLI Mask */ + +/* ------------------------------- GPDMA_C6CONTROL ------------------------------ */ +#define GPDMA_C6CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C6CONTROL: TRANSFERSIZE Position */ +#define GPDMA_C6CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C6CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C6CONTROL: TRANSFERSIZE Mask */ +#define GPDMA_C6CONTROL_SBSIZE_Pos 12 /*!< GPDMA C6CONTROL: SBSIZE Position */ +#define GPDMA_C6CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C6CONTROL_SBSIZE_Pos) /*!< GPDMA C6CONTROL: SBSIZE Mask */ +#define GPDMA_C6CONTROL_DBSIZE_Pos 15 /*!< GPDMA C6CONTROL: DBSIZE Position */ +#define GPDMA_C6CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C6CONTROL_DBSIZE_Pos) /*!< GPDMA C6CONTROL: DBSIZE Mask */ +#define GPDMA_C6CONTROL_SWIDTH_Pos 18 /*!< GPDMA C6CONTROL: SWIDTH Position */ +#define GPDMA_C6CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C6CONTROL_SWIDTH_Pos) /*!< GPDMA C6CONTROL: SWIDTH Mask */ +#define GPDMA_C6CONTROL_DWIDTH_Pos 21 /*!< GPDMA C6CONTROL: DWIDTH Position */ +#define GPDMA_C6CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C6CONTROL_DWIDTH_Pos) /*!< GPDMA C6CONTROL: DWIDTH Mask */ +#define GPDMA_C6CONTROL_S_Pos 24 /*!< GPDMA C6CONTROL: S Position */ +#define GPDMA_C6CONTROL_S_Msk (0x01UL << GPDMA_C6CONTROL_S_Pos) /*!< GPDMA C6CONTROL: S Mask */ +#define GPDMA_C6CONTROL_D_Pos 25 /*!< GPDMA C6CONTROL: D Position */ +#define GPDMA_C6CONTROL_D_Msk (0x01UL << GPDMA_C6CONTROL_D_Pos) /*!< GPDMA C6CONTROL: D Mask */ +#define GPDMA_C6CONTROL_SI_Pos 26 /*!< GPDMA C6CONTROL: SI Position */ +#define GPDMA_C6CONTROL_SI_Msk (0x01UL << GPDMA_C6CONTROL_SI_Pos) /*!< GPDMA C6CONTROL: SI Mask */ +#define GPDMA_C6CONTROL_DI_Pos 27 /*!< GPDMA C6CONTROL: DI Position */ +#define GPDMA_C6CONTROL_DI_Msk (0x01UL << GPDMA_C6CONTROL_DI_Pos) /*!< GPDMA C6CONTROL: DI Mask */ +#define GPDMA_C6CONTROL_PROT1_Pos 28 /*!< GPDMA C6CONTROL: PROT1 Position */ +#define GPDMA_C6CONTROL_PROT1_Msk (0x01UL << GPDMA_C6CONTROL_PROT1_Pos) /*!< GPDMA C6CONTROL: PROT1 Mask */ +#define GPDMA_C6CONTROL_PROT2_Pos 29 /*!< GPDMA C6CONTROL: PROT2 Position */ +#define GPDMA_C6CONTROL_PROT2_Msk (0x01UL << GPDMA_C6CONTROL_PROT2_Pos) /*!< GPDMA C6CONTROL: PROT2 Mask */ +#define GPDMA_C6CONTROL_PROT3_Pos 30 /*!< GPDMA C6CONTROL: PROT3 Position */ +#define GPDMA_C6CONTROL_PROT3_Msk (0x01UL << GPDMA_C6CONTROL_PROT3_Pos) /*!< GPDMA C6CONTROL: PROT3 Mask */ +#define GPDMA_C6CONTROL_I_Pos 31 /*!< GPDMA C6CONTROL: I Position */ +#define GPDMA_C6CONTROL_I_Msk (0x01UL << GPDMA_C6CONTROL_I_Pos) /*!< GPDMA C6CONTROL: I Mask */ + +/* ------------------------------- GPDMA_C6CONFIG ------------------------------- */ +#define GPDMA_C6CONFIG_E_Pos 0 /*!< GPDMA C6CONFIG: E Position */ +#define GPDMA_C6CONFIG_E_Msk (0x01UL << GPDMA_C6CONFIG_E_Pos) /*!< GPDMA C6CONFIG: E Mask */ +#define GPDMA_C6CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C6CONFIG: SRCPERIPHERAL Position */ +#define GPDMA_C6CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C6CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C6CONFIG: SRCPERIPHERAL Mask */ +#define GPDMA_C6CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C6CONFIG: DESTPERIPHERAL Position */ +#define GPDMA_C6CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C6CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C6CONFIG: DESTPERIPHERAL Mask */ +#define GPDMA_C6CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C6CONFIG: FLOWCNTRL Position */ +#define GPDMA_C6CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C6CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C6CONFIG: FLOWCNTRL Mask */ +#define GPDMA_C6CONFIG_IE_Pos 14 /*!< GPDMA C6CONFIG: IE Position */ +#define GPDMA_C6CONFIG_IE_Msk (0x01UL << GPDMA_C6CONFIG_IE_Pos) /*!< GPDMA C6CONFIG: IE Mask */ +#define GPDMA_C6CONFIG_ITC_Pos 15 /*!< GPDMA C6CONFIG: ITC Position */ +#define GPDMA_C6CONFIG_ITC_Msk (0x01UL << GPDMA_C6CONFIG_ITC_Pos) /*!< GPDMA C6CONFIG: ITC Mask */ +#define GPDMA_C6CONFIG_L_Pos 16 /*!< GPDMA C6CONFIG: L Position */ +#define GPDMA_C6CONFIG_L_Msk (0x01UL << GPDMA_C6CONFIG_L_Pos) /*!< GPDMA C6CONFIG: L Mask */ +#define GPDMA_C6CONFIG_A_Pos 17 /*!< GPDMA C6CONFIG: A Position */ +#define GPDMA_C6CONFIG_A_Msk (0x01UL << GPDMA_C6CONFIG_A_Pos) /*!< GPDMA C6CONFIG: A Mask */ +#define GPDMA_C6CONFIG_H_Pos 18 /*!< GPDMA C6CONFIG: H Position */ +#define GPDMA_C6CONFIG_H_Msk (0x01UL << GPDMA_C6CONFIG_H_Pos) /*!< GPDMA C6CONFIG: H Mask */ + +/* ------------------------------- GPDMA_C7SRCADDR ------------------------------ */ +#define GPDMA_C7SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C7SRCADDR: SRCADDR Position */ +#define GPDMA_C7SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C7SRCADDR_SRCADDR_Pos) /*!< GPDMA C7SRCADDR: SRCADDR Mask */ + +/* ------------------------------ GPDMA_C7DESTADDR ------------------------------ */ +#define GPDMA_C7DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C7DESTADDR: DESTADDR Position */ +#define GPDMA_C7DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C7DESTADDR_DESTADDR_Pos) /*!< GPDMA C7DESTADDR: DESTADDR Mask */ + +/* --------------------------------- GPDMA_C7LLI -------------------------------- */ +#define GPDMA_C7LLI_LM_Pos 0 /*!< GPDMA C7LLI: LM Position */ +#define GPDMA_C7LLI_LM_Msk (0x01UL << GPDMA_C7LLI_LM_Pos) /*!< GPDMA C7LLI: LM Mask */ +#define GPDMA_C7LLI_R_Pos 1 /*!< GPDMA C7LLI: R Position */ +#define GPDMA_C7LLI_R_Msk (0x01UL << GPDMA_C7LLI_R_Pos) /*!< GPDMA C7LLI: R Mask */ +#define GPDMA_C7LLI_LLI_Pos 2 /*!< GPDMA C7LLI: LLI Position */ +#define GPDMA_C7LLI_LLI_Msk (0x3fffffffUL << GPDMA_C7LLI_LLI_Pos) /*!< GPDMA C7LLI: LLI Mask */ + +/* ------------------------------- GPDMA_C7CONTROL ------------------------------ */ +#define GPDMA_C7CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C7CONTROL: TRANSFERSIZE Position */ +#define GPDMA_C7CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C7CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C7CONTROL: TRANSFERSIZE Mask */ +#define GPDMA_C7CONTROL_SBSIZE_Pos 12 /*!< GPDMA C7CONTROL: SBSIZE Position */ +#define GPDMA_C7CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C7CONTROL_SBSIZE_Pos) /*!< GPDMA C7CONTROL: SBSIZE Mask */ +#define GPDMA_C7CONTROL_DBSIZE_Pos 15 /*!< GPDMA C7CONTROL: DBSIZE Position */ +#define GPDMA_C7CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C7CONTROL_DBSIZE_Pos) /*!< GPDMA C7CONTROL: DBSIZE Mask */ +#define GPDMA_C7CONTROL_SWIDTH_Pos 18 /*!< GPDMA C7CONTROL: SWIDTH Position */ +#define GPDMA_C7CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C7CONTROL_SWIDTH_Pos) /*!< GPDMA C7CONTROL: SWIDTH Mask */ +#define GPDMA_C7CONTROL_DWIDTH_Pos 21 /*!< GPDMA C7CONTROL: DWIDTH Position */ +#define GPDMA_C7CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C7CONTROL_DWIDTH_Pos) /*!< GPDMA C7CONTROL: DWIDTH Mask */ +#define GPDMA_C7CONTROL_S_Pos 24 /*!< GPDMA C7CONTROL: S Position */ +#define GPDMA_C7CONTROL_S_Msk (0x01UL << GPDMA_C7CONTROL_S_Pos) /*!< GPDMA C7CONTROL: S Mask */ +#define GPDMA_C7CONTROL_D_Pos 25 /*!< GPDMA C7CONTROL: D Position */ +#define GPDMA_C7CONTROL_D_Msk (0x01UL << GPDMA_C7CONTROL_D_Pos) /*!< GPDMA C7CONTROL: D Mask */ +#define GPDMA_C7CONTROL_SI_Pos 26 /*!< GPDMA C7CONTROL: SI Position */ +#define GPDMA_C7CONTROL_SI_Msk (0x01UL << GPDMA_C7CONTROL_SI_Pos) /*!< GPDMA C7CONTROL: SI Mask */ +#define GPDMA_C7CONTROL_DI_Pos 27 /*!< GPDMA C7CONTROL: DI Position */ +#define GPDMA_C7CONTROL_DI_Msk (0x01UL << GPDMA_C7CONTROL_DI_Pos) /*!< GPDMA C7CONTROL: DI Mask */ +#define GPDMA_C7CONTROL_PROT1_Pos 28 /*!< GPDMA C7CONTROL: PROT1 Position */ +#define GPDMA_C7CONTROL_PROT1_Msk (0x01UL << GPDMA_C7CONTROL_PROT1_Pos) /*!< GPDMA C7CONTROL: PROT1 Mask */ +#define GPDMA_C7CONTROL_PROT2_Pos 29 /*!< GPDMA C7CONTROL: PROT2 Position */ +#define GPDMA_C7CONTROL_PROT2_Msk (0x01UL << GPDMA_C7CONTROL_PROT2_Pos) /*!< GPDMA C7CONTROL: PROT2 Mask */ +#define GPDMA_C7CONTROL_PROT3_Pos 30 /*!< GPDMA C7CONTROL: PROT3 Position */ +#define GPDMA_C7CONTROL_PROT3_Msk (0x01UL << GPDMA_C7CONTROL_PROT3_Pos) /*!< GPDMA C7CONTROL: PROT3 Mask */ +#define GPDMA_C7CONTROL_I_Pos 31 /*!< GPDMA C7CONTROL: I Position */ +#define GPDMA_C7CONTROL_I_Msk (0x01UL << GPDMA_C7CONTROL_I_Pos) /*!< GPDMA C7CONTROL: I Mask */ + +/* ------------------------------- GPDMA_C7CONFIG ------------------------------- */ +#define GPDMA_C7CONFIG_E_Pos 0 /*!< GPDMA C7CONFIG: E Position */ +#define GPDMA_C7CONFIG_E_Msk (0x01UL << GPDMA_C7CONFIG_E_Pos) /*!< GPDMA C7CONFIG: E Mask */ +#define GPDMA_C7CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C7CONFIG: SRCPERIPHERAL Position */ +#define GPDMA_C7CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C7CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C7CONFIG: SRCPERIPHERAL Mask */ +#define GPDMA_C7CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C7CONFIG: DESTPERIPHERAL Position */ +#define GPDMA_C7CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C7CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C7CONFIG: DESTPERIPHERAL Mask */ +#define GPDMA_C7CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C7CONFIG: FLOWCNTRL Position */ +#define GPDMA_C7CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C7CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C7CONFIG: FLOWCNTRL Mask */ +#define GPDMA_C7CONFIG_IE_Pos 14 /*!< GPDMA C7CONFIG: IE Position */ +#define GPDMA_C7CONFIG_IE_Msk (0x01UL << GPDMA_C7CONFIG_IE_Pos) /*!< GPDMA C7CONFIG: IE Mask */ +#define GPDMA_C7CONFIG_ITC_Pos 15 /*!< GPDMA C7CONFIG: ITC Position */ +#define GPDMA_C7CONFIG_ITC_Msk (0x01UL << GPDMA_C7CONFIG_ITC_Pos) /*!< GPDMA C7CONFIG: ITC Mask */ +#define GPDMA_C7CONFIG_L_Pos 16 /*!< GPDMA C7CONFIG: L Position */ +#define GPDMA_C7CONFIG_L_Msk (0x01UL << GPDMA_C7CONFIG_L_Pos) /*!< GPDMA C7CONFIG: L Mask */ +#define GPDMA_C7CONFIG_A_Pos 17 /*!< GPDMA C7CONFIG: A Position */ +#define GPDMA_C7CONFIG_A_Msk (0x01UL << GPDMA_C7CONFIG_A_Pos) /*!< GPDMA C7CONFIG: A Mask */ +#define GPDMA_C7CONFIG_H_Pos 18 /*!< GPDMA C7CONFIG: H Position */ +#define GPDMA_C7CONFIG_H_Msk (0x01UL << GPDMA_C7CONFIG_H_Pos) /*!< GPDMA C7CONFIG: H Mask */ + + +/* ================================================================================ */ +/* ================ struct 'SPIFI' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- SPIFI_CTRL --------------------------------- */ +#define SPIFI_CTRL_TIMEOUT_Pos 0 /*!< SPIFI CTRL: TIMEOUT Position */ +#define SPIFI_CTRL_TIMEOUT_Msk (0x0000ffffUL << SPIFI_CTRL_TIMEOUT_Pos) /*!< SPIFI CTRL: TIMEOUT Mask */ +#define SPIFI_CTRL_CSHIGH_Pos 16 /*!< SPIFI CTRL: CSHIGH Position */ +#define SPIFI_CTRL_CSHIGH_Msk (0x0fUL << SPIFI_CTRL_CSHIGH_Pos) /*!< SPIFI CTRL: CSHIGH Mask */ +#define SPIFI_CTRL_D_PRFTCH_DIS_Pos 21 /*!< SPIFI CTRL: D_PRFTCH_DIS Position */ +#define SPIFI_CTRL_D_PRFTCH_DIS_Msk (0x01UL << SPIFI_CTRL_D_PRFTCH_DIS_Pos) /*!< SPIFI CTRL: D_PRFTCH_DIS Mask */ +#define SPIFI_CTRL_INTEN_Pos 22 /*!< SPIFI CTRL: INTEN Position */ +#define SPIFI_CTRL_INTEN_Msk (0x01UL << SPIFI_CTRL_INTEN_Pos) /*!< SPIFI CTRL: INTEN Mask */ +#define SPIFI_CTRL_MODE3_Pos 23 /*!< SPIFI CTRL: MODE3 Position */ +#define SPIFI_CTRL_MODE3_Msk (0x01UL << SPIFI_CTRL_MODE3_Pos) /*!< SPIFI CTRL: MODE3 Mask */ +#define SPIFI_CTRL_PRFTCH_DIS_Pos 27 /*!< SPIFI CTRL: PRFTCH_DIS Position */ +#define SPIFI_CTRL_PRFTCH_DIS_Msk (0x01UL << SPIFI_CTRL_PRFTCH_DIS_Pos) /*!< SPIFI CTRL: PRFTCH_DIS Mask */ +#define SPIFI_CTRL_DUAL_Pos 28 /*!< SPIFI CTRL: DUAL Position */ +#define SPIFI_CTRL_DUAL_Msk (0x01UL << SPIFI_CTRL_DUAL_Pos) /*!< SPIFI CTRL: DUAL Mask */ +#define SPIFI_CTRL_RFCLK_Pos 29 /*!< SPIFI CTRL: RFCLK Position */ +#define SPIFI_CTRL_RFCLK_Msk (0x01UL << SPIFI_CTRL_RFCLK_Pos) /*!< SPIFI CTRL: RFCLK Mask */ +#define SPIFI_CTRL_FBCLK_Pos 30 /*!< SPIFI CTRL: FBCLK Position */ +#define SPIFI_CTRL_FBCLK_Msk (0x01UL << SPIFI_CTRL_FBCLK_Pos) /*!< SPIFI CTRL: FBCLK Mask */ +#define SPIFI_CTRL_DMAEN_Pos 31 /*!< SPIFI CTRL: DMAEN Position */ +#define SPIFI_CTRL_DMAEN_Msk (0x01UL << SPIFI_CTRL_DMAEN_Pos) /*!< SPIFI CTRL: DMAEN Mask */ + +/* ---------------------------------- SPIFI_CMD --------------------------------- */ +#define SPIFI_CMD_DATALEN_Pos 0 /*!< SPIFI CMD: DATALEN Position */ +#define SPIFI_CMD_DATALEN_Msk (0x00003fffUL << SPIFI_CMD_DATALEN_Pos) /*!< SPIFI CMD: DATALEN Mask */ +#define SPIFI_CMD_POLL_Pos 14 /*!< SPIFI CMD: POLL Position */ +#define SPIFI_CMD_POLL_Msk (0x01UL << SPIFI_CMD_POLL_Pos) /*!< SPIFI CMD: POLL Mask */ +#define SPIFI_CMD_DOUT_Pos 15 /*!< SPIFI CMD: DOUT Position */ +#define SPIFI_CMD_DOUT_Msk (0x01UL << SPIFI_CMD_DOUT_Pos) /*!< SPIFI CMD: DOUT Mask */ +#define SPIFI_CMD_INTLEN_Pos 16 /*!< SPIFI CMD: INTLEN Position */ +#define SPIFI_CMD_INTLEN_Msk (0x07UL << SPIFI_CMD_INTLEN_Pos) /*!< SPIFI CMD: INTLEN Mask */ +#define SPIFI_CMD_FIELDFORM_Pos 19 /*!< SPIFI CMD: FIELDFORM Position */ +#define SPIFI_CMD_FIELDFORM_Msk (0x03UL << SPIFI_CMD_FIELDFORM_Pos) /*!< SPIFI CMD: FIELDFORM Mask */ +#define SPIFI_CMD_FRAMEFORM_Pos 21 /*!< SPIFI CMD: FRAMEFORM Position */ +#define SPIFI_CMD_FRAMEFORM_Msk (0x07UL << SPIFI_CMD_FRAMEFORM_Pos) /*!< SPIFI CMD: FRAMEFORM Mask */ +#define SPIFI_CMD_OPCODE_Pos 24 /*!< SPIFI CMD: OPCODE Position */ +#define SPIFI_CMD_OPCODE_Msk (0x000000ffUL << SPIFI_CMD_OPCODE_Pos) /*!< SPIFI CMD: OPCODE Mask */ + +/* --------------------------------- SPIFI_ADDR --------------------------------- */ +#define SPIFI_ADDR_ADDRESS_Pos 0 /*!< SPIFI ADDR: ADDRESS Position */ +#define SPIFI_ADDR_ADDRESS_Msk (0xffffffffUL << SPIFI_ADDR_ADDRESS_Pos) /*!< SPIFI ADDR: ADDRESS Mask */ + +/* --------------------------------- SPIFI_IDATA -------------------------------- */ +#define SPIFI_IDATA_IDATA_Pos 0 /*!< SPIFI IDATA: IDATA Position */ +#define SPIFI_IDATA_IDATA_Msk (0xffffffffUL << SPIFI_IDATA_IDATA_Pos) /*!< SPIFI IDATA: IDATA Mask */ + +/* -------------------------------- SPIFI_CLIMIT -------------------------------- */ +#define SPIFI_CLIMIT_CLIMIT_Pos 0 /*!< SPIFI CLIMIT: CLIMIT Position */ +#define SPIFI_CLIMIT_CLIMIT_Msk (0xffffffffUL << SPIFI_CLIMIT_CLIMIT_Pos) /*!< SPIFI CLIMIT: CLIMIT Mask */ + +/* --------------------------------- SPIFI_DATA --------------------------------- */ +#define SPIFI_DATA_DATA_Pos 0 /*!< SPIFI DATA: DATA Position */ +#define SPIFI_DATA_DATA_Msk (0xffffffffUL << SPIFI_DATA_DATA_Pos) /*!< SPIFI DATA: DATA Mask */ + +/* --------------------------------- SPIFI_MCMD --------------------------------- */ +#define SPIFI_MCMD_POLL_Pos 14 /*!< SPIFI MCMD: POLL Position */ +#define SPIFI_MCMD_POLL_Msk (0x01UL << SPIFI_MCMD_POLL_Pos) /*!< SPIFI MCMD: POLL Mask */ +#define SPIFI_MCMD_DOUT_Pos 15 /*!< SPIFI MCMD: DOUT Position */ +#define SPIFI_MCMD_DOUT_Msk (0x01UL << SPIFI_MCMD_DOUT_Pos) /*!< SPIFI MCMD: DOUT Mask */ +#define SPIFI_MCMD_INTLEN_Pos 16 /*!< SPIFI MCMD: INTLEN Position */ +#define SPIFI_MCMD_INTLEN_Msk (0x07UL << SPIFI_MCMD_INTLEN_Pos) /*!< SPIFI MCMD: INTLEN Mask */ +#define SPIFI_MCMD_FIELDFORM_Pos 19 /*!< SPIFI MCMD: FIELDFORM Position */ +#define SPIFI_MCMD_FIELDFORM_Msk (0x03UL << SPIFI_MCMD_FIELDFORM_Pos) /*!< SPIFI MCMD: FIELDFORM Mask */ +#define SPIFI_MCMD_FRAMEFORM_Pos 21 /*!< SPIFI MCMD: FRAMEFORM Position */ +#define SPIFI_MCMD_FRAMEFORM_Msk (0x07UL << SPIFI_MCMD_FRAMEFORM_Pos) /*!< SPIFI MCMD: FRAMEFORM Mask */ +#define SPIFI_MCMD_OPCODE_Pos 24 /*!< SPIFI MCMD: OPCODE Position */ +#define SPIFI_MCMD_OPCODE_Msk (0x000000ffUL << SPIFI_MCMD_OPCODE_Pos) /*!< SPIFI MCMD: OPCODE Mask */ + +/* --------------------------------- SPIFI_STAT --------------------------------- */ +#define SPIFI_STAT_MCINIT_Pos 0 /*!< SPIFI STAT: MCINIT Position */ +#define SPIFI_STAT_MCINIT_Msk (0x01UL << SPIFI_STAT_MCINIT_Pos) /*!< SPIFI STAT: MCINIT Mask */ +#define SPIFI_STAT_CMD_Pos 1 /*!< SPIFI STAT: CMD Position */ +#define SPIFI_STAT_CMD_Msk (0x01UL << SPIFI_STAT_CMD_Pos) /*!< SPIFI STAT: CMD Mask */ +#define SPIFI_STAT_RESET_Pos 4 /*!< SPIFI STAT: RESET Position */ +#define SPIFI_STAT_RESET_Msk (0x01UL << SPIFI_STAT_RESET_Pos) /*!< SPIFI STAT: RESET Mask */ +#define SPIFI_STAT_INTRQ_Pos 5 /*!< SPIFI STAT: INTRQ Position */ +#define SPIFI_STAT_INTRQ_Msk (0x01UL << SPIFI_STAT_INTRQ_Pos) /*!< SPIFI STAT: INTRQ Mask */ +#define SPIFI_STAT_VERSION_Pos 24 /*!< SPIFI STAT: VERSION Position */ +#define SPIFI_STAT_VERSION_Msk (0x000000ffUL << SPIFI_STAT_VERSION_Pos) /*!< SPIFI STAT: VERSION Mask */ + + +/* ================================================================================ */ +/* ================ struct 'SDMMC' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- SDMMC_CTRL --------------------------------- */ +#define SDMMC_CTRL_CONTROLLER_RESET_Pos 0 /*!< SDMMC CTRL: CONTROLLER_RESET Position */ +#define SDMMC_CTRL_CONTROLLER_RESET_Msk (0x01UL << SDMMC_CTRL_CONTROLLER_RESET_Pos) /*!< SDMMC CTRL: CONTROLLER_RESET Mask */ +#define SDMMC_CTRL_FIFO_RESET_Pos 1 /*!< SDMMC CTRL: FIFO_RESET Position */ +#define SDMMC_CTRL_FIFO_RESET_Msk (0x01UL << SDMMC_CTRL_FIFO_RESET_Pos) /*!< SDMMC CTRL: FIFO_RESET Mask */ +#define SDMMC_CTRL_DMA_RESET_Pos 2 /*!< SDMMC CTRL: DMA_RESET Position */ +#define SDMMC_CTRL_DMA_RESET_Msk (0x01UL << SDMMC_CTRL_DMA_RESET_Pos) /*!< SDMMC CTRL: DMA_RESET Mask */ +#define SDMMC_CTRL_INT_ENABLE_Pos 4 /*!< SDMMC CTRL: INT_ENABLE Position */ +#define SDMMC_CTRL_INT_ENABLE_Msk (0x01UL << SDMMC_CTRL_INT_ENABLE_Pos) /*!< SDMMC CTRL: INT_ENABLE Mask */ +#define SDMMC_CTRL_READ_WAIT_Pos 6 /*!< SDMMC CTRL: READ_WAIT Position */ +#define SDMMC_CTRL_READ_WAIT_Msk (0x01UL << SDMMC_CTRL_READ_WAIT_Pos) /*!< SDMMC CTRL: READ_WAIT Mask */ +#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos 7 /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Position */ +#define SDMMC_CTRL_SEND_IRQ_RESPONSE_Msk (0x01UL << SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos) /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Mask */ +#define SDMMC_CTRL_ABORT_READ_DATA_Pos 8 /*!< SDMMC CTRL: ABORT_READ_DATA Position */ +#define SDMMC_CTRL_ABORT_READ_DATA_Msk (0x01UL << SDMMC_CTRL_ABORT_READ_DATA_Pos) /*!< SDMMC CTRL: ABORT_READ_DATA Mask */ +#define SDMMC_CTRL_SEND_CCSD_Pos 9 /*!< SDMMC CTRL: SEND_CCSD Position */ +#define SDMMC_CTRL_SEND_CCSD_Msk (0x01UL << SDMMC_CTRL_SEND_CCSD_Pos) /*!< SDMMC CTRL: SEND_CCSD Mask */ +#define SDMMC_CTRL_SEND_AUTO_STOP_Pos 10 /*!< SDMMC CTRL: SEND_AUTO_STOP Position */ +#define SDMMC_CTRL_SEND_AUTO_STOP_Msk (0x01UL << SDMMC_CTRL_SEND_AUTO_STOP_Pos) /*!< SDMMC CTRL: SEND_AUTO_STOP Mask */ +#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos 11 /*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Position */ +#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Msk (0x01UL << SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos)/*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Mask */ +#define SDMMC_CTRL_CARD_VOLTAGE_A0_Pos 16 /*!< SDMMC CTRL: CARD_VOLTAGE_A0 Position */ +#define SDMMC_CTRL_CARD_VOLTAGE_A0_Msk (0x01UL << SDMMC_CTRL_CARD_VOLTAGE_A0_Pos) /*!< SDMMC CTRL: CARD_VOLTAGE_A0 Mask */ +#define SDMMC_CTRL_CARD_VOLTAGE_A1_Pos 17 /*!< SDMMC CTRL: CARD_VOLTAGE_A1 Position */ +#define SDMMC_CTRL_CARD_VOLTAGE_A1_Msk (0x01UL << SDMMC_CTRL_CARD_VOLTAGE_A1_Pos) /*!< SDMMC CTRL: CARD_VOLTAGE_A1 Mask */ +#define SDMMC_CTRL_CARD_VOLTAGE_A2_Pos 18 /*!< SDMMC CTRL: CARD_VOLTAGE_A2 Position */ +#define SDMMC_CTRL_CARD_VOLTAGE_A2_Msk (0x01UL << SDMMC_CTRL_CARD_VOLTAGE_A2_Pos) /*!< SDMMC CTRL: CARD_VOLTAGE_A2 Mask */ +#define SDMMC_CTRL_USE_INTERNAL_DMAC_Pos 25 /*!< SDMMC CTRL: USE_INTERNAL_DMAC Position */ +#define SDMMC_CTRL_USE_INTERNAL_DMAC_Msk (0x01UL << SDMMC_CTRL_USE_INTERNAL_DMAC_Pos) /*!< SDMMC CTRL: USE_INTERNAL_DMAC Mask */ + +/* --------------------------------- SDMMC_PWREN -------------------------------- */ +#define SDMMC_PWREN_POWER_ENABLE_Pos 0 /*!< SDMMC PWREN: POWER_ENABLE Position */ +#define SDMMC_PWREN_POWER_ENABLE_Msk (0x01UL << SDMMC_PWREN_POWER_ENABLE_Pos) /*!< SDMMC PWREN: POWER_ENABLE Mask */ + +/* -------------------------------- SDMMC_CLKDIV -------------------------------- */ +#define SDMMC_CLKDIV_CLK_DIVIDER0_Pos 0 /*!< SDMMC CLKDIV: CLK_DIVIDER0 Position */ +#define SDMMC_CLKDIV_CLK_DIVIDER0_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER0_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER0 Mask */ +#define SDMMC_CLKDIV_CLK_DIVIDER1_Pos 8 /*!< SDMMC CLKDIV: CLK_DIVIDER1 Position */ +#define SDMMC_CLKDIV_CLK_DIVIDER1_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER1_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER1 Mask */ +#define SDMMC_CLKDIV_CLK_DIVIDER2_Pos 16 /*!< SDMMC CLKDIV: CLK_DIVIDER2 Position */ +#define SDMMC_CLKDIV_CLK_DIVIDER2_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER2_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER2 Mask */ +#define SDMMC_CLKDIV_CLK_DIVIDER3_Pos 24 /*!< SDMMC CLKDIV: CLK_DIVIDER3 Position */ +#define SDMMC_CLKDIV_CLK_DIVIDER3_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER3_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER3 Mask */ + +/* -------------------------------- SDMMC_CLKSRC -------------------------------- */ +#define SDMMC_CLKSRC_CLK_SOURCE_Pos 0 /*!< SDMMC CLKSRC: CLK_SOURCE Position */ +#define SDMMC_CLKSRC_CLK_SOURCE_Msk (0x03UL << SDMMC_CLKSRC_CLK_SOURCE_Pos) /*!< SDMMC CLKSRC: CLK_SOURCE Mask */ + +/* -------------------------------- SDMMC_CLKENA -------------------------------- */ +#define SDMMC_CLKENA_CCLK_ENABLE_Pos 0 /*!< SDMMC CLKENA: CCLK_ENABLE Position */ +#define SDMMC_CLKENA_CCLK_ENABLE_Msk (0x01UL << SDMMC_CLKENA_CCLK_ENABLE_Pos) /*!< SDMMC CLKENA: CCLK_ENABLE Mask */ +#define SDMMC_CLKENA_CCLK_LOW_POWER_Pos 16 /*!< SDMMC CLKENA: CCLK_LOW_POWER Position */ +#define SDMMC_CLKENA_CCLK_LOW_POWER_Msk (0x01UL << SDMMC_CLKENA_CCLK_LOW_POWER_Pos) /*!< SDMMC CLKENA: CCLK_LOW_POWER Mask */ + +/* --------------------------------- SDMMC_TMOUT -------------------------------- */ +#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos 0 /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Position */ +#define SDMMC_TMOUT_RESPONSE_TIMEOUT_Msk (0x000000ffUL << SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos) /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Mask */ +#define SDMMC_TMOUT_DATA_TIMEOUT_Pos 8 /*!< SDMMC TMOUT: DATA_TIMEOUT Position */ +#define SDMMC_TMOUT_DATA_TIMEOUT_Msk (0x00ffffffUL << SDMMC_TMOUT_DATA_TIMEOUT_Pos) /*!< SDMMC TMOUT: DATA_TIMEOUT Mask */ + +/* --------------------------------- SDMMC_CTYPE -------------------------------- */ +#define SDMMC_CTYPE_CARD_WIDTH0_Pos 0 /*!< SDMMC CTYPE: CARD_WIDTH0 Position */ +#define SDMMC_CTYPE_CARD_WIDTH0_Msk (0x01UL << SDMMC_CTYPE_CARD_WIDTH0_Pos) /*!< SDMMC CTYPE: CARD_WIDTH0 Mask */ +#define SDMMC_CTYPE_CARD_WIDTH1_Pos 16 /*!< SDMMC CTYPE: CARD_WIDTH1 Position */ +#define SDMMC_CTYPE_CARD_WIDTH1_Msk (0x01UL << SDMMC_CTYPE_CARD_WIDTH1_Pos) /*!< SDMMC CTYPE: CARD_WIDTH1 Mask */ + +/* -------------------------------- SDMMC_BLKSIZ -------------------------------- */ +#define SDMMC_BLKSIZ_BLOCK_SIZE_Pos 0 /*!< SDMMC BLKSIZ: BLOCK_SIZE Position */ +#define SDMMC_BLKSIZ_BLOCK_SIZE_Msk (0x0000ffffUL << SDMMC_BLKSIZ_BLOCK_SIZE_Pos) /*!< SDMMC BLKSIZ: BLOCK_SIZE Mask */ + +/* -------------------------------- SDMMC_BYTCNT -------------------------------- */ +#define SDMMC_BYTCNT_BYTE_COUNT_Pos 0 /*!< SDMMC BYTCNT: BYTE_COUNT Position */ +#define SDMMC_BYTCNT_BYTE_COUNT_Msk (0xffffffffUL << SDMMC_BYTCNT_BYTE_COUNT_Pos) /*!< SDMMC BYTCNT: BYTE_COUNT Mask */ + +/* -------------------------------- SDMMC_INTMASK ------------------------------- */ +#define SDMMC_INTMASK_CDET_Pos 0 /*!< SDMMC INTMASK: CDET Position */ +#define SDMMC_INTMASK_CDET_Msk (0x01UL << SDMMC_INTMASK_CDET_Pos) /*!< SDMMC INTMASK: CDET Mask */ +#define SDMMC_INTMASK_RE_Pos 1 /*!< SDMMC INTMASK: RE Position */ +#define SDMMC_INTMASK_RE_Msk (0x01UL << SDMMC_INTMASK_RE_Pos) /*!< SDMMC INTMASK: RE Mask */ +#define SDMMC_INTMASK_CDONE_Pos 2 /*!< SDMMC INTMASK: CDONE Position */ +#define SDMMC_INTMASK_CDONE_Msk (0x01UL << SDMMC_INTMASK_CDONE_Pos) /*!< SDMMC INTMASK: CDONE Mask */ +#define SDMMC_INTMASK_DTO_Pos 3 /*!< SDMMC INTMASK: DTO Position */ +#define SDMMC_INTMASK_DTO_Msk (0x01UL << SDMMC_INTMASK_DTO_Pos) /*!< SDMMC INTMASK: DTO Mask */ +#define SDMMC_INTMASK_TXDR_Pos 4 /*!< SDMMC INTMASK: TXDR Position */ +#define SDMMC_INTMASK_TXDR_Msk (0x01UL << SDMMC_INTMASK_TXDR_Pos) /*!< SDMMC INTMASK: TXDR Mask */ +#define SDMMC_INTMASK_RXDR_Pos 5 /*!< SDMMC INTMASK: RXDR Position */ +#define SDMMC_INTMASK_RXDR_Msk (0x01UL << SDMMC_INTMASK_RXDR_Pos) /*!< SDMMC INTMASK: RXDR Mask */ +#define SDMMC_INTMASK_RCRC_Pos 6 /*!< SDMMC INTMASK: RCRC Position */ +#define SDMMC_INTMASK_RCRC_Msk (0x01UL << SDMMC_INTMASK_RCRC_Pos) /*!< SDMMC INTMASK: RCRC Mask */ +#define SDMMC_INTMASK_DCRC_Pos 7 /*!< SDMMC INTMASK: DCRC Position */ +#define SDMMC_INTMASK_DCRC_Msk (0x01UL << SDMMC_INTMASK_DCRC_Pos) /*!< SDMMC INTMASK: DCRC Mask */ +#define SDMMC_INTMASK_RTO_Pos 8 /*!< SDMMC INTMASK: RTO Position */ +#define SDMMC_INTMASK_RTO_Msk (0x01UL << SDMMC_INTMASK_RTO_Pos) /*!< SDMMC INTMASK: RTO Mask */ +#define SDMMC_INTMASK_DRTO_Pos 9 /*!< SDMMC INTMASK: DRTO Position */ +#define SDMMC_INTMASK_DRTO_Msk (0x01UL << SDMMC_INTMASK_DRTO_Pos) /*!< SDMMC INTMASK: DRTO Mask */ +#define SDMMC_INTMASK_HTO_Pos 10 /*!< SDMMC INTMASK: HTO Position */ +#define SDMMC_INTMASK_HTO_Msk (0x01UL << SDMMC_INTMASK_HTO_Pos) /*!< SDMMC INTMASK: HTO Mask */ +#define SDMMC_INTMASK_FRUN_Pos 11 /*!< SDMMC INTMASK: FRUN Position */ +#define SDMMC_INTMASK_FRUN_Msk (0x01UL << SDMMC_INTMASK_FRUN_Pos) /*!< SDMMC INTMASK: FRUN Mask */ +#define SDMMC_INTMASK_HLE_Pos 12 /*!< SDMMC INTMASK: HLE Position */ +#define SDMMC_INTMASK_HLE_Msk (0x01UL << SDMMC_INTMASK_HLE_Pos) /*!< SDMMC INTMASK: HLE Mask */ +#define SDMMC_INTMASK_SBE_Pos 13 /*!< SDMMC INTMASK: SBE Position */ +#define SDMMC_INTMASK_SBE_Msk (0x01UL << SDMMC_INTMASK_SBE_Pos) /*!< SDMMC INTMASK: SBE Mask */ +#define SDMMC_INTMASK_ACD_Pos 14 /*!< SDMMC INTMASK: ACD Position */ +#define SDMMC_INTMASK_ACD_Msk (0x01UL << SDMMC_INTMASK_ACD_Pos) /*!< SDMMC INTMASK: ACD Mask */ +#define SDMMC_INTMASK_EBE_Pos 15 /*!< SDMMC INTMASK: EBE Position */ +#define SDMMC_INTMASK_EBE_Msk (0x01UL << SDMMC_INTMASK_EBE_Pos) /*!< SDMMC INTMASK: EBE Mask */ +#define SDMMC_INTMASK_SDIO_INT_MASK_Pos 16 /*!< SDMMC INTMASK: SDIO_INT_MASK Position */ +#define SDMMC_INTMASK_SDIO_INT_MASK_Msk (0x01UL << SDMMC_INTMASK_SDIO_INT_MASK_Pos) /*!< SDMMC INTMASK: SDIO_INT_MASK Mask */ + +/* -------------------------------- SDMMC_CMDARG -------------------------------- */ +#define SDMMC_CMDARG_CMD_ARG_Pos 0 /*!< SDMMC CMDARG: CMD_ARG Position */ +#define SDMMC_CMDARG_CMD_ARG_Msk (0xffffffffUL << SDMMC_CMDARG_CMD_ARG_Pos) /*!< SDMMC CMDARG: CMD_ARG Mask */ + +/* ---------------------------------- SDMMC_CMD --------------------------------- */ +#define SDMMC_CMD_CMD_INDEX_Pos 0 /*!< SDMMC CMD: CMD_INDEX Position */ +#define SDMMC_CMD_CMD_INDEX_Msk (0x3fUL << SDMMC_CMD_CMD_INDEX_Pos) /*!< SDMMC CMD: CMD_INDEX Mask */ +#define SDMMC_CMD_RESPONSE_EXPECT_Pos 6 /*!< SDMMC CMD: RESPONSE_EXPECT Position */ +#define SDMMC_CMD_RESPONSE_EXPECT_Msk (0x01UL << SDMMC_CMD_RESPONSE_EXPECT_Pos) /*!< SDMMC CMD: RESPONSE_EXPECT Mask */ +#define SDMMC_CMD_RESPONSE_LENGTH_Pos 7 /*!< SDMMC CMD: RESPONSE_LENGTH Position */ +#define SDMMC_CMD_RESPONSE_LENGTH_Msk (0x01UL << SDMMC_CMD_RESPONSE_LENGTH_Pos) /*!< SDMMC CMD: RESPONSE_LENGTH Mask */ +#define SDMMC_CMD_CHECK_RESPONSE_CRC_Pos 8 /*!< SDMMC CMD: CHECK_RESPONSE_CRC Position */ +#define SDMMC_CMD_CHECK_RESPONSE_CRC_Msk (0x01UL << SDMMC_CMD_CHECK_RESPONSE_CRC_Pos) /*!< SDMMC CMD: CHECK_RESPONSE_CRC Mask */ +#define SDMMC_CMD_DATA_EXPECTED_Pos 9 /*!< SDMMC CMD: DATA_EXPECTED Position */ +#define SDMMC_CMD_DATA_EXPECTED_Msk (0x01UL << SDMMC_CMD_DATA_EXPECTED_Pos) /*!< SDMMC CMD: DATA_EXPECTED Mask */ +#define SDMMC_CMD_READ_WRITE_Pos 10 /*!< SDMMC CMD: READ_WRITE Position */ +#define SDMMC_CMD_READ_WRITE_Msk (0x01UL << SDMMC_CMD_READ_WRITE_Pos) /*!< SDMMC CMD: READ_WRITE Mask */ +#define SDMMC_CMD_TRANSFER_MODE_Pos 11 /*!< SDMMC CMD: TRANSFER_MODE Position */ +#define SDMMC_CMD_TRANSFER_MODE_Msk (0x01UL << SDMMC_CMD_TRANSFER_MODE_Pos) /*!< SDMMC CMD: TRANSFER_MODE Mask */ +#define SDMMC_CMD_SEND_AUTO_STOP_Pos 12 /*!< SDMMC CMD: SEND_AUTO_STOP Position */ +#define SDMMC_CMD_SEND_AUTO_STOP_Msk (0x01UL << SDMMC_CMD_SEND_AUTO_STOP_Pos) /*!< SDMMC CMD: SEND_AUTO_STOP Mask */ +#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos 13 /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Position */ +#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Msk (0x01UL << SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos) /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Mask */ +#define SDMMC_CMD_STOP_ABORT_CMD_Pos 14 /*!< SDMMC CMD: STOP_ABORT_CMD Position */ +#define SDMMC_CMD_STOP_ABORT_CMD_Msk (0x01UL << SDMMC_CMD_STOP_ABORT_CMD_Pos) /*!< SDMMC CMD: STOP_ABORT_CMD Mask */ +#define SDMMC_CMD_SEND_INITIALIZATION_Pos 15 /*!< SDMMC CMD: SEND_INITIALIZATION Position */ +#define SDMMC_CMD_SEND_INITIALIZATION_Msk (0x01UL << SDMMC_CMD_SEND_INITIALIZATION_Pos) /*!< SDMMC CMD: SEND_INITIALIZATION Mask */ +#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos 21 /*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Position */ +#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Msk (0x01UL << SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos)/*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Mask */ +#define SDMMC_CMD_READ_CEATA_DEVICE_Pos 22 /*!< SDMMC CMD: READ_CEATA_DEVICE Position */ +#define SDMMC_CMD_READ_CEATA_DEVICE_Msk (0x01UL << SDMMC_CMD_READ_CEATA_DEVICE_Pos) /*!< SDMMC CMD: READ_CEATA_DEVICE Mask */ +#define SDMMC_CMD_CCS_EXPECTED_Pos 23 /*!< SDMMC CMD: CCS_EXPECTED Position */ +#define SDMMC_CMD_CCS_EXPECTED_Msk (0x01UL << SDMMC_CMD_CCS_EXPECTED_Pos) /*!< SDMMC CMD: CCS_EXPECTED Mask */ +#define SDMMC_CMD_ENABLE_BOOT_Pos 24 /*!< SDMMC CMD: ENABLE_BOOT Position */ +#define SDMMC_CMD_ENABLE_BOOT_Msk (0x01UL << SDMMC_CMD_ENABLE_BOOT_Pos) /*!< SDMMC CMD: ENABLE_BOOT Mask */ +#define SDMMC_CMD_EXPECT_BOOT_ACK_Pos 25 /*!< SDMMC CMD: EXPECT_BOOT_ACK Position */ +#define SDMMC_CMD_EXPECT_BOOT_ACK_Msk (0x01UL << SDMMC_CMD_EXPECT_BOOT_ACK_Pos) /*!< SDMMC CMD: EXPECT_BOOT_ACK Mask */ +#define SDMMC_CMD_DISABLE_BOOT_Pos 26 /*!< SDMMC CMD: DISABLE_BOOT Position */ +#define SDMMC_CMD_DISABLE_BOOT_Msk (0x01UL << SDMMC_CMD_DISABLE_BOOT_Pos) /*!< SDMMC CMD: DISABLE_BOOT Mask */ +#define SDMMC_CMD_BOOT_MODE_Pos 27 /*!< SDMMC CMD: BOOT_MODE Position */ +#define SDMMC_CMD_BOOT_MODE_Msk (0x01UL << SDMMC_CMD_BOOT_MODE_Pos) /*!< SDMMC CMD: BOOT_MODE Mask */ +#define SDMMC_CMD_VOLT_SWITCH_Pos 28 /*!< SDMMC CMD: VOLT_SWITCH Position */ +#define SDMMC_CMD_VOLT_SWITCH_Msk (0x01UL << SDMMC_CMD_VOLT_SWITCH_Pos) /*!< SDMMC CMD: VOLT_SWITCH Mask */ +#define SDMMC_CMD_START_CMD_Pos 31 /*!< SDMMC CMD: START_CMD Position */ +#define SDMMC_CMD_START_CMD_Msk (0x01UL << SDMMC_CMD_START_CMD_Pos) /*!< SDMMC CMD: START_CMD Mask */ + +/* --------------------------------- SDMMC_RESP0 -------------------------------- */ +#define SDMMC_RESP0_RESPONSE0_Pos 0 /*!< SDMMC RESP0: RESPONSE0 Position */ +#define SDMMC_RESP0_RESPONSE0_Msk (0xffffffffUL << SDMMC_RESP0_RESPONSE0_Pos) /*!< SDMMC RESP0: RESPONSE0 Mask */ + +/* --------------------------------- SDMMC_RESP1 -------------------------------- */ +#define SDMMC_RESP1_RESPONSE1_Pos 0 /*!< SDMMC RESP1: RESPONSE1 Position */ +#define SDMMC_RESP1_RESPONSE1_Msk (0xffffffffUL << SDMMC_RESP1_RESPONSE1_Pos) /*!< SDMMC RESP1: RESPONSE1 Mask */ + +/* --------------------------------- SDMMC_RESP2 -------------------------------- */ +#define SDMMC_RESP2_RESPONSE2_Pos 0 /*!< SDMMC RESP2: RESPONSE2 Position */ +#define SDMMC_RESP2_RESPONSE2_Msk (0xffffffffUL << SDMMC_RESP2_RESPONSE2_Pos) /*!< SDMMC RESP2: RESPONSE2 Mask */ + +/* --------------------------------- SDMMC_RESP3 -------------------------------- */ +#define SDMMC_RESP3_RESPONSE3_Pos 0 /*!< SDMMC RESP3: RESPONSE3 Position */ +#define SDMMC_RESP3_RESPONSE3_Msk (0xffffffffUL << SDMMC_RESP3_RESPONSE3_Pos) /*!< SDMMC RESP3: RESPONSE3 Mask */ + +/* -------------------------------- SDMMC_MINTSTS ------------------------------- */ +#define SDMMC_MINTSTS_CDET_Pos 0 /*!< SDMMC MINTSTS: CDET Position */ +#define SDMMC_MINTSTS_CDET_Msk (0x01UL << SDMMC_MINTSTS_CDET_Pos) /*!< SDMMC MINTSTS: CDET Mask */ +#define SDMMC_MINTSTS_RE_Pos 1 /*!< SDMMC MINTSTS: RE Position */ +#define SDMMC_MINTSTS_RE_Msk (0x01UL << SDMMC_MINTSTS_RE_Pos) /*!< SDMMC MINTSTS: RE Mask */ +#define SDMMC_MINTSTS_CDONE_Pos 2 /*!< SDMMC MINTSTS: CDONE Position */ +#define SDMMC_MINTSTS_CDONE_Msk (0x01UL << SDMMC_MINTSTS_CDONE_Pos) /*!< SDMMC MINTSTS: CDONE Mask */ +#define SDMMC_MINTSTS_DTO_Pos 3 /*!< SDMMC MINTSTS: DTO Position */ +#define SDMMC_MINTSTS_DTO_Msk (0x01UL << SDMMC_MINTSTS_DTO_Pos) /*!< SDMMC MINTSTS: DTO Mask */ +#define SDMMC_MINTSTS_TXDR_Pos 4 /*!< SDMMC MINTSTS: TXDR Position */ +#define SDMMC_MINTSTS_TXDR_Msk (0x01UL << SDMMC_MINTSTS_TXDR_Pos) /*!< SDMMC MINTSTS: TXDR Mask */ +#define SDMMC_MINTSTS_RXDR_Pos 5 /*!< SDMMC MINTSTS: RXDR Position */ +#define SDMMC_MINTSTS_RXDR_Msk (0x01UL << SDMMC_MINTSTS_RXDR_Pos) /*!< SDMMC MINTSTS: RXDR Mask */ +#define SDMMC_MINTSTS_RCRC_Pos 6 /*!< SDMMC MINTSTS: RCRC Position */ +#define SDMMC_MINTSTS_RCRC_Msk (0x01UL << SDMMC_MINTSTS_RCRC_Pos) /*!< SDMMC MINTSTS: RCRC Mask */ +#define SDMMC_MINTSTS_DCRC_Pos 7 /*!< SDMMC MINTSTS: DCRC Position */ +#define SDMMC_MINTSTS_DCRC_Msk (0x01UL << SDMMC_MINTSTS_DCRC_Pos) /*!< SDMMC MINTSTS: DCRC Mask */ +#define SDMMC_MINTSTS_RTO_Pos 8 /*!< SDMMC MINTSTS: RTO Position */ +#define SDMMC_MINTSTS_RTO_Msk (0x01UL << SDMMC_MINTSTS_RTO_Pos) /*!< SDMMC MINTSTS: RTO Mask */ +#define SDMMC_MINTSTS_DRTO_Pos 9 /*!< SDMMC MINTSTS: DRTO Position */ +#define SDMMC_MINTSTS_DRTO_Msk (0x01UL << SDMMC_MINTSTS_DRTO_Pos) /*!< SDMMC MINTSTS: DRTO Mask */ +#define SDMMC_MINTSTS_HTO_Pos 10 /*!< SDMMC MINTSTS: HTO Position */ +#define SDMMC_MINTSTS_HTO_Msk (0x01UL << SDMMC_MINTSTS_HTO_Pos) /*!< SDMMC MINTSTS: HTO Mask */ +#define SDMMC_MINTSTS_FRUN_Pos 11 /*!< SDMMC MINTSTS: FRUN Position */ +#define SDMMC_MINTSTS_FRUN_Msk (0x01UL << SDMMC_MINTSTS_FRUN_Pos) /*!< SDMMC MINTSTS: FRUN Mask */ +#define SDMMC_MINTSTS_HLE_Pos 12 /*!< SDMMC MINTSTS: HLE Position */ +#define SDMMC_MINTSTS_HLE_Msk (0x01UL << SDMMC_MINTSTS_HLE_Pos) /*!< SDMMC MINTSTS: HLE Mask */ +#define SDMMC_MINTSTS_SBE_Pos 13 /*!< SDMMC MINTSTS: SBE Position */ +#define SDMMC_MINTSTS_SBE_Msk (0x01UL << SDMMC_MINTSTS_SBE_Pos) /*!< SDMMC MINTSTS: SBE Mask */ +#define SDMMC_MINTSTS_ACD_Pos 14 /*!< SDMMC MINTSTS: ACD Position */ +#define SDMMC_MINTSTS_ACD_Msk (0x01UL << SDMMC_MINTSTS_ACD_Pos) /*!< SDMMC MINTSTS: ACD Mask */ +#define SDMMC_MINTSTS_EBE_Pos 15 /*!< SDMMC MINTSTS: EBE Position */ +#define SDMMC_MINTSTS_EBE_Msk (0x01UL << SDMMC_MINTSTS_EBE_Pos) /*!< SDMMC MINTSTS: EBE Mask */ +#define SDMMC_MINTSTS_SDIO_INTERRUPT_Pos 16 /*!< SDMMC MINTSTS: SDIO_INTERRUPT Position */ +#define SDMMC_MINTSTS_SDIO_INTERRUPT_Msk (0x01UL << SDMMC_MINTSTS_SDIO_INTERRUPT_Pos) /*!< SDMMC MINTSTS: SDIO_INTERRUPT Mask */ + +/* -------------------------------- SDMMC_RINTSTS ------------------------------- */ +#define SDMMC_RINTSTS_CDET_Pos 0 /*!< SDMMC RINTSTS: CDET Position */ +#define SDMMC_RINTSTS_CDET_Msk (0x01UL << SDMMC_RINTSTS_CDET_Pos) /*!< SDMMC RINTSTS: CDET Mask */ +#define SDMMC_RINTSTS_RE_Pos 1 /*!< SDMMC RINTSTS: RE Position */ +#define SDMMC_RINTSTS_RE_Msk (0x01UL << SDMMC_RINTSTS_RE_Pos) /*!< SDMMC RINTSTS: RE Mask */ +#define SDMMC_RINTSTS_CDONE_Pos 2 /*!< SDMMC RINTSTS: CDONE Position */ +#define SDMMC_RINTSTS_CDONE_Msk (0x01UL << SDMMC_RINTSTS_CDONE_Pos) /*!< SDMMC RINTSTS: CDONE Mask */ +#define SDMMC_RINTSTS_DTO_Pos 3 /*!< SDMMC RINTSTS: DTO Position */ +#define SDMMC_RINTSTS_DTO_Msk (0x01UL << SDMMC_RINTSTS_DTO_Pos) /*!< SDMMC RINTSTS: DTO Mask */ +#define SDMMC_RINTSTS_TXDR_Pos 4 /*!< SDMMC RINTSTS: TXDR Position */ +#define SDMMC_RINTSTS_TXDR_Msk (0x01UL << SDMMC_RINTSTS_TXDR_Pos) /*!< SDMMC RINTSTS: TXDR Mask */ +#define SDMMC_RINTSTS_RXDR_Pos 5 /*!< SDMMC RINTSTS: RXDR Position */ +#define SDMMC_RINTSTS_RXDR_Msk (0x01UL << SDMMC_RINTSTS_RXDR_Pos) /*!< SDMMC RINTSTS: RXDR Mask */ +#define SDMMC_RINTSTS_RCRC_Pos 6 /*!< SDMMC RINTSTS: RCRC Position */ +#define SDMMC_RINTSTS_RCRC_Msk (0x01UL << SDMMC_RINTSTS_RCRC_Pos) /*!< SDMMC RINTSTS: RCRC Mask */ +#define SDMMC_RINTSTS_DCRC_Pos 7 /*!< SDMMC RINTSTS: DCRC Position */ +#define SDMMC_RINTSTS_DCRC_Msk (0x01UL << SDMMC_RINTSTS_DCRC_Pos) /*!< SDMMC RINTSTS: DCRC Mask */ +#define SDMMC_RINTSTS_RTO_BAR_Pos 8 /*!< SDMMC RINTSTS: RTO_BAR Position */ +#define SDMMC_RINTSTS_RTO_BAR_Msk (0x01UL << SDMMC_RINTSTS_RTO_BAR_Pos) /*!< SDMMC RINTSTS: RTO_BAR Mask */ +#define SDMMC_RINTSTS_DRTO_BDS_Pos 9 /*!< SDMMC RINTSTS: DRTO_BDS Position */ +#define SDMMC_RINTSTS_DRTO_BDS_Msk (0x01UL << SDMMC_RINTSTS_DRTO_BDS_Pos) /*!< SDMMC RINTSTS: DRTO_BDS Mask */ +#define SDMMC_RINTSTS_HTO_Pos 10 /*!< SDMMC RINTSTS: HTO Position */ +#define SDMMC_RINTSTS_HTO_Msk (0x01UL << SDMMC_RINTSTS_HTO_Pos) /*!< SDMMC RINTSTS: HTO Mask */ +#define SDMMC_RINTSTS_FRUN_Pos 11 /*!< SDMMC RINTSTS: FRUN Position */ +#define SDMMC_RINTSTS_FRUN_Msk (0x01UL << SDMMC_RINTSTS_FRUN_Pos) /*!< SDMMC RINTSTS: FRUN Mask */ +#define SDMMC_RINTSTS_HLE_Pos 12 /*!< SDMMC RINTSTS: HLE Position */ +#define SDMMC_RINTSTS_HLE_Msk (0x01UL << SDMMC_RINTSTS_HLE_Pos) /*!< SDMMC RINTSTS: HLE Mask */ +#define SDMMC_RINTSTS_SBE_Pos 13 /*!< SDMMC RINTSTS: SBE Position */ +#define SDMMC_RINTSTS_SBE_Msk (0x01UL << SDMMC_RINTSTS_SBE_Pos) /*!< SDMMC RINTSTS: SBE Mask */ +#define SDMMC_RINTSTS_ACD_Pos 14 /*!< SDMMC RINTSTS: ACD Position */ +#define SDMMC_RINTSTS_ACD_Msk (0x01UL << SDMMC_RINTSTS_ACD_Pos) /*!< SDMMC RINTSTS: ACD Mask */ +#define SDMMC_RINTSTS_EBE_Pos 15 /*!< SDMMC RINTSTS: EBE Position */ +#define SDMMC_RINTSTS_EBE_Msk (0x01UL << SDMMC_RINTSTS_EBE_Pos) /*!< SDMMC RINTSTS: EBE Mask */ +#define SDMMC_RINTSTS_SDIO_INTERRUPT_Pos 16 /*!< SDMMC RINTSTS: SDIO_INTERRUPT Position */ +#define SDMMC_RINTSTS_SDIO_INTERRUPT_Msk (0x01UL << SDMMC_RINTSTS_SDIO_INTERRUPT_Pos) /*!< SDMMC RINTSTS: SDIO_INTERRUPT Mask */ + +/* -------------------------------- SDMMC_STATUS -------------------------------- */ +#define SDMMC_STATUS_FIFO_RX_WATERMARK_Pos 0 /*!< SDMMC STATUS: FIFO_RX_WATERMARK Position */ +#define SDMMC_STATUS_FIFO_RX_WATERMARK_Msk (0x01UL << SDMMC_STATUS_FIFO_RX_WATERMARK_Pos) /*!< SDMMC STATUS: FIFO_RX_WATERMARK Mask */ +#define SDMMC_STATUS_FIFO_TX_WATERMARK_Pos 1 /*!< SDMMC STATUS: FIFO_TX_WATERMARK Position */ +#define SDMMC_STATUS_FIFO_TX_WATERMARK_Msk (0x01UL << SDMMC_STATUS_FIFO_TX_WATERMARK_Pos) /*!< SDMMC STATUS: FIFO_TX_WATERMARK Mask */ +#define SDMMC_STATUS_FIFO_EMPTY_Pos 2 /*!< SDMMC STATUS: FIFO_EMPTY Position */ +#define SDMMC_STATUS_FIFO_EMPTY_Msk (0x01UL << SDMMC_STATUS_FIFO_EMPTY_Pos) /*!< SDMMC STATUS: FIFO_EMPTY Mask */ +#define SDMMC_STATUS_FIFO_FULL_Pos 3 /*!< SDMMC STATUS: FIFO_FULL Position */ +#define SDMMC_STATUS_FIFO_FULL_Msk (0x01UL << SDMMC_STATUS_FIFO_FULL_Pos) /*!< SDMMC STATUS: FIFO_FULL Mask */ +#define SDMMC_STATUS_CMDFSMSTATES_Pos 4 /*!< SDMMC STATUS: CMDFSMSTATES Position */ +#define SDMMC_STATUS_CMDFSMSTATES_Msk (0x0fUL << SDMMC_STATUS_CMDFSMSTATES_Pos) /*!< SDMMC STATUS: CMDFSMSTATES Mask */ +#define SDMMC_STATUS_DATA_3_STATUS_Pos 8 /*!< SDMMC STATUS: DATA_3_STATUS Position */ +#define SDMMC_STATUS_DATA_3_STATUS_Msk (0x01UL << SDMMC_STATUS_DATA_3_STATUS_Pos) /*!< SDMMC STATUS: DATA_3_STATUS Mask */ +#define SDMMC_STATUS_DATA_BUSY_Pos 9 /*!< SDMMC STATUS: DATA_BUSY Position */ +#define SDMMC_STATUS_DATA_BUSY_Msk (0x01UL << SDMMC_STATUS_DATA_BUSY_Pos) /*!< SDMMC STATUS: DATA_BUSY Mask */ +#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos 10 /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Position */ +#define SDMMC_STATUS_DATA_STATE_MC_BUSY_Msk (0x01UL << SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos) /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Mask */ +#define SDMMC_STATUS_RESPONSE_INDEX_Pos 11 /*!< SDMMC STATUS: RESPONSE_INDEX Position */ +#define SDMMC_STATUS_RESPONSE_INDEX_Msk (0x3fUL << SDMMC_STATUS_RESPONSE_INDEX_Pos) /*!< SDMMC STATUS: RESPONSE_INDEX Mask */ +#define SDMMC_STATUS_FIFO_COUNT_Pos 17 /*!< SDMMC STATUS: FIFO_COUNT Position */ +#define SDMMC_STATUS_FIFO_COUNT_Msk (0x00001fffUL << SDMMC_STATUS_FIFO_COUNT_Pos) /*!< SDMMC STATUS: FIFO_COUNT Mask */ +#define SDMMC_STATUS_DMA_ACK_Pos 30 /*!< SDMMC STATUS: DMA_ACK Position */ +#define SDMMC_STATUS_DMA_ACK_Msk (0x01UL << SDMMC_STATUS_DMA_ACK_Pos) /*!< SDMMC STATUS: DMA_ACK Mask */ +#define SDMMC_STATUS_DMA_REQ_Pos 31 /*!< SDMMC STATUS: DMA_REQ Position */ +#define SDMMC_STATUS_DMA_REQ_Msk (0x01UL << SDMMC_STATUS_DMA_REQ_Pos) /*!< SDMMC STATUS: DMA_REQ Mask */ + +/* -------------------------------- SDMMC_FIFOTH -------------------------------- */ +#define SDMMC_FIFOTH_TX_WMARK_Pos 0 /*!< SDMMC FIFOTH: TX_WMARK Position */ +#define SDMMC_FIFOTH_TX_WMARK_Msk (0x00000fffUL << SDMMC_FIFOTH_TX_WMARK_Pos) /*!< SDMMC FIFOTH: TX_WMARK Mask */ +#define SDMMC_FIFOTH_RX_WMARK_Pos 16 /*!< SDMMC FIFOTH: RX_WMARK Position */ +#define SDMMC_FIFOTH_RX_WMARK_Msk (0x00000fffUL << SDMMC_FIFOTH_RX_WMARK_Pos) /*!< SDMMC FIFOTH: RX_WMARK Mask */ +#define SDMMC_FIFOTH_DMA_MTS_Pos 28 /*!< SDMMC FIFOTH: DMA_MTS Position */ +#define SDMMC_FIFOTH_DMA_MTS_Msk (0x07UL << SDMMC_FIFOTH_DMA_MTS_Pos) /*!< SDMMC FIFOTH: DMA_MTS Mask */ + +/* -------------------------------- SDMMC_CDETECT ------------------------------- */ +#define SDMMC_CDETECT_CARD_DETECT_Pos 0 /*!< SDMMC CDETECT: CARD_DETECT Position */ +#define SDMMC_CDETECT_CARD_DETECT_Msk (0x01UL << SDMMC_CDETECT_CARD_DETECT_Pos) /*!< SDMMC CDETECT: CARD_DETECT Mask */ + +/* -------------------------------- SDMMC_WRTPRT -------------------------------- */ +#define SDMMC_WRTPRT_WRITE_PROTECT_Pos 0 /*!< SDMMC WRTPRT: WRITE_PROTECT Position */ +#define SDMMC_WRTPRT_WRITE_PROTECT_Msk (0x01UL << SDMMC_WRTPRT_WRITE_PROTECT_Pos) /*!< SDMMC WRTPRT: WRITE_PROTECT Mask */ + +/* -------------------------------- SDMMC_TCBCNT -------------------------------- */ +#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos 0 /*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Position */ +#define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Msk (0xffffffffUL << SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos)/*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Mask */ + +/* -------------------------------- SDMMC_TBBCNT -------------------------------- */ +#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos 0 /*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Position */ +#define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Msk (0xffffffffUL << SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos)/*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Mask */ + +/* -------------------------------- SDMMC_DEBNCE -------------------------------- */ +#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos 0 /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Position */ +#define SDMMC_DEBNCE_DEBOUNCE_COUNT_Msk (0x00ffffffUL << SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos) /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Mask */ + +/* --------------------------------- SDMMC_RST_N -------------------------------- */ +#define SDMMC_RST_N_CARD_RESET_Pos 0 /*!< SDMMC RST_N: CARD_RESET Position */ +#define SDMMC_RST_N_CARD_RESET_Msk (0x01UL << SDMMC_RST_N_CARD_RESET_Pos) /*!< SDMMC RST_N: CARD_RESET Mask */ + +/* --------------------------------- SDMMC_BMOD --------------------------------- */ +#define SDMMC_BMOD_SWR_Pos 0 /*!< SDMMC BMOD: SWR Position */ +#define SDMMC_BMOD_SWR_Msk (0x01UL << SDMMC_BMOD_SWR_Pos) /*!< SDMMC BMOD: SWR Mask */ +#define SDMMC_BMOD_FB_Pos 1 /*!< SDMMC BMOD: FB Position */ +#define SDMMC_BMOD_FB_Msk (0x01UL << SDMMC_BMOD_FB_Pos) /*!< SDMMC BMOD: FB Mask */ +#define SDMMC_BMOD_DSL_Pos 2 /*!< SDMMC BMOD: DSL Position */ +#define SDMMC_BMOD_DSL_Msk (0x1fUL << SDMMC_BMOD_DSL_Pos) /*!< SDMMC BMOD: DSL Mask */ +#define SDMMC_BMOD_DE_Pos 7 /*!< SDMMC BMOD: DE Position */ +#define SDMMC_BMOD_DE_Msk (0x01UL << SDMMC_BMOD_DE_Pos) /*!< SDMMC BMOD: DE Mask */ +#define SDMMC_BMOD_PBL_Pos 8 /*!< SDMMC BMOD: PBL Position */ +#define SDMMC_BMOD_PBL_Msk (0x07UL << SDMMC_BMOD_PBL_Pos) /*!< SDMMC BMOD: PBL Mask */ + +/* -------------------------------- SDMMC_PLDMND -------------------------------- */ +#define SDMMC_PLDMND_PD_Pos 0 /*!< SDMMC PLDMND: PD Position */ +#define SDMMC_PLDMND_PD_Msk (0xffffffffUL << SDMMC_PLDMND_PD_Pos) /*!< SDMMC PLDMND: PD Mask */ + +/* -------------------------------- SDMMC_DBADDR -------------------------------- */ +#define SDMMC_DBADDR_SDL_Pos 0 /*!< SDMMC DBADDR: SDL Position */ +#define SDMMC_DBADDR_SDL_Msk (0xffffffffUL << SDMMC_DBADDR_SDL_Pos) /*!< SDMMC DBADDR: SDL Mask */ + +/* --------------------------------- SDMMC_IDSTS -------------------------------- */ +#define SDMMC_IDSTS_TI_Pos 0 /*!< SDMMC IDSTS: TI Position */ +#define SDMMC_IDSTS_TI_Msk (0x01UL << SDMMC_IDSTS_TI_Pos) /*!< SDMMC IDSTS: TI Mask */ +#define SDMMC_IDSTS_RI_Pos 1 /*!< SDMMC IDSTS: RI Position */ +#define SDMMC_IDSTS_RI_Msk (0x01UL << SDMMC_IDSTS_RI_Pos) /*!< SDMMC IDSTS: RI Mask */ +#define SDMMC_IDSTS_FBE_Pos 2 /*!< SDMMC IDSTS: FBE Position */ +#define SDMMC_IDSTS_FBE_Msk (0x01UL << SDMMC_IDSTS_FBE_Pos) /*!< SDMMC IDSTS: FBE Mask */ +#define SDMMC_IDSTS_DU_Pos 4 /*!< SDMMC IDSTS: DU Position */ +#define SDMMC_IDSTS_DU_Msk (0x01UL << SDMMC_IDSTS_DU_Pos) /*!< SDMMC IDSTS: DU Mask */ +#define SDMMC_IDSTS_CES_Pos 5 /*!< SDMMC IDSTS: CES Position */ +#define SDMMC_IDSTS_CES_Msk (0x01UL << SDMMC_IDSTS_CES_Pos) /*!< SDMMC IDSTS: CES Mask */ +#define SDMMC_IDSTS_NIS_Pos 8 /*!< SDMMC IDSTS: NIS Position */ +#define SDMMC_IDSTS_NIS_Msk (0x01UL << SDMMC_IDSTS_NIS_Pos) /*!< SDMMC IDSTS: NIS Mask */ +#define SDMMC_IDSTS_AIS_Pos 9 /*!< SDMMC IDSTS: AIS Position */ +#define SDMMC_IDSTS_AIS_Msk (0x01UL << SDMMC_IDSTS_AIS_Pos) /*!< SDMMC IDSTS: AIS Mask */ +#define SDMMC_IDSTS_EB_Pos 10 /*!< SDMMC IDSTS: EB Position */ +#define SDMMC_IDSTS_EB_Msk (0x07UL << SDMMC_IDSTS_EB_Pos) /*!< SDMMC IDSTS: EB Mask */ +#define SDMMC_IDSTS_FSM_Pos 13 /*!< SDMMC IDSTS: FSM Position */ +#define SDMMC_IDSTS_FSM_Msk (0x0fUL << SDMMC_IDSTS_FSM_Pos) /*!< SDMMC IDSTS: FSM Mask */ + +/* -------------------------------- SDMMC_IDINTEN ------------------------------- */ +#define SDMMC_IDINTEN_TI_Pos 0 /*!< SDMMC IDINTEN: TI Position */ +#define SDMMC_IDINTEN_TI_Msk (0x01UL << SDMMC_IDINTEN_TI_Pos) /*!< SDMMC IDINTEN: TI Mask */ +#define SDMMC_IDINTEN_RI_Pos 1 /*!< SDMMC IDINTEN: RI Position */ +#define SDMMC_IDINTEN_RI_Msk (0x01UL << SDMMC_IDINTEN_RI_Pos) /*!< SDMMC IDINTEN: RI Mask */ +#define SDMMC_IDINTEN_FBE_Pos 2 /*!< SDMMC IDINTEN: FBE Position */ +#define SDMMC_IDINTEN_FBE_Msk (0x01UL << SDMMC_IDINTEN_FBE_Pos) /*!< SDMMC IDINTEN: FBE Mask */ +#define SDMMC_IDINTEN_DU_Pos 4 /*!< SDMMC IDINTEN: DU Position */ +#define SDMMC_IDINTEN_DU_Msk (0x01UL << SDMMC_IDINTEN_DU_Pos) /*!< SDMMC IDINTEN: DU Mask */ +#define SDMMC_IDINTEN_CES_Pos 5 /*!< SDMMC IDINTEN: CES Position */ +#define SDMMC_IDINTEN_CES_Msk (0x01UL << SDMMC_IDINTEN_CES_Pos) /*!< SDMMC IDINTEN: CES Mask */ +#define SDMMC_IDINTEN_NIS_Pos 8 /*!< SDMMC IDINTEN: NIS Position */ +#define SDMMC_IDINTEN_NIS_Msk (0x01UL << SDMMC_IDINTEN_NIS_Pos) /*!< SDMMC IDINTEN: NIS Mask */ +#define SDMMC_IDINTEN_AIS_Pos 9 /*!< SDMMC IDINTEN: AIS Position */ +#define SDMMC_IDINTEN_AIS_Msk (0x01UL << SDMMC_IDINTEN_AIS_Pos) /*!< SDMMC IDINTEN: AIS Mask */ + +/* -------------------------------- SDMMC_DSCADDR ------------------------------- */ +#define SDMMC_DSCADDR_HDA_Pos 0 /*!< SDMMC DSCADDR: HDA Position */ +#define SDMMC_DSCADDR_HDA_Msk (0xffffffffUL << SDMMC_DSCADDR_HDA_Pos) /*!< SDMMC DSCADDR: HDA Mask */ + +/* -------------------------------- SDMMC_BUFADDR ------------------------------- */ +#define SDMMC_BUFADDR_HBA_Pos 0 /*!< SDMMC BUFADDR: HBA Position */ +#define SDMMC_BUFADDR_HBA_Msk (0xffffffffUL << SDMMC_BUFADDR_HBA_Pos) /*!< SDMMC BUFADDR: HBA Mask */ + + +/* ================================================================================ */ +/* ================ struct 'EMC' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- EMC_CONTROL -------------------------------- */ +#define EMC_CONTROL_E_Pos 0 /*!< EMC CONTROL: E Position */ +#define EMC_CONTROL_E_Msk (0x01UL << EMC_CONTROL_E_Pos) /*!< EMC CONTROL: E Mask */ +#define EMC_CONTROL_M_Pos 1 /*!< EMC CONTROL: M Position */ +#define EMC_CONTROL_M_Msk (0x01UL << EMC_CONTROL_M_Pos) /*!< EMC CONTROL: M Mask */ +#define EMC_CONTROL_L_Pos 2 /*!< EMC CONTROL: L Position */ +#define EMC_CONTROL_L_Msk (0x01UL << EMC_CONTROL_L_Pos) /*!< EMC CONTROL: L Mask */ + +/* --------------------------------- EMC_STATUS --------------------------------- */ +#define EMC_STATUS_B_Pos 0 /*!< EMC STATUS: B Position */ +#define EMC_STATUS_B_Msk (0x01UL << EMC_STATUS_B_Pos) /*!< EMC STATUS: B Mask */ +#define EMC_STATUS_S_Pos 1 /*!< EMC STATUS: S Position */ +#define EMC_STATUS_S_Msk (0x01UL << EMC_STATUS_S_Pos) /*!< EMC STATUS: S Mask */ +#define EMC_STATUS_SA_Pos 2 /*!< EMC STATUS: SA Position */ +#define EMC_STATUS_SA_Msk (0x01UL << EMC_STATUS_SA_Pos) /*!< EMC STATUS: SA Mask */ + +/* --------------------------------- EMC_CONFIG --------------------------------- */ +#define EMC_CONFIG_EM_Pos 0 /*!< EMC CONFIG: EM Position */ +#define EMC_CONFIG_EM_Msk (0x01UL << EMC_CONFIG_EM_Pos) /*!< EMC CONFIG: EM Mask */ + +/* ----------------------------- EMC_DYNAMICCONTROL ----------------------------- */ +#define EMC_DYNAMICCONTROL_CE_Pos 0 /*!< EMC DYNAMICCONTROL: CE Position */ +#define EMC_DYNAMICCONTROL_CE_Msk (0x01UL << EMC_DYNAMICCONTROL_CE_Pos) /*!< EMC DYNAMICCONTROL: CE Mask */ +#define EMC_DYNAMICCONTROL_CS_Pos 1 /*!< EMC DYNAMICCONTROL: CS Position */ +#define EMC_DYNAMICCONTROL_CS_Msk (0x01UL << EMC_DYNAMICCONTROL_CS_Pos) /*!< EMC DYNAMICCONTROL: CS Mask */ +#define EMC_DYNAMICCONTROL_SR_Pos 2 /*!< EMC DYNAMICCONTROL: SR Position */ +#define EMC_DYNAMICCONTROL_SR_Msk (0x01UL << EMC_DYNAMICCONTROL_SR_Pos) /*!< EMC DYNAMICCONTROL: SR Mask */ +#define EMC_DYNAMICCONTROL_MMC_Pos 5 /*!< EMC DYNAMICCONTROL: MMC Position */ +#define EMC_DYNAMICCONTROL_MMC_Msk (0x01UL << EMC_DYNAMICCONTROL_MMC_Pos) /*!< EMC DYNAMICCONTROL: MMC Mask */ +#define EMC_DYNAMICCONTROL_I_Pos 7 /*!< EMC DYNAMICCONTROL: I Position */ +#define EMC_DYNAMICCONTROL_I_Msk (0x03UL << EMC_DYNAMICCONTROL_I_Pos) /*!< EMC DYNAMICCONTROL: I Mask */ + +/* ----------------------------- EMC_DYNAMICREFRESH ----------------------------- */ +#define EMC_DYNAMICREFRESH_REFRESH_Pos 0 /*!< EMC DYNAMICREFRESH: REFRESH Position */ +#define EMC_DYNAMICREFRESH_REFRESH_Msk (0x000007ffUL << EMC_DYNAMICREFRESH_REFRESH_Pos) /*!< EMC DYNAMICREFRESH: REFRESH Mask */ + +/* ---------------------------- EMC_DYNAMICREADCONFIG --------------------------- */ +#define EMC_DYNAMICREADCONFIG_RD_Pos 0 /*!< EMC DYNAMICREADCONFIG: RD Position */ +#define EMC_DYNAMICREADCONFIG_RD_Msk (0x03UL << EMC_DYNAMICREADCONFIG_RD_Pos) /*!< EMC DYNAMICREADCONFIG: RD Mask */ + +/* -------------------------------- EMC_DYNAMICRP ------------------------------- */ +#define EMC_DYNAMICRP_TRP_Pos 0 /*!< EMC DYNAMICRP: TRP Position */ +#define EMC_DYNAMICRP_TRP_Msk (0x0fUL << EMC_DYNAMICRP_TRP_Pos) /*!< EMC DYNAMICRP: TRP Mask */ + +/* ------------------------------- EMC_DYNAMICRAS ------------------------------- */ +#define EMC_DYNAMICRAS_TRAS_Pos 0 /*!< EMC DYNAMICRAS: TRAS Position */ +#define EMC_DYNAMICRAS_TRAS_Msk (0x0fUL << EMC_DYNAMICRAS_TRAS_Pos) /*!< EMC DYNAMICRAS: TRAS Mask */ + +/* ------------------------------- EMC_DYNAMICSREX ------------------------------ */ +#define EMC_DYNAMICSREX_TSREX_Pos 0 /*!< EMC DYNAMICSREX: TSREX Position */ +#define EMC_DYNAMICSREX_TSREX_Msk (0x0fUL << EMC_DYNAMICSREX_TSREX_Pos) /*!< EMC DYNAMICSREX: TSREX Mask */ + +/* ------------------------------- EMC_DYNAMICAPR ------------------------------- */ +#define EMC_DYNAMICAPR_TAPR_Pos 0 /*!< EMC DYNAMICAPR: TAPR Position */ +#define EMC_DYNAMICAPR_TAPR_Msk (0x0fUL << EMC_DYNAMICAPR_TAPR_Pos) /*!< EMC DYNAMICAPR: TAPR Mask */ + +/* ------------------------------- EMC_DYNAMICDAL ------------------------------- */ +#define EMC_DYNAMICDAL_TDAL_Pos 0 /*!< EMC DYNAMICDAL: TDAL Position */ +#define EMC_DYNAMICDAL_TDAL_Msk (0x0fUL << EMC_DYNAMICDAL_TDAL_Pos) /*!< EMC DYNAMICDAL: TDAL Mask */ + +/* -------------------------------- EMC_DYNAMICWR ------------------------------- */ +#define EMC_DYNAMICWR_TWR_Pos 0 /*!< EMC DYNAMICWR: TWR Position */ +#define EMC_DYNAMICWR_TWR_Msk (0x0fUL << EMC_DYNAMICWR_TWR_Pos) /*!< EMC DYNAMICWR: TWR Mask */ + +/* -------------------------------- EMC_DYNAMICRC ------------------------------- */ +#define EMC_DYNAMICRC_TRC_Pos 0 /*!< EMC DYNAMICRC: TRC Position */ +#define EMC_DYNAMICRC_TRC_Msk (0x1fUL << EMC_DYNAMICRC_TRC_Pos) /*!< EMC DYNAMICRC: TRC Mask */ + +/* ------------------------------- EMC_DYNAMICRFC ------------------------------- */ +#define EMC_DYNAMICRFC_TRFC_Pos 0 /*!< EMC DYNAMICRFC: TRFC Position */ +#define EMC_DYNAMICRFC_TRFC_Msk (0x1fUL << EMC_DYNAMICRFC_TRFC_Pos) /*!< EMC DYNAMICRFC: TRFC Mask */ + +/* ------------------------------- EMC_DYNAMICXSR ------------------------------- */ +#define EMC_DYNAMICXSR_TXSR_Pos 0 /*!< EMC DYNAMICXSR: TXSR Position */ +#define EMC_DYNAMICXSR_TXSR_Msk (0x1fUL << EMC_DYNAMICXSR_TXSR_Pos) /*!< EMC DYNAMICXSR: TXSR Mask */ + +/* ------------------------------- EMC_DYNAMICRRD ------------------------------- */ +#define EMC_DYNAMICRRD_TRRD_Pos 0 /*!< EMC DYNAMICRRD: TRRD Position */ +#define EMC_DYNAMICRRD_TRRD_Msk (0x0fUL << EMC_DYNAMICRRD_TRRD_Pos) /*!< EMC DYNAMICRRD: TRRD Mask */ + +/* ------------------------------- EMC_DYNAMICMRD ------------------------------- */ +#define EMC_DYNAMICMRD_TMRD_Pos 0 /*!< EMC DYNAMICMRD: TMRD Position */ +#define EMC_DYNAMICMRD_TMRD_Msk (0x0fUL << EMC_DYNAMICMRD_TMRD_Pos) /*!< EMC DYNAMICMRD: TMRD Mask */ + +/* --------------------------- EMC_STATICEXTENDEDWAIT --------------------------- */ +#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos 0 /*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Position */ +#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Msk (0x000003ffUL << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos)/*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Mask */ + +/* ----------------------------- EMC_DYNAMICCONFIG0 ----------------------------- */ +#define EMC_DYNAMICCONFIG0_MD_Pos 3 /*!< EMC DYNAMICCONFIG0: MD Position */ +#define EMC_DYNAMICCONFIG0_MD_Msk (0x03UL << EMC_DYNAMICCONFIG0_MD_Pos) /*!< EMC DYNAMICCONFIG0: MD Mask */ +#define EMC_DYNAMICCONFIG0_AM0_Pos 7 /*!< EMC DYNAMICCONFIG0: AM0 Position */ +#define EMC_DYNAMICCONFIG0_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG0_AM0_Pos) /*!< EMC DYNAMICCONFIG0: AM0 Mask */ +#define EMC_DYNAMICCONFIG0_AM1_Pos 14 /*!< EMC DYNAMICCONFIG0: AM1 Position */ +#define EMC_DYNAMICCONFIG0_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG0_AM1_Pos) /*!< EMC DYNAMICCONFIG0: AM1 Mask */ +#define EMC_DYNAMICCONFIG0_B_Pos 19 /*!< EMC DYNAMICCONFIG0: B Position */ +#define EMC_DYNAMICCONFIG0_B_Msk (0x01UL << EMC_DYNAMICCONFIG0_B_Pos) /*!< EMC DYNAMICCONFIG0: B Mask */ +#define EMC_DYNAMICCONFIG0_P_Pos 20 /*!< EMC DYNAMICCONFIG0: P Position */ +#define EMC_DYNAMICCONFIG0_P_Msk (0x01UL << EMC_DYNAMICCONFIG0_P_Pos) /*!< EMC DYNAMICCONFIG0: P Mask */ + +/* ----------------------------- EMC_DYNAMICRASCAS0 ----------------------------- */ +#define EMC_DYNAMICRASCAS0_RAS_Pos 0 /*!< EMC DYNAMICRASCAS0: RAS Position */ +#define EMC_DYNAMICRASCAS0_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS0_RAS_Pos) /*!< EMC DYNAMICRASCAS0: RAS Mask */ +#define EMC_DYNAMICRASCAS0_CAS_Pos 8 /*!< EMC DYNAMICRASCAS0: CAS Position */ +#define EMC_DYNAMICRASCAS0_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS0_CAS_Pos) /*!< EMC DYNAMICRASCAS0: CAS Mask */ + +/* ----------------------------- EMC_DYNAMICCONFIG1 ----------------------------- */ +#define EMC_DYNAMICCONFIG1_MD_Pos 3 /*!< EMC DYNAMICCONFIG1: MD Position */ +#define EMC_DYNAMICCONFIG1_MD_Msk (0x03UL << EMC_DYNAMICCONFIG1_MD_Pos) /*!< EMC DYNAMICCONFIG1: MD Mask */ +#define EMC_DYNAMICCONFIG1_AM0_Pos 7 /*!< EMC DYNAMICCONFIG1: AM0 Position */ +#define EMC_DYNAMICCONFIG1_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG1_AM0_Pos) /*!< EMC DYNAMICCONFIG1: AM0 Mask */ +#define EMC_DYNAMICCONFIG1_AM1_Pos 14 /*!< EMC DYNAMICCONFIG1: AM1 Position */ +#define EMC_DYNAMICCONFIG1_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG1_AM1_Pos) /*!< EMC DYNAMICCONFIG1: AM1 Mask */ +#define EMC_DYNAMICCONFIG1_B_Pos 19 /*!< EMC DYNAMICCONFIG1: B Position */ +#define EMC_DYNAMICCONFIG1_B_Msk (0x01UL << EMC_DYNAMICCONFIG1_B_Pos) /*!< EMC DYNAMICCONFIG1: B Mask */ +#define EMC_DYNAMICCONFIG1_P_Pos 20 /*!< EMC DYNAMICCONFIG1: P Position */ +#define EMC_DYNAMICCONFIG1_P_Msk (0x01UL << EMC_DYNAMICCONFIG1_P_Pos) /*!< EMC DYNAMICCONFIG1: P Mask */ + +/* ----------------------------- EMC_DYNAMICRASCAS1 ----------------------------- */ +#define EMC_DYNAMICRASCAS1_RAS_Pos 0 /*!< EMC DYNAMICRASCAS1: RAS Position */ +#define EMC_DYNAMICRASCAS1_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS1_RAS_Pos) /*!< EMC DYNAMICRASCAS1: RAS Mask */ +#define EMC_DYNAMICRASCAS1_CAS_Pos 8 /*!< EMC DYNAMICRASCAS1: CAS Position */ +#define EMC_DYNAMICRASCAS1_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS1_CAS_Pos) /*!< EMC DYNAMICRASCAS1: CAS Mask */ + +/* ----------------------------- EMC_DYNAMICCONFIG2 ----------------------------- */ +#define EMC_DYNAMICCONFIG2_MD_Pos 3 /*!< EMC DYNAMICCONFIG2: MD Position */ +#define EMC_DYNAMICCONFIG2_MD_Msk (0x03UL << EMC_DYNAMICCONFIG2_MD_Pos) /*!< EMC DYNAMICCONFIG2: MD Mask */ +#define EMC_DYNAMICCONFIG2_AM0_Pos 7 /*!< EMC DYNAMICCONFIG2: AM0 Position */ +#define EMC_DYNAMICCONFIG2_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG2_AM0_Pos) /*!< EMC DYNAMICCONFIG2: AM0 Mask */ +#define EMC_DYNAMICCONFIG2_AM1_Pos 14 /*!< EMC DYNAMICCONFIG2: AM1 Position */ +#define EMC_DYNAMICCONFIG2_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG2_AM1_Pos) /*!< EMC DYNAMICCONFIG2: AM1 Mask */ +#define EMC_DYNAMICCONFIG2_B_Pos 19 /*!< EMC DYNAMICCONFIG2: B Position */ +#define EMC_DYNAMICCONFIG2_B_Msk (0x01UL << EMC_DYNAMICCONFIG2_B_Pos) /*!< EMC DYNAMICCONFIG2: B Mask */ +#define EMC_DYNAMICCONFIG2_P_Pos 20 /*!< EMC DYNAMICCONFIG2: P Position */ +#define EMC_DYNAMICCONFIG2_P_Msk (0x01UL << EMC_DYNAMICCONFIG2_P_Pos) /*!< EMC DYNAMICCONFIG2: P Mask */ + +/* ----------------------------- EMC_DYNAMICRASCAS2 ----------------------------- */ +#define EMC_DYNAMICRASCAS2_RAS_Pos 0 /*!< EMC DYNAMICRASCAS2: RAS Position */ +#define EMC_DYNAMICRASCAS2_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS2_RAS_Pos) /*!< EMC DYNAMICRASCAS2: RAS Mask */ +#define EMC_DYNAMICRASCAS2_CAS_Pos 8 /*!< EMC DYNAMICRASCAS2: CAS Position */ +#define EMC_DYNAMICRASCAS2_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS2_CAS_Pos) /*!< EMC DYNAMICRASCAS2: CAS Mask */ + +/* ----------------------------- EMC_DYNAMICCONFIG3 ----------------------------- */ +#define EMC_DYNAMICCONFIG3_MD_Pos 3 /*!< EMC DYNAMICCONFIG3: MD Position */ +#define EMC_DYNAMICCONFIG3_MD_Msk (0x03UL << EMC_DYNAMICCONFIG3_MD_Pos) /*!< EMC DYNAMICCONFIG3: MD Mask */ +#define EMC_DYNAMICCONFIG3_AM0_Pos 7 /*!< EMC DYNAMICCONFIG3: AM0 Position */ +#define EMC_DYNAMICCONFIG3_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG3_AM0_Pos) /*!< EMC DYNAMICCONFIG3: AM0 Mask */ +#define EMC_DYNAMICCONFIG3_AM1_Pos 14 /*!< EMC DYNAMICCONFIG3: AM1 Position */ +#define EMC_DYNAMICCONFIG3_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG3_AM1_Pos) /*!< EMC DYNAMICCONFIG3: AM1 Mask */ +#define EMC_DYNAMICCONFIG3_B_Pos 19 /*!< EMC DYNAMICCONFIG3: B Position */ +#define EMC_DYNAMICCONFIG3_B_Msk (0x01UL << EMC_DYNAMICCONFIG3_B_Pos) /*!< EMC DYNAMICCONFIG3: B Mask */ +#define EMC_DYNAMICCONFIG3_P_Pos 20 /*!< EMC DYNAMICCONFIG3: P Position */ +#define EMC_DYNAMICCONFIG3_P_Msk (0x01UL << EMC_DYNAMICCONFIG3_P_Pos) /*!< EMC DYNAMICCONFIG3: P Mask */ + +/* ----------------------------- EMC_DYNAMICRASCAS3 ----------------------------- */ +#define EMC_DYNAMICRASCAS3_RAS_Pos 0 /*!< EMC DYNAMICRASCAS3: RAS Position */ +#define EMC_DYNAMICRASCAS3_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS3_RAS_Pos) /*!< EMC DYNAMICRASCAS3: RAS Mask */ +#define EMC_DYNAMICRASCAS3_CAS_Pos 8 /*!< EMC DYNAMICRASCAS3: CAS Position */ +#define EMC_DYNAMICRASCAS3_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS3_CAS_Pos) /*!< EMC DYNAMICRASCAS3: CAS Mask */ + +/* ------------------------------ EMC_STATICCONFIG0 ----------------------------- */ +#define EMC_STATICCONFIG0_MW_Pos 0 /*!< EMC STATICCONFIG0: MW Position */ +#define EMC_STATICCONFIG0_MW_Msk (0x03UL << EMC_STATICCONFIG0_MW_Pos) /*!< EMC STATICCONFIG0: MW Mask */ +#define EMC_STATICCONFIG0_PM_Pos 3 /*!< EMC STATICCONFIG0: PM Position */ +#define EMC_STATICCONFIG0_PM_Msk (0x01UL << EMC_STATICCONFIG0_PM_Pos) /*!< EMC STATICCONFIG0: PM Mask */ +#define EMC_STATICCONFIG0_PC_Pos 6 /*!< EMC STATICCONFIG0: PC Position */ +#define EMC_STATICCONFIG0_PC_Msk (0x01UL << EMC_STATICCONFIG0_PC_Pos) /*!< EMC STATICCONFIG0: PC Mask */ +#define EMC_STATICCONFIG0_PB_Pos 7 /*!< EMC STATICCONFIG0: PB Position */ +#define EMC_STATICCONFIG0_PB_Msk (0x01UL << EMC_STATICCONFIG0_PB_Pos) /*!< EMC STATICCONFIG0: PB Mask */ +#define EMC_STATICCONFIG0_EW_Pos 8 /*!< EMC STATICCONFIG0: EW Position */ +#define EMC_STATICCONFIG0_EW_Msk (0x01UL << EMC_STATICCONFIG0_EW_Pos) /*!< EMC STATICCONFIG0: EW Mask */ +#define EMC_STATICCONFIG0_B_Pos 19 /*!< EMC STATICCONFIG0: B Position */ +#define EMC_STATICCONFIG0_B_Msk (0x01UL << EMC_STATICCONFIG0_B_Pos) /*!< EMC STATICCONFIG0: B Mask */ +#define EMC_STATICCONFIG0_P_Pos 20 /*!< EMC STATICCONFIG0: P Position */ +#define EMC_STATICCONFIG0_P_Msk (0x01UL << EMC_STATICCONFIG0_P_Pos) /*!< EMC STATICCONFIG0: P Mask */ + +/* ----------------------------- EMC_STATICWAITWEN0 ----------------------------- */ +#define EMC_STATICWAITWEN0_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN0: WAITWEN Position */ +#define EMC_STATICWAITWEN0_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN0_WAITWEN_Pos) /*!< EMC STATICWAITWEN0: WAITWEN Mask */ + +/* ----------------------------- EMC_STATICWAITOEN0 ----------------------------- */ +#define EMC_STATICWAITOEN0_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN0: WAITOEN Position */ +#define EMC_STATICWAITOEN0_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN0_WAITOEN_Pos) /*!< EMC STATICWAITOEN0: WAITOEN Mask */ + +/* ------------------------------ EMC_STATICWAITRD0 ----------------------------- */ +#define EMC_STATICWAITRD0_WAITRD_Pos 0 /*!< EMC STATICWAITRD0: WAITRD Position */ +#define EMC_STATICWAITRD0_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD0_WAITRD_Pos) /*!< EMC STATICWAITRD0: WAITRD Mask */ + +/* ----------------------------- EMC_STATICWAITPAGE0 ---------------------------- */ +#define EMC_STATICWAITPAGE0_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAGE0: WAITPAGE Position */ +#define EMC_STATICWAITPAGE0_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAGE0_WAITPAGE_Pos) /*!< EMC STATICWAITPAGE0: WAITPAGE Mask */ + +/* ------------------------------ EMC_STATICWAITWR0 ----------------------------- */ +#define EMC_STATICWAITWR0_WAITWR_Pos 0 /*!< EMC STATICWAITWR0: WAITWR Position */ +#define EMC_STATICWAITWR0_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR0_WAITWR_Pos) /*!< EMC STATICWAITWR0: WAITWR Mask */ + +/* ----------------------------- EMC_STATICWAITTURN0 ---------------------------- */ +#define EMC_STATICWAITTURN0_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN0: WAITTURN Position */ +#define EMC_STATICWAITTURN0_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN0_WAITTURN_Pos) /*!< EMC STATICWAITTURN0: WAITTURN Mask */ + +/* ------------------------------ EMC_STATICCONFIG1 ----------------------------- */ +#define EMC_STATICCONFIG1_MW_Pos 0 /*!< EMC STATICCONFIG1: MW Position */ +#define EMC_STATICCONFIG1_MW_Msk (0x03UL << EMC_STATICCONFIG1_MW_Pos) /*!< EMC STATICCONFIG1: MW Mask */ +#define EMC_STATICCONFIG1_PM_Pos 3 /*!< EMC STATICCONFIG1: PM Position */ +#define EMC_STATICCONFIG1_PM_Msk (0x01UL << EMC_STATICCONFIG1_PM_Pos) /*!< EMC STATICCONFIG1: PM Mask */ +#define EMC_STATICCONFIG1_PC_Pos 6 /*!< EMC STATICCONFIG1: PC Position */ +#define EMC_STATICCONFIG1_PC_Msk (0x01UL << EMC_STATICCONFIG1_PC_Pos) /*!< EMC STATICCONFIG1: PC Mask */ +#define EMC_STATICCONFIG1_PB_Pos 7 /*!< EMC STATICCONFIG1: PB Position */ +#define EMC_STATICCONFIG1_PB_Msk (0x01UL << EMC_STATICCONFIG1_PB_Pos) /*!< EMC STATICCONFIG1: PB Mask */ +#define EMC_STATICCONFIG1_EW_Pos 8 /*!< EMC STATICCONFIG1: EW Position */ +#define EMC_STATICCONFIG1_EW_Msk (0x01UL << EMC_STATICCONFIG1_EW_Pos) /*!< EMC STATICCONFIG1: EW Mask */ +#define EMC_STATICCONFIG1_B_Pos 19 /*!< EMC STATICCONFIG1: B Position */ +#define EMC_STATICCONFIG1_B_Msk (0x01UL << EMC_STATICCONFIG1_B_Pos) /*!< EMC STATICCONFIG1: B Mask */ +#define EMC_STATICCONFIG1_P_Pos 20 /*!< EMC STATICCONFIG1: P Position */ +#define EMC_STATICCONFIG1_P_Msk (0x01UL << EMC_STATICCONFIG1_P_Pos) /*!< EMC STATICCONFIG1: P Mask */ + +/* ----------------------------- EMC_STATICWAITWEN1 ----------------------------- */ +#define EMC_STATICWAITWEN1_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN1: WAITWEN Position */ +#define EMC_STATICWAITWEN1_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN1_WAITWEN_Pos) /*!< EMC STATICWAITWEN1: WAITWEN Mask */ + +/* ----------------------------- EMC_STATICWAITOEN1 ----------------------------- */ +#define EMC_STATICWAITOEN1_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN1: WAITOEN Position */ +#define EMC_STATICWAITOEN1_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN1_WAITOEN_Pos) /*!< EMC STATICWAITOEN1: WAITOEN Mask */ + +/* ------------------------------ EMC_STATICWAITRD1 ----------------------------- */ +#define EMC_STATICWAITRD1_WAITRD_Pos 0 /*!< EMC STATICWAITRD1: WAITRD Position */ +#define EMC_STATICWAITRD1_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD1_WAITRD_Pos) /*!< EMC STATICWAITRD1: WAITRD Mask */ + +/* ----------------------------- EMC_STATICWAITPAGE1 ---------------------------- */ +#define EMC_STATICWAITPAGE1_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAGE1: WAITPAGE Position */ +#define EMC_STATICWAITPAGE1_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAGE1_WAITPAGE_Pos) /*!< EMC STATICWAITPAGE1: WAITPAGE Mask */ + +/* ------------------------------ EMC_STATICWAITWR1 ----------------------------- */ +#define EMC_STATICWAITWR1_WAITWR_Pos 0 /*!< EMC STATICWAITWR1: WAITWR Position */ +#define EMC_STATICWAITWR1_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR1_WAITWR_Pos) /*!< EMC STATICWAITWR1: WAITWR Mask */ + +/* ----------------------------- EMC_STATICWAITTURN1 ---------------------------- */ +#define EMC_STATICWAITTURN1_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN1: WAITTURN Position */ +#define EMC_STATICWAITTURN1_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN1_WAITTURN_Pos) /*!< EMC STATICWAITTURN1: WAITTURN Mask */ + +/* ------------------------------ EMC_STATICCONFIG2 ----------------------------- */ +#define EMC_STATICCONFIG2_MW_Pos 0 /*!< EMC STATICCONFIG2: MW Position */ +#define EMC_STATICCONFIG2_MW_Msk (0x03UL << EMC_STATICCONFIG2_MW_Pos) /*!< EMC STATICCONFIG2: MW Mask */ +#define EMC_STATICCONFIG2_PM_Pos 3 /*!< EMC STATICCONFIG2: PM Position */ +#define EMC_STATICCONFIG2_PM_Msk (0x01UL << EMC_STATICCONFIG2_PM_Pos) /*!< EMC STATICCONFIG2: PM Mask */ +#define EMC_STATICCONFIG2_PC_Pos 6 /*!< EMC STATICCONFIG2: PC Position */ +#define EMC_STATICCONFIG2_PC_Msk (0x01UL << EMC_STATICCONFIG2_PC_Pos) /*!< EMC STATICCONFIG2: PC Mask */ +#define EMC_STATICCONFIG2_PB_Pos 7 /*!< EMC STATICCONFIG2: PB Position */ +#define EMC_STATICCONFIG2_PB_Msk (0x01UL << EMC_STATICCONFIG2_PB_Pos) /*!< EMC STATICCONFIG2: PB Mask */ +#define EMC_STATICCONFIG2_EW_Pos 8 /*!< EMC STATICCONFIG2: EW Position */ +#define EMC_STATICCONFIG2_EW_Msk (0x01UL << EMC_STATICCONFIG2_EW_Pos) /*!< EMC STATICCONFIG2: EW Mask */ +#define EMC_STATICCONFIG2_B_Pos 19 /*!< EMC STATICCONFIG2: B Position */ +#define EMC_STATICCONFIG2_B_Msk (0x01UL << EMC_STATICCONFIG2_B_Pos) /*!< EMC STATICCONFIG2: B Mask */ +#define EMC_STATICCONFIG2_P_Pos 20 /*!< EMC STATICCONFIG2: P Position */ +#define EMC_STATICCONFIG2_P_Msk (0x01UL << EMC_STATICCONFIG2_P_Pos) /*!< EMC STATICCONFIG2: P Mask */ + +/* ----------------------------- EMC_STATICWAITWEN2 ----------------------------- */ +#define EMC_STATICWAITWEN2_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN2: WAITWEN Position */ +#define EMC_STATICWAITWEN2_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN2_WAITWEN_Pos) /*!< EMC STATICWAITWEN2: WAITWEN Mask */ + +/* ----------------------------- EMC_STATICWAITOEN2 ----------------------------- */ +#define EMC_STATICWAITOEN2_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN2: WAITOEN Position */ +#define EMC_STATICWAITOEN2_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN2_WAITOEN_Pos) /*!< EMC STATICWAITOEN2: WAITOEN Mask */ + +/* ------------------------------ EMC_STATICWAITRD2 ----------------------------- */ +#define EMC_STATICWAITRD2_WAITRD_Pos 0 /*!< EMC STATICWAITRD2: WAITRD Position */ +#define EMC_STATICWAITRD2_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD2_WAITRD_Pos) /*!< EMC STATICWAITRD2: WAITRD Mask */ + +/* ----------------------------- EMC_STATICWAITPAGE2 ---------------------------- */ +#define EMC_STATICWAITPAGE2_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAGE2: WAITPAGE Position */ +#define EMC_STATICWAITPAGE2_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAGE2_WAITPAGE_Pos) /*!< EMC STATICWAITPAGE2: WAITPAGE Mask */ + +/* ------------------------------ EMC_STATICWAITWR2 ----------------------------- */ +#define EMC_STATICWAITWR2_WAITWR_Pos 0 /*!< EMC STATICWAITWR2: WAITWR Position */ +#define EMC_STATICWAITWR2_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR2_WAITWR_Pos) /*!< EMC STATICWAITWR2: WAITWR Mask */ + +/* ----------------------------- EMC_STATICWAITTURN2 ---------------------------- */ +#define EMC_STATICWAITTURN2_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN2: WAITTURN Position */ +#define EMC_STATICWAITTURN2_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN2_WAITTURN_Pos) /*!< EMC STATICWAITTURN2: WAITTURN Mask */ + +/* ------------------------------ EMC_STATICCONFIG3 ----------------------------- */ +#define EMC_STATICCONFIG3_MW_Pos 0 /*!< EMC STATICCONFIG3: MW Position */ +#define EMC_STATICCONFIG3_MW_Msk (0x03UL << EMC_STATICCONFIG3_MW_Pos) /*!< EMC STATICCONFIG3: MW Mask */ +#define EMC_STATICCONFIG3_PM_Pos 3 /*!< EMC STATICCONFIG3: PM Position */ +#define EMC_STATICCONFIG3_PM_Msk (0x01UL << EMC_STATICCONFIG3_PM_Pos) /*!< EMC STATICCONFIG3: PM Mask */ +#define EMC_STATICCONFIG3_PC_Pos 6 /*!< EMC STATICCONFIG3: PC Position */ +#define EMC_STATICCONFIG3_PC_Msk (0x01UL << EMC_STATICCONFIG3_PC_Pos) /*!< EMC STATICCONFIG3: PC Mask */ +#define EMC_STATICCONFIG3_PB_Pos 7 /*!< EMC STATICCONFIG3: PB Position */ +#define EMC_STATICCONFIG3_PB_Msk (0x01UL << EMC_STATICCONFIG3_PB_Pos) /*!< EMC STATICCONFIG3: PB Mask */ +#define EMC_STATICCONFIG3_EW_Pos 8 /*!< EMC STATICCONFIG3: EW Position */ +#define EMC_STATICCONFIG3_EW_Msk (0x01UL << EMC_STATICCONFIG3_EW_Pos) /*!< EMC STATICCONFIG3: EW Mask */ +#define EMC_STATICCONFIG3_B_Pos 19 /*!< EMC STATICCONFIG3: B Position */ +#define EMC_STATICCONFIG3_B_Msk (0x01UL << EMC_STATICCONFIG3_B_Pos) /*!< EMC STATICCONFIG3: B Mask */ +#define EMC_STATICCONFIG3_P_Pos 20 /*!< EMC STATICCONFIG3: P Position */ +#define EMC_STATICCONFIG3_P_Msk (0x01UL << EMC_STATICCONFIG3_P_Pos) /*!< EMC STATICCONFIG3: P Mask */ + +/* ----------------------------- EMC_STATICWAITWEN3 ----------------------------- */ +#define EMC_STATICWAITWEN3_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN3: WAITWEN Position */ +#define EMC_STATICWAITWEN3_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN3_WAITWEN_Pos) /*!< EMC STATICWAITWEN3: WAITWEN Mask */ + +/* ----------------------------- EMC_STATICWAITOEN3 ----------------------------- */ +#define EMC_STATICWAITOEN3_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN3: WAITOEN Position */ +#define EMC_STATICWAITOEN3_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN3_WAITOEN_Pos) /*!< EMC STATICWAITOEN3: WAITOEN Mask */ + +/* ------------------------------ EMC_STATICWAITRD3 ----------------------------- */ +#define EMC_STATICWAITRD3_WAITRD_Pos 0 /*!< EMC STATICWAITRD3: WAITRD Position */ +#define EMC_STATICWAITRD3_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD3_WAITRD_Pos) /*!< EMC STATICWAITRD3: WAITRD Mask */ + +/* ----------------------------- EMC_STATICWAITPAGE3 ---------------------------- */ +#define EMC_STATICWAITPAGE3_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAGE3: WAITPAGE Position */ +#define EMC_STATICWAITPAGE3_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAGE3_WAITPAGE_Pos) /*!< EMC STATICWAITPAGE3: WAITPAGE Mask */ + +/* ------------------------------ EMC_STATICWAITWR3 ----------------------------- */ +#define EMC_STATICWAITWR3_WAITWR_Pos 0 /*!< EMC STATICWAITWR3: WAITWR Position */ +#define EMC_STATICWAITWR3_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR3_WAITWR_Pos) /*!< EMC STATICWAITWR3: WAITWR Mask */ + +/* ----------------------------- EMC_STATICWAITTURN3 ---------------------------- */ +#define EMC_STATICWAITTURN3_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN3: WAITTURN Position */ +#define EMC_STATICWAITTURN3_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN3_WAITTURN_Pos) /*!< EMC STATICWAITTURN3: WAITTURN Mask */ + + +/* ================================================================================ */ +/* ================ struct 'USB0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- USB0_CAPLENGTH ------------------------------- */ +#define USB0_CAPLENGTH_CAPLENGTH_Pos 0 /*!< USB0 CAPLENGTH: CAPLENGTH Position */ +#define USB0_CAPLENGTH_CAPLENGTH_Msk (0x000000ffUL << USB0_CAPLENGTH_CAPLENGTH_Pos) /*!< USB0 CAPLENGTH: CAPLENGTH Mask */ +#define USB0_CAPLENGTH_HCIVERSION_Pos 8 /*!< USB0 CAPLENGTH: HCIVERSION Position */ +#define USB0_CAPLENGTH_HCIVERSION_Msk (0x0000ffffUL << USB0_CAPLENGTH_HCIVERSION_Pos) /*!< USB0 CAPLENGTH: HCIVERSION Mask */ + +/* ------------------------------- USB0_HCSPARAMS ------------------------------- */ +#define USB0_HCSPARAMS_N_PORTS_Pos 0 /*!< USB0 HCSPARAMS: N_PORTS Position */ +#define USB0_HCSPARAMS_N_PORTS_Msk (0x0fUL << USB0_HCSPARAMS_N_PORTS_Pos) /*!< USB0 HCSPARAMS: N_PORTS Mask */ +#define USB0_HCSPARAMS_PPC_Pos 4 /*!< USB0 HCSPARAMS: PPC Position */ +#define USB0_HCSPARAMS_PPC_Msk (0x01UL << USB0_HCSPARAMS_PPC_Pos) /*!< USB0 HCSPARAMS: PPC Mask */ +#define USB0_HCSPARAMS_N_PCC_Pos 8 /*!< USB0 HCSPARAMS: N_PCC Position */ +#define USB0_HCSPARAMS_N_PCC_Msk (0x0fUL << USB0_HCSPARAMS_N_PCC_Pos) /*!< USB0 HCSPARAMS: N_PCC Mask */ +#define USB0_HCSPARAMS_N_CC_Pos 12 /*!< USB0 HCSPARAMS: N_CC Position */ +#define USB0_HCSPARAMS_N_CC_Msk (0x0fUL << USB0_HCSPARAMS_N_CC_Pos) /*!< USB0 HCSPARAMS: N_CC Mask */ +#define USB0_HCSPARAMS_PI_Pos 16 /*!< USB0 HCSPARAMS: PI Position */ +#define USB0_HCSPARAMS_PI_Msk (0x01UL << USB0_HCSPARAMS_PI_Pos) /*!< USB0 HCSPARAMS: PI Mask */ +#define USB0_HCSPARAMS_N_PTT_Pos 20 /*!< USB0 HCSPARAMS: N_PTT Position */ +#define USB0_HCSPARAMS_N_PTT_Msk (0x0fUL << USB0_HCSPARAMS_N_PTT_Pos) /*!< USB0 HCSPARAMS: N_PTT Mask */ +#define USB0_HCSPARAMS_N_TT_Pos 24 /*!< USB0 HCSPARAMS: N_TT Position */ +#define USB0_HCSPARAMS_N_TT_Msk (0x0fUL << USB0_HCSPARAMS_N_TT_Pos) /*!< USB0 HCSPARAMS: N_TT Mask */ + +/* ------------------------------- USB0_HCCPARAMS ------------------------------- */ +#define USB0_HCCPARAMS_ADC_Pos 0 /*!< USB0 HCCPARAMS: ADC Position */ +#define USB0_HCCPARAMS_ADC_Msk (0x01UL << USB0_HCCPARAMS_ADC_Pos) /*!< USB0 HCCPARAMS: ADC Mask */ +#define USB0_HCCPARAMS_PFL_Pos 1 /*!< USB0 HCCPARAMS: PFL Position */ +#define USB0_HCCPARAMS_PFL_Msk (0x01UL << USB0_HCCPARAMS_PFL_Pos) /*!< USB0 HCCPARAMS: PFL Mask */ +#define USB0_HCCPARAMS_ASP_Pos 2 /*!< USB0 HCCPARAMS: ASP Position */ +#define USB0_HCCPARAMS_ASP_Msk (0x01UL << USB0_HCCPARAMS_ASP_Pos) /*!< USB0 HCCPARAMS: ASP Mask */ +#define USB0_HCCPARAMS_IST_Pos 4 /*!< USB0 HCCPARAMS: IST Position */ +#define USB0_HCCPARAMS_IST_Msk (0x0fUL << USB0_HCCPARAMS_IST_Pos) /*!< USB0 HCCPARAMS: IST Mask */ +#define USB0_HCCPARAMS_EECP_Pos 8 /*!< USB0 HCCPARAMS: EECP Position */ +#define USB0_HCCPARAMS_EECP_Msk (0x000000ffUL << USB0_HCCPARAMS_EECP_Pos) /*!< USB0 HCCPARAMS: EECP Mask */ + +/* ------------------------------- USB0_DCIVERSION ------------------------------ */ +#define USB0_DCIVERSION_DCIVERSION_Pos 0 /*!< USB0 DCIVERSION: DCIVERSION Position */ +#define USB0_DCIVERSION_DCIVERSION_Msk (0x0000ffffUL << USB0_DCIVERSION_DCIVERSION_Pos) /*!< USB0 DCIVERSION: DCIVERSION Mask */ + +/* -------------------------------- USB0_USBCMD_D ------------------------------- */ +#define USB0_USBCMD_D_RS_Pos 0 /*!< USB0 USBCMD_D: RS Position */ +#define USB0_USBCMD_D_RS_Msk (0x01UL << USB0_USBCMD_D_RS_Pos) /*!< USB0 USBCMD_D: RS Mask */ +#define USB0_USBCMD_D_RST_Pos 1 /*!< USB0 USBCMD_D: RST Position */ +#define USB0_USBCMD_D_RST_Msk (0x01UL << USB0_USBCMD_D_RST_Pos) /*!< USB0 USBCMD_D: RST Mask */ +#define USB0_USBCMD_D_SUTW_Pos 13 /*!< USB0 USBCMD_D: SUTW Position */ +#define USB0_USBCMD_D_SUTW_Msk (0x01UL << USB0_USBCMD_D_SUTW_Pos) /*!< USB0 USBCMD_D: SUTW Mask */ +#define USB0_USBCMD_D_ATDTW_Pos 14 /*!< USB0 USBCMD_D: ATDTW Position */ +#define USB0_USBCMD_D_ATDTW_Msk (0x01UL << USB0_USBCMD_D_ATDTW_Pos) /*!< USB0 USBCMD_D: ATDTW Mask */ +#define USB0_USBCMD_D_ITC_Pos 16 /*!< USB0 USBCMD_D: ITC Position */ +#define USB0_USBCMD_D_ITC_Msk (0x000000ffUL << USB0_USBCMD_D_ITC_Pos) /*!< USB0 USBCMD_D: ITC Mask */ + +/* -------------------------------- USB0_USBCMD_H ------------------------------- */ +#define USB0_USBCMD_H_RS_Pos 0 /*!< USB0 USBCMD_H: RS Position */ +#define USB0_USBCMD_H_RS_Msk (0x01UL << USB0_USBCMD_H_RS_Pos) /*!< USB0 USBCMD_H: RS Mask */ +#define USB0_USBCMD_H_RST_Pos 1 /*!< USB0 USBCMD_H: RST Position */ +#define USB0_USBCMD_H_RST_Msk (0x01UL << USB0_USBCMD_H_RST_Pos) /*!< USB0 USBCMD_H: RST Mask */ +#define USB0_USBCMD_H_FS0_Pos 2 /*!< USB0 USBCMD_H: FS0 Position */ +#define USB0_USBCMD_H_FS0_Msk (0x01UL << USB0_USBCMD_H_FS0_Pos) /*!< USB0 USBCMD_H: FS0 Mask */ +#define USB0_USBCMD_H_FS1_Pos 3 /*!< USB0 USBCMD_H: FS1 Position */ +#define USB0_USBCMD_H_FS1_Msk (0x01UL << USB0_USBCMD_H_FS1_Pos) /*!< USB0 USBCMD_H: FS1 Mask */ +#define USB0_USBCMD_H_PSE_Pos 4 /*!< USB0 USBCMD_H: PSE Position */ +#define USB0_USBCMD_H_PSE_Msk (0x01UL << USB0_USBCMD_H_PSE_Pos) /*!< USB0 USBCMD_H: PSE Mask */ +#define USB0_USBCMD_H_ASE_Pos 5 /*!< USB0 USBCMD_H: ASE Position */ +#define USB0_USBCMD_H_ASE_Msk (0x01UL << USB0_USBCMD_H_ASE_Pos) /*!< USB0 USBCMD_H: ASE Mask */ +#define USB0_USBCMD_H_IAA_Pos 6 /*!< USB0 USBCMD_H: IAA Position */ +#define USB0_USBCMD_H_IAA_Msk (0x01UL << USB0_USBCMD_H_IAA_Pos) /*!< USB0 USBCMD_H: IAA Mask */ +#define USB0_USBCMD_H_ASP1_0_Pos 8 /*!< USB0 USBCMD_H: ASP1_0 Position */ +#define USB0_USBCMD_H_ASP1_0_Msk (0x03UL << USB0_USBCMD_H_ASP1_0_Pos) /*!< USB0 USBCMD_H: ASP1_0 Mask */ +#define USB0_USBCMD_H_ASPE_Pos 11 /*!< USB0 USBCMD_H: ASPE Position */ +#define USB0_USBCMD_H_ASPE_Msk (0x01UL << USB0_USBCMD_H_ASPE_Pos) /*!< USB0 USBCMD_H: ASPE Mask */ +#define USB0_USBCMD_H_FS2_Pos 15 /*!< USB0 USBCMD_H: FS2 Position */ +#define USB0_USBCMD_H_FS2_Msk (0x01UL << USB0_USBCMD_H_FS2_Pos) /*!< USB0 USBCMD_H: FS2 Mask */ +#define USB0_USBCMD_H_ITC_Pos 16 /*!< USB0 USBCMD_H: ITC Position */ +#define USB0_USBCMD_H_ITC_Msk (0x000000ffUL << USB0_USBCMD_H_ITC_Pos) /*!< USB0 USBCMD_H: ITC Mask */ + +/* -------------------------------- USB0_USBSTS_D ------------------------------- */ +#define USB0_USBSTS_D_UI_Pos 0 /*!< USB0 USBSTS_D: UI Position */ +#define USB0_USBSTS_D_UI_Msk (0x01UL << USB0_USBSTS_D_UI_Pos) /*!< USB0 USBSTS_D: UI Mask */ +#define USB0_USBSTS_D_UEI_Pos 1 /*!< USB0 USBSTS_D: UEI Position */ +#define USB0_USBSTS_D_UEI_Msk (0x01UL << USB0_USBSTS_D_UEI_Pos) /*!< USB0 USBSTS_D: UEI Mask */ +#define USB0_USBSTS_D_PCI_Pos 2 /*!< USB0 USBSTS_D: PCI Position */ +#define USB0_USBSTS_D_PCI_Msk (0x01UL << USB0_USBSTS_D_PCI_Pos) /*!< USB0 USBSTS_D: PCI Mask */ +#define USB0_USBSTS_D_AAI_Pos 5 /*!< USB0 USBSTS_D: AAI Position */ +#define USB0_USBSTS_D_AAI_Msk (0x01UL << USB0_USBSTS_D_AAI_Pos) /*!< USB0 USBSTS_D: AAI Mask */ +#define USB0_USBSTS_D_URI_Pos 6 /*!< USB0 USBSTS_D: URI Position */ +#define USB0_USBSTS_D_URI_Msk (0x01UL << USB0_USBSTS_D_URI_Pos) /*!< USB0 USBSTS_D: URI Mask */ +#define USB0_USBSTS_D_SRI_Pos 7 /*!< USB0 USBSTS_D: SRI Position */ +#define USB0_USBSTS_D_SRI_Msk (0x01UL << USB0_USBSTS_D_SRI_Pos) /*!< USB0 USBSTS_D: SRI Mask */ +#define USB0_USBSTS_D_SLI_Pos 8 /*!< USB0 USBSTS_D: SLI Position */ +#define USB0_USBSTS_D_SLI_Msk (0x01UL << USB0_USBSTS_D_SLI_Pos) /*!< USB0 USBSTS_D: SLI Mask */ +#define USB0_USBSTS_D_NAKI_Pos 16 /*!< USB0 USBSTS_D: NAKI Position */ +#define USB0_USBSTS_D_NAKI_Msk (0x01UL << USB0_USBSTS_D_NAKI_Pos) /*!< USB0 USBSTS_D: NAKI Mask */ + +/* -------------------------------- USB0_USBSTS_H ------------------------------- */ +#define USB0_USBSTS_H_UI_Pos 0 /*!< USB0 USBSTS_H: UI Position */ +#define USB0_USBSTS_H_UI_Msk (0x01UL << USB0_USBSTS_H_UI_Pos) /*!< USB0 USBSTS_H: UI Mask */ +#define USB0_USBSTS_H_UEI_Pos 1 /*!< USB0 USBSTS_H: UEI Position */ +#define USB0_USBSTS_H_UEI_Msk (0x01UL << USB0_USBSTS_H_UEI_Pos) /*!< USB0 USBSTS_H: UEI Mask */ +#define USB0_USBSTS_H_PCI_Pos 2 /*!< USB0 USBSTS_H: PCI Position */ +#define USB0_USBSTS_H_PCI_Msk (0x01UL << USB0_USBSTS_H_PCI_Pos) /*!< USB0 USBSTS_H: PCI Mask */ +#define USB0_USBSTS_H_FRI_Pos 3 /*!< USB0 USBSTS_H: FRI Position */ +#define USB0_USBSTS_H_FRI_Msk (0x01UL << USB0_USBSTS_H_FRI_Pos) /*!< USB0 USBSTS_H: FRI Mask */ +#define USB0_USBSTS_H_AAI_Pos 5 /*!< USB0 USBSTS_H: AAI Position */ +#define USB0_USBSTS_H_AAI_Msk (0x01UL << USB0_USBSTS_H_AAI_Pos) /*!< USB0 USBSTS_H: AAI Mask */ +#define USB0_USBSTS_H_SRI_Pos 7 /*!< USB0 USBSTS_H: SRI Position */ +#define USB0_USBSTS_H_SRI_Msk (0x01UL << USB0_USBSTS_H_SRI_Pos) /*!< USB0 USBSTS_H: SRI Mask */ +#define USB0_USBSTS_H_HCH_Pos 12 /*!< USB0 USBSTS_H: HCH Position */ +#define USB0_USBSTS_H_HCH_Msk (0x01UL << USB0_USBSTS_H_HCH_Pos) /*!< USB0 USBSTS_H: HCH Mask */ +#define USB0_USBSTS_H_RCL_Pos 13 /*!< USB0 USBSTS_H: RCL Position */ +#define USB0_USBSTS_H_RCL_Msk (0x01UL << USB0_USBSTS_H_RCL_Pos) /*!< USB0 USBSTS_H: RCL Mask */ +#define USB0_USBSTS_H_PS_Pos 14 /*!< USB0 USBSTS_H: PS Position */ +#define USB0_USBSTS_H_PS_Msk (0x01UL << USB0_USBSTS_H_PS_Pos) /*!< USB0 USBSTS_H: PS Mask */ +#define USB0_USBSTS_H_AS_Pos 15 /*!< USB0 USBSTS_H: AS Position */ +#define USB0_USBSTS_H_AS_Msk (0x01UL << USB0_USBSTS_H_AS_Pos) /*!< USB0 USBSTS_H: AS Mask */ +#define USB0_USBSTS_H_UAI_Pos 18 /*!< USB0 USBSTS_H: UAI Position */ +#define USB0_USBSTS_H_UAI_Msk (0x01UL << USB0_USBSTS_H_UAI_Pos) /*!< USB0 USBSTS_H: UAI Mask */ +#define USB0_USBSTS_H_UPI_Pos 19 /*!< USB0 USBSTS_H: UPI Position */ +#define USB0_USBSTS_H_UPI_Msk (0x01UL << USB0_USBSTS_H_UPI_Pos) /*!< USB0 USBSTS_H: UPI Mask */ + +/* ------------------------------- USB0_USBINTR_D ------------------------------- */ +#define USB0_USBINTR_D_UE_Pos 0 /*!< USB0 USBINTR_D: UE Position */ +#define USB0_USBINTR_D_UE_Msk (0x01UL << USB0_USBINTR_D_UE_Pos) /*!< USB0 USBINTR_D: UE Mask */ +#define USB0_USBINTR_D_UEE_Pos 1 /*!< USB0 USBINTR_D: UEE Position */ +#define USB0_USBINTR_D_UEE_Msk (0x01UL << USB0_USBINTR_D_UEE_Pos) /*!< USB0 USBINTR_D: UEE Mask */ +#define USB0_USBINTR_D_PCE_Pos 2 /*!< USB0 USBINTR_D: PCE Position */ +#define USB0_USBINTR_D_PCE_Msk (0x01UL << USB0_USBINTR_D_PCE_Pos) /*!< USB0 USBINTR_D: PCE Mask */ +#define USB0_USBINTR_D_URE_Pos 6 /*!< USB0 USBINTR_D: URE Position */ +#define USB0_USBINTR_D_URE_Msk (0x01UL << USB0_USBINTR_D_URE_Pos) /*!< USB0 USBINTR_D: URE Mask */ +#define USB0_USBINTR_D_SRE_Pos 7 /*!< USB0 USBINTR_D: SRE Position */ +#define USB0_USBINTR_D_SRE_Msk (0x01UL << USB0_USBINTR_D_SRE_Pos) /*!< USB0 USBINTR_D: SRE Mask */ +#define USB0_USBINTR_D_SLE_Pos 8 /*!< USB0 USBINTR_D: SLE Position */ +#define USB0_USBINTR_D_SLE_Msk (0x01UL << USB0_USBINTR_D_SLE_Pos) /*!< USB0 USBINTR_D: SLE Mask */ +#define USB0_USBINTR_D_NAKE_Pos 16 /*!< USB0 USBINTR_D: NAKE Position */ +#define USB0_USBINTR_D_NAKE_Msk (0x01UL << USB0_USBINTR_D_NAKE_Pos) /*!< USB0 USBINTR_D: NAKE Mask */ + +/* ------------------------------- USB0_USBINTR_H ------------------------------- */ +#define USB0_USBINTR_H_UE_Pos 0 /*!< USB0 USBINTR_H: UE Position */ +#define USB0_USBINTR_H_UE_Msk (0x01UL << USB0_USBINTR_H_UE_Pos) /*!< USB0 USBINTR_H: UE Mask */ +#define USB0_USBINTR_H_UEE_Pos 1 /*!< USB0 USBINTR_H: UEE Position */ +#define USB0_USBINTR_H_UEE_Msk (0x01UL << USB0_USBINTR_H_UEE_Pos) /*!< USB0 USBINTR_H: UEE Mask */ +#define USB0_USBINTR_H_PCE_Pos 2 /*!< USB0 USBINTR_H: PCE Position */ +#define USB0_USBINTR_H_PCE_Msk (0x01UL << USB0_USBINTR_H_PCE_Pos) /*!< USB0 USBINTR_H: PCE Mask */ +#define USB0_USBINTR_H_FRE_Pos 3 /*!< USB0 USBINTR_H: FRE Position */ +#define USB0_USBINTR_H_FRE_Msk (0x01UL << USB0_USBINTR_H_FRE_Pos) /*!< USB0 USBINTR_H: FRE Mask */ +#define USB0_USBINTR_H_AAE_Pos 5 /*!< USB0 USBINTR_H: AAE Position */ +#define USB0_USBINTR_H_AAE_Msk (0x01UL << USB0_USBINTR_H_AAE_Pos) /*!< USB0 USBINTR_H: AAE Mask */ +#define USB0_USBINTR_H_SRE_Pos 7 /*!< USB0 USBINTR_H: SRE Position */ +#define USB0_USBINTR_H_SRE_Msk (0x01UL << USB0_USBINTR_H_SRE_Pos) /*!< USB0 USBINTR_H: SRE Mask */ +#define USB0_USBINTR_H_UAIE_Pos 18 /*!< USB0 USBINTR_H: UAIE Position */ +#define USB0_USBINTR_H_UAIE_Msk (0x01UL << USB0_USBINTR_H_UAIE_Pos) /*!< USB0 USBINTR_H: UAIE Mask */ +#define USB0_USBINTR_H_UPIA_Pos 19 /*!< USB0 USBINTR_H: UPIA Position */ +#define USB0_USBINTR_H_UPIA_Msk (0x01UL << USB0_USBINTR_H_UPIA_Pos) /*!< USB0 USBINTR_H: UPIA Mask */ + +/* ------------------------------- USB0_FRINDEX_D ------------------------------- */ +#define USB0_FRINDEX_D_FRINDEX2_0_Pos 0 /*!< USB0 FRINDEX_D: FRINDEX2_0 Position */ +#define USB0_FRINDEX_D_FRINDEX2_0_Msk (0x07UL << USB0_FRINDEX_D_FRINDEX2_0_Pos) /*!< USB0 FRINDEX_D: FRINDEX2_0 Mask */ +#define USB0_FRINDEX_D_FRINDEX13_3_Pos 3 /*!< USB0 FRINDEX_D: FRINDEX13_3 Position */ +#define USB0_FRINDEX_D_FRINDEX13_3_Msk (0x000007ffUL << USB0_FRINDEX_D_FRINDEX13_3_Pos) /*!< USB0 FRINDEX_D: FRINDEX13_3 Mask */ + +/* ------------------------------- USB0_FRINDEX_H ------------------------------- */ +#define USB0_FRINDEX_H_FRINDEX2_0_Pos 0 /*!< USB0 FRINDEX_H: FRINDEX2_0 Position */ +#define USB0_FRINDEX_H_FRINDEX2_0_Msk (0x07UL << USB0_FRINDEX_H_FRINDEX2_0_Pos) /*!< USB0 FRINDEX_H: FRINDEX2_0 Mask */ +#define USB0_FRINDEX_H_FRINDEX12_3_Pos 3 /*!< USB0 FRINDEX_H: FRINDEX12_3 Position */ +#define USB0_FRINDEX_H_FRINDEX12_3_Msk (0x000003ffUL << USB0_FRINDEX_H_FRINDEX12_3_Pos) /*!< USB0 FRINDEX_H: FRINDEX12_3 Mask */ + +/* ------------------------------- USB0_DEVICEADDR ------------------------------ */ +#define USB0_DEVICEADDR_USBADRA_Pos 24 /*!< USB0 DEVICEADDR: USBADRA Position */ +#define USB0_DEVICEADDR_USBADRA_Msk (0x01UL << USB0_DEVICEADDR_USBADRA_Pos) /*!< USB0 DEVICEADDR: USBADRA Mask */ +#define USB0_DEVICEADDR_USBADR_Pos 25 /*!< USB0 DEVICEADDR: USBADR Position */ +#define USB0_DEVICEADDR_USBADR_Msk (0x7fUL << USB0_DEVICEADDR_USBADR_Pos) /*!< USB0 DEVICEADDR: USBADR Mask */ + +/* ---------------------------- USB0_PERIODICLISTBASE --------------------------- */ +#define USB0_PERIODICLISTBASE_PERBASE31_12_Pos 12 /*!< USB0 PERIODICLISTBASE: PERBASE31_12 Position */ +#define USB0_PERIODICLISTBASE_PERBASE31_12_Msk (0x000fffffUL << USB0_PERIODICLISTBASE_PERBASE31_12_Pos)/*!< USB0 PERIODICLISTBASE: PERBASE31_12 Mask */ + +/* ---------------------------- USB0_ENDPOINTLISTADDR --------------------------- */ +#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos 11 /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Position */ +#define USB0_ENDPOINTLISTADDR_EPBASE31_11_Msk (0x001fffffUL << USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos) /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Mask */ + +/* ----------------------------- USB0_ASYNCLISTADDR ----------------------------- */ +#define USB0_ASYNCLISTADDR_ASYBASE31_5_Pos 5 /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Position */ +#define USB0_ASYNCLISTADDR_ASYBASE31_5_Msk (0x07ffffffUL << USB0_ASYNCLISTADDR_ASYBASE31_5_Pos) /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Mask */ + +/* --------------------------------- USB0_TTCTRL -------------------------------- */ +#define USB0_TTCTRL_TTHA_Pos 24 /*!< USB0 TTCTRL: TTHA Position */ +#define USB0_TTCTRL_TTHA_Msk (0x7fUL << USB0_TTCTRL_TTHA_Pos) /*!< USB0 TTCTRL: TTHA Mask */ + +/* ------------------------------- USB0_BURSTSIZE ------------------------------- */ +#define USB0_BURSTSIZE_RXPBURST_Pos 0 /*!< USB0 BURSTSIZE: RXPBURST Position */ +#define USB0_BURSTSIZE_RXPBURST_Msk (0x000000ffUL << USB0_BURSTSIZE_RXPBURST_Pos) /*!< USB0 BURSTSIZE: RXPBURST Mask */ +#define USB0_BURSTSIZE_TXPBURST_Pos 8 /*!< USB0 BURSTSIZE: TXPBURST Position */ +#define USB0_BURSTSIZE_TXPBURST_Msk (0x000000ffUL << USB0_BURSTSIZE_TXPBURST_Pos) /*!< USB0 BURSTSIZE: TXPBURST Mask */ + +/* ------------------------------ USB0_TXFILLTUNING ----------------------------- */ +#define USB0_TXFILLTUNING_TXSCHOH_Pos 0 /*!< USB0 TXFILLTUNING: TXSCHOH Position */ +#define USB0_TXFILLTUNING_TXSCHOH_Msk (0x000000ffUL << USB0_TXFILLTUNING_TXSCHOH_Pos) /*!< USB0 TXFILLTUNING: TXSCHOH Mask */ +#define USB0_TXFILLTUNING_TXSCHEATLTH_Pos 8 /*!< USB0 TXFILLTUNING: TXSCHEATLTH Position */ +#define USB0_TXFILLTUNING_TXSCHEATLTH_Msk (0x1fUL << USB0_TXFILLTUNING_TXSCHEATLTH_Pos) /*!< USB0 TXFILLTUNING: TXSCHEATLTH Mask */ +#define USB0_TXFILLTUNING_TXFIFOTHRES_Pos 16 /*!< USB0 TXFILLTUNING: TXFIFOTHRES Position */ +#define USB0_TXFILLTUNING_TXFIFOTHRES_Msk (0x3fUL << USB0_TXFILLTUNING_TXFIFOTHRES_Pos) /*!< USB0 TXFILLTUNING: TXFIFOTHRES Mask */ + +/* ------------------------------- USB0_BINTERVAL ------------------------------- */ +#define USB0_BINTERVAL_BINT_Pos 0 /*!< USB0 BINTERVAL: BINT Position */ +#define USB0_BINTERVAL_BINT_Msk (0x0fUL << USB0_BINTERVAL_BINT_Pos) /*!< USB0 BINTERVAL: BINT Mask */ + +/* -------------------------------- USB0_ENDPTNAK ------------------------------- */ +#define USB0_ENDPTNAK_EPRN0_Pos 0 /*!< USB0 ENDPTNAK: EPRN0 Position */ +#define USB0_ENDPTNAK_EPRN0_Msk (0x01UL << USB0_ENDPTNAK_EPRN0_Pos) /*!< USB0 ENDPTNAK: EPRN0 Mask */ +#define USB0_ENDPTNAK_EPRN1_Pos 1 /*!< USB0 ENDPTNAK: EPRN1 Position */ +#define USB0_ENDPTNAK_EPRN1_Msk (0x01UL << USB0_ENDPTNAK_EPRN1_Pos) /*!< USB0 ENDPTNAK: EPRN1 Mask */ +#define USB0_ENDPTNAK_EPRN2_Pos 2 /*!< USB0 ENDPTNAK: EPRN2 Position */ +#define USB0_ENDPTNAK_EPRN2_Msk (0x01UL << USB0_ENDPTNAK_EPRN2_Pos) /*!< USB0 ENDPTNAK: EPRN2 Mask */ +#define USB0_ENDPTNAK_EPRN3_Pos 3 /*!< USB0 ENDPTNAK: EPRN3 Position */ +#define USB0_ENDPTNAK_EPRN3_Msk (0x01UL << USB0_ENDPTNAK_EPRN3_Pos) /*!< USB0 ENDPTNAK: EPRN3 Mask */ +#define USB0_ENDPTNAK_EPRN4_Pos 4 /*!< USB0 ENDPTNAK: EPRN4 Position */ +#define USB0_ENDPTNAK_EPRN4_Msk (0x01UL << USB0_ENDPTNAK_EPRN4_Pos) /*!< USB0 ENDPTNAK: EPRN4 Mask */ +#define USB0_ENDPTNAK_EPRN5_Pos 5 /*!< USB0 ENDPTNAK: EPRN5 Position */ +#define USB0_ENDPTNAK_EPRN5_Msk (0x01UL << USB0_ENDPTNAK_EPRN5_Pos) /*!< USB0 ENDPTNAK: EPRN5 Mask */ +#define USB0_ENDPTNAK_EPTN0_Pos 16 /*!< USB0 ENDPTNAK: EPTN0 Position */ +#define USB0_ENDPTNAK_EPTN0_Msk (0x01UL << USB0_ENDPTNAK_EPTN0_Pos) /*!< USB0 ENDPTNAK: EPTN0 Mask */ +#define USB0_ENDPTNAK_EPTN1_Pos 17 /*!< USB0 ENDPTNAK: EPTN1 Position */ +#define USB0_ENDPTNAK_EPTN1_Msk (0x01UL << USB0_ENDPTNAK_EPTN1_Pos) /*!< USB0 ENDPTNAK: EPTN1 Mask */ +#define USB0_ENDPTNAK_EPTN2_Pos 18 /*!< USB0 ENDPTNAK: EPTN2 Position */ +#define USB0_ENDPTNAK_EPTN2_Msk (0x01UL << USB0_ENDPTNAK_EPTN2_Pos) /*!< USB0 ENDPTNAK: EPTN2 Mask */ +#define USB0_ENDPTNAK_EPTN3_Pos 19 /*!< USB0 ENDPTNAK: EPTN3 Position */ +#define USB0_ENDPTNAK_EPTN3_Msk (0x01UL << USB0_ENDPTNAK_EPTN3_Pos) /*!< USB0 ENDPTNAK: EPTN3 Mask */ +#define USB0_ENDPTNAK_EPTN4_Pos 20 /*!< USB0 ENDPTNAK: EPTN4 Position */ +#define USB0_ENDPTNAK_EPTN4_Msk (0x01UL << USB0_ENDPTNAK_EPTN4_Pos) /*!< USB0 ENDPTNAK: EPTN4 Mask */ +#define USB0_ENDPTNAK_EPTN5_Pos 21 /*!< USB0 ENDPTNAK: EPTN5 Position */ +#define USB0_ENDPTNAK_EPTN5_Msk (0x01UL << USB0_ENDPTNAK_EPTN5_Pos) /*!< USB0 ENDPTNAK: EPTN5 Mask */ + +/* ------------------------------- USB0_ENDPTNAKEN ------------------------------ */ +#define USB0_ENDPTNAKEN_EPRNE0_Pos 0 /*!< USB0 ENDPTNAKEN: EPRNE0 Position */ +#define USB0_ENDPTNAKEN_EPRNE0_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE0_Pos) /*!< USB0 ENDPTNAKEN: EPRNE0 Mask */ +#define USB0_ENDPTNAKEN_EPRNE1_Pos 1 /*!< USB0 ENDPTNAKEN: EPRNE1 Position */ +#define USB0_ENDPTNAKEN_EPRNE1_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE1_Pos) /*!< USB0 ENDPTNAKEN: EPRNE1 Mask */ +#define USB0_ENDPTNAKEN_EPRNE2_Pos 2 /*!< USB0 ENDPTNAKEN: EPRNE2 Position */ +#define USB0_ENDPTNAKEN_EPRNE2_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE2_Pos) /*!< USB0 ENDPTNAKEN: EPRNE2 Mask */ +#define USB0_ENDPTNAKEN_EPRNE3_Pos 3 /*!< USB0 ENDPTNAKEN: EPRNE3 Position */ +#define USB0_ENDPTNAKEN_EPRNE3_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE3_Pos) /*!< USB0 ENDPTNAKEN: EPRNE3 Mask */ +#define USB0_ENDPTNAKEN_EPRNE4_Pos 4 /*!< USB0 ENDPTNAKEN: EPRNE4 Position */ +#define USB0_ENDPTNAKEN_EPRNE4_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE4_Pos) /*!< USB0 ENDPTNAKEN: EPRNE4 Mask */ +#define USB0_ENDPTNAKEN_EPRNE5_Pos 5 /*!< USB0 ENDPTNAKEN: EPRNE5 Position */ +#define USB0_ENDPTNAKEN_EPRNE5_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE5_Pos) /*!< USB0 ENDPTNAKEN: EPRNE5 Mask */ +#define USB0_ENDPTNAKEN_EPTNE0_Pos 16 /*!< USB0 ENDPTNAKEN: EPTNE0 Position */ +#define USB0_ENDPTNAKEN_EPTNE0_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE0_Pos) /*!< USB0 ENDPTNAKEN: EPTNE0 Mask */ +#define USB0_ENDPTNAKEN_EPTNE1_Pos 17 /*!< USB0 ENDPTNAKEN: EPTNE1 Position */ +#define USB0_ENDPTNAKEN_EPTNE1_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE1_Pos) /*!< USB0 ENDPTNAKEN: EPTNE1 Mask */ +#define USB0_ENDPTNAKEN_EPTNE2_Pos 18 /*!< USB0 ENDPTNAKEN: EPTNE2 Position */ +#define USB0_ENDPTNAKEN_EPTNE2_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE2_Pos) /*!< USB0 ENDPTNAKEN: EPTNE2 Mask */ +#define USB0_ENDPTNAKEN_EPTNE3_Pos 19 /*!< USB0 ENDPTNAKEN: EPTNE3 Position */ +#define USB0_ENDPTNAKEN_EPTNE3_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE3_Pos) /*!< USB0 ENDPTNAKEN: EPTNE3 Mask */ +#define USB0_ENDPTNAKEN_EPTNE4_Pos 20 /*!< USB0 ENDPTNAKEN: EPTNE4 Position */ +#define USB0_ENDPTNAKEN_EPTNE4_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE4_Pos) /*!< USB0 ENDPTNAKEN: EPTNE4 Mask */ +#define USB0_ENDPTNAKEN_EPTNE5_Pos 21 /*!< USB0 ENDPTNAKEN: EPTNE5 Position */ +#define USB0_ENDPTNAKEN_EPTNE5_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE5_Pos) /*!< USB0 ENDPTNAKEN: EPTNE5 Mask */ + +/* ------------------------------- USB0_PORTSC1_D ------------------------------- */ +#define USB0_PORTSC1_D_CCS_Pos 0 /*!< USB0 PORTSC1_D: CCS Position */ +#define USB0_PORTSC1_D_CCS_Msk (0x01UL << USB0_PORTSC1_D_CCS_Pos) /*!< USB0 PORTSC1_D: CCS Mask */ +#define USB0_PORTSC1_D_PE_Pos 2 /*!< USB0 PORTSC1_D: PE Position */ +#define USB0_PORTSC1_D_PE_Msk (0x01UL << USB0_PORTSC1_D_PE_Pos) /*!< USB0 PORTSC1_D: PE Mask */ +#define USB0_PORTSC1_D_PEC_Pos 3 /*!< USB0 PORTSC1_D: PEC Position */ +#define USB0_PORTSC1_D_PEC_Msk (0x01UL << USB0_PORTSC1_D_PEC_Pos) /*!< USB0 PORTSC1_D: PEC Mask */ +#define USB0_PORTSC1_D_FPR_Pos 6 /*!< USB0 PORTSC1_D: FPR Position */ +#define USB0_PORTSC1_D_FPR_Msk (0x01UL << USB0_PORTSC1_D_FPR_Pos) /*!< USB0 PORTSC1_D: FPR Mask */ +#define USB0_PORTSC1_D_SUSP_Pos 7 /*!< USB0 PORTSC1_D: SUSP Position */ +#define USB0_PORTSC1_D_SUSP_Msk (0x01UL << USB0_PORTSC1_D_SUSP_Pos) /*!< USB0 PORTSC1_D: SUSP Mask */ +#define USB0_PORTSC1_D_PR_Pos 8 /*!< USB0 PORTSC1_D: PR Position */ +#define USB0_PORTSC1_D_PR_Msk (0x01UL << USB0_PORTSC1_D_PR_Pos) /*!< USB0 PORTSC1_D: PR Mask */ +#define USB0_PORTSC1_D_HSP_Pos 9 /*!< USB0 PORTSC1_D: HSP Position */ +#define USB0_PORTSC1_D_HSP_Msk (0x01UL << USB0_PORTSC1_D_HSP_Pos) /*!< USB0 PORTSC1_D: HSP Mask */ +#define USB0_PORTSC1_D_PIC1_0_Pos 14 /*!< USB0 PORTSC1_D: PIC1_0 Position */ +#define USB0_PORTSC1_D_PIC1_0_Msk (0x03UL << USB0_PORTSC1_D_PIC1_0_Pos) /*!< USB0 PORTSC1_D: PIC1_0 Mask */ +#define USB0_PORTSC1_D_PTC3_0_Pos 16 /*!< USB0 PORTSC1_D: PTC3_0 Position */ +#define USB0_PORTSC1_D_PTC3_0_Msk (0x0fUL << USB0_PORTSC1_D_PTC3_0_Pos) /*!< USB0 PORTSC1_D: PTC3_0 Mask */ +#define USB0_PORTSC1_D_PHCD_Pos 23 /*!< USB0 PORTSC1_D: PHCD Position */ +#define USB0_PORTSC1_D_PHCD_Msk (0x01UL << USB0_PORTSC1_D_PHCD_Pos) /*!< USB0 PORTSC1_D: PHCD Mask */ +#define USB0_PORTSC1_D_PFSC_Pos 24 /*!< USB0 PORTSC1_D: PFSC Position */ +#define USB0_PORTSC1_D_PFSC_Msk (0x01UL << USB0_PORTSC1_D_PFSC_Pos) /*!< USB0 PORTSC1_D: PFSC Mask */ +#define USB0_PORTSC1_D_PSPD_Pos 26 /*!< USB0 PORTSC1_D: PSPD Position */ +#define USB0_PORTSC1_D_PSPD_Msk (0x03UL << USB0_PORTSC1_D_PSPD_Pos) /*!< USB0 PORTSC1_D: PSPD Mask */ + +/* ------------------------------- USB0_PORTSC1_H ------------------------------- */ +#define USB0_PORTSC1_H_CCS_Pos 0 /*!< USB0 PORTSC1_H: CCS Position */ +#define USB0_PORTSC1_H_CCS_Msk (0x01UL << USB0_PORTSC1_H_CCS_Pos) /*!< USB0 PORTSC1_H: CCS Mask */ +#define USB0_PORTSC1_H_CSC_Pos 1 /*!< USB0 PORTSC1_H: CSC Position */ +#define USB0_PORTSC1_H_CSC_Msk (0x01UL << USB0_PORTSC1_H_CSC_Pos) /*!< USB0 PORTSC1_H: CSC Mask */ +#define USB0_PORTSC1_H_PE_Pos 2 /*!< USB0 PORTSC1_H: PE Position */ +#define USB0_PORTSC1_H_PE_Msk (0x01UL << USB0_PORTSC1_H_PE_Pos) /*!< USB0 PORTSC1_H: PE Mask */ +#define USB0_PORTSC1_H_PEC_Pos 3 /*!< USB0 PORTSC1_H: PEC Position */ +#define USB0_PORTSC1_H_PEC_Msk (0x01UL << USB0_PORTSC1_H_PEC_Pos) /*!< USB0 PORTSC1_H: PEC Mask */ +#define USB0_PORTSC1_H_OCA_Pos 4 /*!< USB0 PORTSC1_H: OCA Position */ +#define USB0_PORTSC1_H_OCA_Msk (0x01UL << USB0_PORTSC1_H_OCA_Pos) /*!< USB0 PORTSC1_H: OCA Mask */ +#define USB0_PORTSC1_H_OCC_Pos 5 /*!< USB0 PORTSC1_H: OCC Position */ +#define USB0_PORTSC1_H_OCC_Msk (0x01UL << USB0_PORTSC1_H_OCC_Pos) /*!< USB0 PORTSC1_H: OCC Mask */ +#define USB0_PORTSC1_H_FPR_Pos 6 /*!< USB0 PORTSC1_H: FPR Position */ +#define USB0_PORTSC1_H_FPR_Msk (0x01UL << USB0_PORTSC1_H_FPR_Pos) /*!< USB0 PORTSC1_H: FPR Mask */ +#define USB0_PORTSC1_H_SUSP_Pos 7 /*!< USB0 PORTSC1_H: SUSP Position */ +#define USB0_PORTSC1_H_SUSP_Msk (0x01UL << USB0_PORTSC1_H_SUSP_Pos) /*!< USB0 PORTSC1_H: SUSP Mask */ +#define USB0_PORTSC1_H_PR_Pos 8 /*!< USB0 PORTSC1_H: PR Position */ +#define USB0_PORTSC1_H_PR_Msk (0x01UL << USB0_PORTSC1_H_PR_Pos) /*!< USB0 PORTSC1_H: PR Mask */ +#define USB0_PORTSC1_H_HSP_Pos 9 /*!< USB0 PORTSC1_H: HSP Position */ +#define USB0_PORTSC1_H_HSP_Msk (0x01UL << USB0_PORTSC1_H_HSP_Pos) /*!< USB0 PORTSC1_H: HSP Mask */ +#define USB0_PORTSC1_H_LS_Pos 10 /*!< USB0 PORTSC1_H: LS Position */ +#define USB0_PORTSC1_H_LS_Msk (0x03UL << USB0_PORTSC1_H_LS_Pos) /*!< USB0 PORTSC1_H: LS Mask */ +#define USB0_PORTSC1_H_PP_Pos 12 /*!< USB0 PORTSC1_H: PP Position */ +#define USB0_PORTSC1_H_PP_Msk (0x01UL << USB0_PORTSC1_H_PP_Pos) /*!< USB0 PORTSC1_H: PP Mask */ +#define USB0_PORTSC1_H_PIC1_0_Pos 14 /*!< USB0 PORTSC1_H: PIC1_0 Position */ +#define USB0_PORTSC1_H_PIC1_0_Msk (0x03UL << USB0_PORTSC1_H_PIC1_0_Pos) /*!< USB0 PORTSC1_H: PIC1_0 Mask */ +#define USB0_PORTSC1_H_PTC3_0_Pos 16 /*!< USB0 PORTSC1_H: PTC3_0 Position */ +#define USB0_PORTSC1_H_PTC3_0_Msk (0x0fUL << USB0_PORTSC1_H_PTC3_0_Pos) /*!< USB0 PORTSC1_H: PTC3_0 Mask */ +#define USB0_PORTSC1_H_WKCN_Pos 20 /*!< USB0 PORTSC1_H: WKCN Position */ +#define USB0_PORTSC1_H_WKCN_Msk (0x01UL << USB0_PORTSC1_H_WKCN_Pos) /*!< USB0 PORTSC1_H: WKCN Mask */ +#define USB0_PORTSC1_H_WKDC_Pos 21 /*!< USB0 PORTSC1_H: WKDC Position */ +#define USB0_PORTSC1_H_WKDC_Msk (0x01UL << USB0_PORTSC1_H_WKDC_Pos) /*!< USB0 PORTSC1_H: WKDC Mask */ +#define USB0_PORTSC1_H_WKOC_Pos 22 /*!< USB0 PORTSC1_H: WKOC Position */ +#define USB0_PORTSC1_H_WKOC_Msk (0x01UL << USB0_PORTSC1_H_WKOC_Pos) /*!< USB0 PORTSC1_H: WKOC Mask */ +#define USB0_PORTSC1_H_PHCD_Pos 23 /*!< USB0 PORTSC1_H: PHCD Position */ +#define USB0_PORTSC1_H_PHCD_Msk (0x01UL << USB0_PORTSC1_H_PHCD_Pos) /*!< USB0 PORTSC1_H: PHCD Mask */ +#define USB0_PORTSC1_H_PFSC_Pos 24 /*!< USB0 PORTSC1_H: PFSC Position */ +#define USB0_PORTSC1_H_PFSC_Msk (0x01UL << USB0_PORTSC1_H_PFSC_Pos) /*!< USB0 PORTSC1_H: PFSC Mask */ +#define USB0_PORTSC1_H_PSPD_Pos 26 /*!< USB0 PORTSC1_H: PSPD Position */ +#define USB0_PORTSC1_H_PSPD_Msk (0x03UL << USB0_PORTSC1_H_PSPD_Pos) /*!< USB0 PORTSC1_H: PSPD Mask */ + +/* --------------------------------- USB0_OTGSC --------------------------------- */ +#define USB0_OTGSC_VD_Pos 0 /*!< USB0 OTGSC: VD Position */ +#define USB0_OTGSC_VD_Msk (0x01UL << USB0_OTGSC_VD_Pos) /*!< USB0 OTGSC: VD Mask */ +#define USB0_OTGSC_VC_Pos 1 /*!< USB0 OTGSC: VC Position */ +#define USB0_OTGSC_VC_Msk (0x01UL << USB0_OTGSC_VC_Pos) /*!< USB0 OTGSC: VC Mask */ +#define USB0_OTGSC_HAAR_Pos 2 /*!< USB0 OTGSC: HAAR Position */ +#define USB0_OTGSC_HAAR_Msk (0x01UL << USB0_OTGSC_HAAR_Pos) /*!< USB0 OTGSC: HAAR Mask */ +#define USB0_OTGSC_OT_Pos 3 /*!< USB0 OTGSC: OT Position */ +#define USB0_OTGSC_OT_Msk (0x01UL << USB0_OTGSC_OT_Pos) /*!< USB0 OTGSC: OT Mask */ +#define USB0_OTGSC_DP_Pos 4 /*!< USB0 OTGSC: DP Position */ +#define USB0_OTGSC_DP_Msk (0x01UL << USB0_OTGSC_DP_Pos) /*!< USB0 OTGSC: DP Mask */ +#define USB0_OTGSC_IDPU_Pos 5 /*!< USB0 OTGSC: IDPU Position */ +#define USB0_OTGSC_IDPU_Msk (0x01UL << USB0_OTGSC_IDPU_Pos) /*!< USB0 OTGSC: IDPU Mask */ +#define USB0_OTGSC_HADP_Pos 6 /*!< USB0 OTGSC: HADP Position */ +#define USB0_OTGSC_HADP_Msk (0x01UL << USB0_OTGSC_HADP_Pos) /*!< USB0 OTGSC: HADP Mask */ +#define USB0_OTGSC_HABA_Pos 7 /*!< USB0 OTGSC: HABA Position */ +#define USB0_OTGSC_HABA_Msk (0x01UL << USB0_OTGSC_HABA_Pos) /*!< USB0 OTGSC: HABA Mask */ +#define USB0_OTGSC_ID_Pos 8 /*!< USB0 OTGSC: ID Position */ +#define USB0_OTGSC_ID_Msk (0x01UL << USB0_OTGSC_ID_Pos) /*!< USB0 OTGSC: ID Mask */ +#define USB0_OTGSC_AVV_Pos 9 /*!< USB0 OTGSC: AVV Position */ +#define USB0_OTGSC_AVV_Msk (0x01UL << USB0_OTGSC_AVV_Pos) /*!< USB0 OTGSC: AVV Mask */ +#define USB0_OTGSC_ASV_Pos 10 /*!< USB0 OTGSC: ASV Position */ +#define USB0_OTGSC_ASV_Msk (0x01UL << USB0_OTGSC_ASV_Pos) /*!< USB0 OTGSC: ASV Mask */ +#define USB0_OTGSC_BSV_Pos 11 /*!< USB0 OTGSC: BSV Position */ +#define USB0_OTGSC_BSV_Msk (0x01UL << USB0_OTGSC_BSV_Pos) /*!< USB0 OTGSC: BSV Mask */ +#define USB0_OTGSC_BSE_Pos 12 /*!< USB0 OTGSC: BSE Position */ +#define USB0_OTGSC_BSE_Msk (0x01UL << USB0_OTGSC_BSE_Pos) /*!< USB0 OTGSC: BSE Mask */ +#define USB0_OTGSC_MS1T_Pos 13 /*!< USB0 OTGSC: MS1T Position */ +#define USB0_OTGSC_MS1T_Msk (0x01UL << USB0_OTGSC_MS1T_Pos) /*!< USB0 OTGSC: MS1T Mask */ +#define USB0_OTGSC_DPS_Pos 14 /*!< USB0 OTGSC: DPS Position */ +#define USB0_OTGSC_DPS_Msk (0x01UL << USB0_OTGSC_DPS_Pos) /*!< USB0 OTGSC: DPS Mask */ +#define USB0_OTGSC_IDIS_Pos 16 /*!< USB0 OTGSC: IDIS Position */ +#define USB0_OTGSC_IDIS_Msk (0x01UL << USB0_OTGSC_IDIS_Pos) /*!< USB0 OTGSC: IDIS Mask */ +#define USB0_OTGSC_AVVIS_Pos 17 /*!< USB0 OTGSC: AVVIS Position */ +#define USB0_OTGSC_AVVIS_Msk (0x01UL << USB0_OTGSC_AVVIS_Pos) /*!< USB0 OTGSC: AVVIS Mask */ +#define USB0_OTGSC_ASVIS_Pos 18 /*!< USB0 OTGSC: ASVIS Position */ +#define USB0_OTGSC_ASVIS_Msk (0x01UL << USB0_OTGSC_ASVIS_Pos) /*!< USB0 OTGSC: ASVIS Mask */ +#define USB0_OTGSC_BSVIS_Pos 19 /*!< USB0 OTGSC: BSVIS Position */ +#define USB0_OTGSC_BSVIS_Msk (0x01UL << USB0_OTGSC_BSVIS_Pos) /*!< USB0 OTGSC: BSVIS Mask */ +#define USB0_OTGSC_BSEIS_Pos 20 /*!< USB0 OTGSC: BSEIS Position */ +#define USB0_OTGSC_BSEIS_Msk (0x01UL << USB0_OTGSC_BSEIS_Pos) /*!< USB0 OTGSC: BSEIS Mask */ +#define USB0_OTGSC_ms1S_Pos 21 /*!< USB0 OTGSC: ms1S Position */ +#define USB0_OTGSC_ms1S_Msk (0x01UL << USB0_OTGSC_ms1S_Pos) /*!< USB0 OTGSC: ms1S Mask */ +#define USB0_OTGSC_DPIS_Pos 22 /*!< USB0 OTGSC: DPIS Position */ +#define USB0_OTGSC_DPIS_Msk (0x01UL << USB0_OTGSC_DPIS_Pos) /*!< USB0 OTGSC: DPIS Mask */ +#define USB0_OTGSC_IDIE_Pos 24 /*!< USB0 OTGSC: IDIE Position */ +#define USB0_OTGSC_IDIE_Msk (0x01UL << USB0_OTGSC_IDIE_Pos) /*!< USB0 OTGSC: IDIE Mask */ +#define USB0_OTGSC_AVVIE_Pos 25 /*!< USB0 OTGSC: AVVIE Position */ +#define USB0_OTGSC_AVVIE_Msk (0x01UL << USB0_OTGSC_AVVIE_Pos) /*!< USB0 OTGSC: AVVIE Mask */ +#define USB0_OTGSC_ASVIE_Pos 26 /*!< USB0 OTGSC: ASVIE Position */ +#define USB0_OTGSC_ASVIE_Msk (0x01UL << USB0_OTGSC_ASVIE_Pos) /*!< USB0 OTGSC: ASVIE Mask */ +#define USB0_OTGSC_BSVIE_Pos 27 /*!< USB0 OTGSC: BSVIE Position */ +#define USB0_OTGSC_BSVIE_Msk (0x01UL << USB0_OTGSC_BSVIE_Pos) /*!< USB0 OTGSC: BSVIE Mask */ +#define USB0_OTGSC_BSEIE_Pos 28 /*!< USB0 OTGSC: BSEIE Position */ +#define USB0_OTGSC_BSEIE_Msk (0x01UL << USB0_OTGSC_BSEIE_Pos) /*!< USB0 OTGSC: BSEIE Mask */ +#define USB0_OTGSC_MS1E_Pos 29 /*!< USB0 OTGSC: MS1E Position */ +#define USB0_OTGSC_MS1E_Msk (0x01UL << USB0_OTGSC_MS1E_Pos) /*!< USB0 OTGSC: MS1E Mask */ +#define USB0_OTGSC_DPIE_Pos 30 /*!< USB0 OTGSC: DPIE Position */ +#define USB0_OTGSC_DPIE_Msk (0x01UL << USB0_OTGSC_DPIE_Pos) /*!< USB0 OTGSC: DPIE Mask */ + +/* ------------------------------- USB0_USBMODE_D ------------------------------- */ +#define USB0_USBMODE_D_CM1_0_Pos 0 /*!< USB0 USBMODE_D: CM1_0 Position */ +#define USB0_USBMODE_D_CM1_0_Msk (0x03UL << USB0_USBMODE_D_CM1_0_Pos) /*!< USB0 USBMODE_D: CM1_0 Mask */ +#define USB0_USBMODE_D_ES_Pos 2 /*!< USB0 USBMODE_D: ES Position */ +#define USB0_USBMODE_D_ES_Msk (0x01UL << USB0_USBMODE_D_ES_Pos) /*!< USB0 USBMODE_D: ES Mask */ +#define USB0_USBMODE_D_SLOM_Pos 3 /*!< USB0 USBMODE_D: SLOM Position */ +#define USB0_USBMODE_D_SLOM_Msk (0x01UL << USB0_USBMODE_D_SLOM_Pos) /*!< USB0 USBMODE_D: SLOM Mask */ +#define USB0_USBMODE_D_SDIS_Pos 4 /*!< USB0 USBMODE_D: SDIS Position */ +#define USB0_USBMODE_D_SDIS_Msk (0x01UL << USB0_USBMODE_D_SDIS_Pos) /*!< USB0 USBMODE_D: SDIS Mask */ + +/* ------------------------------- USB0_USBMODE_H ------------------------------- */ +#define USB0_USBMODE_H_CM_Pos 0 /*!< USB0 USBMODE_H: CM Position */ +#define USB0_USBMODE_H_CM_Msk (0x03UL << USB0_USBMODE_H_CM_Pos) /*!< USB0 USBMODE_H: CM Mask */ +#define USB0_USBMODE_H_ES_Pos 2 /*!< USB0 USBMODE_H: ES Position */ +#define USB0_USBMODE_H_ES_Msk (0x01UL << USB0_USBMODE_H_ES_Pos) /*!< USB0 USBMODE_H: ES Mask */ +#define USB0_USBMODE_H_SDIS_Pos 4 /*!< USB0 USBMODE_H: SDIS Position */ +#define USB0_USBMODE_H_SDIS_Msk (0x01UL << USB0_USBMODE_H_SDIS_Pos) /*!< USB0 USBMODE_H: SDIS Mask */ +#define USB0_USBMODE_H_VBPS_Pos 5 /*!< USB0 USBMODE_H: VBPS Position */ +#define USB0_USBMODE_H_VBPS_Msk (0x01UL << USB0_USBMODE_H_VBPS_Pos) /*!< USB0 USBMODE_H: VBPS Mask */ + +/* ----------------------------- USB0_ENDPTSETUPSTAT ---------------------------- */ +#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos 0 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */ +#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */ +#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos 1 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */ +#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */ +#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos 2 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */ +#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */ +#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos 3 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */ +#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */ +#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos 4 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Position */ +#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Mask */ +#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos 5 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Position */ +#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Mask */ + +/* ------------------------------- USB0_ENDPTPRIME ------------------------------ */ +#define USB0_ENDPTPRIME_PERB0_Pos 0 /*!< USB0 ENDPTPRIME: PERB0 Position */ +#define USB0_ENDPTPRIME_PERB0_Msk (0x01UL << USB0_ENDPTPRIME_PERB0_Pos) /*!< USB0 ENDPTPRIME: PERB0 Mask */ +#define USB0_ENDPTPRIME_PERB1_Pos 1 /*!< USB0 ENDPTPRIME: PERB1 Position */ +#define USB0_ENDPTPRIME_PERB1_Msk (0x01UL << USB0_ENDPTPRIME_PERB1_Pos) /*!< USB0 ENDPTPRIME: PERB1 Mask */ +#define USB0_ENDPTPRIME_PERB2_Pos 2 /*!< USB0 ENDPTPRIME: PERB2 Position */ +#define USB0_ENDPTPRIME_PERB2_Msk (0x01UL << USB0_ENDPTPRIME_PERB2_Pos) /*!< USB0 ENDPTPRIME: PERB2 Mask */ +#define USB0_ENDPTPRIME_PERB3_Pos 3 /*!< USB0 ENDPTPRIME: PERB3 Position */ +#define USB0_ENDPTPRIME_PERB3_Msk (0x01UL << USB0_ENDPTPRIME_PERB3_Pos) /*!< USB0 ENDPTPRIME: PERB3 Mask */ +#define USB0_ENDPTPRIME_PERB4_Pos 4 /*!< USB0 ENDPTPRIME: PERB4 Position */ +#define USB0_ENDPTPRIME_PERB4_Msk (0x01UL << USB0_ENDPTPRIME_PERB4_Pos) /*!< USB0 ENDPTPRIME: PERB4 Mask */ +#define USB0_ENDPTPRIME_PERB5_Pos 5 /*!< USB0 ENDPTPRIME: PERB5 Position */ +#define USB0_ENDPTPRIME_PERB5_Msk (0x01UL << USB0_ENDPTPRIME_PERB5_Pos) /*!< USB0 ENDPTPRIME: PERB5 Mask */ +#define USB0_ENDPTPRIME_PETB0_Pos 16 /*!< USB0 ENDPTPRIME: PETB0 Position */ +#define USB0_ENDPTPRIME_PETB0_Msk (0x01UL << USB0_ENDPTPRIME_PETB0_Pos) /*!< USB0 ENDPTPRIME: PETB0 Mask */ +#define USB0_ENDPTPRIME_PETB1_Pos 17 /*!< USB0 ENDPTPRIME: PETB1 Position */ +#define USB0_ENDPTPRIME_PETB1_Msk (0x01UL << USB0_ENDPTPRIME_PETB1_Pos) /*!< USB0 ENDPTPRIME: PETB1 Mask */ +#define USB0_ENDPTPRIME_PETB2_Pos 18 /*!< USB0 ENDPTPRIME: PETB2 Position */ +#define USB0_ENDPTPRIME_PETB2_Msk (0x01UL << USB0_ENDPTPRIME_PETB2_Pos) /*!< USB0 ENDPTPRIME: PETB2 Mask */ +#define USB0_ENDPTPRIME_PETB3_Pos 19 /*!< USB0 ENDPTPRIME: PETB3 Position */ +#define USB0_ENDPTPRIME_PETB3_Msk (0x01UL << USB0_ENDPTPRIME_PETB3_Pos) /*!< USB0 ENDPTPRIME: PETB3 Mask */ +#define USB0_ENDPTPRIME_PETB4_Pos 20 /*!< USB0 ENDPTPRIME: PETB4 Position */ +#define USB0_ENDPTPRIME_PETB4_Msk (0x01UL << USB0_ENDPTPRIME_PETB4_Pos) /*!< USB0 ENDPTPRIME: PETB4 Mask */ +#define USB0_ENDPTPRIME_PETB5_Pos 21 /*!< USB0 ENDPTPRIME: PETB5 Position */ +#define USB0_ENDPTPRIME_PETB5_Msk (0x01UL << USB0_ENDPTPRIME_PETB5_Pos) /*!< USB0 ENDPTPRIME: PETB5 Mask */ + +/* ------------------------------- USB0_ENDPTFLUSH ------------------------------ */ +#define USB0_ENDPTFLUSH_FERB0_Pos 0 /*!< USB0 ENDPTFLUSH: FERB0 Position */ +#define USB0_ENDPTFLUSH_FERB0_Msk (0x01UL << USB0_ENDPTFLUSH_FERB0_Pos) /*!< USB0 ENDPTFLUSH: FERB0 Mask */ +#define USB0_ENDPTFLUSH_FERB1_Pos 1 /*!< USB0 ENDPTFLUSH: FERB1 Position */ +#define USB0_ENDPTFLUSH_FERB1_Msk (0x01UL << USB0_ENDPTFLUSH_FERB1_Pos) /*!< USB0 ENDPTFLUSH: FERB1 Mask */ +#define USB0_ENDPTFLUSH_FERB2_Pos 2 /*!< USB0 ENDPTFLUSH: FERB2 Position */ +#define USB0_ENDPTFLUSH_FERB2_Msk (0x01UL << USB0_ENDPTFLUSH_FERB2_Pos) /*!< USB0 ENDPTFLUSH: FERB2 Mask */ +#define USB0_ENDPTFLUSH_FERB3_Pos 3 /*!< USB0 ENDPTFLUSH: FERB3 Position */ +#define USB0_ENDPTFLUSH_FERB3_Msk (0x01UL << USB0_ENDPTFLUSH_FERB3_Pos) /*!< USB0 ENDPTFLUSH: FERB3 Mask */ +#define USB0_ENDPTFLUSH_FERB4_Pos 4 /*!< USB0 ENDPTFLUSH: FERB4 Position */ +#define USB0_ENDPTFLUSH_FERB4_Msk (0x01UL << USB0_ENDPTFLUSH_FERB4_Pos) /*!< USB0 ENDPTFLUSH: FERB4 Mask */ +#define USB0_ENDPTFLUSH_FERB5_Pos 5 /*!< USB0 ENDPTFLUSH: FERB5 Position */ +#define USB0_ENDPTFLUSH_FERB5_Msk (0x01UL << USB0_ENDPTFLUSH_FERB5_Pos) /*!< USB0 ENDPTFLUSH: FERB5 Mask */ +#define USB0_ENDPTFLUSH_FETB0_Pos 16 /*!< USB0 ENDPTFLUSH: FETB0 Position */ +#define USB0_ENDPTFLUSH_FETB0_Msk (0x01UL << USB0_ENDPTFLUSH_FETB0_Pos) /*!< USB0 ENDPTFLUSH: FETB0 Mask */ +#define USB0_ENDPTFLUSH_FETB1_Pos 17 /*!< USB0 ENDPTFLUSH: FETB1 Position */ +#define USB0_ENDPTFLUSH_FETB1_Msk (0x01UL << USB0_ENDPTFLUSH_FETB1_Pos) /*!< USB0 ENDPTFLUSH: FETB1 Mask */ +#define USB0_ENDPTFLUSH_FETB2_Pos 18 /*!< USB0 ENDPTFLUSH: FETB2 Position */ +#define USB0_ENDPTFLUSH_FETB2_Msk (0x01UL << USB0_ENDPTFLUSH_FETB2_Pos) /*!< USB0 ENDPTFLUSH: FETB2 Mask */ +#define USB0_ENDPTFLUSH_FETB3_Pos 19 /*!< USB0 ENDPTFLUSH: FETB3 Position */ +#define USB0_ENDPTFLUSH_FETB3_Msk (0x01UL << USB0_ENDPTFLUSH_FETB3_Pos) /*!< USB0 ENDPTFLUSH: FETB3 Mask */ +#define USB0_ENDPTFLUSH_FETB4_Pos 20 /*!< USB0 ENDPTFLUSH: FETB4 Position */ +#define USB0_ENDPTFLUSH_FETB4_Msk (0x01UL << USB0_ENDPTFLUSH_FETB4_Pos) /*!< USB0 ENDPTFLUSH: FETB4 Mask */ +#define USB0_ENDPTFLUSH_FETB5_Pos 21 /*!< USB0 ENDPTFLUSH: FETB5 Position */ +#define USB0_ENDPTFLUSH_FETB5_Msk (0x01UL << USB0_ENDPTFLUSH_FETB5_Pos) /*!< USB0 ENDPTFLUSH: FETB5 Mask */ + +/* ------------------------------- USB0_ENDPTSTAT ------------------------------- */ +#define USB0_ENDPTSTAT_ERBR0_Pos 0 /*!< USB0 ENDPTSTAT: ERBR0 Position */ +#define USB0_ENDPTSTAT_ERBR0_Msk (0x01UL << USB0_ENDPTSTAT_ERBR0_Pos) /*!< USB0 ENDPTSTAT: ERBR0 Mask */ +#define USB0_ENDPTSTAT_ERBR1_Pos 1 /*!< USB0 ENDPTSTAT: ERBR1 Position */ +#define USB0_ENDPTSTAT_ERBR1_Msk (0x01UL << USB0_ENDPTSTAT_ERBR1_Pos) /*!< USB0 ENDPTSTAT: ERBR1 Mask */ +#define USB0_ENDPTSTAT_ERBR2_Pos 2 /*!< USB0 ENDPTSTAT: ERBR2 Position */ +#define USB0_ENDPTSTAT_ERBR2_Msk (0x01UL << USB0_ENDPTSTAT_ERBR2_Pos) /*!< USB0 ENDPTSTAT: ERBR2 Mask */ +#define USB0_ENDPTSTAT_ERBR3_Pos 3 /*!< USB0 ENDPTSTAT: ERBR3 Position */ +#define USB0_ENDPTSTAT_ERBR3_Msk (0x01UL << USB0_ENDPTSTAT_ERBR3_Pos) /*!< USB0 ENDPTSTAT: ERBR3 Mask */ +#define USB0_ENDPTSTAT_ERBR4_Pos 4 /*!< USB0 ENDPTSTAT: ERBR4 Position */ +#define USB0_ENDPTSTAT_ERBR4_Msk (0x01UL << USB0_ENDPTSTAT_ERBR4_Pos) /*!< USB0 ENDPTSTAT: ERBR4 Mask */ +#define USB0_ENDPTSTAT_ERBR5_Pos 5 /*!< USB0 ENDPTSTAT: ERBR5 Position */ +#define USB0_ENDPTSTAT_ERBR5_Msk (0x01UL << USB0_ENDPTSTAT_ERBR5_Pos) /*!< USB0 ENDPTSTAT: ERBR5 Mask */ +#define USB0_ENDPTSTAT_ETBR0_Pos 16 /*!< USB0 ENDPTSTAT: ETBR0 Position */ +#define USB0_ENDPTSTAT_ETBR0_Msk (0x01UL << USB0_ENDPTSTAT_ETBR0_Pos) /*!< USB0 ENDPTSTAT: ETBR0 Mask */ +#define USB0_ENDPTSTAT_ETBR1_Pos 17 /*!< USB0 ENDPTSTAT: ETBR1 Position */ +#define USB0_ENDPTSTAT_ETBR1_Msk (0x01UL << USB0_ENDPTSTAT_ETBR1_Pos) /*!< USB0 ENDPTSTAT: ETBR1 Mask */ +#define USB0_ENDPTSTAT_ETBR2_Pos 18 /*!< USB0 ENDPTSTAT: ETBR2 Position */ +#define USB0_ENDPTSTAT_ETBR2_Msk (0x01UL << USB0_ENDPTSTAT_ETBR2_Pos) /*!< USB0 ENDPTSTAT: ETBR2 Mask */ +#define USB0_ENDPTSTAT_ETBR3_Pos 19 /*!< USB0 ENDPTSTAT: ETBR3 Position */ +#define USB0_ENDPTSTAT_ETBR3_Msk (0x01UL << USB0_ENDPTSTAT_ETBR3_Pos) /*!< USB0 ENDPTSTAT: ETBR3 Mask */ +#define USB0_ENDPTSTAT_ETBR4_Pos 20 /*!< USB0 ENDPTSTAT: ETBR4 Position */ +#define USB0_ENDPTSTAT_ETBR4_Msk (0x01UL << USB0_ENDPTSTAT_ETBR4_Pos) /*!< USB0 ENDPTSTAT: ETBR4 Mask */ +#define USB0_ENDPTSTAT_ETBR5_Pos 21 /*!< USB0 ENDPTSTAT: ETBR5 Position */ +#define USB0_ENDPTSTAT_ETBR5_Msk (0x01UL << USB0_ENDPTSTAT_ETBR5_Pos) /*!< USB0 ENDPTSTAT: ETBR5 Mask */ + +/* ----------------------------- USB0_ENDPTCOMPLETE ----------------------------- */ +#define USB0_ENDPTCOMPLETE_ERCE0_Pos 0 /*!< USB0 ENDPTCOMPLETE: ERCE0 Position */ +#define USB0_ENDPTCOMPLETE_ERCE0_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE0_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE0 Mask */ +#define USB0_ENDPTCOMPLETE_ERCE1_Pos 1 /*!< USB0 ENDPTCOMPLETE: ERCE1 Position */ +#define USB0_ENDPTCOMPLETE_ERCE1_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE1_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE1 Mask */ +#define USB0_ENDPTCOMPLETE_ERCE2_Pos 2 /*!< USB0 ENDPTCOMPLETE: ERCE2 Position */ +#define USB0_ENDPTCOMPLETE_ERCE2_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE2_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE2 Mask */ +#define USB0_ENDPTCOMPLETE_ERCE3_Pos 3 /*!< USB0 ENDPTCOMPLETE: ERCE3 Position */ +#define USB0_ENDPTCOMPLETE_ERCE3_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE3_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE3 Mask */ +#define USB0_ENDPTCOMPLETE_ERCE4_Pos 4 /*!< USB0 ENDPTCOMPLETE: ERCE4 Position */ +#define USB0_ENDPTCOMPLETE_ERCE4_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE4_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE4 Mask */ +#define USB0_ENDPTCOMPLETE_ERCE5_Pos 5 /*!< USB0 ENDPTCOMPLETE: ERCE5 Position */ +#define USB0_ENDPTCOMPLETE_ERCE5_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE5_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE5 Mask */ +#define USB0_ENDPTCOMPLETE_ETCE0_Pos 16 /*!< USB0 ENDPTCOMPLETE: ETCE0 Position */ +#define USB0_ENDPTCOMPLETE_ETCE0_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE0_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE0 Mask */ +#define USB0_ENDPTCOMPLETE_ETCE1_Pos 17 /*!< USB0 ENDPTCOMPLETE: ETCE1 Position */ +#define USB0_ENDPTCOMPLETE_ETCE1_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE1_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE1 Mask */ +#define USB0_ENDPTCOMPLETE_ETCE2_Pos 18 /*!< USB0 ENDPTCOMPLETE: ETCE2 Position */ +#define USB0_ENDPTCOMPLETE_ETCE2_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE2_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE2 Mask */ +#define USB0_ENDPTCOMPLETE_ETCE3_Pos 19 /*!< USB0 ENDPTCOMPLETE: ETCE3 Position */ +#define USB0_ENDPTCOMPLETE_ETCE3_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE3_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE3 Mask */ +#define USB0_ENDPTCOMPLETE_ETCE4_Pos 20 /*!< USB0 ENDPTCOMPLETE: ETCE4 Position */ +#define USB0_ENDPTCOMPLETE_ETCE4_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE4_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE4 Mask */ +#define USB0_ENDPTCOMPLETE_ETCE5_Pos 21 /*!< USB0 ENDPTCOMPLETE: ETCE5 Position */ +#define USB0_ENDPTCOMPLETE_ETCE5_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE5_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE5 Mask */ + +/* ------------------------------- USB0_ENDPTCTRL0 ------------------------------ */ +#define USB0_ENDPTCTRL0_RXS_Pos 0 /*!< USB0 ENDPTCTRL0: RXS Position */ +#define USB0_ENDPTCTRL0_RXS_Msk (0x01UL << USB0_ENDPTCTRL0_RXS_Pos) /*!< USB0 ENDPTCTRL0: RXS Mask */ +#define USB0_ENDPTCTRL0_RXT1_0_Pos 2 /*!< USB0 ENDPTCTRL0: RXT1_0 Position */ +#define USB0_ENDPTCTRL0_RXT1_0_Msk (0x03UL << USB0_ENDPTCTRL0_RXT1_0_Pos) /*!< USB0 ENDPTCTRL0: RXT1_0 Mask */ +#define USB0_ENDPTCTRL0_RXE_Pos 7 /*!< USB0 ENDPTCTRL0: RXE Position */ +#define USB0_ENDPTCTRL0_RXE_Msk (0x01UL << USB0_ENDPTCTRL0_RXE_Pos) /*!< USB0 ENDPTCTRL0: RXE Mask */ +#define USB0_ENDPTCTRL0_TXS_Pos 16 /*!< USB0 ENDPTCTRL0: TXS Position */ +#define USB0_ENDPTCTRL0_TXS_Msk (0x01UL << USB0_ENDPTCTRL0_TXS_Pos) /*!< USB0 ENDPTCTRL0: TXS Mask */ +#define USB0_ENDPTCTRL0_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL0: TXT1_0 Position */ +#define USB0_ENDPTCTRL0_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL0_TXT1_0_Pos) /*!< USB0 ENDPTCTRL0: TXT1_0 Mask */ +#define USB0_ENDPTCTRL0_TXE_Pos 23 /*!< USB0 ENDPTCTRL0: TXE Position */ +#define USB0_ENDPTCTRL0_TXE_Msk (0x01UL << USB0_ENDPTCTRL0_TXE_Pos) /*!< USB0 ENDPTCTRL0: TXE Mask */ + +/* ------------------------------- USB0_ENDPTCTRL1 ------------------------------ */ +#define USB0_ENDPTCTRL1_RXS_Pos 0 /*!< USB0 ENDPTCTRL1: RXS Position */ +#define USB0_ENDPTCTRL1_RXS_Msk (0x01UL << USB0_ENDPTCTRL1_RXS_Pos) /*!< USB0 ENDPTCTRL1: RXS Mask */ +#define USB0_ENDPTCTRL1_RXT_Pos 2 /*!< USB0 ENDPTCTRL1: RXT Position */ +#define USB0_ENDPTCTRL1_RXT_Msk (0x03UL << USB0_ENDPTCTRL1_RXT_Pos) /*!< USB0 ENDPTCTRL1: RXT Mask */ +#define USB0_ENDPTCTRL1_RXI_Pos 5 /*!< USB0 ENDPTCTRL1: RXI Position */ +#define USB0_ENDPTCTRL1_RXI_Msk (0x01UL << USB0_ENDPTCTRL1_RXI_Pos) /*!< USB0 ENDPTCTRL1: RXI Mask */ +#define USB0_ENDPTCTRL1_RXR_Pos 6 /*!< USB0 ENDPTCTRL1: RXR Position */ +#define USB0_ENDPTCTRL1_RXR_Msk (0x01UL << USB0_ENDPTCTRL1_RXR_Pos) /*!< USB0 ENDPTCTRL1: RXR Mask */ +#define USB0_ENDPTCTRL1_RXE_Pos 7 /*!< USB0 ENDPTCTRL1: RXE Position */ +#define USB0_ENDPTCTRL1_RXE_Msk (0x01UL << USB0_ENDPTCTRL1_RXE_Pos) /*!< USB0 ENDPTCTRL1: RXE Mask */ +#define USB0_ENDPTCTRL1_TXS_Pos 16 /*!< USB0 ENDPTCTRL1: TXS Position */ +#define USB0_ENDPTCTRL1_TXS_Msk (0x01UL << USB0_ENDPTCTRL1_TXS_Pos) /*!< USB0 ENDPTCTRL1: TXS Mask */ +#define USB0_ENDPTCTRL1_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL1: TXT1_0 Position */ +#define USB0_ENDPTCTRL1_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL1_TXT1_0_Pos) /*!< USB0 ENDPTCTRL1: TXT1_0 Mask */ +#define USB0_ENDPTCTRL1_TXI_Pos 21 /*!< USB0 ENDPTCTRL1: TXI Position */ +#define USB0_ENDPTCTRL1_TXI_Msk (0x01UL << USB0_ENDPTCTRL1_TXI_Pos) /*!< USB0 ENDPTCTRL1: TXI Mask */ +#define USB0_ENDPTCTRL1_TXR_Pos 22 /*!< USB0 ENDPTCTRL1: TXR Position */ +#define USB0_ENDPTCTRL1_TXR_Msk (0x01UL << USB0_ENDPTCTRL1_TXR_Pos) /*!< USB0 ENDPTCTRL1: TXR Mask */ +#define USB0_ENDPTCTRL1_TXE_Pos 23 /*!< USB0 ENDPTCTRL1: TXE Position */ +#define USB0_ENDPTCTRL1_TXE_Msk (0x01UL << USB0_ENDPTCTRL1_TXE_Pos) /*!< USB0 ENDPTCTRL1: TXE Mask */ + +/* ------------------------------- USB0_ENDPTCTRL2 ------------------------------ */ +#define USB0_ENDPTCTRL2_RXS_Pos 0 /*!< USB0 ENDPTCTRL2: RXS Position */ +#define USB0_ENDPTCTRL2_RXS_Msk (0x01UL << USB0_ENDPTCTRL2_RXS_Pos) /*!< USB0 ENDPTCTRL2: RXS Mask */ +#define USB0_ENDPTCTRL2_RXT_Pos 2 /*!< USB0 ENDPTCTRL2: RXT Position */ +#define USB0_ENDPTCTRL2_RXT_Msk (0x03UL << USB0_ENDPTCTRL2_RXT_Pos) /*!< USB0 ENDPTCTRL2: RXT Mask */ +#define USB0_ENDPTCTRL2_RXI_Pos 5 /*!< USB0 ENDPTCTRL2: RXI Position */ +#define USB0_ENDPTCTRL2_RXI_Msk (0x01UL << USB0_ENDPTCTRL2_RXI_Pos) /*!< USB0 ENDPTCTRL2: RXI Mask */ +#define USB0_ENDPTCTRL2_RXR_Pos 6 /*!< USB0 ENDPTCTRL2: RXR Position */ +#define USB0_ENDPTCTRL2_RXR_Msk (0x01UL << USB0_ENDPTCTRL2_RXR_Pos) /*!< USB0 ENDPTCTRL2: RXR Mask */ +#define USB0_ENDPTCTRL2_RXE_Pos 7 /*!< USB0 ENDPTCTRL2: RXE Position */ +#define USB0_ENDPTCTRL2_RXE_Msk (0x01UL << USB0_ENDPTCTRL2_RXE_Pos) /*!< USB0 ENDPTCTRL2: RXE Mask */ +#define USB0_ENDPTCTRL2_TXS_Pos 16 /*!< USB0 ENDPTCTRL2: TXS Position */ +#define USB0_ENDPTCTRL2_TXS_Msk (0x01UL << USB0_ENDPTCTRL2_TXS_Pos) /*!< USB0 ENDPTCTRL2: TXS Mask */ +#define USB0_ENDPTCTRL2_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL2: TXT1_0 Position */ +#define USB0_ENDPTCTRL2_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL2_TXT1_0_Pos) /*!< USB0 ENDPTCTRL2: TXT1_0 Mask */ +#define USB0_ENDPTCTRL2_TXI_Pos 21 /*!< USB0 ENDPTCTRL2: TXI Position */ +#define USB0_ENDPTCTRL2_TXI_Msk (0x01UL << USB0_ENDPTCTRL2_TXI_Pos) /*!< USB0 ENDPTCTRL2: TXI Mask */ +#define USB0_ENDPTCTRL2_TXR_Pos 22 /*!< USB0 ENDPTCTRL2: TXR Position */ +#define USB0_ENDPTCTRL2_TXR_Msk (0x01UL << USB0_ENDPTCTRL2_TXR_Pos) /*!< USB0 ENDPTCTRL2: TXR Mask */ +#define USB0_ENDPTCTRL2_TXE_Pos 23 /*!< USB0 ENDPTCTRL2: TXE Position */ +#define USB0_ENDPTCTRL2_TXE_Msk (0x01UL << USB0_ENDPTCTRL2_TXE_Pos) /*!< USB0 ENDPTCTRL2: TXE Mask */ + +/* ------------------------------- USB0_ENDPTCTRL3 ------------------------------ */ +#define USB0_ENDPTCTRL3_RXS_Pos 0 /*!< USB0 ENDPTCTRL3: RXS Position */ +#define USB0_ENDPTCTRL3_RXS_Msk (0x01UL << USB0_ENDPTCTRL3_RXS_Pos) /*!< USB0 ENDPTCTRL3: RXS Mask */ +#define USB0_ENDPTCTRL3_RXT_Pos 2 /*!< USB0 ENDPTCTRL3: RXT Position */ +#define USB0_ENDPTCTRL3_RXT_Msk (0x03UL << USB0_ENDPTCTRL3_RXT_Pos) /*!< USB0 ENDPTCTRL3: RXT Mask */ +#define USB0_ENDPTCTRL3_RXI_Pos 5 /*!< USB0 ENDPTCTRL3: RXI Position */ +#define USB0_ENDPTCTRL3_RXI_Msk (0x01UL << USB0_ENDPTCTRL3_RXI_Pos) /*!< USB0 ENDPTCTRL3: RXI Mask */ +#define USB0_ENDPTCTRL3_RXR_Pos 6 /*!< USB0 ENDPTCTRL3: RXR Position */ +#define USB0_ENDPTCTRL3_RXR_Msk (0x01UL << USB0_ENDPTCTRL3_RXR_Pos) /*!< USB0 ENDPTCTRL3: RXR Mask */ +#define USB0_ENDPTCTRL3_RXE_Pos 7 /*!< USB0 ENDPTCTRL3: RXE Position */ +#define USB0_ENDPTCTRL3_RXE_Msk (0x01UL << USB0_ENDPTCTRL3_RXE_Pos) /*!< USB0 ENDPTCTRL3: RXE Mask */ +#define USB0_ENDPTCTRL3_TXS_Pos 16 /*!< USB0 ENDPTCTRL3: TXS Position */ +#define USB0_ENDPTCTRL3_TXS_Msk (0x01UL << USB0_ENDPTCTRL3_TXS_Pos) /*!< USB0 ENDPTCTRL3: TXS Mask */ +#define USB0_ENDPTCTRL3_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL3: TXT1_0 Position */ +#define USB0_ENDPTCTRL3_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL3_TXT1_0_Pos) /*!< USB0 ENDPTCTRL3: TXT1_0 Mask */ +#define USB0_ENDPTCTRL3_TXI_Pos 21 /*!< USB0 ENDPTCTRL3: TXI Position */ +#define USB0_ENDPTCTRL3_TXI_Msk (0x01UL << USB0_ENDPTCTRL3_TXI_Pos) /*!< USB0 ENDPTCTRL3: TXI Mask */ +#define USB0_ENDPTCTRL3_TXR_Pos 22 /*!< USB0 ENDPTCTRL3: TXR Position */ +#define USB0_ENDPTCTRL3_TXR_Msk (0x01UL << USB0_ENDPTCTRL3_TXR_Pos) /*!< USB0 ENDPTCTRL3: TXR Mask */ +#define USB0_ENDPTCTRL3_TXE_Pos 23 /*!< USB0 ENDPTCTRL3: TXE Position */ +#define USB0_ENDPTCTRL3_TXE_Msk (0x01UL << USB0_ENDPTCTRL3_TXE_Pos) /*!< USB0 ENDPTCTRL3: TXE Mask */ + +/* ------------------------------- USB0_ENDPTCTRL4 ------------------------------ */ +#define USB0_ENDPTCTRL4_RXS_Pos 0 /*!< USB0 ENDPTCTRL4: RXS Position */ +#define USB0_ENDPTCTRL4_RXS_Msk (0x01UL << USB0_ENDPTCTRL4_RXS_Pos) /*!< USB0 ENDPTCTRL4: RXS Mask */ +#define USB0_ENDPTCTRL4_RXT_Pos 2 /*!< USB0 ENDPTCTRL4: RXT Position */ +#define USB0_ENDPTCTRL4_RXT_Msk (0x03UL << USB0_ENDPTCTRL4_RXT_Pos) /*!< USB0 ENDPTCTRL4: RXT Mask */ +#define USB0_ENDPTCTRL4_RXI_Pos 5 /*!< USB0 ENDPTCTRL4: RXI Position */ +#define USB0_ENDPTCTRL4_RXI_Msk (0x01UL << USB0_ENDPTCTRL4_RXI_Pos) /*!< USB0 ENDPTCTRL4: RXI Mask */ +#define USB0_ENDPTCTRL4_RXR_Pos 6 /*!< USB0 ENDPTCTRL4: RXR Position */ +#define USB0_ENDPTCTRL4_RXR_Msk (0x01UL << USB0_ENDPTCTRL4_RXR_Pos) /*!< USB0 ENDPTCTRL4: RXR Mask */ +#define USB0_ENDPTCTRL4_RXE_Pos 7 /*!< USB0 ENDPTCTRL4: RXE Position */ +#define USB0_ENDPTCTRL4_RXE_Msk (0x01UL << USB0_ENDPTCTRL4_RXE_Pos) /*!< USB0 ENDPTCTRL4: RXE Mask */ +#define USB0_ENDPTCTRL4_TXS_Pos 16 /*!< USB0 ENDPTCTRL4: TXS Position */ +#define USB0_ENDPTCTRL4_TXS_Msk (0x01UL << USB0_ENDPTCTRL4_TXS_Pos) /*!< USB0 ENDPTCTRL4: TXS Mask */ +#define USB0_ENDPTCTRL4_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL4: TXT1_0 Position */ +#define USB0_ENDPTCTRL4_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL4_TXT1_0_Pos) /*!< USB0 ENDPTCTRL4: TXT1_0 Mask */ +#define USB0_ENDPTCTRL4_TXI_Pos 21 /*!< USB0 ENDPTCTRL4: TXI Position */ +#define USB0_ENDPTCTRL4_TXI_Msk (0x01UL << USB0_ENDPTCTRL4_TXI_Pos) /*!< USB0 ENDPTCTRL4: TXI Mask */ +#define USB0_ENDPTCTRL4_TXR_Pos 22 /*!< USB0 ENDPTCTRL4: TXR Position */ +#define USB0_ENDPTCTRL4_TXR_Msk (0x01UL << USB0_ENDPTCTRL4_TXR_Pos) /*!< USB0 ENDPTCTRL4: TXR Mask */ +#define USB0_ENDPTCTRL4_TXE_Pos 23 /*!< USB0 ENDPTCTRL4: TXE Position */ +#define USB0_ENDPTCTRL4_TXE_Msk (0x01UL << USB0_ENDPTCTRL4_TXE_Pos) /*!< USB0 ENDPTCTRL4: TXE Mask */ + +/* ------------------------------- USB0_ENDPTCTRL5 ------------------------------ */ +#define USB0_ENDPTCTRL5_RXS_Pos 0 /*!< USB0 ENDPTCTRL5: RXS Position */ +#define USB0_ENDPTCTRL5_RXS_Msk (0x01UL << USB0_ENDPTCTRL5_RXS_Pos) /*!< USB0 ENDPTCTRL5: RXS Mask */ +#define USB0_ENDPTCTRL5_RXT_Pos 2 /*!< USB0 ENDPTCTRL5: RXT Position */ +#define USB0_ENDPTCTRL5_RXT_Msk (0x03UL << USB0_ENDPTCTRL5_RXT_Pos) /*!< USB0 ENDPTCTRL5: RXT Mask */ +#define USB0_ENDPTCTRL5_RXI_Pos 5 /*!< USB0 ENDPTCTRL5: RXI Position */ +#define USB0_ENDPTCTRL5_RXI_Msk (0x01UL << USB0_ENDPTCTRL5_RXI_Pos) /*!< USB0 ENDPTCTRL5: RXI Mask */ +#define USB0_ENDPTCTRL5_RXR_Pos 6 /*!< USB0 ENDPTCTRL5: RXR Position */ +#define USB0_ENDPTCTRL5_RXR_Msk (0x01UL << USB0_ENDPTCTRL5_RXR_Pos) /*!< USB0 ENDPTCTRL5: RXR Mask */ +#define USB0_ENDPTCTRL5_RXE_Pos 7 /*!< USB0 ENDPTCTRL5: RXE Position */ +#define USB0_ENDPTCTRL5_RXE_Msk (0x01UL << USB0_ENDPTCTRL5_RXE_Pos) /*!< USB0 ENDPTCTRL5: RXE Mask */ +#define USB0_ENDPTCTRL5_TXS_Pos 16 /*!< USB0 ENDPTCTRL5: TXS Position */ +#define USB0_ENDPTCTRL5_TXS_Msk (0x01UL << USB0_ENDPTCTRL5_TXS_Pos) /*!< USB0 ENDPTCTRL5: TXS Mask */ +#define USB0_ENDPTCTRL5_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL5: TXT1_0 Position */ +#define USB0_ENDPTCTRL5_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL5_TXT1_0_Pos) /*!< USB0 ENDPTCTRL5: TXT1_0 Mask */ +#define USB0_ENDPTCTRL5_TXI_Pos 21 /*!< USB0 ENDPTCTRL5: TXI Position */ +#define USB0_ENDPTCTRL5_TXI_Msk (0x01UL << USB0_ENDPTCTRL5_TXI_Pos) /*!< USB0 ENDPTCTRL5: TXI Mask */ +#define USB0_ENDPTCTRL5_TXR_Pos 22 /*!< USB0 ENDPTCTRL5: TXR Position */ +#define USB0_ENDPTCTRL5_TXR_Msk (0x01UL << USB0_ENDPTCTRL5_TXR_Pos) /*!< USB0 ENDPTCTRL5: TXR Mask */ +#define USB0_ENDPTCTRL5_TXE_Pos 23 /*!< USB0 ENDPTCTRL5: TXE Position */ +#define USB0_ENDPTCTRL5_TXE_Msk (0x01UL << USB0_ENDPTCTRL5_TXE_Pos) /*!< USB0 ENDPTCTRL5: TXE Mask */ + + +/* ================================================================================ */ +/* ================ struct 'USB1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- USB1_CAPLENGTH ------------------------------- */ +#define USB1_CAPLENGTH_CAPLENGTH_Pos 0 /*!< USB1 CAPLENGTH: CAPLENGTH Position */ +#define USB1_CAPLENGTH_CAPLENGTH_Msk (0x000000ffUL << USB1_CAPLENGTH_CAPLENGTH_Pos) /*!< USB1 CAPLENGTH: CAPLENGTH Mask */ +#define USB1_CAPLENGTH_HCIVERSION_Pos 8 /*!< USB1 CAPLENGTH: HCIVERSION Position */ +#define USB1_CAPLENGTH_HCIVERSION_Msk (0x0000ffffUL << USB1_CAPLENGTH_HCIVERSION_Pos) /*!< USB1 CAPLENGTH: HCIVERSION Mask */ + +/* ------------------------------- USB1_HCSPARAMS ------------------------------- */ +#define USB1_HCSPARAMS_N_PORTS_Pos 0 /*!< USB1 HCSPARAMS: N_PORTS Position */ +#define USB1_HCSPARAMS_N_PORTS_Msk (0x0fUL << USB1_HCSPARAMS_N_PORTS_Pos) /*!< USB1 HCSPARAMS: N_PORTS Mask */ +#define USB1_HCSPARAMS_PPC_Pos 4 /*!< USB1 HCSPARAMS: PPC Position */ +#define USB1_HCSPARAMS_PPC_Msk (0x01UL << USB1_HCSPARAMS_PPC_Pos) /*!< USB1 HCSPARAMS: PPC Mask */ +#define USB1_HCSPARAMS_N_PCC_Pos 8 /*!< USB1 HCSPARAMS: N_PCC Position */ +#define USB1_HCSPARAMS_N_PCC_Msk (0x0fUL << USB1_HCSPARAMS_N_PCC_Pos) /*!< USB1 HCSPARAMS: N_PCC Mask */ +#define USB1_HCSPARAMS_N_CC_Pos 12 /*!< USB1 HCSPARAMS: N_CC Position */ +#define USB1_HCSPARAMS_N_CC_Msk (0x0fUL << USB1_HCSPARAMS_N_CC_Pos) /*!< USB1 HCSPARAMS: N_CC Mask */ +#define USB1_HCSPARAMS_PI_Pos 16 /*!< USB1 HCSPARAMS: PI Position */ +#define USB1_HCSPARAMS_PI_Msk (0x01UL << USB1_HCSPARAMS_PI_Pos) /*!< USB1 HCSPARAMS: PI Mask */ +#define USB1_HCSPARAMS_N_PTT_Pos 20 /*!< USB1 HCSPARAMS: N_PTT Position */ +#define USB1_HCSPARAMS_N_PTT_Msk (0x0fUL << USB1_HCSPARAMS_N_PTT_Pos) /*!< USB1 HCSPARAMS: N_PTT Mask */ +#define USB1_HCSPARAMS_N_TT_Pos 24 /*!< USB1 HCSPARAMS: N_TT Position */ +#define USB1_HCSPARAMS_N_TT_Msk (0x0fUL << USB1_HCSPARAMS_N_TT_Pos) /*!< USB1 HCSPARAMS: N_TT Mask */ + +/* ------------------------------- USB1_HCCPARAMS ------------------------------- */ +#define USB1_HCCPARAMS_ADC_Pos 0 /*!< USB1 HCCPARAMS: ADC Position */ +#define USB1_HCCPARAMS_ADC_Msk (0x01UL << USB1_HCCPARAMS_ADC_Pos) /*!< USB1 HCCPARAMS: ADC Mask */ +#define USB1_HCCPARAMS_PFL_Pos 1 /*!< USB1 HCCPARAMS: PFL Position */ +#define USB1_HCCPARAMS_PFL_Msk (0x01UL << USB1_HCCPARAMS_PFL_Pos) /*!< USB1 HCCPARAMS: PFL Mask */ +#define USB1_HCCPARAMS_ASP_Pos 2 /*!< USB1 HCCPARAMS: ASP Position */ +#define USB1_HCCPARAMS_ASP_Msk (0x01UL << USB1_HCCPARAMS_ASP_Pos) /*!< USB1 HCCPARAMS: ASP Mask */ +#define USB1_HCCPARAMS_IST_Pos 4 /*!< USB1 HCCPARAMS: IST Position */ +#define USB1_HCCPARAMS_IST_Msk (0x0fUL << USB1_HCCPARAMS_IST_Pos) /*!< USB1 HCCPARAMS: IST Mask */ +#define USB1_HCCPARAMS_EECP_Pos 8 /*!< USB1 HCCPARAMS: EECP Position */ +#define USB1_HCCPARAMS_EECP_Msk (0x000000ffUL << USB1_HCCPARAMS_EECP_Pos) /*!< USB1 HCCPARAMS: EECP Mask */ + +/* ------------------------------- USB1_DCIVERSION ------------------------------ */ +#define USB1_DCIVERSION_DCIVERSION_Pos 0 /*!< USB1 DCIVERSION: DCIVERSION Position */ +#define USB1_DCIVERSION_DCIVERSION_Msk (0x0000ffffUL << USB1_DCIVERSION_DCIVERSION_Pos) /*!< USB1 DCIVERSION: DCIVERSION Mask */ + +/* -------------------------------- USB1_USBCMD_D ------------------------------- */ +#define USB1_USBCMD_D_RS_Pos 0 /*!< USB1 USBCMD_D: RS Position */ +#define USB1_USBCMD_D_RS_Msk (0x01UL << USB1_USBCMD_D_RS_Pos) /*!< USB1 USBCMD_D: RS Mask */ +#define USB1_USBCMD_D_RST_Pos 1 /*!< USB1 USBCMD_D: RST Position */ +#define USB1_USBCMD_D_RST_Msk (0x01UL << USB1_USBCMD_D_RST_Pos) /*!< USB1 USBCMD_D: RST Mask */ +#define USB1_USBCMD_D_SUTW_Pos 13 /*!< USB1 USBCMD_D: SUTW Position */ +#define USB1_USBCMD_D_SUTW_Msk (0x01UL << USB1_USBCMD_D_SUTW_Pos) /*!< USB1 USBCMD_D: SUTW Mask */ +#define USB1_USBCMD_D_ATDTW_Pos 14 /*!< USB1 USBCMD_D: ATDTW Position */ +#define USB1_USBCMD_D_ATDTW_Msk (0x01UL << USB1_USBCMD_D_ATDTW_Pos) /*!< USB1 USBCMD_D: ATDTW Mask */ +#define USB1_USBCMD_D_FS2_Pos 15 /*!< USB1 USBCMD_D: FS2 Position */ +#define USB1_USBCMD_D_FS2_Msk (0x01UL << USB1_USBCMD_D_FS2_Pos) /*!< USB1 USBCMD_D: FS2 Mask */ +#define USB1_USBCMD_D_ITC_Pos 16 /*!< USB1 USBCMD_D: ITC Position */ +#define USB1_USBCMD_D_ITC_Msk (0x000000ffUL << USB1_USBCMD_D_ITC_Pos) /*!< USB1 USBCMD_D: ITC Mask */ + +/* -------------------------------- USB1_USBCMD_H ------------------------------- */ +#define USB1_USBCMD_H_RS_Pos 0 /*!< USB1 USBCMD_H: RS Position */ +#define USB1_USBCMD_H_RS_Msk (0x01UL << USB1_USBCMD_H_RS_Pos) /*!< USB1 USBCMD_H: RS Mask */ +#define USB1_USBCMD_H_RST_Pos 1 /*!< USB1 USBCMD_H: RST Position */ +#define USB1_USBCMD_H_RST_Msk (0x01UL << USB1_USBCMD_H_RST_Pos) /*!< USB1 USBCMD_H: RST Mask */ +#define USB1_USBCMD_H_FS0_Pos 2 /*!< USB1 USBCMD_H: FS0 Position */ +#define USB1_USBCMD_H_FS0_Msk (0x01UL << USB1_USBCMD_H_FS0_Pos) /*!< USB1 USBCMD_H: FS0 Mask */ +#define USB1_USBCMD_H_FS1_Pos 3 /*!< USB1 USBCMD_H: FS1 Position */ +#define USB1_USBCMD_H_FS1_Msk (0x01UL << USB1_USBCMD_H_FS1_Pos) /*!< USB1 USBCMD_H: FS1 Mask */ +#define USB1_USBCMD_H_PSE_Pos 4 /*!< USB1 USBCMD_H: PSE Position */ +#define USB1_USBCMD_H_PSE_Msk (0x01UL << USB1_USBCMD_H_PSE_Pos) /*!< USB1 USBCMD_H: PSE Mask */ +#define USB1_USBCMD_H_ASE_Pos 5 /*!< USB1 USBCMD_H: ASE Position */ +#define USB1_USBCMD_H_ASE_Msk (0x01UL << USB1_USBCMD_H_ASE_Pos) /*!< USB1 USBCMD_H: ASE Mask */ +#define USB1_USBCMD_H_IAA_Pos 6 /*!< USB1 USBCMD_H: IAA Position */ +#define USB1_USBCMD_H_IAA_Msk (0x01UL << USB1_USBCMD_H_IAA_Pos) /*!< USB1 USBCMD_H: IAA Mask */ +#define USB1_USBCMD_H_ASP1_0_Pos 8 /*!< USB1 USBCMD_H: ASP1_0 Position */ +#define USB1_USBCMD_H_ASP1_0_Msk (0x03UL << USB1_USBCMD_H_ASP1_0_Pos) /*!< USB1 USBCMD_H: ASP1_0 Mask */ +#define USB1_USBCMD_H_ASPE_Pos 11 /*!< USB1 USBCMD_H: ASPE Position */ +#define USB1_USBCMD_H_ASPE_Msk (0x01UL << USB1_USBCMD_H_ASPE_Pos) /*!< USB1 USBCMD_H: ASPE Mask */ +#define USB1_USBCMD_H_FS2_Pos 15 /*!< USB1 USBCMD_H: FS2 Position */ +#define USB1_USBCMD_H_FS2_Msk (0x01UL << USB1_USBCMD_H_FS2_Pos) /*!< USB1 USBCMD_H: FS2 Mask */ +#define USB1_USBCMD_H_ITC_Pos 16 /*!< USB1 USBCMD_H: ITC Position */ +#define USB1_USBCMD_H_ITC_Msk (0x000000ffUL << USB1_USBCMD_H_ITC_Pos) /*!< USB1 USBCMD_H: ITC Mask */ + +/* -------------------------------- USB1_USBSTS_D ------------------------------- */ +#define USB1_USBSTS_D_UI_Pos 0 /*!< USB1 USBSTS_D: UI Position */ +#define USB1_USBSTS_D_UI_Msk (0x01UL << USB1_USBSTS_D_UI_Pos) /*!< USB1 USBSTS_D: UI Mask */ +#define USB1_USBSTS_D_UEI_Pos 1 /*!< USB1 USBSTS_D: UEI Position */ +#define USB1_USBSTS_D_UEI_Msk (0x01UL << USB1_USBSTS_D_UEI_Pos) /*!< USB1 USBSTS_D: UEI Mask */ +#define USB1_USBSTS_D_PCI_Pos 2 /*!< USB1 USBSTS_D: PCI Position */ +#define USB1_USBSTS_D_PCI_Msk (0x01UL << USB1_USBSTS_D_PCI_Pos) /*!< USB1 USBSTS_D: PCI Mask */ +#define USB1_USBSTS_D_URI_Pos 6 /*!< USB1 USBSTS_D: URI Position */ +#define USB1_USBSTS_D_URI_Msk (0x01UL << USB1_USBSTS_D_URI_Pos) /*!< USB1 USBSTS_D: URI Mask */ +#define USB1_USBSTS_D_SRI_Pos 7 /*!< USB1 USBSTS_D: SRI Position */ +#define USB1_USBSTS_D_SRI_Msk (0x01UL << USB1_USBSTS_D_SRI_Pos) /*!< USB1 USBSTS_D: SRI Mask */ +#define USB1_USBSTS_D_SLI_Pos 8 /*!< USB1 USBSTS_D: SLI Position */ +#define USB1_USBSTS_D_SLI_Msk (0x01UL << USB1_USBSTS_D_SLI_Pos) /*!< USB1 USBSTS_D: SLI Mask */ +#define USB1_USBSTS_D_NAKI_Pos 16 /*!< USB1 USBSTS_D: NAKI Position */ +#define USB1_USBSTS_D_NAKI_Msk (0x01UL << USB1_USBSTS_D_NAKI_Pos) /*!< USB1 USBSTS_D: NAKI Mask */ + +/* -------------------------------- USB1_USBSTS_H ------------------------------- */ +#define USB1_USBSTS_H_UI_Pos 0 /*!< USB1 USBSTS_H: UI Position */ +#define USB1_USBSTS_H_UI_Msk (0x01UL << USB1_USBSTS_H_UI_Pos) /*!< USB1 USBSTS_H: UI Mask */ +#define USB1_USBSTS_H_UEI_Pos 1 /*!< USB1 USBSTS_H: UEI Position */ +#define USB1_USBSTS_H_UEI_Msk (0x01UL << USB1_USBSTS_H_UEI_Pos) /*!< USB1 USBSTS_H: UEI Mask */ +#define USB1_USBSTS_H_PCI_Pos 2 /*!< USB1 USBSTS_H: PCI Position */ +#define USB1_USBSTS_H_PCI_Msk (0x01UL << USB1_USBSTS_H_PCI_Pos) /*!< USB1 USBSTS_H: PCI Mask */ +#define USB1_USBSTS_H_FRI_Pos 3 /*!< USB1 USBSTS_H: FRI Position */ +#define USB1_USBSTS_H_FRI_Msk (0x01UL << USB1_USBSTS_H_FRI_Pos) /*!< USB1 USBSTS_H: FRI Mask */ +#define USB1_USBSTS_H_AAI_Pos 5 /*!< USB1 USBSTS_H: AAI Position */ +#define USB1_USBSTS_H_AAI_Msk (0x01UL << USB1_USBSTS_H_AAI_Pos) /*!< USB1 USBSTS_H: AAI Mask */ +#define USB1_USBSTS_H_SRI_Pos 7 /*!< USB1 USBSTS_H: SRI Position */ +#define USB1_USBSTS_H_SRI_Msk (0x01UL << USB1_USBSTS_H_SRI_Pos) /*!< USB1 USBSTS_H: SRI Mask */ +#define USB1_USBSTS_H_SLI_Pos 8 /*!< USB1 USBSTS_H: SLI Position */ +#define USB1_USBSTS_H_SLI_Msk (0x01UL << USB1_USBSTS_H_SLI_Pos) /*!< USB1 USBSTS_H: SLI Mask */ +#define USB1_USBSTS_H_HCH_Pos 12 /*!< USB1 USBSTS_H: HCH Position */ +#define USB1_USBSTS_H_HCH_Msk (0x01UL << USB1_USBSTS_H_HCH_Pos) /*!< USB1 USBSTS_H: HCH Mask */ +#define USB1_USBSTS_H_RCL_Pos 13 /*!< USB1 USBSTS_H: RCL Position */ +#define USB1_USBSTS_H_RCL_Msk (0x01UL << USB1_USBSTS_H_RCL_Pos) /*!< USB1 USBSTS_H: RCL Mask */ +#define USB1_USBSTS_H_PS_Pos 14 /*!< USB1 USBSTS_H: PS Position */ +#define USB1_USBSTS_H_PS_Msk (0x01UL << USB1_USBSTS_H_PS_Pos) /*!< USB1 USBSTS_H: PS Mask */ +#define USB1_USBSTS_H_AS_Pos 15 /*!< USB1 USBSTS_H: AS Position */ +#define USB1_USBSTS_H_AS_Msk (0x01UL << USB1_USBSTS_H_AS_Pos) /*!< USB1 USBSTS_H: AS Mask */ +#define USB1_USBSTS_H_UAI_Pos 18 /*!< USB1 USBSTS_H: UAI Position */ +#define USB1_USBSTS_H_UAI_Msk (0x01UL << USB1_USBSTS_H_UAI_Pos) /*!< USB1 USBSTS_H: UAI Mask */ +#define USB1_USBSTS_H_UPI_Pos 19 /*!< USB1 USBSTS_H: UPI Position */ +#define USB1_USBSTS_H_UPI_Msk (0x01UL << USB1_USBSTS_H_UPI_Pos) /*!< USB1 USBSTS_H: UPI Mask */ + +/* ------------------------------- USB1_USBINTR_D ------------------------------- */ +#define USB1_USBINTR_D_UE_Pos 0 /*!< USB1 USBINTR_D: UE Position */ +#define USB1_USBINTR_D_UE_Msk (0x01UL << USB1_USBINTR_D_UE_Pos) /*!< USB1 USBINTR_D: UE Mask */ +#define USB1_USBINTR_D_UEE_Pos 1 /*!< USB1 USBINTR_D: UEE Position */ +#define USB1_USBINTR_D_UEE_Msk (0x01UL << USB1_USBINTR_D_UEE_Pos) /*!< USB1 USBINTR_D: UEE Mask */ +#define USB1_USBINTR_D_PCE_Pos 2 /*!< USB1 USBINTR_D: PCE Position */ +#define USB1_USBINTR_D_PCE_Msk (0x01UL << USB1_USBINTR_D_PCE_Pos) /*!< USB1 USBINTR_D: PCE Mask */ +#define USB1_USBINTR_D_URE_Pos 6 /*!< USB1 USBINTR_D: URE Position */ +#define USB1_USBINTR_D_URE_Msk (0x01UL << USB1_USBINTR_D_URE_Pos) /*!< USB1 USBINTR_D: URE Mask */ +#define USB1_USBINTR_D_SRE_Pos 7 /*!< USB1 USBINTR_D: SRE Position */ +#define USB1_USBINTR_D_SRE_Msk (0x01UL << USB1_USBINTR_D_SRE_Pos) /*!< USB1 USBINTR_D: SRE Mask */ +#define USB1_USBINTR_D_SLE_Pos 8 /*!< USB1 USBINTR_D: SLE Position */ +#define USB1_USBINTR_D_SLE_Msk (0x01UL << USB1_USBINTR_D_SLE_Pos) /*!< USB1 USBINTR_D: SLE Mask */ +#define USB1_USBINTR_D_NAKE_Pos 16 /*!< USB1 USBINTR_D: NAKE Position */ +#define USB1_USBINTR_D_NAKE_Msk (0x01UL << USB1_USBINTR_D_NAKE_Pos) /*!< USB1 USBINTR_D: NAKE Mask */ +#define USB1_USBINTR_D_UAIE_Pos 18 /*!< USB1 USBINTR_D: UAIE Position */ +#define USB1_USBINTR_D_UAIE_Msk (0x01UL << USB1_USBINTR_D_UAIE_Pos) /*!< USB1 USBINTR_D: UAIE Mask */ +#define USB1_USBINTR_D_UPIA_Pos 19 /*!< USB1 USBINTR_D: UPIA Position */ +#define USB1_USBINTR_D_UPIA_Msk (0x01UL << USB1_USBINTR_D_UPIA_Pos) /*!< USB1 USBINTR_D: UPIA Mask */ + +/* ------------------------------- USB1_USBINTR_H ------------------------------- */ +#define USB1_USBINTR_H_UE_Pos 0 /*!< USB1 USBINTR_H: UE Position */ +#define USB1_USBINTR_H_UE_Msk (0x01UL << USB1_USBINTR_H_UE_Pos) /*!< USB1 USBINTR_H: UE Mask */ +#define USB1_USBINTR_H_UEE_Pos 1 /*!< USB1 USBINTR_H: UEE Position */ +#define USB1_USBINTR_H_UEE_Msk (0x01UL << USB1_USBINTR_H_UEE_Pos) /*!< USB1 USBINTR_H: UEE Mask */ +#define USB1_USBINTR_H_PCE_Pos 2 /*!< USB1 USBINTR_H: PCE Position */ +#define USB1_USBINTR_H_PCE_Msk (0x01UL << USB1_USBINTR_H_PCE_Pos) /*!< USB1 USBINTR_H: PCE Mask */ +#define USB1_USBINTR_H_FRE_Pos 3 /*!< USB1 USBINTR_H: FRE Position */ +#define USB1_USBINTR_H_FRE_Msk (0x01UL << USB1_USBINTR_H_FRE_Pos) /*!< USB1 USBINTR_H: FRE Mask */ +#define USB1_USBINTR_H_AAE_Pos 5 /*!< USB1 USBINTR_H: AAE Position */ +#define USB1_USBINTR_H_AAE_Msk (0x01UL << USB1_USBINTR_H_AAE_Pos) /*!< USB1 USBINTR_H: AAE Mask */ +#define USB1_USBINTR_H_SRE_Pos 7 /*!< USB1 USBINTR_H: SRE Position */ +#define USB1_USBINTR_H_SRE_Msk (0x01UL << USB1_USBINTR_H_SRE_Pos) /*!< USB1 USBINTR_H: SRE Mask */ +#define USB1_USBINTR_H_UAIE_Pos 18 /*!< USB1 USBINTR_H: UAIE Position */ +#define USB1_USBINTR_H_UAIE_Msk (0x01UL << USB1_USBINTR_H_UAIE_Pos) /*!< USB1 USBINTR_H: UAIE Mask */ +#define USB1_USBINTR_H_UPIA_Pos 19 /*!< USB1 USBINTR_H: UPIA Position */ +#define USB1_USBINTR_H_UPIA_Msk (0x01UL << USB1_USBINTR_H_UPIA_Pos) /*!< USB1 USBINTR_H: UPIA Mask */ + +/* ------------------------------- USB1_FRINDEX_D ------------------------------- */ +#define USB1_FRINDEX_D_FRINDEX2_0_Pos 0 /*!< USB1 FRINDEX_D: FRINDEX2_0 Position */ +#define USB1_FRINDEX_D_FRINDEX2_0_Msk (0x07UL << USB1_FRINDEX_D_FRINDEX2_0_Pos) /*!< USB1 FRINDEX_D: FRINDEX2_0 Mask */ +#define USB1_FRINDEX_D_FRINDEX13_3_Pos 3 /*!< USB1 FRINDEX_D: FRINDEX13_3 Position */ +#define USB1_FRINDEX_D_FRINDEX13_3_Msk (0x000007ffUL << USB1_FRINDEX_D_FRINDEX13_3_Pos) /*!< USB1 FRINDEX_D: FRINDEX13_3 Mask */ + +/* ------------------------------- USB1_FRINDEX_H ------------------------------- */ +#define USB1_FRINDEX_H_FRINDEX2_0_Pos 0 /*!< USB1 FRINDEX_H: FRINDEX2_0 Position */ +#define USB1_FRINDEX_H_FRINDEX2_0_Msk (0x07UL << USB1_FRINDEX_H_FRINDEX2_0_Pos) /*!< USB1 FRINDEX_H: FRINDEX2_0 Mask */ +#define USB1_FRINDEX_H_FRINDEX12_3_Pos 3 /*!< USB1 FRINDEX_H: FRINDEX12_3 Position */ +#define USB1_FRINDEX_H_FRINDEX12_3_Msk (0x000003ffUL << USB1_FRINDEX_H_FRINDEX12_3_Pos) /*!< USB1 FRINDEX_H: FRINDEX12_3 Mask */ + +/* ------------------------------- USB1_DEVICEADDR ------------------------------ */ +#define USB1_DEVICEADDR_USBADRA_Pos 24 /*!< USB1 DEVICEADDR: USBADRA Position */ +#define USB1_DEVICEADDR_USBADRA_Msk (0x01UL << USB1_DEVICEADDR_USBADRA_Pos) /*!< USB1 DEVICEADDR: USBADRA Mask */ +#define USB1_DEVICEADDR_USBADR_Pos 25 /*!< USB1 DEVICEADDR: USBADR Position */ +#define USB1_DEVICEADDR_USBADR_Msk (0x7fUL << USB1_DEVICEADDR_USBADR_Pos) /*!< USB1 DEVICEADDR: USBADR Mask */ + +/* ---------------------------- USB1_PERIODICLISTBASE --------------------------- */ +#define USB1_PERIODICLISTBASE_PERBASE31_12_Pos 12 /*!< USB1 PERIODICLISTBASE: PERBASE31_12 Position */ +#define USB1_PERIODICLISTBASE_PERBASE31_12_Msk (0x000fffffUL << USB1_PERIODICLISTBASE_PERBASE31_12_Pos)/*!< USB1 PERIODICLISTBASE: PERBASE31_12 Mask */ + +/* ---------------------------- USB1_ENDPOINTLISTADDR --------------------------- */ +#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos 11 /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Position */ +#define USB1_ENDPOINTLISTADDR_EPBASE31_11_Msk (0x001fffffUL << USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos) /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Mask */ + +/* ----------------------------- USB1_ASYNCLISTADDR ----------------------------- */ +#define USB1_ASYNCLISTADDR_ASYBASE31_5_Pos 5 /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Position */ +#define USB1_ASYNCLISTADDR_ASYBASE31_5_Msk (0x07ffffffUL << USB1_ASYNCLISTADDR_ASYBASE31_5_Pos) /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Mask */ + +/* --------------------------------- USB1_TTCTRL -------------------------------- */ +#define USB1_TTCTRL_TTHA_Pos 24 /*!< USB1 TTCTRL: TTHA Position */ +#define USB1_TTCTRL_TTHA_Msk (0x7fUL << USB1_TTCTRL_TTHA_Pos) /*!< USB1 TTCTRL: TTHA Mask */ + +/* ------------------------------- USB1_BURSTSIZE ------------------------------- */ +#define USB1_BURSTSIZE_RXPBURST_Pos 0 /*!< USB1 BURSTSIZE: RXPBURST Position */ +#define USB1_BURSTSIZE_RXPBURST_Msk (0x000000ffUL << USB1_BURSTSIZE_RXPBURST_Pos) /*!< USB1 BURSTSIZE: RXPBURST Mask */ +#define USB1_BURSTSIZE_TXPBURST_Pos 8 /*!< USB1 BURSTSIZE: TXPBURST Position */ +#define USB1_BURSTSIZE_TXPBURST_Msk (0x000000ffUL << USB1_BURSTSIZE_TXPBURST_Pos) /*!< USB1 BURSTSIZE: TXPBURST Mask */ + +/* ------------------------------ USB1_TXFILLTUNING ----------------------------- */ +#define USB1_TXFILLTUNING_TXSCHOH_Pos 0 /*!< USB1 TXFILLTUNING: TXSCHOH Position */ +#define USB1_TXFILLTUNING_TXSCHOH_Msk (0x000000ffUL << USB1_TXFILLTUNING_TXSCHOH_Pos) /*!< USB1 TXFILLTUNING: TXSCHOH Mask */ +#define USB1_TXFILLTUNING_TXSCHEATLTH_Pos 8 /*!< USB1 TXFILLTUNING: TXSCHEATLTH Position */ +#define USB1_TXFILLTUNING_TXSCHEATLTH_Msk (0x1fUL << USB1_TXFILLTUNING_TXSCHEATLTH_Pos) /*!< USB1 TXFILLTUNING: TXSCHEATLTH Mask */ +#define USB1_TXFILLTUNING_TXFIFOTHRES_Pos 16 /*!< USB1 TXFILLTUNING: TXFIFOTHRES Position */ +#define USB1_TXFILLTUNING_TXFIFOTHRES_Msk (0x3fUL << USB1_TXFILLTUNING_TXFIFOTHRES_Pos) /*!< USB1 TXFILLTUNING: TXFIFOTHRES Mask */ + +/* ------------------------------ USB1_ULPIVIEWPORT ----------------------------- */ +#define USB1_ULPIVIEWPORT_ULPIDATWR_Pos 0 /*!< USB1 ULPIVIEWPORT: ULPIDATWR Position */ +#define USB1_ULPIVIEWPORT_ULPIDATWR_Msk (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATWR_Pos) /*!< USB1 ULPIVIEWPORT: ULPIDATWR Mask */ +#define USB1_ULPIVIEWPORT_ULPIDATRD_Pos 8 /*!< USB1 ULPIVIEWPORT: ULPIDATRD Position */ +#define USB1_ULPIVIEWPORT_ULPIDATRD_Msk (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATRD_Pos) /*!< USB1 ULPIVIEWPORT: ULPIDATRD Mask */ +#define USB1_ULPIVIEWPORT_ULPIADDR_Pos 16 /*!< USB1 ULPIVIEWPORT: ULPIADDR Position */ +#define USB1_ULPIVIEWPORT_ULPIADDR_Msk (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIADDR_Pos) /*!< USB1 ULPIVIEWPORT: ULPIADDR Mask */ +#define USB1_ULPIVIEWPORT_ULPIPORT_Pos 24 /*!< USB1 ULPIVIEWPORT: ULPIPORT Position */ +#define USB1_ULPIVIEWPORT_ULPIPORT_Msk (0x07UL << USB1_ULPIVIEWPORT_ULPIPORT_Pos) /*!< USB1 ULPIVIEWPORT: ULPIPORT Mask */ +#define USB1_ULPIVIEWPORT_ULPISS_Pos 27 /*!< USB1 ULPIVIEWPORT: ULPISS Position */ +#define USB1_ULPIVIEWPORT_ULPISS_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPISS_Pos) /*!< USB1 ULPIVIEWPORT: ULPISS Mask */ +#define USB1_ULPIVIEWPORT_ULPIRW_Pos 29 /*!< USB1 ULPIVIEWPORT: ULPIRW Position */ +#define USB1_ULPIVIEWPORT_ULPIRW_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPIRW_Pos) /*!< USB1 ULPIVIEWPORT: ULPIRW Mask */ +#define USB1_ULPIVIEWPORT_ULPIRUN_Pos 30 /*!< USB1 ULPIVIEWPORT: ULPIRUN Position */ +#define USB1_ULPIVIEWPORT_ULPIRUN_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPIRUN_Pos) /*!< USB1 ULPIVIEWPORT: ULPIRUN Mask */ +#define USB1_ULPIVIEWPORT_ULPIWU_Pos 31 /*!< USB1 ULPIVIEWPORT: ULPIWU Position */ +#define USB1_ULPIVIEWPORT_ULPIWU_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPIWU_Pos) /*!< USB1 ULPIVIEWPORT: ULPIWU Mask */ + +/* ------------------------------- USB1_BINTERVAL ------------------------------- */ +#define USB1_BINTERVAL_BINT_Pos 0 /*!< USB1 BINTERVAL: BINT Position */ +#define USB1_BINTERVAL_BINT_Msk (0x0fUL << USB1_BINTERVAL_BINT_Pos) /*!< USB1 BINTERVAL: BINT Mask */ + +/* -------------------------------- USB1_ENDPTNAK ------------------------------- */ +#define USB1_ENDPTNAK_EPRN0_Pos 0 /*!< USB1 ENDPTNAK: EPRN0 Position */ +#define USB1_ENDPTNAK_EPRN0_Msk (0x01UL << USB1_ENDPTNAK_EPRN0_Pos) /*!< USB1 ENDPTNAK: EPRN0 Mask */ +#define USB1_ENDPTNAK_EPRN1_Pos 1 /*!< USB1 ENDPTNAK: EPRN1 Position */ +#define USB1_ENDPTNAK_EPRN1_Msk (0x01UL << USB1_ENDPTNAK_EPRN1_Pos) /*!< USB1 ENDPTNAK: EPRN1 Mask */ +#define USB1_ENDPTNAK_EPRN2_Pos 2 /*!< USB1 ENDPTNAK: EPRN2 Position */ +#define USB1_ENDPTNAK_EPRN2_Msk (0x01UL << USB1_ENDPTNAK_EPRN2_Pos) /*!< USB1 ENDPTNAK: EPRN2 Mask */ +#define USB1_ENDPTNAK_EPRN3_Pos 3 /*!< USB1 ENDPTNAK: EPRN3 Position */ +#define USB1_ENDPTNAK_EPRN3_Msk (0x01UL << USB1_ENDPTNAK_EPRN3_Pos) /*!< USB1 ENDPTNAK: EPRN3 Mask */ +#define USB1_ENDPTNAK_EPTN16_Pos 16 /*!< USB1 ENDPTNAK: EPTN16 Position */ +#define USB1_ENDPTNAK_EPTN16_Msk (0x01UL << USB1_ENDPTNAK_EPTN16_Pos) /*!< USB1 ENDPTNAK: EPTN16 Mask */ +#define USB1_ENDPTNAK_EPTN17_Pos 17 /*!< USB1 ENDPTNAK: EPTN17 Position */ +#define USB1_ENDPTNAK_EPTN17_Msk (0x01UL << USB1_ENDPTNAK_EPTN17_Pos) /*!< USB1 ENDPTNAK: EPTN17 Mask */ +#define USB1_ENDPTNAK_EPTN18_Pos 18 /*!< USB1 ENDPTNAK: EPTN18 Position */ +#define USB1_ENDPTNAK_EPTN18_Msk (0x01UL << USB1_ENDPTNAK_EPTN18_Pos) /*!< USB1 ENDPTNAK: EPTN18 Mask */ +#define USB1_ENDPTNAK_EPTN19_Pos 19 /*!< USB1 ENDPTNAK: EPTN19 Position */ +#define USB1_ENDPTNAK_EPTN19_Msk (0x01UL << USB1_ENDPTNAK_EPTN19_Pos) /*!< USB1 ENDPTNAK: EPTN19 Mask */ + +/* ------------------------------- USB1_ENDPTNAKEN ------------------------------ */ +#define USB1_ENDPTNAKEN_EPRNE0_Pos 0 /*!< USB1 ENDPTNAKEN: EPRNE0 Position */ +#define USB1_ENDPTNAKEN_EPRNE0_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE0_Pos) /*!< USB1 ENDPTNAKEN: EPRNE0 Mask */ +#define USB1_ENDPTNAKEN_EPRNE1_Pos 1 /*!< USB1 ENDPTNAKEN: EPRNE1 Position */ +#define USB1_ENDPTNAKEN_EPRNE1_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE1_Pos) /*!< USB1 ENDPTNAKEN: EPRNE1 Mask */ +#define USB1_ENDPTNAKEN_EPRNE2_Pos 2 /*!< USB1 ENDPTNAKEN: EPRNE2 Position */ +#define USB1_ENDPTNAKEN_EPRNE2_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE2_Pos) /*!< USB1 ENDPTNAKEN: EPRNE2 Mask */ +#define USB1_ENDPTNAKEN_EPRNE3_Pos 3 /*!< USB1 ENDPTNAKEN: EPRNE3 Position */ +#define USB1_ENDPTNAKEN_EPRNE3_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE3_Pos) /*!< USB1 ENDPTNAKEN: EPRNE3 Mask */ +#define USB1_ENDPTNAKEN_EPTNE16_Pos 16 /*!< USB1 ENDPTNAKEN: EPTNE16 Position */ +#define USB1_ENDPTNAKEN_EPTNE16_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE16_Pos) /*!< USB1 ENDPTNAKEN: EPTNE16 Mask */ +#define USB1_ENDPTNAKEN_EPTNE17_Pos 17 /*!< USB1 ENDPTNAKEN: EPTNE17 Position */ +#define USB1_ENDPTNAKEN_EPTNE17_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE17_Pos) /*!< USB1 ENDPTNAKEN: EPTNE17 Mask */ +#define USB1_ENDPTNAKEN_EPTNE18_Pos 18 /*!< USB1 ENDPTNAKEN: EPTNE18 Position */ +#define USB1_ENDPTNAKEN_EPTNE18_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE18_Pos) /*!< USB1 ENDPTNAKEN: EPTNE18 Mask */ +#define USB1_ENDPTNAKEN_EPTNE19_Pos 19 /*!< USB1 ENDPTNAKEN: EPTNE19 Position */ +#define USB1_ENDPTNAKEN_EPTNE19_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE19_Pos) /*!< USB1 ENDPTNAKEN: EPTNE19 Mask */ + +/* ------------------------------- USB1_PORTSC1_D ------------------------------- */ +#define USB1_PORTSC1_D_CCS_Pos 0 /*!< USB1 PORTSC1_D: CCS Position */ +#define USB1_PORTSC1_D_CCS_Msk (0x01UL << USB1_PORTSC1_D_CCS_Pos) /*!< USB1 PORTSC1_D: CCS Mask */ +#define USB1_PORTSC1_D_CSC_Pos 1 /*!< USB1 PORTSC1_D: CSC Position */ +#define USB1_PORTSC1_D_CSC_Msk (0x01UL << USB1_PORTSC1_D_CSC_Pos) /*!< USB1 PORTSC1_D: CSC Mask */ +#define USB1_PORTSC1_D_PE_Pos 2 /*!< USB1 PORTSC1_D: PE Position */ +#define USB1_PORTSC1_D_PE_Msk (0x01UL << USB1_PORTSC1_D_PE_Pos) /*!< USB1 PORTSC1_D: PE Mask */ +#define USB1_PORTSC1_D_PEC_Pos 3 /*!< USB1 PORTSC1_D: PEC Position */ +#define USB1_PORTSC1_D_PEC_Msk (0x01UL << USB1_PORTSC1_D_PEC_Pos) /*!< USB1 PORTSC1_D: PEC Mask */ +#define USB1_PORTSC1_D_FPR_Pos 6 /*!< USB1 PORTSC1_D: FPR Position */ +#define USB1_PORTSC1_D_FPR_Msk (0x01UL << USB1_PORTSC1_D_FPR_Pos) /*!< USB1 PORTSC1_D: FPR Mask */ +#define USB1_PORTSC1_D_SUSP_Pos 7 /*!< USB1 PORTSC1_D: SUSP Position */ +#define USB1_PORTSC1_D_SUSP_Msk (0x01UL << USB1_PORTSC1_D_SUSP_Pos) /*!< USB1 PORTSC1_D: SUSP Mask */ +#define USB1_PORTSC1_D_PR_Pos 8 /*!< USB1 PORTSC1_D: PR Position */ +#define USB1_PORTSC1_D_PR_Msk (0x01UL << USB1_PORTSC1_D_PR_Pos) /*!< USB1 PORTSC1_D: PR Mask */ +#define USB1_PORTSC1_D_HSP_Pos 9 /*!< USB1 PORTSC1_D: HSP Position */ +#define USB1_PORTSC1_D_HSP_Msk (0x01UL << USB1_PORTSC1_D_HSP_Pos) /*!< USB1 PORTSC1_D: HSP Mask */ +#define USB1_PORTSC1_D_LS_Pos 10 /*!< USB1 PORTSC1_D: LS Position */ +#define USB1_PORTSC1_D_LS_Msk (0x03UL << USB1_PORTSC1_D_LS_Pos) /*!< USB1 PORTSC1_D: LS Mask */ +#define USB1_PORTSC1_D_PP_Pos 12 /*!< USB1 PORTSC1_D: PP Position */ +#define USB1_PORTSC1_D_PP_Msk (0x01UL << USB1_PORTSC1_D_PP_Pos) /*!< USB1 PORTSC1_D: PP Mask */ +#define USB1_PORTSC1_D_PIC1_0_Pos 14 /*!< USB1 PORTSC1_D: PIC1_0 Position */ +#define USB1_PORTSC1_D_PIC1_0_Msk (0x03UL << USB1_PORTSC1_D_PIC1_0_Pos) /*!< USB1 PORTSC1_D: PIC1_0 Mask */ +#define USB1_PORTSC1_D_PTC3_0_Pos 16 /*!< USB1 PORTSC1_D: PTC3_0 Position */ +#define USB1_PORTSC1_D_PTC3_0_Msk (0x0fUL << USB1_PORTSC1_D_PTC3_0_Pos) /*!< USB1 PORTSC1_D: PTC3_0 Mask */ +#define USB1_PORTSC1_D_PHCD_Pos 23 /*!< USB1 PORTSC1_D: PHCD Position */ +#define USB1_PORTSC1_D_PHCD_Msk (0x01UL << USB1_PORTSC1_D_PHCD_Pos) /*!< USB1 PORTSC1_D: PHCD Mask */ +#define USB1_PORTSC1_D_PFSC_Pos 24 /*!< USB1 PORTSC1_D: PFSC Position */ +#define USB1_PORTSC1_D_PFSC_Msk (0x01UL << USB1_PORTSC1_D_PFSC_Pos) /*!< USB1 PORTSC1_D: PFSC Mask */ +#define USB1_PORTSC1_D_PSPD_Pos 26 /*!< USB1 PORTSC1_D: PSPD Position */ +#define USB1_PORTSC1_D_PSPD_Msk (0x03UL << USB1_PORTSC1_D_PSPD_Pos) /*!< USB1 PORTSC1_D: PSPD Mask */ +#define USB1_PORTSC1_D_PTS_Pos 30 /*!< USB1 PORTSC1_D: PTS Position */ +#define USB1_PORTSC1_D_PTS_Msk (0x03UL << USB1_PORTSC1_D_PTS_Pos) /*!< USB1 PORTSC1_D: PTS Mask */ + +/* ------------------------------- USB1_PORTSC1_H ------------------------------- */ +#define USB1_PORTSC1_H_CCS_Pos 0 /*!< USB1 PORTSC1_H: CCS Position */ +#define USB1_PORTSC1_H_CCS_Msk (0x01UL << USB1_PORTSC1_H_CCS_Pos) /*!< USB1 PORTSC1_H: CCS Mask */ +#define USB1_PORTSC1_H_CSC_Pos 1 /*!< USB1 PORTSC1_H: CSC Position */ +#define USB1_PORTSC1_H_CSC_Msk (0x01UL << USB1_PORTSC1_H_CSC_Pos) /*!< USB1 PORTSC1_H: CSC Mask */ +#define USB1_PORTSC1_H_PE_Pos 2 /*!< USB1 PORTSC1_H: PE Position */ +#define USB1_PORTSC1_H_PE_Msk (0x01UL << USB1_PORTSC1_H_PE_Pos) /*!< USB1 PORTSC1_H: PE Mask */ +#define USB1_PORTSC1_H_PEC_Pos 3 /*!< USB1 PORTSC1_H: PEC Position */ +#define USB1_PORTSC1_H_PEC_Msk (0x01UL << USB1_PORTSC1_H_PEC_Pos) /*!< USB1 PORTSC1_H: PEC Mask */ +#define USB1_PORTSC1_H_OCA_Pos 4 /*!< USB1 PORTSC1_H: OCA Position */ +#define USB1_PORTSC1_H_OCA_Msk (0x01UL << USB1_PORTSC1_H_OCA_Pos) /*!< USB1 PORTSC1_H: OCA Mask */ +#define USB1_PORTSC1_H_OCC_Pos 5 /*!< USB1 PORTSC1_H: OCC Position */ +#define USB1_PORTSC1_H_OCC_Msk (0x01UL << USB1_PORTSC1_H_OCC_Pos) /*!< USB1 PORTSC1_H: OCC Mask */ +#define USB1_PORTSC1_H_FPR_Pos 6 /*!< USB1 PORTSC1_H: FPR Position */ +#define USB1_PORTSC1_H_FPR_Msk (0x01UL << USB1_PORTSC1_H_FPR_Pos) /*!< USB1 PORTSC1_H: FPR Mask */ +#define USB1_PORTSC1_H_SUSP_Pos 7 /*!< USB1 PORTSC1_H: SUSP Position */ +#define USB1_PORTSC1_H_SUSP_Msk (0x01UL << USB1_PORTSC1_H_SUSP_Pos) /*!< USB1 PORTSC1_H: SUSP Mask */ +#define USB1_PORTSC1_H_PR_Pos 8 /*!< USB1 PORTSC1_H: PR Position */ +#define USB1_PORTSC1_H_PR_Msk (0x01UL << USB1_PORTSC1_H_PR_Pos) /*!< USB1 PORTSC1_H: PR Mask */ +#define USB1_PORTSC1_H_HSP_Pos 9 /*!< USB1 PORTSC1_H: HSP Position */ +#define USB1_PORTSC1_H_HSP_Msk (0x01UL << USB1_PORTSC1_H_HSP_Pos) /*!< USB1 PORTSC1_H: HSP Mask */ +#define USB1_PORTSC1_H_LS_Pos 10 /*!< USB1 PORTSC1_H: LS Position */ +#define USB1_PORTSC1_H_LS_Msk (0x03UL << USB1_PORTSC1_H_LS_Pos) /*!< USB1 PORTSC1_H: LS Mask */ +#define USB1_PORTSC1_H_PP_Pos 12 /*!< USB1 PORTSC1_H: PP Position */ +#define USB1_PORTSC1_H_PP_Msk (0x01UL << USB1_PORTSC1_H_PP_Pos) /*!< USB1 PORTSC1_H: PP Mask */ +#define USB1_PORTSC1_H_PIC1_0_Pos 14 /*!< USB1 PORTSC1_H: PIC1_0 Position */ +#define USB1_PORTSC1_H_PIC1_0_Msk (0x03UL << USB1_PORTSC1_H_PIC1_0_Pos) /*!< USB1 PORTSC1_H: PIC1_0 Mask */ +#define USB1_PORTSC1_H_PTC3_0_Pos 16 /*!< USB1 PORTSC1_H: PTC3_0 Position */ +#define USB1_PORTSC1_H_PTC3_0_Msk (0x0fUL << USB1_PORTSC1_H_PTC3_0_Pos) /*!< USB1 PORTSC1_H: PTC3_0 Mask */ +#define USB1_PORTSC1_H_WKCN_Pos 20 /*!< USB1 PORTSC1_H: WKCN Position */ +#define USB1_PORTSC1_H_WKCN_Msk (0x01UL << USB1_PORTSC1_H_WKCN_Pos) /*!< USB1 PORTSC1_H: WKCN Mask */ +#define USB1_PORTSC1_H_WKDC_Pos 21 /*!< USB1 PORTSC1_H: WKDC Position */ +#define USB1_PORTSC1_H_WKDC_Msk (0x01UL << USB1_PORTSC1_H_WKDC_Pos) /*!< USB1 PORTSC1_H: WKDC Mask */ +#define USB1_PORTSC1_H_WKOC_Pos 22 /*!< USB1 PORTSC1_H: WKOC Position */ +#define USB1_PORTSC1_H_WKOC_Msk (0x01UL << USB1_PORTSC1_H_WKOC_Pos) /*!< USB1 PORTSC1_H: WKOC Mask */ +#define USB1_PORTSC1_H_PHCD_Pos 23 /*!< USB1 PORTSC1_H: PHCD Position */ +#define USB1_PORTSC1_H_PHCD_Msk (0x01UL << USB1_PORTSC1_H_PHCD_Pos) /*!< USB1 PORTSC1_H: PHCD Mask */ +#define USB1_PORTSC1_H_PFSC_Pos 24 /*!< USB1 PORTSC1_H: PFSC Position */ +#define USB1_PORTSC1_H_PFSC_Msk (0x01UL << USB1_PORTSC1_H_PFSC_Pos) /*!< USB1 PORTSC1_H: PFSC Mask */ +#define USB1_PORTSC1_H_PSPD_Pos 26 /*!< USB1 PORTSC1_H: PSPD Position */ +#define USB1_PORTSC1_H_PSPD_Msk (0x03UL << USB1_PORTSC1_H_PSPD_Pos) /*!< USB1 PORTSC1_H: PSPD Mask */ +#define USB1_PORTSC1_H_PTS_Pos 30 /*!< USB1 PORTSC1_H: PTS Position */ +#define USB1_PORTSC1_H_PTS_Msk (0x03UL << USB1_PORTSC1_H_PTS_Pos) /*!< USB1 PORTSC1_H: PTS Mask */ + +/* ------------------------------- USB1_USBMODE_D ------------------------------- */ +#define USB1_USBMODE_D_CM1_0_Pos 0 /*!< USB1 USBMODE_D: CM1_0 Position */ +#define USB1_USBMODE_D_CM1_0_Msk (0x03UL << USB1_USBMODE_D_CM1_0_Pos) /*!< USB1 USBMODE_D: CM1_0 Mask */ +#define USB1_USBMODE_D_ES_Pos 2 /*!< USB1 USBMODE_D: ES Position */ +#define USB1_USBMODE_D_ES_Msk (0x01UL << USB1_USBMODE_D_ES_Pos) /*!< USB1 USBMODE_D: ES Mask */ +#define USB1_USBMODE_D_SLOM_Pos 3 /*!< USB1 USBMODE_D: SLOM Position */ +#define USB1_USBMODE_D_SLOM_Msk (0x01UL << USB1_USBMODE_D_SLOM_Pos) /*!< USB1 USBMODE_D: SLOM Mask */ +#define USB1_USBMODE_D_SDIS_Pos 4 /*!< USB1 USBMODE_D: SDIS Position */ +#define USB1_USBMODE_D_SDIS_Msk (0x01UL << USB1_USBMODE_D_SDIS_Pos) /*!< USB1 USBMODE_D: SDIS Mask */ + +/* ------------------------------- USB1_USBMODE_H ------------------------------- */ +#define USB1_USBMODE_H_CM1_0_Pos 0 /*!< USB1 USBMODE_H: CM1_0 Position */ +#define USB1_USBMODE_H_CM1_0_Msk (0x03UL << USB1_USBMODE_H_CM1_0_Pos) /*!< USB1 USBMODE_H: CM1_0 Mask */ +#define USB1_USBMODE_H_ES_Pos 2 /*!< USB1 USBMODE_H: ES Position */ +#define USB1_USBMODE_H_ES_Msk (0x01UL << USB1_USBMODE_H_ES_Pos) /*!< USB1 USBMODE_H: ES Mask */ +#define USB1_USBMODE_H_SDIS_Pos 4 /*!< USB1 USBMODE_H: SDIS Position */ +#define USB1_USBMODE_H_SDIS_Msk (0x01UL << USB1_USBMODE_H_SDIS_Pos) /*!< USB1 USBMODE_H: SDIS Mask */ +#define USB1_USBMODE_H_VBPS_Pos 5 /*!< USB1 USBMODE_H: VBPS Position */ +#define USB1_USBMODE_H_VBPS_Msk (0x01UL << USB1_USBMODE_H_VBPS_Pos) /*!< USB1 USBMODE_H: VBPS Mask */ + +/* ----------------------------- USB1_ENDPTSETUPSTAT ---------------------------- */ +#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos 0 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */ +#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */ +#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos 1 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */ +#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */ +#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos 2 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */ +#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */ +#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos 3 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */ +#define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */ + +/* ------------------------------- USB1_ENDPTPRIME ------------------------------ */ +#define USB1_ENDPTPRIME_PERB0_Pos 0 /*!< USB1 ENDPTPRIME: PERB0 Position */ +#define USB1_ENDPTPRIME_PERB0_Msk (0x01UL << USB1_ENDPTPRIME_PERB0_Pos) /*!< USB1 ENDPTPRIME: PERB0 Mask */ +#define USB1_ENDPTPRIME_PERB1_Pos 1 /*!< USB1 ENDPTPRIME: PERB1 Position */ +#define USB1_ENDPTPRIME_PERB1_Msk (0x01UL << USB1_ENDPTPRIME_PERB1_Pos) /*!< USB1 ENDPTPRIME: PERB1 Mask */ +#define USB1_ENDPTPRIME_PERB2_Pos 2 /*!< USB1 ENDPTPRIME: PERB2 Position */ +#define USB1_ENDPTPRIME_PERB2_Msk (0x01UL << USB1_ENDPTPRIME_PERB2_Pos) /*!< USB1 ENDPTPRIME: PERB2 Mask */ +#define USB1_ENDPTPRIME_PERB3_Pos 3 /*!< USB1 ENDPTPRIME: PERB3 Position */ +#define USB1_ENDPTPRIME_PERB3_Msk (0x01UL << USB1_ENDPTPRIME_PERB3_Pos) /*!< USB1 ENDPTPRIME: PERB3 Mask */ +#define USB1_ENDPTPRIME_PETB0_Pos 16 /*!< USB1 ENDPTPRIME: PETB0 Position */ +#define USB1_ENDPTPRIME_PETB0_Msk (0x01UL << USB1_ENDPTPRIME_PETB0_Pos) /*!< USB1 ENDPTPRIME: PETB0 Mask */ +#define USB1_ENDPTPRIME_PETB1_Pos 17 /*!< USB1 ENDPTPRIME: PETB1 Position */ +#define USB1_ENDPTPRIME_PETB1_Msk (0x01UL << USB1_ENDPTPRIME_PETB1_Pos) /*!< USB1 ENDPTPRIME: PETB1 Mask */ +#define USB1_ENDPTPRIME_PETB2_Pos 18 /*!< USB1 ENDPTPRIME: PETB2 Position */ +#define USB1_ENDPTPRIME_PETB2_Msk (0x01UL << USB1_ENDPTPRIME_PETB2_Pos) /*!< USB1 ENDPTPRIME: PETB2 Mask */ +#define USB1_ENDPTPRIME_PETB3_Pos 19 /*!< USB1 ENDPTPRIME: PETB3 Position */ +#define USB1_ENDPTPRIME_PETB3_Msk (0x01UL << USB1_ENDPTPRIME_PETB3_Pos) /*!< USB1 ENDPTPRIME: PETB3 Mask */ + +/* ------------------------------- USB1_ENDPTFLUSH ------------------------------ */ +#define USB1_ENDPTFLUSH_FERB0_Pos 0 /*!< USB1 ENDPTFLUSH: FERB0 Position */ +#define USB1_ENDPTFLUSH_FERB0_Msk (0x01UL << USB1_ENDPTFLUSH_FERB0_Pos) /*!< USB1 ENDPTFLUSH: FERB0 Mask */ +#define USB1_ENDPTFLUSH_FERB1_Pos 1 /*!< USB1 ENDPTFLUSH: FERB1 Position */ +#define USB1_ENDPTFLUSH_FERB1_Msk (0x01UL << USB1_ENDPTFLUSH_FERB1_Pos) /*!< USB1 ENDPTFLUSH: FERB1 Mask */ +#define USB1_ENDPTFLUSH_FERB2_Pos 2 /*!< USB1 ENDPTFLUSH: FERB2 Position */ +#define USB1_ENDPTFLUSH_FERB2_Msk (0x01UL << USB1_ENDPTFLUSH_FERB2_Pos) /*!< USB1 ENDPTFLUSH: FERB2 Mask */ +#define USB1_ENDPTFLUSH_FERB3_Pos 3 /*!< USB1 ENDPTFLUSH: FERB3 Position */ +#define USB1_ENDPTFLUSH_FERB3_Msk (0x01UL << USB1_ENDPTFLUSH_FERB3_Pos) /*!< USB1 ENDPTFLUSH: FERB3 Mask */ +#define USB1_ENDPTFLUSH_FETB0_Pos 16 /*!< USB1 ENDPTFLUSH: FETB0 Position */ +#define USB1_ENDPTFLUSH_FETB0_Msk (0x01UL << USB1_ENDPTFLUSH_FETB0_Pos) /*!< USB1 ENDPTFLUSH: FETB0 Mask */ +#define USB1_ENDPTFLUSH_FETB1_Pos 17 /*!< USB1 ENDPTFLUSH: FETB1 Position */ +#define USB1_ENDPTFLUSH_FETB1_Msk (0x01UL << USB1_ENDPTFLUSH_FETB1_Pos) /*!< USB1 ENDPTFLUSH: FETB1 Mask */ +#define USB1_ENDPTFLUSH_FETB2_Pos 18 /*!< USB1 ENDPTFLUSH: FETB2 Position */ +#define USB1_ENDPTFLUSH_FETB2_Msk (0x01UL << USB1_ENDPTFLUSH_FETB2_Pos) /*!< USB1 ENDPTFLUSH: FETB2 Mask */ +#define USB1_ENDPTFLUSH_FETB3_Pos 19 /*!< USB1 ENDPTFLUSH: FETB3 Position */ +#define USB1_ENDPTFLUSH_FETB3_Msk (0x01UL << USB1_ENDPTFLUSH_FETB3_Pos) /*!< USB1 ENDPTFLUSH: FETB3 Mask */ + +/* ------------------------------- USB1_ENDPTSTAT ------------------------------- */ +#define USB1_ENDPTSTAT_ERBR0_Pos 0 /*!< USB1 ENDPTSTAT: ERBR0 Position */ +#define USB1_ENDPTSTAT_ERBR0_Msk (0x01UL << USB1_ENDPTSTAT_ERBR0_Pos) /*!< USB1 ENDPTSTAT: ERBR0 Mask */ +#define USB1_ENDPTSTAT_ERBR1_Pos 1 /*!< USB1 ENDPTSTAT: ERBR1 Position */ +#define USB1_ENDPTSTAT_ERBR1_Msk (0x01UL << USB1_ENDPTSTAT_ERBR1_Pos) /*!< USB1 ENDPTSTAT: ERBR1 Mask */ +#define USB1_ENDPTSTAT_ERBR2_Pos 2 /*!< USB1 ENDPTSTAT: ERBR2 Position */ +#define USB1_ENDPTSTAT_ERBR2_Msk (0x01UL << USB1_ENDPTSTAT_ERBR2_Pos) /*!< USB1 ENDPTSTAT: ERBR2 Mask */ +#define USB1_ENDPTSTAT_ERBR3_Pos 3 /*!< USB1 ENDPTSTAT: ERBR3 Position */ +#define USB1_ENDPTSTAT_ERBR3_Msk (0x01UL << USB1_ENDPTSTAT_ERBR3_Pos) /*!< USB1 ENDPTSTAT: ERBR3 Mask */ +#define USB1_ENDPTSTAT_ETBR0_Pos 16 /*!< USB1 ENDPTSTAT: ETBR0 Position */ +#define USB1_ENDPTSTAT_ETBR0_Msk (0x01UL << USB1_ENDPTSTAT_ETBR0_Pos) /*!< USB1 ENDPTSTAT: ETBR0 Mask */ +#define USB1_ENDPTSTAT_ETBR1_Pos 17 /*!< USB1 ENDPTSTAT: ETBR1 Position */ +#define USB1_ENDPTSTAT_ETBR1_Msk (0x01UL << USB1_ENDPTSTAT_ETBR1_Pos) /*!< USB1 ENDPTSTAT: ETBR1 Mask */ +#define USB1_ENDPTSTAT_ETBR2_Pos 18 /*!< USB1 ENDPTSTAT: ETBR2 Position */ +#define USB1_ENDPTSTAT_ETBR2_Msk (0x01UL << USB1_ENDPTSTAT_ETBR2_Pos) /*!< USB1 ENDPTSTAT: ETBR2 Mask */ +#define USB1_ENDPTSTAT_ETBR3_Pos 19 /*!< USB1 ENDPTSTAT: ETBR3 Position */ +#define USB1_ENDPTSTAT_ETBR3_Msk (0x01UL << USB1_ENDPTSTAT_ETBR3_Pos) /*!< USB1 ENDPTSTAT: ETBR3 Mask */ + +/* ----------------------------- USB1_ENDPTCOMPLETE ----------------------------- */ +#define USB1_ENDPTCOMPLETE_ERCE0_Pos 0 /*!< USB1 ENDPTCOMPLETE: ERCE0 Position */ +#define USB1_ENDPTCOMPLETE_ERCE0_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE0_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE0 Mask */ +#define USB1_ENDPTCOMPLETE_ERCE1_Pos 1 /*!< USB1 ENDPTCOMPLETE: ERCE1 Position */ +#define USB1_ENDPTCOMPLETE_ERCE1_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE1_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE1 Mask */ +#define USB1_ENDPTCOMPLETE_ERCE2_Pos 2 /*!< USB1 ENDPTCOMPLETE: ERCE2 Position */ +#define USB1_ENDPTCOMPLETE_ERCE2_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE2_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE2 Mask */ +#define USB1_ENDPTCOMPLETE_ERCE3_Pos 3 /*!< USB1 ENDPTCOMPLETE: ERCE3 Position */ +#define USB1_ENDPTCOMPLETE_ERCE3_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE3_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE3 Mask */ +#define USB1_ENDPTCOMPLETE_ETCE0_Pos 16 /*!< USB1 ENDPTCOMPLETE: ETCE0 Position */ +#define USB1_ENDPTCOMPLETE_ETCE0_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE0_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE0 Mask */ +#define USB1_ENDPTCOMPLETE_ETCE1_Pos 17 /*!< USB1 ENDPTCOMPLETE: ETCE1 Position */ +#define USB1_ENDPTCOMPLETE_ETCE1_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE1_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE1 Mask */ +#define USB1_ENDPTCOMPLETE_ETCE2_Pos 18 /*!< USB1 ENDPTCOMPLETE: ETCE2 Position */ +#define USB1_ENDPTCOMPLETE_ETCE2_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE2_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE2 Mask */ +#define USB1_ENDPTCOMPLETE_ETCE3_Pos 19 /*!< USB1 ENDPTCOMPLETE: ETCE3 Position */ +#define USB1_ENDPTCOMPLETE_ETCE3_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE3_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE3 Mask */ + +/* ------------------------------- USB1_ENDPTCTRL0 ------------------------------ */ +#define USB1_ENDPTCTRL0_RXS_Pos 0 /*!< USB1 ENDPTCTRL0: RXS Position */ +#define USB1_ENDPTCTRL0_RXS_Msk (0x01UL << USB1_ENDPTCTRL0_RXS_Pos) /*!< USB1 ENDPTCTRL0: RXS Mask */ +#define USB1_ENDPTCTRL0_RXT_Pos 2 /*!< USB1 ENDPTCTRL0: RXT Position */ +#define USB1_ENDPTCTRL0_RXT_Msk (0x03UL << USB1_ENDPTCTRL0_RXT_Pos) /*!< USB1 ENDPTCTRL0: RXT Mask */ +#define USB1_ENDPTCTRL0_RXE_Pos 7 /*!< USB1 ENDPTCTRL0: RXE Position */ +#define USB1_ENDPTCTRL0_RXE_Msk (0x01UL << USB1_ENDPTCTRL0_RXE_Pos) /*!< USB1 ENDPTCTRL0: RXE Mask */ +#define USB1_ENDPTCTRL0_TXS_Pos 16 /*!< USB1 ENDPTCTRL0: TXS Position */ +#define USB1_ENDPTCTRL0_TXS_Msk (0x01UL << USB1_ENDPTCTRL0_TXS_Pos) /*!< USB1 ENDPTCTRL0: TXS Mask */ +#define USB1_ENDPTCTRL0_TXT_Pos 18 /*!< USB1 ENDPTCTRL0: TXT Position */ +#define USB1_ENDPTCTRL0_TXT_Msk (0x03UL << USB1_ENDPTCTRL0_TXT_Pos) /*!< USB1 ENDPTCTRL0: TXT Mask */ +#define USB1_ENDPTCTRL0_TXE_Pos 23 /*!< USB1 ENDPTCTRL0: TXE Position */ +#define USB1_ENDPTCTRL0_TXE_Msk (0x01UL << USB1_ENDPTCTRL0_TXE_Pos) /*!< USB1 ENDPTCTRL0: TXE Mask */ + +/* ------------------------------- USB1_ENDPTCTRL1 ------------------------------ */ +#define USB1_ENDPTCTRL1_RXS_Pos 0 /*!< USB1 ENDPTCTRL1: RXS Position */ +#define USB1_ENDPTCTRL1_RXS_Msk (0x01UL << USB1_ENDPTCTRL1_RXS_Pos) /*!< USB1 ENDPTCTRL1: RXS Mask */ +#define USB1_ENDPTCTRL1_RXT_Pos 2 /*!< USB1 ENDPTCTRL1: RXT Position */ +#define USB1_ENDPTCTRL1_RXT_Msk (0x03UL << USB1_ENDPTCTRL1_RXT_Pos) /*!< USB1 ENDPTCTRL1: RXT Mask */ +#define USB1_ENDPTCTRL1_RXI_Pos 5 /*!< USB1 ENDPTCTRL1: RXI Position */ +#define USB1_ENDPTCTRL1_RXI_Msk (0x01UL << USB1_ENDPTCTRL1_RXI_Pos) /*!< USB1 ENDPTCTRL1: RXI Mask */ +#define USB1_ENDPTCTRL1_RXR_Pos 6 /*!< USB1 ENDPTCTRL1: RXR Position */ +#define USB1_ENDPTCTRL1_RXR_Msk (0x01UL << USB1_ENDPTCTRL1_RXR_Pos) /*!< USB1 ENDPTCTRL1: RXR Mask */ +#define USB1_ENDPTCTRL1_RXE_Pos 7 /*!< USB1 ENDPTCTRL1: RXE Position */ +#define USB1_ENDPTCTRL1_RXE_Msk (0x01UL << USB1_ENDPTCTRL1_RXE_Pos) /*!< USB1 ENDPTCTRL1: RXE Mask */ +#define USB1_ENDPTCTRL1_TXS_Pos 16 /*!< USB1 ENDPTCTRL1: TXS Position */ +#define USB1_ENDPTCTRL1_TXS_Msk (0x01UL << USB1_ENDPTCTRL1_TXS_Pos) /*!< USB1 ENDPTCTRL1: TXS Mask */ +#define USB1_ENDPTCTRL1_TXT_Pos 18 /*!< USB1 ENDPTCTRL1: TXT Position */ +#define USB1_ENDPTCTRL1_TXT_Msk (0x03UL << USB1_ENDPTCTRL1_TXT_Pos) /*!< USB1 ENDPTCTRL1: TXT Mask */ +#define USB1_ENDPTCTRL1_TXI_Pos 21 /*!< USB1 ENDPTCTRL1: TXI Position */ +#define USB1_ENDPTCTRL1_TXI_Msk (0x01UL << USB1_ENDPTCTRL1_TXI_Pos) /*!< USB1 ENDPTCTRL1: TXI Mask */ +#define USB1_ENDPTCTRL1_TXR_Pos 22 /*!< USB1 ENDPTCTRL1: TXR Position */ +#define USB1_ENDPTCTRL1_TXR_Msk (0x01UL << USB1_ENDPTCTRL1_TXR_Pos) /*!< USB1 ENDPTCTRL1: TXR Mask */ +#define USB1_ENDPTCTRL1_TXE_Pos 23 /*!< USB1 ENDPTCTRL1: TXE Position */ +#define USB1_ENDPTCTRL1_TXE_Msk (0x01UL << USB1_ENDPTCTRL1_TXE_Pos) /*!< USB1 ENDPTCTRL1: TXE Mask */ + +/* ------------------------------- USB1_ENDPTCTRL2 ------------------------------ */ +#define USB1_ENDPTCTRL2_RXS_Pos 0 /*!< USB1 ENDPTCTRL2: RXS Position */ +#define USB1_ENDPTCTRL2_RXS_Msk (0x01UL << USB1_ENDPTCTRL2_RXS_Pos) /*!< USB1 ENDPTCTRL2: RXS Mask */ +#define USB1_ENDPTCTRL2_RXT_Pos 2 /*!< USB1 ENDPTCTRL2: RXT Position */ +#define USB1_ENDPTCTRL2_RXT_Msk (0x03UL << USB1_ENDPTCTRL2_RXT_Pos) /*!< USB1 ENDPTCTRL2: RXT Mask */ +#define USB1_ENDPTCTRL2_RXI_Pos 5 /*!< USB1 ENDPTCTRL2: RXI Position */ +#define USB1_ENDPTCTRL2_RXI_Msk (0x01UL << USB1_ENDPTCTRL2_RXI_Pos) /*!< USB1 ENDPTCTRL2: RXI Mask */ +#define USB1_ENDPTCTRL2_RXR_Pos 6 /*!< USB1 ENDPTCTRL2: RXR Position */ +#define USB1_ENDPTCTRL2_RXR_Msk (0x01UL << USB1_ENDPTCTRL2_RXR_Pos) /*!< USB1 ENDPTCTRL2: RXR Mask */ +#define USB1_ENDPTCTRL2_RXE_Pos 7 /*!< USB1 ENDPTCTRL2: RXE Position */ +#define USB1_ENDPTCTRL2_RXE_Msk (0x01UL << USB1_ENDPTCTRL2_RXE_Pos) /*!< USB1 ENDPTCTRL2: RXE Mask */ +#define USB1_ENDPTCTRL2_TXS_Pos 16 /*!< USB1 ENDPTCTRL2: TXS Position */ +#define USB1_ENDPTCTRL2_TXS_Msk (0x01UL << USB1_ENDPTCTRL2_TXS_Pos) /*!< USB1 ENDPTCTRL2: TXS Mask */ +#define USB1_ENDPTCTRL2_TXT_Pos 18 /*!< USB1 ENDPTCTRL2: TXT Position */ +#define USB1_ENDPTCTRL2_TXT_Msk (0x03UL << USB1_ENDPTCTRL2_TXT_Pos) /*!< USB1 ENDPTCTRL2: TXT Mask */ +#define USB1_ENDPTCTRL2_TXI_Pos 21 /*!< USB1 ENDPTCTRL2: TXI Position */ +#define USB1_ENDPTCTRL2_TXI_Msk (0x01UL << USB1_ENDPTCTRL2_TXI_Pos) /*!< USB1 ENDPTCTRL2: TXI Mask */ +#define USB1_ENDPTCTRL2_TXR_Pos 22 /*!< USB1 ENDPTCTRL2: TXR Position */ +#define USB1_ENDPTCTRL2_TXR_Msk (0x01UL << USB1_ENDPTCTRL2_TXR_Pos) /*!< USB1 ENDPTCTRL2: TXR Mask */ +#define USB1_ENDPTCTRL2_TXE_Pos 23 /*!< USB1 ENDPTCTRL2: TXE Position */ +#define USB1_ENDPTCTRL2_TXE_Msk (0x01UL << USB1_ENDPTCTRL2_TXE_Pos) /*!< USB1 ENDPTCTRL2: TXE Mask */ + +/* ------------------------------- USB1_ENDPTCTRL3 ------------------------------ */ +#define USB1_ENDPTCTRL3_RXS_Pos 0 /*!< USB1 ENDPTCTRL3: RXS Position */ +#define USB1_ENDPTCTRL3_RXS_Msk (0x01UL << USB1_ENDPTCTRL3_RXS_Pos) /*!< USB1 ENDPTCTRL3: RXS Mask */ +#define USB1_ENDPTCTRL3_RXT_Pos 2 /*!< USB1 ENDPTCTRL3: RXT Position */ +#define USB1_ENDPTCTRL3_RXT_Msk (0x03UL << USB1_ENDPTCTRL3_RXT_Pos) /*!< USB1 ENDPTCTRL3: RXT Mask */ +#define USB1_ENDPTCTRL3_RXI_Pos 5 /*!< USB1 ENDPTCTRL3: RXI Position */ +#define USB1_ENDPTCTRL3_RXI_Msk (0x01UL << USB1_ENDPTCTRL3_RXI_Pos) /*!< USB1 ENDPTCTRL3: RXI Mask */ +#define USB1_ENDPTCTRL3_RXR_Pos 6 /*!< USB1 ENDPTCTRL3: RXR Position */ +#define USB1_ENDPTCTRL3_RXR_Msk (0x01UL << USB1_ENDPTCTRL3_RXR_Pos) /*!< USB1 ENDPTCTRL3: RXR Mask */ +#define USB1_ENDPTCTRL3_RXE_Pos 7 /*!< USB1 ENDPTCTRL3: RXE Position */ +#define USB1_ENDPTCTRL3_RXE_Msk (0x01UL << USB1_ENDPTCTRL3_RXE_Pos) /*!< USB1 ENDPTCTRL3: RXE Mask */ +#define USB1_ENDPTCTRL3_TXS_Pos 16 /*!< USB1 ENDPTCTRL3: TXS Position */ +#define USB1_ENDPTCTRL3_TXS_Msk (0x01UL << USB1_ENDPTCTRL3_TXS_Pos) /*!< USB1 ENDPTCTRL3: TXS Mask */ +#define USB1_ENDPTCTRL3_TXT_Pos 18 /*!< USB1 ENDPTCTRL3: TXT Position */ +#define USB1_ENDPTCTRL3_TXT_Msk (0x03UL << USB1_ENDPTCTRL3_TXT_Pos) /*!< USB1 ENDPTCTRL3: TXT Mask */ +#define USB1_ENDPTCTRL3_TXI_Pos 21 /*!< USB1 ENDPTCTRL3: TXI Position */ +#define USB1_ENDPTCTRL3_TXI_Msk (0x01UL << USB1_ENDPTCTRL3_TXI_Pos) /*!< USB1 ENDPTCTRL3: TXI Mask */ +#define USB1_ENDPTCTRL3_TXR_Pos 22 /*!< USB1 ENDPTCTRL3: TXR Position */ +#define USB1_ENDPTCTRL3_TXR_Msk (0x01UL << USB1_ENDPTCTRL3_TXR_Pos) /*!< USB1 ENDPTCTRL3: TXR Mask */ +#define USB1_ENDPTCTRL3_TXE_Pos 23 /*!< USB1 ENDPTCTRL3: TXE Position */ +#define USB1_ENDPTCTRL3_TXE_Msk (0x01UL << USB1_ENDPTCTRL3_TXE_Pos) /*!< USB1 ENDPTCTRL3: TXE Mask */ + + +/* ================================================================================ */ +/* ================ struct 'LCD' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- LCD_TIMH ---------------------------------- */ +#define LCD_TIMH_PPL_Pos 2 /*!< LCD TIMH: PPL Position */ +#define LCD_TIMH_PPL_Msk (0x3fUL << LCD_TIMH_PPL_Pos) /*!< LCD TIMH: PPL Mask */ +#define LCD_TIMH_HSW_Pos 8 /*!< LCD TIMH: HSW Position */ +#define LCD_TIMH_HSW_Msk (0x000000ffUL << LCD_TIMH_HSW_Pos) /*!< LCD TIMH: HSW Mask */ +#define LCD_TIMH_HFP_Pos 16 /*!< LCD TIMH: HFP Position */ +#define LCD_TIMH_HFP_Msk (0x000000ffUL << LCD_TIMH_HFP_Pos) /*!< LCD TIMH: HFP Mask */ +#define LCD_TIMH_HBP_Pos 24 /*!< LCD TIMH: HBP Position */ +#define LCD_TIMH_HBP_Msk (0x000000ffUL << LCD_TIMH_HBP_Pos) /*!< LCD TIMH: HBP Mask */ + +/* ---------------------------------- LCD_TIMV ---------------------------------- */ +#define LCD_TIMV_LPP_Pos 0 /*!< LCD TIMV: LPP Position */ +#define LCD_TIMV_LPP_Msk (0x000003ffUL << LCD_TIMV_LPP_Pos) /*!< LCD TIMV: LPP Mask */ +#define LCD_TIMV_VSW_Pos 10 /*!< LCD TIMV: VSW Position */ +#define LCD_TIMV_VSW_Msk (0x3fUL << LCD_TIMV_VSW_Pos) /*!< LCD TIMV: VSW Mask */ +#define LCD_TIMV_VFP_Pos 16 /*!< LCD TIMV: VFP Position */ +#define LCD_TIMV_VFP_Msk (0x000000ffUL << LCD_TIMV_VFP_Pos) /*!< LCD TIMV: VFP Mask */ +#define LCD_TIMV_VBP_Pos 24 /*!< LCD TIMV: VBP Position */ +#define LCD_TIMV_VBP_Msk (0x000000ffUL << LCD_TIMV_VBP_Pos) /*!< LCD TIMV: VBP Mask */ + +/* ----------------------------------- LCD_POL ---------------------------------- */ +#define LCD_POL_PCD_LO_Pos 0 /*!< LCD POL: PCD_LO Position */ +#define LCD_POL_PCD_LO_Msk (0x1fUL << LCD_POL_PCD_LO_Pos) /*!< LCD POL: PCD_LO Mask */ +#define LCD_POL_CLKSEL_Pos 5 /*!< LCD POL: CLKSEL Position */ +#define LCD_POL_CLKSEL_Msk (0x01UL << LCD_POL_CLKSEL_Pos) /*!< LCD POL: CLKSEL Mask */ +#define LCD_POL_ACB_Pos 6 /*!< LCD POL: ACB Position */ +#define LCD_POL_ACB_Msk (0x1fUL << LCD_POL_ACB_Pos) /*!< LCD POL: ACB Mask */ +#define LCD_POL_IVS_Pos 11 /*!< LCD POL: IVS Position */ +#define LCD_POL_IVS_Msk (0x01UL << LCD_POL_IVS_Pos) /*!< LCD POL: IVS Mask */ +#define LCD_POL_IHS_Pos 12 /*!< LCD POL: IHS Position */ +#define LCD_POL_IHS_Msk (0x01UL << LCD_POL_IHS_Pos) /*!< LCD POL: IHS Mask */ +#define LCD_POL_IPC_Pos 13 /*!< LCD POL: IPC Position */ +#define LCD_POL_IPC_Msk (0x01UL << LCD_POL_IPC_Pos) /*!< LCD POL: IPC Mask */ +#define LCD_POL_IOE_Pos 14 /*!< LCD POL: IOE Position */ +#define LCD_POL_IOE_Msk (0x01UL << LCD_POL_IOE_Pos) /*!< LCD POL: IOE Mask */ +#define LCD_POL_CPL_Pos 16 /*!< LCD POL: CPL Position */ +#define LCD_POL_CPL_Msk (0x000003ffUL << LCD_POL_CPL_Pos) /*!< LCD POL: CPL Mask */ +#define LCD_POL_BCD_Pos 26 /*!< LCD POL: BCD Position */ +#define LCD_POL_BCD_Msk (0x01UL << LCD_POL_BCD_Pos) /*!< LCD POL: BCD Mask */ +#define LCD_POL_PCD_HI_Pos 27 /*!< LCD POL: PCD_HI Position */ +#define LCD_POL_PCD_HI_Msk (0x1fUL << LCD_POL_PCD_HI_Pos) /*!< LCD POL: PCD_HI Mask */ + +/* ----------------------------------- LCD_LE ----------------------------------- */ +#define LCD_LE_LED_Pos 0 /*!< LCD LE: LED Position */ +#define LCD_LE_LED_Msk (0x7fUL << LCD_LE_LED_Pos) /*!< LCD LE: LED Mask */ +#define LCD_LE_LEE_Pos 16 /*!< LCD LE: LEE Position */ +#define LCD_LE_LEE_Msk (0x01UL << LCD_LE_LEE_Pos) /*!< LCD LE: LEE Mask */ + +/* --------------------------------- LCD_UPBASE --------------------------------- */ +#define LCD_UPBASE_LCDUPBASE_Pos 3 /*!< LCD UPBASE: LCDUPBASE Position */ +#define LCD_UPBASE_LCDUPBASE_Msk (0x1fffffffUL << LCD_UPBASE_LCDUPBASE_Pos) /*!< LCD UPBASE: LCDUPBASE Mask */ + +/* --------------------------------- LCD_LPBASE --------------------------------- */ +#define LCD_LPBASE_LCDLPBASE_Pos 3 /*!< LCD LPBASE: LCDLPBASE Position */ +#define LCD_LPBASE_LCDLPBASE_Msk (0x1fffffffUL << LCD_LPBASE_LCDLPBASE_Pos) /*!< LCD LPBASE: LCDLPBASE Mask */ + +/* ---------------------------------- LCD_CTRL ---------------------------------- */ +#define LCD_CTRL_LCDEN_Pos 0 /*!< LCD CTRL: LCDEN Position */ +#define LCD_CTRL_LCDEN_Msk (0x01UL << LCD_CTRL_LCDEN_Pos) /*!< LCD CTRL: LCDEN Mask */ +#define LCD_CTRL_LCDBPP_Pos 1 /*!< LCD CTRL: LCDBPP Position */ +#define LCD_CTRL_LCDBPP_Msk (0x07UL << LCD_CTRL_LCDBPP_Pos) /*!< LCD CTRL: LCDBPP Mask */ +#define LCD_CTRL_LCDBW_Pos 4 /*!< LCD CTRL: LCDBW Position */ +#define LCD_CTRL_LCDBW_Msk (0x01UL << LCD_CTRL_LCDBW_Pos) /*!< LCD CTRL: LCDBW Mask */ +#define LCD_CTRL_LCDTFT_Pos 5 /*!< LCD CTRL: LCDTFT Position */ +#define LCD_CTRL_LCDTFT_Msk (0x01UL << LCD_CTRL_LCDTFT_Pos) /*!< LCD CTRL: LCDTFT Mask */ +#define LCD_CTRL_LCDMONO8_Pos 6 /*!< LCD CTRL: LCDMONO8 Position */ +#define LCD_CTRL_LCDMONO8_Msk (0x01UL << LCD_CTRL_LCDMONO8_Pos) /*!< LCD CTRL: LCDMONO8 Mask */ +#define LCD_CTRL_LCDDUAL_Pos 7 /*!< LCD CTRL: LCDDUAL Position */ +#define LCD_CTRL_LCDDUAL_Msk (0x01UL << LCD_CTRL_LCDDUAL_Pos) /*!< LCD CTRL: LCDDUAL Mask */ +#define LCD_CTRL_BGR_Pos 8 /*!< LCD CTRL: BGR Position */ +#define LCD_CTRL_BGR_Msk (0x01UL << LCD_CTRL_BGR_Pos) /*!< LCD CTRL: BGR Mask */ +#define LCD_CTRL_BEBO_Pos 9 /*!< LCD CTRL: BEBO Position */ +#define LCD_CTRL_BEBO_Msk (0x01UL << LCD_CTRL_BEBO_Pos) /*!< LCD CTRL: BEBO Mask */ +#define LCD_CTRL_BEPO_Pos 10 /*!< LCD CTRL: BEPO Position */ +#define LCD_CTRL_BEPO_Msk (0x01UL << LCD_CTRL_BEPO_Pos) /*!< LCD CTRL: BEPO Mask */ +#define LCD_CTRL_LCDPWR_Pos 11 /*!< LCD CTRL: LCDPWR Position */ +#define LCD_CTRL_LCDPWR_Msk (0x01UL << LCD_CTRL_LCDPWR_Pos) /*!< LCD CTRL: LCDPWR Mask */ +#define LCD_CTRL_LCDVCOMP_Pos 12 /*!< LCD CTRL: LCDVCOMP Position */ +#define LCD_CTRL_LCDVCOMP_Msk (0x03UL << LCD_CTRL_LCDVCOMP_Pos) /*!< LCD CTRL: LCDVCOMP Mask */ +#define LCD_CTRL_WATERMARK_Pos 16 /*!< LCD CTRL: WATERMARK Position */ +#define LCD_CTRL_WATERMARK_Msk (0x01UL << LCD_CTRL_WATERMARK_Pos) /*!< LCD CTRL: WATERMARK Mask */ + +/* --------------------------------- LCD_INTMSK --------------------------------- */ +#define LCD_INTMSK_FUFIM_Pos 1 /*!< LCD INTMSK: FUFIM Position */ +#define LCD_INTMSK_FUFIM_Msk (0x01UL << LCD_INTMSK_FUFIM_Pos) /*!< LCD INTMSK: FUFIM Mask */ +#define LCD_INTMSK_LNBUIM_Pos 2 /*!< LCD INTMSK: LNBUIM Position */ +#define LCD_INTMSK_LNBUIM_Msk (0x01UL << LCD_INTMSK_LNBUIM_Pos) /*!< LCD INTMSK: LNBUIM Mask */ +#define LCD_INTMSK_VCOMPIM_Pos 3 /*!< LCD INTMSK: VCOMPIM Position */ +#define LCD_INTMSK_VCOMPIM_Msk (0x01UL << LCD_INTMSK_VCOMPIM_Pos) /*!< LCD INTMSK: VCOMPIM Mask */ +#define LCD_INTMSK_BERIM_Pos 4 /*!< LCD INTMSK: BERIM Position */ +#define LCD_INTMSK_BERIM_Msk (0x01UL << LCD_INTMSK_BERIM_Pos) /*!< LCD INTMSK: BERIM Mask */ + +/* --------------------------------- LCD_INTRAW --------------------------------- */ +#define LCD_INTRAW_FUFRIS_Pos 1 /*!< LCD INTRAW: FUFRIS Position */ +#define LCD_INTRAW_FUFRIS_Msk (0x01UL << LCD_INTRAW_FUFRIS_Pos) /*!< LCD INTRAW: FUFRIS Mask */ +#define LCD_INTRAW_LNBURIS_Pos 2 /*!< LCD INTRAW: LNBURIS Position */ +#define LCD_INTRAW_LNBURIS_Msk (0x01UL << LCD_INTRAW_LNBURIS_Pos) /*!< LCD INTRAW: LNBURIS Mask */ +#define LCD_INTRAW_VCOMPRIS_Pos 3 /*!< LCD INTRAW: VCOMPRIS Position */ +#define LCD_INTRAW_VCOMPRIS_Msk (0x01UL << LCD_INTRAW_VCOMPRIS_Pos) /*!< LCD INTRAW: VCOMPRIS Mask */ +#define LCD_INTRAW_BERRAW_Pos 4 /*!< LCD INTRAW: BERRAW Position */ +#define LCD_INTRAW_BERRAW_Msk (0x01UL << LCD_INTRAW_BERRAW_Pos) /*!< LCD INTRAW: BERRAW Mask */ + +/* --------------------------------- LCD_INTSTAT -------------------------------- */ +#define LCD_INTSTAT_FUFMIS_Pos 1 /*!< LCD INTSTAT: FUFMIS Position */ +#define LCD_INTSTAT_FUFMIS_Msk (0x01UL << LCD_INTSTAT_FUFMIS_Pos) /*!< LCD INTSTAT: FUFMIS Mask */ +#define LCD_INTSTAT_LNBUMIS_Pos 2 /*!< LCD INTSTAT: LNBUMIS Position */ +#define LCD_INTSTAT_LNBUMIS_Msk (0x01UL << LCD_INTSTAT_LNBUMIS_Pos) /*!< LCD INTSTAT: LNBUMIS Mask */ +#define LCD_INTSTAT_VCOMPMIS_Pos 3 /*!< LCD INTSTAT: VCOMPMIS Position */ +#define LCD_INTSTAT_VCOMPMIS_Msk (0x01UL << LCD_INTSTAT_VCOMPMIS_Pos) /*!< LCD INTSTAT: VCOMPMIS Mask */ +#define LCD_INTSTAT_BERMIS_Pos 4 /*!< LCD INTSTAT: BERMIS Position */ +#define LCD_INTSTAT_BERMIS_Msk (0x01UL << LCD_INTSTAT_BERMIS_Pos) /*!< LCD INTSTAT: BERMIS Mask */ + +/* --------------------------------- LCD_INTCLR --------------------------------- */ +#define LCD_INTCLR_FUFIC_Pos 1 /*!< LCD INTCLR: FUFIC Position */ +#define LCD_INTCLR_FUFIC_Msk (0x01UL << LCD_INTCLR_FUFIC_Pos) /*!< LCD INTCLR: FUFIC Mask */ +#define LCD_INTCLR_LNBUIC_Pos 2 /*!< LCD INTCLR: LNBUIC Position */ +#define LCD_INTCLR_LNBUIC_Msk (0x01UL << LCD_INTCLR_LNBUIC_Pos) /*!< LCD INTCLR: LNBUIC Mask */ +#define LCD_INTCLR_VCOMPIC_Pos 3 /*!< LCD INTCLR: VCOMPIC Position */ +#define LCD_INTCLR_VCOMPIC_Msk (0x01UL << LCD_INTCLR_VCOMPIC_Pos) /*!< LCD INTCLR: VCOMPIC Mask */ +#define LCD_INTCLR_BERIC_Pos 4 /*!< LCD INTCLR: BERIC Position */ +#define LCD_INTCLR_BERIC_Msk (0x01UL << LCD_INTCLR_BERIC_Pos) /*!< LCD INTCLR: BERIC Mask */ + +/* --------------------------------- LCD_UPCURR --------------------------------- */ +#define LCD_UPCURR_LCDUPCURR_Pos 0 /*!< LCD UPCURR: LCDUPCURR Position */ +#define LCD_UPCURR_LCDUPCURR_Msk (0xffffffffUL << LCD_UPCURR_LCDUPCURR_Pos) /*!< LCD UPCURR: LCDUPCURR Mask */ + +/* --------------------------------- LCD_LPCURR --------------------------------- */ +#define LCD_LPCURR_LCDLPCURR_Pos 0 /*!< LCD LPCURR: LCDLPCURR Position */ +#define LCD_LPCURR_LCDLPCURR_Msk (0xffffffffUL << LCD_LPCURR_LCDLPCURR_Pos) /*!< LCD LPCURR: LCDLPCURR Mask */ + +/* ----------------------------------- LCD_PAL ---------------------------------- */ +#define LCD_PAL_R04_0_Pos 0 /*!< LCD PAL: R04_0 Position */ +#define LCD_PAL_R04_0_Msk (0x1fUL << LCD_PAL_R04_0_Pos) /*!< LCD PAL: R04_0 Mask */ +#define LCD_PAL_G04_0_Pos 5 /*!< LCD PAL: G04_0 Position */ +#define LCD_PAL_G04_0_Msk (0x1fUL << LCD_PAL_G04_0_Pos) /*!< LCD PAL: G04_0 Mask */ +#define LCD_PAL_B04_0_Pos 10 /*!< LCD PAL: B04_0 Position */ +#define LCD_PAL_B04_0_Msk (0x1fUL << LCD_PAL_B04_0_Pos) /*!< LCD PAL: B04_0 Mask */ +#define LCD_PAL_I0_Pos 15 /*!< LCD PAL: I0 Position */ +#define LCD_PAL_I0_Msk (0x01UL << LCD_PAL_I0_Pos) /*!< LCD PAL: I0 Mask */ +#define LCD_PAL_R14_0_Pos 16 /*!< LCD PAL: R14_0 Position */ +#define LCD_PAL_R14_0_Msk (0x1fUL << LCD_PAL_R14_0_Pos) /*!< LCD PAL: R14_0 Mask */ +#define LCD_PAL_G14_0_Pos 21 /*!< LCD PAL: G14_0 Position */ +#define LCD_PAL_G14_0_Msk (0x1fUL << LCD_PAL_G14_0_Pos) /*!< LCD PAL: G14_0 Mask */ +#define LCD_PAL_B14_0_Pos 26 /*!< LCD PAL: B14_0 Position */ +#define LCD_PAL_B14_0_Msk (0x1fUL << LCD_PAL_B14_0_Pos) /*!< LCD PAL: B14_0 Mask */ +#define LCD_PAL_I1_Pos 31 /*!< LCD PAL: I1 Position */ +#define LCD_PAL_I1_Msk (0x01UL << LCD_PAL_I1_Pos) /*!< LCD PAL: I1 Mask */ + +/* -------------------------------- LCD_CRSR_IMG -------------------------------- */ +#define LCD_CRSR_IMG_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG: CRSR_IMG Position */ +#define LCD_CRSR_IMG_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG_CRSR_IMG_Pos) /*!< LCD CRSR_IMG: CRSR_IMG Mask */ + +/* -------------------------------- LCD_CRSR_CTRL ------------------------------- */ +#define LCD_CRSR_CTRL_CrsrOn_Pos 0 /*!< LCD CRSR_CTRL: CrsrOn Position */ +#define LCD_CRSR_CTRL_CrsrOn_Msk (0x01UL << LCD_CRSR_CTRL_CrsrOn_Pos) /*!< LCD CRSR_CTRL: CrsrOn Mask */ +#define LCD_CRSR_CTRL_CRSRNUM1_0_Pos 4 /*!< LCD CRSR_CTRL: CRSRNUM1_0 Position */ +#define LCD_CRSR_CTRL_CRSRNUM1_0_Msk (0x03UL << LCD_CRSR_CTRL_CRSRNUM1_0_Pos) /*!< LCD CRSR_CTRL: CRSRNUM1_0 Mask */ + +/* -------------------------------- LCD_CRSR_CFG -------------------------------- */ +#define LCD_CRSR_CFG_CrsrSize_Pos 0 /*!< LCD CRSR_CFG: CrsrSize Position */ +#define LCD_CRSR_CFG_CrsrSize_Msk (0x01UL << LCD_CRSR_CFG_CrsrSize_Pos) /*!< LCD CRSR_CFG: CrsrSize Mask */ +#define LCD_CRSR_CFG_FRAMESYNC_Pos 1 /*!< LCD CRSR_CFG: FRAMESYNC Position */ +#define LCD_CRSR_CFG_FRAMESYNC_Msk (0x01UL << LCD_CRSR_CFG_FRAMESYNC_Pos) /*!< LCD CRSR_CFG: FRAMESYNC Mask */ + +/* -------------------------------- LCD_CRSR_PAL0 ------------------------------- */ +#define LCD_CRSR_PAL0_RED_Pos 0 /*!< LCD CRSR_PAL0: RED Position */ +#define LCD_CRSR_PAL0_RED_Msk (0x000000ffUL << LCD_CRSR_PAL0_RED_Pos) /*!< LCD CRSR_PAL0: RED Mask */ +#define LCD_CRSR_PAL0_GREEN_Pos 8 /*!< LCD CRSR_PAL0: GREEN Position */ +#define LCD_CRSR_PAL0_GREEN_Msk (0x000000ffUL << LCD_CRSR_PAL0_GREEN_Pos) /*!< LCD CRSR_PAL0: GREEN Mask */ +#define LCD_CRSR_PAL0_BLUE_Pos 16 /*!< LCD CRSR_PAL0: BLUE Position */ +#define LCD_CRSR_PAL0_BLUE_Msk (0x000000ffUL << LCD_CRSR_PAL0_BLUE_Pos) /*!< LCD CRSR_PAL0: BLUE Mask */ + +/* -------------------------------- LCD_CRSR_PAL1 ------------------------------- */ +#define LCD_CRSR_PAL1_RED_Pos 0 /*!< LCD CRSR_PAL1: RED Position */ +#define LCD_CRSR_PAL1_RED_Msk (0x000000ffUL << LCD_CRSR_PAL1_RED_Pos) /*!< LCD CRSR_PAL1: RED Mask */ +#define LCD_CRSR_PAL1_GREEN_Pos 8 /*!< LCD CRSR_PAL1: GREEN Position */ +#define LCD_CRSR_PAL1_GREEN_Msk (0x000000ffUL << LCD_CRSR_PAL1_GREEN_Pos) /*!< LCD CRSR_PAL1: GREEN Mask */ +#define LCD_CRSR_PAL1_BLUE_Pos 16 /*!< LCD CRSR_PAL1: BLUE Position */ +#define LCD_CRSR_PAL1_BLUE_Msk (0x000000ffUL << LCD_CRSR_PAL1_BLUE_Pos) /*!< LCD CRSR_PAL1: BLUE Mask */ + +/* --------------------------------- LCD_CRSR_XY -------------------------------- */ +#define LCD_CRSR_XY_CRSRX_Pos 0 /*!< LCD CRSR_XY: CRSRX Position */ +#define LCD_CRSR_XY_CRSRX_Msk (0x000003ffUL << LCD_CRSR_XY_CRSRX_Pos) /*!< LCD CRSR_XY: CRSRX Mask */ +#define LCD_CRSR_XY_CRSRY_Pos 16 /*!< LCD CRSR_XY: CRSRY Position */ +#define LCD_CRSR_XY_CRSRY_Msk (0x000003ffUL << LCD_CRSR_XY_CRSRY_Pos) /*!< LCD CRSR_XY: CRSRY Mask */ + +/* -------------------------------- LCD_CRSR_CLIP ------------------------------- */ +#define LCD_CRSR_CLIP_CRSRCLIPX_Pos 0 /*!< LCD CRSR_CLIP: CRSRCLIPX Position */ +#define LCD_CRSR_CLIP_CRSRCLIPX_Msk (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPX_Pos) /*!< LCD CRSR_CLIP: CRSRCLIPX Mask */ +#define LCD_CRSR_CLIP_CRSRCLIPY_Pos 8 /*!< LCD CRSR_CLIP: CRSRCLIPY Position */ +#define LCD_CRSR_CLIP_CRSRCLIPY_Msk (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPY_Pos) /*!< LCD CRSR_CLIP: CRSRCLIPY Mask */ + +/* ------------------------------- LCD_CRSR_INTMSK ------------------------------ */ +#define LCD_CRSR_INTMSK_CRSRIM_Pos 0 /*!< LCD CRSR_INTMSK: CRSRIM Position */ +#define LCD_CRSR_INTMSK_CRSRIM_Msk (0x01UL << LCD_CRSR_INTMSK_CRSRIM_Pos) /*!< LCD CRSR_INTMSK: CRSRIM Mask */ + +/* ------------------------------- LCD_CRSR_INTCLR ------------------------------ */ +#define LCD_CRSR_INTCLR_CRSRIC_Pos 0 /*!< LCD CRSR_INTCLR: CRSRIC Position */ +#define LCD_CRSR_INTCLR_CRSRIC_Msk (0x01UL << LCD_CRSR_INTCLR_CRSRIC_Pos) /*!< LCD CRSR_INTCLR: CRSRIC Mask */ + +/* ------------------------------- LCD_CRSR_INTRAW ------------------------------ */ +#define LCD_CRSR_INTRAW_CRSRRIS_Pos 0 /*!< LCD CRSR_INTRAW: CRSRRIS Position */ +#define LCD_CRSR_INTRAW_CRSRRIS_Msk (0x01UL << LCD_CRSR_INTRAW_CRSRRIS_Pos) /*!< LCD CRSR_INTRAW: CRSRRIS Mask */ + +/* ------------------------------ LCD_CRSR_INTSTAT ------------------------------ */ +#define LCD_CRSR_INTSTAT_CRSRMIS_Pos 0 /*!< LCD CRSR_INTSTAT: CRSRMIS Position */ +#define LCD_CRSR_INTSTAT_CRSRMIS_Msk (0x01UL << LCD_CRSR_INTSTAT_CRSRMIS_Pos) /*!< LCD CRSR_INTSTAT: CRSRMIS Mask */ + + +/* ================================================================================ */ +/* ================ struct 'EEPROM' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- EEPROM_CMD --------------------------------- */ +#define EEPROM_CMD_CMD_Pos 0 /*!< EEPROM CMD: CMD Position */ +#define EEPROM_CMD_CMD_Msk (0x07UL << EEPROM_CMD_CMD_Pos) /*!< EEPROM CMD: CMD Mask */ + +/* ------------------------------- EEPROM_RWSTATE ------------------------------- */ +#define EEPROM_RWSTATE_RPHASE2_Pos 0 /*!< EEPROM RWSTATE: RPHASE2 Position */ +#define EEPROM_RWSTATE_RPHASE2_Msk (0x000000ffUL << EEPROM_RWSTATE_RPHASE2_Pos) /*!< EEPROM RWSTATE: RPHASE2 Mask */ +#define EEPROM_RWSTATE_RPHASE1_Pos 8 /*!< EEPROM RWSTATE: RPHASE1 Position */ +#define EEPROM_RWSTATE_RPHASE1_Msk (0x000000ffUL << EEPROM_RWSTATE_RPHASE1_Pos) /*!< EEPROM RWSTATE: RPHASE1 Mask */ + +/* ------------------------------- EEPROM_AUTOPROG ------------------------------ */ +#define EEPROM_AUTOPROG_AUTOPROG_Pos 0 /*!< EEPROM AUTOPROG: AUTOPROG Position */ +#define EEPROM_AUTOPROG_AUTOPROG_Msk (0x03UL << EEPROM_AUTOPROG_AUTOPROG_Pos) /*!< EEPROM AUTOPROG: AUTOPROG Mask */ + +/* -------------------------------- EEPROM_WSTATE ------------------------------- */ +#define EEPROM_WSTATE_PHASE3_Pos 0 /*!< EEPROM WSTATE: PHASE3 Position */ +#define EEPROM_WSTATE_PHASE3_Msk (0x000000ffUL << EEPROM_WSTATE_PHASE3_Pos) /*!< EEPROM WSTATE: PHASE3 Mask */ +#define EEPROM_WSTATE_PHASE2_Pos 8 /*!< EEPROM WSTATE: PHASE2 Position */ +#define EEPROM_WSTATE_PHASE2_Msk (0x000000ffUL << EEPROM_WSTATE_PHASE2_Pos) /*!< EEPROM WSTATE: PHASE2 Mask */ +#define EEPROM_WSTATE_PHASE1_Pos 16 /*!< EEPROM WSTATE: PHASE1 Position */ +#define EEPROM_WSTATE_PHASE1_Msk (0x000000ffUL << EEPROM_WSTATE_PHASE1_Pos) /*!< EEPROM WSTATE: PHASE1 Mask */ +#define EEPROM_WSTATE_LCK_PARWEP_Pos 31 /*!< EEPROM WSTATE: LCK_PARWEP Position */ +#define EEPROM_WSTATE_LCK_PARWEP_Msk (0x01UL << EEPROM_WSTATE_LCK_PARWEP_Pos) /*!< EEPROM WSTATE: LCK_PARWEP Mask */ + +/* -------------------------------- EEPROM_CLKDIV ------------------------------- */ +#define EEPROM_CLKDIV_CLKDIV_Pos 0 /*!< EEPROM CLKDIV: CLKDIV Position */ +#define EEPROM_CLKDIV_CLKDIV_Msk (0x0000ffffUL << EEPROM_CLKDIV_CLKDIV_Pos) /*!< EEPROM CLKDIV: CLKDIV Mask */ + +/* -------------------------------- EEPROM_PWRDWN ------------------------------- */ +#define EEPROM_PWRDWN_PWRDWN_Pos 0 /*!< EEPROM PWRDWN: PWRDWN Position */ +#define EEPROM_PWRDWN_PWRDWN_Msk (0x01UL << EEPROM_PWRDWN_PWRDWN_Pos) /*!< EEPROM PWRDWN: PWRDWN Mask */ + +/* ------------------------------- EEPROM_INTENCLR ------------------------------ */ +#define EEPROM_INTENCLR_PROG_CLR_EN_Pos 2 /*!< EEPROM INTENCLR: PROG_CLR_EN Position */ +#define EEPROM_INTENCLR_PROG_CLR_EN_Msk (0x01UL << EEPROM_INTENCLR_PROG_CLR_EN_Pos) /*!< EEPROM INTENCLR: PROG_CLR_EN Mask */ + +/* ------------------------------- EEPROM_INTENSET ------------------------------ */ +#define EEPROM_INTENSET_PROG_SET_EN_Pos 2 /*!< EEPROM INTENSET: PROG_SET_EN Position */ +#define EEPROM_INTENSET_PROG_SET_EN_Msk (0x01UL << EEPROM_INTENSET_PROG_SET_EN_Pos) /*!< EEPROM INTENSET: PROG_SET_EN Mask */ + +/* ------------------------------- EEPROM_INTSTAT ------------------------------- */ +#define EEPROM_INTSTAT_END_OF_PROG_Pos 2 /*!< EEPROM INTSTAT: END_OF_PROG Position */ +#define EEPROM_INTSTAT_END_OF_PROG_Msk (0x01UL << EEPROM_INTSTAT_END_OF_PROG_Pos) /*!< EEPROM INTSTAT: END_OF_PROG Mask */ + +/* -------------------------------- EEPROM_INTEN -------------------------------- */ +#define EEPROM_INTEN_EE_PROG_DONE_Pos 2 /*!< EEPROM INTEN: EE_PROG_DONE Position */ +#define EEPROM_INTEN_EE_PROG_DONE_Msk (0x01UL << EEPROM_INTEN_EE_PROG_DONE_Pos) /*!< EEPROM INTEN: EE_PROG_DONE Mask */ + +/* ------------------------------ EEPROM_INTSTATCLR ----------------------------- */ +#define EEPROM_INTSTATCLR_PROG_CLR_ST_Pos 2 /*!< EEPROM INTSTATCLR: PROG_CLR_ST Position */ +#define EEPROM_INTSTATCLR_PROG_CLR_ST_Msk (0x01UL << EEPROM_INTSTATCLR_PROG_CLR_ST_Pos) /*!< EEPROM INTSTATCLR: PROG_CLR_ST Mask */ + + +/* ================================================================================ */ +/* ================ struct 'ETHERNET' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------- ETHERNET_MAC_CONFIG ---------------------------- */ +#define ETHERNET_MAC_CONFIG_RE_Pos 2 /*!< ETHERNET MAC_CONFIG: RE Position */ +#define ETHERNET_MAC_CONFIG_RE_Msk (0x01UL << ETHERNET_MAC_CONFIG_RE_Pos) /*!< ETHERNET MAC_CONFIG: RE Mask */ +#define ETHERNET_MAC_CONFIG_TE_Pos 3 /*!< ETHERNET MAC_CONFIG: TE Position */ +#define ETHERNET_MAC_CONFIG_TE_Msk (0x01UL << ETHERNET_MAC_CONFIG_TE_Pos) /*!< ETHERNET MAC_CONFIG: TE Mask */ +#define ETHERNET_MAC_CONFIG_DF_Pos 4 /*!< ETHERNET MAC_CONFIG: DF Position */ +#define ETHERNET_MAC_CONFIG_DF_Msk (0x01UL << ETHERNET_MAC_CONFIG_DF_Pos) /*!< ETHERNET MAC_CONFIG: DF Mask */ +#define ETHERNET_MAC_CONFIG_BL_Pos 5 /*!< ETHERNET MAC_CONFIG: BL Position */ +#define ETHERNET_MAC_CONFIG_BL_Msk (0x03UL << ETHERNET_MAC_CONFIG_BL_Pos) /*!< ETHERNET MAC_CONFIG: BL Mask */ +#define ETHERNET_MAC_CONFIG_ACS_Pos 7 /*!< ETHERNET MAC_CONFIG: ACS Position */ +#define ETHERNET_MAC_CONFIG_ACS_Msk (0x01UL << ETHERNET_MAC_CONFIG_ACS_Pos) /*!< ETHERNET MAC_CONFIG: ACS Mask */ +#define ETHERNET_MAC_CONFIG_DR_Pos 9 /*!< ETHERNET MAC_CONFIG: DR Position */ +#define ETHERNET_MAC_CONFIG_DR_Msk (0x01UL << ETHERNET_MAC_CONFIG_DR_Pos) /*!< ETHERNET MAC_CONFIG: DR Mask */ +#define ETHERNET_MAC_CONFIG_DM_Pos 11 /*!< ETHERNET MAC_CONFIG: DM Position */ +#define ETHERNET_MAC_CONFIG_DM_Msk (0x01UL << ETHERNET_MAC_CONFIG_DM_Pos) /*!< ETHERNET MAC_CONFIG: DM Mask */ +#define ETHERNET_MAC_CONFIG_LM_Pos 12 /*!< ETHERNET MAC_CONFIG: LM Position */ +#define ETHERNET_MAC_CONFIG_LM_Msk (0x01UL << ETHERNET_MAC_CONFIG_LM_Pos) /*!< ETHERNET MAC_CONFIG: LM Mask */ +#define ETHERNET_MAC_CONFIG_DO_Pos 13 /*!< ETHERNET MAC_CONFIG: DO Position */ +#define ETHERNET_MAC_CONFIG_DO_Msk (0x01UL << ETHERNET_MAC_CONFIG_DO_Pos) /*!< ETHERNET MAC_CONFIG: DO Mask */ +#define ETHERNET_MAC_CONFIG_FES_Pos 14 /*!< ETHERNET MAC_CONFIG: FES Position */ +#define ETHERNET_MAC_CONFIG_FES_Msk (0x01UL << ETHERNET_MAC_CONFIG_FES_Pos) /*!< ETHERNET MAC_CONFIG: FES Mask */ +#define ETHERNET_MAC_CONFIG_PS_Pos 15 /*!< ETHERNET MAC_CONFIG: PS Position */ +#define ETHERNET_MAC_CONFIG_PS_Msk (0x01UL << ETHERNET_MAC_CONFIG_PS_Pos) /*!< ETHERNET MAC_CONFIG: PS Mask */ +#define ETHERNET_MAC_CONFIG_DCRS_Pos 16 /*!< ETHERNET MAC_CONFIG: DCRS Position */ +#define ETHERNET_MAC_CONFIG_DCRS_Msk (0x01UL << ETHERNET_MAC_CONFIG_DCRS_Pos) /*!< ETHERNET MAC_CONFIG: DCRS Mask */ +#define ETHERNET_MAC_CONFIG_IFG_Pos 17 /*!< ETHERNET MAC_CONFIG: IFG Position */ +#define ETHERNET_MAC_CONFIG_IFG_Msk (0x07UL << ETHERNET_MAC_CONFIG_IFG_Pos) /*!< ETHERNET MAC_CONFIG: IFG Mask */ +#define ETHERNET_MAC_CONFIG_JE_Pos 20 /*!< ETHERNET MAC_CONFIG: JE Position */ +#define ETHERNET_MAC_CONFIG_JE_Msk (0x01UL << ETHERNET_MAC_CONFIG_JE_Pos) /*!< ETHERNET MAC_CONFIG: JE Mask */ +#define ETHERNET_MAC_CONFIG_JD_Pos 22 /*!< ETHERNET MAC_CONFIG: JD Position */ +#define ETHERNET_MAC_CONFIG_JD_Msk (0x01UL << ETHERNET_MAC_CONFIG_JD_Pos) /*!< ETHERNET MAC_CONFIG: JD Mask */ +#define ETHERNET_MAC_CONFIG_WD_Pos 23 /*!< ETHERNET MAC_CONFIG: WD Position */ +#define ETHERNET_MAC_CONFIG_WD_Msk (0x01UL << ETHERNET_MAC_CONFIG_WD_Pos) /*!< ETHERNET MAC_CONFIG: WD Mask */ + +/* -------------------------- ETHERNET_MAC_FRAME_FILTER ------------------------- */ +#define ETHERNET_MAC_FRAME_FILTER_PR_Pos 0 /*!< ETHERNET MAC_FRAME_FILTER: PR Position */ +#define ETHERNET_MAC_FRAME_FILTER_PR_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_PR_Pos) /*!< ETHERNET MAC_FRAME_FILTER: PR Mask */ +#define ETHERNET_MAC_FRAME_FILTER_HUC_Pos 1 /*!< ETHERNET MAC_FRAME_FILTER: HUC Position */ +#define ETHERNET_MAC_FRAME_FILTER_HUC_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_HUC_Pos) /*!< ETHERNET MAC_FRAME_FILTER: HUC Mask */ +#define ETHERNET_MAC_FRAME_FILTER_HMC_Pos 2 /*!< ETHERNET MAC_FRAME_FILTER: HMC Position */ +#define ETHERNET_MAC_FRAME_FILTER_HMC_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_HMC_Pos) /*!< ETHERNET MAC_FRAME_FILTER: HMC Mask */ +#define ETHERNET_MAC_FRAME_FILTER_DAIF_Pos 3 /*!< ETHERNET MAC_FRAME_FILTER: DAIF Position */ +#define ETHERNET_MAC_FRAME_FILTER_DAIF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_DAIF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: DAIF Mask */ +#define ETHERNET_MAC_FRAME_FILTER_PM_Pos 4 /*!< ETHERNET MAC_FRAME_FILTER: PM Position */ +#define ETHERNET_MAC_FRAME_FILTER_PM_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_PM_Pos) /*!< ETHERNET MAC_FRAME_FILTER: PM Mask */ +#define ETHERNET_MAC_FRAME_FILTER_DBF_Pos 5 /*!< ETHERNET MAC_FRAME_FILTER: DBF Position */ +#define ETHERNET_MAC_FRAME_FILTER_DBF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_DBF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: DBF Mask */ +#define ETHERNET_MAC_FRAME_FILTER_PCF_Pos 6 /*!< ETHERNET MAC_FRAME_FILTER: PCF Position */ +#define ETHERNET_MAC_FRAME_FILTER_PCF_Msk (0x03UL << ETHERNET_MAC_FRAME_FILTER_PCF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: PCF Mask */ +#define ETHERNET_MAC_FRAME_FILTER_HPF_Pos 10 /*!< ETHERNET MAC_FRAME_FILTER: HPF Position */ +#define ETHERNET_MAC_FRAME_FILTER_HPF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_HPF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: HPF Mask */ +#define ETHERNET_MAC_FRAME_FILTER_RA_Pos 31 /*!< ETHERNET MAC_FRAME_FILTER: RA Position */ +#define ETHERNET_MAC_FRAME_FILTER_RA_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_RA_Pos) /*!< ETHERNET MAC_FRAME_FILTER: RA Mask */ + +/* ------------------------- ETHERNET_MAC_HASHTABLE_HIGH ------------------------ */ +#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos 0 /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Position */ +#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Msk (0xffffffffUL << ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos) /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Mask */ + +/* ------------------------- ETHERNET_MAC_HASHTABLE_LOW ------------------------- */ +#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos 0 /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Position */ +#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Msk (0xffffffffUL << ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos) /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Mask */ + +/* ---------------------------- ETHERNET_MAC_MII_ADDR --------------------------- */ +#define ETHERNET_MAC_MII_ADDR_GB_Pos 0 /*!< ETHERNET MAC_MII_ADDR: GB Position */ +#define ETHERNET_MAC_MII_ADDR_GB_Msk (0x01UL << ETHERNET_MAC_MII_ADDR_GB_Pos) /*!< ETHERNET MAC_MII_ADDR: GB Mask */ +#define ETHERNET_MAC_MII_ADDR_W_Pos 1 /*!< ETHERNET MAC_MII_ADDR: W Position */ +#define ETHERNET_MAC_MII_ADDR_W_Msk (0x01UL << ETHERNET_MAC_MII_ADDR_W_Pos) /*!< ETHERNET MAC_MII_ADDR: W Mask */ +#define ETHERNET_MAC_MII_ADDR_CR_Pos 2 /*!< ETHERNET MAC_MII_ADDR: CR Position */ +#define ETHERNET_MAC_MII_ADDR_CR_Msk (0x0fUL << ETHERNET_MAC_MII_ADDR_CR_Pos) /*!< ETHERNET MAC_MII_ADDR: CR Mask */ +#define ETHERNET_MAC_MII_ADDR_GR_Pos 6 /*!< ETHERNET MAC_MII_ADDR: GR Position */ +#define ETHERNET_MAC_MII_ADDR_GR_Msk (0x1fUL << ETHERNET_MAC_MII_ADDR_GR_Pos) /*!< ETHERNET MAC_MII_ADDR: GR Mask */ +#define ETHERNET_MAC_MII_ADDR_PA_Pos 11 /*!< ETHERNET MAC_MII_ADDR: PA Position */ +#define ETHERNET_MAC_MII_ADDR_PA_Msk (0x1fUL << ETHERNET_MAC_MII_ADDR_PA_Pos) /*!< ETHERNET MAC_MII_ADDR: PA Mask */ + +/* ---------------------------- ETHERNET_MAC_MII_DATA --------------------------- */ +#define ETHERNET_MAC_MII_DATA_GD_Pos 0 /*!< ETHERNET MAC_MII_DATA: GD Position */ +#define ETHERNET_MAC_MII_DATA_GD_Msk (0x0000ffffUL << ETHERNET_MAC_MII_DATA_GD_Pos) /*!< ETHERNET MAC_MII_DATA: GD Mask */ + +/* --------------------------- ETHERNET_MAC_FLOW_CTRL --------------------------- */ +#define ETHERNET_MAC_FLOW_CTRL_FCB_Pos 0 /*!< ETHERNET MAC_FLOW_CTRL: FCB Position */ +#define ETHERNET_MAC_FLOW_CTRL_FCB_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_FCB_Pos) /*!< ETHERNET MAC_FLOW_CTRL: FCB Mask */ +#define ETHERNET_MAC_FLOW_CTRL_TFE_Pos 1 /*!< ETHERNET MAC_FLOW_CTRL: TFE Position */ +#define ETHERNET_MAC_FLOW_CTRL_TFE_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_TFE_Pos) /*!< ETHERNET MAC_FLOW_CTRL: TFE Mask */ +#define ETHERNET_MAC_FLOW_CTRL_RFE_Pos 2 /*!< ETHERNET MAC_FLOW_CTRL: RFE Position */ +#define ETHERNET_MAC_FLOW_CTRL_RFE_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_RFE_Pos) /*!< ETHERNET MAC_FLOW_CTRL: RFE Mask */ +#define ETHERNET_MAC_FLOW_CTRL_UP_Pos 3 /*!< ETHERNET MAC_FLOW_CTRL: UP Position */ +#define ETHERNET_MAC_FLOW_CTRL_UP_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_UP_Pos) /*!< ETHERNET MAC_FLOW_CTRL: UP Mask */ +#define ETHERNET_MAC_FLOW_CTRL_PLT_Pos 4 /*!< ETHERNET MAC_FLOW_CTRL: PLT Position */ +#define ETHERNET_MAC_FLOW_CTRL_PLT_Msk (0x03UL << ETHERNET_MAC_FLOW_CTRL_PLT_Pos) /*!< ETHERNET MAC_FLOW_CTRL: PLT Mask */ +#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos 7 /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Position */ +#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos) /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Mask */ +#define ETHERNET_MAC_FLOW_CTRL_PT_Pos 16 /*!< ETHERNET MAC_FLOW_CTRL: PT Position */ +#define ETHERNET_MAC_FLOW_CTRL_PT_Msk (0x0000ffffUL << ETHERNET_MAC_FLOW_CTRL_PT_Pos) /*!< ETHERNET MAC_FLOW_CTRL: PT Mask */ + +/* ---------------------------- ETHERNET_MAC_VLAN_TAG --------------------------- */ +#define ETHERNET_MAC_VLAN_TAG_VL_Pos 0 /*!< ETHERNET MAC_VLAN_TAG: VL Position */ +#define ETHERNET_MAC_VLAN_TAG_VL_Msk (0x0000ffffUL << ETHERNET_MAC_VLAN_TAG_VL_Pos) /*!< ETHERNET MAC_VLAN_TAG: VL Mask */ +#define ETHERNET_MAC_VLAN_TAG_ETV_Pos 16 /*!< ETHERNET MAC_VLAN_TAG: ETV Position */ +#define ETHERNET_MAC_VLAN_TAG_ETV_Msk (0x01UL << ETHERNET_MAC_VLAN_TAG_ETV_Pos) /*!< ETHERNET MAC_VLAN_TAG: ETV Mask */ + +/* ----------------------------- ETHERNET_MAC_DEBUG ----------------------------- */ +#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos 0 /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Position */ +#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Msk (0x01UL << ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos) /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Mask */ +#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos 1 /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Position */ +#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Msk (0x03UL << ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos) /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Mask */ +#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos 4 /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Position */ +#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Msk (0x01UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos) /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Mask */ +#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos 5 /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Position */ +#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Msk (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos) /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Mask */ +#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos 8 /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Position */ +#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Msk (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos) /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Mask */ +#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos 16 /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Position */ +#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos) /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Mask */ +#define ETHERNET_MAC_DEBUG_TXSTAT_Pos 17 /*!< ETHERNET MAC_DEBUG: TXSTAT Position */ +#define ETHERNET_MAC_DEBUG_TXSTAT_Msk (0x03UL << ETHERNET_MAC_DEBUG_TXSTAT_Pos) /*!< ETHERNET MAC_DEBUG: TXSTAT Mask */ +#define ETHERNET_MAC_DEBUG_PAUSE_Pos 19 /*!< ETHERNET MAC_DEBUG: PAUSE Position */ +#define ETHERNET_MAC_DEBUG_PAUSE_Msk (0x01UL << ETHERNET_MAC_DEBUG_PAUSE_Pos) /*!< ETHERNET MAC_DEBUG: PAUSE Mask */ +#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos 20 /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Position */ +#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Msk (0x03UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Mask */ +#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos 22 /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Position */ +#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Mask */ +#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos 24 /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Position */ +#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Mask */ +#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos 25 /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Position */ +#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Mask */ + +/* -------------------------- ETHERNET_MAC_RWAKE_FRFLT -------------------------- */ +#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos 0 /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Position */ +#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Msk (0xffffffffUL << ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos) /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Mask */ + +/* ------------------------- ETHERNET_MAC_PMT_CTRL_STAT ------------------------- */ +#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos 0 /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Position */ +#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Mask */ +#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos 1 /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Position */ +#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Mask */ +#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos 2 /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Position */ +#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Mask */ +#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos 5 /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Position */ +#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Mask */ +#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos 6 /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Position */ +#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Mask */ +#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos 9 /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Position */ +#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Mask */ +#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos 31 /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Position */ +#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Mask */ + +/* ------------------------------ ETHERNET_MAC_INTR ----------------------------- */ +#define ETHERNET_MAC_INTR_PMT_Pos 3 /*!< ETHERNET MAC_INTR: PMT Position */ +#define ETHERNET_MAC_INTR_PMT_Msk (0x01UL << ETHERNET_MAC_INTR_PMT_Pos) /*!< ETHERNET MAC_INTR: PMT Mask */ +#define ETHERNET_MAC_INTR_TS_Pos 9 /*!< ETHERNET MAC_INTR: TS Position */ +#define ETHERNET_MAC_INTR_TS_Msk (0x01UL << ETHERNET_MAC_INTR_TS_Pos) /*!< ETHERNET MAC_INTR: TS Mask */ + +/* --------------------------- ETHERNET_MAC_INTR_MASK --------------------------- */ +#define ETHERNET_MAC_INTR_MASK_PMTIM_Pos 3 /*!< ETHERNET MAC_INTR_MASK: PMTIM Position */ +#define ETHERNET_MAC_INTR_MASK_PMTIM_Msk (0x01UL << ETHERNET_MAC_INTR_MASK_PMTIM_Pos) /*!< ETHERNET MAC_INTR_MASK: PMTIM Mask */ +#define ETHERNET_MAC_INTR_MASK_TSIM_Pos 9 /*!< ETHERNET MAC_INTR_MASK: TSIM Position */ +#define ETHERNET_MAC_INTR_MASK_TSIM_Msk (0x01UL << ETHERNET_MAC_INTR_MASK_TSIM_Pos) /*!< ETHERNET MAC_INTR_MASK: TSIM Mask */ + +/* --------------------------- ETHERNET_MAC_ADDR0_HIGH -------------------------- */ +#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos 0 /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Position */ +#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Msk (0x0000ffffUL << ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos) /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Mask */ +#define ETHERNET_MAC_ADDR0_HIGH_MO_Pos 31 /*!< ETHERNET MAC_ADDR0_HIGH: MO Position */ +#define ETHERNET_MAC_ADDR0_HIGH_MO_Msk (0x01UL << ETHERNET_MAC_ADDR0_HIGH_MO_Pos) /*!< ETHERNET MAC_ADDR0_HIGH: MO Mask */ + +/* --------------------------- ETHERNET_MAC_ADDR0_LOW --------------------------- */ +#define ETHERNET_MAC_ADDR0_LOW_A31_0_Pos 0 /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Position */ +#define ETHERNET_MAC_ADDR0_LOW_A31_0_Msk (0xffffffffUL << ETHERNET_MAC_ADDR0_LOW_A31_0_Pos) /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Mask */ + +/* -------------------------- ETHERNET_MAC_TIMESTP_CTRL ------------------------- */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos 0 /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Position */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Mask */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos 1 /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Position */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Mask */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos 2 /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Position */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Mask */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos 3 /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Position */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Mask */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos 4 /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Position */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Mask */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos 5 /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Position */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Mask */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos 8 /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Position */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Mask */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos 9 /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Position */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Mask */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos 10 /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Position */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Mask */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos 11 /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Position */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Mask */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos 12 /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Position */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Mask */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos 13 /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Position */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Mask */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos 14 /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Position */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Mask */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos 15 /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Position */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Mask */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos 16 /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Position */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Msk (0x03UL << ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Mask */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos 18 /*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Position */ +#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos)/*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Mask */ + +/* --------------------------- ETHERNET_SUBSECOND_INCR -------------------------- */ +#define ETHERNET_SUBSECOND_INCR_SSINC_Pos 0 /*!< ETHERNET SUBSECOND_INCR: SSINC Position */ +#define ETHERNET_SUBSECOND_INCR_SSINC_Msk (0x000000ffUL << ETHERNET_SUBSECOND_INCR_SSINC_Pos) /*!< ETHERNET SUBSECOND_INCR: SSINC Mask */ + +/* ------------------------------ ETHERNET_SECONDS ------------------------------ */ +#define ETHERNET_SECONDS_TSS_Pos 0 /*!< ETHERNET SECONDS: TSS Position */ +#define ETHERNET_SECONDS_TSS_Msk (0xffffffffUL << ETHERNET_SECONDS_TSS_Pos) /*!< ETHERNET SECONDS: TSS Mask */ + +/* ---------------------------- ETHERNET_NANOSECONDS ---------------------------- */ +#define ETHERNET_NANOSECONDS_TSSS_Pos 0 /*!< ETHERNET NANOSECONDS: TSSS Position */ +#define ETHERNET_NANOSECONDS_TSSS_Msk (0x7fffffffUL << ETHERNET_NANOSECONDS_TSSS_Pos) /*!< ETHERNET NANOSECONDS: TSSS Mask */ +#define ETHERNET_NANOSECONDS_PSNT_Pos 31 /*!< ETHERNET NANOSECONDS: PSNT Position */ +#define ETHERNET_NANOSECONDS_PSNT_Msk (0x01UL << ETHERNET_NANOSECONDS_PSNT_Pos) /*!< ETHERNET NANOSECONDS: PSNT Mask */ + +/* --------------------------- ETHERNET_SECONDSUPDATE --------------------------- */ +#define ETHERNET_SECONDSUPDATE_TSS_Pos 0 /*!< ETHERNET SECONDSUPDATE: TSS Position */ +#define ETHERNET_SECONDSUPDATE_TSS_Msk (0xffffffffUL << ETHERNET_SECONDSUPDATE_TSS_Pos) /*!< ETHERNET SECONDSUPDATE: TSS Mask */ + +/* ------------------------- ETHERNET_NANOSECONDSUPDATE ------------------------- */ +#define ETHERNET_NANOSECONDSUPDATE_TSSS_Pos 0 /*!< ETHERNET NANOSECONDSUPDATE: TSSS Position */ +#define ETHERNET_NANOSECONDSUPDATE_TSSS_Msk (0x7fffffffUL << ETHERNET_NANOSECONDSUPDATE_TSSS_Pos) /*!< ETHERNET NANOSECONDSUPDATE: TSSS Mask */ +#define ETHERNET_NANOSECONDSUPDATE_ADDSUB_Pos 31 /*!< ETHERNET NANOSECONDSUPDATE: ADDSUB Position */ +#define ETHERNET_NANOSECONDSUPDATE_ADDSUB_Msk (0x01UL << ETHERNET_NANOSECONDSUPDATE_ADDSUB_Pos) /*!< ETHERNET NANOSECONDSUPDATE: ADDSUB Mask */ + +/* ------------------------------- ETHERNET_ADDEND ------------------------------ */ +#define ETHERNET_ADDEND_TSAR_Pos 0 /*!< ETHERNET ADDEND: TSAR Position */ +#define ETHERNET_ADDEND_TSAR_Msk (0xffffffffUL << ETHERNET_ADDEND_TSAR_Pos) /*!< ETHERNET ADDEND: TSAR Mask */ + +/* --------------------------- ETHERNET_TARGETSECONDS --------------------------- */ +#define ETHERNET_TARGETSECONDS_TSTR_Pos 0 /*!< ETHERNET TARGETSECONDS: TSTR Position */ +#define ETHERNET_TARGETSECONDS_TSTR_Msk (0xffffffffUL << ETHERNET_TARGETSECONDS_TSTR_Pos) /*!< ETHERNET TARGETSECONDS: TSTR Mask */ + +/* ------------------------- ETHERNET_TARGETNANOSECONDS ------------------------- */ +#define ETHERNET_TARGETNANOSECONDS_TSTR_Pos 0 /*!< ETHERNET TARGETNANOSECONDS: TSTR Position */ +#define ETHERNET_TARGETNANOSECONDS_TSTR_Msk (0x7fffffffUL << ETHERNET_TARGETNANOSECONDS_TSTR_Pos) /*!< ETHERNET TARGETNANOSECONDS: TSTR Mask */ + +/* ------------------------------ ETHERNET_HIGHWORD ----------------------------- */ +#define ETHERNET_HIGHWORD_TSHWR_Pos 0 /*!< ETHERNET HIGHWORD: TSHWR Position */ +#define ETHERNET_HIGHWORD_TSHWR_Msk (0x0000ffffUL << ETHERNET_HIGHWORD_TSHWR_Pos) /*!< ETHERNET HIGHWORD: TSHWR Mask */ + +/* --------------------------- ETHERNET_TIMESTAMPSTAT --------------------------- */ +#define ETHERNET_TIMESTAMPSTAT_TSSOVF_Pos 0 /*!< ETHERNET TIMESTAMPSTAT: TSSOVF Position */ +#define ETHERNET_TIMESTAMPSTAT_TSSOVF_Msk (0x01UL << ETHERNET_TIMESTAMPSTAT_TSSOVF_Pos) /*!< ETHERNET TIMESTAMPSTAT: TSSOVF Mask */ +#define ETHERNET_TIMESTAMPSTAT_TSTARGT_Pos 1 /*!< ETHERNET TIMESTAMPSTAT: TSTARGT Position */ +#define ETHERNET_TIMESTAMPSTAT_TSTARGT_Msk (0x01UL << ETHERNET_TIMESTAMPSTAT_TSTARGT_Pos) /*!< ETHERNET TIMESTAMPSTAT: TSTARGT Mask */ + +/* ---------------------------- ETHERNET_DMA_BUS_MODE --------------------------- */ +#define ETHERNET_DMA_BUS_MODE_SWR_Pos 0 /*!< ETHERNET DMA_BUS_MODE: SWR Position */ +#define ETHERNET_DMA_BUS_MODE_SWR_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_SWR_Pos) /*!< ETHERNET DMA_BUS_MODE: SWR Mask */ +#define ETHERNET_DMA_BUS_MODE_DA_Pos 1 /*!< ETHERNET DMA_BUS_MODE: DA Position */ +#define ETHERNET_DMA_BUS_MODE_DA_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_DA_Pos) /*!< ETHERNET DMA_BUS_MODE: DA Mask */ +#define ETHERNET_DMA_BUS_MODE_DSL_Pos 2 /*!< ETHERNET DMA_BUS_MODE: DSL Position */ +#define ETHERNET_DMA_BUS_MODE_DSL_Msk (0x1fUL << ETHERNET_DMA_BUS_MODE_DSL_Pos) /*!< ETHERNET DMA_BUS_MODE: DSL Mask */ +#define ETHERNET_DMA_BUS_MODE_ATDS_Pos 7 /*!< ETHERNET DMA_BUS_MODE: ATDS Position */ +#define ETHERNET_DMA_BUS_MODE_ATDS_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_ATDS_Pos) /*!< ETHERNET DMA_BUS_MODE: ATDS Mask */ +#define ETHERNET_DMA_BUS_MODE_PBL_Pos 8 /*!< ETHERNET DMA_BUS_MODE: PBL Position */ +#define ETHERNET_DMA_BUS_MODE_PBL_Msk (0x3fUL << ETHERNET_DMA_BUS_MODE_PBL_Pos) /*!< ETHERNET DMA_BUS_MODE: PBL Mask */ +#define ETHERNET_DMA_BUS_MODE_PR_Pos 14 /*!< ETHERNET DMA_BUS_MODE: PR Position */ +#define ETHERNET_DMA_BUS_MODE_PR_Msk (0x03UL << ETHERNET_DMA_BUS_MODE_PR_Pos) /*!< ETHERNET DMA_BUS_MODE: PR Mask */ +#define ETHERNET_DMA_BUS_MODE_FB_Pos 16 /*!< ETHERNET DMA_BUS_MODE: FB Position */ +#define ETHERNET_DMA_BUS_MODE_FB_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_FB_Pos) /*!< ETHERNET DMA_BUS_MODE: FB Mask */ +#define ETHERNET_DMA_BUS_MODE_RPBL_Pos 17 /*!< ETHERNET DMA_BUS_MODE: RPBL Position */ +#define ETHERNET_DMA_BUS_MODE_RPBL_Msk (0x3fUL << ETHERNET_DMA_BUS_MODE_RPBL_Pos) /*!< ETHERNET DMA_BUS_MODE: RPBL Mask */ +#define ETHERNET_DMA_BUS_MODE_USP_Pos 23 /*!< ETHERNET DMA_BUS_MODE: USP Position */ +#define ETHERNET_DMA_BUS_MODE_USP_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_USP_Pos) /*!< ETHERNET DMA_BUS_MODE: USP Mask */ +#define ETHERNET_DMA_BUS_MODE_PBL8X_Pos 24 /*!< ETHERNET DMA_BUS_MODE: PBL8X Position */ +#define ETHERNET_DMA_BUS_MODE_PBL8X_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_PBL8X_Pos) /*!< ETHERNET DMA_BUS_MODE: PBL8X Mask */ +#define ETHERNET_DMA_BUS_MODE_AAL_Pos 25 /*!< ETHERNET DMA_BUS_MODE: AAL Position */ +#define ETHERNET_DMA_BUS_MODE_AAL_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_AAL_Pos) /*!< ETHERNET DMA_BUS_MODE: AAL Mask */ +#define ETHERNET_DMA_BUS_MODE_MB_Pos 26 /*!< ETHERNET DMA_BUS_MODE: MB Position */ +#define ETHERNET_DMA_BUS_MODE_MB_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_MB_Pos) /*!< ETHERNET DMA_BUS_MODE: MB Mask */ +#define ETHERNET_DMA_BUS_MODE_TXPR_Pos 27 /*!< ETHERNET DMA_BUS_MODE: TXPR Position */ +#define ETHERNET_DMA_BUS_MODE_TXPR_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_TXPR_Pos) /*!< ETHERNET DMA_BUS_MODE: TXPR Mask */ + +/* ----------------------- ETHERNET_DMA_TRANS_POLL_DEMAND ----------------------- */ +#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos 0 /*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Position */ +#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Msk (0xffffffffUL << ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos)/*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Mask */ + +/* ------------------------ ETHERNET_DMA_REC_POLL_DEMAND ------------------------ */ +#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos 0 /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Position */ +#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Msk (0xffffffffUL << ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos) /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Mask */ + +/* -------------------------- ETHERNET_DMA_REC_DES_ADDR ------------------------- */ +#define ETHERNET_DMA_REC_DES_ADDR_SRL_Pos 0 /*!< ETHERNET DMA_REC_DES_ADDR: SRL Position */ +#define ETHERNET_DMA_REC_DES_ADDR_SRL_Msk (0xffffffffUL << ETHERNET_DMA_REC_DES_ADDR_SRL_Pos) /*!< ETHERNET DMA_REC_DES_ADDR: SRL Mask */ + +/* ------------------------- ETHERNET_DMA_TRANS_DES_ADDR ------------------------ */ +#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos 0 /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Position */ +#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Msk (0xffffffffUL << ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos) /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Mask */ + +/* ------------------------------ ETHERNET_DMA_STAT ----------------------------- */ +#define ETHERNET_DMA_STAT_TI_Pos 0 /*!< ETHERNET DMA_STAT: TI Position */ +#define ETHERNET_DMA_STAT_TI_Msk (0x01UL << ETHERNET_DMA_STAT_TI_Pos) /*!< ETHERNET DMA_STAT: TI Mask */ +#define ETHERNET_DMA_STAT_TPS_Pos 1 /*!< ETHERNET DMA_STAT: TPS Position */ +#define ETHERNET_DMA_STAT_TPS_Msk (0x01UL << ETHERNET_DMA_STAT_TPS_Pos) /*!< ETHERNET DMA_STAT: TPS Mask */ +#define ETHERNET_DMA_STAT_TU_Pos 2 /*!< ETHERNET DMA_STAT: TU Position */ +#define ETHERNET_DMA_STAT_TU_Msk (0x01UL << ETHERNET_DMA_STAT_TU_Pos) /*!< ETHERNET DMA_STAT: TU Mask */ +#define ETHERNET_DMA_STAT_TJT_Pos 3 /*!< ETHERNET DMA_STAT: TJT Position */ +#define ETHERNET_DMA_STAT_TJT_Msk (0x01UL << ETHERNET_DMA_STAT_TJT_Pos) /*!< ETHERNET DMA_STAT: TJT Mask */ +#define ETHERNET_DMA_STAT_OVF_Pos 4 /*!< ETHERNET DMA_STAT: OVF Position */ +#define ETHERNET_DMA_STAT_OVF_Msk (0x01UL << ETHERNET_DMA_STAT_OVF_Pos) /*!< ETHERNET DMA_STAT: OVF Mask */ +#define ETHERNET_DMA_STAT_UNF_Pos 5 /*!< ETHERNET DMA_STAT: UNF Position */ +#define ETHERNET_DMA_STAT_UNF_Msk (0x01UL << ETHERNET_DMA_STAT_UNF_Pos) /*!< ETHERNET DMA_STAT: UNF Mask */ +#define ETHERNET_DMA_STAT_RI_Pos 6 /*!< ETHERNET DMA_STAT: RI Position */ +#define ETHERNET_DMA_STAT_RI_Msk (0x01UL << ETHERNET_DMA_STAT_RI_Pos) /*!< ETHERNET DMA_STAT: RI Mask */ +#define ETHERNET_DMA_STAT_RU_Pos 7 /*!< ETHERNET DMA_STAT: RU Position */ +#define ETHERNET_DMA_STAT_RU_Msk (0x01UL << ETHERNET_DMA_STAT_RU_Pos) /*!< ETHERNET DMA_STAT: RU Mask */ +#define ETHERNET_DMA_STAT_RPS_Pos 8 /*!< ETHERNET DMA_STAT: RPS Position */ +#define ETHERNET_DMA_STAT_RPS_Msk (0x01UL << ETHERNET_DMA_STAT_RPS_Pos) /*!< ETHERNET DMA_STAT: RPS Mask */ +#define ETHERNET_DMA_STAT_RWT_Pos 9 /*!< ETHERNET DMA_STAT: RWT Position */ +#define ETHERNET_DMA_STAT_RWT_Msk (0x01UL << ETHERNET_DMA_STAT_RWT_Pos) /*!< ETHERNET DMA_STAT: RWT Mask */ +#define ETHERNET_DMA_STAT_ETI_Pos 10 /*!< ETHERNET DMA_STAT: ETI Position */ +#define ETHERNET_DMA_STAT_ETI_Msk (0x01UL << ETHERNET_DMA_STAT_ETI_Pos) /*!< ETHERNET DMA_STAT: ETI Mask */ +#define ETHERNET_DMA_STAT_FBI_Pos 13 /*!< ETHERNET DMA_STAT: FBI Position */ +#define ETHERNET_DMA_STAT_FBI_Msk (0x01UL << ETHERNET_DMA_STAT_FBI_Pos) /*!< ETHERNET DMA_STAT: FBI Mask */ +#define ETHERNET_DMA_STAT_ERI_Pos 14 /*!< ETHERNET DMA_STAT: ERI Position */ +#define ETHERNET_DMA_STAT_ERI_Msk (0x01UL << ETHERNET_DMA_STAT_ERI_Pos) /*!< ETHERNET DMA_STAT: ERI Mask */ +#define ETHERNET_DMA_STAT_AIE_Pos 15 /*!< ETHERNET DMA_STAT: AIE Position */ +#define ETHERNET_DMA_STAT_AIE_Msk (0x01UL << ETHERNET_DMA_STAT_AIE_Pos) /*!< ETHERNET DMA_STAT: AIE Mask */ +#define ETHERNET_DMA_STAT_NIS_Pos 16 /*!< ETHERNET DMA_STAT: NIS Position */ +#define ETHERNET_DMA_STAT_NIS_Msk (0x01UL << ETHERNET_DMA_STAT_NIS_Pos) /*!< ETHERNET DMA_STAT: NIS Mask */ +#define ETHERNET_DMA_STAT_RS_Pos 17 /*!< ETHERNET DMA_STAT: RS Position */ +#define ETHERNET_DMA_STAT_RS_Msk (0x07UL << ETHERNET_DMA_STAT_RS_Pos) /*!< ETHERNET DMA_STAT: RS Mask */ +#define ETHERNET_DMA_STAT_TS_Pos 20 /*!< ETHERNET DMA_STAT: TS Position */ +#define ETHERNET_DMA_STAT_TS_Msk (0x07UL << ETHERNET_DMA_STAT_TS_Pos) /*!< ETHERNET DMA_STAT: TS Mask */ +#define ETHERNET_DMA_STAT_EB1_Pos 23 /*!< ETHERNET DMA_STAT: EB1 Position */ +#define ETHERNET_DMA_STAT_EB1_Msk (0x01UL << ETHERNET_DMA_STAT_EB1_Pos) /*!< ETHERNET DMA_STAT: EB1 Mask */ +#define ETHERNET_DMA_STAT_EB2_Pos 24 /*!< ETHERNET DMA_STAT: EB2 Position */ +#define ETHERNET_DMA_STAT_EB2_Msk (0x01UL << ETHERNET_DMA_STAT_EB2_Pos) /*!< ETHERNET DMA_STAT: EB2 Mask */ +#define ETHERNET_DMA_STAT_EB3_Pos 25 /*!< ETHERNET DMA_STAT: EB3 Position */ +#define ETHERNET_DMA_STAT_EB3_Msk (0x01UL << ETHERNET_DMA_STAT_EB3_Pos) /*!< ETHERNET DMA_STAT: EB3 Mask */ + +/* ---------------------------- ETHERNET_DMA_OP_MODE ---------------------------- */ +#define ETHERNET_DMA_OP_MODE_SR_Pos 1 /*!< ETHERNET DMA_OP_MODE: SR Position */ +#define ETHERNET_DMA_OP_MODE_SR_Msk (0x01UL << ETHERNET_DMA_OP_MODE_SR_Pos) /*!< ETHERNET DMA_OP_MODE: SR Mask */ +#define ETHERNET_DMA_OP_MODE_OSF_Pos 2 /*!< ETHERNET DMA_OP_MODE: OSF Position */ +#define ETHERNET_DMA_OP_MODE_OSF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_OSF_Pos) /*!< ETHERNET DMA_OP_MODE: OSF Mask */ +#define ETHERNET_DMA_OP_MODE_RTC_Pos 3 /*!< ETHERNET DMA_OP_MODE: RTC Position */ +#define ETHERNET_DMA_OP_MODE_RTC_Msk (0x03UL << ETHERNET_DMA_OP_MODE_RTC_Pos) /*!< ETHERNET DMA_OP_MODE: RTC Mask */ +#define ETHERNET_DMA_OP_MODE_FUF_Pos 6 /*!< ETHERNET DMA_OP_MODE: FUF Position */ +#define ETHERNET_DMA_OP_MODE_FUF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_FUF_Pos) /*!< ETHERNET DMA_OP_MODE: FUF Mask */ +#define ETHERNET_DMA_OP_MODE_FEF_Pos 7 /*!< ETHERNET DMA_OP_MODE: FEF Position */ +#define ETHERNET_DMA_OP_MODE_FEF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_FEF_Pos) /*!< ETHERNET DMA_OP_MODE: FEF Mask */ +#define ETHERNET_DMA_OP_MODE_ST_Pos 13 /*!< ETHERNET DMA_OP_MODE: ST Position */ +#define ETHERNET_DMA_OP_MODE_ST_Msk (0x01UL << ETHERNET_DMA_OP_MODE_ST_Pos) /*!< ETHERNET DMA_OP_MODE: ST Mask */ +#define ETHERNET_DMA_OP_MODE_TTC_Pos 14 /*!< ETHERNET DMA_OP_MODE: TTC Position */ +#define ETHERNET_DMA_OP_MODE_TTC_Msk (0x07UL << ETHERNET_DMA_OP_MODE_TTC_Pos) /*!< ETHERNET DMA_OP_MODE: TTC Mask */ +#define ETHERNET_DMA_OP_MODE_FTF_Pos 20 /*!< ETHERNET DMA_OP_MODE: FTF Position */ +#define ETHERNET_DMA_OP_MODE_FTF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_FTF_Pos) /*!< ETHERNET DMA_OP_MODE: FTF Mask */ +#define ETHERNET_DMA_OP_MODE_DFF_Pos 24 /*!< ETHERNET DMA_OP_MODE: DFF Position */ +#define ETHERNET_DMA_OP_MODE_DFF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_DFF_Pos) /*!< ETHERNET DMA_OP_MODE: DFF Mask */ + +/* ----------------------------- ETHERNET_DMA_INT_EN ---------------------------- */ +#define ETHERNET_DMA_INT_EN_TIE_Pos 0 /*!< ETHERNET DMA_INT_EN: TIE Position */ +#define ETHERNET_DMA_INT_EN_TIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TIE_Pos) /*!< ETHERNET DMA_INT_EN: TIE Mask */ +#define ETHERNET_DMA_INT_EN_TSE_Pos 1 /*!< ETHERNET DMA_INT_EN: TSE Position */ +#define ETHERNET_DMA_INT_EN_TSE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TSE_Pos) /*!< ETHERNET DMA_INT_EN: TSE Mask */ +#define ETHERNET_DMA_INT_EN_TUE_Pos 2 /*!< ETHERNET DMA_INT_EN: TUE Position */ +#define ETHERNET_DMA_INT_EN_TUE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TUE_Pos) /*!< ETHERNET DMA_INT_EN: TUE Mask */ +#define ETHERNET_DMA_INT_EN_TJE_Pos 3 /*!< ETHERNET DMA_INT_EN: TJE Position */ +#define ETHERNET_DMA_INT_EN_TJE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TJE_Pos) /*!< ETHERNET DMA_INT_EN: TJE Mask */ +#define ETHERNET_DMA_INT_EN_OVE_Pos 4 /*!< ETHERNET DMA_INT_EN: OVE Position */ +#define ETHERNET_DMA_INT_EN_OVE_Msk (0x01UL << ETHERNET_DMA_INT_EN_OVE_Pos) /*!< ETHERNET DMA_INT_EN: OVE Mask */ +#define ETHERNET_DMA_INT_EN_UNE_Pos 5 /*!< ETHERNET DMA_INT_EN: UNE Position */ +#define ETHERNET_DMA_INT_EN_UNE_Msk (0x01UL << ETHERNET_DMA_INT_EN_UNE_Pos) /*!< ETHERNET DMA_INT_EN: UNE Mask */ +#define ETHERNET_DMA_INT_EN_RIE_Pos 6 /*!< ETHERNET DMA_INT_EN: RIE Position */ +#define ETHERNET_DMA_INT_EN_RIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RIE_Pos) /*!< ETHERNET DMA_INT_EN: RIE Mask */ +#define ETHERNET_DMA_INT_EN_RUE_Pos 7 /*!< ETHERNET DMA_INT_EN: RUE Position */ +#define ETHERNET_DMA_INT_EN_RUE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RUE_Pos) /*!< ETHERNET DMA_INT_EN: RUE Mask */ +#define ETHERNET_DMA_INT_EN_RSE_Pos 8 /*!< ETHERNET DMA_INT_EN: RSE Position */ +#define ETHERNET_DMA_INT_EN_RSE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RSE_Pos) /*!< ETHERNET DMA_INT_EN: RSE Mask */ +#define ETHERNET_DMA_INT_EN_RWE_Pos 9 /*!< ETHERNET DMA_INT_EN: RWE Position */ +#define ETHERNET_DMA_INT_EN_RWE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RWE_Pos) /*!< ETHERNET DMA_INT_EN: RWE Mask */ +#define ETHERNET_DMA_INT_EN_ETE_Pos 10 /*!< ETHERNET DMA_INT_EN: ETE Position */ +#define ETHERNET_DMA_INT_EN_ETE_Msk (0x01UL << ETHERNET_DMA_INT_EN_ETE_Pos) /*!< ETHERNET DMA_INT_EN: ETE Mask */ +#define ETHERNET_DMA_INT_EN_FBE_Pos 13 /*!< ETHERNET DMA_INT_EN: FBE Position */ +#define ETHERNET_DMA_INT_EN_FBE_Msk (0x01UL << ETHERNET_DMA_INT_EN_FBE_Pos) /*!< ETHERNET DMA_INT_EN: FBE Mask */ +#define ETHERNET_DMA_INT_EN_ERE_Pos 14 /*!< ETHERNET DMA_INT_EN: ERE Position */ +#define ETHERNET_DMA_INT_EN_ERE_Msk (0x01UL << ETHERNET_DMA_INT_EN_ERE_Pos) /*!< ETHERNET DMA_INT_EN: ERE Mask */ +#define ETHERNET_DMA_INT_EN_AIE_Pos 15 /*!< ETHERNET DMA_INT_EN: AIE Position */ +#define ETHERNET_DMA_INT_EN_AIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_AIE_Pos) /*!< ETHERNET DMA_INT_EN: AIE Mask */ +#define ETHERNET_DMA_INT_EN_NIE_Pos 16 /*!< ETHERNET DMA_INT_EN: NIE Position */ +#define ETHERNET_DMA_INT_EN_NIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_NIE_Pos) /*!< ETHERNET DMA_INT_EN: NIE Mask */ + +/* --------------------------- ETHERNET_DMA_MFRM_BUFOF -------------------------- */ +#define ETHERNET_DMA_MFRM_BUFOF_FMC_Pos 0 /*!< ETHERNET DMA_MFRM_BUFOF: FMC Position */ +#define ETHERNET_DMA_MFRM_BUFOF_FMC_Msk (0x0000ffffUL << ETHERNET_DMA_MFRM_BUFOF_FMC_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: FMC Mask */ +#define ETHERNET_DMA_MFRM_BUFOF_OC_Pos 16 /*!< ETHERNET DMA_MFRM_BUFOF: OC Position */ +#define ETHERNET_DMA_MFRM_BUFOF_OC_Msk (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OC_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: OC Mask */ +#define ETHERNET_DMA_MFRM_BUFOF_FMA_Pos 17 /*!< ETHERNET DMA_MFRM_BUFOF: FMA Position */ +#define ETHERNET_DMA_MFRM_BUFOF_FMA_Msk (0x000007ffUL << ETHERNET_DMA_MFRM_BUFOF_FMA_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: FMA Mask */ +#define ETHERNET_DMA_MFRM_BUFOF_OF_Pos 28 /*!< ETHERNET DMA_MFRM_BUFOF: OF Position */ +#define ETHERNET_DMA_MFRM_BUFOF_OF_Msk (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OF_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: OF Mask */ + +/* -------------------------- ETHERNET_DMA_REC_INT_WDT -------------------------- */ +#define ETHERNET_DMA_REC_INT_WDT_RIWT_Pos 0 /*!< ETHERNET DMA_REC_INT_WDT: RIWT Position */ +#define ETHERNET_DMA_REC_INT_WDT_RIWT_Msk (0x000000ffUL << ETHERNET_DMA_REC_INT_WDT_RIWT_Pos) /*!< ETHERNET DMA_REC_INT_WDT: RIWT Mask */ + +/* ----------------------- ETHERNET_DMA_CURHOST_TRANS_DES ----------------------- */ +#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos 0 /*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Position */ +#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos)/*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Mask */ + +/* ------------------------ ETHERNET_DMA_CURHOST_REC_DES ------------------------ */ +#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos 0 /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Position */ +#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos) /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Mask */ + +/* ----------------------- ETHERNET_DMA_CURHOST_TRANS_BUF ----------------------- */ +#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos 0 /*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Position */ +#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos)/*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Mask */ + +/* ------------------------ ETHERNET_DMA_CURHOST_REC_BUF ------------------------ */ +#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos 0 /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Position */ +#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos) /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Mask */ + + +/* ================================================================================ */ +/* ================ struct 'ATIMER' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------- ATIMER_DOWNCOUNTER ----------------------------- */ +#define ATIMER_DOWNCOUNTER_CVAL_Pos 0 /*!< ATIMER DOWNCOUNTER: CVAL Position */ +#define ATIMER_DOWNCOUNTER_CVAL_Msk (0x0000ffffUL << ATIMER_DOWNCOUNTER_CVAL_Pos) /*!< ATIMER DOWNCOUNTER: CVAL Mask */ + +/* -------------------------------- ATIMER_PRESET ------------------------------- */ +#define ATIMER_PRESET_PRESETVAL_Pos 0 /*!< ATIMER PRESET: PRESETVAL Position */ +#define ATIMER_PRESET_PRESETVAL_Msk (0x0000ffffUL << ATIMER_PRESET_PRESETVAL_Pos) /*!< ATIMER PRESET: PRESETVAL Mask */ + +/* -------------------------------- ATIMER_CLR_EN ------------------------------- */ +#define ATIMER_CLR_EN_CLR_EN_Pos 0 /*!< ATIMER CLR_EN: CLR_EN Position */ +#define ATIMER_CLR_EN_CLR_EN_Msk (0x01UL << ATIMER_CLR_EN_CLR_EN_Pos) /*!< ATIMER CLR_EN: CLR_EN Mask */ + +/* -------------------------------- ATIMER_SET_EN ------------------------------- */ +#define ATIMER_SET_EN_SET_EN_Pos 0 /*!< ATIMER SET_EN: SET_EN Position */ +#define ATIMER_SET_EN_SET_EN_Msk (0x01UL << ATIMER_SET_EN_SET_EN_Pos) /*!< ATIMER SET_EN: SET_EN Mask */ + +/* -------------------------------- ATIMER_STATUS ------------------------------- */ +#define ATIMER_STATUS_STAT_Pos 0 /*!< ATIMER STATUS: STAT Position */ +#define ATIMER_STATUS_STAT_Msk (0x01UL << ATIMER_STATUS_STAT_Pos) /*!< ATIMER STATUS: STAT Mask */ + +/* -------------------------------- ATIMER_ENABLE ------------------------------- */ +#define ATIMER_ENABLE_EN_Pos 0 /*!< ATIMER ENABLE: EN Position */ +#define ATIMER_ENABLE_EN_Msk (0x01UL << ATIMER_ENABLE_EN_Pos) /*!< ATIMER ENABLE: EN Mask */ + +/* ------------------------------- ATIMER_CLR_STAT ------------------------------ */ +#define ATIMER_CLR_STAT_CSTAT_Pos 0 /*!< ATIMER CLR_STAT: CSTAT Position */ +#define ATIMER_CLR_STAT_CSTAT_Msk (0x01UL << ATIMER_CLR_STAT_CSTAT_Pos) /*!< ATIMER CLR_STAT: CSTAT Mask */ + +/* ------------------------------- ATIMER_SET_STAT ------------------------------ */ +#define ATIMER_SET_STAT_SSTAT_Pos 0 /*!< ATIMER SET_STAT: SSTAT Position */ +#define ATIMER_SET_STAT_SSTAT_Msk (0x01UL << ATIMER_SET_STAT_SSTAT_Pos) /*!< ATIMER SET_STAT: SSTAT Mask */ + + +/* ================================================================================ */ +/* ================ struct 'REGFILE' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- REGFILE_REGFILE ------------------------------ */ +#define REGFILE_REGFILE_REGVAL_Pos 0 /*!< REGFILE REGFILE: REGVAL Position */ +#define REGFILE_REGFILE_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE_REGVAL_Pos) /*!< REGFILE REGFILE: REGVAL Mask */ + + +/* ================================================================================ */ +/* ================ struct 'PMC' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------- PMC_PD0_SLEEP0_HW_ENA --------------------------- */ +#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos 0 /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Position */ +#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Msk (0x01UL << PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos) /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Mask */ + +/* ----------------------------- PMC_PD0_SLEEP0_MODE ---------------------------- */ +#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos 0 /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Position */ +#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Msk (0xffffffffUL << PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos) /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Mask */ + + +/* ================================================================================ */ +/* ================ struct 'CREG' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- CREG_CREG0 --------------------------------- */ +#define CREG_CREG0_EN1KHZ_Pos 0 /*!< CREG CREG0: EN1KHZ Position */ +#define CREG_CREG0_EN1KHZ_Msk (0x01UL << CREG_CREG0_EN1KHZ_Pos) /*!< CREG CREG0: EN1KHZ Mask */ +#define CREG_CREG0_EN32KHZ_Pos 1 /*!< CREG CREG0: EN32KHZ Position */ +#define CREG_CREG0_EN32KHZ_Msk (0x01UL << CREG_CREG0_EN32KHZ_Pos) /*!< CREG CREG0: EN32KHZ Mask */ +#define CREG_CREG0_RESET32KHZ_Pos 2 /*!< CREG CREG0: RESET32KHZ Position */ +#define CREG_CREG0_RESET32KHZ_Msk (0x01UL << CREG_CREG0_RESET32KHZ_Pos) /*!< CREG CREG0: RESET32KHZ Mask */ +#define CREG_CREG0_PD32KHZ_Pos 3 /*!< CREG CREG0: PD32KHZ Position */ +#define CREG_CREG0_PD32KHZ_Msk (0x01UL << CREG_CREG0_PD32KHZ_Pos) /*!< CREG CREG0: PD32KHZ Mask */ +#define CREG_CREG0_USB0PHY_Pos 5 /*!< CREG CREG0: USB0PHY Position */ +#define CREG_CREG0_USB0PHY_Msk (0x01UL << CREG_CREG0_USB0PHY_Pos) /*!< CREG CREG0: USB0PHY Mask */ +#define CREG_CREG0_ALARMCTRL_Pos 6 /*!< CREG CREG0: ALARMCTRL Position */ +#define CREG_CREG0_ALARMCTRL_Msk (0x03UL << CREG_CREG0_ALARMCTRL_Pos) /*!< CREG CREG0: ALARMCTRL Mask */ +#define CREG_CREG0_BODLVL1_Pos 8 /*!< CREG CREG0: BODLVL1 Position */ +#define CREG_CREG0_BODLVL1_Msk (0x03UL << CREG_CREG0_BODLVL1_Pos) /*!< CREG CREG0: BODLVL1 Mask */ +#define CREG_CREG0_BODLVL2_Pos 10 /*!< CREG CREG0: BODLVL2 Position */ +#define CREG_CREG0_BODLVL2_Msk (0x03UL << CREG_CREG0_BODLVL2_Pos) /*!< CREG CREG0: BODLVL2 Mask */ +#define CREG_CREG0_SAMPLECTRL_Pos 12 /*!< CREG CREG0: SAMPLECTRL Position */ +#define CREG_CREG0_SAMPLECTRL_Msk (0x03UL << CREG_CREG0_SAMPLECTRL_Pos) /*!< CREG CREG0: SAMPLECTRL Mask */ +#define CREG_CREG0_WAKEUP0CTRL_Pos 14 /*!< CREG CREG0: WAKEUP0CTRL Position */ +#define CREG_CREG0_WAKEUP0CTRL_Msk (0x03UL << CREG_CREG0_WAKEUP0CTRL_Pos) /*!< CREG CREG0: WAKEUP0CTRL Mask */ +#define CREG_CREG0_WAKEUP1CTRL_Pos 16 /*!< CREG CREG0: WAKEUP1CTRL Position */ +#define CREG_CREG0_WAKEUP1CTRL_Msk (0x03UL << CREG_CREG0_WAKEUP1CTRL_Pos) /*!< CREG CREG0: WAKEUP1CTRL Mask */ + +/* -------------------------------- CREG_M4MEMMAP ------------------------------- */ +#define CREG_M4MEMMAP_M4MAP_Pos 12 /*!< CREG M4MEMMAP: M4MAP Position */ +#define CREG_M4MEMMAP_M4MAP_Msk (0x000fffffUL << CREG_M4MEMMAP_M4MAP_Pos) /*!< CREG M4MEMMAP: M4MAP Mask */ + +/* --------------------------------- CREG_CREG5 --------------------------------- */ +#define CREG_CREG5_M0SUBTAPSEL_Pos 10 /*!< CREG CREG5: M0SUBTAPSEL Position */ +#define CREG_CREG5_M0SUBTAPSEL_Msk (0x01UL << CREG_CREG5_M0SUBTAPSEL_Pos) /*!< CREG CREG5: M0SUBTAPSEL Mask */ +#define CREG_CREG5_M4TAPSEL_Pos 11 /*!< CREG CREG5: M4TAPSEL Position */ +#define CREG_CREG5_M4TAPSEL_Msk (0x01UL << CREG_CREG5_M4TAPSEL_Pos) /*!< CREG CREG5: M4TAPSEL Mask */ +#define CREG_CREG5_M0APPTAPSEL_Pos 12 /*!< CREG CREG5: M0APPTAPSEL Position */ +#define CREG_CREG5_M0APPTAPSEL_Msk (0x01UL << CREG_CREG5_M0APPTAPSEL_Pos) /*!< CREG CREG5: M0APPTAPSEL Mask */ + +/* --------------------------------- CREG_DMAMUX -------------------------------- */ +#define CREG_DMAMUX_DMAMUXPER0_Pos 0 /*!< CREG DMAMUX: DMAMUXPER0 Position */ +#define CREG_DMAMUX_DMAMUXPER0_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER0_Pos) /*!< CREG DMAMUX: DMAMUXPER0 Mask */ +#define CREG_DMAMUX_DMAMUXPER1_Pos 2 /*!< CREG DMAMUX: DMAMUXPER1 Position */ +#define CREG_DMAMUX_DMAMUXPER1_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER1_Pos) /*!< CREG DMAMUX: DMAMUXPER1 Mask */ +#define CREG_DMAMUX_DMAMUXPER2_Pos 4 /*!< CREG DMAMUX: DMAMUXPER2 Position */ +#define CREG_DMAMUX_DMAMUXPER2_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER2_Pos) /*!< CREG DMAMUX: DMAMUXPER2 Mask */ +#define CREG_DMAMUX_DMAMUXPER3_Pos 6 /*!< CREG DMAMUX: DMAMUXPER3 Position */ +#define CREG_DMAMUX_DMAMUXPER3_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER3_Pos) /*!< CREG DMAMUX: DMAMUXPER3 Mask */ +#define CREG_DMAMUX_DMAMUXPER4_Pos 8 /*!< CREG DMAMUX: DMAMUXPER4 Position */ +#define CREG_DMAMUX_DMAMUXPER4_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER4_Pos) /*!< CREG DMAMUX: DMAMUXPER4 Mask */ +#define CREG_DMAMUX_DMAMUXPER5_Pos 10 /*!< CREG DMAMUX: DMAMUXPER5 Position */ +#define CREG_DMAMUX_DMAMUXPER5_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER5_Pos) /*!< CREG DMAMUX: DMAMUXPER5 Mask */ +#define CREG_DMAMUX_DMAMUXPER6_Pos 12 /*!< CREG DMAMUX: DMAMUXPER6 Position */ +#define CREG_DMAMUX_DMAMUXPER6_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER6_Pos) /*!< CREG DMAMUX: DMAMUXPER6 Mask */ +#define CREG_DMAMUX_DMAMUXPER7_Pos 14 /*!< CREG DMAMUX: DMAMUXPER7 Position */ +#define CREG_DMAMUX_DMAMUXPER7_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER7_Pos) /*!< CREG DMAMUX: DMAMUXPER7 Mask */ +#define CREG_DMAMUX_DMAMUXPER8_Pos 16 /*!< CREG DMAMUX: DMAMUXPER8 Position */ +#define CREG_DMAMUX_DMAMUXPER8_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER8_Pos) /*!< CREG DMAMUX: DMAMUXPER8 Mask */ +#define CREG_DMAMUX_DMAMUXPER9_Pos 18 /*!< CREG DMAMUX: DMAMUXPER9 Position */ +#define CREG_DMAMUX_DMAMUXPER9_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER9_Pos) /*!< CREG DMAMUX: DMAMUXPER9 Mask */ +#define CREG_DMAMUX_DMAMUXPER10_Pos 20 /*!< CREG DMAMUX: DMAMUXPER10 Position */ +#define CREG_DMAMUX_DMAMUXPER10_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER10_Pos) /*!< CREG DMAMUX: DMAMUXPER10 Mask */ +#define CREG_DMAMUX_DMAMUXPER11_Pos 22 /*!< CREG DMAMUX: DMAMUXPER11 Position */ +#define CREG_DMAMUX_DMAMUXPER11_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER11_Pos) /*!< CREG DMAMUX: DMAMUXPER11 Mask */ +#define CREG_DMAMUX_DMAMUXPER12_Pos 24 /*!< CREG DMAMUX: DMAMUXPER12 Position */ +#define CREG_DMAMUX_DMAMUXPER12_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER12_Pos) /*!< CREG DMAMUX: DMAMUXPER12 Mask */ +#define CREG_DMAMUX_DMAMUXPER13_Pos 26 /*!< CREG DMAMUX: DMAMUXPER13 Position */ +#define CREG_DMAMUX_DMAMUXPER13_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER13_Pos) /*!< CREG DMAMUX: DMAMUXPER13 Mask */ +#define CREG_DMAMUX_DMAMUXPER14_Pos 28 /*!< CREG DMAMUX: DMAMUXPER14 Position */ +#define CREG_DMAMUX_DMAMUXPER14_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER14_Pos) /*!< CREG DMAMUX: DMAMUXPER14 Mask */ +#define CREG_DMAMUX_DMAMUXPER15_Pos 30 /*!< CREG DMAMUX: DMAMUXPER15 Position */ +#define CREG_DMAMUX_DMAMUXPER15_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER15_Pos) /*!< CREG DMAMUX: DMAMUXPER15 Mask */ + +/* ------------------------------- CREG_FLASHCFGA ------------------------------- */ +#define CREG_FLASHCFGA_FLASHTIM_Pos 12 /*!< CREG FLASHCFGA: FLASHTIM Position */ +#define CREG_FLASHCFGA_FLASHTIM_Msk (0x0fUL << CREG_FLASHCFGA_FLASHTIM_Pos) /*!< CREG FLASHCFGA: FLASHTIM Mask */ +#define CREG_FLASHCFGA_POW_Pos 31 /*!< CREG FLASHCFGA: POW Position */ +#define CREG_FLASHCFGA_POW_Msk (0x01UL << CREG_FLASHCFGA_POW_Pos) /*!< CREG FLASHCFGA: POW Mask */ + +/* ------------------------------- CREG_FLASHCFGB ------------------------------- */ +#define CREG_FLASHCFGB_FLASHTIM_Pos 12 /*!< CREG FLASHCFGB: FLASHTIM Position */ +#define CREG_FLASHCFGB_FLASHTIM_Msk (0x0fUL << CREG_FLASHCFGB_FLASHTIM_Pos) /*!< CREG FLASHCFGB: FLASHTIM Mask */ +#define CREG_FLASHCFGB_POW_Pos 31 /*!< CREG FLASHCFGB: POW Position */ +#define CREG_FLASHCFGB_POW_Msk (0x01UL << CREG_FLASHCFGB_POW_Pos) /*!< CREG FLASHCFGB: POW Mask */ + +/* --------------------------------- CREG_ETBCFG -------------------------------- */ +#define CREG_ETBCFG_ETB_Pos 0 /*!< CREG ETBCFG: ETB Position */ +#define CREG_ETBCFG_ETB_Msk (0x01UL << CREG_ETBCFG_ETB_Pos) /*!< CREG ETBCFG: ETB Mask */ + +/* --------------------------------- CREG_CREG6 --------------------------------- */ +#define CREG_CREG6_ETHMODE_Pos 0 /*!< CREG CREG6: ETHMODE Position */ +#define CREG_CREG6_ETHMODE_Msk (0x07UL << CREG_CREG6_ETHMODE_Pos) /*!< CREG CREG6: ETHMODE Mask */ +#define CREG_CREG6_CTOUTCTRL_Pos 4 /*!< CREG CREG6: CTOUTCTRL Position */ +#define CREG_CREG6_CTOUTCTRL_Msk (0x01UL << CREG_CREG6_CTOUTCTRL_Pos) /*!< CREG CREG6: CTOUTCTRL Mask */ +#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos 12 /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Position */ +#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Mask */ +#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos 13 /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Position */ +#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Mask */ +#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos 14 /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Position */ +#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Mask */ +#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos 15 /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Position */ +#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Mask */ +#define CREG_CREG6_EMC_CLK_SEL_Pos 16 /*!< CREG CREG6: EMC_CLK_SEL Position */ +#define CREG_CREG6_EMC_CLK_SEL_Msk (0x01UL << CREG_CREG6_EMC_CLK_SEL_Pos) /*!< CREG CREG6: EMC_CLK_SEL Mask */ + +/* ------------------------------- CREG_M4TXEVENT ------------------------------- */ +#define CREG_M4TXEVENT_TXEVCLR_Pos 0 /*!< CREG M4TXEVENT: TXEVCLR Position */ +#define CREG_M4TXEVENT_TXEVCLR_Msk (0x01UL << CREG_M4TXEVENT_TXEVCLR_Pos) /*!< CREG M4TXEVENT: TXEVCLR Mask */ + +/* --------------------------------- CREG_CHIPID -------------------------------- */ +#define CREG_CHIPID_ID_Pos 0 /*!< CREG CHIPID: ID Position */ +#define CREG_CHIPID_ID_Msk (0xffffffffUL << CREG_CHIPID_ID_Pos) /*!< CREG CHIPID: ID Mask */ + +/* ------------------------------ CREG_M0SUBMEMMAP ------------------------------ */ +#define CREG_M0SUBMEMMAP_M0SUBMAP_Pos 12 /*!< CREG M0SUBMEMMAP: M0SUBMAP Position */ +#define CREG_M0SUBMEMMAP_M0SUBMAP_Msk (0x000fffffUL << CREG_M0SUBMEMMAP_M0SUBMAP_Pos) /*!< CREG M0SUBMEMMAP: M0SUBMAP Mask */ + +/* ------------------------------ CREG_M0SUBTXEVENT ----------------------------- */ +#define CREG_M0SUBTXEVENT_TXEVCLR_Pos 0 /*!< CREG M0SUBTXEVENT: TXEVCLR Position */ +#define CREG_M0SUBTXEVENT_TXEVCLR_Msk (0x01UL << CREG_M0SUBTXEVENT_TXEVCLR_Pos) /*!< CREG M0SUBTXEVENT: TXEVCLR Mask */ + +/* ------------------------------ CREG_M0APPTXEVENT ----------------------------- */ +#define CREG_M0APPTXEVENT_TXEVCLR_Pos 0 /*!< CREG M0APPTXEVENT: TXEVCLR Position */ +#define CREG_M0APPTXEVENT_TXEVCLR_Msk (0x01UL << CREG_M0APPTXEVENT_TXEVCLR_Pos) /*!< CREG M0APPTXEVENT: TXEVCLR Mask */ + +/* ------------------------------ CREG_M0APPMEMMAP ------------------------------ */ +#define CREG_M0APPMEMMAP_M0APPMAP_Pos 12 /*!< CREG M0APPMEMMAP: M0APPMAP Position */ +#define CREG_M0APPMEMMAP_M0APPMAP_Msk (0x000fffffUL << CREG_M0APPMEMMAP_M0APPMAP_Pos) /*!< CREG M0APPMEMMAP: M0APPMAP Mask */ + +/* ------------------------------- CREG_USB0FLADJ ------------------------------- */ +#define CREG_USB0FLADJ_FLTV_Pos 0 /*!< CREG USB0FLADJ: FLTV Position */ +#define CREG_USB0FLADJ_FLTV_Msk (0x3fUL << CREG_USB0FLADJ_FLTV_Pos) /*!< CREG USB0FLADJ: FLTV Mask */ + +/* ------------------------------- CREG_USB1FLADJ ------------------------------- */ +#define CREG_USB1FLADJ_FLTV_Pos 0 /*!< CREG USB1FLADJ: FLTV Position */ +#define CREG_USB1FLADJ_FLTV_Msk (0x3fUL << CREG_USB1FLADJ_FLTV_Pos) /*!< CREG USB1FLADJ: FLTV Mask */ + + +/* ================================================================================ */ +/* ================ struct 'EVENTROUTER' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------ EVENTROUTER_HILO ------------------------------ */ +#define EVENTROUTER_HILO_WAKEUP0_L_Pos 0 /*!< EVENTROUTER HILO: WAKEUP0_L Position */ +#define EVENTROUTER_HILO_WAKEUP0_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP0_L_Pos) /*!< EVENTROUTER HILO: WAKEUP0_L Mask */ +#define EVENTROUTER_HILO_WAKEUP1_L_Pos 1 /*!< EVENTROUTER HILO: WAKEUP1_L Position */ +#define EVENTROUTER_HILO_WAKEUP1_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP1_L_Pos) /*!< EVENTROUTER HILO: WAKEUP1_L Mask */ +#define EVENTROUTER_HILO_WAKEUP2_L_Pos 2 /*!< EVENTROUTER HILO: WAKEUP2_L Position */ +#define EVENTROUTER_HILO_WAKEUP2_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP2_L_Pos) /*!< EVENTROUTER HILO: WAKEUP2_L Mask */ +#define EVENTROUTER_HILO_WAKEUP3_L_Pos 3 /*!< EVENTROUTER HILO: WAKEUP3_L Position */ +#define EVENTROUTER_HILO_WAKEUP3_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP3_L_Pos) /*!< EVENTROUTER HILO: WAKEUP3_L Mask */ +#define EVENTROUTER_HILO_ATIMER_L_Pos 4 /*!< EVENTROUTER HILO: ATIMER_L Position */ +#define EVENTROUTER_HILO_ATIMER_L_Msk (0x01UL << EVENTROUTER_HILO_ATIMER_L_Pos) /*!< EVENTROUTER HILO: ATIMER_L Mask */ +#define EVENTROUTER_HILO_RTC_L_Pos 5 /*!< EVENTROUTER HILO: RTC_L Position */ +#define EVENTROUTER_HILO_RTC_L_Msk (0x01UL << EVENTROUTER_HILO_RTC_L_Pos) /*!< EVENTROUTER HILO: RTC_L Mask */ +#define EVENTROUTER_HILO_BOD_L_Pos 6 /*!< EVENTROUTER HILO: BOD_L Position */ +#define EVENTROUTER_HILO_BOD_L_Msk (0x01UL << EVENTROUTER_HILO_BOD_L_Pos) /*!< EVENTROUTER HILO: BOD_L Mask */ +#define EVENTROUTER_HILO_WWDT_L_Pos 7 /*!< EVENTROUTER HILO: WWDT_L Position */ +#define EVENTROUTER_HILO_WWDT_L_Msk (0x01UL << EVENTROUTER_HILO_WWDT_L_Pos) /*!< EVENTROUTER HILO: WWDT_L Mask */ +#define EVENTROUTER_HILO_ETH_L_Pos 8 /*!< EVENTROUTER HILO: ETH_L Position */ +#define EVENTROUTER_HILO_ETH_L_Msk (0x01UL << EVENTROUTER_HILO_ETH_L_Pos) /*!< EVENTROUTER HILO: ETH_L Mask */ +#define EVENTROUTER_HILO_USB0_L_Pos 9 /*!< EVENTROUTER HILO: USB0_L Position */ +#define EVENTROUTER_HILO_USB0_L_Msk (0x01UL << EVENTROUTER_HILO_USB0_L_Pos) /*!< EVENTROUTER HILO: USB0_L Mask */ +#define EVENTROUTER_HILO_USB1_L_Pos 10 /*!< EVENTROUTER HILO: USB1_L Position */ +#define EVENTROUTER_HILO_USB1_L_Msk (0x01UL << EVENTROUTER_HILO_USB1_L_Pos) /*!< EVENTROUTER HILO: USB1_L Mask */ +#define EVENTROUTER_HILO_SDMMC_L_Pos 11 /*!< EVENTROUTER HILO: SDMMC_L Position */ +#define EVENTROUTER_HILO_SDMMC_L_Msk (0x01UL << EVENTROUTER_HILO_SDMMC_L_Pos) /*!< EVENTROUTER HILO: SDMMC_L Mask */ +#define EVENTROUTER_HILO_CAN_L_Pos 12 /*!< EVENTROUTER HILO: CAN_L Position */ +#define EVENTROUTER_HILO_CAN_L_Msk (0x01UL << EVENTROUTER_HILO_CAN_L_Pos) /*!< EVENTROUTER HILO: CAN_L Mask */ +#define EVENTROUTER_HILO_TIM2_L_Pos 13 /*!< EVENTROUTER HILO: TIM2_L Position */ +#define EVENTROUTER_HILO_TIM2_L_Msk (0x01UL << EVENTROUTER_HILO_TIM2_L_Pos) /*!< EVENTROUTER HILO: TIM2_L Mask */ +#define EVENTROUTER_HILO_TIM6_L_Pos 14 /*!< EVENTROUTER HILO: TIM6_L Position */ +#define EVENTROUTER_HILO_TIM6_L_Msk (0x01UL << EVENTROUTER_HILO_TIM6_L_Pos) /*!< EVENTROUTER HILO: TIM6_L Mask */ +#define EVENTROUTER_HILO_QEI_L_Pos 15 /*!< EVENTROUTER HILO: QEI_L Position */ +#define EVENTROUTER_HILO_QEI_L_Msk (0x01UL << EVENTROUTER_HILO_QEI_L_Pos) /*!< EVENTROUTER HILO: QEI_L Mask */ +#define EVENTROUTER_HILO_TIM14_L_Pos 16 /*!< EVENTROUTER HILO: TIM14_L Position */ +#define EVENTROUTER_HILO_TIM14_L_Msk (0x01UL << EVENTROUTER_HILO_TIM14_L_Pos) /*!< EVENTROUTER HILO: TIM14_L Mask */ +#define EVENTROUTER_HILO_RESET_L_Pos 19 /*!< EVENTROUTER HILO: RESET_L Position */ +#define EVENTROUTER_HILO_RESET_L_Msk (0x01UL << EVENTROUTER_HILO_RESET_L_Pos) /*!< EVENTROUTER HILO: RESET_L Mask */ +#define EVENTROUTER_HILO_BODRESET_L_Pos 20 /*!< EVENTROUTER HILO: BODRESET_L Position */ +#define EVENTROUTER_HILO_BODRESET_L_Msk (0x01UL << EVENTROUTER_HILO_BODRESET_L_Pos) /*!< EVENTROUTER HILO: BODRESET_L Mask */ +#define EVENTROUTER_HILO_DPDRESET_L_Pos 21 /*!< EVENTROUTER HILO: DPDRESET_L Position */ +#define EVENTROUTER_HILO_DPDRESET_L_Msk (0x01UL << EVENTROUTER_HILO_DPDRESET_L_Pos) /*!< EVENTROUTER HILO: DPDRESET_L Mask */ + +/* ------------------------------ EVENTROUTER_EDGE ------------------------------ */ +#define EVENTROUTER_EDGE_WAKEUP0_E_Pos 0 /*!< EVENTROUTER EDGE: WAKEUP0_E Position */ +#define EVENTROUTER_EDGE_WAKEUP0_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP0_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP0_E Mask */ +#define EVENTROUTER_EDGE_WAKEUP1_E_Pos 1 /*!< EVENTROUTER EDGE: WAKEUP1_E Position */ +#define EVENTROUTER_EDGE_WAKEUP1_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP1_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP1_E Mask */ +#define EVENTROUTER_EDGE_WAKEUP2_E_Pos 2 /*!< EVENTROUTER EDGE: WAKEUP2_E Position */ +#define EVENTROUTER_EDGE_WAKEUP2_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP2_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP2_E Mask */ +#define EVENTROUTER_EDGE_WAKEUP3_E_Pos 3 /*!< EVENTROUTER EDGE: WAKEUP3_E Position */ +#define EVENTROUTER_EDGE_WAKEUP3_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP3_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP3_E Mask */ +#define EVENTROUTER_EDGE_ATIMER_E_Pos 4 /*!< EVENTROUTER EDGE: ATIMER_E Position */ +#define EVENTROUTER_EDGE_ATIMER_E_Msk (0x01UL << EVENTROUTER_EDGE_ATIMER_E_Pos) /*!< EVENTROUTER EDGE: ATIMER_E Mask */ +#define EVENTROUTER_EDGE_RTC_E_Pos 5 /*!< EVENTROUTER EDGE: RTC_E Position */ +#define EVENTROUTER_EDGE_RTC_E_Msk (0x01UL << EVENTROUTER_EDGE_RTC_E_Pos) /*!< EVENTROUTER EDGE: RTC_E Mask */ +#define EVENTROUTER_EDGE_BOD_E_Pos 6 /*!< EVENTROUTER EDGE: BOD_E Position */ +#define EVENTROUTER_EDGE_BOD_E_Msk (0x01UL << EVENTROUTER_EDGE_BOD_E_Pos) /*!< EVENTROUTER EDGE: BOD_E Mask */ +#define EVENTROUTER_EDGE_WWDT_E_Pos 7 /*!< EVENTROUTER EDGE: WWDT_E Position */ +#define EVENTROUTER_EDGE_WWDT_E_Msk (0x01UL << EVENTROUTER_EDGE_WWDT_E_Pos) /*!< EVENTROUTER EDGE: WWDT_E Mask */ +#define EVENTROUTER_EDGE_ETH_E_Pos 8 /*!< EVENTROUTER EDGE: ETH_E Position */ +#define EVENTROUTER_EDGE_ETH_E_Msk (0x01UL << EVENTROUTER_EDGE_ETH_E_Pos) /*!< EVENTROUTER EDGE: ETH_E Mask */ +#define EVENTROUTER_EDGE_USB0_E_Pos 9 /*!< EVENTROUTER EDGE: USB0_E Position */ +#define EVENTROUTER_EDGE_USB0_E_Msk (0x01UL << EVENTROUTER_EDGE_USB0_E_Pos) /*!< EVENTROUTER EDGE: USB0_E Mask */ +#define EVENTROUTER_EDGE_USB1_E_Pos 10 /*!< EVENTROUTER EDGE: USB1_E Position */ +#define EVENTROUTER_EDGE_USB1_E_Msk (0x01UL << EVENTROUTER_EDGE_USB1_E_Pos) /*!< EVENTROUTER EDGE: USB1_E Mask */ +#define EVENTROUTER_EDGE_SDMMC_E_Pos 11 /*!< EVENTROUTER EDGE: SDMMC_E Position */ +#define EVENTROUTER_EDGE_SDMMC_E_Msk (0x01UL << EVENTROUTER_EDGE_SDMMC_E_Pos) /*!< EVENTROUTER EDGE: SDMMC_E Mask */ +#define EVENTROUTER_EDGE_CAN_E_Pos 12 /*!< EVENTROUTER EDGE: CAN_E Position */ +#define EVENTROUTER_EDGE_CAN_E_Msk (0x01UL << EVENTROUTER_EDGE_CAN_E_Pos) /*!< EVENTROUTER EDGE: CAN_E Mask */ +#define EVENTROUTER_EDGE_TIM2_E_Pos 13 /*!< EVENTROUTER EDGE: TIM2_E Position */ +#define EVENTROUTER_EDGE_TIM2_E_Msk (0x01UL << EVENTROUTER_EDGE_TIM2_E_Pos) /*!< EVENTROUTER EDGE: TIM2_E Mask */ +#define EVENTROUTER_EDGE_TIM6_E_Pos 14 /*!< EVENTROUTER EDGE: TIM6_E Position */ +#define EVENTROUTER_EDGE_TIM6_E_Msk (0x01UL << EVENTROUTER_EDGE_TIM6_E_Pos) /*!< EVENTROUTER EDGE: TIM6_E Mask */ +#define EVENTROUTER_EDGE_QEI_E_Pos 15 /*!< EVENTROUTER EDGE: QEI_E Position */ +#define EVENTROUTER_EDGE_QEI_E_Msk (0x01UL << EVENTROUTER_EDGE_QEI_E_Pos) /*!< EVENTROUTER EDGE: QEI_E Mask */ +#define EVENTROUTER_EDGE_TIM14_E_Pos 16 /*!< EVENTROUTER EDGE: TIM14_E Position */ +#define EVENTROUTER_EDGE_TIM14_E_Msk (0x01UL << EVENTROUTER_EDGE_TIM14_E_Pos) /*!< EVENTROUTER EDGE: TIM14_E Mask */ +#define EVENTROUTER_EDGE_RESET_E_Pos 19 /*!< EVENTROUTER EDGE: RESET_E Position */ +#define EVENTROUTER_EDGE_RESET_E_Msk (0x01UL << EVENTROUTER_EDGE_RESET_E_Pos) /*!< EVENTROUTER EDGE: RESET_E Mask */ +#define EVENTROUTER_EDGE_BODRESET_E_Pos 20 /*!< EVENTROUTER EDGE: BODRESET_E Position */ +#define EVENTROUTER_EDGE_BODRESET_E_Msk (0x01UL << EVENTROUTER_EDGE_BODRESET_E_Pos) /*!< EVENTROUTER EDGE: BODRESET_E Mask */ +#define EVENTROUTER_EDGE_DPDRESET_E_Pos 21 /*!< EVENTROUTER EDGE: DPDRESET_E Position */ +#define EVENTROUTER_EDGE_DPDRESET_E_Msk (0x01UL << EVENTROUTER_EDGE_DPDRESET_E_Pos) /*!< EVENTROUTER EDGE: DPDRESET_E Mask */ + +/* ----------------------------- EVENTROUTER_CLR_EN ----------------------------- */ +#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos 0 /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Position */ +#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Mask */ +#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos 1 /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Position */ +#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Mask */ +#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos 2 /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Position */ +#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Mask */ +#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos 3 /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Position */ +#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Mask */ +#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos 4 /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Position */ +#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos) /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Mask */ +#define EVENTROUTER_CLR_EN_RTC_CLREN_Pos 5 /*!< EVENTROUTER CLR_EN: RTC_CLREN Position */ +#define EVENTROUTER_CLR_EN_RTC_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_RTC_CLREN_Pos) /*!< EVENTROUTER CLR_EN: RTC_CLREN Mask */ +#define EVENTROUTER_CLR_EN_BOD_CLREN_Pos 6 /*!< EVENTROUTER CLR_EN: BOD_CLREN Position */ +#define EVENTROUTER_CLR_EN_BOD_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_BOD_CLREN_Pos) /*!< EVENTROUTER CLR_EN: BOD_CLREN Mask */ +#define EVENTROUTER_CLR_EN_WWDT_CLREN_Pos 7 /*!< EVENTROUTER CLR_EN: WWDT_CLREN Position */ +#define EVENTROUTER_CLR_EN_WWDT_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WWDT_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WWDT_CLREN Mask */ +#define EVENTROUTER_CLR_EN_ETH_CLREN_Pos 8 /*!< EVENTROUTER CLR_EN: ETH_CLREN Position */ +#define EVENTROUTER_CLR_EN_ETH_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_ETH_CLREN_Pos) /*!< EVENTROUTER CLR_EN: ETH_CLREN Mask */ +#define EVENTROUTER_CLR_EN_USB0_CLREN_Pos 9 /*!< EVENTROUTER CLR_EN: USB0_CLREN Position */ +#define EVENTROUTER_CLR_EN_USB0_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_USB0_CLREN_Pos) /*!< EVENTROUTER CLR_EN: USB0_CLREN Mask */ +#define EVENTROUTER_CLR_EN_USB1_CLREN_Pos 10 /*!< EVENTROUTER CLR_EN: USB1_CLREN Position */ +#define EVENTROUTER_CLR_EN_USB1_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_USB1_CLREN_Pos) /*!< EVENTROUTER CLR_EN: USB1_CLREN Mask */ +#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos 11 /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Position */ +#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos) /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Mask */ +#define EVENTROUTER_CLR_EN_CAN_CLREN_Pos 12 /*!< EVENTROUTER CLR_EN: CAN_CLREN Position */ +#define EVENTROUTER_CLR_EN_CAN_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_CAN_CLREN_Pos) /*!< EVENTROUTER CLR_EN: CAN_CLREN Mask */ +#define EVENTROUTER_CLR_EN_TIM2_CLREN_Pos 13 /*!< EVENTROUTER CLR_EN: TIM2_CLREN Position */ +#define EVENTROUTER_CLR_EN_TIM2_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_TIM2_CLREN_Pos) /*!< EVENTROUTER CLR_EN: TIM2_CLREN Mask */ +#define EVENTROUTER_CLR_EN_TIM6_CLREN_Pos 14 /*!< EVENTROUTER CLR_EN: TIM6_CLREN Position */ +#define EVENTROUTER_CLR_EN_TIM6_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_TIM6_CLREN_Pos) /*!< EVENTROUTER CLR_EN: TIM6_CLREN Mask */ +#define EVENTROUTER_CLR_EN_QEI_CLREN_Pos 15 /*!< EVENTROUTER CLR_EN: QEI_CLREN Position */ +#define EVENTROUTER_CLR_EN_QEI_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_QEI_CLREN_Pos) /*!< EVENTROUTER CLR_EN: QEI_CLREN Mask */ +#define EVENTROUTER_CLR_EN_TIM14_CLREN_Pos 16 /*!< EVENTROUTER CLR_EN: TIM14_CLREN Position */ +#define EVENTROUTER_CLR_EN_TIM14_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_TIM14_CLREN_Pos) /*!< EVENTROUTER CLR_EN: TIM14_CLREN Mask */ +#define EVENTROUTER_CLR_EN_RESET_CLREN_Pos 19 /*!< EVENTROUTER CLR_EN: RESET_CLREN Position */ +#define EVENTROUTER_CLR_EN_RESET_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_RESET_CLREN_Pos) /*!< EVENTROUTER CLR_EN: RESET_CLREN Mask */ +#define EVENTROUTER_CLR_EN_BODRESET_CLREN_Pos 20 /*!< EVENTROUTER CLR_EN: BODRESET_CLREN Position */ +#define EVENTROUTER_CLR_EN_BODRESET_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_BODRESET_CLREN_Pos) /*!< EVENTROUTER CLR_EN: BODRESET_CLREN Mask */ +#define EVENTROUTER_CLR_EN_DPDRESET_CLREN_Pos 21 /*!< EVENTROUTER CLR_EN: DPDRESET_CLREN Position */ +#define EVENTROUTER_CLR_EN_DPDRESET_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_DPDRESET_CLREN_Pos) /*!< EVENTROUTER CLR_EN: DPDRESET_CLREN Mask */ + +/* ----------------------------- EVENTROUTER_SET_EN ----------------------------- */ +#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos 0 /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Position */ +#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Mask */ +#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos 1 /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Position */ +#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Mask */ +#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos 2 /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Position */ +#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Mask */ +#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos 3 /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Position */ +#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Mask */ +#define EVENTROUTER_SET_EN_ATIMER_SETEN_Pos 4 /*!< EVENTROUTER SET_EN: ATIMER_SETEN Position */ +#define EVENTROUTER_SET_EN_ATIMER_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_ATIMER_SETEN_Pos) /*!< EVENTROUTER SET_EN: ATIMER_SETEN Mask */ +#define EVENTROUTER_SET_EN_RTC_SETEN_Pos 5 /*!< EVENTROUTER SET_EN: RTC_SETEN Position */ +#define EVENTROUTER_SET_EN_RTC_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_RTC_SETEN_Pos) /*!< EVENTROUTER SET_EN: RTC_SETEN Mask */ +#define EVENTROUTER_SET_EN_BOD_SETEN_Pos 6 /*!< EVENTROUTER SET_EN: BOD_SETEN Position */ +#define EVENTROUTER_SET_EN_BOD_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_BOD_SETEN_Pos) /*!< EVENTROUTER SET_EN: BOD_SETEN Mask */ +#define EVENTROUTER_SET_EN_WWDT_SETEN_Pos 7 /*!< EVENTROUTER SET_EN: WWDT_SETEN Position */ +#define EVENTROUTER_SET_EN_WWDT_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WWDT_SETEN_Pos) /*!< EVENTROUTER SET_EN: WWDT_SETEN Mask */ +#define EVENTROUTER_SET_EN_ETH_SETEN_Pos 8 /*!< EVENTROUTER SET_EN: ETH_SETEN Position */ +#define EVENTROUTER_SET_EN_ETH_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_ETH_SETEN_Pos) /*!< EVENTROUTER SET_EN: ETH_SETEN Mask */ +#define EVENTROUTER_SET_EN_USB0_SETEN_Pos 9 /*!< EVENTROUTER SET_EN: USB0_SETEN Position */ +#define EVENTROUTER_SET_EN_USB0_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_USB0_SETEN_Pos) /*!< EVENTROUTER SET_EN: USB0_SETEN Mask */ +#define EVENTROUTER_SET_EN_USB1_SETEN_Pos 10 /*!< EVENTROUTER SET_EN: USB1_SETEN Position */ +#define EVENTROUTER_SET_EN_USB1_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_USB1_SETEN_Pos) /*!< EVENTROUTER SET_EN: USB1_SETEN Mask */ +#define EVENTROUTER_SET_EN_SDMMC_SETEN_Pos 11 /*!< EVENTROUTER SET_EN: SDMMC_SETEN Position */ +#define EVENTROUTER_SET_EN_SDMMC_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_SDMMC_SETEN_Pos) /*!< EVENTROUTER SET_EN: SDMMC_SETEN Mask */ +#define EVENTROUTER_SET_EN_CAN_SETEN_Pos 12 /*!< EVENTROUTER SET_EN: CAN_SETEN Position */ +#define EVENTROUTER_SET_EN_CAN_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_CAN_SETEN_Pos) /*!< EVENTROUTER SET_EN: CAN_SETEN Mask */ +#define EVENTROUTER_SET_EN_TIM2_SETEN_Pos 13 /*!< EVENTROUTER SET_EN: TIM2_SETEN Position */ +#define EVENTROUTER_SET_EN_TIM2_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_TIM2_SETEN_Pos) /*!< EVENTROUTER SET_EN: TIM2_SETEN Mask */ +#define EVENTROUTER_SET_EN_TIM6_SETEN_Pos 14 /*!< EVENTROUTER SET_EN: TIM6_SETEN Position */ +#define EVENTROUTER_SET_EN_TIM6_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_TIM6_SETEN_Pos) /*!< EVENTROUTER SET_EN: TIM6_SETEN Mask */ +#define EVENTROUTER_SET_EN_QEI_SETEN_Pos 15 /*!< EVENTROUTER SET_EN: QEI_SETEN Position */ +#define EVENTROUTER_SET_EN_QEI_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_QEI_SETEN_Pos) /*!< EVENTROUTER SET_EN: QEI_SETEN Mask */ +#define EVENTROUTER_SET_EN_TIM14_SETEN_Pos 16 /*!< EVENTROUTER SET_EN: TIM14_SETEN Position */ +#define EVENTROUTER_SET_EN_TIM14_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_TIM14_SETEN_Pos) /*!< EVENTROUTER SET_EN: TIM14_SETEN Mask */ +#define EVENTROUTER_SET_EN_RESET_SETEN_Pos 19 /*!< EVENTROUTER SET_EN: RESET_SETEN Position */ +#define EVENTROUTER_SET_EN_RESET_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_RESET_SETEN_Pos) /*!< EVENTROUTER SET_EN: RESET_SETEN Mask */ +#define EVENTROUTER_SET_EN_BODRESET_SETEN_Pos 20 /*!< EVENTROUTER SET_EN: BODRESET_SETEN Position */ +#define EVENTROUTER_SET_EN_BODRESET_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_BODRESET_SETEN_Pos) /*!< EVENTROUTER SET_EN: BODRESET_SETEN Mask */ +#define EVENTROUTER_SET_EN_DPDRESET_SETEN_Pos 21 /*!< EVENTROUTER SET_EN: DPDRESET_SETEN Position */ +#define EVENTROUTER_SET_EN_DPDRESET_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_DPDRESET_SETEN_Pos) /*!< EVENTROUTER SET_EN: DPDRESET_SETEN Mask */ + +/* ----------------------------- EVENTROUTER_STATUS ----------------------------- */ +#define EVENTROUTER_STATUS_WAKEUP0_ST_Pos 0 /*!< EVENTROUTER STATUS: WAKEUP0_ST Position */ +#define EVENTROUTER_STATUS_WAKEUP0_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP0_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP0_ST Mask */ +#define EVENTROUTER_STATUS_WAKEUP1_ST_Pos 1 /*!< EVENTROUTER STATUS: WAKEUP1_ST Position */ +#define EVENTROUTER_STATUS_WAKEUP1_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP1_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP1_ST Mask */ +#define EVENTROUTER_STATUS_WAKEUP2_ST_Pos 2 /*!< EVENTROUTER STATUS: WAKEUP2_ST Position */ +#define EVENTROUTER_STATUS_WAKEUP2_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP2_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP2_ST Mask */ +#define EVENTROUTER_STATUS_WAKEUP3_ST_Pos 3 /*!< EVENTROUTER STATUS: WAKEUP3_ST Position */ +#define EVENTROUTER_STATUS_WAKEUP3_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP3_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP3_ST Mask */ +#define EVENTROUTER_STATUS_ATIMER_ST_Pos 4 /*!< EVENTROUTER STATUS: ATIMER_ST Position */ +#define EVENTROUTER_STATUS_ATIMER_ST_Msk (0x01UL << EVENTROUTER_STATUS_ATIMER_ST_Pos) /*!< EVENTROUTER STATUS: ATIMER_ST Mask */ +#define EVENTROUTER_STATUS_RTC_ST_Pos 5 /*!< EVENTROUTER STATUS: RTC_ST Position */ +#define EVENTROUTER_STATUS_RTC_ST_Msk (0x01UL << EVENTROUTER_STATUS_RTC_ST_Pos) /*!< EVENTROUTER STATUS: RTC_ST Mask */ +#define EVENTROUTER_STATUS_BOD_ST_Pos 6 /*!< EVENTROUTER STATUS: BOD_ST Position */ +#define EVENTROUTER_STATUS_BOD_ST_Msk (0x01UL << EVENTROUTER_STATUS_BOD_ST_Pos) /*!< EVENTROUTER STATUS: BOD_ST Mask */ +#define EVENTROUTER_STATUS_WWDT_ST_Pos 7 /*!< EVENTROUTER STATUS: WWDT_ST Position */ +#define EVENTROUTER_STATUS_WWDT_ST_Msk (0x01UL << EVENTROUTER_STATUS_WWDT_ST_Pos) /*!< EVENTROUTER STATUS: WWDT_ST Mask */ +#define EVENTROUTER_STATUS_ETH_ST_Pos 8 /*!< EVENTROUTER STATUS: ETH_ST Position */ +#define EVENTROUTER_STATUS_ETH_ST_Msk (0x01UL << EVENTROUTER_STATUS_ETH_ST_Pos) /*!< EVENTROUTER STATUS: ETH_ST Mask */ +#define EVENTROUTER_STATUS_USB0_ST_Pos 9 /*!< EVENTROUTER STATUS: USB0_ST Position */ +#define EVENTROUTER_STATUS_USB0_ST_Msk (0x01UL << EVENTROUTER_STATUS_USB0_ST_Pos) /*!< EVENTROUTER STATUS: USB0_ST Mask */ +#define EVENTROUTER_STATUS_USB1_ST_Pos 10 /*!< EVENTROUTER STATUS: USB1_ST Position */ +#define EVENTROUTER_STATUS_USB1_ST_Msk (0x01UL << EVENTROUTER_STATUS_USB1_ST_Pos) /*!< EVENTROUTER STATUS: USB1_ST Mask */ +#define EVENTROUTER_STATUS_SDMMC_ST_Pos 11 /*!< EVENTROUTER STATUS: SDMMC_ST Position */ +#define EVENTROUTER_STATUS_SDMMC_ST_Msk (0x01UL << EVENTROUTER_STATUS_SDMMC_ST_Pos) /*!< EVENTROUTER STATUS: SDMMC_ST Mask */ +#define EVENTROUTER_STATUS_CAN_ST_Pos 12 /*!< EVENTROUTER STATUS: CAN_ST Position */ +#define EVENTROUTER_STATUS_CAN_ST_Msk (0x01UL << EVENTROUTER_STATUS_CAN_ST_Pos) /*!< EVENTROUTER STATUS: CAN_ST Mask */ +#define EVENTROUTER_STATUS_TIM2_ST_Pos 13 /*!< EVENTROUTER STATUS: TIM2_ST Position */ +#define EVENTROUTER_STATUS_TIM2_ST_Msk (0x01UL << EVENTROUTER_STATUS_TIM2_ST_Pos) /*!< EVENTROUTER STATUS: TIM2_ST Mask */ +#define EVENTROUTER_STATUS_TIM6_ST_Pos 14 /*!< EVENTROUTER STATUS: TIM6_ST Position */ +#define EVENTROUTER_STATUS_TIM6_ST_Msk (0x01UL << EVENTROUTER_STATUS_TIM6_ST_Pos) /*!< EVENTROUTER STATUS: TIM6_ST Mask */ +#define EVENTROUTER_STATUS_QEI_ST_Pos 15 /*!< EVENTROUTER STATUS: QEI_ST Position */ +#define EVENTROUTER_STATUS_QEI_ST_Msk (0x01UL << EVENTROUTER_STATUS_QEI_ST_Pos) /*!< EVENTROUTER STATUS: QEI_ST Mask */ +#define EVENTROUTER_STATUS_TIM14_ST_Pos 16 /*!< EVENTROUTER STATUS: TIM14_ST Position */ +#define EVENTROUTER_STATUS_TIM14_ST_Msk (0x01UL << EVENTROUTER_STATUS_TIM14_ST_Pos) /*!< EVENTROUTER STATUS: TIM14_ST Mask */ +#define EVENTROUTER_STATUS_RESET_ST_Pos 19 /*!< EVENTROUTER STATUS: RESET_ST Position */ +#define EVENTROUTER_STATUS_RESET_ST_Msk (0x01UL << EVENTROUTER_STATUS_RESET_ST_Pos) /*!< EVENTROUTER STATUS: RESET_ST Mask */ +#define EVENTROUTER_STATUS_BODRESET_ST_Pos 20 /*!< EVENTROUTER STATUS: BODRESET_ST Position */ +#define EVENTROUTER_STATUS_BODRESET_ST_Msk (0x01UL << EVENTROUTER_STATUS_BODRESET_ST_Pos) /*!< EVENTROUTER STATUS: BODRESET_ST Mask */ +#define EVENTROUTER_STATUS_DPDRESET_ST_Pos 21 /*!< EVENTROUTER STATUS: DPDRESET_ST Position */ +#define EVENTROUTER_STATUS_DPDRESET_ST_Msk (0x01UL << EVENTROUTER_STATUS_DPDRESET_ST_Pos) /*!< EVENTROUTER STATUS: DPDRESET_ST Mask */ + +/* ----------------------------- EVENTROUTER_ENABLE ----------------------------- */ +#define EVENTROUTER_ENABLE_WAKEUP0_EN_Pos 0 /*!< EVENTROUTER ENABLE: WAKEUP0_EN Position */ +#define EVENTROUTER_ENABLE_WAKEUP0_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP0_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP0_EN Mask */ +#define EVENTROUTER_ENABLE_WAKEUP1_EN_Pos 1 /*!< EVENTROUTER ENABLE: WAKEUP1_EN Position */ +#define EVENTROUTER_ENABLE_WAKEUP1_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP1_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP1_EN Mask */ +#define EVENTROUTER_ENABLE_WAKEUP2_EN_Pos 2 /*!< EVENTROUTER ENABLE: WAKEUP2_EN Position */ +#define EVENTROUTER_ENABLE_WAKEUP2_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP2_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP2_EN Mask */ +#define EVENTROUTER_ENABLE_WAKEUP3_EN_Pos 3 /*!< EVENTROUTER ENABLE: WAKEUP3_EN Position */ +#define EVENTROUTER_ENABLE_WAKEUP3_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP3_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP3_EN Mask */ +#define EVENTROUTER_ENABLE_ATIMER_EN_Pos 4 /*!< EVENTROUTER ENABLE: ATIMER_EN Position */ +#define EVENTROUTER_ENABLE_ATIMER_EN_Msk (0x01UL << EVENTROUTER_ENABLE_ATIMER_EN_Pos) /*!< EVENTROUTER ENABLE: ATIMER_EN Mask */ +#define EVENTROUTER_ENABLE_RTC_EN_Pos 5 /*!< EVENTROUTER ENABLE: RTC_EN Position */ +#define EVENTROUTER_ENABLE_RTC_EN_Msk (0x01UL << EVENTROUTER_ENABLE_RTC_EN_Pos) /*!< EVENTROUTER ENABLE: RTC_EN Mask */ +#define EVENTROUTER_ENABLE_BOD_EN_Pos 6 /*!< EVENTROUTER ENABLE: BOD_EN Position */ +#define EVENTROUTER_ENABLE_BOD_EN_Msk (0x01UL << EVENTROUTER_ENABLE_BOD_EN_Pos) /*!< EVENTROUTER ENABLE: BOD_EN Mask */ +#define EVENTROUTER_ENABLE_WWDT_EN_Pos 7 /*!< EVENTROUTER ENABLE: WWDT_EN Position */ +#define EVENTROUTER_ENABLE_WWDT_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WWDT_EN_Pos) /*!< EVENTROUTER ENABLE: WWDT_EN Mask */ +#define EVENTROUTER_ENABLE_ETH_EN_Pos 8 /*!< EVENTROUTER ENABLE: ETH_EN Position */ +#define EVENTROUTER_ENABLE_ETH_EN_Msk (0x01UL << EVENTROUTER_ENABLE_ETH_EN_Pos) /*!< EVENTROUTER ENABLE: ETH_EN Mask */ +#define EVENTROUTER_ENABLE_USB0_EN_Pos 9 /*!< EVENTROUTER ENABLE: USB0_EN Position */ +#define EVENTROUTER_ENABLE_USB0_EN_Msk (0x01UL << EVENTROUTER_ENABLE_USB0_EN_Pos) /*!< EVENTROUTER ENABLE: USB0_EN Mask */ +#define EVENTROUTER_ENABLE_USB1_EN_Pos 10 /*!< EVENTROUTER ENABLE: USB1_EN Position */ +#define EVENTROUTER_ENABLE_USB1_EN_Msk (0x01UL << EVENTROUTER_ENABLE_USB1_EN_Pos) /*!< EVENTROUTER ENABLE: USB1_EN Mask */ +#define EVENTROUTER_ENABLE_SDMMC_EN_Pos 11 /*!< EVENTROUTER ENABLE: SDMMC_EN Position */ +#define EVENTROUTER_ENABLE_SDMMC_EN_Msk (0x01UL << EVENTROUTER_ENABLE_SDMMC_EN_Pos) /*!< EVENTROUTER ENABLE: SDMMC_EN Mask */ +#define EVENTROUTER_ENABLE_CAN_EN_Pos 12 /*!< EVENTROUTER ENABLE: CAN_EN Position */ +#define EVENTROUTER_ENABLE_CAN_EN_Msk (0x01UL << EVENTROUTER_ENABLE_CAN_EN_Pos) /*!< EVENTROUTER ENABLE: CAN_EN Mask */ +#define EVENTROUTER_ENABLE_TIM2_EN_Pos 13 /*!< EVENTROUTER ENABLE: TIM2_EN Position */ +#define EVENTROUTER_ENABLE_TIM2_EN_Msk (0x01UL << EVENTROUTER_ENABLE_TIM2_EN_Pos) /*!< EVENTROUTER ENABLE: TIM2_EN Mask */ +#define EVENTROUTER_ENABLE_TIM6_EN_Pos 14 /*!< EVENTROUTER ENABLE: TIM6_EN Position */ +#define EVENTROUTER_ENABLE_TIM6_EN_Msk (0x01UL << EVENTROUTER_ENABLE_TIM6_EN_Pos) /*!< EVENTROUTER ENABLE: TIM6_EN Mask */ +#define EVENTROUTER_ENABLE_QEI_EN_Pos 15 /*!< EVENTROUTER ENABLE: QEI_EN Position */ +#define EVENTROUTER_ENABLE_QEI_EN_Msk (0x01UL << EVENTROUTER_ENABLE_QEI_EN_Pos) /*!< EVENTROUTER ENABLE: QEI_EN Mask */ +#define EVENTROUTER_ENABLE_TIM14_EN_Pos 16 /*!< EVENTROUTER ENABLE: TIM14_EN Position */ +#define EVENTROUTER_ENABLE_TIM14_EN_Msk (0x01UL << EVENTROUTER_ENABLE_TIM14_EN_Pos) /*!< EVENTROUTER ENABLE: TIM14_EN Mask */ +#define EVENTROUTER_ENABLE_RESET_EN_Pos 19 /*!< EVENTROUTER ENABLE: RESET_EN Position */ +#define EVENTROUTER_ENABLE_RESET_EN_Msk (0x01UL << EVENTROUTER_ENABLE_RESET_EN_Pos) /*!< EVENTROUTER ENABLE: RESET_EN Mask */ +#define EVENTROUTER_ENABLE_BODRESET_EN_Pos 20 /*!< EVENTROUTER ENABLE: BODRESET_EN Position */ +#define EVENTROUTER_ENABLE_BODRESET_EN_Msk (0x01UL << EVENTROUTER_ENABLE_BODRESET_EN_Pos) /*!< EVENTROUTER ENABLE: BODRESET_EN Mask */ +#define EVENTROUTER_ENABLE_DPDRESET_EN_Pos 21 /*!< EVENTROUTER ENABLE: DPDRESET_EN Position */ +#define EVENTROUTER_ENABLE_DPDRESET_EN_Msk (0x01UL << EVENTROUTER_ENABLE_DPDRESET_EN_Pos) /*!< EVENTROUTER ENABLE: DPDRESET_EN Mask */ + +/* ---------------------------- EVENTROUTER_CLR_STAT ---------------------------- */ +#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos 0 /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Position */ +#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Mask */ +#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos 1 /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Position */ +#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Mask */ +#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos 2 /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Position */ +#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Mask */ +#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos 3 /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Position */ +#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Mask */ +#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos 4 /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Position */ +#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Mask */ +#define EVENTROUTER_CLR_STAT_RTC_CLRST_Pos 5 /*!< EVENTROUTER CLR_STAT: RTC_CLRST Position */ +#define EVENTROUTER_CLR_STAT_RTC_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_RTC_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: RTC_CLRST Mask */ +#define EVENTROUTER_CLR_STAT_BOD_CLRST_Pos 6 /*!< EVENTROUTER CLR_STAT: BOD_CLRST Position */ +#define EVENTROUTER_CLR_STAT_BOD_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_BOD_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: BOD_CLRST Mask */ +#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos 7 /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Position */ +#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Mask */ +#define EVENTROUTER_CLR_STAT_ETH_CLRST_Pos 8 /*!< EVENTROUTER CLR_STAT: ETH_CLRST Position */ +#define EVENTROUTER_CLR_STAT_ETH_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_ETH_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: ETH_CLRST Mask */ +#define EVENTROUTER_CLR_STAT_USB0_CLRST_Pos 9 /*!< EVENTROUTER CLR_STAT: USB0_CLRST Position */ +#define EVENTROUTER_CLR_STAT_USB0_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_USB0_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: USB0_CLRST Mask */ +#define EVENTROUTER_CLR_STAT_USB1_CLRST_Pos 10 /*!< EVENTROUTER CLR_STAT: USB1_CLRST Position */ +#define EVENTROUTER_CLR_STAT_USB1_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_USB1_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: USB1_CLRST Mask */ +#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos 11 /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Position */ +#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Mask */ +#define EVENTROUTER_CLR_STAT_CAN_CLRST_Pos 12 /*!< EVENTROUTER CLR_STAT: CAN_CLRST Position */ +#define EVENTROUTER_CLR_STAT_CAN_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_CAN_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: CAN_CLRST Mask */ +#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos 13 /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Position */ +#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Mask */ +#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos 14 /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Position */ +#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Mask */ +#define EVENTROUTER_CLR_STAT_QEI_CLRST_Pos 15 /*!< EVENTROUTER CLR_STAT: QEI_CLRST Position */ +#define EVENTROUTER_CLR_STAT_QEI_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_QEI_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: QEI_CLRST Mask */ +#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos 16 /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Position */ +#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Mask */ +#define EVENTROUTER_CLR_STAT_RESET_CLRST_Pos 19 /*!< EVENTROUTER CLR_STAT: RESET_CLRST Position */ +#define EVENTROUTER_CLR_STAT_RESET_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_RESET_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: RESET_CLRST Mask */ +#define EVENTROUTER_CLR_STAT_BODRESET_CLRST_Pos 20 /*!< EVENTROUTER CLR_STAT: BODRESET_CLRST Position */ +#define EVENTROUTER_CLR_STAT_BODRESET_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_BODRESET_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: BODRESET_CLRST Mask */ +#define EVENTROUTER_CLR_STAT_DPDRESET_CLRST_Pos 21 /*!< EVENTROUTER CLR_STAT: DPDRESET_CLRST Position */ +#define EVENTROUTER_CLR_STAT_DPDRESET_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_DPDRESET_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: DPDRESET_CLRST Mask */ + +/* ---------------------------- EVENTROUTER_SET_STAT ---------------------------- */ +#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos 0 /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Position */ +#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Mask */ +#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos 1 /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Position */ +#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Mask */ +#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos 2 /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Position */ +#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Mask */ +#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos 3 /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Position */ +#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Mask */ +#define EVENTROUTER_SET_STAT_ATIMER_SETST_Pos 4 /*!< EVENTROUTER SET_STAT: ATIMER_SETST Position */ +#define EVENTROUTER_SET_STAT_ATIMER_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_ATIMER_SETST_Pos) /*!< EVENTROUTER SET_STAT: ATIMER_SETST Mask */ +#define EVENTROUTER_SET_STAT_RTC_SETST_Pos 5 /*!< EVENTROUTER SET_STAT: RTC_SETST Position */ +#define EVENTROUTER_SET_STAT_RTC_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_RTC_SETST_Pos) /*!< EVENTROUTER SET_STAT: RTC_SETST Mask */ +#define EVENTROUTER_SET_STAT_BOD_SETST_Pos 6 /*!< EVENTROUTER SET_STAT: BOD_SETST Position */ +#define EVENTROUTER_SET_STAT_BOD_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_BOD_SETST_Pos) /*!< EVENTROUTER SET_STAT: BOD_SETST Mask */ +#define EVENTROUTER_SET_STAT_WWDT_SETST_Pos 7 /*!< EVENTROUTER SET_STAT: WWDT_SETST Position */ +#define EVENTROUTER_SET_STAT_WWDT_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WWDT_SETST_Pos) /*!< EVENTROUTER SET_STAT: WWDT_SETST Mask */ +#define EVENTROUTER_SET_STAT_ETH_SETST_Pos 8 /*!< EVENTROUTER SET_STAT: ETH_SETST Position */ +#define EVENTROUTER_SET_STAT_ETH_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_ETH_SETST_Pos) /*!< EVENTROUTER SET_STAT: ETH_SETST Mask */ +#define EVENTROUTER_SET_STAT_USB0_SETST_Pos 9 /*!< EVENTROUTER SET_STAT: USB0_SETST Position */ +#define EVENTROUTER_SET_STAT_USB0_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_USB0_SETST_Pos) /*!< EVENTROUTER SET_STAT: USB0_SETST Mask */ +#define EVENTROUTER_SET_STAT_USB1_SETST_Pos 10 /*!< EVENTROUTER SET_STAT: USB1_SETST Position */ +#define EVENTROUTER_SET_STAT_USB1_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_USB1_SETST_Pos) /*!< EVENTROUTER SET_STAT: USB1_SETST Mask */ +#define EVENTROUTER_SET_STAT_SDMMC_SETST_Pos 11 /*!< EVENTROUTER SET_STAT: SDMMC_SETST Position */ +#define EVENTROUTER_SET_STAT_SDMMC_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_SDMMC_SETST_Pos) /*!< EVENTROUTER SET_STAT: SDMMC_SETST Mask */ +#define EVENTROUTER_SET_STAT_CAN_SETST_Pos 12 /*!< EVENTROUTER SET_STAT: CAN_SETST Position */ +#define EVENTROUTER_SET_STAT_CAN_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_CAN_SETST_Pos) /*!< EVENTROUTER SET_STAT: CAN_SETST Mask */ +#define EVENTROUTER_SET_STAT_TIM2_SETST_Pos 13 /*!< EVENTROUTER SET_STAT: TIM2_SETST Position */ +#define EVENTROUTER_SET_STAT_TIM2_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_TIM2_SETST_Pos) /*!< EVENTROUTER SET_STAT: TIM2_SETST Mask */ +#define EVENTROUTER_SET_STAT_TIM6_SETST_Pos 14 /*!< EVENTROUTER SET_STAT: TIM6_SETST Position */ +#define EVENTROUTER_SET_STAT_TIM6_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_TIM6_SETST_Pos) /*!< EVENTROUTER SET_STAT: TIM6_SETST Mask */ +#define EVENTROUTER_SET_STAT_QEI_SETST_Pos 15 /*!< EVENTROUTER SET_STAT: QEI_SETST Position */ +#define EVENTROUTER_SET_STAT_QEI_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_QEI_SETST_Pos) /*!< EVENTROUTER SET_STAT: QEI_SETST Mask */ +#define EVENTROUTER_SET_STAT_TIM14_SETST_Pos 16 /*!< EVENTROUTER SET_STAT: TIM14_SETST Position */ +#define EVENTROUTER_SET_STAT_TIM14_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_TIM14_SETST_Pos) /*!< EVENTROUTER SET_STAT: TIM14_SETST Mask */ +#define EVENTROUTER_SET_STAT_RESET_SETST_Pos 19 /*!< EVENTROUTER SET_STAT: RESET_SETST Position */ +#define EVENTROUTER_SET_STAT_RESET_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_RESET_SETST_Pos) /*!< EVENTROUTER SET_STAT: RESET_SETST Mask */ +#define EVENTROUTER_SET_STAT_BODRESET_SETST_Pos 20 /*!< EVENTROUTER SET_STAT: BODRESET_SETST Position */ +#define EVENTROUTER_SET_STAT_BODRESET_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_BODRESET_SETST_Pos) /*!< EVENTROUTER SET_STAT: BODRESET_SETST Mask */ +#define EVENTROUTER_SET_STAT_DPDRESET_SETST_Pos 21 /*!< EVENTROUTER SET_STAT: DPDRESET_SETST Position */ +#define EVENTROUTER_SET_STAT_DPDRESET_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_DPDRESET_SETST_Pos) /*!< EVENTROUTER SET_STAT: DPDRESET_SETST Mask */ + + +/* ================================================================================ */ +/* ================ struct 'RTC' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------------- RTC_ILR ---------------------------------- */ +#define RTC_ILR_RTCCIF_Pos 0 /*!< RTC ILR: RTCCIF Position */ +#define RTC_ILR_RTCCIF_Msk (0x01UL << RTC_ILR_RTCCIF_Pos) /*!< RTC ILR: RTCCIF Mask */ +#define RTC_ILR_RTCALF_Pos 1 /*!< RTC ILR: RTCALF Position */ +#define RTC_ILR_RTCALF_Msk (0x01UL << RTC_ILR_RTCALF_Pos) /*!< RTC ILR: RTCALF Mask */ + +/* ----------------------------------- RTC_CCR ---------------------------------- */ +#define RTC_CCR_CLKEN_Pos 0 /*!< RTC CCR: CLKEN Position */ +#define RTC_CCR_CLKEN_Msk (0x01UL << RTC_CCR_CLKEN_Pos) /*!< RTC CCR: CLKEN Mask */ +#define RTC_CCR_CTCRST_Pos 1 /*!< RTC CCR: CTCRST Position */ +#define RTC_CCR_CTCRST_Msk (0x01UL << RTC_CCR_CTCRST_Pos) /*!< RTC CCR: CTCRST Mask */ +#define RTC_CCR_CCALEN_Pos 4 /*!< RTC CCR: CCALEN Position */ +#define RTC_CCR_CCALEN_Msk (0x01UL << RTC_CCR_CCALEN_Pos) /*!< RTC CCR: CCALEN Mask */ + +/* ---------------------------------- RTC_CIIR ---------------------------------- */ +#define RTC_CIIR_IMSEC_Pos 0 /*!< RTC CIIR: IMSEC Position */ +#define RTC_CIIR_IMSEC_Msk (0x01UL << RTC_CIIR_IMSEC_Pos) /*!< RTC CIIR: IMSEC Mask */ +#define RTC_CIIR_IMMIN_Pos 1 /*!< RTC CIIR: IMMIN Position */ +#define RTC_CIIR_IMMIN_Msk (0x01UL << RTC_CIIR_IMMIN_Pos) /*!< RTC CIIR: IMMIN Mask */ +#define RTC_CIIR_IMHOUR_Pos 2 /*!< RTC CIIR: IMHOUR Position */ +#define RTC_CIIR_IMHOUR_Msk (0x01UL << RTC_CIIR_IMHOUR_Pos) /*!< RTC CIIR: IMHOUR Mask */ +#define RTC_CIIR_IMDOM_Pos 3 /*!< RTC CIIR: IMDOM Position */ +#define RTC_CIIR_IMDOM_Msk (0x01UL << RTC_CIIR_IMDOM_Pos) /*!< RTC CIIR: IMDOM Mask */ +#define RTC_CIIR_IMDOW_Pos 4 /*!< RTC CIIR: IMDOW Position */ +#define RTC_CIIR_IMDOW_Msk (0x01UL << RTC_CIIR_IMDOW_Pos) /*!< RTC CIIR: IMDOW Mask */ +#define RTC_CIIR_IMDOY_Pos 5 /*!< RTC CIIR: IMDOY Position */ +#define RTC_CIIR_IMDOY_Msk (0x01UL << RTC_CIIR_IMDOY_Pos) /*!< RTC CIIR: IMDOY Mask */ +#define RTC_CIIR_IMMON_Pos 6 /*!< RTC CIIR: IMMON Position */ +#define RTC_CIIR_IMMON_Msk (0x01UL << RTC_CIIR_IMMON_Pos) /*!< RTC CIIR: IMMON Mask */ +#define RTC_CIIR_IMYEAR_Pos 7 /*!< RTC CIIR: IMYEAR Position */ +#define RTC_CIIR_IMYEAR_Msk (0x01UL << RTC_CIIR_IMYEAR_Pos) /*!< RTC CIIR: IMYEAR Mask */ + +/* ----------------------------------- RTC_AMR ---------------------------------- */ +#define RTC_AMR_AMRSEC_Pos 0 /*!< RTC AMR: AMRSEC Position */ +#define RTC_AMR_AMRSEC_Msk (0x01UL << RTC_AMR_AMRSEC_Pos) /*!< RTC AMR: AMRSEC Mask */ +#define RTC_AMR_AMRMIN_Pos 1 /*!< RTC AMR: AMRMIN Position */ +#define RTC_AMR_AMRMIN_Msk (0x01UL << RTC_AMR_AMRMIN_Pos) /*!< RTC AMR: AMRMIN Mask */ +#define RTC_AMR_AMRHOUR_Pos 2 /*!< RTC AMR: AMRHOUR Position */ +#define RTC_AMR_AMRHOUR_Msk (0x01UL << RTC_AMR_AMRHOUR_Pos) /*!< RTC AMR: AMRHOUR Mask */ +#define RTC_AMR_AMRDOM_Pos 3 /*!< RTC AMR: AMRDOM Position */ +#define RTC_AMR_AMRDOM_Msk (0x01UL << RTC_AMR_AMRDOM_Pos) /*!< RTC AMR: AMRDOM Mask */ +#define RTC_AMR_AMRDOW_Pos 4 /*!< RTC AMR: AMRDOW Position */ +#define RTC_AMR_AMRDOW_Msk (0x01UL << RTC_AMR_AMRDOW_Pos) /*!< RTC AMR: AMRDOW Mask */ +#define RTC_AMR_AMRDOY_Pos 5 /*!< RTC AMR: AMRDOY Position */ +#define RTC_AMR_AMRDOY_Msk (0x01UL << RTC_AMR_AMRDOY_Pos) /*!< RTC AMR: AMRDOY Mask */ +#define RTC_AMR_AMRMON_Pos 6 /*!< RTC AMR: AMRMON Position */ +#define RTC_AMR_AMRMON_Msk (0x01UL << RTC_AMR_AMRMON_Pos) /*!< RTC AMR: AMRMON Mask */ +#define RTC_AMR_AMRYEAR_Pos 7 /*!< RTC AMR: AMRYEAR Position */ +#define RTC_AMR_AMRYEAR_Msk (0x01UL << RTC_AMR_AMRYEAR_Pos) /*!< RTC AMR: AMRYEAR Mask */ + +/* --------------------------------- RTC_CTIME0 --------------------------------- */ +#define RTC_CTIME0_SECONDS_Pos 0 /*!< RTC CTIME0: SECONDS Position */ +#define RTC_CTIME0_SECONDS_Msk (0x3fUL << RTC_CTIME0_SECONDS_Pos) /*!< RTC CTIME0: SECONDS Mask */ +#define RTC_CTIME0_MINUTES_Pos 8 /*!< RTC CTIME0: MINUTES Position */ +#define RTC_CTIME0_MINUTES_Msk (0x3fUL << RTC_CTIME0_MINUTES_Pos) /*!< RTC CTIME0: MINUTES Mask */ +#define RTC_CTIME0_HOURS_Pos 16 /*!< RTC CTIME0: HOURS Position */ +#define RTC_CTIME0_HOURS_Msk (0x1fUL << RTC_CTIME0_HOURS_Pos) /*!< RTC CTIME0: HOURS Mask */ +#define RTC_CTIME0_DOW_Pos 24 /*!< RTC CTIME0: DOW Position */ +#define RTC_CTIME0_DOW_Msk (0x07UL << RTC_CTIME0_DOW_Pos) /*!< RTC CTIME0: DOW Mask */ + +/* --------------------------------- RTC_CTIME1 --------------------------------- */ +#define RTC_CTIME1_DOM_Pos 0 /*!< RTC CTIME1: DOM Position */ +#define RTC_CTIME1_DOM_Msk (0x1fUL << RTC_CTIME1_DOM_Pos) /*!< RTC CTIME1: DOM Mask */ +#define RTC_CTIME1_MONTH_Pos 8 /*!< RTC CTIME1: MONTH Position */ +#define RTC_CTIME1_MONTH_Msk (0x0fUL << RTC_CTIME1_MONTH_Pos) /*!< RTC CTIME1: MONTH Mask */ +#define RTC_CTIME1_YEAR_Pos 16 /*!< RTC CTIME1: YEAR Position */ +#define RTC_CTIME1_YEAR_Msk (0x00000fffUL << RTC_CTIME1_YEAR_Pos) /*!< RTC CTIME1: YEAR Mask */ + +/* --------------------------------- RTC_CTIME2 --------------------------------- */ +#define RTC_CTIME2_DOY_Pos 0 /*!< RTC CTIME2: DOY Position */ +#define RTC_CTIME2_DOY_Msk (0x00000fffUL << RTC_CTIME2_DOY_Pos) /*!< RTC CTIME2: DOY Mask */ + +/* ----------------------------------- RTC_SEC ---------------------------------- */ +#define RTC_SEC_SECONDS_Pos 0 /*!< RTC SEC: SECONDS Position */ +#define RTC_SEC_SECONDS_Msk (0x3fUL << RTC_SEC_SECONDS_Pos) /*!< RTC SEC: SECONDS Mask */ + +/* ----------------------------------- RTC_MIN ---------------------------------- */ +#define RTC_MIN_MINUTES_Pos 0 /*!< RTC MIN: MINUTES Position */ +#define RTC_MIN_MINUTES_Msk (0x3fUL << RTC_MIN_MINUTES_Pos) /*!< RTC MIN: MINUTES Mask */ + +/* ----------------------------------- RTC_HRS ---------------------------------- */ +#define RTC_HRS_HOURS_Pos 0 /*!< RTC HRS: HOURS Position */ +#define RTC_HRS_HOURS_Msk (0x1fUL << RTC_HRS_HOURS_Pos) /*!< RTC HRS: HOURS Mask */ + +/* ----------------------------------- RTC_DOM ---------------------------------- */ +#define RTC_DOM_DOM_Pos 0 /*!< RTC DOM: DOM Position */ +#define RTC_DOM_DOM_Msk (0x1fUL << RTC_DOM_DOM_Pos) /*!< RTC DOM: DOM Mask */ + +/* ----------------------------------- RTC_DOW ---------------------------------- */ +#define RTC_DOW_DOW_Pos 0 /*!< RTC DOW: DOW Position */ +#define RTC_DOW_DOW_Msk (0x07UL << RTC_DOW_DOW_Pos) /*!< RTC DOW: DOW Mask */ + +/* ----------------------------------- RTC_DOY ---------------------------------- */ +#define RTC_DOY_DOY_Pos 0 /*!< RTC DOY: DOY Position */ +#define RTC_DOY_DOY_Msk (0x000001ffUL << RTC_DOY_DOY_Pos) /*!< RTC DOY: DOY Mask */ + +/* ---------------------------------- RTC_MONTH --------------------------------- */ +#define RTC_MONTH_MONTH_Pos 0 /*!< RTC MONTH: MONTH Position */ +#define RTC_MONTH_MONTH_Msk (0x0fUL << RTC_MONTH_MONTH_Pos) /*!< RTC MONTH: MONTH Mask */ + +/* ---------------------------------- RTC_YEAR ---------------------------------- */ +#define RTC_YEAR_YEAR_Pos 0 /*!< RTC YEAR: YEAR Position */ +#define RTC_YEAR_YEAR_Msk (0x00000fffUL << RTC_YEAR_YEAR_Pos) /*!< RTC YEAR: YEAR Mask */ + +/* ------------------------------- RTC_CALIBRATION ------------------------------ */ +#define RTC_CALIBRATION_CALVAL_Pos 0 /*!< RTC CALIBRATION: CALVAL Position */ +#define RTC_CALIBRATION_CALVAL_Msk (0x0001ffffUL << RTC_CALIBRATION_CALVAL_Pos) /*!< RTC CALIBRATION: CALVAL Mask */ +#define RTC_CALIBRATION_CALDIR_Pos 17 /*!< RTC CALIBRATION: CALDIR Position */ +#define RTC_CALIBRATION_CALDIR_Msk (0x01UL << RTC_CALIBRATION_CALDIR_Pos) /*!< RTC CALIBRATION: CALDIR Mask */ + +/* ---------------------------------- RTC_ASEC ---------------------------------- */ +#define RTC_ASEC_SECONDS_Pos 0 /*!< RTC ASEC: SECONDS Position */ +#define RTC_ASEC_SECONDS_Msk (0x3fUL << RTC_ASEC_SECONDS_Pos) /*!< RTC ASEC: SECONDS Mask */ + +/* ---------------------------------- RTC_AMIN ---------------------------------- */ +#define RTC_AMIN_MINUTES_Pos 0 /*!< RTC AMIN: MINUTES Position */ +#define RTC_AMIN_MINUTES_Msk (0x3fUL << RTC_AMIN_MINUTES_Pos) /*!< RTC AMIN: MINUTES Mask */ + +/* ---------------------------------- RTC_AHRS ---------------------------------- */ +#define RTC_AHRS_HOURS_Pos 0 /*!< RTC AHRS: HOURS Position */ +#define RTC_AHRS_HOURS_Msk (0x1fUL << RTC_AHRS_HOURS_Pos) /*!< RTC AHRS: HOURS Mask */ + +/* ---------------------------------- RTC_ADOM ---------------------------------- */ +#define RTC_ADOM_DOM_Pos 0 /*!< RTC ADOM: DOM Position */ +#define RTC_ADOM_DOM_Msk (0x1fUL << RTC_ADOM_DOM_Pos) /*!< RTC ADOM: DOM Mask */ + +/* ---------------------------------- RTC_ADOW ---------------------------------- */ +#define RTC_ADOW_DOW_Pos 0 /*!< RTC ADOW: DOW Position */ +#define RTC_ADOW_DOW_Msk (0x07UL << RTC_ADOW_DOW_Pos) /*!< RTC ADOW: DOW Mask */ + +/* ---------------------------------- RTC_ADOY ---------------------------------- */ +#define RTC_ADOY_DOY_Pos 0 /*!< RTC ADOY: DOY Position */ +#define RTC_ADOY_DOY_Msk (0x000001ffUL << RTC_ADOY_DOY_Pos) /*!< RTC ADOY: DOY Mask */ + +/* ---------------------------------- RTC_AMON ---------------------------------- */ +#define RTC_AMON_MONTH_Pos 0 /*!< RTC AMON: MONTH Position */ +#define RTC_AMON_MONTH_Msk (0x0fUL << RTC_AMON_MONTH_Pos) /*!< RTC AMON: MONTH Mask */ + +/* ---------------------------------- RTC_AYRS ---------------------------------- */ +#define RTC_AYRS_YEAR_Pos 0 /*!< RTC AYRS: YEAR Position */ +#define RTC_AYRS_YEAR_Msk (0x00000fffUL << RTC_AYRS_YEAR_Pos) /*!< RTC AYRS: YEAR Mask */ + +/* -------------------------------- RTC_ERSTATUS -------------------------------- */ +#define RTC_ERSTATUS_EV0_Pos 0 /*!< RTC ERSTATUS: EV0 Position */ +#define RTC_ERSTATUS_EV0_Msk (0x01UL << RTC_ERSTATUS_EV0_Pos) /*!< RTC ERSTATUS: EV0 Mask */ +#define RTC_ERSTATUS_EV1_Pos 1 /*!< RTC ERSTATUS: EV1 Position */ +#define RTC_ERSTATUS_EV1_Msk (0x01UL << RTC_ERSTATUS_EV1_Pos) /*!< RTC ERSTATUS: EV1 Mask */ +#define RTC_ERSTATUS_EV2_Pos 2 /*!< RTC ERSTATUS: EV2 Position */ +#define RTC_ERSTATUS_EV2_Msk (0x01UL << RTC_ERSTATUS_EV2_Pos) /*!< RTC ERSTATUS: EV2 Mask */ +#define RTC_ERSTATUS_GP_CLEARED_Pos 3 /*!< RTC ERSTATUS: GP_CLEARED Position */ +#define RTC_ERSTATUS_GP_CLEARED_Msk (0x01UL << RTC_ERSTATUS_GP_CLEARED_Pos) /*!< RTC ERSTATUS: GP_CLEARED Mask */ +#define RTC_ERSTATUS_WAKEUP_Pos 31 /*!< RTC ERSTATUS: WAKEUP Position */ +#define RTC_ERSTATUS_WAKEUP_Msk (0x01UL << RTC_ERSTATUS_WAKEUP_Pos) /*!< RTC ERSTATUS: WAKEUP Mask */ + +/* -------------------------------- RTC_ERCONTRO -------------------------------- */ +#define RTC_ERCONTRO_INTWAKE_EN0_Pos 0 /*!< RTC ERCONTRO: INTWAKE_EN0 Position */ +#define RTC_ERCONTRO_INTWAKE_EN0_Msk (0x01UL << RTC_ERCONTRO_INTWAKE_EN0_Pos) /*!< RTC ERCONTRO: INTWAKE_EN0 Mask */ +#define RTC_ERCONTRO_GPCLEAR_EN0_Pos 1 /*!< RTC ERCONTRO: GPCLEAR_EN0 Position */ +#define RTC_ERCONTRO_GPCLEAR_EN0_Msk (0x01UL << RTC_ERCONTRO_GPCLEAR_EN0_Pos) /*!< RTC ERCONTRO: GPCLEAR_EN0 Mask */ +#define RTC_ERCONTRO_POL0_Pos 2 /*!< RTC ERCONTRO: POL0 Position */ +#define RTC_ERCONTRO_POL0_Msk (0x01UL << RTC_ERCONTRO_POL0_Pos) /*!< RTC ERCONTRO: POL0 Mask */ +#define RTC_ERCONTRO_EV0_INPUT_EN_Pos 3 /*!< RTC ERCONTRO: EV0_INPUT_EN Position */ +#define RTC_ERCONTRO_EV0_INPUT_EN_Msk (0x01UL << RTC_ERCONTRO_EV0_INPUT_EN_Pos) /*!< RTC ERCONTRO: EV0_INPUT_EN Mask */ +#define RTC_ERCONTRO_INTWAKE_EN1_Pos 10 /*!< RTC ERCONTRO: INTWAKE_EN1 Position */ +#define RTC_ERCONTRO_INTWAKE_EN1_Msk (0x01UL << RTC_ERCONTRO_INTWAKE_EN1_Pos) /*!< RTC ERCONTRO: INTWAKE_EN1 Mask */ +#define RTC_ERCONTRO_GPCLEAR_EN1_Pos 11 /*!< RTC ERCONTRO: GPCLEAR_EN1 Position */ +#define RTC_ERCONTRO_GPCLEAR_EN1_Msk (0x01UL << RTC_ERCONTRO_GPCLEAR_EN1_Pos) /*!< RTC ERCONTRO: GPCLEAR_EN1 Mask */ +#define RTC_ERCONTRO_POL1_Pos 12 /*!< RTC ERCONTRO: POL1 Position */ +#define RTC_ERCONTRO_POL1_Msk (0x01UL << RTC_ERCONTRO_POL1_Pos) /*!< RTC ERCONTRO: POL1 Mask */ +#define RTC_ERCONTRO_EV1_INPUT_EN_Pos 13 /*!< RTC ERCONTRO: EV1_INPUT_EN Position */ +#define RTC_ERCONTRO_EV1_INPUT_EN_Msk (0x01UL << RTC_ERCONTRO_EV1_INPUT_EN_Pos) /*!< RTC ERCONTRO: EV1_INPUT_EN Mask */ +#define RTC_ERCONTRO_INTWAKE_EN2_Pos 20 /*!< RTC ERCONTRO: INTWAKE_EN2 Position */ +#define RTC_ERCONTRO_INTWAKE_EN2_Msk (0x01UL << RTC_ERCONTRO_INTWAKE_EN2_Pos) /*!< RTC ERCONTRO: INTWAKE_EN2 Mask */ +#define RTC_ERCONTRO_GPCLEAR_EN2_Pos 21 /*!< RTC ERCONTRO: GPCLEAR_EN2 Position */ +#define RTC_ERCONTRO_GPCLEAR_EN2_Msk (0x01UL << RTC_ERCONTRO_GPCLEAR_EN2_Pos) /*!< RTC ERCONTRO: GPCLEAR_EN2 Mask */ +#define RTC_ERCONTRO_POL2_Pos 22 /*!< RTC ERCONTRO: POL2 Position */ +#define RTC_ERCONTRO_POL2_Msk (0x01UL << RTC_ERCONTRO_POL2_Pos) /*!< RTC ERCONTRO: POL2 Mask */ +#define RTC_ERCONTRO_EV2_INPUT_EN_Pos 23 /*!< RTC ERCONTRO: EV2_INPUT_EN Position */ +#define RTC_ERCONTRO_EV2_INPUT_EN_Msk (0x01UL << RTC_ERCONTRO_EV2_INPUT_EN_Pos) /*!< RTC ERCONTRO: EV2_INPUT_EN Mask */ +#define RTC_ERCONTRO_ERMODE_Pos 30 /*!< RTC ERCONTRO: ERMODE Position */ +#define RTC_ERCONTRO_ERMODE_Msk (0x03UL << RTC_ERCONTRO_ERMODE_Pos) /*!< RTC ERCONTRO: ERMODE Mask */ + +/* ------------------------------- RTC_ERCOUNTERS ------------------------------- */ +#define RTC_ERCOUNTERS_COUNTER0_Pos 0 /*!< RTC ERCOUNTERS: COUNTER0 Position */ +#define RTC_ERCOUNTERS_COUNTER0_Msk (0x07UL << RTC_ERCOUNTERS_COUNTER0_Pos) /*!< RTC ERCOUNTERS: COUNTER0 Mask */ +#define RTC_ERCOUNTERS_COUNTER1_Pos 8 /*!< RTC ERCOUNTERS: COUNTER1 Position */ +#define RTC_ERCOUNTERS_COUNTER1_Msk (0x07UL << RTC_ERCOUNTERS_COUNTER1_Pos) /*!< RTC ERCOUNTERS: COUNTER1 Mask */ +#define RTC_ERCOUNTERS_COUNTER2_Pos 16 /*!< RTC ERCOUNTERS: COUNTER2 Position */ +#define RTC_ERCOUNTERS_COUNTER2_Msk (0x07UL << RTC_ERCOUNTERS_COUNTER2_Pos) /*!< RTC ERCOUNTERS: COUNTER2 Mask */ + +/* ------------------------------ RTC_ERFIRSTSTAMP0 ----------------------------- */ +#define RTC_ERFIRSTSTAMP0_SEC_Pos 0 /*!< RTC ERFIRSTSTAMP0: SEC Position */ +#define RTC_ERFIRSTSTAMP0_SEC_Msk (0x3fUL << RTC_ERFIRSTSTAMP0_SEC_Pos) /*!< RTC ERFIRSTSTAMP0: SEC Mask */ +#define RTC_ERFIRSTSTAMP0_MIN_Pos 6 /*!< RTC ERFIRSTSTAMP0: MIN Position */ +#define RTC_ERFIRSTSTAMP0_MIN_Msk (0x3fUL << RTC_ERFIRSTSTAMP0_MIN_Pos) /*!< RTC ERFIRSTSTAMP0: MIN Mask */ +#define RTC_ERFIRSTSTAMP0_HOUR_Pos 12 /*!< RTC ERFIRSTSTAMP0: HOUR Position */ +#define RTC_ERFIRSTSTAMP0_HOUR_Msk (0x1fUL << RTC_ERFIRSTSTAMP0_HOUR_Pos) /*!< RTC ERFIRSTSTAMP0: HOUR Mask */ +#define RTC_ERFIRSTSTAMP0_DOY_Pos 17 /*!< RTC ERFIRSTSTAMP0: DOY Position */ +#define RTC_ERFIRSTSTAMP0_DOY_Msk (0x000001ffUL << RTC_ERFIRSTSTAMP0_DOY_Pos) /*!< RTC ERFIRSTSTAMP0: DOY Mask */ + +/* ------------------------------ RTC_ERFIRSTSTAMP1 ----------------------------- */ +#define RTC_ERFIRSTSTAMP1_SEC_Pos 0 /*!< RTC ERFIRSTSTAMP1: SEC Position */ +#define RTC_ERFIRSTSTAMP1_SEC_Msk (0x3fUL << RTC_ERFIRSTSTAMP1_SEC_Pos) /*!< RTC ERFIRSTSTAMP1: SEC Mask */ +#define RTC_ERFIRSTSTAMP1_MIN_Pos 6 /*!< RTC ERFIRSTSTAMP1: MIN Position */ +#define RTC_ERFIRSTSTAMP1_MIN_Msk (0x3fUL << RTC_ERFIRSTSTAMP1_MIN_Pos) /*!< RTC ERFIRSTSTAMP1: MIN Mask */ +#define RTC_ERFIRSTSTAMP1_HOUR_Pos 12 /*!< RTC ERFIRSTSTAMP1: HOUR Position */ +#define RTC_ERFIRSTSTAMP1_HOUR_Msk (0x1fUL << RTC_ERFIRSTSTAMP1_HOUR_Pos) /*!< RTC ERFIRSTSTAMP1: HOUR Mask */ +#define RTC_ERFIRSTSTAMP1_DOY_Pos 17 /*!< RTC ERFIRSTSTAMP1: DOY Position */ +#define RTC_ERFIRSTSTAMP1_DOY_Msk (0x000001ffUL << RTC_ERFIRSTSTAMP1_DOY_Pos) /*!< RTC ERFIRSTSTAMP1: DOY Mask */ + +/* ------------------------------ RTC_ERFIRSTSTAMP2 ----------------------------- */ +#define RTC_ERFIRSTSTAMP2_SEC_Pos 0 /*!< RTC ERFIRSTSTAMP2: SEC Position */ +#define RTC_ERFIRSTSTAMP2_SEC_Msk (0x3fUL << RTC_ERFIRSTSTAMP2_SEC_Pos) /*!< RTC ERFIRSTSTAMP2: SEC Mask */ +#define RTC_ERFIRSTSTAMP2_MIN_Pos 6 /*!< RTC ERFIRSTSTAMP2: MIN Position */ +#define RTC_ERFIRSTSTAMP2_MIN_Msk (0x3fUL << RTC_ERFIRSTSTAMP2_MIN_Pos) /*!< RTC ERFIRSTSTAMP2: MIN Mask */ +#define RTC_ERFIRSTSTAMP2_HOUR_Pos 12 /*!< RTC ERFIRSTSTAMP2: HOUR Position */ +#define RTC_ERFIRSTSTAMP2_HOUR_Msk (0x1fUL << RTC_ERFIRSTSTAMP2_HOUR_Pos) /*!< RTC ERFIRSTSTAMP2: HOUR Mask */ +#define RTC_ERFIRSTSTAMP2_DOY_Pos 17 /*!< RTC ERFIRSTSTAMP2: DOY Position */ +#define RTC_ERFIRSTSTAMP2_DOY_Msk (0x000001ffUL << RTC_ERFIRSTSTAMP2_DOY_Pos) /*!< RTC ERFIRSTSTAMP2: DOY Mask */ + +/* ------------------------------ RTC_ERLASTSTAMP0 ------------------------------ */ +#define RTC_ERLASTSTAMP0_SEC_Pos 0 /*!< RTC ERLASTSTAMP0: SEC Position */ +#define RTC_ERLASTSTAMP0_SEC_Msk (0x3fUL << RTC_ERLASTSTAMP0_SEC_Pos) /*!< RTC ERLASTSTAMP0: SEC Mask */ +#define RTC_ERLASTSTAMP0_MIN_Pos 6 /*!< RTC ERLASTSTAMP0: MIN Position */ +#define RTC_ERLASTSTAMP0_MIN_Msk (0x3fUL << RTC_ERLASTSTAMP0_MIN_Pos) /*!< RTC ERLASTSTAMP0: MIN Mask */ +#define RTC_ERLASTSTAMP0_HOUR_Pos 12 /*!< RTC ERLASTSTAMP0: HOUR Position */ +#define RTC_ERLASTSTAMP0_HOUR_Msk (0x1fUL << RTC_ERLASTSTAMP0_HOUR_Pos) /*!< RTC ERLASTSTAMP0: HOUR Mask */ +#define RTC_ERLASTSTAMP0_DOY_Pos 17 /*!< RTC ERLASTSTAMP0: DOY Position */ +#define RTC_ERLASTSTAMP0_DOY_Msk (0x000001ffUL << RTC_ERLASTSTAMP0_DOY_Pos) /*!< RTC ERLASTSTAMP0: DOY Mask */ + +/* ------------------------------ RTC_ERLASTSTAMP1 ------------------------------ */ +#define RTC_ERLASTSTAMP1_SEC_Pos 0 /*!< RTC ERLASTSTAMP1: SEC Position */ +#define RTC_ERLASTSTAMP1_SEC_Msk (0x3fUL << RTC_ERLASTSTAMP1_SEC_Pos) /*!< RTC ERLASTSTAMP1: SEC Mask */ +#define RTC_ERLASTSTAMP1_MIN_Pos 6 /*!< RTC ERLASTSTAMP1: MIN Position */ +#define RTC_ERLASTSTAMP1_MIN_Msk (0x3fUL << RTC_ERLASTSTAMP1_MIN_Pos) /*!< RTC ERLASTSTAMP1: MIN Mask */ +#define RTC_ERLASTSTAMP1_HOUR_Pos 12 /*!< RTC ERLASTSTAMP1: HOUR Position */ +#define RTC_ERLASTSTAMP1_HOUR_Msk (0x1fUL << RTC_ERLASTSTAMP1_HOUR_Pos) /*!< RTC ERLASTSTAMP1: HOUR Mask */ +#define RTC_ERLASTSTAMP1_DOY_Pos 17 /*!< RTC ERLASTSTAMP1: DOY Position */ +#define RTC_ERLASTSTAMP1_DOY_Msk (0x000001ffUL << RTC_ERLASTSTAMP1_DOY_Pos) /*!< RTC ERLASTSTAMP1: DOY Mask */ + +/* ------------------------------ RTC_ERLASTSTAMP2 ------------------------------ */ +#define RTC_ERLASTSTAMP2_SEC_Pos 0 /*!< RTC ERLASTSTAMP2: SEC Position */ +#define RTC_ERLASTSTAMP2_SEC_Msk (0x3fUL << RTC_ERLASTSTAMP2_SEC_Pos) /*!< RTC ERLASTSTAMP2: SEC Mask */ +#define RTC_ERLASTSTAMP2_MIN_Pos 6 /*!< RTC ERLASTSTAMP2: MIN Position */ +#define RTC_ERLASTSTAMP2_MIN_Msk (0x3fUL << RTC_ERLASTSTAMP2_MIN_Pos) /*!< RTC ERLASTSTAMP2: MIN Mask */ +#define RTC_ERLASTSTAMP2_HOUR_Pos 12 /*!< RTC ERLASTSTAMP2: HOUR Position */ +#define RTC_ERLASTSTAMP2_HOUR_Msk (0x1fUL << RTC_ERLASTSTAMP2_HOUR_Pos) /*!< RTC ERLASTSTAMP2: HOUR Mask */ +#define RTC_ERLASTSTAMP2_DOY_Pos 17 /*!< RTC ERLASTSTAMP2: DOY Position */ +#define RTC_ERLASTSTAMP2_DOY_Msk (0x000001ffUL << RTC_ERLASTSTAMP2_DOY_Pos) /*!< RTC ERLASTSTAMP2: DOY Mask */ + + +/* ================================================================================ */ +/* ================ struct 'CGU' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- CGU_FREQ_MON -------------------------------- */ +#define CGU_FREQ_MON_RCNT_Pos 0 /*!< CGU FREQ_MON: RCNT Position */ +#define CGU_FREQ_MON_RCNT_Msk (0x000001ffUL << CGU_FREQ_MON_RCNT_Pos) /*!< CGU FREQ_MON: RCNT Mask */ +#define CGU_FREQ_MON_FCNT_Pos 9 /*!< CGU FREQ_MON: FCNT Position */ +#define CGU_FREQ_MON_FCNT_Msk (0x00003fffUL << CGU_FREQ_MON_FCNT_Pos) /*!< CGU FREQ_MON: FCNT Mask */ +#define CGU_FREQ_MON_MEAS_Pos 23 /*!< CGU FREQ_MON: MEAS Position */ +#define CGU_FREQ_MON_MEAS_Msk (0x01UL << CGU_FREQ_MON_MEAS_Pos) /*!< CGU FREQ_MON: MEAS Mask */ +#define CGU_FREQ_MON_CLK_SEL_Pos 24 /*!< CGU FREQ_MON: CLK_SEL Position */ +#define CGU_FREQ_MON_CLK_SEL_Msk (0x1fUL << CGU_FREQ_MON_CLK_SEL_Pos) /*!< CGU FREQ_MON: CLK_SEL Mask */ + +/* ------------------------------ CGU_XTAL_OSC_CTRL ----------------------------- */ +#define CGU_XTAL_OSC_CTRL_ENABLE_Pos 0 /*!< CGU XTAL_OSC_CTRL: ENABLE Position */ +#define CGU_XTAL_OSC_CTRL_ENABLE_Msk (0x01UL << CGU_XTAL_OSC_CTRL_ENABLE_Pos) /*!< CGU XTAL_OSC_CTRL: ENABLE Mask */ +#define CGU_XTAL_OSC_CTRL_BYPASS_Pos 1 /*!< CGU XTAL_OSC_CTRL: BYPASS Position */ +#define CGU_XTAL_OSC_CTRL_BYPASS_Msk (0x01UL << CGU_XTAL_OSC_CTRL_BYPASS_Pos) /*!< CGU XTAL_OSC_CTRL: BYPASS Mask */ +#define CGU_XTAL_OSC_CTRL_HF_Pos 2 /*!< CGU XTAL_OSC_CTRL: HF Position */ +#define CGU_XTAL_OSC_CTRL_HF_Msk (0x01UL << CGU_XTAL_OSC_CTRL_HF_Pos) /*!< CGU XTAL_OSC_CTRL: HF Mask */ + +/* ------------------------------ CGU_PLL0USB_STAT ------------------------------ */ +#define CGU_PLL0USB_STAT_LOCK_Pos 0 /*!< CGU PLL0USB_STAT: LOCK Position */ +#define CGU_PLL0USB_STAT_LOCK_Msk (0x01UL << CGU_PLL0USB_STAT_LOCK_Pos) /*!< CGU PLL0USB_STAT: LOCK Mask */ +#define CGU_PLL0USB_STAT_FR_Pos 1 /*!< CGU PLL0USB_STAT: FR Position */ +#define CGU_PLL0USB_STAT_FR_Msk (0x01UL << CGU_PLL0USB_STAT_FR_Pos) /*!< CGU PLL0USB_STAT: FR Mask */ + +/* ------------------------------ CGU_PLL0USB_CTRL ------------------------------ */ +#define CGU_PLL0USB_CTRL_PD_Pos 0 /*!< CGU PLL0USB_CTRL: PD Position */ +#define CGU_PLL0USB_CTRL_PD_Msk (0x01UL << CGU_PLL0USB_CTRL_PD_Pos) /*!< CGU PLL0USB_CTRL: PD Mask */ +#define CGU_PLL0USB_CTRL_BYPASS_Pos 1 /*!< CGU PLL0USB_CTRL: BYPASS Position */ +#define CGU_PLL0USB_CTRL_BYPASS_Msk (0x01UL << CGU_PLL0USB_CTRL_BYPASS_Pos) /*!< CGU PLL0USB_CTRL: BYPASS Mask */ +#define CGU_PLL0USB_CTRL_DIRECTI_Pos 2 /*!< CGU PLL0USB_CTRL: DIRECTI Position */ +#define CGU_PLL0USB_CTRL_DIRECTI_Msk (0x01UL << CGU_PLL0USB_CTRL_DIRECTI_Pos) /*!< CGU PLL0USB_CTRL: DIRECTI Mask */ +#define CGU_PLL0USB_CTRL_DIRECTO_Pos 3 /*!< CGU PLL0USB_CTRL: DIRECTO Position */ +#define CGU_PLL0USB_CTRL_DIRECTO_Msk (0x01UL << CGU_PLL0USB_CTRL_DIRECTO_Pos) /*!< CGU PLL0USB_CTRL: DIRECTO Mask */ +#define CGU_PLL0USB_CTRL_CLKEN_Pos 4 /*!< CGU PLL0USB_CTRL: CLKEN Position */ +#define CGU_PLL0USB_CTRL_CLKEN_Msk (0x01UL << CGU_PLL0USB_CTRL_CLKEN_Pos) /*!< CGU PLL0USB_CTRL: CLKEN Mask */ +#define CGU_PLL0USB_CTRL_FRM_Pos 6 /*!< CGU PLL0USB_CTRL: FRM Position */ +#define CGU_PLL0USB_CTRL_FRM_Msk (0x01UL << CGU_PLL0USB_CTRL_FRM_Pos) /*!< CGU PLL0USB_CTRL: FRM Mask */ +#define CGU_PLL0USB_CTRL_AUTOBLOCK_Pos 11 /*!< CGU PLL0USB_CTRL: AUTOBLOCK Position */ +#define CGU_PLL0USB_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_PLL0USB_CTRL_AUTOBLOCK_Pos) /*!< CGU PLL0USB_CTRL: AUTOBLOCK Mask */ +#define CGU_PLL0USB_CTRL_CLK_SEL_Pos 24 /*!< CGU PLL0USB_CTRL: CLK_SEL Position */ +#define CGU_PLL0USB_CTRL_CLK_SEL_Msk (0x1fUL << CGU_PLL0USB_CTRL_CLK_SEL_Pos) /*!< CGU PLL0USB_CTRL: CLK_SEL Mask */ + +/* ------------------------------ CGU_PLL0USB_MDIV ------------------------------ */ +#define CGU_PLL0USB_MDIV_MDEC_Pos 0 /*!< CGU PLL0USB_MDIV: MDEC Position */ +#define CGU_PLL0USB_MDIV_MDEC_Msk (0x0001ffffUL << CGU_PLL0USB_MDIV_MDEC_Pos) /*!< CGU PLL0USB_MDIV: MDEC Mask */ +#define CGU_PLL0USB_MDIV_SELP_Pos 17 /*!< CGU PLL0USB_MDIV: SELP Position */ +#define CGU_PLL0USB_MDIV_SELP_Msk (0x1fUL << CGU_PLL0USB_MDIV_SELP_Pos) /*!< CGU PLL0USB_MDIV: SELP Mask */ +#define CGU_PLL0USB_MDIV_SELI_Pos 22 /*!< CGU PLL0USB_MDIV: SELI Position */ +#define CGU_PLL0USB_MDIV_SELI_Msk (0x3fUL << CGU_PLL0USB_MDIV_SELI_Pos) /*!< CGU PLL0USB_MDIV: SELI Mask */ +#define CGU_PLL0USB_MDIV_SELR_Pos 28 /*!< CGU PLL0USB_MDIV: SELR Position */ +#define CGU_PLL0USB_MDIV_SELR_Msk (0x0fUL << CGU_PLL0USB_MDIV_SELR_Pos) /*!< CGU PLL0USB_MDIV: SELR Mask */ + +/* ----------------------------- CGU_PLL0USB_NP_DIV ----------------------------- */ +#define CGU_PLL0USB_NP_DIV_PDEC_Pos 0 /*!< CGU PLL0USB_NP_DIV: PDEC Position */ +#define CGU_PLL0USB_NP_DIV_PDEC_Msk (0x7fUL << CGU_PLL0USB_NP_DIV_PDEC_Pos) /*!< CGU PLL0USB_NP_DIV: PDEC Mask */ +#define CGU_PLL0USB_NP_DIV_NDEC_Pos 12 /*!< CGU PLL0USB_NP_DIV: NDEC Position */ +#define CGU_PLL0USB_NP_DIV_NDEC_Msk (0x000003ffUL << CGU_PLL0USB_NP_DIV_NDEC_Pos) /*!< CGU PLL0USB_NP_DIV: NDEC Mask */ + +/* ----------------------------- CGU_PLL0AUDIO_STAT ----------------------------- */ +#define CGU_PLL0AUDIO_STAT_LOCK_Pos 0 /*!< CGU PLL0AUDIO_STAT: LOCK Position */ +#define CGU_PLL0AUDIO_STAT_LOCK_Msk (0x01UL << CGU_PLL0AUDIO_STAT_LOCK_Pos) /*!< CGU PLL0AUDIO_STAT: LOCK Mask */ +#define CGU_PLL0AUDIO_STAT_FR_Pos 1 /*!< CGU PLL0AUDIO_STAT: FR Position */ +#define CGU_PLL0AUDIO_STAT_FR_Msk (0x01UL << CGU_PLL0AUDIO_STAT_FR_Pos) /*!< CGU PLL0AUDIO_STAT: FR Mask */ + +/* ----------------------------- CGU_PLL0AUDIO_CTRL ----------------------------- */ +#define CGU_PLL0AUDIO_CTRL_PD_Pos 0 /*!< CGU PLL0AUDIO_CTRL: PD Position */ +#define CGU_PLL0AUDIO_CTRL_PD_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_PD_Pos) /*!< CGU PLL0AUDIO_CTRL: PD Mask */ +#define CGU_PLL0AUDIO_CTRL_BYPASS_Pos 1 /*!< CGU PLL0AUDIO_CTRL: BYPASS Position */ +#define CGU_PLL0AUDIO_CTRL_BYPASS_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_BYPASS_Pos) /*!< CGU PLL0AUDIO_CTRL: BYPASS Mask */ +#define CGU_PLL0AUDIO_CTRL_DIRECTI_Pos 2 /*!< CGU PLL0AUDIO_CTRL: DIRECTI Position */ +#define CGU_PLL0AUDIO_CTRL_DIRECTI_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTI_Pos) /*!< CGU PLL0AUDIO_CTRL: DIRECTI Mask */ +#define CGU_PLL0AUDIO_CTRL_DIRECTO_Pos 3 /*!< CGU PLL0AUDIO_CTRL: DIRECTO Position */ +#define CGU_PLL0AUDIO_CTRL_DIRECTO_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTO_Pos) /*!< CGU PLL0AUDIO_CTRL: DIRECTO Mask */ +#define CGU_PLL0AUDIO_CTRL_CLKEN_Pos 4 /*!< CGU PLL0AUDIO_CTRL: CLKEN Position */ +#define CGU_PLL0AUDIO_CTRL_CLKEN_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_CLKEN_Pos) /*!< CGU PLL0AUDIO_CTRL: CLKEN Mask */ +#define CGU_PLL0AUDIO_CTRL_FRM_Pos 6 /*!< CGU PLL0AUDIO_CTRL: FRM Position */ +#define CGU_PLL0AUDIO_CTRL_FRM_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_FRM_Pos) /*!< CGU PLL0AUDIO_CTRL: FRM Mask */ +#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos 11 /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Position */ +#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos) /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Mask */ +#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_Pos 12 /*!< CGU PLL0AUDIO_CTRL: PLLFRACT_REQ Position */ +#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_Pos) /*!< CGU PLL0AUDIO_CTRL: PLLFRACT_REQ Mask */ +#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos 13 /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Position */ +#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos) /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Mask */ +#define CGU_PLL0AUDIO_CTRL_MOD_PD_Pos 14 /*!< CGU PLL0AUDIO_CTRL: MOD_PD Position */ +#define CGU_PLL0AUDIO_CTRL_MOD_PD_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_MOD_PD_Pos) /*!< CGU PLL0AUDIO_CTRL: MOD_PD Mask */ +#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos 24 /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Position */ +#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Msk (0x1fUL << CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos) /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Mask */ + +/* ----------------------------- CGU_PLL0AUDIO_MDIV ----------------------------- */ +#define CGU_PLL0AUDIO_MDIV_MDEC_Pos 0 /*!< CGU PLL0AUDIO_MDIV: MDEC Position */ +#define CGU_PLL0AUDIO_MDIV_MDEC_Msk (0x0001ffffUL << CGU_PLL0AUDIO_MDIV_MDEC_Pos) /*!< CGU PLL0AUDIO_MDIV: MDEC Mask */ + +/* ---------------------------- CGU_PLL0AUDIO_NP_DIV ---------------------------- */ +#define CGU_PLL0AUDIO_NP_DIV_PDEC_Pos 0 /*!< CGU PLL0AUDIO_NP_DIV: PDEC Position */ +#define CGU_PLL0AUDIO_NP_DIV_PDEC_Msk (0x7fUL << CGU_PLL0AUDIO_NP_DIV_PDEC_Pos) /*!< CGU PLL0AUDIO_NP_DIV: PDEC Mask */ +#define CGU_PLL0AUDIO_NP_DIV_NDEC_Pos 12 /*!< CGU PLL0AUDIO_NP_DIV: NDEC Position */ +#define CGU_PLL0AUDIO_NP_DIV_NDEC_Msk (0x000003ffUL << CGU_PLL0AUDIO_NP_DIV_NDEC_Pos) /*!< CGU PLL0AUDIO_NP_DIV: NDEC Mask */ + +/* ----------------------------- CGU_PLL0AUDIO_FRAC ----------------------------- */ +#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos 0 /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Position */ +#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Msk (0x003fffffUL << CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos) /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Mask */ + +/* -------------------------------- CGU_PLL1_STAT ------------------------------- */ +#define CGU_PLL1_STAT_LOCK_Pos 0 /*!< CGU PLL1_STAT: LOCK Position */ +#define CGU_PLL1_STAT_LOCK_Msk (0x01UL << CGU_PLL1_STAT_LOCK_Pos) /*!< CGU PLL1_STAT: LOCK Mask */ + +/* -------------------------------- CGU_PLL1_CTRL ------------------------------- */ +#define CGU_PLL1_CTRL_PD_Pos 0 /*!< CGU PLL1_CTRL: PD Position */ +#define CGU_PLL1_CTRL_PD_Msk (0x01UL << CGU_PLL1_CTRL_PD_Pos) /*!< CGU PLL1_CTRL: PD Mask */ +#define CGU_PLL1_CTRL_BYPASS_Pos 1 /*!< CGU PLL1_CTRL: BYPASS Position */ +#define CGU_PLL1_CTRL_BYPASS_Msk (0x01UL << CGU_PLL1_CTRL_BYPASS_Pos) /*!< CGU PLL1_CTRL: BYPASS Mask */ +#define CGU_PLL1_CTRL_FBSEL_Pos 6 /*!< CGU PLL1_CTRL: FBSEL Position */ +#define CGU_PLL1_CTRL_FBSEL_Msk (0x01UL << CGU_PLL1_CTRL_FBSEL_Pos) /*!< CGU PLL1_CTRL: FBSEL Mask */ +#define CGU_PLL1_CTRL_DIRECT_Pos 7 /*!< CGU PLL1_CTRL: DIRECT Position */ +#define CGU_PLL1_CTRL_DIRECT_Msk (0x01UL << CGU_PLL1_CTRL_DIRECT_Pos) /*!< CGU PLL1_CTRL: DIRECT Mask */ +#define CGU_PLL1_CTRL_PSEL_Pos 8 /*!< CGU PLL1_CTRL: PSEL Position */ +#define CGU_PLL1_CTRL_PSEL_Msk (0x03UL << CGU_PLL1_CTRL_PSEL_Pos) /*!< CGU PLL1_CTRL: PSEL Mask */ +#define CGU_PLL1_CTRL_AUTOBLOCK_Pos 11 /*!< CGU PLL1_CTRL: AUTOBLOCK Position */ +#define CGU_PLL1_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_PLL1_CTRL_AUTOBLOCK_Pos) /*!< CGU PLL1_CTRL: AUTOBLOCK Mask */ +#define CGU_PLL1_CTRL_NSEL_Pos 12 /*!< CGU PLL1_CTRL: NSEL Position */ +#define CGU_PLL1_CTRL_NSEL_Msk (0x03UL << CGU_PLL1_CTRL_NSEL_Pos) /*!< CGU PLL1_CTRL: NSEL Mask */ +#define CGU_PLL1_CTRL_MSEL_Pos 16 /*!< CGU PLL1_CTRL: MSEL Position */ +#define CGU_PLL1_CTRL_MSEL_Msk (0x000000ffUL << CGU_PLL1_CTRL_MSEL_Pos) /*!< CGU PLL1_CTRL: MSEL Mask */ +#define CGU_PLL1_CTRL_CLK_SEL_Pos 24 /*!< CGU PLL1_CTRL: CLK_SEL Position */ +#define CGU_PLL1_CTRL_CLK_SEL_Msk (0x1fUL << CGU_PLL1_CTRL_CLK_SEL_Pos) /*!< CGU PLL1_CTRL: CLK_SEL Mask */ + +/* ------------------------------- CGU_IDIVA_CTRL ------------------------------- */ +#define CGU_IDIVA_CTRL_PD_Pos 0 /*!< CGU IDIVA_CTRL: PD Position */ +#define CGU_IDIVA_CTRL_PD_Msk (0x01UL << CGU_IDIVA_CTRL_PD_Pos) /*!< CGU IDIVA_CTRL: PD Mask */ +#define CGU_IDIVA_CTRL_IDIV_Pos 2 /*!< CGU IDIVA_CTRL: IDIV Position */ +#define CGU_IDIVA_CTRL_IDIV_Msk (0x03UL << CGU_IDIVA_CTRL_IDIV_Pos) /*!< CGU IDIVA_CTRL: IDIV Mask */ +#define CGU_IDIVA_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVA_CTRL: AUTOBLOCK Position */ +#define CGU_IDIVA_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVA_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVA_CTRL: AUTOBLOCK Mask */ +#define CGU_IDIVA_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVA_CTRL: CLK_SEL Position */ +#define CGU_IDIVA_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVA_CTRL_CLK_SEL_Pos) /*!< CGU IDIVA_CTRL: CLK_SEL Mask */ + +/* ------------------------------- CGU_IDIVB_CTRL ------------------------------- */ +#define CGU_IDIVB_CTRL_PD_Pos 0 /*!< CGU IDIVB_CTRL: PD Position */ +#define CGU_IDIVB_CTRL_PD_Msk (0x01UL << CGU_IDIVB_CTRL_PD_Pos) /*!< CGU IDIVB_CTRL: PD Mask */ +#define CGU_IDIVB_CTRL_IDIV_Pos 2 /*!< CGU IDIVB_CTRL: IDIV Position */ +#define CGU_IDIVB_CTRL_IDIV_Msk (0x0fUL << CGU_IDIVB_CTRL_IDIV_Pos) /*!< CGU IDIVB_CTRL: IDIV Mask */ +#define CGU_IDIVB_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVB_CTRL: AUTOBLOCK Position */ +#define CGU_IDIVB_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVB_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVB_CTRL: AUTOBLOCK Mask */ +#define CGU_IDIVB_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVB_CTRL: CLK_SEL Position */ +#define CGU_IDIVB_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVB_CTRL_CLK_SEL_Pos) /*!< CGU IDIVB_CTRL: CLK_SEL Mask */ + +/* ------------------------------- CGU_IDIVC_CTRL ------------------------------- */ +#define CGU_IDIVC_CTRL_PD_Pos 0 /*!< CGU IDIVC_CTRL: PD Position */ +#define CGU_IDIVC_CTRL_PD_Msk (0x01UL << CGU_IDIVC_CTRL_PD_Pos) /*!< CGU IDIVC_CTRL: PD Mask */ +#define CGU_IDIVC_CTRL_IDIV_Pos 2 /*!< CGU IDIVC_CTRL: IDIV Position */ +#define CGU_IDIVC_CTRL_IDIV_Msk (0x0fUL << CGU_IDIVC_CTRL_IDIV_Pos) /*!< CGU IDIVC_CTRL: IDIV Mask */ +#define CGU_IDIVC_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVC_CTRL: AUTOBLOCK Position */ +#define CGU_IDIVC_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVC_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVC_CTRL: AUTOBLOCK Mask */ +#define CGU_IDIVC_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVC_CTRL: CLK_SEL Position */ +#define CGU_IDIVC_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVC_CTRL_CLK_SEL_Pos) /*!< CGU IDIVC_CTRL: CLK_SEL Mask */ + +/* ------------------------------- CGU_IDIVD_CTRL ------------------------------- */ +#define CGU_IDIVD_CTRL_PD_Pos 0 /*!< CGU IDIVD_CTRL: PD Position */ +#define CGU_IDIVD_CTRL_PD_Msk (0x01UL << CGU_IDIVD_CTRL_PD_Pos) /*!< CGU IDIVD_CTRL: PD Mask */ +#define CGU_IDIVD_CTRL_IDIV_Pos 2 /*!< CGU IDIVD_CTRL: IDIV Position */ +#define CGU_IDIVD_CTRL_IDIV_Msk (0x0fUL << CGU_IDIVD_CTRL_IDIV_Pos) /*!< CGU IDIVD_CTRL: IDIV Mask */ +#define CGU_IDIVD_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVD_CTRL: AUTOBLOCK Position */ +#define CGU_IDIVD_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVD_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVD_CTRL: AUTOBLOCK Mask */ +#define CGU_IDIVD_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVD_CTRL: CLK_SEL Position */ +#define CGU_IDIVD_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVD_CTRL_CLK_SEL_Pos) /*!< CGU IDIVD_CTRL: CLK_SEL Mask */ + +/* ------------------------------- CGU_IDIVE_CTRL ------------------------------- */ +#define CGU_IDIVE_CTRL_PD_Pos 0 /*!< CGU IDIVE_CTRL: PD Position */ +#define CGU_IDIVE_CTRL_PD_Msk (0x01UL << CGU_IDIVE_CTRL_PD_Pos) /*!< CGU IDIVE_CTRL: PD Mask */ +#define CGU_IDIVE_CTRL_IDIV_Pos 2 /*!< CGU IDIVE_CTRL: IDIV Position */ +#define CGU_IDIVE_CTRL_IDIV_Msk (0x000000ffUL << CGU_IDIVE_CTRL_IDIV_Pos) /*!< CGU IDIVE_CTRL: IDIV Mask */ +#define CGU_IDIVE_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVE_CTRL: AUTOBLOCK Position */ +#define CGU_IDIVE_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVE_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVE_CTRL: AUTOBLOCK Mask */ +#define CGU_IDIVE_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVE_CTRL: CLK_SEL Position */ +#define CGU_IDIVE_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVE_CTRL_CLK_SEL_Pos) /*!< CGU IDIVE_CTRL: CLK_SEL Mask */ + +/* ------------------------------ CGU_BASE_SAFE_CLK ----------------------------- */ +#define CGU_BASE_SAFE_CLK_PD_Pos 0 /*!< CGU BASE_SAFE_CLK: PD Position */ +#define CGU_BASE_SAFE_CLK_PD_Msk (0x01UL << CGU_BASE_SAFE_CLK_PD_Pos) /*!< CGU BASE_SAFE_CLK: PD Mask */ +#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Position */ +#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_SAFE_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SAFE_CLK: CLK_SEL Position */ +#define CGU_BASE_SAFE_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SAFE_CLK_CLK_SEL_Pos) /*!< CGU BASE_SAFE_CLK: CLK_SEL Mask */ + +/* ------------------------------ CGU_BASE_USB0_CLK ----------------------------- */ +#define CGU_BASE_USB0_CLK_PD_Pos 0 /*!< CGU BASE_USB0_CLK: PD Position */ +#define CGU_BASE_USB0_CLK_PD_Msk (0x01UL << CGU_BASE_USB0_CLK_PD_Pos) /*!< CGU BASE_USB0_CLK: PD Mask */ +#define CGU_BASE_USB0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_USB0_CLK: AUTOBLOCK Position */ +#define CGU_BASE_USB0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_USB0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_USB0_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_USB0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_USB0_CLK: CLK_SEL Position */ +#define CGU_BASE_USB0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_USB0_CLK_CLK_SEL_Pos) /*!< CGU BASE_USB0_CLK: CLK_SEL Mask */ + +/* ----------------------------- CGU_BASE_PERIPH_CLK ---------------------------- */ +#define CGU_BASE_PERIPH_CLK_PD_Pos 0 /*!< CGU BASE_PERIPH_CLK: PD Position */ +#define CGU_BASE_PERIPH_CLK_PD_Msk (0x01UL << CGU_BASE_PERIPH_CLK_PD_Pos) /*!< CGU BASE_PERIPH_CLK: PD Mask */ +#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Position */ +#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_PERIPH_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_PERIPH_CLK: CLK_SEL Position */ +#define CGU_BASE_PERIPH_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_PERIPH_CLK_CLK_SEL_Pos) /*!< CGU BASE_PERIPH_CLK: CLK_SEL Mask */ + +/* ------------------------------ CGU_BASE_USB1_CLK ----------------------------- */ +#define CGU_BASE_USB1_CLK_PD_Pos 0 /*!< CGU BASE_USB1_CLK: PD Position */ +#define CGU_BASE_USB1_CLK_PD_Msk (0x01UL << CGU_BASE_USB1_CLK_PD_Pos) /*!< CGU BASE_USB1_CLK: PD Mask */ +#define CGU_BASE_USB1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_USB1_CLK: AUTOBLOCK Position */ +#define CGU_BASE_USB1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_USB1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_USB1_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_USB1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_USB1_CLK: CLK_SEL Position */ +#define CGU_BASE_USB1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_USB1_CLK_CLK_SEL_Pos) /*!< CGU BASE_USB1_CLK: CLK_SEL Mask */ + +/* ------------------------------- CGU_BASE_M4_CLK ------------------------------ */ +#define CGU_BASE_M4_CLK_PD_Pos 0 /*!< CGU BASE_M4_CLK: PD Position */ +#define CGU_BASE_M4_CLK_PD_Msk (0x01UL << CGU_BASE_M4_CLK_PD_Pos) /*!< CGU BASE_M4_CLK: PD Mask */ +#define CGU_BASE_M4_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_M4_CLK: AUTOBLOCK Position */ +#define CGU_BASE_M4_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_M4_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_M4_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_M4_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_M4_CLK: CLK_SEL Position */ +#define CGU_BASE_M4_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_M4_CLK_CLK_SEL_Pos) /*!< CGU BASE_M4_CLK: CLK_SEL Mask */ + +/* ----------------------------- CGU_BASE_SPIFI_CLK ----------------------------- */ +#define CGU_BASE_SPIFI_CLK_PD_Pos 0 /*!< CGU BASE_SPIFI_CLK: PD Position */ +#define CGU_BASE_SPIFI_CLK_PD_Msk (0x01UL << CGU_BASE_SPIFI_CLK_PD_Pos) /*!< CGU BASE_SPIFI_CLK: PD Mask */ +#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Position */ +#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_SPIFI_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SPIFI_CLK: CLK_SEL Position */ +#define CGU_BASE_SPIFI_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SPIFI_CLK_CLK_SEL_Pos) /*!< CGU BASE_SPIFI_CLK: CLK_SEL Mask */ + +/* ------------------------------ CGU_BASE_SPI_CLK ------------------------------ */ +#define CGU_BASE_SPI_CLK_PD_Pos 0 /*!< CGU BASE_SPI_CLK: PD Position */ +#define CGU_BASE_SPI_CLK_PD_Msk (0x01UL << CGU_BASE_SPI_CLK_PD_Pos) /*!< CGU BASE_SPI_CLK: PD Mask */ +#define CGU_BASE_SPI_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SPI_CLK: AUTOBLOCK Position */ +#define CGU_BASE_SPI_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SPI_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SPI_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_SPI_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SPI_CLK: CLK_SEL Position */ +#define CGU_BASE_SPI_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SPI_CLK_CLK_SEL_Pos) /*!< CGU BASE_SPI_CLK: CLK_SEL Mask */ + +/* ----------------------------- CGU_BASE_PHY_RX_CLK ---------------------------- */ +#define CGU_BASE_PHY_RX_CLK_PD_Pos 0 /*!< CGU BASE_PHY_RX_CLK: PD Position */ +#define CGU_BASE_PHY_RX_CLK_PD_Msk (0x01UL << CGU_BASE_PHY_RX_CLK_PD_Pos) /*!< CGU BASE_PHY_RX_CLK: PD Mask */ +#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Position */ +#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Position */ +#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos) /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Mask */ + +/* ----------------------------- CGU_BASE_PHY_TX_CLK ---------------------------- */ +#define CGU_BASE_PHY_TX_CLK_PD_Pos 0 /*!< CGU BASE_PHY_TX_CLK: PD Position */ +#define CGU_BASE_PHY_TX_CLK_PD_Msk (0x01UL << CGU_BASE_PHY_TX_CLK_PD_Pos) /*!< CGU BASE_PHY_TX_CLK: PD Mask */ +#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Position */ +#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Position */ +#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos) /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Mask */ + +/* ------------------------------ CGU_BASE_APB1_CLK ----------------------------- */ +#define CGU_BASE_APB1_CLK_PD_Pos 0 /*!< CGU BASE_APB1_CLK: PD Position */ +#define CGU_BASE_APB1_CLK_PD_Msk (0x01UL << CGU_BASE_APB1_CLK_PD_Pos) /*!< CGU BASE_APB1_CLK: PD Mask */ +#define CGU_BASE_APB1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_APB1_CLK: AUTOBLOCK Position */ +#define CGU_BASE_APB1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_APB1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_APB1_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_APB1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_APB1_CLK: CLK_SEL Position */ +#define CGU_BASE_APB1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_APB1_CLK_CLK_SEL_Pos) /*!< CGU BASE_APB1_CLK: CLK_SEL Mask */ + +/* ------------------------------ CGU_BASE_APB3_CLK ----------------------------- */ +#define CGU_BASE_APB3_CLK_PD_Pos 0 /*!< CGU BASE_APB3_CLK: PD Position */ +#define CGU_BASE_APB3_CLK_PD_Msk (0x01UL << CGU_BASE_APB3_CLK_PD_Pos) /*!< CGU BASE_APB3_CLK: PD Mask */ +#define CGU_BASE_APB3_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_APB3_CLK: AUTOBLOCK Position */ +#define CGU_BASE_APB3_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_APB3_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_APB3_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_APB3_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_APB3_CLK: CLK_SEL Position */ +#define CGU_BASE_APB3_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_APB3_CLK_CLK_SEL_Pos) /*!< CGU BASE_APB3_CLK: CLK_SEL Mask */ + +/* ------------------------------ CGU_BASE_LCD_CLK ------------------------------ */ +#define CGU_BASE_LCD_CLK_PD_Pos 0 /*!< CGU BASE_LCD_CLK: PD Position */ +#define CGU_BASE_LCD_CLK_PD_Msk (0x01UL << CGU_BASE_LCD_CLK_PD_Pos) /*!< CGU BASE_LCD_CLK: PD Mask */ +#define CGU_BASE_LCD_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_LCD_CLK: AUTOBLOCK Position */ +#define CGU_BASE_LCD_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_LCD_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_LCD_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_LCD_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_LCD_CLK: CLK_SEL Position */ +#define CGU_BASE_LCD_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_LCD_CLK_CLK_SEL_Pos) /*!< CGU BASE_LCD_CLK: CLK_SEL Mask */ + +/* ------------------------------ CGU_BASE_SDIO_CLK ----------------------------- */ +#define CGU_BASE_SDIO_CLK_PD_Pos 0 /*!< CGU BASE_SDIO_CLK: PD Position */ +#define CGU_BASE_SDIO_CLK_PD_Msk (0x01UL << CGU_BASE_SDIO_CLK_PD_Pos) /*!< CGU BASE_SDIO_CLK: PD Mask */ +#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Position */ +#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_SDIO_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SDIO_CLK: CLK_SEL Position */ +#define CGU_BASE_SDIO_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SDIO_CLK_CLK_SEL_Pos) /*!< CGU BASE_SDIO_CLK: CLK_SEL Mask */ + +/* ------------------------------ CGU_BASE_SSP0_CLK ----------------------------- */ +#define CGU_BASE_SSP0_CLK_PD_Pos 0 /*!< CGU BASE_SSP0_CLK: PD Position */ +#define CGU_BASE_SSP0_CLK_PD_Msk (0x01UL << CGU_BASE_SSP0_CLK_PD_Pos) /*!< CGU BASE_SSP0_CLK: PD Mask */ +#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Position */ +#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_SSP0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SSP0_CLK: CLK_SEL Position */ +#define CGU_BASE_SSP0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SSP0_CLK_CLK_SEL_Pos) /*!< CGU BASE_SSP0_CLK: CLK_SEL Mask */ + +/* ------------------------------ CGU_BASE_SSP1_CLK ----------------------------- */ +#define CGU_BASE_SSP1_CLK_PD_Pos 0 /*!< CGU BASE_SSP1_CLK: PD Position */ +#define CGU_BASE_SSP1_CLK_PD_Msk (0x01UL << CGU_BASE_SSP1_CLK_PD_Pos) /*!< CGU BASE_SSP1_CLK: PD Mask */ +#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Position */ +#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_SSP1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SSP1_CLK: CLK_SEL Position */ +#define CGU_BASE_SSP1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SSP1_CLK_CLK_SEL_Pos) /*!< CGU BASE_SSP1_CLK: CLK_SEL Mask */ + +/* ----------------------------- CGU_BASE_UART0_CLK ----------------------------- */ +#define CGU_BASE_UART0_CLK_PD_Pos 0 /*!< CGU BASE_UART0_CLK: PD Position */ +#define CGU_BASE_UART0_CLK_PD_Msk (0x01UL << CGU_BASE_UART0_CLK_PD_Pos) /*!< CGU BASE_UART0_CLK: PD Mask */ +#define CGU_BASE_UART0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART0_CLK: AUTOBLOCK Position */ +#define CGU_BASE_UART0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART0_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_UART0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART0_CLK: CLK_SEL Position */ +#define CGU_BASE_UART0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART0_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART0_CLK: CLK_SEL Mask */ + +/* ----------------------------- CGU_BASE_UART1_CLK ----------------------------- */ +#define CGU_BASE_UART1_CLK_PD_Pos 0 /*!< CGU BASE_UART1_CLK: PD Position */ +#define CGU_BASE_UART1_CLK_PD_Msk (0x01UL << CGU_BASE_UART1_CLK_PD_Pos) /*!< CGU BASE_UART1_CLK: PD Mask */ +#define CGU_BASE_UART1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART1_CLK: AUTOBLOCK Position */ +#define CGU_BASE_UART1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART1_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_UART1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART1_CLK: CLK_SEL Position */ +#define CGU_BASE_UART1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART1_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART1_CLK: CLK_SEL Mask */ + +/* ----------------------------- CGU_BASE_UART2_CLK ----------------------------- */ +#define CGU_BASE_UART2_CLK_PD_Pos 0 /*!< CGU BASE_UART2_CLK: PD Position */ +#define CGU_BASE_UART2_CLK_PD_Msk (0x01UL << CGU_BASE_UART2_CLK_PD_Pos) /*!< CGU BASE_UART2_CLK: PD Mask */ +#define CGU_BASE_UART2_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART2_CLK: AUTOBLOCK Position */ +#define CGU_BASE_UART2_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART2_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART2_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_UART2_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART2_CLK: CLK_SEL Position */ +#define CGU_BASE_UART2_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART2_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART2_CLK: CLK_SEL Mask */ + +/* ----------------------------- CGU_BASE_UART3_CLK ----------------------------- */ +#define CGU_BASE_UART3_CLK_PD_Pos 0 /*!< CGU BASE_UART3_CLK: PD Position */ +#define CGU_BASE_UART3_CLK_PD_Msk (0x01UL << CGU_BASE_UART3_CLK_PD_Pos) /*!< CGU BASE_UART3_CLK: PD Mask */ +#define CGU_BASE_UART3_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART3_CLK: AUTOBLOCK Position */ +#define CGU_BASE_UART3_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART3_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART3_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_UART3_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART3_CLK: CLK_SEL Position */ +#define CGU_BASE_UART3_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART3_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART3_CLK: CLK_SEL Mask */ + +/* ------------------------------ CGU_BASE_OUT_CLK ------------------------------ */ +#define CGU_BASE_OUT_CLK_PD_Pos 0 /*!< CGU BASE_OUT_CLK: PD Position */ +#define CGU_BASE_OUT_CLK_PD_Msk (0x01UL << CGU_BASE_OUT_CLK_PD_Pos) /*!< CGU BASE_OUT_CLK: PD Mask */ +#define CGU_BASE_OUT_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_OUT_CLK: AUTOBLOCK Position */ +#define CGU_BASE_OUT_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_OUT_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_OUT_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_OUT_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_OUT_CLK: CLK_SEL Position */ +#define CGU_BASE_OUT_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_OUT_CLK_CLK_SEL_Pos) /*!< CGU BASE_OUT_CLK: CLK_SEL Mask */ + +/* ------------------------------ CGU_BASE_APLL_CLK ----------------------------- */ +#define CGU_BASE_APLL_CLK_PD_Pos 0 /*!< CGU BASE_APLL_CLK: PD Position */ +#define CGU_BASE_APLL_CLK_PD_Msk (0x01UL << CGU_BASE_APLL_CLK_PD_Pos) /*!< CGU BASE_APLL_CLK: PD Mask */ +#define CGU_BASE_APLL_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_APLL_CLK: AUTOBLOCK Position */ +#define CGU_BASE_APLL_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_APLL_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_APLL_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_APLL_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_APLL_CLK: CLK_SEL Position */ +#define CGU_BASE_APLL_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_APLL_CLK_CLK_SEL_Pos) /*!< CGU BASE_APLL_CLK: CLK_SEL Mask */ + +/* ---------------------------- CGU_BASE_CGU_OUT0_CLK --------------------------- */ +#define CGU_BASE_CGU_OUT0_CLK_PD_Pos 0 /*!< CGU BASE_CGU_OUT0_CLK: PD Position */ +#define CGU_BASE_CGU_OUT0_CLK_PD_Msk (0x01UL << CGU_BASE_CGU_OUT0_CLK_PD_Pos) /*!< CGU BASE_CGU_OUT0_CLK: PD Mask */ +#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Position */ +#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Position */ +#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos) /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Mask */ + +/* ---------------------------- CGU_BASE_CGU_OUT1_CLK --------------------------- */ +#define CGU_BASE_CGU_OUT1_CLK_PD_Pos 0 /*!< CGU BASE_CGU_OUT1_CLK: PD Position */ +#define CGU_BASE_CGU_OUT1_CLK_PD_Msk (0x01UL << CGU_BASE_CGU_OUT1_CLK_PD_Pos) /*!< CGU BASE_CGU_OUT1_CLK: PD Mask */ +#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Position */ +#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Mask */ +#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Position */ +#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos) /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Mask */ + + +/* ================================================================================ */ +/* ================ struct 'CCU1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------------- CCU1_PM ---------------------------------- */ +#define CCU1_PM_PD_Pos 0 /*!< CCU1 PM: PD Position */ +#define CCU1_PM_PD_Msk (0x01UL << CCU1_PM_PD_Pos) /*!< CCU1 PM: PD Mask */ + +/* ------------------------------- CCU1_BASE_STAT ------------------------------- */ +#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos 0 /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Position */ +#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Mask */ +#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos 1 /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Position */ +#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Mask */ +#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos 2 /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Position */ +#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Mask */ +#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos 3 /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Position */ +#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Mask */ +#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos 7 /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Position */ +#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Mask */ +#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos 8 /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Position */ +#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Mask */ + +/* ---------------------------- CCU1_CLK_APB3_BUS_CFG --------------------------- */ +#define CCU1_CLK_APB3_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_BUS_CFG: RUN Position */ +#define CCU1_CLK_APB3_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_BUS_CFG: RUN Mask */ +#define CCU1_CLK_APB3_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Position */ +#define CCU1_CLK_APB3_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Mask */ +#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Position */ +#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_APB3_BUS_STAT --------------------------- */ +#define CCU1_CLK_APB3_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_BUS_STAT: RUN Position */ +#define CCU1_CLK_APB3_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_BUS_STAT: RUN Mask */ +#define CCU1_CLK_APB3_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Position */ +#define CCU1_CLK_APB3_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Mask */ +#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Position */ +#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_APB3_I2C1_CFG --------------------------- */ +#define CCU1_CLK_APB3_I2C1_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Position */ +#define CCU1_CLK_APB3_I2C1_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_I2C1_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Mask */ +#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Position */ +#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Mask */ +#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Position */ +#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_APB3_I2C1_STAT -------------------------- */ +#define CCU1_CLK_APB3_I2C1_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Position */ +#define CCU1_CLK_APB3_I2C1_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_I2C1_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Mask */ +#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Position */ +#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Mask */ +#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Position */ +#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_APB3_DAC_CFG --------------------------- */ +#define CCU1_CLK_APB3_DAC_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_DAC_CFG: RUN Position */ +#define CCU1_CLK_APB3_DAC_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_DAC_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_DAC_CFG: RUN Mask */ +#define CCU1_CLK_APB3_DAC_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Position */ +#define CCU1_CLK_APB3_DAC_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_DAC_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Mask */ +#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Position */ +#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_APB3_DAC_STAT --------------------------- */ +#define CCU1_CLK_APB3_DAC_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_DAC_STAT: RUN Position */ +#define CCU1_CLK_APB3_DAC_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_DAC_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_DAC_STAT: RUN Mask */ +#define CCU1_CLK_APB3_DAC_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Position */ +#define CCU1_CLK_APB3_DAC_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_DAC_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Mask */ +#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Position */ +#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_APB3_ADC0_CFG --------------------------- */ +#define CCU1_CLK_APB3_ADC0_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Position */ +#define CCU1_CLK_APB3_ADC0_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC0_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Mask */ +#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Position */ +#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Mask */ +#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Position */ +#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_APB3_ADC0_STAT -------------------------- */ +#define CCU1_CLK_APB3_ADC0_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Position */ +#define CCU1_CLK_APB3_ADC0_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC0_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Mask */ +#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Position */ +#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Mask */ +#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Position */ +#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_APB3_ADC1_CFG --------------------------- */ +#define CCU1_CLK_APB3_ADC1_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Position */ +#define CCU1_CLK_APB3_ADC1_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC1_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Mask */ +#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Position */ +#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Mask */ +#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Position */ +#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_APB3_ADC1_STAT -------------------------- */ +#define CCU1_CLK_APB3_ADC1_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Position */ +#define CCU1_CLK_APB3_ADC1_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC1_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Mask */ +#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Position */ +#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Mask */ +#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Position */ +#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_APB3_CAN0_CFG --------------------------- */ +#define CCU1_CLK_APB3_CAN0_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Position */ +#define CCU1_CLK_APB3_CAN0_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_CAN0_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Mask */ +#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Position */ +#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Mask */ +#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Position */ +#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_APB3_CAN0_STAT -------------------------- */ +#define CCU1_CLK_APB3_CAN0_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Position */ +#define CCU1_CLK_APB3_CAN0_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_CAN0_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Mask */ +#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Position */ +#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Mask */ +#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Position */ +#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_APB1_BUS_CFG --------------------------- */ +#define CCU1_CLK_APB1_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_BUS_CFG: RUN Position */ +#define CCU1_CLK_APB1_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_BUS_CFG: RUN Mask */ +#define CCU1_CLK_APB1_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Position */ +#define CCU1_CLK_APB1_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Mask */ +#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Position */ +#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_APB1_BUS_STAT --------------------------- */ +#define CCU1_CLK_APB1_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_BUS_STAT: RUN Position */ +#define CCU1_CLK_APB1_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_BUS_STAT: RUN Mask */ +#define CCU1_CLK_APB1_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Position */ +#define CCU1_CLK_APB1_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Mask */ +#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Position */ +#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Mask */ + +/* ------------------------ CCU1_CLK_APB1_MOTOCONPWM_CFG ------------------------ */ +#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Position */ +#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Mask */ +#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Position */ +#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Mask */ +#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Position */ +#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Mask */ + +/* ------------------------ CCU1_CLK_APB1_MOTOCONPWM_STAT ----------------------- */ +#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Position */ +#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Mask */ +#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Position */ +#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Mask */ +#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Position */ +#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_APB1_I2C0_CFG --------------------------- */ +#define CCU1_CLK_APB1_I2C0_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2C0_CFG: RUN Position */ +#define CCU1_CLK_APB1_I2C0_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2C0_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_I2C0_CFG: RUN Mask */ +#define CCU1_CLK_APB1_I2C0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2C0_CFG: AUTO Position */ +#define CCU1_CLK_APB1_I2C0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2C0_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_I2C0_CFG: AUTO Mask */ +#define CCU1_CLK_APB1_I2C0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2C0_CFG: WAKEUP Position */ +#define CCU1_CLK_APB1_I2C0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2C0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2C0_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_APB1_I2C0_STAT -------------------------- */ +#define CCU1_CLK_APB1_I2C0_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Position */ +#define CCU1_CLK_APB1_I2C0_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2C0_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Mask */ +#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Position */ +#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Mask */ +#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Position */ +#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_APB1_I2S_CFG --------------------------- */ +#define CCU1_CLK_APB1_I2S_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2S_CFG: RUN Position */ +#define CCU1_CLK_APB1_I2S_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2S_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_I2S_CFG: RUN Mask */ +#define CCU1_CLK_APB1_I2S_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Position */ +#define CCU1_CLK_APB1_I2S_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2S_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Mask */ +#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Position */ +#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_APB1_I2S_STAT --------------------------- */ +#define CCU1_CLK_APB1_I2S_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2S_STAT: RUN Position */ +#define CCU1_CLK_APB1_I2S_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2S_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_I2S_STAT: RUN Mask */ +#define CCU1_CLK_APB1_I2S_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Position */ +#define CCU1_CLK_APB1_I2S_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2S_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Mask */ +#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Position */ +#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_APB1_CAN1_CFG --------------------------- */ +#define CCU1_CLK_APB1_CAN1_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Position */ +#define CCU1_CLK_APB1_CAN1_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_CAN1_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Mask */ +#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Position */ +#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Mask */ +#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Position */ +#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_APB1_CAN1_STAT -------------------------- */ +#define CCU1_CLK_APB1_CAN1_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Position */ +#define CCU1_CLK_APB1_CAN1_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_CAN1_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Mask */ +#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Position */ +#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Mask */ +#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Position */ +#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Mask */ + +/* ----------------------------- CCU1_CLK_SPIFI_CFG ----------------------------- */ +#define CCU1_CLK_SPIFI_CFG_RUN_Pos 0 /*!< CCU1 CLK_SPIFI_CFG: RUN Position */ +#define CCU1_CLK_SPIFI_CFG_RUN_Msk (0x01UL << CCU1_CLK_SPIFI_CFG_RUN_Pos) /*!< CCU1 CLK_SPIFI_CFG: RUN Mask */ +#define CCU1_CLK_SPIFI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_SPIFI_CFG: AUTO Position */ +#define CCU1_CLK_SPIFI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_SPIFI_CFG_AUTO_Pos) /*!< CCU1 CLK_SPIFI_CFG: AUTO Mask */ +#define CCU1_CLK_SPIFI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Position */ +#define CCU1_CLK_SPIFI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_SPIFI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Mask */ + +/* ----------------------------- CCU1_CLK_SPIFI_STAT ---------------------------- */ +#define CCU1_CLK_SPIFI_STAT_RUN_Pos 0 /*!< CCU1 CLK_SPIFI_STAT: RUN Position */ +#define CCU1_CLK_SPIFI_STAT_RUN_Msk (0x01UL << CCU1_CLK_SPIFI_STAT_RUN_Pos) /*!< CCU1 CLK_SPIFI_STAT: RUN Mask */ +#define CCU1_CLK_SPIFI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_SPIFI_STAT: AUTO Position */ +#define CCU1_CLK_SPIFI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_SPIFI_STAT_AUTO_Pos) /*!< CCU1 CLK_SPIFI_STAT: AUTO Mask */ +#define CCU1_CLK_SPIFI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Position */ +#define CCU1_CLK_SPIFI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_SPIFI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Mask */ + +/* ----------------------------- CCU1_CLK_M4_BUS_CFG ---------------------------- */ +#define CCU1_CLK_M4_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_BUS_CFG: RUN Position */ +#define CCU1_CLK_M4_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_M4_BUS_CFG: RUN Mask */ +#define CCU1_CLK_M4_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_BUS_CFG: AUTO Position */ +#define CCU1_CLK_M4_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_BUS_CFG: AUTO Mask */ +#define CCU1_CLK_M4_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_BUS_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_BUS_CFG: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_BUS_STAT ---------------------------- */ +#define CCU1_CLK_M4_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_BUS_STAT: RUN Position */ +#define CCU1_CLK_M4_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_M4_BUS_STAT: RUN Mask */ +#define CCU1_CLK_M4_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_BUS_STAT: AUTO Position */ +#define CCU1_CLK_M4_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_BUS_STAT: AUTO Mask */ +#define CCU1_CLK_M4_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_BUS_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_BUS_STAT: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_SPIFI_CFG --------------------------- */ +#define CCU1_CLK_M4_SPIFI_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SPIFI_CFG: RUN Position */ +#define CCU1_CLK_M4_SPIFI_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SPIFI_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SPIFI_CFG: RUN Mask */ +#define CCU1_CLK_M4_SPIFI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SPIFI_CFG: AUTO Position */ +#define CCU1_CLK_M4_SPIFI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SPIFI_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SPIFI_CFG: AUTO Mask */ +#define CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SPIFI_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SPIFI_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_SPIFI_STAT --------------------------- */ +#define CCU1_CLK_M4_SPIFI_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SPIFI_STAT: RUN Position */ +#define CCU1_CLK_M4_SPIFI_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SPIFI_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SPIFI_STAT: RUN Mask */ +#define CCU1_CLK_M4_SPIFI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SPIFI_STAT: AUTO Position */ +#define CCU1_CLK_M4_SPIFI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SPIFI_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SPIFI_STAT: AUTO Mask */ +#define CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SPIFI_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SPIFI_STAT: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_GPIO_CFG ---------------------------- */ +#define CCU1_CLK_M4_GPIO_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_GPIO_CFG: RUN Position */ +#define CCU1_CLK_M4_GPIO_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_GPIO_CFG_RUN_Pos) /*!< CCU1 CLK_M4_GPIO_CFG: RUN Mask */ +#define CCU1_CLK_M4_GPIO_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_GPIO_CFG: AUTO Position */ +#define CCU1_CLK_M4_GPIO_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_GPIO_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_GPIO_CFG: AUTO Mask */ +#define CCU1_CLK_M4_GPIO_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_GPIO_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_GPIO_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_GPIO_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_GPIO_CFG: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_GPIO_STAT --------------------------- */ +#define CCU1_CLK_M4_GPIO_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_GPIO_STAT: RUN Position */ +#define CCU1_CLK_M4_GPIO_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_GPIO_STAT_RUN_Pos) /*!< CCU1 CLK_M4_GPIO_STAT: RUN Mask */ +#define CCU1_CLK_M4_GPIO_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_GPIO_STAT: AUTO Position */ +#define CCU1_CLK_M4_GPIO_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_GPIO_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_GPIO_STAT: AUTO Mask */ +#define CCU1_CLK_M4_GPIO_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_GPIO_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_GPIO_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_GPIO_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_GPIO_STAT: WAKEUP Mask */ + +/* ----------------------------- CCU1_CLK_M4_LCD_CFG ---------------------------- */ +#define CCU1_CLK_M4_LCD_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_LCD_CFG: RUN Position */ +#define CCU1_CLK_M4_LCD_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_LCD_CFG_RUN_Pos) /*!< CCU1 CLK_M4_LCD_CFG: RUN Mask */ +#define CCU1_CLK_M4_LCD_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_LCD_CFG: AUTO Position */ +#define CCU1_CLK_M4_LCD_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_LCD_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_LCD_CFG: AUTO Mask */ +#define CCU1_CLK_M4_LCD_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_LCD_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_LCD_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_LCD_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_LCD_CFG: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_LCD_STAT ---------------------------- */ +#define CCU1_CLK_M4_LCD_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_LCD_STAT: RUN Position */ +#define CCU1_CLK_M4_LCD_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_LCD_STAT_RUN_Pos) /*!< CCU1 CLK_M4_LCD_STAT: RUN Mask */ +#define CCU1_CLK_M4_LCD_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_LCD_STAT: AUTO Position */ +#define CCU1_CLK_M4_LCD_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_LCD_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_LCD_STAT: AUTO Mask */ +#define CCU1_CLK_M4_LCD_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_LCD_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_LCD_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_LCD_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_LCD_STAT: WAKEUP Mask */ + +/* -------------------------- CCU1_CLK_M4_ETHERNET_CFG -------------------------- */ +#define CCU1_CLK_M4_ETHERNET_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_ETHERNET_CFG: RUN Position */ +#define CCU1_CLK_M4_ETHERNET_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_RUN_Pos) /*!< CCU1 CLK_M4_ETHERNET_CFG: RUN Mask */ +#define CCU1_CLK_M4_ETHERNET_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_ETHERNET_CFG: AUTO Position */ +#define CCU1_CLK_M4_ETHERNET_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_ETHERNET_CFG: AUTO Mask */ +#define CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_ETHERNET_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_ETHERNET_CFG: WAKEUP Mask */ + +/* -------------------------- CCU1_CLK_M4_ETHERNET_STAT ------------------------- */ +#define CCU1_CLK_M4_ETHERNET_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_ETHERNET_STAT: RUN Position */ +#define CCU1_CLK_M4_ETHERNET_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_RUN_Pos) /*!< CCU1 CLK_M4_ETHERNET_STAT: RUN Mask */ +#define CCU1_CLK_M4_ETHERNET_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_ETHERNET_STAT: AUTO Position */ +#define CCU1_CLK_M4_ETHERNET_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_ETHERNET_STAT: AUTO Mask */ +#define CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_ETHERNET_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_ETHERNET_STAT: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_USB0_CFG ---------------------------- */ +#define CCU1_CLK_M4_USB0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_USB0_CFG: RUN Position */ +#define CCU1_CLK_M4_USB0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_USB0_CFG_RUN_Pos) /*!< CCU1 CLK_M4_USB0_CFG: RUN Mask */ +#define CCU1_CLK_M4_USB0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_USB0_CFG: AUTO Position */ +#define CCU1_CLK_M4_USB0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_USB0_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_USB0_CFG: AUTO Mask */ +#define CCU1_CLK_M4_USB0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USB0_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_USB0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USB0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_USB0_CFG: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_USB0_STAT --------------------------- */ +#define CCU1_CLK_M4_USB0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_USB0_STAT: RUN Position */ +#define CCU1_CLK_M4_USB0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_USB0_STAT_RUN_Pos) /*!< CCU1 CLK_M4_USB0_STAT: RUN Mask */ +#define CCU1_CLK_M4_USB0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_USB0_STAT: AUTO Position */ +#define CCU1_CLK_M4_USB0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_USB0_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_USB0_STAT: AUTO Mask */ +#define CCU1_CLK_M4_USB0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USB0_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_USB0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USB0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_USB0_STAT: WAKEUP Mask */ + +/* ----------------------------- CCU1_CLK_M4_EMC_CFG ---------------------------- */ +#define CCU1_CLK_M4_EMC_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_EMC_CFG: RUN Position */ +#define CCU1_CLK_M4_EMC_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_EMC_CFG_RUN_Pos) /*!< CCU1 CLK_M4_EMC_CFG: RUN Mask */ +#define CCU1_CLK_M4_EMC_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_EMC_CFG: AUTO Position */ +#define CCU1_CLK_M4_EMC_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_EMC_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_EMC_CFG: AUTO Mask */ +#define CCU1_CLK_M4_EMC_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_EMC_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_EMC_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_EMC_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_EMC_CFG: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_EMC_STAT ---------------------------- */ +#define CCU1_CLK_M4_EMC_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_EMC_STAT: RUN Position */ +#define CCU1_CLK_M4_EMC_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_EMC_STAT_RUN_Pos) /*!< CCU1 CLK_M4_EMC_STAT: RUN Mask */ +#define CCU1_CLK_M4_EMC_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_EMC_STAT: AUTO Position */ +#define CCU1_CLK_M4_EMC_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_EMC_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_EMC_STAT: AUTO Mask */ +#define CCU1_CLK_M4_EMC_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_EMC_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_EMC_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_EMC_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_EMC_STAT: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_SDIO_CFG ---------------------------- */ +#define CCU1_CLK_M4_SDIO_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SDIO_CFG: RUN Position */ +#define CCU1_CLK_M4_SDIO_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SDIO_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SDIO_CFG: RUN Mask */ +#define CCU1_CLK_M4_SDIO_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SDIO_CFG: AUTO Position */ +#define CCU1_CLK_M4_SDIO_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SDIO_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SDIO_CFG: AUTO Mask */ +#define CCU1_CLK_M4_SDIO_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SDIO_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_SDIO_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SDIO_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SDIO_CFG: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_SDIO_STAT --------------------------- */ +#define CCU1_CLK_M4_SDIO_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SDIO_STAT: RUN Position */ +#define CCU1_CLK_M4_SDIO_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SDIO_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SDIO_STAT: RUN Mask */ +#define CCU1_CLK_M4_SDIO_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SDIO_STAT: AUTO Position */ +#define CCU1_CLK_M4_SDIO_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SDIO_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SDIO_STAT: AUTO Mask */ +#define CCU1_CLK_M4_SDIO_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SDIO_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_SDIO_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SDIO_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SDIO_STAT: WAKEUP Mask */ + +/* ----------------------------- CCU1_CLK_M4_DMA_CFG ---------------------------- */ +#define CCU1_CLK_M4_DMA_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_DMA_CFG: RUN Position */ +#define CCU1_CLK_M4_DMA_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_DMA_CFG_RUN_Pos) /*!< CCU1 CLK_M4_DMA_CFG: RUN Mask */ +#define CCU1_CLK_M4_DMA_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_DMA_CFG: AUTO Position */ +#define CCU1_CLK_M4_DMA_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_DMA_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_DMA_CFG: AUTO Mask */ +#define CCU1_CLK_M4_DMA_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_DMA_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_DMA_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_DMA_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_DMA_CFG: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_DMA_STAT ---------------------------- */ +#define CCU1_CLK_M4_DMA_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_DMA_STAT: RUN Position */ +#define CCU1_CLK_M4_DMA_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_DMA_STAT_RUN_Pos) /*!< CCU1 CLK_M4_DMA_STAT: RUN Mask */ +#define CCU1_CLK_M4_DMA_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_DMA_STAT: AUTO Position */ +#define CCU1_CLK_M4_DMA_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_DMA_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_DMA_STAT: AUTO Mask */ +#define CCU1_CLK_M4_DMA_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_DMA_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_DMA_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_DMA_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_DMA_STAT: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_M4CORE_CFG --------------------------- */ +#define CCU1_CLK_M4_M4CORE_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_M4CORE_CFG: RUN Position */ +#define CCU1_CLK_M4_M4CORE_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_M4CORE_CFG_RUN_Pos) /*!< CCU1 CLK_M4_M4CORE_CFG: RUN Mask */ +#define CCU1_CLK_M4_M4CORE_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_M4CORE_CFG: AUTO Position */ +#define CCU1_CLK_M4_M4CORE_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_M4CORE_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_M4CORE_CFG: AUTO Mask */ +#define CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_M4CORE_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_M4CORE_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_M4CORE_STAT -------------------------- */ +#define CCU1_CLK_M4_M4CORE_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_M4CORE_STAT: RUN Position */ +#define CCU1_CLK_M4_M4CORE_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_M4CORE_STAT_RUN_Pos) /*!< CCU1 CLK_M4_M4CORE_STAT: RUN Mask */ +#define CCU1_CLK_M4_M4CORE_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_M4CORE_STAT: AUTO Position */ +#define CCU1_CLK_M4_M4CORE_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_M4CORE_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_M4CORE_STAT: AUTO Mask */ +#define CCU1_CLK_M4_M4CORE_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_M4CORE_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_M4CORE_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_M4CORE_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_M4CORE_STAT: WAKEUP Mask */ + +/* ----------------------------- CCU1_CLK_M4_SCT_CFG ---------------------------- */ +#define CCU1_CLK_M4_SCT_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SCT_CFG: RUN Position */ +#define CCU1_CLK_M4_SCT_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SCT_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SCT_CFG: RUN Mask */ +#define CCU1_CLK_M4_SCT_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SCT_CFG: AUTO Position */ +#define CCU1_CLK_M4_SCT_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SCT_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SCT_CFG: AUTO Mask */ +#define CCU1_CLK_M4_SCT_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SCT_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_SCT_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SCT_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SCT_CFG: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_SCT_STAT ---------------------------- */ +#define CCU1_CLK_M4_SCT_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SCT_STAT: RUN Position */ +#define CCU1_CLK_M4_SCT_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SCT_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SCT_STAT: RUN Mask */ +#define CCU1_CLK_M4_SCT_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SCT_STAT: AUTO Position */ +#define CCU1_CLK_M4_SCT_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SCT_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SCT_STAT: AUTO Mask */ +#define CCU1_CLK_M4_SCT_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SCT_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_SCT_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SCT_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SCT_STAT: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_USB1_CFG ---------------------------- */ +#define CCU1_CLK_M4_USB1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_USB1_CFG: RUN Position */ +#define CCU1_CLK_M4_USB1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_USB1_CFG_RUN_Pos) /*!< CCU1 CLK_M4_USB1_CFG: RUN Mask */ +#define CCU1_CLK_M4_USB1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_USB1_CFG: AUTO Position */ +#define CCU1_CLK_M4_USB1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_USB1_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_USB1_CFG: AUTO Mask */ +#define CCU1_CLK_M4_USB1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USB1_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_USB1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USB1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_USB1_CFG: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_USB1_STAT --------------------------- */ +#define CCU1_CLK_M4_USB1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_USB1_STAT: RUN Position */ +#define CCU1_CLK_M4_USB1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_USB1_STAT_RUN_Pos) /*!< CCU1 CLK_M4_USB1_STAT: RUN Mask */ +#define CCU1_CLK_M4_USB1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_USB1_STAT: AUTO Position */ +#define CCU1_CLK_M4_USB1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_USB1_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_USB1_STAT: AUTO Mask */ +#define CCU1_CLK_M4_USB1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USB1_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_USB1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USB1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_USB1_STAT: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_EMCDIV_CFG --------------------------- */ +#define CCU1_CLK_M4_EMCDIV_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_EMCDIV_CFG: RUN Position */ +#define CCU1_CLK_M4_EMCDIV_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_RUN_Pos) /*!< CCU1 CLK_M4_EMCDIV_CFG: RUN Mask */ +#define CCU1_CLK_M4_EMCDIV_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_EMCDIV_CFG: AUTO Position */ +#define CCU1_CLK_M4_EMCDIV_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_EMCDIV_CFG: AUTO Mask */ +#define CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_EMCDIV_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_EMCDIV_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_EMCDIV_STAT -------------------------- */ +#define CCU1_CLK_M4_EMCDIV_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_EMCDIV_STAT: RUN Position */ +#define CCU1_CLK_M4_EMCDIV_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_RUN_Pos) /*!< CCU1 CLK_M4_EMCDIV_STAT: RUN Mask */ +#define CCU1_CLK_M4_EMCDIV_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_EMCDIV_STAT: AUTO Position */ +#define CCU1_CLK_M4_EMCDIV_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_EMCDIV_STAT: AUTO Mask */ +#define CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_EMCDIV_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_EMCDIV_STAT: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_FLASHA_CFG --------------------------- */ +#define CCU1_CLK_M4_FLASHA_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_FLASHA_CFG: RUN Position */ +#define CCU1_CLK_M4_FLASHA_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_FLASHA_CFG_RUN_Pos) /*!< CCU1 CLK_M4_FLASHA_CFG: RUN Mask */ +#define CCU1_CLK_M4_FLASHA_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_FLASHA_CFG: AUTO Position */ +#define CCU1_CLK_M4_FLASHA_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_FLASHA_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_FLASHA_CFG: AUTO Mask */ +#define CCU1_CLK_M4_FLASHA_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_FLASHA_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_FLASHA_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_FLASHA_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_FLASHA_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_FLASHA_STAT -------------------------- */ +#define CCU1_CLK_M4_FLASHA_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_FLASHA_STAT: RUN Position */ +#define CCU1_CLK_M4_FLASHA_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_FLASHA_STAT_RUN_Pos) /*!< CCU1 CLK_M4_FLASHA_STAT: RUN Mask */ +#define CCU1_CLK_M4_FLASHA_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_FLASHA_STAT: AUTO Position */ +#define CCU1_CLK_M4_FLASHA_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_FLASHA_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_FLASHA_STAT: AUTO Mask */ +#define CCU1_CLK_M4_FLASHA_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_FLASHA_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_FLASHA_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_FLASHA_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_FLASHA_STAT: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_FLASHB_CFG --------------------------- */ +#define CCU1_CLK_M4_FLASHB_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_FLASHB_CFG: RUN Position */ +#define CCU1_CLK_M4_FLASHB_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_FLASHB_CFG_RUN_Pos) /*!< CCU1 CLK_M4_FLASHB_CFG: RUN Mask */ +#define CCU1_CLK_M4_FLASHB_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_FLASHB_CFG: AUTO Position */ +#define CCU1_CLK_M4_FLASHB_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_FLASHB_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_FLASHB_CFG: AUTO Mask */ +#define CCU1_CLK_M4_FLASHB_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_FLASHB_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_FLASHB_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_FLASHB_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_FLASHB_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_FLASHB_STAT -------------------------- */ +#define CCU1_CLK_M4_FLASHB_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_FLASHB_STAT: RUN Position */ +#define CCU1_CLK_M4_FLASHB_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_FLASHB_STAT_RUN_Pos) /*!< CCU1 CLK_M4_FLASHB_STAT: RUN Mask */ +#define CCU1_CLK_M4_FLASHB_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_FLASHB_STAT: AUTO Position */ +#define CCU1_CLK_M4_FLASHB_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_FLASHB_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_FLASHB_STAT: AUTO Mask */ +#define CCU1_CLK_M4_FLASHB_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_FLASHB_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_FLASHB_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_FLASHB_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_FLASHB_STAT: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_M0APP_CFG --------------------------- */ +#define CCU1_CLK_M4_M0APP_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_M0APP_CFG: RUN Position */ +#define CCU1_CLK_M4_M0APP_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_M0APP_CFG_RUN_Pos) /*!< CCU1 CLK_M4_M0APP_CFG: RUN Mask */ +#define CCU1_CLK_M4_M0APP_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_M0APP_CFG: AUTO Position */ +#define CCU1_CLK_M4_M0APP_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_M0APP_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_M0APP_CFG: AUTO Mask */ +#define CCU1_CLK_M4_M0APP_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_M0APP_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_M0APP_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_M0APP_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_M0APP_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_M0APP_STAT --------------------------- */ +#define CCU1_CLK_M4_M0APP_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_M0APP_STAT: RUN Position */ +#define CCU1_CLK_M4_M0APP_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_M0APP_STAT_RUN_Pos) /*!< CCU1 CLK_M4_M0APP_STAT: RUN Mask */ +#define CCU1_CLK_M4_M0APP_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_M0APP_STAT: AUTO Position */ +#define CCU1_CLK_M4_M0APP_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_M0APP_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_M0APP_STAT: AUTO Mask */ +#define CCU1_CLK_M4_M0APP_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_M0APP_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_M0APP_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_M0APP_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_M0APP_STAT: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_ADCHS_CFG --------------------------- */ +#define CCU1_CLK_M4_ADCHS_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_ADCHS_CFG: RUN Position */ +#define CCU1_CLK_M4_ADCHS_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_ADCHS_CFG_RUN_Pos) /*!< CCU1 CLK_M4_ADCHS_CFG: RUN Mask */ +#define CCU1_CLK_M4_ADCHS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_ADCHS_CFG: AUTO Position */ +#define CCU1_CLK_M4_ADCHS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_ADCHS_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_ADCHS_CFG: AUTO Mask */ +#define CCU1_CLK_M4_ADCHS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_ADCHS_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_ADCHS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_ADCHS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_ADCHS_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_ADCHS_STAT --------------------------- */ +#define CCU1_CLK_M4_ADCHS_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_ADCHS_STAT: RUN Position */ +#define CCU1_CLK_M4_ADCHS_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_ADCHS_STAT_RUN_Pos) /*!< CCU1 CLK_M4_ADCHS_STAT: RUN Mask */ +#define CCU1_CLK_M4_ADCHS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_ADCHS_STAT: AUTO Position */ +#define CCU1_CLK_M4_ADCHS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_ADCHS_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_ADCHS_STAT: AUTO Mask */ +#define CCU1_CLK_M4_ADCHS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_ADCHS_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_ADCHS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_ADCHS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_ADCHS_STAT: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_EEPROM_CFG --------------------------- */ +#define CCU1_CLK_M4_EEPROM_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_EEPROM_CFG: RUN Position */ +#define CCU1_CLK_M4_EEPROM_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_EEPROM_CFG_RUN_Pos) /*!< CCU1 CLK_M4_EEPROM_CFG: RUN Mask */ +#define CCU1_CLK_M4_EEPROM_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_EEPROM_CFG: AUTO Position */ +#define CCU1_CLK_M4_EEPROM_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_EEPROM_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_EEPROM_CFG: AUTO Mask */ +#define CCU1_CLK_M4_EEPROM_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_EEPROM_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_EEPROM_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_EEPROM_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_EEPROM_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_EEPROM_STAT -------------------------- */ +#define CCU1_CLK_M4_EEPROM_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_EEPROM_STAT: RUN Position */ +#define CCU1_CLK_M4_EEPROM_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_EEPROM_STAT_RUN_Pos) /*!< CCU1 CLK_M4_EEPROM_STAT: RUN Mask */ +#define CCU1_CLK_M4_EEPROM_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_EEPROM_STAT: AUTO Position */ +#define CCU1_CLK_M4_EEPROM_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_EEPROM_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_EEPROM_STAT: AUTO Mask */ +#define CCU1_CLK_M4_EEPROM_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_EEPROM_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_EEPROM_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_EEPROM_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_EEPROM_STAT: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_WWDT_CFG ---------------------------- */ +#define CCU1_CLK_M4_WWDT_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_WWDT_CFG: RUN Position */ +#define CCU1_CLK_M4_WWDT_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_WWDT_CFG_RUN_Pos) /*!< CCU1 CLK_M4_WWDT_CFG: RUN Mask */ +#define CCU1_CLK_M4_WWDT_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_WWDT_CFG: AUTO Position */ +#define CCU1_CLK_M4_WWDT_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_WWDT_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_WWDT_CFG: AUTO Mask */ +#define CCU1_CLK_M4_WWDT_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_WWDT_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_WWDT_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_WWDT_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_WWDT_CFG: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_WWDT_STAT --------------------------- */ +#define CCU1_CLK_M4_WWDT_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_WWDT_STAT: RUN Position */ +#define CCU1_CLK_M4_WWDT_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_WWDT_STAT_RUN_Pos) /*!< CCU1 CLK_M4_WWDT_STAT: RUN Mask */ +#define CCU1_CLK_M4_WWDT_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_WWDT_STAT: AUTO Position */ +#define CCU1_CLK_M4_WWDT_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_WWDT_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_WWDT_STAT: AUTO Mask */ +#define CCU1_CLK_M4_WWDT_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_WWDT_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_WWDT_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_WWDT_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_WWDT_STAT: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_USART0_CFG --------------------------- */ +#define CCU1_CLK_M4_USART0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_USART0_CFG: RUN Position */ +#define CCU1_CLK_M4_USART0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_USART0_CFG_RUN_Pos) /*!< CCU1 CLK_M4_USART0_CFG: RUN Mask */ +#define CCU1_CLK_M4_USART0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART0_CFG: AUTO Position */ +#define CCU1_CLK_M4_USART0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART0_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_USART0_CFG: AUTO Mask */ +#define CCU1_CLK_M4_USART0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART0_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_USART0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART0_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_USART0_STAT -------------------------- */ +#define CCU1_CLK_M4_USART0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_USART0_STAT: RUN Position */ +#define CCU1_CLK_M4_USART0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_USART0_STAT_RUN_Pos) /*!< CCU1 CLK_M4_USART0_STAT: RUN Mask */ +#define CCU1_CLK_M4_USART0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART0_STAT: AUTO Position */ +#define CCU1_CLK_M4_USART0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART0_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_USART0_STAT: AUTO Mask */ +#define CCU1_CLK_M4_USART0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART0_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_USART0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART0_STAT: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_UART1_CFG --------------------------- */ +#define CCU1_CLK_M4_UART1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_UART1_CFG: RUN Position */ +#define CCU1_CLK_M4_UART1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_UART1_CFG_RUN_Pos) /*!< CCU1 CLK_M4_UART1_CFG: RUN Mask */ +#define CCU1_CLK_M4_UART1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_UART1_CFG: AUTO Position */ +#define CCU1_CLK_M4_UART1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_UART1_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_UART1_CFG: AUTO Mask */ +#define CCU1_CLK_M4_UART1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_UART1_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_UART1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_UART1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_UART1_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_UART1_STAT --------------------------- */ +#define CCU1_CLK_M4_UART1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_UART1_STAT: RUN Position */ +#define CCU1_CLK_M4_UART1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_UART1_STAT_RUN_Pos) /*!< CCU1 CLK_M4_UART1_STAT: RUN Mask */ +#define CCU1_CLK_M4_UART1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_UART1_STAT: AUTO Position */ +#define CCU1_CLK_M4_UART1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_UART1_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_UART1_STAT: AUTO Mask */ +#define CCU1_CLK_M4_UART1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_UART1_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_UART1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_UART1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_UART1_STAT: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_SSP0_CFG ---------------------------- */ +#define CCU1_CLK_M4_SSP0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SSP0_CFG: RUN Position */ +#define CCU1_CLK_M4_SSP0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SSP0_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SSP0_CFG: RUN Mask */ +#define CCU1_CLK_M4_SSP0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SSP0_CFG: AUTO Position */ +#define CCU1_CLK_M4_SSP0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SSP0_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SSP0_CFG: AUTO Mask */ +#define CCU1_CLK_M4_SSP0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SSP0_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_SSP0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SSP0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SSP0_CFG: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_SSP0_STAT --------------------------- */ +#define CCU1_CLK_M4_SSP0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SSP0_STAT: RUN Position */ +#define CCU1_CLK_M4_SSP0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SSP0_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SSP0_STAT: RUN Mask */ +#define CCU1_CLK_M4_SSP0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SSP0_STAT: AUTO Position */ +#define CCU1_CLK_M4_SSP0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SSP0_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SSP0_STAT: AUTO Mask */ +#define CCU1_CLK_M4_SSP0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SSP0_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_SSP0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SSP0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SSP0_STAT: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_TIMER0_CFG --------------------------- */ +#define CCU1_CLK_M4_TIMER0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER0_CFG: RUN Position */ +#define CCU1_CLK_M4_TIMER0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER0_CFG_RUN_Pos) /*!< CCU1 CLK_M4_TIMER0_CFG: RUN Mask */ +#define CCU1_CLK_M4_TIMER0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER0_CFG: AUTO Position */ +#define CCU1_CLK_M4_TIMER0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER0_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER0_CFG: AUTO Mask */ +#define CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER0_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER0_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_TIMER0_STAT -------------------------- */ +#define CCU1_CLK_M4_TIMER0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER0_STAT: RUN Position */ +#define CCU1_CLK_M4_TIMER0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER0_STAT_RUN_Pos) /*!< CCU1 CLK_M4_TIMER0_STAT: RUN Mask */ +#define CCU1_CLK_M4_TIMER0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER0_STAT: AUTO Position */ +#define CCU1_CLK_M4_TIMER0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER0_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER0_STAT: AUTO Mask */ +#define CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER0_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER0_STAT: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_TIMER1_CFG --------------------------- */ +#define CCU1_CLK_M4_TIMER1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER1_CFG: RUN Position */ +#define CCU1_CLK_M4_TIMER1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER1_CFG_RUN_Pos) /*!< CCU1 CLK_M4_TIMER1_CFG: RUN Mask */ +#define CCU1_CLK_M4_TIMER1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER1_CFG: AUTO Position */ +#define CCU1_CLK_M4_TIMER1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER1_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER1_CFG: AUTO Mask */ +#define CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER1_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER1_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_TIMER1_STAT -------------------------- */ +#define CCU1_CLK_M4_TIMER1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER1_STAT: RUN Position */ +#define CCU1_CLK_M4_TIMER1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER1_STAT_RUN_Pos) /*!< CCU1 CLK_M4_TIMER1_STAT: RUN Mask */ +#define CCU1_CLK_M4_TIMER1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER1_STAT: AUTO Position */ +#define CCU1_CLK_M4_TIMER1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER1_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER1_STAT: AUTO Mask */ +#define CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER1_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER1_STAT: WAKEUP Mask */ + +/* ----------------------------- CCU1_CLK_M4_SCU_CFG ---------------------------- */ +#define CCU1_CLK_M4_SCU_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SCU_CFG: RUN Position */ +#define CCU1_CLK_M4_SCU_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SCU_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SCU_CFG: RUN Mask */ +#define CCU1_CLK_M4_SCU_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SCU_CFG: AUTO Position */ +#define CCU1_CLK_M4_SCU_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SCU_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SCU_CFG: AUTO Mask */ +#define CCU1_CLK_M4_SCU_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SCU_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_SCU_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SCU_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SCU_CFG: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_SCU_STAT ---------------------------- */ +#define CCU1_CLK_M4_SCU_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SCU_STAT: RUN Position */ +#define CCU1_CLK_M4_SCU_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SCU_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SCU_STAT: RUN Mask */ +#define CCU1_CLK_M4_SCU_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SCU_STAT: AUTO Position */ +#define CCU1_CLK_M4_SCU_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SCU_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SCU_STAT: AUTO Mask */ +#define CCU1_CLK_M4_SCU_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SCU_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_SCU_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SCU_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SCU_STAT: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_CREG_CFG ---------------------------- */ +#define CCU1_CLK_M4_CREG_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_CREG_CFG: RUN Position */ +#define CCU1_CLK_M4_CREG_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_CREG_CFG_RUN_Pos) /*!< CCU1 CLK_M4_CREG_CFG: RUN Mask */ +#define CCU1_CLK_M4_CREG_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_CREG_CFG: AUTO Position */ +#define CCU1_CLK_M4_CREG_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_CREG_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_CREG_CFG: AUTO Mask */ +#define CCU1_CLK_M4_CREG_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_CREG_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_CREG_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_CREG_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_CREG_CFG: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_CREG_STAT --------------------------- */ +#define CCU1_CLK_M4_CREG_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_CREG_STAT: RUN Position */ +#define CCU1_CLK_M4_CREG_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_CREG_STAT_RUN_Pos) /*!< CCU1 CLK_M4_CREG_STAT: RUN Mask */ +#define CCU1_CLK_M4_CREG_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_CREG_STAT: AUTO Position */ +#define CCU1_CLK_M4_CREG_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_CREG_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_CREG_STAT: AUTO Mask */ +#define CCU1_CLK_M4_CREG_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_CREG_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_CREG_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_CREG_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_CREG_STAT: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_RITIMER_CFG -------------------------- */ +#define CCU1_CLK_M4_RITIMER_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_RITIMER_CFG: RUN Position */ +#define CCU1_CLK_M4_RITIMER_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_RITIMER_CFG_RUN_Pos) /*!< CCU1 CLK_M4_RITIMER_CFG: RUN Mask */ +#define CCU1_CLK_M4_RITIMER_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_RITIMER_CFG: AUTO Position */ +#define CCU1_CLK_M4_RITIMER_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_RITIMER_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_RITIMER_CFG: AUTO Mask */ +#define CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_RITIMER_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_RITIMER_CFG: WAKEUP Mask */ + +/* -------------------------- CCU1_CLK_M4_RITIMER_STAT -------------------------- */ +#define CCU1_CLK_M4_RITIMER_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_RITIMER_STAT: RUN Position */ +#define CCU1_CLK_M4_RITIMER_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_RITIMER_STAT_RUN_Pos) /*!< CCU1 CLK_M4_RITIMER_STAT: RUN Mask */ +#define CCU1_CLK_M4_RITIMER_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_RITIMER_STAT: AUTO Position */ +#define CCU1_CLK_M4_RITIMER_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_RITIMER_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_RITIMER_STAT: AUTO Mask */ +#define CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_RITIMER_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_RITIMER_STAT: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_USART2_CFG --------------------------- */ +#define CCU1_CLK_M4_USART2_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_USART2_CFG: RUN Position */ +#define CCU1_CLK_M4_USART2_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_USART2_CFG_RUN_Pos) /*!< CCU1 CLK_M4_USART2_CFG: RUN Mask */ +#define CCU1_CLK_M4_USART2_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART2_CFG: AUTO Position */ +#define CCU1_CLK_M4_USART2_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART2_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_USART2_CFG: AUTO Mask */ +#define CCU1_CLK_M4_USART2_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART2_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_USART2_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART2_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART2_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_USART2_STAT -------------------------- */ +#define CCU1_CLK_M4_USART2_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_USART2_STAT: RUN Position */ +#define CCU1_CLK_M4_USART2_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_USART2_STAT_RUN_Pos) /*!< CCU1 CLK_M4_USART2_STAT: RUN Mask */ +#define CCU1_CLK_M4_USART2_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART2_STAT: AUTO Position */ +#define CCU1_CLK_M4_USART2_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART2_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_USART2_STAT: AUTO Mask */ +#define CCU1_CLK_M4_USART2_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART2_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_USART2_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART2_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART2_STAT: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_USART3_CFG --------------------------- */ +#define CCU1_CLK_M4_USART3_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_USART3_CFG: RUN Position */ +#define CCU1_CLK_M4_USART3_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_USART3_CFG_RUN_Pos) /*!< CCU1 CLK_M4_USART3_CFG: RUN Mask */ +#define CCU1_CLK_M4_USART3_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART3_CFG: AUTO Position */ +#define CCU1_CLK_M4_USART3_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART3_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_USART3_CFG: AUTO Mask */ +#define CCU1_CLK_M4_USART3_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART3_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_USART3_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART3_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART3_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_USART3_STAT -------------------------- */ +#define CCU1_CLK_M4_USART3_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_USART3_STAT: RUN Position */ +#define CCU1_CLK_M4_USART3_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_USART3_STAT_RUN_Pos) /*!< CCU1 CLK_M4_USART3_STAT: RUN Mask */ +#define CCU1_CLK_M4_USART3_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART3_STAT: AUTO Position */ +#define CCU1_CLK_M4_USART3_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART3_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_USART3_STAT: AUTO Mask */ +#define CCU1_CLK_M4_USART3_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART3_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_USART3_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART3_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART3_STAT: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_TIMER2_CFG --------------------------- */ +#define CCU1_CLK_M4_TIMER2_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER2_CFG: RUN Position */ +#define CCU1_CLK_M4_TIMER2_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER2_CFG_RUN_Pos) /*!< CCU1 CLK_M4_TIMER2_CFG: RUN Mask */ +#define CCU1_CLK_M4_TIMER2_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER2_CFG: AUTO Position */ +#define CCU1_CLK_M4_TIMER2_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER2_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER2_CFG: AUTO Mask */ +#define CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER2_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER2_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_TIMER2_STAT -------------------------- */ +#define CCU1_CLK_M4_TIMER2_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER2_STAT: RUN Position */ +#define CCU1_CLK_M4_TIMER2_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER2_STAT_RUN_Pos) /*!< CCU1 CLK_M4_TIMER2_STAT: RUN Mask */ +#define CCU1_CLK_M4_TIMER2_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER2_STAT: AUTO Position */ +#define CCU1_CLK_M4_TIMER2_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER2_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER2_STAT: AUTO Mask */ +#define CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER2_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER2_STAT: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_TIMER3_CFG --------------------------- */ +#define CCU1_CLK_M4_TIMER3_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER3_CFG: RUN Position */ +#define CCU1_CLK_M4_TIMER3_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER3_CFG_RUN_Pos) /*!< CCU1 CLK_M4_TIMER3_CFG: RUN Mask */ +#define CCU1_CLK_M4_TIMER3_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER3_CFG: AUTO Position */ +#define CCU1_CLK_M4_TIMER3_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER3_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER3_CFG: AUTO Mask */ +#define CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER3_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER3_CFG: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_M4_TIMER3_STAT -------------------------- */ +#define CCU1_CLK_M4_TIMER3_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER3_STAT: RUN Position */ +#define CCU1_CLK_M4_TIMER3_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER3_STAT_RUN_Pos) /*!< CCU1 CLK_M4_TIMER3_STAT: RUN Mask */ +#define CCU1_CLK_M4_TIMER3_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER3_STAT: AUTO Position */ +#define CCU1_CLK_M4_TIMER3_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER3_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER3_STAT: AUTO Mask */ +#define CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER3_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER3_STAT: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_SSP1_CFG ---------------------------- */ +#define CCU1_CLK_M4_SSP1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SSP1_CFG: RUN Position */ +#define CCU1_CLK_M4_SSP1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SSP1_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SSP1_CFG: RUN Mask */ +#define CCU1_CLK_M4_SSP1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SSP1_CFG: AUTO Position */ +#define CCU1_CLK_M4_SSP1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SSP1_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SSP1_CFG: AUTO Mask */ +#define CCU1_CLK_M4_SSP1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SSP1_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_SSP1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SSP1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SSP1_CFG: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_SSP1_STAT --------------------------- */ +#define CCU1_CLK_M4_SSP1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SSP1_STAT: RUN Position */ +#define CCU1_CLK_M4_SSP1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SSP1_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SSP1_STAT: RUN Mask */ +#define CCU1_CLK_M4_SSP1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SSP1_STAT: AUTO Position */ +#define CCU1_CLK_M4_SSP1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SSP1_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SSP1_STAT: AUTO Mask */ +#define CCU1_CLK_M4_SSP1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SSP1_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_SSP1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SSP1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SSP1_STAT: WAKEUP Mask */ + +/* ----------------------------- CCU1_CLK_M4_QEI_CFG ---------------------------- */ +#define CCU1_CLK_M4_QEI_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_QEI_CFG: RUN Position */ +#define CCU1_CLK_M4_QEI_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_QEI_CFG_RUN_Pos) /*!< CCU1 CLK_M4_QEI_CFG: RUN Mask */ +#define CCU1_CLK_M4_QEI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_QEI_CFG: AUTO Position */ +#define CCU1_CLK_M4_QEI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_QEI_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_QEI_CFG: AUTO Mask */ +#define CCU1_CLK_M4_QEI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_QEI_CFG: WAKEUP Position */ +#define CCU1_CLK_M4_QEI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_QEI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_QEI_CFG: WAKEUP Mask */ + +/* ---------------------------- CCU1_CLK_M4_QEI_STAT ---------------------------- */ +#define CCU1_CLK_M4_QEI_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_QEI_STAT: RUN Position */ +#define CCU1_CLK_M4_QEI_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_QEI_STAT_RUN_Pos) /*!< CCU1 CLK_M4_QEI_STAT: RUN Mask */ +#define CCU1_CLK_M4_QEI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_QEI_STAT: AUTO Position */ +#define CCU1_CLK_M4_QEI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_QEI_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_QEI_STAT: AUTO Mask */ +#define CCU1_CLK_M4_QEI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_QEI_STAT: WAKEUP Position */ +#define CCU1_CLK_M4_QEI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_QEI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_QEI_STAT: WAKEUP Mask */ + +/* --------------------------- CCU1_CLK_PERIPH_BUS_CFG -------------------------- */ +#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Position */ +#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Mask */ +#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Position */ +#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Mask */ +#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Position */ +#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Mask */ + +/* -------------------------- CCU1_CLK_PERIPH_BUS_STAT -------------------------- */ +#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Position */ +#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Mask */ +#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Position */ +#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Mask */ +#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Position */ +#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Mask */ + +/* -------------------------- CCU1_CLK_PERIPH_CORE_CFG -------------------------- */ +#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Position */ +#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos) /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Mask */ +#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Position */ +#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos) /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Mask */ +#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Position */ +#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Mask */ + +/* -------------------------- CCU1_CLK_PERIPH_CORE_STAT ------------------------- */ +#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Position */ +#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos) /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Mask */ +#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Position */ +#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos) /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Mask */ +#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Position */ +#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Mask */ + +/* -------------------------- CCU1_CLK_PERIPH_SGPIO_CFG ------------------------- */ +#define CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_SGPIO_CFG: RUN Position */ +#define CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_CFG: RUN Mask */ +#define CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_SGPIO_CFG: AUTO Position */ +#define CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_CFG: AUTO Mask */ +#define CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_SGPIO_CFG: WAKEUP Position */ +#define CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_CFG: WAKEUP Mask */ + +/* ------------------------- CCU1_CLK_PERIPH_SGPIO_STAT ------------------------- */ +#define CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_SGPIO_STAT: RUN Position */ +#define CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_STAT: RUN Mask */ +#define CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_SGPIO_STAT: AUTO Position */ +#define CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_STAT: AUTO Mask */ +#define CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_SGPIO_STAT: WAKEUP Position */ +#define CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_STAT: WAKEUP Mask */ + +/* ------------------------------ CCU1_CLK_USB0_CFG ----------------------------- */ +#define CCU1_CLK_USB0_CFG_RUN_Pos 0 /*!< CCU1 CLK_USB0_CFG: RUN Position */ +#define CCU1_CLK_USB0_CFG_RUN_Msk (0x01UL << CCU1_CLK_USB0_CFG_RUN_Pos) /*!< CCU1 CLK_USB0_CFG: RUN Mask */ +#define CCU1_CLK_USB0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_USB0_CFG: AUTO Position */ +#define CCU1_CLK_USB0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_USB0_CFG_AUTO_Pos) /*!< CCU1 CLK_USB0_CFG: AUTO Mask */ +#define CCU1_CLK_USB0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_USB0_CFG: WAKEUP Position */ +#define CCU1_CLK_USB0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_USB0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_USB0_CFG: WAKEUP Mask */ + +/* ----------------------------- CCU1_CLK_USB0_STAT ----------------------------- */ +#define CCU1_CLK_USB0_STAT_RUN_Pos 0 /*!< CCU1 CLK_USB0_STAT: RUN Position */ +#define CCU1_CLK_USB0_STAT_RUN_Msk (0x01UL << CCU1_CLK_USB0_STAT_RUN_Pos) /*!< CCU1 CLK_USB0_STAT: RUN Mask */ +#define CCU1_CLK_USB0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_USB0_STAT: AUTO Position */ +#define CCU1_CLK_USB0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_USB0_STAT_AUTO_Pos) /*!< CCU1 CLK_USB0_STAT: AUTO Mask */ +#define CCU1_CLK_USB0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_USB0_STAT: WAKEUP Position */ +#define CCU1_CLK_USB0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_USB0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_USB0_STAT: WAKEUP Mask */ + +/* ------------------------------ CCU1_CLK_USB1_CFG ----------------------------- */ +#define CCU1_CLK_USB1_CFG_RUN_Pos 0 /*!< CCU1 CLK_USB1_CFG: RUN Position */ +#define CCU1_CLK_USB1_CFG_RUN_Msk (0x01UL << CCU1_CLK_USB1_CFG_RUN_Pos) /*!< CCU1 CLK_USB1_CFG: RUN Mask */ +#define CCU1_CLK_USB1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_USB1_CFG: AUTO Position */ +#define CCU1_CLK_USB1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_USB1_CFG_AUTO_Pos) /*!< CCU1 CLK_USB1_CFG: AUTO Mask */ +#define CCU1_CLK_USB1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_USB1_CFG: WAKEUP Position */ +#define CCU1_CLK_USB1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_USB1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_USB1_CFG: WAKEUP Mask */ + +/* ----------------------------- CCU1_CLK_USB1_STAT ----------------------------- */ +#define CCU1_CLK_USB1_STAT_RUN_Pos 0 /*!< CCU1 CLK_USB1_STAT: RUN Position */ +#define CCU1_CLK_USB1_STAT_RUN_Msk (0x01UL << CCU1_CLK_USB1_STAT_RUN_Pos) /*!< CCU1 CLK_USB1_STAT: RUN Mask */ +#define CCU1_CLK_USB1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_USB1_STAT: AUTO Position */ +#define CCU1_CLK_USB1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_USB1_STAT_AUTO_Pos) /*!< CCU1 CLK_USB1_STAT: AUTO Mask */ +#define CCU1_CLK_USB1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_USB1_STAT: WAKEUP Position */ +#define CCU1_CLK_USB1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_USB1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_USB1_STAT: WAKEUP Mask */ + +/* ------------------------------ CCU1_CLK_SPI_CFG ------------------------------ */ +#define CCU1_CLK_SPI_CFG_RUN_Pos 0 /*!< CCU1 CLK_SPI_CFG: RUN Position */ +#define CCU1_CLK_SPI_CFG_RUN_Msk (0x01UL << CCU1_CLK_SPI_CFG_RUN_Pos) /*!< CCU1 CLK_SPI_CFG: RUN Mask */ +#define CCU1_CLK_SPI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_SPI_CFG: AUTO Position */ +#define CCU1_CLK_SPI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_SPI_CFG_AUTO_Pos) /*!< CCU1 CLK_SPI_CFG: AUTO Mask */ +#define CCU1_CLK_SPI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_SPI_CFG: WAKEUP Position */ +#define CCU1_CLK_SPI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_SPI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_SPI_CFG: WAKEUP Mask */ + +/* ------------------------------ CCU1_CLK_SPI_STAT ----------------------------- */ +#define CCU1_CLK_SPI_STAT_RUN_Pos 0 /*!< CCU1 CLK_SPI_STAT: RUN Position */ +#define CCU1_CLK_SPI_STAT_RUN_Msk (0x01UL << CCU1_CLK_SPI_STAT_RUN_Pos) /*!< CCU1 CLK_SPI_STAT: RUN Mask */ +#define CCU1_CLK_SPI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_SPI_STAT: AUTO Position */ +#define CCU1_CLK_SPI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_SPI_STAT_AUTO_Pos) /*!< CCU1 CLK_SPI_STAT: AUTO Mask */ +#define CCU1_CLK_SPI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_SPI_STAT: WAKEUP Position */ +#define CCU1_CLK_SPI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_SPI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_SPI_STAT: WAKEUP Mask */ + +/* ----------------------------- CCU1_CLK_ADCHS_CFG ----------------------------- */ +#define CCU1_CLK_ADCHS_CFG_RUN_Pos 0 /*!< CCU1 CLK_ADCHS_CFG: RUN Position */ +#define CCU1_CLK_ADCHS_CFG_RUN_Msk (0x01UL << CCU1_CLK_ADCHS_CFG_RUN_Pos) /*!< CCU1 CLK_ADCHS_CFG: RUN Mask */ +#define CCU1_CLK_ADCHS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_ADCHS_CFG: AUTO Position */ +#define CCU1_CLK_ADCHS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_ADCHS_CFG_AUTO_Pos) /*!< CCU1 CLK_ADCHS_CFG: AUTO Mask */ +#define CCU1_CLK_ADCHS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_ADCHS_CFG: WAKEUP Position */ +#define CCU1_CLK_ADCHS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_ADCHS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_ADCHS_CFG: WAKEUP Mask */ + +/* ----------------------------- CCU1_CLK_ADCHS_STAT ---------------------------- */ +#define CCU1_CLK_ADCHS_STAT_RUN_Pos 0 /*!< CCU1 CLK_ADCHS_STAT: RUN Position */ +#define CCU1_CLK_ADCHS_STAT_RUN_Msk (0x01UL << CCU1_CLK_ADCHS_STAT_RUN_Pos) /*!< CCU1 CLK_ADCHS_STAT: RUN Mask */ +#define CCU1_CLK_ADCHS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_ADCHS_STAT: AUTO Position */ +#define CCU1_CLK_ADCHS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_ADCHS_STAT_AUTO_Pos) /*!< CCU1 CLK_ADCHS_STAT: AUTO Mask */ +#define CCU1_CLK_ADCHS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_ADCHS_STAT: WAKEUP Position */ +#define CCU1_CLK_ADCHS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_ADCHS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_ADCHS_STAT: WAKEUP Mask */ + + +/* ================================================================================ */ +/* ================ struct 'CCU2' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------------- CCU2_PM ---------------------------------- */ +#define CCU2_PM_PD_Pos 0 /*!< CCU2 PM: PD Position */ +#define CCU2_PM_PD_Msk (0x01UL << CCU2_PM_PD_Pos) /*!< CCU2 PM: PD Mask */ + +/* ------------------------------- CCU2_BASE_STAT ------------------------------- */ +#define CCU2_BASE_STAT_BASE_UART3_CLK_Pos 1 /*!< CCU2 BASE_STAT: BASE_UART3_CLK Position */ +#define CCU2_BASE_STAT_BASE_UART3_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART3_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART3_CLK Mask */ +#define CCU2_BASE_STAT_BASE_UART2_CLK_Pos 2 /*!< CCU2 BASE_STAT: BASE_UART2_CLK Position */ +#define CCU2_BASE_STAT_BASE_UART2_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART2_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART2_CLK Mask */ +#define CCU2_BASE_STAT_BASE_UART1_CLK_Pos 3 /*!< CCU2 BASE_STAT: BASE_UART1_CLK Position */ +#define CCU2_BASE_STAT_BASE_UART1_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART1_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART1_CLK Mask */ +#define CCU2_BASE_STAT_BASE_UART0_CLK_Pos 4 /*!< CCU2 BASE_STAT: BASE_UART0_CLK Position */ +#define CCU2_BASE_STAT_BASE_UART0_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART0_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART0_CLK Mask */ +#define CCU2_BASE_STAT_BASE_SSP1_CLK_Pos 5 /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Position */ +#define CCU2_BASE_STAT_BASE_SSP1_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_SSP1_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Mask */ +#define CCU2_BASE_STAT_BASE_SSP0_CLK_Pos 6 /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Position */ +#define CCU2_BASE_STAT_BASE_SSP0_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_SSP0_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Mask */ + +/* ----------------------------- CCU2_CLK_AUDIO_CFG ----------------------------- */ +#define CCU2_CLK_AUDIO_CFG_RUN_Pos 0 /*!< CCU2 CLK_AUDIO_CFG: RUN Position */ +#define CCU2_CLK_AUDIO_CFG_RUN_Msk (0x01UL << CCU2_CLK_AUDIO_CFG_RUN_Pos) /*!< CCU2 CLK_AUDIO_CFG: RUN Mask */ +#define CCU2_CLK_AUDIO_CFG_AUTO_Pos 1 /*!< CCU2 CLK_AUDIO_CFG: AUTO Position */ +#define CCU2_CLK_AUDIO_CFG_AUTO_Msk (0x01UL << CCU2_CLK_AUDIO_CFG_AUTO_Pos) /*!< CCU2 CLK_AUDIO_CFG: AUTO Mask */ +#define CCU2_CLK_AUDIO_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_AUDIO_CFG: WAKEUP Position */ +#define CCU2_CLK_AUDIO_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_AUDIO_CFG_WAKEUP_Pos) /*!< CCU2 CLK_AUDIO_CFG: WAKEUP Mask */ + +/* ----------------------------- CCU2_CLK_AUDIO_STAT ---------------------------- */ +#define CCU2_CLK_AUDIO_STAT_RUN_Pos 0 /*!< CCU2 CLK_AUDIO_STAT: RUN Position */ +#define CCU2_CLK_AUDIO_STAT_RUN_Msk (0x01UL << CCU2_CLK_AUDIO_STAT_RUN_Pos) /*!< CCU2 CLK_AUDIO_STAT: RUN Mask */ +#define CCU2_CLK_AUDIO_STAT_AUTO_Pos 1 /*!< CCU2 CLK_AUDIO_STAT: AUTO Position */ +#define CCU2_CLK_AUDIO_STAT_AUTO_Msk (0x01UL << CCU2_CLK_AUDIO_STAT_AUTO_Pos) /*!< CCU2 CLK_AUDIO_STAT: AUTO Mask */ +#define CCU2_CLK_AUDIO_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_AUDIO_STAT: WAKEUP Position */ +#define CCU2_CLK_AUDIO_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_AUDIO_STAT_WAKEUP_Pos) /*!< CCU2 CLK_AUDIO_STAT: WAKEUP Mask */ + +/* -------------------------- CCU2_CLK_APB2_USART3_CFG -------------------------- */ +#define CCU2_CLK_APB2_USART3_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART3_CFG: RUN Position */ +#define CCU2_CLK_APB2_USART3_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART3_CFG_RUN_Pos) /*!< CCU2 CLK_APB2_USART3_CFG: RUN Mask */ +#define CCU2_CLK_APB2_USART3_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Position */ +#define CCU2_CLK_APB2_USART3_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART3_CFG_AUTO_Pos) /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Mask */ +#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Position */ +#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Mask */ + +/* -------------------------- CCU2_CLK_APB2_USART3_STAT ------------------------- */ +#define CCU2_CLK_APB2_USART3_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART3_STAT: RUN Position */ +#define CCU2_CLK_APB2_USART3_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART3_STAT_RUN_Pos) /*!< CCU2 CLK_APB2_USART3_STAT: RUN Mask */ +#define CCU2_CLK_APB2_USART3_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Position */ +#define CCU2_CLK_APB2_USART3_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART3_STAT_AUTO_Pos) /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Mask */ +#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Position */ +#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Mask */ + +/* -------------------------- CCU2_CLK_APB2_USART2_CFG -------------------------- */ +#define CCU2_CLK_APB2_USART2_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART2_CFG: RUN Position */ +#define CCU2_CLK_APB2_USART2_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART2_CFG_RUN_Pos) /*!< CCU2 CLK_APB2_USART2_CFG: RUN Mask */ +#define CCU2_CLK_APB2_USART2_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Position */ +#define CCU2_CLK_APB2_USART2_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART2_CFG_AUTO_Pos) /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Mask */ +#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Position */ +#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Mask */ + +/* -------------------------- CCU2_CLK_APB2_USART2_STAT ------------------------- */ +#define CCU2_CLK_APB2_USART2_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART2_STAT: RUN Position */ +#define CCU2_CLK_APB2_USART2_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART2_STAT_RUN_Pos) /*!< CCU2 CLK_APB2_USART2_STAT: RUN Mask */ +#define CCU2_CLK_APB2_USART2_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Position */ +#define CCU2_CLK_APB2_USART2_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART2_STAT_AUTO_Pos) /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Mask */ +#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Position */ +#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Mask */ + +/* ------------------------- CCU2_CLK_APB0_UART1_CFG ------------------------ */ +#define CCU2_CLK_APB0_UART1_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB0_UART1_CFG: RUN Position */ +#define CCU2_CLK_APB0_UART1_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB0_UART1_CFG_RUN_Pos) /*!< CCU2 CLK_APB0_UART1_CFG: RUN Mask */ +#define CCU2_CLK_APB0_UART1_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB0_UART1_CFG: AUTO Position */ +#define CCU2_CLK_APB0_UART1_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB0_UART1_CFG_AUTO_Pos) /*!< CCU2 CLK_APB0_UART1_CFG: AUTO Mask */ +#define CCU2_CLK_APB0_UART1_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_UART1_CFG: WAKEUP Position */ +#define CCU2_CLK_APB0_UART1_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_UART1_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB0_UART1_CFG: WAKEUP Mask */ + +/* -------------------------- CCU2_CLK_APB0_UART1_STAT -------------------------- */ +#define CCU2_CLK_APB0_UART1_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB0_UART1_STAT: RUN Position */ +#define CCU2_CLK_APB0_UART1_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB0_UART1_STAT_RUN_Pos) /*!< CCU2 CLK_APB0_UART1_STAT: RUN Mask */ +#define CCU2_CLK_APB0_UART1_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Position */ +#define CCU2_CLK_APB0_UART1_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB0_UART1_STAT_AUTO_Pos) /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Mask */ +#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Position */ +#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Mask */ + +/* -------------------------- CCU2_CLK_APB0_USART0_CFG -------------------------- */ +#define CCU2_CLK_APB0_USART0_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB0_USART0_CFG: RUN Position */ +#define CCU2_CLK_APB0_USART0_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB0_USART0_CFG_RUN_Pos) /*!< CCU2 CLK_APB0_USART0_CFG: RUN Mask */ +#define CCU2_CLK_APB0_USART0_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Position */ +#define CCU2_CLK_APB0_USART0_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB0_USART0_CFG_AUTO_Pos) /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Mask */ +#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Position */ +#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Mask */ + +/* -------------------------- CCU2_CLK_APB0_USART0_STAT ------------------------- */ +#define CCU2_CLK_APB0_USART0_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB0_USART0_STAT: RUN Position */ +#define CCU2_CLK_APB0_USART0_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB0_USART0_STAT_RUN_Pos) /*!< CCU2 CLK_APB0_USART0_STAT: RUN Mask */ +#define CCU2_CLK_APB0_USART0_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Position */ +#define CCU2_CLK_APB0_USART0_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB0_USART0_STAT_AUTO_Pos) /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Mask */ +#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Position */ +#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Mask */ + +/* --------------------------- CCU2_CLK_APB2_SSP1_CFG --------------------------- */ +#define CCU2_CLK_APB2_SSP1_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Position */ +#define CCU2_CLK_APB2_SSP1_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB2_SSP1_CFG_RUN_Pos) /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Mask */ +#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Position */ +#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos) /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Mask */ +#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Position */ +#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Mask */ + +/* --------------------------- CCU2_CLK_APB2_SSP1_STAT -------------------------- */ +#define CCU2_CLK_APB2_SSP1_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Position */ +#define CCU2_CLK_APB2_SSP1_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB2_SSP1_STAT_RUN_Pos) /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Mask */ +#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Position */ +#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos) /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Mask */ +#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Position */ +#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Mask */ + +/* --------------------------- CCU2_CLK_APB0_SSP0_CFG --------------------------- */ +#define CCU2_CLK_APB0_SSP0_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Position */ +#define CCU2_CLK_APB0_SSP0_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB0_SSP0_CFG_RUN_Pos) /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Mask */ +#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Position */ +#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos) /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Mask */ +#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Position */ +#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Mask */ + +/* --------------------------- CCU2_CLK_APB0_SSP0_STAT -------------------------- */ +#define CCU2_CLK_APB0_SSP0_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Position */ +#define CCU2_CLK_APB0_SSP0_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB0_SSP0_STAT_RUN_Pos) /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Mask */ +#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Position */ +#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos) /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Mask */ +#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Position */ +#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Mask */ + +/* ------------------------------ CCU2_CLK_SDIO_CFG ----------------------------- */ +#define CCU2_CLK_SDIO_CFG_RUN_Pos 0 /*!< CCU2 CLK_SDIO_CFG: RUN Position */ +#define CCU2_CLK_SDIO_CFG_RUN_Msk (0x01UL << CCU2_CLK_SDIO_CFG_RUN_Pos) /*!< CCU2 CLK_SDIO_CFG: RUN Mask */ +#define CCU2_CLK_SDIO_CFG_AUTO_Pos 1 /*!< CCU2 CLK_SDIO_CFG: AUTO Position */ +#define CCU2_CLK_SDIO_CFG_AUTO_Msk (0x01UL << CCU2_CLK_SDIO_CFG_AUTO_Pos) /*!< CCU2 CLK_SDIO_CFG: AUTO Mask */ +#define CCU2_CLK_SDIO_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_SDIO_CFG: WAKEUP Position */ +#define CCU2_CLK_SDIO_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_SDIO_CFG_WAKEUP_Pos) /*!< CCU2 CLK_SDIO_CFG: WAKEUP Mask */ + +/* ----------------------------- CCU2_CLK_SDIO_STAT ----------------------------- */ +#define CCU2_CLK_SDIO_STAT_RUN_Pos 0 /*!< CCU2 CLK_SDIO_STAT: RUN Position */ +#define CCU2_CLK_SDIO_STAT_RUN_Msk (0x01UL << CCU2_CLK_SDIO_STAT_RUN_Pos) /*!< CCU2 CLK_SDIO_STAT: RUN Mask */ +#define CCU2_CLK_SDIO_STAT_AUTO_Pos 1 /*!< CCU2 CLK_SDIO_STAT: AUTO Position */ +#define CCU2_CLK_SDIO_STAT_AUTO_Msk (0x01UL << CCU2_CLK_SDIO_STAT_AUTO_Pos) /*!< CCU2 CLK_SDIO_STAT: AUTO Mask */ +#define CCU2_CLK_SDIO_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_SDIO_STAT: WAKEUP Position */ +#define CCU2_CLK_SDIO_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_SDIO_STAT_WAKEUP_Pos) /*!< CCU2 CLK_SDIO_STAT: WAKEUP Mask */ + + +/* ================================================================================ */ +/* ================ struct 'RGU' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- RGU_RESET_CTRL0 ------------------------------ */ +#define RGU_RESET_CTRL0_CORE_RST_Pos 0 /*!< RGU RESET_CTRL0: CORE_RST Position */ +#define RGU_RESET_CTRL0_CORE_RST_Msk (0x01UL << RGU_RESET_CTRL0_CORE_RST_Pos) /*!< RGU RESET_CTRL0: CORE_RST Mask */ +#define RGU_RESET_CTRL0_PERIPH_RST_Pos 1 /*!< RGU RESET_CTRL0: PERIPH_RST Position */ +#define RGU_RESET_CTRL0_PERIPH_RST_Msk (0x01UL << RGU_RESET_CTRL0_PERIPH_RST_Pos) /*!< RGU RESET_CTRL0: PERIPH_RST Mask */ +#define RGU_RESET_CTRL0_MASTER_RST_Pos 2 /*!< RGU RESET_CTRL0: MASTER_RST Position */ +#define RGU_RESET_CTRL0_MASTER_RST_Msk (0x01UL << RGU_RESET_CTRL0_MASTER_RST_Pos) /*!< RGU RESET_CTRL0: MASTER_RST Mask */ +#define RGU_RESET_CTRL0_WWDT_RST_Pos 4 /*!< RGU RESET_CTRL0: WWDT_RST Position */ +#define RGU_RESET_CTRL0_WWDT_RST_Msk (0x01UL << RGU_RESET_CTRL0_WWDT_RST_Pos) /*!< RGU RESET_CTRL0: WWDT_RST Mask */ +#define RGU_RESET_CTRL0_CREG_RST_Pos 5 /*!< RGU RESET_CTRL0: CREG_RST Position */ +#define RGU_RESET_CTRL0_CREG_RST_Msk (0x01UL << RGU_RESET_CTRL0_CREG_RST_Pos) /*!< RGU RESET_CTRL0: CREG_RST Mask */ +#define RGU_RESET_CTRL0_BUS_RST_Pos 8 /*!< RGU RESET_CTRL0: BUS_RST Position */ +#define RGU_RESET_CTRL0_BUS_RST_Msk (0x01UL << RGU_RESET_CTRL0_BUS_RST_Pos) /*!< RGU RESET_CTRL0: BUS_RST Mask */ +#define RGU_RESET_CTRL0_SCU_RST_Pos 9 /*!< RGU RESET_CTRL0: SCU_RST Position */ +#define RGU_RESET_CTRL0_SCU_RST_Msk (0x01UL << RGU_RESET_CTRL0_SCU_RST_Pos) /*!< RGU RESET_CTRL0: SCU_RST Mask */ +#define RGU_RESET_CTRL0_M0_SUB_RST_Pos 12 /*!< RGU RESET_CTRL0: M0_SUB_RST Position */ +#define RGU_RESET_CTRL0_M0_SUB_RST_Msk (0x01UL << RGU_RESET_CTRL0_M0_SUB_RST_Pos) /*!< RGU RESET_CTRL0: M0_SUB_RST Mask */ +#define RGU_RESET_CTRL0_M4_RST_Pos 13 /*!< RGU RESET_CTRL0: M4_RST Position */ +#define RGU_RESET_CTRL0_M4_RST_Msk (0x01UL << RGU_RESET_CTRL0_M4_RST_Pos) /*!< RGU RESET_CTRL0: M4_RST Mask */ +#define RGU_RESET_CTRL0_LCD_RST_Pos 16 /*!< RGU RESET_CTRL0: LCD_RST Position */ +#define RGU_RESET_CTRL0_LCD_RST_Msk (0x01UL << RGU_RESET_CTRL0_LCD_RST_Pos) /*!< RGU RESET_CTRL0: LCD_RST Mask */ +#define RGU_RESET_CTRL0_USB0_RST_Pos 17 /*!< RGU RESET_CTRL0: USB0_RST Position */ +#define RGU_RESET_CTRL0_USB0_RST_Msk (0x01UL << RGU_RESET_CTRL0_USB0_RST_Pos) /*!< RGU RESET_CTRL0: USB0_RST Mask */ +#define RGU_RESET_CTRL0_USB1_RST_Pos 18 /*!< RGU RESET_CTRL0: USB1_RST Position */ +#define RGU_RESET_CTRL0_USB1_RST_Msk (0x01UL << RGU_RESET_CTRL0_USB1_RST_Pos) /*!< RGU RESET_CTRL0: USB1_RST Mask */ +#define RGU_RESET_CTRL0_DMA_RST_Pos 19 /*!< RGU RESET_CTRL0: DMA_RST Position */ +#define RGU_RESET_CTRL0_DMA_RST_Msk (0x01UL << RGU_RESET_CTRL0_DMA_RST_Pos) /*!< RGU RESET_CTRL0: DMA_RST Mask */ +#define RGU_RESET_CTRL0_SDIO_RST_Pos 20 /*!< RGU RESET_CTRL0: SDIO_RST Position */ +#define RGU_RESET_CTRL0_SDIO_RST_Msk (0x01UL << RGU_RESET_CTRL0_SDIO_RST_Pos) /*!< RGU RESET_CTRL0: SDIO_RST Mask */ +#define RGU_RESET_CTRL0_EMC_RST_Pos 21 /*!< RGU RESET_CTRL0: EMC_RST Position */ +#define RGU_RESET_CTRL0_EMC_RST_Msk (0x01UL << RGU_RESET_CTRL0_EMC_RST_Pos) /*!< RGU RESET_CTRL0: EMC_RST Mask */ +#define RGU_RESET_CTRL0_ETHERNET_RST_Pos 22 /*!< RGU RESET_CTRL0: ETHERNET_RST Position */ +#define RGU_RESET_CTRL0_ETHERNET_RST_Msk (0x01UL << RGU_RESET_CTRL0_ETHERNET_RST_Pos) /*!< RGU RESET_CTRL0: ETHERNET_RST Mask */ +#define RGU_RESET_CTRL0_FLASHA_RST_Pos 25 /*!< RGU RESET_CTRL0: FLASHA_RST Position */ +#define RGU_RESET_CTRL0_FLASHA_RST_Msk (0x01UL << RGU_RESET_CTRL0_FLASHA_RST_Pos) /*!< RGU RESET_CTRL0: FLASHA_RST Mask */ +#define RGU_RESET_CTRL0_EEPROM_RST_Pos 27 /*!< RGU RESET_CTRL0: EEPROM_RST Position */ +#define RGU_RESET_CTRL0_EEPROM_RST_Msk (0x01UL << RGU_RESET_CTRL0_EEPROM_RST_Pos) /*!< RGU RESET_CTRL0: EEPROM_RST Mask */ +#define RGU_RESET_CTRL0_GPIO_RST_Pos 28 /*!< RGU RESET_CTRL0: GPIO_RST Position */ +#define RGU_RESET_CTRL0_GPIO_RST_Msk (0x01UL << RGU_RESET_CTRL0_GPIO_RST_Pos) /*!< RGU RESET_CTRL0: GPIO_RST Mask */ +#define RGU_RESET_CTRL0_FLASHB_RST_Pos 29 /*!< RGU RESET_CTRL0: FLASHB_RST Position */ +#define RGU_RESET_CTRL0_FLASHB_RST_Msk (0x01UL << RGU_RESET_CTRL0_FLASHB_RST_Pos) /*!< RGU RESET_CTRL0: FLASHB_RST Mask */ + +/* ------------------------------- RGU_RESET_CTRL1 ------------------------------ */ +#define RGU_RESET_CTRL1_TIMER0_RST_Pos 0 /*!< RGU RESET_CTRL1: TIMER0_RST Position */ +#define RGU_RESET_CTRL1_TIMER0_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER0_RST_Pos) /*!< RGU RESET_CTRL1: TIMER0_RST Mask */ +#define RGU_RESET_CTRL1_TIMER1_RST_Pos 1 /*!< RGU RESET_CTRL1: TIMER1_RST Position */ +#define RGU_RESET_CTRL1_TIMER1_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER1_RST_Pos) /*!< RGU RESET_CTRL1: TIMER1_RST Mask */ +#define RGU_RESET_CTRL1_TIMER2_RST_Pos 2 /*!< RGU RESET_CTRL1: TIMER2_RST Position */ +#define RGU_RESET_CTRL1_TIMER2_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER2_RST_Pos) /*!< RGU RESET_CTRL1: TIMER2_RST Mask */ +#define RGU_RESET_CTRL1_TIMER3_RST_Pos 3 /*!< RGU RESET_CTRL1: TIMER3_RST Position */ +#define RGU_RESET_CTRL1_TIMER3_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER3_RST_Pos) /*!< RGU RESET_CTRL1: TIMER3_RST Mask */ +#define RGU_RESET_CTRL1_RITIMER_RST_Pos 4 /*!< RGU RESET_CTRL1: RITIMER_RST Position */ +#define RGU_RESET_CTRL1_RITIMER_RST_Msk (0x01UL << RGU_RESET_CTRL1_RITIMER_RST_Pos) /*!< RGU RESET_CTRL1: RITIMER_RST Mask */ +#define RGU_RESET_CTRL1_SCT_RST_Pos 5 /*!< RGU RESET_CTRL1: SCT_RST Position */ +#define RGU_RESET_CTRL1_SCT_RST_Msk (0x01UL << RGU_RESET_CTRL1_SCT_RST_Pos) /*!< RGU RESET_CTRL1: SCT_RST Mask */ +#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos 6 /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Position */ +#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Msk (0x01UL << RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos) /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Mask */ +#define RGU_RESET_CTRL1_QEI_RST_Pos 7 /*!< RGU RESET_CTRL1: QEI_RST Position */ +#define RGU_RESET_CTRL1_QEI_RST_Msk (0x01UL << RGU_RESET_CTRL1_QEI_RST_Pos) /*!< RGU RESET_CTRL1: QEI_RST Mask */ +#define RGU_RESET_CTRL1_ADC0_RST_Pos 8 /*!< RGU RESET_CTRL1: ADC0_RST Position */ +#define RGU_RESET_CTRL1_ADC0_RST_Msk (0x01UL << RGU_RESET_CTRL1_ADC0_RST_Pos) /*!< RGU RESET_CTRL1: ADC0_RST Mask */ +#define RGU_RESET_CTRL1_ADC1_RST_Pos 9 /*!< RGU RESET_CTRL1: ADC1_RST Position */ +#define RGU_RESET_CTRL1_ADC1_RST_Msk (0x01UL << RGU_RESET_CTRL1_ADC1_RST_Pos) /*!< RGU RESET_CTRL1: ADC1_RST Mask */ +#define RGU_RESET_CTRL1_DAC_RST_Pos 10 /*!< RGU RESET_CTRL1: DAC_RST Position */ +#define RGU_RESET_CTRL1_DAC_RST_Msk (0x01UL << RGU_RESET_CTRL1_DAC_RST_Pos) /*!< RGU RESET_CTRL1: DAC_RST Mask */ +#define RGU_RESET_CTRL1_UART0_RST_Pos 12 /*!< RGU RESET_CTRL1: UART0_RST Position */ +#define RGU_RESET_CTRL1_UART0_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART0_RST_Pos) /*!< RGU RESET_CTRL1: UART0_RST Mask */ +#define RGU_RESET_CTRL1_UART1_RST_Pos 13 /*!< RGU RESET_CTRL1: UART1_RST Position */ +#define RGU_RESET_CTRL1_UART1_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART1_RST_Pos) /*!< RGU RESET_CTRL1: UART1_RST Mask */ +#define RGU_RESET_CTRL1_UART2_RST_Pos 14 /*!< RGU RESET_CTRL1: UART2_RST Position */ +#define RGU_RESET_CTRL1_UART2_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART2_RST_Pos) /*!< RGU RESET_CTRL1: UART2_RST Mask */ +#define RGU_RESET_CTRL1_UART3_RST_Pos 15 /*!< RGU RESET_CTRL1: UART3_RST Position */ +#define RGU_RESET_CTRL1_UART3_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART3_RST_Pos) /*!< RGU RESET_CTRL1: UART3_RST Mask */ +#define RGU_RESET_CTRL1_I2C0_RST_Pos 16 /*!< RGU RESET_CTRL1: I2C0_RST Position */ +#define RGU_RESET_CTRL1_I2C0_RST_Msk (0x01UL << RGU_RESET_CTRL1_I2C0_RST_Pos) /*!< RGU RESET_CTRL1: I2C0_RST Mask */ +#define RGU_RESET_CTRL1_I2C1_RST_Pos 17 /*!< RGU RESET_CTRL1: I2C1_RST Position */ +#define RGU_RESET_CTRL1_I2C1_RST_Msk (0x01UL << RGU_RESET_CTRL1_I2C1_RST_Pos) /*!< RGU RESET_CTRL1: I2C1_RST Mask */ +#define RGU_RESET_CTRL1_SSP0_RST_Pos 18 /*!< RGU RESET_CTRL1: SSP0_RST Position */ +#define RGU_RESET_CTRL1_SSP0_RST_Msk (0x01UL << RGU_RESET_CTRL1_SSP0_RST_Pos) /*!< RGU RESET_CTRL1: SSP0_RST Mask */ +#define RGU_RESET_CTRL1_SSP1_RST_Pos 19 /*!< RGU RESET_CTRL1: SSP1_RST Position */ +#define RGU_RESET_CTRL1_SSP1_RST_Msk (0x01UL << RGU_RESET_CTRL1_SSP1_RST_Pos) /*!< RGU RESET_CTRL1: SSP1_RST Mask */ +#define RGU_RESET_CTRL1_I2S_RST_Pos 20 /*!< RGU RESET_CTRL1: I2S_RST Position */ +#define RGU_RESET_CTRL1_I2S_RST_Msk (0x01UL << RGU_RESET_CTRL1_I2S_RST_Pos) /*!< RGU RESET_CTRL1: I2S_RST Mask */ +#define RGU_RESET_CTRL1_SPIFI_RST_Pos 21 /*!< RGU RESET_CTRL1: SPIFI_RST Position */ +#define RGU_RESET_CTRL1_SPIFI_RST_Msk (0x01UL << RGU_RESET_CTRL1_SPIFI_RST_Pos) /*!< RGU RESET_CTRL1: SPIFI_RST Mask */ +#define RGU_RESET_CTRL1_CAN1_RST_Pos 22 /*!< RGU RESET_CTRL1: CAN1_RST Position */ +#define RGU_RESET_CTRL1_CAN1_RST_Msk (0x01UL << RGU_RESET_CTRL1_CAN1_RST_Pos) /*!< RGU RESET_CTRL1: CAN1_RST Mask */ +#define RGU_RESET_CTRL1_CAN0_RST_Pos 23 /*!< RGU RESET_CTRL1: CAN0_RST Position */ +#define RGU_RESET_CTRL1_CAN0_RST_Msk (0x01UL << RGU_RESET_CTRL1_CAN0_RST_Pos) /*!< RGU RESET_CTRL1: CAN0_RST Mask */ +#define RGU_RESET_CTRL1_M0APP_RST_Pos 24 /*!< RGU RESET_CTRL1: M0APP_RST Position */ +#define RGU_RESET_CTRL1_M0APP_RST_Msk (0x01UL << RGU_RESET_CTRL1_M0APP_RST_Pos) /*!< RGU RESET_CTRL1: M0APP_RST Mask */ +#define RGU_RESET_CTRL1_SGPIO_RST_Pos 25 /*!< RGU RESET_CTRL1: SGPIO_RST Position */ +#define RGU_RESET_CTRL1_SGPIO_RST_Msk (0x01UL << RGU_RESET_CTRL1_SGPIO_RST_Pos) /*!< RGU RESET_CTRL1: SGPIO_RST Mask */ +#define RGU_RESET_CTRL1_SPI_RST_Pos 26 /*!< RGU RESET_CTRL1: SPI_RST Position */ +#define RGU_RESET_CTRL1_SPI_RST_Msk (0x01UL << RGU_RESET_CTRL1_SPI_RST_Pos) /*!< RGU RESET_CTRL1: SPI_RST Mask */ +#define RGU_RESET_CTRL1_ADCHS_RST_Pos 28 /*!< RGU RESET_CTRL1: ADCHS_RST Position */ +#define RGU_RESET_CTRL1_ADCHS_RST_Msk (0x01UL << RGU_RESET_CTRL1_ADCHS_RST_Pos) /*!< RGU RESET_CTRL1: ADCHS_RST Mask */ + +/* ------------------------------ RGU_RESET_STATUS0 ----------------------------- */ +#define RGU_RESET_STATUS0_PERIPH_RST_Pos 2 /*!< RGU RESET_STATUS0: PERIPH_RST Position */ +#define RGU_RESET_STATUS0_PERIPH_RST_Msk (0x03UL << RGU_RESET_STATUS0_PERIPH_RST_Pos) /*!< RGU RESET_STATUS0: PERIPH_RST Mask */ +#define RGU_RESET_STATUS0_MASTER_RST_Pos 4 /*!< RGU RESET_STATUS0: MASTER_RST Position */ +#define RGU_RESET_STATUS0_MASTER_RST_Msk (0x03UL << RGU_RESET_STATUS0_MASTER_RST_Pos) /*!< RGU RESET_STATUS0: MASTER_RST Mask */ +#define RGU_RESET_STATUS0_WWDT_RST_Pos 8 /*!< RGU RESET_STATUS0: WWDT_RST Position */ +#define RGU_RESET_STATUS0_WWDT_RST_Msk (0x03UL << RGU_RESET_STATUS0_WWDT_RST_Pos) /*!< RGU RESET_STATUS0: WWDT_RST Mask */ +#define RGU_RESET_STATUS0_CREG_RST_Pos 10 /*!< RGU RESET_STATUS0: CREG_RST Position */ +#define RGU_RESET_STATUS0_CREG_RST_Msk (0x03UL << RGU_RESET_STATUS0_CREG_RST_Pos) /*!< RGU RESET_STATUS0: CREG_RST Mask */ +#define RGU_RESET_STATUS0_BUS_RST_Pos 16 /*!< RGU RESET_STATUS0: BUS_RST Position */ +#define RGU_RESET_STATUS0_BUS_RST_Msk (0x03UL << RGU_RESET_STATUS0_BUS_RST_Pos) /*!< RGU RESET_STATUS0: BUS_RST Mask */ +#define RGU_RESET_STATUS0_SCU_RST_Pos 18 /*!< RGU RESET_STATUS0: SCU_RST Position */ +#define RGU_RESET_STATUS0_SCU_RST_Msk (0x03UL << RGU_RESET_STATUS0_SCU_RST_Pos) /*!< RGU RESET_STATUS0: SCU_RST Mask */ +#define RGU_RESET_STATUS0_M0SUB_RST_Pos 24 /*!< RGU RESET_STATUS0: M0SUB_RST Position */ +#define RGU_RESET_STATUS0_M0SUB_RST_Msk (0x03UL << RGU_RESET_STATUS0_M0SUB_RST_Pos) /*!< RGU RESET_STATUS0: M0SUB_RST Mask */ +#define RGU_RESET_STATUS0_M4_RST_Pos 26 /*!< RGU RESET_STATUS0: M4_RST Position */ +#define RGU_RESET_STATUS0_M4_RST_Msk (0x03UL << RGU_RESET_STATUS0_M4_RST_Pos) /*!< RGU RESET_STATUS0: M4_RST Mask */ + +/* ------------------------------ RGU_RESET_STATUS1 ----------------------------- */ +#define RGU_RESET_STATUS1_LCD_RST_Pos 0 /*!< RGU RESET_STATUS1: LCD_RST Position */ +#define RGU_RESET_STATUS1_LCD_RST_Msk (0x03UL << RGU_RESET_STATUS1_LCD_RST_Pos) /*!< RGU RESET_STATUS1: LCD_RST Mask */ +#define RGU_RESET_STATUS1_USB0_RST_Pos 2 /*!< RGU RESET_STATUS1: USB0_RST Position */ +#define RGU_RESET_STATUS1_USB0_RST_Msk (0x03UL << RGU_RESET_STATUS1_USB0_RST_Pos) /*!< RGU RESET_STATUS1: USB0_RST Mask */ +#define RGU_RESET_STATUS1_USB1_RST_Pos 4 /*!< RGU RESET_STATUS1: USB1_RST Position */ +#define RGU_RESET_STATUS1_USB1_RST_Msk (0x03UL << RGU_RESET_STATUS1_USB1_RST_Pos) /*!< RGU RESET_STATUS1: USB1_RST Mask */ +#define RGU_RESET_STATUS1_DMA_RST_Pos 6 /*!< RGU RESET_STATUS1: DMA_RST Position */ +#define RGU_RESET_STATUS1_DMA_RST_Msk (0x03UL << RGU_RESET_STATUS1_DMA_RST_Pos) /*!< RGU RESET_STATUS1: DMA_RST Mask */ +#define RGU_RESET_STATUS1_SDIO_RST_Pos 8 /*!< RGU RESET_STATUS1: SDIO_RST Position */ +#define RGU_RESET_STATUS1_SDIO_RST_Msk (0x03UL << RGU_RESET_STATUS1_SDIO_RST_Pos) /*!< RGU RESET_STATUS1: SDIO_RST Mask */ +#define RGU_RESET_STATUS1_EMC_RST_Pos 10 /*!< RGU RESET_STATUS1: EMC_RST Position */ +#define RGU_RESET_STATUS1_EMC_RST_Msk (0x03UL << RGU_RESET_STATUS1_EMC_RST_Pos) /*!< RGU RESET_STATUS1: EMC_RST Mask */ +#define RGU_RESET_STATUS1_ETHERNET_RST_Pos 12 /*!< RGU RESET_STATUS1: ETHERNET_RST Position */ +#define RGU_RESET_STATUS1_ETHERNET_RST_Msk (0x03UL << RGU_RESET_STATUS1_ETHERNET_RST_Pos) /*!< RGU RESET_STATUS1: ETHERNET_RST Mask */ +#define RGU_RESET_STATUS1_FLASHA_RST_Pos 18 /*!< RGU RESET_STATUS1: FLASHA_RST Position */ +#define RGU_RESET_STATUS1_FLASHA_RST_Msk (0x03UL << RGU_RESET_STATUS1_FLASHA_RST_Pos) /*!< RGU RESET_STATUS1: FLASHA_RST Mask */ +#define RGU_RESET_STATUS1_EEPROM_RST_Pos 22 /*!< RGU RESET_STATUS1: EEPROM_RST Position */ +#define RGU_RESET_STATUS1_EEPROM_RST_Msk (0x03UL << RGU_RESET_STATUS1_EEPROM_RST_Pos) /*!< RGU RESET_STATUS1: EEPROM_RST Mask */ +#define RGU_RESET_STATUS1_GPIO_RST_Pos 24 /*!< RGU RESET_STATUS1: GPIO_RST Position */ +#define RGU_RESET_STATUS1_GPIO_RST_Msk (0x03UL << RGU_RESET_STATUS1_GPIO_RST_Pos) /*!< RGU RESET_STATUS1: GPIO_RST Mask */ +#define RGU_RESET_STATUS1_FLASHB_RST_Pos 26 /*!< RGU RESET_STATUS1: FLASHB_RST Position */ +#define RGU_RESET_STATUS1_FLASHB_RST_Msk (0x03UL << RGU_RESET_STATUS1_FLASHB_RST_Pos) /*!< RGU RESET_STATUS1: FLASHB_RST Mask */ + +/* ------------------------------ RGU_RESET_STATUS2 ----------------------------- */ +#define RGU_RESET_STATUS2_TIMER0_RST_Pos 0 /*!< RGU RESET_STATUS2: TIMER0_RST Position */ +#define RGU_RESET_STATUS2_TIMER0_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER0_RST_Pos) /*!< RGU RESET_STATUS2: TIMER0_RST Mask */ +#define RGU_RESET_STATUS2_TIMER1_RST_Pos 2 /*!< RGU RESET_STATUS2: TIMER1_RST Position */ +#define RGU_RESET_STATUS2_TIMER1_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER1_RST_Pos) /*!< RGU RESET_STATUS2: TIMER1_RST Mask */ +#define RGU_RESET_STATUS2_TIMER2_RST_Pos 4 /*!< RGU RESET_STATUS2: TIMER2_RST Position */ +#define RGU_RESET_STATUS2_TIMER2_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER2_RST_Pos) /*!< RGU RESET_STATUS2: TIMER2_RST Mask */ +#define RGU_RESET_STATUS2_TIMER3_RST_Pos 6 /*!< RGU RESET_STATUS2: TIMER3_RST Position */ +#define RGU_RESET_STATUS2_TIMER3_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER3_RST_Pos) /*!< RGU RESET_STATUS2: TIMER3_RST Mask */ +#define RGU_RESET_STATUS2_RITIMER_RST_Pos 8 /*!< RGU RESET_STATUS2: RITIMER_RST Position */ +#define RGU_RESET_STATUS2_RITIMER_RST_Msk (0x03UL << RGU_RESET_STATUS2_RITIMER_RST_Pos) /*!< RGU RESET_STATUS2: RITIMER_RST Mask */ +#define RGU_RESET_STATUS2_SCT_RST_Pos 10 /*!< RGU RESET_STATUS2: SCT_RST Position */ +#define RGU_RESET_STATUS2_SCT_RST_Msk (0x03UL << RGU_RESET_STATUS2_SCT_RST_Pos) /*!< RGU RESET_STATUS2: SCT_RST Mask */ +#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos 12 /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Position */ +#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Msk (0x03UL << RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos) /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Mask */ +#define RGU_RESET_STATUS2_QEI_RST_Pos 14 /*!< RGU RESET_STATUS2: QEI_RST Position */ +#define RGU_RESET_STATUS2_QEI_RST_Msk (0x03UL << RGU_RESET_STATUS2_QEI_RST_Pos) /*!< RGU RESET_STATUS2: QEI_RST Mask */ +#define RGU_RESET_STATUS2_ADC0_RST_Pos 16 /*!< RGU RESET_STATUS2: ADC0_RST Position */ +#define RGU_RESET_STATUS2_ADC0_RST_Msk (0x03UL << RGU_RESET_STATUS2_ADC0_RST_Pos) /*!< RGU RESET_STATUS2: ADC0_RST Mask */ +#define RGU_RESET_STATUS2_ADC1_RST_Pos 18 /*!< RGU RESET_STATUS2: ADC1_RST Position */ +#define RGU_RESET_STATUS2_ADC1_RST_Msk (0x03UL << RGU_RESET_STATUS2_ADC1_RST_Pos) /*!< RGU RESET_STATUS2: ADC1_RST Mask */ +#define RGU_RESET_STATUS2_DAC_RST_Pos 20 /*!< RGU RESET_STATUS2: DAC_RST Position */ +#define RGU_RESET_STATUS2_DAC_RST_Msk (0x03UL << RGU_RESET_STATUS2_DAC_RST_Pos) /*!< RGU RESET_STATUS2: DAC_RST Mask */ +#define RGU_RESET_STATUS2_UART0_RST_Pos 24 /*!< RGU RESET_STATUS2: UART0_RST Position */ +#define RGU_RESET_STATUS2_UART0_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART0_RST_Pos) /*!< RGU RESET_STATUS2: UART0_RST Mask */ +#define RGU_RESET_STATUS2_UART1_RST_Pos 26 /*!< RGU RESET_STATUS2: UART1_RST Position */ +#define RGU_RESET_STATUS2_UART1_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART1_RST_Pos) /*!< RGU RESET_STATUS2: UART1_RST Mask */ +#define RGU_RESET_STATUS2_UART2_RST_Pos 28 /*!< RGU RESET_STATUS2: UART2_RST Position */ +#define RGU_RESET_STATUS2_UART2_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART2_RST_Pos) /*!< RGU RESET_STATUS2: UART2_RST Mask */ +#define RGU_RESET_STATUS2_UART3_RST_Pos 30 /*!< RGU RESET_STATUS2: UART3_RST Position */ +#define RGU_RESET_STATUS2_UART3_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART3_RST_Pos) /*!< RGU RESET_STATUS2: UART3_RST Mask */ + +/* ------------------------------ RGU_RESET_STATUS3 ----------------------------- */ +#define RGU_RESET_STATUS3_I2C0_RST_Pos 0 /*!< RGU RESET_STATUS3: I2C0_RST Position */ +#define RGU_RESET_STATUS3_I2C0_RST_Msk (0x03UL << RGU_RESET_STATUS3_I2C0_RST_Pos) /*!< RGU RESET_STATUS3: I2C0_RST Mask */ +#define RGU_RESET_STATUS3_I2C1_RST_Pos 2 /*!< RGU RESET_STATUS3: I2C1_RST Position */ +#define RGU_RESET_STATUS3_I2C1_RST_Msk (0x03UL << RGU_RESET_STATUS3_I2C1_RST_Pos) /*!< RGU RESET_STATUS3: I2C1_RST Mask */ +#define RGU_RESET_STATUS3_SSP0_RST_Pos 4 /*!< RGU RESET_STATUS3: SSP0_RST Position */ +#define RGU_RESET_STATUS3_SSP0_RST_Msk (0x03UL << RGU_RESET_STATUS3_SSP0_RST_Pos) /*!< RGU RESET_STATUS3: SSP0_RST Mask */ +#define RGU_RESET_STATUS3_SSP1_RST_Pos 6 /*!< RGU RESET_STATUS3: SSP1_RST Position */ +#define RGU_RESET_STATUS3_SSP1_RST_Msk (0x03UL << RGU_RESET_STATUS3_SSP1_RST_Pos) /*!< RGU RESET_STATUS3: SSP1_RST Mask */ +#define RGU_RESET_STATUS3_I2S_RST_Pos 8 /*!< RGU RESET_STATUS3: I2S_RST Position */ +#define RGU_RESET_STATUS3_I2S_RST_Msk (0x03UL << RGU_RESET_STATUS3_I2S_RST_Pos) /*!< RGU RESET_STATUS3: I2S_RST Mask */ +#define RGU_RESET_STATUS3_SPIFI_RST_Pos 10 /*!< RGU RESET_STATUS3: SPIFI_RST Position */ +#define RGU_RESET_STATUS3_SPIFI_RST_Msk (0x03UL << RGU_RESET_STATUS3_SPIFI_RST_Pos) /*!< RGU RESET_STATUS3: SPIFI_RST Mask */ +#define RGU_RESET_STATUS3_CAN1_RST_Pos 12 /*!< RGU RESET_STATUS3: CAN1_RST Position */ +#define RGU_RESET_STATUS3_CAN1_RST_Msk (0x03UL << RGU_RESET_STATUS3_CAN1_RST_Pos) /*!< RGU RESET_STATUS3: CAN1_RST Mask */ +#define RGU_RESET_STATUS3_CAN0_RST_Pos 14 /*!< RGU RESET_STATUS3: CAN0_RST Position */ +#define RGU_RESET_STATUS3_CAN0_RST_Msk (0x03UL << RGU_RESET_STATUS3_CAN0_RST_Pos) /*!< RGU RESET_STATUS3: CAN0_RST Mask */ +#define RGU_RESET_STATUS3_M0APP_RST_Pos 16 /*!< RGU RESET_STATUS3: M0APP_RST Position */ +#define RGU_RESET_STATUS3_M0APP_RST_Msk (0x03UL << RGU_RESET_STATUS3_M0APP_RST_Pos) /*!< RGU RESET_STATUS3: M0APP_RST Mask */ +#define RGU_RESET_STATUS3_SGPIO_RST_Pos 18 /*!< RGU RESET_STATUS3: SGPIO_RST Position */ +#define RGU_RESET_STATUS3_SGPIO_RST_Msk (0x03UL << RGU_RESET_STATUS3_SGPIO_RST_Pos) /*!< RGU RESET_STATUS3: SGPIO_RST Mask */ +#define RGU_RESET_STATUS3_SPI_RST_Pos 20 /*!< RGU RESET_STATUS3: SPI_RST Position */ +#define RGU_RESET_STATUS3_SPI_RST_Msk (0x03UL << RGU_RESET_STATUS3_SPI_RST_Pos) /*!< RGU RESET_STATUS3: SPI_RST Mask */ +#define RGU_RESET_STATUS3_ADCHS_RST_Pos 24 /*!< RGU RESET_STATUS3: ADCHS_RST Position */ +#define RGU_RESET_STATUS3_ADCHS_RST_Msk (0x03UL << RGU_RESET_STATUS3_ADCHS_RST_Pos) /*!< RGU RESET_STATUS3: ADCHS_RST Mask */ + +/* -------------------------- RGU_RESET_ACTIVE_STATUS0 -------------------------- */ +#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos 0 /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Position */ +#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos 1 /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Position */ +#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos 2 /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Position */ +#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos 4 /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Position */ +#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos 5 /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Position */ +#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos 8 /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Position */ +#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos 9 /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Position */ +#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS0_M0SUB_RST_Pos 12 /*!< RGU RESET_ACTIVE_STATUS0: M0SUB_RST Position */ +#define RGU_RESET_ACTIVE_STATUS0_M0SUB_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_M0SUB_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: M0SUB_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS0_M4_RST_Pos 13 /*!< RGU RESET_ACTIVE_STATUS0: M4_RST Position */ +#define RGU_RESET_ACTIVE_STATUS0_M4_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_M4_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: M4_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos 16 /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Position */ +#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos 17 /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Position */ +#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos 18 /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Position */ +#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos 19 /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Position */ +#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos 20 /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Position */ +#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos 21 /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Position */ +#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos 22 /*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Position */ +#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos)/*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS0_FLASHA_RST_Pos 25 /*!< RGU RESET_ACTIVE_STATUS0: FLASHA_RST Position */ +#define RGU_RESET_ACTIVE_STATUS0_FLASHA_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_FLASHA_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: FLASHA_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS0_EEPROM_RST_Pos 27 /*!< RGU RESET_ACTIVE_STATUS0: EEPROM_RST Position */ +#define RGU_RESET_ACTIVE_STATUS0_EEPROM_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_EEPROM_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: EEPROM_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos 28 /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Position */ +#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS0_FLASHB_RST_Pos 29 /*!< RGU RESET_ACTIVE_STATUS0: FLASHB_RST Position */ +#define RGU_RESET_ACTIVE_STATUS0_FLASHB_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_FLASHB_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: FLASHB_RST Mask */ + +/* -------------------------- RGU_RESET_ACTIVE_STATUS1 -------------------------- */ +#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos 0 /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos 1 /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos 2 /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos 3 /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos 4 /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos 5 /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos 6 /*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos)/*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos 7 /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos 8 /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos 9 /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos 10 /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos 12 /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos 13 /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos 14 /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos 15 /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos 16 /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos 17 /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos 18 /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos 19 /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos 20 /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos 21 /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos 22 /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos 23 /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_M0APP_RST_Pos 24 /*!< RGU RESET_ACTIVE_STATUS1: M0APP_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_M0APP_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_M0APP_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: M0APP_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Pos 25 /*!< RGU RESET_ACTIVE_STATUS1: SGPIO_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SGPIO_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_SPI_RST_Pos 26 /*!< RGU RESET_ACTIVE_STATUS1: SPI_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_SPI_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SPI_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SPI_RST Mask */ +#define RGU_RESET_ACTIVE_STATUS1_ADCHS_RST_Pos 28 /*!< RGU RESET_ACTIVE_STATUS1: ADCHS_RST Position */ +#define RGU_RESET_ACTIVE_STATUS1_ADCHS_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADCHS_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: ADCHS_RST Mask */ + +/* ----------------------------- RGU_RESET_EXT_STAT1 ---------------------------- */ +#define RGU_RESET_EXT_STAT1_CORE_RESET_Pos 1 /*!< RGU RESET_EXT_STAT1: CORE_RESET Position */ +#define RGU_RESET_EXT_STAT1_CORE_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT1_CORE_RESET_Pos) /*!< RGU RESET_EXT_STAT1: CORE_RESET Mask */ + +/* ----------------------------- RGU_RESET_EXT_STAT2 ---------------------------- */ +#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Mask */ + +/* ----------------------------- RGU_RESET_EXT_STAT5 ---------------------------- */ +#define RGU_RESET_EXT_STAT5_CORE_RESET_Pos 1 /*!< RGU RESET_EXT_STAT5: CORE_RESET Position */ +#define RGU_RESET_EXT_STAT5_CORE_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT5_CORE_RESET_Pos) /*!< RGU RESET_EXT_STAT5: CORE_RESET Mask */ + +/* ----------------------------- RGU_RESET_EXT_STAT8 ---------------------------- */ +#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Mask */ + +/* ----------------------------- RGU_RESET_EXT_STAT9 ---------------------------- */ +#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT12 ---------------------------- */ +#define RGU_RESET_EXT_STAT12_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT12: MASTER_RESET Position */ +#define RGU_RESET_EXT_STAT12_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT12_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT12: MASTER_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT13 ---------------------------- */ +#define RGU_RESET_EXT_STAT13_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT13: MASTER_RESET Position */ +#define RGU_RESET_EXT_STAT13_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT13_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT13: MASTER_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT16 ---------------------------- */ +#define RGU_RESET_EXT_STAT16_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT16: MASTER_RESET Position */ +#define RGU_RESET_EXT_STAT16_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT16_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT16: MASTER_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT17 ---------------------------- */ +#define RGU_RESET_EXT_STAT17_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT17: MASTER_RESET Position */ +#define RGU_RESET_EXT_STAT17_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT17_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT17: MASTER_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT18 ---------------------------- */ +#define RGU_RESET_EXT_STAT18_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT18: MASTER_RESET Position */ +#define RGU_RESET_EXT_STAT18_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT18_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT18: MASTER_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT19 ---------------------------- */ +#define RGU_RESET_EXT_STAT19_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT19: MASTER_RESET Position */ +#define RGU_RESET_EXT_STAT19_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT19_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT19: MASTER_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT20 ---------------------------- */ +#define RGU_RESET_EXT_STAT20_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT20: MASTER_RESET Position */ +#define RGU_RESET_EXT_STAT20_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT20_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT20: MASTER_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT21 ---------------------------- */ +#define RGU_RESET_EXT_STAT21_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT21: MASTER_RESET Position */ +#define RGU_RESET_EXT_STAT21_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT21_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT21: MASTER_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT22 ---------------------------- */ +#define RGU_RESET_EXT_STAT22_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT22: MASTER_RESET Position */ +#define RGU_RESET_EXT_STAT22_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT22_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT22: MASTER_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT25 ---------------------------- */ +#define RGU_RESET_EXT_STAT25_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT25: MASTER_RESET Position */ +#define RGU_RESET_EXT_STAT25_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT25_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT25: MASTER_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT27 ---------------------------- */ +#define RGU_RESET_EXT_STAT27_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT27: MASTER_RESET Position */ +#define RGU_RESET_EXT_STAT27_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT27_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT27: MASTER_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT28 ---------------------------- */ +#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT29 ---------------------------- */ +#define RGU_RESET_EXT_STAT29_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT29: MASTER_RESET Position */ +#define RGU_RESET_EXT_STAT29_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT29_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT29: MASTER_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT32 ---------------------------- */ +#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT33 ---------------------------- */ +#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT34 ---------------------------- */ +#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT35 ---------------------------- */ +#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT36 ---------------------------- */ +#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT37 ---------------------------- */ +#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT38 ---------------------------- */ +#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Mask */ -// ------------------------------------- LCD_CRSR_IMG39 ----------------------------------------- -#define LCD_CRSR_IMG39_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG39: CRSR_IMG Position */ -#define LCD_CRSR_IMG39_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG39_CRSR_IMG_Pos) /*!< LCD CRSR_IMG39: CRSR_IMG Mask */ +/* ---------------------------- RGU_RESET_EXT_STAT39 ---------------------------- */ +#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Mask */ -// ------------------------------------- LCD_CRSR_IMG40 ----------------------------------------- -#define LCD_CRSR_IMG40_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG40: CRSR_IMG Position */ -#define LCD_CRSR_IMG40_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG40_CRSR_IMG_Pos) /*!< LCD CRSR_IMG40: CRSR_IMG Mask */ +/* ---------------------------- RGU_RESET_EXT_STAT40 ---------------------------- */ +#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Mask */ -// ------------------------------------- LCD_CRSR_IMG41 ----------------------------------------- -#define LCD_CRSR_IMG41_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG41: CRSR_IMG Position */ -#define LCD_CRSR_IMG41_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG41_CRSR_IMG_Pos) /*!< LCD CRSR_IMG41: CRSR_IMG Mask */ +/* ---------------------------- RGU_RESET_EXT_STAT41 ---------------------------- */ +#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Mask */ -// ------------------------------------- LCD_CRSR_IMG42 ----------------------------------------- -#define LCD_CRSR_IMG42_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG42: CRSR_IMG Position */ -#define LCD_CRSR_IMG42_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG42_CRSR_IMG_Pos) /*!< LCD CRSR_IMG42: CRSR_IMG Mask */ +/* ---------------------------- RGU_RESET_EXT_STAT42 ---------------------------- */ +#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Mask */ -// ------------------------------------- LCD_CRSR_IMG43 ----------------------------------------- -#define LCD_CRSR_IMG43_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG43: CRSR_IMG Position */ -#define LCD_CRSR_IMG43_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG43_CRSR_IMG_Pos) /*!< LCD CRSR_IMG43: CRSR_IMG Mask */ +/* ---------------------------- RGU_RESET_EXT_STAT44 ---------------------------- */ +#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Mask */ -// ------------------------------------- LCD_CRSR_IMG44 ----------------------------------------- -#define LCD_CRSR_IMG44_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG44: CRSR_IMG Position */ -#define LCD_CRSR_IMG44_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG44_CRSR_IMG_Pos) /*!< LCD CRSR_IMG44: CRSR_IMG Mask */ +/* ---------------------------- RGU_RESET_EXT_STAT45 ---------------------------- */ +#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Mask */ -// ------------------------------------- LCD_CRSR_IMG45 ----------------------------------------- -#define LCD_CRSR_IMG45_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG45: CRSR_IMG Position */ -#define LCD_CRSR_IMG45_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG45_CRSR_IMG_Pos) /*!< LCD CRSR_IMG45: CRSR_IMG Mask */ +/* ---------------------------- RGU_RESET_EXT_STAT46 ---------------------------- */ +#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Mask */ -// ------------------------------------- LCD_CRSR_IMG46 ----------------------------------------- -#define LCD_CRSR_IMG46_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG46: CRSR_IMG Position */ -#define LCD_CRSR_IMG46_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG46_CRSR_IMG_Pos) /*!< LCD CRSR_IMG46: CRSR_IMG Mask */ +/* ---------------------------- RGU_RESET_EXT_STAT47 ---------------------------- */ +#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Mask */ -// ------------------------------------- LCD_CRSR_IMG47 ----------------------------------------- -#define LCD_CRSR_IMG47_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG47: CRSR_IMG Position */ -#define LCD_CRSR_IMG47_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG47_CRSR_IMG_Pos) /*!< LCD CRSR_IMG47: CRSR_IMG Mask */ +/* ---------------------------- RGU_RESET_EXT_STAT48 ---------------------------- */ +#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Mask */ -// ------------------------------------- LCD_CRSR_IMG48 ----------------------------------------- -#define LCD_CRSR_IMG48_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG48: CRSR_IMG Position */ -#define LCD_CRSR_IMG48_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG48_CRSR_IMG_Pos) /*!< LCD CRSR_IMG48: CRSR_IMG Mask */ +/* ---------------------------- RGU_RESET_EXT_STAT49 ---------------------------- */ +#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Mask */ -// ------------------------------------- LCD_CRSR_IMG49 ----------------------------------------- -#define LCD_CRSR_IMG49_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG49: CRSR_IMG Position */ -#define LCD_CRSR_IMG49_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG49_CRSR_IMG_Pos) /*!< LCD CRSR_IMG49: CRSR_IMG Mask */ +/* ---------------------------- RGU_RESET_EXT_STAT50 ---------------------------- */ +#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Mask */ -// ------------------------------------- LCD_CRSR_IMG50 ----------------------------------------- -#define LCD_CRSR_IMG50_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG50: CRSR_IMG Position */ -#define LCD_CRSR_IMG50_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG50_CRSR_IMG_Pos) /*!< LCD CRSR_IMG50: CRSR_IMG Mask */ +/* ---------------------------- RGU_RESET_EXT_STAT51 ---------------------------- */ +#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Mask */ -// ------------------------------------- LCD_CRSR_IMG51 ----------------------------------------- -#define LCD_CRSR_IMG51_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG51: CRSR_IMG Position */ -#define LCD_CRSR_IMG51_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG51_CRSR_IMG_Pos) /*!< LCD CRSR_IMG51: CRSR_IMG Mask */ +/* ---------------------------- RGU_RESET_EXT_STAT52 ---------------------------- */ +#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Mask */ -// ------------------------------------- LCD_CRSR_IMG52 ----------------------------------------- -#define LCD_CRSR_IMG52_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG52: CRSR_IMG Position */ -#define LCD_CRSR_IMG52_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG52_CRSR_IMG_Pos) /*!< LCD CRSR_IMG52: CRSR_IMG Mask */ +/* ---------------------------- RGU_RESET_EXT_STAT53 ---------------------------- */ +#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT54 ---------------------------- */ +#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT55 ---------------------------- */ +#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT56 ---------------------------- */ +#define RGU_RESET_EXT_STAT56_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT56: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT56_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT56_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT56: PERIPHERAL_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT57 ---------------------------- */ +#define RGU_RESET_EXT_STAT57_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT57: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT57_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT57_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT57: PERIPHERAL_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT58 ---------------------------- */ +#define RGU_RESET_EXT_STAT58_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT58: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT58_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT58_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT58: PERIPHERAL_RESET Mask */ + +/* ---------------------------- RGU_RESET_EXT_STAT60 ---------------------------- */ +#define RGU_RESET_EXT_STAT60_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT60: PERIPHERAL_RESET Position */ +#define RGU_RESET_EXT_STAT60_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT60_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT60: PERIPHERAL_RESET Mask */ + + +/* ================================================================================ */ +/* ================ struct 'WWDT' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- WWDT_MOD ---------------------------------- */ +#define WWDT_MOD_WDEN_Pos 0 /*!< WWDT MOD: WDEN Position */ +#define WWDT_MOD_WDEN_Msk (0x01UL << WWDT_MOD_WDEN_Pos) /*!< WWDT MOD: WDEN Mask */ +#define WWDT_MOD_WDRESET_Pos 1 /*!< WWDT MOD: WDRESET Position */ +#define WWDT_MOD_WDRESET_Msk (0x01UL << WWDT_MOD_WDRESET_Pos) /*!< WWDT MOD: WDRESET Mask */ +#define WWDT_MOD_WDTOF_Pos 2 /*!< WWDT MOD: WDTOF Position */ +#define WWDT_MOD_WDTOF_Msk (0x01UL << WWDT_MOD_WDTOF_Pos) /*!< WWDT MOD: WDTOF Mask */ +#define WWDT_MOD_WDINT_Pos 3 /*!< WWDT MOD: WDINT Position */ +#define WWDT_MOD_WDINT_Msk (0x01UL << WWDT_MOD_WDINT_Pos) /*!< WWDT MOD: WDINT Mask */ +#define WWDT_MOD_WDPROTECT_Pos 4 /*!< WWDT MOD: WDPROTECT Position */ +#define WWDT_MOD_WDPROTECT_Msk (0x01UL << WWDT_MOD_WDPROTECT_Pos) /*!< WWDT MOD: WDPROTECT Mask */ + +/* ----------------------------------- WWDT_TC ---------------------------------- */ +#define WWDT_TC_WDTC_Pos 0 /*!< WWDT TC: WDTC Position */ +#define WWDT_TC_WDTC_Msk (0x00ffffffUL << WWDT_TC_WDTC_Pos) /*!< WWDT TC: WDTC Mask */ + +/* ---------------------------------- WWDT_FEED --------------------------------- */ +#define WWDT_FEED_Feed_Pos 0 /*!< WWDT FEED: Feed Position */ +#define WWDT_FEED_Feed_Msk (0x000000ffUL << WWDT_FEED_Feed_Pos) /*!< WWDT FEED: Feed Mask */ + +/* ----------------------------------- WWDT_TV ---------------------------------- */ +#define WWDT_TV_Count_Pos 0 /*!< WWDT TV: Count Position */ +#define WWDT_TV_Count_Msk (0x00ffffffUL << WWDT_TV_Count_Pos) /*!< WWDT TV: Count Mask */ + +/* -------------------------------- WWDT_WARNINT -------------------------------- */ +#define WWDT_WARNINT_WDWARNINT_Pos 0 /*!< WWDT WARNINT: WDWARNINT Position */ +#define WWDT_WARNINT_WDWARNINT_Msk (0x000003ffUL << WWDT_WARNINT_WDWARNINT_Pos) /*!< WWDT WARNINT: WDWARNINT Mask */ + +/* --------------------------------- WWDT_WINDOW -------------------------------- */ +#define WWDT_WINDOW_WDWINDOW_Pos 0 /*!< WWDT WINDOW: WDWINDOW Position */ +#define WWDT_WINDOW_WDWINDOW_Msk (0x00ffffffUL << WWDT_WINDOW_WDWINDOW_Pos) /*!< WWDT WINDOW: WDWINDOW Mask */ + + +/* ================================================================================ */ +/* ================ Group 'USARTn' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- USARTn_RBR --------------------------------- */ +#define USARTn_RBR_RBR_Pos 0 /*!< USARTn RBR: RBR Position */ +#define USARTn_RBR_RBR_Msk (0x000000ffUL << USARTn_RBR_RBR_Pos) /*!< USARTn RBR: RBR Mask */ + +/* --------------------------------- USARTn_THR --------------------------------- */ +#define USARTn_THR_THR_Pos 0 /*!< USARTn THR: THR Position */ +#define USARTn_THR_THR_Msk (0x000000ffUL << USARTn_THR_THR_Pos) /*!< USARTn THR: THR Mask */ + +/* --------------------------------- USARTn_DLL --------------------------------- */ +#define USARTn_DLL_DLLSB_Pos 0 /*!< USARTn DLL: DLLSB Position */ +#define USARTn_DLL_DLLSB_Msk (0x000000ffUL << USARTn_DLL_DLLSB_Pos) /*!< USARTn DLL: DLLSB Mask */ + +/* --------------------------------- USARTn_DLM --------------------------------- */ +#define USARTn_DLM_DLMSB_Pos 0 /*!< USARTn DLM: DLMSB Position */ +#define USARTn_DLM_DLMSB_Msk (0x000000ffUL << USARTn_DLM_DLMSB_Pos) /*!< USARTn DLM: DLMSB Mask */ + +/* --------------------------------- USARTn_IER --------------------------------- */ +#define USARTn_IER_RBRIE_Pos 0 /*!< USARTn IER: RBRIE Position */ +#define USARTn_IER_RBRIE_Msk (0x01UL << USARTn_IER_RBRIE_Pos) /*!< USARTn IER: RBRIE Mask */ +#define USARTn_IER_THREIE_Pos 1 /*!< USARTn IER: THREIE Position */ +#define USARTn_IER_THREIE_Msk (0x01UL << USARTn_IER_THREIE_Pos) /*!< USARTn IER: THREIE Mask */ +#define USARTn_IER_RXIE_Pos 2 /*!< USARTn IER: RXIE Position */ +#define USARTn_IER_RXIE_Msk (0x01UL << USARTn_IER_RXIE_Pos) /*!< USARTn IER: RXIE Mask */ +#define USARTn_IER_ABEOINTEN_Pos 8 /*!< USARTn IER: ABEOINTEN Position */ +#define USARTn_IER_ABEOINTEN_Msk (0x01UL << USARTn_IER_ABEOINTEN_Pos) /*!< USARTn IER: ABEOINTEN Mask */ +#define USARTn_IER_ABTOINTEN_Pos 9 /*!< USARTn IER: ABTOINTEN Position */ +#define USARTn_IER_ABTOINTEN_Msk (0x01UL << USARTn_IER_ABTOINTEN_Pos) /*!< USARTn IER: ABTOINTEN Mask */ + +/* --------------------------------- USARTn_IIR --------------------------------- */ +#define USARTn_IIR_INTSTATUS_Pos 0 /*!< USARTn IIR: INTSTATUS Position */ +#define USARTn_IIR_INTSTATUS_Msk (0x01UL << USARTn_IIR_INTSTATUS_Pos) /*!< USARTn IIR: INTSTATUS Mask */ +#define USARTn_IIR_INTID_Pos 1 /*!< USARTn IIR: INTID Position */ +#define USARTn_IIR_INTID_Msk (0x07UL << USARTn_IIR_INTID_Pos) /*!< USARTn IIR: INTID Mask */ +#define USARTn_IIR_FIFOENABLE_Pos 6 /*!< USARTn IIR: FIFOENABLE Position */ +#define USARTn_IIR_FIFOENABLE_Msk (0x03UL << USARTn_IIR_FIFOENABLE_Pos) /*!< USARTn IIR: FIFOENABLE Mask */ +#define USARTn_IIR_ABEOINT_Pos 8 /*!< USARTn IIR: ABEOINT Position */ +#define USARTn_IIR_ABEOINT_Msk (0x01UL << USARTn_IIR_ABEOINT_Pos) /*!< USARTn IIR: ABEOINT Mask */ +#define USARTn_IIR_ABTOINT_Pos 9 /*!< USARTn IIR: ABTOINT Position */ +#define USARTn_IIR_ABTOINT_Msk (0x01UL << USARTn_IIR_ABTOINT_Pos) /*!< USARTn IIR: ABTOINT Mask */ + +/* --------------------------------- USARTn_FCR --------------------------------- */ +#define USARTn_FCR_FIFOEN_Pos 0 /*!< USARTn FCR: FIFOEN Position */ +#define USARTn_FCR_FIFOEN_Msk (0x01UL << USARTn_FCR_FIFOEN_Pos) /*!< USARTn FCR: FIFOEN Mask */ +#define USARTn_FCR_RXFIFORES_Pos 1 /*!< USARTn FCR: RXFIFORES Position */ +#define USARTn_FCR_RXFIFORES_Msk (0x01UL << USARTn_FCR_RXFIFORES_Pos) /*!< USARTn FCR: RXFIFORES Mask */ +#define USARTn_FCR_TXFIFORES_Pos 2 /*!< USARTn FCR: TXFIFORES Position */ +#define USARTn_FCR_TXFIFORES_Msk (0x01UL << USARTn_FCR_TXFIFORES_Pos) /*!< USARTn FCR: TXFIFORES Mask */ +#define USARTn_FCR_DMAMODE_Pos 3 /*!< USARTn FCR: DMAMODE Position */ +#define USARTn_FCR_DMAMODE_Msk (0x01UL << USARTn_FCR_DMAMODE_Pos) /*!< USARTn FCR: DMAMODE Mask */ +#define USARTn_FCR_RXTRIGLVL_Pos 6 /*!< USARTn FCR: RXTRIGLVL Position */ +#define USARTn_FCR_RXTRIGLVL_Msk (0x03UL << USARTn_FCR_RXTRIGLVL_Pos) /*!< USARTn FCR: RXTRIGLVL Mask */ + +/* --------------------------------- USARTn_LCR --------------------------------- */ +#define USARTn_LCR_WLS_Pos 0 /*!< USARTn LCR: WLS Position */ +#define USARTn_LCR_WLS_Msk (0x03UL << USARTn_LCR_WLS_Pos) /*!< USARTn LCR: WLS Mask */ +#define USARTn_LCR_SBS_Pos 2 /*!< USARTn LCR: SBS Position */ +#define USARTn_LCR_SBS_Msk (0x01UL << USARTn_LCR_SBS_Pos) /*!< USARTn LCR: SBS Mask */ +#define USARTn_LCR_PE_Pos 3 /*!< USARTn LCR: PE Position */ +#define USARTn_LCR_PE_Msk (0x01UL << USARTn_LCR_PE_Pos) /*!< USARTn LCR: PE Mask */ +#define USARTn_LCR_PS_Pos 4 /*!< USARTn LCR: PS Position */ +#define USARTn_LCR_PS_Msk (0x03UL << USARTn_LCR_PS_Pos) /*!< USARTn LCR: PS Mask */ +#define USARTn_LCR_BC_Pos 6 /*!< USARTn LCR: BC Position */ +#define USARTn_LCR_BC_Msk (0x01UL << USARTn_LCR_BC_Pos) /*!< USARTn LCR: BC Mask */ +#define USARTn_LCR_DLAB_Pos 7 /*!< USARTn LCR: DLAB Position */ +#define USARTn_LCR_DLAB_Msk (0x01UL << USARTn_LCR_DLAB_Pos) /*!< USARTn LCR: DLAB Mask */ + +/* --------------------------------- USARTn_LSR --------------------------------- */ +#define USARTn_LSR_RDR_Pos 0 /*!< USARTn LSR: RDR Position */ +#define USARTn_LSR_RDR_Msk (0x01UL << USARTn_LSR_RDR_Pos) /*!< USARTn LSR: RDR Mask */ +#define USARTn_LSR_OE_Pos 1 /*!< USARTn LSR: OE Position */ +#define USARTn_LSR_OE_Msk (0x01UL << USARTn_LSR_OE_Pos) /*!< USARTn LSR: OE Mask */ +#define USARTn_LSR_PE_Pos 2 /*!< USARTn LSR: PE Position */ +#define USARTn_LSR_PE_Msk (0x01UL << USARTn_LSR_PE_Pos) /*!< USARTn LSR: PE Mask */ +#define USARTn_LSR_FE_Pos 3 /*!< USARTn LSR: FE Position */ +#define USARTn_LSR_FE_Msk (0x01UL << USARTn_LSR_FE_Pos) /*!< USARTn LSR: FE Mask */ +#define USARTn_LSR_BI_Pos 4 /*!< USARTn LSR: BI Position */ +#define USARTn_LSR_BI_Msk (0x01UL << USARTn_LSR_BI_Pos) /*!< USARTn LSR: BI Mask */ +#define USARTn_LSR_THRE_Pos 5 /*!< USARTn LSR: THRE Position */ +#define USARTn_LSR_THRE_Msk (0x01UL << USARTn_LSR_THRE_Pos) /*!< USARTn LSR: THRE Mask */ +#define USARTn_LSR_TEMT_Pos 6 /*!< USARTn LSR: TEMT Position */ +#define USARTn_LSR_TEMT_Msk (0x01UL << USARTn_LSR_TEMT_Pos) /*!< USARTn LSR: TEMT Mask */ +#define USARTn_LSR_RXFE_Pos 7 /*!< USARTn LSR: RXFE Position */ +#define USARTn_LSR_RXFE_Msk (0x01UL << USARTn_LSR_RXFE_Pos) /*!< USARTn LSR: RXFE Mask */ +#define USARTn_LSR_TXERR_Pos 8 /*!< USARTn LSR: TXERR Position */ +#define USARTn_LSR_TXERR_Msk (0x01UL << USARTn_LSR_TXERR_Pos) /*!< USARTn LSR: TXERR Mask */ + +/* --------------------------------- USARTn_SCR --------------------------------- */ +#define USARTn_SCR_PAD_Pos 0 /*!< USARTn SCR: PAD Position */ +#define USARTn_SCR_PAD_Msk (0x000000ffUL << USARTn_SCR_PAD_Pos) /*!< USARTn SCR: PAD Mask */ + +/* --------------------------------- USARTn_ACR --------------------------------- */ +#define USARTn_ACR_START_Pos 0 /*!< USARTn ACR: START Position */ +#define USARTn_ACR_START_Msk (0x01UL << USARTn_ACR_START_Pos) /*!< USARTn ACR: START Mask */ +#define USARTn_ACR_MODE_Pos 1 /*!< USARTn ACR: MODE Position */ +#define USARTn_ACR_MODE_Msk (0x01UL << USARTn_ACR_MODE_Pos) /*!< USARTn ACR: MODE Mask */ +#define USARTn_ACR_AUTORESTART_Pos 2 /*!< USARTn ACR: AUTORESTART Position */ +#define USARTn_ACR_AUTORESTART_Msk (0x01UL << USARTn_ACR_AUTORESTART_Pos) /*!< USARTn ACR: AUTORESTART Mask */ +#define USARTn_ACR_ABEOINTCLR_Pos 8 /*!< USARTn ACR: ABEOINTCLR Position */ +#define USARTn_ACR_ABEOINTCLR_Msk (0x01UL << USARTn_ACR_ABEOINTCLR_Pos) /*!< USARTn ACR: ABEOINTCLR Mask */ +#define USARTn_ACR_ABTOINTCLR_Pos 9 /*!< USARTn ACR: ABTOINTCLR Position */ +#define USARTn_ACR_ABTOINTCLR_Msk (0x01UL << USARTn_ACR_ABTOINTCLR_Pos) /*!< USARTn ACR: ABTOINTCLR Mask */ + +/* --------------------------------- USARTn_ICR --------------------------------- */ +#define USARTn_ICR_IRDAEN_Pos 0 /*!< USARTn ICR: IRDAEN Position */ +#define USARTn_ICR_IRDAEN_Msk (0x01UL << USARTn_ICR_IRDAEN_Pos) /*!< USARTn ICR: IRDAEN Mask */ +#define USARTn_ICR_IRDAINV_Pos 1 /*!< USARTn ICR: IRDAINV Position */ +#define USARTn_ICR_IRDAINV_Msk (0x01UL << USARTn_ICR_IRDAINV_Pos) /*!< USARTn ICR: IRDAINV Mask */ +#define USARTn_ICR_FIXPULSEEN_Pos 2 /*!< USARTn ICR: FIXPULSEEN Position */ +#define USARTn_ICR_FIXPULSEEN_Msk (0x01UL << USARTn_ICR_FIXPULSEEN_Pos) /*!< USARTn ICR: FIXPULSEEN Mask */ +#define USARTn_ICR_PULSEDIV_Pos 3 /*!< USARTn ICR: PULSEDIV Position */ +#define USARTn_ICR_PULSEDIV_Msk (0x07UL << USARTn_ICR_PULSEDIV_Pos) /*!< USARTn ICR: PULSEDIV Mask */ + +/* --------------------------------- USARTn_FDR --------------------------------- */ +#define USARTn_FDR_DIVADDVAL_Pos 0 /*!< USARTn FDR: DIVADDVAL Position */ +#define USARTn_FDR_DIVADDVAL_Msk (0x0fUL << USARTn_FDR_DIVADDVAL_Pos) /*!< USARTn FDR: DIVADDVAL Mask */ +#define USARTn_FDR_MULVAL_Pos 4 /*!< USARTn FDR: MULVAL Position */ +#define USARTn_FDR_MULVAL_Msk (0x0fUL << USARTn_FDR_MULVAL_Pos) /*!< USARTn FDR: MULVAL Mask */ + +/* --------------------------------- USARTn_OSR --------------------------------- */ +#define USARTn_OSR_OSFRAC_Pos 1 /*!< USARTn OSR: OSFRAC Position */ +#define USARTn_OSR_OSFRAC_Msk (0x07UL << USARTn_OSR_OSFRAC_Pos) /*!< USARTn OSR: OSFRAC Mask */ +#define USARTn_OSR_OSINT_Pos 4 /*!< USARTn OSR: OSINT Position */ +#define USARTn_OSR_OSINT_Msk (0x0fUL << USARTn_OSR_OSINT_Pos) /*!< USARTn OSR: OSINT Mask */ +#define USARTn_OSR_FDINT_Pos 8 /*!< USARTn OSR: FDINT Position */ +#define USARTn_OSR_FDINT_Msk (0x7fUL << USARTn_OSR_FDINT_Pos) /*!< USARTn OSR: FDINT Mask */ + +/* --------------------------------- USARTn_HDEN -------------------------------- */ +#define USARTn_HDEN_HDEN_Pos 0 /*!< USARTn HDEN: HDEN Position */ +#define USARTn_HDEN_HDEN_Msk (0x01UL << USARTn_HDEN_HDEN_Pos) /*!< USARTn HDEN: HDEN Mask */ + +/* ------------------------------- USARTn_SCICTRL ------------------------------- */ +#define USARTn_SCICTRL_SCIEN_Pos 0 /*!< USARTn SCICTRL: SCIEN Position */ +#define USARTn_SCICTRL_SCIEN_Msk (0x01UL << USARTn_SCICTRL_SCIEN_Pos) /*!< USARTn SCICTRL: SCIEN Mask */ +#define USARTn_SCICTRL_NACKDIS_Pos 1 /*!< USARTn SCICTRL: NACKDIS Position */ +#define USARTn_SCICTRL_NACKDIS_Msk (0x01UL << USARTn_SCICTRL_NACKDIS_Pos) /*!< USARTn SCICTRL: NACKDIS Mask */ +#define USARTn_SCICTRL_PROTSEL_Pos 2 /*!< USARTn SCICTRL: PROTSEL Position */ +#define USARTn_SCICTRL_PROTSEL_Msk (0x01UL << USARTn_SCICTRL_PROTSEL_Pos) /*!< USARTn SCICTRL: PROTSEL Mask */ +#define USARTn_SCICTRL_TXRETRY_Pos 5 /*!< USARTn SCICTRL: TXRETRY Position */ +#define USARTn_SCICTRL_TXRETRY_Msk (0x07UL << USARTn_SCICTRL_TXRETRY_Pos) /*!< USARTn SCICTRL: TXRETRY Mask */ +#define USARTn_SCICTRL_GUARDTIME_Pos 8 /*!< USARTn SCICTRL: GUARDTIME Position */ +#define USARTn_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USARTn_SCICTRL_GUARDTIME_Pos) /*!< USARTn SCICTRL: GUARDTIME Mask */ + +/* ------------------------------ USARTn_RS485CTRL ------------------------------ */ +#define USARTn_RS485CTRL_NMMEN_Pos 0 /*!< USARTn RS485CTRL: NMMEN Position */ +#define USARTn_RS485CTRL_NMMEN_Msk (0x01UL << USARTn_RS485CTRL_NMMEN_Pos) /*!< USARTn RS485CTRL: NMMEN Mask */ +#define USARTn_RS485CTRL_RXDIS_Pos 1 /*!< USARTn RS485CTRL: RXDIS Position */ +#define USARTn_RS485CTRL_RXDIS_Msk (0x01UL << USARTn_RS485CTRL_RXDIS_Pos) /*!< USARTn RS485CTRL: RXDIS Mask */ +#define USARTn_RS485CTRL_AADEN_Pos 2 /*!< USARTn RS485CTRL: AADEN Position */ +#define USARTn_RS485CTRL_AADEN_Msk (0x01UL << USARTn_RS485CTRL_AADEN_Pos) /*!< USARTn RS485CTRL: AADEN Mask */ +#define USARTn_RS485CTRL_DCTRL_Pos 4 /*!< USARTn RS485CTRL: DCTRL Position */ +#define USARTn_RS485CTRL_DCTRL_Msk (0x01UL << USARTn_RS485CTRL_DCTRL_Pos) /*!< USARTn RS485CTRL: DCTRL Mask */ +#define USARTn_RS485CTRL_OINV_Pos 5 /*!< USARTn RS485CTRL: OINV Position */ +#define USARTn_RS485CTRL_OINV_Msk (0x01UL << USARTn_RS485CTRL_OINV_Pos) /*!< USARTn RS485CTRL: OINV Mask */ + +/* ---------------------------- USARTn_RS485ADRMATCH ---------------------------- */ +#define USARTn_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USARTn RS485ADRMATCH: ADRMATCH Position */ +#define USARTn_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USARTn_RS485ADRMATCH_ADRMATCH_Pos) /*!< USARTn RS485ADRMATCH: ADRMATCH Mask */ + +/* ------------------------------- USARTn_RS485DLY ------------------------------ */ +#define USARTn_RS485DLY_DLY_Pos 0 /*!< USARTn RS485DLY: DLY Position */ +#define USARTn_RS485DLY_DLY_Msk (0x000000ffUL << USARTn_RS485DLY_DLY_Pos) /*!< USARTn RS485DLY: DLY Mask */ + +/* ------------------------------- USARTn_SYNCCTRL ------------------------------ */ +#define USARTn_SYNCCTRL_SYNC_Pos 0 /*!< USARTn SYNCCTRL: SYNC Position */ +#define USARTn_SYNCCTRL_SYNC_Msk (0x01UL << USARTn_SYNCCTRL_SYNC_Pos) /*!< USARTn SYNCCTRL: SYNC Mask */ +#define USARTn_SYNCCTRL_CSRC_Pos 1 /*!< USARTn SYNCCTRL: CSRC Position */ +#define USARTn_SYNCCTRL_CSRC_Msk (0x01UL << USARTn_SYNCCTRL_CSRC_Pos) /*!< USARTn SYNCCTRL: CSRC Mask */ +#define USARTn_SYNCCTRL_FES_Pos 2 /*!< USARTn SYNCCTRL: FES Position */ +#define USARTn_SYNCCTRL_FES_Msk (0x01UL << USARTn_SYNCCTRL_FES_Pos) /*!< USARTn SYNCCTRL: FES Mask */ +#define USARTn_SYNCCTRL_TSBYPASS_Pos 3 /*!< USARTn SYNCCTRL: TSBYPASS Position */ +#define USARTn_SYNCCTRL_TSBYPASS_Msk (0x01UL << USARTn_SYNCCTRL_TSBYPASS_Pos) /*!< USARTn SYNCCTRL: TSBYPASS Mask */ +#define USARTn_SYNCCTRL_CSCEN_Pos 4 /*!< USARTn SYNCCTRL: CSCEN Position */ +#define USARTn_SYNCCTRL_CSCEN_Msk (0x01UL << USARTn_SYNCCTRL_CSCEN_Pos) /*!< USARTn SYNCCTRL: CSCEN Mask */ +#define USARTn_SYNCCTRL_SSSDIS_Pos 5 /*!< USARTn SYNCCTRL: SSSDIS Position */ +#define USARTn_SYNCCTRL_SSSDIS_Msk (0x01UL << USARTn_SYNCCTRL_SSSDIS_Pos) /*!< USARTn SYNCCTRL: SSSDIS Mask */ +#define USARTn_SYNCCTRL_CCCLR_Pos 6 /*!< USARTn SYNCCTRL: CCCLR Position */ +#define USARTn_SYNCCTRL_CCCLR_Msk (0x01UL << USARTn_SYNCCTRL_CCCLR_Pos) /*!< USARTn SYNCCTRL: CCCLR Mask */ + +/* --------------------------------- USARTn_TER --------------------------------- */ +#define USARTn_TER_TXEN_Pos 0 /*!< USARTn TER: TXEN Position */ +#define USARTn_TER_TXEN_Msk (0x01UL << USARTn_TER_TXEN_Pos) /*!< USARTn TER: TXEN Mask */ + + +/* ================================================================================ */ +/* ================ struct 'USART0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- USART0_RBR --------------------------------- */ +#define USART0_RBR_RBR_Pos 0 /*!< USART0 RBR: RBR Position */ +#define USART0_RBR_RBR_Msk (0x000000ffUL << USART0_RBR_RBR_Pos) /*!< USART0 RBR: RBR Mask */ + +/* --------------------------------- USART0_THR --------------------------------- */ +#define USART0_THR_THR_Pos 0 /*!< USART0 THR: THR Position */ +#define USART0_THR_THR_Msk (0x000000ffUL << USART0_THR_THR_Pos) /*!< USART0 THR: THR Mask */ + +/* --------------------------------- USART0_DLL --------------------------------- */ +#define USART0_DLL_DLLSB_Pos 0 /*!< USART0 DLL: DLLSB Position */ +#define USART0_DLL_DLLSB_Msk (0x000000ffUL << USART0_DLL_DLLSB_Pos) /*!< USART0 DLL: DLLSB Mask */ + +/* --------------------------------- USART0_DLM --------------------------------- */ +#define USART0_DLM_DLMSB_Pos 0 /*!< USART0 DLM: DLMSB Position */ +#define USART0_DLM_DLMSB_Msk (0x000000ffUL << USART0_DLM_DLMSB_Pos) /*!< USART0 DLM: DLMSB Mask */ + +/* --------------------------------- USART0_IER --------------------------------- */ +#define USART0_IER_RBRIE_Pos 0 /*!< USART0 IER: RBRIE Position */ +#define USART0_IER_RBRIE_Msk (0x01UL << USART0_IER_RBRIE_Pos) /*!< USART0 IER: RBRIE Mask */ +#define USART0_IER_THREIE_Pos 1 /*!< USART0 IER: THREIE Position */ +#define USART0_IER_THREIE_Msk (0x01UL << USART0_IER_THREIE_Pos) /*!< USART0 IER: THREIE Mask */ +#define USART0_IER_RXIE_Pos 2 /*!< USART0 IER: RXIE Position */ +#define USART0_IER_RXIE_Msk (0x01UL << USART0_IER_RXIE_Pos) /*!< USART0 IER: RXIE Mask */ +#define USART0_IER_ABEOINTEN_Pos 8 /*!< USART0 IER: ABEOINTEN Position */ +#define USART0_IER_ABEOINTEN_Msk (0x01UL << USART0_IER_ABEOINTEN_Pos) /*!< USART0 IER: ABEOINTEN Mask */ +#define USART0_IER_ABTOINTEN_Pos 9 /*!< USART0 IER: ABTOINTEN Position */ +#define USART0_IER_ABTOINTEN_Msk (0x01UL << USART0_IER_ABTOINTEN_Pos) /*!< USART0 IER: ABTOINTEN Mask */ + +/* --------------------------------- USART0_IIR --------------------------------- */ +#define USART0_IIR_INTSTATUS_Pos 0 /*!< USART0 IIR: INTSTATUS Position */ +#define USART0_IIR_INTSTATUS_Msk (0x01UL << USART0_IIR_INTSTATUS_Pos) /*!< USART0 IIR: INTSTATUS Mask */ +#define USART0_IIR_INTID_Pos 1 /*!< USART0 IIR: INTID Position */ +#define USART0_IIR_INTID_Msk (0x07UL << USART0_IIR_INTID_Pos) /*!< USART0 IIR: INTID Mask */ +#define USART0_IIR_FIFOENABLE_Pos 6 /*!< USART0 IIR: FIFOENABLE Position */ +#define USART0_IIR_FIFOENABLE_Msk (0x03UL << USART0_IIR_FIFOENABLE_Pos) /*!< USART0 IIR: FIFOENABLE Mask */ +#define USART0_IIR_ABEOINT_Pos 8 /*!< USART0 IIR: ABEOINT Position */ +#define USART0_IIR_ABEOINT_Msk (0x01UL << USART0_IIR_ABEOINT_Pos) /*!< USART0 IIR: ABEOINT Mask */ +#define USART0_IIR_ABTOINT_Pos 9 /*!< USART0 IIR: ABTOINT Position */ +#define USART0_IIR_ABTOINT_Msk (0x01UL << USART0_IIR_ABTOINT_Pos) /*!< USART0 IIR: ABTOINT Mask */ + +/* --------------------------------- USART0_FCR --------------------------------- */ +#define USART0_FCR_FIFOEN_Pos 0 /*!< USART0 FCR: FIFOEN Position */ +#define USART0_FCR_FIFOEN_Msk (0x01UL << USART0_FCR_FIFOEN_Pos) /*!< USART0 FCR: FIFOEN Mask */ +#define USART0_FCR_RXFIFORES_Pos 1 /*!< USART0 FCR: RXFIFORES Position */ +#define USART0_FCR_RXFIFORES_Msk (0x01UL << USART0_FCR_RXFIFORES_Pos) /*!< USART0 FCR: RXFIFORES Mask */ +#define USART0_FCR_TXFIFORES_Pos 2 /*!< USART0 FCR: TXFIFORES Position */ +#define USART0_FCR_TXFIFORES_Msk (0x01UL << USART0_FCR_TXFIFORES_Pos) /*!< USART0 FCR: TXFIFORES Mask */ +#define USART0_FCR_DMAMODE_Pos 3 /*!< USART0 FCR: DMAMODE Position */ +#define USART0_FCR_DMAMODE_Msk (0x01UL << USART0_FCR_DMAMODE_Pos) /*!< USART0 FCR: DMAMODE Mask */ +#define USART0_FCR_RXTRIGLVL_Pos 6 /*!< USART0 FCR: RXTRIGLVL Position */ +#define USART0_FCR_RXTRIGLVL_Msk (0x03UL << USART0_FCR_RXTRIGLVL_Pos) /*!< USART0 FCR: RXTRIGLVL Mask */ + +/* --------------------------------- USART0_LCR --------------------------------- */ +#define USART0_LCR_WLS_Pos 0 /*!< USART0 LCR: WLS Position */ +#define USART0_LCR_WLS_Msk (0x03UL << USART0_LCR_WLS_Pos) /*!< USART0 LCR: WLS Mask */ +#define USART0_LCR_SBS_Pos 2 /*!< USART0 LCR: SBS Position */ +#define USART0_LCR_SBS_Msk (0x01UL << USART0_LCR_SBS_Pos) /*!< USART0 LCR: SBS Mask */ +#define USART0_LCR_PE_Pos 3 /*!< USART0 LCR: PE Position */ +#define USART0_LCR_PE_Msk (0x01UL << USART0_LCR_PE_Pos) /*!< USART0 LCR: PE Mask */ +#define USART0_LCR_PS_Pos 4 /*!< USART0 LCR: PS Position */ +#define USART0_LCR_PS_Msk (0x03UL << USART0_LCR_PS_Pos) /*!< USART0 LCR: PS Mask */ +#define USART0_LCR_BC_Pos 6 /*!< USART0 LCR: BC Position */ +#define USART0_LCR_BC_Msk (0x01UL << USART0_LCR_BC_Pos) /*!< USART0 LCR: BC Mask */ +#define USART0_LCR_DLAB_Pos 7 /*!< USART0 LCR: DLAB Position */ +#define USART0_LCR_DLAB_Msk (0x01UL << USART0_LCR_DLAB_Pos) /*!< USART0 LCR: DLAB Mask */ + +/* --------------------------------- USART0_LSR --------------------------------- */ +#define USART0_LSR_RDR_Pos 0 /*!< USART0 LSR: RDR Position */ +#define USART0_LSR_RDR_Msk (0x01UL << USART0_LSR_RDR_Pos) /*!< USART0 LSR: RDR Mask */ +#define USART0_LSR_OE_Pos 1 /*!< USART0 LSR: OE Position */ +#define USART0_LSR_OE_Msk (0x01UL << USART0_LSR_OE_Pos) /*!< USART0 LSR: OE Mask */ +#define USART0_LSR_PE_Pos 2 /*!< USART0 LSR: PE Position */ +#define USART0_LSR_PE_Msk (0x01UL << USART0_LSR_PE_Pos) /*!< USART0 LSR: PE Mask */ +#define USART0_LSR_FE_Pos 3 /*!< USART0 LSR: FE Position */ +#define USART0_LSR_FE_Msk (0x01UL << USART0_LSR_FE_Pos) /*!< USART0 LSR: FE Mask */ +#define USART0_LSR_BI_Pos 4 /*!< USART0 LSR: BI Position */ +#define USART0_LSR_BI_Msk (0x01UL << USART0_LSR_BI_Pos) /*!< USART0 LSR: BI Mask */ +#define USART0_LSR_THRE_Pos 5 /*!< USART0 LSR: THRE Position */ +#define USART0_LSR_THRE_Msk (0x01UL << USART0_LSR_THRE_Pos) /*!< USART0 LSR: THRE Mask */ +#define USART0_LSR_TEMT_Pos 6 /*!< USART0 LSR: TEMT Position */ +#define USART0_LSR_TEMT_Msk (0x01UL << USART0_LSR_TEMT_Pos) /*!< USART0 LSR: TEMT Mask */ +#define USART0_LSR_RXFE_Pos 7 /*!< USART0 LSR: RXFE Position */ +#define USART0_LSR_RXFE_Msk (0x01UL << USART0_LSR_RXFE_Pos) /*!< USART0 LSR: RXFE Mask */ +#define USART0_LSR_TXERR_Pos 8 /*!< USART0 LSR: TXERR Position */ +#define USART0_LSR_TXERR_Msk (0x01UL << USART0_LSR_TXERR_Pos) /*!< USART0 LSR: TXERR Mask */ + +/* --------------------------------- USART0_SCR --------------------------------- */ +#define USART0_SCR_PAD_Pos 0 /*!< USART0 SCR: PAD Position */ +#define USART0_SCR_PAD_Msk (0x000000ffUL << USART0_SCR_PAD_Pos) /*!< USART0 SCR: PAD Mask */ + +/* --------------------------------- USART0_ACR --------------------------------- */ +#define USART0_ACR_START_Pos 0 /*!< USART0 ACR: START Position */ +#define USART0_ACR_START_Msk (0x01UL << USART0_ACR_START_Pos) /*!< USART0 ACR: START Mask */ +#define USART0_ACR_MODE_Pos 1 /*!< USART0 ACR: MODE Position */ +#define USART0_ACR_MODE_Msk (0x01UL << USART0_ACR_MODE_Pos) /*!< USART0 ACR: MODE Mask */ +#define USART0_ACR_AUTORESTART_Pos 2 /*!< USART0 ACR: AUTORESTART Position */ +#define USART0_ACR_AUTORESTART_Msk (0x01UL << USART0_ACR_AUTORESTART_Pos) /*!< USART0 ACR: AUTORESTART Mask */ +#define USART0_ACR_ABEOINTCLR_Pos 8 /*!< USART0 ACR: ABEOINTCLR Position */ +#define USART0_ACR_ABEOINTCLR_Msk (0x01UL << USART0_ACR_ABEOINTCLR_Pos) /*!< USART0 ACR: ABEOINTCLR Mask */ +#define USART0_ACR_ABTOINTCLR_Pos 9 /*!< USART0 ACR: ABTOINTCLR Position */ +#define USART0_ACR_ABTOINTCLR_Msk (0x01UL << USART0_ACR_ABTOINTCLR_Pos) /*!< USART0 ACR: ABTOINTCLR Mask */ + +/* --------------------------------- USART0_ICR --------------------------------- */ +#define USART0_ICR_IRDAEN_Pos 0 /*!< USART0 ICR: IRDAEN Position */ +#define USART0_ICR_IRDAEN_Msk (0x01UL << USART0_ICR_IRDAEN_Pos) /*!< USART0 ICR: IRDAEN Mask */ +#define USART0_ICR_IRDAINV_Pos 1 /*!< USART0 ICR: IRDAINV Position */ +#define USART0_ICR_IRDAINV_Msk (0x01UL << USART0_ICR_IRDAINV_Pos) /*!< USART0 ICR: IRDAINV Mask */ +#define USART0_ICR_FIXPULSEEN_Pos 2 /*!< USART0 ICR: FIXPULSEEN Position */ +#define USART0_ICR_FIXPULSEEN_Msk (0x01UL << USART0_ICR_FIXPULSEEN_Pos) /*!< USART0 ICR: FIXPULSEEN Mask */ +#define USART0_ICR_PULSEDIV_Pos 3 /*!< USART0 ICR: PULSEDIV Position */ +#define USART0_ICR_PULSEDIV_Msk (0x07UL << USART0_ICR_PULSEDIV_Pos) /*!< USART0 ICR: PULSEDIV Mask */ + +/* --------------------------------- USART0_FDR --------------------------------- */ +#define USART0_FDR_DIVADDVAL_Pos 0 /*!< USART0 FDR: DIVADDVAL Position */ +#define USART0_FDR_DIVADDVAL_Msk (0x0fUL << USART0_FDR_DIVADDVAL_Pos) /*!< USART0 FDR: DIVADDVAL Mask */ +#define USART0_FDR_MULVAL_Pos 4 /*!< USART0 FDR: MULVAL Position */ +#define USART0_FDR_MULVAL_Msk (0x0fUL << USART0_FDR_MULVAL_Pos) /*!< USART0 FDR: MULVAL Mask */ + +/* --------------------------------- USART0_OSR --------------------------------- */ +#define USART0_OSR_OSFRAC_Pos 1 /*!< USART0 OSR: OSFRAC Position */ +#define USART0_OSR_OSFRAC_Msk (0x07UL << USART0_OSR_OSFRAC_Pos) /*!< USART0 OSR: OSFRAC Mask */ +#define USART0_OSR_OSINT_Pos 4 /*!< USART0 OSR: OSINT Position */ +#define USART0_OSR_OSINT_Msk (0x0fUL << USART0_OSR_OSINT_Pos) /*!< USART0 OSR: OSINT Mask */ +#define USART0_OSR_FDINT_Pos 8 /*!< USART0 OSR: FDINT Position */ +#define USART0_OSR_FDINT_Msk (0x7fUL << USART0_OSR_FDINT_Pos) /*!< USART0 OSR: FDINT Mask */ + +/* --------------------------------- USART0_HDEN -------------------------------- */ +#define USART0_HDEN_HDEN_Pos 0 /*!< USART0 HDEN: HDEN Position */ +#define USART0_HDEN_HDEN_Msk (0x01UL << USART0_HDEN_HDEN_Pos) /*!< USART0 HDEN: HDEN Mask */ + +/* ------------------------------- USART0_SCICTRL ------------------------------- */ +#define USART0_SCICTRL_SCIEN_Pos 0 /*!< USART0 SCICTRL: SCIEN Position */ +#define USART0_SCICTRL_SCIEN_Msk (0x01UL << USART0_SCICTRL_SCIEN_Pos) /*!< USART0 SCICTRL: SCIEN Mask */ +#define USART0_SCICTRL_NACKDIS_Pos 1 /*!< USART0 SCICTRL: NACKDIS Position */ +#define USART0_SCICTRL_NACKDIS_Msk (0x01UL << USART0_SCICTRL_NACKDIS_Pos) /*!< USART0 SCICTRL: NACKDIS Mask */ +#define USART0_SCICTRL_PROTSEL_Pos 2 /*!< USART0 SCICTRL: PROTSEL Position */ +#define USART0_SCICTRL_PROTSEL_Msk (0x01UL << USART0_SCICTRL_PROTSEL_Pos) /*!< USART0 SCICTRL: PROTSEL Mask */ +#define USART0_SCICTRL_TXRETRY_Pos 5 /*!< USART0 SCICTRL: TXRETRY Position */ +#define USART0_SCICTRL_TXRETRY_Msk (0x07UL << USART0_SCICTRL_TXRETRY_Pos) /*!< USART0 SCICTRL: TXRETRY Mask */ +#define USART0_SCICTRL_GUARDTIME_Pos 8 /*!< USART0 SCICTRL: GUARDTIME Position */ +#define USART0_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USART0_SCICTRL_GUARDTIME_Pos) /*!< USART0 SCICTRL: GUARDTIME Mask */ + +/* ------------------------------ USART0_RS485CTRL ------------------------------ */ +#define USART0_RS485CTRL_NMMEN_Pos 0 /*!< USART0 RS485CTRL: NMMEN Position */ +#define USART0_RS485CTRL_NMMEN_Msk (0x01UL << USART0_RS485CTRL_NMMEN_Pos) /*!< USART0 RS485CTRL: NMMEN Mask */ +#define USART0_RS485CTRL_RXDIS_Pos 1 /*!< USART0 RS485CTRL: RXDIS Position */ +#define USART0_RS485CTRL_RXDIS_Msk (0x01UL << USART0_RS485CTRL_RXDIS_Pos) /*!< USART0 RS485CTRL: RXDIS Mask */ +#define USART0_RS485CTRL_AADEN_Pos 2 /*!< USART0 RS485CTRL: AADEN Position */ +#define USART0_RS485CTRL_AADEN_Msk (0x01UL << USART0_RS485CTRL_AADEN_Pos) /*!< USART0 RS485CTRL: AADEN Mask */ +#define USART0_RS485CTRL_DCTRL_Pos 4 /*!< USART0 RS485CTRL: DCTRL Position */ +#define USART0_RS485CTRL_DCTRL_Msk (0x01UL << USART0_RS485CTRL_DCTRL_Pos) /*!< USART0 RS485CTRL: DCTRL Mask */ +#define USART0_RS485CTRL_OINV_Pos 5 /*!< USART0 RS485CTRL: OINV Position */ +#define USART0_RS485CTRL_OINV_Msk (0x01UL << USART0_RS485CTRL_OINV_Pos) /*!< USART0 RS485CTRL: OINV Mask */ + +/* ---------------------------- USART0_RS485ADRMATCH ---------------------------- */ +#define USART0_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USART0 RS485ADRMATCH: ADRMATCH Position */ +#define USART0_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USART0_RS485ADRMATCH_ADRMATCH_Pos) /*!< USART0 RS485ADRMATCH: ADRMATCH Mask */ + +/* ------------------------------- USART0_RS485DLY ------------------------------ */ +#define USART0_RS485DLY_DLY_Pos 0 /*!< USART0 RS485DLY: DLY Position */ +#define USART0_RS485DLY_DLY_Msk (0x000000ffUL << USART0_RS485DLY_DLY_Pos) /*!< USART0 RS485DLY: DLY Mask */ + +/* ------------------------------- USART0_SYNCCTRL ------------------------------ */ +#define USART0_SYNCCTRL_SYNC_Pos 0 /*!< USART0 SYNCCTRL: SYNC Position */ +#define USART0_SYNCCTRL_SYNC_Msk (0x01UL << USART0_SYNCCTRL_SYNC_Pos) /*!< USART0 SYNCCTRL: SYNC Mask */ +#define USART0_SYNCCTRL_CSRC_Pos 1 /*!< USART0 SYNCCTRL: CSRC Position */ +#define USART0_SYNCCTRL_CSRC_Msk (0x01UL << USART0_SYNCCTRL_CSRC_Pos) /*!< USART0 SYNCCTRL: CSRC Mask */ +#define USART0_SYNCCTRL_FES_Pos 2 /*!< USART0 SYNCCTRL: FES Position */ +#define USART0_SYNCCTRL_FES_Msk (0x01UL << USART0_SYNCCTRL_FES_Pos) /*!< USART0 SYNCCTRL: FES Mask */ +#define USART0_SYNCCTRL_TSBYPASS_Pos 3 /*!< USART0 SYNCCTRL: TSBYPASS Position */ +#define USART0_SYNCCTRL_TSBYPASS_Msk (0x01UL << USART0_SYNCCTRL_TSBYPASS_Pos) /*!< USART0 SYNCCTRL: TSBYPASS Mask */ +#define USART0_SYNCCTRL_CSCEN_Pos 4 /*!< USART0 SYNCCTRL: CSCEN Position */ +#define USART0_SYNCCTRL_CSCEN_Msk (0x01UL << USART0_SYNCCTRL_CSCEN_Pos) /*!< USART0 SYNCCTRL: CSCEN Mask */ +#define USART0_SYNCCTRL_SSSDIS_Pos 5 /*!< USART0 SYNCCTRL: SSSDIS Position */ +#define USART0_SYNCCTRL_SSSDIS_Msk (0x01UL << USART0_SYNCCTRL_SSSDIS_Pos) /*!< USART0 SYNCCTRL: SSSDIS Mask */ +#define USART0_SYNCCTRL_CCCLR_Pos 6 /*!< USART0 SYNCCTRL: CCCLR Position */ +#define USART0_SYNCCTRL_CCCLR_Msk (0x01UL << USART0_SYNCCTRL_CCCLR_Pos) /*!< USART0 SYNCCTRL: CCCLR Mask */ + +/* --------------------------------- USART0_TER --------------------------------- */ +#define USART0_TER_TXEN_Pos 0 /*!< USART0 TER: TXEN Position */ +#define USART0_TER_TXEN_Msk (0x01UL << USART0_TER_TXEN_Pos) /*!< USART0 TER: TXEN Mask */ + + +/* ================================================================================ */ +/* ================ struct 'USART2' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- USART2_DLL --------------------------------- */ +#define USART2_DLL_DLLSB_Pos 0 /*!< USART2 DLL: DLLSB Position */ +#define USART2_DLL_DLLSB_Msk (0x000000ffUL << USART2_DLL_DLLSB_Pos) /*!< USART2 DLL: DLLSB Mask */ + +/* --------------------------------- USART2_THR --------------------------------- */ +#define USART2_THR_THR_Pos 0 /*!< USART2 THR: THR Position */ +#define USART2_THR_THR_Msk (0x000000ffUL << USART2_THR_THR_Pos) /*!< USART2 THR: THR Mask */ + +/* --------------------------------- USART2_RBR --------------------------------- */ +#define USART2_RBR_RBR_Pos 0 /*!< USART2 RBR: RBR Position */ +#define USART2_RBR_RBR_Msk (0x000000ffUL << USART2_RBR_RBR_Pos) /*!< USART2 RBR: RBR Mask */ + +/* --------------------------------- USART2_IER --------------------------------- */ +#define USART2_IER_RBRIE_Pos 0 /*!< USART2 IER: RBRIE Position */ +#define USART2_IER_RBRIE_Msk (0x01UL << USART2_IER_RBRIE_Pos) /*!< USART2 IER: RBRIE Mask */ +#define USART2_IER_THREIE_Pos 1 /*!< USART2 IER: THREIE Position */ +#define USART2_IER_THREIE_Msk (0x01UL << USART2_IER_THREIE_Pos) /*!< USART2 IER: THREIE Mask */ +#define USART2_IER_RXIE_Pos 2 /*!< USART2 IER: RXIE Position */ +#define USART2_IER_RXIE_Msk (0x01UL << USART2_IER_RXIE_Pos) /*!< USART2 IER: RXIE Mask */ +#define USART2_IER_ABEOINTEN_Pos 8 /*!< USART2 IER: ABEOINTEN Position */ +#define USART2_IER_ABEOINTEN_Msk (0x01UL << USART2_IER_ABEOINTEN_Pos) /*!< USART2 IER: ABEOINTEN Mask */ +#define USART2_IER_ABTOINTEN_Pos 9 /*!< USART2 IER: ABTOINTEN Position */ +#define USART2_IER_ABTOINTEN_Msk (0x01UL << USART2_IER_ABTOINTEN_Pos) /*!< USART2 IER: ABTOINTEN Mask */ + +/* --------------------------------- USART2_DLM --------------------------------- */ +#define USART2_DLM_DLMSB_Pos 0 /*!< USART2 DLM: DLMSB Position */ +#define USART2_DLM_DLMSB_Msk (0x000000ffUL << USART2_DLM_DLMSB_Pos) /*!< USART2 DLM: DLMSB Mask */ + +/* --------------------------------- USART2_FCR --------------------------------- */ +#define USART2_FCR_FIFOEN_Pos 0 /*!< USART2 FCR: FIFOEN Position */ +#define USART2_FCR_FIFOEN_Msk (0x01UL << USART2_FCR_FIFOEN_Pos) /*!< USART2 FCR: FIFOEN Mask */ +#define USART2_FCR_RXFIFORES_Pos 1 /*!< USART2 FCR: RXFIFORES Position */ +#define USART2_FCR_RXFIFORES_Msk (0x01UL << USART2_FCR_RXFIFORES_Pos) /*!< USART2 FCR: RXFIFORES Mask */ +#define USART2_FCR_TXFIFORES_Pos 2 /*!< USART2 FCR: TXFIFORES Position */ +#define USART2_FCR_TXFIFORES_Msk (0x01UL << USART2_FCR_TXFIFORES_Pos) /*!< USART2 FCR: TXFIFORES Mask */ +#define USART2_FCR_DMAMODE_Pos 3 /*!< USART2 FCR: DMAMODE Position */ +#define USART2_FCR_DMAMODE_Msk (0x01UL << USART2_FCR_DMAMODE_Pos) /*!< USART2 FCR: DMAMODE Mask */ +#define USART2_FCR_RXTRIGLVL_Pos 6 /*!< USART2 FCR: RXTRIGLVL Position */ +#define USART2_FCR_RXTRIGLVL_Msk (0x03UL << USART2_FCR_RXTRIGLVL_Pos) /*!< USART2 FCR: RXTRIGLVL Mask */ + +/* --------------------------------- USART2_IIR --------------------------------- */ +#define USART2_IIR_INTSTATUS_Pos 0 /*!< USART2 IIR: INTSTATUS Position */ +#define USART2_IIR_INTSTATUS_Msk (0x01UL << USART2_IIR_INTSTATUS_Pos) /*!< USART2 IIR: INTSTATUS Mask */ +#define USART2_IIR_INTID_Pos 1 /*!< USART2 IIR: INTID Position */ +#define USART2_IIR_INTID_Msk (0x07UL << USART2_IIR_INTID_Pos) /*!< USART2 IIR: INTID Mask */ +#define USART2_IIR_FIFOENABLE_Pos 6 /*!< USART2 IIR: FIFOENABLE Position */ +#define USART2_IIR_FIFOENABLE_Msk (0x03UL << USART2_IIR_FIFOENABLE_Pos) /*!< USART2 IIR: FIFOENABLE Mask */ +#define USART2_IIR_ABEOINT_Pos 8 /*!< USART2 IIR: ABEOINT Position */ +#define USART2_IIR_ABEOINT_Msk (0x01UL << USART2_IIR_ABEOINT_Pos) /*!< USART2 IIR: ABEOINT Mask */ +#define USART2_IIR_ABTOINT_Pos 9 /*!< USART2 IIR: ABTOINT Position */ +#define USART2_IIR_ABTOINT_Msk (0x01UL << USART2_IIR_ABTOINT_Pos) /*!< USART2 IIR: ABTOINT Mask */ + +/* --------------------------------- USART2_LCR --------------------------------- */ +#define USART2_LCR_WLS_Pos 0 /*!< USART2 LCR: WLS Position */ +#define USART2_LCR_WLS_Msk (0x03UL << USART2_LCR_WLS_Pos) /*!< USART2 LCR: WLS Mask */ +#define USART2_LCR_SBS_Pos 2 /*!< USART2 LCR: SBS Position */ +#define USART2_LCR_SBS_Msk (0x01UL << USART2_LCR_SBS_Pos) /*!< USART2 LCR: SBS Mask */ +#define USART2_LCR_PE_Pos 3 /*!< USART2 LCR: PE Position */ +#define USART2_LCR_PE_Msk (0x01UL << USART2_LCR_PE_Pos) /*!< USART2 LCR: PE Mask */ +#define USART2_LCR_PS_Pos 4 /*!< USART2 LCR: PS Position */ +#define USART2_LCR_PS_Msk (0x03UL << USART2_LCR_PS_Pos) /*!< USART2 LCR: PS Mask */ +#define USART2_LCR_BC_Pos 6 /*!< USART2 LCR: BC Position */ +#define USART2_LCR_BC_Msk (0x01UL << USART2_LCR_BC_Pos) /*!< USART2 LCR: BC Mask */ +#define USART2_LCR_DLAB_Pos 7 /*!< USART2 LCR: DLAB Position */ +#define USART2_LCR_DLAB_Msk (0x01UL << USART2_LCR_DLAB_Pos) /*!< USART2 LCR: DLAB Mask */ + +/* --------------------------------- USART2_LSR --------------------------------- */ +#define USART2_LSR_RDR_Pos 0 /*!< USART2 LSR: RDR Position */ +#define USART2_LSR_RDR_Msk (0x01UL << USART2_LSR_RDR_Pos) /*!< USART2 LSR: RDR Mask */ +#define USART2_LSR_OE_Pos 1 /*!< USART2 LSR: OE Position */ +#define USART2_LSR_OE_Msk (0x01UL << USART2_LSR_OE_Pos) /*!< USART2 LSR: OE Mask */ +#define USART2_LSR_PE_Pos 2 /*!< USART2 LSR: PE Position */ +#define USART2_LSR_PE_Msk (0x01UL << USART2_LSR_PE_Pos) /*!< USART2 LSR: PE Mask */ +#define USART2_LSR_FE_Pos 3 /*!< USART2 LSR: FE Position */ +#define USART2_LSR_FE_Msk (0x01UL << USART2_LSR_FE_Pos) /*!< USART2 LSR: FE Mask */ +#define USART2_LSR_BI_Pos 4 /*!< USART2 LSR: BI Position */ +#define USART2_LSR_BI_Msk (0x01UL << USART2_LSR_BI_Pos) /*!< USART2 LSR: BI Mask */ +#define USART2_LSR_THRE_Pos 5 /*!< USART2 LSR: THRE Position */ +#define USART2_LSR_THRE_Msk (0x01UL << USART2_LSR_THRE_Pos) /*!< USART2 LSR: THRE Mask */ +#define USART2_LSR_TEMT_Pos 6 /*!< USART2 LSR: TEMT Position */ +#define USART2_LSR_TEMT_Msk (0x01UL << USART2_LSR_TEMT_Pos) /*!< USART2 LSR: TEMT Mask */ +#define USART2_LSR_RXFE_Pos 7 /*!< USART2 LSR: RXFE Position */ +#define USART2_LSR_RXFE_Msk (0x01UL << USART2_LSR_RXFE_Pos) /*!< USART2 LSR: RXFE Mask */ +#define USART2_LSR_TXERR_Pos 8 /*!< USART2 LSR: TXERR Position */ +#define USART2_LSR_TXERR_Msk (0x01UL << USART2_LSR_TXERR_Pos) /*!< USART2 LSR: TXERR Mask */ + +/* --------------------------------- USART2_SCR --------------------------------- */ +#define USART2_SCR_PAD_Pos 0 /*!< USART2 SCR: PAD Position */ +#define USART2_SCR_PAD_Msk (0x000000ffUL << USART2_SCR_PAD_Pos) /*!< USART2 SCR: PAD Mask */ + +/* --------------------------------- USART2_ACR --------------------------------- */ +#define USART2_ACR_START_Pos 0 /*!< USART2 ACR: START Position */ +#define USART2_ACR_START_Msk (0x01UL << USART2_ACR_START_Pos) /*!< USART2 ACR: START Mask */ +#define USART2_ACR_MODE_Pos 1 /*!< USART2 ACR: MODE Position */ +#define USART2_ACR_MODE_Msk (0x01UL << USART2_ACR_MODE_Pos) /*!< USART2 ACR: MODE Mask */ +#define USART2_ACR_AUTORESTART_Pos 2 /*!< USART2 ACR: AUTORESTART Position */ +#define USART2_ACR_AUTORESTART_Msk (0x01UL << USART2_ACR_AUTORESTART_Pos) /*!< USART2 ACR: AUTORESTART Mask */ +#define USART2_ACR_ABEOINTCLR_Pos 8 /*!< USART2 ACR: ABEOINTCLR Position */ +#define USART2_ACR_ABEOINTCLR_Msk (0x01UL << USART2_ACR_ABEOINTCLR_Pos) /*!< USART2 ACR: ABEOINTCLR Mask */ +#define USART2_ACR_ABTOINTCLR_Pos 9 /*!< USART2 ACR: ABTOINTCLR Position */ +#define USART2_ACR_ABTOINTCLR_Msk (0x01UL << USART2_ACR_ABTOINTCLR_Pos) /*!< USART2 ACR: ABTOINTCLR Mask */ + +/* --------------------------------- USART2_ICR --------------------------------- */ +#define USART2_ICR_IRDAEN_Pos 0 /*!< USART2 ICR: IRDAEN Position */ +#define USART2_ICR_IRDAEN_Msk (0x01UL << USART2_ICR_IRDAEN_Pos) /*!< USART2 ICR: IRDAEN Mask */ +#define USART2_ICR_IRDAINV_Pos 1 /*!< USART2 ICR: IRDAINV Position */ +#define USART2_ICR_IRDAINV_Msk (0x01UL << USART2_ICR_IRDAINV_Pos) /*!< USART2 ICR: IRDAINV Mask */ +#define USART2_ICR_FIXPULSEEN_Pos 2 /*!< USART2 ICR: FIXPULSEEN Position */ +#define USART2_ICR_FIXPULSEEN_Msk (0x01UL << USART2_ICR_FIXPULSEEN_Pos) /*!< USART2 ICR: FIXPULSEEN Mask */ +#define USART2_ICR_PULSEDIV_Pos 3 /*!< USART2 ICR: PULSEDIV Position */ +#define USART2_ICR_PULSEDIV_Msk (0x07UL << USART2_ICR_PULSEDIV_Pos) /*!< USART2 ICR: PULSEDIV Mask */ + +/* --------------------------------- USART2_FDR --------------------------------- */ +#define USART2_FDR_DIVADDVAL_Pos 0 /*!< USART2 FDR: DIVADDVAL Position */ +#define USART2_FDR_DIVADDVAL_Msk (0x0fUL << USART2_FDR_DIVADDVAL_Pos) /*!< USART2 FDR: DIVADDVAL Mask */ +#define USART2_FDR_MULVAL_Pos 4 /*!< USART2 FDR: MULVAL Position */ +#define USART2_FDR_MULVAL_Msk (0x0fUL << USART2_FDR_MULVAL_Pos) /*!< USART2 FDR: MULVAL Mask */ + +/* --------------------------------- USART2_OSR --------------------------------- */ +#define USART2_OSR_OSFRAC_Pos 1 /*!< USART2 OSR: OSFRAC Position */ +#define USART2_OSR_OSFRAC_Msk (0x07UL << USART2_OSR_OSFRAC_Pos) /*!< USART2 OSR: OSFRAC Mask */ +#define USART2_OSR_OSINT_Pos 4 /*!< USART2 OSR: OSINT Position */ +#define USART2_OSR_OSINT_Msk (0x0fUL << USART2_OSR_OSINT_Pos) /*!< USART2 OSR: OSINT Mask */ +#define USART2_OSR_FDINT_Pos 8 /*!< USART2 OSR: FDINT Position */ +#define USART2_OSR_FDINT_Msk (0x7fUL << USART2_OSR_FDINT_Pos) /*!< USART2 OSR: FDINT Mask */ + +/* --------------------------------- USART2_HDEN -------------------------------- */ +#define USART2_HDEN_HDEN_Pos 0 /*!< USART2 HDEN: HDEN Position */ +#define USART2_HDEN_HDEN_Msk (0x01UL << USART2_HDEN_HDEN_Pos) /*!< USART2 HDEN: HDEN Mask */ + +/* ------------------------------- USART2_SCICTRL ------------------------------- */ +#define USART2_SCICTRL_SCIEN_Pos 0 /*!< USART2 SCICTRL: SCIEN Position */ +#define USART2_SCICTRL_SCIEN_Msk (0x01UL << USART2_SCICTRL_SCIEN_Pos) /*!< USART2 SCICTRL: SCIEN Mask */ +#define USART2_SCICTRL_NACKDIS_Pos 1 /*!< USART2 SCICTRL: NACKDIS Position */ +#define USART2_SCICTRL_NACKDIS_Msk (0x01UL << USART2_SCICTRL_NACKDIS_Pos) /*!< USART2 SCICTRL: NACKDIS Mask */ +#define USART2_SCICTRL_PROTSEL_Pos 2 /*!< USART2 SCICTRL: PROTSEL Position */ +#define USART2_SCICTRL_PROTSEL_Msk (0x01UL << USART2_SCICTRL_PROTSEL_Pos) /*!< USART2 SCICTRL: PROTSEL Mask */ +#define USART2_SCICTRL_TXRETRY_Pos 5 /*!< USART2 SCICTRL: TXRETRY Position */ +#define USART2_SCICTRL_TXRETRY_Msk (0x07UL << USART2_SCICTRL_TXRETRY_Pos) /*!< USART2 SCICTRL: TXRETRY Mask */ +#define USART2_SCICTRL_GUARDTIME_Pos 8 /*!< USART2 SCICTRL: GUARDTIME Position */ +#define USART2_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USART2_SCICTRL_GUARDTIME_Pos) /*!< USART2 SCICTRL: GUARDTIME Mask */ + +/* ------------------------------ USART2_RS485CTRL ------------------------------ */ +#define USART2_RS485CTRL_NMMEN_Pos 0 /*!< USART2 RS485CTRL: NMMEN Position */ +#define USART2_RS485CTRL_NMMEN_Msk (0x01UL << USART2_RS485CTRL_NMMEN_Pos) /*!< USART2 RS485CTRL: NMMEN Mask */ +#define USART2_RS485CTRL_RXDIS_Pos 1 /*!< USART2 RS485CTRL: RXDIS Position */ +#define USART2_RS485CTRL_RXDIS_Msk (0x01UL << USART2_RS485CTRL_RXDIS_Pos) /*!< USART2 RS485CTRL: RXDIS Mask */ +#define USART2_RS485CTRL_AADEN_Pos 2 /*!< USART2 RS485CTRL: AADEN Position */ +#define USART2_RS485CTRL_AADEN_Msk (0x01UL << USART2_RS485CTRL_AADEN_Pos) /*!< USART2 RS485CTRL: AADEN Mask */ +#define USART2_RS485CTRL_DCTRL_Pos 4 /*!< USART2 RS485CTRL: DCTRL Position */ +#define USART2_RS485CTRL_DCTRL_Msk (0x01UL << USART2_RS485CTRL_DCTRL_Pos) /*!< USART2 RS485CTRL: DCTRL Mask */ +#define USART2_RS485CTRL_OINV_Pos 5 /*!< USART2 RS485CTRL: OINV Position */ +#define USART2_RS485CTRL_OINV_Msk (0x01UL << USART2_RS485CTRL_OINV_Pos) /*!< USART2 RS485CTRL: OINV Mask */ + +/* ---------------------------- USART2_RS485ADRMATCH ---------------------------- */ +#define USART2_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USART2 RS485ADRMATCH: ADRMATCH Position */ +#define USART2_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USART2_RS485ADRMATCH_ADRMATCH_Pos) /*!< USART2 RS485ADRMATCH: ADRMATCH Mask */ + +/* ------------------------------- USART2_RS485DLY ------------------------------ */ +#define USART2_RS485DLY_DLY_Pos 0 /*!< USART2 RS485DLY: DLY Position */ +#define USART2_RS485DLY_DLY_Msk (0x000000ffUL << USART2_RS485DLY_DLY_Pos) /*!< USART2 RS485DLY: DLY Mask */ + +/* ------------------------------- USART2_SYNCCTRL ------------------------------ */ +#define USART2_SYNCCTRL_SYNC_Pos 0 /*!< USART2 SYNCCTRL: SYNC Position */ +#define USART2_SYNCCTRL_SYNC_Msk (0x01UL << USART2_SYNCCTRL_SYNC_Pos) /*!< USART2 SYNCCTRL: SYNC Mask */ +#define USART2_SYNCCTRL_CSRC_Pos 1 /*!< USART2 SYNCCTRL: CSRC Position */ +#define USART2_SYNCCTRL_CSRC_Msk (0x01UL << USART2_SYNCCTRL_CSRC_Pos) /*!< USART2 SYNCCTRL: CSRC Mask */ +#define USART2_SYNCCTRL_FES_Pos 2 /*!< USART2 SYNCCTRL: FES Position */ +#define USART2_SYNCCTRL_FES_Msk (0x01UL << USART2_SYNCCTRL_FES_Pos) /*!< USART2 SYNCCTRL: FES Mask */ +#define USART2_SYNCCTRL_TSBYPASS_Pos 3 /*!< USART2 SYNCCTRL: TSBYPASS Position */ +#define USART2_SYNCCTRL_TSBYPASS_Msk (0x01UL << USART2_SYNCCTRL_TSBYPASS_Pos) /*!< USART2 SYNCCTRL: TSBYPASS Mask */ +#define USART2_SYNCCTRL_CSCEN_Pos 4 /*!< USART2 SYNCCTRL: CSCEN Position */ +#define USART2_SYNCCTRL_CSCEN_Msk (0x01UL << USART2_SYNCCTRL_CSCEN_Pos) /*!< USART2 SYNCCTRL: CSCEN Mask */ +#define USART2_SYNCCTRL_SSSDIS_Pos 5 /*!< USART2 SYNCCTRL: SSSDIS Position */ +#define USART2_SYNCCTRL_SSSDIS_Msk (0x01UL << USART2_SYNCCTRL_SSSDIS_Pos) /*!< USART2 SYNCCTRL: SSSDIS Mask */ +#define USART2_SYNCCTRL_CCCLR_Pos 6 /*!< USART2 SYNCCTRL: CCCLR Position */ +#define USART2_SYNCCTRL_CCCLR_Msk (0x01UL << USART2_SYNCCTRL_CCCLR_Pos) /*!< USART2 SYNCCTRL: CCCLR Mask */ + +/* --------------------------------- USART2_TER --------------------------------- */ +#define USART2_TER_TXEN_Pos 0 /*!< USART2 TER: TXEN Position */ +#define USART2_TER_TXEN_Msk (0x01UL << USART2_TER_TXEN_Pos) /*!< USART2 TER: TXEN Mask */ + + +/* ================================================================================ */ +/* ================ struct 'USART3' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- USART3_DLL --------------------------------- */ +#define USART3_DLL_DLLSB_Pos 0 /*!< USART3 DLL: DLLSB Position */ +#define USART3_DLL_DLLSB_Msk (0x000000ffUL << USART3_DLL_DLLSB_Pos) /*!< USART3 DLL: DLLSB Mask */ + +/* --------------------------------- USART3_THR --------------------------------- */ +#define USART3_THR_THR_Pos 0 /*!< USART3 THR: THR Position */ +#define USART3_THR_THR_Msk (0x000000ffUL << USART3_THR_THR_Pos) /*!< USART3 THR: THR Mask */ + +/* --------------------------------- USART3_RBR --------------------------------- */ +#define USART3_RBR_RBR_Pos 0 /*!< USART3 RBR: RBR Position */ +#define USART3_RBR_RBR_Msk (0x000000ffUL << USART3_RBR_RBR_Pos) /*!< USART3 RBR: RBR Mask */ + +/* --------------------------------- USART3_IER --------------------------------- */ +#define USART3_IER_RBRIE_Pos 0 /*!< USART3 IER: RBRIE Position */ +#define USART3_IER_RBRIE_Msk (0x01UL << USART3_IER_RBRIE_Pos) /*!< USART3 IER: RBRIE Mask */ +#define USART3_IER_THREIE_Pos 1 /*!< USART3 IER: THREIE Position */ +#define USART3_IER_THREIE_Msk (0x01UL << USART3_IER_THREIE_Pos) /*!< USART3 IER: THREIE Mask */ +#define USART3_IER_RXIE_Pos 2 /*!< USART3 IER: RXIE Position */ +#define USART3_IER_RXIE_Msk (0x01UL << USART3_IER_RXIE_Pos) /*!< USART3 IER: RXIE Mask */ +#define USART3_IER_ABEOINTEN_Pos 8 /*!< USART3 IER: ABEOINTEN Position */ +#define USART3_IER_ABEOINTEN_Msk (0x01UL << USART3_IER_ABEOINTEN_Pos) /*!< USART3 IER: ABEOINTEN Mask */ +#define USART3_IER_ABTOINTEN_Pos 9 /*!< USART3 IER: ABTOINTEN Position */ +#define USART3_IER_ABTOINTEN_Msk (0x01UL << USART3_IER_ABTOINTEN_Pos) /*!< USART3 IER: ABTOINTEN Mask */ + +/* --------------------------------- USART3_DLM --------------------------------- */ +#define USART3_DLM_DLMSB_Pos 0 /*!< USART3 DLM: DLMSB Position */ +#define USART3_DLM_DLMSB_Msk (0x000000ffUL << USART3_DLM_DLMSB_Pos) /*!< USART3 DLM: DLMSB Mask */ + +/* --------------------------------- USART3_FCR --------------------------------- */ +#define USART3_FCR_FIFOEN_Pos 0 /*!< USART3 FCR: FIFOEN Position */ +#define USART3_FCR_FIFOEN_Msk (0x01UL << USART3_FCR_FIFOEN_Pos) /*!< USART3 FCR: FIFOEN Mask */ +#define USART3_FCR_RXFIFORES_Pos 1 /*!< USART3 FCR: RXFIFORES Position */ +#define USART3_FCR_RXFIFORES_Msk (0x01UL << USART3_FCR_RXFIFORES_Pos) /*!< USART3 FCR: RXFIFORES Mask */ +#define USART3_FCR_TXFIFORES_Pos 2 /*!< USART3 FCR: TXFIFORES Position */ +#define USART3_FCR_TXFIFORES_Msk (0x01UL << USART3_FCR_TXFIFORES_Pos) /*!< USART3 FCR: TXFIFORES Mask */ +#define USART3_FCR_DMAMODE_Pos 3 /*!< USART3 FCR: DMAMODE Position */ +#define USART3_FCR_DMAMODE_Msk (0x01UL << USART3_FCR_DMAMODE_Pos) /*!< USART3 FCR: DMAMODE Mask */ +#define USART3_FCR_RXTRIGLVL_Pos 6 /*!< USART3 FCR: RXTRIGLVL Position */ +#define USART3_FCR_RXTRIGLVL_Msk (0x03UL << USART3_FCR_RXTRIGLVL_Pos) /*!< USART3 FCR: RXTRIGLVL Mask */ + +/* --------------------------------- USART3_IIR --------------------------------- */ +#define USART3_IIR_INTSTATUS_Pos 0 /*!< USART3 IIR: INTSTATUS Position */ +#define USART3_IIR_INTSTATUS_Msk (0x01UL << USART3_IIR_INTSTATUS_Pos) /*!< USART3 IIR: INTSTATUS Mask */ +#define USART3_IIR_INTID_Pos 1 /*!< USART3 IIR: INTID Position */ +#define USART3_IIR_INTID_Msk (0x07UL << USART3_IIR_INTID_Pos) /*!< USART3 IIR: INTID Mask */ +#define USART3_IIR_FIFOENABLE_Pos 6 /*!< USART3 IIR: FIFOENABLE Position */ +#define USART3_IIR_FIFOENABLE_Msk (0x03UL << USART3_IIR_FIFOENABLE_Pos) /*!< USART3 IIR: FIFOENABLE Mask */ +#define USART3_IIR_ABEOINT_Pos 8 /*!< USART3 IIR: ABEOINT Position */ +#define USART3_IIR_ABEOINT_Msk (0x01UL << USART3_IIR_ABEOINT_Pos) /*!< USART3 IIR: ABEOINT Mask */ +#define USART3_IIR_ABTOINT_Pos 9 /*!< USART3 IIR: ABTOINT Position */ +#define USART3_IIR_ABTOINT_Msk (0x01UL << USART3_IIR_ABTOINT_Pos) /*!< USART3 IIR: ABTOINT Mask */ + +/* --------------------------------- USART3_LCR --------------------------------- */ +#define USART3_LCR_WLS_Pos 0 /*!< USART3 LCR: WLS Position */ +#define USART3_LCR_WLS_Msk (0x03UL << USART3_LCR_WLS_Pos) /*!< USART3 LCR: WLS Mask */ +#define USART3_LCR_SBS_Pos 2 /*!< USART3 LCR: SBS Position */ +#define USART3_LCR_SBS_Msk (0x01UL << USART3_LCR_SBS_Pos) /*!< USART3 LCR: SBS Mask */ +#define USART3_LCR_PE_Pos 3 /*!< USART3 LCR: PE Position */ +#define USART3_LCR_PE_Msk (0x01UL << USART3_LCR_PE_Pos) /*!< USART3 LCR: PE Mask */ +#define USART3_LCR_PS_Pos 4 /*!< USART3 LCR: PS Position */ +#define USART3_LCR_PS_Msk (0x03UL << USART3_LCR_PS_Pos) /*!< USART3 LCR: PS Mask */ +#define USART3_LCR_BC_Pos 6 /*!< USART3 LCR: BC Position */ +#define USART3_LCR_BC_Msk (0x01UL << USART3_LCR_BC_Pos) /*!< USART3 LCR: BC Mask */ +#define USART3_LCR_DLAB_Pos 7 /*!< USART3 LCR: DLAB Position */ +#define USART3_LCR_DLAB_Msk (0x01UL << USART3_LCR_DLAB_Pos) /*!< USART3 LCR: DLAB Mask */ + +/* --------------------------------- USART3_LSR --------------------------------- */ +#define USART3_LSR_RDR_Pos 0 /*!< USART3 LSR: RDR Position */ +#define USART3_LSR_RDR_Msk (0x01UL << USART3_LSR_RDR_Pos) /*!< USART3 LSR: RDR Mask */ +#define USART3_LSR_OE_Pos 1 /*!< USART3 LSR: OE Position */ +#define USART3_LSR_OE_Msk (0x01UL << USART3_LSR_OE_Pos) /*!< USART3 LSR: OE Mask */ +#define USART3_LSR_PE_Pos 2 /*!< USART3 LSR: PE Position */ +#define USART3_LSR_PE_Msk (0x01UL << USART3_LSR_PE_Pos) /*!< USART3 LSR: PE Mask */ +#define USART3_LSR_FE_Pos 3 /*!< USART3 LSR: FE Position */ +#define USART3_LSR_FE_Msk (0x01UL << USART3_LSR_FE_Pos) /*!< USART3 LSR: FE Mask */ +#define USART3_LSR_BI_Pos 4 /*!< USART3 LSR: BI Position */ +#define USART3_LSR_BI_Msk (0x01UL << USART3_LSR_BI_Pos) /*!< USART3 LSR: BI Mask */ +#define USART3_LSR_THRE_Pos 5 /*!< USART3 LSR: THRE Position */ +#define USART3_LSR_THRE_Msk (0x01UL << USART3_LSR_THRE_Pos) /*!< USART3 LSR: THRE Mask */ +#define USART3_LSR_TEMT_Pos 6 /*!< USART3 LSR: TEMT Position */ +#define USART3_LSR_TEMT_Msk (0x01UL << USART3_LSR_TEMT_Pos) /*!< USART3 LSR: TEMT Mask */ +#define USART3_LSR_RXFE_Pos 7 /*!< USART3 LSR: RXFE Position */ +#define USART3_LSR_RXFE_Msk (0x01UL << USART3_LSR_RXFE_Pos) /*!< USART3 LSR: RXFE Mask */ +#define USART3_LSR_TXERR_Pos 8 /*!< USART3 LSR: TXERR Position */ +#define USART3_LSR_TXERR_Msk (0x01UL << USART3_LSR_TXERR_Pos) /*!< USART3 LSR: TXERR Mask */ + +/* --------------------------------- USART3_SCR --------------------------------- */ +#define USART3_SCR_PAD_Pos 0 /*!< USART3 SCR: PAD Position */ +#define USART3_SCR_PAD_Msk (0x000000ffUL << USART3_SCR_PAD_Pos) /*!< USART3 SCR: PAD Mask */ + +/* --------------------------------- USART3_ACR --------------------------------- */ +#define USART3_ACR_START_Pos 0 /*!< USART3 ACR: START Position */ +#define USART3_ACR_START_Msk (0x01UL << USART3_ACR_START_Pos) /*!< USART3 ACR: START Mask */ +#define USART3_ACR_MODE_Pos 1 /*!< USART3 ACR: MODE Position */ +#define USART3_ACR_MODE_Msk (0x01UL << USART3_ACR_MODE_Pos) /*!< USART3 ACR: MODE Mask */ +#define USART3_ACR_AUTORESTART_Pos 2 /*!< USART3 ACR: AUTORESTART Position */ +#define USART3_ACR_AUTORESTART_Msk (0x01UL << USART3_ACR_AUTORESTART_Pos) /*!< USART3 ACR: AUTORESTART Mask */ +#define USART3_ACR_ABEOINTCLR_Pos 8 /*!< USART3 ACR: ABEOINTCLR Position */ +#define USART3_ACR_ABEOINTCLR_Msk (0x01UL << USART3_ACR_ABEOINTCLR_Pos) /*!< USART3 ACR: ABEOINTCLR Mask */ +#define USART3_ACR_ABTOINTCLR_Pos 9 /*!< USART3 ACR: ABTOINTCLR Position */ +#define USART3_ACR_ABTOINTCLR_Msk (0x01UL << USART3_ACR_ABTOINTCLR_Pos) /*!< USART3 ACR: ABTOINTCLR Mask */ + +/* --------------------------------- USART3_ICR --------------------------------- */ +#define USART3_ICR_IRDAEN_Pos 0 /*!< USART3 ICR: IRDAEN Position */ +#define USART3_ICR_IRDAEN_Msk (0x01UL << USART3_ICR_IRDAEN_Pos) /*!< USART3 ICR: IRDAEN Mask */ +#define USART3_ICR_IRDAINV_Pos 1 /*!< USART3 ICR: IRDAINV Position */ +#define USART3_ICR_IRDAINV_Msk (0x01UL << USART3_ICR_IRDAINV_Pos) /*!< USART3 ICR: IRDAINV Mask */ +#define USART3_ICR_FIXPULSEEN_Pos 2 /*!< USART3 ICR: FIXPULSEEN Position */ +#define USART3_ICR_FIXPULSEEN_Msk (0x01UL << USART3_ICR_FIXPULSEEN_Pos) /*!< USART3 ICR: FIXPULSEEN Mask */ +#define USART3_ICR_PULSEDIV_Pos 3 /*!< USART3 ICR: PULSEDIV Position */ +#define USART3_ICR_PULSEDIV_Msk (0x07UL << USART3_ICR_PULSEDIV_Pos) /*!< USART3 ICR: PULSEDIV Mask */ + +/* --------------------------------- USART3_FDR --------------------------------- */ +#define USART3_FDR_DIVADDVAL_Pos 0 /*!< USART3 FDR: DIVADDVAL Position */ +#define USART3_FDR_DIVADDVAL_Msk (0x0fUL << USART3_FDR_DIVADDVAL_Pos) /*!< USART3 FDR: DIVADDVAL Mask */ +#define USART3_FDR_MULVAL_Pos 4 /*!< USART3 FDR: MULVAL Position */ +#define USART3_FDR_MULVAL_Msk (0x0fUL << USART3_FDR_MULVAL_Pos) /*!< USART3 FDR: MULVAL Mask */ + +/* --------------------------------- USART3_OSR --------------------------------- */ +#define USART3_OSR_OSFRAC_Pos 1 /*!< USART3 OSR: OSFRAC Position */ +#define USART3_OSR_OSFRAC_Msk (0x07UL << USART3_OSR_OSFRAC_Pos) /*!< USART3 OSR: OSFRAC Mask */ +#define USART3_OSR_OSINT_Pos 4 /*!< USART3 OSR: OSINT Position */ +#define USART3_OSR_OSINT_Msk (0x0fUL << USART3_OSR_OSINT_Pos) /*!< USART3 OSR: OSINT Mask */ +#define USART3_OSR_FDINT_Pos 8 /*!< USART3 OSR: FDINT Position */ +#define USART3_OSR_FDINT_Msk (0x7fUL << USART3_OSR_FDINT_Pos) /*!< USART3 OSR: FDINT Mask */ + +/* --------------------------------- USART3_HDEN -------------------------------- */ +#define USART3_HDEN_HDEN_Pos 0 /*!< USART3 HDEN: HDEN Position */ +#define USART3_HDEN_HDEN_Msk (0x01UL << USART3_HDEN_HDEN_Pos) /*!< USART3 HDEN: HDEN Mask */ + +/* ------------------------------- USART3_SCICTRL ------------------------------- */ +#define USART3_SCICTRL_SCIEN_Pos 0 /*!< USART3 SCICTRL: SCIEN Position */ +#define USART3_SCICTRL_SCIEN_Msk (0x01UL << USART3_SCICTRL_SCIEN_Pos) /*!< USART3 SCICTRL: SCIEN Mask */ +#define USART3_SCICTRL_NACKDIS_Pos 1 /*!< USART3 SCICTRL: NACKDIS Position */ +#define USART3_SCICTRL_NACKDIS_Msk (0x01UL << USART3_SCICTRL_NACKDIS_Pos) /*!< USART3 SCICTRL: NACKDIS Mask */ +#define USART3_SCICTRL_PROTSEL_Pos 2 /*!< USART3 SCICTRL: PROTSEL Position */ +#define USART3_SCICTRL_PROTSEL_Msk (0x01UL << USART3_SCICTRL_PROTSEL_Pos) /*!< USART3 SCICTRL: PROTSEL Mask */ +#define USART3_SCICTRL_TXRETRY_Pos 5 /*!< USART3 SCICTRL: TXRETRY Position */ +#define USART3_SCICTRL_TXRETRY_Msk (0x07UL << USART3_SCICTRL_TXRETRY_Pos) /*!< USART3 SCICTRL: TXRETRY Mask */ +#define USART3_SCICTRL_GUARDTIME_Pos 8 /*!< USART3 SCICTRL: GUARDTIME Position */ +#define USART3_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USART3_SCICTRL_GUARDTIME_Pos) /*!< USART3 SCICTRL: GUARDTIME Mask */ + +/* ------------------------------ USART3_RS485CTRL ------------------------------ */ +#define USART3_RS485CTRL_NMMEN_Pos 0 /*!< USART3 RS485CTRL: NMMEN Position */ +#define USART3_RS485CTRL_NMMEN_Msk (0x01UL << USART3_RS485CTRL_NMMEN_Pos) /*!< USART3 RS485CTRL: NMMEN Mask */ +#define USART3_RS485CTRL_RXDIS_Pos 1 /*!< USART3 RS485CTRL: RXDIS Position */ +#define USART3_RS485CTRL_RXDIS_Msk (0x01UL << USART3_RS485CTRL_RXDIS_Pos) /*!< USART3 RS485CTRL: RXDIS Mask */ +#define USART3_RS485CTRL_AADEN_Pos 2 /*!< USART3 RS485CTRL: AADEN Position */ +#define USART3_RS485CTRL_AADEN_Msk (0x01UL << USART3_RS485CTRL_AADEN_Pos) /*!< USART3 RS485CTRL: AADEN Mask */ +#define USART3_RS485CTRL_DCTRL_Pos 4 /*!< USART3 RS485CTRL: DCTRL Position */ +#define USART3_RS485CTRL_DCTRL_Msk (0x01UL << USART3_RS485CTRL_DCTRL_Pos) /*!< USART3 RS485CTRL: DCTRL Mask */ +#define USART3_RS485CTRL_OINV_Pos 5 /*!< USART3 RS485CTRL: OINV Position */ +#define USART3_RS485CTRL_OINV_Msk (0x01UL << USART3_RS485CTRL_OINV_Pos) /*!< USART3 RS485CTRL: OINV Mask */ + +/* ---------------------------- USART3_RS485ADRMATCH ---------------------------- */ +#define USART3_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USART3 RS485ADRMATCH: ADRMATCH Position */ +#define USART3_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USART3_RS485ADRMATCH_ADRMATCH_Pos) /*!< USART3 RS485ADRMATCH: ADRMATCH Mask */ + +/* ------------------------------- USART3_RS485DLY ------------------------------ */ +#define USART3_RS485DLY_DLY_Pos 0 /*!< USART3 RS485DLY: DLY Position */ +#define USART3_RS485DLY_DLY_Msk (0x000000ffUL << USART3_RS485DLY_DLY_Pos) /*!< USART3 RS485DLY: DLY Mask */ + +/* ------------------------------- USART3_SYNCCTRL ------------------------------ */ +#define USART3_SYNCCTRL_SYNC_Pos 0 /*!< USART3 SYNCCTRL: SYNC Position */ +#define USART3_SYNCCTRL_SYNC_Msk (0x01UL << USART3_SYNCCTRL_SYNC_Pos) /*!< USART3 SYNCCTRL: SYNC Mask */ +#define USART3_SYNCCTRL_CSRC_Pos 1 /*!< USART3 SYNCCTRL: CSRC Position */ +#define USART3_SYNCCTRL_CSRC_Msk (0x01UL << USART3_SYNCCTRL_CSRC_Pos) /*!< USART3 SYNCCTRL: CSRC Mask */ +#define USART3_SYNCCTRL_FES_Pos 2 /*!< USART3 SYNCCTRL: FES Position */ +#define USART3_SYNCCTRL_FES_Msk (0x01UL << USART3_SYNCCTRL_FES_Pos) /*!< USART3 SYNCCTRL: FES Mask */ +#define USART3_SYNCCTRL_TSBYPASS_Pos 3 /*!< USART3 SYNCCTRL: TSBYPASS Position */ +#define USART3_SYNCCTRL_TSBYPASS_Msk (0x01UL << USART3_SYNCCTRL_TSBYPASS_Pos) /*!< USART3 SYNCCTRL: TSBYPASS Mask */ +#define USART3_SYNCCTRL_CSCEN_Pos 4 /*!< USART3 SYNCCTRL: CSCEN Position */ +#define USART3_SYNCCTRL_CSCEN_Msk (0x01UL << USART3_SYNCCTRL_CSCEN_Pos) /*!< USART3 SYNCCTRL: CSCEN Mask */ +#define USART3_SYNCCTRL_SSSDIS_Pos 5 /*!< USART3 SYNCCTRL: SSSDIS Position */ +#define USART3_SYNCCTRL_SSSDIS_Msk (0x01UL << USART3_SYNCCTRL_SSSDIS_Pos) /*!< USART3 SYNCCTRL: SSSDIS Mask */ +#define USART3_SYNCCTRL_CCCLR_Pos 6 /*!< USART3 SYNCCTRL: CCCLR Position */ +#define USART3_SYNCCTRL_CCCLR_Msk (0x01UL << USART3_SYNCCTRL_CCCLR_Pos) /*!< USART3 SYNCCTRL: CCCLR Mask */ + +/* --------------------------------- USART3_TER --------------------------------- */ +#define USART3_TER_TXEN_Pos 0 /*!< USART3 TER: TXEN Position */ +#define USART3_TER_TXEN_Msk (0x01UL << USART3_TER_TXEN_Pos) /*!< USART3 TER: TXEN Mask */ + + +/* ================================================================================ */ +/* ================ struct 'UART1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- UART1_RBR --------------------------------- */ +#define UART1_RBR_RBR_Pos 0 /*!< UART1 RBR: RBR Position */ +#define UART1_RBR_RBR_Msk (0x000000ffUL << UART1_RBR_RBR_Pos) /*!< UART1 RBR: RBR Mask */ + +/* ---------------------------------- UART1_THR --------------------------------- */ +#define UART1_THR_THR_Pos 0 /*!< UART1 THR: THR Position */ +#define UART1_THR_THR_Msk (0x000000ffUL << UART1_THR_THR_Pos) /*!< UART1 THR: THR Mask */ + +/* ---------------------------------- UART1_DLL --------------------------------- */ +#define UART1_DLL_DLLSB_Pos 0 /*!< UART1 DLL: DLLSB Position */ +#define UART1_DLL_DLLSB_Msk (0x000000ffUL << UART1_DLL_DLLSB_Pos) /*!< UART1 DLL: DLLSB Mask */ + +/* ---------------------------------- UART1_DLM --------------------------------- */ +#define UART1_DLM_DLMSB_Pos 0 /*!< UART1 DLM: DLMSB Position */ +#define UART1_DLM_DLMSB_Msk (0x000000ffUL << UART1_DLM_DLMSB_Pos) /*!< UART1 DLM: DLMSB Mask */ + +/* ---------------------------------- UART1_IER --------------------------------- */ +#define UART1_IER_RBRIE_Pos 0 /*!< UART1 IER: RBRIE Position */ +#define UART1_IER_RBRIE_Msk (0x01UL << UART1_IER_RBRIE_Pos) /*!< UART1 IER: RBRIE Mask */ +#define UART1_IER_THREIE_Pos 1 /*!< UART1 IER: THREIE Position */ +#define UART1_IER_THREIE_Msk (0x01UL << UART1_IER_THREIE_Pos) /*!< UART1 IER: THREIE Mask */ +#define UART1_IER_RXIE_Pos 2 /*!< UART1 IER: RXIE Position */ +#define UART1_IER_RXIE_Msk (0x01UL << UART1_IER_RXIE_Pos) /*!< UART1 IER: RXIE Mask */ +#define UART1_IER_MSIE_Pos 3 /*!< UART1 IER: MSIE Position */ +#define UART1_IER_MSIE_Msk (0x01UL << UART1_IER_MSIE_Pos) /*!< UART1 IER: MSIE Mask */ +#define UART1_IER_CTSIE_Pos 7 /*!< UART1 IER: CTSIE Position */ +#define UART1_IER_CTSIE_Msk (0x01UL << UART1_IER_CTSIE_Pos) /*!< UART1 IER: CTSIE Mask */ +#define UART1_IER_ABEOIE_Pos 8 /*!< UART1 IER: ABEOIE Position */ +#define UART1_IER_ABEOIE_Msk (0x01UL << UART1_IER_ABEOIE_Pos) /*!< UART1 IER: ABEOIE Mask */ +#define UART1_IER_ABTOIE_Pos 9 /*!< UART1 IER: ABTOIE Position */ +#define UART1_IER_ABTOIE_Msk (0x01UL << UART1_IER_ABTOIE_Pos) /*!< UART1 IER: ABTOIE Mask */ + +/* ---------------------------------- UART1_IIR --------------------------------- */ +#define UART1_IIR_INTSTATUS_Pos 0 /*!< UART1 IIR: INTSTATUS Position */ +#define UART1_IIR_INTSTATUS_Msk (0x01UL << UART1_IIR_INTSTATUS_Pos) /*!< UART1 IIR: INTSTATUS Mask */ +#define UART1_IIR_INTID_Pos 1 /*!< UART1 IIR: INTID Position */ +#define UART1_IIR_INTID_Msk (0x07UL << UART1_IIR_INTID_Pos) /*!< UART1 IIR: INTID Mask */ +#define UART1_IIR_FIFOENABLE_Pos 6 /*!< UART1 IIR: FIFOENABLE Position */ +#define UART1_IIR_FIFOENABLE_Msk (0x03UL << UART1_IIR_FIFOENABLE_Pos) /*!< UART1 IIR: FIFOENABLE Mask */ +#define UART1_IIR_ABEOINT_Pos 8 /*!< UART1 IIR: ABEOINT Position */ +#define UART1_IIR_ABEOINT_Msk (0x01UL << UART1_IIR_ABEOINT_Pos) /*!< UART1 IIR: ABEOINT Mask */ +#define UART1_IIR_ABTOINT_Pos 9 /*!< UART1 IIR: ABTOINT Position */ +#define UART1_IIR_ABTOINT_Msk (0x01UL << UART1_IIR_ABTOINT_Pos) /*!< UART1 IIR: ABTOINT Mask */ + +/* ---------------------------------- UART1_FCR --------------------------------- */ +#define UART1_FCR_FIFOEN_Pos 0 /*!< UART1 FCR: FIFOEN Position */ +#define UART1_FCR_FIFOEN_Msk (0x01UL << UART1_FCR_FIFOEN_Pos) /*!< UART1 FCR: FIFOEN Mask */ +#define UART1_FCR_RXFIFORES_Pos 1 /*!< UART1 FCR: RXFIFORES Position */ +#define UART1_FCR_RXFIFORES_Msk (0x01UL << UART1_FCR_RXFIFORES_Pos) /*!< UART1 FCR: RXFIFORES Mask */ +#define UART1_FCR_TXFIFORES_Pos 2 /*!< UART1 FCR: TXFIFORES Position */ +#define UART1_FCR_TXFIFORES_Msk (0x01UL << UART1_FCR_TXFIFORES_Pos) /*!< UART1 FCR: TXFIFORES Mask */ +#define UART1_FCR_DMAMODE_Pos 3 /*!< UART1 FCR: DMAMODE Position */ +#define UART1_FCR_DMAMODE_Msk (0x01UL << UART1_FCR_DMAMODE_Pos) /*!< UART1 FCR: DMAMODE Mask */ +#define UART1_FCR_RXTRIGLVL_Pos 6 /*!< UART1 FCR: RXTRIGLVL Position */ +#define UART1_FCR_RXTRIGLVL_Msk (0x03UL << UART1_FCR_RXTRIGLVL_Pos) /*!< UART1 FCR: RXTRIGLVL Mask */ + +/* ---------------------------------- UART1_LCR --------------------------------- */ +#define UART1_LCR_WLS_Pos 0 /*!< UART1 LCR: WLS Position */ +#define UART1_LCR_WLS_Msk (0x03UL << UART1_LCR_WLS_Pos) /*!< UART1 LCR: WLS Mask */ +#define UART1_LCR_SBS_Pos 2 /*!< UART1 LCR: SBS Position */ +#define UART1_LCR_SBS_Msk (0x01UL << UART1_LCR_SBS_Pos) /*!< UART1 LCR: SBS Mask */ +#define UART1_LCR_PE_Pos 3 /*!< UART1 LCR: PE Position */ +#define UART1_LCR_PE_Msk (0x01UL << UART1_LCR_PE_Pos) /*!< UART1 LCR: PE Mask */ +#define UART1_LCR_PS_Pos 4 /*!< UART1 LCR: PS Position */ +#define UART1_LCR_PS_Msk (0x03UL << UART1_LCR_PS_Pos) /*!< UART1 LCR: PS Mask */ +#define UART1_LCR_BC_Pos 6 /*!< UART1 LCR: BC Position */ +#define UART1_LCR_BC_Msk (0x01UL << UART1_LCR_BC_Pos) /*!< UART1 LCR: BC Mask */ +#define UART1_LCR_DLAB_Pos 7 /*!< UART1 LCR: DLAB Position */ +#define UART1_LCR_DLAB_Msk (0x01UL << UART1_LCR_DLAB_Pos) /*!< UART1 LCR: DLAB Mask */ + +/* ---------------------------------- UART1_MCR --------------------------------- */ +#define UART1_MCR_DTRCTRL_Pos 0 /*!< UART1 MCR: DTRCTRL Position */ +#define UART1_MCR_DTRCTRL_Msk (0x01UL << UART1_MCR_DTRCTRL_Pos) /*!< UART1 MCR: DTRCTRL Mask */ +#define UART1_MCR_RTSCTRL_Pos 1 /*!< UART1 MCR: RTSCTRL Position */ +#define UART1_MCR_RTSCTRL_Msk (0x01UL << UART1_MCR_RTSCTRL_Pos) /*!< UART1 MCR: RTSCTRL Mask */ +#define UART1_MCR_LMS_Pos 4 /*!< UART1 MCR: LMS Position */ +#define UART1_MCR_LMS_Msk (0x01UL << UART1_MCR_LMS_Pos) /*!< UART1 MCR: LMS Mask */ +#define UART1_MCR_RTSEN_Pos 6 /*!< UART1 MCR: RTSEN Position */ +#define UART1_MCR_RTSEN_Msk (0x01UL << UART1_MCR_RTSEN_Pos) /*!< UART1 MCR: RTSEN Mask */ +#define UART1_MCR_CTSEN_Pos 7 /*!< UART1 MCR: CTSEN Position */ +#define UART1_MCR_CTSEN_Msk (0x01UL << UART1_MCR_CTSEN_Pos) /*!< UART1 MCR: CTSEN Mask */ + +/* ---------------------------------- UART1_LSR --------------------------------- */ +#define UART1_LSR_RDR_Pos 0 /*!< UART1 LSR: RDR Position */ +#define UART1_LSR_RDR_Msk (0x01UL << UART1_LSR_RDR_Pos) /*!< UART1 LSR: RDR Mask */ +#define UART1_LSR_OE_Pos 1 /*!< UART1 LSR: OE Position */ +#define UART1_LSR_OE_Msk (0x01UL << UART1_LSR_OE_Pos) /*!< UART1 LSR: OE Mask */ +#define UART1_LSR_PE_Pos 2 /*!< UART1 LSR: PE Position */ +#define UART1_LSR_PE_Msk (0x01UL << UART1_LSR_PE_Pos) /*!< UART1 LSR: PE Mask */ +#define UART1_LSR_FE_Pos 3 /*!< UART1 LSR: FE Position */ +#define UART1_LSR_FE_Msk (0x01UL << UART1_LSR_FE_Pos) /*!< UART1 LSR: FE Mask */ +#define UART1_LSR_BI_Pos 4 /*!< UART1 LSR: BI Position */ +#define UART1_LSR_BI_Msk (0x01UL << UART1_LSR_BI_Pos) /*!< UART1 LSR: BI Mask */ +#define UART1_LSR_THRE_Pos 5 /*!< UART1 LSR: THRE Position */ +#define UART1_LSR_THRE_Msk (0x01UL << UART1_LSR_THRE_Pos) /*!< UART1 LSR: THRE Mask */ +#define UART1_LSR_TEMT_Pos 6 /*!< UART1 LSR: TEMT Position */ +#define UART1_LSR_TEMT_Msk (0x01UL << UART1_LSR_TEMT_Pos) /*!< UART1 LSR: TEMT Mask */ +#define UART1_LSR_RXFE_Pos 7 /*!< UART1 LSR: RXFE Position */ +#define UART1_LSR_RXFE_Msk (0x01UL << UART1_LSR_RXFE_Pos) /*!< UART1 LSR: RXFE Mask */ + +/* ---------------------------------- UART1_MSR --------------------------------- */ +#define UART1_MSR_DCTS_Pos 0 /*!< UART1 MSR: DCTS Position */ +#define UART1_MSR_DCTS_Msk (0x01UL << UART1_MSR_DCTS_Pos) /*!< UART1 MSR: DCTS Mask */ +#define UART1_MSR_DDSR_Pos 1 /*!< UART1 MSR: DDSR Position */ +#define UART1_MSR_DDSR_Msk (0x01UL << UART1_MSR_DDSR_Pos) /*!< UART1 MSR: DDSR Mask */ +#define UART1_MSR_TERI_Pos 2 /*!< UART1 MSR: TERI Position */ +#define UART1_MSR_TERI_Msk (0x01UL << UART1_MSR_TERI_Pos) /*!< UART1 MSR: TERI Mask */ +#define UART1_MSR_DDCD_Pos 3 /*!< UART1 MSR: DDCD Position */ +#define UART1_MSR_DDCD_Msk (0x01UL << UART1_MSR_DDCD_Pos) /*!< UART1 MSR: DDCD Mask */ +#define UART1_MSR_CTS_Pos 4 /*!< UART1 MSR: CTS Position */ +#define UART1_MSR_CTS_Msk (0x01UL << UART1_MSR_CTS_Pos) /*!< UART1 MSR: CTS Mask */ +#define UART1_MSR_DSR_Pos 5 /*!< UART1 MSR: DSR Position */ +#define UART1_MSR_DSR_Msk (0x01UL << UART1_MSR_DSR_Pos) /*!< UART1 MSR: DSR Mask */ +#define UART1_MSR_RI_Pos 6 /*!< UART1 MSR: RI Position */ +#define UART1_MSR_RI_Msk (0x01UL << UART1_MSR_RI_Pos) /*!< UART1 MSR: RI Mask */ +#define UART1_MSR_DCD_Pos 7 /*!< UART1 MSR: DCD Position */ +#define UART1_MSR_DCD_Msk (0x01UL << UART1_MSR_DCD_Pos) /*!< UART1 MSR: DCD Mask */ + +/* ---------------------------------- UART1_SCR --------------------------------- */ +#define UART1_SCR_Pad_Pos 0 /*!< UART1 SCR: Pad Position */ +#define UART1_SCR_Pad_Msk (0x000000ffUL << UART1_SCR_Pad_Pos) /*!< UART1 SCR: Pad Mask */ + +/* ---------------------------------- UART1_ACR --------------------------------- */ +#define UART1_ACR_START_Pos 0 /*!< UART1 ACR: START Position */ +#define UART1_ACR_START_Msk (0x01UL << UART1_ACR_START_Pos) /*!< UART1 ACR: START Mask */ +#define UART1_ACR_MODE_Pos 1 /*!< UART1 ACR: MODE Position */ +#define UART1_ACR_MODE_Msk (0x01UL << UART1_ACR_MODE_Pos) /*!< UART1 ACR: MODE Mask */ +#define UART1_ACR_AUTORESTART_Pos 2 /*!< UART1 ACR: AUTORESTART Position */ +#define UART1_ACR_AUTORESTART_Msk (0x01UL << UART1_ACR_AUTORESTART_Pos) /*!< UART1 ACR: AUTORESTART Mask */ +#define UART1_ACR_ABEOINTCLR_Pos 8 /*!< UART1 ACR: ABEOINTCLR Position */ +#define UART1_ACR_ABEOINTCLR_Msk (0x01UL << UART1_ACR_ABEOINTCLR_Pos) /*!< UART1 ACR: ABEOINTCLR Mask */ +#define UART1_ACR_ABTOINTCLR_Pos 9 /*!< UART1 ACR: ABTOINTCLR Position */ +#define UART1_ACR_ABTOINTCLR_Msk (0x01UL << UART1_ACR_ABTOINTCLR_Pos) /*!< UART1 ACR: ABTOINTCLR Mask */ + +/* ---------------------------------- UART1_FDR --------------------------------- */ +#define UART1_FDR_DIVADDVAL_Pos 0 /*!< UART1 FDR: DIVADDVAL Position */ +#define UART1_FDR_DIVADDVAL_Msk (0x0fUL << UART1_FDR_DIVADDVAL_Pos) /*!< UART1 FDR: DIVADDVAL Mask */ +#define UART1_FDR_MULVAL_Pos 4 /*!< UART1 FDR: MULVAL Position */ +#define UART1_FDR_MULVAL_Msk (0x0fUL << UART1_FDR_MULVAL_Pos) /*!< UART1 FDR: MULVAL Mask */ + +/* ------------------------------- UART1_RS485CTRL ------------------------------ */ +#define UART1_RS485CTRL_NMMEN_Pos 0 /*!< UART1 RS485CTRL: NMMEN Position */ +#define UART1_RS485CTRL_NMMEN_Msk (0x01UL << UART1_RS485CTRL_NMMEN_Pos) /*!< UART1 RS485CTRL: NMMEN Mask */ +#define UART1_RS485CTRL_RXDIS_Pos 1 /*!< UART1 RS485CTRL: RXDIS Position */ +#define UART1_RS485CTRL_RXDIS_Msk (0x01UL << UART1_RS485CTRL_RXDIS_Pos) /*!< UART1 RS485CTRL: RXDIS Mask */ +#define UART1_RS485CTRL_AADEN_Pos 2 /*!< UART1 RS485CTRL: AADEN Position */ +#define UART1_RS485CTRL_AADEN_Msk (0x01UL << UART1_RS485CTRL_AADEN_Pos) /*!< UART1 RS485CTRL: AADEN Mask */ +#define UART1_RS485CTRL_SEL_Pos 3 /*!< UART1 RS485CTRL: SEL Position */ +#define UART1_RS485CTRL_SEL_Msk (0x01UL << UART1_RS485CTRL_SEL_Pos) /*!< UART1 RS485CTRL: SEL Mask */ +#define UART1_RS485CTRL_DCTRL_Pos 4 /*!< UART1 RS485CTRL: DCTRL Position */ +#define UART1_RS485CTRL_DCTRL_Msk (0x01UL << UART1_RS485CTRL_DCTRL_Pos) /*!< UART1 RS485CTRL: DCTRL Mask */ +#define UART1_RS485CTRL_OINV_Pos 5 /*!< UART1 RS485CTRL: OINV Position */ +#define UART1_RS485CTRL_OINV_Msk (0x01UL << UART1_RS485CTRL_OINV_Pos) /*!< UART1 RS485CTRL: OINV Mask */ + +/* ----------------------------- UART1_RS485ADRMATCH ---------------------------- */ +#define UART1_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< UART1 RS485ADRMATCH: ADRMATCH Position */ +#define UART1_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << UART1_RS485ADRMATCH_ADRMATCH_Pos) /*!< UART1 RS485ADRMATCH: ADRMATCH Mask */ + +/* ------------------------------- UART1_RS485DLY ------------------------------- */ +#define UART1_RS485DLY_DLY_Pos 0 /*!< UART1 RS485DLY: DLY Position */ +#define UART1_RS485DLY_DLY_Msk (0x000000ffUL << UART1_RS485DLY_DLY_Pos) /*!< UART1 RS485DLY: DLY Mask */ + +/* ---------------------------------- UART1_TER --------------------------------- */ +#define UART1_TER_TXEN_Pos 0 /*!< UART1 TER: TXEN Position */ +#define UART1_TER_TXEN_Msk (0x01UL << UART1_TER_TXEN_Pos) /*!< UART1 TER: TXEN Mask */ + + +/* ================================================================================ */ +/* ================ Group 'SSPn' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- SSPn_CR0 ---------------------------------- */ +#define SSPn_CR0_DSS_Pos 0 /*!< SSPn CR0: DSS Position */ +#define SSPn_CR0_DSS_Msk (0x0fUL << SSPn_CR0_DSS_Pos) /*!< SSPn CR0: DSS Mask */ +#define SSPn_CR0_FRF_Pos 4 /*!< SSPn CR0: FRF Position */ +#define SSPn_CR0_FRF_Msk (0x03UL << SSPn_CR0_FRF_Pos) /*!< SSPn CR0: FRF Mask */ +#define SSPn_CR0_CPOL_Pos 6 /*!< SSPn CR0: CPOL Position */ +#define SSPn_CR0_CPOL_Msk (0x01UL << SSPn_CR0_CPOL_Pos) /*!< SSPn CR0: CPOL Mask */ +#define SSPn_CR0_CPHA_Pos 7 /*!< SSPn CR0: CPHA Position */ +#define SSPn_CR0_CPHA_Msk (0x01UL << SSPn_CR0_CPHA_Pos) /*!< SSPn CR0: CPHA Mask */ +#define SSPn_CR0_SCR_Pos 8 /*!< SSPn CR0: SCR Position */ +#define SSPn_CR0_SCR_Msk (0x000000ffUL << SSPn_CR0_SCR_Pos) /*!< SSPn CR0: SCR Mask */ + +/* ---------------------------------- SSPn_CR1 ---------------------------------- */ +#define SSPn_CR1_LBM_Pos 0 /*!< SSPn CR1: LBM Position */ +#define SSPn_CR1_LBM_Msk (0x01UL << SSPn_CR1_LBM_Pos) /*!< SSPn CR1: LBM Mask */ +#define SSPn_CR1_SSE_Pos 1 /*!< SSPn CR1: SSE Position */ +#define SSPn_CR1_SSE_Msk (0x01UL << SSPn_CR1_SSE_Pos) /*!< SSPn CR1: SSE Mask */ +#define SSPn_CR1_MS_Pos 2 /*!< SSPn CR1: MS Position */ +#define SSPn_CR1_MS_Msk (0x01UL << SSPn_CR1_MS_Pos) /*!< SSPn CR1: MS Mask */ +#define SSPn_CR1_SOD_Pos 3 /*!< SSPn CR1: SOD Position */ +#define SSPn_CR1_SOD_Msk (0x01UL << SSPn_CR1_SOD_Pos) /*!< SSPn CR1: SOD Mask */ + +/* ----------------------------------- SSPn_DR ---------------------------------- */ +#define SSPn_DR_DATA_Pos 0 /*!< SSPn DR: DATA Position */ +#define SSPn_DR_DATA_Msk (0x0000ffffUL << SSPn_DR_DATA_Pos) /*!< SSPn DR: DATA Mask */ + +/* ----------------------------------- SSPn_SR ---------------------------------- */ +#define SSPn_SR_TFE_Pos 0 /*!< SSPn SR: TFE Position */ +#define SSPn_SR_TFE_Msk (0x01UL << SSPn_SR_TFE_Pos) /*!< SSPn SR: TFE Mask */ +#define SSPn_SR_TNF_Pos 1 /*!< SSPn SR: TNF Position */ +#define SSPn_SR_TNF_Msk (0x01UL << SSPn_SR_TNF_Pos) /*!< SSPn SR: TNF Mask */ +#define SSPn_SR_RNE_Pos 2 /*!< SSPn SR: RNE Position */ +#define SSPn_SR_RNE_Msk (0x01UL << SSPn_SR_RNE_Pos) /*!< SSPn SR: RNE Mask */ +#define SSPn_SR_RFF_Pos 3 /*!< SSPn SR: RFF Position */ +#define SSPn_SR_RFF_Msk (0x01UL << SSPn_SR_RFF_Pos) /*!< SSPn SR: RFF Mask */ +#define SSPn_SR_BSY_Pos 4 /*!< SSPn SR: BSY Position */ +#define SSPn_SR_BSY_Msk (0x01UL << SSPn_SR_BSY_Pos) /*!< SSPn SR: BSY Mask */ + +/* ---------------------------------- SSPn_CPSR --------------------------------- */ +#define SSPn_CPSR_CPSDVSR_Pos 0 /*!< SSPn CPSR: CPSDVSR Position */ +#define SSPn_CPSR_CPSDVSR_Msk (0x000000ffUL << SSPn_CPSR_CPSDVSR_Pos) /*!< SSPn CPSR: CPSDVSR Mask */ + +/* ---------------------------------- SSPn_IMSC --------------------------------- */ +#define SSPn_IMSC_RORIM_Pos 0 /*!< SSPn IMSC: RORIM Position */ +#define SSPn_IMSC_RORIM_Msk (0x01UL << SSPn_IMSC_RORIM_Pos) /*!< SSPn IMSC: RORIM Mask */ +#define SSPn_IMSC_RTIM_Pos 1 /*!< SSPn IMSC: RTIM Position */ +#define SSPn_IMSC_RTIM_Msk (0x01UL << SSPn_IMSC_RTIM_Pos) /*!< SSPn IMSC: RTIM Mask */ +#define SSPn_IMSC_RXIM_Pos 2 /*!< SSPn IMSC: RXIM Position */ +#define SSPn_IMSC_RXIM_Msk (0x01UL << SSPn_IMSC_RXIM_Pos) /*!< SSPn IMSC: RXIM Mask */ +#define SSPn_IMSC_TXIM_Pos 3 /*!< SSPn IMSC: TXIM Position */ +#define SSPn_IMSC_TXIM_Msk (0x01UL << SSPn_IMSC_TXIM_Pos) /*!< SSPn IMSC: TXIM Mask */ + +/* ---------------------------------- SSPn_RIS ---------------------------------- */ +#define SSPn_RIS_RORRIS_Pos 0 /*!< SSPn RIS: RORRIS Position */ +#define SSPn_RIS_RORRIS_Msk (0x01UL << SSPn_RIS_RORRIS_Pos) /*!< SSPn RIS: RORRIS Mask */ +#define SSPn_RIS_RTRIS_Pos 1 /*!< SSPn RIS: RTRIS Position */ +#define SSPn_RIS_RTRIS_Msk (0x01UL << SSPn_RIS_RTRIS_Pos) /*!< SSPn RIS: RTRIS Mask */ +#define SSPn_RIS_RXRIS_Pos 2 /*!< SSPn RIS: RXRIS Position */ +#define SSPn_RIS_RXRIS_Msk (0x01UL << SSPn_RIS_RXRIS_Pos) /*!< SSPn RIS: RXRIS Mask */ +#define SSPn_RIS_TXRIS_Pos 3 /*!< SSPn RIS: TXRIS Position */ +#define SSPn_RIS_TXRIS_Msk (0x01UL << SSPn_RIS_TXRIS_Pos) /*!< SSPn RIS: TXRIS Mask */ + +/* ---------------------------------- SSPn_MIS ---------------------------------- */ +#define SSPn_MIS_RORMIS_Pos 0 /*!< SSPn MIS: RORMIS Position */ +#define SSPn_MIS_RORMIS_Msk (0x01UL << SSPn_MIS_RORMIS_Pos) /*!< SSPn MIS: RORMIS Mask */ +#define SSPn_MIS_RTMIS_Pos 1 /*!< SSPn MIS: RTMIS Position */ +#define SSPn_MIS_RTMIS_Msk (0x01UL << SSPn_MIS_RTMIS_Pos) /*!< SSPn MIS: RTMIS Mask */ +#define SSPn_MIS_RXMIS_Pos 2 /*!< SSPn MIS: RXMIS Position */ +#define SSPn_MIS_RXMIS_Msk (0x01UL << SSPn_MIS_RXMIS_Pos) /*!< SSPn MIS: RXMIS Mask */ +#define SSPn_MIS_TXMIS_Pos 3 /*!< SSPn MIS: TXMIS Position */ +#define SSPn_MIS_TXMIS_Msk (0x01UL << SSPn_MIS_TXMIS_Pos) /*!< SSPn MIS: TXMIS Mask */ + +/* ---------------------------------- SSPn_ICR ---------------------------------- */ +#define SSPn_ICR_RORIC_Pos 0 /*!< SSPn ICR: RORIC Position */ +#define SSPn_ICR_RORIC_Msk (0x01UL << SSPn_ICR_RORIC_Pos) /*!< SSPn ICR: RORIC Mask */ +#define SSPn_ICR_RTIC_Pos 1 /*!< SSPn ICR: RTIC Position */ +#define SSPn_ICR_RTIC_Msk (0x01UL << SSPn_ICR_RTIC_Pos) /*!< SSPn ICR: RTIC Mask */ + +/* --------------------------------- SSPn_DMACR --------------------------------- */ +#define SSPn_DMACR_RXDMAE_Pos 0 /*!< SSPn DMACR: RXDMAE Position */ +#define SSPn_DMACR_RXDMAE_Msk (0x01UL << SSPn_DMACR_RXDMAE_Pos) /*!< SSPn DMACR: RXDMAE Mask */ +#define SSPn_DMACR_TXDMAE_Pos 1 /*!< SSPn DMACR: TXDMAE Position */ +#define SSPn_DMACR_TXDMAE_Msk (0x01UL << SSPn_DMACR_TXDMAE_Pos) /*!< SSPn DMACR: TXDMAE Mask */ + + +/* ================================================================================ */ +/* ================ struct 'SSP0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- SSP0_CR0 ---------------------------------- */ +#define SSP0_CR0_DSS_Pos 0 /*!< SSP0 CR0: DSS Position */ +#define SSP0_CR0_DSS_Msk (0x0fUL << SSP0_CR0_DSS_Pos) /*!< SSP0 CR0: DSS Mask */ +#define SSP0_CR0_FRF_Pos 4 /*!< SSP0 CR0: FRF Position */ +#define SSP0_CR0_FRF_Msk (0x03UL << SSP0_CR0_FRF_Pos) /*!< SSP0 CR0: FRF Mask */ +#define SSP0_CR0_CPOL_Pos 6 /*!< SSP0 CR0: CPOL Position */ +#define SSP0_CR0_CPOL_Msk (0x01UL << SSP0_CR0_CPOL_Pos) /*!< SSP0 CR0: CPOL Mask */ +#define SSP0_CR0_CPHA_Pos 7 /*!< SSP0 CR0: CPHA Position */ +#define SSP0_CR0_CPHA_Msk (0x01UL << SSP0_CR0_CPHA_Pos) /*!< SSP0 CR0: CPHA Mask */ +#define SSP0_CR0_SCR_Pos 8 /*!< SSP0 CR0: SCR Position */ +#define SSP0_CR0_SCR_Msk (0x000000ffUL << SSP0_CR0_SCR_Pos) /*!< SSP0 CR0: SCR Mask */ + +/* ---------------------------------- SSP0_CR1 ---------------------------------- */ +#define SSP0_CR1_LBM_Pos 0 /*!< SSP0 CR1: LBM Position */ +#define SSP0_CR1_LBM_Msk (0x01UL << SSP0_CR1_LBM_Pos) /*!< SSP0 CR1: LBM Mask */ +#define SSP0_CR1_SSE_Pos 1 /*!< SSP0 CR1: SSE Position */ +#define SSP0_CR1_SSE_Msk (0x01UL << SSP0_CR1_SSE_Pos) /*!< SSP0 CR1: SSE Mask */ +#define SSP0_CR1_MS_Pos 2 /*!< SSP0 CR1: MS Position */ +#define SSP0_CR1_MS_Msk (0x01UL << SSP0_CR1_MS_Pos) /*!< SSP0 CR1: MS Mask */ +#define SSP0_CR1_SOD_Pos 3 /*!< SSP0 CR1: SOD Position */ +#define SSP0_CR1_SOD_Msk (0x01UL << SSP0_CR1_SOD_Pos) /*!< SSP0 CR1: SOD Mask */ + +/* ----------------------------------- SSP0_DR ---------------------------------- */ +#define SSP0_DR_DATA_Pos 0 /*!< SSP0 DR: DATA Position */ +#define SSP0_DR_DATA_Msk (0x0000ffffUL << SSP0_DR_DATA_Pos) /*!< SSP0 DR: DATA Mask */ + +/* ----------------------------------- SSP0_SR ---------------------------------- */ +#define SSP0_SR_TFE_Pos 0 /*!< SSP0 SR: TFE Position */ +#define SSP0_SR_TFE_Msk (0x01UL << SSP0_SR_TFE_Pos) /*!< SSP0 SR: TFE Mask */ +#define SSP0_SR_TNF_Pos 1 /*!< SSP0 SR: TNF Position */ +#define SSP0_SR_TNF_Msk (0x01UL << SSP0_SR_TNF_Pos) /*!< SSP0 SR: TNF Mask */ +#define SSP0_SR_RNE_Pos 2 /*!< SSP0 SR: RNE Position */ +#define SSP0_SR_RNE_Msk (0x01UL << SSP0_SR_RNE_Pos) /*!< SSP0 SR: RNE Mask */ +#define SSP0_SR_RFF_Pos 3 /*!< SSP0 SR: RFF Position */ +#define SSP0_SR_RFF_Msk (0x01UL << SSP0_SR_RFF_Pos) /*!< SSP0 SR: RFF Mask */ +#define SSP0_SR_BSY_Pos 4 /*!< SSP0 SR: BSY Position */ +#define SSP0_SR_BSY_Msk (0x01UL << SSP0_SR_BSY_Pos) /*!< SSP0 SR: BSY Mask */ + +/* ---------------------------------- SSP0_CPSR --------------------------------- */ +#define SSP0_CPSR_CPSDVSR_Pos 0 /*!< SSP0 CPSR: CPSDVSR Position */ +#define SSP0_CPSR_CPSDVSR_Msk (0x000000ffUL << SSP0_CPSR_CPSDVSR_Pos) /*!< SSP0 CPSR: CPSDVSR Mask */ + +/* ---------------------------------- SSP0_IMSC --------------------------------- */ +#define SSP0_IMSC_RORIM_Pos 0 /*!< SSP0 IMSC: RORIM Position */ +#define SSP0_IMSC_RORIM_Msk (0x01UL << SSP0_IMSC_RORIM_Pos) /*!< SSP0 IMSC: RORIM Mask */ +#define SSP0_IMSC_RTIM_Pos 1 /*!< SSP0 IMSC: RTIM Position */ +#define SSP0_IMSC_RTIM_Msk (0x01UL << SSP0_IMSC_RTIM_Pos) /*!< SSP0 IMSC: RTIM Mask */ +#define SSP0_IMSC_RXIM_Pos 2 /*!< SSP0 IMSC: RXIM Position */ +#define SSP0_IMSC_RXIM_Msk (0x01UL << SSP0_IMSC_RXIM_Pos) /*!< SSP0 IMSC: RXIM Mask */ +#define SSP0_IMSC_TXIM_Pos 3 /*!< SSP0 IMSC: TXIM Position */ +#define SSP0_IMSC_TXIM_Msk (0x01UL << SSP0_IMSC_TXIM_Pos) /*!< SSP0 IMSC: TXIM Mask */ + +/* ---------------------------------- SSP0_RIS ---------------------------------- */ +#define SSP0_RIS_RORRIS_Pos 0 /*!< SSP0 RIS: RORRIS Position */ +#define SSP0_RIS_RORRIS_Msk (0x01UL << SSP0_RIS_RORRIS_Pos) /*!< SSP0 RIS: RORRIS Mask */ +#define SSP0_RIS_RTRIS_Pos 1 /*!< SSP0 RIS: RTRIS Position */ +#define SSP0_RIS_RTRIS_Msk (0x01UL << SSP0_RIS_RTRIS_Pos) /*!< SSP0 RIS: RTRIS Mask */ +#define SSP0_RIS_RXRIS_Pos 2 /*!< SSP0 RIS: RXRIS Position */ +#define SSP0_RIS_RXRIS_Msk (0x01UL << SSP0_RIS_RXRIS_Pos) /*!< SSP0 RIS: RXRIS Mask */ +#define SSP0_RIS_TXRIS_Pos 3 /*!< SSP0 RIS: TXRIS Position */ +#define SSP0_RIS_TXRIS_Msk (0x01UL << SSP0_RIS_TXRIS_Pos) /*!< SSP0 RIS: TXRIS Mask */ + +/* ---------------------------------- SSP0_MIS ---------------------------------- */ +#define SSP0_MIS_RORMIS_Pos 0 /*!< SSP0 MIS: RORMIS Position */ +#define SSP0_MIS_RORMIS_Msk (0x01UL << SSP0_MIS_RORMIS_Pos) /*!< SSP0 MIS: RORMIS Mask */ +#define SSP0_MIS_RTMIS_Pos 1 /*!< SSP0 MIS: RTMIS Position */ +#define SSP0_MIS_RTMIS_Msk (0x01UL << SSP0_MIS_RTMIS_Pos) /*!< SSP0 MIS: RTMIS Mask */ +#define SSP0_MIS_RXMIS_Pos 2 /*!< SSP0 MIS: RXMIS Position */ +#define SSP0_MIS_RXMIS_Msk (0x01UL << SSP0_MIS_RXMIS_Pos) /*!< SSP0 MIS: RXMIS Mask */ +#define SSP0_MIS_TXMIS_Pos 3 /*!< SSP0 MIS: TXMIS Position */ +#define SSP0_MIS_TXMIS_Msk (0x01UL << SSP0_MIS_TXMIS_Pos) /*!< SSP0 MIS: TXMIS Mask */ + +/* ---------------------------------- SSP0_ICR ---------------------------------- */ +#define SSP0_ICR_RORIC_Pos 0 /*!< SSP0 ICR: RORIC Position */ +#define SSP0_ICR_RORIC_Msk (0x01UL << SSP0_ICR_RORIC_Pos) /*!< SSP0 ICR: RORIC Mask */ +#define SSP0_ICR_RTIC_Pos 1 /*!< SSP0 ICR: RTIC Position */ +#define SSP0_ICR_RTIC_Msk (0x01UL << SSP0_ICR_RTIC_Pos) /*!< SSP0 ICR: RTIC Mask */ + +/* --------------------------------- SSP0_DMACR --------------------------------- */ +#define SSP0_DMACR_RXDMAE_Pos 0 /*!< SSP0 DMACR: RXDMAE Position */ +#define SSP0_DMACR_RXDMAE_Msk (0x01UL << SSP0_DMACR_RXDMAE_Pos) /*!< SSP0 DMACR: RXDMAE Mask */ +#define SSP0_DMACR_TXDMAE_Pos 1 /*!< SSP0 DMACR: TXDMAE Position */ +#define SSP0_DMACR_TXDMAE_Msk (0x01UL << SSP0_DMACR_TXDMAE_Pos) /*!< SSP0 DMACR: TXDMAE Mask */ + + +/* ================================================================================ */ +/* ================ struct 'SSP1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- SSP1_CR0 ---------------------------------- */ +#define SSP1_CR0_DSS_Pos 0 /*!< SSP1 CR0: DSS Position */ +#define SSP1_CR0_DSS_Msk (0x0fUL << SSP1_CR0_DSS_Pos) /*!< SSP1 CR0: DSS Mask */ +#define SSP1_CR0_FRF_Pos 4 /*!< SSP1 CR0: FRF Position */ +#define SSP1_CR0_FRF_Msk (0x03UL << SSP1_CR0_FRF_Pos) /*!< SSP1 CR0: FRF Mask */ +#define SSP1_CR0_CPOL_Pos 6 /*!< SSP1 CR0: CPOL Position */ +#define SSP1_CR0_CPOL_Msk (0x01UL << SSP1_CR0_CPOL_Pos) /*!< SSP1 CR0: CPOL Mask */ +#define SSP1_CR0_CPHA_Pos 7 /*!< SSP1 CR0: CPHA Position */ +#define SSP1_CR0_CPHA_Msk (0x01UL << SSP1_CR0_CPHA_Pos) /*!< SSP1 CR0: CPHA Mask */ +#define SSP1_CR0_SCR_Pos 8 /*!< SSP1 CR0: SCR Position */ +#define SSP1_CR0_SCR_Msk (0x000000ffUL << SSP1_CR0_SCR_Pos) /*!< SSP1 CR0: SCR Mask */ + +/* ---------------------------------- SSP1_CR1 ---------------------------------- */ +#define SSP1_CR1_LBM_Pos 0 /*!< SSP1 CR1: LBM Position */ +#define SSP1_CR1_LBM_Msk (0x01UL << SSP1_CR1_LBM_Pos) /*!< SSP1 CR1: LBM Mask */ +#define SSP1_CR1_SSE_Pos 1 /*!< SSP1 CR1: SSE Position */ +#define SSP1_CR1_SSE_Msk (0x01UL << SSP1_CR1_SSE_Pos) /*!< SSP1 CR1: SSE Mask */ +#define SSP1_CR1_MS_Pos 2 /*!< SSP1 CR1: MS Position */ +#define SSP1_CR1_MS_Msk (0x01UL << SSP1_CR1_MS_Pos) /*!< SSP1 CR1: MS Mask */ +#define SSP1_CR1_SOD_Pos 3 /*!< SSP1 CR1: SOD Position */ +#define SSP1_CR1_SOD_Msk (0x01UL << SSP1_CR1_SOD_Pos) /*!< SSP1 CR1: SOD Mask */ + +/* ----------------------------------- SSP1_DR ---------------------------------- */ +#define SSP1_DR_DATA_Pos 0 /*!< SSP1 DR: DATA Position */ +#define SSP1_DR_DATA_Msk (0x0000ffffUL << SSP1_DR_DATA_Pos) /*!< SSP1 DR: DATA Mask */ + +/* ----------------------------------- SSP1_SR ---------------------------------- */ +#define SSP1_SR_TFE_Pos 0 /*!< SSP1 SR: TFE Position */ +#define SSP1_SR_TFE_Msk (0x01UL << SSP1_SR_TFE_Pos) /*!< SSP1 SR: TFE Mask */ +#define SSP1_SR_TNF_Pos 1 /*!< SSP1 SR: TNF Position */ +#define SSP1_SR_TNF_Msk (0x01UL << SSP1_SR_TNF_Pos) /*!< SSP1 SR: TNF Mask */ +#define SSP1_SR_RNE_Pos 2 /*!< SSP1 SR: RNE Position */ +#define SSP1_SR_RNE_Msk (0x01UL << SSP1_SR_RNE_Pos) /*!< SSP1 SR: RNE Mask */ +#define SSP1_SR_RFF_Pos 3 /*!< SSP1 SR: RFF Position */ +#define SSP1_SR_RFF_Msk (0x01UL << SSP1_SR_RFF_Pos) /*!< SSP1 SR: RFF Mask */ +#define SSP1_SR_BSY_Pos 4 /*!< SSP1 SR: BSY Position */ +#define SSP1_SR_BSY_Msk (0x01UL << SSP1_SR_BSY_Pos) /*!< SSP1 SR: BSY Mask */ + +/* ---------------------------------- SSP1_CPSR --------------------------------- */ +#define SSP1_CPSR_CPSDVSR_Pos 0 /*!< SSP1 CPSR: CPSDVSR Position */ +#define SSP1_CPSR_CPSDVSR_Msk (0x000000ffUL << SSP1_CPSR_CPSDVSR_Pos) /*!< SSP1 CPSR: CPSDVSR Mask */ + +/* ---------------------------------- SSP1_IMSC --------------------------------- */ +#define SSP1_IMSC_RORIM_Pos 0 /*!< SSP1 IMSC: RORIM Position */ +#define SSP1_IMSC_RORIM_Msk (0x01UL << SSP1_IMSC_RORIM_Pos) /*!< SSP1 IMSC: RORIM Mask */ +#define SSP1_IMSC_RTIM_Pos 1 /*!< SSP1 IMSC: RTIM Position */ +#define SSP1_IMSC_RTIM_Msk (0x01UL << SSP1_IMSC_RTIM_Pos) /*!< SSP1 IMSC: RTIM Mask */ +#define SSP1_IMSC_RXIM_Pos 2 /*!< SSP1 IMSC: RXIM Position */ +#define SSP1_IMSC_RXIM_Msk (0x01UL << SSP1_IMSC_RXIM_Pos) /*!< SSP1 IMSC: RXIM Mask */ +#define SSP1_IMSC_TXIM_Pos 3 /*!< SSP1 IMSC: TXIM Position */ +#define SSP1_IMSC_TXIM_Msk (0x01UL << SSP1_IMSC_TXIM_Pos) /*!< SSP1 IMSC: TXIM Mask */ + +/* ---------------------------------- SSP1_RIS ---------------------------------- */ +#define SSP1_RIS_RORRIS_Pos 0 /*!< SSP1 RIS: RORRIS Position */ +#define SSP1_RIS_RORRIS_Msk (0x01UL << SSP1_RIS_RORRIS_Pos) /*!< SSP1 RIS: RORRIS Mask */ +#define SSP1_RIS_RTRIS_Pos 1 /*!< SSP1 RIS: RTRIS Position */ +#define SSP1_RIS_RTRIS_Msk (0x01UL << SSP1_RIS_RTRIS_Pos) /*!< SSP1 RIS: RTRIS Mask */ +#define SSP1_RIS_RXRIS_Pos 2 /*!< SSP1 RIS: RXRIS Position */ +#define SSP1_RIS_RXRIS_Msk (0x01UL << SSP1_RIS_RXRIS_Pos) /*!< SSP1 RIS: RXRIS Mask */ +#define SSP1_RIS_TXRIS_Pos 3 /*!< SSP1 RIS: TXRIS Position */ +#define SSP1_RIS_TXRIS_Msk (0x01UL << SSP1_RIS_TXRIS_Pos) /*!< SSP1 RIS: TXRIS Mask */ + +/* ---------------------------------- SSP1_MIS ---------------------------------- */ +#define SSP1_MIS_RORMIS_Pos 0 /*!< SSP1 MIS: RORMIS Position */ +#define SSP1_MIS_RORMIS_Msk (0x01UL << SSP1_MIS_RORMIS_Pos) /*!< SSP1 MIS: RORMIS Mask */ +#define SSP1_MIS_RTMIS_Pos 1 /*!< SSP1 MIS: RTMIS Position */ +#define SSP1_MIS_RTMIS_Msk (0x01UL << SSP1_MIS_RTMIS_Pos) /*!< SSP1 MIS: RTMIS Mask */ +#define SSP1_MIS_RXMIS_Pos 2 /*!< SSP1 MIS: RXMIS Position */ +#define SSP1_MIS_RXMIS_Msk (0x01UL << SSP1_MIS_RXMIS_Pos) /*!< SSP1 MIS: RXMIS Mask */ +#define SSP1_MIS_TXMIS_Pos 3 /*!< SSP1 MIS: TXMIS Position */ +#define SSP1_MIS_TXMIS_Msk (0x01UL << SSP1_MIS_TXMIS_Pos) /*!< SSP1 MIS: TXMIS Mask */ + +/* ---------------------------------- SSP1_ICR ---------------------------------- */ +#define SSP1_ICR_RORIC_Pos 0 /*!< SSP1 ICR: RORIC Position */ +#define SSP1_ICR_RORIC_Msk (0x01UL << SSP1_ICR_RORIC_Pos) /*!< SSP1 ICR: RORIC Mask */ +#define SSP1_ICR_RTIC_Pos 1 /*!< SSP1 ICR: RTIC Position */ +#define SSP1_ICR_RTIC_Msk (0x01UL << SSP1_ICR_RTIC_Pos) /*!< SSP1 ICR: RTIC Mask */ + +/* --------------------------------- SSP1_DMACR --------------------------------- */ +#define SSP1_DMACR_RXDMAE_Pos 0 /*!< SSP1 DMACR: RXDMAE Position */ +#define SSP1_DMACR_RXDMAE_Msk (0x01UL << SSP1_DMACR_RXDMAE_Pos) /*!< SSP1 DMACR: RXDMAE Mask */ +#define SSP1_DMACR_TXDMAE_Pos 1 /*!< SSP1 DMACR: TXDMAE Position */ +#define SSP1_DMACR_TXDMAE_Msk (0x01UL << SSP1_DMACR_TXDMAE_Pos) /*!< SSP1 DMACR: TXDMAE Mask */ + + +/* ================================================================================ */ +/* ================ Group 'TIMERn' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- TIMERn_IR --------------------------------- */ +#define TIMERn_IR_MR0INT_Pos 0 /*!< TIMERn IR: MR0INT Position */ +#define TIMERn_IR_MR0INT_Msk (0x01UL << TIMERn_IR_MR0INT_Pos) /*!< TIMERn IR: MR0INT Mask */ +#define TIMERn_IR_MR1INT_Pos 1 /*!< TIMERn IR: MR1INT Position */ +#define TIMERn_IR_MR1INT_Msk (0x01UL << TIMERn_IR_MR1INT_Pos) /*!< TIMERn IR: MR1INT Mask */ +#define TIMERn_IR_MR2INT_Pos 2 /*!< TIMERn IR: MR2INT Position */ +#define TIMERn_IR_MR2INT_Msk (0x01UL << TIMERn_IR_MR2INT_Pos) /*!< TIMERn IR: MR2INT Mask */ +#define TIMERn_IR_MR3INT_Pos 3 /*!< TIMERn IR: MR3INT Position */ +#define TIMERn_IR_MR3INT_Msk (0x01UL << TIMERn_IR_MR3INT_Pos) /*!< TIMERn IR: MR3INT Mask */ +#define TIMERn_IR_CR0INT_Pos 4 /*!< TIMERn IR: CR0INT Position */ +#define TIMERn_IR_CR0INT_Msk (0x01UL << TIMERn_IR_CR0INT_Pos) /*!< TIMERn IR: CR0INT Mask */ +#define TIMERn_IR_CR1INT_Pos 5 /*!< TIMERn IR: CR1INT Position */ +#define TIMERn_IR_CR1INT_Msk (0x01UL << TIMERn_IR_CR1INT_Pos) /*!< TIMERn IR: CR1INT Mask */ +#define TIMERn_IR_CR2INT_Pos 6 /*!< TIMERn IR: CR2INT Position */ +#define TIMERn_IR_CR2INT_Msk (0x01UL << TIMERn_IR_CR2INT_Pos) /*!< TIMERn IR: CR2INT Mask */ +#define TIMERn_IR_CR3INT_Pos 7 /*!< TIMERn IR: CR3INT Position */ +#define TIMERn_IR_CR3INT_Msk (0x01UL << TIMERn_IR_CR3INT_Pos) /*!< TIMERn IR: CR3INT Mask */ + +/* --------------------------------- TIMERn_TCR --------------------------------- */ +#define TIMERn_TCR_CEN_Pos 0 /*!< TIMERn TCR: CEN Position */ +#define TIMERn_TCR_CEN_Msk (0x01UL << TIMERn_TCR_CEN_Pos) /*!< TIMERn TCR: CEN Mask */ +#define TIMERn_TCR_CRST_Pos 1 /*!< TIMERn TCR: CRST Position */ +#define TIMERn_TCR_CRST_Msk (0x01UL << TIMERn_TCR_CRST_Pos) /*!< TIMERn TCR: CRST Mask */ + +/* ---------------------------------- TIMERn_TC --------------------------------- */ +#define TIMERn_TC_TC_Pos 0 /*!< TIMERn TC: TC Position */ +#define TIMERn_TC_TC_Msk (0xffffffffUL << TIMERn_TC_TC_Pos) /*!< TIMERn TC: TC Mask */ + +/* ---------------------------------- TIMERn_PR --------------------------------- */ +#define TIMERn_PR_PM_Pos 0 /*!< TIMERn PR: PM Position */ +#define TIMERn_PR_PM_Msk (0xffffffffUL << TIMERn_PR_PM_Pos) /*!< TIMERn PR: PM Mask */ + +/* ---------------------------------- TIMERn_PC --------------------------------- */ +#define TIMERn_PC_PC_Pos 0 /*!< TIMERn PC: PC Position */ +#define TIMERn_PC_PC_Msk (0xffffffffUL << TIMERn_PC_PC_Pos) /*!< TIMERn PC: PC Mask */ + +/* --------------------------------- TIMERn_MCR --------------------------------- */ +#define TIMERn_MCR_MR0I_Pos 0 /*!< TIMERn MCR: MR0I Position */ +#define TIMERn_MCR_MR0I_Msk (0x01UL << TIMERn_MCR_MR0I_Pos) /*!< TIMERn MCR: MR0I Mask */ +#define TIMERn_MCR_MR0R_Pos 1 /*!< TIMERn MCR: MR0R Position */ +#define TIMERn_MCR_MR0R_Msk (0x01UL << TIMERn_MCR_MR0R_Pos) /*!< TIMERn MCR: MR0R Mask */ +#define TIMERn_MCR_MR0S_Pos 2 /*!< TIMERn MCR: MR0S Position */ +#define TIMERn_MCR_MR0S_Msk (0x01UL << TIMERn_MCR_MR0S_Pos) /*!< TIMERn MCR: MR0S Mask */ +#define TIMERn_MCR_MR1I_Pos 3 /*!< TIMERn MCR: MR1I Position */ +#define TIMERn_MCR_MR1I_Msk (0x01UL << TIMERn_MCR_MR1I_Pos) /*!< TIMERn MCR: MR1I Mask */ +#define TIMERn_MCR_MR1R_Pos 4 /*!< TIMERn MCR: MR1R Position */ +#define TIMERn_MCR_MR1R_Msk (0x01UL << TIMERn_MCR_MR1R_Pos) /*!< TIMERn MCR: MR1R Mask */ +#define TIMERn_MCR_MR1S_Pos 5 /*!< TIMERn MCR: MR1S Position */ +#define TIMERn_MCR_MR1S_Msk (0x01UL << TIMERn_MCR_MR1S_Pos) /*!< TIMERn MCR: MR1S Mask */ +#define TIMERn_MCR_MR2I_Pos 6 /*!< TIMERn MCR: MR2I Position */ +#define TIMERn_MCR_MR2I_Msk (0x01UL << TIMERn_MCR_MR2I_Pos) /*!< TIMERn MCR: MR2I Mask */ +#define TIMERn_MCR_MR2R_Pos 7 /*!< TIMERn MCR: MR2R Position */ +#define TIMERn_MCR_MR2R_Msk (0x01UL << TIMERn_MCR_MR2R_Pos) /*!< TIMERn MCR: MR2R Mask */ +#define TIMERn_MCR_MR2S_Pos 8 /*!< TIMERn MCR: MR2S Position */ +#define TIMERn_MCR_MR2S_Msk (0x01UL << TIMERn_MCR_MR2S_Pos) /*!< TIMERn MCR: MR2S Mask */ +#define TIMERn_MCR_MR3I_Pos 9 /*!< TIMERn MCR: MR3I Position */ +#define TIMERn_MCR_MR3I_Msk (0x01UL << TIMERn_MCR_MR3I_Pos) /*!< TIMERn MCR: MR3I Mask */ +#define TIMERn_MCR_MR3R_Pos 10 /*!< TIMERn MCR: MR3R Position */ +#define TIMERn_MCR_MR3R_Msk (0x01UL << TIMERn_MCR_MR3R_Pos) /*!< TIMERn MCR: MR3R Mask */ +#define TIMERn_MCR_MR3S_Pos 11 /*!< TIMERn MCR: MR3S Position */ +#define TIMERn_MCR_MR3S_Msk (0x01UL << TIMERn_MCR_MR3S_Pos) /*!< TIMERn MCR: MR3S Mask */ + +/* --------------------------------- TIMERn_MR0 --------------------------------- */ +#define TIMERn_MR0_MATCH_Pos 0 /*!< TIMERn MR0: MATCH Position */ +#define TIMERn_MR0_MATCH_Msk (0xffffffffUL << TIMERn_MR0_MATCH_Pos) /*!< TIMERn MR0: MATCH Mask */ + +/* --------------------------------- TIMERn_MR1 --------------------------------- */ +#define TIMERn_MR1_MATCH_Pos 0 /*!< TIMERn MR1: MATCH Position */ +#define TIMERn_MR1_MATCH_Msk (0xffffffffUL << TIMERn_MR1_MATCH_Pos) /*!< TIMERn MR1: MATCH Mask */ + +/* --------------------------------- TIMERn_MR2 --------------------------------- */ +#define TIMERn_MR2_MATCH_Pos 0 /*!< TIMERn MR2: MATCH Position */ +#define TIMERn_MR2_MATCH_Msk (0xffffffffUL << TIMERn_MR2_MATCH_Pos) /*!< TIMERn MR2: MATCH Mask */ + +/* --------------------------------- TIMERn_MR3 --------------------------------- */ +#define TIMERn_MR3_MATCH_Pos 0 /*!< TIMERn MR3: MATCH Position */ +#define TIMERn_MR3_MATCH_Msk (0xffffffffUL << TIMERn_MR3_MATCH_Pos) /*!< TIMERn MR3: MATCH Mask */ + +/* --------------------------------- TIMERn_CCR --------------------------------- */ +#define TIMERn_CCR_CAP0RE_Pos 0 /*!< TIMERn CCR: CAP0RE Position */ +#define TIMERn_CCR_CAP0RE_Msk (0x01UL << TIMERn_CCR_CAP0RE_Pos) /*!< TIMERn CCR: CAP0RE Mask */ +#define TIMERn_CCR_CAP0FE_Pos 1 /*!< TIMERn CCR: CAP0FE Position */ +#define TIMERn_CCR_CAP0FE_Msk (0x01UL << TIMERn_CCR_CAP0FE_Pos) /*!< TIMERn CCR: CAP0FE Mask */ +#define TIMERn_CCR_CAP0I_Pos 2 /*!< TIMERn CCR: CAP0I Position */ +#define TIMERn_CCR_CAP0I_Msk (0x01UL << TIMERn_CCR_CAP0I_Pos) /*!< TIMERn CCR: CAP0I Mask */ +#define TIMERn_CCR_CAP1RE_Pos 3 /*!< TIMERn CCR: CAP1RE Position */ +#define TIMERn_CCR_CAP1RE_Msk (0x01UL << TIMERn_CCR_CAP1RE_Pos) /*!< TIMERn CCR: CAP1RE Mask */ +#define TIMERn_CCR_CAP1FE_Pos 4 /*!< TIMERn CCR: CAP1FE Position */ +#define TIMERn_CCR_CAP1FE_Msk (0x01UL << TIMERn_CCR_CAP1FE_Pos) /*!< TIMERn CCR: CAP1FE Mask */ +#define TIMERn_CCR_CAP1I_Pos 5 /*!< TIMERn CCR: CAP1I Position */ +#define TIMERn_CCR_CAP1I_Msk (0x01UL << TIMERn_CCR_CAP1I_Pos) /*!< TIMERn CCR: CAP1I Mask */ +#define TIMERn_CCR_CAP2RE_Pos 6 /*!< TIMERn CCR: CAP2RE Position */ +#define TIMERn_CCR_CAP2RE_Msk (0x01UL << TIMERn_CCR_CAP2RE_Pos) /*!< TIMERn CCR: CAP2RE Mask */ +#define TIMERn_CCR_CAP2FE_Pos 7 /*!< TIMERn CCR: CAP2FE Position */ +#define TIMERn_CCR_CAP2FE_Msk (0x01UL << TIMERn_CCR_CAP2FE_Pos) /*!< TIMERn CCR: CAP2FE Mask */ +#define TIMERn_CCR_CAP2I_Pos 8 /*!< TIMERn CCR: CAP2I Position */ +#define TIMERn_CCR_CAP2I_Msk (0x01UL << TIMERn_CCR_CAP2I_Pos) /*!< TIMERn CCR: CAP2I Mask */ +#define TIMERn_CCR_CAP3RE_Pos 9 /*!< TIMERn CCR: CAP3RE Position */ +#define TIMERn_CCR_CAP3RE_Msk (0x01UL << TIMERn_CCR_CAP3RE_Pos) /*!< TIMERn CCR: CAP3RE Mask */ +#define TIMERn_CCR_CAP3FE_Pos 10 /*!< TIMERn CCR: CAP3FE Position */ +#define TIMERn_CCR_CAP3FE_Msk (0x01UL << TIMERn_CCR_CAP3FE_Pos) /*!< TIMERn CCR: CAP3FE Mask */ +#define TIMERn_CCR_CAP3I_Pos 11 /*!< TIMERn CCR: CAP3I Position */ +#define TIMERn_CCR_CAP3I_Msk (0x01UL << TIMERn_CCR_CAP3I_Pos) /*!< TIMERn CCR: CAP3I Mask */ + +/* --------------------------------- TIMERn_CR0 --------------------------------- */ +#define TIMERn_CR0_CAP_Pos 0 /*!< TIMERn CR0: CAP Position */ +#define TIMERn_CR0_CAP_Msk (0xffffffffUL << TIMERn_CR0_CAP_Pos) /*!< TIMERn CR0: CAP Mask */ + +/* --------------------------------- TIMERn_CR1 --------------------------------- */ +#define TIMERn_CR1_CAP_Pos 0 /*!< TIMERn CR1: CAP Position */ +#define TIMERn_CR1_CAP_Msk (0xffffffffUL << TIMERn_CR1_CAP_Pos) /*!< TIMERn CR1: CAP Mask */ + +/* --------------------------------- TIMERn_CR2 --------------------------------- */ +#define TIMERn_CR2_CAP_Pos 0 /*!< TIMERn CR2: CAP Position */ +#define TIMERn_CR2_CAP_Msk (0xffffffffUL << TIMERn_CR2_CAP_Pos) /*!< TIMERn CR2: CAP Mask */ + +/* --------------------------------- TIMERn_CR3 --------------------------------- */ +#define TIMERn_CR3_CAP_Pos 0 /*!< TIMERn CR3: CAP Position */ +#define TIMERn_CR3_CAP_Msk (0xffffffffUL << TIMERn_CR3_CAP_Pos) /*!< TIMERn CR3: CAP Mask */ + +/* --------------------------------- TIMERn_EMR --------------------------------- */ +#define TIMERn_EMR_EM0_Pos 0 /*!< TIMERn EMR: EM0 Position */ +#define TIMERn_EMR_EM0_Msk (0x01UL << TIMERn_EMR_EM0_Pos) /*!< TIMERn EMR: EM0 Mask */ +#define TIMERn_EMR_EM1_Pos 1 /*!< TIMERn EMR: EM1 Position */ +#define TIMERn_EMR_EM1_Msk (0x01UL << TIMERn_EMR_EM1_Pos) /*!< TIMERn EMR: EM1 Mask */ +#define TIMERn_EMR_EM2_Pos 2 /*!< TIMERn EMR: EM2 Position */ +#define TIMERn_EMR_EM2_Msk (0x01UL << TIMERn_EMR_EM2_Pos) /*!< TIMERn EMR: EM2 Mask */ +#define TIMERn_EMR_EM3_Pos 3 /*!< TIMERn EMR: EM3 Position */ +#define TIMERn_EMR_EM3_Msk (0x01UL << TIMERn_EMR_EM3_Pos) /*!< TIMERn EMR: EM3 Mask */ +#define TIMERn_EMR_EMC0_Pos 4 /*!< TIMERn EMR: EMC0 Position */ +#define TIMERn_EMR_EMC0_Msk (0x03UL << TIMERn_EMR_EMC0_Pos) /*!< TIMERn EMR: EMC0 Mask */ +#define TIMERn_EMR_EMC1_Pos 6 /*!< TIMERn EMR: EMC1 Position */ +#define TIMERn_EMR_EMC1_Msk (0x03UL << TIMERn_EMR_EMC1_Pos) /*!< TIMERn EMR: EMC1 Mask */ +#define TIMERn_EMR_EMC2_Pos 8 /*!< TIMERn EMR: EMC2 Position */ +#define TIMERn_EMR_EMC2_Msk (0x03UL << TIMERn_EMR_EMC2_Pos) /*!< TIMERn EMR: EMC2 Mask */ +#define TIMERn_EMR_EMC3_Pos 10 /*!< TIMERn EMR: EMC3 Position */ +#define TIMERn_EMR_EMC3_Msk (0x03UL << TIMERn_EMR_EMC3_Pos) /*!< TIMERn EMR: EMC3 Mask */ + +/* --------------------------------- TIMERn_CTCR -------------------------------- */ +#define TIMERn_CTCR_CTMODE_Pos 0 /*!< TIMERn CTCR: CTMODE Position */ +#define TIMERn_CTCR_CTMODE_Msk (0x03UL << TIMERn_CTCR_CTMODE_Pos) /*!< TIMERn CTCR: CTMODE Mask */ +#define TIMERn_CTCR_CINSEL_Pos 2 /*!< TIMERn CTCR: CINSEL Position */ +#define TIMERn_CTCR_CINSEL_Msk (0x03UL << TIMERn_CTCR_CINSEL_Pos) /*!< TIMERn CTCR: CINSEL Mask */ + + +/* ================================================================================ */ +/* ================ struct 'TIMER0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- TIMER0_IR --------------------------------- */ +#define TIMER0_IR_MR0INT_Pos 0 /*!< TIMER0 IR: MR0INT Position */ +#define TIMER0_IR_MR0INT_Msk (0x01UL << TIMER0_IR_MR0INT_Pos) /*!< TIMER0 IR: MR0INT Mask */ +#define TIMER0_IR_MR1INT_Pos 1 /*!< TIMER0 IR: MR1INT Position */ +#define TIMER0_IR_MR1INT_Msk (0x01UL << TIMER0_IR_MR1INT_Pos) /*!< TIMER0 IR: MR1INT Mask */ +#define TIMER0_IR_MR2INT_Pos 2 /*!< TIMER0 IR: MR2INT Position */ +#define TIMER0_IR_MR2INT_Msk (0x01UL << TIMER0_IR_MR2INT_Pos) /*!< TIMER0 IR: MR2INT Mask */ +#define TIMER0_IR_MR3INT_Pos 3 /*!< TIMER0 IR: MR3INT Position */ +#define TIMER0_IR_MR3INT_Msk (0x01UL << TIMER0_IR_MR3INT_Pos) /*!< TIMER0 IR: MR3INT Mask */ +#define TIMER0_IR_CR0INT_Pos 4 /*!< TIMER0 IR: CR0INT Position */ +#define TIMER0_IR_CR0INT_Msk (0x01UL << TIMER0_IR_CR0INT_Pos) /*!< TIMER0 IR: CR0INT Mask */ +#define TIMER0_IR_CR1INT_Pos 5 /*!< TIMER0 IR: CR1INT Position */ +#define TIMER0_IR_CR1INT_Msk (0x01UL << TIMER0_IR_CR1INT_Pos) /*!< TIMER0 IR: CR1INT Mask */ +#define TIMER0_IR_CR2INT_Pos 6 /*!< TIMER0 IR: CR2INT Position */ +#define TIMER0_IR_CR2INT_Msk (0x01UL << TIMER0_IR_CR2INT_Pos) /*!< TIMER0 IR: CR2INT Mask */ +#define TIMER0_IR_CR3INT_Pos 7 /*!< TIMER0 IR: CR3INT Position */ +#define TIMER0_IR_CR3INT_Msk (0x01UL << TIMER0_IR_CR3INT_Pos) /*!< TIMER0 IR: CR3INT Mask */ + +/* --------------------------------- TIMER0_TCR --------------------------------- */ +#define TIMER0_TCR_CEN_Pos 0 /*!< TIMER0 TCR: CEN Position */ +#define TIMER0_TCR_CEN_Msk (0x01UL << TIMER0_TCR_CEN_Pos) /*!< TIMER0 TCR: CEN Mask */ +#define TIMER0_TCR_CRST_Pos 1 /*!< TIMER0 TCR: CRST Position */ +#define TIMER0_TCR_CRST_Msk (0x01UL << TIMER0_TCR_CRST_Pos) /*!< TIMER0 TCR: CRST Mask */ + +/* ---------------------------------- TIMER0_TC --------------------------------- */ +#define TIMER0_TC_TC_Pos 0 /*!< TIMER0 TC: TC Position */ +#define TIMER0_TC_TC_Msk (0xffffffffUL << TIMER0_TC_TC_Pos) /*!< TIMER0 TC: TC Mask */ + +/* ---------------------------------- TIMER0_PR --------------------------------- */ +#define TIMER0_PR_PM_Pos 0 /*!< TIMER0 PR: PM Position */ +#define TIMER0_PR_PM_Msk (0xffffffffUL << TIMER0_PR_PM_Pos) /*!< TIMER0 PR: PM Mask */ + +/* ---------------------------------- TIMER0_PC --------------------------------- */ +#define TIMER0_PC_PC_Pos 0 /*!< TIMER0 PC: PC Position */ +#define TIMER0_PC_PC_Msk (0xffffffffUL << TIMER0_PC_PC_Pos) /*!< TIMER0 PC: PC Mask */ + +/* --------------------------------- TIMER0_MCR --------------------------------- */ +#define TIMER0_MCR_MR0I_Pos 0 /*!< TIMER0 MCR: MR0I Position */ +#define TIMER0_MCR_MR0I_Msk (0x01UL << TIMER0_MCR_MR0I_Pos) /*!< TIMER0 MCR: MR0I Mask */ +#define TIMER0_MCR_MR0R_Pos 1 /*!< TIMER0 MCR: MR0R Position */ +#define TIMER0_MCR_MR0R_Msk (0x01UL << TIMER0_MCR_MR0R_Pos) /*!< TIMER0 MCR: MR0R Mask */ +#define TIMER0_MCR_MR0S_Pos 2 /*!< TIMER0 MCR: MR0S Position */ +#define TIMER0_MCR_MR0S_Msk (0x01UL << TIMER0_MCR_MR0S_Pos) /*!< TIMER0 MCR: MR0S Mask */ +#define TIMER0_MCR_MR1I_Pos 3 /*!< TIMER0 MCR: MR1I Position */ +#define TIMER0_MCR_MR1I_Msk (0x01UL << TIMER0_MCR_MR1I_Pos) /*!< TIMER0 MCR: MR1I Mask */ +#define TIMER0_MCR_MR1R_Pos 4 /*!< TIMER0 MCR: MR1R Position */ +#define TIMER0_MCR_MR1R_Msk (0x01UL << TIMER0_MCR_MR1R_Pos) /*!< TIMER0 MCR: MR1R Mask */ +#define TIMER0_MCR_MR1S_Pos 5 /*!< TIMER0 MCR: MR1S Position */ +#define TIMER0_MCR_MR1S_Msk (0x01UL << TIMER0_MCR_MR1S_Pos) /*!< TIMER0 MCR: MR1S Mask */ +#define TIMER0_MCR_MR2I_Pos 6 /*!< TIMER0 MCR: MR2I Position */ +#define TIMER0_MCR_MR2I_Msk (0x01UL << TIMER0_MCR_MR2I_Pos) /*!< TIMER0 MCR: MR2I Mask */ +#define TIMER0_MCR_MR2R_Pos 7 /*!< TIMER0 MCR: MR2R Position */ +#define TIMER0_MCR_MR2R_Msk (0x01UL << TIMER0_MCR_MR2R_Pos) /*!< TIMER0 MCR: MR2R Mask */ +#define TIMER0_MCR_MR2S_Pos 8 /*!< TIMER0 MCR: MR2S Position */ +#define TIMER0_MCR_MR2S_Msk (0x01UL << TIMER0_MCR_MR2S_Pos) /*!< TIMER0 MCR: MR2S Mask */ +#define TIMER0_MCR_MR3I_Pos 9 /*!< TIMER0 MCR: MR3I Position */ +#define TIMER0_MCR_MR3I_Msk (0x01UL << TIMER0_MCR_MR3I_Pos) /*!< TIMER0 MCR: MR3I Mask */ +#define TIMER0_MCR_MR3R_Pos 10 /*!< TIMER0 MCR: MR3R Position */ +#define TIMER0_MCR_MR3R_Msk (0x01UL << TIMER0_MCR_MR3R_Pos) /*!< TIMER0 MCR: MR3R Mask */ +#define TIMER0_MCR_MR3S_Pos 11 /*!< TIMER0 MCR: MR3S Position */ +#define TIMER0_MCR_MR3S_Msk (0x01UL << TIMER0_MCR_MR3S_Pos) /*!< TIMER0 MCR: MR3S Mask */ + +/* --------------------------------- TIMER0_MR0 --------------------------------- */ +#define TIMER0_MR0_MATCH_Pos 0 /*!< TIMER0 MR0: MATCH Position */ +#define TIMER0_MR0_MATCH_Msk (0xffffffffUL << TIMER0_MR0_MATCH_Pos) /*!< TIMER0 MR0: MATCH Mask */ + +/* --------------------------------- TIMER0_MR1 --------------------------------- */ +#define TIMER0_MR1_MATCH_Pos 0 /*!< TIMER0 MR1: MATCH Position */ +#define TIMER0_MR1_MATCH_Msk (0xffffffffUL << TIMER0_MR1_MATCH_Pos) /*!< TIMER0 MR1: MATCH Mask */ + +/* --------------------------------- TIMER0_MR2 --------------------------------- */ +#define TIMER0_MR2_MATCH_Pos 0 /*!< TIMER0 MR2: MATCH Position */ +#define TIMER0_MR2_MATCH_Msk (0xffffffffUL << TIMER0_MR2_MATCH_Pos) /*!< TIMER0 MR2: MATCH Mask */ + +/* --------------------------------- TIMER0_MR3 --------------------------------- */ +#define TIMER0_MR3_MATCH_Pos 0 /*!< TIMER0 MR3: MATCH Position */ +#define TIMER0_MR3_MATCH_Msk (0xffffffffUL << TIMER0_MR3_MATCH_Pos) /*!< TIMER0 MR3: MATCH Mask */ + +/* --------------------------------- TIMER0_CCR --------------------------------- */ +#define TIMER0_CCR_CAP0RE_Pos 0 /*!< TIMER0 CCR: CAP0RE Position */ +#define TIMER0_CCR_CAP0RE_Msk (0x01UL << TIMER0_CCR_CAP0RE_Pos) /*!< TIMER0 CCR: CAP0RE Mask */ +#define TIMER0_CCR_CAP0FE_Pos 1 /*!< TIMER0 CCR: CAP0FE Position */ +#define TIMER0_CCR_CAP0FE_Msk (0x01UL << TIMER0_CCR_CAP0FE_Pos) /*!< TIMER0 CCR: CAP0FE Mask */ +#define TIMER0_CCR_CAP0I_Pos 2 /*!< TIMER0 CCR: CAP0I Position */ +#define TIMER0_CCR_CAP0I_Msk (0x01UL << TIMER0_CCR_CAP0I_Pos) /*!< TIMER0 CCR: CAP0I Mask */ +#define TIMER0_CCR_CAP1RE_Pos 3 /*!< TIMER0 CCR: CAP1RE Position */ +#define TIMER0_CCR_CAP1RE_Msk (0x01UL << TIMER0_CCR_CAP1RE_Pos) /*!< TIMER0 CCR: CAP1RE Mask */ +#define TIMER0_CCR_CAP1FE_Pos 4 /*!< TIMER0 CCR: CAP1FE Position */ +#define TIMER0_CCR_CAP1FE_Msk (0x01UL << TIMER0_CCR_CAP1FE_Pos) /*!< TIMER0 CCR: CAP1FE Mask */ +#define TIMER0_CCR_CAP1I_Pos 5 /*!< TIMER0 CCR: CAP1I Position */ +#define TIMER0_CCR_CAP1I_Msk (0x01UL << TIMER0_CCR_CAP1I_Pos) /*!< TIMER0 CCR: CAP1I Mask */ +#define TIMER0_CCR_CAP2RE_Pos 6 /*!< TIMER0 CCR: CAP2RE Position */ +#define TIMER0_CCR_CAP2RE_Msk (0x01UL << TIMER0_CCR_CAP2RE_Pos) /*!< TIMER0 CCR: CAP2RE Mask */ +#define TIMER0_CCR_CAP2FE_Pos 7 /*!< TIMER0 CCR: CAP2FE Position */ +#define TIMER0_CCR_CAP2FE_Msk (0x01UL << TIMER0_CCR_CAP2FE_Pos) /*!< TIMER0 CCR: CAP2FE Mask */ +#define TIMER0_CCR_CAP2I_Pos 8 /*!< TIMER0 CCR: CAP2I Position */ +#define TIMER0_CCR_CAP2I_Msk (0x01UL << TIMER0_CCR_CAP2I_Pos) /*!< TIMER0 CCR: CAP2I Mask */ +#define TIMER0_CCR_CAP3RE_Pos 9 /*!< TIMER0 CCR: CAP3RE Position */ +#define TIMER0_CCR_CAP3RE_Msk (0x01UL << TIMER0_CCR_CAP3RE_Pos) /*!< TIMER0 CCR: CAP3RE Mask */ +#define TIMER0_CCR_CAP3FE_Pos 10 /*!< TIMER0 CCR: CAP3FE Position */ +#define TIMER0_CCR_CAP3FE_Msk (0x01UL << TIMER0_CCR_CAP3FE_Pos) /*!< TIMER0 CCR: CAP3FE Mask */ +#define TIMER0_CCR_CAP3I_Pos 11 /*!< TIMER0 CCR: CAP3I Position */ +#define TIMER0_CCR_CAP3I_Msk (0x01UL << TIMER0_CCR_CAP3I_Pos) /*!< TIMER0 CCR: CAP3I Mask */ + +/* --------------------------------- TIMER0_CR0 --------------------------------- */ +#define TIMER0_CR0_CAP_Pos 0 /*!< TIMER0 CR0: CAP Position */ +#define TIMER0_CR0_CAP_Msk (0xffffffffUL << TIMER0_CR0_CAP_Pos) /*!< TIMER0 CR0: CAP Mask */ + +/* --------------------------------- TIMER0_CR1 --------------------------------- */ +#define TIMER0_CR1_CAP_Pos 0 /*!< TIMER0 CR1: CAP Position */ +#define TIMER0_CR1_CAP_Msk (0xffffffffUL << TIMER0_CR1_CAP_Pos) /*!< TIMER0 CR1: CAP Mask */ + +/* --------------------------------- TIMER0_CR2 --------------------------------- */ +#define TIMER0_CR2_CAP_Pos 0 /*!< TIMER0 CR2: CAP Position */ +#define TIMER0_CR2_CAP_Msk (0xffffffffUL << TIMER0_CR2_CAP_Pos) /*!< TIMER0 CR2: CAP Mask */ + +/* --------------------------------- TIMER0_CR3 --------------------------------- */ +#define TIMER0_CR3_CAP_Pos 0 /*!< TIMER0 CR3: CAP Position */ +#define TIMER0_CR3_CAP_Msk (0xffffffffUL << TIMER0_CR3_CAP_Pos) /*!< TIMER0 CR3: CAP Mask */ + +/* --------------------------------- TIMER0_EMR --------------------------------- */ +#define TIMER0_EMR_EM0_Pos 0 /*!< TIMER0 EMR: EM0 Position */ +#define TIMER0_EMR_EM0_Msk (0x01UL << TIMER0_EMR_EM0_Pos) /*!< TIMER0 EMR: EM0 Mask */ +#define TIMER0_EMR_EM1_Pos 1 /*!< TIMER0 EMR: EM1 Position */ +#define TIMER0_EMR_EM1_Msk (0x01UL << TIMER0_EMR_EM1_Pos) /*!< TIMER0 EMR: EM1 Mask */ +#define TIMER0_EMR_EM2_Pos 2 /*!< TIMER0 EMR: EM2 Position */ +#define TIMER0_EMR_EM2_Msk (0x01UL << TIMER0_EMR_EM2_Pos) /*!< TIMER0 EMR: EM2 Mask */ +#define TIMER0_EMR_EM3_Pos 3 /*!< TIMER0 EMR: EM3 Position */ +#define TIMER0_EMR_EM3_Msk (0x01UL << TIMER0_EMR_EM3_Pos) /*!< TIMER0 EMR: EM3 Mask */ +#define TIMER0_EMR_EMC0_Pos 4 /*!< TIMER0 EMR: EMC0 Position */ +#define TIMER0_EMR_EMC0_Msk (0x03UL << TIMER0_EMR_EMC0_Pos) /*!< TIMER0 EMR: EMC0 Mask */ +#define TIMER0_EMR_EMC1_Pos 6 /*!< TIMER0 EMR: EMC1 Position */ +#define TIMER0_EMR_EMC1_Msk (0x03UL << TIMER0_EMR_EMC1_Pos) /*!< TIMER0 EMR: EMC1 Mask */ +#define TIMER0_EMR_EMC2_Pos 8 /*!< TIMER0 EMR: EMC2 Position */ +#define TIMER0_EMR_EMC2_Msk (0x03UL << TIMER0_EMR_EMC2_Pos) /*!< TIMER0 EMR: EMC2 Mask */ +#define TIMER0_EMR_EMC3_Pos 10 /*!< TIMER0 EMR: EMC3 Position */ +#define TIMER0_EMR_EMC3_Msk (0x03UL << TIMER0_EMR_EMC3_Pos) /*!< TIMER0 EMR: EMC3 Mask */ + +/* --------------------------------- TIMER0_CTCR -------------------------------- */ +#define TIMER0_CTCR_CTMODE_Pos 0 /*!< TIMER0 CTCR: CTMODE Position */ +#define TIMER0_CTCR_CTMODE_Msk (0x03UL << TIMER0_CTCR_CTMODE_Pos) /*!< TIMER0 CTCR: CTMODE Mask */ +#define TIMER0_CTCR_CINSEL_Pos 2 /*!< TIMER0 CTCR: CINSEL Position */ +#define TIMER0_CTCR_CINSEL_Msk (0x03UL << TIMER0_CTCR_CINSEL_Pos) /*!< TIMER0 CTCR: CINSEL Mask */ + + +/* ================================================================================ */ +/* ================ struct 'TIMER1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- TIMER1_IR --------------------------------- */ +#define TIMER1_IR_MR0INT_Pos 0 /*!< TIMER1 IR: MR0INT Position */ +#define TIMER1_IR_MR0INT_Msk (0x01UL << TIMER1_IR_MR0INT_Pos) /*!< TIMER1 IR: MR0INT Mask */ +#define TIMER1_IR_MR1INT_Pos 1 /*!< TIMER1 IR: MR1INT Position */ +#define TIMER1_IR_MR1INT_Msk (0x01UL << TIMER1_IR_MR1INT_Pos) /*!< TIMER1 IR: MR1INT Mask */ +#define TIMER1_IR_MR2INT_Pos 2 /*!< TIMER1 IR: MR2INT Position */ +#define TIMER1_IR_MR2INT_Msk (0x01UL << TIMER1_IR_MR2INT_Pos) /*!< TIMER1 IR: MR2INT Mask */ +#define TIMER1_IR_MR3INT_Pos 3 /*!< TIMER1 IR: MR3INT Position */ +#define TIMER1_IR_MR3INT_Msk (0x01UL << TIMER1_IR_MR3INT_Pos) /*!< TIMER1 IR: MR3INT Mask */ +#define TIMER1_IR_CR0INT_Pos 4 /*!< TIMER1 IR: CR0INT Position */ +#define TIMER1_IR_CR0INT_Msk (0x01UL << TIMER1_IR_CR0INT_Pos) /*!< TIMER1 IR: CR0INT Mask */ +#define TIMER1_IR_CR1INT_Pos 5 /*!< TIMER1 IR: CR1INT Position */ +#define TIMER1_IR_CR1INT_Msk (0x01UL << TIMER1_IR_CR1INT_Pos) /*!< TIMER1 IR: CR1INT Mask */ +#define TIMER1_IR_CR2INT_Pos 6 /*!< TIMER1 IR: CR2INT Position */ +#define TIMER1_IR_CR2INT_Msk (0x01UL << TIMER1_IR_CR2INT_Pos) /*!< TIMER1 IR: CR2INT Mask */ +#define TIMER1_IR_CR3INT_Pos 7 /*!< TIMER1 IR: CR3INT Position */ +#define TIMER1_IR_CR3INT_Msk (0x01UL << TIMER1_IR_CR3INT_Pos) /*!< TIMER1 IR: CR3INT Mask */ + +/* --------------------------------- TIMER1_TCR --------------------------------- */ +#define TIMER1_TCR_CEN_Pos 0 /*!< TIMER1 TCR: CEN Position */ +#define TIMER1_TCR_CEN_Msk (0x01UL << TIMER1_TCR_CEN_Pos) /*!< TIMER1 TCR: CEN Mask */ +#define TIMER1_TCR_CRST_Pos 1 /*!< TIMER1 TCR: CRST Position */ +#define TIMER1_TCR_CRST_Msk (0x01UL << TIMER1_TCR_CRST_Pos) /*!< TIMER1 TCR: CRST Mask */ + +/* ---------------------------------- TIMER1_TC --------------------------------- */ +#define TIMER1_TC_TC_Pos 0 /*!< TIMER1 TC: TC Position */ +#define TIMER1_TC_TC_Msk (0xffffffffUL << TIMER1_TC_TC_Pos) /*!< TIMER1 TC: TC Mask */ + +/* ---------------------------------- TIMER1_PR --------------------------------- */ +#define TIMER1_PR_PM_Pos 0 /*!< TIMER1 PR: PM Position */ +#define TIMER1_PR_PM_Msk (0xffffffffUL << TIMER1_PR_PM_Pos) /*!< TIMER1 PR: PM Mask */ + +/* ---------------------------------- TIMER1_PC --------------------------------- */ +#define TIMER1_PC_PC_Pos 0 /*!< TIMER1 PC: PC Position */ +#define TIMER1_PC_PC_Msk (0xffffffffUL << TIMER1_PC_PC_Pos) /*!< TIMER1 PC: PC Mask */ + +/* --------------------------------- TIMER1_MCR --------------------------------- */ +#define TIMER1_MCR_MR0I_Pos 0 /*!< TIMER1 MCR: MR0I Position */ +#define TIMER1_MCR_MR0I_Msk (0x01UL << TIMER1_MCR_MR0I_Pos) /*!< TIMER1 MCR: MR0I Mask */ +#define TIMER1_MCR_MR0R_Pos 1 /*!< TIMER1 MCR: MR0R Position */ +#define TIMER1_MCR_MR0R_Msk (0x01UL << TIMER1_MCR_MR0R_Pos) /*!< TIMER1 MCR: MR0R Mask */ +#define TIMER1_MCR_MR0S_Pos 2 /*!< TIMER1 MCR: MR0S Position */ +#define TIMER1_MCR_MR0S_Msk (0x01UL << TIMER1_MCR_MR0S_Pos) /*!< TIMER1 MCR: MR0S Mask */ +#define TIMER1_MCR_MR1I_Pos 3 /*!< TIMER1 MCR: MR1I Position */ +#define TIMER1_MCR_MR1I_Msk (0x01UL << TIMER1_MCR_MR1I_Pos) /*!< TIMER1 MCR: MR1I Mask */ +#define TIMER1_MCR_MR1R_Pos 4 /*!< TIMER1 MCR: MR1R Position */ +#define TIMER1_MCR_MR1R_Msk (0x01UL << TIMER1_MCR_MR1R_Pos) /*!< TIMER1 MCR: MR1R Mask */ +#define TIMER1_MCR_MR1S_Pos 5 /*!< TIMER1 MCR: MR1S Position */ +#define TIMER1_MCR_MR1S_Msk (0x01UL << TIMER1_MCR_MR1S_Pos) /*!< TIMER1 MCR: MR1S Mask */ +#define TIMER1_MCR_MR2I_Pos 6 /*!< TIMER1 MCR: MR2I Position */ +#define TIMER1_MCR_MR2I_Msk (0x01UL << TIMER1_MCR_MR2I_Pos) /*!< TIMER1 MCR: MR2I Mask */ +#define TIMER1_MCR_MR2R_Pos 7 /*!< TIMER1 MCR: MR2R Position */ +#define TIMER1_MCR_MR2R_Msk (0x01UL << TIMER1_MCR_MR2R_Pos) /*!< TIMER1 MCR: MR2R Mask */ +#define TIMER1_MCR_MR2S_Pos 8 /*!< TIMER1 MCR: MR2S Position */ +#define TIMER1_MCR_MR2S_Msk (0x01UL << TIMER1_MCR_MR2S_Pos) /*!< TIMER1 MCR: MR2S Mask */ +#define TIMER1_MCR_MR3I_Pos 9 /*!< TIMER1 MCR: MR3I Position */ +#define TIMER1_MCR_MR3I_Msk (0x01UL << TIMER1_MCR_MR3I_Pos) /*!< TIMER1 MCR: MR3I Mask */ +#define TIMER1_MCR_MR3R_Pos 10 /*!< TIMER1 MCR: MR3R Position */ +#define TIMER1_MCR_MR3R_Msk (0x01UL << TIMER1_MCR_MR3R_Pos) /*!< TIMER1 MCR: MR3R Mask */ +#define TIMER1_MCR_MR3S_Pos 11 /*!< TIMER1 MCR: MR3S Position */ +#define TIMER1_MCR_MR3S_Msk (0x01UL << TIMER1_MCR_MR3S_Pos) /*!< TIMER1 MCR: MR3S Mask */ + +/* --------------------------------- TIMER1_MR0 --------------------------------- */ +#define TIMER1_MR0_MATCH_Pos 0 /*!< TIMER1 MR0: MATCH Position */ +#define TIMER1_MR0_MATCH_Msk (0xffffffffUL << TIMER1_MR0_MATCH_Pos) /*!< TIMER1 MR0: MATCH Mask */ + +/* --------------------------------- TIMER1_MR1 --------------------------------- */ +#define TIMER1_MR1_MATCH_Pos 0 /*!< TIMER1 MR1: MATCH Position */ +#define TIMER1_MR1_MATCH_Msk (0xffffffffUL << TIMER1_MR1_MATCH_Pos) /*!< TIMER1 MR1: MATCH Mask */ + +/* --------------------------------- TIMER1_MR2 --------------------------------- */ +#define TIMER1_MR2_MATCH_Pos 0 /*!< TIMER1 MR2: MATCH Position */ +#define TIMER1_MR2_MATCH_Msk (0xffffffffUL << TIMER1_MR2_MATCH_Pos) /*!< TIMER1 MR2: MATCH Mask */ + +/* --------------------------------- TIMER1_MR3 --------------------------------- */ +#define TIMER1_MR3_MATCH_Pos 0 /*!< TIMER1 MR3: MATCH Position */ +#define TIMER1_MR3_MATCH_Msk (0xffffffffUL << TIMER1_MR3_MATCH_Pos) /*!< TIMER1 MR3: MATCH Mask */ + +/* --------------------------------- TIMER1_CCR --------------------------------- */ +#define TIMER1_CCR_CAP0RE_Pos 0 /*!< TIMER1 CCR: CAP0RE Position */ +#define TIMER1_CCR_CAP0RE_Msk (0x01UL << TIMER1_CCR_CAP0RE_Pos) /*!< TIMER1 CCR: CAP0RE Mask */ +#define TIMER1_CCR_CAP0FE_Pos 1 /*!< TIMER1 CCR: CAP0FE Position */ +#define TIMER1_CCR_CAP0FE_Msk (0x01UL << TIMER1_CCR_CAP0FE_Pos) /*!< TIMER1 CCR: CAP0FE Mask */ +#define TIMER1_CCR_CAP0I_Pos 2 /*!< TIMER1 CCR: CAP0I Position */ +#define TIMER1_CCR_CAP0I_Msk (0x01UL << TIMER1_CCR_CAP0I_Pos) /*!< TIMER1 CCR: CAP0I Mask */ +#define TIMER1_CCR_CAP1RE_Pos 3 /*!< TIMER1 CCR: CAP1RE Position */ +#define TIMER1_CCR_CAP1RE_Msk (0x01UL << TIMER1_CCR_CAP1RE_Pos) /*!< TIMER1 CCR: CAP1RE Mask */ +#define TIMER1_CCR_CAP1FE_Pos 4 /*!< TIMER1 CCR: CAP1FE Position */ +#define TIMER1_CCR_CAP1FE_Msk (0x01UL << TIMER1_CCR_CAP1FE_Pos) /*!< TIMER1 CCR: CAP1FE Mask */ +#define TIMER1_CCR_CAP1I_Pos 5 /*!< TIMER1 CCR: CAP1I Position */ +#define TIMER1_CCR_CAP1I_Msk (0x01UL << TIMER1_CCR_CAP1I_Pos) /*!< TIMER1 CCR: CAP1I Mask */ +#define TIMER1_CCR_CAP2RE_Pos 6 /*!< TIMER1 CCR: CAP2RE Position */ +#define TIMER1_CCR_CAP2RE_Msk (0x01UL << TIMER1_CCR_CAP2RE_Pos) /*!< TIMER1 CCR: CAP2RE Mask */ +#define TIMER1_CCR_CAP2FE_Pos 7 /*!< TIMER1 CCR: CAP2FE Position */ +#define TIMER1_CCR_CAP2FE_Msk (0x01UL << TIMER1_CCR_CAP2FE_Pos) /*!< TIMER1 CCR: CAP2FE Mask */ +#define TIMER1_CCR_CAP2I_Pos 8 /*!< TIMER1 CCR: CAP2I Position */ +#define TIMER1_CCR_CAP2I_Msk (0x01UL << TIMER1_CCR_CAP2I_Pos) /*!< TIMER1 CCR: CAP2I Mask */ +#define TIMER1_CCR_CAP3RE_Pos 9 /*!< TIMER1 CCR: CAP3RE Position */ +#define TIMER1_CCR_CAP3RE_Msk (0x01UL << TIMER1_CCR_CAP3RE_Pos) /*!< TIMER1 CCR: CAP3RE Mask */ +#define TIMER1_CCR_CAP3FE_Pos 10 /*!< TIMER1 CCR: CAP3FE Position */ +#define TIMER1_CCR_CAP3FE_Msk (0x01UL << TIMER1_CCR_CAP3FE_Pos) /*!< TIMER1 CCR: CAP3FE Mask */ +#define TIMER1_CCR_CAP3I_Pos 11 /*!< TIMER1 CCR: CAP3I Position */ +#define TIMER1_CCR_CAP3I_Msk (0x01UL << TIMER1_CCR_CAP3I_Pos) /*!< TIMER1 CCR: CAP3I Mask */ + +/* --------------------------------- TIMER1_CR0 --------------------------------- */ +#define TIMER1_CR0_CAP_Pos 0 /*!< TIMER1 CR0: CAP Position */ +#define TIMER1_CR0_CAP_Msk (0xffffffffUL << TIMER1_CR0_CAP_Pos) /*!< TIMER1 CR0: CAP Mask */ + +/* --------------------------------- TIMER1_CR1 --------------------------------- */ +#define TIMER1_CR1_CAP_Pos 0 /*!< TIMER1 CR1: CAP Position */ +#define TIMER1_CR1_CAP_Msk (0xffffffffUL << TIMER1_CR1_CAP_Pos) /*!< TIMER1 CR1: CAP Mask */ + +/* --------------------------------- TIMER1_CR2 --------------------------------- */ +#define TIMER1_CR2_CAP_Pos 0 /*!< TIMER1 CR2: CAP Position */ +#define TIMER1_CR2_CAP_Msk (0xffffffffUL << TIMER1_CR2_CAP_Pos) /*!< TIMER1 CR2: CAP Mask */ + +/* --------------------------------- TIMER1_CR3 --------------------------------- */ +#define TIMER1_CR3_CAP_Pos 0 /*!< TIMER1 CR3: CAP Position */ +#define TIMER1_CR3_CAP_Msk (0xffffffffUL << TIMER1_CR3_CAP_Pos) /*!< TIMER1 CR3: CAP Mask */ + +/* --------------------------------- TIMER1_EMR --------------------------------- */ +#define TIMER1_EMR_EM0_Pos 0 /*!< TIMER1 EMR: EM0 Position */ +#define TIMER1_EMR_EM0_Msk (0x01UL << TIMER1_EMR_EM0_Pos) /*!< TIMER1 EMR: EM0 Mask */ +#define TIMER1_EMR_EM1_Pos 1 /*!< TIMER1 EMR: EM1 Position */ +#define TIMER1_EMR_EM1_Msk (0x01UL << TIMER1_EMR_EM1_Pos) /*!< TIMER1 EMR: EM1 Mask */ +#define TIMER1_EMR_EM2_Pos 2 /*!< TIMER1 EMR: EM2 Position */ +#define TIMER1_EMR_EM2_Msk (0x01UL << TIMER1_EMR_EM2_Pos) /*!< TIMER1 EMR: EM2 Mask */ +#define TIMER1_EMR_EM3_Pos 3 /*!< TIMER1 EMR: EM3 Position */ +#define TIMER1_EMR_EM3_Msk (0x01UL << TIMER1_EMR_EM3_Pos) /*!< TIMER1 EMR: EM3 Mask */ +#define TIMER1_EMR_EMC0_Pos 4 /*!< TIMER1 EMR: EMC0 Position */ +#define TIMER1_EMR_EMC0_Msk (0x03UL << TIMER1_EMR_EMC0_Pos) /*!< TIMER1 EMR: EMC0 Mask */ +#define TIMER1_EMR_EMC1_Pos 6 /*!< TIMER1 EMR: EMC1 Position */ +#define TIMER1_EMR_EMC1_Msk (0x03UL << TIMER1_EMR_EMC1_Pos) /*!< TIMER1 EMR: EMC1 Mask */ +#define TIMER1_EMR_EMC2_Pos 8 /*!< TIMER1 EMR: EMC2 Position */ +#define TIMER1_EMR_EMC2_Msk (0x03UL << TIMER1_EMR_EMC2_Pos) /*!< TIMER1 EMR: EMC2 Mask */ +#define TIMER1_EMR_EMC3_Pos 10 /*!< TIMER1 EMR: EMC3 Position */ +#define TIMER1_EMR_EMC3_Msk (0x03UL << TIMER1_EMR_EMC3_Pos) /*!< TIMER1 EMR: EMC3 Mask */ + +/* --------------------------------- TIMER1_CTCR -------------------------------- */ +#define TIMER1_CTCR_CTMODE_Pos 0 /*!< TIMER1 CTCR: CTMODE Position */ +#define TIMER1_CTCR_CTMODE_Msk (0x03UL << TIMER1_CTCR_CTMODE_Pos) /*!< TIMER1 CTCR: CTMODE Mask */ +#define TIMER1_CTCR_CINSEL_Pos 2 /*!< TIMER1 CTCR: CINSEL Position */ +#define TIMER1_CTCR_CINSEL_Msk (0x03UL << TIMER1_CTCR_CINSEL_Pos) /*!< TIMER1 CTCR: CINSEL Mask */ + + +/* ================================================================================ */ +/* ================ struct 'TIMER2' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- TIMER2_IR --------------------------------- */ +#define TIMER2_IR_MR0INT_Pos 0 /*!< TIMER2 IR: MR0INT Position */ +#define TIMER2_IR_MR0INT_Msk (0x01UL << TIMER2_IR_MR0INT_Pos) /*!< TIMER2 IR: MR0INT Mask */ +#define TIMER2_IR_MR1INT_Pos 1 /*!< TIMER2 IR: MR1INT Position */ +#define TIMER2_IR_MR1INT_Msk (0x01UL << TIMER2_IR_MR1INT_Pos) /*!< TIMER2 IR: MR1INT Mask */ +#define TIMER2_IR_MR2INT_Pos 2 /*!< TIMER2 IR: MR2INT Position */ +#define TIMER2_IR_MR2INT_Msk (0x01UL << TIMER2_IR_MR2INT_Pos) /*!< TIMER2 IR: MR2INT Mask */ +#define TIMER2_IR_MR3INT_Pos 3 /*!< TIMER2 IR: MR3INT Position */ +#define TIMER2_IR_MR3INT_Msk (0x01UL << TIMER2_IR_MR3INT_Pos) /*!< TIMER2 IR: MR3INT Mask */ +#define TIMER2_IR_CR0INT_Pos 4 /*!< TIMER2 IR: CR0INT Position */ +#define TIMER2_IR_CR0INT_Msk (0x01UL << TIMER2_IR_CR0INT_Pos) /*!< TIMER2 IR: CR0INT Mask */ +#define TIMER2_IR_CR1INT_Pos 5 /*!< TIMER2 IR: CR1INT Position */ +#define TIMER2_IR_CR1INT_Msk (0x01UL << TIMER2_IR_CR1INT_Pos) /*!< TIMER2 IR: CR1INT Mask */ +#define TIMER2_IR_CR2INT_Pos 6 /*!< TIMER2 IR: CR2INT Position */ +#define TIMER2_IR_CR2INT_Msk (0x01UL << TIMER2_IR_CR2INT_Pos) /*!< TIMER2 IR: CR2INT Mask */ +#define TIMER2_IR_CR3INT_Pos 7 /*!< TIMER2 IR: CR3INT Position */ +#define TIMER2_IR_CR3INT_Msk (0x01UL << TIMER2_IR_CR3INT_Pos) /*!< TIMER2 IR: CR3INT Mask */ + +/* --------------------------------- TIMER2_TCR --------------------------------- */ +#define TIMER2_TCR_CEN_Pos 0 /*!< TIMER2 TCR: CEN Position */ +#define TIMER2_TCR_CEN_Msk (0x01UL << TIMER2_TCR_CEN_Pos) /*!< TIMER2 TCR: CEN Mask */ +#define TIMER2_TCR_CRST_Pos 1 /*!< TIMER2 TCR: CRST Position */ +#define TIMER2_TCR_CRST_Msk (0x01UL << TIMER2_TCR_CRST_Pos) /*!< TIMER2 TCR: CRST Mask */ + +/* ---------------------------------- TIMER2_TC --------------------------------- */ +#define TIMER2_TC_TC_Pos 0 /*!< TIMER2 TC: TC Position */ +#define TIMER2_TC_TC_Msk (0xffffffffUL << TIMER2_TC_TC_Pos) /*!< TIMER2 TC: TC Mask */ + +/* ---------------------------------- TIMER2_PR --------------------------------- */ +#define TIMER2_PR_PM_Pos 0 /*!< TIMER2 PR: PM Position */ +#define TIMER2_PR_PM_Msk (0xffffffffUL << TIMER2_PR_PM_Pos) /*!< TIMER2 PR: PM Mask */ + +/* ---------------------------------- TIMER2_PC --------------------------------- */ +#define TIMER2_PC_PC_Pos 0 /*!< TIMER2 PC: PC Position */ +#define TIMER2_PC_PC_Msk (0xffffffffUL << TIMER2_PC_PC_Pos) /*!< TIMER2 PC: PC Mask */ + +/* --------------------------------- TIMER2_MCR --------------------------------- */ +#define TIMER2_MCR_MR0I_Pos 0 /*!< TIMER2 MCR: MR0I Position */ +#define TIMER2_MCR_MR0I_Msk (0x01UL << TIMER2_MCR_MR0I_Pos) /*!< TIMER2 MCR: MR0I Mask */ +#define TIMER2_MCR_MR0R_Pos 1 /*!< TIMER2 MCR: MR0R Position */ +#define TIMER2_MCR_MR0R_Msk (0x01UL << TIMER2_MCR_MR0R_Pos) /*!< TIMER2 MCR: MR0R Mask */ +#define TIMER2_MCR_MR0S_Pos 2 /*!< TIMER2 MCR: MR0S Position */ +#define TIMER2_MCR_MR0S_Msk (0x01UL << TIMER2_MCR_MR0S_Pos) /*!< TIMER2 MCR: MR0S Mask */ +#define TIMER2_MCR_MR1I_Pos 3 /*!< TIMER2 MCR: MR1I Position */ +#define TIMER2_MCR_MR1I_Msk (0x01UL << TIMER2_MCR_MR1I_Pos) /*!< TIMER2 MCR: MR1I Mask */ +#define TIMER2_MCR_MR1R_Pos 4 /*!< TIMER2 MCR: MR1R Position */ +#define TIMER2_MCR_MR1R_Msk (0x01UL << TIMER2_MCR_MR1R_Pos) /*!< TIMER2 MCR: MR1R Mask */ +#define TIMER2_MCR_MR1S_Pos 5 /*!< TIMER2 MCR: MR1S Position */ +#define TIMER2_MCR_MR1S_Msk (0x01UL << TIMER2_MCR_MR1S_Pos) /*!< TIMER2 MCR: MR1S Mask */ +#define TIMER2_MCR_MR2I_Pos 6 /*!< TIMER2 MCR: MR2I Position */ +#define TIMER2_MCR_MR2I_Msk (0x01UL << TIMER2_MCR_MR2I_Pos) /*!< TIMER2 MCR: MR2I Mask */ +#define TIMER2_MCR_MR2R_Pos 7 /*!< TIMER2 MCR: MR2R Position */ +#define TIMER2_MCR_MR2R_Msk (0x01UL << TIMER2_MCR_MR2R_Pos) /*!< TIMER2 MCR: MR2R Mask */ +#define TIMER2_MCR_MR2S_Pos 8 /*!< TIMER2 MCR: MR2S Position */ +#define TIMER2_MCR_MR2S_Msk (0x01UL << TIMER2_MCR_MR2S_Pos) /*!< TIMER2 MCR: MR2S Mask */ +#define TIMER2_MCR_MR3I_Pos 9 /*!< TIMER2 MCR: MR3I Position */ +#define TIMER2_MCR_MR3I_Msk (0x01UL << TIMER2_MCR_MR3I_Pos) /*!< TIMER2 MCR: MR3I Mask */ +#define TIMER2_MCR_MR3R_Pos 10 /*!< TIMER2 MCR: MR3R Position */ +#define TIMER2_MCR_MR3R_Msk (0x01UL << TIMER2_MCR_MR3R_Pos) /*!< TIMER2 MCR: MR3R Mask */ +#define TIMER2_MCR_MR3S_Pos 11 /*!< TIMER2 MCR: MR3S Position */ +#define TIMER2_MCR_MR3S_Msk (0x01UL << TIMER2_MCR_MR3S_Pos) /*!< TIMER2 MCR: MR3S Mask */ + +/* --------------------------------- TIMER2_MR0 --------------------------------- */ +#define TIMER2_MR0_MATCH_Pos 0 /*!< TIMER2 MR0: MATCH Position */ +#define TIMER2_MR0_MATCH_Msk (0xffffffffUL << TIMER2_MR0_MATCH_Pos) /*!< TIMER2 MR0: MATCH Mask */ + +/* --------------------------------- TIMER2_MR1 --------------------------------- */ +#define TIMER2_MR1_MATCH_Pos 0 /*!< TIMER2 MR1: MATCH Position */ +#define TIMER2_MR1_MATCH_Msk (0xffffffffUL << TIMER2_MR1_MATCH_Pos) /*!< TIMER2 MR1: MATCH Mask */ + +/* --------------------------------- TIMER2_MR2 --------------------------------- */ +#define TIMER2_MR2_MATCH_Pos 0 /*!< TIMER2 MR2: MATCH Position */ +#define TIMER2_MR2_MATCH_Msk (0xffffffffUL << TIMER2_MR2_MATCH_Pos) /*!< TIMER2 MR2: MATCH Mask */ + +/* --------------------------------- TIMER2_MR3 --------------------------------- */ +#define TIMER2_MR3_MATCH_Pos 0 /*!< TIMER2 MR3: MATCH Position */ +#define TIMER2_MR3_MATCH_Msk (0xffffffffUL << TIMER2_MR3_MATCH_Pos) /*!< TIMER2 MR3: MATCH Mask */ + +/* --------------------------------- TIMER2_CCR --------------------------------- */ +#define TIMER2_CCR_CAP0RE_Pos 0 /*!< TIMER2 CCR: CAP0RE Position */ +#define TIMER2_CCR_CAP0RE_Msk (0x01UL << TIMER2_CCR_CAP0RE_Pos) /*!< TIMER2 CCR: CAP0RE Mask */ +#define TIMER2_CCR_CAP0FE_Pos 1 /*!< TIMER2 CCR: CAP0FE Position */ +#define TIMER2_CCR_CAP0FE_Msk (0x01UL << TIMER2_CCR_CAP0FE_Pos) /*!< TIMER2 CCR: CAP0FE Mask */ +#define TIMER2_CCR_CAP0I_Pos 2 /*!< TIMER2 CCR: CAP0I Position */ +#define TIMER2_CCR_CAP0I_Msk (0x01UL << TIMER2_CCR_CAP0I_Pos) /*!< TIMER2 CCR: CAP0I Mask */ +#define TIMER2_CCR_CAP1RE_Pos 3 /*!< TIMER2 CCR: CAP1RE Position */ +#define TIMER2_CCR_CAP1RE_Msk (0x01UL << TIMER2_CCR_CAP1RE_Pos) /*!< TIMER2 CCR: CAP1RE Mask */ +#define TIMER2_CCR_CAP1FE_Pos 4 /*!< TIMER2 CCR: CAP1FE Position */ +#define TIMER2_CCR_CAP1FE_Msk (0x01UL << TIMER2_CCR_CAP1FE_Pos) /*!< TIMER2 CCR: CAP1FE Mask */ +#define TIMER2_CCR_CAP1I_Pos 5 /*!< TIMER2 CCR: CAP1I Position */ +#define TIMER2_CCR_CAP1I_Msk (0x01UL << TIMER2_CCR_CAP1I_Pos) /*!< TIMER2 CCR: CAP1I Mask */ +#define TIMER2_CCR_CAP2RE_Pos 6 /*!< TIMER2 CCR: CAP2RE Position */ +#define TIMER2_CCR_CAP2RE_Msk (0x01UL << TIMER2_CCR_CAP2RE_Pos) /*!< TIMER2 CCR: CAP2RE Mask */ +#define TIMER2_CCR_CAP2FE_Pos 7 /*!< TIMER2 CCR: CAP2FE Position */ +#define TIMER2_CCR_CAP2FE_Msk (0x01UL << TIMER2_CCR_CAP2FE_Pos) /*!< TIMER2 CCR: CAP2FE Mask */ +#define TIMER2_CCR_CAP2I_Pos 8 /*!< TIMER2 CCR: CAP2I Position */ +#define TIMER2_CCR_CAP2I_Msk (0x01UL << TIMER2_CCR_CAP2I_Pos) /*!< TIMER2 CCR: CAP2I Mask */ +#define TIMER2_CCR_CAP3RE_Pos 9 /*!< TIMER2 CCR: CAP3RE Position */ +#define TIMER2_CCR_CAP3RE_Msk (0x01UL << TIMER2_CCR_CAP3RE_Pos) /*!< TIMER2 CCR: CAP3RE Mask */ +#define TIMER2_CCR_CAP3FE_Pos 10 /*!< TIMER2 CCR: CAP3FE Position */ +#define TIMER2_CCR_CAP3FE_Msk (0x01UL << TIMER2_CCR_CAP3FE_Pos) /*!< TIMER2 CCR: CAP3FE Mask */ +#define TIMER2_CCR_CAP3I_Pos 11 /*!< TIMER2 CCR: CAP3I Position */ +#define TIMER2_CCR_CAP3I_Msk (0x01UL << TIMER2_CCR_CAP3I_Pos) /*!< TIMER2 CCR: CAP3I Mask */ + +/* --------------------------------- TIMER2_CR0 --------------------------------- */ +#define TIMER2_CR0_CAP_Pos 0 /*!< TIMER2 CR0: CAP Position */ +#define TIMER2_CR0_CAP_Msk (0xffffffffUL << TIMER2_CR0_CAP_Pos) /*!< TIMER2 CR0: CAP Mask */ + +/* --------------------------------- TIMER2_CR1 --------------------------------- */ +#define TIMER2_CR1_CAP_Pos 0 /*!< TIMER2 CR1: CAP Position */ +#define TIMER2_CR1_CAP_Msk (0xffffffffUL << TIMER2_CR1_CAP_Pos) /*!< TIMER2 CR1: CAP Mask */ + +/* --------------------------------- TIMER2_CR2 --------------------------------- */ +#define TIMER2_CR2_CAP_Pos 0 /*!< TIMER2 CR2: CAP Position */ +#define TIMER2_CR2_CAP_Msk (0xffffffffUL << TIMER2_CR2_CAP_Pos) /*!< TIMER2 CR2: CAP Mask */ + +/* --------------------------------- TIMER2_CR3 --------------------------------- */ +#define TIMER2_CR3_CAP_Pos 0 /*!< TIMER2 CR3: CAP Position */ +#define TIMER2_CR3_CAP_Msk (0xffffffffUL << TIMER2_CR3_CAP_Pos) /*!< TIMER2 CR3: CAP Mask */ + +/* --------------------------------- TIMER2_EMR --------------------------------- */ +#define TIMER2_EMR_EM0_Pos 0 /*!< TIMER2 EMR: EM0 Position */ +#define TIMER2_EMR_EM0_Msk (0x01UL << TIMER2_EMR_EM0_Pos) /*!< TIMER2 EMR: EM0 Mask */ +#define TIMER2_EMR_EM1_Pos 1 /*!< TIMER2 EMR: EM1 Position */ +#define TIMER2_EMR_EM1_Msk (0x01UL << TIMER2_EMR_EM1_Pos) /*!< TIMER2 EMR: EM1 Mask */ +#define TIMER2_EMR_EM2_Pos 2 /*!< TIMER2 EMR: EM2 Position */ +#define TIMER2_EMR_EM2_Msk (0x01UL << TIMER2_EMR_EM2_Pos) /*!< TIMER2 EMR: EM2 Mask */ +#define TIMER2_EMR_EM3_Pos 3 /*!< TIMER2 EMR: EM3 Position */ +#define TIMER2_EMR_EM3_Msk (0x01UL << TIMER2_EMR_EM3_Pos) /*!< TIMER2 EMR: EM3 Mask */ +#define TIMER2_EMR_EMC0_Pos 4 /*!< TIMER2 EMR: EMC0 Position */ +#define TIMER2_EMR_EMC0_Msk (0x03UL << TIMER2_EMR_EMC0_Pos) /*!< TIMER2 EMR: EMC0 Mask */ +#define TIMER2_EMR_EMC1_Pos 6 /*!< TIMER2 EMR: EMC1 Position */ +#define TIMER2_EMR_EMC1_Msk (0x03UL << TIMER2_EMR_EMC1_Pos) /*!< TIMER2 EMR: EMC1 Mask */ +#define TIMER2_EMR_EMC2_Pos 8 /*!< TIMER2 EMR: EMC2 Position */ +#define TIMER2_EMR_EMC2_Msk (0x03UL << TIMER2_EMR_EMC2_Pos) /*!< TIMER2 EMR: EMC2 Mask */ +#define TIMER2_EMR_EMC3_Pos 10 /*!< TIMER2 EMR: EMC3 Position */ +#define TIMER2_EMR_EMC3_Msk (0x03UL << TIMER2_EMR_EMC3_Pos) /*!< TIMER2 EMR: EMC3 Mask */ + +/* --------------------------------- TIMER2_CTCR -------------------------------- */ +#define TIMER2_CTCR_CTMODE_Pos 0 /*!< TIMER2 CTCR: CTMODE Position */ +#define TIMER2_CTCR_CTMODE_Msk (0x03UL << TIMER2_CTCR_CTMODE_Pos) /*!< TIMER2 CTCR: CTMODE Mask */ +#define TIMER2_CTCR_CINSEL_Pos 2 /*!< TIMER2 CTCR: CINSEL Position */ +#define TIMER2_CTCR_CINSEL_Msk (0x03UL << TIMER2_CTCR_CINSEL_Pos) /*!< TIMER2 CTCR: CINSEL Mask */ + + +/* ================================================================================ */ +/* ================ struct 'TIMER3' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- TIMER3_IR --------------------------------- */ +#define TIMER3_IR_MR0INT_Pos 0 /*!< TIMER3 IR: MR0INT Position */ +#define TIMER3_IR_MR0INT_Msk (0x01UL << TIMER3_IR_MR0INT_Pos) /*!< TIMER3 IR: MR0INT Mask */ +#define TIMER3_IR_MR1INT_Pos 1 /*!< TIMER3 IR: MR1INT Position */ +#define TIMER3_IR_MR1INT_Msk (0x01UL << TIMER3_IR_MR1INT_Pos) /*!< TIMER3 IR: MR1INT Mask */ +#define TIMER3_IR_MR2INT_Pos 2 /*!< TIMER3 IR: MR2INT Position */ +#define TIMER3_IR_MR2INT_Msk (0x01UL << TIMER3_IR_MR2INT_Pos) /*!< TIMER3 IR: MR2INT Mask */ +#define TIMER3_IR_MR3INT_Pos 3 /*!< TIMER3 IR: MR3INT Position */ +#define TIMER3_IR_MR3INT_Msk (0x01UL << TIMER3_IR_MR3INT_Pos) /*!< TIMER3 IR: MR3INT Mask */ +#define TIMER3_IR_CR0INT_Pos 4 /*!< TIMER3 IR: CR0INT Position */ +#define TIMER3_IR_CR0INT_Msk (0x01UL << TIMER3_IR_CR0INT_Pos) /*!< TIMER3 IR: CR0INT Mask */ +#define TIMER3_IR_CR1INT_Pos 5 /*!< TIMER3 IR: CR1INT Position */ +#define TIMER3_IR_CR1INT_Msk (0x01UL << TIMER3_IR_CR1INT_Pos) /*!< TIMER3 IR: CR1INT Mask */ +#define TIMER3_IR_CR2INT_Pos 6 /*!< TIMER3 IR: CR2INT Position */ +#define TIMER3_IR_CR2INT_Msk (0x01UL << TIMER3_IR_CR2INT_Pos) /*!< TIMER3 IR: CR2INT Mask */ +#define TIMER3_IR_CR3INT_Pos 7 /*!< TIMER3 IR: CR3INT Position */ +#define TIMER3_IR_CR3INT_Msk (0x01UL << TIMER3_IR_CR3INT_Pos) /*!< TIMER3 IR: CR3INT Mask */ + +/* --------------------------------- TIMER3_TCR --------------------------------- */ +#define TIMER3_TCR_CEN_Pos 0 /*!< TIMER3 TCR: CEN Position */ +#define TIMER3_TCR_CEN_Msk (0x01UL << TIMER3_TCR_CEN_Pos) /*!< TIMER3 TCR: CEN Mask */ +#define TIMER3_TCR_CRST_Pos 1 /*!< TIMER3 TCR: CRST Position */ +#define TIMER3_TCR_CRST_Msk (0x01UL << TIMER3_TCR_CRST_Pos) /*!< TIMER3 TCR: CRST Mask */ + +/* ---------------------------------- TIMER3_TC --------------------------------- */ +#define TIMER3_TC_TC_Pos 0 /*!< TIMER3 TC: TC Position */ +#define TIMER3_TC_TC_Msk (0xffffffffUL << TIMER3_TC_TC_Pos) /*!< TIMER3 TC: TC Mask */ + +/* ---------------------------------- TIMER3_PR --------------------------------- */ +#define TIMER3_PR_PM_Pos 0 /*!< TIMER3 PR: PM Position */ +#define TIMER3_PR_PM_Msk (0xffffffffUL << TIMER3_PR_PM_Pos) /*!< TIMER3 PR: PM Mask */ + +/* ---------------------------------- TIMER3_PC --------------------------------- */ +#define TIMER3_PC_PC_Pos 0 /*!< TIMER3 PC: PC Position */ +#define TIMER3_PC_PC_Msk (0xffffffffUL << TIMER3_PC_PC_Pos) /*!< TIMER3 PC: PC Mask */ + +/* --------------------------------- TIMER3_MCR --------------------------------- */ +#define TIMER3_MCR_MR0I_Pos 0 /*!< TIMER3 MCR: MR0I Position */ +#define TIMER3_MCR_MR0I_Msk (0x01UL << TIMER3_MCR_MR0I_Pos) /*!< TIMER3 MCR: MR0I Mask */ +#define TIMER3_MCR_MR0R_Pos 1 /*!< TIMER3 MCR: MR0R Position */ +#define TIMER3_MCR_MR0R_Msk (0x01UL << TIMER3_MCR_MR0R_Pos) /*!< TIMER3 MCR: MR0R Mask */ +#define TIMER3_MCR_MR0S_Pos 2 /*!< TIMER3 MCR: MR0S Position */ +#define TIMER3_MCR_MR0S_Msk (0x01UL << TIMER3_MCR_MR0S_Pos) /*!< TIMER3 MCR: MR0S Mask */ +#define TIMER3_MCR_MR1I_Pos 3 /*!< TIMER3 MCR: MR1I Position */ +#define TIMER3_MCR_MR1I_Msk (0x01UL << TIMER3_MCR_MR1I_Pos) /*!< TIMER3 MCR: MR1I Mask */ +#define TIMER3_MCR_MR1R_Pos 4 /*!< TIMER3 MCR: MR1R Position */ +#define TIMER3_MCR_MR1R_Msk (0x01UL << TIMER3_MCR_MR1R_Pos) /*!< TIMER3 MCR: MR1R Mask */ +#define TIMER3_MCR_MR1S_Pos 5 /*!< TIMER3 MCR: MR1S Position */ +#define TIMER3_MCR_MR1S_Msk (0x01UL << TIMER3_MCR_MR1S_Pos) /*!< TIMER3 MCR: MR1S Mask */ +#define TIMER3_MCR_MR2I_Pos 6 /*!< TIMER3 MCR: MR2I Position */ +#define TIMER3_MCR_MR2I_Msk (0x01UL << TIMER3_MCR_MR2I_Pos) /*!< TIMER3 MCR: MR2I Mask */ +#define TIMER3_MCR_MR2R_Pos 7 /*!< TIMER3 MCR: MR2R Position */ +#define TIMER3_MCR_MR2R_Msk (0x01UL << TIMER3_MCR_MR2R_Pos) /*!< TIMER3 MCR: MR2R Mask */ +#define TIMER3_MCR_MR2S_Pos 8 /*!< TIMER3 MCR: MR2S Position */ +#define TIMER3_MCR_MR2S_Msk (0x01UL << TIMER3_MCR_MR2S_Pos) /*!< TIMER3 MCR: MR2S Mask */ +#define TIMER3_MCR_MR3I_Pos 9 /*!< TIMER3 MCR: MR3I Position */ +#define TIMER3_MCR_MR3I_Msk (0x01UL << TIMER3_MCR_MR3I_Pos) /*!< TIMER3 MCR: MR3I Mask */ +#define TIMER3_MCR_MR3R_Pos 10 /*!< TIMER3 MCR: MR3R Position */ +#define TIMER3_MCR_MR3R_Msk (0x01UL << TIMER3_MCR_MR3R_Pos) /*!< TIMER3 MCR: MR3R Mask */ +#define TIMER3_MCR_MR3S_Pos 11 /*!< TIMER3 MCR: MR3S Position */ +#define TIMER3_MCR_MR3S_Msk (0x01UL << TIMER3_MCR_MR3S_Pos) /*!< TIMER3 MCR: MR3S Mask */ + +/* --------------------------------- TIMER3_MR0 --------------------------------- */ +#define TIMER3_MR0_MATCH_Pos 0 /*!< TIMER3 MR0: MATCH Position */ +#define TIMER3_MR0_MATCH_Msk (0xffffffffUL << TIMER3_MR0_MATCH_Pos) /*!< TIMER3 MR0: MATCH Mask */ + +/* --------------------------------- TIMER3_MR1 --------------------------------- */ +#define TIMER3_MR1_MATCH_Pos 0 /*!< TIMER3 MR1: MATCH Position */ +#define TIMER3_MR1_MATCH_Msk (0xffffffffUL << TIMER3_MR1_MATCH_Pos) /*!< TIMER3 MR1: MATCH Mask */ + +/* --------------------------------- TIMER3_MR2 --------------------------------- */ +#define TIMER3_MR2_MATCH_Pos 0 /*!< TIMER3 MR2: MATCH Position */ +#define TIMER3_MR2_MATCH_Msk (0xffffffffUL << TIMER3_MR2_MATCH_Pos) /*!< TIMER3 MR2: MATCH Mask */ + +/* --------------------------------- TIMER3_MR3 --------------------------------- */ +#define TIMER3_MR3_MATCH_Pos 0 /*!< TIMER3 MR3: MATCH Position */ +#define TIMER3_MR3_MATCH_Msk (0xffffffffUL << TIMER3_MR3_MATCH_Pos) /*!< TIMER3 MR3: MATCH Mask */ + +/* --------------------------------- TIMER3_CCR --------------------------------- */ +#define TIMER3_CCR_CAP0RE_Pos 0 /*!< TIMER3 CCR: CAP0RE Position */ +#define TIMER3_CCR_CAP0RE_Msk (0x01UL << TIMER3_CCR_CAP0RE_Pos) /*!< TIMER3 CCR: CAP0RE Mask */ +#define TIMER3_CCR_CAP0FE_Pos 1 /*!< TIMER3 CCR: CAP0FE Position */ +#define TIMER3_CCR_CAP0FE_Msk (0x01UL << TIMER3_CCR_CAP0FE_Pos) /*!< TIMER3 CCR: CAP0FE Mask */ +#define TIMER3_CCR_CAP0I_Pos 2 /*!< TIMER3 CCR: CAP0I Position */ +#define TIMER3_CCR_CAP0I_Msk (0x01UL << TIMER3_CCR_CAP0I_Pos) /*!< TIMER3 CCR: CAP0I Mask */ +#define TIMER3_CCR_CAP1RE_Pos 3 /*!< TIMER3 CCR: CAP1RE Position */ +#define TIMER3_CCR_CAP1RE_Msk (0x01UL << TIMER3_CCR_CAP1RE_Pos) /*!< TIMER3 CCR: CAP1RE Mask */ +#define TIMER3_CCR_CAP1FE_Pos 4 /*!< TIMER3 CCR: CAP1FE Position */ +#define TIMER3_CCR_CAP1FE_Msk (0x01UL << TIMER3_CCR_CAP1FE_Pos) /*!< TIMER3 CCR: CAP1FE Mask */ +#define TIMER3_CCR_CAP1I_Pos 5 /*!< TIMER3 CCR: CAP1I Position */ +#define TIMER3_CCR_CAP1I_Msk (0x01UL << TIMER3_CCR_CAP1I_Pos) /*!< TIMER3 CCR: CAP1I Mask */ +#define TIMER3_CCR_CAP2RE_Pos 6 /*!< TIMER3 CCR: CAP2RE Position */ +#define TIMER3_CCR_CAP2RE_Msk (0x01UL << TIMER3_CCR_CAP2RE_Pos) /*!< TIMER3 CCR: CAP2RE Mask */ +#define TIMER3_CCR_CAP2FE_Pos 7 /*!< TIMER3 CCR: CAP2FE Position */ +#define TIMER3_CCR_CAP2FE_Msk (0x01UL << TIMER3_CCR_CAP2FE_Pos) /*!< TIMER3 CCR: CAP2FE Mask */ +#define TIMER3_CCR_CAP2I_Pos 8 /*!< TIMER3 CCR: CAP2I Position */ +#define TIMER3_CCR_CAP2I_Msk (0x01UL << TIMER3_CCR_CAP2I_Pos) /*!< TIMER3 CCR: CAP2I Mask */ +#define TIMER3_CCR_CAP3RE_Pos 9 /*!< TIMER3 CCR: CAP3RE Position */ +#define TIMER3_CCR_CAP3RE_Msk (0x01UL << TIMER3_CCR_CAP3RE_Pos) /*!< TIMER3 CCR: CAP3RE Mask */ +#define TIMER3_CCR_CAP3FE_Pos 10 /*!< TIMER3 CCR: CAP3FE Position */ +#define TIMER3_CCR_CAP3FE_Msk (0x01UL << TIMER3_CCR_CAP3FE_Pos) /*!< TIMER3 CCR: CAP3FE Mask */ +#define TIMER3_CCR_CAP3I_Pos 11 /*!< TIMER3 CCR: CAP3I Position */ +#define TIMER3_CCR_CAP3I_Msk (0x01UL << TIMER3_CCR_CAP3I_Pos) /*!< TIMER3 CCR: CAP3I Mask */ + +/* --------------------------------- TIMER3_CR0 --------------------------------- */ +#define TIMER3_CR0_CAP_Pos 0 /*!< TIMER3 CR0: CAP Position */ +#define TIMER3_CR0_CAP_Msk (0xffffffffUL << TIMER3_CR0_CAP_Pos) /*!< TIMER3 CR0: CAP Mask */ + +/* --------------------------------- TIMER3_CR1 --------------------------------- */ +#define TIMER3_CR1_CAP_Pos 0 /*!< TIMER3 CR1: CAP Position */ +#define TIMER3_CR1_CAP_Msk (0xffffffffUL << TIMER3_CR1_CAP_Pos) /*!< TIMER3 CR1: CAP Mask */ + +/* --------------------------------- TIMER3_CR2 --------------------------------- */ +#define TIMER3_CR2_CAP_Pos 0 /*!< TIMER3 CR2: CAP Position */ +#define TIMER3_CR2_CAP_Msk (0xffffffffUL << TIMER3_CR2_CAP_Pos) /*!< TIMER3 CR2: CAP Mask */ + +/* --------------------------------- TIMER3_CR3 --------------------------------- */ +#define TIMER3_CR3_CAP_Pos 0 /*!< TIMER3 CR3: CAP Position */ +#define TIMER3_CR3_CAP_Msk (0xffffffffUL << TIMER3_CR3_CAP_Pos) /*!< TIMER3 CR3: CAP Mask */ + +/* --------------------------------- TIMER3_EMR --------------------------------- */ +#define TIMER3_EMR_EM0_Pos 0 /*!< TIMER3 EMR: EM0 Position */ +#define TIMER3_EMR_EM0_Msk (0x01UL << TIMER3_EMR_EM0_Pos) /*!< TIMER3 EMR: EM0 Mask */ +#define TIMER3_EMR_EM1_Pos 1 /*!< TIMER3 EMR: EM1 Position */ +#define TIMER3_EMR_EM1_Msk (0x01UL << TIMER3_EMR_EM1_Pos) /*!< TIMER3 EMR: EM1 Mask */ +#define TIMER3_EMR_EM2_Pos 2 /*!< TIMER3 EMR: EM2 Position */ +#define TIMER3_EMR_EM2_Msk (0x01UL << TIMER3_EMR_EM2_Pos) /*!< TIMER3 EMR: EM2 Mask */ +#define TIMER3_EMR_EM3_Pos 3 /*!< TIMER3 EMR: EM3 Position */ +#define TIMER3_EMR_EM3_Msk (0x01UL << TIMER3_EMR_EM3_Pos) /*!< TIMER3 EMR: EM3 Mask */ +#define TIMER3_EMR_EMC0_Pos 4 /*!< TIMER3 EMR: EMC0 Position */ +#define TIMER3_EMR_EMC0_Msk (0x03UL << TIMER3_EMR_EMC0_Pos) /*!< TIMER3 EMR: EMC0 Mask */ +#define TIMER3_EMR_EMC1_Pos 6 /*!< TIMER3 EMR: EMC1 Position */ +#define TIMER3_EMR_EMC1_Msk (0x03UL << TIMER3_EMR_EMC1_Pos) /*!< TIMER3 EMR: EMC1 Mask */ +#define TIMER3_EMR_EMC2_Pos 8 /*!< TIMER3 EMR: EMC2 Position */ +#define TIMER3_EMR_EMC2_Msk (0x03UL << TIMER3_EMR_EMC2_Pos) /*!< TIMER3 EMR: EMC2 Mask */ +#define TIMER3_EMR_EMC3_Pos 10 /*!< TIMER3 EMR: EMC3 Position */ +#define TIMER3_EMR_EMC3_Msk (0x03UL << TIMER3_EMR_EMC3_Pos) /*!< TIMER3 EMR: EMC3 Mask */ + +/* --------------------------------- TIMER3_CTCR -------------------------------- */ +#define TIMER3_CTCR_CTMODE_Pos 0 /*!< TIMER3 CTCR: CTMODE Position */ +#define TIMER3_CTCR_CTMODE_Msk (0x03UL << TIMER3_CTCR_CTMODE_Pos) /*!< TIMER3 CTCR: CTMODE Mask */ +#define TIMER3_CTCR_CINSEL_Pos 2 /*!< TIMER3 CTCR: CINSEL Position */ +#define TIMER3_CTCR_CINSEL_Msk (0x03UL << TIMER3_CTCR_CINSEL_Pos) /*!< TIMER3 CTCR: CINSEL Mask */ + + +/* ================================================================================ */ +/* ================ struct 'SCU' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- SCU_SFSP0_0 -------------------------------- */ +#define SCU_SFSP0_0_MODE_Pos 0 /*!< SCU SFSP0_0: MODE Position */ +#define SCU_SFSP0_0_MODE_Msk (0x07UL << SCU_SFSP0_0_MODE_Pos) /*!< SCU SFSP0_0: MODE Mask */ +#define SCU_SFSP0_0_EPD_Pos 3 /*!< SCU SFSP0_0: EPD Position */ +#define SCU_SFSP0_0_EPD_Msk (0x01UL << SCU_SFSP0_0_EPD_Pos) /*!< SCU SFSP0_0: EPD Mask */ +#define SCU_SFSP0_0_EPUN_Pos 4 /*!< SCU SFSP0_0: EPUN Position */ +#define SCU_SFSP0_0_EPUN_Msk (0x01UL << SCU_SFSP0_0_EPUN_Pos) /*!< SCU SFSP0_0: EPUN Mask */ +#define SCU_SFSP0_0_EHS_Pos 5 /*!< SCU SFSP0_0: EHS Position */ +#define SCU_SFSP0_0_EHS_Msk (0x01UL << SCU_SFSP0_0_EHS_Pos) /*!< SCU SFSP0_0: EHS Mask */ +#define SCU_SFSP0_0_EZI_Pos 6 /*!< SCU SFSP0_0: EZI Position */ +#define SCU_SFSP0_0_EZI_Msk (0x01UL << SCU_SFSP0_0_EZI_Pos) /*!< SCU SFSP0_0: EZI Mask */ +#define SCU_SFSP0_0_ZIF_Pos 7 /*!< SCU SFSP0_0: ZIF Position */ +#define SCU_SFSP0_0_ZIF_Msk (0x01UL << SCU_SFSP0_0_ZIF_Pos) /*!< SCU SFSP0_0: ZIF Mask */ + +/* --------------------------------- SCU_SFSP0_1 -------------------------------- */ +#define SCU_SFSP0_1_MODE_Pos 0 /*!< SCU SFSP0_1: MODE Position */ +#define SCU_SFSP0_1_MODE_Msk (0x07UL << SCU_SFSP0_1_MODE_Pos) /*!< SCU SFSP0_1: MODE Mask */ +#define SCU_SFSP0_1_EPD_Pos 3 /*!< SCU SFSP0_1: EPD Position */ +#define SCU_SFSP0_1_EPD_Msk (0x01UL << SCU_SFSP0_1_EPD_Pos) /*!< SCU SFSP0_1: EPD Mask */ +#define SCU_SFSP0_1_EPUN_Pos 4 /*!< SCU SFSP0_1: EPUN Position */ +#define SCU_SFSP0_1_EPUN_Msk (0x01UL << SCU_SFSP0_1_EPUN_Pos) /*!< SCU SFSP0_1: EPUN Mask */ +#define SCU_SFSP0_1_EHS_Pos 5 /*!< SCU SFSP0_1: EHS Position */ +#define SCU_SFSP0_1_EHS_Msk (0x01UL << SCU_SFSP0_1_EHS_Pos) /*!< SCU SFSP0_1: EHS Mask */ +#define SCU_SFSP0_1_EZI_Pos 6 /*!< SCU SFSP0_1: EZI Position */ +#define SCU_SFSP0_1_EZI_Msk (0x01UL << SCU_SFSP0_1_EZI_Pos) /*!< SCU SFSP0_1: EZI Mask */ +#define SCU_SFSP0_1_ZIF_Pos 7 /*!< SCU SFSP0_1: ZIF Position */ +#define SCU_SFSP0_1_ZIF_Msk (0x01UL << SCU_SFSP0_1_ZIF_Pos) /*!< SCU SFSP0_1: ZIF Mask */ + +/* --------------------------------- SCU_SFSP1_0 -------------------------------- */ +#define SCU_SFSP1_0_MODE_Pos 0 /*!< SCU SFSP1_0: MODE Position */ +#define SCU_SFSP1_0_MODE_Msk (0x07UL << SCU_SFSP1_0_MODE_Pos) /*!< SCU SFSP1_0: MODE Mask */ +#define SCU_SFSP1_0_EPD_Pos 3 /*!< SCU SFSP1_0: EPD Position */ +#define SCU_SFSP1_0_EPD_Msk (0x01UL << SCU_SFSP1_0_EPD_Pos) /*!< SCU SFSP1_0: EPD Mask */ +#define SCU_SFSP1_0_EPUN_Pos 4 /*!< SCU SFSP1_0: EPUN Position */ +#define SCU_SFSP1_0_EPUN_Msk (0x01UL << SCU_SFSP1_0_EPUN_Pos) /*!< SCU SFSP1_0: EPUN Mask */ +#define SCU_SFSP1_0_EHS_Pos 5 /*!< SCU SFSP1_0: EHS Position */ +#define SCU_SFSP1_0_EHS_Msk (0x01UL << SCU_SFSP1_0_EHS_Pos) /*!< SCU SFSP1_0: EHS Mask */ +#define SCU_SFSP1_0_EZI_Pos 6 /*!< SCU SFSP1_0: EZI Position */ +#define SCU_SFSP1_0_EZI_Msk (0x01UL << SCU_SFSP1_0_EZI_Pos) /*!< SCU SFSP1_0: EZI Mask */ +#define SCU_SFSP1_0_ZIF_Pos 7 /*!< SCU SFSP1_0: ZIF Position */ +#define SCU_SFSP1_0_ZIF_Msk (0x01UL << SCU_SFSP1_0_ZIF_Pos) /*!< SCU SFSP1_0: ZIF Mask */ + +/* --------------------------------- SCU_SFSP1_1 -------------------------------- */ +#define SCU_SFSP1_1_MODE_Pos 0 /*!< SCU SFSP1_1: MODE Position */ +#define SCU_SFSP1_1_MODE_Msk (0x07UL << SCU_SFSP1_1_MODE_Pos) /*!< SCU SFSP1_1: MODE Mask */ +#define SCU_SFSP1_1_EPD_Pos 3 /*!< SCU SFSP1_1: EPD Position */ +#define SCU_SFSP1_1_EPD_Msk (0x01UL << SCU_SFSP1_1_EPD_Pos) /*!< SCU SFSP1_1: EPD Mask */ +#define SCU_SFSP1_1_EPUN_Pos 4 /*!< SCU SFSP1_1: EPUN Position */ +#define SCU_SFSP1_1_EPUN_Msk (0x01UL << SCU_SFSP1_1_EPUN_Pos) /*!< SCU SFSP1_1: EPUN Mask */ +#define SCU_SFSP1_1_EHS_Pos 5 /*!< SCU SFSP1_1: EHS Position */ +#define SCU_SFSP1_1_EHS_Msk (0x01UL << SCU_SFSP1_1_EHS_Pos) /*!< SCU SFSP1_1: EHS Mask */ +#define SCU_SFSP1_1_EZI_Pos 6 /*!< SCU SFSP1_1: EZI Position */ +#define SCU_SFSP1_1_EZI_Msk (0x01UL << SCU_SFSP1_1_EZI_Pos) /*!< SCU SFSP1_1: EZI Mask */ +#define SCU_SFSP1_1_ZIF_Pos 7 /*!< SCU SFSP1_1: ZIF Position */ +#define SCU_SFSP1_1_ZIF_Msk (0x01UL << SCU_SFSP1_1_ZIF_Pos) /*!< SCU SFSP1_1: ZIF Mask */ + +/* --------------------------------- SCU_SFSP1_2 -------------------------------- */ +#define SCU_SFSP1_2_MODE_Pos 0 /*!< SCU SFSP1_2: MODE Position */ +#define SCU_SFSP1_2_MODE_Msk (0x07UL << SCU_SFSP1_2_MODE_Pos) /*!< SCU SFSP1_2: MODE Mask */ +#define SCU_SFSP1_2_EPD_Pos 3 /*!< SCU SFSP1_2: EPD Position */ +#define SCU_SFSP1_2_EPD_Msk (0x01UL << SCU_SFSP1_2_EPD_Pos) /*!< SCU SFSP1_2: EPD Mask */ +#define SCU_SFSP1_2_EPUN_Pos 4 /*!< SCU SFSP1_2: EPUN Position */ +#define SCU_SFSP1_2_EPUN_Msk (0x01UL << SCU_SFSP1_2_EPUN_Pos) /*!< SCU SFSP1_2: EPUN Mask */ +#define SCU_SFSP1_2_EHS_Pos 5 /*!< SCU SFSP1_2: EHS Position */ +#define SCU_SFSP1_2_EHS_Msk (0x01UL << SCU_SFSP1_2_EHS_Pos) /*!< SCU SFSP1_2: EHS Mask */ +#define SCU_SFSP1_2_EZI_Pos 6 /*!< SCU SFSP1_2: EZI Position */ +#define SCU_SFSP1_2_EZI_Msk (0x01UL << SCU_SFSP1_2_EZI_Pos) /*!< SCU SFSP1_2: EZI Mask */ +#define SCU_SFSP1_2_ZIF_Pos 7 /*!< SCU SFSP1_2: ZIF Position */ +#define SCU_SFSP1_2_ZIF_Msk (0x01UL << SCU_SFSP1_2_ZIF_Pos) /*!< SCU SFSP1_2: ZIF Mask */ + +/* --------------------------------- SCU_SFSP1_3 -------------------------------- */ +#define SCU_SFSP1_3_MODE_Pos 0 /*!< SCU SFSP1_3: MODE Position */ +#define SCU_SFSP1_3_MODE_Msk (0x07UL << SCU_SFSP1_3_MODE_Pos) /*!< SCU SFSP1_3: MODE Mask */ +#define SCU_SFSP1_3_EPD_Pos 3 /*!< SCU SFSP1_3: EPD Position */ +#define SCU_SFSP1_3_EPD_Msk (0x01UL << SCU_SFSP1_3_EPD_Pos) /*!< SCU SFSP1_3: EPD Mask */ +#define SCU_SFSP1_3_EPUN_Pos 4 /*!< SCU SFSP1_3: EPUN Position */ +#define SCU_SFSP1_3_EPUN_Msk (0x01UL << SCU_SFSP1_3_EPUN_Pos) /*!< SCU SFSP1_3: EPUN Mask */ +#define SCU_SFSP1_3_EHS_Pos 5 /*!< SCU SFSP1_3: EHS Position */ +#define SCU_SFSP1_3_EHS_Msk (0x01UL << SCU_SFSP1_3_EHS_Pos) /*!< SCU SFSP1_3: EHS Mask */ +#define SCU_SFSP1_3_EZI_Pos 6 /*!< SCU SFSP1_3: EZI Position */ +#define SCU_SFSP1_3_EZI_Msk (0x01UL << SCU_SFSP1_3_EZI_Pos) /*!< SCU SFSP1_3: EZI Mask */ +#define SCU_SFSP1_3_ZIF_Pos 7 /*!< SCU SFSP1_3: ZIF Position */ +#define SCU_SFSP1_3_ZIF_Msk (0x01UL << SCU_SFSP1_3_ZIF_Pos) /*!< SCU SFSP1_3: ZIF Mask */ + +/* --------------------------------- SCU_SFSP1_4 -------------------------------- */ +#define SCU_SFSP1_4_MODE_Pos 0 /*!< SCU SFSP1_4: MODE Position */ +#define SCU_SFSP1_4_MODE_Msk (0x07UL << SCU_SFSP1_4_MODE_Pos) /*!< SCU SFSP1_4: MODE Mask */ +#define SCU_SFSP1_4_EPD_Pos 3 /*!< SCU SFSP1_4: EPD Position */ +#define SCU_SFSP1_4_EPD_Msk (0x01UL << SCU_SFSP1_4_EPD_Pos) /*!< SCU SFSP1_4: EPD Mask */ +#define SCU_SFSP1_4_EPUN_Pos 4 /*!< SCU SFSP1_4: EPUN Position */ +#define SCU_SFSP1_4_EPUN_Msk (0x01UL << SCU_SFSP1_4_EPUN_Pos) /*!< SCU SFSP1_4: EPUN Mask */ +#define SCU_SFSP1_4_EHS_Pos 5 /*!< SCU SFSP1_4: EHS Position */ +#define SCU_SFSP1_4_EHS_Msk (0x01UL << SCU_SFSP1_4_EHS_Pos) /*!< SCU SFSP1_4: EHS Mask */ +#define SCU_SFSP1_4_EZI_Pos 6 /*!< SCU SFSP1_4: EZI Position */ +#define SCU_SFSP1_4_EZI_Msk (0x01UL << SCU_SFSP1_4_EZI_Pos) /*!< SCU SFSP1_4: EZI Mask */ +#define SCU_SFSP1_4_ZIF_Pos 7 /*!< SCU SFSP1_4: ZIF Position */ +#define SCU_SFSP1_4_ZIF_Msk (0x01UL << SCU_SFSP1_4_ZIF_Pos) /*!< SCU SFSP1_4: ZIF Mask */ + +/* --------------------------------- SCU_SFSP1_5 -------------------------------- */ +#define SCU_SFSP1_5_MODE_Pos 0 /*!< SCU SFSP1_5: MODE Position */ +#define SCU_SFSP1_5_MODE_Msk (0x07UL << SCU_SFSP1_5_MODE_Pos) /*!< SCU SFSP1_5: MODE Mask */ +#define SCU_SFSP1_5_EPD_Pos 3 /*!< SCU SFSP1_5: EPD Position */ +#define SCU_SFSP1_5_EPD_Msk (0x01UL << SCU_SFSP1_5_EPD_Pos) /*!< SCU SFSP1_5: EPD Mask */ +#define SCU_SFSP1_5_EPUN_Pos 4 /*!< SCU SFSP1_5: EPUN Position */ +#define SCU_SFSP1_5_EPUN_Msk (0x01UL << SCU_SFSP1_5_EPUN_Pos) /*!< SCU SFSP1_5: EPUN Mask */ +#define SCU_SFSP1_5_EHS_Pos 5 /*!< SCU SFSP1_5: EHS Position */ +#define SCU_SFSP1_5_EHS_Msk (0x01UL << SCU_SFSP1_5_EHS_Pos) /*!< SCU SFSP1_5: EHS Mask */ +#define SCU_SFSP1_5_EZI_Pos 6 /*!< SCU SFSP1_5: EZI Position */ +#define SCU_SFSP1_5_EZI_Msk (0x01UL << SCU_SFSP1_5_EZI_Pos) /*!< SCU SFSP1_5: EZI Mask */ +#define SCU_SFSP1_5_ZIF_Pos 7 /*!< SCU SFSP1_5: ZIF Position */ +#define SCU_SFSP1_5_ZIF_Msk (0x01UL << SCU_SFSP1_5_ZIF_Pos) /*!< SCU SFSP1_5: ZIF Mask */ + +/* --------------------------------- SCU_SFSP1_6 -------------------------------- */ +#define SCU_SFSP1_6_MODE_Pos 0 /*!< SCU SFSP1_6: MODE Position */ +#define SCU_SFSP1_6_MODE_Msk (0x07UL << SCU_SFSP1_6_MODE_Pos) /*!< SCU SFSP1_6: MODE Mask */ +#define SCU_SFSP1_6_EPD_Pos 3 /*!< SCU SFSP1_6: EPD Position */ +#define SCU_SFSP1_6_EPD_Msk (0x01UL << SCU_SFSP1_6_EPD_Pos) /*!< SCU SFSP1_6: EPD Mask */ +#define SCU_SFSP1_6_EPUN_Pos 4 /*!< SCU SFSP1_6: EPUN Position */ +#define SCU_SFSP1_6_EPUN_Msk (0x01UL << SCU_SFSP1_6_EPUN_Pos) /*!< SCU SFSP1_6: EPUN Mask */ +#define SCU_SFSP1_6_EHS_Pos 5 /*!< SCU SFSP1_6: EHS Position */ +#define SCU_SFSP1_6_EHS_Msk (0x01UL << SCU_SFSP1_6_EHS_Pos) /*!< SCU SFSP1_6: EHS Mask */ +#define SCU_SFSP1_6_EZI_Pos 6 /*!< SCU SFSP1_6: EZI Position */ +#define SCU_SFSP1_6_EZI_Msk (0x01UL << SCU_SFSP1_6_EZI_Pos) /*!< SCU SFSP1_6: EZI Mask */ +#define SCU_SFSP1_6_ZIF_Pos 7 /*!< SCU SFSP1_6: ZIF Position */ +#define SCU_SFSP1_6_ZIF_Msk (0x01UL << SCU_SFSP1_6_ZIF_Pos) /*!< SCU SFSP1_6: ZIF Mask */ + +/* --------------------------------- SCU_SFSP1_7 -------------------------------- */ +#define SCU_SFSP1_7_MODE_Pos 0 /*!< SCU SFSP1_7: MODE Position */ +#define SCU_SFSP1_7_MODE_Msk (0x07UL << SCU_SFSP1_7_MODE_Pos) /*!< SCU SFSP1_7: MODE Mask */ +#define SCU_SFSP1_7_EPD_Pos 3 /*!< SCU SFSP1_7: EPD Position */ +#define SCU_SFSP1_7_EPD_Msk (0x01UL << SCU_SFSP1_7_EPD_Pos) /*!< SCU SFSP1_7: EPD Mask */ +#define SCU_SFSP1_7_EPUN_Pos 4 /*!< SCU SFSP1_7: EPUN Position */ +#define SCU_SFSP1_7_EPUN_Msk (0x01UL << SCU_SFSP1_7_EPUN_Pos) /*!< SCU SFSP1_7: EPUN Mask */ +#define SCU_SFSP1_7_EHS_Pos 5 /*!< SCU SFSP1_7: EHS Position */ +#define SCU_SFSP1_7_EHS_Msk (0x01UL << SCU_SFSP1_7_EHS_Pos) /*!< SCU SFSP1_7: EHS Mask */ +#define SCU_SFSP1_7_EZI_Pos 6 /*!< SCU SFSP1_7: EZI Position */ +#define SCU_SFSP1_7_EZI_Msk (0x01UL << SCU_SFSP1_7_EZI_Pos) /*!< SCU SFSP1_7: EZI Mask */ +#define SCU_SFSP1_7_ZIF_Pos 7 /*!< SCU SFSP1_7: ZIF Position */ +#define SCU_SFSP1_7_ZIF_Msk (0x01UL << SCU_SFSP1_7_ZIF_Pos) /*!< SCU SFSP1_7: ZIF Mask */ + +/* --------------------------------- SCU_SFSP1_8 -------------------------------- */ +#define SCU_SFSP1_8_MODE_Pos 0 /*!< SCU SFSP1_8: MODE Position */ +#define SCU_SFSP1_8_MODE_Msk (0x07UL << SCU_SFSP1_8_MODE_Pos) /*!< SCU SFSP1_8: MODE Mask */ +#define SCU_SFSP1_8_EPD_Pos 3 /*!< SCU SFSP1_8: EPD Position */ +#define SCU_SFSP1_8_EPD_Msk (0x01UL << SCU_SFSP1_8_EPD_Pos) /*!< SCU SFSP1_8: EPD Mask */ +#define SCU_SFSP1_8_EPUN_Pos 4 /*!< SCU SFSP1_8: EPUN Position */ +#define SCU_SFSP1_8_EPUN_Msk (0x01UL << SCU_SFSP1_8_EPUN_Pos) /*!< SCU SFSP1_8: EPUN Mask */ +#define SCU_SFSP1_8_EHS_Pos 5 /*!< SCU SFSP1_8: EHS Position */ +#define SCU_SFSP1_8_EHS_Msk (0x01UL << SCU_SFSP1_8_EHS_Pos) /*!< SCU SFSP1_8: EHS Mask */ +#define SCU_SFSP1_8_EZI_Pos 6 /*!< SCU SFSP1_8: EZI Position */ +#define SCU_SFSP1_8_EZI_Msk (0x01UL << SCU_SFSP1_8_EZI_Pos) /*!< SCU SFSP1_8: EZI Mask */ +#define SCU_SFSP1_8_ZIF_Pos 7 /*!< SCU SFSP1_8: ZIF Position */ +#define SCU_SFSP1_8_ZIF_Msk (0x01UL << SCU_SFSP1_8_ZIF_Pos) /*!< SCU SFSP1_8: ZIF Mask */ + +/* --------------------------------- SCU_SFSP1_9 -------------------------------- */ +#define SCU_SFSP1_9_MODE_Pos 0 /*!< SCU SFSP1_9: MODE Position */ +#define SCU_SFSP1_9_MODE_Msk (0x07UL << SCU_SFSP1_9_MODE_Pos) /*!< SCU SFSP1_9: MODE Mask */ +#define SCU_SFSP1_9_EPD_Pos 3 /*!< SCU SFSP1_9: EPD Position */ +#define SCU_SFSP1_9_EPD_Msk (0x01UL << SCU_SFSP1_9_EPD_Pos) /*!< SCU SFSP1_9: EPD Mask */ +#define SCU_SFSP1_9_EPUN_Pos 4 /*!< SCU SFSP1_9: EPUN Position */ +#define SCU_SFSP1_9_EPUN_Msk (0x01UL << SCU_SFSP1_9_EPUN_Pos) /*!< SCU SFSP1_9: EPUN Mask */ +#define SCU_SFSP1_9_EHS_Pos 5 /*!< SCU SFSP1_9: EHS Position */ +#define SCU_SFSP1_9_EHS_Msk (0x01UL << SCU_SFSP1_9_EHS_Pos) /*!< SCU SFSP1_9: EHS Mask */ +#define SCU_SFSP1_9_EZI_Pos 6 /*!< SCU SFSP1_9: EZI Position */ +#define SCU_SFSP1_9_EZI_Msk (0x01UL << SCU_SFSP1_9_EZI_Pos) /*!< SCU SFSP1_9: EZI Mask */ +#define SCU_SFSP1_9_ZIF_Pos 7 /*!< SCU SFSP1_9: ZIF Position */ +#define SCU_SFSP1_9_ZIF_Msk (0x01UL << SCU_SFSP1_9_ZIF_Pos) /*!< SCU SFSP1_9: ZIF Mask */ + +/* -------------------------------- SCU_SFSP1_10 -------------------------------- */ +#define SCU_SFSP1_10_MODE_Pos 0 /*!< SCU SFSP1_10: MODE Position */ +#define SCU_SFSP1_10_MODE_Msk (0x07UL << SCU_SFSP1_10_MODE_Pos) /*!< SCU SFSP1_10: MODE Mask */ +#define SCU_SFSP1_10_EPD_Pos 3 /*!< SCU SFSP1_10: EPD Position */ +#define SCU_SFSP1_10_EPD_Msk (0x01UL << SCU_SFSP1_10_EPD_Pos) /*!< SCU SFSP1_10: EPD Mask */ +#define SCU_SFSP1_10_EPUN_Pos 4 /*!< SCU SFSP1_10: EPUN Position */ +#define SCU_SFSP1_10_EPUN_Msk (0x01UL << SCU_SFSP1_10_EPUN_Pos) /*!< SCU SFSP1_10: EPUN Mask */ +#define SCU_SFSP1_10_EHS_Pos 5 /*!< SCU SFSP1_10: EHS Position */ +#define SCU_SFSP1_10_EHS_Msk (0x01UL << SCU_SFSP1_10_EHS_Pos) /*!< SCU SFSP1_10: EHS Mask */ +#define SCU_SFSP1_10_EZI_Pos 6 /*!< SCU SFSP1_10: EZI Position */ +#define SCU_SFSP1_10_EZI_Msk (0x01UL << SCU_SFSP1_10_EZI_Pos) /*!< SCU SFSP1_10: EZI Mask */ +#define SCU_SFSP1_10_ZIF_Pos 7 /*!< SCU SFSP1_10: ZIF Position */ +#define SCU_SFSP1_10_ZIF_Msk (0x01UL << SCU_SFSP1_10_ZIF_Pos) /*!< SCU SFSP1_10: ZIF Mask */ + +/* -------------------------------- SCU_SFSP1_11 -------------------------------- */ +#define SCU_SFSP1_11_MODE_Pos 0 /*!< SCU SFSP1_11: MODE Position */ +#define SCU_SFSP1_11_MODE_Msk (0x07UL << SCU_SFSP1_11_MODE_Pos) /*!< SCU SFSP1_11: MODE Mask */ +#define SCU_SFSP1_11_EPD_Pos 3 /*!< SCU SFSP1_11: EPD Position */ +#define SCU_SFSP1_11_EPD_Msk (0x01UL << SCU_SFSP1_11_EPD_Pos) /*!< SCU SFSP1_11: EPD Mask */ +#define SCU_SFSP1_11_EPUN_Pos 4 /*!< SCU SFSP1_11: EPUN Position */ +#define SCU_SFSP1_11_EPUN_Msk (0x01UL << SCU_SFSP1_11_EPUN_Pos) /*!< SCU SFSP1_11: EPUN Mask */ +#define SCU_SFSP1_11_EHS_Pos 5 /*!< SCU SFSP1_11: EHS Position */ +#define SCU_SFSP1_11_EHS_Msk (0x01UL << SCU_SFSP1_11_EHS_Pos) /*!< SCU SFSP1_11: EHS Mask */ +#define SCU_SFSP1_11_EZI_Pos 6 /*!< SCU SFSP1_11: EZI Position */ +#define SCU_SFSP1_11_EZI_Msk (0x01UL << SCU_SFSP1_11_EZI_Pos) /*!< SCU SFSP1_11: EZI Mask */ +#define SCU_SFSP1_11_ZIF_Pos 7 /*!< SCU SFSP1_11: ZIF Position */ +#define SCU_SFSP1_11_ZIF_Msk (0x01UL << SCU_SFSP1_11_ZIF_Pos) /*!< SCU SFSP1_11: ZIF Mask */ + +/* -------------------------------- SCU_SFSP1_12 -------------------------------- */ +#define SCU_SFSP1_12_MODE_Pos 0 /*!< SCU SFSP1_12: MODE Position */ +#define SCU_SFSP1_12_MODE_Msk (0x07UL << SCU_SFSP1_12_MODE_Pos) /*!< SCU SFSP1_12: MODE Mask */ +#define SCU_SFSP1_12_EPD_Pos 3 /*!< SCU SFSP1_12: EPD Position */ +#define SCU_SFSP1_12_EPD_Msk (0x01UL << SCU_SFSP1_12_EPD_Pos) /*!< SCU SFSP1_12: EPD Mask */ +#define SCU_SFSP1_12_EPUN_Pos 4 /*!< SCU SFSP1_12: EPUN Position */ +#define SCU_SFSP1_12_EPUN_Msk (0x01UL << SCU_SFSP1_12_EPUN_Pos) /*!< SCU SFSP1_12: EPUN Mask */ +#define SCU_SFSP1_12_EHS_Pos 5 /*!< SCU SFSP1_12: EHS Position */ +#define SCU_SFSP1_12_EHS_Msk (0x01UL << SCU_SFSP1_12_EHS_Pos) /*!< SCU SFSP1_12: EHS Mask */ +#define SCU_SFSP1_12_EZI_Pos 6 /*!< SCU SFSP1_12: EZI Position */ +#define SCU_SFSP1_12_EZI_Msk (0x01UL << SCU_SFSP1_12_EZI_Pos) /*!< SCU SFSP1_12: EZI Mask */ +#define SCU_SFSP1_12_ZIF_Pos 7 /*!< SCU SFSP1_12: ZIF Position */ +#define SCU_SFSP1_12_ZIF_Msk (0x01UL << SCU_SFSP1_12_ZIF_Pos) /*!< SCU SFSP1_12: ZIF Mask */ + +/* -------------------------------- SCU_SFSP1_13 -------------------------------- */ +#define SCU_SFSP1_13_MODE_Pos 0 /*!< SCU SFSP1_13: MODE Position */ +#define SCU_SFSP1_13_MODE_Msk (0x07UL << SCU_SFSP1_13_MODE_Pos) /*!< SCU SFSP1_13: MODE Mask */ +#define SCU_SFSP1_13_EPD_Pos 3 /*!< SCU SFSP1_13: EPD Position */ +#define SCU_SFSP1_13_EPD_Msk (0x01UL << SCU_SFSP1_13_EPD_Pos) /*!< SCU SFSP1_13: EPD Mask */ +#define SCU_SFSP1_13_EPUN_Pos 4 /*!< SCU SFSP1_13: EPUN Position */ +#define SCU_SFSP1_13_EPUN_Msk (0x01UL << SCU_SFSP1_13_EPUN_Pos) /*!< SCU SFSP1_13: EPUN Mask */ +#define SCU_SFSP1_13_EHS_Pos 5 /*!< SCU SFSP1_13: EHS Position */ +#define SCU_SFSP1_13_EHS_Msk (0x01UL << SCU_SFSP1_13_EHS_Pos) /*!< SCU SFSP1_13: EHS Mask */ +#define SCU_SFSP1_13_EZI_Pos 6 /*!< SCU SFSP1_13: EZI Position */ +#define SCU_SFSP1_13_EZI_Msk (0x01UL << SCU_SFSP1_13_EZI_Pos) /*!< SCU SFSP1_13: EZI Mask */ +#define SCU_SFSP1_13_ZIF_Pos 7 /*!< SCU SFSP1_13: ZIF Position */ +#define SCU_SFSP1_13_ZIF_Msk (0x01UL << SCU_SFSP1_13_ZIF_Pos) /*!< SCU SFSP1_13: ZIF Mask */ + +/* -------------------------------- SCU_SFSP1_14 -------------------------------- */ +#define SCU_SFSP1_14_MODE_Pos 0 /*!< SCU SFSP1_14: MODE Position */ +#define SCU_SFSP1_14_MODE_Msk (0x07UL << SCU_SFSP1_14_MODE_Pos) /*!< SCU SFSP1_14: MODE Mask */ +#define SCU_SFSP1_14_EPD_Pos 3 /*!< SCU SFSP1_14: EPD Position */ +#define SCU_SFSP1_14_EPD_Msk (0x01UL << SCU_SFSP1_14_EPD_Pos) /*!< SCU SFSP1_14: EPD Mask */ +#define SCU_SFSP1_14_EPUN_Pos 4 /*!< SCU SFSP1_14: EPUN Position */ +#define SCU_SFSP1_14_EPUN_Msk (0x01UL << SCU_SFSP1_14_EPUN_Pos) /*!< SCU SFSP1_14: EPUN Mask */ +#define SCU_SFSP1_14_EHS_Pos 5 /*!< SCU SFSP1_14: EHS Position */ +#define SCU_SFSP1_14_EHS_Msk (0x01UL << SCU_SFSP1_14_EHS_Pos) /*!< SCU SFSP1_14: EHS Mask */ +#define SCU_SFSP1_14_EZI_Pos 6 /*!< SCU SFSP1_14: EZI Position */ +#define SCU_SFSP1_14_EZI_Msk (0x01UL << SCU_SFSP1_14_EZI_Pos) /*!< SCU SFSP1_14: EZI Mask */ +#define SCU_SFSP1_14_ZIF_Pos 7 /*!< SCU SFSP1_14: ZIF Position */ +#define SCU_SFSP1_14_ZIF_Msk (0x01UL << SCU_SFSP1_14_ZIF_Pos) /*!< SCU SFSP1_14: ZIF Mask */ + +/* -------------------------------- SCU_SFSP1_15 -------------------------------- */ +#define SCU_SFSP1_15_MODE_Pos 0 /*!< SCU SFSP1_15: MODE Position */ +#define SCU_SFSP1_15_MODE_Msk (0x07UL << SCU_SFSP1_15_MODE_Pos) /*!< SCU SFSP1_15: MODE Mask */ +#define SCU_SFSP1_15_EPD_Pos 3 /*!< SCU SFSP1_15: EPD Position */ +#define SCU_SFSP1_15_EPD_Msk (0x01UL << SCU_SFSP1_15_EPD_Pos) /*!< SCU SFSP1_15: EPD Mask */ +#define SCU_SFSP1_15_EPUN_Pos 4 /*!< SCU SFSP1_15: EPUN Position */ +#define SCU_SFSP1_15_EPUN_Msk (0x01UL << SCU_SFSP1_15_EPUN_Pos) /*!< SCU SFSP1_15: EPUN Mask */ +#define SCU_SFSP1_15_EHS_Pos 5 /*!< SCU SFSP1_15: EHS Position */ +#define SCU_SFSP1_15_EHS_Msk (0x01UL << SCU_SFSP1_15_EHS_Pos) /*!< SCU SFSP1_15: EHS Mask */ +#define SCU_SFSP1_15_EZI_Pos 6 /*!< SCU SFSP1_15: EZI Position */ +#define SCU_SFSP1_15_EZI_Msk (0x01UL << SCU_SFSP1_15_EZI_Pos) /*!< SCU SFSP1_15: EZI Mask */ +#define SCU_SFSP1_15_ZIF_Pos 7 /*!< SCU SFSP1_15: ZIF Position */ +#define SCU_SFSP1_15_ZIF_Msk (0x01UL << SCU_SFSP1_15_ZIF_Pos) /*!< SCU SFSP1_15: ZIF Mask */ + +/* -------------------------------- SCU_SFSP1_16 -------------------------------- */ +#define SCU_SFSP1_16_MODE_Pos 0 /*!< SCU SFSP1_16: MODE Position */ +#define SCU_SFSP1_16_MODE_Msk (0x07UL << SCU_SFSP1_16_MODE_Pos) /*!< SCU SFSP1_16: MODE Mask */ +#define SCU_SFSP1_16_EPD_Pos 3 /*!< SCU SFSP1_16: EPD Position */ +#define SCU_SFSP1_16_EPD_Msk (0x01UL << SCU_SFSP1_16_EPD_Pos) /*!< SCU SFSP1_16: EPD Mask */ +#define SCU_SFSP1_16_EPUN_Pos 4 /*!< SCU SFSP1_16: EPUN Position */ +#define SCU_SFSP1_16_EPUN_Msk (0x01UL << SCU_SFSP1_16_EPUN_Pos) /*!< SCU SFSP1_16: EPUN Mask */ +#define SCU_SFSP1_16_EHS_Pos 5 /*!< SCU SFSP1_16: EHS Position */ +#define SCU_SFSP1_16_EHS_Msk (0x01UL << SCU_SFSP1_16_EHS_Pos) /*!< SCU SFSP1_16: EHS Mask */ +#define SCU_SFSP1_16_EZI_Pos 6 /*!< SCU SFSP1_16: EZI Position */ +#define SCU_SFSP1_16_EZI_Msk (0x01UL << SCU_SFSP1_16_EZI_Pos) /*!< SCU SFSP1_16: EZI Mask */ +#define SCU_SFSP1_16_ZIF_Pos 7 /*!< SCU SFSP1_16: ZIF Position */ +#define SCU_SFSP1_16_ZIF_Msk (0x01UL << SCU_SFSP1_16_ZIF_Pos) /*!< SCU SFSP1_16: ZIF Mask */ + +/* -------------------------------- SCU_SFSP1_17 -------------------------------- */ +#define SCU_SFSP1_17_MODE_Pos 0 /*!< SCU SFSP1_17: MODE Position */ +#define SCU_SFSP1_17_MODE_Msk (0x07UL << SCU_SFSP1_17_MODE_Pos) /*!< SCU SFSP1_17: MODE Mask */ +#define SCU_SFSP1_17_EPD_Pos 3 /*!< SCU SFSP1_17: EPD Position */ +#define SCU_SFSP1_17_EPD_Msk (0x01UL << SCU_SFSP1_17_EPD_Pos) /*!< SCU SFSP1_17: EPD Mask */ +#define SCU_SFSP1_17_EPUN_Pos 4 /*!< SCU SFSP1_17: EPUN Position */ +#define SCU_SFSP1_17_EPUN_Msk (0x01UL << SCU_SFSP1_17_EPUN_Pos) /*!< SCU SFSP1_17: EPUN Mask */ +#define SCU_SFSP1_17_EZI_Pos 6 /*!< SCU SFSP1_17: EZI Position */ +#define SCU_SFSP1_17_EZI_Msk (0x01UL << SCU_SFSP1_17_EZI_Pos) /*!< SCU SFSP1_17: EZI Mask */ +#define SCU_SFSP1_17_ZIF_Pos 7 /*!< SCU SFSP1_17: ZIF Position */ +#define SCU_SFSP1_17_ZIF_Msk (0x01UL << SCU_SFSP1_17_ZIF_Pos) /*!< SCU SFSP1_17: ZIF Mask */ +#define SCU_SFSP1_17_EHD_Pos 8 /*!< SCU SFSP1_17: EHD Position */ +#define SCU_SFSP1_17_EHD_Msk (0x03UL << SCU_SFSP1_17_EHD_Pos) /*!< SCU SFSP1_17: EHD Mask */ + +/* -------------------------------- SCU_SFSP1_18 -------------------------------- */ +#define SCU_SFSP1_18_MODE_Pos 0 /*!< SCU SFSP1_18: MODE Position */ +#define SCU_SFSP1_18_MODE_Msk (0x07UL << SCU_SFSP1_18_MODE_Pos) /*!< SCU SFSP1_18: MODE Mask */ +#define SCU_SFSP1_18_EPD_Pos 3 /*!< SCU SFSP1_18: EPD Position */ +#define SCU_SFSP1_18_EPD_Msk (0x01UL << SCU_SFSP1_18_EPD_Pos) /*!< SCU SFSP1_18: EPD Mask */ +#define SCU_SFSP1_18_EPUN_Pos 4 /*!< SCU SFSP1_18: EPUN Position */ +#define SCU_SFSP1_18_EPUN_Msk (0x01UL << SCU_SFSP1_18_EPUN_Pos) /*!< SCU SFSP1_18: EPUN Mask */ +#define SCU_SFSP1_18_EHS_Pos 5 /*!< SCU SFSP1_18: EHS Position */ +#define SCU_SFSP1_18_EHS_Msk (0x01UL << SCU_SFSP1_18_EHS_Pos) /*!< SCU SFSP1_18: EHS Mask */ +#define SCU_SFSP1_18_EZI_Pos 6 /*!< SCU SFSP1_18: EZI Position */ +#define SCU_SFSP1_18_EZI_Msk (0x01UL << SCU_SFSP1_18_EZI_Pos) /*!< SCU SFSP1_18: EZI Mask */ +#define SCU_SFSP1_18_ZIF_Pos 7 /*!< SCU SFSP1_18: ZIF Position */ +#define SCU_SFSP1_18_ZIF_Msk (0x01UL << SCU_SFSP1_18_ZIF_Pos) /*!< SCU SFSP1_18: ZIF Mask */ + +/* -------------------------------- SCU_SFSP1_19 -------------------------------- */ +#define SCU_SFSP1_19_MODE_Pos 0 /*!< SCU SFSP1_19: MODE Position */ +#define SCU_SFSP1_19_MODE_Msk (0x07UL << SCU_SFSP1_19_MODE_Pos) /*!< SCU SFSP1_19: MODE Mask */ +#define SCU_SFSP1_19_EPD_Pos 3 /*!< SCU SFSP1_19: EPD Position */ +#define SCU_SFSP1_19_EPD_Msk (0x01UL << SCU_SFSP1_19_EPD_Pos) /*!< SCU SFSP1_19: EPD Mask */ +#define SCU_SFSP1_19_EPUN_Pos 4 /*!< SCU SFSP1_19: EPUN Position */ +#define SCU_SFSP1_19_EPUN_Msk (0x01UL << SCU_SFSP1_19_EPUN_Pos) /*!< SCU SFSP1_19: EPUN Mask */ +#define SCU_SFSP1_19_EHS_Pos 5 /*!< SCU SFSP1_19: EHS Position */ +#define SCU_SFSP1_19_EHS_Msk (0x01UL << SCU_SFSP1_19_EHS_Pos) /*!< SCU SFSP1_19: EHS Mask */ +#define SCU_SFSP1_19_EZI_Pos 6 /*!< SCU SFSP1_19: EZI Position */ +#define SCU_SFSP1_19_EZI_Msk (0x01UL << SCU_SFSP1_19_EZI_Pos) /*!< SCU SFSP1_19: EZI Mask */ +#define SCU_SFSP1_19_ZIF_Pos 7 /*!< SCU SFSP1_19: ZIF Position */ +#define SCU_SFSP1_19_ZIF_Msk (0x01UL << SCU_SFSP1_19_ZIF_Pos) /*!< SCU SFSP1_19: ZIF Mask */ + +/* -------------------------------- SCU_SFSP1_20 -------------------------------- */ +#define SCU_SFSP1_20_MODE_Pos 0 /*!< SCU SFSP1_20: MODE Position */ +#define SCU_SFSP1_20_MODE_Msk (0x07UL << SCU_SFSP1_20_MODE_Pos) /*!< SCU SFSP1_20: MODE Mask */ +#define SCU_SFSP1_20_EPD_Pos 3 /*!< SCU SFSP1_20: EPD Position */ +#define SCU_SFSP1_20_EPD_Msk (0x01UL << SCU_SFSP1_20_EPD_Pos) /*!< SCU SFSP1_20: EPD Mask */ +#define SCU_SFSP1_20_EPUN_Pos 4 /*!< SCU SFSP1_20: EPUN Position */ +#define SCU_SFSP1_20_EPUN_Msk (0x01UL << SCU_SFSP1_20_EPUN_Pos) /*!< SCU SFSP1_20: EPUN Mask */ +#define SCU_SFSP1_20_EHS_Pos 5 /*!< SCU SFSP1_20: EHS Position */ +#define SCU_SFSP1_20_EHS_Msk (0x01UL << SCU_SFSP1_20_EHS_Pos) /*!< SCU SFSP1_20: EHS Mask */ +#define SCU_SFSP1_20_EZI_Pos 6 /*!< SCU SFSP1_20: EZI Position */ +#define SCU_SFSP1_20_EZI_Msk (0x01UL << SCU_SFSP1_20_EZI_Pos) /*!< SCU SFSP1_20: EZI Mask */ +#define SCU_SFSP1_20_ZIF_Pos 7 /*!< SCU SFSP1_20: ZIF Position */ +#define SCU_SFSP1_20_ZIF_Msk (0x01UL << SCU_SFSP1_20_ZIF_Pos) /*!< SCU SFSP1_20: ZIF Mask */ + +/* --------------------------------- SCU_SFSP2_0 -------------------------------- */ +#define SCU_SFSP2_0_MODE_Pos 0 /*!< SCU SFSP2_0: MODE Position */ +#define SCU_SFSP2_0_MODE_Msk (0x07UL << SCU_SFSP2_0_MODE_Pos) /*!< SCU SFSP2_0: MODE Mask */ +#define SCU_SFSP2_0_EPD_Pos 3 /*!< SCU SFSP2_0: EPD Position */ +#define SCU_SFSP2_0_EPD_Msk (0x01UL << SCU_SFSP2_0_EPD_Pos) /*!< SCU SFSP2_0: EPD Mask */ +#define SCU_SFSP2_0_EPUN_Pos 4 /*!< SCU SFSP2_0: EPUN Position */ +#define SCU_SFSP2_0_EPUN_Msk (0x01UL << SCU_SFSP2_0_EPUN_Pos) /*!< SCU SFSP2_0: EPUN Mask */ +#define SCU_SFSP2_0_EHS_Pos 5 /*!< SCU SFSP2_0: EHS Position */ +#define SCU_SFSP2_0_EHS_Msk (0x01UL << SCU_SFSP2_0_EHS_Pos) /*!< SCU SFSP2_0: EHS Mask */ +#define SCU_SFSP2_0_EZI_Pos 6 /*!< SCU SFSP2_0: EZI Position */ +#define SCU_SFSP2_0_EZI_Msk (0x01UL << SCU_SFSP2_0_EZI_Pos) /*!< SCU SFSP2_0: EZI Mask */ +#define SCU_SFSP2_0_ZIF_Pos 7 /*!< SCU SFSP2_0: ZIF Position */ +#define SCU_SFSP2_0_ZIF_Msk (0x01UL << SCU_SFSP2_0_ZIF_Pos) /*!< SCU SFSP2_0: ZIF Mask */ + +/* --------------------------------- SCU_SFSP2_1 -------------------------------- */ +#define SCU_SFSP2_1_MODE_Pos 0 /*!< SCU SFSP2_1: MODE Position */ +#define SCU_SFSP2_1_MODE_Msk (0x07UL << SCU_SFSP2_1_MODE_Pos) /*!< SCU SFSP2_1: MODE Mask */ +#define SCU_SFSP2_1_EPD_Pos 3 /*!< SCU SFSP2_1: EPD Position */ +#define SCU_SFSP2_1_EPD_Msk (0x01UL << SCU_SFSP2_1_EPD_Pos) /*!< SCU SFSP2_1: EPD Mask */ +#define SCU_SFSP2_1_EPUN_Pos 4 /*!< SCU SFSP2_1: EPUN Position */ +#define SCU_SFSP2_1_EPUN_Msk (0x01UL << SCU_SFSP2_1_EPUN_Pos) /*!< SCU SFSP2_1: EPUN Mask */ +#define SCU_SFSP2_1_EHS_Pos 5 /*!< SCU SFSP2_1: EHS Position */ +#define SCU_SFSP2_1_EHS_Msk (0x01UL << SCU_SFSP2_1_EHS_Pos) /*!< SCU SFSP2_1: EHS Mask */ +#define SCU_SFSP2_1_EZI_Pos 6 /*!< SCU SFSP2_1: EZI Position */ +#define SCU_SFSP2_1_EZI_Msk (0x01UL << SCU_SFSP2_1_EZI_Pos) /*!< SCU SFSP2_1: EZI Mask */ +#define SCU_SFSP2_1_ZIF_Pos 7 /*!< SCU SFSP2_1: ZIF Position */ +#define SCU_SFSP2_1_ZIF_Msk (0x01UL << SCU_SFSP2_1_ZIF_Pos) /*!< SCU SFSP2_1: ZIF Mask */ + +/* --------------------------------- SCU_SFSP2_2 -------------------------------- */ +#define SCU_SFSP2_2_MODE_Pos 0 /*!< SCU SFSP2_2: MODE Position */ +#define SCU_SFSP2_2_MODE_Msk (0x07UL << SCU_SFSP2_2_MODE_Pos) /*!< SCU SFSP2_2: MODE Mask */ +#define SCU_SFSP2_2_EPD_Pos 3 /*!< SCU SFSP2_2: EPD Position */ +#define SCU_SFSP2_2_EPD_Msk (0x01UL << SCU_SFSP2_2_EPD_Pos) /*!< SCU SFSP2_2: EPD Mask */ +#define SCU_SFSP2_2_EPUN_Pos 4 /*!< SCU SFSP2_2: EPUN Position */ +#define SCU_SFSP2_2_EPUN_Msk (0x01UL << SCU_SFSP2_2_EPUN_Pos) /*!< SCU SFSP2_2: EPUN Mask */ +#define SCU_SFSP2_2_EHS_Pos 5 /*!< SCU SFSP2_2: EHS Position */ +#define SCU_SFSP2_2_EHS_Msk (0x01UL << SCU_SFSP2_2_EHS_Pos) /*!< SCU SFSP2_2: EHS Mask */ +#define SCU_SFSP2_2_EZI_Pos 6 /*!< SCU SFSP2_2: EZI Position */ +#define SCU_SFSP2_2_EZI_Msk (0x01UL << SCU_SFSP2_2_EZI_Pos) /*!< SCU SFSP2_2: EZI Mask */ +#define SCU_SFSP2_2_ZIF_Pos 7 /*!< SCU SFSP2_2: ZIF Position */ +#define SCU_SFSP2_2_ZIF_Msk (0x01UL << SCU_SFSP2_2_ZIF_Pos) /*!< SCU SFSP2_2: ZIF Mask */ + +/* --------------------------------- SCU_SFSP2_3 -------------------------------- */ +#define SCU_SFSP2_3_MODE_Pos 0 /*!< SCU SFSP2_3: MODE Position */ +#define SCU_SFSP2_3_MODE_Msk (0x07UL << SCU_SFSP2_3_MODE_Pos) /*!< SCU SFSP2_3: MODE Mask */ +#define SCU_SFSP2_3_EPD_Pos 3 /*!< SCU SFSP2_3: EPD Position */ +#define SCU_SFSP2_3_EPD_Msk (0x01UL << SCU_SFSP2_3_EPD_Pos) /*!< SCU SFSP2_3: EPD Mask */ +#define SCU_SFSP2_3_EPUN_Pos 4 /*!< SCU SFSP2_3: EPUN Position */ +#define SCU_SFSP2_3_EPUN_Msk (0x01UL << SCU_SFSP2_3_EPUN_Pos) /*!< SCU SFSP2_3: EPUN Mask */ +#define SCU_SFSP2_3_EZI_Pos 6 /*!< SCU SFSP2_3: EZI Position */ +#define SCU_SFSP2_3_EZI_Msk (0x01UL << SCU_SFSP2_3_EZI_Pos) /*!< SCU SFSP2_3: EZI Mask */ +#define SCU_SFSP2_3_ZIF_Pos 7 /*!< SCU SFSP2_3: ZIF Position */ +#define SCU_SFSP2_3_ZIF_Msk (0x01UL << SCU_SFSP2_3_ZIF_Pos) /*!< SCU SFSP2_3: ZIF Mask */ +#define SCU_SFSP2_3_EHD_Pos 8 /*!< SCU SFSP2_3: EHD Position */ +#define SCU_SFSP2_3_EHD_Msk (0x03UL << SCU_SFSP2_3_EHD_Pos) /*!< SCU SFSP2_3: EHD Mask */ + +/* --------------------------------- SCU_SFSP2_4 -------------------------------- */ +#define SCU_SFSP2_4_MODE_Pos 0 /*!< SCU SFSP2_4: MODE Position */ +#define SCU_SFSP2_4_MODE_Msk (0x07UL << SCU_SFSP2_4_MODE_Pos) /*!< SCU SFSP2_4: MODE Mask */ +#define SCU_SFSP2_4_EPD_Pos 3 /*!< SCU SFSP2_4: EPD Position */ +#define SCU_SFSP2_4_EPD_Msk (0x01UL << SCU_SFSP2_4_EPD_Pos) /*!< SCU SFSP2_4: EPD Mask */ +#define SCU_SFSP2_4_EPUN_Pos 4 /*!< SCU SFSP2_4: EPUN Position */ +#define SCU_SFSP2_4_EPUN_Msk (0x01UL << SCU_SFSP2_4_EPUN_Pos) /*!< SCU SFSP2_4: EPUN Mask */ +#define SCU_SFSP2_4_EZI_Pos 6 /*!< SCU SFSP2_4: EZI Position */ +#define SCU_SFSP2_4_EZI_Msk (0x01UL << SCU_SFSP2_4_EZI_Pos) /*!< SCU SFSP2_4: EZI Mask */ +#define SCU_SFSP2_4_ZIF_Pos 7 /*!< SCU SFSP2_4: ZIF Position */ +#define SCU_SFSP2_4_ZIF_Msk (0x01UL << SCU_SFSP2_4_ZIF_Pos) /*!< SCU SFSP2_4: ZIF Mask */ +#define SCU_SFSP2_4_EHD_Pos 8 /*!< SCU SFSP2_4: EHD Position */ +#define SCU_SFSP2_4_EHD_Msk (0x03UL << SCU_SFSP2_4_EHD_Pos) /*!< SCU SFSP2_4: EHD Mask */ + +/* --------------------------------- SCU_SFSP2_5 -------------------------------- */ +#define SCU_SFSP2_5_MODE_Pos 0 /*!< SCU SFSP2_5: MODE Position */ +#define SCU_SFSP2_5_MODE_Msk (0x07UL << SCU_SFSP2_5_MODE_Pos) /*!< SCU SFSP2_5: MODE Mask */ +#define SCU_SFSP2_5_EPD_Pos 3 /*!< SCU SFSP2_5: EPD Position */ +#define SCU_SFSP2_5_EPD_Msk (0x01UL << SCU_SFSP2_5_EPD_Pos) /*!< SCU SFSP2_5: EPD Mask */ +#define SCU_SFSP2_5_EPUN_Pos 4 /*!< SCU SFSP2_5: EPUN Position */ +#define SCU_SFSP2_5_EPUN_Msk (0x01UL << SCU_SFSP2_5_EPUN_Pos) /*!< SCU SFSP2_5: EPUN Mask */ +#define SCU_SFSP2_5_EZI_Pos 6 /*!< SCU SFSP2_5: EZI Position */ +#define SCU_SFSP2_5_EZI_Msk (0x01UL << SCU_SFSP2_5_EZI_Pos) /*!< SCU SFSP2_5: EZI Mask */ +#define SCU_SFSP2_5_ZIF_Pos 7 /*!< SCU SFSP2_5: ZIF Position */ +#define SCU_SFSP2_5_ZIF_Msk (0x01UL << SCU_SFSP2_5_ZIF_Pos) /*!< SCU SFSP2_5: ZIF Mask */ +#define SCU_SFSP2_5_EHD_Pos 8 /*!< SCU SFSP2_5: EHD Position */ +#define SCU_SFSP2_5_EHD_Msk (0x03UL << SCU_SFSP2_5_EHD_Pos) /*!< SCU SFSP2_5: EHD Mask */ + +/* --------------------------------- SCU_SFSP2_6 -------------------------------- */ +#define SCU_SFSP2_6_MODE_Pos 0 /*!< SCU SFSP2_6: MODE Position */ +#define SCU_SFSP2_6_MODE_Msk (0x07UL << SCU_SFSP2_6_MODE_Pos) /*!< SCU SFSP2_6: MODE Mask */ +#define SCU_SFSP2_6_EPD_Pos 3 /*!< SCU SFSP2_6: EPD Position */ +#define SCU_SFSP2_6_EPD_Msk (0x01UL << SCU_SFSP2_6_EPD_Pos) /*!< SCU SFSP2_6: EPD Mask */ +#define SCU_SFSP2_6_EPUN_Pos 4 /*!< SCU SFSP2_6: EPUN Position */ +#define SCU_SFSP2_6_EPUN_Msk (0x01UL << SCU_SFSP2_6_EPUN_Pos) /*!< SCU SFSP2_6: EPUN Mask */ +#define SCU_SFSP2_6_EHS_Pos 5 /*!< SCU SFSP2_6: EHS Position */ +#define SCU_SFSP2_6_EHS_Msk (0x01UL << SCU_SFSP2_6_EHS_Pos) /*!< SCU SFSP2_6: EHS Mask */ +#define SCU_SFSP2_6_EZI_Pos 6 /*!< SCU SFSP2_6: EZI Position */ +#define SCU_SFSP2_6_EZI_Msk (0x01UL << SCU_SFSP2_6_EZI_Pos) /*!< SCU SFSP2_6: EZI Mask */ +#define SCU_SFSP2_6_ZIF_Pos 7 /*!< SCU SFSP2_6: ZIF Position */ +#define SCU_SFSP2_6_ZIF_Msk (0x01UL << SCU_SFSP2_6_ZIF_Pos) /*!< SCU SFSP2_6: ZIF Mask */ + +/* --------------------------------- SCU_SFSP2_7 -------------------------------- */ +#define SCU_SFSP2_7_MODE_Pos 0 /*!< SCU SFSP2_7: MODE Position */ +#define SCU_SFSP2_7_MODE_Msk (0x07UL << SCU_SFSP2_7_MODE_Pos) /*!< SCU SFSP2_7: MODE Mask */ +#define SCU_SFSP2_7_EPD_Pos 3 /*!< SCU SFSP2_7: EPD Position */ +#define SCU_SFSP2_7_EPD_Msk (0x01UL << SCU_SFSP2_7_EPD_Pos) /*!< SCU SFSP2_7: EPD Mask */ +#define SCU_SFSP2_7_EPUN_Pos 4 /*!< SCU SFSP2_7: EPUN Position */ +#define SCU_SFSP2_7_EPUN_Msk (0x01UL << SCU_SFSP2_7_EPUN_Pos) /*!< SCU SFSP2_7: EPUN Mask */ +#define SCU_SFSP2_7_EHS_Pos 5 /*!< SCU SFSP2_7: EHS Position */ +#define SCU_SFSP2_7_EHS_Msk (0x01UL << SCU_SFSP2_7_EHS_Pos) /*!< SCU SFSP2_7: EHS Mask */ +#define SCU_SFSP2_7_EZI_Pos 6 /*!< SCU SFSP2_7: EZI Position */ +#define SCU_SFSP2_7_EZI_Msk (0x01UL << SCU_SFSP2_7_EZI_Pos) /*!< SCU SFSP2_7: EZI Mask */ +#define SCU_SFSP2_7_ZIF_Pos 7 /*!< SCU SFSP2_7: ZIF Position */ +#define SCU_SFSP2_7_ZIF_Msk (0x01UL << SCU_SFSP2_7_ZIF_Pos) /*!< SCU SFSP2_7: ZIF Mask */ + +/* --------------------------------- SCU_SFSP2_8 -------------------------------- */ +#define SCU_SFSP2_8_MODE_Pos 0 /*!< SCU SFSP2_8: MODE Position */ +#define SCU_SFSP2_8_MODE_Msk (0x07UL << SCU_SFSP2_8_MODE_Pos) /*!< SCU SFSP2_8: MODE Mask */ +#define SCU_SFSP2_8_EPD_Pos 3 /*!< SCU SFSP2_8: EPD Position */ +#define SCU_SFSP2_8_EPD_Msk (0x01UL << SCU_SFSP2_8_EPD_Pos) /*!< SCU SFSP2_8: EPD Mask */ +#define SCU_SFSP2_8_EPUN_Pos 4 /*!< SCU SFSP2_8: EPUN Position */ +#define SCU_SFSP2_8_EPUN_Msk (0x01UL << SCU_SFSP2_8_EPUN_Pos) /*!< SCU SFSP2_8: EPUN Mask */ +#define SCU_SFSP2_8_EHS_Pos 5 /*!< SCU SFSP2_8: EHS Position */ +#define SCU_SFSP2_8_EHS_Msk (0x01UL << SCU_SFSP2_8_EHS_Pos) /*!< SCU SFSP2_8: EHS Mask */ +#define SCU_SFSP2_8_EZI_Pos 6 /*!< SCU SFSP2_8: EZI Position */ +#define SCU_SFSP2_8_EZI_Msk (0x01UL << SCU_SFSP2_8_EZI_Pos) /*!< SCU SFSP2_8: EZI Mask */ +#define SCU_SFSP2_8_ZIF_Pos 7 /*!< SCU SFSP2_8: ZIF Position */ +#define SCU_SFSP2_8_ZIF_Msk (0x01UL << SCU_SFSP2_8_ZIF_Pos) /*!< SCU SFSP2_8: ZIF Mask */ + +/* --------------------------------- SCU_SFSP2_9 -------------------------------- */ +#define SCU_SFSP2_9_MODE_Pos 0 /*!< SCU SFSP2_9: MODE Position */ +#define SCU_SFSP2_9_MODE_Msk (0x07UL << SCU_SFSP2_9_MODE_Pos) /*!< SCU SFSP2_9: MODE Mask */ +#define SCU_SFSP2_9_EPD_Pos 3 /*!< SCU SFSP2_9: EPD Position */ +#define SCU_SFSP2_9_EPD_Msk (0x01UL << SCU_SFSP2_9_EPD_Pos) /*!< SCU SFSP2_9: EPD Mask */ +#define SCU_SFSP2_9_EPUN_Pos 4 /*!< SCU SFSP2_9: EPUN Position */ +#define SCU_SFSP2_9_EPUN_Msk (0x01UL << SCU_SFSP2_9_EPUN_Pos) /*!< SCU SFSP2_9: EPUN Mask */ +#define SCU_SFSP2_9_EHS_Pos 5 /*!< SCU SFSP2_9: EHS Position */ +#define SCU_SFSP2_9_EHS_Msk (0x01UL << SCU_SFSP2_9_EHS_Pos) /*!< SCU SFSP2_9: EHS Mask */ +#define SCU_SFSP2_9_EZI_Pos 6 /*!< SCU SFSP2_9: EZI Position */ +#define SCU_SFSP2_9_EZI_Msk (0x01UL << SCU_SFSP2_9_EZI_Pos) /*!< SCU SFSP2_9: EZI Mask */ +#define SCU_SFSP2_9_ZIF_Pos 7 /*!< SCU SFSP2_9: ZIF Position */ +#define SCU_SFSP2_9_ZIF_Msk (0x01UL << SCU_SFSP2_9_ZIF_Pos) /*!< SCU SFSP2_9: ZIF Mask */ + +/* -------------------------------- SCU_SFSP2_10 -------------------------------- */ +#define SCU_SFSP2_10_MODE_Pos 0 /*!< SCU SFSP2_10: MODE Position */ +#define SCU_SFSP2_10_MODE_Msk (0x07UL << SCU_SFSP2_10_MODE_Pos) /*!< SCU SFSP2_10: MODE Mask */ +#define SCU_SFSP2_10_EPD_Pos 3 /*!< SCU SFSP2_10: EPD Position */ +#define SCU_SFSP2_10_EPD_Msk (0x01UL << SCU_SFSP2_10_EPD_Pos) /*!< SCU SFSP2_10: EPD Mask */ +#define SCU_SFSP2_10_EPUN_Pos 4 /*!< SCU SFSP2_10: EPUN Position */ +#define SCU_SFSP2_10_EPUN_Msk (0x01UL << SCU_SFSP2_10_EPUN_Pos) /*!< SCU SFSP2_10: EPUN Mask */ +#define SCU_SFSP2_10_EHS_Pos 5 /*!< SCU SFSP2_10: EHS Position */ +#define SCU_SFSP2_10_EHS_Msk (0x01UL << SCU_SFSP2_10_EHS_Pos) /*!< SCU SFSP2_10: EHS Mask */ +#define SCU_SFSP2_10_EZI_Pos 6 /*!< SCU SFSP2_10: EZI Position */ +#define SCU_SFSP2_10_EZI_Msk (0x01UL << SCU_SFSP2_10_EZI_Pos) /*!< SCU SFSP2_10: EZI Mask */ +#define SCU_SFSP2_10_ZIF_Pos 7 /*!< SCU SFSP2_10: ZIF Position */ +#define SCU_SFSP2_10_ZIF_Msk (0x01UL << SCU_SFSP2_10_ZIF_Pos) /*!< SCU SFSP2_10: ZIF Mask */ + +/* -------------------------------- SCU_SFSP2_11 -------------------------------- */ +#define SCU_SFSP2_11_MODE_Pos 0 /*!< SCU SFSP2_11: MODE Position */ +#define SCU_SFSP2_11_MODE_Msk (0x07UL << SCU_SFSP2_11_MODE_Pos) /*!< SCU SFSP2_11: MODE Mask */ +#define SCU_SFSP2_11_EPD_Pos 3 /*!< SCU SFSP2_11: EPD Position */ +#define SCU_SFSP2_11_EPD_Msk (0x01UL << SCU_SFSP2_11_EPD_Pos) /*!< SCU SFSP2_11: EPD Mask */ +#define SCU_SFSP2_11_EPUN_Pos 4 /*!< SCU SFSP2_11: EPUN Position */ +#define SCU_SFSP2_11_EPUN_Msk (0x01UL << SCU_SFSP2_11_EPUN_Pos) /*!< SCU SFSP2_11: EPUN Mask */ +#define SCU_SFSP2_11_EHS_Pos 5 /*!< SCU SFSP2_11: EHS Position */ +#define SCU_SFSP2_11_EHS_Msk (0x01UL << SCU_SFSP2_11_EHS_Pos) /*!< SCU SFSP2_11: EHS Mask */ +#define SCU_SFSP2_11_EZI_Pos 6 /*!< SCU SFSP2_11: EZI Position */ +#define SCU_SFSP2_11_EZI_Msk (0x01UL << SCU_SFSP2_11_EZI_Pos) /*!< SCU SFSP2_11: EZI Mask */ +#define SCU_SFSP2_11_ZIF_Pos 7 /*!< SCU SFSP2_11: ZIF Position */ +#define SCU_SFSP2_11_ZIF_Msk (0x01UL << SCU_SFSP2_11_ZIF_Pos) /*!< SCU SFSP2_11: ZIF Mask */ + +/* -------------------------------- SCU_SFSP2_12 -------------------------------- */ +#define SCU_SFSP2_12_MODE_Pos 0 /*!< SCU SFSP2_12: MODE Position */ +#define SCU_SFSP2_12_MODE_Msk (0x07UL << SCU_SFSP2_12_MODE_Pos) /*!< SCU SFSP2_12: MODE Mask */ +#define SCU_SFSP2_12_EPD_Pos 3 /*!< SCU SFSP2_12: EPD Position */ +#define SCU_SFSP2_12_EPD_Msk (0x01UL << SCU_SFSP2_12_EPD_Pos) /*!< SCU SFSP2_12: EPD Mask */ +#define SCU_SFSP2_12_EPUN_Pos 4 /*!< SCU SFSP2_12: EPUN Position */ +#define SCU_SFSP2_12_EPUN_Msk (0x01UL << SCU_SFSP2_12_EPUN_Pos) /*!< SCU SFSP2_12: EPUN Mask */ +#define SCU_SFSP2_12_EHS_Pos 5 /*!< SCU SFSP2_12: EHS Position */ +#define SCU_SFSP2_12_EHS_Msk (0x01UL << SCU_SFSP2_12_EHS_Pos) /*!< SCU SFSP2_12: EHS Mask */ +#define SCU_SFSP2_12_EZI_Pos 6 /*!< SCU SFSP2_12: EZI Position */ +#define SCU_SFSP2_12_EZI_Msk (0x01UL << SCU_SFSP2_12_EZI_Pos) /*!< SCU SFSP2_12: EZI Mask */ +#define SCU_SFSP2_12_ZIF_Pos 7 /*!< SCU SFSP2_12: ZIF Position */ +#define SCU_SFSP2_12_ZIF_Msk (0x01UL << SCU_SFSP2_12_ZIF_Pos) /*!< SCU SFSP2_12: ZIF Mask */ + +/* -------------------------------- SCU_SFSP2_13 -------------------------------- */ +#define SCU_SFSP2_13_MODE_Pos 0 /*!< SCU SFSP2_13: MODE Position */ +#define SCU_SFSP2_13_MODE_Msk (0x07UL << SCU_SFSP2_13_MODE_Pos) /*!< SCU SFSP2_13: MODE Mask */ +#define SCU_SFSP2_13_EPD_Pos 3 /*!< SCU SFSP2_13: EPD Position */ +#define SCU_SFSP2_13_EPD_Msk (0x01UL << SCU_SFSP2_13_EPD_Pos) /*!< SCU SFSP2_13: EPD Mask */ +#define SCU_SFSP2_13_EPUN_Pos 4 /*!< SCU SFSP2_13: EPUN Position */ +#define SCU_SFSP2_13_EPUN_Msk (0x01UL << SCU_SFSP2_13_EPUN_Pos) /*!< SCU SFSP2_13: EPUN Mask */ +#define SCU_SFSP2_13_EHS_Pos 5 /*!< SCU SFSP2_13: EHS Position */ +#define SCU_SFSP2_13_EHS_Msk (0x01UL << SCU_SFSP2_13_EHS_Pos) /*!< SCU SFSP2_13: EHS Mask */ +#define SCU_SFSP2_13_EZI_Pos 6 /*!< SCU SFSP2_13: EZI Position */ +#define SCU_SFSP2_13_EZI_Msk (0x01UL << SCU_SFSP2_13_EZI_Pos) /*!< SCU SFSP2_13: EZI Mask */ +#define SCU_SFSP2_13_ZIF_Pos 7 /*!< SCU SFSP2_13: ZIF Position */ +#define SCU_SFSP2_13_ZIF_Msk (0x01UL << SCU_SFSP2_13_ZIF_Pos) /*!< SCU SFSP2_13: ZIF Mask */ + +/* --------------------------------- SCU_SFSP3_0 -------------------------------- */ +#define SCU_SFSP3_0_MODE_Pos 0 /*!< SCU SFSP3_0: MODE Position */ +#define SCU_SFSP3_0_MODE_Msk (0x07UL << SCU_SFSP3_0_MODE_Pos) /*!< SCU SFSP3_0: MODE Mask */ +#define SCU_SFSP3_0_EPD_Pos 3 /*!< SCU SFSP3_0: EPD Position */ +#define SCU_SFSP3_0_EPD_Msk (0x01UL << SCU_SFSP3_0_EPD_Pos) /*!< SCU SFSP3_0: EPD Mask */ +#define SCU_SFSP3_0_EPUN_Pos 4 /*!< SCU SFSP3_0: EPUN Position */ +#define SCU_SFSP3_0_EPUN_Msk (0x01UL << SCU_SFSP3_0_EPUN_Pos) /*!< SCU SFSP3_0: EPUN Mask */ +#define SCU_SFSP3_0_EHS_Pos 5 /*!< SCU SFSP3_0: EHS Position */ +#define SCU_SFSP3_0_EHS_Msk (0x01UL << SCU_SFSP3_0_EHS_Pos) /*!< SCU SFSP3_0: EHS Mask */ +#define SCU_SFSP3_0_EZI_Pos 6 /*!< SCU SFSP3_0: EZI Position */ +#define SCU_SFSP3_0_EZI_Msk (0x01UL << SCU_SFSP3_0_EZI_Pos) /*!< SCU SFSP3_0: EZI Mask */ +#define SCU_SFSP3_0_ZIF_Pos 7 /*!< SCU SFSP3_0: ZIF Position */ +#define SCU_SFSP3_0_ZIF_Msk (0x01UL << SCU_SFSP3_0_ZIF_Pos) /*!< SCU SFSP3_0: ZIF Mask */ + +/* --------------------------------- SCU_SFSP3_1 -------------------------------- */ +#define SCU_SFSP3_1_MODE_Pos 0 /*!< SCU SFSP3_1: MODE Position */ +#define SCU_SFSP3_1_MODE_Msk (0x07UL << SCU_SFSP3_1_MODE_Pos) /*!< SCU SFSP3_1: MODE Mask */ +#define SCU_SFSP3_1_EPD_Pos 3 /*!< SCU SFSP3_1: EPD Position */ +#define SCU_SFSP3_1_EPD_Msk (0x01UL << SCU_SFSP3_1_EPD_Pos) /*!< SCU SFSP3_1: EPD Mask */ +#define SCU_SFSP3_1_EPUN_Pos 4 /*!< SCU SFSP3_1: EPUN Position */ +#define SCU_SFSP3_1_EPUN_Msk (0x01UL << SCU_SFSP3_1_EPUN_Pos) /*!< SCU SFSP3_1: EPUN Mask */ +#define SCU_SFSP3_1_EHS_Pos 5 /*!< SCU SFSP3_1: EHS Position */ +#define SCU_SFSP3_1_EHS_Msk (0x01UL << SCU_SFSP3_1_EHS_Pos) /*!< SCU SFSP3_1: EHS Mask */ +#define SCU_SFSP3_1_EZI_Pos 6 /*!< SCU SFSP3_1: EZI Position */ +#define SCU_SFSP3_1_EZI_Msk (0x01UL << SCU_SFSP3_1_EZI_Pos) /*!< SCU SFSP3_1: EZI Mask */ +#define SCU_SFSP3_1_ZIF_Pos 7 /*!< SCU SFSP3_1: ZIF Position */ +#define SCU_SFSP3_1_ZIF_Msk (0x01UL << SCU_SFSP3_1_ZIF_Pos) /*!< SCU SFSP3_1: ZIF Mask */ + +/* --------------------------------- SCU_SFSP3_2 -------------------------------- */ +#define SCU_SFSP3_2_MODE_Pos 0 /*!< SCU SFSP3_2: MODE Position */ +#define SCU_SFSP3_2_MODE_Msk (0x07UL << SCU_SFSP3_2_MODE_Pos) /*!< SCU SFSP3_2: MODE Mask */ +#define SCU_SFSP3_2_EPD_Pos 3 /*!< SCU SFSP3_2: EPD Position */ +#define SCU_SFSP3_2_EPD_Msk (0x01UL << SCU_SFSP3_2_EPD_Pos) /*!< SCU SFSP3_2: EPD Mask */ +#define SCU_SFSP3_2_EPUN_Pos 4 /*!< SCU SFSP3_2: EPUN Position */ +#define SCU_SFSP3_2_EPUN_Msk (0x01UL << SCU_SFSP3_2_EPUN_Pos) /*!< SCU SFSP3_2: EPUN Mask */ +#define SCU_SFSP3_2_EHS_Pos 5 /*!< SCU SFSP3_2: EHS Position */ +#define SCU_SFSP3_2_EHS_Msk (0x01UL << SCU_SFSP3_2_EHS_Pos) /*!< SCU SFSP3_2: EHS Mask */ +#define SCU_SFSP3_2_EZI_Pos 6 /*!< SCU SFSP3_2: EZI Position */ +#define SCU_SFSP3_2_EZI_Msk (0x01UL << SCU_SFSP3_2_EZI_Pos) /*!< SCU SFSP3_2: EZI Mask */ +#define SCU_SFSP3_2_ZIF_Pos 7 /*!< SCU SFSP3_2: ZIF Position */ +#define SCU_SFSP3_2_ZIF_Msk (0x01UL << SCU_SFSP3_2_ZIF_Pos) /*!< SCU SFSP3_2: ZIF Mask */ + +/* --------------------------------- SCU_SFSP3_3 -------------------------------- */ +#define SCU_SFSP3_3_MODE_Pos 0 /*!< SCU SFSP3_3: MODE Position */ +#define SCU_SFSP3_3_MODE_Msk (0x07UL << SCU_SFSP3_3_MODE_Pos) /*!< SCU SFSP3_3: MODE Mask */ +#define SCU_SFSP3_3_EPD_Pos 3 /*!< SCU SFSP3_3: EPD Position */ +#define SCU_SFSP3_3_EPD_Msk (0x01UL << SCU_SFSP3_3_EPD_Pos) /*!< SCU SFSP3_3: EPD Mask */ +#define SCU_SFSP3_3_EPUN_Pos 4 /*!< SCU SFSP3_3: EPUN Position */ +#define SCU_SFSP3_3_EPUN_Msk (0x01UL << SCU_SFSP3_3_EPUN_Pos) /*!< SCU SFSP3_3: EPUN Mask */ +#define SCU_SFSP3_3_EHS_Pos 5 /*!< SCU SFSP3_3: EHS Position */ +#define SCU_SFSP3_3_EHS_Msk (0x01UL << SCU_SFSP3_3_EHS_Pos) /*!< SCU SFSP3_3: EHS Mask */ +#define SCU_SFSP3_3_EZI_Pos 6 /*!< SCU SFSP3_3: EZI Position */ +#define SCU_SFSP3_3_EZI_Msk (0x01UL << SCU_SFSP3_3_EZI_Pos) /*!< SCU SFSP3_3: EZI Mask */ +#define SCU_SFSP3_3_ZIF_Pos 7 /*!< SCU SFSP3_3: ZIF Position */ +#define SCU_SFSP3_3_ZIF_Msk (0x01UL << SCU_SFSP3_3_ZIF_Pos) /*!< SCU SFSP3_3: ZIF Mask */ + +/* --------------------------------- SCU_SFSP3_4 -------------------------------- */ +#define SCU_SFSP3_4_MODE_Pos 0 /*!< SCU SFSP3_4: MODE Position */ +#define SCU_SFSP3_4_MODE_Msk (0x07UL << SCU_SFSP3_4_MODE_Pos) /*!< SCU SFSP3_4: MODE Mask */ +#define SCU_SFSP3_4_EPD_Pos 3 /*!< SCU SFSP3_4: EPD Position */ +#define SCU_SFSP3_4_EPD_Msk (0x01UL << SCU_SFSP3_4_EPD_Pos) /*!< SCU SFSP3_4: EPD Mask */ +#define SCU_SFSP3_4_EPUN_Pos 4 /*!< SCU SFSP3_4: EPUN Position */ +#define SCU_SFSP3_4_EPUN_Msk (0x01UL << SCU_SFSP3_4_EPUN_Pos) /*!< SCU SFSP3_4: EPUN Mask */ +#define SCU_SFSP3_4_EHS_Pos 5 /*!< SCU SFSP3_4: EHS Position */ +#define SCU_SFSP3_4_EHS_Msk (0x01UL << SCU_SFSP3_4_EHS_Pos) /*!< SCU SFSP3_4: EHS Mask */ +#define SCU_SFSP3_4_EZI_Pos 6 /*!< SCU SFSP3_4: EZI Position */ +#define SCU_SFSP3_4_EZI_Msk (0x01UL << SCU_SFSP3_4_EZI_Pos) /*!< SCU SFSP3_4: EZI Mask */ +#define SCU_SFSP3_4_ZIF_Pos 7 /*!< SCU SFSP3_4: ZIF Position */ +#define SCU_SFSP3_4_ZIF_Msk (0x01UL << SCU_SFSP3_4_ZIF_Pos) /*!< SCU SFSP3_4: ZIF Mask */ + +/* --------------------------------- SCU_SFSP3_5 -------------------------------- */ +#define SCU_SFSP3_5_MODE_Pos 0 /*!< SCU SFSP3_5: MODE Position */ +#define SCU_SFSP3_5_MODE_Msk (0x07UL << SCU_SFSP3_5_MODE_Pos) /*!< SCU SFSP3_5: MODE Mask */ +#define SCU_SFSP3_5_EPD_Pos 3 /*!< SCU SFSP3_5: EPD Position */ +#define SCU_SFSP3_5_EPD_Msk (0x01UL << SCU_SFSP3_5_EPD_Pos) /*!< SCU SFSP3_5: EPD Mask */ +#define SCU_SFSP3_5_EPUN_Pos 4 /*!< SCU SFSP3_5: EPUN Position */ +#define SCU_SFSP3_5_EPUN_Msk (0x01UL << SCU_SFSP3_5_EPUN_Pos) /*!< SCU SFSP3_5: EPUN Mask */ +#define SCU_SFSP3_5_EHS_Pos 5 /*!< SCU SFSP3_5: EHS Position */ +#define SCU_SFSP3_5_EHS_Msk (0x01UL << SCU_SFSP3_5_EHS_Pos) /*!< SCU SFSP3_5: EHS Mask */ +#define SCU_SFSP3_5_EZI_Pos 6 /*!< SCU SFSP3_5: EZI Position */ +#define SCU_SFSP3_5_EZI_Msk (0x01UL << SCU_SFSP3_5_EZI_Pos) /*!< SCU SFSP3_5: EZI Mask */ +#define SCU_SFSP3_5_ZIF_Pos 7 /*!< SCU SFSP3_5: ZIF Position */ +#define SCU_SFSP3_5_ZIF_Msk (0x01UL << SCU_SFSP3_5_ZIF_Pos) /*!< SCU SFSP3_5: ZIF Mask */ + +/* --------------------------------- SCU_SFSP3_6 -------------------------------- */ +#define SCU_SFSP3_6_MODE_Pos 0 /*!< SCU SFSP3_6: MODE Position */ +#define SCU_SFSP3_6_MODE_Msk (0x07UL << SCU_SFSP3_6_MODE_Pos) /*!< SCU SFSP3_6: MODE Mask */ +#define SCU_SFSP3_6_EPD_Pos 3 /*!< SCU SFSP3_6: EPD Position */ +#define SCU_SFSP3_6_EPD_Msk (0x01UL << SCU_SFSP3_6_EPD_Pos) /*!< SCU SFSP3_6: EPD Mask */ +#define SCU_SFSP3_6_EPUN_Pos 4 /*!< SCU SFSP3_6: EPUN Position */ +#define SCU_SFSP3_6_EPUN_Msk (0x01UL << SCU_SFSP3_6_EPUN_Pos) /*!< SCU SFSP3_6: EPUN Mask */ +#define SCU_SFSP3_6_EHS_Pos 5 /*!< SCU SFSP3_6: EHS Position */ +#define SCU_SFSP3_6_EHS_Msk (0x01UL << SCU_SFSP3_6_EHS_Pos) /*!< SCU SFSP3_6: EHS Mask */ +#define SCU_SFSP3_6_EZI_Pos 6 /*!< SCU SFSP3_6: EZI Position */ +#define SCU_SFSP3_6_EZI_Msk (0x01UL << SCU_SFSP3_6_EZI_Pos) /*!< SCU SFSP3_6: EZI Mask */ +#define SCU_SFSP3_6_ZIF_Pos 7 /*!< SCU SFSP3_6: ZIF Position */ +#define SCU_SFSP3_6_ZIF_Msk (0x01UL << SCU_SFSP3_6_ZIF_Pos) /*!< SCU SFSP3_6: ZIF Mask */ + +/* --------------------------------- SCU_SFSP3_7 -------------------------------- */ +#define SCU_SFSP3_7_MODE_Pos 0 /*!< SCU SFSP3_7: MODE Position */ +#define SCU_SFSP3_7_MODE_Msk (0x07UL << SCU_SFSP3_7_MODE_Pos) /*!< SCU SFSP3_7: MODE Mask */ +#define SCU_SFSP3_7_EPD_Pos 3 /*!< SCU SFSP3_7: EPD Position */ +#define SCU_SFSP3_7_EPD_Msk (0x01UL << SCU_SFSP3_7_EPD_Pos) /*!< SCU SFSP3_7: EPD Mask */ +#define SCU_SFSP3_7_EPUN_Pos 4 /*!< SCU SFSP3_7: EPUN Position */ +#define SCU_SFSP3_7_EPUN_Msk (0x01UL << SCU_SFSP3_7_EPUN_Pos) /*!< SCU SFSP3_7: EPUN Mask */ +#define SCU_SFSP3_7_EHS_Pos 5 /*!< SCU SFSP3_7: EHS Position */ +#define SCU_SFSP3_7_EHS_Msk (0x01UL << SCU_SFSP3_7_EHS_Pos) /*!< SCU SFSP3_7: EHS Mask */ +#define SCU_SFSP3_7_EZI_Pos 6 /*!< SCU SFSP3_7: EZI Position */ +#define SCU_SFSP3_7_EZI_Msk (0x01UL << SCU_SFSP3_7_EZI_Pos) /*!< SCU SFSP3_7: EZI Mask */ +#define SCU_SFSP3_7_ZIF_Pos 7 /*!< SCU SFSP3_7: ZIF Position */ +#define SCU_SFSP3_7_ZIF_Msk (0x01UL << SCU_SFSP3_7_ZIF_Pos) /*!< SCU SFSP3_7: ZIF Mask */ + +/* --------------------------------- SCU_SFSP3_8 -------------------------------- */ +#define SCU_SFSP3_8_MODE_Pos 0 /*!< SCU SFSP3_8: MODE Position */ +#define SCU_SFSP3_8_MODE_Msk (0x07UL << SCU_SFSP3_8_MODE_Pos) /*!< SCU SFSP3_8: MODE Mask */ +#define SCU_SFSP3_8_EPD_Pos 3 /*!< SCU SFSP3_8: EPD Position */ +#define SCU_SFSP3_8_EPD_Msk (0x01UL << SCU_SFSP3_8_EPD_Pos) /*!< SCU SFSP3_8: EPD Mask */ +#define SCU_SFSP3_8_EPUN_Pos 4 /*!< SCU SFSP3_8: EPUN Position */ +#define SCU_SFSP3_8_EPUN_Msk (0x01UL << SCU_SFSP3_8_EPUN_Pos) /*!< SCU SFSP3_8: EPUN Mask */ +#define SCU_SFSP3_8_EHS_Pos 5 /*!< SCU SFSP3_8: EHS Position */ +#define SCU_SFSP3_8_EHS_Msk (0x01UL << SCU_SFSP3_8_EHS_Pos) /*!< SCU SFSP3_8: EHS Mask */ +#define SCU_SFSP3_8_EZI_Pos 6 /*!< SCU SFSP3_8: EZI Position */ +#define SCU_SFSP3_8_EZI_Msk (0x01UL << SCU_SFSP3_8_EZI_Pos) /*!< SCU SFSP3_8: EZI Mask */ +#define SCU_SFSP3_8_ZIF_Pos 7 /*!< SCU SFSP3_8: ZIF Position */ +#define SCU_SFSP3_8_ZIF_Msk (0x01UL << SCU_SFSP3_8_ZIF_Pos) /*!< SCU SFSP3_8: ZIF Mask */ + +/* --------------------------------- SCU_SFSP4_0 -------------------------------- */ +#define SCU_SFSP4_0_MODE_Pos 0 /*!< SCU SFSP4_0: MODE Position */ +#define SCU_SFSP4_0_MODE_Msk (0x07UL << SCU_SFSP4_0_MODE_Pos) /*!< SCU SFSP4_0: MODE Mask */ +#define SCU_SFSP4_0_EPD_Pos 3 /*!< SCU SFSP4_0: EPD Position */ +#define SCU_SFSP4_0_EPD_Msk (0x01UL << SCU_SFSP4_0_EPD_Pos) /*!< SCU SFSP4_0: EPD Mask */ +#define SCU_SFSP4_0_EPUN_Pos 4 /*!< SCU SFSP4_0: EPUN Position */ +#define SCU_SFSP4_0_EPUN_Msk (0x01UL << SCU_SFSP4_0_EPUN_Pos) /*!< SCU SFSP4_0: EPUN Mask */ +#define SCU_SFSP4_0_EHS_Pos 5 /*!< SCU SFSP4_0: EHS Position */ +#define SCU_SFSP4_0_EHS_Msk (0x01UL << SCU_SFSP4_0_EHS_Pos) /*!< SCU SFSP4_0: EHS Mask */ +#define SCU_SFSP4_0_EZI_Pos 6 /*!< SCU SFSP4_0: EZI Position */ +#define SCU_SFSP4_0_EZI_Msk (0x01UL << SCU_SFSP4_0_EZI_Pos) /*!< SCU SFSP4_0: EZI Mask */ +#define SCU_SFSP4_0_ZIF_Pos 7 /*!< SCU SFSP4_0: ZIF Position */ +#define SCU_SFSP4_0_ZIF_Msk (0x01UL << SCU_SFSP4_0_ZIF_Pos) /*!< SCU SFSP4_0: ZIF Mask */ + +/* --------------------------------- SCU_SFSP4_1 -------------------------------- */ +#define SCU_SFSP4_1_MODE_Pos 0 /*!< SCU SFSP4_1: MODE Position */ +#define SCU_SFSP4_1_MODE_Msk (0x07UL << SCU_SFSP4_1_MODE_Pos) /*!< SCU SFSP4_1: MODE Mask */ +#define SCU_SFSP4_1_EPD_Pos 3 /*!< SCU SFSP4_1: EPD Position */ +#define SCU_SFSP4_1_EPD_Msk (0x01UL << SCU_SFSP4_1_EPD_Pos) /*!< SCU SFSP4_1: EPD Mask */ +#define SCU_SFSP4_1_EPUN_Pos 4 /*!< SCU SFSP4_1: EPUN Position */ +#define SCU_SFSP4_1_EPUN_Msk (0x01UL << SCU_SFSP4_1_EPUN_Pos) /*!< SCU SFSP4_1: EPUN Mask */ +#define SCU_SFSP4_1_EHS_Pos 5 /*!< SCU SFSP4_1: EHS Position */ +#define SCU_SFSP4_1_EHS_Msk (0x01UL << SCU_SFSP4_1_EHS_Pos) /*!< SCU SFSP4_1: EHS Mask */ +#define SCU_SFSP4_1_EZI_Pos 6 /*!< SCU SFSP4_1: EZI Position */ +#define SCU_SFSP4_1_EZI_Msk (0x01UL << SCU_SFSP4_1_EZI_Pos) /*!< SCU SFSP4_1: EZI Mask */ +#define SCU_SFSP4_1_ZIF_Pos 7 /*!< SCU SFSP4_1: ZIF Position */ +#define SCU_SFSP4_1_ZIF_Msk (0x01UL << SCU_SFSP4_1_ZIF_Pos) /*!< SCU SFSP4_1: ZIF Mask */ + +/* --------------------------------- SCU_SFSP4_2 -------------------------------- */ +#define SCU_SFSP4_2_MODE_Pos 0 /*!< SCU SFSP4_2: MODE Position */ +#define SCU_SFSP4_2_MODE_Msk (0x07UL << SCU_SFSP4_2_MODE_Pos) /*!< SCU SFSP4_2: MODE Mask */ +#define SCU_SFSP4_2_EPD_Pos 3 /*!< SCU SFSP4_2: EPD Position */ +#define SCU_SFSP4_2_EPD_Msk (0x01UL << SCU_SFSP4_2_EPD_Pos) /*!< SCU SFSP4_2: EPD Mask */ +#define SCU_SFSP4_2_EPUN_Pos 4 /*!< SCU SFSP4_2: EPUN Position */ +#define SCU_SFSP4_2_EPUN_Msk (0x01UL << SCU_SFSP4_2_EPUN_Pos) /*!< SCU SFSP4_2: EPUN Mask */ +#define SCU_SFSP4_2_EHS_Pos 5 /*!< SCU SFSP4_2: EHS Position */ +#define SCU_SFSP4_2_EHS_Msk (0x01UL << SCU_SFSP4_2_EHS_Pos) /*!< SCU SFSP4_2: EHS Mask */ +#define SCU_SFSP4_2_EZI_Pos 6 /*!< SCU SFSP4_2: EZI Position */ +#define SCU_SFSP4_2_EZI_Msk (0x01UL << SCU_SFSP4_2_EZI_Pos) /*!< SCU SFSP4_2: EZI Mask */ +#define SCU_SFSP4_2_ZIF_Pos 7 /*!< SCU SFSP4_2: ZIF Position */ +#define SCU_SFSP4_2_ZIF_Msk (0x01UL << SCU_SFSP4_2_ZIF_Pos) /*!< SCU SFSP4_2: ZIF Mask */ + +/* --------------------------------- SCU_SFSP4_3 -------------------------------- */ +#define SCU_SFSP4_3_MODE_Pos 0 /*!< SCU SFSP4_3: MODE Position */ +#define SCU_SFSP4_3_MODE_Msk (0x07UL << SCU_SFSP4_3_MODE_Pos) /*!< SCU SFSP4_3: MODE Mask */ +#define SCU_SFSP4_3_EPD_Pos 3 /*!< SCU SFSP4_3: EPD Position */ +#define SCU_SFSP4_3_EPD_Msk (0x01UL << SCU_SFSP4_3_EPD_Pos) /*!< SCU SFSP4_3: EPD Mask */ +#define SCU_SFSP4_3_EPUN_Pos 4 /*!< SCU SFSP4_3: EPUN Position */ +#define SCU_SFSP4_3_EPUN_Msk (0x01UL << SCU_SFSP4_3_EPUN_Pos) /*!< SCU SFSP4_3: EPUN Mask */ +#define SCU_SFSP4_3_EHS_Pos 5 /*!< SCU SFSP4_3: EHS Position */ +#define SCU_SFSP4_3_EHS_Msk (0x01UL << SCU_SFSP4_3_EHS_Pos) /*!< SCU SFSP4_3: EHS Mask */ +#define SCU_SFSP4_3_EZI_Pos 6 /*!< SCU SFSP4_3: EZI Position */ +#define SCU_SFSP4_3_EZI_Msk (0x01UL << SCU_SFSP4_3_EZI_Pos) /*!< SCU SFSP4_3: EZI Mask */ +#define SCU_SFSP4_3_ZIF_Pos 7 /*!< SCU SFSP4_3: ZIF Position */ +#define SCU_SFSP4_3_ZIF_Msk (0x01UL << SCU_SFSP4_3_ZIF_Pos) /*!< SCU SFSP4_3: ZIF Mask */ + +/* --------------------------------- SCU_SFSP4_4 -------------------------------- */ +#define SCU_SFSP4_4_MODE_Pos 0 /*!< SCU SFSP4_4: MODE Position */ +#define SCU_SFSP4_4_MODE_Msk (0x07UL << SCU_SFSP4_4_MODE_Pos) /*!< SCU SFSP4_4: MODE Mask */ +#define SCU_SFSP4_4_EPD_Pos 3 /*!< SCU SFSP4_4: EPD Position */ +#define SCU_SFSP4_4_EPD_Msk (0x01UL << SCU_SFSP4_4_EPD_Pos) /*!< SCU SFSP4_4: EPD Mask */ +#define SCU_SFSP4_4_EPUN_Pos 4 /*!< SCU SFSP4_4: EPUN Position */ +#define SCU_SFSP4_4_EPUN_Msk (0x01UL << SCU_SFSP4_4_EPUN_Pos) /*!< SCU SFSP4_4: EPUN Mask */ +#define SCU_SFSP4_4_EHS_Pos 5 /*!< SCU SFSP4_4: EHS Position */ +#define SCU_SFSP4_4_EHS_Msk (0x01UL << SCU_SFSP4_4_EHS_Pos) /*!< SCU SFSP4_4: EHS Mask */ +#define SCU_SFSP4_4_EZI_Pos 6 /*!< SCU SFSP4_4: EZI Position */ +#define SCU_SFSP4_4_EZI_Msk (0x01UL << SCU_SFSP4_4_EZI_Pos) /*!< SCU SFSP4_4: EZI Mask */ +#define SCU_SFSP4_4_ZIF_Pos 7 /*!< SCU SFSP4_4: ZIF Position */ +#define SCU_SFSP4_4_ZIF_Msk (0x01UL << SCU_SFSP4_4_ZIF_Pos) /*!< SCU SFSP4_4: ZIF Mask */ + +/* --------------------------------- SCU_SFSP4_5 -------------------------------- */ +#define SCU_SFSP4_5_MODE_Pos 0 /*!< SCU SFSP4_5: MODE Position */ +#define SCU_SFSP4_5_MODE_Msk (0x07UL << SCU_SFSP4_5_MODE_Pos) /*!< SCU SFSP4_5: MODE Mask */ +#define SCU_SFSP4_5_EPD_Pos 3 /*!< SCU SFSP4_5: EPD Position */ +#define SCU_SFSP4_5_EPD_Msk (0x01UL << SCU_SFSP4_5_EPD_Pos) /*!< SCU SFSP4_5: EPD Mask */ +#define SCU_SFSP4_5_EPUN_Pos 4 /*!< SCU SFSP4_5: EPUN Position */ +#define SCU_SFSP4_5_EPUN_Msk (0x01UL << SCU_SFSP4_5_EPUN_Pos) /*!< SCU SFSP4_5: EPUN Mask */ +#define SCU_SFSP4_5_EHS_Pos 5 /*!< SCU SFSP4_5: EHS Position */ +#define SCU_SFSP4_5_EHS_Msk (0x01UL << SCU_SFSP4_5_EHS_Pos) /*!< SCU SFSP4_5: EHS Mask */ +#define SCU_SFSP4_5_EZI_Pos 6 /*!< SCU SFSP4_5: EZI Position */ +#define SCU_SFSP4_5_EZI_Msk (0x01UL << SCU_SFSP4_5_EZI_Pos) /*!< SCU SFSP4_5: EZI Mask */ +#define SCU_SFSP4_5_ZIF_Pos 7 /*!< SCU SFSP4_5: ZIF Position */ +#define SCU_SFSP4_5_ZIF_Msk (0x01UL << SCU_SFSP4_5_ZIF_Pos) /*!< SCU SFSP4_5: ZIF Mask */ + +/* --------------------------------- SCU_SFSP4_6 -------------------------------- */ +#define SCU_SFSP4_6_MODE_Pos 0 /*!< SCU SFSP4_6: MODE Position */ +#define SCU_SFSP4_6_MODE_Msk (0x07UL << SCU_SFSP4_6_MODE_Pos) /*!< SCU SFSP4_6: MODE Mask */ +#define SCU_SFSP4_6_EPD_Pos 3 /*!< SCU SFSP4_6: EPD Position */ +#define SCU_SFSP4_6_EPD_Msk (0x01UL << SCU_SFSP4_6_EPD_Pos) /*!< SCU SFSP4_6: EPD Mask */ +#define SCU_SFSP4_6_EPUN_Pos 4 /*!< SCU SFSP4_6: EPUN Position */ +#define SCU_SFSP4_6_EPUN_Msk (0x01UL << SCU_SFSP4_6_EPUN_Pos) /*!< SCU SFSP4_6: EPUN Mask */ +#define SCU_SFSP4_6_EHS_Pos 5 /*!< SCU SFSP4_6: EHS Position */ +#define SCU_SFSP4_6_EHS_Msk (0x01UL << SCU_SFSP4_6_EHS_Pos) /*!< SCU SFSP4_6: EHS Mask */ +#define SCU_SFSP4_6_EZI_Pos 6 /*!< SCU SFSP4_6: EZI Position */ +#define SCU_SFSP4_6_EZI_Msk (0x01UL << SCU_SFSP4_6_EZI_Pos) /*!< SCU SFSP4_6: EZI Mask */ +#define SCU_SFSP4_6_ZIF_Pos 7 /*!< SCU SFSP4_6: ZIF Position */ +#define SCU_SFSP4_6_ZIF_Msk (0x01UL << SCU_SFSP4_6_ZIF_Pos) /*!< SCU SFSP4_6: ZIF Mask */ + +/* --------------------------------- SCU_SFSP4_7 -------------------------------- */ +#define SCU_SFSP4_7_MODE_Pos 0 /*!< SCU SFSP4_7: MODE Position */ +#define SCU_SFSP4_7_MODE_Msk (0x07UL << SCU_SFSP4_7_MODE_Pos) /*!< SCU SFSP4_7: MODE Mask */ +#define SCU_SFSP4_7_EPD_Pos 3 /*!< SCU SFSP4_7: EPD Position */ +#define SCU_SFSP4_7_EPD_Msk (0x01UL << SCU_SFSP4_7_EPD_Pos) /*!< SCU SFSP4_7: EPD Mask */ +#define SCU_SFSP4_7_EPUN_Pos 4 /*!< SCU SFSP4_7: EPUN Position */ +#define SCU_SFSP4_7_EPUN_Msk (0x01UL << SCU_SFSP4_7_EPUN_Pos) /*!< SCU SFSP4_7: EPUN Mask */ +#define SCU_SFSP4_7_EHS_Pos 5 /*!< SCU SFSP4_7: EHS Position */ +#define SCU_SFSP4_7_EHS_Msk (0x01UL << SCU_SFSP4_7_EHS_Pos) /*!< SCU SFSP4_7: EHS Mask */ +#define SCU_SFSP4_7_EZI_Pos 6 /*!< SCU SFSP4_7: EZI Position */ +#define SCU_SFSP4_7_EZI_Msk (0x01UL << SCU_SFSP4_7_EZI_Pos) /*!< SCU SFSP4_7: EZI Mask */ +#define SCU_SFSP4_7_ZIF_Pos 7 /*!< SCU SFSP4_7: ZIF Position */ +#define SCU_SFSP4_7_ZIF_Msk (0x01UL << SCU_SFSP4_7_ZIF_Pos) /*!< SCU SFSP4_7: ZIF Mask */ + +/* --------------------------------- SCU_SFSP4_8 -------------------------------- */ +#define SCU_SFSP4_8_MODE_Pos 0 /*!< SCU SFSP4_8: MODE Position */ +#define SCU_SFSP4_8_MODE_Msk (0x07UL << SCU_SFSP4_8_MODE_Pos) /*!< SCU SFSP4_8: MODE Mask */ +#define SCU_SFSP4_8_EPD_Pos 3 /*!< SCU SFSP4_8: EPD Position */ +#define SCU_SFSP4_8_EPD_Msk (0x01UL << SCU_SFSP4_8_EPD_Pos) /*!< SCU SFSP4_8: EPD Mask */ +#define SCU_SFSP4_8_EPUN_Pos 4 /*!< SCU SFSP4_8: EPUN Position */ +#define SCU_SFSP4_8_EPUN_Msk (0x01UL << SCU_SFSP4_8_EPUN_Pos) /*!< SCU SFSP4_8: EPUN Mask */ +#define SCU_SFSP4_8_EHS_Pos 5 /*!< SCU SFSP4_8: EHS Position */ +#define SCU_SFSP4_8_EHS_Msk (0x01UL << SCU_SFSP4_8_EHS_Pos) /*!< SCU SFSP4_8: EHS Mask */ +#define SCU_SFSP4_8_EZI_Pos 6 /*!< SCU SFSP4_8: EZI Position */ +#define SCU_SFSP4_8_EZI_Msk (0x01UL << SCU_SFSP4_8_EZI_Pos) /*!< SCU SFSP4_8: EZI Mask */ +#define SCU_SFSP4_8_ZIF_Pos 7 /*!< SCU SFSP4_8: ZIF Position */ +#define SCU_SFSP4_8_ZIF_Msk (0x01UL << SCU_SFSP4_8_ZIF_Pos) /*!< SCU SFSP4_8: ZIF Mask */ + +/* --------------------------------- SCU_SFSP4_9 -------------------------------- */ +#define SCU_SFSP4_9_MODE_Pos 0 /*!< SCU SFSP4_9: MODE Position */ +#define SCU_SFSP4_9_MODE_Msk (0x07UL << SCU_SFSP4_9_MODE_Pos) /*!< SCU SFSP4_9: MODE Mask */ +#define SCU_SFSP4_9_EPD_Pos 3 /*!< SCU SFSP4_9: EPD Position */ +#define SCU_SFSP4_9_EPD_Msk (0x01UL << SCU_SFSP4_9_EPD_Pos) /*!< SCU SFSP4_9: EPD Mask */ +#define SCU_SFSP4_9_EPUN_Pos 4 /*!< SCU SFSP4_9: EPUN Position */ +#define SCU_SFSP4_9_EPUN_Msk (0x01UL << SCU_SFSP4_9_EPUN_Pos) /*!< SCU SFSP4_9: EPUN Mask */ +#define SCU_SFSP4_9_EHS_Pos 5 /*!< SCU SFSP4_9: EHS Position */ +#define SCU_SFSP4_9_EHS_Msk (0x01UL << SCU_SFSP4_9_EHS_Pos) /*!< SCU SFSP4_9: EHS Mask */ +#define SCU_SFSP4_9_EZI_Pos 6 /*!< SCU SFSP4_9: EZI Position */ +#define SCU_SFSP4_9_EZI_Msk (0x01UL << SCU_SFSP4_9_EZI_Pos) /*!< SCU SFSP4_9: EZI Mask */ +#define SCU_SFSP4_9_ZIF_Pos 7 /*!< SCU SFSP4_9: ZIF Position */ +#define SCU_SFSP4_9_ZIF_Msk (0x01UL << SCU_SFSP4_9_ZIF_Pos) /*!< SCU SFSP4_9: ZIF Mask */ + +/* -------------------------------- SCU_SFSP4_10 -------------------------------- */ +#define SCU_SFSP4_10_MODE_Pos 0 /*!< SCU SFSP4_10: MODE Position */ +#define SCU_SFSP4_10_MODE_Msk (0x07UL << SCU_SFSP4_10_MODE_Pos) /*!< SCU SFSP4_10: MODE Mask */ +#define SCU_SFSP4_10_EPD_Pos 3 /*!< SCU SFSP4_10: EPD Position */ +#define SCU_SFSP4_10_EPD_Msk (0x01UL << SCU_SFSP4_10_EPD_Pos) /*!< SCU SFSP4_10: EPD Mask */ +#define SCU_SFSP4_10_EPUN_Pos 4 /*!< SCU SFSP4_10: EPUN Position */ +#define SCU_SFSP4_10_EPUN_Msk (0x01UL << SCU_SFSP4_10_EPUN_Pos) /*!< SCU SFSP4_10: EPUN Mask */ +#define SCU_SFSP4_10_EHS_Pos 5 /*!< SCU SFSP4_10: EHS Position */ +#define SCU_SFSP4_10_EHS_Msk (0x01UL << SCU_SFSP4_10_EHS_Pos) /*!< SCU SFSP4_10: EHS Mask */ +#define SCU_SFSP4_10_EZI_Pos 6 /*!< SCU SFSP4_10: EZI Position */ +#define SCU_SFSP4_10_EZI_Msk (0x01UL << SCU_SFSP4_10_EZI_Pos) /*!< SCU SFSP4_10: EZI Mask */ +#define SCU_SFSP4_10_ZIF_Pos 7 /*!< SCU SFSP4_10: ZIF Position */ +#define SCU_SFSP4_10_ZIF_Msk (0x01UL << SCU_SFSP4_10_ZIF_Pos) /*!< SCU SFSP4_10: ZIF Mask */ + +/* --------------------------------- SCU_SFSP5_0 -------------------------------- */ +#define SCU_SFSP5_0_MODE_Pos 0 /*!< SCU SFSP5_0: MODE Position */ +#define SCU_SFSP5_0_MODE_Msk (0x07UL << SCU_SFSP5_0_MODE_Pos) /*!< SCU SFSP5_0: MODE Mask */ +#define SCU_SFSP5_0_EPD_Pos 3 /*!< SCU SFSP5_0: EPD Position */ +#define SCU_SFSP5_0_EPD_Msk (0x01UL << SCU_SFSP5_0_EPD_Pos) /*!< SCU SFSP5_0: EPD Mask */ +#define SCU_SFSP5_0_EPUN_Pos 4 /*!< SCU SFSP5_0: EPUN Position */ +#define SCU_SFSP5_0_EPUN_Msk (0x01UL << SCU_SFSP5_0_EPUN_Pos) /*!< SCU SFSP5_0: EPUN Mask */ +#define SCU_SFSP5_0_EHS_Pos 5 /*!< SCU SFSP5_0: EHS Position */ +#define SCU_SFSP5_0_EHS_Msk (0x01UL << SCU_SFSP5_0_EHS_Pos) /*!< SCU SFSP5_0: EHS Mask */ +#define SCU_SFSP5_0_EZI_Pos 6 /*!< SCU SFSP5_0: EZI Position */ +#define SCU_SFSP5_0_EZI_Msk (0x01UL << SCU_SFSP5_0_EZI_Pos) /*!< SCU SFSP5_0: EZI Mask */ +#define SCU_SFSP5_0_ZIF_Pos 7 /*!< SCU SFSP5_0: ZIF Position */ +#define SCU_SFSP5_0_ZIF_Msk (0x01UL << SCU_SFSP5_0_ZIF_Pos) /*!< SCU SFSP5_0: ZIF Mask */ + +/* --------------------------------- SCU_SFSP5_1 -------------------------------- */ +#define SCU_SFSP5_1_MODE_Pos 0 /*!< SCU SFSP5_1: MODE Position */ +#define SCU_SFSP5_1_MODE_Msk (0x07UL << SCU_SFSP5_1_MODE_Pos) /*!< SCU SFSP5_1: MODE Mask */ +#define SCU_SFSP5_1_EPD_Pos 3 /*!< SCU SFSP5_1: EPD Position */ +#define SCU_SFSP5_1_EPD_Msk (0x01UL << SCU_SFSP5_1_EPD_Pos) /*!< SCU SFSP5_1: EPD Mask */ +#define SCU_SFSP5_1_EPUN_Pos 4 /*!< SCU SFSP5_1: EPUN Position */ +#define SCU_SFSP5_1_EPUN_Msk (0x01UL << SCU_SFSP5_1_EPUN_Pos) /*!< SCU SFSP5_1: EPUN Mask */ +#define SCU_SFSP5_1_EHS_Pos 5 /*!< SCU SFSP5_1: EHS Position */ +#define SCU_SFSP5_1_EHS_Msk (0x01UL << SCU_SFSP5_1_EHS_Pos) /*!< SCU SFSP5_1: EHS Mask */ +#define SCU_SFSP5_1_EZI_Pos 6 /*!< SCU SFSP5_1: EZI Position */ +#define SCU_SFSP5_1_EZI_Msk (0x01UL << SCU_SFSP5_1_EZI_Pos) /*!< SCU SFSP5_1: EZI Mask */ +#define SCU_SFSP5_1_ZIF_Pos 7 /*!< SCU SFSP5_1: ZIF Position */ +#define SCU_SFSP5_1_ZIF_Msk (0x01UL << SCU_SFSP5_1_ZIF_Pos) /*!< SCU SFSP5_1: ZIF Mask */ + +/* --------------------------------- SCU_SFSP5_2 -------------------------------- */ +#define SCU_SFSP5_2_MODE_Pos 0 /*!< SCU SFSP5_2: MODE Position */ +#define SCU_SFSP5_2_MODE_Msk (0x07UL << SCU_SFSP5_2_MODE_Pos) /*!< SCU SFSP5_2: MODE Mask */ +#define SCU_SFSP5_2_EPD_Pos 3 /*!< SCU SFSP5_2: EPD Position */ +#define SCU_SFSP5_2_EPD_Msk (0x01UL << SCU_SFSP5_2_EPD_Pos) /*!< SCU SFSP5_2: EPD Mask */ +#define SCU_SFSP5_2_EPUN_Pos 4 /*!< SCU SFSP5_2: EPUN Position */ +#define SCU_SFSP5_2_EPUN_Msk (0x01UL << SCU_SFSP5_2_EPUN_Pos) /*!< SCU SFSP5_2: EPUN Mask */ +#define SCU_SFSP5_2_EHS_Pos 5 /*!< SCU SFSP5_2: EHS Position */ +#define SCU_SFSP5_2_EHS_Msk (0x01UL << SCU_SFSP5_2_EHS_Pos) /*!< SCU SFSP5_2: EHS Mask */ +#define SCU_SFSP5_2_EZI_Pos 6 /*!< SCU SFSP5_2: EZI Position */ +#define SCU_SFSP5_2_EZI_Msk (0x01UL << SCU_SFSP5_2_EZI_Pos) /*!< SCU SFSP5_2: EZI Mask */ +#define SCU_SFSP5_2_ZIF_Pos 7 /*!< SCU SFSP5_2: ZIF Position */ +#define SCU_SFSP5_2_ZIF_Msk (0x01UL << SCU_SFSP5_2_ZIF_Pos) /*!< SCU SFSP5_2: ZIF Mask */ + +/* --------------------------------- SCU_SFSP5_3 -------------------------------- */ +#define SCU_SFSP5_3_MODE_Pos 0 /*!< SCU SFSP5_3: MODE Position */ +#define SCU_SFSP5_3_MODE_Msk (0x07UL << SCU_SFSP5_3_MODE_Pos) /*!< SCU SFSP5_3: MODE Mask */ +#define SCU_SFSP5_3_EPD_Pos 3 /*!< SCU SFSP5_3: EPD Position */ +#define SCU_SFSP5_3_EPD_Msk (0x01UL << SCU_SFSP5_3_EPD_Pos) /*!< SCU SFSP5_3: EPD Mask */ +#define SCU_SFSP5_3_EPUN_Pos 4 /*!< SCU SFSP5_3: EPUN Position */ +#define SCU_SFSP5_3_EPUN_Msk (0x01UL << SCU_SFSP5_3_EPUN_Pos) /*!< SCU SFSP5_3: EPUN Mask */ +#define SCU_SFSP5_3_EHS_Pos 5 /*!< SCU SFSP5_3: EHS Position */ +#define SCU_SFSP5_3_EHS_Msk (0x01UL << SCU_SFSP5_3_EHS_Pos) /*!< SCU SFSP5_3: EHS Mask */ +#define SCU_SFSP5_3_EZI_Pos 6 /*!< SCU SFSP5_3: EZI Position */ +#define SCU_SFSP5_3_EZI_Msk (0x01UL << SCU_SFSP5_3_EZI_Pos) /*!< SCU SFSP5_3: EZI Mask */ +#define SCU_SFSP5_3_ZIF_Pos 7 /*!< SCU SFSP5_3: ZIF Position */ +#define SCU_SFSP5_3_ZIF_Msk (0x01UL << SCU_SFSP5_3_ZIF_Pos) /*!< SCU SFSP5_3: ZIF Mask */ + +/* --------------------------------- SCU_SFSP5_4 -------------------------------- */ +#define SCU_SFSP5_4_MODE_Pos 0 /*!< SCU SFSP5_4: MODE Position */ +#define SCU_SFSP5_4_MODE_Msk (0x07UL << SCU_SFSP5_4_MODE_Pos) /*!< SCU SFSP5_4: MODE Mask */ +#define SCU_SFSP5_4_EPD_Pos 3 /*!< SCU SFSP5_4: EPD Position */ +#define SCU_SFSP5_4_EPD_Msk (0x01UL << SCU_SFSP5_4_EPD_Pos) /*!< SCU SFSP5_4: EPD Mask */ +#define SCU_SFSP5_4_EPUN_Pos 4 /*!< SCU SFSP5_4: EPUN Position */ +#define SCU_SFSP5_4_EPUN_Msk (0x01UL << SCU_SFSP5_4_EPUN_Pos) /*!< SCU SFSP5_4: EPUN Mask */ +#define SCU_SFSP5_4_EHS_Pos 5 /*!< SCU SFSP5_4: EHS Position */ +#define SCU_SFSP5_4_EHS_Msk (0x01UL << SCU_SFSP5_4_EHS_Pos) /*!< SCU SFSP5_4: EHS Mask */ +#define SCU_SFSP5_4_EZI_Pos 6 /*!< SCU SFSP5_4: EZI Position */ +#define SCU_SFSP5_4_EZI_Msk (0x01UL << SCU_SFSP5_4_EZI_Pos) /*!< SCU SFSP5_4: EZI Mask */ +#define SCU_SFSP5_4_ZIF_Pos 7 /*!< SCU SFSP5_4: ZIF Position */ +#define SCU_SFSP5_4_ZIF_Msk (0x01UL << SCU_SFSP5_4_ZIF_Pos) /*!< SCU SFSP5_4: ZIF Mask */ + +/* --------------------------------- SCU_SFSP5_5 -------------------------------- */ +#define SCU_SFSP5_5_MODE_Pos 0 /*!< SCU SFSP5_5: MODE Position */ +#define SCU_SFSP5_5_MODE_Msk (0x07UL << SCU_SFSP5_5_MODE_Pos) /*!< SCU SFSP5_5: MODE Mask */ +#define SCU_SFSP5_5_EPD_Pos 3 /*!< SCU SFSP5_5: EPD Position */ +#define SCU_SFSP5_5_EPD_Msk (0x01UL << SCU_SFSP5_5_EPD_Pos) /*!< SCU SFSP5_5: EPD Mask */ +#define SCU_SFSP5_5_EPUN_Pos 4 /*!< SCU SFSP5_5: EPUN Position */ +#define SCU_SFSP5_5_EPUN_Msk (0x01UL << SCU_SFSP5_5_EPUN_Pos) /*!< SCU SFSP5_5: EPUN Mask */ +#define SCU_SFSP5_5_EHS_Pos 5 /*!< SCU SFSP5_5: EHS Position */ +#define SCU_SFSP5_5_EHS_Msk (0x01UL << SCU_SFSP5_5_EHS_Pos) /*!< SCU SFSP5_5: EHS Mask */ +#define SCU_SFSP5_5_EZI_Pos 6 /*!< SCU SFSP5_5: EZI Position */ +#define SCU_SFSP5_5_EZI_Msk (0x01UL << SCU_SFSP5_5_EZI_Pos) /*!< SCU SFSP5_5: EZI Mask */ +#define SCU_SFSP5_5_ZIF_Pos 7 /*!< SCU SFSP5_5: ZIF Position */ +#define SCU_SFSP5_5_ZIF_Msk (0x01UL << SCU_SFSP5_5_ZIF_Pos) /*!< SCU SFSP5_5: ZIF Mask */ + +/* --------------------------------- SCU_SFSP5_6 -------------------------------- */ +#define SCU_SFSP5_6_MODE_Pos 0 /*!< SCU SFSP5_6: MODE Position */ +#define SCU_SFSP5_6_MODE_Msk (0x07UL << SCU_SFSP5_6_MODE_Pos) /*!< SCU SFSP5_6: MODE Mask */ +#define SCU_SFSP5_6_EPD_Pos 3 /*!< SCU SFSP5_6: EPD Position */ +#define SCU_SFSP5_6_EPD_Msk (0x01UL << SCU_SFSP5_6_EPD_Pos) /*!< SCU SFSP5_6: EPD Mask */ +#define SCU_SFSP5_6_EPUN_Pos 4 /*!< SCU SFSP5_6: EPUN Position */ +#define SCU_SFSP5_6_EPUN_Msk (0x01UL << SCU_SFSP5_6_EPUN_Pos) /*!< SCU SFSP5_6: EPUN Mask */ +#define SCU_SFSP5_6_EHS_Pos 5 /*!< SCU SFSP5_6: EHS Position */ +#define SCU_SFSP5_6_EHS_Msk (0x01UL << SCU_SFSP5_6_EHS_Pos) /*!< SCU SFSP5_6: EHS Mask */ +#define SCU_SFSP5_6_EZI_Pos 6 /*!< SCU SFSP5_6: EZI Position */ +#define SCU_SFSP5_6_EZI_Msk (0x01UL << SCU_SFSP5_6_EZI_Pos) /*!< SCU SFSP5_6: EZI Mask */ +#define SCU_SFSP5_6_ZIF_Pos 7 /*!< SCU SFSP5_6: ZIF Position */ +#define SCU_SFSP5_6_ZIF_Msk (0x01UL << SCU_SFSP5_6_ZIF_Pos) /*!< SCU SFSP5_6: ZIF Mask */ + +/* --------------------------------- SCU_SFSP5_7 -------------------------------- */ +#define SCU_SFSP5_7_MODE_Pos 0 /*!< SCU SFSP5_7: MODE Position */ +#define SCU_SFSP5_7_MODE_Msk (0x07UL << SCU_SFSP5_7_MODE_Pos) /*!< SCU SFSP5_7: MODE Mask */ +#define SCU_SFSP5_7_EPD_Pos 3 /*!< SCU SFSP5_7: EPD Position */ +#define SCU_SFSP5_7_EPD_Msk (0x01UL << SCU_SFSP5_7_EPD_Pos) /*!< SCU SFSP5_7: EPD Mask */ +#define SCU_SFSP5_7_EPUN_Pos 4 /*!< SCU SFSP5_7: EPUN Position */ +#define SCU_SFSP5_7_EPUN_Msk (0x01UL << SCU_SFSP5_7_EPUN_Pos) /*!< SCU SFSP5_7: EPUN Mask */ +#define SCU_SFSP5_7_EHS_Pos 5 /*!< SCU SFSP5_7: EHS Position */ +#define SCU_SFSP5_7_EHS_Msk (0x01UL << SCU_SFSP5_7_EHS_Pos) /*!< SCU SFSP5_7: EHS Mask */ +#define SCU_SFSP5_7_EZI_Pos 6 /*!< SCU SFSP5_7: EZI Position */ +#define SCU_SFSP5_7_EZI_Msk (0x01UL << SCU_SFSP5_7_EZI_Pos) /*!< SCU SFSP5_7: EZI Mask */ +#define SCU_SFSP5_7_ZIF_Pos 7 /*!< SCU SFSP5_7: ZIF Position */ +#define SCU_SFSP5_7_ZIF_Msk (0x01UL << SCU_SFSP5_7_ZIF_Pos) /*!< SCU SFSP5_7: ZIF Mask */ + +/* --------------------------------- SCU_SFSP6_0 -------------------------------- */ +#define SCU_SFSP6_0_MODE_Pos 0 /*!< SCU SFSP6_0: MODE Position */ +#define SCU_SFSP6_0_MODE_Msk (0x07UL << SCU_SFSP6_0_MODE_Pos) /*!< SCU SFSP6_0: MODE Mask */ +#define SCU_SFSP6_0_EPD_Pos 3 /*!< SCU SFSP6_0: EPD Position */ +#define SCU_SFSP6_0_EPD_Msk (0x01UL << SCU_SFSP6_0_EPD_Pos) /*!< SCU SFSP6_0: EPD Mask */ +#define SCU_SFSP6_0_EPUN_Pos 4 /*!< SCU SFSP6_0: EPUN Position */ +#define SCU_SFSP6_0_EPUN_Msk (0x01UL << SCU_SFSP6_0_EPUN_Pos) /*!< SCU SFSP6_0: EPUN Mask */ +#define SCU_SFSP6_0_EHS_Pos 5 /*!< SCU SFSP6_0: EHS Position */ +#define SCU_SFSP6_0_EHS_Msk (0x01UL << SCU_SFSP6_0_EHS_Pos) /*!< SCU SFSP6_0: EHS Mask */ +#define SCU_SFSP6_0_EZI_Pos 6 /*!< SCU SFSP6_0: EZI Position */ +#define SCU_SFSP6_0_EZI_Msk (0x01UL << SCU_SFSP6_0_EZI_Pos) /*!< SCU SFSP6_0: EZI Mask */ +#define SCU_SFSP6_0_ZIF_Pos 7 /*!< SCU SFSP6_0: ZIF Position */ +#define SCU_SFSP6_0_ZIF_Msk (0x01UL << SCU_SFSP6_0_ZIF_Pos) /*!< SCU SFSP6_0: ZIF Mask */ + +/* --------------------------------- SCU_SFSP6_1 -------------------------------- */ +#define SCU_SFSP6_1_MODE_Pos 0 /*!< SCU SFSP6_1: MODE Position */ +#define SCU_SFSP6_1_MODE_Msk (0x07UL << SCU_SFSP6_1_MODE_Pos) /*!< SCU SFSP6_1: MODE Mask */ +#define SCU_SFSP6_1_EPD_Pos 3 /*!< SCU SFSP6_1: EPD Position */ +#define SCU_SFSP6_1_EPD_Msk (0x01UL << SCU_SFSP6_1_EPD_Pos) /*!< SCU SFSP6_1: EPD Mask */ +#define SCU_SFSP6_1_EPUN_Pos 4 /*!< SCU SFSP6_1: EPUN Position */ +#define SCU_SFSP6_1_EPUN_Msk (0x01UL << SCU_SFSP6_1_EPUN_Pos) /*!< SCU SFSP6_1: EPUN Mask */ +#define SCU_SFSP6_1_EHS_Pos 5 /*!< SCU SFSP6_1: EHS Position */ +#define SCU_SFSP6_1_EHS_Msk (0x01UL << SCU_SFSP6_1_EHS_Pos) /*!< SCU SFSP6_1: EHS Mask */ +#define SCU_SFSP6_1_EZI_Pos 6 /*!< SCU SFSP6_1: EZI Position */ +#define SCU_SFSP6_1_EZI_Msk (0x01UL << SCU_SFSP6_1_EZI_Pos) /*!< SCU SFSP6_1: EZI Mask */ +#define SCU_SFSP6_1_ZIF_Pos 7 /*!< SCU SFSP6_1: ZIF Position */ +#define SCU_SFSP6_1_ZIF_Msk (0x01UL << SCU_SFSP6_1_ZIF_Pos) /*!< SCU SFSP6_1: ZIF Mask */ + +/* --------------------------------- SCU_SFSP6_2 -------------------------------- */ +#define SCU_SFSP6_2_MODE_Pos 0 /*!< SCU SFSP6_2: MODE Position */ +#define SCU_SFSP6_2_MODE_Msk (0x07UL << SCU_SFSP6_2_MODE_Pos) /*!< SCU SFSP6_2: MODE Mask */ +#define SCU_SFSP6_2_EPD_Pos 3 /*!< SCU SFSP6_2: EPD Position */ +#define SCU_SFSP6_2_EPD_Msk (0x01UL << SCU_SFSP6_2_EPD_Pos) /*!< SCU SFSP6_2: EPD Mask */ +#define SCU_SFSP6_2_EPUN_Pos 4 /*!< SCU SFSP6_2: EPUN Position */ +#define SCU_SFSP6_2_EPUN_Msk (0x01UL << SCU_SFSP6_2_EPUN_Pos) /*!< SCU SFSP6_2: EPUN Mask */ +#define SCU_SFSP6_2_EHS_Pos 5 /*!< SCU SFSP6_2: EHS Position */ +#define SCU_SFSP6_2_EHS_Msk (0x01UL << SCU_SFSP6_2_EHS_Pos) /*!< SCU SFSP6_2: EHS Mask */ +#define SCU_SFSP6_2_EZI_Pos 6 /*!< SCU SFSP6_2: EZI Position */ +#define SCU_SFSP6_2_EZI_Msk (0x01UL << SCU_SFSP6_2_EZI_Pos) /*!< SCU SFSP6_2: EZI Mask */ +#define SCU_SFSP6_2_ZIF_Pos 7 /*!< SCU SFSP6_2: ZIF Position */ +#define SCU_SFSP6_2_ZIF_Msk (0x01UL << SCU_SFSP6_2_ZIF_Pos) /*!< SCU SFSP6_2: ZIF Mask */ + +/* --------------------------------- SCU_SFSP6_3 -------------------------------- */ +#define SCU_SFSP6_3_MODE_Pos 0 /*!< SCU SFSP6_3: MODE Position */ +#define SCU_SFSP6_3_MODE_Msk (0x07UL << SCU_SFSP6_3_MODE_Pos) /*!< SCU SFSP6_3: MODE Mask */ +#define SCU_SFSP6_3_EPD_Pos 3 /*!< SCU SFSP6_3: EPD Position */ +#define SCU_SFSP6_3_EPD_Msk (0x01UL << SCU_SFSP6_3_EPD_Pos) /*!< SCU SFSP6_3: EPD Mask */ +#define SCU_SFSP6_3_EPUN_Pos 4 /*!< SCU SFSP6_3: EPUN Position */ +#define SCU_SFSP6_3_EPUN_Msk (0x01UL << SCU_SFSP6_3_EPUN_Pos) /*!< SCU SFSP6_3: EPUN Mask */ +#define SCU_SFSP6_3_EHS_Pos 5 /*!< SCU SFSP6_3: EHS Position */ +#define SCU_SFSP6_3_EHS_Msk (0x01UL << SCU_SFSP6_3_EHS_Pos) /*!< SCU SFSP6_3: EHS Mask */ +#define SCU_SFSP6_3_EZI_Pos 6 /*!< SCU SFSP6_3: EZI Position */ +#define SCU_SFSP6_3_EZI_Msk (0x01UL << SCU_SFSP6_3_EZI_Pos) /*!< SCU SFSP6_3: EZI Mask */ +#define SCU_SFSP6_3_ZIF_Pos 7 /*!< SCU SFSP6_3: ZIF Position */ +#define SCU_SFSP6_3_ZIF_Msk (0x01UL << SCU_SFSP6_3_ZIF_Pos) /*!< SCU SFSP6_3: ZIF Mask */ + +/* --------------------------------- SCU_SFSP6_4 -------------------------------- */ +#define SCU_SFSP6_4_MODE_Pos 0 /*!< SCU SFSP6_4: MODE Position */ +#define SCU_SFSP6_4_MODE_Msk (0x07UL << SCU_SFSP6_4_MODE_Pos) /*!< SCU SFSP6_4: MODE Mask */ +#define SCU_SFSP6_4_EPD_Pos 3 /*!< SCU SFSP6_4: EPD Position */ +#define SCU_SFSP6_4_EPD_Msk (0x01UL << SCU_SFSP6_4_EPD_Pos) /*!< SCU SFSP6_4: EPD Mask */ +#define SCU_SFSP6_4_EPUN_Pos 4 /*!< SCU SFSP6_4: EPUN Position */ +#define SCU_SFSP6_4_EPUN_Msk (0x01UL << SCU_SFSP6_4_EPUN_Pos) /*!< SCU SFSP6_4: EPUN Mask */ +#define SCU_SFSP6_4_EHS_Pos 5 /*!< SCU SFSP6_4: EHS Position */ +#define SCU_SFSP6_4_EHS_Msk (0x01UL << SCU_SFSP6_4_EHS_Pos) /*!< SCU SFSP6_4: EHS Mask */ +#define SCU_SFSP6_4_EZI_Pos 6 /*!< SCU SFSP6_4: EZI Position */ +#define SCU_SFSP6_4_EZI_Msk (0x01UL << SCU_SFSP6_4_EZI_Pos) /*!< SCU SFSP6_4: EZI Mask */ +#define SCU_SFSP6_4_ZIF_Pos 7 /*!< SCU SFSP6_4: ZIF Position */ +#define SCU_SFSP6_4_ZIF_Msk (0x01UL << SCU_SFSP6_4_ZIF_Pos) /*!< SCU SFSP6_4: ZIF Mask */ + +/* --------------------------------- SCU_SFSP6_5 -------------------------------- */ +#define SCU_SFSP6_5_MODE_Pos 0 /*!< SCU SFSP6_5: MODE Position */ +#define SCU_SFSP6_5_MODE_Msk (0x07UL << SCU_SFSP6_5_MODE_Pos) /*!< SCU SFSP6_5: MODE Mask */ +#define SCU_SFSP6_5_EPD_Pos 3 /*!< SCU SFSP6_5: EPD Position */ +#define SCU_SFSP6_5_EPD_Msk (0x01UL << SCU_SFSP6_5_EPD_Pos) /*!< SCU SFSP6_5: EPD Mask */ +#define SCU_SFSP6_5_EPUN_Pos 4 /*!< SCU SFSP6_5: EPUN Position */ +#define SCU_SFSP6_5_EPUN_Msk (0x01UL << SCU_SFSP6_5_EPUN_Pos) /*!< SCU SFSP6_5: EPUN Mask */ +#define SCU_SFSP6_5_EHS_Pos 5 /*!< SCU SFSP6_5: EHS Position */ +#define SCU_SFSP6_5_EHS_Msk (0x01UL << SCU_SFSP6_5_EHS_Pos) /*!< SCU SFSP6_5: EHS Mask */ +#define SCU_SFSP6_5_EZI_Pos 6 /*!< SCU SFSP6_5: EZI Position */ +#define SCU_SFSP6_5_EZI_Msk (0x01UL << SCU_SFSP6_5_EZI_Pos) /*!< SCU SFSP6_5: EZI Mask */ +#define SCU_SFSP6_5_ZIF_Pos 7 /*!< SCU SFSP6_5: ZIF Position */ +#define SCU_SFSP6_5_ZIF_Msk (0x01UL << SCU_SFSP6_5_ZIF_Pos) /*!< SCU SFSP6_5: ZIF Mask */ + +/* --------------------------------- SCU_SFSP6_6 -------------------------------- */ +#define SCU_SFSP6_6_MODE_Pos 0 /*!< SCU SFSP6_6: MODE Position */ +#define SCU_SFSP6_6_MODE_Msk (0x07UL << SCU_SFSP6_6_MODE_Pos) /*!< SCU SFSP6_6: MODE Mask */ +#define SCU_SFSP6_6_EPD_Pos 3 /*!< SCU SFSP6_6: EPD Position */ +#define SCU_SFSP6_6_EPD_Msk (0x01UL << SCU_SFSP6_6_EPD_Pos) /*!< SCU SFSP6_6: EPD Mask */ +#define SCU_SFSP6_6_EPUN_Pos 4 /*!< SCU SFSP6_6: EPUN Position */ +#define SCU_SFSP6_6_EPUN_Msk (0x01UL << SCU_SFSP6_6_EPUN_Pos) /*!< SCU SFSP6_6: EPUN Mask */ +#define SCU_SFSP6_6_EHS_Pos 5 /*!< SCU SFSP6_6: EHS Position */ +#define SCU_SFSP6_6_EHS_Msk (0x01UL << SCU_SFSP6_6_EHS_Pos) /*!< SCU SFSP6_6: EHS Mask */ +#define SCU_SFSP6_6_EZI_Pos 6 /*!< SCU SFSP6_6: EZI Position */ +#define SCU_SFSP6_6_EZI_Msk (0x01UL << SCU_SFSP6_6_EZI_Pos) /*!< SCU SFSP6_6: EZI Mask */ +#define SCU_SFSP6_6_ZIF_Pos 7 /*!< SCU SFSP6_6: ZIF Position */ +#define SCU_SFSP6_6_ZIF_Msk (0x01UL << SCU_SFSP6_6_ZIF_Pos) /*!< SCU SFSP6_6: ZIF Mask */ + +/* --------------------------------- SCU_SFSP6_7 -------------------------------- */ +#define SCU_SFSP6_7_MODE_Pos 0 /*!< SCU SFSP6_7: MODE Position */ +#define SCU_SFSP6_7_MODE_Msk (0x07UL << SCU_SFSP6_7_MODE_Pos) /*!< SCU SFSP6_7: MODE Mask */ +#define SCU_SFSP6_7_EPD_Pos 3 /*!< SCU SFSP6_7: EPD Position */ +#define SCU_SFSP6_7_EPD_Msk (0x01UL << SCU_SFSP6_7_EPD_Pos) /*!< SCU SFSP6_7: EPD Mask */ +#define SCU_SFSP6_7_EPUN_Pos 4 /*!< SCU SFSP6_7: EPUN Position */ +#define SCU_SFSP6_7_EPUN_Msk (0x01UL << SCU_SFSP6_7_EPUN_Pos) /*!< SCU SFSP6_7: EPUN Mask */ +#define SCU_SFSP6_7_EHS_Pos 5 /*!< SCU SFSP6_7: EHS Position */ +#define SCU_SFSP6_7_EHS_Msk (0x01UL << SCU_SFSP6_7_EHS_Pos) /*!< SCU SFSP6_7: EHS Mask */ +#define SCU_SFSP6_7_EZI_Pos 6 /*!< SCU SFSP6_7: EZI Position */ +#define SCU_SFSP6_7_EZI_Msk (0x01UL << SCU_SFSP6_7_EZI_Pos) /*!< SCU SFSP6_7: EZI Mask */ +#define SCU_SFSP6_7_ZIF_Pos 7 /*!< SCU SFSP6_7: ZIF Position */ +#define SCU_SFSP6_7_ZIF_Msk (0x01UL << SCU_SFSP6_7_ZIF_Pos) /*!< SCU SFSP6_7: ZIF Mask */ + +/* --------------------------------- SCU_SFSP6_8 -------------------------------- */ +#define SCU_SFSP6_8_MODE_Pos 0 /*!< SCU SFSP6_8: MODE Position */ +#define SCU_SFSP6_8_MODE_Msk (0x07UL << SCU_SFSP6_8_MODE_Pos) /*!< SCU SFSP6_8: MODE Mask */ +#define SCU_SFSP6_8_EPD_Pos 3 /*!< SCU SFSP6_8: EPD Position */ +#define SCU_SFSP6_8_EPD_Msk (0x01UL << SCU_SFSP6_8_EPD_Pos) /*!< SCU SFSP6_8: EPD Mask */ +#define SCU_SFSP6_8_EPUN_Pos 4 /*!< SCU SFSP6_8: EPUN Position */ +#define SCU_SFSP6_8_EPUN_Msk (0x01UL << SCU_SFSP6_8_EPUN_Pos) /*!< SCU SFSP6_8: EPUN Mask */ +#define SCU_SFSP6_8_EHS_Pos 5 /*!< SCU SFSP6_8: EHS Position */ +#define SCU_SFSP6_8_EHS_Msk (0x01UL << SCU_SFSP6_8_EHS_Pos) /*!< SCU SFSP6_8: EHS Mask */ +#define SCU_SFSP6_8_EZI_Pos 6 /*!< SCU SFSP6_8: EZI Position */ +#define SCU_SFSP6_8_EZI_Msk (0x01UL << SCU_SFSP6_8_EZI_Pos) /*!< SCU SFSP6_8: EZI Mask */ +#define SCU_SFSP6_8_ZIF_Pos 7 /*!< SCU SFSP6_8: ZIF Position */ +#define SCU_SFSP6_8_ZIF_Msk (0x01UL << SCU_SFSP6_8_ZIF_Pos) /*!< SCU SFSP6_8: ZIF Mask */ + +/* --------------------------------- SCU_SFSP6_9 -------------------------------- */ +#define SCU_SFSP6_9_MODE_Pos 0 /*!< SCU SFSP6_9: MODE Position */ +#define SCU_SFSP6_9_MODE_Msk (0x07UL << SCU_SFSP6_9_MODE_Pos) /*!< SCU SFSP6_9: MODE Mask */ +#define SCU_SFSP6_9_EPD_Pos 3 /*!< SCU SFSP6_9: EPD Position */ +#define SCU_SFSP6_9_EPD_Msk (0x01UL << SCU_SFSP6_9_EPD_Pos) /*!< SCU SFSP6_9: EPD Mask */ +#define SCU_SFSP6_9_EPUN_Pos 4 /*!< SCU SFSP6_9: EPUN Position */ +#define SCU_SFSP6_9_EPUN_Msk (0x01UL << SCU_SFSP6_9_EPUN_Pos) /*!< SCU SFSP6_9: EPUN Mask */ +#define SCU_SFSP6_9_EHS_Pos 5 /*!< SCU SFSP6_9: EHS Position */ +#define SCU_SFSP6_9_EHS_Msk (0x01UL << SCU_SFSP6_9_EHS_Pos) /*!< SCU SFSP6_9: EHS Mask */ +#define SCU_SFSP6_9_EZI_Pos 6 /*!< SCU SFSP6_9: EZI Position */ +#define SCU_SFSP6_9_EZI_Msk (0x01UL << SCU_SFSP6_9_EZI_Pos) /*!< SCU SFSP6_9: EZI Mask */ +#define SCU_SFSP6_9_ZIF_Pos 7 /*!< SCU SFSP6_9: ZIF Position */ +#define SCU_SFSP6_9_ZIF_Msk (0x01UL << SCU_SFSP6_9_ZIF_Pos) /*!< SCU SFSP6_9: ZIF Mask */ + +/* -------------------------------- SCU_SFSP6_10 -------------------------------- */ +#define SCU_SFSP6_10_MODE_Pos 0 /*!< SCU SFSP6_10: MODE Position */ +#define SCU_SFSP6_10_MODE_Msk (0x07UL << SCU_SFSP6_10_MODE_Pos) /*!< SCU SFSP6_10: MODE Mask */ +#define SCU_SFSP6_10_EPD_Pos 3 /*!< SCU SFSP6_10: EPD Position */ +#define SCU_SFSP6_10_EPD_Msk (0x01UL << SCU_SFSP6_10_EPD_Pos) /*!< SCU SFSP6_10: EPD Mask */ +#define SCU_SFSP6_10_EPUN_Pos 4 /*!< SCU SFSP6_10: EPUN Position */ +#define SCU_SFSP6_10_EPUN_Msk (0x01UL << SCU_SFSP6_10_EPUN_Pos) /*!< SCU SFSP6_10: EPUN Mask */ +#define SCU_SFSP6_10_EHS_Pos 5 /*!< SCU SFSP6_10: EHS Position */ +#define SCU_SFSP6_10_EHS_Msk (0x01UL << SCU_SFSP6_10_EHS_Pos) /*!< SCU SFSP6_10: EHS Mask */ +#define SCU_SFSP6_10_EZI_Pos 6 /*!< SCU SFSP6_10: EZI Position */ +#define SCU_SFSP6_10_EZI_Msk (0x01UL << SCU_SFSP6_10_EZI_Pos) /*!< SCU SFSP6_10: EZI Mask */ +#define SCU_SFSP6_10_ZIF_Pos 7 /*!< SCU SFSP6_10: ZIF Position */ +#define SCU_SFSP6_10_ZIF_Msk (0x01UL << SCU_SFSP6_10_ZIF_Pos) /*!< SCU SFSP6_10: ZIF Mask */ + +/* -------------------------------- SCU_SFSP6_11 -------------------------------- */ +#define SCU_SFSP6_11_MODE_Pos 0 /*!< SCU SFSP6_11: MODE Position */ +#define SCU_SFSP6_11_MODE_Msk (0x07UL << SCU_SFSP6_11_MODE_Pos) /*!< SCU SFSP6_11: MODE Mask */ +#define SCU_SFSP6_11_EPD_Pos 3 /*!< SCU SFSP6_11: EPD Position */ +#define SCU_SFSP6_11_EPD_Msk (0x01UL << SCU_SFSP6_11_EPD_Pos) /*!< SCU SFSP6_11: EPD Mask */ +#define SCU_SFSP6_11_EPUN_Pos 4 /*!< SCU SFSP6_11: EPUN Position */ +#define SCU_SFSP6_11_EPUN_Msk (0x01UL << SCU_SFSP6_11_EPUN_Pos) /*!< SCU SFSP6_11: EPUN Mask */ +#define SCU_SFSP6_11_EHS_Pos 5 /*!< SCU SFSP6_11: EHS Position */ +#define SCU_SFSP6_11_EHS_Msk (0x01UL << SCU_SFSP6_11_EHS_Pos) /*!< SCU SFSP6_11: EHS Mask */ +#define SCU_SFSP6_11_EZI_Pos 6 /*!< SCU SFSP6_11: EZI Position */ +#define SCU_SFSP6_11_EZI_Msk (0x01UL << SCU_SFSP6_11_EZI_Pos) /*!< SCU SFSP6_11: EZI Mask */ +#define SCU_SFSP6_11_ZIF_Pos 7 /*!< SCU SFSP6_11: ZIF Position */ +#define SCU_SFSP6_11_ZIF_Msk (0x01UL << SCU_SFSP6_11_ZIF_Pos) /*!< SCU SFSP6_11: ZIF Mask */ + +/* -------------------------------- SCU_SFSP6_12 -------------------------------- */ +#define SCU_SFSP6_12_MODE_Pos 0 /*!< SCU SFSP6_12: MODE Position */ +#define SCU_SFSP6_12_MODE_Msk (0x07UL << SCU_SFSP6_12_MODE_Pos) /*!< SCU SFSP6_12: MODE Mask */ +#define SCU_SFSP6_12_EPD_Pos 3 /*!< SCU SFSP6_12: EPD Position */ +#define SCU_SFSP6_12_EPD_Msk (0x01UL << SCU_SFSP6_12_EPD_Pos) /*!< SCU SFSP6_12: EPD Mask */ +#define SCU_SFSP6_12_EPUN_Pos 4 /*!< SCU SFSP6_12: EPUN Position */ +#define SCU_SFSP6_12_EPUN_Msk (0x01UL << SCU_SFSP6_12_EPUN_Pos) /*!< SCU SFSP6_12: EPUN Mask */ +#define SCU_SFSP6_12_EHS_Pos 5 /*!< SCU SFSP6_12: EHS Position */ +#define SCU_SFSP6_12_EHS_Msk (0x01UL << SCU_SFSP6_12_EHS_Pos) /*!< SCU SFSP6_12: EHS Mask */ +#define SCU_SFSP6_12_EZI_Pos 6 /*!< SCU SFSP6_12: EZI Position */ +#define SCU_SFSP6_12_EZI_Msk (0x01UL << SCU_SFSP6_12_EZI_Pos) /*!< SCU SFSP6_12: EZI Mask */ +#define SCU_SFSP6_12_ZIF_Pos 7 /*!< SCU SFSP6_12: ZIF Position */ +#define SCU_SFSP6_12_ZIF_Msk (0x01UL << SCU_SFSP6_12_ZIF_Pos) /*!< SCU SFSP6_12: ZIF Mask */ + +/* --------------------------------- SCU_SFSP7_0 -------------------------------- */ +#define SCU_SFSP7_0_MODE_Pos 0 /*!< SCU SFSP7_0: MODE Position */ +#define SCU_SFSP7_0_MODE_Msk (0x07UL << SCU_SFSP7_0_MODE_Pos) /*!< SCU SFSP7_0: MODE Mask */ +#define SCU_SFSP7_0_EPD_Pos 3 /*!< SCU SFSP7_0: EPD Position */ +#define SCU_SFSP7_0_EPD_Msk (0x01UL << SCU_SFSP7_0_EPD_Pos) /*!< SCU SFSP7_0: EPD Mask */ +#define SCU_SFSP7_0_EPUN_Pos 4 /*!< SCU SFSP7_0: EPUN Position */ +#define SCU_SFSP7_0_EPUN_Msk (0x01UL << SCU_SFSP7_0_EPUN_Pos) /*!< SCU SFSP7_0: EPUN Mask */ +#define SCU_SFSP7_0_EHS_Pos 5 /*!< SCU SFSP7_0: EHS Position */ +#define SCU_SFSP7_0_EHS_Msk (0x01UL << SCU_SFSP7_0_EHS_Pos) /*!< SCU SFSP7_0: EHS Mask */ +#define SCU_SFSP7_0_EZI_Pos 6 /*!< SCU SFSP7_0: EZI Position */ +#define SCU_SFSP7_0_EZI_Msk (0x01UL << SCU_SFSP7_0_EZI_Pos) /*!< SCU SFSP7_0: EZI Mask */ +#define SCU_SFSP7_0_ZIF_Pos 7 /*!< SCU SFSP7_0: ZIF Position */ +#define SCU_SFSP7_0_ZIF_Msk (0x01UL << SCU_SFSP7_0_ZIF_Pos) /*!< SCU SFSP7_0: ZIF Mask */ + +/* --------------------------------- SCU_SFSP7_1 -------------------------------- */ +#define SCU_SFSP7_1_MODE_Pos 0 /*!< SCU SFSP7_1: MODE Position */ +#define SCU_SFSP7_1_MODE_Msk (0x07UL << SCU_SFSP7_1_MODE_Pos) /*!< SCU SFSP7_1: MODE Mask */ +#define SCU_SFSP7_1_EPD_Pos 3 /*!< SCU SFSP7_1: EPD Position */ +#define SCU_SFSP7_1_EPD_Msk (0x01UL << SCU_SFSP7_1_EPD_Pos) /*!< SCU SFSP7_1: EPD Mask */ +#define SCU_SFSP7_1_EPUN_Pos 4 /*!< SCU SFSP7_1: EPUN Position */ +#define SCU_SFSP7_1_EPUN_Msk (0x01UL << SCU_SFSP7_1_EPUN_Pos) /*!< SCU SFSP7_1: EPUN Mask */ +#define SCU_SFSP7_1_EHS_Pos 5 /*!< SCU SFSP7_1: EHS Position */ +#define SCU_SFSP7_1_EHS_Msk (0x01UL << SCU_SFSP7_1_EHS_Pos) /*!< SCU SFSP7_1: EHS Mask */ +#define SCU_SFSP7_1_EZI_Pos 6 /*!< SCU SFSP7_1: EZI Position */ +#define SCU_SFSP7_1_EZI_Msk (0x01UL << SCU_SFSP7_1_EZI_Pos) /*!< SCU SFSP7_1: EZI Mask */ +#define SCU_SFSP7_1_ZIF_Pos 7 /*!< SCU SFSP7_1: ZIF Position */ +#define SCU_SFSP7_1_ZIF_Msk (0x01UL << SCU_SFSP7_1_ZIF_Pos) /*!< SCU SFSP7_1: ZIF Mask */ + +/* --------------------------------- SCU_SFSP7_2 -------------------------------- */ +#define SCU_SFSP7_2_MODE_Pos 0 /*!< SCU SFSP7_2: MODE Position */ +#define SCU_SFSP7_2_MODE_Msk (0x07UL << SCU_SFSP7_2_MODE_Pos) /*!< SCU SFSP7_2: MODE Mask */ +#define SCU_SFSP7_2_EPD_Pos 3 /*!< SCU SFSP7_2: EPD Position */ +#define SCU_SFSP7_2_EPD_Msk (0x01UL << SCU_SFSP7_2_EPD_Pos) /*!< SCU SFSP7_2: EPD Mask */ +#define SCU_SFSP7_2_EPUN_Pos 4 /*!< SCU SFSP7_2: EPUN Position */ +#define SCU_SFSP7_2_EPUN_Msk (0x01UL << SCU_SFSP7_2_EPUN_Pos) /*!< SCU SFSP7_2: EPUN Mask */ +#define SCU_SFSP7_2_EHS_Pos 5 /*!< SCU SFSP7_2: EHS Position */ +#define SCU_SFSP7_2_EHS_Msk (0x01UL << SCU_SFSP7_2_EHS_Pos) /*!< SCU SFSP7_2: EHS Mask */ +#define SCU_SFSP7_2_EZI_Pos 6 /*!< SCU SFSP7_2: EZI Position */ +#define SCU_SFSP7_2_EZI_Msk (0x01UL << SCU_SFSP7_2_EZI_Pos) /*!< SCU SFSP7_2: EZI Mask */ +#define SCU_SFSP7_2_ZIF_Pos 7 /*!< SCU SFSP7_2: ZIF Position */ +#define SCU_SFSP7_2_ZIF_Msk (0x01UL << SCU_SFSP7_2_ZIF_Pos) /*!< SCU SFSP7_2: ZIF Mask */ + +/* --------------------------------- SCU_SFSP7_3 -------------------------------- */ +#define SCU_SFSP7_3_MODE_Pos 0 /*!< SCU SFSP7_3: MODE Position */ +#define SCU_SFSP7_3_MODE_Msk (0x07UL << SCU_SFSP7_3_MODE_Pos) /*!< SCU SFSP7_3: MODE Mask */ +#define SCU_SFSP7_3_EPD_Pos 3 /*!< SCU SFSP7_3: EPD Position */ +#define SCU_SFSP7_3_EPD_Msk (0x01UL << SCU_SFSP7_3_EPD_Pos) /*!< SCU SFSP7_3: EPD Mask */ +#define SCU_SFSP7_3_EPUN_Pos 4 /*!< SCU SFSP7_3: EPUN Position */ +#define SCU_SFSP7_3_EPUN_Msk (0x01UL << SCU_SFSP7_3_EPUN_Pos) /*!< SCU SFSP7_3: EPUN Mask */ +#define SCU_SFSP7_3_EHS_Pos 5 /*!< SCU SFSP7_3: EHS Position */ +#define SCU_SFSP7_3_EHS_Msk (0x01UL << SCU_SFSP7_3_EHS_Pos) /*!< SCU SFSP7_3: EHS Mask */ +#define SCU_SFSP7_3_EZI_Pos 6 /*!< SCU SFSP7_3: EZI Position */ +#define SCU_SFSP7_3_EZI_Msk (0x01UL << SCU_SFSP7_3_EZI_Pos) /*!< SCU SFSP7_3: EZI Mask */ +#define SCU_SFSP7_3_ZIF_Pos 7 /*!< SCU SFSP7_3: ZIF Position */ +#define SCU_SFSP7_3_ZIF_Msk (0x01UL << SCU_SFSP7_3_ZIF_Pos) /*!< SCU SFSP7_3: ZIF Mask */ + +/* --------------------------------- SCU_SFSP7_4 -------------------------------- */ +#define SCU_SFSP7_4_MODE_Pos 0 /*!< SCU SFSP7_4: MODE Position */ +#define SCU_SFSP7_4_MODE_Msk (0x07UL << SCU_SFSP7_4_MODE_Pos) /*!< SCU SFSP7_4: MODE Mask */ +#define SCU_SFSP7_4_EPD_Pos 3 /*!< SCU SFSP7_4: EPD Position */ +#define SCU_SFSP7_4_EPD_Msk (0x01UL << SCU_SFSP7_4_EPD_Pos) /*!< SCU SFSP7_4: EPD Mask */ +#define SCU_SFSP7_4_EPUN_Pos 4 /*!< SCU SFSP7_4: EPUN Position */ +#define SCU_SFSP7_4_EPUN_Msk (0x01UL << SCU_SFSP7_4_EPUN_Pos) /*!< SCU SFSP7_4: EPUN Mask */ +#define SCU_SFSP7_4_EHS_Pos 5 /*!< SCU SFSP7_4: EHS Position */ +#define SCU_SFSP7_4_EHS_Msk (0x01UL << SCU_SFSP7_4_EHS_Pos) /*!< SCU SFSP7_4: EHS Mask */ +#define SCU_SFSP7_4_EZI_Pos 6 /*!< SCU SFSP7_4: EZI Position */ +#define SCU_SFSP7_4_EZI_Msk (0x01UL << SCU_SFSP7_4_EZI_Pos) /*!< SCU SFSP7_4: EZI Mask */ +#define SCU_SFSP7_4_ZIF_Pos 7 /*!< SCU SFSP7_4: ZIF Position */ +#define SCU_SFSP7_4_ZIF_Msk (0x01UL << SCU_SFSP7_4_ZIF_Pos) /*!< SCU SFSP7_4: ZIF Mask */ + +/* --------------------------------- SCU_SFSP7_5 -------------------------------- */ +#define SCU_SFSP7_5_MODE_Pos 0 /*!< SCU SFSP7_5: MODE Position */ +#define SCU_SFSP7_5_MODE_Msk (0x07UL << SCU_SFSP7_5_MODE_Pos) /*!< SCU SFSP7_5: MODE Mask */ +#define SCU_SFSP7_5_EPD_Pos 3 /*!< SCU SFSP7_5: EPD Position */ +#define SCU_SFSP7_5_EPD_Msk (0x01UL << SCU_SFSP7_5_EPD_Pos) /*!< SCU SFSP7_5: EPD Mask */ +#define SCU_SFSP7_5_EPUN_Pos 4 /*!< SCU SFSP7_5: EPUN Position */ +#define SCU_SFSP7_5_EPUN_Msk (0x01UL << SCU_SFSP7_5_EPUN_Pos) /*!< SCU SFSP7_5: EPUN Mask */ +#define SCU_SFSP7_5_EHS_Pos 5 /*!< SCU SFSP7_5: EHS Position */ +#define SCU_SFSP7_5_EHS_Msk (0x01UL << SCU_SFSP7_5_EHS_Pos) /*!< SCU SFSP7_5: EHS Mask */ +#define SCU_SFSP7_5_EZI_Pos 6 /*!< SCU SFSP7_5: EZI Position */ +#define SCU_SFSP7_5_EZI_Msk (0x01UL << SCU_SFSP7_5_EZI_Pos) /*!< SCU SFSP7_5: EZI Mask */ +#define SCU_SFSP7_5_ZIF_Pos 7 /*!< SCU SFSP7_5: ZIF Position */ +#define SCU_SFSP7_5_ZIF_Msk (0x01UL << SCU_SFSP7_5_ZIF_Pos) /*!< SCU SFSP7_5: ZIF Mask */ + +/* --------------------------------- SCU_SFSP7_6 -------------------------------- */ +#define SCU_SFSP7_6_MODE_Pos 0 /*!< SCU SFSP7_6: MODE Position */ +#define SCU_SFSP7_6_MODE_Msk (0x07UL << SCU_SFSP7_6_MODE_Pos) /*!< SCU SFSP7_6: MODE Mask */ +#define SCU_SFSP7_6_EPD_Pos 3 /*!< SCU SFSP7_6: EPD Position */ +#define SCU_SFSP7_6_EPD_Msk (0x01UL << SCU_SFSP7_6_EPD_Pos) /*!< SCU SFSP7_6: EPD Mask */ +#define SCU_SFSP7_6_EPUN_Pos 4 /*!< SCU SFSP7_6: EPUN Position */ +#define SCU_SFSP7_6_EPUN_Msk (0x01UL << SCU_SFSP7_6_EPUN_Pos) /*!< SCU SFSP7_6: EPUN Mask */ +#define SCU_SFSP7_6_EHS_Pos 5 /*!< SCU SFSP7_6: EHS Position */ +#define SCU_SFSP7_6_EHS_Msk (0x01UL << SCU_SFSP7_6_EHS_Pos) /*!< SCU SFSP7_6: EHS Mask */ +#define SCU_SFSP7_6_EZI_Pos 6 /*!< SCU SFSP7_6: EZI Position */ +#define SCU_SFSP7_6_EZI_Msk (0x01UL << SCU_SFSP7_6_EZI_Pos) /*!< SCU SFSP7_6: EZI Mask */ +#define SCU_SFSP7_6_ZIF_Pos 7 /*!< SCU SFSP7_6: ZIF Position */ +#define SCU_SFSP7_6_ZIF_Msk (0x01UL << SCU_SFSP7_6_ZIF_Pos) /*!< SCU SFSP7_6: ZIF Mask */ + +/* --------------------------------- SCU_SFSP7_7 -------------------------------- */ +#define SCU_SFSP7_7_MODE_Pos 0 /*!< SCU SFSP7_7: MODE Position */ +#define SCU_SFSP7_7_MODE_Msk (0x07UL << SCU_SFSP7_7_MODE_Pos) /*!< SCU SFSP7_7: MODE Mask */ +#define SCU_SFSP7_7_EPD_Pos 3 /*!< SCU SFSP7_7: EPD Position */ +#define SCU_SFSP7_7_EPD_Msk (0x01UL << SCU_SFSP7_7_EPD_Pos) /*!< SCU SFSP7_7: EPD Mask */ +#define SCU_SFSP7_7_EPUN_Pos 4 /*!< SCU SFSP7_7: EPUN Position */ +#define SCU_SFSP7_7_EPUN_Msk (0x01UL << SCU_SFSP7_7_EPUN_Pos) /*!< SCU SFSP7_7: EPUN Mask */ +#define SCU_SFSP7_7_EHS_Pos 5 /*!< SCU SFSP7_7: EHS Position */ +#define SCU_SFSP7_7_EHS_Msk (0x01UL << SCU_SFSP7_7_EHS_Pos) /*!< SCU SFSP7_7: EHS Mask */ +#define SCU_SFSP7_7_EZI_Pos 6 /*!< SCU SFSP7_7: EZI Position */ +#define SCU_SFSP7_7_EZI_Msk (0x01UL << SCU_SFSP7_7_EZI_Pos) /*!< SCU SFSP7_7: EZI Mask */ +#define SCU_SFSP7_7_ZIF_Pos 7 /*!< SCU SFSP7_7: ZIF Position */ +#define SCU_SFSP7_7_ZIF_Msk (0x01UL << SCU_SFSP7_7_ZIF_Pos) /*!< SCU SFSP7_7: ZIF Mask */ + +/* --------------------------------- SCU_SFSP8_0 -------------------------------- */ +#define SCU_SFSP8_0_MODE_Pos 0 /*!< SCU SFSP8_0: MODE Position */ +#define SCU_SFSP8_0_MODE_Msk (0x07UL << SCU_SFSP8_0_MODE_Pos) /*!< SCU SFSP8_0: MODE Mask */ +#define SCU_SFSP8_0_EPD_Pos 3 /*!< SCU SFSP8_0: EPD Position */ +#define SCU_SFSP8_0_EPD_Msk (0x01UL << SCU_SFSP8_0_EPD_Pos) /*!< SCU SFSP8_0: EPD Mask */ +#define SCU_SFSP8_0_EPUN_Pos 4 /*!< SCU SFSP8_0: EPUN Position */ +#define SCU_SFSP8_0_EPUN_Msk (0x01UL << SCU_SFSP8_0_EPUN_Pos) /*!< SCU SFSP8_0: EPUN Mask */ +#define SCU_SFSP8_0_EHS_Pos 5 /*!< SCU SFSP8_0: EHS Position */ +#define SCU_SFSP8_0_EHS_Msk (0x01UL << SCU_SFSP8_0_EHS_Pos) /*!< SCU SFSP8_0: EHS Mask */ +#define SCU_SFSP8_0_EZI_Pos 6 /*!< SCU SFSP8_0: EZI Position */ +#define SCU_SFSP8_0_EZI_Msk (0x01UL << SCU_SFSP8_0_EZI_Pos) /*!< SCU SFSP8_0: EZI Mask */ +#define SCU_SFSP8_0_ZIF_Pos 7 /*!< SCU SFSP8_0: ZIF Position */ +#define SCU_SFSP8_0_ZIF_Msk (0x01UL << SCU_SFSP8_0_ZIF_Pos) /*!< SCU SFSP8_0: ZIF Mask */ + +/* --------------------------------- SCU_SFSP8_1 -------------------------------- */ +#define SCU_SFSP8_1_MODE_Pos 0 /*!< SCU SFSP8_1: MODE Position */ +#define SCU_SFSP8_1_MODE_Msk (0x07UL << SCU_SFSP8_1_MODE_Pos) /*!< SCU SFSP8_1: MODE Mask */ +#define SCU_SFSP8_1_EPD_Pos 3 /*!< SCU SFSP8_1: EPD Position */ +#define SCU_SFSP8_1_EPD_Msk (0x01UL << SCU_SFSP8_1_EPD_Pos) /*!< SCU SFSP8_1: EPD Mask */ +#define SCU_SFSP8_1_EPUN_Pos 4 /*!< SCU SFSP8_1: EPUN Position */ +#define SCU_SFSP8_1_EPUN_Msk (0x01UL << SCU_SFSP8_1_EPUN_Pos) /*!< SCU SFSP8_1: EPUN Mask */ +#define SCU_SFSP8_1_EHS_Pos 5 /*!< SCU SFSP8_1: EHS Position */ +#define SCU_SFSP8_1_EHS_Msk (0x01UL << SCU_SFSP8_1_EHS_Pos) /*!< SCU SFSP8_1: EHS Mask */ +#define SCU_SFSP8_1_EZI_Pos 6 /*!< SCU SFSP8_1: EZI Position */ +#define SCU_SFSP8_1_EZI_Msk (0x01UL << SCU_SFSP8_1_EZI_Pos) /*!< SCU SFSP8_1: EZI Mask */ +#define SCU_SFSP8_1_ZIF_Pos 7 /*!< SCU SFSP8_1: ZIF Position */ +#define SCU_SFSP8_1_ZIF_Msk (0x01UL << SCU_SFSP8_1_ZIF_Pos) /*!< SCU SFSP8_1: ZIF Mask */ + +/* --------------------------------- SCU_SFSP8_2 -------------------------------- */ +#define SCU_SFSP8_2_MODE_Pos 0 /*!< SCU SFSP8_2: MODE Position */ +#define SCU_SFSP8_2_MODE_Msk (0x07UL << SCU_SFSP8_2_MODE_Pos) /*!< SCU SFSP8_2: MODE Mask */ +#define SCU_SFSP8_2_EPD_Pos 3 /*!< SCU SFSP8_2: EPD Position */ +#define SCU_SFSP8_2_EPD_Msk (0x01UL << SCU_SFSP8_2_EPD_Pos) /*!< SCU SFSP8_2: EPD Mask */ +#define SCU_SFSP8_2_EPUN_Pos 4 /*!< SCU SFSP8_2: EPUN Position */ +#define SCU_SFSP8_2_EPUN_Msk (0x01UL << SCU_SFSP8_2_EPUN_Pos) /*!< SCU SFSP8_2: EPUN Mask */ +#define SCU_SFSP8_2_EHS_Pos 5 /*!< SCU SFSP8_2: EHS Position */ +#define SCU_SFSP8_2_EHS_Msk (0x01UL << SCU_SFSP8_2_EHS_Pos) /*!< SCU SFSP8_2: EHS Mask */ +#define SCU_SFSP8_2_EZI_Pos 6 /*!< SCU SFSP8_2: EZI Position */ +#define SCU_SFSP8_2_EZI_Msk (0x01UL << SCU_SFSP8_2_EZI_Pos) /*!< SCU SFSP8_2: EZI Mask */ +#define SCU_SFSP8_2_ZIF_Pos 7 /*!< SCU SFSP8_2: ZIF Position */ +#define SCU_SFSP8_2_ZIF_Msk (0x01UL << SCU_SFSP8_2_ZIF_Pos) /*!< SCU SFSP8_2: ZIF Mask */ + +/* --------------------------------- SCU_SFSP8_3 -------------------------------- */ +#define SCU_SFSP8_3_MODE_Pos 0 /*!< SCU SFSP8_3: MODE Position */ +#define SCU_SFSP8_3_MODE_Msk (0x07UL << SCU_SFSP8_3_MODE_Pos) /*!< SCU SFSP8_3: MODE Mask */ +#define SCU_SFSP8_3_EPD_Pos 3 /*!< SCU SFSP8_3: EPD Position */ +#define SCU_SFSP8_3_EPD_Msk (0x01UL << SCU_SFSP8_3_EPD_Pos) /*!< SCU SFSP8_3: EPD Mask */ +#define SCU_SFSP8_3_EPUN_Pos 4 /*!< SCU SFSP8_3: EPUN Position */ +#define SCU_SFSP8_3_EPUN_Msk (0x01UL << SCU_SFSP8_3_EPUN_Pos) /*!< SCU SFSP8_3: EPUN Mask */ +#define SCU_SFSP8_3_EHS_Pos 5 /*!< SCU SFSP8_3: EHS Position */ +#define SCU_SFSP8_3_EHS_Msk (0x01UL << SCU_SFSP8_3_EHS_Pos) /*!< SCU SFSP8_3: EHS Mask */ +#define SCU_SFSP8_3_EZI_Pos 6 /*!< SCU SFSP8_3: EZI Position */ +#define SCU_SFSP8_3_EZI_Msk (0x01UL << SCU_SFSP8_3_EZI_Pos) /*!< SCU SFSP8_3: EZI Mask */ +#define SCU_SFSP8_3_ZIF_Pos 7 /*!< SCU SFSP8_3: ZIF Position */ +#define SCU_SFSP8_3_ZIF_Msk (0x01UL << SCU_SFSP8_3_ZIF_Pos) /*!< SCU SFSP8_3: ZIF Mask */ + +/* --------------------------------- SCU_SFSP8_4 -------------------------------- */ +#define SCU_SFSP8_4_MODE_Pos 0 /*!< SCU SFSP8_4: MODE Position */ +#define SCU_SFSP8_4_MODE_Msk (0x07UL << SCU_SFSP8_4_MODE_Pos) /*!< SCU SFSP8_4: MODE Mask */ +#define SCU_SFSP8_4_EPD_Pos 3 /*!< SCU SFSP8_4: EPD Position */ +#define SCU_SFSP8_4_EPD_Msk (0x01UL << SCU_SFSP8_4_EPD_Pos) /*!< SCU SFSP8_4: EPD Mask */ +#define SCU_SFSP8_4_EPUN_Pos 4 /*!< SCU SFSP8_4: EPUN Position */ +#define SCU_SFSP8_4_EPUN_Msk (0x01UL << SCU_SFSP8_4_EPUN_Pos) /*!< SCU SFSP8_4: EPUN Mask */ +#define SCU_SFSP8_4_EHS_Pos 5 /*!< SCU SFSP8_4: EHS Position */ +#define SCU_SFSP8_4_EHS_Msk (0x01UL << SCU_SFSP8_4_EHS_Pos) /*!< SCU SFSP8_4: EHS Mask */ +#define SCU_SFSP8_4_EZI_Pos 6 /*!< SCU SFSP8_4: EZI Position */ +#define SCU_SFSP8_4_EZI_Msk (0x01UL << SCU_SFSP8_4_EZI_Pos) /*!< SCU SFSP8_4: EZI Mask */ +#define SCU_SFSP8_4_ZIF_Pos 7 /*!< SCU SFSP8_4: ZIF Position */ +#define SCU_SFSP8_4_ZIF_Msk (0x01UL << SCU_SFSP8_4_ZIF_Pos) /*!< SCU SFSP8_4: ZIF Mask */ + +/* --------------------------------- SCU_SFSP8_5 -------------------------------- */ +#define SCU_SFSP8_5_MODE_Pos 0 /*!< SCU SFSP8_5: MODE Position */ +#define SCU_SFSP8_5_MODE_Msk (0x07UL << SCU_SFSP8_5_MODE_Pos) /*!< SCU SFSP8_5: MODE Mask */ +#define SCU_SFSP8_5_EPD_Pos 3 /*!< SCU SFSP8_5: EPD Position */ +#define SCU_SFSP8_5_EPD_Msk (0x01UL << SCU_SFSP8_5_EPD_Pos) /*!< SCU SFSP8_5: EPD Mask */ +#define SCU_SFSP8_5_EPUN_Pos 4 /*!< SCU SFSP8_5: EPUN Position */ +#define SCU_SFSP8_5_EPUN_Msk (0x01UL << SCU_SFSP8_5_EPUN_Pos) /*!< SCU SFSP8_5: EPUN Mask */ +#define SCU_SFSP8_5_EHS_Pos 5 /*!< SCU SFSP8_5: EHS Position */ +#define SCU_SFSP8_5_EHS_Msk (0x01UL << SCU_SFSP8_5_EHS_Pos) /*!< SCU SFSP8_5: EHS Mask */ +#define SCU_SFSP8_5_EZI_Pos 6 /*!< SCU SFSP8_5: EZI Position */ +#define SCU_SFSP8_5_EZI_Msk (0x01UL << SCU_SFSP8_5_EZI_Pos) /*!< SCU SFSP8_5: EZI Mask */ +#define SCU_SFSP8_5_ZIF_Pos 7 /*!< SCU SFSP8_5: ZIF Position */ +#define SCU_SFSP8_5_ZIF_Msk (0x01UL << SCU_SFSP8_5_ZIF_Pos) /*!< SCU SFSP8_5: ZIF Mask */ + +/* --------------------------------- SCU_SFSP8_6 -------------------------------- */ +#define SCU_SFSP8_6_MODE_Pos 0 /*!< SCU SFSP8_6: MODE Position */ +#define SCU_SFSP8_6_MODE_Msk (0x07UL << SCU_SFSP8_6_MODE_Pos) /*!< SCU SFSP8_6: MODE Mask */ +#define SCU_SFSP8_6_EPD_Pos 3 /*!< SCU SFSP8_6: EPD Position */ +#define SCU_SFSP8_6_EPD_Msk (0x01UL << SCU_SFSP8_6_EPD_Pos) /*!< SCU SFSP8_6: EPD Mask */ +#define SCU_SFSP8_6_EPUN_Pos 4 /*!< SCU SFSP8_6: EPUN Position */ +#define SCU_SFSP8_6_EPUN_Msk (0x01UL << SCU_SFSP8_6_EPUN_Pos) /*!< SCU SFSP8_6: EPUN Mask */ +#define SCU_SFSP8_6_EHS_Pos 5 /*!< SCU SFSP8_6: EHS Position */ +#define SCU_SFSP8_6_EHS_Msk (0x01UL << SCU_SFSP8_6_EHS_Pos) /*!< SCU SFSP8_6: EHS Mask */ +#define SCU_SFSP8_6_EZI_Pos 6 /*!< SCU SFSP8_6: EZI Position */ +#define SCU_SFSP8_6_EZI_Msk (0x01UL << SCU_SFSP8_6_EZI_Pos) /*!< SCU SFSP8_6: EZI Mask */ +#define SCU_SFSP8_6_ZIF_Pos 7 /*!< SCU SFSP8_6: ZIF Position */ +#define SCU_SFSP8_6_ZIF_Msk (0x01UL << SCU_SFSP8_6_ZIF_Pos) /*!< SCU SFSP8_6: ZIF Mask */ + +/* --------------------------------- SCU_SFSP8_7 -------------------------------- */ +#define SCU_SFSP8_7_MODE_Pos 0 /*!< SCU SFSP8_7: MODE Position */ +#define SCU_SFSP8_7_MODE_Msk (0x07UL << SCU_SFSP8_7_MODE_Pos) /*!< SCU SFSP8_7: MODE Mask */ +#define SCU_SFSP8_7_EPD_Pos 3 /*!< SCU SFSP8_7: EPD Position */ +#define SCU_SFSP8_7_EPD_Msk (0x01UL << SCU_SFSP8_7_EPD_Pos) /*!< SCU SFSP8_7: EPD Mask */ +#define SCU_SFSP8_7_EPUN_Pos 4 /*!< SCU SFSP8_7: EPUN Position */ +#define SCU_SFSP8_7_EPUN_Msk (0x01UL << SCU_SFSP8_7_EPUN_Pos) /*!< SCU SFSP8_7: EPUN Mask */ +#define SCU_SFSP8_7_EHS_Pos 5 /*!< SCU SFSP8_7: EHS Position */ +#define SCU_SFSP8_7_EHS_Msk (0x01UL << SCU_SFSP8_7_EHS_Pos) /*!< SCU SFSP8_7: EHS Mask */ +#define SCU_SFSP8_7_EZI_Pos 6 /*!< SCU SFSP8_7: EZI Position */ +#define SCU_SFSP8_7_EZI_Msk (0x01UL << SCU_SFSP8_7_EZI_Pos) /*!< SCU SFSP8_7: EZI Mask */ +#define SCU_SFSP8_7_ZIF_Pos 7 /*!< SCU SFSP8_7: ZIF Position */ +#define SCU_SFSP8_7_ZIF_Msk (0x01UL << SCU_SFSP8_7_ZIF_Pos) /*!< SCU SFSP8_7: ZIF Mask */ + +/* --------------------------------- SCU_SFSP8_8 -------------------------------- */ +#define SCU_SFSP8_8_MODE_Pos 0 /*!< SCU SFSP8_8: MODE Position */ +#define SCU_SFSP8_8_MODE_Msk (0x07UL << SCU_SFSP8_8_MODE_Pos) /*!< SCU SFSP8_8: MODE Mask */ +#define SCU_SFSP8_8_EPD_Pos 3 /*!< SCU SFSP8_8: EPD Position */ +#define SCU_SFSP8_8_EPD_Msk (0x01UL << SCU_SFSP8_8_EPD_Pos) /*!< SCU SFSP8_8: EPD Mask */ +#define SCU_SFSP8_8_EPUN_Pos 4 /*!< SCU SFSP8_8: EPUN Position */ +#define SCU_SFSP8_8_EPUN_Msk (0x01UL << SCU_SFSP8_8_EPUN_Pos) /*!< SCU SFSP8_8: EPUN Mask */ +#define SCU_SFSP8_8_EHS_Pos 5 /*!< SCU SFSP8_8: EHS Position */ +#define SCU_SFSP8_8_EHS_Msk (0x01UL << SCU_SFSP8_8_EHS_Pos) /*!< SCU SFSP8_8: EHS Mask */ +#define SCU_SFSP8_8_EZI_Pos 6 /*!< SCU SFSP8_8: EZI Position */ +#define SCU_SFSP8_8_EZI_Msk (0x01UL << SCU_SFSP8_8_EZI_Pos) /*!< SCU SFSP8_8: EZI Mask */ +#define SCU_SFSP8_8_ZIF_Pos 7 /*!< SCU SFSP8_8: ZIF Position */ +#define SCU_SFSP8_8_ZIF_Msk (0x01UL << SCU_SFSP8_8_ZIF_Pos) /*!< SCU SFSP8_8: ZIF Mask */ + +/* --------------------------------- SCU_SFSP9_0 -------------------------------- */ +#define SCU_SFSP9_0_MODE_Pos 0 /*!< SCU SFSP9_0: MODE Position */ +#define SCU_SFSP9_0_MODE_Msk (0x07UL << SCU_SFSP9_0_MODE_Pos) /*!< SCU SFSP9_0: MODE Mask */ +#define SCU_SFSP9_0_EPD_Pos 3 /*!< SCU SFSP9_0: EPD Position */ +#define SCU_SFSP9_0_EPD_Msk (0x01UL << SCU_SFSP9_0_EPD_Pos) /*!< SCU SFSP9_0: EPD Mask */ +#define SCU_SFSP9_0_EPUN_Pos 4 /*!< SCU SFSP9_0: EPUN Position */ +#define SCU_SFSP9_0_EPUN_Msk (0x01UL << SCU_SFSP9_0_EPUN_Pos) /*!< SCU SFSP9_0: EPUN Mask */ +#define SCU_SFSP9_0_EHS_Pos 5 /*!< SCU SFSP9_0: EHS Position */ +#define SCU_SFSP9_0_EHS_Msk (0x01UL << SCU_SFSP9_0_EHS_Pos) /*!< SCU SFSP9_0: EHS Mask */ +#define SCU_SFSP9_0_EZI_Pos 6 /*!< SCU SFSP9_0: EZI Position */ +#define SCU_SFSP9_0_EZI_Msk (0x01UL << SCU_SFSP9_0_EZI_Pos) /*!< SCU SFSP9_0: EZI Mask */ +#define SCU_SFSP9_0_EHD_Pos 8 /*!< SCU SFSP9_0: EHD Position */ +#define SCU_SFSP9_0_EHD_Msk (0x03UL << SCU_SFSP9_0_EHD_Pos) /*!< SCU SFSP9_0: EHD Mask */ + +/* --------------------------------- SCU_SFSP9_1 -------------------------------- */ +#define SCU_SFSP9_1_MODE_Pos 0 /*!< SCU SFSP9_1: MODE Position */ +#define SCU_SFSP9_1_MODE_Msk (0x07UL << SCU_SFSP9_1_MODE_Pos) /*!< SCU SFSP9_1: MODE Mask */ +#define SCU_SFSP9_1_EPD_Pos 3 /*!< SCU SFSP9_1: EPD Position */ +#define SCU_SFSP9_1_EPD_Msk (0x01UL << SCU_SFSP9_1_EPD_Pos) /*!< SCU SFSP9_1: EPD Mask */ +#define SCU_SFSP9_1_EPUN_Pos 4 /*!< SCU SFSP9_1: EPUN Position */ +#define SCU_SFSP9_1_EPUN_Msk (0x01UL << SCU_SFSP9_1_EPUN_Pos) /*!< SCU SFSP9_1: EPUN Mask */ +#define SCU_SFSP9_1_EHS_Pos 5 /*!< SCU SFSP9_1: EHS Position */ +#define SCU_SFSP9_1_EHS_Msk (0x01UL << SCU_SFSP9_1_EHS_Pos) /*!< SCU SFSP9_1: EHS Mask */ +#define SCU_SFSP9_1_EZI_Pos 6 /*!< SCU SFSP9_1: EZI Position */ +#define SCU_SFSP9_1_EZI_Msk (0x01UL << SCU_SFSP9_1_EZI_Pos) /*!< SCU SFSP9_1: EZI Mask */ +#define SCU_SFSP9_1_EHD_Pos 8 /*!< SCU SFSP9_1: EHD Position */ +#define SCU_SFSP9_1_EHD_Msk (0x03UL << SCU_SFSP9_1_EHD_Pos) /*!< SCU SFSP9_1: EHD Mask */ + +/* --------------------------------- SCU_SFSP9_2 -------------------------------- */ +#define SCU_SFSP9_2_MODE_Pos 0 /*!< SCU SFSP9_2: MODE Position */ +#define SCU_SFSP9_2_MODE_Msk (0x07UL << SCU_SFSP9_2_MODE_Pos) /*!< SCU SFSP9_2: MODE Mask */ +#define SCU_SFSP9_2_EPD_Pos 3 /*!< SCU SFSP9_2: EPD Position */ +#define SCU_SFSP9_2_EPD_Msk (0x01UL << SCU_SFSP9_2_EPD_Pos) /*!< SCU SFSP9_2: EPD Mask */ +#define SCU_SFSP9_2_EPUN_Pos 4 /*!< SCU SFSP9_2: EPUN Position */ +#define SCU_SFSP9_2_EPUN_Msk (0x01UL << SCU_SFSP9_2_EPUN_Pos) /*!< SCU SFSP9_2: EPUN Mask */ +#define SCU_SFSP9_2_EHS_Pos 5 /*!< SCU SFSP9_2: EHS Position */ +#define SCU_SFSP9_2_EHS_Msk (0x01UL << SCU_SFSP9_2_EHS_Pos) /*!< SCU SFSP9_2: EHS Mask */ +#define SCU_SFSP9_2_EZI_Pos 6 /*!< SCU SFSP9_2: EZI Position */ +#define SCU_SFSP9_2_EZI_Msk (0x01UL << SCU_SFSP9_2_EZI_Pos) /*!< SCU SFSP9_2: EZI Mask */ +#define SCU_SFSP9_2_EHD_Pos 8 /*!< SCU SFSP9_2: EHD Position */ +#define SCU_SFSP9_2_EHD_Msk (0x03UL << SCU_SFSP9_2_EHD_Pos) /*!< SCU SFSP9_2: EHD Mask */ + +/* --------------------------------- SCU_SFSP9_3 -------------------------------- */ +#define SCU_SFSP9_3_MODE_Pos 0 /*!< SCU SFSP9_3: MODE Position */ +#define SCU_SFSP9_3_MODE_Msk (0x07UL << SCU_SFSP9_3_MODE_Pos) /*!< SCU SFSP9_3: MODE Mask */ +#define SCU_SFSP9_3_EPD_Pos 3 /*!< SCU SFSP9_3: EPD Position */ +#define SCU_SFSP9_3_EPD_Msk (0x01UL << SCU_SFSP9_3_EPD_Pos) /*!< SCU SFSP9_3: EPD Mask */ +#define SCU_SFSP9_3_EPUN_Pos 4 /*!< SCU SFSP9_3: EPUN Position */ +#define SCU_SFSP9_3_EPUN_Msk (0x01UL << SCU_SFSP9_3_EPUN_Pos) /*!< SCU SFSP9_3: EPUN Mask */ +#define SCU_SFSP9_3_EHS_Pos 5 /*!< SCU SFSP9_3: EHS Position */ +#define SCU_SFSP9_3_EHS_Msk (0x01UL << SCU_SFSP9_3_EHS_Pos) /*!< SCU SFSP9_3: EHS Mask */ +#define SCU_SFSP9_3_EZI_Pos 6 /*!< SCU SFSP9_3: EZI Position */ +#define SCU_SFSP9_3_EZI_Msk (0x01UL << SCU_SFSP9_3_EZI_Pos) /*!< SCU SFSP9_3: EZI Mask */ +#define SCU_SFSP9_3_EHD_Pos 8 /*!< SCU SFSP9_3: EHD Position */ +#define SCU_SFSP9_3_EHD_Msk (0x03UL << SCU_SFSP9_3_EHD_Pos) /*!< SCU SFSP9_3: EHD Mask */ + +/* --------------------------------- SCU_SFSP9_4 -------------------------------- */ +#define SCU_SFSP9_4_MODE_Pos 0 /*!< SCU SFSP9_4: MODE Position */ +#define SCU_SFSP9_4_MODE_Msk (0x07UL << SCU_SFSP9_4_MODE_Pos) /*!< SCU SFSP9_4: MODE Mask */ +#define SCU_SFSP9_4_EPD_Pos 3 /*!< SCU SFSP9_4: EPD Position */ +#define SCU_SFSP9_4_EPD_Msk (0x01UL << SCU_SFSP9_4_EPD_Pos) /*!< SCU SFSP9_4: EPD Mask */ +#define SCU_SFSP9_4_EPUN_Pos 4 /*!< SCU SFSP9_4: EPUN Position */ +#define SCU_SFSP9_4_EPUN_Msk (0x01UL << SCU_SFSP9_4_EPUN_Pos) /*!< SCU SFSP9_4: EPUN Mask */ +#define SCU_SFSP9_4_EHS_Pos 5 /*!< SCU SFSP9_4: EHS Position */ +#define SCU_SFSP9_4_EHS_Msk (0x01UL << SCU_SFSP9_4_EHS_Pos) /*!< SCU SFSP9_4: EHS Mask */ +#define SCU_SFSP9_4_EZI_Pos 6 /*!< SCU SFSP9_4: EZI Position */ +#define SCU_SFSP9_4_EZI_Msk (0x01UL << SCU_SFSP9_4_EZI_Pos) /*!< SCU SFSP9_4: EZI Mask */ +#define SCU_SFSP9_4_EHD_Pos 8 /*!< SCU SFSP9_4: EHD Position */ +#define SCU_SFSP9_4_EHD_Msk (0x03UL << SCU_SFSP9_4_EHD_Pos) /*!< SCU SFSP9_4: EHD Mask */ + +/* --------------------------------- SCU_SFSP9_5 -------------------------------- */ +#define SCU_SFSP9_5_MODE_Pos 0 /*!< SCU SFSP9_5: MODE Position */ +#define SCU_SFSP9_5_MODE_Msk (0x07UL << SCU_SFSP9_5_MODE_Pos) /*!< SCU SFSP9_5: MODE Mask */ +#define SCU_SFSP9_5_EPD_Pos 3 /*!< SCU SFSP9_5: EPD Position */ +#define SCU_SFSP9_5_EPD_Msk (0x01UL << SCU_SFSP9_5_EPD_Pos) /*!< SCU SFSP9_5: EPD Mask */ +#define SCU_SFSP9_5_EPUN_Pos 4 /*!< SCU SFSP9_5: EPUN Position */ +#define SCU_SFSP9_5_EPUN_Msk (0x01UL << SCU_SFSP9_5_EPUN_Pos) /*!< SCU SFSP9_5: EPUN Mask */ +#define SCU_SFSP9_5_EHS_Pos 5 /*!< SCU SFSP9_5: EHS Position */ +#define SCU_SFSP9_5_EHS_Msk (0x01UL << SCU_SFSP9_5_EHS_Pos) /*!< SCU SFSP9_5: EHS Mask */ +#define SCU_SFSP9_5_EZI_Pos 6 /*!< SCU SFSP9_5: EZI Position */ +#define SCU_SFSP9_5_EZI_Msk (0x01UL << SCU_SFSP9_5_EZI_Pos) /*!< SCU SFSP9_5: EZI Mask */ +#define SCU_SFSP9_5_EHD_Pos 8 /*!< SCU SFSP9_5: EHD Position */ +#define SCU_SFSP9_5_EHD_Msk (0x03UL << SCU_SFSP9_5_EHD_Pos) /*!< SCU SFSP9_5: EHD Mask */ + +/* --------------------------------- SCU_SFSP9_6 -------------------------------- */ +#define SCU_SFSP9_6_MODE_Pos 0 /*!< SCU SFSP9_6: MODE Position */ +#define SCU_SFSP9_6_MODE_Msk (0x07UL << SCU_SFSP9_6_MODE_Pos) /*!< SCU SFSP9_6: MODE Mask */ +#define SCU_SFSP9_6_EPD_Pos 3 /*!< SCU SFSP9_6: EPD Position */ +#define SCU_SFSP9_6_EPD_Msk (0x01UL << SCU_SFSP9_6_EPD_Pos) /*!< SCU SFSP9_6: EPD Mask */ +#define SCU_SFSP9_6_EPUN_Pos 4 /*!< SCU SFSP9_6: EPUN Position */ +#define SCU_SFSP9_6_EPUN_Msk (0x01UL << SCU_SFSP9_6_EPUN_Pos) /*!< SCU SFSP9_6: EPUN Mask */ +#define SCU_SFSP9_6_EHS_Pos 5 /*!< SCU SFSP9_6: EHS Position */ +#define SCU_SFSP9_6_EHS_Msk (0x01UL << SCU_SFSP9_6_EHS_Pos) /*!< SCU SFSP9_6: EHS Mask */ +#define SCU_SFSP9_6_EZI_Pos 6 /*!< SCU SFSP9_6: EZI Position */ +#define SCU_SFSP9_6_EZI_Msk (0x01UL << SCU_SFSP9_6_EZI_Pos) /*!< SCU SFSP9_6: EZI Mask */ +#define SCU_SFSP9_6_EHD_Pos 8 /*!< SCU SFSP9_6: EHD Position */ +#define SCU_SFSP9_6_EHD_Msk (0x03UL << SCU_SFSP9_6_EHD_Pos) /*!< SCU SFSP9_6: EHD Mask */ + +/* --------------------------------- SCU_SFSPA_0 -------------------------------- */ +#define SCU_SFSPA_0_MODE_Pos 0 /*!< SCU SFSPA_0: MODE Position */ +#define SCU_SFSPA_0_MODE_Msk (0x07UL << SCU_SFSPA_0_MODE_Pos) /*!< SCU SFSPA_0: MODE Mask */ +#define SCU_SFSPA_0_EPD_Pos 3 /*!< SCU SFSPA_0: EPD Position */ +#define SCU_SFSPA_0_EPD_Msk (0x01UL << SCU_SFSPA_0_EPD_Pos) /*!< SCU SFSPA_0: EPD Mask */ +#define SCU_SFSPA_0_EPUN_Pos 4 /*!< SCU SFSPA_0: EPUN Position */ +#define SCU_SFSPA_0_EPUN_Msk (0x01UL << SCU_SFSPA_0_EPUN_Pos) /*!< SCU SFSPA_0: EPUN Mask */ +#define SCU_SFSPA_0_EHS_Pos 5 /*!< SCU SFSPA_0: EHS Position */ +#define SCU_SFSPA_0_EHS_Msk (0x01UL << SCU_SFSPA_0_EHS_Pos) /*!< SCU SFSPA_0: EHS Mask */ +#define SCU_SFSPA_0_EZI_Pos 6 /*!< SCU SFSPA_0: EZI Position */ +#define SCU_SFSPA_0_EZI_Msk (0x01UL << SCU_SFSPA_0_EZI_Pos) /*!< SCU SFSPA_0: EZI Mask */ +#define SCU_SFSPA_0_ZIF_Pos 7 /*!< SCU SFSPA_0: ZIF Position */ +#define SCU_SFSPA_0_ZIF_Msk (0x01UL << SCU_SFSPA_0_ZIF_Pos) /*!< SCU SFSPA_0: ZIF Mask */ + +/* --------------------------------- SCU_SFSPA_1 -------------------------------- */ +#define SCU_SFSPA_1_MODE_Pos 0 /*!< SCU SFSPA_1: MODE Position */ +#define SCU_SFSPA_1_MODE_Msk (0x07UL << SCU_SFSPA_1_MODE_Pos) /*!< SCU SFSPA_1: MODE Mask */ +#define SCU_SFSPA_1_EPD_Pos 3 /*!< SCU SFSPA_1: EPD Position */ +#define SCU_SFSPA_1_EPD_Msk (0x01UL << SCU_SFSPA_1_EPD_Pos) /*!< SCU SFSPA_1: EPD Mask */ +#define SCU_SFSPA_1_EPUN_Pos 4 /*!< SCU SFSPA_1: EPUN Position */ +#define SCU_SFSPA_1_EPUN_Msk (0x01UL << SCU_SFSPA_1_EPUN_Pos) /*!< SCU SFSPA_1: EPUN Mask */ +#define SCU_SFSPA_1_EZI_Pos 6 /*!< SCU SFSPA_1: EZI Position */ +#define SCU_SFSPA_1_EZI_Msk (0x01UL << SCU_SFSPA_1_EZI_Pos) /*!< SCU SFSPA_1: EZI Mask */ +#define SCU_SFSPA_1_ZIF_Pos 7 /*!< SCU SFSPA_1: ZIF Position */ +#define SCU_SFSPA_1_ZIF_Msk (0x01UL << SCU_SFSPA_1_ZIF_Pos) /*!< SCU SFSPA_1: ZIF Mask */ +#define SCU_SFSPA_1_EHD_Pos 8 /*!< SCU SFSPA_1: EHD Position */ +#define SCU_SFSPA_1_EHD_Msk (0x03UL << SCU_SFSPA_1_EHD_Pos) /*!< SCU SFSPA_1: EHD Mask */ + +/* --------------------------------- SCU_SFSPA_2 -------------------------------- */ +#define SCU_SFSPA_2_MODE_Pos 0 /*!< SCU SFSPA_2: MODE Position */ +#define SCU_SFSPA_2_MODE_Msk (0x07UL << SCU_SFSPA_2_MODE_Pos) /*!< SCU SFSPA_2: MODE Mask */ +#define SCU_SFSPA_2_EPD_Pos 3 /*!< SCU SFSPA_2: EPD Position */ +#define SCU_SFSPA_2_EPD_Msk (0x01UL << SCU_SFSPA_2_EPD_Pos) /*!< SCU SFSPA_2: EPD Mask */ +#define SCU_SFSPA_2_EPUN_Pos 4 /*!< SCU SFSPA_2: EPUN Position */ +#define SCU_SFSPA_2_EPUN_Msk (0x01UL << SCU_SFSPA_2_EPUN_Pos) /*!< SCU SFSPA_2: EPUN Mask */ +#define SCU_SFSPA_2_EZI_Pos 6 /*!< SCU SFSPA_2: EZI Position */ +#define SCU_SFSPA_2_EZI_Msk (0x01UL << SCU_SFSPA_2_EZI_Pos) /*!< SCU SFSPA_2: EZI Mask */ +#define SCU_SFSPA_2_ZIF_Pos 7 /*!< SCU SFSPA_2: ZIF Position */ +#define SCU_SFSPA_2_ZIF_Msk (0x01UL << SCU_SFSPA_2_ZIF_Pos) /*!< SCU SFSPA_2: ZIF Mask */ +#define SCU_SFSPA_2_EHD_Pos 8 /*!< SCU SFSPA_2: EHD Position */ +#define SCU_SFSPA_2_EHD_Msk (0x03UL << SCU_SFSPA_2_EHD_Pos) /*!< SCU SFSPA_2: EHD Mask */ + +/* --------------------------------- SCU_SFSPA_3 -------------------------------- */ +#define SCU_SFSPA_3_MODE_Pos 0 /*!< SCU SFSPA_3: MODE Position */ +#define SCU_SFSPA_3_MODE_Msk (0x07UL << SCU_SFSPA_3_MODE_Pos) /*!< SCU SFSPA_3: MODE Mask */ +#define SCU_SFSPA_3_EPD_Pos 3 /*!< SCU SFSPA_3: EPD Position */ +#define SCU_SFSPA_3_EPD_Msk (0x01UL << SCU_SFSPA_3_EPD_Pos) /*!< SCU SFSPA_3: EPD Mask */ +#define SCU_SFSPA_3_EPUN_Pos 4 /*!< SCU SFSPA_3: EPUN Position */ +#define SCU_SFSPA_3_EPUN_Msk (0x01UL << SCU_SFSPA_3_EPUN_Pos) /*!< SCU SFSPA_3: EPUN Mask */ +#define SCU_SFSPA_3_EZI_Pos 6 /*!< SCU SFSPA_3: EZI Position */ +#define SCU_SFSPA_3_EZI_Msk (0x01UL << SCU_SFSPA_3_EZI_Pos) /*!< SCU SFSPA_3: EZI Mask */ +#define SCU_SFSPA_3_ZIF_Pos 7 /*!< SCU SFSPA_3: ZIF Position */ +#define SCU_SFSPA_3_ZIF_Msk (0x01UL << SCU_SFSPA_3_ZIF_Pos) /*!< SCU SFSPA_3: ZIF Mask */ +#define SCU_SFSPA_3_EHD_Pos 8 /*!< SCU SFSPA_3: EHD Position */ +#define SCU_SFSPA_3_EHD_Msk (0x03UL << SCU_SFSPA_3_EHD_Pos) /*!< SCU SFSPA_3: EHD Mask */ + +/* --------------------------------- SCU_SFSPA_4 -------------------------------- */ +#define SCU_SFSPA_4_MODE_Pos 0 /*!< SCU SFSPA_4: MODE Position */ +#define SCU_SFSPA_4_MODE_Msk (0x07UL << SCU_SFSPA_4_MODE_Pos) /*!< SCU SFSPA_4: MODE Mask */ +#define SCU_SFSPA_4_EPD_Pos 3 /*!< SCU SFSPA_4: EPD Position */ +#define SCU_SFSPA_4_EPD_Msk (0x01UL << SCU_SFSPA_4_EPD_Pos) /*!< SCU SFSPA_4: EPD Mask */ +#define SCU_SFSPA_4_EPUN_Pos 4 /*!< SCU SFSPA_4: EPUN Position */ +#define SCU_SFSPA_4_EPUN_Msk (0x01UL << SCU_SFSPA_4_EPUN_Pos) /*!< SCU SFSPA_4: EPUN Mask */ +#define SCU_SFSPA_4_EHS_Pos 5 /*!< SCU SFSPA_4: EHS Position */ +#define SCU_SFSPA_4_EHS_Msk (0x01UL << SCU_SFSPA_4_EHS_Pos) /*!< SCU SFSPA_4: EHS Mask */ +#define SCU_SFSPA_4_EZI_Pos 6 /*!< SCU SFSPA_4: EZI Position */ +#define SCU_SFSPA_4_EZI_Msk (0x01UL << SCU_SFSPA_4_EZI_Pos) /*!< SCU SFSPA_4: EZI Mask */ +#define SCU_SFSPA_4_ZIF_Pos 7 /*!< SCU SFSPA_4: ZIF Position */ +#define SCU_SFSPA_4_ZIF_Msk (0x01UL << SCU_SFSPA_4_ZIF_Pos) /*!< SCU SFSPA_4: ZIF Mask */ + +/* --------------------------------- SCU_SFSPB_0 -------------------------------- */ +#define SCU_SFSPB_0_MODE_Pos 0 /*!< SCU SFSPB_0: MODE Position */ +#define SCU_SFSPB_0_MODE_Msk (0x07UL << SCU_SFSPB_0_MODE_Pos) /*!< SCU SFSPB_0: MODE Mask */ +#define SCU_SFSPB_0_EPD_Pos 3 /*!< SCU SFSPB_0: EPD Position */ +#define SCU_SFSPB_0_EPD_Msk (0x01UL << SCU_SFSPB_0_EPD_Pos) /*!< SCU SFSPB_0: EPD Mask */ +#define SCU_SFSPB_0_EPUN_Pos 4 /*!< SCU SFSPB_0: EPUN Position */ +#define SCU_SFSPB_0_EPUN_Msk (0x01UL << SCU_SFSPB_0_EPUN_Pos) /*!< SCU SFSPB_0: EPUN Mask */ +#define SCU_SFSPB_0_EHS_Pos 5 /*!< SCU SFSPB_0: EHS Position */ +#define SCU_SFSPB_0_EHS_Msk (0x01UL << SCU_SFSPB_0_EHS_Pos) /*!< SCU SFSPB_0: EHS Mask */ +#define SCU_SFSPB_0_EZI_Pos 6 /*!< SCU SFSPB_0: EZI Position */ +#define SCU_SFSPB_0_EZI_Msk (0x01UL << SCU_SFSPB_0_EZI_Pos) /*!< SCU SFSPB_0: EZI Mask */ +#define SCU_SFSPB_0_ZIF_Pos 7 /*!< SCU SFSPB_0: ZIF Position */ +#define SCU_SFSPB_0_ZIF_Msk (0x01UL << SCU_SFSPB_0_ZIF_Pos) /*!< SCU SFSPB_0: ZIF Mask */ + +/* --------------------------------- SCU_SFSPB_1 -------------------------------- */ +#define SCU_SFSPB_1_MODE_Pos 0 /*!< SCU SFSPB_1: MODE Position */ +#define SCU_SFSPB_1_MODE_Msk (0x07UL << SCU_SFSPB_1_MODE_Pos) /*!< SCU SFSPB_1: MODE Mask */ +#define SCU_SFSPB_1_EPD_Pos 3 /*!< SCU SFSPB_1: EPD Position */ +#define SCU_SFSPB_1_EPD_Msk (0x01UL << SCU_SFSPB_1_EPD_Pos) /*!< SCU SFSPB_1: EPD Mask */ +#define SCU_SFSPB_1_EPUN_Pos 4 /*!< SCU SFSPB_1: EPUN Position */ +#define SCU_SFSPB_1_EPUN_Msk (0x01UL << SCU_SFSPB_1_EPUN_Pos) /*!< SCU SFSPB_1: EPUN Mask */ +#define SCU_SFSPB_1_EHS_Pos 5 /*!< SCU SFSPB_1: EHS Position */ +#define SCU_SFSPB_1_EHS_Msk (0x01UL << SCU_SFSPB_1_EHS_Pos) /*!< SCU SFSPB_1: EHS Mask */ +#define SCU_SFSPB_1_EZI_Pos 6 /*!< SCU SFSPB_1: EZI Position */ +#define SCU_SFSPB_1_EZI_Msk (0x01UL << SCU_SFSPB_1_EZI_Pos) /*!< SCU SFSPB_1: EZI Mask */ +#define SCU_SFSPB_1_ZIF_Pos 7 /*!< SCU SFSPB_1: ZIF Position */ +#define SCU_SFSPB_1_ZIF_Msk (0x01UL << SCU_SFSPB_1_ZIF_Pos) /*!< SCU SFSPB_1: ZIF Mask */ + +/* --------------------------------- SCU_SFSPB_2 -------------------------------- */ +#define SCU_SFSPB_2_MODE_Pos 0 /*!< SCU SFSPB_2: MODE Position */ +#define SCU_SFSPB_2_MODE_Msk (0x07UL << SCU_SFSPB_2_MODE_Pos) /*!< SCU SFSPB_2: MODE Mask */ +#define SCU_SFSPB_2_EPD_Pos 3 /*!< SCU SFSPB_2: EPD Position */ +#define SCU_SFSPB_2_EPD_Msk (0x01UL << SCU_SFSPB_2_EPD_Pos) /*!< SCU SFSPB_2: EPD Mask */ +#define SCU_SFSPB_2_EPUN_Pos 4 /*!< SCU SFSPB_2: EPUN Position */ +#define SCU_SFSPB_2_EPUN_Msk (0x01UL << SCU_SFSPB_2_EPUN_Pos) /*!< SCU SFSPB_2: EPUN Mask */ +#define SCU_SFSPB_2_EHS_Pos 5 /*!< SCU SFSPB_2: EHS Position */ +#define SCU_SFSPB_2_EHS_Msk (0x01UL << SCU_SFSPB_2_EHS_Pos) /*!< SCU SFSPB_2: EHS Mask */ +#define SCU_SFSPB_2_EZI_Pos 6 /*!< SCU SFSPB_2: EZI Position */ +#define SCU_SFSPB_2_EZI_Msk (0x01UL << SCU_SFSPB_2_EZI_Pos) /*!< SCU SFSPB_2: EZI Mask */ +#define SCU_SFSPB_2_ZIF_Pos 7 /*!< SCU SFSPB_2: ZIF Position */ +#define SCU_SFSPB_2_ZIF_Msk (0x01UL << SCU_SFSPB_2_ZIF_Pos) /*!< SCU SFSPB_2: ZIF Mask */ + +/* --------------------------------- SCU_SFSPB_3 -------------------------------- */ +#define SCU_SFSPB_3_MODE_Pos 0 /*!< SCU SFSPB_3: MODE Position */ +#define SCU_SFSPB_3_MODE_Msk (0x07UL << SCU_SFSPB_3_MODE_Pos) /*!< SCU SFSPB_3: MODE Mask */ +#define SCU_SFSPB_3_EPD_Pos 3 /*!< SCU SFSPB_3: EPD Position */ +#define SCU_SFSPB_3_EPD_Msk (0x01UL << SCU_SFSPB_3_EPD_Pos) /*!< SCU SFSPB_3: EPD Mask */ +#define SCU_SFSPB_3_EPUN_Pos 4 /*!< SCU SFSPB_3: EPUN Position */ +#define SCU_SFSPB_3_EPUN_Msk (0x01UL << SCU_SFSPB_3_EPUN_Pos) /*!< SCU SFSPB_3: EPUN Mask */ +#define SCU_SFSPB_3_EHS_Pos 5 /*!< SCU SFSPB_3: EHS Position */ +#define SCU_SFSPB_3_EHS_Msk (0x01UL << SCU_SFSPB_3_EHS_Pos) /*!< SCU SFSPB_3: EHS Mask */ +#define SCU_SFSPB_3_EZI_Pos 6 /*!< SCU SFSPB_3: EZI Position */ +#define SCU_SFSPB_3_EZI_Msk (0x01UL << SCU_SFSPB_3_EZI_Pos) /*!< SCU SFSPB_3: EZI Mask */ +#define SCU_SFSPB_3_ZIF_Pos 7 /*!< SCU SFSPB_3: ZIF Position */ +#define SCU_SFSPB_3_ZIF_Msk (0x01UL << SCU_SFSPB_3_ZIF_Pos) /*!< SCU SFSPB_3: ZIF Mask */ + +/* --------------------------------- SCU_SFSPB_4 -------------------------------- */ +#define SCU_SFSPB_4_MODE_Pos 0 /*!< SCU SFSPB_4: MODE Position */ +#define SCU_SFSPB_4_MODE_Msk (0x07UL << SCU_SFSPB_4_MODE_Pos) /*!< SCU SFSPB_4: MODE Mask */ +#define SCU_SFSPB_4_EPD_Pos 3 /*!< SCU SFSPB_4: EPD Position */ +#define SCU_SFSPB_4_EPD_Msk (0x01UL << SCU_SFSPB_4_EPD_Pos) /*!< SCU SFSPB_4: EPD Mask */ +#define SCU_SFSPB_4_EPUN_Pos 4 /*!< SCU SFSPB_4: EPUN Position */ +#define SCU_SFSPB_4_EPUN_Msk (0x01UL << SCU_SFSPB_4_EPUN_Pos) /*!< SCU SFSPB_4: EPUN Mask */ +#define SCU_SFSPB_4_EHS_Pos 5 /*!< SCU SFSPB_4: EHS Position */ +#define SCU_SFSPB_4_EHS_Msk (0x01UL << SCU_SFSPB_4_EHS_Pos) /*!< SCU SFSPB_4: EHS Mask */ +#define SCU_SFSPB_4_EZI_Pos 6 /*!< SCU SFSPB_4: EZI Position */ +#define SCU_SFSPB_4_EZI_Msk (0x01UL << SCU_SFSPB_4_EZI_Pos) /*!< SCU SFSPB_4: EZI Mask */ +#define SCU_SFSPB_4_ZIF_Pos 7 /*!< SCU SFSPB_4: ZIF Position */ +#define SCU_SFSPB_4_ZIF_Msk (0x01UL << SCU_SFSPB_4_ZIF_Pos) /*!< SCU SFSPB_4: ZIF Mask */ + +/* --------------------------------- SCU_SFSPB_5 -------------------------------- */ +#define SCU_SFSPB_5_MODE_Pos 0 /*!< SCU SFSPB_5: MODE Position */ +#define SCU_SFSPB_5_MODE_Msk (0x07UL << SCU_SFSPB_5_MODE_Pos) /*!< SCU SFSPB_5: MODE Mask */ +#define SCU_SFSPB_5_EPD_Pos 3 /*!< SCU SFSPB_5: EPD Position */ +#define SCU_SFSPB_5_EPD_Msk (0x01UL << SCU_SFSPB_5_EPD_Pos) /*!< SCU SFSPB_5: EPD Mask */ +#define SCU_SFSPB_5_EPUN_Pos 4 /*!< SCU SFSPB_5: EPUN Position */ +#define SCU_SFSPB_5_EPUN_Msk (0x01UL << SCU_SFSPB_5_EPUN_Pos) /*!< SCU SFSPB_5: EPUN Mask */ +#define SCU_SFSPB_5_EHS_Pos 5 /*!< SCU SFSPB_5: EHS Position */ +#define SCU_SFSPB_5_EHS_Msk (0x01UL << SCU_SFSPB_5_EHS_Pos) /*!< SCU SFSPB_5: EHS Mask */ +#define SCU_SFSPB_5_EZI_Pos 6 /*!< SCU SFSPB_5: EZI Position */ +#define SCU_SFSPB_5_EZI_Msk (0x01UL << SCU_SFSPB_5_EZI_Pos) /*!< SCU SFSPB_5: EZI Mask */ +#define SCU_SFSPB_5_ZIF_Pos 7 /*!< SCU SFSPB_5: ZIF Position */ +#define SCU_SFSPB_5_ZIF_Msk (0x01UL << SCU_SFSPB_5_ZIF_Pos) /*!< SCU SFSPB_5: ZIF Mask */ + +/* --------------------------------- SCU_SFSPB_6 -------------------------------- */ +#define SCU_SFSPB_6_MODE_Pos 0 /*!< SCU SFSPB_6: MODE Position */ +#define SCU_SFSPB_6_MODE_Msk (0x07UL << SCU_SFSPB_6_MODE_Pos) /*!< SCU SFSPB_6: MODE Mask */ +#define SCU_SFSPB_6_EPD_Pos 3 /*!< SCU SFSPB_6: EPD Position */ +#define SCU_SFSPB_6_EPD_Msk (0x01UL << SCU_SFSPB_6_EPD_Pos) /*!< SCU SFSPB_6: EPD Mask */ +#define SCU_SFSPB_6_EPUN_Pos 4 /*!< SCU SFSPB_6: EPUN Position */ +#define SCU_SFSPB_6_EPUN_Msk (0x01UL << SCU_SFSPB_6_EPUN_Pos) /*!< SCU SFSPB_6: EPUN Mask */ +#define SCU_SFSPB_6_EHS_Pos 5 /*!< SCU SFSPB_6: EHS Position */ +#define SCU_SFSPB_6_EHS_Msk (0x01UL << SCU_SFSPB_6_EHS_Pos) /*!< SCU SFSPB_6: EHS Mask */ +#define SCU_SFSPB_6_EZI_Pos 6 /*!< SCU SFSPB_6: EZI Position */ +#define SCU_SFSPB_6_EZI_Msk (0x01UL << SCU_SFSPB_6_EZI_Pos) /*!< SCU SFSPB_6: EZI Mask */ +#define SCU_SFSPB_6_ZIF_Pos 7 /*!< SCU SFSPB_6: ZIF Position */ +#define SCU_SFSPB_6_ZIF_Msk (0x01UL << SCU_SFSPB_6_ZIF_Pos) /*!< SCU SFSPB_6: ZIF Mask */ + +/* --------------------------------- SCU_SFSPC_0 -------------------------------- */ +#define SCU_SFSPC_0_MODE_Pos 0 /*!< SCU SFSPC_0: MODE Position */ +#define SCU_SFSPC_0_MODE_Msk (0x07UL << SCU_SFSPC_0_MODE_Pos) /*!< SCU SFSPC_0: MODE Mask */ +#define SCU_SFSPC_0_EPD_Pos 3 /*!< SCU SFSPC_0: EPD Position */ +#define SCU_SFSPC_0_EPD_Msk (0x01UL << SCU_SFSPC_0_EPD_Pos) /*!< SCU SFSPC_0: EPD Mask */ +#define SCU_SFSPC_0_EPUN_Pos 4 /*!< SCU SFSPC_0: EPUN Position */ +#define SCU_SFSPC_0_EPUN_Msk (0x01UL << SCU_SFSPC_0_EPUN_Pos) /*!< SCU SFSPC_0: EPUN Mask */ +#define SCU_SFSPC_0_EHS_Pos 5 /*!< SCU SFSPC_0: EHS Position */ +#define SCU_SFSPC_0_EHS_Msk (0x01UL << SCU_SFSPC_0_EHS_Pos) /*!< SCU SFSPC_0: EHS Mask */ +#define SCU_SFSPC_0_EZI_Pos 6 /*!< SCU SFSPC_0: EZI Position */ +#define SCU_SFSPC_0_EZI_Msk (0x01UL << SCU_SFSPC_0_EZI_Pos) /*!< SCU SFSPC_0: EZI Mask */ +#define SCU_SFSPC_0_ZIF_Pos 7 /*!< SCU SFSPC_0: ZIF Position */ +#define SCU_SFSPC_0_ZIF_Msk (0x01UL << SCU_SFSPC_0_ZIF_Pos) /*!< SCU SFSPC_0: ZIF Mask */ + +/* --------------------------------- SCU_SFSPC_1 -------------------------------- */ +#define SCU_SFSPC_1_MODE_Pos 0 /*!< SCU SFSPC_1: MODE Position */ +#define SCU_SFSPC_1_MODE_Msk (0x07UL << SCU_SFSPC_1_MODE_Pos) /*!< SCU SFSPC_1: MODE Mask */ +#define SCU_SFSPC_1_EPD_Pos 3 /*!< SCU SFSPC_1: EPD Position */ +#define SCU_SFSPC_1_EPD_Msk (0x01UL << SCU_SFSPC_1_EPD_Pos) /*!< SCU SFSPC_1: EPD Mask */ +#define SCU_SFSPC_1_EPUN_Pos 4 /*!< SCU SFSPC_1: EPUN Position */ +#define SCU_SFSPC_1_EPUN_Msk (0x01UL << SCU_SFSPC_1_EPUN_Pos) /*!< SCU SFSPC_1: EPUN Mask */ +#define SCU_SFSPC_1_EHS_Pos 5 /*!< SCU SFSPC_1: EHS Position */ +#define SCU_SFSPC_1_EHS_Msk (0x01UL << SCU_SFSPC_1_EHS_Pos) /*!< SCU SFSPC_1: EHS Mask */ +#define SCU_SFSPC_1_EZI_Pos 6 /*!< SCU SFSPC_1: EZI Position */ +#define SCU_SFSPC_1_EZI_Msk (0x01UL << SCU_SFSPC_1_EZI_Pos) /*!< SCU SFSPC_1: EZI Mask */ +#define SCU_SFSPC_1_ZIF_Pos 7 /*!< SCU SFSPC_1: ZIF Position */ +#define SCU_SFSPC_1_ZIF_Msk (0x01UL << SCU_SFSPC_1_ZIF_Pos) /*!< SCU SFSPC_1: ZIF Mask */ + +/* --------------------------------- SCU_SFSPC_2 -------------------------------- */ +#define SCU_SFSPC_2_MODE_Pos 0 /*!< SCU SFSPC_2: MODE Position */ +#define SCU_SFSPC_2_MODE_Msk (0x07UL << SCU_SFSPC_2_MODE_Pos) /*!< SCU SFSPC_2: MODE Mask */ +#define SCU_SFSPC_2_EPD_Pos 3 /*!< SCU SFSPC_2: EPD Position */ +#define SCU_SFSPC_2_EPD_Msk (0x01UL << SCU_SFSPC_2_EPD_Pos) /*!< SCU SFSPC_2: EPD Mask */ +#define SCU_SFSPC_2_EPUN_Pos 4 /*!< SCU SFSPC_2: EPUN Position */ +#define SCU_SFSPC_2_EPUN_Msk (0x01UL << SCU_SFSPC_2_EPUN_Pos) /*!< SCU SFSPC_2: EPUN Mask */ +#define SCU_SFSPC_2_EHS_Pos 5 /*!< SCU SFSPC_2: EHS Position */ +#define SCU_SFSPC_2_EHS_Msk (0x01UL << SCU_SFSPC_2_EHS_Pos) /*!< SCU SFSPC_2: EHS Mask */ +#define SCU_SFSPC_2_EZI_Pos 6 /*!< SCU SFSPC_2: EZI Position */ +#define SCU_SFSPC_2_EZI_Msk (0x01UL << SCU_SFSPC_2_EZI_Pos) /*!< SCU SFSPC_2: EZI Mask */ +#define SCU_SFSPC_2_ZIF_Pos 7 /*!< SCU SFSPC_2: ZIF Position */ +#define SCU_SFSPC_2_ZIF_Msk (0x01UL << SCU_SFSPC_2_ZIF_Pos) /*!< SCU SFSPC_2: ZIF Mask */ + +/* --------------------------------- SCU_SFSPC_3 -------------------------------- */ +#define SCU_SFSPC_3_MODE_Pos 0 /*!< SCU SFSPC_3: MODE Position */ +#define SCU_SFSPC_3_MODE_Msk (0x07UL << SCU_SFSPC_3_MODE_Pos) /*!< SCU SFSPC_3: MODE Mask */ +#define SCU_SFSPC_3_EPD_Pos 3 /*!< SCU SFSPC_3: EPD Position */ +#define SCU_SFSPC_3_EPD_Msk (0x01UL << SCU_SFSPC_3_EPD_Pos) /*!< SCU SFSPC_3: EPD Mask */ +#define SCU_SFSPC_3_EPUN_Pos 4 /*!< SCU SFSPC_3: EPUN Position */ +#define SCU_SFSPC_3_EPUN_Msk (0x01UL << SCU_SFSPC_3_EPUN_Pos) /*!< SCU SFSPC_3: EPUN Mask */ +#define SCU_SFSPC_3_EHS_Pos 5 /*!< SCU SFSPC_3: EHS Position */ +#define SCU_SFSPC_3_EHS_Msk (0x01UL << SCU_SFSPC_3_EHS_Pos) /*!< SCU SFSPC_3: EHS Mask */ +#define SCU_SFSPC_3_EZI_Pos 6 /*!< SCU SFSPC_3: EZI Position */ +#define SCU_SFSPC_3_EZI_Msk (0x01UL << SCU_SFSPC_3_EZI_Pos) /*!< SCU SFSPC_3: EZI Mask */ +#define SCU_SFSPC_3_ZIF_Pos 7 /*!< SCU SFSPC_3: ZIF Position */ +#define SCU_SFSPC_3_ZIF_Msk (0x01UL << SCU_SFSPC_3_ZIF_Pos) /*!< SCU SFSPC_3: ZIF Mask */ + +/* --------------------------------- SCU_SFSPC_4 -------------------------------- */ +#define SCU_SFSPC_4_MODE_Pos 0 /*!< SCU SFSPC_4: MODE Position */ +#define SCU_SFSPC_4_MODE_Msk (0x07UL << SCU_SFSPC_4_MODE_Pos) /*!< SCU SFSPC_4: MODE Mask */ +#define SCU_SFSPC_4_EPD_Pos 3 /*!< SCU SFSPC_4: EPD Position */ +#define SCU_SFSPC_4_EPD_Msk (0x01UL << SCU_SFSPC_4_EPD_Pos) /*!< SCU SFSPC_4: EPD Mask */ +#define SCU_SFSPC_4_EPUN_Pos 4 /*!< SCU SFSPC_4: EPUN Position */ +#define SCU_SFSPC_4_EPUN_Msk (0x01UL << SCU_SFSPC_4_EPUN_Pos) /*!< SCU SFSPC_4: EPUN Mask */ +#define SCU_SFSPC_4_EHS_Pos 5 /*!< SCU SFSPC_4: EHS Position */ +#define SCU_SFSPC_4_EHS_Msk (0x01UL << SCU_SFSPC_4_EHS_Pos) /*!< SCU SFSPC_4: EHS Mask */ +#define SCU_SFSPC_4_EZI_Pos 6 /*!< SCU SFSPC_4: EZI Position */ +#define SCU_SFSPC_4_EZI_Msk (0x01UL << SCU_SFSPC_4_EZI_Pos) /*!< SCU SFSPC_4: EZI Mask */ +#define SCU_SFSPC_4_ZIF_Pos 7 /*!< SCU SFSPC_4: ZIF Position */ +#define SCU_SFSPC_4_ZIF_Msk (0x01UL << SCU_SFSPC_4_ZIF_Pos) /*!< SCU SFSPC_4: ZIF Mask */ + +/* --------------------------------- SCU_SFSPC_5 -------------------------------- */ +#define SCU_SFSPC_5_MODE_Pos 0 /*!< SCU SFSPC_5: MODE Position */ +#define SCU_SFSPC_5_MODE_Msk (0x07UL << SCU_SFSPC_5_MODE_Pos) /*!< SCU SFSPC_5: MODE Mask */ +#define SCU_SFSPC_5_EPD_Pos 3 /*!< SCU SFSPC_5: EPD Position */ +#define SCU_SFSPC_5_EPD_Msk (0x01UL << SCU_SFSPC_5_EPD_Pos) /*!< SCU SFSPC_5: EPD Mask */ +#define SCU_SFSPC_5_EPUN_Pos 4 /*!< SCU SFSPC_5: EPUN Position */ +#define SCU_SFSPC_5_EPUN_Msk (0x01UL << SCU_SFSPC_5_EPUN_Pos) /*!< SCU SFSPC_5: EPUN Mask */ +#define SCU_SFSPC_5_EHS_Pos 5 /*!< SCU SFSPC_5: EHS Position */ +#define SCU_SFSPC_5_EHS_Msk (0x01UL << SCU_SFSPC_5_EHS_Pos) /*!< SCU SFSPC_5: EHS Mask */ +#define SCU_SFSPC_5_EZI_Pos 6 /*!< SCU SFSPC_5: EZI Position */ +#define SCU_SFSPC_5_EZI_Msk (0x01UL << SCU_SFSPC_5_EZI_Pos) /*!< SCU SFSPC_5: EZI Mask */ +#define SCU_SFSPC_5_ZIF_Pos 7 /*!< SCU SFSPC_5: ZIF Position */ +#define SCU_SFSPC_5_ZIF_Msk (0x01UL << SCU_SFSPC_5_ZIF_Pos) /*!< SCU SFSPC_5: ZIF Mask */ + +/* --------------------------------- SCU_SFSPC_6 -------------------------------- */ +#define SCU_SFSPC_6_MODE_Pos 0 /*!< SCU SFSPC_6: MODE Position */ +#define SCU_SFSPC_6_MODE_Msk (0x07UL << SCU_SFSPC_6_MODE_Pos) /*!< SCU SFSPC_6: MODE Mask */ +#define SCU_SFSPC_6_EPD_Pos 3 /*!< SCU SFSPC_6: EPD Position */ +#define SCU_SFSPC_6_EPD_Msk (0x01UL << SCU_SFSPC_6_EPD_Pos) /*!< SCU SFSPC_6: EPD Mask */ +#define SCU_SFSPC_6_EPUN_Pos 4 /*!< SCU SFSPC_6: EPUN Position */ +#define SCU_SFSPC_6_EPUN_Msk (0x01UL << SCU_SFSPC_6_EPUN_Pos) /*!< SCU SFSPC_6: EPUN Mask */ +#define SCU_SFSPC_6_EHS_Pos 5 /*!< SCU SFSPC_6: EHS Position */ +#define SCU_SFSPC_6_EHS_Msk (0x01UL << SCU_SFSPC_6_EHS_Pos) /*!< SCU SFSPC_6: EHS Mask */ +#define SCU_SFSPC_6_EZI_Pos 6 /*!< SCU SFSPC_6: EZI Position */ +#define SCU_SFSPC_6_EZI_Msk (0x01UL << SCU_SFSPC_6_EZI_Pos) /*!< SCU SFSPC_6: EZI Mask */ +#define SCU_SFSPC_6_ZIF_Pos 7 /*!< SCU SFSPC_6: ZIF Position */ +#define SCU_SFSPC_6_ZIF_Msk (0x01UL << SCU_SFSPC_6_ZIF_Pos) /*!< SCU SFSPC_6: ZIF Mask */ + +/* --------------------------------- SCU_SFSPC_7 -------------------------------- */ +#define SCU_SFSPC_7_MODE_Pos 0 /*!< SCU SFSPC_7: MODE Position */ +#define SCU_SFSPC_7_MODE_Msk (0x07UL << SCU_SFSPC_7_MODE_Pos) /*!< SCU SFSPC_7: MODE Mask */ +#define SCU_SFSPC_7_EPD_Pos 3 /*!< SCU SFSPC_7: EPD Position */ +#define SCU_SFSPC_7_EPD_Msk (0x01UL << SCU_SFSPC_7_EPD_Pos) /*!< SCU SFSPC_7: EPD Mask */ +#define SCU_SFSPC_7_EPUN_Pos 4 /*!< SCU SFSPC_7: EPUN Position */ +#define SCU_SFSPC_7_EPUN_Msk (0x01UL << SCU_SFSPC_7_EPUN_Pos) /*!< SCU SFSPC_7: EPUN Mask */ +#define SCU_SFSPC_7_EHS_Pos 5 /*!< SCU SFSPC_7: EHS Position */ +#define SCU_SFSPC_7_EHS_Msk (0x01UL << SCU_SFSPC_7_EHS_Pos) /*!< SCU SFSPC_7: EHS Mask */ +#define SCU_SFSPC_7_EZI_Pos 6 /*!< SCU SFSPC_7: EZI Position */ +#define SCU_SFSPC_7_EZI_Msk (0x01UL << SCU_SFSPC_7_EZI_Pos) /*!< SCU SFSPC_7: EZI Mask */ +#define SCU_SFSPC_7_ZIF_Pos 7 /*!< SCU SFSPC_7: ZIF Position */ +#define SCU_SFSPC_7_ZIF_Msk (0x01UL << SCU_SFSPC_7_ZIF_Pos) /*!< SCU SFSPC_7: ZIF Mask */ + +/* --------------------------------- SCU_SFSPC_8 -------------------------------- */ +#define SCU_SFSPC_8_MODE_Pos 0 /*!< SCU SFSPC_8: MODE Position */ +#define SCU_SFSPC_8_MODE_Msk (0x07UL << SCU_SFSPC_8_MODE_Pos) /*!< SCU SFSPC_8: MODE Mask */ +#define SCU_SFSPC_8_EPD_Pos 3 /*!< SCU SFSPC_8: EPD Position */ +#define SCU_SFSPC_8_EPD_Msk (0x01UL << SCU_SFSPC_8_EPD_Pos) /*!< SCU SFSPC_8: EPD Mask */ +#define SCU_SFSPC_8_EPUN_Pos 4 /*!< SCU SFSPC_8: EPUN Position */ +#define SCU_SFSPC_8_EPUN_Msk (0x01UL << SCU_SFSPC_8_EPUN_Pos) /*!< SCU SFSPC_8: EPUN Mask */ +#define SCU_SFSPC_8_EHS_Pos 5 /*!< SCU SFSPC_8: EHS Position */ +#define SCU_SFSPC_8_EHS_Msk (0x01UL << SCU_SFSPC_8_EHS_Pos) /*!< SCU SFSPC_8: EHS Mask */ +#define SCU_SFSPC_8_EZI_Pos 6 /*!< SCU SFSPC_8: EZI Position */ +#define SCU_SFSPC_8_EZI_Msk (0x01UL << SCU_SFSPC_8_EZI_Pos) /*!< SCU SFSPC_8: EZI Mask */ +#define SCU_SFSPC_8_ZIF_Pos 7 /*!< SCU SFSPC_8: ZIF Position */ +#define SCU_SFSPC_8_ZIF_Msk (0x01UL << SCU_SFSPC_8_ZIF_Pos) /*!< SCU SFSPC_8: ZIF Mask */ + +/* --------------------------------- SCU_SFSPC_9 -------------------------------- */ +#define SCU_SFSPC_9_MODE_Pos 0 /*!< SCU SFSPC_9: MODE Position */ +#define SCU_SFSPC_9_MODE_Msk (0x07UL << SCU_SFSPC_9_MODE_Pos) /*!< SCU SFSPC_9: MODE Mask */ +#define SCU_SFSPC_9_EPD_Pos 3 /*!< SCU SFSPC_9: EPD Position */ +#define SCU_SFSPC_9_EPD_Msk (0x01UL << SCU_SFSPC_9_EPD_Pos) /*!< SCU SFSPC_9: EPD Mask */ +#define SCU_SFSPC_9_EPUN_Pos 4 /*!< SCU SFSPC_9: EPUN Position */ +#define SCU_SFSPC_9_EPUN_Msk (0x01UL << SCU_SFSPC_9_EPUN_Pos) /*!< SCU SFSPC_9: EPUN Mask */ +#define SCU_SFSPC_9_EHS_Pos 5 /*!< SCU SFSPC_9: EHS Position */ +#define SCU_SFSPC_9_EHS_Msk (0x01UL << SCU_SFSPC_9_EHS_Pos) /*!< SCU SFSPC_9: EHS Mask */ +#define SCU_SFSPC_9_EZI_Pos 6 /*!< SCU SFSPC_9: EZI Position */ +#define SCU_SFSPC_9_EZI_Msk (0x01UL << SCU_SFSPC_9_EZI_Pos) /*!< SCU SFSPC_9: EZI Mask */ +#define SCU_SFSPC_9_ZIF_Pos 7 /*!< SCU SFSPC_9: ZIF Position */ +#define SCU_SFSPC_9_ZIF_Msk (0x01UL << SCU_SFSPC_9_ZIF_Pos) /*!< SCU SFSPC_9: ZIF Mask */ + +/* -------------------------------- SCU_SFSPC_10 -------------------------------- */ +#define SCU_SFSPC_10_MODE_Pos 0 /*!< SCU SFSPC_10: MODE Position */ +#define SCU_SFSPC_10_MODE_Msk (0x07UL << SCU_SFSPC_10_MODE_Pos) /*!< SCU SFSPC_10: MODE Mask */ +#define SCU_SFSPC_10_EPD_Pos 3 /*!< SCU SFSPC_10: EPD Position */ +#define SCU_SFSPC_10_EPD_Msk (0x01UL << SCU_SFSPC_10_EPD_Pos) /*!< SCU SFSPC_10: EPD Mask */ +#define SCU_SFSPC_10_EPUN_Pos 4 /*!< SCU SFSPC_10: EPUN Position */ +#define SCU_SFSPC_10_EPUN_Msk (0x01UL << SCU_SFSPC_10_EPUN_Pos) /*!< SCU SFSPC_10: EPUN Mask */ +#define SCU_SFSPC_10_EHS_Pos 5 /*!< SCU SFSPC_10: EHS Position */ +#define SCU_SFSPC_10_EHS_Msk (0x01UL << SCU_SFSPC_10_EHS_Pos) /*!< SCU SFSPC_10: EHS Mask */ +#define SCU_SFSPC_10_EZI_Pos 6 /*!< SCU SFSPC_10: EZI Position */ +#define SCU_SFSPC_10_EZI_Msk (0x01UL << SCU_SFSPC_10_EZI_Pos) /*!< SCU SFSPC_10: EZI Mask */ +#define SCU_SFSPC_10_ZIF_Pos 7 /*!< SCU SFSPC_10: ZIF Position */ +#define SCU_SFSPC_10_ZIF_Msk (0x01UL << SCU_SFSPC_10_ZIF_Pos) /*!< SCU SFSPC_10: ZIF Mask */ + +/* -------------------------------- SCU_SFSPC_11 -------------------------------- */ +#define SCU_SFSPC_11_MODE_Pos 0 /*!< SCU SFSPC_11: MODE Position */ +#define SCU_SFSPC_11_MODE_Msk (0x07UL << SCU_SFSPC_11_MODE_Pos) /*!< SCU SFSPC_11: MODE Mask */ +#define SCU_SFSPC_11_EPD_Pos 3 /*!< SCU SFSPC_11: EPD Position */ +#define SCU_SFSPC_11_EPD_Msk (0x01UL << SCU_SFSPC_11_EPD_Pos) /*!< SCU SFSPC_11: EPD Mask */ +#define SCU_SFSPC_11_EPUN_Pos 4 /*!< SCU SFSPC_11: EPUN Position */ +#define SCU_SFSPC_11_EPUN_Msk (0x01UL << SCU_SFSPC_11_EPUN_Pos) /*!< SCU SFSPC_11: EPUN Mask */ +#define SCU_SFSPC_11_EHS_Pos 5 /*!< SCU SFSPC_11: EHS Position */ +#define SCU_SFSPC_11_EHS_Msk (0x01UL << SCU_SFSPC_11_EHS_Pos) /*!< SCU SFSPC_11: EHS Mask */ +#define SCU_SFSPC_11_EZI_Pos 6 /*!< SCU SFSPC_11: EZI Position */ +#define SCU_SFSPC_11_EZI_Msk (0x01UL << SCU_SFSPC_11_EZI_Pos) /*!< SCU SFSPC_11: EZI Mask */ +#define SCU_SFSPC_11_ZIF_Pos 7 /*!< SCU SFSPC_11: ZIF Position */ +#define SCU_SFSPC_11_ZIF_Msk (0x01UL << SCU_SFSPC_11_ZIF_Pos) /*!< SCU SFSPC_11: ZIF Mask */ + +/* -------------------------------- SCU_SFSPC_12 -------------------------------- */ +#define SCU_SFSPC_12_MODE_Pos 0 /*!< SCU SFSPC_12: MODE Position */ +#define SCU_SFSPC_12_MODE_Msk (0x07UL << SCU_SFSPC_12_MODE_Pos) /*!< SCU SFSPC_12: MODE Mask */ +#define SCU_SFSPC_12_EPD_Pos 3 /*!< SCU SFSPC_12: EPD Position */ +#define SCU_SFSPC_12_EPD_Msk (0x01UL << SCU_SFSPC_12_EPD_Pos) /*!< SCU SFSPC_12: EPD Mask */ +#define SCU_SFSPC_12_EPUN_Pos 4 /*!< SCU SFSPC_12: EPUN Position */ +#define SCU_SFSPC_12_EPUN_Msk (0x01UL << SCU_SFSPC_12_EPUN_Pos) /*!< SCU SFSPC_12: EPUN Mask */ +#define SCU_SFSPC_12_EHS_Pos 5 /*!< SCU SFSPC_12: EHS Position */ +#define SCU_SFSPC_12_EHS_Msk (0x01UL << SCU_SFSPC_12_EHS_Pos) /*!< SCU SFSPC_12: EHS Mask */ +#define SCU_SFSPC_12_EZI_Pos 6 /*!< SCU SFSPC_12: EZI Position */ +#define SCU_SFSPC_12_EZI_Msk (0x01UL << SCU_SFSPC_12_EZI_Pos) /*!< SCU SFSPC_12: EZI Mask */ +#define SCU_SFSPC_12_ZIF_Pos 7 /*!< SCU SFSPC_12: ZIF Position */ +#define SCU_SFSPC_12_ZIF_Msk (0x01UL << SCU_SFSPC_12_ZIF_Pos) /*!< SCU SFSPC_12: ZIF Mask */ + +/* -------------------------------- SCU_SFSPC_13 -------------------------------- */ +#define SCU_SFSPC_13_MODE_Pos 0 /*!< SCU SFSPC_13: MODE Position */ +#define SCU_SFSPC_13_MODE_Msk (0x07UL << SCU_SFSPC_13_MODE_Pos) /*!< SCU SFSPC_13: MODE Mask */ +#define SCU_SFSPC_13_EPD_Pos 3 /*!< SCU SFSPC_13: EPD Position */ +#define SCU_SFSPC_13_EPD_Msk (0x01UL << SCU_SFSPC_13_EPD_Pos) /*!< SCU SFSPC_13: EPD Mask */ +#define SCU_SFSPC_13_EPUN_Pos 4 /*!< SCU SFSPC_13: EPUN Position */ +#define SCU_SFSPC_13_EPUN_Msk (0x01UL << SCU_SFSPC_13_EPUN_Pos) /*!< SCU SFSPC_13: EPUN Mask */ +#define SCU_SFSPC_13_EHS_Pos 5 /*!< SCU SFSPC_13: EHS Position */ +#define SCU_SFSPC_13_EHS_Msk (0x01UL << SCU_SFSPC_13_EHS_Pos) /*!< SCU SFSPC_13: EHS Mask */ +#define SCU_SFSPC_13_EZI_Pos 6 /*!< SCU SFSPC_13: EZI Position */ +#define SCU_SFSPC_13_EZI_Msk (0x01UL << SCU_SFSPC_13_EZI_Pos) /*!< SCU SFSPC_13: EZI Mask */ +#define SCU_SFSPC_13_ZIF_Pos 7 /*!< SCU SFSPC_13: ZIF Position */ +#define SCU_SFSPC_13_ZIF_Msk (0x01UL << SCU_SFSPC_13_ZIF_Pos) /*!< SCU SFSPC_13: ZIF Mask */ + +/* -------------------------------- SCU_SFSPC_14 -------------------------------- */ +#define SCU_SFSPC_14_MODE_Pos 0 /*!< SCU SFSPC_14: MODE Position */ +#define SCU_SFSPC_14_MODE_Msk (0x07UL << SCU_SFSPC_14_MODE_Pos) /*!< SCU SFSPC_14: MODE Mask */ +#define SCU_SFSPC_14_EPD_Pos 3 /*!< SCU SFSPC_14: EPD Position */ +#define SCU_SFSPC_14_EPD_Msk (0x01UL << SCU_SFSPC_14_EPD_Pos) /*!< SCU SFSPC_14: EPD Mask */ +#define SCU_SFSPC_14_EPUN_Pos 4 /*!< SCU SFSPC_14: EPUN Position */ +#define SCU_SFSPC_14_EPUN_Msk (0x01UL << SCU_SFSPC_14_EPUN_Pos) /*!< SCU SFSPC_14: EPUN Mask */ +#define SCU_SFSPC_14_EHS_Pos 5 /*!< SCU SFSPC_14: EHS Position */ +#define SCU_SFSPC_14_EHS_Msk (0x01UL << SCU_SFSPC_14_EHS_Pos) /*!< SCU SFSPC_14: EHS Mask */ +#define SCU_SFSPC_14_EZI_Pos 6 /*!< SCU SFSPC_14: EZI Position */ +#define SCU_SFSPC_14_EZI_Msk (0x01UL << SCU_SFSPC_14_EZI_Pos) /*!< SCU SFSPC_14: EZI Mask */ +#define SCU_SFSPC_14_ZIF_Pos 7 /*!< SCU SFSPC_14: ZIF Position */ +#define SCU_SFSPC_14_ZIF_Msk (0x01UL << SCU_SFSPC_14_ZIF_Pos) /*!< SCU SFSPC_14: ZIF Mask */ + +/* --------------------------------- SCU_SFSPD_0 -------------------------------- */ +#define SCU_SFSPD_0_MODE_Pos 0 /*!< SCU SFSPD_0: MODE Position */ +#define SCU_SFSPD_0_MODE_Msk (0x07UL << SCU_SFSPD_0_MODE_Pos) /*!< SCU SFSPD_0: MODE Mask */ +#define SCU_SFSPD_0_EPD_Pos 3 /*!< SCU SFSPD_0: EPD Position */ +#define SCU_SFSPD_0_EPD_Msk (0x01UL << SCU_SFSPD_0_EPD_Pos) /*!< SCU SFSPD_0: EPD Mask */ +#define SCU_SFSPD_0_EPUN_Pos 4 /*!< SCU SFSPD_0: EPUN Position */ +#define SCU_SFSPD_0_EPUN_Msk (0x01UL << SCU_SFSPD_0_EPUN_Pos) /*!< SCU SFSPD_0: EPUN Mask */ +#define SCU_SFSPD_0_EHS_Pos 5 /*!< SCU SFSPD_0: EHS Position */ +#define SCU_SFSPD_0_EHS_Msk (0x01UL << SCU_SFSPD_0_EHS_Pos) /*!< SCU SFSPD_0: EHS Mask */ +#define SCU_SFSPD_0_EZI_Pos 6 /*!< SCU SFSPD_0: EZI Position */ +#define SCU_SFSPD_0_EZI_Msk (0x01UL << SCU_SFSPD_0_EZI_Pos) /*!< SCU SFSPD_0: EZI Mask */ +#define SCU_SFSPD_0_ZIF_Pos 7 /*!< SCU SFSPD_0: ZIF Position */ +#define SCU_SFSPD_0_ZIF_Msk (0x01UL << SCU_SFSPD_0_ZIF_Pos) /*!< SCU SFSPD_0: ZIF Mask */ + +/* --------------------------------- SCU_SFSPD_1 -------------------------------- */ +#define SCU_SFSPD_1_MODE_Pos 0 /*!< SCU SFSPD_1: MODE Position */ +#define SCU_SFSPD_1_MODE_Msk (0x07UL << SCU_SFSPD_1_MODE_Pos) /*!< SCU SFSPD_1: MODE Mask */ +#define SCU_SFSPD_1_EPD_Pos 3 /*!< SCU SFSPD_1: EPD Position */ +#define SCU_SFSPD_1_EPD_Msk (0x01UL << SCU_SFSPD_1_EPD_Pos) /*!< SCU SFSPD_1: EPD Mask */ +#define SCU_SFSPD_1_EPUN_Pos 4 /*!< SCU SFSPD_1: EPUN Position */ +#define SCU_SFSPD_1_EPUN_Msk (0x01UL << SCU_SFSPD_1_EPUN_Pos) /*!< SCU SFSPD_1: EPUN Mask */ +#define SCU_SFSPD_1_EHS_Pos 5 /*!< SCU SFSPD_1: EHS Position */ +#define SCU_SFSPD_1_EHS_Msk (0x01UL << SCU_SFSPD_1_EHS_Pos) /*!< SCU SFSPD_1: EHS Mask */ +#define SCU_SFSPD_1_EZI_Pos 6 /*!< SCU SFSPD_1: EZI Position */ +#define SCU_SFSPD_1_EZI_Msk (0x01UL << SCU_SFSPD_1_EZI_Pos) /*!< SCU SFSPD_1: EZI Mask */ +#define SCU_SFSPD_1_ZIF_Pos 7 /*!< SCU SFSPD_1: ZIF Position */ +#define SCU_SFSPD_1_ZIF_Msk (0x01UL << SCU_SFSPD_1_ZIF_Pos) /*!< SCU SFSPD_1: ZIF Mask */ + +/* --------------------------------- SCU_SFSPD_2 -------------------------------- */ +#define SCU_SFSPD_2_MODE_Pos 0 /*!< SCU SFSPD_2: MODE Position */ +#define SCU_SFSPD_2_MODE_Msk (0x07UL << SCU_SFSPD_2_MODE_Pos) /*!< SCU SFSPD_2: MODE Mask */ +#define SCU_SFSPD_2_EPD_Pos 3 /*!< SCU SFSPD_2: EPD Position */ +#define SCU_SFSPD_2_EPD_Msk (0x01UL << SCU_SFSPD_2_EPD_Pos) /*!< SCU SFSPD_2: EPD Mask */ +#define SCU_SFSPD_2_EPUN_Pos 4 /*!< SCU SFSPD_2: EPUN Position */ +#define SCU_SFSPD_2_EPUN_Msk (0x01UL << SCU_SFSPD_2_EPUN_Pos) /*!< SCU SFSPD_2: EPUN Mask */ +#define SCU_SFSPD_2_EHS_Pos 5 /*!< SCU SFSPD_2: EHS Position */ +#define SCU_SFSPD_2_EHS_Msk (0x01UL << SCU_SFSPD_2_EHS_Pos) /*!< SCU SFSPD_2: EHS Mask */ +#define SCU_SFSPD_2_EZI_Pos 6 /*!< SCU SFSPD_2: EZI Position */ +#define SCU_SFSPD_2_EZI_Msk (0x01UL << SCU_SFSPD_2_EZI_Pos) /*!< SCU SFSPD_2: EZI Mask */ +#define SCU_SFSPD_2_ZIF_Pos 7 /*!< SCU SFSPD_2: ZIF Position */ +#define SCU_SFSPD_2_ZIF_Msk (0x01UL << SCU_SFSPD_2_ZIF_Pos) /*!< SCU SFSPD_2: ZIF Mask */ + +/* --------------------------------- SCU_SFSPD_3 -------------------------------- */ +#define SCU_SFSPD_3_MODE_Pos 0 /*!< SCU SFSPD_3: MODE Position */ +#define SCU_SFSPD_3_MODE_Msk (0x07UL << SCU_SFSPD_3_MODE_Pos) /*!< SCU SFSPD_3: MODE Mask */ +#define SCU_SFSPD_3_EPD_Pos 3 /*!< SCU SFSPD_3: EPD Position */ +#define SCU_SFSPD_3_EPD_Msk (0x01UL << SCU_SFSPD_3_EPD_Pos) /*!< SCU SFSPD_3: EPD Mask */ +#define SCU_SFSPD_3_EPUN_Pos 4 /*!< SCU SFSPD_3: EPUN Position */ +#define SCU_SFSPD_3_EPUN_Msk (0x01UL << SCU_SFSPD_3_EPUN_Pos) /*!< SCU SFSPD_3: EPUN Mask */ +#define SCU_SFSPD_3_EHS_Pos 5 /*!< SCU SFSPD_3: EHS Position */ +#define SCU_SFSPD_3_EHS_Msk (0x01UL << SCU_SFSPD_3_EHS_Pos) /*!< SCU SFSPD_3: EHS Mask */ +#define SCU_SFSPD_3_EZI_Pos 6 /*!< SCU SFSPD_3: EZI Position */ +#define SCU_SFSPD_3_EZI_Msk (0x01UL << SCU_SFSPD_3_EZI_Pos) /*!< SCU SFSPD_3: EZI Mask */ +#define SCU_SFSPD_3_ZIF_Pos 7 /*!< SCU SFSPD_3: ZIF Position */ +#define SCU_SFSPD_3_ZIF_Msk (0x01UL << SCU_SFSPD_3_ZIF_Pos) /*!< SCU SFSPD_3: ZIF Mask */ + +/* --------------------------------- SCU_SFSPD_4 -------------------------------- */ +#define SCU_SFSPD_4_MODE_Pos 0 /*!< SCU SFSPD_4: MODE Position */ +#define SCU_SFSPD_4_MODE_Msk (0x07UL << SCU_SFSPD_4_MODE_Pos) /*!< SCU SFSPD_4: MODE Mask */ +#define SCU_SFSPD_4_EPD_Pos 3 /*!< SCU SFSPD_4: EPD Position */ +#define SCU_SFSPD_4_EPD_Msk (0x01UL << SCU_SFSPD_4_EPD_Pos) /*!< SCU SFSPD_4: EPD Mask */ +#define SCU_SFSPD_4_EPUN_Pos 4 /*!< SCU SFSPD_4: EPUN Position */ +#define SCU_SFSPD_4_EPUN_Msk (0x01UL << SCU_SFSPD_4_EPUN_Pos) /*!< SCU SFSPD_4: EPUN Mask */ +#define SCU_SFSPD_4_EHS_Pos 5 /*!< SCU SFSPD_4: EHS Position */ +#define SCU_SFSPD_4_EHS_Msk (0x01UL << SCU_SFSPD_4_EHS_Pos) /*!< SCU SFSPD_4: EHS Mask */ +#define SCU_SFSPD_4_EZI_Pos 6 /*!< SCU SFSPD_4: EZI Position */ +#define SCU_SFSPD_4_EZI_Msk (0x01UL << SCU_SFSPD_4_EZI_Pos) /*!< SCU SFSPD_4: EZI Mask */ +#define SCU_SFSPD_4_ZIF_Pos 7 /*!< SCU SFSPD_4: ZIF Position */ +#define SCU_SFSPD_4_ZIF_Msk (0x01UL << SCU_SFSPD_4_ZIF_Pos) /*!< SCU SFSPD_4: ZIF Mask */ + +/* --------------------------------- SCU_SFSPD_5 -------------------------------- */ +#define SCU_SFSPD_5_MODE_Pos 0 /*!< SCU SFSPD_5: MODE Position */ +#define SCU_SFSPD_5_MODE_Msk (0x07UL << SCU_SFSPD_5_MODE_Pos) /*!< SCU SFSPD_5: MODE Mask */ +#define SCU_SFSPD_5_EPD_Pos 3 /*!< SCU SFSPD_5: EPD Position */ +#define SCU_SFSPD_5_EPD_Msk (0x01UL << SCU_SFSPD_5_EPD_Pos) /*!< SCU SFSPD_5: EPD Mask */ +#define SCU_SFSPD_5_EPUN_Pos 4 /*!< SCU SFSPD_5: EPUN Position */ +#define SCU_SFSPD_5_EPUN_Msk (0x01UL << SCU_SFSPD_5_EPUN_Pos) /*!< SCU SFSPD_5: EPUN Mask */ +#define SCU_SFSPD_5_EHS_Pos 5 /*!< SCU SFSPD_5: EHS Position */ +#define SCU_SFSPD_5_EHS_Msk (0x01UL << SCU_SFSPD_5_EHS_Pos) /*!< SCU SFSPD_5: EHS Mask */ +#define SCU_SFSPD_5_EZI_Pos 6 /*!< SCU SFSPD_5: EZI Position */ +#define SCU_SFSPD_5_EZI_Msk (0x01UL << SCU_SFSPD_5_EZI_Pos) /*!< SCU SFSPD_5: EZI Mask */ +#define SCU_SFSPD_5_ZIF_Pos 7 /*!< SCU SFSPD_5: ZIF Position */ +#define SCU_SFSPD_5_ZIF_Msk (0x01UL << SCU_SFSPD_5_ZIF_Pos) /*!< SCU SFSPD_5: ZIF Mask */ + +/* --------------------------------- SCU_SFSPD_6 -------------------------------- */ +#define SCU_SFSPD_6_MODE_Pos 0 /*!< SCU SFSPD_6: MODE Position */ +#define SCU_SFSPD_6_MODE_Msk (0x07UL << SCU_SFSPD_6_MODE_Pos) /*!< SCU SFSPD_6: MODE Mask */ +#define SCU_SFSPD_6_EPD_Pos 3 /*!< SCU SFSPD_6: EPD Position */ +#define SCU_SFSPD_6_EPD_Msk (0x01UL << SCU_SFSPD_6_EPD_Pos) /*!< SCU SFSPD_6: EPD Mask */ +#define SCU_SFSPD_6_EPUN_Pos 4 /*!< SCU SFSPD_6: EPUN Position */ +#define SCU_SFSPD_6_EPUN_Msk (0x01UL << SCU_SFSPD_6_EPUN_Pos) /*!< SCU SFSPD_6: EPUN Mask */ +#define SCU_SFSPD_6_EHS_Pos 5 /*!< SCU SFSPD_6: EHS Position */ +#define SCU_SFSPD_6_EHS_Msk (0x01UL << SCU_SFSPD_6_EHS_Pos) /*!< SCU SFSPD_6: EHS Mask */ +#define SCU_SFSPD_6_EZI_Pos 6 /*!< SCU SFSPD_6: EZI Position */ +#define SCU_SFSPD_6_EZI_Msk (0x01UL << SCU_SFSPD_6_EZI_Pos) /*!< SCU SFSPD_6: EZI Mask */ +#define SCU_SFSPD_6_ZIF_Pos 7 /*!< SCU SFSPD_6: ZIF Position */ +#define SCU_SFSPD_6_ZIF_Msk (0x01UL << SCU_SFSPD_6_ZIF_Pos) /*!< SCU SFSPD_6: ZIF Mask */ + +/* --------------------------------- SCU_SFSPD_7 -------------------------------- */ +#define SCU_SFSPD_7_MODE_Pos 0 /*!< SCU SFSPD_7: MODE Position */ +#define SCU_SFSPD_7_MODE_Msk (0x07UL << SCU_SFSPD_7_MODE_Pos) /*!< SCU SFSPD_7: MODE Mask */ +#define SCU_SFSPD_7_EPD_Pos 3 /*!< SCU SFSPD_7: EPD Position */ +#define SCU_SFSPD_7_EPD_Msk (0x01UL << SCU_SFSPD_7_EPD_Pos) /*!< SCU SFSPD_7: EPD Mask */ +#define SCU_SFSPD_7_EPUN_Pos 4 /*!< SCU SFSPD_7: EPUN Position */ +#define SCU_SFSPD_7_EPUN_Msk (0x01UL << SCU_SFSPD_7_EPUN_Pos) /*!< SCU SFSPD_7: EPUN Mask */ +#define SCU_SFSPD_7_EHS_Pos 5 /*!< SCU SFSPD_7: EHS Position */ +#define SCU_SFSPD_7_EHS_Msk (0x01UL << SCU_SFSPD_7_EHS_Pos) /*!< SCU SFSPD_7: EHS Mask */ +#define SCU_SFSPD_7_EZI_Pos 6 /*!< SCU SFSPD_7: EZI Position */ +#define SCU_SFSPD_7_EZI_Msk (0x01UL << SCU_SFSPD_7_EZI_Pos) /*!< SCU SFSPD_7: EZI Mask */ +#define SCU_SFSPD_7_ZIF_Pos 7 /*!< SCU SFSPD_7: ZIF Position */ +#define SCU_SFSPD_7_ZIF_Msk (0x01UL << SCU_SFSPD_7_ZIF_Pos) /*!< SCU SFSPD_7: ZIF Mask */ + +/* --------------------------------- SCU_SFSPD_8 -------------------------------- */ +#define SCU_SFSPD_8_MODE_Pos 0 /*!< SCU SFSPD_8: MODE Position */ +#define SCU_SFSPD_8_MODE_Msk (0x07UL << SCU_SFSPD_8_MODE_Pos) /*!< SCU SFSPD_8: MODE Mask */ +#define SCU_SFSPD_8_EPD_Pos 3 /*!< SCU SFSPD_8: EPD Position */ +#define SCU_SFSPD_8_EPD_Msk (0x01UL << SCU_SFSPD_8_EPD_Pos) /*!< SCU SFSPD_8: EPD Mask */ +#define SCU_SFSPD_8_EPUN_Pos 4 /*!< SCU SFSPD_8: EPUN Position */ +#define SCU_SFSPD_8_EPUN_Msk (0x01UL << SCU_SFSPD_8_EPUN_Pos) /*!< SCU SFSPD_8: EPUN Mask */ +#define SCU_SFSPD_8_EHS_Pos 5 /*!< SCU SFSPD_8: EHS Position */ +#define SCU_SFSPD_8_EHS_Msk (0x01UL << SCU_SFSPD_8_EHS_Pos) /*!< SCU SFSPD_8: EHS Mask */ +#define SCU_SFSPD_8_EZI_Pos 6 /*!< SCU SFSPD_8: EZI Position */ +#define SCU_SFSPD_8_EZI_Msk (0x01UL << SCU_SFSPD_8_EZI_Pos) /*!< SCU SFSPD_8: EZI Mask */ +#define SCU_SFSPD_8_ZIF_Pos 7 /*!< SCU SFSPD_8: ZIF Position */ +#define SCU_SFSPD_8_ZIF_Msk (0x01UL << SCU_SFSPD_8_ZIF_Pos) /*!< SCU SFSPD_8: ZIF Mask */ + +/* --------------------------------- SCU_SFSPD_9 -------------------------------- */ +#define SCU_SFSPD_9_MODE_Pos 0 /*!< SCU SFSPD_9: MODE Position */ +#define SCU_SFSPD_9_MODE_Msk (0x07UL << SCU_SFSPD_9_MODE_Pos) /*!< SCU SFSPD_9: MODE Mask */ +#define SCU_SFSPD_9_EPD_Pos 3 /*!< SCU SFSPD_9: EPD Position */ +#define SCU_SFSPD_9_EPD_Msk (0x01UL << SCU_SFSPD_9_EPD_Pos) /*!< SCU SFSPD_9: EPD Mask */ +#define SCU_SFSPD_9_EPUN_Pos 4 /*!< SCU SFSPD_9: EPUN Position */ +#define SCU_SFSPD_9_EPUN_Msk (0x01UL << SCU_SFSPD_9_EPUN_Pos) /*!< SCU SFSPD_9: EPUN Mask */ +#define SCU_SFSPD_9_EHS_Pos 5 /*!< SCU SFSPD_9: EHS Position */ +#define SCU_SFSPD_9_EHS_Msk (0x01UL << SCU_SFSPD_9_EHS_Pos) /*!< SCU SFSPD_9: EHS Mask */ +#define SCU_SFSPD_9_EZI_Pos 6 /*!< SCU SFSPD_9: EZI Position */ +#define SCU_SFSPD_9_EZI_Msk (0x01UL << SCU_SFSPD_9_EZI_Pos) /*!< SCU SFSPD_9: EZI Mask */ +#define SCU_SFSPD_9_ZIF_Pos 7 /*!< SCU SFSPD_9: ZIF Position */ +#define SCU_SFSPD_9_ZIF_Msk (0x01UL << SCU_SFSPD_9_ZIF_Pos) /*!< SCU SFSPD_9: ZIF Mask */ + +/* -------------------------------- SCU_SFSPD_10 -------------------------------- */ +#define SCU_SFSPD_10_MODE_Pos 0 /*!< SCU SFSPD_10: MODE Position */ +#define SCU_SFSPD_10_MODE_Msk (0x07UL << SCU_SFSPD_10_MODE_Pos) /*!< SCU SFSPD_10: MODE Mask */ +#define SCU_SFSPD_10_EPD_Pos 3 /*!< SCU SFSPD_10: EPD Position */ +#define SCU_SFSPD_10_EPD_Msk (0x01UL << SCU_SFSPD_10_EPD_Pos) /*!< SCU SFSPD_10: EPD Mask */ +#define SCU_SFSPD_10_EPUN_Pos 4 /*!< SCU SFSPD_10: EPUN Position */ +#define SCU_SFSPD_10_EPUN_Msk (0x01UL << SCU_SFSPD_10_EPUN_Pos) /*!< SCU SFSPD_10: EPUN Mask */ +#define SCU_SFSPD_10_EHS_Pos 5 /*!< SCU SFSPD_10: EHS Position */ +#define SCU_SFSPD_10_EHS_Msk (0x01UL << SCU_SFSPD_10_EHS_Pos) /*!< SCU SFSPD_10: EHS Mask */ +#define SCU_SFSPD_10_EZI_Pos 6 /*!< SCU SFSPD_10: EZI Position */ +#define SCU_SFSPD_10_EZI_Msk (0x01UL << SCU_SFSPD_10_EZI_Pos) /*!< SCU SFSPD_10: EZI Mask */ +#define SCU_SFSPD_10_ZIF_Pos 7 /*!< SCU SFSPD_10: ZIF Position */ +#define SCU_SFSPD_10_ZIF_Msk (0x01UL << SCU_SFSPD_10_ZIF_Pos) /*!< SCU SFSPD_10: ZIF Mask */ + +/* -------------------------------- SCU_SFSPD_11 -------------------------------- */ +#define SCU_SFSPD_11_MODE_Pos 0 /*!< SCU SFSPD_11: MODE Position */ +#define SCU_SFSPD_11_MODE_Msk (0x07UL << SCU_SFSPD_11_MODE_Pos) /*!< SCU SFSPD_11: MODE Mask */ +#define SCU_SFSPD_11_EPD_Pos 3 /*!< SCU SFSPD_11: EPD Position */ +#define SCU_SFSPD_11_EPD_Msk (0x01UL << SCU_SFSPD_11_EPD_Pos) /*!< SCU SFSPD_11: EPD Mask */ +#define SCU_SFSPD_11_EPUN_Pos 4 /*!< SCU SFSPD_11: EPUN Position */ +#define SCU_SFSPD_11_EPUN_Msk (0x01UL << SCU_SFSPD_11_EPUN_Pos) /*!< SCU SFSPD_11: EPUN Mask */ +#define SCU_SFSPD_11_EHS_Pos 5 /*!< SCU SFSPD_11: EHS Position */ +#define SCU_SFSPD_11_EHS_Msk (0x01UL << SCU_SFSPD_11_EHS_Pos) /*!< SCU SFSPD_11: EHS Mask */ +#define SCU_SFSPD_11_EZI_Pos 6 /*!< SCU SFSPD_11: EZI Position */ +#define SCU_SFSPD_11_EZI_Msk (0x01UL << SCU_SFSPD_11_EZI_Pos) /*!< SCU SFSPD_11: EZI Mask */ +#define SCU_SFSPD_11_ZIF_Pos 7 /*!< SCU SFSPD_11: ZIF Position */ +#define SCU_SFSPD_11_ZIF_Msk (0x01UL << SCU_SFSPD_11_ZIF_Pos) /*!< SCU SFSPD_11: ZIF Mask */ + +/* -------------------------------- SCU_SFSPD_12 -------------------------------- */ +#define SCU_SFSPD_12_MODE_Pos 0 /*!< SCU SFSPD_12: MODE Position */ +#define SCU_SFSPD_12_MODE_Msk (0x07UL << SCU_SFSPD_12_MODE_Pos) /*!< SCU SFSPD_12: MODE Mask */ +#define SCU_SFSPD_12_EPD_Pos 3 /*!< SCU SFSPD_12: EPD Position */ +#define SCU_SFSPD_12_EPD_Msk (0x01UL << SCU_SFSPD_12_EPD_Pos) /*!< SCU SFSPD_12: EPD Mask */ +#define SCU_SFSPD_12_EPUN_Pos 4 /*!< SCU SFSPD_12: EPUN Position */ +#define SCU_SFSPD_12_EPUN_Msk (0x01UL << SCU_SFSPD_12_EPUN_Pos) /*!< SCU SFSPD_12: EPUN Mask */ +#define SCU_SFSPD_12_EHS_Pos 5 /*!< SCU SFSPD_12: EHS Position */ +#define SCU_SFSPD_12_EHS_Msk (0x01UL << SCU_SFSPD_12_EHS_Pos) /*!< SCU SFSPD_12: EHS Mask */ +#define SCU_SFSPD_12_EZI_Pos 6 /*!< SCU SFSPD_12: EZI Position */ +#define SCU_SFSPD_12_EZI_Msk (0x01UL << SCU_SFSPD_12_EZI_Pos) /*!< SCU SFSPD_12: EZI Mask */ +#define SCU_SFSPD_12_ZIF_Pos 7 /*!< SCU SFSPD_12: ZIF Position */ +#define SCU_SFSPD_12_ZIF_Msk (0x01UL << SCU_SFSPD_12_ZIF_Pos) /*!< SCU SFSPD_12: ZIF Mask */ + +/* -------------------------------- SCU_SFSPD_13 -------------------------------- */ +#define SCU_SFSPD_13_MODE_Pos 0 /*!< SCU SFSPD_13: MODE Position */ +#define SCU_SFSPD_13_MODE_Msk (0x07UL << SCU_SFSPD_13_MODE_Pos) /*!< SCU SFSPD_13: MODE Mask */ +#define SCU_SFSPD_13_EPD_Pos 3 /*!< SCU SFSPD_13: EPD Position */ +#define SCU_SFSPD_13_EPD_Msk (0x01UL << SCU_SFSPD_13_EPD_Pos) /*!< SCU SFSPD_13: EPD Mask */ +#define SCU_SFSPD_13_EPUN_Pos 4 /*!< SCU SFSPD_13: EPUN Position */ +#define SCU_SFSPD_13_EPUN_Msk (0x01UL << SCU_SFSPD_13_EPUN_Pos) /*!< SCU SFSPD_13: EPUN Mask */ +#define SCU_SFSPD_13_EHS_Pos 5 /*!< SCU SFSPD_13: EHS Position */ +#define SCU_SFSPD_13_EHS_Msk (0x01UL << SCU_SFSPD_13_EHS_Pos) /*!< SCU SFSPD_13: EHS Mask */ +#define SCU_SFSPD_13_EZI_Pos 6 /*!< SCU SFSPD_13: EZI Position */ +#define SCU_SFSPD_13_EZI_Msk (0x01UL << SCU_SFSPD_13_EZI_Pos) /*!< SCU SFSPD_13: EZI Mask */ +#define SCU_SFSPD_13_ZIF_Pos 7 /*!< SCU SFSPD_13: ZIF Position */ +#define SCU_SFSPD_13_ZIF_Msk (0x01UL << SCU_SFSPD_13_ZIF_Pos) /*!< SCU SFSPD_13: ZIF Mask */ + +/* -------------------------------- SCU_SFSPD_14 -------------------------------- */ +#define SCU_SFSPD_14_MODE_Pos 0 /*!< SCU SFSPD_14: MODE Position */ +#define SCU_SFSPD_14_MODE_Msk (0x07UL << SCU_SFSPD_14_MODE_Pos) /*!< SCU SFSPD_14: MODE Mask */ +#define SCU_SFSPD_14_EPD_Pos 3 /*!< SCU SFSPD_14: EPD Position */ +#define SCU_SFSPD_14_EPD_Msk (0x01UL << SCU_SFSPD_14_EPD_Pos) /*!< SCU SFSPD_14: EPD Mask */ +#define SCU_SFSPD_14_EPUN_Pos 4 /*!< SCU SFSPD_14: EPUN Position */ +#define SCU_SFSPD_14_EPUN_Msk (0x01UL << SCU_SFSPD_14_EPUN_Pos) /*!< SCU SFSPD_14: EPUN Mask */ +#define SCU_SFSPD_14_EHS_Pos 5 /*!< SCU SFSPD_14: EHS Position */ +#define SCU_SFSPD_14_EHS_Msk (0x01UL << SCU_SFSPD_14_EHS_Pos) /*!< SCU SFSPD_14: EHS Mask */ +#define SCU_SFSPD_14_EZI_Pos 6 /*!< SCU SFSPD_14: EZI Position */ +#define SCU_SFSPD_14_EZI_Msk (0x01UL << SCU_SFSPD_14_EZI_Pos) /*!< SCU SFSPD_14: EZI Mask */ +#define SCU_SFSPD_14_ZIF_Pos 7 /*!< SCU SFSPD_14: ZIF Position */ +#define SCU_SFSPD_14_ZIF_Msk (0x01UL << SCU_SFSPD_14_ZIF_Pos) /*!< SCU SFSPD_14: ZIF Mask */ + +/* -------------------------------- SCU_SFSPD_15 -------------------------------- */ +#define SCU_SFSPD_15_MODE_Pos 0 /*!< SCU SFSPD_15: MODE Position */ +#define SCU_SFSPD_15_MODE_Msk (0x07UL << SCU_SFSPD_15_MODE_Pos) /*!< SCU SFSPD_15: MODE Mask */ +#define SCU_SFSPD_15_EPD_Pos 3 /*!< SCU SFSPD_15: EPD Position */ +#define SCU_SFSPD_15_EPD_Msk (0x01UL << SCU_SFSPD_15_EPD_Pos) /*!< SCU SFSPD_15: EPD Mask */ +#define SCU_SFSPD_15_EPUN_Pos 4 /*!< SCU SFSPD_15: EPUN Position */ +#define SCU_SFSPD_15_EPUN_Msk (0x01UL << SCU_SFSPD_15_EPUN_Pos) /*!< SCU SFSPD_15: EPUN Mask */ +#define SCU_SFSPD_15_EHS_Pos 5 /*!< SCU SFSPD_15: EHS Position */ +#define SCU_SFSPD_15_EHS_Msk (0x01UL << SCU_SFSPD_15_EHS_Pos) /*!< SCU SFSPD_15: EHS Mask */ +#define SCU_SFSPD_15_EZI_Pos 6 /*!< SCU SFSPD_15: EZI Position */ +#define SCU_SFSPD_15_EZI_Msk (0x01UL << SCU_SFSPD_15_EZI_Pos) /*!< SCU SFSPD_15: EZI Mask */ +#define SCU_SFSPD_15_ZIF_Pos 7 /*!< SCU SFSPD_15: ZIF Position */ +#define SCU_SFSPD_15_ZIF_Msk (0x01UL << SCU_SFSPD_15_ZIF_Pos) /*!< SCU SFSPD_15: ZIF Mask */ + +/* -------------------------------- SCU_SFSPD_16 -------------------------------- */ +#define SCU_SFSPD_16_MODE_Pos 0 /*!< SCU SFSPD_16: MODE Position */ +#define SCU_SFSPD_16_MODE_Msk (0x07UL << SCU_SFSPD_16_MODE_Pos) /*!< SCU SFSPD_16: MODE Mask */ +#define SCU_SFSPD_16_EPD_Pos 3 /*!< SCU SFSPD_16: EPD Position */ +#define SCU_SFSPD_16_EPD_Msk (0x01UL << SCU_SFSPD_16_EPD_Pos) /*!< SCU SFSPD_16: EPD Mask */ +#define SCU_SFSPD_16_EPUN_Pos 4 /*!< SCU SFSPD_16: EPUN Position */ +#define SCU_SFSPD_16_EPUN_Msk (0x01UL << SCU_SFSPD_16_EPUN_Pos) /*!< SCU SFSPD_16: EPUN Mask */ +#define SCU_SFSPD_16_EHS_Pos 5 /*!< SCU SFSPD_16: EHS Position */ +#define SCU_SFSPD_16_EHS_Msk (0x01UL << SCU_SFSPD_16_EHS_Pos) /*!< SCU SFSPD_16: EHS Mask */ +#define SCU_SFSPD_16_EZI_Pos 6 /*!< SCU SFSPD_16: EZI Position */ +#define SCU_SFSPD_16_EZI_Msk (0x01UL << SCU_SFSPD_16_EZI_Pos) /*!< SCU SFSPD_16: EZI Mask */ +#define SCU_SFSPD_16_ZIF_Pos 7 /*!< SCU SFSPD_16: ZIF Position */ +#define SCU_SFSPD_16_ZIF_Msk (0x01UL << SCU_SFSPD_16_ZIF_Pos) /*!< SCU SFSPD_16: ZIF Mask */ + +/* --------------------------------- SCU_SFSPE_0 -------------------------------- */ +#define SCU_SFSPE_0_MODE_Pos 0 /*!< SCU SFSPE_0: MODE Position */ +#define SCU_SFSPE_0_MODE_Msk (0x07UL << SCU_SFSPE_0_MODE_Pos) /*!< SCU SFSPE_0: MODE Mask */ +#define SCU_SFSPE_0_EPD_Pos 3 /*!< SCU SFSPE_0: EPD Position */ +#define SCU_SFSPE_0_EPD_Msk (0x01UL << SCU_SFSPE_0_EPD_Pos) /*!< SCU SFSPE_0: EPD Mask */ +#define SCU_SFSPE_0_EPUN_Pos 4 /*!< SCU SFSPE_0: EPUN Position */ +#define SCU_SFSPE_0_EPUN_Msk (0x01UL << SCU_SFSPE_0_EPUN_Pos) /*!< SCU SFSPE_0: EPUN Mask */ +#define SCU_SFSPE_0_EHS_Pos 5 /*!< SCU SFSPE_0: EHS Position */ +#define SCU_SFSPE_0_EHS_Msk (0x01UL << SCU_SFSPE_0_EHS_Pos) /*!< SCU SFSPE_0: EHS Mask */ +#define SCU_SFSPE_0_EZI_Pos 6 /*!< SCU SFSPE_0: EZI Position */ +#define SCU_SFSPE_0_EZI_Msk (0x01UL << SCU_SFSPE_0_EZI_Pos) /*!< SCU SFSPE_0: EZI Mask */ +#define SCU_SFSPE_0_ZIF_Pos 7 /*!< SCU SFSPE_0: ZIF Position */ +#define SCU_SFSPE_0_ZIF_Msk (0x01UL << SCU_SFSPE_0_ZIF_Pos) /*!< SCU SFSPE_0: ZIF Mask */ + +/* --------------------------------- SCU_SFSPE_1 -------------------------------- */ +#define SCU_SFSPE_1_MODE_Pos 0 /*!< SCU SFSPE_1: MODE Position */ +#define SCU_SFSPE_1_MODE_Msk (0x07UL << SCU_SFSPE_1_MODE_Pos) /*!< SCU SFSPE_1: MODE Mask */ +#define SCU_SFSPE_1_EPD_Pos 3 /*!< SCU SFSPE_1: EPD Position */ +#define SCU_SFSPE_1_EPD_Msk (0x01UL << SCU_SFSPE_1_EPD_Pos) /*!< SCU SFSPE_1: EPD Mask */ +#define SCU_SFSPE_1_EPUN_Pos 4 /*!< SCU SFSPE_1: EPUN Position */ +#define SCU_SFSPE_1_EPUN_Msk (0x01UL << SCU_SFSPE_1_EPUN_Pos) /*!< SCU SFSPE_1: EPUN Mask */ +#define SCU_SFSPE_1_EHS_Pos 5 /*!< SCU SFSPE_1: EHS Position */ +#define SCU_SFSPE_1_EHS_Msk (0x01UL << SCU_SFSPE_1_EHS_Pos) /*!< SCU SFSPE_1: EHS Mask */ +#define SCU_SFSPE_1_EZI_Pos 6 /*!< SCU SFSPE_1: EZI Position */ +#define SCU_SFSPE_1_EZI_Msk (0x01UL << SCU_SFSPE_1_EZI_Pos) /*!< SCU SFSPE_1: EZI Mask */ +#define SCU_SFSPE_1_ZIF_Pos 7 /*!< SCU SFSPE_1: ZIF Position */ +#define SCU_SFSPE_1_ZIF_Msk (0x01UL << SCU_SFSPE_1_ZIF_Pos) /*!< SCU SFSPE_1: ZIF Mask */ + +/* --------------------------------- SCU_SFSPE_2 -------------------------------- */ +#define SCU_SFSPE_2_MODE_Pos 0 /*!< SCU SFSPE_2: MODE Position */ +#define SCU_SFSPE_2_MODE_Msk (0x07UL << SCU_SFSPE_2_MODE_Pos) /*!< SCU SFSPE_2: MODE Mask */ +#define SCU_SFSPE_2_EPD_Pos 3 /*!< SCU SFSPE_2: EPD Position */ +#define SCU_SFSPE_2_EPD_Msk (0x01UL << SCU_SFSPE_2_EPD_Pos) /*!< SCU SFSPE_2: EPD Mask */ +#define SCU_SFSPE_2_EPUN_Pos 4 /*!< SCU SFSPE_2: EPUN Position */ +#define SCU_SFSPE_2_EPUN_Msk (0x01UL << SCU_SFSPE_2_EPUN_Pos) /*!< SCU SFSPE_2: EPUN Mask */ +#define SCU_SFSPE_2_EHS_Pos 5 /*!< SCU SFSPE_2: EHS Position */ +#define SCU_SFSPE_2_EHS_Msk (0x01UL << SCU_SFSPE_2_EHS_Pos) /*!< SCU SFSPE_2: EHS Mask */ +#define SCU_SFSPE_2_EZI_Pos 6 /*!< SCU SFSPE_2: EZI Position */ +#define SCU_SFSPE_2_EZI_Msk (0x01UL << SCU_SFSPE_2_EZI_Pos) /*!< SCU SFSPE_2: EZI Mask */ +#define SCU_SFSPE_2_ZIF_Pos 7 /*!< SCU SFSPE_2: ZIF Position */ +#define SCU_SFSPE_2_ZIF_Msk (0x01UL << SCU_SFSPE_2_ZIF_Pos) /*!< SCU SFSPE_2: ZIF Mask */ + +/* --------------------------------- SCU_SFSPE_3 -------------------------------- */ +#define SCU_SFSPE_3_MODE_Pos 0 /*!< SCU SFSPE_3: MODE Position */ +#define SCU_SFSPE_3_MODE_Msk (0x07UL << SCU_SFSPE_3_MODE_Pos) /*!< SCU SFSPE_3: MODE Mask */ +#define SCU_SFSPE_3_EPD_Pos 3 /*!< SCU SFSPE_3: EPD Position */ +#define SCU_SFSPE_3_EPD_Msk (0x01UL << SCU_SFSPE_3_EPD_Pos) /*!< SCU SFSPE_3: EPD Mask */ +#define SCU_SFSPE_3_EPUN_Pos 4 /*!< SCU SFSPE_3: EPUN Position */ +#define SCU_SFSPE_3_EPUN_Msk (0x01UL << SCU_SFSPE_3_EPUN_Pos) /*!< SCU SFSPE_3: EPUN Mask */ +#define SCU_SFSPE_3_EHS_Pos 5 /*!< SCU SFSPE_3: EHS Position */ +#define SCU_SFSPE_3_EHS_Msk (0x01UL << SCU_SFSPE_3_EHS_Pos) /*!< SCU SFSPE_3: EHS Mask */ +#define SCU_SFSPE_3_EZI_Pos 6 /*!< SCU SFSPE_3: EZI Position */ +#define SCU_SFSPE_3_EZI_Msk (0x01UL << SCU_SFSPE_3_EZI_Pos) /*!< SCU SFSPE_3: EZI Mask */ +#define SCU_SFSPE_3_ZIF_Pos 7 /*!< SCU SFSPE_3: ZIF Position */ +#define SCU_SFSPE_3_ZIF_Msk (0x01UL << SCU_SFSPE_3_ZIF_Pos) /*!< SCU SFSPE_3: ZIF Mask */ + +/* --------------------------------- SCU_SFSPE_4 -------------------------------- */ +#define SCU_SFSPE_4_MODE_Pos 0 /*!< SCU SFSPE_4: MODE Position */ +#define SCU_SFSPE_4_MODE_Msk (0x07UL << SCU_SFSPE_4_MODE_Pos) /*!< SCU SFSPE_4: MODE Mask */ +#define SCU_SFSPE_4_EPD_Pos 3 /*!< SCU SFSPE_4: EPD Position */ +#define SCU_SFSPE_4_EPD_Msk (0x01UL << SCU_SFSPE_4_EPD_Pos) /*!< SCU SFSPE_4: EPD Mask */ +#define SCU_SFSPE_4_EPUN_Pos 4 /*!< SCU SFSPE_4: EPUN Position */ +#define SCU_SFSPE_4_EPUN_Msk (0x01UL << SCU_SFSPE_4_EPUN_Pos) /*!< SCU SFSPE_4: EPUN Mask */ +#define SCU_SFSPE_4_EHS_Pos 5 /*!< SCU SFSPE_4: EHS Position */ +#define SCU_SFSPE_4_EHS_Msk (0x01UL << SCU_SFSPE_4_EHS_Pos) /*!< SCU SFSPE_4: EHS Mask */ +#define SCU_SFSPE_4_EZI_Pos 6 /*!< SCU SFSPE_4: EZI Position */ +#define SCU_SFSPE_4_EZI_Msk (0x01UL << SCU_SFSPE_4_EZI_Pos) /*!< SCU SFSPE_4: EZI Mask */ +#define SCU_SFSPE_4_ZIF_Pos 7 /*!< SCU SFSPE_4: ZIF Position */ +#define SCU_SFSPE_4_ZIF_Msk (0x01UL << SCU_SFSPE_4_ZIF_Pos) /*!< SCU SFSPE_4: ZIF Mask */ + +/* --------------------------------- SCU_SFSPE_5 -------------------------------- */ +#define SCU_SFSPE_5_MODE_Pos 0 /*!< SCU SFSPE_5: MODE Position */ +#define SCU_SFSPE_5_MODE_Msk (0x07UL << SCU_SFSPE_5_MODE_Pos) /*!< SCU SFSPE_5: MODE Mask */ +#define SCU_SFSPE_5_EPD_Pos 3 /*!< SCU SFSPE_5: EPD Position */ +#define SCU_SFSPE_5_EPD_Msk (0x01UL << SCU_SFSPE_5_EPD_Pos) /*!< SCU SFSPE_5: EPD Mask */ +#define SCU_SFSPE_5_EPUN_Pos 4 /*!< SCU SFSPE_5: EPUN Position */ +#define SCU_SFSPE_5_EPUN_Msk (0x01UL << SCU_SFSPE_5_EPUN_Pos) /*!< SCU SFSPE_5: EPUN Mask */ +#define SCU_SFSPE_5_EHS_Pos 5 /*!< SCU SFSPE_5: EHS Position */ +#define SCU_SFSPE_5_EHS_Msk (0x01UL << SCU_SFSPE_5_EHS_Pos) /*!< SCU SFSPE_5: EHS Mask */ +#define SCU_SFSPE_5_EZI_Pos 6 /*!< SCU SFSPE_5: EZI Position */ +#define SCU_SFSPE_5_EZI_Msk (0x01UL << SCU_SFSPE_5_EZI_Pos) /*!< SCU SFSPE_5: EZI Mask */ +#define SCU_SFSPE_5_ZIF_Pos 7 /*!< SCU SFSPE_5: ZIF Position */ +#define SCU_SFSPE_5_ZIF_Msk (0x01UL << SCU_SFSPE_5_ZIF_Pos) /*!< SCU SFSPE_5: ZIF Mask */ + +/* --------------------------------- SCU_SFSPE_6 -------------------------------- */ +#define SCU_SFSPE_6_MODE_Pos 0 /*!< SCU SFSPE_6: MODE Position */ +#define SCU_SFSPE_6_MODE_Msk (0x07UL << SCU_SFSPE_6_MODE_Pos) /*!< SCU SFSPE_6: MODE Mask */ +#define SCU_SFSPE_6_EPD_Pos 3 /*!< SCU SFSPE_6: EPD Position */ +#define SCU_SFSPE_6_EPD_Msk (0x01UL << SCU_SFSPE_6_EPD_Pos) /*!< SCU SFSPE_6: EPD Mask */ +#define SCU_SFSPE_6_EPUN_Pos 4 /*!< SCU SFSPE_6: EPUN Position */ +#define SCU_SFSPE_6_EPUN_Msk (0x01UL << SCU_SFSPE_6_EPUN_Pos) /*!< SCU SFSPE_6: EPUN Mask */ +#define SCU_SFSPE_6_EHS_Pos 5 /*!< SCU SFSPE_6: EHS Position */ +#define SCU_SFSPE_6_EHS_Msk (0x01UL << SCU_SFSPE_6_EHS_Pos) /*!< SCU SFSPE_6: EHS Mask */ +#define SCU_SFSPE_6_EZI_Pos 6 /*!< SCU SFSPE_6: EZI Position */ +#define SCU_SFSPE_6_EZI_Msk (0x01UL << SCU_SFSPE_6_EZI_Pos) /*!< SCU SFSPE_6: EZI Mask */ +#define SCU_SFSPE_6_ZIF_Pos 7 /*!< SCU SFSPE_6: ZIF Position */ +#define SCU_SFSPE_6_ZIF_Msk (0x01UL << SCU_SFSPE_6_ZIF_Pos) /*!< SCU SFSPE_6: ZIF Mask */ + +/* --------------------------------- SCU_SFSPE_7 -------------------------------- */ +#define SCU_SFSPE_7_MODE_Pos 0 /*!< SCU SFSPE_7: MODE Position */ +#define SCU_SFSPE_7_MODE_Msk (0x07UL << SCU_SFSPE_7_MODE_Pos) /*!< SCU SFSPE_7: MODE Mask */ +#define SCU_SFSPE_7_EPD_Pos 3 /*!< SCU SFSPE_7: EPD Position */ +#define SCU_SFSPE_7_EPD_Msk (0x01UL << SCU_SFSPE_7_EPD_Pos) /*!< SCU SFSPE_7: EPD Mask */ +#define SCU_SFSPE_7_EPUN_Pos 4 /*!< SCU SFSPE_7: EPUN Position */ +#define SCU_SFSPE_7_EPUN_Msk (0x01UL << SCU_SFSPE_7_EPUN_Pos) /*!< SCU SFSPE_7: EPUN Mask */ +#define SCU_SFSPE_7_EHS_Pos 5 /*!< SCU SFSPE_7: EHS Position */ +#define SCU_SFSPE_7_EHS_Msk (0x01UL << SCU_SFSPE_7_EHS_Pos) /*!< SCU SFSPE_7: EHS Mask */ +#define SCU_SFSPE_7_EZI_Pos 6 /*!< SCU SFSPE_7: EZI Position */ +#define SCU_SFSPE_7_EZI_Msk (0x01UL << SCU_SFSPE_7_EZI_Pos) /*!< SCU SFSPE_7: EZI Mask */ +#define SCU_SFSPE_7_ZIF_Pos 7 /*!< SCU SFSPE_7: ZIF Position */ +#define SCU_SFSPE_7_ZIF_Msk (0x01UL << SCU_SFSPE_7_ZIF_Pos) /*!< SCU SFSPE_7: ZIF Mask */ + +/* --------------------------------- SCU_SFSPE_8 -------------------------------- */ +#define SCU_SFSPE_8_MODE_Pos 0 /*!< SCU SFSPE_8: MODE Position */ +#define SCU_SFSPE_8_MODE_Msk (0x07UL << SCU_SFSPE_8_MODE_Pos) /*!< SCU SFSPE_8: MODE Mask */ +#define SCU_SFSPE_8_EPD_Pos 3 /*!< SCU SFSPE_8: EPD Position */ +#define SCU_SFSPE_8_EPD_Msk (0x01UL << SCU_SFSPE_8_EPD_Pos) /*!< SCU SFSPE_8: EPD Mask */ +#define SCU_SFSPE_8_EPUN_Pos 4 /*!< SCU SFSPE_8: EPUN Position */ +#define SCU_SFSPE_8_EPUN_Msk (0x01UL << SCU_SFSPE_8_EPUN_Pos) /*!< SCU SFSPE_8: EPUN Mask */ +#define SCU_SFSPE_8_EHS_Pos 5 /*!< SCU SFSPE_8: EHS Position */ +#define SCU_SFSPE_8_EHS_Msk (0x01UL << SCU_SFSPE_8_EHS_Pos) /*!< SCU SFSPE_8: EHS Mask */ +#define SCU_SFSPE_8_EZI_Pos 6 /*!< SCU SFSPE_8: EZI Position */ +#define SCU_SFSPE_8_EZI_Msk (0x01UL << SCU_SFSPE_8_EZI_Pos) /*!< SCU SFSPE_8: EZI Mask */ +#define SCU_SFSPE_8_ZIF_Pos 7 /*!< SCU SFSPE_8: ZIF Position */ +#define SCU_SFSPE_8_ZIF_Msk (0x01UL << SCU_SFSPE_8_ZIF_Pos) /*!< SCU SFSPE_8: ZIF Mask */ + +/* --------------------------------- SCU_SFSPE_9 -------------------------------- */ +#define SCU_SFSPE_9_MODE_Pos 0 /*!< SCU SFSPE_9: MODE Position */ +#define SCU_SFSPE_9_MODE_Msk (0x07UL << SCU_SFSPE_9_MODE_Pos) /*!< SCU SFSPE_9: MODE Mask */ +#define SCU_SFSPE_9_EPD_Pos 3 /*!< SCU SFSPE_9: EPD Position */ +#define SCU_SFSPE_9_EPD_Msk (0x01UL << SCU_SFSPE_9_EPD_Pos) /*!< SCU SFSPE_9: EPD Mask */ +#define SCU_SFSPE_9_EPUN_Pos 4 /*!< SCU SFSPE_9: EPUN Position */ +#define SCU_SFSPE_9_EPUN_Msk (0x01UL << SCU_SFSPE_9_EPUN_Pos) /*!< SCU SFSPE_9: EPUN Mask */ +#define SCU_SFSPE_9_EHS_Pos 5 /*!< SCU SFSPE_9: EHS Position */ +#define SCU_SFSPE_9_EHS_Msk (0x01UL << SCU_SFSPE_9_EHS_Pos) /*!< SCU SFSPE_9: EHS Mask */ +#define SCU_SFSPE_9_EZI_Pos 6 /*!< SCU SFSPE_9: EZI Position */ +#define SCU_SFSPE_9_EZI_Msk (0x01UL << SCU_SFSPE_9_EZI_Pos) /*!< SCU SFSPE_9: EZI Mask */ +#define SCU_SFSPE_9_ZIF_Pos 7 /*!< SCU SFSPE_9: ZIF Position */ +#define SCU_SFSPE_9_ZIF_Msk (0x01UL << SCU_SFSPE_9_ZIF_Pos) /*!< SCU SFSPE_9: ZIF Mask */ + +/* -------------------------------- SCU_SFSPE_10 -------------------------------- */ +#define SCU_SFSPE_10_MODE_Pos 0 /*!< SCU SFSPE_10: MODE Position */ +#define SCU_SFSPE_10_MODE_Msk (0x07UL << SCU_SFSPE_10_MODE_Pos) /*!< SCU SFSPE_10: MODE Mask */ +#define SCU_SFSPE_10_EPD_Pos 3 /*!< SCU SFSPE_10: EPD Position */ +#define SCU_SFSPE_10_EPD_Msk (0x01UL << SCU_SFSPE_10_EPD_Pos) /*!< SCU SFSPE_10: EPD Mask */ +#define SCU_SFSPE_10_EPUN_Pos 4 /*!< SCU SFSPE_10: EPUN Position */ +#define SCU_SFSPE_10_EPUN_Msk (0x01UL << SCU_SFSPE_10_EPUN_Pos) /*!< SCU SFSPE_10: EPUN Mask */ +#define SCU_SFSPE_10_EHS_Pos 5 /*!< SCU SFSPE_10: EHS Position */ +#define SCU_SFSPE_10_EHS_Msk (0x01UL << SCU_SFSPE_10_EHS_Pos) /*!< SCU SFSPE_10: EHS Mask */ +#define SCU_SFSPE_10_EZI_Pos 6 /*!< SCU SFSPE_10: EZI Position */ +#define SCU_SFSPE_10_EZI_Msk (0x01UL << SCU_SFSPE_10_EZI_Pos) /*!< SCU SFSPE_10: EZI Mask */ +#define SCU_SFSPE_10_ZIF_Pos 7 /*!< SCU SFSPE_10: ZIF Position */ +#define SCU_SFSPE_10_ZIF_Msk (0x01UL << SCU_SFSPE_10_ZIF_Pos) /*!< SCU SFSPE_10: ZIF Mask */ + +/* -------------------------------- SCU_SFSPE_11 -------------------------------- */ +#define SCU_SFSPE_11_MODE_Pos 0 /*!< SCU SFSPE_11: MODE Position */ +#define SCU_SFSPE_11_MODE_Msk (0x07UL << SCU_SFSPE_11_MODE_Pos) /*!< SCU SFSPE_11: MODE Mask */ +#define SCU_SFSPE_11_EPD_Pos 3 /*!< SCU SFSPE_11: EPD Position */ +#define SCU_SFSPE_11_EPD_Msk (0x01UL << SCU_SFSPE_11_EPD_Pos) /*!< SCU SFSPE_11: EPD Mask */ +#define SCU_SFSPE_11_EPUN_Pos 4 /*!< SCU SFSPE_11: EPUN Position */ +#define SCU_SFSPE_11_EPUN_Msk (0x01UL << SCU_SFSPE_11_EPUN_Pos) /*!< SCU SFSPE_11: EPUN Mask */ +#define SCU_SFSPE_11_EHS_Pos 5 /*!< SCU SFSPE_11: EHS Position */ +#define SCU_SFSPE_11_EHS_Msk (0x01UL << SCU_SFSPE_11_EHS_Pos) /*!< SCU SFSPE_11: EHS Mask */ +#define SCU_SFSPE_11_EZI_Pos 6 /*!< SCU SFSPE_11: EZI Position */ +#define SCU_SFSPE_11_EZI_Msk (0x01UL << SCU_SFSPE_11_EZI_Pos) /*!< SCU SFSPE_11: EZI Mask */ +#define SCU_SFSPE_11_ZIF_Pos 7 /*!< SCU SFSPE_11: ZIF Position */ +#define SCU_SFSPE_11_ZIF_Msk (0x01UL << SCU_SFSPE_11_ZIF_Pos) /*!< SCU SFSPE_11: ZIF Mask */ + +/* -------------------------------- SCU_SFSPE_12 -------------------------------- */ +#define SCU_SFSPE_12_MODE_Pos 0 /*!< SCU SFSPE_12: MODE Position */ +#define SCU_SFSPE_12_MODE_Msk (0x07UL << SCU_SFSPE_12_MODE_Pos) /*!< SCU SFSPE_12: MODE Mask */ +#define SCU_SFSPE_12_EPD_Pos 3 /*!< SCU SFSPE_12: EPD Position */ +#define SCU_SFSPE_12_EPD_Msk (0x01UL << SCU_SFSPE_12_EPD_Pos) /*!< SCU SFSPE_12: EPD Mask */ +#define SCU_SFSPE_12_EPUN_Pos 4 /*!< SCU SFSPE_12: EPUN Position */ +#define SCU_SFSPE_12_EPUN_Msk (0x01UL << SCU_SFSPE_12_EPUN_Pos) /*!< SCU SFSPE_12: EPUN Mask */ +#define SCU_SFSPE_12_EHS_Pos 5 /*!< SCU SFSPE_12: EHS Position */ +#define SCU_SFSPE_12_EHS_Msk (0x01UL << SCU_SFSPE_12_EHS_Pos) /*!< SCU SFSPE_12: EHS Mask */ +#define SCU_SFSPE_12_EZI_Pos 6 /*!< SCU SFSPE_12: EZI Position */ +#define SCU_SFSPE_12_EZI_Msk (0x01UL << SCU_SFSPE_12_EZI_Pos) /*!< SCU SFSPE_12: EZI Mask */ +#define SCU_SFSPE_12_ZIF_Pos 7 /*!< SCU SFSPE_12: ZIF Position */ +#define SCU_SFSPE_12_ZIF_Msk (0x01UL << SCU_SFSPE_12_ZIF_Pos) /*!< SCU SFSPE_12: ZIF Mask */ + +/* -------------------------------- SCU_SFSPE_13 -------------------------------- */ +#define SCU_SFSPE_13_MODE_Pos 0 /*!< SCU SFSPE_13: MODE Position */ +#define SCU_SFSPE_13_MODE_Msk (0x07UL << SCU_SFSPE_13_MODE_Pos) /*!< SCU SFSPE_13: MODE Mask */ +#define SCU_SFSPE_13_EPD_Pos 3 /*!< SCU SFSPE_13: EPD Position */ +#define SCU_SFSPE_13_EPD_Msk (0x01UL << SCU_SFSPE_13_EPD_Pos) /*!< SCU SFSPE_13: EPD Mask */ +#define SCU_SFSPE_13_EPUN_Pos 4 /*!< SCU SFSPE_13: EPUN Position */ +#define SCU_SFSPE_13_EPUN_Msk (0x01UL << SCU_SFSPE_13_EPUN_Pos) /*!< SCU SFSPE_13: EPUN Mask */ +#define SCU_SFSPE_13_EHS_Pos 5 /*!< SCU SFSPE_13: EHS Position */ +#define SCU_SFSPE_13_EHS_Msk (0x01UL << SCU_SFSPE_13_EHS_Pos) /*!< SCU SFSPE_13: EHS Mask */ +#define SCU_SFSPE_13_EZI_Pos 6 /*!< SCU SFSPE_13: EZI Position */ +#define SCU_SFSPE_13_EZI_Msk (0x01UL << SCU_SFSPE_13_EZI_Pos) /*!< SCU SFSPE_13: EZI Mask */ +#define SCU_SFSPE_13_ZIF_Pos 7 /*!< SCU SFSPE_13: ZIF Position */ +#define SCU_SFSPE_13_ZIF_Msk (0x01UL << SCU_SFSPE_13_ZIF_Pos) /*!< SCU SFSPE_13: ZIF Mask */ + +/* -------------------------------- SCU_SFSPE_14 -------------------------------- */ +#define SCU_SFSPE_14_MODE_Pos 0 /*!< SCU SFSPE_14: MODE Position */ +#define SCU_SFSPE_14_MODE_Msk (0x07UL << SCU_SFSPE_14_MODE_Pos) /*!< SCU SFSPE_14: MODE Mask */ +#define SCU_SFSPE_14_EPD_Pos 3 /*!< SCU SFSPE_14: EPD Position */ +#define SCU_SFSPE_14_EPD_Msk (0x01UL << SCU_SFSPE_14_EPD_Pos) /*!< SCU SFSPE_14: EPD Mask */ +#define SCU_SFSPE_14_EPUN_Pos 4 /*!< SCU SFSPE_14: EPUN Position */ +#define SCU_SFSPE_14_EPUN_Msk (0x01UL << SCU_SFSPE_14_EPUN_Pos) /*!< SCU SFSPE_14: EPUN Mask */ +#define SCU_SFSPE_14_EHS_Pos 5 /*!< SCU SFSPE_14: EHS Position */ +#define SCU_SFSPE_14_EHS_Msk (0x01UL << SCU_SFSPE_14_EHS_Pos) /*!< SCU SFSPE_14: EHS Mask */ +#define SCU_SFSPE_14_EZI_Pos 6 /*!< SCU SFSPE_14: EZI Position */ +#define SCU_SFSPE_14_EZI_Msk (0x01UL << SCU_SFSPE_14_EZI_Pos) /*!< SCU SFSPE_14: EZI Mask */ +#define SCU_SFSPE_14_ZIF_Pos 7 /*!< SCU SFSPE_14: ZIF Position */ +#define SCU_SFSPE_14_ZIF_Msk (0x01UL << SCU_SFSPE_14_ZIF_Pos) /*!< SCU SFSPE_14: ZIF Mask */ + +/* -------------------------------- SCU_SFSPE_15 -------------------------------- */ +#define SCU_SFSPE_15_MODE_Pos 0 /*!< SCU SFSPE_15: MODE Position */ +#define SCU_SFSPE_15_MODE_Msk (0x07UL << SCU_SFSPE_15_MODE_Pos) /*!< SCU SFSPE_15: MODE Mask */ +#define SCU_SFSPE_15_EPD_Pos 3 /*!< SCU SFSPE_15: EPD Position */ +#define SCU_SFSPE_15_EPD_Msk (0x01UL << SCU_SFSPE_15_EPD_Pos) /*!< SCU SFSPE_15: EPD Mask */ +#define SCU_SFSPE_15_EPUN_Pos 4 /*!< SCU SFSPE_15: EPUN Position */ +#define SCU_SFSPE_15_EPUN_Msk (0x01UL << SCU_SFSPE_15_EPUN_Pos) /*!< SCU SFSPE_15: EPUN Mask */ +#define SCU_SFSPE_15_EHS_Pos 5 /*!< SCU SFSPE_15: EHS Position */ +#define SCU_SFSPE_15_EHS_Msk (0x01UL << SCU_SFSPE_15_EHS_Pos) /*!< SCU SFSPE_15: EHS Mask */ +#define SCU_SFSPE_15_EZI_Pos 6 /*!< SCU SFSPE_15: EZI Position */ +#define SCU_SFSPE_15_EZI_Msk (0x01UL << SCU_SFSPE_15_EZI_Pos) /*!< SCU SFSPE_15: EZI Mask */ +#define SCU_SFSPE_15_ZIF_Pos 7 /*!< SCU SFSPE_15: ZIF Position */ +#define SCU_SFSPE_15_ZIF_Msk (0x01UL << SCU_SFSPE_15_ZIF_Pos) /*!< SCU SFSPE_15: ZIF Mask */ + +/* --------------------------------- SCU_SFSPF_0 -------------------------------- */ +#define SCU_SFSPF_0_MODE_Pos 0 /*!< SCU SFSPF_0: MODE Position */ +#define SCU_SFSPF_0_MODE_Msk (0x07UL << SCU_SFSPF_0_MODE_Pos) /*!< SCU SFSPF_0: MODE Mask */ +#define SCU_SFSPF_0_EPD_Pos 3 /*!< SCU SFSPF_0: EPD Position */ +#define SCU_SFSPF_0_EPD_Msk (0x01UL << SCU_SFSPF_0_EPD_Pos) /*!< SCU SFSPF_0: EPD Mask */ +#define SCU_SFSPF_0_EPUN_Pos 4 /*!< SCU SFSPF_0: EPUN Position */ +#define SCU_SFSPF_0_EPUN_Msk (0x01UL << SCU_SFSPF_0_EPUN_Pos) /*!< SCU SFSPF_0: EPUN Mask */ +#define SCU_SFSPF_0_EHS_Pos 5 /*!< SCU SFSPF_0: EHS Position */ +#define SCU_SFSPF_0_EHS_Msk (0x01UL << SCU_SFSPF_0_EHS_Pos) /*!< SCU SFSPF_0: EHS Mask */ +#define SCU_SFSPF_0_EZI_Pos 6 /*!< SCU SFSPF_0: EZI Position */ +#define SCU_SFSPF_0_EZI_Msk (0x01UL << SCU_SFSPF_0_EZI_Pos) /*!< SCU SFSPF_0: EZI Mask */ +#define SCU_SFSPF_0_ZIF_Pos 7 /*!< SCU SFSPF_0: ZIF Position */ +#define SCU_SFSPF_0_ZIF_Msk (0x01UL << SCU_SFSPF_0_ZIF_Pos) /*!< SCU SFSPF_0: ZIF Mask */ + +/* --------------------------------- SCU_SFSPF_1 -------------------------------- */ +#define SCU_SFSPF_1_MODE_Pos 0 /*!< SCU SFSPF_1: MODE Position */ +#define SCU_SFSPF_1_MODE_Msk (0x07UL << SCU_SFSPF_1_MODE_Pos) /*!< SCU SFSPF_1: MODE Mask */ +#define SCU_SFSPF_1_EPD_Pos 3 /*!< SCU SFSPF_1: EPD Position */ +#define SCU_SFSPF_1_EPD_Msk (0x01UL << SCU_SFSPF_1_EPD_Pos) /*!< SCU SFSPF_1: EPD Mask */ +#define SCU_SFSPF_1_EPUN_Pos 4 /*!< SCU SFSPF_1: EPUN Position */ +#define SCU_SFSPF_1_EPUN_Msk (0x01UL << SCU_SFSPF_1_EPUN_Pos) /*!< SCU SFSPF_1: EPUN Mask */ +#define SCU_SFSPF_1_EHS_Pos 5 /*!< SCU SFSPF_1: EHS Position */ +#define SCU_SFSPF_1_EHS_Msk (0x01UL << SCU_SFSPF_1_EHS_Pos) /*!< SCU SFSPF_1: EHS Mask */ +#define SCU_SFSPF_1_EZI_Pos 6 /*!< SCU SFSPF_1: EZI Position */ +#define SCU_SFSPF_1_EZI_Msk (0x01UL << SCU_SFSPF_1_EZI_Pos) /*!< SCU SFSPF_1: EZI Mask */ +#define SCU_SFSPF_1_ZIF_Pos 7 /*!< SCU SFSPF_1: ZIF Position */ +#define SCU_SFSPF_1_ZIF_Msk (0x01UL << SCU_SFSPF_1_ZIF_Pos) /*!< SCU SFSPF_1: ZIF Mask */ + +/* --------------------------------- SCU_SFSPF_2 -------------------------------- */ +#define SCU_SFSPF_2_MODE_Pos 0 /*!< SCU SFSPF_2: MODE Position */ +#define SCU_SFSPF_2_MODE_Msk (0x07UL << SCU_SFSPF_2_MODE_Pos) /*!< SCU SFSPF_2: MODE Mask */ +#define SCU_SFSPF_2_EPD_Pos 3 /*!< SCU SFSPF_2: EPD Position */ +#define SCU_SFSPF_2_EPD_Msk (0x01UL << SCU_SFSPF_2_EPD_Pos) /*!< SCU SFSPF_2: EPD Mask */ +#define SCU_SFSPF_2_EPUN_Pos 4 /*!< SCU SFSPF_2: EPUN Position */ +#define SCU_SFSPF_2_EPUN_Msk (0x01UL << SCU_SFSPF_2_EPUN_Pos) /*!< SCU SFSPF_2: EPUN Mask */ +#define SCU_SFSPF_2_EHS_Pos 5 /*!< SCU SFSPF_2: EHS Position */ +#define SCU_SFSPF_2_EHS_Msk (0x01UL << SCU_SFSPF_2_EHS_Pos) /*!< SCU SFSPF_2: EHS Mask */ +#define SCU_SFSPF_2_EZI_Pos 6 /*!< SCU SFSPF_2: EZI Position */ +#define SCU_SFSPF_2_EZI_Msk (0x01UL << SCU_SFSPF_2_EZI_Pos) /*!< SCU SFSPF_2: EZI Mask */ +#define SCU_SFSPF_2_ZIF_Pos 7 /*!< SCU SFSPF_2: ZIF Position */ +#define SCU_SFSPF_2_ZIF_Msk (0x01UL << SCU_SFSPF_2_ZIF_Pos) /*!< SCU SFSPF_2: ZIF Mask */ + +/* --------------------------------- SCU_SFSPF_3 -------------------------------- */ +#define SCU_SFSPF_3_MODE_Pos 0 /*!< SCU SFSPF_3: MODE Position */ +#define SCU_SFSPF_3_MODE_Msk (0x07UL << SCU_SFSPF_3_MODE_Pos) /*!< SCU SFSPF_3: MODE Mask */ +#define SCU_SFSPF_3_EPD_Pos 3 /*!< SCU SFSPF_3: EPD Position */ +#define SCU_SFSPF_3_EPD_Msk (0x01UL << SCU_SFSPF_3_EPD_Pos) /*!< SCU SFSPF_3: EPD Mask */ +#define SCU_SFSPF_3_EPUN_Pos 4 /*!< SCU SFSPF_3: EPUN Position */ +#define SCU_SFSPF_3_EPUN_Msk (0x01UL << SCU_SFSPF_3_EPUN_Pos) /*!< SCU SFSPF_3: EPUN Mask */ +#define SCU_SFSPF_3_EHS_Pos 5 /*!< SCU SFSPF_3: EHS Position */ +#define SCU_SFSPF_3_EHS_Msk (0x01UL << SCU_SFSPF_3_EHS_Pos) /*!< SCU SFSPF_3: EHS Mask */ +#define SCU_SFSPF_3_EZI_Pos 6 /*!< SCU SFSPF_3: EZI Position */ +#define SCU_SFSPF_3_EZI_Msk (0x01UL << SCU_SFSPF_3_EZI_Pos) /*!< SCU SFSPF_3: EZI Mask */ +#define SCU_SFSPF_3_ZIF_Pos 7 /*!< SCU SFSPF_3: ZIF Position */ +#define SCU_SFSPF_3_ZIF_Msk (0x01UL << SCU_SFSPF_3_ZIF_Pos) /*!< SCU SFSPF_3: ZIF Mask */ + +/* --------------------------------- SCU_SFSPF_4 -------------------------------- */ +#define SCU_SFSPF_4_MODE_Pos 0 /*!< SCU SFSPF_4: MODE Position */ +#define SCU_SFSPF_4_MODE_Msk (0x07UL << SCU_SFSPF_4_MODE_Pos) /*!< SCU SFSPF_4: MODE Mask */ +#define SCU_SFSPF_4_EPD_Pos 3 /*!< SCU SFSPF_4: EPD Position */ +#define SCU_SFSPF_4_EPD_Msk (0x01UL << SCU_SFSPF_4_EPD_Pos) /*!< SCU SFSPF_4: EPD Mask */ +#define SCU_SFSPF_4_EPUN_Pos 4 /*!< SCU SFSPF_4: EPUN Position */ +#define SCU_SFSPF_4_EPUN_Msk (0x01UL << SCU_SFSPF_4_EPUN_Pos) /*!< SCU SFSPF_4: EPUN Mask */ +#define SCU_SFSPF_4_EHS_Pos 5 /*!< SCU SFSPF_4: EHS Position */ +#define SCU_SFSPF_4_EHS_Msk (0x01UL << SCU_SFSPF_4_EHS_Pos) /*!< SCU SFSPF_4: EHS Mask */ +#define SCU_SFSPF_4_EZI_Pos 6 /*!< SCU SFSPF_4: EZI Position */ +#define SCU_SFSPF_4_EZI_Msk (0x01UL << SCU_SFSPF_4_EZI_Pos) /*!< SCU SFSPF_4: EZI Mask */ +#define SCU_SFSPF_4_ZIF_Pos 7 /*!< SCU SFSPF_4: ZIF Position */ +#define SCU_SFSPF_4_ZIF_Msk (0x01UL << SCU_SFSPF_4_ZIF_Pos) /*!< SCU SFSPF_4: ZIF Mask */ + +/* --------------------------------- SCU_SFSPF_5 -------------------------------- */ +#define SCU_SFSPF_5_MODE_Pos 0 /*!< SCU SFSPF_5: MODE Position */ +#define SCU_SFSPF_5_MODE_Msk (0x07UL << SCU_SFSPF_5_MODE_Pos) /*!< SCU SFSPF_5: MODE Mask */ +#define SCU_SFSPF_5_EPD_Pos 3 /*!< SCU SFSPF_5: EPD Position */ +#define SCU_SFSPF_5_EPD_Msk (0x01UL << SCU_SFSPF_5_EPD_Pos) /*!< SCU SFSPF_5: EPD Mask */ +#define SCU_SFSPF_5_EPUN_Pos 4 /*!< SCU SFSPF_5: EPUN Position */ +#define SCU_SFSPF_5_EPUN_Msk (0x01UL << SCU_SFSPF_5_EPUN_Pos) /*!< SCU SFSPF_5: EPUN Mask */ +#define SCU_SFSPF_5_EHS_Pos 5 /*!< SCU SFSPF_5: EHS Position */ +#define SCU_SFSPF_5_EHS_Msk (0x01UL << SCU_SFSPF_5_EHS_Pos) /*!< SCU SFSPF_5: EHS Mask */ +#define SCU_SFSPF_5_EZI_Pos 6 /*!< SCU SFSPF_5: EZI Position */ +#define SCU_SFSPF_5_EZI_Msk (0x01UL << SCU_SFSPF_5_EZI_Pos) /*!< SCU SFSPF_5: EZI Mask */ +#define SCU_SFSPF_5_ZIF_Pos 7 /*!< SCU SFSPF_5: ZIF Position */ +#define SCU_SFSPF_5_ZIF_Msk (0x01UL << SCU_SFSPF_5_ZIF_Pos) /*!< SCU SFSPF_5: ZIF Mask */ + +/* --------------------------------- SCU_SFSPF_6 -------------------------------- */ +#define SCU_SFSPF_6_MODE_Pos 0 /*!< SCU SFSPF_6: MODE Position */ +#define SCU_SFSPF_6_MODE_Msk (0x07UL << SCU_SFSPF_6_MODE_Pos) /*!< SCU SFSPF_6: MODE Mask */ +#define SCU_SFSPF_6_EPD_Pos 3 /*!< SCU SFSPF_6: EPD Position */ +#define SCU_SFSPF_6_EPD_Msk (0x01UL << SCU_SFSPF_6_EPD_Pos) /*!< SCU SFSPF_6: EPD Mask */ +#define SCU_SFSPF_6_EPUN_Pos 4 /*!< SCU SFSPF_6: EPUN Position */ +#define SCU_SFSPF_6_EPUN_Msk (0x01UL << SCU_SFSPF_6_EPUN_Pos) /*!< SCU SFSPF_6: EPUN Mask */ +#define SCU_SFSPF_6_EHS_Pos 5 /*!< SCU SFSPF_6: EHS Position */ +#define SCU_SFSPF_6_EHS_Msk (0x01UL << SCU_SFSPF_6_EHS_Pos) /*!< SCU SFSPF_6: EHS Mask */ +#define SCU_SFSPF_6_EZI_Pos 6 /*!< SCU SFSPF_6: EZI Position */ +#define SCU_SFSPF_6_EZI_Msk (0x01UL << SCU_SFSPF_6_EZI_Pos) /*!< SCU SFSPF_6: EZI Mask */ +#define SCU_SFSPF_6_ZIF_Pos 7 /*!< SCU SFSPF_6: ZIF Position */ +#define SCU_SFSPF_6_ZIF_Msk (0x01UL << SCU_SFSPF_6_ZIF_Pos) /*!< SCU SFSPF_6: ZIF Mask */ + +/* --------------------------------- SCU_SFSPF_7 -------------------------------- */ +#define SCU_SFSPF_7_MODE_Pos 0 /*!< SCU SFSPF_7: MODE Position */ +#define SCU_SFSPF_7_MODE_Msk (0x07UL << SCU_SFSPF_7_MODE_Pos) /*!< SCU SFSPF_7: MODE Mask */ +#define SCU_SFSPF_7_EPD_Pos 3 /*!< SCU SFSPF_7: EPD Position */ +#define SCU_SFSPF_7_EPD_Msk (0x01UL << SCU_SFSPF_7_EPD_Pos) /*!< SCU SFSPF_7: EPD Mask */ +#define SCU_SFSPF_7_EPUN_Pos 4 /*!< SCU SFSPF_7: EPUN Position */ +#define SCU_SFSPF_7_EPUN_Msk (0x01UL << SCU_SFSPF_7_EPUN_Pos) /*!< SCU SFSPF_7: EPUN Mask */ +#define SCU_SFSPF_7_EHS_Pos 5 /*!< SCU SFSPF_7: EHS Position */ +#define SCU_SFSPF_7_EHS_Msk (0x01UL << SCU_SFSPF_7_EHS_Pos) /*!< SCU SFSPF_7: EHS Mask */ +#define SCU_SFSPF_7_EZI_Pos 6 /*!< SCU SFSPF_7: EZI Position */ +#define SCU_SFSPF_7_EZI_Msk (0x01UL << SCU_SFSPF_7_EZI_Pos) /*!< SCU SFSPF_7: EZI Mask */ +#define SCU_SFSPF_7_ZIF_Pos 7 /*!< SCU SFSPF_7: ZIF Position */ +#define SCU_SFSPF_7_ZIF_Msk (0x01UL << SCU_SFSPF_7_ZIF_Pos) /*!< SCU SFSPF_7: ZIF Mask */ + +/* --------------------------------- SCU_SFSPF_8 -------------------------------- */ +#define SCU_SFSPF_8_MODE_Pos 0 /*!< SCU SFSPF_8: MODE Position */ +#define SCU_SFSPF_8_MODE_Msk (0x07UL << SCU_SFSPF_8_MODE_Pos) /*!< SCU SFSPF_8: MODE Mask */ +#define SCU_SFSPF_8_EPD_Pos 3 /*!< SCU SFSPF_8: EPD Position */ +#define SCU_SFSPF_8_EPD_Msk (0x01UL << SCU_SFSPF_8_EPD_Pos) /*!< SCU SFSPF_8: EPD Mask */ +#define SCU_SFSPF_8_EPUN_Pos 4 /*!< SCU SFSPF_8: EPUN Position */ +#define SCU_SFSPF_8_EPUN_Msk (0x01UL << SCU_SFSPF_8_EPUN_Pos) /*!< SCU SFSPF_8: EPUN Mask */ +#define SCU_SFSPF_8_EHS_Pos 5 /*!< SCU SFSPF_8: EHS Position */ +#define SCU_SFSPF_8_EHS_Msk (0x01UL << SCU_SFSPF_8_EHS_Pos) /*!< SCU SFSPF_8: EHS Mask */ +#define SCU_SFSPF_8_EZI_Pos 6 /*!< SCU SFSPF_8: EZI Position */ +#define SCU_SFSPF_8_EZI_Msk (0x01UL << SCU_SFSPF_8_EZI_Pos) /*!< SCU SFSPF_8: EZI Mask */ +#define SCU_SFSPF_8_ZIF_Pos 7 /*!< SCU SFSPF_8: ZIF Position */ +#define SCU_SFSPF_8_ZIF_Msk (0x01UL << SCU_SFSPF_8_ZIF_Pos) /*!< SCU SFSPF_8: ZIF Mask */ + +/* --------------------------------- SCU_SFSPF_9 -------------------------------- */ +#define SCU_SFSPF_9_MODE_Pos 0 /*!< SCU SFSPF_9: MODE Position */ +#define SCU_SFSPF_9_MODE_Msk (0x07UL << SCU_SFSPF_9_MODE_Pos) /*!< SCU SFSPF_9: MODE Mask */ +#define SCU_SFSPF_9_EPD_Pos 3 /*!< SCU SFSPF_9: EPD Position */ +#define SCU_SFSPF_9_EPD_Msk (0x01UL << SCU_SFSPF_9_EPD_Pos) /*!< SCU SFSPF_9: EPD Mask */ +#define SCU_SFSPF_9_EPUN_Pos 4 /*!< SCU SFSPF_9: EPUN Position */ +#define SCU_SFSPF_9_EPUN_Msk (0x01UL << SCU_SFSPF_9_EPUN_Pos) /*!< SCU SFSPF_9: EPUN Mask */ +#define SCU_SFSPF_9_EHS_Pos 5 /*!< SCU SFSPF_9: EHS Position */ +#define SCU_SFSPF_9_EHS_Msk (0x01UL << SCU_SFSPF_9_EHS_Pos) /*!< SCU SFSPF_9: EHS Mask */ +#define SCU_SFSPF_9_EZI_Pos 6 /*!< SCU SFSPF_9: EZI Position */ +#define SCU_SFSPF_9_EZI_Msk (0x01UL << SCU_SFSPF_9_EZI_Pos) /*!< SCU SFSPF_9: EZI Mask */ +#define SCU_SFSPF_9_ZIF_Pos 7 /*!< SCU SFSPF_9: ZIF Position */ +#define SCU_SFSPF_9_ZIF_Msk (0x01UL << SCU_SFSPF_9_ZIF_Pos) /*!< SCU SFSPF_9: ZIF Mask */ + +/* -------------------------------- SCU_SFSPF_10 -------------------------------- */ +#define SCU_SFSPF_10_MODE_Pos 0 /*!< SCU SFSPF_10: MODE Position */ +#define SCU_SFSPF_10_MODE_Msk (0x07UL << SCU_SFSPF_10_MODE_Pos) /*!< SCU SFSPF_10: MODE Mask */ +#define SCU_SFSPF_10_EPD_Pos 3 /*!< SCU SFSPF_10: EPD Position */ +#define SCU_SFSPF_10_EPD_Msk (0x01UL << SCU_SFSPF_10_EPD_Pos) /*!< SCU SFSPF_10: EPD Mask */ +#define SCU_SFSPF_10_EPUN_Pos 4 /*!< SCU SFSPF_10: EPUN Position */ +#define SCU_SFSPF_10_EPUN_Msk (0x01UL << SCU_SFSPF_10_EPUN_Pos) /*!< SCU SFSPF_10: EPUN Mask */ +#define SCU_SFSPF_10_EHS_Pos 5 /*!< SCU SFSPF_10: EHS Position */ +#define SCU_SFSPF_10_EHS_Msk (0x01UL << SCU_SFSPF_10_EHS_Pos) /*!< SCU SFSPF_10: EHS Mask */ +#define SCU_SFSPF_10_EZI_Pos 6 /*!< SCU SFSPF_10: EZI Position */ +#define SCU_SFSPF_10_EZI_Msk (0x01UL << SCU_SFSPF_10_EZI_Pos) /*!< SCU SFSPF_10: EZI Mask */ +#define SCU_SFSPF_10_ZIF_Pos 7 /*!< SCU SFSPF_10: ZIF Position */ +#define SCU_SFSPF_10_ZIF_Msk (0x01UL << SCU_SFSPF_10_ZIF_Pos) /*!< SCU SFSPF_10: ZIF Mask */ + +/* -------------------------------- SCU_SFSPF_11 -------------------------------- */ +#define SCU_SFSPF_11_MODE_Pos 0 /*!< SCU SFSPF_11: MODE Position */ +#define SCU_SFSPF_11_MODE_Msk (0x07UL << SCU_SFSPF_11_MODE_Pos) /*!< SCU SFSPF_11: MODE Mask */ +#define SCU_SFSPF_11_EPD_Pos 3 /*!< SCU SFSPF_11: EPD Position */ +#define SCU_SFSPF_11_EPD_Msk (0x01UL << SCU_SFSPF_11_EPD_Pos) /*!< SCU SFSPF_11: EPD Mask */ +#define SCU_SFSPF_11_EPUN_Pos 4 /*!< SCU SFSPF_11: EPUN Position */ +#define SCU_SFSPF_11_EPUN_Msk (0x01UL << SCU_SFSPF_11_EPUN_Pos) /*!< SCU SFSPF_11: EPUN Mask */ +#define SCU_SFSPF_11_EHS_Pos 5 /*!< SCU SFSPF_11: EHS Position */ +#define SCU_SFSPF_11_EHS_Msk (0x01UL << SCU_SFSPF_11_EHS_Pos) /*!< SCU SFSPF_11: EHS Mask */ +#define SCU_SFSPF_11_EZI_Pos 6 /*!< SCU SFSPF_11: EZI Position */ +#define SCU_SFSPF_11_EZI_Msk (0x01UL << SCU_SFSPF_11_EZI_Pos) /*!< SCU SFSPF_11: EZI Mask */ +#define SCU_SFSPF_11_ZIF_Pos 7 /*!< SCU SFSPF_11: ZIF Position */ +#define SCU_SFSPF_11_ZIF_Msk (0x01UL << SCU_SFSPF_11_ZIF_Pos) /*!< SCU SFSPF_11: ZIF Mask */ + +/* -------------------------------- SCU_SFSCLK_0 -------------------------------- */ +#define SCU_SFSCLK_0_MODE_Pos 0 /*!< SCU SFSCLK_0: MODE Position */ +#define SCU_SFSCLK_0_MODE_Msk (0x07UL << SCU_SFSCLK_0_MODE_Pos) /*!< SCU SFSCLK_0: MODE Mask */ +#define SCU_SFSCLK_0_EPD_Pos 3 /*!< SCU SFSCLK_0: EPD Position */ +#define SCU_SFSCLK_0_EPD_Msk (0x01UL << SCU_SFSCLK_0_EPD_Pos) /*!< SCU SFSCLK_0: EPD Mask */ +#define SCU_SFSCLK_0_EPUN_Pos 4 /*!< SCU SFSCLK_0: EPUN Position */ +#define SCU_SFSCLK_0_EPUN_Msk (0x01UL << SCU_SFSCLK_0_EPUN_Pos) /*!< SCU SFSCLK_0: EPUN Mask */ +#define SCU_SFSCLK_0_EHS_Pos 5 /*!< SCU SFSCLK_0: EHS Position */ +#define SCU_SFSCLK_0_EHS_Msk (0x01UL << SCU_SFSCLK_0_EHS_Pos) /*!< SCU SFSCLK_0: EHS Mask */ +#define SCU_SFSCLK_0_EZI_Pos 6 /*!< SCU SFSCLK_0: EZI Position */ +#define SCU_SFSCLK_0_EZI_Msk (0x01UL << SCU_SFSCLK_0_EZI_Pos) /*!< SCU SFSCLK_0: EZI Mask */ +#define SCU_SFSCLK_0_ZIF_Pos 7 /*!< SCU SFSCLK_0: ZIF Position */ +#define SCU_SFSCLK_0_ZIF_Msk (0x01UL << SCU_SFSCLK_0_ZIF_Pos) /*!< SCU SFSCLK_0: ZIF Mask */ + +/* -------------------------------- SCU_SFSCLK_1 -------------------------------- */ +#define SCU_SFSCLK_1_MODE_Pos 0 /*!< SCU SFSCLK_1: MODE Position */ +#define SCU_SFSCLK_1_MODE_Msk (0x07UL << SCU_SFSCLK_1_MODE_Pos) /*!< SCU SFSCLK_1: MODE Mask */ +#define SCU_SFSCLK_1_EPD_Pos 3 /*!< SCU SFSCLK_1: EPD Position */ +#define SCU_SFSCLK_1_EPD_Msk (0x01UL << SCU_SFSCLK_1_EPD_Pos) /*!< SCU SFSCLK_1: EPD Mask */ +#define SCU_SFSCLK_1_EPUN_Pos 4 /*!< SCU SFSCLK_1: EPUN Position */ +#define SCU_SFSCLK_1_EPUN_Msk (0x01UL << SCU_SFSCLK_1_EPUN_Pos) /*!< SCU SFSCLK_1: EPUN Mask */ +#define SCU_SFSCLK_1_EHS_Pos 5 /*!< SCU SFSCLK_1: EHS Position */ +#define SCU_SFSCLK_1_EHS_Msk (0x01UL << SCU_SFSCLK_1_EHS_Pos) /*!< SCU SFSCLK_1: EHS Mask */ +#define SCU_SFSCLK_1_EZI_Pos 6 /*!< SCU SFSCLK_1: EZI Position */ +#define SCU_SFSCLK_1_EZI_Msk (0x01UL << SCU_SFSCLK_1_EZI_Pos) /*!< SCU SFSCLK_1: EZI Mask */ +#define SCU_SFSCLK_1_ZIF_Pos 7 /*!< SCU SFSCLK_1: ZIF Position */ +#define SCU_SFSCLK_1_ZIF_Msk (0x01UL << SCU_SFSCLK_1_ZIF_Pos) /*!< SCU SFSCLK_1: ZIF Mask */ + +/* -------------------------------- SCU_SFSCLK_2 -------------------------------- */ +#define SCU_SFSCLK_2_MODE_Pos 0 /*!< SCU SFSCLK_2: MODE Position */ +#define SCU_SFSCLK_2_MODE_Msk (0x07UL << SCU_SFSCLK_2_MODE_Pos) /*!< SCU SFSCLK_2: MODE Mask */ +#define SCU_SFSCLK_2_EPD_Pos 3 /*!< SCU SFSCLK_2: EPD Position */ +#define SCU_SFSCLK_2_EPD_Msk (0x01UL << SCU_SFSCLK_2_EPD_Pos) /*!< SCU SFSCLK_2: EPD Mask */ +#define SCU_SFSCLK_2_EPUN_Pos 4 /*!< SCU SFSCLK_2: EPUN Position */ +#define SCU_SFSCLK_2_EPUN_Msk (0x01UL << SCU_SFSCLK_2_EPUN_Pos) /*!< SCU SFSCLK_2: EPUN Mask */ +#define SCU_SFSCLK_2_EHS_Pos 5 /*!< SCU SFSCLK_2: EHS Position */ +#define SCU_SFSCLK_2_EHS_Msk (0x01UL << SCU_SFSCLK_2_EHS_Pos) /*!< SCU SFSCLK_2: EHS Mask */ +#define SCU_SFSCLK_2_EZI_Pos 6 /*!< SCU SFSCLK_2: EZI Position */ +#define SCU_SFSCLK_2_EZI_Msk (0x01UL << SCU_SFSCLK_2_EZI_Pos) /*!< SCU SFSCLK_2: EZI Mask */ +#define SCU_SFSCLK_2_ZIF_Pos 7 /*!< SCU SFSCLK_2: ZIF Position */ +#define SCU_SFSCLK_2_ZIF_Msk (0x01UL << SCU_SFSCLK_2_ZIF_Pos) /*!< SCU SFSCLK_2: ZIF Mask */ + +/* -------------------------------- SCU_SFSCLK_3 -------------------------------- */ +#define SCU_SFSCLK_3_MODE_Pos 0 /*!< SCU SFSCLK_3: MODE Position */ +#define SCU_SFSCLK_3_MODE_Msk (0x07UL << SCU_SFSCLK_3_MODE_Pos) /*!< SCU SFSCLK_3: MODE Mask */ +#define SCU_SFSCLK_3_EPD_Pos 3 /*!< SCU SFSCLK_3: EPD Position */ +#define SCU_SFSCLK_3_EPD_Msk (0x01UL << SCU_SFSCLK_3_EPD_Pos) /*!< SCU SFSCLK_3: EPD Mask */ +#define SCU_SFSCLK_3_EPUN_Pos 4 /*!< SCU SFSCLK_3: EPUN Position */ +#define SCU_SFSCLK_3_EPUN_Msk (0x01UL << SCU_SFSCLK_3_EPUN_Pos) /*!< SCU SFSCLK_3: EPUN Mask */ +#define SCU_SFSCLK_3_EHS_Pos 5 /*!< SCU SFSCLK_3: EHS Position */ +#define SCU_SFSCLK_3_EHS_Msk (0x01UL << SCU_SFSCLK_3_EHS_Pos) /*!< SCU SFSCLK_3: EHS Mask */ +#define SCU_SFSCLK_3_EZI_Pos 6 /*!< SCU SFSCLK_3: EZI Position */ +#define SCU_SFSCLK_3_EZI_Msk (0x01UL << SCU_SFSCLK_3_EZI_Pos) /*!< SCU SFSCLK_3: EZI Mask */ +#define SCU_SFSCLK_3_ZIF_Pos 7 /*!< SCU SFSCLK_3: ZIF Position */ +#define SCU_SFSCLK_3_ZIF_Msk (0x01UL << SCU_SFSCLK_3_ZIF_Pos) /*!< SCU SFSCLK_3: ZIF Mask */ + +/* --------------------------------- SCU_SFSUSB --------------------------------- */ +#define SCU_SFSUSB_USB_AIM_Pos 0 /*!< SCU SFSUSB: USB_AIM Position */ +#define SCU_SFSUSB_USB_AIM_Msk (0x01UL << SCU_SFSUSB_USB_AIM_Pos) /*!< SCU SFSUSB: USB_AIM Mask */ +#define SCU_SFSUSB_USB_ESEA_Pos 1 /*!< SCU SFSUSB: USB_ESEA Position */ +#define SCU_SFSUSB_USB_ESEA_Msk (0x01UL << SCU_SFSUSB_USB_ESEA_Pos) /*!< SCU SFSUSB: USB_ESEA Mask */ +#define SCU_SFSUSB_USB_EPD_Pos 2 /*!< SCU SFSUSB: USB_EPD Position */ +#define SCU_SFSUSB_USB_EPD_Msk (0x01UL << SCU_SFSUSB_USB_EPD_Pos) /*!< SCU SFSUSB: USB_EPD Mask */ +#define SCU_SFSUSB_USB_EPWR_Pos 4 /*!< SCU SFSUSB: USB_EPWR Position */ +#define SCU_SFSUSB_USB_EPWR_Msk (0x01UL << SCU_SFSUSB_USB_EPWR_Pos) /*!< SCU SFSUSB: USB_EPWR Mask */ +#define SCU_SFSUSB_USB_VBUS_Pos 5 /*!< SCU SFSUSB: USB_VBUS Position */ +#define SCU_SFSUSB_USB_VBUS_Msk (0x01UL << SCU_SFSUSB_USB_VBUS_Pos) /*!< SCU SFSUSB: USB_VBUS Mask */ + +/* --------------------------------- SCU_SFSI2C0 -------------------------------- */ +#define SCU_SFSI2C0_SCL_EFP_Pos 0 /*!< SCU SFSI2C0: SCL_EFP Position */ +#define SCU_SFSI2C0_SCL_EFP_Msk (0x01UL << SCU_SFSI2C0_SCL_EFP_Pos) /*!< SCU SFSI2C0: SCL_EFP Mask */ +#define SCU_SFSI2C0_SCL_EHD_Pos 2 /*!< SCU SFSI2C0: SCL_EHD Position */ +#define SCU_SFSI2C0_SCL_EHD_Msk (0x01UL << SCU_SFSI2C0_SCL_EHD_Pos) /*!< SCU SFSI2C0: SCL_EHD Mask */ +#define SCU_SFSI2C0_SCL_EZI_Pos 3 /*!< SCU SFSI2C0: SCL_EZI Position */ +#define SCU_SFSI2C0_SCL_EZI_Msk (0x01UL << SCU_SFSI2C0_SCL_EZI_Pos) /*!< SCU SFSI2C0: SCL_EZI Mask */ +#define SCU_SFSI2C0_SCL_ZIF_Pos 7 /*!< SCU SFSI2C0: SCL_ZIF Position */ +#define SCU_SFSI2C0_SCL_ZIF_Msk (0x01UL << SCU_SFSI2C0_SCL_ZIF_Pos) /*!< SCU SFSI2C0: SCL_ZIF Mask */ +#define SCU_SFSI2C0_SDA_EFP_Pos 8 /*!< SCU SFSI2C0: SDA_EFP Position */ +#define SCU_SFSI2C0_SDA_EFP_Msk (0x01UL << SCU_SFSI2C0_SDA_EFP_Pos) /*!< SCU SFSI2C0: SDA_EFP Mask */ +#define SCU_SFSI2C0_SDA_EHD_Pos 10 /*!< SCU SFSI2C0: SDA_EHD Position */ +#define SCU_SFSI2C0_SDA_EHD_Msk (0x01UL << SCU_SFSI2C0_SDA_EHD_Pos) /*!< SCU SFSI2C0: SDA_EHD Mask */ +#define SCU_SFSI2C0_SDA_EZI_Pos 11 /*!< SCU SFSI2C0: SDA_EZI Position */ +#define SCU_SFSI2C0_SDA_EZI_Msk (0x01UL << SCU_SFSI2C0_SDA_EZI_Pos) /*!< SCU SFSI2C0: SDA_EZI Mask */ +#define SCU_SFSI2C0_SDA_ZIF_Pos 15 /*!< SCU SFSI2C0: SDA_ZIF Position */ +#define SCU_SFSI2C0_SDA_ZIF_Msk (0x01UL << SCU_SFSI2C0_SDA_ZIF_Pos) /*!< SCU SFSI2C0: SDA_ZIF Mask */ + +/* --------------------------------- SCU_ENAIO0 --------------------------------- */ +#define SCU_ENAIO0_ADC0_0_Pos 0 /*!< SCU ENAIO0: ADC0_0 Position */ +#define SCU_ENAIO0_ADC0_0_Msk (0x01UL << SCU_ENAIO0_ADC0_0_Pos) /*!< SCU ENAIO0: ADC0_0 Mask */ +#define SCU_ENAIO0_ADC0_1_Pos 1 /*!< SCU ENAIO0: ADC0_1 Position */ +#define SCU_ENAIO0_ADC0_1_Msk (0x01UL << SCU_ENAIO0_ADC0_1_Pos) /*!< SCU ENAIO0: ADC0_1 Mask */ +#define SCU_ENAIO0_ADC0_2_Pos 2 /*!< SCU ENAIO0: ADC0_2 Position */ +#define SCU_ENAIO0_ADC0_2_Msk (0x01UL << SCU_ENAIO0_ADC0_2_Pos) /*!< SCU ENAIO0: ADC0_2 Mask */ +#define SCU_ENAIO0_ADC0_3_Pos 3 /*!< SCU ENAIO0: ADC0_3 Position */ +#define SCU_ENAIO0_ADC0_3_Msk (0x01UL << SCU_ENAIO0_ADC0_3_Pos) /*!< SCU ENAIO0: ADC0_3 Mask */ +#define SCU_ENAIO0_ADC0_4_Pos 4 /*!< SCU ENAIO0: ADC0_4 Position */ +#define SCU_ENAIO0_ADC0_4_Msk (0x01UL << SCU_ENAIO0_ADC0_4_Pos) /*!< SCU ENAIO0: ADC0_4 Mask */ +#define SCU_ENAIO0_ADC0_5_Pos 5 /*!< SCU ENAIO0: ADC0_5 Position */ +#define SCU_ENAIO0_ADC0_5_Msk (0x01UL << SCU_ENAIO0_ADC0_5_Pos) /*!< SCU ENAIO0: ADC0_5 Mask */ +#define SCU_ENAIO0_ADC0_6_Pos 6 /*!< SCU ENAIO0: ADC0_6 Position */ +#define SCU_ENAIO0_ADC0_6_Msk (0x01UL << SCU_ENAIO0_ADC0_6_Pos) /*!< SCU ENAIO0: ADC0_6 Mask */ + +/* --------------------------------- SCU_ENAIO1 --------------------------------- */ +#define SCU_ENAIO1_ADC1_0_Pos 0 /*!< SCU ENAIO1: ADC1_0 Position */ +#define SCU_ENAIO1_ADC1_0_Msk (0x01UL << SCU_ENAIO1_ADC1_0_Pos) /*!< SCU ENAIO1: ADC1_0 Mask */ +#define SCU_ENAIO1_ADC1_1_Pos 1 /*!< SCU ENAIO1: ADC1_1 Position */ +#define SCU_ENAIO1_ADC1_1_Msk (0x01UL << SCU_ENAIO1_ADC1_1_Pos) /*!< SCU ENAIO1: ADC1_1 Mask */ +#define SCU_ENAIO1_ADC1_2_Pos 2 /*!< SCU ENAIO1: ADC1_2 Position */ +#define SCU_ENAIO1_ADC1_2_Msk (0x01UL << SCU_ENAIO1_ADC1_2_Pos) /*!< SCU ENAIO1: ADC1_2 Mask */ +#define SCU_ENAIO1_ADC1_3_Pos 3 /*!< SCU ENAIO1: ADC1_3 Position */ +#define SCU_ENAIO1_ADC1_3_Msk (0x01UL << SCU_ENAIO1_ADC1_3_Pos) /*!< SCU ENAIO1: ADC1_3 Mask */ +#define SCU_ENAIO1_ADC1_4_Pos 4 /*!< SCU ENAIO1: ADC1_4 Position */ +#define SCU_ENAIO1_ADC1_4_Msk (0x01UL << SCU_ENAIO1_ADC1_4_Pos) /*!< SCU ENAIO1: ADC1_4 Mask */ +#define SCU_ENAIO1_ADC1_5_Pos 5 /*!< SCU ENAIO1: ADC1_5 Position */ +#define SCU_ENAIO1_ADC1_5_Msk (0x01UL << SCU_ENAIO1_ADC1_5_Pos) /*!< SCU ENAIO1: ADC1_5 Mask */ +#define SCU_ENAIO1_ADC1_6_Pos 6 /*!< SCU ENAIO1: ADC1_6 Position */ +#define SCU_ENAIO1_ADC1_6_Msk (0x01UL << SCU_ENAIO1_ADC1_6_Pos) /*!< SCU ENAIO1: ADC1_6 Mask */ +#define SCU_ENAIO1_ADC1_7_Pos 7 /*!< SCU ENAIO1: ADC1_7 Position */ +#define SCU_ENAIO1_ADC1_7_Msk (0x01UL << SCU_ENAIO1_ADC1_7_Pos) /*!< SCU ENAIO1: ADC1_7 Mask */ + +/* --------------------------------- SCU_ENAIO2 --------------------------------- */ +#define SCU_ENAIO2_DAC_Pos 0 /*!< SCU ENAIO2: DAC Position */ +#define SCU_ENAIO2_DAC_Msk (0x01UL << SCU_ENAIO2_DAC_Pos) /*!< SCU ENAIO2: DAC Mask */ +#define SCU_ENAIO2_BG_Pos 4 /*!< SCU ENAIO2: BG Position */ +#define SCU_ENAIO2_BG_Msk (0x01UL << SCU_ENAIO2_BG_Pos) /*!< SCU ENAIO2: BG Mask */ + +/* ------------------------------- SCU_EMCDELAYCLK ------------------------------ */ +#define SCU_EMCDELAYCLK_CLK_DELAY_Pos 0 /*!< SCU EMCDELAYCLK: CLK_DELAY Position */ +#define SCU_EMCDELAYCLK_CLK_DELAY_Msk (0x0000ffffUL << SCU_EMCDELAYCLK_CLK_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK_DELAY Mask */ + +/* --------------------------------- SCU_SDDELAY -------------------------------- */ +#define SCU_SDDELAY_SAMPLE_DELAY_Pos 0 /*!< SCU SDDELAY: SAMPLE_DELAY Position */ +#define SCU_SDDELAY_SAMPLE_DELAY_Msk (0x0fUL << SCU_SDDELAY_SAMPLE_DELAY_Pos) /*!< SCU SDDELAY: SAMPLE_DELAY Mask */ +#define SCU_SDDELAY_DRV_DELAY_Pos 8 /*!< SCU SDDELAY: DRV_DELAY Position */ +#define SCU_SDDELAY_DRV_DELAY_Msk (0x0fUL << SCU_SDDELAY_DRV_DELAY_Pos) /*!< SCU SDDELAY: DRV_DELAY Mask */ + +/* -------------------------------- SCU_PINTSEL0 -------------------------------- */ +#define SCU_PINTSEL0_INTPIN0_Pos 0 /*!< SCU PINTSEL0: INTPIN0 Position */ +#define SCU_PINTSEL0_INTPIN0_Msk (0x1fUL << SCU_PINTSEL0_INTPIN0_Pos) /*!< SCU PINTSEL0: INTPIN0 Mask */ +#define SCU_PINTSEL0_PORTSEL0_Pos 5 /*!< SCU PINTSEL0: PORTSEL0 Position */ +#define SCU_PINTSEL0_PORTSEL0_Msk (0x07UL << SCU_PINTSEL0_PORTSEL0_Pos) /*!< SCU PINTSEL0: PORTSEL0 Mask */ +#define SCU_PINTSEL0_INTPIN1_Pos 8 /*!< SCU PINTSEL0: INTPIN1 Position */ +#define SCU_PINTSEL0_INTPIN1_Msk (0x1fUL << SCU_PINTSEL0_INTPIN1_Pos) /*!< SCU PINTSEL0: INTPIN1 Mask */ +#define SCU_PINTSEL0_PORTSEL1_Pos 13 /*!< SCU PINTSEL0: PORTSEL1 Position */ +#define SCU_PINTSEL0_PORTSEL1_Msk (0x07UL << SCU_PINTSEL0_PORTSEL1_Pos) /*!< SCU PINTSEL0: PORTSEL1 Mask */ +#define SCU_PINTSEL0_INTPIN2_Pos 16 /*!< SCU PINTSEL0: INTPIN2 Position */ +#define SCU_PINTSEL0_INTPIN2_Msk (0x1fUL << SCU_PINTSEL0_INTPIN2_Pos) /*!< SCU PINTSEL0: INTPIN2 Mask */ +#define SCU_PINTSEL0_PORTSEL2_Pos 21 /*!< SCU PINTSEL0: PORTSEL2 Position */ +#define SCU_PINTSEL0_PORTSEL2_Msk (0x07UL << SCU_PINTSEL0_PORTSEL2_Pos) /*!< SCU PINTSEL0: PORTSEL2 Mask */ +#define SCU_PINTSEL0_INTPIN3_Pos 24 /*!< SCU PINTSEL0: INTPIN3 Position */ +#define SCU_PINTSEL0_INTPIN3_Msk (0x1fUL << SCU_PINTSEL0_INTPIN3_Pos) /*!< SCU PINTSEL0: INTPIN3 Mask */ +#define SCU_PINTSEL0_PORTSEL3_Pos 29 /*!< SCU PINTSEL0: PORTSEL3 Position */ +#define SCU_PINTSEL0_PORTSEL3_Msk (0x07UL << SCU_PINTSEL0_PORTSEL3_Pos) /*!< SCU PINTSEL0: PORTSEL3 Mask */ + +/* -------------------------------- SCU_PINTSEL1 -------------------------------- */ +#define SCU_PINTSEL1_INTPIN4_Pos 0 /*!< SCU PINTSEL1: INTPIN4 Position */ +#define SCU_PINTSEL1_INTPIN4_Msk (0x1fUL << SCU_PINTSEL1_INTPIN4_Pos) /*!< SCU PINTSEL1: INTPIN4 Mask */ +#define SCU_PINTSEL1_PORTSEL4_Pos 5 /*!< SCU PINTSEL1: PORTSEL4 Position */ +#define SCU_PINTSEL1_PORTSEL4_Msk (0x07UL << SCU_PINTSEL1_PORTSEL4_Pos) /*!< SCU PINTSEL1: PORTSEL4 Mask */ +#define SCU_PINTSEL1_INTPIN5_Pos 8 /*!< SCU PINTSEL1: INTPIN5 Position */ +#define SCU_PINTSEL1_INTPIN5_Msk (0x1fUL << SCU_PINTSEL1_INTPIN5_Pos) /*!< SCU PINTSEL1: INTPIN5 Mask */ +#define SCU_PINTSEL1_PORTSEL5_Pos 13 /*!< SCU PINTSEL1: PORTSEL5 Position */ +#define SCU_PINTSEL1_PORTSEL5_Msk (0x07UL << SCU_PINTSEL1_PORTSEL5_Pos) /*!< SCU PINTSEL1: PORTSEL5 Mask */ +#define SCU_PINTSEL1_INTPIN6_Pos 16 /*!< SCU PINTSEL1: INTPIN6 Position */ +#define SCU_PINTSEL1_INTPIN6_Msk (0x1fUL << SCU_PINTSEL1_INTPIN6_Pos) /*!< SCU PINTSEL1: INTPIN6 Mask */ +#define SCU_PINTSEL1_PORTSEL6_Pos 21 /*!< SCU PINTSEL1: PORTSEL6 Position */ +#define SCU_PINTSEL1_PORTSEL6_Msk (0x07UL << SCU_PINTSEL1_PORTSEL6_Pos) /*!< SCU PINTSEL1: PORTSEL6 Mask */ +#define SCU_PINTSEL1_INTPIN7_Pos 24 /*!< SCU PINTSEL1: INTPIN7 Position */ +#define SCU_PINTSEL1_INTPIN7_Msk (0x1fUL << SCU_PINTSEL1_INTPIN7_Pos) /*!< SCU PINTSEL1: INTPIN7 Mask */ +#define SCU_PINTSEL1_PORTSEL7_Pos 29 /*!< SCU PINTSEL1: PORTSEL7 Position */ +#define SCU_PINTSEL1_PORTSEL7_Msk (0x07UL << SCU_PINTSEL1_PORTSEL7_Pos) /*!< SCU PINTSEL1: PORTSEL7 Mask */ + + +/* ================================================================================ */ +/* ================ struct 'GPIO_PIN_INT' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------ GPIO_PIN_INT_ISEL ----------------------------- */ +#define GPIO_PIN_INT_ISEL_PMODE0_Pos 0 /*!< GPIO_PIN_INT ISEL: PMODE0 Position */ +#define GPIO_PIN_INT_ISEL_PMODE0_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE0_Pos) /*!< GPIO_PIN_INT ISEL: PMODE0 Mask */ +#define GPIO_PIN_INT_ISEL_PMODE1_Pos 1 /*!< GPIO_PIN_INT ISEL: PMODE1 Position */ +#define GPIO_PIN_INT_ISEL_PMODE1_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE1_Pos) /*!< GPIO_PIN_INT ISEL: PMODE1 Mask */ +#define GPIO_PIN_INT_ISEL_PMODE2_Pos 2 /*!< GPIO_PIN_INT ISEL: PMODE2 Position */ +#define GPIO_PIN_INT_ISEL_PMODE2_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE2_Pos) /*!< GPIO_PIN_INT ISEL: PMODE2 Mask */ +#define GPIO_PIN_INT_ISEL_PMODE3_Pos 3 /*!< GPIO_PIN_INT ISEL: PMODE3 Position */ +#define GPIO_PIN_INT_ISEL_PMODE3_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE3_Pos) /*!< GPIO_PIN_INT ISEL: PMODE3 Mask */ +#define GPIO_PIN_INT_ISEL_PMODE4_Pos 4 /*!< GPIO_PIN_INT ISEL: PMODE4 Position */ +#define GPIO_PIN_INT_ISEL_PMODE4_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE4_Pos) /*!< GPIO_PIN_INT ISEL: PMODE4 Mask */ +#define GPIO_PIN_INT_ISEL_PMODE5_Pos 5 /*!< GPIO_PIN_INT ISEL: PMODE5 Position */ +#define GPIO_PIN_INT_ISEL_PMODE5_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE5_Pos) /*!< GPIO_PIN_INT ISEL: PMODE5 Mask */ +#define GPIO_PIN_INT_ISEL_PMODE6_Pos 6 /*!< GPIO_PIN_INT ISEL: PMODE6 Position */ +#define GPIO_PIN_INT_ISEL_PMODE6_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE6_Pos) /*!< GPIO_PIN_INT ISEL: PMODE6 Mask */ +#define GPIO_PIN_INT_ISEL_PMODE7_Pos 7 /*!< GPIO_PIN_INT ISEL: PMODE7 Position */ +#define GPIO_PIN_INT_ISEL_PMODE7_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE7_Pos) /*!< GPIO_PIN_INT ISEL: PMODE7 Mask */ + +/* ------------------------------ GPIO_PIN_INT_IENR ----------------------------- */ +#define GPIO_PIN_INT_IENR_ENRL0_Pos 0 /*!< GPIO_PIN_INT IENR: ENRL0 Position */ +#define GPIO_PIN_INT_IENR_ENRL0_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL0_Pos) /*!< GPIO_PIN_INT IENR: ENRL0 Mask */ +#define GPIO_PIN_INT_IENR_ENRL1_Pos 1 /*!< GPIO_PIN_INT IENR: ENRL1 Position */ +#define GPIO_PIN_INT_IENR_ENRL1_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL1_Pos) /*!< GPIO_PIN_INT IENR: ENRL1 Mask */ +#define GPIO_PIN_INT_IENR_ENRL2_Pos 2 /*!< GPIO_PIN_INT IENR: ENRL2 Position */ +#define GPIO_PIN_INT_IENR_ENRL2_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL2_Pos) /*!< GPIO_PIN_INT IENR: ENRL2 Mask */ +#define GPIO_PIN_INT_IENR_ENRL3_Pos 3 /*!< GPIO_PIN_INT IENR: ENRL3 Position */ +#define GPIO_PIN_INT_IENR_ENRL3_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL3_Pos) /*!< GPIO_PIN_INT IENR: ENRL3 Mask */ +#define GPIO_PIN_INT_IENR_ENRL4_Pos 4 /*!< GPIO_PIN_INT IENR: ENRL4 Position */ +#define GPIO_PIN_INT_IENR_ENRL4_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL4_Pos) /*!< GPIO_PIN_INT IENR: ENRL4 Mask */ +#define GPIO_PIN_INT_IENR_ENRL5_Pos 5 /*!< GPIO_PIN_INT IENR: ENRL5 Position */ +#define GPIO_PIN_INT_IENR_ENRL5_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL5_Pos) /*!< GPIO_PIN_INT IENR: ENRL5 Mask */ +#define GPIO_PIN_INT_IENR_ENRL6_Pos 6 /*!< GPIO_PIN_INT IENR: ENRL6 Position */ +#define GPIO_PIN_INT_IENR_ENRL6_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL6_Pos) /*!< GPIO_PIN_INT IENR: ENRL6 Mask */ +#define GPIO_PIN_INT_IENR_ENRL7_Pos 7 /*!< GPIO_PIN_INT IENR: ENRL7 Position */ +#define GPIO_PIN_INT_IENR_ENRL7_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL7_Pos) /*!< GPIO_PIN_INT IENR: ENRL7 Mask */ + +/* ----------------------------- GPIO_PIN_INT_SIENR ----------------------------- */ +#define GPIO_PIN_INT_SIENR_SETENRL0_Pos 0 /*!< GPIO_PIN_INT SIENR: SETENRL0 Position */ +#define GPIO_PIN_INT_SIENR_SETENRL0_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL0_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL0 Mask */ +#define GPIO_PIN_INT_SIENR_SETENRL1_Pos 1 /*!< GPIO_PIN_INT SIENR: SETENRL1 Position */ +#define GPIO_PIN_INT_SIENR_SETENRL1_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL1_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL1 Mask */ +#define GPIO_PIN_INT_SIENR_SETENRL2_Pos 2 /*!< GPIO_PIN_INT SIENR: SETENRL2 Position */ +#define GPIO_PIN_INT_SIENR_SETENRL2_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL2_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL2 Mask */ +#define GPIO_PIN_INT_SIENR_SETENRL3_Pos 3 /*!< GPIO_PIN_INT SIENR: SETENRL3 Position */ +#define GPIO_PIN_INT_SIENR_SETENRL3_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL3_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL3 Mask */ +#define GPIO_PIN_INT_SIENR_SETENRL4_Pos 4 /*!< GPIO_PIN_INT SIENR: SETENRL4 Position */ +#define GPIO_PIN_INT_SIENR_SETENRL4_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL4_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL4 Mask */ +#define GPIO_PIN_INT_SIENR_SETENRL5_Pos 5 /*!< GPIO_PIN_INT SIENR: SETENRL5 Position */ +#define GPIO_PIN_INT_SIENR_SETENRL5_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL5_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL5 Mask */ +#define GPIO_PIN_INT_SIENR_SETENRL6_Pos 6 /*!< GPIO_PIN_INT SIENR: SETENRL6 Position */ +#define GPIO_PIN_INT_SIENR_SETENRL6_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL6_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL6 Mask */ +#define GPIO_PIN_INT_SIENR_SETENRL7_Pos 7 /*!< GPIO_PIN_INT SIENR: SETENRL7 Position */ +#define GPIO_PIN_INT_SIENR_SETENRL7_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL7_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL7 Mask */ + +/* ----------------------------- GPIO_PIN_INT_CIENR ----------------------------- */ +#define GPIO_PIN_INT_CIENR_CENRL0_Pos 0 /*!< GPIO_PIN_INT CIENR: CENRL0 Position */ +#define GPIO_PIN_INT_CIENR_CENRL0_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL0_Pos) /*!< GPIO_PIN_INT CIENR: CENRL0 Mask */ +#define GPIO_PIN_INT_CIENR_CENRL1_Pos 1 /*!< GPIO_PIN_INT CIENR: CENRL1 Position */ +#define GPIO_PIN_INT_CIENR_CENRL1_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL1_Pos) /*!< GPIO_PIN_INT CIENR: CENRL1 Mask */ +#define GPIO_PIN_INT_CIENR_CENRL2_Pos 2 /*!< GPIO_PIN_INT CIENR: CENRL2 Position */ +#define GPIO_PIN_INT_CIENR_CENRL2_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL2_Pos) /*!< GPIO_PIN_INT CIENR: CENRL2 Mask */ +#define GPIO_PIN_INT_CIENR_CENRL3_Pos 3 /*!< GPIO_PIN_INT CIENR: CENRL3 Position */ +#define GPIO_PIN_INT_CIENR_CENRL3_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL3_Pos) /*!< GPIO_PIN_INT CIENR: CENRL3 Mask */ +#define GPIO_PIN_INT_CIENR_CENRL4_Pos 4 /*!< GPIO_PIN_INT CIENR: CENRL4 Position */ +#define GPIO_PIN_INT_CIENR_CENRL4_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL4_Pos) /*!< GPIO_PIN_INT CIENR: CENRL4 Mask */ +#define GPIO_PIN_INT_CIENR_CENRL5_Pos 5 /*!< GPIO_PIN_INT CIENR: CENRL5 Position */ +#define GPIO_PIN_INT_CIENR_CENRL5_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL5_Pos) /*!< GPIO_PIN_INT CIENR: CENRL5 Mask */ +#define GPIO_PIN_INT_CIENR_CENRL6_Pos 6 /*!< GPIO_PIN_INT CIENR: CENRL6 Position */ +#define GPIO_PIN_INT_CIENR_CENRL6_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL6_Pos) /*!< GPIO_PIN_INT CIENR: CENRL6 Mask */ +#define GPIO_PIN_INT_CIENR_CENRL7_Pos 7 /*!< GPIO_PIN_INT CIENR: CENRL7 Position */ +#define GPIO_PIN_INT_CIENR_CENRL7_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL7_Pos) /*!< GPIO_PIN_INT CIENR: CENRL7 Mask */ + +/* ------------------------------ GPIO_PIN_INT_IENF ----------------------------- */ +#define GPIO_PIN_INT_IENF_ENAF0_Pos 0 /*!< GPIO_PIN_INT IENF: ENAF0 Position */ +#define GPIO_PIN_INT_IENF_ENAF0_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF0_Pos) /*!< GPIO_PIN_INT IENF: ENAF0 Mask */ +#define GPIO_PIN_INT_IENF_ENAF1_Pos 1 /*!< GPIO_PIN_INT IENF: ENAF1 Position */ +#define GPIO_PIN_INT_IENF_ENAF1_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF1_Pos) /*!< GPIO_PIN_INT IENF: ENAF1 Mask */ +#define GPIO_PIN_INT_IENF_ENAF2_Pos 2 /*!< GPIO_PIN_INT IENF: ENAF2 Position */ +#define GPIO_PIN_INT_IENF_ENAF2_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF2_Pos) /*!< GPIO_PIN_INT IENF: ENAF2 Mask */ +#define GPIO_PIN_INT_IENF_ENAF3_Pos 3 /*!< GPIO_PIN_INT IENF: ENAF3 Position */ +#define GPIO_PIN_INT_IENF_ENAF3_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF3_Pos) /*!< GPIO_PIN_INT IENF: ENAF3 Mask */ +#define GPIO_PIN_INT_IENF_ENAF4_Pos 4 /*!< GPIO_PIN_INT IENF: ENAF4 Position */ +#define GPIO_PIN_INT_IENF_ENAF4_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF4_Pos) /*!< GPIO_PIN_INT IENF: ENAF4 Mask */ +#define GPIO_PIN_INT_IENF_ENAF5_Pos 5 /*!< GPIO_PIN_INT IENF: ENAF5 Position */ +#define GPIO_PIN_INT_IENF_ENAF5_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF5_Pos) /*!< GPIO_PIN_INT IENF: ENAF5 Mask */ +#define GPIO_PIN_INT_IENF_ENAF6_Pos 6 /*!< GPIO_PIN_INT IENF: ENAF6 Position */ +#define GPIO_PIN_INT_IENF_ENAF6_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF6_Pos) /*!< GPIO_PIN_INT IENF: ENAF6 Mask */ +#define GPIO_PIN_INT_IENF_ENAF7_Pos 7 /*!< GPIO_PIN_INT IENF: ENAF7 Position */ +#define GPIO_PIN_INT_IENF_ENAF7_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF7_Pos) /*!< GPIO_PIN_INT IENF: ENAF7 Mask */ + +/* ----------------------------- GPIO_PIN_INT_SIENF ----------------------------- */ +#define GPIO_PIN_INT_SIENF_SETENAF0_Pos 0 /*!< GPIO_PIN_INT SIENF: SETENAF0 Position */ +#define GPIO_PIN_INT_SIENF_SETENAF0_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF0_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF0 Mask */ +#define GPIO_PIN_INT_SIENF_SETENAF1_Pos 1 /*!< GPIO_PIN_INT SIENF: SETENAF1 Position */ +#define GPIO_PIN_INT_SIENF_SETENAF1_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF1_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF1 Mask */ +#define GPIO_PIN_INT_SIENF_SETENAF2_Pos 2 /*!< GPIO_PIN_INT SIENF: SETENAF2 Position */ +#define GPIO_PIN_INT_SIENF_SETENAF2_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF2_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF2 Mask */ +#define GPIO_PIN_INT_SIENF_SETENAF3_Pos 3 /*!< GPIO_PIN_INT SIENF: SETENAF3 Position */ +#define GPIO_PIN_INT_SIENF_SETENAF3_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF3_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF3 Mask */ +#define GPIO_PIN_INT_SIENF_SETENAF4_Pos 4 /*!< GPIO_PIN_INT SIENF: SETENAF4 Position */ +#define GPIO_PIN_INT_SIENF_SETENAF4_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF4_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF4 Mask */ +#define GPIO_PIN_INT_SIENF_SETENAF5_Pos 5 /*!< GPIO_PIN_INT SIENF: SETENAF5 Position */ +#define GPIO_PIN_INT_SIENF_SETENAF5_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF5_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF5 Mask */ +#define GPIO_PIN_INT_SIENF_SETENAF6_Pos 6 /*!< GPIO_PIN_INT SIENF: SETENAF6 Position */ +#define GPIO_PIN_INT_SIENF_SETENAF6_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF6_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF6 Mask */ +#define GPIO_PIN_INT_SIENF_SETENAF7_Pos 7 /*!< GPIO_PIN_INT SIENF: SETENAF7 Position */ +#define GPIO_PIN_INT_SIENF_SETENAF7_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF7_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF7 Mask */ + +/* ----------------------------- GPIO_PIN_INT_CIENF ----------------------------- */ +#define GPIO_PIN_INT_CIENF_CENAF0_Pos 0 /*!< GPIO_PIN_INT CIENF: CENAF0 Position */ +#define GPIO_PIN_INT_CIENF_CENAF0_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF0_Pos) /*!< GPIO_PIN_INT CIENF: CENAF0 Mask */ +#define GPIO_PIN_INT_CIENF_CENAF1_Pos 1 /*!< GPIO_PIN_INT CIENF: CENAF1 Position */ +#define GPIO_PIN_INT_CIENF_CENAF1_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF1_Pos) /*!< GPIO_PIN_INT CIENF: CENAF1 Mask */ +#define GPIO_PIN_INT_CIENF_CENAF2_Pos 2 /*!< GPIO_PIN_INT CIENF: CENAF2 Position */ +#define GPIO_PIN_INT_CIENF_CENAF2_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF2_Pos) /*!< GPIO_PIN_INT CIENF: CENAF2 Mask */ +#define GPIO_PIN_INT_CIENF_CENAF3_Pos 3 /*!< GPIO_PIN_INT CIENF: CENAF3 Position */ +#define GPIO_PIN_INT_CIENF_CENAF3_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF3_Pos) /*!< GPIO_PIN_INT CIENF: CENAF3 Mask */ +#define GPIO_PIN_INT_CIENF_CENAF4_Pos 4 /*!< GPIO_PIN_INT CIENF: CENAF4 Position */ +#define GPIO_PIN_INT_CIENF_CENAF4_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF4_Pos) /*!< GPIO_PIN_INT CIENF: CENAF4 Mask */ +#define GPIO_PIN_INT_CIENF_CENAF5_Pos 5 /*!< GPIO_PIN_INT CIENF: CENAF5 Position */ +#define GPIO_PIN_INT_CIENF_CENAF5_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF5_Pos) /*!< GPIO_PIN_INT CIENF: CENAF5 Mask */ +#define GPIO_PIN_INT_CIENF_CENAF6_Pos 6 /*!< GPIO_PIN_INT CIENF: CENAF6 Position */ +#define GPIO_PIN_INT_CIENF_CENAF6_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF6_Pos) /*!< GPIO_PIN_INT CIENF: CENAF6 Mask */ +#define GPIO_PIN_INT_CIENF_CENAF7_Pos 7 /*!< GPIO_PIN_INT CIENF: CENAF7 Position */ +#define GPIO_PIN_INT_CIENF_CENAF7_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF7_Pos) /*!< GPIO_PIN_INT CIENF: CENAF7 Mask */ + +/* ------------------------------ GPIO_PIN_INT_RISE ----------------------------- */ +#define GPIO_PIN_INT_RISE_RDET0_Pos 0 /*!< GPIO_PIN_INT RISE: RDET0 Position */ +#define GPIO_PIN_INT_RISE_RDET0_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET0_Pos) /*!< GPIO_PIN_INT RISE: RDET0 Mask */ +#define GPIO_PIN_INT_RISE_RDET1_Pos 1 /*!< GPIO_PIN_INT RISE: RDET1 Position */ +#define GPIO_PIN_INT_RISE_RDET1_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET1_Pos) /*!< GPIO_PIN_INT RISE: RDET1 Mask */ +#define GPIO_PIN_INT_RISE_RDET2_Pos 2 /*!< GPIO_PIN_INT RISE: RDET2 Position */ +#define GPIO_PIN_INT_RISE_RDET2_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET2_Pos) /*!< GPIO_PIN_INT RISE: RDET2 Mask */ +#define GPIO_PIN_INT_RISE_RDET3_Pos 3 /*!< GPIO_PIN_INT RISE: RDET3 Position */ +#define GPIO_PIN_INT_RISE_RDET3_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET3_Pos) /*!< GPIO_PIN_INT RISE: RDET3 Mask */ +#define GPIO_PIN_INT_RISE_RDET4_Pos 4 /*!< GPIO_PIN_INT RISE: RDET4 Position */ +#define GPIO_PIN_INT_RISE_RDET4_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET4_Pos) /*!< GPIO_PIN_INT RISE: RDET4 Mask */ +#define GPIO_PIN_INT_RISE_RDET5_Pos 5 /*!< GPIO_PIN_INT RISE: RDET5 Position */ +#define GPIO_PIN_INT_RISE_RDET5_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET5_Pos) /*!< GPIO_PIN_INT RISE: RDET5 Mask */ +#define GPIO_PIN_INT_RISE_RDET6_Pos 6 /*!< GPIO_PIN_INT RISE: RDET6 Position */ +#define GPIO_PIN_INT_RISE_RDET6_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET6_Pos) /*!< GPIO_PIN_INT RISE: RDET6 Mask */ +#define GPIO_PIN_INT_RISE_RDET7_Pos 7 /*!< GPIO_PIN_INT RISE: RDET7 Position */ +#define GPIO_PIN_INT_RISE_RDET7_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET7_Pos) /*!< GPIO_PIN_INT RISE: RDET7 Mask */ + +/* ------------------------------ GPIO_PIN_INT_FALL ----------------------------- */ +#define GPIO_PIN_INT_FALL_FDET0_Pos 0 /*!< GPIO_PIN_INT FALL: FDET0 Position */ +#define GPIO_PIN_INT_FALL_FDET0_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET0_Pos) /*!< GPIO_PIN_INT FALL: FDET0 Mask */ +#define GPIO_PIN_INT_FALL_FDET1_Pos 1 /*!< GPIO_PIN_INT FALL: FDET1 Position */ +#define GPIO_PIN_INT_FALL_FDET1_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET1_Pos) /*!< GPIO_PIN_INT FALL: FDET1 Mask */ +#define GPIO_PIN_INT_FALL_FDET2_Pos 2 /*!< GPIO_PIN_INT FALL: FDET2 Position */ +#define GPIO_PIN_INT_FALL_FDET2_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET2_Pos) /*!< GPIO_PIN_INT FALL: FDET2 Mask */ +#define GPIO_PIN_INT_FALL_FDET3_Pos 3 /*!< GPIO_PIN_INT FALL: FDET3 Position */ +#define GPIO_PIN_INT_FALL_FDET3_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET3_Pos) /*!< GPIO_PIN_INT FALL: FDET3 Mask */ +#define GPIO_PIN_INT_FALL_FDET4_Pos 4 /*!< GPIO_PIN_INT FALL: FDET4 Position */ +#define GPIO_PIN_INT_FALL_FDET4_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET4_Pos) /*!< GPIO_PIN_INT FALL: FDET4 Mask */ +#define GPIO_PIN_INT_FALL_FDET5_Pos 5 /*!< GPIO_PIN_INT FALL: FDET5 Position */ +#define GPIO_PIN_INT_FALL_FDET5_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET5_Pos) /*!< GPIO_PIN_INT FALL: FDET5 Mask */ +#define GPIO_PIN_INT_FALL_FDET6_Pos 6 /*!< GPIO_PIN_INT FALL: FDET6 Position */ +#define GPIO_PIN_INT_FALL_FDET6_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET6_Pos) /*!< GPIO_PIN_INT FALL: FDET6 Mask */ +#define GPIO_PIN_INT_FALL_FDET7_Pos 7 /*!< GPIO_PIN_INT FALL: FDET7 Position */ +#define GPIO_PIN_INT_FALL_FDET7_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET7_Pos) /*!< GPIO_PIN_INT FALL: FDET7 Mask */ + +/* ------------------------------ GPIO_PIN_INT_IST ------------------------------ */ +#define GPIO_PIN_INT_IST_PSTAT0_Pos 0 /*!< GPIO_PIN_INT IST: PSTAT0 Position */ +#define GPIO_PIN_INT_IST_PSTAT0_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT0_Pos) /*!< GPIO_PIN_INT IST: PSTAT0 Mask */ +#define GPIO_PIN_INT_IST_PSTAT1_Pos 1 /*!< GPIO_PIN_INT IST: PSTAT1 Position */ +#define GPIO_PIN_INT_IST_PSTAT1_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT1_Pos) /*!< GPIO_PIN_INT IST: PSTAT1 Mask */ +#define GPIO_PIN_INT_IST_PSTAT2_Pos 2 /*!< GPIO_PIN_INT IST: PSTAT2 Position */ +#define GPIO_PIN_INT_IST_PSTAT2_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT2_Pos) /*!< GPIO_PIN_INT IST: PSTAT2 Mask */ +#define GPIO_PIN_INT_IST_PSTAT3_Pos 3 /*!< GPIO_PIN_INT IST: PSTAT3 Position */ +#define GPIO_PIN_INT_IST_PSTAT3_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT3_Pos) /*!< GPIO_PIN_INT IST: PSTAT3 Mask */ +#define GPIO_PIN_INT_IST_PSTAT4_Pos 4 /*!< GPIO_PIN_INT IST: PSTAT4 Position */ +#define GPIO_PIN_INT_IST_PSTAT4_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT4_Pos) /*!< GPIO_PIN_INT IST: PSTAT4 Mask */ +#define GPIO_PIN_INT_IST_PSTAT5_Pos 5 /*!< GPIO_PIN_INT IST: PSTAT5 Position */ +#define GPIO_PIN_INT_IST_PSTAT5_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT5_Pos) /*!< GPIO_PIN_INT IST: PSTAT5 Mask */ +#define GPIO_PIN_INT_IST_PSTAT6_Pos 6 /*!< GPIO_PIN_INT IST: PSTAT6 Position */ +#define GPIO_PIN_INT_IST_PSTAT6_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT6_Pos) /*!< GPIO_PIN_INT IST: PSTAT6 Mask */ +#define GPIO_PIN_INT_IST_PSTAT7_Pos 7 /*!< GPIO_PIN_INT IST: PSTAT7 Position */ +#define GPIO_PIN_INT_IST_PSTAT7_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT7_Pos) /*!< GPIO_PIN_INT IST: PSTAT7 Mask */ + + +/* ================================================================================ */ +/* ================ Group 'GPIO_GROUP_INTn' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------- GPIO_GROUP_INTn_CTRL ---------------------------- */ +#define GPIO_GROUP_INTn_CTRL_INT_Pos 0 /*!< GPIO_GROUP_INTn CTRL: INT Position */ +#define GPIO_GROUP_INTn_CTRL_INT_Msk (0x01UL << GPIO_GROUP_INTn_CTRL_INT_Pos) /*!< GPIO_GROUP_INTn CTRL: INT Mask */ +#define GPIO_GROUP_INTn_CTRL_COMB_Pos 1 /*!< GPIO_GROUP_INTn CTRL: COMB Position */ +#define GPIO_GROUP_INTn_CTRL_COMB_Msk (0x01UL << GPIO_GROUP_INTn_CTRL_COMB_Pos) /*!< GPIO_GROUP_INTn CTRL: COMB Mask */ +#define GPIO_GROUP_INTn_CTRL_TRIG_Pos 2 /*!< GPIO_GROUP_INTn CTRL: TRIG Position */ +#define GPIO_GROUP_INTn_CTRL_TRIG_Msk (0x01UL << GPIO_GROUP_INTn_CTRL_TRIG_Pos) /*!< GPIO_GROUP_INTn CTRL: TRIG Mask */ + +/* -------------------------- GPIO_GROUP_INTn_PORT_POL0 ------------------------- */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Mask */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Position */ +#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INTn_PORT_POL1 ------------------------- */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Mask */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Position */ +#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INTn_PORT_POL2 ------------------------- */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Mask */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Position */ +#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INTn_PORT_POL3 ------------------------- */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Mask */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Position */ +#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INTn_PORT_POL4 ------------------------- */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Mask */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Position */ +#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INTn_PORT_POL5 ------------------------- */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Mask */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Position */ +#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INTn_PORT_POL6 ------------------------- */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Mask */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Position */ +#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INTn_PORT_POL7 ------------------------- */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Mask */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Position */ +#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INTn_PORT_ENA0 ------------------------- */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Position */ +#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Mask */ + +/* -------------------------- GPIO_GROUP_INTn_PORT_ENA1 ------------------------- */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Position */ +#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Mask */ + +/* -------------------------- GPIO_GROUP_INTn_PORT_ENA2 ------------------------- */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Position */ +#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Mask */ + +/* -------------------------- GPIO_GROUP_INTn_PORT_ENA3 ------------------------- */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Position */ +#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Mask */ + +/* -------------------------- GPIO_GROUP_INTn_PORT_ENA4 ------------------------- */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Position */ +#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Mask */ + +/* -------------------------- GPIO_GROUP_INTn_PORT_ENA5 ------------------------- */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Position */ +#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Mask */ + +/* -------------------------- GPIO_GROUP_INTn_PORT_ENA6 ------------------------- */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Position */ +#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Mask */ + +/* -------------------------- GPIO_GROUP_INTn_PORT_ENA7 ------------------------- */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Mask */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Position */ +#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Mask */ + + +/* ================================================================================ */ +/* ================ struct 'GPIO_GROUP_INT0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------- GPIO_GROUP_INT0_CTRL ---------------------------- */ +#define GPIO_GROUP_INT0_CTRL_INT_Pos 0 /*!< GPIO_GROUP_INT0 CTRL: INT Position */ +#define GPIO_GROUP_INT0_CTRL_INT_Msk (0x01UL << GPIO_GROUP_INT0_CTRL_INT_Pos) /*!< GPIO_GROUP_INT0 CTRL: INT Mask */ +#define GPIO_GROUP_INT0_CTRL_COMB_Pos 1 /*!< GPIO_GROUP_INT0 CTRL: COMB Position */ +#define GPIO_GROUP_INT0_CTRL_COMB_Msk (0x01UL << GPIO_GROUP_INT0_CTRL_COMB_Pos) /*!< GPIO_GROUP_INT0 CTRL: COMB Mask */ +#define GPIO_GROUP_INT0_CTRL_TRIG_Pos 2 /*!< GPIO_GROUP_INT0 CTRL: TRIG Position */ +#define GPIO_GROUP_INT0_CTRL_TRIG_Msk (0x01UL << GPIO_GROUP_INT0_CTRL_TRIG_Pos) /*!< GPIO_GROUP_INT0 CTRL: TRIG Mask */ + +/* -------------------------- GPIO_GROUP_INT0_PORT_POL0 ------------------------- */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_0 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_0_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_0 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_1 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_1_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_1 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_2 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_2_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_2 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_3 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_3_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_3 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_4 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_4_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_4 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_5 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_5_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_5 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_6 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_6_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_6 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_7 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_7_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_7 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_8 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_8_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_8 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_9 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_9_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_9 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_10 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_10_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_10 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_11 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_11_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_11 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_12 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_12_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_12 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_13 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_13_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_13 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_14 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_14_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_14 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_15 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_15_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_15 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_16 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_16_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_16 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_17 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_17_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_17 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_18 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_18_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_18 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_19 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_19_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_19 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_20 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_20_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_20 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_21 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_21_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_21 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_22 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_22_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_22 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_23 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_23_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_23 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_24 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_24_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_24 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_25 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_25_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_25 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_26 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_26_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_26 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_27 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_27_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_27 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_28 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_28_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_28 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_29 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_29_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_29 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_30 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_30_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_30 Mask */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_31 Position */ +#define GPIO_GROUP_INT0_PORT_POL0_POL_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_31_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT0_PORT_POL1 ------------------------- */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_0 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_0_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_0 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_1 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_1_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_1 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_2 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_2_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_2 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_3 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_3_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_3 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_4 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_4_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_4 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_5 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_5_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_5 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_6 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_6_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_6 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_7 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_7_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_7 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_8 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_8_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_8 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_9 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_9_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_9 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_10 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_10_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_10 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_11 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_11_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_11 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_12 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_12_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_12 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_13 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_13_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_13 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_14 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_14_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_14 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_15 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_15_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_15 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_16 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_16_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_16 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_17 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_17_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_17 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_18 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_18_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_18 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_19 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_19_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_19 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_20 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_20_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_20 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_21 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_21_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_21 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_22 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_22_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_22 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_23 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_23_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_23 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_24 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_24_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_24 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_25 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_25_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_25 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_26 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_26_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_26 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_27 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_27_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_27 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_28 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_28_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_28 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_29 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_29_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_29 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_30 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_30_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_30 Mask */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_31 Position */ +#define GPIO_GROUP_INT0_PORT_POL1_POL_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_31_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT0_PORT_POL2 ------------------------- */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_0 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_0_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_0 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_1 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_1_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_1 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_2 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_2_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_2 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_3 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_3_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_3 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_4 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_4_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_4 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_5 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_5_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_5 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_6 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_6_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_6 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_7 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_7_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_7 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_8 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_8_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_8 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_9 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_9_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_9 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_10 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_10_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_10 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_11 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_11_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_11 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_12 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_12_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_12 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_13 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_13_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_13 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_14 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_14_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_14 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_15 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_15_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_15 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_16 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_16_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_16 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_17 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_17_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_17 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_18 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_18_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_18 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_19 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_19_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_19 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_20 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_20_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_20 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_21 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_21_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_21 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_22 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_22_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_22 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_23 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_23_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_23 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_24 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_24_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_24 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_25 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_25_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_25 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_26 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_26_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_26 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_27 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_27_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_27 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_28 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_28_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_28 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_29 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_29_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_29 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_30 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_30_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_30 Mask */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_31 Position */ +#define GPIO_GROUP_INT0_PORT_POL2_POL_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_31_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT0_PORT_POL3 ------------------------- */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_0 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_0_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_0 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_1 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_1_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_1 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_2 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_2_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_2 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_3 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_3_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_3 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_4 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_4_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_4 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_5 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_5_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_5 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_6 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_6_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_6 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_7 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_7_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_7 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_8 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_8_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_8 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_9 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_9_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_9 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_10 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_10_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_10 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_11 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_11_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_11 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_12 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_12_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_12 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_13 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_13_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_13 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_14 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_14_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_14 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_15 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_15_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_15 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_16 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_16_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_16 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_17 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_17_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_17 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_18 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_18_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_18 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_19 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_19_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_19 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_20 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_20_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_20 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_21 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_21_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_21 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_22 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_22_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_22 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_23 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_23_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_23 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_24 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_24_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_24 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_25 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_25_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_25 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_26 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_26_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_26 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_27 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_27_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_27 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_28 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_28_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_28 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_29 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_29_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_29 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_30 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_30_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_30 Mask */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_31 Position */ +#define GPIO_GROUP_INT0_PORT_POL3_POL_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_31_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT0_PORT_POL4 ------------------------- */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_0 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_0_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_0 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_1 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_1_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_1 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_2 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_2_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_2 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_3 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_3_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_3 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_4 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_4_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_4 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_5 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_5_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_5 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_6 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_6_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_6 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_7 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_7_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_7 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_8 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_8_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_8 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_9 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_9_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_9 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_10 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_10_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_10 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_11 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_11_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_11 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_12 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_12_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_12 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_13 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_13_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_13 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_14 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_14_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_14 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_15 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_15_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_15 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_16 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_16_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_16 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_17 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_17_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_17 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_18 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_18_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_18 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_19 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_19_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_19 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_20 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_20_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_20 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_21 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_21_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_21 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_22 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_22_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_22 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_23 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_23_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_23 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_24 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_24_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_24 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_25 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_25_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_25 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_26 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_26_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_26 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_27 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_27_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_27 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_28 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_28_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_28 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_29 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_29_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_29 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_30 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_30_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_30 Mask */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_31 Position */ +#define GPIO_GROUP_INT0_PORT_POL4_POL_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_31_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT0_PORT_POL5 ------------------------- */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_0 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_0_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_0 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_1 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_1_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_1 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_2 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_2_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_2 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_3 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_3_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_3 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_4 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_4_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_4 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_5 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_5_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_5 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_6 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_6_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_6 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_7 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_7_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_7 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_8 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_8_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_8 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_9 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_9_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_9 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_10 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_10_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_10 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_11 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_11_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_11 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_12 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_12_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_12 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_13 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_13_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_13 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_14 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_14_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_14 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_15 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_15_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_15 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_16 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_16_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_16 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_17 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_17_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_17 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_18 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_18_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_18 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_19 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_19_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_19 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_20 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_20_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_20 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_21 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_21_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_21 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_22 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_22_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_22 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_23 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_23_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_23 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_24 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_24_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_24 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_25 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_25_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_25 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_26 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_26_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_26 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_27 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_27_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_27 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_28 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_28_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_28 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_29 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_29_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_29 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_30 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_30_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_30 Mask */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_31 Position */ +#define GPIO_GROUP_INT0_PORT_POL5_POL_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_31_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT0_PORT_POL6 ------------------------- */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_0 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_0_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_0 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_1 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_1_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_1 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_2 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_2_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_2 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_3 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_3_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_3 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_4 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_4_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_4 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_5 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_5_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_5 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_6 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_6_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_6 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_7 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_7_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_7 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_8 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_8_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_8 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_9 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_9_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_9 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_10 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_10_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_10 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_11 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_11_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_11 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_12 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_12_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_12 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_13 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_13_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_13 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_14 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_14_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_14 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_15 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_15_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_15 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_16 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_16_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_16 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_17 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_17_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_17 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_18 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_18_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_18 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_19 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_19_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_19 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_20 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_20_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_20 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_21 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_21_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_21 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_22 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_22_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_22 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_23 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_23_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_23 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_24 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_24_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_24 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_25 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_25_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_25 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_26 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_26_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_26 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_27 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_27_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_27 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_28 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_28_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_28 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_29 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_29_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_29 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_30 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_30_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_30 Mask */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_31 Position */ +#define GPIO_GROUP_INT0_PORT_POL6_POL_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_31_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT0_PORT_POL7 ------------------------- */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_0 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_0_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_0 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_1 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_1_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_1 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_2 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_2_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_2 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_3 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_3_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_3 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_4 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_4_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_4 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_5 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_5_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_5 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_6 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_6_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_6 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_7 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_7_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_7 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_8 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_8_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_8 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_9 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_9_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_9 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_10 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_10_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_10 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_11 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_11_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_11 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_12 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_12_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_12 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_13 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_13_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_13 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_14 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_14_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_14 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_15 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_15_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_15 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_16 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_16_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_16 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_17 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_17_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_17 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_18 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_18_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_18 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_19 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_19_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_19 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_20 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_20_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_20 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_21 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_21_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_21 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_22 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_22_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_22 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_23 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_23_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_23 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_24 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_24_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_24 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_25 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_25_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_25 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_26 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_26_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_26 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_27 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_27_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_27 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_28 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_28_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_28 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_29 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_29_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_29 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_30 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_30_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_30 Mask */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_31 Position */ +#define GPIO_GROUP_INT0_PORT_POL7_POL_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_31_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT0_PORT_ENA0 ------------------------- */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_0 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_0_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_0 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_1 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_1_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_1 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_2 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_2_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_2 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_3 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_3_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_3 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_4 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_4_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_4 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_5 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_5_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_5 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_6 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_6_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_6 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_7 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_7_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_7 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_8 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_8_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_8 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_9 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_9_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_9 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_10 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_10_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_10 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_11 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_11_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_11 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_12 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_12_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_12 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_13 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_13_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_13 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_14 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_14_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_14 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_15 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_15_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_15 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_16 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_16_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_16 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_17 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_17_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_17 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_18 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_18_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_18 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_19 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_19_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_19 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_20 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_20_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_20 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_21 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_21_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_21 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_22 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_22_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_22 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_23 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_23_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_23 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_24 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_24_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_24 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_25 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_25_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_25 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_26 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_26_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_26 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_27 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_27_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_27 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_28 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_28_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_28 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_29 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_29_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_29 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_30 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_30_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_30 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_31 Position */ +#define GPIO_GROUP_INT0_PORT_ENA0_ENA_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_31_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT0_PORT_ENA1 ------------------------- */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_0 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_0_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_0 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_1 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_1_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_1 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_2 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_2_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_2 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_3 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_3_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_3 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_4 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_4_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_4 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_5 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_5_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_5 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_6 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_6_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_6 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_7 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_7_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_7 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_8 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_8_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_8 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_9 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_9_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_9 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_10 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_10_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_10 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_11 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_11_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_11 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_12 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_12_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_12 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_13 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_13_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_13 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_14 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_14_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_14 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_15 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_15_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_15 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_16 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_16_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_16 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_17 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_17_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_17 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_18 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_18_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_18 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_19 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_19_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_19 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_20 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_20_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_20 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_21 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_21_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_21 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_22 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_22_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_22 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_23 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_23_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_23 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_24 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_24_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_24 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_25 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_25_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_25 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_26 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_26_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_26 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_27 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_27_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_27 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_28 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_28_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_28 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_29 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_29_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_29 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_30 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_30_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_30 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_31 Position */ +#define GPIO_GROUP_INT0_PORT_ENA1_ENA_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_31_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT0_PORT_ENA2 ------------------------- */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_0 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_0_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_0 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_1 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_1_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_1 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_2 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_2_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_2 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_3 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_3_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_3 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_4 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_4_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_4 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_5 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_5_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_5 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_6 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_6_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_6 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_7 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_7_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_7 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_8 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_8_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_8 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_9 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_9_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_9 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_10 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_10_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_10 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_11 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_11_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_11 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_12 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_12_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_12 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_13 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_13_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_13 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_14 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_14_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_14 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_15 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_15_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_15 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_16 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_16_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_16 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_17 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_17_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_17 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_18 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_18_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_18 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_19 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_19_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_19 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_20 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_20_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_20 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_21 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_21_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_21 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_22 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_22_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_22 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_23 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_23_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_23 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_24 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_24_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_24 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_25 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_25_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_25 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_26 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_26_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_26 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_27 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_27_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_27 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_28 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_28_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_28 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_29 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_29_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_29 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_30 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_30_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_30 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_31 Position */ +#define GPIO_GROUP_INT0_PORT_ENA2_ENA_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_31_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT0_PORT_ENA3 ------------------------- */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_0 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_0_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_0 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_1 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_1_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_1 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_2 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_2_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_2 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_3 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_3_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_3 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_4 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_4_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_4 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_5 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_5_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_5 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_6 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_6_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_6 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_7 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_7_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_7 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_8 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_8_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_8 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_9 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_9_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_9 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_10 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_10_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_10 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_11 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_11_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_11 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_12 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_12_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_12 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_13 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_13_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_13 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_14 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_14_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_14 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_15 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_15_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_15 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_16 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_16_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_16 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_17 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_17_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_17 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_18 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_18_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_18 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_19 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_19_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_19 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_20 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_20_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_20 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_21 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_21_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_21 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_22 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_22_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_22 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_23 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_23_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_23 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_24 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_24_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_24 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_25 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_25_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_25 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_26 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_26_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_26 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_27 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_27_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_27 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_28 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_28_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_28 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_29 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_29_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_29 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_30 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_30_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_30 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_31 Position */ +#define GPIO_GROUP_INT0_PORT_ENA3_ENA_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_31_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT0_PORT_ENA4 ------------------------- */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_0 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_0_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_0 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_1 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_1_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_1 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_2 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_2_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_2 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_3 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_3_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_3 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_4 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_4_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_4 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_5 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_5_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_5 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_6 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_6_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_6 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_7 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_7_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_7 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_8 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_8_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_8 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_9 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_9_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_9 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_10 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_10_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_10 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_11 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_11_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_11 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_12 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_12_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_12 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_13 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_13_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_13 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_14 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_14_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_14 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_15 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_15_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_15 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_16 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_16_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_16 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_17 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_17_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_17 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_18 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_18_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_18 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_19 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_19_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_19 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_20 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_20_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_20 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_21 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_21_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_21 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_22 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_22_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_22 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_23 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_23_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_23 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_24 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_24_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_24 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_25 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_25_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_25 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_26 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_26_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_26 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_27 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_27_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_27 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_28 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_28_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_28 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_29 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_29_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_29 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_30 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_30_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_30 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_31 Position */ +#define GPIO_GROUP_INT0_PORT_ENA4_ENA_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_31_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT0_PORT_ENA5 ------------------------- */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_0 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_0_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_0 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_1 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_1_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_1 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_2 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_2_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_2 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_3 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_3_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_3 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_4 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_4_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_4 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_5 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_5_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_5 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_6 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_6_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_6 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_7 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_7_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_7 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_8 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_8_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_8 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_9 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_9_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_9 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_10 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_10_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_10 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_11 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_11_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_11 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_12 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_12_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_12 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_13 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_13_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_13 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_14 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_14_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_14 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_15 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_15_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_15 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_16 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_16_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_16 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_17 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_17_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_17 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_18 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_18_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_18 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_19 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_19_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_19 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_20 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_20_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_20 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_21 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_21_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_21 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_22 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_22_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_22 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_23 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_23_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_23 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_24 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_24_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_24 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_25 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_25_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_25 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_26 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_26_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_26 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_27 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_27_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_27 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_28 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_28_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_28 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_29 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_29_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_29 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_30 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_30_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_30 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_31 Position */ +#define GPIO_GROUP_INT0_PORT_ENA5_ENA_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_31_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT0_PORT_ENA6 ------------------------- */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_0 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_0_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_0 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_1 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_1_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_1 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_2 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_2_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_2 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_3 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_3_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_3 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_4 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_4_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_4 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_5 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_5_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_5 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_6 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_6_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_6 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_7 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_7_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_7 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_8 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_8_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_8 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_9 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_9_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_9 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_10 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_10_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_10 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_11 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_11_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_11 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_12 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_12_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_12 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_13 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_13_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_13 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_14 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_14_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_14 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_15 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_15_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_15 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_16 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_16_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_16 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_17 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_17_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_17 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_18 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_18_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_18 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_19 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_19_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_19 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_20 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_20_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_20 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_21 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_21_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_21 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_22 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_22_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_22 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_23 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_23_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_23 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_24 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_24_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_24 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_25 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_25_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_25 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_26 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_26_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_26 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_27 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_27_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_27 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_28 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_28_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_28 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_29 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_29_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_29 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_30 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_30_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_30 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_31 Position */ +#define GPIO_GROUP_INT0_PORT_ENA6_ENA_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_31_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT0_PORT_ENA7 ------------------------- */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_0 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_0_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_0 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_1 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_1_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_1 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_2 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_2_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_2 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_3 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_3_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_3 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_4 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_4_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_4 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_5 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_5_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_5 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_6 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_6_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_6 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_7 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_7_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_7 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_8 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_8_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_8 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_9 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_9_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_9 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_10 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_10_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_10 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_11 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_11_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_11 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_12 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_12_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_12 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_13 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_13_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_13 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_14 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_14_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_14 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_15 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_15_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_15 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_16 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_16_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_16 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_17 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_17_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_17 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_18 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_18_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_18 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_19 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_19_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_19 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_20 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_20_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_20 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_21 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_21_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_21 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_22 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_22_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_22 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_23 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_23_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_23 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_24 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_24_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_24 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_25 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_25_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_25 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_26 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_26_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_26 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_27 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_27_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_27 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_28 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_28_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_28 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_29 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_29_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_29 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_30 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_30_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_30 Mask */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_31 Position */ +#define GPIO_GROUP_INT0_PORT_ENA7_ENA_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_31_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_31 Mask */ + + +/* ================================================================================ */ +/* ================ struct 'GPIO_GROUP_INT1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------- GPIO_GROUP_INT1_CTRL ---------------------------- */ +#define GPIO_GROUP_INT1_CTRL_INT_Pos 0 /*!< GPIO_GROUP_INT1 CTRL: INT Position */ +#define GPIO_GROUP_INT1_CTRL_INT_Msk (0x01UL << GPIO_GROUP_INT1_CTRL_INT_Pos) /*!< GPIO_GROUP_INT1 CTRL: INT Mask */ +#define GPIO_GROUP_INT1_CTRL_COMB_Pos 1 /*!< GPIO_GROUP_INT1 CTRL: COMB Position */ +#define GPIO_GROUP_INT1_CTRL_COMB_Msk (0x01UL << GPIO_GROUP_INT1_CTRL_COMB_Pos) /*!< GPIO_GROUP_INT1 CTRL: COMB Mask */ +#define GPIO_GROUP_INT1_CTRL_TRIG_Pos 2 /*!< GPIO_GROUP_INT1 CTRL: TRIG Position */ +#define GPIO_GROUP_INT1_CTRL_TRIG_Msk (0x01UL << GPIO_GROUP_INT1_CTRL_TRIG_Pos) /*!< GPIO_GROUP_INT1 CTRL: TRIG Mask */ + +/* -------------------------- GPIO_GROUP_INT1_PORT_POL0 ------------------------- */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Mask */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Position */ +#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT1_PORT_POL1 ------------------------- */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Mask */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Position */ +#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT1_PORT_POL2 ------------------------- */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Mask */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Position */ +#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT1_PORT_POL3 ------------------------- */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Mask */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Position */ +#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT1_PORT_POL4 ------------------------- */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Mask */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Position */ +#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT1_PORT_POL5 ------------------------- */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Mask */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Position */ +#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT1_PORT_POL6 ------------------------- */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Mask */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Position */ +#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT1_PORT_POL7 ------------------------- */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Mask */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Position */ +#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT1_PORT_ENA0 ------------------------- */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_29 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_29 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_30 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_30 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_31 Position */ +#define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT1_PORT_ENA1 ------------------------- */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_0 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_0 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_1 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_1 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_2 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_2 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_3 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_3 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_4 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_4 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_5 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_5 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_6 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_6 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_7 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_7 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_8 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_8 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_9 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_9 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_10 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_10 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_11 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_11 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_12 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_12 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_13 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_13 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_14 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_14 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_15 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_15 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_16 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_16 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_17 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_17 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_18 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_18 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_19 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_19 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_20 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_20 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_21 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_21 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_22 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_22 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_23 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_23 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_24 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_24 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_25 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_25 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_26 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_26 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_27 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_27 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_28 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_28 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_29 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_29 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_30 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_30 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_31 Position */ +#define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT1_PORT_ENA2 ------------------------- */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_0 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_0 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_1 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_1 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_2 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_2 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_3 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_3 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_4 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_4 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_5 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_5 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_6 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_6 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_7 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_7 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_8 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_8 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_9 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_9 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_10 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_10 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_11 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_11 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_12 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_12 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_13 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_13 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_14 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_14 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_15 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_15 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_16 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_16 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_17 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_17 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_18 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_18 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_19 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_19 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_20 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_20 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_21 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_21 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_22 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_22 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_23 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_23 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_24 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_24 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_25 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_25 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_26 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_26 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_27 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_27 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_28 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_28 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_29 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_29 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_30 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_30 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_31 Position */ +#define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT1_PORT_ENA3 ------------------------- */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_0 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_0 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_1 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_1 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_2 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_2 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_3 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_3 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_4 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_4 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_5 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_5 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_6 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_6 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_7 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_7 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_8 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_8 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_9 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_9 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_10 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_10 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_11 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_11 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_12 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_12 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_13 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_13 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_14 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_14 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_15 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_15 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_16 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_16 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_17 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_17 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_18 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_18 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_19 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_19 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_20 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_20 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_21 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_21 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_22 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_22 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_23 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_23 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_24 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_24 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_25 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_25 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_26 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_26 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_27 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_27 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_28 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_28 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_29 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_29 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_30 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_30 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_31 Position */ +#define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT1_PORT_ENA4 ------------------------- */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_0 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_0 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_1 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_1 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_2 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_2 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_3 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_3 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_4 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_4 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_5 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_5 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_6 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_6 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_7 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_7 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_8 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_8 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_9 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_9 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_10 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_10 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_11 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_11 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_12 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_12 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_13 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_13 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_14 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_14 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_15 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_15 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_16 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_16 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_17 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_17 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_18 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_18 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_19 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_19 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_20 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_20 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_21 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_21 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_22 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_22 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_23 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_23 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_24 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_24 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_25 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_25 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_26 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_26 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_27 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_27 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_28 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_28 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_29 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_29 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_30 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_30 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_31 Position */ +#define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT1_PORT_ENA5 ------------------------- */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_0 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_0 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_1 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_1 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_2 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_2 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_3 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_3 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_4 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_4 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_5 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_5 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_6 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_6 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_7 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_7 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_8 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_8 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_9 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_9 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_10 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_10 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_11 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_11 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_12 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_12 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_13 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_13 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_14 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_14 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_15 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_15 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_16 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_16 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_17 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_17 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_18 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_18 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_19 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_19 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_20 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_20 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_21 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_21 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_22 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_22 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_23 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_23 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_24 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_24 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_25 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_25 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_26 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_26 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_27 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_27 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_28 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_28 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_29 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_29 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_30 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_30 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_31 Position */ +#define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT1_PORT_ENA6 ------------------------- */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_0 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_0 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_1 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_1 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_2 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_2 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_3 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_3 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_4 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_4 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_5 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_5 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_6 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_6 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_7 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_7 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_8 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_8 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_9 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_9 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_10 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_10 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_11 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_11 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_12 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_12 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_13 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_13 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_14 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_14 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_15 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_15 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_16 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_16 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_17 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_17 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_18 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_18 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_19 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_19 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_20 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_20 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_21 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_21 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_22 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_22 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_23 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_23 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_24 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_24 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_25 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_25 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_26 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_26 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_27 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_27 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_28 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_28 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_29 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_29 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_30 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_30 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_31 Position */ +#define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_31 Mask */ + +/* -------------------------- GPIO_GROUP_INT1_PORT_ENA7 ------------------------- */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_0 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_0 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_1 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_1 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_2 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_2 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_3 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_3 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_4 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_4 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_5 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_5 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_6 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_6 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_7 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_7 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_8 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_8 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_9 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_9 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_10 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_10 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_11 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_11 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_12 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_12 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_13 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_13 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_14 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_14 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_15 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_15 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_16 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_16 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_17 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_17 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_18 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_18 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_19 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_19 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_20 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_20 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_21 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_21 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_22 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_22 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_23 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_23 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_24 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_24 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_25 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_25 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_26 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_26 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_27 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_27 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_28 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_28 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_29 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_29 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_30 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_30 Mask */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_31 Position */ +#define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_31 Mask */ + + +/* ================================================================================ */ +/* ================ struct 'MCPWM' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- MCPWM_CON --------------------------------- */ +#define MCPWM_CON_RUN0_Pos 0 /*!< MCPWM CON: RUN0 Position */ +#define MCPWM_CON_RUN0_Msk (0x01UL << MCPWM_CON_RUN0_Pos) /*!< MCPWM CON: RUN0 Mask */ +#define MCPWM_CON_CENTER0_Pos 1 /*!< MCPWM CON: CENTER0 Position */ +#define MCPWM_CON_CENTER0_Msk (0x01UL << MCPWM_CON_CENTER0_Pos) /*!< MCPWM CON: CENTER0 Mask */ +#define MCPWM_CON_POLA0_Pos 2 /*!< MCPWM CON: POLA0 Position */ +#define MCPWM_CON_POLA0_Msk (0x01UL << MCPWM_CON_POLA0_Pos) /*!< MCPWM CON: POLA0 Mask */ +#define MCPWM_CON_DTE0_Pos 3 /*!< MCPWM CON: DTE0 Position */ +#define MCPWM_CON_DTE0_Msk (0x01UL << MCPWM_CON_DTE0_Pos) /*!< MCPWM CON: DTE0 Mask */ +#define MCPWM_CON_DISUP0_Pos 4 /*!< MCPWM CON: DISUP0 Position */ +#define MCPWM_CON_DISUP0_Msk (0x01UL << MCPWM_CON_DISUP0_Pos) /*!< MCPWM CON: DISUP0 Mask */ +#define MCPWM_CON_RUN1_Pos 8 /*!< MCPWM CON: RUN1 Position */ +#define MCPWM_CON_RUN1_Msk (0x01UL << MCPWM_CON_RUN1_Pos) /*!< MCPWM CON: RUN1 Mask */ +#define MCPWM_CON_CENTER1_Pos 9 /*!< MCPWM CON: CENTER1 Position */ +#define MCPWM_CON_CENTER1_Msk (0x01UL << MCPWM_CON_CENTER1_Pos) /*!< MCPWM CON: CENTER1 Mask */ +#define MCPWM_CON_POLA1_Pos 10 /*!< MCPWM CON: POLA1 Position */ +#define MCPWM_CON_POLA1_Msk (0x01UL << MCPWM_CON_POLA1_Pos) /*!< MCPWM CON: POLA1 Mask */ +#define MCPWM_CON_DTE1_Pos 11 /*!< MCPWM CON: DTE1 Position */ +#define MCPWM_CON_DTE1_Msk (0x01UL << MCPWM_CON_DTE1_Pos) /*!< MCPWM CON: DTE1 Mask */ +#define MCPWM_CON_DISUP1_Pos 12 /*!< MCPWM CON: DISUP1 Position */ +#define MCPWM_CON_DISUP1_Msk (0x01UL << MCPWM_CON_DISUP1_Pos) /*!< MCPWM CON: DISUP1 Mask */ +#define MCPWM_CON_RUN2_Pos 16 /*!< MCPWM CON: RUN2 Position */ +#define MCPWM_CON_RUN2_Msk (0x01UL << MCPWM_CON_RUN2_Pos) /*!< MCPWM CON: RUN2 Mask */ +#define MCPWM_CON_CENTER2_Pos 17 /*!< MCPWM CON: CENTER2 Position */ +#define MCPWM_CON_CENTER2_Msk (0x01UL << MCPWM_CON_CENTER2_Pos) /*!< MCPWM CON: CENTER2 Mask */ +#define MCPWM_CON_POLA2_Pos 18 /*!< MCPWM CON: POLA2 Position */ +#define MCPWM_CON_POLA2_Msk (0x01UL << MCPWM_CON_POLA2_Pos) /*!< MCPWM CON: POLA2 Mask */ +#define MCPWM_CON_DTE2_Pos 19 /*!< MCPWM CON: DTE2 Position */ +#define MCPWM_CON_DTE2_Msk (0x01UL << MCPWM_CON_DTE2_Pos) /*!< MCPWM CON: DTE2 Mask */ +#define MCPWM_CON_DISUP2_Pos 20 /*!< MCPWM CON: DISUP2 Position */ +#define MCPWM_CON_DISUP2_Msk (0x01UL << MCPWM_CON_DISUP2_Pos) /*!< MCPWM CON: DISUP2 Mask */ +#define MCPWM_CON_INVBDC_Pos 29 /*!< MCPWM CON: INVBDC Position */ +#define MCPWM_CON_INVBDC_Msk (0x01UL << MCPWM_CON_INVBDC_Pos) /*!< MCPWM CON: INVBDC Mask */ +#define MCPWM_CON_ACMODE_Pos 30 /*!< MCPWM CON: ACMODE Position */ +#define MCPWM_CON_ACMODE_Msk (0x01UL << MCPWM_CON_ACMODE_Pos) /*!< MCPWM CON: ACMODE Mask */ +#define MCPWM_CON_DCMODE_Pos 31 /*!< MCPWM CON: DCMODE Position */ +#define MCPWM_CON_DCMODE_Msk (0x01UL << MCPWM_CON_DCMODE_Pos) /*!< MCPWM CON: DCMODE Mask */ + +/* -------------------------------- MCPWM_CON_SET ------------------------------- */ +#define MCPWM_CON_SET_RUN0_SET_Pos 0 /*!< MCPWM CON_SET: RUN0_SET Position */ +#define MCPWM_CON_SET_RUN0_SET_Msk (0x01UL << MCPWM_CON_SET_RUN0_SET_Pos) /*!< MCPWM CON_SET: RUN0_SET Mask */ +#define MCPWM_CON_SET_CENTER0_SET_Pos 1 /*!< MCPWM CON_SET: CENTER0_SET Position */ +#define MCPWM_CON_SET_CENTER0_SET_Msk (0x01UL << MCPWM_CON_SET_CENTER0_SET_Pos) /*!< MCPWM CON_SET: CENTER0_SET Mask */ +#define MCPWM_CON_SET_POLA0_SET_Pos 2 /*!< MCPWM CON_SET: POLA0_SET Position */ +#define MCPWM_CON_SET_POLA0_SET_Msk (0x01UL << MCPWM_CON_SET_POLA0_SET_Pos) /*!< MCPWM CON_SET: POLA0_SET Mask */ +#define MCPWM_CON_SET_DTE0_SET_Pos 3 /*!< MCPWM CON_SET: DTE0_SET Position */ +#define MCPWM_CON_SET_DTE0_SET_Msk (0x01UL << MCPWM_CON_SET_DTE0_SET_Pos) /*!< MCPWM CON_SET: DTE0_SET Mask */ +#define MCPWM_CON_SET_DISUP0_SET_Pos 4 /*!< MCPWM CON_SET: DISUP0_SET Position */ +#define MCPWM_CON_SET_DISUP0_SET_Msk (0x01UL << MCPWM_CON_SET_DISUP0_SET_Pos) /*!< MCPWM CON_SET: DISUP0_SET Mask */ +#define MCPWM_CON_SET_RUN1_SET_Pos 8 /*!< MCPWM CON_SET: RUN1_SET Position */ +#define MCPWM_CON_SET_RUN1_SET_Msk (0x01UL << MCPWM_CON_SET_RUN1_SET_Pos) /*!< MCPWM CON_SET: RUN1_SET Mask */ +#define MCPWM_CON_SET_CENTER1_SET_Pos 9 /*!< MCPWM CON_SET: CENTER1_SET Position */ +#define MCPWM_CON_SET_CENTER1_SET_Msk (0x01UL << MCPWM_CON_SET_CENTER1_SET_Pos) /*!< MCPWM CON_SET: CENTER1_SET Mask */ +#define MCPWM_CON_SET_POLA1_SET_Pos 10 /*!< MCPWM CON_SET: POLA1_SET Position */ +#define MCPWM_CON_SET_POLA1_SET_Msk (0x01UL << MCPWM_CON_SET_POLA1_SET_Pos) /*!< MCPWM CON_SET: POLA1_SET Mask */ +#define MCPWM_CON_SET_DTE1_SET_Pos 11 /*!< MCPWM CON_SET: DTE1_SET Position */ +#define MCPWM_CON_SET_DTE1_SET_Msk (0x01UL << MCPWM_CON_SET_DTE1_SET_Pos) /*!< MCPWM CON_SET: DTE1_SET Mask */ +#define MCPWM_CON_SET_DISUP1_SET_Pos 12 /*!< MCPWM CON_SET: DISUP1_SET Position */ +#define MCPWM_CON_SET_DISUP1_SET_Msk (0x01UL << MCPWM_CON_SET_DISUP1_SET_Pos) /*!< MCPWM CON_SET: DISUP1_SET Mask */ +#define MCPWM_CON_SET_RUN2_SET_Pos 16 /*!< MCPWM CON_SET: RUN2_SET Position */ +#define MCPWM_CON_SET_RUN2_SET_Msk (0x01UL << MCPWM_CON_SET_RUN2_SET_Pos) /*!< MCPWM CON_SET: RUN2_SET Mask */ +#define MCPWM_CON_SET_CENTER2_SET_Pos 17 /*!< MCPWM CON_SET: CENTER2_SET Position */ +#define MCPWM_CON_SET_CENTER2_SET_Msk (0x01UL << MCPWM_CON_SET_CENTER2_SET_Pos) /*!< MCPWM CON_SET: CENTER2_SET Mask */ +#define MCPWM_CON_SET_POLA2_SET_Pos 18 /*!< MCPWM CON_SET: POLA2_SET Position */ +#define MCPWM_CON_SET_POLA2_SET_Msk (0x01UL << MCPWM_CON_SET_POLA2_SET_Pos) /*!< MCPWM CON_SET: POLA2_SET Mask */ +#define MCPWM_CON_SET_DTE2_SET_Pos 19 /*!< MCPWM CON_SET: DTE2_SET Position */ +#define MCPWM_CON_SET_DTE2_SET_Msk (0x01UL << MCPWM_CON_SET_DTE2_SET_Pos) /*!< MCPWM CON_SET: DTE2_SET Mask */ +#define MCPWM_CON_SET_DISUP2_SET_Pos 20 /*!< MCPWM CON_SET: DISUP2_SET Position */ +#define MCPWM_CON_SET_DISUP2_SET_Msk (0x01UL << MCPWM_CON_SET_DISUP2_SET_Pos) /*!< MCPWM CON_SET: DISUP2_SET Mask */ +#define MCPWM_CON_SET_INVBDC_SET_Pos 29 /*!< MCPWM CON_SET: INVBDC_SET Position */ +#define MCPWM_CON_SET_INVBDC_SET_Msk (0x01UL << MCPWM_CON_SET_INVBDC_SET_Pos) /*!< MCPWM CON_SET: INVBDC_SET Mask */ +#define MCPWM_CON_SET_ACMODE_SET_Pos 30 /*!< MCPWM CON_SET: ACMODE_SET Position */ +#define MCPWM_CON_SET_ACMODE_SET_Msk (0x01UL << MCPWM_CON_SET_ACMODE_SET_Pos) /*!< MCPWM CON_SET: ACMODE_SET Mask */ +#define MCPWM_CON_SET_DCMODE_SET_Pos 31 /*!< MCPWM CON_SET: DCMODE_SET Position */ +#define MCPWM_CON_SET_DCMODE_SET_Msk (0x01UL << MCPWM_CON_SET_DCMODE_SET_Pos) /*!< MCPWM CON_SET: DCMODE_SET Mask */ + +/* -------------------------------- MCPWM_CON_CLR ------------------------------- */ +#define MCPWM_CON_CLR_RUN0_CLR_Pos 0 /*!< MCPWM CON_CLR: RUN0_CLR Position */ +#define MCPWM_CON_CLR_RUN0_CLR_Msk (0x01UL << MCPWM_CON_CLR_RUN0_CLR_Pos) /*!< MCPWM CON_CLR: RUN0_CLR Mask */ +#define MCPWM_CON_CLR_CENTER0_CLR_Pos 1 /*!< MCPWM CON_CLR: CENTER0_CLR Position */ +#define MCPWM_CON_CLR_CENTER0_CLR_Msk (0x01UL << MCPWM_CON_CLR_CENTER0_CLR_Pos) /*!< MCPWM CON_CLR: CENTER0_CLR Mask */ +#define MCPWM_CON_CLR_POLA0_CLR_Pos 2 /*!< MCPWM CON_CLR: POLA0_CLR Position */ +#define MCPWM_CON_CLR_POLA0_CLR_Msk (0x01UL << MCPWM_CON_CLR_POLA0_CLR_Pos) /*!< MCPWM CON_CLR: POLA0_CLR Mask */ +#define MCPWM_CON_CLR_DTE0_CLR_Pos 3 /*!< MCPWM CON_CLR: DTE0_CLR Position */ +#define MCPWM_CON_CLR_DTE0_CLR_Msk (0x01UL << MCPWM_CON_CLR_DTE0_CLR_Pos) /*!< MCPWM CON_CLR: DTE0_CLR Mask */ +#define MCPWM_CON_CLR_DISUP0_CLR_Pos 4 /*!< MCPWM CON_CLR: DISUP0_CLR Position */ +#define MCPWM_CON_CLR_DISUP0_CLR_Msk (0x01UL << MCPWM_CON_CLR_DISUP0_CLR_Pos) /*!< MCPWM CON_CLR: DISUP0_CLR Mask */ +#define MCPWM_CON_CLR_RUN1_CLR_Pos 8 /*!< MCPWM CON_CLR: RUN1_CLR Position */ +#define MCPWM_CON_CLR_RUN1_CLR_Msk (0x01UL << MCPWM_CON_CLR_RUN1_CLR_Pos) /*!< MCPWM CON_CLR: RUN1_CLR Mask */ +#define MCPWM_CON_CLR_CENTER1_CLR_Pos 9 /*!< MCPWM CON_CLR: CENTER1_CLR Position */ +#define MCPWM_CON_CLR_CENTER1_CLR_Msk (0x01UL << MCPWM_CON_CLR_CENTER1_CLR_Pos) /*!< MCPWM CON_CLR: CENTER1_CLR Mask */ +#define MCPWM_CON_CLR_POLA1_CLR_Pos 10 /*!< MCPWM CON_CLR: POLA1_CLR Position */ +#define MCPWM_CON_CLR_POLA1_CLR_Msk (0x01UL << MCPWM_CON_CLR_POLA1_CLR_Pos) /*!< MCPWM CON_CLR: POLA1_CLR Mask */ +#define MCPWM_CON_CLR_DTE1_CLR_Pos 11 /*!< MCPWM CON_CLR: DTE1_CLR Position */ +#define MCPWM_CON_CLR_DTE1_CLR_Msk (0x01UL << MCPWM_CON_CLR_DTE1_CLR_Pos) /*!< MCPWM CON_CLR: DTE1_CLR Mask */ +#define MCPWM_CON_CLR_DISUP1_CLR_Pos 12 /*!< MCPWM CON_CLR: DISUP1_CLR Position */ +#define MCPWM_CON_CLR_DISUP1_CLR_Msk (0x01UL << MCPWM_CON_CLR_DISUP1_CLR_Pos) /*!< MCPWM CON_CLR: DISUP1_CLR Mask */ +#define MCPWM_CON_CLR_RUN2_CLR_Pos 16 /*!< MCPWM CON_CLR: RUN2_CLR Position */ +#define MCPWM_CON_CLR_RUN2_CLR_Msk (0x01UL << MCPWM_CON_CLR_RUN2_CLR_Pos) /*!< MCPWM CON_CLR: RUN2_CLR Mask */ +#define MCPWM_CON_CLR_CENTER2_CLR_Pos 17 /*!< MCPWM CON_CLR: CENTER2_CLR Position */ +#define MCPWM_CON_CLR_CENTER2_CLR_Msk (0x01UL << MCPWM_CON_CLR_CENTER2_CLR_Pos) /*!< MCPWM CON_CLR: CENTER2_CLR Mask */ +#define MCPWM_CON_CLR_POLA2_CLR_Pos 18 /*!< MCPWM CON_CLR: POLA2_CLR Position */ +#define MCPWM_CON_CLR_POLA2_CLR_Msk (0x01UL << MCPWM_CON_CLR_POLA2_CLR_Pos) /*!< MCPWM CON_CLR: POLA2_CLR Mask */ +#define MCPWM_CON_CLR_DTE2_CLR_Pos 19 /*!< MCPWM CON_CLR: DTE2_CLR Position */ +#define MCPWM_CON_CLR_DTE2_CLR_Msk (0x01UL << MCPWM_CON_CLR_DTE2_CLR_Pos) /*!< MCPWM CON_CLR: DTE2_CLR Mask */ +#define MCPWM_CON_CLR_DISUP2_CLR_Pos 20 /*!< MCPWM CON_CLR: DISUP2_CLR Position */ +#define MCPWM_CON_CLR_DISUP2_CLR_Msk (0x01UL << MCPWM_CON_CLR_DISUP2_CLR_Pos) /*!< MCPWM CON_CLR: DISUP2_CLR Mask */ +#define MCPWM_CON_CLR_INVBDC_CLR_Pos 29 /*!< MCPWM CON_CLR: INVBDC_CLR Position */ +#define MCPWM_CON_CLR_INVBDC_CLR_Msk (0x01UL << MCPWM_CON_CLR_INVBDC_CLR_Pos) /*!< MCPWM CON_CLR: INVBDC_CLR Mask */ +#define MCPWM_CON_CLR_ACMOD_CLR_Pos 30 /*!< MCPWM CON_CLR: ACMOD_CLR Position */ +#define MCPWM_CON_CLR_ACMOD_CLR_Msk (0x01UL << MCPWM_CON_CLR_ACMOD_CLR_Pos) /*!< MCPWM CON_CLR: ACMOD_CLR Mask */ +#define MCPWM_CON_CLR_DCMODE_CLR_Pos 31 /*!< MCPWM CON_CLR: DCMODE_CLR Position */ +#define MCPWM_CON_CLR_DCMODE_CLR_Msk (0x01UL << MCPWM_CON_CLR_DCMODE_CLR_Pos) /*!< MCPWM CON_CLR: DCMODE_CLR Mask */ + +/* -------------------------------- MCPWM_CAPCON -------------------------------- */ +#define MCPWM_CAPCON_CAP0MCI0_RE_Pos 0 /*!< MCPWM CAPCON: CAP0MCI0_RE Position */ +#define MCPWM_CAPCON_CAP0MCI0_RE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI0_RE_Pos) /*!< MCPWM CAPCON: CAP0MCI0_RE Mask */ +#define MCPWM_CAPCON_CAP0MCI0_FE_Pos 1 /*!< MCPWM CAPCON: CAP0MCI0_FE Position */ +#define MCPWM_CAPCON_CAP0MCI0_FE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI0_FE_Pos) /*!< MCPWM CAPCON: CAP0MCI0_FE Mask */ +#define MCPWM_CAPCON_CAP0MCI1_RE_Pos 2 /*!< MCPWM CAPCON: CAP0MCI1_RE Position */ +#define MCPWM_CAPCON_CAP0MCI1_RE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI1_RE_Pos) /*!< MCPWM CAPCON: CAP0MCI1_RE Mask */ +#define MCPWM_CAPCON_CAP0MCI1_FE_Pos 3 /*!< MCPWM CAPCON: CAP0MCI1_FE Position */ +#define MCPWM_CAPCON_CAP0MCI1_FE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI1_FE_Pos) /*!< MCPWM CAPCON: CAP0MCI1_FE Mask */ +#define MCPWM_CAPCON_CAP0MCI2_RE_Pos 4 /*!< MCPWM CAPCON: CAP0MCI2_RE Position */ +#define MCPWM_CAPCON_CAP0MCI2_RE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI2_RE_Pos) /*!< MCPWM CAPCON: CAP0MCI2_RE Mask */ +#define MCPWM_CAPCON_CAP0MCI2_FE_Pos 5 /*!< MCPWM CAPCON: CAP0MCI2_FE Position */ +#define MCPWM_CAPCON_CAP0MCI2_FE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI2_FE_Pos) /*!< MCPWM CAPCON: CAP0MCI2_FE Mask */ +#define MCPWM_CAPCON_CAP1MCI0_RE_Pos 6 /*!< MCPWM CAPCON: CAP1MCI0_RE Position */ +#define MCPWM_CAPCON_CAP1MCI0_RE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI0_RE_Pos) /*!< MCPWM CAPCON: CAP1MCI0_RE Mask */ +#define MCPWM_CAPCON_CAP1MCI0_FE_Pos 7 /*!< MCPWM CAPCON: CAP1MCI0_FE Position */ +#define MCPWM_CAPCON_CAP1MCI0_FE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI0_FE_Pos) /*!< MCPWM CAPCON: CAP1MCI0_FE Mask */ +#define MCPWM_CAPCON_CAP1MCI1_RE_Pos 8 /*!< MCPWM CAPCON: CAP1MCI1_RE Position */ +#define MCPWM_CAPCON_CAP1MCI1_RE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI1_RE_Pos) /*!< MCPWM CAPCON: CAP1MCI1_RE Mask */ +#define MCPWM_CAPCON_CAP1MCI1_FE_Pos 9 /*!< MCPWM CAPCON: CAP1MCI1_FE Position */ +#define MCPWM_CAPCON_CAP1MCI1_FE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI1_FE_Pos) /*!< MCPWM CAPCON: CAP1MCI1_FE Mask */ +#define MCPWM_CAPCON_CAP1MCI2_RE_Pos 10 /*!< MCPWM CAPCON: CAP1MCI2_RE Position */ +#define MCPWM_CAPCON_CAP1MCI2_RE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI2_RE_Pos) /*!< MCPWM CAPCON: CAP1MCI2_RE Mask */ +#define MCPWM_CAPCON_CAP1MCI2_FE_Pos 11 /*!< MCPWM CAPCON: CAP1MCI2_FE Position */ +#define MCPWM_CAPCON_CAP1MCI2_FE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI2_FE_Pos) /*!< MCPWM CAPCON: CAP1MCI2_FE Mask */ +#define MCPWM_CAPCON_CAP2MCI0_RE_Pos 12 /*!< MCPWM CAPCON: CAP2MCI0_RE Position */ +#define MCPWM_CAPCON_CAP2MCI0_RE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI0_RE_Pos) /*!< MCPWM CAPCON: CAP2MCI0_RE Mask */ +#define MCPWM_CAPCON_CAP2MCI0_FE_Pos 13 /*!< MCPWM CAPCON: CAP2MCI0_FE Position */ +#define MCPWM_CAPCON_CAP2MCI0_FE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI0_FE_Pos) /*!< MCPWM CAPCON: CAP2MCI0_FE Mask */ +#define MCPWM_CAPCON_CAP2MCI1_RE_Pos 14 /*!< MCPWM CAPCON: CAP2MCI1_RE Position */ +#define MCPWM_CAPCON_CAP2MCI1_RE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI1_RE_Pos) /*!< MCPWM CAPCON: CAP2MCI1_RE Mask */ +#define MCPWM_CAPCON_CAP2MCI1_FE_Pos 15 /*!< MCPWM CAPCON: CAP2MCI1_FE Position */ +#define MCPWM_CAPCON_CAP2MCI1_FE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI1_FE_Pos) /*!< MCPWM CAPCON: CAP2MCI1_FE Mask */ +#define MCPWM_CAPCON_CAP2MCI2_RE_Pos 16 /*!< MCPWM CAPCON: CAP2MCI2_RE Position */ +#define MCPWM_CAPCON_CAP2MCI2_RE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI2_RE_Pos) /*!< MCPWM CAPCON: CAP2MCI2_RE Mask */ +#define MCPWM_CAPCON_CAP2MCI2_FE_Pos 17 /*!< MCPWM CAPCON: CAP2MCI2_FE Position */ +#define MCPWM_CAPCON_CAP2MCI2_FE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI2_FE_Pos) /*!< MCPWM CAPCON: CAP2MCI2_FE Mask */ +#define MCPWM_CAPCON_RT0_Pos 18 /*!< MCPWM CAPCON: RT0 Position */ +#define MCPWM_CAPCON_RT0_Msk (0x01UL << MCPWM_CAPCON_RT0_Pos) /*!< MCPWM CAPCON: RT0 Mask */ +#define MCPWM_CAPCON_RT1_Pos 19 /*!< MCPWM CAPCON: RT1 Position */ +#define MCPWM_CAPCON_RT1_Msk (0x01UL << MCPWM_CAPCON_RT1_Pos) /*!< MCPWM CAPCON: RT1 Mask */ +#define MCPWM_CAPCON_RT2_Pos 20 /*!< MCPWM CAPCON: RT2 Position */ +#define MCPWM_CAPCON_RT2_Msk (0x01UL << MCPWM_CAPCON_RT2_Pos) /*!< MCPWM CAPCON: RT2 Mask */ + +/* ------------------------------ MCPWM_CAPCON_SET ------------------------------ */ +#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos 0 /*!< MCPWM CAPCON_SET: CAP0MCI0_RE_SET Position */ +#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI0_RE_SET Mask */ +#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos 1 /*!< MCPWM CAPCON_SET: CAP0MCI0_FE_SET Position */ +#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI0_FE_SET Mask */ +#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos 2 /*!< MCPWM CAPCON_SET: CAP0MCI1_RE_SET Position */ +#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI1_RE_SET Mask */ +#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos 3 /*!< MCPWM CAPCON_SET: CAP0MCI1_FE_SET Position */ +#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI1_FE_SET Mask */ +#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos 4 /*!< MCPWM CAPCON_SET: CAP0MCI2_RE_SET Position */ +#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI2_RE_SET Mask */ +#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos 5 /*!< MCPWM CAPCON_SET: CAP0MCI2_FE_SET Position */ +#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI2_FE_SET Mask */ +#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos 6 /*!< MCPWM CAPCON_SET: CAP1MCI0_RE_SET Position */ +#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI0_RE_SET Mask */ +#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos 7 /*!< MCPWM CAPCON_SET: CAP1MCI0_FE_SET Position */ +#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI0_FE_SET Mask */ +#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos 8 /*!< MCPWM CAPCON_SET: CAP1MCI1_RE_SET Position */ +#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI1_RE_SET Mask */ +#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos 9 /*!< MCPWM CAPCON_SET: CAP1MCI1_FE_SET Position */ +#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI1_FE_SET Mask */ +#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos 10 /*!< MCPWM CAPCON_SET: CAP1MCI2_RE_SET Position */ +#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI2_RE_SET Mask */ +#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos 11 /*!< MCPWM CAPCON_SET: CAP1MCI2_FE_SET Position */ +#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI2_FE_SET Mask */ +#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos 12 /*!< MCPWM CAPCON_SET: CAP2MCI0_RE_SET Position */ +#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI0_RE_SET Mask */ +#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos 13 /*!< MCPWM CAPCON_SET: CAP2MCI0_FE_SET Position */ +#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI0_FE_SET Mask */ +#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos 14 /*!< MCPWM CAPCON_SET: CAP2MCI1_RE_SET Position */ +#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI1_RE_SET Mask */ +#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos 15 /*!< MCPWM CAPCON_SET: CAP2MCI1_FE_SET Position */ +#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI1_FE_SET Mask */ +#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos 16 /*!< MCPWM CAPCON_SET: CAP2MCI2_RE_SET Position */ +#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI2_RE_SET Mask */ +#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos 17 /*!< MCPWM CAPCON_SET: CAP2MCI2_FE_SET Position */ +#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI2_FE_SET Mask */ +#define MCPWM_CAPCON_SET_RT0_SET_Pos 18 /*!< MCPWM CAPCON_SET: RT0_SET Position */ +#define MCPWM_CAPCON_SET_RT0_SET_Msk (0x01UL << MCPWM_CAPCON_SET_RT0_SET_Pos) /*!< MCPWM CAPCON_SET: RT0_SET Mask */ +#define MCPWM_CAPCON_SET_RT1_SET_Pos 19 /*!< MCPWM CAPCON_SET: RT1_SET Position */ +#define MCPWM_CAPCON_SET_RT1_SET_Msk (0x01UL << MCPWM_CAPCON_SET_RT1_SET_Pos) /*!< MCPWM CAPCON_SET: RT1_SET Mask */ +#define MCPWM_CAPCON_SET_RT2_SET_Pos 20 /*!< MCPWM CAPCON_SET: RT2_SET Position */ +#define MCPWM_CAPCON_SET_RT2_SET_Msk (0x01UL << MCPWM_CAPCON_SET_RT2_SET_Pos) /*!< MCPWM CAPCON_SET: RT2_SET Mask */ + +/* ------------------------------ MCPWM_CAPCON_CLR ------------------------------ */ +#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos 0 /*!< MCPWM CAPCON_CLR: CAP0MCI0_RE_CLR Position */ +#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI0_RE_CLR Mask */ +#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos 1 /*!< MCPWM CAPCON_CLR: CAP0MCI0_FE_CLR Position */ +#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI0_FE_CLR Mask */ +#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos 2 /*!< MCPWM CAPCON_CLR: CAP0MCI1_RE_CLR Position */ +#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI1_RE_CLR Mask */ +#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos 3 /*!< MCPWM CAPCON_CLR: CAP0MCI1_FE_CLR Position */ +#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI1_FE_CLR Mask */ +#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos 4 /*!< MCPWM CAPCON_CLR: CAP0MCI2_RE_CLR Position */ +#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI2_RE_CLR Mask */ +#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos 5 /*!< MCPWM CAPCON_CLR: CAP0MCI2_FE_CLR Position */ +#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI2_FE_CLR Mask */ +#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos 6 /*!< MCPWM CAPCON_CLR: CAP1MCI0_RE_CLR Position */ +#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI0_RE_CLR Mask */ +#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos 7 /*!< MCPWM CAPCON_CLR: CAP1MCI0_FE_CLR Position */ +#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI0_FE_CLR Mask */ +#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos 8 /*!< MCPWM CAPCON_CLR: CAP1MCI1_RE_CLR Position */ +#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI1_RE_CLR Mask */ +#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos 9 /*!< MCPWM CAPCON_CLR: CAP1MCI1_FE_CLR Position */ +#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI1_FE_CLR Mask */ +#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos 10 /*!< MCPWM CAPCON_CLR: CAP1MCI2_RE_CLR Position */ +#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI2_RE_CLR Mask */ +#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos 11 /*!< MCPWM CAPCON_CLR: CAP1MCI2_FE_CLR Position */ +#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI2_FE_CLR Mask */ +#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos 12 /*!< MCPWM CAPCON_CLR: CAP2MCI0_RE_CLR Position */ +#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI0_RE_CLR Mask */ +#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos 13 /*!< MCPWM CAPCON_CLR: CAP2MCI0_FE_CLR Position */ +#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI0_FE_CLR Mask */ +#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos 14 /*!< MCPWM CAPCON_CLR: CAP2MCI1_RE_CLR Position */ +#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI1_RE_CLR Mask */ +#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos 15 /*!< MCPWM CAPCON_CLR: CAP2MCI1_FE_CLR Position */ +#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI1_FE_CLR Mask */ +#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos 16 /*!< MCPWM CAPCON_CLR: CAP2MCI2_RE_CLR Position */ +#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI2_RE_CLR Mask */ +#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos 17 /*!< MCPWM CAPCON_CLR: CAP2MCI2_FE_CLR Position */ +#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI2_FE_CLR Mask */ +#define MCPWM_CAPCON_CLR_RT0_CLR_Pos 18 /*!< MCPWM CAPCON_CLR: RT0_CLR Position */ +#define MCPWM_CAPCON_CLR_RT0_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_RT0_CLR_Pos) /*!< MCPWM CAPCON_CLR: RT0_CLR Mask */ +#define MCPWM_CAPCON_CLR_RT1_CLR_Pos 19 /*!< MCPWM CAPCON_CLR: RT1_CLR Position */ +#define MCPWM_CAPCON_CLR_RT1_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_RT1_CLR_Pos) /*!< MCPWM CAPCON_CLR: RT1_CLR Mask */ +#define MCPWM_CAPCON_CLR_RT2_CLR_Pos 20 /*!< MCPWM CAPCON_CLR: RT2_CLR Position */ +#define MCPWM_CAPCON_CLR_RT2_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_RT2_CLR_Pos) /*!< MCPWM CAPCON_CLR: RT2_CLR Mask */ + +/* ---------------------------------- MCPWM_TC0 --------------------------------- */ +#define MCPWM_TC0_MCTC_Pos 0 /*!< MCPWM TC0: MCTC Position */ +#define MCPWM_TC0_MCTC_Msk (0xffffffffUL << MCPWM_TC0_MCTC_Pos) /*!< MCPWM TC0: MCTC Mask */ + +/* ---------------------------------- MCPWM_TC1 --------------------------------- */ +#define MCPWM_TC1_MCTC_Pos 0 /*!< MCPWM TC1: MCTC Position */ +#define MCPWM_TC1_MCTC_Msk (0xffffffffUL << MCPWM_TC1_MCTC_Pos) /*!< MCPWM TC1: MCTC Mask */ + +/* ---------------------------------- MCPWM_TC2 --------------------------------- */ +#define MCPWM_TC2_MCTC_Pos 0 /*!< MCPWM TC2: MCTC Position */ +#define MCPWM_TC2_MCTC_Msk (0xffffffffUL << MCPWM_TC2_MCTC_Pos) /*!< MCPWM TC2: MCTC Mask */ + +/* --------------------------------- MCPWM_LIM0 --------------------------------- */ +#define MCPWM_LIM0_MCLIM_Pos 0 /*!< MCPWM LIM0: MCLIM Position */ +#define MCPWM_LIM0_MCLIM_Msk (0xffffffffUL << MCPWM_LIM0_MCLIM_Pos) /*!< MCPWM LIM0: MCLIM Mask */ + +/* --------------------------------- MCPWM_LIM1 --------------------------------- */ +#define MCPWM_LIM1_MCLIM_Pos 0 /*!< MCPWM LIM1: MCLIM Position */ +#define MCPWM_LIM1_MCLIM_Msk (0xffffffffUL << MCPWM_LIM1_MCLIM_Pos) /*!< MCPWM LIM1: MCLIM Mask */ + +/* --------------------------------- MCPWM_LIM2 --------------------------------- */ +#define MCPWM_LIM2_MCLIM_Pos 0 /*!< MCPWM LIM2: MCLIM Position */ +#define MCPWM_LIM2_MCLIM_Msk (0xffffffffUL << MCPWM_LIM2_MCLIM_Pos) /*!< MCPWM LIM2: MCLIM Mask */ + +/* --------------------------------- MCPWM_MAT0 --------------------------------- */ +#define MCPWM_MAT0_MCMAT_Pos 0 /*!< MCPWM MAT0: MCMAT Position */ +#define MCPWM_MAT0_MCMAT_Msk (0xffffffffUL << MCPWM_MAT0_MCMAT_Pos) /*!< MCPWM MAT0: MCMAT Mask */ + +/* --------------------------------- MCPWM_MAT1 --------------------------------- */ +#define MCPWM_MAT1_MCMAT_Pos 0 /*!< MCPWM MAT1: MCMAT Position */ +#define MCPWM_MAT1_MCMAT_Msk (0xffffffffUL << MCPWM_MAT1_MCMAT_Pos) /*!< MCPWM MAT1: MCMAT Mask */ + +/* --------------------------------- MCPWM_MAT2 --------------------------------- */ +#define MCPWM_MAT2_MCMAT_Pos 0 /*!< MCPWM MAT2: MCMAT Position */ +#define MCPWM_MAT2_MCMAT_Msk (0xffffffffUL << MCPWM_MAT2_MCMAT_Pos) /*!< MCPWM MAT2: MCMAT Mask */ + +/* ---------------------------------- MCPWM_DT ---------------------------------- */ +#define MCPWM_DT_DT0_Pos 0 /*!< MCPWM DT: DT0 Position */ +#define MCPWM_DT_DT0_Msk (0x000003ffUL << MCPWM_DT_DT0_Pos) /*!< MCPWM DT: DT0 Mask */ +#define MCPWM_DT_DT1_Pos 10 /*!< MCPWM DT: DT1 Position */ +#define MCPWM_DT_DT1_Msk (0x000003ffUL << MCPWM_DT_DT1_Pos) /*!< MCPWM DT: DT1 Mask */ +#define MCPWM_DT_DT2_Pos 20 /*!< MCPWM DT: DT2 Position */ +#define MCPWM_DT_DT2_Msk (0x000003ffUL << MCPWM_DT_DT2_Pos) /*!< MCPWM DT: DT2 Mask */ + +/* ---------------------------------- MCPWM_CCP --------------------------------- */ +#define MCPWM_CCP_CCPA0_Pos 0 /*!< MCPWM CCP: CCPA0 Position */ +#define MCPWM_CCP_CCPA0_Msk (0x01UL << MCPWM_CCP_CCPA0_Pos) /*!< MCPWM CCP: CCPA0 Mask */ +#define MCPWM_CCP_CCPB0_Pos 1 /*!< MCPWM CCP: CCPB0 Position */ +#define MCPWM_CCP_CCPB0_Msk (0x01UL << MCPWM_CCP_CCPB0_Pos) /*!< MCPWM CCP: CCPB0 Mask */ +#define MCPWM_CCP_CCPA1_Pos 2 /*!< MCPWM CCP: CCPA1 Position */ +#define MCPWM_CCP_CCPA1_Msk (0x01UL << MCPWM_CCP_CCPA1_Pos) /*!< MCPWM CCP: CCPA1 Mask */ +#define MCPWM_CCP_CCPB1_Pos 3 /*!< MCPWM CCP: CCPB1 Position */ +#define MCPWM_CCP_CCPB1_Msk (0x01UL << MCPWM_CCP_CCPB1_Pos) /*!< MCPWM CCP: CCPB1 Mask */ +#define MCPWM_CCP_CCPA2_Pos 4 /*!< MCPWM CCP: CCPA2 Position */ +#define MCPWM_CCP_CCPA2_Msk (0x01UL << MCPWM_CCP_CCPA2_Pos) /*!< MCPWM CCP: CCPA2 Mask */ +#define MCPWM_CCP_CCPB2_Pos 5 /*!< MCPWM CCP: CCPB2 Position */ +#define MCPWM_CCP_CCPB2_Msk (0x01UL << MCPWM_CCP_CCPB2_Pos) /*!< MCPWM CCP: CCPB2 Mask */ + +/* --------------------------------- MCPWM_CAP0 --------------------------------- */ +#define MCPWM_CAP0_CAP_Pos 0 /*!< MCPWM CAP0: CAP Position */ +#define MCPWM_CAP0_CAP_Msk (0xffffffffUL << MCPWM_CAP0_CAP_Pos) /*!< MCPWM CAP0: CAP Mask */ + +/* --------------------------------- MCPWM_CAP1 --------------------------------- */ +#define MCPWM_CAP1_CAP_Pos 0 /*!< MCPWM CAP1: CAP Position */ +#define MCPWM_CAP1_CAP_Msk (0xffffffffUL << MCPWM_CAP1_CAP_Pos) /*!< MCPWM CAP1: CAP Mask */ + +/* --------------------------------- MCPWM_CAP2 --------------------------------- */ +#define MCPWM_CAP2_CAP_Pos 0 /*!< MCPWM CAP2: CAP Position */ +#define MCPWM_CAP2_CAP_Msk (0xffffffffUL << MCPWM_CAP2_CAP_Pos) /*!< MCPWM CAP2: CAP Mask */ + +/* --------------------------------- MCPWM_INTEN -------------------------------- */ +#define MCPWM_INTEN_ILIM0_Pos 0 /*!< MCPWM INTEN: ILIM0 Position */ +#define MCPWM_INTEN_ILIM0_Msk (0x01UL << MCPWM_INTEN_ILIM0_Pos) /*!< MCPWM INTEN: ILIM0 Mask */ +#define MCPWM_INTEN_IMAT0_Pos 1 /*!< MCPWM INTEN: IMAT0 Position */ +#define MCPWM_INTEN_IMAT0_Msk (0x01UL << MCPWM_INTEN_IMAT0_Pos) /*!< MCPWM INTEN: IMAT0 Mask */ +#define MCPWM_INTEN_ICAP0_Pos 2 /*!< MCPWM INTEN: ICAP0 Position */ +#define MCPWM_INTEN_ICAP0_Msk (0x01UL << MCPWM_INTEN_ICAP0_Pos) /*!< MCPWM INTEN: ICAP0 Mask */ +#define MCPWM_INTEN_ILIM1_Pos 4 /*!< MCPWM INTEN: ILIM1 Position */ +#define MCPWM_INTEN_ILIM1_Msk (0x01UL << MCPWM_INTEN_ILIM1_Pos) /*!< MCPWM INTEN: ILIM1 Mask */ +#define MCPWM_INTEN_IMAT1_Pos 5 /*!< MCPWM INTEN: IMAT1 Position */ +#define MCPWM_INTEN_IMAT1_Msk (0x01UL << MCPWM_INTEN_IMAT1_Pos) /*!< MCPWM INTEN: IMAT1 Mask */ +#define MCPWM_INTEN_ICAP1_Pos 6 /*!< MCPWM INTEN: ICAP1 Position */ +#define MCPWM_INTEN_ICAP1_Msk (0x01UL << MCPWM_INTEN_ICAP1_Pos) /*!< MCPWM INTEN: ICAP1 Mask */ +#define MCPWM_INTEN_ILIM2_Pos 8 /*!< MCPWM INTEN: ILIM2 Position */ +#define MCPWM_INTEN_ILIM2_Msk (0x01UL << MCPWM_INTEN_ILIM2_Pos) /*!< MCPWM INTEN: ILIM2 Mask */ +#define MCPWM_INTEN_IMAT2_Pos 9 /*!< MCPWM INTEN: IMAT2 Position */ +#define MCPWM_INTEN_IMAT2_Msk (0x01UL << MCPWM_INTEN_IMAT2_Pos) /*!< MCPWM INTEN: IMAT2 Mask */ +#define MCPWM_INTEN_ICAP2_Pos 10 /*!< MCPWM INTEN: ICAP2 Position */ +#define MCPWM_INTEN_ICAP2_Msk (0x01UL << MCPWM_INTEN_ICAP2_Pos) /*!< MCPWM INTEN: ICAP2 Mask */ +#define MCPWM_INTEN_ABORT_Pos 15 /*!< MCPWM INTEN: ABORT Position */ +#define MCPWM_INTEN_ABORT_Msk (0x01UL << MCPWM_INTEN_ABORT_Pos) /*!< MCPWM INTEN: ABORT Mask */ + +/* ------------------------------- MCPWM_INTEN_SET ------------------------------ */ +#define MCPWM_INTEN_SET_ILIM0_SET_Pos 0 /*!< MCPWM INTEN_SET: ILIM0_SET Position */ +#define MCPWM_INTEN_SET_ILIM0_SET_Msk (0x01UL << MCPWM_INTEN_SET_ILIM0_SET_Pos) /*!< MCPWM INTEN_SET: ILIM0_SET Mask */ +#define MCPWM_INTEN_SET_IMAT0_SET_Pos 1 /*!< MCPWM INTEN_SET: IMAT0_SET Position */ +#define MCPWM_INTEN_SET_IMAT0_SET_Msk (0x01UL << MCPWM_INTEN_SET_IMAT0_SET_Pos) /*!< MCPWM INTEN_SET: IMAT0_SET Mask */ +#define MCPWM_INTEN_SET_ICAP0_SET_Pos 2 /*!< MCPWM INTEN_SET: ICAP0_SET Position */ +#define MCPWM_INTEN_SET_ICAP0_SET_Msk (0x01UL << MCPWM_INTEN_SET_ICAP0_SET_Pos) /*!< MCPWM INTEN_SET: ICAP0_SET Mask */ +#define MCPWM_INTEN_SET_ILIM1_SET_Pos 4 /*!< MCPWM INTEN_SET: ILIM1_SET Position */ +#define MCPWM_INTEN_SET_ILIM1_SET_Msk (0x01UL << MCPWM_INTEN_SET_ILIM1_SET_Pos) /*!< MCPWM INTEN_SET: ILIM1_SET Mask */ +#define MCPWM_INTEN_SET_IMAT1_SET_Pos 5 /*!< MCPWM INTEN_SET: IMAT1_SET Position */ +#define MCPWM_INTEN_SET_IMAT1_SET_Msk (0x01UL << MCPWM_INTEN_SET_IMAT1_SET_Pos) /*!< MCPWM INTEN_SET: IMAT1_SET Mask */ +#define MCPWM_INTEN_SET_ICAP1_SET_Pos 6 /*!< MCPWM INTEN_SET: ICAP1_SET Position */ +#define MCPWM_INTEN_SET_ICAP1_SET_Msk (0x01UL << MCPWM_INTEN_SET_ICAP1_SET_Pos) /*!< MCPWM INTEN_SET: ICAP1_SET Mask */ +#define MCPWM_INTEN_SET_ILIM2_SET_Pos 9 /*!< MCPWM INTEN_SET: ILIM2_SET Position */ +#define MCPWM_INTEN_SET_ILIM2_SET_Msk (0x01UL << MCPWM_INTEN_SET_ILIM2_SET_Pos) /*!< MCPWM INTEN_SET: ILIM2_SET Mask */ +#define MCPWM_INTEN_SET_IMAT2_SET_Pos 10 /*!< MCPWM INTEN_SET: IMAT2_SET Position */ +#define MCPWM_INTEN_SET_IMAT2_SET_Msk (0x01UL << MCPWM_INTEN_SET_IMAT2_SET_Pos) /*!< MCPWM INTEN_SET: IMAT2_SET Mask */ +#define MCPWM_INTEN_SET_ICAP2_SET_Pos 11 /*!< MCPWM INTEN_SET: ICAP2_SET Position */ +#define MCPWM_INTEN_SET_ICAP2_SET_Msk (0x01UL << MCPWM_INTEN_SET_ICAP2_SET_Pos) /*!< MCPWM INTEN_SET: ICAP2_SET Mask */ +#define MCPWM_INTEN_SET_ABORT_SET_Pos 15 /*!< MCPWM INTEN_SET: ABORT_SET Position */ +#define MCPWM_INTEN_SET_ABORT_SET_Msk (0x01UL << MCPWM_INTEN_SET_ABORT_SET_Pos) /*!< MCPWM INTEN_SET: ABORT_SET Mask */ + +/* ------------------------------- MCPWM_INTEN_CLR ------------------------------ */ +#define MCPWM_INTEN_CLR_ILIM0_CLR_Pos 0 /*!< MCPWM INTEN_CLR: ILIM0_CLR Position */ +#define MCPWM_INTEN_CLR_ILIM0_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ILIM0_CLR_Pos) /*!< MCPWM INTEN_CLR: ILIM0_CLR Mask */ +#define MCPWM_INTEN_CLR_IMAT0_CLR_Pos 1 /*!< MCPWM INTEN_CLR: IMAT0_CLR Position */ +#define MCPWM_INTEN_CLR_IMAT0_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_IMAT0_CLR_Pos) /*!< MCPWM INTEN_CLR: IMAT0_CLR Mask */ +#define MCPWM_INTEN_CLR_ICAP0_CLR_Pos 2 /*!< MCPWM INTEN_CLR: ICAP0_CLR Position */ +#define MCPWM_INTEN_CLR_ICAP0_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ICAP0_CLR_Pos) /*!< MCPWM INTEN_CLR: ICAP0_CLR Mask */ +#define MCPWM_INTEN_CLR_ILIM1_CLR_Pos 4 /*!< MCPWM INTEN_CLR: ILIM1_CLR Position */ +#define MCPWM_INTEN_CLR_ILIM1_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ILIM1_CLR_Pos) /*!< MCPWM INTEN_CLR: ILIM1_CLR Mask */ +#define MCPWM_INTEN_CLR_IMAT1_CLR_Pos 5 /*!< MCPWM INTEN_CLR: IMAT1_CLR Position */ +#define MCPWM_INTEN_CLR_IMAT1_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_IMAT1_CLR_Pos) /*!< MCPWM INTEN_CLR: IMAT1_CLR Mask */ +#define MCPWM_INTEN_CLR_ICAP1_CLR_Pos 6 /*!< MCPWM INTEN_CLR: ICAP1_CLR Position */ +#define MCPWM_INTEN_CLR_ICAP1_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ICAP1_CLR_Pos) /*!< MCPWM INTEN_CLR: ICAP1_CLR Mask */ +#define MCPWM_INTEN_CLR_ILIM2_CLR_Pos 8 /*!< MCPWM INTEN_CLR: ILIM2_CLR Position */ +#define MCPWM_INTEN_CLR_ILIM2_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ILIM2_CLR_Pos) /*!< MCPWM INTEN_CLR: ILIM2_CLR Mask */ +#define MCPWM_INTEN_CLR_IMAT2_CLR_Pos 9 /*!< MCPWM INTEN_CLR: IMAT2_CLR Position */ +#define MCPWM_INTEN_CLR_IMAT2_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_IMAT2_CLR_Pos) /*!< MCPWM INTEN_CLR: IMAT2_CLR Mask */ +#define MCPWM_INTEN_CLR_ICAP2_CLR_Pos 10 /*!< MCPWM INTEN_CLR: ICAP2_CLR Position */ +#define MCPWM_INTEN_CLR_ICAP2_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ICAP2_CLR_Pos) /*!< MCPWM INTEN_CLR: ICAP2_CLR Mask */ +#define MCPWM_INTEN_CLR_ABORT_CLR_Pos 15 /*!< MCPWM INTEN_CLR: ABORT_CLR Position */ +#define MCPWM_INTEN_CLR_ABORT_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ABORT_CLR_Pos) /*!< MCPWM INTEN_CLR: ABORT_CLR Mask */ + +/* -------------------------------- MCPWM_CNTCON -------------------------------- */ +#define MCPWM_CNTCON_TC0MCI0_RE_Pos 0 /*!< MCPWM CNTCON: TC0MCI0_RE Position */ +#define MCPWM_CNTCON_TC0MCI0_RE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI0_RE_Pos) /*!< MCPWM CNTCON: TC0MCI0_RE Mask */ +#define MCPWM_CNTCON_TC0MCI0_FE_Pos 1 /*!< MCPWM CNTCON: TC0MCI0_FE Position */ +#define MCPWM_CNTCON_TC0MCI0_FE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI0_FE_Pos) /*!< MCPWM CNTCON: TC0MCI0_FE Mask */ +#define MCPWM_CNTCON_TC0MCI1_RE_Pos 2 /*!< MCPWM CNTCON: TC0MCI1_RE Position */ +#define MCPWM_CNTCON_TC0MCI1_RE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI1_RE_Pos) /*!< MCPWM CNTCON: TC0MCI1_RE Mask */ +#define MCPWM_CNTCON_TC0MCI1_FE_Pos 3 /*!< MCPWM CNTCON: TC0MCI1_FE Position */ +#define MCPWM_CNTCON_TC0MCI1_FE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI1_FE_Pos) /*!< MCPWM CNTCON: TC0MCI1_FE Mask */ +#define MCPWM_CNTCON_TC0MCI2_RE_Pos 4 /*!< MCPWM CNTCON: TC0MCI2_RE Position */ +#define MCPWM_CNTCON_TC0MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI2_RE_Pos) /*!< MCPWM CNTCON: TC0MCI2_RE Mask */ +#define MCPWM_CNTCON_TC0MCI2_FE_Pos 5 /*!< MCPWM CNTCON: TC0MCI2_FE Position */ +#define MCPWM_CNTCON_TC0MCI2_FE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI2_FE_Pos) /*!< MCPWM CNTCON: TC0MCI2_FE Mask */ +#define MCPWM_CNTCON_TC1MCI0_RE_Pos 6 /*!< MCPWM CNTCON: TC1MCI0_RE Position */ +#define MCPWM_CNTCON_TC1MCI0_RE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI0_RE_Pos) /*!< MCPWM CNTCON: TC1MCI0_RE Mask */ +#define MCPWM_CNTCON_TC1MCI0_FE_Pos 7 /*!< MCPWM CNTCON: TC1MCI0_FE Position */ +#define MCPWM_CNTCON_TC1MCI0_FE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI0_FE_Pos) /*!< MCPWM CNTCON: TC1MCI0_FE Mask */ +#define MCPWM_CNTCON_TC1MCI1_RE_Pos 8 /*!< MCPWM CNTCON: TC1MCI1_RE Position */ +#define MCPWM_CNTCON_TC1MCI1_RE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI1_RE_Pos) /*!< MCPWM CNTCON: TC1MCI1_RE Mask */ +#define MCPWM_CNTCON_TC1MCI1_FE_Pos 9 /*!< MCPWM CNTCON: TC1MCI1_FE Position */ +#define MCPWM_CNTCON_TC1MCI1_FE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI1_FE_Pos) /*!< MCPWM CNTCON: TC1MCI1_FE Mask */ +#define MCPWM_CNTCON_TC1MCI2_RE_Pos 10 /*!< MCPWM CNTCON: TC1MCI2_RE Position */ +#define MCPWM_CNTCON_TC1MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI2_RE_Pos) /*!< MCPWM CNTCON: TC1MCI2_RE Mask */ +#define MCPWM_CNTCON_TC1MCI2_FE_Pos 11 /*!< MCPWM CNTCON: TC1MCI2_FE Position */ +#define MCPWM_CNTCON_TC1MCI2_FE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI2_FE_Pos) /*!< MCPWM CNTCON: TC1MCI2_FE Mask */ +#define MCPWM_CNTCON_TC2MCI0_RE_Pos 12 /*!< MCPWM CNTCON: TC2MCI0_RE Position */ +#define MCPWM_CNTCON_TC2MCI0_RE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI0_RE_Pos) /*!< MCPWM CNTCON: TC2MCI0_RE Mask */ +#define MCPWM_CNTCON_TC2MCI0_FE_Pos 13 /*!< MCPWM CNTCON: TC2MCI0_FE Position */ +#define MCPWM_CNTCON_TC2MCI0_FE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI0_FE_Pos) /*!< MCPWM CNTCON: TC2MCI0_FE Mask */ +#define MCPWM_CNTCON_TC2MCI1_RE_Pos 14 /*!< MCPWM CNTCON: TC2MCI1_RE Position */ +#define MCPWM_CNTCON_TC2MCI1_RE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI1_RE_Pos) /*!< MCPWM CNTCON: TC2MCI1_RE Mask */ +#define MCPWM_CNTCON_TC2MCI1_FE_Pos 15 /*!< MCPWM CNTCON: TC2MCI1_FE Position */ +#define MCPWM_CNTCON_TC2MCI1_FE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI1_FE_Pos) /*!< MCPWM CNTCON: TC2MCI1_FE Mask */ +#define MCPWM_CNTCON_TC2MCI2_RE_Pos 16 /*!< MCPWM CNTCON: TC2MCI2_RE Position */ +#define MCPWM_CNTCON_TC2MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI2_RE_Pos) /*!< MCPWM CNTCON: TC2MCI2_RE Mask */ +#define MCPWM_CNTCON_TC2MCI2_FE_Pos 17 /*!< MCPWM CNTCON: TC2MCI2_FE Position */ +#define MCPWM_CNTCON_TC2MCI2_FE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI2_FE_Pos) /*!< MCPWM CNTCON: TC2MCI2_FE Mask */ +#define MCPWM_CNTCON_CNTR0_Pos 29 /*!< MCPWM CNTCON: CNTR0 Position */ +#define MCPWM_CNTCON_CNTR0_Msk (0x01UL << MCPWM_CNTCON_CNTR0_Pos) /*!< MCPWM CNTCON: CNTR0 Mask */ +#define MCPWM_CNTCON_CNTR1_Pos 30 /*!< MCPWM CNTCON: CNTR1 Position */ +#define MCPWM_CNTCON_CNTR1_Msk (0x01UL << MCPWM_CNTCON_CNTR1_Pos) /*!< MCPWM CNTCON: CNTR1 Mask */ +#define MCPWM_CNTCON_CNTR2_Pos 31 /*!< MCPWM CNTCON: CNTR2 Position */ +#define MCPWM_CNTCON_CNTR2_Msk (0x01UL << MCPWM_CNTCON_CNTR2_Pos) /*!< MCPWM CNTCON: CNTR2 Mask */ + +/* ------------------------------ MCPWM_CNTCON_SET ------------------------------ */ +#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos 0 /*!< MCPWM CNTCON_SET: TC0MCI0_RE_SET Position */ +#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI0_RE_SET Mask */ +#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos 1 /*!< MCPWM CNTCON_SET: TC0MCI0_FE_SET Position */ +#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI0_FE_SET Mask */ +#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos 2 /*!< MCPWM CNTCON_SET: TC0MCI1_RE_SET Position */ +#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI1_RE_SET Mask */ +#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos 3 /*!< MCPWM CNTCON_SET: TC0MCI1_FE_SET Position */ +#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI1_FE_SET Mask */ +#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos 4 /*!< MCPWM CNTCON_SET: TC0MCI2_RE_SET Position */ +#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI2_RE_SET Mask */ +#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos 5 /*!< MCPWM CNTCON_SET: TC0MCI2_FE_SET Position */ +#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI2_FE_SET Mask */ +#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos 6 /*!< MCPWM CNTCON_SET: TC1MCI0_RE_SET Position */ +#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI0_RE_SET Mask */ +#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos 7 /*!< MCPWM CNTCON_SET: TC1MCI0_FE_SET Position */ +#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI0_FE_SET Mask */ +#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos 8 /*!< MCPWM CNTCON_SET: TC1MCI1_RE_SET Position */ +#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI1_RE_SET Mask */ +#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos 9 /*!< MCPWM CNTCON_SET: TC1MCI1_FE_SET Position */ +#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI1_FE_SET Mask */ +#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos 10 /*!< MCPWM CNTCON_SET: TC1MCI2_RE_SET Position */ +#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI2_RE_SET Mask */ +#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos 11 /*!< MCPWM CNTCON_SET: TC1MCI2_FE_SET Position */ +#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI2_FE_SET Mask */ +#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos 12 /*!< MCPWM CNTCON_SET: TC2MCI0_RE_SET Position */ +#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI0_RE_SET Mask */ +#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos 13 /*!< MCPWM CNTCON_SET: TC2MCI0_FE_SET Position */ +#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI0_FE_SET Mask */ +#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos 14 /*!< MCPWM CNTCON_SET: TC2MCI1_RE_SET Position */ +#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI1_RE_SET Mask */ +#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos 15 /*!< MCPWM CNTCON_SET: TC2MCI1_FE_SET Position */ +#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI1_FE_SET Mask */ +#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos 16 /*!< MCPWM CNTCON_SET: TC2MCI2_RE_SET Position */ +#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI2_RE_SET Mask */ +#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos 17 /*!< MCPWM CNTCON_SET: TC2MCI2_FE_SET Position */ +#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI2_FE_SET Mask */ +#define MCPWM_CNTCON_SET_CNTR0_SET_Pos 29 /*!< MCPWM CNTCON_SET: CNTR0_SET Position */ +#define MCPWM_CNTCON_SET_CNTR0_SET_Msk (0x01UL << MCPWM_CNTCON_SET_CNTR0_SET_Pos) /*!< MCPWM CNTCON_SET: CNTR0_SET Mask */ +#define MCPWM_CNTCON_SET_CNTR1_SET_Pos 30 /*!< MCPWM CNTCON_SET: CNTR1_SET Position */ +#define MCPWM_CNTCON_SET_CNTR1_SET_Msk (0x01UL << MCPWM_CNTCON_SET_CNTR1_SET_Pos) /*!< MCPWM CNTCON_SET: CNTR1_SET Mask */ +#define MCPWM_CNTCON_SET_CNTR2_SET_Pos 31 /*!< MCPWM CNTCON_SET: CNTR2_SET Position */ +#define MCPWM_CNTCON_SET_CNTR2_SET_Msk (0x01UL << MCPWM_CNTCON_SET_CNTR2_SET_Pos) /*!< MCPWM CNTCON_SET: CNTR2_SET Mask */ + +/* ------------------------------ MCPWM_CNTCON_CLR ------------------------------ */ +#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos 0 /*!< MCPWM CNTCON_CLR: TC0MCI0_RE_CLR Position */ +#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI0_RE_CLR Mask */ +#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos 1 /*!< MCPWM CNTCON_CLR: TC0MCI0_FE_CLR Position */ +#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI0_FE_CLR Mask */ +#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos 2 /*!< MCPWM CNTCON_CLR: TC0MCI1_RE_CLR Position */ +#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI1_RE_CLR Mask */ +#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos 3 /*!< MCPWM CNTCON_CLR: TC0MCI1_FE_CLR Position */ +#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI1_FE_CLR Mask */ +#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos 4 /*!< MCPWM CNTCON_CLR: TC0MCI2_RE Position */ +#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI2_RE Mask */ +#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos 5 /*!< MCPWM CNTCON_CLR: TC0MCI2_FE_CLR Position */ +#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI2_FE_CLR Mask */ +#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos 6 /*!< MCPWM CNTCON_CLR: TC1MCI0_RE_CLR Position */ +#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI0_RE_CLR Mask */ +#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos 7 /*!< MCPWM CNTCON_CLR: TC1MCI0_FE_CLR Position */ +#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI0_FE_CLR Mask */ +#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos 8 /*!< MCPWM CNTCON_CLR: TC1MCI1_RE_CLR Position */ +#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI1_RE_CLR Mask */ +#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos 9 /*!< MCPWM CNTCON_CLR: TC1MCI1_FE_CLR Position */ +#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI1_FE_CLR Mask */ +#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos 10 /*!< MCPWM CNTCON_CLR: TC1MCI2_RE_CLR Position */ +#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI2_RE_CLR Mask */ +#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos 11 /*!< MCPWM CNTCON_CLR: TC1MCI2_FE_CLR Position */ +#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI2_FE_CLR Mask */ +#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos 12 /*!< MCPWM CNTCON_CLR: TC2MCI0_RE_CLR Position */ +#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI0_RE_CLR Mask */ +#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos 13 /*!< MCPWM CNTCON_CLR: TC2MCI0_FE_CLR Position */ +#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI0_FE_CLR Mask */ +#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos 14 /*!< MCPWM CNTCON_CLR: TC2MCI1_RE_CLR Position */ +#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI1_RE_CLR Mask */ +#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos 15 /*!< MCPWM CNTCON_CLR: TC2MCI1_FE_CLR Position */ +#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI1_FE_CLR Mask */ +#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos 16 /*!< MCPWM CNTCON_CLR: TC2MCI2_RE_CLR Position */ +#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI2_RE_CLR Mask */ +#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos 17 /*!< MCPWM CNTCON_CLR: TC2MCI2_FE_CLR Position */ +#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI2_FE_CLR Mask */ +#define MCPWM_CNTCON_CLR_CNTR0_CLR_Pos 29 /*!< MCPWM CNTCON_CLR: CNTR0_CLR Position */ +#define MCPWM_CNTCON_CLR_CNTR0_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_CNTR0_CLR_Pos) /*!< MCPWM CNTCON_CLR: CNTR0_CLR Mask */ +#define MCPWM_CNTCON_CLR_CNTR1_CLR_Pos 30 /*!< MCPWM CNTCON_CLR: CNTR1_CLR Position */ +#define MCPWM_CNTCON_CLR_CNTR1_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_CNTR1_CLR_Pos) /*!< MCPWM CNTCON_CLR: CNTR1_CLR Mask */ +#define MCPWM_CNTCON_CLR_CNTR2_CLR_Pos 31 /*!< MCPWM CNTCON_CLR: CNTR2_CLR Position */ +#define MCPWM_CNTCON_CLR_CNTR2_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_CNTR2_CLR_Pos) /*!< MCPWM CNTCON_CLR: CNTR2_CLR Mask */ + +/* --------------------------------- MCPWM_INTF --------------------------------- */ +#define MCPWM_INTF_ILIM0_F_Pos 0 /*!< MCPWM INTF: ILIM0_F Position */ +#define MCPWM_INTF_ILIM0_F_Msk (0x01UL << MCPWM_INTF_ILIM0_F_Pos) /*!< MCPWM INTF: ILIM0_F Mask */ +#define MCPWM_INTF_IMAT0_F_Pos 1 /*!< MCPWM INTF: IMAT0_F Position */ +#define MCPWM_INTF_IMAT0_F_Msk (0x01UL << MCPWM_INTF_IMAT0_F_Pos) /*!< MCPWM INTF: IMAT0_F Mask */ +#define MCPWM_INTF_ICAP0_F_Pos 2 /*!< MCPWM INTF: ICAP0_F Position */ +#define MCPWM_INTF_ICAP0_F_Msk (0x01UL << MCPWM_INTF_ICAP0_F_Pos) /*!< MCPWM INTF: ICAP0_F Mask */ +#define MCPWM_INTF_ILIM1_F_Pos 4 /*!< MCPWM INTF: ILIM1_F Position */ +#define MCPWM_INTF_ILIM1_F_Msk (0x01UL << MCPWM_INTF_ILIM1_F_Pos) /*!< MCPWM INTF: ILIM1_F Mask */ +#define MCPWM_INTF_IMAT1_F_Pos 5 /*!< MCPWM INTF: IMAT1_F Position */ +#define MCPWM_INTF_IMAT1_F_Msk (0x01UL << MCPWM_INTF_IMAT1_F_Pos) /*!< MCPWM INTF: IMAT1_F Mask */ +#define MCPWM_INTF_ICAP1_F_Pos 6 /*!< MCPWM INTF: ICAP1_F Position */ +#define MCPWM_INTF_ICAP1_F_Msk (0x01UL << MCPWM_INTF_ICAP1_F_Pos) /*!< MCPWM INTF: ICAP1_F Mask */ +#define MCPWM_INTF_ILIM2_F_Pos 8 /*!< MCPWM INTF: ILIM2_F Position */ +#define MCPWM_INTF_ILIM2_F_Msk (0x01UL << MCPWM_INTF_ILIM2_F_Pos) /*!< MCPWM INTF: ILIM2_F Mask */ +#define MCPWM_INTF_IMAT2_F_Pos 9 /*!< MCPWM INTF: IMAT2_F Position */ +#define MCPWM_INTF_IMAT2_F_Msk (0x01UL << MCPWM_INTF_IMAT2_F_Pos) /*!< MCPWM INTF: IMAT2_F Mask */ +#define MCPWM_INTF_ICAP2_F_Pos 10 /*!< MCPWM INTF: ICAP2_F Position */ +#define MCPWM_INTF_ICAP2_F_Msk (0x01UL << MCPWM_INTF_ICAP2_F_Pos) /*!< MCPWM INTF: ICAP2_F Mask */ +#define MCPWM_INTF_ABORT_F_Pos 15 /*!< MCPWM INTF: ABORT_F Position */ +#define MCPWM_INTF_ABORT_F_Msk (0x01UL << MCPWM_INTF_ABORT_F_Pos) /*!< MCPWM INTF: ABORT_F Mask */ + +/* ------------------------------- MCPWM_INTF_SET ------------------------------- */ +#define MCPWM_INTF_SET_ILIM0_F_SET_Pos 0 /*!< MCPWM INTF_SET: ILIM0_F_SET Position */ +#define MCPWM_INTF_SET_ILIM0_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ILIM0_F_SET_Pos) /*!< MCPWM INTF_SET: ILIM0_F_SET Mask */ +#define MCPWM_INTF_SET_IMAT0_F_SET_Pos 1 /*!< MCPWM INTF_SET: IMAT0_F_SET Position */ +#define MCPWM_INTF_SET_IMAT0_F_SET_Msk (0x01UL << MCPWM_INTF_SET_IMAT0_F_SET_Pos) /*!< MCPWM INTF_SET: IMAT0_F_SET Mask */ +#define MCPWM_INTF_SET_ICAP0_F_SET_Pos 2 /*!< MCPWM INTF_SET: ICAP0_F_SET Position */ +#define MCPWM_INTF_SET_ICAP0_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ICAP0_F_SET_Pos) /*!< MCPWM INTF_SET: ICAP0_F_SET Mask */ +#define MCPWM_INTF_SET_ILIM1_F_SET_Pos 4 /*!< MCPWM INTF_SET: ILIM1_F_SET Position */ +#define MCPWM_INTF_SET_ILIM1_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ILIM1_F_SET_Pos) /*!< MCPWM INTF_SET: ILIM1_F_SET Mask */ +#define MCPWM_INTF_SET_IMAT1_F_SET_Pos 5 /*!< MCPWM INTF_SET: IMAT1_F_SET Position */ +#define MCPWM_INTF_SET_IMAT1_F_SET_Msk (0x01UL << MCPWM_INTF_SET_IMAT1_F_SET_Pos) /*!< MCPWM INTF_SET: IMAT1_F_SET Mask */ +#define MCPWM_INTF_SET_ICAP1_F_SET_Pos 6 /*!< MCPWM INTF_SET: ICAP1_F_SET Position */ +#define MCPWM_INTF_SET_ICAP1_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ICAP1_F_SET_Pos) /*!< MCPWM INTF_SET: ICAP1_F_SET Mask */ +#define MCPWM_INTF_SET_ILIM2_F_SET_Pos 8 /*!< MCPWM INTF_SET: ILIM2_F_SET Position */ +#define MCPWM_INTF_SET_ILIM2_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ILIM2_F_SET_Pos) /*!< MCPWM INTF_SET: ILIM2_F_SET Mask */ +#define MCPWM_INTF_SET_IMAT2_F_SET_Pos 9 /*!< MCPWM INTF_SET: IMAT2_F_SET Position */ +#define MCPWM_INTF_SET_IMAT2_F_SET_Msk (0x01UL << MCPWM_INTF_SET_IMAT2_F_SET_Pos) /*!< MCPWM INTF_SET: IMAT2_F_SET Mask */ +#define MCPWM_INTF_SET_ICAP2_F_SET_Pos 10 /*!< MCPWM INTF_SET: ICAP2_F_SET Position */ +#define MCPWM_INTF_SET_ICAP2_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ICAP2_F_SET_Pos) /*!< MCPWM INTF_SET: ICAP2_F_SET Mask */ +#define MCPWM_INTF_SET_ABORT_F_SET_Pos 15 /*!< MCPWM INTF_SET: ABORT_F_SET Position */ +#define MCPWM_INTF_SET_ABORT_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ABORT_F_SET_Pos) /*!< MCPWM INTF_SET: ABORT_F_SET Mask */ + +/* ------------------------------- MCPWM_INTF_CLR ------------------------------- */ +#define MCPWM_INTF_CLR_ILIM0_F_CLR_Pos 0 /*!< MCPWM INTF_CLR: ILIM0_F_CLR Position */ +#define MCPWM_INTF_CLR_ILIM0_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ILIM0_F_CLR_Pos) /*!< MCPWM INTF_CLR: ILIM0_F_CLR Mask */ +#define MCPWM_INTF_CLR_IMAT0_F_CLR_Pos 1 /*!< MCPWM INTF_CLR: IMAT0_F_CLR Position */ +#define MCPWM_INTF_CLR_IMAT0_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_IMAT0_F_CLR_Pos) /*!< MCPWM INTF_CLR: IMAT0_F_CLR Mask */ +#define MCPWM_INTF_CLR_ICAP0_F_CLR_Pos 2 /*!< MCPWM INTF_CLR: ICAP0_F_CLR Position */ +#define MCPWM_INTF_CLR_ICAP0_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ICAP0_F_CLR_Pos) /*!< MCPWM INTF_CLR: ICAP0_F_CLR Mask */ +#define MCPWM_INTF_CLR_ILIM1_F_CLR_Pos 4 /*!< MCPWM INTF_CLR: ILIM1_F_CLR Position */ +#define MCPWM_INTF_CLR_ILIM1_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ILIM1_F_CLR_Pos) /*!< MCPWM INTF_CLR: ILIM1_F_CLR Mask */ +#define MCPWM_INTF_CLR_IMAT1_F_CLR_Pos 5 /*!< MCPWM INTF_CLR: IMAT1_F_CLR Position */ +#define MCPWM_INTF_CLR_IMAT1_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_IMAT1_F_CLR_Pos) /*!< MCPWM INTF_CLR: IMAT1_F_CLR Mask */ +#define MCPWM_INTF_CLR_ICAP1_F_CLR_Pos 6 /*!< MCPWM INTF_CLR: ICAP1_F_CLR Position */ +#define MCPWM_INTF_CLR_ICAP1_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ICAP1_F_CLR_Pos) /*!< MCPWM INTF_CLR: ICAP1_F_CLR Mask */ +#define MCPWM_INTF_CLR_ILIM2_F_CLR_Pos 8 /*!< MCPWM INTF_CLR: ILIM2_F_CLR Position */ +#define MCPWM_INTF_CLR_ILIM2_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ILIM2_F_CLR_Pos) /*!< MCPWM INTF_CLR: ILIM2_F_CLR Mask */ +#define MCPWM_INTF_CLR_IMAT2_F_CLR_Pos 9 /*!< MCPWM INTF_CLR: IMAT2_F_CLR Position */ +#define MCPWM_INTF_CLR_IMAT2_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_IMAT2_F_CLR_Pos) /*!< MCPWM INTF_CLR: IMAT2_F_CLR Mask */ +#define MCPWM_INTF_CLR_ICAP2_F_CLR_Pos 10 /*!< MCPWM INTF_CLR: ICAP2_F_CLR Position */ +#define MCPWM_INTF_CLR_ICAP2_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ICAP2_F_CLR_Pos) /*!< MCPWM INTF_CLR: ICAP2_F_CLR Mask */ +#define MCPWM_INTF_CLR_ABORT_F_CLR_Pos 15 /*!< MCPWM INTF_CLR: ABORT_F_CLR Position */ +#define MCPWM_INTF_CLR_ABORT_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ABORT_F_CLR_Pos) /*!< MCPWM INTF_CLR: ABORT_F_CLR Mask */ + +/* -------------------------------- MCPWM_CAP_CLR ------------------------------- */ +#define MCPWM_CAP_CLR_CAP_CLR0_Pos 0 /*!< MCPWM CAP_CLR: CAP_CLR0 Position */ +#define MCPWM_CAP_CLR_CAP_CLR0_Msk (0x01UL << MCPWM_CAP_CLR_CAP_CLR0_Pos) /*!< MCPWM CAP_CLR: CAP_CLR0 Mask */ +#define MCPWM_CAP_CLR_CAP_CLR1_Pos 1 /*!< MCPWM CAP_CLR: CAP_CLR1 Position */ +#define MCPWM_CAP_CLR_CAP_CLR1_Msk (0x01UL << MCPWM_CAP_CLR_CAP_CLR1_Pos) /*!< MCPWM CAP_CLR: CAP_CLR1 Mask */ +#define MCPWM_CAP_CLR_CAP_CLR2_Pos 2 /*!< MCPWM CAP_CLR: CAP_CLR2 Position */ +#define MCPWM_CAP_CLR_CAP_CLR2_Msk (0x01UL << MCPWM_CAP_CLR_CAP_CLR2_Pos) /*!< MCPWM CAP_CLR: CAP_CLR2 Mask */ + + +/* ================================================================================ */ +/* ================ Group 'I2Cn' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- I2Cn_CONSET -------------------------------- */ +#define I2Cn_CONSET_AA_Pos 2 /*!< I2Cn CONSET: AA Position */ +#define I2Cn_CONSET_AA_Msk (0x01UL << I2Cn_CONSET_AA_Pos) /*!< I2Cn CONSET: AA Mask */ +#define I2Cn_CONSET_SI_Pos 3 /*!< I2Cn CONSET: SI Position */ +#define I2Cn_CONSET_SI_Msk (0x01UL << I2Cn_CONSET_SI_Pos) /*!< I2Cn CONSET: SI Mask */ +#define I2Cn_CONSET_STO_Pos 4 /*!< I2Cn CONSET: STO Position */ +#define I2Cn_CONSET_STO_Msk (0x01UL << I2Cn_CONSET_STO_Pos) /*!< I2Cn CONSET: STO Mask */ +#define I2Cn_CONSET_STA_Pos 5 /*!< I2Cn CONSET: STA Position */ +#define I2Cn_CONSET_STA_Msk (0x01UL << I2Cn_CONSET_STA_Pos) /*!< I2Cn CONSET: STA Mask */ +#define I2Cn_CONSET_I2EN_Pos 6 /*!< I2Cn CONSET: I2EN Position */ +#define I2Cn_CONSET_I2EN_Msk (0x01UL << I2Cn_CONSET_I2EN_Pos) /*!< I2Cn CONSET: I2EN Mask */ + +/* ---------------------------------- I2Cn_STAT --------------------------------- */ +#define I2Cn_STAT_Status_Pos 3 /*!< I2Cn STAT: Status Position */ +#define I2Cn_STAT_Status_Msk (0x1fUL << I2Cn_STAT_Status_Pos) /*!< I2Cn STAT: Status Mask */ + +/* ---------------------------------- I2Cn_DAT ---------------------------------- */ +#define I2Cn_DAT_Data_Pos 0 /*!< I2Cn DAT: Data Position */ +#define I2Cn_DAT_Data_Msk (0x000000ffUL << I2Cn_DAT_Data_Pos) /*!< I2Cn DAT: Data Mask */ + +/* ---------------------------------- I2Cn_ADR0 --------------------------------- */ +#define I2Cn_ADR0_GC_Pos 0 /*!< I2Cn ADR0: GC Position */ +#define I2Cn_ADR0_GC_Msk (0x01UL << I2Cn_ADR0_GC_Pos) /*!< I2Cn ADR0: GC Mask */ +#define I2Cn_ADR0_Address_Pos 1 /*!< I2Cn ADR0: Address Position */ +#define I2Cn_ADR0_Address_Msk (0x7fUL << I2Cn_ADR0_Address_Pos) /*!< I2Cn ADR0: Address Mask */ + +/* ---------------------------------- I2Cn_SCLH --------------------------------- */ +#define I2Cn_SCLH_SCLH_Pos 0 /*!< I2Cn SCLH: SCLH Position */ +#define I2Cn_SCLH_SCLH_Msk (0x0000ffffUL << I2Cn_SCLH_SCLH_Pos) /*!< I2Cn SCLH: SCLH Mask */ + +/* ---------------------------------- I2Cn_SCLL --------------------------------- */ +#define I2Cn_SCLL_SCLL_Pos 0 /*!< I2Cn SCLL: SCLL Position */ +#define I2Cn_SCLL_SCLL_Msk (0x0000ffffUL << I2Cn_SCLL_SCLL_Pos) /*!< I2Cn SCLL: SCLL Mask */ + +/* --------------------------------- I2Cn_CONCLR -------------------------------- */ +#define I2Cn_CONCLR_AAC_Pos 2 /*!< I2Cn CONCLR: AAC Position */ +#define I2Cn_CONCLR_AAC_Msk (0x01UL << I2Cn_CONCLR_AAC_Pos) /*!< I2Cn CONCLR: AAC Mask */ +#define I2Cn_CONCLR_SIC_Pos 3 /*!< I2Cn CONCLR: SIC Position */ +#define I2Cn_CONCLR_SIC_Msk (0x01UL << I2Cn_CONCLR_SIC_Pos) /*!< I2Cn CONCLR: SIC Mask */ +#define I2Cn_CONCLR_STAC_Pos 5 /*!< I2Cn CONCLR: STAC Position */ +#define I2Cn_CONCLR_STAC_Msk (0x01UL << I2Cn_CONCLR_STAC_Pos) /*!< I2Cn CONCLR: STAC Mask */ +#define I2Cn_CONCLR_I2ENC_Pos 6 /*!< I2Cn CONCLR: I2ENC Position */ +#define I2Cn_CONCLR_I2ENC_Msk (0x01UL << I2Cn_CONCLR_I2ENC_Pos) /*!< I2Cn CONCLR: I2ENC Mask */ + +/* --------------------------------- I2Cn_MMCTRL -------------------------------- */ +#define I2Cn_MMCTRL_MM_ENA_Pos 0 /*!< I2Cn MMCTRL: MM_ENA Position */ +#define I2Cn_MMCTRL_MM_ENA_Msk (0x01UL << I2Cn_MMCTRL_MM_ENA_Pos) /*!< I2Cn MMCTRL: MM_ENA Mask */ +#define I2Cn_MMCTRL_ENA_SCL_Pos 1 /*!< I2Cn MMCTRL: ENA_SCL Position */ +#define I2Cn_MMCTRL_ENA_SCL_Msk (0x01UL << I2Cn_MMCTRL_ENA_SCL_Pos) /*!< I2Cn MMCTRL: ENA_SCL Mask */ +#define I2Cn_MMCTRL_MATCH_ALL_Pos 2 /*!< I2Cn MMCTRL: MATCH_ALL Position */ +#define I2Cn_MMCTRL_MATCH_ALL_Msk (0x01UL << I2Cn_MMCTRL_MATCH_ALL_Pos) /*!< I2Cn MMCTRL: MATCH_ALL Mask */ + +/* ---------------------------------- I2Cn_ADR1 --------------------------------- */ +#define I2Cn_ADR1_GC_Pos 0 /*!< I2Cn ADR1: GC Position */ +#define I2Cn_ADR1_GC_Msk (0x01UL << I2Cn_ADR1_GC_Pos) /*!< I2Cn ADR1: GC Mask */ +#define I2Cn_ADR1_Address_Pos 1 /*!< I2Cn ADR1: Address Position */ +#define I2Cn_ADR1_Address_Msk (0x7fUL << I2Cn_ADR1_Address_Pos) /*!< I2Cn ADR1: Address Mask */ + +/* ---------------------------------- I2Cn_ADR2 --------------------------------- */ +#define I2Cn_ADR2_GC_Pos 0 /*!< I2Cn ADR2: GC Position */ +#define I2Cn_ADR2_GC_Msk (0x01UL << I2Cn_ADR2_GC_Pos) /*!< I2Cn ADR2: GC Mask */ +#define I2Cn_ADR2_Address_Pos 1 /*!< I2Cn ADR2: Address Position */ +#define I2Cn_ADR2_Address_Msk (0x7fUL << I2Cn_ADR2_Address_Pos) /*!< I2Cn ADR2: Address Mask */ + +/* ---------------------------------- I2Cn_ADR3 --------------------------------- */ +#define I2Cn_ADR3_GC_Pos 0 /*!< I2Cn ADR3: GC Position */ +#define I2Cn_ADR3_GC_Msk (0x01UL << I2Cn_ADR3_GC_Pos) /*!< I2Cn ADR3: GC Mask */ +#define I2Cn_ADR3_Address_Pos 1 /*!< I2Cn ADR3: Address Position */ +#define I2Cn_ADR3_Address_Msk (0x7fUL << I2Cn_ADR3_Address_Pos) /*!< I2Cn ADR3: Address Mask */ + +/* ------------------------------ I2Cn_DATA_BUFFER ------------------------------ */ +#define I2Cn_DATA_BUFFER_Data_Pos 0 /*!< I2Cn DATA_BUFFER: Data Position */ +#define I2Cn_DATA_BUFFER_Data_Msk (0x000000ffUL << I2Cn_DATA_BUFFER_Data_Pos) /*!< I2Cn DATA_BUFFER: Data Mask */ + +/* --------------------------------- I2Cn_MASK0 --------------------------------- */ +#define I2Cn_MASK0_MASK_Pos 1 /*!< I2Cn MASK0: MASK Position */ +#define I2Cn_MASK0_MASK_Msk (0x7fUL << I2Cn_MASK0_MASK_Pos) /*!< I2Cn MASK0: MASK Mask */ + +/* --------------------------------- I2Cn_MASK1 --------------------------------- */ +#define I2Cn_MASK1_MASK_Pos 1 /*!< I2Cn MASK1: MASK Position */ +#define I2Cn_MASK1_MASK_Msk (0x7fUL << I2Cn_MASK1_MASK_Pos) /*!< I2Cn MASK1: MASK Mask */ + +/* --------------------------------- I2Cn_MASK2 --------------------------------- */ +#define I2Cn_MASK2_MASK_Pos 1 /*!< I2Cn MASK2: MASK Position */ +#define I2Cn_MASK2_MASK_Msk (0x7fUL << I2Cn_MASK2_MASK_Pos) /*!< I2Cn MASK2: MASK Mask */ + +/* --------------------------------- I2Cn_MASK3 --------------------------------- */ +#define I2Cn_MASK3_MASK_Pos 1 /*!< I2Cn MASK3: MASK Position */ +#define I2Cn_MASK3_MASK_Msk (0x7fUL << I2Cn_MASK3_MASK_Pos) /*!< I2Cn MASK3: MASK Mask */ + + +/* ================================================================================ */ +/* ================ struct 'I2C0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- I2C0_CONSET -------------------------------- */ +#define I2C0_CONSET_AA_Pos 2 /*!< I2C0 CONSET: AA Position */ +#define I2C0_CONSET_AA_Msk (0x01UL << I2C0_CONSET_AA_Pos) /*!< I2C0 CONSET: AA Mask */ +#define I2C0_CONSET_SI_Pos 3 /*!< I2C0 CONSET: SI Position */ +#define I2C0_CONSET_SI_Msk (0x01UL << I2C0_CONSET_SI_Pos) /*!< I2C0 CONSET: SI Mask */ +#define I2C0_CONSET_STO_Pos 4 /*!< I2C0 CONSET: STO Position */ +#define I2C0_CONSET_STO_Msk (0x01UL << I2C0_CONSET_STO_Pos) /*!< I2C0 CONSET: STO Mask */ +#define I2C0_CONSET_STA_Pos 5 /*!< I2C0 CONSET: STA Position */ +#define I2C0_CONSET_STA_Msk (0x01UL << I2C0_CONSET_STA_Pos) /*!< I2C0 CONSET: STA Mask */ +#define I2C0_CONSET_I2EN_Pos 6 /*!< I2C0 CONSET: I2EN Position */ +#define I2C0_CONSET_I2EN_Msk (0x01UL << I2C0_CONSET_I2EN_Pos) /*!< I2C0 CONSET: I2EN Mask */ + +/* ---------------------------------- I2C0_STAT --------------------------------- */ +#define I2C0_STAT_Status_Pos 3 /*!< I2C0 STAT: Status Position */ +#define I2C0_STAT_Status_Msk (0x1fUL << I2C0_STAT_Status_Pos) /*!< I2C0 STAT: Status Mask */ + +/* ---------------------------------- I2C0_DAT ---------------------------------- */ +#define I2C0_DAT_Data_Pos 0 /*!< I2C0 DAT: Data Position */ +#define I2C0_DAT_Data_Msk (0x000000ffUL << I2C0_DAT_Data_Pos) /*!< I2C0 DAT: Data Mask */ + +/* ---------------------------------- I2C0_ADR0 --------------------------------- */ +#define I2C0_ADR0_GC_Pos 0 /*!< I2C0 ADR0: GC Position */ +#define I2C0_ADR0_GC_Msk (0x01UL << I2C0_ADR0_GC_Pos) /*!< I2C0 ADR0: GC Mask */ +#define I2C0_ADR0_Address_Pos 1 /*!< I2C0 ADR0: Address Position */ +#define I2C0_ADR0_Address_Msk (0x7fUL << I2C0_ADR0_Address_Pos) /*!< I2C0 ADR0: Address Mask */ + +/* ---------------------------------- I2C0_SCLH --------------------------------- */ +#define I2C0_SCLH_SCLH_Pos 0 /*!< I2C0 SCLH: SCLH Position */ +#define I2C0_SCLH_SCLH_Msk (0x0000ffffUL << I2C0_SCLH_SCLH_Pos) /*!< I2C0 SCLH: SCLH Mask */ + +/* ---------------------------------- I2C0_SCLL --------------------------------- */ +#define I2C0_SCLL_SCLL_Pos 0 /*!< I2C0 SCLL: SCLL Position */ +#define I2C0_SCLL_SCLL_Msk (0x0000ffffUL << I2C0_SCLL_SCLL_Pos) /*!< I2C0 SCLL: SCLL Mask */ + +/* --------------------------------- I2C0_CONCLR -------------------------------- */ +#define I2C0_CONCLR_AAC_Pos 2 /*!< I2C0 CONCLR: AAC Position */ +#define I2C0_CONCLR_AAC_Msk (0x01UL << I2C0_CONCLR_AAC_Pos) /*!< I2C0 CONCLR: AAC Mask */ +#define I2C0_CONCLR_SIC_Pos 3 /*!< I2C0 CONCLR: SIC Position */ +#define I2C0_CONCLR_SIC_Msk (0x01UL << I2C0_CONCLR_SIC_Pos) /*!< I2C0 CONCLR: SIC Mask */ +#define I2C0_CONCLR_STAC_Pos 5 /*!< I2C0 CONCLR: STAC Position */ +#define I2C0_CONCLR_STAC_Msk (0x01UL << I2C0_CONCLR_STAC_Pos) /*!< I2C0 CONCLR: STAC Mask */ +#define I2C0_CONCLR_I2ENC_Pos 6 /*!< I2C0 CONCLR: I2ENC Position */ +#define I2C0_CONCLR_I2ENC_Msk (0x01UL << I2C0_CONCLR_I2ENC_Pos) /*!< I2C0 CONCLR: I2ENC Mask */ + +/* --------------------------------- I2C0_MMCTRL -------------------------------- */ +#define I2C0_MMCTRL_MM_ENA_Pos 0 /*!< I2C0 MMCTRL: MM_ENA Position */ +#define I2C0_MMCTRL_MM_ENA_Msk (0x01UL << I2C0_MMCTRL_MM_ENA_Pos) /*!< I2C0 MMCTRL: MM_ENA Mask */ +#define I2C0_MMCTRL_ENA_SCL_Pos 1 /*!< I2C0 MMCTRL: ENA_SCL Position */ +#define I2C0_MMCTRL_ENA_SCL_Msk (0x01UL << I2C0_MMCTRL_ENA_SCL_Pos) /*!< I2C0 MMCTRL: ENA_SCL Mask */ +#define I2C0_MMCTRL_MATCH_ALL_Pos 2 /*!< I2C0 MMCTRL: MATCH_ALL Position */ +#define I2C0_MMCTRL_MATCH_ALL_Msk (0x01UL << I2C0_MMCTRL_MATCH_ALL_Pos) /*!< I2C0 MMCTRL: MATCH_ALL Mask */ + +/* ---------------------------------- I2C0_ADR1 --------------------------------- */ +#define I2C0_ADR1_GC_Pos 0 /*!< I2C0 ADR1: GC Position */ +#define I2C0_ADR1_GC_Msk (0x01UL << I2C0_ADR1_GC_Pos) /*!< I2C0 ADR1: GC Mask */ +#define I2C0_ADR1_Address_Pos 1 /*!< I2C0 ADR1: Address Position */ +#define I2C0_ADR1_Address_Msk (0x7fUL << I2C0_ADR1_Address_Pos) /*!< I2C0 ADR1: Address Mask */ + +/* ---------------------------------- I2C0_ADR2 --------------------------------- */ +#define I2C0_ADR2_GC_Pos 0 /*!< I2C0 ADR2: GC Position */ +#define I2C0_ADR2_GC_Msk (0x01UL << I2C0_ADR2_GC_Pos) /*!< I2C0 ADR2: GC Mask */ +#define I2C0_ADR2_Address_Pos 1 /*!< I2C0 ADR2: Address Position */ +#define I2C0_ADR2_Address_Msk (0x7fUL << I2C0_ADR2_Address_Pos) /*!< I2C0 ADR2: Address Mask */ + +/* ---------------------------------- I2C0_ADR3 --------------------------------- */ +#define I2C0_ADR3_GC_Pos 0 /*!< I2C0 ADR3: GC Position */ +#define I2C0_ADR3_GC_Msk (0x01UL << I2C0_ADR3_GC_Pos) /*!< I2C0 ADR3: GC Mask */ +#define I2C0_ADR3_Address_Pos 1 /*!< I2C0 ADR3: Address Position */ +#define I2C0_ADR3_Address_Msk (0x7fUL << I2C0_ADR3_Address_Pos) /*!< I2C0 ADR3: Address Mask */ + +/* ------------------------------ I2C0_DATA_BUFFER ------------------------------ */ +#define I2C0_DATA_BUFFER_Data_Pos 0 /*!< I2C0 DATA_BUFFER: Data Position */ +#define I2C0_DATA_BUFFER_Data_Msk (0x000000ffUL << I2C0_DATA_BUFFER_Data_Pos) /*!< I2C0 DATA_BUFFER: Data Mask */ + +/* --------------------------------- I2C0_MASK0 --------------------------------- */ +#define I2C0_MASK0_MASK_Pos 1 /*!< I2C0 MASK0: MASK Position */ +#define I2C0_MASK0_MASK_Msk (0x7fUL << I2C0_MASK0_MASK_Pos) /*!< I2C0 MASK0: MASK Mask */ + +/* --------------------------------- I2C0_MASK1 --------------------------------- */ +#define I2C0_MASK1_MASK_Pos 1 /*!< I2C0 MASK1: MASK Position */ +#define I2C0_MASK1_MASK_Msk (0x7fUL << I2C0_MASK1_MASK_Pos) /*!< I2C0 MASK1: MASK Mask */ + +/* --------------------------------- I2C0_MASK2 --------------------------------- */ +#define I2C0_MASK2_MASK_Pos 1 /*!< I2C0 MASK2: MASK Position */ +#define I2C0_MASK2_MASK_Msk (0x7fUL << I2C0_MASK2_MASK_Pos) /*!< I2C0 MASK2: MASK Mask */ + +/* --------------------------------- I2C0_MASK3 --------------------------------- */ +#define I2C0_MASK3_MASK_Pos 1 /*!< I2C0 MASK3: MASK Position */ +#define I2C0_MASK3_MASK_Msk (0x7fUL << I2C0_MASK3_MASK_Pos) /*!< I2C0 MASK3: MASK Mask */ + + +/* ================================================================================ */ +/* ================ struct 'I2C1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- I2C1_CONSET -------------------------------- */ +#define I2C1_CONSET_AA_Pos 2 /*!< I2C1 CONSET: AA Position */ +#define I2C1_CONSET_AA_Msk (0x01UL << I2C1_CONSET_AA_Pos) /*!< I2C1 CONSET: AA Mask */ +#define I2C1_CONSET_SI_Pos 3 /*!< I2C1 CONSET: SI Position */ +#define I2C1_CONSET_SI_Msk (0x01UL << I2C1_CONSET_SI_Pos) /*!< I2C1 CONSET: SI Mask */ +#define I2C1_CONSET_STO_Pos 4 /*!< I2C1 CONSET: STO Position */ +#define I2C1_CONSET_STO_Msk (0x01UL << I2C1_CONSET_STO_Pos) /*!< I2C1 CONSET: STO Mask */ +#define I2C1_CONSET_STA_Pos 5 /*!< I2C1 CONSET: STA Position */ +#define I2C1_CONSET_STA_Msk (0x01UL << I2C1_CONSET_STA_Pos) /*!< I2C1 CONSET: STA Mask */ +#define I2C1_CONSET_I2EN_Pos 6 /*!< I2C1 CONSET: I2EN Position */ +#define I2C1_CONSET_I2EN_Msk (0x01UL << I2C1_CONSET_I2EN_Pos) /*!< I2C1 CONSET: I2EN Mask */ + +/* ---------------------------------- I2C1_STAT --------------------------------- */ +#define I2C1_STAT_Status_Pos 3 /*!< I2C1 STAT: Status Position */ +#define I2C1_STAT_Status_Msk (0x1fUL << I2C1_STAT_Status_Pos) /*!< I2C1 STAT: Status Mask */ + +/* ---------------------------------- I2C1_DAT ---------------------------------- */ +#define I2C1_DAT_Data_Pos 0 /*!< I2C1 DAT: Data Position */ +#define I2C1_DAT_Data_Msk (0x000000ffUL << I2C1_DAT_Data_Pos) /*!< I2C1 DAT: Data Mask */ + +/* ---------------------------------- I2C1_ADR0 --------------------------------- */ +#define I2C1_ADR0_GC_Pos 0 /*!< I2C1 ADR0: GC Position */ +#define I2C1_ADR0_GC_Msk (0x01UL << I2C1_ADR0_GC_Pos) /*!< I2C1 ADR0: GC Mask */ +#define I2C1_ADR0_Address_Pos 1 /*!< I2C1 ADR0: Address Position */ +#define I2C1_ADR0_Address_Msk (0x7fUL << I2C1_ADR0_Address_Pos) /*!< I2C1 ADR0: Address Mask */ + +/* ---------------------------------- I2C1_SCLH --------------------------------- */ +#define I2C1_SCLH_SCLH_Pos 0 /*!< I2C1 SCLH: SCLH Position */ +#define I2C1_SCLH_SCLH_Msk (0x0000ffffUL << I2C1_SCLH_SCLH_Pos) /*!< I2C1 SCLH: SCLH Mask */ + +/* ---------------------------------- I2C1_SCLL --------------------------------- */ +#define I2C1_SCLL_SCLL_Pos 0 /*!< I2C1 SCLL: SCLL Position */ +#define I2C1_SCLL_SCLL_Msk (0x0000ffffUL << I2C1_SCLL_SCLL_Pos) /*!< I2C1 SCLL: SCLL Mask */ + +/* --------------------------------- I2C1_CONCLR -------------------------------- */ +#define I2C1_CONCLR_AAC_Pos 2 /*!< I2C1 CONCLR: AAC Position */ +#define I2C1_CONCLR_AAC_Msk (0x01UL << I2C1_CONCLR_AAC_Pos) /*!< I2C1 CONCLR: AAC Mask */ +#define I2C1_CONCLR_SIC_Pos 3 /*!< I2C1 CONCLR: SIC Position */ +#define I2C1_CONCLR_SIC_Msk (0x01UL << I2C1_CONCLR_SIC_Pos) /*!< I2C1 CONCLR: SIC Mask */ +#define I2C1_CONCLR_STAC_Pos 5 /*!< I2C1 CONCLR: STAC Position */ +#define I2C1_CONCLR_STAC_Msk (0x01UL << I2C1_CONCLR_STAC_Pos) /*!< I2C1 CONCLR: STAC Mask */ +#define I2C1_CONCLR_I2ENC_Pos 6 /*!< I2C1 CONCLR: I2ENC Position */ +#define I2C1_CONCLR_I2ENC_Msk (0x01UL << I2C1_CONCLR_I2ENC_Pos) /*!< I2C1 CONCLR: I2ENC Mask */ + +/* --------------------------------- I2C1_MMCTRL -------------------------------- */ +#define I2C1_MMCTRL_MM_ENA_Pos 0 /*!< I2C1 MMCTRL: MM_ENA Position */ +#define I2C1_MMCTRL_MM_ENA_Msk (0x01UL << I2C1_MMCTRL_MM_ENA_Pos) /*!< I2C1 MMCTRL: MM_ENA Mask */ +#define I2C1_MMCTRL_ENA_SCL_Pos 1 /*!< I2C1 MMCTRL: ENA_SCL Position */ +#define I2C1_MMCTRL_ENA_SCL_Msk (0x01UL << I2C1_MMCTRL_ENA_SCL_Pos) /*!< I2C1 MMCTRL: ENA_SCL Mask */ +#define I2C1_MMCTRL_MATCH_ALL_Pos 2 /*!< I2C1 MMCTRL: MATCH_ALL Position */ +#define I2C1_MMCTRL_MATCH_ALL_Msk (0x01UL << I2C1_MMCTRL_MATCH_ALL_Pos) /*!< I2C1 MMCTRL: MATCH_ALL Mask */ + +/* ---------------------------------- I2C1_ADR1 --------------------------------- */ +#define I2C1_ADR1_GC_Pos 0 /*!< I2C1 ADR1: GC Position */ +#define I2C1_ADR1_GC_Msk (0x01UL << I2C1_ADR1_GC_Pos) /*!< I2C1 ADR1: GC Mask */ +#define I2C1_ADR1_Address_Pos 1 /*!< I2C1 ADR1: Address Position */ +#define I2C1_ADR1_Address_Msk (0x7fUL << I2C1_ADR1_Address_Pos) /*!< I2C1 ADR1: Address Mask */ + +/* ---------------------------------- I2C1_ADR2 --------------------------------- */ +#define I2C1_ADR2_GC_Pos 0 /*!< I2C1 ADR2: GC Position */ +#define I2C1_ADR2_GC_Msk (0x01UL << I2C1_ADR2_GC_Pos) /*!< I2C1 ADR2: GC Mask */ +#define I2C1_ADR2_Address_Pos 1 /*!< I2C1 ADR2: Address Position */ +#define I2C1_ADR2_Address_Msk (0x7fUL << I2C1_ADR2_Address_Pos) /*!< I2C1 ADR2: Address Mask */ + +/* ---------------------------------- I2C1_ADR3 --------------------------------- */ +#define I2C1_ADR3_GC_Pos 0 /*!< I2C1 ADR3: GC Position */ +#define I2C1_ADR3_GC_Msk (0x01UL << I2C1_ADR3_GC_Pos) /*!< I2C1 ADR3: GC Mask */ +#define I2C1_ADR3_Address_Pos 1 /*!< I2C1 ADR3: Address Position */ +#define I2C1_ADR3_Address_Msk (0x7fUL << I2C1_ADR3_Address_Pos) /*!< I2C1 ADR3: Address Mask */ + +/* ------------------------------ I2C1_DATA_BUFFER ------------------------------ */ +#define I2C1_DATA_BUFFER_Data_Pos 0 /*!< I2C1 DATA_BUFFER: Data Position */ +#define I2C1_DATA_BUFFER_Data_Msk (0x000000ffUL << I2C1_DATA_BUFFER_Data_Pos) /*!< I2C1 DATA_BUFFER: Data Mask */ + +/* --------------------------------- I2C1_MASK0 --------------------------------- */ +#define I2C1_MASK0_MASK_Pos 1 /*!< I2C1 MASK0: MASK Position */ +#define I2C1_MASK0_MASK_Msk (0x7fUL << I2C1_MASK0_MASK_Pos) /*!< I2C1 MASK0: MASK Mask */ + +/* --------------------------------- I2C1_MASK1 --------------------------------- */ +#define I2C1_MASK1_MASK_Pos 1 /*!< I2C1 MASK1: MASK Position */ +#define I2C1_MASK1_MASK_Msk (0x7fUL << I2C1_MASK1_MASK_Pos) /*!< I2C1 MASK1: MASK Mask */ + +/* --------------------------------- I2C1_MASK2 --------------------------------- */ +#define I2C1_MASK2_MASK_Pos 1 /*!< I2C1 MASK2: MASK Position */ +#define I2C1_MASK2_MASK_Msk (0x7fUL << I2C1_MASK2_MASK_Pos) /*!< I2C1 MASK2: MASK Mask */ + +/* --------------------------------- I2C1_MASK3 --------------------------------- */ +#define I2C1_MASK3_MASK_Pos 1 /*!< I2C1 MASK3: MASK Position */ +#define I2C1_MASK3_MASK_Msk (0x7fUL << I2C1_MASK3_MASK_Pos) /*!< I2C1 MASK3: MASK Mask */ + + +/* ================================================================================ */ +/* ================ Group 'I2Sn' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- I2Sn_DAO ---------------------------------- */ +#define I2Sn_DAO_WORDWIDTH_Pos 0 /*!< I2Sn DAO: WORDWIDTH Position */ +#define I2Sn_DAO_WORDWIDTH_Msk (0x03UL << I2Sn_DAO_WORDWIDTH_Pos) /*!< I2Sn DAO: WORDWIDTH Mask */ +#define I2Sn_DAO_MONO_Pos 2 /*!< I2Sn DAO: MONO Position */ +#define I2Sn_DAO_MONO_Msk (0x01UL << I2Sn_DAO_MONO_Pos) /*!< I2Sn DAO: MONO Mask */ +#define I2Sn_DAO_STOP_Pos 3 /*!< I2Sn DAO: STOP Position */ +#define I2Sn_DAO_STOP_Msk (0x01UL << I2Sn_DAO_STOP_Pos) /*!< I2Sn DAO: STOP Mask */ +#define I2Sn_DAO_RESET_Pos 4 /*!< I2Sn DAO: RESET Position */ +#define I2Sn_DAO_RESET_Msk (0x01UL << I2Sn_DAO_RESET_Pos) /*!< I2Sn DAO: RESET Mask */ +#define I2Sn_DAO_WS_SEL_Pos 5 /*!< I2Sn DAO: WS_SEL Position */ +#define I2Sn_DAO_WS_SEL_Msk (0x01UL << I2Sn_DAO_WS_SEL_Pos) /*!< I2Sn DAO: WS_SEL Mask */ +#define I2Sn_DAO_WS_HALFPERIOD_Pos 6 /*!< I2Sn DAO: WS_HALFPERIOD Position */ +#define I2Sn_DAO_WS_HALFPERIOD_Msk (0x000001ffUL << I2Sn_DAO_WS_HALFPERIOD_Pos) /*!< I2Sn DAO: WS_HALFPERIOD Mask */ +#define I2Sn_DAO_MUTE_Pos 15 /*!< I2Sn DAO: MUTE Position */ +#define I2Sn_DAO_MUTE_Msk (0x01UL << I2Sn_DAO_MUTE_Pos) /*!< I2Sn DAO: MUTE Mask */ + +/* ---------------------------------- I2Sn_DAI ---------------------------------- */ +#define I2Sn_DAI_WORDWIDTH_Pos 0 /*!< I2Sn DAI: WORDWIDTH Position */ +#define I2Sn_DAI_WORDWIDTH_Msk (0x03UL << I2Sn_DAI_WORDWIDTH_Pos) /*!< I2Sn DAI: WORDWIDTH Mask */ +#define I2Sn_DAI_MONO_Pos 2 /*!< I2Sn DAI: MONO Position */ +#define I2Sn_DAI_MONO_Msk (0x01UL << I2Sn_DAI_MONO_Pos) /*!< I2Sn DAI: MONO Mask */ +#define I2Sn_DAI_STOP_Pos 3 /*!< I2Sn DAI: STOP Position */ +#define I2Sn_DAI_STOP_Msk (0x01UL << I2Sn_DAI_STOP_Pos) /*!< I2Sn DAI: STOP Mask */ +#define I2Sn_DAI_RESET_Pos 4 /*!< I2Sn DAI: RESET Position */ +#define I2Sn_DAI_RESET_Msk (0x01UL << I2Sn_DAI_RESET_Pos) /*!< I2Sn DAI: RESET Mask */ +#define I2Sn_DAI_WS_SEL_Pos 5 /*!< I2Sn DAI: WS_SEL Position */ +#define I2Sn_DAI_WS_SEL_Msk (0x01UL << I2Sn_DAI_WS_SEL_Pos) /*!< I2Sn DAI: WS_SEL Mask */ +#define I2Sn_DAI_WS_HALFPERIOD_Pos 6 /*!< I2Sn DAI: WS_HALFPERIOD Position */ +#define I2Sn_DAI_WS_HALFPERIOD_Msk (0x000001ffUL << I2Sn_DAI_WS_HALFPERIOD_Pos) /*!< I2Sn DAI: WS_HALFPERIOD Mask */ + +/* --------------------------------- I2Sn_TXFIFO -------------------------------- */ +#define I2Sn_TXFIFO_I2STXFIFO_Pos 0 /*!< I2Sn TXFIFO: I2STXFIFO Position */ +#define I2Sn_TXFIFO_I2STXFIFO_Msk (0xffffffffUL << I2Sn_TXFIFO_I2STXFIFO_Pos) /*!< I2Sn TXFIFO: I2STXFIFO Mask */ + +/* --------------------------------- I2Sn_RXFIFO -------------------------------- */ +#define I2Sn_RXFIFO_I2SRXFIFO_Pos 0 /*!< I2Sn RXFIFO: I2SRXFIFO Position */ +#define I2Sn_RXFIFO_I2SRXFIFO_Msk (0xffffffffUL << I2Sn_RXFIFO_I2SRXFIFO_Pos) /*!< I2Sn RXFIFO: I2SRXFIFO Mask */ + +/* --------------------------------- I2Sn_STATE --------------------------------- */ +#define I2Sn_STATE_IRQ_Pos 0 /*!< I2Sn STATE: IRQ Position */ +#define I2Sn_STATE_IRQ_Msk (0x01UL << I2Sn_STATE_IRQ_Pos) /*!< I2Sn STATE: IRQ Mask */ +#define I2Sn_STATE_DMAREQ1_Pos 1 /*!< I2Sn STATE: DMAREQ1 Position */ +#define I2Sn_STATE_DMAREQ1_Msk (0x01UL << I2Sn_STATE_DMAREQ1_Pos) /*!< I2Sn STATE: DMAREQ1 Mask */ +#define I2Sn_STATE_DMAREQ2_Pos 2 /*!< I2Sn STATE: DMAREQ2 Position */ +#define I2Sn_STATE_DMAREQ2_Msk (0x01UL << I2Sn_STATE_DMAREQ2_Pos) /*!< I2Sn STATE: DMAREQ2 Mask */ +#define I2Sn_STATE_RX_LEVEL_Pos 8 /*!< I2Sn STATE: RX_LEVEL Position */ +#define I2Sn_STATE_RX_LEVEL_Msk (0x0fUL << I2Sn_STATE_RX_LEVEL_Pos) /*!< I2Sn STATE: RX_LEVEL Mask */ +#define I2Sn_STATE_TX_LEVEL_Pos 16 /*!< I2Sn STATE: TX_LEVEL Position */ +#define I2Sn_STATE_TX_LEVEL_Msk (0x0fUL << I2Sn_STATE_TX_LEVEL_Pos) /*!< I2Sn STATE: TX_LEVEL Mask */ + +/* ---------------------------------- I2Sn_DMA1 --------------------------------- */ +#define I2Sn_DMA1_RX_DMA1_ENABLE_Pos 0 /*!< I2Sn DMA1: RX_DMA1_ENABLE Position */ +#define I2Sn_DMA1_RX_DMA1_ENABLE_Msk (0x01UL << I2Sn_DMA1_RX_DMA1_ENABLE_Pos) /*!< I2Sn DMA1: RX_DMA1_ENABLE Mask */ +#define I2Sn_DMA1_TX_DMA1_ENABLE_Pos 1 /*!< I2Sn DMA1: TX_DMA1_ENABLE Position */ +#define I2Sn_DMA1_TX_DMA1_ENABLE_Msk (0x01UL << I2Sn_DMA1_TX_DMA1_ENABLE_Pos) /*!< I2Sn DMA1: TX_DMA1_ENABLE Mask */ +#define I2Sn_DMA1_RX_DEPTH_DMA1_Pos 8 /*!< I2Sn DMA1: RX_DEPTH_DMA1 Position */ +#define I2Sn_DMA1_RX_DEPTH_DMA1_Msk (0x0fUL << I2Sn_DMA1_RX_DEPTH_DMA1_Pos) /*!< I2Sn DMA1: RX_DEPTH_DMA1 Mask */ +#define I2Sn_DMA1_TX_DEPTH_DMA1_Pos 16 /*!< I2Sn DMA1: TX_DEPTH_DMA1 Position */ +#define I2Sn_DMA1_TX_DEPTH_DMA1_Msk (0x0fUL << I2Sn_DMA1_TX_DEPTH_DMA1_Pos) /*!< I2Sn DMA1: TX_DEPTH_DMA1 Mask */ + +/* ---------------------------------- I2Sn_DMA2 --------------------------------- */ +#define I2Sn_DMA2_RX_DMA2_ENABLE_Pos 0 /*!< I2Sn DMA2: RX_DMA2_ENABLE Position */ +#define I2Sn_DMA2_RX_DMA2_ENABLE_Msk (0x01UL << I2Sn_DMA2_RX_DMA2_ENABLE_Pos) /*!< I2Sn DMA2: RX_DMA2_ENABLE Mask */ +#define I2Sn_DMA2_TX_DMA2_ENABLE_Pos 1 /*!< I2Sn DMA2: TX_DMA2_ENABLE Position */ +#define I2Sn_DMA2_TX_DMA2_ENABLE_Msk (0x01UL << I2Sn_DMA2_TX_DMA2_ENABLE_Pos) /*!< I2Sn DMA2: TX_DMA2_ENABLE Mask */ +#define I2Sn_DMA2_RX_DEPTH_DMA2_Pos 8 /*!< I2Sn DMA2: RX_DEPTH_DMA2 Position */ +#define I2Sn_DMA2_RX_DEPTH_DMA2_Msk (0x0fUL << I2Sn_DMA2_RX_DEPTH_DMA2_Pos) /*!< I2Sn DMA2: RX_DEPTH_DMA2 Mask */ +#define I2Sn_DMA2_TX_DEPTH_DMA2_Pos 16 /*!< I2Sn DMA2: TX_DEPTH_DMA2 Position */ +#define I2Sn_DMA2_TX_DEPTH_DMA2_Msk (0x0fUL << I2Sn_DMA2_TX_DEPTH_DMA2_Pos) /*!< I2Sn DMA2: TX_DEPTH_DMA2 Mask */ + +/* ---------------------------------- I2Sn_IRQ ---------------------------------- */ +#define I2Sn_IRQ_RX_IRQ_ENABLE_Pos 0 /*!< I2Sn IRQ: RX_IRQ_ENABLE Position */ +#define I2Sn_IRQ_RX_IRQ_ENABLE_Msk (0x01UL << I2Sn_IRQ_RX_IRQ_ENABLE_Pos) /*!< I2Sn IRQ: RX_IRQ_ENABLE Mask */ +#define I2Sn_IRQ_TX_IRQ_ENABLE_Pos 1 /*!< I2Sn IRQ: TX_IRQ_ENABLE Position */ +#define I2Sn_IRQ_TX_IRQ_ENABLE_Msk (0x01UL << I2Sn_IRQ_TX_IRQ_ENABLE_Pos) /*!< I2Sn IRQ: TX_IRQ_ENABLE Mask */ +#define I2Sn_IRQ_RX_DEPTH_IRQ_Pos 8 /*!< I2Sn IRQ: RX_DEPTH_IRQ Position */ +#define I2Sn_IRQ_RX_DEPTH_IRQ_Msk (0x0fUL << I2Sn_IRQ_RX_DEPTH_IRQ_Pos) /*!< I2Sn IRQ: RX_DEPTH_IRQ Mask */ +#define I2Sn_IRQ_TX_DEPTH_IRQ_Pos 16 /*!< I2Sn IRQ: TX_DEPTH_IRQ Position */ +#define I2Sn_IRQ_TX_DEPTH_IRQ_Msk (0x0fUL << I2Sn_IRQ_TX_DEPTH_IRQ_Pos) /*!< I2Sn IRQ: TX_DEPTH_IRQ Mask */ + +/* --------------------------------- I2Sn_TXRATE -------------------------------- */ +#define I2Sn_TXRATE_Y_DIVIDER_Pos 0 /*!< I2Sn TXRATE: Y_DIVIDER Position */ +#define I2Sn_TXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2Sn_TXRATE_Y_DIVIDER_Pos) /*!< I2Sn TXRATE: Y_DIVIDER Mask */ +#define I2Sn_TXRATE_X_DIVIDER_Pos 8 /*!< I2Sn TXRATE: X_DIVIDER Position */ +#define I2Sn_TXRATE_X_DIVIDER_Msk (0x000000ffUL << I2Sn_TXRATE_X_DIVIDER_Pos) /*!< I2Sn TXRATE: X_DIVIDER Mask */ + +/* --------------------------------- I2Sn_RXRATE -------------------------------- */ +#define I2Sn_RXRATE_Y_DIVIDER_Pos 0 /*!< I2Sn RXRATE: Y_DIVIDER Position */ +#define I2Sn_RXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2Sn_RXRATE_Y_DIVIDER_Pos) /*!< I2Sn RXRATE: Y_DIVIDER Mask */ +#define I2Sn_RXRATE_X_DIVIDER_Pos 8 /*!< I2Sn RXRATE: X_DIVIDER Position */ +#define I2Sn_RXRATE_X_DIVIDER_Msk (0x000000ffUL << I2Sn_RXRATE_X_DIVIDER_Pos) /*!< I2Sn RXRATE: X_DIVIDER Mask */ + +/* ------------------------------- I2Sn_TXBITRATE ------------------------------- */ +#define I2Sn_TXBITRATE_TX_BITRATE_Pos 0 /*!< I2Sn TXBITRATE: TX_BITRATE Position */ +#define I2Sn_TXBITRATE_TX_BITRATE_Msk (0x3fUL << I2Sn_TXBITRATE_TX_BITRATE_Pos) /*!< I2Sn TXBITRATE: TX_BITRATE Mask */ + +/* ------------------------------- I2Sn_RXBITRATE ------------------------------- */ +#define I2Sn_RXBITRATE_RX_BITRATE_Pos 0 /*!< I2Sn RXBITRATE: RX_BITRATE Position */ +#define I2Sn_RXBITRATE_RX_BITRATE_Msk (0x3fUL << I2Sn_RXBITRATE_RX_BITRATE_Pos) /*!< I2Sn RXBITRATE: RX_BITRATE Mask */ + +/* --------------------------------- I2Sn_TXMODE -------------------------------- */ +#define I2Sn_TXMODE_TXCLKSEL_Pos 0 /*!< I2Sn TXMODE: TXCLKSEL Position */ +#define I2Sn_TXMODE_TXCLKSEL_Msk (0x03UL << I2Sn_TXMODE_TXCLKSEL_Pos) /*!< I2Sn TXMODE: TXCLKSEL Mask */ +#define I2Sn_TXMODE_TX4PIN_Pos 2 /*!< I2Sn TXMODE: TX4PIN Position */ +#define I2Sn_TXMODE_TX4PIN_Msk (0x01UL << I2Sn_TXMODE_TX4PIN_Pos) /*!< I2Sn TXMODE: TX4PIN Mask */ +#define I2Sn_TXMODE_TXMCENA_Pos 3 /*!< I2Sn TXMODE: TXMCENA Position */ +#define I2Sn_TXMODE_TXMCENA_Msk (0x01UL << I2Sn_TXMODE_TXMCENA_Pos) /*!< I2Sn TXMODE: TXMCENA Mask */ + +/* --------------------------------- I2Sn_RXMODE -------------------------------- */ +#define I2Sn_RXMODE_RXCLKSEL_Pos 0 /*!< I2Sn RXMODE: RXCLKSEL Position */ +#define I2Sn_RXMODE_RXCLKSEL_Msk (0x03UL << I2Sn_RXMODE_RXCLKSEL_Pos) /*!< I2Sn RXMODE: RXCLKSEL Mask */ +#define I2Sn_RXMODE_RX4PIN_Pos 2 /*!< I2Sn RXMODE: RX4PIN Position */ +#define I2Sn_RXMODE_RX4PIN_Msk (0x01UL << I2Sn_RXMODE_RX4PIN_Pos) /*!< I2Sn RXMODE: RX4PIN Mask */ +#define I2Sn_RXMODE_RXMCENA_Pos 3 /*!< I2Sn RXMODE: RXMCENA Position */ +#define I2Sn_RXMODE_RXMCENA_Msk (0x01UL << I2Sn_RXMODE_RXMCENA_Pos) /*!< I2Sn RXMODE: RXMCENA Mask */ + + +/* ================================================================================ */ +/* ================ struct 'I2S0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- I2S0_DAO ---------------------------------- */ +#define I2S0_DAO_WORDWIDTH_Pos 0 /*!< I2S0 DAO: WORDWIDTH Position */ +#define I2S0_DAO_WORDWIDTH_Msk (0x03UL << I2S0_DAO_WORDWIDTH_Pos) /*!< I2S0 DAO: WORDWIDTH Mask */ +#define I2S0_DAO_MONO_Pos 2 /*!< I2S0 DAO: MONO Position */ +#define I2S0_DAO_MONO_Msk (0x01UL << I2S0_DAO_MONO_Pos) /*!< I2S0 DAO: MONO Mask */ +#define I2S0_DAO_STOP_Pos 3 /*!< I2S0 DAO: STOP Position */ +#define I2S0_DAO_STOP_Msk (0x01UL << I2S0_DAO_STOP_Pos) /*!< I2S0 DAO: STOP Mask */ +#define I2S0_DAO_RESET_Pos 4 /*!< I2S0 DAO: RESET Position */ +#define I2S0_DAO_RESET_Msk (0x01UL << I2S0_DAO_RESET_Pos) /*!< I2S0 DAO: RESET Mask */ +#define I2S0_DAO_WS_SEL_Pos 5 /*!< I2S0 DAO: WS_SEL Position */ +#define I2S0_DAO_WS_SEL_Msk (0x01UL << I2S0_DAO_WS_SEL_Pos) /*!< I2S0 DAO: WS_SEL Mask */ +#define I2S0_DAO_WS_HALFPERIOD_Pos 6 /*!< I2S0 DAO: WS_HALFPERIOD Position */ +#define I2S0_DAO_WS_HALFPERIOD_Msk (0x000001ffUL << I2S0_DAO_WS_HALFPERIOD_Pos) /*!< I2S0 DAO: WS_HALFPERIOD Mask */ +#define I2S0_DAO_MUTE_Pos 15 /*!< I2S0 DAO: MUTE Position */ +#define I2S0_DAO_MUTE_Msk (0x01UL << I2S0_DAO_MUTE_Pos) /*!< I2S0 DAO: MUTE Mask */ + +/* ---------------------------------- I2S0_DAI ---------------------------------- */ +#define I2S0_DAI_WORDWIDTH_Pos 0 /*!< I2S0 DAI: WORDWIDTH Position */ +#define I2S0_DAI_WORDWIDTH_Msk (0x03UL << I2S0_DAI_WORDWIDTH_Pos) /*!< I2S0 DAI: WORDWIDTH Mask */ +#define I2S0_DAI_MONO_Pos 2 /*!< I2S0 DAI: MONO Position */ +#define I2S0_DAI_MONO_Msk (0x01UL << I2S0_DAI_MONO_Pos) /*!< I2S0 DAI: MONO Mask */ +#define I2S0_DAI_STOP_Pos 3 /*!< I2S0 DAI: STOP Position */ +#define I2S0_DAI_STOP_Msk (0x01UL << I2S0_DAI_STOP_Pos) /*!< I2S0 DAI: STOP Mask */ +#define I2S0_DAI_RESET_Pos 4 /*!< I2S0 DAI: RESET Position */ +#define I2S0_DAI_RESET_Msk (0x01UL << I2S0_DAI_RESET_Pos) /*!< I2S0 DAI: RESET Mask */ +#define I2S0_DAI_WS_SEL_Pos 5 /*!< I2S0 DAI: WS_SEL Position */ +#define I2S0_DAI_WS_SEL_Msk (0x01UL << I2S0_DAI_WS_SEL_Pos) /*!< I2S0 DAI: WS_SEL Mask */ +#define I2S0_DAI_WS_HALFPERIOD_Pos 6 /*!< I2S0 DAI: WS_HALFPERIOD Position */ +#define I2S0_DAI_WS_HALFPERIOD_Msk (0x000001ffUL << I2S0_DAI_WS_HALFPERIOD_Pos) /*!< I2S0 DAI: WS_HALFPERIOD Mask */ + +/* --------------------------------- I2S0_TXFIFO -------------------------------- */ +#define I2S0_TXFIFO_I2STXFIFO_Pos 0 /*!< I2S0 TXFIFO: I2STXFIFO Position */ +#define I2S0_TXFIFO_I2STXFIFO_Msk (0xffffffffUL << I2S0_TXFIFO_I2STXFIFO_Pos) /*!< I2S0 TXFIFO: I2STXFIFO Mask */ + +/* --------------------------------- I2S0_RXFIFO -------------------------------- */ +#define I2S0_RXFIFO_I2SRXFIFO_Pos 0 /*!< I2S0 RXFIFO: I2SRXFIFO Position */ +#define I2S0_RXFIFO_I2SRXFIFO_Msk (0xffffffffUL << I2S0_RXFIFO_I2SRXFIFO_Pos) /*!< I2S0 RXFIFO: I2SRXFIFO Mask */ + +/* --------------------------------- I2S0_STATE --------------------------------- */ +#define I2S0_STATE_IRQ_Pos 0 /*!< I2S0 STATE: IRQ Position */ +#define I2S0_STATE_IRQ_Msk (0x01UL << I2S0_STATE_IRQ_Pos) /*!< I2S0 STATE: IRQ Mask */ +#define I2S0_STATE_DMAREQ1_Pos 1 /*!< I2S0 STATE: DMAREQ1 Position */ +#define I2S0_STATE_DMAREQ1_Msk (0x01UL << I2S0_STATE_DMAREQ1_Pos) /*!< I2S0 STATE: DMAREQ1 Mask */ +#define I2S0_STATE_DMAREQ2_Pos 2 /*!< I2S0 STATE: DMAREQ2 Position */ +#define I2S0_STATE_DMAREQ2_Msk (0x01UL << I2S0_STATE_DMAREQ2_Pos) /*!< I2S0 STATE: DMAREQ2 Mask */ +#define I2S0_STATE_RX_LEVEL_Pos 8 /*!< I2S0 STATE: RX_LEVEL Position */ +#define I2S0_STATE_RX_LEVEL_Msk (0x0fUL << I2S0_STATE_RX_LEVEL_Pos) /*!< I2S0 STATE: RX_LEVEL Mask */ +#define I2S0_STATE_TX_LEVEL_Pos 16 /*!< I2S0 STATE: TX_LEVEL Position */ +#define I2S0_STATE_TX_LEVEL_Msk (0x0fUL << I2S0_STATE_TX_LEVEL_Pos) /*!< I2S0 STATE: TX_LEVEL Mask */ + +/* ---------------------------------- I2S0_DMA1 --------------------------------- */ +#define I2S0_DMA1_RX_DMA1_ENABLE_Pos 0 /*!< I2S0 DMA1: RX_DMA1_ENABLE Position */ +#define I2S0_DMA1_RX_DMA1_ENABLE_Msk (0x01UL << I2S0_DMA1_RX_DMA1_ENABLE_Pos) /*!< I2S0 DMA1: RX_DMA1_ENABLE Mask */ +#define I2S0_DMA1_TX_DMA1_ENABLE_Pos 1 /*!< I2S0 DMA1: TX_DMA1_ENABLE Position */ +#define I2S0_DMA1_TX_DMA1_ENABLE_Msk (0x01UL << I2S0_DMA1_TX_DMA1_ENABLE_Pos) /*!< I2S0 DMA1: TX_DMA1_ENABLE Mask */ +#define I2S0_DMA1_RX_DEPTH_DMA1_Pos 8 /*!< I2S0 DMA1: RX_DEPTH_DMA1 Position */ +#define I2S0_DMA1_RX_DEPTH_DMA1_Msk (0x0fUL << I2S0_DMA1_RX_DEPTH_DMA1_Pos) /*!< I2S0 DMA1: RX_DEPTH_DMA1 Mask */ +#define I2S0_DMA1_TX_DEPTH_DMA1_Pos 16 /*!< I2S0 DMA1: TX_DEPTH_DMA1 Position */ +#define I2S0_DMA1_TX_DEPTH_DMA1_Msk (0x0fUL << I2S0_DMA1_TX_DEPTH_DMA1_Pos) /*!< I2S0 DMA1: TX_DEPTH_DMA1 Mask */ + +/* ---------------------------------- I2S0_DMA2 --------------------------------- */ +#define I2S0_DMA2_RX_DMA2_ENABLE_Pos 0 /*!< I2S0 DMA2: RX_DMA2_ENABLE Position */ +#define I2S0_DMA2_RX_DMA2_ENABLE_Msk (0x01UL << I2S0_DMA2_RX_DMA2_ENABLE_Pos) /*!< I2S0 DMA2: RX_DMA2_ENABLE Mask */ +#define I2S0_DMA2_TX_DMA2_ENABLE_Pos 1 /*!< I2S0 DMA2: TX_DMA2_ENABLE Position */ +#define I2S0_DMA2_TX_DMA2_ENABLE_Msk (0x01UL << I2S0_DMA2_TX_DMA2_ENABLE_Pos) /*!< I2S0 DMA2: TX_DMA2_ENABLE Mask */ +#define I2S0_DMA2_RX_DEPTH_DMA2_Pos 8 /*!< I2S0 DMA2: RX_DEPTH_DMA2 Position */ +#define I2S0_DMA2_RX_DEPTH_DMA2_Msk (0x0fUL << I2S0_DMA2_RX_DEPTH_DMA2_Pos) /*!< I2S0 DMA2: RX_DEPTH_DMA2 Mask */ +#define I2S0_DMA2_TX_DEPTH_DMA2_Pos 16 /*!< I2S0 DMA2: TX_DEPTH_DMA2 Position */ +#define I2S0_DMA2_TX_DEPTH_DMA2_Msk (0x0fUL << I2S0_DMA2_TX_DEPTH_DMA2_Pos) /*!< I2S0 DMA2: TX_DEPTH_DMA2 Mask */ + +/* ---------------------------------- I2S0_IRQ ---------------------------------- */ +#define I2S0_IRQ_RX_IRQ_ENABLE_Pos 0 /*!< I2S0 IRQ: RX_IRQ_ENABLE Position */ +#define I2S0_IRQ_RX_IRQ_ENABLE_Msk (0x01UL << I2S0_IRQ_RX_IRQ_ENABLE_Pos) /*!< I2S0 IRQ: RX_IRQ_ENABLE Mask */ +#define I2S0_IRQ_TX_IRQ_ENABLE_Pos 1 /*!< I2S0 IRQ: TX_IRQ_ENABLE Position */ +#define I2S0_IRQ_TX_IRQ_ENABLE_Msk (0x01UL << I2S0_IRQ_TX_IRQ_ENABLE_Pos) /*!< I2S0 IRQ: TX_IRQ_ENABLE Mask */ +#define I2S0_IRQ_RX_DEPTH_IRQ_Pos 8 /*!< I2S0 IRQ: RX_DEPTH_IRQ Position */ +#define I2S0_IRQ_RX_DEPTH_IRQ_Msk (0x0fUL << I2S0_IRQ_RX_DEPTH_IRQ_Pos) /*!< I2S0 IRQ: RX_DEPTH_IRQ Mask */ +#define I2S0_IRQ_TX_DEPTH_IRQ_Pos 16 /*!< I2S0 IRQ: TX_DEPTH_IRQ Position */ +#define I2S0_IRQ_TX_DEPTH_IRQ_Msk (0x0fUL << I2S0_IRQ_TX_DEPTH_IRQ_Pos) /*!< I2S0 IRQ: TX_DEPTH_IRQ Mask */ + +/* --------------------------------- I2S0_TXRATE -------------------------------- */ +#define I2S0_TXRATE_Y_DIVIDER_Pos 0 /*!< I2S0 TXRATE: Y_DIVIDER Position */ +#define I2S0_TXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S0_TXRATE_Y_DIVIDER_Pos) /*!< I2S0 TXRATE: Y_DIVIDER Mask */ +#define I2S0_TXRATE_X_DIVIDER_Pos 8 /*!< I2S0 TXRATE: X_DIVIDER Position */ +#define I2S0_TXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S0_TXRATE_X_DIVIDER_Pos) /*!< I2S0 TXRATE: X_DIVIDER Mask */ + +/* --------------------------------- I2S0_RXRATE -------------------------------- */ +#define I2S0_RXRATE_Y_DIVIDER_Pos 0 /*!< I2S0 RXRATE: Y_DIVIDER Position */ +#define I2S0_RXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S0_RXRATE_Y_DIVIDER_Pos) /*!< I2S0 RXRATE: Y_DIVIDER Mask */ +#define I2S0_RXRATE_X_DIVIDER_Pos 8 /*!< I2S0 RXRATE: X_DIVIDER Position */ +#define I2S0_RXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S0_RXRATE_X_DIVIDER_Pos) /*!< I2S0 RXRATE: X_DIVIDER Mask */ + +/* ------------------------------- I2S0_TXBITRATE ------------------------------- */ +#define I2S0_TXBITRATE_TX_BITRATE_Pos 0 /*!< I2S0 TXBITRATE: TX_BITRATE Position */ +#define I2S0_TXBITRATE_TX_BITRATE_Msk (0x3fUL << I2S0_TXBITRATE_TX_BITRATE_Pos) /*!< I2S0 TXBITRATE: TX_BITRATE Mask */ + +/* ------------------------------- I2S0_RXBITRATE ------------------------------- */ +#define I2S0_RXBITRATE_RX_BITRATE_Pos 0 /*!< I2S0 RXBITRATE: RX_BITRATE Position */ +#define I2S0_RXBITRATE_RX_BITRATE_Msk (0x3fUL << I2S0_RXBITRATE_RX_BITRATE_Pos) /*!< I2S0 RXBITRATE: RX_BITRATE Mask */ + +/* --------------------------------- I2S0_TXMODE -------------------------------- */ +#define I2S0_TXMODE_TXCLKSEL_Pos 0 /*!< I2S0 TXMODE: TXCLKSEL Position */ +#define I2S0_TXMODE_TXCLKSEL_Msk (0x03UL << I2S0_TXMODE_TXCLKSEL_Pos) /*!< I2S0 TXMODE: TXCLKSEL Mask */ +#define I2S0_TXMODE_TX4PIN_Pos 2 /*!< I2S0 TXMODE: TX4PIN Position */ +#define I2S0_TXMODE_TX4PIN_Msk (0x01UL << I2S0_TXMODE_TX4PIN_Pos) /*!< I2S0 TXMODE: TX4PIN Mask */ +#define I2S0_TXMODE_TXMCENA_Pos 3 /*!< I2S0 TXMODE: TXMCENA Position */ +#define I2S0_TXMODE_TXMCENA_Msk (0x01UL << I2S0_TXMODE_TXMCENA_Pos) /*!< I2S0 TXMODE: TXMCENA Mask */ + +/* --------------------------------- I2S0_RXMODE -------------------------------- */ +#define I2S0_RXMODE_RXCLKSEL_Pos 0 /*!< I2S0 RXMODE: RXCLKSEL Position */ +#define I2S0_RXMODE_RXCLKSEL_Msk (0x03UL << I2S0_RXMODE_RXCLKSEL_Pos) /*!< I2S0 RXMODE: RXCLKSEL Mask */ +#define I2S0_RXMODE_RX4PIN_Pos 2 /*!< I2S0 RXMODE: RX4PIN Position */ +#define I2S0_RXMODE_RX4PIN_Msk (0x01UL << I2S0_RXMODE_RX4PIN_Pos) /*!< I2S0 RXMODE: RX4PIN Mask */ +#define I2S0_RXMODE_RXMCENA_Pos 3 /*!< I2S0 RXMODE: RXMCENA Position */ +#define I2S0_RXMODE_RXMCENA_Msk (0x01UL << I2S0_RXMODE_RXMCENA_Pos) /*!< I2S0 RXMODE: RXMCENA Mask */ + + +/* ================================================================================ */ +/* ================ struct 'I2S1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- I2S1_DAO ---------------------------------- */ +#define I2S1_DAO_WORDWIDTH_Pos 0 /*!< I2S1 DAO: WORDWIDTH Position */ +#define I2S1_DAO_WORDWIDTH_Msk (0x03UL << I2S1_DAO_WORDWIDTH_Pos) /*!< I2S1 DAO: WORDWIDTH Mask */ +#define I2S1_DAO_MONO_Pos 2 /*!< I2S1 DAO: MONO Position */ +#define I2S1_DAO_MONO_Msk (0x01UL << I2S1_DAO_MONO_Pos) /*!< I2S1 DAO: MONO Mask */ +#define I2S1_DAO_STOP_Pos 3 /*!< I2S1 DAO: STOP Position */ +#define I2S1_DAO_STOP_Msk (0x01UL << I2S1_DAO_STOP_Pos) /*!< I2S1 DAO: STOP Mask */ +#define I2S1_DAO_RESET_Pos 4 /*!< I2S1 DAO: RESET Position */ +#define I2S1_DAO_RESET_Msk (0x01UL << I2S1_DAO_RESET_Pos) /*!< I2S1 DAO: RESET Mask */ +#define I2S1_DAO_WS_SEL_Pos 5 /*!< I2S1 DAO: WS_SEL Position */ +#define I2S1_DAO_WS_SEL_Msk (0x01UL << I2S1_DAO_WS_SEL_Pos) /*!< I2S1 DAO: WS_SEL Mask */ +#define I2S1_DAO_WS_HALFPERIOD_Pos 6 /*!< I2S1 DAO: WS_HALFPERIOD Position */ +#define I2S1_DAO_WS_HALFPERIOD_Msk (0x000001ffUL << I2S1_DAO_WS_HALFPERIOD_Pos) /*!< I2S1 DAO: WS_HALFPERIOD Mask */ +#define I2S1_DAO_MUTE_Pos 15 /*!< I2S1 DAO: MUTE Position */ +#define I2S1_DAO_MUTE_Msk (0x01UL << I2S1_DAO_MUTE_Pos) /*!< I2S1 DAO: MUTE Mask */ + +/* ---------------------------------- I2S1_DAI ---------------------------------- */ +#define I2S1_DAI_WORDWIDTH_Pos 0 /*!< I2S1 DAI: WORDWIDTH Position */ +#define I2S1_DAI_WORDWIDTH_Msk (0x03UL << I2S1_DAI_WORDWIDTH_Pos) /*!< I2S1 DAI: WORDWIDTH Mask */ +#define I2S1_DAI_MONO_Pos 2 /*!< I2S1 DAI: MONO Position */ +#define I2S1_DAI_MONO_Msk (0x01UL << I2S1_DAI_MONO_Pos) /*!< I2S1 DAI: MONO Mask */ +#define I2S1_DAI_STOP_Pos 3 /*!< I2S1 DAI: STOP Position */ +#define I2S1_DAI_STOP_Msk (0x01UL << I2S1_DAI_STOP_Pos) /*!< I2S1 DAI: STOP Mask */ +#define I2S1_DAI_RESET_Pos 4 /*!< I2S1 DAI: RESET Position */ +#define I2S1_DAI_RESET_Msk (0x01UL << I2S1_DAI_RESET_Pos) /*!< I2S1 DAI: RESET Mask */ +#define I2S1_DAI_WS_SEL_Pos 5 /*!< I2S1 DAI: WS_SEL Position */ +#define I2S1_DAI_WS_SEL_Msk (0x01UL << I2S1_DAI_WS_SEL_Pos) /*!< I2S1 DAI: WS_SEL Mask */ +#define I2S1_DAI_WS_HALFPERIOD_Pos 6 /*!< I2S1 DAI: WS_HALFPERIOD Position */ +#define I2S1_DAI_WS_HALFPERIOD_Msk (0x000001ffUL << I2S1_DAI_WS_HALFPERIOD_Pos) /*!< I2S1 DAI: WS_HALFPERIOD Mask */ + +/* --------------------------------- I2S1_TXFIFO -------------------------------- */ +#define I2S1_TXFIFO_I2STXFIFO_Pos 0 /*!< I2S1 TXFIFO: I2STXFIFO Position */ +#define I2S1_TXFIFO_I2STXFIFO_Msk (0xffffffffUL << I2S1_TXFIFO_I2STXFIFO_Pos) /*!< I2S1 TXFIFO: I2STXFIFO Mask */ + +/* --------------------------------- I2S1_RXFIFO -------------------------------- */ +#define I2S1_RXFIFO_I2SRXFIFO_Pos 0 /*!< I2S1 RXFIFO: I2SRXFIFO Position */ +#define I2S1_RXFIFO_I2SRXFIFO_Msk (0xffffffffUL << I2S1_RXFIFO_I2SRXFIFO_Pos) /*!< I2S1 RXFIFO: I2SRXFIFO Mask */ + +/* --------------------------------- I2S1_STATE --------------------------------- */ +#define I2S1_STATE_IRQ_Pos 0 /*!< I2S1 STATE: IRQ Position */ +#define I2S1_STATE_IRQ_Msk (0x01UL << I2S1_STATE_IRQ_Pos) /*!< I2S1 STATE: IRQ Mask */ +#define I2S1_STATE_DMAREQ1_Pos 1 /*!< I2S1 STATE: DMAREQ1 Position */ +#define I2S1_STATE_DMAREQ1_Msk (0x01UL << I2S1_STATE_DMAREQ1_Pos) /*!< I2S1 STATE: DMAREQ1 Mask */ +#define I2S1_STATE_DMAREQ2_Pos 2 /*!< I2S1 STATE: DMAREQ2 Position */ +#define I2S1_STATE_DMAREQ2_Msk (0x01UL << I2S1_STATE_DMAREQ2_Pos) /*!< I2S1 STATE: DMAREQ2 Mask */ +#define I2S1_STATE_RX_LEVEL_Pos 8 /*!< I2S1 STATE: RX_LEVEL Position */ +#define I2S1_STATE_RX_LEVEL_Msk (0x0fUL << I2S1_STATE_RX_LEVEL_Pos) /*!< I2S1 STATE: RX_LEVEL Mask */ +#define I2S1_STATE_TX_LEVEL_Pos 16 /*!< I2S1 STATE: TX_LEVEL Position */ +#define I2S1_STATE_TX_LEVEL_Msk (0x0fUL << I2S1_STATE_TX_LEVEL_Pos) /*!< I2S1 STATE: TX_LEVEL Mask */ + +/* ---------------------------------- I2S1_DMA1 --------------------------------- */ +#define I2S1_DMA1_RX_DMA1_ENABLE_Pos 0 /*!< I2S1 DMA1: RX_DMA1_ENABLE Position */ +#define I2S1_DMA1_RX_DMA1_ENABLE_Msk (0x01UL << I2S1_DMA1_RX_DMA1_ENABLE_Pos) /*!< I2S1 DMA1: RX_DMA1_ENABLE Mask */ +#define I2S1_DMA1_TX_DMA1_ENABLE_Pos 1 /*!< I2S1 DMA1: TX_DMA1_ENABLE Position */ +#define I2S1_DMA1_TX_DMA1_ENABLE_Msk (0x01UL << I2S1_DMA1_TX_DMA1_ENABLE_Pos) /*!< I2S1 DMA1: TX_DMA1_ENABLE Mask */ +#define I2S1_DMA1_RX_DEPTH_DMA1_Pos 8 /*!< I2S1 DMA1: RX_DEPTH_DMA1 Position */ +#define I2S1_DMA1_RX_DEPTH_DMA1_Msk (0x0fUL << I2S1_DMA1_RX_DEPTH_DMA1_Pos) /*!< I2S1 DMA1: RX_DEPTH_DMA1 Mask */ +#define I2S1_DMA1_TX_DEPTH_DMA1_Pos 16 /*!< I2S1 DMA1: TX_DEPTH_DMA1 Position */ +#define I2S1_DMA1_TX_DEPTH_DMA1_Msk (0x0fUL << I2S1_DMA1_TX_DEPTH_DMA1_Pos) /*!< I2S1 DMA1: TX_DEPTH_DMA1 Mask */ + +/* ---------------------------------- I2S1_DMA2 --------------------------------- */ +#define I2S1_DMA2_RX_DMA2_ENABLE_Pos 0 /*!< I2S1 DMA2: RX_DMA2_ENABLE Position */ +#define I2S1_DMA2_RX_DMA2_ENABLE_Msk (0x01UL << I2S1_DMA2_RX_DMA2_ENABLE_Pos) /*!< I2S1 DMA2: RX_DMA2_ENABLE Mask */ +#define I2S1_DMA2_TX_DMA2_ENABLE_Pos 1 /*!< I2S1 DMA2: TX_DMA2_ENABLE Position */ +#define I2S1_DMA2_TX_DMA2_ENABLE_Msk (0x01UL << I2S1_DMA2_TX_DMA2_ENABLE_Pos) /*!< I2S1 DMA2: TX_DMA2_ENABLE Mask */ +#define I2S1_DMA2_RX_DEPTH_DMA2_Pos 8 /*!< I2S1 DMA2: RX_DEPTH_DMA2 Position */ +#define I2S1_DMA2_RX_DEPTH_DMA2_Msk (0x0fUL << I2S1_DMA2_RX_DEPTH_DMA2_Pos) /*!< I2S1 DMA2: RX_DEPTH_DMA2 Mask */ +#define I2S1_DMA2_TX_DEPTH_DMA2_Pos 16 /*!< I2S1 DMA2: TX_DEPTH_DMA2 Position */ +#define I2S1_DMA2_TX_DEPTH_DMA2_Msk (0x0fUL << I2S1_DMA2_TX_DEPTH_DMA2_Pos) /*!< I2S1 DMA2: TX_DEPTH_DMA2 Mask */ + +/* ---------------------------------- I2S1_IRQ ---------------------------------- */ +#define I2S1_IRQ_RX_IRQ_ENABLE_Pos 0 /*!< I2S1 IRQ: RX_IRQ_ENABLE Position */ +#define I2S1_IRQ_RX_IRQ_ENABLE_Msk (0x01UL << I2S1_IRQ_RX_IRQ_ENABLE_Pos) /*!< I2S1 IRQ: RX_IRQ_ENABLE Mask */ +#define I2S1_IRQ_TX_IRQ_ENABLE_Pos 1 /*!< I2S1 IRQ: TX_IRQ_ENABLE Position */ +#define I2S1_IRQ_TX_IRQ_ENABLE_Msk (0x01UL << I2S1_IRQ_TX_IRQ_ENABLE_Pos) /*!< I2S1 IRQ: TX_IRQ_ENABLE Mask */ +#define I2S1_IRQ_RX_DEPTH_IRQ_Pos 8 /*!< I2S1 IRQ: RX_DEPTH_IRQ Position */ +#define I2S1_IRQ_RX_DEPTH_IRQ_Msk (0x0fUL << I2S1_IRQ_RX_DEPTH_IRQ_Pos) /*!< I2S1 IRQ: RX_DEPTH_IRQ Mask */ +#define I2S1_IRQ_TX_DEPTH_IRQ_Pos 16 /*!< I2S1 IRQ: TX_DEPTH_IRQ Position */ +#define I2S1_IRQ_TX_DEPTH_IRQ_Msk (0x0fUL << I2S1_IRQ_TX_DEPTH_IRQ_Pos) /*!< I2S1 IRQ: TX_DEPTH_IRQ Mask */ + +/* --------------------------------- I2S1_TXRATE -------------------------------- */ +#define I2S1_TXRATE_Y_DIVIDER_Pos 0 /*!< I2S1 TXRATE: Y_DIVIDER Position */ +#define I2S1_TXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S1_TXRATE_Y_DIVIDER_Pos) /*!< I2S1 TXRATE: Y_DIVIDER Mask */ +#define I2S1_TXRATE_X_DIVIDER_Pos 8 /*!< I2S1 TXRATE: X_DIVIDER Position */ +#define I2S1_TXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S1_TXRATE_X_DIVIDER_Pos) /*!< I2S1 TXRATE: X_DIVIDER Mask */ + +/* --------------------------------- I2S1_RXRATE -------------------------------- */ +#define I2S1_RXRATE_Y_DIVIDER_Pos 0 /*!< I2S1 RXRATE: Y_DIVIDER Position */ +#define I2S1_RXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S1_RXRATE_Y_DIVIDER_Pos) /*!< I2S1 RXRATE: Y_DIVIDER Mask */ +#define I2S1_RXRATE_X_DIVIDER_Pos 8 /*!< I2S1 RXRATE: X_DIVIDER Position */ +#define I2S1_RXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S1_RXRATE_X_DIVIDER_Pos) /*!< I2S1 RXRATE: X_DIVIDER Mask */ + +/* ------------------------------- I2S1_TXBITRATE ------------------------------- */ +#define I2S1_TXBITRATE_TX_BITRATE_Pos 0 /*!< I2S1 TXBITRATE: TX_BITRATE Position */ +#define I2S1_TXBITRATE_TX_BITRATE_Msk (0x3fUL << I2S1_TXBITRATE_TX_BITRATE_Pos) /*!< I2S1 TXBITRATE: TX_BITRATE Mask */ + +/* ------------------------------- I2S1_RXBITRATE ------------------------------- */ +#define I2S1_RXBITRATE_RX_BITRATE_Pos 0 /*!< I2S1 RXBITRATE: RX_BITRATE Position */ +#define I2S1_RXBITRATE_RX_BITRATE_Msk (0x3fUL << I2S1_RXBITRATE_RX_BITRATE_Pos) /*!< I2S1 RXBITRATE: RX_BITRATE Mask */ + +/* --------------------------------- I2S1_TXMODE -------------------------------- */ +#define I2S1_TXMODE_TXCLKSEL_Pos 0 /*!< I2S1 TXMODE: TXCLKSEL Position */ +#define I2S1_TXMODE_TXCLKSEL_Msk (0x03UL << I2S1_TXMODE_TXCLKSEL_Pos) /*!< I2S1 TXMODE: TXCLKSEL Mask */ +#define I2S1_TXMODE_TX4PIN_Pos 2 /*!< I2S1 TXMODE: TX4PIN Position */ +#define I2S1_TXMODE_TX4PIN_Msk (0x01UL << I2S1_TXMODE_TX4PIN_Pos) /*!< I2S1 TXMODE: TX4PIN Mask */ +#define I2S1_TXMODE_TXMCENA_Pos 3 /*!< I2S1 TXMODE: TXMCENA Position */ +#define I2S1_TXMODE_TXMCENA_Msk (0x01UL << I2S1_TXMODE_TXMCENA_Pos) /*!< I2S1 TXMODE: TXMCENA Mask */ + +/* --------------------------------- I2S1_RXMODE -------------------------------- */ +#define I2S1_RXMODE_RXCLKSEL_Pos 0 /*!< I2S1 RXMODE: RXCLKSEL Position */ +#define I2S1_RXMODE_RXCLKSEL_Msk (0x03UL << I2S1_RXMODE_RXCLKSEL_Pos) /*!< I2S1 RXMODE: RXCLKSEL Mask */ +#define I2S1_RXMODE_RX4PIN_Pos 2 /*!< I2S1 RXMODE: RX4PIN Position */ +#define I2S1_RXMODE_RX4PIN_Msk (0x01UL << I2S1_RXMODE_RX4PIN_Pos) /*!< I2S1 RXMODE: RX4PIN Mask */ +#define I2S1_RXMODE_RXMCENA_Pos 3 /*!< I2S1 RXMODE: RXMCENA Position */ +#define I2S1_RXMODE_RXMCENA_Msk (0x01UL << I2S1_RXMODE_RXMCENA_Pos) /*!< I2S1 RXMODE: RXMCENA Mask */ + + +/* ================================================================================ */ +/* ================ Group 'C_CANn' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- C_CANn_CNTL -------------------------------- */ +#define C_CANn_CNTL_INIT_Pos 0 /*!< C_CANn CNTL: INIT Position */ +#define C_CANn_CNTL_INIT_Msk (0x01UL << C_CANn_CNTL_INIT_Pos) /*!< C_CANn CNTL: INIT Mask */ +#define C_CANn_CNTL_IE_Pos 1 /*!< C_CANn CNTL: IE Position */ +#define C_CANn_CNTL_IE_Msk (0x01UL << C_CANn_CNTL_IE_Pos) /*!< C_CANn CNTL: IE Mask */ +#define C_CANn_CNTL_SIE_Pos 2 /*!< C_CANn CNTL: SIE Position */ +#define C_CANn_CNTL_SIE_Msk (0x01UL << C_CANn_CNTL_SIE_Pos) /*!< C_CANn CNTL: SIE Mask */ +#define C_CANn_CNTL_EIE_Pos 3 /*!< C_CANn CNTL: EIE Position */ +#define C_CANn_CNTL_EIE_Msk (0x01UL << C_CANn_CNTL_EIE_Pos) /*!< C_CANn CNTL: EIE Mask */ +#define C_CANn_CNTL_DAR_Pos 5 /*!< C_CANn CNTL: DAR Position */ +#define C_CANn_CNTL_DAR_Msk (0x01UL << C_CANn_CNTL_DAR_Pos) /*!< C_CANn CNTL: DAR Mask */ +#define C_CANn_CNTL_CCE_Pos 6 /*!< C_CANn CNTL: CCE Position */ +#define C_CANn_CNTL_CCE_Msk (0x01UL << C_CANn_CNTL_CCE_Pos) /*!< C_CANn CNTL: CCE Mask */ +#define C_CANn_CNTL_TEST_Pos 7 /*!< C_CANn CNTL: TEST Position */ +#define C_CANn_CNTL_TEST_Msk (0x01UL << C_CANn_CNTL_TEST_Pos) /*!< C_CANn CNTL: TEST Mask */ + +/* --------------------------------- C_CANn_STAT -------------------------------- */ +#define C_CANn_STAT_LEC_Pos 0 /*!< C_CANn STAT: LEC Position */ +#define C_CANn_STAT_LEC_Msk (0x07UL << C_CANn_STAT_LEC_Pos) /*!< C_CANn STAT: LEC Mask */ +#define C_CANn_STAT_TXOK_Pos 3 /*!< C_CANn STAT: TXOK Position */ +#define C_CANn_STAT_TXOK_Msk (0x01UL << C_CANn_STAT_TXOK_Pos) /*!< C_CANn STAT: TXOK Mask */ +#define C_CANn_STAT_RXOK_Pos 4 /*!< C_CANn STAT: RXOK Position */ +#define C_CANn_STAT_RXOK_Msk (0x01UL << C_CANn_STAT_RXOK_Pos) /*!< C_CANn STAT: RXOK Mask */ +#define C_CANn_STAT_EPASS_Pos 5 /*!< C_CANn STAT: EPASS Position */ +#define C_CANn_STAT_EPASS_Msk (0x01UL << C_CANn_STAT_EPASS_Pos) /*!< C_CANn STAT: EPASS Mask */ +#define C_CANn_STAT_EWARN_Pos 6 /*!< C_CANn STAT: EWARN Position */ +#define C_CANn_STAT_EWARN_Msk (0x01UL << C_CANn_STAT_EWARN_Pos) /*!< C_CANn STAT: EWARN Mask */ +#define C_CANn_STAT_BOFF_Pos 7 /*!< C_CANn STAT: BOFF Position */ +#define C_CANn_STAT_BOFF_Msk (0x01UL << C_CANn_STAT_BOFF_Pos) /*!< C_CANn STAT: BOFF Mask */ + +/* ---------------------------------- C_CANn_EC --------------------------------- */ +#define C_CANn_EC_TEC_7_0_Pos 0 /*!< C_CANn EC: TEC_7_0 Position */ +#define C_CANn_EC_TEC_7_0_Msk (0x000000ffUL << C_CANn_EC_TEC_7_0_Pos) /*!< C_CANn EC: TEC_7_0 Mask */ +#define C_CANn_EC_REC_6_0_Pos 8 /*!< C_CANn EC: REC_6_0 Position */ +#define C_CANn_EC_REC_6_0_Msk (0x7fUL << C_CANn_EC_REC_6_0_Pos) /*!< C_CANn EC: REC_6_0 Mask */ +#define C_CANn_EC_RP_Pos 15 /*!< C_CANn EC: RP Position */ +#define C_CANn_EC_RP_Msk (0x01UL << C_CANn_EC_RP_Pos) /*!< C_CANn EC: RP Mask */ + +/* ---------------------------------- C_CANn_BT --------------------------------- */ +#define C_CANn_BT_BRP_Pos 0 /*!< C_CANn BT: BRP Position */ +#define C_CANn_BT_BRP_Msk (0x3fUL << C_CANn_BT_BRP_Pos) /*!< C_CANn BT: BRP Mask */ +#define C_CANn_BT_SJW_Pos 6 /*!< C_CANn BT: SJW Position */ +#define C_CANn_BT_SJW_Msk (0x03UL << C_CANn_BT_SJW_Pos) /*!< C_CANn BT: SJW Mask */ +#define C_CANn_BT_TSEG1_Pos 8 /*!< C_CANn BT: TSEG1 Position */ +#define C_CANn_BT_TSEG1_Msk (0x0fUL << C_CANn_BT_TSEG1_Pos) /*!< C_CANn BT: TSEG1 Mask */ +#define C_CANn_BT_TSEG2_Pos 12 /*!< C_CANn BT: TSEG2 Position */ +#define C_CANn_BT_TSEG2_Msk (0x07UL << C_CANn_BT_TSEG2_Pos) /*!< C_CANn BT: TSEG2 Mask */ + +/* --------------------------------- C_CANn_INT --------------------------------- */ +#define C_CANn_INT_INTID15_0_Pos 0 /*!< C_CANn INT: INTID15_0 Position */ +#define C_CANn_INT_INTID15_0_Msk (0x0000ffffUL << C_CANn_INT_INTID15_0_Pos) /*!< C_CANn INT: INTID15_0 Mask */ + +/* --------------------------------- C_CANn_TEST -------------------------------- */ +#define C_CANn_TEST_BASIC_Pos 2 /*!< C_CANn TEST: BASIC Position */ +#define C_CANn_TEST_BASIC_Msk (0x01UL << C_CANn_TEST_BASIC_Pos) /*!< C_CANn TEST: BASIC Mask */ +#define C_CANn_TEST_SILENT_Pos 3 /*!< C_CANn TEST: SILENT Position */ +#define C_CANn_TEST_SILENT_Msk (0x01UL << C_CANn_TEST_SILENT_Pos) /*!< C_CANn TEST: SILENT Mask */ +#define C_CANn_TEST_LBACK_Pos 4 /*!< C_CANn TEST: LBACK Position */ +#define C_CANn_TEST_LBACK_Msk (0x01UL << C_CANn_TEST_LBACK_Pos) /*!< C_CANn TEST: LBACK Mask */ +#define C_CANn_TEST_TX1_0_Pos 5 /*!< C_CANn TEST: TX1_0 Position */ +#define C_CANn_TEST_TX1_0_Msk (0x03UL << C_CANn_TEST_TX1_0_Pos) /*!< C_CANn TEST: TX1_0 Mask */ +#define C_CANn_TEST_RX_Pos 7 /*!< C_CANn TEST: RX Position */ +#define C_CANn_TEST_RX_Msk (0x01UL << C_CANn_TEST_RX_Pos) /*!< C_CANn TEST: RX Mask */ + +/* --------------------------------- C_CANn_BRPE -------------------------------- */ +#define C_CANn_BRPE_BRPE_Pos 0 /*!< C_CANn BRPE: BRPE Position */ +#define C_CANn_BRPE_BRPE_Msk (0x0fUL << C_CANn_BRPE_BRPE_Pos) /*!< C_CANn BRPE: BRPE Mask */ + +/* ------------------------------ C_CANn_IF1_CMDREQ ----------------------------- */ +#define C_CANn_IF1_CMDREQ_MESSNUM_Pos 0 /*!< C_CANn IF1_CMDREQ: MESSNUM Position */ +#define C_CANn_IF1_CMDREQ_MESSNUM_Msk (0x3fUL << C_CANn_IF1_CMDREQ_MESSNUM_Pos) /*!< C_CANn IF1_CMDREQ: MESSNUM Mask */ +#define C_CANn_IF1_CMDREQ_BUSY_Pos 15 /*!< C_CANn IF1_CMDREQ: BUSY Position */ +#define C_CANn_IF1_CMDREQ_BUSY_Msk (0x01UL << C_CANn_IF1_CMDREQ_BUSY_Pos) /*!< C_CANn IF1_CMDREQ: BUSY Mask */ + +/* ----------------------------- C_CANn_IF1_CMDMSK_W ---------------------------- */ +#define C_CANn_IF1_CMDMSK_W_DATA_B_Pos 0 /*!< C_CANn IF1_CMDMSK_W: DATA_B Position */ +#define C_CANn_IF1_CMDMSK_W_DATA_B_Msk (0x01UL << C_CANn_IF1_CMDMSK_W_DATA_B_Pos) /*!< C_CANn IF1_CMDMSK_W: DATA_B Mask */ +#define C_CANn_IF1_CMDMSK_W_DATA_A_Pos 1 /*!< C_CANn IF1_CMDMSK_W: DATA_A Position */ +#define C_CANn_IF1_CMDMSK_W_DATA_A_Msk (0x01UL << C_CANn_IF1_CMDMSK_W_DATA_A_Pos) /*!< C_CANn IF1_CMDMSK_W: DATA_A Mask */ +#define C_CANn_IF1_CMDMSK_W_TXRQST_Pos 2 /*!< C_CANn IF1_CMDMSK_W: TXRQST Position */ +#define C_CANn_IF1_CMDMSK_W_TXRQST_Msk (0x01UL << C_CANn_IF1_CMDMSK_W_TXRQST_Pos) /*!< C_CANn IF1_CMDMSK_W: TXRQST Mask */ +#define C_CANn_IF1_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CANn IF1_CMDMSK_W: CLRINTPND Position */ +#define C_CANn_IF1_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CANn_IF1_CMDMSK_W_CLRINTPND_Pos) /*!< C_CANn IF1_CMDMSK_W: CLRINTPND Mask */ +#define C_CANn_IF1_CMDMSK_W_CTRL_Pos 4 /*!< C_CANn IF1_CMDMSK_W: CTRL Position */ +#define C_CANn_IF1_CMDMSK_W_CTRL_Msk (0x01UL << C_CANn_IF1_CMDMSK_W_CTRL_Pos) /*!< C_CANn IF1_CMDMSK_W: CTRL Mask */ +#define C_CANn_IF1_CMDMSK_W_ARB_Pos 5 /*!< C_CANn IF1_CMDMSK_W: ARB Position */ +#define C_CANn_IF1_CMDMSK_W_ARB_Msk (0x01UL << C_CANn_IF1_CMDMSK_W_ARB_Pos) /*!< C_CANn IF1_CMDMSK_W: ARB Mask */ +#define C_CANn_IF1_CMDMSK_W_MASK_Pos 6 /*!< C_CANn IF1_CMDMSK_W: MASK Position */ +#define C_CANn_IF1_CMDMSK_W_MASK_Msk (0x01UL << C_CANn_IF1_CMDMSK_W_MASK_Pos) /*!< C_CANn IF1_CMDMSK_W: MASK Mask */ +#define C_CANn_IF1_CMDMSK_W_WR_RD_Pos 7 /*!< C_CANn IF1_CMDMSK_W: WR_RD Position */ +#define C_CANn_IF1_CMDMSK_W_WR_RD_Msk (0x01UL << C_CANn_IF1_CMDMSK_W_WR_RD_Pos) /*!< C_CANn IF1_CMDMSK_W: WR_RD Mask */ + +/* ----------------------------- C_CANn_IF1_CMDMSK_R ---------------------------- */ +#define C_CANn_IF1_CMDMSK_R_DATA_B_Pos 0 /*!< C_CANn IF1_CMDMSK_R: DATA_B Position */ +#define C_CANn_IF1_CMDMSK_R_DATA_B_Msk (0x01UL << C_CANn_IF1_CMDMSK_R_DATA_B_Pos) /*!< C_CANn IF1_CMDMSK_R: DATA_B Mask */ +#define C_CANn_IF1_CMDMSK_R_DATA_A_Pos 1 /*!< C_CANn IF1_CMDMSK_R: DATA_A Position */ +#define C_CANn_IF1_CMDMSK_R_DATA_A_Msk (0x01UL << C_CANn_IF1_CMDMSK_R_DATA_A_Pos) /*!< C_CANn IF1_CMDMSK_R: DATA_A Mask */ +#define C_CANn_IF1_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CANn IF1_CMDMSK_R: NEWDAT Position */ +#define C_CANn_IF1_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CANn_IF1_CMDMSK_R_NEWDAT_Pos) /*!< C_CANn IF1_CMDMSK_R: NEWDAT Mask */ +#define C_CANn_IF1_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CANn IF1_CMDMSK_R: CLRINTPND Position */ +#define C_CANn_IF1_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CANn_IF1_CMDMSK_R_CLRINTPND_Pos) /*!< C_CANn IF1_CMDMSK_R: CLRINTPND Mask */ +#define C_CANn_IF1_CMDMSK_R_CTRL_Pos 4 /*!< C_CANn IF1_CMDMSK_R: CTRL Position */ +#define C_CANn_IF1_CMDMSK_R_CTRL_Msk (0x01UL << C_CANn_IF1_CMDMSK_R_CTRL_Pos) /*!< C_CANn IF1_CMDMSK_R: CTRL Mask */ +#define C_CANn_IF1_CMDMSK_R_ARB_Pos 5 /*!< C_CANn IF1_CMDMSK_R: ARB Position */ +#define C_CANn_IF1_CMDMSK_R_ARB_Msk (0x01UL << C_CANn_IF1_CMDMSK_R_ARB_Pos) /*!< C_CANn IF1_CMDMSK_R: ARB Mask */ +#define C_CANn_IF1_CMDMSK_R_MASK_Pos 6 /*!< C_CANn IF1_CMDMSK_R: MASK Position */ +#define C_CANn_IF1_CMDMSK_R_MASK_Msk (0x01UL << C_CANn_IF1_CMDMSK_R_MASK_Pos) /*!< C_CANn IF1_CMDMSK_R: MASK Mask */ +#define C_CANn_IF1_CMDMSK_R_WR_RD_Pos 7 /*!< C_CANn IF1_CMDMSK_R: WR_RD Position */ +#define C_CANn_IF1_CMDMSK_R_WR_RD_Msk (0x01UL << C_CANn_IF1_CMDMSK_R_WR_RD_Pos) /*!< C_CANn IF1_CMDMSK_R: WR_RD Mask */ + +/* ------------------------------- C_CANn_IF1_MSK1 ------------------------------ */ +#define C_CANn_IF1_MSK1_MSK15_0_Pos 0 /*!< C_CANn IF1_MSK1: MSK15_0 Position */ +#define C_CANn_IF1_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CANn_IF1_MSK1_MSK15_0_Pos) /*!< C_CANn IF1_MSK1: MSK15_0 Mask */ + +/* ------------------------------- C_CANn_IF1_MSK2 ------------------------------ */ +#define C_CANn_IF1_MSK2_MSK28_16_Pos 0 /*!< C_CANn IF1_MSK2: MSK28_16 Position */ +#define C_CANn_IF1_MSK2_MSK28_16_Msk (0x00001fffUL << C_CANn_IF1_MSK2_MSK28_16_Pos) /*!< C_CANn IF1_MSK2: MSK28_16 Mask */ +#define C_CANn_IF1_MSK2_MDIR_Pos 14 /*!< C_CANn IF1_MSK2: MDIR Position */ +#define C_CANn_IF1_MSK2_MDIR_Msk (0x01UL << C_CANn_IF1_MSK2_MDIR_Pos) /*!< C_CANn IF1_MSK2: MDIR Mask */ +#define C_CANn_IF1_MSK2_MXTD_Pos 15 /*!< C_CANn IF1_MSK2: MXTD Position */ +#define C_CANn_IF1_MSK2_MXTD_Msk (0x01UL << C_CANn_IF1_MSK2_MXTD_Pos) /*!< C_CANn IF1_MSK2: MXTD Mask */ + +/* ------------------------------- C_CANn_IF1_ARB1 ------------------------------ */ +#define C_CANn_IF1_ARB1_ID15_0_Pos 0 /*!< C_CANn IF1_ARB1: ID15_0 Position */ +#define C_CANn_IF1_ARB1_ID15_0_Msk (0x0000ffffUL << C_CANn_IF1_ARB1_ID15_0_Pos) /*!< C_CANn IF1_ARB1: ID15_0 Mask */ + +/* ------------------------------- C_CANn_IF1_ARB2 ------------------------------ */ +#define C_CANn_IF1_ARB2_ID28_16_Pos 0 /*!< C_CANn IF1_ARB2: ID28_16 Position */ +#define C_CANn_IF1_ARB2_ID28_16_Msk (0x00001fffUL << C_CANn_IF1_ARB2_ID28_16_Pos) /*!< C_CANn IF1_ARB2: ID28_16 Mask */ +#define C_CANn_IF1_ARB2_DIR_Pos 13 /*!< C_CANn IF1_ARB2: DIR Position */ +#define C_CANn_IF1_ARB2_DIR_Msk (0x01UL << C_CANn_IF1_ARB2_DIR_Pos) /*!< C_CANn IF1_ARB2: DIR Mask */ +#define C_CANn_IF1_ARB2_XTD_Pos 14 /*!< C_CANn IF1_ARB2: XTD Position */ +#define C_CANn_IF1_ARB2_XTD_Msk (0x01UL << C_CANn_IF1_ARB2_XTD_Pos) /*!< C_CANn IF1_ARB2: XTD Mask */ +#define C_CANn_IF1_ARB2_MSGVAL_Pos 15 /*!< C_CANn IF1_ARB2: MSGVAL Position */ +#define C_CANn_IF1_ARB2_MSGVAL_Msk (0x01UL << C_CANn_IF1_ARB2_MSGVAL_Pos) /*!< C_CANn IF1_ARB2: MSGVAL Mask */ + +/* ------------------------------ C_CANn_IF1_MCTRL ------------------------------ */ +#define C_CANn_IF1_MCTRL_DLC3_0_Pos 0 /*!< C_CANn IF1_MCTRL: DLC3_0 Position */ +#define C_CANn_IF1_MCTRL_DLC3_0_Msk (0x0fUL << C_CANn_IF1_MCTRL_DLC3_0_Pos) /*!< C_CANn IF1_MCTRL: DLC3_0 Mask */ +#define C_CANn_IF1_MCTRL_EOB_Pos 7 /*!< C_CANn IF1_MCTRL: EOB Position */ +#define C_CANn_IF1_MCTRL_EOB_Msk (0x01UL << C_CANn_IF1_MCTRL_EOB_Pos) /*!< C_CANn IF1_MCTRL: EOB Mask */ +#define C_CANn_IF1_MCTRL_TXRQST_Pos 8 /*!< C_CANn IF1_MCTRL: TXRQST Position */ +#define C_CANn_IF1_MCTRL_TXRQST_Msk (0x01UL << C_CANn_IF1_MCTRL_TXRQST_Pos) /*!< C_CANn IF1_MCTRL: TXRQST Mask */ +#define C_CANn_IF1_MCTRL_RMTEN_Pos 9 /*!< C_CANn IF1_MCTRL: RMTEN Position */ +#define C_CANn_IF1_MCTRL_RMTEN_Msk (0x01UL << C_CANn_IF1_MCTRL_RMTEN_Pos) /*!< C_CANn IF1_MCTRL: RMTEN Mask */ +#define C_CANn_IF1_MCTRL_RXIE_Pos 10 /*!< C_CANn IF1_MCTRL: RXIE Position */ +#define C_CANn_IF1_MCTRL_RXIE_Msk (0x01UL << C_CANn_IF1_MCTRL_RXIE_Pos) /*!< C_CANn IF1_MCTRL: RXIE Mask */ +#define C_CANn_IF1_MCTRL_TXIE_Pos 11 /*!< C_CANn IF1_MCTRL: TXIE Position */ +#define C_CANn_IF1_MCTRL_TXIE_Msk (0x01UL << C_CANn_IF1_MCTRL_TXIE_Pos) /*!< C_CANn IF1_MCTRL: TXIE Mask */ +#define C_CANn_IF1_MCTRL_UMASK_Pos 12 /*!< C_CANn IF1_MCTRL: UMASK Position */ +#define C_CANn_IF1_MCTRL_UMASK_Msk (0x01UL << C_CANn_IF1_MCTRL_UMASK_Pos) /*!< C_CANn IF1_MCTRL: UMASK Mask */ +#define C_CANn_IF1_MCTRL_INTPND_Pos 13 /*!< C_CANn IF1_MCTRL: INTPND Position */ +#define C_CANn_IF1_MCTRL_INTPND_Msk (0x01UL << C_CANn_IF1_MCTRL_INTPND_Pos) /*!< C_CANn IF1_MCTRL: INTPND Mask */ +#define C_CANn_IF1_MCTRL_MSGLST_Pos 14 /*!< C_CANn IF1_MCTRL: MSGLST Position */ +#define C_CANn_IF1_MCTRL_MSGLST_Msk (0x01UL << C_CANn_IF1_MCTRL_MSGLST_Pos) /*!< C_CANn IF1_MCTRL: MSGLST Mask */ +#define C_CANn_IF1_MCTRL_NEWDAT_Pos 15 /*!< C_CANn IF1_MCTRL: NEWDAT Position */ +#define C_CANn_IF1_MCTRL_NEWDAT_Msk (0x01UL << C_CANn_IF1_MCTRL_NEWDAT_Pos) /*!< C_CANn IF1_MCTRL: NEWDAT Mask */ + +/* ------------------------------- C_CANn_IF1_DA1 ------------------------------- */ +#define C_CANn_IF1_DA1_DATA0_Pos 0 /*!< C_CANn IF1_DA1: DATA0 Position */ +#define C_CANn_IF1_DA1_DATA0_Msk (0x000000ffUL << C_CANn_IF1_DA1_DATA0_Pos) /*!< C_CANn IF1_DA1: DATA0 Mask */ +#define C_CANn_IF1_DA1_DATA1_Pos 8 /*!< C_CANn IF1_DA1: DATA1 Position */ +#define C_CANn_IF1_DA1_DATA1_Msk (0x000000ffUL << C_CANn_IF1_DA1_DATA1_Pos) /*!< C_CANn IF1_DA1: DATA1 Mask */ + +/* ------------------------------- C_CANn_IF1_DA2 ------------------------------- */ +#define C_CANn_IF1_DA2_DATA2_Pos 0 /*!< C_CANn IF1_DA2: DATA2 Position */ +#define C_CANn_IF1_DA2_DATA2_Msk (0x000000ffUL << C_CANn_IF1_DA2_DATA2_Pos) /*!< C_CANn IF1_DA2: DATA2 Mask */ +#define C_CANn_IF1_DA2_DATA3_Pos 8 /*!< C_CANn IF1_DA2: DATA3 Position */ +#define C_CANn_IF1_DA2_DATA3_Msk (0x000000ffUL << C_CANn_IF1_DA2_DATA3_Pos) /*!< C_CANn IF1_DA2: DATA3 Mask */ + +/* ------------------------------- C_CANn_IF1_DB1 ------------------------------- */ +#define C_CANn_IF1_DB1_DATA4_Pos 0 /*!< C_CANn IF1_DB1: DATA4 Position */ +#define C_CANn_IF1_DB1_DATA4_Msk (0x000000ffUL << C_CANn_IF1_DB1_DATA4_Pos) /*!< C_CANn IF1_DB1: DATA4 Mask */ +#define C_CANn_IF1_DB1_DATA5_Pos 8 /*!< C_CANn IF1_DB1: DATA5 Position */ +#define C_CANn_IF1_DB1_DATA5_Msk (0x000000ffUL << C_CANn_IF1_DB1_DATA5_Pos) /*!< C_CANn IF1_DB1: DATA5 Mask */ + +/* ------------------------------- C_CANn_IF1_DB2 ------------------------------- */ +#define C_CANn_IF1_DB2_DATA6_Pos 0 /*!< C_CANn IF1_DB2: DATA6 Position */ +#define C_CANn_IF1_DB2_DATA6_Msk (0x000000ffUL << C_CANn_IF1_DB2_DATA6_Pos) /*!< C_CANn IF1_DB2: DATA6 Mask */ +#define C_CANn_IF1_DB2_DATA7_Pos 8 /*!< C_CANn IF1_DB2: DATA7 Position */ +#define C_CANn_IF1_DB2_DATA7_Msk (0x000000ffUL << C_CANn_IF1_DB2_DATA7_Pos) /*!< C_CANn IF1_DB2: DATA7 Mask */ + +/* ------------------------------ C_CANn_IF2_CMDREQ ----------------------------- */ +#define C_CANn_IF2_CMDREQ_MESSNUM_Pos 0 /*!< C_CANn IF2_CMDREQ: MESSNUM Position */ +#define C_CANn_IF2_CMDREQ_MESSNUM_Msk (0x3fUL << C_CANn_IF2_CMDREQ_MESSNUM_Pos) /*!< C_CANn IF2_CMDREQ: MESSNUM Mask */ +#define C_CANn_IF2_CMDREQ_BUSY_Pos 15 /*!< C_CANn IF2_CMDREQ: BUSY Position */ +#define C_CANn_IF2_CMDREQ_BUSY_Msk (0x01UL << C_CANn_IF2_CMDREQ_BUSY_Pos) /*!< C_CANn IF2_CMDREQ: BUSY Mask */ + +/* ----------------------------- C_CANn_IF2_CMDMSK_W ---------------------------- */ +#define C_CANn_IF2_CMDMSK_W_DATA_B_Pos 0 /*!< C_CANn IF2_CMDMSK_W: DATA_B Position */ +#define C_CANn_IF2_CMDMSK_W_DATA_B_Msk (0x01UL << C_CANn_IF2_CMDMSK_W_DATA_B_Pos) /*!< C_CANn IF2_CMDMSK_W: DATA_B Mask */ +#define C_CANn_IF2_CMDMSK_W_DATA_A_Pos 1 /*!< C_CANn IF2_CMDMSK_W: DATA_A Position */ +#define C_CANn_IF2_CMDMSK_W_DATA_A_Msk (0x01UL << C_CANn_IF2_CMDMSK_W_DATA_A_Pos) /*!< C_CANn IF2_CMDMSK_W: DATA_A Mask */ +#define C_CANn_IF2_CMDMSK_W_TXRQST_Pos 2 /*!< C_CANn IF2_CMDMSK_W: TXRQST Position */ +#define C_CANn_IF2_CMDMSK_W_TXRQST_Msk (0x01UL << C_CANn_IF2_CMDMSK_W_TXRQST_Pos) /*!< C_CANn IF2_CMDMSK_W: TXRQST Mask */ +#define C_CANn_IF2_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CANn IF2_CMDMSK_W: CLRINTPND Position */ +#define C_CANn_IF2_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CANn_IF2_CMDMSK_W_CLRINTPND_Pos) /*!< C_CANn IF2_CMDMSK_W: CLRINTPND Mask */ +#define C_CANn_IF2_CMDMSK_W_CTRL_Pos 4 /*!< C_CANn IF2_CMDMSK_W: CTRL Position */ +#define C_CANn_IF2_CMDMSK_W_CTRL_Msk (0x01UL << C_CANn_IF2_CMDMSK_W_CTRL_Pos) /*!< C_CANn IF2_CMDMSK_W: CTRL Mask */ +#define C_CANn_IF2_CMDMSK_W_ARB_Pos 5 /*!< C_CANn IF2_CMDMSK_W: ARB Position */ +#define C_CANn_IF2_CMDMSK_W_ARB_Msk (0x01UL << C_CANn_IF2_CMDMSK_W_ARB_Pos) /*!< C_CANn IF2_CMDMSK_W: ARB Mask */ +#define C_CANn_IF2_CMDMSK_W_MASK_Pos 6 /*!< C_CANn IF2_CMDMSK_W: MASK Position */ +#define C_CANn_IF2_CMDMSK_W_MASK_Msk (0x01UL << C_CANn_IF2_CMDMSK_W_MASK_Pos) /*!< C_CANn IF2_CMDMSK_W: MASK Mask */ +#define C_CANn_IF2_CMDMSK_W_WR_RD_Pos 7 /*!< C_CANn IF2_CMDMSK_W: WR_RD Position */ +#define C_CANn_IF2_CMDMSK_W_WR_RD_Msk (0x01UL << C_CANn_IF2_CMDMSK_W_WR_RD_Pos) /*!< C_CANn IF2_CMDMSK_W: WR_RD Mask */ + +/* ----------------------------- C_CANn_IF2_CMDMSK_R ---------------------------- */ +#define C_CANn_IF2_CMDMSK_R_DATA_B_Pos 0 /*!< C_CANn IF2_CMDMSK_R: DATA_B Position */ +#define C_CANn_IF2_CMDMSK_R_DATA_B_Msk (0x01UL << C_CANn_IF2_CMDMSK_R_DATA_B_Pos) /*!< C_CANn IF2_CMDMSK_R: DATA_B Mask */ +#define C_CANn_IF2_CMDMSK_R_DATA_A_Pos 1 /*!< C_CANn IF2_CMDMSK_R: DATA_A Position */ +#define C_CANn_IF2_CMDMSK_R_DATA_A_Msk (0x01UL << C_CANn_IF2_CMDMSK_R_DATA_A_Pos) /*!< C_CANn IF2_CMDMSK_R: DATA_A Mask */ +#define C_CANn_IF2_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CANn IF2_CMDMSK_R: NEWDAT Position */ +#define C_CANn_IF2_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CANn_IF2_CMDMSK_R_NEWDAT_Pos) /*!< C_CANn IF2_CMDMSK_R: NEWDAT Mask */ +#define C_CANn_IF2_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CANn IF2_CMDMSK_R: CLRINTPND Position */ +#define C_CANn_IF2_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CANn_IF2_CMDMSK_R_CLRINTPND_Pos) /*!< C_CANn IF2_CMDMSK_R: CLRINTPND Mask */ +#define C_CANn_IF2_CMDMSK_R_CTRL_Pos 4 /*!< C_CANn IF2_CMDMSK_R: CTRL Position */ +#define C_CANn_IF2_CMDMSK_R_CTRL_Msk (0x01UL << C_CANn_IF2_CMDMSK_R_CTRL_Pos) /*!< C_CANn IF2_CMDMSK_R: CTRL Mask */ +#define C_CANn_IF2_CMDMSK_R_ARB_Pos 5 /*!< C_CANn IF2_CMDMSK_R: ARB Position */ +#define C_CANn_IF2_CMDMSK_R_ARB_Msk (0x01UL << C_CANn_IF2_CMDMSK_R_ARB_Pos) /*!< C_CANn IF2_CMDMSK_R: ARB Mask */ +#define C_CANn_IF2_CMDMSK_R_MASK_Pos 6 /*!< C_CANn IF2_CMDMSK_R: MASK Position */ +#define C_CANn_IF2_CMDMSK_R_MASK_Msk (0x01UL << C_CANn_IF2_CMDMSK_R_MASK_Pos) /*!< C_CANn IF2_CMDMSK_R: MASK Mask */ +#define C_CANn_IF2_CMDMSK_R_WR_RD_Pos 7 /*!< C_CANn IF2_CMDMSK_R: WR_RD Position */ +#define C_CANn_IF2_CMDMSK_R_WR_RD_Msk (0x01UL << C_CANn_IF2_CMDMSK_R_WR_RD_Pos) /*!< C_CANn IF2_CMDMSK_R: WR_RD Mask */ + +/* ------------------------------- C_CANn_IF2_MSK1 ------------------------------ */ +#define C_CANn_IF2_MSK1_MSK15_0_Pos 0 /*!< C_CANn IF2_MSK1: MSK15_0 Position */ +#define C_CANn_IF2_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CANn_IF2_MSK1_MSK15_0_Pos) /*!< C_CANn IF2_MSK1: MSK15_0 Mask */ + +/* ------------------------------- C_CANn_IF2_MSK2 ------------------------------ */ +#define C_CANn_IF2_MSK2_MSK28_16_Pos 0 /*!< C_CANn IF2_MSK2: MSK28_16 Position */ +#define C_CANn_IF2_MSK2_MSK28_16_Msk (0x00001fffUL << C_CANn_IF2_MSK2_MSK28_16_Pos) /*!< C_CANn IF2_MSK2: MSK28_16 Mask */ +#define C_CANn_IF2_MSK2_MDIR_Pos 14 /*!< C_CANn IF2_MSK2: MDIR Position */ +#define C_CANn_IF2_MSK2_MDIR_Msk (0x01UL << C_CANn_IF2_MSK2_MDIR_Pos) /*!< C_CANn IF2_MSK2: MDIR Mask */ +#define C_CANn_IF2_MSK2_MXTD_Pos 15 /*!< C_CANn IF2_MSK2: MXTD Position */ +#define C_CANn_IF2_MSK2_MXTD_Msk (0x01UL << C_CANn_IF2_MSK2_MXTD_Pos) /*!< C_CANn IF2_MSK2: MXTD Mask */ + +/* ------------------------------- C_CANn_IF2_ARB1 ------------------------------ */ +#define C_CANn_IF2_ARB1_ID15_0_Pos 0 /*!< C_CANn IF2_ARB1: ID15_0 Position */ +#define C_CANn_IF2_ARB1_ID15_0_Msk (0x0000ffffUL << C_CANn_IF2_ARB1_ID15_0_Pos) /*!< C_CANn IF2_ARB1: ID15_0 Mask */ + +/* ------------------------------- C_CANn_IF2_ARB2 ------------------------------ */ +#define C_CANn_IF2_ARB2_ID28_16_Pos 0 /*!< C_CANn IF2_ARB2: ID28_16 Position */ +#define C_CANn_IF2_ARB2_ID28_16_Msk (0x00001fffUL << C_CANn_IF2_ARB2_ID28_16_Pos) /*!< C_CANn IF2_ARB2: ID28_16 Mask */ +#define C_CANn_IF2_ARB2_DIR_Pos 13 /*!< C_CANn IF2_ARB2: DIR Position */ +#define C_CANn_IF2_ARB2_DIR_Msk (0x01UL << C_CANn_IF2_ARB2_DIR_Pos) /*!< C_CANn IF2_ARB2: DIR Mask */ +#define C_CANn_IF2_ARB2_XTD_Pos 14 /*!< C_CANn IF2_ARB2: XTD Position */ +#define C_CANn_IF2_ARB2_XTD_Msk (0x01UL << C_CANn_IF2_ARB2_XTD_Pos) /*!< C_CANn IF2_ARB2: XTD Mask */ +#define C_CANn_IF2_ARB2_MSGVAL_Pos 15 /*!< C_CANn IF2_ARB2: MSGVAL Position */ +#define C_CANn_IF2_ARB2_MSGVAL_Msk (0x01UL << C_CANn_IF2_ARB2_MSGVAL_Pos) /*!< C_CANn IF2_ARB2: MSGVAL Mask */ + +/* ------------------------------ C_CANn_IF2_MCTRL ------------------------------ */ +#define C_CANn_IF2_MCTRL_DLC3_0_Pos 0 /*!< C_CANn IF2_MCTRL: DLC3_0 Position */ +#define C_CANn_IF2_MCTRL_DLC3_0_Msk (0x0fUL << C_CANn_IF2_MCTRL_DLC3_0_Pos) /*!< C_CANn IF2_MCTRL: DLC3_0 Mask */ +#define C_CANn_IF2_MCTRL_EOB_Pos 7 /*!< C_CANn IF2_MCTRL: EOB Position */ +#define C_CANn_IF2_MCTRL_EOB_Msk (0x01UL << C_CANn_IF2_MCTRL_EOB_Pos) /*!< C_CANn IF2_MCTRL: EOB Mask */ +#define C_CANn_IF2_MCTRL_TXRQST_Pos 8 /*!< C_CANn IF2_MCTRL: TXRQST Position */ +#define C_CANn_IF2_MCTRL_TXRQST_Msk (0x01UL << C_CANn_IF2_MCTRL_TXRQST_Pos) /*!< C_CANn IF2_MCTRL: TXRQST Mask */ +#define C_CANn_IF2_MCTRL_RMTEN_Pos 9 /*!< C_CANn IF2_MCTRL: RMTEN Position */ +#define C_CANn_IF2_MCTRL_RMTEN_Msk (0x01UL << C_CANn_IF2_MCTRL_RMTEN_Pos) /*!< C_CANn IF2_MCTRL: RMTEN Mask */ +#define C_CANn_IF2_MCTRL_RXIE_Pos 10 /*!< C_CANn IF2_MCTRL: RXIE Position */ +#define C_CANn_IF2_MCTRL_RXIE_Msk (0x01UL << C_CANn_IF2_MCTRL_RXIE_Pos) /*!< C_CANn IF2_MCTRL: RXIE Mask */ +#define C_CANn_IF2_MCTRL_TXIE_Pos 11 /*!< C_CANn IF2_MCTRL: TXIE Position */ +#define C_CANn_IF2_MCTRL_TXIE_Msk (0x01UL << C_CANn_IF2_MCTRL_TXIE_Pos) /*!< C_CANn IF2_MCTRL: TXIE Mask */ +#define C_CANn_IF2_MCTRL_UMASK_Pos 12 /*!< C_CANn IF2_MCTRL: UMASK Position */ +#define C_CANn_IF2_MCTRL_UMASK_Msk (0x01UL << C_CANn_IF2_MCTRL_UMASK_Pos) /*!< C_CANn IF2_MCTRL: UMASK Mask */ +#define C_CANn_IF2_MCTRL_INTPND_Pos 13 /*!< C_CANn IF2_MCTRL: INTPND Position */ +#define C_CANn_IF2_MCTRL_INTPND_Msk (0x01UL << C_CANn_IF2_MCTRL_INTPND_Pos) /*!< C_CANn IF2_MCTRL: INTPND Mask */ +#define C_CANn_IF2_MCTRL_MSGLST_Pos 14 /*!< C_CANn IF2_MCTRL: MSGLST Position */ +#define C_CANn_IF2_MCTRL_MSGLST_Msk (0x01UL << C_CANn_IF2_MCTRL_MSGLST_Pos) /*!< C_CANn IF2_MCTRL: MSGLST Mask */ +#define C_CANn_IF2_MCTRL_NEWDAT_Pos 15 /*!< C_CANn IF2_MCTRL: NEWDAT Position */ +#define C_CANn_IF2_MCTRL_NEWDAT_Msk (0x01UL << C_CANn_IF2_MCTRL_NEWDAT_Pos) /*!< C_CANn IF2_MCTRL: NEWDAT Mask */ + +/* ------------------------------- C_CANn_IF2_DA1 ------------------------------- */ +#define C_CANn_IF2_DA1_DATA0_Pos 0 /*!< C_CANn IF2_DA1: DATA0 Position */ +#define C_CANn_IF2_DA1_DATA0_Msk (0x000000ffUL << C_CANn_IF2_DA1_DATA0_Pos) /*!< C_CANn IF2_DA1: DATA0 Mask */ +#define C_CANn_IF2_DA1_DATA1_Pos 8 /*!< C_CANn IF2_DA1: DATA1 Position */ +#define C_CANn_IF2_DA1_DATA1_Msk (0x000000ffUL << C_CANn_IF2_DA1_DATA1_Pos) /*!< C_CANn IF2_DA1: DATA1 Mask */ + +/* ------------------------------- C_CANn_IF2_DA2 ------------------------------- */ +#define C_CANn_IF2_DA2_DATA2_Pos 0 /*!< C_CANn IF2_DA2: DATA2 Position */ +#define C_CANn_IF2_DA2_DATA2_Msk (0x000000ffUL << C_CANn_IF2_DA2_DATA2_Pos) /*!< C_CANn IF2_DA2: DATA2 Mask */ +#define C_CANn_IF2_DA2_DATA3_Pos 8 /*!< C_CANn IF2_DA2: DATA3 Position */ +#define C_CANn_IF2_DA2_DATA3_Msk (0x000000ffUL << C_CANn_IF2_DA2_DATA3_Pos) /*!< C_CANn IF2_DA2: DATA3 Mask */ + +/* ------------------------------- C_CANn_IF2_DB1 ------------------------------- */ +#define C_CANn_IF2_DB1_DATA4_Pos 0 /*!< C_CANn IF2_DB1: DATA4 Position */ +#define C_CANn_IF2_DB1_DATA4_Msk (0x000000ffUL << C_CANn_IF2_DB1_DATA4_Pos) /*!< C_CANn IF2_DB1: DATA4 Mask */ +#define C_CANn_IF2_DB1_DATA5_Pos 8 /*!< C_CANn IF2_DB1: DATA5 Position */ +#define C_CANn_IF2_DB1_DATA5_Msk (0x000000ffUL << C_CANn_IF2_DB1_DATA5_Pos) /*!< C_CANn IF2_DB1: DATA5 Mask */ + +/* ------------------------------- C_CANn_IF2_DB2 ------------------------------- */ +#define C_CANn_IF2_DB2_DATA6_Pos 0 /*!< C_CANn IF2_DB2: DATA6 Position */ +#define C_CANn_IF2_DB2_DATA6_Msk (0x000000ffUL << C_CANn_IF2_DB2_DATA6_Pos) /*!< C_CANn IF2_DB2: DATA6 Mask */ +#define C_CANn_IF2_DB2_DATA7_Pos 8 /*!< C_CANn IF2_DB2: DATA7 Position */ +#define C_CANn_IF2_DB2_DATA7_Msk (0x000000ffUL << C_CANn_IF2_DB2_DATA7_Pos) /*!< C_CANn IF2_DB2: DATA7 Mask */ + +/* -------------------------------- C_CANn_TXREQ1 ------------------------------- */ +#define C_CANn_TXREQ1_TXRQST16_1_Pos 0 /*!< C_CANn TXREQ1: TXRQST16_1 Position */ +#define C_CANn_TXREQ1_TXRQST16_1_Msk (0x0000ffffUL << C_CANn_TXREQ1_TXRQST16_1_Pos) /*!< C_CANn TXREQ1: TXRQST16_1 Mask */ + +/* -------------------------------- C_CANn_TXREQ2 ------------------------------- */ +#define C_CANn_TXREQ2_TXRQST32_17_Pos 0 /*!< C_CANn TXREQ2: TXRQST32_17 Position */ +#define C_CANn_TXREQ2_TXRQST32_17_Msk (0x0000ffffUL << C_CANn_TXREQ2_TXRQST32_17_Pos) /*!< C_CANn TXREQ2: TXRQST32_17 Mask */ + +/* --------------------------------- C_CANn_ND1 --------------------------------- */ +#define C_CANn_ND1_NEWDAT16_1_Pos 0 /*!< C_CANn ND1: NEWDAT16_1 Position */ +#define C_CANn_ND1_NEWDAT16_1_Msk (0x0000ffffUL << C_CANn_ND1_NEWDAT16_1_Pos) /*!< C_CANn ND1: NEWDAT16_1 Mask */ + +/* --------------------------------- C_CANn_ND2 --------------------------------- */ +#define C_CANn_ND2_NEWDAT32_17_Pos 0 /*!< C_CANn ND2: NEWDAT32_17 Position */ +#define C_CANn_ND2_NEWDAT32_17_Msk (0x0000ffffUL << C_CANn_ND2_NEWDAT32_17_Pos) /*!< C_CANn ND2: NEWDAT32_17 Mask */ + +/* --------------------------------- C_CANn_IR1 --------------------------------- */ +#define C_CANn_IR1_INTPND16_1_Pos 0 /*!< C_CANn IR1: INTPND16_1 Position */ +#define C_CANn_IR1_INTPND16_1_Msk (0x0000ffffUL << C_CANn_IR1_INTPND16_1_Pos) /*!< C_CANn IR1: INTPND16_1 Mask */ + +/* --------------------------------- C_CANn_IR2 --------------------------------- */ +#define C_CANn_IR2_INTPND32_17_Pos 0 /*!< C_CANn IR2: INTPND32_17 Position */ +#define C_CANn_IR2_INTPND32_17_Msk (0x0000ffffUL << C_CANn_IR2_INTPND32_17_Pos) /*!< C_CANn IR2: INTPND32_17 Mask */ + +/* -------------------------------- C_CANn_MSGV1 -------------------------------- */ +#define C_CANn_MSGV1_MSGVAL16_1_Pos 0 /*!< C_CANn MSGV1: MSGVAL16_1 Position */ +#define C_CANn_MSGV1_MSGVAL16_1_Msk (0x0000ffffUL << C_CANn_MSGV1_MSGVAL16_1_Pos) /*!< C_CANn MSGV1: MSGVAL16_1 Mask */ + +/* -------------------------------- C_CANn_MSGV2 -------------------------------- */ +#define C_CANn_MSGV2_MSGVAL32_17_Pos 0 /*!< C_CANn MSGV2: MSGVAL32_17 Position */ +#define C_CANn_MSGV2_MSGVAL32_17_Msk (0x0000ffffUL << C_CANn_MSGV2_MSGVAL32_17_Pos) /*!< C_CANn MSGV2: MSGVAL32_17 Mask */ + +/* -------------------------------- C_CANn_CLKDIV ------------------------------- */ +#define C_CANn_CLKDIV_CLKDIVVAL_Pos 0 /*!< C_CANn CLKDIV: CLKDIVVAL Position */ +#define C_CANn_CLKDIV_CLKDIVVAL_Msk (0x0fUL << C_CANn_CLKDIV_CLKDIVVAL_Pos) /*!< C_CANn CLKDIV: CLKDIVVAL Mask */ + + +/* ================================================================================ */ +/* ================ struct 'C_CAN1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- C_CAN1_CNTL -------------------------------- */ +#define C_CAN1_CNTL_INIT_Pos 0 /*!< C_CAN1 CNTL: INIT Position */ +#define C_CAN1_CNTL_INIT_Msk (0x01UL << C_CAN1_CNTL_INIT_Pos) /*!< C_CAN1 CNTL: INIT Mask */ +#define C_CAN1_CNTL_IE_Pos 1 /*!< C_CAN1 CNTL: IE Position */ +#define C_CAN1_CNTL_IE_Msk (0x01UL << C_CAN1_CNTL_IE_Pos) /*!< C_CAN1 CNTL: IE Mask */ +#define C_CAN1_CNTL_SIE_Pos 2 /*!< C_CAN1 CNTL: SIE Position */ +#define C_CAN1_CNTL_SIE_Msk (0x01UL << C_CAN1_CNTL_SIE_Pos) /*!< C_CAN1 CNTL: SIE Mask */ +#define C_CAN1_CNTL_EIE_Pos 3 /*!< C_CAN1 CNTL: EIE Position */ +#define C_CAN1_CNTL_EIE_Msk (0x01UL << C_CAN1_CNTL_EIE_Pos) /*!< C_CAN1 CNTL: EIE Mask */ +#define C_CAN1_CNTL_DAR_Pos 5 /*!< C_CAN1 CNTL: DAR Position */ +#define C_CAN1_CNTL_DAR_Msk (0x01UL << C_CAN1_CNTL_DAR_Pos) /*!< C_CAN1 CNTL: DAR Mask */ +#define C_CAN1_CNTL_CCE_Pos 6 /*!< C_CAN1 CNTL: CCE Position */ +#define C_CAN1_CNTL_CCE_Msk (0x01UL << C_CAN1_CNTL_CCE_Pos) /*!< C_CAN1 CNTL: CCE Mask */ +#define C_CAN1_CNTL_TEST_Pos 7 /*!< C_CAN1 CNTL: TEST Position */ +#define C_CAN1_CNTL_TEST_Msk (0x01UL << C_CAN1_CNTL_TEST_Pos) /*!< C_CAN1 CNTL: TEST Mask */ + +/* --------------------------------- C_CAN1_STAT -------------------------------- */ +#define C_CAN1_STAT_LEC_Pos 0 /*!< C_CAN1 STAT: LEC Position */ +#define C_CAN1_STAT_LEC_Msk (0x07UL << C_CAN1_STAT_LEC_Pos) /*!< C_CAN1 STAT: LEC Mask */ +#define C_CAN1_STAT_TXOK_Pos 3 /*!< C_CAN1 STAT: TXOK Position */ +#define C_CAN1_STAT_TXOK_Msk (0x01UL << C_CAN1_STAT_TXOK_Pos) /*!< C_CAN1 STAT: TXOK Mask */ +#define C_CAN1_STAT_RXOK_Pos 4 /*!< C_CAN1 STAT: RXOK Position */ +#define C_CAN1_STAT_RXOK_Msk (0x01UL << C_CAN1_STAT_RXOK_Pos) /*!< C_CAN1 STAT: RXOK Mask */ +#define C_CAN1_STAT_EPASS_Pos 5 /*!< C_CAN1 STAT: EPASS Position */ +#define C_CAN1_STAT_EPASS_Msk (0x01UL << C_CAN1_STAT_EPASS_Pos) /*!< C_CAN1 STAT: EPASS Mask */ +#define C_CAN1_STAT_EWARN_Pos 6 /*!< C_CAN1 STAT: EWARN Position */ +#define C_CAN1_STAT_EWARN_Msk (0x01UL << C_CAN1_STAT_EWARN_Pos) /*!< C_CAN1 STAT: EWARN Mask */ +#define C_CAN1_STAT_BOFF_Pos 7 /*!< C_CAN1 STAT: BOFF Position */ +#define C_CAN1_STAT_BOFF_Msk (0x01UL << C_CAN1_STAT_BOFF_Pos) /*!< C_CAN1 STAT: BOFF Mask */ + +/* ---------------------------------- C_CAN1_EC --------------------------------- */ +#define C_CAN1_EC_TEC_7_0_Pos 0 /*!< C_CAN1 EC: TEC_7_0 Position */ +#define C_CAN1_EC_TEC_7_0_Msk (0x000000ffUL << C_CAN1_EC_TEC_7_0_Pos) /*!< C_CAN1 EC: TEC_7_0 Mask */ +#define C_CAN1_EC_REC_6_0_Pos 8 /*!< C_CAN1 EC: REC_6_0 Position */ +#define C_CAN1_EC_REC_6_0_Msk (0x7fUL << C_CAN1_EC_REC_6_0_Pos) /*!< C_CAN1 EC: REC_6_0 Mask */ +#define C_CAN1_EC_RP_Pos 15 /*!< C_CAN1 EC: RP Position */ +#define C_CAN1_EC_RP_Msk (0x01UL << C_CAN1_EC_RP_Pos) /*!< C_CAN1 EC: RP Mask */ + +/* ---------------------------------- C_CAN1_BT --------------------------------- */ +#define C_CAN1_BT_BRP_Pos 0 /*!< C_CAN1 BT: BRP Position */ +#define C_CAN1_BT_BRP_Msk (0x3fUL << C_CAN1_BT_BRP_Pos) /*!< C_CAN1 BT: BRP Mask */ +#define C_CAN1_BT_SJW_Pos 6 /*!< C_CAN1 BT: SJW Position */ +#define C_CAN1_BT_SJW_Msk (0x03UL << C_CAN1_BT_SJW_Pos) /*!< C_CAN1 BT: SJW Mask */ +#define C_CAN1_BT_TSEG1_Pos 8 /*!< C_CAN1 BT: TSEG1 Position */ +#define C_CAN1_BT_TSEG1_Msk (0x0fUL << C_CAN1_BT_TSEG1_Pos) /*!< C_CAN1 BT: TSEG1 Mask */ +#define C_CAN1_BT_TSEG2_Pos 12 /*!< C_CAN1 BT: TSEG2 Position */ +#define C_CAN1_BT_TSEG2_Msk (0x07UL << C_CAN1_BT_TSEG2_Pos) /*!< C_CAN1 BT: TSEG2 Mask */ + +/* --------------------------------- C_CAN1_INT --------------------------------- */ +#define C_CAN1_INT_INTID15_0_Pos 0 /*!< C_CAN1 INT: INTID15_0 Position */ +#define C_CAN1_INT_INTID15_0_Msk (0x0000ffffUL << C_CAN1_INT_INTID15_0_Pos) /*!< C_CAN1 INT: INTID15_0 Mask */ + +/* --------------------------------- C_CAN1_TEST -------------------------------- */ +#define C_CAN1_TEST_BASIC_Pos 2 /*!< C_CAN1 TEST: BASIC Position */ +#define C_CAN1_TEST_BASIC_Msk (0x01UL << C_CAN1_TEST_BASIC_Pos) /*!< C_CAN1 TEST: BASIC Mask */ +#define C_CAN1_TEST_SILENT_Pos 3 /*!< C_CAN1 TEST: SILENT Position */ +#define C_CAN1_TEST_SILENT_Msk (0x01UL << C_CAN1_TEST_SILENT_Pos) /*!< C_CAN1 TEST: SILENT Mask */ +#define C_CAN1_TEST_LBACK_Pos 4 /*!< C_CAN1 TEST: LBACK Position */ +#define C_CAN1_TEST_LBACK_Msk (0x01UL << C_CAN1_TEST_LBACK_Pos) /*!< C_CAN1 TEST: LBACK Mask */ +#define C_CAN1_TEST_TX1_0_Pos 5 /*!< C_CAN1 TEST: TX1_0 Position */ +#define C_CAN1_TEST_TX1_0_Msk (0x03UL << C_CAN1_TEST_TX1_0_Pos) /*!< C_CAN1 TEST: TX1_0 Mask */ +#define C_CAN1_TEST_RX_Pos 7 /*!< C_CAN1 TEST: RX Position */ +#define C_CAN1_TEST_RX_Msk (0x01UL << C_CAN1_TEST_RX_Pos) /*!< C_CAN1 TEST: RX Mask */ + +/* --------------------------------- C_CAN1_BRPE -------------------------------- */ +#define C_CAN1_BRPE_BRPE_Pos 0 /*!< C_CAN1 BRPE: BRPE Position */ +#define C_CAN1_BRPE_BRPE_Msk (0x0fUL << C_CAN1_BRPE_BRPE_Pos) /*!< C_CAN1 BRPE: BRPE Mask */ + +/* ------------------------------ C_CAN1_IF1_CMDREQ ----------------------------- */ +#define C_CAN1_IF1_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN1 IF1_CMDREQ: MESSNUM Position */ +#define C_CAN1_IF1_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN1_IF1_CMDREQ_MESSNUM_Pos) /*!< C_CAN1 IF1_CMDREQ: MESSNUM Mask */ +#define C_CAN1_IF1_CMDREQ_BUSY_Pos 15 /*!< C_CAN1 IF1_CMDREQ: BUSY Position */ +#define C_CAN1_IF1_CMDREQ_BUSY_Msk (0x01UL << C_CAN1_IF1_CMDREQ_BUSY_Pos) /*!< C_CAN1 IF1_CMDREQ: BUSY Mask */ + +/* ----------------------------- C_CAN1_IF1_CMDMSK_W ---------------------------- */ +#define C_CAN1_IF1_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN1 IF1_CMDMSK_W: DATA_B Position */ +#define C_CAN1_IF1_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_B_Pos) /*!< C_CAN1 IF1_CMDMSK_W: DATA_B Mask */ +#define C_CAN1_IF1_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN1 IF1_CMDMSK_W: DATA_A Position */ +#define C_CAN1_IF1_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_A_Pos) /*!< C_CAN1 IF1_CMDMSK_W: DATA_A Mask */ +#define C_CAN1_IF1_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN1 IF1_CMDMSK_W: TXRQST Position */ +#define C_CAN1_IF1_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_TXRQST_Pos) /*!< C_CAN1 IF1_CMDMSK_W: TXRQST Mask */ +#define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN1 IF1_CMDMSK_W: CLRINTPND Position */ +#define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN1 IF1_CMDMSK_W: CLRINTPND Mask */ +#define C_CAN1_IF1_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN1 IF1_CMDMSK_W: CTRL Position */ +#define C_CAN1_IF1_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_CTRL_Pos) /*!< C_CAN1 IF1_CMDMSK_W: CTRL Mask */ +#define C_CAN1_IF1_CMDMSK_W_ARB_Pos 5 /*!< C_CAN1 IF1_CMDMSK_W: ARB Position */ +#define C_CAN1_IF1_CMDMSK_W_ARB_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_ARB_Pos) /*!< C_CAN1 IF1_CMDMSK_W: ARB Mask */ +#define C_CAN1_IF1_CMDMSK_W_MASK_Pos 6 /*!< C_CAN1 IF1_CMDMSK_W: MASK Position */ +#define C_CAN1_IF1_CMDMSK_W_MASK_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_MASK_Pos) /*!< C_CAN1 IF1_CMDMSK_W: MASK Mask */ +#define C_CAN1_IF1_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN1 IF1_CMDMSK_W: WR_RD Position */ +#define C_CAN1_IF1_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_WR_RD_Pos) /*!< C_CAN1 IF1_CMDMSK_W: WR_RD Mask */ + +/* ----------------------------- C_CAN1_IF1_CMDMSK_R ---------------------------- */ +#define C_CAN1_IF1_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN1 IF1_CMDMSK_R: DATA_B Position */ +#define C_CAN1_IF1_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_B_Pos) /*!< C_CAN1 IF1_CMDMSK_R: DATA_B Mask */ +#define C_CAN1_IF1_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN1 IF1_CMDMSK_R: DATA_A Position */ +#define C_CAN1_IF1_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_A_Pos) /*!< C_CAN1 IF1_CMDMSK_R: DATA_A Mask */ +#define C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN1 IF1_CMDMSK_R: NEWDAT Position */ +#define C_CAN1_IF1_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN1 IF1_CMDMSK_R: NEWDAT Mask */ +#define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN1 IF1_CMDMSK_R: CLRINTPND Position */ +#define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN1 IF1_CMDMSK_R: CLRINTPND Mask */ +#define C_CAN1_IF1_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN1 IF1_CMDMSK_R: CTRL Position */ +#define C_CAN1_IF1_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_CTRL_Pos) /*!< C_CAN1 IF1_CMDMSK_R: CTRL Mask */ +#define C_CAN1_IF1_CMDMSK_R_ARB_Pos 5 /*!< C_CAN1 IF1_CMDMSK_R: ARB Position */ +#define C_CAN1_IF1_CMDMSK_R_ARB_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_ARB_Pos) /*!< C_CAN1 IF1_CMDMSK_R: ARB Mask */ +#define C_CAN1_IF1_CMDMSK_R_MASK_Pos 6 /*!< C_CAN1 IF1_CMDMSK_R: MASK Position */ +#define C_CAN1_IF1_CMDMSK_R_MASK_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_MASK_Pos) /*!< C_CAN1 IF1_CMDMSK_R: MASK Mask */ +#define C_CAN1_IF1_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN1 IF1_CMDMSK_R: WR_RD Position */ +#define C_CAN1_IF1_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_WR_RD_Pos) /*!< C_CAN1 IF1_CMDMSK_R: WR_RD Mask */ + +/* ------------------------------- C_CAN1_IF1_MSK1 ------------------------------ */ +#define C_CAN1_IF1_MSK1_MSK15_0_Pos 0 /*!< C_CAN1 IF1_MSK1: MSK15_0 Position */ +#define C_CAN1_IF1_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN1_IF1_MSK1_MSK15_0_Pos) /*!< C_CAN1 IF1_MSK1: MSK15_0 Mask */ + +/* ------------------------------- C_CAN1_IF1_MSK2 ------------------------------ */ +#define C_CAN1_IF1_MSK2_MSK28_16_Pos 0 /*!< C_CAN1 IF1_MSK2: MSK28_16 Position */ +#define C_CAN1_IF1_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN1_IF1_MSK2_MSK28_16_Pos) /*!< C_CAN1 IF1_MSK2: MSK28_16 Mask */ +#define C_CAN1_IF1_MSK2_MDIR_Pos 14 /*!< C_CAN1 IF1_MSK2: MDIR Position */ +#define C_CAN1_IF1_MSK2_MDIR_Msk (0x01UL << C_CAN1_IF1_MSK2_MDIR_Pos) /*!< C_CAN1 IF1_MSK2: MDIR Mask */ +#define C_CAN1_IF1_MSK2_MXTD_Pos 15 /*!< C_CAN1 IF1_MSK2: MXTD Position */ +#define C_CAN1_IF1_MSK2_MXTD_Msk (0x01UL << C_CAN1_IF1_MSK2_MXTD_Pos) /*!< C_CAN1 IF1_MSK2: MXTD Mask */ + +/* ------------------------------- C_CAN1_IF1_ARB1 ------------------------------ */ +#define C_CAN1_IF1_ARB1_ID15_0_Pos 0 /*!< C_CAN1 IF1_ARB1: ID15_0 Position */ +#define C_CAN1_IF1_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN1_IF1_ARB1_ID15_0_Pos) /*!< C_CAN1 IF1_ARB1: ID15_0 Mask */ + +/* ------------------------------- C_CAN1_IF1_ARB2 ------------------------------ */ +#define C_CAN1_IF1_ARB2_ID28_16_Pos 0 /*!< C_CAN1 IF1_ARB2: ID28_16 Position */ +#define C_CAN1_IF1_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN1_IF1_ARB2_ID28_16_Pos) /*!< C_CAN1 IF1_ARB2: ID28_16 Mask */ +#define C_CAN1_IF1_ARB2_DIR_Pos 13 /*!< C_CAN1 IF1_ARB2: DIR Position */ +#define C_CAN1_IF1_ARB2_DIR_Msk (0x01UL << C_CAN1_IF1_ARB2_DIR_Pos) /*!< C_CAN1 IF1_ARB2: DIR Mask */ +#define C_CAN1_IF1_ARB2_XTD_Pos 14 /*!< C_CAN1 IF1_ARB2: XTD Position */ +#define C_CAN1_IF1_ARB2_XTD_Msk (0x01UL << C_CAN1_IF1_ARB2_XTD_Pos) /*!< C_CAN1 IF1_ARB2: XTD Mask */ +#define C_CAN1_IF1_ARB2_MSGVAL_Pos 15 /*!< C_CAN1 IF1_ARB2: MSGVAL Position */ +#define C_CAN1_IF1_ARB2_MSGVAL_Msk (0x01UL << C_CAN1_IF1_ARB2_MSGVAL_Pos) /*!< C_CAN1 IF1_ARB2: MSGVAL Mask */ + +/* ------------------------------ C_CAN1_IF1_MCTRL ------------------------------ */ +#define C_CAN1_IF1_MCTRL_DLC3_0_Pos 0 /*!< C_CAN1 IF1_MCTRL: DLC3_0 Position */ +#define C_CAN1_IF1_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN1_IF1_MCTRL_DLC3_0_Pos) /*!< C_CAN1 IF1_MCTRL: DLC3_0 Mask */ +#define C_CAN1_IF1_MCTRL_EOB_Pos 7 /*!< C_CAN1 IF1_MCTRL: EOB Position */ +#define C_CAN1_IF1_MCTRL_EOB_Msk (0x01UL << C_CAN1_IF1_MCTRL_EOB_Pos) /*!< C_CAN1 IF1_MCTRL: EOB Mask */ +#define C_CAN1_IF1_MCTRL_TXRQST_Pos 8 /*!< C_CAN1 IF1_MCTRL: TXRQST Position */ +#define C_CAN1_IF1_MCTRL_TXRQST_Msk (0x01UL << C_CAN1_IF1_MCTRL_TXRQST_Pos) /*!< C_CAN1 IF1_MCTRL: TXRQST Mask */ +#define C_CAN1_IF1_MCTRL_RMTEN_Pos 9 /*!< C_CAN1 IF1_MCTRL: RMTEN Position */ +#define C_CAN1_IF1_MCTRL_RMTEN_Msk (0x01UL << C_CAN1_IF1_MCTRL_RMTEN_Pos) /*!< C_CAN1 IF1_MCTRL: RMTEN Mask */ +#define C_CAN1_IF1_MCTRL_RXIE_Pos 10 /*!< C_CAN1 IF1_MCTRL: RXIE Position */ +#define C_CAN1_IF1_MCTRL_RXIE_Msk (0x01UL << C_CAN1_IF1_MCTRL_RXIE_Pos) /*!< C_CAN1 IF1_MCTRL: RXIE Mask */ +#define C_CAN1_IF1_MCTRL_TXIE_Pos 11 /*!< C_CAN1 IF1_MCTRL: TXIE Position */ +#define C_CAN1_IF1_MCTRL_TXIE_Msk (0x01UL << C_CAN1_IF1_MCTRL_TXIE_Pos) /*!< C_CAN1 IF1_MCTRL: TXIE Mask */ +#define C_CAN1_IF1_MCTRL_UMASK_Pos 12 /*!< C_CAN1 IF1_MCTRL: UMASK Position */ +#define C_CAN1_IF1_MCTRL_UMASK_Msk (0x01UL << C_CAN1_IF1_MCTRL_UMASK_Pos) /*!< C_CAN1 IF1_MCTRL: UMASK Mask */ +#define C_CAN1_IF1_MCTRL_INTPND_Pos 13 /*!< C_CAN1 IF1_MCTRL: INTPND Position */ +#define C_CAN1_IF1_MCTRL_INTPND_Msk (0x01UL << C_CAN1_IF1_MCTRL_INTPND_Pos) /*!< C_CAN1 IF1_MCTRL: INTPND Mask */ +#define C_CAN1_IF1_MCTRL_MSGLST_Pos 14 /*!< C_CAN1 IF1_MCTRL: MSGLST Position */ +#define C_CAN1_IF1_MCTRL_MSGLST_Msk (0x01UL << C_CAN1_IF1_MCTRL_MSGLST_Pos) /*!< C_CAN1 IF1_MCTRL: MSGLST Mask */ +#define C_CAN1_IF1_MCTRL_NEWDAT_Pos 15 /*!< C_CAN1 IF1_MCTRL: NEWDAT Position */ +#define C_CAN1_IF1_MCTRL_NEWDAT_Msk (0x01UL << C_CAN1_IF1_MCTRL_NEWDAT_Pos) /*!< C_CAN1 IF1_MCTRL: NEWDAT Mask */ + +/* ------------------------------- C_CAN1_IF1_DA1 ------------------------------- */ +#define C_CAN1_IF1_DA1_DATA0_Pos 0 /*!< C_CAN1 IF1_DA1: DATA0 Position */ +#define C_CAN1_IF1_DA1_DATA0_Msk (0x000000ffUL << C_CAN1_IF1_DA1_DATA0_Pos) /*!< C_CAN1 IF1_DA1: DATA0 Mask */ +#define C_CAN1_IF1_DA1_DATA1_Pos 8 /*!< C_CAN1 IF1_DA1: DATA1 Position */ +#define C_CAN1_IF1_DA1_DATA1_Msk (0x000000ffUL << C_CAN1_IF1_DA1_DATA1_Pos) /*!< C_CAN1 IF1_DA1: DATA1 Mask */ + +/* ------------------------------- C_CAN1_IF1_DA2 ------------------------------- */ +#define C_CAN1_IF1_DA2_DATA2_Pos 0 /*!< C_CAN1 IF1_DA2: DATA2 Position */ +#define C_CAN1_IF1_DA2_DATA2_Msk (0x000000ffUL << C_CAN1_IF1_DA2_DATA2_Pos) /*!< C_CAN1 IF1_DA2: DATA2 Mask */ +#define C_CAN1_IF1_DA2_DATA3_Pos 8 /*!< C_CAN1 IF1_DA2: DATA3 Position */ +#define C_CAN1_IF1_DA2_DATA3_Msk (0x000000ffUL << C_CAN1_IF1_DA2_DATA3_Pos) /*!< C_CAN1 IF1_DA2: DATA3 Mask */ + +/* ------------------------------- C_CAN1_IF1_DB1 ------------------------------- */ +#define C_CAN1_IF1_DB1_DATA4_Pos 0 /*!< C_CAN1 IF1_DB1: DATA4 Position */ +#define C_CAN1_IF1_DB1_DATA4_Msk (0x000000ffUL << C_CAN1_IF1_DB1_DATA4_Pos) /*!< C_CAN1 IF1_DB1: DATA4 Mask */ +#define C_CAN1_IF1_DB1_DATA5_Pos 8 /*!< C_CAN1 IF1_DB1: DATA5 Position */ +#define C_CAN1_IF1_DB1_DATA5_Msk (0x000000ffUL << C_CAN1_IF1_DB1_DATA5_Pos) /*!< C_CAN1 IF1_DB1: DATA5 Mask */ + +/* ------------------------------- C_CAN1_IF1_DB2 ------------------------------- */ +#define C_CAN1_IF1_DB2_DATA6_Pos 0 /*!< C_CAN1 IF1_DB2: DATA6 Position */ +#define C_CAN1_IF1_DB2_DATA6_Msk (0x000000ffUL << C_CAN1_IF1_DB2_DATA6_Pos) /*!< C_CAN1 IF1_DB2: DATA6 Mask */ +#define C_CAN1_IF1_DB2_DATA7_Pos 8 /*!< C_CAN1 IF1_DB2: DATA7 Position */ +#define C_CAN1_IF1_DB2_DATA7_Msk (0x000000ffUL << C_CAN1_IF1_DB2_DATA7_Pos) /*!< C_CAN1 IF1_DB2: DATA7 Mask */ + +/* ------------------------------ C_CAN1_IF2_CMDREQ ----------------------------- */ +#define C_CAN1_IF2_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN1 IF2_CMDREQ: MESSNUM Position */ +#define C_CAN1_IF2_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN1_IF2_CMDREQ_MESSNUM_Pos) /*!< C_CAN1 IF2_CMDREQ: MESSNUM Mask */ +#define C_CAN1_IF2_CMDREQ_BUSY_Pos 15 /*!< C_CAN1 IF2_CMDREQ: BUSY Position */ +#define C_CAN1_IF2_CMDREQ_BUSY_Msk (0x01UL << C_CAN1_IF2_CMDREQ_BUSY_Pos) /*!< C_CAN1 IF2_CMDREQ: BUSY Mask */ + +/* ----------------------------- C_CAN1_IF2_CMDMSK_W ---------------------------- */ +#define C_CAN1_IF2_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN1 IF2_CMDMSK_W: DATA_B Position */ +#define C_CAN1_IF2_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_B_Pos) /*!< C_CAN1 IF2_CMDMSK_W: DATA_B Mask */ +#define C_CAN1_IF2_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN1 IF2_CMDMSK_W: DATA_A Position */ +#define C_CAN1_IF2_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_A_Pos) /*!< C_CAN1 IF2_CMDMSK_W: DATA_A Mask */ +#define C_CAN1_IF2_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN1 IF2_CMDMSK_W: TXRQST Position */ +#define C_CAN1_IF2_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_TXRQST_Pos) /*!< C_CAN1 IF2_CMDMSK_W: TXRQST Mask */ +#define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN1 IF2_CMDMSK_W: CLRINTPND Position */ +#define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN1 IF2_CMDMSK_W: CLRINTPND Mask */ +#define C_CAN1_IF2_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN1 IF2_CMDMSK_W: CTRL Position */ +#define C_CAN1_IF2_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_CTRL_Pos) /*!< C_CAN1 IF2_CMDMSK_W: CTRL Mask */ +#define C_CAN1_IF2_CMDMSK_W_ARB_Pos 5 /*!< C_CAN1 IF2_CMDMSK_W: ARB Position */ +#define C_CAN1_IF2_CMDMSK_W_ARB_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_ARB_Pos) /*!< C_CAN1 IF2_CMDMSK_W: ARB Mask */ +#define C_CAN1_IF2_CMDMSK_W_MASK_Pos 6 /*!< C_CAN1 IF2_CMDMSK_W: MASK Position */ +#define C_CAN1_IF2_CMDMSK_W_MASK_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_MASK_Pos) /*!< C_CAN1 IF2_CMDMSK_W: MASK Mask */ +#define C_CAN1_IF2_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN1 IF2_CMDMSK_W: WR_RD Position */ +#define C_CAN1_IF2_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_WR_RD_Pos) /*!< C_CAN1 IF2_CMDMSK_W: WR_RD Mask */ + +/* ----------------------------- C_CAN1_IF2_CMDMSK_R ---------------------------- */ +#define C_CAN1_IF2_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN1 IF2_CMDMSK_R: DATA_B Position */ +#define C_CAN1_IF2_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_B_Pos) /*!< C_CAN1 IF2_CMDMSK_R: DATA_B Mask */ +#define C_CAN1_IF2_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN1 IF2_CMDMSK_R: DATA_A Position */ +#define C_CAN1_IF2_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_A_Pos) /*!< C_CAN1 IF2_CMDMSK_R: DATA_A Mask */ +#define C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN1 IF2_CMDMSK_R: NEWDAT Position */ +#define C_CAN1_IF2_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN1 IF2_CMDMSK_R: NEWDAT Mask */ +#define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN1 IF2_CMDMSK_R: CLRINTPND Position */ +#define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN1 IF2_CMDMSK_R: CLRINTPND Mask */ +#define C_CAN1_IF2_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN1 IF2_CMDMSK_R: CTRL Position */ +#define C_CAN1_IF2_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_CTRL_Pos) /*!< C_CAN1 IF2_CMDMSK_R: CTRL Mask */ +#define C_CAN1_IF2_CMDMSK_R_ARB_Pos 5 /*!< C_CAN1 IF2_CMDMSK_R: ARB Position */ +#define C_CAN1_IF2_CMDMSK_R_ARB_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_ARB_Pos) /*!< C_CAN1 IF2_CMDMSK_R: ARB Mask */ +#define C_CAN1_IF2_CMDMSK_R_MASK_Pos 6 /*!< C_CAN1 IF2_CMDMSK_R: MASK Position */ +#define C_CAN1_IF2_CMDMSK_R_MASK_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_MASK_Pos) /*!< C_CAN1 IF2_CMDMSK_R: MASK Mask */ +#define C_CAN1_IF2_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN1 IF2_CMDMSK_R: WR_RD Position */ +#define C_CAN1_IF2_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_WR_RD_Pos) /*!< C_CAN1 IF2_CMDMSK_R: WR_RD Mask */ + +/* ------------------------------- C_CAN1_IF2_MSK1 ------------------------------ */ +#define C_CAN1_IF2_MSK1_MSK15_0_Pos 0 /*!< C_CAN1 IF2_MSK1: MSK15_0 Position */ +#define C_CAN1_IF2_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN1_IF2_MSK1_MSK15_0_Pos) /*!< C_CAN1 IF2_MSK1: MSK15_0 Mask */ + +/* ------------------------------- C_CAN1_IF2_MSK2 ------------------------------ */ +#define C_CAN1_IF2_MSK2_MSK28_16_Pos 0 /*!< C_CAN1 IF2_MSK2: MSK28_16 Position */ +#define C_CAN1_IF2_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN1_IF2_MSK2_MSK28_16_Pos) /*!< C_CAN1 IF2_MSK2: MSK28_16 Mask */ +#define C_CAN1_IF2_MSK2_MDIR_Pos 14 /*!< C_CAN1 IF2_MSK2: MDIR Position */ +#define C_CAN1_IF2_MSK2_MDIR_Msk (0x01UL << C_CAN1_IF2_MSK2_MDIR_Pos) /*!< C_CAN1 IF2_MSK2: MDIR Mask */ +#define C_CAN1_IF2_MSK2_MXTD_Pos 15 /*!< C_CAN1 IF2_MSK2: MXTD Position */ +#define C_CAN1_IF2_MSK2_MXTD_Msk (0x01UL << C_CAN1_IF2_MSK2_MXTD_Pos) /*!< C_CAN1 IF2_MSK2: MXTD Mask */ + +/* ------------------------------- C_CAN1_IF2_ARB1 ------------------------------ */ +#define C_CAN1_IF2_ARB1_ID15_0_Pos 0 /*!< C_CAN1 IF2_ARB1: ID15_0 Position */ +#define C_CAN1_IF2_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN1_IF2_ARB1_ID15_0_Pos) /*!< C_CAN1 IF2_ARB1: ID15_0 Mask */ + +/* ------------------------------- C_CAN1_IF2_ARB2 ------------------------------ */ +#define C_CAN1_IF2_ARB2_ID28_16_Pos 0 /*!< C_CAN1 IF2_ARB2: ID28_16 Position */ +#define C_CAN1_IF2_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN1_IF2_ARB2_ID28_16_Pos) /*!< C_CAN1 IF2_ARB2: ID28_16 Mask */ +#define C_CAN1_IF2_ARB2_DIR_Pos 13 /*!< C_CAN1 IF2_ARB2: DIR Position */ +#define C_CAN1_IF2_ARB2_DIR_Msk (0x01UL << C_CAN1_IF2_ARB2_DIR_Pos) /*!< C_CAN1 IF2_ARB2: DIR Mask */ +#define C_CAN1_IF2_ARB2_XTD_Pos 14 /*!< C_CAN1 IF2_ARB2: XTD Position */ +#define C_CAN1_IF2_ARB2_XTD_Msk (0x01UL << C_CAN1_IF2_ARB2_XTD_Pos) /*!< C_CAN1 IF2_ARB2: XTD Mask */ +#define C_CAN1_IF2_ARB2_MSGVAL_Pos 15 /*!< C_CAN1 IF2_ARB2: MSGVAL Position */ +#define C_CAN1_IF2_ARB2_MSGVAL_Msk (0x01UL << C_CAN1_IF2_ARB2_MSGVAL_Pos) /*!< C_CAN1 IF2_ARB2: MSGVAL Mask */ + +/* ------------------------------ C_CAN1_IF2_MCTRL ------------------------------ */ +#define C_CAN1_IF2_MCTRL_DLC3_0_Pos 0 /*!< C_CAN1 IF2_MCTRL: DLC3_0 Position */ +#define C_CAN1_IF2_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN1_IF2_MCTRL_DLC3_0_Pos) /*!< C_CAN1 IF2_MCTRL: DLC3_0 Mask */ +#define C_CAN1_IF2_MCTRL_EOB_Pos 7 /*!< C_CAN1 IF2_MCTRL: EOB Position */ +#define C_CAN1_IF2_MCTRL_EOB_Msk (0x01UL << C_CAN1_IF2_MCTRL_EOB_Pos) /*!< C_CAN1 IF2_MCTRL: EOB Mask */ +#define C_CAN1_IF2_MCTRL_TXRQST_Pos 8 /*!< C_CAN1 IF2_MCTRL: TXRQST Position */ +#define C_CAN1_IF2_MCTRL_TXRQST_Msk (0x01UL << C_CAN1_IF2_MCTRL_TXRQST_Pos) /*!< C_CAN1 IF2_MCTRL: TXRQST Mask */ +#define C_CAN1_IF2_MCTRL_RMTEN_Pos 9 /*!< C_CAN1 IF2_MCTRL: RMTEN Position */ +#define C_CAN1_IF2_MCTRL_RMTEN_Msk (0x01UL << C_CAN1_IF2_MCTRL_RMTEN_Pos) /*!< C_CAN1 IF2_MCTRL: RMTEN Mask */ +#define C_CAN1_IF2_MCTRL_RXIE_Pos 10 /*!< C_CAN1 IF2_MCTRL: RXIE Position */ +#define C_CAN1_IF2_MCTRL_RXIE_Msk (0x01UL << C_CAN1_IF2_MCTRL_RXIE_Pos) /*!< C_CAN1 IF2_MCTRL: RXIE Mask */ +#define C_CAN1_IF2_MCTRL_TXIE_Pos 11 /*!< C_CAN1 IF2_MCTRL: TXIE Position */ +#define C_CAN1_IF2_MCTRL_TXIE_Msk (0x01UL << C_CAN1_IF2_MCTRL_TXIE_Pos) /*!< C_CAN1 IF2_MCTRL: TXIE Mask */ +#define C_CAN1_IF2_MCTRL_UMASK_Pos 12 /*!< C_CAN1 IF2_MCTRL: UMASK Position */ +#define C_CAN1_IF2_MCTRL_UMASK_Msk (0x01UL << C_CAN1_IF2_MCTRL_UMASK_Pos) /*!< C_CAN1 IF2_MCTRL: UMASK Mask */ +#define C_CAN1_IF2_MCTRL_INTPND_Pos 13 /*!< C_CAN1 IF2_MCTRL: INTPND Position */ +#define C_CAN1_IF2_MCTRL_INTPND_Msk (0x01UL << C_CAN1_IF2_MCTRL_INTPND_Pos) /*!< C_CAN1 IF2_MCTRL: INTPND Mask */ +#define C_CAN1_IF2_MCTRL_MSGLST_Pos 14 /*!< C_CAN1 IF2_MCTRL: MSGLST Position */ +#define C_CAN1_IF2_MCTRL_MSGLST_Msk (0x01UL << C_CAN1_IF2_MCTRL_MSGLST_Pos) /*!< C_CAN1 IF2_MCTRL: MSGLST Mask */ +#define C_CAN1_IF2_MCTRL_NEWDAT_Pos 15 /*!< C_CAN1 IF2_MCTRL: NEWDAT Position */ +#define C_CAN1_IF2_MCTRL_NEWDAT_Msk (0x01UL << C_CAN1_IF2_MCTRL_NEWDAT_Pos) /*!< C_CAN1 IF2_MCTRL: NEWDAT Mask */ + +/* ------------------------------- C_CAN1_IF2_DA1 ------------------------------- */ +#define C_CAN1_IF2_DA1_DATA0_Pos 0 /*!< C_CAN1 IF2_DA1: DATA0 Position */ +#define C_CAN1_IF2_DA1_DATA0_Msk (0x000000ffUL << C_CAN1_IF2_DA1_DATA0_Pos) /*!< C_CAN1 IF2_DA1: DATA0 Mask */ +#define C_CAN1_IF2_DA1_DATA1_Pos 8 /*!< C_CAN1 IF2_DA1: DATA1 Position */ +#define C_CAN1_IF2_DA1_DATA1_Msk (0x000000ffUL << C_CAN1_IF2_DA1_DATA1_Pos) /*!< C_CAN1 IF2_DA1: DATA1 Mask */ + +/* ------------------------------- C_CAN1_IF2_DA2 ------------------------------- */ +#define C_CAN1_IF2_DA2_DATA2_Pos 0 /*!< C_CAN1 IF2_DA2: DATA2 Position */ +#define C_CAN1_IF2_DA2_DATA2_Msk (0x000000ffUL << C_CAN1_IF2_DA2_DATA2_Pos) /*!< C_CAN1 IF2_DA2: DATA2 Mask */ +#define C_CAN1_IF2_DA2_DATA3_Pos 8 /*!< C_CAN1 IF2_DA2: DATA3 Position */ +#define C_CAN1_IF2_DA2_DATA3_Msk (0x000000ffUL << C_CAN1_IF2_DA2_DATA3_Pos) /*!< C_CAN1 IF2_DA2: DATA3 Mask */ + +/* ------------------------------- C_CAN1_IF2_DB1 ------------------------------- */ +#define C_CAN1_IF2_DB1_DATA4_Pos 0 /*!< C_CAN1 IF2_DB1: DATA4 Position */ +#define C_CAN1_IF2_DB1_DATA4_Msk (0x000000ffUL << C_CAN1_IF2_DB1_DATA4_Pos) /*!< C_CAN1 IF2_DB1: DATA4 Mask */ +#define C_CAN1_IF2_DB1_DATA5_Pos 8 /*!< C_CAN1 IF2_DB1: DATA5 Position */ +#define C_CAN1_IF2_DB1_DATA5_Msk (0x000000ffUL << C_CAN1_IF2_DB1_DATA5_Pos) /*!< C_CAN1 IF2_DB1: DATA5 Mask */ + +/* ------------------------------- C_CAN1_IF2_DB2 ------------------------------- */ +#define C_CAN1_IF2_DB2_DATA6_Pos 0 /*!< C_CAN1 IF2_DB2: DATA6 Position */ +#define C_CAN1_IF2_DB2_DATA6_Msk (0x000000ffUL << C_CAN1_IF2_DB2_DATA6_Pos) /*!< C_CAN1 IF2_DB2: DATA6 Mask */ +#define C_CAN1_IF2_DB2_DATA7_Pos 8 /*!< C_CAN1 IF2_DB2: DATA7 Position */ +#define C_CAN1_IF2_DB2_DATA7_Msk (0x000000ffUL << C_CAN1_IF2_DB2_DATA7_Pos) /*!< C_CAN1 IF2_DB2: DATA7 Mask */ + +/* -------------------------------- C_CAN1_TXREQ1 ------------------------------- */ +#define C_CAN1_TXREQ1_TXRQST16_1_Pos 0 /*!< C_CAN1 TXREQ1: TXRQST16_1 Position */ +#define C_CAN1_TXREQ1_TXRQST16_1_Msk (0x0000ffffUL << C_CAN1_TXREQ1_TXRQST16_1_Pos) /*!< C_CAN1 TXREQ1: TXRQST16_1 Mask */ + +/* -------------------------------- C_CAN1_TXREQ2 ------------------------------- */ +#define C_CAN1_TXREQ2_TXRQST32_17_Pos 0 /*!< C_CAN1 TXREQ2: TXRQST32_17 Position */ +#define C_CAN1_TXREQ2_TXRQST32_17_Msk (0x0000ffffUL << C_CAN1_TXREQ2_TXRQST32_17_Pos) /*!< C_CAN1 TXREQ2: TXRQST32_17 Mask */ + +/* --------------------------------- C_CAN1_ND1 --------------------------------- */ +#define C_CAN1_ND1_NEWDAT16_1_Pos 0 /*!< C_CAN1 ND1: NEWDAT16_1 Position */ +#define C_CAN1_ND1_NEWDAT16_1_Msk (0x0000ffffUL << C_CAN1_ND1_NEWDAT16_1_Pos) /*!< C_CAN1 ND1: NEWDAT16_1 Mask */ + +/* --------------------------------- C_CAN1_ND2 --------------------------------- */ +#define C_CAN1_ND2_NEWDAT32_17_Pos 0 /*!< C_CAN1 ND2: NEWDAT32_17 Position */ +#define C_CAN1_ND2_NEWDAT32_17_Msk (0x0000ffffUL << C_CAN1_ND2_NEWDAT32_17_Pos) /*!< C_CAN1 ND2: NEWDAT32_17 Mask */ + +/* --------------------------------- C_CAN1_IR1 --------------------------------- */ +#define C_CAN1_IR1_INTPND16_1_Pos 0 /*!< C_CAN1 IR1: INTPND16_1 Position */ +#define C_CAN1_IR1_INTPND16_1_Msk (0x0000ffffUL << C_CAN1_IR1_INTPND16_1_Pos) /*!< C_CAN1 IR1: INTPND16_1 Mask */ + +/* --------------------------------- C_CAN1_IR2 --------------------------------- */ +#define C_CAN1_IR2_INTPND32_17_Pos 0 /*!< C_CAN1 IR2: INTPND32_17 Position */ +#define C_CAN1_IR2_INTPND32_17_Msk (0x0000ffffUL << C_CAN1_IR2_INTPND32_17_Pos) /*!< C_CAN1 IR2: INTPND32_17 Mask */ + +/* -------------------------------- C_CAN1_MSGV1 -------------------------------- */ +#define C_CAN1_MSGV1_MSGVAL16_1_Pos 0 /*!< C_CAN1 MSGV1: MSGVAL16_1 Position */ +#define C_CAN1_MSGV1_MSGVAL16_1_Msk (0x0000ffffUL << C_CAN1_MSGV1_MSGVAL16_1_Pos) /*!< C_CAN1 MSGV1: MSGVAL16_1 Mask */ + +/* -------------------------------- C_CAN1_MSGV2 -------------------------------- */ +#define C_CAN1_MSGV2_MSGVAL32_17_Pos 0 /*!< C_CAN1 MSGV2: MSGVAL32_17 Position */ +#define C_CAN1_MSGV2_MSGVAL32_17_Msk (0x0000ffffUL << C_CAN1_MSGV2_MSGVAL32_17_Pos) /*!< C_CAN1 MSGV2: MSGVAL32_17 Mask */ + +/* -------------------------------- C_CAN1_CLKDIV ------------------------------- */ +#define C_CAN1_CLKDIV_CLKDIVVAL_Pos 0 /*!< C_CAN1 CLKDIV: CLKDIVVAL Position */ +#define C_CAN1_CLKDIV_CLKDIVVAL_Msk (0x0fUL << C_CAN1_CLKDIV_CLKDIVVAL_Pos) /*!< C_CAN1 CLKDIV: CLKDIVVAL Mask */ + + +/* ================================================================================ */ +/* ================ struct 'RITIMER' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- RITIMER_COMPVAL ------------------------------ */ +#define RITIMER_COMPVAL_RICOMP_Pos 0 /*!< RITIMER COMPVAL: RICOMP Position */ +#define RITIMER_COMPVAL_RICOMP_Msk (0xffffffffUL << RITIMER_COMPVAL_RICOMP_Pos) /*!< RITIMER COMPVAL: RICOMP Mask */ + +/* -------------------------------- RITIMER_MASK -------------------------------- */ +#define RITIMER_MASK_RIMASK_Pos 0 /*!< RITIMER MASK: RIMASK Position */ +#define RITIMER_MASK_RIMASK_Msk (0xffffffffUL << RITIMER_MASK_RIMASK_Pos) /*!< RITIMER MASK: RIMASK Mask */ + +/* -------------------------------- RITIMER_CTRL -------------------------------- */ +#define RITIMER_CTRL_RITINT_Pos 0 /*!< RITIMER CTRL: RITINT Position */ +#define RITIMER_CTRL_RITINT_Msk (0x01UL << RITIMER_CTRL_RITINT_Pos) /*!< RITIMER CTRL: RITINT Mask */ +#define RITIMER_CTRL_RITENCLR_Pos 1 /*!< RITIMER CTRL: RITENCLR Position */ +#define RITIMER_CTRL_RITENCLR_Msk (0x01UL << RITIMER_CTRL_RITENCLR_Pos) /*!< RITIMER CTRL: RITENCLR Mask */ +#define RITIMER_CTRL_RITENBR_Pos 2 /*!< RITIMER CTRL: RITENBR Position */ +#define RITIMER_CTRL_RITENBR_Msk (0x01UL << RITIMER_CTRL_RITENBR_Pos) /*!< RITIMER CTRL: RITENBR Mask */ +#define RITIMER_CTRL_RITEN_Pos 3 /*!< RITIMER CTRL: RITEN Position */ +#define RITIMER_CTRL_RITEN_Msk (0x01UL << RITIMER_CTRL_RITEN_Pos) /*!< RITIMER CTRL: RITEN Mask */ + +/* ------------------------------- RITIMER_COUNTER ------------------------------ */ +#define RITIMER_COUNTER_RICOUNTER_Pos 0 /*!< RITIMER COUNTER: RICOUNTER Position */ +#define RITIMER_COUNTER_RICOUNTER_Msk (0xffffffffUL << RITIMER_COUNTER_RICOUNTER_Pos) /*!< RITIMER COUNTER: RICOUNTER Mask */ + + +/* ================================================================================ */ +/* ================ struct 'QEI' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------------- QEI_CON ---------------------------------- */ +#define QEI_CON_RESP_Pos 0 /*!< QEI CON: RESP Position */ +#define QEI_CON_RESP_Msk (0x01UL << QEI_CON_RESP_Pos) /*!< QEI CON: RESP Mask */ +#define QEI_CON_RESPI_Pos 1 /*!< QEI CON: RESPI Position */ +#define QEI_CON_RESPI_Msk (0x01UL << QEI_CON_RESPI_Pos) /*!< QEI CON: RESPI Mask */ +#define QEI_CON_RESV_Pos 2 /*!< QEI CON: RESV Position */ +#define QEI_CON_RESV_Msk (0x01UL << QEI_CON_RESV_Pos) /*!< QEI CON: RESV Mask */ +#define QEI_CON_RESI_Pos 3 /*!< QEI CON: RESI Position */ +#define QEI_CON_RESI_Msk (0x01UL << QEI_CON_RESI_Pos) /*!< QEI CON: RESI Mask */ + +/* ---------------------------------- QEI_STAT ---------------------------------- */ +#define QEI_STAT_DIR_Pos 0 /*!< QEI STAT: DIR Position */ +#define QEI_STAT_DIR_Msk (0x01UL << QEI_STAT_DIR_Pos) /*!< QEI STAT: DIR Mask */ + +/* ---------------------------------- QEI_CONF ---------------------------------- */ +#define QEI_CONF_DIRINV_Pos 0 /*!< QEI CONF: DIRINV Position */ +#define QEI_CONF_DIRINV_Msk (0x01UL << QEI_CONF_DIRINV_Pos) /*!< QEI CONF: DIRINV Mask */ +#define QEI_CONF_SIGMODE_Pos 1 /*!< QEI CONF: SIGMODE Position */ +#define QEI_CONF_SIGMODE_Msk (0x01UL << QEI_CONF_SIGMODE_Pos) /*!< QEI CONF: SIGMODE Mask */ +#define QEI_CONF_CAPMODE_Pos 2 /*!< QEI CONF: CAPMODE Position */ +#define QEI_CONF_CAPMODE_Msk (0x01UL << QEI_CONF_CAPMODE_Pos) /*!< QEI CONF: CAPMODE Mask */ +#define QEI_CONF_INVINX_Pos 3 /*!< QEI CONF: INVINX Position */ +#define QEI_CONF_INVINX_Msk (0x01UL << QEI_CONF_INVINX_Pos) /*!< QEI CONF: INVINX Mask */ +#define QEI_CONF_CRESPI_Pos 4 /*!< QEI CONF: CRESPI Position */ +#define QEI_CONF_CRESPI_Msk (0x01UL << QEI_CONF_CRESPI_Pos) /*!< QEI CONF: CRESPI Mask */ +#define QEI_CONF_INXGATE_Pos 16 /*!< QEI CONF: INXGATE Position */ +#define QEI_CONF_INXGATE_Msk (0x0fUL << QEI_CONF_INXGATE_Pos) /*!< QEI CONF: INXGATE Mask */ + +/* ----------------------------------- QEI_POS ---------------------------------- */ +#define QEI_POS_POS_Pos 0 /*!< QEI POS: POS Position */ +#define QEI_POS_POS_Msk (0xffffffffUL << QEI_POS_POS_Pos) /*!< QEI POS: POS Mask */ + +/* --------------------------------- QEI_MAXPOS --------------------------------- */ +#define QEI_MAXPOS_MAXPOS_Pos 0 /*!< QEI MAXPOS: MAXPOS Position */ +#define QEI_MAXPOS_MAXPOS_Msk (0xffffffffUL << QEI_MAXPOS_MAXPOS_Pos) /*!< QEI MAXPOS: MAXPOS Mask */ + +/* --------------------------------- QEI_CMPOS0 --------------------------------- */ +#define QEI_CMPOS0_PCMP0_Pos 0 /*!< QEI CMPOS0: PCMP0 Position */ +#define QEI_CMPOS0_PCMP0_Msk (0xffffffffUL << QEI_CMPOS0_PCMP0_Pos) /*!< QEI CMPOS0: PCMP0 Mask */ + +/* --------------------------------- QEI_CMPOS1 --------------------------------- */ +#define QEI_CMPOS1_PCMP1_Pos 0 /*!< QEI CMPOS1: PCMP1 Position */ +#define QEI_CMPOS1_PCMP1_Msk (0xffffffffUL << QEI_CMPOS1_PCMP1_Pos) /*!< QEI CMPOS1: PCMP1 Mask */ + +/* --------------------------------- QEI_CMPOS2 --------------------------------- */ +#define QEI_CMPOS2_PCMP2_Pos 0 /*!< QEI CMPOS2: PCMP2 Position */ +#define QEI_CMPOS2_PCMP2_Msk (0xffffffffUL << QEI_CMPOS2_PCMP2_Pos) /*!< QEI CMPOS2: PCMP2 Mask */ + +/* --------------------------------- QEI_INXCNT --------------------------------- */ +#define QEI_INXCNT_ENCPOS_Pos 0 /*!< QEI INXCNT: ENCPOS Position */ +#define QEI_INXCNT_ENCPOS_Msk (0xffffffffUL << QEI_INXCNT_ENCPOS_Pos) /*!< QEI INXCNT: ENCPOS Mask */ + +/* --------------------------------- QEI_INXCMP0 -------------------------------- */ +#define QEI_INXCMP0_ICMP0_Pos 0 /*!< QEI INXCMP0: ICMP0 Position */ +#define QEI_INXCMP0_ICMP0_Msk (0xffffffffUL << QEI_INXCMP0_ICMP0_Pos) /*!< QEI INXCMP0: ICMP0 Mask */ + +/* ---------------------------------- QEI_LOAD ---------------------------------- */ +#define QEI_LOAD_VELLOAD_Pos 0 /*!< QEI LOAD: VELLOAD Position */ +#define QEI_LOAD_VELLOAD_Msk (0xffffffffUL << QEI_LOAD_VELLOAD_Pos) /*!< QEI LOAD: VELLOAD Mask */ + +/* ---------------------------------- QEI_TIME ---------------------------------- */ +#define QEI_TIME_VELVAL_Pos 0 /*!< QEI TIME: VELVAL Position */ +#define QEI_TIME_VELVAL_Msk (0xffffffffUL << QEI_TIME_VELVAL_Pos) /*!< QEI TIME: VELVAL Mask */ + +/* ----------------------------------- QEI_VEL ---------------------------------- */ +#define QEI_VEL_VELPC_Pos 0 /*!< QEI VEL: VELPC Position */ +#define QEI_VEL_VELPC_Msk (0xffffffffUL << QEI_VEL_VELPC_Pos) /*!< QEI VEL: VELPC Mask */ + +/* ----------------------------------- QEI_CAP ---------------------------------- */ +#define QEI_CAP_VELCAP_Pos 0 /*!< QEI CAP: VELCAP Position */ +#define QEI_CAP_VELCAP_Msk (0xffffffffUL << QEI_CAP_VELCAP_Pos) /*!< QEI CAP: VELCAP Mask */ + +/* --------------------------------- QEI_VELCOMP -------------------------------- */ +#define QEI_VELCOMP_VELCMP_Pos 0 /*!< QEI VELCOMP: VELCMP Position */ +#define QEI_VELCOMP_VELCMP_Msk (0xffffffffUL << QEI_VELCOMP_VELCMP_Pos) /*!< QEI VELCOMP: VELCMP Mask */ + +/* -------------------------------- QEI_FILTERPHA ------------------------------- */ +#define QEI_FILTERPHA_FILTA_Pos 0 /*!< QEI FILTERPHA: FILTA Position */ +#define QEI_FILTERPHA_FILTA_Msk (0xffffffffUL << QEI_FILTERPHA_FILTA_Pos) /*!< QEI FILTERPHA: FILTA Mask */ + +/* -------------------------------- QEI_FILTERPHB ------------------------------- */ +#define QEI_FILTERPHB_FILTB_Pos 0 /*!< QEI FILTERPHB: FILTB Position */ +#define QEI_FILTERPHB_FILTB_Msk (0xffffffffUL << QEI_FILTERPHB_FILTB_Pos) /*!< QEI FILTERPHB: FILTB Mask */ + +/* -------------------------------- QEI_FILTERINX ------------------------------- */ +#define QEI_FILTERINX_FITLINX_Pos 0 /*!< QEI FILTERINX: FITLINX Position */ +#define QEI_FILTERINX_FITLINX_Msk (0xffffffffUL << QEI_FILTERINX_FITLINX_Pos) /*!< QEI FILTERINX: FITLINX Mask */ + +/* --------------------------------- QEI_WINDOW --------------------------------- */ +#define QEI_WINDOW_WINDOW_Pos 0 /*!< QEI WINDOW: WINDOW Position */ +#define QEI_WINDOW_WINDOW_Msk (0xffffffffUL << QEI_WINDOW_WINDOW_Pos) /*!< QEI WINDOW: WINDOW Mask */ + +/* --------------------------------- QEI_INXCMP1 -------------------------------- */ +#define QEI_INXCMP1_ICMP1_Pos 0 /*!< QEI INXCMP1: ICMP1 Position */ +#define QEI_INXCMP1_ICMP1_Msk (0xffffffffUL << QEI_INXCMP1_ICMP1_Pos) /*!< QEI INXCMP1: ICMP1 Mask */ + +/* --------------------------------- QEI_INXCMP2 -------------------------------- */ +#define QEI_INXCMP2_ICMP2_Pos 0 /*!< QEI INXCMP2: ICMP2 Position */ +#define QEI_INXCMP2_ICMP2_Msk (0xffffffffUL << QEI_INXCMP2_ICMP2_Pos) /*!< QEI INXCMP2: ICMP2 Mask */ + +/* ----------------------------------- QEI_IEC ---------------------------------- */ +#define QEI_IEC_INX_EN_Pos 0 /*!< QEI IEC: INX_EN Position */ +#define QEI_IEC_INX_EN_Msk (0x01UL << QEI_IEC_INX_EN_Pos) /*!< QEI IEC: INX_EN Mask */ +#define QEI_IEC_TIM_EN_Pos 1 /*!< QEI IEC: TIM_EN Position */ +#define QEI_IEC_TIM_EN_Msk (0x01UL << QEI_IEC_TIM_EN_Pos) /*!< QEI IEC: TIM_EN Mask */ +#define QEI_IEC_VELC_EN_Pos 2 /*!< QEI IEC: VELC_EN Position */ +#define QEI_IEC_VELC_EN_Msk (0x01UL << QEI_IEC_VELC_EN_Pos) /*!< QEI IEC: VELC_EN Mask */ +#define QEI_IEC_DIR_EN_Pos 3 /*!< QEI IEC: DIR_EN Position */ +#define QEI_IEC_DIR_EN_Msk (0x01UL << QEI_IEC_DIR_EN_Pos) /*!< QEI IEC: DIR_EN Mask */ +#define QEI_IEC_ERR_EN_Pos 4 /*!< QEI IEC: ERR_EN Position */ +#define QEI_IEC_ERR_EN_Msk (0x01UL << QEI_IEC_ERR_EN_Pos) /*!< QEI IEC: ERR_EN Mask */ +#define QEI_IEC_ENCLK_EN_Pos 5 /*!< QEI IEC: ENCLK_EN Position */ +#define QEI_IEC_ENCLK_EN_Msk (0x01UL << QEI_IEC_ENCLK_EN_Pos) /*!< QEI IEC: ENCLK_EN Mask */ +#define QEI_IEC_POS0_Int_Pos 6 /*!< QEI IEC: POS0_Int Position */ +#define QEI_IEC_POS0_Int_Msk (0x01UL << QEI_IEC_POS0_Int_Pos) /*!< QEI IEC: POS0_Int Mask */ +#define QEI_IEC_POS1_Int_Pos 7 /*!< QEI IEC: POS1_Int Position */ +#define QEI_IEC_POS1_Int_Msk (0x01UL << QEI_IEC_POS1_Int_Pos) /*!< QEI IEC: POS1_Int Mask */ +#define QEI_IEC_POS2_Int_Pos 8 /*!< QEI IEC: POS2_Int Position */ +#define QEI_IEC_POS2_Int_Msk (0x01UL << QEI_IEC_POS2_Int_Pos) /*!< QEI IEC: POS2_Int Mask */ +#define QEI_IEC_REV_Int_Pos 9 /*!< QEI IEC: REV_Int Position */ +#define QEI_IEC_REV_Int_Msk (0x01UL << QEI_IEC_REV_Int_Pos) /*!< QEI IEC: REV_Int Mask */ +#define QEI_IEC_POS0REV_Int_Pos 10 /*!< QEI IEC: POS0REV_Int Position */ +#define QEI_IEC_POS0REV_Int_Msk (0x01UL << QEI_IEC_POS0REV_Int_Pos) /*!< QEI IEC: POS0REV_Int Mask */ +#define QEI_IEC_POS1REV_Int_Pos 11 /*!< QEI IEC: POS1REV_Int Position */ +#define QEI_IEC_POS1REV_Int_Msk (0x01UL << QEI_IEC_POS1REV_Int_Pos) /*!< QEI IEC: POS1REV_Int Mask */ +#define QEI_IEC_POS2REV_Int_Pos 12 /*!< QEI IEC: POS2REV_Int Position */ +#define QEI_IEC_POS2REV_Int_Msk (0x01UL << QEI_IEC_POS2REV_Int_Pos) /*!< QEI IEC: POS2REV_Int Mask */ +#define QEI_IEC_REV1_Int_Pos 13 /*!< QEI IEC: REV1_Int Position */ +#define QEI_IEC_REV1_Int_Msk (0x01UL << QEI_IEC_REV1_Int_Pos) /*!< QEI IEC: REV1_Int Mask */ +#define QEI_IEC_REV2_Int_Pos 14 /*!< QEI IEC: REV2_Int Position */ +#define QEI_IEC_REV2_Int_Msk (0x01UL << QEI_IEC_REV2_Int_Pos) /*!< QEI IEC: REV2_Int Mask */ +#define QEI_IEC_MAXPOS_Int_Pos 15 /*!< QEI IEC: MAXPOS_Int Position */ +#define QEI_IEC_MAXPOS_Int_Msk (0x01UL << QEI_IEC_MAXPOS_Int_Pos) /*!< QEI IEC: MAXPOS_Int Mask */ + +/* ----------------------------------- QEI_IES ---------------------------------- */ +#define QEI_IES_INX_EN_Pos 0 /*!< QEI IES: INX_EN Position */ +#define QEI_IES_INX_EN_Msk (0x01UL << QEI_IES_INX_EN_Pos) /*!< QEI IES: INX_EN Mask */ +#define QEI_IES_TIM_EN_Pos 1 /*!< QEI IES: TIM_EN Position */ +#define QEI_IES_TIM_EN_Msk (0x01UL << QEI_IES_TIM_EN_Pos) /*!< QEI IES: TIM_EN Mask */ +#define QEI_IES_VELC_EN_Pos 2 /*!< QEI IES: VELC_EN Position */ +#define QEI_IES_VELC_EN_Msk (0x01UL << QEI_IES_VELC_EN_Pos) /*!< QEI IES: VELC_EN Mask */ +#define QEI_IES_DIR_EN_Pos 3 /*!< QEI IES: DIR_EN Position */ +#define QEI_IES_DIR_EN_Msk (0x01UL << QEI_IES_DIR_EN_Pos) /*!< QEI IES: DIR_EN Mask */ +#define QEI_IES_ERR_EN_Pos 4 /*!< QEI IES: ERR_EN Position */ +#define QEI_IES_ERR_EN_Msk (0x01UL << QEI_IES_ERR_EN_Pos) /*!< QEI IES: ERR_EN Mask */ +#define QEI_IES_ENCLK_EN_Pos 5 /*!< QEI IES: ENCLK_EN Position */ +#define QEI_IES_ENCLK_EN_Msk (0x01UL << QEI_IES_ENCLK_EN_Pos) /*!< QEI IES: ENCLK_EN Mask */ +#define QEI_IES_POS0_Int_Pos 6 /*!< QEI IES: POS0_Int Position */ +#define QEI_IES_POS0_Int_Msk (0x01UL << QEI_IES_POS0_Int_Pos) /*!< QEI IES: POS0_Int Mask */ +#define QEI_IES_POS1_Int_Pos 7 /*!< QEI IES: POS1_Int Position */ +#define QEI_IES_POS1_Int_Msk (0x01UL << QEI_IES_POS1_Int_Pos) /*!< QEI IES: POS1_Int Mask */ +#define QEI_IES_POS2_Int_Pos 8 /*!< QEI IES: POS2_Int Position */ +#define QEI_IES_POS2_Int_Msk (0x01UL << QEI_IES_POS2_Int_Pos) /*!< QEI IES: POS2_Int Mask */ +#define QEI_IES_REV_Int_Pos 9 /*!< QEI IES: REV_Int Position */ +#define QEI_IES_REV_Int_Msk (0x01UL << QEI_IES_REV_Int_Pos) /*!< QEI IES: REV_Int Mask */ +#define QEI_IES_POS0REV_Int_Pos 10 /*!< QEI IES: POS0REV_Int Position */ +#define QEI_IES_POS0REV_Int_Msk (0x01UL << QEI_IES_POS0REV_Int_Pos) /*!< QEI IES: POS0REV_Int Mask */ +#define QEI_IES_POS1REV_Int_Pos 11 /*!< QEI IES: POS1REV_Int Position */ +#define QEI_IES_POS1REV_Int_Msk (0x01UL << QEI_IES_POS1REV_Int_Pos) /*!< QEI IES: POS1REV_Int Mask */ +#define QEI_IES_POS2REV_Int_Pos 12 /*!< QEI IES: POS2REV_Int Position */ +#define QEI_IES_POS2REV_Int_Msk (0x01UL << QEI_IES_POS2REV_Int_Pos) /*!< QEI IES: POS2REV_Int Mask */ +#define QEI_IES_REV1_Int_Pos 13 /*!< QEI IES: REV1_Int Position */ +#define QEI_IES_REV1_Int_Msk (0x01UL << QEI_IES_REV1_Int_Pos) /*!< QEI IES: REV1_Int Mask */ +#define QEI_IES_REV2_Int_Pos 14 /*!< QEI IES: REV2_Int Position */ +#define QEI_IES_REV2_Int_Msk (0x01UL << QEI_IES_REV2_Int_Pos) /*!< QEI IES: REV2_Int Mask */ +#define QEI_IES_MAXPOS_Int_Pos 15 /*!< QEI IES: MAXPOS_Int Position */ +#define QEI_IES_MAXPOS_Int_Msk (0x01UL << QEI_IES_MAXPOS_Int_Pos) /*!< QEI IES: MAXPOS_Int Mask */ + +/* --------------------------------- QEI_INTSTAT -------------------------------- */ +#define QEI_INTSTAT_INX_Int_Pos 0 /*!< QEI INTSTAT: INX_Int Position */ +#define QEI_INTSTAT_INX_Int_Msk (0x01UL << QEI_INTSTAT_INX_Int_Pos) /*!< QEI INTSTAT: INX_Int Mask */ +#define QEI_INTSTAT_TIM_Int_Pos 1 /*!< QEI INTSTAT: TIM_Int Position */ +#define QEI_INTSTAT_TIM_Int_Msk (0x01UL << QEI_INTSTAT_TIM_Int_Pos) /*!< QEI INTSTAT: TIM_Int Mask */ +#define QEI_INTSTAT_VELC_Int_Pos 2 /*!< QEI INTSTAT: VELC_Int Position */ +#define QEI_INTSTAT_VELC_Int_Msk (0x01UL << QEI_INTSTAT_VELC_Int_Pos) /*!< QEI INTSTAT: VELC_Int Mask */ +#define QEI_INTSTAT_DIR_Int_Pos 3 /*!< QEI INTSTAT: DIR_Int Position */ +#define QEI_INTSTAT_DIR_Int_Msk (0x01UL << QEI_INTSTAT_DIR_Int_Pos) /*!< QEI INTSTAT: DIR_Int Mask */ +#define QEI_INTSTAT_ERR_Int_Pos 4 /*!< QEI INTSTAT: ERR_Int Position */ +#define QEI_INTSTAT_ERR_Int_Msk (0x01UL << QEI_INTSTAT_ERR_Int_Pos) /*!< QEI INTSTAT: ERR_Int Mask */ +#define QEI_INTSTAT_ENCLK_Int_Pos 5 /*!< QEI INTSTAT: ENCLK_Int Position */ +#define QEI_INTSTAT_ENCLK_Int_Msk (0x01UL << QEI_INTSTAT_ENCLK_Int_Pos) /*!< QEI INTSTAT: ENCLK_Int Mask */ +#define QEI_INTSTAT_POS0_Int_Pos 6 /*!< QEI INTSTAT: POS0_Int Position */ +#define QEI_INTSTAT_POS0_Int_Msk (0x01UL << QEI_INTSTAT_POS0_Int_Pos) /*!< QEI INTSTAT: POS0_Int Mask */ +#define QEI_INTSTAT_POS1_Int_Pos 7 /*!< QEI INTSTAT: POS1_Int Position */ +#define QEI_INTSTAT_POS1_Int_Msk (0x01UL << QEI_INTSTAT_POS1_Int_Pos) /*!< QEI INTSTAT: POS1_Int Mask */ +#define QEI_INTSTAT_POS2_Int_Pos 8 /*!< QEI INTSTAT: POS2_Int Position */ +#define QEI_INTSTAT_POS2_Int_Msk (0x01UL << QEI_INTSTAT_POS2_Int_Pos) /*!< QEI INTSTAT: POS2_Int Mask */ +#define QEI_INTSTAT_REV_Int_Pos 9 /*!< QEI INTSTAT: REV_Int Position */ +#define QEI_INTSTAT_REV_Int_Msk (0x01UL << QEI_INTSTAT_REV_Int_Pos) /*!< QEI INTSTAT: REV_Int Mask */ +#define QEI_INTSTAT_POS0REV_Int_Pos 10 /*!< QEI INTSTAT: POS0REV_Int Position */ +#define QEI_INTSTAT_POS0REV_Int_Msk (0x01UL << QEI_INTSTAT_POS0REV_Int_Pos) /*!< QEI INTSTAT: POS0REV_Int Mask */ +#define QEI_INTSTAT_POS1REV_Int_Pos 11 /*!< QEI INTSTAT: POS1REV_Int Position */ +#define QEI_INTSTAT_POS1REV_Int_Msk (0x01UL << QEI_INTSTAT_POS1REV_Int_Pos) /*!< QEI INTSTAT: POS1REV_Int Mask */ +#define QEI_INTSTAT_POS2REV_Int_Pos 12 /*!< QEI INTSTAT: POS2REV_Int Position */ +#define QEI_INTSTAT_POS2REV_Int_Msk (0x01UL << QEI_INTSTAT_POS2REV_Int_Pos) /*!< QEI INTSTAT: POS2REV_Int Mask */ +#define QEI_INTSTAT_REV1_Int_Pos 13 /*!< QEI INTSTAT: REV1_Int Position */ +#define QEI_INTSTAT_REV1_Int_Msk (0x01UL << QEI_INTSTAT_REV1_Int_Pos) /*!< QEI INTSTAT: REV1_Int Mask */ +#define QEI_INTSTAT_REV2_Int_Pos 14 /*!< QEI INTSTAT: REV2_Int Position */ +#define QEI_INTSTAT_REV2_Int_Msk (0x01UL << QEI_INTSTAT_REV2_Int_Pos) /*!< QEI INTSTAT: REV2_Int Mask */ +#define QEI_INTSTAT_MAXPOS_Int_Pos 15 /*!< QEI INTSTAT: MAXPOS_Int Position */ +#define QEI_INTSTAT_MAXPOS_Int_Msk (0x01UL << QEI_INTSTAT_MAXPOS_Int_Pos) /*!< QEI INTSTAT: MAXPOS_Int Mask */ + +/* ----------------------------------- QEI_IE ----------------------------------- */ +#define QEI_IE_INX_Int_Pos 0 /*!< QEI IE: INX_Int Position */ +#define QEI_IE_INX_Int_Msk (0x01UL << QEI_IE_INX_Int_Pos) /*!< QEI IE: INX_Int Mask */ +#define QEI_IE_TIM_Int_Pos 1 /*!< QEI IE: TIM_Int Position */ +#define QEI_IE_TIM_Int_Msk (0x01UL << QEI_IE_TIM_Int_Pos) /*!< QEI IE: TIM_Int Mask */ +#define QEI_IE_VELC_Int_Pos 2 /*!< QEI IE: VELC_Int Position */ +#define QEI_IE_VELC_Int_Msk (0x01UL << QEI_IE_VELC_Int_Pos) /*!< QEI IE: VELC_Int Mask */ +#define QEI_IE_DIR_Int_Pos 3 /*!< QEI IE: DIR_Int Position */ +#define QEI_IE_DIR_Int_Msk (0x01UL << QEI_IE_DIR_Int_Pos) /*!< QEI IE: DIR_Int Mask */ +#define QEI_IE_ERR_Int_Pos 4 /*!< QEI IE: ERR_Int Position */ +#define QEI_IE_ERR_Int_Msk (0x01UL << QEI_IE_ERR_Int_Pos) /*!< QEI IE: ERR_Int Mask */ +#define QEI_IE_ENCLK_Int_Pos 5 /*!< QEI IE: ENCLK_Int Position */ +#define QEI_IE_ENCLK_Int_Msk (0x01UL << QEI_IE_ENCLK_Int_Pos) /*!< QEI IE: ENCLK_Int Mask */ +#define QEI_IE_POS0_Int_Pos 6 /*!< QEI IE: POS0_Int Position */ +#define QEI_IE_POS0_Int_Msk (0x01UL << QEI_IE_POS0_Int_Pos) /*!< QEI IE: POS0_Int Mask */ +#define QEI_IE_POS1_Int_Pos 7 /*!< QEI IE: POS1_Int Position */ +#define QEI_IE_POS1_Int_Msk (0x01UL << QEI_IE_POS1_Int_Pos) /*!< QEI IE: POS1_Int Mask */ +#define QEI_IE_POS2_Int_Pos 8 /*!< QEI IE: POS2_Int Position */ +#define QEI_IE_POS2_Int_Msk (0x01UL << QEI_IE_POS2_Int_Pos) /*!< QEI IE: POS2_Int Mask */ +#define QEI_IE_REV_Int_Pos 9 /*!< QEI IE: REV_Int Position */ +#define QEI_IE_REV_Int_Msk (0x01UL << QEI_IE_REV_Int_Pos) /*!< QEI IE: REV_Int Mask */ +#define QEI_IE_POS0REV_Int_Pos 10 /*!< QEI IE: POS0REV_Int Position */ +#define QEI_IE_POS0REV_Int_Msk (0x01UL << QEI_IE_POS0REV_Int_Pos) /*!< QEI IE: POS0REV_Int Mask */ +#define QEI_IE_POS1REV_Int_Pos 11 /*!< QEI IE: POS1REV_Int Position */ +#define QEI_IE_POS1REV_Int_Msk (0x01UL << QEI_IE_POS1REV_Int_Pos) /*!< QEI IE: POS1REV_Int Mask */ +#define QEI_IE_POS2REV_Int_Pos 12 /*!< QEI IE: POS2REV_Int Position */ +#define QEI_IE_POS2REV_Int_Msk (0x01UL << QEI_IE_POS2REV_Int_Pos) /*!< QEI IE: POS2REV_Int Mask */ +#define QEI_IE_REV1_Int_Pos 13 /*!< QEI IE: REV1_Int Position */ +#define QEI_IE_REV1_Int_Msk (0x01UL << QEI_IE_REV1_Int_Pos) /*!< QEI IE: REV1_Int Mask */ +#define QEI_IE_REV2_Int_Pos 14 /*!< QEI IE: REV2_Int Position */ +#define QEI_IE_REV2_Int_Msk (0x01UL << QEI_IE_REV2_Int_Pos) /*!< QEI IE: REV2_Int Mask */ +#define QEI_IE_MAXPOS_Int_Pos 15 /*!< QEI IE: MAXPOS_Int Position */ +#define QEI_IE_MAXPOS_Int_Msk (0x01UL << QEI_IE_MAXPOS_Int_Pos) /*!< QEI IE: MAXPOS_Int Mask */ + +/* ----------------------------------- QEI_CLR ---------------------------------- */ +#define QEI_CLR_INX_Int_Pos 0 /*!< QEI CLR: INX_Int Position */ +#define QEI_CLR_INX_Int_Msk (0x01UL << QEI_CLR_INX_Int_Pos) /*!< QEI CLR: INX_Int Mask */ +#define QEI_CLR_TIM_Int_Pos 1 /*!< QEI CLR: TIM_Int Position */ +#define QEI_CLR_TIM_Int_Msk (0x01UL << QEI_CLR_TIM_Int_Pos) /*!< QEI CLR: TIM_Int Mask */ +#define QEI_CLR_VELC_Int_Pos 2 /*!< QEI CLR: VELC_Int Position */ +#define QEI_CLR_VELC_Int_Msk (0x01UL << QEI_CLR_VELC_Int_Pos) /*!< QEI CLR: VELC_Int Mask */ +#define QEI_CLR_DIR_Int_Pos 3 /*!< QEI CLR: DIR_Int Position */ +#define QEI_CLR_DIR_Int_Msk (0x01UL << QEI_CLR_DIR_Int_Pos) /*!< QEI CLR: DIR_Int Mask */ +#define QEI_CLR_ERR_Int_Pos 4 /*!< QEI CLR: ERR_Int Position */ +#define QEI_CLR_ERR_Int_Msk (0x01UL << QEI_CLR_ERR_Int_Pos) /*!< QEI CLR: ERR_Int Mask */ +#define QEI_CLR_ENCLK_Int_Pos 5 /*!< QEI CLR: ENCLK_Int Position */ +#define QEI_CLR_ENCLK_Int_Msk (0x01UL << QEI_CLR_ENCLK_Int_Pos) /*!< QEI CLR: ENCLK_Int Mask */ +#define QEI_CLR_POS0_Int_Pos 6 /*!< QEI CLR: POS0_Int Position */ +#define QEI_CLR_POS0_Int_Msk (0x01UL << QEI_CLR_POS0_Int_Pos) /*!< QEI CLR: POS0_Int Mask */ +#define QEI_CLR_POS1_Int_Pos 7 /*!< QEI CLR: POS1_Int Position */ +#define QEI_CLR_POS1_Int_Msk (0x01UL << QEI_CLR_POS1_Int_Pos) /*!< QEI CLR: POS1_Int Mask */ +#define QEI_CLR_POS2_Int_Pos 8 /*!< QEI CLR: POS2_Int Position */ +#define QEI_CLR_POS2_Int_Msk (0x01UL << QEI_CLR_POS2_Int_Pos) /*!< QEI CLR: POS2_Int Mask */ +#define QEI_CLR_REV_Int_Pos 9 /*!< QEI CLR: REV_Int Position */ +#define QEI_CLR_REV_Int_Msk (0x01UL << QEI_CLR_REV_Int_Pos) /*!< QEI CLR: REV_Int Mask */ +#define QEI_CLR_POS0REV_Int_Pos 10 /*!< QEI CLR: POS0REV_Int Position */ +#define QEI_CLR_POS0REV_Int_Msk (0x01UL << QEI_CLR_POS0REV_Int_Pos) /*!< QEI CLR: POS0REV_Int Mask */ +#define QEI_CLR_POS1REV_Int_Pos 11 /*!< QEI CLR: POS1REV_Int Position */ +#define QEI_CLR_POS1REV_Int_Msk (0x01UL << QEI_CLR_POS1REV_Int_Pos) /*!< QEI CLR: POS1REV_Int Mask */ +#define QEI_CLR_REV1_Int_Pos 13 /*!< QEI CLR: REV1_Int Position */ +#define QEI_CLR_REV1_Int_Msk (0x01UL << QEI_CLR_REV1_Int_Pos) /*!< QEI CLR: REV1_Int Mask */ +#define QEI_CLR_REV2_Int_Pos 14 /*!< QEI CLR: REV2_Int Position */ +#define QEI_CLR_REV2_Int_Msk (0x01UL << QEI_CLR_REV2_Int_Pos) /*!< QEI CLR: REV2_Int Mask */ +#define QEI_CLR_MAXPOS_Int_Pos 15 /*!< QEI CLR: MAXPOS_Int Position */ +#define QEI_CLR_MAXPOS_Int_Msk (0x01UL << QEI_CLR_MAXPOS_Int_Pos) /*!< QEI CLR: MAXPOS_Int Mask */ + +/* ----------------------------------- QEI_SET ---------------------------------- */ +#define QEI_SET_INX_Int_Pos 0 /*!< QEI SET: INX_Int Position */ +#define QEI_SET_INX_Int_Msk (0x01UL << QEI_SET_INX_Int_Pos) /*!< QEI SET: INX_Int Mask */ +#define QEI_SET_TIM_Int_Pos 1 /*!< QEI SET: TIM_Int Position */ +#define QEI_SET_TIM_Int_Msk (0x01UL << QEI_SET_TIM_Int_Pos) /*!< QEI SET: TIM_Int Mask */ +#define QEI_SET_VELC_Int_Pos 2 /*!< QEI SET: VELC_Int Position */ +#define QEI_SET_VELC_Int_Msk (0x01UL << QEI_SET_VELC_Int_Pos) /*!< QEI SET: VELC_Int Mask */ +#define QEI_SET_DIR_Int_Pos 3 /*!< QEI SET: DIR_Int Position */ +#define QEI_SET_DIR_Int_Msk (0x01UL << QEI_SET_DIR_Int_Pos) /*!< QEI SET: DIR_Int Mask */ +#define QEI_SET_ERR_Int_Pos 4 /*!< QEI SET: ERR_Int Position */ +#define QEI_SET_ERR_Int_Msk (0x01UL << QEI_SET_ERR_Int_Pos) /*!< QEI SET: ERR_Int Mask */ +#define QEI_SET_ENCLK_Int_Pos 5 /*!< QEI SET: ENCLK_Int Position */ +#define QEI_SET_ENCLK_Int_Msk (0x01UL << QEI_SET_ENCLK_Int_Pos) /*!< QEI SET: ENCLK_Int Mask */ +#define QEI_SET_POS0_Int_Pos 6 /*!< QEI SET: POS0_Int Position */ +#define QEI_SET_POS0_Int_Msk (0x01UL << QEI_SET_POS0_Int_Pos) /*!< QEI SET: POS0_Int Mask */ +#define QEI_SET_POS1_Int_Pos 7 /*!< QEI SET: POS1_Int Position */ +#define QEI_SET_POS1_Int_Msk (0x01UL << QEI_SET_POS1_Int_Pos) /*!< QEI SET: POS1_Int Mask */ +#define QEI_SET_POS2_Int_Pos 8 /*!< QEI SET: POS2_Int Position */ +#define QEI_SET_POS2_Int_Msk (0x01UL << QEI_SET_POS2_Int_Pos) /*!< QEI SET: POS2_Int Mask */ +#define QEI_SET_REV_Int_Pos 9 /*!< QEI SET: REV_Int Position */ +#define QEI_SET_REV_Int_Msk (0x01UL << QEI_SET_REV_Int_Pos) /*!< QEI SET: REV_Int Mask */ +#define QEI_SET_POS0REV_Int_Pos 10 /*!< QEI SET: POS0REV_Int Position */ +#define QEI_SET_POS0REV_Int_Msk (0x01UL << QEI_SET_POS0REV_Int_Pos) /*!< QEI SET: POS0REV_Int Mask */ +#define QEI_SET_POS1REV_Int_Pos 11 /*!< QEI SET: POS1REV_Int Position */ +#define QEI_SET_POS1REV_Int_Msk (0x01UL << QEI_SET_POS1REV_Int_Pos) /*!< QEI SET: POS1REV_Int Mask */ +#define QEI_SET_POS2REV_Int_Pos 12 /*!< QEI SET: POS2REV_Int Position */ +#define QEI_SET_POS2REV_Int_Msk (0x01UL << QEI_SET_POS2REV_Int_Pos) /*!< QEI SET: POS2REV_Int Mask */ +#define QEI_SET_REV1_Int_Pos 13 /*!< QEI SET: REV1_Int Position */ +#define QEI_SET_REV1_Int_Msk (0x01UL << QEI_SET_REV1_Int_Pos) /*!< QEI SET: REV1_Int Mask */ +#define QEI_SET_REV2_Int_Pos 14 /*!< QEI SET: REV2_Int Position */ +#define QEI_SET_REV2_Int_Msk (0x01UL << QEI_SET_REV2_Int_Pos) /*!< QEI SET: REV2_Int Mask */ +#define QEI_SET_MAXPOS_Int_Pos 15 /*!< QEI SET: MAXPOS_Int Position */ +#define QEI_SET_MAXPOS_Int_Msk (0x01UL << QEI_SET_MAXPOS_Int_Pos) /*!< QEI SET: MAXPOS_Int Mask */ + + +/* ================================================================================ */ +/* ================ struct 'GIMA' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- GIMA_CAP0_0_IN ------------------------------- */ +#define GIMA_CAP0_0_IN_INV_Pos 0 /*!< GIMA CAP0_0_IN: INV Position */ +#define GIMA_CAP0_0_IN_INV_Msk (0x01UL << GIMA_CAP0_0_IN_INV_Pos) /*!< GIMA CAP0_0_IN: INV Mask */ +#define GIMA_CAP0_0_IN_EDGE_Pos 1 /*!< GIMA CAP0_0_IN: EDGE Position */ +#define GIMA_CAP0_0_IN_EDGE_Msk (0x01UL << GIMA_CAP0_0_IN_EDGE_Pos) /*!< GIMA CAP0_0_IN: EDGE Mask */ +#define GIMA_CAP0_0_IN_SYNCH_Pos 2 /*!< GIMA CAP0_0_IN: SYNCH Position */ +#define GIMA_CAP0_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_0_IN_SYNCH_Pos) /*!< GIMA CAP0_0_IN: SYNCH Mask */ +#define GIMA_CAP0_0_IN_PULSE_Pos 3 /*!< GIMA CAP0_0_IN: PULSE Position */ +#define GIMA_CAP0_0_IN_PULSE_Msk (0x01UL << GIMA_CAP0_0_IN_PULSE_Pos) /*!< GIMA CAP0_0_IN: PULSE Mask */ +#define GIMA_CAP0_0_IN_SELECT_Pos 4 /*!< GIMA CAP0_0_IN: SELECT Position */ +#define GIMA_CAP0_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_0_IN_SELECT_Pos) /*!< GIMA CAP0_0_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CAP0_1_IN ------------------------------- */ +#define GIMA_CAP0_1_IN_INV_Pos 0 /*!< GIMA CAP0_1_IN: INV Position */ +#define GIMA_CAP0_1_IN_INV_Msk (0x01UL << GIMA_CAP0_1_IN_INV_Pos) /*!< GIMA CAP0_1_IN: INV Mask */ +#define GIMA_CAP0_1_IN_EDGE_Pos 1 /*!< GIMA CAP0_1_IN: EDGE Position */ +#define GIMA_CAP0_1_IN_EDGE_Msk (0x01UL << GIMA_CAP0_1_IN_EDGE_Pos) /*!< GIMA CAP0_1_IN: EDGE Mask */ +#define GIMA_CAP0_1_IN_SYNCH_Pos 2 /*!< GIMA CAP0_1_IN: SYNCH Position */ +#define GIMA_CAP0_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_1_IN_SYNCH_Pos) /*!< GIMA CAP0_1_IN: SYNCH Mask */ +#define GIMA_CAP0_1_IN_PULSE_Pos 3 /*!< GIMA CAP0_1_IN: PULSE Position */ +#define GIMA_CAP0_1_IN_PULSE_Msk (0x01UL << GIMA_CAP0_1_IN_PULSE_Pos) /*!< GIMA CAP0_1_IN: PULSE Mask */ +#define GIMA_CAP0_1_IN_SELECT_Pos 4 /*!< GIMA CAP0_1_IN: SELECT Position */ +#define GIMA_CAP0_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_1_IN_SELECT_Pos) /*!< GIMA CAP0_1_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CAP0_2_IN ------------------------------- */ +#define GIMA_CAP0_2_IN_INV_Pos 0 /*!< GIMA CAP0_2_IN: INV Position */ +#define GIMA_CAP0_2_IN_INV_Msk (0x01UL << GIMA_CAP0_2_IN_INV_Pos) /*!< GIMA CAP0_2_IN: INV Mask */ +#define GIMA_CAP0_2_IN_EDGE_Pos 1 /*!< GIMA CAP0_2_IN: EDGE Position */ +#define GIMA_CAP0_2_IN_EDGE_Msk (0x01UL << GIMA_CAP0_2_IN_EDGE_Pos) /*!< GIMA CAP0_2_IN: EDGE Mask */ +#define GIMA_CAP0_2_IN_SYNCH_Pos 2 /*!< GIMA CAP0_2_IN: SYNCH Position */ +#define GIMA_CAP0_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_2_IN_SYNCH_Pos) /*!< GIMA CAP0_2_IN: SYNCH Mask */ +#define GIMA_CAP0_2_IN_PULSE_Pos 3 /*!< GIMA CAP0_2_IN: PULSE Position */ +#define GIMA_CAP0_2_IN_PULSE_Msk (0x01UL << GIMA_CAP0_2_IN_PULSE_Pos) /*!< GIMA CAP0_2_IN: PULSE Mask */ +#define GIMA_CAP0_2_IN_SELECT_Pos 4 /*!< GIMA CAP0_2_IN: SELECT Position */ +#define GIMA_CAP0_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_2_IN_SELECT_Pos) /*!< GIMA CAP0_2_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CAP0_3_IN ------------------------------- */ +#define GIMA_CAP0_3_IN_INV_Pos 0 /*!< GIMA CAP0_3_IN: INV Position */ +#define GIMA_CAP0_3_IN_INV_Msk (0x01UL << GIMA_CAP0_3_IN_INV_Pos) /*!< GIMA CAP0_3_IN: INV Mask */ +#define GIMA_CAP0_3_IN_EDGE_Pos 1 /*!< GIMA CAP0_3_IN: EDGE Position */ +#define GIMA_CAP0_3_IN_EDGE_Msk (0x01UL << GIMA_CAP0_3_IN_EDGE_Pos) /*!< GIMA CAP0_3_IN: EDGE Mask */ +#define GIMA_CAP0_3_IN_SYNCH_Pos 2 /*!< GIMA CAP0_3_IN: SYNCH Position */ +#define GIMA_CAP0_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_3_IN_SYNCH_Pos) /*!< GIMA CAP0_3_IN: SYNCH Mask */ +#define GIMA_CAP0_3_IN_PULSE_Pos 3 /*!< GIMA CAP0_3_IN: PULSE Position */ +#define GIMA_CAP0_3_IN_PULSE_Msk (0x01UL << GIMA_CAP0_3_IN_PULSE_Pos) /*!< GIMA CAP0_3_IN: PULSE Mask */ +#define GIMA_CAP0_3_IN_SELECT_Pos 4 /*!< GIMA CAP0_3_IN: SELECT Position */ +#define GIMA_CAP0_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_3_IN_SELECT_Pos) /*!< GIMA CAP0_3_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CAP1_0_IN ------------------------------- */ +#define GIMA_CAP1_0_IN_INV_Pos 0 /*!< GIMA CAP1_0_IN: INV Position */ +#define GIMA_CAP1_0_IN_INV_Msk (0x01UL << GIMA_CAP1_0_IN_INV_Pos) /*!< GIMA CAP1_0_IN: INV Mask */ +#define GIMA_CAP1_0_IN_EDGE_Pos 1 /*!< GIMA CAP1_0_IN: EDGE Position */ +#define GIMA_CAP1_0_IN_EDGE_Msk (0x01UL << GIMA_CAP1_0_IN_EDGE_Pos) /*!< GIMA CAP1_0_IN: EDGE Mask */ +#define GIMA_CAP1_0_IN_SYNCH_Pos 2 /*!< GIMA CAP1_0_IN: SYNCH Position */ +#define GIMA_CAP1_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_0_IN_SYNCH_Pos) /*!< GIMA CAP1_0_IN: SYNCH Mask */ +#define GIMA_CAP1_0_IN_PULSE_Pos 3 /*!< GIMA CAP1_0_IN: PULSE Position */ +#define GIMA_CAP1_0_IN_PULSE_Msk (0x01UL << GIMA_CAP1_0_IN_PULSE_Pos) /*!< GIMA CAP1_0_IN: PULSE Mask */ +#define GIMA_CAP1_0_IN_SELECT_Pos 4 /*!< GIMA CAP1_0_IN: SELECT Position */ +#define GIMA_CAP1_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_0_IN_SELECT_Pos) /*!< GIMA CAP1_0_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CAP1_1_IN ------------------------------- */ +#define GIMA_CAP1_1_IN_INV_Pos 0 /*!< GIMA CAP1_1_IN: INV Position */ +#define GIMA_CAP1_1_IN_INV_Msk (0x01UL << GIMA_CAP1_1_IN_INV_Pos) /*!< GIMA CAP1_1_IN: INV Mask */ +#define GIMA_CAP1_1_IN_EDGE_Pos 1 /*!< GIMA CAP1_1_IN: EDGE Position */ +#define GIMA_CAP1_1_IN_EDGE_Msk (0x01UL << GIMA_CAP1_1_IN_EDGE_Pos) /*!< GIMA CAP1_1_IN: EDGE Mask */ +#define GIMA_CAP1_1_IN_SYNCH_Pos 2 /*!< GIMA CAP1_1_IN: SYNCH Position */ +#define GIMA_CAP1_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_1_IN_SYNCH_Pos) /*!< GIMA CAP1_1_IN: SYNCH Mask */ +#define GIMA_CAP1_1_IN_PULSE_Pos 3 /*!< GIMA CAP1_1_IN: PULSE Position */ +#define GIMA_CAP1_1_IN_PULSE_Msk (0x01UL << GIMA_CAP1_1_IN_PULSE_Pos) /*!< GIMA CAP1_1_IN: PULSE Mask */ +#define GIMA_CAP1_1_IN_SELECT_Pos 4 /*!< GIMA CAP1_1_IN: SELECT Position */ +#define GIMA_CAP1_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_1_IN_SELECT_Pos) /*!< GIMA CAP1_1_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CAP1_2_IN ------------------------------- */ +#define GIMA_CAP1_2_IN_INV_Pos 0 /*!< GIMA CAP1_2_IN: INV Position */ +#define GIMA_CAP1_2_IN_INV_Msk (0x01UL << GIMA_CAP1_2_IN_INV_Pos) /*!< GIMA CAP1_2_IN: INV Mask */ +#define GIMA_CAP1_2_IN_EDGE_Pos 1 /*!< GIMA CAP1_2_IN: EDGE Position */ +#define GIMA_CAP1_2_IN_EDGE_Msk (0x01UL << GIMA_CAP1_2_IN_EDGE_Pos) /*!< GIMA CAP1_2_IN: EDGE Mask */ +#define GIMA_CAP1_2_IN_SYNCH_Pos 2 /*!< GIMA CAP1_2_IN: SYNCH Position */ +#define GIMA_CAP1_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_2_IN_SYNCH_Pos) /*!< GIMA CAP1_2_IN: SYNCH Mask */ +#define GIMA_CAP1_2_IN_PULSE_Pos 3 /*!< GIMA CAP1_2_IN: PULSE Position */ +#define GIMA_CAP1_2_IN_PULSE_Msk (0x01UL << GIMA_CAP1_2_IN_PULSE_Pos) /*!< GIMA CAP1_2_IN: PULSE Mask */ +#define GIMA_CAP1_2_IN_SELECT_Pos 4 /*!< GIMA CAP1_2_IN: SELECT Position */ +#define GIMA_CAP1_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_2_IN_SELECT_Pos) /*!< GIMA CAP1_2_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CAP1_3_IN ------------------------------- */ +#define GIMA_CAP1_3_IN_INV_Pos 0 /*!< GIMA CAP1_3_IN: INV Position */ +#define GIMA_CAP1_3_IN_INV_Msk (0x01UL << GIMA_CAP1_3_IN_INV_Pos) /*!< GIMA CAP1_3_IN: INV Mask */ +#define GIMA_CAP1_3_IN_EDGE_Pos 1 /*!< GIMA CAP1_3_IN: EDGE Position */ +#define GIMA_CAP1_3_IN_EDGE_Msk (0x01UL << GIMA_CAP1_3_IN_EDGE_Pos) /*!< GIMA CAP1_3_IN: EDGE Mask */ +#define GIMA_CAP1_3_IN_SYNCH_Pos 2 /*!< GIMA CAP1_3_IN: SYNCH Position */ +#define GIMA_CAP1_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_3_IN_SYNCH_Pos) /*!< GIMA CAP1_3_IN: SYNCH Mask */ +#define GIMA_CAP1_3_IN_PULSE_Pos 3 /*!< GIMA CAP1_3_IN: PULSE Position */ +#define GIMA_CAP1_3_IN_PULSE_Msk (0x01UL << GIMA_CAP1_3_IN_PULSE_Pos) /*!< GIMA CAP1_3_IN: PULSE Mask */ +#define GIMA_CAP1_3_IN_SELECT_Pos 4 /*!< GIMA CAP1_3_IN: SELECT Position */ +#define GIMA_CAP1_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_3_IN_SELECT_Pos) /*!< GIMA CAP1_3_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CAP2_0_IN ------------------------------- */ +#define GIMA_CAP2_0_IN_INV_Pos 0 /*!< GIMA CAP2_0_IN: INV Position */ +#define GIMA_CAP2_0_IN_INV_Msk (0x01UL << GIMA_CAP2_0_IN_INV_Pos) /*!< GIMA CAP2_0_IN: INV Mask */ +#define GIMA_CAP2_0_IN_EDGE_Pos 1 /*!< GIMA CAP2_0_IN: EDGE Position */ +#define GIMA_CAP2_0_IN_EDGE_Msk (0x01UL << GIMA_CAP2_0_IN_EDGE_Pos) /*!< GIMA CAP2_0_IN: EDGE Mask */ +#define GIMA_CAP2_0_IN_SYNCH_Pos 2 /*!< GIMA CAP2_0_IN: SYNCH Position */ +#define GIMA_CAP2_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_0_IN_SYNCH_Pos) /*!< GIMA CAP2_0_IN: SYNCH Mask */ +#define GIMA_CAP2_0_IN_PULSE_Pos 3 /*!< GIMA CAP2_0_IN: PULSE Position */ +#define GIMA_CAP2_0_IN_PULSE_Msk (0x01UL << GIMA_CAP2_0_IN_PULSE_Pos) /*!< GIMA CAP2_0_IN: PULSE Mask */ +#define GIMA_CAP2_0_IN_SELECT_Pos 4 /*!< GIMA CAP2_0_IN: SELECT Position */ +#define GIMA_CAP2_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_0_IN_SELECT_Pos) /*!< GIMA CAP2_0_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CAP2_1_IN ------------------------------- */ +#define GIMA_CAP2_1_IN_INV_Pos 0 /*!< GIMA CAP2_1_IN: INV Position */ +#define GIMA_CAP2_1_IN_INV_Msk (0x01UL << GIMA_CAP2_1_IN_INV_Pos) /*!< GIMA CAP2_1_IN: INV Mask */ +#define GIMA_CAP2_1_IN_EDGE_Pos 1 /*!< GIMA CAP2_1_IN: EDGE Position */ +#define GIMA_CAP2_1_IN_EDGE_Msk (0x01UL << GIMA_CAP2_1_IN_EDGE_Pos) /*!< GIMA CAP2_1_IN: EDGE Mask */ +#define GIMA_CAP2_1_IN_SYNCH_Pos 2 /*!< GIMA CAP2_1_IN: SYNCH Position */ +#define GIMA_CAP2_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_1_IN_SYNCH_Pos) /*!< GIMA CAP2_1_IN: SYNCH Mask */ +#define GIMA_CAP2_1_IN_PULSE_Pos 3 /*!< GIMA CAP2_1_IN: PULSE Position */ +#define GIMA_CAP2_1_IN_PULSE_Msk (0x01UL << GIMA_CAP2_1_IN_PULSE_Pos) /*!< GIMA CAP2_1_IN: PULSE Mask */ +#define GIMA_CAP2_1_IN_SELECT_Pos 4 /*!< GIMA CAP2_1_IN: SELECT Position */ +#define GIMA_CAP2_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_1_IN_SELECT_Pos) /*!< GIMA CAP2_1_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CAP2_2_IN ------------------------------- */ +#define GIMA_CAP2_2_IN_INV_Pos 0 /*!< GIMA CAP2_2_IN: INV Position */ +#define GIMA_CAP2_2_IN_INV_Msk (0x01UL << GIMA_CAP2_2_IN_INV_Pos) /*!< GIMA CAP2_2_IN: INV Mask */ +#define GIMA_CAP2_2_IN_EDGE_Pos 1 /*!< GIMA CAP2_2_IN: EDGE Position */ +#define GIMA_CAP2_2_IN_EDGE_Msk (0x01UL << GIMA_CAP2_2_IN_EDGE_Pos) /*!< GIMA CAP2_2_IN: EDGE Mask */ +#define GIMA_CAP2_2_IN_SYNCH_Pos 2 /*!< GIMA CAP2_2_IN: SYNCH Position */ +#define GIMA_CAP2_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_2_IN_SYNCH_Pos) /*!< GIMA CAP2_2_IN: SYNCH Mask */ +#define GIMA_CAP2_2_IN_PULSE_Pos 3 /*!< GIMA CAP2_2_IN: PULSE Position */ +#define GIMA_CAP2_2_IN_PULSE_Msk (0x01UL << GIMA_CAP2_2_IN_PULSE_Pos) /*!< GIMA CAP2_2_IN: PULSE Mask */ +#define GIMA_CAP2_2_IN_SELECT_Pos 4 /*!< GIMA CAP2_2_IN: SELECT Position */ +#define GIMA_CAP2_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_2_IN_SELECT_Pos) /*!< GIMA CAP2_2_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CAP2_3_IN ------------------------------- */ +#define GIMA_CAP2_3_IN_INV_Pos 0 /*!< GIMA CAP2_3_IN: INV Position */ +#define GIMA_CAP2_3_IN_INV_Msk (0x01UL << GIMA_CAP2_3_IN_INV_Pos) /*!< GIMA CAP2_3_IN: INV Mask */ +#define GIMA_CAP2_3_IN_EDGE_Pos 1 /*!< GIMA CAP2_3_IN: EDGE Position */ +#define GIMA_CAP2_3_IN_EDGE_Msk (0x01UL << GIMA_CAP2_3_IN_EDGE_Pos) /*!< GIMA CAP2_3_IN: EDGE Mask */ +#define GIMA_CAP2_3_IN_SYNCH_Pos 2 /*!< GIMA CAP2_3_IN: SYNCH Position */ +#define GIMA_CAP2_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_3_IN_SYNCH_Pos) /*!< GIMA CAP2_3_IN: SYNCH Mask */ +#define GIMA_CAP2_3_IN_PULSE_Pos 3 /*!< GIMA CAP2_3_IN: PULSE Position */ +#define GIMA_CAP2_3_IN_PULSE_Msk (0x01UL << GIMA_CAP2_3_IN_PULSE_Pos) /*!< GIMA CAP2_3_IN: PULSE Mask */ +#define GIMA_CAP2_3_IN_SELECT_Pos 4 /*!< GIMA CAP2_3_IN: SELECT Position */ +#define GIMA_CAP2_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_3_IN_SELECT_Pos) /*!< GIMA CAP2_3_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CAP3_0_IN ------------------------------- */ +#define GIMA_CAP3_0_IN_INV_Pos 0 /*!< GIMA CAP3_0_IN: INV Position */ +#define GIMA_CAP3_0_IN_INV_Msk (0x01UL << GIMA_CAP3_0_IN_INV_Pos) /*!< GIMA CAP3_0_IN: INV Mask */ +#define GIMA_CAP3_0_IN_EDGE_Pos 1 /*!< GIMA CAP3_0_IN: EDGE Position */ +#define GIMA_CAP3_0_IN_EDGE_Msk (0x01UL << GIMA_CAP3_0_IN_EDGE_Pos) /*!< GIMA CAP3_0_IN: EDGE Mask */ +#define GIMA_CAP3_0_IN_SYNCH_Pos 2 /*!< GIMA CAP3_0_IN: SYNCH Position */ +#define GIMA_CAP3_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_0_IN_SYNCH_Pos) /*!< GIMA CAP3_0_IN: SYNCH Mask */ +#define GIMA_CAP3_0_IN_PULSE_Pos 3 /*!< GIMA CAP3_0_IN: PULSE Position */ +#define GIMA_CAP3_0_IN_PULSE_Msk (0x01UL << GIMA_CAP3_0_IN_PULSE_Pos) /*!< GIMA CAP3_0_IN: PULSE Mask */ +#define GIMA_CAP3_0_IN_SELECT_Pos 4 /*!< GIMA CAP3_0_IN: SELECT Position */ +#define GIMA_CAP3_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_0_IN_SELECT_Pos) /*!< GIMA CAP3_0_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CAP3_1_IN ------------------------------- */ +#define GIMA_CAP3_1_IN_INV_Pos 0 /*!< GIMA CAP3_1_IN: INV Position */ +#define GIMA_CAP3_1_IN_INV_Msk (0x01UL << GIMA_CAP3_1_IN_INV_Pos) /*!< GIMA CAP3_1_IN: INV Mask */ +#define GIMA_CAP3_1_IN_EDGE_Pos 1 /*!< GIMA CAP3_1_IN: EDGE Position */ +#define GIMA_CAP3_1_IN_EDGE_Msk (0x01UL << GIMA_CAP3_1_IN_EDGE_Pos) /*!< GIMA CAP3_1_IN: EDGE Mask */ +#define GIMA_CAP3_1_IN_SYNCH_Pos 2 /*!< GIMA CAP3_1_IN: SYNCH Position */ +#define GIMA_CAP3_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_1_IN_SYNCH_Pos) /*!< GIMA CAP3_1_IN: SYNCH Mask */ +#define GIMA_CAP3_1_IN_PULSE_Pos 3 /*!< GIMA CAP3_1_IN: PULSE Position */ +#define GIMA_CAP3_1_IN_PULSE_Msk (0x01UL << GIMA_CAP3_1_IN_PULSE_Pos) /*!< GIMA CAP3_1_IN: PULSE Mask */ +#define GIMA_CAP3_1_IN_SELECT_Pos 4 /*!< GIMA CAP3_1_IN: SELECT Position */ +#define GIMA_CAP3_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_1_IN_SELECT_Pos) /*!< GIMA CAP3_1_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CAP3_2_IN ------------------------------- */ +#define GIMA_CAP3_2_IN_INV_Pos 0 /*!< GIMA CAP3_2_IN: INV Position */ +#define GIMA_CAP3_2_IN_INV_Msk (0x01UL << GIMA_CAP3_2_IN_INV_Pos) /*!< GIMA CAP3_2_IN: INV Mask */ +#define GIMA_CAP3_2_IN_EDGE_Pos 1 /*!< GIMA CAP3_2_IN: EDGE Position */ +#define GIMA_CAP3_2_IN_EDGE_Msk (0x01UL << GIMA_CAP3_2_IN_EDGE_Pos) /*!< GIMA CAP3_2_IN: EDGE Mask */ +#define GIMA_CAP3_2_IN_SYNCH_Pos 2 /*!< GIMA CAP3_2_IN: SYNCH Position */ +#define GIMA_CAP3_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_2_IN_SYNCH_Pos) /*!< GIMA CAP3_2_IN: SYNCH Mask */ +#define GIMA_CAP3_2_IN_PULSE_Pos 3 /*!< GIMA CAP3_2_IN: PULSE Position */ +#define GIMA_CAP3_2_IN_PULSE_Msk (0x01UL << GIMA_CAP3_2_IN_PULSE_Pos) /*!< GIMA CAP3_2_IN: PULSE Mask */ +#define GIMA_CAP3_2_IN_SELECT_Pos 4 /*!< GIMA CAP3_2_IN: SELECT Position */ +#define GIMA_CAP3_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_2_IN_SELECT_Pos) /*!< GIMA CAP3_2_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CAP3_3_IN ------------------------------- */ +#define GIMA_CAP3_3_IN_INV_Pos 0 /*!< GIMA CAP3_3_IN: INV Position */ +#define GIMA_CAP3_3_IN_INV_Msk (0x01UL << GIMA_CAP3_3_IN_INV_Pos) /*!< GIMA CAP3_3_IN: INV Mask */ +#define GIMA_CAP3_3_IN_EDGE_Pos 1 /*!< GIMA CAP3_3_IN: EDGE Position */ +#define GIMA_CAP3_3_IN_EDGE_Msk (0x01UL << GIMA_CAP3_3_IN_EDGE_Pos) /*!< GIMA CAP3_3_IN: EDGE Mask */ +#define GIMA_CAP3_3_IN_SYNCH_Pos 2 /*!< GIMA CAP3_3_IN: SYNCH Position */ +#define GIMA_CAP3_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_3_IN_SYNCH_Pos) /*!< GIMA CAP3_3_IN: SYNCH Mask */ +#define GIMA_CAP3_3_IN_PULSE_Pos 3 /*!< GIMA CAP3_3_IN: PULSE Position */ +#define GIMA_CAP3_3_IN_PULSE_Msk (0x01UL << GIMA_CAP3_3_IN_PULSE_Pos) /*!< GIMA CAP3_3_IN: PULSE Mask */ +#define GIMA_CAP3_3_IN_SELECT_Pos 4 /*!< GIMA CAP3_3_IN: SELECT Position */ +#define GIMA_CAP3_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_3_IN_SELECT_Pos) /*!< GIMA CAP3_3_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CTIN_0_IN ------------------------------- */ +#define GIMA_CTIN_0_IN_INV_Pos 0 /*!< GIMA CTIN_0_IN: INV Position */ +#define GIMA_CTIN_0_IN_INV_Msk (0x01UL << GIMA_CTIN_0_IN_INV_Pos) /*!< GIMA CTIN_0_IN: INV Mask */ +#define GIMA_CTIN_0_IN_EDGE_Pos 1 /*!< GIMA CTIN_0_IN: EDGE Position */ +#define GIMA_CTIN_0_IN_EDGE_Msk (0x01UL << GIMA_CTIN_0_IN_EDGE_Pos) /*!< GIMA CTIN_0_IN: EDGE Mask */ +#define GIMA_CTIN_0_IN_SYNCH_Pos 2 /*!< GIMA CTIN_0_IN: SYNCH Position */ +#define GIMA_CTIN_0_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_0_IN_SYNCH_Pos) /*!< GIMA CTIN_0_IN: SYNCH Mask */ +#define GIMA_CTIN_0_IN_PULSE_Pos 3 /*!< GIMA CTIN_0_IN: PULSE Position */ +#define GIMA_CTIN_0_IN_PULSE_Msk (0x01UL << GIMA_CTIN_0_IN_PULSE_Pos) /*!< GIMA CTIN_0_IN: PULSE Mask */ +#define GIMA_CTIN_0_IN_SELECT_Pos 4 /*!< GIMA CTIN_0_IN: SELECT Position */ +#define GIMA_CTIN_0_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_0_IN_SELECT_Pos) /*!< GIMA CTIN_0_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CTIN_1_IN ------------------------------- */ +#define GIMA_CTIN_1_IN_INV_Pos 0 /*!< GIMA CTIN_1_IN: INV Position */ +#define GIMA_CTIN_1_IN_INV_Msk (0x01UL << GIMA_CTIN_1_IN_INV_Pos) /*!< GIMA CTIN_1_IN: INV Mask */ +#define GIMA_CTIN_1_IN_EDGE_Pos 1 /*!< GIMA CTIN_1_IN: EDGE Position */ +#define GIMA_CTIN_1_IN_EDGE_Msk (0x01UL << GIMA_CTIN_1_IN_EDGE_Pos) /*!< GIMA CTIN_1_IN: EDGE Mask */ +#define GIMA_CTIN_1_IN_SYNCH_Pos 2 /*!< GIMA CTIN_1_IN: SYNCH Position */ +#define GIMA_CTIN_1_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_1_IN_SYNCH_Pos) /*!< GIMA CTIN_1_IN: SYNCH Mask */ +#define GIMA_CTIN_1_IN_PULSE_Pos 3 /*!< GIMA CTIN_1_IN: PULSE Position */ +#define GIMA_CTIN_1_IN_PULSE_Msk (0x01UL << GIMA_CTIN_1_IN_PULSE_Pos) /*!< GIMA CTIN_1_IN: PULSE Mask */ +#define GIMA_CTIN_1_IN_SELECT_Pos 4 /*!< GIMA CTIN_1_IN: SELECT Position */ +#define GIMA_CTIN_1_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_1_IN_SELECT_Pos) /*!< GIMA CTIN_1_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CTIN_2_IN ------------------------------- */ +#define GIMA_CTIN_2_IN_INV_Pos 0 /*!< GIMA CTIN_2_IN: INV Position */ +#define GIMA_CTIN_2_IN_INV_Msk (0x01UL << GIMA_CTIN_2_IN_INV_Pos) /*!< GIMA CTIN_2_IN: INV Mask */ +#define GIMA_CTIN_2_IN_EDGE_Pos 1 /*!< GIMA CTIN_2_IN: EDGE Position */ +#define GIMA_CTIN_2_IN_EDGE_Msk (0x01UL << GIMA_CTIN_2_IN_EDGE_Pos) /*!< GIMA CTIN_2_IN: EDGE Mask */ +#define GIMA_CTIN_2_IN_SYNCH_Pos 2 /*!< GIMA CTIN_2_IN: SYNCH Position */ +#define GIMA_CTIN_2_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_2_IN_SYNCH_Pos) /*!< GIMA CTIN_2_IN: SYNCH Mask */ +#define GIMA_CTIN_2_IN_PULSE_Pos 3 /*!< GIMA CTIN_2_IN: PULSE Position */ +#define GIMA_CTIN_2_IN_PULSE_Msk (0x01UL << GIMA_CTIN_2_IN_PULSE_Pos) /*!< GIMA CTIN_2_IN: PULSE Mask */ +#define GIMA_CTIN_2_IN_SELECT_Pos 4 /*!< GIMA CTIN_2_IN: SELECT Position */ +#define GIMA_CTIN_2_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_2_IN_SELECT_Pos) /*!< GIMA CTIN_2_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CTIN_3_IN ------------------------------- */ +#define GIMA_CTIN_3_IN_INV_Pos 0 /*!< GIMA CTIN_3_IN: INV Position */ +#define GIMA_CTIN_3_IN_INV_Msk (0x01UL << GIMA_CTIN_3_IN_INV_Pos) /*!< GIMA CTIN_3_IN: INV Mask */ +#define GIMA_CTIN_3_IN_EDGE_Pos 1 /*!< GIMA CTIN_3_IN: EDGE Position */ +#define GIMA_CTIN_3_IN_EDGE_Msk (0x01UL << GIMA_CTIN_3_IN_EDGE_Pos) /*!< GIMA CTIN_3_IN: EDGE Mask */ +#define GIMA_CTIN_3_IN_SYNCH_Pos 2 /*!< GIMA CTIN_3_IN: SYNCH Position */ +#define GIMA_CTIN_3_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_3_IN_SYNCH_Pos) /*!< GIMA CTIN_3_IN: SYNCH Mask */ +#define GIMA_CTIN_3_IN_PULSE_Pos 3 /*!< GIMA CTIN_3_IN: PULSE Position */ +#define GIMA_CTIN_3_IN_PULSE_Msk (0x01UL << GIMA_CTIN_3_IN_PULSE_Pos) /*!< GIMA CTIN_3_IN: PULSE Mask */ +#define GIMA_CTIN_3_IN_SELECT_Pos 4 /*!< GIMA CTIN_3_IN: SELECT Position */ +#define GIMA_CTIN_3_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_3_IN_SELECT_Pos) /*!< GIMA CTIN_3_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CTIN_4_IN ------------------------------- */ +#define GIMA_CTIN_4_IN_INV_Pos 0 /*!< GIMA CTIN_4_IN: INV Position */ +#define GIMA_CTIN_4_IN_INV_Msk (0x01UL << GIMA_CTIN_4_IN_INV_Pos) /*!< GIMA CTIN_4_IN: INV Mask */ +#define GIMA_CTIN_4_IN_EDGE_Pos 1 /*!< GIMA CTIN_4_IN: EDGE Position */ +#define GIMA_CTIN_4_IN_EDGE_Msk (0x01UL << GIMA_CTIN_4_IN_EDGE_Pos) /*!< GIMA CTIN_4_IN: EDGE Mask */ +#define GIMA_CTIN_4_IN_SYNCH_Pos 2 /*!< GIMA CTIN_4_IN: SYNCH Position */ +#define GIMA_CTIN_4_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_4_IN_SYNCH_Pos) /*!< GIMA CTIN_4_IN: SYNCH Mask */ +#define GIMA_CTIN_4_IN_PULSE_Pos 3 /*!< GIMA CTIN_4_IN: PULSE Position */ +#define GIMA_CTIN_4_IN_PULSE_Msk (0x01UL << GIMA_CTIN_4_IN_PULSE_Pos) /*!< GIMA CTIN_4_IN: PULSE Mask */ +#define GIMA_CTIN_4_IN_SELECT_Pos 4 /*!< GIMA CTIN_4_IN: SELECT Position */ +#define GIMA_CTIN_4_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_4_IN_SELECT_Pos) /*!< GIMA CTIN_4_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CTIN_5_IN ------------------------------- */ +#define GIMA_CTIN_5_IN_INV_Pos 0 /*!< GIMA CTIN_5_IN: INV Position */ +#define GIMA_CTIN_5_IN_INV_Msk (0x01UL << GIMA_CTIN_5_IN_INV_Pos) /*!< GIMA CTIN_5_IN: INV Mask */ +#define GIMA_CTIN_5_IN_EDGE_Pos 1 /*!< GIMA CTIN_5_IN: EDGE Position */ +#define GIMA_CTIN_5_IN_EDGE_Msk (0x01UL << GIMA_CTIN_5_IN_EDGE_Pos) /*!< GIMA CTIN_5_IN: EDGE Mask */ +#define GIMA_CTIN_5_IN_SYNCH_Pos 2 /*!< GIMA CTIN_5_IN: SYNCH Position */ +#define GIMA_CTIN_5_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_5_IN_SYNCH_Pos) /*!< GIMA CTIN_5_IN: SYNCH Mask */ +#define GIMA_CTIN_5_IN_PULSE_Pos 3 /*!< GIMA CTIN_5_IN: PULSE Position */ +#define GIMA_CTIN_5_IN_PULSE_Msk (0x01UL << GIMA_CTIN_5_IN_PULSE_Pos) /*!< GIMA CTIN_5_IN: PULSE Mask */ +#define GIMA_CTIN_5_IN_SELECT_Pos 4 /*!< GIMA CTIN_5_IN: SELECT Position */ +#define GIMA_CTIN_5_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_5_IN_SELECT_Pos) /*!< GIMA CTIN_5_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CTIN_6_IN ------------------------------- */ +#define GIMA_CTIN_6_IN_INV_Pos 0 /*!< GIMA CTIN_6_IN: INV Position */ +#define GIMA_CTIN_6_IN_INV_Msk (0x01UL << GIMA_CTIN_6_IN_INV_Pos) /*!< GIMA CTIN_6_IN: INV Mask */ +#define GIMA_CTIN_6_IN_EDGE_Pos 1 /*!< GIMA CTIN_6_IN: EDGE Position */ +#define GIMA_CTIN_6_IN_EDGE_Msk (0x01UL << GIMA_CTIN_6_IN_EDGE_Pos) /*!< GIMA CTIN_6_IN: EDGE Mask */ +#define GIMA_CTIN_6_IN_SYNCH_Pos 2 /*!< GIMA CTIN_6_IN: SYNCH Position */ +#define GIMA_CTIN_6_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_6_IN_SYNCH_Pos) /*!< GIMA CTIN_6_IN: SYNCH Mask */ +#define GIMA_CTIN_6_IN_PULSE_Pos 3 /*!< GIMA CTIN_6_IN: PULSE Position */ +#define GIMA_CTIN_6_IN_PULSE_Msk (0x01UL << GIMA_CTIN_6_IN_PULSE_Pos) /*!< GIMA CTIN_6_IN: PULSE Mask */ +#define GIMA_CTIN_6_IN_SELECT_Pos 4 /*!< GIMA CTIN_6_IN: SELECT Position */ +#define GIMA_CTIN_6_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_6_IN_SELECT_Pos) /*!< GIMA CTIN_6_IN: SELECT Mask */ + +/* ------------------------------- GIMA_CTIN_7_IN ------------------------------- */ +#define GIMA_CTIN_7_IN_INV_Pos 0 /*!< GIMA CTIN_7_IN: INV Position */ +#define GIMA_CTIN_7_IN_INV_Msk (0x01UL << GIMA_CTIN_7_IN_INV_Pos) /*!< GIMA CTIN_7_IN: INV Mask */ +#define GIMA_CTIN_7_IN_EDGE_Pos 1 /*!< GIMA CTIN_7_IN: EDGE Position */ +#define GIMA_CTIN_7_IN_EDGE_Msk (0x01UL << GIMA_CTIN_7_IN_EDGE_Pos) /*!< GIMA CTIN_7_IN: EDGE Mask */ +#define GIMA_CTIN_7_IN_SYNCH_Pos 2 /*!< GIMA CTIN_7_IN: SYNCH Position */ +#define GIMA_CTIN_7_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_7_IN_SYNCH_Pos) /*!< GIMA CTIN_7_IN: SYNCH Mask */ +#define GIMA_CTIN_7_IN_PULSE_Pos 3 /*!< GIMA CTIN_7_IN: PULSE Position */ +#define GIMA_CTIN_7_IN_PULSE_Msk (0x01UL << GIMA_CTIN_7_IN_PULSE_Pos) /*!< GIMA CTIN_7_IN: PULSE Mask */ +#define GIMA_CTIN_7_IN_SELECT_Pos 4 /*!< GIMA CTIN_7_IN: SELECT Position */ +#define GIMA_CTIN_7_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_7_IN_SELECT_Pos) /*!< GIMA CTIN_7_IN: SELECT Mask */ + +/* ---------------------------- GIMA_ADCHS_TRIGGER_IN --------------------------- */ +#define GIMA_ADCHS_TRIGGER_IN_INV_Pos 0 /*!< GIMA ADCHS_TRIGGER_IN: INV Position */ +#define GIMA_ADCHS_TRIGGER_IN_INV_Msk (0x01UL << GIMA_ADCHS_TRIGGER_IN_INV_Pos) /*!< GIMA ADCHS_TRIGGER_IN: INV Mask */ +#define GIMA_ADCHS_TRIGGER_IN_EDGE_Pos 1 /*!< GIMA ADCHS_TRIGGER_IN: EDGE Position */ +#define GIMA_ADCHS_TRIGGER_IN_EDGE_Msk (0x01UL << GIMA_ADCHS_TRIGGER_IN_EDGE_Pos) /*!< GIMA ADCHS_TRIGGER_IN: EDGE Mask */ +#define GIMA_ADCHS_TRIGGER_IN_SYNCH_Pos 2 /*!< GIMA ADCHS_TRIGGER_IN: SYNCH Position */ +#define GIMA_ADCHS_TRIGGER_IN_SYNCH_Msk (0x01UL << GIMA_ADCHS_TRIGGER_IN_SYNCH_Pos) /*!< GIMA ADCHS_TRIGGER_IN: SYNCH Mask */ +#define GIMA_ADCHS_TRIGGER_IN_PULSE_Pos 3 /*!< GIMA ADCHS_TRIGGER_IN: PULSE Position */ +#define GIMA_ADCHS_TRIGGER_IN_PULSE_Msk (0x01UL << GIMA_ADCHS_TRIGGER_IN_PULSE_Pos) /*!< GIMA ADCHS_TRIGGER_IN: PULSE Mask */ +#define GIMA_ADCHS_TRIGGER_IN_SELECT_Pos 4 /*!< GIMA ADCHS_TRIGGER_IN: SELECT Position */ +#define GIMA_ADCHS_TRIGGER_IN_SELECT_Msk (0x0fUL << GIMA_ADCHS_TRIGGER_IN_SELECT_Pos) /*!< GIMA ADCHS_TRIGGER_IN: SELECT Mask */ + +/* --------------------------- GIMA_EVENTROUTER_13_IN --------------------------- */ +#define GIMA_EVENTROUTER_13_IN_INV_Pos 0 /*!< GIMA EVENTROUTER_13_IN: INV Position */ +#define GIMA_EVENTROUTER_13_IN_INV_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_INV_Pos) /*!< GIMA EVENTROUTER_13_IN: INV Mask */ +#define GIMA_EVENTROUTER_13_IN_EDGE_Pos 1 /*!< GIMA EVENTROUTER_13_IN: EDGE Position */ +#define GIMA_EVENTROUTER_13_IN_EDGE_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_EDGE_Pos) /*!< GIMA EVENTROUTER_13_IN: EDGE Mask */ +#define GIMA_EVENTROUTER_13_IN_SYNCH_Pos 2 /*!< GIMA EVENTROUTER_13_IN: SYNCH Position */ +#define GIMA_EVENTROUTER_13_IN_SYNCH_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_SYNCH_Pos) /*!< GIMA EVENTROUTER_13_IN: SYNCH Mask */ +#define GIMA_EVENTROUTER_13_IN_PULSE_Pos 3 /*!< GIMA EVENTROUTER_13_IN: PULSE Position */ +#define GIMA_EVENTROUTER_13_IN_PULSE_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_PULSE_Pos) /*!< GIMA EVENTROUTER_13_IN: PULSE Mask */ +#define GIMA_EVENTROUTER_13_IN_SELECT_Pos 4 /*!< GIMA EVENTROUTER_13_IN: SELECT Position */ +#define GIMA_EVENTROUTER_13_IN_SELECT_Msk (0x0fUL << GIMA_EVENTROUTER_13_IN_SELECT_Pos) /*!< GIMA EVENTROUTER_13_IN: SELECT Mask */ + +/* --------------------------- GIMA_EVENTROUTER_14_IN --------------------------- */ +#define GIMA_EVENTROUTER_14_IN_INV_Pos 0 /*!< GIMA EVENTROUTER_14_IN: INV Position */ +#define GIMA_EVENTROUTER_14_IN_INV_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_INV_Pos) /*!< GIMA EVENTROUTER_14_IN: INV Mask */ +#define GIMA_EVENTROUTER_14_IN_EDGE_Pos 1 /*!< GIMA EVENTROUTER_14_IN: EDGE Position */ +#define GIMA_EVENTROUTER_14_IN_EDGE_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_EDGE_Pos) /*!< GIMA EVENTROUTER_14_IN: EDGE Mask */ +#define GIMA_EVENTROUTER_14_IN_SYNCH_Pos 2 /*!< GIMA EVENTROUTER_14_IN: SYNCH Position */ +#define GIMA_EVENTROUTER_14_IN_SYNCH_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_SYNCH_Pos) /*!< GIMA EVENTROUTER_14_IN: SYNCH Mask */ +#define GIMA_EVENTROUTER_14_IN_PULSE_Pos 3 /*!< GIMA EVENTROUTER_14_IN: PULSE Position */ +#define GIMA_EVENTROUTER_14_IN_PULSE_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_PULSE_Pos) /*!< GIMA EVENTROUTER_14_IN: PULSE Mask */ +#define GIMA_EVENTROUTER_14_IN_SELECT_Pos 4 /*!< GIMA EVENTROUTER_14_IN: SELECT Position */ +#define GIMA_EVENTROUTER_14_IN_SELECT_Msk (0x0fUL << GIMA_EVENTROUTER_14_IN_SELECT_Pos) /*!< GIMA EVENTROUTER_14_IN: SELECT Mask */ + +/* --------------------------- GIMA_EVENTROUTER_16_IN --------------------------- */ +#define GIMA_EVENTROUTER_16_IN_INV_Pos 0 /*!< GIMA EVENTROUTER_16_IN: INV Position */ +#define GIMA_EVENTROUTER_16_IN_INV_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_INV_Pos) /*!< GIMA EVENTROUTER_16_IN: INV Mask */ +#define GIMA_EVENTROUTER_16_IN_EDGE_Pos 1 /*!< GIMA EVENTROUTER_16_IN: EDGE Position */ +#define GIMA_EVENTROUTER_16_IN_EDGE_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_EDGE_Pos) /*!< GIMA EVENTROUTER_16_IN: EDGE Mask */ +#define GIMA_EVENTROUTER_16_IN_SYNCH_Pos 2 /*!< GIMA EVENTROUTER_16_IN: SYNCH Position */ +#define GIMA_EVENTROUTER_16_IN_SYNCH_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_SYNCH_Pos) /*!< GIMA EVENTROUTER_16_IN: SYNCH Mask */ +#define GIMA_EVENTROUTER_16_IN_PULSE_Pos 3 /*!< GIMA EVENTROUTER_16_IN: PULSE Position */ +#define GIMA_EVENTROUTER_16_IN_PULSE_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_PULSE_Pos) /*!< GIMA EVENTROUTER_16_IN: PULSE Mask */ +#define GIMA_EVENTROUTER_16_IN_SELECT_Pos 4 /*!< GIMA EVENTROUTER_16_IN: SELECT Position */ +#define GIMA_EVENTROUTER_16_IN_SELECT_Msk (0x0fUL << GIMA_EVENTROUTER_16_IN_SELECT_Pos) /*!< GIMA EVENTROUTER_16_IN: SELECT Mask */ + +/* ------------------------------ GIMA_ADCSTART0_IN ----------------------------- */ +#define GIMA_ADCSTART0_IN_INV_Pos 0 /*!< GIMA ADCSTART0_IN: INV Position */ +#define GIMA_ADCSTART0_IN_INV_Msk (0x01UL << GIMA_ADCSTART0_IN_INV_Pos) /*!< GIMA ADCSTART0_IN: INV Mask */ +#define GIMA_ADCSTART0_IN_EDGE_Pos 1 /*!< GIMA ADCSTART0_IN: EDGE Position */ +#define GIMA_ADCSTART0_IN_EDGE_Msk (0x01UL << GIMA_ADCSTART0_IN_EDGE_Pos) /*!< GIMA ADCSTART0_IN: EDGE Mask */ +#define GIMA_ADCSTART0_IN_SYNCH_Pos 2 /*!< GIMA ADCSTART0_IN: SYNCH Position */ +#define GIMA_ADCSTART0_IN_SYNCH_Msk (0x01UL << GIMA_ADCSTART0_IN_SYNCH_Pos) /*!< GIMA ADCSTART0_IN: SYNCH Mask */ +#define GIMA_ADCSTART0_IN_PULSE_Pos 3 /*!< GIMA ADCSTART0_IN: PULSE Position */ +#define GIMA_ADCSTART0_IN_PULSE_Msk (0x01UL << GIMA_ADCSTART0_IN_PULSE_Pos) /*!< GIMA ADCSTART0_IN: PULSE Mask */ +#define GIMA_ADCSTART0_IN_SELECT_Pos 4 /*!< GIMA ADCSTART0_IN: SELECT Position */ +#define GIMA_ADCSTART0_IN_SELECT_Msk (0x0fUL << GIMA_ADCSTART0_IN_SELECT_Pos) /*!< GIMA ADCSTART0_IN: SELECT Mask */ + +/* ------------------------------ GIMA_ADCSTART1_IN ----------------------------- */ +#define GIMA_ADCSTART1_IN_INV_Pos 0 /*!< GIMA ADCSTART1_IN: INV Position */ +#define GIMA_ADCSTART1_IN_INV_Msk (0x01UL << GIMA_ADCSTART1_IN_INV_Pos) /*!< GIMA ADCSTART1_IN: INV Mask */ +#define GIMA_ADCSTART1_IN_EDGE_Pos 1 /*!< GIMA ADCSTART1_IN: EDGE Position */ +#define GIMA_ADCSTART1_IN_EDGE_Msk (0x01UL << GIMA_ADCSTART1_IN_EDGE_Pos) /*!< GIMA ADCSTART1_IN: EDGE Mask */ +#define GIMA_ADCSTART1_IN_SYNCH_Pos 2 /*!< GIMA ADCSTART1_IN: SYNCH Position */ +#define GIMA_ADCSTART1_IN_SYNCH_Msk (0x01UL << GIMA_ADCSTART1_IN_SYNCH_Pos) /*!< GIMA ADCSTART1_IN: SYNCH Mask */ +#define GIMA_ADCSTART1_IN_PULSE_Pos 3 /*!< GIMA ADCSTART1_IN: PULSE Position */ +#define GIMA_ADCSTART1_IN_PULSE_Msk (0x01UL << GIMA_ADCSTART1_IN_PULSE_Pos) /*!< GIMA ADCSTART1_IN: PULSE Mask */ +#define GIMA_ADCSTART1_IN_SELECT_Pos 4 /*!< GIMA ADCSTART1_IN: SELECT Position */ +#define GIMA_ADCSTART1_IN_SELECT_Msk (0x0fUL << GIMA_ADCSTART1_IN_SELECT_Pos) /*!< GIMA ADCSTART1_IN: SELECT Mask */ + + +/* ================================================================================ */ +/* ================ struct 'DAC' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------------- DAC_CR ----------------------------------- */ +#define DAC_CR_VALUE_Pos 6 /*!< DAC CR: VALUE Position */ +#define DAC_CR_VALUE_Msk (0x000003ffUL << DAC_CR_VALUE_Pos) /*!< DAC CR: VALUE Mask */ +#define DAC_CR_BIAS_Pos 16 /*!< DAC CR: BIAS Position */ +#define DAC_CR_BIAS_Msk (0x01UL << DAC_CR_BIAS_Pos) /*!< DAC CR: BIAS Mask */ + +/* ---------------------------------- DAC_CTRL ---------------------------------- */ +#define DAC_CTRL_INT_DMA_REQ_Pos 0 /*!< DAC CTRL: INT_DMA_REQ Position */ +#define DAC_CTRL_INT_DMA_REQ_Msk (0x01UL << DAC_CTRL_INT_DMA_REQ_Pos) /*!< DAC CTRL: INT_DMA_REQ Mask */ +#define DAC_CTRL_DBLBUF_ENA_Pos 1 /*!< DAC CTRL: DBLBUF_ENA Position */ +#define DAC_CTRL_DBLBUF_ENA_Msk (0x01UL << DAC_CTRL_DBLBUF_ENA_Pos) /*!< DAC CTRL: DBLBUF_ENA Mask */ +#define DAC_CTRL_CNT_ENA_Pos 2 /*!< DAC CTRL: CNT_ENA Position */ +#define DAC_CTRL_CNT_ENA_Msk (0x01UL << DAC_CTRL_CNT_ENA_Pos) /*!< DAC CTRL: CNT_ENA Mask */ +#define DAC_CTRL_DMA_ENA_Pos 3 /*!< DAC CTRL: DMA_ENA Position */ +#define DAC_CTRL_DMA_ENA_Msk (0x01UL << DAC_CTRL_DMA_ENA_Pos) /*!< DAC CTRL: DMA_ENA Mask */ + +/* --------------------------------- DAC_CNTVAL --------------------------------- */ +#define DAC_CNTVAL_VALUE_Pos 0 /*!< DAC CNTVAL: VALUE Position */ +#define DAC_CNTVAL_VALUE_Msk (0x0000ffffUL << DAC_CNTVAL_VALUE_Pos) /*!< DAC CNTVAL: VALUE Mask */ + + +/* ================================================================================ */ +/* ================ struct 'C_CAN0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- C_CAN0_CNTL -------------------------------- */ +#define C_CAN0_CNTL_INIT_Pos 0 /*!< C_CAN0 CNTL: INIT Position */ +#define C_CAN0_CNTL_INIT_Msk (0x01UL << C_CAN0_CNTL_INIT_Pos) /*!< C_CAN0 CNTL: INIT Mask */ +#define C_CAN0_CNTL_IE_Pos 1 /*!< C_CAN0 CNTL: IE Position */ +#define C_CAN0_CNTL_IE_Msk (0x01UL << C_CAN0_CNTL_IE_Pos) /*!< C_CAN0 CNTL: IE Mask */ +#define C_CAN0_CNTL_SIE_Pos 2 /*!< C_CAN0 CNTL: SIE Position */ +#define C_CAN0_CNTL_SIE_Msk (0x01UL << C_CAN0_CNTL_SIE_Pos) /*!< C_CAN0 CNTL: SIE Mask */ +#define C_CAN0_CNTL_EIE_Pos 3 /*!< C_CAN0 CNTL: EIE Position */ +#define C_CAN0_CNTL_EIE_Msk (0x01UL << C_CAN0_CNTL_EIE_Pos) /*!< C_CAN0 CNTL: EIE Mask */ +#define C_CAN0_CNTL_DAR_Pos 5 /*!< C_CAN0 CNTL: DAR Position */ +#define C_CAN0_CNTL_DAR_Msk (0x01UL << C_CAN0_CNTL_DAR_Pos) /*!< C_CAN0 CNTL: DAR Mask */ +#define C_CAN0_CNTL_CCE_Pos 6 /*!< C_CAN0 CNTL: CCE Position */ +#define C_CAN0_CNTL_CCE_Msk (0x01UL << C_CAN0_CNTL_CCE_Pos) /*!< C_CAN0 CNTL: CCE Mask */ +#define C_CAN0_CNTL_TEST_Pos 7 /*!< C_CAN0 CNTL: TEST Position */ +#define C_CAN0_CNTL_TEST_Msk (0x01UL << C_CAN0_CNTL_TEST_Pos) /*!< C_CAN0 CNTL: TEST Mask */ + +/* --------------------------------- C_CAN0_STAT -------------------------------- */ +#define C_CAN0_STAT_LEC_Pos 0 /*!< C_CAN0 STAT: LEC Position */ +#define C_CAN0_STAT_LEC_Msk (0x07UL << C_CAN0_STAT_LEC_Pos) /*!< C_CAN0 STAT: LEC Mask */ +#define C_CAN0_STAT_TXOK_Pos 3 /*!< C_CAN0 STAT: TXOK Position */ +#define C_CAN0_STAT_TXOK_Msk (0x01UL << C_CAN0_STAT_TXOK_Pos) /*!< C_CAN0 STAT: TXOK Mask */ +#define C_CAN0_STAT_RXOK_Pos 4 /*!< C_CAN0 STAT: RXOK Position */ +#define C_CAN0_STAT_RXOK_Msk (0x01UL << C_CAN0_STAT_RXOK_Pos) /*!< C_CAN0 STAT: RXOK Mask */ +#define C_CAN0_STAT_EPASS_Pos 5 /*!< C_CAN0 STAT: EPASS Position */ +#define C_CAN0_STAT_EPASS_Msk (0x01UL << C_CAN0_STAT_EPASS_Pos) /*!< C_CAN0 STAT: EPASS Mask */ +#define C_CAN0_STAT_EWARN_Pos 6 /*!< C_CAN0 STAT: EWARN Position */ +#define C_CAN0_STAT_EWARN_Msk (0x01UL << C_CAN0_STAT_EWARN_Pos) /*!< C_CAN0 STAT: EWARN Mask */ +#define C_CAN0_STAT_BOFF_Pos 7 /*!< C_CAN0 STAT: BOFF Position */ +#define C_CAN0_STAT_BOFF_Msk (0x01UL << C_CAN0_STAT_BOFF_Pos) /*!< C_CAN0 STAT: BOFF Mask */ + +/* ---------------------------------- C_CAN0_EC --------------------------------- */ +#define C_CAN0_EC_TEC_7_0_Pos 0 /*!< C_CAN0 EC: TEC_7_0 Position */ +#define C_CAN0_EC_TEC_7_0_Msk (0x000000ffUL << C_CAN0_EC_TEC_7_0_Pos) /*!< C_CAN0 EC: TEC_7_0 Mask */ +#define C_CAN0_EC_REC_6_0_Pos 8 /*!< C_CAN0 EC: REC_6_0 Position */ +#define C_CAN0_EC_REC_6_0_Msk (0x7fUL << C_CAN0_EC_REC_6_0_Pos) /*!< C_CAN0 EC: REC_6_0 Mask */ +#define C_CAN0_EC_RP_Pos 15 /*!< C_CAN0 EC: RP Position */ +#define C_CAN0_EC_RP_Msk (0x01UL << C_CAN0_EC_RP_Pos) /*!< C_CAN0 EC: RP Mask */ + +/* ---------------------------------- C_CAN0_BT --------------------------------- */ +#define C_CAN0_BT_BRP_Pos 0 /*!< C_CAN0 BT: BRP Position */ +#define C_CAN0_BT_BRP_Msk (0x3fUL << C_CAN0_BT_BRP_Pos) /*!< C_CAN0 BT: BRP Mask */ +#define C_CAN0_BT_SJW_Pos 6 /*!< C_CAN0 BT: SJW Position */ +#define C_CAN0_BT_SJW_Msk (0x03UL << C_CAN0_BT_SJW_Pos) /*!< C_CAN0 BT: SJW Mask */ +#define C_CAN0_BT_TSEG1_Pos 8 /*!< C_CAN0 BT: TSEG1 Position */ +#define C_CAN0_BT_TSEG1_Msk (0x0fUL << C_CAN0_BT_TSEG1_Pos) /*!< C_CAN0 BT: TSEG1 Mask */ +#define C_CAN0_BT_TSEG2_Pos 12 /*!< C_CAN0 BT: TSEG2 Position */ +#define C_CAN0_BT_TSEG2_Msk (0x07UL << C_CAN0_BT_TSEG2_Pos) /*!< C_CAN0 BT: TSEG2 Mask */ + +/* --------------------------------- C_CAN0_INT --------------------------------- */ +#define C_CAN0_INT_INTID15_0_Pos 0 /*!< C_CAN0 INT: INTID15_0 Position */ +#define C_CAN0_INT_INTID15_0_Msk (0x0000ffffUL << C_CAN0_INT_INTID15_0_Pos) /*!< C_CAN0 INT: INTID15_0 Mask */ + +/* --------------------------------- C_CAN0_TEST -------------------------------- */ +#define C_CAN0_TEST_BASIC_Pos 2 /*!< C_CAN0 TEST: BASIC Position */ +#define C_CAN0_TEST_BASIC_Msk (0x01UL << C_CAN0_TEST_BASIC_Pos) /*!< C_CAN0 TEST: BASIC Mask */ +#define C_CAN0_TEST_SILENT_Pos 3 /*!< C_CAN0 TEST: SILENT Position */ +#define C_CAN0_TEST_SILENT_Msk (0x01UL << C_CAN0_TEST_SILENT_Pos) /*!< C_CAN0 TEST: SILENT Mask */ +#define C_CAN0_TEST_LBACK_Pos 4 /*!< C_CAN0 TEST: LBACK Position */ +#define C_CAN0_TEST_LBACK_Msk (0x01UL << C_CAN0_TEST_LBACK_Pos) /*!< C_CAN0 TEST: LBACK Mask */ +#define C_CAN0_TEST_TX1_0_Pos 5 /*!< C_CAN0 TEST: TX1_0 Position */ +#define C_CAN0_TEST_TX1_0_Msk (0x03UL << C_CAN0_TEST_TX1_0_Pos) /*!< C_CAN0 TEST: TX1_0 Mask */ +#define C_CAN0_TEST_RX_Pos 7 /*!< C_CAN0 TEST: RX Position */ +#define C_CAN0_TEST_RX_Msk (0x01UL << C_CAN0_TEST_RX_Pos) /*!< C_CAN0 TEST: RX Mask */ + +/* --------------------------------- C_CAN0_BRPE -------------------------------- */ +#define C_CAN0_BRPE_BRPE_Pos 0 /*!< C_CAN0 BRPE: BRPE Position */ +#define C_CAN0_BRPE_BRPE_Msk (0x0fUL << C_CAN0_BRPE_BRPE_Pos) /*!< C_CAN0 BRPE: BRPE Mask */ + +/* ------------------------------ C_CAN0_IF1_CMDREQ ----------------------------- */ +#define C_CAN0_IF1_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN0 IF1_CMDREQ: MESSNUM Position */ +#define C_CAN0_IF1_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN0_IF1_CMDREQ_MESSNUM_Pos) /*!< C_CAN0 IF1_CMDREQ: MESSNUM Mask */ +#define C_CAN0_IF1_CMDREQ_BUSY_Pos 15 /*!< C_CAN0 IF1_CMDREQ: BUSY Position */ +#define C_CAN0_IF1_CMDREQ_BUSY_Msk (0x01UL << C_CAN0_IF1_CMDREQ_BUSY_Pos) /*!< C_CAN0 IF1_CMDREQ: BUSY Mask */ + +/* ----------------------------- C_CAN0_IF1_CMDMSK_R ---------------------------- */ +#define C_CAN0_IF1_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN0 IF1_CMDMSK_R: DATA_B Position */ +#define C_CAN0_IF1_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_B_Pos) /*!< C_CAN0 IF1_CMDMSK_R: DATA_B Mask */ +#define C_CAN0_IF1_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN0 IF1_CMDMSK_R: DATA_A Position */ +#define C_CAN0_IF1_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_A_Pos) /*!< C_CAN0 IF1_CMDMSK_R: DATA_A Mask */ +#define C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN0 IF1_CMDMSK_R: NEWDAT Position */ +#define C_CAN0_IF1_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN0 IF1_CMDMSK_R: NEWDAT Mask */ +#define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN0 IF1_CMDMSK_R: CLRINTPND Position */ +#define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN0 IF1_CMDMSK_R: CLRINTPND Mask */ +#define C_CAN0_IF1_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN0 IF1_CMDMSK_R: CTRL Position */ +#define C_CAN0_IF1_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_CTRL_Pos) /*!< C_CAN0 IF1_CMDMSK_R: CTRL Mask */ +#define C_CAN0_IF1_CMDMSK_R_ARB_Pos 5 /*!< C_CAN0 IF1_CMDMSK_R: ARB Position */ +#define C_CAN0_IF1_CMDMSK_R_ARB_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_ARB_Pos) /*!< C_CAN0 IF1_CMDMSK_R: ARB Mask */ +#define C_CAN0_IF1_CMDMSK_R_MASK_Pos 6 /*!< C_CAN0 IF1_CMDMSK_R: MASK Position */ +#define C_CAN0_IF1_CMDMSK_R_MASK_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_MASK_Pos) /*!< C_CAN0 IF1_CMDMSK_R: MASK Mask */ +#define C_CAN0_IF1_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN0 IF1_CMDMSK_R: WR_RD Position */ +#define C_CAN0_IF1_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_WR_RD_Pos) /*!< C_CAN0 IF1_CMDMSK_R: WR_RD Mask */ + +/* ----------------------------- C_CAN0_IF1_CMDMSK_W ---------------------------- */ +#define C_CAN0_IF1_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN0 IF1_CMDMSK_W: DATA_B Position */ +#define C_CAN0_IF1_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_B_Pos) /*!< C_CAN0 IF1_CMDMSK_W: DATA_B Mask */ +#define C_CAN0_IF1_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN0 IF1_CMDMSK_W: DATA_A Position */ +#define C_CAN0_IF1_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_A_Pos) /*!< C_CAN0 IF1_CMDMSK_W: DATA_A Mask */ +#define C_CAN0_IF1_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN0 IF1_CMDMSK_W: TXRQST Position */ +#define C_CAN0_IF1_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_TXRQST_Pos) /*!< C_CAN0 IF1_CMDMSK_W: TXRQST Mask */ +#define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN0 IF1_CMDMSK_W: CLRINTPND Position */ +#define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN0 IF1_CMDMSK_W: CLRINTPND Mask */ +#define C_CAN0_IF1_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN0 IF1_CMDMSK_W: CTRL Position */ +#define C_CAN0_IF1_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_CTRL_Pos) /*!< C_CAN0 IF1_CMDMSK_W: CTRL Mask */ +#define C_CAN0_IF1_CMDMSK_W_ARB_Pos 5 /*!< C_CAN0 IF1_CMDMSK_W: ARB Position */ +#define C_CAN0_IF1_CMDMSK_W_ARB_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_ARB_Pos) /*!< C_CAN0 IF1_CMDMSK_W: ARB Mask */ +#define C_CAN0_IF1_CMDMSK_W_MASK_Pos 6 /*!< C_CAN0 IF1_CMDMSK_W: MASK Position */ +#define C_CAN0_IF1_CMDMSK_W_MASK_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_MASK_Pos) /*!< C_CAN0 IF1_CMDMSK_W: MASK Mask */ +#define C_CAN0_IF1_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN0 IF1_CMDMSK_W: WR_RD Position */ +#define C_CAN0_IF1_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_WR_RD_Pos) /*!< C_CAN0 IF1_CMDMSK_W: WR_RD Mask */ + +/* ------------------------------- C_CAN0_IF1_MSK1 ------------------------------ */ +#define C_CAN0_IF1_MSK1_MSK15_0_Pos 0 /*!< C_CAN0 IF1_MSK1: MSK15_0 Position */ +#define C_CAN0_IF1_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN0_IF1_MSK1_MSK15_0_Pos) /*!< C_CAN0 IF1_MSK1: MSK15_0 Mask */ + +/* ------------------------------- C_CAN0_IF1_MSK2 ------------------------------ */ +#define C_CAN0_IF1_MSK2_MSK28_16_Pos 0 /*!< C_CAN0 IF1_MSK2: MSK28_16 Position */ +#define C_CAN0_IF1_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN0_IF1_MSK2_MSK28_16_Pos) /*!< C_CAN0 IF1_MSK2: MSK28_16 Mask */ +#define C_CAN0_IF1_MSK2_MDIR_Pos 14 /*!< C_CAN0 IF1_MSK2: MDIR Position */ +#define C_CAN0_IF1_MSK2_MDIR_Msk (0x01UL << C_CAN0_IF1_MSK2_MDIR_Pos) /*!< C_CAN0 IF1_MSK2: MDIR Mask */ +#define C_CAN0_IF1_MSK2_MXTD_Pos 15 /*!< C_CAN0 IF1_MSK2: MXTD Position */ +#define C_CAN0_IF1_MSK2_MXTD_Msk (0x01UL << C_CAN0_IF1_MSK2_MXTD_Pos) /*!< C_CAN0 IF1_MSK2: MXTD Mask */ + +/* ------------------------------- C_CAN0_IF1_ARB1 ------------------------------ */ +#define C_CAN0_IF1_ARB1_ID15_0_Pos 0 /*!< C_CAN0 IF1_ARB1: ID15_0 Position */ +#define C_CAN0_IF1_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN0_IF1_ARB1_ID15_0_Pos) /*!< C_CAN0 IF1_ARB1: ID15_0 Mask */ + +/* ------------------------------- C_CAN0_IF1_ARB2 ------------------------------ */ +#define C_CAN0_IF1_ARB2_ID28_16_Pos 0 /*!< C_CAN0 IF1_ARB2: ID28_16 Position */ +#define C_CAN0_IF1_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN0_IF1_ARB2_ID28_16_Pos) /*!< C_CAN0 IF1_ARB2: ID28_16 Mask */ +#define C_CAN0_IF1_ARB2_DIR_Pos 13 /*!< C_CAN0 IF1_ARB2: DIR Position */ +#define C_CAN0_IF1_ARB2_DIR_Msk (0x01UL << C_CAN0_IF1_ARB2_DIR_Pos) /*!< C_CAN0 IF1_ARB2: DIR Mask */ +#define C_CAN0_IF1_ARB2_XTD_Pos 14 /*!< C_CAN0 IF1_ARB2: XTD Position */ +#define C_CAN0_IF1_ARB2_XTD_Msk (0x01UL << C_CAN0_IF1_ARB2_XTD_Pos) /*!< C_CAN0 IF1_ARB2: XTD Mask */ +#define C_CAN0_IF1_ARB2_MSGVAL_Pos 15 /*!< C_CAN0 IF1_ARB2: MSGVAL Position */ +#define C_CAN0_IF1_ARB2_MSGVAL_Msk (0x01UL << C_CAN0_IF1_ARB2_MSGVAL_Pos) /*!< C_CAN0 IF1_ARB2: MSGVAL Mask */ + +/* ------------------------------ C_CAN0_IF1_MCTRL ------------------------------ */ +#define C_CAN0_IF1_MCTRL_DLC3_0_Pos 0 /*!< C_CAN0 IF1_MCTRL: DLC3_0 Position */ +#define C_CAN0_IF1_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN0_IF1_MCTRL_DLC3_0_Pos) /*!< C_CAN0 IF1_MCTRL: DLC3_0 Mask */ +#define C_CAN0_IF1_MCTRL_EOB_Pos 7 /*!< C_CAN0 IF1_MCTRL: EOB Position */ +#define C_CAN0_IF1_MCTRL_EOB_Msk (0x01UL << C_CAN0_IF1_MCTRL_EOB_Pos) /*!< C_CAN0 IF1_MCTRL: EOB Mask */ +#define C_CAN0_IF1_MCTRL_TXRQST_Pos 8 /*!< C_CAN0 IF1_MCTRL: TXRQST Position */ +#define C_CAN0_IF1_MCTRL_TXRQST_Msk (0x01UL << C_CAN0_IF1_MCTRL_TXRQST_Pos) /*!< C_CAN0 IF1_MCTRL: TXRQST Mask */ +#define C_CAN0_IF1_MCTRL_RMTEN_Pos 9 /*!< C_CAN0 IF1_MCTRL: RMTEN Position */ +#define C_CAN0_IF1_MCTRL_RMTEN_Msk (0x01UL << C_CAN0_IF1_MCTRL_RMTEN_Pos) /*!< C_CAN0 IF1_MCTRL: RMTEN Mask */ +#define C_CAN0_IF1_MCTRL_RXIE_Pos 10 /*!< C_CAN0 IF1_MCTRL: RXIE Position */ +#define C_CAN0_IF1_MCTRL_RXIE_Msk (0x01UL << C_CAN0_IF1_MCTRL_RXIE_Pos) /*!< C_CAN0 IF1_MCTRL: RXIE Mask */ +#define C_CAN0_IF1_MCTRL_TXIE_Pos 11 /*!< C_CAN0 IF1_MCTRL: TXIE Position */ +#define C_CAN0_IF1_MCTRL_TXIE_Msk (0x01UL << C_CAN0_IF1_MCTRL_TXIE_Pos) /*!< C_CAN0 IF1_MCTRL: TXIE Mask */ +#define C_CAN0_IF1_MCTRL_UMASK_Pos 12 /*!< C_CAN0 IF1_MCTRL: UMASK Position */ +#define C_CAN0_IF1_MCTRL_UMASK_Msk (0x01UL << C_CAN0_IF1_MCTRL_UMASK_Pos) /*!< C_CAN0 IF1_MCTRL: UMASK Mask */ +#define C_CAN0_IF1_MCTRL_INTPND_Pos 13 /*!< C_CAN0 IF1_MCTRL: INTPND Position */ +#define C_CAN0_IF1_MCTRL_INTPND_Msk (0x01UL << C_CAN0_IF1_MCTRL_INTPND_Pos) /*!< C_CAN0 IF1_MCTRL: INTPND Mask */ +#define C_CAN0_IF1_MCTRL_MSGLST_Pos 14 /*!< C_CAN0 IF1_MCTRL: MSGLST Position */ +#define C_CAN0_IF1_MCTRL_MSGLST_Msk (0x01UL << C_CAN0_IF1_MCTRL_MSGLST_Pos) /*!< C_CAN0 IF1_MCTRL: MSGLST Mask */ +#define C_CAN0_IF1_MCTRL_NEWDAT_Pos 15 /*!< C_CAN0 IF1_MCTRL: NEWDAT Position */ +#define C_CAN0_IF1_MCTRL_NEWDAT_Msk (0x01UL << C_CAN0_IF1_MCTRL_NEWDAT_Pos) /*!< C_CAN0 IF1_MCTRL: NEWDAT Mask */ + +/* ------------------------------- C_CAN0_IF1_DA1 ------------------------------- */ +#define C_CAN0_IF1_DA1_DATA0_Pos 0 /*!< C_CAN0 IF1_DA1: DATA0 Position */ +#define C_CAN0_IF1_DA1_DATA0_Msk (0x000000ffUL << C_CAN0_IF1_DA1_DATA0_Pos) /*!< C_CAN0 IF1_DA1: DATA0 Mask */ +#define C_CAN0_IF1_DA1_DATA1_Pos 8 /*!< C_CAN0 IF1_DA1: DATA1 Position */ +#define C_CAN0_IF1_DA1_DATA1_Msk (0x000000ffUL << C_CAN0_IF1_DA1_DATA1_Pos) /*!< C_CAN0 IF1_DA1: DATA1 Mask */ + +/* ------------------------------- C_CAN0_IF1_DA2 ------------------------------- */ +#define C_CAN0_IF1_DA2_DATA2_Pos 0 /*!< C_CAN0 IF1_DA2: DATA2 Position */ +#define C_CAN0_IF1_DA2_DATA2_Msk (0x000000ffUL << C_CAN0_IF1_DA2_DATA2_Pos) /*!< C_CAN0 IF1_DA2: DATA2 Mask */ +#define C_CAN0_IF1_DA2_DATA3_Pos 8 /*!< C_CAN0 IF1_DA2: DATA3 Position */ +#define C_CAN0_IF1_DA2_DATA3_Msk (0x000000ffUL << C_CAN0_IF1_DA2_DATA3_Pos) /*!< C_CAN0 IF1_DA2: DATA3 Mask */ + +/* ------------------------------- C_CAN0_IF1_DB1 ------------------------------- */ +#define C_CAN0_IF1_DB1_DATA4_Pos 0 /*!< C_CAN0 IF1_DB1: DATA4 Position */ +#define C_CAN0_IF1_DB1_DATA4_Msk (0x000000ffUL << C_CAN0_IF1_DB1_DATA4_Pos) /*!< C_CAN0 IF1_DB1: DATA4 Mask */ +#define C_CAN0_IF1_DB1_DATA5_Pos 8 /*!< C_CAN0 IF1_DB1: DATA5 Position */ +#define C_CAN0_IF1_DB1_DATA5_Msk (0x000000ffUL << C_CAN0_IF1_DB1_DATA5_Pos) /*!< C_CAN0 IF1_DB1: DATA5 Mask */ + +/* ------------------------------- C_CAN0_IF1_DB2 ------------------------------- */ +#define C_CAN0_IF1_DB2_DATA6_Pos 0 /*!< C_CAN0 IF1_DB2: DATA6 Position */ +#define C_CAN0_IF1_DB2_DATA6_Msk (0x000000ffUL << C_CAN0_IF1_DB2_DATA6_Pos) /*!< C_CAN0 IF1_DB2: DATA6 Mask */ +#define C_CAN0_IF1_DB2_DATA7_Pos 8 /*!< C_CAN0 IF1_DB2: DATA7 Position */ +#define C_CAN0_IF1_DB2_DATA7_Msk (0x000000ffUL << C_CAN0_IF1_DB2_DATA7_Pos) /*!< C_CAN0 IF1_DB2: DATA7 Mask */ + +/* ------------------------------ C_CAN0_IF2_CMDREQ ----------------------------- */ +#define C_CAN0_IF2_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN0 IF2_CMDREQ: MESSNUM Position */ +#define C_CAN0_IF2_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN0_IF2_CMDREQ_MESSNUM_Pos) /*!< C_CAN0 IF2_CMDREQ: MESSNUM Mask */ +#define C_CAN0_IF2_CMDREQ_BUSY_Pos 15 /*!< C_CAN0 IF2_CMDREQ: BUSY Position */ +#define C_CAN0_IF2_CMDREQ_BUSY_Msk (0x01UL << C_CAN0_IF2_CMDREQ_BUSY_Pos) /*!< C_CAN0 IF2_CMDREQ: BUSY Mask */ + +/* ----------------------------- C_CAN0_IF2_CMDMSK_R ---------------------------- */ +#define C_CAN0_IF2_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN0 IF2_CMDMSK_R: DATA_B Position */ +#define C_CAN0_IF2_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_B_Pos) /*!< C_CAN0 IF2_CMDMSK_R: DATA_B Mask */ +#define C_CAN0_IF2_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN0 IF2_CMDMSK_R: DATA_A Position */ +#define C_CAN0_IF2_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_A_Pos) /*!< C_CAN0 IF2_CMDMSK_R: DATA_A Mask */ +#define C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN0 IF2_CMDMSK_R: NEWDAT Position */ +#define C_CAN0_IF2_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN0 IF2_CMDMSK_R: NEWDAT Mask */ +#define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN0 IF2_CMDMSK_R: CLRINTPND Position */ +#define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN0 IF2_CMDMSK_R: CLRINTPND Mask */ +#define C_CAN0_IF2_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN0 IF2_CMDMSK_R: CTRL Position */ +#define C_CAN0_IF2_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_CTRL_Pos) /*!< C_CAN0 IF2_CMDMSK_R: CTRL Mask */ +#define C_CAN0_IF2_CMDMSK_R_ARB_Pos 5 /*!< C_CAN0 IF2_CMDMSK_R: ARB Position */ +#define C_CAN0_IF2_CMDMSK_R_ARB_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_ARB_Pos) /*!< C_CAN0 IF2_CMDMSK_R: ARB Mask */ +#define C_CAN0_IF2_CMDMSK_R_MASK_Pos 6 /*!< C_CAN0 IF2_CMDMSK_R: MASK Position */ +#define C_CAN0_IF2_CMDMSK_R_MASK_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_MASK_Pos) /*!< C_CAN0 IF2_CMDMSK_R: MASK Mask */ +#define C_CAN0_IF2_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN0 IF2_CMDMSK_R: WR_RD Position */ +#define C_CAN0_IF2_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_WR_RD_Pos) /*!< C_CAN0 IF2_CMDMSK_R: WR_RD Mask */ + +/* ----------------------------- C_CAN0_IF2_CMDMSK_W ---------------------------- */ +#define C_CAN0_IF2_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN0 IF2_CMDMSK_W: DATA_B Position */ +#define C_CAN0_IF2_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_B_Pos) /*!< C_CAN0 IF2_CMDMSK_W: DATA_B Mask */ +#define C_CAN0_IF2_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN0 IF2_CMDMSK_W: DATA_A Position */ +#define C_CAN0_IF2_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_A_Pos) /*!< C_CAN0 IF2_CMDMSK_W: DATA_A Mask */ +#define C_CAN0_IF2_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN0 IF2_CMDMSK_W: TXRQST Position */ +#define C_CAN0_IF2_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_TXRQST_Pos) /*!< C_CAN0 IF2_CMDMSK_W: TXRQST Mask */ +#define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN0 IF2_CMDMSK_W: CLRINTPND Position */ +#define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN0 IF2_CMDMSK_W: CLRINTPND Mask */ +#define C_CAN0_IF2_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN0 IF2_CMDMSK_W: CTRL Position */ +#define C_CAN0_IF2_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_CTRL_Pos) /*!< C_CAN0 IF2_CMDMSK_W: CTRL Mask */ +#define C_CAN0_IF2_CMDMSK_W_ARB_Pos 5 /*!< C_CAN0 IF2_CMDMSK_W: ARB Position */ +#define C_CAN0_IF2_CMDMSK_W_ARB_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_ARB_Pos) /*!< C_CAN0 IF2_CMDMSK_W: ARB Mask */ +#define C_CAN0_IF2_CMDMSK_W_MASK_Pos 6 /*!< C_CAN0 IF2_CMDMSK_W: MASK Position */ +#define C_CAN0_IF2_CMDMSK_W_MASK_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_MASK_Pos) /*!< C_CAN0 IF2_CMDMSK_W: MASK Mask */ +#define C_CAN0_IF2_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN0 IF2_CMDMSK_W: WR_RD Position */ +#define C_CAN0_IF2_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_WR_RD_Pos) /*!< C_CAN0 IF2_CMDMSK_W: WR_RD Mask */ + +/* ------------------------------- C_CAN0_IF2_MSK1 ------------------------------ */ +#define C_CAN0_IF2_MSK1_MSK15_0_Pos 0 /*!< C_CAN0 IF2_MSK1: MSK15_0 Position */ +#define C_CAN0_IF2_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN0_IF2_MSK1_MSK15_0_Pos) /*!< C_CAN0 IF2_MSK1: MSK15_0 Mask */ + +/* ------------------------------- C_CAN0_IF2_MSK2 ------------------------------ */ +#define C_CAN0_IF2_MSK2_MSK28_16_Pos 0 /*!< C_CAN0 IF2_MSK2: MSK28_16 Position */ +#define C_CAN0_IF2_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN0_IF2_MSK2_MSK28_16_Pos) /*!< C_CAN0 IF2_MSK2: MSK28_16 Mask */ +#define C_CAN0_IF2_MSK2_MDIR_Pos 14 /*!< C_CAN0 IF2_MSK2: MDIR Position */ +#define C_CAN0_IF2_MSK2_MDIR_Msk (0x01UL << C_CAN0_IF2_MSK2_MDIR_Pos) /*!< C_CAN0 IF2_MSK2: MDIR Mask */ +#define C_CAN0_IF2_MSK2_MXTD_Pos 15 /*!< C_CAN0 IF2_MSK2: MXTD Position */ +#define C_CAN0_IF2_MSK2_MXTD_Msk (0x01UL << C_CAN0_IF2_MSK2_MXTD_Pos) /*!< C_CAN0 IF2_MSK2: MXTD Mask */ + +/* ------------------------------- C_CAN0_IF2_ARB1 ------------------------------ */ +#define C_CAN0_IF2_ARB1_ID15_0_Pos 0 /*!< C_CAN0 IF2_ARB1: ID15_0 Position */ +#define C_CAN0_IF2_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN0_IF2_ARB1_ID15_0_Pos) /*!< C_CAN0 IF2_ARB1: ID15_0 Mask */ + +/* ------------------------------- C_CAN0_IF2_ARB2 ------------------------------ */ +#define C_CAN0_IF2_ARB2_ID28_16_Pos 0 /*!< C_CAN0 IF2_ARB2: ID28_16 Position */ +#define C_CAN0_IF2_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN0_IF2_ARB2_ID28_16_Pos) /*!< C_CAN0 IF2_ARB2: ID28_16 Mask */ +#define C_CAN0_IF2_ARB2_DIR_Pos 13 /*!< C_CAN0 IF2_ARB2: DIR Position */ +#define C_CAN0_IF2_ARB2_DIR_Msk (0x01UL << C_CAN0_IF2_ARB2_DIR_Pos) /*!< C_CAN0 IF2_ARB2: DIR Mask */ +#define C_CAN0_IF2_ARB2_XTD_Pos 14 /*!< C_CAN0 IF2_ARB2: XTD Position */ +#define C_CAN0_IF2_ARB2_XTD_Msk (0x01UL << C_CAN0_IF2_ARB2_XTD_Pos) /*!< C_CAN0 IF2_ARB2: XTD Mask */ +#define C_CAN0_IF2_ARB2_MSGVAL_Pos 15 /*!< C_CAN0 IF2_ARB2: MSGVAL Position */ +#define C_CAN0_IF2_ARB2_MSGVAL_Msk (0x01UL << C_CAN0_IF2_ARB2_MSGVAL_Pos) /*!< C_CAN0 IF2_ARB2: MSGVAL Mask */ + +/* ------------------------------ C_CAN0_IF2_MCTRL ------------------------------ */ +#define C_CAN0_IF2_MCTRL_DLC3_0_Pos 0 /*!< C_CAN0 IF2_MCTRL: DLC3_0 Position */ +#define C_CAN0_IF2_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN0_IF2_MCTRL_DLC3_0_Pos) /*!< C_CAN0 IF2_MCTRL: DLC3_0 Mask */ +#define C_CAN0_IF2_MCTRL_EOB_Pos 7 /*!< C_CAN0 IF2_MCTRL: EOB Position */ +#define C_CAN0_IF2_MCTRL_EOB_Msk (0x01UL << C_CAN0_IF2_MCTRL_EOB_Pos) /*!< C_CAN0 IF2_MCTRL: EOB Mask */ +#define C_CAN0_IF2_MCTRL_TXRQST_Pos 8 /*!< C_CAN0 IF2_MCTRL: TXRQST Position */ +#define C_CAN0_IF2_MCTRL_TXRQST_Msk (0x01UL << C_CAN0_IF2_MCTRL_TXRQST_Pos) /*!< C_CAN0 IF2_MCTRL: TXRQST Mask */ +#define C_CAN0_IF2_MCTRL_RMTEN_Pos 9 /*!< C_CAN0 IF2_MCTRL: RMTEN Position */ +#define C_CAN0_IF2_MCTRL_RMTEN_Msk (0x01UL << C_CAN0_IF2_MCTRL_RMTEN_Pos) /*!< C_CAN0 IF2_MCTRL: RMTEN Mask */ +#define C_CAN0_IF2_MCTRL_RXIE_Pos 10 /*!< C_CAN0 IF2_MCTRL: RXIE Position */ +#define C_CAN0_IF2_MCTRL_RXIE_Msk (0x01UL << C_CAN0_IF2_MCTRL_RXIE_Pos) /*!< C_CAN0 IF2_MCTRL: RXIE Mask */ +#define C_CAN0_IF2_MCTRL_TXIE_Pos 11 /*!< C_CAN0 IF2_MCTRL: TXIE Position */ +#define C_CAN0_IF2_MCTRL_TXIE_Msk (0x01UL << C_CAN0_IF2_MCTRL_TXIE_Pos) /*!< C_CAN0 IF2_MCTRL: TXIE Mask */ +#define C_CAN0_IF2_MCTRL_UMASK_Pos 12 /*!< C_CAN0 IF2_MCTRL: UMASK Position */ +#define C_CAN0_IF2_MCTRL_UMASK_Msk (0x01UL << C_CAN0_IF2_MCTRL_UMASK_Pos) /*!< C_CAN0 IF2_MCTRL: UMASK Mask */ +#define C_CAN0_IF2_MCTRL_INTPND_Pos 13 /*!< C_CAN0 IF2_MCTRL: INTPND Position */ +#define C_CAN0_IF2_MCTRL_INTPND_Msk (0x01UL << C_CAN0_IF2_MCTRL_INTPND_Pos) /*!< C_CAN0 IF2_MCTRL: INTPND Mask */ +#define C_CAN0_IF2_MCTRL_MSGLST_Pos 14 /*!< C_CAN0 IF2_MCTRL: MSGLST Position */ +#define C_CAN0_IF2_MCTRL_MSGLST_Msk (0x01UL << C_CAN0_IF2_MCTRL_MSGLST_Pos) /*!< C_CAN0 IF2_MCTRL: MSGLST Mask */ +#define C_CAN0_IF2_MCTRL_NEWDAT_Pos 15 /*!< C_CAN0 IF2_MCTRL: NEWDAT Position */ +#define C_CAN0_IF2_MCTRL_NEWDAT_Msk (0x01UL << C_CAN0_IF2_MCTRL_NEWDAT_Pos) /*!< C_CAN0 IF2_MCTRL: NEWDAT Mask */ + +/* ------------------------------- C_CAN0_IF2_DA1 ------------------------------- */ +#define C_CAN0_IF2_DA1_DATA0_Pos 0 /*!< C_CAN0 IF2_DA1: DATA0 Position */ +#define C_CAN0_IF2_DA1_DATA0_Msk (0x000000ffUL << C_CAN0_IF2_DA1_DATA0_Pos) /*!< C_CAN0 IF2_DA1: DATA0 Mask */ +#define C_CAN0_IF2_DA1_DATA1_Pos 8 /*!< C_CAN0 IF2_DA1: DATA1 Position */ +#define C_CAN0_IF2_DA1_DATA1_Msk (0x000000ffUL << C_CAN0_IF2_DA1_DATA1_Pos) /*!< C_CAN0 IF2_DA1: DATA1 Mask */ + +/* ------------------------------- C_CAN0_IF2_DA2 ------------------------------- */ +#define C_CAN0_IF2_DA2_DATA2_Pos 0 /*!< C_CAN0 IF2_DA2: DATA2 Position */ +#define C_CAN0_IF2_DA2_DATA2_Msk (0x000000ffUL << C_CAN0_IF2_DA2_DATA2_Pos) /*!< C_CAN0 IF2_DA2: DATA2 Mask */ +#define C_CAN0_IF2_DA2_DATA3_Pos 8 /*!< C_CAN0 IF2_DA2: DATA3 Position */ +#define C_CAN0_IF2_DA2_DATA3_Msk (0x000000ffUL << C_CAN0_IF2_DA2_DATA3_Pos) /*!< C_CAN0 IF2_DA2: DATA3 Mask */ + +/* ------------------------------- C_CAN0_IF2_DB1 ------------------------------- */ +#define C_CAN0_IF2_DB1_DATA4_Pos 0 /*!< C_CAN0 IF2_DB1: DATA4 Position */ +#define C_CAN0_IF2_DB1_DATA4_Msk (0x000000ffUL << C_CAN0_IF2_DB1_DATA4_Pos) /*!< C_CAN0 IF2_DB1: DATA4 Mask */ +#define C_CAN0_IF2_DB1_DATA5_Pos 8 /*!< C_CAN0 IF2_DB1: DATA5 Position */ +#define C_CAN0_IF2_DB1_DATA5_Msk (0x000000ffUL << C_CAN0_IF2_DB1_DATA5_Pos) /*!< C_CAN0 IF2_DB1: DATA5 Mask */ + +/* ------------------------------- C_CAN0_IF2_DB2 ------------------------------- */ +#define C_CAN0_IF2_DB2_DATA6_Pos 0 /*!< C_CAN0 IF2_DB2: DATA6 Position */ +#define C_CAN0_IF2_DB2_DATA6_Msk (0x000000ffUL << C_CAN0_IF2_DB2_DATA6_Pos) /*!< C_CAN0 IF2_DB2: DATA6 Mask */ +#define C_CAN0_IF2_DB2_DATA7_Pos 8 /*!< C_CAN0 IF2_DB2: DATA7 Position */ +#define C_CAN0_IF2_DB2_DATA7_Msk (0x000000ffUL << C_CAN0_IF2_DB2_DATA7_Pos) /*!< C_CAN0 IF2_DB2: DATA7 Mask */ + +/* -------------------------------- C_CAN0_TXREQ1 ------------------------------- */ +#define C_CAN0_TXREQ1_TXRQST16_1_Pos 0 /*!< C_CAN0 TXREQ1: TXRQST16_1 Position */ +#define C_CAN0_TXREQ1_TXRQST16_1_Msk (0x0000ffffUL << C_CAN0_TXREQ1_TXRQST16_1_Pos) /*!< C_CAN0 TXREQ1: TXRQST16_1 Mask */ + +/* -------------------------------- C_CAN0_TXREQ2 ------------------------------- */ +#define C_CAN0_TXREQ2_TXRQST32_17_Pos 0 /*!< C_CAN0 TXREQ2: TXRQST32_17 Position */ +#define C_CAN0_TXREQ2_TXRQST32_17_Msk (0x0000ffffUL << C_CAN0_TXREQ2_TXRQST32_17_Pos) /*!< C_CAN0 TXREQ2: TXRQST32_17 Mask */ + +/* --------------------------------- C_CAN0_ND1 --------------------------------- */ +#define C_CAN0_ND1_NEWDAT16_1_Pos 0 /*!< C_CAN0 ND1: NEWDAT16_1 Position */ +#define C_CAN0_ND1_NEWDAT16_1_Msk (0x0000ffffUL << C_CAN0_ND1_NEWDAT16_1_Pos) /*!< C_CAN0 ND1: NEWDAT16_1 Mask */ + +/* --------------------------------- C_CAN0_ND2 --------------------------------- */ +#define C_CAN0_ND2_NEWDAT32_17_Pos 0 /*!< C_CAN0 ND2: NEWDAT32_17 Position */ +#define C_CAN0_ND2_NEWDAT32_17_Msk (0x0000ffffUL << C_CAN0_ND2_NEWDAT32_17_Pos) /*!< C_CAN0 ND2: NEWDAT32_17 Mask */ + +/* --------------------------------- C_CAN0_IR1 --------------------------------- */ +#define C_CAN0_IR1_INTPND16_1_Pos 0 /*!< C_CAN0 IR1: INTPND16_1 Position */ +#define C_CAN0_IR1_INTPND16_1_Msk (0x0000ffffUL << C_CAN0_IR1_INTPND16_1_Pos) /*!< C_CAN0 IR1: INTPND16_1 Mask */ + +/* --------------------------------- C_CAN0_IR2 --------------------------------- */ +#define C_CAN0_IR2_INTPND32_17_Pos 0 /*!< C_CAN0 IR2: INTPND32_17 Position */ +#define C_CAN0_IR2_INTPND32_17_Msk (0x0000ffffUL << C_CAN0_IR2_INTPND32_17_Pos) /*!< C_CAN0 IR2: INTPND32_17 Mask */ + +/* -------------------------------- C_CAN0_MSGV1 -------------------------------- */ +#define C_CAN0_MSGV1_MSGVAL16_1_Pos 0 /*!< C_CAN0 MSGV1: MSGVAL16_1 Position */ +#define C_CAN0_MSGV1_MSGVAL16_1_Msk (0x0000ffffUL << C_CAN0_MSGV1_MSGVAL16_1_Pos) /*!< C_CAN0 MSGV1: MSGVAL16_1 Mask */ + +/* -------------------------------- C_CAN0_MSGV2 -------------------------------- */ +#define C_CAN0_MSGV2_MSGVAL32_17_Pos 0 /*!< C_CAN0 MSGV2: MSGVAL32_17 Position */ +#define C_CAN0_MSGV2_MSGVAL32_17_Msk (0x0000ffffUL << C_CAN0_MSGV2_MSGVAL32_17_Pos) /*!< C_CAN0 MSGV2: MSGVAL32_17 Mask */ + +/* -------------------------------- C_CAN0_CLKDIV ------------------------------- */ +#define C_CAN0_CLKDIV_CLKDIVVAL_Pos 0 /*!< C_CAN0 CLKDIV: CLKDIVVAL Position */ +#define C_CAN0_CLKDIV_CLKDIVVAL_Msk (0x0fUL << C_CAN0_CLKDIV_CLKDIVVAL_Pos) /*!< C_CAN0 CLKDIV: CLKDIVVAL Mask */ + + +/* ================================================================================ */ +/* ================ Group 'ADCn' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------------- ADCn_CR ---------------------------------- */ +#define ADCn_CR_SEL_Pos 0 /*!< ADCn CR: SEL Position */ +#define ADCn_CR_SEL_Msk (0x000000ffUL << ADCn_CR_SEL_Pos) /*!< ADCn CR: SEL Mask */ +#define ADCn_CR_CLKDIV_Pos 8 /*!< ADCn CR: CLKDIV Position */ +#define ADCn_CR_CLKDIV_Msk (0x000000ffUL << ADCn_CR_CLKDIV_Pos) /*!< ADCn CR: CLKDIV Mask */ +#define ADCn_CR_BURST_Pos 16 /*!< ADCn CR: BURST Position */ +#define ADCn_CR_BURST_Msk (0x01UL << ADCn_CR_BURST_Pos) /*!< ADCn CR: BURST Mask */ +#define ADCn_CR_CLKS_Pos 17 /*!< ADCn CR: CLKS Position */ +#define ADCn_CR_CLKS_Msk (0x07UL << ADCn_CR_CLKS_Pos) /*!< ADCn CR: CLKS Mask */ +#define ADCn_CR_PDN_Pos 21 /*!< ADCn CR: PDN Position */ +#define ADCn_CR_PDN_Msk (0x01UL << ADCn_CR_PDN_Pos) /*!< ADCn CR: PDN Mask */ +#define ADCn_CR_START_Pos 24 /*!< ADCn CR: START Position */ +#define ADCn_CR_START_Msk (0x07UL << ADCn_CR_START_Pos) /*!< ADCn CR: START Mask */ +#define ADCn_CR_EDGE_Pos 27 /*!< ADCn CR: EDGE Position */ +#define ADCn_CR_EDGE_Msk (0x01UL << ADCn_CR_EDGE_Pos) /*!< ADCn CR: EDGE Mask */ + +/* ---------------------------------- ADCn_GDR ---------------------------------- */ +#define ADCn_GDR_V_VREF_Pos 6 /*!< ADCn GDR: V_VREF Position */ +#define ADCn_GDR_V_VREF_Msk (0x000003ffUL << ADCn_GDR_V_VREF_Pos) /*!< ADCn GDR: V_VREF Mask */ +#define ADCn_GDR_CHN_Pos 24 /*!< ADCn GDR: CHN Position */ +#define ADCn_GDR_CHN_Msk (0x07UL << ADCn_GDR_CHN_Pos) /*!< ADCn GDR: CHN Mask */ +#define ADCn_GDR_OVERRUN_Pos 30 /*!< ADCn GDR: OVERRUN Position */ +#define ADCn_GDR_OVERRUN_Msk (0x01UL << ADCn_GDR_OVERRUN_Pos) /*!< ADCn GDR: OVERRUN Mask */ +#define ADCn_GDR_DONE_Pos 31 /*!< ADCn GDR: DONE Position */ +#define ADCn_GDR_DONE_Msk (0x01UL << ADCn_GDR_DONE_Pos) /*!< ADCn GDR: DONE Mask */ + +/* --------------------------------- ADCn_INTEN --------------------------------- */ +#define ADCn_INTEN_ADINTEN_Pos 0 /*!< ADCn INTEN: ADINTEN Position */ +#define ADCn_INTEN_ADINTEN_Msk (0x000000ffUL << ADCn_INTEN_ADINTEN_Pos) /*!< ADCn INTEN: ADINTEN Mask */ +#define ADCn_INTEN_ADGINTEN_Pos 8 /*!< ADCn INTEN: ADGINTEN Position */ +#define ADCn_INTEN_ADGINTEN_Msk (0x01UL << ADCn_INTEN_ADGINTEN_Pos) /*!< ADCn INTEN: ADGINTEN Mask */ + +/* ----------------------------------- ADCn_DR ---------------------------------- */ +#define ADCn_DR_V_VREF_Pos 6 /*!< ADCn DR: V_VREF Position */ +#define ADCn_DR_V_VREF_Msk (0x000003ffUL << ADCn_DR_V_VREF_Pos) /*!< ADCn DR: V_VREF Mask */ +#define ADCn_DR_OVERRUN_Pos 30 /*!< ADCn DR: OVERRUN Position */ +#define ADCn_DR_OVERRUN_Msk (0x01UL << ADCn_DR_OVERRUN_Pos) /*!< ADCn DR: OVERRUN Mask */ +#define ADCn_DR_DONE_Pos 31 /*!< ADCn DR: DONE Position */ +#define ADCn_DR_DONE_Msk (0x01UL << ADCn_DR_DONE_Pos) /*!< ADCn DR: DONE Mask */ + +/* ---------------------------------- ADCn_STAT --------------------------------- */ +#define ADCn_STAT_DONE_Pos 0 /*!< ADCn STAT: DONE Position */ +#define ADCn_STAT_DONE_Msk (0x000000ffUL << ADCn_STAT_DONE_Pos) /*!< ADCn STAT: DONE Mask */ +#define ADCn_STAT_OVERUN_Pos 8 /*!< ADCn STAT: OVERUN Position */ +#define ADCn_STAT_OVERUN_Msk (0x000000ffUL << ADCn_STAT_OVERUN_Pos) /*!< ADCn STAT: OVERUN Mask */ +#define ADCn_STAT_ADINT_Pos 16 /*!< ADCn STAT: ADINT Position */ +#define ADCn_STAT_ADINT_Msk (0x01UL << ADCn_STAT_ADINT_Pos) /*!< ADCn STAT: ADINT Mask */ + + +/* ================================================================================ */ +/* ================ struct 'ADC0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------------- ADC0_CR ---------------------------------- */ +#define ADC0_CR_SEL_Pos 0 /*!< ADC0 CR: SEL Position */ +#define ADC0_CR_SEL_Msk (0x000000ffUL << ADC0_CR_SEL_Pos) /*!< ADC0 CR: SEL Mask */ +#define ADC0_CR_CLKDIV_Pos 8 /*!< ADC0 CR: CLKDIV Position */ +#define ADC0_CR_CLKDIV_Msk (0x000000ffUL << ADC0_CR_CLKDIV_Pos) /*!< ADC0 CR: CLKDIV Mask */ +#define ADC0_CR_BURST_Pos 16 /*!< ADC0 CR: BURST Position */ +#define ADC0_CR_BURST_Msk (0x01UL << ADC0_CR_BURST_Pos) /*!< ADC0 CR: BURST Mask */ +#define ADC0_CR_CLKS_Pos 17 /*!< ADC0 CR: CLKS Position */ +#define ADC0_CR_CLKS_Msk (0x07UL << ADC0_CR_CLKS_Pos) /*!< ADC0 CR: CLKS Mask */ +#define ADC0_CR_PDN_Pos 21 /*!< ADC0 CR: PDN Position */ +#define ADC0_CR_PDN_Msk (0x01UL << ADC0_CR_PDN_Pos) /*!< ADC0 CR: PDN Mask */ +#define ADC0_CR_START_Pos 24 /*!< ADC0 CR: START Position */ +#define ADC0_CR_START_Msk (0x07UL << ADC0_CR_START_Pos) /*!< ADC0 CR: START Mask */ +#define ADC0_CR_EDGE_Pos 27 /*!< ADC0 CR: EDGE Position */ +#define ADC0_CR_EDGE_Msk (0x01UL << ADC0_CR_EDGE_Pos) /*!< ADC0 CR: EDGE Mask */ + +/* ---------------------------------- ADC0_GDR ---------------------------------- */ +#define ADC0_GDR_V_VREF_Pos 6 /*!< ADC0 GDR: V_VREF Position */ +#define ADC0_GDR_V_VREF_Msk (0x000003ffUL << ADC0_GDR_V_VREF_Pos) /*!< ADC0 GDR: V_VREF Mask */ +#define ADC0_GDR_CHN_Pos 24 /*!< ADC0 GDR: CHN Position */ +#define ADC0_GDR_CHN_Msk (0x07UL << ADC0_GDR_CHN_Pos) /*!< ADC0 GDR: CHN Mask */ +#define ADC0_GDR_OVERRUN_Pos 30 /*!< ADC0 GDR: OVERRUN Position */ +#define ADC0_GDR_OVERRUN_Msk (0x01UL << ADC0_GDR_OVERRUN_Pos) /*!< ADC0 GDR: OVERRUN Mask */ +#define ADC0_GDR_DONE_Pos 31 /*!< ADC0 GDR: DONE Position */ +#define ADC0_GDR_DONE_Msk (0x01UL << ADC0_GDR_DONE_Pos) /*!< ADC0 GDR: DONE Mask */ + +/* --------------------------------- ADC0_INTEN --------------------------------- */ +#define ADC0_INTEN_ADINTEN_Pos 0 /*!< ADC0 INTEN: ADINTEN Position */ +#define ADC0_INTEN_ADINTEN_Msk (0x000000ffUL << ADC0_INTEN_ADINTEN_Pos) /*!< ADC0 INTEN: ADINTEN Mask */ +#define ADC0_INTEN_ADGINTEN_Pos 8 /*!< ADC0 INTEN: ADGINTEN Position */ +#define ADC0_INTEN_ADGINTEN_Msk (0x01UL << ADC0_INTEN_ADGINTEN_Pos) /*!< ADC0 INTEN: ADGINTEN Mask */ + +/* ----------------------------------- ADC0_DR ---------------------------------- */ +#define ADC0_DR_V_VREF_Pos 6 /*!< ADC0 DR: V_VREF Position */ +#define ADC0_DR_V_VREF_Msk (0x000003ffUL << ADC0_DR_V_VREF_Pos) /*!< ADC0 DR: V_VREF Mask */ +#define ADC0_DR_OVERRUN_Pos 30 /*!< ADC0 DR: OVERRUN Position */ +#define ADC0_DR_OVERRUN_Msk (0x01UL << ADC0_DR_OVERRUN_Pos) /*!< ADC0 DR: OVERRUN Mask */ +#define ADC0_DR_DONE_Pos 31 /*!< ADC0 DR: DONE Position */ +#define ADC0_DR_DONE_Msk (0x01UL << ADC0_DR_DONE_Pos) /*!< ADC0 DR: DONE Mask */ + +/* ---------------------------------- ADC0_STAT --------------------------------- */ +#define ADC0_STAT_DONE_Pos 0 /*!< ADC0 STAT: DONE Position */ +#define ADC0_STAT_DONE_Msk (0x000000ffUL << ADC0_STAT_DONE_Pos) /*!< ADC0 STAT: DONE Mask */ +#define ADC0_STAT_OVERUN_Pos 8 /*!< ADC0 STAT: OVERUN Position */ +#define ADC0_STAT_OVERUN_Msk (0x000000ffUL << ADC0_STAT_OVERUN_Pos) /*!< ADC0 STAT: OVERUN Mask */ +#define ADC0_STAT_ADINT_Pos 16 /*!< ADC0 STAT: ADINT Position */ +#define ADC0_STAT_ADINT_Msk (0x01UL << ADC0_STAT_ADINT_Pos) /*!< ADC0 STAT: ADINT Mask */ + + +/* ================================================================================ */ +/* ================ struct 'ADC1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------------- ADC1_CR ---------------------------------- */ +#define ADC1_CR_SEL_Pos 0 /*!< ADC1 CR: SEL Position */ +#define ADC1_CR_SEL_Msk (0x000000ffUL << ADC1_CR_SEL_Pos) /*!< ADC1 CR: SEL Mask */ +#define ADC1_CR_CLKDIV_Pos 8 /*!< ADC1 CR: CLKDIV Position */ +#define ADC1_CR_CLKDIV_Msk (0x000000ffUL << ADC1_CR_CLKDIV_Pos) /*!< ADC1 CR: CLKDIV Mask */ +#define ADC1_CR_BURST_Pos 16 /*!< ADC1 CR: BURST Position */ +#define ADC1_CR_BURST_Msk (0x01UL << ADC1_CR_BURST_Pos) /*!< ADC1 CR: BURST Mask */ +#define ADC1_CR_CLKS_Pos 17 /*!< ADC1 CR: CLKS Position */ +#define ADC1_CR_CLKS_Msk (0x07UL << ADC1_CR_CLKS_Pos) /*!< ADC1 CR: CLKS Mask */ +#define ADC1_CR_PDN_Pos 21 /*!< ADC1 CR: PDN Position */ +#define ADC1_CR_PDN_Msk (0x01UL << ADC1_CR_PDN_Pos) /*!< ADC1 CR: PDN Mask */ +#define ADC1_CR_START_Pos 24 /*!< ADC1 CR: START Position */ +#define ADC1_CR_START_Msk (0x07UL << ADC1_CR_START_Pos) /*!< ADC1 CR: START Mask */ +#define ADC1_CR_EDGE_Pos 27 /*!< ADC1 CR: EDGE Position */ +#define ADC1_CR_EDGE_Msk (0x01UL << ADC1_CR_EDGE_Pos) /*!< ADC1 CR: EDGE Mask */ + +/* ---------------------------------- ADC1_GDR ---------------------------------- */ +#define ADC1_GDR_V_VREF_Pos 6 /*!< ADC1 GDR: V_VREF Position */ +#define ADC1_GDR_V_VREF_Msk (0x000003ffUL << ADC1_GDR_V_VREF_Pos) /*!< ADC1 GDR: V_VREF Mask */ +#define ADC1_GDR_CHN_Pos 24 /*!< ADC1 GDR: CHN Position */ +#define ADC1_GDR_CHN_Msk (0x07UL << ADC1_GDR_CHN_Pos) /*!< ADC1 GDR: CHN Mask */ +#define ADC1_GDR_OVERRUN_Pos 30 /*!< ADC1 GDR: OVERRUN Position */ +#define ADC1_GDR_OVERRUN_Msk (0x01UL << ADC1_GDR_OVERRUN_Pos) /*!< ADC1 GDR: OVERRUN Mask */ +#define ADC1_GDR_DONE_Pos 31 /*!< ADC1 GDR: DONE Position */ +#define ADC1_GDR_DONE_Msk (0x01UL << ADC1_GDR_DONE_Pos) /*!< ADC1 GDR: DONE Mask */ + +/* --------------------------------- ADC1_INTEN --------------------------------- */ +#define ADC1_INTEN_ADINTEN_Pos 0 /*!< ADC1 INTEN: ADINTEN Position */ +#define ADC1_INTEN_ADINTEN_Msk (0x000000ffUL << ADC1_INTEN_ADINTEN_Pos) /*!< ADC1 INTEN: ADINTEN Mask */ +#define ADC1_INTEN_ADGINTEN_Pos 8 /*!< ADC1 INTEN: ADGINTEN Position */ +#define ADC1_INTEN_ADGINTEN_Msk (0x01UL << ADC1_INTEN_ADGINTEN_Pos) /*!< ADC1 INTEN: ADGINTEN Mask */ + +/* ----------------------------------- ADC1_DR ---------------------------------- */ +#define ADC1_DR_V_VREF_Pos 6 /*!< ADC1 DR: V_VREF Position */ +#define ADC1_DR_V_VREF_Msk (0x000003ffUL << ADC1_DR_V_VREF_Pos) /*!< ADC1 DR: V_VREF Mask */ +#define ADC1_DR_OVERRUN_Pos 30 /*!< ADC1 DR: OVERRUN Position */ +#define ADC1_DR_OVERRUN_Msk (0x01UL << ADC1_DR_OVERRUN_Pos) /*!< ADC1 DR: OVERRUN Mask */ +#define ADC1_DR_DONE_Pos 31 /*!< ADC1 DR: DONE Position */ +#define ADC1_DR_DONE_Msk (0x01UL << ADC1_DR_DONE_Pos) /*!< ADC1 DR: DONE Mask */ + +/* ---------------------------------- ADC1_STAT --------------------------------- */ +#define ADC1_STAT_DONE_Pos 0 /*!< ADC1 STAT: DONE Position */ +#define ADC1_STAT_DONE_Msk (0x000000ffUL << ADC1_STAT_DONE_Pos) /*!< ADC1 STAT: DONE Mask */ +#define ADC1_STAT_OVERUN_Pos 8 /*!< ADC1 STAT: OVERUN Position */ +#define ADC1_STAT_OVERUN_Msk (0x000000ffUL << ADC1_STAT_OVERUN_Pos) /*!< ADC1 STAT: OVERUN Mask */ +#define ADC1_STAT_ADINT_Pos 16 /*!< ADC1 STAT: ADINT Position */ +#define ADC1_STAT_ADINT_Msk (0x01UL << ADC1_STAT_ADINT_Pos) /*!< ADC1 STAT: ADINT Mask */ + + +/* ================================================================================ */ +/* ================ struct 'ADCHS' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- ADCHS_FLUSH -------------------------------- */ +#define ADCHS_FLUSH_FIFO_FLUSH_Pos 0 /*!< ADCHS FLUSH: FIFO_FLUSH Position */ +#define ADCHS_FLUSH_FIFO_FLUSH_Msk (0x01UL << ADCHS_FLUSH_FIFO_FLUSH_Pos) /*!< ADCHS FLUSH: FIFO_FLUSH Mask */ + +/* -------------------------------- ADCHS_DMA_REQ ------------------------------- */ +#define ADCHS_DMA_REQ_DMA_REQ_WR_Pos 0 /*!< ADCHS DMA_REQ: DMA_REQ_WR Position */ +#define ADCHS_DMA_REQ_DMA_REQ_WR_Msk (0x01UL << ADCHS_DMA_REQ_DMA_REQ_WR_Pos) /*!< ADCHS DMA_REQ: DMA_REQ_WR Mask */ + +/* ------------------------------- ADCHS_FIFO_STS ------------------------------- */ +#define ADCHS_FIFO_STS_LEVEL_Pos 0 /*!< ADCHS FIFO_STS: LEVEL Position */ +#define ADCHS_FIFO_STS_LEVEL_Msk (0x1fUL << ADCHS_FIFO_STS_LEVEL_Pos) /*!< ADCHS FIFO_STS: LEVEL Mask */ + +/* ------------------------------- ADCHS_FIFO_CFG ------------------------------- */ +#define ADCHS_FIFO_CFG_PACKED_READ_Pos 0 /*!< ADCHS FIFO_CFG: PACKED_READ Position */ +#define ADCHS_FIFO_CFG_PACKED_READ_Msk (0x01UL << ADCHS_FIFO_CFG_PACKED_READ_Pos) /*!< ADCHS FIFO_CFG: PACKED_READ Mask */ +#define ADCHS_FIFO_CFG_LEVEL_Pos 1 /*!< ADCHS FIFO_CFG: LEVEL Position */ +#define ADCHS_FIFO_CFG_LEVEL_Msk (0x1fUL << ADCHS_FIFO_CFG_LEVEL_Pos) /*!< ADCHS FIFO_CFG: LEVEL Mask */ + +/* -------------------------------- ADCHS_TRIGGER ------------------------------- */ +#define ADCHS_TRIGGER_SW_TRIGGER_Pos 0 /*!< ADCHS TRIGGER: SW_TRIGGER Position */ +#define ADCHS_TRIGGER_SW_TRIGGER_Msk (0x01UL << ADCHS_TRIGGER_SW_TRIGGER_Pos) /*!< ADCHS TRIGGER: SW_TRIGGER Mask */ + +/* ------------------------------- ADCHS_DSCR_STS ------------------------------- */ +#define ADCHS_DSCR_STS_ACT_TABLE_Pos 0 /*!< ADCHS DSCR_STS: ACT_TABLE Position */ +#define ADCHS_DSCR_STS_ACT_TABLE_Msk (0x01UL << ADCHS_DSCR_STS_ACT_TABLE_Pos) /*!< ADCHS DSCR_STS: ACT_TABLE Mask */ +#define ADCHS_DSCR_STS_ACT_DESCRIPTOR_Pos 1 /*!< ADCHS DSCR_STS: ACT_DESCRIPTOR Position */ +#define ADCHS_DSCR_STS_ACT_DESCRIPTOR_Msk (0x07UL << ADCHS_DSCR_STS_ACT_DESCRIPTOR_Pos) /*!< ADCHS DSCR_STS: ACT_DESCRIPTOR Mask */ + +/* ------------------------------ ADCHS_POWER_DOWN ------------------------------ */ +#define ADCHS_POWER_DOWN_PD_CTRL_Pos 0 /*!< ADCHS POWER_DOWN: PD_CTRL Position */ +#define ADCHS_POWER_DOWN_PD_CTRL_Msk (0x01UL << ADCHS_POWER_DOWN_PD_CTRL_Pos) /*!< ADCHS POWER_DOWN: PD_CTRL Mask */ + +/* -------------------------------- ADCHS_CONFIG -------------------------------- */ +#define ADCHS_CONFIG_TRIGGER__MASK_Pos 0 /*!< ADCHS CONFIG: TRIGGER__MASK Position */ +#define ADCHS_CONFIG_TRIGGER__MASK_Msk (0x03UL << ADCHS_CONFIG_TRIGGER__MASK_Pos) /*!< ADCHS CONFIG: TRIGGER__MASK Mask */ +#define ADCHS_CONFIG_TRIGGER_MODE_Pos 2 /*!< ADCHS CONFIG: TRIGGER_MODE Position */ +#define ADCHS_CONFIG_TRIGGER_MODE_Msk (0x03UL << ADCHS_CONFIG_TRIGGER_MODE_Pos) /*!< ADCHS CONFIG: TRIGGER_MODE Mask */ +#define ADCHS_CONFIG_TRIGGER_SYNC_Pos 4 /*!< ADCHS CONFIG: TRIGGER_SYNC Position */ +#define ADCHS_CONFIG_TRIGGER_SYNC_Msk (0x01UL << ADCHS_CONFIG_TRIGGER_SYNC_Pos) /*!< ADCHS CONFIG: TRIGGER_SYNC Mask */ +#define ADCHS_CONFIG_CHANNEL_ID_EN_Pos 5 /*!< ADCHS CONFIG: CHANNEL_ID_EN Position */ +#define ADCHS_CONFIG_CHANNEL_ID_EN_Msk (0x01UL << ADCHS_CONFIG_CHANNEL_ID_EN_Pos) /*!< ADCHS CONFIG: CHANNEL_ID_EN Mask */ +#define ADCHS_CONFIG_RECOVERY_TIME_Pos 6 /*!< ADCHS CONFIG: RECOVERY_TIME Position */ +#define ADCHS_CONFIG_RECOVERY_TIME_Msk (0x000000ffUL << ADCHS_CONFIG_RECOVERY_TIME_Pos) /*!< ADCHS CONFIG: RECOVERY_TIME Mask */ + +/* --------------------------------- ADCHS_THR_A -------------------------------- */ +#define ADCHS_THR_A_THR_LOW_A_Pos 0 /*!< ADCHS THR_A: THR_LOW_A Position */ +#define ADCHS_THR_A_THR_LOW_A_Msk (0x00000fffUL << ADCHS_THR_A_THR_LOW_A_Pos) /*!< ADCHS THR_A: THR_LOW_A Mask */ +#define ADCHS_THR_A_THR_HIGH_A_Pos 16 /*!< ADCHS THR_A: THR_HIGH_A Position */ +#define ADCHS_THR_A_THR_HIGH_A_Msk (0x00000fffUL << ADCHS_THR_A_THR_HIGH_A_Pos) /*!< ADCHS THR_A: THR_HIGH_A Mask */ + +/* --------------------------------- ADCHS_THR_B -------------------------------- */ +#define ADCHS_THR_B_THR_LOW_B_Pos 0 /*!< ADCHS THR_B: THR_LOW_B Position */ +#define ADCHS_THR_B_THR_LOW_B_Msk (0x00000fffUL << ADCHS_THR_B_THR_LOW_B_Pos) /*!< ADCHS THR_B: THR_LOW_B Mask */ +#define ADCHS_THR_B_THR_HIGH_B_Pos 16 /*!< ADCHS THR_B: THR_HIGH_B Position */ +#define ADCHS_THR_B_THR_HIGH_B_Msk (0x00000fffUL << ADCHS_THR_B_THR_HIGH_B_Pos) /*!< ADCHS THR_B: THR_HIGH_B Mask */ + +/* ------------------------------ ADCHS_LAST_SAMPLE ----------------------------- */ +#define ADCHS_LAST_SAMPLE_DONE_Pos 0 /*!< ADCHS LAST_SAMPLE: DONE Position */ +#define ADCHS_LAST_SAMPLE_DONE_Msk (0x01UL << ADCHS_LAST_SAMPLE_DONE_Pos) /*!< ADCHS LAST_SAMPLE: DONE Mask */ +#define ADCHS_LAST_SAMPLE_OVERRUN_Pos 1 /*!< ADCHS LAST_SAMPLE: OVERRUN Position */ +#define ADCHS_LAST_SAMPLE_OVERRUN_Msk (0x01UL << ADCHS_LAST_SAMPLE_OVERRUN_Pos) /*!< ADCHS LAST_SAMPLE: OVERRUN Mask */ +#define ADCHS_LAST_SAMPLE_THCMP_RANGE_Pos 2 /*!< ADCHS LAST_SAMPLE: THCMP_RANGE Position */ +#define ADCHS_LAST_SAMPLE_THCMP_RANGE_Msk (0x03UL << ADCHS_LAST_SAMPLE_THCMP_RANGE_Pos) /*!< ADCHS LAST_SAMPLE: THCMP_RANGE Mask */ +#define ADCHS_LAST_SAMPLE_THCMP_CROSS_Pos 4 /*!< ADCHS LAST_SAMPLE: THCMP_CROSS Position */ +#define ADCHS_LAST_SAMPLE_THCMP_CROSS_Msk (0x03UL << ADCHS_LAST_SAMPLE_THCMP_CROSS_Pos) /*!< ADCHS LAST_SAMPLE: THCMP_CROSS Mask */ +#define ADCHS_LAST_SAMPLE_SAMPLE_Pos 6 /*!< ADCHS LAST_SAMPLE: SAMPLE Position */ +#define ADCHS_LAST_SAMPLE_SAMPLE_Msk (0x00000fffUL << ADCHS_LAST_SAMPLE_SAMPLE_Pos) /*!< ADCHS LAST_SAMPLE: SAMPLE Mask */ + +/* ------------------------------- ADCHS_ADC_SPEED ------------------------------ */ +#define ADCHS_ADC_SPEED_DGEC0_Pos 0 /*!< ADCHS ADC_SPEED: DGEC0 Position */ +#define ADCHS_ADC_SPEED_DGEC0_Msk (0x0fUL << ADCHS_ADC_SPEED_DGEC0_Pos) /*!< ADCHS ADC_SPEED: DGEC0 Mask */ +#define ADCHS_ADC_SPEED_DGEC1_Pos 4 /*!< ADCHS ADC_SPEED: DGEC1 Position */ +#define ADCHS_ADC_SPEED_DGEC1_Msk (0x0fUL << ADCHS_ADC_SPEED_DGEC1_Pos) /*!< ADCHS ADC_SPEED: DGEC1 Mask */ +#define ADCHS_ADC_SPEED_DGEC2_Pos 8 /*!< ADCHS ADC_SPEED: DGEC2 Position */ +#define ADCHS_ADC_SPEED_DGEC2_Msk (0x0fUL << ADCHS_ADC_SPEED_DGEC2_Pos) /*!< ADCHS ADC_SPEED: DGEC2 Mask */ +#define ADCHS_ADC_SPEED_DGEC3_Pos 12 /*!< ADCHS ADC_SPEED: DGEC3 Position */ +#define ADCHS_ADC_SPEED_DGEC3_Msk (0x0fUL << ADCHS_ADC_SPEED_DGEC3_Pos) /*!< ADCHS ADC_SPEED: DGEC3 Mask */ +#define ADCHS_ADC_SPEED_DGEC4_Pos 16 /*!< ADCHS ADC_SPEED: DGEC4 Position */ +#define ADCHS_ADC_SPEED_DGEC4_Msk (0x0fUL << ADCHS_ADC_SPEED_DGEC4_Pos) /*!< ADCHS ADC_SPEED: DGEC4 Mask */ +#define ADCHS_ADC_SPEED_DGEC5_Pos 20 /*!< ADCHS ADC_SPEED: DGEC5 Position */ +#define ADCHS_ADC_SPEED_DGEC5_Msk (0x0fUL << ADCHS_ADC_SPEED_DGEC5_Pos) /*!< ADCHS ADC_SPEED: DGEC5 Mask */ + +/* ----------------------------- ADCHS_POWER_CONTROL ---------------------------- */ +#define ADCHS_POWER_CONTROL_CRS_Pos 0 /*!< ADCHS POWER_CONTROL: CRS Position */ +#define ADCHS_POWER_CONTROL_CRS_Msk (0x0fUL << ADCHS_POWER_CONTROL_CRS_Pos) /*!< ADCHS POWER_CONTROL: CRS Mask */ +#define ADCHS_POWER_CONTROL_DCINNEG_Pos 4 /*!< ADCHS POWER_CONTROL: DCINNEG Position */ +#define ADCHS_POWER_CONTROL_DCINNEG_Msk (0x3fUL << ADCHS_POWER_CONTROL_DCINNEG_Pos) /*!< ADCHS POWER_CONTROL: DCINNEG Mask */ +#define ADCHS_POWER_CONTROL_DCINPOS_Pos 10 /*!< ADCHS POWER_CONTROL: DCINPOS Position */ +#define ADCHS_POWER_CONTROL_DCINPOS_Msk (0x3fUL << ADCHS_POWER_CONTROL_DCINPOS_Pos) /*!< ADCHS POWER_CONTROL: DCINPOS Mask */ +#define ADCHS_POWER_CONTROL_TWOS_Pos 16 /*!< ADCHS POWER_CONTROL: TWOS Position */ +#define ADCHS_POWER_CONTROL_TWOS_Msk (0x01UL << ADCHS_POWER_CONTROL_TWOS_Pos) /*!< ADCHS POWER_CONTROL: TWOS Mask */ +#define ADCHS_POWER_CONTROL_POWER_SWITCH_Pos 17 /*!< ADCHS POWER_CONTROL: POWER_SWITCH Position */ +#define ADCHS_POWER_CONTROL_POWER_SWITCH_Msk (0x01UL << ADCHS_POWER_CONTROL_POWER_SWITCH_Pos) /*!< ADCHS POWER_CONTROL: POWER_SWITCH Mask */ +#define ADCHS_POWER_CONTROL_BGAP_SWITCH_Pos 18 /*!< ADCHS POWER_CONTROL: BGAP_SWITCH Position */ +#define ADCHS_POWER_CONTROL_BGAP_SWITCH_Msk (0x01UL << ADCHS_POWER_CONTROL_BGAP_SWITCH_Pos) /*!< ADCHS POWER_CONTROL: BGAP_SWITCH Mask */ + +/* ------------------------------ ADCHS_FIFO_OUTPUT ----------------------------- */ +#define ADCHS_FIFO_OUTPUT_SAMPLE_Pos 0 /*!< ADCHS FIFO_OUTPUT: SAMPLE Position */ +#define ADCHS_FIFO_OUTPUT_SAMPLE_Msk (0x00000fffUL << ADCHS_FIFO_OUTPUT_SAMPLE_Pos) /*!< ADCHS FIFO_OUTPUT: SAMPLE Mask */ +#define ADCHS_FIFO_OUTPUT_CHAN_ID_Pos 12 /*!< ADCHS FIFO_OUTPUT: CHAN_ID Position */ +#define ADCHS_FIFO_OUTPUT_CHAN_ID_Msk (0x07UL << ADCHS_FIFO_OUTPUT_CHAN_ID_Pos) /*!< ADCHS FIFO_OUTPUT: CHAN_ID Mask */ +#define ADCHS_FIFO_OUTPUT_EMPTY_Pos 15 /*!< ADCHS FIFO_OUTPUT: EMPTY Position */ +#define ADCHS_FIFO_OUTPUT_EMPTY_Msk (0x01UL << ADCHS_FIFO_OUTPUT_EMPTY_Pos) /*!< ADCHS FIFO_OUTPUT: EMPTY Mask */ +#define ADCHS_FIFO_OUTPUT_SAMPLE2_Pos 16 /*!< ADCHS FIFO_OUTPUT: SAMPLE2 Position */ +#define ADCHS_FIFO_OUTPUT_SAMPLE2_Msk (0x00000fffUL << ADCHS_FIFO_OUTPUT_SAMPLE2_Pos) /*!< ADCHS FIFO_OUTPUT: SAMPLE2 Mask */ +#define ADCHS_FIFO_OUTPUT_CHAN_ID2_Pos 28 /*!< ADCHS FIFO_OUTPUT: CHAN_ID2 Position */ +#define ADCHS_FIFO_OUTPUT_CHAN_ID2_Msk (0x07UL << ADCHS_FIFO_OUTPUT_CHAN_ID2_Pos) /*!< ADCHS FIFO_OUTPUT: CHAN_ID2 Mask */ +#define ADCHS_FIFO_OUTPUT_EMPTY2_Pos 31 /*!< ADCHS FIFO_OUTPUT: EMPTY2 Position */ +#define ADCHS_FIFO_OUTPUT_EMPTY2_Msk (0x01UL << ADCHS_FIFO_OUTPUT_EMPTY2_Pos) /*!< ADCHS FIFO_OUTPUT: EMPTY2 Mask */ + +/* ----------------------------- ADCHS_DESCRIPTOR0_ ----------------------------- */ +#define ADCHS_DESCRIPTOR0__CHANNEL_NR_Pos 0 /*!< ADCHS DESCRIPTOR0_: CHANNEL_NR Position */ +#define ADCHS_DESCRIPTOR0__CHANNEL_NR_Msk (0x07UL << ADCHS_DESCRIPTOR0__CHANNEL_NR_Pos) /*!< ADCHS DESCRIPTOR0_: CHANNEL_NR Mask */ +#define ADCHS_DESCRIPTOR0__HALT_Pos 3 /*!< ADCHS DESCRIPTOR0_: HALT Position */ +#define ADCHS_DESCRIPTOR0__HALT_Msk (0x01UL << ADCHS_DESCRIPTOR0__HALT_Pos) /*!< ADCHS DESCRIPTOR0_: HALT Mask */ +#define ADCHS_DESCRIPTOR0__INTERRUPT_Pos 4 /*!< ADCHS DESCRIPTOR0_: INTERRUPT Position */ +#define ADCHS_DESCRIPTOR0__INTERRUPT_Msk (0x01UL << ADCHS_DESCRIPTOR0__INTERRUPT_Pos) /*!< ADCHS DESCRIPTOR0_: INTERRUPT Mask */ +#define ADCHS_DESCRIPTOR0__POWER_DOWN_Pos 5 /*!< ADCHS DESCRIPTOR0_: POWER_DOWN Position */ +#define ADCHS_DESCRIPTOR0__POWER_DOWN_Msk (0x01UL << ADCHS_DESCRIPTOR0__POWER_DOWN_Pos) /*!< ADCHS DESCRIPTOR0_: POWER_DOWN Mask */ +#define ADCHS_DESCRIPTOR0__BRANCH_Pos 6 /*!< ADCHS DESCRIPTOR0_: BRANCH Position */ +#define ADCHS_DESCRIPTOR0__BRANCH_Msk (0x03UL << ADCHS_DESCRIPTOR0__BRANCH_Pos) /*!< ADCHS DESCRIPTOR0_: BRANCH Mask */ +#define ADCHS_DESCRIPTOR0__MATCH_VALUE_Pos 8 /*!< ADCHS DESCRIPTOR0_: MATCH_VALUE Position */ +#define ADCHS_DESCRIPTOR0__MATCH_VALUE_Msk (0x00003fffUL << ADCHS_DESCRIPTOR0__MATCH_VALUE_Pos) /*!< ADCHS DESCRIPTOR0_: MATCH_VALUE Mask */ +#define ADCHS_DESCRIPTOR0__THRESHOLD_SEL_Pos 22 /*!< ADCHS DESCRIPTOR0_: THRESHOLD_SEL Position */ +#define ADCHS_DESCRIPTOR0__THRESHOLD_SEL_Msk (0x03UL << ADCHS_DESCRIPTOR0__THRESHOLD_SEL_Pos) /*!< ADCHS DESCRIPTOR0_: THRESHOLD_SEL Mask */ +#define ADCHS_DESCRIPTOR0__RESET_TIMER_Pos 24 /*!< ADCHS DESCRIPTOR0_: RESET_TIMER Position */ +#define ADCHS_DESCRIPTOR0__RESET_TIMER_Msk (0x01UL << ADCHS_DESCRIPTOR0__RESET_TIMER_Pos) /*!< ADCHS DESCRIPTOR0_: RESET_TIMER Mask */ +#define ADCHS_DESCRIPTOR0__UPDATE_TABLE_Pos 31 /*!< ADCHS DESCRIPTOR0_: UPDATE_TABLE Position */ +#define ADCHS_DESCRIPTOR0__UPDATE_TABLE_Msk (0x01UL << ADCHS_DESCRIPTOR0__UPDATE_TABLE_Pos) /*!< ADCHS DESCRIPTOR0_: UPDATE_TABLE Mask */ + +/* ----------------------------- ADCHS_DESCRIPTOR1_ ----------------------------- */ +#define ADCHS_DESCRIPTOR1__CHANNEL_NR_Pos 0 /*!< ADCHS DESCRIPTOR1_: CHANNEL_NR Position */ +#define ADCHS_DESCRIPTOR1__CHANNEL_NR_Msk (0x07UL << ADCHS_DESCRIPTOR1__CHANNEL_NR_Pos) /*!< ADCHS DESCRIPTOR1_: CHANNEL_NR Mask */ +#define ADCHS_DESCRIPTOR1__HALT_Pos 3 /*!< ADCHS DESCRIPTOR1_: HALT Position */ +#define ADCHS_DESCRIPTOR1__HALT_Msk (0x01UL << ADCHS_DESCRIPTOR1__HALT_Pos) /*!< ADCHS DESCRIPTOR1_: HALT Mask */ +#define ADCHS_DESCRIPTOR1__INTERRUPT_Pos 4 /*!< ADCHS DESCRIPTOR1_: INTERRUPT Position */ +#define ADCHS_DESCRIPTOR1__INTERRUPT_Msk (0x01UL << ADCHS_DESCRIPTOR1__INTERRUPT_Pos) /*!< ADCHS DESCRIPTOR1_: INTERRUPT Mask */ +#define ADCHS_DESCRIPTOR1__POWER_DOWN_Pos 5 /*!< ADCHS DESCRIPTOR1_: POWER_DOWN Position */ +#define ADCHS_DESCRIPTOR1__POWER_DOWN_Msk (0x01UL << ADCHS_DESCRIPTOR1__POWER_DOWN_Pos) /*!< ADCHS DESCRIPTOR1_: POWER_DOWN Mask */ +#define ADCHS_DESCRIPTOR1__BRANCH_Pos 6 /*!< ADCHS DESCRIPTOR1_: BRANCH Position */ +#define ADCHS_DESCRIPTOR1__BRANCH_Msk (0x03UL << ADCHS_DESCRIPTOR1__BRANCH_Pos) /*!< ADCHS DESCRIPTOR1_: BRANCH Mask */ +#define ADCHS_DESCRIPTOR1__MATCH_VALUE_Pos 8 /*!< ADCHS DESCRIPTOR1_: MATCH_VALUE Position */ +#define ADCHS_DESCRIPTOR1__MATCH_VALUE_Msk (0x00003fffUL << ADCHS_DESCRIPTOR1__MATCH_VALUE_Pos) /*!< ADCHS DESCRIPTOR1_: MATCH_VALUE Mask */ +#define ADCHS_DESCRIPTOR1__THRESHOLD_SEL_Pos 22 /*!< ADCHS DESCRIPTOR1_: THRESHOLD_SEL Position */ +#define ADCHS_DESCRIPTOR1__THRESHOLD_SEL_Msk (0x03UL << ADCHS_DESCRIPTOR1__THRESHOLD_SEL_Pos) /*!< ADCHS DESCRIPTOR1_: THRESHOLD_SEL Mask */ +#define ADCHS_DESCRIPTOR1__RESET_TIMER_Pos 24 /*!< ADCHS DESCRIPTOR1_: RESET_TIMER Position */ +#define ADCHS_DESCRIPTOR1__RESET_TIMER_Msk (0x01UL << ADCHS_DESCRIPTOR1__RESET_TIMER_Pos) /*!< ADCHS DESCRIPTOR1_: RESET_TIMER Mask */ +#define ADCHS_DESCRIPTOR1__UPDATE_TABLE_Pos 31 /*!< ADCHS DESCRIPTOR1_: UPDATE_TABLE Position */ +#define ADCHS_DESCRIPTOR1__UPDATE_TABLE_Msk (0x01UL << ADCHS_DESCRIPTOR1__UPDATE_TABLE_Pos) /*!< ADCHS DESCRIPTOR1_: UPDATE_TABLE Mask */ + +/* -------------------------------- ADCHS_CLR_EN0 ------------------------------- */ +#define ADCHS_CLR_EN0_CEN0_Pos 0 /*!< ADCHS CLR_EN0: CEN0 Position */ +#define ADCHS_CLR_EN0_CEN0_Msk (0x7fUL << ADCHS_CLR_EN0_CEN0_Pos) /*!< ADCHS CLR_EN0: CEN0 Mask */ + +/* -------------------------------- ADCHS_SET_EN0 ------------------------------- */ +#define ADCHS_SET_EN0_SEN0_Pos 0 /*!< ADCHS SET_EN0: SEN0 Position */ +#define ADCHS_SET_EN0_SEN0_Msk (0x7fUL << ADCHS_SET_EN0_SEN0_Pos) /*!< ADCHS SET_EN0: SEN0 Mask */ + +/* --------------------------------- ADCHS_MASK0 -------------------------------- */ +#define ADCHS_MASK0_M0_Pos 0 /*!< ADCHS MASK0: M0 Position */ +#define ADCHS_MASK0_M0_Msk (0x7fUL << ADCHS_MASK0_M0_Pos) /*!< ADCHS MASK0: M0 Mask */ + +/* -------------------------------- ADCHS_STATUS0 ------------------------------- */ +#define ADCHS_STATUS0_FIFO_FULL_Pos 0 /*!< ADCHS STATUS0: FIFO_FULL Position */ +#define ADCHS_STATUS0_FIFO_FULL_Msk (0x01UL << ADCHS_STATUS0_FIFO_FULL_Pos) /*!< ADCHS STATUS0: FIFO_FULL Mask */ +#define ADCHS_STATUS0_FIFO_EMPTY_Pos 1 /*!< ADCHS STATUS0: FIFO_EMPTY Position */ +#define ADCHS_STATUS0_FIFO_EMPTY_Msk (0x01UL << ADCHS_STATUS0_FIFO_EMPTY_Pos) /*!< ADCHS STATUS0: FIFO_EMPTY Mask */ +#define ADCHS_STATUS0_FIFO_OVERFLOW_Pos 2 /*!< ADCHS STATUS0: FIFO_OVERFLOW Position */ +#define ADCHS_STATUS0_FIFO_OVERFLOW_Msk (0x01UL << ADCHS_STATUS0_FIFO_OVERFLOW_Pos) /*!< ADCHS STATUS0: FIFO_OVERFLOW Mask */ +#define ADCHS_STATUS0_DSCR_DONE_Pos 3 /*!< ADCHS STATUS0: DSCR_DONE Position */ +#define ADCHS_STATUS0_DSCR_DONE_Msk (0x01UL << ADCHS_STATUS0_DSCR_DONE_Pos) /*!< ADCHS STATUS0: DSCR_DONE Mask */ +#define ADCHS_STATUS0_DSCR_ERROR_Pos 4 /*!< ADCHS STATUS0: DSCR_ERROR Position */ +#define ADCHS_STATUS0_DSCR_ERROR_Msk (0x01UL << ADCHS_STATUS0_DSCR_ERROR_Pos) /*!< ADCHS STATUS0: DSCR_ERROR Mask */ +#define ADCHS_STATUS0_ADC_OVF_Pos 5 /*!< ADCHS STATUS0: ADC_OVF Position */ +#define ADCHS_STATUS0_ADC_OVF_Msk (0x01UL << ADCHS_STATUS0_ADC_OVF_Pos) /*!< ADCHS STATUS0: ADC_OVF Mask */ +#define ADCHS_STATUS0_ADC_UNF_Pos 6 /*!< ADCHS STATUS0: ADC_UNF Position */ +#define ADCHS_STATUS0_ADC_UNF_Msk (0x01UL << ADCHS_STATUS0_ADC_UNF_Pos) /*!< ADCHS STATUS0: ADC_UNF Mask */ + +/* ------------------------------- ADCHS_CLR_STAT0 ------------------------------ */ +#define ADCHS_CLR_STAT0_CSTAT0_Pos 0 /*!< ADCHS CLR_STAT0: CSTAT0 Position */ +#define ADCHS_CLR_STAT0_CSTAT0_Msk (0x7fUL << ADCHS_CLR_STAT0_CSTAT0_Pos) /*!< ADCHS CLR_STAT0: CSTAT0 Mask */ + +/* ------------------------------- ADCHS_SET_STAT0 ------------------------------ */ +#define ADCHS_SET_STAT0_SSTAT0_Pos 0 /*!< ADCHS SET_STAT0: SSTAT0 Position */ +#define ADCHS_SET_STAT0_SSTAT0_Msk (0x7fUL << ADCHS_SET_STAT0_SSTAT0_Pos) /*!< ADCHS SET_STAT0: SSTAT0 Mask */ + +/* -------------------------------- ADCHS_CLR_EN1 ------------------------------- */ +#define ADCHS_CLR_EN1_CEN1_Pos 0 /*!< ADCHS CLR_EN1: CEN1 Position */ +#define ADCHS_CLR_EN1_CEN1_Msk (0x3fffffffUL << ADCHS_CLR_EN1_CEN1_Pos) /*!< ADCHS CLR_EN1: CEN1 Mask */ + +/* -------------------------------- ADCHS_SET_EN1 ------------------------------- */ +#define ADCHS_SET_EN1_SEN1_Pos 0 /*!< ADCHS SET_EN1: SEN1 Position */ +#define ADCHS_SET_EN1_SEN1_Msk (0x3fffffffUL << ADCHS_SET_EN1_SEN1_Pos) /*!< ADCHS SET_EN1: SEN1 Mask */ + +/* --------------------------------- ADCHS_MASK1 -------------------------------- */ +#define ADCHS_MASK1_M1_Pos 0 /*!< ADCHS MASK1: M1 Position */ +#define ADCHS_MASK1_M1_Msk (0x3fffffffUL << ADCHS_MASK1_M1_Pos) /*!< ADCHS MASK1: M1 Mask */ + +/* -------------------------------- ADCHS_STATUS1 ------------------------------- */ +#define ADCHS_STATUS1_THCMP_BRANGE0_Pos 0 /*!< ADCHS STATUS1: THCMP_BRANGE0 Position */ +#define ADCHS_STATUS1_THCMP_BRANGE0_Msk (0x01UL << ADCHS_STATUS1_THCMP_BRANGE0_Pos) /*!< ADCHS STATUS1: THCMP_BRANGE0 Mask */ +#define ADCHS_STATUS1_THCMP_ARANGE0_Pos 1 /*!< ADCHS STATUS1: THCMP_ARANGE0 Position */ +#define ADCHS_STATUS1_THCMP_ARANGE0_Msk (0x01UL << ADCHS_STATUS1_THCMP_ARANGE0_Pos) /*!< ADCHS STATUS1: THCMP_ARANGE0 Mask */ +#define ADCHS_STATUS1_THCMP_DCROSS0_Pos 2 /*!< ADCHS STATUS1: THCMP_DCROSS0 Position */ +#define ADCHS_STATUS1_THCMP_DCROSS0_Msk (0x01UL << ADCHS_STATUS1_THCMP_DCROSS0_Pos) /*!< ADCHS STATUS1: THCMP_DCROSS0 Mask */ +#define ADCHS_STATUS1_THCMP_UCROSS0_Pos 3 /*!< ADCHS STATUS1: THCMP_UCROSS0 Position */ +#define ADCHS_STATUS1_THCMP_UCROSS0_Msk (0x01UL << ADCHS_STATUS1_THCMP_UCROSS0_Pos) /*!< ADCHS STATUS1: THCMP_UCROSS0 Mask */ +#define ADCHS_STATUS1_OVERRUN_0_Pos 4 /*!< ADCHS STATUS1: OVERRUN_0 Position */ +#define ADCHS_STATUS1_OVERRUN_0_Msk (0x01UL << ADCHS_STATUS1_OVERRUN_0_Pos) /*!< ADCHS STATUS1: OVERRUN_0 Mask */ +#define ADCHS_STATUS1_THCMP_BRANGE1_Pos 5 /*!< ADCHS STATUS1: THCMP_BRANGE1 Position */ +#define ADCHS_STATUS1_THCMP_BRANGE1_Msk (0x01UL << ADCHS_STATUS1_THCMP_BRANGE1_Pos) /*!< ADCHS STATUS1: THCMP_BRANGE1 Mask */ +#define ADCHS_STATUS1_THCMP_ARANGE1_Pos 6 /*!< ADCHS STATUS1: THCMP_ARANGE1 Position */ +#define ADCHS_STATUS1_THCMP_ARANGE1_Msk (0x01UL << ADCHS_STATUS1_THCMP_ARANGE1_Pos) /*!< ADCHS STATUS1: THCMP_ARANGE1 Mask */ +#define ADCHS_STATUS1_THCMP_DCROSS1_Pos 7 /*!< ADCHS STATUS1: THCMP_DCROSS1 Position */ +#define ADCHS_STATUS1_THCMP_DCROSS1_Msk (0x01UL << ADCHS_STATUS1_THCMP_DCROSS1_Pos) /*!< ADCHS STATUS1: THCMP_DCROSS1 Mask */ +#define ADCHS_STATUS1_THCMP_UCROSS1_Pos 8 /*!< ADCHS STATUS1: THCMP_UCROSS1 Position */ +#define ADCHS_STATUS1_THCMP_UCROSS1_Msk (0x01UL << ADCHS_STATUS1_THCMP_UCROSS1_Pos) /*!< ADCHS STATUS1: THCMP_UCROSS1 Mask */ +#define ADCHS_STATUS1_OVERRUN_1_Pos 9 /*!< ADCHS STATUS1: OVERRUN_1 Position */ +#define ADCHS_STATUS1_OVERRUN_1_Msk (0x01UL << ADCHS_STATUS1_OVERRUN_1_Pos) /*!< ADCHS STATUS1: OVERRUN_1 Mask */ +#define ADCHS_STATUS1_THCMP_BRANGE2_Pos 10 /*!< ADCHS STATUS1: THCMP_BRANGE2 Position */ +#define ADCHS_STATUS1_THCMP_BRANGE2_Msk (0x01UL << ADCHS_STATUS1_THCMP_BRANGE2_Pos) /*!< ADCHS STATUS1: THCMP_BRANGE2 Mask */ +#define ADCHS_STATUS1_THCMP_ARANGE2_Pos 11 /*!< ADCHS STATUS1: THCMP_ARANGE2 Position */ +#define ADCHS_STATUS1_THCMP_ARANGE2_Msk (0x01UL << ADCHS_STATUS1_THCMP_ARANGE2_Pos) /*!< ADCHS STATUS1: THCMP_ARANGE2 Mask */ +#define ADCHS_STATUS1_THCMP_DCROSS2_Pos 12 /*!< ADCHS STATUS1: THCMP_DCROSS2 Position */ +#define ADCHS_STATUS1_THCMP_DCROSS2_Msk (0x01UL << ADCHS_STATUS1_THCMP_DCROSS2_Pos) /*!< ADCHS STATUS1: THCMP_DCROSS2 Mask */ +#define ADCHS_STATUS1_THCMP_UCROSS2_Pos 13 /*!< ADCHS STATUS1: THCMP_UCROSS2 Position */ +#define ADCHS_STATUS1_THCMP_UCROSS2_Msk (0x01UL << ADCHS_STATUS1_THCMP_UCROSS2_Pos) /*!< ADCHS STATUS1: THCMP_UCROSS2 Mask */ +#define ADCHS_STATUS1_OVERRUN_2_Pos 14 /*!< ADCHS STATUS1: OVERRUN_2 Position */ +#define ADCHS_STATUS1_OVERRUN_2_Msk (0x01UL << ADCHS_STATUS1_OVERRUN_2_Pos) /*!< ADCHS STATUS1: OVERRUN_2 Mask */ +#define ADCHS_STATUS1_THCMP_BRANGE3_Pos 15 /*!< ADCHS STATUS1: THCMP_BRANGE3 Position */ +#define ADCHS_STATUS1_THCMP_BRANGE3_Msk (0x01UL << ADCHS_STATUS1_THCMP_BRANGE3_Pos) /*!< ADCHS STATUS1: THCMP_BRANGE3 Mask */ +#define ADCHS_STATUS1_THCMP_ARANGE3_Pos 16 /*!< ADCHS STATUS1: THCMP_ARANGE3 Position */ +#define ADCHS_STATUS1_THCMP_ARANGE3_Msk (0x01UL << ADCHS_STATUS1_THCMP_ARANGE3_Pos) /*!< ADCHS STATUS1: THCMP_ARANGE3 Mask */ +#define ADCHS_STATUS1_THCMP_DCROSS3_Pos 17 /*!< ADCHS STATUS1: THCMP_DCROSS3 Position */ +#define ADCHS_STATUS1_THCMP_DCROSS3_Msk (0x01UL << ADCHS_STATUS1_THCMP_DCROSS3_Pos) /*!< ADCHS STATUS1: THCMP_DCROSS3 Mask */ +#define ADCHS_STATUS1_THCMP_UCROSS3_Pos 18 /*!< ADCHS STATUS1: THCMP_UCROSS3 Position */ +#define ADCHS_STATUS1_THCMP_UCROSS3_Msk (0x01UL << ADCHS_STATUS1_THCMP_UCROSS3_Pos) /*!< ADCHS STATUS1: THCMP_UCROSS3 Mask */ +#define ADCHS_STATUS1_OVERRUN_3_Pos 19 /*!< ADCHS STATUS1: OVERRUN_3 Position */ +#define ADCHS_STATUS1_OVERRUN_3_Msk (0x01UL << ADCHS_STATUS1_OVERRUN_3_Pos) /*!< ADCHS STATUS1: OVERRUN_3 Mask */ +#define ADCHS_STATUS1_THCMP_BRANGE4_Pos 20 /*!< ADCHS STATUS1: THCMP_BRANGE4 Position */ +#define ADCHS_STATUS1_THCMP_BRANGE4_Msk (0x01UL << ADCHS_STATUS1_THCMP_BRANGE4_Pos) /*!< ADCHS STATUS1: THCMP_BRANGE4 Mask */ +#define ADCHS_STATUS1_THCMP_ARANGE4_Pos 21 /*!< ADCHS STATUS1: THCMP_ARANGE4 Position */ +#define ADCHS_STATUS1_THCMP_ARANGE4_Msk (0x01UL << ADCHS_STATUS1_THCMP_ARANGE4_Pos) /*!< ADCHS STATUS1: THCMP_ARANGE4 Mask */ +#define ADCHS_STATUS1_THCMP_DCROSS4_Pos 22 /*!< ADCHS STATUS1: THCMP_DCROSS4 Position */ +#define ADCHS_STATUS1_THCMP_DCROSS4_Msk (0x01UL << ADCHS_STATUS1_THCMP_DCROSS4_Pos) /*!< ADCHS STATUS1: THCMP_DCROSS4 Mask */ +#define ADCHS_STATUS1_THCMP_UCROSS4_Pos 23 /*!< ADCHS STATUS1: THCMP_UCROSS4 Position */ +#define ADCHS_STATUS1_THCMP_UCROSS4_Msk (0x01UL << ADCHS_STATUS1_THCMP_UCROSS4_Pos) /*!< ADCHS STATUS1: THCMP_UCROSS4 Mask */ +#define ADCHS_STATUS1_OVERRUN_4_Pos 24 /*!< ADCHS STATUS1: OVERRUN_4 Position */ +#define ADCHS_STATUS1_OVERRUN_4_Msk (0x01UL << ADCHS_STATUS1_OVERRUN_4_Pos) /*!< ADCHS STATUS1: OVERRUN_4 Mask */ +#define ADCHS_STATUS1_THCMP_BRANGE5_Pos 25 /*!< ADCHS STATUS1: THCMP_BRANGE5 Position */ +#define ADCHS_STATUS1_THCMP_BRANGE5_Msk (0x01UL << ADCHS_STATUS1_THCMP_BRANGE5_Pos) /*!< ADCHS STATUS1: THCMP_BRANGE5 Mask */ +#define ADCHS_STATUS1_THCMP_ARANGE5_Pos 26 /*!< ADCHS STATUS1: THCMP_ARANGE5 Position */ +#define ADCHS_STATUS1_THCMP_ARANGE5_Msk (0x01UL << ADCHS_STATUS1_THCMP_ARANGE5_Pos) /*!< ADCHS STATUS1: THCMP_ARANGE5 Mask */ +#define ADCHS_STATUS1_THCMP_DCROSS5_Pos 27 /*!< ADCHS STATUS1: THCMP_DCROSS5 Position */ +#define ADCHS_STATUS1_THCMP_DCROSS5_Msk (0x01UL << ADCHS_STATUS1_THCMP_DCROSS5_Pos) /*!< ADCHS STATUS1: THCMP_DCROSS5 Mask */ +#define ADCHS_STATUS1_THCMP_UCROSS5_Pos 28 /*!< ADCHS STATUS1: THCMP_UCROSS5 Position */ +#define ADCHS_STATUS1_THCMP_UCROSS5_Msk (0x01UL << ADCHS_STATUS1_THCMP_UCROSS5_Pos) /*!< ADCHS STATUS1: THCMP_UCROSS5 Mask */ +#define ADCHS_STATUS1_OVERRUN_5_Pos 29 /*!< ADCHS STATUS1: OVERRUN_5 Position */ +#define ADCHS_STATUS1_OVERRUN_5_Msk (0x01UL << ADCHS_STATUS1_OVERRUN_5_Pos) /*!< ADCHS STATUS1: OVERRUN_5 Mask */ + +/* ------------------------------- ADCHS_CLR_STAT1 ------------------------------ */ +#define ADCHS_CLR_STAT1_CSTAT1_Pos 0 /*!< ADCHS CLR_STAT1: CSTAT1 Position */ +#define ADCHS_CLR_STAT1_CSTAT1_Msk (0x3fffffffUL << ADCHS_CLR_STAT1_CSTAT1_Pos) /*!< ADCHS CLR_STAT1: CSTAT1 Mask */ + +/* ------------------------------- ADCHS_SET_STAT1 ------------------------------ */ +#define ADCHS_SET_STAT1_SSTAT1_Pos 0 /*!< ADCHS SET_STAT1: SSTAT1 Position */ +#define ADCHS_SET_STAT1_SSTAT1_Msk (0x3fffffffUL << ADCHS_SET_STAT1_SSTAT1_Pos) /*!< ADCHS SET_STAT1: SSTAT1 Mask */ + + +/* ================================================================================ */ +/* ================ struct 'GPIO_PORT' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- GPIO_PORT_B -------------------------------- */ +#define GPIO_PORT_B_PBYTE_Pos 0 /*!< GPIO_PORT B: PBYTE Position */ +#define GPIO_PORT_B_PBYTE_Msk (0x01UL << GPIO_PORT_B_PBYTE_Pos) /*!< GPIO_PORT B: PBYTE Mask */ + +/* --------------------------------- GPIO_PORT_W -------------------------------- */ +#define GPIO_PORT_W_PWORD_Pos 0 /*!< GPIO_PORT W: PWORD Position */ +#define GPIO_PORT_W_PWORD_Msk (0xffffffffUL << GPIO_PORT_W_PWORD_Pos) /*!< GPIO_PORT W: PWORD Mask */ + +/* -------------------------------- GPIO_PORT_DIR ------------------------------- */ +#define GPIO_PORT_DIR_DIRP0_Pos 0 /*!< GPIO_PORT DIR: DIRP0 Position */ +#define GPIO_PORT_DIR_DIRP0_Msk (0x01UL << GPIO_PORT_DIR_DIRP0_Pos) /*!< GPIO_PORT DIR: DIRP0 Mask */ +#define GPIO_PORT_DIR_DIRP1_Pos 1 /*!< GPIO_PORT DIR: DIRP1 Position */ +#define GPIO_PORT_DIR_DIRP1_Msk (0x01UL << GPIO_PORT_DIR_DIRP1_Pos) /*!< GPIO_PORT DIR: DIRP1 Mask */ +#define GPIO_PORT_DIR_DIRP2_Pos 2 /*!< GPIO_PORT DIR: DIRP2 Position */ +#define GPIO_PORT_DIR_DIRP2_Msk (0x01UL << GPIO_PORT_DIR_DIRP2_Pos) /*!< GPIO_PORT DIR: DIRP2 Mask */ +#define GPIO_PORT_DIR_DIRP3_Pos 3 /*!< GPIO_PORT DIR: DIRP3 Position */ +#define GPIO_PORT_DIR_DIRP3_Msk (0x01UL << GPIO_PORT_DIR_DIRP3_Pos) /*!< GPIO_PORT DIR: DIRP3 Mask */ +#define GPIO_PORT_DIR_DIRP4_Pos 4 /*!< GPIO_PORT DIR: DIRP4 Position */ +#define GPIO_PORT_DIR_DIRP4_Msk (0x01UL << GPIO_PORT_DIR_DIRP4_Pos) /*!< GPIO_PORT DIR: DIRP4 Mask */ +#define GPIO_PORT_DIR_DIRP5_Pos 5 /*!< GPIO_PORT DIR: DIRP5 Position */ +#define GPIO_PORT_DIR_DIRP5_Msk (0x01UL << GPIO_PORT_DIR_DIRP5_Pos) /*!< GPIO_PORT DIR: DIRP5 Mask */ +#define GPIO_PORT_DIR_DIRP6_Pos 6 /*!< GPIO_PORT DIR: DIRP6 Position */ +#define GPIO_PORT_DIR_DIRP6_Msk (0x01UL << GPIO_PORT_DIR_DIRP6_Pos) /*!< GPIO_PORT DIR: DIRP6 Mask */ +#define GPIO_PORT_DIR_DIRP7_Pos 7 /*!< GPIO_PORT DIR: DIRP7 Position */ +#define GPIO_PORT_DIR_DIRP7_Msk (0x01UL << GPIO_PORT_DIR_DIRP7_Pos) /*!< GPIO_PORT DIR: DIRP7 Mask */ +#define GPIO_PORT_DIR_DIRP8_Pos 8 /*!< GPIO_PORT DIR: DIRP8 Position */ +#define GPIO_PORT_DIR_DIRP8_Msk (0x01UL << GPIO_PORT_DIR_DIRP8_Pos) /*!< GPIO_PORT DIR: DIRP8 Mask */ +#define GPIO_PORT_DIR_DIRP9_Pos 9 /*!< GPIO_PORT DIR: DIRP9 Position */ +#define GPIO_PORT_DIR_DIRP9_Msk (0x01UL << GPIO_PORT_DIR_DIRP9_Pos) /*!< GPIO_PORT DIR: DIRP9 Mask */ +#define GPIO_PORT_DIR_DIRP10_Pos 10 /*!< GPIO_PORT DIR: DIRP10 Position */ +#define GPIO_PORT_DIR_DIRP10_Msk (0x01UL << GPIO_PORT_DIR_DIRP10_Pos) /*!< GPIO_PORT DIR: DIRP10 Mask */ +#define GPIO_PORT_DIR_DIRP11_Pos 11 /*!< GPIO_PORT DIR: DIRP11 Position */ +#define GPIO_PORT_DIR_DIRP11_Msk (0x01UL << GPIO_PORT_DIR_DIRP11_Pos) /*!< GPIO_PORT DIR: DIRP11 Mask */ +#define GPIO_PORT_DIR_DIRP12_Pos 12 /*!< GPIO_PORT DIR: DIRP12 Position */ +#define GPIO_PORT_DIR_DIRP12_Msk (0x01UL << GPIO_PORT_DIR_DIRP12_Pos) /*!< GPIO_PORT DIR: DIRP12 Mask */ +#define GPIO_PORT_DIR_DIRP13_Pos 13 /*!< GPIO_PORT DIR: DIRP13 Position */ +#define GPIO_PORT_DIR_DIRP13_Msk (0x01UL << GPIO_PORT_DIR_DIRP13_Pos) /*!< GPIO_PORT DIR: DIRP13 Mask */ +#define GPIO_PORT_DIR_DIRP14_Pos 14 /*!< GPIO_PORT DIR: DIRP14 Position */ +#define GPIO_PORT_DIR_DIRP14_Msk (0x01UL << GPIO_PORT_DIR_DIRP14_Pos) /*!< GPIO_PORT DIR: DIRP14 Mask */ +#define GPIO_PORT_DIR_DIRP15_Pos 15 /*!< GPIO_PORT DIR: DIRP15 Position */ +#define GPIO_PORT_DIR_DIRP15_Msk (0x01UL << GPIO_PORT_DIR_DIRP15_Pos) /*!< GPIO_PORT DIR: DIRP15 Mask */ +#define GPIO_PORT_DIR_DIRP16_Pos 16 /*!< GPIO_PORT DIR: DIRP16 Position */ +#define GPIO_PORT_DIR_DIRP16_Msk (0x01UL << GPIO_PORT_DIR_DIRP16_Pos) /*!< GPIO_PORT DIR: DIRP16 Mask */ +#define GPIO_PORT_DIR_DIRP17_Pos 17 /*!< GPIO_PORT DIR: DIRP17 Position */ +#define GPIO_PORT_DIR_DIRP17_Msk (0x01UL << GPIO_PORT_DIR_DIRP17_Pos) /*!< GPIO_PORT DIR: DIRP17 Mask */ +#define GPIO_PORT_DIR_DIRP18_Pos 18 /*!< GPIO_PORT DIR: DIRP18 Position */ +#define GPIO_PORT_DIR_DIRP18_Msk (0x01UL << GPIO_PORT_DIR_DIRP18_Pos) /*!< GPIO_PORT DIR: DIRP18 Mask */ +#define GPIO_PORT_DIR_DIRP19_Pos 19 /*!< GPIO_PORT DIR: DIRP19 Position */ +#define GPIO_PORT_DIR_DIRP19_Msk (0x01UL << GPIO_PORT_DIR_DIRP19_Pos) /*!< GPIO_PORT DIR: DIRP19 Mask */ +#define GPIO_PORT_DIR_DIRP20_Pos 20 /*!< GPIO_PORT DIR: DIRP20 Position */ +#define GPIO_PORT_DIR_DIRP20_Msk (0x01UL << GPIO_PORT_DIR_DIRP20_Pos) /*!< GPIO_PORT DIR: DIRP20 Mask */ +#define GPIO_PORT_DIR_DIRP21_Pos 21 /*!< GPIO_PORT DIR: DIRP21 Position */ +#define GPIO_PORT_DIR_DIRP21_Msk (0x01UL << GPIO_PORT_DIR_DIRP21_Pos) /*!< GPIO_PORT DIR: DIRP21 Mask */ +#define GPIO_PORT_DIR_DIRP22_Pos 22 /*!< GPIO_PORT DIR: DIRP22 Position */ +#define GPIO_PORT_DIR_DIRP22_Msk (0x01UL << GPIO_PORT_DIR_DIRP22_Pos) /*!< GPIO_PORT DIR: DIRP22 Mask */ +#define GPIO_PORT_DIR_DIRP23_Pos 23 /*!< GPIO_PORT DIR: DIRP23 Position */ +#define GPIO_PORT_DIR_DIRP23_Msk (0x01UL << GPIO_PORT_DIR_DIRP23_Pos) /*!< GPIO_PORT DIR: DIRP23 Mask */ +#define GPIO_PORT_DIR_DIRP24_Pos 24 /*!< GPIO_PORT DIR: DIRP24 Position */ +#define GPIO_PORT_DIR_DIRP24_Msk (0x01UL << GPIO_PORT_DIR_DIRP24_Pos) /*!< GPIO_PORT DIR: DIRP24 Mask */ +#define GPIO_PORT_DIR_DIRP25_Pos 25 /*!< GPIO_PORT DIR: DIRP25 Position */ +#define GPIO_PORT_DIR_DIRP25_Msk (0x01UL << GPIO_PORT_DIR_DIRP25_Pos) /*!< GPIO_PORT DIR: DIRP25 Mask */ +#define GPIO_PORT_DIR_DIRP26_Pos 26 /*!< GPIO_PORT DIR: DIRP26 Position */ +#define GPIO_PORT_DIR_DIRP26_Msk (0x01UL << GPIO_PORT_DIR_DIRP26_Pos) /*!< GPIO_PORT DIR: DIRP26 Mask */ +#define GPIO_PORT_DIR_DIRP27_Pos 27 /*!< GPIO_PORT DIR: DIRP27 Position */ +#define GPIO_PORT_DIR_DIRP27_Msk (0x01UL << GPIO_PORT_DIR_DIRP27_Pos) /*!< GPIO_PORT DIR: DIRP27 Mask */ +#define GPIO_PORT_DIR_DIRP28_Pos 28 /*!< GPIO_PORT DIR: DIRP28 Position */ +#define GPIO_PORT_DIR_DIRP28_Msk (0x01UL << GPIO_PORT_DIR_DIRP28_Pos) /*!< GPIO_PORT DIR: DIRP28 Mask */ +#define GPIO_PORT_DIR_DIRP29_Pos 29 /*!< GPIO_PORT DIR: DIRP29 Position */ +#define GPIO_PORT_DIR_DIRP29_Msk (0x01UL << GPIO_PORT_DIR_DIRP29_Pos) /*!< GPIO_PORT DIR: DIRP29 Mask */ +#define GPIO_PORT_DIR_DIRP30_Pos 30 /*!< GPIO_PORT DIR: DIRP30 Position */ +#define GPIO_PORT_DIR_DIRP30_Msk (0x01UL << GPIO_PORT_DIR_DIRP30_Pos) /*!< GPIO_PORT DIR: DIRP30 Mask */ +#define GPIO_PORT_DIR_DIRP31_Pos 31 /*!< GPIO_PORT DIR: DIRP31 Position */ +#define GPIO_PORT_DIR_DIRP31_Msk (0x01UL << GPIO_PORT_DIR_DIRP31_Pos) /*!< GPIO_PORT DIR: DIRP31 Mask */ + +/* ------------------------------- GPIO_PORT_MASK ------------------------------- */ +#define GPIO_PORT_MASK_MASKP0_Pos 0 /*!< GPIO_PORT MASK: MASKP0 Position */ +#define GPIO_PORT_MASK_MASKP0_Msk (0x01UL << GPIO_PORT_MASK_MASKP0_Pos) /*!< GPIO_PORT MASK: MASKP0 Mask */ +#define GPIO_PORT_MASK_MASKP1_Pos 1 /*!< GPIO_PORT MASK: MASKP1 Position */ +#define GPIO_PORT_MASK_MASKP1_Msk (0x01UL << GPIO_PORT_MASK_MASKP1_Pos) /*!< GPIO_PORT MASK: MASKP1 Mask */ +#define GPIO_PORT_MASK_MASKP2_Pos 2 /*!< GPIO_PORT MASK: MASKP2 Position */ +#define GPIO_PORT_MASK_MASKP2_Msk (0x01UL << GPIO_PORT_MASK_MASKP2_Pos) /*!< GPIO_PORT MASK: MASKP2 Mask */ +#define GPIO_PORT_MASK_MASKP3_Pos 3 /*!< GPIO_PORT MASK: MASKP3 Position */ +#define GPIO_PORT_MASK_MASKP3_Msk (0x01UL << GPIO_PORT_MASK_MASKP3_Pos) /*!< GPIO_PORT MASK: MASKP3 Mask */ +#define GPIO_PORT_MASK_MASKP4_Pos 4 /*!< GPIO_PORT MASK: MASKP4 Position */ +#define GPIO_PORT_MASK_MASKP4_Msk (0x01UL << GPIO_PORT_MASK_MASKP4_Pos) /*!< GPIO_PORT MASK: MASKP4 Mask */ +#define GPIO_PORT_MASK_MASKP5_Pos 5 /*!< GPIO_PORT MASK: MASKP5 Position */ +#define GPIO_PORT_MASK_MASKP5_Msk (0x01UL << GPIO_PORT_MASK_MASKP5_Pos) /*!< GPIO_PORT MASK: MASKP5 Mask */ +#define GPIO_PORT_MASK_MASKP6_Pos 6 /*!< GPIO_PORT MASK: MASKP6 Position */ +#define GPIO_PORT_MASK_MASKP6_Msk (0x01UL << GPIO_PORT_MASK_MASKP6_Pos) /*!< GPIO_PORT MASK: MASKP6 Mask */ +#define GPIO_PORT_MASK_MASKP7_Pos 7 /*!< GPIO_PORT MASK: MASKP7 Position */ +#define GPIO_PORT_MASK_MASKP7_Msk (0x01UL << GPIO_PORT_MASK_MASKP7_Pos) /*!< GPIO_PORT MASK: MASKP7 Mask */ +#define GPIO_PORT_MASK_MASKP8_Pos 8 /*!< GPIO_PORT MASK: MASKP8 Position */ +#define GPIO_PORT_MASK_MASKP8_Msk (0x01UL << GPIO_PORT_MASK_MASKP8_Pos) /*!< GPIO_PORT MASK: MASKP8 Mask */ +#define GPIO_PORT_MASK_MASKP9_Pos 9 /*!< GPIO_PORT MASK: MASKP9 Position */ +#define GPIO_PORT_MASK_MASKP9_Msk (0x01UL << GPIO_PORT_MASK_MASKP9_Pos) /*!< GPIO_PORT MASK: MASKP9 Mask */ +#define GPIO_PORT_MASK_MASKP10_Pos 10 /*!< GPIO_PORT MASK: MASKP10 Position */ +#define GPIO_PORT_MASK_MASKP10_Msk (0x01UL << GPIO_PORT_MASK_MASKP10_Pos) /*!< GPIO_PORT MASK: MASKP10 Mask */ +#define GPIO_PORT_MASK_MASKP11_Pos 11 /*!< GPIO_PORT MASK: MASKP11 Position */ +#define GPIO_PORT_MASK_MASKP11_Msk (0x01UL << GPIO_PORT_MASK_MASKP11_Pos) /*!< GPIO_PORT MASK: MASKP11 Mask */ +#define GPIO_PORT_MASK_MASKP12_Pos 12 /*!< GPIO_PORT MASK: MASKP12 Position */ +#define GPIO_PORT_MASK_MASKP12_Msk (0x01UL << GPIO_PORT_MASK_MASKP12_Pos) /*!< GPIO_PORT MASK: MASKP12 Mask */ +#define GPIO_PORT_MASK_MASKP13_Pos 13 /*!< GPIO_PORT MASK: MASKP13 Position */ +#define GPIO_PORT_MASK_MASKP13_Msk (0x01UL << GPIO_PORT_MASK_MASKP13_Pos) /*!< GPIO_PORT MASK: MASKP13 Mask */ +#define GPIO_PORT_MASK_MASKP14_Pos 14 /*!< GPIO_PORT MASK: MASKP14 Position */ +#define GPIO_PORT_MASK_MASKP14_Msk (0x01UL << GPIO_PORT_MASK_MASKP14_Pos) /*!< GPIO_PORT MASK: MASKP14 Mask */ +#define GPIO_PORT_MASK_MASKP15_Pos 15 /*!< GPIO_PORT MASK: MASKP15 Position */ +#define GPIO_PORT_MASK_MASKP15_Msk (0x01UL << GPIO_PORT_MASK_MASKP15_Pos) /*!< GPIO_PORT MASK: MASKP15 Mask */ +#define GPIO_PORT_MASK_MASKP16_Pos 16 /*!< GPIO_PORT MASK: MASKP16 Position */ +#define GPIO_PORT_MASK_MASKP16_Msk (0x01UL << GPIO_PORT_MASK_MASKP16_Pos) /*!< GPIO_PORT MASK: MASKP16 Mask */ +#define GPIO_PORT_MASK_MASKP17_Pos 17 /*!< GPIO_PORT MASK: MASKP17 Position */ +#define GPIO_PORT_MASK_MASKP17_Msk (0x01UL << GPIO_PORT_MASK_MASKP17_Pos) /*!< GPIO_PORT MASK: MASKP17 Mask */ +#define GPIO_PORT_MASK_MASKP18_Pos 18 /*!< GPIO_PORT MASK: MASKP18 Position */ +#define GPIO_PORT_MASK_MASKP18_Msk (0x01UL << GPIO_PORT_MASK_MASKP18_Pos) /*!< GPIO_PORT MASK: MASKP18 Mask */ +#define GPIO_PORT_MASK_MASKP19_Pos 19 /*!< GPIO_PORT MASK: MASKP19 Position */ +#define GPIO_PORT_MASK_MASKP19_Msk (0x01UL << GPIO_PORT_MASK_MASKP19_Pos) /*!< GPIO_PORT MASK: MASKP19 Mask */ +#define GPIO_PORT_MASK_MASKP20_Pos 20 /*!< GPIO_PORT MASK: MASKP20 Position */ +#define GPIO_PORT_MASK_MASKP20_Msk (0x01UL << GPIO_PORT_MASK_MASKP20_Pos) /*!< GPIO_PORT MASK: MASKP20 Mask */ +#define GPIO_PORT_MASK_MASKP21_Pos 21 /*!< GPIO_PORT MASK: MASKP21 Position */ +#define GPIO_PORT_MASK_MASKP21_Msk (0x01UL << GPIO_PORT_MASK_MASKP21_Pos) /*!< GPIO_PORT MASK: MASKP21 Mask */ +#define GPIO_PORT_MASK_MASKP22_Pos 22 /*!< GPIO_PORT MASK: MASKP22 Position */ +#define GPIO_PORT_MASK_MASKP22_Msk (0x01UL << GPIO_PORT_MASK_MASKP22_Pos) /*!< GPIO_PORT MASK: MASKP22 Mask */ +#define GPIO_PORT_MASK_MASKP23_Pos 23 /*!< GPIO_PORT MASK: MASKP23 Position */ +#define GPIO_PORT_MASK_MASKP23_Msk (0x01UL << GPIO_PORT_MASK_MASKP23_Pos) /*!< GPIO_PORT MASK: MASKP23 Mask */ +#define GPIO_PORT_MASK_MASKP24_Pos 24 /*!< GPIO_PORT MASK: MASKP24 Position */ +#define GPIO_PORT_MASK_MASKP24_Msk (0x01UL << GPIO_PORT_MASK_MASKP24_Pos) /*!< GPIO_PORT MASK: MASKP24 Mask */ +#define GPIO_PORT_MASK_MASKP25_Pos 25 /*!< GPIO_PORT MASK: MASKP25 Position */ +#define GPIO_PORT_MASK_MASKP25_Msk (0x01UL << GPIO_PORT_MASK_MASKP25_Pos) /*!< GPIO_PORT MASK: MASKP25 Mask */ +#define GPIO_PORT_MASK_MASKP26_Pos 26 /*!< GPIO_PORT MASK: MASKP26 Position */ +#define GPIO_PORT_MASK_MASKP26_Msk (0x01UL << GPIO_PORT_MASK_MASKP26_Pos) /*!< GPIO_PORT MASK: MASKP26 Mask */ +#define GPIO_PORT_MASK_MASKP27_Pos 27 /*!< GPIO_PORT MASK: MASKP27 Position */ +#define GPIO_PORT_MASK_MASKP27_Msk (0x01UL << GPIO_PORT_MASK_MASKP27_Pos) /*!< GPIO_PORT MASK: MASKP27 Mask */ +#define GPIO_PORT_MASK_MASKP28_Pos 28 /*!< GPIO_PORT MASK: MASKP28 Position */ +#define GPIO_PORT_MASK_MASKP28_Msk (0x01UL << GPIO_PORT_MASK_MASKP28_Pos) /*!< GPIO_PORT MASK: MASKP28 Mask */ +#define GPIO_PORT_MASK_MASKP29_Pos 29 /*!< GPIO_PORT MASK: MASKP29 Position */ +#define GPIO_PORT_MASK_MASKP29_Msk (0x01UL << GPIO_PORT_MASK_MASKP29_Pos) /*!< GPIO_PORT MASK: MASKP29 Mask */ +#define GPIO_PORT_MASK_MASKP30_Pos 30 /*!< GPIO_PORT MASK: MASKP30 Position */ +#define GPIO_PORT_MASK_MASKP30_Msk (0x01UL << GPIO_PORT_MASK_MASKP30_Pos) /*!< GPIO_PORT MASK: MASKP30 Mask */ +#define GPIO_PORT_MASK_MASKP31_Pos 31 /*!< GPIO_PORT MASK: MASKP31 Position */ +#define GPIO_PORT_MASK_MASKP31_Msk (0x01UL << GPIO_PORT_MASK_MASKP31_Pos) /*!< GPIO_PORT MASK: MASKP31 Mask */ + +/* -------------------------------- GPIO_PORT_PIN ------------------------------- */ +#define GPIO_PORT_PIN_PORT0_Pos 0 /*!< GPIO_PORT PIN: PORT0 Position */ +#define GPIO_PORT_PIN_PORT0_Msk (0x01UL << GPIO_PORT_PIN_PORT0_Pos) /*!< GPIO_PORT PIN: PORT0 Mask */ +#define GPIO_PORT_PIN_PORT1_Pos 1 /*!< GPIO_PORT PIN: PORT1 Position */ +#define GPIO_PORT_PIN_PORT1_Msk (0x01UL << GPIO_PORT_PIN_PORT1_Pos) /*!< GPIO_PORT PIN: PORT1 Mask */ +#define GPIO_PORT_PIN_PORT2_Pos 2 /*!< GPIO_PORT PIN: PORT2 Position */ +#define GPIO_PORT_PIN_PORT2_Msk (0x01UL << GPIO_PORT_PIN_PORT2_Pos) /*!< GPIO_PORT PIN: PORT2 Mask */ +#define GPIO_PORT_PIN_PORT3_Pos 3 /*!< GPIO_PORT PIN: PORT3 Position */ +#define GPIO_PORT_PIN_PORT3_Msk (0x01UL << GPIO_PORT_PIN_PORT3_Pos) /*!< GPIO_PORT PIN: PORT3 Mask */ +#define GPIO_PORT_PIN_PORT4_Pos 4 /*!< GPIO_PORT PIN: PORT4 Position */ +#define GPIO_PORT_PIN_PORT4_Msk (0x01UL << GPIO_PORT_PIN_PORT4_Pos) /*!< GPIO_PORT PIN: PORT4 Mask */ +#define GPIO_PORT_PIN_PORT5_Pos 5 /*!< GPIO_PORT PIN: PORT5 Position */ +#define GPIO_PORT_PIN_PORT5_Msk (0x01UL << GPIO_PORT_PIN_PORT5_Pos) /*!< GPIO_PORT PIN: PORT5 Mask */ +#define GPIO_PORT_PIN_PORT6_Pos 6 /*!< GPIO_PORT PIN: PORT6 Position */ +#define GPIO_PORT_PIN_PORT6_Msk (0x01UL << GPIO_PORT_PIN_PORT6_Pos) /*!< GPIO_PORT PIN: PORT6 Mask */ +#define GPIO_PORT_PIN_PORT7_Pos 7 /*!< GPIO_PORT PIN: PORT7 Position */ +#define GPIO_PORT_PIN_PORT7_Msk (0x01UL << GPIO_PORT_PIN_PORT7_Pos) /*!< GPIO_PORT PIN: PORT7 Mask */ +#define GPIO_PORT_PIN_PORT8_Pos 8 /*!< GPIO_PORT PIN: PORT8 Position */ +#define GPIO_PORT_PIN_PORT8_Msk (0x01UL << GPIO_PORT_PIN_PORT8_Pos) /*!< GPIO_PORT PIN: PORT8 Mask */ +#define GPIO_PORT_PIN_PORT9_Pos 9 /*!< GPIO_PORT PIN: PORT9 Position */ +#define GPIO_PORT_PIN_PORT9_Msk (0x01UL << GPIO_PORT_PIN_PORT9_Pos) /*!< GPIO_PORT PIN: PORT9 Mask */ +#define GPIO_PORT_PIN_PORT10_Pos 10 /*!< GPIO_PORT PIN: PORT10 Position */ +#define GPIO_PORT_PIN_PORT10_Msk (0x01UL << GPIO_PORT_PIN_PORT10_Pos) /*!< GPIO_PORT PIN: PORT10 Mask */ +#define GPIO_PORT_PIN_PORT11_Pos 11 /*!< GPIO_PORT PIN: PORT11 Position */ +#define GPIO_PORT_PIN_PORT11_Msk (0x01UL << GPIO_PORT_PIN_PORT11_Pos) /*!< GPIO_PORT PIN: PORT11 Mask */ +#define GPIO_PORT_PIN_PORT12_Pos 12 /*!< GPIO_PORT PIN: PORT12 Position */ +#define GPIO_PORT_PIN_PORT12_Msk (0x01UL << GPIO_PORT_PIN_PORT12_Pos) /*!< GPIO_PORT PIN: PORT12 Mask */ +#define GPIO_PORT_PIN_PORT13_Pos 13 /*!< GPIO_PORT PIN: PORT13 Position */ +#define GPIO_PORT_PIN_PORT13_Msk (0x01UL << GPIO_PORT_PIN_PORT13_Pos) /*!< GPIO_PORT PIN: PORT13 Mask */ +#define GPIO_PORT_PIN_PORT14_Pos 14 /*!< GPIO_PORT PIN: PORT14 Position */ +#define GPIO_PORT_PIN_PORT14_Msk (0x01UL << GPIO_PORT_PIN_PORT14_Pos) /*!< GPIO_PORT PIN: PORT14 Mask */ +#define GPIO_PORT_PIN_PORT15_Pos 15 /*!< GPIO_PORT PIN: PORT15 Position */ +#define GPIO_PORT_PIN_PORT15_Msk (0x01UL << GPIO_PORT_PIN_PORT15_Pos) /*!< GPIO_PORT PIN: PORT15 Mask */ +#define GPIO_PORT_PIN_PORT16_Pos 16 /*!< GPIO_PORT PIN: PORT16 Position */ +#define GPIO_PORT_PIN_PORT16_Msk (0x01UL << GPIO_PORT_PIN_PORT16_Pos) /*!< GPIO_PORT PIN: PORT16 Mask */ +#define GPIO_PORT_PIN_PORT17_Pos 17 /*!< GPIO_PORT PIN: PORT17 Position */ +#define GPIO_PORT_PIN_PORT17_Msk (0x01UL << GPIO_PORT_PIN_PORT17_Pos) /*!< GPIO_PORT PIN: PORT17 Mask */ +#define GPIO_PORT_PIN_PORT18_Pos 18 /*!< GPIO_PORT PIN: PORT18 Position */ +#define GPIO_PORT_PIN_PORT18_Msk (0x01UL << GPIO_PORT_PIN_PORT18_Pos) /*!< GPIO_PORT PIN: PORT18 Mask */ +#define GPIO_PORT_PIN_PORT19_Pos 19 /*!< GPIO_PORT PIN: PORT19 Position */ +#define GPIO_PORT_PIN_PORT19_Msk (0x01UL << GPIO_PORT_PIN_PORT19_Pos) /*!< GPIO_PORT PIN: PORT19 Mask */ +#define GPIO_PORT_PIN_PORT20_Pos 20 /*!< GPIO_PORT PIN: PORT20 Position */ +#define GPIO_PORT_PIN_PORT20_Msk (0x01UL << GPIO_PORT_PIN_PORT20_Pos) /*!< GPIO_PORT PIN: PORT20 Mask */ +#define GPIO_PORT_PIN_PORT21_Pos 21 /*!< GPIO_PORT PIN: PORT21 Position */ +#define GPIO_PORT_PIN_PORT21_Msk (0x01UL << GPIO_PORT_PIN_PORT21_Pos) /*!< GPIO_PORT PIN: PORT21 Mask */ +#define GPIO_PORT_PIN_PORT22_Pos 22 /*!< GPIO_PORT PIN: PORT22 Position */ +#define GPIO_PORT_PIN_PORT22_Msk (0x01UL << GPIO_PORT_PIN_PORT22_Pos) /*!< GPIO_PORT PIN: PORT22 Mask */ +#define GPIO_PORT_PIN_PORT23_Pos 23 /*!< GPIO_PORT PIN: PORT23 Position */ +#define GPIO_PORT_PIN_PORT23_Msk (0x01UL << GPIO_PORT_PIN_PORT23_Pos) /*!< GPIO_PORT PIN: PORT23 Mask */ +#define GPIO_PORT_PIN_PORT24_Pos 24 /*!< GPIO_PORT PIN: PORT24 Position */ +#define GPIO_PORT_PIN_PORT24_Msk (0x01UL << GPIO_PORT_PIN_PORT24_Pos) /*!< GPIO_PORT PIN: PORT24 Mask */ +#define GPIO_PORT_PIN_PORT25_Pos 25 /*!< GPIO_PORT PIN: PORT25 Position */ +#define GPIO_PORT_PIN_PORT25_Msk (0x01UL << GPIO_PORT_PIN_PORT25_Pos) /*!< GPIO_PORT PIN: PORT25 Mask */ +#define GPIO_PORT_PIN_PORT26_Pos 26 /*!< GPIO_PORT PIN: PORT26 Position */ +#define GPIO_PORT_PIN_PORT26_Msk (0x01UL << GPIO_PORT_PIN_PORT26_Pos) /*!< GPIO_PORT PIN: PORT26 Mask */ +#define GPIO_PORT_PIN_PORT27_Pos 27 /*!< GPIO_PORT PIN: PORT27 Position */ +#define GPIO_PORT_PIN_PORT27_Msk (0x01UL << GPIO_PORT_PIN_PORT27_Pos) /*!< GPIO_PORT PIN: PORT27 Mask */ +#define GPIO_PORT_PIN_PORT28_Pos 28 /*!< GPIO_PORT PIN: PORT28 Position */ +#define GPIO_PORT_PIN_PORT28_Msk (0x01UL << GPIO_PORT_PIN_PORT28_Pos) /*!< GPIO_PORT PIN: PORT28 Mask */ +#define GPIO_PORT_PIN_PORT29_Pos 29 /*!< GPIO_PORT PIN: PORT29 Position */ +#define GPIO_PORT_PIN_PORT29_Msk (0x01UL << GPIO_PORT_PIN_PORT29_Pos) /*!< GPIO_PORT PIN: PORT29 Mask */ +#define GPIO_PORT_PIN_PORT30_Pos 30 /*!< GPIO_PORT PIN: PORT30 Position */ +#define GPIO_PORT_PIN_PORT30_Msk (0x01UL << GPIO_PORT_PIN_PORT30_Pos) /*!< GPIO_PORT PIN: PORT30 Mask */ +#define GPIO_PORT_PIN_PORT31_Pos 31 /*!< GPIO_PORT PIN: PORT31 Position */ +#define GPIO_PORT_PIN_PORT31_Msk (0x01UL << GPIO_PORT_PIN_PORT31_Pos) /*!< GPIO_PORT PIN: PORT31 Mask */ + +/* ------------------------------- GPIO_PORT_MPIN ------------------------------- */ +#define GPIO_PORT_MPIN_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN: MPORTP0 Position */ +#define GPIO_PORT_MPIN_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP0_Pos) /*!< GPIO_PORT MPIN: MPORTP0 Mask */ +#define GPIO_PORT_MPIN_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN: MPORTP1 Position */ +#define GPIO_PORT_MPIN_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP1_Pos) /*!< GPIO_PORT MPIN: MPORTP1 Mask */ +#define GPIO_PORT_MPIN_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN: MPORTP2 Position */ +#define GPIO_PORT_MPIN_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP2_Pos) /*!< GPIO_PORT MPIN: MPORTP2 Mask */ +#define GPIO_PORT_MPIN_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN: MPORTP3 Position */ +#define GPIO_PORT_MPIN_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP3_Pos) /*!< GPIO_PORT MPIN: MPORTP3 Mask */ +#define GPIO_PORT_MPIN_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN: MPORTP4 Position */ +#define GPIO_PORT_MPIN_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP4_Pos) /*!< GPIO_PORT MPIN: MPORTP4 Mask */ +#define GPIO_PORT_MPIN_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN: MPORTP5 Position */ +#define GPIO_PORT_MPIN_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP5_Pos) /*!< GPIO_PORT MPIN: MPORTP5 Mask */ +#define GPIO_PORT_MPIN_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN: MPORTP6 Position */ +#define GPIO_PORT_MPIN_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP6_Pos) /*!< GPIO_PORT MPIN: MPORTP6 Mask */ +#define GPIO_PORT_MPIN_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN: MPORTP7 Position */ +#define GPIO_PORT_MPIN_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP7_Pos) /*!< GPIO_PORT MPIN: MPORTP7 Mask */ +#define GPIO_PORT_MPIN_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN: MPORTP8 Position */ +#define GPIO_PORT_MPIN_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP8_Pos) /*!< GPIO_PORT MPIN: MPORTP8 Mask */ +#define GPIO_PORT_MPIN_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN: MPORTP9 Position */ +#define GPIO_PORT_MPIN_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP9_Pos) /*!< GPIO_PORT MPIN: MPORTP9 Mask */ +#define GPIO_PORT_MPIN_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN: MPORTP10 Position */ +#define GPIO_PORT_MPIN_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP10_Pos) /*!< GPIO_PORT MPIN: MPORTP10 Mask */ +#define GPIO_PORT_MPIN_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN: MPORTP11 Position */ +#define GPIO_PORT_MPIN_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP11_Pos) /*!< GPIO_PORT MPIN: MPORTP11 Mask */ +#define GPIO_PORT_MPIN_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN: MPORTP12 Position */ +#define GPIO_PORT_MPIN_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP12_Pos) /*!< GPIO_PORT MPIN: MPORTP12 Mask */ +#define GPIO_PORT_MPIN_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN: MPORTP13 Position */ +#define GPIO_PORT_MPIN_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP13_Pos) /*!< GPIO_PORT MPIN: MPORTP13 Mask */ +#define GPIO_PORT_MPIN_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN: MPORTP14 Position */ +#define GPIO_PORT_MPIN_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP14_Pos) /*!< GPIO_PORT MPIN: MPORTP14 Mask */ +#define GPIO_PORT_MPIN_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN: MPORTP15 Position */ +#define GPIO_PORT_MPIN_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP15_Pos) /*!< GPIO_PORT MPIN: MPORTP15 Mask */ +#define GPIO_PORT_MPIN_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN: MPORTP16 Position */ +#define GPIO_PORT_MPIN_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP16_Pos) /*!< GPIO_PORT MPIN: MPORTP16 Mask */ +#define GPIO_PORT_MPIN_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN: MPORTP17 Position */ +#define GPIO_PORT_MPIN_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP17_Pos) /*!< GPIO_PORT MPIN: MPORTP17 Mask */ +#define GPIO_PORT_MPIN_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN: MPORTP18 Position */ +#define GPIO_PORT_MPIN_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP18_Pos) /*!< GPIO_PORT MPIN: MPORTP18 Mask */ +#define GPIO_PORT_MPIN_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN: MPORTP19 Position */ +#define GPIO_PORT_MPIN_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP19_Pos) /*!< GPIO_PORT MPIN: MPORTP19 Mask */ +#define GPIO_PORT_MPIN_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN: MPORTP20 Position */ +#define GPIO_PORT_MPIN_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP20_Pos) /*!< GPIO_PORT MPIN: MPORTP20 Mask */ +#define GPIO_PORT_MPIN_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN: MPORTP21 Position */ +#define GPIO_PORT_MPIN_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP21_Pos) /*!< GPIO_PORT MPIN: MPORTP21 Mask */ +#define GPIO_PORT_MPIN_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN: MPORTP22 Position */ +#define GPIO_PORT_MPIN_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP22_Pos) /*!< GPIO_PORT MPIN: MPORTP22 Mask */ +#define GPIO_PORT_MPIN_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN: MPORTP23 Position */ +#define GPIO_PORT_MPIN_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP23_Pos) /*!< GPIO_PORT MPIN: MPORTP23 Mask */ +#define GPIO_PORT_MPIN_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN: MPORTP24 Position */ +#define GPIO_PORT_MPIN_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP24_Pos) /*!< GPIO_PORT MPIN: MPORTP24 Mask */ +#define GPIO_PORT_MPIN_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN: MPORTP25 Position */ +#define GPIO_PORT_MPIN_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP25_Pos) /*!< GPIO_PORT MPIN: MPORTP25 Mask */ +#define GPIO_PORT_MPIN_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN: MPORTP26 Position */ +#define GPIO_PORT_MPIN_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP26_Pos) /*!< GPIO_PORT MPIN: MPORTP26 Mask */ +#define GPIO_PORT_MPIN_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN: MPORTP27 Position */ +#define GPIO_PORT_MPIN_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP27_Pos) /*!< GPIO_PORT MPIN: MPORTP27 Mask */ +#define GPIO_PORT_MPIN_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN: MPORTP28 Position */ +#define GPIO_PORT_MPIN_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP28_Pos) /*!< GPIO_PORT MPIN: MPORTP28 Mask */ +#define GPIO_PORT_MPIN_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN: MPORTP29 Position */ +#define GPIO_PORT_MPIN_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP29_Pos) /*!< GPIO_PORT MPIN: MPORTP29 Mask */ +#define GPIO_PORT_MPIN_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN: MPORTP30 Position */ +#define GPIO_PORT_MPIN_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP30_Pos) /*!< GPIO_PORT MPIN: MPORTP30 Mask */ +#define GPIO_PORT_MPIN_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN: MPORTP31 Position */ +#define GPIO_PORT_MPIN_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP31_Pos) /*!< GPIO_PORT MPIN: MPORTP31 Mask */ + +/* -------------------------------- GPIO_PORT_SET ------------------------------- */ +#define GPIO_PORT_SET_SETP0_Pos 0 /*!< GPIO_PORT SET: SETP0 Position */ +#define GPIO_PORT_SET_SETP0_Msk (0x01UL << GPIO_PORT_SET_SETP0_Pos) /*!< GPIO_PORT SET: SETP0 Mask */ +#define GPIO_PORT_SET_SETP1_Pos 1 /*!< GPIO_PORT SET: SETP1 Position */ +#define GPIO_PORT_SET_SETP1_Msk (0x01UL << GPIO_PORT_SET_SETP1_Pos) /*!< GPIO_PORT SET: SETP1 Mask */ +#define GPIO_PORT_SET_SETP2_Pos 2 /*!< GPIO_PORT SET: SETP2 Position */ +#define GPIO_PORT_SET_SETP2_Msk (0x01UL << GPIO_PORT_SET_SETP2_Pos) /*!< GPIO_PORT SET: SETP2 Mask */ +#define GPIO_PORT_SET_SETP3_Pos 3 /*!< GPIO_PORT SET: SETP3 Position */ +#define GPIO_PORT_SET_SETP3_Msk (0x01UL << GPIO_PORT_SET_SETP3_Pos) /*!< GPIO_PORT SET: SETP3 Mask */ +#define GPIO_PORT_SET_SETP4_Pos 4 /*!< GPIO_PORT SET: SETP4 Position */ +#define GPIO_PORT_SET_SETP4_Msk (0x01UL << GPIO_PORT_SET_SETP4_Pos) /*!< GPIO_PORT SET: SETP4 Mask */ +#define GPIO_PORT_SET_SETP5_Pos 5 /*!< GPIO_PORT SET: SETP5 Position */ +#define GPIO_PORT_SET_SETP5_Msk (0x01UL << GPIO_PORT_SET_SETP5_Pos) /*!< GPIO_PORT SET: SETP5 Mask */ +#define GPIO_PORT_SET_SETP6_Pos 6 /*!< GPIO_PORT SET: SETP6 Position */ +#define GPIO_PORT_SET_SETP6_Msk (0x01UL << GPIO_PORT_SET_SETP6_Pos) /*!< GPIO_PORT SET: SETP6 Mask */ +#define GPIO_PORT_SET_SETP7_Pos 7 /*!< GPIO_PORT SET: SETP7 Position */ +#define GPIO_PORT_SET_SETP7_Msk (0x01UL << GPIO_PORT_SET_SETP7_Pos) /*!< GPIO_PORT SET: SETP7 Mask */ +#define GPIO_PORT_SET_SETP8_Pos 8 /*!< GPIO_PORT SET: SETP8 Position */ +#define GPIO_PORT_SET_SETP8_Msk (0x01UL << GPIO_PORT_SET_SETP8_Pos) /*!< GPIO_PORT SET: SETP8 Mask */ +#define GPIO_PORT_SET_SETP9_Pos 9 /*!< GPIO_PORT SET: SETP9 Position */ +#define GPIO_PORT_SET_SETP9_Msk (0x01UL << GPIO_PORT_SET_SETP9_Pos) /*!< GPIO_PORT SET: SETP9 Mask */ +#define GPIO_PORT_SET_SETP10_Pos 10 /*!< GPIO_PORT SET: SETP10 Position */ +#define GPIO_PORT_SET_SETP10_Msk (0x01UL << GPIO_PORT_SET_SETP10_Pos) /*!< GPIO_PORT SET: SETP10 Mask */ +#define GPIO_PORT_SET_SETP11_Pos 11 /*!< GPIO_PORT SET: SETP11 Position */ +#define GPIO_PORT_SET_SETP11_Msk (0x01UL << GPIO_PORT_SET_SETP11_Pos) /*!< GPIO_PORT SET: SETP11 Mask */ +#define GPIO_PORT_SET_SETP12_Pos 12 /*!< GPIO_PORT SET: SETP12 Position */ +#define GPIO_PORT_SET_SETP12_Msk (0x01UL << GPIO_PORT_SET_SETP12_Pos) /*!< GPIO_PORT SET: SETP12 Mask */ +#define GPIO_PORT_SET_SETP13_Pos 13 /*!< GPIO_PORT SET: SETP13 Position */ +#define GPIO_PORT_SET_SETP13_Msk (0x01UL << GPIO_PORT_SET_SETP13_Pos) /*!< GPIO_PORT SET: SETP13 Mask */ +#define GPIO_PORT_SET_SETP14_Pos 14 /*!< GPIO_PORT SET: SETP14 Position */ +#define GPIO_PORT_SET_SETP14_Msk (0x01UL << GPIO_PORT_SET_SETP14_Pos) /*!< GPIO_PORT SET: SETP14 Mask */ +#define GPIO_PORT_SET_SETP15_Pos 15 /*!< GPIO_PORT SET: SETP15 Position */ +#define GPIO_PORT_SET_SETP15_Msk (0x01UL << GPIO_PORT_SET_SETP15_Pos) /*!< GPIO_PORT SET: SETP15 Mask */ +#define GPIO_PORT_SET_SETP16_Pos 16 /*!< GPIO_PORT SET: SETP16 Position */ +#define GPIO_PORT_SET_SETP16_Msk (0x01UL << GPIO_PORT_SET_SETP16_Pos) /*!< GPIO_PORT SET: SETP16 Mask */ +#define GPIO_PORT_SET_SETP17_Pos 17 /*!< GPIO_PORT SET: SETP17 Position */ +#define GPIO_PORT_SET_SETP17_Msk (0x01UL << GPIO_PORT_SET_SETP17_Pos) /*!< GPIO_PORT SET: SETP17 Mask */ +#define GPIO_PORT_SET_SETP18_Pos 18 /*!< GPIO_PORT SET: SETP18 Position */ +#define GPIO_PORT_SET_SETP18_Msk (0x01UL << GPIO_PORT_SET_SETP18_Pos) /*!< GPIO_PORT SET: SETP18 Mask */ +#define GPIO_PORT_SET_SETP19_Pos 19 /*!< GPIO_PORT SET: SETP19 Position */ +#define GPIO_PORT_SET_SETP19_Msk (0x01UL << GPIO_PORT_SET_SETP19_Pos) /*!< GPIO_PORT SET: SETP19 Mask */ +#define GPIO_PORT_SET_SETP20_Pos 20 /*!< GPIO_PORT SET: SETP20 Position */ +#define GPIO_PORT_SET_SETP20_Msk (0x01UL << GPIO_PORT_SET_SETP20_Pos) /*!< GPIO_PORT SET: SETP20 Mask */ +#define GPIO_PORT_SET_SETP21_Pos 21 /*!< GPIO_PORT SET: SETP21 Position */ +#define GPIO_PORT_SET_SETP21_Msk (0x01UL << GPIO_PORT_SET_SETP21_Pos) /*!< GPIO_PORT SET: SETP21 Mask */ +#define GPIO_PORT_SET_SETP22_Pos 22 /*!< GPIO_PORT SET: SETP22 Position */ +#define GPIO_PORT_SET_SETP22_Msk (0x01UL << GPIO_PORT_SET_SETP22_Pos) /*!< GPIO_PORT SET: SETP22 Mask */ +#define GPIO_PORT_SET_SETP23_Pos 23 /*!< GPIO_PORT SET: SETP23 Position */ +#define GPIO_PORT_SET_SETP23_Msk (0x01UL << GPIO_PORT_SET_SETP23_Pos) /*!< GPIO_PORT SET: SETP23 Mask */ +#define GPIO_PORT_SET_SETP24_Pos 24 /*!< GPIO_PORT SET: SETP24 Position */ +#define GPIO_PORT_SET_SETP24_Msk (0x01UL << GPIO_PORT_SET_SETP24_Pos) /*!< GPIO_PORT SET: SETP24 Mask */ +#define GPIO_PORT_SET_SETP25_Pos 25 /*!< GPIO_PORT SET: SETP25 Position */ +#define GPIO_PORT_SET_SETP25_Msk (0x01UL << GPIO_PORT_SET_SETP25_Pos) /*!< GPIO_PORT SET: SETP25 Mask */ +#define GPIO_PORT_SET_SETP26_Pos 26 /*!< GPIO_PORT SET: SETP26 Position */ +#define GPIO_PORT_SET_SETP26_Msk (0x01UL << GPIO_PORT_SET_SETP26_Pos) /*!< GPIO_PORT SET: SETP26 Mask */ +#define GPIO_PORT_SET_SETP27_Pos 27 /*!< GPIO_PORT SET: SETP27 Position */ +#define GPIO_PORT_SET_SETP27_Msk (0x01UL << GPIO_PORT_SET_SETP27_Pos) /*!< GPIO_PORT SET: SETP27 Mask */ +#define GPIO_PORT_SET_SETP28_Pos 28 /*!< GPIO_PORT SET: SETP28 Position */ +#define GPIO_PORT_SET_SETP28_Msk (0x01UL << GPIO_PORT_SET_SETP28_Pos) /*!< GPIO_PORT SET: SETP28 Mask */ +#define GPIO_PORT_SET_SETP29_Pos 29 /*!< GPIO_PORT SET: SETP29 Position */ +#define GPIO_PORT_SET_SETP29_Msk (0x01UL << GPIO_PORT_SET_SETP29_Pos) /*!< GPIO_PORT SET: SETP29 Mask */ +#define GPIO_PORT_SET_SETP30_Pos 30 /*!< GPIO_PORT SET: SETP30 Position */ +#define GPIO_PORT_SET_SETP30_Msk (0x01UL << GPIO_PORT_SET_SETP30_Pos) /*!< GPIO_PORT SET: SETP30 Mask */ +#define GPIO_PORT_SET_SETP31_Pos 31 /*!< GPIO_PORT SET: SETP31 Position */ +#define GPIO_PORT_SET_SETP31_Msk (0x01UL << GPIO_PORT_SET_SETP31_Pos) /*!< GPIO_PORT SET: SETP31 Mask */ + +/* -------------------------------- GPIO_PORT_CLR ------------------------------- */ +#define GPIO_PORT_CLR_CLRP00_Pos 0 /*!< GPIO_PORT CLR: CLRP00 Position */ +#define GPIO_PORT_CLR_CLRP00_Msk (0x01UL << GPIO_PORT_CLR_CLRP00_Pos) /*!< GPIO_PORT CLR: CLRP00 Mask */ +#define GPIO_PORT_CLR_CLRP01_Pos 1 /*!< GPIO_PORT CLR: CLRP01 Position */ +#define GPIO_PORT_CLR_CLRP01_Msk (0x01UL << GPIO_PORT_CLR_CLRP01_Pos) /*!< GPIO_PORT CLR: CLRP01 Mask */ +#define GPIO_PORT_CLR_CLRP02_Pos 2 /*!< GPIO_PORT CLR: CLRP02 Position */ +#define GPIO_PORT_CLR_CLRP02_Msk (0x01UL << GPIO_PORT_CLR_CLRP02_Pos) /*!< GPIO_PORT CLR: CLRP02 Mask */ +#define GPIO_PORT_CLR_CLRP03_Pos 3 /*!< GPIO_PORT CLR: CLRP03 Position */ +#define GPIO_PORT_CLR_CLRP03_Msk (0x01UL << GPIO_PORT_CLR_CLRP03_Pos) /*!< GPIO_PORT CLR: CLRP03 Mask */ +#define GPIO_PORT_CLR_CLRP04_Pos 4 /*!< GPIO_PORT CLR: CLRP04 Position */ +#define GPIO_PORT_CLR_CLRP04_Msk (0x01UL << GPIO_PORT_CLR_CLRP04_Pos) /*!< GPIO_PORT CLR: CLRP04 Mask */ +#define GPIO_PORT_CLR_CLRP05_Pos 5 /*!< GPIO_PORT CLR: CLRP05 Position */ +#define GPIO_PORT_CLR_CLRP05_Msk (0x01UL << GPIO_PORT_CLR_CLRP05_Pos) /*!< GPIO_PORT CLR: CLRP05 Mask */ +#define GPIO_PORT_CLR_CLRP06_Pos 6 /*!< GPIO_PORT CLR: CLRP06 Position */ +#define GPIO_PORT_CLR_CLRP06_Msk (0x01UL << GPIO_PORT_CLR_CLRP06_Pos) /*!< GPIO_PORT CLR: CLRP06 Mask */ +#define GPIO_PORT_CLR_CLRP07_Pos 7 /*!< GPIO_PORT CLR: CLRP07 Position */ +#define GPIO_PORT_CLR_CLRP07_Msk (0x01UL << GPIO_PORT_CLR_CLRP07_Pos) /*!< GPIO_PORT CLR: CLRP07 Mask */ +#define GPIO_PORT_CLR_CLRP08_Pos 8 /*!< GPIO_PORT CLR: CLRP08 Position */ +#define GPIO_PORT_CLR_CLRP08_Msk (0x01UL << GPIO_PORT_CLR_CLRP08_Pos) /*!< GPIO_PORT CLR: CLRP08 Mask */ +#define GPIO_PORT_CLR_CLRP09_Pos 9 /*!< GPIO_PORT CLR: CLRP09 Position */ +#define GPIO_PORT_CLR_CLRP09_Msk (0x01UL << GPIO_PORT_CLR_CLRP09_Pos) /*!< GPIO_PORT CLR: CLRP09 Mask */ +#define GPIO_PORT_CLR_CLRP010_Pos 10 /*!< GPIO_PORT CLR: CLRP010 Position */ +#define GPIO_PORT_CLR_CLRP010_Msk (0x01UL << GPIO_PORT_CLR_CLRP010_Pos) /*!< GPIO_PORT CLR: CLRP010 Mask */ +#define GPIO_PORT_CLR_CLRP011_Pos 11 /*!< GPIO_PORT CLR: CLRP011 Position */ +#define GPIO_PORT_CLR_CLRP011_Msk (0x01UL << GPIO_PORT_CLR_CLRP011_Pos) /*!< GPIO_PORT CLR: CLRP011 Mask */ +#define GPIO_PORT_CLR_CLRP012_Pos 12 /*!< GPIO_PORT CLR: CLRP012 Position */ +#define GPIO_PORT_CLR_CLRP012_Msk (0x01UL << GPIO_PORT_CLR_CLRP012_Pos) /*!< GPIO_PORT CLR: CLRP012 Mask */ +#define GPIO_PORT_CLR_CLRP013_Pos 13 /*!< GPIO_PORT CLR: CLRP013 Position */ +#define GPIO_PORT_CLR_CLRP013_Msk (0x01UL << GPIO_PORT_CLR_CLRP013_Pos) /*!< GPIO_PORT CLR: CLRP013 Mask */ +#define GPIO_PORT_CLR_CLRP014_Pos 14 /*!< GPIO_PORT CLR: CLRP014 Position */ +#define GPIO_PORT_CLR_CLRP014_Msk (0x01UL << GPIO_PORT_CLR_CLRP014_Pos) /*!< GPIO_PORT CLR: CLRP014 Mask */ +#define GPIO_PORT_CLR_CLRP015_Pos 15 /*!< GPIO_PORT CLR: CLRP015 Position */ +#define GPIO_PORT_CLR_CLRP015_Msk (0x01UL << GPIO_PORT_CLR_CLRP015_Pos) /*!< GPIO_PORT CLR: CLRP015 Mask */ +#define GPIO_PORT_CLR_CLRP016_Pos 16 /*!< GPIO_PORT CLR: CLRP016 Position */ +#define GPIO_PORT_CLR_CLRP016_Msk (0x01UL << GPIO_PORT_CLR_CLRP016_Pos) /*!< GPIO_PORT CLR: CLRP016 Mask */ +#define GPIO_PORT_CLR_CLRP017_Pos 17 /*!< GPIO_PORT CLR: CLRP017 Position */ +#define GPIO_PORT_CLR_CLRP017_Msk (0x01UL << GPIO_PORT_CLR_CLRP017_Pos) /*!< GPIO_PORT CLR: CLRP017 Mask */ +#define GPIO_PORT_CLR_CLRP018_Pos 18 /*!< GPIO_PORT CLR: CLRP018 Position */ +#define GPIO_PORT_CLR_CLRP018_Msk (0x01UL << GPIO_PORT_CLR_CLRP018_Pos) /*!< GPIO_PORT CLR: CLRP018 Mask */ +#define GPIO_PORT_CLR_CLRP019_Pos 19 /*!< GPIO_PORT CLR: CLRP019 Position */ +#define GPIO_PORT_CLR_CLRP019_Msk (0x01UL << GPIO_PORT_CLR_CLRP019_Pos) /*!< GPIO_PORT CLR: CLRP019 Mask */ +#define GPIO_PORT_CLR_CLRP020_Pos 20 /*!< GPIO_PORT CLR: CLRP020 Position */ +#define GPIO_PORT_CLR_CLRP020_Msk (0x01UL << GPIO_PORT_CLR_CLRP020_Pos) /*!< GPIO_PORT CLR: CLRP020 Mask */ +#define GPIO_PORT_CLR_CLRP021_Pos 21 /*!< GPIO_PORT CLR: CLRP021 Position */ +#define GPIO_PORT_CLR_CLRP021_Msk (0x01UL << GPIO_PORT_CLR_CLRP021_Pos) /*!< GPIO_PORT CLR: CLRP021 Mask */ +#define GPIO_PORT_CLR_CLRP022_Pos 22 /*!< GPIO_PORT CLR: CLRP022 Position */ +#define GPIO_PORT_CLR_CLRP022_Msk (0x01UL << GPIO_PORT_CLR_CLRP022_Pos) /*!< GPIO_PORT CLR: CLRP022 Mask */ +#define GPIO_PORT_CLR_CLRP023_Pos 23 /*!< GPIO_PORT CLR: CLRP023 Position */ +#define GPIO_PORT_CLR_CLRP023_Msk (0x01UL << GPIO_PORT_CLR_CLRP023_Pos) /*!< GPIO_PORT CLR: CLRP023 Mask */ +#define GPIO_PORT_CLR_CLRP024_Pos 24 /*!< GPIO_PORT CLR: CLRP024 Position */ +#define GPIO_PORT_CLR_CLRP024_Msk (0x01UL << GPIO_PORT_CLR_CLRP024_Pos) /*!< GPIO_PORT CLR: CLRP024 Mask */ +#define GPIO_PORT_CLR_CLRP025_Pos 25 /*!< GPIO_PORT CLR: CLRP025 Position */ +#define GPIO_PORT_CLR_CLRP025_Msk (0x01UL << GPIO_PORT_CLR_CLRP025_Pos) /*!< GPIO_PORT CLR: CLRP025 Mask */ +#define GPIO_PORT_CLR_CLRP026_Pos 26 /*!< GPIO_PORT CLR: CLRP026 Position */ +#define GPIO_PORT_CLR_CLRP026_Msk (0x01UL << GPIO_PORT_CLR_CLRP026_Pos) /*!< GPIO_PORT CLR: CLRP026 Mask */ +#define GPIO_PORT_CLR_CLRP027_Pos 27 /*!< GPIO_PORT CLR: CLRP027 Position */ +#define GPIO_PORT_CLR_CLRP027_Msk (0x01UL << GPIO_PORT_CLR_CLRP027_Pos) /*!< GPIO_PORT CLR: CLRP027 Mask */ +#define GPIO_PORT_CLR_CLRP028_Pos 28 /*!< GPIO_PORT CLR: CLRP028 Position */ +#define GPIO_PORT_CLR_CLRP028_Msk (0x01UL << GPIO_PORT_CLR_CLRP028_Pos) /*!< GPIO_PORT CLR: CLRP028 Mask */ +#define GPIO_PORT_CLR_CLRP029_Pos 29 /*!< GPIO_PORT CLR: CLRP029 Position */ +#define GPIO_PORT_CLR_CLRP029_Msk (0x01UL << GPIO_PORT_CLR_CLRP029_Pos) /*!< GPIO_PORT CLR: CLRP029 Mask */ +#define GPIO_PORT_CLR_CLRP030_Pos 30 /*!< GPIO_PORT CLR: CLRP030 Position */ +#define GPIO_PORT_CLR_CLRP030_Msk (0x01UL << GPIO_PORT_CLR_CLRP030_Pos) /*!< GPIO_PORT CLR: CLRP030 Mask */ +#define GPIO_PORT_CLR_CLRP031_Pos 31 /*!< GPIO_PORT CLR: CLRP031 Position */ +#define GPIO_PORT_CLR_CLRP031_Msk (0x01UL << GPIO_PORT_CLR_CLRP031_Pos) /*!< GPIO_PORT CLR: CLRP031 Mask */ + +/* -------------------------------- GPIO_PORT_NOT ------------------------------- */ +#define GPIO_PORT_NOT_NOTP0_Pos 0 /*!< GPIO_PORT NOT: NOTP0 Position */ +#define GPIO_PORT_NOT_NOTP0_Msk (0x01UL << GPIO_PORT_NOT_NOTP0_Pos) /*!< GPIO_PORT NOT: NOTP0 Mask */ +#define GPIO_PORT_NOT_NOTP1_Pos 1 /*!< GPIO_PORT NOT: NOTP1 Position */ +#define GPIO_PORT_NOT_NOTP1_Msk (0x01UL << GPIO_PORT_NOT_NOTP1_Pos) /*!< GPIO_PORT NOT: NOTP1 Mask */ +#define GPIO_PORT_NOT_NOTP2_Pos 2 /*!< GPIO_PORT NOT: NOTP2 Position */ +#define GPIO_PORT_NOT_NOTP2_Msk (0x01UL << GPIO_PORT_NOT_NOTP2_Pos) /*!< GPIO_PORT NOT: NOTP2 Mask */ +#define GPIO_PORT_NOT_NOTP3_Pos 3 /*!< GPIO_PORT NOT: NOTP3 Position */ +#define GPIO_PORT_NOT_NOTP3_Msk (0x01UL << GPIO_PORT_NOT_NOTP3_Pos) /*!< GPIO_PORT NOT: NOTP3 Mask */ +#define GPIO_PORT_NOT_NOTP4_Pos 4 /*!< GPIO_PORT NOT: NOTP4 Position */ +#define GPIO_PORT_NOT_NOTP4_Msk (0x01UL << GPIO_PORT_NOT_NOTP4_Pos) /*!< GPIO_PORT NOT: NOTP4 Mask */ +#define GPIO_PORT_NOT_NOTP5_Pos 5 /*!< GPIO_PORT NOT: NOTP5 Position */ +#define GPIO_PORT_NOT_NOTP5_Msk (0x01UL << GPIO_PORT_NOT_NOTP5_Pos) /*!< GPIO_PORT NOT: NOTP5 Mask */ +#define GPIO_PORT_NOT_NOTP6_Pos 6 /*!< GPIO_PORT NOT: NOTP6 Position */ +#define GPIO_PORT_NOT_NOTP6_Msk (0x01UL << GPIO_PORT_NOT_NOTP6_Pos) /*!< GPIO_PORT NOT: NOTP6 Mask */ +#define GPIO_PORT_NOT_NOTP7_Pos 7 /*!< GPIO_PORT NOT: NOTP7 Position */ +#define GPIO_PORT_NOT_NOTP7_Msk (0x01UL << GPIO_PORT_NOT_NOTP7_Pos) /*!< GPIO_PORT NOT: NOTP7 Mask */ +#define GPIO_PORT_NOT_NOTP8_Pos 8 /*!< GPIO_PORT NOT: NOTP8 Position */ +#define GPIO_PORT_NOT_NOTP8_Msk (0x01UL << GPIO_PORT_NOT_NOTP8_Pos) /*!< GPIO_PORT NOT: NOTP8 Mask */ +#define GPIO_PORT_NOT_NOTP9_Pos 9 /*!< GPIO_PORT NOT: NOTP9 Position */ +#define GPIO_PORT_NOT_NOTP9_Msk (0x01UL << GPIO_PORT_NOT_NOTP9_Pos) /*!< GPIO_PORT NOT: NOTP9 Mask */ +#define GPIO_PORT_NOT_NOTP10_Pos 10 /*!< GPIO_PORT NOT: NOTP10 Position */ +#define GPIO_PORT_NOT_NOTP10_Msk (0x01UL << GPIO_PORT_NOT_NOTP10_Pos) /*!< GPIO_PORT NOT: NOTP10 Mask */ +#define GPIO_PORT_NOT_NOTP11_Pos 11 /*!< GPIO_PORT NOT: NOTP11 Position */ +#define GPIO_PORT_NOT_NOTP11_Msk (0x01UL << GPIO_PORT_NOT_NOTP11_Pos) /*!< GPIO_PORT NOT: NOTP11 Mask */ +#define GPIO_PORT_NOT_NOTP12_Pos 12 /*!< GPIO_PORT NOT: NOTP12 Position */ +#define GPIO_PORT_NOT_NOTP12_Msk (0x01UL << GPIO_PORT_NOT_NOTP12_Pos) /*!< GPIO_PORT NOT: NOTP12 Mask */ +#define GPIO_PORT_NOT_NOTP13_Pos 13 /*!< GPIO_PORT NOT: NOTP13 Position */ +#define GPIO_PORT_NOT_NOTP13_Msk (0x01UL << GPIO_PORT_NOT_NOTP13_Pos) /*!< GPIO_PORT NOT: NOTP13 Mask */ +#define GPIO_PORT_NOT_NOTP14_Pos 14 /*!< GPIO_PORT NOT: NOTP14 Position */ +#define GPIO_PORT_NOT_NOTP14_Msk (0x01UL << GPIO_PORT_NOT_NOTP14_Pos) /*!< GPIO_PORT NOT: NOTP14 Mask */ +#define GPIO_PORT_NOT_NOTP15_Pos 15 /*!< GPIO_PORT NOT: NOTP15 Position */ +#define GPIO_PORT_NOT_NOTP15_Msk (0x01UL << GPIO_PORT_NOT_NOTP15_Pos) /*!< GPIO_PORT NOT: NOTP15 Mask */ +#define GPIO_PORT_NOT_NOTP16_Pos 16 /*!< GPIO_PORT NOT: NOTP16 Position */ +#define GPIO_PORT_NOT_NOTP16_Msk (0x01UL << GPIO_PORT_NOT_NOTP16_Pos) /*!< GPIO_PORT NOT: NOTP16 Mask */ +#define GPIO_PORT_NOT_NOTP17_Pos 17 /*!< GPIO_PORT NOT: NOTP17 Position */ +#define GPIO_PORT_NOT_NOTP17_Msk (0x01UL << GPIO_PORT_NOT_NOTP17_Pos) /*!< GPIO_PORT NOT: NOTP17 Mask */ +#define GPIO_PORT_NOT_NOTP18_Pos 18 /*!< GPIO_PORT NOT: NOTP18 Position */ +#define GPIO_PORT_NOT_NOTP18_Msk (0x01UL << GPIO_PORT_NOT_NOTP18_Pos) /*!< GPIO_PORT NOT: NOTP18 Mask */ +#define GPIO_PORT_NOT_NOTP19_Pos 19 /*!< GPIO_PORT NOT: NOTP19 Position */ +#define GPIO_PORT_NOT_NOTP19_Msk (0x01UL << GPIO_PORT_NOT_NOTP19_Pos) /*!< GPIO_PORT NOT: NOTP19 Mask */ +#define GPIO_PORT_NOT_NOTP20_Pos 20 /*!< GPIO_PORT NOT: NOTP20 Position */ +#define GPIO_PORT_NOT_NOTP20_Msk (0x01UL << GPIO_PORT_NOT_NOTP20_Pos) /*!< GPIO_PORT NOT: NOTP20 Mask */ +#define GPIO_PORT_NOT_NOTP21_Pos 21 /*!< GPIO_PORT NOT: NOTP21 Position */ +#define GPIO_PORT_NOT_NOTP21_Msk (0x01UL << GPIO_PORT_NOT_NOTP21_Pos) /*!< GPIO_PORT NOT: NOTP21 Mask */ +#define GPIO_PORT_NOT_NOTP22_Pos 22 /*!< GPIO_PORT NOT: NOTP22 Position */ +#define GPIO_PORT_NOT_NOTP22_Msk (0x01UL << GPIO_PORT_NOT_NOTP22_Pos) /*!< GPIO_PORT NOT: NOTP22 Mask */ +#define GPIO_PORT_NOT_NOTP23_Pos 23 /*!< GPIO_PORT NOT: NOTP23 Position */ +#define GPIO_PORT_NOT_NOTP23_Msk (0x01UL << GPIO_PORT_NOT_NOTP23_Pos) /*!< GPIO_PORT NOT: NOTP23 Mask */ +#define GPIO_PORT_NOT_NOTP24_Pos 24 /*!< GPIO_PORT NOT: NOTP24 Position */ +#define GPIO_PORT_NOT_NOTP24_Msk (0x01UL << GPIO_PORT_NOT_NOTP24_Pos) /*!< GPIO_PORT NOT: NOTP24 Mask */ +#define GPIO_PORT_NOT_NOTP25_Pos 25 /*!< GPIO_PORT NOT: NOTP25 Position */ +#define GPIO_PORT_NOT_NOTP25_Msk (0x01UL << GPIO_PORT_NOT_NOTP25_Pos) /*!< GPIO_PORT NOT: NOTP25 Mask */ +#define GPIO_PORT_NOT_NOTP26_Pos 26 /*!< GPIO_PORT NOT: NOTP26 Position */ +#define GPIO_PORT_NOT_NOTP26_Msk (0x01UL << GPIO_PORT_NOT_NOTP26_Pos) /*!< GPIO_PORT NOT: NOTP26 Mask */ +#define GPIO_PORT_NOT_NOTP27_Pos 27 /*!< GPIO_PORT NOT: NOTP27 Position */ +#define GPIO_PORT_NOT_NOTP27_Msk (0x01UL << GPIO_PORT_NOT_NOTP27_Pos) /*!< GPIO_PORT NOT: NOTP27 Mask */ +#define GPIO_PORT_NOT_NOTP28_Pos 28 /*!< GPIO_PORT NOT: NOTP28 Position */ +#define GPIO_PORT_NOT_NOTP28_Msk (0x01UL << GPIO_PORT_NOT_NOTP28_Pos) /*!< GPIO_PORT NOT: NOTP28 Mask */ +#define GPIO_PORT_NOT_NOTP29_Pos 29 /*!< GPIO_PORT NOT: NOTP29 Position */ +#define GPIO_PORT_NOT_NOTP29_Msk (0x01UL << GPIO_PORT_NOT_NOTP29_Pos) /*!< GPIO_PORT NOT: NOTP29 Mask */ +#define GPIO_PORT_NOT_NOTP30_Pos 30 /*!< GPIO_PORT NOT: NOTP30 Position */ +#define GPIO_PORT_NOT_NOTP30_Msk (0x01UL << GPIO_PORT_NOT_NOTP30_Pos) /*!< GPIO_PORT NOT: NOTP30 Mask */ +#define GPIO_PORT_NOT_NOTP31_Pos 31 /*!< GPIO_PORT NOT: NOTP31 Position */ +#define GPIO_PORT_NOT_NOTP31_Msk (0x01UL << GPIO_PORT_NOT_NOTP31_Pos) /*!< GPIO_PORT NOT: NOTP31 Mask */ + + +/* ================================================================================ */ +/* ================ struct 'SPI' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------------- SPI_CR ----------------------------------- */ +#define SPI_CR_BITENABLE_Pos 2 /*!< SPI CR: BITENABLE Position */ +#define SPI_CR_BITENABLE_Msk (0x01UL << SPI_CR_BITENABLE_Pos) /*!< SPI CR: BITENABLE Mask */ +#define SPI_CR_CPHA_Pos 3 /*!< SPI CR: CPHA Position */ +#define SPI_CR_CPHA_Msk (0x01UL << SPI_CR_CPHA_Pos) /*!< SPI CR: CPHA Mask */ +#define SPI_CR_CPOL_Pos 4 /*!< SPI CR: CPOL Position */ +#define SPI_CR_CPOL_Msk (0x01UL << SPI_CR_CPOL_Pos) /*!< SPI CR: CPOL Mask */ +#define SPI_CR_MSTR_Pos 5 /*!< SPI CR: MSTR Position */ +#define SPI_CR_MSTR_Msk (0x01UL << SPI_CR_MSTR_Pos) /*!< SPI CR: MSTR Mask */ +#define SPI_CR_LSBF_Pos 6 /*!< SPI CR: LSBF Position */ +#define SPI_CR_LSBF_Msk (0x01UL << SPI_CR_LSBF_Pos) /*!< SPI CR: LSBF Mask */ +#define SPI_CR_SPIE_Pos 7 /*!< SPI CR: SPIE Position */ +#define SPI_CR_SPIE_Msk (0x01UL << SPI_CR_SPIE_Pos) /*!< SPI CR: SPIE Mask */ +#define SPI_CR_BITS_Pos 8 /*!< SPI CR: BITS Position */ +#define SPI_CR_BITS_Msk (0x0fUL << SPI_CR_BITS_Pos) /*!< SPI CR: BITS Mask */ + +/* ----------------------------------- SPI_SR ----------------------------------- */ +#define SPI_SR_ABRT_Pos 3 /*!< SPI SR: ABRT Position */ +#define SPI_SR_ABRT_Msk (0x01UL << SPI_SR_ABRT_Pos) /*!< SPI SR: ABRT Mask */ +#define SPI_SR_MODF_Pos 4 /*!< SPI SR: MODF Position */ +#define SPI_SR_MODF_Msk (0x01UL << SPI_SR_MODF_Pos) /*!< SPI SR: MODF Mask */ +#define SPI_SR_ROVR_Pos 5 /*!< SPI SR: ROVR Position */ +#define SPI_SR_ROVR_Msk (0x01UL << SPI_SR_ROVR_Pos) /*!< SPI SR: ROVR Mask */ +#define SPI_SR_WCOL_Pos 6 /*!< SPI SR: WCOL Position */ +#define SPI_SR_WCOL_Msk (0x01UL << SPI_SR_WCOL_Pos) /*!< SPI SR: WCOL Mask */ +#define SPI_SR_SPIF_Pos 7 /*!< SPI SR: SPIF Position */ +#define SPI_SR_SPIF_Msk (0x01UL << SPI_SR_SPIF_Pos) /*!< SPI SR: SPIF Mask */ + +/* ----------------------------------- SPI_DR ----------------------------------- */ +#define SPI_DR_DATALOW_Pos 0 /*!< SPI DR: DATALOW Position */ +#define SPI_DR_DATALOW_Msk (0x000000ffUL << SPI_DR_DATALOW_Pos) /*!< SPI DR: DATALOW Mask */ +#define SPI_DR_DATAHIGH_Pos 8 /*!< SPI DR: DATAHIGH Position */ +#define SPI_DR_DATAHIGH_Msk (0x000000ffUL << SPI_DR_DATAHIGH_Pos) /*!< SPI DR: DATAHIGH Mask */ + +/* ----------------------------------- SPI_CCR ---------------------------------- */ +#define SPI_CCR_COUNTER_Pos 0 /*!< SPI CCR: COUNTER Position */ +#define SPI_CCR_COUNTER_Msk (0x000000ffUL << SPI_CCR_COUNTER_Pos) /*!< SPI CCR: COUNTER Mask */ + +/* ----------------------------------- SPI_TCR ---------------------------------- */ +#define SPI_TCR_TEST_Pos 1 /*!< SPI TCR: TEST Position */ +#define SPI_TCR_TEST_Msk (0x7fUL << SPI_TCR_TEST_Pos) /*!< SPI TCR: TEST Mask */ + +/* ----------------------------------- SPI_TSR ---------------------------------- */ +#define SPI_TSR_ABRT_Pos 3 /*!< SPI TSR: ABRT Position */ +#define SPI_TSR_ABRT_Msk (0x01UL << SPI_TSR_ABRT_Pos) /*!< SPI TSR: ABRT Mask */ +#define SPI_TSR_MODF_Pos 4 /*!< SPI TSR: MODF Position */ +#define SPI_TSR_MODF_Msk (0x01UL << SPI_TSR_MODF_Pos) /*!< SPI TSR: MODF Mask */ +#define SPI_TSR_ROVR_Pos 5 /*!< SPI TSR: ROVR Position */ +#define SPI_TSR_ROVR_Msk (0x01UL << SPI_TSR_ROVR_Pos) /*!< SPI TSR: ROVR Mask */ +#define SPI_TSR_WCOL_Pos 6 /*!< SPI TSR: WCOL Position */ +#define SPI_TSR_WCOL_Msk (0x01UL << SPI_TSR_WCOL_Pos) /*!< SPI TSR: WCOL Mask */ +#define SPI_TSR_SPIF_Pos 7 /*!< SPI TSR: SPIF Position */ +#define SPI_TSR_SPIF_Msk (0x01UL << SPI_TSR_SPIF_Pos) /*!< SPI TSR: SPIF Mask */ + +/* ----------------------------------- SPI_INT ---------------------------------- */ +#define SPI_INT_SPIF_Pos 0 /*!< SPI INT: SPIF Position */ +#define SPI_INT_SPIF_Msk (0x01UL << SPI_INT_SPIF_Pos) /*!< SPI INT: SPIF Mask */ + + +/* ================================================================================ */ +/* ================ struct 'SGPIO' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------ SGPIO_OUT_MUX_CFG ----------------------------- */ +#define SGPIO_OUT_MUX_CFG_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG: P_OUT_CFG Position */ +#define SGPIO_OUT_MUX_CFG_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG: P_OUT_CFG Mask */ +#define SGPIO_OUT_MUX_CFG_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG: P_OE_CFG Position */ +#define SGPIO_OUT_MUX_CFG_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG: P_OE_CFG Mask */ + +/* ----------------------------- SGPIO_SGPIO_MUX_CFG ---------------------------- */ +#define SGPIO_SGPIO_MUX_CFG_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG: EXT_CLK_ENABLE Position */ +#define SGPIO_SGPIO_MUX_CFG_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG: EXT_CLK_ENABLE Mask */ +#define SGPIO_SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG: CLK_SOURCE_PIN_MODE Position */ +#define SGPIO_SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG: CLK_SOURCE_PIN_MODE Mask */ +#define SGPIO_SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG: CLK_SOURCE_SLICE_MODE Position */ +#define SGPIO_SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG: CLK_SOURCE_SLICE_MODE Mask */ +#define SGPIO_SGPIO_MUX_CFG_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG: QUALIFIER_MODE Position */ +#define SGPIO_SGPIO_MUX_CFG_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG: QUALIFIER_MODE Mask */ +#define SGPIO_SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG: QUALIFIER_PIN_MODE Position */ +#define SGPIO_SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG: QUALIFIER_PIN_MODE Mask */ +#define SGPIO_SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG: QUALIFIER_SLICE_MODE Position */ +#define SGPIO_SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG: QUALIFIER_SLICE_MODE Mask */ +#define SGPIO_SGPIO_MUX_CFG_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG: CONCAT_ENABLE Position */ +#define SGPIO_SGPIO_MUX_CFG_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG: CONCAT_ENABLE Mask */ +#define SGPIO_SGPIO_MUX_CFG_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG: CONCAT_ORDER Position */ +#define SGPIO_SGPIO_MUX_CFG_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG: CONCAT_ORDER Mask */ + +/* ----------------------------- SGPIO_SLICE_MUX_CFG ---------------------------- */ +#define SGPIO_SLICE_MUX_CFG_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG: MATCH_MODE Position */ +#define SGPIO_SLICE_MUX_CFG_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG: MATCH_MODE Mask */ +#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG: CLK_CAPTURE_MODE Position */ +#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG: CLK_CAPTURE_MODE Mask */ +#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG: CLKGEN_MODE Position */ +#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG: CLKGEN_MODE Mask */ +#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG: INV_OUT_CLK Position */ +#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG: INV_OUT_CLK Mask */ +#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG: DATA_CAPTURE_MODE Position */ +#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_Pos)/*!< SGPIO SLICE_MUX_CFG: DATA_CAPTURE_MODE Mask */ +#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG: PARALLEL_MODE Position */ +#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG: PARALLEL_MODE Mask */ +#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG: INV_QUALIFIER Position */ +#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG: INV_QUALIFIER Mask */ + +/* ---------------------------------- SGPIO_REG --------------------------------- */ +#define SGPIO_REG_REG_Pos 0 /*!< SGPIO REG: REG Position */ +#define SGPIO_REG_REG_Msk (0xffffffffUL << SGPIO_REG_REG_Pos) /*!< SGPIO REG: REG Mask */ + +/* -------------------------------- SGPIO_REG_SS -------------------------------- */ +#define SGPIO_REG_SS_REG_SS_Pos 0 /*!< SGPIO REG_SS: REG_SS Position */ +#define SGPIO_REG_SS_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS_REG_SS_Pos) /*!< SGPIO REG_SS: REG_SS Mask */ + +/* -------------------------------- SGPIO_PRESET -------------------------------- */ +#define SGPIO_PRESET_PRESET_Pos 0 /*!< SGPIO PRESET: PRESET Position */ +#define SGPIO_PRESET_PRESET_Msk (0x00000fffUL << SGPIO_PRESET_PRESET_Pos) /*!< SGPIO PRESET: PRESET Mask */ + +/* --------------------------------- SGPIO_COUNT -------------------------------- */ +#define SGPIO_COUNT_COUNT_Pos 0 /*!< SGPIO COUNT: COUNT Position */ +#define SGPIO_COUNT_COUNT_Msk (0x00000fffUL << SGPIO_COUNT_COUNT_Pos) /*!< SGPIO COUNT: COUNT Mask */ + +/* ---------------------------------- SGPIO_POS --------------------------------- */ +#define SGPIO_POS_POS_Pos 0 /*!< SGPIO POS: POS Position */ +#define SGPIO_POS_POS_Msk (0x000000ffUL << SGPIO_POS_POS_Pos) /*!< SGPIO POS: POS Mask */ +#define SGPIO_POS_POS_RESET_Pos 8 /*!< SGPIO POS: POS_RESET Position */ +#define SGPIO_POS_POS_RESET_Msk (0x000000ffUL << SGPIO_POS_POS_RESET_Pos) /*!< SGPIO POS: POS_RESET Mask */ + +/* -------------------------------- SGPIO_MASK_A -------------------------------- */ +#define SGPIO_MASK_A_MASK_A_Pos 0 /*!< SGPIO MASK_A: MASK_A Position */ +#define SGPIO_MASK_A_MASK_A_Msk (0xffffffffUL << SGPIO_MASK_A_MASK_A_Pos) /*!< SGPIO MASK_A: MASK_A Mask */ + +/* -------------------------------- SGPIO_MASK_H -------------------------------- */ +#define SGPIO_MASK_H_MASK_H_Pos 0 /*!< SGPIO MASK_H: MASK_H Position */ +#define SGPIO_MASK_H_MASK_H_Msk (0xffffffffUL << SGPIO_MASK_H_MASK_H_Pos) /*!< SGPIO MASK_H: MASK_H Mask */ + +/* -------------------------------- SGPIO_MASK_I -------------------------------- */ +#define SGPIO_MASK_I_MASK_I_Pos 0 /*!< SGPIO MASK_I: MASK_I Position */ +#define SGPIO_MASK_I_MASK_I_Msk (0xffffffffUL << SGPIO_MASK_I_MASK_I_Pos) /*!< SGPIO MASK_I: MASK_I Mask */ + +/* -------------------------------- SGPIO_MASK_P -------------------------------- */ +#define SGPIO_MASK_P_MASK_P_Pos 0 /*!< SGPIO MASK_P: MASK_P Position */ +#define SGPIO_MASK_P_MASK_P_Msk (0xffffffffUL << SGPIO_MASK_P_MASK_P_Pos) /*!< SGPIO MASK_P: MASK_P Mask */ + +/* ------------------------------ SGPIO_GPIO_INREG ------------------------------ */ +#define SGPIO_GPIO_INREG_GPIO_INi_Pos 0 /*!< SGPIO GPIO_INREG: GPIO_INi Position */ +#define SGPIO_GPIO_INREG_GPIO_INi_Msk (0x0000ffffUL << SGPIO_GPIO_INREG_GPIO_INi_Pos) /*!< SGPIO GPIO_INREG: GPIO_INi Mask */ + +/* ------------------------------ SGPIO_GPIO_OUTREG ----------------------------- */ +#define SGPIO_GPIO_OUTREG_GPIO_OUT_Pos 0 /*!< SGPIO GPIO_OUTREG: GPIO_OUT Position */ +#define SGPIO_GPIO_OUTREG_GPIO_OUT_Msk (0x0000ffffUL << SGPIO_GPIO_OUTREG_GPIO_OUT_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT Mask */ + +/* ------------------------------ SGPIO_GPIO_OENREG ----------------------------- */ +#define SGPIO_GPIO_OENREG_GPIO_OE_Pos 0 /*!< SGPIO GPIO_OENREG: GPIO_OE Position */ +#define SGPIO_GPIO_OENREG_GPIO_OE_Msk (0x0000ffffUL << SGPIO_GPIO_OENREG_GPIO_OE_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE Mask */ + +/* ------------------------------ SGPIO_CTRL_ENABLE ----------------------------- */ +#define SGPIO_CTRL_ENABLE_CTRL_EN_Pos 0 /*!< SGPIO CTRL_ENABLE: CTRL_EN Position */ +#define SGPIO_CTRL_ENABLE_CTRL_EN_Msk (0x0000ffffUL << SGPIO_CTRL_ENABLE_CTRL_EN_Pos) /*!< SGPIO CTRL_ENABLE: CTRL_EN Mask */ + +/* ----------------------------- SGPIO_CTRL_DISABLE ----------------------------- */ +#define SGPIO_CTRL_DISABLE_CTRL_DIS_Pos 0 /*!< SGPIO CTRL_DISABLE: CTRL_DIS Position */ +#define SGPIO_CTRL_DISABLE_CTRL_DIS_Msk (0x0000ffffUL << SGPIO_CTRL_DISABLE_CTRL_DIS_Pos) /*!< SGPIO CTRL_DISABLE: CTRL_DIS Mask */ + +/* ------------------------------- SGPIO_CLR_EN_0 ------------------------------- */ +#define SGPIO_CLR_EN_0_CLR_SCI_Pos 0 /*!< SGPIO CLR_EN_0: CLR_SCI Position */ +#define SGPIO_CLR_EN_0_CLR_SCI_Msk (0x0000ffffUL << SGPIO_CLR_EN_0_CLR_SCI_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI Mask */ + +/* ------------------------------- SGPIO_SET_EN_0 ------------------------------- */ +#define SGPIO_SET_EN_0_SET_SCI_Pos 0 /*!< SGPIO SET_EN_0: SET_SCI Position */ +#define SGPIO_SET_EN_0_SET_SCI_Msk (0x0000ffffUL << SGPIO_SET_EN_0_SET_SCI_Pos) /*!< SGPIO SET_EN_0: SET_SCI Mask */ + +/* ------------------------------- SGPIO_ENABLE_0 ------------------------------- */ +#define SGPIO_ENABLE_0_ENABLE_SCI_Pos 0 /*!< SGPIO ENABLE_0: ENABLE_SCI Position */ +#define SGPIO_ENABLE_0_ENABLE_SCI_Msk (0x0000ffffUL << SGPIO_ENABLE_0_ENABLE_SCI_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI Mask */ + +/* ------------------------------- SGPIO_STATUS_0 ------------------------------- */ +#define SGPIO_STATUS_0_STATUS_SCI_Pos 0 /*!< SGPIO STATUS_0: STATUS_SCI Position */ +#define SGPIO_STATUS_0_STATUS_SCI_Msk (0x0000ffffUL << SGPIO_STATUS_0_STATUS_SCI_Pos) /*!< SGPIO STATUS_0: STATUS_SCI Mask */ + +/* ----------------------------- SGPIO_CLR_STATUS_0 ----------------------------- */ +#define SGPIO_CLR_STATUS_0_CLR_STATUS_SCI_Pos 0 /*!< SGPIO CLR_STATUS_0: CLR_STATUS_SCI Position */ +#define SGPIO_CLR_STATUS_0_CLR_STATUS_SCI_Msk (0x0000ffffUL << SGPIO_CLR_STATUS_0_CLR_STATUS_SCI_Pos) /*!< SGPIO CLR_STATUS_0: CLR_STATUS_SCI Mask */ + +/* ----------------------------- SGPIO_SET_STATUS_0 ----------------------------- */ +#define SGPIO_SET_STATUS_0_SET_STATUS_SCI_Pos 0 /*!< SGPIO SET_STATUS_0: SET_STATUS_SCI Position */ +#define SGPIO_SET_STATUS_0_SET_STATUS_SCI_Msk (0x0000ffffUL << SGPIO_SET_STATUS_0_SET_STATUS_SCI_Pos) /*!< SGPIO SET_STATUS_0: SET_STATUS_SCI Mask */ + +/* ------------------------------- SGPIO_CLR_EN_1 ------------------------------- */ +#define SGPIO_CLR_EN_1_CLR_EN_CCI_Pos 0 /*!< SGPIO CLR_EN_1: CLR_EN_CCI Position */ +#define SGPIO_CLR_EN_1_CLR_EN_CCI_Msk (0x0000ffffUL << SGPIO_CLR_EN_1_CLR_EN_CCI_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI Mask */ + +/* ------------------------------- SGPIO_SET_EN_1 ------------------------------- */ +#define SGPIO_SET_EN_1_SET_EN_CCI_Pos 0 /*!< SGPIO SET_EN_1: SET_EN_CCI Position */ +#define SGPIO_SET_EN_1_SET_EN_CCI_Msk (0x0000ffffUL << SGPIO_SET_EN_1_SET_EN_CCI_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI Mask */ + +/* ------------------------------- SGPIO_ENABLE_1 ------------------------------- */ +#define SGPIO_ENABLE_1_ENABLE_CCI_Pos 0 /*!< SGPIO ENABLE_1: ENABLE_CCI Position */ +#define SGPIO_ENABLE_1_ENABLE_CCI_Msk (0x0000ffffUL << SGPIO_ENABLE_1_ENABLE_CCI_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI Mask */ + +/* ------------------------------- SGPIO_STATUS_1 ------------------------------- */ +#define SGPIO_STATUS_1_STATUS_CCI_Pos 0 /*!< SGPIO STATUS_1: STATUS_CCI Position */ +#define SGPIO_STATUS_1_STATUS_CCI_Msk (0x0000ffffUL << SGPIO_STATUS_1_STATUS_CCI_Pos) /*!< SGPIO STATUS_1: STATUS_CCI Mask */ -// ------------------------------------- LCD_CRSR_IMG53 ----------------------------------------- -#define LCD_CRSR_IMG53_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG53: CRSR_IMG Position */ -#define LCD_CRSR_IMG53_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG53_CRSR_IMG_Pos) /*!< LCD CRSR_IMG53: CRSR_IMG Mask */ +/* ----------------------------- SGPIO_CLR_STATUS_1 ----------------------------- */ +#define SGPIO_CLR_STATUS_1_CLR_STATUS_CCI_Pos 0 /*!< SGPIO CLR_STATUS_1: CLR_STATUS_CCI Position */ +#define SGPIO_CLR_STATUS_1_CLR_STATUS_CCI_Msk (0x0000ffffUL << SGPIO_CLR_STATUS_1_CLR_STATUS_CCI_Pos) /*!< SGPIO CLR_STATUS_1: CLR_STATUS_CCI Mask */ -// ------------------------------------- LCD_CRSR_IMG54 ----------------------------------------- -#define LCD_CRSR_IMG54_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG54: CRSR_IMG Position */ -#define LCD_CRSR_IMG54_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG54_CRSR_IMG_Pos) /*!< LCD CRSR_IMG54: CRSR_IMG Mask */ +/* ----------------------------- SGPIO_SET_STATUS_1 ----------------------------- */ +#define SGPIO_SET_STATUS_1_SET_STATUS_CCI_Pos 0 /*!< SGPIO SET_STATUS_1: SET_STATUS_CCI Position */ +#define SGPIO_SET_STATUS_1_SET_STATUS_CCI_Msk (0x0000ffffUL << SGPIO_SET_STATUS_1_SET_STATUS_CCI_Pos) /*!< SGPIO SET_STATUS_1: SET_STATUS_CCI Mask */ -// ------------------------------------- LCD_CRSR_IMG55 ----------------------------------------- -#define LCD_CRSR_IMG55_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG55: CRSR_IMG Position */ -#define LCD_CRSR_IMG55_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG55_CRSR_IMG_Pos) /*!< LCD CRSR_IMG55: CRSR_IMG Mask */ +/* ------------------------------- SGPIO_CLR_EN_2 ------------------------------- */ +#define SGPIO_CLR_EN_2_CLR_EN2_PMI_Pos 0 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI Position */ +#define SGPIO_CLR_EN_2_CLR_EN2_PMI_Msk (0x0000ffffUL << SGPIO_CLR_EN_2_CLR_EN2_PMI_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI Mask */ -// ------------------------------------- LCD_CRSR_IMG56 ----------------------------------------- -#define LCD_CRSR_IMG56_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG56: CRSR_IMG Position */ -#define LCD_CRSR_IMG56_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG56_CRSR_IMG_Pos) /*!< LCD CRSR_IMG56: CRSR_IMG Mask */ +/* ------------------------------- SGPIO_SET_EN_2 ------------------------------- */ +#define SGPIO_SET_EN_2_SET_EN_PMI_Pos 0 /*!< SGPIO SET_EN_2: SET_EN_PMI Position */ +#define SGPIO_SET_EN_2_SET_EN_PMI_Msk (0x0000ffffUL << SGPIO_SET_EN_2_SET_EN_PMI_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI Mask */ -// ------------------------------------- LCD_CRSR_IMG57 ----------------------------------------- -#define LCD_CRSR_IMG57_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG57: CRSR_IMG Position */ -#define LCD_CRSR_IMG57_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG57_CRSR_IMG_Pos) /*!< LCD CRSR_IMG57: CRSR_IMG Mask */ +/* ------------------------------- SGPIO_ENABLE_2 ------------------------------- */ +#define SGPIO_ENABLE_2_ENABLE_PMI_Pos 0 /*!< SGPIO ENABLE_2: ENABLE_PMI Position */ +#define SGPIO_ENABLE_2_ENABLE_PMI_Msk (0x0000ffffUL << SGPIO_ENABLE_2_ENABLE_PMI_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI Mask */ -// ------------------------------------- LCD_CRSR_IMG58 ----------------------------------------- -#define LCD_CRSR_IMG58_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG58: CRSR_IMG Position */ -#define LCD_CRSR_IMG58_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG58_CRSR_IMG_Pos) /*!< LCD CRSR_IMG58: CRSR_IMG Mask */ +/* ------------------------------- SGPIO_STATUS_2 ------------------------------- */ +#define SGPIO_STATUS_2_STATUS_PMI_Pos 0 /*!< SGPIO STATUS_2: STATUS_PMI Position */ +#define SGPIO_STATUS_2_STATUS_PMI_Msk (0x0000ffffUL << SGPIO_STATUS_2_STATUS_PMI_Pos) /*!< SGPIO STATUS_2: STATUS_PMI Mask */ -// ------------------------------------- LCD_CRSR_IMG59 ----------------------------------------- -#define LCD_CRSR_IMG59_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG59: CRSR_IMG Position */ -#define LCD_CRSR_IMG59_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG59_CRSR_IMG_Pos) /*!< LCD CRSR_IMG59: CRSR_IMG Mask */ +/* ----------------------------- SGPIO_CLR_STATUS_2 ----------------------------- */ +#define SGPIO_CLR_STATUS_2_CLR_STATUS_PMI_Pos 0 /*!< SGPIO CLR_STATUS_2: CLR_STATUS_PMI Position */ +#define SGPIO_CLR_STATUS_2_CLR_STATUS_PMI_Msk (0x0000ffffUL << SGPIO_CLR_STATUS_2_CLR_STATUS_PMI_Pos) /*!< SGPIO CLR_STATUS_2: CLR_STATUS_PMI Mask */ -// ------------------------------------- LCD_CRSR_IMG60 ----------------------------------------- -#define LCD_CRSR_IMG60_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG60: CRSR_IMG Position */ -#define LCD_CRSR_IMG60_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG60_CRSR_IMG_Pos) /*!< LCD CRSR_IMG60: CRSR_IMG Mask */ +/* ----------------------------- SGPIO_SET_STATUS_2 ----------------------------- */ +#define SGPIO_SET_STATUS_2_SET_STATUS_PMI_Pos 0 /*!< SGPIO SET_STATUS_2: SET_STATUS_PMI Position */ +#define SGPIO_SET_STATUS_2_SET_STATUS_PMI_Msk (0x0000ffffUL << SGPIO_SET_STATUS_2_SET_STATUS_PMI_Pos) /*!< SGPIO SET_STATUS_2: SET_STATUS_PMI Mask */ -// ------------------------------------- LCD_CRSR_IMG61 ----------------------------------------- -#define LCD_CRSR_IMG61_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG61: CRSR_IMG Position */ -#define LCD_CRSR_IMG61_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG61_CRSR_IMG_Pos) /*!< LCD CRSR_IMG61: CRSR_IMG Mask */ +/* ------------------------------- SGPIO_CLR_EN_3 ------------------------------- */ +#define SGPIO_CLR_EN_3_CLR_EN_INPI_Pos 0 /*!< SGPIO CLR_EN_3: CLR_EN_INPI Position */ +#define SGPIO_CLR_EN_3_CLR_EN_INPI_Msk (0x0000ffffUL << SGPIO_CLR_EN_3_CLR_EN_INPI_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI Mask */ -// ------------------------------------- LCD_CRSR_IMG62 ----------------------------------------- -#define LCD_CRSR_IMG62_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG62: CRSR_IMG Position */ -#define LCD_CRSR_IMG62_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG62_CRSR_IMG_Pos) /*!< LCD CRSR_IMG62: CRSR_IMG Mask */ +/* ------------------------------- SGPIO_SET_EN_3 ------------------------------- */ +#define SGPIO_SET_EN_3_SET_EN_INPI_Pos 0 /*!< SGPIO SET_EN_3: SET_EN_INPI Position */ +#define SGPIO_SET_EN_3_SET_EN_INPI_Msk (0x0000ffffUL << SGPIO_SET_EN_3_SET_EN_INPI_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI Mask */ -// ------------------------------------- LCD_CRSR_IMG63 ----------------------------------------- -#define LCD_CRSR_IMG63_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG63: CRSR_IMG Position */ -#define LCD_CRSR_IMG63_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG63_CRSR_IMG_Pos) /*!< LCD CRSR_IMG63: CRSR_IMG Mask */ +/* ------------------------------- SGPIO_ENABLE_3 ------------------------------- */ +#define SGPIO_ENABLE_3_ENABLE3_INPI_Pos 0 /*!< SGPIO ENABLE_3: ENABLE3_INPI Position */ +#define SGPIO_ENABLE_3_ENABLE3_INPI_Msk (0x0000ffffUL << SGPIO_ENABLE_3_ENABLE3_INPI_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI Mask */ -// ------------------------------------- LCD_CRSR_IMG64 ----------------------------------------- -#define LCD_CRSR_IMG64_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG64: CRSR_IMG Position */ -#define LCD_CRSR_IMG64_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG64_CRSR_IMG_Pos) /*!< LCD CRSR_IMG64: CRSR_IMG Mask */ +/* ------------------------------- SGPIO_STATUS_3 ------------------------------- */ +#define SGPIO_STATUS_3_STATUS_INPI_Pos 0 /*!< SGPIO STATUS_3: STATUS_INPI Position */ +#define SGPIO_STATUS_3_STATUS_INPI_Msk (0x0000ffffUL << SGPIO_STATUS_3_STATUS_INPI_Pos) /*!< SGPIO STATUS_3: STATUS_INPI Mask */ -// ------------------------------------- LCD_CRSR_IMG65 ----------------------------------------- -#define LCD_CRSR_IMG65_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG65: CRSR_IMG Position */ -#define LCD_CRSR_IMG65_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG65_CRSR_IMG_Pos) /*!< LCD CRSR_IMG65: CRSR_IMG Mask */ +/* ----------------------------- SGPIO_CLR_STATUS_3 ----------------------------- */ +#define SGPIO_CLR_STATUS_3_CLR_STATUS_INPI_Pos 0 /*!< SGPIO CLR_STATUS_3: CLR_STATUS_INPI Position */ +#define SGPIO_CLR_STATUS_3_CLR_STATUS_INPI_Msk (0x0000ffffUL << SGPIO_CLR_STATUS_3_CLR_STATUS_INPI_Pos)/*!< SGPIO CLR_STATUS_3: CLR_STATUS_INPI Mask */ -// ------------------------------------- LCD_CRSR_IMG66 ----------------------------------------- -#define LCD_CRSR_IMG66_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG66: CRSR_IMG Position */ -#define LCD_CRSR_IMG66_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG66_CRSR_IMG_Pos) /*!< LCD CRSR_IMG66: CRSR_IMG Mask */ +/* ----------------------------- SGPIO_SET_STATUS_3 ----------------------------- */ +#define SGPIO_SET_STATUS_3_SET_STATUS_INPI_Pos 0 /*!< SGPIO SET_STATUS_3: SET_STATUS_INPI Position */ +#define SGPIO_SET_STATUS_3_SET_STATUS_INPI_Msk (0x0000ffffUL << SGPIO_SET_STATUS_3_SET_STATUS_INPI_Pos)/*!< SGPIO SET_STATUS_3: SET_STATUS_INPI Mask */ -// ------------------------------------- LCD_CRSR_IMG67 ----------------------------------------- -#define LCD_CRSR_IMG67_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG67: CRSR_IMG Position */ -#define LCD_CRSR_IMG67_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG67_CRSR_IMG_Pos) /*!< LCD CRSR_IMG67: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG68 ----------------------------------------- -#define LCD_CRSR_IMG68_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG68: CRSR_IMG Position */ -#define LCD_CRSR_IMG68_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG68_CRSR_IMG_Pos) /*!< LCD CRSR_IMG68: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG69 ----------------------------------------- -#define LCD_CRSR_IMG69_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG69: CRSR_IMG Position */ -#define LCD_CRSR_IMG69_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG69_CRSR_IMG_Pos) /*!< LCD CRSR_IMG69: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG70 ----------------------------------------- -#define LCD_CRSR_IMG70_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG70: CRSR_IMG Position */ -#define LCD_CRSR_IMG70_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG70_CRSR_IMG_Pos) /*!< LCD CRSR_IMG70: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG71 ----------------------------------------- -#define LCD_CRSR_IMG71_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG71: CRSR_IMG Position */ -#define LCD_CRSR_IMG71_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG71_CRSR_IMG_Pos) /*!< LCD CRSR_IMG71: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG72 ----------------------------------------- -#define LCD_CRSR_IMG72_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG72: CRSR_IMG Position */ -#define LCD_CRSR_IMG72_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG72_CRSR_IMG_Pos) /*!< LCD CRSR_IMG72: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG73 ----------------------------------------- -#define LCD_CRSR_IMG73_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG73: CRSR_IMG Position */ -#define LCD_CRSR_IMG73_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG73_CRSR_IMG_Pos) /*!< LCD CRSR_IMG73: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG74 ----------------------------------------- -#define LCD_CRSR_IMG74_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG74: CRSR_IMG Position */ -#define LCD_CRSR_IMG74_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG74_CRSR_IMG_Pos) /*!< LCD CRSR_IMG74: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG75 ----------------------------------------- -#define LCD_CRSR_IMG75_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG75: CRSR_IMG Position */ -#define LCD_CRSR_IMG75_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG75_CRSR_IMG_Pos) /*!< LCD CRSR_IMG75: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG76 ----------------------------------------- -#define LCD_CRSR_IMG76_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG76: CRSR_IMG Position */ -#define LCD_CRSR_IMG76_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG76_CRSR_IMG_Pos) /*!< LCD CRSR_IMG76: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG77 ----------------------------------------- -#define LCD_CRSR_IMG77_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG77: CRSR_IMG Position */ -#define LCD_CRSR_IMG77_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG77_CRSR_IMG_Pos) /*!< LCD CRSR_IMG77: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG78 ----------------------------------------- -#define LCD_CRSR_IMG78_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG78: CRSR_IMG Position */ -#define LCD_CRSR_IMG78_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG78_CRSR_IMG_Pos) /*!< LCD CRSR_IMG78: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG79 ----------------------------------------- -#define LCD_CRSR_IMG79_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG79: CRSR_IMG Position */ -#define LCD_CRSR_IMG79_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG79_CRSR_IMG_Pos) /*!< LCD CRSR_IMG79: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG80 ----------------------------------------- -#define LCD_CRSR_IMG80_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG80: CRSR_IMG Position */ -#define LCD_CRSR_IMG80_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG80_CRSR_IMG_Pos) /*!< LCD CRSR_IMG80: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG81 ----------------------------------------- -#define LCD_CRSR_IMG81_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG81: CRSR_IMG Position */ -#define LCD_CRSR_IMG81_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG81_CRSR_IMG_Pos) /*!< LCD CRSR_IMG81: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG82 ----------------------------------------- -#define LCD_CRSR_IMG82_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG82: CRSR_IMG Position */ -#define LCD_CRSR_IMG82_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG82_CRSR_IMG_Pos) /*!< LCD CRSR_IMG82: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG83 ----------------------------------------- -#define LCD_CRSR_IMG83_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG83: CRSR_IMG Position */ -#define LCD_CRSR_IMG83_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG83_CRSR_IMG_Pos) /*!< LCD CRSR_IMG83: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG84 ----------------------------------------- -#define LCD_CRSR_IMG84_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG84: CRSR_IMG Position */ -#define LCD_CRSR_IMG84_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG84_CRSR_IMG_Pos) /*!< LCD CRSR_IMG84: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG85 ----------------------------------------- -#define LCD_CRSR_IMG85_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG85: CRSR_IMG Position */ -#define LCD_CRSR_IMG85_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG85_CRSR_IMG_Pos) /*!< LCD CRSR_IMG85: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG86 ----------------------------------------- -#define LCD_CRSR_IMG86_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG86: CRSR_IMG Position */ -#define LCD_CRSR_IMG86_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG86_CRSR_IMG_Pos) /*!< LCD CRSR_IMG86: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG87 ----------------------------------------- -#define LCD_CRSR_IMG87_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG87: CRSR_IMG Position */ -#define LCD_CRSR_IMG87_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG87_CRSR_IMG_Pos) /*!< LCD CRSR_IMG87: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG88 ----------------------------------------- -#define LCD_CRSR_IMG88_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG88: CRSR_IMG Position */ -#define LCD_CRSR_IMG88_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG88_CRSR_IMG_Pos) /*!< LCD CRSR_IMG88: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG89 ----------------------------------------- -#define LCD_CRSR_IMG89_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG89: CRSR_IMG Position */ -#define LCD_CRSR_IMG89_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG89_CRSR_IMG_Pos) /*!< LCD CRSR_IMG89: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG90 ----------------------------------------- -#define LCD_CRSR_IMG90_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG90: CRSR_IMG Position */ -#define LCD_CRSR_IMG90_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG90_CRSR_IMG_Pos) /*!< LCD CRSR_IMG90: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG91 ----------------------------------------- -#define LCD_CRSR_IMG91_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG91: CRSR_IMG Position */ -#define LCD_CRSR_IMG91_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG91_CRSR_IMG_Pos) /*!< LCD CRSR_IMG91: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG92 ----------------------------------------- -#define LCD_CRSR_IMG92_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG92: CRSR_IMG Position */ -#define LCD_CRSR_IMG92_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG92_CRSR_IMG_Pos) /*!< LCD CRSR_IMG92: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG93 ----------------------------------------- -#define LCD_CRSR_IMG93_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG93: CRSR_IMG Position */ -#define LCD_CRSR_IMG93_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG93_CRSR_IMG_Pos) /*!< LCD CRSR_IMG93: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG94 ----------------------------------------- -#define LCD_CRSR_IMG94_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG94: CRSR_IMG Position */ -#define LCD_CRSR_IMG94_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG94_CRSR_IMG_Pos) /*!< LCD CRSR_IMG94: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG95 ----------------------------------------- -#define LCD_CRSR_IMG95_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG95: CRSR_IMG Position */ -#define LCD_CRSR_IMG95_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG95_CRSR_IMG_Pos) /*!< LCD CRSR_IMG95: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG96 ----------------------------------------- -#define LCD_CRSR_IMG96_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG96: CRSR_IMG Position */ -#define LCD_CRSR_IMG96_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG96_CRSR_IMG_Pos) /*!< LCD CRSR_IMG96: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG97 ----------------------------------------- -#define LCD_CRSR_IMG97_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG97: CRSR_IMG Position */ -#define LCD_CRSR_IMG97_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG97_CRSR_IMG_Pos) /*!< LCD CRSR_IMG97: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG98 ----------------------------------------- -#define LCD_CRSR_IMG98_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG98: CRSR_IMG Position */ -#define LCD_CRSR_IMG98_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG98_CRSR_IMG_Pos) /*!< LCD CRSR_IMG98: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG99 ----------------------------------------- -#define LCD_CRSR_IMG99_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG99: CRSR_IMG Position */ -#define LCD_CRSR_IMG99_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG99_CRSR_IMG_Pos) /*!< LCD CRSR_IMG99: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG100 ---------------------------------------- -#define LCD_CRSR_IMG100_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG100: CRSR_IMG Position */ -#define LCD_CRSR_IMG100_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG100_CRSR_IMG_Pos) /*!< LCD CRSR_IMG100: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG101 ---------------------------------------- -#define LCD_CRSR_IMG101_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG101: CRSR_IMG Position */ -#define LCD_CRSR_IMG101_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG101_CRSR_IMG_Pos) /*!< LCD CRSR_IMG101: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG102 ---------------------------------------- -#define LCD_CRSR_IMG102_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG102: CRSR_IMG Position */ -#define LCD_CRSR_IMG102_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG102_CRSR_IMG_Pos) /*!< LCD CRSR_IMG102: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG103 ---------------------------------------- -#define LCD_CRSR_IMG103_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG103: CRSR_IMG Position */ -#define LCD_CRSR_IMG103_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG103_CRSR_IMG_Pos) /*!< LCD CRSR_IMG103: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG104 ---------------------------------------- -#define LCD_CRSR_IMG104_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG104: CRSR_IMG Position */ -#define LCD_CRSR_IMG104_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG104_CRSR_IMG_Pos) /*!< LCD CRSR_IMG104: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG105 ---------------------------------------- -#define LCD_CRSR_IMG105_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG105: CRSR_IMG Position */ -#define LCD_CRSR_IMG105_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG105_CRSR_IMG_Pos) /*!< LCD CRSR_IMG105: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG106 ---------------------------------------- -#define LCD_CRSR_IMG106_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG106: CRSR_IMG Position */ -#define LCD_CRSR_IMG106_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG106_CRSR_IMG_Pos) /*!< LCD CRSR_IMG106: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG107 ---------------------------------------- -#define LCD_CRSR_IMG107_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG107: CRSR_IMG Position */ -#define LCD_CRSR_IMG107_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG107_CRSR_IMG_Pos) /*!< LCD CRSR_IMG107: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG108 ---------------------------------------- -#define LCD_CRSR_IMG108_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG108: CRSR_IMG Position */ -#define LCD_CRSR_IMG108_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG108_CRSR_IMG_Pos) /*!< LCD CRSR_IMG108: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG109 ---------------------------------------- -#define LCD_CRSR_IMG109_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG109: CRSR_IMG Position */ -#define LCD_CRSR_IMG109_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG109_CRSR_IMG_Pos) /*!< LCD CRSR_IMG109: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG110 ---------------------------------------- -#define LCD_CRSR_IMG110_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG110: CRSR_IMG Position */ -#define LCD_CRSR_IMG110_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG110_CRSR_IMG_Pos) /*!< LCD CRSR_IMG110: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG111 ---------------------------------------- -#define LCD_CRSR_IMG111_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG111: CRSR_IMG Position */ -#define LCD_CRSR_IMG111_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG111_CRSR_IMG_Pos) /*!< LCD CRSR_IMG111: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG112 ---------------------------------------- -#define LCD_CRSR_IMG112_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG112: CRSR_IMG Position */ -#define LCD_CRSR_IMG112_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG112_CRSR_IMG_Pos) /*!< LCD CRSR_IMG112: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG113 ---------------------------------------- -#define LCD_CRSR_IMG113_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG113: CRSR_IMG Position */ -#define LCD_CRSR_IMG113_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG113_CRSR_IMG_Pos) /*!< LCD CRSR_IMG113: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG114 ---------------------------------------- -#define LCD_CRSR_IMG114_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG114: CRSR_IMG Position */ -#define LCD_CRSR_IMG114_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG114_CRSR_IMG_Pos) /*!< LCD CRSR_IMG114: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG115 ---------------------------------------- -#define LCD_CRSR_IMG115_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG115: CRSR_IMG Position */ -#define LCD_CRSR_IMG115_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG115_CRSR_IMG_Pos) /*!< LCD CRSR_IMG115: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG116 ---------------------------------------- -#define LCD_CRSR_IMG116_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG116: CRSR_IMG Position */ -#define LCD_CRSR_IMG116_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG116_CRSR_IMG_Pos) /*!< LCD CRSR_IMG116: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG117 ---------------------------------------- -#define LCD_CRSR_IMG117_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG117: CRSR_IMG Position */ -#define LCD_CRSR_IMG117_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG117_CRSR_IMG_Pos) /*!< LCD CRSR_IMG117: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG118 ---------------------------------------- -#define LCD_CRSR_IMG118_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG118: CRSR_IMG Position */ -#define LCD_CRSR_IMG118_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG118_CRSR_IMG_Pos) /*!< LCD CRSR_IMG118: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG119 ---------------------------------------- -#define LCD_CRSR_IMG119_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG119: CRSR_IMG Position */ -#define LCD_CRSR_IMG119_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG119_CRSR_IMG_Pos) /*!< LCD CRSR_IMG119: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG120 ---------------------------------------- -#define LCD_CRSR_IMG120_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG120: CRSR_IMG Position */ -#define LCD_CRSR_IMG120_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG120_CRSR_IMG_Pos) /*!< LCD CRSR_IMG120: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG121 ---------------------------------------- -#define LCD_CRSR_IMG121_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG121: CRSR_IMG Position */ -#define LCD_CRSR_IMG121_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG121_CRSR_IMG_Pos) /*!< LCD CRSR_IMG121: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG122 ---------------------------------------- -#define LCD_CRSR_IMG122_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG122: CRSR_IMG Position */ -#define LCD_CRSR_IMG122_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG122_CRSR_IMG_Pos) /*!< LCD CRSR_IMG122: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG123 ---------------------------------------- -#define LCD_CRSR_IMG123_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG123: CRSR_IMG Position */ -#define LCD_CRSR_IMG123_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG123_CRSR_IMG_Pos) /*!< LCD CRSR_IMG123: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG124 ---------------------------------------- -#define LCD_CRSR_IMG124_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG124: CRSR_IMG Position */ -#define LCD_CRSR_IMG124_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG124_CRSR_IMG_Pos) /*!< LCD CRSR_IMG124: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG125 ---------------------------------------- -#define LCD_CRSR_IMG125_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG125: CRSR_IMG Position */ -#define LCD_CRSR_IMG125_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG125_CRSR_IMG_Pos) /*!< LCD CRSR_IMG125: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG126 ---------------------------------------- -#define LCD_CRSR_IMG126_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG126: CRSR_IMG Position */ -#define LCD_CRSR_IMG126_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG126_CRSR_IMG_Pos) /*!< LCD CRSR_IMG126: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG127 ---------------------------------------- -#define LCD_CRSR_IMG127_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG127: CRSR_IMG Position */ -#define LCD_CRSR_IMG127_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG127_CRSR_IMG_Pos) /*!< LCD CRSR_IMG127: CRSR_IMG Mask */ +#endif -// ------------------------------------- LCD_CRSR_IMG128 ---------------------------------------- -#define LCD_CRSR_IMG128_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG128: CRSR_IMG Position */ -#define LCD_CRSR_IMG128_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG128_CRSR_IMG_Pos) /*!< LCD CRSR_IMG128: CRSR_IMG Mask */ +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define LPC_SCT_BASE 0x40000000UL +#define LPC_GPDMA_BASE 0x40002000UL +#define LPC_SPIFI_BASE 0x40003000UL +#define LPC_SDMMC_BASE 0x40004000UL +#define LPC_EMC_BASE 0x40005000UL +#define LPC_USB0_BASE 0x40006000UL +#define LPC_USB1_BASE 0x40007000UL +#define LPC_LCD_BASE 0x40008000UL +#define LPC_EEPROM_BASE 0x4000E000UL +#define LPC_ETHERNET_BASE 0x40010000UL +#define LPC_ATIMER_BASE 0x40040000UL +#define LPC_REGFILE_BASE 0x40041000UL +#define LPC_PMC_BASE 0x40042000UL +#define LPC_CREG_BASE 0x40043000UL +#define LPC_EVENTROUTER_BASE 0x40044000UL +#define LPC_RTC_BASE 0x40046000UL +#define LPC_CGU_BASE 0x40050000UL +#define LPC_CCU1_BASE 0x40051000UL +#define LPC_CCU2_BASE 0x40052000UL +#define LPC_RGU_BASE 0x40053000UL +#define LPC_WWDT_BASE 0x40080000UL +#define LPC_USART0_BASE 0x40081000UL +#define LPC_USART2_BASE 0x400C1000UL +#define LPC_USART3_BASE 0x400C2000UL +#define LPC_UART1_BASE 0x40082000UL +#define LPC_SSP0_BASE 0x40083000UL +#define LPC_SSP1_BASE 0x400C5000UL +#define LPC_TIMER0_BASE 0x40084000UL +#define LPC_TIMER1_BASE 0x40085000UL +#define LPC_TIMER2_BASE 0x400C3000UL +#define LPC_TIMER3_BASE 0x400C4000UL +#define LPC_SCU_BASE 0x40086000UL +#define LPC_GPIO_PIN_INT_BASE 0x40087000UL +#define LPC_GPIO_GROUP_INT0_BASE 0x40088000UL +#define LPC_GPIO_GROUP_INT1_BASE 0x40089000UL +#define LPC_MCPWM_BASE 0x400A0000UL +#define LPC_I2C0_BASE 0x400A1000UL +#define LPC_I2C1_BASE 0x400E0000UL +#define LPC_I2S0_BASE 0x400A2000UL +#define LPC_I2S1_BASE 0x400A3000UL +#define LPC_C_CAN1_BASE 0x400A4000UL +#define LPC_RITIMER_BASE 0x400C0000UL +#define LPC_QEI_BASE 0x400C6000UL +#define LPC_GIMA_BASE 0x400C7000UL +#define LPC_DAC_BASE 0x400E1000UL +#define LPC_C_CAN0_BASE 0x400E2000UL +#define LPC_ADC0_BASE 0x400E3000UL +#define LPC_ADC1_BASE 0x400E4000UL +#define LPC_ADCHS_BASE 0x400F0000UL +#define LPC_GPIO_PORT_BASE 0x400F4000UL +#define LPC_SPI_BASE 0x40100000UL +#define LPC_SGPIO_BASE 0x40101000UL + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define LPC_SCT ((LPC_SCT_Type *) LPC_SCT_BASE) +#define LPC_GPDMA ((LPC_GPDMA_Type *) LPC_GPDMA_BASE) +#define LPC_SPIFI ((LPC_SPIFI_Type *) LPC_SPIFI_BASE) +#define LPC_SDMMC ((LPC_SDMMC_Type *) LPC_SDMMC_BASE) +#define LPC_EMC ((LPC_EMC_Type *) LPC_EMC_BASE) +#define LPC_USB0 ((LPC_USB0_Type *) LPC_USB0_BASE) +#define LPC_USB1 ((LPC_USB1_Type *) LPC_USB1_BASE) +#define LPC_LCD ((LPC_LCD_Type *) LPC_LCD_BASE) +#define LPC_EEPROM ((LPC_EEPROM_Type *) LPC_EEPROM_BASE) +#define LPC_ETHERNET ((LPC_ETHERNET_Type *) LPC_ETHERNET_BASE) +#define LPC_ATIMER ((LPC_ATIMER_Type *) LPC_ATIMER_BASE) +#define LPC_REGFILE ((LPC_REGFILE_Type *) LPC_REGFILE_BASE) +#define LPC_PMC ((LPC_PMC_Type *) LPC_PMC_BASE) +#define LPC_CREG ((LPC_CREG_Type *) LPC_CREG_BASE) +#define LPC_EVENTROUTER ((LPC_EVENTROUTER_Type *) LPC_EVENTROUTER_BASE) +#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE) +#define LPC_CGU ((LPC_CGU_Type *) LPC_CGU_BASE) +#define LPC_CCU1 ((LPC_CCU1_Type *) LPC_CCU1_BASE) +#define LPC_CCU2 ((LPC_CCU2_Type *) LPC_CCU2_BASE) +#define LPC_RGU ((LPC_RGU_Type *) LPC_RGU_BASE) +#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE) +#define LPC_USART0 ((LPC_USARTn_Type *) LPC_USART0_BASE) +#define LPC_USART2 ((LPC_USARTn_Type *) LPC_USART2_BASE) +#define LPC_USART3 ((LPC_USARTn_Type *) LPC_USART3_BASE) +#define LPC_UART1 ((LPC_UART1_Type *) LPC_UART1_BASE) +#define LPC_SSP0 ((LPC_SSPn_Type *) LPC_SSP0_BASE) +#define LPC_SSP1 ((LPC_SSPn_Type *) LPC_SSP1_BASE) +#define LPC_TIMER0 ((LPC_TIMERn_Type *) LPC_TIMER0_BASE) +#define LPC_TIMER1 ((LPC_TIMERn_Type *) LPC_TIMER1_BASE) +#define LPC_TIMER2 ((LPC_TIMERn_Type *) LPC_TIMER2_BASE) +#define LPC_TIMER3 ((LPC_TIMERn_Type *) LPC_TIMER3_BASE) +#define LPC_SCU ((LPC_SCU_Type *) LPC_SCU_BASE) +#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE) +#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT0_BASE) +#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT1_BASE) +#define LPC_MCPWM ((LPC_MCPWM_Type *) LPC_MCPWM_BASE) +#define LPC_I2C0 ((LPC_I2Cn_Type *) LPC_I2C0_BASE) +#define LPC_I2C1 ((LPC_I2Cn_Type *) LPC_I2C1_BASE) +#define LPC_I2S0 ((LPC_I2Sn_Type *) LPC_I2S0_BASE) +#define LPC_I2S1 ((LPC_I2Sn_Type *) LPC_I2S1_BASE) +#define LPC_C_CAN1 ((LPC_C_CANn_Type *) LPC_C_CAN1_BASE) +#define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE) +#define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE) +#define LPC_GIMA ((LPC_GIMA_Type *) LPC_GIMA_BASE) +#define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE) +#define LPC_C_CAN0 ((LPC_C_CANn_Type *) LPC_C_CAN0_BASE) +#define LPC_ADC0 ((LPC_ADCn_Type *) LPC_ADC0_BASE) +#define LPC_ADC1 ((LPC_ADCn_Type *) LPC_ADC1_BASE) +#define LPC_ADCHS ((LPC_ADCHS_Type *) LPC_ADCHS_BASE) +#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE) +#define LPC_SPI ((LPC_SPI_Type *) LPC_SPI_BASE) +#define LPC_SGPIO ((LPC_SGPIO_Type *) LPC_SGPIO_BASE) -// ------------------------------------- LCD_CRSR_IMG129 ---------------------------------------- -#define LCD_CRSR_IMG129_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG129: CRSR_IMG Position */ -#define LCD_CRSR_IMG129_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG129_CRSR_IMG_Pos) /*!< LCD CRSR_IMG129: CRSR_IMG Mask */ -// ------------------------------------- LCD_CRSR_IMG130 ---------------------------------------- -#define LCD_CRSR_IMG130_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG130: CRSR_IMG Position */ -#define LCD_CRSR_IMG130_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG130_CRSR_IMG_Pos) /*!< LCD CRSR_IMG130: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG131 ---------------------------------------- -#define LCD_CRSR_IMG131_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG131: CRSR_IMG Position */ -#define LCD_CRSR_IMG131_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG131_CRSR_IMG_Pos) /*!< LCD CRSR_IMG131: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG132 ---------------------------------------- -#define LCD_CRSR_IMG132_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG132: CRSR_IMG Position */ -#define LCD_CRSR_IMG132_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG132_CRSR_IMG_Pos) /*!< LCD CRSR_IMG132: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG133 ---------------------------------------- -#define LCD_CRSR_IMG133_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG133: CRSR_IMG Position */ -#define LCD_CRSR_IMG133_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG133_CRSR_IMG_Pos) /*!< LCD CRSR_IMG133: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG134 ---------------------------------------- -#define LCD_CRSR_IMG134_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG134: CRSR_IMG Position */ -#define LCD_CRSR_IMG134_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG134_CRSR_IMG_Pos) /*!< LCD CRSR_IMG134: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG135 ---------------------------------------- -#define LCD_CRSR_IMG135_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG135: CRSR_IMG Position */ -#define LCD_CRSR_IMG135_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG135_CRSR_IMG_Pos) /*!< LCD CRSR_IMG135: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG136 ---------------------------------------- -#define LCD_CRSR_IMG136_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG136: CRSR_IMG Position */ -#define LCD_CRSR_IMG136_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG136_CRSR_IMG_Pos) /*!< LCD CRSR_IMG136: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG137 ---------------------------------------- -#define LCD_CRSR_IMG137_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG137: CRSR_IMG Position */ -#define LCD_CRSR_IMG137_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG137_CRSR_IMG_Pos) /*!< LCD CRSR_IMG137: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG138 ---------------------------------------- -#define LCD_CRSR_IMG138_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG138: CRSR_IMG Position */ -#define LCD_CRSR_IMG138_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG138_CRSR_IMG_Pos) /*!< LCD CRSR_IMG138: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG139 ---------------------------------------- -#define LCD_CRSR_IMG139_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG139: CRSR_IMG Position */ -#define LCD_CRSR_IMG139_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG139_CRSR_IMG_Pos) /*!< LCD CRSR_IMG139: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG140 ---------------------------------------- -#define LCD_CRSR_IMG140_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG140: CRSR_IMG Position */ -#define LCD_CRSR_IMG140_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG140_CRSR_IMG_Pos) /*!< LCD CRSR_IMG140: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG141 ---------------------------------------- -#define LCD_CRSR_IMG141_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG141: CRSR_IMG Position */ -#define LCD_CRSR_IMG141_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG141_CRSR_IMG_Pos) /*!< LCD CRSR_IMG141: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG142 ---------------------------------------- -#define LCD_CRSR_IMG142_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG142: CRSR_IMG Position */ -#define LCD_CRSR_IMG142_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG142_CRSR_IMG_Pos) /*!< LCD CRSR_IMG142: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG143 ---------------------------------------- -#define LCD_CRSR_IMG143_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG143: CRSR_IMG Position */ -#define LCD_CRSR_IMG143_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG143_CRSR_IMG_Pos) /*!< LCD CRSR_IMG143: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG144 ---------------------------------------- -#define LCD_CRSR_IMG144_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG144: CRSR_IMG Position */ -#define LCD_CRSR_IMG144_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG144_CRSR_IMG_Pos) /*!< LCD CRSR_IMG144: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG145 ---------------------------------------- -#define LCD_CRSR_IMG145_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG145: CRSR_IMG Position */ -#define LCD_CRSR_IMG145_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG145_CRSR_IMG_Pos) /*!< LCD CRSR_IMG145: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG146 ---------------------------------------- -#define LCD_CRSR_IMG146_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG146: CRSR_IMG Position */ -#define LCD_CRSR_IMG146_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG146_CRSR_IMG_Pos) /*!< LCD CRSR_IMG146: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG147 ---------------------------------------- -#define LCD_CRSR_IMG147_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG147: CRSR_IMG Position */ -#define LCD_CRSR_IMG147_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG147_CRSR_IMG_Pos) /*!< LCD CRSR_IMG147: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG148 ---------------------------------------- -#define LCD_CRSR_IMG148_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG148: CRSR_IMG Position */ -#define LCD_CRSR_IMG148_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG148_CRSR_IMG_Pos) /*!< LCD CRSR_IMG148: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG149 ---------------------------------------- -#define LCD_CRSR_IMG149_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG149: CRSR_IMG Position */ -#define LCD_CRSR_IMG149_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG149_CRSR_IMG_Pos) /*!< LCD CRSR_IMG149: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG150 ---------------------------------------- -#define LCD_CRSR_IMG150_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG150: CRSR_IMG Position */ -#define LCD_CRSR_IMG150_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG150_CRSR_IMG_Pos) /*!< LCD CRSR_IMG150: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG151 ---------------------------------------- -#define LCD_CRSR_IMG151_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG151: CRSR_IMG Position */ -#define LCD_CRSR_IMG151_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG151_CRSR_IMG_Pos) /*!< LCD CRSR_IMG151: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG152 ---------------------------------------- -#define LCD_CRSR_IMG152_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG152: CRSR_IMG Position */ -#define LCD_CRSR_IMG152_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG152_CRSR_IMG_Pos) /*!< LCD CRSR_IMG152: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG153 ---------------------------------------- -#define LCD_CRSR_IMG153_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG153: CRSR_IMG Position */ -#define LCD_CRSR_IMG153_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG153_CRSR_IMG_Pos) /*!< LCD CRSR_IMG153: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG154 ---------------------------------------- -#define LCD_CRSR_IMG154_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG154: CRSR_IMG Position */ -#define LCD_CRSR_IMG154_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG154_CRSR_IMG_Pos) /*!< LCD CRSR_IMG154: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG155 ---------------------------------------- -#define LCD_CRSR_IMG155_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG155: CRSR_IMG Position */ -#define LCD_CRSR_IMG155_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG155_CRSR_IMG_Pos) /*!< LCD CRSR_IMG155: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG156 ---------------------------------------- -#define LCD_CRSR_IMG156_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG156: CRSR_IMG Position */ -#define LCD_CRSR_IMG156_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG156_CRSR_IMG_Pos) /*!< LCD CRSR_IMG156: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG157 ---------------------------------------- -#define LCD_CRSR_IMG157_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG157: CRSR_IMG Position */ -#define LCD_CRSR_IMG157_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG157_CRSR_IMG_Pos) /*!< LCD CRSR_IMG157: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG158 ---------------------------------------- -#define LCD_CRSR_IMG158_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG158: CRSR_IMG Position */ -#define LCD_CRSR_IMG158_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG158_CRSR_IMG_Pos) /*!< LCD CRSR_IMG158: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG159 ---------------------------------------- -#define LCD_CRSR_IMG159_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG159: CRSR_IMG Position */ -#define LCD_CRSR_IMG159_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG159_CRSR_IMG_Pos) /*!< LCD CRSR_IMG159: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG160 ---------------------------------------- -#define LCD_CRSR_IMG160_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG160: CRSR_IMG Position */ -#define LCD_CRSR_IMG160_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG160_CRSR_IMG_Pos) /*!< LCD CRSR_IMG160: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG161 ---------------------------------------- -#define LCD_CRSR_IMG161_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG161: CRSR_IMG Position */ -#define LCD_CRSR_IMG161_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG161_CRSR_IMG_Pos) /*!< LCD CRSR_IMG161: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG162 ---------------------------------------- -#define LCD_CRSR_IMG162_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG162: CRSR_IMG Position */ -#define LCD_CRSR_IMG162_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG162_CRSR_IMG_Pos) /*!< LCD CRSR_IMG162: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG163 ---------------------------------------- -#define LCD_CRSR_IMG163_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG163: CRSR_IMG Position */ -#define LCD_CRSR_IMG163_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG163_CRSR_IMG_Pos) /*!< LCD CRSR_IMG163: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG164 ---------------------------------------- -#define LCD_CRSR_IMG164_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG164: CRSR_IMG Position */ -#define LCD_CRSR_IMG164_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG164_CRSR_IMG_Pos) /*!< LCD CRSR_IMG164: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG165 ---------------------------------------- -#define LCD_CRSR_IMG165_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG165: CRSR_IMG Position */ -#define LCD_CRSR_IMG165_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG165_CRSR_IMG_Pos) /*!< LCD CRSR_IMG165: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG166 ---------------------------------------- -#define LCD_CRSR_IMG166_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG166: CRSR_IMG Position */ -#define LCD_CRSR_IMG166_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG166_CRSR_IMG_Pos) /*!< LCD CRSR_IMG166: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG167 ---------------------------------------- -#define LCD_CRSR_IMG167_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG167: CRSR_IMG Position */ -#define LCD_CRSR_IMG167_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG167_CRSR_IMG_Pos) /*!< LCD CRSR_IMG167: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG168 ---------------------------------------- -#define LCD_CRSR_IMG168_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG168: CRSR_IMG Position */ -#define LCD_CRSR_IMG168_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG168_CRSR_IMG_Pos) /*!< LCD CRSR_IMG168: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG169 ---------------------------------------- -#define LCD_CRSR_IMG169_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG169: CRSR_IMG Position */ -#define LCD_CRSR_IMG169_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG169_CRSR_IMG_Pos) /*!< LCD CRSR_IMG169: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG170 ---------------------------------------- -#define LCD_CRSR_IMG170_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG170: CRSR_IMG Position */ -#define LCD_CRSR_IMG170_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG170_CRSR_IMG_Pos) /*!< LCD CRSR_IMG170: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG171 ---------------------------------------- -#define LCD_CRSR_IMG171_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG171: CRSR_IMG Position */ -#define LCD_CRSR_IMG171_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG171_CRSR_IMG_Pos) /*!< LCD CRSR_IMG171: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG172 ---------------------------------------- -#define LCD_CRSR_IMG172_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG172: CRSR_IMG Position */ -#define LCD_CRSR_IMG172_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG172_CRSR_IMG_Pos) /*!< LCD CRSR_IMG172: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG173 ---------------------------------------- -#define LCD_CRSR_IMG173_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG173: CRSR_IMG Position */ -#define LCD_CRSR_IMG173_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG173_CRSR_IMG_Pos) /*!< LCD CRSR_IMG173: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG174 ---------------------------------------- -#define LCD_CRSR_IMG174_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG174: CRSR_IMG Position */ -#define LCD_CRSR_IMG174_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG174_CRSR_IMG_Pos) /*!< LCD CRSR_IMG174: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG175 ---------------------------------------- -#define LCD_CRSR_IMG175_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG175: CRSR_IMG Position */ -#define LCD_CRSR_IMG175_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG175_CRSR_IMG_Pos) /*!< LCD CRSR_IMG175: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG176 ---------------------------------------- -#define LCD_CRSR_IMG176_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG176: CRSR_IMG Position */ -#define LCD_CRSR_IMG176_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG176_CRSR_IMG_Pos) /*!< LCD CRSR_IMG176: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG177 ---------------------------------------- -#define LCD_CRSR_IMG177_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG177: CRSR_IMG Position */ -#define LCD_CRSR_IMG177_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG177_CRSR_IMG_Pos) /*!< LCD CRSR_IMG177: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG178 ---------------------------------------- -#define LCD_CRSR_IMG178_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG178: CRSR_IMG Position */ -#define LCD_CRSR_IMG178_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG178_CRSR_IMG_Pos) /*!< LCD CRSR_IMG178: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG179 ---------------------------------------- -#define LCD_CRSR_IMG179_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG179: CRSR_IMG Position */ -#define LCD_CRSR_IMG179_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG179_CRSR_IMG_Pos) /*!< LCD CRSR_IMG179: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG180 ---------------------------------------- -#define LCD_CRSR_IMG180_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG180: CRSR_IMG Position */ -#define LCD_CRSR_IMG180_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG180_CRSR_IMG_Pos) /*!< LCD CRSR_IMG180: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG181 ---------------------------------------- -#define LCD_CRSR_IMG181_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG181: CRSR_IMG Position */ -#define LCD_CRSR_IMG181_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG181_CRSR_IMG_Pos) /*!< LCD CRSR_IMG181: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG182 ---------------------------------------- -#define LCD_CRSR_IMG182_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG182: CRSR_IMG Position */ -#define LCD_CRSR_IMG182_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG182_CRSR_IMG_Pos) /*!< LCD CRSR_IMG182: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG183 ---------------------------------------- -#define LCD_CRSR_IMG183_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG183: CRSR_IMG Position */ -#define LCD_CRSR_IMG183_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG183_CRSR_IMG_Pos) /*!< LCD CRSR_IMG183: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG184 ---------------------------------------- -#define LCD_CRSR_IMG184_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG184: CRSR_IMG Position */ -#define LCD_CRSR_IMG184_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG184_CRSR_IMG_Pos) /*!< LCD CRSR_IMG184: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG185 ---------------------------------------- -#define LCD_CRSR_IMG185_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG185: CRSR_IMG Position */ -#define LCD_CRSR_IMG185_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG185_CRSR_IMG_Pos) /*!< LCD CRSR_IMG185: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG186 ---------------------------------------- -#define LCD_CRSR_IMG186_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG186: CRSR_IMG Position */ -#define LCD_CRSR_IMG186_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG186_CRSR_IMG_Pos) /*!< LCD CRSR_IMG186: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG187 ---------------------------------------- -#define LCD_CRSR_IMG187_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG187: CRSR_IMG Position */ -#define LCD_CRSR_IMG187_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG187_CRSR_IMG_Pos) /*!< LCD CRSR_IMG187: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG188 ---------------------------------------- -#define LCD_CRSR_IMG188_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG188: CRSR_IMG Position */ -#define LCD_CRSR_IMG188_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG188_CRSR_IMG_Pos) /*!< LCD CRSR_IMG188: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG189 ---------------------------------------- -#define LCD_CRSR_IMG189_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG189: CRSR_IMG Position */ -#define LCD_CRSR_IMG189_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG189_CRSR_IMG_Pos) /*!< LCD CRSR_IMG189: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG190 ---------------------------------------- -#define LCD_CRSR_IMG190_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG190: CRSR_IMG Position */ -#define LCD_CRSR_IMG190_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG190_CRSR_IMG_Pos) /*!< LCD CRSR_IMG190: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG191 ---------------------------------------- -#define LCD_CRSR_IMG191_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG191: CRSR_IMG Position */ -#define LCD_CRSR_IMG191_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG191_CRSR_IMG_Pos) /*!< LCD CRSR_IMG191: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG192 ---------------------------------------- -#define LCD_CRSR_IMG192_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG192: CRSR_IMG Position */ -#define LCD_CRSR_IMG192_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG192_CRSR_IMG_Pos) /*!< LCD CRSR_IMG192: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG193 ---------------------------------------- -#define LCD_CRSR_IMG193_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG193: CRSR_IMG Position */ -#define LCD_CRSR_IMG193_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG193_CRSR_IMG_Pos) /*!< LCD CRSR_IMG193: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG194 ---------------------------------------- -#define LCD_CRSR_IMG194_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG194: CRSR_IMG Position */ -#define LCD_CRSR_IMG194_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG194_CRSR_IMG_Pos) /*!< LCD CRSR_IMG194: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG195 ---------------------------------------- -#define LCD_CRSR_IMG195_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG195: CRSR_IMG Position */ -#define LCD_CRSR_IMG195_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG195_CRSR_IMG_Pos) /*!< LCD CRSR_IMG195: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG196 ---------------------------------------- -#define LCD_CRSR_IMG196_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG196: CRSR_IMG Position */ -#define LCD_CRSR_IMG196_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG196_CRSR_IMG_Pos) /*!< LCD CRSR_IMG196: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG197 ---------------------------------------- -#define LCD_CRSR_IMG197_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG197: CRSR_IMG Position */ -#define LCD_CRSR_IMG197_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG197_CRSR_IMG_Pos) /*!< LCD CRSR_IMG197: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG198 ---------------------------------------- -#define LCD_CRSR_IMG198_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG198: CRSR_IMG Position */ -#define LCD_CRSR_IMG198_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG198_CRSR_IMG_Pos) /*!< LCD CRSR_IMG198: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG199 ---------------------------------------- -#define LCD_CRSR_IMG199_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG199: CRSR_IMG Position */ -#define LCD_CRSR_IMG199_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG199_CRSR_IMG_Pos) /*!< LCD CRSR_IMG199: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG200 ---------------------------------------- -#define LCD_CRSR_IMG200_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG200: CRSR_IMG Position */ -#define LCD_CRSR_IMG200_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG200_CRSR_IMG_Pos) /*!< LCD CRSR_IMG200: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG201 ---------------------------------------- -#define LCD_CRSR_IMG201_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG201: CRSR_IMG Position */ -#define LCD_CRSR_IMG201_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG201_CRSR_IMG_Pos) /*!< LCD CRSR_IMG201: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG202 ---------------------------------------- -#define LCD_CRSR_IMG202_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG202: CRSR_IMG Position */ -#define LCD_CRSR_IMG202_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG202_CRSR_IMG_Pos) /*!< LCD CRSR_IMG202: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG203 ---------------------------------------- -#define LCD_CRSR_IMG203_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG203: CRSR_IMG Position */ -#define LCD_CRSR_IMG203_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG203_CRSR_IMG_Pos) /*!< LCD CRSR_IMG203: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG204 ---------------------------------------- -#define LCD_CRSR_IMG204_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG204: CRSR_IMG Position */ -#define LCD_CRSR_IMG204_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG204_CRSR_IMG_Pos) /*!< LCD CRSR_IMG204: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG205 ---------------------------------------- -#define LCD_CRSR_IMG205_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG205: CRSR_IMG Position */ -#define LCD_CRSR_IMG205_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG205_CRSR_IMG_Pos) /*!< LCD CRSR_IMG205: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG206 ---------------------------------------- -#define LCD_CRSR_IMG206_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG206: CRSR_IMG Position */ -#define LCD_CRSR_IMG206_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG206_CRSR_IMG_Pos) /*!< LCD CRSR_IMG206: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG207 ---------------------------------------- -#define LCD_CRSR_IMG207_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG207: CRSR_IMG Position */ -#define LCD_CRSR_IMG207_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG207_CRSR_IMG_Pos) /*!< LCD CRSR_IMG207: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG208 ---------------------------------------- -#define LCD_CRSR_IMG208_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG208: CRSR_IMG Position */ -#define LCD_CRSR_IMG208_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG208_CRSR_IMG_Pos) /*!< LCD CRSR_IMG208: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG209 ---------------------------------------- -#define LCD_CRSR_IMG209_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG209: CRSR_IMG Position */ -#define LCD_CRSR_IMG209_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG209_CRSR_IMG_Pos) /*!< LCD CRSR_IMG209: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG210 ---------------------------------------- -#define LCD_CRSR_IMG210_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG210: CRSR_IMG Position */ -#define LCD_CRSR_IMG210_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG210_CRSR_IMG_Pos) /*!< LCD CRSR_IMG210: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG211 ---------------------------------------- -#define LCD_CRSR_IMG211_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG211: CRSR_IMG Position */ -#define LCD_CRSR_IMG211_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG211_CRSR_IMG_Pos) /*!< LCD CRSR_IMG211: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG212 ---------------------------------------- -#define LCD_CRSR_IMG212_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG212: CRSR_IMG Position */ -#define LCD_CRSR_IMG212_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG212_CRSR_IMG_Pos) /*!< LCD CRSR_IMG212: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG213 ---------------------------------------- -#define LCD_CRSR_IMG213_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG213: CRSR_IMG Position */ -#define LCD_CRSR_IMG213_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG213_CRSR_IMG_Pos) /*!< LCD CRSR_IMG213: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG214 ---------------------------------------- -#define LCD_CRSR_IMG214_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG214: CRSR_IMG Position */ -#define LCD_CRSR_IMG214_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG214_CRSR_IMG_Pos) /*!< LCD CRSR_IMG214: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG215 ---------------------------------------- -#define LCD_CRSR_IMG215_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG215: CRSR_IMG Position */ -#define LCD_CRSR_IMG215_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG215_CRSR_IMG_Pos) /*!< LCD CRSR_IMG215: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG216 ---------------------------------------- -#define LCD_CRSR_IMG216_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG216: CRSR_IMG Position */ -#define LCD_CRSR_IMG216_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG216_CRSR_IMG_Pos) /*!< LCD CRSR_IMG216: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG217 ---------------------------------------- -#define LCD_CRSR_IMG217_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG217: CRSR_IMG Position */ -#define LCD_CRSR_IMG217_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG217_CRSR_IMG_Pos) /*!< LCD CRSR_IMG217: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG218 ---------------------------------------- -#define LCD_CRSR_IMG218_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG218: CRSR_IMG Position */ -#define LCD_CRSR_IMG218_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG218_CRSR_IMG_Pos) /*!< LCD CRSR_IMG218: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG219 ---------------------------------------- -#define LCD_CRSR_IMG219_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG219: CRSR_IMG Position */ -#define LCD_CRSR_IMG219_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG219_CRSR_IMG_Pos) /*!< LCD CRSR_IMG219: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG220 ---------------------------------------- -#define LCD_CRSR_IMG220_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG220: CRSR_IMG Position */ -#define LCD_CRSR_IMG220_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG220_CRSR_IMG_Pos) /*!< LCD CRSR_IMG220: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG221 ---------------------------------------- -#define LCD_CRSR_IMG221_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG221: CRSR_IMG Position */ -#define LCD_CRSR_IMG221_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG221_CRSR_IMG_Pos) /*!< LCD CRSR_IMG221: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG222 ---------------------------------------- -#define LCD_CRSR_IMG222_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG222: CRSR_IMG Position */ -#define LCD_CRSR_IMG222_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG222_CRSR_IMG_Pos) /*!< LCD CRSR_IMG222: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG223 ---------------------------------------- -#define LCD_CRSR_IMG223_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG223: CRSR_IMG Position */ -#define LCD_CRSR_IMG223_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG223_CRSR_IMG_Pos) /*!< LCD CRSR_IMG223: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG224 ---------------------------------------- -#define LCD_CRSR_IMG224_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG224: CRSR_IMG Position */ -#define LCD_CRSR_IMG224_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG224_CRSR_IMG_Pos) /*!< LCD CRSR_IMG224: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG225 ---------------------------------------- -#define LCD_CRSR_IMG225_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG225: CRSR_IMG Position */ -#define LCD_CRSR_IMG225_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG225_CRSR_IMG_Pos) /*!< LCD CRSR_IMG225: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG226 ---------------------------------------- -#define LCD_CRSR_IMG226_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG226: CRSR_IMG Position */ -#define LCD_CRSR_IMG226_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG226_CRSR_IMG_Pos) /*!< LCD CRSR_IMG226: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG227 ---------------------------------------- -#define LCD_CRSR_IMG227_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG227: CRSR_IMG Position */ -#define LCD_CRSR_IMG227_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG227_CRSR_IMG_Pos) /*!< LCD CRSR_IMG227: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG228 ---------------------------------------- -#define LCD_CRSR_IMG228_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG228: CRSR_IMG Position */ -#define LCD_CRSR_IMG228_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG228_CRSR_IMG_Pos) /*!< LCD CRSR_IMG228: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG229 ---------------------------------------- -#define LCD_CRSR_IMG229_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG229: CRSR_IMG Position */ -#define LCD_CRSR_IMG229_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG229_CRSR_IMG_Pos) /*!< LCD CRSR_IMG229: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG230 ---------------------------------------- -#define LCD_CRSR_IMG230_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG230: CRSR_IMG Position */ -#define LCD_CRSR_IMG230_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG230_CRSR_IMG_Pos) /*!< LCD CRSR_IMG230: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG231 ---------------------------------------- -#define LCD_CRSR_IMG231_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG231: CRSR_IMG Position */ -#define LCD_CRSR_IMG231_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG231_CRSR_IMG_Pos) /*!< LCD CRSR_IMG231: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG232 ---------------------------------------- -#define LCD_CRSR_IMG232_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG232: CRSR_IMG Position */ -#define LCD_CRSR_IMG232_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG232_CRSR_IMG_Pos) /*!< LCD CRSR_IMG232: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG233 ---------------------------------------- -#define LCD_CRSR_IMG233_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG233: CRSR_IMG Position */ -#define LCD_CRSR_IMG233_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG233_CRSR_IMG_Pos) /*!< LCD CRSR_IMG233: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG234 ---------------------------------------- -#define LCD_CRSR_IMG234_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG234: CRSR_IMG Position */ -#define LCD_CRSR_IMG234_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG234_CRSR_IMG_Pos) /*!< LCD CRSR_IMG234: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG235 ---------------------------------------- -#define LCD_CRSR_IMG235_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG235: CRSR_IMG Position */ -#define LCD_CRSR_IMG235_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG235_CRSR_IMG_Pos) /*!< LCD CRSR_IMG235: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG236 ---------------------------------------- -#define LCD_CRSR_IMG236_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG236: CRSR_IMG Position */ -#define LCD_CRSR_IMG236_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG236_CRSR_IMG_Pos) /*!< LCD CRSR_IMG236: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG237 ---------------------------------------- -#define LCD_CRSR_IMG237_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG237: CRSR_IMG Position */ -#define LCD_CRSR_IMG237_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG237_CRSR_IMG_Pos) /*!< LCD CRSR_IMG237: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG238 ---------------------------------------- -#define LCD_CRSR_IMG238_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG238: CRSR_IMG Position */ -#define LCD_CRSR_IMG238_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG238_CRSR_IMG_Pos) /*!< LCD CRSR_IMG238: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG239 ---------------------------------------- -#define LCD_CRSR_IMG239_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG239: CRSR_IMG Position */ -#define LCD_CRSR_IMG239_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG239_CRSR_IMG_Pos) /*!< LCD CRSR_IMG239: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG240 ---------------------------------------- -#define LCD_CRSR_IMG240_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG240: CRSR_IMG Position */ -#define LCD_CRSR_IMG240_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG240_CRSR_IMG_Pos) /*!< LCD CRSR_IMG240: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG241 ---------------------------------------- -#define LCD_CRSR_IMG241_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG241: CRSR_IMG Position */ -#define LCD_CRSR_IMG241_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG241_CRSR_IMG_Pos) /*!< LCD CRSR_IMG241: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG242 ---------------------------------------- -#define LCD_CRSR_IMG242_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG242: CRSR_IMG Position */ -#define LCD_CRSR_IMG242_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG242_CRSR_IMG_Pos) /*!< LCD CRSR_IMG242: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG243 ---------------------------------------- -#define LCD_CRSR_IMG243_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG243: CRSR_IMG Position */ -#define LCD_CRSR_IMG243_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG243_CRSR_IMG_Pos) /*!< LCD CRSR_IMG243: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG244 ---------------------------------------- -#define LCD_CRSR_IMG244_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG244: CRSR_IMG Position */ -#define LCD_CRSR_IMG244_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG244_CRSR_IMG_Pos) /*!< LCD CRSR_IMG244: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG245 ---------------------------------------- -#define LCD_CRSR_IMG245_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG245: CRSR_IMG Position */ -#define LCD_CRSR_IMG245_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG245_CRSR_IMG_Pos) /*!< LCD CRSR_IMG245: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG246 ---------------------------------------- -#define LCD_CRSR_IMG246_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG246: CRSR_IMG Position */ -#define LCD_CRSR_IMG246_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG246_CRSR_IMG_Pos) /*!< LCD CRSR_IMG246: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG247 ---------------------------------------- -#define LCD_CRSR_IMG247_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG247: CRSR_IMG Position */ -#define LCD_CRSR_IMG247_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG247_CRSR_IMG_Pos) /*!< LCD CRSR_IMG247: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG248 ---------------------------------------- -#define LCD_CRSR_IMG248_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG248: CRSR_IMG Position */ -#define LCD_CRSR_IMG248_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG248_CRSR_IMG_Pos) /*!< LCD CRSR_IMG248: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG249 ---------------------------------------- -#define LCD_CRSR_IMG249_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG249: CRSR_IMG Position */ -#define LCD_CRSR_IMG249_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG249_CRSR_IMG_Pos) /*!< LCD CRSR_IMG249: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG250 ---------------------------------------- -#define LCD_CRSR_IMG250_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG250: CRSR_IMG Position */ -#define LCD_CRSR_IMG250_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG250_CRSR_IMG_Pos) /*!< LCD CRSR_IMG250: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG251 ---------------------------------------- -#define LCD_CRSR_IMG251_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG251: CRSR_IMG Position */ -#define LCD_CRSR_IMG251_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG251_CRSR_IMG_Pos) /*!< LCD CRSR_IMG251: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG252 ---------------------------------------- -#define LCD_CRSR_IMG252_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG252: CRSR_IMG Position */ -#define LCD_CRSR_IMG252_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG252_CRSR_IMG_Pos) /*!< LCD CRSR_IMG252: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG253 ---------------------------------------- -#define LCD_CRSR_IMG253_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG253: CRSR_IMG Position */ -#define LCD_CRSR_IMG253_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG253_CRSR_IMG_Pos) /*!< LCD CRSR_IMG253: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG254 ---------------------------------------- -#define LCD_CRSR_IMG254_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG254: CRSR_IMG Position */ -#define LCD_CRSR_IMG254_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG254_CRSR_IMG_Pos) /*!< LCD CRSR_IMG254: CRSR_IMG Mask */ - -// ------------------------------------- LCD_CRSR_IMG255 ---------------------------------------- -#define LCD_CRSR_IMG255_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG255: CRSR_IMG Position */ -#define LCD_CRSR_IMG255_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG255_CRSR_IMG_Pos) /*!< LCD CRSR_IMG255: CRSR_IMG Mask */ - -// -------------------------------------- LCD_CRSR_CTRL ----------------------------------------- -#define LCD_CRSR_CTRL_CrsrOn_Pos 0 /*!< LCD CRSR_CTRL: CrsrOn Position */ -#define LCD_CRSR_CTRL_CrsrOn_Msk (0x01UL << LCD_CRSR_CTRL_CrsrOn_Pos) /*!< LCD CRSR_CTRL: CrsrOn Mask */ -#define LCD_CRSR_CTRL_CRSRNUM1_0_Pos 4 /*!< LCD CRSR_CTRL: CRSRNUM1_0 Position */ -#define LCD_CRSR_CTRL_CRSRNUM1_0_Msk (0x03UL << LCD_CRSR_CTRL_CRSRNUM1_0_Pos) /*!< LCD CRSR_CTRL: CRSRNUM1_0 Mask */ - -// -------------------------------------- LCD_CRSR_CFG ------------------------------------------ -#define LCD_CRSR_CFG_CrsrSize_Pos 0 /*!< LCD CRSR_CFG: CrsrSize Position */ -#define LCD_CRSR_CFG_CrsrSize_Msk (0x01UL << LCD_CRSR_CFG_CrsrSize_Pos) /*!< LCD CRSR_CFG: CrsrSize Mask */ -#define LCD_CRSR_CFG_FRAMESYNC_Pos 1 /*!< LCD CRSR_CFG: FRAMESYNC Position */ -#define LCD_CRSR_CFG_FRAMESYNC_Msk (0x01UL << LCD_CRSR_CFG_FRAMESYNC_Pos) /*!< LCD CRSR_CFG: FRAMESYNC Mask */ - -// -------------------------------------- LCD_CRSR_PAL0 ----------------------------------------- -#define LCD_CRSR_PAL0_RED_Pos 0 /*!< LCD CRSR_PAL0: RED Position */ -#define LCD_CRSR_PAL0_RED_Msk (0x000000ffUL << LCD_CRSR_PAL0_RED_Pos) /*!< LCD CRSR_PAL0: RED Mask */ -#define LCD_CRSR_PAL0_GREEN_Pos 8 /*!< LCD CRSR_PAL0: GREEN Position */ -#define LCD_CRSR_PAL0_GREEN_Msk (0x000000ffUL << LCD_CRSR_PAL0_GREEN_Pos) /*!< LCD CRSR_PAL0: GREEN Mask */ -#define LCD_CRSR_PAL0_BLUE_Pos 16 /*!< LCD CRSR_PAL0: BLUE Position */ -#define LCD_CRSR_PAL0_BLUE_Msk (0x000000ffUL << LCD_CRSR_PAL0_BLUE_Pos) /*!< LCD CRSR_PAL0: BLUE Mask */ - -// -------------------------------------- LCD_CRSR_PAL1 ----------------------------------------- -#define LCD_CRSR_PAL1_RED_Pos 0 /*!< LCD CRSR_PAL1: RED Position */ -#define LCD_CRSR_PAL1_RED_Msk (0x000000ffUL << LCD_CRSR_PAL1_RED_Pos) /*!< LCD CRSR_PAL1: RED Mask */ -#define LCD_CRSR_PAL1_GREEN_Pos 8 /*!< LCD CRSR_PAL1: GREEN Position */ -#define LCD_CRSR_PAL1_GREEN_Msk (0x000000ffUL << LCD_CRSR_PAL1_GREEN_Pos) /*!< LCD CRSR_PAL1: GREEN Mask */ -#define LCD_CRSR_PAL1_BLUE_Pos 16 /*!< LCD CRSR_PAL1: BLUE Position */ -#define LCD_CRSR_PAL1_BLUE_Msk (0x000000ffUL << LCD_CRSR_PAL1_BLUE_Pos) /*!< LCD CRSR_PAL1: BLUE Mask */ - -// --------------------------------------- LCD_CRSR_XY ------------------------------------------ -#define LCD_CRSR_XY_CRSRX_Pos 0 /*!< LCD CRSR_XY: CRSRX Position */ -#define LCD_CRSR_XY_CRSRX_Msk (0x000003ffUL << LCD_CRSR_XY_CRSRX_Pos) /*!< LCD CRSR_XY: CRSRX Mask */ -#define LCD_CRSR_XY_CRSRY_Pos 16 /*!< LCD CRSR_XY: CRSRY Position */ -#define LCD_CRSR_XY_CRSRY_Msk (0x000003ffUL << LCD_CRSR_XY_CRSRY_Pos) /*!< LCD CRSR_XY: CRSRY Mask */ - -// -------------------------------------- LCD_CRSR_CLIP ----------------------------------------- -#define LCD_CRSR_CLIP_CRSRCLIPX_Pos 0 /*!< LCD CRSR_CLIP: CRSRCLIPX Position */ -#define LCD_CRSR_CLIP_CRSRCLIPX_Msk (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPX_Pos) /*!< LCD CRSR_CLIP: CRSRCLIPX Mask */ -#define LCD_CRSR_CLIP_CRSRCLIPY_Pos 8 /*!< LCD CRSR_CLIP: CRSRCLIPY Position */ -#define LCD_CRSR_CLIP_CRSRCLIPY_Msk (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPY_Pos) /*!< LCD CRSR_CLIP: CRSRCLIPY Mask */ - -// ------------------------------------- LCD_CRSR_INTMSK ---------------------------------------- -#define LCD_CRSR_INTMSK_CRSRIM_Pos 0 /*!< LCD CRSR_INTMSK: CRSRIM Position */ -#define LCD_CRSR_INTMSK_CRSRIM_Msk (0x01UL << LCD_CRSR_INTMSK_CRSRIM_Pos) /*!< LCD CRSR_INTMSK: CRSRIM Mask */ - -// ------------------------------------- LCD_CRSR_INTCLR ---------------------------------------- -#define LCD_CRSR_INTCLR_CRSRIC_Pos 0 /*!< LCD CRSR_INTCLR: CRSRIC Position */ -#define LCD_CRSR_INTCLR_CRSRIC_Msk (0x01UL << LCD_CRSR_INTCLR_CRSRIC_Pos) /*!< LCD CRSR_INTCLR: CRSRIC Mask */ - -// ------------------------------------- LCD_CRSR_INTRAW ---------------------------------------- -#define LCD_CRSR_INTRAW_CRSRRIS_Pos 0 /*!< LCD CRSR_INTRAW: CRSRRIS Position */ -#define LCD_CRSR_INTRAW_CRSRRIS_Msk (0x01UL << LCD_CRSR_INTRAW_CRSRRIS_Pos) /*!< LCD CRSR_INTRAW: CRSRRIS Mask */ - -// ------------------------------------ LCD_CRSR_INTSTAT ---------------------------------------- -#define LCD_CRSR_INTSTAT_CRSRMIS_Pos 0 /*!< LCD CRSR_INTSTAT: CRSRMIS Position */ -#define LCD_CRSR_INTSTAT_CRSRMIS_Msk (0x01UL << LCD_CRSR_INTSTAT_CRSRMIS_Pos) /*!< LCD CRSR_INTSTAT: CRSRMIS Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- ETHERNET Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ----------------------------------- ETHERNET_MAC_CONFIG -------------------------------------- -#define ETHERNET_MAC_CONFIG_RE_Pos 2 /*!< ETHERNET MAC_CONFIG: RE Position */ -#define ETHERNET_MAC_CONFIG_RE_Msk (0x01UL << ETHERNET_MAC_CONFIG_RE_Pos) /*!< ETHERNET MAC_CONFIG: RE Mask */ -#define ETHERNET_MAC_CONFIG_TE_Pos 3 /*!< ETHERNET MAC_CONFIG: TE Position */ -#define ETHERNET_MAC_CONFIG_TE_Msk (0x01UL << ETHERNET_MAC_CONFIG_TE_Pos) /*!< ETHERNET MAC_CONFIG: TE Mask */ -#define ETHERNET_MAC_CONFIG_DF_Pos 4 /*!< ETHERNET MAC_CONFIG: DF Position */ -#define ETHERNET_MAC_CONFIG_DF_Msk (0x01UL << ETHERNET_MAC_CONFIG_DF_Pos) /*!< ETHERNET MAC_CONFIG: DF Mask */ -#define ETHERNET_MAC_CONFIG_BL_Pos 5 /*!< ETHERNET MAC_CONFIG: BL Position */ -#define ETHERNET_MAC_CONFIG_BL_Msk (0x03UL << ETHERNET_MAC_CONFIG_BL_Pos) /*!< ETHERNET MAC_CONFIG: BL Mask */ -#define ETHERNET_MAC_CONFIG_ACS_Pos 7 /*!< ETHERNET MAC_CONFIG: ACS Position */ -#define ETHERNET_MAC_CONFIG_ACS_Msk (0x01UL << ETHERNET_MAC_CONFIG_ACS_Pos) /*!< ETHERNET MAC_CONFIG: ACS Mask */ -#define ETHERNET_MAC_CONFIG_DR_Pos 9 /*!< ETHERNET MAC_CONFIG: DR Position */ -#define ETHERNET_MAC_CONFIG_DR_Msk (0x01UL << ETHERNET_MAC_CONFIG_DR_Pos) /*!< ETHERNET MAC_CONFIG: DR Mask */ -#define ETHERNET_MAC_CONFIG_IPC_Pos 10 /*!< ETHERNET MAC_CONFIG: IPC Position */ -#define ETHERNET_MAC_CONFIG_IPC_Msk (0x01UL << ETHERNET_MAC_CONFIG_IPC_Pos) /*!< ETHERNET MAC_CONFIG: IPC Mask */ -#define ETHERNET_MAC_CONFIG_DM_Pos 11 /*!< ETHERNET MAC_CONFIG: DM Position */ -#define ETHERNET_MAC_CONFIG_DM_Msk (0x01UL << ETHERNET_MAC_CONFIG_DM_Pos) /*!< ETHERNET MAC_CONFIG: DM Mask */ -#define ETHERNET_MAC_CONFIG_LM_Pos 12 /*!< ETHERNET MAC_CONFIG: LM Position */ -#define ETHERNET_MAC_CONFIG_LM_Msk (0x01UL << ETHERNET_MAC_CONFIG_LM_Pos) /*!< ETHERNET MAC_CONFIG: LM Mask */ -#define ETHERNET_MAC_CONFIG_DO_Pos 13 /*!< ETHERNET MAC_CONFIG: DO Position */ -#define ETHERNET_MAC_CONFIG_DO_Msk (0x01UL << ETHERNET_MAC_CONFIG_DO_Pos) /*!< ETHERNET MAC_CONFIG: DO Mask */ -#define ETHERNET_MAC_CONFIG_FES_Pos 14 /*!< ETHERNET MAC_CONFIG: FES Position */ -#define ETHERNET_MAC_CONFIG_FES_Msk (0x01UL << ETHERNET_MAC_CONFIG_FES_Pos) /*!< ETHERNET MAC_CONFIG: FES Mask */ -#define ETHERNET_MAC_CONFIG_PS_Pos 15 /*!< ETHERNET MAC_CONFIG: PS Position */ -#define ETHERNET_MAC_CONFIG_PS_Msk (0x01UL << ETHERNET_MAC_CONFIG_PS_Pos) /*!< ETHERNET MAC_CONFIG: PS Mask */ -#define ETHERNET_MAC_CONFIG_DCRS_Pos 16 /*!< ETHERNET MAC_CONFIG: DCRS Position */ -#define ETHERNET_MAC_CONFIG_DCRS_Msk (0x01UL << ETHERNET_MAC_CONFIG_DCRS_Pos) /*!< ETHERNET MAC_CONFIG: DCRS Mask */ -#define ETHERNET_MAC_CONFIG_IFG_Pos 17 /*!< ETHERNET MAC_CONFIG: IFG Position */ -#define ETHERNET_MAC_CONFIG_IFG_Msk (0x07UL << ETHERNET_MAC_CONFIG_IFG_Pos) /*!< ETHERNET MAC_CONFIG: IFG Mask */ -#define ETHERNET_MAC_CONFIG_JE_Pos 20 /*!< ETHERNET MAC_CONFIG: JE Position */ -#define ETHERNET_MAC_CONFIG_JE_Msk (0x01UL << ETHERNET_MAC_CONFIG_JE_Pos) /*!< ETHERNET MAC_CONFIG: JE Mask */ -#define ETHERNET_MAC_CONFIG_JD_Pos 22 /*!< ETHERNET MAC_CONFIG: JD Position */ -#define ETHERNET_MAC_CONFIG_JD_Msk (0x01UL << ETHERNET_MAC_CONFIG_JD_Pos) /*!< ETHERNET MAC_CONFIG: JD Mask */ -#define ETHERNET_MAC_CONFIG_WD_Pos 23 /*!< ETHERNET MAC_CONFIG: WD Position */ -#define ETHERNET_MAC_CONFIG_WD_Msk (0x01UL << ETHERNET_MAC_CONFIG_WD_Pos) /*!< ETHERNET MAC_CONFIG: WD Mask */ - -// -------------------------------- ETHERNET_MAC_FRAME_FILTER ----------------------------------- -#define ETHERNET_MAC_FRAME_FILTER_PR_Pos 0 /*!< ETHERNET MAC_FRAME_FILTER: PR Position */ -#define ETHERNET_MAC_FRAME_FILTER_PR_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_PR_Pos) /*!< ETHERNET MAC_FRAME_FILTER: PR Mask */ -#define ETHERNET_MAC_FRAME_FILTER_DAIF_Pos 3 /*!< ETHERNET MAC_FRAME_FILTER: DAIF Position */ -#define ETHERNET_MAC_FRAME_FILTER_DAIF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_DAIF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: DAIF Mask */ -#define ETHERNET_MAC_FRAME_FILTER_PM_Pos 4 /*!< ETHERNET MAC_FRAME_FILTER: PM Position */ -#define ETHERNET_MAC_FRAME_FILTER_PM_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_PM_Pos) /*!< ETHERNET MAC_FRAME_FILTER: PM Mask */ -#define ETHERNET_MAC_FRAME_FILTER_DBF_Pos 5 /*!< ETHERNET MAC_FRAME_FILTER: DBF Position */ -#define ETHERNET_MAC_FRAME_FILTER_DBF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_DBF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: DBF Mask */ -#define ETHERNET_MAC_FRAME_FILTER_PCF_Pos 6 /*!< ETHERNET MAC_FRAME_FILTER: PCF Position */ -#define ETHERNET_MAC_FRAME_FILTER_PCF_Msk (0x03UL << ETHERNET_MAC_FRAME_FILTER_PCF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: PCF Mask */ -#define ETHERNET_MAC_FRAME_FILTER_SAIF_Pos 8 /*!< ETHERNET MAC_FRAME_FILTER: SAIF Position */ -#define ETHERNET_MAC_FRAME_FILTER_SAIF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_SAIF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: SAIF Mask */ -#define ETHERNET_MAC_FRAME_FILTER_SAF_Pos 9 /*!< ETHERNET MAC_FRAME_FILTER: SAF Position */ -#define ETHERNET_MAC_FRAME_FILTER_SAF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_SAF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: SAF Mask */ -#define ETHERNET_MAC_FRAME_FILTER_RA_Pos 31 /*!< ETHERNET MAC_FRAME_FILTER: RA Position */ -#define ETHERNET_MAC_FRAME_FILTER_RA_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_RA_Pos) /*!< ETHERNET MAC_FRAME_FILTER: RA Mask */ - -// ------------------------------- ETHERNET_MAC_HASHTABLE_HIGH ---------------------------------- -#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos 0 /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Position */ -#define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Msk (0xffffffffUL << ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos) /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Mask */ - -// ------------------------------- ETHERNET_MAC_HASHTABLE_LOW ----------------------------------- -#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos 0 /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Position */ -#define ETHERNET_MAC_HASHTABLE_LOW_HTL_Msk (0xffffffffUL << ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos) /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Mask */ - -// ---------------------------------- ETHERNET_MAC_MII_ADDR ------------------------------------- -#define ETHERNET_MAC_MII_ADDR_GB_Pos 0 /*!< ETHERNET MAC_MII_ADDR: GB Position */ -#define ETHERNET_MAC_MII_ADDR_GB_Msk (0x01UL << ETHERNET_MAC_MII_ADDR_GB_Pos) /*!< ETHERNET MAC_MII_ADDR: GB Mask */ -#define ETHERNET_MAC_MII_ADDR_W_Pos 1 /*!< ETHERNET MAC_MII_ADDR: W Position */ -#define ETHERNET_MAC_MII_ADDR_W_Msk (0x01UL << ETHERNET_MAC_MII_ADDR_W_Pos) /*!< ETHERNET MAC_MII_ADDR: W Mask */ -#define ETHERNET_MAC_MII_ADDR_CR_Pos 2 /*!< ETHERNET MAC_MII_ADDR: CR Position */ -#define ETHERNET_MAC_MII_ADDR_CR_Msk (0x0fUL << ETHERNET_MAC_MII_ADDR_CR_Pos) /*!< ETHERNET MAC_MII_ADDR: CR Mask */ -#define ETHERNET_MAC_MII_ADDR_GR_Pos 6 /*!< ETHERNET MAC_MII_ADDR: GR Position */ -#define ETHERNET_MAC_MII_ADDR_GR_Msk (0x1fUL << ETHERNET_MAC_MII_ADDR_GR_Pos) /*!< ETHERNET MAC_MII_ADDR: GR Mask */ -#define ETHERNET_MAC_MII_ADDR_PA_Pos 11 /*!< ETHERNET MAC_MII_ADDR: PA Position */ -#define ETHERNET_MAC_MII_ADDR_PA_Msk (0x1fUL << ETHERNET_MAC_MII_ADDR_PA_Pos) /*!< ETHERNET MAC_MII_ADDR: PA Mask */ - -// ---------------------------------- ETHERNET_MAC_MII_DATA ------------------------------------- -#define ETHERNET_MAC_MII_DATA_GD_Pos 0 /*!< ETHERNET MAC_MII_DATA: GD Position */ -#define ETHERNET_MAC_MII_DATA_GD_Msk (0x0000ffffUL << ETHERNET_MAC_MII_DATA_GD_Pos) /*!< ETHERNET MAC_MII_DATA: GD Mask */ - -// --------------------------------- ETHERNET_MAC_FLOW_CTRL ------------------------------------- -#define ETHERNET_MAC_FLOW_CTRL_FCB_Pos 0 /*!< ETHERNET MAC_FLOW_CTRL: FCB Position */ -#define ETHERNET_MAC_FLOW_CTRL_FCB_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_FCB_Pos) /*!< ETHERNET MAC_FLOW_CTRL: FCB Mask */ -#define ETHERNET_MAC_FLOW_CTRL_TFE_Pos 1 /*!< ETHERNET MAC_FLOW_CTRL: TFE Position */ -#define ETHERNET_MAC_FLOW_CTRL_TFE_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_TFE_Pos) /*!< ETHERNET MAC_FLOW_CTRL: TFE Mask */ -#define ETHERNET_MAC_FLOW_CTRL_RFE_Pos 2 /*!< ETHERNET MAC_FLOW_CTRL: RFE Position */ -#define ETHERNET_MAC_FLOW_CTRL_RFE_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_RFE_Pos) /*!< ETHERNET MAC_FLOW_CTRL: RFE Mask */ -#define ETHERNET_MAC_FLOW_CTRL_UP_Pos 3 /*!< ETHERNET MAC_FLOW_CTRL: UP Position */ -#define ETHERNET_MAC_FLOW_CTRL_UP_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_UP_Pos) /*!< ETHERNET MAC_FLOW_CTRL: UP Mask */ -#define ETHERNET_MAC_FLOW_CTRL_PLT_Pos 4 /*!< ETHERNET MAC_FLOW_CTRL: PLT Position */ -#define ETHERNET_MAC_FLOW_CTRL_PLT_Msk (0x03UL << ETHERNET_MAC_FLOW_CTRL_PLT_Pos) /*!< ETHERNET MAC_FLOW_CTRL: PLT Mask */ -#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos 7 /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Position */ -#define ETHERNET_MAC_FLOW_CTRL_DZPQ_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos) /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Mask */ -#define ETHERNET_MAC_FLOW_CTRL_PT_Pos 16 /*!< ETHERNET MAC_FLOW_CTRL: PT Position */ -#define ETHERNET_MAC_FLOW_CTRL_PT_Msk (0x0000ffffUL << ETHERNET_MAC_FLOW_CTRL_PT_Pos) /*!< ETHERNET MAC_FLOW_CTRL: PT Mask */ - -// ---------------------------------- ETHERNET_MAC_VLAN_TAG ------------------------------------- -#define ETHERNET_MAC_VLAN_TAG_VL_Pos 0 /*!< ETHERNET MAC_VLAN_TAG: VL Position */ -#define ETHERNET_MAC_VLAN_TAG_VL_Msk (0x0000ffffUL << ETHERNET_MAC_VLAN_TAG_VL_Pos) /*!< ETHERNET MAC_VLAN_TAG: VL Mask */ -#define ETHERNET_MAC_VLAN_TAG_ETV_Pos 16 /*!< ETHERNET MAC_VLAN_TAG: ETV Position */ -#define ETHERNET_MAC_VLAN_TAG_ETV_Msk (0x01UL << ETHERNET_MAC_VLAN_TAG_ETV_Pos) /*!< ETHERNET MAC_VLAN_TAG: ETV Mask */ - -// ----------------------------------- ETHERNET_MAC_DEBUG --------------------------------------- -#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos 0 /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Position */ -#define ETHERNET_MAC_DEBUG_RXIDLESTAT_Msk (0x01UL << ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos) /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Mask */ -#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos 1 /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Position */ -#define ETHERNET_MAC_DEBUG_FIFOSTAT0_Msk (0x03UL << ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos) /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Mask */ -#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos 4 /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Position */ -#define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Msk (0x01UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos) /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Mask */ -#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos 5 /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Position */ -#define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Msk (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos) /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Mask */ -#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos 8 /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Position */ -#define ETHERNET_MAC_DEBUG_RXFIFOLVL_Msk (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos) /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Mask */ -#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos 16 /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Position */ -#define ETHERNET_MAC_DEBUG_TXIDLESTAT_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos) /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Mask */ -#define ETHERNET_MAC_DEBUG_TXSTAT_Pos 17 /*!< ETHERNET MAC_DEBUG: TXSTAT Position */ -#define ETHERNET_MAC_DEBUG_TXSTAT_Msk (0x03UL << ETHERNET_MAC_DEBUG_TXSTAT_Pos) /*!< ETHERNET MAC_DEBUG: TXSTAT Mask */ -#define ETHERNET_MAC_DEBUG_PAUSE_Pos 19 /*!< ETHERNET MAC_DEBUG: PAUSE Position */ -#define ETHERNET_MAC_DEBUG_PAUSE_Msk (0x01UL << ETHERNET_MAC_DEBUG_PAUSE_Pos) /*!< ETHERNET MAC_DEBUG: PAUSE Mask */ -#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos 20 /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Position */ -#define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Msk (0x03UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Mask */ -#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos 22 /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Position */ -#define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Mask */ -#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos 24 /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Position */ -#define ETHERNET_MAC_DEBUG_TXFIFOLVL_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Mask */ -#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos 25 /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Position */ -#define ETHERNET_MAC_DEBUG_TXFIFOFULL_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Mask */ - -// -------------------------------- ETHERNET_MAC_RWAKE_FRFLT ------------------------------------ -#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos 0 /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Position */ -#define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Msk (0xffffffffUL << ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos) /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Mask */ - -// ------------------------------- ETHERNET_MAC_PMT_CTRL_STAT ----------------------------------- -#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos 0 /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Position */ -#define ETHERNET_MAC_PMT_CTRL_STAT_PD_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Mask */ -#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos 1 /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Position */ -#define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Mask */ -#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos 2 /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Position */ -#define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Mask */ -#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos 5 /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Position */ -#define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Mask */ -#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos 6 /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Position */ -#define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Mask */ -#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos 9 /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Position */ -#define ETHERNET_MAC_PMT_CTRL_STAT_GU_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Mask */ -#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos 31 /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Position */ -#define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Mask */ - -// --------------------------------- ETHERNET_MAC_INTR_MASK ------------------------------------- -#define ETHERNET_MAC_INTR_MASK_PMTMSK_Pos 3 /*!< ETHERNET MAC_INTR_MASK: PMTMSK Position */ -#define ETHERNET_MAC_INTR_MASK_PMTMSK_Msk (0x01UL << ETHERNET_MAC_INTR_MASK_PMTMSK_Pos) /*!< ETHERNET MAC_INTR_MASK: PMTMSK Mask */ - -// --------------------------------- ETHERNET_MAC_ADDR0_HIGH ------------------------------------ -#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos 0 /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Position */ -#define ETHERNET_MAC_ADDR0_HIGH_A47_32_Msk (0x0000ffffUL << ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos) /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Mask */ -#define ETHERNET_MAC_ADDR0_HIGH_MO_Pos 31 /*!< ETHERNET MAC_ADDR0_HIGH: MO Position */ -#define ETHERNET_MAC_ADDR0_HIGH_MO_Msk (0x01UL << ETHERNET_MAC_ADDR0_HIGH_MO_Pos) /*!< ETHERNET MAC_ADDR0_HIGH: MO Mask */ - -// --------------------------------- ETHERNET_MAC_ADDR0_LOW ------------------------------------- -#define ETHERNET_MAC_ADDR0_LOW_A31_0_Pos 0 /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Position */ -#define ETHERNET_MAC_ADDR0_LOW_A31_0_Msk (0xffffffffUL << ETHERNET_MAC_ADDR0_LOW_A31_0_Pos) /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Mask */ - -// -------------------------------- ETHERNET_MAC_TIMESTP_CTRL ----------------------------------- -#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos 0 /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos 1 /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos 2 /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos 3 /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos 4 /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos 5 /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos 8 /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos 9 /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos 10 /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos 11 /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos 12 /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos 13 /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos 14 /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos 15 /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos 16 /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Msk (0x03UL << ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Mask */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos 18 /*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Position */ -#define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Mask */ - -// --------------------------------- ETHERNET_SUBSECOND_INCR ------------------------------------ -#define ETHERNET_SUBSECOND_INCR_SSINC_Pos 0 /*!< ETHERNET SUBSECOND_INCR: SSINC Position */ -#define ETHERNET_SUBSECOND_INCR_SSINC_Msk (0x000000ffUL << ETHERNET_SUBSECOND_INCR_SSINC_Pos) /*!< ETHERNET SUBSECOND_INCR: SSINC Mask */ - -// ------------------------------------ ETHERNET_SECONDS ---------------------------------------- -#define ETHERNET_SECONDS_TSS_Pos 0 /*!< ETHERNET SECONDS: TSS Position */ -#define ETHERNET_SECONDS_TSS_Msk (0xffffffffUL << ETHERNET_SECONDS_TSS_Pos) /*!< ETHERNET SECONDS: TSS Mask */ - -// ---------------------------------- ETHERNET_NANOSECONDS -------------------------------------- -#define ETHERNET_NANOSECONDS_TSSS_Pos 0 /*!< ETHERNET NANOSECONDS: TSSS Position */ -#define ETHERNET_NANOSECONDS_TSSS_Msk (0x7fffffffUL << ETHERNET_NANOSECONDS_TSSS_Pos) /*!< ETHERNET NANOSECONDS: TSSS Mask */ -#define ETHERNET_NANOSECONDS_PSNT_Pos 31 /*!< ETHERNET NANOSECONDS: PSNT Position */ -#define ETHERNET_NANOSECONDS_PSNT_Msk (0x01UL << ETHERNET_NANOSECONDS_PSNT_Pos) /*!< ETHERNET NANOSECONDS: PSNT Mask */ - -// --------------------------------- ETHERNET_SECONDSUPDATE ------------------------------------- -#define ETHERNET_SECONDSUPDATE_TSS_Pos 0 /*!< ETHERNET SECONDSUPDATE: TSS Position */ -#define ETHERNET_SECONDSUPDATE_TSS_Msk (0xffffffffUL << ETHERNET_SECONDSUPDATE_TSS_Pos) /*!< ETHERNET SECONDSUPDATE: TSS Mask */ - -// ------------------------------- ETHERNET_NANOSECONDSUPDATE ----------------------------------- -#define ETHERNET_NANOSECONDSUPDATE_TSSS_Pos 0 /*!< ETHERNET NANOSECONDSUPDATE: TSSS Position */ -#define ETHERNET_NANOSECONDSUPDATE_TSSS_Msk (0x7fffffffUL << ETHERNET_NANOSECONDSUPDATE_TSSS_Pos) /*!< ETHERNET NANOSECONDSUPDATE: TSSS Mask */ -#define ETHERNET_NANOSECONDSUPDATE_ADDSUB_Pos 31 /*!< ETHERNET NANOSECONDSUPDATE: ADDSUB Position */ -#define ETHERNET_NANOSECONDSUPDATE_ADDSUB_Msk (0x01UL << ETHERNET_NANOSECONDSUPDATE_ADDSUB_Pos) /*!< ETHERNET NANOSECONDSUPDATE: ADDSUB Mask */ - -// ------------------------------------- ETHERNET_ADDEND ---------------------------------------- -#define ETHERNET_ADDEND_TSAR_Pos 0 /*!< ETHERNET ADDEND: TSAR Position */ -#define ETHERNET_ADDEND_TSAR_Msk (0xffffffffUL << ETHERNET_ADDEND_TSAR_Pos) /*!< ETHERNET ADDEND: TSAR Mask */ - -// --------------------------------- ETHERNET_TARGETSECONDS ------------------------------------- -#define ETHERNET_TARGETSECONDS_TSTR_Pos 0 /*!< ETHERNET TARGETSECONDS: TSTR Position */ -#define ETHERNET_TARGETSECONDS_TSTR_Msk (0xffffffffUL << ETHERNET_TARGETSECONDS_TSTR_Pos) /*!< ETHERNET TARGETSECONDS: TSTR Mask */ - -// ------------------------------- ETHERNET_TARGETNANOSECONDS ----------------------------------- -#define ETHERNET_TARGETNANOSECONDS_TSTR_Pos 0 /*!< ETHERNET TARGETNANOSECONDS: TSTR Position */ -#define ETHERNET_TARGETNANOSECONDS_TSTR_Msk (0x7fffffffUL << ETHERNET_TARGETNANOSECONDS_TSTR_Pos) /*!< ETHERNET TARGETNANOSECONDS: TSTR Mask */ - -// ------------------------------------ ETHERNET_HIGHWORD --------------------------------------- -#define ETHERNET_HIGHWORD_TSHWR_Pos 0 /*!< ETHERNET HIGHWORD: TSHWR Position */ -#define ETHERNET_HIGHWORD_TSHWR_Msk (0x0000ffffUL << ETHERNET_HIGHWORD_TSHWR_Pos) /*!< ETHERNET HIGHWORD: TSHWR Mask */ - -// --------------------------------- ETHERNET_TIMESTAMPSTAT ------------------------------------- -#define ETHERNET_TIMESTAMPSTAT_TSSOVF_Pos 0 /*!< ETHERNET TIMESTAMPSTAT: TSSOVF Position */ -#define ETHERNET_TIMESTAMPSTAT_TSSOVF_Msk (0x01UL << ETHERNET_TIMESTAMPSTAT_TSSOVF_Pos) /*!< ETHERNET TIMESTAMPSTAT: TSSOVF Mask */ -#define ETHERNET_TIMESTAMPSTAT_TSTARGT_Pos 1 /*!< ETHERNET TIMESTAMPSTAT: TSTARGT Position */ -#define ETHERNET_TIMESTAMPSTAT_TSTARGT_Msk (0x01UL << ETHERNET_TIMESTAMPSTAT_TSTARGT_Pos) /*!< ETHERNET TIMESTAMPSTAT: TSTARGT Mask */ -#define ETHERNET_TIMESTAMPSTAT_AUXSS_Pos 2 /*!< ETHERNET TIMESTAMPSTAT: AUXSS Position */ -#define ETHERNET_TIMESTAMPSTAT_AUXSS_Msk (0x01UL << ETHERNET_TIMESTAMPSTAT_AUXSS_Pos) /*!< ETHERNET TIMESTAMPSTAT: AUXSS Mask */ -#define ETHERNET_TIMESTAMPSTAT_ATSSTM_Pos 24 /*!< ETHERNET TIMESTAMPSTAT: ATSSTM Position */ -#define ETHERNET_TIMESTAMPSTAT_ATSSTM_Msk (0x01UL << ETHERNET_TIMESTAMPSTAT_ATSSTM_Pos) /*!< ETHERNET TIMESTAMPSTAT: ATSSTM Mask */ -#define ETHERNET_TIMESTAMPSTAT_ATSNS_Pos 25 /*!< ETHERNET TIMESTAMPSTAT: ATSNS Position */ -#define ETHERNET_TIMESTAMPSTAT_ATSNS_Msk (0x07UL << ETHERNET_TIMESTAMPSTAT_ATSNS_Pos) /*!< ETHERNET TIMESTAMPSTAT: ATSNS Mask */ - -// ------------------------------------ ETHERNET_PPSCTRL ---------------------------------------- -#define ETHERNET_PPSCTRL_PPSCTRL_Pos 0 /*!< ETHERNET PPSCTRL: PPSCTRL Position */ -#define ETHERNET_PPSCTRL_PPSCTRL_Msk (0x0fUL << ETHERNET_PPSCTRL_PPSCTRL_Pos) /*!< ETHERNET PPSCTRL: PPSCTRL Mask */ - -// --------------------------------- ETHERNET_AUXNANOSECONDS ------------------------------------ -#define ETHERNET_AUXNANOSECONDS_AUXNS_Pos 0 /*!< ETHERNET AUXNANOSECONDS: AUXNS Position */ -#define ETHERNET_AUXNANOSECONDS_AUXNS_Msk (0xffffffffUL << ETHERNET_AUXNANOSECONDS_AUXNS_Pos) /*!< ETHERNET AUXNANOSECONDS: AUXNS Mask */ - -// ----------------------------------- ETHERNET_AUXSECONDS -------------------------------------- -#define ETHERNET_AUXSECONDS_AUXS_Pos 0 /*!< ETHERNET AUXSECONDS: AUXS Position */ -#define ETHERNET_AUXSECONDS_AUXS_Msk (0xffffffffUL << ETHERNET_AUXSECONDS_AUXS_Pos) /*!< ETHERNET AUXSECONDS: AUXS Mask */ - -// ---------------------------------- ETHERNET_DMA_BUS_MODE ------------------------------------- -#define ETHERNET_DMA_BUS_MODE_SWR_Pos 0 /*!< ETHERNET DMA_BUS_MODE: SWR Position */ -#define ETHERNET_DMA_BUS_MODE_SWR_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_SWR_Pos) /*!< ETHERNET DMA_BUS_MODE: SWR Mask */ -#define ETHERNET_DMA_BUS_MODE_DA_Pos 1 /*!< ETHERNET DMA_BUS_MODE: DA Position */ -#define ETHERNET_DMA_BUS_MODE_DA_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_DA_Pos) /*!< ETHERNET DMA_BUS_MODE: DA Mask */ -#define ETHERNET_DMA_BUS_MODE_DSL_Pos 2 /*!< ETHERNET DMA_BUS_MODE: DSL Position */ -#define ETHERNET_DMA_BUS_MODE_DSL_Msk (0x1fUL << ETHERNET_DMA_BUS_MODE_DSL_Pos) /*!< ETHERNET DMA_BUS_MODE: DSL Mask */ -#define ETHERNET_DMA_BUS_MODE_ATDS_Pos 7 /*!< ETHERNET DMA_BUS_MODE: ATDS Position */ -#define ETHERNET_DMA_BUS_MODE_ATDS_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_ATDS_Pos) /*!< ETHERNET DMA_BUS_MODE: ATDS Mask */ -#define ETHERNET_DMA_BUS_MODE_PBL_Pos 8 /*!< ETHERNET DMA_BUS_MODE: PBL Position */ -#define ETHERNET_DMA_BUS_MODE_PBL_Msk (0x3fUL << ETHERNET_DMA_BUS_MODE_PBL_Pos) /*!< ETHERNET DMA_BUS_MODE: PBL Mask */ -#define ETHERNET_DMA_BUS_MODE_PR_Pos 14 /*!< ETHERNET DMA_BUS_MODE: PR Position */ -#define ETHERNET_DMA_BUS_MODE_PR_Msk (0x03UL << ETHERNET_DMA_BUS_MODE_PR_Pos) /*!< ETHERNET DMA_BUS_MODE: PR Mask */ -#define ETHERNET_DMA_BUS_MODE_FB_Pos 16 /*!< ETHERNET DMA_BUS_MODE: FB Position */ -#define ETHERNET_DMA_BUS_MODE_FB_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_FB_Pos) /*!< ETHERNET DMA_BUS_MODE: FB Mask */ -#define ETHERNET_DMA_BUS_MODE_RPBL_Pos 17 /*!< ETHERNET DMA_BUS_MODE: RPBL Position */ -#define ETHERNET_DMA_BUS_MODE_RPBL_Msk (0x3fUL << ETHERNET_DMA_BUS_MODE_RPBL_Pos) /*!< ETHERNET DMA_BUS_MODE: RPBL Mask */ -#define ETHERNET_DMA_BUS_MODE_USP_Pos 23 /*!< ETHERNET DMA_BUS_MODE: USP Position */ -#define ETHERNET_DMA_BUS_MODE_USP_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_USP_Pos) /*!< ETHERNET DMA_BUS_MODE: USP Mask */ -#define ETHERNET_DMA_BUS_MODE_PBL8X_Pos 24 /*!< ETHERNET DMA_BUS_MODE: PBL8X Position */ -#define ETHERNET_DMA_BUS_MODE_PBL8X_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_PBL8X_Pos) /*!< ETHERNET DMA_BUS_MODE: PBL8X Mask */ -#define ETHERNET_DMA_BUS_MODE_AAL_Pos 25 /*!< ETHERNET DMA_BUS_MODE: AAL Position */ -#define ETHERNET_DMA_BUS_MODE_AAL_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_AAL_Pos) /*!< ETHERNET DMA_BUS_MODE: AAL Mask */ -#define ETHERNET_DMA_BUS_MODE_MB_Pos 26 /*!< ETHERNET DMA_BUS_MODE: MB Position */ -#define ETHERNET_DMA_BUS_MODE_MB_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_MB_Pos) /*!< ETHERNET DMA_BUS_MODE: MB Mask */ -#define ETHERNET_DMA_BUS_MODE_TXPR_Pos 27 /*!< ETHERNET DMA_BUS_MODE: TXPR Position */ -#define ETHERNET_DMA_BUS_MODE_TXPR_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_TXPR_Pos) /*!< ETHERNET DMA_BUS_MODE: TXPR Mask */ - -// ----------------------------- ETHERNET_DMA_TRANS_POLL_DEMAND --------------------------------- -#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos 0 /*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Position */ -#define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Msk (0xffffffffUL << ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos) /*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Mask */ - -// ------------------------------ ETHERNET_DMA_REC_POLL_DEMAND ---------------------------------- -#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos 0 /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Position */ -#define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Msk (0xffffffffUL << ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos) /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Mask */ - -// -------------------------------- ETHERNET_DMA_REC_DES_ADDR ----------------------------------- -#define ETHERNET_DMA_REC_DES_ADDR_SRL_Pos 0 /*!< ETHERNET DMA_REC_DES_ADDR: SRL Position */ -#define ETHERNET_DMA_REC_DES_ADDR_SRL_Msk (0xffffffffUL << ETHERNET_DMA_REC_DES_ADDR_SRL_Pos) /*!< ETHERNET DMA_REC_DES_ADDR: SRL Mask */ - -// ------------------------------- ETHERNET_DMA_TRANS_DES_ADDR ---------------------------------- -#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos 0 /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Position */ -#define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Msk (0xffffffffUL << ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos) /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Mask */ - -// ------------------------------------ ETHERNET_DMA_STAT --------------------------------------- -#define ETHERNET_DMA_STAT_TI_Pos 0 /*!< ETHERNET DMA_STAT: TI Position */ -#define ETHERNET_DMA_STAT_TI_Msk (0x01UL << ETHERNET_DMA_STAT_TI_Pos) /*!< ETHERNET DMA_STAT: TI Mask */ -#define ETHERNET_DMA_STAT_TPS_Pos 1 /*!< ETHERNET DMA_STAT: TPS Position */ -#define ETHERNET_DMA_STAT_TPS_Msk (0x01UL << ETHERNET_DMA_STAT_TPS_Pos) /*!< ETHERNET DMA_STAT: TPS Mask */ -#define ETHERNET_DMA_STAT_TU_Pos 2 /*!< ETHERNET DMA_STAT: TU Position */ -#define ETHERNET_DMA_STAT_TU_Msk (0x01UL << ETHERNET_DMA_STAT_TU_Pos) /*!< ETHERNET DMA_STAT: TU Mask */ -#define ETHERNET_DMA_STAT_TJT_Pos 3 /*!< ETHERNET DMA_STAT: TJT Position */ -#define ETHERNET_DMA_STAT_TJT_Msk (0x01UL << ETHERNET_DMA_STAT_TJT_Pos) /*!< ETHERNET DMA_STAT: TJT Mask */ -#define ETHERNET_DMA_STAT_OVF_Pos 4 /*!< ETHERNET DMA_STAT: OVF Position */ -#define ETHERNET_DMA_STAT_OVF_Msk (0x01UL << ETHERNET_DMA_STAT_OVF_Pos) /*!< ETHERNET DMA_STAT: OVF Mask */ -#define ETHERNET_DMA_STAT_UNF_Pos 5 /*!< ETHERNET DMA_STAT: UNF Position */ -#define ETHERNET_DMA_STAT_UNF_Msk (0x01UL << ETHERNET_DMA_STAT_UNF_Pos) /*!< ETHERNET DMA_STAT: UNF Mask */ -#define ETHERNET_DMA_STAT_RI_Pos 6 /*!< ETHERNET DMA_STAT: RI Position */ -#define ETHERNET_DMA_STAT_RI_Msk (0x01UL << ETHERNET_DMA_STAT_RI_Pos) /*!< ETHERNET DMA_STAT: RI Mask */ -#define ETHERNET_DMA_STAT_RU_Pos 7 /*!< ETHERNET DMA_STAT: RU Position */ -#define ETHERNET_DMA_STAT_RU_Msk (0x01UL << ETHERNET_DMA_STAT_RU_Pos) /*!< ETHERNET DMA_STAT: RU Mask */ -#define ETHERNET_DMA_STAT_RPS_Pos 8 /*!< ETHERNET DMA_STAT: RPS Position */ -#define ETHERNET_DMA_STAT_RPS_Msk (0x01UL << ETHERNET_DMA_STAT_RPS_Pos) /*!< ETHERNET DMA_STAT: RPS Mask */ -#define ETHERNET_DMA_STAT_RWT_Pos 9 /*!< ETHERNET DMA_STAT: RWT Position */ -#define ETHERNET_DMA_STAT_RWT_Msk (0x01UL << ETHERNET_DMA_STAT_RWT_Pos) /*!< ETHERNET DMA_STAT: RWT Mask */ -#define ETHERNET_DMA_STAT_ETI_Pos 10 /*!< ETHERNET DMA_STAT: ETI Position */ -#define ETHERNET_DMA_STAT_ETI_Msk (0x01UL << ETHERNET_DMA_STAT_ETI_Pos) /*!< ETHERNET DMA_STAT: ETI Mask */ -#define ETHERNET_DMA_STAT_FBI_Pos 13 /*!< ETHERNET DMA_STAT: FBI Position */ -#define ETHERNET_DMA_STAT_FBI_Msk (0x01UL << ETHERNET_DMA_STAT_FBI_Pos) /*!< ETHERNET DMA_STAT: FBI Mask */ -#define ETHERNET_DMA_STAT_ERI_Pos 14 /*!< ETHERNET DMA_STAT: ERI Position */ -#define ETHERNET_DMA_STAT_ERI_Msk (0x01UL << ETHERNET_DMA_STAT_ERI_Pos) /*!< ETHERNET DMA_STAT: ERI Mask */ -#define ETHERNET_DMA_STAT_AIE_Pos 15 /*!< ETHERNET DMA_STAT: AIE Position */ -#define ETHERNET_DMA_STAT_AIE_Msk (0x01UL << ETHERNET_DMA_STAT_AIE_Pos) /*!< ETHERNET DMA_STAT: AIE Mask */ -#define ETHERNET_DMA_STAT_NIS_Pos 16 /*!< ETHERNET DMA_STAT: NIS Position */ -#define ETHERNET_DMA_STAT_NIS_Msk (0x01UL << ETHERNET_DMA_STAT_NIS_Pos) /*!< ETHERNET DMA_STAT: NIS Mask */ - -// ---------------------------------- ETHERNET_DMA_OP_MODE -------------------------------------- -#define ETHERNET_DMA_OP_MODE_SR_Pos 1 /*!< ETHERNET DMA_OP_MODE: SR Position */ -#define ETHERNET_DMA_OP_MODE_SR_Msk (0x01UL << ETHERNET_DMA_OP_MODE_SR_Pos) /*!< ETHERNET DMA_OP_MODE: SR Mask */ -#define ETHERNET_DMA_OP_MODE_OSF_Pos 2 /*!< ETHERNET DMA_OP_MODE: OSF Position */ -#define ETHERNET_DMA_OP_MODE_OSF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_OSF_Pos) /*!< ETHERNET DMA_OP_MODE: OSF Mask */ -#define ETHERNET_DMA_OP_MODE_RTC_Pos 3 /*!< ETHERNET DMA_OP_MODE: RTC Position */ -#define ETHERNET_DMA_OP_MODE_RTC_Msk (0x03UL << ETHERNET_DMA_OP_MODE_RTC_Pos) /*!< ETHERNET DMA_OP_MODE: RTC Mask */ -#define ETHERNET_DMA_OP_MODE_FUF_Pos 6 /*!< ETHERNET DMA_OP_MODE: FUF Position */ -#define ETHERNET_DMA_OP_MODE_FUF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_FUF_Pos) /*!< ETHERNET DMA_OP_MODE: FUF Mask */ -#define ETHERNET_DMA_OP_MODE_FEF_Pos 7 /*!< ETHERNET DMA_OP_MODE: FEF Position */ -#define ETHERNET_DMA_OP_MODE_FEF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_FEF_Pos) /*!< ETHERNET DMA_OP_MODE: FEF Mask */ -#define ETHERNET_DMA_OP_MODE_ST_Pos 13 /*!< ETHERNET DMA_OP_MODE: ST Position */ -#define ETHERNET_DMA_OP_MODE_ST_Msk (0x01UL << ETHERNET_DMA_OP_MODE_ST_Pos) /*!< ETHERNET DMA_OP_MODE: ST Mask */ -#define ETHERNET_DMA_OP_MODE_TTC_Pos 14 /*!< ETHERNET DMA_OP_MODE: TTC Position */ -#define ETHERNET_DMA_OP_MODE_TTC_Msk (0x07UL << ETHERNET_DMA_OP_MODE_TTC_Pos) /*!< ETHERNET DMA_OP_MODE: TTC Mask */ -#define ETHERNET_DMA_OP_MODE_FTF_Pos 20 /*!< ETHERNET DMA_OP_MODE: FTF Position */ -#define ETHERNET_DMA_OP_MODE_FTF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_FTF_Pos) /*!< ETHERNET DMA_OP_MODE: FTF Mask */ -#define ETHERNET_DMA_OP_MODE_TSF_Pos 21 /*!< ETHERNET DMA_OP_MODE: TSF Position */ -#define ETHERNET_DMA_OP_MODE_TSF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_TSF_Pos) /*!< ETHERNET DMA_OP_MODE: TSF Mask */ -#define ETHERNET_DMA_OP_MODE_DFF_Pos 24 /*!< ETHERNET DMA_OP_MODE: DFF Position */ -#define ETHERNET_DMA_OP_MODE_DFF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_DFF_Pos) /*!< ETHERNET DMA_OP_MODE: DFF Mask */ -#define ETHERNET_DMA_OP_MODE_RSF_Pos 25 /*!< ETHERNET DMA_OP_MODE: RSF Position */ -#define ETHERNET_DMA_OP_MODE_RSF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_RSF_Pos) /*!< ETHERNET DMA_OP_MODE: RSF Mask */ -#define ETHERNET_DMA_OP_MODE_DT_Pos 26 /*!< ETHERNET DMA_OP_MODE: DT Position */ -#define ETHERNET_DMA_OP_MODE_DT_Msk (0x01UL << ETHERNET_DMA_OP_MODE_DT_Pos) /*!< ETHERNET DMA_OP_MODE: DT Mask */ - -// ----------------------------------- ETHERNET_DMA_INT_EN -------------------------------------- -#define ETHERNET_DMA_INT_EN_TIE_Pos 0 /*!< ETHERNET DMA_INT_EN: TIE Position */ -#define ETHERNET_DMA_INT_EN_TIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TIE_Pos) /*!< ETHERNET DMA_INT_EN: TIE Mask */ -#define ETHERNET_DMA_INT_EN_TSE_Pos 1 /*!< ETHERNET DMA_INT_EN: TSE Position */ -#define ETHERNET_DMA_INT_EN_TSE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TSE_Pos) /*!< ETHERNET DMA_INT_EN: TSE Mask */ -#define ETHERNET_DMA_INT_EN_TUE_Pos 2 /*!< ETHERNET DMA_INT_EN: TUE Position */ -#define ETHERNET_DMA_INT_EN_TUE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TUE_Pos) /*!< ETHERNET DMA_INT_EN: TUE Mask */ -#define ETHERNET_DMA_INT_EN_TJE_Pos 3 /*!< ETHERNET DMA_INT_EN: TJE Position */ -#define ETHERNET_DMA_INT_EN_TJE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TJE_Pos) /*!< ETHERNET DMA_INT_EN: TJE Mask */ -#define ETHERNET_DMA_INT_EN_OVE_Pos 4 /*!< ETHERNET DMA_INT_EN: OVE Position */ -#define ETHERNET_DMA_INT_EN_OVE_Msk (0x01UL << ETHERNET_DMA_INT_EN_OVE_Pos) /*!< ETHERNET DMA_INT_EN: OVE Mask */ -#define ETHERNET_DMA_INT_EN_UNE_Pos 5 /*!< ETHERNET DMA_INT_EN: UNE Position */ -#define ETHERNET_DMA_INT_EN_UNE_Msk (0x01UL << ETHERNET_DMA_INT_EN_UNE_Pos) /*!< ETHERNET DMA_INT_EN: UNE Mask */ -#define ETHERNET_DMA_INT_EN_RIE_Pos 6 /*!< ETHERNET DMA_INT_EN: RIE Position */ -#define ETHERNET_DMA_INT_EN_RIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RIE_Pos) /*!< ETHERNET DMA_INT_EN: RIE Mask */ -#define ETHERNET_DMA_INT_EN_RUE_Pos 7 /*!< ETHERNET DMA_INT_EN: RUE Position */ -#define ETHERNET_DMA_INT_EN_RUE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RUE_Pos) /*!< ETHERNET DMA_INT_EN: RUE Mask */ -#define ETHERNET_DMA_INT_EN_RSE_Pos 8 /*!< ETHERNET DMA_INT_EN: RSE Position */ -#define ETHERNET_DMA_INT_EN_RSE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RSE_Pos) /*!< ETHERNET DMA_INT_EN: RSE Mask */ -#define ETHERNET_DMA_INT_EN_RWE_Pos 9 /*!< ETHERNET DMA_INT_EN: RWE Position */ -#define ETHERNET_DMA_INT_EN_RWE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RWE_Pos) /*!< ETHERNET DMA_INT_EN: RWE Mask */ -#define ETHERNET_DMA_INT_EN_ETE_Pos 10 /*!< ETHERNET DMA_INT_EN: ETE Position */ -#define ETHERNET_DMA_INT_EN_ETE_Msk (0x01UL << ETHERNET_DMA_INT_EN_ETE_Pos) /*!< ETHERNET DMA_INT_EN: ETE Mask */ -#define ETHERNET_DMA_INT_EN_FBE_Pos 13 /*!< ETHERNET DMA_INT_EN: FBE Position */ -#define ETHERNET_DMA_INT_EN_FBE_Msk (0x01UL << ETHERNET_DMA_INT_EN_FBE_Pos) /*!< ETHERNET DMA_INT_EN: FBE Mask */ -#define ETHERNET_DMA_INT_EN_ERE_Pos 14 /*!< ETHERNET DMA_INT_EN: ERE Position */ -#define ETHERNET_DMA_INT_EN_ERE_Msk (0x01UL << ETHERNET_DMA_INT_EN_ERE_Pos) /*!< ETHERNET DMA_INT_EN: ERE Mask */ -#define ETHERNET_DMA_INT_EN_AIE_Pos 15 /*!< ETHERNET DMA_INT_EN: AIE Position */ -#define ETHERNET_DMA_INT_EN_AIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_AIE_Pos) /*!< ETHERNET DMA_INT_EN: AIE Mask */ -#define ETHERNET_DMA_INT_EN_NIE_Pos 16 /*!< ETHERNET DMA_INT_EN: NIE Position */ -#define ETHERNET_DMA_INT_EN_NIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_NIE_Pos) /*!< ETHERNET DMA_INT_EN: NIE Mask */ - -// --------------------------------- ETHERNET_DMA_MFRM_BUFOF ------------------------------------ -#define ETHERNET_DMA_MFRM_BUFOF_FMC_Pos 0 /*!< ETHERNET DMA_MFRM_BUFOF: FMC Position */ -#define ETHERNET_DMA_MFRM_BUFOF_FMC_Msk (0x0000ffffUL << ETHERNET_DMA_MFRM_BUFOF_FMC_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: FMC Mask */ -#define ETHERNET_DMA_MFRM_BUFOF_OC_Pos 16 /*!< ETHERNET DMA_MFRM_BUFOF: OC Position */ -#define ETHERNET_DMA_MFRM_BUFOF_OC_Msk (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OC_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: OC Mask */ -#define ETHERNET_DMA_MFRM_BUFOF_FMA_Pos 17 /*!< ETHERNET DMA_MFRM_BUFOF: FMA Position */ -#define ETHERNET_DMA_MFRM_BUFOF_FMA_Msk (0x000007ffUL << ETHERNET_DMA_MFRM_BUFOF_FMA_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: FMA Mask */ -#define ETHERNET_DMA_MFRM_BUFOF_OF_Pos 28 /*!< ETHERNET DMA_MFRM_BUFOF: OF Position */ -#define ETHERNET_DMA_MFRM_BUFOF_OF_Msk (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OF_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: OF Mask */ - -// -------------------------------- ETHERNET_DMA_REC_INT_WDT ------------------------------------ -#define ETHERNET_DMA_REC_INT_WDT_RIWT_Pos 0 /*!< ETHERNET DMA_REC_INT_WDT: RIWT Position */ -#define ETHERNET_DMA_REC_INT_WDT_RIWT_Msk (0x000000ffUL << ETHERNET_DMA_REC_INT_WDT_RIWT_Pos) /*!< ETHERNET DMA_REC_INT_WDT: RIWT Mask */ - -// ----------------------------- ETHERNET_DMA_CURHOST_TRANS_DES --------------------------------- -#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos 0 /*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Position */ -#define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos) /*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Mask */ - -// ------------------------------ ETHERNET_DMA_CURHOST_REC_DES ---------------------------------- -#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos 0 /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Position */ -#define ETHERNET_DMA_CURHOST_REC_DES_HRD_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos) /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Mask */ - -// ----------------------------- ETHERNET_DMA_CURHOST_TRANS_BUF --------------------------------- -#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos 0 /*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Position */ -#define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos) /*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Mask */ - -// ------------------------------ ETHERNET_DMA_CURHOST_REC_BUF ---------------------------------- -#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos 0 /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Position */ -#define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos) /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- ATIMER Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ----------------------------------- ATIMER_DOWNCOUNTER --------------------------------------- -#define ATIMER_DOWNCOUNTER_CVAL_Pos 0 /*!< ATIMER DOWNCOUNTER: CVAL Position */ -#define ATIMER_DOWNCOUNTER_CVAL_Msk (0x0000ffffUL << ATIMER_DOWNCOUNTER_CVAL_Pos) /*!< ATIMER DOWNCOUNTER: CVAL Mask */ - -// -------------------------------------- ATIMER_PRESET ----------------------------------------- -#define ATIMER_PRESET_PRESETVAL_Pos 0 /*!< ATIMER PRESET: PRESETVAL Position */ -#define ATIMER_PRESET_PRESETVAL_Msk (0x0000ffffUL << ATIMER_PRESET_PRESETVAL_Pos) /*!< ATIMER PRESET: PRESETVAL Mask */ - -// -------------------------------------- ATIMER_CLR_EN ----------------------------------------- -#define ATIMER_CLR_EN_CLR_EN_Pos 0 /*!< ATIMER CLR_EN: CLR_EN Position */ -#define ATIMER_CLR_EN_CLR_EN_Msk (0x01UL << ATIMER_CLR_EN_CLR_EN_Pos) /*!< ATIMER CLR_EN: CLR_EN Mask */ - -// -------------------------------------- ATIMER_SET_EN ----------------------------------------- -#define ATIMER_SET_EN_SET_EN_Pos 0 /*!< ATIMER SET_EN: SET_EN Position */ -#define ATIMER_SET_EN_SET_EN_Msk (0x01UL << ATIMER_SET_EN_SET_EN_Pos) /*!< ATIMER SET_EN: SET_EN Mask */ - -// -------------------------------------- ATIMER_STATUS ----------------------------------------- -#define ATIMER_STATUS_STAT_Pos 0 /*!< ATIMER STATUS: STAT Position */ -#define ATIMER_STATUS_STAT_Msk (0x01UL << ATIMER_STATUS_STAT_Pos) /*!< ATIMER STATUS: STAT Mask */ - -// -------------------------------------- ATIMER_ENABLE ----------------------------------------- -#define ATIMER_ENABLE_EN_Pos 0 /*!< ATIMER ENABLE: EN Position */ -#define ATIMER_ENABLE_EN_Msk (0x01UL << ATIMER_ENABLE_EN_Pos) /*!< ATIMER ENABLE: EN Mask */ - -// ------------------------------------- ATIMER_CLR_STAT ---------------------------------------- -#define ATIMER_CLR_STAT_CSTAT_Pos 0 /*!< ATIMER CLR_STAT: CSTAT Position */ -#define ATIMER_CLR_STAT_CSTAT_Msk (0x01UL << ATIMER_CLR_STAT_CSTAT_Pos) /*!< ATIMER CLR_STAT: CSTAT Mask */ - -// ------------------------------------- ATIMER_SET_STAT ---------------------------------------- -#define ATIMER_SET_STAT_SSTAT_Pos 0 /*!< ATIMER SET_STAT: SSTAT Position */ -#define ATIMER_SET_STAT_SSTAT_Msk (0x01UL << ATIMER_SET_STAT_SSTAT_Pos) /*!< ATIMER SET_STAT: SSTAT Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- REGFILE Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ------------------------------------ REGFILE_REGFILE0 ---------------------------------------- -#define REGFILE_REGFILE0_REGVAL_Pos 0 /*!< REGFILE REGFILE0: REGVAL Position */ -#define REGFILE_REGFILE0_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE0_REGVAL_Pos) /*!< REGFILE REGFILE0: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE1 ---------------------------------------- -#define REGFILE_REGFILE1_REGVAL_Pos 0 /*!< REGFILE REGFILE1: REGVAL Position */ -#define REGFILE_REGFILE1_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE1_REGVAL_Pos) /*!< REGFILE REGFILE1: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE2 ---------------------------------------- -#define REGFILE_REGFILE2_REGVAL_Pos 0 /*!< REGFILE REGFILE2: REGVAL Position */ -#define REGFILE_REGFILE2_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE2_REGVAL_Pos) /*!< REGFILE REGFILE2: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE3 ---------------------------------------- -#define REGFILE_REGFILE3_REGVAL_Pos 0 /*!< REGFILE REGFILE3: REGVAL Position */ -#define REGFILE_REGFILE3_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE3_REGVAL_Pos) /*!< REGFILE REGFILE3: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE4 ---------------------------------------- -#define REGFILE_REGFILE4_REGVAL_Pos 0 /*!< REGFILE REGFILE4: REGVAL Position */ -#define REGFILE_REGFILE4_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE4_REGVAL_Pos) /*!< REGFILE REGFILE4: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE5 ---------------------------------------- -#define REGFILE_REGFILE5_REGVAL_Pos 0 /*!< REGFILE REGFILE5: REGVAL Position */ -#define REGFILE_REGFILE5_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE5_REGVAL_Pos) /*!< REGFILE REGFILE5: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE6 ---------------------------------------- -#define REGFILE_REGFILE6_REGVAL_Pos 0 /*!< REGFILE REGFILE6: REGVAL Position */ -#define REGFILE_REGFILE6_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE6_REGVAL_Pos) /*!< REGFILE REGFILE6: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE7 ---------------------------------------- -#define REGFILE_REGFILE7_REGVAL_Pos 0 /*!< REGFILE REGFILE7: REGVAL Position */ -#define REGFILE_REGFILE7_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE7_REGVAL_Pos) /*!< REGFILE REGFILE7: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE8 ---------------------------------------- -#define REGFILE_REGFILE8_REGVAL_Pos 0 /*!< REGFILE REGFILE8: REGVAL Position */ -#define REGFILE_REGFILE8_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE8_REGVAL_Pos) /*!< REGFILE REGFILE8: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE9 ---------------------------------------- -#define REGFILE_REGFILE9_REGVAL_Pos 0 /*!< REGFILE REGFILE9: REGVAL Position */ -#define REGFILE_REGFILE9_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE9_REGVAL_Pos) /*!< REGFILE REGFILE9: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE10 --------------------------------------- -#define REGFILE_REGFILE10_REGVAL_Pos 0 /*!< REGFILE REGFILE10: REGVAL Position */ -#define REGFILE_REGFILE10_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE10_REGVAL_Pos) /*!< REGFILE REGFILE10: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE11 --------------------------------------- -#define REGFILE_REGFILE11_REGVAL_Pos 0 /*!< REGFILE REGFILE11: REGVAL Position */ -#define REGFILE_REGFILE11_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE11_REGVAL_Pos) /*!< REGFILE REGFILE11: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE12 --------------------------------------- -#define REGFILE_REGFILE12_REGVAL_Pos 0 /*!< REGFILE REGFILE12: REGVAL Position */ -#define REGFILE_REGFILE12_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE12_REGVAL_Pos) /*!< REGFILE REGFILE12: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE13 --------------------------------------- -#define REGFILE_REGFILE13_REGVAL_Pos 0 /*!< REGFILE REGFILE13: REGVAL Position */ -#define REGFILE_REGFILE13_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE13_REGVAL_Pos) /*!< REGFILE REGFILE13: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE14 --------------------------------------- -#define REGFILE_REGFILE14_REGVAL_Pos 0 /*!< REGFILE REGFILE14: REGVAL Position */ -#define REGFILE_REGFILE14_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE14_REGVAL_Pos) /*!< REGFILE REGFILE14: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE15 --------------------------------------- -#define REGFILE_REGFILE15_REGVAL_Pos 0 /*!< REGFILE REGFILE15: REGVAL Position */ -#define REGFILE_REGFILE15_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE15_REGVAL_Pos) /*!< REGFILE REGFILE15: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE16 --------------------------------------- -#define REGFILE_REGFILE16_REGVAL_Pos 0 /*!< REGFILE REGFILE16: REGVAL Position */ -#define REGFILE_REGFILE16_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE16_REGVAL_Pos) /*!< REGFILE REGFILE16: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE17 --------------------------------------- -#define REGFILE_REGFILE17_REGVAL_Pos 0 /*!< REGFILE REGFILE17: REGVAL Position */ -#define REGFILE_REGFILE17_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE17_REGVAL_Pos) /*!< REGFILE REGFILE17: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE18 --------------------------------------- -#define REGFILE_REGFILE18_REGVAL_Pos 0 /*!< REGFILE REGFILE18: REGVAL Position */ -#define REGFILE_REGFILE18_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE18_REGVAL_Pos) /*!< REGFILE REGFILE18: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE19 --------------------------------------- -#define REGFILE_REGFILE19_REGVAL_Pos 0 /*!< REGFILE REGFILE19: REGVAL Position */ -#define REGFILE_REGFILE19_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE19_REGVAL_Pos) /*!< REGFILE REGFILE19: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE20 --------------------------------------- -#define REGFILE_REGFILE20_REGVAL_Pos 0 /*!< REGFILE REGFILE20: REGVAL Position */ -#define REGFILE_REGFILE20_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE20_REGVAL_Pos) /*!< REGFILE REGFILE20: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE21 --------------------------------------- -#define REGFILE_REGFILE21_REGVAL_Pos 0 /*!< REGFILE REGFILE21: REGVAL Position */ -#define REGFILE_REGFILE21_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE21_REGVAL_Pos) /*!< REGFILE REGFILE21: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE22 --------------------------------------- -#define REGFILE_REGFILE22_REGVAL_Pos 0 /*!< REGFILE REGFILE22: REGVAL Position */ -#define REGFILE_REGFILE22_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE22_REGVAL_Pos) /*!< REGFILE REGFILE22: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE23 --------------------------------------- -#define REGFILE_REGFILE23_REGVAL_Pos 0 /*!< REGFILE REGFILE23: REGVAL Position */ -#define REGFILE_REGFILE23_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE23_REGVAL_Pos) /*!< REGFILE REGFILE23: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE24 --------------------------------------- -#define REGFILE_REGFILE24_REGVAL_Pos 0 /*!< REGFILE REGFILE24: REGVAL Position */ -#define REGFILE_REGFILE24_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE24_REGVAL_Pos) /*!< REGFILE REGFILE24: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE25 --------------------------------------- -#define REGFILE_REGFILE25_REGVAL_Pos 0 /*!< REGFILE REGFILE25: REGVAL Position */ -#define REGFILE_REGFILE25_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE25_REGVAL_Pos) /*!< REGFILE REGFILE25: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE26 --------------------------------------- -#define REGFILE_REGFILE26_REGVAL_Pos 0 /*!< REGFILE REGFILE26: REGVAL Position */ -#define REGFILE_REGFILE26_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE26_REGVAL_Pos) /*!< REGFILE REGFILE26: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE27 --------------------------------------- -#define REGFILE_REGFILE27_REGVAL_Pos 0 /*!< REGFILE REGFILE27: REGVAL Position */ -#define REGFILE_REGFILE27_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE27_REGVAL_Pos) /*!< REGFILE REGFILE27: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE28 --------------------------------------- -#define REGFILE_REGFILE28_REGVAL_Pos 0 /*!< REGFILE REGFILE28: REGVAL Position */ -#define REGFILE_REGFILE28_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE28_REGVAL_Pos) /*!< REGFILE REGFILE28: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE29 --------------------------------------- -#define REGFILE_REGFILE29_REGVAL_Pos 0 /*!< REGFILE REGFILE29: REGVAL Position */ -#define REGFILE_REGFILE29_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE29_REGVAL_Pos) /*!< REGFILE REGFILE29: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE30 --------------------------------------- -#define REGFILE_REGFILE30_REGVAL_Pos 0 /*!< REGFILE REGFILE30: REGVAL Position */ -#define REGFILE_REGFILE30_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE30_REGVAL_Pos) /*!< REGFILE REGFILE30: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE31 --------------------------------------- -#define REGFILE_REGFILE31_REGVAL_Pos 0 /*!< REGFILE REGFILE31: REGVAL Position */ -#define REGFILE_REGFILE31_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE31_REGVAL_Pos) /*!< REGFILE REGFILE31: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE32 --------------------------------------- -#define REGFILE_REGFILE32_REGVAL_Pos 0 /*!< REGFILE REGFILE32: REGVAL Position */ -#define REGFILE_REGFILE32_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE32_REGVAL_Pos) /*!< REGFILE REGFILE32: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE33 --------------------------------------- -#define REGFILE_REGFILE33_REGVAL_Pos 0 /*!< REGFILE REGFILE33: REGVAL Position */ -#define REGFILE_REGFILE33_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE33_REGVAL_Pos) /*!< REGFILE REGFILE33: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE34 --------------------------------------- -#define REGFILE_REGFILE34_REGVAL_Pos 0 /*!< REGFILE REGFILE34: REGVAL Position */ -#define REGFILE_REGFILE34_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE34_REGVAL_Pos) /*!< REGFILE REGFILE34: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE35 --------------------------------------- -#define REGFILE_REGFILE35_REGVAL_Pos 0 /*!< REGFILE REGFILE35: REGVAL Position */ -#define REGFILE_REGFILE35_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE35_REGVAL_Pos) /*!< REGFILE REGFILE35: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE36 --------------------------------------- -#define REGFILE_REGFILE36_REGVAL_Pos 0 /*!< REGFILE REGFILE36: REGVAL Position */ -#define REGFILE_REGFILE36_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE36_REGVAL_Pos) /*!< REGFILE REGFILE36: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE37 --------------------------------------- -#define REGFILE_REGFILE37_REGVAL_Pos 0 /*!< REGFILE REGFILE37: REGVAL Position */ -#define REGFILE_REGFILE37_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE37_REGVAL_Pos) /*!< REGFILE REGFILE37: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE38 --------------------------------------- -#define REGFILE_REGFILE38_REGVAL_Pos 0 /*!< REGFILE REGFILE38: REGVAL Position */ -#define REGFILE_REGFILE38_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE38_REGVAL_Pos) /*!< REGFILE REGFILE38: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE39 --------------------------------------- -#define REGFILE_REGFILE39_REGVAL_Pos 0 /*!< REGFILE REGFILE39: REGVAL Position */ -#define REGFILE_REGFILE39_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE39_REGVAL_Pos) /*!< REGFILE REGFILE39: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE40 --------------------------------------- -#define REGFILE_REGFILE40_REGVAL_Pos 0 /*!< REGFILE REGFILE40: REGVAL Position */ -#define REGFILE_REGFILE40_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE40_REGVAL_Pos) /*!< REGFILE REGFILE40: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE41 --------------------------------------- -#define REGFILE_REGFILE41_REGVAL_Pos 0 /*!< REGFILE REGFILE41: REGVAL Position */ -#define REGFILE_REGFILE41_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE41_REGVAL_Pos) /*!< REGFILE REGFILE41: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE42 --------------------------------------- -#define REGFILE_REGFILE42_REGVAL_Pos 0 /*!< REGFILE REGFILE42: REGVAL Position */ -#define REGFILE_REGFILE42_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE42_REGVAL_Pos) /*!< REGFILE REGFILE42: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE43 --------------------------------------- -#define REGFILE_REGFILE43_REGVAL_Pos 0 /*!< REGFILE REGFILE43: REGVAL Position */ -#define REGFILE_REGFILE43_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE43_REGVAL_Pos) /*!< REGFILE REGFILE43: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE44 --------------------------------------- -#define REGFILE_REGFILE44_REGVAL_Pos 0 /*!< REGFILE REGFILE44: REGVAL Position */ -#define REGFILE_REGFILE44_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE44_REGVAL_Pos) /*!< REGFILE REGFILE44: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE45 --------------------------------------- -#define REGFILE_REGFILE45_REGVAL_Pos 0 /*!< REGFILE REGFILE45: REGVAL Position */ -#define REGFILE_REGFILE45_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE45_REGVAL_Pos) /*!< REGFILE REGFILE45: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE46 --------------------------------------- -#define REGFILE_REGFILE46_REGVAL_Pos 0 /*!< REGFILE REGFILE46: REGVAL Position */ -#define REGFILE_REGFILE46_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE46_REGVAL_Pos) /*!< REGFILE REGFILE46: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE47 --------------------------------------- -#define REGFILE_REGFILE47_REGVAL_Pos 0 /*!< REGFILE REGFILE47: REGVAL Position */ -#define REGFILE_REGFILE47_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE47_REGVAL_Pos) /*!< REGFILE REGFILE47: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE48 --------------------------------------- -#define REGFILE_REGFILE48_REGVAL_Pos 0 /*!< REGFILE REGFILE48: REGVAL Position */ -#define REGFILE_REGFILE48_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE48_REGVAL_Pos) /*!< REGFILE REGFILE48: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE49 --------------------------------------- -#define REGFILE_REGFILE49_REGVAL_Pos 0 /*!< REGFILE REGFILE49: REGVAL Position */ -#define REGFILE_REGFILE49_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE49_REGVAL_Pos) /*!< REGFILE REGFILE49: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE50 --------------------------------------- -#define REGFILE_REGFILE50_REGVAL_Pos 0 /*!< REGFILE REGFILE50: REGVAL Position */ -#define REGFILE_REGFILE50_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE50_REGVAL_Pos) /*!< REGFILE REGFILE50: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE51 --------------------------------------- -#define REGFILE_REGFILE51_REGVAL_Pos 0 /*!< REGFILE REGFILE51: REGVAL Position */ -#define REGFILE_REGFILE51_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE51_REGVAL_Pos) /*!< REGFILE REGFILE51: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE52 --------------------------------------- -#define REGFILE_REGFILE52_REGVAL_Pos 0 /*!< REGFILE REGFILE52: REGVAL Position */ -#define REGFILE_REGFILE52_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE52_REGVAL_Pos) /*!< REGFILE REGFILE52: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE53 --------------------------------------- -#define REGFILE_REGFILE53_REGVAL_Pos 0 /*!< REGFILE REGFILE53: REGVAL Position */ -#define REGFILE_REGFILE53_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE53_REGVAL_Pos) /*!< REGFILE REGFILE53: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE54 --------------------------------------- -#define REGFILE_REGFILE54_REGVAL_Pos 0 /*!< REGFILE REGFILE54: REGVAL Position */ -#define REGFILE_REGFILE54_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE54_REGVAL_Pos) /*!< REGFILE REGFILE54: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE55 --------------------------------------- -#define REGFILE_REGFILE55_REGVAL_Pos 0 /*!< REGFILE REGFILE55: REGVAL Position */ -#define REGFILE_REGFILE55_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE55_REGVAL_Pos) /*!< REGFILE REGFILE55: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE56 --------------------------------------- -#define REGFILE_REGFILE56_REGVAL_Pos 0 /*!< REGFILE REGFILE56: REGVAL Position */ -#define REGFILE_REGFILE56_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE56_REGVAL_Pos) /*!< REGFILE REGFILE56: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE57 --------------------------------------- -#define REGFILE_REGFILE57_REGVAL_Pos 0 /*!< REGFILE REGFILE57: REGVAL Position */ -#define REGFILE_REGFILE57_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE57_REGVAL_Pos) /*!< REGFILE REGFILE57: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE58 --------------------------------------- -#define REGFILE_REGFILE58_REGVAL_Pos 0 /*!< REGFILE REGFILE58: REGVAL Position */ -#define REGFILE_REGFILE58_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE58_REGVAL_Pos) /*!< REGFILE REGFILE58: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE59 --------------------------------------- -#define REGFILE_REGFILE59_REGVAL_Pos 0 /*!< REGFILE REGFILE59: REGVAL Position */ -#define REGFILE_REGFILE59_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE59_REGVAL_Pos) /*!< REGFILE REGFILE59: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE60 --------------------------------------- -#define REGFILE_REGFILE60_REGVAL_Pos 0 /*!< REGFILE REGFILE60: REGVAL Position */ -#define REGFILE_REGFILE60_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE60_REGVAL_Pos) /*!< REGFILE REGFILE60: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE61 --------------------------------------- -#define REGFILE_REGFILE61_REGVAL_Pos 0 /*!< REGFILE REGFILE61: REGVAL Position */ -#define REGFILE_REGFILE61_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE61_REGVAL_Pos) /*!< REGFILE REGFILE61: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE62 --------------------------------------- -#define REGFILE_REGFILE62_REGVAL_Pos 0 /*!< REGFILE REGFILE62: REGVAL Position */ -#define REGFILE_REGFILE62_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE62_REGVAL_Pos) /*!< REGFILE REGFILE62: REGVAL Mask */ - -// ------------------------------------ REGFILE_REGFILE63 --------------------------------------- -#define REGFILE_REGFILE63_REGVAL_Pos 0 /*!< REGFILE REGFILE63: REGVAL Position */ -#define REGFILE_REGFILE63_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE63_REGVAL_Pos) /*!< REGFILE REGFILE63: REGVAL Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- PMC Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------- PMC_PD0_SLEEP0_HW_ENA ------------------------------------- -#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos 0 /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Position */ -#define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Msk (0x01UL << PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos) /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Mask */ - -// ----------------------------------- PMC_PD0_SLEEP0_MODE -------------------------------------- -#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos 0 /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Position */ -#define PMC_PD0_SLEEP0_MODE_PWR_STATE_Msk (0xffffffffUL << PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos) /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- CREG Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- CREG_IRCTRM ------------------------------------------ -#define CREG_IRCTRM_TRM_Pos 0 /*!< CREG IRCTRM: TRM Position */ -#define CREG_IRCTRM_TRM_Msk (0x00000fffUL << CREG_IRCTRM_TRM_Pos) /*!< CREG IRCTRM: TRM Mask */ - -// --------------------------------------- CREG_CREG0 ------------------------------------------- -#define CREG_CREG0_EN1KHZ_Pos 0 /*!< CREG CREG0: EN1KHZ Position */ -#define CREG_CREG0_EN1KHZ_Msk (0x01UL << CREG_CREG0_EN1KHZ_Pos) /*!< CREG CREG0: EN1KHZ Mask */ -#define CREG_CREG0_EN32KHZ_Pos 1 /*!< CREG CREG0: EN32KHZ Position */ -#define CREG_CREG0_EN32KHZ_Msk (0x01UL << CREG_CREG0_EN32KHZ_Pos) /*!< CREG CREG0: EN32KHZ Mask */ -#define CREG_CREG0_RESET32KHZ_Pos 2 /*!< CREG CREG0: RESET32KHZ Position */ -#define CREG_CREG0_RESET32KHZ_Msk (0x01UL << CREG_CREG0_RESET32KHZ_Pos) /*!< CREG CREG0: RESET32KHZ Mask */ -#define CREG_CREG0_32KHZPD_Pos 3 /*!< CREG CREG0: 32KHZPD Position */ -#define CREG_CREG0_32KHZPD_Msk (0x01UL << CREG_CREG0_32KHZPD_Pos) /*!< CREG CREG0: 32KHZPD Mask */ -#define CREG_CREG0_USB0PHY_Pos 5 /*!< CREG CREG0: USB0PHY Position */ -#define CREG_CREG0_USB0PHY_Msk (0x01UL << CREG_CREG0_USB0PHY_Pos) /*!< CREG CREG0: USB0PHY Mask */ -#define CREG_CREG0_ALARMCTRL_Pos 6 /*!< CREG CREG0: ALARMCTRL Position */ -#define CREG_CREG0_ALARMCTRL_Msk (0x03UL << CREG_CREG0_ALARMCTRL_Pos) /*!< CREG CREG0: ALARMCTRL Mask */ -#define CREG_CREG0_BODLVL1_Pos 8 /*!< CREG CREG0: BODLVL1 Position */ -#define CREG_CREG0_BODLVL1_Msk (0x03UL << CREG_CREG0_BODLVL1_Pos) /*!< CREG CREG0: BODLVL1 Mask */ -#define CREG_CREG0_BODLVL2_Pos 10 /*!< CREG CREG0: BODLVL2 Position */ -#define CREG_CREG0_BODLVL2_Msk (0x03UL << CREG_CREG0_BODLVL2_Pos) /*!< CREG CREG0: BODLVL2 Mask */ -#define CREG_CREG0_WAKEUP0CTRL_Pos 14 /*!< CREG CREG0: WAKEUP0CTRL Position */ -#define CREG_CREG0_WAKEUP0CTRL_Msk (0x03UL << CREG_CREG0_WAKEUP0CTRL_Pos) /*!< CREG CREG0: WAKEUP0CTRL Mask */ -#define CREG_CREG0_WAKEUP1CTRL_Pos 16 /*!< CREG CREG0: WAKEUP1CTRL Position */ -#define CREG_CREG0_WAKEUP1CTRL_Msk (0x03UL << CREG_CREG0_WAKEUP1CTRL_Pos) /*!< CREG CREG0: WAKEUP1CTRL Mask */ - -// -------------------------------------- CREG_M4MEMMAP ----------------------------------------- -#define CREG_M4MEMMAP_M4MAP_Pos 12 /*!< CREG M4MEMMAP: M4MAP Position */ -#define CREG_M4MEMMAP_M4MAP_Msk (0x000fffffUL << CREG_M4MEMMAP_M4MAP_Pos) /*!< CREG M4MEMMAP: M4MAP Mask */ - -// --------------------------------------- CREG_CREG5 ------------------------------------------- -#define CREG_CREG5_M4TAPSEL_Pos 6 /*!< CREG CREG5: M4TAPSEL Position */ -#define CREG_CREG5_M4TAPSEL_Msk (0x01UL << CREG_CREG5_M4TAPSEL_Pos) /*!< CREG CREG5: M4TAPSEL Mask */ - -// --------------------------------------- CREG_DMAMUX ------------------------------------------ -#define CREG_DMAMUX_DMAMUXCH0_Pos 0 /*!< CREG DMAMUX: DMAMUXCH0 Position */ -#define CREG_DMAMUX_DMAMUXCH0_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH0_Pos) /*!< CREG DMAMUX: DMAMUXCH0 Mask */ -#define CREG_DMAMUX_DMAMUXCH1_Pos 2 /*!< CREG DMAMUX: DMAMUXCH1 Position */ -#define CREG_DMAMUX_DMAMUXCH1_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH1_Pos) /*!< CREG DMAMUX: DMAMUXCH1 Mask */ -#define CREG_DMAMUX_DMAMUXCH2_Pos 4 /*!< CREG DMAMUX: DMAMUXCH2 Position */ -#define CREG_DMAMUX_DMAMUXCH2_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH2_Pos) /*!< CREG DMAMUX: DMAMUXCH2 Mask */ -#define CREG_DMAMUX_DMAMUXCH3_Pos 6 /*!< CREG DMAMUX: DMAMUXCH3 Position */ -#define CREG_DMAMUX_DMAMUXCH3_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH3_Pos) /*!< CREG DMAMUX: DMAMUXCH3 Mask */ -#define CREG_DMAMUX_DMAMUXCH4_Pos 8 /*!< CREG DMAMUX: DMAMUXCH4 Position */ -#define CREG_DMAMUX_DMAMUXCH4_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH4_Pos) /*!< CREG DMAMUX: DMAMUXCH4 Mask */ -#define CREG_DMAMUX_DMAMUXCH5_Pos 10 /*!< CREG DMAMUX: DMAMUXCH5 Position */ -#define CREG_DMAMUX_DMAMUXCH5_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH5_Pos) /*!< CREG DMAMUX: DMAMUXCH5 Mask */ -#define CREG_DMAMUX_DMAMUXCH6_Pos 12 /*!< CREG DMAMUX: DMAMUXCH6 Position */ -#define CREG_DMAMUX_DMAMUXCH6_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH6_Pos) /*!< CREG DMAMUX: DMAMUXCH6 Mask */ -#define CREG_DMAMUX_DMAMUXCH7_Pos 14 /*!< CREG DMAMUX: DMAMUXCH7 Position */ -#define CREG_DMAMUX_DMAMUXCH7_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH7_Pos) /*!< CREG DMAMUX: DMAMUXCH7 Mask */ -#define CREG_DMAMUX_DMAMUXCH8_Pos 16 /*!< CREG DMAMUX: DMAMUXCH8 Position */ -#define CREG_DMAMUX_DMAMUXCH8_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH8_Pos) /*!< CREG DMAMUX: DMAMUXCH8 Mask */ -#define CREG_DMAMUX_DMAMUXCH9_Pos 18 /*!< CREG DMAMUX: DMAMUXCH9 Position */ -#define CREG_DMAMUX_DMAMUXCH9_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH9_Pos) /*!< CREG DMAMUX: DMAMUXCH9 Mask */ -#define CREG_DMAMUX_DMAMUXCH10_Pos 20 /*!< CREG DMAMUX: DMAMUXCH10 Position */ -#define CREG_DMAMUX_DMAMUXCH10_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH10_Pos) /*!< CREG DMAMUX: DMAMUXCH10 Mask */ -#define CREG_DMAMUX_DMAMUXCH11_Pos 22 /*!< CREG DMAMUX: DMAMUXCH11 Position */ -#define CREG_DMAMUX_DMAMUXCH11_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH11_Pos) /*!< CREG DMAMUX: DMAMUXCH11 Mask */ -#define CREG_DMAMUX_DMAMUXCH12_Pos 24 /*!< CREG DMAMUX: DMAMUXCH12 Position */ -#define CREG_DMAMUX_DMAMUXCH12_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH12_Pos) /*!< CREG DMAMUX: DMAMUXCH12 Mask */ -#define CREG_DMAMUX_DMAMUXCH13_Pos 26 /*!< CREG DMAMUX: DMAMUXCH13 Position */ -#define CREG_DMAMUX_DMAMUXCH13_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH13_Pos) /*!< CREG DMAMUX: DMAMUXCH13 Mask */ -#define CREG_DMAMUX_DMAMUXCH14_Pos 28 /*!< CREG DMAMUX: DMAMUXCH14 Position */ -#define CREG_DMAMUX_DMAMUXCH14_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH14_Pos) /*!< CREG DMAMUX: DMAMUXCH14 Mask */ -#define CREG_DMAMUX_DMAMUXCH15_Pos 30 /*!< CREG DMAMUX: DMAMUXCH15 Position */ -#define CREG_DMAMUX_DMAMUXCH15_Msk (0x03UL << CREG_DMAMUX_DMAMUXCH15_Pos) /*!< CREG DMAMUX: DMAMUXCH15 Mask */ - -// --------------------------------------- CREG_ETBCFG ------------------------------------------ -#define CREG_ETBCFG_ETB_Pos 0 /*!< CREG ETBCFG: ETB Position */ -#define CREG_ETBCFG_ETB_Msk (0x01UL << CREG_ETBCFG_ETB_Pos) /*!< CREG ETBCFG: ETB Mask */ - -// --------------------------------------- CREG_CREG6 ------------------------------------------- -#define CREG_CREG6_ETHMODE_Pos 0 /*!< CREG CREG6: ETHMODE Position */ -#define CREG_CREG6_ETHMODE_Msk (0x07UL << CREG_CREG6_ETHMODE_Pos) /*!< CREG CREG6: ETHMODE Mask */ -#define CREG_CREG6_TIMCTRL_Pos 4 /*!< CREG CREG6: TIMCTRL Position */ -#define CREG_CREG6_TIMCTRL_Msk (0x01UL << CREG_CREG6_TIMCTRL_Pos) /*!< CREG CREG6: TIMCTRL Mask */ -#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos 12 /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Position */ -#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Mask */ -#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos 13 /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Position */ -#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Mask */ -#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos 14 /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Position */ -#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Mask */ -#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos 15 /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Position */ -#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Mask */ -#define CREG_CREG6_EMC_CLK_SEL_Pos 16 /*!< CREG CREG6: EMC_CLK_SEL Position */ -#define CREG_CREG6_EMC_CLK_SEL_Msk (0x01UL << CREG_CREG6_EMC_CLK_SEL_Pos) /*!< CREG CREG6: EMC_CLK_SEL Mask */ - -// ------------------------------------- CREG_M4TXEVENT ----------------------------------------- -#define CREG_M4TXEVENT_TXEVCLR_Pos 0 /*!< CREG M4TXEVENT: TXEVCLR Position */ -#define CREG_M4TXEVENT_TXEVCLR_Msk (0x01UL << CREG_M4TXEVENT_TXEVCLR_Pos) /*!< CREG M4TXEVENT: TXEVCLR Mask */ - -// --------------------------------------- CREG_CHIPID ------------------------------------------ -#define CREG_CHIPID_ID_Pos 0 /*!< CREG CHIPID: ID Position */ -#define CREG_CHIPID_ID_Msk (0xffffffffUL << CREG_CHIPID_ID_Pos) /*!< CREG CHIPID: ID Mask */ - -// ------------------------------------- CREG_M0TXEVENT ----------------------------------------- -#define CREG_M0TXEVENT_TXEVCLR_Pos 0 /*!< CREG M0TXEVENT: TXEVCLR Position */ -#define CREG_M0TXEVENT_TXEVCLR_Msk (0x01UL << CREG_M0TXEVENT_TXEVCLR_Pos) /*!< CREG M0TXEVENT: TXEVCLR Mask */ - -// ------------------------------------ CREG_M0APPMEMMAP ---------------------------------------- -#define CREG_M0APPMEMMAP_M0APPMAP_Pos 12 /*!< CREG M0APPMEMMAP: M0APPMAP Position */ -#define CREG_M0APPMEMMAP_M0APPMAP_Msk (0x000fffffUL << CREG_M0APPMEMMAP_M0APPMAP_Pos) /*!< CREG M0APPMEMMAP: M0APPMAP Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- EVENTROUTER Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ------------------------------------ EVENTROUTER_HILO ---------------------------------------- -#define EVENTROUTER_HILO_WAKEUP0_L_Pos 0 /*!< EVENTROUTER HILO: WAKEUP0_L Position */ -#define EVENTROUTER_HILO_WAKEUP0_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP0_L_Pos) /*!< EVENTROUTER HILO: WAKEUP0_L Mask */ -#define EVENTROUTER_HILO_WAKEUP1_L_Pos 1 /*!< EVENTROUTER HILO: WAKEUP1_L Position */ -#define EVENTROUTER_HILO_WAKEUP1_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP1_L_Pos) /*!< EVENTROUTER HILO: WAKEUP1_L Mask */ -#define EVENTROUTER_HILO_WAKEUP2_L_Pos 2 /*!< EVENTROUTER HILO: WAKEUP2_L Position */ -#define EVENTROUTER_HILO_WAKEUP2_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP2_L_Pos) /*!< EVENTROUTER HILO: WAKEUP2_L Mask */ -#define EVENTROUTER_HILO_WAKEUP3_L_Pos 3 /*!< EVENTROUTER HILO: WAKEUP3_L Position */ -#define EVENTROUTER_HILO_WAKEUP3_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP3_L_Pos) /*!< EVENTROUTER HILO: WAKEUP3_L Mask */ -#define EVENTROUTER_HILO_ATIMER_L_Pos 4 /*!< EVENTROUTER HILO: ATIMER_L Position */ -#define EVENTROUTER_HILO_ATIMER_L_Msk (0x01UL << EVENTROUTER_HILO_ATIMER_L_Pos) /*!< EVENTROUTER HILO: ATIMER_L Mask */ -#define EVENTROUTER_HILO_RTC_L_Pos 5 /*!< EVENTROUTER HILO: RTC_L Position */ -#define EVENTROUTER_HILO_RTC_L_Msk (0x01UL << EVENTROUTER_HILO_RTC_L_Pos) /*!< EVENTROUTER HILO: RTC_L Mask */ -#define EVENTROUTER_HILO_BOD_L_Pos 6 /*!< EVENTROUTER HILO: BOD_L Position */ -#define EVENTROUTER_HILO_BOD_L_Msk (0x01UL << EVENTROUTER_HILO_BOD_L_Pos) /*!< EVENTROUTER HILO: BOD_L Mask */ -#define EVENTROUTER_HILO_WWDT_L_Pos 7 /*!< EVENTROUTER HILO: WWDT_L Position */ -#define EVENTROUTER_HILO_WWDT_L_Msk (0x01UL << EVENTROUTER_HILO_WWDT_L_Pos) /*!< EVENTROUTER HILO: WWDT_L Mask */ -#define EVENTROUTER_HILO_ETH_L_Pos 8 /*!< EVENTROUTER HILO: ETH_L Position */ -#define EVENTROUTER_HILO_ETH_L_Msk (0x01UL << EVENTROUTER_HILO_ETH_L_Pos) /*!< EVENTROUTER HILO: ETH_L Mask */ -#define EVENTROUTER_HILO_USB0_L_Pos 9 /*!< EVENTROUTER HILO: USB0_L Position */ -#define EVENTROUTER_HILO_USB0_L_Msk (0x01UL << EVENTROUTER_HILO_USB0_L_Pos) /*!< EVENTROUTER HILO: USB0_L Mask */ -#define EVENTROUTER_HILO_USB1_L_Pos 10 /*!< EVENTROUTER HILO: USB1_L Position */ -#define EVENTROUTER_HILO_USB1_L_Msk (0x01UL << EVENTROUTER_HILO_USB1_L_Pos) /*!< EVENTROUTER HILO: USB1_L Mask */ -#define EVENTROUTER_HILO_SDMMC_L_Pos 11 /*!< EVENTROUTER HILO: SDMMC_L Position */ -#define EVENTROUTER_HILO_SDMMC_L_Msk (0x01UL << EVENTROUTER_HILO_SDMMC_L_Pos) /*!< EVENTROUTER HILO: SDMMC_L Mask */ -#define EVENTROUTER_HILO_CAN_L_Pos 12 /*!< EVENTROUTER HILO: CAN_L Position */ -#define EVENTROUTER_HILO_CAN_L_Msk (0x01UL << EVENTROUTER_HILO_CAN_L_Pos) /*!< EVENTROUTER HILO: CAN_L Mask */ -#define EVENTROUTER_HILO_TIM2_L_Pos 13 /*!< EVENTROUTER HILO: TIM2_L Position */ -#define EVENTROUTER_HILO_TIM2_L_Msk (0x01UL << EVENTROUTER_HILO_TIM2_L_Pos) /*!< EVENTROUTER HILO: TIM2_L Mask */ -#define EVENTROUTER_HILO_TIM6_L_Pos 14 /*!< EVENTROUTER HILO: TIM6_L Position */ -#define EVENTROUTER_HILO_TIM6_L_Msk (0x01UL << EVENTROUTER_HILO_TIM6_L_Pos) /*!< EVENTROUTER HILO: TIM6_L Mask */ -#define EVENTROUTER_HILO_QEI_L_Pos 15 /*!< EVENTROUTER HILO: QEI_L Position */ -#define EVENTROUTER_HILO_QEI_L_Msk (0x01UL << EVENTROUTER_HILO_QEI_L_Pos) /*!< EVENTROUTER HILO: QEI_L Mask */ -#define EVENTROUTER_HILO_TIM14_L_Pos 16 /*!< EVENTROUTER HILO: TIM14_L Position */ -#define EVENTROUTER_HILO_TIM14_L_Msk (0x01UL << EVENTROUTER_HILO_TIM14_L_Pos) /*!< EVENTROUTER HILO: TIM14_L Mask */ -#define EVENTROUTER_HILO_RESET_L_Pos 19 /*!< EVENTROUTER HILO: RESET_L Position */ -#define EVENTROUTER_HILO_RESET_L_Msk (0x01UL << EVENTROUTER_HILO_RESET_L_Pos) /*!< EVENTROUTER HILO: RESET_L Mask */ - -// ------------------------------------ EVENTROUTER_EDGE ---------------------------------------- -#define EVENTROUTER_EDGE_WAKEUP0_E_Pos 0 /*!< EVENTROUTER EDGE: WAKEUP0_E Position */ -#define EVENTROUTER_EDGE_WAKEUP0_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP0_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP0_E Mask */ -#define EVENTROUTER_EDGE_WAKEUP1_E_Pos 1 /*!< EVENTROUTER EDGE: WAKEUP1_E Position */ -#define EVENTROUTER_EDGE_WAKEUP1_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP1_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP1_E Mask */ -#define EVENTROUTER_EDGE_WAKEUP2_E_Pos 2 /*!< EVENTROUTER EDGE: WAKEUP2_E Position */ -#define EVENTROUTER_EDGE_WAKEUP2_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP2_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP2_E Mask */ -#define EVENTROUTER_EDGE_WAKEUP3_E_Pos 3 /*!< EVENTROUTER EDGE: WAKEUP3_E Position */ -#define EVENTROUTER_EDGE_WAKEUP3_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP3_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP3_E Mask */ -#define EVENTROUTER_EDGE_ATIMER_E_Pos 4 /*!< EVENTROUTER EDGE: ATIMER_E Position */ -#define EVENTROUTER_EDGE_ATIMER_E_Msk (0x01UL << EVENTROUTER_EDGE_ATIMER_E_Pos) /*!< EVENTROUTER EDGE: ATIMER_E Mask */ -#define EVENTROUTER_EDGE_RTC_E_Pos 5 /*!< EVENTROUTER EDGE: RTC_E Position */ -#define EVENTROUTER_EDGE_RTC_E_Msk (0x01UL << EVENTROUTER_EDGE_RTC_E_Pos) /*!< EVENTROUTER EDGE: RTC_E Mask */ -#define EVENTROUTER_EDGE_BOD_E_Pos 6 /*!< EVENTROUTER EDGE: BOD_E Position */ -#define EVENTROUTER_EDGE_BOD_E_Msk (0x01UL << EVENTROUTER_EDGE_BOD_E_Pos) /*!< EVENTROUTER EDGE: BOD_E Mask */ -#define EVENTROUTER_EDGE_WWDT_E_Pos 7 /*!< EVENTROUTER EDGE: WWDT_E Position */ -#define EVENTROUTER_EDGE_WWDT_E_Msk (0x01UL << EVENTROUTER_EDGE_WWDT_E_Pos) /*!< EVENTROUTER EDGE: WWDT_E Mask */ -#define EVENTROUTER_EDGE_ETH_E_Pos 8 /*!< EVENTROUTER EDGE: ETH_E Position */ -#define EVENTROUTER_EDGE_ETH_E_Msk (0x01UL << EVENTROUTER_EDGE_ETH_E_Pos) /*!< EVENTROUTER EDGE: ETH_E Mask */ -#define EVENTROUTER_EDGE_USB0_E_Pos 9 /*!< EVENTROUTER EDGE: USB0_E Position */ -#define EVENTROUTER_EDGE_USB0_E_Msk (0x01UL << EVENTROUTER_EDGE_USB0_E_Pos) /*!< EVENTROUTER EDGE: USB0_E Mask */ -#define EVENTROUTER_EDGE_USB1_E_Pos 10 /*!< EVENTROUTER EDGE: USB1_E Position */ -#define EVENTROUTER_EDGE_USB1_E_Msk (0x01UL << EVENTROUTER_EDGE_USB1_E_Pos) /*!< EVENTROUTER EDGE: USB1_E Mask */ -#define EVENTROUTER_EDGE_SDMMC_E_Pos 11 /*!< EVENTROUTER EDGE: SDMMC_E Position */ -#define EVENTROUTER_EDGE_SDMMC_E_Msk (0x01UL << EVENTROUTER_EDGE_SDMMC_E_Pos) /*!< EVENTROUTER EDGE: SDMMC_E Mask */ -#define EVENTROUTER_EDGE_CAN_E_Pos 12 /*!< EVENTROUTER EDGE: CAN_E Position */ -#define EVENTROUTER_EDGE_CAN_E_Msk (0x01UL << EVENTROUTER_EDGE_CAN_E_Pos) /*!< EVENTROUTER EDGE: CAN_E Mask */ -#define EVENTROUTER_EDGE_TIM2_E_Pos 13 /*!< EVENTROUTER EDGE: TIM2_E Position */ -#define EVENTROUTER_EDGE_TIM2_E_Msk (0x01UL << EVENTROUTER_EDGE_TIM2_E_Pos) /*!< EVENTROUTER EDGE: TIM2_E Mask */ -#define EVENTROUTER_EDGE_TIM6_E_Pos 14 /*!< EVENTROUTER EDGE: TIM6_E Position */ -#define EVENTROUTER_EDGE_TIM6_E_Msk (0x01UL << EVENTROUTER_EDGE_TIM6_E_Pos) /*!< EVENTROUTER EDGE: TIM6_E Mask */ -#define EVENTROUTER_EDGE_QEI_E_Pos 15 /*!< EVENTROUTER EDGE: QEI_E Position */ -#define EVENTROUTER_EDGE_QEI_E_Msk (0x01UL << EVENTROUTER_EDGE_QEI_E_Pos) /*!< EVENTROUTER EDGE: QEI_E Mask */ -#define EVENTROUTER_EDGE_TIM14_E_Pos 16 /*!< EVENTROUTER EDGE: TIM14_E Position */ -#define EVENTROUTER_EDGE_TIM14_E_Msk (0x01UL << EVENTROUTER_EDGE_TIM14_E_Pos) /*!< EVENTROUTER EDGE: TIM14_E Mask */ -#define EVENTROUTER_EDGE_RESET_E_Pos 19 /*!< EVENTROUTER EDGE: RESET_E Position */ -#define EVENTROUTER_EDGE_RESET_E_Msk (0x01UL << EVENTROUTER_EDGE_RESET_E_Pos) /*!< EVENTROUTER EDGE: RESET_E Mask */ - -// ----------------------------------- EVENTROUTER_CLR_EN --------------------------------------- -#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos 0 /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Position */ -#define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Mask */ -#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos 1 /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Position */ -#define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Mask */ -#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos 2 /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Position */ -#define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Mask */ -#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos 3 /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Position */ -#define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Mask */ -#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos 4 /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Position */ -#define EVENTROUTER_CLR_EN_ATIMER_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos) /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Mask */ -#define EVENTROUTER_CLR_EN_RTC_CLREN_Pos 5 /*!< EVENTROUTER CLR_EN: RTC_CLREN Position */ -#define EVENTROUTER_CLR_EN_RTC_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_RTC_CLREN_Pos) /*!< EVENTROUTER CLR_EN: RTC_CLREN Mask */ -#define EVENTROUTER_CLR_EN_BOD_CLREN_Pos 6 /*!< EVENTROUTER CLR_EN: BOD_CLREN Position */ -#define EVENTROUTER_CLR_EN_BOD_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_BOD_CLREN_Pos) /*!< EVENTROUTER CLR_EN: BOD_CLREN Mask */ -#define EVENTROUTER_CLR_EN_WWDT_CLREN_Pos 7 /*!< EVENTROUTER CLR_EN: WWDT_CLREN Position */ -#define EVENTROUTER_CLR_EN_WWDT_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WWDT_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WWDT_CLREN Mask */ -#define EVENTROUTER_CLR_EN_ETH_CLREN_Pos 8 /*!< EVENTROUTER CLR_EN: ETH_CLREN Position */ -#define EVENTROUTER_CLR_EN_ETH_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_ETH_CLREN_Pos) /*!< EVENTROUTER CLR_EN: ETH_CLREN Mask */ -#define EVENTROUTER_CLR_EN_USB0_CLREN_Pos 9 /*!< EVENTROUTER CLR_EN: USB0_CLREN Position */ -#define EVENTROUTER_CLR_EN_USB0_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_USB0_CLREN_Pos) /*!< EVENTROUTER CLR_EN: USB0_CLREN Mask */ -#define EVENTROUTER_CLR_EN_USB1_CLREN_Pos 10 /*!< EVENTROUTER CLR_EN: USB1_CLREN Position */ -#define EVENTROUTER_CLR_EN_USB1_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_USB1_CLREN_Pos) /*!< EVENTROUTER CLR_EN: USB1_CLREN Mask */ -#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos 11 /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Position */ -#define EVENTROUTER_CLR_EN_SDMMC_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos) /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Mask */ -#define EVENTROUTER_CLR_EN_CAN_CLREN_Pos 12 /*!< EVENTROUTER CLR_EN: CAN_CLREN Position */ -#define EVENTROUTER_CLR_EN_CAN_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_CAN_CLREN_Pos) /*!< EVENTROUTER CLR_EN: CAN_CLREN Mask */ -#define EVENTROUTER_CLR_EN_TIM2_CLREN_Pos 13 /*!< EVENTROUTER CLR_EN: TIM2_CLREN Position */ -#define EVENTROUTER_CLR_EN_TIM2_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_TIM2_CLREN_Pos) /*!< EVENTROUTER CLR_EN: TIM2_CLREN Mask */ -#define EVENTROUTER_CLR_EN_TIM6_CLREN_Pos 14 /*!< EVENTROUTER CLR_EN: TIM6_CLREN Position */ -#define EVENTROUTER_CLR_EN_TIM6_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_TIM6_CLREN_Pos) /*!< EVENTROUTER CLR_EN: TIM6_CLREN Mask */ -#define EVENTROUTER_CLR_EN_QEI_CLREN_Pos 15 /*!< EVENTROUTER CLR_EN: QEI_CLREN Position */ -#define EVENTROUTER_CLR_EN_QEI_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_QEI_CLREN_Pos) /*!< EVENTROUTER CLR_EN: QEI_CLREN Mask */ -#define EVENTROUTER_CLR_EN_TIM14_CLREN_Pos 16 /*!< EVENTROUTER CLR_EN: TIM14_CLREN Position */ -#define EVENTROUTER_CLR_EN_TIM14_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_TIM14_CLREN_Pos) /*!< EVENTROUTER CLR_EN: TIM14_CLREN Mask */ -#define EVENTROUTER_CLR_EN_RESET_CLREN_Pos 19 /*!< EVENTROUTER CLR_EN: RESET_CLREN Position */ -#define EVENTROUTER_CLR_EN_RESET_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_RESET_CLREN_Pos) /*!< EVENTROUTER CLR_EN: RESET_CLREN Mask */ - -// ----------------------------------- EVENTROUTER_SET_EN --------------------------------------- -#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos 0 /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Position */ -#define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Mask */ -#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos 1 /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Position */ -#define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Mask */ -#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos 2 /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Position */ -#define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Mask */ -#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos 3 /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Position */ -#define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Mask */ -#define EVENTROUTER_SET_EN_ATIMER_SETEN_Pos 4 /*!< EVENTROUTER SET_EN: ATIMER_SETEN Position */ -#define EVENTROUTER_SET_EN_ATIMER_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_ATIMER_SETEN_Pos) /*!< EVENTROUTER SET_EN: ATIMER_SETEN Mask */ -#define EVENTROUTER_SET_EN_RTC_SETEN_Pos 5 /*!< EVENTROUTER SET_EN: RTC_SETEN Position */ -#define EVENTROUTER_SET_EN_RTC_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_RTC_SETEN_Pos) /*!< EVENTROUTER SET_EN: RTC_SETEN Mask */ -#define EVENTROUTER_SET_EN_BOD_SETEN_Pos 6 /*!< EVENTROUTER SET_EN: BOD_SETEN Position */ -#define EVENTROUTER_SET_EN_BOD_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_BOD_SETEN_Pos) /*!< EVENTROUTER SET_EN: BOD_SETEN Mask */ -#define EVENTROUTER_SET_EN_WWDT_SETEN_Pos 7 /*!< EVENTROUTER SET_EN: WWDT_SETEN Position */ -#define EVENTROUTER_SET_EN_WWDT_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WWDT_SETEN_Pos) /*!< EVENTROUTER SET_EN: WWDT_SETEN Mask */ -#define EVENTROUTER_SET_EN_ETH_SETEN_Pos 8 /*!< EVENTROUTER SET_EN: ETH_SETEN Position */ -#define EVENTROUTER_SET_EN_ETH_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_ETH_SETEN_Pos) /*!< EVENTROUTER SET_EN: ETH_SETEN Mask */ -#define EVENTROUTER_SET_EN_USB0_SETEN_Pos 9 /*!< EVENTROUTER SET_EN: USB0_SETEN Position */ -#define EVENTROUTER_SET_EN_USB0_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_USB0_SETEN_Pos) /*!< EVENTROUTER SET_EN: USB0_SETEN Mask */ -#define EVENTROUTER_SET_EN_USB1_SETEN_Pos 10 /*!< EVENTROUTER SET_EN: USB1_SETEN Position */ -#define EVENTROUTER_SET_EN_USB1_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_USB1_SETEN_Pos) /*!< EVENTROUTER SET_EN: USB1_SETEN Mask */ -#define EVENTROUTER_SET_EN_SDMMC_SETEN_Pos 11 /*!< EVENTROUTER SET_EN: SDMMC_SETEN Position */ -#define EVENTROUTER_SET_EN_SDMMC_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_SDMMC_SETEN_Pos) /*!< EVENTROUTER SET_EN: SDMMC_SETEN Mask */ -#define EVENTROUTER_SET_EN_CAN_SETEN_Pos 12 /*!< EVENTROUTER SET_EN: CAN_SETEN Position */ -#define EVENTROUTER_SET_EN_CAN_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_CAN_SETEN_Pos) /*!< EVENTROUTER SET_EN: CAN_SETEN Mask */ -#define EVENTROUTER_SET_EN_TIM2_SETEN_Pos 13 /*!< EVENTROUTER SET_EN: TIM2_SETEN Position */ -#define EVENTROUTER_SET_EN_TIM2_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_TIM2_SETEN_Pos) /*!< EVENTROUTER SET_EN: TIM2_SETEN Mask */ -#define EVENTROUTER_SET_EN_TIM6_SETEN_Pos 14 /*!< EVENTROUTER SET_EN: TIM6_SETEN Position */ -#define EVENTROUTER_SET_EN_TIM6_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_TIM6_SETEN_Pos) /*!< EVENTROUTER SET_EN: TIM6_SETEN Mask */ -#define EVENTROUTER_SET_EN_QEI_SETEN_Pos 15 /*!< EVENTROUTER SET_EN: QEI_SETEN Position */ -#define EVENTROUTER_SET_EN_QEI_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_QEI_SETEN_Pos) /*!< EVENTROUTER SET_EN: QEI_SETEN Mask */ -#define EVENTROUTER_SET_EN_TIM14_SETEN_Pos 16 /*!< EVENTROUTER SET_EN: TIM14_SETEN Position */ -#define EVENTROUTER_SET_EN_TIM14_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_TIM14_SETEN_Pos) /*!< EVENTROUTER SET_EN: TIM14_SETEN Mask */ -#define EVENTROUTER_SET_EN_RESET_SETEN_Pos 19 /*!< EVENTROUTER SET_EN: RESET_SETEN Position */ -#define EVENTROUTER_SET_EN_RESET_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_RESET_SETEN_Pos) /*!< EVENTROUTER SET_EN: RESET_SETEN Mask */ - -// ----------------------------------- EVENTROUTER_STATUS --------------------------------------- -#define EVENTROUTER_STATUS_WAKEUP0_ST_Pos 0 /*!< EVENTROUTER STATUS: WAKEUP0_ST Position */ -#define EVENTROUTER_STATUS_WAKEUP0_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP0_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP0_ST Mask */ -#define EVENTROUTER_STATUS_WAKEUP1_ST_Pos 1 /*!< EVENTROUTER STATUS: WAKEUP1_ST Position */ -#define EVENTROUTER_STATUS_WAKEUP1_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP1_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP1_ST Mask */ -#define EVENTROUTER_STATUS_WAKEUP2_ST_Pos 2 /*!< EVENTROUTER STATUS: WAKEUP2_ST Position */ -#define EVENTROUTER_STATUS_WAKEUP2_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP2_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP2_ST Mask */ -#define EVENTROUTER_STATUS_WAKEUP3_ST_Pos 3 /*!< EVENTROUTER STATUS: WAKEUP3_ST Position */ -#define EVENTROUTER_STATUS_WAKEUP3_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP3_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP3_ST Mask */ -#define EVENTROUTER_STATUS_ATIMER_ST_Pos 4 /*!< EVENTROUTER STATUS: ATIMER_ST Position */ -#define EVENTROUTER_STATUS_ATIMER_ST_Msk (0x01UL << EVENTROUTER_STATUS_ATIMER_ST_Pos) /*!< EVENTROUTER STATUS: ATIMER_ST Mask */ -#define EVENTROUTER_STATUS_RTC_ST_Pos 5 /*!< EVENTROUTER STATUS: RTC_ST Position */ -#define EVENTROUTER_STATUS_RTC_ST_Msk (0x01UL << EVENTROUTER_STATUS_RTC_ST_Pos) /*!< EVENTROUTER STATUS: RTC_ST Mask */ -#define EVENTROUTER_STATUS_BOD_ST_Pos 6 /*!< EVENTROUTER STATUS: BOD_ST Position */ -#define EVENTROUTER_STATUS_BOD_ST_Msk (0x01UL << EVENTROUTER_STATUS_BOD_ST_Pos) /*!< EVENTROUTER STATUS: BOD_ST Mask */ -#define EVENTROUTER_STATUS_WWDT_ST_Pos 7 /*!< EVENTROUTER STATUS: WWDT_ST Position */ -#define EVENTROUTER_STATUS_WWDT_ST_Msk (0x01UL << EVENTROUTER_STATUS_WWDT_ST_Pos) /*!< EVENTROUTER STATUS: WWDT_ST Mask */ -#define EVENTROUTER_STATUS_ETH_ST_Pos 8 /*!< EVENTROUTER STATUS: ETH_ST Position */ -#define EVENTROUTER_STATUS_ETH_ST_Msk (0x01UL << EVENTROUTER_STATUS_ETH_ST_Pos) /*!< EVENTROUTER STATUS: ETH_ST Mask */ -#define EVENTROUTER_STATUS_USB0_ST_Pos 9 /*!< EVENTROUTER STATUS: USB0_ST Position */ -#define EVENTROUTER_STATUS_USB0_ST_Msk (0x01UL << EVENTROUTER_STATUS_USB0_ST_Pos) /*!< EVENTROUTER STATUS: USB0_ST Mask */ -#define EVENTROUTER_STATUS_USB1_ST_Pos 10 /*!< EVENTROUTER STATUS: USB1_ST Position */ -#define EVENTROUTER_STATUS_USB1_ST_Msk (0x01UL << EVENTROUTER_STATUS_USB1_ST_Pos) /*!< EVENTROUTER STATUS: USB1_ST Mask */ -#define EVENTROUTER_STATUS_SDMMC_ST_Pos 11 /*!< EVENTROUTER STATUS: SDMMC_ST Position */ -#define EVENTROUTER_STATUS_SDMMC_ST_Msk (0x01UL << EVENTROUTER_STATUS_SDMMC_ST_Pos) /*!< EVENTROUTER STATUS: SDMMC_ST Mask */ -#define EVENTROUTER_STATUS_CAN_ST_Pos 12 /*!< EVENTROUTER STATUS: CAN_ST Position */ -#define EVENTROUTER_STATUS_CAN_ST_Msk (0x01UL << EVENTROUTER_STATUS_CAN_ST_Pos) /*!< EVENTROUTER STATUS: CAN_ST Mask */ -#define EVENTROUTER_STATUS_TIM2_ST_Pos 13 /*!< EVENTROUTER STATUS: TIM2_ST Position */ -#define EVENTROUTER_STATUS_TIM2_ST_Msk (0x01UL << EVENTROUTER_STATUS_TIM2_ST_Pos) /*!< EVENTROUTER STATUS: TIM2_ST Mask */ -#define EVENTROUTER_STATUS_TIM6_ST_Pos 14 /*!< EVENTROUTER STATUS: TIM6_ST Position */ -#define EVENTROUTER_STATUS_TIM6_ST_Msk (0x01UL << EVENTROUTER_STATUS_TIM6_ST_Pos) /*!< EVENTROUTER STATUS: TIM6_ST Mask */ -#define EVENTROUTER_STATUS_QEI_ST_Pos 15 /*!< EVENTROUTER STATUS: QEI_ST Position */ -#define EVENTROUTER_STATUS_QEI_ST_Msk (0x01UL << EVENTROUTER_STATUS_QEI_ST_Pos) /*!< EVENTROUTER STATUS: QEI_ST Mask */ -#define EVENTROUTER_STATUS_TIM14_ST_Pos 16 /*!< EVENTROUTER STATUS: TIM14_ST Position */ -#define EVENTROUTER_STATUS_TIM14_ST_Msk (0x01UL << EVENTROUTER_STATUS_TIM14_ST_Pos) /*!< EVENTROUTER STATUS: TIM14_ST Mask */ -#define EVENTROUTER_STATUS_RESET_ST_Pos 19 /*!< EVENTROUTER STATUS: RESET_ST Position */ -#define EVENTROUTER_STATUS_RESET_ST_Msk (0x01UL << EVENTROUTER_STATUS_RESET_ST_Pos) /*!< EVENTROUTER STATUS: RESET_ST Mask */ - -// ----------------------------------- EVENTROUTER_ENABLE --------------------------------------- -#define EVENTROUTER_ENABLE_WAKEUP0_EN_Pos 0 /*!< EVENTROUTER ENABLE: WAKEUP0_EN Position */ -#define EVENTROUTER_ENABLE_WAKEUP0_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP0_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP0_EN Mask */ -#define EVENTROUTER_ENABLE_WAKEUP1_EN_Pos 1 /*!< EVENTROUTER ENABLE: WAKEUP1_EN Position */ -#define EVENTROUTER_ENABLE_WAKEUP1_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP1_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP1_EN Mask */ -#define EVENTROUTER_ENABLE_WAKEUP2_EN_Pos 2 /*!< EVENTROUTER ENABLE: WAKEUP2_EN Position */ -#define EVENTROUTER_ENABLE_WAKEUP2_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP2_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP2_EN Mask */ -#define EVENTROUTER_ENABLE_WAKEUP3_EN_Pos 3 /*!< EVENTROUTER ENABLE: WAKEUP3_EN Position */ -#define EVENTROUTER_ENABLE_WAKEUP3_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP3_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP3_EN Mask */ -#define EVENTROUTER_ENABLE_ATIMER_EN_Pos 4 /*!< EVENTROUTER ENABLE: ATIMER_EN Position */ -#define EVENTROUTER_ENABLE_ATIMER_EN_Msk (0x01UL << EVENTROUTER_ENABLE_ATIMER_EN_Pos) /*!< EVENTROUTER ENABLE: ATIMER_EN Mask */ -#define EVENTROUTER_ENABLE_RTC_EN_Pos 5 /*!< EVENTROUTER ENABLE: RTC_EN Position */ -#define EVENTROUTER_ENABLE_RTC_EN_Msk (0x01UL << EVENTROUTER_ENABLE_RTC_EN_Pos) /*!< EVENTROUTER ENABLE: RTC_EN Mask */ -#define EVENTROUTER_ENABLE_BOD_EN_Pos 6 /*!< EVENTROUTER ENABLE: BOD_EN Position */ -#define EVENTROUTER_ENABLE_BOD_EN_Msk (0x01UL << EVENTROUTER_ENABLE_BOD_EN_Pos) /*!< EVENTROUTER ENABLE: BOD_EN Mask */ -#define EVENTROUTER_ENABLE_WWDT_EN_Pos 7 /*!< EVENTROUTER ENABLE: WWDT_EN Position */ -#define EVENTROUTER_ENABLE_WWDT_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WWDT_EN_Pos) /*!< EVENTROUTER ENABLE: WWDT_EN Mask */ -#define EVENTROUTER_ENABLE_ETH_EN_Pos 8 /*!< EVENTROUTER ENABLE: ETH_EN Position */ -#define EVENTROUTER_ENABLE_ETH_EN_Msk (0x01UL << EVENTROUTER_ENABLE_ETH_EN_Pos) /*!< EVENTROUTER ENABLE: ETH_EN Mask */ -#define EVENTROUTER_ENABLE_USB0_EN_Pos 9 /*!< EVENTROUTER ENABLE: USB0_EN Position */ -#define EVENTROUTER_ENABLE_USB0_EN_Msk (0x01UL << EVENTROUTER_ENABLE_USB0_EN_Pos) /*!< EVENTROUTER ENABLE: USB0_EN Mask */ -#define EVENTROUTER_ENABLE_USB1_EN_Pos 10 /*!< EVENTROUTER ENABLE: USB1_EN Position */ -#define EVENTROUTER_ENABLE_USB1_EN_Msk (0x01UL << EVENTROUTER_ENABLE_USB1_EN_Pos) /*!< EVENTROUTER ENABLE: USB1_EN Mask */ -#define EVENTROUTER_ENABLE_SDMMC_EN_Pos 11 /*!< EVENTROUTER ENABLE: SDMMC_EN Position */ -#define EVENTROUTER_ENABLE_SDMMC_EN_Msk (0x01UL << EVENTROUTER_ENABLE_SDMMC_EN_Pos) /*!< EVENTROUTER ENABLE: SDMMC_EN Mask */ -#define EVENTROUTER_ENABLE_CAN_EN_Pos 12 /*!< EVENTROUTER ENABLE: CAN_EN Position */ -#define EVENTROUTER_ENABLE_CAN_EN_Msk (0x01UL << EVENTROUTER_ENABLE_CAN_EN_Pos) /*!< EVENTROUTER ENABLE: CAN_EN Mask */ -#define EVENTROUTER_ENABLE_TIM2_EN_Pos 13 /*!< EVENTROUTER ENABLE: TIM2_EN Position */ -#define EVENTROUTER_ENABLE_TIM2_EN_Msk (0x01UL << EVENTROUTER_ENABLE_TIM2_EN_Pos) /*!< EVENTROUTER ENABLE: TIM2_EN Mask */ -#define EVENTROUTER_ENABLE_TIM6_EN_Pos 14 /*!< EVENTROUTER ENABLE: TIM6_EN Position */ -#define EVENTROUTER_ENABLE_TIM6_EN_Msk (0x01UL << EVENTROUTER_ENABLE_TIM6_EN_Pos) /*!< EVENTROUTER ENABLE: TIM6_EN Mask */ -#define EVENTROUTER_ENABLE_QEI_EN_Pos 15 /*!< EVENTROUTER ENABLE: QEI_EN Position */ -#define EVENTROUTER_ENABLE_QEI_EN_Msk (0x01UL << EVENTROUTER_ENABLE_QEI_EN_Pos) /*!< EVENTROUTER ENABLE: QEI_EN Mask */ -#define EVENTROUTER_ENABLE_TIM14_EN_Pos 16 /*!< EVENTROUTER ENABLE: TIM14_EN Position */ -#define EVENTROUTER_ENABLE_TIM14_EN_Msk (0x01UL << EVENTROUTER_ENABLE_TIM14_EN_Pos) /*!< EVENTROUTER ENABLE: TIM14_EN Mask */ -#define EVENTROUTER_ENABLE_RESET_EN_Pos 19 /*!< EVENTROUTER ENABLE: RESET_EN Position */ -#define EVENTROUTER_ENABLE_RESET_EN_Msk (0x01UL << EVENTROUTER_ENABLE_RESET_EN_Pos) /*!< EVENTROUTER ENABLE: RESET_EN Mask */ - -// ---------------------------------- EVENTROUTER_CLR_STAT -------------------------------------- -#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos 0 /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Position */ -#define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos 1 /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Position */ -#define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos 2 /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Position */ -#define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos 3 /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Position */ -#define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos 4 /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Position */ -#define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_RTC_CLRST_Pos 5 /*!< EVENTROUTER CLR_STAT: RTC_CLRST Position */ -#define EVENTROUTER_CLR_STAT_RTC_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_RTC_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: RTC_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_BOD_CLRST_Pos 6 /*!< EVENTROUTER CLR_STAT: BOD_CLRST Position */ -#define EVENTROUTER_CLR_STAT_BOD_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_BOD_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: BOD_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos 7 /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Position */ -#define EVENTROUTER_CLR_STAT_WWDT_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_ETH_CLRST_Pos 8 /*!< EVENTROUTER CLR_STAT: ETH_CLRST Position */ -#define EVENTROUTER_CLR_STAT_ETH_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_ETH_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: ETH_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_USB0_CLRST_Pos 9 /*!< EVENTROUTER CLR_STAT: USB0_CLRST Position */ -#define EVENTROUTER_CLR_STAT_USB0_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_USB0_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: USB0_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_USB1_CLRST_Pos 10 /*!< EVENTROUTER CLR_STAT: USB1_CLRST Position */ -#define EVENTROUTER_CLR_STAT_USB1_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_USB1_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: USB1_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos 11 /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Position */ -#define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_CAN_CLRST_Pos 12 /*!< EVENTROUTER CLR_STAT: CAN_CLRST Position */ -#define EVENTROUTER_CLR_STAT_CAN_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_CAN_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: CAN_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos 13 /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Position */ -#define EVENTROUTER_CLR_STAT_TIM2_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos 14 /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Position */ -#define EVENTROUTER_CLR_STAT_TIM6_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_QEI_CLRST_Pos 15 /*!< EVENTROUTER CLR_STAT: QEI_CLRST Position */ -#define EVENTROUTER_CLR_STAT_QEI_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_QEI_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: QEI_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos 16 /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Position */ -#define EVENTROUTER_CLR_STAT_TIM14_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Mask */ -#define EVENTROUTER_CLR_STAT_RESET_CLRST_Pos 19 /*!< EVENTROUTER CLR_STAT: RESET_CLRST Position */ -#define EVENTROUTER_CLR_STAT_RESET_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_RESET_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: RESET_CLRST Mask */ - -// ---------------------------------- EVENTROUTER_SET_STAT -------------------------------------- -#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos 0 /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Position */ -#define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Mask */ -#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos 1 /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Position */ -#define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Mask */ -#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos 2 /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Position */ -#define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Mask */ -#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos 3 /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Position */ -#define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Mask */ -#define EVENTROUTER_SET_STAT_ATIMER_SETST_Pos 4 /*!< EVENTROUTER SET_STAT: ATIMER_SETST Position */ -#define EVENTROUTER_SET_STAT_ATIMER_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_ATIMER_SETST_Pos) /*!< EVENTROUTER SET_STAT: ATIMER_SETST Mask */ -#define EVENTROUTER_SET_STAT_RTC_SETST_Pos 5 /*!< EVENTROUTER SET_STAT: RTC_SETST Position */ -#define EVENTROUTER_SET_STAT_RTC_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_RTC_SETST_Pos) /*!< EVENTROUTER SET_STAT: RTC_SETST Mask */ -#define EVENTROUTER_SET_STAT_BOD_SETST_Pos 6 /*!< EVENTROUTER SET_STAT: BOD_SETST Position */ -#define EVENTROUTER_SET_STAT_BOD_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_BOD_SETST_Pos) /*!< EVENTROUTER SET_STAT: BOD_SETST Mask */ -#define EVENTROUTER_SET_STAT_WWDT_SETST_Pos 7 /*!< EVENTROUTER SET_STAT: WWDT_SETST Position */ -#define EVENTROUTER_SET_STAT_WWDT_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WWDT_SETST_Pos) /*!< EVENTROUTER SET_STAT: WWDT_SETST Mask */ -#define EVENTROUTER_SET_STAT_ETH_SETST_Pos 8 /*!< EVENTROUTER SET_STAT: ETH_SETST Position */ -#define EVENTROUTER_SET_STAT_ETH_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_ETH_SETST_Pos) /*!< EVENTROUTER SET_STAT: ETH_SETST Mask */ -#define EVENTROUTER_SET_STAT_USB0_SETST_Pos 9 /*!< EVENTROUTER SET_STAT: USB0_SETST Position */ -#define EVENTROUTER_SET_STAT_USB0_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_USB0_SETST_Pos) /*!< EVENTROUTER SET_STAT: USB0_SETST Mask */ -#define EVENTROUTER_SET_STAT_USB1_SETST_Pos 10 /*!< EVENTROUTER SET_STAT: USB1_SETST Position */ -#define EVENTROUTER_SET_STAT_USB1_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_USB1_SETST_Pos) /*!< EVENTROUTER SET_STAT: USB1_SETST Mask */ -#define EVENTROUTER_SET_STAT_SDMMC_SETST_Pos 11 /*!< EVENTROUTER SET_STAT: SDMMC_SETST Position */ -#define EVENTROUTER_SET_STAT_SDMMC_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_SDMMC_SETST_Pos) /*!< EVENTROUTER SET_STAT: SDMMC_SETST Mask */ -#define EVENTROUTER_SET_STAT_CAN_SETST_Pos 12 /*!< EVENTROUTER SET_STAT: CAN_SETST Position */ -#define EVENTROUTER_SET_STAT_CAN_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_CAN_SETST_Pos) /*!< EVENTROUTER SET_STAT: CAN_SETST Mask */ -#define EVENTROUTER_SET_STAT_TIM2_SETST_Pos 13 /*!< EVENTROUTER SET_STAT: TIM2_SETST Position */ -#define EVENTROUTER_SET_STAT_TIM2_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_TIM2_SETST_Pos) /*!< EVENTROUTER SET_STAT: TIM2_SETST Mask */ -#define EVENTROUTER_SET_STAT_TIM6_SETST_Pos 14 /*!< EVENTROUTER SET_STAT: TIM6_SETST Position */ -#define EVENTROUTER_SET_STAT_TIM6_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_TIM6_SETST_Pos) /*!< EVENTROUTER SET_STAT: TIM6_SETST Mask */ -#define EVENTROUTER_SET_STAT_QEI_SETST_Pos 15 /*!< EVENTROUTER SET_STAT: QEI_SETST Position */ -#define EVENTROUTER_SET_STAT_QEI_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_QEI_SETST_Pos) /*!< EVENTROUTER SET_STAT: QEI_SETST Mask */ -#define EVENTROUTER_SET_STAT_TIM14_SETST_Pos 16 /*!< EVENTROUTER SET_STAT: TIM14_SETST Position */ -#define EVENTROUTER_SET_STAT_TIM14_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_TIM14_SETST_Pos) /*!< EVENTROUTER SET_STAT: TIM14_SETST Mask */ -#define EVENTROUTER_SET_STAT_RESET_SETST_Pos 19 /*!< EVENTROUTER SET_STAT: RESET_SETST Position */ -#define EVENTROUTER_SET_STAT_RESET_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_RESET_SETST_Pos) /*!< EVENTROUTER SET_STAT: RESET_SETST Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- RTC Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ----------------------------------------- RTC_ILR -------------------------------------------- -#define RTC_ILR_RTCCIF_Pos 0 /*!< RTC ILR: RTCCIF Position */ -#define RTC_ILR_RTCCIF_Msk (0x01UL << RTC_ILR_RTCCIF_Pos) /*!< RTC ILR: RTCCIF Mask */ -#define RTC_ILR_RTCALF_Pos 1 /*!< RTC ILR: RTCALF Position */ -#define RTC_ILR_RTCALF_Msk (0x01UL << RTC_ILR_RTCALF_Pos) /*!< RTC ILR: RTCALF Mask */ - -// ----------------------------------------- RTC_CCR -------------------------------------------- -#define RTC_CCR_CLKEN_Pos 0 /*!< RTC CCR: CLKEN Position */ -#define RTC_CCR_CLKEN_Msk (0x01UL << RTC_CCR_CLKEN_Pos) /*!< RTC CCR: CLKEN Mask */ -#define RTC_CCR_CTCRST_Pos 1 /*!< RTC CCR: CTCRST Position */ -#define RTC_CCR_CTCRST_Msk (0x01UL << RTC_CCR_CTCRST_Pos) /*!< RTC CCR: CTCRST Mask */ -#define RTC_CCR_CCALEN_Pos 4 /*!< RTC CCR: CCALEN Position */ -#define RTC_CCR_CCALEN_Msk (0x01UL << RTC_CCR_CCALEN_Pos) /*!< RTC CCR: CCALEN Mask */ - -// ---------------------------------------- RTC_CIIR -------------------------------------------- -#define RTC_CIIR_IMSEC_Pos 0 /*!< RTC CIIR: IMSEC Position */ -#define RTC_CIIR_IMSEC_Msk (0x01UL << RTC_CIIR_IMSEC_Pos) /*!< RTC CIIR: IMSEC Mask */ -#define RTC_CIIR_IMMIN_Pos 1 /*!< RTC CIIR: IMMIN Position */ -#define RTC_CIIR_IMMIN_Msk (0x01UL << RTC_CIIR_IMMIN_Pos) /*!< RTC CIIR: IMMIN Mask */ -#define RTC_CIIR_IMHOUR_Pos 2 /*!< RTC CIIR: IMHOUR Position */ -#define RTC_CIIR_IMHOUR_Msk (0x01UL << RTC_CIIR_IMHOUR_Pos) /*!< RTC CIIR: IMHOUR Mask */ -#define RTC_CIIR_IMDOM_Pos 3 /*!< RTC CIIR: IMDOM Position */ -#define RTC_CIIR_IMDOM_Msk (0x01UL << RTC_CIIR_IMDOM_Pos) /*!< RTC CIIR: IMDOM Mask */ -#define RTC_CIIR_IMDOW_Pos 4 /*!< RTC CIIR: IMDOW Position */ -#define RTC_CIIR_IMDOW_Msk (0x01UL << RTC_CIIR_IMDOW_Pos) /*!< RTC CIIR: IMDOW Mask */ -#define RTC_CIIR_IMDOY_Pos 5 /*!< RTC CIIR: IMDOY Position */ -#define RTC_CIIR_IMDOY_Msk (0x01UL << RTC_CIIR_IMDOY_Pos) /*!< RTC CIIR: IMDOY Mask */ -#define RTC_CIIR_IMMON_Pos 6 /*!< RTC CIIR: IMMON Position */ -#define RTC_CIIR_IMMON_Msk (0x01UL << RTC_CIIR_IMMON_Pos) /*!< RTC CIIR: IMMON Mask */ -#define RTC_CIIR_IMYEAR_Pos 7 /*!< RTC CIIR: IMYEAR Position */ -#define RTC_CIIR_IMYEAR_Msk (0x01UL << RTC_CIIR_IMYEAR_Pos) /*!< RTC CIIR: IMYEAR Mask */ - -// ----------------------------------------- RTC_AMR -------------------------------------------- -#define RTC_AMR_AMRSEC_Pos 0 /*!< RTC AMR: AMRSEC Position */ -#define RTC_AMR_AMRSEC_Msk (0x01UL << RTC_AMR_AMRSEC_Pos) /*!< RTC AMR: AMRSEC Mask */ -#define RTC_AMR_AMRMIN_Pos 1 /*!< RTC AMR: AMRMIN Position */ -#define RTC_AMR_AMRMIN_Msk (0x01UL << RTC_AMR_AMRMIN_Pos) /*!< RTC AMR: AMRMIN Mask */ -#define RTC_AMR_AMRHOUR_Pos 2 /*!< RTC AMR: AMRHOUR Position */ -#define RTC_AMR_AMRHOUR_Msk (0x01UL << RTC_AMR_AMRHOUR_Pos) /*!< RTC AMR: AMRHOUR Mask */ -#define RTC_AMR_AMRDOM_Pos 3 /*!< RTC AMR: AMRDOM Position */ -#define RTC_AMR_AMRDOM_Msk (0x01UL << RTC_AMR_AMRDOM_Pos) /*!< RTC AMR: AMRDOM Mask */ -#define RTC_AMR_AMRDOW_Pos 4 /*!< RTC AMR: AMRDOW Position */ -#define RTC_AMR_AMRDOW_Msk (0x01UL << RTC_AMR_AMRDOW_Pos) /*!< RTC AMR: AMRDOW Mask */ -#define RTC_AMR_AMRDOY_Pos 5 /*!< RTC AMR: AMRDOY Position */ -#define RTC_AMR_AMRDOY_Msk (0x01UL << RTC_AMR_AMRDOY_Pos) /*!< RTC AMR: AMRDOY Mask */ -#define RTC_AMR_AMRMON_Pos 6 /*!< RTC AMR: AMRMON Position */ -#define RTC_AMR_AMRMON_Msk (0x01UL << RTC_AMR_AMRMON_Pos) /*!< RTC AMR: AMRMON Mask */ -#define RTC_AMR_AMRYEAR_Pos 7 /*!< RTC AMR: AMRYEAR Position */ -#define RTC_AMR_AMRYEAR_Msk (0x01UL << RTC_AMR_AMRYEAR_Pos) /*!< RTC AMR: AMRYEAR Mask */ - -// --------------------------------------- RTC_CTIME0 ------------------------------------------- -#define RTC_CTIME0_SECONDS_Pos 0 /*!< RTC CTIME0: SECONDS Position */ -#define RTC_CTIME0_SECONDS_Msk (0x3fUL << RTC_CTIME0_SECONDS_Pos) /*!< RTC CTIME0: SECONDS Mask */ -#define RTC_CTIME0_MINUTES_Pos 8 /*!< RTC CTIME0: MINUTES Position */ -#define RTC_CTIME0_MINUTES_Msk (0x3fUL << RTC_CTIME0_MINUTES_Pos) /*!< RTC CTIME0: MINUTES Mask */ -#define RTC_CTIME0_HOURS_Pos 16 /*!< RTC CTIME0: HOURS Position */ -#define RTC_CTIME0_HOURS_Msk (0x1fUL << RTC_CTIME0_HOURS_Pos) /*!< RTC CTIME0: HOURS Mask */ -#define RTC_CTIME0_DOW_Pos 24 /*!< RTC CTIME0: DOW Position */ -#define RTC_CTIME0_DOW_Msk (0x07UL << RTC_CTIME0_DOW_Pos) /*!< RTC CTIME0: DOW Mask */ - -// --------------------------------------- RTC_CTIME1 ------------------------------------------- -#define RTC_CTIME1_DOM_Pos 0 /*!< RTC CTIME1: DOM Position */ -#define RTC_CTIME1_DOM_Msk (0x1fUL << RTC_CTIME1_DOM_Pos) /*!< RTC CTIME1: DOM Mask */ -#define RTC_CTIME1_MONTH_Pos 8 /*!< RTC CTIME1: MONTH Position */ -#define RTC_CTIME1_MONTH_Msk (0x0fUL << RTC_CTIME1_MONTH_Pos) /*!< RTC CTIME1: MONTH Mask */ -#define RTC_CTIME1_YEAR_Pos 16 /*!< RTC CTIME1: YEAR Position */ -#define RTC_CTIME1_YEAR_Msk (0x00000fffUL << RTC_CTIME1_YEAR_Pos) /*!< RTC CTIME1: YEAR Mask */ - -// --------------------------------------- RTC_CTIME2 ------------------------------------------- -#define RTC_CTIME2_DOY_Pos 0 /*!< RTC CTIME2: DOY Position */ -#define RTC_CTIME2_DOY_Msk (0x00000fffUL << RTC_CTIME2_DOY_Pos) /*!< RTC CTIME2: DOY Mask */ - -// ----------------------------------------- RTC_SEC -------------------------------------------- -#define RTC_SEC_SECONDS_Pos 0 /*!< RTC SEC: SECONDS Position */ -#define RTC_SEC_SECONDS_Msk (0x3fUL << RTC_SEC_SECONDS_Pos) /*!< RTC SEC: SECONDS Mask */ - -// ----------------------------------------- RTC_MIN -------------------------------------------- -#define RTC_MIN_MINUTES_Pos 0 /*!< RTC MIN: MINUTES Position */ -#define RTC_MIN_MINUTES_Msk (0x3fUL << RTC_MIN_MINUTES_Pos) /*!< RTC MIN: MINUTES Mask */ - -// ----------------------------------------- RTC_HRS -------------------------------------------- -#define RTC_HRS_HOURS_Pos 0 /*!< RTC HRS: HOURS Position */ -#define RTC_HRS_HOURS_Msk (0x1fUL << RTC_HRS_HOURS_Pos) /*!< RTC HRS: HOURS Mask */ - -// ----------------------------------------- RTC_DOM -------------------------------------------- -#define RTC_DOM_DOM_Pos 0 /*!< RTC DOM: DOM Position */ -#define RTC_DOM_DOM_Msk (0x1fUL << RTC_DOM_DOM_Pos) /*!< RTC DOM: DOM Mask */ - -// ----------------------------------------- RTC_DOW -------------------------------------------- -#define RTC_DOW_DOW_Pos 0 /*!< RTC DOW: DOW Position */ -#define RTC_DOW_DOW_Msk (0x07UL << RTC_DOW_DOW_Pos) /*!< RTC DOW: DOW Mask */ - -// ----------------------------------------- RTC_DOY -------------------------------------------- -#define RTC_DOY_DOY_Pos 0 /*!< RTC DOY: DOY Position */ -#define RTC_DOY_DOY_Msk (0x000001ffUL << RTC_DOY_DOY_Pos) /*!< RTC DOY: DOY Mask */ - -// ---------------------------------------- RTC_MONTH ------------------------------------------- -#define RTC_MONTH_MONTH_Pos 0 /*!< RTC MONTH: MONTH Position */ -#define RTC_MONTH_MONTH_Msk (0x0fUL << RTC_MONTH_MONTH_Pos) /*!< RTC MONTH: MONTH Mask */ - -// ---------------------------------------- RTC_YEAR -------------------------------------------- -#define RTC_YEAR_YEAR_Pos 0 /*!< RTC YEAR: YEAR Position */ -#define RTC_YEAR_YEAR_Msk (0x00000fffUL << RTC_YEAR_YEAR_Pos) /*!< RTC YEAR: YEAR Mask */ - -// ------------------------------------- RTC_CALIBRATION ---------------------------------------- -#define RTC_CALIBRATION_CALVAL_Pos 0 /*!< RTC CALIBRATION: CALVAL Position */ -#define RTC_CALIBRATION_CALVAL_Msk (0x0001ffffUL << RTC_CALIBRATION_CALVAL_Pos) /*!< RTC CALIBRATION: CALVAL Mask */ -#define RTC_CALIBRATION_CALDIR_Pos 17 /*!< RTC CALIBRATION: CALDIR Position */ -#define RTC_CALIBRATION_CALDIR_Msk (0x01UL << RTC_CALIBRATION_CALDIR_Pos) /*!< RTC CALIBRATION: CALDIR Mask */ - -// ---------------------------------------- RTC_ASEC -------------------------------------------- -#define RTC_ASEC_SECONDS_Pos 0 /*!< RTC ASEC: SECONDS Position */ -#define RTC_ASEC_SECONDS_Msk (0x3fUL << RTC_ASEC_SECONDS_Pos) /*!< RTC ASEC: SECONDS Mask */ - -// ---------------------------------------- RTC_AMIN -------------------------------------------- -#define RTC_AMIN_MINUTES_Pos 0 /*!< RTC AMIN: MINUTES Position */ -#define RTC_AMIN_MINUTES_Msk (0x3fUL << RTC_AMIN_MINUTES_Pos) /*!< RTC AMIN: MINUTES Mask */ - -// ---------------------------------------- RTC_AHRS -------------------------------------------- -#define RTC_AHRS_HOURS_Pos 0 /*!< RTC AHRS: HOURS Position */ -#define RTC_AHRS_HOURS_Msk (0x1fUL << RTC_AHRS_HOURS_Pos) /*!< RTC AHRS: HOURS Mask */ - -// ---------------------------------------- RTC_ADOM -------------------------------------------- -#define RTC_ADOM_DOM_Pos 0 /*!< RTC ADOM: DOM Position */ -#define RTC_ADOM_DOM_Msk (0x1fUL << RTC_ADOM_DOM_Pos) /*!< RTC ADOM: DOM Mask */ - -// ---------------------------------------- RTC_ADOW -------------------------------------------- -#define RTC_ADOW_DOW_Pos 0 /*!< RTC ADOW: DOW Position */ -#define RTC_ADOW_DOW_Msk (0x07UL << RTC_ADOW_DOW_Pos) /*!< RTC ADOW: DOW Mask */ - -// ---------------------------------------- RTC_ADOY -------------------------------------------- -#define RTC_ADOY_DOY_Pos 0 /*!< RTC ADOY: DOY Position */ -#define RTC_ADOY_DOY_Msk (0x000001ffUL << RTC_ADOY_DOY_Pos) /*!< RTC ADOY: DOY Mask */ - -// ---------------------------------------- RTC_AMON -------------------------------------------- -#define RTC_AMON_MONTH_Pos 0 /*!< RTC AMON: MONTH Position */ -#define RTC_AMON_MONTH_Msk (0x0fUL << RTC_AMON_MONTH_Pos) /*!< RTC AMON: MONTH Mask */ - -// ---------------------------------------- RTC_AYRS -------------------------------------------- -#define RTC_AYRS_YEAR_Pos 0 /*!< RTC AYRS: YEAR Position */ -#define RTC_AYRS_YEAR_Msk (0x00000fffUL << RTC_AYRS_YEAR_Pos) /*!< RTC AYRS: YEAR Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- CGU Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// -------------------------------------- CGU_FREQ_MON ------------------------------------------ -#define CGU_FREQ_MON_RCNT_Pos 0 /*!< CGU FREQ_MON: RCNT Position */ -#define CGU_FREQ_MON_RCNT_Msk (0x000001ffUL << CGU_FREQ_MON_RCNT_Pos) /*!< CGU FREQ_MON: RCNT Mask */ -#define CGU_FREQ_MON_FCNT_Pos 9 /*!< CGU FREQ_MON: FCNT Position */ -#define CGU_FREQ_MON_FCNT_Msk (0x00003fffUL << CGU_FREQ_MON_FCNT_Pos) /*!< CGU FREQ_MON: FCNT Mask */ -#define CGU_FREQ_MON_MEAS_Pos 23 /*!< CGU FREQ_MON: MEAS Position */ -#define CGU_FREQ_MON_MEAS_Msk (0x01UL << CGU_FREQ_MON_MEAS_Pos) /*!< CGU FREQ_MON: MEAS Mask */ -#define CGU_FREQ_MON_CLK_SEL_Pos 24 /*!< CGU FREQ_MON: CLK_SEL Position */ -#define CGU_FREQ_MON_CLK_SEL_Msk (0x1fUL << CGU_FREQ_MON_CLK_SEL_Pos) /*!< CGU FREQ_MON: CLK_SEL Mask */ - -// ------------------------------------ CGU_XTAL_OSC_CTRL --------------------------------------- -#define CGU_XTAL_OSC_CTRL_ENABLE_Pos 0 /*!< CGU XTAL_OSC_CTRL: ENABLE Position */ -#define CGU_XTAL_OSC_CTRL_ENABLE_Msk (0x01UL << CGU_XTAL_OSC_CTRL_ENABLE_Pos) /*!< CGU XTAL_OSC_CTRL: ENABLE Mask */ -#define CGU_XTAL_OSC_CTRL_BYPASS_Pos 1 /*!< CGU XTAL_OSC_CTRL: BYPASS Position */ -#define CGU_XTAL_OSC_CTRL_BYPASS_Msk (0x01UL << CGU_XTAL_OSC_CTRL_BYPASS_Pos) /*!< CGU XTAL_OSC_CTRL: BYPASS Mask */ -#define CGU_XTAL_OSC_CTRL_HF_Pos 2 /*!< CGU XTAL_OSC_CTRL: HF Position */ -#define CGU_XTAL_OSC_CTRL_HF_Msk (0x01UL << CGU_XTAL_OSC_CTRL_HF_Pos) /*!< CGU XTAL_OSC_CTRL: HF Mask */ - -// ------------------------------------ CGU_PLL0USB_STAT ---------------------------------------- -#define CGU_PLL0USB_STAT_LOCK_Pos 0 /*!< CGU PLL0USB_STAT: LOCK Position */ -#define CGU_PLL0USB_STAT_LOCK_Msk (0x01UL << CGU_PLL0USB_STAT_LOCK_Pos) /*!< CGU PLL0USB_STAT: LOCK Mask */ -#define CGU_PLL0USB_STAT_FR_Pos 1 /*!< CGU PLL0USB_STAT: FR Position */ -#define CGU_PLL0USB_STAT_FR_Msk (0x01UL << CGU_PLL0USB_STAT_FR_Pos) /*!< CGU PLL0USB_STAT: FR Mask */ - -// ------------------------------------ CGU_PLL0USB_CTRL ---------------------------------------- -#define CGU_PLL0USB_CTRL_PD_Pos 0 /*!< CGU PLL0USB_CTRL: PD Position */ -#define CGU_PLL0USB_CTRL_PD_Msk (0x01UL << CGU_PLL0USB_CTRL_PD_Pos) /*!< CGU PLL0USB_CTRL: PD Mask */ -#define CGU_PLL0USB_CTRL_BYPASS_Pos 1 /*!< CGU PLL0USB_CTRL: BYPASS Position */ -#define CGU_PLL0USB_CTRL_BYPASS_Msk (0x01UL << CGU_PLL0USB_CTRL_BYPASS_Pos) /*!< CGU PLL0USB_CTRL: BYPASS Mask */ -#define CGU_PLL0USB_CTRL_DIRECTI_Pos 2 /*!< CGU PLL0USB_CTRL: DIRECTI Position */ -#define CGU_PLL0USB_CTRL_DIRECTI_Msk (0x01UL << CGU_PLL0USB_CTRL_DIRECTI_Pos) /*!< CGU PLL0USB_CTRL: DIRECTI Mask */ -#define CGU_PLL0USB_CTRL_DIRECTO_Pos 3 /*!< CGU PLL0USB_CTRL: DIRECTO Position */ -#define CGU_PLL0USB_CTRL_DIRECTO_Msk (0x01UL << CGU_PLL0USB_CTRL_DIRECTO_Pos) /*!< CGU PLL0USB_CTRL: DIRECTO Mask */ -#define CGU_PLL0USB_CTRL_CLKEN_Pos 4 /*!< CGU PLL0USB_CTRL: CLKEN Position */ -#define CGU_PLL0USB_CTRL_CLKEN_Msk (0x01UL << CGU_PLL0USB_CTRL_CLKEN_Pos) /*!< CGU PLL0USB_CTRL: CLKEN Mask */ -#define CGU_PLL0USB_CTRL_FRM_Pos 6 /*!< CGU PLL0USB_CTRL: FRM Position */ -#define CGU_PLL0USB_CTRL_FRM_Msk (0x01UL << CGU_PLL0USB_CTRL_FRM_Pos) /*!< CGU PLL0USB_CTRL: FRM Mask */ -#define CGU_PLL0USB_CTRL_AUTOBLOCK_Pos 11 /*!< CGU PLL0USB_CTRL: AUTOBLOCK Position */ -#define CGU_PLL0USB_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_PLL0USB_CTRL_AUTOBLOCK_Pos) /*!< CGU PLL0USB_CTRL: AUTOBLOCK Mask */ -#define CGU_PLL0USB_CTRL_CLK_SEL_Pos 24 /*!< CGU PLL0USB_CTRL: CLK_SEL Position */ -#define CGU_PLL0USB_CTRL_CLK_SEL_Msk (0x1fUL << CGU_PLL0USB_CTRL_CLK_SEL_Pos) /*!< CGU PLL0USB_CTRL: CLK_SEL Mask */ - -// ------------------------------------ CGU_PLL0USB_MDIV ---------------------------------------- -#define CGU_PLL0USB_MDIV_MDEC_Pos 0 /*!< CGU PLL0USB_MDIV: MDEC Position */ -#define CGU_PLL0USB_MDIV_MDEC_Msk (0x0001ffffUL << CGU_PLL0USB_MDIV_MDEC_Pos) /*!< CGU PLL0USB_MDIV: MDEC Mask */ -#define CGU_PLL0USB_MDIV_SELP_Pos 17 /*!< CGU PLL0USB_MDIV: SELP Position */ -#define CGU_PLL0USB_MDIV_SELP_Msk (0x1fUL << CGU_PLL0USB_MDIV_SELP_Pos) /*!< CGU PLL0USB_MDIV: SELP Mask */ -#define CGU_PLL0USB_MDIV_SELI_Pos 22 /*!< CGU PLL0USB_MDIV: SELI Position */ -#define CGU_PLL0USB_MDIV_SELI_Msk (0x3fUL << CGU_PLL0USB_MDIV_SELI_Pos) /*!< CGU PLL0USB_MDIV: SELI Mask */ -#define CGU_PLL0USB_MDIV_SELR_Pos 28 /*!< CGU PLL0USB_MDIV: SELR Position */ -#define CGU_PLL0USB_MDIV_SELR_Msk (0x0fUL << CGU_PLL0USB_MDIV_SELR_Pos) /*!< CGU PLL0USB_MDIV: SELR Mask */ - -// ----------------------------------- CGU_PLL0USB_NP_DIV --------------------------------------- -#define CGU_PLL0USB_NP_DIV_PDEC_Pos 0 /*!< CGU PLL0USB_NP_DIV: PDEC Position */ -#define CGU_PLL0USB_NP_DIV_PDEC_Msk (0x7fUL << CGU_PLL0USB_NP_DIV_PDEC_Pos) /*!< CGU PLL0USB_NP_DIV: PDEC Mask */ -#define CGU_PLL0USB_NP_DIV_NDEC_Pos 12 /*!< CGU PLL0USB_NP_DIV: NDEC Position */ -#define CGU_PLL0USB_NP_DIV_NDEC_Msk (0x000003ffUL << CGU_PLL0USB_NP_DIV_NDEC_Pos) /*!< CGU PLL0USB_NP_DIV: NDEC Mask */ - -// ----------------------------------- CGU_PLL0AUDIO_STAT --------------------------------------- -#define CGU_PLL0AUDIO_STAT_LOCK_Pos 0 /*!< CGU PLL0AUDIO_STAT: LOCK Position */ -#define CGU_PLL0AUDIO_STAT_LOCK_Msk (0x01UL << CGU_PLL0AUDIO_STAT_LOCK_Pos) /*!< CGU PLL0AUDIO_STAT: LOCK Mask */ -#define CGU_PLL0AUDIO_STAT_FR_Pos 1 /*!< CGU PLL0AUDIO_STAT: FR Position */ -#define CGU_PLL0AUDIO_STAT_FR_Msk (0x01UL << CGU_PLL0AUDIO_STAT_FR_Pos) /*!< CGU PLL0AUDIO_STAT: FR Mask */ - -// ----------------------------------- CGU_PLL0AUDIO_CTRL --------------------------------------- -#define CGU_PLL0AUDIO_CTRL_PD_Pos 0 /*!< CGU PLL0AUDIO_CTRL: PD Position */ -#define CGU_PLL0AUDIO_CTRL_PD_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_PD_Pos) /*!< CGU PLL0AUDIO_CTRL: PD Mask */ -#define CGU_PLL0AUDIO_CTRL_BYPASS_Pos 1 /*!< CGU PLL0AUDIO_CTRL: BYPASS Position */ -#define CGU_PLL0AUDIO_CTRL_BYPASS_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_BYPASS_Pos) /*!< CGU PLL0AUDIO_CTRL: BYPASS Mask */ -#define CGU_PLL0AUDIO_CTRL_DIRECTI_Pos 2 /*!< CGU PLL0AUDIO_CTRL: DIRECTI Position */ -#define CGU_PLL0AUDIO_CTRL_DIRECTI_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTI_Pos) /*!< CGU PLL0AUDIO_CTRL: DIRECTI Mask */ -#define CGU_PLL0AUDIO_CTRL_DIRECTO_Pos 3 /*!< CGU PLL0AUDIO_CTRL: DIRECTO Position */ -#define CGU_PLL0AUDIO_CTRL_DIRECTO_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTO_Pos) /*!< CGU PLL0AUDIO_CTRL: DIRECTO Mask */ -#define CGU_PLL0AUDIO_CTRL_CLKEN_Pos 4 /*!< CGU PLL0AUDIO_CTRL: CLKEN Position */ -#define CGU_PLL0AUDIO_CTRL_CLKEN_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_CLKEN_Pos) /*!< CGU PLL0AUDIO_CTRL: CLKEN Mask */ -#define CGU_PLL0AUDIO_CTRL_FRM_Pos 6 /*!< CGU PLL0AUDIO_CTRL: FRM Position */ -#define CGU_PLL0AUDIO_CTRL_FRM_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_FRM_Pos) /*!< CGU PLL0AUDIO_CTRL: FRM Mask */ -#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos 11 /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Position */ -#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos) /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Mask */ -#define CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Pos 12 /*!< CGU PLL0AUDIO_CTRL: PLLFRAQ_REQ Position */ -#define CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_PLLFRAQ_REQ_Pos) /*!< CGU PLL0AUDIO_CTRL: PLLFRAQ_REQ Mask */ -#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos 13 /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Position */ -#define CGU_PLL0AUDIO_CTRL_SEL_EXT_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos) /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Mask */ -#define CGU_PLL0AUDIO_CTRL_MOD_PD_Pos 14 /*!< CGU PLL0AUDIO_CTRL: MOD_PD Position */ -#define CGU_PLL0AUDIO_CTRL_MOD_PD_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_MOD_PD_Pos) /*!< CGU PLL0AUDIO_CTRL: MOD_PD Mask */ -#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos 24 /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Position */ -#define CGU_PLL0AUDIO_CTRL_CLK_SEL_Msk (0x1fUL << CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos) /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Mask */ - -// ----------------------------------- CGU_PLL0AUDIO_MDIV --------------------------------------- -#define CGU_PLL0AUDIO_MDIV_MDEC_Pos 0 /*!< CGU PLL0AUDIO_MDIV: MDEC Position */ -#define CGU_PLL0AUDIO_MDIV_MDEC_Msk (0x0001ffffUL << CGU_PLL0AUDIO_MDIV_MDEC_Pos) /*!< CGU PLL0AUDIO_MDIV: MDEC Mask */ - -// ---------------------------------- CGU_PLL0AUDIO_NP_DIV -------------------------------------- -#define CGU_PLL0AUDIO_NP_DIV_PDEC_Pos 0 /*!< CGU PLL0AUDIO_NP_DIV: PDEC Position */ -#define CGU_PLL0AUDIO_NP_DIV_PDEC_Msk (0x7fUL << CGU_PLL0AUDIO_NP_DIV_PDEC_Pos) /*!< CGU PLL0AUDIO_NP_DIV: PDEC Mask */ -#define CGU_PLL0AUDIO_NP_DIV_NDEC_Pos 12 /*!< CGU PLL0AUDIO_NP_DIV: NDEC Position */ -#define CGU_PLL0AUDIO_NP_DIV_NDEC_Msk (0x000003ffUL << CGU_PLL0AUDIO_NP_DIV_NDEC_Pos) /*!< CGU PLL0AUDIO_NP_DIV: NDEC Mask */ - -// ----------------------------------- CGU_PLL0AUDIO_FRAC --------------------------------------- -#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos 0 /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Position */ -#define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Msk (0x003fffffUL << CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos) /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Mask */ - -// -------------------------------------- CGU_PLL1_STAT ----------------------------------------- -#define CGU_PLL1_STAT_LOCK_Pos 0 /*!< CGU PLL1_STAT: LOCK Position */ -#define CGU_PLL1_STAT_LOCK_Msk (0x01UL << CGU_PLL1_STAT_LOCK_Pos) /*!< CGU PLL1_STAT: LOCK Mask */ - -// -------------------------------------- CGU_PLL1_CTRL ----------------------------------------- -#define CGU_PLL1_CTRL_PD_Pos 0 /*!< CGU PLL1_CTRL: PD Position */ -#define CGU_PLL1_CTRL_PD_Msk (0x01UL << CGU_PLL1_CTRL_PD_Pos) /*!< CGU PLL1_CTRL: PD Mask */ -#define CGU_PLL1_CTRL_BYPASS_Pos 1 /*!< CGU PLL1_CTRL: BYPASS Position */ -#define CGU_PLL1_CTRL_BYPASS_Msk (0x01UL << CGU_PLL1_CTRL_BYPASS_Pos) /*!< CGU PLL1_CTRL: BYPASS Mask */ -#define CGU_PLL1_CTRL_FBSEL_Pos 6 /*!< CGU PLL1_CTRL: FBSEL Position */ -#define CGU_PLL1_CTRL_FBSEL_Msk (0x01UL << CGU_PLL1_CTRL_FBSEL_Pos) /*!< CGU PLL1_CTRL: FBSEL Mask */ -#define CGU_PLL1_CTRL_DIRECT_Pos 7 /*!< CGU PLL1_CTRL: DIRECT Position */ -#define CGU_PLL1_CTRL_DIRECT_Msk (0x01UL << CGU_PLL1_CTRL_DIRECT_Pos) /*!< CGU PLL1_CTRL: DIRECT Mask */ -#define CGU_PLL1_CTRL_PSEL_Pos 8 /*!< CGU PLL1_CTRL: PSEL Position */ -#define CGU_PLL1_CTRL_PSEL_Msk (0x03UL << CGU_PLL1_CTRL_PSEL_Pos) /*!< CGU PLL1_CTRL: PSEL Mask */ -#define CGU_PLL1_CTRL_AUTOBLOCK_Pos 11 /*!< CGU PLL1_CTRL: AUTOBLOCK Position */ -#define CGU_PLL1_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_PLL1_CTRL_AUTOBLOCK_Pos) /*!< CGU PLL1_CTRL: AUTOBLOCK Mask */ -#define CGU_PLL1_CTRL_NSEL_Pos 12 /*!< CGU PLL1_CTRL: NSEL Position */ -#define CGU_PLL1_CTRL_NSEL_Msk (0x03UL << CGU_PLL1_CTRL_NSEL_Pos) /*!< CGU PLL1_CTRL: NSEL Mask */ -#define CGU_PLL1_CTRL_MSEL_Pos 16 /*!< CGU PLL1_CTRL: MSEL Position */ -#define CGU_PLL1_CTRL_MSEL_Msk (0x000000ffUL << CGU_PLL1_CTRL_MSEL_Pos) /*!< CGU PLL1_CTRL: MSEL Mask */ -#define CGU_PLL1_CTRL_CLK_SEL_Pos 24 /*!< CGU PLL1_CTRL: CLK_SEL Position */ -#define CGU_PLL1_CTRL_CLK_SEL_Msk (0x1fUL << CGU_PLL1_CTRL_CLK_SEL_Pos) /*!< CGU PLL1_CTRL: CLK_SEL Mask */ - -// ------------------------------------- CGU_IDIVA_CTRL ----------------------------------------- -#define CGU_IDIVA_CTRL_PD_Pos 0 /*!< CGU IDIVA_CTRL: PD Position */ -#define CGU_IDIVA_CTRL_PD_Msk (0x01UL << CGU_IDIVA_CTRL_PD_Pos) /*!< CGU IDIVA_CTRL: PD Mask */ -#define CGU_IDIVA_CTRL_IDIV_Pos 2 /*!< CGU IDIVA_CTRL: IDIV Position */ -#define CGU_IDIVA_CTRL_IDIV_Msk (0x03UL << CGU_IDIVA_CTRL_IDIV_Pos) /*!< CGU IDIVA_CTRL: IDIV Mask */ -#define CGU_IDIVA_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVA_CTRL: AUTOBLOCK Position */ -#define CGU_IDIVA_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVA_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVA_CTRL: AUTOBLOCK Mask */ -#define CGU_IDIVA_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVA_CTRL: CLK_SEL Position */ -#define CGU_IDIVA_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVA_CTRL_CLK_SEL_Pos) /*!< CGU IDIVA_CTRL: CLK_SEL Mask */ - -// ------------------------------------- CGU_IDIVB_CTRL ----------------------------------------- -#define CGU_IDIVB_CTRL_PD_Pos 0 /*!< CGU IDIVB_CTRL: PD Position */ -#define CGU_IDIVB_CTRL_PD_Msk (0x01UL << CGU_IDIVB_CTRL_PD_Pos) /*!< CGU IDIVB_CTRL: PD Mask */ -#define CGU_IDIVB_CTRL_IDIV_Pos 2 /*!< CGU IDIVB_CTRL: IDIV Position */ -#define CGU_IDIVB_CTRL_IDIV_Msk (0x0fUL << CGU_IDIVB_CTRL_IDIV_Pos) /*!< CGU IDIVB_CTRL: IDIV Mask */ -#define CGU_IDIVB_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVB_CTRL: AUTOBLOCK Position */ -#define CGU_IDIVB_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVB_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVB_CTRL: AUTOBLOCK Mask */ -#define CGU_IDIVB_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVB_CTRL: CLK_SEL Position */ -#define CGU_IDIVB_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVB_CTRL_CLK_SEL_Pos) /*!< CGU IDIVB_CTRL: CLK_SEL Mask */ - -// ------------------------------------- CGU_IDIVE_CTRL ----------------------------------------- -#define CGU_IDIVE_CTRL_PD_Pos 0 /*!< CGU IDIVE_CTRL: PD Position */ -#define CGU_IDIVE_CTRL_PD_Msk (0x01UL << CGU_IDIVE_CTRL_PD_Pos) /*!< CGU IDIVE_CTRL: PD Mask */ -#define CGU_IDIVE_CTRL_IDIV_Pos 2 /*!< CGU IDIVE_CTRL: IDIV Position */ -#define CGU_IDIVE_CTRL_IDIV_Msk (0x000000ffUL << CGU_IDIVE_CTRL_IDIV_Pos) /*!< CGU IDIVE_CTRL: IDIV Mask */ -#define CGU_IDIVE_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVE_CTRL: AUTOBLOCK Position */ -#define CGU_IDIVE_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVE_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVE_CTRL: AUTOBLOCK Mask */ -#define CGU_IDIVE_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVE_CTRL: CLK_SEL Position */ -#define CGU_IDIVE_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVE_CTRL_CLK_SEL_Pos) /*!< CGU IDIVE_CTRL: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_SAFE_CLK --------------------------------------- -#define CGU_BASE_SAFE_CLK_PD_Pos 0 /*!< CGU BASE_SAFE_CLK: PD Position */ -#define CGU_BASE_SAFE_CLK_PD_Msk (0x01UL << CGU_BASE_SAFE_CLK_PD_Pos) /*!< CGU BASE_SAFE_CLK: PD Mask */ -#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Position */ -#define CGU_BASE_SAFE_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_SAFE_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SAFE_CLK: CLK_SEL Position */ -#define CGU_BASE_SAFE_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SAFE_CLK_CLK_SEL_Pos) /*!< CGU BASE_SAFE_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_USB0_CLK --------------------------------------- -#define CGU_BASE_USB0_CLK_PD_Pos 0 /*!< CGU BASE_USB0_CLK: PD Position */ -#define CGU_BASE_USB0_CLK_PD_Msk (0x01UL << CGU_BASE_USB0_CLK_PD_Pos) /*!< CGU BASE_USB0_CLK: PD Mask */ -#define CGU_BASE_USB0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_USB0_CLK: AUTOBLOCK Position */ -#define CGU_BASE_USB0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_USB0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_USB0_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_USB0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_USB0_CLK: CLK_SEL Position */ -#define CGU_BASE_USB0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_USB0_CLK_CLK_SEL_Pos) /*!< CGU BASE_USB0_CLK: CLK_SEL Mask */ - -// ----------------------------------- CGU_BASE_PERIPH_CLK -------------------------------------- -#define CGU_BASE_PERIPH_CLK_PD_Pos 0 /*!< CGU BASE_PERIPH_CLK: PD Position */ -#define CGU_BASE_PERIPH_CLK_PD_Msk (0x01UL << CGU_BASE_PERIPH_CLK_PD_Pos) /*!< CGU BASE_PERIPH_CLK: PD Mask */ -#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Position */ -#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_PERIPH_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_PERIPH_CLK: CLK_SEL Position */ -#define CGU_BASE_PERIPH_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_PERIPH_CLK_CLK_SEL_Pos) /*!< CGU BASE_PERIPH_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_USB1_CLK --------------------------------------- -#define CGU_BASE_USB1_CLK_PD_Pos 0 /*!< CGU BASE_USB1_CLK: PD Position */ -#define CGU_BASE_USB1_CLK_PD_Msk (0x01UL << CGU_BASE_USB1_CLK_PD_Pos) /*!< CGU BASE_USB1_CLK: PD Mask */ -#define CGU_BASE_USB1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_USB1_CLK: AUTOBLOCK Position */ -#define CGU_BASE_USB1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_USB1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_USB1_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_USB1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_USB1_CLK: CLK_SEL Position */ -#define CGU_BASE_USB1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_USB1_CLK_CLK_SEL_Pos) /*!< CGU BASE_USB1_CLK: CLK_SEL Mask */ - -// ------------------------------------- CGU_BASE_M4_CLK ---------------------------------------- -#define CGU_BASE_M4_CLK_PD_Pos 0 /*!< CGU BASE_M4_CLK: PD Position */ -#define CGU_BASE_M4_CLK_PD_Msk (0x01UL << CGU_BASE_M4_CLK_PD_Pos) /*!< CGU BASE_M4_CLK: PD Mask */ -#define CGU_BASE_M4_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_M4_CLK: AUTOBLOCK Position */ -#define CGU_BASE_M4_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_M4_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_M4_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_M4_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_M4_CLK: CLK_SEL Position */ -#define CGU_BASE_M4_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_M4_CLK_CLK_SEL_Pos) /*!< CGU BASE_M4_CLK: CLK_SEL Mask */ - -// ----------------------------------- CGU_BASE_SPIFI_CLK --------------------------------------- -#define CGU_BASE_SPIFI_CLK_PD_Pos 0 /*!< CGU BASE_SPIFI_CLK: PD Position */ -#define CGU_BASE_SPIFI_CLK_PD_Msk (0x01UL << CGU_BASE_SPIFI_CLK_PD_Pos) /*!< CGU BASE_SPIFI_CLK: PD Mask */ -#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Position */ -#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_SPIFI_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SPIFI_CLK: CLK_SEL Position */ -#define CGU_BASE_SPIFI_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SPIFI_CLK_CLK_SEL_Pos) /*!< CGU BASE_SPIFI_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_SPI_CLK ---------------------------------------- -#define CGU_BASE_SPI_CLK_PD_Pos 0 /*!< CGU BASE_SPI_CLK: PD Position */ -#define CGU_BASE_SPI_CLK_PD_Msk (0x01UL << CGU_BASE_SPI_CLK_PD_Pos) /*!< CGU BASE_SPI_CLK: PD Mask */ -#define CGU_BASE_SPI_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SPI_CLK: AUTOBLOCK Position */ -#define CGU_BASE_SPI_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SPI_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SPI_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_SPI_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SPI_CLK: CLK_SEL Position */ -#define CGU_BASE_SPI_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SPI_CLK_CLK_SEL_Pos) /*!< CGU BASE_SPI_CLK: CLK_SEL Mask */ - -// ----------------------------------- CGU_BASE_PHY_RX_CLK -------------------------------------- -#define CGU_BASE_PHY_RX_CLK_PD_Pos 0 /*!< CGU BASE_PHY_RX_CLK: PD Position */ -#define CGU_BASE_PHY_RX_CLK_PD_Msk (0x01UL << CGU_BASE_PHY_RX_CLK_PD_Pos) /*!< CGU BASE_PHY_RX_CLK: PD Mask */ -#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Position */ -#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Position */ -#define CGU_BASE_PHY_RX_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos) /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Mask */ - -// ----------------------------------- CGU_BASE_PHY_TX_CLK -------------------------------------- -#define CGU_BASE_PHY_TX_CLK_PD_Pos 0 /*!< CGU BASE_PHY_TX_CLK: PD Position */ -#define CGU_BASE_PHY_TX_CLK_PD_Msk (0x01UL << CGU_BASE_PHY_TX_CLK_PD_Pos) /*!< CGU BASE_PHY_TX_CLK: PD Mask */ -#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Position */ -#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Position */ -#define CGU_BASE_PHY_TX_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos) /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_APB1_CLK --------------------------------------- -#define CGU_BASE_APB1_CLK_PD_Pos 0 /*!< CGU BASE_APB1_CLK: PD Position */ -#define CGU_BASE_APB1_CLK_PD_Msk (0x01UL << CGU_BASE_APB1_CLK_PD_Pos) /*!< CGU BASE_APB1_CLK: PD Mask */ -#define CGU_BASE_APB1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_APB1_CLK: AUTOBLOCK Position */ -#define CGU_BASE_APB1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_APB1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_APB1_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_APB1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_APB1_CLK: CLK_SEL Position */ -#define CGU_BASE_APB1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_APB1_CLK_CLK_SEL_Pos) /*!< CGU BASE_APB1_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_APB3_CLK --------------------------------------- -#define CGU_BASE_APB3_CLK_PD_Pos 0 /*!< CGU BASE_APB3_CLK: PD Position */ -#define CGU_BASE_APB3_CLK_PD_Msk (0x01UL << CGU_BASE_APB3_CLK_PD_Pos) /*!< CGU BASE_APB3_CLK: PD Mask */ -#define CGU_BASE_APB3_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_APB3_CLK: AUTOBLOCK Position */ -#define CGU_BASE_APB3_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_APB3_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_APB3_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_APB3_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_APB3_CLK: CLK_SEL Position */ -#define CGU_BASE_APB3_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_APB3_CLK_CLK_SEL_Pos) /*!< CGU BASE_APB3_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_LCD_CLK ---------------------------------------- -#define CGU_BASE_LCD_CLK_PD_Pos 0 /*!< CGU BASE_LCD_CLK: PD Position */ -#define CGU_BASE_LCD_CLK_PD_Msk (0x01UL << CGU_BASE_LCD_CLK_PD_Pos) /*!< CGU BASE_LCD_CLK: PD Mask */ -#define CGU_BASE_LCD_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_LCD_CLK: AUTOBLOCK Position */ -#define CGU_BASE_LCD_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_LCD_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_LCD_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_LCD_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_LCD_CLK: CLK_SEL Position */ -#define CGU_BASE_LCD_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_LCD_CLK_CLK_SEL_Pos) /*!< CGU BASE_LCD_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_SDIO_CLK --------------------------------------- -#define CGU_BASE_SDIO_CLK_PD_Pos 0 /*!< CGU BASE_SDIO_CLK: PD Position */ -#define CGU_BASE_SDIO_CLK_PD_Msk (0x01UL << CGU_BASE_SDIO_CLK_PD_Pos) /*!< CGU BASE_SDIO_CLK: PD Mask */ -#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Position */ -#define CGU_BASE_SDIO_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_SDIO_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SDIO_CLK: CLK_SEL Position */ -#define CGU_BASE_SDIO_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SDIO_CLK_CLK_SEL_Pos) /*!< CGU BASE_SDIO_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_SSP0_CLK --------------------------------------- -#define CGU_BASE_SSP0_CLK_PD_Pos 0 /*!< CGU BASE_SSP0_CLK: PD Position */ -#define CGU_BASE_SSP0_CLK_PD_Msk (0x01UL << CGU_BASE_SSP0_CLK_PD_Pos) /*!< CGU BASE_SSP0_CLK: PD Mask */ -#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Position */ -#define CGU_BASE_SSP0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_SSP0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SSP0_CLK: CLK_SEL Position */ -#define CGU_BASE_SSP0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SSP0_CLK_CLK_SEL_Pos) /*!< CGU BASE_SSP0_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_SSP1_CLK --------------------------------------- -#define CGU_BASE_SSP1_CLK_PD_Pos 0 /*!< CGU BASE_SSP1_CLK: PD Position */ -#define CGU_BASE_SSP1_CLK_PD_Msk (0x01UL << CGU_BASE_SSP1_CLK_PD_Pos) /*!< CGU BASE_SSP1_CLK: PD Mask */ -#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Position */ -#define CGU_BASE_SSP1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_SSP1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SSP1_CLK: CLK_SEL Position */ -#define CGU_BASE_SSP1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SSP1_CLK_CLK_SEL_Pos) /*!< CGU BASE_SSP1_CLK: CLK_SEL Mask */ - -// ----------------------------------- CGU_BASE_UART0_CLK --------------------------------------- -#define CGU_BASE_UART0_CLK_PD_Pos 0 /*!< CGU BASE_UART0_CLK: PD Position */ -#define CGU_BASE_UART0_CLK_PD_Msk (0x01UL << CGU_BASE_UART0_CLK_PD_Pos) /*!< CGU BASE_UART0_CLK: PD Mask */ -#define CGU_BASE_UART0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART0_CLK: AUTOBLOCK Position */ -#define CGU_BASE_UART0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART0_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_UART0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART0_CLK: CLK_SEL Position */ -#define CGU_BASE_UART0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART0_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART0_CLK: CLK_SEL Mask */ - -// ----------------------------------- CGU_BASE_UART1_CLK --------------------------------------- -#define CGU_BASE_UART1_CLK_PD_Pos 0 /*!< CGU BASE_UART1_CLK: PD Position */ -#define CGU_BASE_UART1_CLK_PD_Msk (0x01UL << CGU_BASE_UART1_CLK_PD_Pos) /*!< CGU BASE_UART1_CLK: PD Mask */ -#define CGU_BASE_UART1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART1_CLK: AUTOBLOCK Position */ -#define CGU_BASE_UART1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART1_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_UART1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART1_CLK: CLK_SEL Position */ -#define CGU_BASE_UART1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART1_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART1_CLK: CLK_SEL Mask */ - -// ----------------------------------- CGU_BASE_UART2_CLK --------------------------------------- -#define CGU_BASE_UART2_CLK_PD_Pos 0 /*!< CGU BASE_UART2_CLK: PD Position */ -#define CGU_BASE_UART2_CLK_PD_Msk (0x01UL << CGU_BASE_UART2_CLK_PD_Pos) /*!< CGU BASE_UART2_CLK: PD Mask */ -#define CGU_BASE_UART2_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART2_CLK: AUTOBLOCK Position */ -#define CGU_BASE_UART2_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART2_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART2_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_UART2_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART2_CLK: CLK_SEL Position */ -#define CGU_BASE_UART2_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART2_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART2_CLK: CLK_SEL Mask */ - -// ----------------------------------- CGU_BASE_UART3_CLK --------------------------------------- -#define CGU_BASE_UART3_CLK_PD_Pos 0 /*!< CGU BASE_UART3_CLK: PD Position */ -#define CGU_BASE_UART3_CLK_PD_Msk (0x01UL << CGU_BASE_UART3_CLK_PD_Pos) /*!< CGU BASE_UART3_CLK: PD Mask */ -#define CGU_BASE_UART3_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART3_CLK: AUTOBLOCK Position */ -#define CGU_BASE_UART3_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART3_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART3_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_UART3_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART3_CLK: CLK_SEL Position */ -#define CGU_BASE_UART3_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART3_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART3_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_OUT_CLK ---------------------------------------- -#define CGU_BASE_OUT_CLK_PD_Pos 0 /*!< CGU BASE_OUT_CLK: PD Position */ -#define CGU_BASE_OUT_CLK_PD_Msk (0x01UL << CGU_BASE_OUT_CLK_PD_Pos) /*!< CGU BASE_OUT_CLK: PD Mask */ -#define CGU_BASE_OUT_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_OUT_CLK: AUTOBLOCK Position */ -#define CGU_BASE_OUT_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_OUT_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_OUT_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_OUT_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_OUT_CLK: CLK_SEL Position */ -#define CGU_BASE_OUT_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_OUT_CLK_CLK_SEL_Pos) /*!< CGU BASE_OUT_CLK: CLK_SEL Mask */ - -// ------------------------------------ CGU_BASE_APLL_CLK --------------------------------------- -#define CGU_BASE_APLL_CLK_PD_Pos 0 /*!< CGU BASE_APLL_CLK: PD Position */ -#define CGU_BASE_APLL_CLK_PD_Msk (0x01UL << CGU_BASE_APLL_CLK_PD_Pos) /*!< CGU BASE_APLL_CLK: PD Mask */ -#define CGU_BASE_APLL_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_APLL_CLK: AUTOBLOCK Position */ -#define CGU_BASE_APLL_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_APLL_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_APLL_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_APLL_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_APLL_CLK: CLK_SEL Position */ -#define CGU_BASE_APLL_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_APLL_CLK_CLK_SEL_Pos) /*!< CGU BASE_APLL_CLK: CLK_SEL Mask */ - -// ---------------------------------- CGU_BASE_CGU_OUT0_CLK ------------------------------------- -#define CGU_BASE_CGU_OUT0_CLK_PD_Pos 0 /*!< CGU BASE_CGU_OUT0_CLK: PD Position */ -#define CGU_BASE_CGU_OUT0_CLK_PD_Msk (0x01UL << CGU_BASE_CGU_OUT0_CLK_PD_Pos) /*!< CGU BASE_CGU_OUT0_CLK: PD Mask */ -#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Position */ -#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Position */ -#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos) /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Mask */ - -// ---------------------------------- CGU_BASE_CGU_OUT1_CLK ------------------------------------- -#define CGU_BASE_CGU_OUT1_CLK_PD_Pos 0 /*!< CGU BASE_CGU_OUT1_CLK: PD Position */ -#define CGU_BASE_CGU_OUT1_CLK_PD_Msk (0x01UL << CGU_BASE_CGU_OUT1_CLK_PD_Pos) /*!< CGU BASE_CGU_OUT1_CLK: PD Mask */ -#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Position */ -#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Mask */ -#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Position */ -#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos) /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Mask */ - -// ------------------------------------- CGU_IDIVC_CTRL ----------------------------------------- -#define CGU_IDIVC_CTRL_PD_Pos 0 /*!< CGU IDIVC_CTRL: PD Position */ -#define CGU_IDIVC_CTRL_PD_Msk (0x01UL << CGU_IDIVC_CTRL_PD_Pos) /*!< CGU IDIVC_CTRL: PD Mask */ -#define CGU_IDIVC_CTRL_IDIV_Pos 2 /*!< CGU IDIVC_CTRL: IDIV Position */ -#define CGU_IDIVC_CTRL_IDIV_Msk (0x0fUL << CGU_IDIVC_CTRL_IDIV_Pos) /*!< CGU IDIVC_CTRL: IDIV Mask */ -#define CGU_IDIVC_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVC_CTRL: AUTOBLOCK Position */ -#define CGU_IDIVC_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVC_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVC_CTRL: AUTOBLOCK Mask */ -#define CGU_IDIVC_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVC_CTRL: CLK_SEL Position */ -#define CGU_IDIVC_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVC_CTRL_CLK_SEL_Pos) /*!< CGU IDIVC_CTRL: CLK_SEL Mask */ - -// ------------------------------------- CGU_IDIVD_CTRL ----------------------------------------- -#define CGU_IDIVD_CTRL_PD_Pos 0 /*!< CGU IDIVD_CTRL: PD Position */ -#define CGU_IDIVD_CTRL_PD_Msk (0x01UL << CGU_IDIVD_CTRL_PD_Pos) /*!< CGU IDIVD_CTRL: PD Mask */ -#define CGU_IDIVD_CTRL_IDIV_Pos 2 /*!< CGU IDIVD_CTRL: IDIV Position */ -#define CGU_IDIVD_CTRL_IDIV_Msk (0x0fUL << CGU_IDIVD_CTRL_IDIV_Pos) /*!< CGU IDIVD_CTRL: IDIV Mask */ -#define CGU_IDIVD_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVD_CTRL: AUTOBLOCK Position */ -#define CGU_IDIVD_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVD_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVD_CTRL: AUTOBLOCK Mask */ -#define CGU_IDIVD_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVD_CTRL: CLK_SEL Position */ -#define CGU_IDIVD_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVD_CTRL_CLK_SEL_Pos) /*!< CGU IDIVD_CTRL: CLK_SEL Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- CCU1 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ----------------------------------------- CCU1_PM -------------------------------------------- -#define CCU1_PM_PD_Pos 0 /*!< CCU1 PM: PD Position */ -#define CCU1_PM_PD_Msk (0x01UL << CCU1_PM_PD_Pos) /*!< CCU1 PM: PD Mask */ - -// ------------------------------------- CCU1_BASE_STAT ----------------------------------------- -#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos 0 /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Position */ -#define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Mask */ -#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos 1 /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Position */ -#define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Mask */ -#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos 2 /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Position */ -#define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Mask */ -#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos 3 /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Position */ -#define CCU1_BASE_STAT_BASE_M3_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Mask */ -#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos 7 /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Position */ -#define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Mask */ -#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos 8 /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Position */ -#define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Mask */ - -// ---------------------------------- CCU1_CLK_APB3_BUS_CFG ------------------------------------- -#define CCU1_CLK_APB3_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_BUS_CFG: RUN Position */ -#define CCU1_CLK_APB3_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_BUS_CFG: RUN Mask */ -#define CCU1_CLK_APB3_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Position */ -#define CCU1_CLK_APB3_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Mask */ -#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Position */ -#define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB3_BUS_STAT ------------------------------------- -#define CCU1_CLK_APB3_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_BUS_STAT: RUN Position */ -#define CCU1_CLK_APB3_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_BUS_STAT: RUN Mask */ -#define CCU1_CLK_APB3_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Position */ -#define CCU1_CLK_APB3_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Mask */ -#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Position */ -#define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB3_I2C1_CFG ------------------------------------- -#define CCU1_CLK_APB3_I2C1_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Position */ -#define CCU1_CLK_APB3_I2C1_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_I2C1_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Mask */ -#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Position */ -#define CCU1_CLK_APB3_I2C1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Mask */ -#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Position */ -#define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB3_I2C1_STAT ------------------------------------ -#define CCU1_CLK_APB3_I2C1_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Position */ -#define CCU1_CLK_APB3_I2C1_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_I2C1_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Mask */ -#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Position */ -#define CCU1_CLK_APB3_I2C1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Mask */ -#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Position */ -#define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_APB3_DAC_CFG ------------------------------------- -#define CCU1_CLK_APB3_DAC_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_DAC_CFG: RUN Position */ -#define CCU1_CLK_APB3_DAC_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_DAC_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_DAC_CFG: RUN Mask */ -#define CCU1_CLK_APB3_DAC_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Position */ -#define CCU1_CLK_APB3_DAC_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_DAC_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Mask */ -#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Position */ -#define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB3_DAC_STAT ------------------------------------- -#define CCU1_CLK_APB3_DAC_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_DAC_STAT: RUN Position */ -#define CCU1_CLK_APB3_DAC_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_DAC_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_DAC_STAT: RUN Mask */ -#define CCU1_CLK_APB3_DAC_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Position */ -#define CCU1_CLK_APB3_DAC_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_DAC_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Mask */ -#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Position */ -#define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB3_ADC0_CFG ------------------------------------- -#define CCU1_CLK_APB3_ADC0_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Position */ -#define CCU1_CLK_APB3_ADC0_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC0_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Mask */ -#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Position */ -#define CCU1_CLK_APB3_ADC0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Mask */ -#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Position */ -#define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB3_ADC0_STAT ------------------------------------ -#define CCU1_CLK_APB3_ADC0_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Position */ -#define CCU1_CLK_APB3_ADC0_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC0_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Mask */ -#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Position */ -#define CCU1_CLK_APB3_ADC0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Mask */ -#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Position */ -#define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB3_ADC1_CFG ------------------------------------- -#define CCU1_CLK_APB3_ADC1_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Position */ -#define CCU1_CLK_APB3_ADC1_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC1_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Mask */ -#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Position */ -#define CCU1_CLK_APB3_ADC1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Mask */ -#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Position */ -#define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB3_ADC1_STAT ------------------------------------ -#define CCU1_CLK_APB3_ADC1_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Position */ -#define CCU1_CLK_APB3_ADC1_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC1_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Mask */ -#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Position */ -#define CCU1_CLK_APB3_ADC1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Mask */ -#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Position */ -#define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB3_CAN0_CFG ------------------------------------- -#define CCU1_CLK_APB3_CAN0_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Position */ -#define CCU1_CLK_APB3_CAN0_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_CAN0_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Mask */ -#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Position */ -#define CCU1_CLK_APB3_CAN0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Mask */ -#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Position */ -#define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB3_CAN0_STAT ------------------------------------ -#define CCU1_CLK_APB3_CAN0_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Position */ -#define CCU1_CLK_APB3_CAN0_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_CAN0_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Mask */ -#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Position */ -#define CCU1_CLK_APB3_CAN0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Mask */ -#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Position */ -#define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_APB1_BUS_CFG ------------------------------------- -#define CCU1_CLK_APB1_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_BUS_CFG: RUN Position */ -#define CCU1_CLK_APB1_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_BUS_CFG: RUN Mask */ -#define CCU1_CLK_APB1_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Position */ -#define CCU1_CLK_APB1_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Mask */ -#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Position */ -#define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB1_BUS_STAT ------------------------------------- -#define CCU1_CLK_APB1_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_BUS_STAT: RUN Position */ -#define CCU1_CLK_APB1_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_BUS_STAT: RUN Mask */ -#define CCU1_CLK_APB1_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Position */ -#define CCU1_CLK_APB1_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Mask */ -#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Position */ -#define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Mask */ - -// ------------------------------ CCU1_CLK_APB1_MOTOCONPWM_CFG ---------------------------------- -#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Position */ -#define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Mask */ -#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Position */ -#define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Mask */ -#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Position */ -#define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Mask */ - -// ------------------------------ CCU1_CLK_APB1_MOTOCONPWM_STAT --------------------------------- -#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Position */ -#define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Mask */ -#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Position */ -#define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Mask */ -#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Position */ -#define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_ABP1_I2C0_CFG ------------------------------------- -#define CCU1_CLK_ABP1_I2C0_CFG_RUN_Pos 0 /*!< CCU1 CLK_ABP1_I2C0_CFG: RUN Position */ -#define CCU1_CLK_ABP1_I2C0_CFG_RUN_Msk (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_RUN_Pos) /*!< CCU1 CLK_ABP1_I2C0_CFG: RUN Mask */ -#define CCU1_CLK_ABP1_I2C0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_ABP1_I2C0_CFG: AUTO Position */ -#define CCU1_CLK_ABP1_I2C0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_AUTO_Pos) /*!< CCU1 CLK_ABP1_I2C0_CFG: AUTO Mask */ -#define CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_ABP1_I2C0_CFG: WAKEUP Position */ -#define CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_ABP1_I2C0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_ABP1_I2C0_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB1_I2C0_STAT ------------------------------------ -#define CCU1_CLK_APB1_I2C0_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Position */ -#define CCU1_CLK_APB1_I2C0_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2C0_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Mask */ -#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Position */ -#define CCU1_CLK_APB1_I2C0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Mask */ -#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Position */ -#define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_APB1_I2S_CFG ------------------------------------- -#define CCU1_CLK_APB1_I2S_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2S_CFG: RUN Position */ -#define CCU1_CLK_APB1_I2S_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2S_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_I2S_CFG: RUN Mask */ -#define CCU1_CLK_APB1_I2S_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Position */ -#define CCU1_CLK_APB1_I2S_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2S_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Mask */ -#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Position */ -#define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB1_I2S_STAT ------------------------------------- -#define CCU1_CLK_APB1_I2S_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2S_STAT: RUN Position */ -#define CCU1_CLK_APB1_I2S_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2S_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_I2S_STAT: RUN Mask */ -#define CCU1_CLK_APB1_I2S_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Position */ -#define CCU1_CLK_APB1_I2S_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2S_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Mask */ -#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Position */ -#define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB1_CAN1_CFG ------------------------------------- -#define CCU1_CLK_APB1_CAN1_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Position */ -#define CCU1_CLK_APB1_CAN1_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_CAN1_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Mask */ -#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Position */ -#define CCU1_CLK_APB1_CAN1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Mask */ -#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Position */ -#define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_APB1_CAN1_STAT ------------------------------------ -#define CCU1_CLK_APB1_CAN1_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Position */ -#define CCU1_CLK_APB1_CAN1_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_CAN1_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Mask */ -#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Position */ -#define CCU1_CLK_APB1_CAN1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Mask */ -#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Position */ -#define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_SPIFI_CFG --------------------------------------- -#define CCU1_CLK_SPIFI_CFG_RUN_Pos 0 /*!< CCU1 CLK_SPIFI_CFG: RUN Position */ -#define CCU1_CLK_SPIFI_CFG_RUN_Msk (0x01UL << CCU1_CLK_SPIFI_CFG_RUN_Pos) /*!< CCU1 CLK_SPIFI_CFG: RUN Mask */ -#define CCU1_CLK_SPIFI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_SPIFI_CFG: AUTO Position */ -#define CCU1_CLK_SPIFI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_SPIFI_CFG_AUTO_Pos) /*!< CCU1 CLK_SPIFI_CFG: AUTO Mask */ -#define CCU1_CLK_SPIFI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Position */ -#define CCU1_CLK_SPIFI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_SPIFI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_SPIFI_STAT -------------------------------------- -#define CCU1_CLK_SPIFI_STAT_RUN_Pos 0 /*!< CCU1 CLK_SPIFI_STAT: RUN Position */ -#define CCU1_CLK_SPIFI_STAT_RUN_Msk (0x01UL << CCU1_CLK_SPIFI_STAT_RUN_Pos) /*!< CCU1 CLK_SPIFI_STAT: RUN Mask */ -#define CCU1_CLK_SPIFI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_SPIFI_STAT: AUTO Position */ -#define CCU1_CLK_SPIFI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_SPIFI_STAT_AUTO_Pos) /*!< CCU1 CLK_SPIFI_STAT: AUTO Mask */ -#define CCU1_CLK_SPIFI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Position */ -#define CCU1_CLK_SPIFI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_SPIFI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_M4_BUS_CFG -------------------------------------- -#define CCU1_CLK_M4_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_BUS_CFG: RUN Position */ -#define CCU1_CLK_M4_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_M4_BUS_CFG: RUN Mask */ -#define CCU1_CLK_M4_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_BUS_CFG: AUTO Position */ -#define CCU1_CLK_M4_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_BUS_CFG: AUTO Mask */ -#define CCU1_CLK_M4_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_BUS_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_BUS_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_BUS_STAT -------------------------------------- -#define CCU1_CLK_M4_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_BUS_STAT: RUN Position */ -#define CCU1_CLK_M4_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_M4_BUS_STAT: RUN Mask */ -#define CCU1_CLK_M4_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_BUS_STAT: AUTO Position */ -#define CCU1_CLK_M4_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_BUS_STAT: AUTO Mask */ -#define CCU1_CLK_M4_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_BUS_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_BUS_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_SPIFI_CFG ------------------------------------- -#define CCU1_CLK_M4_SPIFI_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SPIFI_CFG: RUN Position */ -#define CCU1_CLK_M4_SPIFI_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SPIFI_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SPIFI_CFG: RUN Mask */ -#define CCU1_CLK_M4_SPIFI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SPIFI_CFG: AUTO Position */ -#define CCU1_CLK_M4_SPIFI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SPIFI_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SPIFI_CFG: AUTO Mask */ -#define CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SPIFI_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SPIFI_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_SPIFI_STAT ------------------------------------- -#define CCU1_CLK_M4_SPIFI_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SPIFI_STAT: RUN Position */ -#define CCU1_CLK_M4_SPIFI_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SPIFI_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SPIFI_STAT: RUN Mask */ -#define CCU1_CLK_M4_SPIFI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SPIFI_STAT: AUTO Position */ -#define CCU1_CLK_M4_SPIFI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SPIFI_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SPIFI_STAT: AUTO Mask */ -#define CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SPIFI_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SPIFI_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_GPIO_CFG -------------------------------------- -#define CCU1_CLK_M4_GPIO_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_GPIO_CFG: RUN Position */ -#define CCU1_CLK_M4_GPIO_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_GPIO_CFG_RUN_Pos) /*!< CCU1 CLK_M4_GPIO_CFG: RUN Mask */ -#define CCU1_CLK_M4_GPIO_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_GPIO_CFG: AUTO Position */ -#define CCU1_CLK_M4_GPIO_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_GPIO_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_GPIO_CFG: AUTO Mask */ -#define CCU1_CLK_M4_GPIO_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_GPIO_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_GPIO_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_GPIO_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_GPIO_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_GPIO_STAT ------------------------------------- -#define CCU1_CLK_M4_GPIO_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_GPIO_STAT: RUN Position */ -#define CCU1_CLK_M4_GPIO_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_GPIO_STAT_RUN_Pos) /*!< CCU1 CLK_M4_GPIO_STAT: RUN Mask */ -#define CCU1_CLK_M4_GPIO_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_GPIO_STAT: AUTO Position */ -#define CCU1_CLK_M4_GPIO_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_GPIO_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_GPIO_STAT: AUTO Mask */ -#define CCU1_CLK_M4_GPIO_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_GPIO_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_GPIO_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_GPIO_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_GPIO_STAT: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_M4_LCD_CFG -------------------------------------- -#define CCU1_CLK_M4_LCD_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_LCD_CFG: RUN Position */ -#define CCU1_CLK_M4_LCD_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_LCD_CFG_RUN_Pos) /*!< CCU1 CLK_M4_LCD_CFG: RUN Mask */ -#define CCU1_CLK_M4_LCD_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_LCD_CFG: AUTO Position */ -#define CCU1_CLK_M4_LCD_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_LCD_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_LCD_CFG: AUTO Mask */ -#define CCU1_CLK_M4_LCD_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_LCD_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_LCD_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_LCD_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_LCD_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_LCD_STAT -------------------------------------- -#define CCU1_CLK_M4_LCD_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_LCD_STAT: RUN Position */ -#define CCU1_CLK_M4_LCD_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_LCD_STAT_RUN_Pos) /*!< CCU1 CLK_M4_LCD_STAT: RUN Mask */ -#define CCU1_CLK_M4_LCD_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_LCD_STAT: AUTO Position */ -#define CCU1_CLK_M4_LCD_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_LCD_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_LCD_STAT: AUTO Mask */ -#define CCU1_CLK_M4_LCD_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_LCD_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_LCD_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_LCD_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_LCD_STAT: WAKEUP Mask */ - -// -------------------------------- CCU1_CLK_M4_ETHERNET_CFG ------------------------------------ -#define CCU1_CLK_M4_ETHERNET_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_ETHERNET_CFG: RUN Position */ -#define CCU1_CLK_M4_ETHERNET_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_RUN_Pos) /*!< CCU1 CLK_M4_ETHERNET_CFG: RUN Mask */ -#define CCU1_CLK_M4_ETHERNET_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_ETHERNET_CFG: AUTO Position */ -#define CCU1_CLK_M4_ETHERNET_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_ETHERNET_CFG: AUTO Mask */ -#define CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_ETHERNET_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_ETHERNET_CFG: WAKEUP Mask */ - -// -------------------------------- CCU1_CLK_M4_ETHERNET_STAT ----------------------------------- -#define CCU1_CLK_M4_ETHERNET_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_ETHERNET_STAT: RUN Position */ -#define CCU1_CLK_M4_ETHERNET_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_RUN_Pos) /*!< CCU1 CLK_M4_ETHERNET_STAT: RUN Mask */ -#define CCU1_CLK_M4_ETHERNET_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_ETHERNET_STAT: AUTO Position */ -#define CCU1_CLK_M4_ETHERNET_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_ETHERNET_STAT: AUTO Mask */ -#define CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_ETHERNET_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_ETHERNET_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_USB0_CFG -------------------------------------- -#define CCU1_CLK_M4_USB0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_USB0_CFG: RUN Position */ -#define CCU1_CLK_M4_USB0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_USB0_CFG_RUN_Pos) /*!< CCU1 CLK_M4_USB0_CFG: RUN Mask */ -#define CCU1_CLK_M4_USB0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_USB0_CFG: AUTO Position */ -#define CCU1_CLK_M4_USB0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_USB0_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_USB0_CFG: AUTO Mask */ -#define CCU1_CLK_M4_USB0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USB0_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_USB0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USB0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_USB0_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_USB0_STAT ------------------------------------- -#define CCU1_CLK_M4_USB0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_USB0_STAT: RUN Position */ -#define CCU1_CLK_M4_USB0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_USB0_STAT_RUN_Pos) /*!< CCU1 CLK_M4_USB0_STAT: RUN Mask */ -#define CCU1_CLK_M4_USB0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_USB0_STAT: AUTO Position */ -#define CCU1_CLK_M4_USB0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_USB0_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_USB0_STAT: AUTO Mask */ -#define CCU1_CLK_M4_USB0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USB0_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_USB0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USB0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_USB0_STAT: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_M4_EMC_CFG -------------------------------------- -#define CCU1_CLK_M4_EMC_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_EMC_CFG: RUN Position */ -#define CCU1_CLK_M4_EMC_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_EMC_CFG_RUN_Pos) /*!< CCU1 CLK_M4_EMC_CFG: RUN Mask */ -#define CCU1_CLK_M4_EMC_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_EMC_CFG: AUTO Position */ -#define CCU1_CLK_M4_EMC_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_EMC_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_EMC_CFG: AUTO Mask */ -#define CCU1_CLK_M4_EMC_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_EMC_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_EMC_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_EMC_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_EMC_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_EMC_STAT -------------------------------------- -#define CCU1_CLK_M4_EMC_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_EMC_STAT: RUN Position */ -#define CCU1_CLK_M4_EMC_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_EMC_STAT_RUN_Pos) /*!< CCU1 CLK_M4_EMC_STAT: RUN Mask */ -#define CCU1_CLK_M4_EMC_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_EMC_STAT: AUTO Position */ -#define CCU1_CLK_M4_EMC_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_EMC_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_EMC_STAT: AUTO Mask */ -#define CCU1_CLK_M4_EMC_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_EMC_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_EMC_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_EMC_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_EMC_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_SDIO_CFG -------------------------------------- -#define CCU1_CLK_M4_SDIO_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SDIO_CFG: RUN Position */ -#define CCU1_CLK_M4_SDIO_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SDIO_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SDIO_CFG: RUN Mask */ -#define CCU1_CLK_M4_SDIO_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SDIO_CFG: AUTO Position */ -#define CCU1_CLK_M4_SDIO_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SDIO_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SDIO_CFG: AUTO Mask */ -#define CCU1_CLK_M4_SDIO_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SDIO_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_SDIO_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SDIO_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SDIO_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_SDIO_STAT ------------------------------------- -#define CCU1_CLK_M4_SDIO_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SDIO_STAT: RUN Position */ -#define CCU1_CLK_M4_SDIO_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SDIO_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SDIO_STAT: RUN Mask */ -#define CCU1_CLK_M4_SDIO_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SDIO_STAT: AUTO Position */ -#define CCU1_CLK_M4_SDIO_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SDIO_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SDIO_STAT: AUTO Mask */ -#define CCU1_CLK_M4_SDIO_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SDIO_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_SDIO_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SDIO_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SDIO_STAT: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_M4_DMA_CFG -------------------------------------- -#define CCU1_CLK_M4_DMA_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_DMA_CFG: RUN Position */ -#define CCU1_CLK_M4_DMA_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_DMA_CFG_RUN_Pos) /*!< CCU1 CLK_M4_DMA_CFG: RUN Mask */ -#define CCU1_CLK_M4_DMA_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_DMA_CFG: AUTO Position */ -#define CCU1_CLK_M4_DMA_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_DMA_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_DMA_CFG: AUTO Mask */ -#define CCU1_CLK_M4_DMA_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_DMA_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_DMA_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_DMA_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_DMA_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_DMA_STAT -------------------------------------- -#define CCU1_CLK_M4_DMA_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_DMA_STAT: RUN Position */ -#define CCU1_CLK_M4_DMA_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_DMA_STAT_RUN_Pos) /*!< CCU1 CLK_M4_DMA_STAT: RUN Mask */ -#define CCU1_CLK_M4_DMA_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_DMA_STAT: AUTO Position */ -#define CCU1_CLK_M4_DMA_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_DMA_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_DMA_STAT: AUTO Mask */ -#define CCU1_CLK_M4_DMA_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_DMA_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_DMA_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_DMA_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_DMA_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_M4CORE_CFG ------------------------------------- -#define CCU1_CLK_M4_M4CORE_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_M4CORE_CFG: RUN Position */ -#define CCU1_CLK_M4_M4CORE_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_M4CORE_CFG_RUN_Pos) /*!< CCU1 CLK_M4_M4CORE_CFG: RUN Mask */ -#define CCU1_CLK_M4_M4CORE_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_M4CORE_CFG: AUTO Position */ -#define CCU1_CLK_M4_M4CORE_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_M4CORE_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_M4CORE_CFG: AUTO Mask */ -#define CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_M4CORE_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_M4CORE_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_M3CORE_STAT ------------------------------------ -#define CCU1_CLK_M4_M3CORE_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_M3CORE_STAT: RUN Position */ -#define CCU1_CLK_M4_M3CORE_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_M3CORE_STAT_RUN_Pos) /*!< CCU1 CLK_M4_M3CORE_STAT: RUN Mask */ -#define CCU1_CLK_M4_M3CORE_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_M3CORE_STAT: AUTO Position */ -#define CCU1_CLK_M4_M3CORE_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_M3CORE_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_M3CORE_STAT: AUTO Mask */ -#define CCU1_CLK_M4_M3CORE_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_M3CORE_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_M3CORE_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_M3CORE_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_M3CORE_STAT: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_M4_SCT_CFG -------------------------------------- -#define CCU1_CLK_M4_SCT_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SCT_CFG: RUN Position */ -#define CCU1_CLK_M4_SCT_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SCT_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SCT_CFG: RUN Mask */ -#define CCU1_CLK_M4_SCT_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SCT_CFG: AUTO Position */ -#define CCU1_CLK_M4_SCT_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SCT_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SCT_CFG: AUTO Mask */ -#define CCU1_CLK_M4_SCT_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SCT_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_SCT_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SCT_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SCT_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_SCT_STAT -------------------------------------- -#define CCU1_CLK_M4_SCT_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SCT_STAT: RUN Position */ -#define CCU1_CLK_M4_SCT_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SCT_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SCT_STAT: RUN Mask */ -#define CCU1_CLK_M4_SCT_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SCT_STAT: AUTO Position */ -#define CCU1_CLK_M4_SCT_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SCT_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SCT_STAT: AUTO Mask */ -#define CCU1_CLK_M4_SCT_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SCT_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_SCT_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SCT_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SCT_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_USB1_CFG -------------------------------------- -#define CCU1_CLK_M4_USB1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_USB1_CFG: RUN Position */ -#define CCU1_CLK_M4_USB1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_USB1_CFG_RUN_Pos) /*!< CCU1 CLK_M4_USB1_CFG: RUN Mask */ -#define CCU1_CLK_M4_USB1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_USB1_CFG: AUTO Position */ -#define CCU1_CLK_M4_USB1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_USB1_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_USB1_CFG: AUTO Mask */ -#define CCU1_CLK_M4_USB1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USB1_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_USB1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USB1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_USB1_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_USB1_STAT ------------------------------------- -#define CCU1_CLK_M4_USB1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_USB1_STAT: RUN Position */ -#define CCU1_CLK_M4_USB1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_USB1_STAT_RUN_Pos) /*!< CCU1 CLK_M4_USB1_STAT: RUN Mask */ -#define CCU1_CLK_M4_USB1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_USB1_STAT: AUTO Position */ -#define CCU1_CLK_M4_USB1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_USB1_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_USB1_STAT: AUTO Mask */ -#define CCU1_CLK_M4_USB1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USB1_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_USB1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USB1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_USB1_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_EMCDIV_CFG ------------------------------------- -#define CCU1_CLK_M4_EMCDIV_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_EMCDIV_CFG: RUN Position */ -#define CCU1_CLK_M4_EMCDIV_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_RUN_Pos) /*!< CCU1 CLK_M4_EMCDIV_CFG: RUN Mask */ -#define CCU1_CLK_M4_EMCDIV_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_EMCDIV_CFG: AUTO Position */ -#define CCU1_CLK_M4_EMCDIV_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_EMCDIV_CFG: AUTO Mask */ -#define CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_EMCDIV_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_EMCDIV_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_EMCDIV_STAT ------------------------------------ -#define CCU1_CLK_M4_EMCDIV_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_EMCDIV_STAT: RUN Position */ -#define CCU1_CLK_M4_EMCDIV_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_RUN_Pos) /*!< CCU1 CLK_M4_EMCDIV_STAT: RUN Mask */ -#define CCU1_CLK_M4_EMCDIV_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_EMCDIV_STAT: AUTO Position */ -#define CCU1_CLK_M4_EMCDIV_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_EMCDIV_STAT: AUTO Mask */ -#define CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_EMCDIV_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_EMCDIV_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_M0APP_CFG ------------------------------------- -#define CCU1_CLK_M4_M0APP_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_M0APP_CFG: RUN Position */ -#define CCU1_CLK_M4_M0APP_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_M0APP_CFG_RUN_Pos) /*!< CCU1 CLK_M4_M0APP_CFG: RUN Mask */ -#define CCU1_CLK_M4_M0APP_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_M0APP_CFG: AUTO Position */ -#define CCU1_CLK_M4_M0APP_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_M0APP_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_M0APP_CFG: AUTO Mask */ -#define CCU1_CLK_M4_M0APP_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_M0APP_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_M0APP_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_M0APP_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_M0APP_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_M0APP_STAT ------------------------------------- -#define CCU1_CLK_M4_M0APP_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_M0APP_STAT: RUN Position */ -#define CCU1_CLK_M4_M0APP_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_M0APP_STAT_RUN_Pos) /*!< CCU1 CLK_M4_M0APP_STAT: RUN Mask */ -#define CCU1_CLK_M4_M0APP_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_M0APP_STAT: AUTO Position */ -#define CCU1_CLK_M4_M0APP_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_M0APP_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_M0APP_STAT: AUTO Mask */ -#define CCU1_CLK_M4_M0APP_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_M0APP_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_M0APP_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_M0APP_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_M0APP_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_WWDT_CFG -------------------------------------- -#define CCU1_CLK_M4_WWDT_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_WWDT_CFG: RUN Position */ -#define CCU1_CLK_M4_WWDT_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_WWDT_CFG_RUN_Pos) /*!< CCU1 CLK_M4_WWDT_CFG: RUN Mask */ -#define CCU1_CLK_M4_WWDT_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_WWDT_CFG: AUTO Position */ -#define CCU1_CLK_M4_WWDT_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_WWDT_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_WWDT_CFG: AUTO Mask */ -#define CCU1_CLK_M4_WWDT_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_WWDT_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_WWDT_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_WWDT_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_WWDT_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_WWDT_STAT ------------------------------------- -#define CCU1_CLK_M4_WWDT_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_WWDT_STAT: RUN Position */ -#define CCU1_CLK_M4_WWDT_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_WWDT_STAT_RUN_Pos) /*!< CCU1 CLK_M4_WWDT_STAT: RUN Mask */ -#define CCU1_CLK_M4_WWDT_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_WWDT_STAT: AUTO Position */ -#define CCU1_CLK_M4_WWDT_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_WWDT_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_WWDT_STAT: AUTO Mask */ -#define CCU1_CLK_M4_WWDT_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_WWDT_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_WWDT_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_WWDT_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_WWDT_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_USART0_CFG ------------------------------------- -#define CCU1_CLK_M4_USART0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_USART0_CFG: RUN Position */ -#define CCU1_CLK_M4_USART0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_USART0_CFG_RUN_Pos) /*!< CCU1 CLK_M4_USART0_CFG: RUN Mask */ -#define CCU1_CLK_M4_USART0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART0_CFG: AUTO Position */ -#define CCU1_CLK_M4_USART0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART0_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_USART0_CFG: AUTO Mask */ -#define CCU1_CLK_M4_USART0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART0_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_USART0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART0_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_USART0_STAT ------------------------------------ -#define CCU1_CLK_M4_USART0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_USART0_STAT: RUN Position */ -#define CCU1_CLK_M4_USART0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_USART0_STAT_RUN_Pos) /*!< CCU1 CLK_M4_USART0_STAT: RUN Mask */ -#define CCU1_CLK_M4_USART0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART0_STAT: AUTO Position */ -#define CCU1_CLK_M4_USART0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART0_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_USART0_STAT: AUTO Mask */ -#define CCU1_CLK_M4_USART0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART0_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_USART0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART0_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_UART1_CFG ------------------------------------- -#define CCU1_CLK_M4_UART1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_UART1_CFG: RUN Position */ -#define CCU1_CLK_M4_UART1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_UART1_CFG_RUN_Pos) /*!< CCU1 CLK_M4_UART1_CFG: RUN Mask */ -#define CCU1_CLK_M4_UART1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_UART1_CFG: AUTO Position */ -#define CCU1_CLK_M4_UART1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_UART1_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_UART1_CFG: AUTO Mask */ -#define CCU1_CLK_M4_UART1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_UART1_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_UART1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_UART1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_UART1_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_UART1_STAT ------------------------------------- -#define CCU1_CLK_M4_UART1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_UART1_STAT: RUN Position */ -#define CCU1_CLK_M4_UART1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_UART1_STAT_RUN_Pos) /*!< CCU1 CLK_M4_UART1_STAT: RUN Mask */ -#define CCU1_CLK_M4_UART1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_UART1_STAT: AUTO Position */ -#define CCU1_CLK_M4_UART1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_UART1_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_UART1_STAT: AUTO Mask */ -#define CCU1_CLK_M4_UART1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_UART1_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_UART1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_UART1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_UART1_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_SSP0_CFG -------------------------------------- -#define CCU1_CLK_M4_SSP0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SSP0_CFG: RUN Position */ -#define CCU1_CLK_M4_SSP0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SSP0_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SSP0_CFG: RUN Mask */ -#define CCU1_CLK_M4_SSP0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SSP0_CFG: AUTO Position */ -#define CCU1_CLK_M4_SSP0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SSP0_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SSP0_CFG: AUTO Mask */ -#define CCU1_CLK_M4_SSP0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SSP0_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_SSP0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SSP0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SSP0_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_SSP0_STAT ------------------------------------- -#define CCU1_CLK_M4_SSP0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SSP0_STAT: RUN Position */ -#define CCU1_CLK_M4_SSP0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SSP0_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SSP0_STAT: RUN Mask */ -#define CCU1_CLK_M4_SSP0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SSP0_STAT: AUTO Position */ -#define CCU1_CLK_M4_SSP0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SSP0_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SSP0_STAT: AUTO Mask */ -#define CCU1_CLK_M4_SSP0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SSP0_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_SSP0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SSP0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SSP0_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_TIMER0_CFG ------------------------------------- -#define CCU1_CLK_M4_TIMER0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER0_CFG: RUN Position */ -#define CCU1_CLK_M4_TIMER0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER0_CFG_RUN_Pos) /*!< CCU1 CLK_M4_TIMER0_CFG: RUN Mask */ -#define CCU1_CLK_M4_TIMER0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER0_CFG: AUTO Position */ -#define CCU1_CLK_M4_TIMER0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER0_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER0_CFG: AUTO Mask */ -#define CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER0_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER0_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_TIMER0_STAT ------------------------------------ -#define CCU1_CLK_M4_TIMER0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER0_STAT: RUN Position */ -#define CCU1_CLK_M4_TIMER0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER0_STAT_RUN_Pos) /*!< CCU1 CLK_M4_TIMER0_STAT: RUN Mask */ -#define CCU1_CLK_M4_TIMER0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER0_STAT: AUTO Position */ -#define CCU1_CLK_M4_TIMER0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER0_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER0_STAT: AUTO Mask */ -#define CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER0_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER0_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_TIMER1_CFG ------------------------------------- -#define CCU1_CLK_M4_TIMER1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER1_CFG: RUN Position */ -#define CCU1_CLK_M4_TIMER1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER1_CFG_RUN_Pos) /*!< CCU1 CLK_M4_TIMER1_CFG: RUN Mask */ -#define CCU1_CLK_M4_TIMER1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER1_CFG: AUTO Position */ -#define CCU1_CLK_M4_TIMER1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER1_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER1_CFG: AUTO Mask */ -#define CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER1_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER1_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_TIMER1_STAT ------------------------------------ -#define CCU1_CLK_M4_TIMER1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER1_STAT: RUN Position */ -#define CCU1_CLK_M4_TIMER1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER1_STAT_RUN_Pos) /*!< CCU1 CLK_M4_TIMER1_STAT: RUN Mask */ -#define CCU1_CLK_M4_TIMER1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER1_STAT: AUTO Position */ -#define CCU1_CLK_M4_TIMER1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER1_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER1_STAT: AUTO Mask */ -#define CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER1_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER1_STAT: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_M4_SCU_CFG -------------------------------------- -#define CCU1_CLK_M4_SCU_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SCU_CFG: RUN Position */ -#define CCU1_CLK_M4_SCU_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SCU_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SCU_CFG: RUN Mask */ -#define CCU1_CLK_M4_SCU_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SCU_CFG: AUTO Position */ -#define CCU1_CLK_M4_SCU_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SCU_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SCU_CFG: AUTO Mask */ -#define CCU1_CLK_M4_SCU_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SCU_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_SCU_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SCU_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SCU_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_SCU_STAT -------------------------------------- -#define CCU1_CLK_M4_SCU_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SCU_STAT: RUN Position */ -#define CCU1_CLK_M4_SCU_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SCU_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SCU_STAT: RUN Mask */ -#define CCU1_CLK_M4_SCU_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SCU_STAT: AUTO Position */ -#define CCU1_CLK_M4_SCU_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SCU_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SCU_STAT: AUTO Mask */ -#define CCU1_CLK_M4_SCU_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SCU_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_SCU_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SCU_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SCU_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_CREG_CFG -------------------------------------- -#define CCU1_CLK_M4_CREG_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_CREG_CFG: RUN Position */ -#define CCU1_CLK_M4_CREG_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_CREG_CFG_RUN_Pos) /*!< CCU1 CLK_M4_CREG_CFG: RUN Mask */ -#define CCU1_CLK_M4_CREG_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_CREG_CFG: AUTO Position */ -#define CCU1_CLK_M4_CREG_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_CREG_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_CREG_CFG: AUTO Mask */ -#define CCU1_CLK_M4_CREG_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_CREG_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_CREG_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_CREG_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_CREG_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_CREG_STAT ------------------------------------- -#define CCU1_CLK_M4_CREG_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_CREG_STAT: RUN Position */ -#define CCU1_CLK_M4_CREG_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_CREG_STAT_RUN_Pos) /*!< CCU1 CLK_M4_CREG_STAT: RUN Mask */ -#define CCU1_CLK_M4_CREG_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_CREG_STAT: AUTO Position */ -#define CCU1_CLK_M4_CREG_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_CREG_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_CREG_STAT: AUTO Mask */ -#define CCU1_CLK_M4_CREG_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_CREG_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_CREG_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_CREG_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_CREG_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_RITIMER_CFG ------------------------------------ -#define CCU1_CLK_M4_RITIMER_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_RITIMER_CFG: RUN Position */ -#define CCU1_CLK_M4_RITIMER_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_RITIMER_CFG_RUN_Pos) /*!< CCU1 CLK_M4_RITIMER_CFG: RUN Mask */ -#define CCU1_CLK_M4_RITIMER_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_RITIMER_CFG: AUTO Position */ -#define CCU1_CLK_M4_RITIMER_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_RITIMER_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_RITIMER_CFG: AUTO Mask */ -#define CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_RITIMER_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_RITIMER_CFG: WAKEUP Mask */ - -// -------------------------------- CCU1_CLK_M4_RITIMER_STAT ------------------------------------ -#define CCU1_CLK_M4_RITIMER_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_RITIMER_STAT: RUN Position */ -#define CCU1_CLK_M4_RITIMER_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_RITIMER_STAT_RUN_Pos) /*!< CCU1 CLK_M4_RITIMER_STAT: RUN Mask */ -#define CCU1_CLK_M4_RITIMER_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_RITIMER_STAT: AUTO Position */ -#define CCU1_CLK_M4_RITIMER_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_RITIMER_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_RITIMER_STAT: AUTO Mask */ -#define CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_RITIMER_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_RITIMER_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_USART2_CFG ------------------------------------- -#define CCU1_CLK_M4_USART2_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_USART2_CFG: RUN Position */ -#define CCU1_CLK_M4_USART2_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_USART2_CFG_RUN_Pos) /*!< CCU1 CLK_M4_USART2_CFG: RUN Mask */ -#define CCU1_CLK_M4_USART2_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART2_CFG: AUTO Position */ -#define CCU1_CLK_M4_USART2_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART2_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_USART2_CFG: AUTO Mask */ -#define CCU1_CLK_M4_USART2_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART2_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_USART2_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART2_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART2_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_USART2_STAT ------------------------------------ -#define CCU1_CLK_M4_USART2_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_USART2_STAT: RUN Position */ -#define CCU1_CLK_M4_USART2_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_USART2_STAT_RUN_Pos) /*!< CCU1 CLK_M4_USART2_STAT: RUN Mask */ -#define CCU1_CLK_M4_USART2_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART2_STAT: AUTO Position */ -#define CCU1_CLK_M4_USART2_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART2_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_USART2_STAT: AUTO Mask */ -#define CCU1_CLK_M4_USART2_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART2_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_USART2_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART2_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART2_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_USART3_CFG ------------------------------------- -#define CCU1_CLK_M4_USART3_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_USART3_CFG: RUN Position */ -#define CCU1_CLK_M4_USART3_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_USART3_CFG_RUN_Pos) /*!< CCU1 CLK_M4_USART3_CFG: RUN Mask */ -#define CCU1_CLK_M4_USART3_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART3_CFG: AUTO Position */ -#define CCU1_CLK_M4_USART3_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART3_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_USART3_CFG: AUTO Mask */ -#define CCU1_CLK_M4_USART3_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART3_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_USART3_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART3_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART3_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_USART3_STAT ------------------------------------ -#define CCU1_CLK_M4_USART3_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_USART3_STAT: RUN Position */ -#define CCU1_CLK_M4_USART3_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_USART3_STAT_RUN_Pos) /*!< CCU1 CLK_M4_USART3_STAT: RUN Mask */ -#define CCU1_CLK_M4_USART3_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART3_STAT: AUTO Position */ -#define CCU1_CLK_M4_USART3_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART3_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_USART3_STAT: AUTO Mask */ -#define CCU1_CLK_M4_USART3_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART3_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_USART3_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART3_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART3_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_TIMER2_CFG ------------------------------------- -#define CCU1_CLK_M4_TIMER2_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER2_CFG: RUN Position */ -#define CCU1_CLK_M4_TIMER2_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER2_CFG_RUN_Pos) /*!< CCU1 CLK_M4_TIMER2_CFG: RUN Mask */ -#define CCU1_CLK_M4_TIMER2_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER2_CFG: AUTO Position */ -#define CCU1_CLK_M4_TIMER2_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER2_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER2_CFG: AUTO Mask */ -#define CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER2_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER2_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_TIMER2_STAT ------------------------------------ -#define CCU1_CLK_M4_TIMER2_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER2_STAT: RUN Position */ -#define CCU1_CLK_M4_TIMER2_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER2_STAT_RUN_Pos) /*!< CCU1 CLK_M4_TIMER2_STAT: RUN Mask */ -#define CCU1_CLK_M4_TIMER2_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER2_STAT: AUTO Position */ -#define CCU1_CLK_M4_TIMER2_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER2_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER2_STAT: AUTO Mask */ -#define CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER2_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER2_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_TIMER3_CFG ------------------------------------- -#define CCU1_CLK_M4_TIMER3_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER3_CFG: RUN Position */ -#define CCU1_CLK_M4_TIMER3_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER3_CFG_RUN_Pos) /*!< CCU1 CLK_M4_TIMER3_CFG: RUN Mask */ -#define CCU1_CLK_M4_TIMER3_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER3_CFG: AUTO Position */ -#define CCU1_CLK_M4_TIMER3_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER3_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER3_CFG: AUTO Mask */ -#define CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER3_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER3_CFG: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_M4_TIMER3_STAT ------------------------------------ -#define CCU1_CLK_M4_TIMER3_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER3_STAT: RUN Position */ -#define CCU1_CLK_M4_TIMER3_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER3_STAT_RUN_Pos) /*!< CCU1 CLK_M4_TIMER3_STAT: RUN Mask */ -#define CCU1_CLK_M4_TIMER3_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER3_STAT: AUTO Position */ -#define CCU1_CLK_M4_TIMER3_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER3_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER3_STAT: AUTO Mask */ -#define CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER3_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER3_STAT: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_SSP1_CFG -------------------------------------- -#define CCU1_CLK_M4_SSP1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SSP1_CFG: RUN Position */ -#define CCU1_CLK_M4_SSP1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SSP1_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SSP1_CFG: RUN Mask */ -#define CCU1_CLK_M4_SSP1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SSP1_CFG: AUTO Position */ -#define CCU1_CLK_M4_SSP1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SSP1_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SSP1_CFG: AUTO Mask */ -#define CCU1_CLK_M4_SSP1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SSP1_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_SSP1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SSP1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SSP1_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_SSP1_STAT ------------------------------------- -#define CCU1_CLK_M4_SSP1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SSP1_STAT: RUN Position */ -#define CCU1_CLK_M4_SSP1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SSP1_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SSP1_STAT: RUN Mask */ -#define CCU1_CLK_M4_SSP1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SSP1_STAT: AUTO Position */ -#define CCU1_CLK_M4_SSP1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SSP1_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SSP1_STAT: AUTO Mask */ -#define CCU1_CLK_M4_SSP1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SSP1_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_SSP1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SSP1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SSP1_STAT: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_M4_QEI_CFG -------------------------------------- -#define CCU1_CLK_M4_QEI_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_QEI_CFG: RUN Position */ -#define CCU1_CLK_M4_QEI_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_QEI_CFG_RUN_Pos) /*!< CCU1 CLK_M4_QEI_CFG: RUN Mask */ -#define CCU1_CLK_M4_QEI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_QEI_CFG: AUTO Position */ -#define CCU1_CLK_M4_QEI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_QEI_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_QEI_CFG: AUTO Mask */ -#define CCU1_CLK_M4_QEI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_QEI_CFG: WAKEUP Position */ -#define CCU1_CLK_M4_QEI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_QEI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_QEI_CFG: WAKEUP Mask */ - -// ---------------------------------- CCU1_CLK_M4_QEI_STAT -------------------------------------- -#define CCU1_CLK_M4_QEI_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_QEI_STAT: RUN Position */ -#define CCU1_CLK_M4_QEI_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_QEI_STAT_RUN_Pos) /*!< CCU1 CLK_M4_QEI_STAT: RUN Mask */ -#define CCU1_CLK_M4_QEI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_QEI_STAT: AUTO Position */ -#define CCU1_CLK_M4_QEI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_QEI_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_QEI_STAT: AUTO Mask */ -#define CCU1_CLK_M4_QEI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_QEI_STAT: WAKEUP Position */ -#define CCU1_CLK_M4_QEI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_QEI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_QEI_STAT: WAKEUP Mask */ - -// --------------------------------- CCU1_CLK_PERIPH_BUS_CFG ------------------------------------ -#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Position */ -#define CCU1_CLK_PERIPH_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Mask */ -#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Position */ -#define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Mask */ -#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Position */ -#define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Mask */ - -// -------------------------------- CCU1_CLK_PERIPH_BUS_STAT ------------------------------------ -#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Position */ -#define CCU1_CLK_PERIPH_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Mask */ -#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Position */ -#define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Mask */ -#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Position */ -#define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Mask */ - -// -------------------------------- CCU1_CLK_PERIPH_CORE_CFG ------------------------------------ -#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Position */ -#define CCU1_CLK_PERIPH_CORE_CFG_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos) /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Mask */ -#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Position */ -#define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos) /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Mask */ -#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Position */ -#define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Mask */ - -// -------------------------------- CCU1_CLK_PERIPH_CORE_STAT ----------------------------------- -#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Position */ -#define CCU1_CLK_PERIPH_CORE_STAT_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos) /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Mask */ -#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Position */ -#define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos) /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Mask */ -#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Position */ -#define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Mask */ - -// -------------------------------- CCU1_CLK_PERIPH_SGPIO_CFG ----------------------------------- -#define CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_SGPIO_CFG: RUN Position */ -#define CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_CFG: RUN Mask */ -#define CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_SGPIO_CFG: AUTO Position */ -#define CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_CFG: AUTO Mask */ -#define CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_SGPIO_CFG: WAKEUP Position */ -#define CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_CFG: WAKEUP Mask */ - -// ------------------------------- CCU1_CLK_PERIPH_SGPIO_STAT ----------------------------------- -#define CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_SGPIO_STAT: RUN Position */ -#define CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_STAT: RUN Mask */ -#define CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_SGPIO_STAT: AUTO Position */ -#define CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_STAT: AUTO Mask */ -#define CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_SGPIO_STAT: WAKEUP Position */ -#define CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_STAT: WAKEUP Mask */ - -// ------------------------------------ CCU1_CLK_USB0_CFG --------------------------------------- -#define CCU1_CLK_USB0_CFG_RUN_Pos 0 /*!< CCU1 CLK_USB0_CFG: RUN Position */ -#define CCU1_CLK_USB0_CFG_RUN_Msk (0x01UL << CCU1_CLK_USB0_CFG_RUN_Pos) /*!< CCU1 CLK_USB0_CFG: RUN Mask */ -#define CCU1_CLK_USB0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_USB0_CFG: AUTO Position */ -#define CCU1_CLK_USB0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_USB0_CFG_AUTO_Pos) /*!< CCU1 CLK_USB0_CFG: AUTO Mask */ -#define CCU1_CLK_USB0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_USB0_CFG: WAKEUP Position */ -#define CCU1_CLK_USB0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_USB0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_USB0_CFG: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_USB0_STAT --------------------------------------- -#define CCU1_CLK_USB0_STAT_RUN_Pos 0 /*!< CCU1 CLK_USB0_STAT: RUN Position */ -#define CCU1_CLK_USB0_STAT_RUN_Msk (0x01UL << CCU1_CLK_USB0_STAT_RUN_Pos) /*!< CCU1 CLK_USB0_STAT: RUN Mask */ -#define CCU1_CLK_USB0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_USB0_STAT: AUTO Position */ -#define CCU1_CLK_USB0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_USB0_STAT_AUTO_Pos) /*!< CCU1 CLK_USB0_STAT: AUTO Mask */ -#define CCU1_CLK_USB0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_USB0_STAT: WAKEUP Position */ -#define CCU1_CLK_USB0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_USB0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_USB0_STAT: WAKEUP Mask */ - -// ------------------------------------ CCU1_CLK_USB1_CFG --------------------------------------- -#define CCU1_CLK_USB1_CFG_RUN_Pos 0 /*!< CCU1 CLK_USB1_CFG: RUN Position */ -#define CCU1_CLK_USB1_CFG_RUN_Msk (0x01UL << CCU1_CLK_USB1_CFG_RUN_Pos) /*!< CCU1 CLK_USB1_CFG: RUN Mask */ -#define CCU1_CLK_USB1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_USB1_CFG: AUTO Position */ -#define CCU1_CLK_USB1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_USB1_CFG_AUTO_Pos) /*!< CCU1 CLK_USB1_CFG: AUTO Mask */ -#define CCU1_CLK_USB1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_USB1_CFG: WAKEUP Position */ -#define CCU1_CLK_USB1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_USB1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_USB1_CFG: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_USB1_STAT --------------------------------------- -#define CCU1_CLK_USB1_STAT_RUN_Pos 0 /*!< CCU1 CLK_USB1_STAT: RUN Position */ -#define CCU1_CLK_USB1_STAT_RUN_Msk (0x01UL << CCU1_CLK_USB1_STAT_RUN_Pos) /*!< CCU1 CLK_USB1_STAT: RUN Mask */ -#define CCU1_CLK_USB1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_USB1_STAT: AUTO Position */ -#define CCU1_CLK_USB1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_USB1_STAT_AUTO_Pos) /*!< CCU1 CLK_USB1_STAT: AUTO Mask */ -#define CCU1_CLK_USB1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_USB1_STAT: WAKEUP Position */ -#define CCU1_CLK_USB1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_USB1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_USB1_STAT: WAKEUP Mask */ - -// ------------------------------------ CCU1_CLK_SPI_CFG ---------------------------------------- -#define CCU1_CLK_SPI_CFG_RUN_Pos 0 /*!< CCU1 CLK_SPI_CFG: RUN Position */ -#define CCU1_CLK_SPI_CFG_RUN_Msk (0x01UL << CCU1_CLK_SPI_CFG_RUN_Pos) /*!< CCU1 CLK_SPI_CFG: RUN Mask */ -#define CCU1_CLK_SPI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_SPI_CFG: AUTO Position */ -#define CCU1_CLK_SPI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_SPI_CFG_AUTO_Pos) /*!< CCU1 CLK_SPI_CFG: AUTO Mask */ -#define CCU1_CLK_SPI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_SPI_CFG: WAKEUP Position */ -#define CCU1_CLK_SPI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_SPI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_SPI_CFG: WAKEUP Mask */ - -// ------------------------------------ CCU1_CLK_SPI_STAT --------------------------------------- -#define CCU1_CLK_SPI_STAT_RUN_Pos 0 /*!< CCU1 CLK_SPI_STAT: RUN Position */ -#define CCU1_CLK_SPI_STAT_RUN_Msk (0x01UL << CCU1_CLK_SPI_STAT_RUN_Pos) /*!< CCU1 CLK_SPI_STAT: RUN Mask */ -#define CCU1_CLK_SPI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_SPI_STAT: AUTO Position */ -#define CCU1_CLK_SPI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_SPI_STAT_AUTO_Pos) /*!< CCU1 CLK_SPI_STAT: AUTO Mask */ -#define CCU1_CLK_SPI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_SPI_STAT: WAKEUP Position */ -#define CCU1_CLK_SPI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_SPI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_SPI_STAT: WAKEUP Mask */ - -// ------------------------------------ CCU1_CLK_VADC_CFG --------------------------------------- -#define CCU1_CLK_VADC_CFG_RUN_Pos 0 /*!< CCU1 CLK_VADC_CFG: RUN Position */ -#define CCU1_CLK_VADC_CFG_RUN_Msk (0x01UL << CCU1_CLK_VADC_CFG_RUN_Pos) /*!< CCU1 CLK_VADC_CFG: RUN Mask */ -#define CCU1_CLK_VADC_CFG_AUTO_Pos 1 /*!< CCU1 CLK_VADC_CFG: AUTO Position */ -#define CCU1_CLK_VADC_CFG_AUTO_Msk (0x01UL << CCU1_CLK_VADC_CFG_AUTO_Pos) /*!< CCU1 CLK_VADC_CFG: AUTO Mask */ -#define CCU1_CLK_VADC_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_VADC_CFG: WAKEUP Position */ -#define CCU1_CLK_VADC_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_VADC_CFG_WAKEUP_Pos) /*!< CCU1 CLK_VADC_CFG: WAKEUP Mask */ - -// ----------------------------------- CCU1_CLK_VADC_STAT --------------------------------------- -#define CCU1_CLK_VADC_STAT_RUN_Pos 0 /*!< CCU1 CLK_VADC_STAT: RUN Position */ -#define CCU1_CLK_VADC_STAT_RUN_Msk (0x01UL << CCU1_CLK_VADC_STAT_RUN_Pos) /*!< CCU1 CLK_VADC_STAT: RUN Mask */ -#define CCU1_CLK_VADC_STAT_AUTO_Pos 1 /*!< CCU1 CLK_VADC_STAT: AUTO Position */ -#define CCU1_CLK_VADC_STAT_AUTO_Msk (0x01UL << CCU1_CLK_VADC_STAT_AUTO_Pos) /*!< CCU1 CLK_VADC_STAT: AUTO Mask */ -#define CCU1_CLK_VADC_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_VADC_STAT: WAKEUP Position */ -#define CCU1_CLK_VADC_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_VADC_STAT_WAKEUP_Pos) /*!< CCU1 CLK_VADC_STAT: WAKEUP Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- CCU2 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ----------------------------------------- CCU2_PM -------------------------------------------- -#define CCU2_PM_PD_Pos 0 /*!< CCU2 PM: PD Position */ -#define CCU2_PM_PD_Msk (0x01UL << CCU2_PM_PD_Pos) /*!< CCU2 PM: PD Mask */ - -// ------------------------------------- CCU2_BASE_STAT ----------------------------------------- -#define CCU2_BASE_STAT_BASE_UART3_CLK_Pos 1 /*!< CCU2 BASE_STAT: BASE_UART3_CLK Position */ -#define CCU2_BASE_STAT_BASE_UART3_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART3_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART3_CLK Mask */ -#define CCU2_BASE_STAT_BASE_UART2_CLK_Pos 2 /*!< CCU2 BASE_STAT: BASE_UART2_CLK Position */ -#define CCU2_BASE_STAT_BASE_UART2_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART2_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART2_CLK Mask */ -#define CCU2_BASE_STAT_BASE_UART1_CLK_Pos 3 /*!< CCU2 BASE_STAT: BASE_UART1_CLK Position */ -#define CCU2_BASE_STAT_BASE_UART1_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART1_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART1_CLK Mask */ -#define CCU2_BASE_STAT_BASE_UART0_CLK_Pos 4 /*!< CCU2 BASE_STAT: BASE_UART0_CLK Position */ -#define CCU2_BASE_STAT_BASE_UART0_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART0_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART0_CLK Mask */ -#define CCU2_BASE_STAT_BASE_SSP1_CLK_Pos 5 /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Position */ -#define CCU2_BASE_STAT_BASE_SSP1_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_SSP1_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Mask */ -#define CCU2_BASE_STAT_BASE_SSP0_CLK_Pos 6 /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Position */ -#define CCU2_BASE_STAT_BASE_SSP0_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_SSP0_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Mask */ - -// ------------------------------------ CCU2_CLK_APLL_CFG --------------------------------------- -#define CCU2_CLK_APLL_CFG_RUN_Pos 0 /*!< CCU2 CLK_APLL_CFG: RUN Position */ -#define CCU2_CLK_APLL_CFG_RUN_Msk (0x01UL << CCU2_CLK_APLL_CFG_RUN_Pos) /*!< CCU2 CLK_APLL_CFG: RUN Mask */ -#define CCU2_CLK_APLL_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APLL_CFG: AUTO Position */ -#define CCU2_CLK_APLL_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APLL_CFG_AUTO_Pos) /*!< CCU2 CLK_APLL_CFG: AUTO Mask */ -#define CCU2_CLK_APLL_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APLL_CFG: WAKEUP Position */ -#define CCU2_CLK_APLL_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APLL_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APLL_CFG: WAKEUP Mask */ - -// ----------------------------------- CCU2_CLK_APLL_STAT --------------------------------------- -#define CCU2_CLK_APLL_STAT_RUN_Pos 0 /*!< CCU2 CLK_APLL_STAT: RUN Position */ -#define CCU2_CLK_APLL_STAT_RUN_Msk (0x01UL << CCU2_CLK_APLL_STAT_RUN_Pos) /*!< CCU2 CLK_APLL_STAT: RUN Mask */ -#define CCU2_CLK_APLL_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APLL_STAT: AUTO Position */ -#define CCU2_CLK_APLL_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APLL_STAT_AUTO_Pos) /*!< CCU2 CLK_APLL_STAT: AUTO Mask */ -#define CCU2_CLK_APLL_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APLL_STAT: WAKEUP Position */ -#define CCU2_CLK_APLL_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APLL_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APLL_STAT: WAKEUP Mask */ - -// -------------------------------- CCU2_CLK_APB2_USART3_CFG ------------------------------------ -#define CCU2_CLK_APB2_USART3_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART3_CFG: RUN Position */ -#define CCU2_CLK_APB2_USART3_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART3_CFG_RUN_Pos) /*!< CCU2 CLK_APB2_USART3_CFG: RUN Mask */ -#define CCU2_CLK_APB2_USART3_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Position */ -#define CCU2_CLK_APB2_USART3_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART3_CFG_AUTO_Pos) /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Mask */ -#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Position */ -#define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Mask */ - -// -------------------------------- CCU2_CLK_APB2_USART3_STAT ----------------------------------- -#define CCU2_CLK_APB2_USART3_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART3_STAT: RUN Position */ -#define CCU2_CLK_APB2_USART3_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART3_STAT_RUN_Pos) /*!< CCU2 CLK_APB2_USART3_STAT: RUN Mask */ -#define CCU2_CLK_APB2_USART3_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Position */ -#define CCU2_CLK_APB2_USART3_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART3_STAT_AUTO_Pos) /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Mask */ -#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Position */ -#define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Mask */ - -// -------------------------------- CCU2_CLK_APB2_USART2_CFG ------------------------------------ -#define CCU2_CLK_APB2_USART2_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART2_CFG: RUN Position */ -#define CCU2_CLK_APB2_USART2_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART2_CFG_RUN_Pos) /*!< CCU2 CLK_APB2_USART2_CFG: RUN Mask */ -#define CCU2_CLK_APB2_USART2_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Position */ -#define CCU2_CLK_APB2_USART2_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART2_CFG_AUTO_Pos) /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Mask */ -#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Position */ -#define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Mask */ - -// -------------------------------- CCU2_CLK_APB2_USART2_STAT ----------------------------------- -#define CCU2_CLK_APB2_USART2_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART2_STAT: RUN Position */ -#define CCU2_CLK_APB2_USART2_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART2_STAT_RUN_Pos) /*!< CCU2 CLK_APB2_USART2_STAT: RUN Mask */ -#define CCU2_CLK_APB2_USART2_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Position */ -#define CCU2_CLK_APB2_USART2_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART2_STAT_AUTO_Pos) /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Mask */ -#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Position */ -#define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Mask */ - -// ------------------------------- CCU2_CLK_APB0_UART1_BUS_CFG ---------------------------------- -#define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB0_UART1_BUS_CFG: RUN Position */ -#define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos) /*!< CCU2 CLK_APB0_UART1_BUS_CFG: RUN Mask */ -#define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB0_UART1_BUS_CFG: AUTO Position */ -#define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos) /*!< CCU2 CLK_APB0_UART1_BUS_CFG: AUTO Mask */ -#define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_UART1_BUS_CFG: WAKEUP Position */ -#define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB0_UART1_BUS_CFG: WAKEUP Mask */ - -// -------------------------------- CCU2_CLK_APB0_UART1_STAT ------------------------------------ -#define CCU2_CLK_APB0_UART1_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB0_UART1_STAT: RUN Position */ -#define CCU2_CLK_APB0_UART1_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB0_UART1_STAT_RUN_Pos) /*!< CCU2 CLK_APB0_UART1_STAT: RUN Mask */ -#define CCU2_CLK_APB0_UART1_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Position */ -#define CCU2_CLK_APB0_UART1_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB0_UART1_STAT_AUTO_Pos) /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Mask */ -#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Position */ -#define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Mask */ - -// -------------------------------- CCU2_CLK_APB0_USART0_CFG ------------------------------------ -#define CCU2_CLK_APB0_USART0_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB0_USART0_CFG: RUN Position */ -#define CCU2_CLK_APB0_USART0_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB0_USART0_CFG_RUN_Pos) /*!< CCU2 CLK_APB0_USART0_CFG: RUN Mask */ -#define CCU2_CLK_APB0_USART0_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Position */ -#define CCU2_CLK_APB0_USART0_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB0_USART0_CFG_AUTO_Pos) /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Mask */ -#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Position */ -#define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Mask */ - -// -------------------------------- CCU2_CLK_APB0_USART0_STAT ----------------------------------- -#define CCU2_CLK_APB0_USART0_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB0_USART0_STAT: RUN Position */ -#define CCU2_CLK_APB0_USART0_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB0_USART0_STAT_RUN_Pos) /*!< CCU2 CLK_APB0_USART0_STAT: RUN Mask */ -#define CCU2_CLK_APB0_USART0_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Position */ -#define CCU2_CLK_APB0_USART0_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB0_USART0_STAT_AUTO_Pos) /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Mask */ -#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Position */ -#define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Mask */ - -// --------------------------------- CCU2_CLK_APB2_SSP1_CFG ------------------------------------- -#define CCU2_CLK_APB2_SSP1_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Position */ -#define CCU2_CLK_APB2_SSP1_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB2_SSP1_CFG_RUN_Pos) /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Mask */ -#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Position */ -#define CCU2_CLK_APB2_SSP1_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos) /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Mask */ -#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Position */ -#define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Mask */ - -// --------------------------------- CCU2_CLK_APB2_SSP1_STAT ------------------------------------ -#define CCU2_CLK_APB2_SSP1_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Position */ -#define CCU2_CLK_APB2_SSP1_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB2_SSP1_STAT_RUN_Pos) /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Mask */ -#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Position */ -#define CCU2_CLK_APB2_SSP1_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos) /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Mask */ -#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Position */ -#define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Mask */ - -// --------------------------------- CCU2_CLK_APB0_SSP0_CFG ------------------------------------- -#define CCU2_CLK_APB0_SSP0_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Position */ -#define CCU2_CLK_APB0_SSP0_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB0_SSP0_CFG_RUN_Pos) /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Mask */ -#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Position */ -#define CCU2_CLK_APB0_SSP0_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos) /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Mask */ -#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Position */ -#define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Mask */ - -// --------------------------------- CCU2_CLK_APB0_SSP0_STAT ------------------------------------ -#define CCU2_CLK_APB0_SSP0_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Position */ -#define CCU2_CLK_APB0_SSP0_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB0_SSP0_STAT_RUN_Pos) /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Mask */ -#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Position */ -#define CCU2_CLK_APB0_SSP0_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos) /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Mask */ -#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Position */ -#define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Mask */ - -// ------------------------------------ CCU2_CLK_SDIO_CFG --------------------------------------- -#define CCU2_CLK_SDIO_CFG_RUN_Pos 0 /*!< CCU2 CLK_SDIO_CFG: RUN Position */ -#define CCU2_CLK_SDIO_CFG_RUN_Msk (0x01UL << CCU2_CLK_SDIO_CFG_RUN_Pos) /*!< CCU2 CLK_SDIO_CFG: RUN Mask */ -#define CCU2_CLK_SDIO_CFG_AUTO_Pos 1 /*!< CCU2 CLK_SDIO_CFG: AUTO Position */ -#define CCU2_CLK_SDIO_CFG_AUTO_Msk (0x01UL << CCU2_CLK_SDIO_CFG_AUTO_Pos) /*!< CCU2 CLK_SDIO_CFG: AUTO Mask */ -#define CCU2_CLK_SDIO_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_SDIO_CFG: WAKEUP Position */ -#define CCU2_CLK_SDIO_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_SDIO_CFG_WAKEUP_Pos) /*!< CCU2 CLK_SDIO_CFG: WAKEUP Mask */ - -// ----------------------------------- CCU2_CLK_SDIO_STAT --------------------------------------- -#define CCU2_CLK_SDIO_STAT_RUN_Pos 0 /*!< CCU2 CLK_SDIO_STAT: RUN Position */ -#define CCU2_CLK_SDIO_STAT_RUN_Msk (0x01UL << CCU2_CLK_SDIO_STAT_RUN_Pos) /*!< CCU2 CLK_SDIO_STAT: RUN Mask */ -#define CCU2_CLK_SDIO_STAT_AUTO_Pos 1 /*!< CCU2 CLK_SDIO_STAT: AUTO Position */ -#define CCU2_CLK_SDIO_STAT_AUTO_Msk (0x01UL << CCU2_CLK_SDIO_STAT_AUTO_Pos) /*!< CCU2 CLK_SDIO_STAT: AUTO Mask */ -#define CCU2_CLK_SDIO_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_SDIO_STAT: WAKEUP Position */ -#define CCU2_CLK_SDIO_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_SDIO_STAT_WAKEUP_Pos) /*!< CCU2 CLK_SDIO_STAT: WAKEUP Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- RGU Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ------------------------------------- RGU_RESET_CTRL0 ---------------------------------------- -#define RGU_RESET_CTRL0_CORE_RST_Pos 0 /*!< RGU RESET_CTRL0: CORE_RST Position */ -#define RGU_RESET_CTRL0_CORE_RST_Msk (0x01UL << RGU_RESET_CTRL0_CORE_RST_Pos) /*!< RGU RESET_CTRL0: CORE_RST Mask */ -#define RGU_RESET_CTRL0_PERIPH_RST_Pos 1 /*!< RGU RESET_CTRL0: PERIPH_RST Position */ -#define RGU_RESET_CTRL0_PERIPH_RST_Msk (0x01UL << RGU_RESET_CTRL0_PERIPH_RST_Pos) /*!< RGU RESET_CTRL0: PERIPH_RST Mask */ -#define RGU_RESET_CTRL0_MASTER_RST_Pos 2 /*!< RGU RESET_CTRL0: MASTER_RST Position */ -#define RGU_RESET_CTRL0_MASTER_RST_Msk (0x01UL << RGU_RESET_CTRL0_MASTER_RST_Pos) /*!< RGU RESET_CTRL0: MASTER_RST Mask */ -#define RGU_RESET_CTRL0_WWDT_RST_Pos 4 /*!< RGU RESET_CTRL0: WWDT_RST Position */ -#define RGU_RESET_CTRL0_WWDT_RST_Msk (0x01UL << RGU_RESET_CTRL0_WWDT_RST_Pos) /*!< RGU RESET_CTRL0: WWDT_RST Mask */ -#define RGU_RESET_CTRL0_CREG_RST_Pos 5 /*!< RGU RESET_CTRL0: CREG_RST Position */ -#define RGU_RESET_CTRL0_CREG_RST_Msk (0x01UL << RGU_RESET_CTRL0_CREG_RST_Pos) /*!< RGU RESET_CTRL0: CREG_RST Mask */ -#define RGU_RESET_CTRL0_BUS_RST_Pos 8 /*!< RGU RESET_CTRL0: BUS_RST Position */ -#define RGU_RESET_CTRL0_BUS_RST_Msk (0x01UL << RGU_RESET_CTRL0_BUS_RST_Pos) /*!< RGU RESET_CTRL0: BUS_RST Mask */ -#define RGU_RESET_CTRL0_SCU_RST_Pos 9 /*!< RGU RESET_CTRL0: SCU_RST Position */ -#define RGU_RESET_CTRL0_SCU_RST_Msk (0x01UL << RGU_RESET_CTRL0_SCU_RST_Pos) /*!< RGU RESET_CTRL0: SCU_RST Mask */ -#define RGU_RESET_CTRL0_PINMUX_RST_Pos 10 /*!< RGU RESET_CTRL0: PINMUX_RST Position */ -#define RGU_RESET_CTRL0_PINMUX_RST_Msk (0x01UL << RGU_RESET_CTRL0_PINMUX_RST_Pos) /*!< RGU RESET_CTRL0: PINMUX_RST Mask */ -#define RGU_RESET_CTRL0_M4_RST_Pos 13 /*!< RGU RESET_CTRL0: M4_RST Position */ -#define RGU_RESET_CTRL0_M4_RST_Msk (0x01UL << RGU_RESET_CTRL0_M4_RST_Pos) /*!< RGU RESET_CTRL0: M4_RST Mask */ -#define RGU_RESET_CTRL0_LCD_RST_Pos 16 /*!< RGU RESET_CTRL0: LCD_RST Position */ -#define RGU_RESET_CTRL0_LCD_RST_Msk (0x01UL << RGU_RESET_CTRL0_LCD_RST_Pos) /*!< RGU RESET_CTRL0: LCD_RST Mask */ -#define RGU_RESET_CTRL0_USB0_RST_Pos 17 /*!< RGU RESET_CTRL0: USB0_RST Position */ -#define RGU_RESET_CTRL0_USB0_RST_Msk (0x01UL << RGU_RESET_CTRL0_USB0_RST_Pos) /*!< RGU RESET_CTRL0: USB0_RST Mask */ -#define RGU_RESET_CTRL0_USB1_RST_Pos 18 /*!< RGU RESET_CTRL0: USB1_RST Position */ -#define RGU_RESET_CTRL0_USB1_RST_Msk (0x01UL << RGU_RESET_CTRL0_USB1_RST_Pos) /*!< RGU RESET_CTRL0: USB1_RST Mask */ -#define RGU_RESET_CTRL0_DMA_RST_Pos 19 /*!< RGU RESET_CTRL0: DMA_RST Position */ -#define RGU_RESET_CTRL0_DMA_RST_Msk (0x01UL << RGU_RESET_CTRL0_DMA_RST_Pos) /*!< RGU RESET_CTRL0: DMA_RST Mask */ -#define RGU_RESET_CTRL0_SDIO_RST_Pos 20 /*!< RGU RESET_CTRL0: SDIO_RST Position */ -#define RGU_RESET_CTRL0_SDIO_RST_Msk (0x01UL << RGU_RESET_CTRL0_SDIO_RST_Pos) /*!< RGU RESET_CTRL0: SDIO_RST Mask */ -#define RGU_RESET_CTRL0_EMC_RST_Pos 21 /*!< RGU RESET_CTRL0: EMC_RST Position */ -#define RGU_RESET_CTRL0_EMC_RST_Msk (0x01UL << RGU_RESET_CTRL0_EMC_RST_Pos) /*!< RGU RESET_CTRL0: EMC_RST Mask */ -#define RGU_RESET_CTRL0_ETHERNET_RST_Pos 22 /*!< RGU RESET_CTRL0: ETHERNET_RST Position */ -#define RGU_RESET_CTRL0_ETHERNET_RST_Msk (0x01UL << RGU_RESET_CTRL0_ETHERNET_RST_Pos) /*!< RGU RESET_CTRL0: ETHERNET_RST Mask */ -#define RGU_RESET_CTRL0_GPIO_RST_Pos 28 /*!< RGU RESET_CTRL0: GPIO_RST Position */ -#define RGU_RESET_CTRL0_GPIO_RST_Msk (0x01UL << RGU_RESET_CTRL0_GPIO_RST_Pos) /*!< RGU RESET_CTRL0: GPIO_RST Mask */ - -// ------------------------------------- RGU_RESET_CTRL1 ---------------------------------------- -#define RGU_RESET_CTRL1_TIMER0_RST_Pos 0 /*!< RGU RESET_CTRL1: TIMER0_RST Position */ -#define RGU_RESET_CTRL1_TIMER0_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER0_RST_Pos) /*!< RGU RESET_CTRL1: TIMER0_RST Mask */ -#define RGU_RESET_CTRL1_TIMER1_RST_Pos 1 /*!< RGU RESET_CTRL1: TIMER1_RST Position */ -#define RGU_RESET_CTRL1_TIMER1_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER1_RST_Pos) /*!< RGU RESET_CTRL1: TIMER1_RST Mask */ -#define RGU_RESET_CTRL1_TIMER2_RST_Pos 2 /*!< RGU RESET_CTRL1: TIMER2_RST Position */ -#define RGU_RESET_CTRL1_TIMER2_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER2_RST_Pos) /*!< RGU RESET_CTRL1: TIMER2_RST Mask */ -#define RGU_RESET_CTRL1_TIMER3_RST_Pos 3 /*!< RGU RESET_CTRL1: TIMER3_RST Position */ -#define RGU_RESET_CTRL1_TIMER3_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER3_RST_Pos) /*!< RGU RESET_CTRL1: TIMER3_RST Mask */ -#define RGU_RESET_CTRL1_RITIMER_RST_Pos 4 /*!< RGU RESET_CTRL1: RITIMER_RST Position */ -#define RGU_RESET_CTRL1_RITIMER_RST_Msk (0x01UL << RGU_RESET_CTRL1_RITIMER_RST_Pos) /*!< RGU RESET_CTRL1: RITIMER_RST Mask */ -#define RGU_RESET_CTRL1_SCT_RST_Pos 5 /*!< RGU RESET_CTRL1: SCT_RST Position */ -#define RGU_RESET_CTRL1_SCT_RST_Msk (0x01UL << RGU_RESET_CTRL1_SCT_RST_Pos) /*!< RGU RESET_CTRL1: SCT_RST Mask */ -#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos 6 /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Position */ -#define RGU_RESET_CTRL1_MOTOCONPWM_RST_Msk (0x01UL << RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos) /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Mask */ -#define RGU_RESET_CTRL1_QEI_RST_Pos 7 /*!< RGU RESET_CTRL1: QEI_RST Position */ -#define RGU_RESET_CTRL1_QEI_RST_Msk (0x01UL << RGU_RESET_CTRL1_QEI_RST_Pos) /*!< RGU RESET_CTRL1: QEI_RST Mask */ -#define RGU_RESET_CTRL1_ADC0_RST_Pos 8 /*!< RGU RESET_CTRL1: ADC0_RST Position */ -#define RGU_RESET_CTRL1_ADC0_RST_Msk (0x01UL << RGU_RESET_CTRL1_ADC0_RST_Pos) /*!< RGU RESET_CTRL1: ADC0_RST Mask */ -#define RGU_RESET_CTRL1_ADC1_RST_Pos 9 /*!< RGU RESET_CTRL1: ADC1_RST Position */ -#define RGU_RESET_CTRL1_ADC1_RST_Msk (0x01UL << RGU_RESET_CTRL1_ADC1_RST_Pos) /*!< RGU RESET_CTRL1: ADC1_RST Mask */ -#define RGU_RESET_CTRL1_DAC_RST_Pos 10 /*!< RGU RESET_CTRL1: DAC_RST Position */ -#define RGU_RESET_CTRL1_DAC_RST_Msk (0x01UL << RGU_RESET_CTRL1_DAC_RST_Pos) /*!< RGU RESET_CTRL1: DAC_RST Mask */ -#define RGU_RESET_CTRL1_UART0_RST_Pos 12 /*!< RGU RESET_CTRL1: UART0_RST Position */ -#define RGU_RESET_CTRL1_UART0_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART0_RST_Pos) /*!< RGU RESET_CTRL1: UART0_RST Mask */ -#define RGU_RESET_CTRL1_UART1_RST_Pos 13 /*!< RGU RESET_CTRL1: UART1_RST Position */ -#define RGU_RESET_CTRL1_UART1_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART1_RST_Pos) /*!< RGU RESET_CTRL1: UART1_RST Mask */ -#define RGU_RESET_CTRL1_UART2_RST_Pos 14 /*!< RGU RESET_CTRL1: UART2_RST Position */ -#define RGU_RESET_CTRL1_UART2_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART2_RST_Pos) /*!< RGU RESET_CTRL1: UART2_RST Mask */ -#define RGU_RESET_CTRL1_UART3_RST_Pos 15 /*!< RGU RESET_CTRL1: UART3_RST Position */ -#define RGU_RESET_CTRL1_UART3_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART3_RST_Pos) /*!< RGU RESET_CTRL1: UART3_RST Mask */ -#define RGU_RESET_CTRL1_I2C0_RST_Pos 16 /*!< RGU RESET_CTRL1: I2C0_RST Position */ -#define RGU_RESET_CTRL1_I2C0_RST_Msk (0x01UL << RGU_RESET_CTRL1_I2C0_RST_Pos) /*!< RGU RESET_CTRL1: I2C0_RST Mask */ -#define RGU_RESET_CTRL1_I2C1_RST_Pos 17 /*!< RGU RESET_CTRL1: I2C1_RST Position */ -#define RGU_RESET_CTRL1_I2C1_RST_Msk (0x01UL << RGU_RESET_CTRL1_I2C1_RST_Pos) /*!< RGU RESET_CTRL1: I2C1_RST Mask */ -#define RGU_RESET_CTRL1_SSP0_RST_Pos 18 /*!< RGU RESET_CTRL1: SSP0_RST Position */ -#define RGU_RESET_CTRL1_SSP0_RST_Msk (0x01UL << RGU_RESET_CTRL1_SSP0_RST_Pos) /*!< RGU RESET_CTRL1: SSP0_RST Mask */ -#define RGU_RESET_CTRL1_SSP1_RST_Pos 19 /*!< RGU RESET_CTRL1: SSP1_RST Position */ -#define RGU_RESET_CTRL1_SSP1_RST_Msk (0x01UL << RGU_RESET_CTRL1_SSP1_RST_Pos) /*!< RGU RESET_CTRL1: SSP1_RST Mask */ -#define RGU_RESET_CTRL1_I2S_RST_Pos 20 /*!< RGU RESET_CTRL1: I2S_RST Position */ -#define RGU_RESET_CTRL1_I2S_RST_Msk (0x01UL << RGU_RESET_CTRL1_I2S_RST_Pos) /*!< RGU RESET_CTRL1: I2S_RST Mask */ -#define RGU_RESET_CTRL1_SPIFI_RST_Pos 21 /*!< RGU RESET_CTRL1: SPIFI_RST Position */ -#define RGU_RESET_CTRL1_SPIFI_RST_Msk (0x01UL << RGU_RESET_CTRL1_SPIFI_RST_Pos) /*!< RGU RESET_CTRL1: SPIFI_RST Mask */ -#define RGU_RESET_CTRL1_CAN1_RST_Pos 22 /*!< RGU RESET_CTRL1: CAN1_RST Position */ -#define RGU_RESET_CTRL1_CAN1_RST_Msk (0x01UL << RGU_RESET_CTRL1_CAN1_RST_Pos) /*!< RGU RESET_CTRL1: CAN1_RST Mask */ -#define RGU_RESET_CTRL1_CAN0_RST_Pos 23 /*!< RGU RESET_CTRL1: CAN0_RST Position */ -#define RGU_RESET_CTRL1_CAN0_RST_Msk (0x01UL << RGU_RESET_CTRL1_CAN0_RST_Pos) /*!< RGU RESET_CTRL1: CAN0_RST Mask */ -#define RGU_RESET_CTRL1_M0APP_RST_Pos 24 /*!< RGU RESET_CTRL1: M0APP_RST Position */ -#define RGU_RESET_CTRL1_M0APP_RST_Msk (0x01UL << RGU_RESET_CTRL1_M0APP_RST_Pos) /*!< RGU RESET_CTRL1: M0APP_RST Mask */ -#define RGU_RESET_CTRL1_SGPIO_RST_Pos 25 /*!< RGU RESET_CTRL1: SGPIO_RST Position */ -#define RGU_RESET_CTRL1_SGPIO_RST_Msk (0x01UL << RGU_RESET_CTRL1_SGPIO_RST_Pos) /*!< RGU RESET_CTRL1: SGPIO_RST Mask */ -#define RGU_RESET_CTRL1_SPI_RST_Pos 26 /*!< RGU RESET_CTRL1: SPI_RST Position */ -#define RGU_RESET_CTRL1_SPI_RST_Msk (0x01UL << RGU_RESET_CTRL1_SPI_RST_Pos) /*!< RGU RESET_CTRL1: SPI_RST Mask */ - -// ------------------------------------ RGU_RESET_STATUS0 --------------------------------------- -#define RGU_RESET_STATUS0_CORE_RST_Pos 0 /*!< RGU RESET_STATUS0: CORE_RST Position */ -#define RGU_RESET_STATUS0_CORE_RST_Msk (0x03UL << RGU_RESET_STATUS0_CORE_RST_Pos) /*!< RGU RESET_STATUS0: CORE_RST Mask */ -#define RGU_RESET_STATUS0_PERIPH_RST_Pos 2 /*!< RGU RESET_STATUS0: PERIPH_RST Position */ -#define RGU_RESET_STATUS0_PERIPH_RST_Msk (0x03UL << RGU_RESET_STATUS0_PERIPH_RST_Pos) /*!< RGU RESET_STATUS0: PERIPH_RST Mask */ -#define RGU_RESET_STATUS0_MASTER_RST_Pos 4 /*!< RGU RESET_STATUS0: MASTER_RST Position */ -#define RGU_RESET_STATUS0_MASTER_RST_Msk (0x03UL << RGU_RESET_STATUS0_MASTER_RST_Pos) /*!< RGU RESET_STATUS0: MASTER_RST Mask */ -#define RGU_RESET_STATUS0_WWDT_RST_Pos 8 /*!< RGU RESET_STATUS0: WWDT_RST Position */ -#define RGU_RESET_STATUS0_WWDT_RST_Msk (0x03UL << RGU_RESET_STATUS0_WWDT_RST_Pos) /*!< RGU RESET_STATUS0: WWDT_RST Mask */ -#define RGU_RESET_STATUS0_CREG_RST_Pos 10 /*!< RGU RESET_STATUS0: CREG_RST Position */ -#define RGU_RESET_STATUS0_CREG_RST_Msk (0x03UL << RGU_RESET_STATUS0_CREG_RST_Pos) /*!< RGU RESET_STATUS0: CREG_RST Mask */ -#define RGU_RESET_STATUS0_BUS_RST_Pos 16 /*!< RGU RESET_STATUS0: BUS_RST Position */ -#define RGU_RESET_STATUS0_BUS_RST_Msk (0x03UL << RGU_RESET_STATUS0_BUS_RST_Pos) /*!< RGU RESET_STATUS0: BUS_RST Mask */ -#define RGU_RESET_STATUS0_SCU_RST_Pos 18 /*!< RGU RESET_STATUS0: SCU_RST Position */ -#define RGU_RESET_STATUS0_SCU_RST_Msk (0x03UL << RGU_RESET_STATUS0_SCU_RST_Pos) /*!< RGU RESET_STATUS0: SCU_RST Mask */ -#define RGU_RESET_STATUS0_M4_RST_Pos 26 /*!< RGU RESET_STATUS0: M4_RST Position */ -#define RGU_RESET_STATUS0_M4_RST_Msk (0x03UL << RGU_RESET_STATUS0_M4_RST_Pos) /*!< RGU RESET_STATUS0: M4_RST Mask */ - -// ------------------------------------ RGU_RESET_STATUS1 --------------------------------------- -#define RGU_RESET_STATUS1_LCD_RST_Pos 0 /*!< RGU RESET_STATUS1: LCD_RST Position */ -#define RGU_RESET_STATUS1_LCD_RST_Msk (0x03UL << RGU_RESET_STATUS1_LCD_RST_Pos) /*!< RGU RESET_STATUS1: LCD_RST Mask */ -#define RGU_RESET_STATUS1_USB0_RST_Pos 2 /*!< RGU RESET_STATUS1: USB0_RST Position */ -#define RGU_RESET_STATUS1_USB0_RST_Msk (0x03UL << RGU_RESET_STATUS1_USB0_RST_Pos) /*!< RGU RESET_STATUS1: USB0_RST Mask */ -#define RGU_RESET_STATUS1_USB1_RST_Pos 4 /*!< RGU RESET_STATUS1: USB1_RST Position */ -#define RGU_RESET_STATUS1_USB1_RST_Msk (0x03UL << RGU_RESET_STATUS1_USB1_RST_Pos) /*!< RGU RESET_STATUS1: USB1_RST Mask */ -#define RGU_RESET_STATUS1_DMA_RST_Pos 6 /*!< RGU RESET_STATUS1: DMA_RST Position */ -#define RGU_RESET_STATUS1_DMA_RST_Msk (0x03UL << RGU_RESET_STATUS1_DMA_RST_Pos) /*!< RGU RESET_STATUS1: DMA_RST Mask */ -#define RGU_RESET_STATUS1_SDIO_RST_Pos 8 /*!< RGU RESET_STATUS1: SDIO_RST Position */ -#define RGU_RESET_STATUS1_SDIO_RST_Msk (0x03UL << RGU_RESET_STATUS1_SDIO_RST_Pos) /*!< RGU RESET_STATUS1: SDIO_RST Mask */ -#define RGU_RESET_STATUS1_EMC_RST_Pos 10 /*!< RGU RESET_STATUS1: EMC_RST Position */ -#define RGU_RESET_STATUS1_EMC_RST_Msk (0x03UL << RGU_RESET_STATUS1_EMC_RST_Pos) /*!< RGU RESET_STATUS1: EMC_RST Mask */ -#define RGU_RESET_STATUS1_ETHERNET_RST_Pos 12 /*!< RGU RESET_STATUS1: ETHERNET_RST Position */ -#define RGU_RESET_STATUS1_ETHERNET_RST_Msk (0x03UL << RGU_RESET_STATUS1_ETHERNET_RST_Pos) /*!< RGU RESET_STATUS1: ETHERNET_RST Mask */ -#define RGU_RESET_STATUS1_GPIO_RST_Pos 24 /*!< RGU RESET_STATUS1: GPIO_RST Position */ -#define RGU_RESET_STATUS1_GPIO_RST_Msk (0x03UL << RGU_RESET_STATUS1_GPIO_RST_Pos) /*!< RGU RESET_STATUS1: GPIO_RST Mask */ - -// ------------------------------------ RGU_RESET_STATUS2 --------------------------------------- -#define RGU_RESET_STATUS2_TIMER0_RST_Pos 0 /*!< RGU RESET_STATUS2: TIMER0_RST Position */ -#define RGU_RESET_STATUS2_TIMER0_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER0_RST_Pos) /*!< RGU RESET_STATUS2: TIMER0_RST Mask */ -#define RGU_RESET_STATUS2_TIMER1_RST_Pos 2 /*!< RGU RESET_STATUS2: TIMER1_RST Position */ -#define RGU_RESET_STATUS2_TIMER1_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER1_RST_Pos) /*!< RGU RESET_STATUS2: TIMER1_RST Mask */ -#define RGU_RESET_STATUS2_TIMER2_RST_Pos 4 /*!< RGU RESET_STATUS2: TIMER2_RST Position */ -#define RGU_RESET_STATUS2_TIMER2_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER2_RST_Pos) /*!< RGU RESET_STATUS2: TIMER2_RST Mask */ -#define RGU_RESET_STATUS2_TIMER3_RST_Pos 6 /*!< RGU RESET_STATUS2: TIMER3_RST Position */ -#define RGU_RESET_STATUS2_TIMER3_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER3_RST_Pos) /*!< RGU RESET_STATUS2: TIMER3_RST Mask */ -#define RGU_RESET_STATUS2_RITIMER_RST_Pos 8 /*!< RGU RESET_STATUS2: RITIMER_RST Position */ -#define RGU_RESET_STATUS2_RITIMER_RST_Msk (0x03UL << RGU_RESET_STATUS2_RITIMER_RST_Pos) /*!< RGU RESET_STATUS2: RITIMER_RST Mask */ -#define RGU_RESET_STATUS2_SCT_RST_Pos 10 /*!< RGU RESET_STATUS2: SCT_RST Position */ -#define RGU_RESET_STATUS2_SCT_RST_Msk (0x03UL << RGU_RESET_STATUS2_SCT_RST_Pos) /*!< RGU RESET_STATUS2: SCT_RST Mask */ -#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos 12 /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Position */ -#define RGU_RESET_STATUS2_MOTOCONPWM_RST_Msk (0x03UL << RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos) /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Mask */ -#define RGU_RESET_STATUS2_QEI_RST_Pos 14 /*!< RGU RESET_STATUS2: QEI_RST Position */ -#define RGU_RESET_STATUS2_QEI_RST_Msk (0x03UL << RGU_RESET_STATUS2_QEI_RST_Pos) /*!< RGU RESET_STATUS2: QEI_RST Mask */ -#define RGU_RESET_STATUS2_ADC0_RST_Pos 16 /*!< RGU RESET_STATUS2: ADC0_RST Position */ -#define RGU_RESET_STATUS2_ADC0_RST_Msk (0x03UL << RGU_RESET_STATUS2_ADC0_RST_Pos) /*!< RGU RESET_STATUS2: ADC0_RST Mask */ -#define RGU_RESET_STATUS2_ADC1_RST_Pos 18 /*!< RGU RESET_STATUS2: ADC1_RST Position */ -#define RGU_RESET_STATUS2_ADC1_RST_Msk (0x03UL << RGU_RESET_STATUS2_ADC1_RST_Pos) /*!< RGU RESET_STATUS2: ADC1_RST Mask */ -#define RGU_RESET_STATUS2_DAC_RST_Pos 20 /*!< RGU RESET_STATUS2: DAC_RST Position */ -#define RGU_RESET_STATUS2_DAC_RST_Msk (0x03UL << RGU_RESET_STATUS2_DAC_RST_Pos) /*!< RGU RESET_STATUS2: DAC_RST Mask */ -#define RGU_RESET_STATUS2_UART0_RST_Pos 24 /*!< RGU RESET_STATUS2: UART0_RST Position */ -#define RGU_RESET_STATUS2_UART0_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART0_RST_Pos) /*!< RGU RESET_STATUS2: UART0_RST Mask */ -#define RGU_RESET_STATUS2_UART1_RST_Pos 26 /*!< RGU RESET_STATUS2: UART1_RST Position */ -#define RGU_RESET_STATUS2_UART1_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART1_RST_Pos) /*!< RGU RESET_STATUS2: UART1_RST Mask */ -#define RGU_RESET_STATUS2_UART2_RST_Pos 28 /*!< RGU RESET_STATUS2: UART2_RST Position */ -#define RGU_RESET_STATUS2_UART2_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART2_RST_Pos) /*!< RGU RESET_STATUS2: UART2_RST Mask */ -#define RGU_RESET_STATUS2_UART3_RST_Pos 30 /*!< RGU RESET_STATUS2: UART3_RST Position */ -#define RGU_RESET_STATUS2_UART3_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART3_RST_Pos) /*!< RGU RESET_STATUS2: UART3_RST Mask */ - -// ------------------------------------ RGU_RESET_STATUS3 --------------------------------------- -#define RGU_RESET_STATUS3_I2C0_RST_Pos 0 /*!< RGU RESET_STATUS3: I2C0_RST Position */ -#define RGU_RESET_STATUS3_I2C0_RST_Msk (0x03UL << RGU_RESET_STATUS3_I2C0_RST_Pos) /*!< RGU RESET_STATUS3: I2C0_RST Mask */ -#define RGU_RESET_STATUS3_I2C1_RST_Pos 2 /*!< RGU RESET_STATUS3: I2C1_RST Position */ -#define RGU_RESET_STATUS3_I2C1_RST_Msk (0x03UL << RGU_RESET_STATUS3_I2C1_RST_Pos) /*!< RGU RESET_STATUS3: I2C1_RST Mask */ -#define RGU_RESET_STATUS3_SSP0_RST_Pos 4 /*!< RGU RESET_STATUS3: SSP0_RST Position */ -#define RGU_RESET_STATUS3_SSP0_RST_Msk (0x03UL << RGU_RESET_STATUS3_SSP0_RST_Pos) /*!< RGU RESET_STATUS3: SSP0_RST Mask */ -#define RGU_RESET_STATUS3_SSP1_RST_Pos 6 /*!< RGU RESET_STATUS3: SSP1_RST Position */ -#define RGU_RESET_STATUS3_SSP1_RST_Msk (0x03UL << RGU_RESET_STATUS3_SSP1_RST_Pos) /*!< RGU RESET_STATUS3: SSP1_RST Mask */ -#define RGU_RESET_STATUS3_I2S_RST_Pos 8 /*!< RGU RESET_STATUS3: I2S_RST Position */ -#define RGU_RESET_STATUS3_I2S_RST_Msk (0x03UL << RGU_RESET_STATUS3_I2S_RST_Pos) /*!< RGU RESET_STATUS3: I2S_RST Mask */ -#define RGU_RESET_STATUS3_SPIFI_RST_Pos 10 /*!< RGU RESET_STATUS3: SPIFI_RST Position */ -#define RGU_RESET_STATUS3_SPIFI_RST_Msk (0x03UL << RGU_RESET_STATUS3_SPIFI_RST_Pos) /*!< RGU RESET_STATUS3: SPIFI_RST Mask */ -#define RGU_RESET_STATUS3_CAN1_RST_Pos 12 /*!< RGU RESET_STATUS3: CAN1_RST Position */ -#define RGU_RESET_STATUS3_CAN1_RST_Msk (0x03UL << RGU_RESET_STATUS3_CAN1_RST_Pos) /*!< RGU RESET_STATUS3: CAN1_RST Mask */ -#define RGU_RESET_STATUS3_CAN0_RST_Pos 14 /*!< RGU RESET_STATUS3: CAN0_RST Position */ -#define RGU_RESET_STATUS3_CAN0_RST_Msk (0x03UL << RGU_RESET_STATUS3_CAN0_RST_Pos) /*!< RGU RESET_STATUS3: CAN0_RST Mask */ -#define RGU_RESET_STATUS3_M0APP_RST_Pos 16 /*!< RGU RESET_STATUS3: M0APP_RST Position */ -#define RGU_RESET_STATUS3_M0APP_RST_Msk (0x03UL << RGU_RESET_STATUS3_M0APP_RST_Pos) /*!< RGU RESET_STATUS3: M0APP_RST Mask */ -#define RGU_RESET_STATUS3_SGPIO_RST_Pos 18 /*!< RGU RESET_STATUS3: SGPIO_RST Position */ -#define RGU_RESET_STATUS3_SGPIO_RST_Msk (0x03UL << RGU_RESET_STATUS3_SGPIO_RST_Pos) /*!< RGU RESET_STATUS3: SGPIO_RST Mask */ -#define RGU_RESET_STATUS3_SPI_RST_Pos 20 /*!< RGU RESET_STATUS3: SPI_RST Position */ -#define RGU_RESET_STATUS3_SPI_RST_Msk (0x03UL << RGU_RESET_STATUS3_SPI_RST_Pos) /*!< RGU RESET_STATUS3: SPI_RST Mask */ - -// -------------------------------- RGU_RESET_ACTIVE_STATUS0 ------------------------------------ -#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos 0 /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos 1 /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos 2 /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos 4 /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos 5 /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos 8 /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos 9 /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Pos 10 /*!< RGU RESET_ACTIVE_STATUS0: PINMUX_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_PINMUX_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: PINMUX_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_M3_RST_Pos 13 /*!< RGU RESET_ACTIVE_STATUS0: M3_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_M3_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_M3_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: M3_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos 16 /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos 17 /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos 18 /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos 19 /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos 20 /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos 21 /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos 22 /*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos 28 /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Position */ -#define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Mask */ - -// -------------------------------- RGU_RESET_ACTIVE_STATUS1 ------------------------------------ -#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos 0 /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos 1 /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos 2 /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos 3 /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos 4 /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos 5 /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos 6 /*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos 7 /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos 8 /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos 9 /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos 10 /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos 12 /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos 13 /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos 14 /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos 15 /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos 16 /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos 17 /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos 18 /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos 19 /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos 20 /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos 21 /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos 22 /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos 23 /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_MOAPP_RST_Pos 24 /*!< RGU RESET_ACTIVE_STATUS1: MOAPP_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_MOAPP_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_MOAPP_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: MOAPP_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Pos 25 /*!< RGU RESET_ACTIVE_STATUS1: SGPIO_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SGPIO_RST Mask */ -#define RGU_RESET_ACTIVE_STATUS1_SPI_RST_Pos 26 /*!< RGU RESET_ACTIVE_STATUS1: SPI_RST Position */ -#define RGU_RESET_ACTIVE_STATUS1_SPI_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SPI_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SPI_RST Mask */ - -// ----------------------------------- RGU_RESET_EXT_STAT0 -------------------------------------- -#define RGU_RESET_EXT_STAT0_EXT_RESET_Pos 0 /*!< RGU RESET_EXT_STAT0: EXT_RESET Position */ -#define RGU_RESET_EXT_STAT0_EXT_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT0_EXT_RESET_Pos) /*!< RGU RESET_EXT_STAT0: EXT_RESET Mask */ -#define RGU_RESET_EXT_STAT0_BOD_RESET_Pos 4 /*!< RGU RESET_EXT_STAT0: BOD_RESET Position */ -#define RGU_RESET_EXT_STAT0_BOD_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT0_BOD_RESET_Pos) /*!< RGU RESET_EXT_STAT0: BOD_RESET Mask */ -#define RGU_RESET_EXT_STAT0_WWDT_RESET_Pos 5 /*!< RGU RESET_EXT_STAT0: WWDT_RESET Position */ -#define RGU_RESET_EXT_STAT0_WWDT_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT0_WWDT_RESET_Pos) /*!< RGU RESET_EXT_STAT0: WWDT_RESET Mask */ - -// ----------------------------------- RGU_RESET_EXT_STAT1 -------------------------------------- -#define RGU_RESET_EXT_STAT1_CORE_RESET_Pos 1 /*!< RGU RESET_EXT_STAT1: CORE_RESET Position */ -#define RGU_RESET_EXT_STAT1_CORE_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT1_CORE_RESET_Pos) /*!< RGU RESET_EXT_STAT1: CORE_RESET Mask */ - -// ----------------------------------- RGU_RESET_EXT_STAT2 -------------------------------------- -#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Mask */ - -// ----------------------------------- RGU_RESET_EXT_STAT4 -------------------------------------- -#define RGU_RESET_EXT_STAT4_CORE_RESET_Pos 1 /*!< RGU RESET_EXT_STAT4: CORE_RESET Position */ -#define RGU_RESET_EXT_STAT4_CORE_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT4_CORE_RESET_Pos) /*!< RGU RESET_EXT_STAT4: CORE_RESET Mask */ - -// ----------------------------------- RGU_RESET_EXT_STAT5 -------------------------------------- -#define RGU_RESET_EXT_STAT5_CORE_RESET_Pos 1 /*!< RGU RESET_EXT_STAT5: CORE_RESET Position */ -#define RGU_RESET_EXT_STAT5_CORE_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT5_CORE_RESET_Pos) /*!< RGU RESET_EXT_STAT5: CORE_RESET Mask */ - -// ----------------------------------- RGU_RESET_EXT_STAT8 -------------------------------------- -#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Mask */ - -// ----------------------------------- RGU_RESET_EXT_STAT9 -------------------------------------- -#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT13 -------------------------------------- -#define RGU_RESET_EXT_STAT13_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT13: MASTER_RESET Position */ -#define RGU_RESET_EXT_STAT13_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT13_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT13: MASTER_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT16 -------------------------------------- -#define RGU_RESET_EXT_STAT16_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT16: MASTER_RESET Position */ -#define RGU_RESET_EXT_STAT16_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT16_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT16: MASTER_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT17 -------------------------------------- -#define RGU_RESET_EXT_STAT17_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT17: MASTER_RESET Position */ -#define RGU_RESET_EXT_STAT17_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT17_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT17: MASTER_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT18 -------------------------------------- -#define RGU_RESET_EXT_STAT18_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT18: MASTER_RESET Position */ -#define RGU_RESET_EXT_STAT18_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT18_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT18: MASTER_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT19 -------------------------------------- -#define RGU_RESET_EXT_STAT19_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT19: MASTER_RESET Position */ -#define RGU_RESET_EXT_STAT19_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT19_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT19: MASTER_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT20 -------------------------------------- -#define RGU_RESET_EXT_STAT20_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT20: MASTER_RESET Position */ -#define RGU_RESET_EXT_STAT20_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT20_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT20: MASTER_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT21 -------------------------------------- -#define RGU_RESET_EXT_STAT21_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT21: MASTER_RESET Position */ -#define RGU_RESET_EXT_STAT21_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT21_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT21: MASTER_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT22 -------------------------------------- -#define RGU_RESET_EXT_STAT22_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT22: MASTER_RESET Position */ -#define RGU_RESET_EXT_STAT22_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT22_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT22: MASTER_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT23 -------------------------------------- -#define RGU_RESET_EXT_STAT23_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT23: MASTER_RESET Position */ -#define RGU_RESET_EXT_STAT23_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT23_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT23: MASTER_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT28 -------------------------------------- -#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT32 -------------------------------------- -#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT33 -------------------------------------- -#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT34 -------------------------------------- -#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT35 -------------------------------------- -#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT36 -------------------------------------- -#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT37 -------------------------------------- -#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT38 -------------------------------------- -#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT39 -------------------------------------- -#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT40 -------------------------------------- -#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT41 -------------------------------------- -#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT42 -------------------------------------- -#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT44 -------------------------------------- -#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT45 -------------------------------------- -#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT46 -------------------------------------- -#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT47 -------------------------------------- -#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT48 -------------------------------------- -#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT49 -------------------------------------- -#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT50 -------------------------------------- -#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT51 -------------------------------------- -#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT52 -------------------------------------- -#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT53 -------------------------------------- -#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT54 -------------------------------------- -#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Mask */ - -// ---------------------------------- RGU_RESET_EXT_STAT55 -------------------------------------- -#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Position */ -#define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- WWDT Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- WWDT_MOD -------------------------------------------- -#define WWDT_MOD_WDEN_Pos 0 /*!< WWDT MOD: WDEN Position */ -#define WWDT_MOD_WDEN_Msk (0x01UL << WWDT_MOD_WDEN_Pos) /*!< WWDT MOD: WDEN Mask */ -#define WWDT_MOD_WDRESET_Pos 1 /*!< WWDT MOD: WDRESET Position */ -#define WWDT_MOD_WDRESET_Msk (0x01UL << WWDT_MOD_WDRESET_Pos) /*!< WWDT MOD: WDRESET Mask */ -#define WWDT_MOD_WDTOF_Pos 2 /*!< WWDT MOD: WDTOF Position */ -#define WWDT_MOD_WDTOF_Msk (0x01UL << WWDT_MOD_WDTOF_Pos) /*!< WWDT MOD: WDTOF Mask */ -#define WWDT_MOD_WDINT_Pos 3 /*!< WWDT MOD: WDINT Position */ -#define WWDT_MOD_WDINT_Msk (0x01UL << WWDT_MOD_WDINT_Pos) /*!< WWDT MOD: WDINT Mask */ -#define WWDT_MOD_WDPROTECT_Pos 4 /*!< WWDT MOD: WDPROTECT Position */ -#define WWDT_MOD_WDPROTECT_Msk (0x01UL << WWDT_MOD_WDPROTECT_Pos) /*!< WWDT MOD: WDPROTECT Mask */ - -// ----------------------------------------- WWDT_TC -------------------------------------------- -#define WWDT_TC_WDTC_Pos 0 /*!< WWDT TC: WDTC Position */ -#define WWDT_TC_WDTC_Msk (0x00ffffffUL << WWDT_TC_WDTC_Pos) /*!< WWDT TC: WDTC Mask */ - -// ---------------------------------------- WWDT_FEED ------------------------------------------- -#define WWDT_FEED_Feed_Pos 0 /*!< WWDT FEED: Feed Position */ -#define WWDT_FEED_Feed_Msk (0x000000ffUL << WWDT_FEED_Feed_Pos) /*!< WWDT FEED: Feed Mask */ - -// ----------------------------------------- WWDT_TV -------------------------------------------- -#define WWDT_TV_Count_Pos 0 /*!< WWDT TV: Count Position */ -#define WWDT_TV_Count_Msk (0x00ffffffUL << WWDT_TV_Count_Pos) /*!< WWDT TV: Count Mask */ - -// -------------------------------------- WWDT_WARNINT ------------------------------------------ -#define WWDT_WARNINT_WDWARNINT_Pos 0 /*!< WWDT WARNINT: WDWARNINT Position */ -#define WWDT_WARNINT_WDWARNINT_Msk (0x000003ffUL << WWDT_WARNINT_WDWARNINT_Pos) /*!< WWDT WARNINT: WDWARNINT Mask */ - -// --------------------------------------- WWDT_WINDOW ------------------------------------------ -#define WWDT_WINDOW_WDWINDOW_Pos 0 /*!< WWDT WINDOW: WDWINDOW Position */ -#define WWDT_WINDOW_WDWINDOW_Msk (0x00ffffffUL << WWDT_WINDOW_WDWINDOW_Pos) /*!< WWDT WINDOW: WDWINDOW Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- USART0 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- USART0_RBR ------------------------------------------- -#define USART0_RBR_RBR_Pos 0 /*!< USART0 RBR: RBR Position */ -#define USART0_RBR_RBR_Msk (0x000000ffUL << USART0_RBR_RBR_Pos) /*!< USART0 RBR: RBR Mask */ - -// --------------------------------------- USART0_THR ------------------------------------------- -#define USART0_THR_THR_Pos 0 /*!< USART0 THR: THR Position */ -#define USART0_THR_THR_Msk (0x000000ffUL << USART0_THR_THR_Pos) /*!< USART0 THR: THR Mask */ - -// --------------------------------------- USART0_DLL ------------------------------------------- -#define USART0_DLL_DLLSB_Pos 0 /*!< USART0 DLL: DLLSB Position */ -#define USART0_DLL_DLLSB_Msk (0x000000ffUL << USART0_DLL_DLLSB_Pos) /*!< USART0 DLL: DLLSB Mask */ - -// --------------------------------------- USART0_DLM ------------------------------------------- -#define USART0_DLM_DLMSB_Pos 0 /*!< USART0 DLM: DLMSB Position */ -#define USART0_DLM_DLMSB_Msk (0x000000ffUL << USART0_DLM_DLMSB_Pos) /*!< USART0 DLM: DLMSB Mask */ - -// --------------------------------------- USART0_IER ------------------------------------------- -#define USART0_IER_RBRIE_Pos 0 /*!< USART0 IER: RBRIE Position */ -#define USART0_IER_RBRIE_Msk (0x01UL << USART0_IER_RBRIE_Pos) /*!< USART0 IER: RBRIE Mask */ -#define USART0_IER_THREIE_Pos 1 /*!< USART0 IER: THREIE Position */ -#define USART0_IER_THREIE_Msk (0x01UL << USART0_IER_THREIE_Pos) /*!< USART0 IER: THREIE Mask */ -#define USART0_IER_RXIE_Pos 2 /*!< USART0 IER: RXIE Position */ -#define USART0_IER_RXIE_Msk (0x01UL << USART0_IER_RXIE_Pos) /*!< USART0 IER: RXIE Mask */ -#define USART0_IER_ABEOINTEN_Pos 8 /*!< USART0 IER: ABEOINTEN Position */ -#define USART0_IER_ABEOINTEN_Msk (0x01UL << USART0_IER_ABEOINTEN_Pos) /*!< USART0 IER: ABEOINTEN Mask */ -#define USART0_IER_ABTOINTEN_Pos 9 /*!< USART0 IER: ABTOINTEN Position */ -#define USART0_IER_ABTOINTEN_Msk (0x01UL << USART0_IER_ABTOINTEN_Pos) /*!< USART0 IER: ABTOINTEN Mask */ - -// --------------------------------------- USART0_IIR ------------------------------------------- -#define USART0_IIR_INTSTATUS_Pos 0 /*!< USART0 IIR: INTSTATUS Position */ -#define USART0_IIR_INTSTATUS_Msk (0x01UL << USART0_IIR_INTSTATUS_Pos) /*!< USART0 IIR: INTSTATUS Mask */ -#define USART0_IIR_INTID_Pos 1 /*!< USART0 IIR: INTID Position */ -#define USART0_IIR_INTID_Msk (0x07UL << USART0_IIR_INTID_Pos) /*!< USART0 IIR: INTID Mask */ -#define USART0_IIR_FIFOENABLE_Pos 6 /*!< USART0 IIR: FIFOENABLE Position */ -#define USART0_IIR_FIFOENABLE_Msk (0x03UL << USART0_IIR_FIFOENABLE_Pos) /*!< USART0 IIR: FIFOENABLE Mask */ -#define USART0_IIR_ABEOINT_Pos 8 /*!< USART0 IIR: ABEOINT Position */ -#define USART0_IIR_ABEOINT_Msk (0x01UL << USART0_IIR_ABEOINT_Pos) /*!< USART0 IIR: ABEOINT Mask */ -#define USART0_IIR_ABTOINT_Pos 9 /*!< USART0 IIR: ABTOINT Position */ -#define USART0_IIR_ABTOINT_Msk (0x01UL << USART0_IIR_ABTOINT_Pos) /*!< USART0 IIR: ABTOINT Mask */ - -// --------------------------------------- USART0_FCR ------------------------------------------- -#define USART0_FCR_FIFOEN_Pos 0 /*!< USART0 FCR: FIFOEN Position */ -#define USART0_FCR_FIFOEN_Msk (0x01UL << USART0_FCR_FIFOEN_Pos) /*!< USART0 FCR: FIFOEN Mask */ -#define USART0_FCR_RXFIFORES_Pos 1 /*!< USART0 FCR: RXFIFORES Position */ -#define USART0_FCR_RXFIFORES_Msk (0x01UL << USART0_FCR_RXFIFORES_Pos) /*!< USART0 FCR: RXFIFORES Mask */ -#define USART0_FCR_TXFIFORES_Pos 2 /*!< USART0 FCR: TXFIFORES Position */ -#define USART0_FCR_TXFIFORES_Msk (0x01UL << USART0_FCR_TXFIFORES_Pos) /*!< USART0 FCR: TXFIFORES Mask */ -#define USART0_FCR_DMAMODE_Pos 3 /*!< USART0 FCR: DMAMODE Position */ -#define USART0_FCR_DMAMODE_Msk (0x01UL << USART0_FCR_DMAMODE_Pos) /*!< USART0 FCR: DMAMODE Mask */ -#define USART0_FCR_RXTRIGLVL_Pos 6 /*!< USART0 FCR: RXTRIGLVL Position */ -#define USART0_FCR_RXTRIGLVL_Msk (0x03UL << USART0_FCR_RXTRIGLVL_Pos) /*!< USART0 FCR: RXTRIGLVL Mask */ - -// --------------------------------------- USART0_LCR ------------------------------------------- -#define USART0_LCR_WLS_Pos 0 /*!< USART0 LCR: WLS Position */ -#define USART0_LCR_WLS_Msk (0x03UL << USART0_LCR_WLS_Pos) /*!< USART0 LCR: WLS Mask */ -#define USART0_LCR_SBS_Pos 2 /*!< USART0 LCR: SBS Position */ -#define USART0_LCR_SBS_Msk (0x01UL << USART0_LCR_SBS_Pos) /*!< USART0 LCR: SBS Mask */ -#define USART0_LCR_PE_Pos 3 /*!< USART0 LCR: PE Position */ -#define USART0_LCR_PE_Msk (0x01UL << USART0_LCR_PE_Pos) /*!< USART0 LCR: PE Mask */ -#define USART0_LCR_PS_Pos 4 /*!< USART0 LCR: PS Position */ -#define USART0_LCR_PS_Msk (0x03UL << USART0_LCR_PS_Pos) /*!< USART0 LCR: PS Mask */ -#define USART0_LCR_BC_Pos 6 /*!< USART0 LCR: BC Position */ -#define USART0_LCR_BC_Msk (0x01UL << USART0_LCR_BC_Pos) /*!< USART0 LCR: BC Mask */ -#define USART0_LCR_DLAB_Pos 7 /*!< USART0 LCR: DLAB Position */ -#define USART0_LCR_DLAB_Msk (0x01UL << USART0_LCR_DLAB_Pos) /*!< USART0 LCR: DLAB Mask */ - -// --------------------------------------- USART0_LSR ------------------------------------------- -#define USART0_LSR_RDR_Pos 0 /*!< USART0 LSR: RDR Position */ -#define USART0_LSR_RDR_Msk (0x01UL << USART0_LSR_RDR_Pos) /*!< USART0 LSR: RDR Mask */ -#define USART0_LSR_OE_Pos 1 /*!< USART0 LSR: OE Position */ -#define USART0_LSR_OE_Msk (0x01UL << USART0_LSR_OE_Pos) /*!< USART0 LSR: OE Mask */ -#define USART0_LSR_PE_Pos 2 /*!< USART0 LSR: PE Position */ -#define USART0_LSR_PE_Msk (0x01UL << USART0_LSR_PE_Pos) /*!< USART0 LSR: PE Mask */ -#define USART0_LSR_FE_Pos 3 /*!< USART0 LSR: FE Position */ -#define USART0_LSR_FE_Msk (0x01UL << USART0_LSR_FE_Pos) /*!< USART0 LSR: FE Mask */ -#define USART0_LSR_BI_Pos 4 /*!< USART0 LSR: BI Position */ -#define USART0_LSR_BI_Msk (0x01UL << USART0_LSR_BI_Pos) /*!< USART0 LSR: BI Mask */ -#define USART0_LSR_THRE_Pos 5 /*!< USART0 LSR: THRE Position */ -#define USART0_LSR_THRE_Msk (0x01UL << USART0_LSR_THRE_Pos) /*!< USART0 LSR: THRE Mask */ -#define USART0_LSR_TEMT_Pos 6 /*!< USART0 LSR: TEMT Position */ -#define USART0_LSR_TEMT_Msk (0x01UL << USART0_LSR_TEMT_Pos) /*!< USART0 LSR: TEMT Mask */ -#define USART0_LSR_RXFE_Pos 7 /*!< USART0 LSR: RXFE Position */ -#define USART0_LSR_RXFE_Msk (0x01UL << USART0_LSR_RXFE_Pos) /*!< USART0 LSR: RXFE Mask */ -#define USART0_LSR_TXERR_Pos 8 /*!< USART0 LSR: TXERR Position */ -#define USART0_LSR_TXERR_Msk (0x01UL << USART0_LSR_TXERR_Pos) /*!< USART0 LSR: TXERR Mask */ - -// --------------------------------------- USART0_SCR ------------------------------------------- -#define USART0_SCR_PAD_Pos 0 /*!< USART0 SCR: PAD Position */ -#define USART0_SCR_PAD_Msk (0x000000ffUL << USART0_SCR_PAD_Pos) /*!< USART0 SCR: PAD Mask */ - -// --------------------------------------- USART0_ACR ------------------------------------------- -#define USART0_ACR_START_Pos 0 /*!< USART0 ACR: START Position */ -#define USART0_ACR_START_Msk (0x01UL << USART0_ACR_START_Pos) /*!< USART0 ACR: START Mask */ -#define USART0_ACR_MODE_Pos 1 /*!< USART0 ACR: MODE Position */ -#define USART0_ACR_MODE_Msk (0x01UL << USART0_ACR_MODE_Pos) /*!< USART0 ACR: MODE Mask */ -#define USART0_ACR_AUTORESTART_Pos 2 /*!< USART0 ACR: AUTORESTART Position */ -#define USART0_ACR_AUTORESTART_Msk (0x01UL << USART0_ACR_AUTORESTART_Pos) /*!< USART0 ACR: AUTORESTART Mask */ -#define USART0_ACR_ABEOINTCLR_Pos 8 /*!< USART0 ACR: ABEOINTCLR Position */ -#define USART0_ACR_ABEOINTCLR_Msk (0x01UL << USART0_ACR_ABEOINTCLR_Pos) /*!< USART0 ACR: ABEOINTCLR Mask */ -#define USART0_ACR_ABTOINTCLR_Pos 9 /*!< USART0 ACR: ABTOINTCLR Position */ -#define USART0_ACR_ABTOINTCLR_Msk (0x01UL << USART0_ACR_ABTOINTCLR_Pos) /*!< USART0 ACR: ABTOINTCLR Mask */ - -// --------------------------------------- USART0_ICR ------------------------------------------- -#define USART0_ICR_IRDAEN_Pos 0 /*!< USART0 ICR: IRDAEN Position */ -#define USART0_ICR_IRDAEN_Msk (0x01UL << USART0_ICR_IRDAEN_Pos) /*!< USART0 ICR: IRDAEN Mask */ -#define USART0_ICR_IRDAINV_Pos 1 /*!< USART0 ICR: IRDAINV Position */ -#define USART0_ICR_IRDAINV_Msk (0x01UL << USART0_ICR_IRDAINV_Pos) /*!< USART0 ICR: IRDAINV Mask */ -#define USART0_ICR_FIXPULSEEN_Pos 2 /*!< USART0 ICR: FIXPULSEEN Position */ -#define USART0_ICR_FIXPULSEEN_Msk (0x01UL << USART0_ICR_FIXPULSEEN_Pos) /*!< USART0 ICR: FIXPULSEEN Mask */ -#define USART0_ICR_PULSEDIV_Pos 3 /*!< USART0 ICR: PULSEDIV Position */ -#define USART0_ICR_PULSEDIV_Msk (0x07UL << USART0_ICR_PULSEDIV_Pos) /*!< USART0 ICR: PULSEDIV Mask */ - -// --------------------------------------- USART0_FDR ------------------------------------------- -#define USART0_FDR_DIVADDVAL_Pos 0 /*!< USART0 FDR: DIVADDVAL Position */ -#define USART0_FDR_DIVADDVAL_Msk (0x0fUL << USART0_FDR_DIVADDVAL_Pos) /*!< USART0 FDR: DIVADDVAL Mask */ -#define USART0_FDR_MULVAL_Pos 4 /*!< USART0 FDR: MULVAL Position */ -#define USART0_FDR_MULVAL_Msk (0x0fUL << USART0_FDR_MULVAL_Pos) /*!< USART0 FDR: MULVAL Mask */ - -// --------------------------------------- USART0_OSR ------------------------------------------- -#define USART0_OSR_OSFRAC_Pos 1 /*!< USART0 OSR: OSFRAC Position */ -#define USART0_OSR_OSFRAC_Msk (0x07UL << USART0_OSR_OSFRAC_Pos) /*!< USART0 OSR: OSFRAC Mask */ -#define USART0_OSR_OSINT_Pos 4 /*!< USART0 OSR: OSINT Position */ -#define USART0_OSR_OSINT_Msk (0x0fUL << USART0_OSR_OSINT_Pos) /*!< USART0 OSR: OSINT Mask */ -#define USART0_OSR_FDINT_Pos 8 /*!< USART0 OSR: FDINT Position */ -#define USART0_OSR_FDINT_Msk (0x7fUL << USART0_OSR_FDINT_Pos) /*!< USART0 OSR: FDINT Mask */ - -// --------------------------------------- USART0_HDEN ------------------------------------------ -#define USART0_HDEN_HDEN_Pos 0 /*!< USART0 HDEN: HDEN Position */ -#define USART0_HDEN_HDEN_Msk (0x01UL << USART0_HDEN_HDEN_Pos) /*!< USART0 HDEN: HDEN Mask */ - -// ------------------------------------- USART0_SCICTRL ----------------------------------------- -#define USART0_SCICTRL_SCIEN_Pos 0 /*!< USART0 SCICTRL: SCIEN Position */ -#define USART0_SCICTRL_SCIEN_Msk (0x01UL << USART0_SCICTRL_SCIEN_Pos) /*!< USART0 SCICTRL: SCIEN Mask */ -#define USART0_SCICTRL_NACKDIS_Pos 1 /*!< USART0 SCICTRL: NACKDIS Position */ -#define USART0_SCICTRL_NACKDIS_Msk (0x01UL << USART0_SCICTRL_NACKDIS_Pos) /*!< USART0 SCICTRL: NACKDIS Mask */ -#define USART0_SCICTRL_PROTSEL_Pos 2 /*!< USART0 SCICTRL: PROTSEL Position */ -#define USART0_SCICTRL_PROTSEL_Msk (0x01UL << USART0_SCICTRL_PROTSEL_Pos) /*!< USART0 SCICTRL: PROTSEL Mask */ -#define USART0_SCICTRL_TXRETRY_Pos 5 /*!< USART0 SCICTRL: TXRETRY Position */ -#define USART0_SCICTRL_TXRETRY_Msk (0x07UL << USART0_SCICTRL_TXRETRY_Pos) /*!< USART0 SCICTRL: TXRETRY Mask */ -#define USART0_SCICTRL_GUARDTIME_Pos 8 /*!< USART0 SCICTRL: GUARDTIME Position */ -#define USART0_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USART0_SCICTRL_GUARDTIME_Pos) /*!< USART0 SCICTRL: GUARDTIME Mask */ - -// ------------------------------------ USART0_RS485CTRL ---------------------------------------- -#define USART0_RS485CTRL_NMMEN_Pos 0 /*!< USART0 RS485CTRL: NMMEN Position */ -#define USART0_RS485CTRL_NMMEN_Msk (0x01UL << USART0_RS485CTRL_NMMEN_Pos) /*!< USART0 RS485CTRL: NMMEN Mask */ -#define USART0_RS485CTRL_RXDIS_Pos 1 /*!< USART0 RS485CTRL: RXDIS Position */ -#define USART0_RS485CTRL_RXDIS_Msk (0x01UL << USART0_RS485CTRL_RXDIS_Pos) /*!< USART0 RS485CTRL: RXDIS Mask */ -#define USART0_RS485CTRL_AADEN_Pos 2 /*!< USART0 RS485CTRL: AADEN Position */ -#define USART0_RS485CTRL_AADEN_Msk (0x01UL << USART0_RS485CTRL_AADEN_Pos) /*!< USART0 RS485CTRL: AADEN Mask */ -#define USART0_RS485CTRL_DCTRL_Pos 4 /*!< USART0 RS485CTRL: DCTRL Position */ -#define USART0_RS485CTRL_DCTRL_Msk (0x01UL << USART0_RS485CTRL_DCTRL_Pos) /*!< USART0 RS485CTRL: DCTRL Mask */ -#define USART0_RS485CTRL_OINV_Pos 5 /*!< USART0 RS485CTRL: OINV Position */ -#define USART0_RS485CTRL_OINV_Msk (0x01UL << USART0_RS485CTRL_OINV_Pos) /*!< USART0 RS485CTRL: OINV Mask */ - -// ---------------------------------- USART0_RS485ADRMATCH -------------------------------------- -#define USART0_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USART0 RS485ADRMATCH: ADRMATCH Position */ -#define USART0_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USART0_RS485ADRMATCH_ADRMATCH_Pos) /*!< USART0 RS485ADRMATCH: ADRMATCH Mask */ - -// ------------------------------------- USART0_RS485DLY ---------------------------------------- -#define USART0_RS485DLY_DLY_Pos 0 /*!< USART0 RS485DLY: DLY Position */ -#define USART0_RS485DLY_DLY_Msk (0x000000ffUL << USART0_RS485DLY_DLY_Pos) /*!< USART0 RS485DLY: DLY Mask */ - -// ------------------------------------- USART0_SYNCCTRL ---------------------------------------- -#define USART0_SYNCCTRL_SYNC_Pos 0 /*!< USART0 SYNCCTRL: SYNC Position */ -#define USART0_SYNCCTRL_SYNC_Msk (0x01UL << USART0_SYNCCTRL_SYNC_Pos) /*!< USART0 SYNCCTRL: SYNC Mask */ -#define USART0_SYNCCTRL_CSRC_Pos 1 /*!< USART0 SYNCCTRL: CSRC Position */ -#define USART0_SYNCCTRL_CSRC_Msk (0x01UL << USART0_SYNCCTRL_CSRC_Pos) /*!< USART0 SYNCCTRL: CSRC Mask */ -#define USART0_SYNCCTRL_FES_Pos 2 /*!< USART0 SYNCCTRL: FES Position */ -#define USART0_SYNCCTRL_FES_Msk (0x01UL << USART0_SYNCCTRL_FES_Pos) /*!< USART0 SYNCCTRL: FES Mask */ -#define USART0_SYNCCTRL_TSBYPASS_Pos 3 /*!< USART0 SYNCCTRL: TSBYPASS Position */ -#define USART0_SYNCCTRL_TSBYPASS_Msk (0x01UL << USART0_SYNCCTRL_TSBYPASS_Pos) /*!< USART0 SYNCCTRL: TSBYPASS Mask */ -#define USART0_SYNCCTRL_CSCEN_Pos 4 /*!< USART0 SYNCCTRL: CSCEN Position */ -#define USART0_SYNCCTRL_CSCEN_Msk (0x01UL << USART0_SYNCCTRL_CSCEN_Pos) /*!< USART0 SYNCCTRL: CSCEN Mask */ -#define USART0_SYNCCTRL_SSSDIS_Pos 5 /*!< USART0 SYNCCTRL: SSSDIS Position */ -#define USART0_SYNCCTRL_SSSDIS_Msk (0x01UL << USART0_SYNCCTRL_SSSDIS_Pos) /*!< USART0 SYNCCTRL: SSSDIS Mask */ -#define USART0_SYNCCTRL_CCCLR_Pos 6 /*!< USART0 SYNCCTRL: CCCLR Position */ -#define USART0_SYNCCTRL_CCCLR_Msk (0x01UL << USART0_SYNCCTRL_CCCLR_Pos) /*!< USART0 SYNCCTRL: CCCLR Mask */ - -// --------------------------------------- USART0_TER ------------------------------------------- -#define USART0_TER_TXEN_Pos 0 /*!< USART0 TER: TXEN Position */ -#define USART0_TER_TXEN_Msk (0x01UL << USART0_TER_TXEN_Pos) /*!< USART0 TER: TXEN Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- USART2 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- USART2_DLL ------------------------------------------- -#define USART2_DLL_DLLSB_Pos 0 /*!< USART2 DLL: DLLSB Position */ -#define USART2_DLL_DLLSB_Msk (0x000000ffUL << USART2_DLL_DLLSB_Pos) /*!< USART2 DLL: DLLSB Mask */ - -// --------------------------------------- USART2_THR ------------------------------------------- -#define USART2_THR_THR_Pos 0 /*!< USART2 THR: THR Position */ -#define USART2_THR_THR_Msk (0x000000ffUL << USART2_THR_THR_Pos) /*!< USART2 THR: THR Mask */ - -// --------------------------------------- USART2_RBR ------------------------------------------- -#define USART2_RBR_RBR_Pos 0 /*!< USART2 RBR: RBR Position */ -#define USART2_RBR_RBR_Msk (0x000000ffUL << USART2_RBR_RBR_Pos) /*!< USART2 RBR: RBR Mask */ - -// --------------------------------------- USART2_IER ------------------------------------------- -#define USART2_IER_RBRIE_Pos 0 /*!< USART2 IER: RBRIE Position */ -#define USART2_IER_RBRIE_Msk (0x01UL << USART2_IER_RBRIE_Pos) /*!< USART2 IER: RBRIE Mask */ -#define USART2_IER_THREIE_Pos 1 /*!< USART2 IER: THREIE Position */ -#define USART2_IER_THREIE_Msk (0x01UL << USART2_IER_THREIE_Pos) /*!< USART2 IER: THREIE Mask */ -#define USART2_IER_RXIE_Pos 2 /*!< USART2 IER: RXIE Position */ -#define USART2_IER_RXIE_Msk (0x01UL << USART2_IER_RXIE_Pos) /*!< USART2 IER: RXIE Mask */ -#define USART2_IER_ABEOINTEN_Pos 8 /*!< USART2 IER: ABEOINTEN Position */ -#define USART2_IER_ABEOINTEN_Msk (0x01UL << USART2_IER_ABEOINTEN_Pos) /*!< USART2 IER: ABEOINTEN Mask */ -#define USART2_IER_ABTOINTEN_Pos 9 /*!< USART2 IER: ABTOINTEN Position */ -#define USART2_IER_ABTOINTEN_Msk (0x01UL << USART2_IER_ABTOINTEN_Pos) /*!< USART2 IER: ABTOINTEN Mask */ - -// --------------------------------------- USART2_DLM ------------------------------------------- -#define USART2_DLM_DLMSB_Pos 0 /*!< USART2 DLM: DLMSB Position */ -#define USART2_DLM_DLMSB_Msk (0x000000ffUL << USART2_DLM_DLMSB_Pos) /*!< USART2 DLM: DLMSB Mask */ - -// --------------------------------------- USART2_FCR ------------------------------------------- -#define USART2_FCR_FIFOEN_Pos 0 /*!< USART2 FCR: FIFOEN Position */ -#define USART2_FCR_FIFOEN_Msk (0x01UL << USART2_FCR_FIFOEN_Pos) /*!< USART2 FCR: FIFOEN Mask */ -#define USART2_FCR_RXFIFORES_Pos 1 /*!< USART2 FCR: RXFIFORES Position */ -#define USART2_FCR_RXFIFORES_Msk (0x01UL << USART2_FCR_RXFIFORES_Pos) /*!< USART2 FCR: RXFIFORES Mask */ -#define USART2_FCR_TXFIFORES_Pos 2 /*!< USART2 FCR: TXFIFORES Position */ -#define USART2_FCR_TXFIFORES_Msk (0x01UL << USART2_FCR_TXFIFORES_Pos) /*!< USART2 FCR: TXFIFORES Mask */ -#define USART2_FCR_DMAMODE_Pos 3 /*!< USART2 FCR: DMAMODE Position */ -#define USART2_FCR_DMAMODE_Msk (0x01UL << USART2_FCR_DMAMODE_Pos) /*!< USART2 FCR: DMAMODE Mask */ -#define USART2_FCR_RXTRIGLVL_Pos 6 /*!< USART2 FCR: RXTRIGLVL Position */ -#define USART2_FCR_RXTRIGLVL_Msk (0x03UL << USART2_FCR_RXTRIGLVL_Pos) /*!< USART2 FCR: RXTRIGLVL Mask */ - -// --------------------------------------- USART2_IIR ------------------------------------------- -#define USART2_IIR_INTSTATUS_Pos 0 /*!< USART2 IIR: INTSTATUS Position */ -#define USART2_IIR_INTSTATUS_Msk (0x01UL << USART2_IIR_INTSTATUS_Pos) /*!< USART2 IIR: INTSTATUS Mask */ -#define USART2_IIR_INTID_Pos 1 /*!< USART2 IIR: INTID Position */ -#define USART2_IIR_INTID_Msk (0x07UL << USART2_IIR_INTID_Pos) /*!< USART2 IIR: INTID Mask */ -#define USART2_IIR_FIFOENABLE_Pos 6 /*!< USART2 IIR: FIFOENABLE Position */ -#define USART2_IIR_FIFOENABLE_Msk (0x03UL << USART2_IIR_FIFOENABLE_Pos) /*!< USART2 IIR: FIFOENABLE Mask */ -#define USART2_IIR_ABEOINT_Pos 8 /*!< USART2 IIR: ABEOINT Position */ -#define USART2_IIR_ABEOINT_Msk (0x01UL << USART2_IIR_ABEOINT_Pos) /*!< USART2 IIR: ABEOINT Mask */ -#define USART2_IIR_ABTOINT_Pos 9 /*!< USART2 IIR: ABTOINT Position */ -#define USART2_IIR_ABTOINT_Msk (0x01UL << USART2_IIR_ABTOINT_Pos) /*!< USART2 IIR: ABTOINT Mask */ - -// --------------------------------------- USART2_LCR ------------------------------------------- -#define USART2_LCR_WLS_Pos 0 /*!< USART2 LCR: WLS Position */ -#define USART2_LCR_WLS_Msk (0x03UL << USART2_LCR_WLS_Pos) /*!< USART2 LCR: WLS Mask */ -#define USART2_LCR_SBS_Pos 2 /*!< USART2 LCR: SBS Position */ -#define USART2_LCR_SBS_Msk (0x01UL << USART2_LCR_SBS_Pos) /*!< USART2 LCR: SBS Mask */ -#define USART2_LCR_PE_Pos 3 /*!< USART2 LCR: PE Position */ -#define USART2_LCR_PE_Msk (0x01UL << USART2_LCR_PE_Pos) /*!< USART2 LCR: PE Mask */ -#define USART2_LCR_PS_Pos 4 /*!< USART2 LCR: PS Position */ -#define USART2_LCR_PS_Msk (0x03UL << USART2_LCR_PS_Pos) /*!< USART2 LCR: PS Mask */ -#define USART2_LCR_BC_Pos 6 /*!< USART2 LCR: BC Position */ -#define USART2_LCR_BC_Msk (0x01UL << USART2_LCR_BC_Pos) /*!< USART2 LCR: BC Mask */ -#define USART2_LCR_DLAB_Pos 7 /*!< USART2 LCR: DLAB Position */ -#define USART2_LCR_DLAB_Msk (0x01UL << USART2_LCR_DLAB_Pos) /*!< USART2 LCR: DLAB Mask */ - -// --------------------------------------- USART2_LSR ------------------------------------------- -#define USART2_LSR_RDR_Pos 0 /*!< USART2 LSR: RDR Position */ -#define USART2_LSR_RDR_Msk (0x01UL << USART2_LSR_RDR_Pos) /*!< USART2 LSR: RDR Mask */ -#define USART2_LSR_OE_Pos 1 /*!< USART2 LSR: OE Position */ -#define USART2_LSR_OE_Msk (0x01UL << USART2_LSR_OE_Pos) /*!< USART2 LSR: OE Mask */ -#define USART2_LSR_PE_Pos 2 /*!< USART2 LSR: PE Position */ -#define USART2_LSR_PE_Msk (0x01UL << USART2_LSR_PE_Pos) /*!< USART2 LSR: PE Mask */ -#define USART2_LSR_FE_Pos 3 /*!< USART2 LSR: FE Position */ -#define USART2_LSR_FE_Msk (0x01UL << USART2_LSR_FE_Pos) /*!< USART2 LSR: FE Mask */ -#define USART2_LSR_BI_Pos 4 /*!< USART2 LSR: BI Position */ -#define USART2_LSR_BI_Msk (0x01UL << USART2_LSR_BI_Pos) /*!< USART2 LSR: BI Mask */ -#define USART2_LSR_THRE_Pos 5 /*!< USART2 LSR: THRE Position */ -#define USART2_LSR_THRE_Msk (0x01UL << USART2_LSR_THRE_Pos) /*!< USART2 LSR: THRE Mask */ -#define USART2_LSR_TEMT_Pos 6 /*!< USART2 LSR: TEMT Position */ -#define USART2_LSR_TEMT_Msk (0x01UL << USART2_LSR_TEMT_Pos) /*!< USART2 LSR: TEMT Mask */ -#define USART2_LSR_RXFE_Pos 7 /*!< USART2 LSR: RXFE Position */ -#define USART2_LSR_RXFE_Msk (0x01UL << USART2_LSR_RXFE_Pos) /*!< USART2 LSR: RXFE Mask */ -#define USART2_LSR_TXERR_Pos 8 /*!< USART2 LSR: TXERR Position */ -#define USART2_LSR_TXERR_Msk (0x01UL << USART2_LSR_TXERR_Pos) /*!< USART2 LSR: TXERR Mask */ - -// --------------------------------------- USART2_SCR ------------------------------------------- -#define USART2_SCR_PAD_Pos 0 /*!< USART2 SCR: PAD Position */ -#define USART2_SCR_PAD_Msk (0x000000ffUL << USART2_SCR_PAD_Pos) /*!< USART2 SCR: PAD Mask */ - -// --------------------------------------- USART2_ACR ------------------------------------------- -#define USART2_ACR_START_Pos 0 /*!< USART2 ACR: START Position */ -#define USART2_ACR_START_Msk (0x01UL << USART2_ACR_START_Pos) /*!< USART2 ACR: START Mask */ -#define USART2_ACR_MODE_Pos 1 /*!< USART2 ACR: MODE Position */ -#define USART2_ACR_MODE_Msk (0x01UL << USART2_ACR_MODE_Pos) /*!< USART2 ACR: MODE Mask */ -#define USART2_ACR_AUTORESTART_Pos 2 /*!< USART2 ACR: AUTORESTART Position */ -#define USART2_ACR_AUTORESTART_Msk (0x01UL << USART2_ACR_AUTORESTART_Pos) /*!< USART2 ACR: AUTORESTART Mask */ -#define USART2_ACR_ABEOINTCLR_Pos 8 /*!< USART2 ACR: ABEOINTCLR Position */ -#define USART2_ACR_ABEOINTCLR_Msk (0x01UL << USART2_ACR_ABEOINTCLR_Pos) /*!< USART2 ACR: ABEOINTCLR Mask */ -#define USART2_ACR_ABTOINTCLR_Pos 9 /*!< USART2 ACR: ABTOINTCLR Position */ -#define USART2_ACR_ABTOINTCLR_Msk (0x01UL << USART2_ACR_ABTOINTCLR_Pos) /*!< USART2 ACR: ABTOINTCLR Mask */ - -// --------------------------------------- USART2_ICR ------------------------------------------- -#define USART2_ICR_IRDAEN_Pos 0 /*!< USART2 ICR: IRDAEN Position */ -#define USART2_ICR_IRDAEN_Msk (0x01UL << USART2_ICR_IRDAEN_Pos) /*!< USART2 ICR: IRDAEN Mask */ -#define USART2_ICR_IRDAINV_Pos 1 /*!< USART2 ICR: IRDAINV Position */ -#define USART2_ICR_IRDAINV_Msk (0x01UL << USART2_ICR_IRDAINV_Pos) /*!< USART2 ICR: IRDAINV Mask */ -#define USART2_ICR_FIXPULSEEN_Pos 2 /*!< USART2 ICR: FIXPULSEEN Position */ -#define USART2_ICR_FIXPULSEEN_Msk (0x01UL << USART2_ICR_FIXPULSEEN_Pos) /*!< USART2 ICR: FIXPULSEEN Mask */ -#define USART2_ICR_PULSEDIV_Pos 3 /*!< USART2 ICR: PULSEDIV Position */ -#define USART2_ICR_PULSEDIV_Msk (0x07UL << USART2_ICR_PULSEDIV_Pos) /*!< USART2 ICR: PULSEDIV Mask */ - -// --------------------------------------- USART2_FDR ------------------------------------------- -#define USART2_FDR_DIVADDVAL_Pos 0 /*!< USART2 FDR: DIVADDVAL Position */ -#define USART2_FDR_DIVADDVAL_Msk (0x0fUL << USART2_FDR_DIVADDVAL_Pos) /*!< USART2 FDR: DIVADDVAL Mask */ -#define USART2_FDR_MULVAL_Pos 4 /*!< USART2 FDR: MULVAL Position */ -#define USART2_FDR_MULVAL_Msk (0x0fUL << USART2_FDR_MULVAL_Pos) /*!< USART2 FDR: MULVAL Mask */ - -// --------------------------------------- USART2_OSR ------------------------------------------- -#define USART2_OSR_OSFRAC_Pos 1 /*!< USART2 OSR: OSFRAC Position */ -#define USART2_OSR_OSFRAC_Msk (0x07UL << USART2_OSR_OSFRAC_Pos) /*!< USART2 OSR: OSFRAC Mask */ -#define USART2_OSR_OSINT_Pos 4 /*!< USART2 OSR: OSINT Position */ -#define USART2_OSR_OSINT_Msk (0x0fUL << USART2_OSR_OSINT_Pos) /*!< USART2 OSR: OSINT Mask */ -#define USART2_OSR_FDINT_Pos 8 /*!< USART2 OSR: FDINT Position */ -#define USART2_OSR_FDINT_Msk (0x7fUL << USART2_OSR_FDINT_Pos) /*!< USART2 OSR: FDINT Mask */ - -// --------------------------------------- USART2_HDEN ------------------------------------------ -#define USART2_HDEN_HDEN_Pos 0 /*!< USART2 HDEN: HDEN Position */ -#define USART2_HDEN_HDEN_Msk (0x01UL << USART2_HDEN_HDEN_Pos) /*!< USART2 HDEN: HDEN Mask */ - -// ------------------------------------- USART2_SCICTRL ----------------------------------------- -#define USART2_SCICTRL_SCIEN_Pos 0 /*!< USART2 SCICTRL: SCIEN Position */ -#define USART2_SCICTRL_SCIEN_Msk (0x01UL << USART2_SCICTRL_SCIEN_Pos) /*!< USART2 SCICTRL: SCIEN Mask */ -#define USART2_SCICTRL_NACKDIS_Pos 1 /*!< USART2 SCICTRL: NACKDIS Position */ -#define USART2_SCICTRL_NACKDIS_Msk (0x01UL << USART2_SCICTRL_NACKDIS_Pos) /*!< USART2 SCICTRL: NACKDIS Mask */ -#define USART2_SCICTRL_PROTSEL_Pos 2 /*!< USART2 SCICTRL: PROTSEL Position */ -#define USART2_SCICTRL_PROTSEL_Msk (0x01UL << USART2_SCICTRL_PROTSEL_Pos) /*!< USART2 SCICTRL: PROTSEL Mask */ -#define USART2_SCICTRL_TXRETRY_Pos 5 /*!< USART2 SCICTRL: TXRETRY Position */ -#define USART2_SCICTRL_TXRETRY_Msk (0x07UL << USART2_SCICTRL_TXRETRY_Pos) /*!< USART2 SCICTRL: TXRETRY Mask */ -#define USART2_SCICTRL_GUARDTIME_Pos 8 /*!< USART2 SCICTRL: GUARDTIME Position */ -#define USART2_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USART2_SCICTRL_GUARDTIME_Pos) /*!< USART2 SCICTRL: GUARDTIME Mask */ - -// ------------------------------------ USART2_RS485CTRL ---------------------------------------- -#define USART2_RS485CTRL_NMMEN_Pos 0 /*!< USART2 RS485CTRL: NMMEN Position */ -#define USART2_RS485CTRL_NMMEN_Msk (0x01UL << USART2_RS485CTRL_NMMEN_Pos) /*!< USART2 RS485CTRL: NMMEN Mask */ -#define USART2_RS485CTRL_RXDIS_Pos 1 /*!< USART2 RS485CTRL: RXDIS Position */ -#define USART2_RS485CTRL_RXDIS_Msk (0x01UL << USART2_RS485CTRL_RXDIS_Pos) /*!< USART2 RS485CTRL: RXDIS Mask */ -#define USART2_RS485CTRL_AADEN_Pos 2 /*!< USART2 RS485CTRL: AADEN Position */ -#define USART2_RS485CTRL_AADEN_Msk (0x01UL << USART2_RS485CTRL_AADEN_Pos) /*!< USART2 RS485CTRL: AADEN Mask */ -#define USART2_RS485CTRL_DCTRL_Pos 4 /*!< USART2 RS485CTRL: DCTRL Position */ -#define USART2_RS485CTRL_DCTRL_Msk (0x01UL << USART2_RS485CTRL_DCTRL_Pos) /*!< USART2 RS485CTRL: DCTRL Mask */ -#define USART2_RS485CTRL_OINV_Pos 5 /*!< USART2 RS485CTRL: OINV Position */ -#define USART2_RS485CTRL_OINV_Msk (0x01UL << USART2_RS485CTRL_OINV_Pos) /*!< USART2 RS485CTRL: OINV Mask */ - -// ---------------------------------- USART2_RS485ADRMATCH -------------------------------------- -#define USART2_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USART2 RS485ADRMATCH: ADRMATCH Position */ -#define USART2_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USART2_RS485ADRMATCH_ADRMATCH_Pos) /*!< USART2 RS485ADRMATCH: ADRMATCH Mask */ - -// ------------------------------------- USART2_RS485DLY ---------------------------------------- -#define USART2_RS485DLY_DLY_Pos 0 /*!< USART2 RS485DLY: DLY Position */ -#define USART2_RS485DLY_DLY_Msk (0x000000ffUL << USART2_RS485DLY_DLY_Pos) /*!< USART2 RS485DLY: DLY Mask */ - -// ------------------------------------- USART2_SYNCCTRL ---------------------------------------- -#define USART2_SYNCCTRL_SYNC_Pos 0 /*!< USART2 SYNCCTRL: SYNC Position */ -#define USART2_SYNCCTRL_SYNC_Msk (0x01UL << USART2_SYNCCTRL_SYNC_Pos) /*!< USART2 SYNCCTRL: SYNC Mask */ -#define USART2_SYNCCTRL_CSRC_Pos 1 /*!< USART2 SYNCCTRL: CSRC Position */ -#define USART2_SYNCCTRL_CSRC_Msk (0x01UL << USART2_SYNCCTRL_CSRC_Pos) /*!< USART2 SYNCCTRL: CSRC Mask */ -#define USART2_SYNCCTRL_FES_Pos 2 /*!< USART2 SYNCCTRL: FES Position */ -#define USART2_SYNCCTRL_FES_Msk (0x01UL << USART2_SYNCCTRL_FES_Pos) /*!< USART2 SYNCCTRL: FES Mask */ -#define USART2_SYNCCTRL_TSBYPASS_Pos 3 /*!< USART2 SYNCCTRL: TSBYPASS Position */ -#define USART2_SYNCCTRL_TSBYPASS_Msk (0x01UL << USART2_SYNCCTRL_TSBYPASS_Pos) /*!< USART2 SYNCCTRL: TSBYPASS Mask */ -#define USART2_SYNCCTRL_CSCEN_Pos 4 /*!< USART2 SYNCCTRL: CSCEN Position */ -#define USART2_SYNCCTRL_CSCEN_Msk (0x01UL << USART2_SYNCCTRL_CSCEN_Pos) /*!< USART2 SYNCCTRL: CSCEN Mask */ -#define USART2_SYNCCTRL_SSSDIS_Pos 5 /*!< USART2 SYNCCTRL: SSSDIS Position */ -#define USART2_SYNCCTRL_SSSDIS_Msk (0x01UL << USART2_SYNCCTRL_SSSDIS_Pos) /*!< USART2 SYNCCTRL: SSSDIS Mask */ -#define USART2_SYNCCTRL_CCCLR_Pos 6 /*!< USART2 SYNCCTRL: CCCLR Position */ -#define USART2_SYNCCTRL_CCCLR_Msk (0x01UL << USART2_SYNCCTRL_CCCLR_Pos) /*!< USART2 SYNCCTRL: CCCLR Mask */ - -// --------------------------------------- USART2_TER ------------------------------------------- -#define USART2_TER_TXEN_Pos 0 /*!< USART2 TER: TXEN Position */ -#define USART2_TER_TXEN_Msk (0x01UL << USART2_TER_TXEN_Pos) /*!< USART2 TER: TXEN Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- USART3 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- USART3_DLL ------------------------------------------- -#define USART3_DLL_DLLSB_Pos 0 /*!< USART3 DLL: DLLSB Position */ -#define USART3_DLL_DLLSB_Msk (0x000000ffUL << USART3_DLL_DLLSB_Pos) /*!< USART3 DLL: DLLSB Mask */ - -// --------------------------------------- USART3_THR ------------------------------------------- -#define USART3_THR_THR_Pos 0 /*!< USART3 THR: THR Position */ -#define USART3_THR_THR_Msk (0x000000ffUL << USART3_THR_THR_Pos) /*!< USART3 THR: THR Mask */ - -// --------------------------------------- USART3_RBR ------------------------------------------- -#define USART3_RBR_RBR_Pos 0 /*!< USART3 RBR: RBR Position */ -#define USART3_RBR_RBR_Msk (0x000000ffUL << USART3_RBR_RBR_Pos) /*!< USART3 RBR: RBR Mask */ - -// --------------------------------------- USART3_IER ------------------------------------------- -#define USART3_IER_RBRIE_Pos 0 /*!< USART3 IER: RBRIE Position */ -#define USART3_IER_RBRIE_Msk (0x01UL << USART3_IER_RBRIE_Pos) /*!< USART3 IER: RBRIE Mask */ -#define USART3_IER_THREIE_Pos 1 /*!< USART3 IER: THREIE Position */ -#define USART3_IER_THREIE_Msk (0x01UL << USART3_IER_THREIE_Pos) /*!< USART3 IER: THREIE Mask */ -#define USART3_IER_RXIE_Pos 2 /*!< USART3 IER: RXIE Position */ -#define USART3_IER_RXIE_Msk (0x01UL << USART3_IER_RXIE_Pos) /*!< USART3 IER: RXIE Mask */ -#define USART3_IER_ABEOINTEN_Pos 8 /*!< USART3 IER: ABEOINTEN Position */ -#define USART3_IER_ABEOINTEN_Msk (0x01UL << USART3_IER_ABEOINTEN_Pos) /*!< USART3 IER: ABEOINTEN Mask */ -#define USART3_IER_ABTOINTEN_Pos 9 /*!< USART3 IER: ABTOINTEN Position */ -#define USART3_IER_ABTOINTEN_Msk (0x01UL << USART3_IER_ABTOINTEN_Pos) /*!< USART3 IER: ABTOINTEN Mask */ - -// --------------------------------------- USART3_DLM ------------------------------------------- -#define USART3_DLM_DLMSB_Pos 0 /*!< USART3 DLM: DLMSB Position */ -#define USART3_DLM_DLMSB_Msk (0x000000ffUL << USART3_DLM_DLMSB_Pos) /*!< USART3 DLM: DLMSB Mask */ - -// --------------------------------------- USART3_FCR ------------------------------------------- -#define USART3_FCR_FIFOEN_Pos 0 /*!< USART3 FCR: FIFOEN Position */ -#define USART3_FCR_FIFOEN_Msk (0x01UL << USART3_FCR_FIFOEN_Pos) /*!< USART3 FCR: FIFOEN Mask */ -#define USART3_FCR_RXFIFORES_Pos 1 /*!< USART3 FCR: RXFIFORES Position */ -#define USART3_FCR_RXFIFORES_Msk (0x01UL << USART3_FCR_RXFIFORES_Pos) /*!< USART3 FCR: RXFIFORES Mask */ -#define USART3_FCR_TXFIFORES_Pos 2 /*!< USART3 FCR: TXFIFORES Position */ -#define USART3_FCR_TXFIFORES_Msk (0x01UL << USART3_FCR_TXFIFORES_Pos) /*!< USART3 FCR: TXFIFORES Mask */ -#define USART3_FCR_DMAMODE_Pos 3 /*!< USART3 FCR: DMAMODE Position */ -#define USART3_FCR_DMAMODE_Msk (0x01UL << USART3_FCR_DMAMODE_Pos) /*!< USART3 FCR: DMAMODE Mask */ -#define USART3_FCR_RXTRIGLVL_Pos 6 /*!< USART3 FCR: RXTRIGLVL Position */ -#define USART3_FCR_RXTRIGLVL_Msk (0x03UL << USART3_FCR_RXTRIGLVL_Pos) /*!< USART3 FCR: RXTRIGLVL Mask */ - -// --------------------------------------- USART3_IIR ------------------------------------------- -#define USART3_IIR_INTSTATUS_Pos 0 /*!< USART3 IIR: INTSTATUS Position */ -#define USART3_IIR_INTSTATUS_Msk (0x01UL << USART3_IIR_INTSTATUS_Pos) /*!< USART3 IIR: INTSTATUS Mask */ -#define USART3_IIR_INTID_Pos 1 /*!< USART3 IIR: INTID Position */ -#define USART3_IIR_INTID_Msk (0x07UL << USART3_IIR_INTID_Pos) /*!< USART3 IIR: INTID Mask */ -#define USART3_IIR_FIFOENABLE_Pos 6 /*!< USART3 IIR: FIFOENABLE Position */ -#define USART3_IIR_FIFOENABLE_Msk (0x03UL << USART3_IIR_FIFOENABLE_Pos) /*!< USART3 IIR: FIFOENABLE Mask */ -#define USART3_IIR_ABEOINT_Pos 8 /*!< USART3 IIR: ABEOINT Position */ -#define USART3_IIR_ABEOINT_Msk (0x01UL << USART3_IIR_ABEOINT_Pos) /*!< USART3 IIR: ABEOINT Mask */ -#define USART3_IIR_ABTOINT_Pos 9 /*!< USART3 IIR: ABTOINT Position */ -#define USART3_IIR_ABTOINT_Msk (0x01UL << USART3_IIR_ABTOINT_Pos) /*!< USART3 IIR: ABTOINT Mask */ - -// --------------------------------------- USART3_LCR ------------------------------------------- -#define USART3_LCR_WLS_Pos 0 /*!< USART3 LCR: WLS Position */ -#define USART3_LCR_WLS_Msk (0x03UL << USART3_LCR_WLS_Pos) /*!< USART3 LCR: WLS Mask */ -#define USART3_LCR_SBS_Pos 2 /*!< USART3 LCR: SBS Position */ -#define USART3_LCR_SBS_Msk (0x01UL << USART3_LCR_SBS_Pos) /*!< USART3 LCR: SBS Mask */ -#define USART3_LCR_PE_Pos 3 /*!< USART3 LCR: PE Position */ -#define USART3_LCR_PE_Msk (0x01UL << USART3_LCR_PE_Pos) /*!< USART3 LCR: PE Mask */ -#define USART3_LCR_PS_Pos 4 /*!< USART3 LCR: PS Position */ -#define USART3_LCR_PS_Msk (0x03UL << USART3_LCR_PS_Pos) /*!< USART3 LCR: PS Mask */ -#define USART3_LCR_BC_Pos 6 /*!< USART3 LCR: BC Position */ -#define USART3_LCR_BC_Msk (0x01UL << USART3_LCR_BC_Pos) /*!< USART3 LCR: BC Mask */ -#define USART3_LCR_DLAB_Pos 7 /*!< USART3 LCR: DLAB Position */ -#define USART3_LCR_DLAB_Msk (0x01UL << USART3_LCR_DLAB_Pos) /*!< USART3 LCR: DLAB Mask */ - -// --------------------------------------- USART3_LSR ------------------------------------------- -#define USART3_LSR_RDR_Pos 0 /*!< USART3 LSR: RDR Position */ -#define USART3_LSR_RDR_Msk (0x01UL << USART3_LSR_RDR_Pos) /*!< USART3 LSR: RDR Mask */ -#define USART3_LSR_OE_Pos 1 /*!< USART3 LSR: OE Position */ -#define USART3_LSR_OE_Msk (0x01UL << USART3_LSR_OE_Pos) /*!< USART3 LSR: OE Mask */ -#define USART3_LSR_PE_Pos 2 /*!< USART3 LSR: PE Position */ -#define USART3_LSR_PE_Msk (0x01UL << USART3_LSR_PE_Pos) /*!< USART3 LSR: PE Mask */ -#define USART3_LSR_FE_Pos 3 /*!< USART3 LSR: FE Position */ -#define USART3_LSR_FE_Msk (0x01UL << USART3_LSR_FE_Pos) /*!< USART3 LSR: FE Mask */ -#define USART3_LSR_BI_Pos 4 /*!< USART3 LSR: BI Position */ -#define USART3_LSR_BI_Msk (0x01UL << USART3_LSR_BI_Pos) /*!< USART3 LSR: BI Mask */ -#define USART3_LSR_THRE_Pos 5 /*!< USART3 LSR: THRE Position */ -#define USART3_LSR_THRE_Msk (0x01UL << USART3_LSR_THRE_Pos) /*!< USART3 LSR: THRE Mask */ -#define USART3_LSR_TEMT_Pos 6 /*!< USART3 LSR: TEMT Position */ -#define USART3_LSR_TEMT_Msk (0x01UL << USART3_LSR_TEMT_Pos) /*!< USART3 LSR: TEMT Mask */ -#define USART3_LSR_RXFE_Pos 7 /*!< USART3 LSR: RXFE Position */ -#define USART3_LSR_RXFE_Msk (0x01UL << USART3_LSR_RXFE_Pos) /*!< USART3 LSR: RXFE Mask */ -#define USART3_LSR_TXERR_Pos 8 /*!< USART3 LSR: TXERR Position */ -#define USART3_LSR_TXERR_Msk (0x01UL << USART3_LSR_TXERR_Pos) /*!< USART3 LSR: TXERR Mask */ - -// --------------------------------------- USART3_SCR ------------------------------------------- -#define USART3_SCR_PAD_Pos 0 /*!< USART3 SCR: PAD Position */ -#define USART3_SCR_PAD_Msk (0x000000ffUL << USART3_SCR_PAD_Pos) /*!< USART3 SCR: PAD Mask */ - -// --------------------------------------- USART3_ACR ------------------------------------------- -#define USART3_ACR_START_Pos 0 /*!< USART3 ACR: START Position */ -#define USART3_ACR_START_Msk (0x01UL << USART3_ACR_START_Pos) /*!< USART3 ACR: START Mask */ -#define USART3_ACR_MODE_Pos 1 /*!< USART3 ACR: MODE Position */ -#define USART3_ACR_MODE_Msk (0x01UL << USART3_ACR_MODE_Pos) /*!< USART3 ACR: MODE Mask */ -#define USART3_ACR_AUTORESTART_Pos 2 /*!< USART3 ACR: AUTORESTART Position */ -#define USART3_ACR_AUTORESTART_Msk (0x01UL << USART3_ACR_AUTORESTART_Pos) /*!< USART3 ACR: AUTORESTART Mask */ -#define USART3_ACR_ABEOINTCLR_Pos 8 /*!< USART3 ACR: ABEOINTCLR Position */ -#define USART3_ACR_ABEOINTCLR_Msk (0x01UL << USART3_ACR_ABEOINTCLR_Pos) /*!< USART3 ACR: ABEOINTCLR Mask */ -#define USART3_ACR_ABTOINTCLR_Pos 9 /*!< USART3 ACR: ABTOINTCLR Position */ -#define USART3_ACR_ABTOINTCLR_Msk (0x01UL << USART3_ACR_ABTOINTCLR_Pos) /*!< USART3 ACR: ABTOINTCLR Mask */ - -// --------------------------------------- USART3_ICR ------------------------------------------- -#define USART3_ICR_IRDAEN_Pos 0 /*!< USART3 ICR: IRDAEN Position */ -#define USART3_ICR_IRDAEN_Msk (0x01UL << USART3_ICR_IRDAEN_Pos) /*!< USART3 ICR: IRDAEN Mask */ -#define USART3_ICR_IRDAINV_Pos 1 /*!< USART3 ICR: IRDAINV Position */ -#define USART3_ICR_IRDAINV_Msk (0x01UL << USART3_ICR_IRDAINV_Pos) /*!< USART3 ICR: IRDAINV Mask */ -#define USART3_ICR_FIXPULSEEN_Pos 2 /*!< USART3 ICR: FIXPULSEEN Position */ -#define USART3_ICR_FIXPULSEEN_Msk (0x01UL << USART3_ICR_FIXPULSEEN_Pos) /*!< USART3 ICR: FIXPULSEEN Mask */ -#define USART3_ICR_PULSEDIV_Pos 3 /*!< USART3 ICR: PULSEDIV Position */ -#define USART3_ICR_PULSEDIV_Msk (0x07UL << USART3_ICR_PULSEDIV_Pos) /*!< USART3 ICR: PULSEDIV Mask */ - -// --------------------------------------- USART3_FDR ------------------------------------------- -#define USART3_FDR_DIVADDVAL_Pos 0 /*!< USART3 FDR: DIVADDVAL Position */ -#define USART3_FDR_DIVADDVAL_Msk (0x0fUL << USART3_FDR_DIVADDVAL_Pos) /*!< USART3 FDR: DIVADDVAL Mask */ -#define USART3_FDR_MULVAL_Pos 4 /*!< USART3 FDR: MULVAL Position */ -#define USART3_FDR_MULVAL_Msk (0x0fUL << USART3_FDR_MULVAL_Pos) /*!< USART3 FDR: MULVAL Mask */ - -// --------------------------------------- USART3_OSR ------------------------------------------- -#define USART3_OSR_OSFRAC_Pos 1 /*!< USART3 OSR: OSFRAC Position */ -#define USART3_OSR_OSFRAC_Msk (0x07UL << USART3_OSR_OSFRAC_Pos) /*!< USART3 OSR: OSFRAC Mask */ -#define USART3_OSR_OSINT_Pos 4 /*!< USART3 OSR: OSINT Position */ -#define USART3_OSR_OSINT_Msk (0x0fUL << USART3_OSR_OSINT_Pos) /*!< USART3 OSR: OSINT Mask */ -#define USART3_OSR_FDINT_Pos 8 /*!< USART3 OSR: FDINT Position */ -#define USART3_OSR_FDINT_Msk (0x7fUL << USART3_OSR_FDINT_Pos) /*!< USART3 OSR: FDINT Mask */ - -// --------------------------------------- USART3_HDEN ------------------------------------------ -#define USART3_HDEN_HDEN_Pos 0 /*!< USART3 HDEN: HDEN Position */ -#define USART3_HDEN_HDEN_Msk (0x01UL << USART3_HDEN_HDEN_Pos) /*!< USART3 HDEN: HDEN Mask */ - -// ------------------------------------- USART3_SCICTRL ----------------------------------------- -#define USART3_SCICTRL_SCIEN_Pos 0 /*!< USART3 SCICTRL: SCIEN Position */ -#define USART3_SCICTRL_SCIEN_Msk (0x01UL << USART3_SCICTRL_SCIEN_Pos) /*!< USART3 SCICTRL: SCIEN Mask */ -#define USART3_SCICTRL_NACKDIS_Pos 1 /*!< USART3 SCICTRL: NACKDIS Position */ -#define USART3_SCICTRL_NACKDIS_Msk (0x01UL << USART3_SCICTRL_NACKDIS_Pos) /*!< USART3 SCICTRL: NACKDIS Mask */ -#define USART3_SCICTRL_PROTSEL_Pos 2 /*!< USART3 SCICTRL: PROTSEL Position */ -#define USART3_SCICTRL_PROTSEL_Msk (0x01UL << USART3_SCICTRL_PROTSEL_Pos) /*!< USART3 SCICTRL: PROTSEL Mask */ -#define USART3_SCICTRL_TXRETRY_Pos 5 /*!< USART3 SCICTRL: TXRETRY Position */ -#define USART3_SCICTRL_TXRETRY_Msk (0x07UL << USART3_SCICTRL_TXRETRY_Pos) /*!< USART3 SCICTRL: TXRETRY Mask */ -#define USART3_SCICTRL_GUARDTIME_Pos 8 /*!< USART3 SCICTRL: GUARDTIME Position */ -#define USART3_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USART3_SCICTRL_GUARDTIME_Pos) /*!< USART3 SCICTRL: GUARDTIME Mask */ - -// ------------------------------------ USART3_RS485CTRL ---------------------------------------- -#define USART3_RS485CTRL_NMMEN_Pos 0 /*!< USART3 RS485CTRL: NMMEN Position */ -#define USART3_RS485CTRL_NMMEN_Msk (0x01UL << USART3_RS485CTRL_NMMEN_Pos) /*!< USART3 RS485CTRL: NMMEN Mask */ -#define USART3_RS485CTRL_RXDIS_Pos 1 /*!< USART3 RS485CTRL: RXDIS Position */ -#define USART3_RS485CTRL_RXDIS_Msk (0x01UL << USART3_RS485CTRL_RXDIS_Pos) /*!< USART3 RS485CTRL: RXDIS Mask */ -#define USART3_RS485CTRL_AADEN_Pos 2 /*!< USART3 RS485CTRL: AADEN Position */ -#define USART3_RS485CTRL_AADEN_Msk (0x01UL << USART3_RS485CTRL_AADEN_Pos) /*!< USART3 RS485CTRL: AADEN Mask */ -#define USART3_RS485CTRL_DCTRL_Pos 4 /*!< USART3 RS485CTRL: DCTRL Position */ -#define USART3_RS485CTRL_DCTRL_Msk (0x01UL << USART3_RS485CTRL_DCTRL_Pos) /*!< USART3 RS485CTRL: DCTRL Mask */ -#define USART3_RS485CTRL_OINV_Pos 5 /*!< USART3 RS485CTRL: OINV Position */ -#define USART3_RS485CTRL_OINV_Msk (0x01UL << USART3_RS485CTRL_OINV_Pos) /*!< USART3 RS485CTRL: OINV Mask */ - -// ---------------------------------- USART3_RS485ADRMATCH -------------------------------------- -#define USART3_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USART3 RS485ADRMATCH: ADRMATCH Position */ -#define USART3_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USART3_RS485ADRMATCH_ADRMATCH_Pos) /*!< USART3 RS485ADRMATCH: ADRMATCH Mask */ - -// ------------------------------------- USART3_RS485DLY ---------------------------------------- -#define USART3_RS485DLY_DLY_Pos 0 /*!< USART3 RS485DLY: DLY Position */ -#define USART3_RS485DLY_DLY_Msk (0x000000ffUL << USART3_RS485DLY_DLY_Pos) /*!< USART3 RS485DLY: DLY Mask */ - -// ------------------------------------- USART3_SYNCCTRL ---------------------------------------- -#define USART3_SYNCCTRL_SYNC_Pos 0 /*!< USART3 SYNCCTRL: SYNC Position */ -#define USART3_SYNCCTRL_SYNC_Msk (0x01UL << USART3_SYNCCTRL_SYNC_Pos) /*!< USART3 SYNCCTRL: SYNC Mask */ -#define USART3_SYNCCTRL_CSRC_Pos 1 /*!< USART3 SYNCCTRL: CSRC Position */ -#define USART3_SYNCCTRL_CSRC_Msk (0x01UL << USART3_SYNCCTRL_CSRC_Pos) /*!< USART3 SYNCCTRL: CSRC Mask */ -#define USART3_SYNCCTRL_FES_Pos 2 /*!< USART3 SYNCCTRL: FES Position */ -#define USART3_SYNCCTRL_FES_Msk (0x01UL << USART3_SYNCCTRL_FES_Pos) /*!< USART3 SYNCCTRL: FES Mask */ -#define USART3_SYNCCTRL_TSBYPASS_Pos 3 /*!< USART3 SYNCCTRL: TSBYPASS Position */ -#define USART3_SYNCCTRL_TSBYPASS_Msk (0x01UL << USART3_SYNCCTRL_TSBYPASS_Pos) /*!< USART3 SYNCCTRL: TSBYPASS Mask */ -#define USART3_SYNCCTRL_CSCEN_Pos 4 /*!< USART3 SYNCCTRL: CSCEN Position */ -#define USART3_SYNCCTRL_CSCEN_Msk (0x01UL << USART3_SYNCCTRL_CSCEN_Pos) /*!< USART3 SYNCCTRL: CSCEN Mask */ -#define USART3_SYNCCTRL_SSSDIS_Pos 5 /*!< USART3 SYNCCTRL: SSSDIS Position */ -#define USART3_SYNCCTRL_SSSDIS_Msk (0x01UL << USART3_SYNCCTRL_SSSDIS_Pos) /*!< USART3 SYNCCTRL: SSSDIS Mask */ -#define USART3_SYNCCTRL_CCCLR_Pos 6 /*!< USART3 SYNCCTRL: CCCLR Position */ -#define USART3_SYNCCTRL_CCCLR_Msk (0x01UL << USART3_SYNCCTRL_CCCLR_Pos) /*!< USART3 SYNCCTRL: CCCLR Mask */ - -// --------------------------------------- USART3_TER ------------------------------------------- -#define USART3_TER_TXEN_Pos 0 /*!< USART3 TER: TXEN Position */ -#define USART3_TER_TXEN_Msk (0x01UL << USART3_TER_TXEN_Pos) /*!< USART3 TER: TXEN Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- UART1 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- UART1_RBR ------------------------------------------- -#define UART1_RBR_RBR_Pos 0 /*!< UART1 RBR: RBR Position */ -#define UART1_RBR_RBR_Msk (0x000000ffUL << UART1_RBR_RBR_Pos) /*!< UART1 RBR: RBR Mask */ - -// ---------------------------------------- UART1_THR ------------------------------------------- -#define UART1_THR_THR_Pos 0 /*!< UART1 THR: THR Position */ -#define UART1_THR_THR_Msk (0x000000ffUL << UART1_THR_THR_Pos) /*!< UART1 THR: THR Mask */ - -// ---------------------------------------- UART1_DLL ------------------------------------------- -#define UART1_DLL_DLLSB_Pos 0 /*!< UART1 DLL: DLLSB Position */ -#define UART1_DLL_DLLSB_Msk (0x000000ffUL << UART1_DLL_DLLSB_Pos) /*!< UART1 DLL: DLLSB Mask */ - -// ---------------------------------------- UART1_DLM ------------------------------------------- -#define UART1_DLM_DLMSB_Pos 0 /*!< UART1 DLM: DLMSB Position */ -#define UART1_DLM_DLMSB_Msk (0x000000ffUL << UART1_DLM_DLMSB_Pos) /*!< UART1 DLM: DLMSB Mask */ - -// ---------------------------------------- UART1_IER ------------------------------------------- -#define UART1_IER_RBRIE_Pos 0 /*!< UART1 IER: RBRIE Position */ -#define UART1_IER_RBRIE_Msk (0x01UL << UART1_IER_RBRIE_Pos) /*!< UART1 IER: RBRIE Mask */ -#define UART1_IER_THREIE_Pos 1 /*!< UART1 IER: THREIE Position */ -#define UART1_IER_THREIE_Msk (0x01UL << UART1_IER_THREIE_Pos) /*!< UART1 IER: THREIE Mask */ -#define UART1_IER_RXIE_Pos 2 /*!< UART1 IER: RXIE Position */ -#define UART1_IER_RXIE_Msk (0x01UL << UART1_IER_RXIE_Pos) /*!< UART1 IER: RXIE Mask */ -#define UART1_IER_MSIE_Pos 3 /*!< UART1 IER: MSIE Position */ -#define UART1_IER_MSIE_Msk (0x01UL << UART1_IER_MSIE_Pos) /*!< UART1 IER: MSIE Mask */ -#define UART1_IER_CTSIE_Pos 7 /*!< UART1 IER: CTSIE Position */ -#define UART1_IER_CTSIE_Msk (0x01UL << UART1_IER_CTSIE_Pos) /*!< UART1 IER: CTSIE Mask */ -#define UART1_IER_ABEOIE_Pos 8 /*!< UART1 IER: ABEOIE Position */ -#define UART1_IER_ABEOIE_Msk (0x01UL << UART1_IER_ABEOIE_Pos) /*!< UART1 IER: ABEOIE Mask */ -#define UART1_IER_ABTOIE_Pos 9 /*!< UART1 IER: ABTOIE Position */ -#define UART1_IER_ABTOIE_Msk (0x01UL << UART1_IER_ABTOIE_Pos) /*!< UART1 IER: ABTOIE Mask */ - -// ---------------------------------------- UART1_IIR ------------------------------------------- -#define UART1_IIR_INTSTATUS_Pos 0 /*!< UART1 IIR: INTSTATUS Position */ -#define UART1_IIR_INTSTATUS_Msk (0x01UL << UART1_IIR_INTSTATUS_Pos) /*!< UART1 IIR: INTSTATUS Mask */ -#define UART1_IIR_INTID_Pos 1 /*!< UART1 IIR: INTID Position */ -#define UART1_IIR_INTID_Msk (0x07UL << UART1_IIR_INTID_Pos) /*!< UART1 IIR: INTID Mask */ -#define UART1_IIR_FIFOENABLE_Pos 6 /*!< UART1 IIR: FIFOENABLE Position */ -#define UART1_IIR_FIFOENABLE_Msk (0x03UL << UART1_IIR_FIFOENABLE_Pos) /*!< UART1 IIR: FIFOENABLE Mask */ -#define UART1_IIR_ABEOINT_Pos 8 /*!< UART1 IIR: ABEOINT Position */ -#define UART1_IIR_ABEOINT_Msk (0x01UL << UART1_IIR_ABEOINT_Pos) /*!< UART1 IIR: ABEOINT Mask */ -#define UART1_IIR_ABTOINT_Pos 9 /*!< UART1 IIR: ABTOINT Position */ -#define UART1_IIR_ABTOINT_Msk (0x01UL << UART1_IIR_ABTOINT_Pos) /*!< UART1 IIR: ABTOINT Mask */ - -// ---------------------------------------- UART1_FCR ------------------------------------------- -#define UART1_FCR_FIFOEN_Pos 0 /*!< UART1 FCR: FIFOEN Position */ -#define UART1_FCR_FIFOEN_Msk (0x01UL << UART1_FCR_FIFOEN_Pos) /*!< UART1 FCR: FIFOEN Mask */ -#define UART1_FCR_RXFIFORES_Pos 1 /*!< UART1 FCR: RXFIFORES Position */ -#define UART1_FCR_RXFIFORES_Msk (0x01UL << UART1_FCR_RXFIFORES_Pos) /*!< UART1 FCR: RXFIFORES Mask */ -#define UART1_FCR_TXFIFORES_Pos 2 /*!< UART1 FCR: TXFIFORES Position */ -#define UART1_FCR_TXFIFORES_Msk (0x01UL << UART1_FCR_TXFIFORES_Pos) /*!< UART1 FCR: TXFIFORES Mask */ -#define UART1_FCR_DMAMODE_Pos 3 /*!< UART1 FCR: DMAMODE Position */ -#define UART1_FCR_DMAMODE_Msk (0x01UL << UART1_FCR_DMAMODE_Pos) /*!< UART1 FCR: DMAMODE Mask */ -#define UART1_FCR_RXTRIGLVL_Pos 6 /*!< UART1 FCR: RXTRIGLVL Position */ -#define UART1_FCR_RXTRIGLVL_Msk (0x03UL << UART1_FCR_RXTRIGLVL_Pos) /*!< UART1 FCR: RXTRIGLVL Mask */ - -// ---------------------------------------- UART1_LCR ------------------------------------------- -#define UART1_LCR_WLS_Pos 0 /*!< UART1 LCR: WLS Position */ -#define UART1_LCR_WLS_Msk (0x03UL << UART1_LCR_WLS_Pos) /*!< UART1 LCR: WLS Mask */ -#define UART1_LCR_SBS_Pos 2 /*!< UART1 LCR: SBS Position */ -#define UART1_LCR_SBS_Msk (0x01UL << UART1_LCR_SBS_Pos) /*!< UART1 LCR: SBS Mask */ -#define UART1_LCR_PE_Pos 3 /*!< UART1 LCR: PE Position */ -#define UART1_LCR_PE_Msk (0x01UL << UART1_LCR_PE_Pos) /*!< UART1 LCR: PE Mask */ -#define UART1_LCR_PS_Pos 4 /*!< UART1 LCR: PS Position */ -#define UART1_LCR_PS_Msk (0x03UL << UART1_LCR_PS_Pos) /*!< UART1 LCR: PS Mask */ -#define UART1_LCR_BC_Pos 6 /*!< UART1 LCR: BC Position */ -#define UART1_LCR_BC_Msk (0x01UL << UART1_LCR_BC_Pos) /*!< UART1 LCR: BC Mask */ -#define UART1_LCR_DLAB_Pos 7 /*!< UART1 LCR: DLAB Position */ -#define UART1_LCR_DLAB_Msk (0x01UL << UART1_LCR_DLAB_Pos) /*!< UART1 LCR: DLAB Mask */ - -// ---------------------------------------- UART1_MCR ------------------------------------------- -#define UART1_MCR_DTRCTRL_Pos 0 /*!< UART1 MCR: DTRCTRL Position */ -#define UART1_MCR_DTRCTRL_Msk (0x01UL << UART1_MCR_DTRCTRL_Pos) /*!< UART1 MCR: DTRCTRL Mask */ -#define UART1_MCR_RTSCTRL_Pos 1 /*!< UART1 MCR: RTSCTRL Position */ -#define UART1_MCR_RTSCTRL_Msk (0x01UL << UART1_MCR_RTSCTRL_Pos) /*!< UART1 MCR: RTSCTRL Mask */ -#define UART1_MCR_LMS_Pos 4 /*!< UART1 MCR: LMS Position */ -#define UART1_MCR_LMS_Msk (0x01UL << UART1_MCR_LMS_Pos) /*!< UART1 MCR: LMS Mask */ -#define UART1_MCR_RTSEN_Pos 6 /*!< UART1 MCR: RTSEN Position */ -#define UART1_MCR_RTSEN_Msk (0x01UL << UART1_MCR_RTSEN_Pos) /*!< UART1 MCR: RTSEN Mask */ -#define UART1_MCR_CTSEN_Pos 7 /*!< UART1 MCR: CTSEN Position */ -#define UART1_MCR_CTSEN_Msk (0x01UL << UART1_MCR_CTSEN_Pos) /*!< UART1 MCR: CTSEN Mask */ - -// ---------------------------------------- UART1_LSR ------------------------------------------- -#define UART1_LSR_RDR_Pos 0 /*!< UART1 LSR: RDR Position */ -#define UART1_LSR_RDR_Msk (0x01UL << UART1_LSR_RDR_Pos) /*!< UART1 LSR: RDR Mask */ -#define UART1_LSR_OE_Pos 1 /*!< UART1 LSR: OE Position */ -#define UART1_LSR_OE_Msk (0x01UL << UART1_LSR_OE_Pos) /*!< UART1 LSR: OE Mask */ -#define UART1_LSR_PE_Pos 2 /*!< UART1 LSR: PE Position */ -#define UART1_LSR_PE_Msk (0x01UL << UART1_LSR_PE_Pos) /*!< UART1 LSR: PE Mask */ -#define UART1_LSR_FE_Pos 3 /*!< UART1 LSR: FE Position */ -#define UART1_LSR_FE_Msk (0x01UL << UART1_LSR_FE_Pos) /*!< UART1 LSR: FE Mask */ -#define UART1_LSR_BI_Pos 4 /*!< UART1 LSR: BI Position */ -#define UART1_LSR_BI_Msk (0x01UL << UART1_LSR_BI_Pos) /*!< UART1 LSR: BI Mask */ -#define UART1_LSR_THRE_Pos 5 /*!< UART1 LSR: THRE Position */ -#define UART1_LSR_THRE_Msk (0x01UL << UART1_LSR_THRE_Pos) /*!< UART1 LSR: THRE Mask */ -#define UART1_LSR_TEMT_Pos 6 /*!< UART1 LSR: TEMT Position */ -#define UART1_LSR_TEMT_Msk (0x01UL << UART1_LSR_TEMT_Pos) /*!< UART1 LSR: TEMT Mask */ -#define UART1_LSR_RXFE_Pos 7 /*!< UART1 LSR: RXFE Position */ -#define UART1_LSR_RXFE_Msk (0x01UL << UART1_LSR_RXFE_Pos) /*!< UART1 LSR: RXFE Mask */ - -// ---------------------------------------- UART1_MSR ------------------------------------------- -#define UART1_MSR_DCTS_Pos 0 /*!< UART1 MSR: DCTS Position */ -#define UART1_MSR_DCTS_Msk (0x01UL << UART1_MSR_DCTS_Pos) /*!< UART1 MSR: DCTS Mask */ -#define UART1_MSR_DDSR_Pos 1 /*!< UART1 MSR: DDSR Position */ -#define UART1_MSR_DDSR_Msk (0x01UL << UART1_MSR_DDSR_Pos) /*!< UART1 MSR: DDSR Mask */ -#define UART1_MSR_TERI_Pos 2 /*!< UART1 MSR: TERI Position */ -#define UART1_MSR_TERI_Msk (0x01UL << UART1_MSR_TERI_Pos) /*!< UART1 MSR: TERI Mask */ -#define UART1_MSR_DDCD_Pos 3 /*!< UART1 MSR: DDCD Position */ -#define UART1_MSR_DDCD_Msk (0x01UL << UART1_MSR_DDCD_Pos) /*!< UART1 MSR: DDCD Mask */ -#define UART1_MSR_CTS_Pos 4 /*!< UART1 MSR: CTS Position */ -#define UART1_MSR_CTS_Msk (0x01UL << UART1_MSR_CTS_Pos) /*!< UART1 MSR: CTS Mask */ -#define UART1_MSR_DSR_Pos 5 /*!< UART1 MSR: DSR Position */ -#define UART1_MSR_DSR_Msk (0x01UL << UART1_MSR_DSR_Pos) /*!< UART1 MSR: DSR Mask */ -#define UART1_MSR_RI_Pos 6 /*!< UART1 MSR: RI Position */ -#define UART1_MSR_RI_Msk (0x01UL << UART1_MSR_RI_Pos) /*!< UART1 MSR: RI Mask */ -#define UART1_MSR_DCD_Pos 7 /*!< UART1 MSR: DCD Position */ -#define UART1_MSR_DCD_Msk (0x01UL << UART1_MSR_DCD_Pos) /*!< UART1 MSR: DCD Mask */ - -// ---------------------------------------- UART1_SCR ------------------------------------------- -#define UART1_SCR_Pad_Pos 0 /*!< UART1 SCR: Pad Position */ -#define UART1_SCR_Pad_Msk (0x000000ffUL << UART1_SCR_Pad_Pos) /*!< UART1 SCR: Pad Mask */ - -// ---------------------------------------- UART1_ACR ------------------------------------------- -#define UART1_ACR_START_Pos 0 /*!< UART1 ACR: START Position */ -#define UART1_ACR_START_Msk (0x01UL << UART1_ACR_START_Pos) /*!< UART1 ACR: START Mask */ -#define UART1_ACR_MODE_Pos 1 /*!< UART1 ACR: MODE Position */ -#define UART1_ACR_MODE_Msk (0x01UL << UART1_ACR_MODE_Pos) /*!< UART1 ACR: MODE Mask */ -#define UART1_ACR_AUTORESTART_Pos 2 /*!< UART1 ACR: AUTORESTART Position */ -#define UART1_ACR_AUTORESTART_Msk (0x01UL << UART1_ACR_AUTORESTART_Pos) /*!< UART1 ACR: AUTORESTART Mask */ -#define UART1_ACR_ABEOINTCLR_Pos 8 /*!< UART1 ACR: ABEOINTCLR Position */ -#define UART1_ACR_ABEOINTCLR_Msk (0x01UL << UART1_ACR_ABEOINTCLR_Pos) /*!< UART1 ACR: ABEOINTCLR Mask */ -#define UART1_ACR_ABTOINTCLR_Pos 9 /*!< UART1 ACR: ABTOINTCLR Position */ -#define UART1_ACR_ABTOINTCLR_Msk (0x01UL << UART1_ACR_ABTOINTCLR_Pos) /*!< UART1 ACR: ABTOINTCLR Mask */ - -// ---------------------------------------- UART1_FDR ------------------------------------------- -#define UART1_FDR_DIVADDVAL_Pos 0 /*!< UART1 FDR: DIVADDVAL Position */ -#define UART1_FDR_DIVADDVAL_Msk (0x0fUL << UART1_FDR_DIVADDVAL_Pos) /*!< UART1 FDR: DIVADDVAL Mask */ -#define UART1_FDR_MULVAL_Pos 4 /*!< UART1 FDR: MULVAL Position */ -#define UART1_FDR_MULVAL_Msk (0x0fUL << UART1_FDR_MULVAL_Pos) /*!< UART1 FDR: MULVAL Mask */ - -// ---------------------------------------- UART1_TER ------------------------------------------- -#define UART1_TER_TXEN_Pos 7 /*!< UART1 TER: TXEN Position */ -#define UART1_TER_TXEN_Msk (0x01UL << UART1_TER_TXEN_Pos) /*!< UART1 TER: TXEN Mask */ - -// ------------------------------------- UART1_RS485CTRL ---------------------------------------- -#define UART1_RS485CTRL_NMMEN_Pos 0 /*!< UART1 RS485CTRL: NMMEN Position */ -#define UART1_RS485CTRL_NMMEN_Msk (0x01UL << UART1_RS485CTRL_NMMEN_Pos) /*!< UART1 RS485CTRL: NMMEN Mask */ -#define UART1_RS485CTRL_RXDIS_Pos 1 /*!< UART1 RS485CTRL: RXDIS Position */ -#define UART1_RS485CTRL_RXDIS_Msk (0x01UL << UART1_RS485CTRL_RXDIS_Pos) /*!< UART1 RS485CTRL: RXDIS Mask */ -#define UART1_RS485CTRL_AADEN_Pos 2 /*!< UART1 RS485CTRL: AADEN Position */ -#define UART1_RS485CTRL_AADEN_Msk (0x01UL << UART1_RS485CTRL_AADEN_Pos) /*!< UART1 RS485CTRL: AADEN Mask */ -#define UART1_RS485CTRL_SEL_Pos 3 /*!< UART1 RS485CTRL: SEL Position */ -#define UART1_RS485CTRL_SEL_Msk (0x01UL << UART1_RS485CTRL_SEL_Pos) /*!< UART1 RS485CTRL: SEL Mask */ -#define UART1_RS485CTRL_DCTRL_Pos 4 /*!< UART1 RS485CTRL: DCTRL Position */ -#define UART1_RS485CTRL_DCTRL_Msk (0x01UL << UART1_RS485CTRL_DCTRL_Pos) /*!< UART1 RS485CTRL: DCTRL Mask */ -#define UART1_RS485CTRL_OINV_Pos 5 /*!< UART1 RS485CTRL: OINV Position */ -#define UART1_RS485CTRL_OINV_Msk (0x01UL << UART1_RS485CTRL_OINV_Pos) /*!< UART1 RS485CTRL: OINV Mask */ - -// ----------------------------------- UART1_RS485ADRMATCH -------------------------------------- -#define UART1_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< UART1 RS485ADRMATCH: ADRMATCH Position */ -#define UART1_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << UART1_RS485ADRMATCH_ADRMATCH_Pos) /*!< UART1 RS485ADRMATCH: ADRMATCH Mask */ - -// ------------------------------------- UART1_RS485DLY ----------------------------------------- -#define UART1_RS485DLY_DLY_Pos 0 /*!< UART1 RS485DLY: DLY Position */ -#define UART1_RS485DLY_DLY_Msk (0x000000ffUL << UART1_RS485DLY_DLY_Pos) /*!< UART1 RS485DLY: DLY Mask */ - -// -------------------------------------- UART1_FIFOLVL ----------------------------------------- -#define UART1_FIFOLVL_RXFIFILVL_Pos 0 /*!< UART1 FIFOLVL: RXFIFILVL Position */ -#define UART1_FIFOLVL_RXFIFILVL_Msk (0x0fUL << UART1_FIFOLVL_RXFIFILVL_Pos) /*!< UART1 FIFOLVL: RXFIFILVL Mask */ -#define UART1_FIFOLVL_TXFIFOLVL_Pos 8 /*!< UART1 FIFOLVL: TXFIFOLVL Position */ -#define UART1_FIFOLVL_TXFIFOLVL_Msk (0x0fUL << UART1_FIFOLVL_TXFIFOLVL_Pos) /*!< UART1 FIFOLVL: TXFIFOLVL Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- SSP0 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- SSP0_CR0 -------------------------------------------- -#define SSP0_CR0_DSS_Pos 0 /*!< SSP0 CR0: DSS Position */ -#define SSP0_CR0_DSS_Msk (0x0fUL << SSP0_CR0_DSS_Pos) /*!< SSP0 CR0: DSS Mask */ -#define SSP0_CR0_FRF_Pos 4 /*!< SSP0 CR0: FRF Position */ -#define SSP0_CR0_FRF_Msk (0x03UL << SSP0_CR0_FRF_Pos) /*!< SSP0 CR0: FRF Mask */ -#define SSP0_CR0_CPOL_Pos 6 /*!< SSP0 CR0: CPOL Position */ -#define SSP0_CR0_CPOL_Msk (0x01UL << SSP0_CR0_CPOL_Pos) /*!< SSP0 CR0: CPOL Mask */ -#define SSP0_CR0_CPHA_Pos 7 /*!< SSP0 CR0: CPHA Position */ -#define SSP0_CR0_CPHA_Msk (0x01UL << SSP0_CR0_CPHA_Pos) /*!< SSP0 CR0: CPHA Mask */ -#define SSP0_CR0_SCR_Pos 8 /*!< SSP0 CR0: SCR Position */ -#define SSP0_CR0_SCR_Msk (0x000000ffUL << SSP0_CR0_SCR_Pos) /*!< SSP0 CR0: SCR Mask */ - -// ---------------------------------------- SSP0_CR1 -------------------------------------------- -#define SSP0_CR1_LBM_Pos 0 /*!< SSP0 CR1: LBM Position */ -#define SSP0_CR1_LBM_Msk (0x01UL << SSP0_CR1_LBM_Pos) /*!< SSP0 CR1: LBM Mask */ -#define SSP0_CR1_SSE_Pos 1 /*!< SSP0 CR1: SSE Position */ -#define SSP0_CR1_SSE_Msk (0x01UL << SSP0_CR1_SSE_Pos) /*!< SSP0 CR1: SSE Mask */ -#define SSP0_CR1_MS_Pos 2 /*!< SSP0 CR1: MS Position */ -#define SSP0_CR1_MS_Msk (0x01UL << SSP0_CR1_MS_Pos) /*!< SSP0 CR1: MS Mask */ -#define SSP0_CR1_SOD_Pos 3 /*!< SSP0 CR1: SOD Position */ -#define SSP0_CR1_SOD_Msk (0x01UL << SSP0_CR1_SOD_Pos) /*!< SSP0 CR1: SOD Mask */ - -// ----------------------------------------- SSP0_DR -------------------------------------------- -#define SSP0_DR_DATA_Pos 0 /*!< SSP0 DR: DATA Position */ -#define SSP0_DR_DATA_Msk (0x0000ffffUL << SSP0_DR_DATA_Pos) /*!< SSP0 DR: DATA Mask */ - -// ----------------------------------------- SSP0_SR -------------------------------------------- -#define SSP0_SR_TFE_Pos 0 /*!< SSP0 SR: TFE Position */ -#define SSP0_SR_TFE_Msk (0x01UL << SSP0_SR_TFE_Pos) /*!< SSP0 SR: TFE Mask */ -#define SSP0_SR_TNF_Pos 1 /*!< SSP0 SR: TNF Position */ -#define SSP0_SR_TNF_Msk (0x01UL << SSP0_SR_TNF_Pos) /*!< SSP0 SR: TNF Mask */ -#define SSP0_SR_RNE_Pos 2 /*!< SSP0 SR: RNE Position */ -#define SSP0_SR_RNE_Msk (0x01UL << SSP0_SR_RNE_Pos) /*!< SSP0 SR: RNE Mask */ -#define SSP0_SR_RFF_Pos 3 /*!< SSP0 SR: RFF Position */ -#define SSP0_SR_RFF_Msk (0x01UL << SSP0_SR_RFF_Pos) /*!< SSP0 SR: RFF Mask */ -#define SSP0_SR_BSY_Pos 4 /*!< SSP0 SR: BSY Position */ -#define SSP0_SR_BSY_Msk (0x01UL << SSP0_SR_BSY_Pos) /*!< SSP0 SR: BSY Mask */ - -// ---------------------------------------- SSP0_CPSR ------------------------------------------- -#define SSP0_CPSR_CPSDVSR_Pos 0 /*!< SSP0 CPSR: CPSDVSR Position */ -#define SSP0_CPSR_CPSDVSR_Msk (0x000000ffUL << SSP0_CPSR_CPSDVSR_Pos) /*!< SSP0 CPSR: CPSDVSR Mask */ - -// ---------------------------------------- SSP0_IMSC ------------------------------------------- -#define SSP0_IMSC_RORIM_Pos 0 /*!< SSP0 IMSC: RORIM Position */ -#define SSP0_IMSC_RORIM_Msk (0x01UL << SSP0_IMSC_RORIM_Pos) /*!< SSP0 IMSC: RORIM Mask */ -#define SSP0_IMSC_RTIM_Pos 1 /*!< SSP0 IMSC: RTIM Position */ -#define SSP0_IMSC_RTIM_Msk (0x01UL << SSP0_IMSC_RTIM_Pos) /*!< SSP0 IMSC: RTIM Mask */ -#define SSP0_IMSC_RXIM_Pos 2 /*!< SSP0 IMSC: RXIM Position */ -#define SSP0_IMSC_RXIM_Msk (0x01UL << SSP0_IMSC_RXIM_Pos) /*!< SSP0 IMSC: RXIM Mask */ -#define SSP0_IMSC_TXIM_Pos 3 /*!< SSP0 IMSC: TXIM Position */ -#define SSP0_IMSC_TXIM_Msk (0x01UL << SSP0_IMSC_TXIM_Pos) /*!< SSP0 IMSC: TXIM Mask */ - -// ---------------------------------------- SSP0_RIS -------------------------------------------- -#define SSP0_RIS_RORRIS_Pos 0 /*!< SSP0 RIS: RORRIS Position */ -#define SSP0_RIS_RORRIS_Msk (0x01UL << SSP0_RIS_RORRIS_Pos) /*!< SSP0 RIS: RORRIS Mask */ -#define SSP0_RIS_RTRIS_Pos 1 /*!< SSP0 RIS: RTRIS Position */ -#define SSP0_RIS_RTRIS_Msk (0x01UL << SSP0_RIS_RTRIS_Pos) /*!< SSP0 RIS: RTRIS Mask */ -#define SSP0_RIS_RXRIS_Pos 2 /*!< SSP0 RIS: RXRIS Position */ -#define SSP0_RIS_RXRIS_Msk (0x01UL << SSP0_RIS_RXRIS_Pos) /*!< SSP0 RIS: RXRIS Mask */ -#define SSP0_RIS_TXRIS_Pos 3 /*!< SSP0 RIS: TXRIS Position */ -#define SSP0_RIS_TXRIS_Msk (0x01UL << SSP0_RIS_TXRIS_Pos) /*!< SSP0 RIS: TXRIS Mask */ - -// ---------------------------------------- SSP0_MIS -------------------------------------------- -#define SSP0_MIS_RORMIS_Pos 0 /*!< SSP0 MIS: RORMIS Position */ -#define SSP0_MIS_RORMIS_Msk (0x01UL << SSP0_MIS_RORMIS_Pos) /*!< SSP0 MIS: RORMIS Mask */ -#define SSP0_MIS_RTMIS_Pos 1 /*!< SSP0 MIS: RTMIS Position */ -#define SSP0_MIS_RTMIS_Msk (0x01UL << SSP0_MIS_RTMIS_Pos) /*!< SSP0 MIS: RTMIS Mask */ -#define SSP0_MIS_RXMIS_Pos 2 /*!< SSP0 MIS: RXMIS Position */ -#define SSP0_MIS_RXMIS_Msk (0x01UL << SSP0_MIS_RXMIS_Pos) /*!< SSP0 MIS: RXMIS Mask */ -#define SSP0_MIS_TXMIS_Pos 3 /*!< SSP0 MIS: TXMIS Position */ -#define SSP0_MIS_TXMIS_Msk (0x01UL << SSP0_MIS_TXMIS_Pos) /*!< SSP0 MIS: TXMIS Mask */ - -// ---------------------------------------- SSP0_ICR -------------------------------------------- -#define SSP0_ICR_RORIC_Pos 0 /*!< SSP0 ICR: RORIC Position */ -#define SSP0_ICR_RORIC_Msk (0x01UL << SSP0_ICR_RORIC_Pos) /*!< SSP0 ICR: RORIC Mask */ -#define SSP0_ICR_RTIC_Pos 1 /*!< SSP0 ICR: RTIC Position */ -#define SSP0_ICR_RTIC_Msk (0x01UL << SSP0_ICR_RTIC_Pos) /*!< SSP0 ICR: RTIC Mask */ - -// --------------------------------------- SSP0_DMACR ------------------------------------------- -#define SSP0_DMACR_RXDMAE_Pos 0 /*!< SSP0 DMACR: RXDMAE Position */ -#define SSP0_DMACR_RXDMAE_Msk (0x01UL << SSP0_DMACR_RXDMAE_Pos) /*!< SSP0 DMACR: RXDMAE Mask */ -#define SSP0_DMACR_TXDMAE_Pos 1 /*!< SSP0 DMACR: TXDMAE Position */ -#define SSP0_DMACR_TXDMAE_Msk (0x01UL << SSP0_DMACR_TXDMAE_Pos) /*!< SSP0 DMACR: TXDMAE Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- SSP1 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- SSP1_CR0 -------------------------------------------- -#define SSP1_CR0_DSS_Pos 0 /*!< SSP1 CR0: DSS Position */ -#define SSP1_CR0_DSS_Msk (0x0fUL << SSP1_CR0_DSS_Pos) /*!< SSP1 CR0: DSS Mask */ -#define SSP1_CR0_FRF_Pos 4 /*!< SSP1 CR0: FRF Position */ -#define SSP1_CR0_FRF_Msk (0x03UL << SSP1_CR0_FRF_Pos) /*!< SSP1 CR0: FRF Mask */ -#define SSP1_CR0_CPOL_Pos 6 /*!< SSP1 CR0: CPOL Position */ -#define SSP1_CR0_CPOL_Msk (0x01UL << SSP1_CR0_CPOL_Pos) /*!< SSP1 CR0: CPOL Mask */ -#define SSP1_CR0_CPHA_Pos 7 /*!< SSP1 CR0: CPHA Position */ -#define SSP1_CR0_CPHA_Msk (0x01UL << SSP1_CR0_CPHA_Pos) /*!< SSP1 CR0: CPHA Mask */ -#define SSP1_CR0_SCR_Pos 8 /*!< SSP1 CR0: SCR Position */ -#define SSP1_CR0_SCR_Msk (0x000000ffUL << SSP1_CR0_SCR_Pos) /*!< SSP1 CR0: SCR Mask */ - -// ---------------------------------------- SSP1_CR1 -------------------------------------------- -#define SSP1_CR1_LBM_Pos 0 /*!< SSP1 CR1: LBM Position */ -#define SSP1_CR1_LBM_Msk (0x01UL << SSP1_CR1_LBM_Pos) /*!< SSP1 CR1: LBM Mask */ -#define SSP1_CR1_SSE_Pos 1 /*!< SSP1 CR1: SSE Position */ -#define SSP1_CR1_SSE_Msk (0x01UL << SSP1_CR1_SSE_Pos) /*!< SSP1 CR1: SSE Mask */ -#define SSP1_CR1_MS_Pos 2 /*!< SSP1 CR1: MS Position */ -#define SSP1_CR1_MS_Msk (0x01UL << SSP1_CR1_MS_Pos) /*!< SSP1 CR1: MS Mask */ -#define SSP1_CR1_SOD_Pos 3 /*!< SSP1 CR1: SOD Position */ -#define SSP1_CR1_SOD_Msk (0x01UL << SSP1_CR1_SOD_Pos) /*!< SSP1 CR1: SOD Mask */ - -// ----------------------------------------- SSP1_DR -------------------------------------------- -#define SSP1_DR_DATA_Pos 0 /*!< SSP1 DR: DATA Position */ -#define SSP1_DR_DATA_Msk (0x0000ffffUL << SSP1_DR_DATA_Pos) /*!< SSP1 DR: DATA Mask */ - -// ----------------------------------------- SSP1_SR -------------------------------------------- -#define SSP1_SR_TFE_Pos 0 /*!< SSP1 SR: TFE Position */ -#define SSP1_SR_TFE_Msk (0x01UL << SSP1_SR_TFE_Pos) /*!< SSP1 SR: TFE Mask */ -#define SSP1_SR_TNF_Pos 1 /*!< SSP1 SR: TNF Position */ -#define SSP1_SR_TNF_Msk (0x01UL << SSP1_SR_TNF_Pos) /*!< SSP1 SR: TNF Mask */ -#define SSP1_SR_RNE_Pos 2 /*!< SSP1 SR: RNE Position */ -#define SSP1_SR_RNE_Msk (0x01UL << SSP1_SR_RNE_Pos) /*!< SSP1 SR: RNE Mask */ -#define SSP1_SR_RFF_Pos 3 /*!< SSP1 SR: RFF Position */ -#define SSP1_SR_RFF_Msk (0x01UL << SSP1_SR_RFF_Pos) /*!< SSP1 SR: RFF Mask */ -#define SSP1_SR_BSY_Pos 4 /*!< SSP1 SR: BSY Position */ -#define SSP1_SR_BSY_Msk (0x01UL << SSP1_SR_BSY_Pos) /*!< SSP1 SR: BSY Mask */ - -// ---------------------------------------- SSP1_CPSR ------------------------------------------- -#define SSP1_CPSR_CPSDVSR_Pos 0 /*!< SSP1 CPSR: CPSDVSR Position */ -#define SSP1_CPSR_CPSDVSR_Msk (0x000000ffUL << SSP1_CPSR_CPSDVSR_Pos) /*!< SSP1 CPSR: CPSDVSR Mask */ - -// ---------------------------------------- SSP1_IMSC ------------------------------------------- -#define SSP1_IMSC_RORIM_Pos 0 /*!< SSP1 IMSC: RORIM Position */ -#define SSP1_IMSC_RORIM_Msk (0x01UL << SSP1_IMSC_RORIM_Pos) /*!< SSP1 IMSC: RORIM Mask */ -#define SSP1_IMSC_RTIM_Pos 1 /*!< SSP1 IMSC: RTIM Position */ -#define SSP1_IMSC_RTIM_Msk (0x01UL << SSP1_IMSC_RTIM_Pos) /*!< SSP1 IMSC: RTIM Mask */ -#define SSP1_IMSC_RXIM_Pos 2 /*!< SSP1 IMSC: RXIM Position */ -#define SSP1_IMSC_RXIM_Msk (0x01UL << SSP1_IMSC_RXIM_Pos) /*!< SSP1 IMSC: RXIM Mask */ -#define SSP1_IMSC_TXIM_Pos 3 /*!< SSP1 IMSC: TXIM Position */ -#define SSP1_IMSC_TXIM_Msk (0x01UL << SSP1_IMSC_TXIM_Pos) /*!< SSP1 IMSC: TXIM Mask */ - -// ---------------------------------------- SSP1_RIS -------------------------------------------- -#define SSP1_RIS_RORRIS_Pos 0 /*!< SSP1 RIS: RORRIS Position */ -#define SSP1_RIS_RORRIS_Msk (0x01UL << SSP1_RIS_RORRIS_Pos) /*!< SSP1 RIS: RORRIS Mask */ -#define SSP1_RIS_RTRIS_Pos 1 /*!< SSP1 RIS: RTRIS Position */ -#define SSP1_RIS_RTRIS_Msk (0x01UL << SSP1_RIS_RTRIS_Pos) /*!< SSP1 RIS: RTRIS Mask */ -#define SSP1_RIS_RXRIS_Pos 2 /*!< SSP1 RIS: RXRIS Position */ -#define SSP1_RIS_RXRIS_Msk (0x01UL << SSP1_RIS_RXRIS_Pos) /*!< SSP1 RIS: RXRIS Mask */ -#define SSP1_RIS_TXRIS_Pos 3 /*!< SSP1 RIS: TXRIS Position */ -#define SSP1_RIS_TXRIS_Msk (0x01UL << SSP1_RIS_TXRIS_Pos) /*!< SSP1 RIS: TXRIS Mask */ - -// ---------------------------------------- SSP1_MIS -------------------------------------------- -#define SSP1_MIS_RORMIS_Pos 0 /*!< SSP1 MIS: RORMIS Position */ -#define SSP1_MIS_RORMIS_Msk (0x01UL << SSP1_MIS_RORMIS_Pos) /*!< SSP1 MIS: RORMIS Mask */ -#define SSP1_MIS_RTMIS_Pos 1 /*!< SSP1 MIS: RTMIS Position */ -#define SSP1_MIS_RTMIS_Msk (0x01UL << SSP1_MIS_RTMIS_Pos) /*!< SSP1 MIS: RTMIS Mask */ -#define SSP1_MIS_RXMIS_Pos 2 /*!< SSP1 MIS: RXMIS Position */ -#define SSP1_MIS_RXMIS_Msk (0x01UL << SSP1_MIS_RXMIS_Pos) /*!< SSP1 MIS: RXMIS Mask */ -#define SSP1_MIS_TXMIS_Pos 3 /*!< SSP1 MIS: TXMIS Position */ -#define SSP1_MIS_TXMIS_Msk (0x01UL << SSP1_MIS_TXMIS_Pos) /*!< SSP1 MIS: TXMIS Mask */ - -// ---------------------------------------- SSP1_ICR -------------------------------------------- -#define SSP1_ICR_RORIC_Pos 0 /*!< SSP1 ICR: RORIC Position */ -#define SSP1_ICR_RORIC_Msk (0x01UL << SSP1_ICR_RORIC_Pos) /*!< SSP1 ICR: RORIC Mask */ -#define SSP1_ICR_RTIC_Pos 1 /*!< SSP1 ICR: RTIC Position */ -#define SSP1_ICR_RTIC_Msk (0x01UL << SSP1_ICR_RTIC_Pos) /*!< SSP1 ICR: RTIC Mask */ - -// --------------------------------------- SSP1_DMACR ------------------------------------------- -#define SSP1_DMACR_RXDMAE_Pos 0 /*!< SSP1 DMACR: RXDMAE Position */ -#define SSP1_DMACR_RXDMAE_Msk (0x01UL << SSP1_DMACR_RXDMAE_Pos) /*!< SSP1 DMACR: RXDMAE Mask */ -#define SSP1_DMACR_TXDMAE_Pos 1 /*!< SSP1 DMACR: TXDMAE Position */ -#define SSP1_DMACR_TXDMAE_Msk (0x01UL << SSP1_DMACR_TXDMAE_Pos) /*!< SSP1 DMACR: TXDMAE Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- TIMER0 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- TIMER0_IR ------------------------------------------- -#define TIMER0_IR_MR0INT_Pos 0 /*!< TIMER0 IR: MR0INT Position */ -#define TIMER0_IR_MR0INT_Msk (0x01UL << TIMER0_IR_MR0INT_Pos) /*!< TIMER0 IR: MR0INT Mask */ -#define TIMER0_IR_MR1INT_Pos 1 /*!< TIMER0 IR: MR1INT Position */ -#define TIMER0_IR_MR1INT_Msk (0x01UL << TIMER0_IR_MR1INT_Pos) /*!< TIMER0 IR: MR1INT Mask */ -#define TIMER0_IR_MR2INT_Pos 2 /*!< TIMER0 IR: MR2INT Position */ -#define TIMER0_IR_MR2INT_Msk (0x01UL << TIMER0_IR_MR2INT_Pos) /*!< TIMER0 IR: MR2INT Mask */ -#define TIMER0_IR_MR3INT_Pos 3 /*!< TIMER0 IR: MR3INT Position */ -#define TIMER0_IR_MR3INT_Msk (0x01UL << TIMER0_IR_MR3INT_Pos) /*!< TIMER0 IR: MR3INT Mask */ -#define TIMER0_IR_CR0INT_Pos 4 /*!< TIMER0 IR: CR0INT Position */ -#define TIMER0_IR_CR0INT_Msk (0x01UL << TIMER0_IR_CR0INT_Pos) /*!< TIMER0 IR: CR0INT Mask */ -#define TIMER0_IR_CR1INT_Pos 5 /*!< TIMER0 IR: CR1INT Position */ -#define TIMER0_IR_CR1INT_Msk (0x01UL << TIMER0_IR_CR1INT_Pos) /*!< TIMER0 IR: CR1INT Mask */ -#define TIMER0_IR_CR2INT_Pos 6 /*!< TIMER0 IR: CR2INT Position */ -#define TIMER0_IR_CR2INT_Msk (0x01UL << TIMER0_IR_CR2INT_Pos) /*!< TIMER0 IR: CR2INT Mask */ -#define TIMER0_IR_CR3INT_Pos 7 /*!< TIMER0 IR: CR3INT Position */ -#define TIMER0_IR_CR3INT_Msk (0x01UL << TIMER0_IR_CR3INT_Pos) /*!< TIMER0 IR: CR3INT Mask */ - -// --------------------------------------- TIMER0_TCR ------------------------------------------- -#define TIMER0_TCR_CEN_Pos 0 /*!< TIMER0 TCR: CEN Position */ -#define TIMER0_TCR_CEN_Msk (0x01UL << TIMER0_TCR_CEN_Pos) /*!< TIMER0 TCR: CEN Mask */ -#define TIMER0_TCR_CRST_Pos 1 /*!< TIMER0 TCR: CRST Position */ -#define TIMER0_TCR_CRST_Msk (0x01UL << TIMER0_TCR_CRST_Pos) /*!< TIMER0 TCR: CRST Mask */ - -// ---------------------------------------- TIMER0_TC ------------------------------------------- -#define TIMER0_TC_TC_Pos 0 /*!< TIMER0 TC: TC Position */ -#define TIMER0_TC_TC_Msk (0xffffffffUL << TIMER0_TC_TC_Pos) /*!< TIMER0 TC: TC Mask */ - -// ---------------------------------------- TIMER0_PR ------------------------------------------- -#define TIMER0_PR_PM_Pos 0 /*!< TIMER0 PR: PM Position */ -#define TIMER0_PR_PM_Msk (0xffffffffUL << TIMER0_PR_PM_Pos) /*!< TIMER0 PR: PM Mask */ - -// ---------------------------------------- TIMER0_PC ------------------------------------------- -#define TIMER0_PC_PC_Pos 0 /*!< TIMER0 PC: PC Position */ -#define TIMER0_PC_PC_Msk (0xffffffffUL << TIMER0_PC_PC_Pos) /*!< TIMER0 PC: PC Mask */ - -// --------------------------------------- TIMER0_MCR ------------------------------------------- -#define TIMER0_MCR_MR0I_Pos 0 /*!< TIMER0 MCR: MR0I Position */ -#define TIMER0_MCR_MR0I_Msk (0x01UL << TIMER0_MCR_MR0I_Pos) /*!< TIMER0 MCR: MR0I Mask */ -#define TIMER0_MCR_MR0R_Pos 1 /*!< TIMER0 MCR: MR0R Position */ -#define TIMER0_MCR_MR0R_Msk (0x01UL << TIMER0_MCR_MR0R_Pos) /*!< TIMER0 MCR: MR0R Mask */ -#define TIMER0_MCR_MR0S_Pos 2 /*!< TIMER0 MCR: MR0S Position */ -#define TIMER0_MCR_MR0S_Msk (0x01UL << TIMER0_MCR_MR0S_Pos) /*!< TIMER0 MCR: MR0S Mask */ -#define TIMER0_MCR_MR1I_Pos 3 /*!< TIMER0 MCR: MR1I Position */ -#define TIMER0_MCR_MR1I_Msk (0x01UL << TIMER0_MCR_MR1I_Pos) /*!< TIMER0 MCR: MR1I Mask */ -#define TIMER0_MCR_MR1R_Pos 4 /*!< TIMER0 MCR: MR1R Position */ -#define TIMER0_MCR_MR1R_Msk (0x01UL << TIMER0_MCR_MR1R_Pos) /*!< TIMER0 MCR: MR1R Mask */ -#define TIMER0_MCR_MR1S_Pos 5 /*!< TIMER0 MCR: MR1S Position */ -#define TIMER0_MCR_MR1S_Msk (0x01UL << TIMER0_MCR_MR1S_Pos) /*!< TIMER0 MCR: MR1S Mask */ -#define TIMER0_MCR_MR2I_Pos 6 /*!< TIMER0 MCR: MR2I Position */ -#define TIMER0_MCR_MR2I_Msk (0x01UL << TIMER0_MCR_MR2I_Pos) /*!< TIMER0 MCR: MR2I Mask */ -#define TIMER0_MCR_MR2R_Pos 7 /*!< TIMER0 MCR: MR2R Position */ -#define TIMER0_MCR_MR2R_Msk (0x01UL << TIMER0_MCR_MR2R_Pos) /*!< TIMER0 MCR: MR2R Mask */ -#define TIMER0_MCR_MR2S_Pos 8 /*!< TIMER0 MCR: MR2S Position */ -#define TIMER0_MCR_MR2S_Msk (0x01UL << TIMER0_MCR_MR2S_Pos) /*!< TIMER0 MCR: MR2S Mask */ -#define TIMER0_MCR_MR3I_Pos 9 /*!< TIMER0 MCR: MR3I Position */ -#define TIMER0_MCR_MR3I_Msk (0x01UL << TIMER0_MCR_MR3I_Pos) /*!< TIMER0 MCR: MR3I Mask */ -#define TIMER0_MCR_MR3R_Pos 10 /*!< TIMER0 MCR: MR3R Position */ -#define TIMER0_MCR_MR3R_Msk (0x01UL << TIMER0_MCR_MR3R_Pos) /*!< TIMER0 MCR: MR3R Mask */ -#define TIMER0_MCR_MR3S_Pos 11 /*!< TIMER0 MCR: MR3S Position */ -#define TIMER0_MCR_MR3S_Msk (0x01UL << TIMER0_MCR_MR3S_Pos) /*!< TIMER0 MCR: MR3S Mask */ - -// --------------------------------------- TIMER0_MR0 ------------------------------------------- -#define TIMER0_MR0_MATCH_Pos 0 /*!< TIMER0 MR0: MATCH Position */ -#define TIMER0_MR0_MATCH_Msk (0xffffffffUL << TIMER0_MR0_MATCH_Pos) /*!< TIMER0 MR0: MATCH Mask */ - -// --------------------------------------- TIMER0_MR1 ------------------------------------------- -#define TIMER0_MR1_MATCH_Pos 0 /*!< TIMER0 MR1: MATCH Position */ -#define TIMER0_MR1_MATCH_Msk (0xffffffffUL << TIMER0_MR1_MATCH_Pos) /*!< TIMER0 MR1: MATCH Mask */ - -// --------------------------------------- TIMER0_MR2 ------------------------------------------- -#define TIMER0_MR2_MATCH_Pos 0 /*!< TIMER0 MR2: MATCH Position */ -#define TIMER0_MR2_MATCH_Msk (0xffffffffUL << TIMER0_MR2_MATCH_Pos) /*!< TIMER0 MR2: MATCH Mask */ - -// --------------------------------------- TIMER0_MR3 ------------------------------------------- -#define TIMER0_MR3_MATCH_Pos 0 /*!< TIMER0 MR3: MATCH Position */ -#define TIMER0_MR3_MATCH_Msk (0xffffffffUL << TIMER0_MR3_MATCH_Pos) /*!< TIMER0 MR3: MATCH Mask */ - -// --------------------------------------- TIMER0_CCR ------------------------------------------- -#define TIMER0_CCR_CAP0RE_Pos 0 /*!< TIMER0 CCR: CAP0RE Position */ -#define TIMER0_CCR_CAP0RE_Msk (0x01UL << TIMER0_CCR_CAP0RE_Pos) /*!< TIMER0 CCR: CAP0RE Mask */ -#define TIMER0_CCR_CAP0FE_Pos 1 /*!< TIMER0 CCR: CAP0FE Position */ -#define TIMER0_CCR_CAP0FE_Msk (0x01UL << TIMER0_CCR_CAP0FE_Pos) /*!< TIMER0 CCR: CAP0FE Mask */ -#define TIMER0_CCR_CAP0I_Pos 2 /*!< TIMER0 CCR: CAP0I Position */ -#define TIMER0_CCR_CAP0I_Msk (0x01UL << TIMER0_CCR_CAP0I_Pos) /*!< TIMER0 CCR: CAP0I Mask */ -#define TIMER0_CCR_CAP1RE_Pos 3 /*!< TIMER0 CCR: CAP1RE Position */ -#define TIMER0_CCR_CAP1RE_Msk (0x01UL << TIMER0_CCR_CAP1RE_Pos) /*!< TIMER0 CCR: CAP1RE Mask */ -#define TIMER0_CCR_CAP1FE_Pos 4 /*!< TIMER0 CCR: CAP1FE Position */ -#define TIMER0_CCR_CAP1FE_Msk (0x01UL << TIMER0_CCR_CAP1FE_Pos) /*!< TIMER0 CCR: CAP1FE Mask */ -#define TIMER0_CCR_CAP1I_Pos 5 /*!< TIMER0 CCR: CAP1I Position */ -#define TIMER0_CCR_CAP1I_Msk (0x01UL << TIMER0_CCR_CAP1I_Pos) /*!< TIMER0 CCR: CAP1I Mask */ -#define TIMER0_CCR_CAP2RE_Pos 6 /*!< TIMER0 CCR: CAP2RE Position */ -#define TIMER0_CCR_CAP2RE_Msk (0x01UL << TIMER0_CCR_CAP2RE_Pos) /*!< TIMER0 CCR: CAP2RE Mask */ -#define TIMER0_CCR_CAP2FE_Pos 7 /*!< TIMER0 CCR: CAP2FE Position */ -#define TIMER0_CCR_CAP2FE_Msk (0x01UL << TIMER0_CCR_CAP2FE_Pos) /*!< TIMER0 CCR: CAP2FE Mask */ -#define TIMER0_CCR_CAP2I_Pos 8 /*!< TIMER0 CCR: CAP2I Position */ -#define TIMER0_CCR_CAP2I_Msk (0x01UL << TIMER0_CCR_CAP2I_Pos) /*!< TIMER0 CCR: CAP2I Mask */ -#define TIMER0_CCR_CAP3RE_Pos 9 /*!< TIMER0 CCR: CAP3RE Position */ -#define TIMER0_CCR_CAP3RE_Msk (0x01UL << TIMER0_CCR_CAP3RE_Pos) /*!< TIMER0 CCR: CAP3RE Mask */ -#define TIMER0_CCR_CAP3FE_Pos 10 /*!< TIMER0 CCR: CAP3FE Position */ -#define TIMER0_CCR_CAP3FE_Msk (0x01UL << TIMER0_CCR_CAP3FE_Pos) /*!< TIMER0 CCR: CAP3FE Mask */ -#define TIMER0_CCR_CAP3I_Pos 11 /*!< TIMER0 CCR: CAP3I Position */ -#define TIMER0_CCR_CAP3I_Msk (0x01UL << TIMER0_CCR_CAP3I_Pos) /*!< TIMER0 CCR: CAP3I Mask */ - -// --------------------------------------- TIMER0_CR0 ------------------------------------------- -#define TIMER0_CR0_CAP_Pos 0 /*!< TIMER0 CR0: CAP Position */ -#define TIMER0_CR0_CAP_Msk (0xffffffffUL << TIMER0_CR0_CAP_Pos) /*!< TIMER0 CR0: CAP Mask */ - -// --------------------------------------- TIMER0_CR1 ------------------------------------------- -#define TIMER0_CR1_CAP_Pos 0 /*!< TIMER0 CR1: CAP Position */ -#define TIMER0_CR1_CAP_Msk (0xffffffffUL << TIMER0_CR1_CAP_Pos) /*!< TIMER0 CR1: CAP Mask */ - -// --------------------------------------- TIMER0_CR2 ------------------------------------------- -#define TIMER0_CR2_CAP_Pos 0 /*!< TIMER0 CR2: CAP Position */ -#define TIMER0_CR2_CAP_Msk (0xffffffffUL << TIMER0_CR2_CAP_Pos) /*!< TIMER0 CR2: CAP Mask */ - -// --------------------------------------- TIMER0_CR3 ------------------------------------------- -#define TIMER0_CR3_CAP_Pos 0 /*!< TIMER0 CR3: CAP Position */ -#define TIMER0_CR3_CAP_Msk (0xffffffffUL << TIMER0_CR3_CAP_Pos) /*!< TIMER0 CR3: CAP Mask */ - -// --------------------------------------- TIMER0_EMR ------------------------------------------- -#define TIMER0_EMR_EM0_Pos 0 /*!< TIMER0 EMR: EM0 Position */ -#define TIMER0_EMR_EM0_Msk (0x01UL << TIMER0_EMR_EM0_Pos) /*!< TIMER0 EMR: EM0 Mask */ -#define TIMER0_EMR_EM1_Pos 1 /*!< TIMER0 EMR: EM1 Position */ -#define TIMER0_EMR_EM1_Msk (0x01UL << TIMER0_EMR_EM1_Pos) /*!< TIMER0 EMR: EM1 Mask */ -#define TIMER0_EMR_EM2_Pos 2 /*!< TIMER0 EMR: EM2 Position */ -#define TIMER0_EMR_EM2_Msk (0x01UL << TIMER0_EMR_EM2_Pos) /*!< TIMER0 EMR: EM2 Mask */ -#define TIMER0_EMR_EM3_Pos 3 /*!< TIMER0 EMR: EM3 Position */ -#define TIMER0_EMR_EM3_Msk (0x01UL << TIMER0_EMR_EM3_Pos) /*!< TIMER0 EMR: EM3 Mask */ -#define TIMER0_EMR_EMC0_Pos 4 /*!< TIMER0 EMR: EMC0 Position */ -#define TIMER0_EMR_EMC0_Msk (0x03UL << TIMER0_EMR_EMC0_Pos) /*!< TIMER0 EMR: EMC0 Mask */ -#define TIMER0_EMR_EMC1_Pos 6 /*!< TIMER0 EMR: EMC1 Position */ -#define TIMER0_EMR_EMC1_Msk (0x03UL << TIMER0_EMR_EMC1_Pos) /*!< TIMER0 EMR: EMC1 Mask */ -#define TIMER0_EMR_EMC2_Pos 8 /*!< TIMER0 EMR: EMC2 Position */ -#define TIMER0_EMR_EMC2_Msk (0x03UL << TIMER0_EMR_EMC2_Pos) /*!< TIMER0 EMR: EMC2 Mask */ -#define TIMER0_EMR_EMC3_Pos 10 /*!< TIMER0 EMR: EMC3 Position */ -#define TIMER0_EMR_EMC3_Msk (0x03UL << TIMER0_EMR_EMC3_Pos) /*!< TIMER0 EMR: EMC3 Mask */ - -// --------------------------------------- TIMER0_CTCR ------------------------------------------ -#define TIMER0_CTCR_CTMODE_Pos 0 /*!< TIMER0 CTCR: CTMODE Position */ -#define TIMER0_CTCR_CTMODE_Msk (0x03UL << TIMER0_CTCR_CTMODE_Pos) /*!< TIMER0 CTCR: CTMODE Mask */ -#define TIMER0_CTCR_CINSEL_Pos 2 /*!< TIMER0 CTCR: CINSEL Position */ -#define TIMER0_CTCR_CINSEL_Msk (0x03UL << TIMER0_CTCR_CINSEL_Pos) /*!< TIMER0 CTCR: CINSEL Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- TIMER1 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- TIMER1_IR ------------------------------------------- -#define TIMER1_IR_MR0INT_Pos 0 /*!< TIMER1 IR: MR0INT Position */ -#define TIMER1_IR_MR0INT_Msk (0x01UL << TIMER1_IR_MR0INT_Pos) /*!< TIMER1 IR: MR0INT Mask */ -#define TIMER1_IR_MR1INT_Pos 1 /*!< TIMER1 IR: MR1INT Position */ -#define TIMER1_IR_MR1INT_Msk (0x01UL << TIMER1_IR_MR1INT_Pos) /*!< TIMER1 IR: MR1INT Mask */ -#define TIMER1_IR_MR2INT_Pos 2 /*!< TIMER1 IR: MR2INT Position */ -#define TIMER1_IR_MR2INT_Msk (0x01UL << TIMER1_IR_MR2INT_Pos) /*!< TIMER1 IR: MR2INT Mask */ -#define TIMER1_IR_MR3INT_Pos 3 /*!< TIMER1 IR: MR3INT Position */ -#define TIMER1_IR_MR3INT_Msk (0x01UL << TIMER1_IR_MR3INT_Pos) /*!< TIMER1 IR: MR3INT Mask */ -#define TIMER1_IR_CR0INT_Pos 4 /*!< TIMER1 IR: CR0INT Position */ -#define TIMER1_IR_CR0INT_Msk (0x01UL << TIMER1_IR_CR0INT_Pos) /*!< TIMER1 IR: CR0INT Mask */ -#define TIMER1_IR_CR1INT_Pos 5 /*!< TIMER1 IR: CR1INT Position */ -#define TIMER1_IR_CR1INT_Msk (0x01UL << TIMER1_IR_CR1INT_Pos) /*!< TIMER1 IR: CR1INT Mask */ -#define TIMER1_IR_CR2INT_Pos 6 /*!< TIMER1 IR: CR2INT Position */ -#define TIMER1_IR_CR2INT_Msk (0x01UL << TIMER1_IR_CR2INT_Pos) /*!< TIMER1 IR: CR2INT Mask */ -#define TIMER1_IR_CR3INT_Pos 7 /*!< TIMER1 IR: CR3INT Position */ -#define TIMER1_IR_CR3INT_Msk (0x01UL << TIMER1_IR_CR3INT_Pos) /*!< TIMER1 IR: CR3INT Mask */ - -// --------------------------------------- TIMER1_TCR ------------------------------------------- -#define TIMER1_TCR_CEN_Pos 0 /*!< TIMER1 TCR: CEN Position */ -#define TIMER1_TCR_CEN_Msk (0x01UL << TIMER1_TCR_CEN_Pos) /*!< TIMER1 TCR: CEN Mask */ -#define TIMER1_TCR_CRST_Pos 1 /*!< TIMER1 TCR: CRST Position */ -#define TIMER1_TCR_CRST_Msk (0x01UL << TIMER1_TCR_CRST_Pos) /*!< TIMER1 TCR: CRST Mask */ - -// ---------------------------------------- TIMER1_TC ------------------------------------------- -#define TIMER1_TC_TC_Pos 0 /*!< TIMER1 TC: TC Position */ -#define TIMER1_TC_TC_Msk (0xffffffffUL << TIMER1_TC_TC_Pos) /*!< TIMER1 TC: TC Mask */ - -// ---------------------------------------- TIMER1_PR ------------------------------------------- -#define TIMER1_PR_PM_Pos 0 /*!< TIMER1 PR: PM Position */ -#define TIMER1_PR_PM_Msk (0xffffffffUL << TIMER1_PR_PM_Pos) /*!< TIMER1 PR: PM Mask */ - -// ---------------------------------------- TIMER1_PC ------------------------------------------- -#define TIMER1_PC_PC_Pos 0 /*!< TIMER1 PC: PC Position */ -#define TIMER1_PC_PC_Msk (0xffffffffUL << TIMER1_PC_PC_Pos) /*!< TIMER1 PC: PC Mask */ - -// --------------------------------------- TIMER1_MCR ------------------------------------------- -#define TIMER1_MCR_MR0I_Pos 0 /*!< TIMER1 MCR: MR0I Position */ -#define TIMER1_MCR_MR0I_Msk (0x01UL << TIMER1_MCR_MR0I_Pos) /*!< TIMER1 MCR: MR0I Mask */ -#define TIMER1_MCR_MR0R_Pos 1 /*!< TIMER1 MCR: MR0R Position */ -#define TIMER1_MCR_MR0R_Msk (0x01UL << TIMER1_MCR_MR0R_Pos) /*!< TIMER1 MCR: MR0R Mask */ -#define TIMER1_MCR_MR0S_Pos 2 /*!< TIMER1 MCR: MR0S Position */ -#define TIMER1_MCR_MR0S_Msk (0x01UL << TIMER1_MCR_MR0S_Pos) /*!< TIMER1 MCR: MR0S Mask */ -#define TIMER1_MCR_MR1I_Pos 3 /*!< TIMER1 MCR: MR1I Position */ -#define TIMER1_MCR_MR1I_Msk (0x01UL << TIMER1_MCR_MR1I_Pos) /*!< TIMER1 MCR: MR1I Mask */ -#define TIMER1_MCR_MR1R_Pos 4 /*!< TIMER1 MCR: MR1R Position */ -#define TIMER1_MCR_MR1R_Msk (0x01UL << TIMER1_MCR_MR1R_Pos) /*!< TIMER1 MCR: MR1R Mask */ -#define TIMER1_MCR_MR1S_Pos 5 /*!< TIMER1 MCR: MR1S Position */ -#define TIMER1_MCR_MR1S_Msk (0x01UL << TIMER1_MCR_MR1S_Pos) /*!< TIMER1 MCR: MR1S Mask */ -#define TIMER1_MCR_MR2I_Pos 6 /*!< TIMER1 MCR: MR2I Position */ -#define TIMER1_MCR_MR2I_Msk (0x01UL << TIMER1_MCR_MR2I_Pos) /*!< TIMER1 MCR: MR2I Mask */ -#define TIMER1_MCR_MR2R_Pos 7 /*!< TIMER1 MCR: MR2R Position */ -#define TIMER1_MCR_MR2R_Msk (0x01UL << TIMER1_MCR_MR2R_Pos) /*!< TIMER1 MCR: MR2R Mask */ -#define TIMER1_MCR_MR2S_Pos 8 /*!< TIMER1 MCR: MR2S Position */ -#define TIMER1_MCR_MR2S_Msk (0x01UL << TIMER1_MCR_MR2S_Pos) /*!< TIMER1 MCR: MR2S Mask */ -#define TIMER1_MCR_MR3I_Pos 9 /*!< TIMER1 MCR: MR3I Position */ -#define TIMER1_MCR_MR3I_Msk (0x01UL << TIMER1_MCR_MR3I_Pos) /*!< TIMER1 MCR: MR3I Mask */ -#define TIMER1_MCR_MR3R_Pos 10 /*!< TIMER1 MCR: MR3R Position */ -#define TIMER1_MCR_MR3R_Msk (0x01UL << TIMER1_MCR_MR3R_Pos) /*!< TIMER1 MCR: MR3R Mask */ -#define TIMER1_MCR_MR3S_Pos 11 /*!< TIMER1 MCR: MR3S Position */ -#define TIMER1_MCR_MR3S_Msk (0x01UL << TIMER1_MCR_MR3S_Pos) /*!< TIMER1 MCR: MR3S Mask */ - -// --------------------------------------- TIMER1_MR0 ------------------------------------------- -#define TIMER1_MR0_MATCH_Pos 0 /*!< TIMER1 MR0: MATCH Position */ -#define TIMER1_MR0_MATCH_Msk (0xffffffffUL << TIMER1_MR0_MATCH_Pos) /*!< TIMER1 MR0: MATCH Mask */ - -// --------------------------------------- TIMER1_MR1 ------------------------------------------- -#define TIMER1_MR1_MATCH_Pos 0 /*!< TIMER1 MR1: MATCH Position */ -#define TIMER1_MR1_MATCH_Msk (0xffffffffUL << TIMER1_MR1_MATCH_Pos) /*!< TIMER1 MR1: MATCH Mask */ - -// --------------------------------------- TIMER1_MR2 ------------------------------------------- -#define TIMER1_MR2_MATCH_Pos 0 /*!< TIMER1 MR2: MATCH Position */ -#define TIMER1_MR2_MATCH_Msk (0xffffffffUL << TIMER1_MR2_MATCH_Pos) /*!< TIMER1 MR2: MATCH Mask */ - -// --------------------------------------- TIMER1_MR3 ------------------------------------------- -#define TIMER1_MR3_MATCH_Pos 0 /*!< TIMER1 MR3: MATCH Position */ -#define TIMER1_MR3_MATCH_Msk (0xffffffffUL << TIMER1_MR3_MATCH_Pos) /*!< TIMER1 MR3: MATCH Mask */ - -// --------------------------------------- TIMER1_CCR ------------------------------------------- -#define TIMER1_CCR_CAP0RE_Pos 0 /*!< TIMER1 CCR: CAP0RE Position */ -#define TIMER1_CCR_CAP0RE_Msk (0x01UL << TIMER1_CCR_CAP0RE_Pos) /*!< TIMER1 CCR: CAP0RE Mask */ -#define TIMER1_CCR_CAP0FE_Pos 1 /*!< TIMER1 CCR: CAP0FE Position */ -#define TIMER1_CCR_CAP0FE_Msk (0x01UL << TIMER1_CCR_CAP0FE_Pos) /*!< TIMER1 CCR: CAP0FE Mask */ -#define TIMER1_CCR_CAP0I_Pos 2 /*!< TIMER1 CCR: CAP0I Position */ -#define TIMER1_CCR_CAP0I_Msk (0x01UL << TIMER1_CCR_CAP0I_Pos) /*!< TIMER1 CCR: CAP0I Mask */ -#define TIMER1_CCR_CAP1RE_Pos 3 /*!< TIMER1 CCR: CAP1RE Position */ -#define TIMER1_CCR_CAP1RE_Msk (0x01UL << TIMER1_CCR_CAP1RE_Pos) /*!< TIMER1 CCR: CAP1RE Mask */ -#define TIMER1_CCR_CAP1FE_Pos 4 /*!< TIMER1 CCR: CAP1FE Position */ -#define TIMER1_CCR_CAP1FE_Msk (0x01UL << TIMER1_CCR_CAP1FE_Pos) /*!< TIMER1 CCR: CAP1FE Mask */ -#define TIMER1_CCR_CAP1I_Pos 5 /*!< TIMER1 CCR: CAP1I Position */ -#define TIMER1_CCR_CAP1I_Msk (0x01UL << TIMER1_CCR_CAP1I_Pos) /*!< TIMER1 CCR: CAP1I Mask */ -#define TIMER1_CCR_CAP2RE_Pos 6 /*!< TIMER1 CCR: CAP2RE Position */ -#define TIMER1_CCR_CAP2RE_Msk (0x01UL << TIMER1_CCR_CAP2RE_Pos) /*!< TIMER1 CCR: CAP2RE Mask */ -#define TIMER1_CCR_CAP2FE_Pos 7 /*!< TIMER1 CCR: CAP2FE Position */ -#define TIMER1_CCR_CAP2FE_Msk (0x01UL << TIMER1_CCR_CAP2FE_Pos) /*!< TIMER1 CCR: CAP2FE Mask */ -#define TIMER1_CCR_CAP2I_Pos 8 /*!< TIMER1 CCR: CAP2I Position */ -#define TIMER1_CCR_CAP2I_Msk (0x01UL << TIMER1_CCR_CAP2I_Pos) /*!< TIMER1 CCR: CAP2I Mask */ -#define TIMER1_CCR_CAP3RE_Pos 9 /*!< TIMER1 CCR: CAP3RE Position */ -#define TIMER1_CCR_CAP3RE_Msk (0x01UL << TIMER1_CCR_CAP3RE_Pos) /*!< TIMER1 CCR: CAP3RE Mask */ -#define TIMER1_CCR_CAP3FE_Pos 10 /*!< TIMER1 CCR: CAP3FE Position */ -#define TIMER1_CCR_CAP3FE_Msk (0x01UL << TIMER1_CCR_CAP3FE_Pos) /*!< TIMER1 CCR: CAP3FE Mask */ -#define TIMER1_CCR_CAP3I_Pos 11 /*!< TIMER1 CCR: CAP3I Position */ -#define TIMER1_CCR_CAP3I_Msk (0x01UL << TIMER1_CCR_CAP3I_Pos) /*!< TIMER1 CCR: CAP3I Mask */ - -// --------------------------------------- TIMER1_CR0 ------------------------------------------- -#define TIMER1_CR0_CAP_Pos 0 /*!< TIMER1 CR0: CAP Position */ -#define TIMER1_CR0_CAP_Msk (0xffffffffUL << TIMER1_CR0_CAP_Pos) /*!< TIMER1 CR0: CAP Mask */ - -// --------------------------------------- TIMER1_CR1 ------------------------------------------- -#define TIMER1_CR1_CAP_Pos 0 /*!< TIMER1 CR1: CAP Position */ -#define TIMER1_CR1_CAP_Msk (0xffffffffUL << TIMER1_CR1_CAP_Pos) /*!< TIMER1 CR1: CAP Mask */ - -// --------------------------------------- TIMER1_CR2 ------------------------------------------- -#define TIMER1_CR2_CAP_Pos 0 /*!< TIMER1 CR2: CAP Position */ -#define TIMER1_CR2_CAP_Msk (0xffffffffUL << TIMER1_CR2_CAP_Pos) /*!< TIMER1 CR2: CAP Mask */ - -// --------------------------------------- TIMER1_CR3 ------------------------------------------- -#define TIMER1_CR3_CAP_Pos 0 /*!< TIMER1 CR3: CAP Position */ -#define TIMER1_CR3_CAP_Msk (0xffffffffUL << TIMER1_CR3_CAP_Pos) /*!< TIMER1 CR3: CAP Mask */ - -// --------------------------------------- TIMER1_EMR ------------------------------------------- -#define TIMER1_EMR_EM0_Pos 0 /*!< TIMER1 EMR: EM0 Position */ -#define TIMER1_EMR_EM0_Msk (0x01UL << TIMER1_EMR_EM0_Pos) /*!< TIMER1 EMR: EM0 Mask */ -#define TIMER1_EMR_EM1_Pos 1 /*!< TIMER1 EMR: EM1 Position */ -#define TIMER1_EMR_EM1_Msk (0x01UL << TIMER1_EMR_EM1_Pos) /*!< TIMER1 EMR: EM1 Mask */ -#define TIMER1_EMR_EM2_Pos 2 /*!< TIMER1 EMR: EM2 Position */ -#define TIMER1_EMR_EM2_Msk (0x01UL << TIMER1_EMR_EM2_Pos) /*!< TIMER1 EMR: EM2 Mask */ -#define TIMER1_EMR_EM3_Pos 3 /*!< TIMER1 EMR: EM3 Position */ -#define TIMER1_EMR_EM3_Msk (0x01UL << TIMER1_EMR_EM3_Pos) /*!< TIMER1 EMR: EM3 Mask */ -#define TIMER1_EMR_EMC0_Pos 4 /*!< TIMER1 EMR: EMC0 Position */ -#define TIMER1_EMR_EMC0_Msk (0x03UL << TIMER1_EMR_EMC0_Pos) /*!< TIMER1 EMR: EMC0 Mask */ -#define TIMER1_EMR_EMC1_Pos 6 /*!< TIMER1 EMR: EMC1 Position */ -#define TIMER1_EMR_EMC1_Msk (0x03UL << TIMER1_EMR_EMC1_Pos) /*!< TIMER1 EMR: EMC1 Mask */ -#define TIMER1_EMR_EMC2_Pos 8 /*!< TIMER1 EMR: EMC2 Position */ -#define TIMER1_EMR_EMC2_Msk (0x03UL << TIMER1_EMR_EMC2_Pos) /*!< TIMER1 EMR: EMC2 Mask */ -#define TIMER1_EMR_EMC3_Pos 10 /*!< TIMER1 EMR: EMC3 Position */ -#define TIMER1_EMR_EMC3_Msk (0x03UL << TIMER1_EMR_EMC3_Pos) /*!< TIMER1 EMR: EMC3 Mask */ - -// --------------------------------------- TIMER1_CTCR ------------------------------------------ -#define TIMER1_CTCR_CTMODE_Pos 0 /*!< TIMER1 CTCR: CTMODE Position */ -#define TIMER1_CTCR_CTMODE_Msk (0x03UL << TIMER1_CTCR_CTMODE_Pos) /*!< TIMER1 CTCR: CTMODE Mask */ -#define TIMER1_CTCR_CINSEL_Pos 2 /*!< TIMER1 CTCR: CINSEL Position */ -#define TIMER1_CTCR_CINSEL_Msk (0x03UL << TIMER1_CTCR_CINSEL_Pos) /*!< TIMER1 CTCR: CINSEL Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- TIMER2 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- TIMER2_IR ------------------------------------------- -#define TIMER2_IR_MR0INT_Pos 0 /*!< TIMER2 IR: MR0INT Position */ -#define TIMER2_IR_MR0INT_Msk (0x01UL << TIMER2_IR_MR0INT_Pos) /*!< TIMER2 IR: MR0INT Mask */ -#define TIMER2_IR_MR1INT_Pos 1 /*!< TIMER2 IR: MR1INT Position */ -#define TIMER2_IR_MR1INT_Msk (0x01UL << TIMER2_IR_MR1INT_Pos) /*!< TIMER2 IR: MR1INT Mask */ -#define TIMER2_IR_MR2INT_Pos 2 /*!< TIMER2 IR: MR2INT Position */ -#define TIMER2_IR_MR2INT_Msk (0x01UL << TIMER2_IR_MR2INT_Pos) /*!< TIMER2 IR: MR2INT Mask */ -#define TIMER2_IR_MR3INT_Pos 3 /*!< TIMER2 IR: MR3INT Position */ -#define TIMER2_IR_MR3INT_Msk (0x01UL << TIMER2_IR_MR3INT_Pos) /*!< TIMER2 IR: MR3INT Mask */ -#define TIMER2_IR_CR0INT_Pos 4 /*!< TIMER2 IR: CR0INT Position */ -#define TIMER2_IR_CR0INT_Msk (0x01UL << TIMER2_IR_CR0INT_Pos) /*!< TIMER2 IR: CR0INT Mask */ -#define TIMER2_IR_CR1INT_Pos 5 /*!< TIMER2 IR: CR1INT Position */ -#define TIMER2_IR_CR1INT_Msk (0x01UL << TIMER2_IR_CR1INT_Pos) /*!< TIMER2 IR: CR1INT Mask */ -#define TIMER2_IR_CR2INT_Pos 6 /*!< TIMER2 IR: CR2INT Position */ -#define TIMER2_IR_CR2INT_Msk (0x01UL << TIMER2_IR_CR2INT_Pos) /*!< TIMER2 IR: CR2INT Mask */ -#define TIMER2_IR_CR3INT_Pos 7 /*!< TIMER2 IR: CR3INT Position */ -#define TIMER2_IR_CR3INT_Msk (0x01UL << TIMER2_IR_CR3INT_Pos) /*!< TIMER2 IR: CR3INT Mask */ - -// --------------------------------------- TIMER2_TCR ------------------------------------------- -#define TIMER2_TCR_CEN_Pos 0 /*!< TIMER2 TCR: CEN Position */ -#define TIMER2_TCR_CEN_Msk (0x01UL << TIMER2_TCR_CEN_Pos) /*!< TIMER2 TCR: CEN Mask */ -#define TIMER2_TCR_CRST_Pos 1 /*!< TIMER2 TCR: CRST Position */ -#define TIMER2_TCR_CRST_Msk (0x01UL << TIMER2_TCR_CRST_Pos) /*!< TIMER2 TCR: CRST Mask */ - -// ---------------------------------------- TIMER2_TC ------------------------------------------- -#define TIMER2_TC_TC_Pos 0 /*!< TIMER2 TC: TC Position */ -#define TIMER2_TC_TC_Msk (0xffffffffUL << TIMER2_TC_TC_Pos) /*!< TIMER2 TC: TC Mask */ - -// ---------------------------------------- TIMER2_PR ------------------------------------------- -#define TIMER2_PR_PM_Pos 0 /*!< TIMER2 PR: PM Position */ -#define TIMER2_PR_PM_Msk (0xffffffffUL << TIMER2_PR_PM_Pos) /*!< TIMER2 PR: PM Mask */ - -// ---------------------------------------- TIMER2_PC ------------------------------------------- -#define TIMER2_PC_PC_Pos 0 /*!< TIMER2 PC: PC Position */ -#define TIMER2_PC_PC_Msk (0xffffffffUL << TIMER2_PC_PC_Pos) /*!< TIMER2 PC: PC Mask */ - -// --------------------------------------- TIMER2_MCR ------------------------------------------- -#define TIMER2_MCR_MR0I_Pos 0 /*!< TIMER2 MCR: MR0I Position */ -#define TIMER2_MCR_MR0I_Msk (0x01UL << TIMER2_MCR_MR0I_Pos) /*!< TIMER2 MCR: MR0I Mask */ -#define TIMER2_MCR_MR0R_Pos 1 /*!< TIMER2 MCR: MR0R Position */ -#define TIMER2_MCR_MR0R_Msk (0x01UL << TIMER2_MCR_MR0R_Pos) /*!< TIMER2 MCR: MR0R Mask */ -#define TIMER2_MCR_MR0S_Pos 2 /*!< TIMER2 MCR: MR0S Position */ -#define TIMER2_MCR_MR0S_Msk (0x01UL << TIMER2_MCR_MR0S_Pos) /*!< TIMER2 MCR: MR0S Mask */ -#define TIMER2_MCR_MR1I_Pos 3 /*!< TIMER2 MCR: MR1I Position */ -#define TIMER2_MCR_MR1I_Msk (0x01UL << TIMER2_MCR_MR1I_Pos) /*!< TIMER2 MCR: MR1I Mask */ -#define TIMER2_MCR_MR1R_Pos 4 /*!< TIMER2 MCR: MR1R Position */ -#define TIMER2_MCR_MR1R_Msk (0x01UL << TIMER2_MCR_MR1R_Pos) /*!< TIMER2 MCR: MR1R Mask */ -#define TIMER2_MCR_MR1S_Pos 5 /*!< TIMER2 MCR: MR1S Position */ -#define TIMER2_MCR_MR1S_Msk (0x01UL << TIMER2_MCR_MR1S_Pos) /*!< TIMER2 MCR: MR1S Mask */ -#define TIMER2_MCR_MR2I_Pos 6 /*!< TIMER2 MCR: MR2I Position */ -#define TIMER2_MCR_MR2I_Msk (0x01UL << TIMER2_MCR_MR2I_Pos) /*!< TIMER2 MCR: MR2I Mask */ -#define TIMER2_MCR_MR2R_Pos 7 /*!< TIMER2 MCR: MR2R Position */ -#define TIMER2_MCR_MR2R_Msk (0x01UL << TIMER2_MCR_MR2R_Pos) /*!< TIMER2 MCR: MR2R Mask */ -#define TIMER2_MCR_MR2S_Pos 8 /*!< TIMER2 MCR: MR2S Position */ -#define TIMER2_MCR_MR2S_Msk (0x01UL << TIMER2_MCR_MR2S_Pos) /*!< TIMER2 MCR: MR2S Mask */ -#define TIMER2_MCR_MR3I_Pos 9 /*!< TIMER2 MCR: MR3I Position */ -#define TIMER2_MCR_MR3I_Msk (0x01UL << TIMER2_MCR_MR3I_Pos) /*!< TIMER2 MCR: MR3I Mask */ -#define TIMER2_MCR_MR3R_Pos 10 /*!< TIMER2 MCR: MR3R Position */ -#define TIMER2_MCR_MR3R_Msk (0x01UL << TIMER2_MCR_MR3R_Pos) /*!< TIMER2 MCR: MR3R Mask */ -#define TIMER2_MCR_MR3S_Pos 11 /*!< TIMER2 MCR: MR3S Position */ -#define TIMER2_MCR_MR3S_Msk (0x01UL << TIMER2_MCR_MR3S_Pos) /*!< TIMER2 MCR: MR3S Mask */ - -// --------------------------------------- TIMER2_MR0 ------------------------------------------- -#define TIMER2_MR0_MATCH_Pos 0 /*!< TIMER2 MR0: MATCH Position */ -#define TIMER2_MR0_MATCH_Msk (0xffffffffUL << TIMER2_MR0_MATCH_Pos) /*!< TIMER2 MR0: MATCH Mask */ - -// --------------------------------------- TIMER2_MR1 ------------------------------------------- -#define TIMER2_MR1_MATCH_Pos 0 /*!< TIMER2 MR1: MATCH Position */ -#define TIMER2_MR1_MATCH_Msk (0xffffffffUL << TIMER2_MR1_MATCH_Pos) /*!< TIMER2 MR1: MATCH Mask */ - -// --------------------------------------- TIMER2_MR2 ------------------------------------------- -#define TIMER2_MR2_MATCH_Pos 0 /*!< TIMER2 MR2: MATCH Position */ -#define TIMER2_MR2_MATCH_Msk (0xffffffffUL << TIMER2_MR2_MATCH_Pos) /*!< TIMER2 MR2: MATCH Mask */ - -// --------------------------------------- TIMER2_MR3 ------------------------------------------- -#define TIMER2_MR3_MATCH_Pos 0 /*!< TIMER2 MR3: MATCH Position */ -#define TIMER2_MR3_MATCH_Msk (0xffffffffUL << TIMER2_MR3_MATCH_Pos) /*!< TIMER2 MR3: MATCH Mask */ - -// --------------------------------------- TIMER2_CCR ------------------------------------------- -#define TIMER2_CCR_CAP0RE_Pos 0 /*!< TIMER2 CCR: CAP0RE Position */ -#define TIMER2_CCR_CAP0RE_Msk (0x01UL << TIMER2_CCR_CAP0RE_Pos) /*!< TIMER2 CCR: CAP0RE Mask */ -#define TIMER2_CCR_CAP0FE_Pos 1 /*!< TIMER2 CCR: CAP0FE Position */ -#define TIMER2_CCR_CAP0FE_Msk (0x01UL << TIMER2_CCR_CAP0FE_Pos) /*!< TIMER2 CCR: CAP0FE Mask */ -#define TIMER2_CCR_CAP0I_Pos 2 /*!< TIMER2 CCR: CAP0I Position */ -#define TIMER2_CCR_CAP0I_Msk (0x01UL << TIMER2_CCR_CAP0I_Pos) /*!< TIMER2 CCR: CAP0I Mask */ -#define TIMER2_CCR_CAP1RE_Pos 3 /*!< TIMER2 CCR: CAP1RE Position */ -#define TIMER2_CCR_CAP1RE_Msk (0x01UL << TIMER2_CCR_CAP1RE_Pos) /*!< TIMER2 CCR: CAP1RE Mask */ -#define TIMER2_CCR_CAP1FE_Pos 4 /*!< TIMER2 CCR: CAP1FE Position */ -#define TIMER2_CCR_CAP1FE_Msk (0x01UL << TIMER2_CCR_CAP1FE_Pos) /*!< TIMER2 CCR: CAP1FE Mask */ -#define TIMER2_CCR_CAP1I_Pos 5 /*!< TIMER2 CCR: CAP1I Position */ -#define TIMER2_CCR_CAP1I_Msk (0x01UL << TIMER2_CCR_CAP1I_Pos) /*!< TIMER2 CCR: CAP1I Mask */ -#define TIMER2_CCR_CAP2RE_Pos 6 /*!< TIMER2 CCR: CAP2RE Position */ -#define TIMER2_CCR_CAP2RE_Msk (0x01UL << TIMER2_CCR_CAP2RE_Pos) /*!< TIMER2 CCR: CAP2RE Mask */ -#define TIMER2_CCR_CAP2FE_Pos 7 /*!< TIMER2 CCR: CAP2FE Position */ -#define TIMER2_CCR_CAP2FE_Msk (0x01UL << TIMER2_CCR_CAP2FE_Pos) /*!< TIMER2 CCR: CAP2FE Mask */ -#define TIMER2_CCR_CAP2I_Pos 8 /*!< TIMER2 CCR: CAP2I Position */ -#define TIMER2_CCR_CAP2I_Msk (0x01UL << TIMER2_CCR_CAP2I_Pos) /*!< TIMER2 CCR: CAP2I Mask */ -#define TIMER2_CCR_CAP3RE_Pos 9 /*!< TIMER2 CCR: CAP3RE Position */ -#define TIMER2_CCR_CAP3RE_Msk (0x01UL << TIMER2_CCR_CAP3RE_Pos) /*!< TIMER2 CCR: CAP3RE Mask */ -#define TIMER2_CCR_CAP3FE_Pos 10 /*!< TIMER2 CCR: CAP3FE Position */ -#define TIMER2_CCR_CAP3FE_Msk (0x01UL << TIMER2_CCR_CAP3FE_Pos) /*!< TIMER2 CCR: CAP3FE Mask */ -#define TIMER2_CCR_CAP3I_Pos 11 /*!< TIMER2 CCR: CAP3I Position */ -#define TIMER2_CCR_CAP3I_Msk (0x01UL << TIMER2_CCR_CAP3I_Pos) /*!< TIMER2 CCR: CAP3I Mask */ - -// --------------------------------------- TIMER2_CR0 ------------------------------------------- -#define TIMER2_CR0_CAP_Pos 0 /*!< TIMER2 CR0: CAP Position */ -#define TIMER2_CR0_CAP_Msk (0xffffffffUL << TIMER2_CR0_CAP_Pos) /*!< TIMER2 CR0: CAP Mask */ - -// --------------------------------------- TIMER2_CR1 ------------------------------------------- -#define TIMER2_CR1_CAP_Pos 0 /*!< TIMER2 CR1: CAP Position */ -#define TIMER2_CR1_CAP_Msk (0xffffffffUL << TIMER2_CR1_CAP_Pos) /*!< TIMER2 CR1: CAP Mask */ - -// --------------------------------------- TIMER2_CR2 ------------------------------------------- -#define TIMER2_CR2_CAP_Pos 0 /*!< TIMER2 CR2: CAP Position */ -#define TIMER2_CR2_CAP_Msk (0xffffffffUL << TIMER2_CR2_CAP_Pos) /*!< TIMER2 CR2: CAP Mask */ - -// --------------------------------------- TIMER2_CR3 ------------------------------------------- -#define TIMER2_CR3_CAP_Pos 0 /*!< TIMER2 CR3: CAP Position */ -#define TIMER2_CR3_CAP_Msk (0xffffffffUL << TIMER2_CR3_CAP_Pos) /*!< TIMER2 CR3: CAP Mask */ - -// --------------------------------------- TIMER2_EMR ------------------------------------------- -#define TIMER2_EMR_EM0_Pos 0 /*!< TIMER2 EMR: EM0 Position */ -#define TIMER2_EMR_EM0_Msk (0x01UL << TIMER2_EMR_EM0_Pos) /*!< TIMER2 EMR: EM0 Mask */ -#define TIMER2_EMR_EM1_Pos 1 /*!< TIMER2 EMR: EM1 Position */ -#define TIMER2_EMR_EM1_Msk (0x01UL << TIMER2_EMR_EM1_Pos) /*!< TIMER2 EMR: EM1 Mask */ -#define TIMER2_EMR_EM2_Pos 2 /*!< TIMER2 EMR: EM2 Position */ -#define TIMER2_EMR_EM2_Msk (0x01UL << TIMER2_EMR_EM2_Pos) /*!< TIMER2 EMR: EM2 Mask */ -#define TIMER2_EMR_EM3_Pos 3 /*!< TIMER2 EMR: EM3 Position */ -#define TIMER2_EMR_EM3_Msk (0x01UL << TIMER2_EMR_EM3_Pos) /*!< TIMER2 EMR: EM3 Mask */ -#define TIMER2_EMR_EMC0_Pos 4 /*!< TIMER2 EMR: EMC0 Position */ -#define TIMER2_EMR_EMC0_Msk (0x03UL << TIMER2_EMR_EMC0_Pos) /*!< TIMER2 EMR: EMC0 Mask */ -#define TIMER2_EMR_EMC1_Pos 6 /*!< TIMER2 EMR: EMC1 Position */ -#define TIMER2_EMR_EMC1_Msk (0x03UL << TIMER2_EMR_EMC1_Pos) /*!< TIMER2 EMR: EMC1 Mask */ -#define TIMER2_EMR_EMC2_Pos 8 /*!< TIMER2 EMR: EMC2 Position */ -#define TIMER2_EMR_EMC2_Msk (0x03UL << TIMER2_EMR_EMC2_Pos) /*!< TIMER2 EMR: EMC2 Mask */ -#define TIMER2_EMR_EMC3_Pos 10 /*!< TIMER2 EMR: EMC3 Position */ -#define TIMER2_EMR_EMC3_Msk (0x03UL << TIMER2_EMR_EMC3_Pos) /*!< TIMER2 EMR: EMC3 Mask */ - -// --------------------------------------- TIMER2_CTCR ------------------------------------------ -#define TIMER2_CTCR_CTMODE_Pos 0 /*!< TIMER2 CTCR: CTMODE Position */ -#define TIMER2_CTCR_CTMODE_Msk (0x03UL << TIMER2_CTCR_CTMODE_Pos) /*!< TIMER2 CTCR: CTMODE Mask */ -#define TIMER2_CTCR_CINSEL_Pos 2 /*!< TIMER2 CTCR: CINSEL Position */ -#define TIMER2_CTCR_CINSEL_Msk (0x03UL << TIMER2_CTCR_CINSEL_Pos) /*!< TIMER2 CTCR: CINSEL Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- TIMER3 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- TIMER3_IR ------------------------------------------- -#define TIMER3_IR_MR0INT_Pos 0 /*!< TIMER3 IR: MR0INT Position */ -#define TIMER3_IR_MR0INT_Msk (0x01UL << TIMER3_IR_MR0INT_Pos) /*!< TIMER3 IR: MR0INT Mask */ -#define TIMER3_IR_MR1INT_Pos 1 /*!< TIMER3 IR: MR1INT Position */ -#define TIMER3_IR_MR1INT_Msk (0x01UL << TIMER3_IR_MR1INT_Pos) /*!< TIMER3 IR: MR1INT Mask */ -#define TIMER3_IR_MR2INT_Pos 2 /*!< TIMER3 IR: MR2INT Position */ -#define TIMER3_IR_MR2INT_Msk (0x01UL << TIMER3_IR_MR2INT_Pos) /*!< TIMER3 IR: MR2INT Mask */ -#define TIMER3_IR_MR3INT_Pos 3 /*!< TIMER3 IR: MR3INT Position */ -#define TIMER3_IR_MR3INT_Msk (0x01UL << TIMER3_IR_MR3INT_Pos) /*!< TIMER3 IR: MR3INT Mask */ -#define TIMER3_IR_CR0INT_Pos 4 /*!< TIMER3 IR: CR0INT Position */ -#define TIMER3_IR_CR0INT_Msk (0x01UL << TIMER3_IR_CR0INT_Pos) /*!< TIMER3 IR: CR0INT Mask */ -#define TIMER3_IR_CR1INT_Pos 5 /*!< TIMER3 IR: CR1INT Position */ -#define TIMER3_IR_CR1INT_Msk (0x01UL << TIMER3_IR_CR1INT_Pos) /*!< TIMER3 IR: CR1INT Mask */ -#define TIMER3_IR_CR2INT_Pos 6 /*!< TIMER3 IR: CR2INT Position */ -#define TIMER3_IR_CR2INT_Msk (0x01UL << TIMER3_IR_CR2INT_Pos) /*!< TIMER3 IR: CR2INT Mask */ -#define TIMER3_IR_CR3INT_Pos 7 /*!< TIMER3 IR: CR3INT Position */ -#define TIMER3_IR_CR3INT_Msk (0x01UL << TIMER3_IR_CR3INT_Pos) /*!< TIMER3 IR: CR3INT Mask */ - -// --------------------------------------- TIMER3_TCR ------------------------------------------- -#define TIMER3_TCR_CEN_Pos 0 /*!< TIMER3 TCR: CEN Position */ -#define TIMER3_TCR_CEN_Msk (0x01UL << TIMER3_TCR_CEN_Pos) /*!< TIMER3 TCR: CEN Mask */ -#define TIMER3_TCR_CRST_Pos 1 /*!< TIMER3 TCR: CRST Position */ -#define TIMER3_TCR_CRST_Msk (0x01UL << TIMER3_TCR_CRST_Pos) /*!< TIMER3 TCR: CRST Mask */ - -// ---------------------------------------- TIMER3_TC ------------------------------------------- -#define TIMER3_TC_TC_Pos 0 /*!< TIMER3 TC: TC Position */ -#define TIMER3_TC_TC_Msk (0xffffffffUL << TIMER3_TC_TC_Pos) /*!< TIMER3 TC: TC Mask */ - -// ---------------------------------------- TIMER3_PR ------------------------------------------- -#define TIMER3_PR_PM_Pos 0 /*!< TIMER3 PR: PM Position */ -#define TIMER3_PR_PM_Msk (0xffffffffUL << TIMER3_PR_PM_Pos) /*!< TIMER3 PR: PM Mask */ - -// ---------------------------------------- TIMER3_PC ------------------------------------------- -#define TIMER3_PC_PC_Pos 0 /*!< TIMER3 PC: PC Position */ -#define TIMER3_PC_PC_Msk (0xffffffffUL << TIMER3_PC_PC_Pos) /*!< TIMER3 PC: PC Mask */ - -// --------------------------------------- TIMER3_MCR ------------------------------------------- -#define TIMER3_MCR_MR0I_Pos 0 /*!< TIMER3 MCR: MR0I Position */ -#define TIMER3_MCR_MR0I_Msk (0x01UL << TIMER3_MCR_MR0I_Pos) /*!< TIMER3 MCR: MR0I Mask */ -#define TIMER3_MCR_MR0R_Pos 1 /*!< TIMER3 MCR: MR0R Position */ -#define TIMER3_MCR_MR0R_Msk (0x01UL << TIMER3_MCR_MR0R_Pos) /*!< TIMER3 MCR: MR0R Mask */ -#define TIMER3_MCR_MR0S_Pos 2 /*!< TIMER3 MCR: MR0S Position */ -#define TIMER3_MCR_MR0S_Msk (0x01UL << TIMER3_MCR_MR0S_Pos) /*!< TIMER3 MCR: MR0S Mask */ -#define TIMER3_MCR_MR1I_Pos 3 /*!< TIMER3 MCR: MR1I Position */ -#define TIMER3_MCR_MR1I_Msk (0x01UL << TIMER3_MCR_MR1I_Pos) /*!< TIMER3 MCR: MR1I Mask */ -#define TIMER3_MCR_MR1R_Pos 4 /*!< TIMER3 MCR: MR1R Position */ -#define TIMER3_MCR_MR1R_Msk (0x01UL << TIMER3_MCR_MR1R_Pos) /*!< TIMER3 MCR: MR1R Mask */ -#define TIMER3_MCR_MR1S_Pos 5 /*!< TIMER3 MCR: MR1S Position */ -#define TIMER3_MCR_MR1S_Msk (0x01UL << TIMER3_MCR_MR1S_Pos) /*!< TIMER3 MCR: MR1S Mask */ -#define TIMER3_MCR_MR2I_Pos 6 /*!< TIMER3 MCR: MR2I Position */ -#define TIMER3_MCR_MR2I_Msk (0x01UL << TIMER3_MCR_MR2I_Pos) /*!< TIMER3 MCR: MR2I Mask */ -#define TIMER3_MCR_MR2R_Pos 7 /*!< TIMER3 MCR: MR2R Position */ -#define TIMER3_MCR_MR2R_Msk (0x01UL << TIMER3_MCR_MR2R_Pos) /*!< TIMER3 MCR: MR2R Mask */ -#define TIMER3_MCR_MR2S_Pos 8 /*!< TIMER3 MCR: MR2S Position */ -#define TIMER3_MCR_MR2S_Msk (0x01UL << TIMER3_MCR_MR2S_Pos) /*!< TIMER3 MCR: MR2S Mask */ -#define TIMER3_MCR_MR3I_Pos 9 /*!< TIMER3 MCR: MR3I Position */ -#define TIMER3_MCR_MR3I_Msk (0x01UL << TIMER3_MCR_MR3I_Pos) /*!< TIMER3 MCR: MR3I Mask */ -#define TIMER3_MCR_MR3R_Pos 10 /*!< TIMER3 MCR: MR3R Position */ -#define TIMER3_MCR_MR3R_Msk (0x01UL << TIMER3_MCR_MR3R_Pos) /*!< TIMER3 MCR: MR3R Mask */ -#define TIMER3_MCR_MR3S_Pos 11 /*!< TIMER3 MCR: MR3S Position */ -#define TIMER3_MCR_MR3S_Msk (0x01UL << TIMER3_MCR_MR3S_Pos) /*!< TIMER3 MCR: MR3S Mask */ - -// --------------------------------------- TIMER3_MR0 ------------------------------------------- -#define TIMER3_MR0_MATCH_Pos 0 /*!< TIMER3 MR0: MATCH Position */ -#define TIMER3_MR0_MATCH_Msk (0xffffffffUL << TIMER3_MR0_MATCH_Pos) /*!< TIMER3 MR0: MATCH Mask */ - -// --------------------------------------- TIMER3_MR1 ------------------------------------------- -#define TIMER3_MR1_MATCH_Pos 0 /*!< TIMER3 MR1: MATCH Position */ -#define TIMER3_MR1_MATCH_Msk (0xffffffffUL << TIMER3_MR1_MATCH_Pos) /*!< TIMER3 MR1: MATCH Mask */ - -// --------------------------------------- TIMER3_MR2 ------------------------------------------- -#define TIMER3_MR2_MATCH_Pos 0 /*!< TIMER3 MR2: MATCH Position */ -#define TIMER3_MR2_MATCH_Msk (0xffffffffUL << TIMER3_MR2_MATCH_Pos) /*!< TIMER3 MR2: MATCH Mask */ - -// --------------------------------------- TIMER3_MR3 ------------------------------------------- -#define TIMER3_MR3_MATCH_Pos 0 /*!< TIMER3 MR3: MATCH Position */ -#define TIMER3_MR3_MATCH_Msk (0xffffffffUL << TIMER3_MR3_MATCH_Pos) /*!< TIMER3 MR3: MATCH Mask */ - -// --------------------------------------- TIMER3_CCR ------------------------------------------- -#define TIMER3_CCR_CAP0RE_Pos 0 /*!< TIMER3 CCR: CAP0RE Position */ -#define TIMER3_CCR_CAP0RE_Msk (0x01UL << TIMER3_CCR_CAP0RE_Pos) /*!< TIMER3 CCR: CAP0RE Mask */ -#define TIMER3_CCR_CAP0FE_Pos 1 /*!< TIMER3 CCR: CAP0FE Position */ -#define TIMER3_CCR_CAP0FE_Msk (0x01UL << TIMER3_CCR_CAP0FE_Pos) /*!< TIMER3 CCR: CAP0FE Mask */ -#define TIMER3_CCR_CAP0I_Pos 2 /*!< TIMER3 CCR: CAP0I Position */ -#define TIMER3_CCR_CAP0I_Msk (0x01UL << TIMER3_CCR_CAP0I_Pos) /*!< TIMER3 CCR: CAP0I Mask */ -#define TIMER3_CCR_CAP1RE_Pos 3 /*!< TIMER3 CCR: CAP1RE Position */ -#define TIMER3_CCR_CAP1RE_Msk (0x01UL << TIMER3_CCR_CAP1RE_Pos) /*!< TIMER3 CCR: CAP1RE Mask */ -#define TIMER3_CCR_CAP1FE_Pos 4 /*!< TIMER3 CCR: CAP1FE Position */ -#define TIMER3_CCR_CAP1FE_Msk (0x01UL << TIMER3_CCR_CAP1FE_Pos) /*!< TIMER3 CCR: CAP1FE Mask */ -#define TIMER3_CCR_CAP1I_Pos 5 /*!< TIMER3 CCR: CAP1I Position */ -#define TIMER3_CCR_CAP1I_Msk (0x01UL << TIMER3_CCR_CAP1I_Pos) /*!< TIMER3 CCR: CAP1I Mask */ -#define TIMER3_CCR_CAP2RE_Pos 6 /*!< TIMER3 CCR: CAP2RE Position */ -#define TIMER3_CCR_CAP2RE_Msk (0x01UL << TIMER3_CCR_CAP2RE_Pos) /*!< TIMER3 CCR: CAP2RE Mask */ -#define TIMER3_CCR_CAP2FE_Pos 7 /*!< TIMER3 CCR: CAP2FE Position */ -#define TIMER3_CCR_CAP2FE_Msk (0x01UL << TIMER3_CCR_CAP2FE_Pos) /*!< TIMER3 CCR: CAP2FE Mask */ -#define TIMER3_CCR_CAP2I_Pos 8 /*!< TIMER3 CCR: CAP2I Position */ -#define TIMER3_CCR_CAP2I_Msk (0x01UL << TIMER3_CCR_CAP2I_Pos) /*!< TIMER3 CCR: CAP2I Mask */ -#define TIMER3_CCR_CAP3RE_Pos 9 /*!< TIMER3 CCR: CAP3RE Position */ -#define TIMER3_CCR_CAP3RE_Msk (0x01UL << TIMER3_CCR_CAP3RE_Pos) /*!< TIMER3 CCR: CAP3RE Mask */ -#define TIMER3_CCR_CAP3FE_Pos 10 /*!< TIMER3 CCR: CAP3FE Position */ -#define TIMER3_CCR_CAP3FE_Msk (0x01UL << TIMER3_CCR_CAP3FE_Pos) /*!< TIMER3 CCR: CAP3FE Mask */ -#define TIMER3_CCR_CAP3I_Pos 11 /*!< TIMER3 CCR: CAP3I Position */ -#define TIMER3_CCR_CAP3I_Msk (0x01UL << TIMER3_CCR_CAP3I_Pos) /*!< TIMER3 CCR: CAP3I Mask */ - -// --------------------------------------- TIMER3_CR0 ------------------------------------------- -#define TIMER3_CR0_CAP_Pos 0 /*!< TIMER3 CR0: CAP Position */ -#define TIMER3_CR0_CAP_Msk (0xffffffffUL << TIMER3_CR0_CAP_Pos) /*!< TIMER3 CR0: CAP Mask */ - -// --------------------------------------- TIMER3_CR1 ------------------------------------------- -#define TIMER3_CR1_CAP_Pos 0 /*!< TIMER3 CR1: CAP Position */ -#define TIMER3_CR1_CAP_Msk (0xffffffffUL << TIMER3_CR1_CAP_Pos) /*!< TIMER3 CR1: CAP Mask */ - -// --------------------------------------- TIMER3_CR2 ------------------------------------------- -#define TIMER3_CR2_CAP_Pos 0 /*!< TIMER3 CR2: CAP Position */ -#define TIMER3_CR2_CAP_Msk (0xffffffffUL << TIMER3_CR2_CAP_Pos) /*!< TIMER3 CR2: CAP Mask */ - -// --------------------------------------- TIMER3_CR3 ------------------------------------------- -#define TIMER3_CR3_CAP_Pos 0 /*!< TIMER3 CR3: CAP Position */ -#define TIMER3_CR3_CAP_Msk (0xffffffffUL << TIMER3_CR3_CAP_Pos) /*!< TIMER3 CR3: CAP Mask */ - -// --------------------------------------- TIMER3_EMR ------------------------------------------- -#define TIMER3_EMR_EM0_Pos 0 /*!< TIMER3 EMR: EM0 Position */ -#define TIMER3_EMR_EM0_Msk (0x01UL << TIMER3_EMR_EM0_Pos) /*!< TIMER3 EMR: EM0 Mask */ -#define TIMER3_EMR_EM1_Pos 1 /*!< TIMER3 EMR: EM1 Position */ -#define TIMER3_EMR_EM1_Msk (0x01UL << TIMER3_EMR_EM1_Pos) /*!< TIMER3 EMR: EM1 Mask */ -#define TIMER3_EMR_EM2_Pos 2 /*!< TIMER3 EMR: EM2 Position */ -#define TIMER3_EMR_EM2_Msk (0x01UL << TIMER3_EMR_EM2_Pos) /*!< TIMER3 EMR: EM2 Mask */ -#define TIMER3_EMR_EM3_Pos 3 /*!< TIMER3 EMR: EM3 Position */ -#define TIMER3_EMR_EM3_Msk (0x01UL << TIMER3_EMR_EM3_Pos) /*!< TIMER3 EMR: EM3 Mask */ -#define TIMER3_EMR_EMC0_Pos 4 /*!< TIMER3 EMR: EMC0 Position */ -#define TIMER3_EMR_EMC0_Msk (0x03UL << TIMER3_EMR_EMC0_Pos) /*!< TIMER3 EMR: EMC0 Mask */ -#define TIMER3_EMR_EMC1_Pos 6 /*!< TIMER3 EMR: EMC1 Position */ -#define TIMER3_EMR_EMC1_Msk (0x03UL << TIMER3_EMR_EMC1_Pos) /*!< TIMER3 EMR: EMC1 Mask */ -#define TIMER3_EMR_EMC2_Pos 8 /*!< TIMER3 EMR: EMC2 Position */ -#define TIMER3_EMR_EMC2_Msk (0x03UL << TIMER3_EMR_EMC2_Pos) /*!< TIMER3 EMR: EMC2 Mask */ -#define TIMER3_EMR_EMC3_Pos 10 /*!< TIMER3 EMR: EMC3 Position */ -#define TIMER3_EMR_EMC3_Msk (0x03UL << TIMER3_EMR_EMC3_Pos) /*!< TIMER3 EMR: EMC3 Mask */ - -// --------------------------------------- TIMER3_CTCR ------------------------------------------ -#define TIMER3_CTCR_CTMODE_Pos 0 /*!< TIMER3 CTCR: CTMODE Position */ -#define TIMER3_CTCR_CTMODE_Msk (0x03UL << TIMER3_CTCR_CTMODE_Pos) /*!< TIMER3 CTCR: CTMODE Mask */ -#define TIMER3_CTCR_CINSEL_Pos 2 /*!< TIMER3 CTCR: CINSEL Position */ -#define TIMER3_CTCR_CINSEL_Msk (0x03UL << TIMER3_CTCR_CINSEL_Pos) /*!< TIMER3 CTCR: CINSEL Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- SCU Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- SCU_SFSP0_0 ------------------------------------------ -#define SCU_SFSP0_0_MODE_Pos 0 /*!< SCU SFSP0_0: MODE Position */ -#define SCU_SFSP0_0_MODE_Msk (0x07UL << SCU_SFSP0_0_MODE_Pos) /*!< SCU SFSP0_0: MODE Mask */ -#define SCU_SFSP0_0_EPD_Pos 3 /*!< SCU SFSP0_0: EPD Position */ -#define SCU_SFSP0_0_EPD_Msk (0x01UL << SCU_SFSP0_0_EPD_Pos) /*!< SCU SFSP0_0: EPD Mask */ -#define SCU_SFSP0_0_EPUN_Pos 4 /*!< SCU SFSP0_0: EPUN Position */ -#define SCU_SFSP0_0_EPUN_Msk (0x01UL << SCU_SFSP0_0_EPUN_Pos) /*!< SCU SFSP0_0: EPUN Mask */ -#define SCU_SFSP0_0_EHS_Pos 5 /*!< SCU SFSP0_0: EHS Position */ -#define SCU_SFSP0_0_EHS_Msk (0x01UL << SCU_SFSP0_0_EHS_Pos) /*!< SCU SFSP0_0: EHS Mask */ -#define SCU_SFSP0_0_EZI_Pos 6 /*!< SCU SFSP0_0: EZI Position */ -#define SCU_SFSP0_0_EZI_Msk (0x01UL << SCU_SFSP0_0_EZI_Pos) /*!< SCU SFSP0_0: EZI Mask */ - -// --------------------------------------- SCU_SFSP0_1 ------------------------------------------ -#define SCU_SFSP0_1_MODE_Pos 0 /*!< SCU SFSP0_1: MODE Position */ -#define SCU_SFSP0_1_MODE_Msk (0x07UL << SCU_SFSP0_1_MODE_Pos) /*!< SCU SFSP0_1: MODE Mask */ -#define SCU_SFSP0_1_EPD_Pos 3 /*!< SCU SFSP0_1: EPD Position */ -#define SCU_SFSP0_1_EPD_Msk (0x01UL << SCU_SFSP0_1_EPD_Pos) /*!< SCU SFSP0_1: EPD Mask */ -#define SCU_SFSP0_1_EPUN_Pos 4 /*!< SCU SFSP0_1: EPUN Position */ -#define SCU_SFSP0_1_EPUN_Msk (0x01UL << SCU_SFSP0_1_EPUN_Pos) /*!< SCU SFSP0_1: EPUN Mask */ -#define SCU_SFSP0_1_EHS_Pos 5 /*!< SCU SFSP0_1: EHS Position */ -#define SCU_SFSP0_1_EHS_Msk (0x01UL << SCU_SFSP0_1_EHS_Pos) /*!< SCU SFSP0_1: EHS Mask */ -#define SCU_SFSP0_1_EZI_Pos 6 /*!< SCU SFSP0_1: EZI Position */ -#define SCU_SFSP0_1_EZI_Msk (0x01UL << SCU_SFSP0_1_EZI_Pos) /*!< SCU SFSP0_1: EZI Mask */ - -// --------------------------------------- SCU_SFSP1_0 ------------------------------------------ -#define SCU_SFSP1_0_MODE_Pos 0 /*!< SCU SFSP1_0: MODE Position */ -#define SCU_SFSP1_0_MODE_Msk (0x07UL << SCU_SFSP1_0_MODE_Pos) /*!< SCU SFSP1_0: MODE Mask */ -#define SCU_SFSP1_0_EPD_Pos 3 /*!< SCU SFSP1_0: EPD Position */ -#define SCU_SFSP1_0_EPD_Msk (0x01UL << SCU_SFSP1_0_EPD_Pos) /*!< SCU SFSP1_0: EPD Mask */ -#define SCU_SFSP1_0_EPUN_Pos 4 /*!< SCU SFSP1_0: EPUN Position */ -#define SCU_SFSP1_0_EPUN_Msk (0x01UL << SCU_SFSP1_0_EPUN_Pos) /*!< SCU SFSP1_0: EPUN Mask */ -#define SCU_SFSP1_0_EHS_Pos 5 /*!< SCU SFSP1_0: EHS Position */ -#define SCU_SFSP1_0_EHS_Msk (0x01UL << SCU_SFSP1_0_EHS_Pos) /*!< SCU SFSP1_0: EHS Mask */ -#define SCU_SFSP1_0_EZI_Pos 6 /*!< SCU SFSP1_0: EZI Position */ -#define SCU_SFSP1_0_EZI_Msk (0x01UL << SCU_SFSP1_0_EZI_Pos) /*!< SCU SFSP1_0: EZI Mask */ -#define SCU_SFSP1_0_EHD_Pos 8 /*!< SCU SFSP1_0: EHD Position */ -#define SCU_SFSP1_0_EHD_Msk (0x03UL << SCU_SFSP1_0_EHD_Pos) /*!< SCU SFSP1_0: EHD Mask */ - -// --------------------------------------- SCU_SFSP1_1 ------------------------------------------ -#define SCU_SFSP1_1_MODE_Pos 0 /*!< SCU SFSP1_1: MODE Position */ -#define SCU_SFSP1_1_MODE_Msk (0x07UL << SCU_SFSP1_1_MODE_Pos) /*!< SCU SFSP1_1: MODE Mask */ -#define SCU_SFSP1_1_EPD_Pos 3 /*!< SCU SFSP1_1: EPD Position */ -#define SCU_SFSP1_1_EPD_Msk (0x01UL << SCU_SFSP1_1_EPD_Pos) /*!< SCU SFSP1_1: EPD Mask */ -#define SCU_SFSP1_1_EPUN_Pos 4 /*!< SCU SFSP1_1: EPUN Position */ -#define SCU_SFSP1_1_EPUN_Msk (0x01UL << SCU_SFSP1_1_EPUN_Pos) /*!< SCU SFSP1_1: EPUN Mask */ -#define SCU_SFSP1_1_EHS_Pos 5 /*!< SCU SFSP1_1: EHS Position */ -#define SCU_SFSP1_1_EHS_Msk (0x01UL << SCU_SFSP1_1_EHS_Pos) /*!< SCU SFSP1_1: EHS Mask */ -#define SCU_SFSP1_1_EZI_Pos 6 /*!< SCU SFSP1_1: EZI Position */ -#define SCU_SFSP1_1_EZI_Msk (0x01UL << SCU_SFSP1_1_EZI_Pos) /*!< SCU SFSP1_1: EZI Mask */ -#define SCU_SFSP1_1_EHD_Pos 8 /*!< SCU SFSP1_1: EHD Position */ -#define SCU_SFSP1_1_EHD_Msk (0x03UL << SCU_SFSP1_1_EHD_Pos) /*!< SCU SFSP1_1: EHD Mask */ - -// --------------------------------------- SCU_SFSP1_2 ------------------------------------------ -#define SCU_SFSP1_2_MODE_Pos 0 /*!< SCU SFSP1_2: MODE Position */ -#define SCU_SFSP1_2_MODE_Msk (0x07UL << SCU_SFSP1_2_MODE_Pos) /*!< SCU SFSP1_2: MODE Mask */ -#define SCU_SFSP1_2_EPD_Pos 3 /*!< SCU SFSP1_2: EPD Position */ -#define SCU_SFSP1_2_EPD_Msk (0x01UL << SCU_SFSP1_2_EPD_Pos) /*!< SCU SFSP1_2: EPD Mask */ -#define SCU_SFSP1_2_EPUN_Pos 4 /*!< SCU SFSP1_2: EPUN Position */ -#define SCU_SFSP1_2_EPUN_Msk (0x01UL << SCU_SFSP1_2_EPUN_Pos) /*!< SCU SFSP1_2: EPUN Mask */ -#define SCU_SFSP1_2_EHS_Pos 5 /*!< SCU SFSP1_2: EHS Position */ -#define SCU_SFSP1_2_EHS_Msk (0x01UL << SCU_SFSP1_2_EHS_Pos) /*!< SCU SFSP1_2: EHS Mask */ -#define SCU_SFSP1_2_EZI_Pos 6 /*!< SCU SFSP1_2: EZI Position */ -#define SCU_SFSP1_2_EZI_Msk (0x01UL << SCU_SFSP1_2_EZI_Pos) /*!< SCU SFSP1_2: EZI Mask */ -#define SCU_SFSP1_2_EHD_Pos 8 /*!< SCU SFSP1_2: EHD Position */ -#define SCU_SFSP1_2_EHD_Msk (0x03UL << SCU_SFSP1_2_EHD_Pos) /*!< SCU SFSP1_2: EHD Mask */ - -// --------------------------------------- SCU_SFSP1_3 ------------------------------------------ -#define SCU_SFSP1_3_MODE_Pos 0 /*!< SCU SFSP1_3: MODE Position */ -#define SCU_SFSP1_3_MODE_Msk (0x07UL << SCU_SFSP1_3_MODE_Pos) /*!< SCU SFSP1_3: MODE Mask */ -#define SCU_SFSP1_3_EPD_Pos 3 /*!< SCU SFSP1_3: EPD Position */ -#define SCU_SFSP1_3_EPD_Msk (0x01UL << SCU_SFSP1_3_EPD_Pos) /*!< SCU SFSP1_3: EPD Mask */ -#define SCU_SFSP1_3_EPUN_Pos 4 /*!< SCU SFSP1_3: EPUN Position */ -#define SCU_SFSP1_3_EPUN_Msk (0x01UL << SCU_SFSP1_3_EPUN_Pos) /*!< SCU SFSP1_3: EPUN Mask */ -#define SCU_SFSP1_3_EHS_Pos 5 /*!< SCU SFSP1_3: EHS Position */ -#define SCU_SFSP1_3_EHS_Msk (0x01UL << SCU_SFSP1_3_EHS_Pos) /*!< SCU SFSP1_3: EHS Mask */ -#define SCU_SFSP1_3_EZI_Pos 6 /*!< SCU SFSP1_3: EZI Position */ -#define SCU_SFSP1_3_EZI_Msk (0x01UL << SCU_SFSP1_3_EZI_Pos) /*!< SCU SFSP1_3: EZI Mask */ -#define SCU_SFSP1_3_EHD_Pos 8 /*!< SCU SFSP1_3: EHD Position */ -#define SCU_SFSP1_3_EHD_Msk (0x03UL << SCU_SFSP1_3_EHD_Pos) /*!< SCU SFSP1_3: EHD Mask */ - -// --------------------------------------- SCU_SFSP1_4 ------------------------------------------ -#define SCU_SFSP1_4_MODE_Pos 0 /*!< SCU SFSP1_4: MODE Position */ -#define SCU_SFSP1_4_MODE_Msk (0x07UL << SCU_SFSP1_4_MODE_Pos) /*!< SCU SFSP1_4: MODE Mask */ -#define SCU_SFSP1_4_EPD_Pos 3 /*!< SCU SFSP1_4: EPD Position */ -#define SCU_SFSP1_4_EPD_Msk (0x01UL << SCU_SFSP1_4_EPD_Pos) /*!< SCU SFSP1_4: EPD Mask */ -#define SCU_SFSP1_4_EPUN_Pos 4 /*!< SCU SFSP1_4: EPUN Position */ -#define SCU_SFSP1_4_EPUN_Msk (0x01UL << SCU_SFSP1_4_EPUN_Pos) /*!< SCU SFSP1_4: EPUN Mask */ -#define SCU_SFSP1_4_EHS_Pos 5 /*!< SCU SFSP1_4: EHS Position */ -#define SCU_SFSP1_4_EHS_Msk (0x01UL << SCU_SFSP1_4_EHS_Pos) /*!< SCU SFSP1_4: EHS Mask */ -#define SCU_SFSP1_4_EZI_Pos 6 /*!< SCU SFSP1_4: EZI Position */ -#define SCU_SFSP1_4_EZI_Msk (0x01UL << SCU_SFSP1_4_EZI_Pos) /*!< SCU SFSP1_4: EZI Mask */ -#define SCU_SFSP1_4_EHD_Pos 8 /*!< SCU SFSP1_4: EHD Position */ -#define SCU_SFSP1_4_EHD_Msk (0x03UL << SCU_SFSP1_4_EHD_Pos) /*!< SCU SFSP1_4: EHD Mask */ - -// --------------------------------------- SCU_SFSP1_5 ------------------------------------------ -#define SCU_SFSP1_5_MODE_Pos 0 /*!< SCU SFSP1_5: MODE Position */ -#define SCU_SFSP1_5_MODE_Msk (0x07UL << SCU_SFSP1_5_MODE_Pos) /*!< SCU SFSP1_5: MODE Mask */ -#define SCU_SFSP1_5_EPD_Pos 3 /*!< SCU SFSP1_5: EPD Position */ -#define SCU_SFSP1_5_EPD_Msk (0x01UL << SCU_SFSP1_5_EPD_Pos) /*!< SCU SFSP1_5: EPD Mask */ -#define SCU_SFSP1_5_EPUN_Pos 4 /*!< SCU SFSP1_5: EPUN Position */ -#define SCU_SFSP1_5_EPUN_Msk (0x01UL << SCU_SFSP1_5_EPUN_Pos) /*!< SCU SFSP1_5: EPUN Mask */ -#define SCU_SFSP1_5_EHS_Pos 5 /*!< SCU SFSP1_5: EHS Position */ -#define SCU_SFSP1_5_EHS_Msk (0x01UL << SCU_SFSP1_5_EHS_Pos) /*!< SCU SFSP1_5: EHS Mask */ -#define SCU_SFSP1_5_EZI_Pos 6 /*!< SCU SFSP1_5: EZI Position */ -#define SCU_SFSP1_5_EZI_Msk (0x01UL << SCU_SFSP1_5_EZI_Pos) /*!< SCU SFSP1_5: EZI Mask */ -#define SCU_SFSP1_5_EHD_Pos 8 /*!< SCU SFSP1_5: EHD Position */ -#define SCU_SFSP1_5_EHD_Msk (0x03UL << SCU_SFSP1_5_EHD_Pos) /*!< SCU SFSP1_5: EHD Mask */ - -// --------------------------------------- SCU_SFSP1_6 ------------------------------------------ -#define SCU_SFSP1_6_MODE_Pos 0 /*!< SCU SFSP1_6: MODE Position */ -#define SCU_SFSP1_6_MODE_Msk (0x07UL << SCU_SFSP1_6_MODE_Pos) /*!< SCU SFSP1_6: MODE Mask */ -#define SCU_SFSP1_6_EPD_Pos 3 /*!< SCU SFSP1_6: EPD Position */ -#define SCU_SFSP1_6_EPD_Msk (0x01UL << SCU_SFSP1_6_EPD_Pos) /*!< SCU SFSP1_6: EPD Mask */ -#define SCU_SFSP1_6_EPUN_Pos 4 /*!< SCU SFSP1_6: EPUN Position */ -#define SCU_SFSP1_6_EPUN_Msk (0x01UL << SCU_SFSP1_6_EPUN_Pos) /*!< SCU SFSP1_6: EPUN Mask */ -#define SCU_SFSP1_6_EHS_Pos 5 /*!< SCU SFSP1_6: EHS Position */ -#define SCU_SFSP1_6_EHS_Msk (0x01UL << SCU_SFSP1_6_EHS_Pos) /*!< SCU SFSP1_6: EHS Mask */ -#define SCU_SFSP1_6_EZI_Pos 6 /*!< SCU SFSP1_6: EZI Position */ -#define SCU_SFSP1_6_EZI_Msk (0x01UL << SCU_SFSP1_6_EZI_Pos) /*!< SCU SFSP1_6: EZI Mask */ -#define SCU_SFSP1_6_EHD_Pos 8 /*!< SCU SFSP1_6: EHD Position */ -#define SCU_SFSP1_6_EHD_Msk (0x03UL << SCU_SFSP1_6_EHD_Pos) /*!< SCU SFSP1_6: EHD Mask */ - -// --------------------------------------- SCU_SFSP1_7 ------------------------------------------ -#define SCU_SFSP1_7_MODE_Pos 0 /*!< SCU SFSP1_7: MODE Position */ -#define SCU_SFSP1_7_MODE_Msk (0x07UL << SCU_SFSP1_7_MODE_Pos) /*!< SCU SFSP1_7: MODE Mask */ -#define SCU_SFSP1_7_EPD_Pos 3 /*!< SCU SFSP1_7: EPD Position */ -#define SCU_SFSP1_7_EPD_Msk (0x01UL << SCU_SFSP1_7_EPD_Pos) /*!< SCU SFSP1_7: EPD Mask */ -#define SCU_SFSP1_7_EPUN_Pos 4 /*!< SCU SFSP1_7: EPUN Position */ -#define SCU_SFSP1_7_EPUN_Msk (0x01UL << SCU_SFSP1_7_EPUN_Pos) /*!< SCU SFSP1_7: EPUN Mask */ -#define SCU_SFSP1_7_EHS_Pos 5 /*!< SCU SFSP1_7: EHS Position */ -#define SCU_SFSP1_7_EHS_Msk (0x01UL << SCU_SFSP1_7_EHS_Pos) /*!< SCU SFSP1_7: EHS Mask */ -#define SCU_SFSP1_7_EZI_Pos 6 /*!< SCU SFSP1_7: EZI Position */ -#define SCU_SFSP1_7_EZI_Msk (0x01UL << SCU_SFSP1_7_EZI_Pos) /*!< SCU SFSP1_7: EZI Mask */ -#define SCU_SFSP1_7_EHD_Pos 8 /*!< SCU SFSP1_7: EHD Position */ -#define SCU_SFSP1_7_EHD_Msk (0x03UL << SCU_SFSP1_7_EHD_Pos) /*!< SCU SFSP1_7: EHD Mask */ - -// --------------------------------------- SCU_SFSP1_8 ------------------------------------------ -#define SCU_SFSP1_8_MODE_Pos 0 /*!< SCU SFSP1_8: MODE Position */ -#define SCU_SFSP1_8_MODE_Msk (0x07UL << SCU_SFSP1_8_MODE_Pos) /*!< SCU SFSP1_8: MODE Mask */ -#define SCU_SFSP1_8_EPD_Pos 3 /*!< SCU SFSP1_8: EPD Position */ -#define SCU_SFSP1_8_EPD_Msk (0x01UL << SCU_SFSP1_8_EPD_Pos) /*!< SCU SFSP1_8: EPD Mask */ -#define SCU_SFSP1_8_EPUN_Pos 4 /*!< SCU SFSP1_8: EPUN Position */ -#define SCU_SFSP1_8_EPUN_Msk (0x01UL << SCU_SFSP1_8_EPUN_Pos) /*!< SCU SFSP1_8: EPUN Mask */ -#define SCU_SFSP1_8_EHS_Pos 5 /*!< SCU SFSP1_8: EHS Position */ -#define SCU_SFSP1_8_EHS_Msk (0x01UL << SCU_SFSP1_8_EHS_Pos) /*!< SCU SFSP1_8: EHS Mask */ -#define SCU_SFSP1_8_EZI_Pos 6 /*!< SCU SFSP1_8: EZI Position */ -#define SCU_SFSP1_8_EZI_Msk (0x01UL << SCU_SFSP1_8_EZI_Pos) /*!< SCU SFSP1_8: EZI Mask */ -#define SCU_SFSP1_8_EHD_Pos 8 /*!< SCU SFSP1_8: EHD Position */ -#define SCU_SFSP1_8_EHD_Msk (0x03UL << SCU_SFSP1_8_EHD_Pos) /*!< SCU SFSP1_8: EHD Mask */ - -// --------------------------------------- SCU_SFSP1_9 ------------------------------------------ -#define SCU_SFSP1_9_MODE_Pos 0 /*!< SCU SFSP1_9: MODE Position */ -#define SCU_SFSP1_9_MODE_Msk (0x07UL << SCU_SFSP1_9_MODE_Pos) /*!< SCU SFSP1_9: MODE Mask */ -#define SCU_SFSP1_9_EPD_Pos 3 /*!< SCU SFSP1_9: EPD Position */ -#define SCU_SFSP1_9_EPD_Msk (0x01UL << SCU_SFSP1_9_EPD_Pos) /*!< SCU SFSP1_9: EPD Mask */ -#define SCU_SFSP1_9_EPUN_Pos 4 /*!< SCU SFSP1_9: EPUN Position */ -#define SCU_SFSP1_9_EPUN_Msk (0x01UL << SCU_SFSP1_9_EPUN_Pos) /*!< SCU SFSP1_9: EPUN Mask */ -#define SCU_SFSP1_9_EHS_Pos 5 /*!< SCU SFSP1_9: EHS Position */ -#define SCU_SFSP1_9_EHS_Msk (0x01UL << SCU_SFSP1_9_EHS_Pos) /*!< SCU SFSP1_9: EHS Mask */ -#define SCU_SFSP1_9_EZI_Pos 6 /*!< SCU SFSP1_9: EZI Position */ -#define SCU_SFSP1_9_EZI_Msk (0x01UL << SCU_SFSP1_9_EZI_Pos) /*!< SCU SFSP1_9: EZI Mask */ -#define SCU_SFSP1_9_EHD_Pos 8 /*!< SCU SFSP1_9: EHD Position */ -#define SCU_SFSP1_9_EHD_Msk (0x03UL << SCU_SFSP1_9_EHD_Pos) /*!< SCU SFSP1_9: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_10 ------------------------------------------ -#define SCU_SFSP1_10_MODE_Pos 0 /*!< SCU SFSP1_10: MODE Position */ -#define SCU_SFSP1_10_MODE_Msk (0x07UL << SCU_SFSP1_10_MODE_Pos) /*!< SCU SFSP1_10: MODE Mask */ -#define SCU_SFSP1_10_EPD_Pos 3 /*!< SCU SFSP1_10: EPD Position */ -#define SCU_SFSP1_10_EPD_Msk (0x01UL << SCU_SFSP1_10_EPD_Pos) /*!< SCU SFSP1_10: EPD Mask */ -#define SCU_SFSP1_10_EPUN_Pos 4 /*!< SCU SFSP1_10: EPUN Position */ -#define SCU_SFSP1_10_EPUN_Msk (0x01UL << SCU_SFSP1_10_EPUN_Pos) /*!< SCU SFSP1_10: EPUN Mask */ -#define SCU_SFSP1_10_EHS_Pos 5 /*!< SCU SFSP1_10: EHS Position */ -#define SCU_SFSP1_10_EHS_Msk (0x01UL << SCU_SFSP1_10_EHS_Pos) /*!< SCU SFSP1_10: EHS Mask */ -#define SCU_SFSP1_10_EZI_Pos 6 /*!< SCU SFSP1_10: EZI Position */ -#define SCU_SFSP1_10_EZI_Msk (0x01UL << SCU_SFSP1_10_EZI_Pos) /*!< SCU SFSP1_10: EZI Mask */ -#define SCU_SFSP1_10_EHD_Pos 8 /*!< SCU SFSP1_10: EHD Position */ -#define SCU_SFSP1_10_EHD_Msk (0x03UL << SCU_SFSP1_10_EHD_Pos) /*!< SCU SFSP1_10: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_11 ------------------------------------------ -#define SCU_SFSP1_11_MODE_Pos 0 /*!< SCU SFSP1_11: MODE Position */ -#define SCU_SFSP1_11_MODE_Msk (0x07UL << SCU_SFSP1_11_MODE_Pos) /*!< SCU SFSP1_11: MODE Mask */ -#define SCU_SFSP1_11_EPD_Pos 3 /*!< SCU SFSP1_11: EPD Position */ -#define SCU_SFSP1_11_EPD_Msk (0x01UL << SCU_SFSP1_11_EPD_Pos) /*!< SCU SFSP1_11: EPD Mask */ -#define SCU_SFSP1_11_EPUN_Pos 4 /*!< SCU SFSP1_11: EPUN Position */ -#define SCU_SFSP1_11_EPUN_Msk (0x01UL << SCU_SFSP1_11_EPUN_Pos) /*!< SCU SFSP1_11: EPUN Mask */ -#define SCU_SFSP1_11_EHS_Pos 5 /*!< SCU SFSP1_11: EHS Position */ -#define SCU_SFSP1_11_EHS_Msk (0x01UL << SCU_SFSP1_11_EHS_Pos) /*!< SCU SFSP1_11: EHS Mask */ -#define SCU_SFSP1_11_EZI_Pos 6 /*!< SCU SFSP1_11: EZI Position */ -#define SCU_SFSP1_11_EZI_Msk (0x01UL << SCU_SFSP1_11_EZI_Pos) /*!< SCU SFSP1_11: EZI Mask */ -#define SCU_SFSP1_11_EHD_Pos 8 /*!< SCU SFSP1_11: EHD Position */ -#define SCU_SFSP1_11_EHD_Msk (0x03UL << SCU_SFSP1_11_EHD_Pos) /*!< SCU SFSP1_11: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_12 ------------------------------------------ -#define SCU_SFSP1_12_MODE_Pos 0 /*!< SCU SFSP1_12: MODE Position */ -#define SCU_SFSP1_12_MODE_Msk (0x07UL << SCU_SFSP1_12_MODE_Pos) /*!< SCU SFSP1_12: MODE Mask */ -#define SCU_SFSP1_12_EPD_Pos 3 /*!< SCU SFSP1_12: EPD Position */ -#define SCU_SFSP1_12_EPD_Msk (0x01UL << SCU_SFSP1_12_EPD_Pos) /*!< SCU SFSP1_12: EPD Mask */ -#define SCU_SFSP1_12_EPUN_Pos 4 /*!< SCU SFSP1_12: EPUN Position */ -#define SCU_SFSP1_12_EPUN_Msk (0x01UL << SCU_SFSP1_12_EPUN_Pos) /*!< SCU SFSP1_12: EPUN Mask */ -#define SCU_SFSP1_12_EHS_Pos 5 /*!< SCU SFSP1_12: EHS Position */ -#define SCU_SFSP1_12_EHS_Msk (0x01UL << SCU_SFSP1_12_EHS_Pos) /*!< SCU SFSP1_12: EHS Mask */ -#define SCU_SFSP1_12_EZI_Pos 6 /*!< SCU SFSP1_12: EZI Position */ -#define SCU_SFSP1_12_EZI_Msk (0x01UL << SCU_SFSP1_12_EZI_Pos) /*!< SCU SFSP1_12: EZI Mask */ -#define SCU_SFSP1_12_EHD_Pos 8 /*!< SCU SFSP1_12: EHD Position */ -#define SCU_SFSP1_12_EHD_Msk (0x03UL << SCU_SFSP1_12_EHD_Pos) /*!< SCU SFSP1_12: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_13 ------------------------------------------ -#define SCU_SFSP1_13_MODE_Pos 0 /*!< SCU SFSP1_13: MODE Position */ -#define SCU_SFSP1_13_MODE_Msk (0x07UL << SCU_SFSP1_13_MODE_Pos) /*!< SCU SFSP1_13: MODE Mask */ -#define SCU_SFSP1_13_EPD_Pos 3 /*!< SCU SFSP1_13: EPD Position */ -#define SCU_SFSP1_13_EPD_Msk (0x01UL << SCU_SFSP1_13_EPD_Pos) /*!< SCU SFSP1_13: EPD Mask */ -#define SCU_SFSP1_13_EPUN_Pos 4 /*!< SCU SFSP1_13: EPUN Position */ -#define SCU_SFSP1_13_EPUN_Msk (0x01UL << SCU_SFSP1_13_EPUN_Pos) /*!< SCU SFSP1_13: EPUN Mask */ -#define SCU_SFSP1_13_EHS_Pos 5 /*!< SCU SFSP1_13: EHS Position */ -#define SCU_SFSP1_13_EHS_Msk (0x01UL << SCU_SFSP1_13_EHS_Pos) /*!< SCU SFSP1_13: EHS Mask */ -#define SCU_SFSP1_13_EZI_Pos 6 /*!< SCU SFSP1_13: EZI Position */ -#define SCU_SFSP1_13_EZI_Msk (0x01UL << SCU_SFSP1_13_EZI_Pos) /*!< SCU SFSP1_13: EZI Mask */ -#define SCU_SFSP1_13_EHD_Pos 8 /*!< SCU SFSP1_13: EHD Position */ -#define SCU_SFSP1_13_EHD_Msk (0x03UL << SCU_SFSP1_13_EHD_Pos) /*!< SCU SFSP1_13: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_14 ------------------------------------------ -#define SCU_SFSP1_14_MODE_Pos 0 /*!< SCU SFSP1_14: MODE Position */ -#define SCU_SFSP1_14_MODE_Msk (0x07UL << SCU_SFSP1_14_MODE_Pos) /*!< SCU SFSP1_14: MODE Mask */ -#define SCU_SFSP1_14_EPD_Pos 3 /*!< SCU SFSP1_14: EPD Position */ -#define SCU_SFSP1_14_EPD_Msk (0x01UL << SCU_SFSP1_14_EPD_Pos) /*!< SCU SFSP1_14: EPD Mask */ -#define SCU_SFSP1_14_EPUN_Pos 4 /*!< SCU SFSP1_14: EPUN Position */ -#define SCU_SFSP1_14_EPUN_Msk (0x01UL << SCU_SFSP1_14_EPUN_Pos) /*!< SCU SFSP1_14: EPUN Mask */ -#define SCU_SFSP1_14_EHS_Pos 5 /*!< SCU SFSP1_14: EHS Position */ -#define SCU_SFSP1_14_EHS_Msk (0x01UL << SCU_SFSP1_14_EHS_Pos) /*!< SCU SFSP1_14: EHS Mask */ -#define SCU_SFSP1_14_EZI_Pos 6 /*!< SCU SFSP1_14: EZI Position */ -#define SCU_SFSP1_14_EZI_Msk (0x01UL << SCU_SFSP1_14_EZI_Pos) /*!< SCU SFSP1_14: EZI Mask */ -#define SCU_SFSP1_14_EHD_Pos 8 /*!< SCU SFSP1_14: EHD Position */ -#define SCU_SFSP1_14_EHD_Msk (0x03UL << SCU_SFSP1_14_EHD_Pos) /*!< SCU SFSP1_14: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_15 ------------------------------------------ -#define SCU_SFSP1_15_MODE_Pos 0 /*!< SCU SFSP1_15: MODE Position */ -#define SCU_SFSP1_15_MODE_Msk (0x07UL << SCU_SFSP1_15_MODE_Pos) /*!< SCU SFSP1_15: MODE Mask */ -#define SCU_SFSP1_15_EPD_Pos 3 /*!< SCU SFSP1_15: EPD Position */ -#define SCU_SFSP1_15_EPD_Msk (0x01UL << SCU_SFSP1_15_EPD_Pos) /*!< SCU SFSP1_15: EPD Mask */ -#define SCU_SFSP1_15_EPUN_Pos 4 /*!< SCU SFSP1_15: EPUN Position */ -#define SCU_SFSP1_15_EPUN_Msk (0x01UL << SCU_SFSP1_15_EPUN_Pos) /*!< SCU SFSP1_15: EPUN Mask */ -#define SCU_SFSP1_15_EHS_Pos 5 /*!< SCU SFSP1_15: EHS Position */ -#define SCU_SFSP1_15_EHS_Msk (0x01UL << SCU_SFSP1_15_EHS_Pos) /*!< SCU SFSP1_15: EHS Mask */ -#define SCU_SFSP1_15_EZI_Pos 6 /*!< SCU SFSP1_15: EZI Position */ -#define SCU_SFSP1_15_EZI_Msk (0x01UL << SCU_SFSP1_15_EZI_Pos) /*!< SCU SFSP1_15: EZI Mask */ -#define SCU_SFSP1_15_EHD_Pos 8 /*!< SCU SFSP1_15: EHD Position */ -#define SCU_SFSP1_15_EHD_Msk (0x03UL << SCU_SFSP1_15_EHD_Pos) /*!< SCU SFSP1_15: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_16 ------------------------------------------ -#define SCU_SFSP1_16_MODE_Pos 0 /*!< SCU SFSP1_16: MODE Position */ -#define SCU_SFSP1_16_MODE_Msk (0x07UL << SCU_SFSP1_16_MODE_Pos) /*!< SCU SFSP1_16: MODE Mask */ -#define SCU_SFSP1_16_EPD_Pos 3 /*!< SCU SFSP1_16: EPD Position */ -#define SCU_SFSP1_16_EPD_Msk (0x01UL << SCU_SFSP1_16_EPD_Pos) /*!< SCU SFSP1_16: EPD Mask */ -#define SCU_SFSP1_16_EPUN_Pos 4 /*!< SCU SFSP1_16: EPUN Position */ -#define SCU_SFSP1_16_EPUN_Msk (0x01UL << SCU_SFSP1_16_EPUN_Pos) /*!< SCU SFSP1_16: EPUN Mask */ -#define SCU_SFSP1_16_EHS_Pos 5 /*!< SCU SFSP1_16: EHS Position */ -#define SCU_SFSP1_16_EHS_Msk (0x01UL << SCU_SFSP1_16_EHS_Pos) /*!< SCU SFSP1_16: EHS Mask */ -#define SCU_SFSP1_16_EZI_Pos 6 /*!< SCU SFSP1_16: EZI Position */ -#define SCU_SFSP1_16_EZI_Msk (0x01UL << SCU_SFSP1_16_EZI_Pos) /*!< SCU SFSP1_16: EZI Mask */ -#define SCU_SFSP1_16_EHD_Pos 8 /*!< SCU SFSP1_16: EHD Position */ -#define SCU_SFSP1_16_EHD_Msk (0x03UL << SCU_SFSP1_16_EHD_Pos) /*!< SCU SFSP1_16: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_17 ------------------------------------------ -#define SCU_SFSP1_17_MODE_Pos 0 /*!< SCU SFSP1_17: MODE Position */ -#define SCU_SFSP1_17_MODE_Msk (0x07UL << SCU_SFSP1_17_MODE_Pos) /*!< SCU SFSP1_17: MODE Mask */ -#define SCU_SFSP1_17_EPD_Pos 3 /*!< SCU SFSP1_17: EPD Position */ -#define SCU_SFSP1_17_EPD_Msk (0x01UL << SCU_SFSP1_17_EPD_Pos) /*!< SCU SFSP1_17: EPD Mask */ -#define SCU_SFSP1_17_EPUN_Pos 4 /*!< SCU SFSP1_17: EPUN Position */ -#define SCU_SFSP1_17_EPUN_Msk (0x01UL << SCU_SFSP1_17_EPUN_Pos) /*!< SCU SFSP1_17: EPUN Mask */ -#define SCU_SFSP1_17_EHS_Pos 5 /*!< SCU SFSP1_17: EHS Position */ -#define SCU_SFSP1_17_EHS_Msk (0x01UL << SCU_SFSP1_17_EHS_Pos) /*!< SCU SFSP1_17: EHS Mask */ -#define SCU_SFSP1_17_EZI_Pos 6 /*!< SCU SFSP1_17: EZI Position */ -#define SCU_SFSP1_17_EZI_Msk (0x01UL << SCU_SFSP1_17_EZI_Pos) /*!< SCU SFSP1_17: EZI Mask */ -#define SCU_SFSP1_17_EHD_Pos 8 /*!< SCU SFSP1_17: EHD Position */ -#define SCU_SFSP1_17_EHD_Msk (0x03UL << SCU_SFSP1_17_EHD_Pos) /*!< SCU SFSP1_17: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_18 ------------------------------------------ -#define SCU_SFSP1_18_MODE_Pos 0 /*!< SCU SFSP1_18: MODE Position */ -#define SCU_SFSP1_18_MODE_Msk (0x07UL << SCU_SFSP1_18_MODE_Pos) /*!< SCU SFSP1_18: MODE Mask */ -#define SCU_SFSP1_18_EPD_Pos 3 /*!< SCU SFSP1_18: EPD Position */ -#define SCU_SFSP1_18_EPD_Msk (0x01UL << SCU_SFSP1_18_EPD_Pos) /*!< SCU SFSP1_18: EPD Mask */ -#define SCU_SFSP1_18_EPUN_Pos 4 /*!< SCU SFSP1_18: EPUN Position */ -#define SCU_SFSP1_18_EPUN_Msk (0x01UL << SCU_SFSP1_18_EPUN_Pos) /*!< SCU SFSP1_18: EPUN Mask */ -#define SCU_SFSP1_18_EHS_Pos 5 /*!< SCU SFSP1_18: EHS Position */ -#define SCU_SFSP1_18_EHS_Msk (0x01UL << SCU_SFSP1_18_EHS_Pos) /*!< SCU SFSP1_18: EHS Mask */ -#define SCU_SFSP1_18_EZI_Pos 6 /*!< SCU SFSP1_18: EZI Position */ -#define SCU_SFSP1_18_EZI_Msk (0x01UL << SCU_SFSP1_18_EZI_Pos) /*!< SCU SFSP1_18: EZI Mask */ -#define SCU_SFSP1_18_EHD_Pos 8 /*!< SCU SFSP1_18: EHD Position */ -#define SCU_SFSP1_18_EHD_Msk (0x03UL << SCU_SFSP1_18_EHD_Pos) /*!< SCU SFSP1_18: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_19 ------------------------------------------ -#define SCU_SFSP1_19_MODE_Pos 0 /*!< SCU SFSP1_19: MODE Position */ -#define SCU_SFSP1_19_MODE_Msk (0x07UL << SCU_SFSP1_19_MODE_Pos) /*!< SCU SFSP1_19: MODE Mask */ -#define SCU_SFSP1_19_EPD_Pos 3 /*!< SCU SFSP1_19: EPD Position */ -#define SCU_SFSP1_19_EPD_Msk (0x01UL << SCU_SFSP1_19_EPD_Pos) /*!< SCU SFSP1_19: EPD Mask */ -#define SCU_SFSP1_19_EPUN_Pos 4 /*!< SCU SFSP1_19: EPUN Position */ -#define SCU_SFSP1_19_EPUN_Msk (0x01UL << SCU_SFSP1_19_EPUN_Pos) /*!< SCU SFSP1_19: EPUN Mask */ -#define SCU_SFSP1_19_EHS_Pos 5 /*!< SCU SFSP1_19: EHS Position */ -#define SCU_SFSP1_19_EHS_Msk (0x01UL << SCU_SFSP1_19_EHS_Pos) /*!< SCU SFSP1_19: EHS Mask */ -#define SCU_SFSP1_19_EZI_Pos 6 /*!< SCU SFSP1_19: EZI Position */ -#define SCU_SFSP1_19_EZI_Msk (0x01UL << SCU_SFSP1_19_EZI_Pos) /*!< SCU SFSP1_19: EZI Mask */ -#define SCU_SFSP1_19_EHD_Pos 8 /*!< SCU SFSP1_19: EHD Position */ -#define SCU_SFSP1_19_EHD_Msk (0x03UL << SCU_SFSP1_19_EHD_Pos) /*!< SCU SFSP1_19: EHD Mask */ - -// -------------------------------------- SCU_SFSP1_20 ------------------------------------------ -#define SCU_SFSP1_20_MODE_Pos 0 /*!< SCU SFSP1_20: MODE Position */ -#define SCU_SFSP1_20_MODE_Msk (0x07UL << SCU_SFSP1_20_MODE_Pos) /*!< SCU SFSP1_20: MODE Mask */ -#define SCU_SFSP1_20_EPD_Pos 3 /*!< SCU SFSP1_20: EPD Position */ -#define SCU_SFSP1_20_EPD_Msk (0x01UL << SCU_SFSP1_20_EPD_Pos) /*!< SCU SFSP1_20: EPD Mask */ -#define SCU_SFSP1_20_EPUN_Pos 4 /*!< SCU SFSP1_20: EPUN Position */ -#define SCU_SFSP1_20_EPUN_Msk (0x01UL << SCU_SFSP1_20_EPUN_Pos) /*!< SCU SFSP1_20: EPUN Mask */ -#define SCU_SFSP1_20_EHS_Pos 5 /*!< SCU SFSP1_20: EHS Position */ -#define SCU_SFSP1_20_EHS_Msk (0x01UL << SCU_SFSP1_20_EHS_Pos) /*!< SCU SFSP1_20: EHS Mask */ -#define SCU_SFSP1_20_EZI_Pos 6 /*!< SCU SFSP1_20: EZI Position */ -#define SCU_SFSP1_20_EZI_Msk (0x01UL << SCU_SFSP1_20_EZI_Pos) /*!< SCU SFSP1_20: EZI Mask */ -#define SCU_SFSP1_20_EHD_Pos 8 /*!< SCU SFSP1_20: EHD Position */ -#define SCU_SFSP1_20_EHD_Msk (0x03UL << SCU_SFSP1_20_EHD_Pos) /*!< SCU SFSP1_20: EHD Mask */ - -// --------------------------------------- SCU_SFSP2_0 ------------------------------------------ -#define SCU_SFSP2_0_MODE_Pos 0 /*!< SCU SFSP2_0: MODE Position */ -#define SCU_SFSP2_0_MODE_Msk (0x07UL << SCU_SFSP2_0_MODE_Pos) /*!< SCU SFSP2_0: MODE Mask */ -#define SCU_SFSP2_0_EPD_Pos 3 /*!< SCU SFSP2_0: EPD Position */ -#define SCU_SFSP2_0_EPD_Msk (0x01UL << SCU_SFSP2_0_EPD_Pos) /*!< SCU SFSP2_0: EPD Mask */ -#define SCU_SFSP2_0_EPUN_Pos 4 /*!< SCU SFSP2_0: EPUN Position */ -#define SCU_SFSP2_0_EPUN_Msk (0x01UL << SCU_SFSP2_0_EPUN_Pos) /*!< SCU SFSP2_0: EPUN Mask */ -#define SCU_SFSP2_0_EHS_Pos 5 /*!< SCU SFSP2_0: EHS Position */ -#define SCU_SFSP2_0_EHS_Msk (0x01UL << SCU_SFSP2_0_EHS_Pos) /*!< SCU SFSP2_0: EHS Mask */ -#define SCU_SFSP2_0_EZI_Pos 6 /*!< SCU SFSP2_0: EZI Position */ -#define SCU_SFSP2_0_EZI_Msk (0x01UL << SCU_SFSP2_0_EZI_Pos) /*!< SCU SFSP2_0: EZI Mask */ -#define SCU_SFSP2_0_EHD_Pos 8 /*!< SCU SFSP2_0: EHD Position */ -#define SCU_SFSP2_0_EHD_Msk (0x03UL << SCU_SFSP2_0_EHD_Pos) /*!< SCU SFSP2_0: EHD Mask */ - -// --------------------------------------- SCU_SFSP2_1 ------------------------------------------ -#define SCU_SFSP2_1_MODE_Pos 0 /*!< SCU SFSP2_1: MODE Position */ -#define SCU_SFSP2_1_MODE_Msk (0x07UL << SCU_SFSP2_1_MODE_Pos) /*!< SCU SFSP2_1: MODE Mask */ -#define SCU_SFSP2_1_EPD_Pos 3 /*!< SCU SFSP2_1: EPD Position */ -#define SCU_SFSP2_1_EPD_Msk (0x01UL << SCU_SFSP2_1_EPD_Pos) /*!< SCU SFSP2_1: EPD Mask */ -#define SCU_SFSP2_1_EPUN_Pos 4 /*!< SCU SFSP2_1: EPUN Position */ -#define SCU_SFSP2_1_EPUN_Msk (0x01UL << SCU_SFSP2_1_EPUN_Pos) /*!< SCU SFSP2_1: EPUN Mask */ -#define SCU_SFSP2_1_EHS_Pos 5 /*!< SCU SFSP2_1: EHS Position */ -#define SCU_SFSP2_1_EHS_Msk (0x01UL << SCU_SFSP2_1_EHS_Pos) /*!< SCU SFSP2_1: EHS Mask */ -#define SCU_SFSP2_1_EZI_Pos 6 /*!< SCU SFSP2_1: EZI Position */ -#define SCU_SFSP2_1_EZI_Msk (0x01UL << SCU_SFSP2_1_EZI_Pos) /*!< SCU SFSP2_1: EZI Mask */ -#define SCU_SFSP2_1_EHD_Pos 8 /*!< SCU SFSP2_1: EHD Position */ -#define SCU_SFSP2_1_EHD_Msk (0x03UL << SCU_SFSP2_1_EHD_Pos) /*!< SCU SFSP2_1: EHD Mask */ - -// --------------------------------------- SCU_SFSP2_2 ------------------------------------------ -#define SCU_SFSP2_2_MODE_Pos 0 /*!< SCU SFSP2_2: MODE Position */ -#define SCU_SFSP2_2_MODE_Msk (0x07UL << SCU_SFSP2_2_MODE_Pos) /*!< SCU SFSP2_2: MODE Mask */ -#define SCU_SFSP2_2_EPD_Pos 3 /*!< SCU SFSP2_2: EPD Position */ -#define SCU_SFSP2_2_EPD_Msk (0x01UL << SCU_SFSP2_2_EPD_Pos) /*!< SCU SFSP2_2: EPD Mask */ -#define SCU_SFSP2_2_EPUN_Pos 4 /*!< SCU SFSP2_2: EPUN Position */ -#define SCU_SFSP2_2_EPUN_Msk (0x01UL << SCU_SFSP2_2_EPUN_Pos) /*!< SCU SFSP2_2: EPUN Mask */ -#define SCU_SFSP2_2_EHS_Pos 5 /*!< SCU SFSP2_2: EHS Position */ -#define SCU_SFSP2_2_EHS_Msk (0x01UL << SCU_SFSP2_2_EHS_Pos) /*!< SCU SFSP2_2: EHS Mask */ -#define SCU_SFSP2_2_EZI_Pos 6 /*!< SCU SFSP2_2: EZI Position */ -#define SCU_SFSP2_2_EZI_Msk (0x01UL << SCU_SFSP2_2_EZI_Pos) /*!< SCU SFSP2_2: EZI Mask */ -#define SCU_SFSP2_2_EHD_Pos 8 /*!< SCU SFSP2_2: EHD Position */ -#define SCU_SFSP2_2_EHD_Msk (0x03UL << SCU_SFSP2_2_EHD_Pos) /*!< SCU SFSP2_2: EHD Mask */ - -// --------------------------------------- SCU_SFSP2_3 ------------------------------------------ -#define SCU_SFSP2_3_MODE_Pos 0 /*!< SCU SFSP2_3: MODE Position */ -#define SCU_SFSP2_3_MODE_Msk (0x07UL << SCU_SFSP2_3_MODE_Pos) /*!< SCU SFSP2_3: MODE Mask */ -#define SCU_SFSP2_3_EPD_Pos 3 /*!< SCU SFSP2_3: EPD Position */ -#define SCU_SFSP2_3_EPD_Msk (0x01UL << SCU_SFSP2_3_EPD_Pos) /*!< SCU SFSP2_3: EPD Mask */ -#define SCU_SFSP2_3_EPUN_Pos 4 /*!< SCU SFSP2_3: EPUN Position */ -#define SCU_SFSP2_3_EPUN_Msk (0x01UL << SCU_SFSP2_3_EPUN_Pos) /*!< SCU SFSP2_3: EPUN Mask */ -#define SCU_SFSP2_3_EHS_Pos 5 /*!< SCU SFSP2_3: EHS Position */ -#define SCU_SFSP2_3_EHS_Msk (0x01UL << SCU_SFSP2_3_EHS_Pos) /*!< SCU SFSP2_3: EHS Mask */ -#define SCU_SFSP2_3_EZI_Pos 6 /*!< SCU SFSP2_3: EZI Position */ -#define SCU_SFSP2_3_EZI_Msk (0x01UL << SCU_SFSP2_3_EZI_Pos) /*!< SCU SFSP2_3: EZI Mask */ -#define SCU_SFSP2_3_EHD_Pos 8 /*!< SCU SFSP2_3: EHD Position */ -#define SCU_SFSP2_3_EHD_Msk (0x03UL << SCU_SFSP2_3_EHD_Pos) /*!< SCU SFSP2_3: EHD Mask */ - -// --------------------------------------- SCU_SFSP2_4 ------------------------------------------ -#define SCU_SFSP2_4_MODE_Pos 0 /*!< SCU SFSP2_4: MODE Position */ -#define SCU_SFSP2_4_MODE_Msk (0x07UL << SCU_SFSP2_4_MODE_Pos) /*!< SCU SFSP2_4: MODE Mask */ -#define SCU_SFSP2_4_EPD_Pos 3 /*!< SCU SFSP2_4: EPD Position */ -#define SCU_SFSP2_4_EPD_Msk (0x01UL << SCU_SFSP2_4_EPD_Pos) /*!< SCU SFSP2_4: EPD Mask */ -#define SCU_SFSP2_4_EPUN_Pos 4 /*!< SCU SFSP2_4: EPUN Position */ -#define SCU_SFSP2_4_EPUN_Msk (0x01UL << SCU_SFSP2_4_EPUN_Pos) /*!< SCU SFSP2_4: EPUN Mask */ -#define SCU_SFSP2_4_EHS_Pos 5 /*!< SCU SFSP2_4: EHS Position */ -#define SCU_SFSP2_4_EHS_Msk (0x01UL << SCU_SFSP2_4_EHS_Pos) /*!< SCU SFSP2_4: EHS Mask */ -#define SCU_SFSP2_4_EZI_Pos 6 /*!< SCU SFSP2_4: EZI Position */ -#define SCU_SFSP2_4_EZI_Msk (0x01UL << SCU_SFSP2_4_EZI_Pos) /*!< SCU SFSP2_4: EZI Mask */ -#define SCU_SFSP2_4_EHD_Pos 8 /*!< SCU SFSP2_4: EHD Position */ -#define SCU_SFSP2_4_EHD_Msk (0x03UL << SCU_SFSP2_4_EHD_Pos) /*!< SCU SFSP2_4: EHD Mask */ - -// --------------------------------------- SCU_SFSP2_5 ------------------------------------------ -#define SCU_SFSP2_5_MODE_Pos 0 /*!< SCU SFSP2_5: MODE Position */ -#define SCU_SFSP2_5_MODE_Msk (0x07UL << SCU_SFSP2_5_MODE_Pos) /*!< SCU SFSP2_5: MODE Mask */ -#define SCU_SFSP2_5_EPD_Pos 3 /*!< SCU SFSP2_5: EPD Position */ -#define SCU_SFSP2_5_EPD_Msk (0x01UL << SCU_SFSP2_5_EPD_Pos) /*!< SCU SFSP2_5: EPD Mask */ -#define SCU_SFSP2_5_EPUN_Pos 4 /*!< SCU SFSP2_5: EPUN Position */ -#define SCU_SFSP2_5_EPUN_Msk (0x01UL << SCU_SFSP2_5_EPUN_Pos) /*!< SCU SFSP2_5: EPUN Mask */ -#define SCU_SFSP2_5_EHS_Pos 5 /*!< SCU SFSP2_5: EHS Position */ -#define SCU_SFSP2_5_EHS_Msk (0x01UL << SCU_SFSP2_5_EHS_Pos) /*!< SCU SFSP2_5: EHS Mask */ -#define SCU_SFSP2_5_EZI_Pos 6 /*!< SCU SFSP2_5: EZI Position */ -#define SCU_SFSP2_5_EZI_Msk (0x01UL << SCU_SFSP2_5_EZI_Pos) /*!< SCU SFSP2_5: EZI Mask */ -#define SCU_SFSP2_5_EHD_Pos 8 /*!< SCU SFSP2_5: EHD Position */ -#define SCU_SFSP2_5_EHD_Msk (0x03UL << SCU_SFSP2_5_EHD_Pos) /*!< SCU SFSP2_5: EHD Mask */ - -// --------------------------------------- SCU_SFSP2_6 ------------------------------------------ -#define SCU_SFSP2_6_MODE_Pos 0 /*!< SCU SFSP2_6: MODE Position */ -#define SCU_SFSP2_6_MODE_Msk (0x07UL << SCU_SFSP2_6_MODE_Pos) /*!< SCU SFSP2_6: MODE Mask */ -#define SCU_SFSP2_6_EPD_Pos 3 /*!< SCU SFSP2_6: EPD Position */ -#define SCU_SFSP2_6_EPD_Msk (0x01UL << SCU_SFSP2_6_EPD_Pos) /*!< SCU SFSP2_6: EPD Mask */ -#define SCU_SFSP2_6_EPUN_Pos 4 /*!< SCU SFSP2_6: EPUN Position */ -#define SCU_SFSP2_6_EPUN_Msk (0x01UL << SCU_SFSP2_6_EPUN_Pos) /*!< SCU SFSP2_6: EPUN Mask */ -#define SCU_SFSP2_6_EHS_Pos 5 /*!< SCU SFSP2_6: EHS Position */ -#define SCU_SFSP2_6_EHS_Msk (0x01UL << SCU_SFSP2_6_EHS_Pos) /*!< SCU SFSP2_6: EHS Mask */ -#define SCU_SFSP2_6_EZI_Pos 6 /*!< SCU SFSP2_6: EZI Position */ -#define SCU_SFSP2_6_EZI_Msk (0x01UL << SCU_SFSP2_6_EZI_Pos) /*!< SCU SFSP2_6: EZI Mask */ -#define SCU_SFSP2_6_EHD_Pos 8 /*!< SCU SFSP2_6: EHD Position */ -#define SCU_SFSP2_6_EHD_Msk (0x03UL << SCU_SFSP2_6_EHD_Pos) /*!< SCU SFSP2_6: EHD Mask */ - -// --------------------------------------- SCU_SFSP2_7 ------------------------------------------ -#define SCU_SFSP2_7_MODE_Pos 0 /*!< SCU SFSP2_7: MODE Position */ -#define SCU_SFSP2_7_MODE_Msk (0x07UL << SCU_SFSP2_7_MODE_Pos) /*!< SCU SFSP2_7: MODE Mask */ -#define SCU_SFSP2_7_EPD_Pos 3 /*!< SCU SFSP2_7: EPD Position */ -#define SCU_SFSP2_7_EPD_Msk (0x01UL << SCU_SFSP2_7_EPD_Pos) /*!< SCU SFSP2_7: EPD Mask */ -#define SCU_SFSP2_7_EPUN_Pos 4 /*!< SCU SFSP2_7: EPUN Position */ -#define SCU_SFSP2_7_EPUN_Msk (0x01UL << SCU_SFSP2_7_EPUN_Pos) /*!< SCU SFSP2_7: EPUN Mask */ -#define SCU_SFSP2_7_EHS_Pos 5 /*!< SCU SFSP2_7: EHS Position */ -#define SCU_SFSP2_7_EHS_Msk (0x01UL << SCU_SFSP2_7_EHS_Pos) /*!< SCU SFSP2_7: EHS Mask */ -#define SCU_SFSP2_7_EZI_Pos 6 /*!< SCU SFSP2_7: EZI Position */ -#define SCU_SFSP2_7_EZI_Msk (0x01UL << SCU_SFSP2_7_EZI_Pos) /*!< SCU SFSP2_7: EZI Mask */ -#define SCU_SFSP2_7_EHD_Pos 8 /*!< SCU SFSP2_7: EHD Position */ -#define SCU_SFSP2_7_EHD_Msk (0x03UL << SCU_SFSP2_7_EHD_Pos) /*!< SCU SFSP2_7: EHD Mask */ - -// --------------------------------------- SCU_SFSP2_8 ------------------------------------------ -#define SCU_SFSP2_8_MODE_Pos 0 /*!< SCU SFSP2_8: MODE Position */ -#define SCU_SFSP2_8_MODE_Msk (0x07UL << SCU_SFSP2_8_MODE_Pos) /*!< SCU SFSP2_8: MODE Mask */ -#define SCU_SFSP2_8_EPD_Pos 3 /*!< SCU SFSP2_8: EPD Position */ -#define SCU_SFSP2_8_EPD_Msk (0x01UL << SCU_SFSP2_8_EPD_Pos) /*!< SCU SFSP2_8: EPD Mask */ -#define SCU_SFSP2_8_EPUN_Pos 4 /*!< SCU SFSP2_8: EPUN Position */ -#define SCU_SFSP2_8_EPUN_Msk (0x01UL << SCU_SFSP2_8_EPUN_Pos) /*!< SCU SFSP2_8: EPUN Mask */ -#define SCU_SFSP2_8_EHS_Pos 5 /*!< SCU SFSP2_8: EHS Position */ -#define SCU_SFSP2_8_EHS_Msk (0x01UL << SCU_SFSP2_8_EHS_Pos) /*!< SCU SFSP2_8: EHS Mask */ -#define SCU_SFSP2_8_EZI_Pos 6 /*!< SCU SFSP2_8: EZI Position */ -#define SCU_SFSP2_8_EZI_Msk (0x01UL << SCU_SFSP2_8_EZI_Pos) /*!< SCU SFSP2_8: EZI Mask */ -#define SCU_SFSP2_8_EHD_Pos 8 /*!< SCU SFSP2_8: EHD Position */ -#define SCU_SFSP2_8_EHD_Msk (0x03UL << SCU_SFSP2_8_EHD_Pos) /*!< SCU SFSP2_8: EHD Mask */ - -// --------------------------------------- SCU_SFSP2_9 ------------------------------------------ -#define SCU_SFSP2_9_MODE_Pos 0 /*!< SCU SFSP2_9: MODE Position */ -#define SCU_SFSP2_9_MODE_Msk (0x07UL << SCU_SFSP2_9_MODE_Pos) /*!< SCU SFSP2_9: MODE Mask */ -#define SCU_SFSP2_9_EPD_Pos 3 /*!< SCU SFSP2_9: EPD Position */ -#define SCU_SFSP2_9_EPD_Msk (0x01UL << SCU_SFSP2_9_EPD_Pos) /*!< SCU SFSP2_9: EPD Mask */ -#define SCU_SFSP2_9_EPUN_Pos 4 /*!< SCU SFSP2_9: EPUN Position */ -#define SCU_SFSP2_9_EPUN_Msk (0x01UL << SCU_SFSP2_9_EPUN_Pos) /*!< SCU SFSP2_9: EPUN Mask */ -#define SCU_SFSP2_9_EHS_Pos 5 /*!< SCU SFSP2_9: EHS Position */ -#define SCU_SFSP2_9_EHS_Msk (0x01UL << SCU_SFSP2_9_EHS_Pos) /*!< SCU SFSP2_9: EHS Mask */ -#define SCU_SFSP2_9_EZI_Pos 6 /*!< SCU SFSP2_9: EZI Position */ -#define SCU_SFSP2_9_EZI_Msk (0x01UL << SCU_SFSP2_9_EZI_Pos) /*!< SCU SFSP2_9: EZI Mask */ -#define SCU_SFSP2_9_EHD_Pos 8 /*!< SCU SFSP2_9: EHD Position */ -#define SCU_SFSP2_9_EHD_Msk (0x03UL << SCU_SFSP2_9_EHD_Pos) /*!< SCU SFSP2_9: EHD Mask */ - -// -------------------------------------- SCU_SFSP2_10 ------------------------------------------ -#define SCU_SFSP2_10_MODE_Pos 0 /*!< SCU SFSP2_10: MODE Position */ -#define SCU_SFSP2_10_MODE_Msk (0x07UL << SCU_SFSP2_10_MODE_Pos) /*!< SCU SFSP2_10: MODE Mask */ -#define SCU_SFSP2_10_EPD_Pos 3 /*!< SCU SFSP2_10: EPD Position */ -#define SCU_SFSP2_10_EPD_Msk (0x01UL << SCU_SFSP2_10_EPD_Pos) /*!< SCU SFSP2_10: EPD Mask */ -#define SCU_SFSP2_10_EPUN_Pos 4 /*!< SCU SFSP2_10: EPUN Position */ -#define SCU_SFSP2_10_EPUN_Msk (0x01UL << SCU_SFSP2_10_EPUN_Pos) /*!< SCU SFSP2_10: EPUN Mask */ -#define SCU_SFSP2_10_EHS_Pos 5 /*!< SCU SFSP2_10: EHS Position */ -#define SCU_SFSP2_10_EHS_Msk (0x01UL << SCU_SFSP2_10_EHS_Pos) /*!< SCU SFSP2_10: EHS Mask */ -#define SCU_SFSP2_10_EZI_Pos 6 /*!< SCU SFSP2_10: EZI Position */ -#define SCU_SFSP2_10_EZI_Msk (0x01UL << SCU_SFSP2_10_EZI_Pos) /*!< SCU SFSP2_10: EZI Mask */ -#define SCU_SFSP2_10_EHD_Pos 8 /*!< SCU SFSP2_10: EHD Position */ -#define SCU_SFSP2_10_EHD_Msk (0x03UL << SCU_SFSP2_10_EHD_Pos) /*!< SCU SFSP2_10: EHD Mask */ - -// -------------------------------------- SCU_SFSP2_11 ------------------------------------------ -#define SCU_SFSP2_11_MODE_Pos 0 /*!< SCU SFSP2_11: MODE Position */ -#define SCU_SFSP2_11_MODE_Msk (0x07UL << SCU_SFSP2_11_MODE_Pos) /*!< SCU SFSP2_11: MODE Mask */ -#define SCU_SFSP2_11_EPD_Pos 3 /*!< SCU SFSP2_11: EPD Position */ -#define SCU_SFSP2_11_EPD_Msk (0x01UL << SCU_SFSP2_11_EPD_Pos) /*!< SCU SFSP2_11: EPD Mask */ -#define SCU_SFSP2_11_EPUN_Pos 4 /*!< SCU SFSP2_11: EPUN Position */ -#define SCU_SFSP2_11_EPUN_Msk (0x01UL << SCU_SFSP2_11_EPUN_Pos) /*!< SCU SFSP2_11: EPUN Mask */ -#define SCU_SFSP2_11_EHS_Pos 5 /*!< SCU SFSP2_11: EHS Position */ -#define SCU_SFSP2_11_EHS_Msk (0x01UL << SCU_SFSP2_11_EHS_Pos) /*!< SCU SFSP2_11: EHS Mask */ -#define SCU_SFSP2_11_EZI_Pos 6 /*!< SCU SFSP2_11: EZI Position */ -#define SCU_SFSP2_11_EZI_Msk (0x01UL << SCU_SFSP2_11_EZI_Pos) /*!< SCU SFSP2_11: EZI Mask */ -#define SCU_SFSP2_11_EHD_Pos 8 /*!< SCU SFSP2_11: EHD Position */ -#define SCU_SFSP2_11_EHD_Msk (0x03UL << SCU_SFSP2_11_EHD_Pos) /*!< SCU SFSP2_11: EHD Mask */ - -// -------------------------------------- SCU_SFSP2_12 ------------------------------------------ -#define SCU_SFSP2_12_MODE_Pos 0 /*!< SCU SFSP2_12: MODE Position */ -#define SCU_SFSP2_12_MODE_Msk (0x07UL << SCU_SFSP2_12_MODE_Pos) /*!< SCU SFSP2_12: MODE Mask */ -#define SCU_SFSP2_12_EPD_Pos 3 /*!< SCU SFSP2_12: EPD Position */ -#define SCU_SFSP2_12_EPD_Msk (0x01UL << SCU_SFSP2_12_EPD_Pos) /*!< SCU SFSP2_12: EPD Mask */ -#define SCU_SFSP2_12_EPUN_Pos 4 /*!< SCU SFSP2_12: EPUN Position */ -#define SCU_SFSP2_12_EPUN_Msk (0x01UL << SCU_SFSP2_12_EPUN_Pos) /*!< SCU SFSP2_12: EPUN Mask */ -#define SCU_SFSP2_12_EHS_Pos 5 /*!< SCU SFSP2_12: EHS Position */ -#define SCU_SFSP2_12_EHS_Msk (0x01UL << SCU_SFSP2_12_EHS_Pos) /*!< SCU SFSP2_12: EHS Mask */ -#define SCU_SFSP2_12_EZI_Pos 6 /*!< SCU SFSP2_12: EZI Position */ -#define SCU_SFSP2_12_EZI_Msk (0x01UL << SCU_SFSP2_12_EZI_Pos) /*!< SCU SFSP2_12: EZI Mask */ -#define SCU_SFSP2_12_EHD_Pos 8 /*!< SCU SFSP2_12: EHD Position */ -#define SCU_SFSP2_12_EHD_Msk (0x03UL << SCU_SFSP2_12_EHD_Pos) /*!< SCU SFSP2_12: EHD Mask */ - -// -------------------------------------- SCU_SFSP2_13 ------------------------------------------ -#define SCU_SFSP2_13_MODE_Pos 0 /*!< SCU SFSP2_13: MODE Position */ -#define SCU_SFSP2_13_MODE_Msk (0x07UL << SCU_SFSP2_13_MODE_Pos) /*!< SCU SFSP2_13: MODE Mask */ -#define SCU_SFSP2_13_EPD_Pos 3 /*!< SCU SFSP2_13: EPD Position */ -#define SCU_SFSP2_13_EPD_Msk (0x01UL << SCU_SFSP2_13_EPD_Pos) /*!< SCU SFSP2_13: EPD Mask */ -#define SCU_SFSP2_13_EPUN_Pos 4 /*!< SCU SFSP2_13: EPUN Position */ -#define SCU_SFSP2_13_EPUN_Msk (0x01UL << SCU_SFSP2_13_EPUN_Pos) /*!< SCU SFSP2_13: EPUN Mask */ -#define SCU_SFSP2_13_EHS_Pos 5 /*!< SCU SFSP2_13: EHS Position */ -#define SCU_SFSP2_13_EHS_Msk (0x01UL << SCU_SFSP2_13_EHS_Pos) /*!< SCU SFSP2_13: EHS Mask */ -#define SCU_SFSP2_13_EZI_Pos 6 /*!< SCU SFSP2_13: EZI Position */ -#define SCU_SFSP2_13_EZI_Msk (0x01UL << SCU_SFSP2_13_EZI_Pos) /*!< SCU SFSP2_13: EZI Mask */ -#define SCU_SFSP2_13_EHD_Pos 8 /*!< SCU SFSP2_13: EHD Position */ -#define SCU_SFSP2_13_EHD_Msk (0x03UL << SCU_SFSP2_13_EHD_Pos) /*!< SCU SFSP2_13: EHD Mask */ - -// --------------------------------------- SCU_SFSP3_0 ------------------------------------------ -#define SCU_SFSP3_0_MODE_Pos 0 /*!< SCU SFSP3_0: MODE Position */ -#define SCU_SFSP3_0_MODE_Msk (0x07UL << SCU_SFSP3_0_MODE_Pos) /*!< SCU SFSP3_0: MODE Mask */ -#define SCU_SFSP3_0_EPD_Pos 3 /*!< SCU SFSP3_0: EPD Position */ -#define SCU_SFSP3_0_EPD_Msk (0x01UL << SCU_SFSP3_0_EPD_Pos) /*!< SCU SFSP3_0: EPD Mask */ -#define SCU_SFSP3_0_EPUN_Pos 4 /*!< SCU SFSP3_0: EPUN Position */ -#define SCU_SFSP3_0_EPUN_Msk (0x01UL << SCU_SFSP3_0_EPUN_Pos) /*!< SCU SFSP3_0: EPUN Mask */ -#define SCU_SFSP3_0_EHS_Pos 5 /*!< SCU SFSP3_0: EHS Position */ -#define SCU_SFSP3_0_EHS_Msk (0x01UL << SCU_SFSP3_0_EHS_Pos) /*!< SCU SFSP3_0: EHS Mask */ -#define SCU_SFSP3_0_EZI_Pos 6 /*!< SCU SFSP3_0: EZI Position */ -#define SCU_SFSP3_0_EZI_Msk (0x01UL << SCU_SFSP3_0_EZI_Pos) /*!< SCU SFSP3_0: EZI Mask */ -#define SCU_SFSP3_0_EHD_Pos 8 /*!< SCU SFSP3_0: EHD Position */ -#define SCU_SFSP3_0_EHD_Msk (0x03UL << SCU_SFSP3_0_EHD_Pos) /*!< SCU SFSP3_0: EHD Mask */ - -// --------------------------------------- SCU_SFSP3_1 ------------------------------------------ -#define SCU_SFSP3_1_MODE_Pos 0 /*!< SCU SFSP3_1: MODE Position */ -#define SCU_SFSP3_1_MODE_Msk (0x07UL << SCU_SFSP3_1_MODE_Pos) /*!< SCU SFSP3_1: MODE Mask */ -#define SCU_SFSP3_1_EPD_Pos 3 /*!< SCU SFSP3_1: EPD Position */ -#define SCU_SFSP3_1_EPD_Msk (0x01UL << SCU_SFSP3_1_EPD_Pos) /*!< SCU SFSP3_1: EPD Mask */ -#define SCU_SFSP3_1_EPUN_Pos 4 /*!< SCU SFSP3_1: EPUN Position */ -#define SCU_SFSP3_1_EPUN_Msk (0x01UL << SCU_SFSP3_1_EPUN_Pos) /*!< SCU SFSP3_1: EPUN Mask */ -#define SCU_SFSP3_1_EHS_Pos 5 /*!< SCU SFSP3_1: EHS Position */ -#define SCU_SFSP3_1_EHS_Msk (0x01UL << SCU_SFSP3_1_EHS_Pos) /*!< SCU SFSP3_1: EHS Mask */ -#define SCU_SFSP3_1_EZI_Pos 6 /*!< SCU SFSP3_1: EZI Position */ -#define SCU_SFSP3_1_EZI_Msk (0x01UL << SCU_SFSP3_1_EZI_Pos) /*!< SCU SFSP3_1: EZI Mask */ -#define SCU_SFSP3_1_EHD_Pos 8 /*!< SCU SFSP3_1: EHD Position */ -#define SCU_SFSP3_1_EHD_Msk (0x03UL << SCU_SFSP3_1_EHD_Pos) /*!< SCU SFSP3_1: EHD Mask */ - -// --------------------------------------- SCU_SFSP3_2 ------------------------------------------ -#define SCU_SFSP3_2_MODE_Pos 0 /*!< SCU SFSP3_2: MODE Position */ -#define SCU_SFSP3_2_MODE_Msk (0x07UL << SCU_SFSP3_2_MODE_Pos) /*!< SCU SFSP3_2: MODE Mask */ -#define SCU_SFSP3_2_EPD_Pos 3 /*!< SCU SFSP3_2: EPD Position */ -#define SCU_SFSP3_2_EPD_Msk (0x01UL << SCU_SFSP3_2_EPD_Pos) /*!< SCU SFSP3_2: EPD Mask */ -#define SCU_SFSP3_2_EPUN_Pos 4 /*!< SCU SFSP3_2: EPUN Position */ -#define SCU_SFSP3_2_EPUN_Msk (0x01UL << SCU_SFSP3_2_EPUN_Pos) /*!< SCU SFSP3_2: EPUN Mask */ -#define SCU_SFSP3_2_EHS_Pos 5 /*!< SCU SFSP3_2: EHS Position */ -#define SCU_SFSP3_2_EHS_Msk (0x01UL << SCU_SFSP3_2_EHS_Pos) /*!< SCU SFSP3_2: EHS Mask */ -#define SCU_SFSP3_2_EZI_Pos 6 /*!< SCU SFSP3_2: EZI Position */ -#define SCU_SFSP3_2_EZI_Msk (0x01UL << SCU_SFSP3_2_EZI_Pos) /*!< SCU SFSP3_2: EZI Mask */ -#define SCU_SFSP3_2_EHD_Pos 8 /*!< SCU SFSP3_2: EHD Position */ -#define SCU_SFSP3_2_EHD_Msk (0x03UL << SCU_SFSP3_2_EHD_Pos) /*!< SCU SFSP3_2: EHD Mask */ - -// --------------------------------------- SCU_SFSP3_3 ------------------------------------------ -#define SCU_SFSP3_3_MODE_Pos 0 /*!< SCU SFSP3_3: MODE Position */ -#define SCU_SFSP3_3_MODE_Msk (0x07UL << SCU_SFSP3_3_MODE_Pos) /*!< SCU SFSP3_3: MODE Mask */ -#define SCU_SFSP3_3_EPD_Pos 3 /*!< SCU SFSP3_3: EPD Position */ -#define SCU_SFSP3_3_EPD_Msk (0x01UL << SCU_SFSP3_3_EPD_Pos) /*!< SCU SFSP3_3: EPD Mask */ -#define SCU_SFSP3_3_EPUN_Pos 4 /*!< SCU SFSP3_3: EPUN Position */ -#define SCU_SFSP3_3_EPUN_Msk (0x01UL << SCU_SFSP3_3_EPUN_Pos) /*!< SCU SFSP3_3: EPUN Mask */ -#define SCU_SFSP3_3_EHS_Pos 5 /*!< SCU SFSP3_3: EHS Position */ -#define SCU_SFSP3_3_EHS_Msk (0x01UL << SCU_SFSP3_3_EHS_Pos) /*!< SCU SFSP3_3: EHS Mask */ -#define SCU_SFSP3_3_EZI_Pos 6 /*!< SCU SFSP3_3: EZI Position */ -#define SCU_SFSP3_3_EZI_Msk (0x01UL << SCU_SFSP3_3_EZI_Pos) /*!< SCU SFSP3_3: EZI Mask */ -#define SCU_SFSP3_3_EHD_Pos 8 /*!< SCU SFSP3_3: EHD Position */ -#define SCU_SFSP3_3_EHD_Msk (0x03UL << SCU_SFSP3_3_EHD_Pos) /*!< SCU SFSP3_3: EHD Mask */ - -// --------------------------------------- SCU_SFSP3_4 ------------------------------------------ -#define SCU_SFSP3_4_MODE_Pos 0 /*!< SCU SFSP3_4: MODE Position */ -#define SCU_SFSP3_4_MODE_Msk (0x07UL << SCU_SFSP3_4_MODE_Pos) /*!< SCU SFSP3_4: MODE Mask */ -#define SCU_SFSP3_4_EPD_Pos 3 /*!< SCU SFSP3_4: EPD Position */ -#define SCU_SFSP3_4_EPD_Msk (0x01UL << SCU_SFSP3_4_EPD_Pos) /*!< SCU SFSP3_4: EPD Mask */ -#define SCU_SFSP3_4_EPUN_Pos 4 /*!< SCU SFSP3_4: EPUN Position */ -#define SCU_SFSP3_4_EPUN_Msk (0x01UL << SCU_SFSP3_4_EPUN_Pos) /*!< SCU SFSP3_4: EPUN Mask */ -#define SCU_SFSP3_4_EHS_Pos 5 /*!< SCU SFSP3_4: EHS Position */ -#define SCU_SFSP3_4_EHS_Msk (0x01UL << SCU_SFSP3_4_EHS_Pos) /*!< SCU SFSP3_4: EHS Mask */ -#define SCU_SFSP3_4_EZI_Pos 6 /*!< SCU SFSP3_4: EZI Position */ -#define SCU_SFSP3_4_EZI_Msk (0x01UL << SCU_SFSP3_4_EZI_Pos) /*!< SCU SFSP3_4: EZI Mask */ -#define SCU_SFSP3_4_EHD_Pos 8 /*!< SCU SFSP3_4: EHD Position */ -#define SCU_SFSP3_4_EHD_Msk (0x03UL << SCU_SFSP3_4_EHD_Pos) /*!< SCU SFSP3_4: EHD Mask */ - -// --------------------------------------- SCU_SFSP3_5 ------------------------------------------ -#define SCU_SFSP3_5_MODE_Pos 0 /*!< SCU SFSP3_5: MODE Position */ -#define SCU_SFSP3_5_MODE_Msk (0x07UL << SCU_SFSP3_5_MODE_Pos) /*!< SCU SFSP3_5: MODE Mask */ -#define SCU_SFSP3_5_EPD_Pos 3 /*!< SCU SFSP3_5: EPD Position */ -#define SCU_SFSP3_5_EPD_Msk (0x01UL << SCU_SFSP3_5_EPD_Pos) /*!< SCU SFSP3_5: EPD Mask */ -#define SCU_SFSP3_5_EPUN_Pos 4 /*!< SCU SFSP3_5: EPUN Position */ -#define SCU_SFSP3_5_EPUN_Msk (0x01UL << SCU_SFSP3_5_EPUN_Pos) /*!< SCU SFSP3_5: EPUN Mask */ -#define SCU_SFSP3_5_EHS_Pos 5 /*!< SCU SFSP3_5: EHS Position */ -#define SCU_SFSP3_5_EHS_Msk (0x01UL << SCU_SFSP3_5_EHS_Pos) /*!< SCU SFSP3_5: EHS Mask */ -#define SCU_SFSP3_5_EZI_Pos 6 /*!< SCU SFSP3_5: EZI Position */ -#define SCU_SFSP3_5_EZI_Msk (0x01UL << SCU_SFSP3_5_EZI_Pos) /*!< SCU SFSP3_5: EZI Mask */ -#define SCU_SFSP3_5_EHD_Pos 8 /*!< SCU SFSP3_5: EHD Position */ -#define SCU_SFSP3_5_EHD_Msk (0x03UL << SCU_SFSP3_5_EHD_Pos) /*!< SCU SFSP3_5: EHD Mask */ - -// --------------------------------------- SCU_SFSP3_6 ------------------------------------------ -#define SCU_SFSP3_6_MODE_Pos 0 /*!< SCU SFSP3_6: MODE Position */ -#define SCU_SFSP3_6_MODE_Msk (0x07UL << SCU_SFSP3_6_MODE_Pos) /*!< SCU SFSP3_6: MODE Mask */ -#define SCU_SFSP3_6_EPD_Pos 3 /*!< SCU SFSP3_6: EPD Position */ -#define SCU_SFSP3_6_EPD_Msk (0x01UL << SCU_SFSP3_6_EPD_Pos) /*!< SCU SFSP3_6: EPD Mask */ -#define SCU_SFSP3_6_EPUN_Pos 4 /*!< SCU SFSP3_6: EPUN Position */ -#define SCU_SFSP3_6_EPUN_Msk (0x01UL << SCU_SFSP3_6_EPUN_Pos) /*!< SCU SFSP3_6: EPUN Mask */ -#define SCU_SFSP3_6_EHS_Pos 5 /*!< SCU SFSP3_6: EHS Position */ -#define SCU_SFSP3_6_EHS_Msk (0x01UL << SCU_SFSP3_6_EHS_Pos) /*!< SCU SFSP3_6: EHS Mask */ -#define SCU_SFSP3_6_EZI_Pos 6 /*!< SCU SFSP3_6: EZI Position */ -#define SCU_SFSP3_6_EZI_Msk (0x01UL << SCU_SFSP3_6_EZI_Pos) /*!< SCU SFSP3_6: EZI Mask */ -#define SCU_SFSP3_6_EHD_Pos 8 /*!< SCU SFSP3_6: EHD Position */ -#define SCU_SFSP3_6_EHD_Msk (0x03UL << SCU_SFSP3_6_EHD_Pos) /*!< SCU SFSP3_6: EHD Mask */ - -// --------------------------------------- SCU_SFSP3_7 ------------------------------------------ -#define SCU_SFSP3_7_MODE_Pos 0 /*!< SCU SFSP3_7: MODE Position */ -#define SCU_SFSP3_7_MODE_Msk (0x07UL << SCU_SFSP3_7_MODE_Pos) /*!< SCU SFSP3_7: MODE Mask */ -#define SCU_SFSP3_7_EPD_Pos 3 /*!< SCU SFSP3_7: EPD Position */ -#define SCU_SFSP3_7_EPD_Msk (0x01UL << SCU_SFSP3_7_EPD_Pos) /*!< SCU SFSP3_7: EPD Mask */ -#define SCU_SFSP3_7_EPUN_Pos 4 /*!< SCU SFSP3_7: EPUN Position */ -#define SCU_SFSP3_7_EPUN_Msk (0x01UL << SCU_SFSP3_7_EPUN_Pos) /*!< SCU SFSP3_7: EPUN Mask */ -#define SCU_SFSP3_7_EHS_Pos 5 /*!< SCU SFSP3_7: EHS Position */ -#define SCU_SFSP3_7_EHS_Msk (0x01UL << SCU_SFSP3_7_EHS_Pos) /*!< SCU SFSP3_7: EHS Mask */ -#define SCU_SFSP3_7_EZI_Pos 6 /*!< SCU SFSP3_7: EZI Position */ -#define SCU_SFSP3_7_EZI_Msk (0x01UL << SCU_SFSP3_7_EZI_Pos) /*!< SCU SFSP3_7: EZI Mask */ -#define SCU_SFSP3_7_EHD_Pos 8 /*!< SCU SFSP3_7: EHD Position */ -#define SCU_SFSP3_7_EHD_Msk (0x03UL << SCU_SFSP3_7_EHD_Pos) /*!< SCU SFSP3_7: EHD Mask */ - -// --------------------------------------- SCU_SFSP3_8 ------------------------------------------ -#define SCU_SFSP3_8_MODE_Pos 0 /*!< SCU SFSP3_8: MODE Position */ -#define SCU_SFSP3_8_MODE_Msk (0x07UL << SCU_SFSP3_8_MODE_Pos) /*!< SCU SFSP3_8: MODE Mask */ -#define SCU_SFSP3_8_EPD_Pos 3 /*!< SCU SFSP3_8: EPD Position */ -#define SCU_SFSP3_8_EPD_Msk (0x01UL << SCU_SFSP3_8_EPD_Pos) /*!< SCU SFSP3_8: EPD Mask */ -#define SCU_SFSP3_8_EPUN_Pos 4 /*!< SCU SFSP3_8: EPUN Position */ -#define SCU_SFSP3_8_EPUN_Msk (0x01UL << SCU_SFSP3_8_EPUN_Pos) /*!< SCU SFSP3_8: EPUN Mask */ -#define SCU_SFSP3_8_EHS_Pos 5 /*!< SCU SFSP3_8: EHS Position */ -#define SCU_SFSP3_8_EHS_Msk (0x01UL << SCU_SFSP3_8_EHS_Pos) /*!< SCU SFSP3_8: EHS Mask */ -#define SCU_SFSP3_8_EZI_Pos 6 /*!< SCU SFSP3_8: EZI Position */ -#define SCU_SFSP3_8_EZI_Msk (0x01UL << SCU_SFSP3_8_EZI_Pos) /*!< SCU SFSP3_8: EZI Mask */ -#define SCU_SFSP3_8_EHD_Pos 8 /*!< SCU SFSP3_8: EHD Position */ -#define SCU_SFSP3_8_EHD_Msk (0x03UL << SCU_SFSP3_8_EHD_Pos) /*!< SCU SFSP3_8: EHD Mask */ - -// --------------------------------------- SCU_SFSP4_0 ------------------------------------------ -#define SCU_SFSP4_0_MODE_Pos 0 /*!< SCU SFSP4_0: MODE Position */ -#define SCU_SFSP4_0_MODE_Msk (0x07UL << SCU_SFSP4_0_MODE_Pos) /*!< SCU SFSP4_0: MODE Mask */ -#define SCU_SFSP4_0_EPD_Pos 3 /*!< SCU SFSP4_0: EPD Position */ -#define SCU_SFSP4_0_EPD_Msk (0x01UL << SCU_SFSP4_0_EPD_Pos) /*!< SCU SFSP4_0: EPD Mask */ -#define SCU_SFSP4_0_EPUN_Pos 4 /*!< SCU SFSP4_0: EPUN Position */ -#define SCU_SFSP4_0_EPUN_Msk (0x01UL << SCU_SFSP4_0_EPUN_Pos) /*!< SCU SFSP4_0: EPUN Mask */ -#define SCU_SFSP4_0_EHS_Pos 5 /*!< SCU SFSP4_0: EHS Position */ -#define SCU_SFSP4_0_EHS_Msk (0x01UL << SCU_SFSP4_0_EHS_Pos) /*!< SCU SFSP4_0: EHS Mask */ -#define SCU_SFSP4_0_EZI_Pos 6 /*!< SCU SFSP4_0: EZI Position */ -#define SCU_SFSP4_0_EZI_Msk (0x01UL << SCU_SFSP4_0_EZI_Pos) /*!< SCU SFSP4_0: EZI Mask */ -#define SCU_SFSP4_0_EHD_Pos 8 /*!< SCU SFSP4_0: EHD Position */ -#define SCU_SFSP4_0_EHD_Msk (0x03UL << SCU_SFSP4_0_EHD_Pos) /*!< SCU SFSP4_0: EHD Mask */ - -// --------------------------------------- SCU_SFSP4_1 ------------------------------------------ -#define SCU_SFSP4_1_MODE_Pos 0 /*!< SCU SFSP4_1: MODE Position */ -#define SCU_SFSP4_1_MODE_Msk (0x07UL << SCU_SFSP4_1_MODE_Pos) /*!< SCU SFSP4_1: MODE Mask */ -#define SCU_SFSP4_1_EPD_Pos 3 /*!< SCU SFSP4_1: EPD Position */ -#define SCU_SFSP4_1_EPD_Msk (0x01UL << SCU_SFSP4_1_EPD_Pos) /*!< SCU SFSP4_1: EPD Mask */ -#define SCU_SFSP4_1_EPUN_Pos 4 /*!< SCU SFSP4_1: EPUN Position */ -#define SCU_SFSP4_1_EPUN_Msk (0x01UL << SCU_SFSP4_1_EPUN_Pos) /*!< SCU SFSP4_1: EPUN Mask */ -#define SCU_SFSP4_1_EHS_Pos 5 /*!< SCU SFSP4_1: EHS Position */ -#define SCU_SFSP4_1_EHS_Msk (0x01UL << SCU_SFSP4_1_EHS_Pos) /*!< SCU SFSP4_1: EHS Mask */ -#define SCU_SFSP4_1_EZI_Pos 6 /*!< SCU SFSP4_1: EZI Position */ -#define SCU_SFSP4_1_EZI_Msk (0x01UL << SCU_SFSP4_1_EZI_Pos) /*!< SCU SFSP4_1: EZI Mask */ -#define SCU_SFSP4_1_EHD_Pos 8 /*!< SCU SFSP4_1: EHD Position */ -#define SCU_SFSP4_1_EHD_Msk (0x03UL << SCU_SFSP4_1_EHD_Pos) /*!< SCU SFSP4_1: EHD Mask */ - -// --------------------------------------- SCU_SFSP4_2 ------------------------------------------ -#define SCU_SFSP4_2_MODE_Pos 0 /*!< SCU SFSP4_2: MODE Position */ -#define SCU_SFSP4_2_MODE_Msk (0x07UL << SCU_SFSP4_2_MODE_Pos) /*!< SCU SFSP4_2: MODE Mask */ -#define SCU_SFSP4_2_EPD_Pos 3 /*!< SCU SFSP4_2: EPD Position */ -#define SCU_SFSP4_2_EPD_Msk (0x01UL << SCU_SFSP4_2_EPD_Pos) /*!< SCU SFSP4_2: EPD Mask */ -#define SCU_SFSP4_2_EPUN_Pos 4 /*!< SCU SFSP4_2: EPUN Position */ -#define SCU_SFSP4_2_EPUN_Msk (0x01UL << SCU_SFSP4_2_EPUN_Pos) /*!< SCU SFSP4_2: EPUN Mask */ -#define SCU_SFSP4_2_EHS_Pos 5 /*!< SCU SFSP4_2: EHS Position */ -#define SCU_SFSP4_2_EHS_Msk (0x01UL << SCU_SFSP4_2_EHS_Pos) /*!< SCU SFSP4_2: EHS Mask */ -#define SCU_SFSP4_2_EZI_Pos 6 /*!< SCU SFSP4_2: EZI Position */ -#define SCU_SFSP4_2_EZI_Msk (0x01UL << SCU_SFSP4_2_EZI_Pos) /*!< SCU SFSP4_2: EZI Mask */ -#define SCU_SFSP4_2_EHD_Pos 8 /*!< SCU SFSP4_2: EHD Position */ -#define SCU_SFSP4_2_EHD_Msk (0x03UL << SCU_SFSP4_2_EHD_Pos) /*!< SCU SFSP4_2: EHD Mask */ - -// --------------------------------------- SCU_SFSP4_3 ------------------------------------------ -#define SCU_SFSP4_3_MODE_Pos 0 /*!< SCU SFSP4_3: MODE Position */ -#define SCU_SFSP4_3_MODE_Msk (0x07UL << SCU_SFSP4_3_MODE_Pos) /*!< SCU SFSP4_3: MODE Mask */ -#define SCU_SFSP4_3_EPD_Pos 3 /*!< SCU SFSP4_3: EPD Position */ -#define SCU_SFSP4_3_EPD_Msk (0x01UL << SCU_SFSP4_3_EPD_Pos) /*!< SCU SFSP4_3: EPD Mask */ -#define SCU_SFSP4_3_EPUN_Pos 4 /*!< SCU SFSP4_3: EPUN Position */ -#define SCU_SFSP4_3_EPUN_Msk (0x01UL << SCU_SFSP4_3_EPUN_Pos) /*!< SCU SFSP4_3: EPUN Mask */ -#define SCU_SFSP4_3_EHS_Pos 5 /*!< SCU SFSP4_3: EHS Position */ -#define SCU_SFSP4_3_EHS_Msk (0x01UL << SCU_SFSP4_3_EHS_Pos) /*!< SCU SFSP4_3: EHS Mask */ -#define SCU_SFSP4_3_EZI_Pos 6 /*!< SCU SFSP4_3: EZI Position */ -#define SCU_SFSP4_3_EZI_Msk (0x01UL << SCU_SFSP4_3_EZI_Pos) /*!< SCU SFSP4_3: EZI Mask */ -#define SCU_SFSP4_3_EHD_Pos 8 /*!< SCU SFSP4_3: EHD Position */ -#define SCU_SFSP4_3_EHD_Msk (0x03UL << SCU_SFSP4_3_EHD_Pos) /*!< SCU SFSP4_3: EHD Mask */ - -// --------------------------------------- SCU_SFSP4_4 ------------------------------------------ -#define SCU_SFSP4_4_MODE_Pos 0 /*!< SCU SFSP4_4: MODE Position */ -#define SCU_SFSP4_4_MODE_Msk (0x07UL << SCU_SFSP4_4_MODE_Pos) /*!< SCU SFSP4_4: MODE Mask */ -#define SCU_SFSP4_4_EPD_Pos 3 /*!< SCU SFSP4_4: EPD Position */ -#define SCU_SFSP4_4_EPD_Msk (0x01UL << SCU_SFSP4_4_EPD_Pos) /*!< SCU SFSP4_4: EPD Mask */ -#define SCU_SFSP4_4_EPUN_Pos 4 /*!< SCU SFSP4_4: EPUN Position */ -#define SCU_SFSP4_4_EPUN_Msk (0x01UL << SCU_SFSP4_4_EPUN_Pos) /*!< SCU SFSP4_4: EPUN Mask */ -#define SCU_SFSP4_4_EHS_Pos 5 /*!< SCU SFSP4_4: EHS Position */ -#define SCU_SFSP4_4_EHS_Msk (0x01UL << SCU_SFSP4_4_EHS_Pos) /*!< SCU SFSP4_4: EHS Mask */ -#define SCU_SFSP4_4_EZI_Pos 6 /*!< SCU SFSP4_4: EZI Position */ -#define SCU_SFSP4_4_EZI_Msk (0x01UL << SCU_SFSP4_4_EZI_Pos) /*!< SCU SFSP4_4: EZI Mask */ -#define SCU_SFSP4_4_EHD_Pos 8 /*!< SCU SFSP4_4: EHD Position */ -#define SCU_SFSP4_4_EHD_Msk (0x03UL << SCU_SFSP4_4_EHD_Pos) /*!< SCU SFSP4_4: EHD Mask */ - -// --------------------------------------- SCU_SFSP4_5 ------------------------------------------ -#define SCU_SFSP4_5_MODE_Pos 0 /*!< SCU SFSP4_5: MODE Position */ -#define SCU_SFSP4_5_MODE_Msk (0x07UL << SCU_SFSP4_5_MODE_Pos) /*!< SCU SFSP4_5: MODE Mask */ -#define SCU_SFSP4_5_EPD_Pos 3 /*!< SCU SFSP4_5: EPD Position */ -#define SCU_SFSP4_5_EPD_Msk (0x01UL << SCU_SFSP4_5_EPD_Pos) /*!< SCU SFSP4_5: EPD Mask */ -#define SCU_SFSP4_5_EPUN_Pos 4 /*!< SCU SFSP4_5: EPUN Position */ -#define SCU_SFSP4_5_EPUN_Msk (0x01UL << SCU_SFSP4_5_EPUN_Pos) /*!< SCU SFSP4_5: EPUN Mask */ -#define SCU_SFSP4_5_EHS_Pos 5 /*!< SCU SFSP4_5: EHS Position */ -#define SCU_SFSP4_5_EHS_Msk (0x01UL << SCU_SFSP4_5_EHS_Pos) /*!< SCU SFSP4_5: EHS Mask */ -#define SCU_SFSP4_5_EZI_Pos 6 /*!< SCU SFSP4_5: EZI Position */ -#define SCU_SFSP4_5_EZI_Msk (0x01UL << SCU_SFSP4_5_EZI_Pos) /*!< SCU SFSP4_5: EZI Mask */ -#define SCU_SFSP4_5_EHD_Pos 8 /*!< SCU SFSP4_5: EHD Position */ -#define SCU_SFSP4_5_EHD_Msk (0x03UL << SCU_SFSP4_5_EHD_Pos) /*!< SCU SFSP4_5: EHD Mask */ - -// --------------------------------------- SCU_SFSP4_6 ------------------------------------------ -#define SCU_SFSP4_6_MODE_Pos 0 /*!< SCU SFSP4_6: MODE Position */ -#define SCU_SFSP4_6_MODE_Msk (0x07UL << SCU_SFSP4_6_MODE_Pos) /*!< SCU SFSP4_6: MODE Mask */ -#define SCU_SFSP4_6_EPD_Pos 3 /*!< SCU SFSP4_6: EPD Position */ -#define SCU_SFSP4_6_EPD_Msk (0x01UL << SCU_SFSP4_6_EPD_Pos) /*!< SCU SFSP4_6: EPD Mask */ -#define SCU_SFSP4_6_EPUN_Pos 4 /*!< SCU SFSP4_6: EPUN Position */ -#define SCU_SFSP4_6_EPUN_Msk (0x01UL << SCU_SFSP4_6_EPUN_Pos) /*!< SCU SFSP4_6: EPUN Mask */ -#define SCU_SFSP4_6_EHS_Pos 5 /*!< SCU SFSP4_6: EHS Position */ -#define SCU_SFSP4_6_EHS_Msk (0x01UL << SCU_SFSP4_6_EHS_Pos) /*!< SCU SFSP4_6: EHS Mask */ -#define SCU_SFSP4_6_EZI_Pos 6 /*!< SCU SFSP4_6: EZI Position */ -#define SCU_SFSP4_6_EZI_Msk (0x01UL << SCU_SFSP4_6_EZI_Pos) /*!< SCU SFSP4_6: EZI Mask */ -#define SCU_SFSP4_6_EHD_Pos 8 /*!< SCU SFSP4_6: EHD Position */ -#define SCU_SFSP4_6_EHD_Msk (0x03UL << SCU_SFSP4_6_EHD_Pos) /*!< SCU SFSP4_6: EHD Mask */ - -// --------------------------------------- SCU_SFSP4_7 ------------------------------------------ -#define SCU_SFSP4_7_MODE_Pos 0 /*!< SCU SFSP4_7: MODE Position */ -#define SCU_SFSP4_7_MODE_Msk (0x07UL << SCU_SFSP4_7_MODE_Pos) /*!< SCU SFSP4_7: MODE Mask */ -#define SCU_SFSP4_7_EPD_Pos 3 /*!< SCU SFSP4_7: EPD Position */ -#define SCU_SFSP4_7_EPD_Msk (0x01UL << SCU_SFSP4_7_EPD_Pos) /*!< SCU SFSP4_7: EPD Mask */ -#define SCU_SFSP4_7_EPUN_Pos 4 /*!< SCU SFSP4_7: EPUN Position */ -#define SCU_SFSP4_7_EPUN_Msk (0x01UL << SCU_SFSP4_7_EPUN_Pos) /*!< SCU SFSP4_7: EPUN Mask */ -#define SCU_SFSP4_7_EHS_Pos 5 /*!< SCU SFSP4_7: EHS Position */ -#define SCU_SFSP4_7_EHS_Msk (0x01UL << SCU_SFSP4_7_EHS_Pos) /*!< SCU SFSP4_7: EHS Mask */ -#define SCU_SFSP4_7_EZI_Pos 6 /*!< SCU SFSP4_7: EZI Position */ -#define SCU_SFSP4_7_EZI_Msk (0x01UL << SCU_SFSP4_7_EZI_Pos) /*!< SCU SFSP4_7: EZI Mask */ -#define SCU_SFSP4_7_EHD_Pos 8 /*!< SCU SFSP4_7: EHD Position */ -#define SCU_SFSP4_7_EHD_Msk (0x03UL << SCU_SFSP4_7_EHD_Pos) /*!< SCU SFSP4_7: EHD Mask */ - -// --------------------------------------- SCU_SFSP4_8 ------------------------------------------ -#define SCU_SFSP4_8_MODE_Pos 0 /*!< SCU SFSP4_8: MODE Position */ -#define SCU_SFSP4_8_MODE_Msk (0x07UL << SCU_SFSP4_8_MODE_Pos) /*!< SCU SFSP4_8: MODE Mask */ -#define SCU_SFSP4_8_EPD_Pos 3 /*!< SCU SFSP4_8: EPD Position */ -#define SCU_SFSP4_8_EPD_Msk (0x01UL << SCU_SFSP4_8_EPD_Pos) /*!< SCU SFSP4_8: EPD Mask */ -#define SCU_SFSP4_8_EPUN_Pos 4 /*!< SCU SFSP4_8: EPUN Position */ -#define SCU_SFSP4_8_EPUN_Msk (0x01UL << SCU_SFSP4_8_EPUN_Pos) /*!< SCU SFSP4_8: EPUN Mask */ -#define SCU_SFSP4_8_EHS_Pos 5 /*!< SCU SFSP4_8: EHS Position */ -#define SCU_SFSP4_8_EHS_Msk (0x01UL << SCU_SFSP4_8_EHS_Pos) /*!< SCU SFSP4_8: EHS Mask */ -#define SCU_SFSP4_8_EZI_Pos 6 /*!< SCU SFSP4_8: EZI Position */ -#define SCU_SFSP4_8_EZI_Msk (0x01UL << SCU_SFSP4_8_EZI_Pos) /*!< SCU SFSP4_8: EZI Mask */ -#define SCU_SFSP4_8_EHD_Pos 8 /*!< SCU SFSP4_8: EHD Position */ -#define SCU_SFSP4_8_EHD_Msk (0x03UL << SCU_SFSP4_8_EHD_Pos) /*!< SCU SFSP4_8: EHD Mask */ - -// --------------------------------------- SCU_SFSP4_9 ------------------------------------------ -#define SCU_SFSP4_9_MODE_Pos 0 /*!< SCU SFSP4_9: MODE Position */ -#define SCU_SFSP4_9_MODE_Msk (0x07UL << SCU_SFSP4_9_MODE_Pos) /*!< SCU SFSP4_9: MODE Mask */ -#define SCU_SFSP4_9_EPD_Pos 3 /*!< SCU SFSP4_9: EPD Position */ -#define SCU_SFSP4_9_EPD_Msk (0x01UL << SCU_SFSP4_9_EPD_Pos) /*!< SCU SFSP4_9: EPD Mask */ -#define SCU_SFSP4_9_EPUN_Pos 4 /*!< SCU SFSP4_9: EPUN Position */ -#define SCU_SFSP4_9_EPUN_Msk (0x01UL << SCU_SFSP4_9_EPUN_Pos) /*!< SCU SFSP4_9: EPUN Mask */ -#define SCU_SFSP4_9_EHS_Pos 5 /*!< SCU SFSP4_9: EHS Position */ -#define SCU_SFSP4_9_EHS_Msk (0x01UL << SCU_SFSP4_9_EHS_Pos) /*!< SCU SFSP4_9: EHS Mask */ -#define SCU_SFSP4_9_EZI_Pos 6 /*!< SCU SFSP4_9: EZI Position */ -#define SCU_SFSP4_9_EZI_Msk (0x01UL << SCU_SFSP4_9_EZI_Pos) /*!< SCU SFSP4_9: EZI Mask */ -#define SCU_SFSP4_9_EHD_Pos 8 /*!< SCU SFSP4_9: EHD Position */ -#define SCU_SFSP4_9_EHD_Msk (0x03UL << SCU_SFSP4_9_EHD_Pos) /*!< SCU SFSP4_9: EHD Mask */ - -// -------------------------------------- SCU_SFSP4_10 ------------------------------------------ -#define SCU_SFSP4_10_MODE_Pos 0 /*!< SCU SFSP4_10: MODE Position */ -#define SCU_SFSP4_10_MODE_Msk (0x07UL << SCU_SFSP4_10_MODE_Pos) /*!< SCU SFSP4_10: MODE Mask */ -#define SCU_SFSP4_10_EPD_Pos 3 /*!< SCU SFSP4_10: EPD Position */ -#define SCU_SFSP4_10_EPD_Msk (0x01UL << SCU_SFSP4_10_EPD_Pos) /*!< SCU SFSP4_10: EPD Mask */ -#define SCU_SFSP4_10_EPUN_Pos 4 /*!< SCU SFSP4_10: EPUN Position */ -#define SCU_SFSP4_10_EPUN_Msk (0x01UL << SCU_SFSP4_10_EPUN_Pos) /*!< SCU SFSP4_10: EPUN Mask */ -#define SCU_SFSP4_10_EHS_Pos 5 /*!< SCU SFSP4_10: EHS Position */ -#define SCU_SFSP4_10_EHS_Msk (0x01UL << SCU_SFSP4_10_EHS_Pos) /*!< SCU SFSP4_10: EHS Mask */ -#define SCU_SFSP4_10_EZI_Pos 6 /*!< SCU SFSP4_10: EZI Position */ -#define SCU_SFSP4_10_EZI_Msk (0x01UL << SCU_SFSP4_10_EZI_Pos) /*!< SCU SFSP4_10: EZI Mask */ -#define SCU_SFSP4_10_EHD_Pos 8 /*!< SCU SFSP4_10: EHD Position */ -#define SCU_SFSP4_10_EHD_Msk (0x03UL << SCU_SFSP4_10_EHD_Pos) /*!< SCU SFSP4_10: EHD Mask */ - -// --------------------------------------- SCU_SFSP5_0 ------------------------------------------ -#define SCU_SFSP5_0_MODE_Pos 0 /*!< SCU SFSP5_0: MODE Position */ -#define SCU_SFSP5_0_MODE_Msk (0x07UL << SCU_SFSP5_0_MODE_Pos) /*!< SCU SFSP5_0: MODE Mask */ -#define SCU_SFSP5_0_EPD_Pos 3 /*!< SCU SFSP5_0: EPD Position */ -#define SCU_SFSP5_0_EPD_Msk (0x01UL << SCU_SFSP5_0_EPD_Pos) /*!< SCU SFSP5_0: EPD Mask */ -#define SCU_SFSP5_0_EPUN_Pos 4 /*!< SCU SFSP5_0: EPUN Position */ -#define SCU_SFSP5_0_EPUN_Msk (0x01UL << SCU_SFSP5_0_EPUN_Pos) /*!< SCU SFSP5_0: EPUN Mask */ -#define SCU_SFSP5_0_EHS_Pos 5 /*!< SCU SFSP5_0: EHS Position */ -#define SCU_SFSP5_0_EHS_Msk (0x01UL << SCU_SFSP5_0_EHS_Pos) /*!< SCU SFSP5_0: EHS Mask */ -#define SCU_SFSP5_0_EZI_Pos 6 /*!< SCU SFSP5_0: EZI Position */ -#define SCU_SFSP5_0_EZI_Msk (0x01UL << SCU_SFSP5_0_EZI_Pos) /*!< SCU SFSP5_0: EZI Mask */ -#define SCU_SFSP5_0_EHD_Pos 8 /*!< SCU SFSP5_0: EHD Position */ -#define SCU_SFSP5_0_EHD_Msk (0x03UL << SCU_SFSP5_0_EHD_Pos) /*!< SCU SFSP5_0: EHD Mask */ - -// --------------------------------------- SCU_SFSP5_1 ------------------------------------------ -#define SCU_SFSP5_1_MODE_Pos 0 /*!< SCU SFSP5_1: MODE Position */ -#define SCU_SFSP5_1_MODE_Msk (0x07UL << SCU_SFSP5_1_MODE_Pos) /*!< SCU SFSP5_1: MODE Mask */ -#define SCU_SFSP5_1_EPD_Pos 3 /*!< SCU SFSP5_1: EPD Position */ -#define SCU_SFSP5_1_EPD_Msk (0x01UL << SCU_SFSP5_1_EPD_Pos) /*!< SCU SFSP5_1: EPD Mask */ -#define SCU_SFSP5_1_EPUN_Pos 4 /*!< SCU SFSP5_1: EPUN Position */ -#define SCU_SFSP5_1_EPUN_Msk (0x01UL << SCU_SFSP5_1_EPUN_Pos) /*!< SCU SFSP5_1: EPUN Mask */ -#define SCU_SFSP5_1_EHS_Pos 5 /*!< SCU SFSP5_1: EHS Position */ -#define SCU_SFSP5_1_EHS_Msk (0x01UL << SCU_SFSP5_1_EHS_Pos) /*!< SCU SFSP5_1: EHS Mask */ -#define SCU_SFSP5_1_EZI_Pos 6 /*!< SCU SFSP5_1: EZI Position */ -#define SCU_SFSP5_1_EZI_Msk (0x01UL << SCU_SFSP5_1_EZI_Pos) /*!< SCU SFSP5_1: EZI Mask */ -#define SCU_SFSP5_1_EHD_Pos 8 /*!< SCU SFSP5_1: EHD Position */ -#define SCU_SFSP5_1_EHD_Msk (0x03UL << SCU_SFSP5_1_EHD_Pos) /*!< SCU SFSP5_1: EHD Mask */ - -// --------------------------------------- SCU_SFSP5_2 ------------------------------------------ -#define SCU_SFSP5_2_MODE_Pos 0 /*!< SCU SFSP5_2: MODE Position */ -#define SCU_SFSP5_2_MODE_Msk (0x07UL << SCU_SFSP5_2_MODE_Pos) /*!< SCU SFSP5_2: MODE Mask */ -#define SCU_SFSP5_2_EPD_Pos 3 /*!< SCU SFSP5_2: EPD Position */ -#define SCU_SFSP5_2_EPD_Msk (0x01UL << SCU_SFSP5_2_EPD_Pos) /*!< SCU SFSP5_2: EPD Mask */ -#define SCU_SFSP5_2_EPUN_Pos 4 /*!< SCU SFSP5_2: EPUN Position */ -#define SCU_SFSP5_2_EPUN_Msk (0x01UL << SCU_SFSP5_2_EPUN_Pos) /*!< SCU SFSP5_2: EPUN Mask */ -#define SCU_SFSP5_2_EHS_Pos 5 /*!< SCU SFSP5_2: EHS Position */ -#define SCU_SFSP5_2_EHS_Msk (0x01UL << SCU_SFSP5_2_EHS_Pos) /*!< SCU SFSP5_2: EHS Mask */ -#define SCU_SFSP5_2_EZI_Pos 6 /*!< SCU SFSP5_2: EZI Position */ -#define SCU_SFSP5_2_EZI_Msk (0x01UL << SCU_SFSP5_2_EZI_Pos) /*!< SCU SFSP5_2: EZI Mask */ -#define SCU_SFSP5_2_EHD_Pos 8 /*!< SCU SFSP5_2: EHD Position */ -#define SCU_SFSP5_2_EHD_Msk (0x03UL << SCU_SFSP5_2_EHD_Pos) /*!< SCU SFSP5_2: EHD Mask */ - -// --------------------------------------- SCU_SFSP5_3 ------------------------------------------ -#define SCU_SFSP5_3_MODE_Pos 0 /*!< SCU SFSP5_3: MODE Position */ -#define SCU_SFSP5_3_MODE_Msk (0x07UL << SCU_SFSP5_3_MODE_Pos) /*!< SCU SFSP5_3: MODE Mask */ -#define SCU_SFSP5_3_EPD_Pos 3 /*!< SCU SFSP5_3: EPD Position */ -#define SCU_SFSP5_3_EPD_Msk (0x01UL << SCU_SFSP5_3_EPD_Pos) /*!< SCU SFSP5_3: EPD Mask */ -#define SCU_SFSP5_3_EPUN_Pos 4 /*!< SCU SFSP5_3: EPUN Position */ -#define SCU_SFSP5_3_EPUN_Msk (0x01UL << SCU_SFSP5_3_EPUN_Pos) /*!< SCU SFSP5_3: EPUN Mask */ -#define SCU_SFSP5_3_EHS_Pos 5 /*!< SCU SFSP5_3: EHS Position */ -#define SCU_SFSP5_3_EHS_Msk (0x01UL << SCU_SFSP5_3_EHS_Pos) /*!< SCU SFSP5_3: EHS Mask */ -#define SCU_SFSP5_3_EZI_Pos 6 /*!< SCU SFSP5_3: EZI Position */ -#define SCU_SFSP5_3_EZI_Msk (0x01UL << SCU_SFSP5_3_EZI_Pos) /*!< SCU SFSP5_3: EZI Mask */ -#define SCU_SFSP5_3_EHD_Pos 8 /*!< SCU SFSP5_3: EHD Position */ -#define SCU_SFSP5_3_EHD_Msk (0x03UL << SCU_SFSP5_3_EHD_Pos) /*!< SCU SFSP5_3: EHD Mask */ - -// --------------------------------------- SCU_SFSP5_4 ------------------------------------------ -#define SCU_SFSP5_4_MODE_Pos 0 /*!< SCU SFSP5_4: MODE Position */ -#define SCU_SFSP5_4_MODE_Msk (0x07UL << SCU_SFSP5_4_MODE_Pos) /*!< SCU SFSP5_4: MODE Mask */ -#define SCU_SFSP5_4_EPD_Pos 3 /*!< SCU SFSP5_4: EPD Position */ -#define SCU_SFSP5_4_EPD_Msk (0x01UL << SCU_SFSP5_4_EPD_Pos) /*!< SCU SFSP5_4: EPD Mask */ -#define SCU_SFSP5_4_EPUN_Pos 4 /*!< SCU SFSP5_4: EPUN Position */ -#define SCU_SFSP5_4_EPUN_Msk (0x01UL << SCU_SFSP5_4_EPUN_Pos) /*!< SCU SFSP5_4: EPUN Mask */ -#define SCU_SFSP5_4_EHS_Pos 5 /*!< SCU SFSP5_4: EHS Position */ -#define SCU_SFSP5_4_EHS_Msk (0x01UL << SCU_SFSP5_4_EHS_Pos) /*!< SCU SFSP5_4: EHS Mask */ -#define SCU_SFSP5_4_EZI_Pos 6 /*!< SCU SFSP5_4: EZI Position */ -#define SCU_SFSP5_4_EZI_Msk (0x01UL << SCU_SFSP5_4_EZI_Pos) /*!< SCU SFSP5_4: EZI Mask */ -#define SCU_SFSP5_4_EHD_Pos 8 /*!< SCU SFSP5_4: EHD Position */ -#define SCU_SFSP5_4_EHD_Msk (0x03UL << SCU_SFSP5_4_EHD_Pos) /*!< SCU SFSP5_4: EHD Mask */ - -// --------------------------------------- SCU_SFSP5_5 ------------------------------------------ -#define SCU_SFSP5_5_MODE_Pos 0 /*!< SCU SFSP5_5: MODE Position */ -#define SCU_SFSP5_5_MODE_Msk (0x07UL << SCU_SFSP5_5_MODE_Pos) /*!< SCU SFSP5_5: MODE Mask */ -#define SCU_SFSP5_5_EPD_Pos 3 /*!< SCU SFSP5_5: EPD Position */ -#define SCU_SFSP5_5_EPD_Msk (0x01UL << SCU_SFSP5_5_EPD_Pos) /*!< SCU SFSP5_5: EPD Mask */ -#define SCU_SFSP5_5_EPUN_Pos 4 /*!< SCU SFSP5_5: EPUN Position */ -#define SCU_SFSP5_5_EPUN_Msk (0x01UL << SCU_SFSP5_5_EPUN_Pos) /*!< SCU SFSP5_5: EPUN Mask */ -#define SCU_SFSP5_5_EHS_Pos 5 /*!< SCU SFSP5_5: EHS Position */ -#define SCU_SFSP5_5_EHS_Msk (0x01UL << SCU_SFSP5_5_EHS_Pos) /*!< SCU SFSP5_5: EHS Mask */ -#define SCU_SFSP5_5_EZI_Pos 6 /*!< SCU SFSP5_5: EZI Position */ -#define SCU_SFSP5_5_EZI_Msk (0x01UL << SCU_SFSP5_5_EZI_Pos) /*!< SCU SFSP5_5: EZI Mask */ -#define SCU_SFSP5_5_EHD_Pos 8 /*!< SCU SFSP5_5: EHD Position */ -#define SCU_SFSP5_5_EHD_Msk (0x03UL << SCU_SFSP5_5_EHD_Pos) /*!< SCU SFSP5_5: EHD Mask */ - -// --------------------------------------- SCU_SFSP5_6 ------------------------------------------ -#define SCU_SFSP5_6_MODE_Pos 0 /*!< SCU SFSP5_6: MODE Position */ -#define SCU_SFSP5_6_MODE_Msk (0x07UL << SCU_SFSP5_6_MODE_Pos) /*!< SCU SFSP5_6: MODE Mask */ -#define SCU_SFSP5_6_EPD_Pos 3 /*!< SCU SFSP5_6: EPD Position */ -#define SCU_SFSP5_6_EPD_Msk (0x01UL << SCU_SFSP5_6_EPD_Pos) /*!< SCU SFSP5_6: EPD Mask */ -#define SCU_SFSP5_6_EPUN_Pos 4 /*!< SCU SFSP5_6: EPUN Position */ -#define SCU_SFSP5_6_EPUN_Msk (0x01UL << SCU_SFSP5_6_EPUN_Pos) /*!< SCU SFSP5_6: EPUN Mask */ -#define SCU_SFSP5_6_EHS_Pos 5 /*!< SCU SFSP5_6: EHS Position */ -#define SCU_SFSP5_6_EHS_Msk (0x01UL << SCU_SFSP5_6_EHS_Pos) /*!< SCU SFSP5_6: EHS Mask */ -#define SCU_SFSP5_6_EZI_Pos 6 /*!< SCU SFSP5_6: EZI Position */ -#define SCU_SFSP5_6_EZI_Msk (0x01UL << SCU_SFSP5_6_EZI_Pos) /*!< SCU SFSP5_6: EZI Mask */ -#define SCU_SFSP5_6_EHD_Pos 8 /*!< SCU SFSP5_6: EHD Position */ -#define SCU_SFSP5_6_EHD_Msk (0x03UL << SCU_SFSP5_6_EHD_Pos) /*!< SCU SFSP5_6: EHD Mask */ - -// --------------------------------------- SCU_SFSP5_7 ------------------------------------------ -#define SCU_SFSP5_7_MODE_Pos 0 /*!< SCU SFSP5_7: MODE Position */ -#define SCU_SFSP5_7_MODE_Msk (0x07UL << SCU_SFSP5_7_MODE_Pos) /*!< SCU SFSP5_7: MODE Mask */ -#define SCU_SFSP5_7_EPD_Pos 3 /*!< SCU SFSP5_7: EPD Position */ -#define SCU_SFSP5_7_EPD_Msk (0x01UL << SCU_SFSP5_7_EPD_Pos) /*!< SCU SFSP5_7: EPD Mask */ -#define SCU_SFSP5_7_EPUN_Pos 4 /*!< SCU SFSP5_7: EPUN Position */ -#define SCU_SFSP5_7_EPUN_Msk (0x01UL << SCU_SFSP5_7_EPUN_Pos) /*!< SCU SFSP5_7: EPUN Mask */ -#define SCU_SFSP5_7_EHS_Pos 5 /*!< SCU SFSP5_7: EHS Position */ -#define SCU_SFSP5_7_EHS_Msk (0x01UL << SCU_SFSP5_7_EHS_Pos) /*!< SCU SFSP5_7: EHS Mask */ -#define SCU_SFSP5_7_EZI_Pos 6 /*!< SCU SFSP5_7: EZI Position */ -#define SCU_SFSP5_7_EZI_Msk (0x01UL << SCU_SFSP5_7_EZI_Pos) /*!< SCU SFSP5_7: EZI Mask */ -#define SCU_SFSP5_7_EHD_Pos 8 /*!< SCU SFSP5_7: EHD Position */ -#define SCU_SFSP5_7_EHD_Msk (0x03UL << SCU_SFSP5_7_EHD_Pos) /*!< SCU SFSP5_7: EHD Mask */ - -// --------------------------------------- SCU_SFSP6_0 ------------------------------------------ -#define SCU_SFSP6_0_MODE_Pos 0 /*!< SCU SFSP6_0: MODE Position */ -#define SCU_SFSP6_0_MODE_Msk (0x07UL << SCU_SFSP6_0_MODE_Pos) /*!< SCU SFSP6_0: MODE Mask */ -#define SCU_SFSP6_0_EPD_Pos 3 /*!< SCU SFSP6_0: EPD Position */ -#define SCU_SFSP6_0_EPD_Msk (0x01UL << SCU_SFSP6_0_EPD_Pos) /*!< SCU SFSP6_0: EPD Mask */ -#define SCU_SFSP6_0_EPUN_Pos 4 /*!< SCU SFSP6_0: EPUN Position */ -#define SCU_SFSP6_0_EPUN_Msk (0x01UL << SCU_SFSP6_0_EPUN_Pos) /*!< SCU SFSP6_0: EPUN Mask */ -#define SCU_SFSP6_0_EHS_Pos 5 /*!< SCU SFSP6_0: EHS Position */ -#define SCU_SFSP6_0_EHS_Msk (0x01UL << SCU_SFSP6_0_EHS_Pos) /*!< SCU SFSP6_0: EHS Mask */ -#define SCU_SFSP6_0_EZI_Pos 6 /*!< SCU SFSP6_0: EZI Position */ -#define SCU_SFSP6_0_EZI_Msk (0x01UL << SCU_SFSP6_0_EZI_Pos) /*!< SCU SFSP6_0: EZI Mask */ -#define SCU_SFSP6_0_EHD_Pos 8 /*!< SCU SFSP6_0: EHD Position */ -#define SCU_SFSP6_0_EHD_Msk (0x03UL << SCU_SFSP6_0_EHD_Pos) /*!< SCU SFSP6_0: EHD Mask */ - -// --------------------------------------- SCU_SFSP6_1 ------------------------------------------ -#define SCU_SFSP6_1_MODE_Pos 0 /*!< SCU SFSP6_1: MODE Position */ -#define SCU_SFSP6_1_MODE_Msk (0x07UL << SCU_SFSP6_1_MODE_Pos) /*!< SCU SFSP6_1: MODE Mask */ -#define SCU_SFSP6_1_EPD_Pos 3 /*!< SCU SFSP6_1: EPD Position */ -#define SCU_SFSP6_1_EPD_Msk (0x01UL << SCU_SFSP6_1_EPD_Pos) /*!< SCU SFSP6_1: EPD Mask */ -#define SCU_SFSP6_1_EPUN_Pos 4 /*!< SCU SFSP6_1: EPUN Position */ -#define SCU_SFSP6_1_EPUN_Msk (0x01UL << SCU_SFSP6_1_EPUN_Pos) /*!< SCU SFSP6_1: EPUN Mask */ -#define SCU_SFSP6_1_EHS_Pos 5 /*!< SCU SFSP6_1: EHS Position */ -#define SCU_SFSP6_1_EHS_Msk (0x01UL << SCU_SFSP6_1_EHS_Pos) /*!< SCU SFSP6_1: EHS Mask */ -#define SCU_SFSP6_1_EZI_Pos 6 /*!< SCU SFSP6_1: EZI Position */ -#define SCU_SFSP6_1_EZI_Msk (0x01UL << SCU_SFSP6_1_EZI_Pos) /*!< SCU SFSP6_1: EZI Mask */ -#define SCU_SFSP6_1_EHD_Pos 8 /*!< SCU SFSP6_1: EHD Position */ -#define SCU_SFSP6_1_EHD_Msk (0x03UL << SCU_SFSP6_1_EHD_Pos) /*!< SCU SFSP6_1: EHD Mask */ - -// --------------------------------------- SCU_SFSP6_2 ------------------------------------------ -#define SCU_SFSP6_2_MODE_Pos 0 /*!< SCU SFSP6_2: MODE Position */ -#define SCU_SFSP6_2_MODE_Msk (0x07UL << SCU_SFSP6_2_MODE_Pos) /*!< SCU SFSP6_2: MODE Mask */ -#define SCU_SFSP6_2_EPD_Pos 3 /*!< SCU SFSP6_2: EPD Position */ -#define SCU_SFSP6_2_EPD_Msk (0x01UL << SCU_SFSP6_2_EPD_Pos) /*!< SCU SFSP6_2: EPD Mask */ -#define SCU_SFSP6_2_EPUN_Pos 4 /*!< SCU SFSP6_2: EPUN Position */ -#define SCU_SFSP6_2_EPUN_Msk (0x01UL << SCU_SFSP6_2_EPUN_Pos) /*!< SCU SFSP6_2: EPUN Mask */ -#define SCU_SFSP6_2_EHS_Pos 5 /*!< SCU SFSP6_2: EHS Position */ -#define SCU_SFSP6_2_EHS_Msk (0x01UL << SCU_SFSP6_2_EHS_Pos) /*!< SCU SFSP6_2: EHS Mask */ -#define SCU_SFSP6_2_EZI_Pos 6 /*!< SCU SFSP6_2: EZI Position */ -#define SCU_SFSP6_2_EZI_Msk (0x01UL << SCU_SFSP6_2_EZI_Pos) /*!< SCU SFSP6_2: EZI Mask */ -#define SCU_SFSP6_2_EHD_Pos 8 /*!< SCU SFSP6_2: EHD Position */ -#define SCU_SFSP6_2_EHD_Msk (0x03UL << SCU_SFSP6_2_EHD_Pos) /*!< SCU SFSP6_2: EHD Mask */ - -// --------------------------------------- SCU_SFSP6_3 ------------------------------------------ -#define SCU_SFSP6_3_MODE_Pos 0 /*!< SCU SFSP6_3: MODE Position */ -#define SCU_SFSP6_3_MODE_Msk (0x07UL << SCU_SFSP6_3_MODE_Pos) /*!< SCU SFSP6_3: MODE Mask */ -#define SCU_SFSP6_3_EPD_Pos 3 /*!< SCU SFSP6_3: EPD Position */ -#define SCU_SFSP6_3_EPD_Msk (0x01UL << SCU_SFSP6_3_EPD_Pos) /*!< SCU SFSP6_3: EPD Mask */ -#define SCU_SFSP6_3_EPUN_Pos 4 /*!< SCU SFSP6_3: EPUN Position */ -#define SCU_SFSP6_3_EPUN_Msk (0x01UL << SCU_SFSP6_3_EPUN_Pos) /*!< SCU SFSP6_3: EPUN Mask */ -#define SCU_SFSP6_3_EHS_Pos 5 /*!< SCU SFSP6_3: EHS Position */ -#define SCU_SFSP6_3_EHS_Msk (0x01UL << SCU_SFSP6_3_EHS_Pos) /*!< SCU SFSP6_3: EHS Mask */ -#define SCU_SFSP6_3_EZI_Pos 6 /*!< SCU SFSP6_3: EZI Position */ -#define SCU_SFSP6_3_EZI_Msk (0x01UL << SCU_SFSP6_3_EZI_Pos) /*!< SCU SFSP6_3: EZI Mask */ -#define SCU_SFSP6_3_EHD_Pos 8 /*!< SCU SFSP6_3: EHD Position */ -#define SCU_SFSP6_3_EHD_Msk (0x03UL << SCU_SFSP6_3_EHD_Pos) /*!< SCU SFSP6_3: EHD Mask */ - -// --------------------------------------- SCU_SFSP6_4 ------------------------------------------ -#define SCU_SFSP6_4_MODE_Pos 0 /*!< SCU SFSP6_4: MODE Position */ -#define SCU_SFSP6_4_MODE_Msk (0x07UL << SCU_SFSP6_4_MODE_Pos) /*!< SCU SFSP6_4: MODE Mask */ -#define SCU_SFSP6_4_EPD_Pos 3 /*!< SCU SFSP6_4: EPD Position */ -#define SCU_SFSP6_4_EPD_Msk (0x01UL << SCU_SFSP6_4_EPD_Pos) /*!< SCU SFSP6_4: EPD Mask */ -#define SCU_SFSP6_4_EPUN_Pos 4 /*!< SCU SFSP6_4: EPUN Position */ -#define SCU_SFSP6_4_EPUN_Msk (0x01UL << SCU_SFSP6_4_EPUN_Pos) /*!< SCU SFSP6_4: EPUN Mask */ -#define SCU_SFSP6_4_EHS_Pos 5 /*!< SCU SFSP6_4: EHS Position */ -#define SCU_SFSP6_4_EHS_Msk (0x01UL << SCU_SFSP6_4_EHS_Pos) /*!< SCU SFSP6_4: EHS Mask */ -#define SCU_SFSP6_4_EZI_Pos 6 /*!< SCU SFSP6_4: EZI Position */ -#define SCU_SFSP6_4_EZI_Msk (0x01UL << SCU_SFSP6_4_EZI_Pos) /*!< SCU SFSP6_4: EZI Mask */ -#define SCU_SFSP6_4_EHD_Pos 8 /*!< SCU SFSP6_4: EHD Position */ -#define SCU_SFSP6_4_EHD_Msk (0x03UL << SCU_SFSP6_4_EHD_Pos) /*!< SCU SFSP6_4: EHD Mask */ - -// --------------------------------------- SCU_SFSP6_5 ------------------------------------------ -#define SCU_SFSP6_5_MODE_Pos 0 /*!< SCU SFSP6_5: MODE Position */ -#define SCU_SFSP6_5_MODE_Msk (0x07UL << SCU_SFSP6_5_MODE_Pos) /*!< SCU SFSP6_5: MODE Mask */ -#define SCU_SFSP6_5_EPD_Pos 3 /*!< SCU SFSP6_5: EPD Position */ -#define SCU_SFSP6_5_EPD_Msk (0x01UL << SCU_SFSP6_5_EPD_Pos) /*!< SCU SFSP6_5: EPD Mask */ -#define SCU_SFSP6_5_EPUN_Pos 4 /*!< SCU SFSP6_5: EPUN Position */ -#define SCU_SFSP6_5_EPUN_Msk (0x01UL << SCU_SFSP6_5_EPUN_Pos) /*!< SCU SFSP6_5: EPUN Mask */ -#define SCU_SFSP6_5_EHS_Pos 5 /*!< SCU SFSP6_5: EHS Position */ -#define SCU_SFSP6_5_EHS_Msk (0x01UL << SCU_SFSP6_5_EHS_Pos) /*!< SCU SFSP6_5: EHS Mask */ -#define SCU_SFSP6_5_EZI_Pos 6 /*!< SCU SFSP6_5: EZI Position */ -#define SCU_SFSP6_5_EZI_Msk (0x01UL << SCU_SFSP6_5_EZI_Pos) /*!< SCU SFSP6_5: EZI Mask */ -#define SCU_SFSP6_5_EHD_Pos 8 /*!< SCU SFSP6_5: EHD Position */ -#define SCU_SFSP6_5_EHD_Msk (0x03UL << SCU_SFSP6_5_EHD_Pos) /*!< SCU SFSP6_5: EHD Mask */ - -// --------------------------------------- SCU_SFSP6_6 ------------------------------------------ -#define SCU_SFSP6_6_MODE_Pos 0 /*!< SCU SFSP6_6: MODE Position */ -#define SCU_SFSP6_6_MODE_Msk (0x07UL << SCU_SFSP6_6_MODE_Pos) /*!< SCU SFSP6_6: MODE Mask */ -#define SCU_SFSP6_6_EPD_Pos 3 /*!< SCU SFSP6_6: EPD Position */ -#define SCU_SFSP6_6_EPD_Msk (0x01UL << SCU_SFSP6_6_EPD_Pos) /*!< SCU SFSP6_6: EPD Mask */ -#define SCU_SFSP6_6_EPUN_Pos 4 /*!< SCU SFSP6_6: EPUN Position */ -#define SCU_SFSP6_6_EPUN_Msk (0x01UL << SCU_SFSP6_6_EPUN_Pos) /*!< SCU SFSP6_6: EPUN Mask */ -#define SCU_SFSP6_6_EHS_Pos 5 /*!< SCU SFSP6_6: EHS Position */ -#define SCU_SFSP6_6_EHS_Msk (0x01UL << SCU_SFSP6_6_EHS_Pos) /*!< SCU SFSP6_6: EHS Mask */ -#define SCU_SFSP6_6_EZI_Pos 6 /*!< SCU SFSP6_6: EZI Position */ -#define SCU_SFSP6_6_EZI_Msk (0x01UL << SCU_SFSP6_6_EZI_Pos) /*!< SCU SFSP6_6: EZI Mask */ -#define SCU_SFSP6_6_EHD_Pos 8 /*!< SCU SFSP6_6: EHD Position */ -#define SCU_SFSP6_6_EHD_Msk (0x03UL << SCU_SFSP6_6_EHD_Pos) /*!< SCU SFSP6_6: EHD Mask */ - -// --------------------------------------- SCU_SFSP6_7 ------------------------------------------ -#define SCU_SFSP6_7_MODE_Pos 0 /*!< SCU SFSP6_7: MODE Position */ -#define SCU_SFSP6_7_MODE_Msk (0x07UL << SCU_SFSP6_7_MODE_Pos) /*!< SCU SFSP6_7: MODE Mask */ -#define SCU_SFSP6_7_EPD_Pos 3 /*!< SCU SFSP6_7: EPD Position */ -#define SCU_SFSP6_7_EPD_Msk (0x01UL << SCU_SFSP6_7_EPD_Pos) /*!< SCU SFSP6_7: EPD Mask */ -#define SCU_SFSP6_7_EPUN_Pos 4 /*!< SCU SFSP6_7: EPUN Position */ -#define SCU_SFSP6_7_EPUN_Msk (0x01UL << SCU_SFSP6_7_EPUN_Pos) /*!< SCU SFSP6_7: EPUN Mask */ -#define SCU_SFSP6_7_EHS_Pos 5 /*!< SCU SFSP6_7: EHS Position */ -#define SCU_SFSP6_7_EHS_Msk (0x01UL << SCU_SFSP6_7_EHS_Pos) /*!< SCU SFSP6_7: EHS Mask */ -#define SCU_SFSP6_7_EZI_Pos 6 /*!< SCU SFSP6_7: EZI Position */ -#define SCU_SFSP6_7_EZI_Msk (0x01UL << SCU_SFSP6_7_EZI_Pos) /*!< SCU SFSP6_7: EZI Mask */ -#define SCU_SFSP6_7_EHD_Pos 8 /*!< SCU SFSP6_7: EHD Position */ -#define SCU_SFSP6_7_EHD_Msk (0x03UL << SCU_SFSP6_7_EHD_Pos) /*!< SCU SFSP6_7: EHD Mask */ - -// --------------------------------------- SCU_SFSP6_8 ------------------------------------------ -#define SCU_SFSP6_8_MODE_Pos 0 /*!< SCU SFSP6_8: MODE Position */ -#define SCU_SFSP6_8_MODE_Msk (0x07UL << SCU_SFSP6_8_MODE_Pos) /*!< SCU SFSP6_8: MODE Mask */ -#define SCU_SFSP6_8_EPD_Pos 3 /*!< SCU SFSP6_8: EPD Position */ -#define SCU_SFSP6_8_EPD_Msk (0x01UL << SCU_SFSP6_8_EPD_Pos) /*!< SCU SFSP6_8: EPD Mask */ -#define SCU_SFSP6_8_EPUN_Pos 4 /*!< SCU SFSP6_8: EPUN Position */ -#define SCU_SFSP6_8_EPUN_Msk (0x01UL << SCU_SFSP6_8_EPUN_Pos) /*!< SCU SFSP6_8: EPUN Mask */ -#define SCU_SFSP6_8_EHS_Pos 5 /*!< SCU SFSP6_8: EHS Position */ -#define SCU_SFSP6_8_EHS_Msk (0x01UL << SCU_SFSP6_8_EHS_Pos) /*!< SCU SFSP6_8: EHS Mask */ -#define SCU_SFSP6_8_EZI_Pos 6 /*!< SCU SFSP6_8: EZI Position */ -#define SCU_SFSP6_8_EZI_Msk (0x01UL << SCU_SFSP6_8_EZI_Pos) /*!< SCU SFSP6_8: EZI Mask */ -#define SCU_SFSP6_8_EHD_Pos 8 /*!< SCU SFSP6_8: EHD Position */ -#define SCU_SFSP6_8_EHD_Msk (0x03UL << SCU_SFSP6_8_EHD_Pos) /*!< SCU SFSP6_8: EHD Mask */ - -// --------------------------------------- SCU_SFSP6_9 ------------------------------------------ -#define SCU_SFSP6_9_MODE_Pos 0 /*!< SCU SFSP6_9: MODE Position */ -#define SCU_SFSP6_9_MODE_Msk (0x07UL << SCU_SFSP6_9_MODE_Pos) /*!< SCU SFSP6_9: MODE Mask */ -#define SCU_SFSP6_9_EPD_Pos 3 /*!< SCU SFSP6_9: EPD Position */ -#define SCU_SFSP6_9_EPD_Msk (0x01UL << SCU_SFSP6_9_EPD_Pos) /*!< SCU SFSP6_9: EPD Mask */ -#define SCU_SFSP6_9_EPUN_Pos 4 /*!< SCU SFSP6_9: EPUN Position */ -#define SCU_SFSP6_9_EPUN_Msk (0x01UL << SCU_SFSP6_9_EPUN_Pos) /*!< SCU SFSP6_9: EPUN Mask */ -#define SCU_SFSP6_9_EHS_Pos 5 /*!< SCU SFSP6_9: EHS Position */ -#define SCU_SFSP6_9_EHS_Msk (0x01UL << SCU_SFSP6_9_EHS_Pos) /*!< SCU SFSP6_9: EHS Mask */ -#define SCU_SFSP6_9_EZI_Pos 6 /*!< SCU SFSP6_9: EZI Position */ -#define SCU_SFSP6_9_EZI_Msk (0x01UL << SCU_SFSP6_9_EZI_Pos) /*!< SCU SFSP6_9: EZI Mask */ -#define SCU_SFSP6_9_EHD_Pos 8 /*!< SCU SFSP6_9: EHD Position */ -#define SCU_SFSP6_9_EHD_Msk (0x03UL << SCU_SFSP6_9_EHD_Pos) /*!< SCU SFSP6_9: EHD Mask */ - -// -------------------------------------- SCU_SFSP6_10 ------------------------------------------ -#define SCU_SFSP6_10_MODE_Pos 0 /*!< SCU SFSP6_10: MODE Position */ -#define SCU_SFSP6_10_MODE_Msk (0x07UL << SCU_SFSP6_10_MODE_Pos) /*!< SCU SFSP6_10: MODE Mask */ -#define SCU_SFSP6_10_EPD_Pos 3 /*!< SCU SFSP6_10: EPD Position */ -#define SCU_SFSP6_10_EPD_Msk (0x01UL << SCU_SFSP6_10_EPD_Pos) /*!< SCU SFSP6_10: EPD Mask */ -#define SCU_SFSP6_10_EPUN_Pos 4 /*!< SCU SFSP6_10: EPUN Position */ -#define SCU_SFSP6_10_EPUN_Msk (0x01UL << SCU_SFSP6_10_EPUN_Pos) /*!< SCU SFSP6_10: EPUN Mask */ -#define SCU_SFSP6_10_EHS_Pos 5 /*!< SCU SFSP6_10: EHS Position */ -#define SCU_SFSP6_10_EHS_Msk (0x01UL << SCU_SFSP6_10_EHS_Pos) /*!< SCU SFSP6_10: EHS Mask */ -#define SCU_SFSP6_10_EZI_Pos 6 /*!< SCU SFSP6_10: EZI Position */ -#define SCU_SFSP6_10_EZI_Msk (0x01UL << SCU_SFSP6_10_EZI_Pos) /*!< SCU SFSP6_10: EZI Mask */ -#define SCU_SFSP6_10_EHD_Pos 8 /*!< SCU SFSP6_10: EHD Position */ -#define SCU_SFSP6_10_EHD_Msk (0x03UL << SCU_SFSP6_10_EHD_Pos) /*!< SCU SFSP6_10: EHD Mask */ - -// -------------------------------------- SCU_SFSP6_11 ------------------------------------------ -#define SCU_SFSP6_11_MODE_Pos 0 /*!< SCU SFSP6_11: MODE Position */ -#define SCU_SFSP6_11_MODE_Msk (0x07UL << SCU_SFSP6_11_MODE_Pos) /*!< SCU SFSP6_11: MODE Mask */ -#define SCU_SFSP6_11_EPD_Pos 3 /*!< SCU SFSP6_11: EPD Position */ -#define SCU_SFSP6_11_EPD_Msk (0x01UL << SCU_SFSP6_11_EPD_Pos) /*!< SCU SFSP6_11: EPD Mask */ -#define SCU_SFSP6_11_EPUN_Pos 4 /*!< SCU SFSP6_11: EPUN Position */ -#define SCU_SFSP6_11_EPUN_Msk (0x01UL << SCU_SFSP6_11_EPUN_Pos) /*!< SCU SFSP6_11: EPUN Mask */ -#define SCU_SFSP6_11_EHS_Pos 5 /*!< SCU SFSP6_11: EHS Position */ -#define SCU_SFSP6_11_EHS_Msk (0x01UL << SCU_SFSP6_11_EHS_Pos) /*!< SCU SFSP6_11: EHS Mask */ -#define SCU_SFSP6_11_EZI_Pos 6 /*!< SCU SFSP6_11: EZI Position */ -#define SCU_SFSP6_11_EZI_Msk (0x01UL << SCU_SFSP6_11_EZI_Pos) /*!< SCU SFSP6_11: EZI Mask */ -#define SCU_SFSP6_11_EHD_Pos 8 /*!< SCU SFSP6_11: EHD Position */ -#define SCU_SFSP6_11_EHD_Msk (0x03UL << SCU_SFSP6_11_EHD_Pos) /*!< SCU SFSP6_11: EHD Mask */ - -// -------------------------------------- SCU_SFSP6_12 ------------------------------------------ -#define SCU_SFSP6_12_MODE_Pos 0 /*!< SCU SFSP6_12: MODE Position */ -#define SCU_SFSP6_12_MODE_Msk (0x07UL << SCU_SFSP6_12_MODE_Pos) /*!< SCU SFSP6_12: MODE Mask */ -#define SCU_SFSP6_12_EPD_Pos 3 /*!< SCU SFSP6_12: EPD Position */ -#define SCU_SFSP6_12_EPD_Msk (0x01UL << SCU_SFSP6_12_EPD_Pos) /*!< SCU SFSP6_12: EPD Mask */ -#define SCU_SFSP6_12_EPUN_Pos 4 /*!< SCU SFSP6_12: EPUN Position */ -#define SCU_SFSP6_12_EPUN_Msk (0x01UL << SCU_SFSP6_12_EPUN_Pos) /*!< SCU SFSP6_12: EPUN Mask */ -#define SCU_SFSP6_12_EHS_Pos 5 /*!< SCU SFSP6_12: EHS Position */ -#define SCU_SFSP6_12_EHS_Msk (0x01UL << SCU_SFSP6_12_EHS_Pos) /*!< SCU SFSP6_12: EHS Mask */ -#define SCU_SFSP6_12_EZI_Pos 6 /*!< SCU SFSP6_12: EZI Position */ -#define SCU_SFSP6_12_EZI_Msk (0x01UL << SCU_SFSP6_12_EZI_Pos) /*!< SCU SFSP6_12: EZI Mask */ -#define SCU_SFSP6_12_EHD_Pos 8 /*!< SCU SFSP6_12: EHD Position */ -#define SCU_SFSP6_12_EHD_Msk (0x03UL << SCU_SFSP6_12_EHD_Pos) /*!< SCU SFSP6_12: EHD Mask */ - -// --------------------------------------- SCU_SFSP7_0 ------------------------------------------ -#define SCU_SFSP7_0_MODE_Pos 0 /*!< SCU SFSP7_0: MODE Position */ -#define SCU_SFSP7_0_MODE_Msk (0x07UL << SCU_SFSP7_0_MODE_Pos) /*!< SCU SFSP7_0: MODE Mask */ -#define SCU_SFSP7_0_EPD_Pos 3 /*!< SCU SFSP7_0: EPD Position */ -#define SCU_SFSP7_0_EPD_Msk (0x01UL << SCU_SFSP7_0_EPD_Pos) /*!< SCU SFSP7_0: EPD Mask */ -#define SCU_SFSP7_0_EPUN_Pos 4 /*!< SCU SFSP7_0: EPUN Position */ -#define SCU_SFSP7_0_EPUN_Msk (0x01UL << SCU_SFSP7_0_EPUN_Pos) /*!< SCU SFSP7_0: EPUN Mask */ -#define SCU_SFSP7_0_EHS_Pos 5 /*!< SCU SFSP7_0: EHS Position */ -#define SCU_SFSP7_0_EHS_Msk (0x01UL << SCU_SFSP7_0_EHS_Pos) /*!< SCU SFSP7_0: EHS Mask */ -#define SCU_SFSP7_0_EZI_Pos 6 /*!< SCU SFSP7_0: EZI Position */ -#define SCU_SFSP7_0_EZI_Msk (0x01UL << SCU_SFSP7_0_EZI_Pos) /*!< SCU SFSP7_0: EZI Mask */ -#define SCU_SFSP7_0_EHD_Pos 8 /*!< SCU SFSP7_0: EHD Position */ -#define SCU_SFSP7_0_EHD_Msk (0x03UL << SCU_SFSP7_0_EHD_Pos) /*!< SCU SFSP7_0: EHD Mask */ - -// --------------------------------------- SCU_SFSP7_1 ------------------------------------------ -#define SCU_SFSP7_1_MODE_Pos 0 /*!< SCU SFSP7_1: MODE Position */ -#define SCU_SFSP7_1_MODE_Msk (0x07UL << SCU_SFSP7_1_MODE_Pos) /*!< SCU SFSP7_1: MODE Mask */ -#define SCU_SFSP7_1_EPD_Pos 3 /*!< SCU SFSP7_1: EPD Position */ -#define SCU_SFSP7_1_EPD_Msk (0x01UL << SCU_SFSP7_1_EPD_Pos) /*!< SCU SFSP7_1: EPD Mask */ -#define SCU_SFSP7_1_EPUN_Pos 4 /*!< SCU SFSP7_1: EPUN Position */ -#define SCU_SFSP7_1_EPUN_Msk (0x01UL << SCU_SFSP7_1_EPUN_Pos) /*!< SCU SFSP7_1: EPUN Mask */ -#define SCU_SFSP7_1_EHS_Pos 5 /*!< SCU SFSP7_1: EHS Position */ -#define SCU_SFSP7_1_EHS_Msk (0x01UL << SCU_SFSP7_1_EHS_Pos) /*!< SCU SFSP7_1: EHS Mask */ -#define SCU_SFSP7_1_EZI_Pos 6 /*!< SCU SFSP7_1: EZI Position */ -#define SCU_SFSP7_1_EZI_Msk (0x01UL << SCU_SFSP7_1_EZI_Pos) /*!< SCU SFSP7_1: EZI Mask */ -#define SCU_SFSP7_1_EHD_Pos 8 /*!< SCU SFSP7_1: EHD Position */ -#define SCU_SFSP7_1_EHD_Msk (0x03UL << SCU_SFSP7_1_EHD_Pos) /*!< SCU SFSP7_1: EHD Mask */ - -// --------------------------------------- SCU_SFSP7_2 ------------------------------------------ -#define SCU_SFSP7_2_MODE_Pos 0 /*!< SCU SFSP7_2: MODE Position */ -#define SCU_SFSP7_2_MODE_Msk (0x07UL << SCU_SFSP7_2_MODE_Pos) /*!< SCU SFSP7_2: MODE Mask */ -#define SCU_SFSP7_2_EPD_Pos 3 /*!< SCU SFSP7_2: EPD Position */ -#define SCU_SFSP7_2_EPD_Msk (0x01UL << SCU_SFSP7_2_EPD_Pos) /*!< SCU SFSP7_2: EPD Mask */ -#define SCU_SFSP7_2_EPUN_Pos 4 /*!< SCU SFSP7_2: EPUN Position */ -#define SCU_SFSP7_2_EPUN_Msk (0x01UL << SCU_SFSP7_2_EPUN_Pos) /*!< SCU SFSP7_2: EPUN Mask */ -#define SCU_SFSP7_2_EHS_Pos 5 /*!< SCU SFSP7_2: EHS Position */ -#define SCU_SFSP7_2_EHS_Msk (0x01UL << SCU_SFSP7_2_EHS_Pos) /*!< SCU SFSP7_2: EHS Mask */ -#define SCU_SFSP7_2_EZI_Pos 6 /*!< SCU SFSP7_2: EZI Position */ -#define SCU_SFSP7_2_EZI_Msk (0x01UL << SCU_SFSP7_2_EZI_Pos) /*!< SCU SFSP7_2: EZI Mask */ -#define SCU_SFSP7_2_EHD_Pos 8 /*!< SCU SFSP7_2: EHD Position */ -#define SCU_SFSP7_2_EHD_Msk (0x03UL << SCU_SFSP7_2_EHD_Pos) /*!< SCU SFSP7_2: EHD Mask */ - -// --------------------------------------- SCU_SFSP7_3 ------------------------------------------ -#define SCU_SFSP7_3_MODE_Pos 0 /*!< SCU SFSP7_3: MODE Position */ -#define SCU_SFSP7_3_MODE_Msk (0x07UL << SCU_SFSP7_3_MODE_Pos) /*!< SCU SFSP7_3: MODE Mask */ -#define SCU_SFSP7_3_EPD_Pos 3 /*!< SCU SFSP7_3: EPD Position */ -#define SCU_SFSP7_3_EPD_Msk (0x01UL << SCU_SFSP7_3_EPD_Pos) /*!< SCU SFSP7_3: EPD Mask */ -#define SCU_SFSP7_3_EPUN_Pos 4 /*!< SCU SFSP7_3: EPUN Position */ -#define SCU_SFSP7_3_EPUN_Msk (0x01UL << SCU_SFSP7_3_EPUN_Pos) /*!< SCU SFSP7_3: EPUN Mask */ -#define SCU_SFSP7_3_EHS_Pos 5 /*!< SCU SFSP7_3: EHS Position */ -#define SCU_SFSP7_3_EHS_Msk (0x01UL << SCU_SFSP7_3_EHS_Pos) /*!< SCU SFSP7_3: EHS Mask */ -#define SCU_SFSP7_3_EZI_Pos 6 /*!< SCU SFSP7_3: EZI Position */ -#define SCU_SFSP7_3_EZI_Msk (0x01UL << SCU_SFSP7_3_EZI_Pos) /*!< SCU SFSP7_3: EZI Mask */ -#define SCU_SFSP7_3_EHD_Pos 8 /*!< SCU SFSP7_3: EHD Position */ -#define SCU_SFSP7_3_EHD_Msk (0x03UL << SCU_SFSP7_3_EHD_Pos) /*!< SCU SFSP7_3: EHD Mask */ - -// --------------------------------------- SCU_SFSP7_4 ------------------------------------------ -#define SCU_SFSP7_4_MODE_Pos 0 /*!< SCU SFSP7_4: MODE Position */ -#define SCU_SFSP7_4_MODE_Msk (0x07UL << SCU_SFSP7_4_MODE_Pos) /*!< SCU SFSP7_4: MODE Mask */ -#define SCU_SFSP7_4_EPD_Pos 3 /*!< SCU SFSP7_4: EPD Position */ -#define SCU_SFSP7_4_EPD_Msk (0x01UL << SCU_SFSP7_4_EPD_Pos) /*!< SCU SFSP7_4: EPD Mask */ -#define SCU_SFSP7_4_EPUN_Pos 4 /*!< SCU SFSP7_4: EPUN Position */ -#define SCU_SFSP7_4_EPUN_Msk (0x01UL << SCU_SFSP7_4_EPUN_Pos) /*!< SCU SFSP7_4: EPUN Mask */ -#define SCU_SFSP7_4_EHS_Pos 5 /*!< SCU SFSP7_4: EHS Position */ -#define SCU_SFSP7_4_EHS_Msk (0x01UL << SCU_SFSP7_4_EHS_Pos) /*!< SCU SFSP7_4: EHS Mask */ -#define SCU_SFSP7_4_EZI_Pos 6 /*!< SCU SFSP7_4: EZI Position */ -#define SCU_SFSP7_4_EZI_Msk (0x01UL << SCU_SFSP7_4_EZI_Pos) /*!< SCU SFSP7_4: EZI Mask */ -#define SCU_SFSP7_4_EHD_Pos 8 /*!< SCU SFSP7_4: EHD Position */ -#define SCU_SFSP7_4_EHD_Msk (0x03UL << SCU_SFSP7_4_EHD_Pos) /*!< SCU SFSP7_4: EHD Mask */ - -// --------------------------------------- SCU_SFSP7_5 ------------------------------------------ -#define SCU_SFSP7_5_MODE_Pos 0 /*!< SCU SFSP7_5: MODE Position */ -#define SCU_SFSP7_5_MODE_Msk (0x07UL << SCU_SFSP7_5_MODE_Pos) /*!< SCU SFSP7_5: MODE Mask */ -#define SCU_SFSP7_5_EPD_Pos 3 /*!< SCU SFSP7_5: EPD Position */ -#define SCU_SFSP7_5_EPD_Msk (0x01UL << SCU_SFSP7_5_EPD_Pos) /*!< SCU SFSP7_5: EPD Mask */ -#define SCU_SFSP7_5_EPUN_Pos 4 /*!< SCU SFSP7_5: EPUN Position */ -#define SCU_SFSP7_5_EPUN_Msk (0x01UL << SCU_SFSP7_5_EPUN_Pos) /*!< SCU SFSP7_5: EPUN Mask */ -#define SCU_SFSP7_5_EHS_Pos 5 /*!< SCU SFSP7_5: EHS Position */ -#define SCU_SFSP7_5_EHS_Msk (0x01UL << SCU_SFSP7_5_EHS_Pos) /*!< SCU SFSP7_5: EHS Mask */ -#define SCU_SFSP7_5_EZI_Pos 6 /*!< SCU SFSP7_5: EZI Position */ -#define SCU_SFSP7_5_EZI_Msk (0x01UL << SCU_SFSP7_5_EZI_Pos) /*!< SCU SFSP7_5: EZI Mask */ -#define SCU_SFSP7_5_EHD_Pos 8 /*!< SCU SFSP7_5: EHD Position */ -#define SCU_SFSP7_5_EHD_Msk (0x03UL << SCU_SFSP7_5_EHD_Pos) /*!< SCU SFSP7_5: EHD Mask */ - -// --------------------------------------- SCU_SFSP7_6 ------------------------------------------ -#define SCU_SFSP7_6_MODE_Pos 0 /*!< SCU SFSP7_6: MODE Position */ -#define SCU_SFSP7_6_MODE_Msk (0x07UL << SCU_SFSP7_6_MODE_Pos) /*!< SCU SFSP7_6: MODE Mask */ -#define SCU_SFSP7_6_EPD_Pos 3 /*!< SCU SFSP7_6: EPD Position */ -#define SCU_SFSP7_6_EPD_Msk (0x01UL << SCU_SFSP7_6_EPD_Pos) /*!< SCU SFSP7_6: EPD Mask */ -#define SCU_SFSP7_6_EPUN_Pos 4 /*!< SCU SFSP7_6: EPUN Position */ -#define SCU_SFSP7_6_EPUN_Msk (0x01UL << SCU_SFSP7_6_EPUN_Pos) /*!< SCU SFSP7_6: EPUN Mask */ -#define SCU_SFSP7_6_EHS_Pos 5 /*!< SCU SFSP7_6: EHS Position */ -#define SCU_SFSP7_6_EHS_Msk (0x01UL << SCU_SFSP7_6_EHS_Pos) /*!< SCU SFSP7_6: EHS Mask */ -#define SCU_SFSP7_6_EZI_Pos 6 /*!< SCU SFSP7_6: EZI Position */ -#define SCU_SFSP7_6_EZI_Msk (0x01UL << SCU_SFSP7_6_EZI_Pos) /*!< SCU SFSP7_6: EZI Mask */ -#define SCU_SFSP7_6_EHD_Pos 8 /*!< SCU SFSP7_6: EHD Position */ -#define SCU_SFSP7_6_EHD_Msk (0x03UL << SCU_SFSP7_6_EHD_Pos) /*!< SCU SFSP7_6: EHD Mask */ - -// --------------------------------------- SCU_SFSP7_7 ------------------------------------------ -#define SCU_SFSP7_7_MODE_Pos 0 /*!< SCU SFSP7_7: MODE Position */ -#define SCU_SFSP7_7_MODE_Msk (0x07UL << SCU_SFSP7_7_MODE_Pos) /*!< SCU SFSP7_7: MODE Mask */ -#define SCU_SFSP7_7_EPD_Pos 3 /*!< SCU SFSP7_7: EPD Position */ -#define SCU_SFSP7_7_EPD_Msk (0x01UL << SCU_SFSP7_7_EPD_Pos) /*!< SCU SFSP7_7: EPD Mask */ -#define SCU_SFSP7_7_EPUN_Pos 4 /*!< SCU SFSP7_7: EPUN Position */ -#define SCU_SFSP7_7_EPUN_Msk (0x01UL << SCU_SFSP7_7_EPUN_Pos) /*!< SCU SFSP7_7: EPUN Mask */ -#define SCU_SFSP7_7_EHS_Pos 5 /*!< SCU SFSP7_7: EHS Position */ -#define SCU_SFSP7_7_EHS_Msk (0x01UL << SCU_SFSP7_7_EHS_Pos) /*!< SCU SFSP7_7: EHS Mask */ -#define SCU_SFSP7_7_EZI_Pos 6 /*!< SCU SFSP7_7: EZI Position */ -#define SCU_SFSP7_7_EZI_Msk (0x01UL << SCU_SFSP7_7_EZI_Pos) /*!< SCU SFSP7_7: EZI Mask */ -#define SCU_SFSP7_7_EHD_Pos 8 /*!< SCU SFSP7_7: EHD Position */ -#define SCU_SFSP7_7_EHD_Msk (0x03UL << SCU_SFSP7_7_EHD_Pos) /*!< SCU SFSP7_7: EHD Mask */ - -// --------------------------------------- SCU_SFSP8_0 ------------------------------------------ -#define SCU_SFSP8_0_MODE_Pos 0 /*!< SCU SFSP8_0: MODE Position */ -#define SCU_SFSP8_0_MODE_Msk (0x07UL << SCU_SFSP8_0_MODE_Pos) /*!< SCU SFSP8_0: MODE Mask */ -#define SCU_SFSP8_0_EPD_Pos 3 /*!< SCU SFSP8_0: EPD Position */ -#define SCU_SFSP8_0_EPD_Msk (0x01UL << SCU_SFSP8_0_EPD_Pos) /*!< SCU SFSP8_0: EPD Mask */ -#define SCU_SFSP8_0_EPUN_Pos 4 /*!< SCU SFSP8_0: EPUN Position */ -#define SCU_SFSP8_0_EPUN_Msk (0x01UL << SCU_SFSP8_0_EPUN_Pos) /*!< SCU SFSP8_0: EPUN Mask */ -#define SCU_SFSP8_0_EHS_Pos 5 /*!< SCU SFSP8_0: EHS Position */ -#define SCU_SFSP8_0_EHS_Msk (0x01UL << SCU_SFSP8_0_EHS_Pos) /*!< SCU SFSP8_0: EHS Mask */ -#define SCU_SFSP8_0_EZI_Pos 6 /*!< SCU SFSP8_0: EZI Position */ -#define SCU_SFSP8_0_EZI_Msk (0x01UL << SCU_SFSP8_0_EZI_Pos) /*!< SCU SFSP8_0: EZI Mask */ -#define SCU_SFSP8_0_EHD_Pos 8 /*!< SCU SFSP8_0: EHD Position */ -#define SCU_SFSP8_0_EHD_Msk (0x03UL << SCU_SFSP8_0_EHD_Pos) /*!< SCU SFSP8_0: EHD Mask */ - -// --------------------------------------- SCU_SFSP8_1 ------------------------------------------ -#define SCU_SFSP8_1_MODE_Pos 0 /*!< SCU SFSP8_1: MODE Position */ -#define SCU_SFSP8_1_MODE_Msk (0x07UL << SCU_SFSP8_1_MODE_Pos) /*!< SCU SFSP8_1: MODE Mask */ -#define SCU_SFSP8_1_EPD_Pos 3 /*!< SCU SFSP8_1: EPD Position */ -#define SCU_SFSP8_1_EPD_Msk (0x01UL << SCU_SFSP8_1_EPD_Pos) /*!< SCU SFSP8_1: EPD Mask */ -#define SCU_SFSP8_1_EPUN_Pos 4 /*!< SCU SFSP8_1: EPUN Position */ -#define SCU_SFSP8_1_EPUN_Msk (0x01UL << SCU_SFSP8_1_EPUN_Pos) /*!< SCU SFSP8_1: EPUN Mask */ -#define SCU_SFSP8_1_EHS_Pos 5 /*!< SCU SFSP8_1: EHS Position */ -#define SCU_SFSP8_1_EHS_Msk (0x01UL << SCU_SFSP8_1_EHS_Pos) /*!< SCU SFSP8_1: EHS Mask */ -#define SCU_SFSP8_1_EZI_Pos 6 /*!< SCU SFSP8_1: EZI Position */ -#define SCU_SFSP8_1_EZI_Msk (0x01UL << SCU_SFSP8_1_EZI_Pos) /*!< SCU SFSP8_1: EZI Mask */ -#define SCU_SFSP8_1_EHD_Pos 8 /*!< SCU SFSP8_1: EHD Position */ -#define SCU_SFSP8_1_EHD_Msk (0x03UL << SCU_SFSP8_1_EHD_Pos) /*!< SCU SFSP8_1: EHD Mask */ - -// --------------------------------------- SCU_SFSP8_2 ------------------------------------------ -#define SCU_SFSP8_2_MODE_Pos 0 /*!< SCU SFSP8_2: MODE Position */ -#define SCU_SFSP8_2_MODE_Msk (0x07UL << SCU_SFSP8_2_MODE_Pos) /*!< SCU SFSP8_2: MODE Mask */ -#define SCU_SFSP8_2_EPD_Pos 3 /*!< SCU SFSP8_2: EPD Position */ -#define SCU_SFSP8_2_EPD_Msk (0x01UL << SCU_SFSP8_2_EPD_Pos) /*!< SCU SFSP8_2: EPD Mask */ -#define SCU_SFSP8_2_EPUN_Pos 4 /*!< SCU SFSP8_2: EPUN Position */ -#define SCU_SFSP8_2_EPUN_Msk (0x01UL << SCU_SFSP8_2_EPUN_Pos) /*!< SCU SFSP8_2: EPUN Mask */ -#define SCU_SFSP8_2_EHS_Pos 5 /*!< SCU SFSP8_2: EHS Position */ -#define SCU_SFSP8_2_EHS_Msk (0x01UL << SCU_SFSP8_2_EHS_Pos) /*!< SCU SFSP8_2: EHS Mask */ -#define SCU_SFSP8_2_EZI_Pos 6 /*!< SCU SFSP8_2: EZI Position */ -#define SCU_SFSP8_2_EZI_Msk (0x01UL << SCU_SFSP8_2_EZI_Pos) /*!< SCU SFSP8_2: EZI Mask */ -#define SCU_SFSP8_2_EHD_Pos 8 /*!< SCU SFSP8_2: EHD Position */ -#define SCU_SFSP8_2_EHD_Msk (0x03UL << SCU_SFSP8_2_EHD_Pos) /*!< SCU SFSP8_2: EHD Mask */ - -// --------------------------------------- SCU_SFSP8_3 ------------------------------------------ -#define SCU_SFSP8_3_MODE_Pos 0 /*!< SCU SFSP8_3: MODE Position */ -#define SCU_SFSP8_3_MODE_Msk (0x07UL << SCU_SFSP8_3_MODE_Pos) /*!< SCU SFSP8_3: MODE Mask */ -#define SCU_SFSP8_3_EPD_Pos 3 /*!< SCU SFSP8_3: EPD Position */ -#define SCU_SFSP8_3_EPD_Msk (0x01UL << SCU_SFSP8_3_EPD_Pos) /*!< SCU SFSP8_3: EPD Mask */ -#define SCU_SFSP8_3_EPUN_Pos 4 /*!< SCU SFSP8_3: EPUN Position */ -#define SCU_SFSP8_3_EPUN_Msk (0x01UL << SCU_SFSP8_3_EPUN_Pos) /*!< SCU SFSP8_3: EPUN Mask */ -#define SCU_SFSP8_3_EHS_Pos 5 /*!< SCU SFSP8_3: EHS Position */ -#define SCU_SFSP8_3_EHS_Msk (0x01UL << SCU_SFSP8_3_EHS_Pos) /*!< SCU SFSP8_3: EHS Mask */ -#define SCU_SFSP8_3_EZI_Pos 6 /*!< SCU SFSP8_3: EZI Position */ -#define SCU_SFSP8_3_EZI_Msk (0x01UL << SCU_SFSP8_3_EZI_Pos) /*!< SCU SFSP8_3: EZI Mask */ -#define SCU_SFSP8_3_EHD_Pos 8 /*!< SCU SFSP8_3: EHD Position */ -#define SCU_SFSP8_3_EHD_Msk (0x03UL << SCU_SFSP8_3_EHD_Pos) /*!< SCU SFSP8_3: EHD Mask */ - -// --------------------------------------- SCU_SFSP8_4 ------------------------------------------ -#define SCU_SFSP8_4_MODE_Pos 0 /*!< SCU SFSP8_4: MODE Position */ -#define SCU_SFSP8_4_MODE_Msk (0x07UL << SCU_SFSP8_4_MODE_Pos) /*!< SCU SFSP8_4: MODE Mask */ -#define SCU_SFSP8_4_EPD_Pos 3 /*!< SCU SFSP8_4: EPD Position */ -#define SCU_SFSP8_4_EPD_Msk (0x01UL << SCU_SFSP8_4_EPD_Pos) /*!< SCU SFSP8_4: EPD Mask */ -#define SCU_SFSP8_4_EPUN_Pos 4 /*!< SCU SFSP8_4: EPUN Position */ -#define SCU_SFSP8_4_EPUN_Msk (0x01UL << SCU_SFSP8_4_EPUN_Pos) /*!< SCU SFSP8_4: EPUN Mask */ -#define SCU_SFSP8_4_EHS_Pos 5 /*!< SCU SFSP8_4: EHS Position */ -#define SCU_SFSP8_4_EHS_Msk (0x01UL << SCU_SFSP8_4_EHS_Pos) /*!< SCU SFSP8_4: EHS Mask */ -#define SCU_SFSP8_4_EZI_Pos 6 /*!< SCU SFSP8_4: EZI Position */ -#define SCU_SFSP8_4_EZI_Msk (0x01UL << SCU_SFSP8_4_EZI_Pos) /*!< SCU SFSP8_4: EZI Mask */ -#define SCU_SFSP8_4_EHD_Pos 8 /*!< SCU SFSP8_4: EHD Position */ -#define SCU_SFSP8_4_EHD_Msk (0x03UL << SCU_SFSP8_4_EHD_Pos) /*!< SCU SFSP8_4: EHD Mask */ - -// --------------------------------------- SCU_SFSP8_5 ------------------------------------------ -#define SCU_SFSP8_5_MODE_Pos 0 /*!< SCU SFSP8_5: MODE Position */ -#define SCU_SFSP8_5_MODE_Msk (0x07UL << SCU_SFSP8_5_MODE_Pos) /*!< SCU SFSP8_5: MODE Mask */ -#define SCU_SFSP8_5_EPD_Pos 3 /*!< SCU SFSP8_5: EPD Position */ -#define SCU_SFSP8_5_EPD_Msk (0x01UL << SCU_SFSP8_5_EPD_Pos) /*!< SCU SFSP8_5: EPD Mask */ -#define SCU_SFSP8_5_EPUN_Pos 4 /*!< SCU SFSP8_5: EPUN Position */ -#define SCU_SFSP8_5_EPUN_Msk (0x01UL << SCU_SFSP8_5_EPUN_Pos) /*!< SCU SFSP8_5: EPUN Mask */ -#define SCU_SFSP8_5_EHS_Pos 5 /*!< SCU SFSP8_5: EHS Position */ -#define SCU_SFSP8_5_EHS_Msk (0x01UL << SCU_SFSP8_5_EHS_Pos) /*!< SCU SFSP8_5: EHS Mask */ -#define SCU_SFSP8_5_EZI_Pos 6 /*!< SCU SFSP8_5: EZI Position */ -#define SCU_SFSP8_5_EZI_Msk (0x01UL << SCU_SFSP8_5_EZI_Pos) /*!< SCU SFSP8_5: EZI Mask */ -#define SCU_SFSP8_5_EHD_Pos 8 /*!< SCU SFSP8_5: EHD Position */ -#define SCU_SFSP8_5_EHD_Msk (0x03UL << SCU_SFSP8_5_EHD_Pos) /*!< SCU SFSP8_5: EHD Mask */ - -// --------------------------------------- SCU_SFSP8_6 ------------------------------------------ -#define SCU_SFSP8_6_MODE_Pos 0 /*!< SCU SFSP8_6: MODE Position */ -#define SCU_SFSP8_6_MODE_Msk (0x07UL << SCU_SFSP8_6_MODE_Pos) /*!< SCU SFSP8_6: MODE Mask */ -#define SCU_SFSP8_6_EPD_Pos 3 /*!< SCU SFSP8_6: EPD Position */ -#define SCU_SFSP8_6_EPD_Msk (0x01UL << SCU_SFSP8_6_EPD_Pos) /*!< SCU SFSP8_6: EPD Mask */ -#define SCU_SFSP8_6_EPUN_Pos 4 /*!< SCU SFSP8_6: EPUN Position */ -#define SCU_SFSP8_6_EPUN_Msk (0x01UL << SCU_SFSP8_6_EPUN_Pos) /*!< SCU SFSP8_6: EPUN Mask */ -#define SCU_SFSP8_6_EHS_Pos 5 /*!< SCU SFSP8_6: EHS Position */ -#define SCU_SFSP8_6_EHS_Msk (0x01UL << SCU_SFSP8_6_EHS_Pos) /*!< SCU SFSP8_6: EHS Mask */ -#define SCU_SFSP8_6_EZI_Pos 6 /*!< SCU SFSP8_6: EZI Position */ -#define SCU_SFSP8_6_EZI_Msk (0x01UL << SCU_SFSP8_6_EZI_Pos) /*!< SCU SFSP8_6: EZI Mask */ -#define SCU_SFSP8_6_EHD_Pos 8 /*!< SCU SFSP8_6: EHD Position */ -#define SCU_SFSP8_6_EHD_Msk (0x03UL << SCU_SFSP8_6_EHD_Pos) /*!< SCU SFSP8_6: EHD Mask */ - -// --------------------------------------- SCU_SFSP8_7 ------------------------------------------ -#define SCU_SFSP8_7_MODE_Pos 0 /*!< SCU SFSP8_7: MODE Position */ -#define SCU_SFSP8_7_MODE_Msk (0x07UL << SCU_SFSP8_7_MODE_Pos) /*!< SCU SFSP8_7: MODE Mask */ -#define SCU_SFSP8_7_EPD_Pos 3 /*!< SCU SFSP8_7: EPD Position */ -#define SCU_SFSP8_7_EPD_Msk (0x01UL << SCU_SFSP8_7_EPD_Pos) /*!< SCU SFSP8_7: EPD Mask */ -#define SCU_SFSP8_7_EPUN_Pos 4 /*!< SCU SFSP8_7: EPUN Position */ -#define SCU_SFSP8_7_EPUN_Msk (0x01UL << SCU_SFSP8_7_EPUN_Pos) /*!< SCU SFSP8_7: EPUN Mask */ -#define SCU_SFSP8_7_EHS_Pos 5 /*!< SCU SFSP8_7: EHS Position */ -#define SCU_SFSP8_7_EHS_Msk (0x01UL << SCU_SFSP8_7_EHS_Pos) /*!< SCU SFSP8_7: EHS Mask */ -#define SCU_SFSP8_7_EZI_Pos 6 /*!< SCU SFSP8_7: EZI Position */ -#define SCU_SFSP8_7_EZI_Msk (0x01UL << SCU_SFSP8_7_EZI_Pos) /*!< SCU SFSP8_7: EZI Mask */ -#define SCU_SFSP8_7_EHD_Pos 8 /*!< SCU SFSP8_7: EHD Position */ -#define SCU_SFSP8_7_EHD_Msk (0x03UL << SCU_SFSP8_7_EHD_Pos) /*!< SCU SFSP8_7: EHD Mask */ - -// --------------------------------------- SCU_SFSP8_8 ------------------------------------------ -#define SCU_SFSP8_8_MODE_Pos 0 /*!< SCU SFSP8_8: MODE Position */ -#define SCU_SFSP8_8_MODE_Msk (0x07UL << SCU_SFSP8_8_MODE_Pos) /*!< SCU SFSP8_8: MODE Mask */ -#define SCU_SFSP8_8_EPD_Pos 3 /*!< SCU SFSP8_8: EPD Position */ -#define SCU_SFSP8_8_EPD_Msk (0x01UL << SCU_SFSP8_8_EPD_Pos) /*!< SCU SFSP8_8: EPD Mask */ -#define SCU_SFSP8_8_EPUN_Pos 4 /*!< SCU SFSP8_8: EPUN Position */ -#define SCU_SFSP8_8_EPUN_Msk (0x01UL << SCU_SFSP8_8_EPUN_Pos) /*!< SCU SFSP8_8: EPUN Mask */ -#define SCU_SFSP8_8_EHS_Pos 5 /*!< SCU SFSP8_8: EHS Position */ -#define SCU_SFSP8_8_EHS_Msk (0x01UL << SCU_SFSP8_8_EHS_Pos) /*!< SCU SFSP8_8: EHS Mask */ -#define SCU_SFSP8_8_EZI_Pos 6 /*!< SCU SFSP8_8: EZI Position */ -#define SCU_SFSP8_8_EZI_Msk (0x01UL << SCU_SFSP8_8_EZI_Pos) /*!< SCU SFSP8_8: EZI Mask */ -#define SCU_SFSP8_8_EHD_Pos 8 /*!< SCU SFSP8_8: EHD Position */ -#define SCU_SFSP8_8_EHD_Msk (0x03UL << SCU_SFSP8_8_EHD_Pos) /*!< SCU SFSP8_8: EHD Mask */ - -// --------------------------------------- SCU_SFSP9_0 ------------------------------------------ -#define SCU_SFSP9_0_MODE_Pos 0 /*!< SCU SFSP9_0: MODE Position */ -#define SCU_SFSP9_0_MODE_Msk (0x07UL << SCU_SFSP9_0_MODE_Pos) /*!< SCU SFSP9_0: MODE Mask */ -#define SCU_SFSP9_0_EPD_Pos 3 /*!< SCU SFSP9_0: EPD Position */ -#define SCU_SFSP9_0_EPD_Msk (0x01UL << SCU_SFSP9_0_EPD_Pos) /*!< SCU SFSP9_0: EPD Mask */ -#define SCU_SFSP9_0_EPUN_Pos 4 /*!< SCU SFSP9_0: EPUN Position */ -#define SCU_SFSP9_0_EPUN_Msk (0x01UL << SCU_SFSP9_0_EPUN_Pos) /*!< SCU SFSP9_0: EPUN Mask */ -#define SCU_SFSP9_0_EHS_Pos 5 /*!< SCU SFSP9_0: EHS Position */ -#define SCU_SFSP9_0_EHS_Msk (0x01UL << SCU_SFSP9_0_EHS_Pos) /*!< SCU SFSP9_0: EHS Mask */ -#define SCU_SFSP9_0_EZI_Pos 6 /*!< SCU SFSP9_0: EZI Position */ -#define SCU_SFSP9_0_EZI_Msk (0x01UL << SCU_SFSP9_0_EZI_Pos) /*!< SCU SFSP9_0: EZI Mask */ -#define SCU_SFSP9_0_EHD_Pos 8 /*!< SCU SFSP9_0: EHD Position */ -#define SCU_SFSP9_0_EHD_Msk (0x03UL << SCU_SFSP9_0_EHD_Pos) /*!< SCU SFSP9_0: EHD Mask */ - -// --------------------------------------- SCU_SFSP9_1 ------------------------------------------ -#define SCU_SFSP9_1_MODE_Pos 0 /*!< SCU SFSP9_1: MODE Position */ -#define SCU_SFSP9_1_MODE_Msk (0x07UL << SCU_SFSP9_1_MODE_Pos) /*!< SCU SFSP9_1: MODE Mask */ -#define SCU_SFSP9_1_EPD_Pos 3 /*!< SCU SFSP9_1: EPD Position */ -#define SCU_SFSP9_1_EPD_Msk (0x01UL << SCU_SFSP9_1_EPD_Pos) /*!< SCU SFSP9_1: EPD Mask */ -#define SCU_SFSP9_1_EPUN_Pos 4 /*!< SCU SFSP9_1: EPUN Position */ -#define SCU_SFSP9_1_EPUN_Msk (0x01UL << SCU_SFSP9_1_EPUN_Pos) /*!< SCU SFSP9_1: EPUN Mask */ -#define SCU_SFSP9_1_EHS_Pos 5 /*!< SCU SFSP9_1: EHS Position */ -#define SCU_SFSP9_1_EHS_Msk (0x01UL << SCU_SFSP9_1_EHS_Pos) /*!< SCU SFSP9_1: EHS Mask */ -#define SCU_SFSP9_1_EZI_Pos 6 /*!< SCU SFSP9_1: EZI Position */ -#define SCU_SFSP9_1_EZI_Msk (0x01UL << SCU_SFSP9_1_EZI_Pos) /*!< SCU SFSP9_1: EZI Mask */ -#define SCU_SFSP9_1_EHD_Pos 8 /*!< SCU SFSP9_1: EHD Position */ -#define SCU_SFSP9_1_EHD_Msk (0x03UL << SCU_SFSP9_1_EHD_Pos) /*!< SCU SFSP9_1: EHD Mask */ - -// --------------------------------------- SCU_SFSP9_2 ------------------------------------------ -#define SCU_SFSP9_2_MODE_Pos 0 /*!< SCU SFSP9_2: MODE Position */ -#define SCU_SFSP9_2_MODE_Msk (0x07UL << SCU_SFSP9_2_MODE_Pos) /*!< SCU SFSP9_2: MODE Mask */ -#define SCU_SFSP9_2_EPD_Pos 3 /*!< SCU SFSP9_2: EPD Position */ -#define SCU_SFSP9_2_EPD_Msk (0x01UL << SCU_SFSP9_2_EPD_Pos) /*!< SCU SFSP9_2: EPD Mask */ -#define SCU_SFSP9_2_EPUN_Pos 4 /*!< SCU SFSP9_2: EPUN Position */ -#define SCU_SFSP9_2_EPUN_Msk (0x01UL << SCU_SFSP9_2_EPUN_Pos) /*!< SCU SFSP9_2: EPUN Mask */ -#define SCU_SFSP9_2_EHS_Pos 5 /*!< SCU SFSP9_2: EHS Position */ -#define SCU_SFSP9_2_EHS_Msk (0x01UL << SCU_SFSP9_2_EHS_Pos) /*!< SCU SFSP9_2: EHS Mask */ -#define SCU_SFSP9_2_EZI_Pos 6 /*!< SCU SFSP9_2: EZI Position */ -#define SCU_SFSP9_2_EZI_Msk (0x01UL << SCU_SFSP9_2_EZI_Pos) /*!< SCU SFSP9_2: EZI Mask */ -#define SCU_SFSP9_2_EHD_Pos 8 /*!< SCU SFSP9_2: EHD Position */ -#define SCU_SFSP9_2_EHD_Msk (0x03UL << SCU_SFSP9_2_EHD_Pos) /*!< SCU SFSP9_2: EHD Mask */ - -// --------------------------------------- SCU_SFSP9_3 ------------------------------------------ -#define SCU_SFSP9_3_MODE_Pos 0 /*!< SCU SFSP9_3: MODE Position */ -#define SCU_SFSP9_3_MODE_Msk (0x07UL << SCU_SFSP9_3_MODE_Pos) /*!< SCU SFSP9_3: MODE Mask */ -#define SCU_SFSP9_3_EPD_Pos 3 /*!< SCU SFSP9_3: EPD Position */ -#define SCU_SFSP9_3_EPD_Msk (0x01UL << SCU_SFSP9_3_EPD_Pos) /*!< SCU SFSP9_3: EPD Mask */ -#define SCU_SFSP9_3_EPUN_Pos 4 /*!< SCU SFSP9_3: EPUN Position */ -#define SCU_SFSP9_3_EPUN_Msk (0x01UL << SCU_SFSP9_3_EPUN_Pos) /*!< SCU SFSP9_3: EPUN Mask */ -#define SCU_SFSP9_3_EHS_Pos 5 /*!< SCU SFSP9_3: EHS Position */ -#define SCU_SFSP9_3_EHS_Msk (0x01UL << SCU_SFSP9_3_EHS_Pos) /*!< SCU SFSP9_3: EHS Mask */ -#define SCU_SFSP9_3_EZI_Pos 6 /*!< SCU SFSP9_3: EZI Position */ -#define SCU_SFSP9_3_EZI_Msk (0x01UL << SCU_SFSP9_3_EZI_Pos) /*!< SCU SFSP9_3: EZI Mask */ -#define SCU_SFSP9_3_EHD_Pos 8 /*!< SCU SFSP9_3: EHD Position */ -#define SCU_SFSP9_3_EHD_Msk (0x03UL << SCU_SFSP9_3_EHD_Pos) /*!< SCU SFSP9_3: EHD Mask */ - -// --------------------------------------- SCU_SFSP9_4 ------------------------------------------ -#define SCU_SFSP9_4_MODE_Pos 0 /*!< SCU SFSP9_4: MODE Position */ -#define SCU_SFSP9_4_MODE_Msk (0x07UL << SCU_SFSP9_4_MODE_Pos) /*!< SCU SFSP9_4: MODE Mask */ -#define SCU_SFSP9_4_EPD_Pos 3 /*!< SCU SFSP9_4: EPD Position */ -#define SCU_SFSP9_4_EPD_Msk (0x01UL << SCU_SFSP9_4_EPD_Pos) /*!< SCU SFSP9_4: EPD Mask */ -#define SCU_SFSP9_4_EPUN_Pos 4 /*!< SCU SFSP9_4: EPUN Position */ -#define SCU_SFSP9_4_EPUN_Msk (0x01UL << SCU_SFSP9_4_EPUN_Pos) /*!< SCU SFSP9_4: EPUN Mask */ -#define SCU_SFSP9_4_EHS_Pos 5 /*!< SCU SFSP9_4: EHS Position */ -#define SCU_SFSP9_4_EHS_Msk (0x01UL << SCU_SFSP9_4_EHS_Pos) /*!< SCU SFSP9_4: EHS Mask */ -#define SCU_SFSP9_4_EZI_Pos 6 /*!< SCU SFSP9_4: EZI Position */ -#define SCU_SFSP9_4_EZI_Msk (0x01UL << SCU_SFSP9_4_EZI_Pos) /*!< SCU SFSP9_4: EZI Mask */ -#define SCU_SFSP9_4_EHD_Pos 8 /*!< SCU SFSP9_4: EHD Position */ -#define SCU_SFSP9_4_EHD_Msk (0x03UL << SCU_SFSP9_4_EHD_Pos) /*!< SCU SFSP9_4: EHD Mask */ - -// --------------------------------------- SCU_SFSP9_5 ------------------------------------------ -#define SCU_SFSP9_5_MODE_Pos 0 /*!< SCU SFSP9_5: MODE Position */ -#define SCU_SFSP9_5_MODE_Msk (0x07UL << SCU_SFSP9_5_MODE_Pos) /*!< SCU SFSP9_5: MODE Mask */ -#define SCU_SFSP9_5_EPD_Pos 3 /*!< SCU SFSP9_5: EPD Position */ -#define SCU_SFSP9_5_EPD_Msk (0x01UL << SCU_SFSP9_5_EPD_Pos) /*!< SCU SFSP9_5: EPD Mask */ -#define SCU_SFSP9_5_EPUN_Pos 4 /*!< SCU SFSP9_5: EPUN Position */ -#define SCU_SFSP9_5_EPUN_Msk (0x01UL << SCU_SFSP9_5_EPUN_Pos) /*!< SCU SFSP9_5: EPUN Mask */ -#define SCU_SFSP9_5_EHS_Pos 5 /*!< SCU SFSP9_5: EHS Position */ -#define SCU_SFSP9_5_EHS_Msk (0x01UL << SCU_SFSP9_5_EHS_Pos) /*!< SCU SFSP9_5: EHS Mask */ -#define SCU_SFSP9_5_EZI_Pos 6 /*!< SCU SFSP9_5: EZI Position */ -#define SCU_SFSP9_5_EZI_Msk (0x01UL << SCU_SFSP9_5_EZI_Pos) /*!< SCU SFSP9_5: EZI Mask */ -#define SCU_SFSP9_5_EHD_Pos 8 /*!< SCU SFSP9_5: EHD Position */ -#define SCU_SFSP9_5_EHD_Msk (0x03UL << SCU_SFSP9_5_EHD_Pos) /*!< SCU SFSP9_5: EHD Mask */ - -// --------------------------------------- SCU_SFSP9_6 ------------------------------------------ -#define SCU_SFSP9_6_MODE_Pos 0 /*!< SCU SFSP9_6: MODE Position */ -#define SCU_SFSP9_6_MODE_Msk (0x07UL << SCU_SFSP9_6_MODE_Pos) /*!< SCU SFSP9_6: MODE Mask */ -#define SCU_SFSP9_6_EPD_Pos 3 /*!< SCU SFSP9_6: EPD Position */ -#define SCU_SFSP9_6_EPD_Msk (0x01UL << SCU_SFSP9_6_EPD_Pos) /*!< SCU SFSP9_6: EPD Mask */ -#define SCU_SFSP9_6_EPUN_Pos 4 /*!< SCU SFSP9_6: EPUN Position */ -#define SCU_SFSP9_6_EPUN_Msk (0x01UL << SCU_SFSP9_6_EPUN_Pos) /*!< SCU SFSP9_6: EPUN Mask */ -#define SCU_SFSP9_6_EHS_Pos 5 /*!< SCU SFSP9_6: EHS Position */ -#define SCU_SFSP9_6_EHS_Msk (0x01UL << SCU_SFSP9_6_EHS_Pos) /*!< SCU SFSP9_6: EHS Mask */ -#define SCU_SFSP9_6_EZI_Pos 6 /*!< SCU SFSP9_6: EZI Position */ -#define SCU_SFSP9_6_EZI_Msk (0x01UL << SCU_SFSP9_6_EZI_Pos) /*!< SCU SFSP9_6: EZI Mask */ -#define SCU_SFSP9_6_EHD_Pos 8 /*!< SCU SFSP9_6: EHD Position */ -#define SCU_SFSP9_6_EHD_Msk (0x03UL << SCU_SFSP9_6_EHD_Pos) /*!< SCU SFSP9_6: EHD Mask */ - -// --------------------------------------- SCU_SFSPA_0 ------------------------------------------ -#define SCU_SFSPA_0_MODE_Pos 0 /*!< SCU SFSPA_0: MODE Position */ -#define SCU_SFSPA_0_MODE_Msk (0x07UL << SCU_SFSPA_0_MODE_Pos) /*!< SCU SFSPA_0: MODE Mask */ -#define SCU_SFSPA_0_EPD_Pos 3 /*!< SCU SFSPA_0: EPD Position */ -#define SCU_SFSPA_0_EPD_Msk (0x01UL << SCU_SFSPA_0_EPD_Pos) /*!< SCU SFSPA_0: EPD Mask */ -#define SCU_SFSPA_0_EPUN_Pos 4 /*!< SCU SFSPA_0: EPUN Position */ -#define SCU_SFSPA_0_EPUN_Msk (0x01UL << SCU_SFSPA_0_EPUN_Pos) /*!< SCU SFSPA_0: EPUN Mask */ -#define SCU_SFSPA_0_EHS_Pos 5 /*!< SCU SFSPA_0: EHS Position */ -#define SCU_SFSPA_0_EHS_Msk (0x01UL << SCU_SFSPA_0_EHS_Pos) /*!< SCU SFSPA_0: EHS Mask */ -#define SCU_SFSPA_0_EZI_Pos 6 /*!< SCU SFSPA_0: EZI Position */ -#define SCU_SFSPA_0_EZI_Msk (0x01UL << SCU_SFSPA_0_EZI_Pos) /*!< SCU SFSPA_0: EZI Mask */ -#define SCU_SFSPA_0_EHD_Pos 8 /*!< SCU SFSPA_0: EHD Position */ -#define SCU_SFSPA_0_EHD_Msk (0x03UL << SCU_SFSPA_0_EHD_Pos) /*!< SCU SFSPA_0: EHD Mask */ - -// --------------------------------------- SCU_SFSPA_1 ------------------------------------------ -#define SCU_SFSPA_1_MODE_Pos 0 /*!< SCU SFSPA_1: MODE Position */ -#define SCU_SFSPA_1_MODE_Msk (0x07UL << SCU_SFSPA_1_MODE_Pos) /*!< SCU SFSPA_1: MODE Mask */ -#define SCU_SFSPA_1_EPD_Pos 3 /*!< SCU SFSPA_1: EPD Position */ -#define SCU_SFSPA_1_EPD_Msk (0x01UL << SCU_SFSPA_1_EPD_Pos) /*!< SCU SFSPA_1: EPD Mask */ -#define SCU_SFSPA_1_EPUN_Pos 4 /*!< SCU SFSPA_1: EPUN Position */ -#define SCU_SFSPA_1_EPUN_Msk (0x01UL << SCU_SFSPA_1_EPUN_Pos) /*!< SCU SFSPA_1: EPUN Mask */ -#define SCU_SFSPA_1_EHS_Pos 5 /*!< SCU SFSPA_1: EHS Position */ -#define SCU_SFSPA_1_EHS_Msk (0x01UL << SCU_SFSPA_1_EHS_Pos) /*!< SCU SFSPA_1: EHS Mask */ -#define SCU_SFSPA_1_EZI_Pos 6 /*!< SCU SFSPA_1: EZI Position */ -#define SCU_SFSPA_1_EZI_Msk (0x01UL << SCU_SFSPA_1_EZI_Pos) /*!< SCU SFSPA_1: EZI Mask */ -#define SCU_SFSPA_1_EHD_Pos 8 /*!< SCU SFSPA_1: EHD Position */ -#define SCU_SFSPA_1_EHD_Msk (0x03UL << SCU_SFSPA_1_EHD_Pos) /*!< SCU SFSPA_1: EHD Mask */ - -// --------------------------------------- SCU_SFSPA_2 ------------------------------------------ -#define SCU_SFSPA_2_MODE_Pos 0 /*!< SCU SFSPA_2: MODE Position */ -#define SCU_SFSPA_2_MODE_Msk (0x07UL << SCU_SFSPA_2_MODE_Pos) /*!< SCU SFSPA_2: MODE Mask */ -#define SCU_SFSPA_2_EPD_Pos 3 /*!< SCU SFSPA_2: EPD Position */ -#define SCU_SFSPA_2_EPD_Msk (0x01UL << SCU_SFSPA_2_EPD_Pos) /*!< SCU SFSPA_2: EPD Mask */ -#define SCU_SFSPA_2_EPUN_Pos 4 /*!< SCU SFSPA_2: EPUN Position */ -#define SCU_SFSPA_2_EPUN_Msk (0x01UL << SCU_SFSPA_2_EPUN_Pos) /*!< SCU SFSPA_2: EPUN Mask */ -#define SCU_SFSPA_2_EHS_Pos 5 /*!< SCU SFSPA_2: EHS Position */ -#define SCU_SFSPA_2_EHS_Msk (0x01UL << SCU_SFSPA_2_EHS_Pos) /*!< SCU SFSPA_2: EHS Mask */ -#define SCU_SFSPA_2_EZI_Pos 6 /*!< SCU SFSPA_2: EZI Position */ -#define SCU_SFSPA_2_EZI_Msk (0x01UL << SCU_SFSPA_2_EZI_Pos) /*!< SCU SFSPA_2: EZI Mask */ -#define SCU_SFSPA_2_EHD_Pos 8 /*!< SCU SFSPA_2: EHD Position */ -#define SCU_SFSPA_2_EHD_Msk (0x03UL << SCU_SFSPA_2_EHD_Pos) /*!< SCU SFSPA_2: EHD Mask */ - -// --------------------------------------- SCU_SFSPA_3 ------------------------------------------ -#define SCU_SFSPA_3_MODE_Pos 0 /*!< SCU SFSPA_3: MODE Position */ -#define SCU_SFSPA_3_MODE_Msk (0x07UL << SCU_SFSPA_3_MODE_Pos) /*!< SCU SFSPA_3: MODE Mask */ -#define SCU_SFSPA_3_EPD_Pos 3 /*!< SCU SFSPA_3: EPD Position */ -#define SCU_SFSPA_3_EPD_Msk (0x01UL << SCU_SFSPA_3_EPD_Pos) /*!< SCU SFSPA_3: EPD Mask */ -#define SCU_SFSPA_3_EPUN_Pos 4 /*!< SCU SFSPA_3: EPUN Position */ -#define SCU_SFSPA_3_EPUN_Msk (0x01UL << SCU_SFSPA_3_EPUN_Pos) /*!< SCU SFSPA_3: EPUN Mask */ -#define SCU_SFSPA_3_EHS_Pos 5 /*!< SCU SFSPA_3: EHS Position */ -#define SCU_SFSPA_3_EHS_Msk (0x01UL << SCU_SFSPA_3_EHS_Pos) /*!< SCU SFSPA_3: EHS Mask */ -#define SCU_SFSPA_3_EZI_Pos 6 /*!< SCU SFSPA_3: EZI Position */ -#define SCU_SFSPA_3_EZI_Msk (0x01UL << SCU_SFSPA_3_EZI_Pos) /*!< SCU SFSPA_3: EZI Mask */ -#define SCU_SFSPA_3_EHD_Pos 8 /*!< SCU SFSPA_3: EHD Position */ -#define SCU_SFSPA_3_EHD_Msk (0x03UL << SCU_SFSPA_3_EHD_Pos) /*!< SCU SFSPA_3: EHD Mask */ - -// --------------------------------------- SCU_SFSPA_4 ------------------------------------------ -#define SCU_SFSPA_4_MODE_Pos 0 /*!< SCU SFSPA_4: MODE Position */ -#define SCU_SFSPA_4_MODE_Msk (0x07UL << SCU_SFSPA_4_MODE_Pos) /*!< SCU SFSPA_4: MODE Mask */ -#define SCU_SFSPA_4_EPD_Pos 3 /*!< SCU SFSPA_4: EPD Position */ -#define SCU_SFSPA_4_EPD_Msk (0x01UL << SCU_SFSPA_4_EPD_Pos) /*!< SCU SFSPA_4: EPD Mask */ -#define SCU_SFSPA_4_EPUN_Pos 4 /*!< SCU SFSPA_4: EPUN Position */ -#define SCU_SFSPA_4_EPUN_Msk (0x01UL << SCU_SFSPA_4_EPUN_Pos) /*!< SCU SFSPA_4: EPUN Mask */ -#define SCU_SFSPA_4_EHS_Pos 5 /*!< SCU SFSPA_4: EHS Position */ -#define SCU_SFSPA_4_EHS_Msk (0x01UL << SCU_SFSPA_4_EHS_Pos) /*!< SCU SFSPA_4: EHS Mask */ -#define SCU_SFSPA_4_EZI_Pos 6 /*!< SCU SFSPA_4: EZI Position */ -#define SCU_SFSPA_4_EZI_Msk (0x01UL << SCU_SFSPA_4_EZI_Pos) /*!< SCU SFSPA_4: EZI Mask */ -#define SCU_SFSPA_4_EHD_Pos 8 /*!< SCU SFSPA_4: EHD Position */ -#define SCU_SFSPA_4_EHD_Msk (0x03UL << SCU_SFSPA_4_EHD_Pos) /*!< SCU SFSPA_4: EHD Mask */ - -// --------------------------------------- SCU_SFSPB_0 ------------------------------------------ -#define SCU_SFSPB_0_MODE_Pos 0 /*!< SCU SFSPB_0: MODE Position */ -#define SCU_SFSPB_0_MODE_Msk (0x07UL << SCU_SFSPB_0_MODE_Pos) /*!< SCU SFSPB_0: MODE Mask */ -#define SCU_SFSPB_0_EPD_Pos 3 /*!< SCU SFSPB_0: EPD Position */ -#define SCU_SFSPB_0_EPD_Msk (0x01UL << SCU_SFSPB_0_EPD_Pos) /*!< SCU SFSPB_0: EPD Mask */ -#define SCU_SFSPB_0_EPUN_Pos 4 /*!< SCU SFSPB_0: EPUN Position */ -#define SCU_SFSPB_0_EPUN_Msk (0x01UL << SCU_SFSPB_0_EPUN_Pos) /*!< SCU SFSPB_0: EPUN Mask */ -#define SCU_SFSPB_0_EHS_Pos 5 /*!< SCU SFSPB_0: EHS Position */ -#define SCU_SFSPB_0_EHS_Msk (0x01UL << SCU_SFSPB_0_EHS_Pos) /*!< SCU SFSPB_0: EHS Mask */ -#define SCU_SFSPB_0_EZI_Pos 6 /*!< SCU SFSPB_0: EZI Position */ -#define SCU_SFSPB_0_EZI_Msk (0x01UL << SCU_SFSPB_0_EZI_Pos) /*!< SCU SFSPB_0: EZI Mask */ -#define SCU_SFSPB_0_EHD_Pos 8 /*!< SCU SFSPB_0: EHD Position */ -#define SCU_SFSPB_0_EHD_Msk (0x03UL << SCU_SFSPB_0_EHD_Pos) /*!< SCU SFSPB_0: EHD Mask */ - -// --------------------------------------- SCU_SFSPB_1 ------------------------------------------ -#define SCU_SFSPB_1_MODE_Pos 0 /*!< SCU SFSPB_1: MODE Position */ -#define SCU_SFSPB_1_MODE_Msk (0x07UL << SCU_SFSPB_1_MODE_Pos) /*!< SCU SFSPB_1: MODE Mask */ -#define SCU_SFSPB_1_EPD_Pos 3 /*!< SCU SFSPB_1: EPD Position */ -#define SCU_SFSPB_1_EPD_Msk (0x01UL << SCU_SFSPB_1_EPD_Pos) /*!< SCU SFSPB_1: EPD Mask */ -#define SCU_SFSPB_1_EPUN_Pos 4 /*!< SCU SFSPB_1: EPUN Position */ -#define SCU_SFSPB_1_EPUN_Msk (0x01UL << SCU_SFSPB_1_EPUN_Pos) /*!< SCU SFSPB_1: EPUN Mask */ -#define SCU_SFSPB_1_EHS_Pos 5 /*!< SCU SFSPB_1: EHS Position */ -#define SCU_SFSPB_1_EHS_Msk (0x01UL << SCU_SFSPB_1_EHS_Pos) /*!< SCU SFSPB_1: EHS Mask */ -#define SCU_SFSPB_1_EZI_Pos 6 /*!< SCU SFSPB_1: EZI Position */ -#define SCU_SFSPB_1_EZI_Msk (0x01UL << SCU_SFSPB_1_EZI_Pos) /*!< SCU SFSPB_1: EZI Mask */ -#define SCU_SFSPB_1_EHD_Pos 8 /*!< SCU SFSPB_1: EHD Position */ -#define SCU_SFSPB_1_EHD_Msk (0x03UL << SCU_SFSPB_1_EHD_Pos) /*!< SCU SFSPB_1: EHD Mask */ - -// --------------------------------------- SCU_SFSPB_2 ------------------------------------------ -#define SCU_SFSPB_2_MODE_Pos 0 /*!< SCU SFSPB_2: MODE Position */ -#define SCU_SFSPB_2_MODE_Msk (0x07UL << SCU_SFSPB_2_MODE_Pos) /*!< SCU SFSPB_2: MODE Mask */ -#define SCU_SFSPB_2_EPD_Pos 3 /*!< SCU SFSPB_2: EPD Position */ -#define SCU_SFSPB_2_EPD_Msk (0x01UL << SCU_SFSPB_2_EPD_Pos) /*!< SCU SFSPB_2: EPD Mask */ -#define SCU_SFSPB_2_EPUN_Pos 4 /*!< SCU SFSPB_2: EPUN Position */ -#define SCU_SFSPB_2_EPUN_Msk (0x01UL << SCU_SFSPB_2_EPUN_Pos) /*!< SCU SFSPB_2: EPUN Mask */ -#define SCU_SFSPB_2_EHS_Pos 5 /*!< SCU SFSPB_2: EHS Position */ -#define SCU_SFSPB_2_EHS_Msk (0x01UL << SCU_SFSPB_2_EHS_Pos) /*!< SCU SFSPB_2: EHS Mask */ -#define SCU_SFSPB_2_EZI_Pos 6 /*!< SCU SFSPB_2: EZI Position */ -#define SCU_SFSPB_2_EZI_Msk (0x01UL << SCU_SFSPB_2_EZI_Pos) /*!< SCU SFSPB_2: EZI Mask */ -#define SCU_SFSPB_2_EHD_Pos 8 /*!< SCU SFSPB_2: EHD Position */ -#define SCU_SFSPB_2_EHD_Msk (0x03UL << SCU_SFSPB_2_EHD_Pos) /*!< SCU SFSPB_2: EHD Mask */ - -// --------------------------------------- SCU_SFSPB_3 ------------------------------------------ -#define SCU_SFSPB_3_MODE_Pos 0 /*!< SCU SFSPB_3: MODE Position */ -#define SCU_SFSPB_3_MODE_Msk (0x07UL << SCU_SFSPB_3_MODE_Pos) /*!< SCU SFSPB_3: MODE Mask */ -#define SCU_SFSPB_3_EPD_Pos 3 /*!< SCU SFSPB_3: EPD Position */ -#define SCU_SFSPB_3_EPD_Msk (0x01UL << SCU_SFSPB_3_EPD_Pos) /*!< SCU SFSPB_3: EPD Mask */ -#define SCU_SFSPB_3_EPUN_Pos 4 /*!< SCU SFSPB_3: EPUN Position */ -#define SCU_SFSPB_3_EPUN_Msk (0x01UL << SCU_SFSPB_3_EPUN_Pos) /*!< SCU SFSPB_3: EPUN Mask */ -#define SCU_SFSPB_3_EHS_Pos 5 /*!< SCU SFSPB_3: EHS Position */ -#define SCU_SFSPB_3_EHS_Msk (0x01UL << SCU_SFSPB_3_EHS_Pos) /*!< SCU SFSPB_3: EHS Mask */ -#define SCU_SFSPB_3_EZI_Pos 6 /*!< SCU SFSPB_3: EZI Position */ -#define SCU_SFSPB_3_EZI_Msk (0x01UL << SCU_SFSPB_3_EZI_Pos) /*!< SCU SFSPB_3: EZI Mask */ -#define SCU_SFSPB_3_EHD_Pos 8 /*!< SCU SFSPB_3: EHD Position */ -#define SCU_SFSPB_3_EHD_Msk (0x03UL << SCU_SFSPB_3_EHD_Pos) /*!< SCU SFSPB_3: EHD Mask */ - -// --------------------------------------- SCU_SFSPB_4 ------------------------------------------ -#define SCU_SFSPB_4_MODE_Pos 0 /*!< SCU SFSPB_4: MODE Position */ -#define SCU_SFSPB_4_MODE_Msk (0x07UL << SCU_SFSPB_4_MODE_Pos) /*!< SCU SFSPB_4: MODE Mask */ -#define SCU_SFSPB_4_EPD_Pos 3 /*!< SCU SFSPB_4: EPD Position */ -#define SCU_SFSPB_4_EPD_Msk (0x01UL << SCU_SFSPB_4_EPD_Pos) /*!< SCU SFSPB_4: EPD Mask */ -#define SCU_SFSPB_4_EPUN_Pos 4 /*!< SCU SFSPB_4: EPUN Position */ -#define SCU_SFSPB_4_EPUN_Msk (0x01UL << SCU_SFSPB_4_EPUN_Pos) /*!< SCU SFSPB_4: EPUN Mask */ -#define SCU_SFSPB_4_EHS_Pos 5 /*!< SCU SFSPB_4: EHS Position */ -#define SCU_SFSPB_4_EHS_Msk (0x01UL << SCU_SFSPB_4_EHS_Pos) /*!< SCU SFSPB_4: EHS Mask */ -#define SCU_SFSPB_4_EZI_Pos 6 /*!< SCU SFSPB_4: EZI Position */ -#define SCU_SFSPB_4_EZI_Msk (0x01UL << SCU_SFSPB_4_EZI_Pos) /*!< SCU SFSPB_4: EZI Mask */ -#define SCU_SFSPB_4_EHD_Pos 8 /*!< SCU SFSPB_4: EHD Position */ -#define SCU_SFSPB_4_EHD_Msk (0x03UL << SCU_SFSPB_4_EHD_Pos) /*!< SCU SFSPB_4: EHD Mask */ - -// --------------------------------------- SCU_SFSPB_5 ------------------------------------------ -#define SCU_SFSPB_5_MODE_Pos 0 /*!< SCU SFSPB_5: MODE Position */ -#define SCU_SFSPB_5_MODE_Msk (0x07UL << SCU_SFSPB_5_MODE_Pos) /*!< SCU SFSPB_5: MODE Mask */ -#define SCU_SFSPB_5_EPD_Pos 3 /*!< SCU SFSPB_5: EPD Position */ -#define SCU_SFSPB_5_EPD_Msk (0x01UL << SCU_SFSPB_5_EPD_Pos) /*!< SCU SFSPB_5: EPD Mask */ -#define SCU_SFSPB_5_EPUN_Pos 4 /*!< SCU SFSPB_5: EPUN Position */ -#define SCU_SFSPB_5_EPUN_Msk (0x01UL << SCU_SFSPB_5_EPUN_Pos) /*!< SCU SFSPB_5: EPUN Mask */ -#define SCU_SFSPB_5_EHS_Pos 5 /*!< SCU SFSPB_5: EHS Position */ -#define SCU_SFSPB_5_EHS_Msk (0x01UL << SCU_SFSPB_5_EHS_Pos) /*!< SCU SFSPB_5: EHS Mask */ -#define SCU_SFSPB_5_EZI_Pos 6 /*!< SCU SFSPB_5: EZI Position */ -#define SCU_SFSPB_5_EZI_Msk (0x01UL << SCU_SFSPB_5_EZI_Pos) /*!< SCU SFSPB_5: EZI Mask */ -#define SCU_SFSPB_5_EHD_Pos 8 /*!< SCU SFSPB_5: EHD Position */ -#define SCU_SFSPB_5_EHD_Msk (0x03UL << SCU_SFSPB_5_EHD_Pos) /*!< SCU SFSPB_5: EHD Mask */ - -// --------------------------------------- SCU_SFSPB_6 ------------------------------------------ -#define SCU_SFSPB_6_MODE_Pos 0 /*!< SCU SFSPB_6: MODE Position */ -#define SCU_SFSPB_6_MODE_Msk (0x07UL << SCU_SFSPB_6_MODE_Pos) /*!< SCU SFSPB_6: MODE Mask */ -#define SCU_SFSPB_6_EPD_Pos 3 /*!< SCU SFSPB_6: EPD Position */ -#define SCU_SFSPB_6_EPD_Msk (0x01UL << SCU_SFSPB_6_EPD_Pos) /*!< SCU SFSPB_6: EPD Mask */ -#define SCU_SFSPB_6_EPUN_Pos 4 /*!< SCU SFSPB_6: EPUN Position */ -#define SCU_SFSPB_6_EPUN_Msk (0x01UL << SCU_SFSPB_6_EPUN_Pos) /*!< SCU SFSPB_6: EPUN Mask */ -#define SCU_SFSPB_6_EHS_Pos 5 /*!< SCU SFSPB_6: EHS Position */ -#define SCU_SFSPB_6_EHS_Msk (0x01UL << SCU_SFSPB_6_EHS_Pos) /*!< SCU SFSPB_6: EHS Mask */ -#define SCU_SFSPB_6_EZI_Pos 6 /*!< SCU SFSPB_6: EZI Position */ -#define SCU_SFSPB_6_EZI_Msk (0x01UL << SCU_SFSPB_6_EZI_Pos) /*!< SCU SFSPB_6: EZI Mask */ -#define SCU_SFSPB_6_EHD_Pos 8 /*!< SCU SFSPB_6: EHD Position */ -#define SCU_SFSPB_6_EHD_Msk (0x03UL << SCU_SFSPB_6_EHD_Pos) /*!< SCU SFSPB_6: EHD Mask */ - -// --------------------------------------- SCU_SFSPC_0 ------------------------------------------ -#define SCU_SFSPC_0_MODE_Pos 0 /*!< SCU SFSPC_0: MODE Position */ -#define SCU_SFSPC_0_MODE_Msk (0x07UL << SCU_SFSPC_0_MODE_Pos) /*!< SCU SFSPC_0: MODE Mask */ -#define SCU_SFSPC_0_EPD_Pos 3 /*!< SCU SFSPC_0: EPD Position */ -#define SCU_SFSPC_0_EPD_Msk (0x01UL << SCU_SFSPC_0_EPD_Pos) /*!< SCU SFSPC_0: EPD Mask */ -#define SCU_SFSPC_0_EPUN_Pos 4 /*!< SCU SFSPC_0: EPUN Position */ -#define SCU_SFSPC_0_EPUN_Msk (0x01UL << SCU_SFSPC_0_EPUN_Pos) /*!< SCU SFSPC_0: EPUN Mask */ -#define SCU_SFSPC_0_EHS_Pos 5 /*!< SCU SFSPC_0: EHS Position */ -#define SCU_SFSPC_0_EHS_Msk (0x01UL << SCU_SFSPC_0_EHS_Pos) /*!< SCU SFSPC_0: EHS Mask */ -#define SCU_SFSPC_0_EZI_Pos 6 /*!< SCU SFSPC_0: EZI Position */ -#define SCU_SFSPC_0_EZI_Msk (0x01UL << SCU_SFSPC_0_EZI_Pos) /*!< SCU SFSPC_0: EZI Mask */ -#define SCU_SFSPC_0_EHD_Pos 8 /*!< SCU SFSPC_0: EHD Position */ -#define SCU_SFSPC_0_EHD_Msk (0x03UL << SCU_SFSPC_0_EHD_Pos) /*!< SCU SFSPC_0: EHD Mask */ - -// --------------------------------------- SCU_SFSPC_1 ------------------------------------------ -#define SCU_SFSPC_1_MODE_Pos 0 /*!< SCU SFSPC_1: MODE Position */ -#define SCU_SFSPC_1_MODE_Msk (0x07UL << SCU_SFSPC_1_MODE_Pos) /*!< SCU SFSPC_1: MODE Mask */ -#define SCU_SFSPC_1_EPD_Pos 3 /*!< SCU SFSPC_1: EPD Position */ -#define SCU_SFSPC_1_EPD_Msk (0x01UL << SCU_SFSPC_1_EPD_Pos) /*!< SCU SFSPC_1: EPD Mask */ -#define SCU_SFSPC_1_EPUN_Pos 4 /*!< SCU SFSPC_1: EPUN Position */ -#define SCU_SFSPC_1_EPUN_Msk (0x01UL << SCU_SFSPC_1_EPUN_Pos) /*!< SCU SFSPC_1: EPUN Mask */ -#define SCU_SFSPC_1_EHS_Pos 5 /*!< SCU SFSPC_1: EHS Position */ -#define SCU_SFSPC_1_EHS_Msk (0x01UL << SCU_SFSPC_1_EHS_Pos) /*!< SCU SFSPC_1: EHS Mask */ -#define SCU_SFSPC_1_EZI_Pos 6 /*!< SCU SFSPC_1: EZI Position */ -#define SCU_SFSPC_1_EZI_Msk (0x01UL << SCU_SFSPC_1_EZI_Pos) /*!< SCU SFSPC_1: EZI Mask */ -#define SCU_SFSPC_1_EHD_Pos 8 /*!< SCU SFSPC_1: EHD Position */ -#define SCU_SFSPC_1_EHD_Msk (0x03UL << SCU_SFSPC_1_EHD_Pos) /*!< SCU SFSPC_1: EHD Mask */ - -// --------------------------------------- SCU_SFSPC_2 ------------------------------------------ -#define SCU_SFSPC_2_MODE_Pos 0 /*!< SCU SFSPC_2: MODE Position */ -#define SCU_SFSPC_2_MODE_Msk (0x07UL << SCU_SFSPC_2_MODE_Pos) /*!< SCU SFSPC_2: MODE Mask */ -#define SCU_SFSPC_2_EPD_Pos 3 /*!< SCU SFSPC_2: EPD Position */ -#define SCU_SFSPC_2_EPD_Msk (0x01UL << SCU_SFSPC_2_EPD_Pos) /*!< SCU SFSPC_2: EPD Mask */ -#define SCU_SFSPC_2_EPUN_Pos 4 /*!< SCU SFSPC_2: EPUN Position */ -#define SCU_SFSPC_2_EPUN_Msk (0x01UL << SCU_SFSPC_2_EPUN_Pos) /*!< SCU SFSPC_2: EPUN Mask */ -#define SCU_SFSPC_2_EHS_Pos 5 /*!< SCU SFSPC_2: EHS Position */ -#define SCU_SFSPC_2_EHS_Msk (0x01UL << SCU_SFSPC_2_EHS_Pos) /*!< SCU SFSPC_2: EHS Mask */ -#define SCU_SFSPC_2_EZI_Pos 6 /*!< SCU SFSPC_2: EZI Position */ -#define SCU_SFSPC_2_EZI_Msk (0x01UL << SCU_SFSPC_2_EZI_Pos) /*!< SCU SFSPC_2: EZI Mask */ -#define SCU_SFSPC_2_EHD_Pos 8 /*!< SCU SFSPC_2: EHD Position */ -#define SCU_SFSPC_2_EHD_Msk (0x03UL << SCU_SFSPC_2_EHD_Pos) /*!< SCU SFSPC_2: EHD Mask */ - -// --------------------------------------- SCU_SFSPC_3 ------------------------------------------ -#define SCU_SFSPC_3_MODE_Pos 0 /*!< SCU SFSPC_3: MODE Position */ -#define SCU_SFSPC_3_MODE_Msk (0x07UL << SCU_SFSPC_3_MODE_Pos) /*!< SCU SFSPC_3: MODE Mask */ -#define SCU_SFSPC_3_EPD_Pos 3 /*!< SCU SFSPC_3: EPD Position */ -#define SCU_SFSPC_3_EPD_Msk (0x01UL << SCU_SFSPC_3_EPD_Pos) /*!< SCU SFSPC_3: EPD Mask */ -#define SCU_SFSPC_3_EPUN_Pos 4 /*!< SCU SFSPC_3: EPUN Position */ -#define SCU_SFSPC_3_EPUN_Msk (0x01UL << SCU_SFSPC_3_EPUN_Pos) /*!< SCU SFSPC_3: EPUN Mask */ -#define SCU_SFSPC_3_EHS_Pos 5 /*!< SCU SFSPC_3: EHS Position */ -#define SCU_SFSPC_3_EHS_Msk (0x01UL << SCU_SFSPC_3_EHS_Pos) /*!< SCU SFSPC_3: EHS Mask */ -#define SCU_SFSPC_3_EZI_Pos 6 /*!< SCU SFSPC_3: EZI Position */ -#define SCU_SFSPC_3_EZI_Msk (0x01UL << SCU_SFSPC_3_EZI_Pos) /*!< SCU SFSPC_3: EZI Mask */ -#define SCU_SFSPC_3_EHD_Pos 8 /*!< SCU SFSPC_3: EHD Position */ -#define SCU_SFSPC_3_EHD_Msk (0x03UL << SCU_SFSPC_3_EHD_Pos) /*!< SCU SFSPC_3: EHD Mask */ - -// --------------------------------------- SCU_SFSPC_4 ------------------------------------------ -#define SCU_SFSPC_4_MODE_Pos 0 /*!< SCU SFSPC_4: MODE Position */ -#define SCU_SFSPC_4_MODE_Msk (0x07UL << SCU_SFSPC_4_MODE_Pos) /*!< SCU SFSPC_4: MODE Mask */ -#define SCU_SFSPC_4_EPD_Pos 3 /*!< SCU SFSPC_4: EPD Position */ -#define SCU_SFSPC_4_EPD_Msk (0x01UL << SCU_SFSPC_4_EPD_Pos) /*!< SCU SFSPC_4: EPD Mask */ -#define SCU_SFSPC_4_EPUN_Pos 4 /*!< SCU SFSPC_4: EPUN Position */ -#define SCU_SFSPC_4_EPUN_Msk (0x01UL << SCU_SFSPC_4_EPUN_Pos) /*!< SCU SFSPC_4: EPUN Mask */ -#define SCU_SFSPC_4_EHS_Pos 5 /*!< SCU SFSPC_4: EHS Position */ -#define SCU_SFSPC_4_EHS_Msk (0x01UL << SCU_SFSPC_4_EHS_Pos) /*!< SCU SFSPC_4: EHS Mask */ -#define SCU_SFSPC_4_EZI_Pos 6 /*!< SCU SFSPC_4: EZI Position */ -#define SCU_SFSPC_4_EZI_Msk (0x01UL << SCU_SFSPC_4_EZI_Pos) /*!< SCU SFSPC_4: EZI Mask */ -#define SCU_SFSPC_4_EHD_Pos 8 /*!< SCU SFSPC_4: EHD Position */ -#define SCU_SFSPC_4_EHD_Msk (0x03UL << SCU_SFSPC_4_EHD_Pos) /*!< SCU SFSPC_4: EHD Mask */ - -// --------------------------------------- SCU_SFSPC_5 ------------------------------------------ -#define SCU_SFSPC_5_MODE_Pos 0 /*!< SCU SFSPC_5: MODE Position */ -#define SCU_SFSPC_5_MODE_Msk (0x07UL << SCU_SFSPC_5_MODE_Pos) /*!< SCU SFSPC_5: MODE Mask */ -#define SCU_SFSPC_5_EPD_Pos 3 /*!< SCU SFSPC_5: EPD Position */ -#define SCU_SFSPC_5_EPD_Msk (0x01UL << SCU_SFSPC_5_EPD_Pos) /*!< SCU SFSPC_5: EPD Mask */ -#define SCU_SFSPC_5_EPUN_Pos 4 /*!< SCU SFSPC_5: EPUN Position */ -#define SCU_SFSPC_5_EPUN_Msk (0x01UL << SCU_SFSPC_5_EPUN_Pos) /*!< SCU SFSPC_5: EPUN Mask */ -#define SCU_SFSPC_5_EHS_Pos 5 /*!< SCU SFSPC_5: EHS Position */ -#define SCU_SFSPC_5_EHS_Msk (0x01UL << SCU_SFSPC_5_EHS_Pos) /*!< SCU SFSPC_5: EHS Mask */ -#define SCU_SFSPC_5_EZI_Pos 6 /*!< SCU SFSPC_5: EZI Position */ -#define SCU_SFSPC_5_EZI_Msk (0x01UL << SCU_SFSPC_5_EZI_Pos) /*!< SCU SFSPC_5: EZI Mask */ -#define SCU_SFSPC_5_EHD_Pos 8 /*!< SCU SFSPC_5: EHD Position */ -#define SCU_SFSPC_5_EHD_Msk (0x03UL << SCU_SFSPC_5_EHD_Pos) /*!< SCU SFSPC_5: EHD Mask */ - -// --------------------------------------- SCU_SFSPC_6 ------------------------------------------ -#define SCU_SFSPC_6_MODE_Pos 0 /*!< SCU SFSPC_6: MODE Position */ -#define SCU_SFSPC_6_MODE_Msk (0x07UL << SCU_SFSPC_6_MODE_Pos) /*!< SCU SFSPC_6: MODE Mask */ -#define SCU_SFSPC_6_EPD_Pos 3 /*!< SCU SFSPC_6: EPD Position */ -#define SCU_SFSPC_6_EPD_Msk (0x01UL << SCU_SFSPC_6_EPD_Pos) /*!< SCU SFSPC_6: EPD Mask */ -#define SCU_SFSPC_6_EPUN_Pos 4 /*!< SCU SFSPC_6: EPUN Position */ -#define SCU_SFSPC_6_EPUN_Msk (0x01UL << SCU_SFSPC_6_EPUN_Pos) /*!< SCU SFSPC_6: EPUN Mask */ -#define SCU_SFSPC_6_EHS_Pos 5 /*!< SCU SFSPC_6: EHS Position */ -#define SCU_SFSPC_6_EHS_Msk (0x01UL << SCU_SFSPC_6_EHS_Pos) /*!< SCU SFSPC_6: EHS Mask */ -#define SCU_SFSPC_6_EZI_Pos 6 /*!< SCU SFSPC_6: EZI Position */ -#define SCU_SFSPC_6_EZI_Msk (0x01UL << SCU_SFSPC_6_EZI_Pos) /*!< SCU SFSPC_6: EZI Mask */ -#define SCU_SFSPC_6_EHD_Pos 8 /*!< SCU SFSPC_6: EHD Position */ -#define SCU_SFSPC_6_EHD_Msk (0x03UL << SCU_SFSPC_6_EHD_Pos) /*!< SCU SFSPC_6: EHD Mask */ - -// --------------------------------------- SCU_SFSPC_7 ------------------------------------------ -#define SCU_SFSPC_7_MODE_Pos 0 /*!< SCU SFSPC_7: MODE Position */ -#define SCU_SFSPC_7_MODE_Msk (0x07UL << SCU_SFSPC_7_MODE_Pos) /*!< SCU SFSPC_7: MODE Mask */ -#define SCU_SFSPC_7_EPD_Pos 3 /*!< SCU SFSPC_7: EPD Position */ -#define SCU_SFSPC_7_EPD_Msk (0x01UL << SCU_SFSPC_7_EPD_Pos) /*!< SCU SFSPC_7: EPD Mask */ -#define SCU_SFSPC_7_EPUN_Pos 4 /*!< SCU SFSPC_7: EPUN Position */ -#define SCU_SFSPC_7_EPUN_Msk (0x01UL << SCU_SFSPC_7_EPUN_Pos) /*!< SCU SFSPC_7: EPUN Mask */ -#define SCU_SFSPC_7_EHS_Pos 5 /*!< SCU SFSPC_7: EHS Position */ -#define SCU_SFSPC_7_EHS_Msk (0x01UL << SCU_SFSPC_7_EHS_Pos) /*!< SCU SFSPC_7: EHS Mask */ -#define SCU_SFSPC_7_EZI_Pos 6 /*!< SCU SFSPC_7: EZI Position */ -#define SCU_SFSPC_7_EZI_Msk (0x01UL << SCU_SFSPC_7_EZI_Pos) /*!< SCU SFSPC_7: EZI Mask */ -#define SCU_SFSPC_7_EHD_Pos 8 /*!< SCU SFSPC_7: EHD Position */ -#define SCU_SFSPC_7_EHD_Msk (0x03UL << SCU_SFSPC_7_EHD_Pos) /*!< SCU SFSPC_7: EHD Mask */ - -// --------------------------------------- SCU_SFSPC_8 ------------------------------------------ -#define SCU_SFSPC_8_MODE_Pos 0 /*!< SCU SFSPC_8: MODE Position */ -#define SCU_SFSPC_8_MODE_Msk (0x07UL << SCU_SFSPC_8_MODE_Pos) /*!< SCU SFSPC_8: MODE Mask */ -#define SCU_SFSPC_8_EPD_Pos 3 /*!< SCU SFSPC_8: EPD Position */ -#define SCU_SFSPC_8_EPD_Msk (0x01UL << SCU_SFSPC_8_EPD_Pos) /*!< SCU SFSPC_8: EPD Mask */ -#define SCU_SFSPC_8_EPUN_Pos 4 /*!< SCU SFSPC_8: EPUN Position */ -#define SCU_SFSPC_8_EPUN_Msk (0x01UL << SCU_SFSPC_8_EPUN_Pos) /*!< SCU SFSPC_8: EPUN Mask */ -#define SCU_SFSPC_8_EHS_Pos 5 /*!< SCU SFSPC_8: EHS Position */ -#define SCU_SFSPC_8_EHS_Msk (0x01UL << SCU_SFSPC_8_EHS_Pos) /*!< SCU SFSPC_8: EHS Mask */ -#define SCU_SFSPC_8_EZI_Pos 6 /*!< SCU SFSPC_8: EZI Position */ -#define SCU_SFSPC_8_EZI_Msk (0x01UL << SCU_SFSPC_8_EZI_Pos) /*!< SCU SFSPC_8: EZI Mask */ -#define SCU_SFSPC_8_EHD_Pos 8 /*!< SCU SFSPC_8: EHD Position */ -#define SCU_SFSPC_8_EHD_Msk (0x03UL << SCU_SFSPC_8_EHD_Pos) /*!< SCU SFSPC_8: EHD Mask */ - -// --------------------------------------- SCU_SFSPC_9 ------------------------------------------ -#define SCU_SFSPC_9_MODE_Pos 0 /*!< SCU SFSPC_9: MODE Position */ -#define SCU_SFSPC_9_MODE_Msk (0x07UL << SCU_SFSPC_9_MODE_Pos) /*!< SCU SFSPC_9: MODE Mask */ -#define SCU_SFSPC_9_EPD_Pos 3 /*!< SCU SFSPC_9: EPD Position */ -#define SCU_SFSPC_9_EPD_Msk (0x01UL << SCU_SFSPC_9_EPD_Pos) /*!< SCU SFSPC_9: EPD Mask */ -#define SCU_SFSPC_9_EPUN_Pos 4 /*!< SCU SFSPC_9: EPUN Position */ -#define SCU_SFSPC_9_EPUN_Msk (0x01UL << SCU_SFSPC_9_EPUN_Pos) /*!< SCU SFSPC_9: EPUN Mask */ -#define SCU_SFSPC_9_EHS_Pos 5 /*!< SCU SFSPC_9: EHS Position */ -#define SCU_SFSPC_9_EHS_Msk (0x01UL << SCU_SFSPC_9_EHS_Pos) /*!< SCU SFSPC_9: EHS Mask */ -#define SCU_SFSPC_9_EZI_Pos 6 /*!< SCU SFSPC_9: EZI Position */ -#define SCU_SFSPC_9_EZI_Msk (0x01UL << SCU_SFSPC_9_EZI_Pos) /*!< SCU SFSPC_9: EZI Mask */ -#define SCU_SFSPC_9_EHD_Pos 8 /*!< SCU SFSPC_9: EHD Position */ -#define SCU_SFSPC_9_EHD_Msk (0x03UL << SCU_SFSPC_9_EHD_Pos) /*!< SCU SFSPC_9: EHD Mask */ - -// -------------------------------------- SCU_SFSPC_10 ------------------------------------------ -#define SCU_SFSPC_10_MODE_Pos 0 /*!< SCU SFSPC_10: MODE Position */ -#define SCU_SFSPC_10_MODE_Msk (0x07UL << SCU_SFSPC_10_MODE_Pos) /*!< SCU SFSPC_10: MODE Mask */ -#define SCU_SFSPC_10_EPD_Pos 3 /*!< SCU SFSPC_10: EPD Position */ -#define SCU_SFSPC_10_EPD_Msk (0x01UL << SCU_SFSPC_10_EPD_Pos) /*!< SCU SFSPC_10: EPD Mask */ -#define SCU_SFSPC_10_EPUN_Pos 4 /*!< SCU SFSPC_10: EPUN Position */ -#define SCU_SFSPC_10_EPUN_Msk (0x01UL << SCU_SFSPC_10_EPUN_Pos) /*!< SCU SFSPC_10: EPUN Mask */ -#define SCU_SFSPC_10_EHS_Pos 5 /*!< SCU SFSPC_10: EHS Position */ -#define SCU_SFSPC_10_EHS_Msk (0x01UL << SCU_SFSPC_10_EHS_Pos) /*!< SCU SFSPC_10: EHS Mask */ -#define SCU_SFSPC_10_EZI_Pos 6 /*!< SCU SFSPC_10: EZI Position */ -#define SCU_SFSPC_10_EZI_Msk (0x01UL << SCU_SFSPC_10_EZI_Pos) /*!< SCU SFSPC_10: EZI Mask */ -#define SCU_SFSPC_10_EHD_Pos 8 /*!< SCU SFSPC_10: EHD Position */ -#define SCU_SFSPC_10_EHD_Msk (0x03UL << SCU_SFSPC_10_EHD_Pos) /*!< SCU SFSPC_10: EHD Mask */ - -// -------------------------------------- SCU_SFSPC_11 ------------------------------------------ -#define SCU_SFSPC_11_MODE_Pos 0 /*!< SCU SFSPC_11: MODE Position */ -#define SCU_SFSPC_11_MODE_Msk (0x07UL << SCU_SFSPC_11_MODE_Pos) /*!< SCU SFSPC_11: MODE Mask */ -#define SCU_SFSPC_11_EPD_Pos 3 /*!< SCU SFSPC_11: EPD Position */ -#define SCU_SFSPC_11_EPD_Msk (0x01UL << SCU_SFSPC_11_EPD_Pos) /*!< SCU SFSPC_11: EPD Mask */ -#define SCU_SFSPC_11_EPUN_Pos 4 /*!< SCU SFSPC_11: EPUN Position */ -#define SCU_SFSPC_11_EPUN_Msk (0x01UL << SCU_SFSPC_11_EPUN_Pos) /*!< SCU SFSPC_11: EPUN Mask */ -#define SCU_SFSPC_11_EHS_Pos 5 /*!< SCU SFSPC_11: EHS Position */ -#define SCU_SFSPC_11_EHS_Msk (0x01UL << SCU_SFSPC_11_EHS_Pos) /*!< SCU SFSPC_11: EHS Mask */ -#define SCU_SFSPC_11_EZI_Pos 6 /*!< SCU SFSPC_11: EZI Position */ -#define SCU_SFSPC_11_EZI_Msk (0x01UL << SCU_SFSPC_11_EZI_Pos) /*!< SCU SFSPC_11: EZI Mask */ -#define SCU_SFSPC_11_EHD_Pos 8 /*!< SCU SFSPC_11: EHD Position */ -#define SCU_SFSPC_11_EHD_Msk (0x03UL << SCU_SFSPC_11_EHD_Pos) /*!< SCU SFSPC_11: EHD Mask */ - -// -------------------------------------- SCU_SFSPC_12 ------------------------------------------ -#define SCU_SFSPC_12_MODE_Pos 0 /*!< SCU SFSPC_12: MODE Position */ -#define SCU_SFSPC_12_MODE_Msk (0x07UL << SCU_SFSPC_12_MODE_Pos) /*!< SCU SFSPC_12: MODE Mask */ -#define SCU_SFSPC_12_EPD_Pos 3 /*!< SCU SFSPC_12: EPD Position */ -#define SCU_SFSPC_12_EPD_Msk (0x01UL << SCU_SFSPC_12_EPD_Pos) /*!< SCU SFSPC_12: EPD Mask */ -#define SCU_SFSPC_12_EPUN_Pos 4 /*!< SCU SFSPC_12: EPUN Position */ -#define SCU_SFSPC_12_EPUN_Msk (0x01UL << SCU_SFSPC_12_EPUN_Pos) /*!< SCU SFSPC_12: EPUN Mask */ -#define SCU_SFSPC_12_EHS_Pos 5 /*!< SCU SFSPC_12: EHS Position */ -#define SCU_SFSPC_12_EHS_Msk (0x01UL << SCU_SFSPC_12_EHS_Pos) /*!< SCU SFSPC_12: EHS Mask */ -#define SCU_SFSPC_12_EZI_Pos 6 /*!< SCU SFSPC_12: EZI Position */ -#define SCU_SFSPC_12_EZI_Msk (0x01UL << SCU_SFSPC_12_EZI_Pos) /*!< SCU SFSPC_12: EZI Mask */ -#define SCU_SFSPC_12_EHD_Pos 8 /*!< SCU SFSPC_12: EHD Position */ -#define SCU_SFSPC_12_EHD_Msk (0x03UL << SCU_SFSPC_12_EHD_Pos) /*!< SCU SFSPC_12: EHD Mask */ - -// -------------------------------------- SCU_SFSPC_13 ------------------------------------------ -#define SCU_SFSPC_13_MODE_Pos 0 /*!< SCU SFSPC_13: MODE Position */ -#define SCU_SFSPC_13_MODE_Msk (0x07UL << SCU_SFSPC_13_MODE_Pos) /*!< SCU SFSPC_13: MODE Mask */ -#define SCU_SFSPC_13_EPD_Pos 3 /*!< SCU SFSPC_13: EPD Position */ -#define SCU_SFSPC_13_EPD_Msk (0x01UL << SCU_SFSPC_13_EPD_Pos) /*!< SCU SFSPC_13: EPD Mask */ -#define SCU_SFSPC_13_EPUN_Pos 4 /*!< SCU SFSPC_13: EPUN Position */ -#define SCU_SFSPC_13_EPUN_Msk (0x01UL << SCU_SFSPC_13_EPUN_Pos) /*!< SCU SFSPC_13: EPUN Mask */ -#define SCU_SFSPC_13_EHS_Pos 5 /*!< SCU SFSPC_13: EHS Position */ -#define SCU_SFSPC_13_EHS_Msk (0x01UL << SCU_SFSPC_13_EHS_Pos) /*!< SCU SFSPC_13: EHS Mask */ -#define SCU_SFSPC_13_EZI_Pos 6 /*!< SCU SFSPC_13: EZI Position */ -#define SCU_SFSPC_13_EZI_Msk (0x01UL << SCU_SFSPC_13_EZI_Pos) /*!< SCU SFSPC_13: EZI Mask */ -#define SCU_SFSPC_13_EHD_Pos 8 /*!< SCU SFSPC_13: EHD Position */ -#define SCU_SFSPC_13_EHD_Msk (0x03UL << SCU_SFSPC_13_EHD_Pos) /*!< SCU SFSPC_13: EHD Mask */ - -// -------------------------------------- SCU_SFSPC_14 ------------------------------------------ -#define SCU_SFSPC_14_MODE_Pos 0 /*!< SCU SFSPC_14: MODE Position */ -#define SCU_SFSPC_14_MODE_Msk (0x07UL << SCU_SFSPC_14_MODE_Pos) /*!< SCU SFSPC_14: MODE Mask */ -#define SCU_SFSPC_14_EPD_Pos 3 /*!< SCU SFSPC_14: EPD Position */ -#define SCU_SFSPC_14_EPD_Msk (0x01UL << SCU_SFSPC_14_EPD_Pos) /*!< SCU SFSPC_14: EPD Mask */ -#define SCU_SFSPC_14_EPUN_Pos 4 /*!< SCU SFSPC_14: EPUN Position */ -#define SCU_SFSPC_14_EPUN_Msk (0x01UL << SCU_SFSPC_14_EPUN_Pos) /*!< SCU SFSPC_14: EPUN Mask */ -#define SCU_SFSPC_14_EHS_Pos 5 /*!< SCU SFSPC_14: EHS Position */ -#define SCU_SFSPC_14_EHS_Msk (0x01UL << SCU_SFSPC_14_EHS_Pos) /*!< SCU SFSPC_14: EHS Mask */ -#define SCU_SFSPC_14_EZI_Pos 6 /*!< SCU SFSPC_14: EZI Position */ -#define SCU_SFSPC_14_EZI_Msk (0x01UL << SCU_SFSPC_14_EZI_Pos) /*!< SCU SFSPC_14: EZI Mask */ -#define SCU_SFSPC_14_EHD_Pos 8 /*!< SCU SFSPC_14: EHD Position */ -#define SCU_SFSPC_14_EHD_Msk (0x03UL << SCU_SFSPC_14_EHD_Pos) /*!< SCU SFSPC_14: EHD Mask */ - -// --------------------------------------- SCU_SFSPD_0 ------------------------------------------ -#define SCU_SFSPD_0_MODE_Pos 0 /*!< SCU SFSPD_0: MODE Position */ -#define SCU_SFSPD_0_MODE_Msk (0x07UL << SCU_SFSPD_0_MODE_Pos) /*!< SCU SFSPD_0: MODE Mask */ -#define SCU_SFSPD_0_EPD_Pos 3 /*!< SCU SFSPD_0: EPD Position */ -#define SCU_SFSPD_0_EPD_Msk (0x01UL << SCU_SFSPD_0_EPD_Pos) /*!< SCU SFSPD_0: EPD Mask */ -#define SCU_SFSPD_0_EPUN_Pos 4 /*!< SCU SFSPD_0: EPUN Position */ -#define SCU_SFSPD_0_EPUN_Msk (0x01UL << SCU_SFSPD_0_EPUN_Pos) /*!< SCU SFSPD_0: EPUN Mask */ -#define SCU_SFSPD_0_EHS_Pos 5 /*!< SCU SFSPD_0: EHS Position */ -#define SCU_SFSPD_0_EHS_Msk (0x01UL << SCU_SFSPD_0_EHS_Pos) /*!< SCU SFSPD_0: EHS Mask */ -#define SCU_SFSPD_0_EZI_Pos 6 /*!< SCU SFSPD_0: EZI Position */ -#define SCU_SFSPD_0_EZI_Msk (0x01UL << SCU_SFSPD_0_EZI_Pos) /*!< SCU SFSPD_0: EZI Mask */ -#define SCU_SFSPD_0_EHD_Pos 8 /*!< SCU SFSPD_0: EHD Position */ -#define SCU_SFSPD_0_EHD_Msk (0x03UL << SCU_SFSPD_0_EHD_Pos) /*!< SCU SFSPD_0: EHD Mask */ - -// --------------------------------------- SCU_SFSPD_1 ------------------------------------------ -#define SCU_SFSPD_1_MODE_Pos 0 /*!< SCU SFSPD_1: MODE Position */ -#define SCU_SFSPD_1_MODE_Msk (0x07UL << SCU_SFSPD_1_MODE_Pos) /*!< SCU SFSPD_1: MODE Mask */ -#define SCU_SFSPD_1_EPD_Pos 3 /*!< SCU SFSPD_1: EPD Position */ -#define SCU_SFSPD_1_EPD_Msk (0x01UL << SCU_SFSPD_1_EPD_Pos) /*!< SCU SFSPD_1: EPD Mask */ -#define SCU_SFSPD_1_EPUN_Pos 4 /*!< SCU SFSPD_1: EPUN Position */ -#define SCU_SFSPD_1_EPUN_Msk (0x01UL << SCU_SFSPD_1_EPUN_Pos) /*!< SCU SFSPD_1: EPUN Mask */ -#define SCU_SFSPD_1_EHS_Pos 5 /*!< SCU SFSPD_1: EHS Position */ -#define SCU_SFSPD_1_EHS_Msk (0x01UL << SCU_SFSPD_1_EHS_Pos) /*!< SCU SFSPD_1: EHS Mask */ -#define SCU_SFSPD_1_EZI_Pos 6 /*!< SCU SFSPD_1: EZI Position */ -#define SCU_SFSPD_1_EZI_Msk (0x01UL << SCU_SFSPD_1_EZI_Pos) /*!< SCU SFSPD_1: EZI Mask */ -#define SCU_SFSPD_1_EHD_Pos 8 /*!< SCU SFSPD_1: EHD Position */ -#define SCU_SFSPD_1_EHD_Msk (0x03UL << SCU_SFSPD_1_EHD_Pos) /*!< SCU SFSPD_1: EHD Mask */ - -// --------------------------------------- SCU_SFSPD_2 ------------------------------------------ -#define SCU_SFSPD_2_MODE_Pos 0 /*!< SCU SFSPD_2: MODE Position */ -#define SCU_SFSPD_2_MODE_Msk (0x07UL << SCU_SFSPD_2_MODE_Pos) /*!< SCU SFSPD_2: MODE Mask */ -#define SCU_SFSPD_2_EPD_Pos 3 /*!< SCU SFSPD_2: EPD Position */ -#define SCU_SFSPD_2_EPD_Msk (0x01UL << SCU_SFSPD_2_EPD_Pos) /*!< SCU SFSPD_2: EPD Mask */ -#define SCU_SFSPD_2_EPUN_Pos 4 /*!< SCU SFSPD_2: EPUN Position */ -#define SCU_SFSPD_2_EPUN_Msk (0x01UL << SCU_SFSPD_2_EPUN_Pos) /*!< SCU SFSPD_2: EPUN Mask */ -#define SCU_SFSPD_2_EHS_Pos 5 /*!< SCU SFSPD_2: EHS Position */ -#define SCU_SFSPD_2_EHS_Msk (0x01UL << SCU_SFSPD_2_EHS_Pos) /*!< SCU SFSPD_2: EHS Mask */ -#define SCU_SFSPD_2_EZI_Pos 6 /*!< SCU SFSPD_2: EZI Position */ -#define SCU_SFSPD_2_EZI_Msk (0x01UL << SCU_SFSPD_2_EZI_Pos) /*!< SCU SFSPD_2: EZI Mask */ -#define SCU_SFSPD_2_EHD_Pos 8 /*!< SCU SFSPD_2: EHD Position */ -#define SCU_SFSPD_2_EHD_Msk (0x03UL << SCU_SFSPD_2_EHD_Pos) /*!< SCU SFSPD_2: EHD Mask */ - -// --------------------------------------- SCU_SFSPD_3 ------------------------------------------ -#define SCU_SFSPD_3_MODE_Pos 0 /*!< SCU SFSPD_3: MODE Position */ -#define SCU_SFSPD_3_MODE_Msk (0x07UL << SCU_SFSPD_3_MODE_Pos) /*!< SCU SFSPD_3: MODE Mask */ -#define SCU_SFSPD_3_EPD_Pos 3 /*!< SCU SFSPD_3: EPD Position */ -#define SCU_SFSPD_3_EPD_Msk (0x01UL << SCU_SFSPD_3_EPD_Pos) /*!< SCU SFSPD_3: EPD Mask */ -#define SCU_SFSPD_3_EPUN_Pos 4 /*!< SCU SFSPD_3: EPUN Position */ -#define SCU_SFSPD_3_EPUN_Msk (0x01UL << SCU_SFSPD_3_EPUN_Pos) /*!< SCU SFSPD_3: EPUN Mask */ -#define SCU_SFSPD_3_EHS_Pos 5 /*!< SCU SFSPD_3: EHS Position */ -#define SCU_SFSPD_3_EHS_Msk (0x01UL << SCU_SFSPD_3_EHS_Pos) /*!< SCU SFSPD_3: EHS Mask */ -#define SCU_SFSPD_3_EZI_Pos 6 /*!< SCU SFSPD_3: EZI Position */ -#define SCU_SFSPD_3_EZI_Msk (0x01UL << SCU_SFSPD_3_EZI_Pos) /*!< SCU SFSPD_3: EZI Mask */ -#define SCU_SFSPD_3_EHD_Pos 8 /*!< SCU SFSPD_3: EHD Position */ -#define SCU_SFSPD_3_EHD_Msk (0x03UL << SCU_SFSPD_3_EHD_Pos) /*!< SCU SFSPD_3: EHD Mask */ - -// --------------------------------------- SCU_SFSPD_4 ------------------------------------------ -#define SCU_SFSPD_4_MODE_Pos 0 /*!< SCU SFSPD_4: MODE Position */ -#define SCU_SFSPD_4_MODE_Msk (0x07UL << SCU_SFSPD_4_MODE_Pos) /*!< SCU SFSPD_4: MODE Mask */ -#define SCU_SFSPD_4_EPD_Pos 3 /*!< SCU SFSPD_4: EPD Position */ -#define SCU_SFSPD_4_EPD_Msk (0x01UL << SCU_SFSPD_4_EPD_Pos) /*!< SCU SFSPD_4: EPD Mask */ -#define SCU_SFSPD_4_EPUN_Pos 4 /*!< SCU SFSPD_4: EPUN Position */ -#define SCU_SFSPD_4_EPUN_Msk (0x01UL << SCU_SFSPD_4_EPUN_Pos) /*!< SCU SFSPD_4: EPUN Mask */ -#define SCU_SFSPD_4_EHS_Pos 5 /*!< SCU SFSPD_4: EHS Position */ -#define SCU_SFSPD_4_EHS_Msk (0x01UL << SCU_SFSPD_4_EHS_Pos) /*!< SCU SFSPD_4: EHS Mask */ -#define SCU_SFSPD_4_EZI_Pos 6 /*!< SCU SFSPD_4: EZI Position */ -#define SCU_SFSPD_4_EZI_Msk (0x01UL << SCU_SFSPD_4_EZI_Pos) /*!< SCU SFSPD_4: EZI Mask */ -#define SCU_SFSPD_4_EHD_Pos 8 /*!< SCU SFSPD_4: EHD Position */ -#define SCU_SFSPD_4_EHD_Msk (0x03UL << SCU_SFSPD_4_EHD_Pos) /*!< SCU SFSPD_4: EHD Mask */ - -// --------------------------------------- SCU_SFSPD_5 ------------------------------------------ -#define SCU_SFSPD_5_MODE_Pos 0 /*!< SCU SFSPD_5: MODE Position */ -#define SCU_SFSPD_5_MODE_Msk (0x07UL << SCU_SFSPD_5_MODE_Pos) /*!< SCU SFSPD_5: MODE Mask */ -#define SCU_SFSPD_5_EPD_Pos 3 /*!< SCU SFSPD_5: EPD Position */ -#define SCU_SFSPD_5_EPD_Msk (0x01UL << SCU_SFSPD_5_EPD_Pos) /*!< SCU SFSPD_5: EPD Mask */ -#define SCU_SFSPD_5_EPUN_Pos 4 /*!< SCU SFSPD_5: EPUN Position */ -#define SCU_SFSPD_5_EPUN_Msk (0x01UL << SCU_SFSPD_5_EPUN_Pos) /*!< SCU SFSPD_5: EPUN Mask */ -#define SCU_SFSPD_5_EHS_Pos 5 /*!< SCU SFSPD_5: EHS Position */ -#define SCU_SFSPD_5_EHS_Msk (0x01UL << SCU_SFSPD_5_EHS_Pos) /*!< SCU SFSPD_5: EHS Mask */ -#define SCU_SFSPD_5_EZI_Pos 6 /*!< SCU SFSPD_5: EZI Position */ -#define SCU_SFSPD_5_EZI_Msk (0x01UL << SCU_SFSPD_5_EZI_Pos) /*!< SCU SFSPD_5: EZI Mask */ -#define SCU_SFSPD_5_EHD_Pos 8 /*!< SCU SFSPD_5: EHD Position */ -#define SCU_SFSPD_5_EHD_Msk (0x03UL << SCU_SFSPD_5_EHD_Pos) /*!< SCU SFSPD_5: EHD Mask */ - -// --------------------------------------- SCU_SFSPD_6 ------------------------------------------ -#define SCU_SFSPD_6_MODE_Pos 0 /*!< SCU SFSPD_6: MODE Position */ -#define SCU_SFSPD_6_MODE_Msk (0x07UL << SCU_SFSPD_6_MODE_Pos) /*!< SCU SFSPD_6: MODE Mask */ -#define SCU_SFSPD_6_EPD_Pos 3 /*!< SCU SFSPD_6: EPD Position */ -#define SCU_SFSPD_6_EPD_Msk (0x01UL << SCU_SFSPD_6_EPD_Pos) /*!< SCU SFSPD_6: EPD Mask */ -#define SCU_SFSPD_6_EPUN_Pos 4 /*!< SCU SFSPD_6: EPUN Position */ -#define SCU_SFSPD_6_EPUN_Msk (0x01UL << SCU_SFSPD_6_EPUN_Pos) /*!< SCU SFSPD_6: EPUN Mask */ -#define SCU_SFSPD_6_EHS_Pos 5 /*!< SCU SFSPD_6: EHS Position */ -#define SCU_SFSPD_6_EHS_Msk (0x01UL << SCU_SFSPD_6_EHS_Pos) /*!< SCU SFSPD_6: EHS Mask */ -#define SCU_SFSPD_6_EZI_Pos 6 /*!< SCU SFSPD_6: EZI Position */ -#define SCU_SFSPD_6_EZI_Msk (0x01UL << SCU_SFSPD_6_EZI_Pos) /*!< SCU SFSPD_6: EZI Mask */ -#define SCU_SFSPD_6_EHD_Pos 8 /*!< SCU SFSPD_6: EHD Position */ -#define SCU_SFSPD_6_EHD_Msk (0x03UL << SCU_SFSPD_6_EHD_Pos) /*!< SCU SFSPD_6: EHD Mask */ - -// --------------------------------------- SCU_SFSPD_7 ------------------------------------------ -#define SCU_SFSPD_7_MODE_Pos 0 /*!< SCU SFSPD_7: MODE Position */ -#define SCU_SFSPD_7_MODE_Msk (0x07UL << SCU_SFSPD_7_MODE_Pos) /*!< SCU SFSPD_7: MODE Mask */ -#define SCU_SFSPD_7_EPD_Pos 3 /*!< SCU SFSPD_7: EPD Position */ -#define SCU_SFSPD_7_EPD_Msk (0x01UL << SCU_SFSPD_7_EPD_Pos) /*!< SCU SFSPD_7: EPD Mask */ -#define SCU_SFSPD_7_EPUN_Pos 4 /*!< SCU SFSPD_7: EPUN Position */ -#define SCU_SFSPD_7_EPUN_Msk (0x01UL << SCU_SFSPD_7_EPUN_Pos) /*!< SCU SFSPD_7: EPUN Mask */ -#define SCU_SFSPD_7_EHS_Pos 5 /*!< SCU SFSPD_7: EHS Position */ -#define SCU_SFSPD_7_EHS_Msk (0x01UL << SCU_SFSPD_7_EHS_Pos) /*!< SCU SFSPD_7: EHS Mask */ -#define SCU_SFSPD_7_EZI_Pos 6 /*!< SCU SFSPD_7: EZI Position */ -#define SCU_SFSPD_7_EZI_Msk (0x01UL << SCU_SFSPD_7_EZI_Pos) /*!< SCU SFSPD_7: EZI Mask */ -#define SCU_SFSPD_7_EHD_Pos 8 /*!< SCU SFSPD_7: EHD Position */ -#define SCU_SFSPD_7_EHD_Msk (0x03UL << SCU_SFSPD_7_EHD_Pos) /*!< SCU SFSPD_7: EHD Mask */ - -// --------------------------------------- SCU_SFSPD_8 ------------------------------------------ -#define SCU_SFSPD_8_MODE_Pos 0 /*!< SCU SFSPD_8: MODE Position */ -#define SCU_SFSPD_8_MODE_Msk (0x07UL << SCU_SFSPD_8_MODE_Pos) /*!< SCU SFSPD_8: MODE Mask */ -#define SCU_SFSPD_8_EPD_Pos 3 /*!< SCU SFSPD_8: EPD Position */ -#define SCU_SFSPD_8_EPD_Msk (0x01UL << SCU_SFSPD_8_EPD_Pos) /*!< SCU SFSPD_8: EPD Mask */ -#define SCU_SFSPD_8_EPUN_Pos 4 /*!< SCU SFSPD_8: EPUN Position */ -#define SCU_SFSPD_8_EPUN_Msk (0x01UL << SCU_SFSPD_8_EPUN_Pos) /*!< SCU SFSPD_8: EPUN Mask */ -#define SCU_SFSPD_8_EHS_Pos 5 /*!< SCU SFSPD_8: EHS Position */ -#define SCU_SFSPD_8_EHS_Msk (0x01UL << SCU_SFSPD_8_EHS_Pos) /*!< SCU SFSPD_8: EHS Mask */ -#define SCU_SFSPD_8_EZI_Pos 6 /*!< SCU SFSPD_8: EZI Position */ -#define SCU_SFSPD_8_EZI_Msk (0x01UL << SCU_SFSPD_8_EZI_Pos) /*!< SCU SFSPD_8: EZI Mask */ -#define SCU_SFSPD_8_EHD_Pos 8 /*!< SCU SFSPD_8: EHD Position */ -#define SCU_SFSPD_8_EHD_Msk (0x03UL << SCU_SFSPD_8_EHD_Pos) /*!< SCU SFSPD_8: EHD Mask */ - -// --------------------------------------- SCU_SFSPD_9 ------------------------------------------ -#define SCU_SFSPD_9_MODE_Pos 0 /*!< SCU SFSPD_9: MODE Position */ -#define SCU_SFSPD_9_MODE_Msk (0x07UL << SCU_SFSPD_9_MODE_Pos) /*!< SCU SFSPD_9: MODE Mask */ -#define SCU_SFSPD_9_EPD_Pos 3 /*!< SCU SFSPD_9: EPD Position */ -#define SCU_SFSPD_9_EPD_Msk (0x01UL << SCU_SFSPD_9_EPD_Pos) /*!< SCU SFSPD_9: EPD Mask */ -#define SCU_SFSPD_9_EPUN_Pos 4 /*!< SCU SFSPD_9: EPUN Position */ -#define SCU_SFSPD_9_EPUN_Msk (0x01UL << SCU_SFSPD_9_EPUN_Pos) /*!< SCU SFSPD_9: EPUN Mask */ -#define SCU_SFSPD_9_EHS_Pos 5 /*!< SCU SFSPD_9: EHS Position */ -#define SCU_SFSPD_9_EHS_Msk (0x01UL << SCU_SFSPD_9_EHS_Pos) /*!< SCU SFSPD_9: EHS Mask */ -#define SCU_SFSPD_9_EZI_Pos 6 /*!< SCU SFSPD_9: EZI Position */ -#define SCU_SFSPD_9_EZI_Msk (0x01UL << SCU_SFSPD_9_EZI_Pos) /*!< SCU SFSPD_9: EZI Mask */ -#define SCU_SFSPD_9_EHD_Pos 8 /*!< SCU SFSPD_9: EHD Position */ -#define SCU_SFSPD_9_EHD_Msk (0x03UL << SCU_SFSPD_9_EHD_Pos) /*!< SCU SFSPD_9: EHD Mask */ - -// -------------------------------------- SCU_SFSPD_10 ------------------------------------------ -#define SCU_SFSPD_10_MODE_Pos 0 /*!< SCU SFSPD_10: MODE Position */ -#define SCU_SFSPD_10_MODE_Msk (0x07UL << SCU_SFSPD_10_MODE_Pos) /*!< SCU SFSPD_10: MODE Mask */ -#define SCU_SFSPD_10_EPD_Pos 3 /*!< SCU SFSPD_10: EPD Position */ -#define SCU_SFSPD_10_EPD_Msk (0x01UL << SCU_SFSPD_10_EPD_Pos) /*!< SCU SFSPD_10: EPD Mask */ -#define SCU_SFSPD_10_EPUN_Pos 4 /*!< SCU SFSPD_10: EPUN Position */ -#define SCU_SFSPD_10_EPUN_Msk (0x01UL << SCU_SFSPD_10_EPUN_Pos) /*!< SCU SFSPD_10: EPUN Mask */ -#define SCU_SFSPD_10_EHS_Pos 5 /*!< SCU SFSPD_10: EHS Position */ -#define SCU_SFSPD_10_EHS_Msk (0x01UL << SCU_SFSPD_10_EHS_Pos) /*!< SCU SFSPD_10: EHS Mask */ -#define SCU_SFSPD_10_EZI_Pos 6 /*!< SCU SFSPD_10: EZI Position */ -#define SCU_SFSPD_10_EZI_Msk (0x01UL << SCU_SFSPD_10_EZI_Pos) /*!< SCU SFSPD_10: EZI Mask */ -#define SCU_SFSPD_10_EHD_Pos 8 /*!< SCU SFSPD_10: EHD Position */ -#define SCU_SFSPD_10_EHD_Msk (0x03UL << SCU_SFSPD_10_EHD_Pos) /*!< SCU SFSPD_10: EHD Mask */ - -// -------------------------------------- SCU_SFSPD_11 ------------------------------------------ -#define SCU_SFSPD_11_MODE_Pos 0 /*!< SCU SFSPD_11: MODE Position */ -#define SCU_SFSPD_11_MODE_Msk (0x07UL << SCU_SFSPD_11_MODE_Pos) /*!< SCU SFSPD_11: MODE Mask */ -#define SCU_SFSPD_11_EPD_Pos 3 /*!< SCU SFSPD_11: EPD Position */ -#define SCU_SFSPD_11_EPD_Msk (0x01UL << SCU_SFSPD_11_EPD_Pos) /*!< SCU SFSPD_11: EPD Mask */ -#define SCU_SFSPD_11_EPUN_Pos 4 /*!< SCU SFSPD_11: EPUN Position */ -#define SCU_SFSPD_11_EPUN_Msk (0x01UL << SCU_SFSPD_11_EPUN_Pos) /*!< SCU SFSPD_11: EPUN Mask */ -#define SCU_SFSPD_11_EHS_Pos 5 /*!< SCU SFSPD_11: EHS Position */ -#define SCU_SFSPD_11_EHS_Msk (0x01UL << SCU_SFSPD_11_EHS_Pos) /*!< SCU SFSPD_11: EHS Mask */ -#define SCU_SFSPD_11_EZI_Pos 6 /*!< SCU SFSPD_11: EZI Position */ -#define SCU_SFSPD_11_EZI_Msk (0x01UL << SCU_SFSPD_11_EZI_Pos) /*!< SCU SFSPD_11: EZI Mask */ -#define SCU_SFSPD_11_EHD_Pos 8 /*!< SCU SFSPD_11: EHD Position */ -#define SCU_SFSPD_11_EHD_Msk (0x03UL << SCU_SFSPD_11_EHD_Pos) /*!< SCU SFSPD_11: EHD Mask */ - -// -------------------------------------- SCU_SFSPD_12 ------------------------------------------ -#define SCU_SFSPD_12_MODE_Pos 0 /*!< SCU SFSPD_12: MODE Position */ -#define SCU_SFSPD_12_MODE_Msk (0x07UL << SCU_SFSPD_12_MODE_Pos) /*!< SCU SFSPD_12: MODE Mask */ -#define SCU_SFSPD_12_EPD_Pos 3 /*!< SCU SFSPD_12: EPD Position */ -#define SCU_SFSPD_12_EPD_Msk (0x01UL << SCU_SFSPD_12_EPD_Pos) /*!< SCU SFSPD_12: EPD Mask */ -#define SCU_SFSPD_12_EPUN_Pos 4 /*!< SCU SFSPD_12: EPUN Position */ -#define SCU_SFSPD_12_EPUN_Msk (0x01UL << SCU_SFSPD_12_EPUN_Pos) /*!< SCU SFSPD_12: EPUN Mask */ -#define SCU_SFSPD_12_EHS_Pos 5 /*!< SCU SFSPD_12: EHS Position */ -#define SCU_SFSPD_12_EHS_Msk (0x01UL << SCU_SFSPD_12_EHS_Pos) /*!< SCU SFSPD_12: EHS Mask */ -#define SCU_SFSPD_12_EZI_Pos 6 /*!< SCU SFSPD_12: EZI Position */ -#define SCU_SFSPD_12_EZI_Msk (0x01UL << SCU_SFSPD_12_EZI_Pos) /*!< SCU SFSPD_12: EZI Mask */ -#define SCU_SFSPD_12_EHD_Pos 8 /*!< SCU SFSPD_12: EHD Position */ -#define SCU_SFSPD_12_EHD_Msk (0x03UL << SCU_SFSPD_12_EHD_Pos) /*!< SCU SFSPD_12: EHD Mask */ - -// -------------------------------------- SCU_SFSPD_13 ------------------------------------------ -#define SCU_SFSPD_13_MODE_Pos 0 /*!< SCU SFSPD_13: MODE Position */ -#define SCU_SFSPD_13_MODE_Msk (0x07UL << SCU_SFSPD_13_MODE_Pos) /*!< SCU SFSPD_13: MODE Mask */ -#define SCU_SFSPD_13_EPD_Pos 3 /*!< SCU SFSPD_13: EPD Position */ -#define SCU_SFSPD_13_EPD_Msk (0x01UL << SCU_SFSPD_13_EPD_Pos) /*!< SCU SFSPD_13: EPD Mask */ -#define SCU_SFSPD_13_EPUN_Pos 4 /*!< SCU SFSPD_13: EPUN Position */ -#define SCU_SFSPD_13_EPUN_Msk (0x01UL << SCU_SFSPD_13_EPUN_Pos) /*!< SCU SFSPD_13: EPUN Mask */ -#define SCU_SFSPD_13_EHS_Pos 5 /*!< SCU SFSPD_13: EHS Position */ -#define SCU_SFSPD_13_EHS_Msk (0x01UL << SCU_SFSPD_13_EHS_Pos) /*!< SCU SFSPD_13: EHS Mask */ -#define SCU_SFSPD_13_EZI_Pos 6 /*!< SCU SFSPD_13: EZI Position */ -#define SCU_SFSPD_13_EZI_Msk (0x01UL << SCU_SFSPD_13_EZI_Pos) /*!< SCU SFSPD_13: EZI Mask */ -#define SCU_SFSPD_13_EHD_Pos 8 /*!< SCU SFSPD_13: EHD Position */ -#define SCU_SFSPD_13_EHD_Msk (0x03UL << SCU_SFSPD_13_EHD_Pos) /*!< SCU SFSPD_13: EHD Mask */ - -// -------------------------------------- SCU_SFSPD_14 ------------------------------------------ -#define SCU_SFSPD_14_MODE_Pos 0 /*!< SCU SFSPD_14: MODE Position */ -#define SCU_SFSPD_14_MODE_Msk (0x07UL << SCU_SFSPD_14_MODE_Pos) /*!< SCU SFSPD_14: MODE Mask */ -#define SCU_SFSPD_14_EPD_Pos 3 /*!< SCU SFSPD_14: EPD Position */ -#define SCU_SFSPD_14_EPD_Msk (0x01UL << SCU_SFSPD_14_EPD_Pos) /*!< SCU SFSPD_14: EPD Mask */ -#define SCU_SFSPD_14_EPUN_Pos 4 /*!< SCU SFSPD_14: EPUN Position */ -#define SCU_SFSPD_14_EPUN_Msk (0x01UL << SCU_SFSPD_14_EPUN_Pos) /*!< SCU SFSPD_14: EPUN Mask */ -#define SCU_SFSPD_14_EHS_Pos 5 /*!< SCU SFSPD_14: EHS Position */ -#define SCU_SFSPD_14_EHS_Msk (0x01UL << SCU_SFSPD_14_EHS_Pos) /*!< SCU SFSPD_14: EHS Mask */ -#define SCU_SFSPD_14_EZI_Pos 6 /*!< SCU SFSPD_14: EZI Position */ -#define SCU_SFSPD_14_EZI_Msk (0x01UL << SCU_SFSPD_14_EZI_Pos) /*!< SCU SFSPD_14: EZI Mask */ -#define SCU_SFSPD_14_EHD_Pos 8 /*!< SCU SFSPD_14: EHD Position */ -#define SCU_SFSPD_14_EHD_Msk (0x03UL << SCU_SFSPD_14_EHD_Pos) /*!< SCU SFSPD_14: EHD Mask */ - -// -------------------------------------- SCU_SFSPD_15 ------------------------------------------ -#define SCU_SFSPD_15_MODE_Pos 0 /*!< SCU SFSPD_15: MODE Position */ -#define SCU_SFSPD_15_MODE_Msk (0x07UL << SCU_SFSPD_15_MODE_Pos) /*!< SCU SFSPD_15: MODE Mask */ -#define SCU_SFSPD_15_EPD_Pos 3 /*!< SCU SFSPD_15: EPD Position */ -#define SCU_SFSPD_15_EPD_Msk (0x01UL << SCU_SFSPD_15_EPD_Pos) /*!< SCU SFSPD_15: EPD Mask */ -#define SCU_SFSPD_15_EPUN_Pos 4 /*!< SCU SFSPD_15: EPUN Position */ -#define SCU_SFSPD_15_EPUN_Msk (0x01UL << SCU_SFSPD_15_EPUN_Pos) /*!< SCU SFSPD_15: EPUN Mask */ -#define SCU_SFSPD_15_EHS_Pos 5 /*!< SCU SFSPD_15: EHS Position */ -#define SCU_SFSPD_15_EHS_Msk (0x01UL << SCU_SFSPD_15_EHS_Pos) /*!< SCU SFSPD_15: EHS Mask */ -#define SCU_SFSPD_15_EZI_Pos 6 /*!< SCU SFSPD_15: EZI Position */ -#define SCU_SFSPD_15_EZI_Msk (0x01UL << SCU_SFSPD_15_EZI_Pos) /*!< SCU SFSPD_15: EZI Mask */ -#define SCU_SFSPD_15_EHD_Pos 8 /*!< SCU SFSPD_15: EHD Position */ -#define SCU_SFSPD_15_EHD_Msk (0x03UL << SCU_SFSPD_15_EHD_Pos) /*!< SCU SFSPD_15: EHD Mask */ - -// -------------------------------------- SCU_SFSPD_16 ------------------------------------------ -#define SCU_SFSPD_16_MODE_Pos 0 /*!< SCU SFSPD_16: MODE Position */ -#define SCU_SFSPD_16_MODE_Msk (0x07UL << SCU_SFSPD_16_MODE_Pos) /*!< SCU SFSPD_16: MODE Mask */ -#define SCU_SFSPD_16_EPD_Pos 3 /*!< SCU SFSPD_16: EPD Position */ -#define SCU_SFSPD_16_EPD_Msk (0x01UL << SCU_SFSPD_16_EPD_Pos) /*!< SCU SFSPD_16: EPD Mask */ -#define SCU_SFSPD_16_EPUN_Pos 4 /*!< SCU SFSPD_16: EPUN Position */ -#define SCU_SFSPD_16_EPUN_Msk (0x01UL << SCU_SFSPD_16_EPUN_Pos) /*!< SCU SFSPD_16: EPUN Mask */ -#define SCU_SFSPD_16_EHS_Pos 5 /*!< SCU SFSPD_16: EHS Position */ -#define SCU_SFSPD_16_EHS_Msk (0x01UL << SCU_SFSPD_16_EHS_Pos) /*!< SCU SFSPD_16: EHS Mask */ -#define SCU_SFSPD_16_EZI_Pos 6 /*!< SCU SFSPD_16: EZI Position */ -#define SCU_SFSPD_16_EZI_Msk (0x01UL << SCU_SFSPD_16_EZI_Pos) /*!< SCU SFSPD_16: EZI Mask */ -#define SCU_SFSPD_16_EHD_Pos 8 /*!< SCU SFSPD_16: EHD Position */ -#define SCU_SFSPD_16_EHD_Msk (0x03UL << SCU_SFSPD_16_EHD_Pos) /*!< SCU SFSPD_16: EHD Mask */ - -// --------------------------------------- SCU_SFSPE_0 ------------------------------------------ -#define SCU_SFSPE_0_MODE_Pos 0 /*!< SCU SFSPE_0: MODE Position */ -#define SCU_SFSPE_0_MODE_Msk (0x07UL << SCU_SFSPE_0_MODE_Pos) /*!< SCU SFSPE_0: MODE Mask */ -#define SCU_SFSPE_0_EPD_Pos 3 /*!< SCU SFSPE_0: EPD Position */ -#define SCU_SFSPE_0_EPD_Msk (0x01UL << SCU_SFSPE_0_EPD_Pos) /*!< SCU SFSPE_0: EPD Mask */ -#define SCU_SFSPE_0_EPUN_Pos 4 /*!< SCU SFSPE_0: EPUN Position */ -#define SCU_SFSPE_0_EPUN_Msk (0x01UL << SCU_SFSPE_0_EPUN_Pos) /*!< SCU SFSPE_0: EPUN Mask */ -#define SCU_SFSPE_0_EHS_Pos 5 /*!< SCU SFSPE_0: EHS Position */ -#define SCU_SFSPE_0_EHS_Msk (0x01UL << SCU_SFSPE_0_EHS_Pos) /*!< SCU SFSPE_0: EHS Mask */ -#define SCU_SFSPE_0_EZI_Pos 6 /*!< SCU SFSPE_0: EZI Position */ -#define SCU_SFSPE_0_EZI_Msk (0x01UL << SCU_SFSPE_0_EZI_Pos) /*!< SCU SFSPE_0: EZI Mask */ -#define SCU_SFSPE_0_EHD_Pos 8 /*!< SCU SFSPE_0: EHD Position */ -#define SCU_SFSPE_0_EHD_Msk (0x03UL << SCU_SFSPE_0_EHD_Pos) /*!< SCU SFSPE_0: EHD Mask */ - -// --------------------------------------- SCU_SFSPE_1 ------------------------------------------ -#define SCU_SFSPE_1_MODE_Pos 0 /*!< SCU SFSPE_1: MODE Position */ -#define SCU_SFSPE_1_MODE_Msk (0x07UL << SCU_SFSPE_1_MODE_Pos) /*!< SCU SFSPE_1: MODE Mask */ -#define SCU_SFSPE_1_EPD_Pos 3 /*!< SCU SFSPE_1: EPD Position */ -#define SCU_SFSPE_1_EPD_Msk (0x01UL << SCU_SFSPE_1_EPD_Pos) /*!< SCU SFSPE_1: EPD Mask */ -#define SCU_SFSPE_1_EPUN_Pos 4 /*!< SCU SFSPE_1: EPUN Position */ -#define SCU_SFSPE_1_EPUN_Msk (0x01UL << SCU_SFSPE_1_EPUN_Pos) /*!< SCU SFSPE_1: EPUN Mask */ -#define SCU_SFSPE_1_EHS_Pos 5 /*!< SCU SFSPE_1: EHS Position */ -#define SCU_SFSPE_1_EHS_Msk (0x01UL << SCU_SFSPE_1_EHS_Pos) /*!< SCU SFSPE_1: EHS Mask */ -#define SCU_SFSPE_1_EZI_Pos 6 /*!< SCU SFSPE_1: EZI Position */ -#define SCU_SFSPE_1_EZI_Msk (0x01UL << SCU_SFSPE_1_EZI_Pos) /*!< SCU SFSPE_1: EZI Mask */ -#define SCU_SFSPE_1_EHD_Pos 8 /*!< SCU SFSPE_1: EHD Position */ -#define SCU_SFSPE_1_EHD_Msk (0x03UL << SCU_SFSPE_1_EHD_Pos) /*!< SCU SFSPE_1: EHD Mask */ - -// --------------------------------------- SCU_SFSPE_2 ------------------------------------------ -#define SCU_SFSPE_2_MODE_Pos 0 /*!< SCU SFSPE_2: MODE Position */ -#define SCU_SFSPE_2_MODE_Msk (0x07UL << SCU_SFSPE_2_MODE_Pos) /*!< SCU SFSPE_2: MODE Mask */ -#define SCU_SFSPE_2_EPD_Pos 3 /*!< SCU SFSPE_2: EPD Position */ -#define SCU_SFSPE_2_EPD_Msk (0x01UL << SCU_SFSPE_2_EPD_Pos) /*!< SCU SFSPE_2: EPD Mask */ -#define SCU_SFSPE_2_EPUN_Pos 4 /*!< SCU SFSPE_2: EPUN Position */ -#define SCU_SFSPE_2_EPUN_Msk (0x01UL << SCU_SFSPE_2_EPUN_Pos) /*!< SCU SFSPE_2: EPUN Mask */ -#define SCU_SFSPE_2_EHS_Pos 5 /*!< SCU SFSPE_2: EHS Position */ -#define SCU_SFSPE_2_EHS_Msk (0x01UL << SCU_SFSPE_2_EHS_Pos) /*!< SCU SFSPE_2: EHS Mask */ -#define SCU_SFSPE_2_EZI_Pos 6 /*!< SCU SFSPE_2: EZI Position */ -#define SCU_SFSPE_2_EZI_Msk (0x01UL << SCU_SFSPE_2_EZI_Pos) /*!< SCU SFSPE_2: EZI Mask */ -#define SCU_SFSPE_2_EHD_Pos 8 /*!< SCU SFSPE_2: EHD Position */ -#define SCU_SFSPE_2_EHD_Msk (0x03UL << SCU_SFSPE_2_EHD_Pos) /*!< SCU SFSPE_2: EHD Mask */ - -// --------------------------------------- SCU_SFSPE_3 ------------------------------------------ -#define SCU_SFSPE_3_MODE_Pos 0 /*!< SCU SFSPE_3: MODE Position */ -#define SCU_SFSPE_3_MODE_Msk (0x07UL << SCU_SFSPE_3_MODE_Pos) /*!< SCU SFSPE_3: MODE Mask */ -#define SCU_SFSPE_3_EPD_Pos 3 /*!< SCU SFSPE_3: EPD Position */ -#define SCU_SFSPE_3_EPD_Msk (0x01UL << SCU_SFSPE_3_EPD_Pos) /*!< SCU SFSPE_3: EPD Mask */ -#define SCU_SFSPE_3_EPUN_Pos 4 /*!< SCU SFSPE_3: EPUN Position */ -#define SCU_SFSPE_3_EPUN_Msk (0x01UL << SCU_SFSPE_3_EPUN_Pos) /*!< SCU SFSPE_3: EPUN Mask */ -#define SCU_SFSPE_3_EHS_Pos 5 /*!< SCU SFSPE_3: EHS Position */ -#define SCU_SFSPE_3_EHS_Msk (0x01UL << SCU_SFSPE_3_EHS_Pos) /*!< SCU SFSPE_3: EHS Mask */ -#define SCU_SFSPE_3_EZI_Pos 6 /*!< SCU SFSPE_3: EZI Position */ -#define SCU_SFSPE_3_EZI_Msk (0x01UL << SCU_SFSPE_3_EZI_Pos) /*!< SCU SFSPE_3: EZI Mask */ -#define SCU_SFSPE_3_EHD_Pos 8 /*!< SCU SFSPE_3: EHD Position */ -#define SCU_SFSPE_3_EHD_Msk (0x03UL << SCU_SFSPE_3_EHD_Pos) /*!< SCU SFSPE_3: EHD Mask */ - -// --------------------------------------- SCU_SFSPE_4 ------------------------------------------ -#define SCU_SFSPE_4_MODE_Pos 0 /*!< SCU SFSPE_4: MODE Position */ -#define SCU_SFSPE_4_MODE_Msk (0x07UL << SCU_SFSPE_4_MODE_Pos) /*!< SCU SFSPE_4: MODE Mask */ -#define SCU_SFSPE_4_EPD_Pos 3 /*!< SCU SFSPE_4: EPD Position */ -#define SCU_SFSPE_4_EPD_Msk (0x01UL << SCU_SFSPE_4_EPD_Pos) /*!< SCU SFSPE_4: EPD Mask */ -#define SCU_SFSPE_4_EPUN_Pos 4 /*!< SCU SFSPE_4: EPUN Position */ -#define SCU_SFSPE_4_EPUN_Msk (0x01UL << SCU_SFSPE_4_EPUN_Pos) /*!< SCU SFSPE_4: EPUN Mask */ -#define SCU_SFSPE_4_EHS_Pos 5 /*!< SCU SFSPE_4: EHS Position */ -#define SCU_SFSPE_4_EHS_Msk (0x01UL << SCU_SFSPE_4_EHS_Pos) /*!< SCU SFSPE_4: EHS Mask */ -#define SCU_SFSPE_4_EZI_Pos 6 /*!< SCU SFSPE_4: EZI Position */ -#define SCU_SFSPE_4_EZI_Msk (0x01UL << SCU_SFSPE_4_EZI_Pos) /*!< SCU SFSPE_4: EZI Mask */ -#define SCU_SFSPE_4_EHD_Pos 8 /*!< SCU SFSPE_4: EHD Position */ -#define SCU_SFSPE_4_EHD_Msk (0x03UL << SCU_SFSPE_4_EHD_Pos) /*!< SCU SFSPE_4: EHD Mask */ - -// --------------------------------------- SCU_SFSPE_5 ------------------------------------------ -#define SCU_SFSPE_5_MODE_Pos 0 /*!< SCU SFSPE_5: MODE Position */ -#define SCU_SFSPE_5_MODE_Msk (0x07UL << SCU_SFSPE_5_MODE_Pos) /*!< SCU SFSPE_5: MODE Mask */ -#define SCU_SFSPE_5_EPD_Pos 3 /*!< SCU SFSPE_5: EPD Position */ -#define SCU_SFSPE_5_EPD_Msk (0x01UL << SCU_SFSPE_5_EPD_Pos) /*!< SCU SFSPE_5: EPD Mask */ -#define SCU_SFSPE_5_EPUN_Pos 4 /*!< SCU SFSPE_5: EPUN Position */ -#define SCU_SFSPE_5_EPUN_Msk (0x01UL << SCU_SFSPE_5_EPUN_Pos) /*!< SCU SFSPE_5: EPUN Mask */ -#define SCU_SFSPE_5_EHS_Pos 5 /*!< SCU SFSPE_5: EHS Position */ -#define SCU_SFSPE_5_EHS_Msk (0x01UL << SCU_SFSPE_5_EHS_Pos) /*!< SCU SFSPE_5: EHS Mask */ -#define SCU_SFSPE_5_EZI_Pos 6 /*!< SCU SFSPE_5: EZI Position */ -#define SCU_SFSPE_5_EZI_Msk (0x01UL << SCU_SFSPE_5_EZI_Pos) /*!< SCU SFSPE_5: EZI Mask */ -#define SCU_SFSPE_5_EHD_Pos 8 /*!< SCU SFSPE_5: EHD Position */ -#define SCU_SFSPE_5_EHD_Msk (0x03UL << SCU_SFSPE_5_EHD_Pos) /*!< SCU SFSPE_5: EHD Mask */ - -// --------------------------------------- SCU_SFSPE_6 ------------------------------------------ -#define SCU_SFSPE_6_MODE_Pos 0 /*!< SCU SFSPE_6: MODE Position */ -#define SCU_SFSPE_6_MODE_Msk (0x07UL << SCU_SFSPE_6_MODE_Pos) /*!< SCU SFSPE_6: MODE Mask */ -#define SCU_SFSPE_6_EPD_Pos 3 /*!< SCU SFSPE_6: EPD Position */ -#define SCU_SFSPE_6_EPD_Msk (0x01UL << SCU_SFSPE_6_EPD_Pos) /*!< SCU SFSPE_6: EPD Mask */ -#define SCU_SFSPE_6_EPUN_Pos 4 /*!< SCU SFSPE_6: EPUN Position */ -#define SCU_SFSPE_6_EPUN_Msk (0x01UL << SCU_SFSPE_6_EPUN_Pos) /*!< SCU SFSPE_6: EPUN Mask */ -#define SCU_SFSPE_6_EHS_Pos 5 /*!< SCU SFSPE_6: EHS Position */ -#define SCU_SFSPE_6_EHS_Msk (0x01UL << SCU_SFSPE_6_EHS_Pos) /*!< SCU SFSPE_6: EHS Mask */ -#define SCU_SFSPE_6_EZI_Pos 6 /*!< SCU SFSPE_6: EZI Position */ -#define SCU_SFSPE_6_EZI_Msk (0x01UL << SCU_SFSPE_6_EZI_Pos) /*!< SCU SFSPE_6: EZI Mask */ -#define SCU_SFSPE_6_EHD_Pos 8 /*!< SCU SFSPE_6: EHD Position */ -#define SCU_SFSPE_6_EHD_Msk (0x03UL << SCU_SFSPE_6_EHD_Pos) /*!< SCU SFSPE_6: EHD Mask */ - -// --------------------------------------- SCU_SFSPE_7 ------------------------------------------ -#define SCU_SFSPE_7_MODE_Pos 0 /*!< SCU SFSPE_7: MODE Position */ -#define SCU_SFSPE_7_MODE_Msk (0x07UL << SCU_SFSPE_7_MODE_Pos) /*!< SCU SFSPE_7: MODE Mask */ -#define SCU_SFSPE_7_EPD_Pos 3 /*!< SCU SFSPE_7: EPD Position */ -#define SCU_SFSPE_7_EPD_Msk (0x01UL << SCU_SFSPE_7_EPD_Pos) /*!< SCU SFSPE_7: EPD Mask */ -#define SCU_SFSPE_7_EPUN_Pos 4 /*!< SCU SFSPE_7: EPUN Position */ -#define SCU_SFSPE_7_EPUN_Msk (0x01UL << SCU_SFSPE_7_EPUN_Pos) /*!< SCU SFSPE_7: EPUN Mask */ -#define SCU_SFSPE_7_EHS_Pos 5 /*!< SCU SFSPE_7: EHS Position */ -#define SCU_SFSPE_7_EHS_Msk (0x01UL << SCU_SFSPE_7_EHS_Pos) /*!< SCU SFSPE_7: EHS Mask */ -#define SCU_SFSPE_7_EZI_Pos 6 /*!< SCU SFSPE_7: EZI Position */ -#define SCU_SFSPE_7_EZI_Msk (0x01UL << SCU_SFSPE_7_EZI_Pos) /*!< SCU SFSPE_7: EZI Mask */ -#define SCU_SFSPE_7_EHD_Pos 8 /*!< SCU SFSPE_7: EHD Position */ -#define SCU_SFSPE_7_EHD_Msk (0x03UL << SCU_SFSPE_7_EHD_Pos) /*!< SCU SFSPE_7: EHD Mask */ - -// --------------------------------------- SCU_SFSPE_8 ------------------------------------------ -#define SCU_SFSPE_8_MODE_Pos 0 /*!< SCU SFSPE_8: MODE Position */ -#define SCU_SFSPE_8_MODE_Msk (0x07UL << SCU_SFSPE_8_MODE_Pos) /*!< SCU SFSPE_8: MODE Mask */ -#define SCU_SFSPE_8_EPD_Pos 3 /*!< SCU SFSPE_8: EPD Position */ -#define SCU_SFSPE_8_EPD_Msk (0x01UL << SCU_SFSPE_8_EPD_Pos) /*!< SCU SFSPE_8: EPD Mask */ -#define SCU_SFSPE_8_EPUN_Pos 4 /*!< SCU SFSPE_8: EPUN Position */ -#define SCU_SFSPE_8_EPUN_Msk (0x01UL << SCU_SFSPE_8_EPUN_Pos) /*!< SCU SFSPE_8: EPUN Mask */ -#define SCU_SFSPE_8_EHS_Pos 5 /*!< SCU SFSPE_8: EHS Position */ -#define SCU_SFSPE_8_EHS_Msk (0x01UL << SCU_SFSPE_8_EHS_Pos) /*!< SCU SFSPE_8: EHS Mask */ -#define SCU_SFSPE_8_EZI_Pos 6 /*!< SCU SFSPE_8: EZI Position */ -#define SCU_SFSPE_8_EZI_Msk (0x01UL << SCU_SFSPE_8_EZI_Pos) /*!< SCU SFSPE_8: EZI Mask */ -#define SCU_SFSPE_8_EHD_Pos 8 /*!< SCU SFSPE_8: EHD Position */ -#define SCU_SFSPE_8_EHD_Msk (0x03UL << SCU_SFSPE_8_EHD_Pos) /*!< SCU SFSPE_8: EHD Mask */ - -// --------------------------------------- SCU_SFSPE_9 ------------------------------------------ -#define SCU_SFSPE_9_MODE_Pos 0 /*!< SCU SFSPE_9: MODE Position */ -#define SCU_SFSPE_9_MODE_Msk (0x07UL << SCU_SFSPE_9_MODE_Pos) /*!< SCU SFSPE_9: MODE Mask */ -#define SCU_SFSPE_9_EPD_Pos 3 /*!< SCU SFSPE_9: EPD Position */ -#define SCU_SFSPE_9_EPD_Msk (0x01UL << SCU_SFSPE_9_EPD_Pos) /*!< SCU SFSPE_9: EPD Mask */ -#define SCU_SFSPE_9_EPUN_Pos 4 /*!< SCU SFSPE_9: EPUN Position */ -#define SCU_SFSPE_9_EPUN_Msk (0x01UL << SCU_SFSPE_9_EPUN_Pos) /*!< SCU SFSPE_9: EPUN Mask */ -#define SCU_SFSPE_9_EHS_Pos 5 /*!< SCU SFSPE_9: EHS Position */ -#define SCU_SFSPE_9_EHS_Msk (0x01UL << SCU_SFSPE_9_EHS_Pos) /*!< SCU SFSPE_9: EHS Mask */ -#define SCU_SFSPE_9_EZI_Pos 6 /*!< SCU SFSPE_9: EZI Position */ -#define SCU_SFSPE_9_EZI_Msk (0x01UL << SCU_SFSPE_9_EZI_Pos) /*!< SCU SFSPE_9: EZI Mask */ -#define SCU_SFSPE_9_EHD_Pos 8 /*!< SCU SFSPE_9: EHD Position */ -#define SCU_SFSPE_9_EHD_Msk (0x03UL << SCU_SFSPE_9_EHD_Pos) /*!< SCU SFSPE_9: EHD Mask */ - -// -------------------------------------- SCU_SFSPE_10 ------------------------------------------ -#define SCU_SFSPE_10_MODE_Pos 0 /*!< SCU SFSPE_10: MODE Position */ -#define SCU_SFSPE_10_MODE_Msk (0x07UL << SCU_SFSPE_10_MODE_Pos) /*!< SCU SFSPE_10: MODE Mask */ -#define SCU_SFSPE_10_EPD_Pos 3 /*!< SCU SFSPE_10: EPD Position */ -#define SCU_SFSPE_10_EPD_Msk (0x01UL << SCU_SFSPE_10_EPD_Pos) /*!< SCU SFSPE_10: EPD Mask */ -#define SCU_SFSPE_10_EPUN_Pos 4 /*!< SCU SFSPE_10: EPUN Position */ -#define SCU_SFSPE_10_EPUN_Msk (0x01UL << SCU_SFSPE_10_EPUN_Pos) /*!< SCU SFSPE_10: EPUN Mask */ -#define SCU_SFSPE_10_EHS_Pos 5 /*!< SCU SFSPE_10: EHS Position */ -#define SCU_SFSPE_10_EHS_Msk (0x01UL << SCU_SFSPE_10_EHS_Pos) /*!< SCU SFSPE_10: EHS Mask */ -#define SCU_SFSPE_10_EZI_Pos 6 /*!< SCU SFSPE_10: EZI Position */ -#define SCU_SFSPE_10_EZI_Msk (0x01UL << SCU_SFSPE_10_EZI_Pos) /*!< SCU SFSPE_10: EZI Mask */ -#define SCU_SFSPE_10_EHD_Pos 8 /*!< SCU SFSPE_10: EHD Position */ -#define SCU_SFSPE_10_EHD_Msk (0x03UL << SCU_SFSPE_10_EHD_Pos) /*!< SCU SFSPE_10: EHD Mask */ - -// -------------------------------------- SCU_SFSPE_11 ------------------------------------------ -#define SCU_SFSPE_11_MODE_Pos 0 /*!< SCU SFSPE_11: MODE Position */ -#define SCU_SFSPE_11_MODE_Msk (0x07UL << SCU_SFSPE_11_MODE_Pos) /*!< SCU SFSPE_11: MODE Mask */ -#define SCU_SFSPE_11_EPD_Pos 3 /*!< SCU SFSPE_11: EPD Position */ -#define SCU_SFSPE_11_EPD_Msk (0x01UL << SCU_SFSPE_11_EPD_Pos) /*!< SCU SFSPE_11: EPD Mask */ -#define SCU_SFSPE_11_EPUN_Pos 4 /*!< SCU SFSPE_11: EPUN Position */ -#define SCU_SFSPE_11_EPUN_Msk (0x01UL << SCU_SFSPE_11_EPUN_Pos) /*!< SCU SFSPE_11: EPUN Mask */ -#define SCU_SFSPE_11_EHS_Pos 5 /*!< SCU SFSPE_11: EHS Position */ -#define SCU_SFSPE_11_EHS_Msk (0x01UL << SCU_SFSPE_11_EHS_Pos) /*!< SCU SFSPE_11: EHS Mask */ -#define SCU_SFSPE_11_EZI_Pos 6 /*!< SCU SFSPE_11: EZI Position */ -#define SCU_SFSPE_11_EZI_Msk (0x01UL << SCU_SFSPE_11_EZI_Pos) /*!< SCU SFSPE_11: EZI Mask */ -#define SCU_SFSPE_11_EHD_Pos 8 /*!< SCU SFSPE_11: EHD Position */ -#define SCU_SFSPE_11_EHD_Msk (0x03UL << SCU_SFSPE_11_EHD_Pos) /*!< SCU SFSPE_11: EHD Mask */ - -// -------------------------------------- SCU_SFSPE_12 ------------------------------------------ -#define SCU_SFSPE_12_MODE_Pos 0 /*!< SCU SFSPE_12: MODE Position */ -#define SCU_SFSPE_12_MODE_Msk (0x07UL << SCU_SFSPE_12_MODE_Pos) /*!< SCU SFSPE_12: MODE Mask */ -#define SCU_SFSPE_12_EPD_Pos 3 /*!< SCU SFSPE_12: EPD Position */ -#define SCU_SFSPE_12_EPD_Msk (0x01UL << SCU_SFSPE_12_EPD_Pos) /*!< SCU SFSPE_12: EPD Mask */ -#define SCU_SFSPE_12_EPUN_Pos 4 /*!< SCU SFSPE_12: EPUN Position */ -#define SCU_SFSPE_12_EPUN_Msk (0x01UL << SCU_SFSPE_12_EPUN_Pos) /*!< SCU SFSPE_12: EPUN Mask */ -#define SCU_SFSPE_12_EHS_Pos 5 /*!< SCU SFSPE_12: EHS Position */ -#define SCU_SFSPE_12_EHS_Msk (0x01UL << SCU_SFSPE_12_EHS_Pos) /*!< SCU SFSPE_12: EHS Mask */ -#define SCU_SFSPE_12_EZI_Pos 6 /*!< SCU SFSPE_12: EZI Position */ -#define SCU_SFSPE_12_EZI_Msk (0x01UL << SCU_SFSPE_12_EZI_Pos) /*!< SCU SFSPE_12: EZI Mask */ -#define SCU_SFSPE_12_EHD_Pos 8 /*!< SCU SFSPE_12: EHD Position */ -#define SCU_SFSPE_12_EHD_Msk (0x03UL << SCU_SFSPE_12_EHD_Pos) /*!< SCU SFSPE_12: EHD Mask */ - -// -------------------------------------- SCU_SFSPE_13 ------------------------------------------ -#define SCU_SFSPE_13_MODE_Pos 0 /*!< SCU SFSPE_13: MODE Position */ -#define SCU_SFSPE_13_MODE_Msk (0x07UL << SCU_SFSPE_13_MODE_Pos) /*!< SCU SFSPE_13: MODE Mask */ -#define SCU_SFSPE_13_EPD_Pos 3 /*!< SCU SFSPE_13: EPD Position */ -#define SCU_SFSPE_13_EPD_Msk (0x01UL << SCU_SFSPE_13_EPD_Pos) /*!< SCU SFSPE_13: EPD Mask */ -#define SCU_SFSPE_13_EPUN_Pos 4 /*!< SCU SFSPE_13: EPUN Position */ -#define SCU_SFSPE_13_EPUN_Msk (0x01UL << SCU_SFSPE_13_EPUN_Pos) /*!< SCU SFSPE_13: EPUN Mask */ -#define SCU_SFSPE_13_EHS_Pos 5 /*!< SCU SFSPE_13: EHS Position */ -#define SCU_SFSPE_13_EHS_Msk (0x01UL << SCU_SFSPE_13_EHS_Pos) /*!< SCU SFSPE_13: EHS Mask */ -#define SCU_SFSPE_13_EZI_Pos 6 /*!< SCU SFSPE_13: EZI Position */ -#define SCU_SFSPE_13_EZI_Msk (0x01UL << SCU_SFSPE_13_EZI_Pos) /*!< SCU SFSPE_13: EZI Mask */ -#define SCU_SFSPE_13_EHD_Pos 8 /*!< SCU SFSPE_13: EHD Position */ -#define SCU_SFSPE_13_EHD_Msk (0x03UL << SCU_SFSPE_13_EHD_Pos) /*!< SCU SFSPE_13: EHD Mask */ - -// -------------------------------------- SCU_SFSPE_14 ------------------------------------------ -#define SCU_SFSPE_14_MODE_Pos 0 /*!< SCU SFSPE_14: MODE Position */ -#define SCU_SFSPE_14_MODE_Msk (0x07UL << SCU_SFSPE_14_MODE_Pos) /*!< SCU SFSPE_14: MODE Mask */ -#define SCU_SFSPE_14_EPD_Pos 3 /*!< SCU SFSPE_14: EPD Position */ -#define SCU_SFSPE_14_EPD_Msk (0x01UL << SCU_SFSPE_14_EPD_Pos) /*!< SCU SFSPE_14: EPD Mask */ -#define SCU_SFSPE_14_EPUN_Pos 4 /*!< SCU SFSPE_14: EPUN Position */ -#define SCU_SFSPE_14_EPUN_Msk (0x01UL << SCU_SFSPE_14_EPUN_Pos) /*!< SCU SFSPE_14: EPUN Mask */ -#define SCU_SFSPE_14_EHS_Pos 5 /*!< SCU SFSPE_14: EHS Position */ -#define SCU_SFSPE_14_EHS_Msk (0x01UL << SCU_SFSPE_14_EHS_Pos) /*!< SCU SFSPE_14: EHS Mask */ -#define SCU_SFSPE_14_EZI_Pos 6 /*!< SCU SFSPE_14: EZI Position */ -#define SCU_SFSPE_14_EZI_Msk (0x01UL << SCU_SFSPE_14_EZI_Pos) /*!< SCU SFSPE_14: EZI Mask */ -#define SCU_SFSPE_14_EHD_Pos 8 /*!< SCU SFSPE_14: EHD Position */ -#define SCU_SFSPE_14_EHD_Msk (0x03UL << SCU_SFSPE_14_EHD_Pos) /*!< SCU SFSPE_14: EHD Mask */ - -// -------------------------------------- SCU_SFSPE_15 ------------------------------------------ -#define SCU_SFSPE_15_MODE_Pos 0 /*!< SCU SFSPE_15: MODE Position */ -#define SCU_SFSPE_15_MODE_Msk (0x07UL << SCU_SFSPE_15_MODE_Pos) /*!< SCU SFSPE_15: MODE Mask */ -#define SCU_SFSPE_15_EPD_Pos 3 /*!< SCU SFSPE_15: EPD Position */ -#define SCU_SFSPE_15_EPD_Msk (0x01UL << SCU_SFSPE_15_EPD_Pos) /*!< SCU SFSPE_15: EPD Mask */ -#define SCU_SFSPE_15_EPUN_Pos 4 /*!< SCU SFSPE_15: EPUN Position */ -#define SCU_SFSPE_15_EPUN_Msk (0x01UL << SCU_SFSPE_15_EPUN_Pos) /*!< SCU SFSPE_15: EPUN Mask */ -#define SCU_SFSPE_15_EHS_Pos 5 /*!< SCU SFSPE_15: EHS Position */ -#define SCU_SFSPE_15_EHS_Msk (0x01UL << SCU_SFSPE_15_EHS_Pos) /*!< SCU SFSPE_15: EHS Mask */ -#define SCU_SFSPE_15_EZI_Pos 6 /*!< SCU SFSPE_15: EZI Position */ -#define SCU_SFSPE_15_EZI_Msk (0x01UL << SCU_SFSPE_15_EZI_Pos) /*!< SCU SFSPE_15: EZI Mask */ -#define SCU_SFSPE_15_EHD_Pos 8 /*!< SCU SFSPE_15: EHD Position */ -#define SCU_SFSPE_15_EHD_Msk (0x03UL << SCU_SFSPE_15_EHD_Pos) /*!< SCU SFSPE_15: EHD Mask */ - -// --------------------------------------- SCU_SFSPF_0 ------------------------------------------ -#define SCU_SFSPF_0_MODE_Pos 0 /*!< SCU SFSPF_0: MODE Position */ -#define SCU_SFSPF_0_MODE_Msk (0x07UL << SCU_SFSPF_0_MODE_Pos) /*!< SCU SFSPF_0: MODE Mask */ -#define SCU_SFSPF_0_EPD_Pos 3 /*!< SCU SFSPF_0: EPD Position */ -#define SCU_SFSPF_0_EPD_Msk (0x01UL << SCU_SFSPF_0_EPD_Pos) /*!< SCU SFSPF_0: EPD Mask */ -#define SCU_SFSPF_0_EPUN_Pos 4 /*!< SCU SFSPF_0: EPUN Position */ -#define SCU_SFSPF_0_EPUN_Msk (0x01UL << SCU_SFSPF_0_EPUN_Pos) /*!< SCU SFSPF_0: EPUN Mask */ -#define SCU_SFSPF_0_EHS_Pos 5 /*!< SCU SFSPF_0: EHS Position */ -#define SCU_SFSPF_0_EHS_Msk (0x01UL << SCU_SFSPF_0_EHS_Pos) /*!< SCU SFSPF_0: EHS Mask */ -#define SCU_SFSPF_0_EZI_Pos 6 /*!< SCU SFSPF_0: EZI Position */ -#define SCU_SFSPF_0_EZI_Msk (0x01UL << SCU_SFSPF_0_EZI_Pos) /*!< SCU SFSPF_0: EZI Mask */ -#define SCU_SFSPF_0_EHD_Pos 8 /*!< SCU SFSPF_0: EHD Position */ -#define SCU_SFSPF_0_EHD_Msk (0x03UL << SCU_SFSPF_0_EHD_Pos) /*!< SCU SFSPF_0: EHD Mask */ - -// --------------------------------------- SCU_SFSPF_1 ------------------------------------------ -#define SCU_SFSPF_1_MODE_Pos 0 /*!< SCU SFSPF_1: MODE Position */ -#define SCU_SFSPF_1_MODE_Msk (0x07UL << SCU_SFSPF_1_MODE_Pos) /*!< SCU SFSPF_1: MODE Mask */ -#define SCU_SFSPF_1_EPD_Pos 3 /*!< SCU SFSPF_1: EPD Position */ -#define SCU_SFSPF_1_EPD_Msk (0x01UL << SCU_SFSPF_1_EPD_Pos) /*!< SCU SFSPF_1: EPD Mask */ -#define SCU_SFSPF_1_EPUN_Pos 4 /*!< SCU SFSPF_1: EPUN Position */ -#define SCU_SFSPF_1_EPUN_Msk (0x01UL << SCU_SFSPF_1_EPUN_Pos) /*!< SCU SFSPF_1: EPUN Mask */ -#define SCU_SFSPF_1_EHS_Pos 5 /*!< SCU SFSPF_1: EHS Position */ -#define SCU_SFSPF_1_EHS_Msk (0x01UL << SCU_SFSPF_1_EHS_Pos) /*!< SCU SFSPF_1: EHS Mask */ -#define SCU_SFSPF_1_EZI_Pos 6 /*!< SCU SFSPF_1: EZI Position */ -#define SCU_SFSPF_1_EZI_Msk (0x01UL << SCU_SFSPF_1_EZI_Pos) /*!< SCU SFSPF_1: EZI Mask */ -#define SCU_SFSPF_1_EHD_Pos 8 /*!< SCU SFSPF_1: EHD Position */ -#define SCU_SFSPF_1_EHD_Msk (0x03UL << SCU_SFSPF_1_EHD_Pos) /*!< SCU SFSPF_1: EHD Mask */ - -// --------------------------------------- SCU_SFSPF_2 ------------------------------------------ -#define SCU_SFSPF_2_MODE_Pos 0 /*!< SCU SFSPF_2: MODE Position */ -#define SCU_SFSPF_2_MODE_Msk (0x07UL << SCU_SFSPF_2_MODE_Pos) /*!< SCU SFSPF_2: MODE Mask */ -#define SCU_SFSPF_2_EPD_Pos 3 /*!< SCU SFSPF_2: EPD Position */ -#define SCU_SFSPF_2_EPD_Msk (0x01UL << SCU_SFSPF_2_EPD_Pos) /*!< SCU SFSPF_2: EPD Mask */ -#define SCU_SFSPF_2_EPUN_Pos 4 /*!< SCU SFSPF_2: EPUN Position */ -#define SCU_SFSPF_2_EPUN_Msk (0x01UL << SCU_SFSPF_2_EPUN_Pos) /*!< SCU SFSPF_2: EPUN Mask */ -#define SCU_SFSPF_2_EHS_Pos 5 /*!< SCU SFSPF_2: EHS Position */ -#define SCU_SFSPF_2_EHS_Msk (0x01UL << SCU_SFSPF_2_EHS_Pos) /*!< SCU SFSPF_2: EHS Mask */ -#define SCU_SFSPF_2_EZI_Pos 6 /*!< SCU SFSPF_2: EZI Position */ -#define SCU_SFSPF_2_EZI_Msk (0x01UL << SCU_SFSPF_2_EZI_Pos) /*!< SCU SFSPF_2: EZI Mask */ -#define SCU_SFSPF_2_EHD_Pos 8 /*!< SCU SFSPF_2: EHD Position */ -#define SCU_SFSPF_2_EHD_Msk (0x03UL << SCU_SFSPF_2_EHD_Pos) /*!< SCU SFSPF_2: EHD Mask */ - -// --------------------------------------- SCU_SFSPF_3 ------------------------------------------ -#define SCU_SFSPF_3_MODE_Pos 0 /*!< SCU SFSPF_3: MODE Position */ -#define SCU_SFSPF_3_MODE_Msk (0x07UL << SCU_SFSPF_3_MODE_Pos) /*!< SCU SFSPF_3: MODE Mask */ -#define SCU_SFSPF_3_EPD_Pos 3 /*!< SCU SFSPF_3: EPD Position */ -#define SCU_SFSPF_3_EPD_Msk (0x01UL << SCU_SFSPF_3_EPD_Pos) /*!< SCU SFSPF_3: EPD Mask */ -#define SCU_SFSPF_3_EPUN_Pos 4 /*!< SCU SFSPF_3: EPUN Position */ -#define SCU_SFSPF_3_EPUN_Msk (0x01UL << SCU_SFSPF_3_EPUN_Pos) /*!< SCU SFSPF_3: EPUN Mask */ -#define SCU_SFSPF_3_EHS_Pos 5 /*!< SCU SFSPF_3: EHS Position */ -#define SCU_SFSPF_3_EHS_Msk (0x01UL << SCU_SFSPF_3_EHS_Pos) /*!< SCU SFSPF_3: EHS Mask */ -#define SCU_SFSPF_3_EZI_Pos 6 /*!< SCU SFSPF_3: EZI Position */ -#define SCU_SFSPF_3_EZI_Msk (0x01UL << SCU_SFSPF_3_EZI_Pos) /*!< SCU SFSPF_3: EZI Mask */ -#define SCU_SFSPF_3_EHD_Pos 8 /*!< SCU SFSPF_3: EHD Position */ -#define SCU_SFSPF_3_EHD_Msk (0x03UL << SCU_SFSPF_3_EHD_Pos) /*!< SCU SFSPF_3: EHD Mask */ - -// --------------------------------------- SCU_SFSPF_4 ------------------------------------------ -#define SCU_SFSPF_4_MODE_Pos 0 /*!< SCU SFSPF_4: MODE Position */ -#define SCU_SFSPF_4_MODE_Msk (0x07UL << SCU_SFSPF_4_MODE_Pos) /*!< SCU SFSPF_4: MODE Mask */ -#define SCU_SFSPF_4_EPD_Pos 3 /*!< SCU SFSPF_4: EPD Position */ -#define SCU_SFSPF_4_EPD_Msk (0x01UL << SCU_SFSPF_4_EPD_Pos) /*!< SCU SFSPF_4: EPD Mask */ -#define SCU_SFSPF_4_EPUN_Pos 4 /*!< SCU SFSPF_4: EPUN Position */ -#define SCU_SFSPF_4_EPUN_Msk (0x01UL << SCU_SFSPF_4_EPUN_Pos) /*!< SCU SFSPF_4: EPUN Mask */ -#define SCU_SFSPF_4_EHS_Pos 5 /*!< SCU SFSPF_4: EHS Position */ -#define SCU_SFSPF_4_EHS_Msk (0x01UL << SCU_SFSPF_4_EHS_Pos) /*!< SCU SFSPF_4: EHS Mask */ -#define SCU_SFSPF_4_EZI_Pos 6 /*!< SCU SFSPF_4: EZI Position */ -#define SCU_SFSPF_4_EZI_Msk (0x01UL << SCU_SFSPF_4_EZI_Pos) /*!< SCU SFSPF_4: EZI Mask */ -#define SCU_SFSPF_4_EHD_Pos 8 /*!< SCU SFSPF_4: EHD Position */ -#define SCU_SFSPF_4_EHD_Msk (0x03UL << SCU_SFSPF_4_EHD_Pos) /*!< SCU SFSPF_4: EHD Mask */ - -// --------------------------------------- SCU_SFSPF_5 ------------------------------------------ -#define SCU_SFSPF_5_MODE_Pos 0 /*!< SCU SFSPF_5: MODE Position */ -#define SCU_SFSPF_5_MODE_Msk (0x07UL << SCU_SFSPF_5_MODE_Pos) /*!< SCU SFSPF_5: MODE Mask */ -#define SCU_SFSPF_5_EPD_Pos 3 /*!< SCU SFSPF_5: EPD Position */ -#define SCU_SFSPF_5_EPD_Msk (0x01UL << SCU_SFSPF_5_EPD_Pos) /*!< SCU SFSPF_5: EPD Mask */ -#define SCU_SFSPF_5_EPUN_Pos 4 /*!< SCU SFSPF_5: EPUN Position */ -#define SCU_SFSPF_5_EPUN_Msk (0x01UL << SCU_SFSPF_5_EPUN_Pos) /*!< SCU SFSPF_5: EPUN Mask */ -#define SCU_SFSPF_5_EHS_Pos 5 /*!< SCU SFSPF_5: EHS Position */ -#define SCU_SFSPF_5_EHS_Msk (0x01UL << SCU_SFSPF_5_EHS_Pos) /*!< SCU SFSPF_5: EHS Mask */ -#define SCU_SFSPF_5_EZI_Pos 6 /*!< SCU SFSPF_5: EZI Position */ -#define SCU_SFSPF_5_EZI_Msk (0x01UL << SCU_SFSPF_5_EZI_Pos) /*!< SCU SFSPF_5: EZI Mask */ -#define SCU_SFSPF_5_EHD_Pos 8 /*!< SCU SFSPF_5: EHD Position */ -#define SCU_SFSPF_5_EHD_Msk (0x03UL << SCU_SFSPF_5_EHD_Pos) /*!< SCU SFSPF_5: EHD Mask */ - -// --------------------------------------- SCU_SFSPF_6 ------------------------------------------ -#define SCU_SFSPF_6_MODE_Pos 0 /*!< SCU SFSPF_6: MODE Position */ -#define SCU_SFSPF_6_MODE_Msk (0x07UL << SCU_SFSPF_6_MODE_Pos) /*!< SCU SFSPF_6: MODE Mask */ -#define SCU_SFSPF_6_EPD_Pos 3 /*!< SCU SFSPF_6: EPD Position */ -#define SCU_SFSPF_6_EPD_Msk (0x01UL << SCU_SFSPF_6_EPD_Pos) /*!< SCU SFSPF_6: EPD Mask */ -#define SCU_SFSPF_6_EPUN_Pos 4 /*!< SCU SFSPF_6: EPUN Position */ -#define SCU_SFSPF_6_EPUN_Msk (0x01UL << SCU_SFSPF_6_EPUN_Pos) /*!< SCU SFSPF_6: EPUN Mask */ -#define SCU_SFSPF_6_EHS_Pos 5 /*!< SCU SFSPF_6: EHS Position */ -#define SCU_SFSPF_6_EHS_Msk (0x01UL << SCU_SFSPF_6_EHS_Pos) /*!< SCU SFSPF_6: EHS Mask */ -#define SCU_SFSPF_6_EZI_Pos 6 /*!< SCU SFSPF_6: EZI Position */ -#define SCU_SFSPF_6_EZI_Msk (0x01UL << SCU_SFSPF_6_EZI_Pos) /*!< SCU SFSPF_6: EZI Mask */ -#define SCU_SFSPF_6_EHD_Pos 8 /*!< SCU SFSPF_6: EHD Position */ -#define SCU_SFSPF_6_EHD_Msk (0x03UL << SCU_SFSPF_6_EHD_Pos) /*!< SCU SFSPF_6: EHD Mask */ - -// --------------------------------------- SCU_SFSPF_7 ------------------------------------------ -#define SCU_SFSPF_7_MODE_Pos 0 /*!< SCU SFSPF_7: MODE Position */ -#define SCU_SFSPF_7_MODE_Msk (0x07UL << SCU_SFSPF_7_MODE_Pos) /*!< SCU SFSPF_7: MODE Mask */ -#define SCU_SFSPF_7_EPD_Pos 3 /*!< SCU SFSPF_7: EPD Position */ -#define SCU_SFSPF_7_EPD_Msk (0x01UL << SCU_SFSPF_7_EPD_Pos) /*!< SCU SFSPF_7: EPD Mask */ -#define SCU_SFSPF_7_EPUN_Pos 4 /*!< SCU SFSPF_7: EPUN Position */ -#define SCU_SFSPF_7_EPUN_Msk (0x01UL << SCU_SFSPF_7_EPUN_Pos) /*!< SCU SFSPF_7: EPUN Mask */ -#define SCU_SFSPF_7_EHS_Pos 5 /*!< SCU SFSPF_7: EHS Position */ -#define SCU_SFSPF_7_EHS_Msk (0x01UL << SCU_SFSPF_7_EHS_Pos) /*!< SCU SFSPF_7: EHS Mask */ -#define SCU_SFSPF_7_EZI_Pos 6 /*!< SCU SFSPF_7: EZI Position */ -#define SCU_SFSPF_7_EZI_Msk (0x01UL << SCU_SFSPF_7_EZI_Pos) /*!< SCU SFSPF_7: EZI Mask */ -#define SCU_SFSPF_7_EHD_Pos 8 /*!< SCU SFSPF_7: EHD Position */ -#define SCU_SFSPF_7_EHD_Msk (0x03UL << SCU_SFSPF_7_EHD_Pos) /*!< SCU SFSPF_7: EHD Mask */ - -// --------------------------------------- SCU_SFSPF_8 ------------------------------------------ -#define SCU_SFSPF_8_MODE_Pos 0 /*!< SCU SFSPF_8: MODE Position */ -#define SCU_SFSPF_8_MODE_Msk (0x07UL << SCU_SFSPF_8_MODE_Pos) /*!< SCU SFSPF_8: MODE Mask */ -#define SCU_SFSPF_8_EPD_Pos 3 /*!< SCU SFSPF_8: EPD Position */ -#define SCU_SFSPF_8_EPD_Msk (0x01UL << SCU_SFSPF_8_EPD_Pos) /*!< SCU SFSPF_8: EPD Mask */ -#define SCU_SFSPF_8_EPUN_Pos 4 /*!< SCU SFSPF_8: EPUN Position */ -#define SCU_SFSPF_8_EPUN_Msk (0x01UL << SCU_SFSPF_8_EPUN_Pos) /*!< SCU SFSPF_8: EPUN Mask */ -#define SCU_SFSPF_8_EHS_Pos 5 /*!< SCU SFSPF_8: EHS Position */ -#define SCU_SFSPF_8_EHS_Msk (0x01UL << SCU_SFSPF_8_EHS_Pos) /*!< SCU SFSPF_8: EHS Mask */ -#define SCU_SFSPF_8_EZI_Pos 6 /*!< SCU SFSPF_8: EZI Position */ -#define SCU_SFSPF_8_EZI_Msk (0x01UL << SCU_SFSPF_8_EZI_Pos) /*!< SCU SFSPF_8: EZI Mask */ -#define SCU_SFSPF_8_EHD_Pos 8 /*!< SCU SFSPF_8: EHD Position */ -#define SCU_SFSPF_8_EHD_Msk (0x03UL << SCU_SFSPF_8_EHD_Pos) /*!< SCU SFSPF_8: EHD Mask */ - -// --------------------------------------- SCU_SFSPF_9 ------------------------------------------ -#define SCU_SFSPF_9_MODE_Pos 0 /*!< SCU SFSPF_9: MODE Position */ -#define SCU_SFSPF_9_MODE_Msk (0x07UL << SCU_SFSPF_9_MODE_Pos) /*!< SCU SFSPF_9: MODE Mask */ -#define SCU_SFSPF_9_EPD_Pos 3 /*!< SCU SFSPF_9: EPD Position */ -#define SCU_SFSPF_9_EPD_Msk (0x01UL << SCU_SFSPF_9_EPD_Pos) /*!< SCU SFSPF_9: EPD Mask */ -#define SCU_SFSPF_9_EPUN_Pos 4 /*!< SCU SFSPF_9: EPUN Position */ -#define SCU_SFSPF_9_EPUN_Msk (0x01UL << SCU_SFSPF_9_EPUN_Pos) /*!< SCU SFSPF_9: EPUN Mask */ -#define SCU_SFSPF_9_EHS_Pos 5 /*!< SCU SFSPF_9: EHS Position */ -#define SCU_SFSPF_9_EHS_Msk (0x01UL << SCU_SFSPF_9_EHS_Pos) /*!< SCU SFSPF_9: EHS Mask */ -#define SCU_SFSPF_9_EZI_Pos 6 /*!< SCU SFSPF_9: EZI Position */ -#define SCU_SFSPF_9_EZI_Msk (0x01UL << SCU_SFSPF_9_EZI_Pos) /*!< SCU SFSPF_9: EZI Mask */ -#define SCU_SFSPF_9_EHD_Pos 8 /*!< SCU SFSPF_9: EHD Position */ -#define SCU_SFSPF_9_EHD_Msk (0x03UL << SCU_SFSPF_9_EHD_Pos) /*!< SCU SFSPF_9: EHD Mask */ - -// -------------------------------------- SCU_SFSPF_10 ------------------------------------------ -#define SCU_SFSPF_10_MODE_Pos 0 /*!< SCU SFSPF_10: MODE Position */ -#define SCU_SFSPF_10_MODE_Msk (0x07UL << SCU_SFSPF_10_MODE_Pos) /*!< SCU SFSPF_10: MODE Mask */ -#define SCU_SFSPF_10_EPD_Pos 3 /*!< SCU SFSPF_10: EPD Position */ -#define SCU_SFSPF_10_EPD_Msk (0x01UL << SCU_SFSPF_10_EPD_Pos) /*!< SCU SFSPF_10: EPD Mask */ -#define SCU_SFSPF_10_EPUN_Pos 4 /*!< SCU SFSPF_10: EPUN Position */ -#define SCU_SFSPF_10_EPUN_Msk (0x01UL << SCU_SFSPF_10_EPUN_Pos) /*!< SCU SFSPF_10: EPUN Mask */ -#define SCU_SFSPF_10_EHS_Pos 5 /*!< SCU SFSPF_10: EHS Position */ -#define SCU_SFSPF_10_EHS_Msk (0x01UL << SCU_SFSPF_10_EHS_Pos) /*!< SCU SFSPF_10: EHS Mask */ -#define SCU_SFSPF_10_EZI_Pos 6 /*!< SCU SFSPF_10: EZI Position */ -#define SCU_SFSPF_10_EZI_Msk (0x01UL << SCU_SFSPF_10_EZI_Pos) /*!< SCU SFSPF_10: EZI Mask */ -#define SCU_SFSPF_10_EHD_Pos 8 /*!< SCU SFSPF_10: EHD Position */ -#define SCU_SFSPF_10_EHD_Msk (0x03UL << SCU_SFSPF_10_EHD_Pos) /*!< SCU SFSPF_10: EHD Mask */ - -// -------------------------------------- SCU_SFSPF_11 ------------------------------------------ -#define SCU_SFSPF_11_MODE_Pos 0 /*!< SCU SFSPF_11: MODE Position */ -#define SCU_SFSPF_11_MODE_Msk (0x07UL << SCU_SFSPF_11_MODE_Pos) /*!< SCU SFSPF_11: MODE Mask */ -#define SCU_SFSPF_11_EPD_Pos 3 /*!< SCU SFSPF_11: EPD Position */ -#define SCU_SFSPF_11_EPD_Msk (0x01UL << SCU_SFSPF_11_EPD_Pos) /*!< SCU SFSPF_11: EPD Mask */ -#define SCU_SFSPF_11_EPUN_Pos 4 /*!< SCU SFSPF_11: EPUN Position */ -#define SCU_SFSPF_11_EPUN_Msk (0x01UL << SCU_SFSPF_11_EPUN_Pos) /*!< SCU SFSPF_11: EPUN Mask */ -#define SCU_SFSPF_11_EHS_Pos 5 /*!< SCU SFSPF_11: EHS Position */ -#define SCU_SFSPF_11_EHS_Msk (0x01UL << SCU_SFSPF_11_EHS_Pos) /*!< SCU SFSPF_11: EHS Mask */ -#define SCU_SFSPF_11_EZI_Pos 6 /*!< SCU SFSPF_11: EZI Position */ -#define SCU_SFSPF_11_EZI_Msk (0x01UL << SCU_SFSPF_11_EZI_Pos) /*!< SCU SFSPF_11: EZI Mask */ -#define SCU_SFSPF_11_EHD_Pos 8 /*!< SCU SFSPF_11: EHD Position */ -#define SCU_SFSPF_11_EHD_Msk (0x03UL << SCU_SFSPF_11_EHD_Pos) /*!< SCU SFSPF_11: EHD Mask */ - -// -------------------------------------- SCU_SFSCLK_0 ------------------------------------------ -#define SCU_SFSCLK_0_MODE_Pos 0 /*!< SCU SFSCLK_0: MODE Position */ -#define SCU_SFSCLK_0_MODE_Msk (0x07UL << SCU_SFSCLK_0_MODE_Pos) /*!< SCU SFSCLK_0: MODE Mask */ -#define SCU_SFSCLK_0_EPD_Pos 3 /*!< SCU SFSCLK_0: EPD Position */ -#define SCU_SFSCLK_0_EPD_Msk (0x01UL << SCU_SFSCLK_0_EPD_Pos) /*!< SCU SFSCLK_0: EPD Mask */ -#define SCU_SFSCLK_0_EPUN_Pos 4 /*!< SCU SFSCLK_0: EPUN Position */ -#define SCU_SFSCLK_0_EPUN_Msk (0x01UL << SCU_SFSCLK_0_EPUN_Pos) /*!< SCU SFSCLK_0: EPUN Mask */ -#define SCU_SFSCLK_0_EHS_Pos 5 /*!< SCU SFSCLK_0: EHS Position */ -#define SCU_SFSCLK_0_EHS_Msk (0x01UL << SCU_SFSCLK_0_EHS_Pos) /*!< SCU SFSCLK_0: EHS Mask */ -#define SCU_SFSCLK_0_EZI_Pos 6 /*!< SCU SFSCLK_0: EZI Position */ -#define SCU_SFSCLK_0_EZI_Msk (0x01UL << SCU_SFSCLK_0_EZI_Pos) /*!< SCU SFSCLK_0: EZI Mask */ -#define SCU_SFSCLK_0_EHD_Pos 8 /*!< SCU SFSCLK_0: EHD Position */ -#define SCU_SFSCLK_0_EHD_Msk (0x03UL << SCU_SFSCLK_0_EHD_Pos) /*!< SCU SFSCLK_0: EHD Mask */ - -// -------------------------------------- SCU_SFSCLK_1 ------------------------------------------ -#define SCU_SFSCLK_1_MODE_Pos 0 /*!< SCU SFSCLK_1: MODE Position */ -#define SCU_SFSCLK_1_MODE_Msk (0x07UL << SCU_SFSCLK_1_MODE_Pos) /*!< SCU SFSCLK_1: MODE Mask */ -#define SCU_SFSCLK_1_EPD_Pos 3 /*!< SCU SFSCLK_1: EPD Position */ -#define SCU_SFSCLK_1_EPD_Msk (0x01UL << SCU_SFSCLK_1_EPD_Pos) /*!< SCU SFSCLK_1: EPD Mask */ -#define SCU_SFSCLK_1_EPUN_Pos 4 /*!< SCU SFSCLK_1: EPUN Position */ -#define SCU_SFSCLK_1_EPUN_Msk (0x01UL << SCU_SFSCLK_1_EPUN_Pos) /*!< SCU SFSCLK_1: EPUN Mask */ -#define SCU_SFSCLK_1_EHS_Pos 5 /*!< SCU SFSCLK_1: EHS Position */ -#define SCU_SFSCLK_1_EHS_Msk (0x01UL << SCU_SFSCLK_1_EHS_Pos) /*!< SCU SFSCLK_1: EHS Mask */ -#define SCU_SFSCLK_1_EZI_Pos 6 /*!< SCU SFSCLK_1: EZI Position */ -#define SCU_SFSCLK_1_EZI_Msk (0x01UL << SCU_SFSCLK_1_EZI_Pos) /*!< SCU SFSCLK_1: EZI Mask */ -#define SCU_SFSCLK_1_EHD_Pos 8 /*!< SCU SFSCLK_1: EHD Position */ -#define SCU_SFSCLK_1_EHD_Msk (0x03UL << SCU_SFSCLK_1_EHD_Pos) /*!< SCU SFSCLK_1: EHD Mask */ - -// -------------------------------------- SCU_SFSCLK_2 ------------------------------------------ -#define SCU_SFSCLK_2_MODE_Pos 0 /*!< SCU SFSCLK_2: MODE Position */ -#define SCU_SFSCLK_2_MODE_Msk (0x07UL << SCU_SFSCLK_2_MODE_Pos) /*!< SCU SFSCLK_2: MODE Mask */ -#define SCU_SFSCLK_2_EPD_Pos 3 /*!< SCU SFSCLK_2: EPD Position */ -#define SCU_SFSCLK_2_EPD_Msk (0x01UL << SCU_SFSCLK_2_EPD_Pos) /*!< SCU SFSCLK_2: EPD Mask */ -#define SCU_SFSCLK_2_EPUN_Pos 4 /*!< SCU SFSCLK_2: EPUN Position */ -#define SCU_SFSCLK_2_EPUN_Msk (0x01UL << SCU_SFSCLK_2_EPUN_Pos) /*!< SCU SFSCLK_2: EPUN Mask */ -#define SCU_SFSCLK_2_EHS_Pos 5 /*!< SCU SFSCLK_2: EHS Position */ -#define SCU_SFSCLK_2_EHS_Msk (0x01UL << SCU_SFSCLK_2_EHS_Pos) /*!< SCU SFSCLK_2: EHS Mask */ -#define SCU_SFSCLK_2_EZI_Pos 6 /*!< SCU SFSCLK_2: EZI Position */ -#define SCU_SFSCLK_2_EZI_Msk (0x01UL << SCU_SFSCLK_2_EZI_Pos) /*!< SCU SFSCLK_2: EZI Mask */ -#define SCU_SFSCLK_2_EHD_Pos 8 /*!< SCU SFSCLK_2: EHD Position */ -#define SCU_SFSCLK_2_EHD_Msk (0x03UL << SCU_SFSCLK_2_EHD_Pos) /*!< SCU SFSCLK_2: EHD Mask */ - -// -------------------------------------- SCU_SFSCLK_3 ------------------------------------------ -#define SCU_SFSCLK_3_MODE_Pos 0 /*!< SCU SFSCLK_3: MODE Position */ -#define SCU_SFSCLK_3_MODE_Msk (0x07UL << SCU_SFSCLK_3_MODE_Pos) /*!< SCU SFSCLK_3: MODE Mask */ -#define SCU_SFSCLK_3_EPD_Pos 3 /*!< SCU SFSCLK_3: EPD Position */ -#define SCU_SFSCLK_3_EPD_Msk (0x01UL << SCU_SFSCLK_3_EPD_Pos) /*!< SCU SFSCLK_3: EPD Mask */ -#define SCU_SFSCLK_3_EPUN_Pos 4 /*!< SCU SFSCLK_3: EPUN Position */ -#define SCU_SFSCLK_3_EPUN_Msk (0x01UL << SCU_SFSCLK_3_EPUN_Pos) /*!< SCU SFSCLK_3: EPUN Mask */ -#define SCU_SFSCLK_3_EHS_Pos 5 /*!< SCU SFSCLK_3: EHS Position */ -#define SCU_SFSCLK_3_EHS_Msk (0x01UL << SCU_SFSCLK_3_EHS_Pos) /*!< SCU SFSCLK_3: EHS Mask */ -#define SCU_SFSCLK_3_EZI_Pos 6 /*!< SCU SFSCLK_3: EZI Position */ -#define SCU_SFSCLK_3_EZI_Msk (0x01UL << SCU_SFSCLK_3_EZI_Pos) /*!< SCU SFSCLK_3: EZI Mask */ -#define SCU_SFSCLK_3_EHD_Pos 8 /*!< SCU SFSCLK_3: EHD Position */ -#define SCU_SFSCLK_3_EHD_Msk (0x03UL << SCU_SFSCLK_3_EHD_Pos) /*!< SCU SFSCLK_3: EHD Mask */ - -// --------------------------------------- SCU_SFSUSB ------------------------------------------- -#define SCU_SFSUSB_USB_AIM_Pos 0 /*!< SCU SFSUSB: USB_AIM Position */ -#define SCU_SFSUSB_USB_AIM_Msk (0x01UL << SCU_SFSUSB_USB_AIM_Pos) /*!< SCU SFSUSB: USB_AIM Mask */ -#define SCU_SFSUSB_USB_ESEA_Pos 1 /*!< SCU SFSUSB: USB_ESEA Position */ -#define SCU_SFSUSB_USB_ESEA_Msk (0x01UL << SCU_SFSUSB_USB_ESEA_Pos) /*!< SCU SFSUSB: USB_ESEA Mask */ - -// --------------------------------------- SCU_SFSI2C0 ------------------------------------------ -#define SCU_SFSI2C0_SDA_EHS_Pos 0 /*!< SCU SFSI2C0: SDA_EHS Position */ -#define SCU_SFSI2C0_SDA_EHS_Msk (0x01UL << SCU_SFSI2C0_SDA_EHS_Pos) /*!< SCU SFSI2C0: SDA_EHS Mask */ -#define SCU_SFSI2C0_SCL_EHS_Pos 1 /*!< SCU SFSI2C0: SCL_EHS Position */ -#define SCU_SFSI2C0_SCL_EHS_Msk (0x01UL << SCU_SFSI2C0_SCL_EHS_Pos) /*!< SCU SFSI2C0: SCL_EHS Mask */ -#define SCU_SFSI2C0_SCL_ECS_Pos 2 /*!< SCU SFSI2C0: SCL_ECS Position */ -#define SCU_SFSI2C0_SCL_ECS_Msk (0x01UL << SCU_SFSI2C0_SCL_ECS_Pos) /*!< SCU SFSI2C0: SCL_ECS Mask */ - -// --------------------------------------- SCU_ENAIO0 ------------------------------------------- -#define SCU_ENAIO0_ADC0_0_Pos 0 /*!< SCU ENAIO0: ADC0_0 Position */ -#define SCU_ENAIO0_ADC0_0_Msk (0x01UL << SCU_ENAIO0_ADC0_0_Pos) /*!< SCU ENAIO0: ADC0_0 Mask */ -#define SCU_ENAIO0_ADC0_1_Pos 1 /*!< SCU ENAIO0: ADC0_1 Position */ -#define SCU_ENAIO0_ADC0_1_Msk (0x01UL << SCU_ENAIO0_ADC0_1_Pos) /*!< SCU ENAIO0: ADC0_1 Mask */ -#define SCU_ENAIO0_ADC0_2_Pos 2 /*!< SCU ENAIO0: ADC0_2 Position */ -#define SCU_ENAIO0_ADC0_2_Msk (0x01UL << SCU_ENAIO0_ADC0_2_Pos) /*!< SCU ENAIO0: ADC0_2 Mask */ -#define SCU_ENAIO0_ADC0_3_Pos 3 /*!< SCU ENAIO0: ADC0_3 Position */ -#define SCU_ENAIO0_ADC0_3_Msk (0x01UL << SCU_ENAIO0_ADC0_3_Pos) /*!< SCU ENAIO0: ADC0_3 Mask */ -#define SCU_ENAIO0_ADC0_4_Pos 4 /*!< SCU ENAIO0: ADC0_4 Position */ -#define SCU_ENAIO0_ADC0_4_Msk (0x01UL << SCU_ENAIO0_ADC0_4_Pos) /*!< SCU ENAIO0: ADC0_4 Mask */ -#define SCU_ENAIO0_ADC0_5_Pos 5 /*!< SCU ENAIO0: ADC0_5 Position */ -#define SCU_ENAIO0_ADC0_5_Msk (0x01UL << SCU_ENAIO0_ADC0_5_Pos) /*!< SCU ENAIO0: ADC0_5 Mask */ -#define SCU_ENAIO0_ADC0_6_Pos 6 /*!< SCU ENAIO0: ADC0_6 Position */ -#define SCU_ENAIO0_ADC0_6_Msk (0x01UL << SCU_ENAIO0_ADC0_6_Pos) /*!< SCU ENAIO0: ADC0_6 Mask */ - -// --------------------------------------- SCU_ENAIO1 ------------------------------------------- -#define SCU_ENAIO1_ADC1_0_Pos 0 /*!< SCU ENAIO1: ADC1_0 Position */ -#define SCU_ENAIO1_ADC1_0_Msk (0x01UL << SCU_ENAIO1_ADC1_0_Pos) /*!< SCU ENAIO1: ADC1_0 Mask */ -#define SCU_ENAIO1_ADC1_1_Pos 1 /*!< SCU ENAIO1: ADC1_1 Position */ -#define SCU_ENAIO1_ADC1_1_Msk (0x01UL << SCU_ENAIO1_ADC1_1_Pos) /*!< SCU ENAIO1: ADC1_1 Mask */ -#define SCU_ENAIO1_ADC1_2_Pos 2 /*!< SCU ENAIO1: ADC1_2 Position */ -#define SCU_ENAIO1_ADC1_2_Msk (0x01UL << SCU_ENAIO1_ADC1_2_Pos) /*!< SCU ENAIO1: ADC1_2 Mask */ -#define SCU_ENAIO1_ADC1_3_Pos 3 /*!< SCU ENAIO1: ADC1_3 Position */ -#define SCU_ENAIO1_ADC1_3_Msk (0x01UL << SCU_ENAIO1_ADC1_3_Pos) /*!< SCU ENAIO1: ADC1_3 Mask */ -#define SCU_ENAIO1_ADC1_4_Pos 4 /*!< SCU ENAIO1: ADC1_4 Position */ -#define SCU_ENAIO1_ADC1_4_Msk (0x01UL << SCU_ENAIO1_ADC1_4_Pos) /*!< SCU ENAIO1: ADC1_4 Mask */ -#define SCU_ENAIO1_ADC1_5_Pos 5 /*!< SCU ENAIO1: ADC1_5 Position */ -#define SCU_ENAIO1_ADC1_5_Msk (0x01UL << SCU_ENAIO1_ADC1_5_Pos) /*!< SCU ENAIO1: ADC1_5 Mask */ -#define SCU_ENAIO1_ADC1_6_Pos 6 /*!< SCU ENAIO1: ADC1_6 Position */ -#define SCU_ENAIO1_ADC1_6_Msk (0x01UL << SCU_ENAIO1_ADC1_6_Pos) /*!< SCU ENAIO1: ADC1_6 Mask */ -#define SCU_ENAIO1_ADC1_7_Pos 7 /*!< SCU ENAIO1: ADC1_7 Position */ -#define SCU_ENAIO1_ADC1_7_Msk (0x01UL << SCU_ENAIO1_ADC1_7_Pos) /*!< SCU ENAIO1: ADC1_7 Mask */ - -// --------------------------------------- SCU_ENAIO2 ------------------------------------------- -#define SCU_ENAIO2_DAC_Pos 0 /*!< SCU ENAIO2: DAC Position */ -#define SCU_ENAIO2_DAC_Msk (0x01UL << SCU_ENAIO2_DAC_Pos) /*!< SCU ENAIO2: DAC Mask */ -#define SCU_ENAIO2_BG_Pos 4 /*!< SCU ENAIO2: BG Position */ -#define SCU_ENAIO2_BG_Msk (0x01UL << SCU_ENAIO2_BG_Pos) /*!< SCU ENAIO2: BG Mask */ - -// ------------------------------------- SCU_EMCDELAYCLK ---------------------------------------- -#define SCU_EMCDELAYCLK_CLK0_DELAY_Pos 0 /*!< SCU EMCDELAYCLK: CLK0_DELAY Position */ -#define SCU_EMCDELAYCLK_CLK0_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CLK0_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK0_DELAY Mask */ -#define SCU_EMCDELAYCLK_CLK1_DELAY_Pos 4 /*!< SCU EMCDELAYCLK: CLK1_DELAY Position */ -#define SCU_EMCDELAYCLK_CLK1_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CLK1_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK1_DELAY Mask */ -#define SCU_EMCDELAYCLK_CLK2_DELAY_Pos 8 /*!< SCU EMCDELAYCLK: CLK2_DELAY Position */ -#define SCU_EMCDELAYCLK_CLK2_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CLK2_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK2_DELAY Mask */ -#define SCU_EMCDELAYCLK_CLK3_DELAY_Pos 12 /*!< SCU EMCDELAYCLK: CLK3_DELAY Position */ -#define SCU_EMCDELAYCLK_CLK3_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CLK3_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK3_DELAY Mask */ -#define SCU_EMCDELAYCLK_CKE0_DELAY_Pos 16 /*!< SCU EMCDELAYCLK: CKE0_DELAY Position */ -#define SCU_EMCDELAYCLK_CKE0_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CKE0_DELAY_Pos) /*!< SCU EMCDELAYCLK: CKE0_DELAY Mask */ -#define SCU_EMCDELAYCLK_CKE1_DELAY_Pos 20 /*!< SCU EMCDELAYCLK: CKE1_DELAY Position */ -#define SCU_EMCDELAYCLK_CKE1_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CKE1_DELAY_Pos) /*!< SCU EMCDELAYCLK: CKE1_DELAY Mask */ -#define SCU_EMCDELAYCLK_CKE2_DELAY_Pos 24 /*!< SCU EMCDELAYCLK: CKE2_DELAY Position */ -#define SCU_EMCDELAYCLK_CKE2_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CKE2_DELAY_Pos) /*!< SCU EMCDELAYCLK: CKE2_DELAY Mask */ -#define SCU_EMCDELAYCLK_CKE3_DELAY_Pos 28 /*!< SCU EMCDELAYCLK: CKE3_DELAY Position */ -#define SCU_EMCDELAYCLK_CKE3_DELAY_Msk (0x07UL << SCU_EMCDELAYCLK_CKE3_DELAY_Pos) /*!< SCU EMCDELAYCLK: CKE3_DELAY Mask */ - -// -------------------------------------- SCU_PINTSEL0 ------------------------------------------ -#define SCU_PINTSEL0_INTPIN0_Pos 0 /*!< SCU PINTSEL0: INTPIN0 Position */ -#define SCU_PINTSEL0_INTPIN0_Msk (0x1fUL << SCU_PINTSEL0_INTPIN0_Pos) /*!< SCU PINTSEL0: INTPIN0 Mask */ -#define SCU_PINTSEL0_PORTSEL0_Pos 5 /*!< SCU PINTSEL0: PORTSEL0 Position */ -#define SCU_PINTSEL0_PORTSEL0_Msk (0x07UL << SCU_PINTSEL0_PORTSEL0_Pos) /*!< SCU PINTSEL0: PORTSEL0 Mask */ -#define SCU_PINTSEL0_INTPIN1_Pos 8 /*!< SCU PINTSEL0: INTPIN1 Position */ -#define SCU_PINTSEL0_INTPIN1_Msk (0x1fUL << SCU_PINTSEL0_INTPIN1_Pos) /*!< SCU PINTSEL0: INTPIN1 Mask */ -#define SCU_PINTSEL0_PORTSEL1_Pos 13 /*!< SCU PINTSEL0: PORTSEL1 Position */ -#define SCU_PINTSEL0_PORTSEL1_Msk (0x07UL << SCU_PINTSEL0_PORTSEL1_Pos) /*!< SCU PINTSEL0: PORTSEL1 Mask */ -#define SCU_PINTSEL0_INTPIN2_Pos 16 /*!< SCU PINTSEL0: INTPIN2 Position */ -#define SCU_PINTSEL0_INTPIN2_Msk (0x1fUL << SCU_PINTSEL0_INTPIN2_Pos) /*!< SCU PINTSEL0: INTPIN2 Mask */ -#define SCU_PINTSEL0_PORTSEL2_Pos 21 /*!< SCU PINTSEL0: PORTSEL2 Position */ -#define SCU_PINTSEL0_PORTSEL2_Msk (0x07UL << SCU_PINTSEL0_PORTSEL2_Pos) /*!< SCU PINTSEL0: PORTSEL2 Mask */ -#define SCU_PINTSEL0_INTPIN3_Pos 24 /*!< SCU PINTSEL0: INTPIN3 Position */ -#define SCU_PINTSEL0_INTPIN3_Msk (0x1fUL << SCU_PINTSEL0_INTPIN3_Pos) /*!< SCU PINTSEL0: INTPIN3 Mask */ -#define SCU_PINTSEL0_PORTSEL3_Pos 29 /*!< SCU PINTSEL0: PORTSEL3 Position */ -#define SCU_PINTSEL0_PORTSEL3_Msk (0x07UL << SCU_PINTSEL0_PORTSEL3_Pos) /*!< SCU PINTSEL0: PORTSEL3 Mask */ - -// -------------------------------------- SCU_PINTSEL1 ------------------------------------------ -#define SCU_PINTSEL1_INTPIN4_Pos 0 /*!< SCU PINTSEL1: INTPIN4 Position */ -#define SCU_PINTSEL1_INTPIN4_Msk (0x1fUL << SCU_PINTSEL1_INTPIN4_Pos) /*!< SCU PINTSEL1: INTPIN4 Mask */ -#define SCU_PINTSEL1_PORTSEL4_Pos 5 /*!< SCU PINTSEL1: PORTSEL4 Position */ -#define SCU_PINTSEL1_PORTSEL4_Msk (0x07UL << SCU_PINTSEL1_PORTSEL4_Pos) /*!< SCU PINTSEL1: PORTSEL4 Mask */ -#define SCU_PINTSEL1_INTPIN5_Pos 8 /*!< SCU PINTSEL1: INTPIN5 Position */ -#define SCU_PINTSEL1_INTPIN5_Msk (0x1fUL << SCU_PINTSEL1_INTPIN5_Pos) /*!< SCU PINTSEL1: INTPIN5 Mask */ -#define SCU_PINTSEL1_PORTSEL5_Pos 13 /*!< SCU PINTSEL1: PORTSEL5 Position */ -#define SCU_PINTSEL1_PORTSEL5_Msk (0x07UL << SCU_PINTSEL1_PORTSEL5_Pos) /*!< SCU PINTSEL1: PORTSEL5 Mask */ -#define SCU_PINTSEL1_INTPIN6_Pos 16 /*!< SCU PINTSEL1: INTPIN6 Position */ -#define SCU_PINTSEL1_INTPIN6_Msk (0x1fUL << SCU_PINTSEL1_INTPIN6_Pos) /*!< SCU PINTSEL1: INTPIN6 Mask */ -#define SCU_PINTSEL1_PORTSEL6_Pos 21 /*!< SCU PINTSEL1: PORTSEL6 Position */ -#define SCU_PINTSEL1_PORTSEL6_Msk (0x07UL << SCU_PINTSEL1_PORTSEL6_Pos) /*!< SCU PINTSEL1: PORTSEL6 Mask */ -#define SCU_PINTSEL1_INTPIN7_Pos 24 /*!< SCU PINTSEL1: INTPIN7 Position */ -#define SCU_PINTSEL1_INTPIN7_Msk (0x1fUL << SCU_PINTSEL1_INTPIN7_Pos) /*!< SCU PINTSEL1: INTPIN7 Mask */ -#define SCU_PINTSEL1_PORTSEL7_Pos 29 /*!< SCU PINTSEL1: PORTSEL7 Position */ -#define SCU_PINTSEL1_PORTSEL7_Msk (0x07UL << SCU_PINTSEL1_PORTSEL7_Pos) /*!< SCU PINTSEL1: PORTSEL7 Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_PIN_INT Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ------------------------------------ GPIO_PIN_INT_ISEL --------------------------------------- -#define GPIO_PIN_INT_ISEL_PMODE0_Pos 0 /*!< GPIO_PIN_INT ISEL: PMODE0 Position */ -#define GPIO_PIN_INT_ISEL_PMODE0_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE0_Pos) /*!< GPIO_PIN_INT ISEL: PMODE0 Mask */ -#define GPIO_PIN_INT_ISEL_PMODE1_Pos 1 /*!< GPIO_PIN_INT ISEL: PMODE1 Position */ -#define GPIO_PIN_INT_ISEL_PMODE1_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE1_Pos) /*!< GPIO_PIN_INT ISEL: PMODE1 Mask */ -#define GPIO_PIN_INT_ISEL_PMODE2_Pos 2 /*!< GPIO_PIN_INT ISEL: PMODE2 Position */ -#define GPIO_PIN_INT_ISEL_PMODE2_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE2_Pos) /*!< GPIO_PIN_INT ISEL: PMODE2 Mask */ -#define GPIO_PIN_INT_ISEL_PMODE3_Pos 3 /*!< GPIO_PIN_INT ISEL: PMODE3 Position */ -#define GPIO_PIN_INT_ISEL_PMODE3_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE3_Pos) /*!< GPIO_PIN_INT ISEL: PMODE3 Mask */ -#define GPIO_PIN_INT_ISEL_PMODE4_Pos 4 /*!< GPIO_PIN_INT ISEL: PMODE4 Position */ -#define GPIO_PIN_INT_ISEL_PMODE4_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE4_Pos) /*!< GPIO_PIN_INT ISEL: PMODE4 Mask */ -#define GPIO_PIN_INT_ISEL_PMODE5_Pos 5 /*!< GPIO_PIN_INT ISEL: PMODE5 Position */ -#define GPIO_PIN_INT_ISEL_PMODE5_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE5_Pos) /*!< GPIO_PIN_INT ISEL: PMODE5 Mask */ -#define GPIO_PIN_INT_ISEL_PMODE6_Pos 6 /*!< GPIO_PIN_INT ISEL: PMODE6 Position */ -#define GPIO_PIN_INT_ISEL_PMODE6_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE6_Pos) /*!< GPIO_PIN_INT ISEL: PMODE6 Mask */ -#define GPIO_PIN_INT_ISEL_PMODE7_Pos 7 /*!< GPIO_PIN_INT ISEL: PMODE7 Position */ -#define GPIO_PIN_INT_ISEL_PMODE7_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE7_Pos) /*!< GPIO_PIN_INT ISEL: PMODE7 Mask */ - -// ------------------------------------ GPIO_PIN_INT_IENR --------------------------------------- -#define GPIO_PIN_INT_IENR_ENRL0_Pos 0 /*!< GPIO_PIN_INT IENR: ENRL0 Position */ -#define GPIO_PIN_INT_IENR_ENRL0_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL0_Pos) /*!< GPIO_PIN_INT IENR: ENRL0 Mask */ -#define GPIO_PIN_INT_IENR_ENRL1_Pos 1 /*!< GPIO_PIN_INT IENR: ENRL1 Position */ -#define GPIO_PIN_INT_IENR_ENRL1_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL1_Pos) /*!< GPIO_PIN_INT IENR: ENRL1 Mask */ -#define GPIO_PIN_INT_IENR_ENRL2_Pos 2 /*!< GPIO_PIN_INT IENR: ENRL2 Position */ -#define GPIO_PIN_INT_IENR_ENRL2_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL2_Pos) /*!< GPIO_PIN_INT IENR: ENRL2 Mask */ -#define GPIO_PIN_INT_IENR_ENRL3_Pos 3 /*!< GPIO_PIN_INT IENR: ENRL3 Position */ -#define GPIO_PIN_INT_IENR_ENRL3_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL3_Pos) /*!< GPIO_PIN_INT IENR: ENRL3 Mask */ -#define GPIO_PIN_INT_IENR_ENRL4_Pos 4 /*!< GPIO_PIN_INT IENR: ENRL4 Position */ -#define GPIO_PIN_INT_IENR_ENRL4_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL4_Pos) /*!< GPIO_PIN_INT IENR: ENRL4 Mask */ -#define GPIO_PIN_INT_IENR_ENRL5_Pos 5 /*!< GPIO_PIN_INT IENR: ENRL5 Position */ -#define GPIO_PIN_INT_IENR_ENRL5_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL5_Pos) /*!< GPIO_PIN_INT IENR: ENRL5 Mask */ -#define GPIO_PIN_INT_IENR_ENRL6_Pos 6 /*!< GPIO_PIN_INT IENR: ENRL6 Position */ -#define GPIO_PIN_INT_IENR_ENRL6_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL6_Pos) /*!< GPIO_PIN_INT IENR: ENRL6 Mask */ -#define GPIO_PIN_INT_IENR_ENRL7_Pos 7 /*!< GPIO_PIN_INT IENR: ENRL7 Position */ -#define GPIO_PIN_INT_IENR_ENRL7_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL7_Pos) /*!< GPIO_PIN_INT IENR: ENRL7 Mask */ - -// ----------------------------------- GPIO_PIN_INT_SIENR --------------------------------------- -#define GPIO_PIN_INT_SIENR_SETENRL0_Pos 0 /*!< GPIO_PIN_INT SIENR: SETENRL0 Position */ -#define GPIO_PIN_INT_SIENR_SETENRL0_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL0_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL0 Mask */ -#define GPIO_PIN_INT_SIENR_SETENRL1_Pos 1 /*!< GPIO_PIN_INT SIENR: SETENRL1 Position */ -#define GPIO_PIN_INT_SIENR_SETENRL1_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL1_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL1 Mask */ -#define GPIO_PIN_INT_SIENR_SETENRL2_Pos 2 /*!< GPIO_PIN_INT SIENR: SETENRL2 Position */ -#define GPIO_PIN_INT_SIENR_SETENRL2_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL2_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL2 Mask */ -#define GPIO_PIN_INT_SIENR_SETENRL3_Pos 3 /*!< GPIO_PIN_INT SIENR: SETENRL3 Position */ -#define GPIO_PIN_INT_SIENR_SETENRL3_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL3_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL3 Mask */ -#define GPIO_PIN_INT_SIENR_SETENRL4_Pos 4 /*!< GPIO_PIN_INT SIENR: SETENRL4 Position */ -#define GPIO_PIN_INT_SIENR_SETENRL4_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL4_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL4 Mask */ -#define GPIO_PIN_INT_SIENR_SETENRL5_Pos 5 /*!< GPIO_PIN_INT SIENR: SETENRL5 Position */ -#define GPIO_PIN_INT_SIENR_SETENRL5_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL5_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL5 Mask */ -#define GPIO_PIN_INT_SIENR_SETENRL6_Pos 6 /*!< GPIO_PIN_INT SIENR: SETENRL6 Position */ -#define GPIO_PIN_INT_SIENR_SETENRL6_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL6_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL6 Mask */ -#define GPIO_PIN_INT_SIENR_SETENRL7_Pos 7 /*!< GPIO_PIN_INT SIENR: SETENRL7 Position */ -#define GPIO_PIN_INT_SIENR_SETENRL7_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL7_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL7 Mask */ - -// ----------------------------------- GPIO_PIN_INT_CIENR --------------------------------------- -#define GPIO_PIN_INT_CIENR_CENRL0_Pos 0 /*!< GPIO_PIN_INT CIENR: CENRL0 Position */ -#define GPIO_PIN_INT_CIENR_CENRL0_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL0_Pos) /*!< GPIO_PIN_INT CIENR: CENRL0 Mask */ -#define GPIO_PIN_INT_CIENR_CENRL1_Pos 1 /*!< GPIO_PIN_INT CIENR: CENRL1 Position */ -#define GPIO_PIN_INT_CIENR_CENRL1_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL1_Pos) /*!< GPIO_PIN_INT CIENR: CENRL1 Mask */ -#define GPIO_PIN_INT_CIENR_CENRL2_Pos 2 /*!< GPIO_PIN_INT CIENR: CENRL2 Position */ -#define GPIO_PIN_INT_CIENR_CENRL2_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL2_Pos) /*!< GPIO_PIN_INT CIENR: CENRL2 Mask */ -#define GPIO_PIN_INT_CIENR_CENRL3_Pos 3 /*!< GPIO_PIN_INT CIENR: CENRL3 Position */ -#define GPIO_PIN_INT_CIENR_CENRL3_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL3_Pos) /*!< GPIO_PIN_INT CIENR: CENRL3 Mask */ -#define GPIO_PIN_INT_CIENR_CENRL4_Pos 4 /*!< GPIO_PIN_INT CIENR: CENRL4 Position */ -#define GPIO_PIN_INT_CIENR_CENRL4_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL4_Pos) /*!< GPIO_PIN_INT CIENR: CENRL4 Mask */ -#define GPIO_PIN_INT_CIENR_CENRL5_Pos 5 /*!< GPIO_PIN_INT CIENR: CENRL5 Position */ -#define GPIO_PIN_INT_CIENR_CENRL5_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL5_Pos) /*!< GPIO_PIN_INT CIENR: CENRL5 Mask */ -#define GPIO_PIN_INT_CIENR_CENRL6_Pos 6 /*!< GPIO_PIN_INT CIENR: CENRL6 Position */ -#define GPIO_PIN_INT_CIENR_CENRL6_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL6_Pos) /*!< GPIO_PIN_INT CIENR: CENRL6 Mask */ -#define GPIO_PIN_INT_CIENR_CENRL7_Pos 7 /*!< GPIO_PIN_INT CIENR: CENRL7 Position */ -#define GPIO_PIN_INT_CIENR_CENRL7_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL7_Pos) /*!< GPIO_PIN_INT CIENR: CENRL7 Mask */ - -// ------------------------------------ GPIO_PIN_INT_IENF --------------------------------------- -#define GPIO_PIN_INT_IENF_ENAF0_Pos 0 /*!< GPIO_PIN_INT IENF: ENAF0 Position */ -#define GPIO_PIN_INT_IENF_ENAF0_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF0_Pos) /*!< GPIO_PIN_INT IENF: ENAF0 Mask */ -#define GPIO_PIN_INT_IENF_ENAF1_Pos 1 /*!< GPIO_PIN_INT IENF: ENAF1 Position */ -#define GPIO_PIN_INT_IENF_ENAF1_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF1_Pos) /*!< GPIO_PIN_INT IENF: ENAF1 Mask */ -#define GPIO_PIN_INT_IENF_ENAF2_Pos 2 /*!< GPIO_PIN_INT IENF: ENAF2 Position */ -#define GPIO_PIN_INT_IENF_ENAF2_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF2_Pos) /*!< GPIO_PIN_INT IENF: ENAF2 Mask */ -#define GPIO_PIN_INT_IENF_ENAF3_Pos 3 /*!< GPIO_PIN_INT IENF: ENAF3 Position */ -#define GPIO_PIN_INT_IENF_ENAF3_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF3_Pos) /*!< GPIO_PIN_INT IENF: ENAF3 Mask */ -#define GPIO_PIN_INT_IENF_ENAF4_Pos 4 /*!< GPIO_PIN_INT IENF: ENAF4 Position */ -#define GPIO_PIN_INT_IENF_ENAF4_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF4_Pos) /*!< GPIO_PIN_INT IENF: ENAF4 Mask */ -#define GPIO_PIN_INT_IENF_ENAF5_Pos 5 /*!< GPIO_PIN_INT IENF: ENAF5 Position */ -#define GPIO_PIN_INT_IENF_ENAF5_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF5_Pos) /*!< GPIO_PIN_INT IENF: ENAF5 Mask */ -#define GPIO_PIN_INT_IENF_ENAF6_Pos 6 /*!< GPIO_PIN_INT IENF: ENAF6 Position */ -#define GPIO_PIN_INT_IENF_ENAF6_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF6_Pos) /*!< GPIO_PIN_INT IENF: ENAF6 Mask */ -#define GPIO_PIN_INT_IENF_ENAF7_Pos 7 /*!< GPIO_PIN_INT IENF: ENAF7 Position */ -#define GPIO_PIN_INT_IENF_ENAF7_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF7_Pos) /*!< GPIO_PIN_INT IENF: ENAF7 Mask */ - -// ----------------------------------- GPIO_PIN_INT_SIENF --------------------------------------- -#define GPIO_PIN_INT_SIENF_SETENAF0_Pos 0 /*!< GPIO_PIN_INT SIENF: SETENAF0 Position */ -#define GPIO_PIN_INT_SIENF_SETENAF0_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF0_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF0 Mask */ -#define GPIO_PIN_INT_SIENF_SETENAF1_Pos 1 /*!< GPIO_PIN_INT SIENF: SETENAF1 Position */ -#define GPIO_PIN_INT_SIENF_SETENAF1_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF1_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF1 Mask */ -#define GPIO_PIN_INT_SIENF_SETENAF2_Pos 2 /*!< GPIO_PIN_INT SIENF: SETENAF2 Position */ -#define GPIO_PIN_INT_SIENF_SETENAF2_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF2_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF2 Mask */ -#define GPIO_PIN_INT_SIENF_SETENAF3_Pos 3 /*!< GPIO_PIN_INT SIENF: SETENAF3 Position */ -#define GPIO_PIN_INT_SIENF_SETENAF3_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF3_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF3 Mask */ -#define GPIO_PIN_INT_SIENF_SETENAF4_Pos 4 /*!< GPIO_PIN_INT SIENF: SETENAF4 Position */ -#define GPIO_PIN_INT_SIENF_SETENAF4_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF4_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF4 Mask */ -#define GPIO_PIN_INT_SIENF_SETENAF5_Pos 5 /*!< GPIO_PIN_INT SIENF: SETENAF5 Position */ -#define GPIO_PIN_INT_SIENF_SETENAF5_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF5_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF5 Mask */ -#define GPIO_PIN_INT_SIENF_SETENAF6_Pos 6 /*!< GPIO_PIN_INT SIENF: SETENAF6 Position */ -#define GPIO_PIN_INT_SIENF_SETENAF6_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF6_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF6 Mask */ -#define GPIO_PIN_INT_SIENF_SETENAF7_Pos 7 /*!< GPIO_PIN_INT SIENF: SETENAF7 Position */ -#define GPIO_PIN_INT_SIENF_SETENAF7_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF7_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF7 Mask */ - -// ----------------------------------- GPIO_PIN_INT_CIENF --------------------------------------- -#define GPIO_PIN_INT_CIENF_CENAF0_Pos 0 /*!< GPIO_PIN_INT CIENF: CENAF0 Position */ -#define GPIO_PIN_INT_CIENF_CENAF0_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF0_Pos) /*!< GPIO_PIN_INT CIENF: CENAF0 Mask */ -#define GPIO_PIN_INT_CIENF_CENAF1_Pos 1 /*!< GPIO_PIN_INT CIENF: CENAF1 Position */ -#define GPIO_PIN_INT_CIENF_CENAF1_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF1_Pos) /*!< GPIO_PIN_INT CIENF: CENAF1 Mask */ -#define GPIO_PIN_INT_CIENF_CENAF2_Pos 2 /*!< GPIO_PIN_INT CIENF: CENAF2 Position */ -#define GPIO_PIN_INT_CIENF_CENAF2_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF2_Pos) /*!< GPIO_PIN_INT CIENF: CENAF2 Mask */ -#define GPIO_PIN_INT_CIENF_CENAF3_Pos 3 /*!< GPIO_PIN_INT CIENF: CENAF3 Position */ -#define GPIO_PIN_INT_CIENF_CENAF3_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF3_Pos) /*!< GPIO_PIN_INT CIENF: CENAF3 Mask */ -#define GPIO_PIN_INT_CIENF_CENAF4_Pos 4 /*!< GPIO_PIN_INT CIENF: CENAF4 Position */ -#define GPIO_PIN_INT_CIENF_CENAF4_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF4_Pos) /*!< GPIO_PIN_INT CIENF: CENAF4 Mask */ -#define GPIO_PIN_INT_CIENF_CENAF5_Pos 5 /*!< GPIO_PIN_INT CIENF: CENAF5 Position */ -#define GPIO_PIN_INT_CIENF_CENAF5_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF5_Pos) /*!< GPIO_PIN_INT CIENF: CENAF5 Mask */ -#define GPIO_PIN_INT_CIENF_CENAF6_Pos 6 /*!< GPIO_PIN_INT CIENF: CENAF6 Position */ -#define GPIO_PIN_INT_CIENF_CENAF6_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF6_Pos) /*!< GPIO_PIN_INT CIENF: CENAF6 Mask */ -#define GPIO_PIN_INT_CIENF_CENAF7_Pos 7 /*!< GPIO_PIN_INT CIENF: CENAF7 Position */ -#define GPIO_PIN_INT_CIENF_CENAF7_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF7_Pos) /*!< GPIO_PIN_INT CIENF: CENAF7 Mask */ - -// ------------------------------------ GPIO_PIN_INT_RISE --------------------------------------- -#define GPIO_PIN_INT_RISE_RDET0_Pos 0 /*!< GPIO_PIN_INT RISE: RDET0 Position */ -#define GPIO_PIN_INT_RISE_RDET0_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET0_Pos) /*!< GPIO_PIN_INT RISE: RDET0 Mask */ -#define GPIO_PIN_INT_RISE_RDET1_Pos 1 /*!< GPIO_PIN_INT RISE: RDET1 Position */ -#define GPIO_PIN_INT_RISE_RDET1_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET1_Pos) /*!< GPIO_PIN_INT RISE: RDET1 Mask */ -#define GPIO_PIN_INT_RISE_RDET2_Pos 2 /*!< GPIO_PIN_INT RISE: RDET2 Position */ -#define GPIO_PIN_INT_RISE_RDET2_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET2_Pos) /*!< GPIO_PIN_INT RISE: RDET2 Mask */ -#define GPIO_PIN_INT_RISE_RDET3_Pos 3 /*!< GPIO_PIN_INT RISE: RDET3 Position */ -#define GPIO_PIN_INT_RISE_RDET3_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET3_Pos) /*!< GPIO_PIN_INT RISE: RDET3 Mask */ -#define GPIO_PIN_INT_RISE_RDET4_Pos 4 /*!< GPIO_PIN_INT RISE: RDET4 Position */ -#define GPIO_PIN_INT_RISE_RDET4_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET4_Pos) /*!< GPIO_PIN_INT RISE: RDET4 Mask */ -#define GPIO_PIN_INT_RISE_RDET5_Pos 5 /*!< GPIO_PIN_INT RISE: RDET5 Position */ -#define GPIO_PIN_INT_RISE_RDET5_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET5_Pos) /*!< GPIO_PIN_INT RISE: RDET5 Mask */ -#define GPIO_PIN_INT_RISE_RDET6_Pos 6 /*!< GPIO_PIN_INT RISE: RDET6 Position */ -#define GPIO_PIN_INT_RISE_RDET6_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET6_Pos) /*!< GPIO_PIN_INT RISE: RDET6 Mask */ -#define GPIO_PIN_INT_RISE_RDET7_Pos 7 /*!< GPIO_PIN_INT RISE: RDET7 Position */ -#define GPIO_PIN_INT_RISE_RDET7_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET7_Pos) /*!< GPIO_PIN_INT RISE: RDET7 Mask */ - -// ------------------------------------ GPIO_PIN_INT_FALL --------------------------------------- -#define GPIO_PIN_INT_FALL_FDET0_Pos 0 /*!< GPIO_PIN_INT FALL: FDET0 Position */ -#define GPIO_PIN_INT_FALL_FDET0_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET0_Pos) /*!< GPIO_PIN_INT FALL: FDET0 Mask */ -#define GPIO_PIN_INT_FALL_FDET1_Pos 1 /*!< GPIO_PIN_INT FALL: FDET1 Position */ -#define GPIO_PIN_INT_FALL_FDET1_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET1_Pos) /*!< GPIO_PIN_INT FALL: FDET1 Mask */ -#define GPIO_PIN_INT_FALL_FDET2_Pos 2 /*!< GPIO_PIN_INT FALL: FDET2 Position */ -#define GPIO_PIN_INT_FALL_FDET2_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET2_Pos) /*!< GPIO_PIN_INT FALL: FDET2 Mask */ -#define GPIO_PIN_INT_FALL_FDET3_Pos 3 /*!< GPIO_PIN_INT FALL: FDET3 Position */ -#define GPIO_PIN_INT_FALL_FDET3_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET3_Pos) /*!< GPIO_PIN_INT FALL: FDET3 Mask */ -#define GPIO_PIN_INT_FALL_FDET4_Pos 4 /*!< GPIO_PIN_INT FALL: FDET4 Position */ -#define GPIO_PIN_INT_FALL_FDET4_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET4_Pos) /*!< GPIO_PIN_INT FALL: FDET4 Mask */ -#define GPIO_PIN_INT_FALL_FDET5_Pos 5 /*!< GPIO_PIN_INT FALL: FDET5 Position */ -#define GPIO_PIN_INT_FALL_FDET5_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET5_Pos) /*!< GPIO_PIN_INT FALL: FDET5 Mask */ -#define GPIO_PIN_INT_FALL_FDET6_Pos 6 /*!< GPIO_PIN_INT FALL: FDET6 Position */ -#define GPIO_PIN_INT_FALL_FDET6_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET6_Pos) /*!< GPIO_PIN_INT FALL: FDET6 Mask */ -#define GPIO_PIN_INT_FALL_FDET7_Pos 7 /*!< GPIO_PIN_INT FALL: FDET7 Position */ -#define GPIO_PIN_INT_FALL_FDET7_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET7_Pos) /*!< GPIO_PIN_INT FALL: FDET7 Mask */ - -// ------------------------------------ GPIO_PIN_INT_IST ---------------------------------------- -#define GPIO_PIN_INT_IST_PSTAT0_Pos 0 /*!< GPIO_PIN_INT IST: PSTAT0 Position */ -#define GPIO_PIN_INT_IST_PSTAT0_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT0_Pos) /*!< GPIO_PIN_INT IST: PSTAT0 Mask */ -#define GPIO_PIN_INT_IST_PSTAT1_Pos 1 /*!< GPIO_PIN_INT IST: PSTAT1 Position */ -#define GPIO_PIN_INT_IST_PSTAT1_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT1_Pos) /*!< GPIO_PIN_INT IST: PSTAT1 Mask */ -#define GPIO_PIN_INT_IST_PSTAT2_Pos 2 /*!< GPIO_PIN_INT IST: PSTAT2 Position */ -#define GPIO_PIN_INT_IST_PSTAT2_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT2_Pos) /*!< GPIO_PIN_INT IST: PSTAT2 Mask */ -#define GPIO_PIN_INT_IST_PSTAT3_Pos 3 /*!< GPIO_PIN_INT IST: PSTAT3 Position */ -#define GPIO_PIN_INT_IST_PSTAT3_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT3_Pos) /*!< GPIO_PIN_INT IST: PSTAT3 Mask */ -#define GPIO_PIN_INT_IST_PSTAT4_Pos 4 /*!< GPIO_PIN_INT IST: PSTAT4 Position */ -#define GPIO_PIN_INT_IST_PSTAT4_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT4_Pos) /*!< GPIO_PIN_INT IST: PSTAT4 Mask */ -#define GPIO_PIN_INT_IST_PSTAT5_Pos 5 /*!< GPIO_PIN_INT IST: PSTAT5 Position */ -#define GPIO_PIN_INT_IST_PSTAT5_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT5_Pos) /*!< GPIO_PIN_INT IST: PSTAT5 Mask */ -#define GPIO_PIN_INT_IST_PSTAT6_Pos 6 /*!< GPIO_PIN_INT IST: PSTAT6 Position */ -#define GPIO_PIN_INT_IST_PSTAT6_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT6_Pos) /*!< GPIO_PIN_INT IST: PSTAT6 Mask */ -#define GPIO_PIN_INT_IST_PSTAT7_Pos 7 /*!< GPIO_PIN_INT IST: PSTAT7 Position */ -#define GPIO_PIN_INT_IST_PSTAT7_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT7_Pos) /*!< GPIO_PIN_INT IST: PSTAT7 Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_GROUP_INTn Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------- GPIO_GROUP_INTn_CTRL -------------------------------------- -#define GPIO_GROUP_INTn_CTRL_INT_Pos 0 /*!< GPIO_GROUP_INTn CTRL: INT Position */ -#define GPIO_GROUP_INTn_CTRL_INT_Msk (0x01UL << GPIO_GROUP_INTn_CTRL_INT_Pos) /*!< GPIO_GROUP_INTn CTRL: INT Mask */ -#define GPIO_GROUP_INTn_CTRL_COMB_Pos 1 /*!< GPIO_GROUP_INTn CTRL: COMB Position */ -#define GPIO_GROUP_INTn_CTRL_COMB_Msk (0x01UL << GPIO_GROUP_INTn_CTRL_COMB_Pos) /*!< GPIO_GROUP_INTn CTRL: COMB Mask */ -#define GPIO_GROUP_INTn_CTRL_TRIG_Pos 2 /*!< GPIO_GROUP_INTn CTRL: TRIG Position */ -#define GPIO_GROUP_INTn_CTRL_TRIG_Msk (0x01UL << GPIO_GROUP_INTn_CTRL_TRIG_Pos) /*!< GPIO_GROUP_INTn CTRL: TRIG Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_POL0 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Mask */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Position */ -#define GPIO_GROUP_INTn_PORT_POL0_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_POL1 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Mask */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Position */ -#define GPIO_GROUP_INTn_PORT_POL1_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_POL2 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Mask */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Position */ -#define GPIO_GROUP_INTn_PORT_POL2_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_POL3 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Mask */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Position */ -#define GPIO_GROUP_INTn_PORT_POL3_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_POL4 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Mask */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Position */ -#define GPIO_GROUP_INTn_PORT_POL4_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_POL5 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Mask */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Position */ -#define GPIO_GROUP_INTn_PORT_POL5_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_POL6 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Mask */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Position */ -#define GPIO_GROUP_INTn_PORT_POL6_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_POL7 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Mask */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Position */ -#define GPIO_GROUP_INTn_PORT_POL7_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_ENA0 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Position */ -#define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_ENA1 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Position */ -#define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_ENA2 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Position */ -#define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_ENA3 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Position */ -#define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_ENA4 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Position */ -#define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_ENA5 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Position */ -#define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_ENA6 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Position */ -#define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INTn_PORT_ENA7 ----------------------------------- -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Mask */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Position */ -#define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_GROUP_INT1 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------- GPIO_GROUP_INT1_CTRL -------------------------------------- -#define GPIO_GROUP_INT1_CTRL_INT_Pos 0 /*!< GPIO_GROUP_INT1 CTRL: INT Position */ -#define GPIO_GROUP_INT1_CTRL_INT_Msk (0x01UL << GPIO_GROUP_INT1_CTRL_INT_Pos) /*!< GPIO_GROUP_INT1 CTRL: INT Mask */ -#define GPIO_GROUP_INT1_CTRL_COMB_Pos 1 /*!< GPIO_GROUP_INT1 CTRL: COMB Position */ -#define GPIO_GROUP_INT1_CTRL_COMB_Msk (0x01UL << GPIO_GROUP_INT1_CTRL_COMB_Pos) /*!< GPIO_GROUP_INT1 CTRL: COMB Mask */ -#define GPIO_GROUP_INT1_CTRL_TRIG_Pos 2 /*!< GPIO_GROUP_INT1 CTRL: TRIG Position */ -#define GPIO_GROUP_INT1_CTRL_TRIG_Msk (0x01UL << GPIO_GROUP_INT1_CTRL_TRIG_Pos) /*!< GPIO_GROUP_INT1 CTRL: TRIG Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_POL0 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Mask */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Position */ -#define GPIO_GROUP_INT1_PORT_POL0_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_POL1 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Mask */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Position */ -#define GPIO_GROUP_INT1_PORT_POL1_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_POL2 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Mask */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Position */ -#define GPIO_GROUP_INT1_PORT_POL2_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_POL3 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Mask */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Position */ -#define GPIO_GROUP_INT1_PORT_POL3_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_POL4 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Mask */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Position */ -#define GPIO_GROUP_INT1_PORT_POL4_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_POL5 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Mask */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Position */ -#define GPIO_GROUP_INT1_PORT_POL5_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_POL6 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Mask */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Position */ -#define GPIO_GROUP_INT1_PORT_POL6_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_POL7 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Mask */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Position */ -#define GPIO_GROUP_INT1_PORT_POL7_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_ENA0 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_29 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_29 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_30 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_30 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_31 Position */ -#define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_ENA1 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_0 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_0 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_1 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_1 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_2 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_2 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_3 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_3 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_4 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_4 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_5 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_5 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_6 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_6 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_7 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_7 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_8 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_8 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_9 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_9 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_10 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_10 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_11 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_11 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_12 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_12 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_13 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_13 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_14 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_14 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_15 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_15 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_16 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_16 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_17 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_17 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_18 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_18 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_19 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_19 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_20 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_20 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_21 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_21 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_22 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_22 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_23 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_23 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_24 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_24 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_25 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_25 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_26 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_26 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_27 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_27 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_28 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_28 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_29 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_29 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_30 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_30 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_31 Position */ -#define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_ENA2 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_0 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_0 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_1 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_1 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_2 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_2 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_3 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_3 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_4 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_4 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_5 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_5 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_6 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_6 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_7 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_7 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_8 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_8 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_9 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_9 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_10 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_10 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_11 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_11 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_12 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_12 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_13 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_13 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_14 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_14 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_15 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_15 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_16 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_16 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_17 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_17 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_18 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_18 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_19 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_19 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_20 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_20 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_21 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_21 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_22 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_22 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_23 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_23 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_24 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_24 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_25 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_25 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_26 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_26 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_27 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_27 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_28 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_28 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_29 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_29 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_30 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_30 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_31 Position */ -#define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_ENA3 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_0 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_0 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_1 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_1 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_2 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_2 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_3 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_3 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_4 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_4 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_5 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_5 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_6 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_6 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_7 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_7 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_8 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_8 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_9 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_9 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_10 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_10 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_11 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_11 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_12 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_12 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_13 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_13 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_14 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_14 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_15 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_15 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_16 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_16 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_17 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_17 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_18 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_18 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_19 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_19 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_20 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_20 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_21 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_21 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_22 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_22 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_23 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_23 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_24 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_24 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_25 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_25 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_26 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_26 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_27 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_27 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_28 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_28 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_29 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_29 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_30 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_30 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_31 Position */ -#define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_ENA4 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_0 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_0 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_1 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_1 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_2 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_2 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_3 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_3 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_4 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_4 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_5 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_5 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_6 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_6 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_7 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_7 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_8 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_8 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_9 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_9 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_10 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_10 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_11 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_11 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_12 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_12 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_13 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_13 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_14 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_14 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_15 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_15 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_16 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_16 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_17 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_17 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_18 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_18 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_19 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_19 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_20 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_20 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_21 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_21 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_22 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_22 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_23 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_23 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_24 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_24 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_25 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_25 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_26 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_26 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_27 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_27 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_28 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_28 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_29 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_29 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_30 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_30 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_31 Position */ -#define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_ENA5 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_0 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_0 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_1 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_1 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_2 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_2 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_3 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_3 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_4 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_4 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_5 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_5 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_6 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_6 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_7 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_7 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_8 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_8 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_9 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_9 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_10 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_10 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_11 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_11 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_12 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_12 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_13 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_13 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_14 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_14 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_15 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_15 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_16 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_16 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_17 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_17 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_18 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_18 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_19 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_19 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_20 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_20 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_21 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_21 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_22 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_22 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_23 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_23 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_24 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_24 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_25 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_25 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_26 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_26 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_27 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_27 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_28 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_28 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_29 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_29 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_30 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_30 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_31 Position */ -#define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_ENA6 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_0 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_0 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_1 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_1 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_2 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_2 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_3 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_3 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_4 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_4 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_5 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_5 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_6 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_6 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_7 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_7 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_8 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_8 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_9 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_9 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_10 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_10 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_11 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_11 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_12 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_12 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_13 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_13 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_14 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_14 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_15 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_15 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_16 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_16 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_17 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_17 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_18 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_18 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_19 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_19 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_20 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_20 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_21 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_21 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_22 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_22 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_23 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_23 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_24 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_24 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_25 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_25 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_26 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_26 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_27 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_27 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_28 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_28 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_29 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_29 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_30 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_30 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_31 Position */ -#define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_31 Mask */ - -// -------------------------------- GPIO_GROUP_INT1_PORT_ENA7 ----------------------------------- -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_0 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_0 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_1 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_1 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_2 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_2 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_3 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_3 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_4 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_4 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_5 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_5 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_6 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_6 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_7 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_7 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_8 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_8 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_9 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_9 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_10 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_10 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_11 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_11 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_12 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_12 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_13 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_13 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_14 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_14 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_15 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_15 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_16 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_16 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_17 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_17 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_18 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_18 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_19 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_19 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_20 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_20 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_21 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_21 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_22 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_22 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_23 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_23 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_24 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_24 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_25 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_25 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_26 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_26 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_27 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_27 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_28 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_28 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_29 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_29 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_30 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_30 Mask */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_31 Position */ -#define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_31 Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- MCPWM Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- MCPWM_CON ------------------------------------------- -#define MCPWM_CON_RUN0_Pos 0 /*!< MCPWM CON: RUN0 Position */ -#define MCPWM_CON_RUN0_Msk (0x01UL << MCPWM_CON_RUN0_Pos) /*!< MCPWM CON: RUN0 Mask */ -#define MCPWM_CON_CENTER0_Pos 1 /*!< MCPWM CON: CENTER0 Position */ -#define MCPWM_CON_CENTER0_Msk (0x01UL << MCPWM_CON_CENTER0_Pos) /*!< MCPWM CON: CENTER0 Mask */ -#define MCPWM_CON_POLA0_Pos 2 /*!< MCPWM CON: POLA0 Position */ -#define MCPWM_CON_POLA0_Msk (0x01UL << MCPWM_CON_POLA0_Pos) /*!< MCPWM CON: POLA0 Mask */ -#define MCPWM_CON_DTE0_Pos 3 /*!< MCPWM CON: DTE0 Position */ -#define MCPWM_CON_DTE0_Msk (0x01UL << MCPWM_CON_DTE0_Pos) /*!< MCPWM CON: DTE0 Mask */ -#define MCPWM_CON_DISUP0_Pos 4 /*!< MCPWM CON: DISUP0 Position */ -#define MCPWM_CON_DISUP0_Msk (0x01UL << MCPWM_CON_DISUP0_Pos) /*!< MCPWM CON: DISUP0 Mask */ -#define MCPWM_CON_RUN1_Pos 8 /*!< MCPWM CON: RUN1 Position */ -#define MCPWM_CON_RUN1_Msk (0x01UL << MCPWM_CON_RUN1_Pos) /*!< MCPWM CON: RUN1 Mask */ -#define MCPWM_CON_CENTER1_Pos 9 /*!< MCPWM CON: CENTER1 Position */ -#define MCPWM_CON_CENTER1_Msk (0x01UL << MCPWM_CON_CENTER1_Pos) /*!< MCPWM CON: CENTER1 Mask */ -#define MCPWM_CON_POLA1_Pos 10 /*!< MCPWM CON: POLA1 Position */ -#define MCPWM_CON_POLA1_Msk (0x01UL << MCPWM_CON_POLA1_Pos) /*!< MCPWM CON: POLA1 Mask */ -#define MCPWM_CON_DTE1_Pos 11 /*!< MCPWM CON: DTE1 Position */ -#define MCPWM_CON_DTE1_Msk (0x01UL << MCPWM_CON_DTE1_Pos) /*!< MCPWM CON: DTE1 Mask */ -#define MCPWM_CON_DISUP1_Pos 12 /*!< MCPWM CON: DISUP1 Position */ -#define MCPWM_CON_DISUP1_Msk (0x01UL << MCPWM_CON_DISUP1_Pos) /*!< MCPWM CON: DISUP1 Mask */ -#define MCPWM_CON_RUN2_Pos 16 /*!< MCPWM CON: RUN2 Position */ -#define MCPWM_CON_RUN2_Msk (0x01UL << MCPWM_CON_RUN2_Pos) /*!< MCPWM CON: RUN2 Mask */ -#define MCPWM_CON_CENTER2_Pos 17 /*!< MCPWM CON: CENTER2 Position */ -#define MCPWM_CON_CENTER2_Msk (0x01UL << MCPWM_CON_CENTER2_Pos) /*!< MCPWM CON: CENTER2 Mask */ -#define MCPWM_CON_POLA2_Pos 18 /*!< MCPWM CON: POLA2 Position */ -#define MCPWM_CON_POLA2_Msk (0x01UL << MCPWM_CON_POLA2_Pos) /*!< MCPWM CON: POLA2 Mask */ -#define MCPWM_CON_DTE2_Pos 19 /*!< MCPWM CON: DTE2 Position */ -#define MCPWM_CON_DTE2_Msk (0x01UL << MCPWM_CON_DTE2_Pos) /*!< MCPWM CON: DTE2 Mask */ -#define MCPWM_CON_DISUP2_Pos 20 /*!< MCPWM CON: DISUP2 Position */ -#define MCPWM_CON_DISUP2_Msk (0x01UL << MCPWM_CON_DISUP2_Pos) /*!< MCPWM CON: DISUP2 Mask */ -#define MCPWM_CON_INVBDC_Pos 29 /*!< MCPWM CON: INVBDC Position */ -#define MCPWM_CON_INVBDC_Msk (0x01UL << MCPWM_CON_INVBDC_Pos) /*!< MCPWM CON: INVBDC Mask */ -#define MCPWM_CON_ACMODE_Pos 30 /*!< MCPWM CON: ACMODE Position */ -#define MCPWM_CON_ACMODE_Msk (0x01UL << MCPWM_CON_ACMODE_Pos) /*!< MCPWM CON: ACMODE Mask */ -#define MCPWM_CON_DCMODE_Pos 31 /*!< MCPWM CON: DCMODE Position */ -#define MCPWM_CON_DCMODE_Msk (0x01UL << MCPWM_CON_DCMODE_Pos) /*!< MCPWM CON: DCMODE Mask */ - -// -------------------------------------- MCPWM_CON_SET ----------------------------------------- -#define MCPWM_CON_SET_RUN0_SET_Pos 0 /*!< MCPWM CON_SET: RUN0_SET Position */ -#define MCPWM_CON_SET_RUN0_SET_Msk (0x01UL << MCPWM_CON_SET_RUN0_SET_Pos) /*!< MCPWM CON_SET: RUN0_SET Mask */ -#define MCPWM_CON_SET_CENTER0_SET_Pos 1 /*!< MCPWM CON_SET: CENTER0_SET Position */ -#define MCPWM_CON_SET_CENTER0_SET_Msk (0x01UL << MCPWM_CON_SET_CENTER0_SET_Pos) /*!< MCPWM CON_SET: CENTER0_SET Mask */ -#define MCPWM_CON_SET_POLA0_SET_Pos 2 /*!< MCPWM CON_SET: POLA0_SET Position */ -#define MCPWM_CON_SET_POLA0_SET_Msk (0x01UL << MCPWM_CON_SET_POLA0_SET_Pos) /*!< MCPWM CON_SET: POLA0_SET Mask */ -#define MCPWM_CON_SET_DTE0_SET_Pos 3 /*!< MCPWM CON_SET: DTE0_SET Position */ -#define MCPWM_CON_SET_DTE0_SET_Msk (0x01UL << MCPWM_CON_SET_DTE0_SET_Pos) /*!< MCPWM CON_SET: DTE0_SET Mask */ -#define MCPWM_CON_SET_DISUP0_SET_Pos 4 /*!< MCPWM CON_SET: DISUP0_SET Position */ -#define MCPWM_CON_SET_DISUP0_SET_Msk (0x01UL << MCPWM_CON_SET_DISUP0_SET_Pos) /*!< MCPWM CON_SET: DISUP0_SET Mask */ -#define MCPWM_CON_SET_RUN1_SET_Pos 8 /*!< MCPWM CON_SET: RUN1_SET Position */ -#define MCPWM_CON_SET_RUN1_SET_Msk (0x01UL << MCPWM_CON_SET_RUN1_SET_Pos) /*!< MCPWM CON_SET: RUN1_SET Mask */ -#define MCPWM_CON_SET_CENTER1_SET_Pos 9 /*!< MCPWM CON_SET: CENTER1_SET Position */ -#define MCPWM_CON_SET_CENTER1_SET_Msk (0x01UL << MCPWM_CON_SET_CENTER1_SET_Pos) /*!< MCPWM CON_SET: CENTER1_SET Mask */ -#define MCPWM_CON_SET_POLA1_SET_Pos 10 /*!< MCPWM CON_SET: POLA1_SET Position */ -#define MCPWM_CON_SET_POLA1_SET_Msk (0x01UL << MCPWM_CON_SET_POLA1_SET_Pos) /*!< MCPWM CON_SET: POLA1_SET Mask */ -#define MCPWM_CON_SET_DTE1_SET_Pos 11 /*!< MCPWM CON_SET: DTE1_SET Position */ -#define MCPWM_CON_SET_DTE1_SET_Msk (0x01UL << MCPWM_CON_SET_DTE1_SET_Pos) /*!< MCPWM CON_SET: DTE1_SET Mask */ -#define MCPWM_CON_SET_DISUP1_SET_Pos 12 /*!< MCPWM CON_SET: DISUP1_SET Position */ -#define MCPWM_CON_SET_DISUP1_SET_Msk (0x01UL << MCPWM_CON_SET_DISUP1_SET_Pos) /*!< MCPWM CON_SET: DISUP1_SET Mask */ -#define MCPWM_CON_SET_RUN2_SET_Pos 16 /*!< MCPWM CON_SET: RUN2_SET Position */ -#define MCPWM_CON_SET_RUN2_SET_Msk (0x01UL << MCPWM_CON_SET_RUN2_SET_Pos) /*!< MCPWM CON_SET: RUN2_SET Mask */ -#define MCPWM_CON_SET_CENTER2_SET_Pos 17 /*!< MCPWM CON_SET: CENTER2_SET Position */ -#define MCPWM_CON_SET_CENTER2_SET_Msk (0x01UL << MCPWM_CON_SET_CENTER2_SET_Pos) /*!< MCPWM CON_SET: CENTER2_SET Mask */ -#define MCPWM_CON_SET_POLA2_SET_Pos 18 /*!< MCPWM CON_SET: POLA2_SET Position */ -#define MCPWM_CON_SET_POLA2_SET_Msk (0x01UL << MCPWM_CON_SET_POLA2_SET_Pos) /*!< MCPWM CON_SET: POLA2_SET Mask */ -#define MCPWM_CON_SET_DTE2_SET_Pos 19 /*!< MCPWM CON_SET: DTE2_SET Position */ -#define MCPWM_CON_SET_DTE2_SET_Msk (0x01UL << MCPWM_CON_SET_DTE2_SET_Pos) /*!< MCPWM CON_SET: DTE2_SET Mask */ -#define MCPWM_CON_SET_DISUP2_SET_Pos 20 /*!< MCPWM CON_SET: DISUP2_SET Position */ -#define MCPWM_CON_SET_DISUP2_SET_Msk (0x01UL << MCPWM_CON_SET_DISUP2_SET_Pos) /*!< MCPWM CON_SET: DISUP2_SET Mask */ -#define MCPWM_CON_SET_INVBDC_SET_Pos 29 /*!< MCPWM CON_SET: INVBDC_SET Position */ -#define MCPWM_CON_SET_INVBDC_SET_Msk (0x01UL << MCPWM_CON_SET_INVBDC_SET_Pos) /*!< MCPWM CON_SET: INVBDC_SET Mask */ -#define MCPWM_CON_SET_ACMODE_SET_Pos 30 /*!< MCPWM CON_SET: ACMODE_SET Position */ -#define MCPWM_CON_SET_ACMODE_SET_Msk (0x01UL << MCPWM_CON_SET_ACMODE_SET_Pos) /*!< MCPWM CON_SET: ACMODE_SET Mask */ -#define MCPWM_CON_SET_DCMODE_SET_Pos 31 /*!< MCPWM CON_SET: DCMODE_SET Position */ -#define MCPWM_CON_SET_DCMODE_SET_Msk (0x01UL << MCPWM_CON_SET_DCMODE_SET_Pos) /*!< MCPWM CON_SET: DCMODE_SET Mask */ - -// -------------------------------------- MCPWM_CON_CLR ----------------------------------------- -#define MCPWM_CON_CLR_RUN0_CLR_Pos 0 /*!< MCPWM CON_CLR: RUN0_CLR Position */ -#define MCPWM_CON_CLR_RUN0_CLR_Msk (0x01UL << MCPWM_CON_CLR_RUN0_CLR_Pos) /*!< MCPWM CON_CLR: RUN0_CLR Mask */ -#define MCPWM_CON_CLR_CENTER0_CLR_Pos 1 /*!< MCPWM CON_CLR: CENTER0_CLR Position */ -#define MCPWM_CON_CLR_CENTER0_CLR_Msk (0x01UL << MCPWM_CON_CLR_CENTER0_CLR_Pos) /*!< MCPWM CON_CLR: CENTER0_CLR Mask */ -#define MCPWM_CON_CLR_POLA0_CLR_Pos 2 /*!< MCPWM CON_CLR: POLA0_CLR Position */ -#define MCPWM_CON_CLR_POLA0_CLR_Msk (0x01UL << MCPWM_CON_CLR_POLA0_CLR_Pos) /*!< MCPWM CON_CLR: POLA0_CLR Mask */ -#define MCPWM_CON_CLR_DTE0_CLR_Pos 3 /*!< MCPWM CON_CLR: DTE0_CLR Position */ -#define MCPWM_CON_CLR_DTE0_CLR_Msk (0x01UL << MCPWM_CON_CLR_DTE0_CLR_Pos) /*!< MCPWM CON_CLR: DTE0_CLR Mask */ -#define MCPWM_CON_CLR_DISUP0_CLR_Pos 4 /*!< MCPWM CON_CLR: DISUP0_CLR Position */ -#define MCPWM_CON_CLR_DISUP0_CLR_Msk (0x01UL << MCPWM_CON_CLR_DISUP0_CLR_Pos) /*!< MCPWM CON_CLR: DISUP0_CLR Mask */ -#define MCPWM_CON_CLR_RUN1_CLR_Pos 8 /*!< MCPWM CON_CLR: RUN1_CLR Position */ -#define MCPWM_CON_CLR_RUN1_CLR_Msk (0x01UL << MCPWM_CON_CLR_RUN1_CLR_Pos) /*!< MCPWM CON_CLR: RUN1_CLR Mask */ -#define MCPWM_CON_CLR_CENTER1_CLR_Pos 9 /*!< MCPWM CON_CLR: CENTER1_CLR Position */ -#define MCPWM_CON_CLR_CENTER1_CLR_Msk (0x01UL << MCPWM_CON_CLR_CENTER1_CLR_Pos) /*!< MCPWM CON_CLR: CENTER1_CLR Mask */ -#define MCPWM_CON_CLR_POLA1_CLR_Pos 10 /*!< MCPWM CON_CLR: POLA1_CLR Position */ -#define MCPWM_CON_CLR_POLA1_CLR_Msk (0x01UL << MCPWM_CON_CLR_POLA1_CLR_Pos) /*!< MCPWM CON_CLR: POLA1_CLR Mask */ -#define MCPWM_CON_CLR_DTE1_CLR_Pos 11 /*!< MCPWM CON_CLR: DTE1_CLR Position */ -#define MCPWM_CON_CLR_DTE1_CLR_Msk (0x01UL << MCPWM_CON_CLR_DTE1_CLR_Pos) /*!< MCPWM CON_CLR: DTE1_CLR Mask */ -#define MCPWM_CON_CLR_DISUP1_CLR_Pos 12 /*!< MCPWM CON_CLR: DISUP1_CLR Position */ -#define MCPWM_CON_CLR_DISUP1_CLR_Msk (0x01UL << MCPWM_CON_CLR_DISUP1_CLR_Pos) /*!< MCPWM CON_CLR: DISUP1_CLR Mask */ -#define MCPWM_CON_CLR_RUN2_CLR_Pos 16 /*!< MCPWM CON_CLR: RUN2_CLR Position */ -#define MCPWM_CON_CLR_RUN2_CLR_Msk (0x01UL << MCPWM_CON_CLR_RUN2_CLR_Pos) /*!< MCPWM CON_CLR: RUN2_CLR Mask */ -#define MCPWM_CON_CLR_CENTER2_CLR_Pos 17 /*!< MCPWM CON_CLR: CENTER2_CLR Position */ -#define MCPWM_CON_CLR_CENTER2_CLR_Msk (0x01UL << MCPWM_CON_CLR_CENTER2_CLR_Pos) /*!< MCPWM CON_CLR: CENTER2_CLR Mask */ -#define MCPWM_CON_CLR_POLA2_CLR_Pos 18 /*!< MCPWM CON_CLR: POLA2_CLR Position */ -#define MCPWM_CON_CLR_POLA2_CLR_Msk (0x01UL << MCPWM_CON_CLR_POLA2_CLR_Pos) /*!< MCPWM CON_CLR: POLA2_CLR Mask */ -#define MCPWM_CON_CLR_DTE2_CLR_Pos 19 /*!< MCPWM CON_CLR: DTE2_CLR Position */ -#define MCPWM_CON_CLR_DTE2_CLR_Msk (0x01UL << MCPWM_CON_CLR_DTE2_CLR_Pos) /*!< MCPWM CON_CLR: DTE2_CLR Mask */ -#define MCPWM_CON_CLR_DISUP2_CLR_Pos 20 /*!< MCPWM CON_CLR: DISUP2_CLR Position */ -#define MCPWM_CON_CLR_DISUP2_CLR_Msk (0x01UL << MCPWM_CON_CLR_DISUP2_CLR_Pos) /*!< MCPWM CON_CLR: DISUP2_CLR Mask */ -#define MCPWM_CON_CLR_INVBDC_CLR_Pos 29 /*!< MCPWM CON_CLR: INVBDC_CLR Position */ -#define MCPWM_CON_CLR_INVBDC_CLR_Msk (0x01UL << MCPWM_CON_CLR_INVBDC_CLR_Pos) /*!< MCPWM CON_CLR: INVBDC_CLR Mask */ -#define MCPWM_CON_CLR_ACMOD_CLR_Pos 30 /*!< MCPWM CON_CLR: ACMOD_CLR Position */ -#define MCPWM_CON_CLR_ACMOD_CLR_Msk (0x01UL << MCPWM_CON_CLR_ACMOD_CLR_Pos) /*!< MCPWM CON_CLR: ACMOD_CLR Mask */ -#define MCPWM_CON_CLR_DCMODE_CLR_Pos 31 /*!< MCPWM CON_CLR: DCMODE_CLR Position */ -#define MCPWM_CON_CLR_DCMODE_CLR_Msk (0x01UL << MCPWM_CON_CLR_DCMODE_CLR_Pos) /*!< MCPWM CON_CLR: DCMODE_CLR Mask */ - -// -------------------------------------- MCPWM_CAPCON ------------------------------------------ -#define MCPWM_CAPCON_CAP0MCI0_RE_Pos 0 /*!< MCPWM CAPCON: CAP0MCI0_RE Position */ -#define MCPWM_CAPCON_CAP0MCI0_RE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI0_RE_Pos) /*!< MCPWM CAPCON: CAP0MCI0_RE Mask */ -#define MCPWM_CAPCON_CAP0MCI0_FE_Pos 1 /*!< MCPWM CAPCON: CAP0MCI0_FE Position */ -#define MCPWM_CAPCON_CAP0MCI0_FE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI0_FE_Pos) /*!< MCPWM CAPCON: CAP0MCI0_FE Mask */ -#define MCPWM_CAPCON_CAP0MCI1_RE_Pos 2 /*!< MCPWM CAPCON: CAP0MCI1_RE Position */ -#define MCPWM_CAPCON_CAP0MCI1_RE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI1_RE_Pos) /*!< MCPWM CAPCON: CAP0MCI1_RE Mask */ -#define MCPWM_CAPCON_CAP0MCI1_FE_Pos 3 /*!< MCPWM CAPCON: CAP0MCI1_FE Position */ -#define MCPWM_CAPCON_CAP0MCI1_FE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI1_FE_Pos) /*!< MCPWM CAPCON: CAP0MCI1_FE Mask */ -#define MCPWM_CAPCON_CAP0MCI2_RE_Pos 4 /*!< MCPWM CAPCON: CAP0MCI2_RE Position */ -#define MCPWM_CAPCON_CAP0MCI2_RE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI2_RE_Pos) /*!< MCPWM CAPCON: CAP0MCI2_RE Mask */ -#define MCPWM_CAPCON_CAP0MCI2_FE_Pos 5 /*!< MCPWM CAPCON: CAP0MCI2_FE Position */ -#define MCPWM_CAPCON_CAP0MCI2_FE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI2_FE_Pos) /*!< MCPWM CAPCON: CAP0MCI2_FE Mask */ -#define MCPWM_CAPCON_CAP1MCI0_RE_Pos 6 /*!< MCPWM CAPCON: CAP1MCI0_RE Position */ -#define MCPWM_CAPCON_CAP1MCI0_RE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI0_RE_Pos) /*!< MCPWM CAPCON: CAP1MCI0_RE Mask */ -#define MCPWM_CAPCON_CAP1MCI0_FE_Pos 7 /*!< MCPWM CAPCON: CAP1MCI0_FE Position */ -#define MCPWM_CAPCON_CAP1MCI0_FE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI0_FE_Pos) /*!< MCPWM CAPCON: CAP1MCI0_FE Mask */ -#define MCPWM_CAPCON_CAP1MCI1_RE_Pos 8 /*!< MCPWM CAPCON: CAP1MCI1_RE Position */ -#define MCPWM_CAPCON_CAP1MCI1_RE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI1_RE_Pos) /*!< MCPWM CAPCON: CAP1MCI1_RE Mask */ -#define MCPWM_CAPCON_CAP1MCI1_FE_Pos 9 /*!< MCPWM CAPCON: CAP1MCI1_FE Position */ -#define MCPWM_CAPCON_CAP1MCI1_FE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI1_FE_Pos) /*!< MCPWM CAPCON: CAP1MCI1_FE Mask */ -#define MCPWM_CAPCON_CAP1MCI2_RE_Pos 10 /*!< MCPWM CAPCON: CAP1MCI2_RE Position */ -#define MCPWM_CAPCON_CAP1MCI2_RE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI2_RE_Pos) /*!< MCPWM CAPCON: CAP1MCI2_RE Mask */ -#define MCPWM_CAPCON_CAP1MCI2_FE_Pos 11 /*!< MCPWM CAPCON: CAP1MCI2_FE Position */ -#define MCPWM_CAPCON_CAP1MCI2_FE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI2_FE_Pos) /*!< MCPWM CAPCON: CAP1MCI2_FE Mask */ -#define MCPWM_CAPCON_CAP2MCI0_RE_Pos 12 /*!< MCPWM CAPCON: CAP2MCI0_RE Position */ -#define MCPWM_CAPCON_CAP2MCI0_RE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI0_RE_Pos) /*!< MCPWM CAPCON: CAP2MCI0_RE Mask */ -#define MCPWM_CAPCON_CAP2MCI0_FE_Pos 13 /*!< MCPWM CAPCON: CAP2MCI0_FE Position */ -#define MCPWM_CAPCON_CAP2MCI0_FE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI0_FE_Pos) /*!< MCPWM CAPCON: CAP2MCI0_FE Mask */ -#define MCPWM_CAPCON_CAP2MCI1_RE_Pos 14 /*!< MCPWM CAPCON: CAP2MCI1_RE Position */ -#define MCPWM_CAPCON_CAP2MCI1_RE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI1_RE_Pos) /*!< MCPWM CAPCON: CAP2MCI1_RE Mask */ -#define MCPWM_CAPCON_CAP2MCI1_FE_Pos 15 /*!< MCPWM CAPCON: CAP2MCI1_FE Position */ -#define MCPWM_CAPCON_CAP2MCI1_FE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI1_FE_Pos) /*!< MCPWM CAPCON: CAP2MCI1_FE Mask */ -#define MCPWM_CAPCON_CAP2MCI2_RE_Pos 16 /*!< MCPWM CAPCON: CAP2MCI2_RE Position */ -#define MCPWM_CAPCON_CAP2MCI2_RE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI2_RE_Pos) /*!< MCPWM CAPCON: CAP2MCI2_RE Mask */ -#define MCPWM_CAPCON_CAP2MCI2_FE_Pos 17 /*!< MCPWM CAPCON: CAP2MCI2_FE Position */ -#define MCPWM_CAPCON_CAP2MCI2_FE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI2_FE_Pos) /*!< MCPWM CAPCON: CAP2MCI2_FE Mask */ -#define MCPWM_CAPCON_RT0_Pos 18 /*!< MCPWM CAPCON: RT0 Position */ -#define MCPWM_CAPCON_RT0_Msk (0x01UL << MCPWM_CAPCON_RT0_Pos) /*!< MCPWM CAPCON: RT0 Mask */ -#define MCPWM_CAPCON_RT1_Pos 19 /*!< MCPWM CAPCON: RT1 Position */ -#define MCPWM_CAPCON_RT1_Msk (0x01UL << MCPWM_CAPCON_RT1_Pos) /*!< MCPWM CAPCON: RT1 Mask */ -#define MCPWM_CAPCON_RT2_Pos 20 /*!< MCPWM CAPCON: RT2 Position */ -#define MCPWM_CAPCON_RT2_Msk (0x01UL << MCPWM_CAPCON_RT2_Pos) /*!< MCPWM CAPCON: RT2 Mask */ -#define MCPWM_CAPCON_HNFCAP0_Pos 21 /*!< MCPWM CAPCON: HNFCAP0 Position */ -#define MCPWM_CAPCON_HNFCAP0_Msk (0x01UL << MCPWM_CAPCON_HNFCAP0_Pos) /*!< MCPWM CAPCON: HNFCAP0 Mask */ -#define MCPWM_CAPCON_HNFCAP1_Pos 22 /*!< MCPWM CAPCON: HNFCAP1 Position */ -#define MCPWM_CAPCON_HNFCAP1_Msk (0x01UL << MCPWM_CAPCON_HNFCAP1_Pos) /*!< MCPWM CAPCON: HNFCAP1 Mask */ -#define MCPWM_CAPCON_HNFCAP2_Pos 23 /*!< MCPWM CAPCON: HNFCAP2 Position */ -#define MCPWM_CAPCON_HNFCAP2_Msk (0x01UL << MCPWM_CAPCON_HNFCAP2_Pos) /*!< MCPWM CAPCON: HNFCAP2 Mask */ - -// ------------------------------------ MCPWM_CAPCON_SET ---------------------------------------- -#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos 0 /*!< MCPWM CAPCON_SET: CAP0MCI0_RE_SET Position */ -#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI0_RE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos 1 /*!< MCPWM CAPCON_SET: CAP0MCI0_FE_SET Position */ -#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI0_FE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos 2 /*!< MCPWM CAPCON_SET: CAP0MCI1_RE_SET Position */ -#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI1_RE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos 3 /*!< MCPWM CAPCON_SET: CAP0MCI1_FE_SET Position */ -#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI1_FE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos 4 /*!< MCPWM CAPCON_SET: CAP0MCI2_RE_SET Position */ -#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI2_RE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos 5 /*!< MCPWM CAPCON_SET: CAP0MCI2_FE_SET Position */ -#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI2_FE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos 6 /*!< MCPWM CAPCON_SET: CAP1MCI0_RE_SET Position */ -#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI0_RE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos 7 /*!< MCPWM CAPCON_SET: CAP1MCI0_FE_SET Position */ -#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI0_FE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos 8 /*!< MCPWM CAPCON_SET: CAP1MCI1_RE_SET Position */ -#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI1_RE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos 9 /*!< MCPWM CAPCON_SET: CAP1MCI1_FE_SET Position */ -#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI1_FE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos 10 /*!< MCPWM CAPCON_SET: CAP1MCI2_RE_SET Position */ -#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI2_RE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos 11 /*!< MCPWM CAPCON_SET: CAP1MCI2_FE_SET Position */ -#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI2_FE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos 12 /*!< MCPWM CAPCON_SET: CAP2MCI0_RE_SET Position */ -#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI0_RE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos 13 /*!< MCPWM CAPCON_SET: CAP2MCI0_FE_SET Position */ -#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI0_FE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos 14 /*!< MCPWM CAPCON_SET: CAP2MCI1_RE_SET Position */ -#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI1_RE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos 15 /*!< MCPWM CAPCON_SET: CAP2MCI1_FE_SET Position */ -#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI1_FE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos 16 /*!< MCPWM CAPCON_SET: CAP2MCI2_RE_SET Position */ -#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI2_RE_SET Mask */ -#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos 17 /*!< MCPWM CAPCON_SET: CAP2MCI2_FE_SET Position */ -#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI2_FE_SET Mask */ -#define MCPWM_CAPCON_SET_RT0_SET_Pos 18 /*!< MCPWM CAPCON_SET: RT0_SET Position */ -#define MCPWM_CAPCON_SET_RT0_SET_Msk (0x01UL << MCPWM_CAPCON_SET_RT0_SET_Pos) /*!< MCPWM CAPCON_SET: RT0_SET Mask */ -#define MCPWM_CAPCON_SET_RT1_SET_Pos 19 /*!< MCPWM CAPCON_SET: RT1_SET Position */ -#define MCPWM_CAPCON_SET_RT1_SET_Msk (0x01UL << MCPWM_CAPCON_SET_RT1_SET_Pos) /*!< MCPWM CAPCON_SET: RT1_SET Mask */ -#define MCPWM_CAPCON_SET_RT2_SET_Pos 20 /*!< MCPWM CAPCON_SET: RT2_SET Position */ -#define MCPWM_CAPCON_SET_RT2_SET_Msk (0x01UL << MCPWM_CAPCON_SET_RT2_SET_Pos) /*!< MCPWM CAPCON_SET: RT2_SET Mask */ -#define MCPWM_CAPCON_SET_HNFCAP0_SET_Pos 21 /*!< MCPWM CAPCON_SET: HNFCAP0_SET Position */ -#define MCPWM_CAPCON_SET_HNFCAP0_SET_Msk (0x01UL << MCPWM_CAPCON_SET_HNFCAP0_SET_Pos) /*!< MCPWM CAPCON_SET: HNFCAP0_SET Mask */ -#define MCPWM_CAPCON_SET_HNFCAP1_SET_Pos 22 /*!< MCPWM CAPCON_SET: HNFCAP1_SET Position */ -#define MCPWM_CAPCON_SET_HNFCAP1_SET_Msk (0x01UL << MCPWM_CAPCON_SET_HNFCAP1_SET_Pos) /*!< MCPWM CAPCON_SET: HNFCAP1_SET Mask */ -#define MCPWM_CAPCON_SET_HNFCAP2_SET_Pos 23 /*!< MCPWM CAPCON_SET: HNFCAP2_SET Position */ -#define MCPWM_CAPCON_SET_HNFCAP2_SET_Msk (0x01UL << MCPWM_CAPCON_SET_HNFCAP2_SET_Pos) /*!< MCPWM CAPCON_SET: HNFCAP2_SET Mask */ - -// ------------------------------------ MCPWM_CAPCON_CLR ---------------------------------------- -#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos 0 /*!< MCPWM CAPCON_CLR: CAP0MCI0_RE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI0_RE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos 1 /*!< MCPWM CAPCON_CLR: CAP0MCI0_FE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI0_FE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos 2 /*!< MCPWM CAPCON_CLR: CAP0MCI1_RE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI1_RE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos 3 /*!< MCPWM CAPCON_CLR: CAP0MCI1_FE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI1_FE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos 4 /*!< MCPWM CAPCON_CLR: CAP0MCI2_RE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI2_RE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos 5 /*!< MCPWM CAPCON_CLR: CAP0MCI2_FE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI2_FE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos 6 /*!< MCPWM CAPCON_CLR: CAP1MCI0_RE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI0_RE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos 7 /*!< MCPWM CAPCON_CLR: CAP1MCI0_FE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI0_FE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos 8 /*!< MCPWM CAPCON_CLR: CAP1MCI1_RE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI1_RE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos 9 /*!< MCPWM CAPCON_CLR: CAP1MCI1_FE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI1_FE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos 10 /*!< MCPWM CAPCON_CLR: CAP1MCI2_RE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI2_RE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos 11 /*!< MCPWM CAPCON_CLR: CAP1MCI2_FE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI2_FE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos 12 /*!< MCPWM CAPCON_CLR: CAP2MCI0_RE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI0_RE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos 13 /*!< MCPWM CAPCON_CLR: CAP2MCI0_FE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI0_FE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos 14 /*!< MCPWM CAPCON_CLR: CAP2MCI1_RE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI1_RE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos 15 /*!< MCPWM CAPCON_CLR: CAP2MCI1_FE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI1_FE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos 16 /*!< MCPWM CAPCON_CLR: CAP2MCI2_RE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI2_RE_CLR Mask */ -#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos 17 /*!< MCPWM CAPCON_CLR: CAP2MCI2_FE_CLR Position */ -#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI2_FE_CLR Mask */ -#define MCPWM_CAPCON_CLR_RT0_CLR_Pos 18 /*!< MCPWM CAPCON_CLR: RT0_CLR Position */ -#define MCPWM_CAPCON_CLR_RT0_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_RT0_CLR_Pos) /*!< MCPWM CAPCON_CLR: RT0_CLR Mask */ -#define MCPWM_CAPCON_CLR_RT1_CLR_Pos 19 /*!< MCPWM CAPCON_CLR: RT1_CLR Position */ -#define MCPWM_CAPCON_CLR_RT1_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_RT1_CLR_Pos) /*!< MCPWM CAPCON_CLR: RT1_CLR Mask */ -#define MCPWM_CAPCON_CLR_RT2_CLR_Pos 20 /*!< MCPWM CAPCON_CLR: RT2_CLR Position */ -#define MCPWM_CAPCON_CLR_RT2_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_RT2_CLR_Pos) /*!< MCPWM CAPCON_CLR: RT2_CLR Mask */ -#define MCPWM_CAPCON_CLR_HNFCAP0_CLR_Pos 21 /*!< MCPWM CAPCON_CLR: HNFCAP0_CLR Position */ -#define MCPWM_CAPCON_CLR_HNFCAP0_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_HNFCAP0_CLR_Pos) /*!< MCPWM CAPCON_CLR: HNFCAP0_CLR Mask */ -#define MCPWM_CAPCON_CLR_HNFCAP1_CLR_Pos 22 /*!< MCPWM CAPCON_CLR: HNFCAP1_CLR Position */ -#define MCPWM_CAPCON_CLR_HNFCAP1_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_HNFCAP1_CLR_Pos) /*!< MCPWM CAPCON_CLR: HNFCAP1_CLR Mask */ -#define MCPWM_CAPCON_CLR_HNFCAP2_CLR_Pos 23 /*!< MCPWM CAPCON_CLR: HNFCAP2_CLR Position */ -#define MCPWM_CAPCON_CLR_HNFCAP2_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_HNFCAP2_CLR_Pos) /*!< MCPWM CAPCON_CLR: HNFCAP2_CLR Mask */ - -// ---------------------------------------- MCPWM_TC0 ------------------------------------------- -#define MCPWM_TC0_MCTC_Pos 0 /*!< MCPWM TC0: MCTC Position */ -#define MCPWM_TC0_MCTC_Msk (0xffffffffUL << MCPWM_TC0_MCTC_Pos) /*!< MCPWM TC0: MCTC Mask */ - -// ---------------------------------------- MCPWM_TC1 ------------------------------------------- -#define MCPWM_TC1_MCTC_Pos 0 /*!< MCPWM TC1: MCTC Position */ -#define MCPWM_TC1_MCTC_Msk (0xffffffffUL << MCPWM_TC1_MCTC_Pos) /*!< MCPWM TC1: MCTC Mask */ - -// ---------------------------------------- MCPWM_TC2 ------------------------------------------- -#define MCPWM_TC2_MCTC_Pos 0 /*!< MCPWM TC2: MCTC Position */ -#define MCPWM_TC2_MCTC_Msk (0xffffffffUL << MCPWM_TC2_MCTC_Pos) /*!< MCPWM TC2: MCTC Mask */ - -// --------------------------------------- MCPWM_LIM0 ------------------------------------------- -#define MCPWM_LIM0_MCLIM_Pos 0 /*!< MCPWM LIM0: MCLIM Position */ -#define MCPWM_LIM0_MCLIM_Msk (0xffffffffUL << MCPWM_LIM0_MCLIM_Pos) /*!< MCPWM LIM0: MCLIM Mask */ - -// --------------------------------------- MCPWM_LIM1 ------------------------------------------- -#define MCPWM_LIM1_MCLIM_Pos 0 /*!< MCPWM LIM1: MCLIM Position */ -#define MCPWM_LIM1_MCLIM_Msk (0xffffffffUL << MCPWM_LIM1_MCLIM_Pos) /*!< MCPWM LIM1: MCLIM Mask */ - -// --------------------------------------- MCPWM_LIM2 ------------------------------------------- -#define MCPWM_LIM2_MCLIM_Pos 0 /*!< MCPWM LIM2: MCLIM Position */ -#define MCPWM_LIM2_MCLIM_Msk (0xffffffffUL << MCPWM_LIM2_MCLIM_Pos) /*!< MCPWM LIM2: MCLIM Mask */ - -// --------------------------------------- MCPWM_MAT0 ------------------------------------------- -#define MCPWM_MAT0_MCMAT_Pos 0 /*!< MCPWM MAT0: MCMAT Position */ -#define MCPWM_MAT0_MCMAT_Msk (0xffffffffUL << MCPWM_MAT0_MCMAT_Pos) /*!< MCPWM MAT0: MCMAT Mask */ - -// --------------------------------------- MCPWM_MAT1 ------------------------------------------- -#define MCPWM_MAT1_MCMAT_Pos 0 /*!< MCPWM MAT1: MCMAT Position */ -#define MCPWM_MAT1_MCMAT_Msk (0xffffffffUL << MCPWM_MAT1_MCMAT_Pos) /*!< MCPWM MAT1: MCMAT Mask */ - -// --------------------------------------- MCPWM_MAT2 ------------------------------------------- -#define MCPWM_MAT2_MCMAT_Pos 0 /*!< MCPWM MAT2: MCMAT Position */ -#define MCPWM_MAT2_MCMAT_Msk (0xffffffffUL << MCPWM_MAT2_MCMAT_Pos) /*!< MCPWM MAT2: MCMAT Mask */ - -// ---------------------------------------- MCPWM_DT -------------------------------------------- -#define MCPWM_DT_DT0_Pos 0 /*!< MCPWM DT: DT0 Position */ -#define MCPWM_DT_DT0_Msk (0x000003ffUL << MCPWM_DT_DT0_Pos) /*!< MCPWM DT: DT0 Mask */ -#define MCPWM_DT_DT1_Pos 10 /*!< MCPWM DT: DT1 Position */ -#define MCPWM_DT_DT1_Msk (0x000003ffUL << MCPWM_DT_DT1_Pos) /*!< MCPWM DT: DT1 Mask */ -#define MCPWM_DT_DT2_Pos 20 /*!< MCPWM DT: DT2 Position */ -#define MCPWM_DT_DT2_Msk (0x000003ffUL << MCPWM_DT_DT2_Pos) /*!< MCPWM DT: DT2 Mask */ - -// ---------------------------------------- MCPWM_CCP ------------------------------------------- -#define MCPWM_CCP_CCPA0_Pos 0 /*!< MCPWM CCP: CCPA0 Position */ -#define MCPWM_CCP_CCPA0_Msk (0x01UL << MCPWM_CCP_CCPA0_Pos) /*!< MCPWM CCP: CCPA0 Mask */ -#define MCPWM_CCP_CCPB0_Pos 1 /*!< MCPWM CCP: CCPB0 Position */ -#define MCPWM_CCP_CCPB0_Msk (0x01UL << MCPWM_CCP_CCPB0_Pos) /*!< MCPWM CCP: CCPB0 Mask */ -#define MCPWM_CCP_CCPA1_Pos 2 /*!< MCPWM CCP: CCPA1 Position */ -#define MCPWM_CCP_CCPA1_Msk (0x01UL << MCPWM_CCP_CCPA1_Pos) /*!< MCPWM CCP: CCPA1 Mask */ -#define MCPWM_CCP_CCPB1_Pos 3 /*!< MCPWM CCP: CCPB1 Position */ -#define MCPWM_CCP_CCPB1_Msk (0x01UL << MCPWM_CCP_CCPB1_Pos) /*!< MCPWM CCP: CCPB1 Mask */ -#define MCPWM_CCP_CCPA2_Pos 4 /*!< MCPWM CCP: CCPA2 Position */ -#define MCPWM_CCP_CCPA2_Msk (0x01UL << MCPWM_CCP_CCPA2_Pos) /*!< MCPWM CCP: CCPA2 Mask */ -#define MCPWM_CCP_CCPB2_Pos 5 /*!< MCPWM CCP: CCPB2 Position */ -#define MCPWM_CCP_CCPB2_Msk (0x01UL << MCPWM_CCP_CCPB2_Pos) /*!< MCPWM CCP: CCPB2 Mask */ - -// --------------------------------------- MCPWM_CAP0 ------------------------------------------- -#define MCPWM_CAP0_CAP_Pos 0 /*!< MCPWM CAP0: CAP Position */ -#define MCPWM_CAP0_CAP_Msk (0xffffffffUL << MCPWM_CAP0_CAP_Pos) /*!< MCPWM CAP0: CAP Mask */ - -// --------------------------------------- MCPWM_CAP1 ------------------------------------------- -#define MCPWM_CAP1_CAP_Pos 0 /*!< MCPWM CAP1: CAP Position */ -#define MCPWM_CAP1_CAP_Msk (0xffffffffUL << MCPWM_CAP1_CAP_Pos) /*!< MCPWM CAP1: CAP Mask */ - -// --------------------------------------- MCPWM_CAP2 ------------------------------------------- -#define MCPWM_CAP2_CAP_Pos 0 /*!< MCPWM CAP2: CAP Position */ -#define MCPWM_CAP2_CAP_Msk (0xffffffffUL << MCPWM_CAP2_CAP_Pos) /*!< MCPWM CAP2: CAP Mask */ - -// --------------------------------------- MCPWM_INTEN ------------------------------------------ -#define MCPWM_INTEN_ILIM0_Pos 0 /*!< MCPWM INTEN: ILIM0 Position */ -#define MCPWM_INTEN_ILIM0_Msk (0x01UL << MCPWM_INTEN_ILIM0_Pos) /*!< MCPWM INTEN: ILIM0 Mask */ -#define MCPWM_INTEN_IMAT0_Pos 1 /*!< MCPWM INTEN: IMAT0 Position */ -#define MCPWM_INTEN_IMAT0_Msk (0x01UL << MCPWM_INTEN_IMAT0_Pos) /*!< MCPWM INTEN: IMAT0 Mask */ -#define MCPWM_INTEN_ICAP0_Pos 2 /*!< MCPWM INTEN: ICAP0 Position */ -#define MCPWM_INTEN_ICAP0_Msk (0x01UL << MCPWM_INTEN_ICAP0_Pos) /*!< MCPWM INTEN: ICAP0 Mask */ -#define MCPWM_INTEN_ILIM1_Pos 4 /*!< MCPWM INTEN: ILIM1 Position */ -#define MCPWM_INTEN_ILIM1_Msk (0x01UL << MCPWM_INTEN_ILIM1_Pos) /*!< MCPWM INTEN: ILIM1 Mask */ -#define MCPWM_INTEN_IMAT1_Pos 5 /*!< MCPWM INTEN: IMAT1 Position */ -#define MCPWM_INTEN_IMAT1_Msk (0x01UL << MCPWM_INTEN_IMAT1_Pos) /*!< MCPWM INTEN: IMAT1 Mask */ -#define MCPWM_INTEN_ICAP1_Pos 6 /*!< MCPWM INTEN: ICAP1 Position */ -#define MCPWM_INTEN_ICAP1_Msk (0x01UL << MCPWM_INTEN_ICAP1_Pos) /*!< MCPWM INTEN: ICAP1 Mask */ -#define MCPWM_INTEN_ILIM2_Pos 8 /*!< MCPWM INTEN: ILIM2 Position */ -#define MCPWM_INTEN_ILIM2_Msk (0x01UL << MCPWM_INTEN_ILIM2_Pos) /*!< MCPWM INTEN: ILIM2 Mask */ -#define MCPWM_INTEN_IMAT2_Pos 9 /*!< MCPWM INTEN: IMAT2 Position */ -#define MCPWM_INTEN_IMAT2_Msk (0x01UL << MCPWM_INTEN_IMAT2_Pos) /*!< MCPWM INTEN: IMAT2 Mask */ -#define MCPWM_INTEN_ICAP2_Pos 10 /*!< MCPWM INTEN: ICAP2 Position */ -#define MCPWM_INTEN_ICAP2_Msk (0x01UL << MCPWM_INTEN_ICAP2_Pos) /*!< MCPWM INTEN: ICAP2 Mask */ -#define MCPWM_INTEN_ABORT_Pos 15 /*!< MCPWM INTEN: ABORT Position */ -#define MCPWM_INTEN_ABORT_Msk (0x01UL << MCPWM_INTEN_ABORT_Pos) /*!< MCPWM INTEN: ABORT Mask */ - -// ------------------------------------- MCPWM_INTEN_SET ---------------------------------------- -#define MCPWM_INTEN_SET_ILIM0_SET_Pos 0 /*!< MCPWM INTEN_SET: ILIM0_SET Position */ -#define MCPWM_INTEN_SET_ILIM0_SET_Msk (0x01UL << MCPWM_INTEN_SET_ILIM0_SET_Pos) /*!< MCPWM INTEN_SET: ILIM0_SET Mask */ -#define MCPWM_INTEN_SET_IMAT0_SET_Pos 1 /*!< MCPWM INTEN_SET: IMAT0_SET Position */ -#define MCPWM_INTEN_SET_IMAT0_SET_Msk (0x01UL << MCPWM_INTEN_SET_IMAT0_SET_Pos) /*!< MCPWM INTEN_SET: IMAT0_SET Mask */ -#define MCPWM_INTEN_SET_ICAP0_SET_Pos 2 /*!< MCPWM INTEN_SET: ICAP0_SET Position */ -#define MCPWM_INTEN_SET_ICAP0_SET_Msk (0x01UL << MCPWM_INTEN_SET_ICAP0_SET_Pos) /*!< MCPWM INTEN_SET: ICAP0_SET Mask */ -#define MCPWM_INTEN_SET_ILIM1_SET_Pos 4 /*!< MCPWM INTEN_SET: ILIM1_SET Position */ -#define MCPWM_INTEN_SET_ILIM1_SET_Msk (0x01UL << MCPWM_INTEN_SET_ILIM1_SET_Pos) /*!< MCPWM INTEN_SET: ILIM1_SET Mask */ -#define MCPWM_INTEN_SET_IMAT1_SET_Pos 5 /*!< MCPWM INTEN_SET: IMAT1_SET Position */ -#define MCPWM_INTEN_SET_IMAT1_SET_Msk (0x01UL << MCPWM_INTEN_SET_IMAT1_SET_Pos) /*!< MCPWM INTEN_SET: IMAT1_SET Mask */ -#define MCPWM_INTEN_SET_ICAP1_SET_Pos 6 /*!< MCPWM INTEN_SET: ICAP1_SET Position */ -#define MCPWM_INTEN_SET_ICAP1_SET_Msk (0x01UL << MCPWM_INTEN_SET_ICAP1_SET_Pos) /*!< MCPWM INTEN_SET: ICAP1_SET Mask */ -#define MCPWM_INTEN_SET_ILIM2_SET_Pos 9 /*!< MCPWM INTEN_SET: ILIM2_SET Position */ -#define MCPWM_INTEN_SET_ILIM2_SET_Msk (0x01UL << MCPWM_INTEN_SET_ILIM2_SET_Pos) /*!< MCPWM INTEN_SET: ILIM2_SET Mask */ -#define MCPWM_INTEN_SET_IMAT2_SET_Pos 10 /*!< MCPWM INTEN_SET: IMAT2_SET Position */ -#define MCPWM_INTEN_SET_IMAT2_SET_Msk (0x01UL << MCPWM_INTEN_SET_IMAT2_SET_Pos) /*!< MCPWM INTEN_SET: IMAT2_SET Mask */ -#define MCPWM_INTEN_SET_ICAP2_SET_Pos 11 /*!< MCPWM INTEN_SET: ICAP2_SET Position */ -#define MCPWM_INTEN_SET_ICAP2_SET_Msk (0x01UL << MCPWM_INTEN_SET_ICAP2_SET_Pos) /*!< MCPWM INTEN_SET: ICAP2_SET Mask */ -#define MCPWM_INTEN_SET_ABORT_SET_Pos 15 /*!< MCPWM INTEN_SET: ABORT_SET Position */ -#define MCPWM_INTEN_SET_ABORT_SET_Msk (0x01UL << MCPWM_INTEN_SET_ABORT_SET_Pos) /*!< MCPWM INTEN_SET: ABORT_SET Mask */ - -// ------------------------------------- MCPWM_INTEN_CLR ---------------------------------------- -#define MCPWM_INTEN_CLR_ILIM0_CLR_Pos 0 /*!< MCPWM INTEN_CLR: ILIM0_CLR Position */ -#define MCPWM_INTEN_CLR_ILIM0_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ILIM0_CLR_Pos) /*!< MCPWM INTEN_CLR: ILIM0_CLR Mask */ -#define MCPWM_INTEN_CLR_IMAT0_CLR_Pos 1 /*!< MCPWM INTEN_CLR: IMAT0_CLR Position */ -#define MCPWM_INTEN_CLR_IMAT0_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_IMAT0_CLR_Pos) /*!< MCPWM INTEN_CLR: IMAT0_CLR Mask */ -#define MCPWM_INTEN_CLR_ICAP0_CLR_Pos 2 /*!< MCPWM INTEN_CLR: ICAP0_CLR Position */ -#define MCPWM_INTEN_CLR_ICAP0_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ICAP0_CLR_Pos) /*!< MCPWM INTEN_CLR: ICAP0_CLR Mask */ -#define MCPWM_INTEN_CLR_ILIM1_CLR_Pos 4 /*!< MCPWM INTEN_CLR: ILIM1_CLR Position */ -#define MCPWM_INTEN_CLR_ILIM1_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ILIM1_CLR_Pos) /*!< MCPWM INTEN_CLR: ILIM1_CLR Mask */ -#define MCPWM_INTEN_CLR_IMAT1_CLR_Pos 5 /*!< MCPWM INTEN_CLR: IMAT1_CLR Position */ -#define MCPWM_INTEN_CLR_IMAT1_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_IMAT1_CLR_Pos) /*!< MCPWM INTEN_CLR: IMAT1_CLR Mask */ -#define MCPWM_INTEN_CLR_ICAP1_CLR_Pos 6 /*!< MCPWM INTEN_CLR: ICAP1_CLR Position */ -#define MCPWM_INTEN_CLR_ICAP1_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ICAP1_CLR_Pos) /*!< MCPWM INTEN_CLR: ICAP1_CLR Mask */ -#define MCPWM_INTEN_CLR_ILIM2_CLR_Pos 8 /*!< MCPWM INTEN_CLR: ILIM2_CLR Position */ -#define MCPWM_INTEN_CLR_ILIM2_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ILIM2_CLR_Pos) /*!< MCPWM INTEN_CLR: ILIM2_CLR Mask */ -#define MCPWM_INTEN_CLR_IMAT2_CLR_Pos 9 /*!< MCPWM INTEN_CLR: IMAT2_CLR Position */ -#define MCPWM_INTEN_CLR_IMAT2_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_IMAT2_CLR_Pos) /*!< MCPWM INTEN_CLR: IMAT2_CLR Mask */ -#define MCPWM_INTEN_CLR_ICAP2_CLR_Pos 10 /*!< MCPWM INTEN_CLR: ICAP2_CLR Position */ -#define MCPWM_INTEN_CLR_ICAP2_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ICAP2_CLR_Pos) /*!< MCPWM INTEN_CLR: ICAP2_CLR Mask */ -#define MCPWM_INTEN_CLR_ABORT_CLR_Pos 15 /*!< MCPWM INTEN_CLR: ABORT_CLR Position */ -#define MCPWM_INTEN_CLR_ABORT_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ABORT_CLR_Pos) /*!< MCPWM INTEN_CLR: ABORT_CLR Mask */ - -// -------------------------------------- MCPWM_CNTCON ------------------------------------------ -#define MCPWM_CNTCON_TC0MCI0_RE_Pos 0 /*!< MCPWM CNTCON: TC0MCI0_RE Position */ -#define MCPWM_CNTCON_TC0MCI0_RE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI0_RE_Pos) /*!< MCPWM CNTCON: TC0MCI0_RE Mask */ -#define MCPWM_CNTCON_TC0MCI0_FE_Pos 1 /*!< MCPWM CNTCON: TC0MCI0_FE Position */ -#define MCPWM_CNTCON_TC0MCI0_FE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI0_FE_Pos) /*!< MCPWM CNTCON: TC0MCI0_FE Mask */ -#define MCPWM_CNTCON_TC0MCI1_RE_Pos 2 /*!< MCPWM CNTCON: TC0MCI1_RE Position */ -#define MCPWM_CNTCON_TC0MCI1_RE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI1_RE_Pos) /*!< MCPWM CNTCON: TC0MCI1_RE Mask */ -#define MCPWM_CNTCON_TC0MCI1_FE_Pos 3 /*!< MCPWM CNTCON: TC0MCI1_FE Position */ -#define MCPWM_CNTCON_TC0MCI1_FE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI1_FE_Pos) /*!< MCPWM CNTCON: TC0MCI1_FE Mask */ -#define MCPWM_CNTCON_TC0MCI2_RE_Pos 4 /*!< MCPWM CNTCON: TC0MCI2_RE Position */ -#define MCPWM_CNTCON_TC0MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI2_RE_Pos) /*!< MCPWM CNTCON: TC0MCI2_RE Mask */ -#define MCPWM_CNTCON_TC0MCI2_FE_Pos 5 /*!< MCPWM CNTCON: TC0MCI2_FE Position */ -#define MCPWM_CNTCON_TC0MCI2_FE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI2_FE_Pos) /*!< MCPWM CNTCON: TC0MCI2_FE Mask */ -#define MCPWM_CNTCON_TC1MCI0_RE_Pos 6 /*!< MCPWM CNTCON: TC1MCI0_RE Position */ -#define MCPWM_CNTCON_TC1MCI0_RE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI0_RE_Pos) /*!< MCPWM CNTCON: TC1MCI0_RE Mask */ -#define MCPWM_CNTCON_TC1MCI0_FE_Pos 7 /*!< MCPWM CNTCON: TC1MCI0_FE Position */ -#define MCPWM_CNTCON_TC1MCI0_FE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI0_FE_Pos) /*!< MCPWM CNTCON: TC1MCI0_FE Mask */ -#define MCPWM_CNTCON_TC1MCI1_RE_Pos 8 /*!< MCPWM CNTCON: TC1MCI1_RE Position */ -#define MCPWM_CNTCON_TC1MCI1_RE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI1_RE_Pos) /*!< MCPWM CNTCON: TC1MCI1_RE Mask */ -#define MCPWM_CNTCON_TC1MCI1_FE_Pos 9 /*!< MCPWM CNTCON: TC1MCI1_FE Position */ -#define MCPWM_CNTCON_TC1MCI1_FE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI1_FE_Pos) /*!< MCPWM CNTCON: TC1MCI1_FE Mask */ -#define MCPWM_CNTCON_TC1MCI2_RE_Pos 10 /*!< MCPWM CNTCON: TC1MCI2_RE Position */ -#define MCPWM_CNTCON_TC1MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI2_RE_Pos) /*!< MCPWM CNTCON: TC1MCI2_RE Mask */ -#define MCPWM_CNTCON_TC1MCI2_FE_Pos 11 /*!< MCPWM CNTCON: TC1MCI2_FE Position */ -#define MCPWM_CNTCON_TC1MCI2_FE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI2_FE_Pos) /*!< MCPWM CNTCON: TC1MCI2_FE Mask */ -#define MCPWM_CNTCON_TC2MCI0_RE_Pos 12 /*!< MCPWM CNTCON: TC2MCI0_RE Position */ -#define MCPWM_CNTCON_TC2MCI0_RE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI0_RE_Pos) /*!< MCPWM CNTCON: TC2MCI0_RE Mask */ -#define MCPWM_CNTCON_TC2MCI0_FE_Pos 13 /*!< MCPWM CNTCON: TC2MCI0_FE Position */ -#define MCPWM_CNTCON_TC2MCI0_FE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI0_FE_Pos) /*!< MCPWM CNTCON: TC2MCI0_FE Mask */ -#define MCPWM_CNTCON_TC2MCI1_RE_Pos 14 /*!< MCPWM CNTCON: TC2MCI1_RE Position */ -#define MCPWM_CNTCON_TC2MCI1_RE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI1_RE_Pos) /*!< MCPWM CNTCON: TC2MCI1_RE Mask */ -#define MCPWM_CNTCON_TC2MCI1_FE_Pos 15 /*!< MCPWM CNTCON: TC2MCI1_FE Position */ -#define MCPWM_CNTCON_TC2MCI1_FE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI1_FE_Pos) /*!< MCPWM CNTCON: TC2MCI1_FE Mask */ -#define MCPWM_CNTCON_TC2MCI2_RE_Pos 16 /*!< MCPWM CNTCON: TC2MCI2_RE Position */ -#define MCPWM_CNTCON_TC2MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI2_RE_Pos) /*!< MCPWM CNTCON: TC2MCI2_RE Mask */ -#define MCPWM_CNTCON_TC2MCI2_FE_Pos 17 /*!< MCPWM CNTCON: TC2MCI2_FE Position */ -#define MCPWM_CNTCON_TC2MCI2_FE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI2_FE_Pos) /*!< MCPWM CNTCON: TC2MCI2_FE Mask */ -#define MCPWM_CNTCON_CNTR0_Pos 29 /*!< MCPWM CNTCON: CNTR0 Position */ -#define MCPWM_CNTCON_CNTR0_Msk (0x01UL << MCPWM_CNTCON_CNTR0_Pos) /*!< MCPWM CNTCON: CNTR0 Mask */ -#define MCPWM_CNTCON_CNTR1_Pos 30 /*!< MCPWM CNTCON: CNTR1 Position */ -#define MCPWM_CNTCON_CNTR1_Msk (0x01UL << MCPWM_CNTCON_CNTR1_Pos) /*!< MCPWM CNTCON: CNTR1 Mask */ -#define MCPWM_CNTCON_CNTR2_Pos 31 /*!< MCPWM CNTCON: CNTR2 Position */ -#define MCPWM_CNTCON_CNTR2_Msk (0x01UL << MCPWM_CNTCON_CNTR2_Pos) /*!< MCPWM CNTCON: CNTR2 Mask */ - -// ------------------------------------ MCPWM_CNTCON_SET ---------------------------------------- -#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos 0 /*!< MCPWM CNTCON_SET: TC0MCI0_RE_SET Position */ -#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI0_RE_SET Mask */ -#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos 1 /*!< MCPWM CNTCON_SET: TC0MCI0_FE_SET Position */ -#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI0_FE_SET Mask */ -#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos 2 /*!< MCPWM CNTCON_SET: TC0MCI1_RE_SET Position */ -#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI1_RE_SET Mask */ -#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos 3 /*!< MCPWM CNTCON_SET: TC0MCI1_FE_SET Position */ -#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI1_FE_SET Mask */ -#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos 4 /*!< MCPWM CNTCON_SET: TC0MCI2_RE_SET Position */ -#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI2_RE_SET Mask */ -#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos 5 /*!< MCPWM CNTCON_SET: TC0MCI2_FE_SET Position */ -#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI2_FE_SET Mask */ -#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos 6 /*!< MCPWM CNTCON_SET: TC1MCI0_RE_SET Position */ -#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI0_RE_SET Mask */ -#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos 7 /*!< MCPWM CNTCON_SET: TC1MCI0_FE_SET Position */ -#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI0_FE_SET Mask */ -#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos 8 /*!< MCPWM CNTCON_SET: TC1MCI1_RE_SET Position */ -#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI1_RE_SET Mask */ -#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos 9 /*!< MCPWM CNTCON_SET: TC1MCI1_FE_SET Position */ -#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI1_FE_SET Mask */ -#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos 10 /*!< MCPWM CNTCON_SET: TC1MCI2_RE_SET Position */ -#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI2_RE_SET Mask */ -#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos 11 /*!< MCPWM CNTCON_SET: TC1MCI2_FE_SET Position */ -#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI2_FE_SET Mask */ -#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos 12 /*!< MCPWM CNTCON_SET: TC2MCI0_RE_SET Position */ -#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI0_RE_SET Mask */ -#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos 13 /*!< MCPWM CNTCON_SET: TC2MCI0_FE_SET Position */ -#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI0_FE_SET Mask */ -#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos 14 /*!< MCPWM CNTCON_SET: TC2MCI1_RE_SET Position */ -#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI1_RE_SET Mask */ -#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos 15 /*!< MCPWM CNTCON_SET: TC2MCI1_FE_SET Position */ -#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI1_FE_SET Mask */ -#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos 16 /*!< MCPWM CNTCON_SET: TC2MCI2_RE_SET Position */ -#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI2_RE_SET Mask */ -#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos 17 /*!< MCPWM CNTCON_SET: TC2MCI2_FE_SET Position */ -#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI2_FE_SET Mask */ -#define MCPWM_CNTCON_SET_CNTR0_SET_Pos 29 /*!< MCPWM CNTCON_SET: CNTR0_SET Position */ -#define MCPWM_CNTCON_SET_CNTR0_SET_Msk (0x01UL << MCPWM_CNTCON_SET_CNTR0_SET_Pos) /*!< MCPWM CNTCON_SET: CNTR0_SET Mask */ -#define MCPWM_CNTCON_SET_CNTR1_SET_Pos 30 /*!< MCPWM CNTCON_SET: CNTR1_SET Position */ -#define MCPWM_CNTCON_SET_CNTR1_SET_Msk (0x01UL << MCPWM_CNTCON_SET_CNTR1_SET_Pos) /*!< MCPWM CNTCON_SET: CNTR1_SET Mask */ -#define MCPWM_CNTCON_SET_CNTR2_SET_Pos 31 /*!< MCPWM CNTCON_SET: CNTR2_SET Position */ -#define MCPWM_CNTCON_SET_CNTR2_SET_Msk (0x01UL << MCPWM_CNTCON_SET_CNTR2_SET_Pos) /*!< MCPWM CNTCON_SET: CNTR2_SET Mask */ - -// ------------------------------------ MCPWM_CNTCON_CLR ---------------------------------------- -#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos 0 /*!< MCPWM CNTCON_CLR: TC0MCI0_RE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI0_RE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos 1 /*!< MCPWM CNTCON_CLR: TC0MCI0_FE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI0_FE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos 2 /*!< MCPWM CNTCON_CLR: TC0MCI1_RE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI1_RE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos 3 /*!< MCPWM CNTCON_CLR: TC0MCI1_FE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI1_FE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos 4 /*!< MCPWM CNTCON_CLR: TC0MCI2_RE Position */ -#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI2_RE Mask */ -#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos 5 /*!< MCPWM CNTCON_CLR: TC0MCI2_FE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI2_FE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos 6 /*!< MCPWM CNTCON_CLR: TC1MCI0_RE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI0_RE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos 7 /*!< MCPWM CNTCON_CLR: TC1MCI0_FE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI0_FE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos 8 /*!< MCPWM CNTCON_CLR: TC1MCI1_RE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI1_RE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos 9 /*!< MCPWM CNTCON_CLR: TC1MCI1_FE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI1_FE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos 10 /*!< MCPWM CNTCON_CLR: TC1MCI2_RE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI2_RE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos 11 /*!< MCPWM CNTCON_CLR: TC1MCI2_FE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI2_FE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos 12 /*!< MCPWM CNTCON_CLR: TC2MCI0_RE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI0_RE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos 13 /*!< MCPWM CNTCON_CLR: TC2MCI0_FE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI0_FE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos 14 /*!< MCPWM CNTCON_CLR: TC2MCI1_RE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI1_RE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos 15 /*!< MCPWM CNTCON_CLR: TC2MCI1_FE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI1_FE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos 16 /*!< MCPWM CNTCON_CLR: TC2MCI2_RE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI2_RE_CLR Mask */ -#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos 17 /*!< MCPWM CNTCON_CLR: TC2MCI2_FE_CLR Position */ -#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI2_FE_CLR Mask */ -#define MCPWM_CNTCON_CLR_CNTR0_CLR_Pos 29 /*!< MCPWM CNTCON_CLR: CNTR0_CLR Position */ -#define MCPWM_CNTCON_CLR_CNTR0_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_CNTR0_CLR_Pos) /*!< MCPWM CNTCON_CLR: CNTR0_CLR Mask */ -#define MCPWM_CNTCON_CLR_CNTR1_CLR_Pos 30 /*!< MCPWM CNTCON_CLR: CNTR1_CLR Position */ -#define MCPWM_CNTCON_CLR_CNTR1_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_CNTR1_CLR_Pos) /*!< MCPWM CNTCON_CLR: CNTR1_CLR Mask */ -#define MCPWM_CNTCON_CLR_CNTR2_CLR_Pos 31 /*!< MCPWM CNTCON_CLR: CNTR2_CLR Position */ -#define MCPWM_CNTCON_CLR_CNTR2_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_CNTR2_CLR_Pos) /*!< MCPWM CNTCON_CLR: CNTR2_CLR Mask */ - -// --------------------------------------- MCPWM_INTF ------------------------------------------- -#define MCPWM_INTF_ILIM0_F_Pos 0 /*!< MCPWM INTF: ILIM0_F Position */ -#define MCPWM_INTF_ILIM0_F_Msk (0x01UL << MCPWM_INTF_ILIM0_F_Pos) /*!< MCPWM INTF: ILIM0_F Mask */ -#define MCPWM_INTF_IMAT0_F_Pos 1 /*!< MCPWM INTF: IMAT0_F Position */ -#define MCPWM_INTF_IMAT0_F_Msk (0x01UL << MCPWM_INTF_IMAT0_F_Pos) /*!< MCPWM INTF: IMAT0_F Mask */ -#define MCPWM_INTF_ICAP0_F_Pos 2 /*!< MCPWM INTF: ICAP0_F Position */ -#define MCPWM_INTF_ICAP0_F_Msk (0x01UL << MCPWM_INTF_ICAP0_F_Pos) /*!< MCPWM INTF: ICAP0_F Mask */ -#define MCPWM_INTF_ILIM1_F_Pos 4 /*!< MCPWM INTF: ILIM1_F Position */ -#define MCPWM_INTF_ILIM1_F_Msk (0x01UL << MCPWM_INTF_ILIM1_F_Pos) /*!< MCPWM INTF: ILIM1_F Mask */ -#define MCPWM_INTF_IMAT1_F_Pos 5 /*!< MCPWM INTF: IMAT1_F Position */ -#define MCPWM_INTF_IMAT1_F_Msk (0x01UL << MCPWM_INTF_IMAT1_F_Pos) /*!< MCPWM INTF: IMAT1_F Mask */ -#define MCPWM_INTF_ICAP1_F_Pos 6 /*!< MCPWM INTF: ICAP1_F Position */ -#define MCPWM_INTF_ICAP1_F_Msk (0x01UL << MCPWM_INTF_ICAP1_F_Pos) /*!< MCPWM INTF: ICAP1_F Mask */ -#define MCPWM_INTF_ILIM2_F_Pos 8 /*!< MCPWM INTF: ILIM2_F Position */ -#define MCPWM_INTF_ILIM2_F_Msk (0x01UL << MCPWM_INTF_ILIM2_F_Pos) /*!< MCPWM INTF: ILIM2_F Mask */ -#define MCPWM_INTF_IMAT2_F_Pos 9 /*!< MCPWM INTF: IMAT2_F Position */ -#define MCPWM_INTF_IMAT2_F_Msk (0x01UL << MCPWM_INTF_IMAT2_F_Pos) /*!< MCPWM INTF: IMAT2_F Mask */ -#define MCPWM_INTF_ICAP2_F_Pos 10 /*!< MCPWM INTF: ICAP2_F Position */ -#define MCPWM_INTF_ICAP2_F_Msk (0x01UL << MCPWM_INTF_ICAP2_F_Pos) /*!< MCPWM INTF: ICAP2_F Mask */ -#define MCPWM_INTF_ABORT_F_Pos 15 /*!< MCPWM INTF: ABORT_F Position */ -#define MCPWM_INTF_ABORT_F_Msk (0x01UL << MCPWM_INTF_ABORT_F_Pos) /*!< MCPWM INTF: ABORT_F Mask */ - -// ------------------------------------- MCPWM_INTF_SET ----------------------------------------- -#define MCPWM_INTF_SET_ILIM0_F_SET_Pos 0 /*!< MCPWM INTF_SET: ILIM0_F_SET Position */ -#define MCPWM_INTF_SET_ILIM0_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ILIM0_F_SET_Pos) /*!< MCPWM INTF_SET: ILIM0_F_SET Mask */ -#define MCPWM_INTF_SET_IMAT0_F_SET_Pos 1 /*!< MCPWM INTF_SET: IMAT0_F_SET Position */ -#define MCPWM_INTF_SET_IMAT0_F_SET_Msk (0x01UL << MCPWM_INTF_SET_IMAT0_F_SET_Pos) /*!< MCPWM INTF_SET: IMAT0_F_SET Mask */ -#define MCPWM_INTF_SET_ICAP0_F_SET_Pos 2 /*!< MCPWM INTF_SET: ICAP0_F_SET Position */ -#define MCPWM_INTF_SET_ICAP0_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ICAP0_F_SET_Pos) /*!< MCPWM INTF_SET: ICAP0_F_SET Mask */ -#define MCPWM_INTF_SET_ILIM1_F_SET_Pos 4 /*!< MCPWM INTF_SET: ILIM1_F_SET Position */ -#define MCPWM_INTF_SET_ILIM1_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ILIM1_F_SET_Pos) /*!< MCPWM INTF_SET: ILIM1_F_SET Mask */ -#define MCPWM_INTF_SET_IMAT1_F_SET_Pos 5 /*!< MCPWM INTF_SET: IMAT1_F_SET Position */ -#define MCPWM_INTF_SET_IMAT1_F_SET_Msk (0x01UL << MCPWM_INTF_SET_IMAT1_F_SET_Pos) /*!< MCPWM INTF_SET: IMAT1_F_SET Mask */ -#define MCPWM_INTF_SET_ICAP1_F_SET_Pos 6 /*!< MCPWM INTF_SET: ICAP1_F_SET Position */ -#define MCPWM_INTF_SET_ICAP1_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ICAP1_F_SET_Pos) /*!< MCPWM INTF_SET: ICAP1_F_SET Mask */ -#define MCPWM_INTF_SET_ILIM2_F_SET_Pos 8 /*!< MCPWM INTF_SET: ILIM2_F_SET Position */ -#define MCPWM_INTF_SET_ILIM2_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ILIM2_F_SET_Pos) /*!< MCPWM INTF_SET: ILIM2_F_SET Mask */ -#define MCPWM_INTF_SET_IMAT2_F_SET_Pos 9 /*!< MCPWM INTF_SET: IMAT2_F_SET Position */ -#define MCPWM_INTF_SET_IMAT2_F_SET_Msk (0x01UL << MCPWM_INTF_SET_IMAT2_F_SET_Pos) /*!< MCPWM INTF_SET: IMAT2_F_SET Mask */ -#define MCPWM_INTF_SET_ICAP2_F_SET_Pos 10 /*!< MCPWM INTF_SET: ICAP2_F_SET Position */ -#define MCPWM_INTF_SET_ICAP2_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ICAP2_F_SET_Pos) /*!< MCPWM INTF_SET: ICAP2_F_SET Mask */ -#define MCPWM_INTF_SET_ABORT_F_SET_Pos 15 /*!< MCPWM INTF_SET: ABORT_F_SET Position */ -#define MCPWM_INTF_SET_ABORT_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ABORT_F_SET_Pos) /*!< MCPWM INTF_SET: ABORT_F_SET Mask */ - -// ------------------------------------- MCPWM_INTF_CLR ----------------------------------------- -#define MCPWM_INTF_CLR_ILIM0_F_CLR_Pos 0 /*!< MCPWM INTF_CLR: ILIM0_F_CLR Position */ -#define MCPWM_INTF_CLR_ILIM0_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ILIM0_F_CLR_Pos) /*!< MCPWM INTF_CLR: ILIM0_F_CLR Mask */ -#define MCPWM_INTF_CLR_IMAT0_F_CLR_Pos 1 /*!< MCPWM INTF_CLR: IMAT0_F_CLR Position */ -#define MCPWM_INTF_CLR_IMAT0_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_IMAT0_F_CLR_Pos) /*!< MCPWM INTF_CLR: IMAT0_F_CLR Mask */ -#define MCPWM_INTF_CLR_ICAP0_F_CLR_Pos 2 /*!< MCPWM INTF_CLR: ICAP0_F_CLR Position */ -#define MCPWM_INTF_CLR_ICAP0_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ICAP0_F_CLR_Pos) /*!< MCPWM INTF_CLR: ICAP0_F_CLR Mask */ -#define MCPWM_INTF_CLR_ILIM1_F_CLR_Pos 4 /*!< MCPWM INTF_CLR: ILIM1_F_CLR Position */ -#define MCPWM_INTF_CLR_ILIM1_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ILIM1_F_CLR_Pos) /*!< MCPWM INTF_CLR: ILIM1_F_CLR Mask */ -#define MCPWM_INTF_CLR_IMAT1_F_CLR_Pos 5 /*!< MCPWM INTF_CLR: IMAT1_F_CLR Position */ -#define MCPWM_INTF_CLR_IMAT1_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_IMAT1_F_CLR_Pos) /*!< MCPWM INTF_CLR: IMAT1_F_CLR Mask */ -#define MCPWM_INTF_CLR_ICAP1_F_CLR_Pos 6 /*!< MCPWM INTF_CLR: ICAP1_F_CLR Position */ -#define MCPWM_INTF_CLR_ICAP1_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ICAP1_F_CLR_Pos) /*!< MCPWM INTF_CLR: ICAP1_F_CLR Mask */ -#define MCPWM_INTF_CLR_ILIM2_F_CLR_Pos 8 /*!< MCPWM INTF_CLR: ILIM2_F_CLR Position */ -#define MCPWM_INTF_CLR_ILIM2_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ILIM2_F_CLR_Pos) /*!< MCPWM INTF_CLR: ILIM2_F_CLR Mask */ -#define MCPWM_INTF_CLR_IMAT2_F_CLR_Pos 9 /*!< MCPWM INTF_CLR: IMAT2_F_CLR Position */ -#define MCPWM_INTF_CLR_IMAT2_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_IMAT2_F_CLR_Pos) /*!< MCPWM INTF_CLR: IMAT2_F_CLR Mask */ -#define MCPWM_INTF_CLR_ICAP2_F_CLR_Pos 10 /*!< MCPWM INTF_CLR: ICAP2_F_CLR Position */ -#define MCPWM_INTF_CLR_ICAP2_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ICAP2_F_CLR_Pos) /*!< MCPWM INTF_CLR: ICAP2_F_CLR Mask */ -#define MCPWM_INTF_CLR_ABORT_F_CLR_Pos 15 /*!< MCPWM INTF_CLR: ABORT_F_CLR Position */ -#define MCPWM_INTF_CLR_ABORT_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ABORT_F_CLR_Pos) /*!< MCPWM INTF_CLR: ABORT_F_CLR Mask */ - -// -------------------------------------- MCPWM_CAP_CLR ----------------------------------------- -#define MCPWM_CAP_CLR_CAP_CLR0_Pos 0 /*!< MCPWM CAP_CLR: CAP_CLR0 Position */ -#define MCPWM_CAP_CLR_CAP_CLR0_Msk (0x01UL << MCPWM_CAP_CLR_CAP_CLR0_Pos) /*!< MCPWM CAP_CLR: CAP_CLR0 Mask */ -#define MCPWM_CAP_CLR_CAP_CLR1_Pos 1 /*!< MCPWM CAP_CLR: CAP_CLR1 Position */ -#define MCPWM_CAP_CLR_CAP_CLR1_Msk (0x01UL << MCPWM_CAP_CLR_CAP_CLR1_Pos) /*!< MCPWM CAP_CLR: CAP_CLR1 Mask */ -#define MCPWM_CAP_CLR_CAP_CLR2_Pos 2 /*!< MCPWM CAP_CLR: CAP_CLR2 Position */ -#define MCPWM_CAP_CLR_CAP_CLR2_Msk (0x01UL << MCPWM_CAP_CLR_CAP_CLR2_Pos) /*!< MCPWM CAP_CLR: CAP_CLR2 Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- I2C0 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- I2C0_CONSET ------------------------------------------ -#define I2C0_CONSET_AA_Pos 2 /*!< I2C0 CONSET: AA Position */ -#define I2C0_CONSET_AA_Msk (0x01UL << I2C0_CONSET_AA_Pos) /*!< I2C0 CONSET: AA Mask */ -#define I2C0_CONSET_SI_Pos 3 /*!< I2C0 CONSET: SI Position */ -#define I2C0_CONSET_SI_Msk (0x01UL << I2C0_CONSET_SI_Pos) /*!< I2C0 CONSET: SI Mask */ -#define I2C0_CONSET_STO_Pos 4 /*!< I2C0 CONSET: STO Position */ -#define I2C0_CONSET_STO_Msk (0x01UL << I2C0_CONSET_STO_Pos) /*!< I2C0 CONSET: STO Mask */ -#define I2C0_CONSET_STA_Pos 5 /*!< I2C0 CONSET: STA Position */ -#define I2C0_CONSET_STA_Msk (0x01UL << I2C0_CONSET_STA_Pos) /*!< I2C0 CONSET: STA Mask */ -#define I2C0_CONSET_I2EN_Pos 6 /*!< I2C0 CONSET: I2EN Position */ -#define I2C0_CONSET_I2EN_Msk (0x01UL << I2C0_CONSET_I2EN_Pos) /*!< I2C0 CONSET: I2EN Mask */ - -// ---------------------------------------- I2C0_STAT ------------------------------------------- -#define I2C0_STAT_Status_Pos 3 /*!< I2C0 STAT: Status Position */ -#define I2C0_STAT_Status_Msk (0x1fUL << I2C0_STAT_Status_Pos) /*!< I2C0 STAT: Status Mask */ - -// ---------------------------------------- I2C0_DAT -------------------------------------------- -#define I2C0_DAT_Data_Pos 0 /*!< I2C0 DAT: Data Position */ -#define I2C0_DAT_Data_Msk (0x000000ffUL << I2C0_DAT_Data_Pos) /*!< I2C0 DAT: Data Mask */ - -// ---------------------------------------- I2C0_ADR0 ------------------------------------------- -#define I2C0_ADR0_GC_Pos 0 /*!< I2C0 ADR0: GC Position */ -#define I2C0_ADR0_GC_Msk (0x01UL << I2C0_ADR0_GC_Pos) /*!< I2C0 ADR0: GC Mask */ -#define I2C0_ADR0_Address_Pos 1 /*!< I2C0 ADR0: Address Position */ -#define I2C0_ADR0_Address_Msk (0x7fUL << I2C0_ADR0_Address_Pos) /*!< I2C0 ADR0: Address Mask */ - -// ---------------------------------------- I2C0_SCLH ------------------------------------------- -#define I2C0_SCLH_SCLH_Pos 0 /*!< I2C0 SCLH: SCLH Position */ -#define I2C0_SCLH_SCLH_Msk (0x0000ffffUL << I2C0_SCLH_SCLH_Pos) /*!< I2C0 SCLH: SCLH Mask */ - -// ---------------------------------------- I2C0_SCLL ------------------------------------------- -#define I2C0_SCLL_SCLL_Pos 0 /*!< I2C0 SCLL: SCLL Position */ -#define I2C0_SCLL_SCLL_Msk (0x0000ffffUL << I2C0_SCLL_SCLL_Pos) /*!< I2C0 SCLL: SCLL Mask */ - -// --------------------------------------- I2C0_CONCLR ------------------------------------------ -#define I2C0_CONCLR_AAC_Pos 2 /*!< I2C0 CONCLR: AAC Position */ -#define I2C0_CONCLR_AAC_Msk (0x01UL << I2C0_CONCLR_AAC_Pos) /*!< I2C0 CONCLR: AAC Mask */ -#define I2C0_CONCLR_SIC_Pos 3 /*!< I2C0 CONCLR: SIC Position */ -#define I2C0_CONCLR_SIC_Msk (0x01UL << I2C0_CONCLR_SIC_Pos) /*!< I2C0 CONCLR: SIC Mask */ -#define I2C0_CONCLR_STAC_Pos 5 /*!< I2C0 CONCLR: STAC Position */ -#define I2C0_CONCLR_STAC_Msk (0x01UL << I2C0_CONCLR_STAC_Pos) /*!< I2C0 CONCLR: STAC Mask */ -#define I2C0_CONCLR_I2ENC_Pos 6 /*!< I2C0 CONCLR: I2ENC Position */ -#define I2C0_CONCLR_I2ENC_Msk (0x01UL << I2C0_CONCLR_I2ENC_Pos) /*!< I2C0 CONCLR: I2ENC Mask */ - -// --------------------------------------- I2C0_MMCTRL ------------------------------------------ -#define I2C0_MMCTRL_MM_ENA_Pos 0 /*!< I2C0 MMCTRL: MM_ENA Position */ -#define I2C0_MMCTRL_MM_ENA_Msk (0x01UL << I2C0_MMCTRL_MM_ENA_Pos) /*!< I2C0 MMCTRL: MM_ENA Mask */ -#define I2C0_MMCTRL_ENA_SCL_Pos 1 /*!< I2C0 MMCTRL: ENA_SCL Position */ -#define I2C0_MMCTRL_ENA_SCL_Msk (0x01UL << I2C0_MMCTRL_ENA_SCL_Pos) /*!< I2C0 MMCTRL: ENA_SCL Mask */ -#define I2C0_MMCTRL_MATCH_ALL_Pos 2 /*!< I2C0 MMCTRL: MATCH_ALL Position */ -#define I2C0_MMCTRL_MATCH_ALL_Msk (0x01UL << I2C0_MMCTRL_MATCH_ALL_Pos) /*!< I2C0 MMCTRL: MATCH_ALL Mask */ - -// ---------------------------------------- I2C0_ADR1 ------------------------------------------- -#define I2C0_ADR1_GC_Pos 0 /*!< I2C0 ADR1: GC Position */ -#define I2C0_ADR1_GC_Msk (0x01UL << I2C0_ADR1_GC_Pos) /*!< I2C0 ADR1: GC Mask */ -#define I2C0_ADR1_Address_Pos 1 /*!< I2C0 ADR1: Address Position */ -#define I2C0_ADR1_Address_Msk (0x7fUL << I2C0_ADR1_Address_Pos) /*!< I2C0 ADR1: Address Mask */ - -// ---------------------------------------- I2C0_ADR2 ------------------------------------------- -#define I2C0_ADR2_GC_Pos 0 /*!< I2C0 ADR2: GC Position */ -#define I2C0_ADR2_GC_Msk (0x01UL << I2C0_ADR2_GC_Pos) /*!< I2C0 ADR2: GC Mask */ -#define I2C0_ADR2_Address_Pos 1 /*!< I2C0 ADR2: Address Position */ -#define I2C0_ADR2_Address_Msk (0x7fUL << I2C0_ADR2_Address_Pos) /*!< I2C0 ADR2: Address Mask */ - -// ---------------------------------------- I2C0_ADR3 ------------------------------------------- -#define I2C0_ADR3_GC_Pos 0 /*!< I2C0 ADR3: GC Position */ -#define I2C0_ADR3_GC_Msk (0x01UL << I2C0_ADR3_GC_Pos) /*!< I2C0 ADR3: GC Mask */ -#define I2C0_ADR3_Address_Pos 1 /*!< I2C0 ADR3: Address Position */ -#define I2C0_ADR3_Address_Msk (0x7fUL << I2C0_ADR3_Address_Pos) /*!< I2C0 ADR3: Address Mask */ - -// ------------------------------------ I2C0_DATA_BUFFER ---------------------------------------- -#define I2C0_DATA_BUFFER_Data_Pos 0 /*!< I2C0 DATA_BUFFER: Data Position */ -#define I2C0_DATA_BUFFER_Data_Msk (0x000000ffUL << I2C0_DATA_BUFFER_Data_Pos) /*!< I2C0 DATA_BUFFER: Data Mask */ - -// --------------------------------------- I2C0_MASK0 ------------------------------------------- -#define I2C0_MASK0_MASK_Pos 1 /*!< I2C0 MASK0: MASK Position */ -#define I2C0_MASK0_MASK_Msk (0x7fUL << I2C0_MASK0_MASK_Pos) /*!< I2C0 MASK0: MASK Mask */ - -// --------------------------------------- I2C0_MASK1 ------------------------------------------- -#define I2C0_MASK1_MASK_Pos 1 /*!< I2C0 MASK1: MASK Position */ -#define I2C0_MASK1_MASK_Msk (0x7fUL << I2C0_MASK1_MASK_Pos) /*!< I2C0 MASK1: MASK Mask */ - -// --------------------------------------- I2C0_MASK2 ------------------------------------------- -#define I2C0_MASK2_MASK_Pos 1 /*!< I2C0 MASK2: MASK Position */ -#define I2C0_MASK2_MASK_Msk (0x7fUL << I2C0_MASK2_MASK_Pos) /*!< I2C0 MASK2: MASK Mask */ - -// --------------------------------------- I2C0_MASK3 ------------------------------------------- -#define I2C0_MASK3_MASK_Pos 1 /*!< I2C0 MASK3: MASK Position */ -#define I2C0_MASK3_MASK_Msk (0x7fUL << I2C0_MASK3_MASK_Pos) /*!< I2C0 MASK3: MASK Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- I2C1 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- I2C1_CONSET ------------------------------------------ -#define I2C1_CONSET_AA_Pos 2 /*!< I2C1 CONSET: AA Position */ -#define I2C1_CONSET_AA_Msk (0x01UL << I2C1_CONSET_AA_Pos) /*!< I2C1 CONSET: AA Mask */ -#define I2C1_CONSET_SI_Pos 3 /*!< I2C1 CONSET: SI Position */ -#define I2C1_CONSET_SI_Msk (0x01UL << I2C1_CONSET_SI_Pos) /*!< I2C1 CONSET: SI Mask */ -#define I2C1_CONSET_STO_Pos 4 /*!< I2C1 CONSET: STO Position */ -#define I2C1_CONSET_STO_Msk (0x01UL << I2C1_CONSET_STO_Pos) /*!< I2C1 CONSET: STO Mask */ -#define I2C1_CONSET_STA_Pos 5 /*!< I2C1 CONSET: STA Position */ -#define I2C1_CONSET_STA_Msk (0x01UL << I2C1_CONSET_STA_Pos) /*!< I2C1 CONSET: STA Mask */ -#define I2C1_CONSET_I2EN_Pos 6 /*!< I2C1 CONSET: I2EN Position */ -#define I2C1_CONSET_I2EN_Msk (0x01UL << I2C1_CONSET_I2EN_Pos) /*!< I2C1 CONSET: I2EN Mask */ - -// ---------------------------------------- I2C1_STAT ------------------------------------------- -#define I2C1_STAT_Status_Pos 3 /*!< I2C1 STAT: Status Position */ -#define I2C1_STAT_Status_Msk (0x1fUL << I2C1_STAT_Status_Pos) /*!< I2C1 STAT: Status Mask */ - -// ---------------------------------------- I2C1_DAT -------------------------------------------- -#define I2C1_DAT_Data_Pos 0 /*!< I2C1 DAT: Data Position */ -#define I2C1_DAT_Data_Msk (0x000000ffUL << I2C1_DAT_Data_Pos) /*!< I2C1 DAT: Data Mask */ - -// ---------------------------------------- I2C1_ADR0 ------------------------------------------- -#define I2C1_ADR0_GC_Pos 0 /*!< I2C1 ADR0: GC Position */ -#define I2C1_ADR0_GC_Msk (0x01UL << I2C1_ADR0_GC_Pos) /*!< I2C1 ADR0: GC Mask */ -#define I2C1_ADR0_Address_Pos 1 /*!< I2C1 ADR0: Address Position */ -#define I2C1_ADR0_Address_Msk (0x7fUL << I2C1_ADR0_Address_Pos) /*!< I2C1 ADR0: Address Mask */ - -// ---------------------------------------- I2C1_SCLH ------------------------------------------- -#define I2C1_SCLH_SCLH_Pos 0 /*!< I2C1 SCLH: SCLH Position */ -#define I2C1_SCLH_SCLH_Msk (0x0000ffffUL << I2C1_SCLH_SCLH_Pos) /*!< I2C1 SCLH: SCLH Mask */ - -// ---------------------------------------- I2C1_SCLL ------------------------------------------- -#define I2C1_SCLL_SCLL_Pos 0 /*!< I2C1 SCLL: SCLL Position */ -#define I2C1_SCLL_SCLL_Msk (0x0000ffffUL << I2C1_SCLL_SCLL_Pos) /*!< I2C1 SCLL: SCLL Mask */ - -// --------------------------------------- I2C1_CONCLR ------------------------------------------ -#define I2C1_CONCLR_AAC_Pos 2 /*!< I2C1 CONCLR: AAC Position */ -#define I2C1_CONCLR_AAC_Msk (0x01UL << I2C1_CONCLR_AAC_Pos) /*!< I2C1 CONCLR: AAC Mask */ -#define I2C1_CONCLR_SIC_Pos 3 /*!< I2C1 CONCLR: SIC Position */ -#define I2C1_CONCLR_SIC_Msk (0x01UL << I2C1_CONCLR_SIC_Pos) /*!< I2C1 CONCLR: SIC Mask */ -#define I2C1_CONCLR_STAC_Pos 5 /*!< I2C1 CONCLR: STAC Position */ -#define I2C1_CONCLR_STAC_Msk (0x01UL << I2C1_CONCLR_STAC_Pos) /*!< I2C1 CONCLR: STAC Mask */ -#define I2C1_CONCLR_I2ENC_Pos 6 /*!< I2C1 CONCLR: I2ENC Position */ -#define I2C1_CONCLR_I2ENC_Msk (0x01UL << I2C1_CONCLR_I2ENC_Pos) /*!< I2C1 CONCLR: I2ENC Mask */ - -// --------------------------------------- I2C1_MMCTRL ------------------------------------------ -#define I2C1_MMCTRL_MM_ENA_Pos 0 /*!< I2C1 MMCTRL: MM_ENA Position */ -#define I2C1_MMCTRL_MM_ENA_Msk (0x01UL << I2C1_MMCTRL_MM_ENA_Pos) /*!< I2C1 MMCTRL: MM_ENA Mask */ -#define I2C1_MMCTRL_ENA_SCL_Pos 1 /*!< I2C1 MMCTRL: ENA_SCL Position */ -#define I2C1_MMCTRL_ENA_SCL_Msk (0x01UL << I2C1_MMCTRL_ENA_SCL_Pos) /*!< I2C1 MMCTRL: ENA_SCL Mask */ -#define I2C1_MMCTRL_MATCH_ALL_Pos 2 /*!< I2C1 MMCTRL: MATCH_ALL Position */ -#define I2C1_MMCTRL_MATCH_ALL_Msk (0x01UL << I2C1_MMCTRL_MATCH_ALL_Pos) /*!< I2C1 MMCTRL: MATCH_ALL Mask */ - -// ---------------------------------------- I2C1_ADR1 ------------------------------------------- -#define I2C1_ADR1_GC_Pos 0 /*!< I2C1 ADR1: GC Position */ -#define I2C1_ADR1_GC_Msk (0x01UL << I2C1_ADR1_GC_Pos) /*!< I2C1 ADR1: GC Mask */ -#define I2C1_ADR1_Address_Pos 1 /*!< I2C1 ADR1: Address Position */ -#define I2C1_ADR1_Address_Msk (0x7fUL << I2C1_ADR1_Address_Pos) /*!< I2C1 ADR1: Address Mask */ - -// ---------------------------------------- I2C1_ADR2 ------------------------------------------- -#define I2C1_ADR2_GC_Pos 0 /*!< I2C1 ADR2: GC Position */ -#define I2C1_ADR2_GC_Msk (0x01UL << I2C1_ADR2_GC_Pos) /*!< I2C1 ADR2: GC Mask */ -#define I2C1_ADR2_Address_Pos 1 /*!< I2C1 ADR2: Address Position */ -#define I2C1_ADR2_Address_Msk (0x7fUL << I2C1_ADR2_Address_Pos) /*!< I2C1 ADR2: Address Mask */ - -// ---------------------------------------- I2C1_ADR3 ------------------------------------------- -#define I2C1_ADR3_GC_Pos 0 /*!< I2C1 ADR3: GC Position */ -#define I2C1_ADR3_GC_Msk (0x01UL << I2C1_ADR3_GC_Pos) /*!< I2C1 ADR3: GC Mask */ -#define I2C1_ADR3_Address_Pos 1 /*!< I2C1 ADR3: Address Position */ -#define I2C1_ADR3_Address_Msk (0x7fUL << I2C1_ADR3_Address_Pos) /*!< I2C1 ADR3: Address Mask */ - -// ------------------------------------ I2C1_DATA_BUFFER ---------------------------------------- -#define I2C1_DATA_BUFFER_Data_Pos 0 /*!< I2C1 DATA_BUFFER: Data Position */ -#define I2C1_DATA_BUFFER_Data_Msk (0x000000ffUL << I2C1_DATA_BUFFER_Data_Pos) /*!< I2C1 DATA_BUFFER: Data Mask */ - -// --------------------------------------- I2C1_MASK0 ------------------------------------------- -#define I2C1_MASK0_MASK_Pos 1 /*!< I2C1 MASK0: MASK Position */ -#define I2C1_MASK0_MASK_Msk (0x7fUL << I2C1_MASK0_MASK_Pos) /*!< I2C1 MASK0: MASK Mask */ - -// --------------------------------------- I2C1_MASK1 ------------------------------------------- -#define I2C1_MASK1_MASK_Pos 1 /*!< I2C1 MASK1: MASK Position */ -#define I2C1_MASK1_MASK_Msk (0x7fUL << I2C1_MASK1_MASK_Pos) /*!< I2C1 MASK1: MASK Mask */ - -// --------------------------------------- I2C1_MASK2 ------------------------------------------- -#define I2C1_MASK2_MASK_Pos 1 /*!< I2C1 MASK2: MASK Position */ -#define I2C1_MASK2_MASK_Msk (0x7fUL << I2C1_MASK2_MASK_Pos) /*!< I2C1 MASK2: MASK Mask */ - -// --------------------------------------- I2C1_MASK3 ------------------------------------------- -#define I2C1_MASK3_MASK_Pos 1 /*!< I2C1 MASK3: MASK Position */ -#define I2C1_MASK3_MASK_Msk (0x7fUL << I2C1_MASK3_MASK_Pos) /*!< I2C1 MASK3: MASK Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- I2S0 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- I2S0_DAO -------------------------------------------- -#define I2S0_DAO_WORDWIDTH_Pos 0 /*!< I2S0 DAO: WORDWIDTH Position */ -#define I2S0_DAO_WORDWIDTH_Msk (0x03UL << I2S0_DAO_WORDWIDTH_Pos) /*!< I2S0 DAO: WORDWIDTH Mask */ -#define I2S0_DAO_MONO_Pos 2 /*!< I2S0 DAO: MONO Position */ -#define I2S0_DAO_MONO_Msk (0x01UL << I2S0_DAO_MONO_Pos) /*!< I2S0 DAO: MONO Mask */ -#define I2S0_DAO_STOP_Pos 3 /*!< I2S0 DAO: STOP Position */ -#define I2S0_DAO_STOP_Msk (0x01UL << I2S0_DAO_STOP_Pos) /*!< I2S0 DAO: STOP Mask */ -#define I2S0_DAO_RESET_Pos 4 /*!< I2S0 DAO: RESET Position */ -#define I2S0_DAO_RESET_Msk (0x01UL << I2S0_DAO_RESET_Pos) /*!< I2S0 DAO: RESET Mask */ -#define I2S0_DAO_WS_SEL_Pos 5 /*!< I2S0 DAO: WS_SEL Position */ -#define I2S0_DAO_WS_SEL_Msk (0x01UL << I2S0_DAO_WS_SEL_Pos) /*!< I2S0 DAO: WS_SEL Mask */ -#define I2S0_DAO_WS_HALFPERIOD_Pos 6 /*!< I2S0 DAO: WS_HALFPERIOD Position */ -#define I2S0_DAO_WS_HALFPERIOD_Msk (0x000001ffUL << I2S0_DAO_WS_HALFPERIOD_Pos) /*!< I2S0 DAO: WS_HALFPERIOD Mask */ -#define I2S0_DAO_MUTE_Pos 15 /*!< I2S0 DAO: MUTE Position */ -#define I2S0_DAO_MUTE_Msk (0x01UL << I2S0_DAO_MUTE_Pos) /*!< I2S0 DAO: MUTE Mask */ - -// ---------------------------------------- I2S0_DAI -------------------------------------------- -#define I2S0_DAI_WORDWIDTH_Pos 0 /*!< I2S0 DAI: WORDWIDTH Position */ -#define I2S0_DAI_WORDWIDTH_Msk (0x03UL << I2S0_DAI_WORDWIDTH_Pos) /*!< I2S0 DAI: WORDWIDTH Mask */ -#define I2S0_DAI_MONO_Pos 2 /*!< I2S0 DAI: MONO Position */ -#define I2S0_DAI_MONO_Msk (0x01UL << I2S0_DAI_MONO_Pos) /*!< I2S0 DAI: MONO Mask */ -#define I2S0_DAI_STOP_Pos 3 /*!< I2S0 DAI: STOP Position */ -#define I2S0_DAI_STOP_Msk (0x01UL << I2S0_DAI_STOP_Pos) /*!< I2S0 DAI: STOP Mask */ -#define I2S0_DAI_RESET_Pos 4 /*!< I2S0 DAI: RESET Position */ -#define I2S0_DAI_RESET_Msk (0x01UL << I2S0_DAI_RESET_Pos) /*!< I2S0 DAI: RESET Mask */ -#define I2S0_DAI_WS_SEL_Pos 5 /*!< I2S0 DAI: WS_SEL Position */ -#define I2S0_DAI_WS_SEL_Msk (0x01UL << I2S0_DAI_WS_SEL_Pos) /*!< I2S0 DAI: WS_SEL Mask */ -#define I2S0_DAI_WS_HALFPERIOD_Pos 6 /*!< I2S0 DAI: WS_HALFPERIOD Position */ -#define I2S0_DAI_WS_HALFPERIOD_Msk (0x000001ffUL << I2S0_DAI_WS_HALFPERIOD_Pos) /*!< I2S0 DAI: WS_HALFPERIOD Mask */ - -// --------------------------------------- I2S0_TXFIFO ------------------------------------------ -#define I2S0_TXFIFO_I2STXFIFO_Pos 0 /*!< I2S0 TXFIFO: I2STXFIFO Position */ -#define I2S0_TXFIFO_I2STXFIFO_Msk (0xffffffffUL << I2S0_TXFIFO_I2STXFIFO_Pos) /*!< I2S0 TXFIFO: I2STXFIFO Mask */ - -// --------------------------------------- I2S0_RXFIFO ------------------------------------------ -#define I2S0_RXFIFO_I2SRXFIFO_Pos 0 /*!< I2S0 RXFIFO: I2SRXFIFO Position */ -#define I2S0_RXFIFO_I2SRXFIFO_Msk (0xffffffffUL << I2S0_RXFIFO_I2SRXFIFO_Pos) /*!< I2S0 RXFIFO: I2SRXFIFO Mask */ - -// --------------------------------------- I2S0_STATE ------------------------------------------- -#define I2S0_STATE_IRQ_Pos 0 /*!< I2S0 STATE: IRQ Position */ -#define I2S0_STATE_IRQ_Msk (0x01UL << I2S0_STATE_IRQ_Pos) /*!< I2S0 STATE: IRQ Mask */ -#define I2S0_STATE_DMAREQ1_Pos 1 /*!< I2S0 STATE: DMAREQ1 Position */ -#define I2S0_STATE_DMAREQ1_Msk (0x01UL << I2S0_STATE_DMAREQ1_Pos) /*!< I2S0 STATE: DMAREQ1 Mask */ -#define I2S0_STATE_DMAREQ2_Pos 2 /*!< I2S0 STATE: DMAREQ2 Position */ -#define I2S0_STATE_DMAREQ2_Msk (0x01UL << I2S0_STATE_DMAREQ2_Pos) /*!< I2S0 STATE: DMAREQ2 Mask */ -#define I2S0_STATE_RX_LEVEL_Pos 8 /*!< I2S0 STATE: RX_LEVEL Position */ -#define I2S0_STATE_RX_LEVEL_Msk (0x0fUL << I2S0_STATE_RX_LEVEL_Pos) /*!< I2S0 STATE: RX_LEVEL Mask */ -#define I2S0_STATE_TX_LEVEL_Pos 16 /*!< I2S0 STATE: TX_LEVEL Position */ -#define I2S0_STATE_TX_LEVEL_Msk (0x0fUL << I2S0_STATE_TX_LEVEL_Pos) /*!< I2S0 STATE: TX_LEVEL Mask */ - -// ---------------------------------------- I2S0_DMA1 ------------------------------------------- -#define I2S0_DMA1_RX_DMA1_ENABLE_Pos 0 /*!< I2S0 DMA1: RX_DMA1_ENABLE Position */ -#define I2S0_DMA1_RX_DMA1_ENABLE_Msk (0x01UL << I2S0_DMA1_RX_DMA1_ENABLE_Pos) /*!< I2S0 DMA1: RX_DMA1_ENABLE Mask */ -#define I2S0_DMA1_TX_DMA1_ENABLE_Pos 1 /*!< I2S0 DMA1: TX_DMA1_ENABLE Position */ -#define I2S0_DMA1_TX_DMA1_ENABLE_Msk (0x01UL << I2S0_DMA1_TX_DMA1_ENABLE_Pos) /*!< I2S0 DMA1: TX_DMA1_ENABLE Mask */ -#define I2S0_DMA1_RX_DEPTH_DMA1_Pos 8 /*!< I2S0 DMA1: RX_DEPTH_DMA1 Position */ -#define I2S0_DMA1_RX_DEPTH_DMA1_Msk (0x0fUL << I2S0_DMA1_RX_DEPTH_DMA1_Pos) /*!< I2S0 DMA1: RX_DEPTH_DMA1 Mask */ -#define I2S0_DMA1_TX_DEPTH_DMA1_Pos 16 /*!< I2S0 DMA1: TX_DEPTH_DMA1 Position */ -#define I2S0_DMA1_TX_DEPTH_DMA1_Msk (0x0fUL << I2S0_DMA1_TX_DEPTH_DMA1_Pos) /*!< I2S0 DMA1: TX_DEPTH_DMA1 Mask */ - -// ---------------------------------------- I2S0_DMA2 ------------------------------------------- -#define I2S0_DMA2_RX_DMA2_ENABLE_Pos 0 /*!< I2S0 DMA2: RX_DMA2_ENABLE Position */ -#define I2S0_DMA2_RX_DMA2_ENABLE_Msk (0x01UL << I2S0_DMA2_RX_DMA2_ENABLE_Pos) /*!< I2S0 DMA2: RX_DMA2_ENABLE Mask */ -#define I2S0_DMA2_TX_DMA2_ENABLE_Pos 1 /*!< I2S0 DMA2: TX_DMA2_ENABLE Position */ -#define I2S0_DMA2_TX_DMA2_ENABLE_Msk (0x01UL << I2S0_DMA2_TX_DMA2_ENABLE_Pos) /*!< I2S0 DMA2: TX_DMA2_ENABLE Mask */ -#define I2S0_DMA2_RX_DEPTH_DMA2_Pos 8 /*!< I2S0 DMA2: RX_DEPTH_DMA2 Position */ -#define I2S0_DMA2_RX_DEPTH_DMA2_Msk (0x0fUL << I2S0_DMA2_RX_DEPTH_DMA2_Pos) /*!< I2S0 DMA2: RX_DEPTH_DMA2 Mask */ -#define I2S0_DMA2_TX_DEPTH_DMA2_Pos 16 /*!< I2S0 DMA2: TX_DEPTH_DMA2 Position */ -#define I2S0_DMA2_TX_DEPTH_DMA2_Msk (0x0fUL << I2S0_DMA2_TX_DEPTH_DMA2_Pos) /*!< I2S0 DMA2: TX_DEPTH_DMA2 Mask */ - -// ---------------------------------------- I2S0_IRQ -------------------------------------------- -#define I2S0_IRQ_RX_IRQ_ENABLE_Pos 0 /*!< I2S0 IRQ: RX_IRQ_ENABLE Position */ -#define I2S0_IRQ_RX_IRQ_ENABLE_Msk (0x01UL << I2S0_IRQ_RX_IRQ_ENABLE_Pos) /*!< I2S0 IRQ: RX_IRQ_ENABLE Mask */ -#define I2S0_IRQ_TX_IRQ_ENABLE_Pos 1 /*!< I2S0 IRQ: TX_IRQ_ENABLE Position */ -#define I2S0_IRQ_TX_IRQ_ENABLE_Msk (0x01UL << I2S0_IRQ_TX_IRQ_ENABLE_Pos) /*!< I2S0 IRQ: TX_IRQ_ENABLE Mask */ -#define I2S0_IRQ_RX_DEPTH_IRQ_Pos 8 /*!< I2S0 IRQ: RX_DEPTH_IRQ Position */ -#define I2S0_IRQ_RX_DEPTH_IRQ_Msk (0x0fUL << I2S0_IRQ_RX_DEPTH_IRQ_Pos) /*!< I2S0 IRQ: RX_DEPTH_IRQ Mask */ -#define I2S0_IRQ_TX_DEPTH_IRQ_Pos 16 /*!< I2S0 IRQ: TX_DEPTH_IRQ Position */ -#define I2S0_IRQ_TX_DEPTH_IRQ_Msk (0x0fUL << I2S0_IRQ_TX_DEPTH_IRQ_Pos) /*!< I2S0 IRQ: TX_DEPTH_IRQ Mask */ - -// --------------------------------------- I2S0_TXRATE ------------------------------------------ -#define I2S0_TXRATE_Y_DIVIDER_Pos 0 /*!< I2S0 TXRATE: Y_DIVIDER Position */ -#define I2S0_TXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S0_TXRATE_Y_DIVIDER_Pos) /*!< I2S0 TXRATE: Y_DIVIDER Mask */ -#define I2S0_TXRATE_X_DIVIDER_Pos 8 /*!< I2S0 TXRATE: X_DIVIDER Position */ -#define I2S0_TXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S0_TXRATE_X_DIVIDER_Pos) /*!< I2S0 TXRATE: X_DIVIDER Mask */ - -// --------------------------------------- I2S0_RXRATE ------------------------------------------ -#define I2S0_RXRATE_Y_DIVIDER_Pos 0 /*!< I2S0 RXRATE: Y_DIVIDER Position */ -#define I2S0_RXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S0_RXRATE_Y_DIVIDER_Pos) /*!< I2S0 RXRATE: Y_DIVIDER Mask */ -#define I2S0_RXRATE_X_DIVIDER_Pos 8 /*!< I2S0 RXRATE: X_DIVIDER Position */ -#define I2S0_RXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S0_RXRATE_X_DIVIDER_Pos) /*!< I2S0 RXRATE: X_DIVIDER Mask */ - -// ------------------------------------- I2S0_TXBITRATE ----------------------------------------- -#define I2S0_TXBITRATE_TX_BITRATE_Pos 0 /*!< I2S0 TXBITRATE: TX_BITRATE Position */ -#define I2S0_TXBITRATE_TX_BITRATE_Msk (0x3fUL << I2S0_TXBITRATE_TX_BITRATE_Pos) /*!< I2S0 TXBITRATE: TX_BITRATE Mask */ - -// ------------------------------------- I2S0_RXBITRATE ----------------------------------------- -#define I2S0_RXBITRATE_RX_BITRATE_Pos 0 /*!< I2S0 RXBITRATE: RX_BITRATE Position */ -#define I2S0_RXBITRATE_RX_BITRATE_Msk (0x3fUL << I2S0_RXBITRATE_RX_BITRATE_Pos) /*!< I2S0 RXBITRATE: RX_BITRATE Mask */ - -// --------------------------------------- I2S0_TXMODE ------------------------------------------ -#define I2S0_TXMODE_TXCLKSEL_Pos 0 /*!< I2S0 TXMODE: TXCLKSEL Position */ -#define I2S0_TXMODE_TXCLKSEL_Msk (0x03UL << I2S0_TXMODE_TXCLKSEL_Pos) /*!< I2S0 TXMODE: TXCLKSEL Mask */ -#define I2S0_TXMODE_TX4PIN_Pos 2 /*!< I2S0 TXMODE: TX4PIN Position */ -#define I2S0_TXMODE_TX4PIN_Msk (0x01UL << I2S0_TXMODE_TX4PIN_Pos) /*!< I2S0 TXMODE: TX4PIN Mask */ -#define I2S0_TXMODE_TXMCENA_Pos 3 /*!< I2S0 TXMODE: TXMCENA Position */ -#define I2S0_TXMODE_TXMCENA_Msk (0x01UL << I2S0_TXMODE_TXMCENA_Pos) /*!< I2S0 TXMODE: TXMCENA Mask */ - -// --------------------------------------- I2S0_RXMODE ------------------------------------------ -#define I2S0_RXMODE_RXCLKSEL_Pos 0 /*!< I2S0 RXMODE: RXCLKSEL Position */ -#define I2S0_RXMODE_RXCLKSEL_Msk (0x03UL << I2S0_RXMODE_RXCLKSEL_Pos) /*!< I2S0 RXMODE: RXCLKSEL Mask */ -#define I2S0_RXMODE_RX4PIN_Pos 2 /*!< I2S0 RXMODE: RX4PIN Position */ -#define I2S0_RXMODE_RX4PIN_Msk (0x01UL << I2S0_RXMODE_RX4PIN_Pos) /*!< I2S0 RXMODE: RX4PIN Mask */ -#define I2S0_RXMODE_RXMCENA_Pos 3 /*!< I2S0 RXMODE: RXMCENA Position */ -#define I2S0_RXMODE_RXMCENA_Msk (0x01UL << I2S0_RXMODE_RXMCENA_Pos) /*!< I2S0 RXMODE: RXMCENA Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- I2S1 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ---------------------------------------- I2S1_DAO -------------------------------------------- -#define I2S1_DAO_WORDWIDTH_Pos 0 /*!< I2S1 DAO: WORDWIDTH Position */ -#define I2S1_DAO_WORDWIDTH_Msk (0x03UL << I2S1_DAO_WORDWIDTH_Pos) /*!< I2S1 DAO: WORDWIDTH Mask */ -#define I2S1_DAO_MONO_Pos 2 /*!< I2S1 DAO: MONO Position */ -#define I2S1_DAO_MONO_Msk (0x01UL << I2S1_DAO_MONO_Pos) /*!< I2S1 DAO: MONO Mask */ -#define I2S1_DAO_STOP_Pos 3 /*!< I2S1 DAO: STOP Position */ -#define I2S1_DAO_STOP_Msk (0x01UL << I2S1_DAO_STOP_Pos) /*!< I2S1 DAO: STOP Mask */ -#define I2S1_DAO_RESET_Pos 4 /*!< I2S1 DAO: RESET Position */ -#define I2S1_DAO_RESET_Msk (0x01UL << I2S1_DAO_RESET_Pos) /*!< I2S1 DAO: RESET Mask */ -#define I2S1_DAO_WS_SEL_Pos 5 /*!< I2S1 DAO: WS_SEL Position */ -#define I2S1_DAO_WS_SEL_Msk (0x01UL << I2S1_DAO_WS_SEL_Pos) /*!< I2S1 DAO: WS_SEL Mask */ -#define I2S1_DAO_WS_HALFPERIOD_Pos 6 /*!< I2S1 DAO: WS_HALFPERIOD Position */ -#define I2S1_DAO_WS_HALFPERIOD_Msk (0x000001ffUL << I2S1_DAO_WS_HALFPERIOD_Pos) /*!< I2S1 DAO: WS_HALFPERIOD Mask */ -#define I2S1_DAO_MUTE_Pos 15 /*!< I2S1 DAO: MUTE Position */ -#define I2S1_DAO_MUTE_Msk (0x01UL << I2S1_DAO_MUTE_Pos) /*!< I2S1 DAO: MUTE Mask */ - -// ---------------------------------------- I2S1_DAI -------------------------------------------- -#define I2S1_DAI_WORDWIDTH_Pos 0 /*!< I2S1 DAI: WORDWIDTH Position */ -#define I2S1_DAI_WORDWIDTH_Msk (0x03UL << I2S1_DAI_WORDWIDTH_Pos) /*!< I2S1 DAI: WORDWIDTH Mask */ -#define I2S1_DAI_MONO_Pos 2 /*!< I2S1 DAI: MONO Position */ -#define I2S1_DAI_MONO_Msk (0x01UL << I2S1_DAI_MONO_Pos) /*!< I2S1 DAI: MONO Mask */ -#define I2S1_DAI_STOP_Pos 3 /*!< I2S1 DAI: STOP Position */ -#define I2S1_DAI_STOP_Msk (0x01UL << I2S1_DAI_STOP_Pos) /*!< I2S1 DAI: STOP Mask */ -#define I2S1_DAI_RESET_Pos 4 /*!< I2S1 DAI: RESET Position */ -#define I2S1_DAI_RESET_Msk (0x01UL << I2S1_DAI_RESET_Pos) /*!< I2S1 DAI: RESET Mask */ -#define I2S1_DAI_WS_SEL_Pos 5 /*!< I2S1 DAI: WS_SEL Position */ -#define I2S1_DAI_WS_SEL_Msk (0x01UL << I2S1_DAI_WS_SEL_Pos) /*!< I2S1 DAI: WS_SEL Mask */ -#define I2S1_DAI_WS_HALFPERIOD_Pos 6 /*!< I2S1 DAI: WS_HALFPERIOD Position */ -#define I2S1_DAI_WS_HALFPERIOD_Msk (0x000001ffUL << I2S1_DAI_WS_HALFPERIOD_Pos) /*!< I2S1 DAI: WS_HALFPERIOD Mask */ - -// --------------------------------------- I2S1_TXFIFO ------------------------------------------ -#define I2S1_TXFIFO_I2STXFIFO_Pos 0 /*!< I2S1 TXFIFO: I2STXFIFO Position */ -#define I2S1_TXFIFO_I2STXFIFO_Msk (0xffffffffUL << I2S1_TXFIFO_I2STXFIFO_Pos) /*!< I2S1 TXFIFO: I2STXFIFO Mask */ - -// --------------------------------------- I2S1_RXFIFO ------------------------------------------ -#define I2S1_RXFIFO_I2SRXFIFO_Pos 0 /*!< I2S1 RXFIFO: I2SRXFIFO Position */ -#define I2S1_RXFIFO_I2SRXFIFO_Msk (0xffffffffUL << I2S1_RXFIFO_I2SRXFIFO_Pos) /*!< I2S1 RXFIFO: I2SRXFIFO Mask */ - -// --------------------------------------- I2S1_STATE ------------------------------------------- -#define I2S1_STATE_IRQ_Pos 0 /*!< I2S1 STATE: IRQ Position */ -#define I2S1_STATE_IRQ_Msk (0x01UL << I2S1_STATE_IRQ_Pos) /*!< I2S1 STATE: IRQ Mask */ -#define I2S1_STATE_DMAREQ1_Pos 1 /*!< I2S1 STATE: DMAREQ1 Position */ -#define I2S1_STATE_DMAREQ1_Msk (0x01UL << I2S1_STATE_DMAREQ1_Pos) /*!< I2S1 STATE: DMAREQ1 Mask */ -#define I2S1_STATE_DMAREQ2_Pos 2 /*!< I2S1 STATE: DMAREQ2 Position */ -#define I2S1_STATE_DMAREQ2_Msk (0x01UL << I2S1_STATE_DMAREQ2_Pos) /*!< I2S1 STATE: DMAREQ2 Mask */ -#define I2S1_STATE_RX_LEVEL_Pos 8 /*!< I2S1 STATE: RX_LEVEL Position */ -#define I2S1_STATE_RX_LEVEL_Msk (0x0fUL << I2S1_STATE_RX_LEVEL_Pos) /*!< I2S1 STATE: RX_LEVEL Mask */ -#define I2S1_STATE_TX_LEVEL_Pos 16 /*!< I2S1 STATE: TX_LEVEL Position */ -#define I2S1_STATE_TX_LEVEL_Msk (0x0fUL << I2S1_STATE_TX_LEVEL_Pos) /*!< I2S1 STATE: TX_LEVEL Mask */ - -// ---------------------------------------- I2S1_DMA1 ------------------------------------------- -#define I2S1_DMA1_RX_DMA1_ENABLE_Pos 0 /*!< I2S1 DMA1: RX_DMA1_ENABLE Position */ -#define I2S1_DMA1_RX_DMA1_ENABLE_Msk (0x01UL << I2S1_DMA1_RX_DMA1_ENABLE_Pos) /*!< I2S1 DMA1: RX_DMA1_ENABLE Mask */ -#define I2S1_DMA1_TX_DMA1_ENABLE_Pos 1 /*!< I2S1 DMA1: TX_DMA1_ENABLE Position */ -#define I2S1_DMA1_TX_DMA1_ENABLE_Msk (0x01UL << I2S1_DMA1_TX_DMA1_ENABLE_Pos) /*!< I2S1 DMA1: TX_DMA1_ENABLE Mask */ -#define I2S1_DMA1_RX_DEPTH_DMA1_Pos 8 /*!< I2S1 DMA1: RX_DEPTH_DMA1 Position */ -#define I2S1_DMA1_RX_DEPTH_DMA1_Msk (0x0fUL << I2S1_DMA1_RX_DEPTH_DMA1_Pos) /*!< I2S1 DMA1: RX_DEPTH_DMA1 Mask */ -#define I2S1_DMA1_TX_DEPTH_DMA1_Pos 16 /*!< I2S1 DMA1: TX_DEPTH_DMA1 Position */ -#define I2S1_DMA1_TX_DEPTH_DMA1_Msk (0x0fUL << I2S1_DMA1_TX_DEPTH_DMA1_Pos) /*!< I2S1 DMA1: TX_DEPTH_DMA1 Mask */ - -// ---------------------------------------- I2S1_DMA2 ------------------------------------------- -#define I2S1_DMA2_RX_DMA2_ENABLE_Pos 0 /*!< I2S1 DMA2: RX_DMA2_ENABLE Position */ -#define I2S1_DMA2_RX_DMA2_ENABLE_Msk (0x01UL << I2S1_DMA2_RX_DMA2_ENABLE_Pos) /*!< I2S1 DMA2: RX_DMA2_ENABLE Mask */ -#define I2S1_DMA2_TX_DMA2_ENABLE_Pos 1 /*!< I2S1 DMA2: TX_DMA2_ENABLE Position */ -#define I2S1_DMA2_TX_DMA2_ENABLE_Msk (0x01UL << I2S1_DMA2_TX_DMA2_ENABLE_Pos) /*!< I2S1 DMA2: TX_DMA2_ENABLE Mask */ -#define I2S1_DMA2_RX_DEPTH_DMA2_Pos 8 /*!< I2S1 DMA2: RX_DEPTH_DMA2 Position */ -#define I2S1_DMA2_RX_DEPTH_DMA2_Msk (0x0fUL << I2S1_DMA2_RX_DEPTH_DMA2_Pos) /*!< I2S1 DMA2: RX_DEPTH_DMA2 Mask */ -#define I2S1_DMA2_TX_DEPTH_DMA2_Pos 16 /*!< I2S1 DMA2: TX_DEPTH_DMA2 Position */ -#define I2S1_DMA2_TX_DEPTH_DMA2_Msk (0x0fUL << I2S1_DMA2_TX_DEPTH_DMA2_Pos) /*!< I2S1 DMA2: TX_DEPTH_DMA2 Mask */ - -// ---------------------------------------- I2S1_IRQ -------------------------------------------- -#define I2S1_IRQ_RX_IRQ_ENABLE_Pos 0 /*!< I2S1 IRQ: RX_IRQ_ENABLE Position */ -#define I2S1_IRQ_RX_IRQ_ENABLE_Msk (0x01UL << I2S1_IRQ_RX_IRQ_ENABLE_Pos) /*!< I2S1 IRQ: RX_IRQ_ENABLE Mask */ -#define I2S1_IRQ_TX_IRQ_ENABLE_Pos 1 /*!< I2S1 IRQ: TX_IRQ_ENABLE Position */ -#define I2S1_IRQ_TX_IRQ_ENABLE_Msk (0x01UL << I2S1_IRQ_TX_IRQ_ENABLE_Pos) /*!< I2S1 IRQ: TX_IRQ_ENABLE Mask */ -#define I2S1_IRQ_RX_DEPTH_IRQ_Pos 8 /*!< I2S1 IRQ: RX_DEPTH_IRQ Position */ -#define I2S1_IRQ_RX_DEPTH_IRQ_Msk (0x0fUL << I2S1_IRQ_RX_DEPTH_IRQ_Pos) /*!< I2S1 IRQ: RX_DEPTH_IRQ Mask */ -#define I2S1_IRQ_TX_DEPTH_IRQ_Pos 16 /*!< I2S1 IRQ: TX_DEPTH_IRQ Position */ -#define I2S1_IRQ_TX_DEPTH_IRQ_Msk (0x0fUL << I2S1_IRQ_TX_DEPTH_IRQ_Pos) /*!< I2S1 IRQ: TX_DEPTH_IRQ Mask */ - -// --------------------------------------- I2S1_TXRATE ------------------------------------------ -#define I2S1_TXRATE_Y_DIVIDER_Pos 0 /*!< I2S1 TXRATE: Y_DIVIDER Position */ -#define I2S1_TXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S1_TXRATE_Y_DIVIDER_Pos) /*!< I2S1 TXRATE: Y_DIVIDER Mask */ -#define I2S1_TXRATE_X_DIVIDER_Pos 8 /*!< I2S1 TXRATE: X_DIVIDER Position */ -#define I2S1_TXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S1_TXRATE_X_DIVIDER_Pos) /*!< I2S1 TXRATE: X_DIVIDER Mask */ - -// --------------------------------------- I2S1_RXRATE ------------------------------------------ -#define I2S1_RXRATE_Y_DIVIDER_Pos 0 /*!< I2S1 RXRATE: Y_DIVIDER Position */ -#define I2S1_RXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S1_RXRATE_Y_DIVIDER_Pos) /*!< I2S1 RXRATE: Y_DIVIDER Mask */ -#define I2S1_RXRATE_X_DIVIDER_Pos 8 /*!< I2S1 RXRATE: X_DIVIDER Position */ -#define I2S1_RXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S1_RXRATE_X_DIVIDER_Pos) /*!< I2S1 RXRATE: X_DIVIDER Mask */ - -// ------------------------------------- I2S1_TXBITRATE ----------------------------------------- -#define I2S1_TXBITRATE_TX_BITRATE_Pos 0 /*!< I2S1 TXBITRATE: TX_BITRATE Position */ -#define I2S1_TXBITRATE_TX_BITRATE_Msk (0x3fUL << I2S1_TXBITRATE_TX_BITRATE_Pos) /*!< I2S1 TXBITRATE: TX_BITRATE Mask */ - -// ------------------------------------- I2S1_RXBITRATE ----------------------------------------- -#define I2S1_RXBITRATE_RX_BITRATE_Pos 0 /*!< I2S1 RXBITRATE: RX_BITRATE Position */ -#define I2S1_RXBITRATE_RX_BITRATE_Msk (0x3fUL << I2S1_RXBITRATE_RX_BITRATE_Pos) /*!< I2S1 RXBITRATE: RX_BITRATE Mask */ - -// --------------------------------------- I2S1_TXMODE ------------------------------------------ -#define I2S1_TXMODE_TXCLKSEL_Pos 0 /*!< I2S1 TXMODE: TXCLKSEL Position */ -#define I2S1_TXMODE_TXCLKSEL_Msk (0x03UL << I2S1_TXMODE_TXCLKSEL_Pos) /*!< I2S1 TXMODE: TXCLKSEL Mask */ -#define I2S1_TXMODE_TX4PIN_Pos 2 /*!< I2S1 TXMODE: TX4PIN Position */ -#define I2S1_TXMODE_TX4PIN_Msk (0x01UL << I2S1_TXMODE_TX4PIN_Pos) /*!< I2S1 TXMODE: TX4PIN Mask */ -#define I2S1_TXMODE_TXMCENA_Pos 3 /*!< I2S1 TXMODE: TXMCENA Position */ -#define I2S1_TXMODE_TXMCENA_Msk (0x01UL << I2S1_TXMODE_TXMCENA_Pos) /*!< I2S1 TXMODE: TXMCENA Mask */ - -// --------------------------------------- I2S1_RXMODE ------------------------------------------ -#define I2S1_RXMODE_RXCLKSEL_Pos 0 /*!< I2S1 RXMODE: RXCLKSEL Position */ -#define I2S1_RXMODE_RXCLKSEL_Msk (0x03UL << I2S1_RXMODE_RXCLKSEL_Pos) /*!< I2S1 RXMODE: RXCLKSEL Mask */ -#define I2S1_RXMODE_RX4PIN_Pos 2 /*!< I2S1 RXMODE: RX4PIN Position */ -#define I2S1_RXMODE_RX4PIN_Msk (0x01UL << I2S1_RXMODE_RX4PIN_Pos) /*!< I2S1 RXMODE: RX4PIN Mask */ -#define I2S1_RXMODE_RXMCENA_Pos 3 /*!< I2S1 RXMODE: RXMCENA Position */ -#define I2S1_RXMODE_RXMCENA_Msk (0x01UL << I2S1_RXMODE_RXMCENA_Pos) /*!< I2S1 RXMODE: RXMCENA Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- C_CAN1 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- C_CAN1_CNTL ------------------------------------------ -#define C_CAN1_CNTL_INIT_Pos 0 /*!< C_CAN1 CNTL: INIT Position */ -#define C_CAN1_CNTL_INIT_Msk (0x01UL << C_CAN1_CNTL_INIT_Pos) /*!< C_CAN1 CNTL: INIT Mask */ -#define C_CAN1_CNTL_IE_Pos 1 /*!< C_CAN1 CNTL: IE Position */ -#define C_CAN1_CNTL_IE_Msk (0x01UL << C_CAN1_CNTL_IE_Pos) /*!< C_CAN1 CNTL: IE Mask */ -#define C_CAN1_CNTL_SIE_Pos 2 /*!< C_CAN1 CNTL: SIE Position */ -#define C_CAN1_CNTL_SIE_Msk (0x01UL << C_CAN1_CNTL_SIE_Pos) /*!< C_CAN1 CNTL: SIE Mask */ -#define C_CAN1_CNTL_EIE_Pos 3 /*!< C_CAN1 CNTL: EIE Position */ -#define C_CAN1_CNTL_EIE_Msk (0x01UL << C_CAN1_CNTL_EIE_Pos) /*!< C_CAN1 CNTL: EIE Mask */ -#define C_CAN1_CNTL_DAR_Pos 5 /*!< C_CAN1 CNTL: DAR Position */ -#define C_CAN1_CNTL_DAR_Msk (0x01UL << C_CAN1_CNTL_DAR_Pos) /*!< C_CAN1 CNTL: DAR Mask */ -#define C_CAN1_CNTL_CCE_Pos 6 /*!< C_CAN1 CNTL: CCE Position */ -#define C_CAN1_CNTL_CCE_Msk (0x01UL << C_CAN1_CNTL_CCE_Pos) /*!< C_CAN1 CNTL: CCE Mask */ -#define C_CAN1_CNTL_TEST_Pos 7 /*!< C_CAN1 CNTL: TEST Position */ -#define C_CAN1_CNTL_TEST_Msk (0x01UL << C_CAN1_CNTL_TEST_Pos) /*!< C_CAN1 CNTL: TEST Mask */ - -// --------------------------------------- C_CAN1_STAT ------------------------------------------ -#define C_CAN1_STAT_LEC_Pos 0 /*!< C_CAN1 STAT: LEC Position */ -#define C_CAN1_STAT_LEC_Msk (0x07UL << C_CAN1_STAT_LEC_Pos) /*!< C_CAN1 STAT: LEC Mask */ -#define C_CAN1_STAT_TXOK_Pos 3 /*!< C_CAN1 STAT: TXOK Position */ -#define C_CAN1_STAT_TXOK_Msk (0x01UL << C_CAN1_STAT_TXOK_Pos) /*!< C_CAN1 STAT: TXOK Mask */ -#define C_CAN1_STAT_RXOK_Pos 4 /*!< C_CAN1 STAT: RXOK Position */ -#define C_CAN1_STAT_RXOK_Msk (0x01UL << C_CAN1_STAT_RXOK_Pos) /*!< C_CAN1 STAT: RXOK Mask */ -#define C_CAN1_STAT_EPASS_Pos 5 /*!< C_CAN1 STAT: EPASS Position */ -#define C_CAN1_STAT_EPASS_Msk (0x01UL << C_CAN1_STAT_EPASS_Pos) /*!< C_CAN1 STAT: EPASS Mask */ -#define C_CAN1_STAT_EWARN_Pos 6 /*!< C_CAN1 STAT: EWARN Position */ -#define C_CAN1_STAT_EWARN_Msk (0x01UL << C_CAN1_STAT_EWARN_Pos) /*!< C_CAN1 STAT: EWARN Mask */ -#define C_CAN1_STAT_BOFF_Pos 7 /*!< C_CAN1 STAT: BOFF Position */ -#define C_CAN1_STAT_BOFF_Msk (0x01UL << C_CAN1_STAT_BOFF_Pos) /*!< C_CAN1 STAT: BOFF Mask */ - -// ---------------------------------------- C_CAN1_EC ------------------------------------------- -#define C_CAN1_EC_TEC_7_0_Pos 0 /*!< C_CAN1 EC: TEC_7_0 Position */ -#define C_CAN1_EC_TEC_7_0_Msk (0x000000ffUL << C_CAN1_EC_TEC_7_0_Pos) /*!< C_CAN1 EC: TEC_7_0 Mask */ -#define C_CAN1_EC_REC_6_0_Pos 8 /*!< C_CAN1 EC: REC_6_0 Position */ -#define C_CAN1_EC_REC_6_0_Msk (0x7fUL << C_CAN1_EC_REC_6_0_Pos) /*!< C_CAN1 EC: REC_6_0 Mask */ -#define C_CAN1_EC_RP_Pos 15 /*!< C_CAN1 EC: RP Position */ -#define C_CAN1_EC_RP_Msk (0x01UL << C_CAN1_EC_RP_Pos) /*!< C_CAN1 EC: RP Mask */ - -// ---------------------------------------- C_CAN1_BT ------------------------------------------- -#define C_CAN1_BT_BRP_Pos 0 /*!< C_CAN1 BT: BRP Position */ -#define C_CAN1_BT_BRP_Msk (0x3fUL << C_CAN1_BT_BRP_Pos) /*!< C_CAN1 BT: BRP Mask */ -#define C_CAN1_BT_SJW_Pos 6 /*!< C_CAN1 BT: SJW Position */ -#define C_CAN1_BT_SJW_Msk (0x03UL << C_CAN1_BT_SJW_Pos) /*!< C_CAN1 BT: SJW Mask */ -#define C_CAN1_BT_TSEG1_Pos 8 /*!< C_CAN1 BT: TSEG1 Position */ -#define C_CAN1_BT_TSEG1_Msk (0x0fUL << C_CAN1_BT_TSEG1_Pos) /*!< C_CAN1 BT: TSEG1 Mask */ -#define C_CAN1_BT_TSEG2_Pos 12 /*!< C_CAN1 BT: TSEG2 Position */ -#define C_CAN1_BT_TSEG2_Msk (0x07UL << C_CAN1_BT_TSEG2_Pos) /*!< C_CAN1 BT: TSEG2 Mask */ - -// --------------------------------------- C_CAN1_INT ------------------------------------------- -#define C_CAN1_INT_INTID15_0_Pos 0 /*!< C_CAN1 INT: INTID15_0 Position */ -#define C_CAN1_INT_INTID15_0_Msk (0x0000ffffUL << C_CAN1_INT_INTID15_0_Pos) /*!< C_CAN1 INT: INTID15_0 Mask */ - -// --------------------------------------- C_CAN1_TEST ------------------------------------------ -#define C_CAN1_TEST_BASIC_Pos 2 /*!< C_CAN1 TEST: BASIC Position */ -#define C_CAN1_TEST_BASIC_Msk (0x01UL << C_CAN1_TEST_BASIC_Pos) /*!< C_CAN1 TEST: BASIC Mask */ -#define C_CAN1_TEST_SILENT_Pos 3 /*!< C_CAN1 TEST: SILENT Position */ -#define C_CAN1_TEST_SILENT_Msk (0x01UL << C_CAN1_TEST_SILENT_Pos) /*!< C_CAN1 TEST: SILENT Mask */ -#define C_CAN1_TEST_LBACK_Pos 4 /*!< C_CAN1 TEST: LBACK Position */ -#define C_CAN1_TEST_LBACK_Msk (0x01UL << C_CAN1_TEST_LBACK_Pos) /*!< C_CAN1 TEST: LBACK Mask */ -#define C_CAN1_TEST_TX1_0_Pos 5 /*!< C_CAN1 TEST: TX1_0 Position */ -#define C_CAN1_TEST_TX1_0_Msk (0x03UL << C_CAN1_TEST_TX1_0_Pos) /*!< C_CAN1 TEST: TX1_0 Mask */ -#define C_CAN1_TEST_RX_Pos 7 /*!< C_CAN1 TEST: RX Position */ -#define C_CAN1_TEST_RX_Msk (0x01UL << C_CAN1_TEST_RX_Pos) /*!< C_CAN1 TEST: RX Mask */ - -// --------------------------------------- C_CAN1_BRPE ------------------------------------------ -#define C_CAN1_BRPE_BRPE_Pos 0 /*!< C_CAN1 BRPE: BRPE Position */ -#define C_CAN1_BRPE_BRPE_Msk (0x0fUL << C_CAN1_BRPE_BRPE_Pos) /*!< C_CAN1 BRPE: BRPE Mask */ - -// ------------------------------------ C_CAN1_IF1_CMDREQ --------------------------------------- -#define C_CAN1_IF1_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN1 IF1_CMDREQ: MESSNUM Position */ -#define C_CAN1_IF1_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN1_IF1_CMDREQ_MESSNUM_Pos) /*!< C_CAN1 IF1_CMDREQ: MESSNUM Mask */ -#define C_CAN1_IF1_CMDREQ_BUSY_Pos 15 /*!< C_CAN1 IF1_CMDREQ: BUSY Position */ -#define C_CAN1_IF1_CMDREQ_BUSY_Msk (0x01UL << C_CAN1_IF1_CMDREQ_BUSY_Pos) /*!< C_CAN1 IF1_CMDREQ: BUSY Mask */ - -// ----------------------------------- C_CAN1_IF1_CMDMSK_W -------------------------------------- -#define C_CAN1_IF1_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN1 IF1_CMDMSK_W: DATA_B Position */ -#define C_CAN1_IF1_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_B_Pos) /*!< C_CAN1 IF1_CMDMSK_W: DATA_B Mask */ -#define C_CAN1_IF1_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN1 IF1_CMDMSK_W: DATA_A Position */ -#define C_CAN1_IF1_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_A_Pos) /*!< C_CAN1 IF1_CMDMSK_W: DATA_A Mask */ -#define C_CAN1_IF1_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN1 IF1_CMDMSK_W: TXRQST Position */ -#define C_CAN1_IF1_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_TXRQST_Pos) /*!< C_CAN1 IF1_CMDMSK_W: TXRQST Mask */ -#define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN1 IF1_CMDMSK_W: CLRINTPND Position */ -#define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN1 IF1_CMDMSK_W: CLRINTPND Mask */ -#define C_CAN1_IF1_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN1 IF1_CMDMSK_W: CTRL Position */ -#define C_CAN1_IF1_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_CTRL_Pos) /*!< C_CAN1 IF1_CMDMSK_W: CTRL Mask */ -#define C_CAN1_IF1_CMDMSK_W_ARB_Pos 5 /*!< C_CAN1 IF1_CMDMSK_W: ARB Position */ -#define C_CAN1_IF1_CMDMSK_W_ARB_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_ARB_Pos) /*!< C_CAN1 IF1_CMDMSK_W: ARB Mask */ -#define C_CAN1_IF1_CMDMSK_W_MASK_Pos 6 /*!< C_CAN1 IF1_CMDMSK_W: MASK Position */ -#define C_CAN1_IF1_CMDMSK_W_MASK_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_MASK_Pos) /*!< C_CAN1 IF1_CMDMSK_W: MASK Mask */ -#define C_CAN1_IF1_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN1 IF1_CMDMSK_W: WR_RD Position */ -#define C_CAN1_IF1_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_WR_RD_Pos) /*!< C_CAN1 IF1_CMDMSK_W: WR_RD Mask */ - -// ----------------------------------- C_CAN1_IF1_CMDMSK_R -------------------------------------- -#define C_CAN1_IF1_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN1 IF1_CMDMSK_R: DATA_B Position */ -#define C_CAN1_IF1_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_B_Pos) /*!< C_CAN1 IF1_CMDMSK_R: DATA_B Mask */ -#define C_CAN1_IF1_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN1 IF1_CMDMSK_R: DATA_A Position */ -#define C_CAN1_IF1_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_A_Pos) /*!< C_CAN1 IF1_CMDMSK_R: DATA_A Mask */ -#define C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN1 IF1_CMDMSK_R: NEWDAT Position */ -#define C_CAN1_IF1_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN1 IF1_CMDMSK_R: NEWDAT Mask */ -#define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN1 IF1_CMDMSK_R: CLRINTPND Position */ -#define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN1 IF1_CMDMSK_R: CLRINTPND Mask */ -#define C_CAN1_IF1_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN1 IF1_CMDMSK_R: CTRL Position */ -#define C_CAN1_IF1_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_CTRL_Pos) /*!< C_CAN1 IF1_CMDMSK_R: CTRL Mask */ -#define C_CAN1_IF1_CMDMSK_R_ARB_Pos 5 /*!< C_CAN1 IF1_CMDMSK_R: ARB Position */ -#define C_CAN1_IF1_CMDMSK_R_ARB_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_ARB_Pos) /*!< C_CAN1 IF1_CMDMSK_R: ARB Mask */ -#define C_CAN1_IF1_CMDMSK_R_MASK_Pos 6 /*!< C_CAN1 IF1_CMDMSK_R: MASK Position */ -#define C_CAN1_IF1_CMDMSK_R_MASK_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_MASK_Pos) /*!< C_CAN1 IF1_CMDMSK_R: MASK Mask */ -#define C_CAN1_IF1_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN1 IF1_CMDMSK_R: WR_RD Position */ -#define C_CAN1_IF1_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_WR_RD_Pos) /*!< C_CAN1 IF1_CMDMSK_R: WR_RD Mask */ - -// ------------------------------------- C_CAN1_IF1_MSK1 ---------------------------------------- -#define C_CAN1_IF1_MSK1_MSK15_0_Pos 0 /*!< C_CAN1 IF1_MSK1: MSK15_0 Position */ -#define C_CAN1_IF1_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN1_IF1_MSK1_MSK15_0_Pos) /*!< C_CAN1 IF1_MSK1: MSK15_0 Mask */ - -// ------------------------------------- C_CAN1_IF1_MSK2 ---------------------------------------- -#define C_CAN1_IF1_MSK2_MSK28_16_Pos 0 /*!< C_CAN1 IF1_MSK2: MSK28_16 Position */ -#define C_CAN1_IF1_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN1_IF1_MSK2_MSK28_16_Pos) /*!< C_CAN1 IF1_MSK2: MSK28_16 Mask */ -#define C_CAN1_IF1_MSK2_MDIR_Pos 14 /*!< C_CAN1 IF1_MSK2: MDIR Position */ -#define C_CAN1_IF1_MSK2_MDIR_Msk (0x01UL << C_CAN1_IF1_MSK2_MDIR_Pos) /*!< C_CAN1 IF1_MSK2: MDIR Mask */ -#define C_CAN1_IF1_MSK2_MXTD_Pos 15 /*!< C_CAN1 IF1_MSK2: MXTD Position */ -#define C_CAN1_IF1_MSK2_MXTD_Msk (0x01UL << C_CAN1_IF1_MSK2_MXTD_Pos) /*!< C_CAN1 IF1_MSK2: MXTD Mask */ - -// ------------------------------------- C_CAN1_IF1_ARB1 ---------------------------------------- -#define C_CAN1_IF1_ARB1_ID15_0_Pos 0 /*!< C_CAN1 IF1_ARB1: ID15_0 Position */ -#define C_CAN1_IF1_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN1_IF1_ARB1_ID15_0_Pos) /*!< C_CAN1 IF1_ARB1: ID15_0 Mask */ - -// ------------------------------------- C_CAN1_IF1_ARB2 ---------------------------------------- -#define C_CAN1_IF1_ARB2_ID28_16_Pos 0 /*!< C_CAN1 IF1_ARB2: ID28_16 Position */ -#define C_CAN1_IF1_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN1_IF1_ARB2_ID28_16_Pos) /*!< C_CAN1 IF1_ARB2: ID28_16 Mask */ -#define C_CAN1_IF1_ARB2_DIR_Pos 13 /*!< C_CAN1 IF1_ARB2: DIR Position */ -#define C_CAN1_IF1_ARB2_DIR_Msk (0x01UL << C_CAN1_IF1_ARB2_DIR_Pos) /*!< C_CAN1 IF1_ARB2: DIR Mask */ -#define C_CAN1_IF1_ARB2_XTD_Pos 14 /*!< C_CAN1 IF1_ARB2: XTD Position */ -#define C_CAN1_IF1_ARB2_XTD_Msk (0x01UL << C_CAN1_IF1_ARB2_XTD_Pos) /*!< C_CAN1 IF1_ARB2: XTD Mask */ -#define C_CAN1_IF1_ARB2_MSGVAL_Pos 15 /*!< C_CAN1 IF1_ARB2: MSGVAL Position */ -#define C_CAN1_IF1_ARB2_MSGVAL_Msk (0x01UL << C_CAN1_IF1_ARB2_MSGVAL_Pos) /*!< C_CAN1 IF1_ARB2: MSGVAL Mask */ - -// ------------------------------------ C_CAN1_IF1_MCTRL ---------------------------------------- -#define C_CAN1_IF1_MCTRL_DLC3_0_Pos 0 /*!< C_CAN1 IF1_MCTRL: DLC3_0 Position */ -#define C_CAN1_IF1_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN1_IF1_MCTRL_DLC3_0_Pos) /*!< C_CAN1 IF1_MCTRL: DLC3_0 Mask */ -#define C_CAN1_IF1_MCTRL_EOB_Pos 7 /*!< C_CAN1 IF1_MCTRL: EOB Position */ -#define C_CAN1_IF1_MCTRL_EOB_Msk (0x01UL << C_CAN1_IF1_MCTRL_EOB_Pos) /*!< C_CAN1 IF1_MCTRL: EOB Mask */ -#define C_CAN1_IF1_MCTRL_TXRQST_Pos 8 /*!< C_CAN1 IF1_MCTRL: TXRQST Position */ -#define C_CAN1_IF1_MCTRL_TXRQST_Msk (0x01UL << C_CAN1_IF1_MCTRL_TXRQST_Pos) /*!< C_CAN1 IF1_MCTRL: TXRQST Mask */ -#define C_CAN1_IF1_MCTRL_RMTEN_Pos 9 /*!< C_CAN1 IF1_MCTRL: RMTEN Position */ -#define C_CAN1_IF1_MCTRL_RMTEN_Msk (0x01UL << C_CAN1_IF1_MCTRL_RMTEN_Pos) /*!< C_CAN1 IF1_MCTRL: RMTEN Mask */ -#define C_CAN1_IF1_MCTRL_RXIE_Pos 10 /*!< C_CAN1 IF1_MCTRL: RXIE Position */ -#define C_CAN1_IF1_MCTRL_RXIE_Msk (0x01UL << C_CAN1_IF1_MCTRL_RXIE_Pos) /*!< C_CAN1 IF1_MCTRL: RXIE Mask */ -#define C_CAN1_IF1_MCTRL_TXIE_Pos 11 /*!< C_CAN1 IF1_MCTRL: TXIE Position */ -#define C_CAN1_IF1_MCTRL_TXIE_Msk (0x01UL << C_CAN1_IF1_MCTRL_TXIE_Pos) /*!< C_CAN1 IF1_MCTRL: TXIE Mask */ -#define C_CAN1_IF1_MCTRL_UMASK_Pos 12 /*!< C_CAN1 IF1_MCTRL: UMASK Position */ -#define C_CAN1_IF1_MCTRL_UMASK_Msk (0x01UL << C_CAN1_IF1_MCTRL_UMASK_Pos) /*!< C_CAN1 IF1_MCTRL: UMASK Mask */ -#define C_CAN1_IF1_MCTRL_INTPND_Pos 13 /*!< C_CAN1 IF1_MCTRL: INTPND Position */ -#define C_CAN1_IF1_MCTRL_INTPND_Msk (0x01UL << C_CAN1_IF1_MCTRL_INTPND_Pos) /*!< C_CAN1 IF1_MCTRL: INTPND Mask */ -#define C_CAN1_IF1_MCTRL_MSGLST_Pos 14 /*!< C_CAN1 IF1_MCTRL: MSGLST Position */ -#define C_CAN1_IF1_MCTRL_MSGLST_Msk (0x01UL << C_CAN1_IF1_MCTRL_MSGLST_Pos) /*!< C_CAN1 IF1_MCTRL: MSGLST Mask */ -#define C_CAN1_IF1_MCTRL_NEWDAT_Pos 15 /*!< C_CAN1 IF1_MCTRL: NEWDAT Position */ -#define C_CAN1_IF1_MCTRL_NEWDAT_Msk (0x01UL << C_CAN1_IF1_MCTRL_NEWDAT_Pos) /*!< C_CAN1 IF1_MCTRL: NEWDAT Mask */ - -// ------------------------------------- C_CAN1_IF1_DA1 ----------------------------------------- -#define C_CAN1_IF1_DA1_DATA0_Pos 0 /*!< C_CAN1 IF1_DA1: DATA0 Position */ -#define C_CAN1_IF1_DA1_DATA0_Msk (0x000000ffUL << C_CAN1_IF1_DA1_DATA0_Pos) /*!< C_CAN1 IF1_DA1: DATA0 Mask */ -#define C_CAN1_IF1_DA1_DATA1_Pos 8 /*!< C_CAN1 IF1_DA1: DATA1 Position */ -#define C_CAN1_IF1_DA1_DATA1_Msk (0x000000ffUL << C_CAN1_IF1_DA1_DATA1_Pos) /*!< C_CAN1 IF1_DA1: DATA1 Mask */ - -// ------------------------------------- C_CAN1_IF1_DA2 ----------------------------------------- -#define C_CAN1_IF1_DA2_DATA2_Pos 0 /*!< C_CAN1 IF1_DA2: DATA2 Position */ -#define C_CAN1_IF1_DA2_DATA2_Msk (0x000000ffUL << C_CAN1_IF1_DA2_DATA2_Pos) /*!< C_CAN1 IF1_DA2: DATA2 Mask */ -#define C_CAN1_IF1_DA2_DATA3_Pos 8 /*!< C_CAN1 IF1_DA2: DATA3 Position */ -#define C_CAN1_IF1_DA2_DATA3_Msk (0x000000ffUL << C_CAN1_IF1_DA2_DATA3_Pos) /*!< C_CAN1 IF1_DA2: DATA3 Mask */ - -// ------------------------------------- C_CAN1_IF1_DB1 ----------------------------------------- -#define C_CAN1_IF1_DB1_DATA4_Pos 0 /*!< C_CAN1 IF1_DB1: DATA4 Position */ -#define C_CAN1_IF1_DB1_DATA4_Msk (0x000000ffUL << C_CAN1_IF1_DB1_DATA4_Pos) /*!< C_CAN1 IF1_DB1: DATA4 Mask */ -#define C_CAN1_IF1_DB1_DATA5_Pos 8 /*!< C_CAN1 IF1_DB1: DATA5 Position */ -#define C_CAN1_IF1_DB1_DATA5_Msk (0x000000ffUL << C_CAN1_IF1_DB1_DATA5_Pos) /*!< C_CAN1 IF1_DB1: DATA5 Mask */ - -// ------------------------------------- C_CAN1_IF1_DB2 ----------------------------------------- -#define C_CAN1_IF1_DB2_DATA6_Pos 0 /*!< C_CAN1 IF1_DB2: DATA6 Position */ -#define C_CAN1_IF1_DB2_DATA6_Msk (0x000000ffUL << C_CAN1_IF1_DB2_DATA6_Pos) /*!< C_CAN1 IF1_DB2: DATA6 Mask */ -#define C_CAN1_IF1_DB2_DATA7_Pos 8 /*!< C_CAN1 IF1_DB2: DATA7 Position */ -#define C_CAN1_IF1_DB2_DATA7_Msk (0x000000ffUL << C_CAN1_IF1_DB2_DATA7_Pos) /*!< C_CAN1 IF1_DB2: DATA7 Mask */ - -// ------------------------------------ C_CAN1_IF2_CMDREQ --------------------------------------- -#define C_CAN1_IF2_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN1 IF2_CMDREQ: MESSNUM Position */ -#define C_CAN1_IF2_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN1_IF2_CMDREQ_MESSNUM_Pos) /*!< C_CAN1 IF2_CMDREQ: MESSNUM Mask */ -#define C_CAN1_IF2_CMDREQ_BUSY_Pos 15 /*!< C_CAN1 IF2_CMDREQ: BUSY Position */ -#define C_CAN1_IF2_CMDREQ_BUSY_Msk (0x01UL << C_CAN1_IF2_CMDREQ_BUSY_Pos) /*!< C_CAN1 IF2_CMDREQ: BUSY Mask */ - -// ----------------------------------- C_CAN1_IF2_CMDMSK_W -------------------------------------- -#define C_CAN1_IF2_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN1 IF2_CMDMSK_W: DATA_B Position */ -#define C_CAN1_IF2_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_B_Pos) /*!< C_CAN1 IF2_CMDMSK_W: DATA_B Mask */ -#define C_CAN1_IF2_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN1 IF2_CMDMSK_W: DATA_A Position */ -#define C_CAN1_IF2_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_A_Pos) /*!< C_CAN1 IF2_CMDMSK_W: DATA_A Mask */ -#define C_CAN1_IF2_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN1 IF2_CMDMSK_W: TXRQST Position */ -#define C_CAN1_IF2_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_TXRQST_Pos) /*!< C_CAN1 IF2_CMDMSK_W: TXRQST Mask */ -#define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN1 IF2_CMDMSK_W: CLRINTPND Position */ -#define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN1 IF2_CMDMSK_W: CLRINTPND Mask */ -#define C_CAN1_IF2_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN1 IF2_CMDMSK_W: CTRL Position */ -#define C_CAN1_IF2_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_CTRL_Pos) /*!< C_CAN1 IF2_CMDMSK_W: CTRL Mask */ -#define C_CAN1_IF2_CMDMSK_W_ARB_Pos 5 /*!< C_CAN1 IF2_CMDMSK_W: ARB Position */ -#define C_CAN1_IF2_CMDMSK_W_ARB_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_ARB_Pos) /*!< C_CAN1 IF2_CMDMSK_W: ARB Mask */ -#define C_CAN1_IF2_CMDMSK_W_MASK_Pos 6 /*!< C_CAN1 IF2_CMDMSK_W: MASK Position */ -#define C_CAN1_IF2_CMDMSK_W_MASK_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_MASK_Pos) /*!< C_CAN1 IF2_CMDMSK_W: MASK Mask */ -#define C_CAN1_IF2_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN1 IF2_CMDMSK_W: WR_RD Position */ -#define C_CAN1_IF2_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_WR_RD_Pos) /*!< C_CAN1 IF2_CMDMSK_W: WR_RD Mask */ - -// ----------------------------------- C_CAN1_IF2_CMDMSK_R -------------------------------------- -#define C_CAN1_IF2_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN1 IF2_CMDMSK_R: DATA_B Position */ -#define C_CAN1_IF2_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_B_Pos) /*!< C_CAN1 IF2_CMDMSK_R: DATA_B Mask */ -#define C_CAN1_IF2_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN1 IF2_CMDMSK_R: DATA_A Position */ -#define C_CAN1_IF2_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_A_Pos) /*!< C_CAN1 IF2_CMDMSK_R: DATA_A Mask */ -#define C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN1 IF2_CMDMSK_R: NEWDAT Position */ -#define C_CAN1_IF2_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN1 IF2_CMDMSK_R: NEWDAT Mask */ -#define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN1 IF2_CMDMSK_R: CLRINTPND Position */ -#define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN1 IF2_CMDMSK_R: CLRINTPND Mask */ -#define C_CAN1_IF2_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN1 IF2_CMDMSK_R: CTRL Position */ -#define C_CAN1_IF2_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_CTRL_Pos) /*!< C_CAN1 IF2_CMDMSK_R: CTRL Mask */ -#define C_CAN1_IF2_CMDMSK_R_ARB_Pos 5 /*!< C_CAN1 IF2_CMDMSK_R: ARB Position */ -#define C_CAN1_IF2_CMDMSK_R_ARB_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_ARB_Pos) /*!< C_CAN1 IF2_CMDMSK_R: ARB Mask */ -#define C_CAN1_IF2_CMDMSK_R_MASK_Pos 6 /*!< C_CAN1 IF2_CMDMSK_R: MASK Position */ -#define C_CAN1_IF2_CMDMSK_R_MASK_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_MASK_Pos) /*!< C_CAN1 IF2_CMDMSK_R: MASK Mask */ -#define C_CAN1_IF2_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN1 IF2_CMDMSK_R: WR_RD Position */ -#define C_CAN1_IF2_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_WR_RD_Pos) /*!< C_CAN1 IF2_CMDMSK_R: WR_RD Mask */ - -// ------------------------------------- C_CAN1_IF2_MSK1 ---------------------------------------- -#define C_CAN1_IF2_MSK1_MSK15_0_Pos 0 /*!< C_CAN1 IF2_MSK1: MSK15_0 Position */ -#define C_CAN1_IF2_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN1_IF2_MSK1_MSK15_0_Pos) /*!< C_CAN1 IF2_MSK1: MSK15_0 Mask */ - -// ------------------------------------- C_CAN1_IF2_MSK2 ---------------------------------------- -#define C_CAN1_IF2_MSK2_MSK28_16_Pos 0 /*!< C_CAN1 IF2_MSK2: MSK28_16 Position */ -#define C_CAN1_IF2_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN1_IF2_MSK2_MSK28_16_Pos) /*!< C_CAN1 IF2_MSK2: MSK28_16 Mask */ -#define C_CAN1_IF2_MSK2_MDIR_Pos 14 /*!< C_CAN1 IF2_MSK2: MDIR Position */ -#define C_CAN1_IF2_MSK2_MDIR_Msk (0x01UL << C_CAN1_IF2_MSK2_MDIR_Pos) /*!< C_CAN1 IF2_MSK2: MDIR Mask */ -#define C_CAN1_IF2_MSK2_MXTD_Pos 15 /*!< C_CAN1 IF2_MSK2: MXTD Position */ -#define C_CAN1_IF2_MSK2_MXTD_Msk (0x01UL << C_CAN1_IF2_MSK2_MXTD_Pos) /*!< C_CAN1 IF2_MSK2: MXTD Mask */ - -// ------------------------------------- C_CAN1_IF2_ARB1 ---------------------------------------- -#define C_CAN1_IF2_ARB1_ID15_0_Pos 0 /*!< C_CAN1 IF2_ARB1: ID15_0 Position */ -#define C_CAN1_IF2_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN1_IF2_ARB1_ID15_0_Pos) /*!< C_CAN1 IF2_ARB1: ID15_0 Mask */ - -// ------------------------------------- C_CAN1_IF2_ARB2 ---------------------------------------- -#define C_CAN1_IF2_ARB2_ID28_16_Pos 0 /*!< C_CAN1 IF2_ARB2: ID28_16 Position */ -#define C_CAN1_IF2_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN1_IF2_ARB2_ID28_16_Pos) /*!< C_CAN1 IF2_ARB2: ID28_16 Mask */ -#define C_CAN1_IF2_ARB2_DIR_Pos 13 /*!< C_CAN1 IF2_ARB2: DIR Position */ -#define C_CAN1_IF2_ARB2_DIR_Msk (0x01UL << C_CAN1_IF2_ARB2_DIR_Pos) /*!< C_CAN1 IF2_ARB2: DIR Mask */ -#define C_CAN1_IF2_ARB2_XTD_Pos 14 /*!< C_CAN1 IF2_ARB2: XTD Position */ -#define C_CAN1_IF2_ARB2_XTD_Msk (0x01UL << C_CAN1_IF2_ARB2_XTD_Pos) /*!< C_CAN1 IF2_ARB2: XTD Mask */ -#define C_CAN1_IF2_ARB2_MSGVAL_Pos 15 /*!< C_CAN1 IF2_ARB2: MSGVAL Position */ -#define C_CAN1_IF2_ARB2_MSGVAL_Msk (0x01UL << C_CAN1_IF2_ARB2_MSGVAL_Pos) /*!< C_CAN1 IF2_ARB2: MSGVAL Mask */ - -// ------------------------------------ C_CAN1_IF2_MCTRL ---------------------------------------- -#define C_CAN1_IF2_MCTRL_DLC3_0_Pos 0 /*!< C_CAN1 IF2_MCTRL: DLC3_0 Position */ -#define C_CAN1_IF2_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN1_IF2_MCTRL_DLC3_0_Pos) /*!< C_CAN1 IF2_MCTRL: DLC3_0 Mask */ -#define C_CAN1_IF2_MCTRL_EOB_Pos 7 /*!< C_CAN1 IF2_MCTRL: EOB Position */ -#define C_CAN1_IF2_MCTRL_EOB_Msk (0x01UL << C_CAN1_IF2_MCTRL_EOB_Pos) /*!< C_CAN1 IF2_MCTRL: EOB Mask */ -#define C_CAN1_IF2_MCTRL_TXRQST_Pos 8 /*!< C_CAN1 IF2_MCTRL: TXRQST Position */ -#define C_CAN1_IF2_MCTRL_TXRQST_Msk (0x01UL << C_CAN1_IF2_MCTRL_TXRQST_Pos) /*!< C_CAN1 IF2_MCTRL: TXRQST Mask */ -#define C_CAN1_IF2_MCTRL_RMTEN_Pos 9 /*!< C_CAN1 IF2_MCTRL: RMTEN Position */ -#define C_CAN1_IF2_MCTRL_RMTEN_Msk (0x01UL << C_CAN1_IF2_MCTRL_RMTEN_Pos) /*!< C_CAN1 IF2_MCTRL: RMTEN Mask */ -#define C_CAN1_IF2_MCTRL_RXIE_Pos 10 /*!< C_CAN1 IF2_MCTRL: RXIE Position */ -#define C_CAN1_IF2_MCTRL_RXIE_Msk (0x01UL << C_CAN1_IF2_MCTRL_RXIE_Pos) /*!< C_CAN1 IF2_MCTRL: RXIE Mask */ -#define C_CAN1_IF2_MCTRL_TXIE_Pos 11 /*!< C_CAN1 IF2_MCTRL: TXIE Position */ -#define C_CAN1_IF2_MCTRL_TXIE_Msk (0x01UL << C_CAN1_IF2_MCTRL_TXIE_Pos) /*!< C_CAN1 IF2_MCTRL: TXIE Mask */ -#define C_CAN1_IF2_MCTRL_UMASK_Pos 12 /*!< C_CAN1 IF2_MCTRL: UMASK Position */ -#define C_CAN1_IF2_MCTRL_UMASK_Msk (0x01UL << C_CAN1_IF2_MCTRL_UMASK_Pos) /*!< C_CAN1 IF2_MCTRL: UMASK Mask */ -#define C_CAN1_IF2_MCTRL_INTPND_Pos 13 /*!< C_CAN1 IF2_MCTRL: INTPND Position */ -#define C_CAN1_IF2_MCTRL_INTPND_Msk (0x01UL << C_CAN1_IF2_MCTRL_INTPND_Pos) /*!< C_CAN1 IF2_MCTRL: INTPND Mask */ -#define C_CAN1_IF2_MCTRL_MSGLST_Pos 14 /*!< C_CAN1 IF2_MCTRL: MSGLST Position */ -#define C_CAN1_IF2_MCTRL_MSGLST_Msk (0x01UL << C_CAN1_IF2_MCTRL_MSGLST_Pos) /*!< C_CAN1 IF2_MCTRL: MSGLST Mask */ -#define C_CAN1_IF2_MCTRL_NEWDAT_Pos 15 /*!< C_CAN1 IF2_MCTRL: NEWDAT Position */ -#define C_CAN1_IF2_MCTRL_NEWDAT_Msk (0x01UL << C_CAN1_IF2_MCTRL_NEWDAT_Pos) /*!< C_CAN1 IF2_MCTRL: NEWDAT Mask */ - -// ------------------------------------- C_CAN1_IF2_DA1 ----------------------------------------- -#define C_CAN1_IF2_DA1_DATA0_Pos 0 /*!< C_CAN1 IF2_DA1: DATA0 Position */ -#define C_CAN1_IF2_DA1_DATA0_Msk (0x000000ffUL << C_CAN1_IF2_DA1_DATA0_Pos) /*!< C_CAN1 IF2_DA1: DATA0 Mask */ -#define C_CAN1_IF2_DA1_DATA1_Pos 8 /*!< C_CAN1 IF2_DA1: DATA1 Position */ -#define C_CAN1_IF2_DA1_DATA1_Msk (0x000000ffUL << C_CAN1_IF2_DA1_DATA1_Pos) /*!< C_CAN1 IF2_DA1: DATA1 Mask */ - -// ------------------------------------- C_CAN1_IF2_DA2 ----------------------------------------- -#define C_CAN1_IF2_DA2_DATA2_Pos 0 /*!< C_CAN1 IF2_DA2: DATA2 Position */ -#define C_CAN1_IF2_DA2_DATA2_Msk (0x000000ffUL << C_CAN1_IF2_DA2_DATA2_Pos) /*!< C_CAN1 IF2_DA2: DATA2 Mask */ -#define C_CAN1_IF2_DA2_DATA3_Pos 8 /*!< C_CAN1 IF2_DA2: DATA3 Position */ -#define C_CAN1_IF2_DA2_DATA3_Msk (0x000000ffUL << C_CAN1_IF2_DA2_DATA3_Pos) /*!< C_CAN1 IF2_DA2: DATA3 Mask */ - -// ------------------------------------- C_CAN1_IF2_DB1 ----------------------------------------- -#define C_CAN1_IF2_DB1_DATA4_Pos 0 /*!< C_CAN1 IF2_DB1: DATA4 Position */ -#define C_CAN1_IF2_DB1_DATA4_Msk (0x000000ffUL << C_CAN1_IF2_DB1_DATA4_Pos) /*!< C_CAN1 IF2_DB1: DATA4 Mask */ -#define C_CAN1_IF2_DB1_DATA5_Pos 8 /*!< C_CAN1 IF2_DB1: DATA5 Position */ -#define C_CAN1_IF2_DB1_DATA5_Msk (0x000000ffUL << C_CAN1_IF2_DB1_DATA5_Pos) /*!< C_CAN1 IF2_DB1: DATA5 Mask */ - -// ------------------------------------- C_CAN1_IF2_DB2 ----------------------------------------- -#define C_CAN1_IF2_DB2_DATA6_Pos 0 /*!< C_CAN1 IF2_DB2: DATA6 Position */ -#define C_CAN1_IF2_DB2_DATA6_Msk (0x000000ffUL << C_CAN1_IF2_DB2_DATA6_Pos) /*!< C_CAN1 IF2_DB2: DATA6 Mask */ -#define C_CAN1_IF2_DB2_DATA7_Pos 8 /*!< C_CAN1 IF2_DB2: DATA7 Position */ -#define C_CAN1_IF2_DB2_DATA7_Msk (0x000000ffUL << C_CAN1_IF2_DB2_DATA7_Pos) /*!< C_CAN1 IF2_DB2: DATA7 Mask */ - -// -------------------------------------- C_CAN1_TXREQ1 ----------------------------------------- -#define C_CAN1_TXREQ1_TXRQST16_1_Pos 0 /*!< C_CAN1 TXREQ1: TXRQST16_1 Position */ -#define C_CAN1_TXREQ1_TXRQST16_1_Msk (0x0000ffffUL << C_CAN1_TXREQ1_TXRQST16_1_Pos) /*!< C_CAN1 TXREQ1: TXRQST16_1 Mask */ - -// -------------------------------------- C_CAN1_TXREQ2 ----------------------------------------- -#define C_CAN1_TXREQ2_TXRQST32_17_Pos 0 /*!< C_CAN1 TXREQ2: TXRQST32_17 Position */ -#define C_CAN1_TXREQ2_TXRQST32_17_Msk (0x0000ffffUL << C_CAN1_TXREQ2_TXRQST32_17_Pos) /*!< C_CAN1 TXREQ2: TXRQST32_17 Mask */ - -// --------------------------------------- C_CAN1_ND1 ------------------------------------------- -#define C_CAN1_ND1_NEWDAT16_1_Pos 0 /*!< C_CAN1 ND1: NEWDAT16_1 Position */ -#define C_CAN1_ND1_NEWDAT16_1_Msk (0x0000ffffUL << C_CAN1_ND1_NEWDAT16_1_Pos) /*!< C_CAN1 ND1: NEWDAT16_1 Mask */ - -// --------------------------------------- C_CAN1_ND2 ------------------------------------------- -#define C_CAN1_ND2_NEWDAT32_17_Pos 0 /*!< C_CAN1 ND2: NEWDAT32_17 Position */ -#define C_CAN1_ND2_NEWDAT32_17_Msk (0x0000ffffUL << C_CAN1_ND2_NEWDAT32_17_Pos) /*!< C_CAN1 ND2: NEWDAT32_17 Mask */ - -// --------------------------------------- C_CAN1_IR1 ------------------------------------------- -#define C_CAN1_IR1_INTPND16_1_Pos 0 /*!< C_CAN1 IR1: INTPND16_1 Position */ -#define C_CAN1_IR1_INTPND16_1_Msk (0x0000ffffUL << C_CAN1_IR1_INTPND16_1_Pos) /*!< C_CAN1 IR1: INTPND16_1 Mask */ - -// --------------------------------------- C_CAN1_IR2 ------------------------------------------- -#define C_CAN1_IR2_INTPND32_17_Pos 0 /*!< C_CAN1 IR2: INTPND32_17 Position */ -#define C_CAN1_IR2_INTPND32_17_Msk (0x0000ffffUL << C_CAN1_IR2_INTPND32_17_Pos) /*!< C_CAN1 IR2: INTPND32_17 Mask */ - -// -------------------------------------- C_CAN1_MSGV1 ------------------------------------------ -#define C_CAN1_MSGV1_MSGVAL16_1_Pos 0 /*!< C_CAN1 MSGV1: MSGVAL16_1 Position */ -#define C_CAN1_MSGV1_MSGVAL16_1_Msk (0x0000ffffUL << C_CAN1_MSGV1_MSGVAL16_1_Pos) /*!< C_CAN1 MSGV1: MSGVAL16_1 Mask */ - -// -------------------------------------- C_CAN1_MSGV2 ------------------------------------------ -#define C_CAN1_MSGV2_MSGVAL32_17_Pos 0 /*!< C_CAN1 MSGV2: MSGVAL32_17 Position */ -#define C_CAN1_MSGV2_MSGVAL32_17_Msk (0x0000ffffUL << C_CAN1_MSGV2_MSGVAL32_17_Pos) /*!< C_CAN1 MSGV2: MSGVAL32_17 Mask */ - -// -------------------------------------- C_CAN1_CLKDIV ----------------------------------------- -#define C_CAN1_CLKDIV_CLKDIVVAL_Pos 0 /*!< C_CAN1 CLKDIV: CLKDIVVAL Position */ -#define C_CAN1_CLKDIV_CLKDIVVAL_Msk (0x0fUL << C_CAN1_CLKDIV_CLKDIVVAL_Pos) /*!< C_CAN1 CLKDIV: CLKDIVVAL Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- RITIMER Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ------------------------------------- RITIMER_COMPVAL ---------------------------------------- -#define RITIMER_COMPVAL_RICOMP_Pos 0 /*!< RITIMER COMPVAL: RICOMP Position */ -#define RITIMER_COMPVAL_RICOMP_Msk (0xffffffffUL << RITIMER_COMPVAL_RICOMP_Pos) /*!< RITIMER COMPVAL: RICOMP Mask */ - -// -------------------------------------- RITIMER_MASK ------------------------------------------ -#define RITIMER_MASK_RIMASK_Pos 0 /*!< RITIMER MASK: RIMASK Position */ -#define RITIMER_MASK_RIMASK_Msk (0xffffffffUL << RITIMER_MASK_RIMASK_Pos) /*!< RITIMER MASK: RIMASK Mask */ - -// -------------------------------------- RITIMER_CTRL ------------------------------------------ -#define RITIMER_CTRL_RITINT_Pos 0 /*!< RITIMER CTRL: RITINT Position */ -#define RITIMER_CTRL_RITINT_Msk (0x01UL << RITIMER_CTRL_RITINT_Pos) /*!< RITIMER CTRL: RITINT Mask */ -#define RITIMER_CTRL_RITENCLR_Pos 1 /*!< RITIMER CTRL: RITENCLR Position */ -#define RITIMER_CTRL_RITENCLR_Msk (0x01UL << RITIMER_CTRL_RITENCLR_Pos) /*!< RITIMER CTRL: RITENCLR Mask */ -#define RITIMER_CTRL_RITENBR_Pos 2 /*!< RITIMER CTRL: RITENBR Position */ -#define RITIMER_CTRL_RITENBR_Msk (0x01UL << RITIMER_CTRL_RITENBR_Pos) /*!< RITIMER CTRL: RITENBR Mask */ -#define RITIMER_CTRL_RITEN_Pos 3 /*!< RITIMER CTRL: RITEN Position */ -#define RITIMER_CTRL_RITEN_Msk (0x01UL << RITIMER_CTRL_RITEN_Pos) /*!< RITIMER CTRL: RITEN Mask */ - -// ------------------------------------- RITIMER_COUNTER ---------------------------------------- -#define RITIMER_COUNTER_RICOUNTER_Pos 0 /*!< RITIMER COUNTER: RICOUNTER Position */ -#define RITIMER_COUNTER_RICOUNTER_Msk (0xffffffffUL << RITIMER_COUNTER_RICOUNTER_Pos) /*!< RITIMER COUNTER: RICOUNTER Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- QEI Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ----------------------------------------- QEI_CON -------------------------------------------- -#define QEI_CON_RESP_Pos 0 /*!< QEI CON: RESP Position */ -#define QEI_CON_RESP_Msk (0x01UL << QEI_CON_RESP_Pos) /*!< QEI CON: RESP Mask */ -#define QEI_CON_RESPI_Pos 1 /*!< QEI CON: RESPI Position */ -#define QEI_CON_RESPI_Msk (0x01UL << QEI_CON_RESPI_Pos) /*!< QEI CON: RESPI Mask */ -#define QEI_CON_RESV_Pos 2 /*!< QEI CON: RESV Position */ -#define QEI_CON_RESV_Msk (0x01UL << QEI_CON_RESV_Pos) /*!< QEI CON: RESV Mask */ -#define QEI_CON_RESI_Pos 3 /*!< QEI CON: RESI Position */ -#define QEI_CON_RESI_Msk (0x01UL << QEI_CON_RESI_Pos) /*!< QEI CON: RESI Mask */ - -// ---------------------------------------- QEI_STAT -------------------------------------------- -#define QEI_STAT_DIR_Pos 0 /*!< QEI STAT: DIR Position */ -#define QEI_STAT_DIR_Msk (0x01UL << QEI_STAT_DIR_Pos) /*!< QEI STAT: DIR Mask */ - -// ---------------------------------------- QEI_CONF -------------------------------------------- -#define QEI_CONF_DIRINV_Pos 0 /*!< QEI CONF: DIRINV Position */ -#define QEI_CONF_DIRINV_Msk (0x01UL << QEI_CONF_DIRINV_Pos) /*!< QEI CONF: DIRINV Mask */ -#define QEI_CONF_SIGMODE_Pos 1 /*!< QEI CONF: SIGMODE Position */ -#define QEI_CONF_SIGMODE_Msk (0x01UL << QEI_CONF_SIGMODE_Pos) /*!< QEI CONF: SIGMODE Mask */ -#define QEI_CONF_CAPMODE_Pos 2 /*!< QEI CONF: CAPMODE Position */ -#define QEI_CONF_CAPMODE_Msk (0x01UL << QEI_CONF_CAPMODE_Pos) /*!< QEI CONF: CAPMODE Mask */ -#define QEI_CONF_INVINX_Pos 3 /*!< QEI CONF: INVINX Position */ -#define QEI_CONF_INVINX_Msk (0x01UL << QEI_CONF_INVINX_Pos) /*!< QEI CONF: INVINX Mask */ -#define QEI_CONF_CRESPI_Pos 4 /*!< QEI CONF: CRESPI Position */ -#define QEI_CONF_CRESPI_Msk (0x01UL << QEI_CONF_CRESPI_Pos) /*!< QEI CONF: CRESPI Mask */ -#define QEI_CONF_INXGATE_Pos 16 /*!< QEI CONF: INXGATE Position */ -#define QEI_CONF_INXGATE_Msk (0x0fUL << QEI_CONF_INXGATE_Pos) /*!< QEI CONF: INXGATE Mask */ - -// ----------------------------------------- QEI_POS -------------------------------------------- -#define QEI_POS_POS_Pos 0 /*!< QEI POS: POS Position */ -#define QEI_POS_POS_Msk (0xffffffffUL << QEI_POS_POS_Pos) /*!< QEI POS: POS Mask */ - -// --------------------------------------- QEI_MAXPOS ------------------------------------------- -#define QEI_MAXPOS_MAXPOS_Pos 0 /*!< QEI MAXPOS: MAXPOS Position */ -#define QEI_MAXPOS_MAXPOS_Msk (0xffffffffUL << QEI_MAXPOS_MAXPOS_Pos) /*!< QEI MAXPOS: MAXPOS Mask */ - -// --------------------------------------- QEI_CMPOS0 ------------------------------------------- -#define QEI_CMPOS0_PCMP0_Pos 0 /*!< QEI CMPOS0: PCMP0 Position */ -#define QEI_CMPOS0_PCMP0_Msk (0xffffffffUL << QEI_CMPOS0_PCMP0_Pos) /*!< QEI CMPOS0: PCMP0 Mask */ - -// --------------------------------------- QEI_CMPOS1 ------------------------------------------- -#define QEI_CMPOS1_PCMP1_Pos 0 /*!< QEI CMPOS1: PCMP1 Position */ -#define QEI_CMPOS1_PCMP1_Msk (0xffffffffUL << QEI_CMPOS1_PCMP1_Pos) /*!< QEI CMPOS1: PCMP1 Mask */ - -// --------------------------------------- QEI_CMPOS2 ------------------------------------------- -#define QEI_CMPOS2_PCMP2_Pos 0 /*!< QEI CMPOS2: PCMP2 Position */ -#define QEI_CMPOS2_PCMP2_Msk (0xffffffffUL << QEI_CMPOS2_PCMP2_Pos) /*!< QEI CMPOS2: PCMP2 Mask */ - -// --------------------------------------- QEI_INXCNT ------------------------------------------- -#define QEI_INXCNT_ENCPOS_Pos 0 /*!< QEI INXCNT: ENCPOS Position */ -#define QEI_INXCNT_ENCPOS_Msk (0xffffffffUL << QEI_INXCNT_ENCPOS_Pos) /*!< QEI INXCNT: ENCPOS Mask */ - -// --------------------------------------- QEI_INXCMP0 ------------------------------------------ -#define QEI_INXCMP0_ICMP0_Pos 0 /*!< QEI INXCMP0: ICMP0 Position */ -#define QEI_INXCMP0_ICMP0_Msk (0xffffffffUL << QEI_INXCMP0_ICMP0_Pos) /*!< QEI INXCMP0: ICMP0 Mask */ - -// ---------------------------------------- QEI_LOAD -------------------------------------------- -#define QEI_LOAD_VELLOAD_Pos 0 /*!< QEI LOAD: VELLOAD Position */ -#define QEI_LOAD_VELLOAD_Msk (0xffffffffUL << QEI_LOAD_VELLOAD_Pos) /*!< QEI LOAD: VELLOAD Mask */ - -// ---------------------------------------- QEI_TIME -------------------------------------------- -#define QEI_TIME_VELVAL_Pos 0 /*!< QEI TIME: VELVAL Position */ -#define QEI_TIME_VELVAL_Msk (0xffffffffUL << QEI_TIME_VELVAL_Pos) /*!< QEI TIME: VELVAL Mask */ - -// ----------------------------------------- QEI_VEL -------------------------------------------- -#define QEI_VEL_VELPC_Pos 0 /*!< QEI VEL: VELPC Position */ -#define QEI_VEL_VELPC_Msk (0xffffffffUL << QEI_VEL_VELPC_Pos) /*!< QEI VEL: VELPC Mask */ - -// ----------------------------------------- QEI_CAP -------------------------------------------- -#define QEI_CAP_VELCAP_Pos 0 /*!< QEI CAP: VELCAP Position */ -#define QEI_CAP_VELCAP_Msk (0xffffffffUL << QEI_CAP_VELCAP_Pos) /*!< QEI CAP: VELCAP Mask */ - -// --------------------------------------- QEI_VELCOMP ------------------------------------------ -#define QEI_VELCOMP_VELCMP_Pos 0 /*!< QEI VELCOMP: VELCMP Position */ -#define QEI_VELCOMP_VELCMP_Msk (0xffffffffUL << QEI_VELCOMP_VELCMP_Pos) /*!< QEI VELCOMP: VELCMP Mask */ - -// -------------------------------------- QEI_FILTERPHA ----------------------------------------- -#define QEI_FILTERPHA_FILTA_Pos 0 /*!< QEI FILTERPHA: FILTA Position */ -#define QEI_FILTERPHA_FILTA_Msk (0xffffffffUL << QEI_FILTERPHA_FILTA_Pos) /*!< QEI FILTERPHA: FILTA Mask */ - -// -------------------------------------- QEI_FILTERPHB ----------------------------------------- -#define QEI_FILTERPHB_FILTB_Pos 0 /*!< QEI FILTERPHB: FILTB Position */ -#define QEI_FILTERPHB_FILTB_Msk (0xffffffffUL << QEI_FILTERPHB_FILTB_Pos) /*!< QEI FILTERPHB: FILTB Mask */ - -// -------------------------------------- QEI_FILTERINX ----------------------------------------- -#define QEI_FILTERINX_FITLINX_Pos 0 /*!< QEI FILTERINX: FITLINX Position */ -#define QEI_FILTERINX_FITLINX_Msk (0xffffffffUL << QEI_FILTERINX_FITLINX_Pos) /*!< QEI FILTERINX: FITLINX Mask */ - -// --------------------------------------- QEI_WINDOW ------------------------------------------- -#define QEI_WINDOW_WINDOW_Pos 0 /*!< QEI WINDOW: WINDOW Position */ -#define QEI_WINDOW_WINDOW_Msk (0xffffffffUL << QEI_WINDOW_WINDOW_Pos) /*!< QEI WINDOW: WINDOW Mask */ - -// --------------------------------------- QEI_INXCMP1 ------------------------------------------ -#define QEI_INXCMP1_ICMP1_Pos 0 /*!< QEI INXCMP1: ICMP1 Position */ -#define QEI_INXCMP1_ICMP1_Msk (0xffffffffUL << QEI_INXCMP1_ICMP1_Pos) /*!< QEI INXCMP1: ICMP1 Mask */ - -// --------------------------------------- QEI_INXCMP2 ------------------------------------------ -#define QEI_INXCMP2_ICMP2_Pos 0 /*!< QEI INXCMP2: ICMP2 Position */ -#define QEI_INXCMP2_ICMP2_Msk (0xffffffffUL << QEI_INXCMP2_ICMP2_Pos) /*!< QEI INXCMP2: ICMP2 Mask */ - -// ----------------------------------------- QEI_IEC -------------------------------------------- -#define QEI_IEC_INX_EN_Pos 0 /*!< QEI IEC: INX_EN Position */ -#define QEI_IEC_INX_EN_Msk (0x01UL << QEI_IEC_INX_EN_Pos) /*!< QEI IEC: INX_EN Mask */ -#define QEI_IEC_TIM_EN_Pos 1 /*!< QEI IEC: TIM_EN Position */ -#define QEI_IEC_TIM_EN_Msk (0x01UL << QEI_IEC_TIM_EN_Pos) /*!< QEI IEC: TIM_EN Mask */ -#define QEI_IEC_VELC_EN_Pos 2 /*!< QEI IEC: VELC_EN Position */ -#define QEI_IEC_VELC_EN_Msk (0x01UL << QEI_IEC_VELC_EN_Pos) /*!< QEI IEC: VELC_EN Mask */ -#define QEI_IEC_DIR_EN_Pos 3 /*!< QEI IEC: DIR_EN Position */ -#define QEI_IEC_DIR_EN_Msk (0x01UL << QEI_IEC_DIR_EN_Pos) /*!< QEI IEC: DIR_EN Mask */ -#define QEI_IEC_ERR_EN_Pos 4 /*!< QEI IEC: ERR_EN Position */ -#define QEI_IEC_ERR_EN_Msk (0x01UL << QEI_IEC_ERR_EN_Pos) /*!< QEI IEC: ERR_EN Mask */ -#define QEI_IEC_ENCLK_EN_Pos 5 /*!< QEI IEC: ENCLK_EN Position */ -#define QEI_IEC_ENCLK_EN_Msk (0x01UL << QEI_IEC_ENCLK_EN_Pos) /*!< QEI IEC: ENCLK_EN Mask */ -#define QEI_IEC_POS0_Int_Pos 6 /*!< QEI IEC: POS0_Int Position */ -#define QEI_IEC_POS0_Int_Msk (0x01UL << QEI_IEC_POS0_Int_Pos) /*!< QEI IEC: POS0_Int Mask */ -#define QEI_IEC_POS1_Int_Pos 7 /*!< QEI IEC: POS1_Int Position */ -#define QEI_IEC_POS1_Int_Msk (0x01UL << QEI_IEC_POS1_Int_Pos) /*!< QEI IEC: POS1_Int Mask */ -#define QEI_IEC_POS2_Int_Pos 8 /*!< QEI IEC: POS2_Int Position */ -#define QEI_IEC_POS2_Int_Msk (0x01UL << QEI_IEC_POS2_Int_Pos) /*!< QEI IEC: POS2_Int Mask */ -#define QEI_IEC_REV_Int_Pos 9 /*!< QEI IEC: REV_Int Position */ -#define QEI_IEC_REV_Int_Msk (0x01UL << QEI_IEC_REV_Int_Pos) /*!< QEI IEC: REV_Int Mask */ -#define QEI_IEC_POS0REV_Int_Pos 10 /*!< QEI IEC: POS0REV_Int Position */ -#define QEI_IEC_POS0REV_Int_Msk (0x01UL << QEI_IEC_POS0REV_Int_Pos) /*!< QEI IEC: POS0REV_Int Mask */ -#define QEI_IEC_POS1REV_Int_Pos 11 /*!< QEI IEC: POS1REV_Int Position */ -#define QEI_IEC_POS1REV_Int_Msk (0x01UL << QEI_IEC_POS1REV_Int_Pos) /*!< QEI IEC: POS1REV_Int Mask */ -#define QEI_IEC_POS2REV_Int_Pos 12 /*!< QEI IEC: POS2REV_Int Position */ -#define QEI_IEC_POS2REV_Int_Msk (0x01UL << QEI_IEC_POS2REV_Int_Pos) /*!< QEI IEC: POS2REV_Int Mask */ -#define QEI_IEC_REV1_Int_Pos 13 /*!< QEI IEC: REV1_Int Position */ -#define QEI_IEC_REV1_Int_Msk (0x01UL << QEI_IEC_REV1_Int_Pos) /*!< QEI IEC: REV1_Int Mask */ -#define QEI_IEC_REV2_Int_Pos 14 /*!< QEI IEC: REV2_Int Position */ -#define QEI_IEC_REV2_Int_Msk (0x01UL << QEI_IEC_REV2_Int_Pos) /*!< QEI IEC: REV2_Int Mask */ -#define QEI_IEC_MAXPOS_Int_Pos 15 /*!< QEI IEC: MAXPOS_Int Position */ -#define QEI_IEC_MAXPOS_Int_Msk (0x01UL << QEI_IEC_MAXPOS_Int_Pos) /*!< QEI IEC: MAXPOS_Int Mask */ - -// ----------------------------------------- QEI_IES -------------------------------------------- -#define QEI_IES_INX_EN_Pos 0 /*!< QEI IES: INX_EN Position */ -#define QEI_IES_INX_EN_Msk (0x01UL << QEI_IES_INX_EN_Pos) /*!< QEI IES: INX_EN Mask */ -#define QEI_IES_TIM_EN_Pos 1 /*!< QEI IES: TIM_EN Position */ -#define QEI_IES_TIM_EN_Msk (0x01UL << QEI_IES_TIM_EN_Pos) /*!< QEI IES: TIM_EN Mask */ -#define QEI_IES_VELC_EN_Pos 2 /*!< QEI IES: VELC_EN Position */ -#define QEI_IES_VELC_EN_Msk (0x01UL << QEI_IES_VELC_EN_Pos) /*!< QEI IES: VELC_EN Mask */ -#define QEI_IES_DIR_EN_Pos 3 /*!< QEI IES: DIR_EN Position */ -#define QEI_IES_DIR_EN_Msk (0x01UL << QEI_IES_DIR_EN_Pos) /*!< QEI IES: DIR_EN Mask */ -#define QEI_IES_ERR_EN_Pos 4 /*!< QEI IES: ERR_EN Position */ -#define QEI_IES_ERR_EN_Msk (0x01UL << QEI_IES_ERR_EN_Pos) /*!< QEI IES: ERR_EN Mask */ -#define QEI_IES_ENCLK_EN_Pos 5 /*!< QEI IES: ENCLK_EN Position */ -#define QEI_IES_ENCLK_EN_Msk (0x01UL << QEI_IES_ENCLK_EN_Pos) /*!< QEI IES: ENCLK_EN Mask */ -#define QEI_IES_POS0_Int_Pos 6 /*!< QEI IES: POS0_Int Position */ -#define QEI_IES_POS0_Int_Msk (0x01UL << QEI_IES_POS0_Int_Pos) /*!< QEI IES: POS0_Int Mask */ -#define QEI_IES_POS1_Int_Pos 7 /*!< QEI IES: POS1_Int Position */ -#define QEI_IES_POS1_Int_Msk (0x01UL << QEI_IES_POS1_Int_Pos) /*!< QEI IES: POS1_Int Mask */ -#define QEI_IES_POS2_Int_Pos 8 /*!< QEI IES: POS2_Int Position */ -#define QEI_IES_POS2_Int_Msk (0x01UL << QEI_IES_POS2_Int_Pos) /*!< QEI IES: POS2_Int Mask */ -#define QEI_IES_REV_Int_Pos 9 /*!< QEI IES: REV_Int Position */ -#define QEI_IES_REV_Int_Msk (0x01UL << QEI_IES_REV_Int_Pos) /*!< QEI IES: REV_Int Mask */ -#define QEI_IES_POS0REV_Int_Pos 10 /*!< QEI IES: POS0REV_Int Position */ -#define QEI_IES_POS0REV_Int_Msk (0x01UL << QEI_IES_POS0REV_Int_Pos) /*!< QEI IES: POS0REV_Int Mask */ -#define QEI_IES_POS1REV_Int_Pos 11 /*!< QEI IES: POS1REV_Int Position */ -#define QEI_IES_POS1REV_Int_Msk (0x01UL << QEI_IES_POS1REV_Int_Pos) /*!< QEI IES: POS1REV_Int Mask */ -#define QEI_IES_POS2REV_Int_Pos 12 /*!< QEI IES: POS2REV_Int Position */ -#define QEI_IES_POS2REV_Int_Msk (0x01UL << QEI_IES_POS2REV_Int_Pos) /*!< QEI IES: POS2REV_Int Mask */ -#define QEI_IES_REV1_Int_Pos 13 /*!< QEI IES: REV1_Int Position */ -#define QEI_IES_REV1_Int_Msk (0x01UL << QEI_IES_REV1_Int_Pos) /*!< QEI IES: REV1_Int Mask */ -#define QEI_IES_REV2_Int_Pos 14 /*!< QEI IES: REV2_Int Position */ -#define QEI_IES_REV2_Int_Msk (0x01UL << QEI_IES_REV2_Int_Pos) /*!< QEI IES: REV2_Int Mask */ -#define QEI_IES_MAXPOS_Int_Pos 15 /*!< QEI IES: MAXPOS_Int Position */ -#define QEI_IES_MAXPOS_Int_Msk (0x01UL << QEI_IES_MAXPOS_Int_Pos) /*!< QEI IES: MAXPOS_Int Mask */ - -// --------------------------------------- QEI_INTSTAT ------------------------------------------ -#define QEI_INTSTAT_INX_Int_Pos 0 /*!< QEI INTSTAT: INX_Int Position */ -#define QEI_INTSTAT_INX_Int_Msk (0x01UL << QEI_INTSTAT_INX_Int_Pos) /*!< QEI INTSTAT: INX_Int Mask */ -#define QEI_INTSTAT_TIM_Int_Pos 1 /*!< QEI INTSTAT: TIM_Int Position */ -#define QEI_INTSTAT_TIM_Int_Msk (0x01UL << QEI_INTSTAT_TIM_Int_Pos) /*!< QEI INTSTAT: TIM_Int Mask */ -#define QEI_INTSTAT_VELC_Int_Pos 2 /*!< QEI INTSTAT: VELC_Int Position */ -#define QEI_INTSTAT_VELC_Int_Msk (0x01UL << QEI_INTSTAT_VELC_Int_Pos) /*!< QEI INTSTAT: VELC_Int Mask */ -#define QEI_INTSTAT_DIR_Int_Pos 3 /*!< QEI INTSTAT: DIR_Int Position */ -#define QEI_INTSTAT_DIR_Int_Msk (0x01UL << QEI_INTSTAT_DIR_Int_Pos) /*!< QEI INTSTAT: DIR_Int Mask */ -#define QEI_INTSTAT_ERR_Int_Pos 4 /*!< QEI INTSTAT: ERR_Int Position */ -#define QEI_INTSTAT_ERR_Int_Msk (0x01UL << QEI_INTSTAT_ERR_Int_Pos) /*!< QEI INTSTAT: ERR_Int Mask */ -#define QEI_INTSTAT_ENCLK_Int_Pos 5 /*!< QEI INTSTAT: ENCLK_Int Position */ -#define QEI_INTSTAT_ENCLK_Int_Msk (0x01UL << QEI_INTSTAT_ENCLK_Int_Pos) /*!< QEI INTSTAT: ENCLK_Int Mask */ -#define QEI_INTSTAT_POS0_Int_Pos 6 /*!< QEI INTSTAT: POS0_Int Position */ -#define QEI_INTSTAT_POS0_Int_Msk (0x01UL << QEI_INTSTAT_POS0_Int_Pos) /*!< QEI INTSTAT: POS0_Int Mask */ -#define QEI_INTSTAT_POS1_Int_Pos 7 /*!< QEI INTSTAT: POS1_Int Position */ -#define QEI_INTSTAT_POS1_Int_Msk (0x01UL << QEI_INTSTAT_POS1_Int_Pos) /*!< QEI INTSTAT: POS1_Int Mask */ -#define QEI_INTSTAT_POS2_Int_Pos 8 /*!< QEI INTSTAT: POS2_Int Position */ -#define QEI_INTSTAT_POS2_Int_Msk (0x01UL << QEI_INTSTAT_POS2_Int_Pos) /*!< QEI INTSTAT: POS2_Int Mask */ -#define QEI_INTSTAT_REV_Int_Pos 9 /*!< QEI INTSTAT: REV_Int Position */ -#define QEI_INTSTAT_REV_Int_Msk (0x01UL << QEI_INTSTAT_REV_Int_Pos) /*!< QEI INTSTAT: REV_Int Mask */ -#define QEI_INTSTAT_POS0REV_Int_Pos 10 /*!< QEI INTSTAT: POS0REV_Int Position */ -#define QEI_INTSTAT_POS0REV_Int_Msk (0x01UL << QEI_INTSTAT_POS0REV_Int_Pos) /*!< QEI INTSTAT: POS0REV_Int Mask */ -#define QEI_INTSTAT_POS1REV_Int_Pos 11 /*!< QEI INTSTAT: POS1REV_Int Position */ -#define QEI_INTSTAT_POS1REV_Int_Msk (0x01UL << QEI_INTSTAT_POS1REV_Int_Pos) /*!< QEI INTSTAT: POS1REV_Int Mask */ -#define QEI_INTSTAT_POS2REV_Int_Pos 12 /*!< QEI INTSTAT: POS2REV_Int Position */ -#define QEI_INTSTAT_POS2REV_Int_Msk (0x01UL << QEI_INTSTAT_POS2REV_Int_Pos) /*!< QEI INTSTAT: POS2REV_Int Mask */ -#define QEI_INTSTAT_REV1_Int_Pos 13 /*!< QEI INTSTAT: REV1_Int Position */ -#define QEI_INTSTAT_REV1_Int_Msk (0x01UL << QEI_INTSTAT_REV1_Int_Pos) /*!< QEI INTSTAT: REV1_Int Mask */ -#define QEI_INTSTAT_REV2_Int_Pos 14 /*!< QEI INTSTAT: REV2_Int Position */ -#define QEI_INTSTAT_REV2_Int_Msk (0x01UL << QEI_INTSTAT_REV2_Int_Pos) /*!< QEI INTSTAT: REV2_Int Mask */ -#define QEI_INTSTAT_MAXPOS_Int_Pos 15 /*!< QEI INTSTAT: MAXPOS_Int Position */ -#define QEI_INTSTAT_MAXPOS_Int_Msk (0x01UL << QEI_INTSTAT_MAXPOS_Int_Pos) /*!< QEI INTSTAT: MAXPOS_Int Mask */ - -// ----------------------------------------- QEI_IE --------------------------------------------- -#define QEI_IE_INX_Int_Pos 0 /*!< QEI IE: INX_Int Position */ -#define QEI_IE_INX_Int_Msk (0x01UL << QEI_IE_INX_Int_Pos) /*!< QEI IE: INX_Int Mask */ -#define QEI_IE_TIM_Int_Pos 1 /*!< QEI IE: TIM_Int Position */ -#define QEI_IE_TIM_Int_Msk (0x01UL << QEI_IE_TIM_Int_Pos) /*!< QEI IE: TIM_Int Mask */ -#define QEI_IE_VELC_Int_Pos 2 /*!< QEI IE: VELC_Int Position */ -#define QEI_IE_VELC_Int_Msk (0x01UL << QEI_IE_VELC_Int_Pos) /*!< QEI IE: VELC_Int Mask */ -#define QEI_IE_DIR_Int_Pos 3 /*!< QEI IE: DIR_Int Position */ -#define QEI_IE_DIR_Int_Msk (0x01UL << QEI_IE_DIR_Int_Pos) /*!< QEI IE: DIR_Int Mask */ -#define QEI_IE_ERR_Int_Pos 4 /*!< QEI IE: ERR_Int Position */ -#define QEI_IE_ERR_Int_Msk (0x01UL << QEI_IE_ERR_Int_Pos) /*!< QEI IE: ERR_Int Mask */ -#define QEI_IE_ENCLK_Int_Pos 5 /*!< QEI IE: ENCLK_Int Position */ -#define QEI_IE_ENCLK_Int_Msk (0x01UL << QEI_IE_ENCLK_Int_Pos) /*!< QEI IE: ENCLK_Int Mask */ -#define QEI_IE_POS0_Int_Pos 6 /*!< QEI IE: POS0_Int Position */ -#define QEI_IE_POS0_Int_Msk (0x01UL << QEI_IE_POS0_Int_Pos) /*!< QEI IE: POS0_Int Mask */ -#define QEI_IE_POS1_Int_Pos 7 /*!< QEI IE: POS1_Int Position */ -#define QEI_IE_POS1_Int_Msk (0x01UL << QEI_IE_POS1_Int_Pos) /*!< QEI IE: POS1_Int Mask */ -#define QEI_IE_POS2_Int_Pos 8 /*!< QEI IE: POS2_Int Position */ -#define QEI_IE_POS2_Int_Msk (0x01UL << QEI_IE_POS2_Int_Pos) /*!< QEI IE: POS2_Int Mask */ -#define QEI_IE_REV_Int_Pos 9 /*!< QEI IE: REV_Int Position */ -#define QEI_IE_REV_Int_Msk (0x01UL << QEI_IE_REV_Int_Pos) /*!< QEI IE: REV_Int Mask */ -#define QEI_IE_POS0REV_Int_Pos 10 /*!< QEI IE: POS0REV_Int Position */ -#define QEI_IE_POS0REV_Int_Msk (0x01UL << QEI_IE_POS0REV_Int_Pos) /*!< QEI IE: POS0REV_Int Mask */ -#define QEI_IE_POS1REV_Int_Pos 11 /*!< QEI IE: POS1REV_Int Position */ -#define QEI_IE_POS1REV_Int_Msk (0x01UL << QEI_IE_POS1REV_Int_Pos) /*!< QEI IE: POS1REV_Int Mask */ -#define QEI_IE_POS2REV_Int_Pos 12 /*!< QEI IE: POS2REV_Int Position */ -#define QEI_IE_POS2REV_Int_Msk (0x01UL << QEI_IE_POS2REV_Int_Pos) /*!< QEI IE: POS2REV_Int Mask */ -#define QEI_IE_REV1_Int_Pos 13 /*!< QEI IE: REV1_Int Position */ -#define QEI_IE_REV1_Int_Msk (0x01UL << QEI_IE_REV1_Int_Pos) /*!< QEI IE: REV1_Int Mask */ -#define QEI_IE_REV2_Int_Pos 14 /*!< QEI IE: REV2_Int Position */ -#define QEI_IE_REV2_Int_Msk (0x01UL << QEI_IE_REV2_Int_Pos) /*!< QEI IE: REV2_Int Mask */ -#define QEI_IE_MAXPOS_Int_Pos 15 /*!< QEI IE: MAXPOS_Int Position */ -#define QEI_IE_MAXPOS_Int_Msk (0x01UL << QEI_IE_MAXPOS_Int_Pos) /*!< QEI IE: MAXPOS_Int Mask */ - -// ----------------------------------------- QEI_CLR -------------------------------------------- -#define QEI_CLR_INX_Int_Pos 0 /*!< QEI CLR: INX_Int Position */ -#define QEI_CLR_INX_Int_Msk (0x01UL << QEI_CLR_INX_Int_Pos) /*!< QEI CLR: INX_Int Mask */ -#define QEI_CLR_TIM_Int_Pos 1 /*!< QEI CLR: TIM_Int Position */ -#define QEI_CLR_TIM_Int_Msk (0x01UL << QEI_CLR_TIM_Int_Pos) /*!< QEI CLR: TIM_Int Mask */ -#define QEI_CLR_VELC_Int_Pos 2 /*!< QEI CLR: VELC_Int Position */ -#define QEI_CLR_VELC_Int_Msk (0x01UL << QEI_CLR_VELC_Int_Pos) /*!< QEI CLR: VELC_Int Mask */ -#define QEI_CLR_DIR_Int_Pos 3 /*!< QEI CLR: DIR_Int Position */ -#define QEI_CLR_DIR_Int_Msk (0x01UL << QEI_CLR_DIR_Int_Pos) /*!< QEI CLR: DIR_Int Mask */ -#define QEI_CLR_ERR_Int_Pos 4 /*!< QEI CLR: ERR_Int Position */ -#define QEI_CLR_ERR_Int_Msk (0x01UL << QEI_CLR_ERR_Int_Pos) /*!< QEI CLR: ERR_Int Mask */ -#define QEI_CLR_ENCLK_Int_Pos 5 /*!< QEI CLR: ENCLK_Int Position */ -#define QEI_CLR_ENCLK_Int_Msk (0x01UL << QEI_CLR_ENCLK_Int_Pos) /*!< QEI CLR: ENCLK_Int Mask */ -#define QEI_CLR_POS0_Int_Pos 6 /*!< QEI CLR: POS0_Int Position */ -#define QEI_CLR_POS0_Int_Msk (0x01UL << QEI_CLR_POS0_Int_Pos) /*!< QEI CLR: POS0_Int Mask */ -#define QEI_CLR_POS1_Int_Pos 7 /*!< QEI CLR: POS1_Int Position */ -#define QEI_CLR_POS1_Int_Msk (0x01UL << QEI_CLR_POS1_Int_Pos) /*!< QEI CLR: POS1_Int Mask */ -#define QEI_CLR_POS2_Int_Pos 8 /*!< QEI CLR: POS2_Int Position */ -#define QEI_CLR_POS2_Int_Msk (0x01UL << QEI_CLR_POS2_Int_Pos) /*!< QEI CLR: POS2_Int Mask */ -#define QEI_CLR_REV_Int_Pos 9 /*!< QEI CLR: REV_Int Position */ -#define QEI_CLR_REV_Int_Msk (0x01UL << QEI_CLR_REV_Int_Pos) /*!< QEI CLR: REV_Int Mask */ -#define QEI_CLR_POS0REV_Int_Pos 10 /*!< QEI CLR: POS0REV_Int Position */ -#define QEI_CLR_POS0REV_Int_Msk (0x01UL << QEI_CLR_POS0REV_Int_Pos) /*!< QEI CLR: POS0REV_Int Mask */ -#define QEI_CLR_POS1REV_Int_Pos 11 /*!< QEI CLR: POS1REV_Int Position */ -#define QEI_CLR_POS1REV_Int_Msk (0x01UL << QEI_CLR_POS1REV_Int_Pos) /*!< QEI CLR: POS1REV_Int Mask */ -#define QEI_CLR_REV1_Int_Pos 13 /*!< QEI CLR: REV1_Int Position */ -#define QEI_CLR_REV1_Int_Msk (0x01UL << QEI_CLR_REV1_Int_Pos) /*!< QEI CLR: REV1_Int Mask */ -#define QEI_CLR_REV2_Int_Pos 14 /*!< QEI CLR: REV2_Int Position */ -#define QEI_CLR_REV2_Int_Msk (0x01UL << QEI_CLR_REV2_Int_Pos) /*!< QEI CLR: REV2_Int Mask */ -#define QEI_CLR_MAXPOS_Int_Pos 15 /*!< QEI CLR: MAXPOS_Int Position */ -#define QEI_CLR_MAXPOS_Int_Msk (0x01UL << QEI_CLR_MAXPOS_Int_Pos) /*!< QEI CLR: MAXPOS_Int Mask */ - -// ----------------------------------------- QEI_SET -------------------------------------------- -#define QEI_SET_INX_Int_Pos 0 /*!< QEI SET: INX_Int Position */ -#define QEI_SET_INX_Int_Msk (0x01UL << QEI_SET_INX_Int_Pos) /*!< QEI SET: INX_Int Mask */ -#define QEI_SET_TIM_Int_Pos 1 /*!< QEI SET: TIM_Int Position */ -#define QEI_SET_TIM_Int_Msk (0x01UL << QEI_SET_TIM_Int_Pos) /*!< QEI SET: TIM_Int Mask */ -#define QEI_SET_VELC_Int_Pos 2 /*!< QEI SET: VELC_Int Position */ -#define QEI_SET_VELC_Int_Msk (0x01UL << QEI_SET_VELC_Int_Pos) /*!< QEI SET: VELC_Int Mask */ -#define QEI_SET_DIR_Int_Pos 3 /*!< QEI SET: DIR_Int Position */ -#define QEI_SET_DIR_Int_Msk (0x01UL << QEI_SET_DIR_Int_Pos) /*!< QEI SET: DIR_Int Mask */ -#define QEI_SET_ERR_Int_Pos 4 /*!< QEI SET: ERR_Int Position */ -#define QEI_SET_ERR_Int_Msk (0x01UL << QEI_SET_ERR_Int_Pos) /*!< QEI SET: ERR_Int Mask */ -#define QEI_SET_ENCLK_Int_Pos 5 /*!< QEI SET: ENCLK_Int Position */ -#define QEI_SET_ENCLK_Int_Msk (0x01UL << QEI_SET_ENCLK_Int_Pos) /*!< QEI SET: ENCLK_Int Mask */ -#define QEI_SET_POS0_Int_Pos 6 /*!< QEI SET: POS0_Int Position */ -#define QEI_SET_POS0_Int_Msk (0x01UL << QEI_SET_POS0_Int_Pos) /*!< QEI SET: POS0_Int Mask */ -#define QEI_SET_POS1_Int_Pos 7 /*!< QEI SET: POS1_Int Position */ -#define QEI_SET_POS1_Int_Msk (0x01UL << QEI_SET_POS1_Int_Pos) /*!< QEI SET: POS1_Int Mask */ -#define QEI_SET_POS2_Int_Pos 8 /*!< QEI SET: POS2_Int Position */ -#define QEI_SET_POS2_Int_Msk (0x01UL << QEI_SET_POS2_Int_Pos) /*!< QEI SET: POS2_Int Mask */ -#define QEI_SET_REV_Int_Pos 9 /*!< QEI SET: REV_Int Position */ -#define QEI_SET_REV_Int_Msk (0x01UL << QEI_SET_REV_Int_Pos) /*!< QEI SET: REV_Int Mask */ -#define QEI_SET_POS0REV_Int_Pos 10 /*!< QEI SET: POS0REV_Int Position */ -#define QEI_SET_POS0REV_Int_Msk (0x01UL << QEI_SET_POS0REV_Int_Pos) /*!< QEI SET: POS0REV_Int Mask */ -#define QEI_SET_POS1REV_Int_Pos 11 /*!< QEI SET: POS1REV_Int Position */ -#define QEI_SET_POS1REV_Int_Msk (0x01UL << QEI_SET_POS1REV_Int_Pos) /*!< QEI SET: POS1REV_Int Mask */ -#define QEI_SET_POS2REV_Int_Pos 12 /*!< QEI SET: POS2REV_Int Position */ -#define QEI_SET_POS2REV_Int_Msk (0x01UL << QEI_SET_POS2REV_Int_Pos) /*!< QEI SET: POS2REV_Int Mask */ -#define QEI_SET_REV1_Int_Pos 13 /*!< QEI SET: REV1_Int Position */ -#define QEI_SET_REV1_Int_Msk (0x01UL << QEI_SET_REV1_Int_Pos) /*!< QEI SET: REV1_Int Mask */ -#define QEI_SET_REV2_Int_Pos 14 /*!< QEI SET: REV2_Int Position */ -#define QEI_SET_REV2_Int_Msk (0x01UL << QEI_SET_REV2_Int_Pos) /*!< QEI SET: REV2_Int Mask */ -#define QEI_SET_MAXPOS_Int_Pos 15 /*!< QEI SET: MAXPOS_Int Position */ -#define QEI_SET_MAXPOS_Int_Msk (0x01UL << QEI_SET_MAXPOS_Int_Pos) /*!< QEI SET: MAXPOS_Int Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- GIMA Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ------------------------------------- GIMA_CAP0_0_IN ----------------------------------------- -#define GIMA_CAP0_0_IN_INV_Pos 0 /*!< GIMA CAP0_0_IN: INV Position */ -#define GIMA_CAP0_0_IN_INV_Msk (0x01UL << GIMA_CAP0_0_IN_INV_Pos) /*!< GIMA CAP0_0_IN: INV Mask */ -#define GIMA_CAP0_0_IN_EDGE_Pos 1 /*!< GIMA CAP0_0_IN: EDGE Position */ -#define GIMA_CAP0_0_IN_EDGE_Msk (0x01UL << GIMA_CAP0_0_IN_EDGE_Pos) /*!< GIMA CAP0_0_IN: EDGE Mask */ -#define GIMA_CAP0_0_IN_SYNCH_Pos 2 /*!< GIMA CAP0_0_IN: SYNCH Position */ -#define GIMA_CAP0_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_0_IN_SYNCH_Pos) /*!< GIMA CAP0_0_IN: SYNCH Mask */ -#define GIMA_CAP0_0_IN_PULSE_Pos 3 /*!< GIMA CAP0_0_IN: PULSE Position */ -#define GIMA_CAP0_0_IN_PULSE_Msk (0x01UL << GIMA_CAP0_0_IN_PULSE_Pos) /*!< GIMA CAP0_0_IN: PULSE Mask */ -#define GIMA_CAP0_0_IN_SELECT_Pos 4 /*!< GIMA CAP0_0_IN: SELECT Position */ -#define GIMA_CAP0_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_0_IN_SELECT_Pos) /*!< GIMA CAP0_0_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP0_1_IN ----------------------------------------- -#define GIMA_CAP0_1_IN_INV_Pos 0 /*!< GIMA CAP0_1_IN: INV Position */ -#define GIMA_CAP0_1_IN_INV_Msk (0x01UL << GIMA_CAP0_1_IN_INV_Pos) /*!< GIMA CAP0_1_IN: INV Mask */ -#define GIMA_CAP0_1_IN_EDGE_Pos 1 /*!< GIMA CAP0_1_IN: EDGE Position */ -#define GIMA_CAP0_1_IN_EDGE_Msk (0x01UL << GIMA_CAP0_1_IN_EDGE_Pos) /*!< GIMA CAP0_1_IN: EDGE Mask */ -#define GIMA_CAP0_1_IN_SYNCH_Pos 2 /*!< GIMA CAP0_1_IN: SYNCH Position */ -#define GIMA_CAP0_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_1_IN_SYNCH_Pos) /*!< GIMA CAP0_1_IN: SYNCH Mask */ -#define GIMA_CAP0_1_IN_PULSE_Pos 3 /*!< GIMA CAP0_1_IN: PULSE Position */ -#define GIMA_CAP0_1_IN_PULSE_Msk (0x01UL << GIMA_CAP0_1_IN_PULSE_Pos) /*!< GIMA CAP0_1_IN: PULSE Mask */ -#define GIMA_CAP0_1_IN_SELECT_Pos 4 /*!< GIMA CAP0_1_IN: SELECT Position */ -#define GIMA_CAP0_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_1_IN_SELECT_Pos) /*!< GIMA CAP0_1_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP0_2_IN ----------------------------------------- -#define GIMA_CAP0_2_IN_INV_Pos 0 /*!< GIMA CAP0_2_IN: INV Position */ -#define GIMA_CAP0_2_IN_INV_Msk (0x01UL << GIMA_CAP0_2_IN_INV_Pos) /*!< GIMA CAP0_2_IN: INV Mask */ -#define GIMA_CAP0_2_IN_EDGE_Pos 1 /*!< GIMA CAP0_2_IN: EDGE Position */ -#define GIMA_CAP0_2_IN_EDGE_Msk (0x01UL << GIMA_CAP0_2_IN_EDGE_Pos) /*!< GIMA CAP0_2_IN: EDGE Mask */ -#define GIMA_CAP0_2_IN_SYNCH_Pos 2 /*!< GIMA CAP0_2_IN: SYNCH Position */ -#define GIMA_CAP0_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_2_IN_SYNCH_Pos) /*!< GIMA CAP0_2_IN: SYNCH Mask */ -#define GIMA_CAP0_2_IN_PULSE_Pos 3 /*!< GIMA CAP0_2_IN: PULSE Position */ -#define GIMA_CAP0_2_IN_PULSE_Msk (0x01UL << GIMA_CAP0_2_IN_PULSE_Pos) /*!< GIMA CAP0_2_IN: PULSE Mask */ -#define GIMA_CAP0_2_IN_SELECT_Pos 4 /*!< GIMA CAP0_2_IN: SELECT Position */ -#define GIMA_CAP0_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_2_IN_SELECT_Pos) /*!< GIMA CAP0_2_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP0_3_IN ----------------------------------------- -#define GIMA_CAP0_3_IN_INV_Pos 0 /*!< GIMA CAP0_3_IN: INV Position */ -#define GIMA_CAP0_3_IN_INV_Msk (0x01UL << GIMA_CAP0_3_IN_INV_Pos) /*!< GIMA CAP0_3_IN: INV Mask */ -#define GIMA_CAP0_3_IN_EDGE_Pos 1 /*!< GIMA CAP0_3_IN: EDGE Position */ -#define GIMA_CAP0_3_IN_EDGE_Msk (0x01UL << GIMA_CAP0_3_IN_EDGE_Pos) /*!< GIMA CAP0_3_IN: EDGE Mask */ -#define GIMA_CAP0_3_IN_SYNCH_Pos 2 /*!< GIMA CAP0_3_IN: SYNCH Position */ -#define GIMA_CAP0_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_3_IN_SYNCH_Pos) /*!< GIMA CAP0_3_IN: SYNCH Mask */ -#define GIMA_CAP0_3_IN_PULSE_Pos 3 /*!< GIMA CAP0_3_IN: PULSE Position */ -#define GIMA_CAP0_3_IN_PULSE_Msk (0x01UL << GIMA_CAP0_3_IN_PULSE_Pos) /*!< GIMA CAP0_3_IN: PULSE Mask */ -#define GIMA_CAP0_3_IN_SELECT_Pos 4 /*!< GIMA CAP0_3_IN: SELECT Position */ -#define GIMA_CAP0_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_3_IN_SELECT_Pos) /*!< GIMA CAP0_3_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP1_0_IN ----------------------------------------- -#define GIMA_CAP1_0_IN_INV_Pos 0 /*!< GIMA CAP1_0_IN: INV Position */ -#define GIMA_CAP1_0_IN_INV_Msk (0x01UL << GIMA_CAP1_0_IN_INV_Pos) /*!< GIMA CAP1_0_IN: INV Mask */ -#define GIMA_CAP1_0_IN_EDGE_Pos 1 /*!< GIMA CAP1_0_IN: EDGE Position */ -#define GIMA_CAP1_0_IN_EDGE_Msk (0x01UL << GIMA_CAP1_0_IN_EDGE_Pos) /*!< GIMA CAP1_0_IN: EDGE Mask */ -#define GIMA_CAP1_0_IN_SYNCH_Pos 2 /*!< GIMA CAP1_0_IN: SYNCH Position */ -#define GIMA_CAP1_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_0_IN_SYNCH_Pos) /*!< GIMA CAP1_0_IN: SYNCH Mask */ -#define GIMA_CAP1_0_IN_PULSE_Pos 3 /*!< GIMA CAP1_0_IN: PULSE Position */ -#define GIMA_CAP1_0_IN_PULSE_Msk (0x01UL << GIMA_CAP1_0_IN_PULSE_Pos) /*!< GIMA CAP1_0_IN: PULSE Mask */ -#define GIMA_CAP1_0_IN_SELECT_Pos 4 /*!< GIMA CAP1_0_IN: SELECT Position */ -#define GIMA_CAP1_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_0_IN_SELECT_Pos) /*!< GIMA CAP1_0_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP1_1_IN ----------------------------------------- -#define GIMA_CAP1_1_IN_INV_Pos 0 /*!< GIMA CAP1_1_IN: INV Position */ -#define GIMA_CAP1_1_IN_INV_Msk (0x01UL << GIMA_CAP1_1_IN_INV_Pos) /*!< GIMA CAP1_1_IN: INV Mask */ -#define GIMA_CAP1_1_IN_EDGE_Pos 1 /*!< GIMA CAP1_1_IN: EDGE Position */ -#define GIMA_CAP1_1_IN_EDGE_Msk (0x01UL << GIMA_CAP1_1_IN_EDGE_Pos) /*!< GIMA CAP1_1_IN: EDGE Mask */ -#define GIMA_CAP1_1_IN_SYNCH_Pos 2 /*!< GIMA CAP1_1_IN: SYNCH Position */ -#define GIMA_CAP1_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_1_IN_SYNCH_Pos) /*!< GIMA CAP1_1_IN: SYNCH Mask */ -#define GIMA_CAP1_1_IN_PULSE_Pos 3 /*!< GIMA CAP1_1_IN: PULSE Position */ -#define GIMA_CAP1_1_IN_PULSE_Msk (0x01UL << GIMA_CAP1_1_IN_PULSE_Pos) /*!< GIMA CAP1_1_IN: PULSE Mask */ -#define GIMA_CAP1_1_IN_SELECT_Pos 4 /*!< GIMA CAP1_1_IN: SELECT Position */ -#define GIMA_CAP1_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_1_IN_SELECT_Pos) /*!< GIMA CAP1_1_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP1_2_IN ----------------------------------------- -#define GIMA_CAP1_2_IN_INV_Pos 0 /*!< GIMA CAP1_2_IN: INV Position */ -#define GIMA_CAP1_2_IN_INV_Msk (0x01UL << GIMA_CAP1_2_IN_INV_Pos) /*!< GIMA CAP1_2_IN: INV Mask */ -#define GIMA_CAP1_2_IN_EDGE_Pos 1 /*!< GIMA CAP1_2_IN: EDGE Position */ -#define GIMA_CAP1_2_IN_EDGE_Msk (0x01UL << GIMA_CAP1_2_IN_EDGE_Pos) /*!< GIMA CAP1_2_IN: EDGE Mask */ -#define GIMA_CAP1_2_IN_SYNCH_Pos 2 /*!< GIMA CAP1_2_IN: SYNCH Position */ -#define GIMA_CAP1_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_2_IN_SYNCH_Pos) /*!< GIMA CAP1_2_IN: SYNCH Mask */ -#define GIMA_CAP1_2_IN_PULSE_Pos 3 /*!< GIMA CAP1_2_IN: PULSE Position */ -#define GIMA_CAP1_2_IN_PULSE_Msk (0x01UL << GIMA_CAP1_2_IN_PULSE_Pos) /*!< GIMA CAP1_2_IN: PULSE Mask */ -#define GIMA_CAP1_2_IN_SELECT_Pos 4 /*!< GIMA CAP1_2_IN: SELECT Position */ -#define GIMA_CAP1_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_2_IN_SELECT_Pos) /*!< GIMA CAP1_2_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP1_3_IN ----------------------------------------- -#define GIMA_CAP1_3_IN_INV_Pos 0 /*!< GIMA CAP1_3_IN: INV Position */ -#define GIMA_CAP1_3_IN_INV_Msk (0x01UL << GIMA_CAP1_3_IN_INV_Pos) /*!< GIMA CAP1_3_IN: INV Mask */ -#define GIMA_CAP1_3_IN_EDGE_Pos 1 /*!< GIMA CAP1_3_IN: EDGE Position */ -#define GIMA_CAP1_3_IN_EDGE_Msk (0x01UL << GIMA_CAP1_3_IN_EDGE_Pos) /*!< GIMA CAP1_3_IN: EDGE Mask */ -#define GIMA_CAP1_3_IN_SYNCH_Pos 2 /*!< GIMA CAP1_3_IN: SYNCH Position */ -#define GIMA_CAP1_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_3_IN_SYNCH_Pos) /*!< GIMA CAP1_3_IN: SYNCH Mask */ -#define GIMA_CAP1_3_IN_PULSE_Pos 3 /*!< GIMA CAP1_3_IN: PULSE Position */ -#define GIMA_CAP1_3_IN_PULSE_Msk (0x01UL << GIMA_CAP1_3_IN_PULSE_Pos) /*!< GIMA CAP1_3_IN: PULSE Mask */ -#define GIMA_CAP1_3_IN_SELECT_Pos 4 /*!< GIMA CAP1_3_IN: SELECT Position */ -#define GIMA_CAP1_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_3_IN_SELECT_Pos) /*!< GIMA CAP1_3_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP2_0_IN ----------------------------------------- -#define GIMA_CAP2_0_IN_INV_Pos 0 /*!< GIMA CAP2_0_IN: INV Position */ -#define GIMA_CAP2_0_IN_INV_Msk (0x01UL << GIMA_CAP2_0_IN_INV_Pos) /*!< GIMA CAP2_0_IN: INV Mask */ -#define GIMA_CAP2_0_IN_EDGE_Pos 1 /*!< GIMA CAP2_0_IN: EDGE Position */ -#define GIMA_CAP2_0_IN_EDGE_Msk (0x01UL << GIMA_CAP2_0_IN_EDGE_Pos) /*!< GIMA CAP2_0_IN: EDGE Mask */ -#define GIMA_CAP2_0_IN_SYNCH_Pos 2 /*!< GIMA CAP2_0_IN: SYNCH Position */ -#define GIMA_CAP2_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_0_IN_SYNCH_Pos) /*!< GIMA CAP2_0_IN: SYNCH Mask */ -#define GIMA_CAP2_0_IN_PULSE_Pos 3 /*!< GIMA CAP2_0_IN: PULSE Position */ -#define GIMA_CAP2_0_IN_PULSE_Msk (0x01UL << GIMA_CAP2_0_IN_PULSE_Pos) /*!< GIMA CAP2_0_IN: PULSE Mask */ -#define GIMA_CAP2_0_IN_SELECT_Pos 4 /*!< GIMA CAP2_0_IN: SELECT Position */ -#define GIMA_CAP2_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_0_IN_SELECT_Pos) /*!< GIMA CAP2_0_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP2_1_IN ----------------------------------------- -#define GIMA_CAP2_1_IN_INV_Pos 0 /*!< GIMA CAP2_1_IN: INV Position */ -#define GIMA_CAP2_1_IN_INV_Msk (0x01UL << GIMA_CAP2_1_IN_INV_Pos) /*!< GIMA CAP2_1_IN: INV Mask */ -#define GIMA_CAP2_1_IN_EDGE_Pos 1 /*!< GIMA CAP2_1_IN: EDGE Position */ -#define GIMA_CAP2_1_IN_EDGE_Msk (0x01UL << GIMA_CAP2_1_IN_EDGE_Pos) /*!< GIMA CAP2_1_IN: EDGE Mask */ -#define GIMA_CAP2_1_IN_SYNCH_Pos 2 /*!< GIMA CAP2_1_IN: SYNCH Position */ -#define GIMA_CAP2_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_1_IN_SYNCH_Pos) /*!< GIMA CAP2_1_IN: SYNCH Mask */ -#define GIMA_CAP2_1_IN_PULSE_Pos 3 /*!< GIMA CAP2_1_IN: PULSE Position */ -#define GIMA_CAP2_1_IN_PULSE_Msk (0x01UL << GIMA_CAP2_1_IN_PULSE_Pos) /*!< GIMA CAP2_1_IN: PULSE Mask */ -#define GIMA_CAP2_1_IN_SELECT_Pos 4 /*!< GIMA CAP2_1_IN: SELECT Position */ -#define GIMA_CAP2_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_1_IN_SELECT_Pos) /*!< GIMA CAP2_1_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP2_2_IN ----------------------------------------- -#define GIMA_CAP2_2_IN_INV_Pos 0 /*!< GIMA CAP2_2_IN: INV Position */ -#define GIMA_CAP2_2_IN_INV_Msk (0x01UL << GIMA_CAP2_2_IN_INV_Pos) /*!< GIMA CAP2_2_IN: INV Mask */ -#define GIMA_CAP2_2_IN_EDGE_Pos 1 /*!< GIMA CAP2_2_IN: EDGE Position */ -#define GIMA_CAP2_2_IN_EDGE_Msk (0x01UL << GIMA_CAP2_2_IN_EDGE_Pos) /*!< GIMA CAP2_2_IN: EDGE Mask */ -#define GIMA_CAP2_2_IN_SYNCH_Pos 2 /*!< GIMA CAP2_2_IN: SYNCH Position */ -#define GIMA_CAP2_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_2_IN_SYNCH_Pos) /*!< GIMA CAP2_2_IN: SYNCH Mask */ -#define GIMA_CAP2_2_IN_PULSE_Pos 3 /*!< GIMA CAP2_2_IN: PULSE Position */ -#define GIMA_CAP2_2_IN_PULSE_Msk (0x01UL << GIMA_CAP2_2_IN_PULSE_Pos) /*!< GIMA CAP2_2_IN: PULSE Mask */ -#define GIMA_CAP2_2_IN_SELECT_Pos 4 /*!< GIMA CAP2_2_IN: SELECT Position */ -#define GIMA_CAP2_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_2_IN_SELECT_Pos) /*!< GIMA CAP2_2_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP2_3_IN ----------------------------------------- -#define GIMA_CAP2_3_IN_INV_Pos 0 /*!< GIMA CAP2_3_IN: INV Position */ -#define GIMA_CAP2_3_IN_INV_Msk (0x01UL << GIMA_CAP2_3_IN_INV_Pos) /*!< GIMA CAP2_3_IN: INV Mask */ -#define GIMA_CAP2_3_IN_EDGE_Pos 1 /*!< GIMA CAP2_3_IN: EDGE Position */ -#define GIMA_CAP2_3_IN_EDGE_Msk (0x01UL << GIMA_CAP2_3_IN_EDGE_Pos) /*!< GIMA CAP2_3_IN: EDGE Mask */ -#define GIMA_CAP2_3_IN_SYNCH_Pos 2 /*!< GIMA CAP2_3_IN: SYNCH Position */ -#define GIMA_CAP2_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_3_IN_SYNCH_Pos) /*!< GIMA CAP2_3_IN: SYNCH Mask */ -#define GIMA_CAP2_3_IN_PULSE_Pos 3 /*!< GIMA CAP2_3_IN: PULSE Position */ -#define GIMA_CAP2_3_IN_PULSE_Msk (0x01UL << GIMA_CAP2_3_IN_PULSE_Pos) /*!< GIMA CAP2_3_IN: PULSE Mask */ -#define GIMA_CAP2_3_IN_SELECT_Pos 4 /*!< GIMA CAP2_3_IN: SELECT Position */ -#define GIMA_CAP2_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_3_IN_SELECT_Pos) /*!< GIMA CAP2_3_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP3_0_IN ----------------------------------------- -#define GIMA_CAP3_0_IN_INV_Pos 0 /*!< GIMA CAP3_0_IN: INV Position */ -#define GIMA_CAP3_0_IN_INV_Msk (0x01UL << GIMA_CAP3_0_IN_INV_Pos) /*!< GIMA CAP3_0_IN: INV Mask */ -#define GIMA_CAP3_0_IN_EDGE_Pos 1 /*!< GIMA CAP3_0_IN: EDGE Position */ -#define GIMA_CAP3_0_IN_EDGE_Msk (0x01UL << GIMA_CAP3_0_IN_EDGE_Pos) /*!< GIMA CAP3_0_IN: EDGE Mask */ -#define GIMA_CAP3_0_IN_SYNCH_Pos 2 /*!< GIMA CAP3_0_IN: SYNCH Position */ -#define GIMA_CAP3_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_0_IN_SYNCH_Pos) /*!< GIMA CAP3_0_IN: SYNCH Mask */ -#define GIMA_CAP3_0_IN_PULSE_Pos 3 /*!< GIMA CAP3_0_IN: PULSE Position */ -#define GIMA_CAP3_0_IN_PULSE_Msk (0x01UL << GIMA_CAP3_0_IN_PULSE_Pos) /*!< GIMA CAP3_0_IN: PULSE Mask */ -#define GIMA_CAP3_0_IN_SELECT_Pos 4 /*!< GIMA CAP3_0_IN: SELECT Position */ -#define GIMA_CAP3_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_0_IN_SELECT_Pos) /*!< GIMA CAP3_0_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP3_1_IN ----------------------------------------- -#define GIMA_CAP3_1_IN_INV_Pos 0 /*!< GIMA CAP3_1_IN: INV Position */ -#define GIMA_CAP3_1_IN_INV_Msk (0x01UL << GIMA_CAP3_1_IN_INV_Pos) /*!< GIMA CAP3_1_IN: INV Mask */ -#define GIMA_CAP3_1_IN_EDGE_Pos 1 /*!< GIMA CAP3_1_IN: EDGE Position */ -#define GIMA_CAP3_1_IN_EDGE_Msk (0x01UL << GIMA_CAP3_1_IN_EDGE_Pos) /*!< GIMA CAP3_1_IN: EDGE Mask */ -#define GIMA_CAP3_1_IN_SYNCH_Pos 2 /*!< GIMA CAP3_1_IN: SYNCH Position */ -#define GIMA_CAP3_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_1_IN_SYNCH_Pos) /*!< GIMA CAP3_1_IN: SYNCH Mask */ -#define GIMA_CAP3_1_IN_PULSE_Pos 3 /*!< GIMA CAP3_1_IN: PULSE Position */ -#define GIMA_CAP3_1_IN_PULSE_Msk (0x01UL << GIMA_CAP3_1_IN_PULSE_Pos) /*!< GIMA CAP3_1_IN: PULSE Mask */ -#define GIMA_CAP3_1_IN_SELECT_Pos 4 /*!< GIMA CAP3_1_IN: SELECT Position */ -#define GIMA_CAP3_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_1_IN_SELECT_Pos) /*!< GIMA CAP3_1_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP3_2_IN ----------------------------------------- -#define GIMA_CAP3_2_IN_INV_Pos 0 /*!< GIMA CAP3_2_IN: INV Position */ -#define GIMA_CAP3_2_IN_INV_Msk (0x01UL << GIMA_CAP3_2_IN_INV_Pos) /*!< GIMA CAP3_2_IN: INV Mask */ -#define GIMA_CAP3_2_IN_EDGE_Pos 1 /*!< GIMA CAP3_2_IN: EDGE Position */ -#define GIMA_CAP3_2_IN_EDGE_Msk (0x01UL << GIMA_CAP3_2_IN_EDGE_Pos) /*!< GIMA CAP3_2_IN: EDGE Mask */ -#define GIMA_CAP3_2_IN_SYNCH_Pos 2 /*!< GIMA CAP3_2_IN: SYNCH Position */ -#define GIMA_CAP3_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_2_IN_SYNCH_Pos) /*!< GIMA CAP3_2_IN: SYNCH Mask */ -#define GIMA_CAP3_2_IN_PULSE_Pos 3 /*!< GIMA CAP3_2_IN: PULSE Position */ -#define GIMA_CAP3_2_IN_PULSE_Msk (0x01UL << GIMA_CAP3_2_IN_PULSE_Pos) /*!< GIMA CAP3_2_IN: PULSE Mask */ -#define GIMA_CAP3_2_IN_SELECT_Pos 4 /*!< GIMA CAP3_2_IN: SELECT Position */ -#define GIMA_CAP3_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_2_IN_SELECT_Pos) /*!< GIMA CAP3_2_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CAP3_3_IN ----------------------------------------- -#define GIMA_CAP3_3_IN_INV_Pos 0 /*!< GIMA CAP3_3_IN: INV Position */ -#define GIMA_CAP3_3_IN_INV_Msk (0x01UL << GIMA_CAP3_3_IN_INV_Pos) /*!< GIMA CAP3_3_IN: INV Mask */ -#define GIMA_CAP3_3_IN_EDGE_Pos 1 /*!< GIMA CAP3_3_IN: EDGE Position */ -#define GIMA_CAP3_3_IN_EDGE_Msk (0x01UL << GIMA_CAP3_3_IN_EDGE_Pos) /*!< GIMA CAP3_3_IN: EDGE Mask */ -#define GIMA_CAP3_3_IN_SYNCH_Pos 2 /*!< GIMA CAP3_3_IN: SYNCH Position */ -#define GIMA_CAP3_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_3_IN_SYNCH_Pos) /*!< GIMA CAP3_3_IN: SYNCH Mask */ -#define GIMA_CAP3_3_IN_PULSE_Pos 3 /*!< GIMA CAP3_3_IN: PULSE Position */ -#define GIMA_CAP3_3_IN_PULSE_Msk (0x01UL << GIMA_CAP3_3_IN_PULSE_Pos) /*!< GIMA CAP3_3_IN: PULSE Mask */ -#define GIMA_CAP3_3_IN_SELECT_Pos 4 /*!< GIMA CAP3_3_IN: SELECT Position */ -#define GIMA_CAP3_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_3_IN_SELECT_Pos) /*!< GIMA CAP3_3_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CTIN_0_IN ----------------------------------------- -#define GIMA_CTIN_0_IN_INV_Pos 0 /*!< GIMA CTIN_0_IN: INV Position */ -#define GIMA_CTIN_0_IN_INV_Msk (0x01UL << GIMA_CTIN_0_IN_INV_Pos) /*!< GIMA CTIN_0_IN: INV Mask */ -#define GIMA_CTIN_0_IN_EDGE_Pos 1 /*!< GIMA CTIN_0_IN: EDGE Position */ -#define GIMA_CTIN_0_IN_EDGE_Msk (0x01UL << GIMA_CTIN_0_IN_EDGE_Pos) /*!< GIMA CTIN_0_IN: EDGE Mask */ -#define GIMA_CTIN_0_IN_SYNCH_Pos 2 /*!< GIMA CTIN_0_IN: SYNCH Position */ -#define GIMA_CTIN_0_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_0_IN_SYNCH_Pos) /*!< GIMA CTIN_0_IN: SYNCH Mask */ -#define GIMA_CTIN_0_IN_PULSE_Pos 3 /*!< GIMA CTIN_0_IN: PULSE Position */ -#define GIMA_CTIN_0_IN_PULSE_Msk (0x01UL << GIMA_CTIN_0_IN_PULSE_Pos) /*!< GIMA CTIN_0_IN: PULSE Mask */ -#define GIMA_CTIN_0_IN_SELECT_Pos 4 /*!< GIMA CTIN_0_IN: SELECT Position */ -#define GIMA_CTIN_0_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_0_IN_SELECT_Pos) /*!< GIMA CTIN_0_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CTIN_1_IN ----------------------------------------- -#define GIMA_CTIN_1_IN_INV_Pos 0 /*!< GIMA CTIN_1_IN: INV Position */ -#define GIMA_CTIN_1_IN_INV_Msk (0x01UL << GIMA_CTIN_1_IN_INV_Pos) /*!< GIMA CTIN_1_IN: INV Mask */ -#define GIMA_CTIN_1_IN_EDGE_Pos 1 /*!< GIMA CTIN_1_IN: EDGE Position */ -#define GIMA_CTIN_1_IN_EDGE_Msk (0x01UL << GIMA_CTIN_1_IN_EDGE_Pos) /*!< GIMA CTIN_1_IN: EDGE Mask */ -#define GIMA_CTIN_1_IN_SYNCH_Pos 2 /*!< GIMA CTIN_1_IN: SYNCH Position */ -#define GIMA_CTIN_1_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_1_IN_SYNCH_Pos) /*!< GIMA CTIN_1_IN: SYNCH Mask */ -#define GIMA_CTIN_1_IN_PULSE_Pos 3 /*!< GIMA CTIN_1_IN: PULSE Position */ -#define GIMA_CTIN_1_IN_PULSE_Msk (0x01UL << GIMA_CTIN_1_IN_PULSE_Pos) /*!< GIMA CTIN_1_IN: PULSE Mask */ -#define GIMA_CTIN_1_IN_SELECT_Pos 4 /*!< GIMA CTIN_1_IN: SELECT Position */ -#define GIMA_CTIN_1_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_1_IN_SELECT_Pos) /*!< GIMA CTIN_1_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CTIN_2_IN ----------------------------------------- -#define GIMA_CTIN_2_IN_INV_Pos 0 /*!< GIMA CTIN_2_IN: INV Position */ -#define GIMA_CTIN_2_IN_INV_Msk (0x01UL << GIMA_CTIN_2_IN_INV_Pos) /*!< GIMA CTIN_2_IN: INV Mask */ -#define GIMA_CTIN_2_IN_EDGE_Pos 1 /*!< GIMA CTIN_2_IN: EDGE Position */ -#define GIMA_CTIN_2_IN_EDGE_Msk (0x01UL << GIMA_CTIN_2_IN_EDGE_Pos) /*!< GIMA CTIN_2_IN: EDGE Mask */ -#define GIMA_CTIN_2_IN_SYNCH_Pos 2 /*!< GIMA CTIN_2_IN: SYNCH Position */ -#define GIMA_CTIN_2_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_2_IN_SYNCH_Pos) /*!< GIMA CTIN_2_IN: SYNCH Mask */ -#define GIMA_CTIN_2_IN_PULSE_Pos 3 /*!< GIMA CTIN_2_IN: PULSE Position */ -#define GIMA_CTIN_2_IN_PULSE_Msk (0x01UL << GIMA_CTIN_2_IN_PULSE_Pos) /*!< GIMA CTIN_2_IN: PULSE Mask */ -#define GIMA_CTIN_2_IN_SELECT_Pos 4 /*!< GIMA CTIN_2_IN: SELECT Position */ -#define GIMA_CTIN_2_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_2_IN_SELECT_Pos) /*!< GIMA CTIN_2_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CTIN_3_IN ----------------------------------------- -#define GIMA_CTIN_3_IN_INV_Pos 0 /*!< GIMA CTIN_3_IN: INV Position */ -#define GIMA_CTIN_3_IN_INV_Msk (0x01UL << GIMA_CTIN_3_IN_INV_Pos) /*!< GIMA CTIN_3_IN: INV Mask */ -#define GIMA_CTIN_3_IN_EDGE_Pos 1 /*!< GIMA CTIN_3_IN: EDGE Position */ -#define GIMA_CTIN_3_IN_EDGE_Msk (0x01UL << GIMA_CTIN_3_IN_EDGE_Pos) /*!< GIMA CTIN_3_IN: EDGE Mask */ -#define GIMA_CTIN_3_IN_SYNCH_Pos 2 /*!< GIMA CTIN_3_IN: SYNCH Position */ -#define GIMA_CTIN_3_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_3_IN_SYNCH_Pos) /*!< GIMA CTIN_3_IN: SYNCH Mask */ -#define GIMA_CTIN_3_IN_PULSE_Pos 3 /*!< GIMA CTIN_3_IN: PULSE Position */ -#define GIMA_CTIN_3_IN_PULSE_Msk (0x01UL << GIMA_CTIN_3_IN_PULSE_Pos) /*!< GIMA CTIN_3_IN: PULSE Mask */ -#define GIMA_CTIN_3_IN_SELECT_Pos 4 /*!< GIMA CTIN_3_IN: SELECT Position */ -#define GIMA_CTIN_3_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_3_IN_SELECT_Pos) /*!< GIMA CTIN_3_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CTIN_4_IN ----------------------------------------- -#define GIMA_CTIN_4_IN_INV_Pos 0 /*!< GIMA CTIN_4_IN: INV Position */ -#define GIMA_CTIN_4_IN_INV_Msk (0x01UL << GIMA_CTIN_4_IN_INV_Pos) /*!< GIMA CTIN_4_IN: INV Mask */ -#define GIMA_CTIN_4_IN_EDGE_Pos 1 /*!< GIMA CTIN_4_IN: EDGE Position */ -#define GIMA_CTIN_4_IN_EDGE_Msk (0x01UL << GIMA_CTIN_4_IN_EDGE_Pos) /*!< GIMA CTIN_4_IN: EDGE Mask */ -#define GIMA_CTIN_4_IN_SYNCH_Pos 2 /*!< GIMA CTIN_4_IN: SYNCH Position */ -#define GIMA_CTIN_4_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_4_IN_SYNCH_Pos) /*!< GIMA CTIN_4_IN: SYNCH Mask */ -#define GIMA_CTIN_4_IN_PULSE_Pos 3 /*!< GIMA CTIN_4_IN: PULSE Position */ -#define GIMA_CTIN_4_IN_PULSE_Msk (0x01UL << GIMA_CTIN_4_IN_PULSE_Pos) /*!< GIMA CTIN_4_IN: PULSE Mask */ -#define GIMA_CTIN_4_IN_SELECT_Pos 4 /*!< GIMA CTIN_4_IN: SELECT Position */ -#define GIMA_CTIN_4_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_4_IN_SELECT_Pos) /*!< GIMA CTIN_4_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CTIN_5_IN ----------------------------------------- -#define GIMA_CTIN_5_IN_INV_Pos 0 /*!< GIMA CTIN_5_IN: INV Position */ -#define GIMA_CTIN_5_IN_INV_Msk (0x01UL << GIMA_CTIN_5_IN_INV_Pos) /*!< GIMA CTIN_5_IN: INV Mask */ -#define GIMA_CTIN_5_IN_EDGE_Pos 1 /*!< GIMA CTIN_5_IN: EDGE Position */ -#define GIMA_CTIN_5_IN_EDGE_Msk (0x01UL << GIMA_CTIN_5_IN_EDGE_Pos) /*!< GIMA CTIN_5_IN: EDGE Mask */ -#define GIMA_CTIN_5_IN_SYNCH_Pos 2 /*!< GIMA CTIN_5_IN: SYNCH Position */ -#define GIMA_CTIN_5_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_5_IN_SYNCH_Pos) /*!< GIMA CTIN_5_IN: SYNCH Mask */ -#define GIMA_CTIN_5_IN_PULSE_Pos 3 /*!< GIMA CTIN_5_IN: PULSE Position */ -#define GIMA_CTIN_5_IN_PULSE_Msk (0x01UL << GIMA_CTIN_5_IN_PULSE_Pos) /*!< GIMA CTIN_5_IN: PULSE Mask */ -#define GIMA_CTIN_5_IN_SELECT_Pos 4 /*!< GIMA CTIN_5_IN: SELECT Position */ -#define GIMA_CTIN_5_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_5_IN_SELECT_Pos) /*!< GIMA CTIN_5_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CTIN_6_IN ----------------------------------------- -#define GIMA_CTIN_6_IN_INV_Pos 0 /*!< GIMA CTIN_6_IN: INV Position */ -#define GIMA_CTIN_6_IN_INV_Msk (0x01UL << GIMA_CTIN_6_IN_INV_Pos) /*!< GIMA CTIN_6_IN: INV Mask */ -#define GIMA_CTIN_6_IN_EDGE_Pos 1 /*!< GIMA CTIN_6_IN: EDGE Position */ -#define GIMA_CTIN_6_IN_EDGE_Msk (0x01UL << GIMA_CTIN_6_IN_EDGE_Pos) /*!< GIMA CTIN_6_IN: EDGE Mask */ -#define GIMA_CTIN_6_IN_SYNCH_Pos 2 /*!< GIMA CTIN_6_IN: SYNCH Position */ -#define GIMA_CTIN_6_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_6_IN_SYNCH_Pos) /*!< GIMA CTIN_6_IN: SYNCH Mask */ -#define GIMA_CTIN_6_IN_PULSE_Pos 3 /*!< GIMA CTIN_6_IN: PULSE Position */ -#define GIMA_CTIN_6_IN_PULSE_Msk (0x01UL << GIMA_CTIN_6_IN_PULSE_Pos) /*!< GIMA CTIN_6_IN: PULSE Mask */ -#define GIMA_CTIN_6_IN_SELECT_Pos 4 /*!< GIMA CTIN_6_IN: SELECT Position */ -#define GIMA_CTIN_6_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_6_IN_SELECT_Pos) /*!< GIMA CTIN_6_IN: SELECT Mask */ - -// ------------------------------------- GIMA_CTIN_7_IN ----------------------------------------- -#define GIMA_CTIN_7_IN_INV_Pos 0 /*!< GIMA CTIN_7_IN: INV Position */ -#define GIMA_CTIN_7_IN_INV_Msk (0x01UL << GIMA_CTIN_7_IN_INV_Pos) /*!< GIMA CTIN_7_IN: INV Mask */ -#define GIMA_CTIN_7_IN_EDGE_Pos 1 /*!< GIMA CTIN_7_IN: EDGE Position */ -#define GIMA_CTIN_7_IN_EDGE_Msk (0x01UL << GIMA_CTIN_7_IN_EDGE_Pos) /*!< GIMA CTIN_7_IN: EDGE Mask */ -#define GIMA_CTIN_7_IN_SYNCH_Pos 2 /*!< GIMA CTIN_7_IN: SYNCH Position */ -#define GIMA_CTIN_7_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_7_IN_SYNCH_Pos) /*!< GIMA CTIN_7_IN: SYNCH Mask */ -#define GIMA_CTIN_7_IN_PULSE_Pos 3 /*!< GIMA CTIN_7_IN: PULSE Position */ -#define GIMA_CTIN_7_IN_PULSE_Msk (0x01UL << GIMA_CTIN_7_IN_PULSE_Pos) /*!< GIMA CTIN_7_IN: PULSE Mask */ -#define GIMA_CTIN_7_IN_SELECT_Pos 4 /*!< GIMA CTIN_7_IN: SELECT Position */ -#define GIMA_CTIN_7_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_7_IN_SELECT_Pos) /*!< GIMA CTIN_7_IN: SELECT Mask */ - -// ---------------------------------- GIMA_VADC_TRIGGER_IN -------------------------------------- -#define GIMA_VADC_TRIGGER_IN_INV_Pos 0 /*!< GIMA VADC_TRIGGER_IN: INV Position */ -#define GIMA_VADC_TRIGGER_IN_INV_Msk (0x01UL << GIMA_VADC_TRIGGER_IN_INV_Pos) /*!< GIMA VADC_TRIGGER_IN: INV Mask */ -#define GIMA_VADC_TRIGGER_IN_EDGE_Pos 1 /*!< GIMA VADC_TRIGGER_IN: EDGE Position */ -#define GIMA_VADC_TRIGGER_IN_EDGE_Msk (0x01UL << GIMA_VADC_TRIGGER_IN_EDGE_Pos) /*!< GIMA VADC_TRIGGER_IN: EDGE Mask */ -#define GIMA_VADC_TRIGGER_IN_SYNCH_Pos 2 /*!< GIMA VADC_TRIGGER_IN: SYNCH Position */ -#define GIMA_VADC_TRIGGER_IN_SYNCH_Msk (0x01UL << GIMA_VADC_TRIGGER_IN_SYNCH_Pos) /*!< GIMA VADC_TRIGGER_IN: SYNCH Mask */ -#define GIMA_VADC_TRIGGER_IN_PULSE_Pos 3 /*!< GIMA VADC_TRIGGER_IN: PULSE Position */ -#define GIMA_VADC_TRIGGER_IN_PULSE_Msk (0x01UL << GIMA_VADC_TRIGGER_IN_PULSE_Pos) /*!< GIMA VADC_TRIGGER_IN: PULSE Mask */ -#define GIMA_VADC_TRIGGER_IN_SELECT_Pos 4 /*!< GIMA VADC_TRIGGER_IN: SELECT Position */ -#define GIMA_VADC_TRIGGER_IN_SELECT_Msk (0x0fUL << GIMA_VADC_TRIGGER_IN_SELECT_Pos) /*!< GIMA VADC_TRIGGER_IN: SELECT Mask */ - -// --------------------------------- GIMA_EVENTROUTER_13_IN ------------------------------------- -#define GIMA_EVENTROUTER_13_IN_INV_Pos 0 /*!< GIMA EVENTROUTER_13_IN: INV Position */ -#define GIMA_EVENTROUTER_13_IN_INV_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_INV_Pos) /*!< GIMA EVENTROUTER_13_IN: INV Mask */ -#define GIMA_EVENTROUTER_13_IN_EDGE_Pos 1 /*!< GIMA EVENTROUTER_13_IN: EDGE Position */ -#define GIMA_EVENTROUTER_13_IN_EDGE_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_EDGE_Pos) /*!< GIMA EVENTROUTER_13_IN: EDGE Mask */ -#define GIMA_EVENTROUTER_13_IN_SYNCH_Pos 2 /*!< GIMA EVENTROUTER_13_IN: SYNCH Position */ -#define GIMA_EVENTROUTER_13_IN_SYNCH_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_SYNCH_Pos) /*!< GIMA EVENTROUTER_13_IN: SYNCH Mask */ -#define GIMA_EVENTROUTER_13_IN_PULSE_Pos 3 /*!< GIMA EVENTROUTER_13_IN: PULSE Position */ -#define GIMA_EVENTROUTER_13_IN_PULSE_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_PULSE_Pos) /*!< GIMA EVENTROUTER_13_IN: PULSE Mask */ -#define GIMA_EVENTROUTER_13_IN_SELECT_Pos 4 /*!< GIMA EVENTROUTER_13_IN: SELECT Position */ -#define GIMA_EVENTROUTER_13_IN_SELECT_Msk (0x0fUL << GIMA_EVENTROUTER_13_IN_SELECT_Pos) /*!< GIMA EVENTROUTER_13_IN: SELECT Mask */ - -// --------------------------------- GIMA_EVENTROUTER_14_IN ------------------------------------- -#define GIMA_EVENTROUTER_14_IN_INV_Pos 0 /*!< GIMA EVENTROUTER_14_IN: INV Position */ -#define GIMA_EVENTROUTER_14_IN_INV_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_INV_Pos) /*!< GIMA EVENTROUTER_14_IN: INV Mask */ -#define GIMA_EVENTROUTER_14_IN_EDGE_Pos 1 /*!< GIMA EVENTROUTER_14_IN: EDGE Position */ -#define GIMA_EVENTROUTER_14_IN_EDGE_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_EDGE_Pos) /*!< GIMA EVENTROUTER_14_IN: EDGE Mask */ -#define GIMA_EVENTROUTER_14_IN_SYNCH_Pos 2 /*!< GIMA EVENTROUTER_14_IN: SYNCH Position */ -#define GIMA_EVENTROUTER_14_IN_SYNCH_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_SYNCH_Pos) /*!< GIMA EVENTROUTER_14_IN: SYNCH Mask */ -#define GIMA_EVENTROUTER_14_IN_PULSE_Pos 3 /*!< GIMA EVENTROUTER_14_IN: PULSE Position */ -#define GIMA_EVENTROUTER_14_IN_PULSE_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_PULSE_Pos) /*!< GIMA EVENTROUTER_14_IN: PULSE Mask */ -#define GIMA_EVENTROUTER_14_IN_SELECT_Pos 4 /*!< GIMA EVENTROUTER_14_IN: SELECT Position */ -#define GIMA_EVENTROUTER_14_IN_SELECT_Msk (0x0fUL << GIMA_EVENTROUTER_14_IN_SELECT_Pos) /*!< GIMA EVENTROUTER_14_IN: SELECT Mask */ - -// --------------------------------- GIMA_EVENTROUTER_16_IN ------------------------------------- -#define GIMA_EVENTROUTER_16_IN_INV_Pos 0 /*!< GIMA EVENTROUTER_16_IN: INV Position */ -#define GIMA_EVENTROUTER_16_IN_INV_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_INV_Pos) /*!< GIMA EVENTROUTER_16_IN: INV Mask */ -#define GIMA_EVENTROUTER_16_IN_EDGE_Pos 1 /*!< GIMA EVENTROUTER_16_IN: EDGE Position */ -#define GIMA_EVENTROUTER_16_IN_EDGE_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_EDGE_Pos) /*!< GIMA EVENTROUTER_16_IN: EDGE Mask */ -#define GIMA_EVENTROUTER_16_IN_SYNCH_Pos 2 /*!< GIMA EVENTROUTER_16_IN: SYNCH Position */ -#define GIMA_EVENTROUTER_16_IN_SYNCH_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_SYNCH_Pos) /*!< GIMA EVENTROUTER_16_IN: SYNCH Mask */ -#define GIMA_EVENTROUTER_16_IN_PULSE_Pos 3 /*!< GIMA EVENTROUTER_16_IN: PULSE Position */ -#define GIMA_EVENTROUTER_16_IN_PULSE_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_PULSE_Pos) /*!< GIMA EVENTROUTER_16_IN: PULSE Mask */ -#define GIMA_EVENTROUTER_16_IN_SELECT_Pos 4 /*!< GIMA EVENTROUTER_16_IN: SELECT Position */ -#define GIMA_EVENTROUTER_16_IN_SELECT_Msk (0x0fUL << GIMA_EVENTROUTER_16_IN_SELECT_Pos) /*!< GIMA EVENTROUTER_16_IN: SELECT Mask */ - -// ------------------------------------ GIMA_ADCSTART0_IN --------------------------------------- -#define GIMA_ADCSTART0_IN_INV_Pos 0 /*!< GIMA ADCSTART0_IN: INV Position */ -#define GIMA_ADCSTART0_IN_INV_Msk (0x01UL << GIMA_ADCSTART0_IN_INV_Pos) /*!< GIMA ADCSTART0_IN: INV Mask */ -#define GIMA_ADCSTART0_IN_EDGE_Pos 1 /*!< GIMA ADCSTART0_IN: EDGE Position */ -#define GIMA_ADCSTART0_IN_EDGE_Msk (0x01UL << GIMA_ADCSTART0_IN_EDGE_Pos) /*!< GIMA ADCSTART0_IN: EDGE Mask */ -#define GIMA_ADCSTART0_IN_SYNCH_Pos 2 /*!< GIMA ADCSTART0_IN: SYNCH Position */ -#define GIMA_ADCSTART0_IN_SYNCH_Msk (0x01UL << GIMA_ADCSTART0_IN_SYNCH_Pos) /*!< GIMA ADCSTART0_IN: SYNCH Mask */ -#define GIMA_ADCSTART0_IN_PULSE_Pos 3 /*!< GIMA ADCSTART0_IN: PULSE Position */ -#define GIMA_ADCSTART0_IN_PULSE_Msk (0x01UL << GIMA_ADCSTART0_IN_PULSE_Pos) /*!< GIMA ADCSTART0_IN: PULSE Mask */ -#define GIMA_ADCSTART0_IN_SELECT_Pos 4 /*!< GIMA ADCSTART0_IN: SELECT Position */ -#define GIMA_ADCSTART0_IN_SELECT_Msk (0x0fUL << GIMA_ADCSTART0_IN_SELECT_Pos) /*!< GIMA ADCSTART0_IN: SELECT Mask */ - -// ------------------------------------ GIMA_ADCSTART1_IN --------------------------------------- -#define GIMA_ADCSTART1_IN_INV_Pos 0 /*!< GIMA ADCSTART1_IN: INV Position */ -#define GIMA_ADCSTART1_IN_INV_Msk (0x01UL << GIMA_ADCSTART1_IN_INV_Pos) /*!< GIMA ADCSTART1_IN: INV Mask */ -#define GIMA_ADCSTART1_IN_EDGE_Pos 1 /*!< GIMA ADCSTART1_IN: EDGE Position */ -#define GIMA_ADCSTART1_IN_EDGE_Msk (0x01UL << GIMA_ADCSTART1_IN_EDGE_Pos) /*!< GIMA ADCSTART1_IN: EDGE Mask */ -#define GIMA_ADCSTART1_IN_SYNCH_Pos 2 /*!< GIMA ADCSTART1_IN: SYNCH Position */ -#define GIMA_ADCSTART1_IN_SYNCH_Msk (0x01UL << GIMA_ADCSTART1_IN_SYNCH_Pos) /*!< GIMA ADCSTART1_IN: SYNCH Mask */ -#define GIMA_ADCSTART1_IN_PULSE_Pos 3 /*!< GIMA ADCSTART1_IN: PULSE Position */ -#define GIMA_ADCSTART1_IN_PULSE_Msk (0x01UL << GIMA_ADCSTART1_IN_PULSE_Pos) /*!< GIMA ADCSTART1_IN: PULSE Mask */ -#define GIMA_ADCSTART1_IN_SELECT_Pos 4 /*!< GIMA ADCSTART1_IN: SELECT Position */ -#define GIMA_ADCSTART1_IN_SELECT_Msk (0x0fUL << GIMA_ADCSTART1_IN_SELECT_Pos) /*!< GIMA ADCSTART1_IN: SELECT Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- DAC Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ----------------------------------------- DAC_CR --------------------------------------------- -#define DAC_CR_VALUE_Pos 6 /*!< DAC CR: VALUE Position */ -#define DAC_CR_VALUE_Msk (0x000003ffUL << DAC_CR_VALUE_Pos) /*!< DAC CR: VALUE Mask */ -#define DAC_CR_BIAS_Pos 16 /*!< DAC CR: BIAS Position */ -#define DAC_CR_BIAS_Msk (0x01UL << DAC_CR_BIAS_Pos) /*!< DAC CR: BIAS Mask */ - -// ---------------------------------------- DAC_CTRL -------------------------------------------- -#define DAC_CTRL_INT_DMA_REQ_Pos 0 /*!< DAC CTRL: INT_DMA_REQ Position */ -#define DAC_CTRL_INT_DMA_REQ_Msk (0x01UL << DAC_CTRL_INT_DMA_REQ_Pos) /*!< DAC CTRL: INT_DMA_REQ Mask */ -#define DAC_CTRL_DBLBUF_ENA_Pos 1 /*!< DAC CTRL: DBLBUF_ENA Position */ -#define DAC_CTRL_DBLBUF_ENA_Msk (0x01UL << DAC_CTRL_DBLBUF_ENA_Pos) /*!< DAC CTRL: DBLBUF_ENA Mask */ -#define DAC_CTRL_CNT_ENA_Pos 2 /*!< DAC CTRL: CNT_ENA Position */ -#define DAC_CTRL_CNT_ENA_Msk (0x01UL << DAC_CTRL_CNT_ENA_Pos) /*!< DAC CTRL: CNT_ENA Mask */ -#define DAC_CTRL_DMA_ENA_Pos 3 /*!< DAC CTRL: DMA_ENA Position */ -#define DAC_CTRL_DMA_ENA_Msk (0x01UL << DAC_CTRL_DMA_ENA_Pos) /*!< DAC CTRL: DMA_ENA Mask */ - -// --------------------------------------- DAC_CNTVAL ------------------------------------------- -#define DAC_CNTVAL_VALUE_Pos 0 /*!< DAC CNTVAL: VALUE Position */ -#define DAC_CNTVAL_VALUE_Msk (0x0000ffffUL << DAC_CNTVAL_VALUE_Pos) /*!< DAC CNTVAL: VALUE Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- C_CAN0 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// --------------------------------------- C_CAN0_CNTL ------------------------------------------ -#define C_CAN0_CNTL_INIT_Pos 0 /*!< C_CAN0 CNTL: INIT Position */ -#define C_CAN0_CNTL_INIT_Msk (0x01UL << C_CAN0_CNTL_INIT_Pos) /*!< C_CAN0 CNTL: INIT Mask */ -#define C_CAN0_CNTL_IE_Pos 1 /*!< C_CAN0 CNTL: IE Position */ -#define C_CAN0_CNTL_IE_Msk (0x01UL << C_CAN0_CNTL_IE_Pos) /*!< C_CAN0 CNTL: IE Mask */ -#define C_CAN0_CNTL_SIE_Pos 2 /*!< C_CAN0 CNTL: SIE Position */ -#define C_CAN0_CNTL_SIE_Msk (0x01UL << C_CAN0_CNTL_SIE_Pos) /*!< C_CAN0 CNTL: SIE Mask */ -#define C_CAN0_CNTL_EIE_Pos 3 /*!< C_CAN0 CNTL: EIE Position */ -#define C_CAN0_CNTL_EIE_Msk (0x01UL << C_CAN0_CNTL_EIE_Pos) /*!< C_CAN0 CNTL: EIE Mask */ -#define C_CAN0_CNTL_DAR_Pos 5 /*!< C_CAN0 CNTL: DAR Position */ -#define C_CAN0_CNTL_DAR_Msk (0x01UL << C_CAN0_CNTL_DAR_Pos) /*!< C_CAN0 CNTL: DAR Mask */ -#define C_CAN0_CNTL_CCE_Pos 6 /*!< C_CAN0 CNTL: CCE Position */ -#define C_CAN0_CNTL_CCE_Msk (0x01UL << C_CAN0_CNTL_CCE_Pos) /*!< C_CAN0 CNTL: CCE Mask */ -#define C_CAN0_CNTL_TEST_Pos 7 /*!< C_CAN0 CNTL: TEST Position */ -#define C_CAN0_CNTL_TEST_Msk (0x01UL << C_CAN0_CNTL_TEST_Pos) /*!< C_CAN0 CNTL: TEST Mask */ - -// --------------------------------------- C_CAN0_STAT ------------------------------------------ -#define C_CAN0_STAT_LEC_Pos 0 /*!< C_CAN0 STAT: LEC Position */ -#define C_CAN0_STAT_LEC_Msk (0x07UL << C_CAN0_STAT_LEC_Pos) /*!< C_CAN0 STAT: LEC Mask */ -#define C_CAN0_STAT_TXOK_Pos 3 /*!< C_CAN0 STAT: TXOK Position */ -#define C_CAN0_STAT_TXOK_Msk (0x01UL << C_CAN0_STAT_TXOK_Pos) /*!< C_CAN0 STAT: TXOK Mask */ -#define C_CAN0_STAT_RXOK_Pos 4 /*!< C_CAN0 STAT: RXOK Position */ -#define C_CAN0_STAT_RXOK_Msk (0x01UL << C_CAN0_STAT_RXOK_Pos) /*!< C_CAN0 STAT: RXOK Mask */ -#define C_CAN0_STAT_EPASS_Pos 5 /*!< C_CAN0 STAT: EPASS Position */ -#define C_CAN0_STAT_EPASS_Msk (0x01UL << C_CAN0_STAT_EPASS_Pos) /*!< C_CAN0 STAT: EPASS Mask */ -#define C_CAN0_STAT_EWARN_Pos 6 /*!< C_CAN0 STAT: EWARN Position */ -#define C_CAN0_STAT_EWARN_Msk (0x01UL << C_CAN0_STAT_EWARN_Pos) /*!< C_CAN0 STAT: EWARN Mask */ -#define C_CAN0_STAT_BOFF_Pos 7 /*!< C_CAN0 STAT: BOFF Position */ -#define C_CAN0_STAT_BOFF_Msk (0x01UL << C_CAN0_STAT_BOFF_Pos) /*!< C_CAN0 STAT: BOFF Mask */ - -// ---------------------------------------- C_CAN0_EC ------------------------------------------- -#define C_CAN0_EC_TEC_7_0_Pos 0 /*!< C_CAN0 EC: TEC_7_0 Position */ -#define C_CAN0_EC_TEC_7_0_Msk (0x000000ffUL << C_CAN0_EC_TEC_7_0_Pos) /*!< C_CAN0 EC: TEC_7_0 Mask */ -#define C_CAN0_EC_REC_6_0_Pos 8 /*!< C_CAN0 EC: REC_6_0 Position */ -#define C_CAN0_EC_REC_6_0_Msk (0x7fUL << C_CAN0_EC_REC_6_0_Pos) /*!< C_CAN0 EC: REC_6_0 Mask */ -#define C_CAN0_EC_RP_Pos 15 /*!< C_CAN0 EC: RP Position */ -#define C_CAN0_EC_RP_Msk (0x01UL << C_CAN0_EC_RP_Pos) /*!< C_CAN0 EC: RP Mask */ - -// ---------------------------------------- C_CAN0_BT ------------------------------------------- -#define C_CAN0_BT_BRP_Pos 0 /*!< C_CAN0 BT: BRP Position */ -#define C_CAN0_BT_BRP_Msk (0x3fUL << C_CAN0_BT_BRP_Pos) /*!< C_CAN0 BT: BRP Mask */ -#define C_CAN0_BT_SJW_Pos 6 /*!< C_CAN0 BT: SJW Position */ -#define C_CAN0_BT_SJW_Msk (0x03UL << C_CAN0_BT_SJW_Pos) /*!< C_CAN0 BT: SJW Mask */ -#define C_CAN0_BT_TSEG1_Pos 8 /*!< C_CAN0 BT: TSEG1 Position */ -#define C_CAN0_BT_TSEG1_Msk (0x0fUL << C_CAN0_BT_TSEG1_Pos) /*!< C_CAN0 BT: TSEG1 Mask */ -#define C_CAN0_BT_TSEG2_Pos 12 /*!< C_CAN0 BT: TSEG2 Position */ -#define C_CAN0_BT_TSEG2_Msk (0x07UL << C_CAN0_BT_TSEG2_Pos) /*!< C_CAN0 BT: TSEG2 Mask */ - -// --------------------------------------- C_CAN0_INT ------------------------------------------- -#define C_CAN0_INT_INTID15_0_Pos 0 /*!< C_CAN0 INT: INTID15_0 Position */ -#define C_CAN0_INT_INTID15_0_Msk (0x0000ffffUL << C_CAN0_INT_INTID15_0_Pos) /*!< C_CAN0 INT: INTID15_0 Mask */ - -// --------------------------------------- C_CAN0_TEST ------------------------------------------ -#define C_CAN0_TEST_BASIC_Pos 2 /*!< C_CAN0 TEST: BASIC Position */ -#define C_CAN0_TEST_BASIC_Msk (0x01UL << C_CAN0_TEST_BASIC_Pos) /*!< C_CAN0 TEST: BASIC Mask */ -#define C_CAN0_TEST_SILENT_Pos 3 /*!< C_CAN0 TEST: SILENT Position */ -#define C_CAN0_TEST_SILENT_Msk (0x01UL << C_CAN0_TEST_SILENT_Pos) /*!< C_CAN0 TEST: SILENT Mask */ -#define C_CAN0_TEST_LBACK_Pos 4 /*!< C_CAN0 TEST: LBACK Position */ -#define C_CAN0_TEST_LBACK_Msk (0x01UL << C_CAN0_TEST_LBACK_Pos) /*!< C_CAN0 TEST: LBACK Mask */ -#define C_CAN0_TEST_TX1_0_Pos 5 /*!< C_CAN0 TEST: TX1_0 Position */ -#define C_CAN0_TEST_TX1_0_Msk (0x03UL << C_CAN0_TEST_TX1_0_Pos) /*!< C_CAN0 TEST: TX1_0 Mask */ -#define C_CAN0_TEST_RX_Pos 7 /*!< C_CAN0 TEST: RX Position */ -#define C_CAN0_TEST_RX_Msk (0x01UL << C_CAN0_TEST_RX_Pos) /*!< C_CAN0 TEST: RX Mask */ - -// --------------------------------------- C_CAN0_BRPE ------------------------------------------ -#define C_CAN0_BRPE_BRPE_Pos 0 /*!< C_CAN0 BRPE: BRPE Position */ -#define C_CAN0_BRPE_BRPE_Msk (0x0fUL << C_CAN0_BRPE_BRPE_Pos) /*!< C_CAN0 BRPE: BRPE Mask */ - -// ------------------------------------ C_CAN0_IF1_CMDREQ --------------------------------------- -#define C_CAN0_IF1_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN0 IF1_CMDREQ: MESSNUM Position */ -#define C_CAN0_IF1_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN0_IF1_CMDREQ_MESSNUM_Pos) /*!< C_CAN0 IF1_CMDREQ: MESSNUM Mask */ -#define C_CAN0_IF1_CMDREQ_BUSY_Pos 15 /*!< C_CAN0 IF1_CMDREQ: BUSY Position */ -#define C_CAN0_IF1_CMDREQ_BUSY_Msk (0x01UL << C_CAN0_IF1_CMDREQ_BUSY_Pos) /*!< C_CAN0 IF1_CMDREQ: BUSY Mask */ - -// ----------------------------------- C_CAN0_IF1_CMDMSK_R -------------------------------------- -#define C_CAN0_IF1_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN0 IF1_CMDMSK_R: DATA_B Position */ -#define C_CAN0_IF1_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_B_Pos) /*!< C_CAN0 IF1_CMDMSK_R: DATA_B Mask */ -#define C_CAN0_IF1_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN0 IF1_CMDMSK_R: DATA_A Position */ -#define C_CAN0_IF1_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_A_Pos) /*!< C_CAN0 IF1_CMDMSK_R: DATA_A Mask */ -#define C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN0 IF1_CMDMSK_R: NEWDAT Position */ -#define C_CAN0_IF1_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN0 IF1_CMDMSK_R: NEWDAT Mask */ -#define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN0 IF1_CMDMSK_R: CLRINTPND Position */ -#define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN0 IF1_CMDMSK_R: CLRINTPND Mask */ -#define C_CAN0_IF1_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN0 IF1_CMDMSK_R: CTRL Position */ -#define C_CAN0_IF1_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_CTRL_Pos) /*!< C_CAN0 IF1_CMDMSK_R: CTRL Mask */ -#define C_CAN0_IF1_CMDMSK_R_ARB_Pos 5 /*!< C_CAN0 IF1_CMDMSK_R: ARB Position */ -#define C_CAN0_IF1_CMDMSK_R_ARB_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_ARB_Pos) /*!< C_CAN0 IF1_CMDMSK_R: ARB Mask */ -#define C_CAN0_IF1_CMDMSK_R_MASK_Pos 6 /*!< C_CAN0 IF1_CMDMSK_R: MASK Position */ -#define C_CAN0_IF1_CMDMSK_R_MASK_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_MASK_Pos) /*!< C_CAN0 IF1_CMDMSK_R: MASK Mask */ -#define C_CAN0_IF1_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN0 IF1_CMDMSK_R: WR_RD Position */ -#define C_CAN0_IF1_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_WR_RD_Pos) /*!< C_CAN0 IF1_CMDMSK_R: WR_RD Mask */ - -// ----------------------------------- C_CAN0_IF1_CMDMSK_W -------------------------------------- -#define C_CAN0_IF1_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN0 IF1_CMDMSK_W: DATA_B Position */ -#define C_CAN0_IF1_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_B_Pos) /*!< C_CAN0 IF1_CMDMSK_W: DATA_B Mask */ -#define C_CAN0_IF1_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN0 IF1_CMDMSK_W: DATA_A Position */ -#define C_CAN0_IF1_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_A_Pos) /*!< C_CAN0 IF1_CMDMSK_W: DATA_A Mask */ -#define C_CAN0_IF1_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN0 IF1_CMDMSK_W: TXRQST Position */ -#define C_CAN0_IF1_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_TXRQST_Pos) /*!< C_CAN0 IF1_CMDMSK_W: TXRQST Mask */ -#define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN0 IF1_CMDMSK_W: CLRINTPND Position */ -#define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN0 IF1_CMDMSK_W: CLRINTPND Mask */ -#define C_CAN0_IF1_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN0 IF1_CMDMSK_W: CTRL Position */ -#define C_CAN0_IF1_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_CTRL_Pos) /*!< C_CAN0 IF1_CMDMSK_W: CTRL Mask */ -#define C_CAN0_IF1_CMDMSK_W_ARB_Pos 5 /*!< C_CAN0 IF1_CMDMSK_W: ARB Position */ -#define C_CAN0_IF1_CMDMSK_W_ARB_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_ARB_Pos) /*!< C_CAN0 IF1_CMDMSK_W: ARB Mask */ -#define C_CAN0_IF1_CMDMSK_W_MASK_Pos 6 /*!< C_CAN0 IF1_CMDMSK_W: MASK Position */ -#define C_CAN0_IF1_CMDMSK_W_MASK_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_MASK_Pos) /*!< C_CAN0 IF1_CMDMSK_W: MASK Mask */ -#define C_CAN0_IF1_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN0 IF1_CMDMSK_W: WR_RD Position */ -#define C_CAN0_IF1_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_WR_RD_Pos) /*!< C_CAN0 IF1_CMDMSK_W: WR_RD Mask */ - -// ------------------------------------- C_CAN0_IF1_MSK1 ---------------------------------------- -#define C_CAN0_IF1_MSK1_MSK15_0_Pos 0 /*!< C_CAN0 IF1_MSK1: MSK15_0 Position */ -#define C_CAN0_IF1_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN0_IF1_MSK1_MSK15_0_Pos) /*!< C_CAN0 IF1_MSK1: MSK15_0 Mask */ - -// ------------------------------------- C_CAN0_IF1_MSK2 ---------------------------------------- -#define C_CAN0_IF1_MSK2_MSK28_16_Pos 0 /*!< C_CAN0 IF1_MSK2: MSK28_16 Position */ -#define C_CAN0_IF1_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN0_IF1_MSK2_MSK28_16_Pos) /*!< C_CAN0 IF1_MSK2: MSK28_16 Mask */ -#define C_CAN0_IF1_MSK2_MDIR_Pos 14 /*!< C_CAN0 IF1_MSK2: MDIR Position */ -#define C_CAN0_IF1_MSK2_MDIR_Msk (0x01UL << C_CAN0_IF1_MSK2_MDIR_Pos) /*!< C_CAN0 IF1_MSK2: MDIR Mask */ -#define C_CAN0_IF1_MSK2_MXTD_Pos 15 /*!< C_CAN0 IF1_MSK2: MXTD Position */ -#define C_CAN0_IF1_MSK2_MXTD_Msk (0x01UL << C_CAN0_IF1_MSK2_MXTD_Pos) /*!< C_CAN0 IF1_MSK2: MXTD Mask */ - -// ------------------------------------- C_CAN0_IF1_ARB1 ---------------------------------------- -#define C_CAN0_IF1_ARB1_ID15_0_Pos 0 /*!< C_CAN0 IF1_ARB1: ID15_0 Position */ -#define C_CAN0_IF1_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN0_IF1_ARB1_ID15_0_Pos) /*!< C_CAN0 IF1_ARB1: ID15_0 Mask */ - -// ------------------------------------- C_CAN0_IF1_ARB2 ---------------------------------------- -#define C_CAN0_IF1_ARB2_ID28_16_Pos 0 /*!< C_CAN0 IF1_ARB2: ID28_16 Position */ -#define C_CAN0_IF1_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN0_IF1_ARB2_ID28_16_Pos) /*!< C_CAN0 IF1_ARB2: ID28_16 Mask */ -#define C_CAN0_IF1_ARB2_DIR_Pos 13 /*!< C_CAN0 IF1_ARB2: DIR Position */ -#define C_CAN0_IF1_ARB2_DIR_Msk (0x01UL << C_CAN0_IF1_ARB2_DIR_Pos) /*!< C_CAN0 IF1_ARB2: DIR Mask */ -#define C_CAN0_IF1_ARB2_XTD_Pos 14 /*!< C_CAN0 IF1_ARB2: XTD Position */ -#define C_CAN0_IF1_ARB2_XTD_Msk (0x01UL << C_CAN0_IF1_ARB2_XTD_Pos) /*!< C_CAN0 IF1_ARB2: XTD Mask */ -#define C_CAN0_IF1_ARB2_MSGVAL_Pos 15 /*!< C_CAN0 IF1_ARB2: MSGVAL Position */ -#define C_CAN0_IF1_ARB2_MSGVAL_Msk (0x01UL << C_CAN0_IF1_ARB2_MSGVAL_Pos) /*!< C_CAN0 IF1_ARB2: MSGVAL Mask */ - -// ------------------------------------ C_CAN0_IF1_MCTRL ---------------------------------------- -#define C_CAN0_IF1_MCTRL_DLC3_0_Pos 0 /*!< C_CAN0 IF1_MCTRL: DLC3_0 Position */ -#define C_CAN0_IF1_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN0_IF1_MCTRL_DLC3_0_Pos) /*!< C_CAN0 IF1_MCTRL: DLC3_0 Mask */ -#define C_CAN0_IF1_MCTRL_EOB_Pos 7 /*!< C_CAN0 IF1_MCTRL: EOB Position */ -#define C_CAN0_IF1_MCTRL_EOB_Msk (0x01UL << C_CAN0_IF1_MCTRL_EOB_Pos) /*!< C_CAN0 IF1_MCTRL: EOB Mask */ -#define C_CAN0_IF1_MCTRL_TXRQST_Pos 8 /*!< C_CAN0 IF1_MCTRL: TXRQST Position */ -#define C_CAN0_IF1_MCTRL_TXRQST_Msk (0x01UL << C_CAN0_IF1_MCTRL_TXRQST_Pos) /*!< C_CAN0 IF1_MCTRL: TXRQST Mask */ -#define C_CAN0_IF1_MCTRL_RMTEN_Pos 9 /*!< C_CAN0 IF1_MCTRL: RMTEN Position */ -#define C_CAN0_IF1_MCTRL_RMTEN_Msk (0x01UL << C_CAN0_IF1_MCTRL_RMTEN_Pos) /*!< C_CAN0 IF1_MCTRL: RMTEN Mask */ -#define C_CAN0_IF1_MCTRL_RXIE_Pos 10 /*!< C_CAN0 IF1_MCTRL: RXIE Position */ -#define C_CAN0_IF1_MCTRL_RXIE_Msk (0x01UL << C_CAN0_IF1_MCTRL_RXIE_Pos) /*!< C_CAN0 IF1_MCTRL: RXIE Mask */ -#define C_CAN0_IF1_MCTRL_TXIE_Pos 11 /*!< C_CAN0 IF1_MCTRL: TXIE Position */ -#define C_CAN0_IF1_MCTRL_TXIE_Msk (0x01UL << C_CAN0_IF1_MCTRL_TXIE_Pos) /*!< C_CAN0 IF1_MCTRL: TXIE Mask */ -#define C_CAN0_IF1_MCTRL_UMASK_Pos 12 /*!< C_CAN0 IF1_MCTRL: UMASK Position */ -#define C_CAN0_IF1_MCTRL_UMASK_Msk (0x01UL << C_CAN0_IF1_MCTRL_UMASK_Pos) /*!< C_CAN0 IF1_MCTRL: UMASK Mask */ -#define C_CAN0_IF1_MCTRL_INTPND_Pos 13 /*!< C_CAN0 IF1_MCTRL: INTPND Position */ -#define C_CAN0_IF1_MCTRL_INTPND_Msk (0x01UL << C_CAN0_IF1_MCTRL_INTPND_Pos) /*!< C_CAN0 IF1_MCTRL: INTPND Mask */ -#define C_CAN0_IF1_MCTRL_MSGLST_Pos 14 /*!< C_CAN0 IF1_MCTRL: MSGLST Position */ -#define C_CAN0_IF1_MCTRL_MSGLST_Msk (0x01UL << C_CAN0_IF1_MCTRL_MSGLST_Pos) /*!< C_CAN0 IF1_MCTRL: MSGLST Mask */ -#define C_CAN0_IF1_MCTRL_NEWDAT_Pos 15 /*!< C_CAN0 IF1_MCTRL: NEWDAT Position */ -#define C_CAN0_IF1_MCTRL_NEWDAT_Msk (0x01UL << C_CAN0_IF1_MCTRL_NEWDAT_Pos) /*!< C_CAN0 IF1_MCTRL: NEWDAT Mask */ - -// ------------------------------------- C_CAN0_IF1_DA1 ----------------------------------------- -#define C_CAN0_IF1_DA1_DATA0_Pos 0 /*!< C_CAN0 IF1_DA1: DATA0 Position */ -#define C_CAN0_IF1_DA1_DATA0_Msk (0x000000ffUL << C_CAN0_IF1_DA1_DATA0_Pos) /*!< C_CAN0 IF1_DA1: DATA0 Mask */ -#define C_CAN0_IF1_DA1_DATA1_Pos 8 /*!< C_CAN0 IF1_DA1: DATA1 Position */ -#define C_CAN0_IF1_DA1_DATA1_Msk (0x000000ffUL << C_CAN0_IF1_DA1_DATA1_Pos) /*!< C_CAN0 IF1_DA1: DATA1 Mask */ - -// ------------------------------------- C_CAN0_IF1_DA2 ----------------------------------------- -#define C_CAN0_IF1_DA2_DATA2_Pos 0 /*!< C_CAN0 IF1_DA2: DATA2 Position */ -#define C_CAN0_IF1_DA2_DATA2_Msk (0x000000ffUL << C_CAN0_IF1_DA2_DATA2_Pos) /*!< C_CAN0 IF1_DA2: DATA2 Mask */ -#define C_CAN0_IF1_DA2_DATA3_Pos 8 /*!< C_CAN0 IF1_DA2: DATA3 Position */ -#define C_CAN0_IF1_DA2_DATA3_Msk (0x000000ffUL << C_CAN0_IF1_DA2_DATA3_Pos) /*!< C_CAN0 IF1_DA2: DATA3 Mask */ - -// ------------------------------------- C_CAN0_IF1_DB1 ----------------------------------------- -#define C_CAN0_IF1_DB1_DATA4_Pos 0 /*!< C_CAN0 IF1_DB1: DATA4 Position */ -#define C_CAN0_IF1_DB1_DATA4_Msk (0x000000ffUL << C_CAN0_IF1_DB1_DATA4_Pos) /*!< C_CAN0 IF1_DB1: DATA4 Mask */ -#define C_CAN0_IF1_DB1_DATA5_Pos 8 /*!< C_CAN0 IF1_DB1: DATA5 Position */ -#define C_CAN0_IF1_DB1_DATA5_Msk (0x000000ffUL << C_CAN0_IF1_DB1_DATA5_Pos) /*!< C_CAN0 IF1_DB1: DATA5 Mask */ - -// ------------------------------------- C_CAN0_IF1_DB2 ----------------------------------------- -#define C_CAN0_IF1_DB2_DATA6_Pos 0 /*!< C_CAN0 IF1_DB2: DATA6 Position */ -#define C_CAN0_IF1_DB2_DATA6_Msk (0x000000ffUL << C_CAN0_IF1_DB2_DATA6_Pos) /*!< C_CAN0 IF1_DB2: DATA6 Mask */ -#define C_CAN0_IF1_DB2_DATA7_Pos 8 /*!< C_CAN0 IF1_DB2: DATA7 Position */ -#define C_CAN0_IF1_DB2_DATA7_Msk (0x000000ffUL << C_CAN0_IF1_DB2_DATA7_Pos) /*!< C_CAN0 IF1_DB2: DATA7 Mask */ - -// ------------------------------------ C_CAN0_IF2_CMDREQ --------------------------------------- -#define C_CAN0_IF2_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN0 IF2_CMDREQ: MESSNUM Position */ -#define C_CAN0_IF2_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN0_IF2_CMDREQ_MESSNUM_Pos) /*!< C_CAN0 IF2_CMDREQ: MESSNUM Mask */ -#define C_CAN0_IF2_CMDREQ_BUSY_Pos 15 /*!< C_CAN0 IF2_CMDREQ: BUSY Position */ -#define C_CAN0_IF2_CMDREQ_BUSY_Msk (0x01UL << C_CAN0_IF2_CMDREQ_BUSY_Pos) /*!< C_CAN0 IF2_CMDREQ: BUSY Mask */ - -// ----------------------------------- C_CAN0_IF2_CMDMSK_R -------------------------------------- -#define C_CAN0_IF2_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN0 IF2_CMDMSK_R: DATA_B Position */ -#define C_CAN0_IF2_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_B_Pos) /*!< C_CAN0 IF2_CMDMSK_R: DATA_B Mask */ -#define C_CAN0_IF2_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN0 IF2_CMDMSK_R: DATA_A Position */ -#define C_CAN0_IF2_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_A_Pos) /*!< C_CAN0 IF2_CMDMSK_R: DATA_A Mask */ -#define C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN0 IF2_CMDMSK_R: NEWDAT Position */ -#define C_CAN0_IF2_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN0 IF2_CMDMSK_R: NEWDAT Mask */ -#define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN0 IF2_CMDMSK_R: CLRINTPND Position */ -#define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN0 IF2_CMDMSK_R: CLRINTPND Mask */ -#define C_CAN0_IF2_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN0 IF2_CMDMSK_R: CTRL Position */ -#define C_CAN0_IF2_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_CTRL_Pos) /*!< C_CAN0 IF2_CMDMSK_R: CTRL Mask */ -#define C_CAN0_IF2_CMDMSK_R_ARB_Pos 5 /*!< C_CAN0 IF2_CMDMSK_R: ARB Position */ -#define C_CAN0_IF2_CMDMSK_R_ARB_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_ARB_Pos) /*!< C_CAN0 IF2_CMDMSK_R: ARB Mask */ -#define C_CAN0_IF2_CMDMSK_R_MASK_Pos 6 /*!< C_CAN0 IF2_CMDMSK_R: MASK Position */ -#define C_CAN0_IF2_CMDMSK_R_MASK_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_MASK_Pos) /*!< C_CAN0 IF2_CMDMSK_R: MASK Mask */ -#define C_CAN0_IF2_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN0 IF2_CMDMSK_R: WR_RD Position */ -#define C_CAN0_IF2_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_WR_RD_Pos) /*!< C_CAN0 IF2_CMDMSK_R: WR_RD Mask */ - -// ----------------------------------- C_CAN0_IF2_CMDMSK_W -------------------------------------- -#define C_CAN0_IF2_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN0 IF2_CMDMSK_W: DATA_B Position */ -#define C_CAN0_IF2_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_B_Pos) /*!< C_CAN0 IF2_CMDMSK_W: DATA_B Mask */ -#define C_CAN0_IF2_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN0 IF2_CMDMSK_W: DATA_A Position */ -#define C_CAN0_IF2_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_A_Pos) /*!< C_CAN0 IF2_CMDMSK_W: DATA_A Mask */ -#define C_CAN0_IF2_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN0 IF2_CMDMSK_W: TXRQST Position */ -#define C_CAN0_IF2_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_TXRQST_Pos) /*!< C_CAN0 IF2_CMDMSK_W: TXRQST Mask */ -#define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN0 IF2_CMDMSK_W: CLRINTPND Position */ -#define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN0 IF2_CMDMSK_W: CLRINTPND Mask */ -#define C_CAN0_IF2_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN0 IF2_CMDMSK_W: CTRL Position */ -#define C_CAN0_IF2_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_CTRL_Pos) /*!< C_CAN0 IF2_CMDMSK_W: CTRL Mask */ -#define C_CAN0_IF2_CMDMSK_W_ARB_Pos 5 /*!< C_CAN0 IF2_CMDMSK_W: ARB Position */ -#define C_CAN0_IF2_CMDMSK_W_ARB_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_ARB_Pos) /*!< C_CAN0 IF2_CMDMSK_W: ARB Mask */ -#define C_CAN0_IF2_CMDMSK_W_MASK_Pos 6 /*!< C_CAN0 IF2_CMDMSK_W: MASK Position */ -#define C_CAN0_IF2_CMDMSK_W_MASK_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_MASK_Pos) /*!< C_CAN0 IF2_CMDMSK_W: MASK Mask */ -#define C_CAN0_IF2_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN0 IF2_CMDMSK_W: WR_RD Position */ -#define C_CAN0_IF2_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_WR_RD_Pos) /*!< C_CAN0 IF2_CMDMSK_W: WR_RD Mask */ - -// ------------------------------------- C_CAN0_IF2_MSK1 ---------------------------------------- -#define C_CAN0_IF2_MSK1_MSK15_0_Pos 0 /*!< C_CAN0 IF2_MSK1: MSK15_0 Position */ -#define C_CAN0_IF2_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN0_IF2_MSK1_MSK15_0_Pos) /*!< C_CAN0 IF2_MSK1: MSK15_0 Mask */ - -// ------------------------------------- C_CAN0_IF2_MSK2 ---------------------------------------- -#define C_CAN0_IF2_MSK2_MSK28_16_Pos 0 /*!< C_CAN0 IF2_MSK2: MSK28_16 Position */ -#define C_CAN0_IF2_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN0_IF2_MSK2_MSK28_16_Pos) /*!< C_CAN0 IF2_MSK2: MSK28_16 Mask */ -#define C_CAN0_IF2_MSK2_MDIR_Pos 14 /*!< C_CAN0 IF2_MSK2: MDIR Position */ -#define C_CAN0_IF2_MSK2_MDIR_Msk (0x01UL << C_CAN0_IF2_MSK2_MDIR_Pos) /*!< C_CAN0 IF2_MSK2: MDIR Mask */ -#define C_CAN0_IF2_MSK2_MXTD_Pos 15 /*!< C_CAN0 IF2_MSK2: MXTD Position */ -#define C_CAN0_IF2_MSK2_MXTD_Msk (0x01UL << C_CAN0_IF2_MSK2_MXTD_Pos) /*!< C_CAN0 IF2_MSK2: MXTD Mask */ - -// ------------------------------------- C_CAN0_IF2_ARB1 ---------------------------------------- -#define C_CAN0_IF2_ARB1_ID15_0_Pos 0 /*!< C_CAN0 IF2_ARB1: ID15_0 Position */ -#define C_CAN0_IF2_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN0_IF2_ARB1_ID15_0_Pos) /*!< C_CAN0 IF2_ARB1: ID15_0 Mask */ - -// ------------------------------------- C_CAN0_IF2_ARB2 ---------------------------------------- -#define C_CAN0_IF2_ARB2_ID28_16_Pos 0 /*!< C_CAN0 IF2_ARB2: ID28_16 Position */ -#define C_CAN0_IF2_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN0_IF2_ARB2_ID28_16_Pos) /*!< C_CAN0 IF2_ARB2: ID28_16 Mask */ -#define C_CAN0_IF2_ARB2_DIR_Pos 13 /*!< C_CAN0 IF2_ARB2: DIR Position */ -#define C_CAN0_IF2_ARB2_DIR_Msk (0x01UL << C_CAN0_IF2_ARB2_DIR_Pos) /*!< C_CAN0 IF2_ARB2: DIR Mask */ -#define C_CAN0_IF2_ARB2_XTD_Pos 14 /*!< C_CAN0 IF2_ARB2: XTD Position */ -#define C_CAN0_IF2_ARB2_XTD_Msk (0x01UL << C_CAN0_IF2_ARB2_XTD_Pos) /*!< C_CAN0 IF2_ARB2: XTD Mask */ -#define C_CAN0_IF2_ARB2_MSGVAL_Pos 15 /*!< C_CAN0 IF2_ARB2: MSGVAL Position */ -#define C_CAN0_IF2_ARB2_MSGVAL_Msk (0x01UL << C_CAN0_IF2_ARB2_MSGVAL_Pos) /*!< C_CAN0 IF2_ARB2: MSGVAL Mask */ - -// ------------------------------------ C_CAN0_IF2_MCTRL ---------------------------------------- -#define C_CAN0_IF2_MCTRL_DLC3_0_Pos 0 /*!< C_CAN0 IF2_MCTRL: DLC3_0 Position */ -#define C_CAN0_IF2_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN0_IF2_MCTRL_DLC3_0_Pos) /*!< C_CAN0 IF2_MCTRL: DLC3_0 Mask */ -#define C_CAN0_IF2_MCTRL_EOB_Pos 7 /*!< C_CAN0 IF2_MCTRL: EOB Position */ -#define C_CAN0_IF2_MCTRL_EOB_Msk (0x01UL << C_CAN0_IF2_MCTRL_EOB_Pos) /*!< C_CAN0 IF2_MCTRL: EOB Mask */ -#define C_CAN0_IF2_MCTRL_TXRQST_Pos 8 /*!< C_CAN0 IF2_MCTRL: TXRQST Position */ -#define C_CAN0_IF2_MCTRL_TXRQST_Msk (0x01UL << C_CAN0_IF2_MCTRL_TXRQST_Pos) /*!< C_CAN0 IF2_MCTRL: TXRQST Mask */ -#define C_CAN0_IF2_MCTRL_RMTEN_Pos 9 /*!< C_CAN0 IF2_MCTRL: RMTEN Position */ -#define C_CAN0_IF2_MCTRL_RMTEN_Msk (0x01UL << C_CAN0_IF2_MCTRL_RMTEN_Pos) /*!< C_CAN0 IF2_MCTRL: RMTEN Mask */ -#define C_CAN0_IF2_MCTRL_RXIE_Pos 10 /*!< C_CAN0 IF2_MCTRL: RXIE Position */ -#define C_CAN0_IF2_MCTRL_RXIE_Msk (0x01UL << C_CAN0_IF2_MCTRL_RXIE_Pos) /*!< C_CAN0 IF2_MCTRL: RXIE Mask */ -#define C_CAN0_IF2_MCTRL_TXIE_Pos 11 /*!< C_CAN0 IF2_MCTRL: TXIE Position */ -#define C_CAN0_IF2_MCTRL_TXIE_Msk (0x01UL << C_CAN0_IF2_MCTRL_TXIE_Pos) /*!< C_CAN0 IF2_MCTRL: TXIE Mask */ -#define C_CAN0_IF2_MCTRL_UMASK_Pos 12 /*!< C_CAN0 IF2_MCTRL: UMASK Position */ -#define C_CAN0_IF2_MCTRL_UMASK_Msk (0x01UL << C_CAN0_IF2_MCTRL_UMASK_Pos) /*!< C_CAN0 IF2_MCTRL: UMASK Mask */ -#define C_CAN0_IF2_MCTRL_INTPND_Pos 13 /*!< C_CAN0 IF2_MCTRL: INTPND Position */ -#define C_CAN0_IF2_MCTRL_INTPND_Msk (0x01UL << C_CAN0_IF2_MCTRL_INTPND_Pos) /*!< C_CAN0 IF2_MCTRL: INTPND Mask */ -#define C_CAN0_IF2_MCTRL_MSGLST_Pos 14 /*!< C_CAN0 IF2_MCTRL: MSGLST Position */ -#define C_CAN0_IF2_MCTRL_MSGLST_Msk (0x01UL << C_CAN0_IF2_MCTRL_MSGLST_Pos) /*!< C_CAN0 IF2_MCTRL: MSGLST Mask */ -#define C_CAN0_IF2_MCTRL_NEWDAT_Pos 15 /*!< C_CAN0 IF2_MCTRL: NEWDAT Position */ -#define C_CAN0_IF2_MCTRL_NEWDAT_Msk (0x01UL << C_CAN0_IF2_MCTRL_NEWDAT_Pos) /*!< C_CAN0 IF2_MCTRL: NEWDAT Mask */ - -// ------------------------------------- C_CAN0_IF2_DA1 ----------------------------------------- -#define C_CAN0_IF2_DA1_DATA0_Pos 0 /*!< C_CAN0 IF2_DA1: DATA0 Position */ -#define C_CAN0_IF2_DA1_DATA0_Msk (0x000000ffUL << C_CAN0_IF2_DA1_DATA0_Pos) /*!< C_CAN0 IF2_DA1: DATA0 Mask */ -#define C_CAN0_IF2_DA1_DATA1_Pos 8 /*!< C_CAN0 IF2_DA1: DATA1 Position */ -#define C_CAN0_IF2_DA1_DATA1_Msk (0x000000ffUL << C_CAN0_IF2_DA1_DATA1_Pos) /*!< C_CAN0 IF2_DA1: DATA1 Mask */ - -// ------------------------------------- C_CAN0_IF2_DA2 ----------------------------------------- -#define C_CAN0_IF2_DA2_DATA2_Pos 0 /*!< C_CAN0 IF2_DA2: DATA2 Position */ -#define C_CAN0_IF2_DA2_DATA2_Msk (0x000000ffUL << C_CAN0_IF2_DA2_DATA2_Pos) /*!< C_CAN0 IF2_DA2: DATA2 Mask */ -#define C_CAN0_IF2_DA2_DATA3_Pos 8 /*!< C_CAN0 IF2_DA2: DATA3 Position */ -#define C_CAN0_IF2_DA2_DATA3_Msk (0x000000ffUL << C_CAN0_IF2_DA2_DATA3_Pos) /*!< C_CAN0 IF2_DA2: DATA3 Mask */ - -// ------------------------------------- C_CAN0_IF2_DB1 ----------------------------------------- -#define C_CAN0_IF2_DB1_DATA4_Pos 0 /*!< C_CAN0 IF2_DB1: DATA4 Position */ -#define C_CAN0_IF2_DB1_DATA4_Msk (0x000000ffUL << C_CAN0_IF2_DB1_DATA4_Pos) /*!< C_CAN0 IF2_DB1: DATA4 Mask */ -#define C_CAN0_IF2_DB1_DATA5_Pos 8 /*!< C_CAN0 IF2_DB1: DATA5 Position */ -#define C_CAN0_IF2_DB1_DATA5_Msk (0x000000ffUL << C_CAN0_IF2_DB1_DATA5_Pos) /*!< C_CAN0 IF2_DB1: DATA5 Mask */ - -// ------------------------------------- C_CAN0_IF2_DB2 ----------------------------------------- -#define C_CAN0_IF2_DB2_DATA6_Pos 0 /*!< C_CAN0 IF2_DB2: DATA6 Position */ -#define C_CAN0_IF2_DB2_DATA6_Msk (0x000000ffUL << C_CAN0_IF2_DB2_DATA6_Pos) /*!< C_CAN0 IF2_DB2: DATA6 Mask */ -#define C_CAN0_IF2_DB2_DATA7_Pos 8 /*!< C_CAN0 IF2_DB2: DATA7 Position */ -#define C_CAN0_IF2_DB2_DATA7_Msk (0x000000ffUL << C_CAN0_IF2_DB2_DATA7_Pos) /*!< C_CAN0 IF2_DB2: DATA7 Mask */ - -// -------------------------------------- C_CAN0_TXREQ1 ----------------------------------------- -#define C_CAN0_TXREQ1_TXRQST16_1_Pos 0 /*!< C_CAN0 TXREQ1: TXRQST16_1 Position */ -#define C_CAN0_TXREQ1_TXRQST16_1_Msk (0x0000ffffUL << C_CAN0_TXREQ1_TXRQST16_1_Pos) /*!< C_CAN0 TXREQ1: TXRQST16_1 Mask */ - -// -------------------------------------- C_CAN0_TXREQ2 ----------------------------------------- -#define C_CAN0_TXREQ2_TXRQST32_17_Pos 0 /*!< C_CAN0 TXREQ2: TXRQST32_17 Position */ -#define C_CAN0_TXREQ2_TXRQST32_17_Msk (0x0000ffffUL << C_CAN0_TXREQ2_TXRQST32_17_Pos) /*!< C_CAN0 TXREQ2: TXRQST32_17 Mask */ - -// --------------------------------------- C_CAN0_ND1 ------------------------------------------- -#define C_CAN0_ND1_NEWDAT16_1_Pos 0 /*!< C_CAN0 ND1: NEWDAT16_1 Position */ -#define C_CAN0_ND1_NEWDAT16_1_Msk (0x0000ffffUL << C_CAN0_ND1_NEWDAT16_1_Pos) /*!< C_CAN0 ND1: NEWDAT16_1 Mask */ - -// --------------------------------------- C_CAN0_ND2 ------------------------------------------- -#define C_CAN0_ND2_NEWDAT32_17_Pos 0 /*!< C_CAN0 ND2: NEWDAT32_17 Position */ -#define C_CAN0_ND2_NEWDAT32_17_Msk (0x0000ffffUL << C_CAN0_ND2_NEWDAT32_17_Pos) /*!< C_CAN0 ND2: NEWDAT32_17 Mask */ - -// --------------------------------------- C_CAN0_IR1 ------------------------------------------- -#define C_CAN0_IR1_INTPND16_1_Pos 0 /*!< C_CAN0 IR1: INTPND16_1 Position */ -#define C_CAN0_IR1_INTPND16_1_Msk (0x0000ffffUL << C_CAN0_IR1_INTPND16_1_Pos) /*!< C_CAN0 IR1: INTPND16_1 Mask */ - -// --------------------------------------- C_CAN0_IR2 ------------------------------------------- -#define C_CAN0_IR2_INTPND32_17_Pos 0 /*!< C_CAN0 IR2: INTPND32_17 Position */ -#define C_CAN0_IR2_INTPND32_17_Msk (0x0000ffffUL << C_CAN0_IR2_INTPND32_17_Pos) /*!< C_CAN0 IR2: INTPND32_17 Mask */ - -// -------------------------------------- C_CAN0_MSGV1 ------------------------------------------ -#define C_CAN0_MSGV1_MSGVAL16_1_Pos 0 /*!< C_CAN0 MSGV1: MSGVAL16_1 Position */ -#define C_CAN0_MSGV1_MSGVAL16_1_Msk (0x0000ffffUL << C_CAN0_MSGV1_MSGVAL16_1_Pos) /*!< C_CAN0 MSGV1: MSGVAL16_1 Mask */ - -// -------------------------------------- C_CAN0_MSGV2 ------------------------------------------ -#define C_CAN0_MSGV2_MSGVAL32_17_Pos 0 /*!< C_CAN0 MSGV2: MSGVAL32_17 Position */ -#define C_CAN0_MSGV2_MSGVAL32_17_Msk (0x0000ffffUL << C_CAN0_MSGV2_MSGVAL32_17_Pos) /*!< C_CAN0 MSGV2: MSGVAL32_17 Mask */ - -// -------------------------------------- C_CAN0_CLKDIV ----------------------------------------- -#define C_CAN0_CLKDIV_CLKDIVVAL_Pos 0 /*!< C_CAN0 CLKDIV: CLKDIVVAL Position */ -#define C_CAN0_CLKDIV_CLKDIVVAL_Msk (0x0fUL << C_CAN0_CLKDIV_CLKDIVVAL_Pos) /*!< C_CAN0 CLKDIV: CLKDIVVAL Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- ADC0 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ----------------------------------------- ADC0_CR -------------------------------------------- -#define ADC0_CR_SEL_Pos 0 /*!< ADC0 CR: SEL Position */ -#define ADC0_CR_SEL_Msk (0x000000ffUL << ADC0_CR_SEL_Pos) /*!< ADC0 CR: SEL Mask */ -#define ADC0_CR_CLKDIV_Pos 8 /*!< ADC0 CR: CLKDIV Position */ -#define ADC0_CR_CLKDIV_Msk (0x000000ffUL << ADC0_CR_CLKDIV_Pos) /*!< ADC0 CR: CLKDIV Mask */ -#define ADC0_CR_BURST_Pos 16 /*!< ADC0 CR: BURST Position */ -#define ADC0_CR_BURST_Msk (0x01UL << ADC0_CR_BURST_Pos) /*!< ADC0 CR: BURST Mask */ -#define ADC0_CR_CLKS_Pos 17 /*!< ADC0 CR: CLKS Position */ -#define ADC0_CR_CLKS_Msk (0x07UL << ADC0_CR_CLKS_Pos) /*!< ADC0 CR: CLKS Mask */ -#define ADC0_CR_PDN_Pos 21 /*!< ADC0 CR: PDN Position */ -#define ADC0_CR_PDN_Msk (0x01UL << ADC0_CR_PDN_Pos) /*!< ADC0 CR: PDN Mask */ -#define ADC0_CR_START_Pos 24 /*!< ADC0 CR: START Position */ -#define ADC0_CR_START_Msk (0x07UL << ADC0_CR_START_Pos) /*!< ADC0 CR: START Mask */ -#define ADC0_CR_EDGE_Pos 27 /*!< ADC0 CR: EDGE Position */ -#define ADC0_CR_EDGE_Msk (0x01UL << ADC0_CR_EDGE_Pos) /*!< ADC0 CR: EDGE Mask */ - -// ---------------------------------------- ADC0_GDR -------------------------------------------- -#define ADC0_GDR_V_VREF_Pos 6 /*!< ADC0 GDR: V_VREF Position */ -#define ADC0_GDR_V_VREF_Msk (0x000003ffUL << ADC0_GDR_V_VREF_Pos) /*!< ADC0 GDR: V_VREF Mask */ -#define ADC0_GDR_CHN_Pos 24 /*!< ADC0 GDR: CHN Position */ -#define ADC0_GDR_CHN_Msk (0x07UL << ADC0_GDR_CHN_Pos) /*!< ADC0 GDR: CHN Mask */ -#define ADC0_GDR_OVERRUN_Pos 30 /*!< ADC0 GDR: OVERRUN Position */ -#define ADC0_GDR_OVERRUN_Msk (0x01UL << ADC0_GDR_OVERRUN_Pos) /*!< ADC0 GDR: OVERRUN Mask */ -#define ADC0_GDR_DONE_Pos 31 /*!< ADC0 GDR: DONE Position */ -#define ADC0_GDR_DONE_Msk (0x01UL << ADC0_GDR_DONE_Pos) /*!< ADC0 GDR: DONE Mask */ - -// --------------------------------------- ADC0_INTEN ------------------------------------------- -#define ADC0_INTEN_ADINTEN_Pos 0 /*!< ADC0 INTEN: ADINTEN Position */ -#define ADC0_INTEN_ADINTEN_Msk (0x000000ffUL << ADC0_INTEN_ADINTEN_Pos) /*!< ADC0 INTEN: ADINTEN Mask */ -#define ADC0_INTEN_ADGINTEN_Pos 8 /*!< ADC0 INTEN: ADGINTEN Position */ -#define ADC0_INTEN_ADGINTEN_Msk (0x01UL << ADC0_INTEN_ADGINTEN_Pos) /*!< ADC0 INTEN: ADGINTEN Mask */ - -// ---------------------------------------- ADC0_DR0 -------------------------------------------- -#define ADC0_DR0_V_VREF_Pos 6 /*!< ADC0 DR0: V_VREF Position */ -#define ADC0_DR0_V_VREF_Msk (0x000003ffUL << ADC0_DR0_V_VREF_Pos) /*!< ADC0 DR0: V_VREF Mask */ -#define ADC0_DR0_OVERRUN_Pos 30 /*!< ADC0 DR0: OVERRUN Position */ -#define ADC0_DR0_OVERRUN_Msk (0x01UL << ADC0_DR0_OVERRUN_Pos) /*!< ADC0 DR0: OVERRUN Mask */ -#define ADC0_DR0_DONE_Pos 31 /*!< ADC0 DR0: DONE Position */ -#define ADC0_DR0_DONE_Msk (0x01UL << ADC0_DR0_DONE_Pos) /*!< ADC0 DR0: DONE Mask */ - -// ---------------------------------------- ADC0_DR1 -------------------------------------------- -#define ADC0_DR1_V_VREF_Pos 6 /*!< ADC0 DR1: V_VREF Position */ -#define ADC0_DR1_V_VREF_Msk (0x000003ffUL << ADC0_DR1_V_VREF_Pos) /*!< ADC0 DR1: V_VREF Mask */ -#define ADC0_DR1_OVERRUN_Pos 30 /*!< ADC0 DR1: OVERRUN Position */ -#define ADC0_DR1_OVERRUN_Msk (0x01UL << ADC0_DR1_OVERRUN_Pos) /*!< ADC0 DR1: OVERRUN Mask */ -#define ADC0_DR1_DONE_Pos 31 /*!< ADC0 DR1: DONE Position */ -#define ADC0_DR1_DONE_Msk (0x01UL << ADC0_DR1_DONE_Pos) /*!< ADC0 DR1: DONE Mask */ - -// ---------------------------------------- ADC0_DR2 -------------------------------------------- -#define ADC0_DR2_V_VREF_Pos 6 /*!< ADC0 DR2: V_VREF Position */ -#define ADC0_DR2_V_VREF_Msk (0x000003ffUL << ADC0_DR2_V_VREF_Pos) /*!< ADC0 DR2: V_VREF Mask */ -#define ADC0_DR2_OVERRUN_Pos 30 /*!< ADC0 DR2: OVERRUN Position */ -#define ADC0_DR2_OVERRUN_Msk (0x01UL << ADC0_DR2_OVERRUN_Pos) /*!< ADC0 DR2: OVERRUN Mask */ -#define ADC0_DR2_DONE_Pos 31 /*!< ADC0 DR2: DONE Position */ -#define ADC0_DR2_DONE_Msk (0x01UL << ADC0_DR2_DONE_Pos) /*!< ADC0 DR2: DONE Mask */ - -// ---------------------------------------- ADC0_DR3 -------------------------------------------- -#define ADC0_DR3_V_VREF_Pos 6 /*!< ADC0 DR3: V_VREF Position */ -#define ADC0_DR3_V_VREF_Msk (0x000003ffUL << ADC0_DR3_V_VREF_Pos) /*!< ADC0 DR3: V_VREF Mask */ -#define ADC0_DR3_OVERRUN_Pos 30 /*!< ADC0 DR3: OVERRUN Position */ -#define ADC0_DR3_OVERRUN_Msk (0x01UL << ADC0_DR3_OVERRUN_Pos) /*!< ADC0 DR3: OVERRUN Mask */ -#define ADC0_DR3_DONE_Pos 31 /*!< ADC0 DR3: DONE Position */ -#define ADC0_DR3_DONE_Msk (0x01UL << ADC0_DR3_DONE_Pos) /*!< ADC0 DR3: DONE Mask */ - -// ---------------------------------------- ADC0_DR4 -------------------------------------------- -#define ADC0_DR4_V_VREF_Pos 6 /*!< ADC0 DR4: V_VREF Position */ -#define ADC0_DR4_V_VREF_Msk (0x000003ffUL << ADC0_DR4_V_VREF_Pos) /*!< ADC0 DR4: V_VREF Mask */ -#define ADC0_DR4_OVERRUN_Pos 30 /*!< ADC0 DR4: OVERRUN Position */ -#define ADC0_DR4_OVERRUN_Msk (0x01UL << ADC0_DR4_OVERRUN_Pos) /*!< ADC0 DR4: OVERRUN Mask */ -#define ADC0_DR4_DONE_Pos 31 /*!< ADC0 DR4: DONE Position */ -#define ADC0_DR4_DONE_Msk (0x01UL << ADC0_DR4_DONE_Pos) /*!< ADC0 DR4: DONE Mask */ - -// ---------------------------------------- ADC0_DR5 -------------------------------------------- -#define ADC0_DR5_V_VREF_Pos 6 /*!< ADC0 DR5: V_VREF Position */ -#define ADC0_DR5_V_VREF_Msk (0x000003ffUL << ADC0_DR5_V_VREF_Pos) /*!< ADC0 DR5: V_VREF Mask */ -#define ADC0_DR5_OVERRUN_Pos 30 /*!< ADC0 DR5: OVERRUN Position */ -#define ADC0_DR5_OVERRUN_Msk (0x01UL << ADC0_DR5_OVERRUN_Pos) /*!< ADC0 DR5: OVERRUN Mask */ -#define ADC0_DR5_DONE_Pos 31 /*!< ADC0 DR5: DONE Position */ -#define ADC0_DR5_DONE_Msk (0x01UL << ADC0_DR5_DONE_Pos) /*!< ADC0 DR5: DONE Mask */ - -// ---------------------------------------- ADC0_DR6 -------------------------------------------- -#define ADC0_DR6_V_VREF_Pos 6 /*!< ADC0 DR6: V_VREF Position */ -#define ADC0_DR6_V_VREF_Msk (0x000003ffUL << ADC0_DR6_V_VREF_Pos) /*!< ADC0 DR6: V_VREF Mask */ -#define ADC0_DR6_OVERRUN_Pos 30 /*!< ADC0 DR6: OVERRUN Position */ -#define ADC0_DR6_OVERRUN_Msk (0x01UL << ADC0_DR6_OVERRUN_Pos) /*!< ADC0 DR6: OVERRUN Mask */ -#define ADC0_DR6_DONE_Pos 31 /*!< ADC0 DR6: DONE Position */ -#define ADC0_DR6_DONE_Msk (0x01UL << ADC0_DR6_DONE_Pos) /*!< ADC0 DR6: DONE Mask */ - -// ---------------------------------------- ADC0_DR7 -------------------------------------------- -#define ADC0_DR7_V_VREF_Pos 6 /*!< ADC0 DR7: V_VREF Position */ -#define ADC0_DR7_V_VREF_Msk (0x000003ffUL << ADC0_DR7_V_VREF_Pos) /*!< ADC0 DR7: V_VREF Mask */ -#define ADC0_DR7_OVERRUN_Pos 30 /*!< ADC0 DR7: OVERRUN Position */ -#define ADC0_DR7_OVERRUN_Msk (0x01UL << ADC0_DR7_OVERRUN_Pos) /*!< ADC0 DR7: OVERRUN Mask */ -#define ADC0_DR7_DONE_Pos 31 /*!< ADC0 DR7: DONE Position */ -#define ADC0_DR7_DONE_Msk (0x01UL << ADC0_DR7_DONE_Pos) /*!< ADC0 DR7: DONE Mask */ - -// ---------------------------------------- ADC0_STAT ------------------------------------------- -#define ADC0_STAT_DONE_Pos 0 /*!< ADC0 STAT: DONE Position */ -#define ADC0_STAT_DONE_Msk (0x000000ffUL << ADC0_STAT_DONE_Pos) /*!< ADC0 STAT: DONE Mask */ -#define ADC0_STAT_OVERUN_Pos 8 /*!< ADC0 STAT: OVERUN Position */ -#define ADC0_STAT_OVERUN_Msk (0x000000ffUL << ADC0_STAT_OVERUN_Pos) /*!< ADC0 STAT: OVERUN Mask */ -#define ADC0_STAT_ADINT_Pos 16 /*!< ADC0 STAT: ADINT Position */ -#define ADC0_STAT_ADINT_Msk (0x01UL << ADC0_STAT_ADINT_Pos) /*!< ADC0 STAT: ADINT Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- ADC1 Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ----------------------------------------- ADC1_CR -------------------------------------------- -#define ADC1_CR_SEL_Pos 0 /*!< ADC1 CR: SEL Position */ -#define ADC1_CR_SEL_Msk (0x000000ffUL << ADC1_CR_SEL_Pos) /*!< ADC1 CR: SEL Mask */ -#define ADC1_CR_CLKDIV_Pos 8 /*!< ADC1 CR: CLKDIV Position */ -#define ADC1_CR_CLKDIV_Msk (0x000000ffUL << ADC1_CR_CLKDIV_Pos) /*!< ADC1 CR: CLKDIV Mask */ -#define ADC1_CR_BURST_Pos 16 /*!< ADC1 CR: BURST Position */ -#define ADC1_CR_BURST_Msk (0x01UL << ADC1_CR_BURST_Pos) /*!< ADC1 CR: BURST Mask */ -#define ADC1_CR_CLKS_Pos 17 /*!< ADC1 CR: CLKS Position */ -#define ADC1_CR_CLKS_Msk (0x07UL << ADC1_CR_CLKS_Pos) /*!< ADC1 CR: CLKS Mask */ -#define ADC1_CR_PDN_Pos 21 /*!< ADC1 CR: PDN Position */ -#define ADC1_CR_PDN_Msk (0x01UL << ADC1_CR_PDN_Pos) /*!< ADC1 CR: PDN Mask */ -#define ADC1_CR_START_Pos 24 /*!< ADC1 CR: START Position */ -#define ADC1_CR_START_Msk (0x07UL << ADC1_CR_START_Pos) /*!< ADC1 CR: START Mask */ -#define ADC1_CR_EDGE_Pos 27 /*!< ADC1 CR: EDGE Position */ -#define ADC1_CR_EDGE_Msk (0x01UL << ADC1_CR_EDGE_Pos) /*!< ADC1 CR: EDGE Mask */ - -// ---------------------------------------- ADC1_GDR -------------------------------------------- -#define ADC1_GDR_V_VREF_Pos 6 /*!< ADC1 GDR: V_VREF Position */ -#define ADC1_GDR_V_VREF_Msk (0x000003ffUL << ADC1_GDR_V_VREF_Pos) /*!< ADC1 GDR: V_VREF Mask */ -#define ADC1_GDR_CHN_Pos 24 /*!< ADC1 GDR: CHN Position */ -#define ADC1_GDR_CHN_Msk (0x07UL << ADC1_GDR_CHN_Pos) /*!< ADC1 GDR: CHN Mask */ -#define ADC1_GDR_OVERRUN_Pos 30 /*!< ADC1 GDR: OVERRUN Position */ -#define ADC1_GDR_OVERRUN_Msk (0x01UL << ADC1_GDR_OVERRUN_Pos) /*!< ADC1 GDR: OVERRUN Mask */ -#define ADC1_GDR_DONE_Pos 31 /*!< ADC1 GDR: DONE Position */ -#define ADC1_GDR_DONE_Msk (0x01UL << ADC1_GDR_DONE_Pos) /*!< ADC1 GDR: DONE Mask */ - -// --------------------------------------- ADC1_INTEN ------------------------------------------- -#define ADC1_INTEN_ADINTEN_Pos 0 /*!< ADC1 INTEN: ADINTEN Position */ -#define ADC1_INTEN_ADINTEN_Msk (0x000000ffUL << ADC1_INTEN_ADINTEN_Pos) /*!< ADC1 INTEN: ADINTEN Mask */ -#define ADC1_INTEN_ADGINTEN_Pos 8 /*!< ADC1 INTEN: ADGINTEN Position */ -#define ADC1_INTEN_ADGINTEN_Msk (0x01UL << ADC1_INTEN_ADGINTEN_Pos) /*!< ADC1 INTEN: ADGINTEN Mask */ - -// ---------------------------------------- ADC1_DR0 -------------------------------------------- -#define ADC1_DR0_V_VREF_Pos 6 /*!< ADC1 DR0: V_VREF Position */ -#define ADC1_DR0_V_VREF_Msk (0x000003ffUL << ADC1_DR0_V_VREF_Pos) /*!< ADC1 DR0: V_VREF Mask */ -#define ADC1_DR0_OVERRUN_Pos 30 /*!< ADC1 DR0: OVERRUN Position */ -#define ADC1_DR0_OVERRUN_Msk (0x01UL << ADC1_DR0_OVERRUN_Pos) /*!< ADC1 DR0: OVERRUN Mask */ -#define ADC1_DR0_DONE_Pos 31 /*!< ADC1 DR0: DONE Position */ -#define ADC1_DR0_DONE_Msk (0x01UL << ADC1_DR0_DONE_Pos) /*!< ADC1 DR0: DONE Mask */ - -// ---------------------------------------- ADC1_DR1 -------------------------------------------- -#define ADC1_DR1_V_VREF_Pos 6 /*!< ADC1 DR1: V_VREF Position */ -#define ADC1_DR1_V_VREF_Msk (0x000003ffUL << ADC1_DR1_V_VREF_Pos) /*!< ADC1 DR1: V_VREF Mask */ -#define ADC1_DR1_OVERRUN_Pos 30 /*!< ADC1 DR1: OVERRUN Position */ -#define ADC1_DR1_OVERRUN_Msk (0x01UL << ADC1_DR1_OVERRUN_Pos) /*!< ADC1 DR1: OVERRUN Mask */ -#define ADC1_DR1_DONE_Pos 31 /*!< ADC1 DR1: DONE Position */ -#define ADC1_DR1_DONE_Msk (0x01UL << ADC1_DR1_DONE_Pos) /*!< ADC1 DR1: DONE Mask */ - -// ---------------------------------------- ADC1_DR2 -------------------------------------------- -#define ADC1_DR2_V_VREF_Pos 6 /*!< ADC1 DR2: V_VREF Position */ -#define ADC1_DR2_V_VREF_Msk (0x000003ffUL << ADC1_DR2_V_VREF_Pos) /*!< ADC1 DR2: V_VREF Mask */ -#define ADC1_DR2_OVERRUN_Pos 30 /*!< ADC1 DR2: OVERRUN Position */ -#define ADC1_DR2_OVERRUN_Msk (0x01UL << ADC1_DR2_OVERRUN_Pos) /*!< ADC1 DR2: OVERRUN Mask */ -#define ADC1_DR2_DONE_Pos 31 /*!< ADC1 DR2: DONE Position */ -#define ADC1_DR2_DONE_Msk (0x01UL << ADC1_DR2_DONE_Pos) /*!< ADC1 DR2: DONE Mask */ - -// ---------------------------------------- ADC1_DR3 -------------------------------------------- -#define ADC1_DR3_V_VREF_Pos 6 /*!< ADC1 DR3: V_VREF Position */ -#define ADC1_DR3_V_VREF_Msk (0x000003ffUL << ADC1_DR3_V_VREF_Pos) /*!< ADC1 DR3: V_VREF Mask */ -#define ADC1_DR3_OVERRUN_Pos 30 /*!< ADC1 DR3: OVERRUN Position */ -#define ADC1_DR3_OVERRUN_Msk (0x01UL << ADC1_DR3_OVERRUN_Pos) /*!< ADC1 DR3: OVERRUN Mask */ -#define ADC1_DR3_DONE_Pos 31 /*!< ADC1 DR3: DONE Position */ -#define ADC1_DR3_DONE_Msk (0x01UL << ADC1_DR3_DONE_Pos) /*!< ADC1 DR3: DONE Mask */ - -// ---------------------------------------- ADC1_DR4 -------------------------------------------- -#define ADC1_DR4_V_VREF_Pos 6 /*!< ADC1 DR4: V_VREF Position */ -#define ADC1_DR4_V_VREF_Msk (0x000003ffUL << ADC1_DR4_V_VREF_Pos) /*!< ADC1 DR4: V_VREF Mask */ -#define ADC1_DR4_OVERRUN_Pos 30 /*!< ADC1 DR4: OVERRUN Position */ -#define ADC1_DR4_OVERRUN_Msk (0x01UL << ADC1_DR4_OVERRUN_Pos) /*!< ADC1 DR4: OVERRUN Mask */ -#define ADC1_DR4_DONE_Pos 31 /*!< ADC1 DR4: DONE Position */ -#define ADC1_DR4_DONE_Msk (0x01UL << ADC1_DR4_DONE_Pos) /*!< ADC1 DR4: DONE Mask */ - -// ---------------------------------------- ADC1_DR5 -------------------------------------------- -#define ADC1_DR5_V_VREF_Pos 6 /*!< ADC1 DR5: V_VREF Position */ -#define ADC1_DR5_V_VREF_Msk (0x000003ffUL << ADC1_DR5_V_VREF_Pos) /*!< ADC1 DR5: V_VREF Mask */ -#define ADC1_DR5_OVERRUN_Pos 30 /*!< ADC1 DR5: OVERRUN Position */ -#define ADC1_DR5_OVERRUN_Msk (0x01UL << ADC1_DR5_OVERRUN_Pos) /*!< ADC1 DR5: OVERRUN Mask */ -#define ADC1_DR5_DONE_Pos 31 /*!< ADC1 DR5: DONE Position */ -#define ADC1_DR5_DONE_Msk (0x01UL << ADC1_DR5_DONE_Pos) /*!< ADC1 DR5: DONE Mask */ - -// ---------------------------------------- ADC1_DR6 -------------------------------------------- -#define ADC1_DR6_V_VREF_Pos 6 /*!< ADC1 DR6: V_VREF Position */ -#define ADC1_DR6_V_VREF_Msk (0x000003ffUL << ADC1_DR6_V_VREF_Pos) /*!< ADC1 DR6: V_VREF Mask */ -#define ADC1_DR6_OVERRUN_Pos 30 /*!< ADC1 DR6: OVERRUN Position */ -#define ADC1_DR6_OVERRUN_Msk (0x01UL << ADC1_DR6_OVERRUN_Pos) /*!< ADC1 DR6: OVERRUN Mask */ -#define ADC1_DR6_DONE_Pos 31 /*!< ADC1 DR6: DONE Position */ -#define ADC1_DR6_DONE_Msk (0x01UL << ADC1_DR6_DONE_Pos) /*!< ADC1 DR6: DONE Mask */ - -// ---------------------------------------- ADC1_DR7 -------------------------------------------- -#define ADC1_DR7_V_VREF_Pos 6 /*!< ADC1 DR7: V_VREF Position */ -#define ADC1_DR7_V_VREF_Msk (0x000003ffUL << ADC1_DR7_V_VREF_Pos) /*!< ADC1 DR7: V_VREF Mask */ -#define ADC1_DR7_OVERRUN_Pos 30 /*!< ADC1 DR7: OVERRUN Position */ -#define ADC1_DR7_OVERRUN_Msk (0x01UL << ADC1_DR7_OVERRUN_Pos) /*!< ADC1 DR7: OVERRUN Mask */ -#define ADC1_DR7_DONE_Pos 31 /*!< ADC1 DR7: DONE Position */ -#define ADC1_DR7_DONE_Msk (0x01UL << ADC1_DR7_DONE_Pos) /*!< ADC1 DR7: DONE Mask */ - -// ---------------------------------------- ADC1_STAT ------------------------------------------- -#define ADC1_STAT_DONE_Pos 0 /*!< ADC1 STAT: DONE Position */ -#define ADC1_STAT_DONE_Msk (0x000000ffUL << ADC1_STAT_DONE_Pos) /*!< ADC1 STAT: DONE Mask */ -#define ADC1_STAT_OVERUN_Pos 8 /*!< ADC1 STAT: OVERUN Position */ -#define ADC1_STAT_OVERUN_Msk (0x000000ffUL << ADC1_STAT_OVERUN_Pos) /*!< ADC1 STAT: OVERUN Mask */ -#define ADC1_STAT_ADINT_Pos 16 /*!< ADC1 STAT: ADINT Position */ -#define ADC1_STAT_ADINT_Msk (0x01UL << ADC1_STAT_ADINT_Pos) /*!< ADC1 STAT: ADINT Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_PORT Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// -------------------------------------- GPIO_PORT_B0 ------------------------------------------ -#define GPIO_PORT_B0_PBYTE_Pos 0 /*!< GPIO_PORT B0: PBYTE Position */ -#define GPIO_PORT_B0_PBYTE_Msk (0x01UL << GPIO_PORT_B0_PBYTE_Pos) /*!< GPIO_PORT B0: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B1 ------------------------------------------ -#define GPIO_PORT_B1_PBYTE_Pos 0 /*!< GPIO_PORT B1: PBYTE Position */ -#define GPIO_PORT_B1_PBYTE_Msk (0x01UL << GPIO_PORT_B1_PBYTE_Pos) /*!< GPIO_PORT B1: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B2 ------------------------------------------ -#define GPIO_PORT_B2_PBYTE_Pos 0 /*!< GPIO_PORT B2: PBYTE Position */ -#define GPIO_PORT_B2_PBYTE_Msk (0x01UL << GPIO_PORT_B2_PBYTE_Pos) /*!< GPIO_PORT B2: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B3 ------------------------------------------ -#define GPIO_PORT_B3_PBYTE_Pos 0 /*!< GPIO_PORT B3: PBYTE Position */ -#define GPIO_PORT_B3_PBYTE_Msk (0x01UL << GPIO_PORT_B3_PBYTE_Pos) /*!< GPIO_PORT B3: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B4 ------------------------------------------ -#define GPIO_PORT_B4_PBYTE_Pos 0 /*!< GPIO_PORT B4: PBYTE Position */ -#define GPIO_PORT_B4_PBYTE_Msk (0x01UL << GPIO_PORT_B4_PBYTE_Pos) /*!< GPIO_PORT B4: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B5 ------------------------------------------ -#define GPIO_PORT_B5_PBYTE_Pos 0 /*!< GPIO_PORT B5: PBYTE Position */ -#define GPIO_PORT_B5_PBYTE_Msk (0x01UL << GPIO_PORT_B5_PBYTE_Pos) /*!< GPIO_PORT B5: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B6 ------------------------------------------ -#define GPIO_PORT_B6_PBYTE_Pos 0 /*!< GPIO_PORT B6: PBYTE Position */ -#define GPIO_PORT_B6_PBYTE_Msk (0x01UL << GPIO_PORT_B6_PBYTE_Pos) /*!< GPIO_PORT B6: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B7 ------------------------------------------ -#define GPIO_PORT_B7_PBYTE_Pos 0 /*!< GPIO_PORT B7: PBYTE Position */ -#define GPIO_PORT_B7_PBYTE_Msk (0x01UL << GPIO_PORT_B7_PBYTE_Pos) /*!< GPIO_PORT B7: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B8 ------------------------------------------ -#define GPIO_PORT_B8_PBYTE_Pos 0 /*!< GPIO_PORT B8: PBYTE Position */ -#define GPIO_PORT_B8_PBYTE_Msk (0x01UL << GPIO_PORT_B8_PBYTE_Pos) /*!< GPIO_PORT B8: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B9 ------------------------------------------ -#define GPIO_PORT_B9_PBYTE_Pos 0 /*!< GPIO_PORT B9: PBYTE Position */ -#define GPIO_PORT_B9_PBYTE_Msk (0x01UL << GPIO_PORT_B9_PBYTE_Pos) /*!< GPIO_PORT B9: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B10 ----------------------------------------- -#define GPIO_PORT_B10_PBYTE_Pos 0 /*!< GPIO_PORT B10: PBYTE Position */ -#define GPIO_PORT_B10_PBYTE_Msk (0x01UL << GPIO_PORT_B10_PBYTE_Pos) /*!< GPIO_PORT B10: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B11 ----------------------------------------- -#define GPIO_PORT_B11_PBYTE_Pos 0 /*!< GPIO_PORT B11: PBYTE Position */ -#define GPIO_PORT_B11_PBYTE_Msk (0x01UL << GPIO_PORT_B11_PBYTE_Pos) /*!< GPIO_PORT B11: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B12 ----------------------------------------- -#define GPIO_PORT_B12_PBYTE_Pos 0 /*!< GPIO_PORT B12: PBYTE Position */ -#define GPIO_PORT_B12_PBYTE_Msk (0x01UL << GPIO_PORT_B12_PBYTE_Pos) /*!< GPIO_PORT B12: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B13 ----------------------------------------- -#define GPIO_PORT_B13_PBYTE_Pos 0 /*!< GPIO_PORT B13: PBYTE Position */ -#define GPIO_PORT_B13_PBYTE_Msk (0x01UL << GPIO_PORT_B13_PBYTE_Pos) /*!< GPIO_PORT B13: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B14 ----------------------------------------- -#define GPIO_PORT_B14_PBYTE_Pos 0 /*!< GPIO_PORT B14: PBYTE Position */ -#define GPIO_PORT_B14_PBYTE_Msk (0x01UL << GPIO_PORT_B14_PBYTE_Pos) /*!< GPIO_PORT B14: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B15 ----------------------------------------- -#define GPIO_PORT_B15_PBYTE_Pos 0 /*!< GPIO_PORT B15: PBYTE Position */ -#define GPIO_PORT_B15_PBYTE_Msk (0x01UL << GPIO_PORT_B15_PBYTE_Pos) /*!< GPIO_PORT B15: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B16 ----------------------------------------- -#define GPIO_PORT_B16_PBYTE_Pos 0 /*!< GPIO_PORT B16: PBYTE Position */ -#define GPIO_PORT_B16_PBYTE_Msk (0x01UL << GPIO_PORT_B16_PBYTE_Pos) /*!< GPIO_PORT B16: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B17 ----------------------------------------- -#define GPIO_PORT_B17_PBYTE_Pos 0 /*!< GPIO_PORT B17: PBYTE Position */ -#define GPIO_PORT_B17_PBYTE_Msk (0x01UL << GPIO_PORT_B17_PBYTE_Pos) /*!< GPIO_PORT B17: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B18 ----------------------------------------- -#define GPIO_PORT_B18_PBYTE_Pos 0 /*!< GPIO_PORT B18: PBYTE Position */ -#define GPIO_PORT_B18_PBYTE_Msk (0x01UL << GPIO_PORT_B18_PBYTE_Pos) /*!< GPIO_PORT B18: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B19 ----------------------------------------- -#define GPIO_PORT_B19_PBYTE_Pos 0 /*!< GPIO_PORT B19: PBYTE Position */ -#define GPIO_PORT_B19_PBYTE_Msk (0x01UL << GPIO_PORT_B19_PBYTE_Pos) /*!< GPIO_PORT B19: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B20 ----------------------------------------- -#define GPIO_PORT_B20_PBYTE_Pos 0 /*!< GPIO_PORT B20: PBYTE Position */ -#define GPIO_PORT_B20_PBYTE_Msk (0x01UL << GPIO_PORT_B20_PBYTE_Pos) /*!< GPIO_PORT B20: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B21 ----------------------------------------- -#define GPIO_PORT_B21_PBYTE_Pos 0 /*!< GPIO_PORT B21: PBYTE Position */ -#define GPIO_PORT_B21_PBYTE_Msk (0x01UL << GPIO_PORT_B21_PBYTE_Pos) /*!< GPIO_PORT B21: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B22 ----------------------------------------- -#define GPIO_PORT_B22_PBYTE_Pos 0 /*!< GPIO_PORT B22: PBYTE Position */ -#define GPIO_PORT_B22_PBYTE_Msk (0x01UL << GPIO_PORT_B22_PBYTE_Pos) /*!< GPIO_PORT B22: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B23 ----------------------------------------- -#define GPIO_PORT_B23_PBYTE_Pos 0 /*!< GPIO_PORT B23: PBYTE Position */ -#define GPIO_PORT_B23_PBYTE_Msk (0x01UL << GPIO_PORT_B23_PBYTE_Pos) /*!< GPIO_PORT B23: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B24 ----------------------------------------- -#define GPIO_PORT_B24_PBYTE_Pos 0 /*!< GPIO_PORT B24: PBYTE Position */ -#define GPIO_PORT_B24_PBYTE_Msk (0x01UL << GPIO_PORT_B24_PBYTE_Pos) /*!< GPIO_PORT B24: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B25 ----------------------------------------- -#define GPIO_PORT_B25_PBYTE_Pos 0 /*!< GPIO_PORT B25: PBYTE Position */ -#define GPIO_PORT_B25_PBYTE_Msk (0x01UL << GPIO_PORT_B25_PBYTE_Pos) /*!< GPIO_PORT B25: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B26 ----------------------------------------- -#define GPIO_PORT_B26_PBYTE_Pos 0 /*!< GPIO_PORT B26: PBYTE Position */ -#define GPIO_PORT_B26_PBYTE_Msk (0x01UL << GPIO_PORT_B26_PBYTE_Pos) /*!< GPIO_PORT B26: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B27 ----------------------------------------- -#define GPIO_PORT_B27_PBYTE_Pos 0 /*!< GPIO_PORT B27: PBYTE Position */ -#define GPIO_PORT_B27_PBYTE_Msk (0x01UL << GPIO_PORT_B27_PBYTE_Pos) /*!< GPIO_PORT B27: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B28 ----------------------------------------- -#define GPIO_PORT_B28_PBYTE_Pos 0 /*!< GPIO_PORT B28: PBYTE Position */ -#define GPIO_PORT_B28_PBYTE_Msk (0x01UL << GPIO_PORT_B28_PBYTE_Pos) /*!< GPIO_PORT B28: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B29 ----------------------------------------- -#define GPIO_PORT_B29_PBYTE_Pos 0 /*!< GPIO_PORT B29: PBYTE Position */ -#define GPIO_PORT_B29_PBYTE_Msk (0x01UL << GPIO_PORT_B29_PBYTE_Pos) /*!< GPIO_PORT B29: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B30 ----------------------------------------- -#define GPIO_PORT_B30_PBYTE_Pos 0 /*!< GPIO_PORT B30: PBYTE Position */ -#define GPIO_PORT_B30_PBYTE_Msk (0x01UL << GPIO_PORT_B30_PBYTE_Pos) /*!< GPIO_PORT B30: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B31 ----------------------------------------- -#define GPIO_PORT_B31_PBYTE_Pos 0 /*!< GPIO_PORT B31: PBYTE Position */ -#define GPIO_PORT_B31_PBYTE_Msk (0x01UL << GPIO_PORT_B31_PBYTE_Pos) /*!< GPIO_PORT B31: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B32 ----------------------------------------- -#define GPIO_PORT_B32_PBYTE_Pos 0 /*!< GPIO_PORT B32: PBYTE Position */ -#define GPIO_PORT_B32_PBYTE_Msk (0x01UL << GPIO_PORT_B32_PBYTE_Pos) /*!< GPIO_PORT B32: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B33 ----------------------------------------- -#define GPIO_PORT_B33_PBYTE_Pos 0 /*!< GPIO_PORT B33: PBYTE Position */ -#define GPIO_PORT_B33_PBYTE_Msk (0x01UL << GPIO_PORT_B33_PBYTE_Pos) /*!< GPIO_PORT B33: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B34 ----------------------------------------- -#define GPIO_PORT_B34_PBYTE_Pos 0 /*!< GPIO_PORT B34: PBYTE Position */ -#define GPIO_PORT_B34_PBYTE_Msk (0x01UL << GPIO_PORT_B34_PBYTE_Pos) /*!< GPIO_PORT B34: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B35 ----------------------------------------- -#define GPIO_PORT_B35_PBYTE_Pos 0 /*!< GPIO_PORT B35: PBYTE Position */ -#define GPIO_PORT_B35_PBYTE_Msk (0x01UL << GPIO_PORT_B35_PBYTE_Pos) /*!< GPIO_PORT B35: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B36 ----------------------------------------- -#define GPIO_PORT_B36_PBYTE_Pos 0 /*!< GPIO_PORT B36: PBYTE Position */ -#define GPIO_PORT_B36_PBYTE_Msk (0x01UL << GPIO_PORT_B36_PBYTE_Pos) /*!< GPIO_PORT B36: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B37 ----------------------------------------- -#define GPIO_PORT_B37_PBYTE_Pos 0 /*!< GPIO_PORT B37: PBYTE Position */ -#define GPIO_PORT_B37_PBYTE_Msk (0x01UL << GPIO_PORT_B37_PBYTE_Pos) /*!< GPIO_PORT B37: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B38 ----------------------------------------- -#define GPIO_PORT_B38_PBYTE_Pos 0 /*!< GPIO_PORT B38: PBYTE Position */ -#define GPIO_PORT_B38_PBYTE_Msk (0x01UL << GPIO_PORT_B38_PBYTE_Pos) /*!< GPIO_PORT B38: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B39 ----------------------------------------- -#define GPIO_PORT_B39_PBYTE_Pos 0 /*!< GPIO_PORT B39: PBYTE Position */ -#define GPIO_PORT_B39_PBYTE_Msk (0x01UL << GPIO_PORT_B39_PBYTE_Pos) /*!< GPIO_PORT B39: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B40 ----------------------------------------- -#define GPIO_PORT_B40_PBYTE_Pos 0 /*!< GPIO_PORT B40: PBYTE Position */ -#define GPIO_PORT_B40_PBYTE_Msk (0x01UL << GPIO_PORT_B40_PBYTE_Pos) /*!< GPIO_PORT B40: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B41 ----------------------------------------- -#define GPIO_PORT_B41_PBYTE_Pos 0 /*!< GPIO_PORT B41: PBYTE Position */ -#define GPIO_PORT_B41_PBYTE_Msk (0x01UL << GPIO_PORT_B41_PBYTE_Pos) /*!< GPIO_PORT B41: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B42 ----------------------------------------- -#define GPIO_PORT_B42_PBYTE_Pos 0 /*!< GPIO_PORT B42: PBYTE Position */ -#define GPIO_PORT_B42_PBYTE_Msk (0x01UL << GPIO_PORT_B42_PBYTE_Pos) /*!< GPIO_PORT B42: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B43 ----------------------------------------- -#define GPIO_PORT_B43_PBYTE_Pos 0 /*!< GPIO_PORT B43: PBYTE Position */ -#define GPIO_PORT_B43_PBYTE_Msk (0x01UL << GPIO_PORT_B43_PBYTE_Pos) /*!< GPIO_PORT B43: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B44 ----------------------------------------- -#define GPIO_PORT_B44_PBYTE_Pos 0 /*!< GPIO_PORT B44: PBYTE Position */ -#define GPIO_PORT_B44_PBYTE_Msk (0x01UL << GPIO_PORT_B44_PBYTE_Pos) /*!< GPIO_PORT B44: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B45 ----------------------------------------- -#define GPIO_PORT_B45_PBYTE_Pos 0 /*!< GPIO_PORT B45: PBYTE Position */ -#define GPIO_PORT_B45_PBYTE_Msk (0x01UL << GPIO_PORT_B45_PBYTE_Pos) /*!< GPIO_PORT B45: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B46 ----------------------------------------- -#define GPIO_PORT_B46_PBYTE_Pos 0 /*!< GPIO_PORT B46: PBYTE Position */ -#define GPIO_PORT_B46_PBYTE_Msk (0x01UL << GPIO_PORT_B46_PBYTE_Pos) /*!< GPIO_PORT B46: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B47 ----------------------------------------- -#define GPIO_PORT_B47_PBYTE_Pos 0 /*!< GPIO_PORT B47: PBYTE Position */ -#define GPIO_PORT_B47_PBYTE_Msk (0x01UL << GPIO_PORT_B47_PBYTE_Pos) /*!< GPIO_PORT B47: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B48 ----------------------------------------- -#define GPIO_PORT_B48_PBYTE_Pos 0 /*!< GPIO_PORT B48: PBYTE Position */ -#define GPIO_PORT_B48_PBYTE_Msk (0x01UL << GPIO_PORT_B48_PBYTE_Pos) /*!< GPIO_PORT B48: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B49 ----------------------------------------- -#define GPIO_PORT_B49_PBYTE_Pos 0 /*!< GPIO_PORT B49: PBYTE Position */ -#define GPIO_PORT_B49_PBYTE_Msk (0x01UL << GPIO_PORT_B49_PBYTE_Pos) /*!< GPIO_PORT B49: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B50 ----------------------------------------- -#define GPIO_PORT_B50_PBYTE_Pos 0 /*!< GPIO_PORT B50: PBYTE Position */ -#define GPIO_PORT_B50_PBYTE_Msk (0x01UL << GPIO_PORT_B50_PBYTE_Pos) /*!< GPIO_PORT B50: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B51 ----------------------------------------- -#define GPIO_PORT_B51_PBYTE_Pos 0 /*!< GPIO_PORT B51: PBYTE Position */ -#define GPIO_PORT_B51_PBYTE_Msk (0x01UL << GPIO_PORT_B51_PBYTE_Pos) /*!< GPIO_PORT B51: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B52 ----------------------------------------- -#define GPIO_PORT_B52_PBYTE_Pos 0 /*!< GPIO_PORT B52: PBYTE Position */ -#define GPIO_PORT_B52_PBYTE_Msk (0x01UL << GPIO_PORT_B52_PBYTE_Pos) /*!< GPIO_PORT B52: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B53 ----------------------------------------- -#define GPIO_PORT_B53_PBYTE_Pos 0 /*!< GPIO_PORT B53: PBYTE Position */ -#define GPIO_PORT_B53_PBYTE_Msk (0x01UL << GPIO_PORT_B53_PBYTE_Pos) /*!< GPIO_PORT B53: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B54 ----------------------------------------- -#define GPIO_PORT_B54_PBYTE_Pos 0 /*!< GPIO_PORT B54: PBYTE Position */ -#define GPIO_PORT_B54_PBYTE_Msk (0x01UL << GPIO_PORT_B54_PBYTE_Pos) /*!< GPIO_PORT B54: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B55 ----------------------------------------- -#define GPIO_PORT_B55_PBYTE_Pos 0 /*!< GPIO_PORT B55: PBYTE Position */ -#define GPIO_PORT_B55_PBYTE_Msk (0x01UL << GPIO_PORT_B55_PBYTE_Pos) /*!< GPIO_PORT B55: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B56 ----------------------------------------- -#define GPIO_PORT_B56_PBYTE_Pos 0 /*!< GPIO_PORT B56: PBYTE Position */ -#define GPIO_PORT_B56_PBYTE_Msk (0x01UL << GPIO_PORT_B56_PBYTE_Pos) /*!< GPIO_PORT B56: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B57 ----------------------------------------- -#define GPIO_PORT_B57_PBYTE_Pos 0 /*!< GPIO_PORT B57: PBYTE Position */ -#define GPIO_PORT_B57_PBYTE_Msk (0x01UL << GPIO_PORT_B57_PBYTE_Pos) /*!< GPIO_PORT B57: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B58 ----------------------------------------- -#define GPIO_PORT_B58_PBYTE_Pos 0 /*!< GPIO_PORT B58: PBYTE Position */ -#define GPIO_PORT_B58_PBYTE_Msk (0x01UL << GPIO_PORT_B58_PBYTE_Pos) /*!< GPIO_PORT B58: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B59 ----------------------------------------- -#define GPIO_PORT_B59_PBYTE_Pos 0 /*!< GPIO_PORT B59: PBYTE Position */ -#define GPIO_PORT_B59_PBYTE_Msk (0x01UL << GPIO_PORT_B59_PBYTE_Pos) /*!< GPIO_PORT B59: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B60 ----------------------------------------- -#define GPIO_PORT_B60_PBYTE_Pos 0 /*!< GPIO_PORT B60: PBYTE Position */ -#define GPIO_PORT_B60_PBYTE_Msk (0x01UL << GPIO_PORT_B60_PBYTE_Pos) /*!< GPIO_PORT B60: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B61 ----------------------------------------- -#define GPIO_PORT_B61_PBYTE_Pos 0 /*!< GPIO_PORT B61: PBYTE Position */ -#define GPIO_PORT_B61_PBYTE_Msk (0x01UL << GPIO_PORT_B61_PBYTE_Pos) /*!< GPIO_PORT B61: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B62 ----------------------------------------- -#define GPIO_PORT_B62_PBYTE_Pos 0 /*!< GPIO_PORT B62: PBYTE Position */ -#define GPIO_PORT_B62_PBYTE_Msk (0x01UL << GPIO_PORT_B62_PBYTE_Pos) /*!< GPIO_PORT B62: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B63 ----------------------------------------- -#define GPIO_PORT_B63_PBYTE_Pos 0 /*!< GPIO_PORT B63: PBYTE Position */ -#define GPIO_PORT_B63_PBYTE_Msk (0x01UL << GPIO_PORT_B63_PBYTE_Pos) /*!< GPIO_PORT B63: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B64 ----------------------------------------- -#define GPIO_PORT_B64_PBYTE_Pos 0 /*!< GPIO_PORT B64: PBYTE Position */ -#define GPIO_PORT_B64_PBYTE_Msk (0x01UL << GPIO_PORT_B64_PBYTE_Pos) /*!< GPIO_PORT B64: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B65 ----------------------------------------- -#define GPIO_PORT_B65_PBYTE_Pos 0 /*!< GPIO_PORT B65: PBYTE Position */ -#define GPIO_PORT_B65_PBYTE_Msk (0x01UL << GPIO_PORT_B65_PBYTE_Pos) /*!< GPIO_PORT B65: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B66 ----------------------------------------- -#define GPIO_PORT_B66_PBYTE_Pos 0 /*!< GPIO_PORT B66: PBYTE Position */ -#define GPIO_PORT_B66_PBYTE_Msk (0x01UL << GPIO_PORT_B66_PBYTE_Pos) /*!< GPIO_PORT B66: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B67 ----------------------------------------- -#define GPIO_PORT_B67_PBYTE_Pos 0 /*!< GPIO_PORT B67: PBYTE Position */ -#define GPIO_PORT_B67_PBYTE_Msk (0x01UL << GPIO_PORT_B67_PBYTE_Pos) /*!< GPIO_PORT B67: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B68 ----------------------------------------- -#define GPIO_PORT_B68_PBYTE_Pos 0 /*!< GPIO_PORT B68: PBYTE Position */ -#define GPIO_PORT_B68_PBYTE_Msk (0x01UL << GPIO_PORT_B68_PBYTE_Pos) /*!< GPIO_PORT B68: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B69 ----------------------------------------- -#define GPIO_PORT_B69_PBYTE_Pos 0 /*!< GPIO_PORT B69: PBYTE Position */ -#define GPIO_PORT_B69_PBYTE_Msk (0x01UL << GPIO_PORT_B69_PBYTE_Pos) /*!< GPIO_PORT B69: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B70 ----------------------------------------- -#define GPIO_PORT_B70_PBYTE_Pos 0 /*!< GPIO_PORT B70: PBYTE Position */ -#define GPIO_PORT_B70_PBYTE_Msk (0x01UL << GPIO_PORT_B70_PBYTE_Pos) /*!< GPIO_PORT B70: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B71 ----------------------------------------- -#define GPIO_PORT_B71_PBYTE_Pos 0 /*!< GPIO_PORT B71: PBYTE Position */ -#define GPIO_PORT_B71_PBYTE_Msk (0x01UL << GPIO_PORT_B71_PBYTE_Pos) /*!< GPIO_PORT B71: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B72 ----------------------------------------- -#define GPIO_PORT_B72_PBYTE_Pos 0 /*!< GPIO_PORT B72: PBYTE Position */ -#define GPIO_PORT_B72_PBYTE_Msk (0x01UL << GPIO_PORT_B72_PBYTE_Pos) /*!< GPIO_PORT B72: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B73 ----------------------------------------- -#define GPIO_PORT_B73_PBYTE_Pos 0 /*!< GPIO_PORT B73: PBYTE Position */ -#define GPIO_PORT_B73_PBYTE_Msk (0x01UL << GPIO_PORT_B73_PBYTE_Pos) /*!< GPIO_PORT B73: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B74 ----------------------------------------- -#define GPIO_PORT_B74_PBYTE_Pos 0 /*!< GPIO_PORT B74: PBYTE Position */ -#define GPIO_PORT_B74_PBYTE_Msk (0x01UL << GPIO_PORT_B74_PBYTE_Pos) /*!< GPIO_PORT B74: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B75 ----------------------------------------- -#define GPIO_PORT_B75_PBYTE_Pos 0 /*!< GPIO_PORT B75: PBYTE Position */ -#define GPIO_PORT_B75_PBYTE_Msk (0x01UL << GPIO_PORT_B75_PBYTE_Pos) /*!< GPIO_PORT B75: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B76 ----------------------------------------- -#define GPIO_PORT_B76_PBYTE_Pos 0 /*!< GPIO_PORT B76: PBYTE Position */ -#define GPIO_PORT_B76_PBYTE_Msk (0x01UL << GPIO_PORT_B76_PBYTE_Pos) /*!< GPIO_PORT B76: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B77 ----------------------------------------- -#define GPIO_PORT_B77_PBYTE_Pos 0 /*!< GPIO_PORT B77: PBYTE Position */ -#define GPIO_PORT_B77_PBYTE_Msk (0x01UL << GPIO_PORT_B77_PBYTE_Pos) /*!< GPIO_PORT B77: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B78 ----------------------------------------- -#define GPIO_PORT_B78_PBYTE_Pos 0 /*!< GPIO_PORT B78: PBYTE Position */ -#define GPIO_PORT_B78_PBYTE_Msk (0x01UL << GPIO_PORT_B78_PBYTE_Pos) /*!< GPIO_PORT B78: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B79 ----------------------------------------- -#define GPIO_PORT_B79_PBYTE_Pos 0 /*!< GPIO_PORT B79: PBYTE Position */ -#define GPIO_PORT_B79_PBYTE_Msk (0x01UL << GPIO_PORT_B79_PBYTE_Pos) /*!< GPIO_PORT B79: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B80 ----------------------------------------- -#define GPIO_PORT_B80_PBYTE_Pos 0 /*!< GPIO_PORT B80: PBYTE Position */ -#define GPIO_PORT_B80_PBYTE_Msk (0x01UL << GPIO_PORT_B80_PBYTE_Pos) /*!< GPIO_PORT B80: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B81 ----------------------------------------- -#define GPIO_PORT_B81_PBYTE_Pos 0 /*!< GPIO_PORT B81: PBYTE Position */ -#define GPIO_PORT_B81_PBYTE_Msk (0x01UL << GPIO_PORT_B81_PBYTE_Pos) /*!< GPIO_PORT B81: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B82 ----------------------------------------- -#define GPIO_PORT_B82_PBYTE_Pos 0 /*!< GPIO_PORT B82: PBYTE Position */ -#define GPIO_PORT_B82_PBYTE_Msk (0x01UL << GPIO_PORT_B82_PBYTE_Pos) /*!< GPIO_PORT B82: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B83 ----------------------------------------- -#define GPIO_PORT_B83_PBYTE_Pos 0 /*!< GPIO_PORT B83: PBYTE Position */ -#define GPIO_PORT_B83_PBYTE_Msk (0x01UL << GPIO_PORT_B83_PBYTE_Pos) /*!< GPIO_PORT B83: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B84 ----------------------------------------- -#define GPIO_PORT_B84_PBYTE_Pos 0 /*!< GPIO_PORT B84: PBYTE Position */ -#define GPIO_PORT_B84_PBYTE_Msk (0x01UL << GPIO_PORT_B84_PBYTE_Pos) /*!< GPIO_PORT B84: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B85 ----------------------------------------- -#define GPIO_PORT_B85_PBYTE_Pos 0 /*!< GPIO_PORT B85: PBYTE Position */ -#define GPIO_PORT_B85_PBYTE_Msk (0x01UL << GPIO_PORT_B85_PBYTE_Pos) /*!< GPIO_PORT B85: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B86 ----------------------------------------- -#define GPIO_PORT_B86_PBYTE_Pos 0 /*!< GPIO_PORT B86: PBYTE Position */ -#define GPIO_PORT_B86_PBYTE_Msk (0x01UL << GPIO_PORT_B86_PBYTE_Pos) /*!< GPIO_PORT B86: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B87 ----------------------------------------- -#define GPIO_PORT_B87_PBYTE_Pos 0 /*!< GPIO_PORT B87: PBYTE Position */ -#define GPIO_PORT_B87_PBYTE_Msk (0x01UL << GPIO_PORT_B87_PBYTE_Pos) /*!< GPIO_PORT B87: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B88 ----------------------------------------- -#define GPIO_PORT_B88_PBYTE_Pos 0 /*!< GPIO_PORT B88: PBYTE Position */ -#define GPIO_PORT_B88_PBYTE_Msk (0x01UL << GPIO_PORT_B88_PBYTE_Pos) /*!< GPIO_PORT B88: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B89 ----------------------------------------- -#define GPIO_PORT_B89_PBYTE_Pos 0 /*!< GPIO_PORT B89: PBYTE Position */ -#define GPIO_PORT_B89_PBYTE_Msk (0x01UL << GPIO_PORT_B89_PBYTE_Pos) /*!< GPIO_PORT B89: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B90 ----------------------------------------- -#define GPIO_PORT_B90_PBYTE_Pos 0 /*!< GPIO_PORT B90: PBYTE Position */ -#define GPIO_PORT_B90_PBYTE_Msk (0x01UL << GPIO_PORT_B90_PBYTE_Pos) /*!< GPIO_PORT B90: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B91 ----------------------------------------- -#define GPIO_PORT_B91_PBYTE_Pos 0 /*!< GPIO_PORT B91: PBYTE Position */ -#define GPIO_PORT_B91_PBYTE_Msk (0x01UL << GPIO_PORT_B91_PBYTE_Pos) /*!< GPIO_PORT B91: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B92 ----------------------------------------- -#define GPIO_PORT_B92_PBYTE_Pos 0 /*!< GPIO_PORT B92: PBYTE Position */ -#define GPIO_PORT_B92_PBYTE_Msk (0x01UL << GPIO_PORT_B92_PBYTE_Pos) /*!< GPIO_PORT B92: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B93 ----------------------------------------- -#define GPIO_PORT_B93_PBYTE_Pos 0 /*!< GPIO_PORT B93: PBYTE Position */ -#define GPIO_PORT_B93_PBYTE_Msk (0x01UL << GPIO_PORT_B93_PBYTE_Pos) /*!< GPIO_PORT B93: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B94 ----------------------------------------- -#define GPIO_PORT_B94_PBYTE_Pos 0 /*!< GPIO_PORT B94: PBYTE Position */ -#define GPIO_PORT_B94_PBYTE_Msk (0x01UL << GPIO_PORT_B94_PBYTE_Pos) /*!< GPIO_PORT B94: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B95 ----------------------------------------- -#define GPIO_PORT_B95_PBYTE_Pos 0 /*!< GPIO_PORT B95: PBYTE Position */ -#define GPIO_PORT_B95_PBYTE_Msk (0x01UL << GPIO_PORT_B95_PBYTE_Pos) /*!< GPIO_PORT B95: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B96 ----------------------------------------- -#define GPIO_PORT_B96_PBYTE_Pos 0 /*!< GPIO_PORT B96: PBYTE Position */ -#define GPIO_PORT_B96_PBYTE_Msk (0x01UL << GPIO_PORT_B96_PBYTE_Pos) /*!< GPIO_PORT B96: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B97 ----------------------------------------- -#define GPIO_PORT_B97_PBYTE_Pos 0 /*!< GPIO_PORT B97: PBYTE Position */ -#define GPIO_PORT_B97_PBYTE_Msk (0x01UL << GPIO_PORT_B97_PBYTE_Pos) /*!< GPIO_PORT B97: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B98 ----------------------------------------- -#define GPIO_PORT_B98_PBYTE_Pos 0 /*!< GPIO_PORT B98: PBYTE Position */ -#define GPIO_PORT_B98_PBYTE_Msk (0x01UL << GPIO_PORT_B98_PBYTE_Pos) /*!< GPIO_PORT B98: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_B99 ----------------------------------------- -#define GPIO_PORT_B99_PBYTE_Pos 0 /*!< GPIO_PORT B99: PBYTE Position */ -#define GPIO_PORT_B99_PBYTE_Msk (0x01UL << GPIO_PORT_B99_PBYTE_Pos) /*!< GPIO_PORT B99: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B100 ----------------------------------------- -#define GPIO_PORT_B100_PBYTE_Pos 0 /*!< GPIO_PORT B100: PBYTE Position */ -#define GPIO_PORT_B100_PBYTE_Msk (0x01UL << GPIO_PORT_B100_PBYTE_Pos) /*!< GPIO_PORT B100: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B101 ----------------------------------------- -#define GPIO_PORT_B101_PBYTE_Pos 0 /*!< GPIO_PORT B101: PBYTE Position */ -#define GPIO_PORT_B101_PBYTE_Msk (0x01UL << GPIO_PORT_B101_PBYTE_Pos) /*!< GPIO_PORT B101: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B102 ----------------------------------------- -#define GPIO_PORT_B102_PBYTE_Pos 0 /*!< GPIO_PORT B102: PBYTE Position */ -#define GPIO_PORT_B102_PBYTE_Msk (0x01UL << GPIO_PORT_B102_PBYTE_Pos) /*!< GPIO_PORT B102: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B103 ----------------------------------------- -#define GPIO_PORT_B103_PBYTE_Pos 0 /*!< GPIO_PORT B103: PBYTE Position */ -#define GPIO_PORT_B103_PBYTE_Msk (0x01UL << GPIO_PORT_B103_PBYTE_Pos) /*!< GPIO_PORT B103: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B104 ----------------------------------------- -#define GPIO_PORT_B104_PBYTE_Pos 0 /*!< GPIO_PORT B104: PBYTE Position */ -#define GPIO_PORT_B104_PBYTE_Msk (0x01UL << GPIO_PORT_B104_PBYTE_Pos) /*!< GPIO_PORT B104: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B105 ----------------------------------------- -#define GPIO_PORT_B105_PBYTE_Pos 0 /*!< GPIO_PORT B105: PBYTE Position */ -#define GPIO_PORT_B105_PBYTE_Msk (0x01UL << GPIO_PORT_B105_PBYTE_Pos) /*!< GPIO_PORT B105: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B106 ----------------------------------------- -#define GPIO_PORT_B106_PBYTE_Pos 0 /*!< GPIO_PORT B106: PBYTE Position */ -#define GPIO_PORT_B106_PBYTE_Msk (0x01UL << GPIO_PORT_B106_PBYTE_Pos) /*!< GPIO_PORT B106: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B107 ----------------------------------------- -#define GPIO_PORT_B107_PBYTE_Pos 0 /*!< GPIO_PORT B107: PBYTE Position */ -#define GPIO_PORT_B107_PBYTE_Msk (0x01UL << GPIO_PORT_B107_PBYTE_Pos) /*!< GPIO_PORT B107: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B108 ----------------------------------------- -#define GPIO_PORT_B108_PBYTE_Pos 0 /*!< GPIO_PORT B108: PBYTE Position */ -#define GPIO_PORT_B108_PBYTE_Msk (0x01UL << GPIO_PORT_B108_PBYTE_Pos) /*!< GPIO_PORT B108: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B109 ----------------------------------------- -#define GPIO_PORT_B109_PBYTE_Pos 0 /*!< GPIO_PORT B109: PBYTE Position */ -#define GPIO_PORT_B109_PBYTE_Msk (0x01UL << GPIO_PORT_B109_PBYTE_Pos) /*!< GPIO_PORT B109: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B110 ----------------------------------------- -#define GPIO_PORT_B110_PBYTE_Pos 0 /*!< GPIO_PORT B110: PBYTE Position */ -#define GPIO_PORT_B110_PBYTE_Msk (0x01UL << GPIO_PORT_B110_PBYTE_Pos) /*!< GPIO_PORT B110: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B111 ----------------------------------------- -#define GPIO_PORT_B111_PBYTE_Pos 0 /*!< GPIO_PORT B111: PBYTE Position */ -#define GPIO_PORT_B111_PBYTE_Msk (0x01UL << GPIO_PORT_B111_PBYTE_Pos) /*!< GPIO_PORT B111: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B112 ----------------------------------------- -#define GPIO_PORT_B112_PBYTE_Pos 0 /*!< GPIO_PORT B112: PBYTE Position */ -#define GPIO_PORT_B112_PBYTE_Msk (0x01UL << GPIO_PORT_B112_PBYTE_Pos) /*!< GPIO_PORT B112: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B113 ----------------------------------------- -#define GPIO_PORT_B113_PBYTE_Pos 0 /*!< GPIO_PORT B113: PBYTE Position */ -#define GPIO_PORT_B113_PBYTE_Msk (0x01UL << GPIO_PORT_B113_PBYTE_Pos) /*!< GPIO_PORT B113: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B114 ----------------------------------------- -#define GPIO_PORT_B114_PBYTE_Pos 0 /*!< GPIO_PORT B114: PBYTE Position */ -#define GPIO_PORT_B114_PBYTE_Msk (0x01UL << GPIO_PORT_B114_PBYTE_Pos) /*!< GPIO_PORT B114: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B115 ----------------------------------------- -#define GPIO_PORT_B115_PBYTE_Pos 0 /*!< GPIO_PORT B115: PBYTE Position */ -#define GPIO_PORT_B115_PBYTE_Msk (0x01UL << GPIO_PORT_B115_PBYTE_Pos) /*!< GPIO_PORT B115: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B116 ----------------------------------------- -#define GPIO_PORT_B116_PBYTE_Pos 0 /*!< GPIO_PORT B116: PBYTE Position */ -#define GPIO_PORT_B116_PBYTE_Msk (0x01UL << GPIO_PORT_B116_PBYTE_Pos) /*!< GPIO_PORT B116: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B117 ----------------------------------------- -#define GPIO_PORT_B117_PBYTE_Pos 0 /*!< GPIO_PORT B117: PBYTE Position */ -#define GPIO_PORT_B117_PBYTE_Msk (0x01UL << GPIO_PORT_B117_PBYTE_Pos) /*!< GPIO_PORT B117: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B118 ----------------------------------------- -#define GPIO_PORT_B118_PBYTE_Pos 0 /*!< GPIO_PORT B118: PBYTE Position */ -#define GPIO_PORT_B118_PBYTE_Msk (0x01UL << GPIO_PORT_B118_PBYTE_Pos) /*!< GPIO_PORT B118: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B119 ----------------------------------------- -#define GPIO_PORT_B119_PBYTE_Pos 0 /*!< GPIO_PORT B119: PBYTE Position */ -#define GPIO_PORT_B119_PBYTE_Msk (0x01UL << GPIO_PORT_B119_PBYTE_Pos) /*!< GPIO_PORT B119: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B120 ----------------------------------------- -#define GPIO_PORT_B120_PBYTE_Pos 0 /*!< GPIO_PORT B120: PBYTE Position */ -#define GPIO_PORT_B120_PBYTE_Msk (0x01UL << GPIO_PORT_B120_PBYTE_Pos) /*!< GPIO_PORT B120: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B121 ----------------------------------------- -#define GPIO_PORT_B121_PBYTE_Pos 0 /*!< GPIO_PORT B121: PBYTE Position */ -#define GPIO_PORT_B121_PBYTE_Msk (0x01UL << GPIO_PORT_B121_PBYTE_Pos) /*!< GPIO_PORT B121: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B122 ----------------------------------------- -#define GPIO_PORT_B122_PBYTE_Pos 0 /*!< GPIO_PORT B122: PBYTE Position */ -#define GPIO_PORT_B122_PBYTE_Msk (0x01UL << GPIO_PORT_B122_PBYTE_Pos) /*!< GPIO_PORT B122: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B123 ----------------------------------------- -#define GPIO_PORT_B123_PBYTE_Pos 0 /*!< GPIO_PORT B123: PBYTE Position */ -#define GPIO_PORT_B123_PBYTE_Msk (0x01UL << GPIO_PORT_B123_PBYTE_Pos) /*!< GPIO_PORT B123: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B124 ----------------------------------------- -#define GPIO_PORT_B124_PBYTE_Pos 0 /*!< GPIO_PORT B124: PBYTE Position */ -#define GPIO_PORT_B124_PBYTE_Msk (0x01UL << GPIO_PORT_B124_PBYTE_Pos) /*!< GPIO_PORT B124: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B125 ----------------------------------------- -#define GPIO_PORT_B125_PBYTE_Pos 0 /*!< GPIO_PORT B125: PBYTE Position */ -#define GPIO_PORT_B125_PBYTE_Msk (0x01UL << GPIO_PORT_B125_PBYTE_Pos) /*!< GPIO_PORT B125: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B126 ----------------------------------------- -#define GPIO_PORT_B126_PBYTE_Pos 0 /*!< GPIO_PORT B126: PBYTE Position */ -#define GPIO_PORT_B126_PBYTE_Msk (0x01UL << GPIO_PORT_B126_PBYTE_Pos) /*!< GPIO_PORT B126: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B127 ----------------------------------------- -#define GPIO_PORT_B127_PBYTE_Pos 0 /*!< GPIO_PORT B127: PBYTE Position */ -#define GPIO_PORT_B127_PBYTE_Msk (0x01UL << GPIO_PORT_B127_PBYTE_Pos) /*!< GPIO_PORT B127: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B128 ----------------------------------------- -#define GPIO_PORT_B128_PBYTE_Pos 0 /*!< GPIO_PORT B128: PBYTE Position */ -#define GPIO_PORT_B128_PBYTE_Msk (0x01UL << GPIO_PORT_B128_PBYTE_Pos) /*!< GPIO_PORT B128: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B129 ----------------------------------------- -#define GPIO_PORT_B129_PBYTE_Pos 0 /*!< GPIO_PORT B129: PBYTE Position */ -#define GPIO_PORT_B129_PBYTE_Msk (0x01UL << GPIO_PORT_B129_PBYTE_Pos) /*!< GPIO_PORT B129: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B130 ----------------------------------------- -#define GPIO_PORT_B130_PBYTE_Pos 0 /*!< GPIO_PORT B130: PBYTE Position */ -#define GPIO_PORT_B130_PBYTE_Msk (0x01UL << GPIO_PORT_B130_PBYTE_Pos) /*!< GPIO_PORT B130: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B131 ----------------------------------------- -#define GPIO_PORT_B131_PBYTE_Pos 0 /*!< GPIO_PORT B131: PBYTE Position */ -#define GPIO_PORT_B131_PBYTE_Msk (0x01UL << GPIO_PORT_B131_PBYTE_Pos) /*!< GPIO_PORT B131: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B132 ----------------------------------------- -#define GPIO_PORT_B132_PBYTE_Pos 0 /*!< GPIO_PORT B132: PBYTE Position */ -#define GPIO_PORT_B132_PBYTE_Msk (0x01UL << GPIO_PORT_B132_PBYTE_Pos) /*!< GPIO_PORT B132: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B133 ----------------------------------------- -#define GPIO_PORT_B133_PBYTE_Pos 0 /*!< GPIO_PORT B133: PBYTE Position */ -#define GPIO_PORT_B133_PBYTE_Msk (0x01UL << GPIO_PORT_B133_PBYTE_Pos) /*!< GPIO_PORT B133: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B134 ----------------------------------------- -#define GPIO_PORT_B134_PBYTE_Pos 0 /*!< GPIO_PORT B134: PBYTE Position */ -#define GPIO_PORT_B134_PBYTE_Msk (0x01UL << GPIO_PORT_B134_PBYTE_Pos) /*!< GPIO_PORT B134: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B135 ----------------------------------------- -#define GPIO_PORT_B135_PBYTE_Pos 0 /*!< GPIO_PORT B135: PBYTE Position */ -#define GPIO_PORT_B135_PBYTE_Msk (0x01UL << GPIO_PORT_B135_PBYTE_Pos) /*!< GPIO_PORT B135: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B136 ----------------------------------------- -#define GPIO_PORT_B136_PBYTE_Pos 0 /*!< GPIO_PORT B136: PBYTE Position */ -#define GPIO_PORT_B136_PBYTE_Msk (0x01UL << GPIO_PORT_B136_PBYTE_Pos) /*!< GPIO_PORT B136: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B137 ----------------------------------------- -#define GPIO_PORT_B137_PBYTE_Pos 0 /*!< GPIO_PORT B137: PBYTE Position */ -#define GPIO_PORT_B137_PBYTE_Msk (0x01UL << GPIO_PORT_B137_PBYTE_Pos) /*!< GPIO_PORT B137: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B138 ----------------------------------------- -#define GPIO_PORT_B138_PBYTE_Pos 0 /*!< GPIO_PORT B138: PBYTE Position */ -#define GPIO_PORT_B138_PBYTE_Msk (0x01UL << GPIO_PORT_B138_PBYTE_Pos) /*!< GPIO_PORT B138: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B139 ----------------------------------------- -#define GPIO_PORT_B139_PBYTE_Pos 0 /*!< GPIO_PORT B139: PBYTE Position */ -#define GPIO_PORT_B139_PBYTE_Msk (0x01UL << GPIO_PORT_B139_PBYTE_Pos) /*!< GPIO_PORT B139: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B140 ----------------------------------------- -#define GPIO_PORT_B140_PBYTE_Pos 0 /*!< GPIO_PORT B140: PBYTE Position */ -#define GPIO_PORT_B140_PBYTE_Msk (0x01UL << GPIO_PORT_B140_PBYTE_Pos) /*!< GPIO_PORT B140: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B141 ----------------------------------------- -#define GPIO_PORT_B141_PBYTE_Pos 0 /*!< GPIO_PORT B141: PBYTE Position */ -#define GPIO_PORT_B141_PBYTE_Msk (0x01UL << GPIO_PORT_B141_PBYTE_Pos) /*!< GPIO_PORT B141: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B142 ----------------------------------------- -#define GPIO_PORT_B142_PBYTE_Pos 0 /*!< GPIO_PORT B142: PBYTE Position */ -#define GPIO_PORT_B142_PBYTE_Msk (0x01UL << GPIO_PORT_B142_PBYTE_Pos) /*!< GPIO_PORT B142: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B143 ----------------------------------------- -#define GPIO_PORT_B143_PBYTE_Pos 0 /*!< GPIO_PORT B143: PBYTE Position */ -#define GPIO_PORT_B143_PBYTE_Msk (0x01UL << GPIO_PORT_B143_PBYTE_Pos) /*!< GPIO_PORT B143: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B144 ----------------------------------------- -#define GPIO_PORT_B144_PBYTE_Pos 0 /*!< GPIO_PORT B144: PBYTE Position */ -#define GPIO_PORT_B144_PBYTE_Msk (0x01UL << GPIO_PORT_B144_PBYTE_Pos) /*!< GPIO_PORT B144: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B145 ----------------------------------------- -#define GPIO_PORT_B145_PBYTE_Pos 0 /*!< GPIO_PORT B145: PBYTE Position */ -#define GPIO_PORT_B145_PBYTE_Msk (0x01UL << GPIO_PORT_B145_PBYTE_Pos) /*!< GPIO_PORT B145: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B146 ----------------------------------------- -#define GPIO_PORT_B146_PBYTE_Pos 0 /*!< GPIO_PORT B146: PBYTE Position */ -#define GPIO_PORT_B146_PBYTE_Msk (0x01UL << GPIO_PORT_B146_PBYTE_Pos) /*!< GPIO_PORT B146: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B147 ----------------------------------------- -#define GPIO_PORT_B147_PBYTE_Pos 0 /*!< GPIO_PORT B147: PBYTE Position */ -#define GPIO_PORT_B147_PBYTE_Msk (0x01UL << GPIO_PORT_B147_PBYTE_Pos) /*!< GPIO_PORT B147: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B148 ----------------------------------------- -#define GPIO_PORT_B148_PBYTE_Pos 0 /*!< GPIO_PORT B148: PBYTE Position */ -#define GPIO_PORT_B148_PBYTE_Msk (0x01UL << GPIO_PORT_B148_PBYTE_Pos) /*!< GPIO_PORT B148: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B149 ----------------------------------------- -#define GPIO_PORT_B149_PBYTE_Pos 0 /*!< GPIO_PORT B149: PBYTE Position */ -#define GPIO_PORT_B149_PBYTE_Msk (0x01UL << GPIO_PORT_B149_PBYTE_Pos) /*!< GPIO_PORT B149: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B150 ----------------------------------------- -#define GPIO_PORT_B150_PBYTE_Pos 0 /*!< GPIO_PORT B150: PBYTE Position */ -#define GPIO_PORT_B150_PBYTE_Msk (0x01UL << GPIO_PORT_B150_PBYTE_Pos) /*!< GPIO_PORT B150: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B151 ----------------------------------------- -#define GPIO_PORT_B151_PBYTE_Pos 0 /*!< GPIO_PORT B151: PBYTE Position */ -#define GPIO_PORT_B151_PBYTE_Msk (0x01UL << GPIO_PORT_B151_PBYTE_Pos) /*!< GPIO_PORT B151: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B152 ----------------------------------------- -#define GPIO_PORT_B152_PBYTE_Pos 0 /*!< GPIO_PORT B152: PBYTE Position */ -#define GPIO_PORT_B152_PBYTE_Msk (0x01UL << GPIO_PORT_B152_PBYTE_Pos) /*!< GPIO_PORT B152: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B153 ----------------------------------------- -#define GPIO_PORT_B153_PBYTE_Pos 0 /*!< GPIO_PORT B153: PBYTE Position */ -#define GPIO_PORT_B153_PBYTE_Msk (0x01UL << GPIO_PORT_B153_PBYTE_Pos) /*!< GPIO_PORT B153: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B154 ----------------------------------------- -#define GPIO_PORT_B154_PBYTE_Pos 0 /*!< GPIO_PORT B154: PBYTE Position */ -#define GPIO_PORT_B154_PBYTE_Msk (0x01UL << GPIO_PORT_B154_PBYTE_Pos) /*!< GPIO_PORT B154: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B155 ----------------------------------------- -#define GPIO_PORT_B155_PBYTE_Pos 0 /*!< GPIO_PORT B155: PBYTE Position */ -#define GPIO_PORT_B155_PBYTE_Msk (0x01UL << GPIO_PORT_B155_PBYTE_Pos) /*!< GPIO_PORT B155: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B156 ----------------------------------------- -#define GPIO_PORT_B156_PBYTE_Pos 0 /*!< GPIO_PORT B156: PBYTE Position */ -#define GPIO_PORT_B156_PBYTE_Msk (0x01UL << GPIO_PORT_B156_PBYTE_Pos) /*!< GPIO_PORT B156: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B157 ----------------------------------------- -#define GPIO_PORT_B157_PBYTE_Pos 0 /*!< GPIO_PORT B157: PBYTE Position */ -#define GPIO_PORT_B157_PBYTE_Msk (0x01UL << GPIO_PORT_B157_PBYTE_Pos) /*!< GPIO_PORT B157: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B158 ----------------------------------------- -#define GPIO_PORT_B158_PBYTE_Pos 0 /*!< GPIO_PORT B158: PBYTE Position */ -#define GPIO_PORT_B158_PBYTE_Msk (0x01UL << GPIO_PORT_B158_PBYTE_Pos) /*!< GPIO_PORT B158: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B159 ----------------------------------------- -#define GPIO_PORT_B159_PBYTE_Pos 0 /*!< GPIO_PORT B159: PBYTE Position */ -#define GPIO_PORT_B159_PBYTE_Msk (0x01UL << GPIO_PORT_B159_PBYTE_Pos) /*!< GPIO_PORT B159: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B160 ----------------------------------------- -#define GPIO_PORT_B160_PBYTE_Pos 0 /*!< GPIO_PORT B160: PBYTE Position */ -#define GPIO_PORT_B160_PBYTE_Msk (0x01UL << GPIO_PORT_B160_PBYTE_Pos) /*!< GPIO_PORT B160: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B161 ----------------------------------------- -#define GPIO_PORT_B161_PBYTE_Pos 0 /*!< GPIO_PORT B161: PBYTE Position */ -#define GPIO_PORT_B161_PBYTE_Msk (0x01UL << GPIO_PORT_B161_PBYTE_Pos) /*!< GPIO_PORT B161: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B162 ----------------------------------------- -#define GPIO_PORT_B162_PBYTE_Pos 0 /*!< GPIO_PORT B162: PBYTE Position */ -#define GPIO_PORT_B162_PBYTE_Msk (0x01UL << GPIO_PORT_B162_PBYTE_Pos) /*!< GPIO_PORT B162: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B163 ----------------------------------------- -#define GPIO_PORT_B163_PBYTE_Pos 0 /*!< GPIO_PORT B163: PBYTE Position */ -#define GPIO_PORT_B163_PBYTE_Msk (0x01UL << GPIO_PORT_B163_PBYTE_Pos) /*!< GPIO_PORT B163: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B164 ----------------------------------------- -#define GPIO_PORT_B164_PBYTE_Pos 0 /*!< GPIO_PORT B164: PBYTE Position */ -#define GPIO_PORT_B164_PBYTE_Msk (0x01UL << GPIO_PORT_B164_PBYTE_Pos) /*!< GPIO_PORT B164: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B165 ----------------------------------------- -#define GPIO_PORT_B165_PBYTE_Pos 0 /*!< GPIO_PORT B165: PBYTE Position */ -#define GPIO_PORT_B165_PBYTE_Msk (0x01UL << GPIO_PORT_B165_PBYTE_Pos) /*!< GPIO_PORT B165: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B166 ----------------------------------------- -#define GPIO_PORT_B166_PBYTE_Pos 0 /*!< GPIO_PORT B166: PBYTE Position */ -#define GPIO_PORT_B166_PBYTE_Msk (0x01UL << GPIO_PORT_B166_PBYTE_Pos) /*!< GPIO_PORT B166: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B167 ----------------------------------------- -#define GPIO_PORT_B167_PBYTE_Pos 0 /*!< GPIO_PORT B167: PBYTE Position */ -#define GPIO_PORT_B167_PBYTE_Msk (0x01UL << GPIO_PORT_B167_PBYTE_Pos) /*!< GPIO_PORT B167: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B168 ----------------------------------------- -#define GPIO_PORT_B168_PBYTE_Pos 0 /*!< GPIO_PORT B168: PBYTE Position */ -#define GPIO_PORT_B168_PBYTE_Msk (0x01UL << GPIO_PORT_B168_PBYTE_Pos) /*!< GPIO_PORT B168: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B169 ----------------------------------------- -#define GPIO_PORT_B169_PBYTE_Pos 0 /*!< GPIO_PORT B169: PBYTE Position */ -#define GPIO_PORT_B169_PBYTE_Msk (0x01UL << GPIO_PORT_B169_PBYTE_Pos) /*!< GPIO_PORT B169: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B170 ----------------------------------------- -#define GPIO_PORT_B170_PBYTE_Pos 0 /*!< GPIO_PORT B170: PBYTE Position */ -#define GPIO_PORT_B170_PBYTE_Msk (0x01UL << GPIO_PORT_B170_PBYTE_Pos) /*!< GPIO_PORT B170: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B171 ----------------------------------------- -#define GPIO_PORT_B171_PBYTE_Pos 0 /*!< GPIO_PORT B171: PBYTE Position */ -#define GPIO_PORT_B171_PBYTE_Msk (0x01UL << GPIO_PORT_B171_PBYTE_Pos) /*!< GPIO_PORT B171: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B172 ----------------------------------------- -#define GPIO_PORT_B172_PBYTE_Pos 0 /*!< GPIO_PORT B172: PBYTE Position */ -#define GPIO_PORT_B172_PBYTE_Msk (0x01UL << GPIO_PORT_B172_PBYTE_Pos) /*!< GPIO_PORT B172: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B173 ----------------------------------------- -#define GPIO_PORT_B173_PBYTE_Pos 0 /*!< GPIO_PORT B173: PBYTE Position */ -#define GPIO_PORT_B173_PBYTE_Msk (0x01UL << GPIO_PORT_B173_PBYTE_Pos) /*!< GPIO_PORT B173: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B174 ----------------------------------------- -#define GPIO_PORT_B174_PBYTE_Pos 0 /*!< GPIO_PORT B174: PBYTE Position */ -#define GPIO_PORT_B174_PBYTE_Msk (0x01UL << GPIO_PORT_B174_PBYTE_Pos) /*!< GPIO_PORT B174: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B175 ----------------------------------------- -#define GPIO_PORT_B175_PBYTE_Pos 0 /*!< GPIO_PORT B175: PBYTE Position */ -#define GPIO_PORT_B175_PBYTE_Msk (0x01UL << GPIO_PORT_B175_PBYTE_Pos) /*!< GPIO_PORT B175: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B176 ----------------------------------------- -#define GPIO_PORT_B176_PBYTE_Pos 0 /*!< GPIO_PORT B176: PBYTE Position */ -#define GPIO_PORT_B176_PBYTE_Msk (0x01UL << GPIO_PORT_B176_PBYTE_Pos) /*!< GPIO_PORT B176: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B177 ----------------------------------------- -#define GPIO_PORT_B177_PBYTE_Pos 0 /*!< GPIO_PORT B177: PBYTE Position */ -#define GPIO_PORT_B177_PBYTE_Msk (0x01UL << GPIO_PORT_B177_PBYTE_Pos) /*!< GPIO_PORT B177: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B178 ----------------------------------------- -#define GPIO_PORT_B178_PBYTE_Pos 0 /*!< GPIO_PORT B178: PBYTE Position */ -#define GPIO_PORT_B178_PBYTE_Msk (0x01UL << GPIO_PORT_B178_PBYTE_Pos) /*!< GPIO_PORT B178: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B179 ----------------------------------------- -#define GPIO_PORT_B179_PBYTE_Pos 0 /*!< GPIO_PORT B179: PBYTE Position */ -#define GPIO_PORT_B179_PBYTE_Msk (0x01UL << GPIO_PORT_B179_PBYTE_Pos) /*!< GPIO_PORT B179: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B180 ----------------------------------------- -#define GPIO_PORT_B180_PBYTE_Pos 0 /*!< GPIO_PORT B180: PBYTE Position */ -#define GPIO_PORT_B180_PBYTE_Msk (0x01UL << GPIO_PORT_B180_PBYTE_Pos) /*!< GPIO_PORT B180: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B181 ----------------------------------------- -#define GPIO_PORT_B181_PBYTE_Pos 0 /*!< GPIO_PORT B181: PBYTE Position */ -#define GPIO_PORT_B181_PBYTE_Msk (0x01UL << GPIO_PORT_B181_PBYTE_Pos) /*!< GPIO_PORT B181: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B182 ----------------------------------------- -#define GPIO_PORT_B182_PBYTE_Pos 0 /*!< GPIO_PORT B182: PBYTE Position */ -#define GPIO_PORT_B182_PBYTE_Msk (0x01UL << GPIO_PORT_B182_PBYTE_Pos) /*!< GPIO_PORT B182: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B183 ----------------------------------------- -#define GPIO_PORT_B183_PBYTE_Pos 0 /*!< GPIO_PORT B183: PBYTE Position */ -#define GPIO_PORT_B183_PBYTE_Msk (0x01UL << GPIO_PORT_B183_PBYTE_Pos) /*!< GPIO_PORT B183: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B184 ----------------------------------------- -#define GPIO_PORT_B184_PBYTE_Pos 0 /*!< GPIO_PORT B184: PBYTE Position */ -#define GPIO_PORT_B184_PBYTE_Msk (0x01UL << GPIO_PORT_B184_PBYTE_Pos) /*!< GPIO_PORT B184: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B185 ----------------------------------------- -#define GPIO_PORT_B185_PBYTE_Pos 0 /*!< GPIO_PORT B185: PBYTE Position */ -#define GPIO_PORT_B185_PBYTE_Msk (0x01UL << GPIO_PORT_B185_PBYTE_Pos) /*!< GPIO_PORT B185: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B186 ----------------------------------------- -#define GPIO_PORT_B186_PBYTE_Pos 0 /*!< GPIO_PORT B186: PBYTE Position */ -#define GPIO_PORT_B186_PBYTE_Msk (0x01UL << GPIO_PORT_B186_PBYTE_Pos) /*!< GPIO_PORT B186: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B187 ----------------------------------------- -#define GPIO_PORT_B187_PBYTE_Pos 0 /*!< GPIO_PORT B187: PBYTE Position */ -#define GPIO_PORT_B187_PBYTE_Msk (0x01UL << GPIO_PORT_B187_PBYTE_Pos) /*!< GPIO_PORT B187: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B188 ----------------------------------------- -#define GPIO_PORT_B188_PBYTE_Pos 0 /*!< GPIO_PORT B188: PBYTE Position */ -#define GPIO_PORT_B188_PBYTE_Msk (0x01UL << GPIO_PORT_B188_PBYTE_Pos) /*!< GPIO_PORT B188: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B189 ----------------------------------------- -#define GPIO_PORT_B189_PBYTE_Pos 0 /*!< GPIO_PORT B189: PBYTE Position */ -#define GPIO_PORT_B189_PBYTE_Msk (0x01UL << GPIO_PORT_B189_PBYTE_Pos) /*!< GPIO_PORT B189: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B190 ----------------------------------------- -#define GPIO_PORT_B190_PBYTE_Pos 0 /*!< GPIO_PORT B190: PBYTE Position */ -#define GPIO_PORT_B190_PBYTE_Msk (0x01UL << GPIO_PORT_B190_PBYTE_Pos) /*!< GPIO_PORT B190: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B191 ----------------------------------------- -#define GPIO_PORT_B191_PBYTE_Pos 0 /*!< GPIO_PORT B191: PBYTE Position */ -#define GPIO_PORT_B191_PBYTE_Msk (0x01UL << GPIO_PORT_B191_PBYTE_Pos) /*!< GPIO_PORT B191: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B192 ----------------------------------------- -#define GPIO_PORT_B192_PBYTE_Pos 0 /*!< GPIO_PORT B192: PBYTE Position */ -#define GPIO_PORT_B192_PBYTE_Msk (0x01UL << GPIO_PORT_B192_PBYTE_Pos) /*!< GPIO_PORT B192: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B193 ----------------------------------------- -#define GPIO_PORT_B193_PBYTE_Pos 0 /*!< GPIO_PORT B193: PBYTE Position */ -#define GPIO_PORT_B193_PBYTE_Msk (0x01UL << GPIO_PORT_B193_PBYTE_Pos) /*!< GPIO_PORT B193: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B194 ----------------------------------------- -#define GPIO_PORT_B194_PBYTE_Pos 0 /*!< GPIO_PORT B194: PBYTE Position */ -#define GPIO_PORT_B194_PBYTE_Msk (0x01UL << GPIO_PORT_B194_PBYTE_Pos) /*!< GPIO_PORT B194: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B195 ----------------------------------------- -#define GPIO_PORT_B195_PBYTE_Pos 0 /*!< GPIO_PORT B195: PBYTE Position */ -#define GPIO_PORT_B195_PBYTE_Msk (0x01UL << GPIO_PORT_B195_PBYTE_Pos) /*!< GPIO_PORT B195: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B196 ----------------------------------------- -#define GPIO_PORT_B196_PBYTE_Pos 0 /*!< GPIO_PORT B196: PBYTE Position */ -#define GPIO_PORT_B196_PBYTE_Msk (0x01UL << GPIO_PORT_B196_PBYTE_Pos) /*!< GPIO_PORT B196: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B197 ----------------------------------------- -#define GPIO_PORT_B197_PBYTE_Pos 0 /*!< GPIO_PORT B197: PBYTE Position */ -#define GPIO_PORT_B197_PBYTE_Msk (0x01UL << GPIO_PORT_B197_PBYTE_Pos) /*!< GPIO_PORT B197: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B198 ----------------------------------------- -#define GPIO_PORT_B198_PBYTE_Pos 0 /*!< GPIO_PORT B198: PBYTE Position */ -#define GPIO_PORT_B198_PBYTE_Msk (0x01UL << GPIO_PORT_B198_PBYTE_Pos) /*!< GPIO_PORT B198: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B199 ----------------------------------------- -#define GPIO_PORT_B199_PBYTE_Pos 0 /*!< GPIO_PORT B199: PBYTE Position */ -#define GPIO_PORT_B199_PBYTE_Msk (0x01UL << GPIO_PORT_B199_PBYTE_Pos) /*!< GPIO_PORT B199: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B200 ----------------------------------------- -#define GPIO_PORT_B200_PBYTE_Pos 0 /*!< GPIO_PORT B200: PBYTE Position */ -#define GPIO_PORT_B200_PBYTE_Msk (0x01UL << GPIO_PORT_B200_PBYTE_Pos) /*!< GPIO_PORT B200: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B201 ----------------------------------------- -#define GPIO_PORT_B201_PBYTE_Pos 0 /*!< GPIO_PORT B201: PBYTE Position */ -#define GPIO_PORT_B201_PBYTE_Msk (0x01UL << GPIO_PORT_B201_PBYTE_Pos) /*!< GPIO_PORT B201: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B202 ----------------------------------------- -#define GPIO_PORT_B202_PBYTE_Pos 0 /*!< GPIO_PORT B202: PBYTE Position */ -#define GPIO_PORT_B202_PBYTE_Msk (0x01UL << GPIO_PORT_B202_PBYTE_Pos) /*!< GPIO_PORT B202: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B203 ----------------------------------------- -#define GPIO_PORT_B203_PBYTE_Pos 0 /*!< GPIO_PORT B203: PBYTE Position */ -#define GPIO_PORT_B203_PBYTE_Msk (0x01UL << GPIO_PORT_B203_PBYTE_Pos) /*!< GPIO_PORT B203: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B204 ----------------------------------------- -#define GPIO_PORT_B204_PBYTE_Pos 0 /*!< GPIO_PORT B204: PBYTE Position */ -#define GPIO_PORT_B204_PBYTE_Msk (0x01UL << GPIO_PORT_B204_PBYTE_Pos) /*!< GPIO_PORT B204: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B205 ----------------------------------------- -#define GPIO_PORT_B205_PBYTE_Pos 0 /*!< GPIO_PORT B205: PBYTE Position */ -#define GPIO_PORT_B205_PBYTE_Msk (0x01UL << GPIO_PORT_B205_PBYTE_Pos) /*!< GPIO_PORT B205: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B206 ----------------------------------------- -#define GPIO_PORT_B206_PBYTE_Pos 0 /*!< GPIO_PORT B206: PBYTE Position */ -#define GPIO_PORT_B206_PBYTE_Msk (0x01UL << GPIO_PORT_B206_PBYTE_Pos) /*!< GPIO_PORT B206: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B207 ----------------------------------------- -#define GPIO_PORT_B207_PBYTE_Pos 0 /*!< GPIO_PORT B207: PBYTE Position */ -#define GPIO_PORT_B207_PBYTE_Msk (0x01UL << GPIO_PORT_B207_PBYTE_Pos) /*!< GPIO_PORT B207: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B208 ----------------------------------------- -#define GPIO_PORT_B208_PBYTE_Pos 0 /*!< GPIO_PORT B208: PBYTE Position */ -#define GPIO_PORT_B208_PBYTE_Msk (0x01UL << GPIO_PORT_B208_PBYTE_Pos) /*!< GPIO_PORT B208: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B209 ----------------------------------------- -#define GPIO_PORT_B209_PBYTE_Pos 0 /*!< GPIO_PORT B209: PBYTE Position */ -#define GPIO_PORT_B209_PBYTE_Msk (0x01UL << GPIO_PORT_B209_PBYTE_Pos) /*!< GPIO_PORT B209: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B210 ----------------------------------------- -#define GPIO_PORT_B210_PBYTE_Pos 0 /*!< GPIO_PORT B210: PBYTE Position */ -#define GPIO_PORT_B210_PBYTE_Msk (0x01UL << GPIO_PORT_B210_PBYTE_Pos) /*!< GPIO_PORT B210: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B211 ----------------------------------------- -#define GPIO_PORT_B211_PBYTE_Pos 0 /*!< GPIO_PORT B211: PBYTE Position */ -#define GPIO_PORT_B211_PBYTE_Msk (0x01UL << GPIO_PORT_B211_PBYTE_Pos) /*!< GPIO_PORT B211: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B212 ----------------------------------------- -#define GPIO_PORT_B212_PBYTE_Pos 0 /*!< GPIO_PORT B212: PBYTE Position */ -#define GPIO_PORT_B212_PBYTE_Msk (0x01UL << GPIO_PORT_B212_PBYTE_Pos) /*!< GPIO_PORT B212: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B213 ----------------------------------------- -#define GPIO_PORT_B213_PBYTE_Pos 0 /*!< GPIO_PORT B213: PBYTE Position */ -#define GPIO_PORT_B213_PBYTE_Msk (0x01UL << GPIO_PORT_B213_PBYTE_Pos) /*!< GPIO_PORT B213: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B214 ----------------------------------------- -#define GPIO_PORT_B214_PBYTE_Pos 0 /*!< GPIO_PORT B214: PBYTE Position */ -#define GPIO_PORT_B214_PBYTE_Msk (0x01UL << GPIO_PORT_B214_PBYTE_Pos) /*!< GPIO_PORT B214: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B215 ----------------------------------------- -#define GPIO_PORT_B215_PBYTE_Pos 0 /*!< GPIO_PORT B215: PBYTE Position */ -#define GPIO_PORT_B215_PBYTE_Msk (0x01UL << GPIO_PORT_B215_PBYTE_Pos) /*!< GPIO_PORT B215: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B216 ----------------------------------------- -#define GPIO_PORT_B216_PBYTE_Pos 0 /*!< GPIO_PORT B216: PBYTE Position */ -#define GPIO_PORT_B216_PBYTE_Msk (0x01UL << GPIO_PORT_B216_PBYTE_Pos) /*!< GPIO_PORT B216: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B217 ----------------------------------------- -#define GPIO_PORT_B217_PBYTE_Pos 0 /*!< GPIO_PORT B217: PBYTE Position */ -#define GPIO_PORT_B217_PBYTE_Msk (0x01UL << GPIO_PORT_B217_PBYTE_Pos) /*!< GPIO_PORT B217: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B218 ----------------------------------------- -#define GPIO_PORT_B218_PBYTE_Pos 0 /*!< GPIO_PORT B218: PBYTE Position */ -#define GPIO_PORT_B218_PBYTE_Msk (0x01UL << GPIO_PORT_B218_PBYTE_Pos) /*!< GPIO_PORT B218: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B219 ----------------------------------------- -#define GPIO_PORT_B219_PBYTE_Pos 0 /*!< GPIO_PORT B219: PBYTE Position */ -#define GPIO_PORT_B219_PBYTE_Msk (0x01UL << GPIO_PORT_B219_PBYTE_Pos) /*!< GPIO_PORT B219: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B220 ----------------------------------------- -#define GPIO_PORT_B220_PBYTE_Pos 0 /*!< GPIO_PORT B220: PBYTE Position */ -#define GPIO_PORT_B220_PBYTE_Msk (0x01UL << GPIO_PORT_B220_PBYTE_Pos) /*!< GPIO_PORT B220: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B221 ----------------------------------------- -#define GPIO_PORT_B221_PBYTE_Pos 0 /*!< GPIO_PORT B221: PBYTE Position */ -#define GPIO_PORT_B221_PBYTE_Msk (0x01UL << GPIO_PORT_B221_PBYTE_Pos) /*!< GPIO_PORT B221: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B222 ----------------------------------------- -#define GPIO_PORT_B222_PBYTE_Pos 0 /*!< GPIO_PORT B222: PBYTE Position */ -#define GPIO_PORT_B222_PBYTE_Msk (0x01UL << GPIO_PORT_B222_PBYTE_Pos) /*!< GPIO_PORT B222: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B223 ----------------------------------------- -#define GPIO_PORT_B223_PBYTE_Pos 0 /*!< GPIO_PORT B223: PBYTE Position */ -#define GPIO_PORT_B223_PBYTE_Msk (0x01UL << GPIO_PORT_B223_PBYTE_Pos) /*!< GPIO_PORT B223: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B224 ----------------------------------------- -#define GPIO_PORT_B224_PBYTE_Pos 0 /*!< GPIO_PORT B224: PBYTE Position */ -#define GPIO_PORT_B224_PBYTE_Msk (0x01UL << GPIO_PORT_B224_PBYTE_Pos) /*!< GPIO_PORT B224: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B225 ----------------------------------------- -#define GPIO_PORT_B225_PBYTE_Pos 0 /*!< GPIO_PORT B225: PBYTE Position */ -#define GPIO_PORT_B225_PBYTE_Msk (0x01UL << GPIO_PORT_B225_PBYTE_Pos) /*!< GPIO_PORT B225: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B226 ----------------------------------------- -#define GPIO_PORT_B226_PBYTE_Pos 0 /*!< GPIO_PORT B226: PBYTE Position */ -#define GPIO_PORT_B226_PBYTE_Msk (0x01UL << GPIO_PORT_B226_PBYTE_Pos) /*!< GPIO_PORT B226: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B227 ----------------------------------------- -#define GPIO_PORT_B227_PBYTE_Pos 0 /*!< GPIO_PORT B227: PBYTE Position */ -#define GPIO_PORT_B227_PBYTE_Msk (0x01UL << GPIO_PORT_B227_PBYTE_Pos) /*!< GPIO_PORT B227: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B228 ----------------------------------------- -#define GPIO_PORT_B228_PBYTE_Pos 0 /*!< GPIO_PORT B228: PBYTE Position */ -#define GPIO_PORT_B228_PBYTE_Msk (0x01UL << GPIO_PORT_B228_PBYTE_Pos) /*!< GPIO_PORT B228: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B229 ----------------------------------------- -#define GPIO_PORT_B229_PBYTE_Pos 0 /*!< GPIO_PORT B229: PBYTE Position */ -#define GPIO_PORT_B229_PBYTE_Msk (0x01UL << GPIO_PORT_B229_PBYTE_Pos) /*!< GPIO_PORT B229: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B230 ----------------------------------------- -#define GPIO_PORT_B230_PBYTE_Pos 0 /*!< GPIO_PORT B230: PBYTE Position */ -#define GPIO_PORT_B230_PBYTE_Msk (0x01UL << GPIO_PORT_B230_PBYTE_Pos) /*!< GPIO_PORT B230: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B231 ----------------------------------------- -#define GPIO_PORT_B231_PBYTE_Pos 0 /*!< GPIO_PORT B231: PBYTE Position */ -#define GPIO_PORT_B231_PBYTE_Msk (0x01UL << GPIO_PORT_B231_PBYTE_Pos) /*!< GPIO_PORT B231: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B232 ----------------------------------------- -#define GPIO_PORT_B232_PBYTE_Pos 0 /*!< GPIO_PORT B232: PBYTE Position */ -#define GPIO_PORT_B232_PBYTE_Msk (0x01UL << GPIO_PORT_B232_PBYTE_Pos) /*!< GPIO_PORT B232: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B233 ----------------------------------------- -#define GPIO_PORT_B233_PBYTE_Pos 0 /*!< GPIO_PORT B233: PBYTE Position */ -#define GPIO_PORT_B233_PBYTE_Msk (0x01UL << GPIO_PORT_B233_PBYTE_Pos) /*!< GPIO_PORT B233: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B234 ----------------------------------------- -#define GPIO_PORT_B234_PBYTE_Pos 0 /*!< GPIO_PORT B234: PBYTE Position */ -#define GPIO_PORT_B234_PBYTE_Msk (0x01UL << GPIO_PORT_B234_PBYTE_Pos) /*!< GPIO_PORT B234: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B235 ----------------------------------------- -#define GPIO_PORT_B235_PBYTE_Pos 0 /*!< GPIO_PORT B235: PBYTE Position */ -#define GPIO_PORT_B235_PBYTE_Msk (0x01UL << GPIO_PORT_B235_PBYTE_Pos) /*!< GPIO_PORT B235: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B236 ----------------------------------------- -#define GPIO_PORT_B236_PBYTE_Pos 0 /*!< GPIO_PORT B236: PBYTE Position */ -#define GPIO_PORT_B236_PBYTE_Msk (0x01UL << GPIO_PORT_B236_PBYTE_Pos) /*!< GPIO_PORT B236: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B237 ----------------------------------------- -#define GPIO_PORT_B237_PBYTE_Pos 0 /*!< GPIO_PORT B237: PBYTE Position */ -#define GPIO_PORT_B237_PBYTE_Msk (0x01UL << GPIO_PORT_B237_PBYTE_Pos) /*!< GPIO_PORT B237: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B238 ----------------------------------------- -#define GPIO_PORT_B238_PBYTE_Pos 0 /*!< GPIO_PORT B238: PBYTE Position */ -#define GPIO_PORT_B238_PBYTE_Msk (0x01UL << GPIO_PORT_B238_PBYTE_Pos) /*!< GPIO_PORT B238: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B239 ----------------------------------------- -#define GPIO_PORT_B239_PBYTE_Pos 0 /*!< GPIO_PORT B239: PBYTE Position */ -#define GPIO_PORT_B239_PBYTE_Msk (0x01UL << GPIO_PORT_B239_PBYTE_Pos) /*!< GPIO_PORT B239: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B240 ----------------------------------------- -#define GPIO_PORT_B240_PBYTE_Pos 0 /*!< GPIO_PORT B240: PBYTE Position */ -#define GPIO_PORT_B240_PBYTE_Msk (0x01UL << GPIO_PORT_B240_PBYTE_Pos) /*!< GPIO_PORT B240: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B241 ----------------------------------------- -#define GPIO_PORT_B241_PBYTE_Pos 0 /*!< GPIO_PORT B241: PBYTE Position */ -#define GPIO_PORT_B241_PBYTE_Msk (0x01UL << GPIO_PORT_B241_PBYTE_Pos) /*!< GPIO_PORT B241: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B242 ----------------------------------------- -#define GPIO_PORT_B242_PBYTE_Pos 0 /*!< GPIO_PORT B242: PBYTE Position */ -#define GPIO_PORT_B242_PBYTE_Msk (0x01UL << GPIO_PORT_B242_PBYTE_Pos) /*!< GPIO_PORT B242: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B243 ----------------------------------------- -#define GPIO_PORT_B243_PBYTE_Pos 0 /*!< GPIO_PORT B243: PBYTE Position */ -#define GPIO_PORT_B243_PBYTE_Msk (0x01UL << GPIO_PORT_B243_PBYTE_Pos) /*!< GPIO_PORT B243: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B244 ----------------------------------------- -#define GPIO_PORT_B244_PBYTE_Pos 0 /*!< GPIO_PORT B244: PBYTE Position */ -#define GPIO_PORT_B244_PBYTE_Msk (0x01UL << GPIO_PORT_B244_PBYTE_Pos) /*!< GPIO_PORT B244: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B245 ----------------------------------------- -#define GPIO_PORT_B245_PBYTE_Pos 0 /*!< GPIO_PORT B245: PBYTE Position */ -#define GPIO_PORT_B245_PBYTE_Msk (0x01UL << GPIO_PORT_B245_PBYTE_Pos) /*!< GPIO_PORT B245: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B246 ----------------------------------------- -#define GPIO_PORT_B246_PBYTE_Pos 0 /*!< GPIO_PORT B246: PBYTE Position */ -#define GPIO_PORT_B246_PBYTE_Msk (0x01UL << GPIO_PORT_B246_PBYTE_Pos) /*!< GPIO_PORT B246: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B247 ----------------------------------------- -#define GPIO_PORT_B247_PBYTE_Pos 0 /*!< GPIO_PORT B247: PBYTE Position */ -#define GPIO_PORT_B247_PBYTE_Msk (0x01UL << GPIO_PORT_B247_PBYTE_Pos) /*!< GPIO_PORT B247: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B248 ----------------------------------------- -#define GPIO_PORT_B248_PBYTE_Pos 0 /*!< GPIO_PORT B248: PBYTE Position */ -#define GPIO_PORT_B248_PBYTE_Msk (0x01UL << GPIO_PORT_B248_PBYTE_Pos) /*!< GPIO_PORT B248: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B249 ----------------------------------------- -#define GPIO_PORT_B249_PBYTE_Pos 0 /*!< GPIO_PORT B249: PBYTE Position */ -#define GPIO_PORT_B249_PBYTE_Msk (0x01UL << GPIO_PORT_B249_PBYTE_Pos) /*!< GPIO_PORT B249: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B250 ----------------------------------------- -#define GPIO_PORT_B250_PBYTE_Pos 0 /*!< GPIO_PORT B250: PBYTE Position */ -#define GPIO_PORT_B250_PBYTE_Msk (0x01UL << GPIO_PORT_B250_PBYTE_Pos) /*!< GPIO_PORT B250: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B251 ----------------------------------------- -#define GPIO_PORT_B251_PBYTE_Pos 0 /*!< GPIO_PORT B251: PBYTE Position */ -#define GPIO_PORT_B251_PBYTE_Msk (0x01UL << GPIO_PORT_B251_PBYTE_Pos) /*!< GPIO_PORT B251: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B252 ----------------------------------------- -#define GPIO_PORT_B252_PBYTE_Pos 0 /*!< GPIO_PORT B252: PBYTE Position */ -#define GPIO_PORT_B252_PBYTE_Msk (0x01UL << GPIO_PORT_B252_PBYTE_Pos) /*!< GPIO_PORT B252: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B253 ----------------------------------------- -#define GPIO_PORT_B253_PBYTE_Pos 0 /*!< GPIO_PORT B253: PBYTE Position */ -#define GPIO_PORT_B253_PBYTE_Msk (0x01UL << GPIO_PORT_B253_PBYTE_Pos) /*!< GPIO_PORT B253: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B254 ----------------------------------------- -#define GPIO_PORT_B254_PBYTE_Pos 0 /*!< GPIO_PORT B254: PBYTE Position */ -#define GPIO_PORT_B254_PBYTE_Msk (0x01UL << GPIO_PORT_B254_PBYTE_Pos) /*!< GPIO_PORT B254: PBYTE Mask */ - -// ------------------------------------- GPIO_PORT_B255 ----------------------------------------- -#define GPIO_PORT_B255_PBYTE_Pos 0 /*!< GPIO_PORT B255: PBYTE Position */ -#define GPIO_PORT_B255_PBYTE_Msk (0x01UL << GPIO_PORT_B255_PBYTE_Pos) /*!< GPIO_PORT B255: PBYTE Mask */ - -// -------------------------------------- GPIO_PORT_W0 ------------------------------------------ -#define GPIO_PORT_W0_PWORD_Pos 0 /*!< GPIO_PORT W0: PWORD Position */ -#define GPIO_PORT_W0_PWORD_Msk (0xffffffffUL << GPIO_PORT_W0_PWORD_Pos) /*!< GPIO_PORT W0: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W1 ------------------------------------------ -#define GPIO_PORT_W1_PWORD_Pos 0 /*!< GPIO_PORT W1: PWORD Position */ -#define GPIO_PORT_W1_PWORD_Msk (0xffffffffUL << GPIO_PORT_W1_PWORD_Pos) /*!< GPIO_PORT W1: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W2 ------------------------------------------ -#define GPIO_PORT_W2_PWORD_Pos 0 /*!< GPIO_PORT W2: PWORD Position */ -#define GPIO_PORT_W2_PWORD_Msk (0xffffffffUL << GPIO_PORT_W2_PWORD_Pos) /*!< GPIO_PORT W2: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W3 ------------------------------------------ -#define GPIO_PORT_W3_PWORD_Pos 0 /*!< GPIO_PORT W3: PWORD Position */ -#define GPIO_PORT_W3_PWORD_Msk (0xffffffffUL << GPIO_PORT_W3_PWORD_Pos) /*!< GPIO_PORT W3: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W4 ------------------------------------------ -#define GPIO_PORT_W4_PWORD_Pos 0 /*!< GPIO_PORT W4: PWORD Position */ -#define GPIO_PORT_W4_PWORD_Msk (0xffffffffUL << GPIO_PORT_W4_PWORD_Pos) /*!< GPIO_PORT W4: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W5 ------------------------------------------ -#define GPIO_PORT_W5_PWORD_Pos 0 /*!< GPIO_PORT W5: PWORD Position */ -#define GPIO_PORT_W5_PWORD_Msk (0xffffffffUL << GPIO_PORT_W5_PWORD_Pos) /*!< GPIO_PORT W5: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W6 ------------------------------------------ -#define GPIO_PORT_W6_PWORD_Pos 0 /*!< GPIO_PORT W6: PWORD Position */ -#define GPIO_PORT_W6_PWORD_Msk (0xffffffffUL << GPIO_PORT_W6_PWORD_Pos) /*!< GPIO_PORT W6: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W7 ------------------------------------------ -#define GPIO_PORT_W7_PWORD_Pos 0 /*!< GPIO_PORT W7: PWORD Position */ -#define GPIO_PORT_W7_PWORD_Msk (0xffffffffUL << GPIO_PORT_W7_PWORD_Pos) /*!< GPIO_PORT W7: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W8 ------------------------------------------ -#define GPIO_PORT_W8_PWORD_Pos 0 /*!< GPIO_PORT W8: PWORD Position */ -#define GPIO_PORT_W8_PWORD_Msk (0xffffffffUL << GPIO_PORT_W8_PWORD_Pos) /*!< GPIO_PORT W8: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W9 ------------------------------------------ -#define GPIO_PORT_W9_PWORD_Pos 0 /*!< GPIO_PORT W9: PWORD Position */ -#define GPIO_PORT_W9_PWORD_Msk (0xffffffffUL << GPIO_PORT_W9_PWORD_Pos) /*!< GPIO_PORT W9: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W10 ----------------------------------------- -#define GPIO_PORT_W10_PWORD_Pos 0 /*!< GPIO_PORT W10: PWORD Position */ -#define GPIO_PORT_W10_PWORD_Msk (0xffffffffUL << GPIO_PORT_W10_PWORD_Pos) /*!< GPIO_PORT W10: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W11 ----------------------------------------- -#define GPIO_PORT_W11_PWORD_Pos 0 /*!< GPIO_PORT W11: PWORD Position */ -#define GPIO_PORT_W11_PWORD_Msk (0xffffffffUL << GPIO_PORT_W11_PWORD_Pos) /*!< GPIO_PORT W11: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W12 ----------------------------------------- -#define GPIO_PORT_W12_PWORD_Pos 0 /*!< GPIO_PORT W12: PWORD Position */ -#define GPIO_PORT_W12_PWORD_Msk (0xffffffffUL << GPIO_PORT_W12_PWORD_Pos) /*!< GPIO_PORT W12: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W13 ----------------------------------------- -#define GPIO_PORT_W13_PWORD_Pos 0 /*!< GPIO_PORT W13: PWORD Position */ -#define GPIO_PORT_W13_PWORD_Msk (0xffffffffUL << GPIO_PORT_W13_PWORD_Pos) /*!< GPIO_PORT W13: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W14 ----------------------------------------- -#define GPIO_PORT_W14_PWORD_Pos 0 /*!< GPIO_PORT W14: PWORD Position */ -#define GPIO_PORT_W14_PWORD_Msk (0xffffffffUL << GPIO_PORT_W14_PWORD_Pos) /*!< GPIO_PORT W14: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W15 ----------------------------------------- -#define GPIO_PORT_W15_PWORD_Pos 0 /*!< GPIO_PORT W15: PWORD Position */ -#define GPIO_PORT_W15_PWORD_Msk (0xffffffffUL << GPIO_PORT_W15_PWORD_Pos) /*!< GPIO_PORT W15: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W16 ----------------------------------------- -#define GPIO_PORT_W16_PWORD_Pos 0 /*!< GPIO_PORT W16: PWORD Position */ -#define GPIO_PORT_W16_PWORD_Msk (0xffffffffUL << GPIO_PORT_W16_PWORD_Pos) /*!< GPIO_PORT W16: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W17 ----------------------------------------- -#define GPIO_PORT_W17_PWORD_Pos 0 /*!< GPIO_PORT W17: PWORD Position */ -#define GPIO_PORT_W17_PWORD_Msk (0xffffffffUL << GPIO_PORT_W17_PWORD_Pos) /*!< GPIO_PORT W17: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W18 ----------------------------------------- -#define GPIO_PORT_W18_PWORD_Pos 0 /*!< GPIO_PORT W18: PWORD Position */ -#define GPIO_PORT_W18_PWORD_Msk (0xffffffffUL << GPIO_PORT_W18_PWORD_Pos) /*!< GPIO_PORT W18: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W19 ----------------------------------------- -#define GPIO_PORT_W19_PWORD_Pos 0 /*!< GPIO_PORT W19: PWORD Position */ -#define GPIO_PORT_W19_PWORD_Msk (0xffffffffUL << GPIO_PORT_W19_PWORD_Pos) /*!< GPIO_PORT W19: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W20 ----------------------------------------- -#define GPIO_PORT_W20_PWORD_Pos 0 /*!< GPIO_PORT W20: PWORD Position */ -#define GPIO_PORT_W20_PWORD_Msk (0xffffffffUL << GPIO_PORT_W20_PWORD_Pos) /*!< GPIO_PORT W20: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W21 ----------------------------------------- -#define GPIO_PORT_W21_PWORD_Pos 0 /*!< GPIO_PORT W21: PWORD Position */ -#define GPIO_PORT_W21_PWORD_Msk (0xffffffffUL << GPIO_PORT_W21_PWORD_Pos) /*!< GPIO_PORT W21: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W22 ----------------------------------------- -#define GPIO_PORT_W22_PWORD_Pos 0 /*!< GPIO_PORT W22: PWORD Position */ -#define GPIO_PORT_W22_PWORD_Msk (0xffffffffUL << GPIO_PORT_W22_PWORD_Pos) /*!< GPIO_PORT W22: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W23 ----------------------------------------- -#define GPIO_PORT_W23_PWORD_Pos 0 /*!< GPIO_PORT W23: PWORD Position */ -#define GPIO_PORT_W23_PWORD_Msk (0xffffffffUL << GPIO_PORT_W23_PWORD_Pos) /*!< GPIO_PORT W23: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W24 ----------------------------------------- -#define GPIO_PORT_W24_PWORD_Pos 0 /*!< GPIO_PORT W24: PWORD Position */ -#define GPIO_PORT_W24_PWORD_Msk (0xffffffffUL << GPIO_PORT_W24_PWORD_Pos) /*!< GPIO_PORT W24: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W25 ----------------------------------------- -#define GPIO_PORT_W25_PWORD_Pos 0 /*!< GPIO_PORT W25: PWORD Position */ -#define GPIO_PORT_W25_PWORD_Msk (0xffffffffUL << GPIO_PORT_W25_PWORD_Pos) /*!< GPIO_PORT W25: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W26 ----------------------------------------- -#define GPIO_PORT_W26_PWORD_Pos 0 /*!< GPIO_PORT W26: PWORD Position */ -#define GPIO_PORT_W26_PWORD_Msk (0xffffffffUL << GPIO_PORT_W26_PWORD_Pos) /*!< GPIO_PORT W26: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W27 ----------------------------------------- -#define GPIO_PORT_W27_PWORD_Pos 0 /*!< GPIO_PORT W27: PWORD Position */ -#define GPIO_PORT_W27_PWORD_Msk (0xffffffffUL << GPIO_PORT_W27_PWORD_Pos) /*!< GPIO_PORT W27: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W28 ----------------------------------------- -#define GPIO_PORT_W28_PWORD_Pos 0 /*!< GPIO_PORT W28: PWORD Position */ -#define GPIO_PORT_W28_PWORD_Msk (0xffffffffUL << GPIO_PORT_W28_PWORD_Pos) /*!< GPIO_PORT W28: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W29 ----------------------------------------- -#define GPIO_PORT_W29_PWORD_Pos 0 /*!< GPIO_PORT W29: PWORD Position */ -#define GPIO_PORT_W29_PWORD_Msk (0xffffffffUL << GPIO_PORT_W29_PWORD_Pos) /*!< GPIO_PORT W29: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W30 ----------------------------------------- -#define GPIO_PORT_W30_PWORD_Pos 0 /*!< GPIO_PORT W30: PWORD Position */ -#define GPIO_PORT_W30_PWORD_Msk (0xffffffffUL << GPIO_PORT_W30_PWORD_Pos) /*!< GPIO_PORT W30: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W31 ----------------------------------------- -#define GPIO_PORT_W31_PWORD_Pos 0 /*!< GPIO_PORT W31: PWORD Position */ -#define GPIO_PORT_W31_PWORD_Msk (0xffffffffUL << GPIO_PORT_W31_PWORD_Pos) /*!< GPIO_PORT W31: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W32 ----------------------------------------- -#define GPIO_PORT_W32_PWORD_Pos 0 /*!< GPIO_PORT W32: PWORD Position */ -#define GPIO_PORT_W32_PWORD_Msk (0xffffffffUL << GPIO_PORT_W32_PWORD_Pos) /*!< GPIO_PORT W32: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W33 ----------------------------------------- -#define GPIO_PORT_W33_PWORD_Pos 0 /*!< GPIO_PORT W33: PWORD Position */ -#define GPIO_PORT_W33_PWORD_Msk (0xffffffffUL << GPIO_PORT_W33_PWORD_Pos) /*!< GPIO_PORT W33: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W34 ----------------------------------------- -#define GPIO_PORT_W34_PWORD_Pos 0 /*!< GPIO_PORT W34: PWORD Position */ -#define GPIO_PORT_W34_PWORD_Msk (0xffffffffUL << GPIO_PORT_W34_PWORD_Pos) /*!< GPIO_PORT W34: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W35 ----------------------------------------- -#define GPIO_PORT_W35_PWORD_Pos 0 /*!< GPIO_PORT W35: PWORD Position */ -#define GPIO_PORT_W35_PWORD_Msk (0xffffffffUL << GPIO_PORT_W35_PWORD_Pos) /*!< GPIO_PORT W35: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W36 ----------------------------------------- -#define GPIO_PORT_W36_PWORD_Pos 0 /*!< GPIO_PORT W36: PWORD Position */ -#define GPIO_PORT_W36_PWORD_Msk (0xffffffffUL << GPIO_PORT_W36_PWORD_Pos) /*!< GPIO_PORT W36: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W37 ----------------------------------------- -#define GPIO_PORT_W37_PWORD_Pos 0 /*!< GPIO_PORT W37: PWORD Position */ -#define GPIO_PORT_W37_PWORD_Msk (0xffffffffUL << GPIO_PORT_W37_PWORD_Pos) /*!< GPIO_PORT W37: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W38 ----------------------------------------- -#define GPIO_PORT_W38_PWORD_Pos 0 /*!< GPIO_PORT W38: PWORD Position */ -#define GPIO_PORT_W38_PWORD_Msk (0xffffffffUL << GPIO_PORT_W38_PWORD_Pos) /*!< GPIO_PORT W38: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W39 ----------------------------------------- -#define GPIO_PORT_W39_PWORD_Pos 0 /*!< GPIO_PORT W39: PWORD Position */ -#define GPIO_PORT_W39_PWORD_Msk (0xffffffffUL << GPIO_PORT_W39_PWORD_Pos) /*!< GPIO_PORT W39: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W40 ----------------------------------------- -#define GPIO_PORT_W40_PWORD_Pos 0 /*!< GPIO_PORT W40: PWORD Position */ -#define GPIO_PORT_W40_PWORD_Msk (0xffffffffUL << GPIO_PORT_W40_PWORD_Pos) /*!< GPIO_PORT W40: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W41 ----------------------------------------- -#define GPIO_PORT_W41_PWORD_Pos 0 /*!< GPIO_PORT W41: PWORD Position */ -#define GPIO_PORT_W41_PWORD_Msk (0xffffffffUL << GPIO_PORT_W41_PWORD_Pos) /*!< GPIO_PORT W41: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W42 ----------------------------------------- -#define GPIO_PORT_W42_PWORD_Pos 0 /*!< GPIO_PORT W42: PWORD Position */ -#define GPIO_PORT_W42_PWORD_Msk (0xffffffffUL << GPIO_PORT_W42_PWORD_Pos) /*!< GPIO_PORT W42: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W43 ----------------------------------------- -#define GPIO_PORT_W43_PWORD_Pos 0 /*!< GPIO_PORT W43: PWORD Position */ -#define GPIO_PORT_W43_PWORD_Msk (0xffffffffUL << GPIO_PORT_W43_PWORD_Pos) /*!< GPIO_PORT W43: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W44 ----------------------------------------- -#define GPIO_PORT_W44_PWORD_Pos 0 /*!< GPIO_PORT W44: PWORD Position */ -#define GPIO_PORT_W44_PWORD_Msk (0xffffffffUL << GPIO_PORT_W44_PWORD_Pos) /*!< GPIO_PORT W44: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W45 ----------------------------------------- -#define GPIO_PORT_W45_PWORD_Pos 0 /*!< GPIO_PORT W45: PWORD Position */ -#define GPIO_PORT_W45_PWORD_Msk (0xffffffffUL << GPIO_PORT_W45_PWORD_Pos) /*!< GPIO_PORT W45: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W46 ----------------------------------------- -#define GPIO_PORT_W46_PWORD_Pos 0 /*!< GPIO_PORT W46: PWORD Position */ -#define GPIO_PORT_W46_PWORD_Msk (0xffffffffUL << GPIO_PORT_W46_PWORD_Pos) /*!< GPIO_PORT W46: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W47 ----------------------------------------- -#define GPIO_PORT_W47_PWORD_Pos 0 /*!< GPIO_PORT W47: PWORD Position */ -#define GPIO_PORT_W47_PWORD_Msk (0xffffffffUL << GPIO_PORT_W47_PWORD_Pos) /*!< GPIO_PORT W47: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W48 ----------------------------------------- -#define GPIO_PORT_W48_PWORD_Pos 0 /*!< GPIO_PORT W48: PWORD Position */ -#define GPIO_PORT_W48_PWORD_Msk (0xffffffffUL << GPIO_PORT_W48_PWORD_Pos) /*!< GPIO_PORT W48: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W49 ----------------------------------------- -#define GPIO_PORT_W49_PWORD_Pos 0 /*!< GPIO_PORT W49: PWORD Position */ -#define GPIO_PORT_W49_PWORD_Msk (0xffffffffUL << GPIO_PORT_W49_PWORD_Pos) /*!< GPIO_PORT W49: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W50 ----------------------------------------- -#define GPIO_PORT_W50_PWORD_Pos 0 /*!< GPIO_PORT W50: PWORD Position */ -#define GPIO_PORT_W50_PWORD_Msk (0xffffffffUL << GPIO_PORT_W50_PWORD_Pos) /*!< GPIO_PORT W50: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W51 ----------------------------------------- -#define GPIO_PORT_W51_PWORD_Pos 0 /*!< GPIO_PORT W51: PWORD Position */ -#define GPIO_PORT_W51_PWORD_Msk (0xffffffffUL << GPIO_PORT_W51_PWORD_Pos) /*!< GPIO_PORT W51: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W52 ----------------------------------------- -#define GPIO_PORT_W52_PWORD_Pos 0 /*!< GPIO_PORT W52: PWORD Position */ -#define GPIO_PORT_W52_PWORD_Msk (0xffffffffUL << GPIO_PORT_W52_PWORD_Pos) /*!< GPIO_PORT W52: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W53 ----------------------------------------- -#define GPIO_PORT_W53_PWORD_Pos 0 /*!< GPIO_PORT W53: PWORD Position */ -#define GPIO_PORT_W53_PWORD_Msk (0xffffffffUL << GPIO_PORT_W53_PWORD_Pos) /*!< GPIO_PORT W53: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W54 ----------------------------------------- -#define GPIO_PORT_W54_PWORD_Pos 0 /*!< GPIO_PORT W54: PWORD Position */ -#define GPIO_PORT_W54_PWORD_Msk (0xffffffffUL << GPIO_PORT_W54_PWORD_Pos) /*!< GPIO_PORT W54: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W55 ----------------------------------------- -#define GPIO_PORT_W55_PWORD_Pos 0 /*!< GPIO_PORT W55: PWORD Position */ -#define GPIO_PORT_W55_PWORD_Msk (0xffffffffUL << GPIO_PORT_W55_PWORD_Pos) /*!< GPIO_PORT W55: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W56 ----------------------------------------- -#define GPIO_PORT_W56_PWORD_Pos 0 /*!< GPIO_PORT W56: PWORD Position */ -#define GPIO_PORT_W56_PWORD_Msk (0xffffffffUL << GPIO_PORT_W56_PWORD_Pos) /*!< GPIO_PORT W56: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W57 ----------------------------------------- -#define GPIO_PORT_W57_PWORD_Pos 0 /*!< GPIO_PORT W57: PWORD Position */ -#define GPIO_PORT_W57_PWORD_Msk (0xffffffffUL << GPIO_PORT_W57_PWORD_Pos) /*!< GPIO_PORT W57: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W58 ----------------------------------------- -#define GPIO_PORT_W58_PWORD_Pos 0 /*!< GPIO_PORT W58: PWORD Position */ -#define GPIO_PORT_W58_PWORD_Msk (0xffffffffUL << GPIO_PORT_W58_PWORD_Pos) /*!< GPIO_PORT W58: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W59 ----------------------------------------- -#define GPIO_PORT_W59_PWORD_Pos 0 /*!< GPIO_PORT W59: PWORD Position */ -#define GPIO_PORT_W59_PWORD_Msk (0xffffffffUL << GPIO_PORT_W59_PWORD_Pos) /*!< GPIO_PORT W59: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W60 ----------------------------------------- -#define GPIO_PORT_W60_PWORD_Pos 0 /*!< GPIO_PORT W60: PWORD Position */ -#define GPIO_PORT_W60_PWORD_Msk (0xffffffffUL << GPIO_PORT_W60_PWORD_Pos) /*!< GPIO_PORT W60: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W61 ----------------------------------------- -#define GPIO_PORT_W61_PWORD_Pos 0 /*!< GPIO_PORT W61: PWORD Position */ -#define GPIO_PORT_W61_PWORD_Msk (0xffffffffUL << GPIO_PORT_W61_PWORD_Pos) /*!< GPIO_PORT W61: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W62 ----------------------------------------- -#define GPIO_PORT_W62_PWORD_Pos 0 /*!< GPIO_PORT W62: PWORD Position */ -#define GPIO_PORT_W62_PWORD_Msk (0xffffffffUL << GPIO_PORT_W62_PWORD_Pos) /*!< GPIO_PORT W62: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W63 ----------------------------------------- -#define GPIO_PORT_W63_PWORD_Pos 0 /*!< GPIO_PORT W63: PWORD Position */ -#define GPIO_PORT_W63_PWORD_Msk (0xffffffffUL << GPIO_PORT_W63_PWORD_Pos) /*!< GPIO_PORT W63: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W64 ----------------------------------------- -#define GPIO_PORT_W64_PWORD_Pos 0 /*!< GPIO_PORT W64: PWORD Position */ -#define GPIO_PORT_W64_PWORD_Msk (0xffffffffUL << GPIO_PORT_W64_PWORD_Pos) /*!< GPIO_PORT W64: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W65 ----------------------------------------- -#define GPIO_PORT_W65_PWORD_Pos 0 /*!< GPIO_PORT W65: PWORD Position */ -#define GPIO_PORT_W65_PWORD_Msk (0xffffffffUL << GPIO_PORT_W65_PWORD_Pos) /*!< GPIO_PORT W65: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W66 ----------------------------------------- -#define GPIO_PORT_W66_PWORD_Pos 0 /*!< GPIO_PORT W66: PWORD Position */ -#define GPIO_PORT_W66_PWORD_Msk (0xffffffffUL << GPIO_PORT_W66_PWORD_Pos) /*!< GPIO_PORT W66: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W67 ----------------------------------------- -#define GPIO_PORT_W67_PWORD_Pos 0 /*!< GPIO_PORT W67: PWORD Position */ -#define GPIO_PORT_W67_PWORD_Msk (0xffffffffUL << GPIO_PORT_W67_PWORD_Pos) /*!< GPIO_PORT W67: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W68 ----------------------------------------- -#define GPIO_PORT_W68_PWORD_Pos 0 /*!< GPIO_PORT W68: PWORD Position */ -#define GPIO_PORT_W68_PWORD_Msk (0xffffffffUL << GPIO_PORT_W68_PWORD_Pos) /*!< GPIO_PORT W68: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W69 ----------------------------------------- -#define GPIO_PORT_W69_PWORD_Pos 0 /*!< GPIO_PORT W69: PWORD Position */ -#define GPIO_PORT_W69_PWORD_Msk (0xffffffffUL << GPIO_PORT_W69_PWORD_Pos) /*!< GPIO_PORT W69: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W70 ----------------------------------------- -#define GPIO_PORT_W70_PWORD_Pos 0 /*!< GPIO_PORT W70: PWORD Position */ -#define GPIO_PORT_W70_PWORD_Msk (0xffffffffUL << GPIO_PORT_W70_PWORD_Pos) /*!< GPIO_PORT W70: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W71 ----------------------------------------- -#define GPIO_PORT_W71_PWORD_Pos 0 /*!< GPIO_PORT W71: PWORD Position */ -#define GPIO_PORT_W71_PWORD_Msk (0xffffffffUL << GPIO_PORT_W71_PWORD_Pos) /*!< GPIO_PORT W71: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W72 ----------------------------------------- -#define GPIO_PORT_W72_PWORD_Pos 0 /*!< GPIO_PORT W72: PWORD Position */ -#define GPIO_PORT_W72_PWORD_Msk (0xffffffffUL << GPIO_PORT_W72_PWORD_Pos) /*!< GPIO_PORT W72: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W73 ----------------------------------------- -#define GPIO_PORT_W73_PWORD_Pos 0 /*!< GPIO_PORT W73: PWORD Position */ -#define GPIO_PORT_W73_PWORD_Msk (0xffffffffUL << GPIO_PORT_W73_PWORD_Pos) /*!< GPIO_PORT W73: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W74 ----------------------------------------- -#define GPIO_PORT_W74_PWORD_Pos 0 /*!< GPIO_PORT W74: PWORD Position */ -#define GPIO_PORT_W74_PWORD_Msk (0xffffffffUL << GPIO_PORT_W74_PWORD_Pos) /*!< GPIO_PORT W74: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W75 ----------------------------------------- -#define GPIO_PORT_W75_PWORD_Pos 0 /*!< GPIO_PORT W75: PWORD Position */ -#define GPIO_PORT_W75_PWORD_Msk (0xffffffffUL << GPIO_PORT_W75_PWORD_Pos) /*!< GPIO_PORT W75: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W76 ----------------------------------------- -#define GPIO_PORT_W76_PWORD_Pos 0 /*!< GPIO_PORT W76: PWORD Position */ -#define GPIO_PORT_W76_PWORD_Msk (0xffffffffUL << GPIO_PORT_W76_PWORD_Pos) /*!< GPIO_PORT W76: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W77 ----------------------------------------- -#define GPIO_PORT_W77_PWORD_Pos 0 /*!< GPIO_PORT W77: PWORD Position */ -#define GPIO_PORT_W77_PWORD_Msk (0xffffffffUL << GPIO_PORT_W77_PWORD_Pos) /*!< GPIO_PORT W77: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W78 ----------------------------------------- -#define GPIO_PORT_W78_PWORD_Pos 0 /*!< GPIO_PORT W78: PWORD Position */ -#define GPIO_PORT_W78_PWORD_Msk (0xffffffffUL << GPIO_PORT_W78_PWORD_Pos) /*!< GPIO_PORT W78: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W79 ----------------------------------------- -#define GPIO_PORT_W79_PWORD_Pos 0 /*!< GPIO_PORT W79: PWORD Position */ -#define GPIO_PORT_W79_PWORD_Msk (0xffffffffUL << GPIO_PORT_W79_PWORD_Pos) /*!< GPIO_PORT W79: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W80 ----------------------------------------- -#define GPIO_PORT_W80_PWORD_Pos 0 /*!< GPIO_PORT W80: PWORD Position */ -#define GPIO_PORT_W80_PWORD_Msk (0xffffffffUL << GPIO_PORT_W80_PWORD_Pos) /*!< GPIO_PORT W80: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W81 ----------------------------------------- -#define GPIO_PORT_W81_PWORD_Pos 0 /*!< GPIO_PORT W81: PWORD Position */ -#define GPIO_PORT_W81_PWORD_Msk (0xffffffffUL << GPIO_PORT_W81_PWORD_Pos) /*!< GPIO_PORT W81: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W82 ----------------------------------------- -#define GPIO_PORT_W82_PWORD_Pos 0 /*!< GPIO_PORT W82: PWORD Position */ -#define GPIO_PORT_W82_PWORD_Msk (0xffffffffUL << GPIO_PORT_W82_PWORD_Pos) /*!< GPIO_PORT W82: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W83 ----------------------------------------- -#define GPIO_PORT_W83_PWORD_Pos 0 /*!< GPIO_PORT W83: PWORD Position */ -#define GPIO_PORT_W83_PWORD_Msk (0xffffffffUL << GPIO_PORT_W83_PWORD_Pos) /*!< GPIO_PORT W83: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W84 ----------------------------------------- -#define GPIO_PORT_W84_PWORD_Pos 0 /*!< GPIO_PORT W84: PWORD Position */ -#define GPIO_PORT_W84_PWORD_Msk (0xffffffffUL << GPIO_PORT_W84_PWORD_Pos) /*!< GPIO_PORT W84: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W85 ----------------------------------------- -#define GPIO_PORT_W85_PWORD_Pos 0 /*!< GPIO_PORT W85: PWORD Position */ -#define GPIO_PORT_W85_PWORD_Msk (0xffffffffUL << GPIO_PORT_W85_PWORD_Pos) /*!< GPIO_PORT W85: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W86 ----------------------------------------- -#define GPIO_PORT_W86_PWORD_Pos 0 /*!< GPIO_PORT W86: PWORD Position */ -#define GPIO_PORT_W86_PWORD_Msk (0xffffffffUL << GPIO_PORT_W86_PWORD_Pos) /*!< GPIO_PORT W86: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W87 ----------------------------------------- -#define GPIO_PORT_W87_PWORD_Pos 0 /*!< GPIO_PORT W87: PWORD Position */ -#define GPIO_PORT_W87_PWORD_Msk (0xffffffffUL << GPIO_PORT_W87_PWORD_Pos) /*!< GPIO_PORT W87: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W88 ----------------------------------------- -#define GPIO_PORT_W88_PWORD_Pos 0 /*!< GPIO_PORT W88: PWORD Position */ -#define GPIO_PORT_W88_PWORD_Msk (0xffffffffUL << GPIO_PORT_W88_PWORD_Pos) /*!< GPIO_PORT W88: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W89 ----------------------------------------- -#define GPIO_PORT_W89_PWORD_Pos 0 /*!< GPIO_PORT W89: PWORD Position */ -#define GPIO_PORT_W89_PWORD_Msk (0xffffffffUL << GPIO_PORT_W89_PWORD_Pos) /*!< GPIO_PORT W89: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W90 ----------------------------------------- -#define GPIO_PORT_W90_PWORD_Pos 0 /*!< GPIO_PORT W90: PWORD Position */ -#define GPIO_PORT_W90_PWORD_Msk (0xffffffffUL << GPIO_PORT_W90_PWORD_Pos) /*!< GPIO_PORT W90: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W91 ----------------------------------------- -#define GPIO_PORT_W91_PWORD_Pos 0 /*!< GPIO_PORT W91: PWORD Position */ -#define GPIO_PORT_W91_PWORD_Msk (0xffffffffUL << GPIO_PORT_W91_PWORD_Pos) /*!< GPIO_PORT W91: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W92 ----------------------------------------- -#define GPIO_PORT_W92_PWORD_Pos 0 /*!< GPIO_PORT W92: PWORD Position */ -#define GPIO_PORT_W92_PWORD_Msk (0xffffffffUL << GPIO_PORT_W92_PWORD_Pos) /*!< GPIO_PORT W92: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W93 ----------------------------------------- -#define GPIO_PORT_W93_PWORD_Pos 0 /*!< GPIO_PORT W93: PWORD Position */ -#define GPIO_PORT_W93_PWORD_Msk (0xffffffffUL << GPIO_PORT_W93_PWORD_Pos) /*!< GPIO_PORT W93: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W94 ----------------------------------------- -#define GPIO_PORT_W94_PWORD_Pos 0 /*!< GPIO_PORT W94: PWORD Position */ -#define GPIO_PORT_W94_PWORD_Msk (0xffffffffUL << GPIO_PORT_W94_PWORD_Pos) /*!< GPIO_PORT W94: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W95 ----------------------------------------- -#define GPIO_PORT_W95_PWORD_Pos 0 /*!< GPIO_PORT W95: PWORD Position */ -#define GPIO_PORT_W95_PWORD_Msk (0xffffffffUL << GPIO_PORT_W95_PWORD_Pos) /*!< GPIO_PORT W95: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W96 ----------------------------------------- -#define GPIO_PORT_W96_PWORD_Pos 0 /*!< GPIO_PORT W96: PWORD Position */ -#define GPIO_PORT_W96_PWORD_Msk (0xffffffffUL << GPIO_PORT_W96_PWORD_Pos) /*!< GPIO_PORT W96: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W97 ----------------------------------------- -#define GPIO_PORT_W97_PWORD_Pos 0 /*!< GPIO_PORT W97: PWORD Position */ -#define GPIO_PORT_W97_PWORD_Msk (0xffffffffUL << GPIO_PORT_W97_PWORD_Pos) /*!< GPIO_PORT W97: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W98 ----------------------------------------- -#define GPIO_PORT_W98_PWORD_Pos 0 /*!< GPIO_PORT W98: PWORD Position */ -#define GPIO_PORT_W98_PWORD_Msk (0xffffffffUL << GPIO_PORT_W98_PWORD_Pos) /*!< GPIO_PORT W98: PWORD Mask */ - -// -------------------------------------- GPIO_PORT_W99 ----------------------------------------- -#define GPIO_PORT_W99_PWORD_Pos 0 /*!< GPIO_PORT W99: PWORD Position */ -#define GPIO_PORT_W99_PWORD_Msk (0xffffffffUL << GPIO_PORT_W99_PWORD_Pos) /*!< GPIO_PORT W99: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W100 ----------------------------------------- -#define GPIO_PORT_W100_PWORD_Pos 0 /*!< GPIO_PORT W100: PWORD Position */ -#define GPIO_PORT_W100_PWORD_Msk (0xffffffffUL << GPIO_PORT_W100_PWORD_Pos) /*!< GPIO_PORT W100: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W101 ----------------------------------------- -#define GPIO_PORT_W101_PWORD_Pos 0 /*!< GPIO_PORT W101: PWORD Position */ -#define GPIO_PORT_W101_PWORD_Msk (0xffffffffUL << GPIO_PORT_W101_PWORD_Pos) /*!< GPIO_PORT W101: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W102 ----------------------------------------- -#define GPIO_PORT_W102_PWORD_Pos 0 /*!< GPIO_PORT W102: PWORD Position */ -#define GPIO_PORT_W102_PWORD_Msk (0xffffffffUL << GPIO_PORT_W102_PWORD_Pos) /*!< GPIO_PORT W102: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W103 ----------------------------------------- -#define GPIO_PORT_W103_PWORD_Pos 0 /*!< GPIO_PORT W103: PWORD Position */ -#define GPIO_PORT_W103_PWORD_Msk (0xffffffffUL << GPIO_PORT_W103_PWORD_Pos) /*!< GPIO_PORT W103: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W104 ----------------------------------------- -#define GPIO_PORT_W104_PWORD_Pos 0 /*!< GPIO_PORT W104: PWORD Position */ -#define GPIO_PORT_W104_PWORD_Msk (0xffffffffUL << GPIO_PORT_W104_PWORD_Pos) /*!< GPIO_PORT W104: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W105 ----------------------------------------- -#define GPIO_PORT_W105_PWORD_Pos 0 /*!< GPIO_PORT W105: PWORD Position */ -#define GPIO_PORT_W105_PWORD_Msk (0xffffffffUL << GPIO_PORT_W105_PWORD_Pos) /*!< GPIO_PORT W105: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W106 ----------------------------------------- -#define GPIO_PORT_W106_PWORD_Pos 0 /*!< GPIO_PORT W106: PWORD Position */ -#define GPIO_PORT_W106_PWORD_Msk (0xffffffffUL << GPIO_PORT_W106_PWORD_Pos) /*!< GPIO_PORT W106: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W107 ----------------------------------------- -#define GPIO_PORT_W107_PWORD_Pos 0 /*!< GPIO_PORT W107: PWORD Position */ -#define GPIO_PORT_W107_PWORD_Msk (0xffffffffUL << GPIO_PORT_W107_PWORD_Pos) /*!< GPIO_PORT W107: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W108 ----------------------------------------- -#define GPIO_PORT_W108_PWORD_Pos 0 /*!< GPIO_PORT W108: PWORD Position */ -#define GPIO_PORT_W108_PWORD_Msk (0xffffffffUL << GPIO_PORT_W108_PWORD_Pos) /*!< GPIO_PORT W108: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W109 ----------------------------------------- -#define GPIO_PORT_W109_PWORD_Pos 0 /*!< GPIO_PORT W109: PWORD Position */ -#define GPIO_PORT_W109_PWORD_Msk (0xffffffffUL << GPIO_PORT_W109_PWORD_Pos) /*!< GPIO_PORT W109: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W110 ----------------------------------------- -#define GPIO_PORT_W110_PWORD_Pos 0 /*!< GPIO_PORT W110: PWORD Position */ -#define GPIO_PORT_W110_PWORD_Msk (0xffffffffUL << GPIO_PORT_W110_PWORD_Pos) /*!< GPIO_PORT W110: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W111 ----------------------------------------- -#define GPIO_PORT_W111_PWORD_Pos 0 /*!< GPIO_PORT W111: PWORD Position */ -#define GPIO_PORT_W111_PWORD_Msk (0xffffffffUL << GPIO_PORT_W111_PWORD_Pos) /*!< GPIO_PORT W111: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W112 ----------------------------------------- -#define GPIO_PORT_W112_PWORD_Pos 0 /*!< GPIO_PORT W112: PWORD Position */ -#define GPIO_PORT_W112_PWORD_Msk (0xffffffffUL << GPIO_PORT_W112_PWORD_Pos) /*!< GPIO_PORT W112: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W113 ----------------------------------------- -#define GPIO_PORT_W113_PWORD_Pos 0 /*!< GPIO_PORT W113: PWORD Position */ -#define GPIO_PORT_W113_PWORD_Msk (0xffffffffUL << GPIO_PORT_W113_PWORD_Pos) /*!< GPIO_PORT W113: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W114 ----------------------------------------- -#define GPIO_PORT_W114_PWORD_Pos 0 /*!< GPIO_PORT W114: PWORD Position */ -#define GPIO_PORT_W114_PWORD_Msk (0xffffffffUL << GPIO_PORT_W114_PWORD_Pos) /*!< GPIO_PORT W114: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W115 ----------------------------------------- -#define GPIO_PORT_W115_PWORD_Pos 0 /*!< GPIO_PORT W115: PWORD Position */ -#define GPIO_PORT_W115_PWORD_Msk (0xffffffffUL << GPIO_PORT_W115_PWORD_Pos) /*!< GPIO_PORT W115: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W116 ----------------------------------------- -#define GPIO_PORT_W116_PWORD_Pos 0 /*!< GPIO_PORT W116: PWORD Position */ -#define GPIO_PORT_W116_PWORD_Msk (0xffffffffUL << GPIO_PORT_W116_PWORD_Pos) /*!< GPIO_PORT W116: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W117 ----------------------------------------- -#define GPIO_PORT_W117_PWORD_Pos 0 /*!< GPIO_PORT W117: PWORD Position */ -#define GPIO_PORT_W117_PWORD_Msk (0xffffffffUL << GPIO_PORT_W117_PWORD_Pos) /*!< GPIO_PORT W117: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W118 ----------------------------------------- -#define GPIO_PORT_W118_PWORD_Pos 0 /*!< GPIO_PORT W118: PWORD Position */ -#define GPIO_PORT_W118_PWORD_Msk (0xffffffffUL << GPIO_PORT_W118_PWORD_Pos) /*!< GPIO_PORT W118: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W119 ----------------------------------------- -#define GPIO_PORT_W119_PWORD_Pos 0 /*!< GPIO_PORT W119: PWORD Position */ -#define GPIO_PORT_W119_PWORD_Msk (0xffffffffUL << GPIO_PORT_W119_PWORD_Pos) /*!< GPIO_PORT W119: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W120 ----------------------------------------- -#define GPIO_PORT_W120_PWORD_Pos 0 /*!< GPIO_PORT W120: PWORD Position */ -#define GPIO_PORT_W120_PWORD_Msk (0xffffffffUL << GPIO_PORT_W120_PWORD_Pos) /*!< GPIO_PORT W120: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W121 ----------------------------------------- -#define GPIO_PORT_W121_PWORD_Pos 0 /*!< GPIO_PORT W121: PWORD Position */ -#define GPIO_PORT_W121_PWORD_Msk (0xffffffffUL << GPIO_PORT_W121_PWORD_Pos) /*!< GPIO_PORT W121: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W122 ----------------------------------------- -#define GPIO_PORT_W122_PWORD_Pos 0 /*!< GPIO_PORT W122: PWORD Position */ -#define GPIO_PORT_W122_PWORD_Msk (0xffffffffUL << GPIO_PORT_W122_PWORD_Pos) /*!< GPIO_PORT W122: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W123 ----------------------------------------- -#define GPIO_PORT_W123_PWORD_Pos 0 /*!< GPIO_PORT W123: PWORD Position */ -#define GPIO_PORT_W123_PWORD_Msk (0xffffffffUL << GPIO_PORT_W123_PWORD_Pos) /*!< GPIO_PORT W123: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W124 ----------------------------------------- -#define GPIO_PORT_W124_PWORD_Pos 0 /*!< GPIO_PORT W124: PWORD Position */ -#define GPIO_PORT_W124_PWORD_Msk (0xffffffffUL << GPIO_PORT_W124_PWORD_Pos) /*!< GPIO_PORT W124: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W125 ----------------------------------------- -#define GPIO_PORT_W125_PWORD_Pos 0 /*!< GPIO_PORT W125: PWORD Position */ -#define GPIO_PORT_W125_PWORD_Msk (0xffffffffUL << GPIO_PORT_W125_PWORD_Pos) /*!< GPIO_PORT W125: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W126 ----------------------------------------- -#define GPIO_PORT_W126_PWORD_Pos 0 /*!< GPIO_PORT W126: PWORD Position */ -#define GPIO_PORT_W126_PWORD_Msk (0xffffffffUL << GPIO_PORT_W126_PWORD_Pos) /*!< GPIO_PORT W126: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W127 ----------------------------------------- -#define GPIO_PORT_W127_PWORD_Pos 0 /*!< GPIO_PORT W127: PWORD Position */ -#define GPIO_PORT_W127_PWORD_Msk (0xffffffffUL << GPIO_PORT_W127_PWORD_Pos) /*!< GPIO_PORT W127: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W128 ----------------------------------------- -#define GPIO_PORT_W128_PWORD_Pos 0 /*!< GPIO_PORT W128: PWORD Position */ -#define GPIO_PORT_W128_PWORD_Msk (0xffffffffUL << GPIO_PORT_W128_PWORD_Pos) /*!< GPIO_PORT W128: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W129 ----------------------------------------- -#define GPIO_PORT_W129_PWORD_Pos 0 /*!< GPIO_PORT W129: PWORD Position */ -#define GPIO_PORT_W129_PWORD_Msk (0xffffffffUL << GPIO_PORT_W129_PWORD_Pos) /*!< GPIO_PORT W129: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W130 ----------------------------------------- -#define GPIO_PORT_W130_PWORD_Pos 0 /*!< GPIO_PORT W130: PWORD Position */ -#define GPIO_PORT_W130_PWORD_Msk (0xffffffffUL << GPIO_PORT_W130_PWORD_Pos) /*!< GPIO_PORT W130: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W131 ----------------------------------------- -#define GPIO_PORT_W131_PWORD_Pos 0 /*!< GPIO_PORT W131: PWORD Position */ -#define GPIO_PORT_W131_PWORD_Msk (0xffffffffUL << GPIO_PORT_W131_PWORD_Pos) /*!< GPIO_PORT W131: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W132 ----------------------------------------- -#define GPIO_PORT_W132_PWORD_Pos 0 /*!< GPIO_PORT W132: PWORD Position */ -#define GPIO_PORT_W132_PWORD_Msk (0xffffffffUL << GPIO_PORT_W132_PWORD_Pos) /*!< GPIO_PORT W132: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W133 ----------------------------------------- -#define GPIO_PORT_W133_PWORD_Pos 0 /*!< GPIO_PORT W133: PWORD Position */ -#define GPIO_PORT_W133_PWORD_Msk (0xffffffffUL << GPIO_PORT_W133_PWORD_Pos) /*!< GPIO_PORT W133: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W134 ----------------------------------------- -#define GPIO_PORT_W134_PWORD_Pos 0 /*!< GPIO_PORT W134: PWORD Position */ -#define GPIO_PORT_W134_PWORD_Msk (0xffffffffUL << GPIO_PORT_W134_PWORD_Pos) /*!< GPIO_PORT W134: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W135 ----------------------------------------- -#define GPIO_PORT_W135_PWORD_Pos 0 /*!< GPIO_PORT W135: PWORD Position */ -#define GPIO_PORT_W135_PWORD_Msk (0xffffffffUL << GPIO_PORT_W135_PWORD_Pos) /*!< GPIO_PORT W135: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W136 ----------------------------------------- -#define GPIO_PORT_W136_PWORD_Pos 0 /*!< GPIO_PORT W136: PWORD Position */ -#define GPIO_PORT_W136_PWORD_Msk (0xffffffffUL << GPIO_PORT_W136_PWORD_Pos) /*!< GPIO_PORT W136: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W137 ----------------------------------------- -#define GPIO_PORT_W137_PWORD_Pos 0 /*!< GPIO_PORT W137: PWORD Position */ -#define GPIO_PORT_W137_PWORD_Msk (0xffffffffUL << GPIO_PORT_W137_PWORD_Pos) /*!< GPIO_PORT W137: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W138 ----------------------------------------- -#define GPIO_PORT_W138_PWORD_Pos 0 /*!< GPIO_PORT W138: PWORD Position */ -#define GPIO_PORT_W138_PWORD_Msk (0xffffffffUL << GPIO_PORT_W138_PWORD_Pos) /*!< GPIO_PORT W138: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W139 ----------------------------------------- -#define GPIO_PORT_W139_PWORD_Pos 0 /*!< GPIO_PORT W139: PWORD Position */ -#define GPIO_PORT_W139_PWORD_Msk (0xffffffffUL << GPIO_PORT_W139_PWORD_Pos) /*!< GPIO_PORT W139: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W140 ----------------------------------------- -#define GPIO_PORT_W140_PWORD_Pos 0 /*!< GPIO_PORT W140: PWORD Position */ -#define GPIO_PORT_W140_PWORD_Msk (0xffffffffUL << GPIO_PORT_W140_PWORD_Pos) /*!< GPIO_PORT W140: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W141 ----------------------------------------- -#define GPIO_PORT_W141_PWORD_Pos 0 /*!< GPIO_PORT W141: PWORD Position */ -#define GPIO_PORT_W141_PWORD_Msk (0xffffffffUL << GPIO_PORT_W141_PWORD_Pos) /*!< GPIO_PORT W141: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W142 ----------------------------------------- -#define GPIO_PORT_W142_PWORD_Pos 0 /*!< GPIO_PORT W142: PWORD Position */ -#define GPIO_PORT_W142_PWORD_Msk (0xffffffffUL << GPIO_PORT_W142_PWORD_Pos) /*!< GPIO_PORT W142: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W143 ----------------------------------------- -#define GPIO_PORT_W143_PWORD_Pos 0 /*!< GPIO_PORT W143: PWORD Position */ -#define GPIO_PORT_W143_PWORD_Msk (0xffffffffUL << GPIO_PORT_W143_PWORD_Pos) /*!< GPIO_PORT W143: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W144 ----------------------------------------- -#define GPIO_PORT_W144_PWORD_Pos 0 /*!< GPIO_PORT W144: PWORD Position */ -#define GPIO_PORT_W144_PWORD_Msk (0xffffffffUL << GPIO_PORT_W144_PWORD_Pos) /*!< GPIO_PORT W144: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W145 ----------------------------------------- -#define GPIO_PORT_W145_PWORD_Pos 0 /*!< GPIO_PORT W145: PWORD Position */ -#define GPIO_PORT_W145_PWORD_Msk (0xffffffffUL << GPIO_PORT_W145_PWORD_Pos) /*!< GPIO_PORT W145: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W146 ----------------------------------------- -#define GPIO_PORT_W146_PWORD_Pos 0 /*!< GPIO_PORT W146: PWORD Position */ -#define GPIO_PORT_W146_PWORD_Msk (0xffffffffUL << GPIO_PORT_W146_PWORD_Pos) /*!< GPIO_PORT W146: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W147 ----------------------------------------- -#define GPIO_PORT_W147_PWORD_Pos 0 /*!< GPIO_PORT W147: PWORD Position */ -#define GPIO_PORT_W147_PWORD_Msk (0xffffffffUL << GPIO_PORT_W147_PWORD_Pos) /*!< GPIO_PORT W147: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W148 ----------------------------------------- -#define GPIO_PORT_W148_PWORD_Pos 0 /*!< GPIO_PORT W148: PWORD Position */ -#define GPIO_PORT_W148_PWORD_Msk (0xffffffffUL << GPIO_PORT_W148_PWORD_Pos) /*!< GPIO_PORT W148: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W149 ----------------------------------------- -#define GPIO_PORT_W149_PWORD_Pos 0 /*!< GPIO_PORT W149: PWORD Position */ -#define GPIO_PORT_W149_PWORD_Msk (0xffffffffUL << GPIO_PORT_W149_PWORD_Pos) /*!< GPIO_PORT W149: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W150 ----------------------------------------- -#define GPIO_PORT_W150_PWORD_Pos 0 /*!< GPIO_PORT W150: PWORD Position */ -#define GPIO_PORT_W150_PWORD_Msk (0xffffffffUL << GPIO_PORT_W150_PWORD_Pos) /*!< GPIO_PORT W150: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W151 ----------------------------------------- -#define GPIO_PORT_W151_PWORD_Pos 0 /*!< GPIO_PORT W151: PWORD Position */ -#define GPIO_PORT_W151_PWORD_Msk (0xffffffffUL << GPIO_PORT_W151_PWORD_Pos) /*!< GPIO_PORT W151: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W152 ----------------------------------------- -#define GPIO_PORT_W152_PWORD_Pos 0 /*!< GPIO_PORT W152: PWORD Position */ -#define GPIO_PORT_W152_PWORD_Msk (0xffffffffUL << GPIO_PORT_W152_PWORD_Pos) /*!< GPIO_PORT W152: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W153 ----------------------------------------- -#define GPIO_PORT_W153_PWORD_Pos 0 /*!< GPIO_PORT W153: PWORD Position */ -#define GPIO_PORT_W153_PWORD_Msk (0xffffffffUL << GPIO_PORT_W153_PWORD_Pos) /*!< GPIO_PORT W153: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W154 ----------------------------------------- -#define GPIO_PORT_W154_PWORD_Pos 0 /*!< GPIO_PORT W154: PWORD Position */ -#define GPIO_PORT_W154_PWORD_Msk (0xffffffffUL << GPIO_PORT_W154_PWORD_Pos) /*!< GPIO_PORT W154: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W155 ----------------------------------------- -#define GPIO_PORT_W155_PWORD_Pos 0 /*!< GPIO_PORT W155: PWORD Position */ -#define GPIO_PORT_W155_PWORD_Msk (0xffffffffUL << GPIO_PORT_W155_PWORD_Pos) /*!< GPIO_PORT W155: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W156 ----------------------------------------- -#define GPIO_PORT_W156_PWORD_Pos 0 /*!< GPIO_PORT W156: PWORD Position */ -#define GPIO_PORT_W156_PWORD_Msk (0xffffffffUL << GPIO_PORT_W156_PWORD_Pos) /*!< GPIO_PORT W156: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W157 ----------------------------------------- -#define GPIO_PORT_W157_PWORD_Pos 0 /*!< GPIO_PORT W157: PWORD Position */ -#define GPIO_PORT_W157_PWORD_Msk (0xffffffffUL << GPIO_PORT_W157_PWORD_Pos) /*!< GPIO_PORT W157: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W158 ----------------------------------------- -#define GPIO_PORT_W158_PWORD_Pos 0 /*!< GPIO_PORT W158: PWORD Position */ -#define GPIO_PORT_W158_PWORD_Msk (0xffffffffUL << GPIO_PORT_W158_PWORD_Pos) /*!< GPIO_PORT W158: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W159 ----------------------------------------- -#define GPIO_PORT_W159_PWORD_Pos 0 /*!< GPIO_PORT W159: PWORD Position */ -#define GPIO_PORT_W159_PWORD_Msk (0xffffffffUL << GPIO_PORT_W159_PWORD_Pos) /*!< GPIO_PORT W159: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W160 ----------------------------------------- -#define GPIO_PORT_W160_PWORD_Pos 0 /*!< GPIO_PORT W160: PWORD Position */ -#define GPIO_PORT_W160_PWORD_Msk (0xffffffffUL << GPIO_PORT_W160_PWORD_Pos) /*!< GPIO_PORT W160: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W161 ----------------------------------------- -#define GPIO_PORT_W161_PWORD_Pos 0 /*!< GPIO_PORT W161: PWORD Position */ -#define GPIO_PORT_W161_PWORD_Msk (0xffffffffUL << GPIO_PORT_W161_PWORD_Pos) /*!< GPIO_PORT W161: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W162 ----------------------------------------- -#define GPIO_PORT_W162_PWORD_Pos 0 /*!< GPIO_PORT W162: PWORD Position */ -#define GPIO_PORT_W162_PWORD_Msk (0xffffffffUL << GPIO_PORT_W162_PWORD_Pos) /*!< GPIO_PORT W162: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W163 ----------------------------------------- -#define GPIO_PORT_W163_PWORD_Pos 0 /*!< GPIO_PORT W163: PWORD Position */ -#define GPIO_PORT_W163_PWORD_Msk (0xffffffffUL << GPIO_PORT_W163_PWORD_Pos) /*!< GPIO_PORT W163: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W164 ----------------------------------------- -#define GPIO_PORT_W164_PWORD_Pos 0 /*!< GPIO_PORT W164: PWORD Position */ -#define GPIO_PORT_W164_PWORD_Msk (0xffffffffUL << GPIO_PORT_W164_PWORD_Pos) /*!< GPIO_PORT W164: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W165 ----------------------------------------- -#define GPIO_PORT_W165_PWORD_Pos 0 /*!< GPIO_PORT W165: PWORD Position */ -#define GPIO_PORT_W165_PWORD_Msk (0xffffffffUL << GPIO_PORT_W165_PWORD_Pos) /*!< GPIO_PORT W165: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W166 ----------------------------------------- -#define GPIO_PORT_W166_PWORD_Pos 0 /*!< GPIO_PORT W166: PWORD Position */ -#define GPIO_PORT_W166_PWORD_Msk (0xffffffffUL << GPIO_PORT_W166_PWORD_Pos) /*!< GPIO_PORT W166: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W167 ----------------------------------------- -#define GPIO_PORT_W167_PWORD_Pos 0 /*!< GPIO_PORT W167: PWORD Position */ -#define GPIO_PORT_W167_PWORD_Msk (0xffffffffUL << GPIO_PORT_W167_PWORD_Pos) /*!< GPIO_PORT W167: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W168 ----------------------------------------- -#define GPIO_PORT_W168_PWORD_Pos 0 /*!< GPIO_PORT W168: PWORD Position */ -#define GPIO_PORT_W168_PWORD_Msk (0xffffffffUL << GPIO_PORT_W168_PWORD_Pos) /*!< GPIO_PORT W168: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W169 ----------------------------------------- -#define GPIO_PORT_W169_PWORD_Pos 0 /*!< GPIO_PORT W169: PWORD Position */ -#define GPIO_PORT_W169_PWORD_Msk (0xffffffffUL << GPIO_PORT_W169_PWORD_Pos) /*!< GPIO_PORT W169: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W170 ----------------------------------------- -#define GPIO_PORT_W170_PWORD_Pos 0 /*!< GPIO_PORT W170: PWORD Position */ -#define GPIO_PORT_W170_PWORD_Msk (0xffffffffUL << GPIO_PORT_W170_PWORD_Pos) /*!< GPIO_PORT W170: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W171 ----------------------------------------- -#define GPIO_PORT_W171_PWORD_Pos 0 /*!< GPIO_PORT W171: PWORD Position */ -#define GPIO_PORT_W171_PWORD_Msk (0xffffffffUL << GPIO_PORT_W171_PWORD_Pos) /*!< GPIO_PORT W171: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W172 ----------------------------------------- -#define GPIO_PORT_W172_PWORD_Pos 0 /*!< GPIO_PORT W172: PWORD Position */ -#define GPIO_PORT_W172_PWORD_Msk (0xffffffffUL << GPIO_PORT_W172_PWORD_Pos) /*!< GPIO_PORT W172: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W173 ----------------------------------------- -#define GPIO_PORT_W173_PWORD_Pos 0 /*!< GPIO_PORT W173: PWORD Position */ -#define GPIO_PORT_W173_PWORD_Msk (0xffffffffUL << GPIO_PORT_W173_PWORD_Pos) /*!< GPIO_PORT W173: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W174 ----------------------------------------- -#define GPIO_PORT_W174_PWORD_Pos 0 /*!< GPIO_PORT W174: PWORD Position */ -#define GPIO_PORT_W174_PWORD_Msk (0xffffffffUL << GPIO_PORT_W174_PWORD_Pos) /*!< GPIO_PORT W174: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W175 ----------------------------------------- -#define GPIO_PORT_W175_PWORD_Pos 0 /*!< GPIO_PORT W175: PWORD Position */ -#define GPIO_PORT_W175_PWORD_Msk (0xffffffffUL << GPIO_PORT_W175_PWORD_Pos) /*!< GPIO_PORT W175: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W176 ----------------------------------------- -#define GPIO_PORT_W176_PWORD_Pos 0 /*!< GPIO_PORT W176: PWORD Position */ -#define GPIO_PORT_W176_PWORD_Msk (0xffffffffUL << GPIO_PORT_W176_PWORD_Pos) /*!< GPIO_PORT W176: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W177 ----------------------------------------- -#define GPIO_PORT_W177_PWORD_Pos 0 /*!< GPIO_PORT W177: PWORD Position */ -#define GPIO_PORT_W177_PWORD_Msk (0xffffffffUL << GPIO_PORT_W177_PWORD_Pos) /*!< GPIO_PORT W177: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W178 ----------------------------------------- -#define GPIO_PORT_W178_PWORD_Pos 0 /*!< GPIO_PORT W178: PWORD Position */ -#define GPIO_PORT_W178_PWORD_Msk (0xffffffffUL << GPIO_PORT_W178_PWORD_Pos) /*!< GPIO_PORT W178: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W179 ----------------------------------------- -#define GPIO_PORT_W179_PWORD_Pos 0 /*!< GPIO_PORT W179: PWORD Position */ -#define GPIO_PORT_W179_PWORD_Msk (0xffffffffUL << GPIO_PORT_W179_PWORD_Pos) /*!< GPIO_PORT W179: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W180 ----------------------------------------- -#define GPIO_PORT_W180_PWORD_Pos 0 /*!< GPIO_PORT W180: PWORD Position */ -#define GPIO_PORT_W180_PWORD_Msk (0xffffffffUL << GPIO_PORT_W180_PWORD_Pos) /*!< GPIO_PORT W180: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W181 ----------------------------------------- -#define GPIO_PORT_W181_PWORD_Pos 0 /*!< GPIO_PORT W181: PWORD Position */ -#define GPIO_PORT_W181_PWORD_Msk (0xffffffffUL << GPIO_PORT_W181_PWORD_Pos) /*!< GPIO_PORT W181: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W182 ----------------------------------------- -#define GPIO_PORT_W182_PWORD_Pos 0 /*!< GPIO_PORT W182: PWORD Position */ -#define GPIO_PORT_W182_PWORD_Msk (0xffffffffUL << GPIO_PORT_W182_PWORD_Pos) /*!< GPIO_PORT W182: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W183 ----------------------------------------- -#define GPIO_PORT_W183_PWORD_Pos 0 /*!< GPIO_PORT W183: PWORD Position */ -#define GPIO_PORT_W183_PWORD_Msk (0xffffffffUL << GPIO_PORT_W183_PWORD_Pos) /*!< GPIO_PORT W183: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W184 ----------------------------------------- -#define GPIO_PORT_W184_PWORD_Pos 0 /*!< GPIO_PORT W184: PWORD Position */ -#define GPIO_PORT_W184_PWORD_Msk (0xffffffffUL << GPIO_PORT_W184_PWORD_Pos) /*!< GPIO_PORT W184: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W185 ----------------------------------------- -#define GPIO_PORT_W185_PWORD_Pos 0 /*!< GPIO_PORT W185: PWORD Position */ -#define GPIO_PORT_W185_PWORD_Msk (0xffffffffUL << GPIO_PORT_W185_PWORD_Pos) /*!< GPIO_PORT W185: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W186 ----------------------------------------- -#define GPIO_PORT_W186_PWORD_Pos 0 /*!< GPIO_PORT W186: PWORD Position */ -#define GPIO_PORT_W186_PWORD_Msk (0xffffffffUL << GPIO_PORT_W186_PWORD_Pos) /*!< GPIO_PORT W186: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W187 ----------------------------------------- -#define GPIO_PORT_W187_PWORD_Pos 0 /*!< GPIO_PORT W187: PWORD Position */ -#define GPIO_PORT_W187_PWORD_Msk (0xffffffffUL << GPIO_PORT_W187_PWORD_Pos) /*!< GPIO_PORT W187: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W188 ----------------------------------------- -#define GPIO_PORT_W188_PWORD_Pos 0 /*!< GPIO_PORT W188: PWORD Position */ -#define GPIO_PORT_W188_PWORD_Msk (0xffffffffUL << GPIO_PORT_W188_PWORD_Pos) /*!< GPIO_PORT W188: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W189 ----------------------------------------- -#define GPIO_PORT_W189_PWORD_Pos 0 /*!< GPIO_PORT W189: PWORD Position */ -#define GPIO_PORT_W189_PWORD_Msk (0xffffffffUL << GPIO_PORT_W189_PWORD_Pos) /*!< GPIO_PORT W189: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W190 ----------------------------------------- -#define GPIO_PORT_W190_PWORD_Pos 0 /*!< GPIO_PORT W190: PWORD Position */ -#define GPIO_PORT_W190_PWORD_Msk (0xffffffffUL << GPIO_PORT_W190_PWORD_Pos) /*!< GPIO_PORT W190: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W191 ----------------------------------------- -#define GPIO_PORT_W191_PWORD_Pos 0 /*!< GPIO_PORT W191: PWORD Position */ -#define GPIO_PORT_W191_PWORD_Msk (0xffffffffUL << GPIO_PORT_W191_PWORD_Pos) /*!< GPIO_PORT W191: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W192 ----------------------------------------- -#define GPIO_PORT_W192_PWORD_Pos 0 /*!< GPIO_PORT W192: PWORD Position */ -#define GPIO_PORT_W192_PWORD_Msk (0xffffffffUL << GPIO_PORT_W192_PWORD_Pos) /*!< GPIO_PORT W192: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W193 ----------------------------------------- -#define GPIO_PORT_W193_PWORD_Pos 0 /*!< GPIO_PORT W193: PWORD Position */ -#define GPIO_PORT_W193_PWORD_Msk (0xffffffffUL << GPIO_PORT_W193_PWORD_Pos) /*!< GPIO_PORT W193: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W194 ----------------------------------------- -#define GPIO_PORT_W194_PWORD_Pos 0 /*!< GPIO_PORT W194: PWORD Position */ -#define GPIO_PORT_W194_PWORD_Msk (0xffffffffUL << GPIO_PORT_W194_PWORD_Pos) /*!< GPIO_PORT W194: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W195 ----------------------------------------- -#define GPIO_PORT_W195_PWORD_Pos 0 /*!< GPIO_PORT W195: PWORD Position */ -#define GPIO_PORT_W195_PWORD_Msk (0xffffffffUL << GPIO_PORT_W195_PWORD_Pos) /*!< GPIO_PORT W195: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W196 ----------------------------------------- -#define GPIO_PORT_W196_PWORD_Pos 0 /*!< GPIO_PORT W196: PWORD Position */ -#define GPIO_PORT_W196_PWORD_Msk (0xffffffffUL << GPIO_PORT_W196_PWORD_Pos) /*!< GPIO_PORT W196: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W197 ----------------------------------------- -#define GPIO_PORT_W197_PWORD_Pos 0 /*!< GPIO_PORT W197: PWORD Position */ -#define GPIO_PORT_W197_PWORD_Msk (0xffffffffUL << GPIO_PORT_W197_PWORD_Pos) /*!< GPIO_PORT W197: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W198 ----------------------------------------- -#define GPIO_PORT_W198_PWORD_Pos 0 /*!< GPIO_PORT W198: PWORD Position */ -#define GPIO_PORT_W198_PWORD_Msk (0xffffffffUL << GPIO_PORT_W198_PWORD_Pos) /*!< GPIO_PORT W198: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W199 ----------------------------------------- -#define GPIO_PORT_W199_PWORD_Pos 0 /*!< GPIO_PORT W199: PWORD Position */ -#define GPIO_PORT_W199_PWORD_Msk (0xffffffffUL << GPIO_PORT_W199_PWORD_Pos) /*!< GPIO_PORT W199: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W200 ----------------------------------------- -#define GPIO_PORT_W200_PWORD_Pos 0 /*!< GPIO_PORT W200: PWORD Position */ -#define GPIO_PORT_W200_PWORD_Msk (0xffffffffUL << GPIO_PORT_W200_PWORD_Pos) /*!< GPIO_PORT W200: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W201 ----------------------------------------- -#define GPIO_PORT_W201_PWORD_Pos 0 /*!< GPIO_PORT W201: PWORD Position */ -#define GPIO_PORT_W201_PWORD_Msk (0xffffffffUL << GPIO_PORT_W201_PWORD_Pos) /*!< GPIO_PORT W201: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W202 ----------------------------------------- -#define GPIO_PORT_W202_PWORD_Pos 0 /*!< GPIO_PORT W202: PWORD Position */ -#define GPIO_PORT_W202_PWORD_Msk (0xffffffffUL << GPIO_PORT_W202_PWORD_Pos) /*!< GPIO_PORT W202: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W203 ----------------------------------------- -#define GPIO_PORT_W203_PWORD_Pos 0 /*!< GPIO_PORT W203: PWORD Position */ -#define GPIO_PORT_W203_PWORD_Msk (0xffffffffUL << GPIO_PORT_W203_PWORD_Pos) /*!< GPIO_PORT W203: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W204 ----------------------------------------- -#define GPIO_PORT_W204_PWORD_Pos 0 /*!< GPIO_PORT W204: PWORD Position */ -#define GPIO_PORT_W204_PWORD_Msk (0xffffffffUL << GPIO_PORT_W204_PWORD_Pos) /*!< GPIO_PORT W204: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W205 ----------------------------------------- -#define GPIO_PORT_W205_PWORD_Pos 0 /*!< GPIO_PORT W205: PWORD Position */ -#define GPIO_PORT_W205_PWORD_Msk (0xffffffffUL << GPIO_PORT_W205_PWORD_Pos) /*!< GPIO_PORT W205: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W206 ----------------------------------------- -#define GPIO_PORT_W206_PWORD_Pos 0 /*!< GPIO_PORT W206: PWORD Position */ -#define GPIO_PORT_W206_PWORD_Msk (0xffffffffUL << GPIO_PORT_W206_PWORD_Pos) /*!< GPIO_PORT W206: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W207 ----------------------------------------- -#define GPIO_PORT_W207_PWORD_Pos 0 /*!< GPIO_PORT W207: PWORD Position */ -#define GPIO_PORT_W207_PWORD_Msk (0xffffffffUL << GPIO_PORT_W207_PWORD_Pos) /*!< GPIO_PORT W207: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W208 ----------------------------------------- -#define GPIO_PORT_W208_PWORD_Pos 0 /*!< GPIO_PORT W208: PWORD Position */ -#define GPIO_PORT_W208_PWORD_Msk (0xffffffffUL << GPIO_PORT_W208_PWORD_Pos) /*!< GPIO_PORT W208: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W209 ----------------------------------------- -#define GPIO_PORT_W209_PWORD_Pos 0 /*!< GPIO_PORT W209: PWORD Position */ -#define GPIO_PORT_W209_PWORD_Msk (0xffffffffUL << GPIO_PORT_W209_PWORD_Pos) /*!< GPIO_PORT W209: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W210 ----------------------------------------- -#define GPIO_PORT_W210_PWORD_Pos 0 /*!< GPIO_PORT W210: PWORD Position */ -#define GPIO_PORT_W210_PWORD_Msk (0xffffffffUL << GPIO_PORT_W210_PWORD_Pos) /*!< GPIO_PORT W210: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W211 ----------------------------------------- -#define GPIO_PORT_W211_PWORD_Pos 0 /*!< GPIO_PORT W211: PWORD Position */ -#define GPIO_PORT_W211_PWORD_Msk (0xffffffffUL << GPIO_PORT_W211_PWORD_Pos) /*!< GPIO_PORT W211: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W212 ----------------------------------------- -#define GPIO_PORT_W212_PWORD_Pos 0 /*!< GPIO_PORT W212: PWORD Position */ -#define GPIO_PORT_W212_PWORD_Msk (0xffffffffUL << GPIO_PORT_W212_PWORD_Pos) /*!< GPIO_PORT W212: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W213 ----------------------------------------- -#define GPIO_PORT_W213_PWORD_Pos 0 /*!< GPIO_PORT W213: PWORD Position */ -#define GPIO_PORT_W213_PWORD_Msk (0xffffffffUL << GPIO_PORT_W213_PWORD_Pos) /*!< GPIO_PORT W213: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W214 ----------------------------------------- -#define GPIO_PORT_W214_PWORD_Pos 0 /*!< GPIO_PORT W214: PWORD Position */ -#define GPIO_PORT_W214_PWORD_Msk (0xffffffffUL << GPIO_PORT_W214_PWORD_Pos) /*!< GPIO_PORT W214: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W215 ----------------------------------------- -#define GPIO_PORT_W215_PWORD_Pos 0 /*!< GPIO_PORT W215: PWORD Position */ -#define GPIO_PORT_W215_PWORD_Msk (0xffffffffUL << GPIO_PORT_W215_PWORD_Pos) /*!< GPIO_PORT W215: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W216 ----------------------------------------- -#define GPIO_PORT_W216_PWORD_Pos 0 /*!< GPIO_PORT W216: PWORD Position */ -#define GPIO_PORT_W216_PWORD_Msk (0xffffffffUL << GPIO_PORT_W216_PWORD_Pos) /*!< GPIO_PORT W216: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W217 ----------------------------------------- -#define GPIO_PORT_W217_PWORD_Pos 0 /*!< GPIO_PORT W217: PWORD Position */ -#define GPIO_PORT_W217_PWORD_Msk (0xffffffffUL << GPIO_PORT_W217_PWORD_Pos) /*!< GPIO_PORT W217: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W218 ----------------------------------------- -#define GPIO_PORT_W218_PWORD_Pos 0 /*!< GPIO_PORT W218: PWORD Position */ -#define GPIO_PORT_W218_PWORD_Msk (0xffffffffUL << GPIO_PORT_W218_PWORD_Pos) /*!< GPIO_PORT W218: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W219 ----------------------------------------- -#define GPIO_PORT_W219_PWORD_Pos 0 /*!< GPIO_PORT W219: PWORD Position */ -#define GPIO_PORT_W219_PWORD_Msk (0xffffffffUL << GPIO_PORT_W219_PWORD_Pos) /*!< GPIO_PORT W219: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W220 ----------------------------------------- -#define GPIO_PORT_W220_PWORD_Pos 0 /*!< GPIO_PORT W220: PWORD Position */ -#define GPIO_PORT_W220_PWORD_Msk (0xffffffffUL << GPIO_PORT_W220_PWORD_Pos) /*!< GPIO_PORT W220: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W221 ----------------------------------------- -#define GPIO_PORT_W221_PWORD_Pos 0 /*!< GPIO_PORT W221: PWORD Position */ -#define GPIO_PORT_W221_PWORD_Msk (0xffffffffUL << GPIO_PORT_W221_PWORD_Pos) /*!< GPIO_PORT W221: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W222 ----------------------------------------- -#define GPIO_PORT_W222_PWORD_Pos 0 /*!< GPIO_PORT W222: PWORD Position */ -#define GPIO_PORT_W222_PWORD_Msk (0xffffffffUL << GPIO_PORT_W222_PWORD_Pos) /*!< GPIO_PORT W222: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W223 ----------------------------------------- -#define GPIO_PORT_W223_PWORD_Pos 0 /*!< GPIO_PORT W223: PWORD Position */ -#define GPIO_PORT_W223_PWORD_Msk (0xffffffffUL << GPIO_PORT_W223_PWORD_Pos) /*!< GPIO_PORT W223: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W224 ----------------------------------------- -#define GPIO_PORT_W224_PWORD_Pos 0 /*!< GPIO_PORT W224: PWORD Position */ -#define GPIO_PORT_W224_PWORD_Msk (0xffffffffUL << GPIO_PORT_W224_PWORD_Pos) /*!< GPIO_PORT W224: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W225 ----------------------------------------- -#define GPIO_PORT_W225_PWORD_Pos 0 /*!< GPIO_PORT W225: PWORD Position */ -#define GPIO_PORT_W225_PWORD_Msk (0xffffffffUL << GPIO_PORT_W225_PWORD_Pos) /*!< GPIO_PORT W225: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W226 ----------------------------------------- -#define GPIO_PORT_W226_PWORD_Pos 0 /*!< GPIO_PORT W226: PWORD Position */ -#define GPIO_PORT_W226_PWORD_Msk (0xffffffffUL << GPIO_PORT_W226_PWORD_Pos) /*!< GPIO_PORT W226: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W227 ----------------------------------------- -#define GPIO_PORT_W227_PWORD_Pos 0 /*!< GPIO_PORT W227: PWORD Position */ -#define GPIO_PORT_W227_PWORD_Msk (0xffffffffUL << GPIO_PORT_W227_PWORD_Pos) /*!< GPIO_PORT W227: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W228 ----------------------------------------- -#define GPIO_PORT_W228_PWORD_Pos 0 /*!< GPIO_PORT W228: PWORD Position */ -#define GPIO_PORT_W228_PWORD_Msk (0xffffffffUL << GPIO_PORT_W228_PWORD_Pos) /*!< GPIO_PORT W228: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W229 ----------------------------------------- -#define GPIO_PORT_W229_PWORD_Pos 0 /*!< GPIO_PORT W229: PWORD Position */ -#define GPIO_PORT_W229_PWORD_Msk (0xffffffffUL << GPIO_PORT_W229_PWORD_Pos) /*!< GPIO_PORT W229: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W230 ----------------------------------------- -#define GPIO_PORT_W230_PWORD_Pos 0 /*!< GPIO_PORT W230: PWORD Position */ -#define GPIO_PORT_W230_PWORD_Msk (0xffffffffUL << GPIO_PORT_W230_PWORD_Pos) /*!< GPIO_PORT W230: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W231 ----------------------------------------- -#define GPIO_PORT_W231_PWORD_Pos 0 /*!< GPIO_PORT W231: PWORD Position */ -#define GPIO_PORT_W231_PWORD_Msk (0xffffffffUL << GPIO_PORT_W231_PWORD_Pos) /*!< GPIO_PORT W231: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W232 ----------------------------------------- -#define GPIO_PORT_W232_PWORD_Pos 0 /*!< GPIO_PORT W232: PWORD Position */ -#define GPIO_PORT_W232_PWORD_Msk (0xffffffffUL << GPIO_PORT_W232_PWORD_Pos) /*!< GPIO_PORT W232: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W233 ----------------------------------------- -#define GPIO_PORT_W233_PWORD_Pos 0 /*!< GPIO_PORT W233: PWORD Position */ -#define GPIO_PORT_W233_PWORD_Msk (0xffffffffUL << GPIO_PORT_W233_PWORD_Pos) /*!< GPIO_PORT W233: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W234 ----------------------------------------- -#define GPIO_PORT_W234_PWORD_Pos 0 /*!< GPIO_PORT W234: PWORD Position */ -#define GPIO_PORT_W234_PWORD_Msk (0xffffffffUL << GPIO_PORT_W234_PWORD_Pos) /*!< GPIO_PORT W234: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W235 ----------------------------------------- -#define GPIO_PORT_W235_PWORD_Pos 0 /*!< GPIO_PORT W235: PWORD Position */ -#define GPIO_PORT_W235_PWORD_Msk (0xffffffffUL << GPIO_PORT_W235_PWORD_Pos) /*!< GPIO_PORT W235: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W236 ----------------------------------------- -#define GPIO_PORT_W236_PWORD_Pos 0 /*!< GPIO_PORT W236: PWORD Position */ -#define GPIO_PORT_W236_PWORD_Msk (0xffffffffUL << GPIO_PORT_W236_PWORD_Pos) /*!< GPIO_PORT W236: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W237 ----------------------------------------- -#define GPIO_PORT_W237_PWORD_Pos 0 /*!< GPIO_PORT W237: PWORD Position */ -#define GPIO_PORT_W237_PWORD_Msk (0xffffffffUL << GPIO_PORT_W237_PWORD_Pos) /*!< GPIO_PORT W237: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W238 ----------------------------------------- -#define GPIO_PORT_W238_PWORD_Pos 0 /*!< GPIO_PORT W238: PWORD Position */ -#define GPIO_PORT_W238_PWORD_Msk (0xffffffffUL << GPIO_PORT_W238_PWORD_Pos) /*!< GPIO_PORT W238: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W239 ----------------------------------------- -#define GPIO_PORT_W239_PWORD_Pos 0 /*!< GPIO_PORT W239: PWORD Position */ -#define GPIO_PORT_W239_PWORD_Msk (0xffffffffUL << GPIO_PORT_W239_PWORD_Pos) /*!< GPIO_PORT W239: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W240 ----------------------------------------- -#define GPIO_PORT_W240_PWORD_Pos 0 /*!< GPIO_PORT W240: PWORD Position */ -#define GPIO_PORT_W240_PWORD_Msk (0xffffffffUL << GPIO_PORT_W240_PWORD_Pos) /*!< GPIO_PORT W240: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W241 ----------------------------------------- -#define GPIO_PORT_W241_PWORD_Pos 0 /*!< GPIO_PORT W241: PWORD Position */ -#define GPIO_PORT_W241_PWORD_Msk (0xffffffffUL << GPIO_PORT_W241_PWORD_Pos) /*!< GPIO_PORT W241: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W242 ----------------------------------------- -#define GPIO_PORT_W242_PWORD_Pos 0 /*!< GPIO_PORT W242: PWORD Position */ -#define GPIO_PORT_W242_PWORD_Msk (0xffffffffUL << GPIO_PORT_W242_PWORD_Pos) /*!< GPIO_PORT W242: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W243 ----------------------------------------- -#define GPIO_PORT_W243_PWORD_Pos 0 /*!< GPIO_PORT W243: PWORD Position */ -#define GPIO_PORT_W243_PWORD_Msk (0xffffffffUL << GPIO_PORT_W243_PWORD_Pos) /*!< GPIO_PORT W243: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W244 ----------------------------------------- -#define GPIO_PORT_W244_PWORD_Pos 0 /*!< GPIO_PORT W244: PWORD Position */ -#define GPIO_PORT_W244_PWORD_Msk (0xffffffffUL << GPIO_PORT_W244_PWORD_Pos) /*!< GPIO_PORT W244: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W245 ----------------------------------------- -#define GPIO_PORT_W245_PWORD_Pos 0 /*!< GPIO_PORT W245: PWORD Position */ -#define GPIO_PORT_W245_PWORD_Msk (0xffffffffUL << GPIO_PORT_W245_PWORD_Pos) /*!< GPIO_PORT W245: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W246 ----------------------------------------- -#define GPIO_PORT_W246_PWORD_Pos 0 /*!< GPIO_PORT W246: PWORD Position */ -#define GPIO_PORT_W246_PWORD_Msk (0xffffffffUL << GPIO_PORT_W246_PWORD_Pos) /*!< GPIO_PORT W246: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W247 ----------------------------------------- -#define GPIO_PORT_W247_PWORD_Pos 0 /*!< GPIO_PORT W247: PWORD Position */ -#define GPIO_PORT_W247_PWORD_Msk (0xffffffffUL << GPIO_PORT_W247_PWORD_Pos) /*!< GPIO_PORT W247: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W248 ----------------------------------------- -#define GPIO_PORT_W248_PWORD_Pos 0 /*!< GPIO_PORT W248: PWORD Position */ -#define GPIO_PORT_W248_PWORD_Msk (0xffffffffUL << GPIO_PORT_W248_PWORD_Pos) /*!< GPIO_PORT W248: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W249 ----------------------------------------- -#define GPIO_PORT_W249_PWORD_Pos 0 /*!< GPIO_PORT W249: PWORD Position */ -#define GPIO_PORT_W249_PWORD_Msk (0xffffffffUL << GPIO_PORT_W249_PWORD_Pos) /*!< GPIO_PORT W249: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W250 ----------------------------------------- -#define GPIO_PORT_W250_PWORD_Pos 0 /*!< GPIO_PORT W250: PWORD Position */ -#define GPIO_PORT_W250_PWORD_Msk (0xffffffffUL << GPIO_PORT_W250_PWORD_Pos) /*!< GPIO_PORT W250: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W251 ----------------------------------------- -#define GPIO_PORT_W251_PWORD_Pos 0 /*!< GPIO_PORT W251: PWORD Position */ -#define GPIO_PORT_W251_PWORD_Msk (0xffffffffUL << GPIO_PORT_W251_PWORD_Pos) /*!< GPIO_PORT W251: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W252 ----------------------------------------- -#define GPIO_PORT_W252_PWORD_Pos 0 /*!< GPIO_PORT W252: PWORD Position */ -#define GPIO_PORT_W252_PWORD_Msk (0xffffffffUL << GPIO_PORT_W252_PWORD_Pos) /*!< GPIO_PORT W252: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W253 ----------------------------------------- -#define GPIO_PORT_W253_PWORD_Pos 0 /*!< GPIO_PORT W253: PWORD Position */ -#define GPIO_PORT_W253_PWORD_Msk (0xffffffffUL << GPIO_PORT_W253_PWORD_Pos) /*!< GPIO_PORT W253: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W254 ----------------------------------------- -#define GPIO_PORT_W254_PWORD_Pos 0 /*!< GPIO_PORT W254: PWORD Position */ -#define GPIO_PORT_W254_PWORD_Msk (0xffffffffUL << GPIO_PORT_W254_PWORD_Pos) /*!< GPIO_PORT W254: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_W255 ----------------------------------------- -#define GPIO_PORT_W255_PWORD_Pos 0 /*!< GPIO_PORT W255: PWORD Position */ -#define GPIO_PORT_W255_PWORD_Msk (0xffffffffUL << GPIO_PORT_W255_PWORD_Pos) /*!< GPIO_PORT W255: PWORD Mask */ - -// ------------------------------------- GPIO_PORT_DIR0 ----------------------------------------- -#define GPIO_PORT_DIR0_DIRP0_Pos 0 /*!< GPIO_PORT DIR0: DIRP0 Position */ -#define GPIO_PORT_DIR0_DIRP0_Msk (0x01UL << GPIO_PORT_DIR0_DIRP0_Pos) /*!< GPIO_PORT DIR0: DIRP0 Mask */ -#define GPIO_PORT_DIR0_DIRP1_Pos 1 /*!< GPIO_PORT DIR0: DIRP1 Position */ -#define GPIO_PORT_DIR0_DIRP1_Msk (0x01UL << GPIO_PORT_DIR0_DIRP1_Pos) /*!< GPIO_PORT DIR0: DIRP1 Mask */ -#define GPIO_PORT_DIR0_DIRP2_Pos 2 /*!< GPIO_PORT DIR0: DIRP2 Position */ -#define GPIO_PORT_DIR0_DIRP2_Msk (0x01UL << GPIO_PORT_DIR0_DIRP2_Pos) /*!< GPIO_PORT DIR0: DIRP2 Mask */ -#define GPIO_PORT_DIR0_DIRP3_Pos 3 /*!< GPIO_PORT DIR0: DIRP3 Position */ -#define GPIO_PORT_DIR0_DIRP3_Msk (0x01UL << GPIO_PORT_DIR0_DIRP3_Pos) /*!< GPIO_PORT DIR0: DIRP3 Mask */ -#define GPIO_PORT_DIR0_DIRP4_Pos 4 /*!< GPIO_PORT DIR0: DIRP4 Position */ -#define GPIO_PORT_DIR0_DIRP4_Msk (0x01UL << GPIO_PORT_DIR0_DIRP4_Pos) /*!< GPIO_PORT DIR0: DIRP4 Mask */ -#define GPIO_PORT_DIR0_DIRP5_Pos 5 /*!< GPIO_PORT DIR0: DIRP5 Position */ -#define GPIO_PORT_DIR0_DIRP5_Msk (0x01UL << GPIO_PORT_DIR0_DIRP5_Pos) /*!< GPIO_PORT DIR0: DIRP5 Mask */ -#define GPIO_PORT_DIR0_DIRP6_Pos 6 /*!< GPIO_PORT DIR0: DIRP6 Position */ -#define GPIO_PORT_DIR0_DIRP6_Msk (0x01UL << GPIO_PORT_DIR0_DIRP6_Pos) /*!< GPIO_PORT DIR0: DIRP6 Mask */ -#define GPIO_PORT_DIR0_DIRP7_Pos 7 /*!< GPIO_PORT DIR0: DIRP7 Position */ -#define GPIO_PORT_DIR0_DIRP7_Msk (0x01UL << GPIO_PORT_DIR0_DIRP7_Pos) /*!< GPIO_PORT DIR0: DIRP7 Mask */ -#define GPIO_PORT_DIR0_DIRP8_Pos 8 /*!< GPIO_PORT DIR0: DIRP8 Position */ -#define GPIO_PORT_DIR0_DIRP8_Msk (0x01UL << GPIO_PORT_DIR0_DIRP8_Pos) /*!< GPIO_PORT DIR0: DIRP8 Mask */ -#define GPIO_PORT_DIR0_DIRP9_Pos 9 /*!< GPIO_PORT DIR0: DIRP9 Position */ -#define GPIO_PORT_DIR0_DIRP9_Msk (0x01UL << GPIO_PORT_DIR0_DIRP9_Pos) /*!< GPIO_PORT DIR0: DIRP9 Mask */ -#define GPIO_PORT_DIR0_DIRP10_Pos 10 /*!< GPIO_PORT DIR0: DIRP10 Position */ -#define GPIO_PORT_DIR0_DIRP10_Msk (0x01UL << GPIO_PORT_DIR0_DIRP10_Pos) /*!< GPIO_PORT DIR0: DIRP10 Mask */ -#define GPIO_PORT_DIR0_DIRP11_Pos 11 /*!< GPIO_PORT DIR0: DIRP11 Position */ -#define GPIO_PORT_DIR0_DIRP11_Msk (0x01UL << GPIO_PORT_DIR0_DIRP11_Pos) /*!< GPIO_PORT DIR0: DIRP11 Mask */ -#define GPIO_PORT_DIR0_DIRP12_Pos 12 /*!< GPIO_PORT DIR0: DIRP12 Position */ -#define GPIO_PORT_DIR0_DIRP12_Msk (0x01UL << GPIO_PORT_DIR0_DIRP12_Pos) /*!< GPIO_PORT DIR0: DIRP12 Mask */ -#define GPIO_PORT_DIR0_DIRP13_Pos 13 /*!< GPIO_PORT DIR0: DIRP13 Position */ -#define GPIO_PORT_DIR0_DIRP13_Msk (0x01UL << GPIO_PORT_DIR0_DIRP13_Pos) /*!< GPIO_PORT DIR0: DIRP13 Mask */ -#define GPIO_PORT_DIR0_DIRP14_Pos 14 /*!< GPIO_PORT DIR0: DIRP14 Position */ -#define GPIO_PORT_DIR0_DIRP14_Msk (0x01UL << GPIO_PORT_DIR0_DIRP14_Pos) /*!< GPIO_PORT DIR0: DIRP14 Mask */ -#define GPIO_PORT_DIR0_DIRP15_Pos 15 /*!< GPIO_PORT DIR0: DIRP15 Position */ -#define GPIO_PORT_DIR0_DIRP15_Msk (0x01UL << GPIO_PORT_DIR0_DIRP15_Pos) /*!< GPIO_PORT DIR0: DIRP15 Mask */ -#define GPIO_PORT_DIR0_DIRP16_Pos 16 /*!< GPIO_PORT DIR0: DIRP16 Position */ -#define GPIO_PORT_DIR0_DIRP16_Msk (0x01UL << GPIO_PORT_DIR0_DIRP16_Pos) /*!< GPIO_PORT DIR0: DIRP16 Mask */ -#define GPIO_PORT_DIR0_DIRP17_Pos 17 /*!< GPIO_PORT DIR0: DIRP17 Position */ -#define GPIO_PORT_DIR0_DIRP17_Msk (0x01UL << GPIO_PORT_DIR0_DIRP17_Pos) /*!< GPIO_PORT DIR0: DIRP17 Mask */ -#define GPIO_PORT_DIR0_DIRP18_Pos 18 /*!< GPIO_PORT DIR0: DIRP18 Position */ -#define GPIO_PORT_DIR0_DIRP18_Msk (0x01UL << GPIO_PORT_DIR0_DIRP18_Pos) /*!< GPIO_PORT DIR0: DIRP18 Mask */ -#define GPIO_PORT_DIR0_DIRP19_Pos 19 /*!< GPIO_PORT DIR0: DIRP19 Position */ -#define GPIO_PORT_DIR0_DIRP19_Msk (0x01UL << GPIO_PORT_DIR0_DIRP19_Pos) /*!< GPIO_PORT DIR0: DIRP19 Mask */ -#define GPIO_PORT_DIR0_DIRP20_Pos 20 /*!< GPIO_PORT DIR0: DIRP20 Position */ -#define GPIO_PORT_DIR0_DIRP20_Msk (0x01UL << GPIO_PORT_DIR0_DIRP20_Pos) /*!< GPIO_PORT DIR0: DIRP20 Mask */ -#define GPIO_PORT_DIR0_DIRP21_Pos 21 /*!< GPIO_PORT DIR0: DIRP21 Position */ -#define GPIO_PORT_DIR0_DIRP21_Msk (0x01UL << GPIO_PORT_DIR0_DIRP21_Pos) /*!< GPIO_PORT DIR0: DIRP21 Mask */ -#define GPIO_PORT_DIR0_DIRP22_Pos 22 /*!< GPIO_PORT DIR0: DIRP22 Position */ -#define GPIO_PORT_DIR0_DIRP22_Msk (0x01UL << GPIO_PORT_DIR0_DIRP22_Pos) /*!< GPIO_PORT DIR0: DIRP22 Mask */ -#define GPIO_PORT_DIR0_DIRP23_Pos 23 /*!< GPIO_PORT DIR0: DIRP23 Position */ -#define GPIO_PORT_DIR0_DIRP23_Msk (0x01UL << GPIO_PORT_DIR0_DIRP23_Pos) /*!< GPIO_PORT DIR0: DIRP23 Mask */ -#define GPIO_PORT_DIR0_DIRP24_Pos 24 /*!< GPIO_PORT DIR0: DIRP24 Position */ -#define GPIO_PORT_DIR0_DIRP24_Msk (0x01UL << GPIO_PORT_DIR0_DIRP24_Pos) /*!< GPIO_PORT DIR0: DIRP24 Mask */ -#define GPIO_PORT_DIR0_DIRP25_Pos 25 /*!< GPIO_PORT DIR0: DIRP25 Position */ -#define GPIO_PORT_DIR0_DIRP25_Msk (0x01UL << GPIO_PORT_DIR0_DIRP25_Pos) /*!< GPIO_PORT DIR0: DIRP25 Mask */ -#define GPIO_PORT_DIR0_DIRP26_Pos 26 /*!< GPIO_PORT DIR0: DIRP26 Position */ -#define GPIO_PORT_DIR0_DIRP26_Msk (0x01UL << GPIO_PORT_DIR0_DIRP26_Pos) /*!< GPIO_PORT DIR0: DIRP26 Mask */ -#define GPIO_PORT_DIR0_DIRP27_Pos 27 /*!< GPIO_PORT DIR0: DIRP27 Position */ -#define GPIO_PORT_DIR0_DIRP27_Msk (0x01UL << GPIO_PORT_DIR0_DIRP27_Pos) /*!< GPIO_PORT DIR0: DIRP27 Mask */ -#define GPIO_PORT_DIR0_DIRP28_Pos 28 /*!< GPIO_PORT DIR0: DIRP28 Position */ -#define GPIO_PORT_DIR0_DIRP28_Msk (0x01UL << GPIO_PORT_DIR0_DIRP28_Pos) /*!< GPIO_PORT DIR0: DIRP28 Mask */ -#define GPIO_PORT_DIR0_DIRP29_Pos 29 /*!< GPIO_PORT DIR0: DIRP29 Position */ -#define GPIO_PORT_DIR0_DIRP29_Msk (0x01UL << GPIO_PORT_DIR0_DIRP29_Pos) /*!< GPIO_PORT DIR0: DIRP29 Mask */ -#define GPIO_PORT_DIR0_DIRP30_Pos 30 /*!< GPIO_PORT DIR0: DIRP30 Position */ -#define GPIO_PORT_DIR0_DIRP30_Msk (0x01UL << GPIO_PORT_DIR0_DIRP30_Pos) /*!< GPIO_PORT DIR0: DIRP30 Mask */ -#define GPIO_PORT_DIR0_DIRP31_Pos 31 /*!< GPIO_PORT DIR0: DIRP31 Position */ -#define GPIO_PORT_DIR0_DIRP31_Msk (0x01UL << GPIO_PORT_DIR0_DIRP31_Pos) /*!< GPIO_PORT DIR0: DIRP31 Mask */ - -// ------------------------------------- GPIO_PORT_DIR1 ----------------------------------------- -#define GPIO_PORT_DIR1_DIRP0_Pos 0 /*!< GPIO_PORT DIR1: DIRP0 Position */ -#define GPIO_PORT_DIR1_DIRP0_Msk (0x01UL << GPIO_PORT_DIR1_DIRP0_Pos) /*!< GPIO_PORT DIR1: DIRP0 Mask */ -#define GPIO_PORT_DIR1_DIRP1_Pos 1 /*!< GPIO_PORT DIR1: DIRP1 Position */ -#define GPIO_PORT_DIR1_DIRP1_Msk (0x01UL << GPIO_PORT_DIR1_DIRP1_Pos) /*!< GPIO_PORT DIR1: DIRP1 Mask */ -#define GPIO_PORT_DIR1_DIRP2_Pos 2 /*!< GPIO_PORT DIR1: DIRP2 Position */ -#define GPIO_PORT_DIR1_DIRP2_Msk (0x01UL << GPIO_PORT_DIR1_DIRP2_Pos) /*!< GPIO_PORT DIR1: DIRP2 Mask */ -#define GPIO_PORT_DIR1_DIRP3_Pos 3 /*!< GPIO_PORT DIR1: DIRP3 Position */ -#define GPIO_PORT_DIR1_DIRP3_Msk (0x01UL << GPIO_PORT_DIR1_DIRP3_Pos) /*!< GPIO_PORT DIR1: DIRP3 Mask */ -#define GPIO_PORT_DIR1_DIRP4_Pos 4 /*!< GPIO_PORT DIR1: DIRP4 Position */ -#define GPIO_PORT_DIR1_DIRP4_Msk (0x01UL << GPIO_PORT_DIR1_DIRP4_Pos) /*!< GPIO_PORT DIR1: DIRP4 Mask */ -#define GPIO_PORT_DIR1_DIRP5_Pos 5 /*!< GPIO_PORT DIR1: DIRP5 Position */ -#define GPIO_PORT_DIR1_DIRP5_Msk (0x01UL << GPIO_PORT_DIR1_DIRP5_Pos) /*!< GPIO_PORT DIR1: DIRP5 Mask */ -#define GPIO_PORT_DIR1_DIRP6_Pos 6 /*!< GPIO_PORT DIR1: DIRP6 Position */ -#define GPIO_PORT_DIR1_DIRP6_Msk (0x01UL << GPIO_PORT_DIR1_DIRP6_Pos) /*!< GPIO_PORT DIR1: DIRP6 Mask */ -#define GPIO_PORT_DIR1_DIRP7_Pos 7 /*!< GPIO_PORT DIR1: DIRP7 Position */ -#define GPIO_PORT_DIR1_DIRP7_Msk (0x01UL << GPIO_PORT_DIR1_DIRP7_Pos) /*!< GPIO_PORT DIR1: DIRP7 Mask */ -#define GPIO_PORT_DIR1_DIRP8_Pos 8 /*!< GPIO_PORT DIR1: DIRP8 Position */ -#define GPIO_PORT_DIR1_DIRP8_Msk (0x01UL << GPIO_PORT_DIR1_DIRP8_Pos) /*!< GPIO_PORT DIR1: DIRP8 Mask */ -#define GPIO_PORT_DIR1_DIRP9_Pos 9 /*!< GPIO_PORT DIR1: DIRP9 Position */ -#define GPIO_PORT_DIR1_DIRP9_Msk (0x01UL << GPIO_PORT_DIR1_DIRP9_Pos) /*!< GPIO_PORT DIR1: DIRP9 Mask */ -#define GPIO_PORT_DIR1_DIRP10_Pos 10 /*!< GPIO_PORT DIR1: DIRP10 Position */ -#define GPIO_PORT_DIR1_DIRP10_Msk (0x01UL << GPIO_PORT_DIR1_DIRP10_Pos) /*!< GPIO_PORT DIR1: DIRP10 Mask */ -#define GPIO_PORT_DIR1_DIRP11_Pos 11 /*!< GPIO_PORT DIR1: DIRP11 Position */ -#define GPIO_PORT_DIR1_DIRP11_Msk (0x01UL << GPIO_PORT_DIR1_DIRP11_Pos) /*!< GPIO_PORT DIR1: DIRP11 Mask */ -#define GPIO_PORT_DIR1_DIRP12_Pos 12 /*!< GPIO_PORT DIR1: DIRP12 Position */ -#define GPIO_PORT_DIR1_DIRP12_Msk (0x01UL << GPIO_PORT_DIR1_DIRP12_Pos) /*!< GPIO_PORT DIR1: DIRP12 Mask */ -#define GPIO_PORT_DIR1_DIRP13_Pos 13 /*!< GPIO_PORT DIR1: DIRP13 Position */ -#define GPIO_PORT_DIR1_DIRP13_Msk (0x01UL << GPIO_PORT_DIR1_DIRP13_Pos) /*!< GPIO_PORT DIR1: DIRP13 Mask */ -#define GPIO_PORT_DIR1_DIRP14_Pos 14 /*!< GPIO_PORT DIR1: DIRP14 Position */ -#define GPIO_PORT_DIR1_DIRP14_Msk (0x01UL << GPIO_PORT_DIR1_DIRP14_Pos) /*!< GPIO_PORT DIR1: DIRP14 Mask */ -#define GPIO_PORT_DIR1_DIRP15_Pos 15 /*!< GPIO_PORT DIR1: DIRP15 Position */ -#define GPIO_PORT_DIR1_DIRP15_Msk (0x01UL << GPIO_PORT_DIR1_DIRP15_Pos) /*!< GPIO_PORT DIR1: DIRP15 Mask */ -#define GPIO_PORT_DIR1_DIRP16_Pos 16 /*!< GPIO_PORT DIR1: DIRP16 Position */ -#define GPIO_PORT_DIR1_DIRP16_Msk (0x01UL << GPIO_PORT_DIR1_DIRP16_Pos) /*!< GPIO_PORT DIR1: DIRP16 Mask */ -#define GPIO_PORT_DIR1_DIRP17_Pos 17 /*!< GPIO_PORT DIR1: DIRP17 Position */ -#define GPIO_PORT_DIR1_DIRP17_Msk (0x01UL << GPIO_PORT_DIR1_DIRP17_Pos) /*!< GPIO_PORT DIR1: DIRP17 Mask */ -#define GPIO_PORT_DIR1_DIRP18_Pos 18 /*!< GPIO_PORT DIR1: DIRP18 Position */ -#define GPIO_PORT_DIR1_DIRP18_Msk (0x01UL << GPIO_PORT_DIR1_DIRP18_Pos) /*!< GPIO_PORT DIR1: DIRP18 Mask */ -#define GPIO_PORT_DIR1_DIRP19_Pos 19 /*!< GPIO_PORT DIR1: DIRP19 Position */ -#define GPIO_PORT_DIR1_DIRP19_Msk (0x01UL << GPIO_PORT_DIR1_DIRP19_Pos) /*!< GPIO_PORT DIR1: DIRP19 Mask */ -#define GPIO_PORT_DIR1_DIRP20_Pos 20 /*!< GPIO_PORT DIR1: DIRP20 Position */ -#define GPIO_PORT_DIR1_DIRP20_Msk (0x01UL << GPIO_PORT_DIR1_DIRP20_Pos) /*!< GPIO_PORT DIR1: DIRP20 Mask */ -#define GPIO_PORT_DIR1_DIRP21_Pos 21 /*!< GPIO_PORT DIR1: DIRP21 Position */ -#define GPIO_PORT_DIR1_DIRP21_Msk (0x01UL << GPIO_PORT_DIR1_DIRP21_Pos) /*!< GPIO_PORT DIR1: DIRP21 Mask */ -#define GPIO_PORT_DIR1_DIRP22_Pos 22 /*!< GPIO_PORT DIR1: DIRP22 Position */ -#define GPIO_PORT_DIR1_DIRP22_Msk (0x01UL << GPIO_PORT_DIR1_DIRP22_Pos) /*!< GPIO_PORT DIR1: DIRP22 Mask */ -#define GPIO_PORT_DIR1_DIRP23_Pos 23 /*!< GPIO_PORT DIR1: DIRP23 Position */ -#define GPIO_PORT_DIR1_DIRP23_Msk (0x01UL << GPIO_PORT_DIR1_DIRP23_Pos) /*!< GPIO_PORT DIR1: DIRP23 Mask */ -#define GPIO_PORT_DIR1_DIRP24_Pos 24 /*!< GPIO_PORT DIR1: DIRP24 Position */ -#define GPIO_PORT_DIR1_DIRP24_Msk (0x01UL << GPIO_PORT_DIR1_DIRP24_Pos) /*!< GPIO_PORT DIR1: DIRP24 Mask */ -#define GPIO_PORT_DIR1_DIRP25_Pos 25 /*!< GPIO_PORT DIR1: DIRP25 Position */ -#define GPIO_PORT_DIR1_DIRP25_Msk (0x01UL << GPIO_PORT_DIR1_DIRP25_Pos) /*!< GPIO_PORT DIR1: DIRP25 Mask */ -#define GPIO_PORT_DIR1_DIRP26_Pos 26 /*!< GPIO_PORT DIR1: DIRP26 Position */ -#define GPIO_PORT_DIR1_DIRP26_Msk (0x01UL << GPIO_PORT_DIR1_DIRP26_Pos) /*!< GPIO_PORT DIR1: DIRP26 Mask */ -#define GPIO_PORT_DIR1_DIRP27_Pos 27 /*!< GPIO_PORT DIR1: DIRP27 Position */ -#define GPIO_PORT_DIR1_DIRP27_Msk (0x01UL << GPIO_PORT_DIR1_DIRP27_Pos) /*!< GPIO_PORT DIR1: DIRP27 Mask */ -#define GPIO_PORT_DIR1_DIRP28_Pos 28 /*!< GPIO_PORT DIR1: DIRP28 Position */ -#define GPIO_PORT_DIR1_DIRP28_Msk (0x01UL << GPIO_PORT_DIR1_DIRP28_Pos) /*!< GPIO_PORT DIR1: DIRP28 Mask */ -#define GPIO_PORT_DIR1_DIRP29_Pos 29 /*!< GPIO_PORT DIR1: DIRP29 Position */ -#define GPIO_PORT_DIR1_DIRP29_Msk (0x01UL << GPIO_PORT_DIR1_DIRP29_Pos) /*!< GPIO_PORT DIR1: DIRP29 Mask */ -#define GPIO_PORT_DIR1_DIRP30_Pos 30 /*!< GPIO_PORT DIR1: DIRP30 Position */ -#define GPIO_PORT_DIR1_DIRP30_Msk (0x01UL << GPIO_PORT_DIR1_DIRP30_Pos) /*!< GPIO_PORT DIR1: DIRP30 Mask */ -#define GPIO_PORT_DIR1_DIRP31_Pos 31 /*!< GPIO_PORT DIR1: DIRP31 Position */ -#define GPIO_PORT_DIR1_DIRP31_Msk (0x01UL << GPIO_PORT_DIR1_DIRP31_Pos) /*!< GPIO_PORT DIR1: DIRP31 Mask */ - -// ------------------------------------- GPIO_PORT_DIR2 ----------------------------------------- -#define GPIO_PORT_DIR2_DIRP0_Pos 0 /*!< GPIO_PORT DIR2: DIRP0 Position */ -#define GPIO_PORT_DIR2_DIRP0_Msk (0x01UL << GPIO_PORT_DIR2_DIRP0_Pos) /*!< GPIO_PORT DIR2: DIRP0 Mask */ -#define GPIO_PORT_DIR2_DIRP1_Pos 1 /*!< GPIO_PORT DIR2: DIRP1 Position */ -#define GPIO_PORT_DIR2_DIRP1_Msk (0x01UL << GPIO_PORT_DIR2_DIRP1_Pos) /*!< GPIO_PORT DIR2: DIRP1 Mask */ -#define GPIO_PORT_DIR2_DIRP2_Pos 2 /*!< GPIO_PORT DIR2: DIRP2 Position */ -#define GPIO_PORT_DIR2_DIRP2_Msk (0x01UL << GPIO_PORT_DIR2_DIRP2_Pos) /*!< GPIO_PORT DIR2: DIRP2 Mask */ -#define GPIO_PORT_DIR2_DIRP3_Pos 3 /*!< GPIO_PORT DIR2: DIRP3 Position */ -#define GPIO_PORT_DIR2_DIRP3_Msk (0x01UL << GPIO_PORT_DIR2_DIRP3_Pos) /*!< GPIO_PORT DIR2: DIRP3 Mask */ -#define GPIO_PORT_DIR2_DIRP4_Pos 4 /*!< GPIO_PORT DIR2: DIRP4 Position */ -#define GPIO_PORT_DIR2_DIRP4_Msk (0x01UL << GPIO_PORT_DIR2_DIRP4_Pos) /*!< GPIO_PORT DIR2: DIRP4 Mask */ -#define GPIO_PORT_DIR2_DIRP5_Pos 5 /*!< GPIO_PORT DIR2: DIRP5 Position */ -#define GPIO_PORT_DIR2_DIRP5_Msk (0x01UL << GPIO_PORT_DIR2_DIRP5_Pos) /*!< GPIO_PORT DIR2: DIRP5 Mask */ -#define GPIO_PORT_DIR2_DIRP6_Pos 6 /*!< GPIO_PORT DIR2: DIRP6 Position */ -#define GPIO_PORT_DIR2_DIRP6_Msk (0x01UL << GPIO_PORT_DIR2_DIRP6_Pos) /*!< GPIO_PORT DIR2: DIRP6 Mask */ -#define GPIO_PORT_DIR2_DIRP7_Pos 7 /*!< GPIO_PORT DIR2: DIRP7 Position */ -#define GPIO_PORT_DIR2_DIRP7_Msk (0x01UL << GPIO_PORT_DIR2_DIRP7_Pos) /*!< GPIO_PORT DIR2: DIRP7 Mask */ -#define GPIO_PORT_DIR2_DIRP8_Pos 8 /*!< GPIO_PORT DIR2: DIRP8 Position */ -#define GPIO_PORT_DIR2_DIRP8_Msk (0x01UL << GPIO_PORT_DIR2_DIRP8_Pos) /*!< GPIO_PORT DIR2: DIRP8 Mask */ -#define GPIO_PORT_DIR2_DIRP9_Pos 9 /*!< GPIO_PORT DIR2: DIRP9 Position */ -#define GPIO_PORT_DIR2_DIRP9_Msk (0x01UL << GPIO_PORT_DIR2_DIRP9_Pos) /*!< GPIO_PORT DIR2: DIRP9 Mask */ -#define GPIO_PORT_DIR2_DIRP10_Pos 10 /*!< GPIO_PORT DIR2: DIRP10 Position */ -#define GPIO_PORT_DIR2_DIRP10_Msk (0x01UL << GPIO_PORT_DIR2_DIRP10_Pos) /*!< GPIO_PORT DIR2: DIRP10 Mask */ -#define GPIO_PORT_DIR2_DIRP11_Pos 11 /*!< GPIO_PORT DIR2: DIRP11 Position */ -#define GPIO_PORT_DIR2_DIRP11_Msk (0x01UL << GPIO_PORT_DIR2_DIRP11_Pos) /*!< GPIO_PORT DIR2: DIRP11 Mask */ -#define GPIO_PORT_DIR2_DIRP12_Pos 12 /*!< GPIO_PORT DIR2: DIRP12 Position */ -#define GPIO_PORT_DIR2_DIRP12_Msk (0x01UL << GPIO_PORT_DIR2_DIRP12_Pos) /*!< GPIO_PORT DIR2: DIRP12 Mask */ -#define GPIO_PORT_DIR2_DIRP13_Pos 13 /*!< GPIO_PORT DIR2: DIRP13 Position */ -#define GPIO_PORT_DIR2_DIRP13_Msk (0x01UL << GPIO_PORT_DIR2_DIRP13_Pos) /*!< GPIO_PORT DIR2: DIRP13 Mask */ -#define GPIO_PORT_DIR2_DIRP14_Pos 14 /*!< GPIO_PORT DIR2: DIRP14 Position */ -#define GPIO_PORT_DIR2_DIRP14_Msk (0x01UL << GPIO_PORT_DIR2_DIRP14_Pos) /*!< GPIO_PORT DIR2: DIRP14 Mask */ -#define GPIO_PORT_DIR2_DIRP15_Pos 15 /*!< GPIO_PORT DIR2: DIRP15 Position */ -#define GPIO_PORT_DIR2_DIRP15_Msk (0x01UL << GPIO_PORT_DIR2_DIRP15_Pos) /*!< GPIO_PORT DIR2: DIRP15 Mask */ -#define GPIO_PORT_DIR2_DIRP16_Pos 16 /*!< GPIO_PORT DIR2: DIRP16 Position */ -#define GPIO_PORT_DIR2_DIRP16_Msk (0x01UL << GPIO_PORT_DIR2_DIRP16_Pos) /*!< GPIO_PORT DIR2: DIRP16 Mask */ -#define GPIO_PORT_DIR2_DIRP17_Pos 17 /*!< GPIO_PORT DIR2: DIRP17 Position */ -#define GPIO_PORT_DIR2_DIRP17_Msk (0x01UL << GPIO_PORT_DIR2_DIRP17_Pos) /*!< GPIO_PORT DIR2: DIRP17 Mask */ -#define GPIO_PORT_DIR2_DIRP18_Pos 18 /*!< GPIO_PORT DIR2: DIRP18 Position */ -#define GPIO_PORT_DIR2_DIRP18_Msk (0x01UL << GPIO_PORT_DIR2_DIRP18_Pos) /*!< GPIO_PORT DIR2: DIRP18 Mask */ -#define GPIO_PORT_DIR2_DIRP19_Pos 19 /*!< GPIO_PORT DIR2: DIRP19 Position */ -#define GPIO_PORT_DIR2_DIRP19_Msk (0x01UL << GPIO_PORT_DIR2_DIRP19_Pos) /*!< GPIO_PORT DIR2: DIRP19 Mask */ -#define GPIO_PORT_DIR2_DIRP20_Pos 20 /*!< GPIO_PORT DIR2: DIRP20 Position */ -#define GPIO_PORT_DIR2_DIRP20_Msk (0x01UL << GPIO_PORT_DIR2_DIRP20_Pos) /*!< GPIO_PORT DIR2: DIRP20 Mask */ -#define GPIO_PORT_DIR2_DIRP21_Pos 21 /*!< GPIO_PORT DIR2: DIRP21 Position */ -#define GPIO_PORT_DIR2_DIRP21_Msk (0x01UL << GPIO_PORT_DIR2_DIRP21_Pos) /*!< GPIO_PORT DIR2: DIRP21 Mask */ -#define GPIO_PORT_DIR2_DIRP22_Pos 22 /*!< GPIO_PORT DIR2: DIRP22 Position */ -#define GPIO_PORT_DIR2_DIRP22_Msk (0x01UL << GPIO_PORT_DIR2_DIRP22_Pos) /*!< GPIO_PORT DIR2: DIRP22 Mask */ -#define GPIO_PORT_DIR2_DIRP23_Pos 23 /*!< GPIO_PORT DIR2: DIRP23 Position */ -#define GPIO_PORT_DIR2_DIRP23_Msk (0x01UL << GPIO_PORT_DIR2_DIRP23_Pos) /*!< GPIO_PORT DIR2: DIRP23 Mask */ -#define GPIO_PORT_DIR2_DIRP24_Pos 24 /*!< GPIO_PORT DIR2: DIRP24 Position */ -#define GPIO_PORT_DIR2_DIRP24_Msk (0x01UL << GPIO_PORT_DIR2_DIRP24_Pos) /*!< GPIO_PORT DIR2: DIRP24 Mask */ -#define GPIO_PORT_DIR2_DIRP25_Pos 25 /*!< GPIO_PORT DIR2: DIRP25 Position */ -#define GPIO_PORT_DIR2_DIRP25_Msk (0x01UL << GPIO_PORT_DIR2_DIRP25_Pos) /*!< GPIO_PORT DIR2: DIRP25 Mask */ -#define GPIO_PORT_DIR2_DIRP26_Pos 26 /*!< GPIO_PORT DIR2: DIRP26 Position */ -#define GPIO_PORT_DIR2_DIRP26_Msk (0x01UL << GPIO_PORT_DIR2_DIRP26_Pos) /*!< GPIO_PORT DIR2: DIRP26 Mask */ -#define GPIO_PORT_DIR2_DIRP27_Pos 27 /*!< GPIO_PORT DIR2: DIRP27 Position */ -#define GPIO_PORT_DIR2_DIRP27_Msk (0x01UL << GPIO_PORT_DIR2_DIRP27_Pos) /*!< GPIO_PORT DIR2: DIRP27 Mask */ -#define GPIO_PORT_DIR2_DIRP28_Pos 28 /*!< GPIO_PORT DIR2: DIRP28 Position */ -#define GPIO_PORT_DIR2_DIRP28_Msk (0x01UL << GPIO_PORT_DIR2_DIRP28_Pos) /*!< GPIO_PORT DIR2: DIRP28 Mask */ -#define GPIO_PORT_DIR2_DIRP29_Pos 29 /*!< GPIO_PORT DIR2: DIRP29 Position */ -#define GPIO_PORT_DIR2_DIRP29_Msk (0x01UL << GPIO_PORT_DIR2_DIRP29_Pos) /*!< GPIO_PORT DIR2: DIRP29 Mask */ -#define GPIO_PORT_DIR2_DIRP30_Pos 30 /*!< GPIO_PORT DIR2: DIRP30 Position */ -#define GPIO_PORT_DIR2_DIRP30_Msk (0x01UL << GPIO_PORT_DIR2_DIRP30_Pos) /*!< GPIO_PORT DIR2: DIRP30 Mask */ -#define GPIO_PORT_DIR2_DIRP31_Pos 31 /*!< GPIO_PORT DIR2: DIRP31 Position */ -#define GPIO_PORT_DIR2_DIRP31_Msk (0x01UL << GPIO_PORT_DIR2_DIRP31_Pos) /*!< GPIO_PORT DIR2: DIRP31 Mask */ - -// ------------------------------------- GPIO_PORT_DIR3 ----------------------------------------- -#define GPIO_PORT_DIR3_DIRP0_Pos 0 /*!< GPIO_PORT DIR3: DIRP0 Position */ -#define GPIO_PORT_DIR3_DIRP0_Msk (0x01UL << GPIO_PORT_DIR3_DIRP0_Pos) /*!< GPIO_PORT DIR3: DIRP0 Mask */ -#define GPIO_PORT_DIR3_DIRP1_Pos 1 /*!< GPIO_PORT DIR3: DIRP1 Position */ -#define GPIO_PORT_DIR3_DIRP1_Msk (0x01UL << GPIO_PORT_DIR3_DIRP1_Pos) /*!< GPIO_PORT DIR3: DIRP1 Mask */ -#define GPIO_PORT_DIR3_DIRP2_Pos 2 /*!< GPIO_PORT DIR3: DIRP2 Position */ -#define GPIO_PORT_DIR3_DIRP2_Msk (0x01UL << GPIO_PORT_DIR3_DIRP2_Pos) /*!< GPIO_PORT DIR3: DIRP2 Mask */ -#define GPIO_PORT_DIR3_DIRP3_Pos 3 /*!< GPIO_PORT DIR3: DIRP3 Position */ -#define GPIO_PORT_DIR3_DIRP3_Msk (0x01UL << GPIO_PORT_DIR3_DIRP3_Pos) /*!< GPIO_PORT DIR3: DIRP3 Mask */ -#define GPIO_PORT_DIR3_DIRP4_Pos 4 /*!< GPIO_PORT DIR3: DIRP4 Position */ -#define GPIO_PORT_DIR3_DIRP4_Msk (0x01UL << GPIO_PORT_DIR3_DIRP4_Pos) /*!< GPIO_PORT DIR3: DIRP4 Mask */ -#define GPIO_PORT_DIR3_DIRP5_Pos 5 /*!< GPIO_PORT DIR3: DIRP5 Position */ -#define GPIO_PORT_DIR3_DIRP5_Msk (0x01UL << GPIO_PORT_DIR3_DIRP5_Pos) /*!< GPIO_PORT DIR3: DIRP5 Mask */ -#define GPIO_PORT_DIR3_DIRP6_Pos 6 /*!< GPIO_PORT DIR3: DIRP6 Position */ -#define GPIO_PORT_DIR3_DIRP6_Msk (0x01UL << GPIO_PORT_DIR3_DIRP6_Pos) /*!< GPIO_PORT DIR3: DIRP6 Mask */ -#define GPIO_PORT_DIR3_DIRP7_Pos 7 /*!< GPIO_PORT DIR3: DIRP7 Position */ -#define GPIO_PORT_DIR3_DIRP7_Msk (0x01UL << GPIO_PORT_DIR3_DIRP7_Pos) /*!< GPIO_PORT DIR3: DIRP7 Mask */ -#define GPIO_PORT_DIR3_DIRP8_Pos 8 /*!< GPIO_PORT DIR3: DIRP8 Position */ -#define GPIO_PORT_DIR3_DIRP8_Msk (0x01UL << GPIO_PORT_DIR3_DIRP8_Pos) /*!< GPIO_PORT DIR3: DIRP8 Mask */ -#define GPIO_PORT_DIR3_DIRP9_Pos 9 /*!< GPIO_PORT DIR3: DIRP9 Position */ -#define GPIO_PORT_DIR3_DIRP9_Msk (0x01UL << GPIO_PORT_DIR3_DIRP9_Pos) /*!< GPIO_PORT DIR3: DIRP9 Mask */ -#define GPIO_PORT_DIR3_DIRP10_Pos 10 /*!< GPIO_PORT DIR3: DIRP10 Position */ -#define GPIO_PORT_DIR3_DIRP10_Msk (0x01UL << GPIO_PORT_DIR3_DIRP10_Pos) /*!< GPIO_PORT DIR3: DIRP10 Mask */ -#define GPIO_PORT_DIR3_DIRP11_Pos 11 /*!< GPIO_PORT DIR3: DIRP11 Position */ -#define GPIO_PORT_DIR3_DIRP11_Msk (0x01UL << GPIO_PORT_DIR3_DIRP11_Pos) /*!< GPIO_PORT DIR3: DIRP11 Mask */ -#define GPIO_PORT_DIR3_DIRP12_Pos 12 /*!< GPIO_PORT DIR3: DIRP12 Position */ -#define GPIO_PORT_DIR3_DIRP12_Msk (0x01UL << GPIO_PORT_DIR3_DIRP12_Pos) /*!< GPIO_PORT DIR3: DIRP12 Mask */ -#define GPIO_PORT_DIR3_DIRP13_Pos 13 /*!< GPIO_PORT DIR3: DIRP13 Position */ -#define GPIO_PORT_DIR3_DIRP13_Msk (0x01UL << GPIO_PORT_DIR3_DIRP13_Pos) /*!< GPIO_PORT DIR3: DIRP13 Mask */ -#define GPIO_PORT_DIR3_DIRP14_Pos 14 /*!< GPIO_PORT DIR3: DIRP14 Position */ -#define GPIO_PORT_DIR3_DIRP14_Msk (0x01UL << GPIO_PORT_DIR3_DIRP14_Pos) /*!< GPIO_PORT DIR3: DIRP14 Mask */ -#define GPIO_PORT_DIR3_DIRP15_Pos 15 /*!< GPIO_PORT DIR3: DIRP15 Position */ -#define GPIO_PORT_DIR3_DIRP15_Msk (0x01UL << GPIO_PORT_DIR3_DIRP15_Pos) /*!< GPIO_PORT DIR3: DIRP15 Mask */ -#define GPIO_PORT_DIR3_DIRP16_Pos 16 /*!< GPIO_PORT DIR3: DIRP16 Position */ -#define GPIO_PORT_DIR3_DIRP16_Msk (0x01UL << GPIO_PORT_DIR3_DIRP16_Pos) /*!< GPIO_PORT DIR3: DIRP16 Mask */ -#define GPIO_PORT_DIR3_DIRP17_Pos 17 /*!< GPIO_PORT DIR3: DIRP17 Position */ -#define GPIO_PORT_DIR3_DIRP17_Msk (0x01UL << GPIO_PORT_DIR3_DIRP17_Pos) /*!< GPIO_PORT DIR3: DIRP17 Mask */ -#define GPIO_PORT_DIR3_DIRP18_Pos 18 /*!< GPIO_PORT DIR3: DIRP18 Position */ -#define GPIO_PORT_DIR3_DIRP18_Msk (0x01UL << GPIO_PORT_DIR3_DIRP18_Pos) /*!< GPIO_PORT DIR3: DIRP18 Mask */ -#define GPIO_PORT_DIR3_DIRP19_Pos 19 /*!< GPIO_PORT DIR3: DIRP19 Position */ -#define GPIO_PORT_DIR3_DIRP19_Msk (0x01UL << GPIO_PORT_DIR3_DIRP19_Pos) /*!< GPIO_PORT DIR3: DIRP19 Mask */ -#define GPIO_PORT_DIR3_DIRP20_Pos 20 /*!< GPIO_PORT DIR3: DIRP20 Position */ -#define GPIO_PORT_DIR3_DIRP20_Msk (0x01UL << GPIO_PORT_DIR3_DIRP20_Pos) /*!< GPIO_PORT DIR3: DIRP20 Mask */ -#define GPIO_PORT_DIR3_DIRP21_Pos 21 /*!< GPIO_PORT DIR3: DIRP21 Position */ -#define GPIO_PORT_DIR3_DIRP21_Msk (0x01UL << GPIO_PORT_DIR3_DIRP21_Pos) /*!< GPIO_PORT DIR3: DIRP21 Mask */ -#define GPIO_PORT_DIR3_DIRP22_Pos 22 /*!< GPIO_PORT DIR3: DIRP22 Position */ -#define GPIO_PORT_DIR3_DIRP22_Msk (0x01UL << GPIO_PORT_DIR3_DIRP22_Pos) /*!< GPIO_PORT DIR3: DIRP22 Mask */ -#define GPIO_PORT_DIR3_DIRP23_Pos 23 /*!< GPIO_PORT DIR3: DIRP23 Position */ -#define GPIO_PORT_DIR3_DIRP23_Msk (0x01UL << GPIO_PORT_DIR3_DIRP23_Pos) /*!< GPIO_PORT DIR3: DIRP23 Mask */ -#define GPIO_PORT_DIR3_DIRP24_Pos 24 /*!< GPIO_PORT DIR3: DIRP24 Position */ -#define GPIO_PORT_DIR3_DIRP24_Msk (0x01UL << GPIO_PORT_DIR3_DIRP24_Pos) /*!< GPIO_PORT DIR3: DIRP24 Mask */ -#define GPIO_PORT_DIR3_DIRP25_Pos 25 /*!< GPIO_PORT DIR3: DIRP25 Position */ -#define GPIO_PORT_DIR3_DIRP25_Msk (0x01UL << GPIO_PORT_DIR3_DIRP25_Pos) /*!< GPIO_PORT DIR3: DIRP25 Mask */ -#define GPIO_PORT_DIR3_DIRP26_Pos 26 /*!< GPIO_PORT DIR3: DIRP26 Position */ -#define GPIO_PORT_DIR3_DIRP26_Msk (0x01UL << GPIO_PORT_DIR3_DIRP26_Pos) /*!< GPIO_PORT DIR3: DIRP26 Mask */ -#define GPIO_PORT_DIR3_DIRP27_Pos 27 /*!< GPIO_PORT DIR3: DIRP27 Position */ -#define GPIO_PORT_DIR3_DIRP27_Msk (0x01UL << GPIO_PORT_DIR3_DIRP27_Pos) /*!< GPIO_PORT DIR3: DIRP27 Mask */ -#define GPIO_PORT_DIR3_DIRP28_Pos 28 /*!< GPIO_PORT DIR3: DIRP28 Position */ -#define GPIO_PORT_DIR3_DIRP28_Msk (0x01UL << GPIO_PORT_DIR3_DIRP28_Pos) /*!< GPIO_PORT DIR3: DIRP28 Mask */ -#define GPIO_PORT_DIR3_DIRP29_Pos 29 /*!< GPIO_PORT DIR3: DIRP29 Position */ -#define GPIO_PORT_DIR3_DIRP29_Msk (0x01UL << GPIO_PORT_DIR3_DIRP29_Pos) /*!< GPIO_PORT DIR3: DIRP29 Mask */ -#define GPIO_PORT_DIR3_DIRP30_Pos 30 /*!< GPIO_PORT DIR3: DIRP30 Position */ -#define GPIO_PORT_DIR3_DIRP30_Msk (0x01UL << GPIO_PORT_DIR3_DIRP30_Pos) /*!< GPIO_PORT DIR3: DIRP30 Mask */ -#define GPIO_PORT_DIR3_DIRP31_Pos 31 /*!< GPIO_PORT DIR3: DIRP31 Position */ -#define GPIO_PORT_DIR3_DIRP31_Msk (0x01UL << GPIO_PORT_DIR3_DIRP31_Pos) /*!< GPIO_PORT DIR3: DIRP31 Mask */ - -// ------------------------------------- GPIO_PORT_DIR4 ----------------------------------------- -#define GPIO_PORT_DIR4_DIRP0_Pos 0 /*!< GPIO_PORT DIR4: DIRP0 Position */ -#define GPIO_PORT_DIR4_DIRP0_Msk (0x01UL << GPIO_PORT_DIR4_DIRP0_Pos) /*!< GPIO_PORT DIR4: DIRP0 Mask */ -#define GPIO_PORT_DIR4_DIRP1_Pos 1 /*!< GPIO_PORT DIR4: DIRP1 Position */ -#define GPIO_PORT_DIR4_DIRP1_Msk (0x01UL << GPIO_PORT_DIR4_DIRP1_Pos) /*!< GPIO_PORT DIR4: DIRP1 Mask */ -#define GPIO_PORT_DIR4_DIRP2_Pos 2 /*!< GPIO_PORT DIR4: DIRP2 Position */ -#define GPIO_PORT_DIR4_DIRP2_Msk (0x01UL << GPIO_PORT_DIR4_DIRP2_Pos) /*!< GPIO_PORT DIR4: DIRP2 Mask */ -#define GPIO_PORT_DIR4_DIRP3_Pos 3 /*!< GPIO_PORT DIR4: DIRP3 Position */ -#define GPIO_PORT_DIR4_DIRP3_Msk (0x01UL << GPIO_PORT_DIR4_DIRP3_Pos) /*!< GPIO_PORT DIR4: DIRP3 Mask */ -#define GPIO_PORT_DIR4_DIRP4_Pos 4 /*!< GPIO_PORT DIR4: DIRP4 Position */ -#define GPIO_PORT_DIR4_DIRP4_Msk (0x01UL << GPIO_PORT_DIR4_DIRP4_Pos) /*!< GPIO_PORT DIR4: DIRP4 Mask */ -#define GPIO_PORT_DIR4_DIRP5_Pos 5 /*!< GPIO_PORT DIR4: DIRP5 Position */ -#define GPIO_PORT_DIR4_DIRP5_Msk (0x01UL << GPIO_PORT_DIR4_DIRP5_Pos) /*!< GPIO_PORT DIR4: DIRP5 Mask */ -#define GPIO_PORT_DIR4_DIRP6_Pos 6 /*!< GPIO_PORT DIR4: DIRP6 Position */ -#define GPIO_PORT_DIR4_DIRP6_Msk (0x01UL << GPIO_PORT_DIR4_DIRP6_Pos) /*!< GPIO_PORT DIR4: DIRP6 Mask */ -#define GPIO_PORT_DIR4_DIRP7_Pos 7 /*!< GPIO_PORT DIR4: DIRP7 Position */ -#define GPIO_PORT_DIR4_DIRP7_Msk (0x01UL << GPIO_PORT_DIR4_DIRP7_Pos) /*!< GPIO_PORT DIR4: DIRP7 Mask */ -#define GPIO_PORT_DIR4_DIRP8_Pos 8 /*!< GPIO_PORT DIR4: DIRP8 Position */ -#define GPIO_PORT_DIR4_DIRP8_Msk (0x01UL << GPIO_PORT_DIR4_DIRP8_Pos) /*!< GPIO_PORT DIR4: DIRP8 Mask */ -#define GPIO_PORT_DIR4_DIRP9_Pos 9 /*!< GPIO_PORT DIR4: DIRP9 Position */ -#define GPIO_PORT_DIR4_DIRP9_Msk (0x01UL << GPIO_PORT_DIR4_DIRP9_Pos) /*!< GPIO_PORT DIR4: DIRP9 Mask */ -#define GPIO_PORT_DIR4_DIRP10_Pos 10 /*!< GPIO_PORT DIR4: DIRP10 Position */ -#define GPIO_PORT_DIR4_DIRP10_Msk (0x01UL << GPIO_PORT_DIR4_DIRP10_Pos) /*!< GPIO_PORT DIR4: DIRP10 Mask */ -#define GPIO_PORT_DIR4_DIRP11_Pos 11 /*!< GPIO_PORT DIR4: DIRP11 Position */ -#define GPIO_PORT_DIR4_DIRP11_Msk (0x01UL << GPIO_PORT_DIR4_DIRP11_Pos) /*!< GPIO_PORT DIR4: DIRP11 Mask */ -#define GPIO_PORT_DIR4_DIRP12_Pos 12 /*!< GPIO_PORT DIR4: DIRP12 Position */ -#define GPIO_PORT_DIR4_DIRP12_Msk (0x01UL << GPIO_PORT_DIR4_DIRP12_Pos) /*!< GPIO_PORT DIR4: DIRP12 Mask */ -#define GPIO_PORT_DIR4_DIRP13_Pos 13 /*!< GPIO_PORT DIR4: DIRP13 Position */ -#define GPIO_PORT_DIR4_DIRP13_Msk (0x01UL << GPIO_PORT_DIR4_DIRP13_Pos) /*!< GPIO_PORT DIR4: DIRP13 Mask */ -#define GPIO_PORT_DIR4_DIRP14_Pos 14 /*!< GPIO_PORT DIR4: DIRP14 Position */ -#define GPIO_PORT_DIR4_DIRP14_Msk (0x01UL << GPIO_PORT_DIR4_DIRP14_Pos) /*!< GPIO_PORT DIR4: DIRP14 Mask */ -#define GPIO_PORT_DIR4_DIRP15_Pos 15 /*!< GPIO_PORT DIR4: DIRP15 Position */ -#define GPIO_PORT_DIR4_DIRP15_Msk (0x01UL << GPIO_PORT_DIR4_DIRP15_Pos) /*!< GPIO_PORT DIR4: DIRP15 Mask */ -#define GPIO_PORT_DIR4_DIRP16_Pos 16 /*!< GPIO_PORT DIR4: DIRP16 Position */ -#define GPIO_PORT_DIR4_DIRP16_Msk (0x01UL << GPIO_PORT_DIR4_DIRP16_Pos) /*!< GPIO_PORT DIR4: DIRP16 Mask */ -#define GPIO_PORT_DIR4_DIRP17_Pos 17 /*!< GPIO_PORT DIR4: DIRP17 Position */ -#define GPIO_PORT_DIR4_DIRP17_Msk (0x01UL << GPIO_PORT_DIR4_DIRP17_Pos) /*!< GPIO_PORT DIR4: DIRP17 Mask */ -#define GPIO_PORT_DIR4_DIRP18_Pos 18 /*!< GPIO_PORT DIR4: DIRP18 Position */ -#define GPIO_PORT_DIR4_DIRP18_Msk (0x01UL << GPIO_PORT_DIR4_DIRP18_Pos) /*!< GPIO_PORT DIR4: DIRP18 Mask */ -#define GPIO_PORT_DIR4_DIRP19_Pos 19 /*!< GPIO_PORT DIR4: DIRP19 Position */ -#define GPIO_PORT_DIR4_DIRP19_Msk (0x01UL << GPIO_PORT_DIR4_DIRP19_Pos) /*!< GPIO_PORT DIR4: DIRP19 Mask */ -#define GPIO_PORT_DIR4_DIRP20_Pos 20 /*!< GPIO_PORT DIR4: DIRP20 Position */ -#define GPIO_PORT_DIR4_DIRP20_Msk (0x01UL << GPIO_PORT_DIR4_DIRP20_Pos) /*!< GPIO_PORT DIR4: DIRP20 Mask */ -#define GPIO_PORT_DIR4_DIRP21_Pos 21 /*!< GPIO_PORT DIR4: DIRP21 Position */ -#define GPIO_PORT_DIR4_DIRP21_Msk (0x01UL << GPIO_PORT_DIR4_DIRP21_Pos) /*!< GPIO_PORT DIR4: DIRP21 Mask */ -#define GPIO_PORT_DIR4_DIRP22_Pos 22 /*!< GPIO_PORT DIR4: DIRP22 Position */ -#define GPIO_PORT_DIR4_DIRP22_Msk (0x01UL << GPIO_PORT_DIR4_DIRP22_Pos) /*!< GPIO_PORT DIR4: DIRP22 Mask */ -#define GPIO_PORT_DIR4_DIRP23_Pos 23 /*!< GPIO_PORT DIR4: DIRP23 Position */ -#define GPIO_PORT_DIR4_DIRP23_Msk (0x01UL << GPIO_PORT_DIR4_DIRP23_Pos) /*!< GPIO_PORT DIR4: DIRP23 Mask */ -#define GPIO_PORT_DIR4_DIRP24_Pos 24 /*!< GPIO_PORT DIR4: DIRP24 Position */ -#define GPIO_PORT_DIR4_DIRP24_Msk (0x01UL << GPIO_PORT_DIR4_DIRP24_Pos) /*!< GPIO_PORT DIR4: DIRP24 Mask */ -#define GPIO_PORT_DIR4_DIRP25_Pos 25 /*!< GPIO_PORT DIR4: DIRP25 Position */ -#define GPIO_PORT_DIR4_DIRP25_Msk (0x01UL << GPIO_PORT_DIR4_DIRP25_Pos) /*!< GPIO_PORT DIR4: DIRP25 Mask */ -#define GPIO_PORT_DIR4_DIRP26_Pos 26 /*!< GPIO_PORT DIR4: DIRP26 Position */ -#define GPIO_PORT_DIR4_DIRP26_Msk (0x01UL << GPIO_PORT_DIR4_DIRP26_Pos) /*!< GPIO_PORT DIR4: DIRP26 Mask */ -#define GPIO_PORT_DIR4_DIRP27_Pos 27 /*!< GPIO_PORT DIR4: DIRP27 Position */ -#define GPIO_PORT_DIR4_DIRP27_Msk (0x01UL << GPIO_PORT_DIR4_DIRP27_Pos) /*!< GPIO_PORT DIR4: DIRP27 Mask */ -#define GPIO_PORT_DIR4_DIRP28_Pos 28 /*!< GPIO_PORT DIR4: DIRP28 Position */ -#define GPIO_PORT_DIR4_DIRP28_Msk (0x01UL << GPIO_PORT_DIR4_DIRP28_Pos) /*!< GPIO_PORT DIR4: DIRP28 Mask */ -#define GPIO_PORT_DIR4_DIRP29_Pos 29 /*!< GPIO_PORT DIR4: DIRP29 Position */ -#define GPIO_PORT_DIR4_DIRP29_Msk (0x01UL << GPIO_PORT_DIR4_DIRP29_Pos) /*!< GPIO_PORT DIR4: DIRP29 Mask */ -#define GPIO_PORT_DIR4_DIRP30_Pos 30 /*!< GPIO_PORT DIR4: DIRP30 Position */ -#define GPIO_PORT_DIR4_DIRP30_Msk (0x01UL << GPIO_PORT_DIR4_DIRP30_Pos) /*!< GPIO_PORT DIR4: DIRP30 Mask */ -#define GPIO_PORT_DIR4_DIRP31_Pos 31 /*!< GPIO_PORT DIR4: DIRP31 Position */ -#define GPIO_PORT_DIR4_DIRP31_Msk (0x01UL << GPIO_PORT_DIR4_DIRP31_Pos) /*!< GPIO_PORT DIR4: DIRP31 Mask */ - -// ------------------------------------- GPIO_PORT_DIR5 ----------------------------------------- -#define GPIO_PORT_DIR5_DIRP0_Pos 0 /*!< GPIO_PORT DIR5: DIRP0 Position */ -#define GPIO_PORT_DIR5_DIRP0_Msk (0x01UL << GPIO_PORT_DIR5_DIRP0_Pos) /*!< GPIO_PORT DIR5: DIRP0 Mask */ -#define GPIO_PORT_DIR5_DIRP1_Pos 1 /*!< GPIO_PORT DIR5: DIRP1 Position */ -#define GPIO_PORT_DIR5_DIRP1_Msk (0x01UL << GPIO_PORT_DIR5_DIRP1_Pos) /*!< GPIO_PORT DIR5: DIRP1 Mask */ -#define GPIO_PORT_DIR5_DIRP2_Pos 2 /*!< GPIO_PORT DIR5: DIRP2 Position */ -#define GPIO_PORT_DIR5_DIRP2_Msk (0x01UL << GPIO_PORT_DIR5_DIRP2_Pos) /*!< GPIO_PORT DIR5: DIRP2 Mask */ -#define GPIO_PORT_DIR5_DIRP3_Pos 3 /*!< GPIO_PORT DIR5: DIRP3 Position */ -#define GPIO_PORT_DIR5_DIRP3_Msk (0x01UL << GPIO_PORT_DIR5_DIRP3_Pos) /*!< GPIO_PORT DIR5: DIRP3 Mask */ -#define GPIO_PORT_DIR5_DIRP4_Pos 4 /*!< GPIO_PORT DIR5: DIRP4 Position */ -#define GPIO_PORT_DIR5_DIRP4_Msk (0x01UL << GPIO_PORT_DIR5_DIRP4_Pos) /*!< GPIO_PORT DIR5: DIRP4 Mask */ -#define GPIO_PORT_DIR5_DIRP5_Pos 5 /*!< GPIO_PORT DIR5: DIRP5 Position */ -#define GPIO_PORT_DIR5_DIRP5_Msk (0x01UL << GPIO_PORT_DIR5_DIRP5_Pos) /*!< GPIO_PORT DIR5: DIRP5 Mask */ -#define GPIO_PORT_DIR5_DIRP6_Pos 6 /*!< GPIO_PORT DIR5: DIRP6 Position */ -#define GPIO_PORT_DIR5_DIRP6_Msk (0x01UL << GPIO_PORT_DIR5_DIRP6_Pos) /*!< GPIO_PORT DIR5: DIRP6 Mask */ -#define GPIO_PORT_DIR5_DIRP7_Pos 7 /*!< GPIO_PORT DIR5: DIRP7 Position */ -#define GPIO_PORT_DIR5_DIRP7_Msk (0x01UL << GPIO_PORT_DIR5_DIRP7_Pos) /*!< GPIO_PORT DIR5: DIRP7 Mask */ -#define GPIO_PORT_DIR5_DIRP8_Pos 8 /*!< GPIO_PORT DIR5: DIRP8 Position */ -#define GPIO_PORT_DIR5_DIRP8_Msk (0x01UL << GPIO_PORT_DIR5_DIRP8_Pos) /*!< GPIO_PORT DIR5: DIRP8 Mask */ -#define GPIO_PORT_DIR5_DIRP9_Pos 9 /*!< GPIO_PORT DIR5: DIRP9 Position */ -#define GPIO_PORT_DIR5_DIRP9_Msk (0x01UL << GPIO_PORT_DIR5_DIRP9_Pos) /*!< GPIO_PORT DIR5: DIRP9 Mask */ -#define GPIO_PORT_DIR5_DIRP10_Pos 10 /*!< GPIO_PORT DIR5: DIRP10 Position */ -#define GPIO_PORT_DIR5_DIRP10_Msk (0x01UL << GPIO_PORT_DIR5_DIRP10_Pos) /*!< GPIO_PORT DIR5: DIRP10 Mask */ -#define GPIO_PORT_DIR5_DIRP11_Pos 11 /*!< GPIO_PORT DIR5: DIRP11 Position */ -#define GPIO_PORT_DIR5_DIRP11_Msk (0x01UL << GPIO_PORT_DIR5_DIRP11_Pos) /*!< GPIO_PORT DIR5: DIRP11 Mask */ -#define GPIO_PORT_DIR5_DIRP12_Pos 12 /*!< GPIO_PORT DIR5: DIRP12 Position */ -#define GPIO_PORT_DIR5_DIRP12_Msk (0x01UL << GPIO_PORT_DIR5_DIRP12_Pos) /*!< GPIO_PORT DIR5: DIRP12 Mask */ -#define GPIO_PORT_DIR5_DIRP13_Pos 13 /*!< GPIO_PORT DIR5: DIRP13 Position */ -#define GPIO_PORT_DIR5_DIRP13_Msk (0x01UL << GPIO_PORT_DIR5_DIRP13_Pos) /*!< GPIO_PORT DIR5: DIRP13 Mask */ -#define GPIO_PORT_DIR5_DIRP14_Pos 14 /*!< GPIO_PORT DIR5: DIRP14 Position */ -#define GPIO_PORT_DIR5_DIRP14_Msk (0x01UL << GPIO_PORT_DIR5_DIRP14_Pos) /*!< GPIO_PORT DIR5: DIRP14 Mask */ -#define GPIO_PORT_DIR5_DIRP15_Pos 15 /*!< GPIO_PORT DIR5: DIRP15 Position */ -#define GPIO_PORT_DIR5_DIRP15_Msk (0x01UL << GPIO_PORT_DIR5_DIRP15_Pos) /*!< GPIO_PORT DIR5: DIRP15 Mask */ -#define GPIO_PORT_DIR5_DIRP16_Pos 16 /*!< GPIO_PORT DIR5: DIRP16 Position */ -#define GPIO_PORT_DIR5_DIRP16_Msk (0x01UL << GPIO_PORT_DIR5_DIRP16_Pos) /*!< GPIO_PORT DIR5: DIRP16 Mask */ -#define GPIO_PORT_DIR5_DIRP17_Pos 17 /*!< GPIO_PORT DIR5: DIRP17 Position */ -#define GPIO_PORT_DIR5_DIRP17_Msk (0x01UL << GPIO_PORT_DIR5_DIRP17_Pos) /*!< GPIO_PORT DIR5: DIRP17 Mask */ -#define GPIO_PORT_DIR5_DIRP18_Pos 18 /*!< GPIO_PORT DIR5: DIRP18 Position */ -#define GPIO_PORT_DIR5_DIRP18_Msk (0x01UL << GPIO_PORT_DIR5_DIRP18_Pos) /*!< GPIO_PORT DIR5: DIRP18 Mask */ -#define GPIO_PORT_DIR5_DIRP19_Pos 19 /*!< GPIO_PORT DIR5: DIRP19 Position */ -#define GPIO_PORT_DIR5_DIRP19_Msk (0x01UL << GPIO_PORT_DIR5_DIRP19_Pos) /*!< GPIO_PORT DIR5: DIRP19 Mask */ -#define GPIO_PORT_DIR5_DIRP20_Pos 20 /*!< GPIO_PORT DIR5: DIRP20 Position */ -#define GPIO_PORT_DIR5_DIRP20_Msk (0x01UL << GPIO_PORT_DIR5_DIRP20_Pos) /*!< GPIO_PORT DIR5: DIRP20 Mask */ -#define GPIO_PORT_DIR5_DIRP21_Pos 21 /*!< GPIO_PORT DIR5: DIRP21 Position */ -#define GPIO_PORT_DIR5_DIRP21_Msk (0x01UL << GPIO_PORT_DIR5_DIRP21_Pos) /*!< GPIO_PORT DIR5: DIRP21 Mask */ -#define GPIO_PORT_DIR5_DIRP22_Pos 22 /*!< GPIO_PORT DIR5: DIRP22 Position */ -#define GPIO_PORT_DIR5_DIRP22_Msk (0x01UL << GPIO_PORT_DIR5_DIRP22_Pos) /*!< GPIO_PORT DIR5: DIRP22 Mask */ -#define GPIO_PORT_DIR5_DIRP23_Pos 23 /*!< GPIO_PORT DIR5: DIRP23 Position */ -#define GPIO_PORT_DIR5_DIRP23_Msk (0x01UL << GPIO_PORT_DIR5_DIRP23_Pos) /*!< GPIO_PORT DIR5: DIRP23 Mask */ -#define GPIO_PORT_DIR5_DIRP24_Pos 24 /*!< GPIO_PORT DIR5: DIRP24 Position */ -#define GPIO_PORT_DIR5_DIRP24_Msk (0x01UL << GPIO_PORT_DIR5_DIRP24_Pos) /*!< GPIO_PORT DIR5: DIRP24 Mask */ -#define GPIO_PORT_DIR5_DIRP25_Pos 25 /*!< GPIO_PORT DIR5: DIRP25 Position */ -#define GPIO_PORT_DIR5_DIRP25_Msk (0x01UL << GPIO_PORT_DIR5_DIRP25_Pos) /*!< GPIO_PORT DIR5: DIRP25 Mask */ -#define GPIO_PORT_DIR5_DIRP26_Pos 26 /*!< GPIO_PORT DIR5: DIRP26 Position */ -#define GPIO_PORT_DIR5_DIRP26_Msk (0x01UL << GPIO_PORT_DIR5_DIRP26_Pos) /*!< GPIO_PORT DIR5: DIRP26 Mask */ -#define GPIO_PORT_DIR5_DIRP27_Pos 27 /*!< GPIO_PORT DIR5: DIRP27 Position */ -#define GPIO_PORT_DIR5_DIRP27_Msk (0x01UL << GPIO_PORT_DIR5_DIRP27_Pos) /*!< GPIO_PORT DIR5: DIRP27 Mask */ -#define GPIO_PORT_DIR5_DIRP28_Pos 28 /*!< GPIO_PORT DIR5: DIRP28 Position */ -#define GPIO_PORT_DIR5_DIRP28_Msk (0x01UL << GPIO_PORT_DIR5_DIRP28_Pos) /*!< GPIO_PORT DIR5: DIRP28 Mask */ -#define GPIO_PORT_DIR5_DIRP29_Pos 29 /*!< GPIO_PORT DIR5: DIRP29 Position */ -#define GPIO_PORT_DIR5_DIRP29_Msk (0x01UL << GPIO_PORT_DIR5_DIRP29_Pos) /*!< GPIO_PORT DIR5: DIRP29 Mask */ -#define GPIO_PORT_DIR5_DIRP30_Pos 30 /*!< GPIO_PORT DIR5: DIRP30 Position */ -#define GPIO_PORT_DIR5_DIRP30_Msk (0x01UL << GPIO_PORT_DIR5_DIRP30_Pos) /*!< GPIO_PORT DIR5: DIRP30 Mask */ -#define GPIO_PORT_DIR5_DIRP31_Pos 31 /*!< GPIO_PORT DIR5: DIRP31 Position */ -#define GPIO_PORT_DIR5_DIRP31_Msk (0x01UL << GPIO_PORT_DIR5_DIRP31_Pos) /*!< GPIO_PORT DIR5: DIRP31 Mask */ - -// ------------------------------------- GPIO_PORT_DIR6 ----------------------------------------- -#define GPIO_PORT_DIR6_DIRP0_Pos 0 /*!< GPIO_PORT DIR6: DIRP0 Position */ -#define GPIO_PORT_DIR6_DIRP0_Msk (0x01UL << GPIO_PORT_DIR6_DIRP0_Pos) /*!< GPIO_PORT DIR6: DIRP0 Mask */ -#define GPIO_PORT_DIR6_DIRP1_Pos 1 /*!< GPIO_PORT DIR6: DIRP1 Position */ -#define GPIO_PORT_DIR6_DIRP1_Msk (0x01UL << GPIO_PORT_DIR6_DIRP1_Pos) /*!< GPIO_PORT DIR6: DIRP1 Mask */ -#define GPIO_PORT_DIR6_DIRP2_Pos 2 /*!< GPIO_PORT DIR6: DIRP2 Position */ -#define GPIO_PORT_DIR6_DIRP2_Msk (0x01UL << GPIO_PORT_DIR6_DIRP2_Pos) /*!< GPIO_PORT DIR6: DIRP2 Mask */ -#define GPIO_PORT_DIR6_DIRP3_Pos 3 /*!< GPIO_PORT DIR6: DIRP3 Position */ -#define GPIO_PORT_DIR6_DIRP3_Msk (0x01UL << GPIO_PORT_DIR6_DIRP3_Pos) /*!< GPIO_PORT DIR6: DIRP3 Mask */ -#define GPIO_PORT_DIR6_DIRP4_Pos 4 /*!< GPIO_PORT DIR6: DIRP4 Position */ -#define GPIO_PORT_DIR6_DIRP4_Msk (0x01UL << GPIO_PORT_DIR6_DIRP4_Pos) /*!< GPIO_PORT DIR6: DIRP4 Mask */ -#define GPIO_PORT_DIR6_DIRP5_Pos 5 /*!< GPIO_PORT DIR6: DIRP5 Position */ -#define GPIO_PORT_DIR6_DIRP5_Msk (0x01UL << GPIO_PORT_DIR6_DIRP5_Pos) /*!< GPIO_PORT DIR6: DIRP5 Mask */ -#define GPIO_PORT_DIR6_DIRP6_Pos 6 /*!< GPIO_PORT DIR6: DIRP6 Position */ -#define GPIO_PORT_DIR6_DIRP6_Msk (0x01UL << GPIO_PORT_DIR6_DIRP6_Pos) /*!< GPIO_PORT DIR6: DIRP6 Mask */ -#define GPIO_PORT_DIR6_DIRP7_Pos 7 /*!< GPIO_PORT DIR6: DIRP7 Position */ -#define GPIO_PORT_DIR6_DIRP7_Msk (0x01UL << GPIO_PORT_DIR6_DIRP7_Pos) /*!< GPIO_PORT DIR6: DIRP7 Mask */ -#define GPIO_PORT_DIR6_DIRP8_Pos 8 /*!< GPIO_PORT DIR6: DIRP8 Position */ -#define GPIO_PORT_DIR6_DIRP8_Msk (0x01UL << GPIO_PORT_DIR6_DIRP8_Pos) /*!< GPIO_PORT DIR6: DIRP8 Mask */ -#define GPIO_PORT_DIR6_DIRP9_Pos 9 /*!< GPIO_PORT DIR6: DIRP9 Position */ -#define GPIO_PORT_DIR6_DIRP9_Msk (0x01UL << GPIO_PORT_DIR6_DIRP9_Pos) /*!< GPIO_PORT DIR6: DIRP9 Mask */ -#define GPIO_PORT_DIR6_DIRP10_Pos 10 /*!< GPIO_PORT DIR6: DIRP10 Position */ -#define GPIO_PORT_DIR6_DIRP10_Msk (0x01UL << GPIO_PORT_DIR6_DIRP10_Pos) /*!< GPIO_PORT DIR6: DIRP10 Mask */ -#define GPIO_PORT_DIR6_DIRP11_Pos 11 /*!< GPIO_PORT DIR6: DIRP11 Position */ -#define GPIO_PORT_DIR6_DIRP11_Msk (0x01UL << GPIO_PORT_DIR6_DIRP11_Pos) /*!< GPIO_PORT DIR6: DIRP11 Mask */ -#define GPIO_PORT_DIR6_DIRP12_Pos 12 /*!< GPIO_PORT DIR6: DIRP12 Position */ -#define GPIO_PORT_DIR6_DIRP12_Msk (0x01UL << GPIO_PORT_DIR6_DIRP12_Pos) /*!< GPIO_PORT DIR6: DIRP12 Mask */ -#define GPIO_PORT_DIR6_DIRP13_Pos 13 /*!< GPIO_PORT DIR6: DIRP13 Position */ -#define GPIO_PORT_DIR6_DIRP13_Msk (0x01UL << GPIO_PORT_DIR6_DIRP13_Pos) /*!< GPIO_PORT DIR6: DIRP13 Mask */ -#define GPIO_PORT_DIR6_DIRP14_Pos 14 /*!< GPIO_PORT DIR6: DIRP14 Position */ -#define GPIO_PORT_DIR6_DIRP14_Msk (0x01UL << GPIO_PORT_DIR6_DIRP14_Pos) /*!< GPIO_PORT DIR6: DIRP14 Mask */ -#define GPIO_PORT_DIR6_DIRP15_Pos 15 /*!< GPIO_PORT DIR6: DIRP15 Position */ -#define GPIO_PORT_DIR6_DIRP15_Msk (0x01UL << GPIO_PORT_DIR6_DIRP15_Pos) /*!< GPIO_PORT DIR6: DIRP15 Mask */ -#define GPIO_PORT_DIR6_DIRP16_Pos 16 /*!< GPIO_PORT DIR6: DIRP16 Position */ -#define GPIO_PORT_DIR6_DIRP16_Msk (0x01UL << GPIO_PORT_DIR6_DIRP16_Pos) /*!< GPIO_PORT DIR6: DIRP16 Mask */ -#define GPIO_PORT_DIR6_DIRP17_Pos 17 /*!< GPIO_PORT DIR6: DIRP17 Position */ -#define GPIO_PORT_DIR6_DIRP17_Msk (0x01UL << GPIO_PORT_DIR6_DIRP17_Pos) /*!< GPIO_PORT DIR6: DIRP17 Mask */ -#define GPIO_PORT_DIR6_DIRP18_Pos 18 /*!< GPIO_PORT DIR6: DIRP18 Position */ -#define GPIO_PORT_DIR6_DIRP18_Msk (0x01UL << GPIO_PORT_DIR6_DIRP18_Pos) /*!< GPIO_PORT DIR6: DIRP18 Mask */ -#define GPIO_PORT_DIR6_DIRP19_Pos 19 /*!< GPIO_PORT DIR6: DIRP19 Position */ -#define GPIO_PORT_DIR6_DIRP19_Msk (0x01UL << GPIO_PORT_DIR6_DIRP19_Pos) /*!< GPIO_PORT DIR6: DIRP19 Mask */ -#define GPIO_PORT_DIR6_DIRP20_Pos 20 /*!< GPIO_PORT DIR6: DIRP20 Position */ -#define GPIO_PORT_DIR6_DIRP20_Msk (0x01UL << GPIO_PORT_DIR6_DIRP20_Pos) /*!< GPIO_PORT DIR6: DIRP20 Mask */ -#define GPIO_PORT_DIR6_DIRP21_Pos 21 /*!< GPIO_PORT DIR6: DIRP21 Position */ -#define GPIO_PORT_DIR6_DIRP21_Msk (0x01UL << GPIO_PORT_DIR6_DIRP21_Pos) /*!< GPIO_PORT DIR6: DIRP21 Mask */ -#define GPIO_PORT_DIR6_DIRP22_Pos 22 /*!< GPIO_PORT DIR6: DIRP22 Position */ -#define GPIO_PORT_DIR6_DIRP22_Msk (0x01UL << GPIO_PORT_DIR6_DIRP22_Pos) /*!< GPIO_PORT DIR6: DIRP22 Mask */ -#define GPIO_PORT_DIR6_DIRP23_Pos 23 /*!< GPIO_PORT DIR6: DIRP23 Position */ -#define GPIO_PORT_DIR6_DIRP23_Msk (0x01UL << GPIO_PORT_DIR6_DIRP23_Pos) /*!< GPIO_PORT DIR6: DIRP23 Mask */ -#define GPIO_PORT_DIR6_DIRP24_Pos 24 /*!< GPIO_PORT DIR6: DIRP24 Position */ -#define GPIO_PORT_DIR6_DIRP24_Msk (0x01UL << GPIO_PORT_DIR6_DIRP24_Pos) /*!< GPIO_PORT DIR6: DIRP24 Mask */ -#define GPIO_PORT_DIR6_DIRP25_Pos 25 /*!< GPIO_PORT DIR6: DIRP25 Position */ -#define GPIO_PORT_DIR6_DIRP25_Msk (0x01UL << GPIO_PORT_DIR6_DIRP25_Pos) /*!< GPIO_PORT DIR6: DIRP25 Mask */ -#define GPIO_PORT_DIR6_DIRP26_Pos 26 /*!< GPIO_PORT DIR6: DIRP26 Position */ -#define GPIO_PORT_DIR6_DIRP26_Msk (0x01UL << GPIO_PORT_DIR6_DIRP26_Pos) /*!< GPIO_PORT DIR6: DIRP26 Mask */ -#define GPIO_PORT_DIR6_DIRP27_Pos 27 /*!< GPIO_PORT DIR6: DIRP27 Position */ -#define GPIO_PORT_DIR6_DIRP27_Msk (0x01UL << GPIO_PORT_DIR6_DIRP27_Pos) /*!< GPIO_PORT DIR6: DIRP27 Mask */ -#define GPIO_PORT_DIR6_DIRP28_Pos 28 /*!< GPIO_PORT DIR6: DIRP28 Position */ -#define GPIO_PORT_DIR6_DIRP28_Msk (0x01UL << GPIO_PORT_DIR6_DIRP28_Pos) /*!< GPIO_PORT DIR6: DIRP28 Mask */ -#define GPIO_PORT_DIR6_DIRP29_Pos 29 /*!< GPIO_PORT DIR6: DIRP29 Position */ -#define GPIO_PORT_DIR6_DIRP29_Msk (0x01UL << GPIO_PORT_DIR6_DIRP29_Pos) /*!< GPIO_PORT DIR6: DIRP29 Mask */ -#define GPIO_PORT_DIR6_DIRP30_Pos 30 /*!< GPIO_PORT DIR6: DIRP30 Position */ -#define GPIO_PORT_DIR6_DIRP30_Msk (0x01UL << GPIO_PORT_DIR6_DIRP30_Pos) /*!< GPIO_PORT DIR6: DIRP30 Mask */ -#define GPIO_PORT_DIR6_DIRP31_Pos 31 /*!< GPIO_PORT DIR6: DIRP31 Position */ -#define GPIO_PORT_DIR6_DIRP31_Msk (0x01UL << GPIO_PORT_DIR6_DIRP31_Pos) /*!< GPIO_PORT DIR6: DIRP31 Mask */ - -// ------------------------------------- GPIO_PORT_DIR7 ----------------------------------------- -#define GPIO_PORT_DIR7_DIRP0_Pos 0 /*!< GPIO_PORT DIR7: DIRP0 Position */ -#define GPIO_PORT_DIR7_DIRP0_Msk (0x01UL << GPIO_PORT_DIR7_DIRP0_Pos) /*!< GPIO_PORT DIR7: DIRP0 Mask */ -#define GPIO_PORT_DIR7_DIRP1_Pos 1 /*!< GPIO_PORT DIR7: DIRP1 Position */ -#define GPIO_PORT_DIR7_DIRP1_Msk (0x01UL << GPIO_PORT_DIR7_DIRP1_Pos) /*!< GPIO_PORT DIR7: DIRP1 Mask */ -#define GPIO_PORT_DIR7_DIRP2_Pos 2 /*!< GPIO_PORT DIR7: DIRP2 Position */ -#define GPIO_PORT_DIR7_DIRP2_Msk (0x01UL << GPIO_PORT_DIR7_DIRP2_Pos) /*!< GPIO_PORT DIR7: DIRP2 Mask */ -#define GPIO_PORT_DIR7_DIRP3_Pos 3 /*!< GPIO_PORT DIR7: DIRP3 Position */ -#define GPIO_PORT_DIR7_DIRP3_Msk (0x01UL << GPIO_PORT_DIR7_DIRP3_Pos) /*!< GPIO_PORT DIR7: DIRP3 Mask */ -#define GPIO_PORT_DIR7_DIRP4_Pos 4 /*!< GPIO_PORT DIR7: DIRP4 Position */ -#define GPIO_PORT_DIR7_DIRP4_Msk (0x01UL << GPIO_PORT_DIR7_DIRP4_Pos) /*!< GPIO_PORT DIR7: DIRP4 Mask */ -#define GPIO_PORT_DIR7_DIRP5_Pos 5 /*!< GPIO_PORT DIR7: DIRP5 Position */ -#define GPIO_PORT_DIR7_DIRP5_Msk (0x01UL << GPIO_PORT_DIR7_DIRP5_Pos) /*!< GPIO_PORT DIR7: DIRP5 Mask */ -#define GPIO_PORT_DIR7_DIRP6_Pos 6 /*!< GPIO_PORT DIR7: DIRP6 Position */ -#define GPIO_PORT_DIR7_DIRP6_Msk (0x01UL << GPIO_PORT_DIR7_DIRP6_Pos) /*!< GPIO_PORT DIR7: DIRP6 Mask */ -#define GPIO_PORT_DIR7_DIRP7_Pos 7 /*!< GPIO_PORT DIR7: DIRP7 Position */ -#define GPIO_PORT_DIR7_DIRP7_Msk (0x01UL << GPIO_PORT_DIR7_DIRP7_Pos) /*!< GPIO_PORT DIR7: DIRP7 Mask */ -#define GPIO_PORT_DIR7_DIRP8_Pos 8 /*!< GPIO_PORT DIR7: DIRP8 Position */ -#define GPIO_PORT_DIR7_DIRP8_Msk (0x01UL << GPIO_PORT_DIR7_DIRP8_Pos) /*!< GPIO_PORT DIR7: DIRP8 Mask */ -#define GPIO_PORT_DIR7_DIRP9_Pos 9 /*!< GPIO_PORT DIR7: DIRP9 Position */ -#define GPIO_PORT_DIR7_DIRP9_Msk (0x01UL << GPIO_PORT_DIR7_DIRP9_Pos) /*!< GPIO_PORT DIR7: DIRP9 Mask */ -#define GPIO_PORT_DIR7_DIRP10_Pos 10 /*!< GPIO_PORT DIR7: DIRP10 Position */ -#define GPIO_PORT_DIR7_DIRP10_Msk (0x01UL << GPIO_PORT_DIR7_DIRP10_Pos) /*!< GPIO_PORT DIR7: DIRP10 Mask */ -#define GPIO_PORT_DIR7_DIRP11_Pos 11 /*!< GPIO_PORT DIR7: DIRP11 Position */ -#define GPIO_PORT_DIR7_DIRP11_Msk (0x01UL << GPIO_PORT_DIR7_DIRP11_Pos) /*!< GPIO_PORT DIR7: DIRP11 Mask */ -#define GPIO_PORT_DIR7_DIRP12_Pos 12 /*!< GPIO_PORT DIR7: DIRP12 Position */ -#define GPIO_PORT_DIR7_DIRP12_Msk (0x01UL << GPIO_PORT_DIR7_DIRP12_Pos) /*!< GPIO_PORT DIR7: DIRP12 Mask */ -#define GPIO_PORT_DIR7_DIRP13_Pos 13 /*!< GPIO_PORT DIR7: DIRP13 Position */ -#define GPIO_PORT_DIR7_DIRP13_Msk (0x01UL << GPIO_PORT_DIR7_DIRP13_Pos) /*!< GPIO_PORT DIR7: DIRP13 Mask */ -#define GPIO_PORT_DIR7_DIRP14_Pos 14 /*!< GPIO_PORT DIR7: DIRP14 Position */ -#define GPIO_PORT_DIR7_DIRP14_Msk (0x01UL << GPIO_PORT_DIR7_DIRP14_Pos) /*!< GPIO_PORT DIR7: DIRP14 Mask */ -#define GPIO_PORT_DIR7_DIRP15_Pos 15 /*!< GPIO_PORT DIR7: DIRP15 Position */ -#define GPIO_PORT_DIR7_DIRP15_Msk (0x01UL << GPIO_PORT_DIR7_DIRP15_Pos) /*!< GPIO_PORT DIR7: DIRP15 Mask */ -#define GPIO_PORT_DIR7_DIRP16_Pos 16 /*!< GPIO_PORT DIR7: DIRP16 Position */ -#define GPIO_PORT_DIR7_DIRP16_Msk (0x01UL << GPIO_PORT_DIR7_DIRP16_Pos) /*!< GPIO_PORT DIR7: DIRP16 Mask */ -#define GPIO_PORT_DIR7_DIRP17_Pos 17 /*!< GPIO_PORT DIR7: DIRP17 Position */ -#define GPIO_PORT_DIR7_DIRP17_Msk (0x01UL << GPIO_PORT_DIR7_DIRP17_Pos) /*!< GPIO_PORT DIR7: DIRP17 Mask */ -#define GPIO_PORT_DIR7_DIRP18_Pos 18 /*!< GPIO_PORT DIR7: DIRP18 Position */ -#define GPIO_PORT_DIR7_DIRP18_Msk (0x01UL << GPIO_PORT_DIR7_DIRP18_Pos) /*!< GPIO_PORT DIR7: DIRP18 Mask */ -#define GPIO_PORT_DIR7_DIRP19_Pos 19 /*!< GPIO_PORT DIR7: DIRP19 Position */ -#define GPIO_PORT_DIR7_DIRP19_Msk (0x01UL << GPIO_PORT_DIR7_DIRP19_Pos) /*!< GPIO_PORT DIR7: DIRP19 Mask */ -#define GPIO_PORT_DIR7_DIRP20_Pos 20 /*!< GPIO_PORT DIR7: DIRP20 Position */ -#define GPIO_PORT_DIR7_DIRP20_Msk (0x01UL << GPIO_PORT_DIR7_DIRP20_Pos) /*!< GPIO_PORT DIR7: DIRP20 Mask */ -#define GPIO_PORT_DIR7_DIRP21_Pos 21 /*!< GPIO_PORT DIR7: DIRP21 Position */ -#define GPIO_PORT_DIR7_DIRP21_Msk (0x01UL << GPIO_PORT_DIR7_DIRP21_Pos) /*!< GPIO_PORT DIR7: DIRP21 Mask */ -#define GPIO_PORT_DIR7_DIRP22_Pos 22 /*!< GPIO_PORT DIR7: DIRP22 Position */ -#define GPIO_PORT_DIR7_DIRP22_Msk (0x01UL << GPIO_PORT_DIR7_DIRP22_Pos) /*!< GPIO_PORT DIR7: DIRP22 Mask */ -#define GPIO_PORT_DIR7_DIRP23_Pos 23 /*!< GPIO_PORT DIR7: DIRP23 Position */ -#define GPIO_PORT_DIR7_DIRP23_Msk (0x01UL << GPIO_PORT_DIR7_DIRP23_Pos) /*!< GPIO_PORT DIR7: DIRP23 Mask */ -#define GPIO_PORT_DIR7_DIRP24_Pos 24 /*!< GPIO_PORT DIR7: DIRP24 Position */ -#define GPIO_PORT_DIR7_DIRP24_Msk (0x01UL << GPIO_PORT_DIR7_DIRP24_Pos) /*!< GPIO_PORT DIR7: DIRP24 Mask */ -#define GPIO_PORT_DIR7_DIRP25_Pos 25 /*!< GPIO_PORT DIR7: DIRP25 Position */ -#define GPIO_PORT_DIR7_DIRP25_Msk (0x01UL << GPIO_PORT_DIR7_DIRP25_Pos) /*!< GPIO_PORT DIR7: DIRP25 Mask */ -#define GPIO_PORT_DIR7_DIRP26_Pos 26 /*!< GPIO_PORT DIR7: DIRP26 Position */ -#define GPIO_PORT_DIR7_DIRP26_Msk (0x01UL << GPIO_PORT_DIR7_DIRP26_Pos) /*!< GPIO_PORT DIR7: DIRP26 Mask */ -#define GPIO_PORT_DIR7_DIRP27_Pos 27 /*!< GPIO_PORT DIR7: DIRP27 Position */ -#define GPIO_PORT_DIR7_DIRP27_Msk (0x01UL << GPIO_PORT_DIR7_DIRP27_Pos) /*!< GPIO_PORT DIR7: DIRP27 Mask */ -#define GPIO_PORT_DIR7_DIRP28_Pos 28 /*!< GPIO_PORT DIR7: DIRP28 Position */ -#define GPIO_PORT_DIR7_DIRP28_Msk (0x01UL << GPIO_PORT_DIR7_DIRP28_Pos) /*!< GPIO_PORT DIR7: DIRP28 Mask */ -#define GPIO_PORT_DIR7_DIRP29_Pos 29 /*!< GPIO_PORT DIR7: DIRP29 Position */ -#define GPIO_PORT_DIR7_DIRP29_Msk (0x01UL << GPIO_PORT_DIR7_DIRP29_Pos) /*!< GPIO_PORT DIR7: DIRP29 Mask */ -#define GPIO_PORT_DIR7_DIRP30_Pos 30 /*!< GPIO_PORT DIR7: DIRP30 Position */ -#define GPIO_PORT_DIR7_DIRP30_Msk (0x01UL << GPIO_PORT_DIR7_DIRP30_Pos) /*!< GPIO_PORT DIR7: DIRP30 Mask */ -#define GPIO_PORT_DIR7_DIRP31_Pos 31 /*!< GPIO_PORT DIR7: DIRP31 Position */ -#define GPIO_PORT_DIR7_DIRP31_Msk (0x01UL << GPIO_PORT_DIR7_DIRP31_Pos) /*!< GPIO_PORT DIR7: DIRP31 Mask */ - -// ------------------------------------- GPIO_PORT_MASK0 ---------------------------------------- -#define GPIO_PORT_MASK0_MASKP0_Pos 0 /*!< GPIO_PORT MASK0: MASKP0 Position */ -#define GPIO_PORT_MASK0_MASKP0_Msk (0x01UL << GPIO_PORT_MASK0_MASKP0_Pos) /*!< GPIO_PORT MASK0: MASKP0 Mask */ -#define GPIO_PORT_MASK0_MASKP1_Pos 1 /*!< GPIO_PORT MASK0: MASKP1 Position */ -#define GPIO_PORT_MASK0_MASKP1_Msk (0x01UL << GPIO_PORT_MASK0_MASKP1_Pos) /*!< GPIO_PORT MASK0: MASKP1 Mask */ -#define GPIO_PORT_MASK0_MASKP2_Pos 2 /*!< GPIO_PORT MASK0: MASKP2 Position */ -#define GPIO_PORT_MASK0_MASKP2_Msk (0x01UL << GPIO_PORT_MASK0_MASKP2_Pos) /*!< GPIO_PORT MASK0: MASKP2 Mask */ -#define GPIO_PORT_MASK0_MASKP3_Pos 3 /*!< GPIO_PORT MASK0: MASKP3 Position */ -#define GPIO_PORT_MASK0_MASKP3_Msk (0x01UL << GPIO_PORT_MASK0_MASKP3_Pos) /*!< GPIO_PORT MASK0: MASKP3 Mask */ -#define GPIO_PORT_MASK0_MASKP4_Pos 4 /*!< GPIO_PORT MASK0: MASKP4 Position */ -#define GPIO_PORT_MASK0_MASKP4_Msk (0x01UL << GPIO_PORT_MASK0_MASKP4_Pos) /*!< GPIO_PORT MASK0: MASKP4 Mask */ -#define GPIO_PORT_MASK0_MASKP5_Pos 5 /*!< GPIO_PORT MASK0: MASKP5 Position */ -#define GPIO_PORT_MASK0_MASKP5_Msk (0x01UL << GPIO_PORT_MASK0_MASKP5_Pos) /*!< GPIO_PORT MASK0: MASKP5 Mask */ -#define GPIO_PORT_MASK0_MASKP6_Pos 6 /*!< GPIO_PORT MASK0: MASKP6 Position */ -#define GPIO_PORT_MASK0_MASKP6_Msk (0x01UL << GPIO_PORT_MASK0_MASKP6_Pos) /*!< GPIO_PORT MASK0: MASKP6 Mask */ -#define GPIO_PORT_MASK0_MASKP7_Pos 7 /*!< GPIO_PORT MASK0: MASKP7 Position */ -#define GPIO_PORT_MASK0_MASKP7_Msk (0x01UL << GPIO_PORT_MASK0_MASKP7_Pos) /*!< GPIO_PORT MASK0: MASKP7 Mask */ -#define GPIO_PORT_MASK0_MASKP8_Pos 8 /*!< GPIO_PORT MASK0: MASKP8 Position */ -#define GPIO_PORT_MASK0_MASKP8_Msk (0x01UL << GPIO_PORT_MASK0_MASKP8_Pos) /*!< GPIO_PORT MASK0: MASKP8 Mask */ -#define GPIO_PORT_MASK0_MASKP9_Pos 9 /*!< GPIO_PORT MASK0: MASKP9 Position */ -#define GPIO_PORT_MASK0_MASKP9_Msk (0x01UL << GPIO_PORT_MASK0_MASKP9_Pos) /*!< GPIO_PORT MASK0: MASKP9 Mask */ -#define GPIO_PORT_MASK0_MASKP10_Pos 10 /*!< GPIO_PORT MASK0: MASKP10 Position */ -#define GPIO_PORT_MASK0_MASKP10_Msk (0x01UL << GPIO_PORT_MASK0_MASKP10_Pos) /*!< GPIO_PORT MASK0: MASKP10 Mask */ -#define GPIO_PORT_MASK0_MASKP11_Pos 11 /*!< GPIO_PORT MASK0: MASKP11 Position */ -#define GPIO_PORT_MASK0_MASKP11_Msk (0x01UL << GPIO_PORT_MASK0_MASKP11_Pos) /*!< GPIO_PORT MASK0: MASKP11 Mask */ -#define GPIO_PORT_MASK0_MASKP12_Pos 12 /*!< GPIO_PORT MASK0: MASKP12 Position */ -#define GPIO_PORT_MASK0_MASKP12_Msk (0x01UL << GPIO_PORT_MASK0_MASKP12_Pos) /*!< GPIO_PORT MASK0: MASKP12 Mask */ -#define GPIO_PORT_MASK0_MASKP13_Pos 13 /*!< GPIO_PORT MASK0: MASKP13 Position */ -#define GPIO_PORT_MASK0_MASKP13_Msk (0x01UL << GPIO_PORT_MASK0_MASKP13_Pos) /*!< GPIO_PORT MASK0: MASKP13 Mask */ -#define GPIO_PORT_MASK0_MASKP14_Pos 14 /*!< GPIO_PORT MASK0: MASKP14 Position */ -#define GPIO_PORT_MASK0_MASKP14_Msk (0x01UL << GPIO_PORT_MASK0_MASKP14_Pos) /*!< GPIO_PORT MASK0: MASKP14 Mask */ -#define GPIO_PORT_MASK0_MASKP15_Pos 15 /*!< GPIO_PORT MASK0: MASKP15 Position */ -#define GPIO_PORT_MASK0_MASKP15_Msk (0x01UL << GPIO_PORT_MASK0_MASKP15_Pos) /*!< GPIO_PORT MASK0: MASKP15 Mask */ -#define GPIO_PORT_MASK0_MASKP16_Pos 16 /*!< GPIO_PORT MASK0: MASKP16 Position */ -#define GPIO_PORT_MASK0_MASKP16_Msk (0x01UL << GPIO_PORT_MASK0_MASKP16_Pos) /*!< GPIO_PORT MASK0: MASKP16 Mask */ -#define GPIO_PORT_MASK0_MASKP17_Pos 17 /*!< GPIO_PORT MASK0: MASKP17 Position */ -#define GPIO_PORT_MASK0_MASKP17_Msk (0x01UL << GPIO_PORT_MASK0_MASKP17_Pos) /*!< GPIO_PORT MASK0: MASKP17 Mask */ -#define GPIO_PORT_MASK0_MASKP18_Pos 18 /*!< GPIO_PORT MASK0: MASKP18 Position */ -#define GPIO_PORT_MASK0_MASKP18_Msk (0x01UL << GPIO_PORT_MASK0_MASKP18_Pos) /*!< GPIO_PORT MASK0: MASKP18 Mask */ -#define GPIO_PORT_MASK0_MASKP19_Pos 19 /*!< GPIO_PORT MASK0: MASKP19 Position */ -#define GPIO_PORT_MASK0_MASKP19_Msk (0x01UL << GPIO_PORT_MASK0_MASKP19_Pos) /*!< GPIO_PORT MASK0: MASKP19 Mask */ -#define GPIO_PORT_MASK0_MASKP20_Pos 20 /*!< GPIO_PORT MASK0: MASKP20 Position */ -#define GPIO_PORT_MASK0_MASKP20_Msk (0x01UL << GPIO_PORT_MASK0_MASKP20_Pos) /*!< GPIO_PORT MASK0: MASKP20 Mask */ -#define GPIO_PORT_MASK0_MASKP21_Pos 21 /*!< GPIO_PORT MASK0: MASKP21 Position */ -#define GPIO_PORT_MASK0_MASKP21_Msk (0x01UL << GPIO_PORT_MASK0_MASKP21_Pos) /*!< GPIO_PORT MASK0: MASKP21 Mask */ -#define GPIO_PORT_MASK0_MASKP22_Pos 22 /*!< GPIO_PORT MASK0: MASKP22 Position */ -#define GPIO_PORT_MASK0_MASKP22_Msk (0x01UL << GPIO_PORT_MASK0_MASKP22_Pos) /*!< GPIO_PORT MASK0: MASKP22 Mask */ -#define GPIO_PORT_MASK0_MASKP23_Pos 23 /*!< GPIO_PORT MASK0: MASKP23 Position */ -#define GPIO_PORT_MASK0_MASKP23_Msk (0x01UL << GPIO_PORT_MASK0_MASKP23_Pos) /*!< GPIO_PORT MASK0: MASKP23 Mask */ -#define GPIO_PORT_MASK0_MASKP24_Pos 24 /*!< GPIO_PORT MASK0: MASKP24 Position */ -#define GPIO_PORT_MASK0_MASKP24_Msk (0x01UL << GPIO_PORT_MASK0_MASKP24_Pos) /*!< GPIO_PORT MASK0: MASKP24 Mask */ -#define GPIO_PORT_MASK0_MASKP25_Pos 25 /*!< GPIO_PORT MASK0: MASKP25 Position */ -#define GPIO_PORT_MASK0_MASKP25_Msk (0x01UL << GPIO_PORT_MASK0_MASKP25_Pos) /*!< GPIO_PORT MASK0: MASKP25 Mask */ -#define GPIO_PORT_MASK0_MASKP26_Pos 26 /*!< GPIO_PORT MASK0: MASKP26 Position */ -#define GPIO_PORT_MASK0_MASKP26_Msk (0x01UL << GPIO_PORT_MASK0_MASKP26_Pos) /*!< GPIO_PORT MASK0: MASKP26 Mask */ -#define GPIO_PORT_MASK0_MASKP27_Pos 27 /*!< GPIO_PORT MASK0: MASKP27 Position */ -#define GPIO_PORT_MASK0_MASKP27_Msk (0x01UL << GPIO_PORT_MASK0_MASKP27_Pos) /*!< GPIO_PORT MASK0: MASKP27 Mask */ -#define GPIO_PORT_MASK0_MASKP28_Pos 28 /*!< GPIO_PORT MASK0: MASKP28 Position */ -#define GPIO_PORT_MASK0_MASKP28_Msk (0x01UL << GPIO_PORT_MASK0_MASKP28_Pos) /*!< GPIO_PORT MASK0: MASKP28 Mask */ -#define GPIO_PORT_MASK0_MASKP29_Pos 29 /*!< GPIO_PORT MASK0: MASKP29 Position */ -#define GPIO_PORT_MASK0_MASKP29_Msk (0x01UL << GPIO_PORT_MASK0_MASKP29_Pos) /*!< GPIO_PORT MASK0: MASKP29 Mask */ -#define GPIO_PORT_MASK0_MASKP30_Pos 30 /*!< GPIO_PORT MASK0: MASKP30 Position */ -#define GPIO_PORT_MASK0_MASKP30_Msk (0x01UL << GPIO_PORT_MASK0_MASKP30_Pos) /*!< GPIO_PORT MASK0: MASKP30 Mask */ -#define GPIO_PORT_MASK0_MASKP31_Pos 31 /*!< GPIO_PORT MASK0: MASKP31 Position */ -#define GPIO_PORT_MASK0_MASKP31_Msk (0x01UL << GPIO_PORT_MASK0_MASKP31_Pos) /*!< GPIO_PORT MASK0: MASKP31 Mask */ - -// ------------------------------------- GPIO_PORT_MASK1 ---------------------------------------- -#define GPIO_PORT_MASK1_MASKP0_Pos 0 /*!< GPIO_PORT MASK1: MASKP0 Position */ -#define GPIO_PORT_MASK1_MASKP0_Msk (0x01UL << GPIO_PORT_MASK1_MASKP0_Pos) /*!< GPIO_PORT MASK1: MASKP0 Mask */ -#define GPIO_PORT_MASK1_MASKP1_Pos 1 /*!< GPIO_PORT MASK1: MASKP1 Position */ -#define GPIO_PORT_MASK1_MASKP1_Msk (0x01UL << GPIO_PORT_MASK1_MASKP1_Pos) /*!< GPIO_PORT MASK1: MASKP1 Mask */ -#define GPIO_PORT_MASK1_MASKP2_Pos 2 /*!< GPIO_PORT MASK1: MASKP2 Position */ -#define GPIO_PORT_MASK1_MASKP2_Msk (0x01UL << GPIO_PORT_MASK1_MASKP2_Pos) /*!< GPIO_PORT MASK1: MASKP2 Mask */ -#define GPIO_PORT_MASK1_MASKP3_Pos 3 /*!< GPIO_PORT MASK1: MASKP3 Position */ -#define GPIO_PORT_MASK1_MASKP3_Msk (0x01UL << GPIO_PORT_MASK1_MASKP3_Pos) /*!< GPIO_PORT MASK1: MASKP3 Mask */ -#define GPIO_PORT_MASK1_MASKP4_Pos 4 /*!< GPIO_PORT MASK1: MASKP4 Position */ -#define GPIO_PORT_MASK1_MASKP4_Msk (0x01UL << GPIO_PORT_MASK1_MASKP4_Pos) /*!< GPIO_PORT MASK1: MASKP4 Mask */ -#define GPIO_PORT_MASK1_MASKP5_Pos 5 /*!< GPIO_PORT MASK1: MASKP5 Position */ -#define GPIO_PORT_MASK1_MASKP5_Msk (0x01UL << GPIO_PORT_MASK1_MASKP5_Pos) /*!< GPIO_PORT MASK1: MASKP5 Mask */ -#define GPIO_PORT_MASK1_MASKP6_Pos 6 /*!< GPIO_PORT MASK1: MASKP6 Position */ -#define GPIO_PORT_MASK1_MASKP6_Msk (0x01UL << GPIO_PORT_MASK1_MASKP6_Pos) /*!< GPIO_PORT MASK1: MASKP6 Mask */ -#define GPIO_PORT_MASK1_MASKP7_Pos 7 /*!< GPIO_PORT MASK1: MASKP7 Position */ -#define GPIO_PORT_MASK1_MASKP7_Msk (0x01UL << GPIO_PORT_MASK1_MASKP7_Pos) /*!< GPIO_PORT MASK1: MASKP7 Mask */ -#define GPIO_PORT_MASK1_MASKP8_Pos 8 /*!< GPIO_PORT MASK1: MASKP8 Position */ -#define GPIO_PORT_MASK1_MASKP8_Msk (0x01UL << GPIO_PORT_MASK1_MASKP8_Pos) /*!< GPIO_PORT MASK1: MASKP8 Mask */ -#define GPIO_PORT_MASK1_MASKP9_Pos 9 /*!< GPIO_PORT MASK1: MASKP9 Position */ -#define GPIO_PORT_MASK1_MASKP9_Msk (0x01UL << GPIO_PORT_MASK1_MASKP9_Pos) /*!< GPIO_PORT MASK1: MASKP9 Mask */ -#define GPIO_PORT_MASK1_MASKP10_Pos 10 /*!< GPIO_PORT MASK1: MASKP10 Position */ -#define GPIO_PORT_MASK1_MASKP10_Msk (0x01UL << GPIO_PORT_MASK1_MASKP10_Pos) /*!< GPIO_PORT MASK1: MASKP10 Mask */ -#define GPIO_PORT_MASK1_MASKP11_Pos 11 /*!< GPIO_PORT MASK1: MASKP11 Position */ -#define GPIO_PORT_MASK1_MASKP11_Msk (0x01UL << GPIO_PORT_MASK1_MASKP11_Pos) /*!< GPIO_PORT MASK1: MASKP11 Mask */ -#define GPIO_PORT_MASK1_MASKP12_Pos 12 /*!< GPIO_PORT MASK1: MASKP12 Position */ -#define GPIO_PORT_MASK1_MASKP12_Msk (0x01UL << GPIO_PORT_MASK1_MASKP12_Pos) /*!< GPIO_PORT MASK1: MASKP12 Mask */ -#define GPIO_PORT_MASK1_MASKP13_Pos 13 /*!< GPIO_PORT MASK1: MASKP13 Position */ -#define GPIO_PORT_MASK1_MASKP13_Msk (0x01UL << GPIO_PORT_MASK1_MASKP13_Pos) /*!< GPIO_PORT MASK1: MASKP13 Mask */ -#define GPIO_PORT_MASK1_MASKP14_Pos 14 /*!< GPIO_PORT MASK1: MASKP14 Position */ -#define GPIO_PORT_MASK1_MASKP14_Msk (0x01UL << GPIO_PORT_MASK1_MASKP14_Pos) /*!< GPIO_PORT MASK1: MASKP14 Mask */ -#define GPIO_PORT_MASK1_MASKP15_Pos 15 /*!< GPIO_PORT MASK1: MASKP15 Position */ -#define GPIO_PORT_MASK1_MASKP15_Msk (0x01UL << GPIO_PORT_MASK1_MASKP15_Pos) /*!< GPIO_PORT MASK1: MASKP15 Mask */ -#define GPIO_PORT_MASK1_MASKP16_Pos 16 /*!< GPIO_PORT MASK1: MASKP16 Position */ -#define GPIO_PORT_MASK1_MASKP16_Msk (0x01UL << GPIO_PORT_MASK1_MASKP16_Pos) /*!< GPIO_PORT MASK1: MASKP16 Mask */ -#define GPIO_PORT_MASK1_MASKP17_Pos 17 /*!< GPIO_PORT MASK1: MASKP17 Position */ -#define GPIO_PORT_MASK1_MASKP17_Msk (0x01UL << GPIO_PORT_MASK1_MASKP17_Pos) /*!< GPIO_PORT MASK1: MASKP17 Mask */ -#define GPIO_PORT_MASK1_MASKP18_Pos 18 /*!< GPIO_PORT MASK1: MASKP18 Position */ -#define GPIO_PORT_MASK1_MASKP18_Msk (0x01UL << GPIO_PORT_MASK1_MASKP18_Pos) /*!< GPIO_PORT MASK1: MASKP18 Mask */ -#define GPIO_PORT_MASK1_MASKP19_Pos 19 /*!< GPIO_PORT MASK1: MASKP19 Position */ -#define GPIO_PORT_MASK1_MASKP19_Msk (0x01UL << GPIO_PORT_MASK1_MASKP19_Pos) /*!< GPIO_PORT MASK1: MASKP19 Mask */ -#define GPIO_PORT_MASK1_MASKP20_Pos 20 /*!< GPIO_PORT MASK1: MASKP20 Position */ -#define GPIO_PORT_MASK1_MASKP20_Msk (0x01UL << GPIO_PORT_MASK1_MASKP20_Pos) /*!< GPIO_PORT MASK1: MASKP20 Mask */ -#define GPIO_PORT_MASK1_MASKP21_Pos 21 /*!< GPIO_PORT MASK1: MASKP21 Position */ -#define GPIO_PORT_MASK1_MASKP21_Msk (0x01UL << GPIO_PORT_MASK1_MASKP21_Pos) /*!< GPIO_PORT MASK1: MASKP21 Mask */ -#define GPIO_PORT_MASK1_MASKP22_Pos 22 /*!< GPIO_PORT MASK1: MASKP22 Position */ -#define GPIO_PORT_MASK1_MASKP22_Msk (0x01UL << GPIO_PORT_MASK1_MASKP22_Pos) /*!< GPIO_PORT MASK1: MASKP22 Mask */ -#define GPIO_PORT_MASK1_MASKP23_Pos 23 /*!< GPIO_PORT MASK1: MASKP23 Position */ -#define GPIO_PORT_MASK1_MASKP23_Msk (0x01UL << GPIO_PORT_MASK1_MASKP23_Pos) /*!< GPIO_PORT MASK1: MASKP23 Mask */ -#define GPIO_PORT_MASK1_MASKP24_Pos 24 /*!< GPIO_PORT MASK1: MASKP24 Position */ -#define GPIO_PORT_MASK1_MASKP24_Msk (0x01UL << GPIO_PORT_MASK1_MASKP24_Pos) /*!< GPIO_PORT MASK1: MASKP24 Mask */ -#define GPIO_PORT_MASK1_MASKP25_Pos 25 /*!< GPIO_PORT MASK1: MASKP25 Position */ -#define GPIO_PORT_MASK1_MASKP25_Msk (0x01UL << GPIO_PORT_MASK1_MASKP25_Pos) /*!< GPIO_PORT MASK1: MASKP25 Mask */ -#define GPIO_PORT_MASK1_MASKP26_Pos 26 /*!< GPIO_PORT MASK1: MASKP26 Position */ -#define GPIO_PORT_MASK1_MASKP26_Msk (0x01UL << GPIO_PORT_MASK1_MASKP26_Pos) /*!< GPIO_PORT MASK1: MASKP26 Mask */ -#define GPIO_PORT_MASK1_MASKP27_Pos 27 /*!< GPIO_PORT MASK1: MASKP27 Position */ -#define GPIO_PORT_MASK1_MASKP27_Msk (0x01UL << GPIO_PORT_MASK1_MASKP27_Pos) /*!< GPIO_PORT MASK1: MASKP27 Mask */ -#define GPIO_PORT_MASK1_MASKP28_Pos 28 /*!< GPIO_PORT MASK1: MASKP28 Position */ -#define GPIO_PORT_MASK1_MASKP28_Msk (0x01UL << GPIO_PORT_MASK1_MASKP28_Pos) /*!< GPIO_PORT MASK1: MASKP28 Mask */ -#define GPIO_PORT_MASK1_MASKP29_Pos 29 /*!< GPIO_PORT MASK1: MASKP29 Position */ -#define GPIO_PORT_MASK1_MASKP29_Msk (0x01UL << GPIO_PORT_MASK1_MASKP29_Pos) /*!< GPIO_PORT MASK1: MASKP29 Mask */ -#define GPIO_PORT_MASK1_MASKP30_Pos 30 /*!< GPIO_PORT MASK1: MASKP30 Position */ -#define GPIO_PORT_MASK1_MASKP30_Msk (0x01UL << GPIO_PORT_MASK1_MASKP30_Pos) /*!< GPIO_PORT MASK1: MASKP30 Mask */ -#define GPIO_PORT_MASK1_MASKP31_Pos 31 /*!< GPIO_PORT MASK1: MASKP31 Position */ -#define GPIO_PORT_MASK1_MASKP31_Msk (0x01UL << GPIO_PORT_MASK1_MASKP31_Pos) /*!< GPIO_PORT MASK1: MASKP31 Mask */ - -// ------------------------------------- GPIO_PORT_MASK2 ---------------------------------------- -#define GPIO_PORT_MASK2_MASKP0_Pos 0 /*!< GPIO_PORT MASK2: MASKP0 Position */ -#define GPIO_PORT_MASK2_MASKP0_Msk (0x01UL << GPIO_PORT_MASK2_MASKP0_Pos) /*!< GPIO_PORT MASK2: MASKP0 Mask */ -#define GPIO_PORT_MASK2_MASKP1_Pos 1 /*!< GPIO_PORT MASK2: MASKP1 Position */ -#define GPIO_PORT_MASK2_MASKP1_Msk (0x01UL << GPIO_PORT_MASK2_MASKP1_Pos) /*!< GPIO_PORT MASK2: MASKP1 Mask */ -#define GPIO_PORT_MASK2_MASKP2_Pos 2 /*!< GPIO_PORT MASK2: MASKP2 Position */ -#define GPIO_PORT_MASK2_MASKP2_Msk (0x01UL << GPIO_PORT_MASK2_MASKP2_Pos) /*!< GPIO_PORT MASK2: MASKP2 Mask */ -#define GPIO_PORT_MASK2_MASKP3_Pos 3 /*!< GPIO_PORT MASK2: MASKP3 Position */ -#define GPIO_PORT_MASK2_MASKP3_Msk (0x01UL << GPIO_PORT_MASK2_MASKP3_Pos) /*!< GPIO_PORT MASK2: MASKP3 Mask */ -#define GPIO_PORT_MASK2_MASKP4_Pos 4 /*!< GPIO_PORT MASK2: MASKP4 Position */ -#define GPIO_PORT_MASK2_MASKP4_Msk (0x01UL << GPIO_PORT_MASK2_MASKP4_Pos) /*!< GPIO_PORT MASK2: MASKP4 Mask */ -#define GPIO_PORT_MASK2_MASKP5_Pos 5 /*!< GPIO_PORT MASK2: MASKP5 Position */ -#define GPIO_PORT_MASK2_MASKP5_Msk (0x01UL << GPIO_PORT_MASK2_MASKP5_Pos) /*!< GPIO_PORT MASK2: MASKP5 Mask */ -#define GPIO_PORT_MASK2_MASKP6_Pos 6 /*!< GPIO_PORT MASK2: MASKP6 Position */ -#define GPIO_PORT_MASK2_MASKP6_Msk (0x01UL << GPIO_PORT_MASK2_MASKP6_Pos) /*!< GPIO_PORT MASK2: MASKP6 Mask */ -#define GPIO_PORT_MASK2_MASKP7_Pos 7 /*!< GPIO_PORT MASK2: MASKP7 Position */ -#define GPIO_PORT_MASK2_MASKP7_Msk (0x01UL << GPIO_PORT_MASK2_MASKP7_Pos) /*!< GPIO_PORT MASK2: MASKP7 Mask */ -#define GPIO_PORT_MASK2_MASKP8_Pos 8 /*!< GPIO_PORT MASK2: MASKP8 Position */ -#define GPIO_PORT_MASK2_MASKP8_Msk (0x01UL << GPIO_PORT_MASK2_MASKP8_Pos) /*!< GPIO_PORT MASK2: MASKP8 Mask */ -#define GPIO_PORT_MASK2_MASKP9_Pos 9 /*!< GPIO_PORT MASK2: MASKP9 Position */ -#define GPIO_PORT_MASK2_MASKP9_Msk (0x01UL << GPIO_PORT_MASK2_MASKP9_Pos) /*!< GPIO_PORT MASK2: MASKP9 Mask */ -#define GPIO_PORT_MASK2_MASKP10_Pos 10 /*!< GPIO_PORT MASK2: MASKP10 Position */ -#define GPIO_PORT_MASK2_MASKP10_Msk (0x01UL << GPIO_PORT_MASK2_MASKP10_Pos) /*!< GPIO_PORT MASK2: MASKP10 Mask */ -#define GPIO_PORT_MASK2_MASKP11_Pos 11 /*!< GPIO_PORT MASK2: MASKP11 Position */ -#define GPIO_PORT_MASK2_MASKP11_Msk (0x01UL << GPIO_PORT_MASK2_MASKP11_Pos) /*!< GPIO_PORT MASK2: MASKP11 Mask */ -#define GPIO_PORT_MASK2_MASKP12_Pos 12 /*!< GPIO_PORT MASK2: MASKP12 Position */ -#define GPIO_PORT_MASK2_MASKP12_Msk (0x01UL << GPIO_PORT_MASK2_MASKP12_Pos) /*!< GPIO_PORT MASK2: MASKP12 Mask */ -#define GPIO_PORT_MASK2_MASKP13_Pos 13 /*!< GPIO_PORT MASK2: MASKP13 Position */ -#define GPIO_PORT_MASK2_MASKP13_Msk (0x01UL << GPIO_PORT_MASK2_MASKP13_Pos) /*!< GPIO_PORT MASK2: MASKP13 Mask */ -#define GPIO_PORT_MASK2_MASKP14_Pos 14 /*!< GPIO_PORT MASK2: MASKP14 Position */ -#define GPIO_PORT_MASK2_MASKP14_Msk (0x01UL << GPIO_PORT_MASK2_MASKP14_Pos) /*!< GPIO_PORT MASK2: MASKP14 Mask */ -#define GPIO_PORT_MASK2_MASKP15_Pos 15 /*!< GPIO_PORT MASK2: MASKP15 Position */ -#define GPIO_PORT_MASK2_MASKP15_Msk (0x01UL << GPIO_PORT_MASK2_MASKP15_Pos) /*!< GPIO_PORT MASK2: MASKP15 Mask */ -#define GPIO_PORT_MASK2_MASKP16_Pos 16 /*!< GPIO_PORT MASK2: MASKP16 Position */ -#define GPIO_PORT_MASK2_MASKP16_Msk (0x01UL << GPIO_PORT_MASK2_MASKP16_Pos) /*!< GPIO_PORT MASK2: MASKP16 Mask */ -#define GPIO_PORT_MASK2_MASKP17_Pos 17 /*!< GPIO_PORT MASK2: MASKP17 Position */ -#define GPIO_PORT_MASK2_MASKP17_Msk (0x01UL << GPIO_PORT_MASK2_MASKP17_Pos) /*!< GPIO_PORT MASK2: MASKP17 Mask */ -#define GPIO_PORT_MASK2_MASKP18_Pos 18 /*!< GPIO_PORT MASK2: MASKP18 Position */ -#define GPIO_PORT_MASK2_MASKP18_Msk (0x01UL << GPIO_PORT_MASK2_MASKP18_Pos) /*!< GPIO_PORT MASK2: MASKP18 Mask */ -#define GPIO_PORT_MASK2_MASKP19_Pos 19 /*!< GPIO_PORT MASK2: MASKP19 Position */ -#define GPIO_PORT_MASK2_MASKP19_Msk (0x01UL << GPIO_PORT_MASK2_MASKP19_Pos) /*!< GPIO_PORT MASK2: MASKP19 Mask */ -#define GPIO_PORT_MASK2_MASKP20_Pos 20 /*!< GPIO_PORT MASK2: MASKP20 Position */ -#define GPIO_PORT_MASK2_MASKP20_Msk (0x01UL << GPIO_PORT_MASK2_MASKP20_Pos) /*!< GPIO_PORT MASK2: MASKP20 Mask */ -#define GPIO_PORT_MASK2_MASKP21_Pos 21 /*!< GPIO_PORT MASK2: MASKP21 Position */ -#define GPIO_PORT_MASK2_MASKP21_Msk (0x01UL << GPIO_PORT_MASK2_MASKP21_Pos) /*!< GPIO_PORT MASK2: MASKP21 Mask */ -#define GPIO_PORT_MASK2_MASKP22_Pos 22 /*!< GPIO_PORT MASK2: MASKP22 Position */ -#define GPIO_PORT_MASK2_MASKP22_Msk (0x01UL << GPIO_PORT_MASK2_MASKP22_Pos) /*!< GPIO_PORT MASK2: MASKP22 Mask */ -#define GPIO_PORT_MASK2_MASKP23_Pos 23 /*!< GPIO_PORT MASK2: MASKP23 Position */ -#define GPIO_PORT_MASK2_MASKP23_Msk (0x01UL << GPIO_PORT_MASK2_MASKP23_Pos) /*!< GPIO_PORT MASK2: MASKP23 Mask */ -#define GPIO_PORT_MASK2_MASKP24_Pos 24 /*!< GPIO_PORT MASK2: MASKP24 Position */ -#define GPIO_PORT_MASK2_MASKP24_Msk (0x01UL << GPIO_PORT_MASK2_MASKP24_Pos) /*!< GPIO_PORT MASK2: MASKP24 Mask */ -#define GPIO_PORT_MASK2_MASKP25_Pos 25 /*!< GPIO_PORT MASK2: MASKP25 Position */ -#define GPIO_PORT_MASK2_MASKP25_Msk (0x01UL << GPIO_PORT_MASK2_MASKP25_Pos) /*!< GPIO_PORT MASK2: MASKP25 Mask */ -#define GPIO_PORT_MASK2_MASKP26_Pos 26 /*!< GPIO_PORT MASK2: MASKP26 Position */ -#define GPIO_PORT_MASK2_MASKP26_Msk (0x01UL << GPIO_PORT_MASK2_MASKP26_Pos) /*!< GPIO_PORT MASK2: MASKP26 Mask */ -#define GPIO_PORT_MASK2_MASKP27_Pos 27 /*!< GPIO_PORT MASK2: MASKP27 Position */ -#define GPIO_PORT_MASK2_MASKP27_Msk (0x01UL << GPIO_PORT_MASK2_MASKP27_Pos) /*!< GPIO_PORT MASK2: MASKP27 Mask */ -#define GPIO_PORT_MASK2_MASKP28_Pos 28 /*!< GPIO_PORT MASK2: MASKP28 Position */ -#define GPIO_PORT_MASK2_MASKP28_Msk (0x01UL << GPIO_PORT_MASK2_MASKP28_Pos) /*!< GPIO_PORT MASK2: MASKP28 Mask */ -#define GPIO_PORT_MASK2_MASKP29_Pos 29 /*!< GPIO_PORT MASK2: MASKP29 Position */ -#define GPIO_PORT_MASK2_MASKP29_Msk (0x01UL << GPIO_PORT_MASK2_MASKP29_Pos) /*!< GPIO_PORT MASK2: MASKP29 Mask */ -#define GPIO_PORT_MASK2_MASKP30_Pos 30 /*!< GPIO_PORT MASK2: MASKP30 Position */ -#define GPIO_PORT_MASK2_MASKP30_Msk (0x01UL << GPIO_PORT_MASK2_MASKP30_Pos) /*!< GPIO_PORT MASK2: MASKP30 Mask */ -#define GPIO_PORT_MASK2_MASKP31_Pos 31 /*!< GPIO_PORT MASK2: MASKP31 Position */ -#define GPIO_PORT_MASK2_MASKP31_Msk (0x01UL << GPIO_PORT_MASK2_MASKP31_Pos) /*!< GPIO_PORT MASK2: MASKP31 Mask */ - -// ------------------------------------- GPIO_PORT_MASK3 ---------------------------------------- -#define GPIO_PORT_MASK3_MASKP0_Pos 0 /*!< GPIO_PORT MASK3: MASKP0 Position */ -#define GPIO_PORT_MASK3_MASKP0_Msk (0x01UL << GPIO_PORT_MASK3_MASKP0_Pos) /*!< GPIO_PORT MASK3: MASKP0 Mask */ -#define GPIO_PORT_MASK3_MASKP1_Pos 1 /*!< GPIO_PORT MASK3: MASKP1 Position */ -#define GPIO_PORT_MASK3_MASKP1_Msk (0x01UL << GPIO_PORT_MASK3_MASKP1_Pos) /*!< GPIO_PORT MASK3: MASKP1 Mask */ -#define GPIO_PORT_MASK3_MASKP2_Pos 2 /*!< GPIO_PORT MASK3: MASKP2 Position */ -#define GPIO_PORT_MASK3_MASKP2_Msk (0x01UL << GPIO_PORT_MASK3_MASKP2_Pos) /*!< GPIO_PORT MASK3: MASKP2 Mask */ -#define GPIO_PORT_MASK3_MASKP3_Pos 3 /*!< GPIO_PORT MASK3: MASKP3 Position */ -#define GPIO_PORT_MASK3_MASKP3_Msk (0x01UL << GPIO_PORT_MASK3_MASKP3_Pos) /*!< GPIO_PORT MASK3: MASKP3 Mask */ -#define GPIO_PORT_MASK3_MASKP4_Pos 4 /*!< GPIO_PORT MASK3: MASKP4 Position */ -#define GPIO_PORT_MASK3_MASKP4_Msk (0x01UL << GPIO_PORT_MASK3_MASKP4_Pos) /*!< GPIO_PORT MASK3: MASKP4 Mask */ -#define GPIO_PORT_MASK3_MASKP5_Pos 5 /*!< GPIO_PORT MASK3: MASKP5 Position */ -#define GPIO_PORT_MASK3_MASKP5_Msk (0x01UL << GPIO_PORT_MASK3_MASKP5_Pos) /*!< GPIO_PORT MASK3: MASKP5 Mask */ -#define GPIO_PORT_MASK3_MASKP6_Pos 6 /*!< GPIO_PORT MASK3: MASKP6 Position */ -#define GPIO_PORT_MASK3_MASKP6_Msk (0x01UL << GPIO_PORT_MASK3_MASKP6_Pos) /*!< GPIO_PORT MASK3: MASKP6 Mask */ -#define GPIO_PORT_MASK3_MASKP7_Pos 7 /*!< GPIO_PORT MASK3: MASKP7 Position */ -#define GPIO_PORT_MASK3_MASKP7_Msk (0x01UL << GPIO_PORT_MASK3_MASKP7_Pos) /*!< GPIO_PORT MASK3: MASKP7 Mask */ -#define GPIO_PORT_MASK3_MASKP8_Pos 8 /*!< GPIO_PORT MASK3: MASKP8 Position */ -#define GPIO_PORT_MASK3_MASKP8_Msk (0x01UL << GPIO_PORT_MASK3_MASKP8_Pos) /*!< GPIO_PORT MASK3: MASKP8 Mask */ -#define GPIO_PORT_MASK3_MASKP9_Pos 9 /*!< GPIO_PORT MASK3: MASKP9 Position */ -#define GPIO_PORT_MASK3_MASKP9_Msk (0x01UL << GPIO_PORT_MASK3_MASKP9_Pos) /*!< GPIO_PORT MASK3: MASKP9 Mask */ -#define GPIO_PORT_MASK3_MASKP10_Pos 10 /*!< GPIO_PORT MASK3: MASKP10 Position */ -#define GPIO_PORT_MASK3_MASKP10_Msk (0x01UL << GPIO_PORT_MASK3_MASKP10_Pos) /*!< GPIO_PORT MASK3: MASKP10 Mask */ -#define GPIO_PORT_MASK3_MASKP11_Pos 11 /*!< GPIO_PORT MASK3: MASKP11 Position */ -#define GPIO_PORT_MASK3_MASKP11_Msk (0x01UL << GPIO_PORT_MASK3_MASKP11_Pos) /*!< GPIO_PORT MASK3: MASKP11 Mask */ -#define GPIO_PORT_MASK3_MASKP12_Pos 12 /*!< GPIO_PORT MASK3: MASKP12 Position */ -#define GPIO_PORT_MASK3_MASKP12_Msk (0x01UL << GPIO_PORT_MASK3_MASKP12_Pos) /*!< GPIO_PORT MASK3: MASKP12 Mask */ -#define GPIO_PORT_MASK3_MASKP13_Pos 13 /*!< GPIO_PORT MASK3: MASKP13 Position */ -#define GPIO_PORT_MASK3_MASKP13_Msk (0x01UL << GPIO_PORT_MASK3_MASKP13_Pos) /*!< GPIO_PORT MASK3: MASKP13 Mask */ -#define GPIO_PORT_MASK3_MASKP14_Pos 14 /*!< GPIO_PORT MASK3: MASKP14 Position */ -#define GPIO_PORT_MASK3_MASKP14_Msk (0x01UL << GPIO_PORT_MASK3_MASKP14_Pos) /*!< GPIO_PORT MASK3: MASKP14 Mask */ -#define GPIO_PORT_MASK3_MASKP15_Pos 15 /*!< GPIO_PORT MASK3: MASKP15 Position */ -#define GPIO_PORT_MASK3_MASKP15_Msk (0x01UL << GPIO_PORT_MASK3_MASKP15_Pos) /*!< GPIO_PORT MASK3: MASKP15 Mask */ -#define GPIO_PORT_MASK3_MASKP16_Pos 16 /*!< GPIO_PORT MASK3: MASKP16 Position */ -#define GPIO_PORT_MASK3_MASKP16_Msk (0x01UL << GPIO_PORT_MASK3_MASKP16_Pos) /*!< GPIO_PORT MASK3: MASKP16 Mask */ -#define GPIO_PORT_MASK3_MASKP17_Pos 17 /*!< GPIO_PORT MASK3: MASKP17 Position */ -#define GPIO_PORT_MASK3_MASKP17_Msk (0x01UL << GPIO_PORT_MASK3_MASKP17_Pos) /*!< GPIO_PORT MASK3: MASKP17 Mask */ -#define GPIO_PORT_MASK3_MASKP18_Pos 18 /*!< GPIO_PORT MASK3: MASKP18 Position */ -#define GPIO_PORT_MASK3_MASKP18_Msk (0x01UL << GPIO_PORT_MASK3_MASKP18_Pos) /*!< GPIO_PORT MASK3: MASKP18 Mask */ -#define GPIO_PORT_MASK3_MASKP19_Pos 19 /*!< GPIO_PORT MASK3: MASKP19 Position */ -#define GPIO_PORT_MASK3_MASKP19_Msk (0x01UL << GPIO_PORT_MASK3_MASKP19_Pos) /*!< GPIO_PORT MASK3: MASKP19 Mask */ -#define GPIO_PORT_MASK3_MASKP20_Pos 20 /*!< GPIO_PORT MASK3: MASKP20 Position */ -#define GPIO_PORT_MASK3_MASKP20_Msk (0x01UL << GPIO_PORT_MASK3_MASKP20_Pos) /*!< GPIO_PORT MASK3: MASKP20 Mask */ -#define GPIO_PORT_MASK3_MASKP21_Pos 21 /*!< GPIO_PORT MASK3: MASKP21 Position */ -#define GPIO_PORT_MASK3_MASKP21_Msk (0x01UL << GPIO_PORT_MASK3_MASKP21_Pos) /*!< GPIO_PORT MASK3: MASKP21 Mask */ -#define GPIO_PORT_MASK3_MASKP22_Pos 22 /*!< GPIO_PORT MASK3: MASKP22 Position */ -#define GPIO_PORT_MASK3_MASKP22_Msk (0x01UL << GPIO_PORT_MASK3_MASKP22_Pos) /*!< GPIO_PORT MASK3: MASKP22 Mask */ -#define GPIO_PORT_MASK3_MASKP23_Pos 23 /*!< GPIO_PORT MASK3: MASKP23 Position */ -#define GPIO_PORT_MASK3_MASKP23_Msk (0x01UL << GPIO_PORT_MASK3_MASKP23_Pos) /*!< GPIO_PORT MASK3: MASKP23 Mask */ -#define GPIO_PORT_MASK3_MASKP24_Pos 24 /*!< GPIO_PORT MASK3: MASKP24 Position */ -#define GPIO_PORT_MASK3_MASKP24_Msk (0x01UL << GPIO_PORT_MASK3_MASKP24_Pos) /*!< GPIO_PORT MASK3: MASKP24 Mask */ -#define GPIO_PORT_MASK3_MASKP25_Pos 25 /*!< GPIO_PORT MASK3: MASKP25 Position */ -#define GPIO_PORT_MASK3_MASKP25_Msk (0x01UL << GPIO_PORT_MASK3_MASKP25_Pos) /*!< GPIO_PORT MASK3: MASKP25 Mask */ -#define GPIO_PORT_MASK3_MASKP26_Pos 26 /*!< GPIO_PORT MASK3: MASKP26 Position */ -#define GPIO_PORT_MASK3_MASKP26_Msk (0x01UL << GPIO_PORT_MASK3_MASKP26_Pos) /*!< GPIO_PORT MASK3: MASKP26 Mask */ -#define GPIO_PORT_MASK3_MASKP27_Pos 27 /*!< GPIO_PORT MASK3: MASKP27 Position */ -#define GPIO_PORT_MASK3_MASKP27_Msk (0x01UL << GPIO_PORT_MASK3_MASKP27_Pos) /*!< GPIO_PORT MASK3: MASKP27 Mask */ -#define GPIO_PORT_MASK3_MASKP28_Pos 28 /*!< GPIO_PORT MASK3: MASKP28 Position */ -#define GPIO_PORT_MASK3_MASKP28_Msk (0x01UL << GPIO_PORT_MASK3_MASKP28_Pos) /*!< GPIO_PORT MASK3: MASKP28 Mask */ -#define GPIO_PORT_MASK3_MASKP29_Pos 29 /*!< GPIO_PORT MASK3: MASKP29 Position */ -#define GPIO_PORT_MASK3_MASKP29_Msk (0x01UL << GPIO_PORT_MASK3_MASKP29_Pos) /*!< GPIO_PORT MASK3: MASKP29 Mask */ -#define GPIO_PORT_MASK3_MASKP30_Pos 30 /*!< GPIO_PORT MASK3: MASKP30 Position */ -#define GPIO_PORT_MASK3_MASKP30_Msk (0x01UL << GPIO_PORT_MASK3_MASKP30_Pos) /*!< GPIO_PORT MASK3: MASKP30 Mask */ -#define GPIO_PORT_MASK3_MASKP31_Pos 31 /*!< GPIO_PORT MASK3: MASKP31 Position */ -#define GPIO_PORT_MASK3_MASKP31_Msk (0x01UL << GPIO_PORT_MASK3_MASKP31_Pos) /*!< GPIO_PORT MASK3: MASKP31 Mask */ - -// ------------------------------------- GPIO_PORT_MASK4 ---------------------------------------- -#define GPIO_PORT_MASK4_MASKP0_Pos 0 /*!< GPIO_PORT MASK4: MASKP0 Position */ -#define GPIO_PORT_MASK4_MASKP0_Msk (0x01UL << GPIO_PORT_MASK4_MASKP0_Pos) /*!< GPIO_PORT MASK4: MASKP0 Mask */ -#define GPIO_PORT_MASK4_MASKP1_Pos 1 /*!< GPIO_PORT MASK4: MASKP1 Position */ -#define GPIO_PORT_MASK4_MASKP1_Msk (0x01UL << GPIO_PORT_MASK4_MASKP1_Pos) /*!< GPIO_PORT MASK4: MASKP1 Mask */ -#define GPIO_PORT_MASK4_MASKP2_Pos 2 /*!< GPIO_PORT MASK4: MASKP2 Position */ -#define GPIO_PORT_MASK4_MASKP2_Msk (0x01UL << GPIO_PORT_MASK4_MASKP2_Pos) /*!< GPIO_PORT MASK4: MASKP2 Mask */ -#define GPIO_PORT_MASK4_MASKP3_Pos 3 /*!< GPIO_PORT MASK4: MASKP3 Position */ -#define GPIO_PORT_MASK4_MASKP3_Msk (0x01UL << GPIO_PORT_MASK4_MASKP3_Pos) /*!< GPIO_PORT MASK4: MASKP3 Mask */ -#define GPIO_PORT_MASK4_MASKP4_Pos 4 /*!< GPIO_PORT MASK4: MASKP4 Position */ -#define GPIO_PORT_MASK4_MASKP4_Msk (0x01UL << GPIO_PORT_MASK4_MASKP4_Pos) /*!< GPIO_PORT MASK4: MASKP4 Mask */ -#define GPIO_PORT_MASK4_MASKP5_Pos 5 /*!< GPIO_PORT MASK4: MASKP5 Position */ -#define GPIO_PORT_MASK4_MASKP5_Msk (0x01UL << GPIO_PORT_MASK4_MASKP5_Pos) /*!< GPIO_PORT MASK4: MASKP5 Mask */ -#define GPIO_PORT_MASK4_MASKP6_Pos 6 /*!< GPIO_PORT MASK4: MASKP6 Position */ -#define GPIO_PORT_MASK4_MASKP6_Msk (0x01UL << GPIO_PORT_MASK4_MASKP6_Pos) /*!< GPIO_PORT MASK4: MASKP6 Mask */ -#define GPIO_PORT_MASK4_MASKP7_Pos 7 /*!< GPIO_PORT MASK4: MASKP7 Position */ -#define GPIO_PORT_MASK4_MASKP7_Msk (0x01UL << GPIO_PORT_MASK4_MASKP7_Pos) /*!< GPIO_PORT MASK4: MASKP7 Mask */ -#define GPIO_PORT_MASK4_MASKP8_Pos 8 /*!< GPIO_PORT MASK4: MASKP8 Position */ -#define GPIO_PORT_MASK4_MASKP8_Msk (0x01UL << GPIO_PORT_MASK4_MASKP8_Pos) /*!< GPIO_PORT MASK4: MASKP8 Mask */ -#define GPIO_PORT_MASK4_MASKP9_Pos 9 /*!< GPIO_PORT MASK4: MASKP9 Position */ -#define GPIO_PORT_MASK4_MASKP9_Msk (0x01UL << GPIO_PORT_MASK4_MASKP9_Pos) /*!< GPIO_PORT MASK4: MASKP9 Mask */ -#define GPIO_PORT_MASK4_MASKP10_Pos 10 /*!< GPIO_PORT MASK4: MASKP10 Position */ -#define GPIO_PORT_MASK4_MASKP10_Msk (0x01UL << GPIO_PORT_MASK4_MASKP10_Pos) /*!< GPIO_PORT MASK4: MASKP10 Mask */ -#define GPIO_PORT_MASK4_MASKP11_Pos 11 /*!< GPIO_PORT MASK4: MASKP11 Position */ -#define GPIO_PORT_MASK4_MASKP11_Msk (0x01UL << GPIO_PORT_MASK4_MASKP11_Pos) /*!< GPIO_PORT MASK4: MASKP11 Mask */ -#define GPIO_PORT_MASK4_MASKP12_Pos 12 /*!< GPIO_PORT MASK4: MASKP12 Position */ -#define GPIO_PORT_MASK4_MASKP12_Msk (0x01UL << GPIO_PORT_MASK4_MASKP12_Pos) /*!< GPIO_PORT MASK4: MASKP12 Mask */ -#define GPIO_PORT_MASK4_MASKP13_Pos 13 /*!< GPIO_PORT MASK4: MASKP13 Position */ -#define GPIO_PORT_MASK4_MASKP13_Msk (0x01UL << GPIO_PORT_MASK4_MASKP13_Pos) /*!< GPIO_PORT MASK4: MASKP13 Mask */ -#define GPIO_PORT_MASK4_MASKP14_Pos 14 /*!< GPIO_PORT MASK4: MASKP14 Position */ -#define GPIO_PORT_MASK4_MASKP14_Msk (0x01UL << GPIO_PORT_MASK4_MASKP14_Pos) /*!< GPIO_PORT MASK4: MASKP14 Mask */ -#define GPIO_PORT_MASK4_MASKP15_Pos 15 /*!< GPIO_PORT MASK4: MASKP15 Position */ -#define GPIO_PORT_MASK4_MASKP15_Msk (0x01UL << GPIO_PORT_MASK4_MASKP15_Pos) /*!< GPIO_PORT MASK4: MASKP15 Mask */ -#define GPIO_PORT_MASK4_MASKP16_Pos 16 /*!< GPIO_PORT MASK4: MASKP16 Position */ -#define GPIO_PORT_MASK4_MASKP16_Msk (0x01UL << GPIO_PORT_MASK4_MASKP16_Pos) /*!< GPIO_PORT MASK4: MASKP16 Mask */ -#define GPIO_PORT_MASK4_MASKP17_Pos 17 /*!< GPIO_PORT MASK4: MASKP17 Position */ -#define GPIO_PORT_MASK4_MASKP17_Msk (0x01UL << GPIO_PORT_MASK4_MASKP17_Pos) /*!< GPIO_PORT MASK4: MASKP17 Mask */ -#define GPIO_PORT_MASK4_MASKP18_Pos 18 /*!< GPIO_PORT MASK4: MASKP18 Position */ -#define GPIO_PORT_MASK4_MASKP18_Msk (0x01UL << GPIO_PORT_MASK4_MASKP18_Pos) /*!< GPIO_PORT MASK4: MASKP18 Mask */ -#define GPIO_PORT_MASK4_MASKP19_Pos 19 /*!< GPIO_PORT MASK4: MASKP19 Position */ -#define GPIO_PORT_MASK4_MASKP19_Msk (0x01UL << GPIO_PORT_MASK4_MASKP19_Pos) /*!< GPIO_PORT MASK4: MASKP19 Mask */ -#define GPIO_PORT_MASK4_MASKP20_Pos 20 /*!< GPIO_PORT MASK4: MASKP20 Position */ -#define GPIO_PORT_MASK4_MASKP20_Msk (0x01UL << GPIO_PORT_MASK4_MASKP20_Pos) /*!< GPIO_PORT MASK4: MASKP20 Mask */ -#define GPIO_PORT_MASK4_MASKP21_Pos 21 /*!< GPIO_PORT MASK4: MASKP21 Position */ -#define GPIO_PORT_MASK4_MASKP21_Msk (0x01UL << GPIO_PORT_MASK4_MASKP21_Pos) /*!< GPIO_PORT MASK4: MASKP21 Mask */ -#define GPIO_PORT_MASK4_MASKP22_Pos 22 /*!< GPIO_PORT MASK4: MASKP22 Position */ -#define GPIO_PORT_MASK4_MASKP22_Msk (0x01UL << GPIO_PORT_MASK4_MASKP22_Pos) /*!< GPIO_PORT MASK4: MASKP22 Mask */ -#define GPIO_PORT_MASK4_MASKP23_Pos 23 /*!< GPIO_PORT MASK4: MASKP23 Position */ -#define GPIO_PORT_MASK4_MASKP23_Msk (0x01UL << GPIO_PORT_MASK4_MASKP23_Pos) /*!< GPIO_PORT MASK4: MASKP23 Mask */ -#define GPIO_PORT_MASK4_MASKP24_Pos 24 /*!< GPIO_PORT MASK4: MASKP24 Position */ -#define GPIO_PORT_MASK4_MASKP24_Msk (0x01UL << GPIO_PORT_MASK4_MASKP24_Pos) /*!< GPIO_PORT MASK4: MASKP24 Mask */ -#define GPIO_PORT_MASK4_MASKP25_Pos 25 /*!< GPIO_PORT MASK4: MASKP25 Position */ -#define GPIO_PORT_MASK4_MASKP25_Msk (0x01UL << GPIO_PORT_MASK4_MASKP25_Pos) /*!< GPIO_PORT MASK4: MASKP25 Mask */ -#define GPIO_PORT_MASK4_MASKP26_Pos 26 /*!< GPIO_PORT MASK4: MASKP26 Position */ -#define GPIO_PORT_MASK4_MASKP26_Msk (0x01UL << GPIO_PORT_MASK4_MASKP26_Pos) /*!< GPIO_PORT MASK4: MASKP26 Mask */ -#define GPIO_PORT_MASK4_MASKP27_Pos 27 /*!< GPIO_PORT MASK4: MASKP27 Position */ -#define GPIO_PORT_MASK4_MASKP27_Msk (0x01UL << GPIO_PORT_MASK4_MASKP27_Pos) /*!< GPIO_PORT MASK4: MASKP27 Mask */ -#define GPIO_PORT_MASK4_MASKP28_Pos 28 /*!< GPIO_PORT MASK4: MASKP28 Position */ -#define GPIO_PORT_MASK4_MASKP28_Msk (0x01UL << GPIO_PORT_MASK4_MASKP28_Pos) /*!< GPIO_PORT MASK4: MASKP28 Mask */ -#define GPIO_PORT_MASK4_MASKP29_Pos 29 /*!< GPIO_PORT MASK4: MASKP29 Position */ -#define GPIO_PORT_MASK4_MASKP29_Msk (0x01UL << GPIO_PORT_MASK4_MASKP29_Pos) /*!< GPIO_PORT MASK4: MASKP29 Mask */ -#define GPIO_PORT_MASK4_MASKP30_Pos 30 /*!< GPIO_PORT MASK4: MASKP30 Position */ -#define GPIO_PORT_MASK4_MASKP30_Msk (0x01UL << GPIO_PORT_MASK4_MASKP30_Pos) /*!< GPIO_PORT MASK4: MASKP30 Mask */ -#define GPIO_PORT_MASK4_MASKP31_Pos 31 /*!< GPIO_PORT MASK4: MASKP31 Position */ -#define GPIO_PORT_MASK4_MASKP31_Msk (0x01UL << GPIO_PORT_MASK4_MASKP31_Pos) /*!< GPIO_PORT MASK4: MASKP31 Mask */ - -// ------------------------------------- GPIO_PORT_MASK5 ---------------------------------------- -#define GPIO_PORT_MASK5_MASKP0_Pos 0 /*!< GPIO_PORT MASK5: MASKP0 Position */ -#define GPIO_PORT_MASK5_MASKP0_Msk (0x01UL << GPIO_PORT_MASK5_MASKP0_Pos) /*!< GPIO_PORT MASK5: MASKP0 Mask */ -#define GPIO_PORT_MASK5_MASKP1_Pos 1 /*!< GPIO_PORT MASK5: MASKP1 Position */ -#define GPIO_PORT_MASK5_MASKP1_Msk (0x01UL << GPIO_PORT_MASK5_MASKP1_Pos) /*!< GPIO_PORT MASK5: MASKP1 Mask */ -#define GPIO_PORT_MASK5_MASKP2_Pos 2 /*!< GPIO_PORT MASK5: MASKP2 Position */ -#define GPIO_PORT_MASK5_MASKP2_Msk (0x01UL << GPIO_PORT_MASK5_MASKP2_Pos) /*!< GPIO_PORT MASK5: MASKP2 Mask */ -#define GPIO_PORT_MASK5_MASKP3_Pos 3 /*!< GPIO_PORT MASK5: MASKP3 Position */ -#define GPIO_PORT_MASK5_MASKP3_Msk (0x01UL << GPIO_PORT_MASK5_MASKP3_Pos) /*!< GPIO_PORT MASK5: MASKP3 Mask */ -#define GPIO_PORT_MASK5_MASKP4_Pos 4 /*!< GPIO_PORT MASK5: MASKP4 Position */ -#define GPIO_PORT_MASK5_MASKP4_Msk (0x01UL << GPIO_PORT_MASK5_MASKP4_Pos) /*!< GPIO_PORT MASK5: MASKP4 Mask */ -#define GPIO_PORT_MASK5_MASKP5_Pos 5 /*!< GPIO_PORT MASK5: MASKP5 Position */ -#define GPIO_PORT_MASK5_MASKP5_Msk (0x01UL << GPIO_PORT_MASK5_MASKP5_Pos) /*!< GPIO_PORT MASK5: MASKP5 Mask */ -#define GPIO_PORT_MASK5_MASKP6_Pos 6 /*!< GPIO_PORT MASK5: MASKP6 Position */ -#define GPIO_PORT_MASK5_MASKP6_Msk (0x01UL << GPIO_PORT_MASK5_MASKP6_Pos) /*!< GPIO_PORT MASK5: MASKP6 Mask */ -#define GPIO_PORT_MASK5_MASKP7_Pos 7 /*!< GPIO_PORT MASK5: MASKP7 Position */ -#define GPIO_PORT_MASK5_MASKP7_Msk (0x01UL << GPIO_PORT_MASK5_MASKP7_Pos) /*!< GPIO_PORT MASK5: MASKP7 Mask */ -#define GPIO_PORT_MASK5_MASKP8_Pos 8 /*!< GPIO_PORT MASK5: MASKP8 Position */ -#define GPIO_PORT_MASK5_MASKP8_Msk (0x01UL << GPIO_PORT_MASK5_MASKP8_Pos) /*!< GPIO_PORT MASK5: MASKP8 Mask */ -#define GPIO_PORT_MASK5_MASKP9_Pos 9 /*!< GPIO_PORT MASK5: MASKP9 Position */ -#define GPIO_PORT_MASK5_MASKP9_Msk (0x01UL << GPIO_PORT_MASK5_MASKP9_Pos) /*!< GPIO_PORT MASK5: MASKP9 Mask */ -#define GPIO_PORT_MASK5_MASKP10_Pos 10 /*!< GPIO_PORT MASK5: MASKP10 Position */ -#define GPIO_PORT_MASK5_MASKP10_Msk (0x01UL << GPIO_PORT_MASK5_MASKP10_Pos) /*!< GPIO_PORT MASK5: MASKP10 Mask */ -#define GPIO_PORT_MASK5_MASKP11_Pos 11 /*!< GPIO_PORT MASK5: MASKP11 Position */ -#define GPIO_PORT_MASK5_MASKP11_Msk (0x01UL << GPIO_PORT_MASK5_MASKP11_Pos) /*!< GPIO_PORT MASK5: MASKP11 Mask */ -#define GPIO_PORT_MASK5_MASKP12_Pos 12 /*!< GPIO_PORT MASK5: MASKP12 Position */ -#define GPIO_PORT_MASK5_MASKP12_Msk (0x01UL << GPIO_PORT_MASK5_MASKP12_Pos) /*!< GPIO_PORT MASK5: MASKP12 Mask */ -#define GPIO_PORT_MASK5_MASKP13_Pos 13 /*!< GPIO_PORT MASK5: MASKP13 Position */ -#define GPIO_PORT_MASK5_MASKP13_Msk (0x01UL << GPIO_PORT_MASK5_MASKP13_Pos) /*!< GPIO_PORT MASK5: MASKP13 Mask */ -#define GPIO_PORT_MASK5_MASKP14_Pos 14 /*!< GPIO_PORT MASK5: MASKP14 Position */ -#define GPIO_PORT_MASK5_MASKP14_Msk (0x01UL << GPIO_PORT_MASK5_MASKP14_Pos) /*!< GPIO_PORT MASK5: MASKP14 Mask */ -#define GPIO_PORT_MASK5_MASKP15_Pos 15 /*!< GPIO_PORT MASK5: MASKP15 Position */ -#define GPIO_PORT_MASK5_MASKP15_Msk (0x01UL << GPIO_PORT_MASK5_MASKP15_Pos) /*!< GPIO_PORT MASK5: MASKP15 Mask */ -#define GPIO_PORT_MASK5_MASKP16_Pos 16 /*!< GPIO_PORT MASK5: MASKP16 Position */ -#define GPIO_PORT_MASK5_MASKP16_Msk (0x01UL << GPIO_PORT_MASK5_MASKP16_Pos) /*!< GPIO_PORT MASK5: MASKP16 Mask */ -#define GPIO_PORT_MASK5_MASKP17_Pos 17 /*!< GPIO_PORT MASK5: MASKP17 Position */ -#define GPIO_PORT_MASK5_MASKP17_Msk (0x01UL << GPIO_PORT_MASK5_MASKP17_Pos) /*!< GPIO_PORT MASK5: MASKP17 Mask */ -#define GPIO_PORT_MASK5_MASKP18_Pos 18 /*!< GPIO_PORT MASK5: MASKP18 Position */ -#define GPIO_PORT_MASK5_MASKP18_Msk (0x01UL << GPIO_PORT_MASK5_MASKP18_Pos) /*!< GPIO_PORT MASK5: MASKP18 Mask */ -#define GPIO_PORT_MASK5_MASKP19_Pos 19 /*!< GPIO_PORT MASK5: MASKP19 Position */ -#define GPIO_PORT_MASK5_MASKP19_Msk (0x01UL << GPIO_PORT_MASK5_MASKP19_Pos) /*!< GPIO_PORT MASK5: MASKP19 Mask */ -#define GPIO_PORT_MASK5_MASKP20_Pos 20 /*!< GPIO_PORT MASK5: MASKP20 Position */ -#define GPIO_PORT_MASK5_MASKP20_Msk (0x01UL << GPIO_PORT_MASK5_MASKP20_Pos) /*!< GPIO_PORT MASK5: MASKP20 Mask */ -#define GPIO_PORT_MASK5_MASKP21_Pos 21 /*!< GPIO_PORT MASK5: MASKP21 Position */ -#define GPIO_PORT_MASK5_MASKP21_Msk (0x01UL << GPIO_PORT_MASK5_MASKP21_Pos) /*!< GPIO_PORT MASK5: MASKP21 Mask */ -#define GPIO_PORT_MASK5_MASKP22_Pos 22 /*!< GPIO_PORT MASK5: MASKP22 Position */ -#define GPIO_PORT_MASK5_MASKP22_Msk (0x01UL << GPIO_PORT_MASK5_MASKP22_Pos) /*!< GPIO_PORT MASK5: MASKP22 Mask */ -#define GPIO_PORT_MASK5_MASKP23_Pos 23 /*!< GPIO_PORT MASK5: MASKP23 Position */ -#define GPIO_PORT_MASK5_MASKP23_Msk (0x01UL << GPIO_PORT_MASK5_MASKP23_Pos) /*!< GPIO_PORT MASK5: MASKP23 Mask */ -#define GPIO_PORT_MASK5_MASKP24_Pos 24 /*!< GPIO_PORT MASK5: MASKP24 Position */ -#define GPIO_PORT_MASK5_MASKP24_Msk (0x01UL << GPIO_PORT_MASK5_MASKP24_Pos) /*!< GPIO_PORT MASK5: MASKP24 Mask */ -#define GPIO_PORT_MASK5_MASKP25_Pos 25 /*!< GPIO_PORT MASK5: MASKP25 Position */ -#define GPIO_PORT_MASK5_MASKP25_Msk (0x01UL << GPIO_PORT_MASK5_MASKP25_Pos) /*!< GPIO_PORT MASK5: MASKP25 Mask */ -#define GPIO_PORT_MASK5_MASKP26_Pos 26 /*!< GPIO_PORT MASK5: MASKP26 Position */ -#define GPIO_PORT_MASK5_MASKP26_Msk (0x01UL << GPIO_PORT_MASK5_MASKP26_Pos) /*!< GPIO_PORT MASK5: MASKP26 Mask */ -#define GPIO_PORT_MASK5_MASKP27_Pos 27 /*!< GPIO_PORT MASK5: MASKP27 Position */ -#define GPIO_PORT_MASK5_MASKP27_Msk (0x01UL << GPIO_PORT_MASK5_MASKP27_Pos) /*!< GPIO_PORT MASK5: MASKP27 Mask */ -#define GPIO_PORT_MASK5_MASKP28_Pos 28 /*!< GPIO_PORT MASK5: MASKP28 Position */ -#define GPIO_PORT_MASK5_MASKP28_Msk (0x01UL << GPIO_PORT_MASK5_MASKP28_Pos) /*!< GPIO_PORT MASK5: MASKP28 Mask */ -#define GPIO_PORT_MASK5_MASKP29_Pos 29 /*!< GPIO_PORT MASK5: MASKP29 Position */ -#define GPIO_PORT_MASK5_MASKP29_Msk (0x01UL << GPIO_PORT_MASK5_MASKP29_Pos) /*!< GPIO_PORT MASK5: MASKP29 Mask */ -#define GPIO_PORT_MASK5_MASKP30_Pos 30 /*!< GPIO_PORT MASK5: MASKP30 Position */ -#define GPIO_PORT_MASK5_MASKP30_Msk (0x01UL << GPIO_PORT_MASK5_MASKP30_Pos) /*!< GPIO_PORT MASK5: MASKP30 Mask */ -#define GPIO_PORT_MASK5_MASKP31_Pos 31 /*!< GPIO_PORT MASK5: MASKP31 Position */ -#define GPIO_PORT_MASK5_MASKP31_Msk (0x01UL << GPIO_PORT_MASK5_MASKP31_Pos) /*!< GPIO_PORT MASK5: MASKP31 Mask */ - -// ------------------------------------- GPIO_PORT_MASK6 ---------------------------------------- -#define GPIO_PORT_MASK6_MASKP0_Pos 0 /*!< GPIO_PORT MASK6: MASKP0 Position */ -#define GPIO_PORT_MASK6_MASKP0_Msk (0x01UL << GPIO_PORT_MASK6_MASKP0_Pos) /*!< GPIO_PORT MASK6: MASKP0 Mask */ -#define GPIO_PORT_MASK6_MASKP1_Pos 1 /*!< GPIO_PORT MASK6: MASKP1 Position */ -#define GPIO_PORT_MASK6_MASKP1_Msk (0x01UL << GPIO_PORT_MASK6_MASKP1_Pos) /*!< GPIO_PORT MASK6: MASKP1 Mask */ -#define GPIO_PORT_MASK6_MASKP2_Pos 2 /*!< GPIO_PORT MASK6: MASKP2 Position */ -#define GPIO_PORT_MASK6_MASKP2_Msk (0x01UL << GPIO_PORT_MASK6_MASKP2_Pos) /*!< GPIO_PORT MASK6: MASKP2 Mask */ -#define GPIO_PORT_MASK6_MASKP3_Pos 3 /*!< GPIO_PORT MASK6: MASKP3 Position */ -#define GPIO_PORT_MASK6_MASKP3_Msk (0x01UL << GPIO_PORT_MASK6_MASKP3_Pos) /*!< GPIO_PORT MASK6: MASKP3 Mask */ -#define GPIO_PORT_MASK6_MASKP4_Pos 4 /*!< GPIO_PORT MASK6: MASKP4 Position */ -#define GPIO_PORT_MASK6_MASKP4_Msk (0x01UL << GPIO_PORT_MASK6_MASKP4_Pos) /*!< GPIO_PORT MASK6: MASKP4 Mask */ -#define GPIO_PORT_MASK6_MASKP5_Pos 5 /*!< GPIO_PORT MASK6: MASKP5 Position */ -#define GPIO_PORT_MASK6_MASKP5_Msk (0x01UL << GPIO_PORT_MASK6_MASKP5_Pos) /*!< GPIO_PORT MASK6: MASKP5 Mask */ -#define GPIO_PORT_MASK6_MASKP6_Pos 6 /*!< GPIO_PORT MASK6: MASKP6 Position */ -#define GPIO_PORT_MASK6_MASKP6_Msk (0x01UL << GPIO_PORT_MASK6_MASKP6_Pos) /*!< GPIO_PORT MASK6: MASKP6 Mask */ -#define GPIO_PORT_MASK6_MASKP7_Pos 7 /*!< GPIO_PORT MASK6: MASKP7 Position */ -#define GPIO_PORT_MASK6_MASKP7_Msk (0x01UL << GPIO_PORT_MASK6_MASKP7_Pos) /*!< GPIO_PORT MASK6: MASKP7 Mask */ -#define GPIO_PORT_MASK6_MASKP8_Pos 8 /*!< GPIO_PORT MASK6: MASKP8 Position */ -#define GPIO_PORT_MASK6_MASKP8_Msk (0x01UL << GPIO_PORT_MASK6_MASKP8_Pos) /*!< GPIO_PORT MASK6: MASKP8 Mask */ -#define GPIO_PORT_MASK6_MASKP9_Pos 9 /*!< GPIO_PORT MASK6: MASKP9 Position */ -#define GPIO_PORT_MASK6_MASKP9_Msk (0x01UL << GPIO_PORT_MASK6_MASKP9_Pos) /*!< GPIO_PORT MASK6: MASKP9 Mask */ -#define GPIO_PORT_MASK6_MASKP10_Pos 10 /*!< GPIO_PORT MASK6: MASKP10 Position */ -#define GPIO_PORT_MASK6_MASKP10_Msk (0x01UL << GPIO_PORT_MASK6_MASKP10_Pos) /*!< GPIO_PORT MASK6: MASKP10 Mask */ -#define GPIO_PORT_MASK6_MASKP11_Pos 11 /*!< GPIO_PORT MASK6: MASKP11 Position */ -#define GPIO_PORT_MASK6_MASKP11_Msk (0x01UL << GPIO_PORT_MASK6_MASKP11_Pos) /*!< GPIO_PORT MASK6: MASKP11 Mask */ -#define GPIO_PORT_MASK6_MASKP12_Pos 12 /*!< GPIO_PORT MASK6: MASKP12 Position */ -#define GPIO_PORT_MASK6_MASKP12_Msk (0x01UL << GPIO_PORT_MASK6_MASKP12_Pos) /*!< GPIO_PORT MASK6: MASKP12 Mask */ -#define GPIO_PORT_MASK6_MASKP13_Pos 13 /*!< GPIO_PORT MASK6: MASKP13 Position */ -#define GPIO_PORT_MASK6_MASKP13_Msk (0x01UL << GPIO_PORT_MASK6_MASKP13_Pos) /*!< GPIO_PORT MASK6: MASKP13 Mask */ -#define GPIO_PORT_MASK6_MASKP14_Pos 14 /*!< GPIO_PORT MASK6: MASKP14 Position */ -#define GPIO_PORT_MASK6_MASKP14_Msk (0x01UL << GPIO_PORT_MASK6_MASKP14_Pos) /*!< GPIO_PORT MASK6: MASKP14 Mask */ -#define GPIO_PORT_MASK6_MASKP15_Pos 15 /*!< GPIO_PORT MASK6: MASKP15 Position */ -#define GPIO_PORT_MASK6_MASKP15_Msk (0x01UL << GPIO_PORT_MASK6_MASKP15_Pos) /*!< GPIO_PORT MASK6: MASKP15 Mask */ -#define GPIO_PORT_MASK6_MASKP16_Pos 16 /*!< GPIO_PORT MASK6: MASKP16 Position */ -#define GPIO_PORT_MASK6_MASKP16_Msk (0x01UL << GPIO_PORT_MASK6_MASKP16_Pos) /*!< GPIO_PORT MASK6: MASKP16 Mask */ -#define GPIO_PORT_MASK6_MASKP17_Pos 17 /*!< GPIO_PORT MASK6: MASKP17 Position */ -#define GPIO_PORT_MASK6_MASKP17_Msk (0x01UL << GPIO_PORT_MASK6_MASKP17_Pos) /*!< GPIO_PORT MASK6: MASKP17 Mask */ -#define GPIO_PORT_MASK6_MASKP18_Pos 18 /*!< GPIO_PORT MASK6: MASKP18 Position */ -#define GPIO_PORT_MASK6_MASKP18_Msk (0x01UL << GPIO_PORT_MASK6_MASKP18_Pos) /*!< GPIO_PORT MASK6: MASKP18 Mask */ -#define GPIO_PORT_MASK6_MASKP19_Pos 19 /*!< GPIO_PORT MASK6: MASKP19 Position */ -#define GPIO_PORT_MASK6_MASKP19_Msk (0x01UL << GPIO_PORT_MASK6_MASKP19_Pos) /*!< GPIO_PORT MASK6: MASKP19 Mask */ -#define GPIO_PORT_MASK6_MASKP20_Pos 20 /*!< GPIO_PORT MASK6: MASKP20 Position */ -#define GPIO_PORT_MASK6_MASKP20_Msk (0x01UL << GPIO_PORT_MASK6_MASKP20_Pos) /*!< GPIO_PORT MASK6: MASKP20 Mask */ -#define GPIO_PORT_MASK6_MASKP21_Pos 21 /*!< GPIO_PORT MASK6: MASKP21 Position */ -#define GPIO_PORT_MASK6_MASKP21_Msk (0x01UL << GPIO_PORT_MASK6_MASKP21_Pos) /*!< GPIO_PORT MASK6: MASKP21 Mask */ -#define GPIO_PORT_MASK6_MASKP22_Pos 22 /*!< GPIO_PORT MASK6: MASKP22 Position */ -#define GPIO_PORT_MASK6_MASKP22_Msk (0x01UL << GPIO_PORT_MASK6_MASKP22_Pos) /*!< GPIO_PORT MASK6: MASKP22 Mask */ -#define GPIO_PORT_MASK6_MASKP23_Pos 23 /*!< GPIO_PORT MASK6: MASKP23 Position */ -#define GPIO_PORT_MASK6_MASKP23_Msk (0x01UL << GPIO_PORT_MASK6_MASKP23_Pos) /*!< GPIO_PORT MASK6: MASKP23 Mask */ -#define GPIO_PORT_MASK6_MASKP24_Pos 24 /*!< GPIO_PORT MASK6: MASKP24 Position */ -#define GPIO_PORT_MASK6_MASKP24_Msk (0x01UL << GPIO_PORT_MASK6_MASKP24_Pos) /*!< GPIO_PORT MASK6: MASKP24 Mask */ -#define GPIO_PORT_MASK6_MASKP25_Pos 25 /*!< GPIO_PORT MASK6: MASKP25 Position */ -#define GPIO_PORT_MASK6_MASKP25_Msk (0x01UL << GPIO_PORT_MASK6_MASKP25_Pos) /*!< GPIO_PORT MASK6: MASKP25 Mask */ -#define GPIO_PORT_MASK6_MASKP26_Pos 26 /*!< GPIO_PORT MASK6: MASKP26 Position */ -#define GPIO_PORT_MASK6_MASKP26_Msk (0x01UL << GPIO_PORT_MASK6_MASKP26_Pos) /*!< GPIO_PORT MASK6: MASKP26 Mask */ -#define GPIO_PORT_MASK6_MASKP27_Pos 27 /*!< GPIO_PORT MASK6: MASKP27 Position */ -#define GPIO_PORT_MASK6_MASKP27_Msk (0x01UL << GPIO_PORT_MASK6_MASKP27_Pos) /*!< GPIO_PORT MASK6: MASKP27 Mask */ -#define GPIO_PORT_MASK6_MASKP28_Pos 28 /*!< GPIO_PORT MASK6: MASKP28 Position */ -#define GPIO_PORT_MASK6_MASKP28_Msk (0x01UL << GPIO_PORT_MASK6_MASKP28_Pos) /*!< GPIO_PORT MASK6: MASKP28 Mask */ -#define GPIO_PORT_MASK6_MASKP29_Pos 29 /*!< GPIO_PORT MASK6: MASKP29 Position */ -#define GPIO_PORT_MASK6_MASKP29_Msk (0x01UL << GPIO_PORT_MASK6_MASKP29_Pos) /*!< GPIO_PORT MASK6: MASKP29 Mask */ -#define GPIO_PORT_MASK6_MASKP30_Pos 30 /*!< GPIO_PORT MASK6: MASKP30 Position */ -#define GPIO_PORT_MASK6_MASKP30_Msk (0x01UL << GPIO_PORT_MASK6_MASKP30_Pos) /*!< GPIO_PORT MASK6: MASKP30 Mask */ -#define GPIO_PORT_MASK6_MASKP31_Pos 31 /*!< GPIO_PORT MASK6: MASKP31 Position */ -#define GPIO_PORT_MASK6_MASKP31_Msk (0x01UL << GPIO_PORT_MASK6_MASKP31_Pos) /*!< GPIO_PORT MASK6: MASKP31 Mask */ - -// ------------------------------------- GPIO_PORT_MASK7 ---------------------------------------- -#define GPIO_PORT_MASK7_MASKP0_Pos 0 /*!< GPIO_PORT MASK7: MASKP0 Position */ -#define GPIO_PORT_MASK7_MASKP0_Msk (0x01UL << GPIO_PORT_MASK7_MASKP0_Pos) /*!< GPIO_PORT MASK7: MASKP0 Mask */ -#define GPIO_PORT_MASK7_MASKP1_Pos 1 /*!< GPIO_PORT MASK7: MASKP1 Position */ -#define GPIO_PORT_MASK7_MASKP1_Msk (0x01UL << GPIO_PORT_MASK7_MASKP1_Pos) /*!< GPIO_PORT MASK7: MASKP1 Mask */ -#define GPIO_PORT_MASK7_MASKP2_Pos 2 /*!< GPIO_PORT MASK7: MASKP2 Position */ -#define GPIO_PORT_MASK7_MASKP2_Msk (0x01UL << GPIO_PORT_MASK7_MASKP2_Pos) /*!< GPIO_PORT MASK7: MASKP2 Mask */ -#define GPIO_PORT_MASK7_MASKP3_Pos 3 /*!< GPIO_PORT MASK7: MASKP3 Position */ -#define GPIO_PORT_MASK7_MASKP3_Msk (0x01UL << GPIO_PORT_MASK7_MASKP3_Pos) /*!< GPIO_PORT MASK7: MASKP3 Mask */ -#define GPIO_PORT_MASK7_MASKP4_Pos 4 /*!< GPIO_PORT MASK7: MASKP4 Position */ -#define GPIO_PORT_MASK7_MASKP4_Msk (0x01UL << GPIO_PORT_MASK7_MASKP4_Pos) /*!< GPIO_PORT MASK7: MASKP4 Mask */ -#define GPIO_PORT_MASK7_MASKP5_Pos 5 /*!< GPIO_PORT MASK7: MASKP5 Position */ -#define GPIO_PORT_MASK7_MASKP5_Msk (0x01UL << GPIO_PORT_MASK7_MASKP5_Pos) /*!< GPIO_PORT MASK7: MASKP5 Mask */ -#define GPIO_PORT_MASK7_MASKP6_Pos 6 /*!< GPIO_PORT MASK7: MASKP6 Position */ -#define GPIO_PORT_MASK7_MASKP6_Msk (0x01UL << GPIO_PORT_MASK7_MASKP6_Pos) /*!< GPIO_PORT MASK7: MASKP6 Mask */ -#define GPIO_PORT_MASK7_MASKP7_Pos 7 /*!< GPIO_PORT MASK7: MASKP7 Position */ -#define GPIO_PORT_MASK7_MASKP7_Msk (0x01UL << GPIO_PORT_MASK7_MASKP7_Pos) /*!< GPIO_PORT MASK7: MASKP7 Mask */ -#define GPIO_PORT_MASK7_MASKP8_Pos 8 /*!< GPIO_PORT MASK7: MASKP8 Position */ -#define GPIO_PORT_MASK7_MASKP8_Msk (0x01UL << GPIO_PORT_MASK7_MASKP8_Pos) /*!< GPIO_PORT MASK7: MASKP8 Mask */ -#define GPIO_PORT_MASK7_MASKP9_Pos 9 /*!< GPIO_PORT MASK7: MASKP9 Position */ -#define GPIO_PORT_MASK7_MASKP9_Msk (0x01UL << GPIO_PORT_MASK7_MASKP9_Pos) /*!< GPIO_PORT MASK7: MASKP9 Mask */ -#define GPIO_PORT_MASK7_MASKP10_Pos 10 /*!< GPIO_PORT MASK7: MASKP10 Position */ -#define GPIO_PORT_MASK7_MASKP10_Msk (0x01UL << GPIO_PORT_MASK7_MASKP10_Pos) /*!< GPIO_PORT MASK7: MASKP10 Mask */ -#define GPIO_PORT_MASK7_MASKP11_Pos 11 /*!< GPIO_PORT MASK7: MASKP11 Position */ -#define GPIO_PORT_MASK7_MASKP11_Msk (0x01UL << GPIO_PORT_MASK7_MASKP11_Pos) /*!< GPIO_PORT MASK7: MASKP11 Mask */ -#define GPIO_PORT_MASK7_MASKP12_Pos 12 /*!< GPIO_PORT MASK7: MASKP12 Position */ -#define GPIO_PORT_MASK7_MASKP12_Msk (0x01UL << GPIO_PORT_MASK7_MASKP12_Pos) /*!< GPIO_PORT MASK7: MASKP12 Mask */ -#define GPIO_PORT_MASK7_MASKP13_Pos 13 /*!< GPIO_PORT MASK7: MASKP13 Position */ -#define GPIO_PORT_MASK7_MASKP13_Msk (0x01UL << GPIO_PORT_MASK7_MASKP13_Pos) /*!< GPIO_PORT MASK7: MASKP13 Mask */ -#define GPIO_PORT_MASK7_MASKP14_Pos 14 /*!< GPIO_PORT MASK7: MASKP14 Position */ -#define GPIO_PORT_MASK7_MASKP14_Msk (0x01UL << GPIO_PORT_MASK7_MASKP14_Pos) /*!< GPIO_PORT MASK7: MASKP14 Mask */ -#define GPIO_PORT_MASK7_MASKP15_Pos 15 /*!< GPIO_PORT MASK7: MASKP15 Position */ -#define GPIO_PORT_MASK7_MASKP15_Msk (0x01UL << GPIO_PORT_MASK7_MASKP15_Pos) /*!< GPIO_PORT MASK7: MASKP15 Mask */ -#define GPIO_PORT_MASK7_MASKP16_Pos 16 /*!< GPIO_PORT MASK7: MASKP16 Position */ -#define GPIO_PORT_MASK7_MASKP16_Msk (0x01UL << GPIO_PORT_MASK7_MASKP16_Pos) /*!< GPIO_PORT MASK7: MASKP16 Mask */ -#define GPIO_PORT_MASK7_MASKP17_Pos 17 /*!< GPIO_PORT MASK7: MASKP17 Position */ -#define GPIO_PORT_MASK7_MASKP17_Msk (0x01UL << GPIO_PORT_MASK7_MASKP17_Pos) /*!< GPIO_PORT MASK7: MASKP17 Mask */ -#define GPIO_PORT_MASK7_MASKP18_Pos 18 /*!< GPIO_PORT MASK7: MASKP18 Position */ -#define GPIO_PORT_MASK7_MASKP18_Msk (0x01UL << GPIO_PORT_MASK7_MASKP18_Pos) /*!< GPIO_PORT MASK7: MASKP18 Mask */ -#define GPIO_PORT_MASK7_MASKP19_Pos 19 /*!< GPIO_PORT MASK7: MASKP19 Position */ -#define GPIO_PORT_MASK7_MASKP19_Msk (0x01UL << GPIO_PORT_MASK7_MASKP19_Pos) /*!< GPIO_PORT MASK7: MASKP19 Mask */ -#define GPIO_PORT_MASK7_MASKP20_Pos 20 /*!< GPIO_PORT MASK7: MASKP20 Position */ -#define GPIO_PORT_MASK7_MASKP20_Msk (0x01UL << GPIO_PORT_MASK7_MASKP20_Pos) /*!< GPIO_PORT MASK7: MASKP20 Mask */ -#define GPIO_PORT_MASK7_MASKP21_Pos 21 /*!< GPIO_PORT MASK7: MASKP21 Position */ -#define GPIO_PORT_MASK7_MASKP21_Msk (0x01UL << GPIO_PORT_MASK7_MASKP21_Pos) /*!< GPIO_PORT MASK7: MASKP21 Mask */ -#define GPIO_PORT_MASK7_MASKP22_Pos 22 /*!< GPIO_PORT MASK7: MASKP22 Position */ -#define GPIO_PORT_MASK7_MASKP22_Msk (0x01UL << GPIO_PORT_MASK7_MASKP22_Pos) /*!< GPIO_PORT MASK7: MASKP22 Mask */ -#define GPIO_PORT_MASK7_MASKP23_Pos 23 /*!< GPIO_PORT MASK7: MASKP23 Position */ -#define GPIO_PORT_MASK7_MASKP23_Msk (0x01UL << GPIO_PORT_MASK7_MASKP23_Pos) /*!< GPIO_PORT MASK7: MASKP23 Mask */ -#define GPIO_PORT_MASK7_MASKP24_Pos 24 /*!< GPIO_PORT MASK7: MASKP24 Position */ -#define GPIO_PORT_MASK7_MASKP24_Msk (0x01UL << GPIO_PORT_MASK7_MASKP24_Pos) /*!< GPIO_PORT MASK7: MASKP24 Mask */ -#define GPIO_PORT_MASK7_MASKP25_Pos 25 /*!< GPIO_PORT MASK7: MASKP25 Position */ -#define GPIO_PORT_MASK7_MASKP25_Msk (0x01UL << GPIO_PORT_MASK7_MASKP25_Pos) /*!< GPIO_PORT MASK7: MASKP25 Mask */ -#define GPIO_PORT_MASK7_MASKP26_Pos 26 /*!< GPIO_PORT MASK7: MASKP26 Position */ -#define GPIO_PORT_MASK7_MASKP26_Msk (0x01UL << GPIO_PORT_MASK7_MASKP26_Pos) /*!< GPIO_PORT MASK7: MASKP26 Mask */ -#define GPIO_PORT_MASK7_MASKP27_Pos 27 /*!< GPIO_PORT MASK7: MASKP27 Position */ -#define GPIO_PORT_MASK7_MASKP27_Msk (0x01UL << GPIO_PORT_MASK7_MASKP27_Pos) /*!< GPIO_PORT MASK7: MASKP27 Mask */ -#define GPIO_PORT_MASK7_MASKP28_Pos 28 /*!< GPIO_PORT MASK7: MASKP28 Position */ -#define GPIO_PORT_MASK7_MASKP28_Msk (0x01UL << GPIO_PORT_MASK7_MASKP28_Pos) /*!< GPIO_PORT MASK7: MASKP28 Mask */ -#define GPIO_PORT_MASK7_MASKP29_Pos 29 /*!< GPIO_PORT MASK7: MASKP29 Position */ -#define GPIO_PORT_MASK7_MASKP29_Msk (0x01UL << GPIO_PORT_MASK7_MASKP29_Pos) /*!< GPIO_PORT MASK7: MASKP29 Mask */ -#define GPIO_PORT_MASK7_MASKP30_Pos 30 /*!< GPIO_PORT MASK7: MASKP30 Position */ -#define GPIO_PORT_MASK7_MASKP30_Msk (0x01UL << GPIO_PORT_MASK7_MASKP30_Pos) /*!< GPIO_PORT MASK7: MASKP30 Mask */ -#define GPIO_PORT_MASK7_MASKP31_Pos 31 /*!< GPIO_PORT MASK7: MASKP31 Position */ -#define GPIO_PORT_MASK7_MASKP31_Msk (0x01UL << GPIO_PORT_MASK7_MASKP31_Pos) /*!< GPIO_PORT MASK7: MASKP31 Mask */ - -// ------------------------------------- GPIO_PORT_PIN0 ----------------------------------------- -#define GPIO_PORT_PIN0_PORT0_Pos 0 /*!< GPIO_PORT PIN0: PORT0 Position */ -#define GPIO_PORT_PIN0_PORT0_Msk (0x01UL << GPIO_PORT_PIN0_PORT0_Pos) /*!< GPIO_PORT PIN0: PORT0 Mask */ -#define GPIO_PORT_PIN0_PORT1_Pos 1 /*!< GPIO_PORT PIN0: PORT1 Position */ -#define GPIO_PORT_PIN0_PORT1_Msk (0x01UL << GPIO_PORT_PIN0_PORT1_Pos) /*!< GPIO_PORT PIN0: PORT1 Mask */ -#define GPIO_PORT_PIN0_PORT2_Pos 2 /*!< GPIO_PORT PIN0: PORT2 Position */ -#define GPIO_PORT_PIN0_PORT2_Msk (0x01UL << GPIO_PORT_PIN0_PORT2_Pos) /*!< GPIO_PORT PIN0: PORT2 Mask */ -#define GPIO_PORT_PIN0_PORT3_Pos 3 /*!< GPIO_PORT PIN0: PORT3 Position */ -#define GPIO_PORT_PIN0_PORT3_Msk (0x01UL << GPIO_PORT_PIN0_PORT3_Pos) /*!< GPIO_PORT PIN0: PORT3 Mask */ -#define GPIO_PORT_PIN0_PORT4_Pos 4 /*!< GPIO_PORT PIN0: PORT4 Position */ -#define GPIO_PORT_PIN0_PORT4_Msk (0x01UL << GPIO_PORT_PIN0_PORT4_Pos) /*!< GPIO_PORT PIN0: PORT4 Mask */ -#define GPIO_PORT_PIN0_PORT5_Pos 5 /*!< GPIO_PORT PIN0: PORT5 Position */ -#define GPIO_PORT_PIN0_PORT5_Msk (0x01UL << GPIO_PORT_PIN0_PORT5_Pos) /*!< GPIO_PORT PIN0: PORT5 Mask */ -#define GPIO_PORT_PIN0_PORT6_Pos 6 /*!< GPIO_PORT PIN0: PORT6 Position */ -#define GPIO_PORT_PIN0_PORT6_Msk (0x01UL << GPIO_PORT_PIN0_PORT6_Pos) /*!< GPIO_PORT PIN0: PORT6 Mask */ -#define GPIO_PORT_PIN0_PORT7_Pos 7 /*!< GPIO_PORT PIN0: PORT7 Position */ -#define GPIO_PORT_PIN0_PORT7_Msk (0x01UL << GPIO_PORT_PIN0_PORT7_Pos) /*!< GPIO_PORT PIN0: PORT7 Mask */ -#define GPIO_PORT_PIN0_PORT8_Pos 8 /*!< GPIO_PORT PIN0: PORT8 Position */ -#define GPIO_PORT_PIN0_PORT8_Msk (0x01UL << GPIO_PORT_PIN0_PORT8_Pos) /*!< GPIO_PORT PIN0: PORT8 Mask */ -#define GPIO_PORT_PIN0_PORT9_Pos 9 /*!< GPIO_PORT PIN0: PORT9 Position */ -#define GPIO_PORT_PIN0_PORT9_Msk (0x01UL << GPIO_PORT_PIN0_PORT9_Pos) /*!< GPIO_PORT PIN0: PORT9 Mask */ -#define GPIO_PORT_PIN0_PORT10_Pos 10 /*!< GPIO_PORT PIN0: PORT10 Position */ -#define GPIO_PORT_PIN0_PORT10_Msk (0x01UL << GPIO_PORT_PIN0_PORT10_Pos) /*!< GPIO_PORT PIN0: PORT10 Mask */ -#define GPIO_PORT_PIN0_PORT11_Pos 11 /*!< GPIO_PORT PIN0: PORT11 Position */ -#define GPIO_PORT_PIN0_PORT11_Msk (0x01UL << GPIO_PORT_PIN0_PORT11_Pos) /*!< GPIO_PORT PIN0: PORT11 Mask */ -#define GPIO_PORT_PIN0_PORT12_Pos 12 /*!< GPIO_PORT PIN0: PORT12 Position */ -#define GPIO_PORT_PIN0_PORT12_Msk (0x01UL << GPIO_PORT_PIN0_PORT12_Pos) /*!< GPIO_PORT PIN0: PORT12 Mask */ -#define GPIO_PORT_PIN0_PORT13_Pos 13 /*!< GPIO_PORT PIN0: PORT13 Position */ -#define GPIO_PORT_PIN0_PORT13_Msk (0x01UL << GPIO_PORT_PIN0_PORT13_Pos) /*!< GPIO_PORT PIN0: PORT13 Mask */ -#define GPIO_PORT_PIN0_PORT14_Pos 14 /*!< GPIO_PORT PIN0: PORT14 Position */ -#define GPIO_PORT_PIN0_PORT14_Msk (0x01UL << GPIO_PORT_PIN0_PORT14_Pos) /*!< GPIO_PORT PIN0: PORT14 Mask */ -#define GPIO_PORT_PIN0_PORT15_Pos 15 /*!< GPIO_PORT PIN0: PORT15 Position */ -#define GPIO_PORT_PIN0_PORT15_Msk (0x01UL << GPIO_PORT_PIN0_PORT15_Pos) /*!< GPIO_PORT PIN0: PORT15 Mask */ -#define GPIO_PORT_PIN0_PORT16_Pos 16 /*!< GPIO_PORT PIN0: PORT16 Position */ -#define GPIO_PORT_PIN0_PORT16_Msk (0x01UL << GPIO_PORT_PIN0_PORT16_Pos) /*!< GPIO_PORT PIN0: PORT16 Mask */ -#define GPIO_PORT_PIN0_PORT17_Pos 17 /*!< GPIO_PORT PIN0: PORT17 Position */ -#define GPIO_PORT_PIN0_PORT17_Msk (0x01UL << GPIO_PORT_PIN0_PORT17_Pos) /*!< GPIO_PORT PIN0: PORT17 Mask */ -#define GPIO_PORT_PIN0_PORT18_Pos 18 /*!< GPIO_PORT PIN0: PORT18 Position */ -#define GPIO_PORT_PIN0_PORT18_Msk (0x01UL << GPIO_PORT_PIN0_PORT18_Pos) /*!< GPIO_PORT PIN0: PORT18 Mask */ -#define GPIO_PORT_PIN0_PORT19_Pos 19 /*!< GPIO_PORT PIN0: PORT19 Position */ -#define GPIO_PORT_PIN0_PORT19_Msk (0x01UL << GPIO_PORT_PIN0_PORT19_Pos) /*!< GPIO_PORT PIN0: PORT19 Mask */ -#define GPIO_PORT_PIN0_PORT20_Pos 20 /*!< GPIO_PORT PIN0: PORT20 Position */ -#define GPIO_PORT_PIN0_PORT20_Msk (0x01UL << GPIO_PORT_PIN0_PORT20_Pos) /*!< GPIO_PORT PIN0: PORT20 Mask */ -#define GPIO_PORT_PIN0_PORT21_Pos 21 /*!< GPIO_PORT PIN0: PORT21 Position */ -#define GPIO_PORT_PIN0_PORT21_Msk (0x01UL << GPIO_PORT_PIN0_PORT21_Pos) /*!< GPIO_PORT PIN0: PORT21 Mask */ -#define GPIO_PORT_PIN0_PORT22_Pos 22 /*!< GPIO_PORT PIN0: PORT22 Position */ -#define GPIO_PORT_PIN0_PORT22_Msk (0x01UL << GPIO_PORT_PIN0_PORT22_Pos) /*!< GPIO_PORT PIN0: PORT22 Mask */ -#define GPIO_PORT_PIN0_PORT23_Pos 23 /*!< GPIO_PORT PIN0: PORT23 Position */ -#define GPIO_PORT_PIN0_PORT23_Msk (0x01UL << GPIO_PORT_PIN0_PORT23_Pos) /*!< GPIO_PORT PIN0: PORT23 Mask */ -#define GPIO_PORT_PIN0_PORT24_Pos 24 /*!< GPIO_PORT PIN0: PORT24 Position */ -#define GPIO_PORT_PIN0_PORT24_Msk (0x01UL << GPIO_PORT_PIN0_PORT24_Pos) /*!< GPIO_PORT PIN0: PORT24 Mask */ -#define GPIO_PORT_PIN0_PORT25_Pos 25 /*!< GPIO_PORT PIN0: PORT25 Position */ -#define GPIO_PORT_PIN0_PORT25_Msk (0x01UL << GPIO_PORT_PIN0_PORT25_Pos) /*!< GPIO_PORT PIN0: PORT25 Mask */ -#define GPIO_PORT_PIN0_PORT26_Pos 26 /*!< GPIO_PORT PIN0: PORT26 Position */ -#define GPIO_PORT_PIN0_PORT26_Msk (0x01UL << GPIO_PORT_PIN0_PORT26_Pos) /*!< GPIO_PORT PIN0: PORT26 Mask */ -#define GPIO_PORT_PIN0_PORT27_Pos 27 /*!< GPIO_PORT PIN0: PORT27 Position */ -#define GPIO_PORT_PIN0_PORT27_Msk (0x01UL << GPIO_PORT_PIN0_PORT27_Pos) /*!< GPIO_PORT PIN0: PORT27 Mask */ -#define GPIO_PORT_PIN0_PORT28_Pos 28 /*!< GPIO_PORT PIN0: PORT28 Position */ -#define GPIO_PORT_PIN0_PORT28_Msk (0x01UL << GPIO_PORT_PIN0_PORT28_Pos) /*!< GPIO_PORT PIN0: PORT28 Mask */ -#define GPIO_PORT_PIN0_PORT29_Pos 29 /*!< GPIO_PORT PIN0: PORT29 Position */ -#define GPIO_PORT_PIN0_PORT29_Msk (0x01UL << GPIO_PORT_PIN0_PORT29_Pos) /*!< GPIO_PORT PIN0: PORT29 Mask */ -#define GPIO_PORT_PIN0_PORT30_Pos 30 /*!< GPIO_PORT PIN0: PORT30 Position */ -#define GPIO_PORT_PIN0_PORT30_Msk (0x01UL << GPIO_PORT_PIN0_PORT30_Pos) /*!< GPIO_PORT PIN0: PORT30 Mask */ -#define GPIO_PORT_PIN0_PORT31_Pos 31 /*!< GPIO_PORT PIN0: PORT31 Position */ -#define GPIO_PORT_PIN0_PORT31_Msk (0x01UL << GPIO_PORT_PIN0_PORT31_Pos) /*!< GPIO_PORT PIN0: PORT31 Mask */ - -// ------------------------------------- GPIO_PORT_PIN1 ----------------------------------------- -#define GPIO_PORT_PIN1_PORT0_Pos 0 /*!< GPIO_PORT PIN1: PORT0 Position */ -#define GPIO_PORT_PIN1_PORT0_Msk (0x01UL << GPIO_PORT_PIN1_PORT0_Pos) /*!< GPIO_PORT PIN1: PORT0 Mask */ -#define GPIO_PORT_PIN1_PORT1_Pos 1 /*!< GPIO_PORT PIN1: PORT1 Position */ -#define GPIO_PORT_PIN1_PORT1_Msk (0x01UL << GPIO_PORT_PIN1_PORT1_Pos) /*!< GPIO_PORT PIN1: PORT1 Mask */ -#define GPIO_PORT_PIN1_PORT2_Pos 2 /*!< GPIO_PORT PIN1: PORT2 Position */ -#define GPIO_PORT_PIN1_PORT2_Msk (0x01UL << GPIO_PORT_PIN1_PORT2_Pos) /*!< GPIO_PORT PIN1: PORT2 Mask */ -#define GPIO_PORT_PIN1_PORT3_Pos 3 /*!< GPIO_PORT PIN1: PORT3 Position */ -#define GPIO_PORT_PIN1_PORT3_Msk (0x01UL << GPIO_PORT_PIN1_PORT3_Pos) /*!< GPIO_PORT PIN1: PORT3 Mask */ -#define GPIO_PORT_PIN1_PORT4_Pos 4 /*!< GPIO_PORT PIN1: PORT4 Position */ -#define GPIO_PORT_PIN1_PORT4_Msk (0x01UL << GPIO_PORT_PIN1_PORT4_Pos) /*!< GPIO_PORT PIN1: PORT4 Mask */ -#define GPIO_PORT_PIN1_PORT5_Pos 5 /*!< GPIO_PORT PIN1: PORT5 Position */ -#define GPIO_PORT_PIN1_PORT5_Msk (0x01UL << GPIO_PORT_PIN1_PORT5_Pos) /*!< GPIO_PORT PIN1: PORT5 Mask */ -#define GPIO_PORT_PIN1_PORT6_Pos 6 /*!< GPIO_PORT PIN1: PORT6 Position */ -#define GPIO_PORT_PIN1_PORT6_Msk (0x01UL << GPIO_PORT_PIN1_PORT6_Pos) /*!< GPIO_PORT PIN1: PORT6 Mask */ -#define GPIO_PORT_PIN1_PORT7_Pos 7 /*!< GPIO_PORT PIN1: PORT7 Position */ -#define GPIO_PORT_PIN1_PORT7_Msk (0x01UL << GPIO_PORT_PIN1_PORT7_Pos) /*!< GPIO_PORT PIN1: PORT7 Mask */ -#define GPIO_PORT_PIN1_PORT8_Pos 8 /*!< GPIO_PORT PIN1: PORT8 Position */ -#define GPIO_PORT_PIN1_PORT8_Msk (0x01UL << GPIO_PORT_PIN1_PORT8_Pos) /*!< GPIO_PORT PIN1: PORT8 Mask */ -#define GPIO_PORT_PIN1_PORT9_Pos 9 /*!< GPIO_PORT PIN1: PORT9 Position */ -#define GPIO_PORT_PIN1_PORT9_Msk (0x01UL << GPIO_PORT_PIN1_PORT9_Pos) /*!< GPIO_PORT PIN1: PORT9 Mask */ -#define GPIO_PORT_PIN1_PORT10_Pos 10 /*!< GPIO_PORT PIN1: PORT10 Position */ -#define GPIO_PORT_PIN1_PORT10_Msk (0x01UL << GPIO_PORT_PIN1_PORT10_Pos) /*!< GPIO_PORT PIN1: PORT10 Mask */ -#define GPIO_PORT_PIN1_PORT11_Pos 11 /*!< GPIO_PORT PIN1: PORT11 Position */ -#define GPIO_PORT_PIN1_PORT11_Msk (0x01UL << GPIO_PORT_PIN1_PORT11_Pos) /*!< GPIO_PORT PIN1: PORT11 Mask */ -#define GPIO_PORT_PIN1_PORT12_Pos 12 /*!< GPIO_PORT PIN1: PORT12 Position */ -#define GPIO_PORT_PIN1_PORT12_Msk (0x01UL << GPIO_PORT_PIN1_PORT12_Pos) /*!< GPIO_PORT PIN1: PORT12 Mask */ -#define GPIO_PORT_PIN1_PORT13_Pos 13 /*!< GPIO_PORT PIN1: PORT13 Position */ -#define GPIO_PORT_PIN1_PORT13_Msk (0x01UL << GPIO_PORT_PIN1_PORT13_Pos) /*!< GPIO_PORT PIN1: PORT13 Mask */ -#define GPIO_PORT_PIN1_PORT14_Pos 14 /*!< GPIO_PORT PIN1: PORT14 Position */ -#define GPIO_PORT_PIN1_PORT14_Msk (0x01UL << GPIO_PORT_PIN1_PORT14_Pos) /*!< GPIO_PORT PIN1: PORT14 Mask */ -#define GPIO_PORT_PIN1_PORT15_Pos 15 /*!< GPIO_PORT PIN1: PORT15 Position */ -#define GPIO_PORT_PIN1_PORT15_Msk (0x01UL << GPIO_PORT_PIN1_PORT15_Pos) /*!< GPIO_PORT PIN1: PORT15 Mask */ -#define GPIO_PORT_PIN1_PORT16_Pos 16 /*!< GPIO_PORT PIN1: PORT16 Position */ -#define GPIO_PORT_PIN1_PORT16_Msk (0x01UL << GPIO_PORT_PIN1_PORT16_Pos) /*!< GPIO_PORT PIN1: PORT16 Mask */ -#define GPIO_PORT_PIN1_PORT17_Pos 17 /*!< GPIO_PORT PIN1: PORT17 Position */ -#define GPIO_PORT_PIN1_PORT17_Msk (0x01UL << GPIO_PORT_PIN1_PORT17_Pos) /*!< GPIO_PORT PIN1: PORT17 Mask */ -#define GPIO_PORT_PIN1_PORT18_Pos 18 /*!< GPIO_PORT PIN1: PORT18 Position */ -#define GPIO_PORT_PIN1_PORT18_Msk (0x01UL << GPIO_PORT_PIN1_PORT18_Pos) /*!< GPIO_PORT PIN1: PORT18 Mask */ -#define GPIO_PORT_PIN1_PORT19_Pos 19 /*!< GPIO_PORT PIN1: PORT19 Position */ -#define GPIO_PORT_PIN1_PORT19_Msk (0x01UL << GPIO_PORT_PIN1_PORT19_Pos) /*!< GPIO_PORT PIN1: PORT19 Mask */ -#define GPIO_PORT_PIN1_PORT20_Pos 20 /*!< GPIO_PORT PIN1: PORT20 Position */ -#define GPIO_PORT_PIN1_PORT20_Msk (0x01UL << GPIO_PORT_PIN1_PORT20_Pos) /*!< GPIO_PORT PIN1: PORT20 Mask */ -#define GPIO_PORT_PIN1_PORT21_Pos 21 /*!< GPIO_PORT PIN1: PORT21 Position */ -#define GPIO_PORT_PIN1_PORT21_Msk (0x01UL << GPIO_PORT_PIN1_PORT21_Pos) /*!< GPIO_PORT PIN1: PORT21 Mask */ -#define GPIO_PORT_PIN1_PORT22_Pos 22 /*!< GPIO_PORT PIN1: PORT22 Position */ -#define GPIO_PORT_PIN1_PORT22_Msk (0x01UL << GPIO_PORT_PIN1_PORT22_Pos) /*!< GPIO_PORT PIN1: PORT22 Mask */ -#define GPIO_PORT_PIN1_PORT23_Pos 23 /*!< GPIO_PORT PIN1: PORT23 Position */ -#define GPIO_PORT_PIN1_PORT23_Msk (0x01UL << GPIO_PORT_PIN1_PORT23_Pos) /*!< GPIO_PORT PIN1: PORT23 Mask */ -#define GPIO_PORT_PIN1_PORT24_Pos 24 /*!< GPIO_PORT PIN1: PORT24 Position */ -#define GPIO_PORT_PIN1_PORT24_Msk (0x01UL << GPIO_PORT_PIN1_PORT24_Pos) /*!< GPIO_PORT PIN1: PORT24 Mask */ -#define GPIO_PORT_PIN1_PORT25_Pos 25 /*!< GPIO_PORT PIN1: PORT25 Position */ -#define GPIO_PORT_PIN1_PORT25_Msk (0x01UL << GPIO_PORT_PIN1_PORT25_Pos) /*!< GPIO_PORT PIN1: PORT25 Mask */ -#define GPIO_PORT_PIN1_PORT26_Pos 26 /*!< GPIO_PORT PIN1: PORT26 Position */ -#define GPIO_PORT_PIN1_PORT26_Msk (0x01UL << GPIO_PORT_PIN1_PORT26_Pos) /*!< GPIO_PORT PIN1: PORT26 Mask */ -#define GPIO_PORT_PIN1_PORT27_Pos 27 /*!< GPIO_PORT PIN1: PORT27 Position */ -#define GPIO_PORT_PIN1_PORT27_Msk (0x01UL << GPIO_PORT_PIN1_PORT27_Pos) /*!< GPIO_PORT PIN1: PORT27 Mask */ -#define GPIO_PORT_PIN1_PORT28_Pos 28 /*!< GPIO_PORT PIN1: PORT28 Position */ -#define GPIO_PORT_PIN1_PORT28_Msk (0x01UL << GPIO_PORT_PIN1_PORT28_Pos) /*!< GPIO_PORT PIN1: PORT28 Mask */ -#define GPIO_PORT_PIN1_PORT29_Pos 29 /*!< GPIO_PORT PIN1: PORT29 Position */ -#define GPIO_PORT_PIN1_PORT29_Msk (0x01UL << GPIO_PORT_PIN1_PORT29_Pos) /*!< GPIO_PORT PIN1: PORT29 Mask */ -#define GPIO_PORT_PIN1_PORT30_Pos 30 /*!< GPIO_PORT PIN1: PORT30 Position */ -#define GPIO_PORT_PIN1_PORT30_Msk (0x01UL << GPIO_PORT_PIN1_PORT30_Pos) /*!< GPIO_PORT PIN1: PORT30 Mask */ -#define GPIO_PORT_PIN1_PORT31_Pos 31 /*!< GPIO_PORT PIN1: PORT31 Position */ -#define GPIO_PORT_PIN1_PORT31_Msk (0x01UL << GPIO_PORT_PIN1_PORT31_Pos) /*!< GPIO_PORT PIN1: PORT31 Mask */ - -// ------------------------------------- GPIO_PORT_PIN2 ----------------------------------------- -#define GPIO_PORT_PIN2_PORT0_Pos 0 /*!< GPIO_PORT PIN2: PORT0 Position */ -#define GPIO_PORT_PIN2_PORT0_Msk (0x01UL << GPIO_PORT_PIN2_PORT0_Pos) /*!< GPIO_PORT PIN2: PORT0 Mask */ -#define GPIO_PORT_PIN2_PORT1_Pos 1 /*!< GPIO_PORT PIN2: PORT1 Position */ -#define GPIO_PORT_PIN2_PORT1_Msk (0x01UL << GPIO_PORT_PIN2_PORT1_Pos) /*!< GPIO_PORT PIN2: PORT1 Mask */ -#define GPIO_PORT_PIN2_PORT2_Pos 2 /*!< GPIO_PORT PIN2: PORT2 Position */ -#define GPIO_PORT_PIN2_PORT2_Msk (0x01UL << GPIO_PORT_PIN2_PORT2_Pos) /*!< GPIO_PORT PIN2: PORT2 Mask */ -#define GPIO_PORT_PIN2_PORT3_Pos 3 /*!< GPIO_PORT PIN2: PORT3 Position */ -#define GPIO_PORT_PIN2_PORT3_Msk (0x01UL << GPIO_PORT_PIN2_PORT3_Pos) /*!< GPIO_PORT PIN2: PORT3 Mask */ -#define GPIO_PORT_PIN2_PORT4_Pos 4 /*!< GPIO_PORT PIN2: PORT4 Position */ -#define GPIO_PORT_PIN2_PORT4_Msk (0x01UL << GPIO_PORT_PIN2_PORT4_Pos) /*!< GPIO_PORT PIN2: PORT4 Mask */ -#define GPIO_PORT_PIN2_PORT5_Pos 5 /*!< GPIO_PORT PIN2: PORT5 Position */ -#define GPIO_PORT_PIN2_PORT5_Msk (0x01UL << GPIO_PORT_PIN2_PORT5_Pos) /*!< GPIO_PORT PIN2: PORT5 Mask */ -#define GPIO_PORT_PIN2_PORT6_Pos 6 /*!< GPIO_PORT PIN2: PORT6 Position */ -#define GPIO_PORT_PIN2_PORT6_Msk (0x01UL << GPIO_PORT_PIN2_PORT6_Pos) /*!< GPIO_PORT PIN2: PORT6 Mask */ -#define GPIO_PORT_PIN2_PORT7_Pos 7 /*!< GPIO_PORT PIN2: PORT7 Position */ -#define GPIO_PORT_PIN2_PORT7_Msk (0x01UL << GPIO_PORT_PIN2_PORT7_Pos) /*!< GPIO_PORT PIN2: PORT7 Mask */ -#define GPIO_PORT_PIN2_PORT8_Pos 8 /*!< GPIO_PORT PIN2: PORT8 Position */ -#define GPIO_PORT_PIN2_PORT8_Msk (0x01UL << GPIO_PORT_PIN2_PORT8_Pos) /*!< GPIO_PORT PIN2: PORT8 Mask */ -#define GPIO_PORT_PIN2_PORT9_Pos 9 /*!< GPIO_PORT PIN2: PORT9 Position */ -#define GPIO_PORT_PIN2_PORT9_Msk (0x01UL << GPIO_PORT_PIN2_PORT9_Pos) /*!< GPIO_PORT PIN2: PORT9 Mask */ -#define GPIO_PORT_PIN2_PORT10_Pos 10 /*!< GPIO_PORT PIN2: PORT10 Position */ -#define GPIO_PORT_PIN2_PORT10_Msk (0x01UL << GPIO_PORT_PIN2_PORT10_Pos) /*!< GPIO_PORT PIN2: PORT10 Mask */ -#define GPIO_PORT_PIN2_PORT11_Pos 11 /*!< GPIO_PORT PIN2: PORT11 Position */ -#define GPIO_PORT_PIN2_PORT11_Msk (0x01UL << GPIO_PORT_PIN2_PORT11_Pos) /*!< GPIO_PORT PIN2: PORT11 Mask */ -#define GPIO_PORT_PIN2_PORT12_Pos 12 /*!< GPIO_PORT PIN2: PORT12 Position */ -#define GPIO_PORT_PIN2_PORT12_Msk (0x01UL << GPIO_PORT_PIN2_PORT12_Pos) /*!< GPIO_PORT PIN2: PORT12 Mask */ -#define GPIO_PORT_PIN2_PORT13_Pos 13 /*!< GPIO_PORT PIN2: PORT13 Position */ -#define GPIO_PORT_PIN2_PORT13_Msk (0x01UL << GPIO_PORT_PIN2_PORT13_Pos) /*!< GPIO_PORT PIN2: PORT13 Mask */ -#define GPIO_PORT_PIN2_PORT14_Pos 14 /*!< GPIO_PORT PIN2: PORT14 Position */ -#define GPIO_PORT_PIN2_PORT14_Msk (0x01UL << GPIO_PORT_PIN2_PORT14_Pos) /*!< GPIO_PORT PIN2: PORT14 Mask */ -#define GPIO_PORT_PIN2_PORT15_Pos 15 /*!< GPIO_PORT PIN2: PORT15 Position */ -#define GPIO_PORT_PIN2_PORT15_Msk (0x01UL << GPIO_PORT_PIN2_PORT15_Pos) /*!< GPIO_PORT PIN2: PORT15 Mask */ -#define GPIO_PORT_PIN2_PORT16_Pos 16 /*!< GPIO_PORT PIN2: PORT16 Position */ -#define GPIO_PORT_PIN2_PORT16_Msk (0x01UL << GPIO_PORT_PIN2_PORT16_Pos) /*!< GPIO_PORT PIN2: PORT16 Mask */ -#define GPIO_PORT_PIN2_PORT17_Pos 17 /*!< GPIO_PORT PIN2: PORT17 Position */ -#define GPIO_PORT_PIN2_PORT17_Msk (0x01UL << GPIO_PORT_PIN2_PORT17_Pos) /*!< GPIO_PORT PIN2: PORT17 Mask */ -#define GPIO_PORT_PIN2_PORT18_Pos 18 /*!< GPIO_PORT PIN2: PORT18 Position */ -#define GPIO_PORT_PIN2_PORT18_Msk (0x01UL << GPIO_PORT_PIN2_PORT18_Pos) /*!< GPIO_PORT PIN2: PORT18 Mask */ -#define GPIO_PORT_PIN2_PORT19_Pos 19 /*!< GPIO_PORT PIN2: PORT19 Position */ -#define GPIO_PORT_PIN2_PORT19_Msk (0x01UL << GPIO_PORT_PIN2_PORT19_Pos) /*!< GPIO_PORT PIN2: PORT19 Mask */ -#define GPIO_PORT_PIN2_PORT20_Pos 20 /*!< GPIO_PORT PIN2: PORT20 Position */ -#define GPIO_PORT_PIN2_PORT20_Msk (0x01UL << GPIO_PORT_PIN2_PORT20_Pos) /*!< GPIO_PORT PIN2: PORT20 Mask */ -#define GPIO_PORT_PIN2_PORT21_Pos 21 /*!< GPIO_PORT PIN2: PORT21 Position */ -#define GPIO_PORT_PIN2_PORT21_Msk (0x01UL << GPIO_PORT_PIN2_PORT21_Pos) /*!< GPIO_PORT PIN2: PORT21 Mask */ -#define GPIO_PORT_PIN2_PORT22_Pos 22 /*!< GPIO_PORT PIN2: PORT22 Position */ -#define GPIO_PORT_PIN2_PORT22_Msk (0x01UL << GPIO_PORT_PIN2_PORT22_Pos) /*!< GPIO_PORT PIN2: PORT22 Mask */ -#define GPIO_PORT_PIN2_PORT23_Pos 23 /*!< GPIO_PORT PIN2: PORT23 Position */ -#define GPIO_PORT_PIN2_PORT23_Msk (0x01UL << GPIO_PORT_PIN2_PORT23_Pos) /*!< GPIO_PORT PIN2: PORT23 Mask */ -#define GPIO_PORT_PIN2_PORT24_Pos 24 /*!< GPIO_PORT PIN2: PORT24 Position */ -#define GPIO_PORT_PIN2_PORT24_Msk (0x01UL << GPIO_PORT_PIN2_PORT24_Pos) /*!< GPIO_PORT PIN2: PORT24 Mask */ -#define GPIO_PORT_PIN2_PORT25_Pos 25 /*!< GPIO_PORT PIN2: PORT25 Position */ -#define GPIO_PORT_PIN2_PORT25_Msk (0x01UL << GPIO_PORT_PIN2_PORT25_Pos) /*!< GPIO_PORT PIN2: PORT25 Mask */ -#define GPIO_PORT_PIN2_PORT26_Pos 26 /*!< GPIO_PORT PIN2: PORT26 Position */ -#define GPIO_PORT_PIN2_PORT26_Msk (0x01UL << GPIO_PORT_PIN2_PORT26_Pos) /*!< GPIO_PORT PIN2: PORT26 Mask */ -#define GPIO_PORT_PIN2_PORT27_Pos 27 /*!< GPIO_PORT PIN2: PORT27 Position */ -#define GPIO_PORT_PIN2_PORT27_Msk (0x01UL << GPIO_PORT_PIN2_PORT27_Pos) /*!< GPIO_PORT PIN2: PORT27 Mask */ -#define GPIO_PORT_PIN2_PORT28_Pos 28 /*!< GPIO_PORT PIN2: PORT28 Position */ -#define GPIO_PORT_PIN2_PORT28_Msk (0x01UL << GPIO_PORT_PIN2_PORT28_Pos) /*!< GPIO_PORT PIN2: PORT28 Mask */ -#define GPIO_PORT_PIN2_PORT29_Pos 29 /*!< GPIO_PORT PIN2: PORT29 Position */ -#define GPIO_PORT_PIN2_PORT29_Msk (0x01UL << GPIO_PORT_PIN2_PORT29_Pos) /*!< GPIO_PORT PIN2: PORT29 Mask */ -#define GPIO_PORT_PIN2_PORT30_Pos 30 /*!< GPIO_PORT PIN2: PORT30 Position */ -#define GPIO_PORT_PIN2_PORT30_Msk (0x01UL << GPIO_PORT_PIN2_PORT30_Pos) /*!< GPIO_PORT PIN2: PORT30 Mask */ -#define GPIO_PORT_PIN2_PORT31_Pos 31 /*!< GPIO_PORT PIN2: PORT31 Position */ -#define GPIO_PORT_PIN2_PORT31_Msk (0x01UL << GPIO_PORT_PIN2_PORT31_Pos) /*!< GPIO_PORT PIN2: PORT31 Mask */ - -// ------------------------------------- GPIO_PORT_PIN3 ----------------------------------------- -#define GPIO_PORT_PIN3_PORT0_Pos 0 /*!< GPIO_PORT PIN3: PORT0 Position */ -#define GPIO_PORT_PIN3_PORT0_Msk (0x01UL << GPIO_PORT_PIN3_PORT0_Pos) /*!< GPIO_PORT PIN3: PORT0 Mask */ -#define GPIO_PORT_PIN3_PORT1_Pos 1 /*!< GPIO_PORT PIN3: PORT1 Position */ -#define GPIO_PORT_PIN3_PORT1_Msk (0x01UL << GPIO_PORT_PIN3_PORT1_Pos) /*!< GPIO_PORT PIN3: PORT1 Mask */ -#define GPIO_PORT_PIN3_PORT2_Pos 2 /*!< GPIO_PORT PIN3: PORT2 Position */ -#define GPIO_PORT_PIN3_PORT2_Msk (0x01UL << GPIO_PORT_PIN3_PORT2_Pos) /*!< GPIO_PORT PIN3: PORT2 Mask */ -#define GPIO_PORT_PIN3_PORT3_Pos 3 /*!< GPIO_PORT PIN3: PORT3 Position */ -#define GPIO_PORT_PIN3_PORT3_Msk (0x01UL << GPIO_PORT_PIN3_PORT3_Pos) /*!< GPIO_PORT PIN3: PORT3 Mask */ -#define GPIO_PORT_PIN3_PORT4_Pos 4 /*!< GPIO_PORT PIN3: PORT4 Position */ -#define GPIO_PORT_PIN3_PORT4_Msk (0x01UL << GPIO_PORT_PIN3_PORT4_Pos) /*!< GPIO_PORT PIN3: PORT4 Mask */ -#define GPIO_PORT_PIN3_PORT5_Pos 5 /*!< GPIO_PORT PIN3: PORT5 Position */ -#define GPIO_PORT_PIN3_PORT5_Msk (0x01UL << GPIO_PORT_PIN3_PORT5_Pos) /*!< GPIO_PORT PIN3: PORT5 Mask */ -#define GPIO_PORT_PIN3_PORT6_Pos 6 /*!< GPIO_PORT PIN3: PORT6 Position */ -#define GPIO_PORT_PIN3_PORT6_Msk (0x01UL << GPIO_PORT_PIN3_PORT6_Pos) /*!< GPIO_PORT PIN3: PORT6 Mask */ -#define GPIO_PORT_PIN3_PORT7_Pos 7 /*!< GPIO_PORT PIN3: PORT7 Position */ -#define GPIO_PORT_PIN3_PORT7_Msk (0x01UL << GPIO_PORT_PIN3_PORT7_Pos) /*!< GPIO_PORT PIN3: PORT7 Mask */ -#define GPIO_PORT_PIN3_PORT8_Pos 8 /*!< GPIO_PORT PIN3: PORT8 Position */ -#define GPIO_PORT_PIN3_PORT8_Msk (0x01UL << GPIO_PORT_PIN3_PORT8_Pos) /*!< GPIO_PORT PIN3: PORT8 Mask */ -#define GPIO_PORT_PIN3_PORT9_Pos 9 /*!< GPIO_PORT PIN3: PORT9 Position */ -#define GPIO_PORT_PIN3_PORT9_Msk (0x01UL << GPIO_PORT_PIN3_PORT9_Pos) /*!< GPIO_PORT PIN3: PORT9 Mask */ -#define GPIO_PORT_PIN3_PORT10_Pos 10 /*!< GPIO_PORT PIN3: PORT10 Position */ -#define GPIO_PORT_PIN3_PORT10_Msk (0x01UL << GPIO_PORT_PIN3_PORT10_Pos) /*!< GPIO_PORT PIN3: PORT10 Mask */ -#define GPIO_PORT_PIN3_PORT11_Pos 11 /*!< GPIO_PORT PIN3: PORT11 Position */ -#define GPIO_PORT_PIN3_PORT11_Msk (0x01UL << GPIO_PORT_PIN3_PORT11_Pos) /*!< GPIO_PORT PIN3: PORT11 Mask */ -#define GPIO_PORT_PIN3_PORT12_Pos 12 /*!< GPIO_PORT PIN3: PORT12 Position */ -#define GPIO_PORT_PIN3_PORT12_Msk (0x01UL << GPIO_PORT_PIN3_PORT12_Pos) /*!< GPIO_PORT PIN3: PORT12 Mask */ -#define GPIO_PORT_PIN3_PORT13_Pos 13 /*!< GPIO_PORT PIN3: PORT13 Position */ -#define GPIO_PORT_PIN3_PORT13_Msk (0x01UL << GPIO_PORT_PIN3_PORT13_Pos) /*!< GPIO_PORT PIN3: PORT13 Mask */ -#define GPIO_PORT_PIN3_PORT14_Pos 14 /*!< GPIO_PORT PIN3: PORT14 Position */ -#define GPIO_PORT_PIN3_PORT14_Msk (0x01UL << GPIO_PORT_PIN3_PORT14_Pos) /*!< GPIO_PORT PIN3: PORT14 Mask */ -#define GPIO_PORT_PIN3_PORT15_Pos 15 /*!< GPIO_PORT PIN3: PORT15 Position */ -#define GPIO_PORT_PIN3_PORT15_Msk (0x01UL << GPIO_PORT_PIN3_PORT15_Pos) /*!< GPIO_PORT PIN3: PORT15 Mask */ -#define GPIO_PORT_PIN3_PORT16_Pos 16 /*!< GPIO_PORT PIN3: PORT16 Position */ -#define GPIO_PORT_PIN3_PORT16_Msk (0x01UL << GPIO_PORT_PIN3_PORT16_Pos) /*!< GPIO_PORT PIN3: PORT16 Mask */ -#define GPIO_PORT_PIN3_PORT17_Pos 17 /*!< GPIO_PORT PIN3: PORT17 Position */ -#define GPIO_PORT_PIN3_PORT17_Msk (0x01UL << GPIO_PORT_PIN3_PORT17_Pos) /*!< GPIO_PORT PIN3: PORT17 Mask */ -#define GPIO_PORT_PIN3_PORT18_Pos 18 /*!< GPIO_PORT PIN3: PORT18 Position */ -#define GPIO_PORT_PIN3_PORT18_Msk (0x01UL << GPIO_PORT_PIN3_PORT18_Pos) /*!< GPIO_PORT PIN3: PORT18 Mask */ -#define GPIO_PORT_PIN3_PORT19_Pos 19 /*!< GPIO_PORT PIN3: PORT19 Position */ -#define GPIO_PORT_PIN3_PORT19_Msk (0x01UL << GPIO_PORT_PIN3_PORT19_Pos) /*!< GPIO_PORT PIN3: PORT19 Mask */ -#define GPIO_PORT_PIN3_PORT20_Pos 20 /*!< GPIO_PORT PIN3: PORT20 Position */ -#define GPIO_PORT_PIN3_PORT20_Msk (0x01UL << GPIO_PORT_PIN3_PORT20_Pos) /*!< GPIO_PORT PIN3: PORT20 Mask */ -#define GPIO_PORT_PIN3_PORT21_Pos 21 /*!< GPIO_PORT PIN3: PORT21 Position */ -#define GPIO_PORT_PIN3_PORT21_Msk (0x01UL << GPIO_PORT_PIN3_PORT21_Pos) /*!< GPIO_PORT PIN3: PORT21 Mask */ -#define GPIO_PORT_PIN3_PORT22_Pos 22 /*!< GPIO_PORT PIN3: PORT22 Position */ -#define GPIO_PORT_PIN3_PORT22_Msk (0x01UL << GPIO_PORT_PIN3_PORT22_Pos) /*!< GPIO_PORT PIN3: PORT22 Mask */ -#define GPIO_PORT_PIN3_PORT23_Pos 23 /*!< GPIO_PORT PIN3: PORT23 Position */ -#define GPIO_PORT_PIN3_PORT23_Msk (0x01UL << GPIO_PORT_PIN3_PORT23_Pos) /*!< GPIO_PORT PIN3: PORT23 Mask */ -#define GPIO_PORT_PIN3_PORT24_Pos 24 /*!< GPIO_PORT PIN3: PORT24 Position */ -#define GPIO_PORT_PIN3_PORT24_Msk (0x01UL << GPIO_PORT_PIN3_PORT24_Pos) /*!< GPIO_PORT PIN3: PORT24 Mask */ -#define GPIO_PORT_PIN3_PORT25_Pos 25 /*!< GPIO_PORT PIN3: PORT25 Position */ -#define GPIO_PORT_PIN3_PORT25_Msk (0x01UL << GPIO_PORT_PIN3_PORT25_Pos) /*!< GPIO_PORT PIN3: PORT25 Mask */ -#define GPIO_PORT_PIN3_PORT26_Pos 26 /*!< GPIO_PORT PIN3: PORT26 Position */ -#define GPIO_PORT_PIN3_PORT26_Msk (0x01UL << GPIO_PORT_PIN3_PORT26_Pos) /*!< GPIO_PORT PIN3: PORT26 Mask */ -#define GPIO_PORT_PIN3_PORT27_Pos 27 /*!< GPIO_PORT PIN3: PORT27 Position */ -#define GPIO_PORT_PIN3_PORT27_Msk (0x01UL << GPIO_PORT_PIN3_PORT27_Pos) /*!< GPIO_PORT PIN3: PORT27 Mask */ -#define GPIO_PORT_PIN3_PORT28_Pos 28 /*!< GPIO_PORT PIN3: PORT28 Position */ -#define GPIO_PORT_PIN3_PORT28_Msk (0x01UL << GPIO_PORT_PIN3_PORT28_Pos) /*!< GPIO_PORT PIN3: PORT28 Mask */ -#define GPIO_PORT_PIN3_PORT29_Pos 29 /*!< GPIO_PORT PIN3: PORT29 Position */ -#define GPIO_PORT_PIN3_PORT29_Msk (0x01UL << GPIO_PORT_PIN3_PORT29_Pos) /*!< GPIO_PORT PIN3: PORT29 Mask */ -#define GPIO_PORT_PIN3_PORT30_Pos 30 /*!< GPIO_PORT PIN3: PORT30 Position */ -#define GPIO_PORT_PIN3_PORT30_Msk (0x01UL << GPIO_PORT_PIN3_PORT30_Pos) /*!< GPIO_PORT PIN3: PORT30 Mask */ -#define GPIO_PORT_PIN3_PORT31_Pos 31 /*!< GPIO_PORT PIN3: PORT31 Position */ -#define GPIO_PORT_PIN3_PORT31_Msk (0x01UL << GPIO_PORT_PIN3_PORT31_Pos) /*!< GPIO_PORT PIN3: PORT31 Mask */ - -// ------------------------------------- GPIO_PORT_PIN4 ----------------------------------------- -#define GPIO_PORT_PIN4_PORT0_Pos 0 /*!< GPIO_PORT PIN4: PORT0 Position */ -#define GPIO_PORT_PIN4_PORT0_Msk (0x01UL << GPIO_PORT_PIN4_PORT0_Pos) /*!< GPIO_PORT PIN4: PORT0 Mask */ -#define GPIO_PORT_PIN4_PORT1_Pos 1 /*!< GPIO_PORT PIN4: PORT1 Position */ -#define GPIO_PORT_PIN4_PORT1_Msk (0x01UL << GPIO_PORT_PIN4_PORT1_Pos) /*!< GPIO_PORT PIN4: PORT1 Mask */ -#define GPIO_PORT_PIN4_PORT2_Pos 2 /*!< GPIO_PORT PIN4: PORT2 Position */ -#define GPIO_PORT_PIN4_PORT2_Msk (0x01UL << GPIO_PORT_PIN4_PORT2_Pos) /*!< GPIO_PORT PIN4: PORT2 Mask */ -#define GPIO_PORT_PIN4_PORT3_Pos 3 /*!< GPIO_PORT PIN4: PORT3 Position */ -#define GPIO_PORT_PIN4_PORT3_Msk (0x01UL << GPIO_PORT_PIN4_PORT3_Pos) /*!< GPIO_PORT PIN4: PORT3 Mask */ -#define GPIO_PORT_PIN4_PORT4_Pos 4 /*!< GPIO_PORT PIN4: PORT4 Position */ -#define GPIO_PORT_PIN4_PORT4_Msk (0x01UL << GPIO_PORT_PIN4_PORT4_Pos) /*!< GPIO_PORT PIN4: PORT4 Mask */ -#define GPIO_PORT_PIN4_PORT5_Pos 5 /*!< GPIO_PORT PIN4: PORT5 Position */ -#define GPIO_PORT_PIN4_PORT5_Msk (0x01UL << GPIO_PORT_PIN4_PORT5_Pos) /*!< GPIO_PORT PIN4: PORT5 Mask */ -#define GPIO_PORT_PIN4_PORT6_Pos 6 /*!< GPIO_PORT PIN4: PORT6 Position */ -#define GPIO_PORT_PIN4_PORT6_Msk (0x01UL << GPIO_PORT_PIN4_PORT6_Pos) /*!< GPIO_PORT PIN4: PORT6 Mask */ -#define GPIO_PORT_PIN4_PORT7_Pos 7 /*!< GPIO_PORT PIN4: PORT7 Position */ -#define GPIO_PORT_PIN4_PORT7_Msk (0x01UL << GPIO_PORT_PIN4_PORT7_Pos) /*!< GPIO_PORT PIN4: PORT7 Mask */ -#define GPIO_PORT_PIN4_PORT8_Pos 8 /*!< GPIO_PORT PIN4: PORT8 Position */ -#define GPIO_PORT_PIN4_PORT8_Msk (0x01UL << GPIO_PORT_PIN4_PORT8_Pos) /*!< GPIO_PORT PIN4: PORT8 Mask */ -#define GPIO_PORT_PIN4_PORT9_Pos 9 /*!< GPIO_PORT PIN4: PORT9 Position */ -#define GPIO_PORT_PIN4_PORT9_Msk (0x01UL << GPIO_PORT_PIN4_PORT9_Pos) /*!< GPIO_PORT PIN4: PORT9 Mask */ -#define GPIO_PORT_PIN4_PORT10_Pos 10 /*!< GPIO_PORT PIN4: PORT10 Position */ -#define GPIO_PORT_PIN4_PORT10_Msk (0x01UL << GPIO_PORT_PIN4_PORT10_Pos) /*!< GPIO_PORT PIN4: PORT10 Mask */ -#define GPIO_PORT_PIN4_PORT11_Pos 11 /*!< GPIO_PORT PIN4: PORT11 Position */ -#define GPIO_PORT_PIN4_PORT11_Msk (0x01UL << GPIO_PORT_PIN4_PORT11_Pos) /*!< GPIO_PORT PIN4: PORT11 Mask */ -#define GPIO_PORT_PIN4_PORT12_Pos 12 /*!< GPIO_PORT PIN4: PORT12 Position */ -#define GPIO_PORT_PIN4_PORT12_Msk (0x01UL << GPIO_PORT_PIN4_PORT12_Pos) /*!< GPIO_PORT PIN4: PORT12 Mask */ -#define GPIO_PORT_PIN4_PORT13_Pos 13 /*!< GPIO_PORT PIN4: PORT13 Position */ -#define GPIO_PORT_PIN4_PORT13_Msk (0x01UL << GPIO_PORT_PIN4_PORT13_Pos) /*!< GPIO_PORT PIN4: PORT13 Mask */ -#define GPIO_PORT_PIN4_PORT14_Pos 14 /*!< GPIO_PORT PIN4: PORT14 Position */ -#define GPIO_PORT_PIN4_PORT14_Msk (0x01UL << GPIO_PORT_PIN4_PORT14_Pos) /*!< GPIO_PORT PIN4: PORT14 Mask */ -#define GPIO_PORT_PIN4_PORT15_Pos 15 /*!< GPIO_PORT PIN4: PORT15 Position */ -#define GPIO_PORT_PIN4_PORT15_Msk (0x01UL << GPIO_PORT_PIN4_PORT15_Pos) /*!< GPIO_PORT PIN4: PORT15 Mask */ -#define GPIO_PORT_PIN4_PORT16_Pos 16 /*!< GPIO_PORT PIN4: PORT16 Position */ -#define GPIO_PORT_PIN4_PORT16_Msk (0x01UL << GPIO_PORT_PIN4_PORT16_Pos) /*!< GPIO_PORT PIN4: PORT16 Mask */ -#define GPIO_PORT_PIN4_PORT17_Pos 17 /*!< GPIO_PORT PIN4: PORT17 Position */ -#define GPIO_PORT_PIN4_PORT17_Msk (0x01UL << GPIO_PORT_PIN4_PORT17_Pos) /*!< GPIO_PORT PIN4: PORT17 Mask */ -#define GPIO_PORT_PIN4_PORT18_Pos 18 /*!< GPIO_PORT PIN4: PORT18 Position */ -#define GPIO_PORT_PIN4_PORT18_Msk (0x01UL << GPIO_PORT_PIN4_PORT18_Pos) /*!< GPIO_PORT PIN4: PORT18 Mask */ -#define GPIO_PORT_PIN4_PORT19_Pos 19 /*!< GPIO_PORT PIN4: PORT19 Position */ -#define GPIO_PORT_PIN4_PORT19_Msk (0x01UL << GPIO_PORT_PIN4_PORT19_Pos) /*!< GPIO_PORT PIN4: PORT19 Mask */ -#define GPIO_PORT_PIN4_PORT20_Pos 20 /*!< GPIO_PORT PIN4: PORT20 Position */ -#define GPIO_PORT_PIN4_PORT20_Msk (0x01UL << GPIO_PORT_PIN4_PORT20_Pos) /*!< GPIO_PORT PIN4: PORT20 Mask */ -#define GPIO_PORT_PIN4_PORT21_Pos 21 /*!< GPIO_PORT PIN4: PORT21 Position */ -#define GPIO_PORT_PIN4_PORT21_Msk (0x01UL << GPIO_PORT_PIN4_PORT21_Pos) /*!< GPIO_PORT PIN4: PORT21 Mask */ -#define GPIO_PORT_PIN4_PORT22_Pos 22 /*!< GPIO_PORT PIN4: PORT22 Position */ -#define GPIO_PORT_PIN4_PORT22_Msk (0x01UL << GPIO_PORT_PIN4_PORT22_Pos) /*!< GPIO_PORT PIN4: PORT22 Mask */ -#define GPIO_PORT_PIN4_PORT23_Pos 23 /*!< GPIO_PORT PIN4: PORT23 Position */ -#define GPIO_PORT_PIN4_PORT23_Msk (0x01UL << GPIO_PORT_PIN4_PORT23_Pos) /*!< GPIO_PORT PIN4: PORT23 Mask */ -#define GPIO_PORT_PIN4_PORT24_Pos 24 /*!< GPIO_PORT PIN4: PORT24 Position */ -#define GPIO_PORT_PIN4_PORT24_Msk (0x01UL << GPIO_PORT_PIN4_PORT24_Pos) /*!< GPIO_PORT PIN4: PORT24 Mask */ -#define GPIO_PORT_PIN4_PORT25_Pos 25 /*!< GPIO_PORT PIN4: PORT25 Position */ -#define GPIO_PORT_PIN4_PORT25_Msk (0x01UL << GPIO_PORT_PIN4_PORT25_Pos) /*!< GPIO_PORT PIN4: PORT25 Mask */ -#define GPIO_PORT_PIN4_PORT26_Pos 26 /*!< GPIO_PORT PIN4: PORT26 Position */ -#define GPIO_PORT_PIN4_PORT26_Msk (0x01UL << GPIO_PORT_PIN4_PORT26_Pos) /*!< GPIO_PORT PIN4: PORT26 Mask */ -#define GPIO_PORT_PIN4_PORT27_Pos 27 /*!< GPIO_PORT PIN4: PORT27 Position */ -#define GPIO_PORT_PIN4_PORT27_Msk (0x01UL << GPIO_PORT_PIN4_PORT27_Pos) /*!< GPIO_PORT PIN4: PORT27 Mask */ -#define GPIO_PORT_PIN4_PORT28_Pos 28 /*!< GPIO_PORT PIN4: PORT28 Position */ -#define GPIO_PORT_PIN4_PORT28_Msk (0x01UL << GPIO_PORT_PIN4_PORT28_Pos) /*!< GPIO_PORT PIN4: PORT28 Mask */ -#define GPIO_PORT_PIN4_PORT29_Pos 29 /*!< GPIO_PORT PIN4: PORT29 Position */ -#define GPIO_PORT_PIN4_PORT29_Msk (0x01UL << GPIO_PORT_PIN4_PORT29_Pos) /*!< GPIO_PORT PIN4: PORT29 Mask */ -#define GPIO_PORT_PIN4_PORT30_Pos 30 /*!< GPIO_PORT PIN4: PORT30 Position */ -#define GPIO_PORT_PIN4_PORT30_Msk (0x01UL << GPIO_PORT_PIN4_PORT30_Pos) /*!< GPIO_PORT PIN4: PORT30 Mask */ -#define GPIO_PORT_PIN4_PORT31_Pos 31 /*!< GPIO_PORT PIN4: PORT31 Position */ -#define GPIO_PORT_PIN4_PORT31_Msk (0x01UL << GPIO_PORT_PIN4_PORT31_Pos) /*!< GPIO_PORT PIN4: PORT31 Mask */ - -// ------------------------------------- GPIO_PORT_PIN5 ----------------------------------------- -#define GPIO_PORT_PIN5_PORT0_Pos 0 /*!< GPIO_PORT PIN5: PORT0 Position */ -#define GPIO_PORT_PIN5_PORT0_Msk (0x01UL << GPIO_PORT_PIN5_PORT0_Pos) /*!< GPIO_PORT PIN5: PORT0 Mask */ -#define GPIO_PORT_PIN5_PORT1_Pos 1 /*!< GPIO_PORT PIN5: PORT1 Position */ -#define GPIO_PORT_PIN5_PORT1_Msk (0x01UL << GPIO_PORT_PIN5_PORT1_Pos) /*!< GPIO_PORT PIN5: PORT1 Mask */ -#define GPIO_PORT_PIN5_PORT2_Pos 2 /*!< GPIO_PORT PIN5: PORT2 Position */ -#define GPIO_PORT_PIN5_PORT2_Msk (0x01UL << GPIO_PORT_PIN5_PORT2_Pos) /*!< GPIO_PORT PIN5: PORT2 Mask */ -#define GPIO_PORT_PIN5_PORT3_Pos 3 /*!< GPIO_PORT PIN5: PORT3 Position */ -#define GPIO_PORT_PIN5_PORT3_Msk (0x01UL << GPIO_PORT_PIN5_PORT3_Pos) /*!< GPIO_PORT PIN5: PORT3 Mask */ -#define GPIO_PORT_PIN5_PORT4_Pos 4 /*!< GPIO_PORT PIN5: PORT4 Position */ -#define GPIO_PORT_PIN5_PORT4_Msk (0x01UL << GPIO_PORT_PIN5_PORT4_Pos) /*!< GPIO_PORT PIN5: PORT4 Mask */ -#define GPIO_PORT_PIN5_PORT5_Pos 5 /*!< GPIO_PORT PIN5: PORT5 Position */ -#define GPIO_PORT_PIN5_PORT5_Msk (0x01UL << GPIO_PORT_PIN5_PORT5_Pos) /*!< GPIO_PORT PIN5: PORT5 Mask */ -#define GPIO_PORT_PIN5_PORT6_Pos 6 /*!< GPIO_PORT PIN5: PORT6 Position */ -#define GPIO_PORT_PIN5_PORT6_Msk (0x01UL << GPIO_PORT_PIN5_PORT6_Pos) /*!< GPIO_PORT PIN5: PORT6 Mask */ -#define GPIO_PORT_PIN5_PORT7_Pos 7 /*!< GPIO_PORT PIN5: PORT7 Position */ -#define GPIO_PORT_PIN5_PORT7_Msk (0x01UL << GPIO_PORT_PIN5_PORT7_Pos) /*!< GPIO_PORT PIN5: PORT7 Mask */ -#define GPIO_PORT_PIN5_PORT8_Pos 8 /*!< GPIO_PORT PIN5: PORT8 Position */ -#define GPIO_PORT_PIN5_PORT8_Msk (0x01UL << GPIO_PORT_PIN5_PORT8_Pos) /*!< GPIO_PORT PIN5: PORT8 Mask */ -#define GPIO_PORT_PIN5_PORT9_Pos 9 /*!< GPIO_PORT PIN5: PORT9 Position */ -#define GPIO_PORT_PIN5_PORT9_Msk (0x01UL << GPIO_PORT_PIN5_PORT9_Pos) /*!< GPIO_PORT PIN5: PORT9 Mask */ -#define GPIO_PORT_PIN5_PORT10_Pos 10 /*!< GPIO_PORT PIN5: PORT10 Position */ -#define GPIO_PORT_PIN5_PORT10_Msk (0x01UL << GPIO_PORT_PIN5_PORT10_Pos) /*!< GPIO_PORT PIN5: PORT10 Mask */ -#define GPIO_PORT_PIN5_PORT11_Pos 11 /*!< GPIO_PORT PIN5: PORT11 Position */ -#define GPIO_PORT_PIN5_PORT11_Msk (0x01UL << GPIO_PORT_PIN5_PORT11_Pos) /*!< GPIO_PORT PIN5: PORT11 Mask */ -#define GPIO_PORT_PIN5_PORT12_Pos 12 /*!< GPIO_PORT PIN5: PORT12 Position */ -#define GPIO_PORT_PIN5_PORT12_Msk (0x01UL << GPIO_PORT_PIN5_PORT12_Pos) /*!< GPIO_PORT PIN5: PORT12 Mask */ -#define GPIO_PORT_PIN5_PORT13_Pos 13 /*!< GPIO_PORT PIN5: PORT13 Position */ -#define GPIO_PORT_PIN5_PORT13_Msk (0x01UL << GPIO_PORT_PIN5_PORT13_Pos) /*!< GPIO_PORT PIN5: PORT13 Mask */ -#define GPIO_PORT_PIN5_PORT14_Pos 14 /*!< GPIO_PORT PIN5: PORT14 Position */ -#define GPIO_PORT_PIN5_PORT14_Msk (0x01UL << GPIO_PORT_PIN5_PORT14_Pos) /*!< GPIO_PORT PIN5: PORT14 Mask */ -#define GPIO_PORT_PIN5_PORT15_Pos 15 /*!< GPIO_PORT PIN5: PORT15 Position */ -#define GPIO_PORT_PIN5_PORT15_Msk (0x01UL << GPIO_PORT_PIN5_PORT15_Pos) /*!< GPIO_PORT PIN5: PORT15 Mask */ -#define GPIO_PORT_PIN5_PORT16_Pos 16 /*!< GPIO_PORT PIN5: PORT16 Position */ -#define GPIO_PORT_PIN5_PORT16_Msk (0x01UL << GPIO_PORT_PIN5_PORT16_Pos) /*!< GPIO_PORT PIN5: PORT16 Mask */ -#define GPIO_PORT_PIN5_PORT17_Pos 17 /*!< GPIO_PORT PIN5: PORT17 Position */ -#define GPIO_PORT_PIN5_PORT17_Msk (0x01UL << GPIO_PORT_PIN5_PORT17_Pos) /*!< GPIO_PORT PIN5: PORT17 Mask */ -#define GPIO_PORT_PIN5_PORT18_Pos 18 /*!< GPIO_PORT PIN5: PORT18 Position */ -#define GPIO_PORT_PIN5_PORT18_Msk (0x01UL << GPIO_PORT_PIN5_PORT18_Pos) /*!< GPIO_PORT PIN5: PORT18 Mask */ -#define GPIO_PORT_PIN5_PORT19_Pos 19 /*!< GPIO_PORT PIN5: PORT19 Position */ -#define GPIO_PORT_PIN5_PORT19_Msk (0x01UL << GPIO_PORT_PIN5_PORT19_Pos) /*!< GPIO_PORT PIN5: PORT19 Mask */ -#define GPIO_PORT_PIN5_PORT20_Pos 20 /*!< GPIO_PORT PIN5: PORT20 Position */ -#define GPIO_PORT_PIN5_PORT20_Msk (0x01UL << GPIO_PORT_PIN5_PORT20_Pos) /*!< GPIO_PORT PIN5: PORT20 Mask */ -#define GPIO_PORT_PIN5_PORT21_Pos 21 /*!< GPIO_PORT PIN5: PORT21 Position */ -#define GPIO_PORT_PIN5_PORT21_Msk (0x01UL << GPIO_PORT_PIN5_PORT21_Pos) /*!< GPIO_PORT PIN5: PORT21 Mask */ -#define GPIO_PORT_PIN5_PORT22_Pos 22 /*!< GPIO_PORT PIN5: PORT22 Position */ -#define GPIO_PORT_PIN5_PORT22_Msk (0x01UL << GPIO_PORT_PIN5_PORT22_Pos) /*!< GPIO_PORT PIN5: PORT22 Mask */ -#define GPIO_PORT_PIN5_PORT23_Pos 23 /*!< GPIO_PORT PIN5: PORT23 Position */ -#define GPIO_PORT_PIN5_PORT23_Msk (0x01UL << GPIO_PORT_PIN5_PORT23_Pos) /*!< GPIO_PORT PIN5: PORT23 Mask */ -#define GPIO_PORT_PIN5_PORT24_Pos 24 /*!< GPIO_PORT PIN5: PORT24 Position */ -#define GPIO_PORT_PIN5_PORT24_Msk (0x01UL << GPIO_PORT_PIN5_PORT24_Pos) /*!< GPIO_PORT PIN5: PORT24 Mask */ -#define GPIO_PORT_PIN5_PORT25_Pos 25 /*!< GPIO_PORT PIN5: PORT25 Position */ -#define GPIO_PORT_PIN5_PORT25_Msk (0x01UL << GPIO_PORT_PIN5_PORT25_Pos) /*!< GPIO_PORT PIN5: PORT25 Mask */ -#define GPIO_PORT_PIN5_PORT26_Pos 26 /*!< GPIO_PORT PIN5: PORT26 Position */ -#define GPIO_PORT_PIN5_PORT26_Msk (0x01UL << GPIO_PORT_PIN5_PORT26_Pos) /*!< GPIO_PORT PIN5: PORT26 Mask */ -#define GPIO_PORT_PIN5_PORT27_Pos 27 /*!< GPIO_PORT PIN5: PORT27 Position */ -#define GPIO_PORT_PIN5_PORT27_Msk (0x01UL << GPIO_PORT_PIN5_PORT27_Pos) /*!< GPIO_PORT PIN5: PORT27 Mask */ -#define GPIO_PORT_PIN5_PORT28_Pos 28 /*!< GPIO_PORT PIN5: PORT28 Position */ -#define GPIO_PORT_PIN5_PORT28_Msk (0x01UL << GPIO_PORT_PIN5_PORT28_Pos) /*!< GPIO_PORT PIN5: PORT28 Mask */ -#define GPIO_PORT_PIN5_PORT29_Pos 29 /*!< GPIO_PORT PIN5: PORT29 Position */ -#define GPIO_PORT_PIN5_PORT29_Msk (0x01UL << GPIO_PORT_PIN5_PORT29_Pos) /*!< GPIO_PORT PIN5: PORT29 Mask */ -#define GPIO_PORT_PIN5_PORT30_Pos 30 /*!< GPIO_PORT PIN5: PORT30 Position */ -#define GPIO_PORT_PIN5_PORT30_Msk (0x01UL << GPIO_PORT_PIN5_PORT30_Pos) /*!< GPIO_PORT PIN5: PORT30 Mask */ -#define GPIO_PORT_PIN5_PORT31_Pos 31 /*!< GPIO_PORT PIN5: PORT31 Position */ -#define GPIO_PORT_PIN5_PORT31_Msk (0x01UL << GPIO_PORT_PIN5_PORT31_Pos) /*!< GPIO_PORT PIN5: PORT31 Mask */ - -// ------------------------------------- GPIO_PORT_PIN6 ----------------------------------------- -#define GPIO_PORT_PIN6_PORT0_Pos 0 /*!< GPIO_PORT PIN6: PORT0 Position */ -#define GPIO_PORT_PIN6_PORT0_Msk (0x01UL << GPIO_PORT_PIN6_PORT0_Pos) /*!< GPIO_PORT PIN6: PORT0 Mask */ -#define GPIO_PORT_PIN6_PORT1_Pos 1 /*!< GPIO_PORT PIN6: PORT1 Position */ -#define GPIO_PORT_PIN6_PORT1_Msk (0x01UL << GPIO_PORT_PIN6_PORT1_Pos) /*!< GPIO_PORT PIN6: PORT1 Mask */ -#define GPIO_PORT_PIN6_PORT2_Pos 2 /*!< GPIO_PORT PIN6: PORT2 Position */ -#define GPIO_PORT_PIN6_PORT2_Msk (0x01UL << GPIO_PORT_PIN6_PORT2_Pos) /*!< GPIO_PORT PIN6: PORT2 Mask */ -#define GPIO_PORT_PIN6_PORT3_Pos 3 /*!< GPIO_PORT PIN6: PORT3 Position */ -#define GPIO_PORT_PIN6_PORT3_Msk (0x01UL << GPIO_PORT_PIN6_PORT3_Pos) /*!< GPIO_PORT PIN6: PORT3 Mask */ -#define GPIO_PORT_PIN6_PORT4_Pos 4 /*!< GPIO_PORT PIN6: PORT4 Position */ -#define GPIO_PORT_PIN6_PORT4_Msk (0x01UL << GPIO_PORT_PIN6_PORT4_Pos) /*!< GPIO_PORT PIN6: PORT4 Mask */ -#define GPIO_PORT_PIN6_PORT5_Pos 5 /*!< GPIO_PORT PIN6: PORT5 Position */ -#define GPIO_PORT_PIN6_PORT5_Msk (0x01UL << GPIO_PORT_PIN6_PORT5_Pos) /*!< GPIO_PORT PIN6: PORT5 Mask */ -#define GPIO_PORT_PIN6_PORT6_Pos 6 /*!< GPIO_PORT PIN6: PORT6 Position */ -#define GPIO_PORT_PIN6_PORT6_Msk (0x01UL << GPIO_PORT_PIN6_PORT6_Pos) /*!< GPIO_PORT PIN6: PORT6 Mask */ -#define GPIO_PORT_PIN6_PORT7_Pos 7 /*!< GPIO_PORT PIN6: PORT7 Position */ -#define GPIO_PORT_PIN6_PORT7_Msk (0x01UL << GPIO_PORT_PIN6_PORT7_Pos) /*!< GPIO_PORT PIN6: PORT7 Mask */ -#define GPIO_PORT_PIN6_PORT8_Pos 8 /*!< GPIO_PORT PIN6: PORT8 Position */ -#define GPIO_PORT_PIN6_PORT8_Msk (0x01UL << GPIO_PORT_PIN6_PORT8_Pos) /*!< GPIO_PORT PIN6: PORT8 Mask */ -#define GPIO_PORT_PIN6_PORT9_Pos 9 /*!< GPIO_PORT PIN6: PORT9 Position */ -#define GPIO_PORT_PIN6_PORT9_Msk (0x01UL << GPIO_PORT_PIN6_PORT9_Pos) /*!< GPIO_PORT PIN6: PORT9 Mask */ -#define GPIO_PORT_PIN6_PORT10_Pos 10 /*!< GPIO_PORT PIN6: PORT10 Position */ -#define GPIO_PORT_PIN6_PORT10_Msk (0x01UL << GPIO_PORT_PIN6_PORT10_Pos) /*!< GPIO_PORT PIN6: PORT10 Mask */ -#define GPIO_PORT_PIN6_PORT11_Pos 11 /*!< GPIO_PORT PIN6: PORT11 Position */ -#define GPIO_PORT_PIN6_PORT11_Msk (0x01UL << GPIO_PORT_PIN6_PORT11_Pos) /*!< GPIO_PORT PIN6: PORT11 Mask */ -#define GPIO_PORT_PIN6_PORT12_Pos 12 /*!< GPIO_PORT PIN6: PORT12 Position */ -#define GPIO_PORT_PIN6_PORT12_Msk (0x01UL << GPIO_PORT_PIN6_PORT12_Pos) /*!< GPIO_PORT PIN6: PORT12 Mask */ -#define GPIO_PORT_PIN6_PORT13_Pos 13 /*!< GPIO_PORT PIN6: PORT13 Position */ -#define GPIO_PORT_PIN6_PORT13_Msk (0x01UL << GPIO_PORT_PIN6_PORT13_Pos) /*!< GPIO_PORT PIN6: PORT13 Mask */ -#define GPIO_PORT_PIN6_PORT14_Pos 14 /*!< GPIO_PORT PIN6: PORT14 Position */ -#define GPIO_PORT_PIN6_PORT14_Msk (0x01UL << GPIO_PORT_PIN6_PORT14_Pos) /*!< GPIO_PORT PIN6: PORT14 Mask */ -#define GPIO_PORT_PIN6_PORT15_Pos 15 /*!< GPIO_PORT PIN6: PORT15 Position */ -#define GPIO_PORT_PIN6_PORT15_Msk (0x01UL << GPIO_PORT_PIN6_PORT15_Pos) /*!< GPIO_PORT PIN6: PORT15 Mask */ -#define GPIO_PORT_PIN6_PORT16_Pos 16 /*!< GPIO_PORT PIN6: PORT16 Position */ -#define GPIO_PORT_PIN6_PORT16_Msk (0x01UL << GPIO_PORT_PIN6_PORT16_Pos) /*!< GPIO_PORT PIN6: PORT16 Mask */ -#define GPIO_PORT_PIN6_PORT17_Pos 17 /*!< GPIO_PORT PIN6: PORT17 Position */ -#define GPIO_PORT_PIN6_PORT17_Msk (0x01UL << GPIO_PORT_PIN6_PORT17_Pos) /*!< GPIO_PORT PIN6: PORT17 Mask */ -#define GPIO_PORT_PIN6_PORT18_Pos 18 /*!< GPIO_PORT PIN6: PORT18 Position */ -#define GPIO_PORT_PIN6_PORT18_Msk (0x01UL << GPIO_PORT_PIN6_PORT18_Pos) /*!< GPIO_PORT PIN6: PORT18 Mask */ -#define GPIO_PORT_PIN6_PORT19_Pos 19 /*!< GPIO_PORT PIN6: PORT19 Position */ -#define GPIO_PORT_PIN6_PORT19_Msk (0x01UL << GPIO_PORT_PIN6_PORT19_Pos) /*!< GPIO_PORT PIN6: PORT19 Mask */ -#define GPIO_PORT_PIN6_PORT20_Pos 20 /*!< GPIO_PORT PIN6: PORT20 Position */ -#define GPIO_PORT_PIN6_PORT20_Msk (0x01UL << GPIO_PORT_PIN6_PORT20_Pos) /*!< GPIO_PORT PIN6: PORT20 Mask */ -#define GPIO_PORT_PIN6_PORT21_Pos 21 /*!< GPIO_PORT PIN6: PORT21 Position */ -#define GPIO_PORT_PIN6_PORT21_Msk (0x01UL << GPIO_PORT_PIN6_PORT21_Pos) /*!< GPIO_PORT PIN6: PORT21 Mask */ -#define GPIO_PORT_PIN6_PORT22_Pos 22 /*!< GPIO_PORT PIN6: PORT22 Position */ -#define GPIO_PORT_PIN6_PORT22_Msk (0x01UL << GPIO_PORT_PIN6_PORT22_Pos) /*!< GPIO_PORT PIN6: PORT22 Mask */ -#define GPIO_PORT_PIN6_PORT23_Pos 23 /*!< GPIO_PORT PIN6: PORT23 Position */ -#define GPIO_PORT_PIN6_PORT23_Msk (0x01UL << GPIO_PORT_PIN6_PORT23_Pos) /*!< GPIO_PORT PIN6: PORT23 Mask */ -#define GPIO_PORT_PIN6_PORT24_Pos 24 /*!< GPIO_PORT PIN6: PORT24 Position */ -#define GPIO_PORT_PIN6_PORT24_Msk (0x01UL << GPIO_PORT_PIN6_PORT24_Pos) /*!< GPIO_PORT PIN6: PORT24 Mask */ -#define GPIO_PORT_PIN6_PORT25_Pos 25 /*!< GPIO_PORT PIN6: PORT25 Position */ -#define GPIO_PORT_PIN6_PORT25_Msk (0x01UL << GPIO_PORT_PIN6_PORT25_Pos) /*!< GPIO_PORT PIN6: PORT25 Mask */ -#define GPIO_PORT_PIN6_PORT26_Pos 26 /*!< GPIO_PORT PIN6: PORT26 Position */ -#define GPIO_PORT_PIN6_PORT26_Msk (0x01UL << GPIO_PORT_PIN6_PORT26_Pos) /*!< GPIO_PORT PIN6: PORT26 Mask */ -#define GPIO_PORT_PIN6_PORT27_Pos 27 /*!< GPIO_PORT PIN6: PORT27 Position */ -#define GPIO_PORT_PIN6_PORT27_Msk (0x01UL << GPIO_PORT_PIN6_PORT27_Pos) /*!< GPIO_PORT PIN6: PORT27 Mask */ -#define GPIO_PORT_PIN6_PORT28_Pos 28 /*!< GPIO_PORT PIN6: PORT28 Position */ -#define GPIO_PORT_PIN6_PORT28_Msk (0x01UL << GPIO_PORT_PIN6_PORT28_Pos) /*!< GPIO_PORT PIN6: PORT28 Mask */ -#define GPIO_PORT_PIN6_PORT29_Pos 29 /*!< GPIO_PORT PIN6: PORT29 Position */ -#define GPIO_PORT_PIN6_PORT29_Msk (0x01UL << GPIO_PORT_PIN6_PORT29_Pos) /*!< GPIO_PORT PIN6: PORT29 Mask */ -#define GPIO_PORT_PIN6_PORT30_Pos 30 /*!< GPIO_PORT PIN6: PORT30 Position */ -#define GPIO_PORT_PIN6_PORT30_Msk (0x01UL << GPIO_PORT_PIN6_PORT30_Pos) /*!< GPIO_PORT PIN6: PORT30 Mask */ -#define GPIO_PORT_PIN6_PORT31_Pos 31 /*!< GPIO_PORT PIN6: PORT31 Position */ -#define GPIO_PORT_PIN6_PORT31_Msk (0x01UL << GPIO_PORT_PIN6_PORT31_Pos) /*!< GPIO_PORT PIN6: PORT31 Mask */ - -// ------------------------------------- GPIO_PORT_PIN7 ----------------------------------------- -#define GPIO_PORT_PIN7_PORT0_Pos 0 /*!< GPIO_PORT PIN7: PORT0 Position */ -#define GPIO_PORT_PIN7_PORT0_Msk (0x01UL << GPIO_PORT_PIN7_PORT0_Pos) /*!< GPIO_PORT PIN7: PORT0 Mask */ -#define GPIO_PORT_PIN7_PORT1_Pos 1 /*!< GPIO_PORT PIN7: PORT1 Position */ -#define GPIO_PORT_PIN7_PORT1_Msk (0x01UL << GPIO_PORT_PIN7_PORT1_Pos) /*!< GPIO_PORT PIN7: PORT1 Mask */ -#define GPIO_PORT_PIN7_PORT2_Pos 2 /*!< GPIO_PORT PIN7: PORT2 Position */ -#define GPIO_PORT_PIN7_PORT2_Msk (0x01UL << GPIO_PORT_PIN7_PORT2_Pos) /*!< GPIO_PORT PIN7: PORT2 Mask */ -#define GPIO_PORT_PIN7_PORT3_Pos 3 /*!< GPIO_PORT PIN7: PORT3 Position */ -#define GPIO_PORT_PIN7_PORT3_Msk (0x01UL << GPIO_PORT_PIN7_PORT3_Pos) /*!< GPIO_PORT PIN7: PORT3 Mask */ -#define GPIO_PORT_PIN7_PORT4_Pos 4 /*!< GPIO_PORT PIN7: PORT4 Position */ -#define GPIO_PORT_PIN7_PORT4_Msk (0x01UL << GPIO_PORT_PIN7_PORT4_Pos) /*!< GPIO_PORT PIN7: PORT4 Mask */ -#define GPIO_PORT_PIN7_PORT5_Pos 5 /*!< GPIO_PORT PIN7: PORT5 Position */ -#define GPIO_PORT_PIN7_PORT5_Msk (0x01UL << GPIO_PORT_PIN7_PORT5_Pos) /*!< GPIO_PORT PIN7: PORT5 Mask */ -#define GPIO_PORT_PIN7_PORT6_Pos 6 /*!< GPIO_PORT PIN7: PORT6 Position */ -#define GPIO_PORT_PIN7_PORT6_Msk (0x01UL << GPIO_PORT_PIN7_PORT6_Pos) /*!< GPIO_PORT PIN7: PORT6 Mask */ -#define GPIO_PORT_PIN7_PORT7_Pos 7 /*!< GPIO_PORT PIN7: PORT7 Position */ -#define GPIO_PORT_PIN7_PORT7_Msk (0x01UL << GPIO_PORT_PIN7_PORT7_Pos) /*!< GPIO_PORT PIN7: PORT7 Mask */ -#define GPIO_PORT_PIN7_PORT8_Pos 8 /*!< GPIO_PORT PIN7: PORT8 Position */ -#define GPIO_PORT_PIN7_PORT8_Msk (0x01UL << GPIO_PORT_PIN7_PORT8_Pos) /*!< GPIO_PORT PIN7: PORT8 Mask */ -#define GPIO_PORT_PIN7_PORT9_Pos 9 /*!< GPIO_PORT PIN7: PORT9 Position */ -#define GPIO_PORT_PIN7_PORT9_Msk (0x01UL << GPIO_PORT_PIN7_PORT9_Pos) /*!< GPIO_PORT PIN7: PORT9 Mask */ -#define GPIO_PORT_PIN7_PORT10_Pos 10 /*!< GPIO_PORT PIN7: PORT10 Position */ -#define GPIO_PORT_PIN7_PORT10_Msk (0x01UL << GPIO_PORT_PIN7_PORT10_Pos) /*!< GPIO_PORT PIN7: PORT10 Mask */ -#define GPIO_PORT_PIN7_PORT11_Pos 11 /*!< GPIO_PORT PIN7: PORT11 Position */ -#define GPIO_PORT_PIN7_PORT11_Msk (0x01UL << GPIO_PORT_PIN7_PORT11_Pos) /*!< GPIO_PORT PIN7: PORT11 Mask */ -#define GPIO_PORT_PIN7_PORT12_Pos 12 /*!< GPIO_PORT PIN7: PORT12 Position */ -#define GPIO_PORT_PIN7_PORT12_Msk (0x01UL << GPIO_PORT_PIN7_PORT12_Pos) /*!< GPIO_PORT PIN7: PORT12 Mask */ -#define GPIO_PORT_PIN7_PORT13_Pos 13 /*!< GPIO_PORT PIN7: PORT13 Position */ -#define GPIO_PORT_PIN7_PORT13_Msk (0x01UL << GPIO_PORT_PIN7_PORT13_Pos) /*!< GPIO_PORT PIN7: PORT13 Mask */ -#define GPIO_PORT_PIN7_PORT14_Pos 14 /*!< GPIO_PORT PIN7: PORT14 Position */ -#define GPIO_PORT_PIN7_PORT14_Msk (0x01UL << GPIO_PORT_PIN7_PORT14_Pos) /*!< GPIO_PORT PIN7: PORT14 Mask */ -#define GPIO_PORT_PIN7_PORT15_Pos 15 /*!< GPIO_PORT PIN7: PORT15 Position */ -#define GPIO_PORT_PIN7_PORT15_Msk (0x01UL << GPIO_PORT_PIN7_PORT15_Pos) /*!< GPIO_PORT PIN7: PORT15 Mask */ -#define GPIO_PORT_PIN7_PORT16_Pos 16 /*!< GPIO_PORT PIN7: PORT16 Position */ -#define GPIO_PORT_PIN7_PORT16_Msk (0x01UL << GPIO_PORT_PIN7_PORT16_Pos) /*!< GPIO_PORT PIN7: PORT16 Mask */ -#define GPIO_PORT_PIN7_PORT17_Pos 17 /*!< GPIO_PORT PIN7: PORT17 Position */ -#define GPIO_PORT_PIN7_PORT17_Msk (0x01UL << GPIO_PORT_PIN7_PORT17_Pos) /*!< GPIO_PORT PIN7: PORT17 Mask */ -#define GPIO_PORT_PIN7_PORT18_Pos 18 /*!< GPIO_PORT PIN7: PORT18 Position */ -#define GPIO_PORT_PIN7_PORT18_Msk (0x01UL << GPIO_PORT_PIN7_PORT18_Pos) /*!< GPIO_PORT PIN7: PORT18 Mask */ -#define GPIO_PORT_PIN7_PORT19_Pos 19 /*!< GPIO_PORT PIN7: PORT19 Position */ -#define GPIO_PORT_PIN7_PORT19_Msk (0x01UL << GPIO_PORT_PIN7_PORT19_Pos) /*!< GPIO_PORT PIN7: PORT19 Mask */ -#define GPIO_PORT_PIN7_PORT20_Pos 20 /*!< GPIO_PORT PIN7: PORT20 Position */ -#define GPIO_PORT_PIN7_PORT20_Msk (0x01UL << GPIO_PORT_PIN7_PORT20_Pos) /*!< GPIO_PORT PIN7: PORT20 Mask */ -#define GPIO_PORT_PIN7_PORT21_Pos 21 /*!< GPIO_PORT PIN7: PORT21 Position */ -#define GPIO_PORT_PIN7_PORT21_Msk (0x01UL << GPIO_PORT_PIN7_PORT21_Pos) /*!< GPIO_PORT PIN7: PORT21 Mask */ -#define GPIO_PORT_PIN7_PORT22_Pos 22 /*!< GPIO_PORT PIN7: PORT22 Position */ -#define GPIO_PORT_PIN7_PORT22_Msk (0x01UL << GPIO_PORT_PIN7_PORT22_Pos) /*!< GPIO_PORT PIN7: PORT22 Mask */ -#define GPIO_PORT_PIN7_PORT23_Pos 23 /*!< GPIO_PORT PIN7: PORT23 Position */ -#define GPIO_PORT_PIN7_PORT23_Msk (0x01UL << GPIO_PORT_PIN7_PORT23_Pos) /*!< GPIO_PORT PIN7: PORT23 Mask */ -#define GPIO_PORT_PIN7_PORT24_Pos 24 /*!< GPIO_PORT PIN7: PORT24 Position */ -#define GPIO_PORT_PIN7_PORT24_Msk (0x01UL << GPIO_PORT_PIN7_PORT24_Pos) /*!< GPIO_PORT PIN7: PORT24 Mask */ -#define GPIO_PORT_PIN7_PORT25_Pos 25 /*!< GPIO_PORT PIN7: PORT25 Position */ -#define GPIO_PORT_PIN7_PORT25_Msk (0x01UL << GPIO_PORT_PIN7_PORT25_Pos) /*!< GPIO_PORT PIN7: PORT25 Mask */ -#define GPIO_PORT_PIN7_PORT26_Pos 26 /*!< GPIO_PORT PIN7: PORT26 Position */ -#define GPIO_PORT_PIN7_PORT26_Msk (0x01UL << GPIO_PORT_PIN7_PORT26_Pos) /*!< GPIO_PORT PIN7: PORT26 Mask */ -#define GPIO_PORT_PIN7_PORT27_Pos 27 /*!< GPIO_PORT PIN7: PORT27 Position */ -#define GPIO_PORT_PIN7_PORT27_Msk (0x01UL << GPIO_PORT_PIN7_PORT27_Pos) /*!< GPIO_PORT PIN7: PORT27 Mask */ -#define GPIO_PORT_PIN7_PORT28_Pos 28 /*!< GPIO_PORT PIN7: PORT28 Position */ -#define GPIO_PORT_PIN7_PORT28_Msk (0x01UL << GPIO_PORT_PIN7_PORT28_Pos) /*!< GPIO_PORT PIN7: PORT28 Mask */ -#define GPIO_PORT_PIN7_PORT29_Pos 29 /*!< GPIO_PORT PIN7: PORT29 Position */ -#define GPIO_PORT_PIN7_PORT29_Msk (0x01UL << GPIO_PORT_PIN7_PORT29_Pos) /*!< GPIO_PORT PIN7: PORT29 Mask */ -#define GPIO_PORT_PIN7_PORT30_Pos 30 /*!< GPIO_PORT PIN7: PORT30 Position */ -#define GPIO_PORT_PIN7_PORT30_Msk (0x01UL << GPIO_PORT_PIN7_PORT30_Pos) /*!< GPIO_PORT PIN7: PORT30 Mask */ -#define GPIO_PORT_PIN7_PORT31_Pos 31 /*!< GPIO_PORT PIN7: PORT31 Position */ -#define GPIO_PORT_PIN7_PORT31_Msk (0x01UL << GPIO_PORT_PIN7_PORT31_Pos) /*!< GPIO_PORT PIN7: PORT31 Mask */ - -// ------------------------------------- GPIO_PORT_MPIN0 ---------------------------------------- -#define GPIO_PORT_MPIN0_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN0: MPORTP0 Position */ -#define GPIO_PORT_MPIN0_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP0_Pos) /*!< GPIO_PORT MPIN0: MPORTP0 Mask */ -#define GPIO_PORT_MPIN0_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN0: MPORTP1 Position */ -#define GPIO_PORT_MPIN0_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP1_Pos) /*!< GPIO_PORT MPIN0: MPORTP1 Mask */ -#define GPIO_PORT_MPIN0_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN0: MPORTP2 Position */ -#define GPIO_PORT_MPIN0_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP2_Pos) /*!< GPIO_PORT MPIN0: MPORTP2 Mask */ -#define GPIO_PORT_MPIN0_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN0: MPORTP3 Position */ -#define GPIO_PORT_MPIN0_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP3_Pos) /*!< GPIO_PORT MPIN0: MPORTP3 Mask */ -#define GPIO_PORT_MPIN0_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN0: MPORTP4 Position */ -#define GPIO_PORT_MPIN0_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP4_Pos) /*!< GPIO_PORT MPIN0: MPORTP4 Mask */ -#define GPIO_PORT_MPIN0_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN0: MPORTP5 Position */ -#define GPIO_PORT_MPIN0_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP5_Pos) /*!< GPIO_PORT MPIN0: MPORTP5 Mask */ -#define GPIO_PORT_MPIN0_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN0: MPORTP6 Position */ -#define GPIO_PORT_MPIN0_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP6_Pos) /*!< GPIO_PORT MPIN0: MPORTP6 Mask */ -#define GPIO_PORT_MPIN0_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN0: MPORTP7 Position */ -#define GPIO_PORT_MPIN0_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP7_Pos) /*!< GPIO_PORT MPIN0: MPORTP7 Mask */ -#define GPIO_PORT_MPIN0_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN0: MPORTP8 Position */ -#define GPIO_PORT_MPIN0_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP8_Pos) /*!< GPIO_PORT MPIN0: MPORTP8 Mask */ -#define GPIO_PORT_MPIN0_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN0: MPORTP9 Position */ -#define GPIO_PORT_MPIN0_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP9_Pos) /*!< GPIO_PORT MPIN0: MPORTP9 Mask */ -#define GPIO_PORT_MPIN0_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN0: MPORTP10 Position */ -#define GPIO_PORT_MPIN0_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP10_Pos) /*!< GPIO_PORT MPIN0: MPORTP10 Mask */ -#define GPIO_PORT_MPIN0_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN0: MPORTP11 Position */ -#define GPIO_PORT_MPIN0_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP11_Pos) /*!< GPIO_PORT MPIN0: MPORTP11 Mask */ -#define GPIO_PORT_MPIN0_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN0: MPORTP12 Position */ -#define GPIO_PORT_MPIN0_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP12_Pos) /*!< GPIO_PORT MPIN0: MPORTP12 Mask */ -#define GPIO_PORT_MPIN0_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN0: MPORTP13 Position */ -#define GPIO_PORT_MPIN0_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP13_Pos) /*!< GPIO_PORT MPIN0: MPORTP13 Mask */ -#define GPIO_PORT_MPIN0_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN0: MPORTP14 Position */ -#define GPIO_PORT_MPIN0_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP14_Pos) /*!< GPIO_PORT MPIN0: MPORTP14 Mask */ -#define GPIO_PORT_MPIN0_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN0: MPORTP15 Position */ -#define GPIO_PORT_MPIN0_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP15_Pos) /*!< GPIO_PORT MPIN0: MPORTP15 Mask */ -#define GPIO_PORT_MPIN0_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN0: MPORTP16 Position */ -#define GPIO_PORT_MPIN0_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP16_Pos) /*!< GPIO_PORT MPIN0: MPORTP16 Mask */ -#define GPIO_PORT_MPIN0_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN0: MPORTP17 Position */ -#define GPIO_PORT_MPIN0_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP17_Pos) /*!< GPIO_PORT MPIN0: MPORTP17 Mask */ -#define GPIO_PORT_MPIN0_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN0: MPORTP18 Position */ -#define GPIO_PORT_MPIN0_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP18_Pos) /*!< GPIO_PORT MPIN0: MPORTP18 Mask */ -#define GPIO_PORT_MPIN0_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN0: MPORTP19 Position */ -#define GPIO_PORT_MPIN0_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP19_Pos) /*!< GPIO_PORT MPIN0: MPORTP19 Mask */ -#define GPIO_PORT_MPIN0_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN0: MPORTP20 Position */ -#define GPIO_PORT_MPIN0_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP20_Pos) /*!< GPIO_PORT MPIN0: MPORTP20 Mask */ -#define GPIO_PORT_MPIN0_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN0: MPORTP21 Position */ -#define GPIO_PORT_MPIN0_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP21_Pos) /*!< GPIO_PORT MPIN0: MPORTP21 Mask */ -#define GPIO_PORT_MPIN0_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN0: MPORTP22 Position */ -#define GPIO_PORT_MPIN0_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP22_Pos) /*!< GPIO_PORT MPIN0: MPORTP22 Mask */ -#define GPIO_PORT_MPIN0_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN0: MPORTP23 Position */ -#define GPIO_PORT_MPIN0_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP23_Pos) /*!< GPIO_PORT MPIN0: MPORTP23 Mask */ -#define GPIO_PORT_MPIN0_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN0: MPORTP24 Position */ -#define GPIO_PORT_MPIN0_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP24_Pos) /*!< GPIO_PORT MPIN0: MPORTP24 Mask */ -#define GPIO_PORT_MPIN0_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN0: MPORTP25 Position */ -#define GPIO_PORT_MPIN0_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP25_Pos) /*!< GPIO_PORT MPIN0: MPORTP25 Mask */ -#define GPIO_PORT_MPIN0_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN0: MPORTP26 Position */ -#define GPIO_PORT_MPIN0_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP26_Pos) /*!< GPIO_PORT MPIN0: MPORTP26 Mask */ -#define GPIO_PORT_MPIN0_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN0: MPORTP27 Position */ -#define GPIO_PORT_MPIN0_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP27_Pos) /*!< GPIO_PORT MPIN0: MPORTP27 Mask */ -#define GPIO_PORT_MPIN0_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN0: MPORTP28 Position */ -#define GPIO_PORT_MPIN0_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP28_Pos) /*!< GPIO_PORT MPIN0: MPORTP28 Mask */ -#define GPIO_PORT_MPIN0_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN0: MPORTP29 Position */ -#define GPIO_PORT_MPIN0_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP29_Pos) /*!< GPIO_PORT MPIN0: MPORTP29 Mask */ -#define GPIO_PORT_MPIN0_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN0: MPORTP30 Position */ -#define GPIO_PORT_MPIN0_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP30_Pos) /*!< GPIO_PORT MPIN0: MPORTP30 Mask */ -#define GPIO_PORT_MPIN0_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN0: MPORTP31 Position */ -#define GPIO_PORT_MPIN0_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN0_MPORTP31_Pos) /*!< GPIO_PORT MPIN0: MPORTP31 Mask */ - -// ------------------------------------- GPIO_PORT_MPIN1 ---------------------------------------- -#define GPIO_PORT_MPIN1_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN1: MPORTP0 Position */ -#define GPIO_PORT_MPIN1_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP0_Pos) /*!< GPIO_PORT MPIN1: MPORTP0 Mask */ -#define GPIO_PORT_MPIN1_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN1: MPORTP1 Position */ -#define GPIO_PORT_MPIN1_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP1_Pos) /*!< GPIO_PORT MPIN1: MPORTP1 Mask */ -#define GPIO_PORT_MPIN1_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN1: MPORTP2 Position */ -#define GPIO_PORT_MPIN1_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP2_Pos) /*!< GPIO_PORT MPIN1: MPORTP2 Mask */ -#define GPIO_PORT_MPIN1_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN1: MPORTP3 Position */ -#define GPIO_PORT_MPIN1_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP3_Pos) /*!< GPIO_PORT MPIN1: MPORTP3 Mask */ -#define GPIO_PORT_MPIN1_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN1: MPORTP4 Position */ -#define GPIO_PORT_MPIN1_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP4_Pos) /*!< GPIO_PORT MPIN1: MPORTP4 Mask */ -#define GPIO_PORT_MPIN1_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN1: MPORTP5 Position */ -#define GPIO_PORT_MPIN1_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP5_Pos) /*!< GPIO_PORT MPIN1: MPORTP5 Mask */ -#define GPIO_PORT_MPIN1_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN1: MPORTP6 Position */ -#define GPIO_PORT_MPIN1_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP6_Pos) /*!< GPIO_PORT MPIN1: MPORTP6 Mask */ -#define GPIO_PORT_MPIN1_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN1: MPORTP7 Position */ -#define GPIO_PORT_MPIN1_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP7_Pos) /*!< GPIO_PORT MPIN1: MPORTP7 Mask */ -#define GPIO_PORT_MPIN1_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN1: MPORTP8 Position */ -#define GPIO_PORT_MPIN1_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP8_Pos) /*!< GPIO_PORT MPIN1: MPORTP8 Mask */ -#define GPIO_PORT_MPIN1_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN1: MPORTP9 Position */ -#define GPIO_PORT_MPIN1_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP9_Pos) /*!< GPIO_PORT MPIN1: MPORTP9 Mask */ -#define GPIO_PORT_MPIN1_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN1: MPORTP10 Position */ -#define GPIO_PORT_MPIN1_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP10_Pos) /*!< GPIO_PORT MPIN1: MPORTP10 Mask */ -#define GPIO_PORT_MPIN1_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN1: MPORTP11 Position */ -#define GPIO_PORT_MPIN1_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP11_Pos) /*!< GPIO_PORT MPIN1: MPORTP11 Mask */ -#define GPIO_PORT_MPIN1_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN1: MPORTP12 Position */ -#define GPIO_PORT_MPIN1_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP12_Pos) /*!< GPIO_PORT MPIN1: MPORTP12 Mask */ -#define GPIO_PORT_MPIN1_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN1: MPORTP13 Position */ -#define GPIO_PORT_MPIN1_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP13_Pos) /*!< GPIO_PORT MPIN1: MPORTP13 Mask */ -#define GPIO_PORT_MPIN1_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN1: MPORTP14 Position */ -#define GPIO_PORT_MPIN1_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP14_Pos) /*!< GPIO_PORT MPIN1: MPORTP14 Mask */ -#define GPIO_PORT_MPIN1_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN1: MPORTP15 Position */ -#define GPIO_PORT_MPIN1_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP15_Pos) /*!< GPIO_PORT MPIN1: MPORTP15 Mask */ -#define GPIO_PORT_MPIN1_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN1: MPORTP16 Position */ -#define GPIO_PORT_MPIN1_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP16_Pos) /*!< GPIO_PORT MPIN1: MPORTP16 Mask */ -#define GPIO_PORT_MPIN1_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN1: MPORTP17 Position */ -#define GPIO_PORT_MPIN1_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP17_Pos) /*!< GPIO_PORT MPIN1: MPORTP17 Mask */ -#define GPIO_PORT_MPIN1_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN1: MPORTP18 Position */ -#define GPIO_PORT_MPIN1_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP18_Pos) /*!< GPIO_PORT MPIN1: MPORTP18 Mask */ -#define GPIO_PORT_MPIN1_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN1: MPORTP19 Position */ -#define GPIO_PORT_MPIN1_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP19_Pos) /*!< GPIO_PORT MPIN1: MPORTP19 Mask */ -#define GPIO_PORT_MPIN1_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN1: MPORTP20 Position */ -#define GPIO_PORT_MPIN1_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP20_Pos) /*!< GPIO_PORT MPIN1: MPORTP20 Mask */ -#define GPIO_PORT_MPIN1_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN1: MPORTP21 Position */ -#define GPIO_PORT_MPIN1_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP21_Pos) /*!< GPIO_PORT MPIN1: MPORTP21 Mask */ -#define GPIO_PORT_MPIN1_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN1: MPORTP22 Position */ -#define GPIO_PORT_MPIN1_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP22_Pos) /*!< GPIO_PORT MPIN1: MPORTP22 Mask */ -#define GPIO_PORT_MPIN1_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN1: MPORTP23 Position */ -#define GPIO_PORT_MPIN1_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP23_Pos) /*!< GPIO_PORT MPIN1: MPORTP23 Mask */ -#define GPIO_PORT_MPIN1_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN1: MPORTP24 Position */ -#define GPIO_PORT_MPIN1_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP24_Pos) /*!< GPIO_PORT MPIN1: MPORTP24 Mask */ -#define GPIO_PORT_MPIN1_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN1: MPORTP25 Position */ -#define GPIO_PORT_MPIN1_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP25_Pos) /*!< GPIO_PORT MPIN1: MPORTP25 Mask */ -#define GPIO_PORT_MPIN1_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN1: MPORTP26 Position */ -#define GPIO_PORT_MPIN1_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP26_Pos) /*!< GPIO_PORT MPIN1: MPORTP26 Mask */ -#define GPIO_PORT_MPIN1_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN1: MPORTP27 Position */ -#define GPIO_PORT_MPIN1_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP27_Pos) /*!< GPIO_PORT MPIN1: MPORTP27 Mask */ -#define GPIO_PORT_MPIN1_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN1: MPORTP28 Position */ -#define GPIO_PORT_MPIN1_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP28_Pos) /*!< GPIO_PORT MPIN1: MPORTP28 Mask */ -#define GPIO_PORT_MPIN1_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN1: MPORTP29 Position */ -#define GPIO_PORT_MPIN1_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP29_Pos) /*!< GPIO_PORT MPIN1: MPORTP29 Mask */ -#define GPIO_PORT_MPIN1_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN1: MPORTP30 Position */ -#define GPIO_PORT_MPIN1_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP30_Pos) /*!< GPIO_PORT MPIN1: MPORTP30 Mask */ -#define GPIO_PORT_MPIN1_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN1: MPORTP31 Position */ -#define GPIO_PORT_MPIN1_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN1_MPORTP31_Pos) /*!< GPIO_PORT MPIN1: MPORTP31 Mask */ - -// ------------------------------------- GPIO_PORT_MPIN2 ---------------------------------------- -#define GPIO_PORT_MPIN2_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN2: MPORTP0 Position */ -#define GPIO_PORT_MPIN2_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP0_Pos) /*!< GPIO_PORT MPIN2: MPORTP0 Mask */ -#define GPIO_PORT_MPIN2_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN2: MPORTP1 Position */ -#define GPIO_PORT_MPIN2_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP1_Pos) /*!< GPIO_PORT MPIN2: MPORTP1 Mask */ -#define GPIO_PORT_MPIN2_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN2: MPORTP2 Position */ -#define GPIO_PORT_MPIN2_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP2_Pos) /*!< GPIO_PORT MPIN2: MPORTP2 Mask */ -#define GPIO_PORT_MPIN2_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN2: MPORTP3 Position */ -#define GPIO_PORT_MPIN2_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP3_Pos) /*!< GPIO_PORT MPIN2: MPORTP3 Mask */ -#define GPIO_PORT_MPIN2_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN2: MPORTP4 Position */ -#define GPIO_PORT_MPIN2_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP4_Pos) /*!< GPIO_PORT MPIN2: MPORTP4 Mask */ -#define GPIO_PORT_MPIN2_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN2: MPORTP5 Position */ -#define GPIO_PORT_MPIN2_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP5_Pos) /*!< GPIO_PORT MPIN2: MPORTP5 Mask */ -#define GPIO_PORT_MPIN2_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN2: MPORTP6 Position */ -#define GPIO_PORT_MPIN2_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP6_Pos) /*!< GPIO_PORT MPIN2: MPORTP6 Mask */ -#define GPIO_PORT_MPIN2_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN2: MPORTP7 Position */ -#define GPIO_PORT_MPIN2_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP7_Pos) /*!< GPIO_PORT MPIN2: MPORTP7 Mask */ -#define GPIO_PORT_MPIN2_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN2: MPORTP8 Position */ -#define GPIO_PORT_MPIN2_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP8_Pos) /*!< GPIO_PORT MPIN2: MPORTP8 Mask */ -#define GPIO_PORT_MPIN2_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN2: MPORTP9 Position */ -#define GPIO_PORT_MPIN2_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP9_Pos) /*!< GPIO_PORT MPIN2: MPORTP9 Mask */ -#define GPIO_PORT_MPIN2_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN2: MPORTP10 Position */ -#define GPIO_PORT_MPIN2_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP10_Pos) /*!< GPIO_PORT MPIN2: MPORTP10 Mask */ -#define GPIO_PORT_MPIN2_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN2: MPORTP11 Position */ -#define GPIO_PORT_MPIN2_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP11_Pos) /*!< GPIO_PORT MPIN2: MPORTP11 Mask */ -#define GPIO_PORT_MPIN2_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN2: MPORTP12 Position */ -#define GPIO_PORT_MPIN2_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP12_Pos) /*!< GPIO_PORT MPIN2: MPORTP12 Mask */ -#define GPIO_PORT_MPIN2_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN2: MPORTP13 Position */ -#define GPIO_PORT_MPIN2_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP13_Pos) /*!< GPIO_PORT MPIN2: MPORTP13 Mask */ -#define GPIO_PORT_MPIN2_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN2: MPORTP14 Position */ -#define GPIO_PORT_MPIN2_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP14_Pos) /*!< GPIO_PORT MPIN2: MPORTP14 Mask */ -#define GPIO_PORT_MPIN2_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN2: MPORTP15 Position */ -#define GPIO_PORT_MPIN2_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP15_Pos) /*!< GPIO_PORT MPIN2: MPORTP15 Mask */ -#define GPIO_PORT_MPIN2_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN2: MPORTP16 Position */ -#define GPIO_PORT_MPIN2_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP16_Pos) /*!< GPIO_PORT MPIN2: MPORTP16 Mask */ -#define GPIO_PORT_MPIN2_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN2: MPORTP17 Position */ -#define GPIO_PORT_MPIN2_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP17_Pos) /*!< GPIO_PORT MPIN2: MPORTP17 Mask */ -#define GPIO_PORT_MPIN2_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN2: MPORTP18 Position */ -#define GPIO_PORT_MPIN2_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP18_Pos) /*!< GPIO_PORT MPIN2: MPORTP18 Mask */ -#define GPIO_PORT_MPIN2_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN2: MPORTP19 Position */ -#define GPIO_PORT_MPIN2_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP19_Pos) /*!< GPIO_PORT MPIN2: MPORTP19 Mask */ -#define GPIO_PORT_MPIN2_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN2: MPORTP20 Position */ -#define GPIO_PORT_MPIN2_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP20_Pos) /*!< GPIO_PORT MPIN2: MPORTP20 Mask */ -#define GPIO_PORT_MPIN2_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN2: MPORTP21 Position */ -#define GPIO_PORT_MPIN2_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP21_Pos) /*!< GPIO_PORT MPIN2: MPORTP21 Mask */ -#define GPIO_PORT_MPIN2_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN2: MPORTP22 Position */ -#define GPIO_PORT_MPIN2_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP22_Pos) /*!< GPIO_PORT MPIN2: MPORTP22 Mask */ -#define GPIO_PORT_MPIN2_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN2: MPORTP23 Position */ -#define GPIO_PORT_MPIN2_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP23_Pos) /*!< GPIO_PORT MPIN2: MPORTP23 Mask */ -#define GPIO_PORT_MPIN2_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN2: MPORTP24 Position */ -#define GPIO_PORT_MPIN2_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP24_Pos) /*!< GPIO_PORT MPIN2: MPORTP24 Mask */ -#define GPIO_PORT_MPIN2_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN2: MPORTP25 Position */ -#define GPIO_PORT_MPIN2_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP25_Pos) /*!< GPIO_PORT MPIN2: MPORTP25 Mask */ -#define GPIO_PORT_MPIN2_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN2: MPORTP26 Position */ -#define GPIO_PORT_MPIN2_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP26_Pos) /*!< GPIO_PORT MPIN2: MPORTP26 Mask */ -#define GPIO_PORT_MPIN2_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN2: MPORTP27 Position */ -#define GPIO_PORT_MPIN2_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP27_Pos) /*!< GPIO_PORT MPIN2: MPORTP27 Mask */ -#define GPIO_PORT_MPIN2_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN2: MPORTP28 Position */ -#define GPIO_PORT_MPIN2_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP28_Pos) /*!< GPIO_PORT MPIN2: MPORTP28 Mask */ -#define GPIO_PORT_MPIN2_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN2: MPORTP29 Position */ -#define GPIO_PORT_MPIN2_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP29_Pos) /*!< GPIO_PORT MPIN2: MPORTP29 Mask */ -#define GPIO_PORT_MPIN2_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN2: MPORTP30 Position */ -#define GPIO_PORT_MPIN2_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP30_Pos) /*!< GPIO_PORT MPIN2: MPORTP30 Mask */ -#define GPIO_PORT_MPIN2_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN2: MPORTP31 Position */ -#define GPIO_PORT_MPIN2_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN2_MPORTP31_Pos) /*!< GPIO_PORT MPIN2: MPORTP31 Mask */ - -// ------------------------------------- GPIO_PORT_MPIN3 ---------------------------------------- -#define GPIO_PORT_MPIN3_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN3: MPORTP0 Position */ -#define GPIO_PORT_MPIN3_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP0_Pos) /*!< GPIO_PORT MPIN3: MPORTP0 Mask */ -#define GPIO_PORT_MPIN3_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN3: MPORTP1 Position */ -#define GPIO_PORT_MPIN3_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP1_Pos) /*!< GPIO_PORT MPIN3: MPORTP1 Mask */ -#define GPIO_PORT_MPIN3_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN3: MPORTP2 Position */ -#define GPIO_PORT_MPIN3_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP2_Pos) /*!< GPIO_PORT MPIN3: MPORTP2 Mask */ -#define GPIO_PORT_MPIN3_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN3: MPORTP3 Position */ -#define GPIO_PORT_MPIN3_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP3_Pos) /*!< GPIO_PORT MPIN3: MPORTP3 Mask */ -#define GPIO_PORT_MPIN3_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN3: MPORTP4 Position */ -#define GPIO_PORT_MPIN3_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP4_Pos) /*!< GPIO_PORT MPIN3: MPORTP4 Mask */ -#define GPIO_PORT_MPIN3_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN3: MPORTP5 Position */ -#define GPIO_PORT_MPIN3_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP5_Pos) /*!< GPIO_PORT MPIN3: MPORTP5 Mask */ -#define GPIO_PORT_MPIN3_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN3: MPORTP6 Position */ -#define GPIO_PORT_MPIN3_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP6_Pos) /*!< GPIO_PORT MPIN3: MPORTP6 Mask */ -#define GPIO_PORT_MPIN3_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN3: MPORTP7 Position */ -#define GPIO_PORT_MPIN3_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP7_Pos) /*!< GPIO_PORT MPIN3: MPORTP7 Mask */ -#define GPIO_PORT_MPIN3_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN3: MPORTP8 Position */ -#define GPIO_PORT_MPIN3_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP8_Pos) /*!< GPIO_PORT MPIN3: MPORTP8 Mask */ -#define GPIO_PORT_MPIN3_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN3: MPORTP9 Position */ -#define GPIO_PORT_MPIN3_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP9_Pos) /*!< GPIO_PORT MPIN3: MPORTP9 Mask */ -#define GPIO_PORT_MPIN3_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN3: MPORTP10 Position */ -#define GPIO_PORT_MPIN3_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP10_Pos) /*!< GPIO_PORT MPIN3: MPORTP10 Mask */ -#define GPIO_PORT_MPIN3_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN3: MPORTP11 Position */ -#define GPIO_PORT_MPIN3_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP11_Pos) /*!< GPIO_PORT MPIN3: MPORTP11 Mask */ -#define GPIO_PORT_MPIN3_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN3: MPORTP12 Position */ -#define GPIO_PORT_MPIN3_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP12_Pos) /*!< GPIO_PORT MPIN3: MPORTP12 Mask */ -#define GPIO_PORT_MPIN3_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN3: MPORTP13 Position */ -#define GPIO_PORT_MPIN3_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP13_Pos) /*!< GPIO_PORT MPIN3: MPORTP13 Mask */ -#define GPIO_PORT_MPIN3_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN3: MPORTP14 Position */ -#define GPIO_PORT_MPIN3_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP14_Pos) /*!< GPIO_PORT MPIN3: MPORTP14 Mask */ -#define GPIO_PORT_MPIN3_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN3: MPORTP15 Position */ -#define GPIO_PORT_MPIN3_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP15_Pos) /*!< GPIO_PORT MPIN3: MPORTP15 Mask */ -#define GPIO_PORT_MPIN3_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN3: MPORTP16 Position */ -#define GPIO_PORT_MPIN3_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP16_Pos) /*!< GPIO_PORT MPIN3: MPORTP16 Mask */ -#define GPIO_PORT_MPIN3_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN3: MPORTP17 Position */ -#define GPIO_PORT_MPIN3_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP17_Pos) /*!< GPIO_PORT MPIN3: MPORTP17 Mask */ -#define GPIO_PORT_MPIN3_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN3: MPORTP18 Position */ -#define GPIO_PORT_MPIN3_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP18_Pos) /*!< GPIO_PORT MPIN3: MPORTP18 Mask */ -#define GPIO_PORT_MPIN3_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN3: MPORTP19 Position */ -#define GPIO_PORT_MPIN3_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP19_Pos) /*!< GPIO_PORT MPIN3: MPORTP19 Mask */ -#define GPIO_PORT_MPIN3_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN3: MPORTP20 Position */ -#define GPIO_PORT_MPIN3_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP20_Pos) /*!< GPIO_PORT MPIN3: MPORTP20 Mask */ -#define GPIO_PORT_MPIN3_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN3: MPORTP21 Position */ -#define GPIO_PORT_MPIN3_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP21_Pos) /*!< GPIO_PORT MPIN3: MPORTP21 Mask */ -#define GPIO_PORT_MPIN3_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN3: MPORTP22 Position */ -#define GPIO_PORT_MPIN3_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP22_Pos) /*!< GPIO_PORT MPIN3: MPORTP22 Mask */ -#define GPIO_PORT_MPIN3_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN3: MPORTP23 Position */ -#define GPIO_PORT_MPIN3_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP23_Pos) /*!< GPIO_PORT MPIN3: MPORTP23 Mask */ -#define GPIO_PORT_MPIN3_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN3: MPORTP24 Position */ -#define GPIO_PORT_MPIN3_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP24_Pos) /*!< GPIO_PORT MPIN3: MPORTP24 Mask */ -#define GPIO_PORT_MPIN3_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN3: MPORTP25 Position */ -#define GPIO_PORT_MPIN3_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP25_Pos) /*!< GPIO_PORT MPIN3: MPORTP25 Mask */ -#define GPIO_PORT_MPIN3_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN3: MPORTP26 Position */ -#define GPIO_PORT_MPIN3_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP26_Pos) /*!< GPIO_PORT MPIN3: MPORTP26 Mask */ -#define GPIO_PORT_MPIN3_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN3: MPORTP27 Position */ -#define GPIO_PORT_MPIN3_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP27_Pos) /*!< GPIO_PORT MPIN3: MPORTP27 Mask */ -#define GPIO_PORT_MPIN3_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN3: MPORTP28 Position */ -#define GPIO_PORT_MPIN3_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP28_Pos) /*!< GPIO_PORT MPIN3: MPORTP28 Mask */ -#define GPIO_PORT_MPIN3_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN3: MPORTP29 Position */ -#define GPIO_PORT_MPIN3_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP29_Pos) /*!< GPIO_PORT MPIN3: MPORTP29 Mask */ -#define GPIO_PORT_MPIN3_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN3: MPORTP30 Position */ -#define GPIO_PORT_MPIN3_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP30_Pos) /*!< GPIO_PORT MPIN3: MPORTP30 Mask */ -#define GPIO_PORT_MPIN3_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN3: MPORTP31 Position */ -#define GPIO_PORT_MPIN3_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN3_MPORTP31_Pos) /*!< GPIO_PORT MPIN3: MPORTP31 Mask */ - -// ------------------------------------- GPIO_PORT_MPIN4 ---------------------------------------- -#define GPIO_PORT_MPIN4_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN4: MPORTP0 Position */ -#define GPIO_PORT_MPIN4_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP0_Pos) /*!< GPIO_PORT MPIN4: MPORTP0 Mask */ -#define GPIO_PORT_MPIN4_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN4: MPORTP1 Position */ -#define GPIO_PORT_MPIN4_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP1_Pos) /*!< GPIO_PORT MPIN4: MPORTP1 Mask */ -#define GPIO_PORT_MPIN4_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN4: MPORTP2 Position */ -#define GPIO_PORT_MPIN4_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP2_Pos) /*!< GPIO_PORT MPIN4: MPORTP2 Mask */ -#define GPIO_PORT_MPIN4_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN4: MPORTP3 Position */ -#define GPIO_PORT_MPIN4_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP3_Pos) /*!< GPIO_PORT MPIN4: MPORTP3 Mask */ -#define GPIO_PORT_MPIN4_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN4: MPORTP4 Position */ -#define GPIO_PORT_MPIN4_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP4_Pos) /*!< GPIO_PORT MPIN4: MPORTP4 Mask */ -#define GPIO_PORT_MPIN4_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN4: MPORTP5 Position */ -#define GPIO_PORT_MPIN4_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP5_Pos) /*!< GPIO_PORT MPIN4: MPORTP5 Mask */ -#define GPIO_PORT_MPIN4_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN4: MPORTP6 Position */ -#define GPIO_PORT_MPIN4_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP6_Pos) /*!< GPIO_PORT MPIN4: MPORTP6 Mask */ -#define GPIO_PORT_MPIN4_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN4: MPORTP7 Position */ -#define GPIO_PORT_MPIN4_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP7_Pos) /*!< GPIO_PORT MPIN4: MPORTP7 Mask */ -#define GPIO_PORT_MPIN4_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN4: MPORTP8 Position */ -#define GPIO_PORT_MPIN4_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP8_Pos) /*!< GPIO_PORT MPIN4: MPORTP8 Mask */ -#define GPIO_PORT_MPIN4_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN4: MPORTP9 Position */ -#define GPIO_PORT_MPIN4_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP9_Pos) /*!< GPIO_PORT MPIN4: MPORTP9 Mask */ -#define GPIO_PORT_MPIN4_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN4: MPORTP10 Position */ -#define GPIO_PORT_MPIN4_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP10_Pos) /*!< GPIO_PORT MPIN4: MPORTP10 Mask */ -#define GPIO_PORT_MPIN4_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN4: MPORTP11 Position */ -#define GPIO_PORT_MPIN4_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP11_Pos) /*!< GPIO_PORT MPIN4: MPORTP11 Mask */ -#define GPIO_PORT_MPIN4_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN4: MPORTP12 Position */ -#define GPIO_PORT_MPIN4_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP12_Pos) /*!< GPIO_PORT MPIN4: MPORTP12 Mask */ -#define GPIO_PORT_MPIN4_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN4: MPORTP13 Position */ -#define GPIO_PORT_MPIN4_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP13_Pos) /*!< GPIO_PORT MPIN4: MPORTP13 Mask */ -#define GPIO_PORT_MPIN4_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN4: MPORTP14 Position */ -#define GPIO_PORT_MPIN4_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP14_Pos) /*!< GPIO_PORT MPIN4: MPORTP14 Mask */ -#define GPIO_PORT_MPIN4_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN4: MPORTP15 Position */ -#define GPIO_PORT_MPIN4_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP15_Pos) /*!< GPIO_PORT MPIN4: MPORTP15 Mask */ -#define GPIO_PORT_MPIN4_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN4: MPORTP16 Position */ -#define GPIO_PORT_MPIN4_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP16_Pos) /*!< GPIO_PORT MPIN4: MPORTP16 Mask */ -#define GPIO_PORT_MPIN4_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN4: MPORTP17 Position */ -#define GPIO_PORT_MPIN4_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP17_Pos) /*!< GPIO_PORT MPIN4: MPORTP17 Mask */ -#define GPIO_PORT_MPIN4_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN4: MPORTP18 Position */ -#define GPIO_PORT_MPIN4_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP18_Pos) /*!< GPIO_PORT MPIN4: MPORTP18 Mask */ -#define GPIO_PORT_MPIN4_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN4: MPORTP19 Position */ -#define GPIO_PORT_MPIN4_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP19_Pos) /*!< GPIO_PORT MPIN4: MPORTP19 Mask */ -#define GPIO_PORT_MPIN4_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN4: MPORTP20 Position */ -#define GPIO_PORT_MPIN4_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP20_Pos) /*!< GPIO_PORT MPIN4: MPORTP20 Mask */ -#define GPIO_PORT_MPIN4_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN4: MPORTP21 Position */ -#define GPIO_PORT_MPIN4_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP21_Pos) /*!< GPIO_PORT MPIN4: MPORTP21 Mask */ -#define GPIO_PORT_MPIN4_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN4: MPORTP22 Position */ -#define GPIO_PORT_MPIN4_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP22_Pos) /*!< GPIO_PORT MPIN4: MPORTP22 Mask */ -#define GPIO_PORT_MPIN4_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN4: MPORTP23 Position */ -#define GPIO_PORT_MPIN4_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP23_Pos) /*!< GPIO_PORT MPIN4: MPORTP23 Mask */ -#define GPIO_PORT_MPIN4_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN4: MPORTP24 Position */ -#define GPIO_PORT_MPIN4_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP24_Pos) /*!< GPIO_PORT MPIN4: MPORTP24 Mask */ -#define GPIO_PORT_MPIN4_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN4: MPORTP25 Position */ -#define GPIO_PORT_MPIN4_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP25_Pos) /*!< GPIO_PORT MPIN4: MPORTP25 Mask */ -#define GPIO_PORT_MPIN4_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN4: MPORTP26 Position */ -#define GPIO_PORT_MPIN4_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP26_Pos) /*!< GPIO_PORT MPIN4: MPORTP26 Mask */ -#define GPIO_PORT_MPIN4_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN4: MPORTP27 Position */ -#define GPIO_PORT_MPIN4_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP27_Pos) /*!< GPIO_PORT MPIN4: MPORTP27 Mask */ -#define GPIO_PORT_MPIN4_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN4: MPORTP28 Position */ -#define GPIO_PORT_MPIN4_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP28_Pos) /*!< GPIO_PORT MPIN4: MPORTP28 Mask */ -#define GPIO_PORT_MPIN4_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN4: MPORTP29 Position */ -#define GPIO_PORT_MPIN4_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP29_Pos) /*!< GPIO_PORT MPIN4: MPORTP29 Mask */ -#define GPIO_PORT_MPIN4_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN4: MPORTP30 Position */ -#define GPIO_PORT_MPIN4_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP30_Pos) /*!< GPIO_PORT MPIN4: MPORTP30 Mask */ -#define GPIO_PORT_MPIN4_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN4: MPORTP31 Position */ -#define GPIO_PORT_MPIN4_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN4_MPORTP31_Pos) /*!< GPIO_PORT MPIN4: MPORTP31 Mask */ - -// ------------------------------------- GPIO_PORT_MPIN5 ---------------------------------------- -#define GPIO_PORT_MPIN5_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN5: MPORTP0 Position */ -#define GPIO_PORT_MPIN5_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP0_Pos) /*!< GPIO_PORT MPIN5: MPORTP0 Mask */ -#define GPIO_PORT_MPIN5_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN5: MPORTP1 Position */ -#define GPIO_PORT_MPIN5_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP1_Pos) /*!< GPIO_PORT MPIN5: MPORTP1 Mask */ -#define GPIO_PORT_MPIN5_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN5: MPORTP2 Position */ -#define GPIO_PORT_MPIN5_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP2_Pos) /*!< GPIO_PORT MPIN5: MPORTP2 Mask */ -#define GPIO_PORT_MPIN5_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN5: MPORTP3 Position */ -#define GPIO_PORT_MPIN5_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP3_Pos) /*!< GPIO_PORT MPIN5: MPORTP3 Mask */ -#define GPIO_PORT_MPIN5_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN5: MPORTP4 Position */ -#define GPIO_PORT_MPIN5_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP4_Pos) /*!< GPIO_PORT MPIN5: MPORTP4 Mask */ -#define GPIO_PORT_MPIN5_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN5: MPORTP5 Position */ -#define GPIO_PORT_MPIN5_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP5_Pos) /*!< GPIO_PORT MPIN5: MPORTP5 Mask */ -#define GPIO_PORT_MPIN5_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN5: MPORTP6 Position */ -#define GPIO_PORT_MPIN5_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP6_Pos) /*!< GPIO_PORT MPIN5: MPORTP6 Mask */ -#define GPIO_PORT_MPIN5_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN5: MPORTP7 Position */ -#define GPIO_PORT_MPIN5_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP7_Pos) /*!< GPIO_PORT MPIN5: MPORTP7 Mask */ -#define GPIO_PORT_MPIN5_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN5: MPORTP8 Position */ -#define GPIO_PORT_MPIN5_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP8_Pos) /*!< GPIO_PORT MPIN5: MPORTP8 Mask */ -#define GPIO_PORT_MPIN5_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN5: MPORTP9 Position */ -#define GPIO_PORT_MPIN5_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP9_Pos) /*!< GPIO_PORT MPIN5: MPORTP9 Mask */ -#define GPIO_PORT_MPIN5_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN5: MPORTP10 Position */ -#define GPIO_PORT_MPIN5_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP10_Pos) /*!< GPIO_PORT MPIN5: MPORTP10 Mask */ -#define GPIO_PORT_MPIN5_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN5: MPORTP11 Position */ -#define GPIO_PORT_MPIN5_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP11_Pos) /*!< GPIO_PORT MPIN5: MPORTP11 Mask */ -#define GPIO_PORT_MPIN5_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN5: MPORTP12 Position */ -#define GPIO_PORT_MPIN5_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP12_Pos) /*!< GPIO_PORT MPIN5: MPORTP12 Mask */ -#define GPIO_PORT_MPIN5_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN5: MPORTP13 Position */ -#define GPIO_PORT_MPIN5_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP13_Pos) /*!< GPIO_PORT MPIN5: MPORTP13 Mask */ -#define GPIO_PORT_MPIN5_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN5: MPORTP14 Position */ -#define GPIO_PORT_MPIN5_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP14_Pos) /*!< GPIO_PORT MPIN5: MPORTP14 Mask */ -#define GPIO_PORT_MPIN5_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN5: MPORTP15 Position */ -#define GPIO_PORT_MPIN5_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP15_Pos) /*!< GPIO_PORT MPIN5: MPORTP15 Mask */ -#define GPIO_PORT_MPIN5_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN5: MPORTP16 Position */ -#define GPIO_PORT_MPIN5_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP16_Pos) /*!< GPIO_PORT MPIN5: MPORTP16 Mask */ -#define GPIO_PORT_MPIN5_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN5: MPORTP17 Position */ -#define GPIO_PORT_MPIN5_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP17_Pos) /*!< GPIO_PORT MPIN5: MPORTP17 Mask */ -#define GPIO_PORT_MPIN5_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN5: MPORTP18 Position */ -#define GPIO_PORT_MPIN5_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP18_Pos) /*!< GPIO_PORT MPIN5: MPORTP18 Mask */ -#define GPIO_PORT_MPIN5_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN5: MPORTP19 Position */ -#define GPIO_PORT_MPIN5_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP19_Pos) /*!< GPIO_PORT MPIN5: MPORTP19 Mask */ -#define GPIO_PORT_MPIN5_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN5: MPORTP20 Position */ -#define GPIO_PORT_MPIN5_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP20_Pos) /*!< GPIO_PORT MPIN5: MPORTP20 Mask */ -#define GPIO_PORT_MPIN5_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN5: MPORTP21 Position */ -#define GPIO_PORT_MPIN5_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP21_Pos) /*!< GPIO_PORT MPIN5: MPORTP21 Mask */ -#define GPIO_PORT_MPIN5_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN5: MPORTP22 Position */ -#define GPIO_PORT_MPIN5_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP22_Pos) /*!< GPIO_PORT MPIN5: MPORTP22 Mask */ -#define GPIO_PORT_MPIN5_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN5: MPORTP23 Position */ -#define GPIO_PORT_MPIN5_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP23_Pos) /*!< GPIO_PORT MPIN5: MPORTP23 Mask */ -#define GPIO_PORT_MPIN5_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN5: MPORTP24 Position */ -#define GPIO_PORT_MPIN5_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP24_Pos) /*!< GPIO_PORT MPIN5: MPORTP24 Mask */ -#define GPIO_PORT_MPIN5_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN5: MPORTP25 Position */ -#define GPIO_PORT_MPIN5_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP25_Pos) /*!< GPIO_PORT MPIN5: MPORTP25 Mask */ -#define GPIO_PORT_MPIN5_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN5: MPORTP26 Position */ -#define GPIO_PORT_MPIN5_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP26_Pos) /*!< GPIO_PORT MPIN5: MPORTP26 Mask */ -#define GPIO_PORT_MPIN5_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN5: MPORTP27 Position */ -#define GPIO_PORT_MPIN5_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP27_Pos) /*!< GPIO_PORT MPIN5: MPORTP27 Mask */ -#define GPIO_PORT_MPIN5_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN5: MPORTP28 Position */ -#define GPIO_PORT_MPIN5_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP28_Pos) /*!< GPIO_PORT MPIN5: MPORTP28 Mask */ -#define GPIO_PORT_MPIN5_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN5: MPORTP29 Position */ -#define GPIO_PORT_MPIN5_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP29_Pos) /*!< GPIO_PORT MPIN5: MPORTP29 Mask */ -#define GPIO_PORT_MPIN5_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN5: MPORTP30 Position */ -#define GPIO_PORT_MPIN5_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP30_Pos) /*!< GPIO_PORT MPIN5: MPORTP30 Mask */ -#define GPIO_PORT_MPIN5_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN5: MPORTP31 Position */ -#define GPIO_PORT_MPIN5_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN5_MPORTP31_Pos) /*!< GPIO_PORT MPIN5: MPORTP31 Mask */ - -// ------------------------------------- GPIO_PORT_MPIN6 ---------------------------------------- -#define GPIO_PORT_MPIN6_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN6: MPORTP0 Position */ -#define GPIO_PORT_MPIN6_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP0_Pos) /*!< GPIO_PORT MPIN6: MPORTP0 Mask */ -#define GPIO_PORT_MPIN6_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN6: MPORTP1 Position */ -#define GPIO_PORT_MPIN6_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP1_Pos) /*!< GPIO_PORT MPIN6: MPORTP1 Mask */ -#define GPIO_PORT_MPIN6_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN6: MPORTP2 Position */ -#define GPIO_PORT_MPIN6_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP2_Pos) /*!< GPIO_PORT MPIN6: MPORTP2 Mask */ -#define GPIO_PORT_MPIN6_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN6: MPORTP3 Position */ -#define GPIO_PORT_MPIN6_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP3_Pos) /*!< GPIO_PORT MPIN6: MPORTP3 Mask */ -#define GPIO_PORT_MPIN6_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN6: MPORTP4 Position */ -#define GPIO_PORT_MPIN6_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP4_Pos) /*!< GPIO_PORT MPIN6: MPORTP4 Mask */ -#define GPIO_PORT_MPIN6_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN6: MPORTP5 Position */ -#define GPIO_PORT_MPIN6_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP5_Pos) /*!< GPIO_PORT MPIN6: MPORTP5 Mask */ -#define GPIO_PORT_MPIN6_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN6: MPORTP6 Position */ -#define GPIO_PORT_MPIN6_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP6_Pos) /*!< GPIO_PORT MPIN6: MPORTP6 Mask */ -#define GPIO_PORT_MPIN6_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN6: MPORTP7 Position */ -#define GPIO_PORT_MPIN6_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP7_Pos) /*!< GPIO_PORT MPIN6: MPORTP7 Mask */ -#define GPIO_PORT_MPIN6_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN6: MPORTP8 Position */ -#define GPIO_PORT_MPIN6_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP8_Pos) /*!< GPIO_PORT MPIN6: MPORTP8 Mask */ -#define GPIO_PORT_MPIN6_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN6: MPORTP9 Position */ -#define GPIO_PORT_MPIN6_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP9_Pos) /*!< GPIO_PORT MPIN6: MPORTP9 Mask */ -#define GPIO_PORT_MPIN6_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN6: MPORTP10 Position */ -#define GPIO_PORT_MPIN6_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP10_Pos) /*!< GPIO_PORT MPIN6: MPORTP10 Mask */ -#define GPIO_PORT_MPIN6_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN6: MPORTP11 Position */ -#define GPIO_PORT_MPIN6_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP11_Pos) /*!< GPIO_PORT MPIN6: MPORTP11 Mask */ -#define GPIO_PORT_MPIN6_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN6: MPORTP12 Position */ -#define GPIO_PORT_MPIN6_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP12_Pos) /*!< GPIO_PORT MPIN6: MPORTP12 Mask */ -#define GPIO_PORT_MPIN6_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN6: MPORTP13 Position */ -#define GPIO_PORT_MPIN6_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP13_Pos) /*!< GPIO_PORT MPIN6: MPORTP13 Mask */ -#define GPIO_PORT_MPIN6_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN6: MPORTP14 Position */ -#define GPIO_PORT_MPIN6_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP14_Pos) /*!< GPIO_PORT MPIN6: MPORTP14 Mask */ -#define GPIO_PORT_MPIN6_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN6: MPORTP15 Position */ -#define GPIO_PORT_MPIN6_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP15_Pos) /*!< GPIO_PORT MPIN6: MPORTP15 Mask */ -#define GPIO_PORT_MPIN6_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN6: MPORTP16 Position */ -#define GPIO_PORT_MPIN6_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP16_Pos) /*!< GPIO_PORT MPIN6: MPORTP16 Mask */ -#define GPIO_PORT_MPIN6_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN6: MPORTP17 Position */ -#define GPIO_PORT_MPIN6_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP17_Pos) /*!< GPIO_PORT MPIN6: MPORTP17 Mask */ -#define GPIO_PORT_MPIN6_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN6: MPORTP18 Position */ -#define GPIO_PORT_MPIN6_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP18_Pos) /*!< GPIO_PORT MPIN6: MPORTP18 Mask */ -#define GPIO_PORT_MPIN6_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN6: MPORTP19 Position */ -#define GPIO_PORT_MPIN6_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP19_Pos) /*!< GPIO_PORT MPIN6: MPORTP19 Mask */ -#define GPIO_PORT_MPIN6_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN6: MPORTP20 Position */ -#define GPIO_PORT_MPIN6_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP20_Pos) /*!< GPIO_PORT MPIN6: MPORTP20 Mask */ -#define GPIO_PORT_MPIN6_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN6: MPORTP21 Position */ -#define GPIO_PORT_MPIN6_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP21_Pos) /*!< GPIO_PORT MPIN6: MPORTP21 Mask */ -#define GPIO_PORT_MPIN6_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN6: MPORTP22 Position */ -#define GPIO_PORT_MPIN6_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP22_Pos) /*!< GPIO_PORT MPIN6: MPORTP22 Mask */ -#define GPIO_PORT_MPIN6_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN6: MPORTP23 Position */ -#define GPIO_PORT_MPIN6_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP23_Pos) /*!< GPIO_PORT MPIN6: MPORTP23 Mask */ -#define GPIO_PORT_MPIN6_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN6: MPORTP24 Position */ -#define GPIO_PORT_MPIN6_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP24_Pos) /*!< GPIO_PORT MPIN6: MPORTP24 Mask */ -#define GPIO_PORT_MPIN6_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN6: MPORTP25 Position */ -#define GPIO_PORT_MPIN6_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP25_Pos) /*!< GPIO_PORT MPIN6: MPORTP25 Mask */ -#define GPIO_PORT_MPIN6_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN6: MPORTP26 Position */ -#define GPIO_PORT_MPIN6_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP26_Pos) /*!< GPIO_PORT MPIN6: MPORTP26 Mask */ -#define GPIO_PORT_MPIN6_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN6: MPORTP27 Position */ -#define GPIO_PORT_MPIN6_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP27_Pos) /*!< GPIO_PORT MPIN6: MPORTP27 Mask */ -#define GPIO_PORT_MPIN6_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN6: MPORTP28 Position */ -#define GPIO_PORT_MPIN6_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP28_Pos) /*!< GPIO_PORT MPIN6: MPORTP28 Mask */ -#define GPIO_PORT_MPIN6_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN6: MPORTP29 Position */ -#define GPIO_PORT_MPIN6_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP29_Pos) /*!< GPIO_PORT MPIN6: MPORTP29 Mask */ -#define GPIO_PORT_MPIN6_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN6: MPORTP30 Position */ -#define GPIO_PORT_MPIN6_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP30_Pos) /*!< GPIO_PORT MPIN6: MPORTP30 Mask */ -#define GPIO_PORT_MPIN6_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN6: MPORTP31 Position */ -#define GPIO_PORT_MPIN6_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN6_MPORTP31_Pos) /*!< GPIO_PORT MPIN6: MPORTP31 Mask */ - -// ------------------------------------- GPIO_PORT_MPIN7 ---------------------------------------- -#define GPIO_PORT_MPIN7_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN7: MPORTP0 Position */ -#define GPIO_PORT_MPIN7_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP0_Pos) /*!< GPIO_PORT MPIN7: MPORTP0 Mask */ -#define GPIO_PORT_MPIN7_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN7: MPORTP1 Position */ -#define GPIO_PORT_MPIN7_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP1_Pos) /*!< GPIO_PORT MPIN7: MPORTP1 Mask */ -#define GPIO_PORT_MPIN7_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN7: MPORTP2 Position */ -#define GPIO_PORT_MPIN7_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP2_Pos) /*!< GPIO_PORT MPIN7: MPORTP2 Mask */ -#define GPIO_PORT_MPIN7_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN7: MPORTP3 Position */ -#define GPIO_PORT_MPIN7_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP3_Pos) /*!< GPIO_PORT MPIN7: MPORTP3 Mask */ -#define GPIO_PORT_MPIN7_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN7: MPORTP4 Position */ -#define GPIO_PORT_MPIN7_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP4_Pos) /*!< GPIO_PORT MPIN7: MPORTP4 Mask */ -#define GPIO_PORT_MPIN7_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN7: MPORTP5 Position */ -#define GPIO_PORT_MPIN7_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP5_Pos) /*!< GPIO_PORT MPIN7: MPORTP5 Mask */ -#define GPIO_PORT_MPIN7_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN7: MPORTP6 Position */ -#define GPIO_PORT_MPIN7_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP6_Pos) /*!< GPIO_PORT MPIN7: MPORTP6 Mask */ -#define GPIO_PORT_MPIN7_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN7: MPORTP7 Position */ -#define GPIO_PORT_MPIN7_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP7_Pos) /*!< GPIO_PORT MPIN7: MPORTP7 Mask */ -#define GPIO_PORT_MPIN7_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN7: MPORTP8 Position */ -#define GPIO_PORT_MPIN7_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP8_Pos) /*!< GPIO_PORT MPIN7: MPORTP8 Mask */ -#define GPIO_PORT_MPIN7_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN7: MPORTP9 Position */ -#define GPIO_PORT_MPIN7_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP9_Pos) /*!< GPIO_PORT MPIN7: MPORTP9 Mask */ -#define GPIO_PORT_MPIN7_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN7: MPORTP10 Position */ -#define GPIO_PORT_MPIN7_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP10_Pos) /*!< GPIO_PORT MPIN7: MPORTP10 Mask */ -#define GPIO_PORT_MPIN7_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN7: MPORTP11 Position */ -#define GPIO_PORT_MPIN7_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP11_Pos) /*!< GPIO_PORT MPIN7: MPORTP11 Mask */ -#define GPIO_PORT_MPIN7_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN7: MPORTP12 Position */ -#define GPIO_PORT_MPIN7_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP12_Pos) /*!< GPIO_PORT MPIN7: MPORTP12 Mask */ -#define GPIO_PORT_MPIN7_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN7: MPORTP13 Position */ -#define GPIO_PORT_MPIN7_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP13_Pos) /*!< GPIO_PORT MPIN7: MPORTP13 Mask */ -#define GPIO_PORT_MPIN7_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN7: MPORTP14 Position */ -#define GPIO_PORT_MPIN7_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP14_Pos) /*!< GPIO_PORT MPIN7: MPORTP14 Mask */ -#define GPIO_PORT_MPIN7_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN7: MPORTP15 Position */ -#define GPIO_PORT_MPIN7_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP15_Pos) /*!< GPIO_PORT MPIN7: MPORTP15 Mask */ -#define GPIO_PORT_MPIN7_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN7: MPORTP16 Position */ -#define GPIO_PORT_MPIN7_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP16_Pos) /*!< GPIO_PORT MPIN7: MPORTP16 Mask */ -#define GPIO_PORT_MPIN7_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN7: MPORTP17 Position */ -#define GPIO_PORT_MPIN7_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP17_Pos) /*!< GPIO_PORT MPIN7: MPORTP17 Mask */ -#define GPIO_PORT_MPIN7_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN7: MPORTP18 Position */ -#define GPIO_PORT_MPIN7_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP18_Pos) /*!< GPIO_PORT MPIN7: MPORTP18 Mask */ -#define GPIO_PORT_MPIN7_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN7: MPORTP19 Position */ -#define GPIO_PORT_MPIN7_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP19_Pos) /*!< GPIO_PORT MPIN7: MPORTP19 Mask */ -#define GPIO_PORT_MPIN7_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN7: MPORTP20 Position */ -#define GPIO_PORT_MPIN7_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP20_Pos) /*!< GPIO_PORT MPIN7: MPORTP20 Mask */ -#define GPIO_PORT_MPIN7_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN7: MPORTP21 Position */ -#define GPIO_PORT_MPIN7_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP21_Pos) /*!< GPIO_PORT MPIN7: MPORTP21 Mask */ -#define GPIO_PORT_MPIN7_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN7: MPORTP22 Position */ -#define GPIO_PORT_MPIN7_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP22_Pos) /*!< GPIO_PORT MPIN7: MPORTP22 Mask */ -#define GPIO_PORT_MPIN7_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN7: MPORTP23 Position */ -#define GPIO_PORT_MPIN7_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP23_Pos) /*!< GPIO_PORT MPIN7: MPORTP23 Mask */ -#define GPIO_PORT_MPIN7_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN7: MPORTP24 Position */ -#define GPIO_PORT_MPIN7_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP24_Pos) /*!< GPIO_PORT MPIN7: MPORTP24 Mask */ -#define GPIO_PORT_MPIN7_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN7: MPORTP25 Position */ -#define GPIO_PORT_MPIN7_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP25_Pos) /*!< GPIO_PORT MPIN7: MPORTP25 Mask */ -#define GPIO_PORT_MPIN7_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN7: MPORTP26 Position */ -#define GPIO_PORT_MPIN7_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP26_Pos) /*!< GPIO_PORT MPIN7: MPORTP26 Mask */ -#define GPIO_PORT_MPIN7_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN7: MPORTP27 Position */ -#define GPIO_PORT_MPIN7_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP27_Pos) /*!< GPIO_PORT MPIN7: MPORTP27 Mask */ -#define GPIO_PORT_MPIN7_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN7: MPORTP28 Position */ -#define GPIO_PORT_MPIN7_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP28_Pos) /*!< GPIO_PORT MPIN7: MPORTP28 Mask */ -#define GPIO_PORT_MPIN7_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN7: MPORTP29 Position */ -#define GPIO_PORT_MPIN7_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP29_Pos) /*!< GPIO_PORT MPIN7: MPORTP29 Mask */ -#define GPIO_PORT_MPIN7_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN7: MPORTP30 Position */ -#define GPIO_PORT_MPIN7_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP30_Pos) /*!< GPIO_PORT MPIN7: MPORTP30 Mask */ -#define GPIO_PORT_MPIN7_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN7: MPORTP31 Position */ -#define GPIO_PORT_MPIN7_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN7_MPORTP31_Pos) /*!< GPIO_PORT MPIN7: MPORTP31 Mask */ - -// ------------------------------------- GPIO_PORT_SET0 ----------------------------------------- -#define GPIO_PORT_SET0_SETP0_Pos 0 /*!< GPIO_PORT SET0: SETP0 Position */ -#define GPIO_PORT_SET0_SETP0_Msk (0x01UL << GPIO_PORT_SET0_SETP0_Pos) /*!< GPIO_PORT SET0: SETP0 Mask */ -#define GPIO_PORT_SET0_SETP1_Pos 1 /*!< GPIO_PORT SET0: SETP1 Position */ -#define GPIO_PORT_SET0_SETP1_Msk (0x01UL << GPIO_PORT_SET0_SETP1_Pos) /*!< GPIO_PORT SET0: SETP1 Mask */ -#define GPIO_PORT_SET0_SETP2_Pos 2 /*!< GPIO_PORT SET0: SETP2 Position */ -#define GPIO_PORT_SET0_SETP2_Msk (0x01UL << GPIO_PORT_SET0_SETP2_Pos) /*!< GPIO_PORT SET0: SETP2 Mask */ -#define GPIO_PORT_SET0_SETP3_Pos 3 /*!< GPIO_PORT SET0: SETP3 Position */ -#define GPIO_PORT_SET0_SETP3_Msk (0x01UL << GPIO_PORT_SET0_SETP3_Pos) /*!< GPIO_PORT SET0: SETP3 Mask */ -#define GPIO_PORT_SET0_SETP4_Pos 4 /*!< GPIO_PORT SET0: SETP4 Position */ -#define GPIO_PORT_SET0_SETP4_Msk (0x01UL << GPIO_PORT_SET0_SETP4_Pos) /*!< GPIO_PORT SET0: SETP4 Mask */ -#define GPIO_PORT_SET0_SETP5_Pos 5 /*!< GPIO_PORT SET0: SETP5 Position */ -#define GPIO_PORT_SET0_SETP5_Msk (0x01UL << GPIO_PORT_SET0_SETP5_Pos) /*!< GPIO_PORT SET0: SETP5 Mask */ -#define GPIO_PORT_SET0_SETP6_Pos 6 /*!< GPIO_PORT SET0: SETP6 Position */ -#define GPIO_PORT_SET0_SETP6_Msk (0x01UL << GPIO_PORT_SET0_SETP6_Pos) /*!< GPIO_PORT SET0: SETP6 Mask */ -#define GPIO_PORT_SET0_SETP7_Pos 7 /*!< GPIO_PORT SET0: SETP7 Position */ -#define GPIO_PORT_SET0_SETP7_Msk (0x01UL << GPIO_PORT_SET0_SETP7_Pos) /*!< GPIO_PORT SET0: SETP7 Mask */ -#define GPIO_PORT_SET0_SETP8_Pos 8 /*!< GPIO_PORT SET0: SETP8 Position */ -#define GPIO_PORT_SET0_SETP8_Msk (0x01UL << GPIO_PORT_SET0_SETP8_Pos) /*!< GPIO_PORT SET0: SETP8 Mask */ -#define GPIO_PORT_SET0_SETP9_Pos 9 /*!< GPIO_PORT SET0: SETP9 Position */ -#define GPIO_PORT_SET0_SETP9_Msk (0x01UL << GPIO_PORT_SET0_SETP9_Pos) /*!< GPIO_PORT SET0: SETP9 Mask */ -#define GPIO_PORT_SET0_SETP10_Pos 10 /*!< GPIO_PORT SET0: SETP10 Position */ -#define GPIO_PORT_SET0_SETP10_Msk (0x01UL << GPIO_PORT_SET0_SETP10_Pos) /*!< GPIO_PORT SET0: SETP10 Mask */ -#define GPIO_PORT_SET0_SETP11_Pos 11 /*!< GPIO_PORT SET0: SETP11 Position */ -#define GPIO_PORT_SET0_SETP11_Msk (0x01UL << GPIO_PORT_SET0_SETP11_Pos) /*!< GPIO_PORT SET0: SETP11 Mask */ -#define GPIO_PORT_SET0_SETP12_Pos 12 /*!< GPIO_PORT SET0: SETP12 Position */ -#define GPIO_PORT_SET0_SETP12_Msk (0x01UL << GPIO_PORT_SET0_SETP12_Pos) /*!< GPIO_PORT SET0: SETP12 Mask */ -#define GPIO_PORT_SET0_SETP13_Pos 13 /*!< GPIO_PORT SET0: SETP13 Position */ -#define GPIO_PORT_SET0_SETP13_Msk (0x01UL << GPIO_PORT_SET0_SETP13_Pos) /*!< GPIO_PORT SET0: SETP13 Mask */ -#define GPIO_PORT_SET0_SETP14_Pos 14 /*!< GPIO_PORT SET0: SETP14 Position */ -#define GPIO_PORT_SET0_SETP14_Msk (0x01UL << GPIO_PORT_SET0_SETP14_Pos) /*!< GPIO_PORT SET0: SETP14 Mask */ -#define GPIO_PORT_SET0_SETP15_Pos 15 /*!< GPIO_PORT SET0: SETP15 Position */ -#define GPIO_PORT_SET0_SETP15_Msk (0x01UL << GPIO_PORT_SET0_SETP15_Pos) /*!< GPIO_PORT SET0: SETP15 Mask */ -#define GPIO_PORT_SET0_SETP16_Pos 16 /*!< GPIO_PORT SET0: SETP16 Position */ -#define GPIO_PORT_SET0_SETP16_Msk (0x01UL << GPIO_PORT_SET0_SETP16_Pos) /*!< GPIO_PORT SET0: SETP16 Mask */ -#define GPIO_PORT_SET0_SETP17_Pos 17 /*!< GPIO_PORT SET0: SETP17 Position */ -#define GPIO_PORT_SET0_SETP17_Msk (0x01UL << GPIO_PORT_SET0_SETP17_Pos) /*!< GPIO_PORT SET0: SETP17 Mask */ -#define GPIO_PORT_SET0_SETP18_Pos 18 /*!< GPIO_PORT SET0: SETP18 Position */ -#define GPIO_PORT_SET0_SETP18_Msk (0x01UL << GPIO_PORT_SET0_SETP18_Pos) /*!< GPIO_PORT SET0: SETP18 Mask */ -#define GPIO_PORT_SET0_SETP19_Pos 19 /*!< GPIO_PORT SET0: SETP19 Position */ -#define GPIO_PORT_SET0_SETP19_Msk (0x01UL << GPIO_PORT_SET0_SETP19_Pos) /*!< GPIO_PORT SET0: SETP19 Mask */ -#define GPIO_PORT_SET0_SETP20_Pos 20 /*!< GPIO_PORT SET0: SETP20 Position */ -#define GPIO_PORT_SET0_SETP20_Msk (0x01UL << GPIO_PORT_SET0_SETP20_Pos) /*!< GPIO_PORT SET0: SETP20 Mask */ -#define GPIO_PORT_SET0_SETP21_Pos 21 /*!< GPIO_PORT SET0: SETP21 Position */ -#define GPIO_PORT_SET0_SETP21_Msk (0x01UL << GPIO_PORT_SET0_SETP21_Pos) /*!< GPIO_PORT SET0: SETP21 Mask */ -#define GPIO_PORT_SET0_SETP22_Pos 22 /*!< GPIO_PORT SET0: SETP22 Position */ -#define GPIO_PORT_SET0_SETP22_Msk (0x01UL << GPIO_PORT_SET0_SETP22_Pos) /*!< GPIO_PORT SET0: SETP22 Mask */ -#define GPIO_PORT_SET0_SETP23_Pos 23 /*!< GPIO_PORT SET0: SETP23 Position */ -#define GPIO_PORT_SET0_SETP23_Msk (0x01UL << GPIO_PORT_SET0_SETP23_Pos) /*!< GPIO_PORT SET0: SETP23 Mask */ -#define GPIO_PORT_SET0_SETP24_Pos 24 /*!< GPIO_PORT SET0: SETP24 Position */ -#define GPIO_PORT_SET0_SETP24_Msk (0x01UL << GPIO_PORT_SET0_SETP24_Pos) /*!< GPIO_PORT SET0: SETP24 Mask */ -#define GPIO_PORT_SET0_SETP25_Pos 25 /*!< GPIO_PORT SET0: SETP25 Position */ -#define GPIO_PORT_SET0_SETP25_Msk (0x01UL << GPIO_PORT_SET0_SETP25_Pos) /*!< GPIO_PORT SET0: SETP25 Mask */ -#define GPIO_PORT_SET0_SETP26_Pos 26 /*!< GPIO_PORT SET0: SETP26 Position */ -#define GPIO_PORT_SET0_SETP26_Msk (0x01UL << GPIO_PORT_SET0_SETP26_Pos) /*!< GPIO_PORT SET0: SETP26 Mask */ -#define GPIO_PORT_SET0_SETP27_Pos 27 /*!< GPIO_PORT SET0: SETP27 Position */ -#define GPIO_PORT_SET0_SETP27_Msk (0x01UL << GPIO_PORT_SET0_SETP27_Pos) /*!< GPIO_PORT SET0: SETP27 Mask */ -#define GPIO_PORT_SET0_SETP28_Pos 28 /*!< GPIO_PORT SET0: SETP28 Position */ -#define GPIO_PORT_SET0_SETP28_Msk (0x01UL << GPIO_PORT_SET0_SETP28_Pos) /*!< GPIO_PORT SET0: SETP28 Mask */ -#define GPIO_PORT_SET0_SETP29_Pos 29 /*!< GPIO_PORT SET0: SETP29 Position */ -#define GPIO_PORT_SET0_SETP29_Msk (0x01UL << GPIO_PORT_SET0_SETP29_Pos) /*!< GPIO_PORT SET0: SETP29 Mask */ -#define GPIO_PORT_SET0_SETP30_Pos 30 /*!< GPIO_PORT SET0: SETP30 Position */ -#define GPIO_PORT_SET0_SETP30_Msk (0x01UL << GPIO_PORT_SET0_SETP30_Pos) /*!< GPIO_PORT SET0: SETP30 Mask */ -#define GPIO_PORT_SET0_SETP31_Pos 31 /*!< GPIO_PORT SET0: SETP31 Position */ -#define GPIO_PORT_SET0_SETP31_Msk (0x01UL << GPIO_PORT_SET0_SETP31_Pos) /*!< GPIO_PORT SET0: SETP31 Mask */ - -// ------------------------------------- GPIO_PORT_SET1 ----------------------------------------- -#define GPIO_PORT_SET1_SETP0_Pos 0 /*!< GPIO_PORT SET1: SETP0 Position */ -#define GPIO_PORT_SET1_SETP0_Msk (0x01UL << GPIO_PORT_SET1_SETP0_Pos) /*!< GPIO_PORT SET1: SETP0 Mask */ -#define GPIO_PORT_SET1_SETP1_Pos 1 /*!< GPIO_PORT SET1: SETP1 Position */ -#define GPIO_PORT_SET1_SETP1_Msk (0x01UL << GPIO_PORT_SET1_SETP1_Pos) /*!< GPIO_PORT SET1: SETP1 Mask */ -#define GPIO_PORT_SET1_SETP2_Pos 2 /*!< GPIO_PORT SET1: SETP2 Position */ -#define GPIO_PORT_SET1_SETP2_Msk (0x01UL << GPIO_PORT_SET1_SETP2_Pos) /*!< GPIO_PORT SET1: SETP2 Mask */ -#define GPIO_PORT_SET1_SETP3_Pos 3 /*!< GPIO_PORT SET1: SETP3 Position */ -#define GPIO_PORT_SET1_SETP3_Msk (0x01UL << GPIO_PORT_SET1_SETP3_Pos) /*!< GPIO_PORT SET1: SETP3 Mask */ -#define GPIO_PORT_SET1_SETP4_Pos 4 /*!< GPIO_PORT SET1: SETP4 Position */ -#define GPIO_PORT_SET1_SETP4_Msk (0x01UL << GPIO_PORT_SET1_SETP4_Pos) /*!< GPIO_PORT SET1: SETP4 Mask */ -#define GPIO_PORT_SET1_SETP5_Pos 5 /*!< GPIO_PORT SET1: SETP5 Position */ -#define GPIO_PORT_SET1_SETP5_Msk (0x01UL << GPIO_PORT_SET1_SETP5_Pos) /*!< GPIO_PORT SET1: SETP5 Mask */ -#define GPIO_PORT_SET1_SETP6_Pos 6 /*!< GPIO_PORT SET1: SETP6 Position */ -#define GPIO_PORT_SET1_SETP6_Msk (0x01UL << GPIO_PORT_SET1_SETP6_Pos) /*!< GPIO_PORT SET1: SETP6 Mask */ -#define GPIO_PORT_SET1_SETP7_Pos 7 /*!< GPIO_PORT SET1: SETP7 Position */ -#define GPIO_PORT_SET1_SETP7_Msk (0x01UL << GPIO_PORT_SET1_SETP7_Pos) /*!< GPIO_PORT SET1: SETP7 Mask */ -#define GPIO_PORT_SET1_SETP8_Pos 8 /*!< GPIO_PORT SET1: SETP8 Position */ -#define GPIO_PORT_SET1_SETP8_Msk (0x01UL << GPIO_PORT_SET1_SETP8_Pos) /*!< GPIO_PORT SET1: SETP8 Mask */ -#define GPIO_PORT_SET1_SETP9_Pos 9 /*!< GPIO_PORT SET1: SETP9 Position */ -#define GPIO_PORT_SET1_SETP9_Msk (0x01UL << GPIO_PORT_SET1_SETP9_Pos) /*!< GPIO_PORT SET1: SETP9 Mask */ -#define GPIO_PORT_SET1_SETP10_Pos 10 /*!< GPIO_PORT SET1: SETP10 Position */ -#define GPIO_PORT_SET1_SETP10_Msk (0x01UL << GPIO_PORT_SET1_SETP10_Pos) /*!< GPIO_PORT SET1: SETP10 Mask */ -#define GPIO_PORT_SET1_SETP11_Pos 11 /*!< GPIO_PORT SET1: SETP11 Position */ -#define GPIO_PORT_SET1_SETP11_Msk (0x01UL << GPIO_PORT_SET1_SETP11_Pos) /*!< GPIO_PORT SET1: SETP11 Mask */ -#define GPIO_PORT_SET1_SETP12_Pos 12 /*!< GPIO_PORT SET1: SETP12 Position */ -#define GPIO_PORT_SET1_SETP12_Msk (0x01UL << GPIO_PORT_SET1_SETP12_Pos) /*!< GPIO_PORT SET1: SETP12 Mask */ -#define GPIO_PORT_SET1_SETP13_Pos 13 /*!< GPIO_PORT SET1: SETP13 Position */ -#define GPIO_PORT_SET1_SETP13_Msk (0x01UL << GPIO_PORT_SET1_SETP13_Pos) /*!< GPIO_PORT SET1: SETP13 Mask */ -#define GPIO_PORT_SET1_SETP14_Pos 14 /*!< GPIO_PORT SET1: SETP14 Position */ -#define GPIO_PORT_SET1_SETP14_Msk (0x01UL << GPIO_PORT_SET1_SETP14_Pos) /*!< GPIO_PORT SET1: SETP14 Mask */ -#define GPIO_PORT_SET1_SETP15_Pos 15 /*!< GPIO_PORT SET1: SETP15 Position */ -#define GPIO_PORT_SET1_SETP15_Msk (0x01UL << GPIO_PORT_SET1_SETP15_Pos) /*!< GPIO_PORT SET1: SETP15 Mask */ -#define GPIO_PORT_SET1_SETP16_Pos 16 /*!< GPIO_PORT SET1: SETP16 Position */ -#define GPIO_PORT_SET1_SETP16_Msk (0x01UL << GPIO_PORT_SET1_SETP16_Pos) /*!< GPIO_PORT SET1: SETP16 Mask */ -#define GPIO_PORT_SET1_SETP17_Pos 17 /*!< GPIO_PORT SET1: SETP17 Position */ -#define GPIO_PORT_SET1_SETP17_Msk (0x01UL << GPIO_PORT_SET1_SETP17_Pos) /*!< GPIO_PORT SET1: SETP17 Mask */ -#define GPIO_PORT_SET1_SETP18_Pos 18 /*!< GPIO_PORT SET1: SETP18 Position */ -#define GPIO_PORT_SET1_SETP18_Msk (0x01UL << GPIO_PORT_SET1_SETP18_Pos) /*!< GPIO_PORT SET1: SETP18 Mask */ -#define GPIO_PORT_SET1_SETP19_Pos 19 /*!< GPIO_PORT SET1: SETP19 Position */ -#define GPIO_PORT_SET1_SETP19_Msk (0x01UL << GPIO_PORT_SET1_SETP19_Pos) /*!< GPIO_PORT SET1: SETP19 Mask */ -#define GPIO_PORT_SET1_SETP20_Pos 20 /*!< GPIO_PORT SET1: SETP20 Position */ -#define GPIO_PORT_SET1_SETP20_Msk (0x01UL << GPIO_PORT_SET1_SETP20_Pos) /*!< GPIO_PORT SET1: SETP20 Mask */ -#define GPIO_PORT_SET1_SETP21_Pos 21 /*!< GPIO_PORT SET1: SETP21 Position */ -#define GPIO_PORT_SET1_SETP21_Msk (0x01UL << GPIO_PORT_SET1_SETP21_Pos) /*!< GPIO_PORT SET1: SETP21 Mask */ -#define GPIO_PORT_SET1_SETP22_Pos 22 /*!< GPIO_PORT SET1: SETP22 Position */ -#define GPIO_PORT_SET1_SETP22_Msk (0x01UL << GPIO_PORT_SET1_SETP22_Pos) /*!< GPIO_PORT SET1: SETP22 Mask */ -#define GPIO_PORT_SET1_SETP23_Pos 23 /*!< GPIO_PORT SET1: SETP23 Position */ -#define GPIO_PORT_SET1_SETP23_Msk (0x01UL << GPIO_PORT_SET1_SETP23_Pos) /*!< GPIO_PORT SET1: SETP23 Mask */ -#define GPIO_PORT_SET1_SETP24_Pos 24 /*!< GPIO_PORT SET1: SETP24 Position */ -#define GPIO_PORT_SET1_SETP24_Msk (0x01UL << GPIO_PORT_SET1_SETP24_Pos) /*!< GPIO_PORT SET1: SETP24 Mask */ -#define GPIO_PORT_SET1_SETP25_Pos 25 /*!< GPIO_PORT SET1: SETP25 Position */ -#define GPIO_PORT_SET1_SETP25_Msk (0x01UL << GPIO_PORT_SET1_SETP25_Pos) /*!< GPIO_PORT SET1: SETP25 Mask */ -#define GPIO_PORT_SET1_SETP26_Pos 26 /*!< GPIO_PORT SET1: SETP26 Position */ -#define GPIO_PORT_SET1_SETP26_Msk (0x01UL << GPIO_PORT_SET1_SETP26_Pos) /*!< GPIO_PORT SET1: SETP26 Mask */ -#define GPIO_PORT_SET1_SETP27_Pos 27 /*!< GPIO_PORT SET1: SETP27 Position */ -#define GPIO_PORT_SET1_SETP27_Msk (0x01UL << GPIO_PORT_SET1_SETP27_Pos) /*!< GPIO_PORT SET1: SETP27 Mask */ -#define GPIO_PORT_SET1_SETP28_Pos 28 /*!< GPIO_PORT SET1: SETP28 Position */ -#define GPIO_PORT_SET1_SETP28_Msk (0x01UL << GPIO_PORT_SET1_SETP28_Pos) /*!< GPIO_PORT SET1: SETP28 Mask */ -#define GPIO_PORT_SET1_SETP29_Pos 29 /*!< GPIO_PORT SET1: SETP29 Position */ -#define GPIO_PORT_SET1_SETP29_Msk (0x01UL << GPIO_PORT_SET1_SETP29_Pos) /*!< GPIO_PORT SET1: SETP29 Mask */ -#define GPIO_PORT_SET1_SETP30_Pos 30 /*!< GPIO_PORT SET1: SETP30 Position */ -#define GPIO_PORT_SET1_SETP30_Msk (0x01UL << GPIO_PORT_SET1_SETP30_Pos) /*!< GPIO_PORT SET1: SETP30 Mask */ -#define GPIO_PORT_SET1_SETP31_Pos 31 /*!< GPIO_PORT SET1: SETP31 Position */ -#define GPIO_PORT_SET1_SETP31_Msk (0x01UL << GPIO_PORT_SET1_SETP31_Pos) /*!< GPIO_PORT SET1: SETP31 Mask */ - -// ------------------------------------- GPIO_PORT_SET2 ----------------------------------------- -#define GPIO_PORT_SET2_SETP0_Pos 0 /*!< GPIO_PORT SET2: SETP0 Position */ -#define GPIO_PORT_SET2_SETP0_Msk (0x01UL << GPIO_PORT_SET2_SETP0_Pos) /*!< GPIO_PORT SET2: SETP0 Mask */ -#define GPIO_PORT_SET2_SETP1_Pos 1 /*!< GPIO_PORT SET2: SETP1 Position */ -#define GPIO_PORT_SET2_SETP1_Msk (0x01UL << GPIO_PORT_SET2_SETP1_Pos) /*!< GPIO_PORT SET2: SETP1 Mask */ -#define GPIO_PORT_SET2_SETP2_Pos 2 /*!< GPIO_PORT SET2: SETP2 Position */ -#define GPIO_PORT_SET2_SETP2_Msk (0x01UL << GPIO_PORT_SET2_SETP2_Pos) /*!< GPIO_PORT SET2: SETP2 Mask */ -#define GPIO_PORT_SET2_SETP3_Pos 3 /*!< GPIO_PORT SET2: SETP3 Position */ -#define GPIO_PORT_SET2_SETP3_Msk (0x01UL << GPIO_PORT_SET2_SETP3_Pos) /*!< GPIO_PORT SET2: SETP3 Mask */ -#define GPIO_PORT_SET2_SETP4_Pos 4 /*!< GPIO_PORT SET2: SETP4 Position */ -#define GPIO_PORT_SET2_SETP4_Msk (0x01UL << GPIO_PORT_SET2_SETP4_Pos) /*!< GPIO_PORT SET2: SETP4 Mask */ -#define GPIO_PORT_SET2_SETP5_Pos 5 /*!< GPIO_PORT SET2: SETP5 Position */ -#define GPIO_PORT_SET2_SETP5_Msk (0x01UL << GPIO_PORT_SET2_SETP5_Pos) /*!< GPIO_PORT SET2: SETP5 Mask */ -#define GPIO_PORT_SET2_SETP6_Pos 6 /*!< GPIO_PORT SET2: SETP6 Position */ -#define GPIO_PORT_SET2_SETP6_Msk (0x01UL << GPIO_PORT_SET2_SETP6_Pos) /*!< GPIO_PORT SET2: SETP6 Mask */ -#define GPIO_PORT_SET2_SETP7_Pos 7 /*!< GPIO_PORT SET2: SETP7 Position */ -#define GPIO_PORT_SET2_SETP7_Msk (0x01UL << GPIO_PORT_SET2_SETP7_Pos) /*!< GPIO_PORT SET2: SETP7 Mask */ -#define GPIO_PORT_SET2_SETP8_Pos 8 /*!< GPIO_PORT SET2: SETP8 Position */ -#define GPIO_PORT_SET2_SETP8_Msk (0x01UL << GPIO_PORT_SET2_SETP8_Pos) /*!< GPIO_PORT SET2: SETP8 Mask */ -#define GPIO_PORT_SET2_SETP9_Pos 9 /*!< GPIO_PORT SET2: SETP9 Position */ -#define GPIO_PORT_SET2_SETP9_Msk (0x01UL << GPIO_PORT_SET2_SETP9_Pos) /*!< GPIO_PORT SET2: SETP9 Mask */ -#define GPIO_PORT_SET2_SETP10_Pos 10 /*!< GPIO_PORT SET2: SETP10 Position */ -#define GPIO_PORT_SET2_SETP10_Msk (0x01UL << GPIO_PORT_SET2_SETP10_Pos) /*!< GPIO_PORT SET2: SETP10 Mask */ -#define GPIO_PORT_SET2_SETP11_Pos 11 /*!< GPIO_PORT SET2: SETP11 Position */ -#define GPIO_PORT_SET2_SETP11_Msk (0x01UL << GPIO_PORT_SET2_SETP11_Pos) /*!< GPIO_PORT SET2: SETP11 Mask */ -#define GPIO_PORT_SET2_SETP12_Pos 12 /*!< GPIO_PORT SET2: SETP12 Position */ -#define GPIO_PORT_SET2_SETP12_Msk (0x01UL << GPIO_PORT_SET2_SETP12_Pos) /*!< GPIO_PORT SET2: SETP12 Mask */ -#define GPIO_PORT_SET2_SETP13_Pos 13 /*!< GPIO_PORT SET2: SETP13 Position */ -#define GPIO_PORT_SET2_SETP13_Msk (0x01UL << GPIO_PORT_SET2_SETP13_Pos) /*!< GPIO_PORT SET2: SETP13 Mask */ -#define GPIO_PORT_SET2_SETP14_Pos 14 /*!< GPIO_PORT SET2: SETP14 Position */ -#define GPIO_PORT_SET2_SETP14_Msk (0x01UL << GPIO_PORT_SET2_SETP14_Pos) /*!< GPIO_PORT SET2: SETP14 Mask */ -#define GPIO_PORT_SET2_SETP15_Pos 15 /*!< GPIO_PORT SET2: SETP15 Position */ -#define GPIO_PORT_SET2_SETP15_Msk (0x01UL << GPIO_PORT_SET2_SETP15_Pos) /*!< GPIO_PORT SET2: SETP15 Mask */ -#define GPIO_PORT_SET2_SETP16_Pos 16 /*!< GPIO_PORT SET2: SETP16 Position */ -#define GPIO_PORT_SET2_SETP16_Msk (0x01UL << GPIO_PORT_SET2_SETP16_Pos) /*!< GPIO_PORT SET2: SETP16 Mask */ -#define GPIO_PORT_SET2_SETP17_Pos 17 /*!< GPIO_PORT SET2: SETP17 Position */ -#define GPIO_PORT_SET2_SETP17_Msk (0x01UL << GPIO_PORT_SET2_SETP17_Pos) /*!< GPIO_PORT SET2: SETP17 Mask */ -#define GPIO_PORT_SET2_SETP18_Pos 18 /*!< GPIO_PORT SET2: SETP18 Position */ -#define GPIO_PORT_SET2_SETP18_Msk (0x01UL << GPIO_PORT_SET2_SETP18_Pos) /*!< GPIO_PORT SET2: SETP18 Mask */ -#define GPIO_PORT_SET2_SETP19_Pos 19 /*!< GPIO_PORT SET2: SETP19 Position */ -#define GPIO_PORT_SET2_SETP19_Msk (0x01UL << GPIO_PORT_SET2_SETP19_Pos) /*!< GPIO_PORT SET2: SETP19 Mask */ -#define GPIO_PORT_SET2_SETP20_Pos 20 /*!< GPIO_PORT SET2: SETP20 Position */ -#define GPIO_PORT_SET2_SETP20_Msk (0x01UL << GPIO_PORT_SET2_SETP20_Pos) /*!< GPIO_PORT SET2: SETP20 Mask */ -#define GPIO_PORT_SET2_SETP21_Pos 21 /*!< GPIO_PORT SET2: SETP21 Position */ -#define GPIO_PORT_SET2_SETP21_Msk (0x01UL << GPIO_PORT_SET2_SETP21_Pos) /*!< GPIO_PORT SET2: SETP21 Mask */ -#define GPIO_PORT_SET2_SETP22_Pos 22 /*!< GPIO_PORT SET2: SETP22 Position */ -#define GPIO_PORT_SET2_SETP22_Msk (0x01UL << GPIO_PORT_SET2_SETP22_Pos) /*!< GPIO_PORT SET2: SETP22 Mask */ -#define GPIO_PORT_SET2_SETP23_Pos 23 /*!< GPIO_PORT SET2: SETP23 Position */ -#define GPIO_PORT_SET2_SETP23_Msk (0x01UL << GPIO_PORT_SET2_SETP23_Pos) /*!< GPIO_PORT SET2: SETP23 Mask */ -#define GPIO_PORT_SET2_SETP24_Pos 24 /*!< GPIO_PORT SET2: SETP24 Position */ -#define GPIO_PORT_SET2_SETP24_Msk (0x01UL << GPIO_PORT_SET2_SETP24_Pos) /*!< GPIO_PORT SET2: SETP24 Mask */ -#define GPIO_PORT_SET2_SETP25_Pos 25 /*!< GPIO_PORT SET2: SETP25 Position */ -#define GPIO_PORT_SET2_SETP25_Msk (0x01UL << GPIO_PORT_SET2_SETP25_Pos) /*!< GPIO_PORT SET2: SETP25 Mask */ -#define GPIO_PORT_SET2_SETP26_Pos 26 /*!< GPIO_PORT SET2: SETP26 Position */ -#define GPIO_PORT_SET2_SETP26_Msk (0x01UL << GPIO_PORT_SET2_SETP26_Pos) /*!< GPIO_PORT SET2: SETP26 Mask */ -#define GPIO_PORT_SET2_SETP27_Pos 27 /*!< GPIO_PORT SET2: SETP27 Position */ -#define GPIO_PORT_SET2_SETP27_Msk (0x01UL << GPIO_PORT_SET2_SETP27_Pos) /*!< GPIO_PORT SET2: SETP27 Mask */ -#define GPIO_PORT_SET2_SETP28_Pos 28 /*!< GPIO_PORT SET2: SETP28 Position */ -#define GPIO_PORT_SET2_SETP28_Msk (0x01UL << GPIO_PORT_SET2_SETP28_Pos) /*!< GPIO_PORT SET2: SETP28 Mask */ -#define GPIO_PORT_SET2_SETP29_Pos 29 /*!< GPIO_PORT SET2: SETP29 Position */ -#define GPIO_PORT_SET2_SETP29_Msk (0x01UL << GPIO_PORT_SET2_SETP29_Pos) /*!< GPIO_PORT SET2: SETP29 Mask */ -#define GPIO_PORT_SET2_SETP30_Pos 30 /*!< GPIO_PORT SET2: SETP30 Position */ -#define GPIO_PORT_SET2_SETP30_Msk (0x01UL << GPIO_PORT_SET2_SETP30_Pos) /*!< GPIO_PORT SET2: SETP30 Mask */ -#define GPIO_PORT_SET2_SETP31_Pos 31 /*!< GPIO_PORT SET2: SETP31 Position */ -#define GPIO_PORT_SET2_SETP31_Msk (0x01UL << GPIO_PORT_SET2_SETP31_Pos) /*!< GPIO_PORT SET2: SETP31 Mask */ - -// ------------------------------------- GPIO_PORT_SET3 ----------------------------------------- -#define GPIO_PORT_SET3_SETP0_Pos 0 /*!< GPIO_PORT SET3: SETP0 Position */ -#define GPIO_PORT_SET3_SETP0_Msk (0x01UL << GPIO_PORT_SET3_SETP0_Pos) /*!< GPIO_PORT SET3: SETP0 Mask */ -#define GPIO_PORT_SET3_SETP1_Pos 1 /*!< GPIO_PORT SET3: SETP1 Position */ -#define GPIO_PORT_SET3_SETP1_Msk (0x01UL << GPIO_PORT_SET3_SETP1_Pos) /*!< GPIO_PORT SET3: SETP1 Mask */ -#define GPIO_PORT_SET3_SETP2_Pos 2 /*!< GPIO_PORT SET3: SETP2 Position */ -#define GPIO_PORT_SET3_SETP2_Msk (0x01UL << GPIO_PORT_SET3_SETP2_Pos) /*!< GPIO_PORT SET3: SETP2 Mask */ -#define GPIO_PORT_SET3_SETP3_Pos 3 /*!< GPIO_PORT SET3: SETP3 Position */ -#define GPIO_PORT_SET3_SETP3_Msk (0x01UL << GPIO_PORT_SET3_SETP3_Pos) /*!< GPIO_PORT SET3: SETP3 Mask */ -#define GPIO_PORT_SET3_SETP4_Pos 4 /*!< GPIO_PORT SET3: SETP4 Position */ -#define GPIO_PORT_SET3_SETP4_Msk (0x01UL << GPIO_PORT_SET3_SETP4_Pos) /*!< GPIO_PORT SET3: SETP4 Mask */ -#define GPIO_PORT_SET3_SETP5_Pos 5 /*!< GPIO_PORT SET3: SETP5 Position */ -#define GPIO_PORT_SET3_SETP5_Msk (0x01UL << GPIO_PORT_SET3_SETP5_Pos) /*!< GPIO_PORT SET3: SETP5 Mask */ -#define GPIO_PORT_SET3_SETP6_Pos 6 /*!< GPIO_PORT SET3: SETP6 Position */ -#define GPIO_PORT_SET3_SETP6_Msk (0x01UL << GPIO_PORT_SET3_SETP6_Pos) /*!< GPIO_PORT SET3: SETP6 Mask */ -#define GPIO_PORT_SET3_SETP7_Pos 7 /*!< GPIO_PORT SET3: SETP7 Position */ -#define GPIO_PORT_SET3_SETP7_Msk (0x01UL << GPIO_PORT_SET3_SETP7_Pos) /*!< GPIO_PORT SET3: SETP7 Mask */ -#define GPIO_PORT_SET3_SETP8_Pos 8 /*!< GPIO_PORT SET3: SETP8 Position */ -#define GPIO_PORT_SET3_SETP8_Msk (0x01UL << GPIO_PORT_SET3_SETP8_Pos) /*!< GPIO_PORT SET3: SETP8 Mask */ -#define GPIO_PORT_SET3_SETP9_Pos 9 /*!< GPIO_PORT SET3: SETP9 Position */ -#define GPIO_PORT_SET3_SETP9_Msk (0x01UL << GPIO_PORT_SET3_SETP9_Pos) /*!< GPIO_PORT SET3: SETP9 Mask */ -#define GPIO_PORT_SET3_SETP10_Pos 10 /*!< GPIO_PORT SET3: SETP10 Position */ -#define GPIO_PORT_SET3_SETP10_Msk (0x01UL << GPIO_PORT_SET3_SETP10_Pos) /*!< GPIO_PORT SET3: SETP10 Mask */ -#define GPIO_PORT_SET3_SETP11_Pos 11 /*!< GPIO_PORT SET3: SETP11 Position */ -#define GPIO_PORT_SET3_SETP11_Msk (0x01UL << GPIO_PORT_SET3_SETP11_Pos) /*!< GPIO_PORT SET3: SETP11 Mask */ -#define GPIO_PORT_SET3_SETP12_Pos 12 /*!< GPIO_PORT SET3: SETP12 Position */ -#define GPIO_PORT_SET3_SETP12_Msk (0x01UL << GPIO_PORT_SET3_SETP12_Pos) /*!< GPIO_PORT SET3: SETP12 Mask */ -#define GPIO_PORT_SET3_SETP13_Pos 13 /*!< GPIO_PORT SET3: SETP13 Position */ -#define GPIO_PORT_SET3_SETP13_Msk (0x01UL << GPIO_PORT_SET3_SETP13_Pos) /*!< GPIO_PORT SET3: SETP13 Mask */ -#define GPIO_PORT_SET3_SETP14_Pos 14 /*!< GPIO_PORT SET3: SETP14 Position */ -#define GPIO_PORT_SET3_SETP14_Msk (0x01UL << GPIO_PORT_SET3_SETP14_Pos) /*!< GPIO_PORT SET3: SETP14 Mask */ -#define GPIO_PORT_SET3_SETP15_Pos 15 /*!< GPIO_PORT SET3: SETP15 Position */ -#define GPIO_PORT_SET3_SETP15_Msk (0x01UL << GPIO_PORT_SET3_SETP15_Pos) /*!< GPIO_PORT SET3: SETP15 Mask */ -#define GPIO_PORT_SET3_SETP16_Pos 16 /*!< GPIO_PORT SET3: SETP16 Position */ -#define GPIO_PORT_SET3_SETP16_Msk (0x01UL << GPIO_PORT_SET3_SETP16_Pos) /*!< GPIO_PORT SET3: SETP16 Mask */ -#define GPIO_PORT_SET3_SETP17_Pos 17 /*!< GPIO_PORT SET3: SETP17 Position */ -#define GPIO_PORT_SET3_SETP17_Msk (0x01UL << GPIO_PORT_SET3_SETP17_Pos) /*!< GPIO_PORT SET3: SETP17 Mask */ -#define GPIO_PORT_SET3_SETP18_Pos 18 /*!< GPIO_PORT SET3: SETP18 Position */ -#define GPIO_PORT_SET3_SETP18_Msk (0x01UL << GPIO_PORT_SET3_SETP18_Pos) /*!< GPIO_PORT SET3: SETP18 Mask */ -#define GPIO_PORT_SET3_SETP19_Pos 19 /*!< GPIO_PORT SET3: SETP19 Position */ -#define GPIO_PORT_SET3_SETP19_Msk (0x01UL << GPIO_PORT_SET3_SETP19_Pos) /*!< GPIO_PORT SET3: SETP19 Mask */ -#define GPIO_PORT_SET3_SETP20_Pos 20 /*!< GPIO_PORT SET3: SETP20 Position */ -#define GPIO_PORT_SET3_SETP20_Msk (0x01UL << GPIO_PORT_SET3_SETP20_Pos) /*!< GPIO_PORT SET3: SETP20 Mask */ -#define GPIO_PORT_SET3_SETP21_Pos 21 /*!< GPIO_PORT SET3: SETP21 Position */ -#define GPIO_PORT_SET3_SETP21_Msk (0x01UL << GPIO_PORT_SET3_SETP21_Pos) /*!< GPIO_PORT SET3: SETP21 Mask */ -#define GPIO_PORT_SET3_SETP22_Pos 22 /*!< GPIO_PORT SET3: SETP22 Position */ -#define GPIO_PORT_SET3_SETP22_Msk (0x01UL << GPIO_PORT_SET3_SETP22_Pos) /*!< GPIO_PORT SET3: SETP22 Mask */ -#define GPIO_PORT_SET3_SETP23_Pos 23 /*!< GPIO_PORT SET3: SETP23 Position */ -#define GPIO_PORT_SET3_SETP23_Msk (0x01UL << GPIO_PORT_SET3_SETP23_Pos) /*!< GPIO_PORT SET3: SETP23 Mask */ -#define GPIO_PORT_SET3_SETP24_Pos 24 /*!< GPIO_PORT SET3: SETP24 Position */ -#define GPIO_PORT_SET3_SETP24_Msk (0x01UL << GPIO_PORT_SET3_SETP24_Pos) /*!< GPIO_PORT SET3: SETP24 Mask */ -#define GPIO_PORT_SET3_SETP25_Pos 25 /*!< GPIO_PORT SET3: SETP25 Position */ -#define GPIO_PORT_SET3_SETP25_Msk (0x01UL << GPIO_PORT_SET3_SETP25_Pos) /*!< GPIO_PORT SET3: SETP25 Mask */ -#define GPIO_PORT_SET3_SETP26_Pos 26 /*!< GPIO_PORT SET3: SETP26 Position */ -#define GPIO_PORT_SET3_SETP26_Msk (0x01UL << GPIO_PORT_SET3_SETP26_Pos) /*!< GPIO_PORT SET3: SETP26 Mask */ -#define GPIO_PORT_SET3_SETP27_Pos 27 /*!< GPIO_PORT SET3: SETP27 Position */ -#define GPIO_PORT_SET3_SETP27_Msk (0x01UL << GPIO_PORT_SET3_SETP27_Pos) /*!< GPIO_PORT SET3: SETP27 Mask */ -#define GPIO_PORT_SET3_SETP28_Pos 28 /*!< GPIO_PORT SET3: SETP28 Position */ -#define GPIO_PORT_SET3_SETP28_Msk (0x01UL << GPIO_PORT_SET3_SETP28_Pos) /*!< GPIO_PORT SET3: SETP28 Mask */ -#define GPIO_PORT_SET3_SETP29_Pos 29 /*!< GPIO_PORT SET3: SETP29 Position */ -#define GPIO_PORT_SET3_SETP29_Msk (0x01UL << GPIO_PORT_SET3_SETP29_Pos) /*!< GPIO_PORT SET3: SETP29 Mask */ -#define GPIO_PORT_SET3_SETP30_Pos 30 /*!< GPIO_PORT SET3: SETP30 Position */ -#define GPIO_PORT_SET3_SETP30_Msk (0x01UL << GPIO_PORT_SET3_SETP30_Pos) /*!< GPIO_PORT SET3: SETP30 Mask */ -#define GPIO_PORT_SET3_SETP31_Pos 31 /*!< GPIO_PORT SET3: SETP31 Position */ -#define GPIO_PORT_SET3_SETP31_Msk (0x01UL << GPIO_PORT_SET3_SETP31_Pos) /*!< GPIO_PORT SET3: SETP31 Mask */ - -// ------------------------------------- GPIO_PORT_SET4 ----------------------------------------- -#define GPIO_PORT_SET4_SETP0_Pos 0 /*!< GPIO_PORT SET4: SETP0 Position */ -#define GPIO_PORT_SET4_SETP0_Msk (0x01UL << GPIO_PORT_SET4_SETP0_Pos) /*!< GPIO_PORT SET4: SETP0 Mask */ -#define GPIO_PORT_SET4_SETP1_Pos 1 /*!< GPIO_PORT SET4: SETP1 Position */ -#define GPIO_PORT_SET4_SETP1_Msk (0x01UL << GPIO_PORT_SET4_SETP1_Pos) /*!< GPIO_PORT SET4: SETP1 Mask */ -#define GPIO_PORT_SET4_SETP2_Pos 2 /*!< GPIO_PORT SET4: SETP2 Position */ -#define GPIO_PORT_SET4_SETP2_Msk (0x01UL << GPIO_PORT_SET4_SETP2_Pos) /*!< GPIO_PORT SET4: SETP2 Mask */ -#define GPIO_PORT_SET4_SETP3_Pos 3 /*!< GPIO_PORT SET4: SETP3 Position */ -#define GPIO_PORT_SET4_SETP3_Msk (0x01UL << GPIO_PORT_SET4_SETP3_Pos) /*!< GPIO_PORT SET4: SETP3 Mask */ -#define GPIO_PORT_SET4_SETP4_Pos 4 /*!< GPIO_PORT SET4: SETP4 Position */ -#define GPIO_PORT_SET4_SETP4_Msk (0x01UL << GPIO_PORT_SET4_SETP4_Pos) /*!< GPIO_PORT SET4: SETP4 Mask */ -#define GPIO_PORT_SET4_SETP5_Pos 5 /*!< GPIO_PORT SET4: SETP5 Position */ -#define GPIO_PORT_SET4_SETP5_Msk (0x01UL << GPIO_PORT_SET4_SETP5_Pos) /*!< GPIO_PORT SET4: SETP5 Mask */ -#define GPIO_PORT_SET4_SETP6_Pos 6 /*!< GPIO_PORT SET4: SETP6 Position */ -#define GPIO_PORT_SET4_SETP6_Msk (0x01UL << GPIO_PORT_SET4_SETP6_Pos) /*!< GPIO_PORT SET4: SETP6 Mask */ -#define GPIO_PORT_SET4_SETP7_Pos 7 /*!< GPIO_PORT SET4: SETP7 Position */ -#define GPIO_PORT_SET4_SETP7_Msk (0x01UL << GPIO_PORT_SET4_SETP7_Pos) /*!< GPIO_PORT SET4: SETP7 Mask */ -#define GPIO_PORT_SET4_SETP8_Pos 8 /*!< GPIO_PORT SET4: SETP8 Position */ -#define GPIO_PORT_SET4_SETP8_Msk (0x01UL << GPIO_PORT_SET4_SETP8_Pos) /*!< GPIO_PORT SET4: SETP8 Mask */ -#define GPIO_PORT_SET4_SETP9_Pos 9 /*!< GPIO_PORT SET4: SETP9 Position */ -#define GPIO_PORT_SET4_SETP9_Msk (0x01UL << GPIO_PORT_SET4_SETP9_Pos) /*!< GPIO_PORT SET4: SETP9 Mask */ -#define GPIO_PORT_SET4_SETP10_Pos 10 /*!< GPIO_PORT SET4: SETP10 Position */ -#define GPIO_PORT_SET4_SETP10_Msk (0x01UL << GPIO_PORT_SET4_SETP10_Pos) /*!< GPIO_PORT SET4: SETP10 Mask */ -#define GPIO_PORT_SET4_SETP11_Pos 11 /*!< GPIO_PORT SET4: SETP11 Position */ -#define GPIO_PORT_SET4_SETP11_Msk (0x01UL << GPIO_PORT_SET4_SETP11_Pos) /*!< GPIO_PORT SET4: SETP11 Mask */ -#define GPIO_PORT_SET4_SETP12_Pos 12 /*!< GPIO_PORT SET4: SETP12 Position */ -#define GPIO_PORT_SET4_SETP12_Msk (0x01UL << GPIO_PORT_SET4_SETP12_Pos) /*!< GPIO_PORT SET4: SETP12 Mask */ -#define GPIO_PORT_SET4_SETP13_Pos 13 /*!< GPIO_PORT SET4: SETP13 Position */ -#define GPIO_PORT_SET4_SETP13_Msk (0x01UL << GPIO_PORT_SET4_SETP13_Pos) /*!< GPIO_PORT SET4: SETP13 Mask */ -#define GPIO_PORT_SET4_SETP14_Pos 14 /*!< GPIO_PORT SET4: SETP14 Position */ -#define GPIO_PORT_SET4_SETP14_Msk (0x01UL << GPIO_PORT_SET4_SETP14_Pos) /*!< GPIO_PORT SET4: SETP14 Mask */ -#define GPIO_PORT_SET4_SETP15_Pos 15 /*!< GPIO_PORT SET4: SETP15 Position */ -#define GPIO_PORT_SET4_SETP15_Msk (0x01UL << GPIO_PORT_SET4_SETP15_Pos) /*!< GPIO_PORT SET4: SETP15 Mask */ -#define GPIO_PORT_SET4_SETP16_Pos 16 /*!< GPIO_PORT SET4: SETP16 Position */ -#define GPIO_PORT_SET4_SETP16_Msk (0x01UL << GPIO_PORT_SET4_SETP16_Pos) /*!< GPIO_PORT SET4: SETP16 Mask */ -#define GPIO_PORT_SET4_SETP17_Pos 17 /*!< GPIO_PORT SET4: SETP17 Position */ -#define GPIO_PORT_SET4_SETP17_Msk (0x01UL << GPIO_PORT_SET4_SETP17_Pos) /*!< GPIO_PORT SET4: SETP17 Mask */ -#define GPIO_PORT_SET4_SETP18_Pos 18 /*!< GPIO_PORT SET4: SETP18 Position */ -#define GPIO_PORT_SET4_SETP18_Msk (0x01UL << GPIO_PORT_SET4_SETP18_Pos) /*!< GPIO_PORT SET4: SETP18 Mask */ -#define GPIO_PORT_SET4_SETP19_Pos 19 /*!< GPIO_PORT SET4: SETP19 Position */ -#define GPIO_PORT_SET4_SETP19_Msk (0x01UL << GPIO_PORT_SET4_SETP19_Pos) /*!< GPIO_PORT SET4: SETP19 Mask */ -#define GPIO_PORT_SET4_SETP20_Pos 20 /*!< GPIO_PORT SET4: SETP20 Position */ -#define GPIO_PORT_SET4_SETP20_Msk (0x01UL << GPIO_PORT_SET4_SETP20_Pos) /*!< GPIO_PORT SET4: SETP20 Mask */ -#define GPIO_PORT_SET4_SETP21_Pos 21 /*!< GPIO_PORT SET4: SETP21 Position */ -#define GPIO_PORT_SET4_SETP21_Msk (0x01UL << GPIO_PORT_SET4_SETP21_Pos) /*!< GPIO_PORT SET4: SETP21 Mask */ -#define GPIO_PORT_SET4_SETP22_Pos 22 /*!< GPIO_PORT SET4: SETP22 Position */ -#define GPIO_PORT_SET4_SETP22_Msk (0x01UL << GPIO_PORT_SET4_SETP22_Pos) /*!< GPIO_PORT SET4: SETP22 Mask */ -#define GPIO_PORT_SET4_SETP23_Pos 23 /*!< GPIO_PORT SET4: SETP23 Position */ -#define GPIO_PORT_SET4_SETP23_Msk (0x01UL << GPIO_PORT_SET4_SETP23_Pos) /*!< GPIO_PORT SET4: SETP23 Mask */ -#define GPIO_PORT_SET4_SETP24_Pos 24 /*!< GPIO_PORT SET4: SETP24 Position */ -#define GPIO_PORT_SET4_SETP24_Msk (0x01UL << GPIO_PORT_SET4_SETP24_Pos) /*!< GPIO_PORT SET4: SETP24 Mask */ -#define GPIO_PORT_SET4_SETP25_Pos 25 /*!< GPIO_PORT SET4: SETP25 Position */ -#define GPIO_PORT_SET4_SETP25_Msk (0x01UL << GPIO_PORT_SET4_SETP25_Pos) /*!< GPIO_PORT SET4: SETP25 Mask */ -#define GPIO_PORT_SET4_SETP26_Pos 26 /*!< GPIO_PORT SET4: SETP26 Position */ -#define GPIO_PORT_SET4_SETP26_Msk (0x01UL << GPIO_PORT_SET4_SETP26_Pos) /*!< GPIO_PORT SET4: SETP26 Mask */ -#define GPIO_PORT_SET4_SETP27_Pos 27 /*!< GPIO_PORT SET4: SETP27 Position */ -#define GPIO_PORT_SET4_SETP27_Msk (0x01UL << GPIO_PORT_SET4_SETP27_Pos) /*!< GPIO_PORT SET4: SETP27 Mask */ -#define GPIO_PORT_SET4_SETP28_Pos 28 /*!< GPIO_PORT SET4: SETP28 Position */ -#define GPIO_PORT_SET4_SETP28_Msk (0x01UL << GPIO_PORT_SET4_SETP28_Pos) /*!< GPIO_PORT SET4: SETP28 Mask */ -#define GPIO_PORT_SET4_SETP29_Pos 29 /*!< GPIO_PORT SET4: SETP29 Position */ -#define GPIO_PORT_SET4_SETP29_Msk (0x01UL << GPIO_PORT_SET4_SETP29_Pos) /*!< GPIO_PORT SET4: SETP29 Mask */ -#define GPIO_PORT_SET4_SETP30_Pos 30 /*!< GPIO_PORT SET4: SETP30 Position */ -#define GPIO_PORT_SET4_SETP30_Msk (0x01UL << GPIO_PORT_SET4_SETP30_Pos) /*!< GPIO_PORT SET4: SETP30 Mask */ -#define GPIO_PORT_SET4_SETP31_Pos 31 /*!< GPIO_PORT SET4: SETP31 Position */ -#define GPIO_PORT_SET4_SETP31_Msk (0x01UL << GPIO_PORT_SET4_SETP31_Pos) /*!< GPIO_PORT SET4: SETP31 Mask */ - -// ------------------------------------- GPIO_PORT_SET5 ----------------------------------------- -#define GPIO_PORT_SET5_SETP0_Pos 0 /*!< GPIO_PORT SET5: SETP0 Position */ -#define GPIO_PORT_SET5_SETP0_Msk (0x01UL << GPIO_PORT_SET5_SETP0_Pos) /*!< GPIO_PORT SET5: SETP0 Mask */ -#define GPIO_PORT_SET5_SETP1_Pos 1 /*!< GPIO_PORT SET5: SETP1 Position */ -#define GPIO_PORT_SET5_SETP1_Msk (0x01UL << GPIO_PORT_SET5_SETP1_Pos) /*!< GPIO_PORT SET5: SETP1 Mask */ -#define GPIO_PORT_SET5_SETP2_Pos 2 /*!< GPIO_PORT SET5: SETP2 Position */ -#define GPIO_PORT_SET5_SETP2_Msk (0x01UL << GPIO_PORT_SET5_SETP2_Pos) /*!< GPIO_PORT SET5: SETP2 Mask */ -#define GPIO_PORT_SET5_SETP3_Pos 3 /*!< GPIO_PORT SET5: SETP3 Position */ -#define GPIO_PORT_SET5_SETP3_Msk (0x01UL << GPIO_PORT_SET5_SETP3_Pos) /*!< GPIO_PORT SET5: SETP3 Mask */ -#define GPIO_PORT_SET5_SETP4_Pos 4 /*!< GPIO_PORT SET5: SETP4 Position */ -#define GPIO_PORT_SET5_SETP4_Msk (0x01UL << GPIO_PORT_SET5_SETP4_Pos) /*!< GPIO_PORT SET5: SETP4 Mask */ -#define GPIO_PORT_SET5_SETP5_Pos 5 /*!< GPIO_PORT SET5: SETP5 Position */ -#define GPIO_PORT_SET5_SETP5_Msk (0x01UL << GPIO_PORT_SET5_SETP5_Pos) /*!< GPIO_PORT SET5: SETP5 Mask */ -#define GPIO_PORT_SET5_SETP6_Pos 6 /*!< GPIO_PORT SET5: SETP6 Position */ -#define GPIO_PORT_SET5_SETP6_Msk (0x01UL << GPIO_PORT_SET5_SETP6_Pos) /*!< GPIO_PORT SET5: SETP6 Mask */ -#define GPIO_PORT_SET5_SETP7_Pos 7 /*!< GPIO_PORT SET5: SETP7 Position */ -#define GPIO_PORT_SET5_SETP7_Msk (0x01UL << GPIO_PORT_SET5_SETP7_Pos) /*!< GPIO_PORT SET5: SETP7 Mask */ -#define GPIO_PORT_SET5_SETP8_Pos 8 /*!< GPIO_PORT SET5: SETP8 Position */ -#define GPIO_PORT_SET5_SETP8_Msk (0x01UL << GPIO_PORT_SET5_SETP8_Pos) /*!< GPIO_PORT SET5: SETP8 Mask */ -#define GPIO_PORT_SET5_SETP9_Pos 9 /*!< GPIO_PORT SET5: SETP9 Position */ -#define GPIO_PORT_SET5_SETP9_Msk (0x01UL << GPIO_PORT_SET5_SETP9_Pos) /*!< GPIO_PORT SET5: SETP9 Mask */ -#define GPIO_PORT_SET5_SETP10_Pos 10 /*!< GPIO_PORT SET5: SETP10 Position */ -#define GPIO_PORT_SET5_SETP10_Msk (0x01UL << GPIO_PORT_SET5_SETP10_Pos) /*!< GPIO_PORT SET5: SETP10 Mask */ -#define GPIO_PORT_SET5_SETP11_Pos 11 /*!< GPIO_PORT SET5: SETP11 Position */ -#define GPIO_PORT_SET5_SETP11_Msk (0x01UL << GPIO_PORT_SET5_SETP11_Pos) /*!< GPIO_PORT SET5: SETP11 Mask */ -#define GPIO_PORT_SET5_SETP12_Pos 12 /*!< GPIO_PORT SET5: SETP12 Position */ -#define GPIO_PORT_SET5_SETP12_Msk (0x01UL << GPIO_PORT_SET5_SETP12_Pos) /*!< GPIO_PORT SET5: SETP12 Mask */ -#define GPIO_PORT_SET5_SETP13_Pos 13 /*!< GPIO_PORT SET5: SETP13 Position */ -#define GPIO_PORT_SET5_SETP13_Msk (0x01UL << GPIO_PORT_SET5_SETP13_Pos) /*!< GPIO_PORT SET5: SETP13 Mask */ -#define GPIO_PORT_SET5_SETP14_Pos 14 /*!< GPIO_PORT SET5: SETP14 Position */ -#define GPIO_PORT_SET5_SETP14_Msk (0x01UL << GPIO_PORT_SET5_SETP14_Pos) /*!< GPIO_PORT SET5: SETP14 Mask */ -#define GPIO_PORT_SET5_SETP15_Pos 15 /*!< GPIO_PORT SET5: SETP15 Position */ -#define GPIO_PORT_SET5_SETP15_Msk (0x01UL << GPIO_PORT_SET5_SETP15_Pos) /*!< GPIO_PORT SET5: SETP15 Mask */ -#define GPIO_PORT_SET5_SETP16_Pos 16 /*!< GPIO_PORT SET5: SETP16 Position */ -#define GPIO_PORT_SET5_SETP16_Msk (0x01UL << GPIO_PORT_SET5_SETP16_Pos) /*!< GPIO_PORT SET5: SETP16 Mask */ -#define GPIO_PORT_SET5_SETP17_Pos 17 /*!< GPIO_PORT SET5: SETP17 Position */ -#define GPIO_PORT_SET5_SETP17_Msk (0x01UL << GPIO_PORT_SET5_SETP17_Pos) /*!< GPIO_PORT SET5: SETP17 Mask */ -#define GPIO_PORT_SET5_SETP18_Pos 18 /*!< GPIO_PORT SET5: SETP18 Position */ -#define GPIO_PORT_SET5_SETP18_Msk (0x01UL << GPIO_PORT_SET5_SETP18_Pos) /*!< GPIO_PORT SET5: SETP18 Mask */ -#define GPIO_PORT_SET5_SETP19_Pos 19 /*!< GPIO_PORT SET5: SETP19 Position */ -#define GPIO_PORT_SET5_SETP19_Msk (0x01UL << GPIO_PORT_SET5_SETP19_Pos) /*!< GPIO_PORT SET5: SETP19 Mask */ -#define GPIO_PORT_SET5_SETP20_Pos 20 /*!< GPIO_PORT SET5: SETP20 Position */ -#define GPIO_PORT_SET5_SETP20_Msk (0x01UL << GPIO_PORT_SET5_SETP20_Pos) /*!< GPIO_PORT SET5: SETP20 Mask */ -#define GPIO_PORT_SET5_SETP21_Pos 21 /*!< GPIO_PORT SET5: SETP21 Position */ -#define GPIO_PORT_SET5_SETP21_Msk (0x01UL << GPIO_PORT_SET5_SETP21_Pos) /*!< GPIO_PORT SET5: SETP21 Mask */ -#define GPIO_PORT_SET5_SETP22_Pos 22 /*!< GPIO_PORT SET5: SETP22 Position */ -#define GPIO_PORT_SET5_SETP22_Msk (0x01UL << GPIO_PORT_SET5_SETP22_Pos) /*!< GPIO_PORT SET5: SETP22 Mask */ -#define GPIO_PORT_SET5_SETP23_Pos 23 /*!< GPIO_PORT SET5: SETP23 Position */ -#define GPIO_PORT_SET5_SETP23_Msk (0x01UL << GPIO_PORT_SET5_SETP23_Pos) /*!< GPIO_PORT SET5: SETP23 Mask */ -#define GPIO_PORT_SET5_SETP24_Pos 24 /*!< GPIO_PORT SET5: SETP24 Position */ -#define GPIO_PORT_SET5_SETP24_Msk (0x01UL << GPIO_PORT_SET5_SETP24_Pos) /*!< GPIO_PORT SET5: SETP24 Mask */ -#define GPIO_PORT_SET5_SETP25_Pos 25 /*!< GPIO_PORT SET5: SETP25 Position */ -#define GPIO_PORT_SET5_SETP25_Msk (0x01UL << GPIO_PORT_SET5_SETP25_Pos) /*!< GPIO_PORT SET5: SETP25 Mask */ -#define GPIO_PORT_SET5_SETP26_Pos 26 /*!< GPIO_PORT SET5: SETP26 Position */ -#define GPIO_PORT_SET5_SETP26_Msk (0x01UL << GPIO_PORT_SET5_SETP26_Pos) /*!< GPIO_PORT SET5: SETP26 Mask */ -#define GPIO_PORT_SET5_SETP27_Pos 27 /*!< GPIO_PORT SET5: SETP27 Position */ -#define GPIO_PORT_SET5_SETP27_Msk (0x01UL << GPIO_PORT_SET5_SETP27_Pos) /*!< GPIO_PORT SET5: SETP27 Mask */ -#define GPIO_PORT_SET5_SETP28_Pos 28 /*!< GPIO_PORT SET5: SETP28 Position */ -#define GPIO_PORT_SET5_SETP28_Msk (0x01UL << GPIO_PORT_SET5_SETP28_Pos) /*!< GPIO_PORT SET5: SETP28 Mask */ -#define GPIO_PORT_SET5_SETP29_Pos 29 /*!< GPIO_PORT SET5: SETP29 Position */ -#define GPIO_PORT_SET5_SETP29_Msk (0x01UL << GPIO_PORT_SET5_SETP29_Pos) /*!< GPIO_PORT SET5: SETP29 Mask */ -#define GPIO_PORT_SET5_SETP30_Pos 30 /*!< GPIO_PORT SET5: SETP30 Position */ -#define GPIO_PORT_SET5_SETP30_Msk (0x01UL << GPIO_PORT_SET5_SETP30_Pos) /*!< GPIO_PORT SET5: SETP30 Mask */ -#define GPIO_PORT_SET5_SETP31_Pos 31 /*!< GPIO_PORT SET5: SETP31 Position */ -#define GPIO_PORT_SET5_SETP31_Msk (0x01UL << GPIO_PORT_SET5_SETP31_Pos) /*!< GPIO_PORT SET5: SETP31 Mask */ - -// ------------------------------------- GPIO_PORT_SET6 ----------------------------------------- -#define GPIO_PORT_SET6_SETP0_Pos 0 /*!< GPIO_PORT SET6: SETP0 Position */ -#define GPIO_PORT_SET6_SETP0_Msk (0x01UL << GPIO_PORT_SET6_SETP0_Pos) /*!< GPIO_PORT SET6: SETP0 Mask */ -#define GPIO_PORT_SET6_SETP1_Pos 1 /*!< GPIO_PORT SET6: SETP1 Position */ -#define GPIO_PORT_SET6_SETP1_Msk (0x01UL << GPIO_PORT_SET6_SETP1_Pos) /*!< GPIO_PORT SET6: SETP1 Mask */ -#define GPIO_PORT_SET6_SETP2_Pos 2 /*!< GPIO_PORT SET6: SETP2 Position */ -#define GPIO_PORT_SET6_SETP2_Msk (0x01UL << GPIO_PORT_SET6_SETP2_Pos) /*!< GPIO_PORT SET6: SETP2 Mask */ -#define GPIO_PORT_SET6_SETP3_Pos 3 /*!< GPIO_PORT SET6: SETP3 Position */ -#define GPIO_PORT_SET6_SETP3_Msk (0x01UL << GPIO_PORT_SET6_SETP3_Pos) /*!< GPIO_PORT SET6: SETP3 Mask */ -#define GPIO_PORT_SET6_SETP4_Pos 4 /*!< GPIO_PORT SET6: SETP4 Position */ -#define GPIO_PORT_SET6_SETP4_Msk (0x01UL << GPIO_PORT_SET6_SETP4_Pos) /*!< GPIO_PORT SET6: SETP4 Mask */ -#define GPIO_PORT_SET6_SETP5_Pos 5 /*!< GPIO_PORT SET6: SETP5 Position */ -#define GPIO_PORT_SET6_SETP5_Msk (0x01UL << GPIO_PORT_SET6_SETP5_Pos) /*!< GPIO_PORT SET6: SETP5 Mask */ -#define GPIO_PORT_SET6_SETP6_Pos 6 /*!< GPIO_PORT SET6: SETP6 Position */ -#define GPIO_PORT_SET6_SETP6_Msk (0x01UL << GPIO_PORT_SET6_SETP6_Pos) /*!< GPIO_PORT SET6: SETP6 Mask */ -#define GPIO_PORT_SET6_SETP7_Pos 7 /*!< GPIO_PORT SET6: SETP7 Position */ -#define GPIO_PORT_SET6_SETP7_Msk (0x01UL << GPIO_PORT_SET6_SETP7_Pos) /*!< GPIO_PORT SET6: SETP7 Mask */ -#define GPIO_PORT_SET6_SETP8_Pos 8 /*!< GPIO_PORT SET6: SETP8 Position */ -#define GPIO_PORT_SET6_SETP8_Msk (0x01UL << GPIO_PORT_SET6_SETP8_Pos) /*!< GPIO_PORT SET6: SETP8 Mask */ -#define GPIO_PORT_SET6_SETP9_Pos 9 /*!< GPIO_PORT SET6: SETP9 Position */ -#define GPIO_PORT_SET6_SETP9_Msk (0x01UL << GPIO_PORT_SET6_SETP9_Pos) /*!< GPIO_PORT SET6: SETP9 Mask */ -#define GPIO_PORT_SET6_SETP10_Pos 10 /*!< GPIO_PORT SET6: SETP10 Position */ -#define GPIO_PORT_SET6_SETP10_Msk (0x01UL << GPIO_PORT_SET6_SETP10_Pos) /*!< GPIO_PORT SET6: SETP10 Mask */ -#define GPIO_PORT_SET6_SETP11_Pos 11 /*!< GPIO_PORT SET6: SETP11 Position */ -#define GPIO_PORT_SET6_SETP11_Msk (0x01UL << GPIO_PORT_SET6_SETP11_Pos) /*!< GPIO_PORT SET6: SETP11 Mask */ -#define GPIO_PORT_SET6_SETP12_Pos 12 /*!< GPIO_PORT SET6: SETP12 Position */ -#define GPIO_PORT_SET6_SETP12_Msk (0x01UL << GPIO_PORT_SET6_SETP12_Pos) /*!< GPIO_PORT SET6: SETP12 Mask */ -#define GPIO_PORT_SET6_SETP13_Pos 13 /*!< GPIO_PORT SET6: SETP13 Position */ -#define GPIO_PORT_SET6_SETP13_Msk (0x01UL << GPIO_PORT_SET6_SETP13_Pos) /*!< GPIO_PORT SET6: SETP13 Mask */ -#define GPIO_PORT_SET6_SETP14_Pos 14 /*!< GPIO_PORT SET6: SETP14 Position */ -#define GPIO_PORT_SET6_SETP14_Msk (0x01UL << GPIO_PORT_SET6_SETP14_Pos) /*!< GPIO_PORT SET6: SETP14 Mask */ -#define GPIO_PORT_SET6_SETP15_Pos 15 /*!< GPIO_PORT SET6: SETP15 Position */ -#define GPIO_PORT_SET6_SETP15_Msk (0x01UL << GPIO_PORT_SET6_SETP15_Pos) /*!< GPIO_PORT SET6: SETP15 Mask */ -#define GPIO_PORT_SET6_SETP16_Pos 16 /*!< GPIO_PORT SET6: SETP16 Position */ -#define GPIO_PORT_SET6_SETP16_Msk (0x01UL << GPIO_PORT_SET6_SETP16_Pos) /*!< GPIO_PORT SET6: SETP16 Mask */ -#define GPIO_PORT_SET6_SETP17_Pos 17 /*!< GPIO_PORT SET6: SETP17 Position */ -#define GPIO_PORT_SET6_SETP17_Msk (0x01UL << GPIO_PORT_SET6_SETP17_Pos) /*!< GPIO_PORT SET6: SETP17 Mask */ -#define GPIO_PORT_SET6_SETP18_Pos 18 /*!< GPIO_PORT SET6: SETP18 Position */ -#define GPIO_PORT_SET6_SETP18_Msk (0x01UL << GPIO_PORT_SET6_SETP18_Pos) /*!< GPIO_PORT SET6: SETP18 Mask */ -#define GPIO_PORT_SET6_SETP19_Pos 19 /*!< GPIO_PORT SET6: SETP19 Position */ -#define GPIO_PORT_SET6_SETP19_Msk (0x01UL << GPIO_PORT_SET6_SETP19_Pos) /*!< GPIO_PORT SET6: SETP19 Mask */ -#define GPIO_PORT_SET6_SETP20_Pos 20 /*!< GPIO_PORT SET6: SETP20 Position */ -#define GPIO_PORT_SET6_SETP20_Msk (0x01UL << GPIO_PORT_SET6_SETP20_Pos) /*!< GPIO_PORT SET6: SETP20 Mask */ -#define GPIO_PORT_SET6_SETP21_Pos 21 /*!< GPIO_PORT SET6: SETP21 Position */ -#define GPIO_PORT_SET6_SETP21_Msk (0x01UL << GPIO_PORT_SET6_SETP21_Pos) /*!< GPIO_PORT SET6: SETP21 Mask */ -#define GPIO_PORT_SET6_SETP22_Pos 22 /*!< GPIO_PORT SET6: SETP22 Position */ -#define GPIO_PORT_SET6_SETP22_Msk (0x01UL << GPIO_PORT_SET6_SETP22_Pos) /*!< GPIO_PORT SET6: SETP22 Mask */ -#define GPIO_PORT_SET6_SETP23_Pos 23 /*!< GPIO_PORT SET6: SETP23 Position */ -#define GPIO_PORT_SET6_SETP23_Msk (0x01UL << GPIO_PORT_SET6_SETP23_Pos) /*!< GPIO_PORT SET6: SETP23 Mask */ -#define GPIO_PORT_SET6_SETP24_Pos 24 /*!< GPIO_PORT SET6: SETP24 Position */ -#define GPIO_PORT_SET6_SETP24_Msk (0x01UL << GPIO_PORT_SET6_SETP24_Pos) /*!< GPIO_PORT SET6: SETP24 Mask */ -#define GPIO_PORT_SET6_SETP25_Pos 25 /*!< GPIO_PORT SET6: SETP25 Position */ -#define GPIO_PORT_SET6_SETP25_Msk (0x01UL << GPIO_PORT_SET6_SETP25_Pos) /*!< GPIO_PORT SET6: SETP25 Mask */ -#define GPIO_PORT_SET6_SETP26_Pos 26 /*!< GPIO_PORT SET6: SETP26 Position */ -#define GPIO_PORT_SET6_SETP26_Msk (0x01UL << GPIO_PORT_SET6_SETP26_Pos) /*!< GPIO_PORT SET6: SETP26 Mask */ -#define GPIO_PORT_SET6_SETP27_Pos 27 /*!< GPIO_PORT SET6: SETP27 Position */ -#define GPIO_PORT_SET6_SETP27_Msk (0x01UL << GPIO_PORT_SET6_SETP27_Pos) /*!< GPIO_PORT SET6: SETP27 Mask */ -#define GPIO_PORT_SET6_SETP28_Pos 28 /*!< GPIO_PORT SET6: SETP28 Position */ -#define GPIO_PORT_SET6_SETP28_Msk (0x01UL << GPIO_PORT_SET6_SETP28_Pos) /*!< GPIO_PORT SET6: SETP28 Mask */ -#define GPIO_PORT_SET6_SETP29_Pos 29 /*!< GPIO_PORT SET6: SETP29 Position */ -#define GPIO_PORT_SET6_SETP29_Msk (0x01UL << GPIO_PORT_SET6_SETP29_Pos) /*!< GPIO_PORT SET6: SETP29 Mask */ -#define GPIO_PORT_SET6_SETP30_Pos 30 /*!< GPIO_PORT SET6: SETP30 Position */ -#define GPIO_PORT_SET6_SETP30_Msk (0x01UL << GPIO_PORT_SET6_SETP30_Pos) /*!< GPIO_PORT SET6: SETP30 Mask */ -#define GPIO_PORT_SET6_SETP31_Pos 31 /*!< GPIO_PORT SET6: SETP31 Position */ -#define GPIO_PORT_SET6_SETP31_Msk (0x01UL << GPIO_PORT_SET6_SETP31_Pos) /*!< GPIO_PORT SET6: SETP31 Mask */ - -// ------------------------------------- GPIO_PORT_SET7 ----------------------------------------- -#define GPIO_PORT_SET7_SETP0_Pos 0 /*!< GPIO_PORT SET7: SETP0 Position */ -#define GPIO_PORT_SET7_SETP0_Msk (0x01UL << GPIO_PORT_SET7_SETP0_Pos) /*!< GPIO_PORT SET7: SETP0 Mask */ -#define GPIO_PORT_SET7_SETP1_Pos 1 /*!< GPIO_PORT SET7: SETP1 Position */ -#define GPIO_PORT_SET7_SETP1_Msk (0x01UL << GPIO_PORT_SET7_SETP1_Pos) /*!< GPIO_PORT SET7: SETP1 Mask */ -#define GPIO_PORT_SET7_SETP2_Pos 2 /*!< GPIO_PORT SET7: SETP2 Position */ -#define GPIO_PORT_SET7_SETP2_Msk (0x01UL << GPIO_PORT_SET7_SETP2_Pos) /*!< GPIO_PORT SET7: SETP2 Mask */ -#define GPIO_PORT_SET7_SETP3_Pos 3 /*!< GPIO_PORT SET7: SETP3 Position */ -#define GPIO_PORT_SET7_SETP3_Msk (0x01UL << GPIO_PORT_SET7_SETP3_Pos) /*!< GPIO_PORT SET7: SETP3 Mask */ -#define GPIO_PORT_SET7_SETP4_Pos 4 /*!< GPIO_PORT SET7: SETP4 Position */ -#define GPIO_PORT_SET7_SETP4_Msk (0x01UL << GPIO_PORT_SET7_SETP4_Pos) /*!< GPIO_PORT SET7: SETP4 Mask */ -#define GPIO_PORT_SET7_SETP5_Pos 5 /*!< GPIO_PORT SET7: SETP5 Position */ -#define GPIO_PORT_SET7_SETP5_Msk (0x01UL << GPIO_PORT_SET7_SETP5_Pos) /*!< GPIO_PORT SET7: SETP5 Mask */ -#define GPIO_PORT_SET7_SETP6_Pos 6 /*!< GPIO_PORT SET7: SETP6 Position */ -#define GPIO_PORT_SET7_SETP6_Msk (0x01UL << GPIO_PORT_SET7_SETP6_Pos) /*!< GPIO_PORT SET7: SETP6 Mask */ -#define GPIO_PORT_SET7_SETP7_Pos 7 /*!< GPIO_PORT SET7: SETP7 Position */ -#define GPIO_PORT_SET7_SETP7_Msk (0x01UL << GPIO_PORT_SET7_SETP7_Pos) /*!< GPIO_PORT SET7: SETP7 Mask */ -#define GPIO_PORT_SET7_SETP8_Pos 8 /*!< GPIO_PORT SET7: SETP8 Position */ -#define GPIO_PORT_SET7_SETP8_Msk (0x01UL << GPIO_PORT_SET7_SETP8_Pos) /*!< GPIO_PORT SET7: SETP8 Mask */ -#define GPIO_PORT_SET7_SETP9_Pos 9 /*!< GPIO_PORT SET7: SETP9 Position */ -#define GPIO_PORT_SET7_SETP9_Msk (0x01UL << GPIO_PORT_SET7_SETP9_Pos) /*!< GPIO_PORT SET7: SETP9 Mask */ -#define GPIO_PORT_SET7_SETP10_Pos 10 /*!< GPIO_PORT SET7: SETP10 Position */ -#define GPIO_PORT_SET7_SETP10_Msk (0x01UL << GPIO_PORT_SET7_SETP10_Pos) /*!< GPIO_PORT SET7: SETP10 Mask */ -#define GPIO_PORT_SET7_SETP11_Pos 11 /*!< GPIO_PORT SET7: SETP11 Position */ -#define GPIO_PORT_SET7_SETP11_Msk (0x01UL << GPIO_PORT_SET7_SETP11_Pos) /*!< GPIO_PORT SET7: SETP11 Mask */ -#define GPIO_PORT_SET7_SETP12_Pos 12 /*!< GPIO_PORT SET7: SETP12 Position */ -#define GPIO_PORT_SET7_SETP12_Msk (0x01UL << GPIO_PORT_SET7_SETP12_Pos) /*!< GPIO_PORT SET7: SETP12 Mask */ -#define GPIO_PORT_SET7_SETP13_Pos 13 /*!< GPIO_PORT SET7: SETP13 Position */ -#define GPIO_PORT_SET7_SETP13_Msk (0x01UL << GPIO_PORT_SET7_SETP13_Pos) /*!< GPIO_PORT SET7: SETP13 Mask */ -#define GPIO_PORT_SET7_SETP14_Pos 14 /*!< GPIO_PORT SET7: SETP14 Position */ -#define GPIO_PORT_SET7_SETP14_Msk (0x01UL << GPIO_PORT_SET7_SETP14_Pos) /*!< GPIO_PORT SET7: SETP14 Mask */ -#define GPIO_PORT_SET7_SETP15_Pos 15 /*!< GPIO_PORT SET7: SETP15 Position */ -#define GPIO_PORT_SET7_SETP15_Msk (0x01UL << GPIO_PORT_SET7_SETP15_Pos) /*!< GPIO_PORT SET7: SETP15 Mask */ -#define GPIO_PORT_SET7_SETP16_Pos 16 /*!< GPIO_PORT SET7: SETP16 Position */ -#define GPIO_PORT_SET7_SETP16_Msk (0x01UL << GPIO_PORT_SET7_SETP16_Pos) /*!< GPIO_PORT SET7: SETP16 Mask */ -#define GPIO_PORT_SET7_SETP17_Pos 17 /*!< GPIO_PORT SET7: SETP17 Position */ -#define GPIO_PORT_SET7_SETP17_Msk (0x01UL << GPIO_PORT_SET7_SETP17_Pos) /*!< GPIO_PORT SET7: SETP17 Mask */ -#define GPIO_PORT_SET7_SETP18_Pos 18 /*!< GPIO_PORT SET7: SETP18 Position */ -#define GPIO_PORT_SET7_SETP18_Msk (0x01UL << GPIO_PORT_SET7_SETP18_Pos) /*!< GPIO_PORT SET7: SETP18 Mask */ -#define GPIO_PORT_SET7_SETP19_Pos 19 /*!< GPIO_PORT SET7: SETP19 Position */ -#define GPIO_PORT_SET7_SETP19_Msk (0x01UL << GPIO_PORT_SET7_SETP19_Pos) /*!< GPIO_PORT SET7: SETP19 Mask */ -#define GPIO_PORT_SET7_SETP20_Pos 20 /*!< GPIO_PORT SET7: SETP20 Position */ -#define GPIO_PORT_SET7_SETP20_Msk (0x01UL << GPIO_PORT_SET7_SETP20_Pos) /*!< GPIO_PORT SET7: SETP20 Mask */ -#define GPIO_PORT_SET7_SETP21_Pos 21 /*!< GPIO_PORT SET7: SETP21 Position */ -#define GPIO_PORT_SET7_SETP21_Msk (0x01UL << GPIO_PORT_SET7_SETP21_Pos) /*!< GPIO_PORT SET7: SETP21 Mask */ -#define GPIO_PORT_SET7_SETP22_Pos 22 /*!< GPIO_PORT SET7: SETP22 Position */ -#define GPIO_PORT_SET7_SETP22_Msk (0x01UL << GPIO_PORT_SET7_SETP22_Pos) /*!< GPIO_PORT SET7: SETP22 Mask */ -#define GPIO_PORT_SET7_SETP23_Pos 23 /*!< GPIO_PORT SET7: SETP23 Position */ -#define GPIO_PORT_SET7_SETP23_Msk (0x01UL << GPIO_PORT_SET7_SETP23_Pos) /*!< GPIO_PORT SET7: SETP23 Mask */ -#define GPIO_PORT_SET7_SETP24_Pos 24 /*!< GPIO_PORT SET7: SETP24 Position */ -#define GPIO_PORT_SET7_SETP24_Msk (0x01UL << GPIO_PORT_SET7_SETP24_Pos) /*!< GPIO_PORT SET7: SETP24 Mask */ -#define GPIO_PORT_SET7_SETP25_Pos 25 /*!< GPIO_PORT SET7: SETP25 Position */ -#define GPIO_PORT_SET7_SETP25_Msk (0x01UL << GPIO_PORT_SET7_SETP25_Pos) /*!< GPIO_PORT SET7: SETP25 Mask */ -#define GPIO_PORT_SET7_SETP26_Pos 26 /*!< GPIO_PORT SET7: SETP26 Position */ -#define GPIO_PORT_SET7_SETP26_Msk (0x01UL << GPIO_PORT_SET7_SETP26_Pos) /*!< GPIO_PORT SET7: SETP26 Mask */ -#define GPIO_PORT_SET7_SETP27_Pos 27 /*!< GPIO_PORT SET7: SETP27 Position */ -#define GPIO_PORT_SET7_SETP27_Msk (0x01UL << GPIO_PORT_SET7_SETP27_Pos) /*!< GPIO_PORT SET7: SETP27 Mask */ -#define GPIO_PORT_SET7_SETP28_Pos 28 /*!< GPIO_PORT SET7: SETP28 Position */ -#define GPIO_PORT_SET7_SETP28_Msk (0x01UL << GPIO_PORT_SET7_SETP28_Pos) /*!< GPIO_PORT SET7: SETP28 Mask */ -#define GPIO_PORT_SET7_SETP29_Pos 29 /*!< GPIO_PORT SET7: SETP29 Position */ -#define GPIO_PORT_SET7_SETP29_Msk (0x01UL << GPIO_PORT_SET7_SETP29_Pos) /*!< GPIO_PORT SET7: SETP29 Mask */ -#define GPIO_PORT_SET7_SETP30_Pos 30 /*!< GPIO_PORT SET7: SETP30 Position */ -#define GPIO_PORT_SET7_SETP30_Msk (0x01UL << GPIO_PORT_SET7_SETP30_Pos) /*!< GPIO_PORT SET7: SETP30 Mask */ -#define GPIO_PORT_SET7_SETP31_Pos 31 /*!< GPIO_PORT SET7: SETP31 Position */ -#define GPIO_PORT_SET7_SETP31_Msk (0x01UL << GPIO_PORT_SET7_SETP31_Pos) /*!< GPIO_PORT SET7: SETP31 Mask */ - -// ------------------------------------- GPIO_PORT_CLR0 ----------------------------------------- -#define GPIO_PORT_CLR0_CLRP00_Pos 0 /*!< GPIO_PORT CLR0: CLRP00 Position */ -#define GPIO_PORT_CLR0_CLRP00_Msk (0x01UL << GPIO_PORT_CLR0_CLRP00_Pos) /*!< GPIO_PORT CLR0: CLRP00 Mask */ -#define GPIO_PORT_CLR0_CLRP01_Pos 1 /*!< GPIO_PORT CLR0: CLRP01 Position */ -#define GPIO_PORT_CLR0_CLRP01_Msk (0x01UL << GPIO_PORT_CLR0_CLRP01_Pos) /*!< GPIO_PORT CLR0: CLRP01 Mask */ -#define GPIO_PORT_CLR0_CLRP02_Pos 2 /*!< GPIO_PORT CLR0: CLRP02 Position */ -#define GPIO_PORT_CLR0_CLRP02_Msk (0x01UL << GPIO_PORT_CLR0_CLRP02_Pos) /*!< GPIO_PORT CLR0: CLRP02 Mask */ -#define GPIO_PORT_CLR0_CLRP03_Pos 3 /*!< GPIO_PORT CLR0: CLRP03 Position */ -#define GPIO_PORT_CLR0_CLRP03_Msk (0x01UL << GPIO_PORT_CLR0_CLRP03_Pos) /*!< GPIO_PORT CLR0: CLRP03 Mask */ -#define GPIO_PORT_CLR0_CLRP04_Pos 4 /*!< GPIO_PORT CLR0: CLRP04 Position */ -#define GPIO_PORT_CLR0_CLRP04_Msk (0x01UL << GPIO_PORT_CLR0_CLRP04_Pos) /*!< GPIO_PORT CLR0: CLRP04 Mask */ -#define GPIO_PORT_CLR0_CLRP05_Pos 5 /*!< GPIO_PORT CLR0: CLRP05 Position */ -#define GPIO_PORT_CLR0_CLRP05_Msk (0x01UL << GPIO_PORT_CLR0_CLRP05_Pos) /*!< GPIO_PORT CLR0: CLRP05 Mask */ -#define GPIO_PORT_CLR0_CLRP06_Pos 6 /*!< GPIO_PORT CLR0: CLRP06 Position */ -#define GPIO_PORT_CLR0_CLRP06_Msk (0x01UL << GPIO_PORT_CLR0_CLRP06_Pos) /*!< GPIO_PORT CLR0: CLRP06 Mask */ -#define GPIO_PORT_CLR0_CLRP07_Pos 7 /*!< GPIO_PORT CLR0: CLRP07 Position */ -#define GPIO_PORT_CLR0_CLRP07_Msk (0x01UL << GPIO_PORT_CLR0_CLRP07_Pos) /*!< GPIO_PORT CLR0: CLRP07 Mask */ -#define GPIO_PORT_CLR0_CLRP08_Pos 8 /*!< GPIO_PORT CLR0: CLRP08 Position */ -#define GPIO_PORT_CLR0_CLRP08_Msk (0x01UL << GPIO_PORT_CLR0_CLRP08_Pos) /*!< GPIO_PORT CLR0: CLRP08 Mask */ -#define GPIO_PORT_CLR0_CLRP09_Pos 9 /*!< GPIO_PORT CLR0: CLRP09 Position */ -#define GPIO_PORT_CLR0_CLRP09_Msk (0x01UL << GPIO_PORT_CLR0_CLRP09_Pos) /*!< GPIO_PORT CLR0: CLRP09 Mask */ -#define GPIO_PORT_CLR0_CLRP010_Pos 10 /*!< GPIO_PORT CLR0: CLRP010 Position */ -#define GPIO_PORT_CLR0_CLRP010_Msk (0x01UL << GPIO_PORT_CLR0_CLRP010_Pos) /*!< GPIO_PORT CLR0: CLRP010 Mask */ -#define GPIO_PORT_CLR0_CLRP011_Pos 11 /*!< GPIO_PORT CLR0: CLRP011 Position */ -#define GPIO_PORT_CLR0_CLRP011_Msk (0x01UL << GPIO_PORT_CLR0_CLRP011_Pos) /*!< GPIO_PORT CLR0: CLRP011 Mask */ -#define GPIO_PORT_CLR0_CLRP012_Pos 12 /*!< GPIO_PORT CLR0: CLRP012 Position */ -#define GPIO_PORT_CLR0_CLRP012_Msk (0x01UL << GPIO_PORT_CLR0_CLRP012_Pos) /*!< GPIO_PORT CLR0: CLRP012 Mask */ -#define GPIO_PORT_CLR0_CLRP013_Pos 13 /*!< GPIO_PORT CLR0: CLRP013 Position */ -#define GPIO_PORT_CLR0_CLRP013_Msk (0x01UL << GPIO_PORT_CLR0_CLRP013_Pos) /*!< GPIO_PORT CLR0: CLRP013 Mask */ -#define GPIO_PORT_CLR0_CLRP014_Pos 14 /*!< GPIO_PORT CLR0: CLRP014 Position */ -#define GPIO_PORT_CLR0_CLRP014_Msk (0x01UL << GPIO_PORT_CLR0_CLRP014_Pos) /*!< GPIO_PORT CLR0: CLRP014 Mask */ -#define GPIO_PORT_CLR0_CLRP015_Pos 15 /*!< GPIO_PORT CLR0: CLRP015 Position */ -#define GPIO_PORT_CLR0_CLRP015_Msk (0x01UL << GPIO_PORT_CLR0_CLRP015_Pos) /*!< GPIO_PORT CLR0: CLRP015 Mask */ -#define GPIO_PORT_CLR0_CLRP016_Pos 16 /*!< GPIO_PORT CLR0: CLRP016 Position */ -#define GPIO_PORT_CLR0_CLRP016_Msk (0x01UL << GPIO_PORT_CLR0_CLRP016_Pos) /*!< GPIO_PORT CLR0: CLRP016 Mask */ -#define GPIO_PORT_CLR0_CLRP017_Pos 17 /*!< GPIO_PORT CLR0: CLRP017 Position */ -#define GPIO_PORT_CLR0_CLRP017_Msk (0x01UL << GPIO_PORT_CLR0_CLRP017_Pos) /*!< GPIO_PORT CLR0: CLRP017 Mask */ -#define GPIO_PORT_CLR0_CLRP018_Pos 18 /*!< GPIO_PORT CLR0: CLRP018 Position */ -#define GPIO_PORT_CLR0_CLRP018_Msk (0x01UL << GPIO_PORT_CLR0_CLRP018_Pos) /*!< GPIO_PORT CLR0: CLRP018 Mask */ -#define GPIO_PORT_CLR0_CLRP019_Pos 19 /*!< GPIO_PORT CLR0: CLRP019 Position */ -#define GPIO_PORT_CLR0_CLRP019_Msk (0x01UL << GPIO_PORT_CLR0_CLRP019_Pos) /*!< GPIO_PORT CLR0: CLRP019 Mask */ -#define GPIO_PORT_CLR0_CLRP020_Pos 20 /*!< GPIO_PORT CLR0: CLRP020 Position */ -#define GPIO_PORT_CLR0_CLRP020_Msk (0x01UL << GPIO_PORT_CLR0_CLRP020_Pos) /*!< GPIO_PORT CLR0: CLRP020 Mask */ -#define GPIO_PORT_CLR0_CLRP021_Pos 21 /*!< GPIO_PORT CLR0: CLRP021 Position */ -#define GPIO_PORT_CLR0_CLRP021_Msk (0x01UL << GPIO_PORT_CLR0_CLRP021_Pos) /*!< GPIO_PORT CLR0: CLRP021 Mask */ -#define GPIO_PORT_CLR0_CLRP022_Pos 22 /*!< GPIO_PORT CLR0: CLRP022 Position */ -#define GPIO_PORT_CLR0_CLRP022_Msk (0x01UL << GPIO_PORT_CLR0_CLRP022_Pos) /*!< GPIO_PORT CLR0: CLRP022 Mask */ -#define GPIO_PORT_CLR0_CLRP023_Pos 23 /*!< GPIO_PORT CLR0: CLRP023 Position */ -#define GPIO_PORT_CLR0_CLRP023_Msk (0x01UL << GPIO_PORT_CLR0_CLRP023_Pos) /*!< GPIO_PORT CLR0: CLRP023 Mask */ -#define GPIO_PORT_CLR0_CLRP024_Pos 24 /*!< GPIO_PORT CLR0: CLRP024 Position */ -#define GPIO_PORT_CLR0_CLRP024_Msk (0x01UL << GPIO_PORT_CLR0_CLRP024_Pos) /*!< GPIO_PORT CLR0: CLRP024 Mask */ -#define GPIO_PORT_CLR0_CLRP025_Pos 25 /*!< GPIO_PORT CLR0: CLRP025 Position */ -#define GPIO_PORT_CLR0_CLRP025_Msk (0x01UL << GPIO_PORT_CLR0_CLRP025_Pos) /*!< GPIO_PORT CLR0: CLRP025 Mask */ -#define GPIO_PORT_CLR0_CLRP026_Pos 26 /*!< GPIO_PORT CLR0: CLRP026 Position */ -#define GPIO_PORT_CLR0_CLRP026_Msk (0x01UL << GPIO_PORT_CLR0_CLRP026_Pos) /*!< GPIO_PORT CLR0: CLRP026 Mask */ -#define GPIO_PORT_CLR0_CLRP027_Pos 27 /*!< GPIO_PORT CLR0: CLRP027 Position */ -#define GPIO_PORT_CLR0_CLRP027_Msk (0x01UL << GPIO_PORT_CLR0_CLRP027_Pos) /*!< GPIO_PORT CLR0: CLRP027 Mask */ -#define GPIO_PORT_CLR0_CLRP028_Pos 28 /*!< GPIO_PORT CLR0: CLRP028 Position */ -#define GPIO_PORT_CLR0_CLRP028_Msk (0x01UL << GPIO_PORT_CLR0_CLRP028_Pos) /*!< GPIO_PORT CLR0: CLRP028 Mask */ -#define GPIO_PORT_CLR0_CLRP029_Pos 29 /*!< GPIO_PORT CLR0: CLRP029 Position */ -#define GPIO_PORT_CLR0_CLRP029_Msk (0x01UL << GPIO_PORT_CLR0_CLRP029_Pos) /*!< GPIO_PORT CLR0: CLRP029 Mask */ -#define GPIO_PORT_CLR0_CLRP030_Pos 30 /*!< GPIO_PORT CLR0: CLRP030 Position */ -#define GPIO_PORT_CLR0_CLRP030_Msk (0x01UL << GPIO_PORT_CLR0_CLRP030_Pos) /*!< GPIO_PORT CLR0: CLRP030 Mask */ -#define GPIO_PORT_CLR0_CLRP031_Pos 31 /*!< GPIO_PORT CLR0: CLRP031 Position */ -#define GPIO_PORT_CLR0_CLRP031_Msk (0x01UL << GPIO_PORT_CLR0_CLRP031_Pos) /*!< GPIO_PORT CLR0: CLRP031 Mask */ - -// ------------------------------------- GPIO_PORT_CLR1 ----------------------------------------- -#define GPIO_PORT_CLR1_CLRP00_Pos 0 /*!< GPIO_PORT CLR1: CLRP00 Position */ -#define GPIO_PORT_CLR1_CLRP00_Msk (0x01UL << GPIO_PORT_CLR1_CLRP00_Pos) /*!< GPIO_PORT CLR1: CLRP00 Mask */ -#define GPIO_PORT_CLR1_CLRP01_Pos 1 /*!< GPIO_PORT CLR1: CLRP01 Position */ -#define GPIO_PORT_CLR1_CLRP01_Msk (0x01UL << GPIO_PORT_CLR1_CLRP01_Pos) /*!< GPIO_PORT CLR1: CLRP01 Mask */ -#define GPIO_PORT_CLR1_CLRP02_Pos 2 /*!< GPIO_PORT CLR1: CLRP02 Position */ -#define GPIO_PORT_CLR1_CLRP02_Msk (0x01UL << GPIO_PORT_CLR1_CLRP02_Pos) /*!< GPIO_PORT CLR1: CLRP02 Mask */ -#define GPIO_PORT_CLR1_CLRP03_Pos 3 /*!< GPIO_PORT CLR1: CLRP03 Position */ -#define GPIO_PORT_CLR1_CLRP03_Msk (0x01UL << GPIO_PORT_CLR1_CLRP03_Pos) /*!< GPIO_PORT CLR1: CLRP03 Mask */ -#define GPIO_PORT_CLR1_CLRP04_Pos 4 /*!< GPIO_PORT CLR1: CLRP04 Position */ -#define GPIO_PORT_CLR1_CLRP04_Msk (0x01UL << GPIO_PORT_CLR1_CLRP04_Pos) /*!< GPIO_PORT CLR1: CLRP04 Mask */ -#define GPIO_PORT_CLR1_CLRP05_Pos 5 /*!< GPIO_PORT CLR1: CLRP05 Position */ -#define GPIO_PORT_CLR1_CLRP05_Msk (0x01UL << GPIO_PORT_CLR1_CLRP05_Pos) /*!< GPIO_PORT CLR1: CLRP05 Mask */ -#define GPIO_PORT_CLR1_CLRP06_Pos 6 /*!< GPIO_PORT CLR1: CLRP06 Position */ -#define GPIO_PORT_CLR1_CLRP06_Msk (0x01UL << GPIO_PORT_CLR1_CLRP06_Pos) /*!< GPIO_PORT CLR1: CLRP06 Mask */ -#define GPIO_PORT_CLR1_CLRP07_Pos 7 /*!< GPIO_PORT CLR1: CLRP07 Position */ -#define GPIO_PORT_CLR1_CLRP07_Msk (0x01UL << GPIO_PORT_CLR1_CLRP07_Pos) /*!< GPIO_PORT CLR1: CLRP07 Mask */ -#define GPIO_PORT_CLR1_CLRP08_Pos 8 /*!< GPIO_PORT CLR1: CLRP08 Position */ -#define GPIO_PORT_CLR1_CLRP08_Msk (0x01UL << GPIO_PORT_CLR1_CLRP08_Pos) /*!< GPIO_PORT CLR1: CLRP08 Mask */ -#define GPIO_PORT_CLR1_CLRP09_Pos 9 /*!< GPIO_PORT CLR1: CLRP09 Position */ -#define GPIO_PORT_CLR1_CLRP09_Msk (0x01UL << GPIO_PORT_CLR1_CLRP09_Pos) /*!< GPIO_PORT CLR1: CLRP09 Mask */ -#define GPIO_PORT_CLR1_CLRP010_Pos 10 /*!< GPIO_PORT CLR1: CLRP010 Position */ -#define GPIO_PORT_CLR1_CLRP010_Msk (0x01UL << GPIO_PORT_CLR1_CLRP010_Pos) /*!< GPIO_PORT CLR1: CLRP010 Mask */ -#define GPIO_PORT_CLR1_CLRP011_Pos 11 /*!< GPIO_PORT CLR1: CLRP011 Position */ -#define GPIO_PORT_CLR1_CLRP011_Msk (0x01UL << GPIO_PORT_CLR1_CLRP011_Pos) /*!< GPIO_PORT CLR1: CLRP011 Mask */ -#define GPIO_PORT_CLR1_CLRP012_Pos 12 /*!< GPIO_PORT CLR1: CLRP012 Position */ -#define GPIO_PORT_CLR1_CLRP012_Msk (0x01UL << GPIO_PORT_CLR1_CLRP012_Pos) /*!< GPIO_PORT CLR1: CLRP012 Mask */ -#define GPIO_PORT_CLR1_CLRP013_Pos 13 /*!< GPIO_PORT CLR1: CLRP013 Position */ -#define GPIO_PORT_CLR1_CLRP013_Msk (0x01UL << GPIO_PORT_CLR1_CLRP013_Pos) /*!< GPIO_PORT CLR1: CLRP013 Mask */ -#define GPIO_PORT_CLR1_CLRP014_Pos 14 /*!< GPIO_PORT CLR1: CLRP014 Position */ -#define GPIO_PORT_CLR1_CLRP014_Msk (0x01UL << GPIO_PORT_CLR1_CLRP014_Pos) /*!< GPIO_PORT CLR1: CLRP014 Mask */ -#define GPIO_PORT_CLR1_CLRP015_Pos 15 /*!< GPIO_PORT CLR1: CLRP015 Position */ -#define GPIO_PORT_CLR1_CLRP015_Msk (0x01UL << GPIO_PORT_CLR1_CLRP015_Pos) /*!< GPIO_PORT CLR1: CLRP015 Mask */ -#define GPIO_PORT_CLR1_CLRP016_Pos 16 /*!< GPIO_PORT CLR1: CLRP016 Position */ -#define GPIO_PORT_CLR1_CLRP016_Msk (0x01UL << GPIO_PORT_CLR1_CLRP016_Pos) /*!< GPIO_PORT CLR1: CLRP016 Mask */ -#define GPIO_PORT_CLR1_CLRP017_Pos 17 /*!< GPIO_PORT CLR1: CLRP017 Position */ -#define GPIO_PORT_CLR1_CLRP017_Msk (0x01UL << GPIO_PORT_CLR1_CLRP017_Pos) /*!< GPIO_PORT CLR1: CLRP017 Mask */ -#define GPIO_PORT_CLR1_CLRP018_Pos 18 /*!< GPIO_PORT CLR1: CLRP018 Position */ -#define GPIO_PORT_CLR1_CLRP018_Msk (0x01UL << GPIO_PORT_CLR1_CLRP018_Pos) /*!< GPIO_PORT CLR1: CLRP018 Mask */ -#define GPIO_PORT_CLR1_CLRP019_Pos 19 /*!< GPIO_PORT CLR1: CLRP019 Position */ -#define GPIO_PORT_CLR1_CLRP019_Msk (0x01UL << GPIO_PORT_CLR1_CLRP019_Pos) /*!< GPIO_PORT CLR1: CLRP019 Mask */ -#define GPIO_PORT_CLR1_CLRP020_Pos 20 /*!< GPIO_PORT CLR1: CLRP020 Position */ -#define GPIO_PORT_CLR1_CLRP020_Msk (0x01UL << GPIO_PORT_CLR1_CLRP020_Pos) /*!< GPIO_PORT CLR1: CLRP020 Mask */ -#define GPIO_PORT_CLR1_CLRP021_Pos 21 /*!< GPIO_PORT CLR1: CLRP021 Position */ -#define GPIO_PORT_CLR1_CLRP021_Msk (0x01UL << GPIO_PORT_CLR1_CLRP021_Pos) /*!< GPIO_PORT CLR1: CLRP021 Mask */ -#define GPIO_PORT_CLR1_CLRP022_Pos 22 /*!< GPIO_PORT CLR1: CLRP022 Position */ -#define GPIO_PORT_CLR1_CLRP022_Msk (0x01UL << GPIO_PORT_CLR1_CLRP022_Pos) /*!< GPIO_PORT CLR1: CLRP022 Mask */ -#define GPIO_PORT_CLR1_CLRP023_Pos 23 /*!< GPIO_PORT CLR1: CLRP023 Position */ -#define GPIO_PORT_CLR1_CLRP023_Msk (0x01UL << GPIO_PORT_CLR1_CLRP023_Pos) /*!< GPIO_PORT CLR1: CLRP023 Mask */ -#define GPIO_PORT_CLR1_CLRP024_Pos 24 /*!< GPIO_PORT CLR1: CLRP024 Position */ -#define GPIO_PORT_CLR1_CLRP024_Msk (0x01UL << GPIO_PORT_CLR1_CLRP024_Pos) /*!< GPIO_PORT CLR1: CLRP024 Mask */ -#define GPIO_PORT_CLR1_CLRP025_Pos 25 /*!< GPIO_PORT CLR1: CLRP025 Position */ -#define GPIO_PORT_CLR1_CLRP025_Msk (0x01UL << GPIO_PORT_CLR1_CLRP025_Pos) /*!< GPIO_PORT CLR1: CLRP025 Mask */ -#define GPIO_PORT_CLR1_CLRP026_Pos 26 /*!< GPIO_PORT CLR1: CLRP026 Position */ -#define GPIO_PORT_CLR1_CLRP026_Msk (0x01UL << GPIO_PORT_CLR1_CLRP026_Pos) /*!< GPIO_PORT CLR1: CLRP026 Mask */ -#define GPIO_PORT_CLR1_CLRP027_Pos 27 /*!< GPIO_PORT CLR1: CLRP027 Position */ -#define GPIO_PORT_CLR1_CLRP027_Msk (0x01UL << GPIO_PORT_CLR1_CLRP027_Pos) /*!< GPIO_PORT CLR1: CLRP027 Mask */ -#define GPIO_PORT_CLR1_CLRP028_Pos 28 /*!< GPIO_PORT CLR1: CLRP028 Position */ -#define GPIO_PORT_CLR1_CLRP028_Msk (0x01UL << GPIO_PORT_CLR1_CLRP028_Pos) /*!< GPIO_PORT CLR1: CLRP028 Mask */ -#define GPIO_PORT_CLR1_CLRP029_Pos 29 /*!< GPIO_PORT CLR1: CLRP029 Position */ -#define GPIO_PORT_CLR1_CLRP029_Msk (0x01UL << GPIO_PORT_CLR1_CLRP029_Pos) /*!< GPIO_PORT CLR1: CLRP029 Mask */ -#define GPIO_PORT_CLR1_CLRP030_Pos 30 /*!< GPIO_PORT CLR1: CLRP030 Position */ -#define GPIO_PORT_CLR1_CLRP030_Msk (0x01UL << GPIO_PORT_CLR1_CLRP030_Pos) /*!< GPIO_PORT CLR1: CLRP030 Mask */ -#define GPIO_PORT_CLR1_CLRP031_Pos 31 /*!< GPIO_PORT CLR1: CLRP031 Position */ -#define GPIO_PORT_CLR1_CLRP031_Msk (0x01UL << GPIO_PORT_CLR1_CLRP031_Pos) /*!< GPIO_PORT CLR1: CLRP031 Mask */ - -// ------------------------------------- GPIO_PORT_CLR2 ----------------------------------------- -#define GPIO_PORT_CLR2_CLRP00_Pos 0 /*!< GPIO_PORT CLR2: CLRP00 Position */ -#define GPIO_PORT_CLR2_CLRP00_Msk (0x01UL << GPIO_PORT_CLR2_CLRP00_Pos) /*!< GPIO_PORT CLR2: CLRP00 Mask */ -#define GPIO_PORT_CLR2_CLRP01_Pos 1 /*!< GPIO_PORT CLR2: CLRP01 Position */ -#define GPIO_PORT_CLR2_CLRP01_Msk (0x01UL << GPIO_PORT_CLR2_CLRP01_Pos) /*!< GPIO_PORT CLR2: CLRP01 Mask */ -#define GPIO_PORT_CLR2_CLRP02_Pos 2 /*!< GPIO_PORT CLR2: CLRP02 Position */ -#define GPIO_PORT_CLR2_CLRP02_Msk (0x01UL << GPIO_PORT_CLR2_CLRP02_Pos) /*!< GPIO_PORT CLR2: CLRP02 Mask */ -#define GPIO_PORT_CLR2_CLRP03_Pos 3 /*!< GPIO_PORT CLR2: CLRP03 Position */ -#define GPIO_PORT_CLR2_CLRP03_Msk (0x01UL << GPIO_PORT_CLR2_CLRP03_Pos) /*!< GPIO_PORT CLR2: CLRP03 Mask */ -#define GPIO_PORT_CLR2_CLRP04_Pos 4 /*!< GPIO_PORT CLR2: CLRP04 Position */ -#define GPIO_PORT_CLR2_CLRP04_Msk (0x01UL << GPIO_PORT_CLR2_CLRP04_Pos) /*!< GPIO_PORT CLR2: CLRP04 Mask */ -#define GPIO_PORT_CLR2_CLRP05_Pos 5 /*!< GPIO_PORT CLR2: CLRP05 Position */ -#define GPIO_PORT_CLR2_CLRP05_Msk (0x01UL << GPIO_PORT_CLR2_CLRP05_Pos) /*!< GPIO_PORT CLR2: CLRP05 Mask */ -#define GPIO_PORT_CLR2_CLRP06_Pos 6 /*!< GPIO_PORT CLR2: CLRP06 Position */ -#define GPIO_PORT_CLR2_CLRP06_Msk (0x01UL << GPIO_PORT_CLR2_CLRP06_Pos) /*!< GPIO_PORT CLR2: CLRP06 Mask */ -#define GPIO_PORT_CLR2_CLRP07_Pos 7 /*!< GPIO_PORT CLR2: CLRP07 Position */ -#define GPIO_PORT_CLR2_CLRP07_Msk (0x01UL << GPIO_PORT_CLR2_CLRP07_Pos) /*!< GPIO_PORT CLR2: CLRP07 Mask */ -#define GPIO_PORT_CLR2_CLRP08_Pos 8 /*!< GPIO_PORT CLR2: CLRP08 Position */ -#define GPIO_PORT_CLR2_CLRP08_Msk (0x01UL << GPIO_PORT_CLR2_CLRP08_Pos) /*!< GPIO_PORT CLR2: CLRP08 Mask */ -#define GPIO_PORT_CLR2_CLRP09_Pos 9 /*!< GPIO_PORT CLR2: CLRP09 Position */ -#define GPIO_PORT_CLR2_CLRP09_Msk (0x01UL << GPIO_PORT_CLR2_CLRP09_Pos) /*!< GPIO_PORT CLR2: CLRP09 Mask */ -#define GPIO_PORT_CLR2_CLRP010_Pos 10 /*!< GPIO_PORT CLR2: CLRP010 Position */ -#define GPIO_PORT_CLR2_CLRP010_Msk (0x01UL << GPIO_PORT_CLR2_CLRP010_Pos) /*!< GPIO_PORT CLR2: CLRP010 Mask */ -#define GPIO_PORT_CLR2_CLRP011_Pos 11 /*!< GPIO_PORT CLR2: CLRP011 Position */ -#define GPIO_PORT_CLR2_CLRP011_Msk (0x01UL << GPIO_PORT_CLR2_CLRP011_Pos) /*!< GPIO_PORT CLR2: CLRP011 Mask */ -#define GPIO_PORT_CLR2_CLRP012_Pos 12 /*!< GPIO_PORT CLR2: CLRP012 Position */ -#define GPIO_PORT_CLR2_CLRP012_Msk (0x01UL << GPIO_PORT_CLR2_CLRP012_Pos) /*!< GPIO_PORT CLR2: CLRP012 Mask */ -#define GPIO_PORT_CLR2_CLRP013_Pos 13 /*!< GPIO_PORT CLR2: CLRP013 Position */ -#define GPIO_PORT_CLR2_CLRP013_Msk (0x01UL << GPIO_PORT_CLR2_CLRP013_Pos) /*!< GPIO_PORT CLR2: CLRP013 Mask */ -#define GPIO_PORT_CLR2_CLRP014_Pos 14 /*!< GPIO_PORT CLR2: CLRP014 Position */ -#define GPIO_PORT_CLR2_CLRP014_Msk (0x01UL << GPIO_PORT_CLR2_CLRP014_Pos) /*!< GPIO_PORT CLR2: CLRP014 Mask */ -#define GPIO_PORT_CLR2_CLRP015_Pos 15 /*!< GPIO_PORT CLR2: CLRP015 Position */ -#define GPIO_PORT_CLR2_CLRP015_Msk (0x01UL << GPIO_PORT_CLR2_CLRP015_Pos) /*!< GPIO_PORT CLR2: CLRP015 Mask */ -#define GPIO_PORT_CLR2_CLRP016_Pos 16 /*!< GPIO_PORT CLR2: CLRP016 Position */ -#define GPIO_PORT_CLR2_CLRP016_Msk (0x01UL << GPIO_PORT_CLR2_CLRP016_Pos) /*!< GPIO_PORT CLR2: CLRP016 Mask */ -#define GPIO_PORT_CLR2_CLRP017_Pos 17 /*!< GPIO_PORT CLR2: CLRP017 Position */ -#define GPIO_PORT_CLR2_CLRP017_Msk (0x01UL << GPIO_PORT_CLR2_CLRP017_Pos) /*!< GPIO_PORT CLR2: CLRP017 Mask */ -#define GPIO_PORT_CLR2_CLRP018_Pos 18 /*!< GPIO_PORT CLR2: CLRP018 Position */ -#define GPIO_PORT_CLR2_CLRP018_Msk (0x01UL << GPIO_PORT_CLR2_CLRP018_Pos) /*!< GPIO_PORT CLR2: CLRP018 Mask */ -#define GPIO_PORT_CLR2_CLRP019_Pos 19 /*!< GPIO_PORT CLR2: CLRP019 Position */ -#define GPIO_PORT_CLR2_CLRP019_Msk (0x01UL << GPIO_PORT_CLR2_CLRP019_Pos) /*!< GPIO_PORT CLR2: CLRP019 Mask */ -#define GPIO_PORT_CLR2_CLRP020_Pos 20 /*!< GPIO_PORT CLR2: CLRP020 Position */ -#define GPIO_PORT_CLR2_CLRP020_Msk (0x01UL << GPIO_PORT_CLR2_CLRP020_Pos) /*!< GPIO_PORT CLR2: CLRP020 Mask */ -#define GPIO_PORT_CLR2_CLRP021_Pos 21 /*!< GPIO_PORT CLR2: CLRP021 Position */ -#define GPIO_PORT_CLR2_CLRP021_Msk (0x01UL << GPIO_PORT_CLR2_CLRP021_Pos) /*!< GPIO_PORT CLR2: CLRP021 Mask */ -#define GPIO_PORT_CLR2_CLRP022_Pos 22 /*!< GPIO_PORT CLR2: CLRP022 Position */ -#define GPIO_PORT_CLR2_CLRP022_Msk (0x01UL << GPIO_PORT_CLR2_CLRP022_Pos) /*!< GPIO_PORT CLR2: CLRP022 Mask */ -#define GPIO_PORT_CLR2_CLRP023_Pos 23 /*!< GPIO_PORT CLR2: CLRP023 Position */ -#define GPIO_PORT_CLR2_CLRP023_Msk (0x01UL << GPIO_PORT_CLR2_CLRP023_Pos) /*!< GPIO_PORT CLR2: CLRP023 Mask */ -#define GPIO_PORT_CLR2_CLRP024_Pos 24 /*!< GPIO_PORT CLR2: CLRP024 Position */ -#define GPIO_PORT_CLR2_CLRP024_Msk (0x01UL << GPIO_PORT_CLR2_CLRP024_Pos) /*!< GPIO_PORT CLR2: CLRP024 Mask */ -#define GPIO_PORT_CLR2_CLRP025_Pos 25 /*!< GPIO_PORT CLR2: CLRP025 Position */ -#define GPIO_PORT_CLR2_CLRP025_Msk (0x01UL << GPIO_PORT_CLR2_CLRP025_Pos) /*!< GPIO_PORT CLR2: CLRP025 Mask */ -#define GPIO_PORT_CLR2_CLRP026_Pos 26 /*!< GPIO_PORT CLR2: CLRP026 Position */ -#define GPIO_PORT_CLR2_CLRP026_Msk (0x01UL << GPIO_PORT_CLR2_CLRP026_Pos) /*!< GPIO_PORT CLR2: CLRP026 Mask */ -#define GPIO_PORT_CLR2_CLRP027_Pos 27 /*!< GPIO_PORT CLR2: CLRP027 Position */ -#define GPIO_PORT_CLR2_CLRP027_Msk (0x01UL << GPIO_PORT_CLR2_CLRP027_Pos) /*!< GPIO_PORT CLR2: CLRP027 Mask */ -#define GPIO_PORT_CLR2_CLRP028_Pos 28 /*!< GPIO_PORT CLR2: CLRP028 Position */ -#define GPIO_PORT_CLR2_CLRP028_Msk (0x01UL << GPIO_PORT_CLR2_CLRP028_Pos) /*!< GPIO_PORT CLR2: CLRP028 Mask */ -#define GPIO_PORT_CLR2_CLRP029_Pos 29 /*!< GPIO_PORT CLR2: CLRP029 Position */ -#define GPIO_PORT_CLR2_CLRP029_Msk (0x01UL << GPIO_PORT_CLR2_CLRP029_Pos) /*!< GPIO_PORT CLR2: CLRP029 Mask */ -#define GPIO_PORT_CLR2_CLRP030_Pos 30 /*!< GPIO_PORT CLR2: CLRP030 Position */ -#define GPIO_PORT_CLR2_CLRP030_Msk (0x01UL << GPIO_PORT_CLR2_CLRP030_Pos) /*!< GPIO_PORT CLR2: CLRP030 Mask */ -#define GPIO_PORT_CLR2_CLRP031_Pos 31 /*!< GPIO_PORT CLR2: CLRP031 Position */ -#define GPIO_PORT_CLR2_CLRP031_Msk (0x01UL << GPIO_PORT_CLR2_CLRP031_Pos) /*!< GPIO_PORT CLR2: CLRP031 Mask */ - -// ------------------------------------- GPIO_PORT_CLR3 ----------------------------------------- -#define GPIO_PORT_CLR3_CLRP00_Pos 0 /*!< GPIO_PORT CLR3: CLRP00 Position */ -#define GPIO_PORT_CLR3_CLRP00_Msk (0x01UL << GPIO_PORT_CLR3_CLRP00_Pos) /*!< GPIO_PORT CLR3: CLRP00 Mask */ -#define GPIO_PORT_CLR3_CLRP01_Pos 1 /*!< GPIO_PORT CLR3: CLRP01 Position */ -#define GPIO_PORT_CLR3_CLRP01_Msk (0x01UL << GPIO_PORT_CLR3_CLRP01_Pos) /*!< GPIO_PORT CLR3: CLRP01 Mask */ -#define GPIO_PORT_CLR3_CLRP02_Pos 2 /*!< GPIO_PORT CLR3: CLRP02 Position */ -#define GPIO_PORT_CLR3_CLRP02_Msk (0x01UL << GPIO_PORT_CLR3_CLRP02_Pos) /*!< GPIO_PORT CLR3: CLRP02 Mask */ -#define GPIO_PORT_CLR3_CLRP03_Pos 3 /*!< GPIO_PORT CLR3: CLRP03 Position */ -#define GPIO_PORT_CLR3_CLRP03_Msk (0x01UL << GPIO_PORT_CLR3_CLRP03_Pos) /*!< GPIO_PORT CLR3: CLRP03 Mask */ -#define GPIO_PORT_CLR3_CLRP04_Pos 4 /*!< GPIO_PORT CLR3: CLRP04 Position */ -#define GPIO_PORT_CLR3_CLRP04_Msk (0x01UL << GPIO_PORT_CLR3_CLRP04_Pos) /*!< GPIO_PORT CLR3: CLRP04 Mask */ -#define GPIO_PORT_CLR3_CLRP05_Pos 5 /*!< GPIO_PORT CLR3: CLRP05 Position */ -#define GPIO_PORT_CLR3_CLRP05_Msk (0x01UL << GPIO_PORT_CLR3_CLRP05_Pos) /*!< GPIO_PORT CLR3: CLRP05 Mask */ -#define GPIO_PORT_CLR3_CLRP06_Pos 6 /*!< GPIO_PORT CLR3: CLRP06 Position */ -#define GPIO_PORT_CLR3_CLRP06_Msk (0x01UL << GPIO_PORT_CLR3_CLRP06_Pos) /*!< GPIO_PORT CLR3: CLRP06 Mask */ -#define GPIO_PORT_CLR3_CLRP07_Pos 7 /*!< GPIO_PORT CLR3: CLRP07 Position */ -#define GPIO_PORT_CLR3_CLRP07_Msk (0x01UL << GPIO_PORT_CLR3_CLRP07_Pos) /*!< GPIO_PORT CLR3: CLRP07 Mask */ -#define GPIO_PORT_CLR3_CLRP08_Pos 8 /*!< GPIO_PORT CLR3: CLRP08 Position */ -#define GPIO_PORT_CLR3_CLRP08_Msk (0x01UL << GPIO_PORT_CLR3_CLRP08_Pos) /*!< GPIO_PORT CLR3: CLRP08 Mask */ -#define GPIO_PORT_CLR3_CLRP09_Pos 9 /*!< GPIO_PORT CLR3: CLRP09 Position */ -#define GPIO_PORT_CLR3_CLRP09_Msk (0x01UL << GPIO_PORT_CLR3_CLRP09_Pos) /*!< GPIO_PORT CLR3: CLRP09 Mask */ -#define GPIO_PORT_CLR3_CLRP010_Pos 10 /*!< GPIO_PORT CLR3: CLRP010 Position */ -#define GPIO_PORT_CLR3_CLRP010_Msk (0x01UL << GPIO_PORT_CLR3_CLRP010_Pos) /*!< GPIO_PORT CLR3: CLRP010 Mask */ -#define GPIO_PORT_CLR3_CLRP011_Pos 11 /*!< GPIO_PORT CLR3: CLRP011 Position */ -#define GPIO_PORT_CLR3_CLRP011_Msk (0x01UL << GPIO_PORT_CLR3_CLRP011_Pos) /*!< GPIO_PORT CLR3: CLRP011 Mask */ -#define GPIO_PORT_CLR3_CLRP012_Pos 12 /*!< GPIO_PORT CLR3: CLRP012 Position */ -#define GPIO_PORT_CLR3_CLRP012_Msk (0x01UL << GPIO_PORT_CLR3_CLRP012_Pos) /*!< GPIO_PORT CLR3: CLRP012 Mask */ -#define GPIO_PORT_CLR3_CLRP013_Pos 13 /*!< GPIO_PORT CLR3: CLRP013 Position */ -#define GPIO_PORT_CLR3_CLRP013_Msk (0x01UL << GPIO_PORT_CLR3_CLRP013_Pos) /*!< GPIO_PORT CLR3: CLRP013 Mask */ -#define GPIO_PORT_CLR3_CLRP014_Pos 14 /*!< GPIO_PORT CLR3: CLRP014 Position */ -#define GPIO_PORT_CLR3_CLRP014_Msk (0x01UL << GPIO_PORT_CLR3_CLRP014_Pos) /*!< GPIO_PORT CLR3: CLRP014 Mask */ -#define GPIO_PORT_CLR3_CLRP015_Pos 15 /*!< GPIO_PORT CLR3: CLRP015 Position */ -#define GPIO_PORT_CLR3_CLRP015_Msk (0x01UL << GPIO_PORT_CLR3_CLRP015_Pos) /*!< GPIO_PORT CLR3: CLRP015 Mask */ -#define GPIO_PORT_CLR3_CLRP016_Pos 16 /*!< GPIO_PORT CLR3: CLRP016 Position */ -#define GPIO_PORT_CLR3_CLRP016_Msk (0x01UL << GPIO_PORT_CLR3_CLRP016_Pos) /*!< GPIO_PORT CLR3: CLRP016 Mask */ -#define GPIO_PORT_CLR3_CLRP017_Pos 17 /*!< GPIO_PORT CLR3: CLRP017 Position */ -#define GPIO_PORT_CLR3_CLRP017_Msk (0x01UL << GPIO_PORT_CLR3_CLRP017_Pos) /*!< GPIO_PORT CLR3: CLRP017 Mask */ -#define GPIO_PORT_CLR3_CLRP018_Pos 18 /*!< GPIO_PORT CLR3: CLRP018 Position */ -#define GPIO_PORT_CLR3_CLRP018_Msk (0x01UL << GPIO_PORT_CLR3_CLRP018_Pos) /*!< GPIO_PORT CLR3: CLRP018 Mask */ -#define GPIO_PORT_CLR3_CLRP019_Pos 19 /*!< GPIO_PORT CLR3: CLRP019 Position */ -#define GPIO_PORT_CLR3_CLRP019_Msk (0x01UL << GPIO_PORT_CLR3_CLRP019_Pos) /*!< GPIO_PORT CLR3: CLRP019 Mask */ -#define GPIO_PORT_CLR3_CLRP020_Pos 20 /*!< GPIO_PORT CLR3: CLRP020 Position */ -#define GPIO_PORT_CLR3_CLRP020_Msk (0x01UL << GPIO_PORT_CLR3_CLRP020_Pos) /*!< GPIO_PORT CLR3: CLRP020 Mask */ -#define GPIO_PORT_CLR3_CLRP021_Pos 21 /*!< GPIO_PORT CLR3: CLRP021 Position */ -#define GPIO_PORT_CLR3_CLRP021_Msk (0x01UL << GPIO_PORT_CLR3_CLRP021_Pos) /*!< GPIO_PORT CLR3: CLRP021 Mask */ -#define GPIO_PORT_CLR3_CLRP022_Pos 22 /*!< GPIO_PORT CLR3: CLRP022 Position */ -#define GPIO_PORT_CLR3_CLRP022_Msk (0x01UL << GPIO_PORT_CLR3_CLRP022_Pos) /*!< GPIO_PORT CLR3: CLRP022 Mask */ -#define GPIO_PORT_CLR3_CLRP023_Pos 23 /*!< GPIO_PORT CLR3: CLRP023 Position */ -#define GPIO_PORT_CLR3_CLRP023_Msk (0x01UL << GPIO_PORT_CLR3_CLRP023_Pos) /*!< GPIO_PORT CLR3: CLRP023 Mask */ -#define GPIO_PORT_CLR3_CLRP024_Pos 24 /*!< GPIO_PORT CLR3: CLRP024 Position */ -#define GPIO_PORT_CLR3_CLRP024_Msk (0x01UL << GPIO_PORT_CLR3_CLRP024_Pos) /*!< GPIO_PORT CLR3: CLRP024 Mask */ -#define GPIO_PORT_CLR3_CLRP025_Pos 25 /*!< GPIO_PORT CLR3: CLRP025 Position */ -#define GPIO_PORT_CLR3_CLRP025_Msk (0x01UL << GPIO_PORT_CLR3_CLRP025_Pos) /*!< GPIO_PORT CLR3: CLRP025 Mask */ -#define GPIO_PORT_CLR3_CLRP026_Pos 26 /*!< GPIO_PORT CLR3: CLRP026 Position */ -#define GPIO_PORT_CLR3_CLRP026_Msk (0x01UL << GPIO_PORT_CLR3_CLRP026_Pos) /*!< GPIO_PORT CLR3: CLRP026 Mask */ -#define GPIO_PORT_CLR3_CLRP027_Pos 27 /*!< GPIO_PORT CLR3: CLRP027 Position */ -#define GPIO_PORT_CLR3_CLRP027_Msk (0x01UL << GPIO_PORT_CLR3_CLRP027_Pos) /*!< GPIO_PORT CLR3: CLRP027 Mask */ -#define GPIO_PORT_CLR3_CLRP028_Pos 28 /*!< GPIO_PORT CLR3: CLRP028 Position */ -#define GPIO_PORT_CLR3_CLRP028_Msk (0x01UL << GPIO_PORT_CLR3_CLRP028_Pos) /*!< GPIO_PORT CLR3: CLRP028 Mask */ -#define GPIO_PORT_CLR3_CLRP029_Pos 29 /*!< GPIO_PORT CLR3: CLRP029 Position */ -#define GPIO_PORT_CLR3_CLRP029_Msk (0x01UL << GPIO_PORT_CLR3_CLRP029_Pos) /*!< GPIO_PORT CLR3: CLRP029 Mask */ -#define GPIO_PORT_CLR3_CLRP030_Pos 30 /*!< GPIO_PORT CLR3: CLRP030 Position */ -#define GPIO_PORT_CLR3_CLRP030_Msk (0x01UL << GPIO_PORT_CLR3_CLRP030_Pos) /*!< GPIO_PORT CLR3: CLRP030 Mask */ -#define GPIO_PORT_CLR3_CLRP031_Pos 31 /*!< GPIO_PORT CLR3: CLRP031 Position */ -#define GPIO_PORT_CLR3_CLRP031_Msk (0x01UL << GPIO_PORT_CLR3_CLRP031_Pos) /*!< GPIO_PORT CLR3: CLRP031 Mask */ - -// ------------------------------------- GPIO_PORT_CLR4 ----------------------------------------- -#define GPIO_PORT_CLR4_CLRP00_Pos 0 /*!< GPIO_PORT CLR4: CLRP00 Position */ -#define GPIO_PORT_CLR4_CLRP00_Msk (0x01UL << GPIO_PORT_CLR4_CLRP00_Pos) /*!< GPIO_PORT CLR4: CLRP00 Mask */ -#define GPIO_PORT_CLR4_CLRP01_Pos 1 /*!< GPIO_PORT CLR4: CLRP01 Position */ -#define GPIO_PORT_CLR4_CLRP01_Msk (0x01UL << GPIO_PORT_CLR4_CLRP01_Pos) /*!< GPIO_PORT CLR4: CLRP01 Mask */ -#define GPIO_PORT_CLR4_CLRP02_Pos 2 /*!< GPIO_PORT CLR4: CLRP02 Position */ -#define GPIO_PORT_CLR4_CLRP02_Msk (0x01UL << GPIO_PORT_CLR4_CLRP02_Pos) /*!< GPIO_PORT CLR4: CLRP02 Mask */ -#define GPIO_PORT_CLR4_CLRP03_Pos 3 /*!< GPIO_PORT CLR4: CLRP03 Position */ -#define GPIO_PORT_CLR4_CLRP03_Msk (0x01UL << GPIO_PORT_CLR4_CLRP03_Pos) /*!< GPIO_PORT CLR4: CLRP03 Mask */ -#define GPIO_PORT_CLR4_CLRP04_Pos 4 /*!< GPIO_PORT CLR4: CLRP04 Position */ -#define GPIO_PORT_CLR4_CLRP04_Msk (0x01UL << GPIO_PORT_CLR4_CLRP04_Pos) /*!< GPIO_PORT CLR4: CLRP04 Mask */ -#define GPIO_PORT_CLR4_CLRP05_Pos 5 /*!< GPIO_PORT CLR4: CLRP05 Position */ -#define GPIO_PORT_CLR4_CLRP05_Msk (0x01UL << GPIO_PORT_CLR4_CLRP05_Pos) /*!< GPIO_PORT CLR4: CLRP05 Mask */ -#define GPIO_PORT_CLR4_CLRP06_Pos 6 /*!< GPIO_PORT CLR4: CLRP06 Position */ -#define GPIO_PORT_CLR4_CLRP06_Msk (0x01UL << GPIO_PORT_CLR4_CLRP06_Pos) /*!< GPIO_PORT CLR4: CLRP06 Mask */ -#define GPIO_PORT_CLR4_CLRP07_Pos 7 /*!< GPIO_PORT CLR4: CLRP07 Position */ -#define GPIO_PORT_CLR4_CLRP07_Msk (0x01UL << GPIO_PORT_CLR4_CLRP07_Pos) /*!< GPIO_PORT CLR4: CLRP07 Mask */ -#define GPIO_PORT_CLR4_CLRP08_Pos 8 /*!< GPIO_PORT CLR4: CLRP08 Position */ -#define GPIO_PORT_CLR4_CLRP08_Msk (0x01UL << GPIO_PORT_CLR4_CLRP08_Pos) /*!< GPIO_PORT CLR4: CLRP08 Mask */ -#define GPIO_PORT_CLR4_CLRP09_Pos 9 /*!< GPIO_PORT CLR4: CLRP09 Position */ -#define GPIO_PORT_CLR4_CLRP09_Msk (0x01UL << GPIO_PORT_CLR4_CLRP09_Pos) /*!< GPIO_PORT CLR4: CLRP09 Mask */ -#define GPIO_PORT_CLR4_CLRP010_Pos 10 /*!< GPIO_PORT CLR4: CLRP010 Position */ -#define GPIO_PORT_CLR4_CLRP010_Msk (0x01UL << GPIO_PORT_CLR4_CLRP010_Pos) /*!< GPIO_PORT CLR4: CLRP010 Mask */ -#define GPIO_PORT_CLR4_CLRP011_Pos 11 /*!< GPIO_PORT CLR4: CLRP011 Position */ -#define GPIO_PORT_CLR4_CLRP011_Msk (0x01UL << GPIO_PORT_CLR4_CLRP011_Pos) /*!< GPIO_PORT CLR4: CLRP011 Mask */ -#define GPIO_PORT_CLR4_CLRP012_Pos 12 /*!< GPIO_PORT CLR4: CLRP012 Position */ -#define GPIO_PORT_CLR4_CLRP012_Msk (0x01UL << GPIO_PORT_CLR4_CLRP012_Pos) /*!< GPIO_PORT CLR4: CLRP012 Mask */ -#define GPIO_PORT_CLR4_CLRP013_Pos 13 /*!< GPIO_PORT CLR4: CLRP013 Position */ -#define GPIO_PORT_CLR4_CLRP013_Msk (0x01UL << GPIO_PORT_CLR4_CLRP013_Pos) /*!< GPIO_PORT CLR4: CLRP013 Mask */ -#define GPIO_PORT_CLR4_CLRP014_Pos 14 /*!< GPIO_PORT CLR4: CLRP014 Position */ -#define GPIO_PORT_CLR4_CLRP014_Msk (0x01UL << GPIO_PORT_CLR4_CLRP014_Pos) /*!< GPIO_PORT CLR4: CLRP014 Mask */ -#define GPIO_PORT_CLR4_CLRP015_Pos 15 /*!< GPIO_PORT CLR4: CLRP015 Position */ -#define GPIO_PORT_CLR4_CLRP015_Msk (0x01UL << GPIO_PORT_CLR4_CLRP015_Pos) /*!< GPIO_PORT CLR4: CLRP015 Mask */ -#define GPIO_PORT_CLR4_CLRP016_Pos 16 /*!< GPIO_PORT CLR4: CLRP016 Position */ -#define GPIO_PORT_CLR4_CLRP016_Msk (0x01UL << GPIO_PORT_CLR4_CLRP016_Pos) /*!< GPIO_PORT CLR4: CLRP016 Mask */ -#define GPIO_PORT_CLR4_CLRP017_Pos 17 /*!< GPIO_PORT CLR4: CLRP017 Position */ -#define GPIO_PORT_CLR4_CLRP017_Msk (0x01UL << GPIO_PORT_CLR4_CLRP017_Pos) /*!< GPIO_PORT CLR4: CLRP017 Mask */ -#define GPIO_PORT_CLR4_CLRP018_Pos 18 /*!< GPIO_PORT CLR4: CLRP018 Position */ -#define GPIO_PORT_CLR4_CLRP018_Msk (0x01UL << GPIO_PORT_CLR4_CLRP018_Pos) /*!< GPIO_PORT CLR4: CLRP018 Mask */ -#define GPIO_PORT_CLR4_CLRP019_Pos 19 /*!< GPIO_PORT CLR4: CLRP019 Position */ -#define GPIO_PORT_CLR4_CLRP019_Msk (0x01UL << GPIO_PORT_CLR4_CLRP019_Pos) /*!< GPIO_PORT CLR4: CLRP019 Mask */ -#define GPIO_PORT_CLR4_CLRP020_Pos 20 /*!< GPIO_PORT CLR4: CLRP020 Position */ -#define GPIO_PORT_CLR4_CLRP020_Msk (0x01UL << GPIO_PORT_CLR4_CLRP020_Pos) /*!< GPIO_PORT CLR4: CLRP020 Mask */ -#define GPIO_PORT_CLR4_CLRP021_Pos 21 /*!< GPIO_PORT CLR4: CLRP021 Position */ -#define GPIO_PORT_CLR4_CLRP021_Msk (0x01UL << GPIO_PORT_CLR4_CLRP021_Pos) /*!< GPIO_PORT CLR4: CLRP021 Mask */ -#define GPIO_PORT_CLR4_CLRP022_Pos 22 /*!< GPIO_PORT CLR4: CLRP022 Position */ -#define GPIO_PORT_CLR4_CLRP022_Msk (0x01UL << GPIO_PORT_CLR4_CLRP022_Pos) /*!< GPIO_PORT CLR4: CLRP022 Mask */ -#define GPIO_PORT_CLR4_CLRP023_Pos 23 /*!< GPIO_PORT CLR4: CLRP023 Position */ -#define GPIO_PORT_CLR4_CLRP023_Msk (0x01UL << GPIO_PORT_CLR4_CLRP023_Pos) /*!< GPIO_PORT CLR4: CLRP023 Mask */ -#define GPIO_PORT_CLR4_CLRP024_Pos 24 /*!< GPIO_PORT CLR4: CLRP024 Position */ -#define GPIO_PORT_CLR4_CLRP024_Msk (0x01UL << GPIO_PORT_CLR4_CLRP024_Pos) /*!< GPIO_PORT CLR4: CLRP024 Mask */ -#define GPIO_PORT_CLR4_CLRP025_Pos 25 /*!< GPIO_PORT CLR4: CLRP025 Position */ -#define GPIO_PORT_CLR4_CLRP025_Msk (0x01UL << GPIO_PORT_CLR4_CLRP025_Pos) /*!< GPIO_PORT CLR4: CLRP025 Mask */ -#define GPIO_PORT_CLR4_CLRP026_Pos 26 /*!< GPIO_PORT CLR4: CLRP026 Position */ -#define GPIO_PORT_CLR4_CLRP026_Msk (0x01UL << GPIO_PORT_CLR4_CLRP026_Pos) /*!< GPIO_PORT CLR4: CLRP026 Mask */ -#define GPIO_PORT_CLR4_CLRP027_Pos 27 /*!< GPIO_PORT CLR4: CLRP027 Position */ -#define GPIO_PORT_CLR4_CLRP027_Msk (0x01UL << GPIO_PORT_CLR4_CLRP027_Pos) /*!< GPIO_PORT CLR4: CLRP027 Mask */ -#define GPIO_PORT_CLR4_CLRP028_Pos 28 /*!< GPIO_PORT CLR4: CLRP028 Position */ -#define GPIO_PORT_CLR4_CLRP028_Msk (0x01UL << GPIO_PORT_CLR4_CLRP028_Pos) /*!< GPIO_PORT CLR4: CLRP028 Mask */ -#define GPIO_PORT_CLR4_CLRP029_Pos 29 /*!< GPIO_PORT CLR4: CLRP029 Position */ -#define GPIO_PORT_CLR4_CLRP029_Msk (0x01UL << GPIO_PORT_CLR4_CLRP029_Pos) /*!< GPIO_PORT CLR4: CLRP029 Mask */ -#define GPIO_PORT_CLR4_CLRP030_Pos 30 /*!< GPIO_PORT CLR4: CLRP030 Position */ -#define GPIO_PORT_CLR4_CLRP030_Msk (0x01UL << GPIO_PORT_CLR4_CLRP030_Pos) /*!< GPIO_PORT CLR4: CLRP030 Mask */ -#define GPIO_PORT_CLR4_CLRP031_Pos 31 /*!< GPIO_PORT CLR4: CLRP031 Position */ -#define GPIO_PORT_CLR4_CLRP031_Msk (0x01UL << GPIO_PORT_CLR4_CLRP031_Pos) /*!< GPIO_PORT CLR4: CLRP031 Mask */ - -// ------------------------------------- GPIO_PORT_CLR5 ----------------------------------------- -#define GPIO_PORT_CLR5_CLRP00_Pos 0 /*!< GPIO_PORT CLR5: CLRP00 Position */ -#define GPIO_PORT_CLR5_CLRP00_Msk (0x01UL << GPIO_PORT_CLR5_CLRP00_Pos) /*!< GPIO_PORT CLR5: CLRP00 Mask */ -#define GPIO_PORT_CLR5_CLRP01_Pos 1 /*!< GPIO_PORT CLR5: CLRP01 Position */ -#define GPIO_PORT_CLR5_CLRP01_Msk (0x01UL << GPIO_PORT_CLR5_CLRP01_Pos) /*!< GPIO_PORT CLR5: CLRP01 Mask */ -#define GPIO_PORT_CLR5_CLRP02_Pos 2 /*!< GPIO_PORT CLR5: CLRP02 Position */ -#define GPIO_PORT_CLR5_CLRP02_Msk (0x01UL << GPIO_PORT_CLR5_CLRP02_Pos) /*!< GPIO_PORT CLR5: CLRP02 Mask */ -#define GPIO_PORT_CLR5_CLRP03_Pos 3 /*!< GPIO_PORT CLR5: CLRP03 Position */ -#define GPIO_PORT_CLR5_CLRP03_Msk (0x01UL << GPIO_PORT_CLR5_CLRP03_Pos) /*!< GPIO_PORT CLR5: CLRP03 Mask */ -#define GPIO_PORT_CLR5_CLRP04_Pos 4 /*!< GPIO_PORT CLR5: CLRP04 Position */ -#define GPIO_PORT_CLR5_CLRP04_Msk (0x01UL << GPIO_PORT_CLR5_CLRP04_Pos) /*!< GPIO_PORT CLR5: CLRP04 Mask */ -#define GPIO_PORT_CLR5_CLRP05_Pos 5 /*!< GPIO_PORT CLR5: CLRP05 Position */ -#define GPIO_PORT_CLR5_CLRP05_Msk (0x01UL << GPIO_PORT_CLR5_CLRP05_Pos) /*!< GPIO_PORT CLR5: CLRP05 Mask */ -#define GPIO_PORT_CLR5_CLRP06_Pos 6 /*!< GPIO_PORT CLR5: CLRP06 Position */ -#define GPIO_PORT_CLR5_CLRP06_Msk (0x01UL << GPIO_PORT_CLR5_CLRP06_Pos) /*!< GPIO_PORT CLR5: CLRP06 Mask */ -#define GPIO_PORT_CLR5_CLRP07_Pos 7 /*!< GPIO_PORT CLR5: CLRP07 Position */ -#define GPIO_PORT_CLR5_CLRP07_Msk (0x01UL << GPIO_PORT_CLR5_CLRP07_Pos) /*!< GPIO_PORT CLR5: CLRP07 Mask */ -#define GPIO_PORT_CLR5_CLRP08_Pos 8 /*!< GPIO_PORT CLR5: CLRP08 Position */ -#define GPIO_PORT_CLR5_CLRP08_Msk (0x01UL << GPIO_PORT_CLR5_CLRP08_Pos) /*!< GPIO_PORT CLR5: CLRP08 Mask */ -#define GPIO_PORT_CLR5_CLRP09_Pos 9 /*!< GPIO_PORT CLR5: CLRP09 Position */ -#define GPIO_PORT_CLR5_CLRP09_Msk (0x01UL << GPIO_PORT_CLR5_CLRP09_Pos) /*!< GPIO_PORT CLR5: CLRP09 Mask */ -#define GPIO_PORT_CLR5_CLRP010_Pos 10 /*!< GPIO_PORT CLR5: CLRP010 Position */ -#define GPIO_PORT_CLR5_CLRP010_Msk (0x01UL << GPIO_PORT_CLR5_CLRP010_Pos) /*!< GPIO_PORT CLR5: CLRP010 Mask */ -#define GPIO_PORT_CLR5_CLRP011_Pos 11 /*!< GPIO_PORT CLR5: CLRP011 Position */ -#define GPIO_PORT_CLR5_CLRP011_Msk (0x01UL << GPIO_PORT_CLR5_CLRP011_Pos) /*!< GPIO_PORT CLR5: CLRP011 Mask */ -#define GPIO_PORT_CLR5_CLRP012_Pos 12 /*!< GPIO_PORT CLR5: CLRP012 Position */ -#define GPIO_PORT_CLR5_CLRP012_Msk (0x01UL << GPIO_PORT_CLR5_CLRP012_Pos) /*!< GPIO_PORT CLR5: CLRP012 Mask */ -#define GPIO_PORT_CLR5_CLRP013_Pos 13 /*!< GPIO_PORT CLR5: CLRP013 Position */ -#define GPIO_PORT_CLR5_CLRP013_Msk (0x01UL << GPIO_PORT_CLR5_CLRP013_Pos) /*!< GPIO_PORT CLR5: CLRP013 Mask */ -#define GPIO_PORT_CLR5_CLRP014_Pos 14 /*!< GPIO_PORT CLR5: CLRP014 Position */ -#define GPIO_PORT_CLR5_CLRP014_Msk (0x01UL << GPIO_PORT_CLR5_CLRP014_Pos) /*!< GPIO_PORT CLR5: CLRP014 Mask */ -#define GPIO_PORT_CLR5_CLRP015_Pos 15 /*!< GPIO_PORT CLR5: CLRP015 Position */ -#define GPIO_PORT_CLR5_CLRP015_Msk (0x01UL << GPIO_PORT_CLR5_CLRP015_Pos) /*!< GPIO_PORT CLR5: CLRP015 Mask */ -#define GPIO_PORT_CLR5_CLRP016_Pos 16 /*!< GPIO_PORT CLR5: CLRP016 Position */ -#define GPIO_PORT_CLR5_CLRP016_Msk (0x01UL << GPIO_PORT_CLR5_CLRP016_Pos) /*!< GPIO_PORT CLR5: CLRP016 Mask */ -#define GPIO_PORT_CLR5_CLRP017_Pos 17 /*!< GPIO_PORT CLR5: CLRP017 Position */ -#define GPIO_PORT_CLR5_CLRP017_Msk (0x01UL << GPIO_PORT_CLR5_CLRP017_Pos) /*!< GPIO_PORT CLR5: CLRP017 Mask */ -#define GPIO_PORT_CLR5_CLRP018_Pos 18 /*!< GPIO_PORT CLR5: CLRP018 Position */ -#define GPIO_PORT_CLR5_CLRP018_Msk (0x01UL << GPIO_PORT_CLR5_CLRP018_Pos) /*!< GPIO_PORT CLR5: CLRP018 Mask */ -#define GPIO_PORT_CLR5_CLRP019_Pos 19 /*!< GPIO_PORT CLR5: CLRP019 Position */ -#define GPIO_PORT_CLR5_CLRP019_Msk (0x01UL << GPIO_PORT_CLR5_CLRP019_Pos) /*!< GPIO_PORT CLR5: CLRP019 Mask */ -#define GPIO_PORT_CLR5_CLRP020_Pos 20 /*!< GPIO_PORT CLR5: CLRP020 Position */ -#define GPIO_PORT_CLR5_CLRP020_Msk (0x01UL << GPIO_PORT_CLR5_CLRP020_Pos) /*!< GPIO_PORT CLR5: CLRP020 Mask */ -#define GPIO_PORT_CLR5_CLRP021_Pos 21 /*!< GPIO_PORT CLR5: CLRP021 Position */ -#define GPIO_PORT_CLR5_CLRP021_Msk (0x01UL << GPIO_PORT_CLR5_CLRP021_Pos) /*!< GPIO_PORT CLR5: CLRP021 Mask */ -#define GPIO_PORT_CLR5_CLRP022_Pos 22 /*!< GPIO_PORT CLR5: CLRP022 Position */ -#define GPIO_PORT_CLR5_CLRP022_Msk (0x01UL << GPIO_PORT_CLR5_CLRP022_Pos) /*!< GPIO_PORT CLR5: CLRP022 Mask */ -#define GPIO_PORT_CLR5_CLRP023_Pos 23 /*!< GPIO_PORT CLR5: CLRP023 Position */ -#define GPIO_PORT_CLR5_CLRP023_Msk (0x01UL << GPIO_PORT_CLR5_CLRP023_Pos) /*!< GPIO_PORT CLR5: CLRP023 Mask */ -#define GPIO_PORT_CLR5_CLRP024_Pos 24 /*!< GPIO_PORT CLR5: CLRP024 Position */ -#define GPIO_PORT_CLR5_CLRP024_Msk (0x01UL << GPIO_PORT_CLR5_CLRP024_Pos) /*!< GPIO_PORT CLR5: CLRP024 Mask */ -#define GPIO_PORT_CLR5_CLRP025_Pos 25 /*!< GPIO_PORT CLR5: CLRP025 Position */ -#define GPIO_PORT_CLR5_CLRP025_Msk (0x01UL << GPIO_PORT_CLR5_CLRP025_Pos) /*!< GPIO_PORT CLR5: CLRP025 Mask */ -#define GPIO_PORT_CLR5_CLRP026_Pos 26 /*!< GPIO_PORT CLR5: CLRP026 Position */ -#define GPIO_PORT_CLR5_CLRP026_Msk (0x01UL << GPIO_PORT_CLR5_CLRP026_Pos) /*!< GPIO_PORT CLR5: CLRP026 Mask */ -#define GPIO_PORT_CLR5_CLRP027_Pos 27 /*!< GPIO_PORT CLR5: CLRP027 Position */ -#define GPIO_PORT_CLR5_CLRP027_Msk (0x01UL << GPIO_PORT_CLR5_CLRP027_Pos) /*!< GPIO_PORT CLR5: CLRP027 Mask */ -#define GPIO_PORT_CLR5_CLRP028_Pos 28 /*!< GPIO_PORT CLR5: CLRP028 Position */ -#define GPIO_PORT_CLR5_CLRP028_Msk (0x01UL << GPIO_PORT_CLR5_CLRP028_Pos) /*!< GPIO_PORT CLR5: CLRP028 Mask */ -#define GPIO_PORT_CLR5_CLRP029_Pos 29 /*!< GPIO_PORT CLR5: CLRP029 Position */ -#define GPIO_PORT_CLR5_CLRP029_Msk (0x01UL << GPIO_PORT_CLR5_CLRP029_Pos) /*!< GPIO_PORT CLR5: CLRP029 Mask */ -#define GPIO_PORT_CLR5_CLRP030_Pos 30 /*!< GPIO_PORT CLR5: CLRP030 Position */ -#define GPIO_PORT_CLR5_CLRP030_Msk (0x01UL << GPIO_PORT_CLR5_CLRP030_Pos) /*!< GPIO_PORT CLR5: CLRP030 Mask */ -#define GPIO_PORT_CLR5_CLRP031_Pos 31 /*!< GPIO_PORT CLR5: CLRP031 Position */ -#define GPIO_PORT_CLR5_CLRP031_Msk (0x01UL << GPIO_PORT_CLR5_CLRP031_Pos) /*!< GPIO_PORT CLR5: CLRP031 Mask */ - -// ------------------------------------- GPIO_PORT_CLR6 ----------------------------------------- -#define GPIO_PORT_CLR6_CLRP00_Pos 0 /*!< GPIO_PORT CLR6: CLRP00 Position */ -#define GPIO_PORT_CLR6_CLRP00_Msk (0x01UL << GPIO_PORT_CLR6_CLRP00_Pos) /*!< GPIO_PORT CLR6: CLRP00 Mask */ -#define GPIO_PORT_CLR6_CLRP01_Pos 1 /*!< GPIO_PORT CLR6: CLRP01 Position */ -#define GPIO_PORT_CLR6_CLRP01_Msk (0x01UL << GPIO_PORT_CLR6_CLRP01_Pos) /*!< GPIO_PORT CLR6: CLRP01 Mask */ -#define GPIO_PORT_CLR6_CLRP02_Pos 2 /*!< GPIO_PORT CLR6: CLRP02 Position */ -#define GPIO_PORT_CLR6_CLRP02_Msk (0x01UL << GPIO_PORT_CLR6_CLRP02_Pos) /*!< GPIO_PORT CLR6: CLRP02 Mask */ -#define GPIO_PORT_CLR6_CLRP03_Pos 3 /*!< GPIO_PORT CLR6: CLRP03 Position */ -#define GPIO_PORT_CLR6_CLRP03_Msk (0x01UL << GPIO_PORT_CLR6_CLRP03_Pos) /*!< GPIO_PORT CLR6: CLRP03 Mask */ -#define GPIO_PORT_CLR6_CLRP04_Pos 4 /*!< GPIO_PORT CLR6: CLRP04 Position */ -#define GPIO_PORT_CLR6_CLRP04_Msk (0x01UL << GPIO_PORT_CLR6_CLRP04_Pos) /*!< GPIO_PORT CLR6: CLRP04 Mask */ -#define GPIO_PORT_CLR6_CLRP05_Pos 5 /*!< GPIO_PORT CLR6: CLRP05 Position */ -#define GPIO_PORT_CLR6_CLRP05_Msk (0x01UL << GPIO_PORT_CLR6_CLRP05_Pos) /*!< GPIO_PORT CLR6: CLRP05 Mask */ -#define GPIO_PORT_CLR6_CLRP06_Pos 6 /*!< GPIO_PORT CLR6: CLRP06 Position */ -#define GPIO_PORT_CLR6_CLRP06_Msk (0x01UL << GPIO_PORT_CLR6_CLRP06_Pos) /*!< GPIO_PORT CLR6: CLRP06 Mask */ -#define GPIO_PORT_CLR6_CLRP07_Pos 7 /*!< GPIO_PORT CLR6: CLRP07 Position */ -#define GPIO_PORT_CLR6_CLRP07_Msk (0x01UL << GPIO_PORT_CLR6_CLRP07_Pos) /*!< GPIO_PORT CLR6: CLRP07 Mask */ -#define GPIO_PORT_CLR6_CLRP08_Pos 8 /*!< GPIO_PORT CLR6: CLRP08 Position */ -#define GPIO_PORT_CLR6_CLRP08_Msk (0x01UL << GPIO_PORT_CLR6_CLRP08_Pos) /*!< GPIO_PORT CLR6: CLRP08 Mask */ -#define GPIO_PORT_CLR6_CLRP09_Pos 9 /*!< GPIO_PORT CLR6: CLRP09 Position */ -#define GPIO_PORT_CLR6_CLRP09_Msk (0x01UL << GPIO_PORT_CLR6_CLRP09_Pos) /*!< GPIO_PORT CLR6: CLRP09 Mask */ -#define GPIO_PORT_CLR6_CLRP010_Pos 10 /*!< GPIO_PORT CLR6: CLRP010 Position */ -#define GPIO_PORT_CLR6_CLRP010_Msk (0x01UL << GPIO_PORT_CLR6_CLRP010_Pos) /*!< GPIO_PORT CLR6: CLRP010 Mask */ -#define GPIO_PORT_CLR6_CLRP011_Pos 11 /*!< GPIO_PORT CLR6: CLRP011 Position */ -#define GPIO_PORT_CLR6_CLRP011_Msk (0x01UL << GPIO_PORT_CLR6_CLRP011_Pos) /*!< GPIO_PORT CLR6: CLRP011 Mask */ -#define GPIO_PORT_CLR6_CLRP012_Pos 12 /*!< GPIO_PORT CLR6: CLRP012 Position */ -#define GPIO_PORT_CLR6_CLRP012_Msk (0x01UL << GPIO_PORT_CLR6_CLRP012_Pos) /*!< GPIO_PORT CLR6: CLRP012 Mask */ -#define GPIO_PORT_CLR6_CLRP013_Pos 13 /*!< GPIO_PORT CLR6: CLRP013 Position */ -#define GPIO_PORT_CLR6_CLRP013_Msk (0x01UL << GPIO_PORT_CLR6_CLRP013_Pos) /*!< GPIO_PORT CLR6: CLRP013 Mask */ -#define GPIO_PORT_CLR6_CLRP014_Pos 14 /*!< GPIO_PORT CLR6: CLRP014 Position */ -#define GPIO_PORT_CLR6_CLRP014_Msk (0x01UL << GPIO_PORT_CLR6_CLRP014_Pos) /*!< GPIO_PORT CLR6: CLRP014 Mask */ -#define GPIO_PORT_CLR6_CLRP015_Pos 15 /*!< GPIO_PORT CLR6: CLRP015 Position */ -#define GPIO_PORT_CLR6_CLRP015_Msk (0x01UL << GPIO_PORT_CLR6_CLRP015_Pos) /*!< GPIO_PORT CLR6: CLRP015 Mask */ -#define GPIO_PORT_CLR6_CLRP016_Pos 16 /*!< GPIO_PORT CLR6: CLRP016 Position */ -#define GPIO_PORT_CLR6_CLRP016_Msk (0x01UL << GPIO_PORT_CLR6_CLRP016_Pos) /*!< GPIO_PORT CLR6: CLRP016 Mask */ -#define GPIO_PORT_CLR6_CLRP017_Pos 17 /*!< GPIO_PORT CLR6: CLRP017 Position */ -#define GPIO_PORT_CLR6_CLRP017_Msk (0x01UL << GPIO_PORT_CLR6_CLRP017_Pos) /*!< GPIO_PORT CLR6: CLRP017 Mask */ -#define GPIO_PORT_CLR6_CLRP018_Pos 18 /*!< GPIO_PORT CLR6: CLRP018 Position */ -#define GPIO_PORT_CLR6_CLRP018_Msk (0x01UL << GPIO_PORT_CLR6_CLRP018_Pos) /*!< GPIO_PORT CLR6: CLRP018 Mask */ -#define GPIO_PORT_CLR6_CLRP019_Pos 19 /*!< GPIO_PORT CLR6: CLRP019 Position */ -#define GPIO_PORT_CLR6_CLRP019_Msk (0x01UL << GPIO_PORT_CLR6_CLRP019_Pos) /*!< GPIO_PORT CLR6: CLRP019 Mask */ -#define GPIO_PORT_CLR6_CLRP020_Pos 20 /*!< GPIO_PORT CLR6: CLRP020 Position */ -#define GPIO_PORT_CLR6_CLRP020_Msk (0x01UL << GPIO_PORT_CLR6_CLRP020_Pos) /*!< GPIO_PORT CLR6: CLRP020 Mask */ -#define GPIO_PORT_CLR6_CLRP021_Pos 21 /*!< GPIO_PORT CLR6: CLRP021 Position */ -#define GPIO_PORT_CLR6_CLRP021_Msk (0x01UL << GPIO_PORT_CLR6_CLRP021_Pos) /*!< GPIO_PORT CLR6: CLRP021 Mask */ -#define GPIO_PORT_CLR6_CLRP022_Pos 22 /*!< GPIO_PORT CLR6: CLRP022 Position */ -#define GPIO_PORT_CLR6_CLRP022_Msk (0x01UL << GPIO_PORT_CLR6_CLRP022_Pos) /*!< GPIO_PORT CLR6: CLRP022 Mask */ -#define GPIO_PORT_CLR6_CLRP023_Pos 23 /*!< GPIO_PORT CLR6: CLRP023 Position */ -#define GPIO_PORT_CLR6_CLRP023_Msk (0x01UL << GPIO_PORT_CLR6_CLRP023_Pos) /*!< GPIO_PORT CLR6: CLRP023 Mask */ -#define GPIO_PORT_CLR6_CLRP024_Pos 24 /*!< GPIO_PORT CLR6: CLRP024 Position */ -#define GPIO_PORT_CLR6_CLRP024_Msk (0x01UL << GPIO_PORT_CLR6_CLRP024_Pos) /*!< GPIO_PORT CLR6: CLRP024 Mask */ -#define GPIO_PORT_CLR6_CLRP025_Pos 25 /*!< GPIO_PORT CLR6: CLRP025 Position */ -#define GPIO_PORT_CLR6_CLRP025_Msk (0x01UL << GPIO_PORT_CLR6_CLRP025_Pos) /*!< GPIO_PORT CLR6: CLRP025 Mask */ -#define GPIO_PORT_CLR6_CLRP026_Pos 26 /*!< GPIO_PORT CLR6: CLRP026 Position */ -#define GPIO_PORT_CLR6_CLRP026_Msk (0x01UL << GPIO_PORT_CLR6_CLRP026_Pos) /*!< GPIO_PORT CLR6: CLRP026 Mask */ -#define GPIO_PORT_CLR6_CLRP027_Pos 27 /*!< GPIO_PORT CLR6: CLRP027 Position */ -#define GPIO_PORT_CLR6_CLRP027_Msk (0x01UL << GPIO_PORT_CLR6_CLRP027_Pos) /*!< GPIO_PORT CLR6: CLRP027 Mask */ -#define GPIO_PORT_CLR6_CLRP028_Pos 28 /*!< GPIO_PORT CLR6: CLRP028 Position */ -#define GPIO_PORT_CLR6_CLRP028_Msk (0x01UL << GPIO_PORT_CLR6_CLRP028_Pos) /*!< GPIO_PORT CLR6: CLRP028 Mask */ -#define GPIO_PORT_CLR6_CLRP029_Pos 29 /*!< GPIO_PORT CLR6: CLRP029 Position */ -#define GPIO_PORT_CLR6_CLRP029_Msk (0x01UL << GPIO_PORT_CLR6_CLRP029_Pos) /*!< GPIO_PORT CLR6: CLRP029 Mask */ -#define GPIO_PORT_CLR6_CLRP030_Pos 30 /*!< GPIO_PORT CLR6: CLRP030 Position */ -#define GPIO_PORT_CLR6_CLRP030_Msk (0x01UL << GPIO_PORT_CLR6_CLRP030_Pos) /*!< GPIO_PORT CLR6: CLRP030 Mask */ -#define GPIO_PORT_CLR6_CLRP031_Pos 31 /*!< GPIO_PORT CLR6: CLRP031 Position */ -#define GPIO_PORT_CLR6_CLRP031_Msk (0x01UL << GPIO_PORT_CLR6_CLRP031_Pos) /*!< GPIO_PORT CLR6: CLRP031 Mask */ - -// ------------------------------------- GPIO_PORT_CLR7 ----------------------------------------- -#define GPIO_PORT_CLR7_CLRP00_Pos 0 /*!< GPIO_PORT CLR7: CLRP00 Position */ -#define GPIO_PORT_CLR7_CLRP00_Msk (0x01UL << GPIO_PORT_CLR7_CLRP00_Pos) /*!< GPIO_PORT CLR7: CLRP00 Mask */ -#define GPIO_PORT_CLR7_CLRP01_Pos 1 /*!< GPIO_PORT CLR7: CLRP01 Position */ -#define GPIO_PORT_CLR7_CLRP01_Msk (0x01UL << GPIO_PORT_CLR7_CLRP01_Pos) /*!< GPIO_PORT CLR7: CLRP01 Mask */ -#define GPIO_PORT_CLR7_CLRP02_Pos 2 /*!< GPIO_PORT CLR7: CLRP02 Position */ -#define GPIO_PORT_CLR7_CLRP02_Msk (0x01UL << GPIO_PORT_CLR7_CLRP02_Pos) /*!< GPIO_PORT CLR7: CLRP02 Mask */ -#define GPIO_PORT_CLR7_CLRP03_Pos 3 /*!< GPIO_PORT CLR7: CLRP03 Position */ -#define GPIO_PORT_CLR7_CLRP03_Msk (0x01UL << GPIO_PORT_CLR7_CLRP03_Pos) /*!< GPIO_PORT CLR7: CLRP03 Mask */ -#define GPIO_PORT_CLR7_CLRP04_Pos 4 /*!< GPIO_PORT CLR7: CLRP04 Position */ -#define GPIO_PORT_CLR7_CLRP04_Msk (0x01UL << GPIO_PORT_CLR7_CLRP04_Pos) /*!< GPIO_PORT CLR7: CLRP04 Mask */ -#define GPIO_PORT_CLR7_CLRP05_Pos 5 /*!< GPIO_PORT CLR7: CLRP05 Position */ -#define GPIO_PORT_CLR7_CLRP05_Msk (0x01UL << GPIO_PORT_CLR7_CLRP05_Pos) /*!< GPIO_PORT CLR7: CLRP05 Mask */ -#define GPIO_PORT_CLR7_CLRP06_Pos 6 /*!< GPIO_PORT CLR7: CLRP06 Position */ -#define GPIO_PORT_CLR7_CLRP06_Msk (0x01UL << GPIO_PORT_CLR7_CLRP06_Pos) /*!< GPIO_PORT CLR7: CLRP06 Mask */ -#define GPIO_PORT_CLR7_CLRP07_Pos 7 /*!< GPIO_PORT CLR7: CLRP07 Position */ -#define GPIO_PORT_CLR7_CLRP07_Msk (0x01UL << GPIO_PORT_CLR7_CLRP07_Pos) /*!< GPIO_PORT CLR7: CLRP07 Mask */ -#define GPIO_PORT_CLR7_CLRP08_Pos 8 /*!< GPIO_PORT CLR7: CLRP08 Position */ -#define GPIO_PORT_CLR7_CLRP08_Msk (0x01UL << GPIO_PORT_CLR7_CLRP08_Pos) /*!< GPIO_PORT CLR7: CLRP08 Mask */ -#define GPIO_PORT_CLR7_CLRP09_Pos 9 /*!< GPIO_PORT CLR7: CLRP09 Position */ -#define GPIO_PORT_CLR7_CLRP09_Msk (0x01UL << GPIO_PORT_CLR7_CLRP09_Pos) /*!< GPIO_PORT CLR7: CLRP09 Mask */ -#define GPIO_PORT_CLR7_CLRP010_Pos 10 /*!< GPIO_PORT CLR7: CLRP010 Position */ -#define GPIO_PORT_CLR7_CLRP010_Msk (0x01UL << GPIO_PORT_CLR7_CLRP010_Pos) /*!< GPIO_PORT CLR7: CLRP010 Mask */ -#define GPIO_PORT_CLR7_CLRP011_Pos 11 /*!< GPIO_PORT CLR7: CLRP011 Position */ -#define GPIO_PORT_CLR7_CLRP011_Msk (0x01UL << GPIO_PORT_CLR7_CLRP011_Pos) /*!< GPIO_PORT CLR7: CLRP011 Mask */ -#define GPIO_PORT_CLR7_CLRP012_Pos 12 /*!< GPIO_PORT CLR7: CLRP012 Position */ -#define GPIO_PORT_CLR7_CLRP012_Msk (0x01UL << GPIO_PORT_CLR7_CLRP012_Pos) /*!< GPIO_PORT CLR7: CLRP012 Mask */ -#define GPIO_PORT_CLR7_CLRP013_Pos 13 /*!< GPIO_PORT CLR7: CLRP013 Position */ -#define GPIO_PORT_CLR7_CLRP013_Msk (0x01UL << GPIO_PORT_CLR7_CLRP013_Pos) /*!< GPIO_PORT CLR7: CLRP013 Mask */ -#define GPIO_PORT_CLR7_CLRP014_Pos 14 /*!< GPIO_PORT CLR7: CLRP014 Position */ -#define GPIO_PORT_CLR7_CLRP014_Msk (0x01UL << GPIO_PORT_CLR7_CLRP014_Pos) /*!< GPIO_PORT CLR7: CLRP014 Mask */ -#define GPIO_PORT_CLR7_CLRP015_Pos 15 /*!< GPIO_PORT CLR7: CLRP015 Position */ -#define GPIO_PORT_CLR7_CLRP015_Msk (0x01UL << GPIO_PORT_CLR7_CLRP015_Pos) /*!< GPIO_PORT CLR7: CLRP015 Mask */ -#define GPIO_PORT_CLR7_CLRP016_Pos 16 /*!< GPIO_PORT CLR7: CLRP016 Position */ -#define GPIO_PORT_CLR7_CLRP016_Msk (0x01UL << GPIO_PORT_CLR7_CLRP016_Pos) /*!< GPIO_PORT CLR7: CLRP016 Mask */ -#define GPIO_PORT_CLR7_CLRP017_Pos 17 /*!< GPIO_PORT CLR7: CLRP017 Position */ -#define GPIO_PORT_CLR7_CLRP017_Msk (0x01UL << GPIO_PORT_CLR7_CLRP017_Pos) /*!< GPIO_PORT CLR7: CLRP017 Mask */ -#define GPIO_PORT_CLR7_CLRP018_Pos 18 /*!< GPIO_PORT CLR7: CLRP018 Position */ -#define GPIO_PORT_CLR7_CLRP018_Msk (0x01UL << GPIO_PORT_CLR7_CLRP018_Pos) /*!< GPIO_PORT CLR7: CLRP018 Mask */ -#define GPIO_PORT_CLR7_CLRP019_Pos 19 /*!< GPIO_PORT CLR7: CLRP019 Position */ -#define GPIO_PORT_CLR7_CLRP019_Msk (0x01UL << GPIO_PORT_CLR7_CLRP019_Pos) /*!< GPIO_PORT CLR7: CLRP019 Mask */ -#define GPIO_PORT_CLR7_CLRP020_Pos 20 /*!< GPIO_PORT CLR7: CLRP020 Position */ -#define GPIO_PORT_CLR7_CLRP020_Msk (0x01UL << GPIO_PORT_CLR7_CLRP020_Pos) /*!< GPIO_PORT CLR7: CLRP020 Mask */ -#define GPIO_PORT_CLR7_CLRP021_Pos 21 /*!< GPIO_PORT CLR7: CLRP021 Position */ -#define GPIO_PORT_CLR7_CLRP021_Msk (0x01UL << GPIO_PORT_CLR7_CLRP021_Pos) /*!< GPIO_PORT CLR7: CLRP021 Mask */ -#define GPIO_PORT_CLR7_CLRP022_Pos 22 /*!< GPIO_PORT CLR7: CLRP022 Position */ -#define GPIO_PORT_CLR7_CLRP022_Msk (0x01UL << GPIO_PORT_CLR7_CLRP022_Pos) /*!< GPIO_PORT CLR7: CLRP022 Mask */ -#define GPIO_PORT_CLR7_CLRP023_Pos 23 /*!< GPIO_PORT CLR7: CLRP023 Position */ -#define GPIO_PORT_CLR7_CLRP023_Msk (0x01UL << GPIO_PORT_CLR7_CLRP023_Pos) /*!< GPIO_PORT CLR7: CLRP023 Mask */ -#define GPIO_PORT_CLR7_CLRP024_Pos 24 /*!< GPIO_PORT CLR7: CLRP024 Position */ -#define GPIO_PORT_CLR7_CLRP024_Msk (0x01UL << GPIO_PORT_CLR7_CLRP024_Pos) /*!< GPIO_PORT CLR7: CLRP024 Mask */ -#define GPIO_PORT_CLR7_CLRP025_Pos 25 /*!< GPIO_PORT CLR7: CLRP025 Position */ -#define GPIO_PORT_CLR7_CLRP025_Msk (0x01UL << GPIO_PORT_CLR7_CLRP025_Pos) /*!< GPIO_PORT CLR7: CLRP025 Mask */ -#define GPIO_PORT_CLR7_CLRP026_Pos 26 /*!< GPIO_PORT CLR7: CLRP026 Position */ -#define GPIO_PORT_CLR7_CLRP026_Msk (0x01UL << GPIO_PORT_CLR7_CLRP026_Pos) /*!< GPIO_PORT CLR7: CLRP026 Mask */ -#define GPIO_PORT_CLR7_CLRP027_Pos 27 /*!< GPIO_PORT CLR7: CLRP027 Position */ -#define GPIO_PORT_CLR7_CLRP027_Msk (0x01UL << GPIO_PORT_CLR7_CLRP027_Pos) /*!< GPIO_PORT CLR7: CLRP027 Mask */ -#define GPIO_PORT_CLR7_CLRP028_Pos 28 /*!< GPIO_PORT CLR7: CLRP028 Position */ -#define GPIO_PORT_CLR7_CLRP028_Msk (0x01UL << GPIO_PORT_CLR7_CLRP028_Pos) /*!< GPIO_PORT CLR7: CLRP028 Mask */ -#define GPIO_PORT_CLR7_CLRP029_Pos 29 /*!< GPIO_PORT CLR7: CLRP029 Position */ -#define GPIO_PORT_CLR7_CLRP029_Msk (0x01UL << GPIO_PORT_CLR7_CLRP029_Pos) /*!< GPIO_PORT CLR7: CLRP029 Mask */ -#define GPIO_PORT_CLR7_CLRP030_Pos 30 /*!< GPIO_PORT CLR7: CLRP030 Position */ -#define GPIO_PORT_CLR7_CLRP030_Msk (0x01UL << GPIO_PORT_CLR7_CLRP030_Pos) /*!< GPIO_PORT CLR7: CLRP030 Mask */ -#define GPIO_PORT_CLR7_CLRP031_Pos 31 /*!< GPIO_PORT CLR7: CLRP031 Position */ -#define GPIO_PORT_CLR7_CLRP031_Msk (0x01UL << GPIO_PORT_CLR7_CLRP031_Pos) /*!< GPIO_PORT CLR7: CLRP031 Mask */ - -// ------------------------------------- GPIO_PORT_NOT0 ----------------------------------------- -#define GPIO_PORT_NOT0_NOTP0_Pos 0 /*!< GPIO_PORT NOT0: NOTP0 Position */ -#define GPIO_PORT_NOT0_NOTP0_Msk (0x01UL << GPIO_PORT_NOT0_NOTP0_Pos) /*!< GPIO_PORT NOT0: NOTP0 Mask */ -#define GPIO_PORT_NOT0_NOTP1_Pos 1 /*!< GPIO_PORT NOT0: NOTP1 Position */ -#define GPIO_PORT_NOT0_NOTP1_Msk (0x01UL << GPIO_PORT_NOT0_NOTP1_Pos) /*!< GPIO_PORT NOT0: NOTP1 Mask */ -#define GPIO_PORT_NOT0_NOTP2_Pos 2 /*!< GPIO_PORT NOT0: NOTP2 Position */ -#define GPIO_PORT_NOT0_NOTP2_Msk (0x01UL << GPIO_PORT_NOT0_NOTP2_Pos) /*!< GPIO_PORT NOT0: NOTP2 Mask */ -#define GPIO_PORT_NOT0_NOTP3_Pos 3 /*!< GPIO_PORT NOT0: NOTP3 Position */ -#define GPIO_PORT_NOT0_NOTP3_Msk (0x01UL << GPIO_PORT_NOT0_NOTP3_Pos) /*!< GPIO_PORT NOT0: NOTP3 Mask */ -#define GPIO_PORT_NOT0_NOTP4_Pos 4 /*!< GPIO_PORT NOT0: NOTP4 Position */ -#define GPIO_PORT_NOT0_NOTP4_Msk (0x01UL << GPIO_PORT_NOT0_NOTP4_Pos) /*!< GPIO_PORT NOT0: NOTP4 Mask */ -#define GPIO_PORT_NOT0_NOTP5_Pos 5 /*!< GPIO_PORT NOT0: NOTP5 Position */ -#define GPIO_PORT_NOT0_NOTP5_Msk (0x01UL << GPIO_PORT_NOT0_NOTP5_Pos) /*!< GPIO_PORT NOT0: NOTP5 Mask */ -#define GPIO_PORT_NOT0_NOTP6_Pos 6 /*!< GPIO_PORT NOT0: NOTP6 Position */ -#define GPIO_PORT_NOT0_NOTP6_Msk (0x01UL << GPIO_PORT_NOT0_NOTP6_Pos) /*!< GPIO_PORT NOT0: NOTP6 Mask */ -#define GPIO_PORT_NOT0_NOTP7_Pos 7 /*!< GPIO_PORT NOT0: NOTP7 Position */ -#define GPIO_PORT_NOT0_NOTP7_Msk (0x01UL << GPIO_PORT_NOT0_NOTP7_Pos) /*!< GPIO_PORT NOT0: NOTP7 Mask */ -#define GPIO_PORT_NOT0_NOTP8_Pos 8 /*!< GPIO_PORT NOT0: NOTP8 Position */ -#define GPIO_PORT_NOT0_NOTP8_Msk (0x01UL << GPIO_PORT_NOT0_NOTP8_Pos) /*!< GPIO_PORT NOT0: NOTP8 Mask */ -#define GPIO_PORT_NOT0_NOTP9_Pos 9 /*!< GPIO_PORT NOT0: NOTP9 Position */ -#define GPIO_PORT_NOT0_NOTP9_Msk (0x01UL << GPIO_PORT_NOT0_NOTP9_Pos) /*!< GPIO_PORT NOT0: NOTP9 Mask */ -#define GPIO_PORT_NOT0_NOTP10_Pos 10 /*!< GPIO_PORT NOT0: NOTP10 Position */ -#define GPIO_PORT_NOT0_NOTP10_Msk (0x01UL << GPIO_PORT_NOT0_NOTP10_Pos) /*!< GPIO_PORT NOT0: NOTP10 Mask */ -#define GPIO_PORT_NOT0_NOTP11_Pos 11 /*!< GPIO_PORT NOT0: NOTP11 Position */ -#define GPIO_PORT_NOT0_NOTP11_Msk (0x01UL << GPIO_PORT_NOT0_NOTP11_Pos) /*!< GPIO_PORT NOT0: NOTP11 Mask */ -#define GPIO_PORT_NOT0_NOTP12_Pos 12 /*!< GPIO_PORT NOT0: NOTP12 Position */ -#define GPIO_PORT_NOT0_NOTP12_Msk (0x01UL << GPIO_PORT_NOT0_NOTP12_Pos) /*!< GPIO_PORT NOT0: NOTP12 Mask */ -#define GPIO_PORT_NOT0_NOTP13_Pos 13 /*!< GPIO_PORT NOT0: NOTP13 Position */ -#define GPIO_PORT_NOT0_NOTP13_Msk (0x01UL << GPIO_PORT_NOT0_NOTP13_Pos) /*!< GPIO_PORT NOT0: NOTP13 Mask */ -#define GPIO_PORT_NOT0_NOTP14_Pos 14 /*!< GPIO_PORT NOT0: NOTP14 Position */ -#define GPIO_PORT_NOT0_NOTP14_Msk (0x01UL << GPIO_PORT_NOT0_NOTP14_Pos) /*!< GPIO_PORT NOT0: NOTP14 Mask */ -#define GPIO_PORT_NOT0_NOTP15_Pos 15 /*!< GPIO_PORT NOT0: NOTP15 Position */ -#define GPIO_PORT_NOT0_NOTP15_Msk (0x01UL << GPIO_PORT_NOT0_NOTP15_Pos) /*!< GPIO_PORT NOT0: NOTP15 Mask */ -#define GPIO_PORT_NOT0_NOTP16_Pos 16 /*!< GPIO_PORT NOT0: NOTP16 Position */ -#define GPIO_PORT_NOT0_NOTP16_Msk (0x01UL << GPIO_PORT_NOT0_NOTP16_Pos) /*!< GPIO_PORT NOT0: NOTP16 Mask */ -#define GPIO_PORT_NOT0_NOTP17_Pos 17 /*!< GPIO_PORT NOT0: NOTP17 Position */ -#define GPIO_PORT_NOT0_NOTP17_Msk (0x01UL << GPIO_PORT_NOT0_NOTP17_Pos) /*!< GPIO_PORT NOT0: NOTP17 Mask */ -#define GPIO_PORT_NOT0_NOTP18_Pos 18 /*!< GPIO_PORT NOT0: NOTP18 Position */ -#define GPIO_PORT_NOT0_NOTP18_Msk (0x01UL << GPIO_PORT_NOT0_NOTP18_Pos) /*!< GPIO_PORT NOT0: NOTP18 Mask */ -#define GPIO_PORT_NOT0_NOTP19_Pos 19 /*!< GPIO_PORT NOT0: NOTP19 Position */ -#define GPIO_PORT_NOT0_NOTP19_Msk (0x01UL << GPIO_PORT_NOT0_NOTP19_Pos) /*!< GPIO_PORT NOT0: NOTP19 Mask */ -#define GPIO_PORT_NOT0_NOTP20_Pos 20 /*!< GPIO_PORT NOT0: NOTP20 Position */ -#define GPIO_PORT_NOT0_NOTP20_Msk (0x01UL << GPIO_PORT_NOT0_NOTP20_Pos) /*!< GPIO_PORT NOT0: NOTP20 Mask */ -#define GPIO_PORT_NOT0_NOTP21_Pos 21 /*!< GPIO_PORT NOT0: NOTP21 Position */ -#define GPIO_PORT_NOT0_NOTP21_Msk (0x01UL << GPIO_PORT_NOT0_NOTP21_Pos) /*!< GPIO_PORT NOT0: NOTP21 Mask */ -#define GPIO_PORT_NOT0_NOTP22_Pos 22 /*!< GPIO_PORT NOT0: NOTP22 Position */ -#define GPIO_PORT_NOT0_NOTP22_Msk (0x01UL << GPIO_PORT_NOT0_NOTP22_Pos) /*!< GPIO_PORT NOT0: NOTP22 Mask */ -#define GPIO_PORT_NOT0_NOTP23_Pos 23 /*!< GPIO_PORT NOT0: NOTP23 Position */ -#define GPIO_PORT_NOT0_NOTP23_Msk (0x01UL << GPIO_PORT_NOT0_NOTP23_Pos) /*!< GPIO_PORT NOT0: NOTP23 Mask */ -#define GPIO_PORT_NOT0_NOTP24_Pos 24 /*!< GPIO_PORT NOT0: NOTP24 Position */ -#define GPIO_PORT_NOT0_NOTP24_Msk (0x01UL << GPIO_PORT_NOT0_NOTP24_Pos) /*!< GPIO_PORT NOT0: NOTP24 Mask */ -#define GPIO_PORT_NOT0_NOTP25_Pos 25 /*!< GPIO_PORT NOT0: NOTP25 Position */ -#define GPIO_PORT_NOT0_NOTP25_Msk (0x01UL << GPIO_PORT_NOT0_NOTP25_Pos) /*!< GPIO_PORT NOT0: NOTP25 Mask */ -#define GPIO_PORT_NOT0_NOTP26_Pos 26 /*!< GPIO_PORT NOT0: NOTP26 Position */ -#define GPIO_PORT_NOT0_NOTP26_Msk (0x01UL << GPIO_PORT_NOT0_NOTP26_Pos) /*!< GPIO_PORT NOT0: NOTP26 Mask */ -#define GPIO_PORT_NOT0_NOTP27_Pos 27 /*!< GPIO_PORT NOT0: NOTP27 Position */ -#define GPIO_PORT_NOT0_NOTP27_Msk (0x01UL << GPIO_PORT_NOT0_NOTP27_Pos) /*!< GPIO_PORT NOT0: NOTP27 Mask */ -#define GPIO_PORT_NOT0_NOTP28_Pos 28 /*!< GPIO_PORT NOT0: NOTP28 Position */ -#define GPIO_PORT_NOT0_NOTP28_Msk (0x01UL << GPIO_PORT_NOT0_NOTP28_Pos) /*!< GPIO_PORT NOT0: NOTP28 Mask */ -#define GPIO_PORT_NOT0_NOTP29_Pos 29 /*!< GPIO_PORT NOT0: NOTP29 Position */ -#define GPIO_PORT_NOT0_NOTP29_Msk (0x01UL << GPIO_PORT_NOT0_NOTP29_Pos) /*!< GPIO_PORT NOT0: NOTP29 Mask */ -#define GPIO_PORT_NOT0_NOTP30_Pos 30 /*!< GPIO_PORT NOT0: NOTP30 Position */ -#define GPIO_PORT_NOT0_NOTP30_Msk (0x01UL << GPIO_PORT_NOT0_NOTP30_Pos) /*!< GPIO_PORT NOT0: NOTP30 Mask */ -#define GPIO_PORT_NOT0_NOTP31_Pos 31 /*!< GPIO_PORT NOT0: NOTP31 Position */ -#define GPIO_PORT_NOT0_NOTP31_Msk (0x01UL << GPIO_PORT_NOT0_NOTP31_Pos) /*!< GPIO_PORT NOT0: NOTP31 Mask */ - -// ------------------------------------- GPIO_PORT_NOT1 ----------------------------------------- -#define GPIO_PORT_NOT1_NOTP0_Pos 0 /*!< GPIO_PORT NOT1: NOTP0 Position */ -#define GPIO_PORT_NOT1_NOTP0_Msk (0x01UL << GPIO_PORT_NOT1_NOTP0_Pos) /*!< GPIO_PORT NOT1: NOTP0 Mask */ -#define GPIO_PORT_NOT1_NOTP1_Pos 1 /*!< GPIO_PORT NOT1: NOTP1 Position */ -#define GPIO_PORT_NOT1_NOTP1_Msk (0x01UL << GPIO_PORT_NOT1_NOTP1_Pos) /*!< GPIO_PORT NOT1: NOTP1 Mask */ -#define GPIO_PORT_NOT1_NOTP2_Pos 2 /*!< GPIO_PORT NOT1: NOTP2 Position */ -#define GPIO_PORT_NOT1_NOTP2_Msk (0x01UL << GPIO_PORT_NOT1_NOTP2_Pos) /*!< GPIO_PORT NOT1: NOTP2 Mask */ -#define GPIO_PORT_NOT1_NOTP3_Pos 3 /*!< GPIO_PORT NOT1: NOTP3 Position */ -#define GPIO_PORT_NOT1_NOTP3_Msk (0x01UL << GPIO_PORT_NOT1_NOTP3_Pos) /*!< GPIO_PORT NOT1: NOTP3 Mask */ -#define GPIO_PORT_NOT1_NOTP4_Pos 4 /*!< GPIO_PORT NOT1: NOTP4 Position */ -#define GPIO_PORT_NOT1_NOTP4_Msk (0x01UL << GPIO_PORT_NOT1_NOTP4_Pos) /*!< GPIO_PORT NOT1: NOTP4 Mask */ -#define GPIO_PORT_NOT1_NOTP5_Pos 5 /*!< GPIO_PORT NOT1: NOTP5 Position */ -#define GPIO_PORT_NOT1_NOTP5_Msk (0x01UL << GPIO_PORT_NOT1_NOTP5_Pos) /*!< GPIO_PORT NOT1: NOTP5 Mask */ -#define GPIO_PORT_NOT1_NOTP6_Pos 6 /*!< GPIO_PORT NOT1: NOTP6 Position */ -#define GPIO_PORT_NOT1_NOTP6_Msk (0x01UL << GPIO_PORT_NOT1_NOTP6_Pos) /*!< GPIO_PORT NOT1: NOTP6 Mask */ -#define GPIO_PORT_NOT1_NOTP7_Pos 7 /*!< GPIO_PORT NOT1: NOTP7 Position */ -#define GPIO_PORT_NOT1_NOTP7_Msk (0x01UL << GPIO_PORT_NOT1_NOTP7_Pos) /*!< GPIO_PORT NOT1: NOTP7 Mask */ -#define GPIO_PORT_NOT1_NOTP8_Pos 8 /*!< GPIO_PORT NOT1: NOTP8 Position */ -#define GPIO_PORT_NOT1_NOTP8_Msk (0x01UL << GPIO_PORT_NOT1_NOTP8_Pos) /*!< GPIO_PORT NOT1: NOTP8 Mask */ -#define GPIO_PORT_NOT1_NOTP9_Pos 9 /*!< GPIO_PORT NOT1: NOTP9 Position */ -#define GPIO_PORT_NOT1_NOTP9_Msk (0x01UL << GPIO_PORT_NOT1_NOTP9_Pos) /*!< GPIO_PORT NOT1: NOTP9 Mask */ -#define GPIO_PORT_NOT1_NOTP10_Pos 10 /*!< GPIO_PORT NOT1: NOTP10 Position */ -#define GPIO_PORT_NOT1_NOTP10_Msk (0x01UL << GPIO_PORT_NOT1_NOTP10_Pos) /*!< GPIO_PORT NOT1: NOTP10 Mask */ -#define GPIO_PORT_NOT1_NOTP11_Pos 11 /*!< GPIO_PORT NOT1: NOTP11 Position */ -#define GPIO_PORT_NOT1_NOTP11_Msk (0x01UL << GPIO_PORT_NOT1_NOTP11_Pos) /*!< GPIO_PORT NOT1: NOTP11 Mask */ -#define GPIO_PORT_NOT1_NOTP12_Pos 12 /*!< GPIO_PORT NOT1: NOTP12 Position */ -#define GPIO_PORT_NOT1_NOTP12_Msk (0x01UL << GPIO_PORT_NOT1_NOTP12_Pos) /*!< GPIO_PORT NOT1: NOTP12 Mask */ -#define GPIO_PORT_NOT1_NOTP13_Pos 13 /*!< GPIO_PORT NOT1: NOTP13 Position */ -#define GPIO_PORT_NOT1_NOTP13_Msk (0x01UL << GPIO_PORT_NOT1_NOTP13_Pos) /*!< GPIO_PORT NOT1: NOTP13 Mask */ -#define GPIO_PORT_NOT1_NOTP14_Pos 14 /*!< GPIO_PORT NOT1: NOTP14 Position */ -#define GPIO_PORT_NOT1_NOTP14_Msk (0x01UL << GPIO_PORT_NOT1_NOTP14_Pos) /*!< GPIO_PORT NOT1: NOTP14 Mask */ -#define GPIO_PORT_NOT1_NOTP15_Pos 15 /*!< GPIO_PORT NOT1: NOTP15 Position */ -#define GPIO_PORT_NOT1_NOTP15_Msk (0x01UL << GPIO_PORT_NOT1_NOTP15_Pos) /*!< GPIO_PORT NOT1: NOTP15 Mask */ -#define GPIO_PORT_NOT1_NOTP16_Pos 16 /*!< GPIO_PORT NOT1: NOTP16 Position */ -#define GPIO_PORT_NOT1_NOTP16_Msk (0x01UL << GPIO_PORT_NOT1_NOTP16_Pos) /*!< GPIO_PORT NOT1: NOTP16 Mask */ -#define GPIO_PORT_NOT1_NOTP17_Pos 17 /*!< GPIO_PORT NOT1: NOTP17 Position */ -#define GPIO_PORT_NOT1_NOTP17_Msk (0x01UL << GPIO_PORT_NOT1_NOTP17_Pos) /*!< GPIO_PORT NOT1: NOTP17 Mask */ -#define GPIO_PORT_NOT1_NOTP18_Pos 18 /*!< GPIO_PORT NOT1: NOTP18 Position */ -#define GPIO_PORT_NOT1_NOTP18_Msk (0x01UL << GPIO_PORT_NOT1_NOTP18_Pos) /*!< GPIO_PORT NOT1: NOTP18 Mask */ -#define GPIO_PORT_NOT1_NOTP19_Pos 19 /*!< GPIO_PORT NOT1: NOTP19 Position */ -#define GPIO_PORT_NOT1_NOTP19_Msk (0x01UL << GPIO_PORT_NOT1_NOTP19_Pos) /*!< GPIO_PORT NOT1: NOTP19 Mask */ -#define GPIO_PORT_NOT1_NOTP20_Pos 20 /*!< GPIO_PORT NOT1: NOTP20 Position */ -#define GPIO_PORT_NOT1_NOTP20_Msk (0x01UL << GPIO_PORT_NOT1_NOTP20_Pos) /*!< GPIO_PORT NOT1: NOTP20 Mask */ -#define GPIO_PORT_NOT1_NOTP21_Pos 21 /*!< GPIO_PORT NOT1: NOTP21 Position */ -#define GPIO_PORT_NOT1_NOTP21_Msk (0x01UL << GPIO_PORT_NOT1_NOTP21_Pos) /*!< GPIO_PORT NOT1: NOTP21 Mask */ -#define GPIO_PORT_NOT1_NOTP22_Pos 22 /*!< GPIO_PORT NOT1: NOTP22 Position */ -#define GPIO_PORT_NOT1_NOTP22_Msk (0x01UL << GPIO_PORT_NOT1_NOTP22_Pos) /*!< GPIO_PORT NOT1: NOTP22 Mask */ -#define GPIO_PORT_NOT1_NOTP23_Pos 23 /*!< GPIO_PORT NOT1: NOTP23 Position */ -#define GPIO_PORT_NOT1_NOTP23_Msk (0x01UL << GPIO_PORT_NOT1_NOTP23_Pos) /*!< GPIO_PORT NOT1: NOTP23 Mask */ -#define GPIO_PORT_NOT1_NOTP24_Pos 24 /*!< GPIO_PORT NOT1: NOTP24 Position */ -#define GPIO_PORT_NOT1_NOTP24_Msk (0x01UL << GPIO_PORT_NOT1_NOTP24_Pos) /*!< GPIO_PORT NOT1: NOTP24 Mask */ -#define GPIO_PORT_NOT1_NOTP25_Pos 25 /*!< GPIO_PORT NOT1: NOTP25 Position */ -#define GPIO_PORT_NOT1_NOTP25_Msk (0x01UL << GPIO_PORT_NOT1_NOTP25_Pos) /*!< GPIO_PORT NOT1: NOTP25 Mask */ -#define GPIO_PORT_NOT1_NOTP26_Pos 26 /*!< GPIO_PORT NOT1: NOTP26 Position */ -#define GPIO_PORT_NOT1_NOTP26_Msk (0x01UL << GPIO_PORT_NOT1_NOTP26_Pos) /*!< GPIO_PORT NOT1: NOTP26 Mask */ -#define GPIO_PORT_NOT1_NOTP27_Pos 27 /*!< GPIO_PORT NOT1: NOTP27 Position */ -#define GPIO_PORT_NOT1_NOTP27_Msk (0x01UL << GPIO_PORT_NOT1_NOTP27_Pos) /*!< GPIO_PORT NOT1: NOTP27 Mask */ -#define GPIO_PORT_NOT1_NOTP28_Pos 28 /*!< GPIO_PORT NOT1: NOTP28 Position */ -#define GPIO_PORT_NOT1_NOTP28_Msk (0x01UL << GPIO_PORT_NOT1_NOTP28_Pos) /*!< GPIO_PORT NOT1: NOTP28 Mask */ -#define GPIO_PORT_NOT1_NOTP29_Pos 29 /*!< GPIO_PORT NOT1: NOTP29 Position */ -#define GPIO_PORT_NOT1_NOTP29_Msk (0x01UL << GPIO_PORT_NOT1_NOTP29_Pos) /*!< GPIO_PORT NOT1: NOTP29 Mask */ -#define GPIO_PORT_NOT1_NOTP30_Pos 30 /*!< GPIO_PORT NOT1: NOTP30 Position */ -#define GPIO_PORT_NOT1_NOTP30_Msk (0x01UL << GPIO_PORT_NOT1_NOTP30_Pos) /*!< GPIO_PORT NOT1: NOTP30 Mask */ -#define GPIO_PORT_NOT1_NOTP31_Pos 31 /*!< GPIO_PORT NOT1: NOTP31 Position */ -#define GPIO_PORT_NOT1_NOTP31_Msk (0x01UL << GPIO_PORT_NOT1_NOTP31_Pos) /*!< GPIO_PORT NOT1: NOTP31 Mask */ - -// ------------------------------------- GPIO_PORT_NOT2 ----------------------------------------- -#define GPIO_PORT_NOT2_NOTP0_Pos 0 /*!< GPIO_PORT NOT2: NOTP0 Position */ -#define GPIO_PORT_NOT2_NOTP0_Msk (0x01UL << GPIO_PORT_NOT2_NOTP0_Pos) /*!< GPIO_PORT NOT2: NOTP0 Mask */ -#define GPIO_PORT_NOT2_NOTP1_Pos 1 /*!< GPIO_PORT NOT2: NOTP1 Position */ -#define GPIO_PORT_NOT2_NOTP1_Msk (0x01UL << GPIO_PORT_NOT2_NOTP1_Pos) /*!< GPIO_PORT NOT2: NOTP1 Mask */ -#define GPIO_PORT_NOT2_NOTP2_Pos 2 /*!< GPIO_PORT NOT2: NOTP2 Position */ -#define GPIO_PORT_NOT2_NOTP2_Msk (0x01UL << GPIO_PORT_NOT2_NOTP2_Pos) /*!< GPIO_PORT NOT2: NOTP2 Mask */ -#define GPIO_PORT_NOT2_NOTP3_Pos 3 /*!< GPIO_PORT NOT2: NOTP3 Position */ -#define GPIO_PORT_NOT2_NOTP3_Msk (0x01UL << GPIO_PORT_NOT2_NOTP3_Pos) /*!< GPIO_PORT NOT2: NOTP3 Mask */ -#define GPIO_PORT_NOT2_NOTP4_Pos 4 /*!< GPIO_PORT NOT2: NOTP4 Position */ -#define GPIO_PORT_NOT2_NOTP4_Msk (0x01UL << GPIO_PORT_NOT2_NOTP4_Pos) /*!< GPIO_PORT NOT2: NOTP4 Mask */ -#define GPIO_PORT_NOT2_NOTP5_Pos 5 /*!< GPIO_PORT NOT2: NOTP5 Position */ -#define GPIO_PORT_NOT2_NOTP5_Msk (0x01UL << GPIO_PORT_NOT2_NOTP5_Pos) /*!< GPIO_PORT NOT2: NOTP5 Mask */ -#define GPIO_PORT_NOT2_NOTP6_Pos 6 /*!< GPIO_PORT NOT2: NOTP6 Position */ -#define GPIO_PORT_NOT2_NOTP6_Msk (0x01UL << GPIO_PORT_NOT2_NOTP6_Pos) /*!< GPIO_PORT NOT2: NOTP6 Mask */ -#define GPIO_PORT_NOT2_NOTP7_Pos 7 /*!< GPIO_PORT NOT2: NOTP7 Position */ -#define GPIO_PORT_NOT2_NOTP7_Msk (0x01UL << GPIO_PORT_NOT2_NOTP7_Pos) /*!< GPIO_PORT NOT2: NOTP7 Mask */ -#define GPIO_PORT_NOT2_NOTP8_Pos 8 /*!< GPIO_PORT NOT2: NOTP8 Position */ -#define GPIO_PORT_NOT2_NOTP8_Msk (0x01UL << GPIO_PORT_NOT2_NOTP8_Pos) /*!< GPIO_PORT NOT2: NOTP8 Mask */ -#define GPIO_PORT_NOT2_NOTP9_Pos 9 /*!< GPIO_PORT NOT2: NOTP9 Position */ -#define GPIO_PORT_NOT2_NOTP9_Msk (0x01UL << GPIO_PORT_NOT2_NOTP9_Pos) /*!< GPIO_PORT NOT2: NOTP9 Mask */ -#define GPIO_PORT_NOT2_NOTP10_Pos 10 /*!< GPIO_PORT NOT2: NOTP10 Position */ -#define GPIO_PORT_NOT2_NOTP10_Msk (0x01UL << GPIO_PORT_NOT2_NOTP10_Pos) /*!< GPIO_PORT NOT2: NOTP10 Mask */ -#define GPIO_PORT_NOT2_NOTP11_Pos 11 /*!< GPIO_PORT NOT2: NOTP11 Position */ -#define GPIO_PORT_NOT2_NOTP11_Msk (0x01UL << GPIO_PORT_NOT2_NOTP11_Pos) /*!< GPIO_PORT NOT2: NOTP11 Mask */ -#define GPIO_PORT_NOT2_NOTP12_Pos 12 /*!< GPIO_PORT NOT2: NOTP12 Position */ -#define GPIO_PORT_NOT2_NOTP12_Msk (0x01UL << GPIO_PORT_NOT2_NOTP12_Pos) /*!< GPIO_PORT NOT2: NOTP12 Mask */ -#define GPIO_PORT_NOT2_NOTP13_Pos 13 /*!< GPIO_PORT NOT2: NOTP13 Position */ -#define GPIO_PORT_NOT2_NOTP13_Msk (0x01UL << GPIO_PORT_NOT2_NOTP13_Pos) /*!< GPIO_PORT NOT2: NOTP13 Mask */ -#define GPIO_PORT_NOT2_NOTP14_Pos 14 /*!< GPIO_PORT NOT2: NOTP14 Position */ -#define GPIO_PORT_NOT2_NOTP14_Msk (0x01UL << GPIO_PORT_NOT2_NOTP14_Pos) /*!< GPIO_PORT NOT2: NOTP14 Mask */ -#define GPIO_PORT_NOT2_NOTP15_Pos 15 /*!< GPIO_PORT NOT2: NOTP15 Position */ -#define GPIO_PORT_NOT2_NOTP15_Msk (0x01UL << GPIO_PORT_NOT2_NOTP15_Pos) /*!< GPIO_PORT NOT2: NOTP15 Mask */ -#define GPIO_PORT_NOT2_NOTP16_Pos 16 /*!< GPIO_PORT NOT2: NOTP16 Position */ -#define GPIO_PORT_NOT2_NOTP16_Msk (0x01UL << GPIO_PORT_NOT2_NOTP16_Pos) /*!< GPIO_PORT NOT2: NOTP16 Mask */ -#define GPIO_PORT_NOT2_NOTP17_Pos 17 /*!< GPIO_PORT NOT2: NOTP17 Position */ -#define GPIO_PORT_NOT2_NOTP17_Msk (0x01UL << GPIO_PORT_NOT2_NOTP17_Pos) /*!< GPIO_PORT NOT2: NOTP17 Mask */ -#define GPIO_PORT_NOT2_NOTP18_Pos 18 /*!< GPIO_PORT NOT2: NOTP18 Position */ -#define GPIO_PORT_NOT2_NOTP18_Msk (0x01UL << GPIO_PORT_NOT2_NOTP18_Pos) /*!< GPIO_PORT NOT2: NOTP18 Mask */ -#define GPIO_PORT_NOT2_NOTP19_Pos 19 /*!< GPIO_PORT NOT2: NOTP19 Position */ -#define GPIO_PORT_NOT2_NOTP19_Msk (0x01UL << GPIO_PORT_NOT2_NOTP19_Pos) /*!< GPIO_PORT NOT2: NOTP19 Mask */ -#define GPIO_PORT_NOT2_NOTP20_Pos 20 /*!< GPIO_PORT NOT2: NOTP20 Position */ -#define GPIO_PORT_NOT2_NOTP20_Msk (0x01UL << GPIO_PORT_NOT2_NOTP20_Pos) /*!< GPIO_PORT NOT2: NOTP20 Mask */ -#define GPIO_PORT_NOT2_NOTP21_Pos 21 /*!< GPIO_PORT NOT2: NOTP21 Position */ -#define GPIO_PORT_NOT2_NOTP21_Msk (0x01UL << GPIO_PORT_NOT2_NOTP21_Pos) /*!< GPIO_PORT NOT2: NOTP21 Mask */ -#define GPIO_PORT_NOT2_NOTP22_Pos 22 /*!< GPIO_PORT NOT2: NOTP22 Position */ -#define GPIO_PORT_NOT2_NOTP22_Msk (0x01UL << GPIO_PORT_NOT2_NOTP22_Pos) /*!< GPIO_PORT NOT2: NOTP22 Mask */ -#define GPIO_PORT_NOT2_NOTP23_Pos 23 /*!< GPIO_PORT NOT2: NOTP23 Position */ -#define GPIO_PORT_NOT2_NOTP23_Msk (0x01UL << GPIO_PORT_NOT2_NOTP23_Pos) /*!< GPIO_PORT NOT2: NOTP23 Mask */ -#define GPIO_PORT_NOT2_NOTP24_Pos 24 /*!< GPIO_PORT NOT2: NOTP24 Position */ -#define GPIO_PORT_NOT2_NOTP24_Msk (0x01UL << GPIO_PORT_NOT2_NOTP24_Pos) /*!< GPIO_PORT NOT2: NOTP24 Mask */ -#define GPIO_PORT_NOT2_NOTP25_Pos 25 /*!< GPIO_PORT NOT2: NOTP25 Position */ -#define GPIO_PORT_NOT2_NOTP25_Msk (0x01UL << GPIO_PORT_NOT2_NOTP25_Pos) /*!< GPIO_PORT NOT2: NOTP25 Mask */ -#define GPIO_PORT_NOT2_NOTP26_Pos 26 /*!< GPIO_PORT NOT2: NOTP26 Position */ -#define GPIO_PORT_NOT2_NOTP26_Msk (0x01UL << GPIO_PORT_NOT2_NOTP26_Pos) /*!< GPIO_PORT NOT2: NOTP26 Mask */ -#define GPIO_PORT_NOT2_NOTP27_Pos 27 /*!< GPIO_PORT NOT2: NOTP27 Position */ -#define GPIO_PORT_NOT2_NOTP27_Msk (0x01UL << GPIO_PORT_NOT2_NOTP27_Pos) /*!< GPIO_PORT NOT2: NOTP27 Mask */ -#define GPIO_PORT_NOT2_NOTP28_Pos 28 /*!< GPIO_PORT NOT2: NOTP28 Position */ -#define GPIO_PORT_NOT2_NOTP28_Msk (0x01UL << GPIO_PORT_NOT2_NOTP28_Pos) /*!< GPIO_PORT NOT2: NOTP28 Mask */ -#define GPIO_PORT_NOT2_NOTP29_Pos 29 /*!< GPIO_PORT NOT2: NOTP29 Position */ -#define GPIO_PORT_NOT2_NOTP29_Msk (0x01UL << GPIO_PORT_NOT2_NOTP29_Pos) /*!< GPIO_PORT NOT2: NOTP29 Mask */ -#define GPIO_PORT_NOT2_NOTP30_Pos 30 /*!< GPIO_PORT NOT2: NOTP30 Position */ -#define GPIO_PORT_NOT2_NOTP30_Msk (0x01UL << GPIO_PORT_NOT2_NOTP30_Pos) /*!< GPIO_PORT NOT2: NOTP30 Mask */ -#define GPIO_PORT_NOT2_NOTP31_Pos 31 /*!< GPIO_PORT NOT2: NOTP31 Position */ -#define GPIO_PORT_NOT2_NOTP31_Msk (0x01UL << GPIO_PORT_NOT2_NOTP31_Pos) /*!< GPIO_PORT NOT2: NOTP31 Mask */ - -// ------------------------------------- GPIO_PORT_NOT3 ----------------------------------------- -#define GPIO_PORT_NOT3_NOTP0_Pos 0 /*!< GPIO_PORT NOT3: NOTP0 Position */ -#define GPIO_PORT_NOT3_NOTP0_Msk (0x01UL << GPIO_PORT_NOT3_NOTP0_Pos) /*!< GPIO_PORT NOT3: NOTP0 Mask */ -#define GPIO_PORT_NOT3_NOTP1_Pos 1 /*!< GPIO_PORT NOT3: NOTP1 Position */ -#define GPIO_PORT_NOT3_NOTP1_Msk (0x01UL << GPIO_PORT_NOT3_NOTP1_Pos) /*!< GPIO_PORT NOT3: NOTP1 Mask */ -#define GPIO_PORT_NOT3_NOTP2_Pos 2 /*!< GPIO_PORT NOT3: NOTP2 Position */ -#define GPIO_PORT_NOT3_NOTP2_Msk (0x01UL << GPIO_PORT_NOT3_NOTP2_Pos) /*!< GPIO_PORT NOT3: NOTP2 Mask */ -#define GPIO_PORT_NOT3_NOTP3_Pos 3 /*!< GPIO_PORT NOT3: NOTP3 Position */ -#define GPIO_PORT_NOT3_NOTP3_Msk (0x01UL << GPIO_PORT_NOT3_NOTP3_Pos) /*!< GPIO_PORT NOT3: NOTP3 Mask */ -#define GPIO_PORT_NOT3_NOTP4_Pos 4 /*!< GPIO_PORT NOT3: NOTP4 Position */ -#define GPIO_PORT_NOT3_NOTP4_Msk (0x01UL << GPIO_PORT_NOT3_NOTP4_Pos) /*!< GPIO_PORT NOT3: NOTP4 Mask */ -#define GPIO_PORT_NOT3_NOTP5_Pos 5 /*!< GPIO_PORT NOT3: NOTP5 Position */ -#define GPIO_PORT_NOT3_NOTP5_Msk (0x01UL << GPIO_PORT_NOT3_NOTP5_Pos) /*!< GPIO_PORT NOT3: NOTP5 Mask */ -#define GPIO_PORT_NOT3_NOTP6_Pos 6 /*!< GPIO_PORT NOT3: NOTP6 Position */ -#define GPIO_PORT_NOT3_NOTP6_Msk (0x01UL << GPIO_PORT_NOT3_NOTP6_Pos) /*!< GPIO_PORT NOT3: NOTP6 Mask */ -#define GPIO_PORT_NOT3_NOTP7_Pos 7 /*!< GPIO_PORT NOT3: NOTP7 Position */ -#define GPIO_PORT_NOT3_NOTP7_Msk (0x01UL << GPIO_PORT_NOT3_NOTP7_Pos) /*!< GPIO_PORT NOT3: NOTP7 Mask */ -#define GPIO_PORT_NOT3_NOTP8_Pos 8 /*!< GPIO_PORT NOT3: NOTP8 Position */ -#define GPIO_PORT_NOT3_NOTP8_Msk (0x01UL << GPIO_PORT_NOT3_NOTP8_Pos) /*!< GPIO_PORT NOT3: NOTP8 Mask */ -#define GPIO_PORT_NOT3_NOTP9_Pos 9 /*!< GPIO_PORT NOT3: NOTP9 Position */ -#define GPIO_PORT_NOT3_NOTP9_Msk (0x01UL << GPIO_PORT_NOT3_NOTP9_Pos) /*!< GPIO_PORT NOT3: NOTP9 Mask */ -#define GPIO_PORT_NOT3_NOTP10_Pos 10 /*!< GPIO_PORT NOT3: NOTP10 Position */ -#define GPIO_PORT_NOT3_NOTP10_Msk (0x01UL << GPIO_PORT_NOT3_NOTP10_Pos) /*!< GPIO_PORT NOT3: NOTP10 Mask */ -#define GPIO_PORT_NOT3_NOTP11_Pos 11 /*!< GPIO_PORT NOT3: NOTP11 Position */ -#define GPIO_PORT_NOT3_NOTP11_Msk (0x01UL << GPIO_PORT_NOT3_NOTP11_Pos) /*!< GPIO_PORT NOT3: NOTP11 Mask */ -#define GPIO_PORT_NOT3_NOTP12_Pos 12 /*!< GPIO_PORT NOT3: NOTP12 Position */ -#define GPIO_PORT_NOT3_NOTP12_Msk (0x01UL << GPIO_PORT_NOT3_NOTP12_Pos) /*!< GPIO_PORT NOT3: NOTP12 Mask */ -#define GPIO_PORT_NOT3_NOTP13_Pos 13 /*!< GPIO_PORT NOT3: NOTP13 Position */ -#define GPIO_PORT_NOT3_NOTP13_Msk (0x01UL << GPIO_PORT_NOT3_NOTP13_Pos) /*!< GPIO_PORT NOT3: NOTP13 Mask */ -#define GPIO_PORT_NOT3_NOTP14_Pos 14 /*!< GPIO_PORT NOT3: NOTP14 Position */ -#define GPIO_PORT_NOT3_NOTP14_Msk (0x01UL << GPIO_PORT_NOT3_NOTP14_Pos) /*!< GPIO_PORT NOT3: NOTP14 Mask */ -#define GPIO_PORT_NOT3_NOTP15_Pos 15 /*!< GPIO_PORT NOT3: NOTP15 Position */ -#define GPIO_PORT_NOT3_NOTP15_Msk (0x01UL << GPIO_PORT_NOT3_NOTP15_Pos) /*!< GPIO_PORT NOT3: NOTP15 Mask */ -#define GPIO_PORT_NOT3_NOTP16_Pos 16 /*!< GPIO_PORT NOT3: NOTP16 Position */ -#define GPIO_PORT_NOT3_NOTP16_Msk (0x01UL << GPIO_PORT_NOT3_NOTP16_Pos) /*!< GPIO_PORT NOT3: NOTP16 Mask */ -#define GPIO_PORT_NOT3_NOTP17_Pos 17 /*!< GPIO_PORT NOT3: NOTP17 Position */ -#define GPIO_PORT_NOT3_NOTP17_Msk (0x01UL << GPIO_PORT_NOT3_NOTP17_Pos) /*!< GPIO_PORT NOT3: NOTP17 Mask */ -#define GPIO_PORT_NOT3_NOTP18_Pos 18 /*!< GPIO_PORT NOT3: NOTP18 Position */ -#define GPIO_PORT_NOT3_NOTP18_Msk (0x01UL << GPIO_PORT_NOT3_NOTP18_Pos) /*!< GPIO_PORT NOT3: NOTP18 Mask */ -#define GPIO_PORT_NOT3_NOTP19_Pos 19 /*!< GPIO_PORT NOT3: NOTP19 Position */ -#define GPIO_PORT_NOT3_NOTP19_Msk (0x01UL << GPIO_PORT_NOT3_NOTP19_Pos) /*!< GPIO_PORT NOT3: NOTP19 Mask */ -#define GPIO_PORT_NOT3_NOTP20_Pos 20 /*!< GPIO_PORT NOT3: NOTP20 Position */ -#define GPIO_PORT_NOT3_NOTP20_Msk (0x01UL << GPIO_PORT_NOT3_NOTP20_Pos) /*!< GPIO_PORT NOT3: NOTP20 Mask */ -#define GPIO_PORT_NOT3_NOTP21_Pos 21 /*!< GPIO_PORT NOT3: NOTP21 Position */ -#define GPIO_PORT_NOT3_NOTP21_Msk (0x01UL << GPIO_PORT_NOT3_NOTP21_Pos) /*!< GPIO_PORT NOT3: NOTP21 Mask */ -#define GPIO_PORT_NOT3_NOTP22_Pos 22 /*!< GPIO_PORT NOT3: NOTP22 Position */ -#define GPIO_PORT_NOT3_NOTP22_Msk (0x01UL << GPIO_PORT_NOT3_NOTP22_Pos) /*!< GPIO_PORT NOT3: NOTP22 Mask */ -#define GPIO_PORT_NOT3_NOTP23_Pos 23 /*!< GPIO_PORT NOT3: NOTP23 Position */ -#define GPIO_PORT_NOT3_NOTP23_Msk (0x01UL << GPIO_PORT_NOT3_NOTP23_Pos) /*!< GPIO_PORT NOT3: NOTP23 Mask */ -#define GPIO_PORT_NOT3_NOTP24_Pos 24 /*!< GPIO_PORT NOT3: NOTP24 Position */ -#define GPIO_PORT_NOT3_NOTP24_Msk (0x01UL << GPIO_PORT_NOT3_NOTP24_Pos) /*!< GPIO_PORT NOT3: NOTP24 Mask */ -#define GPIO_PORT_NOT3_NOTP25_Pos 25 /*!< GPIO_PORT NOT3: NOTP25 Position */ -#define GPIO_PORT_NOT3_NOTP25_Msk (0x01UL << GPIO_PORT_NOT3_NOTP25_Pos) /*!< GPIO_PORT NOT3: NOTP25 Mask */ -#define GPIO_PORT_NOT3_NOTP26_Pos 26 /*!< GPIO_PORT NOT3: NOTP26 Position */ -#define GPIO_PORT_NOT3_NOTP26_Msk (0x01UL << GPIO_PORT_NOT3_NOTP26_Pos) /*!< GPIO_PORT NOT3: NOTP26 Mask */ -#define GPIO_PORT_NOT3_NOTP27_Pos 27 /*!< GPIO_PORT NOT3: NOTP27 Position */ -#define GPIO_PORT_NOT3_NOTP27_Msk (0x01UL << GPIO_PORT_NOT3_NOTP27_Pos) /*!< GPIO_PORT NOT3: NOTP27 Mask */ -#define GPIO_PORT_NOT3_NOTP28_Pos 28 /*!< GPIO_PORT NOT3: NOTP28 Position */ -#define GPIO_PORT_NOT3_NOTP28_Msk (0x01UL << GPIO_PORT_NOT3_NOTP28_Pos) /*!< GPIO_PORT NOT3: NOTP28 Mask */ -#define GPIO_PORT_NOT3_NOTP29_Pos 29 /*!< GPIO_PORT NOT3: NOTP29 Position */ -#define GPIO_PORT_NOT3_NOTP29_Msk (0x01UL << GPIO_PORT_NOT3_NOTP29_Pos) /*!< GPIO_PORT NOT3: NOTP29 Mask */ -#define GPIO_PORT_NOT3_NOTP30_Pos 30 /*!< GPIO_PORT NOT3: NOTP30 Position */ -#define GPIO_PORT_NOT3_NOTP30_Msk (0x01UL << GPIO_PORT_NOT3_NOTP30_Pos) /*!< GPIO_PORT NOT3: NOTP30 Mask */ -#define GPIO_PORT_NOT3_NOTP31_Pos 31 /*!< GPIO_PORT NOT3: NOTP31 Position */ -#define GPIO_PORT_NOT3_NOTP31_Msk (0x01UL << GPIO_PORT_NOT3_NOTP31_Pos) /*!< GPIO_PORT NOT3: NOTP31 Mask */ - -// ------------------------------------- GPIO_PORT_NOT4 ----------------------------------------- -#define GPIO_PORT_NOT4_NOTP0_Pos 0 /*!< GPIO_PORT NOT4: NOTP0 Position */ -#define GPIO_PORT_NOT4_NOTP0_Msk (0x01UL << GPIO_PORT_NOT4_NOTP0_Pos) /*!< GPIO_PORT NOT4: NOTP0 Mask */ -#define GPIO_PORT_NOT4_NOTP1_Pos 1 /*!< GPIO_PORT NOT4: NOTP1 Position */ -#define GPIO_PORT_NOT4_NOTP1_Msk (0x01UL << GPIO_PORT_NOT4_NOTP1_Pos) /*!< GPIO_PORT NOT4: NOTP1 Mask */ -#define GPIO_PORT_NOT4_NOTP2_Pos 2 /*!< GPIO_PORT NOT4: NOTP2 Position */ -#define GPIO_PORT_NOT4_NOTP2_Msk (0x01UL << GPIO_PORT_NOT4_NOTP2_Pos) /*!< GPIO_PORT NOT4: NOTP2 Mask */ -#define GPIO_PORT_NOT4_NOTP3_Pos 3 /*!< GPIO_PORT NOT4: NOTP3 Position */ -#define GPIO_PORT_NOT4_NOTP3_Msk (0x01UL << GPIO_PORT_NOT4_NOTP3_Pos) /*!< GPIO_PORT NOT4: NOTP3 Mask */ -#define GPIO_PORT_NOT4_NOTP4_Pos 4 /*!< GPIO_PORT NOT4: NOTP4 Position */ -#define GPIO_PORT_NOT4_NOTP4_Msk (0x01UL << GPIO_PORT_NOT4_NOTP4_Pos) /*!< GPIO_PORT NOT4: NOTP4 Mask */ -#define GPIO_PORT_NOT4_NOTP5_Pos 5 /*!< GPIO_PORT NOT4: NOTP5 Position */ -#define GPIO_PORT_NOT4_NOTP5_Msk (0x01UL << GPIO_PORT_NOT4_NOTP5_Pos) /*!< GPIO_PORT NOT4: NOTP5 Mask */ -#define GPIO_PORT_NOT4_NOTP6_Pos 6 /*!< GPIO_PORT NOT4: NOTP6 Position */ -#define GPIO_PORT_NOT4_NOTP6_Msk (0x01UL << GPIO_PORT_NOT4_NOTP6_Pos) /*!< GPIO_PORT NOT4: NOTP6 Mask */ -#define GPIO_PORT_NOT4_NOTP7_Pos 7 /*!< GPIO_PORT NOT4: NOTP7 Position */ -#define GPIO_PORT_NOT4_NOTP7_Msk (0x01UL << GPIO_PORT_NOT4_NOTP7_Pos) /*!< GPIO_PORT NOT4: NOTP7 Mask */ -#define GPIO_PORT_NOT4_NOTP8_Pos 8 /*!< GPIO_PORT NOT4: NOTP8 Position */ -#define GPIO_PORT_NOT4_NOTP8_Msk (0x01UL << GPIO_PORT_NOT4_NOTP8_Pos) /*!< GPIO_PORT NOT4: NOTP8 Mask */ -#define GPIO_PORT_NOT4_NOTP9_Pos 9 /*!< GPIO_PORT NOT4: NOTP9 Position */ -#define GPIO_PORT_NOT4_NOTP9_Msk (0x01UL << GPIO_PORT_NOT4_NOTP9_Pos) /*!< GPIO_PORT NOT4: NOTP9 Mask */ -#define GPIO_PORT_NOT4_NOTP10_Pos 10 /*!< GPIO_PORT NOT4: NOTP10 Position */ -#define GPIO_PORT_NOT4_NOTP10_Msk (0x01UL << GPIO_PORT_NOT4_NOTP10_Pos) /*!< GPIO_PORT NOT4: NOTP10 Mask */ -#define GPIO_PORT_NOT4_NOTP11_Pos 11 /*!< GPIO_PORT NOT4: NOTP11 Position */ -#define GPIO_PORT_NOT4_NOTP11_Msk (0x01UL << GPIO_PORT_NOT4_NOTP11_Pos) /*!< GPIO_PORT NOT4: NOTP11 Mask */ -#define GPIO_PORT_NOT4_NOTP12_Pos 12 /*!< GPIO_PORT NOT4: NOTP12 Position */ -#define GPIO_PORT_NOT4_NOTP12_Msk (0x01UL << GPIO_PORT_NOT4_NOTP12_Pos) /*!< GPIO_PORT NOT4: NOTP12 Mask */ -#define GPIO_PORT_NOT4_NOTP13_Pos 13 /*!< GPIO_PORT NOT4: NOTP13 Position */ -#define GPIO_PORT_NOT4_NOTP13_Msk (0x01UL << GPIO_PORT_NOT4_NOTP13_Pos) /*!< GPIO_PORT NOT4: NOTP13 Mask */ -#define GPIO_PORT_NOT4_NOTP14_Pos 14 /*!< GPIO_PORT NOT4: NOTP14 Position */ -#define GPIO_PORT_NOT4_NOTP14_Msk (0x01UL << GPIO_PORT_NOT4_NOTP14_Pos) /*!< GPIO_PORT NOT4: NOTP14 Mask */ -#define GPIO_PORT_NOT4_NOTP15_Pos 15 /*!< GPIO_PORT NOT4: NOTP15 Position */ -#define GPIO_PORT_NOT4_NOTP15_Msk (0x01UL << GPIO_PORT_NOT4_NOTP15_Pos) /*!< GPIO_PORT NOT4: NOTP15 Mask */ -#define GPIO_PORT_NOT4_NOTP16_Pos 16 /*!< GPIO_PORT NOT4: NOTP16 Position */ -#define GPIO_PORT_NOT4_NOTP16_Msk (0x01UL << GPIO_PORT_NOT4_NOTP16_Pos) /*!< GPIO_PORT NOT4: NOTP16 Mask */ -#define GPIO_PORT_NOT4_NOTP17_Pos 17 /*!< GPIO_PORT NOT4: NOTP17 Position */ -#define GPIO_PORT_NOT4_NOTP17_Msk (0x01UL << GPIO_PORT_NOT4_NOTP17_Pos) /*!< GPIO_PORT NOT4: NOTP17 Mask */ -#define GPIO_PORT_NOT4_NOTP18_Pos 18 /*!< GPIO_PORT NOT4: NOTP18 Position */ -#define GPIO_PORT_NOT4_NOTP18_Msk (0x01UL << GPIO_PORT_NOT4_NOTP18_Pos) /*!< GPIO_PORT NOT4: NOTP18 Mask */ -#define GPIO_PORT_NOT4_NOTP19_Pos 19 /*!< GPIO_PORT NOT4: NOTP19 Position */ -#define GPIO_PORT_NOT4_NOTP19_Msk (0x01UL << GPIO_PORT_NOT4_NOTP19_Pos) /*!< GPIO_PORT NOT4: NOTP19 Mask */ -#define GPIO_PORT_NOT4_NOTP20_Pos 20 /*!< GPIO_PORT NOT4: NOTP20 Position */ -#define GPIO_PORT_NOT4_NOTP20_Msk (0x01UL << GPIO_PORT_NOT4_NOTP20_Pos) /*!< GPIO_PORT NOT4: NOTP20 Mask */ -#define GPIO_PORT_NOT4_NOTP21_Pos 21 /*!< GPIO_PORT NOT4: NOTP21 Position */ -#define GPIO_PORT_NOT4_NOTP21_Msk (0x01UL << GPIO_PORT_NOT4_NOTP21_Pos) /*!< GPIO_PORT NOT4: NOTP21 Mask */ -#define GPIO_PORT_NOT4_NOTP22_Pos 22 /*!< GPIO_PORT NOT4: NOTP22 Position */ -#define GPIO_PORT_NOT4_NOTP22_Msk (0x01UL << GPIO_PORT_NOT4_NOTP22_Pos) /*!< GPIO_PORT NOT4: NOTP22 Mask */ -#define GPIO_PORT_NOT4_NOTP23_Pos 23 /*!< GPIO_PORT NOT4: NOTP23 Position */ -#define GPIO_PORT_NOT4_NOTP23_Msk (0x01UL << GPIO_PORT_NOT4_NOTP23_Pos) /*!< GPIO_PORT NOT4: NOTP23 Mask */ -#define GPIO_PORT_NOT4_NOTP24_Pos 24 /*!< GPIO_PORT NOT4: NOTP24 Position */ -#define GPIO_PORT_NOT4_NOTP24_Msk (0x01UL << GPIO_PORT_NOT4_NOTP24_Pos) /*!< GPIO_PORT NOT4: NOTP24 Mask */ -#define GPIO_PORT_NOT4_NOTP25_Pos 25 /*!< GPIO_PORT NOT4: NOTP25 Position */ -#define GPIO_PORT_NOT4_NOTP25_Msk (0x01UL << GPIO_PORT_NOT4_NOTP25_Pos) /*!< GPIO_PORT NOT4: NOTP25 Mask */ -#define GPIO_PORT_NOT4_NOTP26_Pos 26 /*!< GPIO_PORT NOT4: NOTP26 Position */ -#define GPIO_PORT_NOT4_NOTP26_Msk (0x01UL << GPIO_PORT_NOT4_NOTP26_Pos) /*!< GPIO_PORT NOT4: NOTP26 Mask */ -#define GPIO_PORT_NOT4_NOTP27_Pos 27 /*!< GPIO_PORT NOT4: NOTP27 Position */ -#define GPIO_PORT_NOT4_NOTP27_Msk (0x01UL << GPIO_PORT_NOT4_NOTP27_Pos) /*!< GPIO_PORT NOT4: NOTP27 Mask */ -#define GPIO_PORT_NOT4_NOTP28_Pos 28 /*!< GPIO_PORT NOT4: NOTP28 Position */ -#define GPIO_PORT_NOT4_NOTP28_Msk (0x01UL << GPIO_PORT_NOT4_NOTP28_Pos) /*!< GPIO_PORT NOT4: NOTP28 Mask */ -#define GPIO_PORT_NOT4_NOTP29_Pos 29 /*!< GPIO_PORT NOT4: NOTP29 Position */ -#define GPIO_PORT_NOT4_NOTP29_Msk (0x01UL << GPIO_PORT_NOT4_NOTP29_Pos) /*!< GPIO_PORT NOT4: NOTP29 Mask */ -#define GPIO_PORT_NOT4_NOTP30_Pos 30 /*!< GPIO_PORT NOT4: NOTP30 Position */ -#define GPIO_PORT_NOT4_NOTP30_Msk (0x01UL << GPIO_PORT_NOT4_NOTP30_Pos) /*!< GPIO_PORT NOT4: NOTP30 Mask */ -#define GPIO_PORT_NOT4_NOTP31_Pos 31 /*!< GPIO_PORT NOT4: NOTP31 Position */ -#define GPIO_PORT_NOT4_NOTP31_Msk (0x01UL << GPIO_PORT_NOT4_NOTP31_Pos) /*!< GPIO_PORT NOT4: NOTP31 Mask */ - -// ------------------------------------- GPIO_PORT_NOT5 ----------------------------------------- -#define GPIO_PORT_NOT5_NOTP0_Pos 0 /*!< GPIO_PORT NOT5: NOTP0 Position */ -#define GPIO_PORT_NOT5_NOTP0_Msk (0x01UL << GPIO_PORT_NOT5_NOTP0_Pos) /*!< GPIO_PORT NOT5: NOTP0 Mask */ -#define GPIO_PORT_NOT5_NOTP1_Pos 1 /*!< GPIO_PORT NOT5: NOTP1 Position */ -#define GPIO_PORT_NOT5_NOTP1_Msk (0x01UL << GPIO_PORT_NOT5_NOTP1_Pos) /*!< GPIO_PORT NOT5: NOTP1 Mask */ -#define GPIO_PORT_NOT5_NOTP2_Pos 2 /*!< GPIO_PORT NOT5: NOTP2 Position */ -#define GPIO_PORT_NOT5_NOTP2_Msk (0x01UL << GPIO_PORT_NOT5_NOTP2_Pos) /*!< GPIO_PORT NOT5: NOTP2 Mask */ -#define GPIO_PORT_NOT5_NOTP3_Pos 3 /*!< GPIO_PORT NOT5: NOTP3 Position */ -#define GPIO_PORT_NOT5_NOTP3_Msk (0x01UL << GPIO_PORT_NOT5_NOTP3_Pos) /*!< GPIO_PORT NOT5: NOTP3 Mask */ -#define GPIO_PORT_NOT5_NOTP4_Pos 4 /*!< GPIO_PORT NOT5: NOTP4 Position */ -#define GPIO_PORT_NOT5_NOTP4_Msk (0x01UL << GPIO_PORT_NOT5_NOTP4_Pos) /*!< GPIO_PORT NOT5: NOTP4 Mask */ -#define GPIO_PORT_NOT5_NOTP5_Pos 5 /*!< GPIO_PORT NOT5: NOTP5 Position */ -#define GPIO_PORT_NOT5_NOTP5_Msk (0x01UL << GPIO_PORT_NOT5_NOTP5_Pos) /*!< GPIO_PORT NOT5: NOTP5 Mask */ -#define GPIO_PORT_NOT5_NOTP6_Pos 6 /*!< GPIO_PORT NOT5: NOTP6 Position */ -#define GPIO_PORT_NOT5_NOTP6_Msk (0x01UL << GPIO_PORT_NOT5_NOTP6_Pos) /*!< GPIO_PORT NOT5: NOTP6 Mask */ -#define GPIO_PORT_NOT5_NOTP7_Pos 7 /*!< GPIO_PORT NOT5: NOTP7 Position */ -#define GPIO_PORT_NOT5_NOTP7_Msk (0x01UL << GPIO_PORT_NOT5_NOTP7_Pos) /*!< GPIO_PORT NOT5: NOTP7 Mask */ -#define GPIO_PORT_NOT5_NOTP8_Pos 8 /*!< GPIO_PORT NOT5: NOTP8 Position */ -#define GPIO_PORT_NOT5_NOTP8_Msk (0x01UL << GPIO_PORT_NOT5_NOTP8_Pos) /*!< GPIO_PORT NOT5: NOTP8 Mask */ -#define GPIO_PORT_NOT5_NOTP9_Pos 9 /*!< GPIO_PORT NOT5: NOTP9 Position */ -#define GPIO_PORT_NOT5_NOTP9_Msk (0x01UL << GPIO_PORT_NOT5_NOTP9_Pos) /*!< GPIO_PORT NOT5: NOTP9 Mask */ -#define GPIO_PORT_NOT5_NOTP10_Pos 10 /*!< GPIO_PORT NOT5: NOTP10 Position */ -#define GPIO_PORT_NOT5_NOTP10_Msk (0x01UL << GPIO_PORT_NOT5_NOTP10_Pos) /*!< GPIO_PORT NOT5: NOTP10 Mask */ -#define GPIO_PORT_NOT5_NOTP11_Pos 11 /*!< GPIO_PORT NOT5: NOTP11 Position */ -#define GPIO_PORT_NOT5_NOTP11_Msk (0x01UL << GPIO_PORT_NOT5_NOTP11_Pos) /*!< GPIO_PORT NOT5: NOTP11 Mask */ -#define GPIO_PORT_NOT5_NOTP12_Pos 12 /*!< GPIO_PORT NOT5: NOTP12 Position */ -#define GPIO_PORT_NOT5_NOTP12_Msk (0x01UL << GPIO_PORT_NOT5_NOTP12_Pos) /*!< GPIO_PORT NOT5: NOTP12 Mask */ -#define GPIO_PORT_NOT5_NOTP13_Pos 13 /*!< GPIO_PORT NOT5: NOTP13 Position */ -#define GPIO_PORT_NOT5_NOTP13_Msk (0x01UL << GPIO_PORT_NOT5_NOTP13_Pos) /*!< GPIO_PORT NOT5: NOTP13 Mask */ -#define GPIO_PORT_NOT5_NOTP14_Pos 14 /*!< GPIO_PORT NOT5: NOTP14 Position */ -#define GPIO_PORT_NOT5_NOTP14_Msk (0x01UL << GPIO_PORT_NOT5_NOTP14_Pos) /*!< GPIO_PORT NOT5: NOTP14 Mask */ -#define GPIO_PORT_NOT5_NOTP15_Pos 15 /*!< GPIO_PORT NOT5: NOTP15 Position */ -#define GPIO_PORT_NOT5_NOTP15_Msk (0x01UL << GPIO_PORT_NOT5_NOTP15_Pos) /*!< GPIO_PORT NOT5: NOTP15 Mask */ -#define GPIO_PORT_NOT5_NOTP16_Pos 16 /*!< GPIO_PORT NOT5: NOTP16 Position */ -#define GPIO_PORT_NOT5_NOTP16_Msk (0x01UL << GPIO_PORT_NOT5_NOTP16_Pos) /*!< GPIO_PORT NOT5: NOTP16 Mask */ -#define GPIO_PORT_NOT5_NOTP17_Pos 17 /*!< GPIO_PORT NOT5: NOTP17 Position */ -#define GPIO_PORT_NOT5_NOTP17_Msk (0x01UL << GPIO_PORT_NOT5_NOTP17_Pos) /*!< GPIO_PORT NOT5: NOTP17 Mask */ -#define GPIO_PORT_NOT5_NOTP18_Pos 18 /*!< GPIO_PORT NOT5: NOTP18 Position */ -#define GPIO_PORT_NOT5_NOTP18_Msk (0x01UL << GPIO_PORT_NOT5_NOTP18_Pos) /*!< GPIO_PORT NOT5: NOTP18 Mask */ -#define GPIO_PORT_NOT5_NOTP19_Pos 19 /*!< GPIO_PORT NOT5: NOTP19 Position */ -#define GPIO_PORT_NOT5_NOTP19_Msk (0x01UL << GPIO_PORT_NOT5_NOTP19_Pos) /*!< GPIO_PORT NOT5: NOTP19 Mask */ -#define GPIO_PORT_NOT5_NOTP20_Pos 20 /*!< GPIO_PORT NOT5: NOTP20 Position */ -#define GPIO_PORT_NOT5_NOTP20_Msk (0x01UL << GPIO_PORT_NOT5_NOTP20_Pos) /*!< GPIO_PORT NOT5: NOTP20 Mask */ -#define GPIO_PORT_NOT5_NOTP21_Pos 21 /*!< GPIO_PORT NOT5: NOTP21 Position */ -#define GPIO_PORT_NOT5_NOTP21_Msk (0x01UL << GPIO_PORT_NOT5_NOTP21_Pos) /*!< GPIO_PORT NOT5: NOTP21 Mask */ -#define GPIO_PORT_NOT5_NOTP22_Pos 22 /*!< GPIO_PORT NOT5: NOTP22 Position */ -#define GPIO_PORT_NOT5_NOTP22_Msk (0x01UL << GPIO_PORT_NOT5_NOTP22_Pos) /*!< GPIO_PORT NOT5: NOTP22 Mask */ -#define GPIO_PORT_NOT5_NOTP23_Pos 23 /*!< GPIO_PORT NOT5: NOTP23 Position */ -#define GPIO_PORT_NOT5_NOTP23_Msk (0x01UL << GPIO_PORT_NOT5_NOTP23_Pos) /*!< GPIO_PORT NOT5: NOTP23 Mask */ -#define GPIO_PORT_NOT5_NOTP24_Pos 24 /*!< GPIO_PORT NOT5: NOTP24 Position */ -#define GPIO_PORT_NOT5_NOTP24_Msk (0x01UL << GPIO_PORT_NOT5_NOTP24_Pos) /*!< GPIO_PORT NOT5: NOTP24 Mask */ -#define GPIO_PORT_NOT5_NOTP25_Pos 25 /*!< GPIO_PORT NOT5: NOTP25 Position */ -#define GPIO_PORT_NOT5_NOTP25_Msk (0x01UL << GPIO_PORT_NOT5_NOTP25_Pos) /*!< GPIO_PORT NOT5: NOTP25 Mask */ -#define GPIO_PORT_NOT5_NOTP26_Pos 26 /*!< GPIO_PORT NOT5: NOTP26 Position */ -#define GPIO_PORT_NOT5_NOTP26_Msk (0x01UL << GPIO_PORT_NOT5_NOTP26_Pos) /*!< GPIO_PORT NOT5: NOTP26 Mask */ -#define GPIO_PORT_NOT5_NOTP27_Pos 27 /*!< GPIO_PORT NOT5: NOTP27 Position */ -#define GPIO_PORT_NOT5_NOTP27_Msk (0x01UL << GPIO_PORT_NOT5_NOTP27_Pos) /*!< GPIO_PORT NOT5: NOTP27 Mask */ -#define GPIO_PORT_NOT5_NOTP28_Pos 28 /*!< GPIO_PORT NOT5: NOTP28 Position */ -#define GPIO_PORT_NOT5_NOTP28_Msk (0x01UL << GPIO_PORT_NOT5_NOTP28_Pos) /*!< GPIO_PORT NOT5: NOTP28 Mask */ -#define GPIO_PORT_NOT5_NOTP29_Pos 29 /*!< GPIO_PORT NOT5: NOTP29 Position */ -#define GPIO_PORT_NOT5_NOTP29_Msk (0x01UL << GPIO_PORT_NOT5_NOTP29_Pos) /*!< GPIO_PORT NOT5: NOTP29 Mask */ -#define GPIO_PORT_NOT5_NOTP30_Pos 30 /*!< GPIO_PORT NOT5: NOTP30 Position */ -#define GPIO_PORT_NOT5_NOTP30_Msk (0x01UL << GPIO_PORT_NOT5_NOTP30_Pos) /*!< GPIO_PORT NOT5: NOTP30 Mask */ -#define GPIO_PORT_NOT5_NOTP31_Pos 31 /*!< GPIO_PORT NOT5: NOTP31 Position */ -#define GPIO_PORT_NOT5_NOTP31_Msk (0x01UL << GPIO_PORT_NOT5_NOTP31_Pos) /*!< GPIO_PORT NOT5: NOTP31 Mask */ - -// ------------------------------------- GPIO_PORT_NOT6 ----------------------------------------- -#define GPIO_PORT_NOT6_NOTP0_Pos 0 /*!< GPIO_PORT NOT6: NOTP0 Position */ -#define GPIO_PORT_NOT6_NOTP0_Msk (0x01UL << GPIO_PORT_NOT6_NOTP0_Pos) /*!< GPIO_PORT NOT6: NOTP0 Mask */ -#define GPIO_PORT_NOT6_NOTP1_Pos 1 /*!< GPIO_PORT NOT6: NOTP1 Position */ -#define GPIO_PORT_NOT6_NOTP1_Msk (0x01UL << GPIO_PORT_NOT6_NOTP1_Pos) /*!< GPIO_PORT NOT6: NOTP1 Mask */ -#define GPIO_PORT_NOT6_NOTP2_Pos 2 /*!< GPIO_PORT NOT6: NOTP2 Position */ -#define GPIO_PORT_NOT6_NOTP2_Msk (0x01UL << GPIO_PORT_NOT6_NOTP2_Pos) /*!< GPIO_PORT NOT6: NOTP2 Mask */ -#define GPIO_PORT_NOT6_NOTP3_Pos 3 /*!< GPIO_PORT NOT6: NOTP3 Position */ -#define GPIO_PORT_NOT6_NOTP3_Msk (0x01UL << GPIO_PORT_NOT6_NOTP3_Pos) /*!< GPIO_PORT NOT6: NOTP3 Mask */ -#define GPIO_PORT_NOT6_NOTP4_Pos 4 /*!< GPIO_PORT NOT6: NOTP4 Position */ -#define GPIO_PORT_NOT6_NOTP4_Msk (0x01UL << GPIO_PORT_NOT6_NOTP4_Pos) /*!< GPIO_PORT NOT6: NOTP4 Mask */ -#define GPIO_PORT_NOT6_NOTP5_Pos 5 /*!< GPIO_PORT NOT6: NOTP5 Position */ -#define GPIO_PORT_NOT6_NOTP5_Msk (0x01UL << GPIO_PORT_NOT6_NOTP5_Pos) /*!< GPIO_PORT NOT6: NOTP5 Mask */ -#define GPIO_PORT_NOT6_NOTP6_Pos 6 /*!< GPIO_PORT NOT6: NOTP6 Position */ -#define GPIO_PORT_NOT6_NOTP6_Msk (0x01UL << GPIO_PORT_NOT6_NOTP6_Pos) /*!< GPIO_PORT NOT6: NOTP6 Mask */ -#define GPIO_PORT_NOT6_NOTP7_Pos 7 /*!< GPIO_PORT NOT6: NOTP7 Position */ -#define GPIO_PORT_NOT6_NOTP7_Msk (0x01UL << GPIO_PORT_NOT6_NOTP7_Pos) /*!< GPIO_PORT NOT6: NOTP7 Mask */ -#define GPIO_PORT_NOT6_NOTP8_Pos 8 /*!< GPIO_PORT NOT6: NOTP8 Position */ -#define GPIO_PORT_NOT6_NOTP8_Msk (0x01UL << GPIO_PORT_NOT6_NOTP8_Pos) /*!< GPIO_PORT NOT6: NOTP8 Mask */ -#define GPIO_PORT_NOT6_NOTP9_Pos 9 /*!< GPIO_PORT NOT6: NOTP9 Position */ -#define GPIO_PORT_NOT6_NOTP9_Msk (0x01UL << GPIO_PORT_NOT6_NOTP9_Pos) /*!< GPIO_PORT NOT6: NOTP9 Mask */ -#define GPIO_PORT_NOT6_NOTP10_Pos 10 /*!< GPIO_PORT NOT6: NOTP10 Position */ -#define GPIO_PORT_NOT6_NOTP10_Msk (0x01UL << GPIO_PORT_NOT6_NOTP10_Pos) /*!< GPIO_PORT NOT6: NOTP10 Mask */ -#define GPIO_PORT_NOT6_NOTP11_Pos 11 /*!< GPIO_PORT NOT6: NOTP11 Position */ -#define GPIO_PORT_NOT6_NOTP11_Msk (0x01UL << GPIO_PORT_NOT6_NOTP11_Pos) /*!< GPIO_PORT NOT6: NOTP11 Mask */ -#define GPIO_PORT_NOT6_NOTP12_Pos 12 /*!< GPIO_PORT NOT6: NOTP12 Position */ -#define GPIO_PORT_NOT6_NOTP12_Msk (0x01UL << GPIO_PORT_NOT6_NOTP12_Pos) /*!< GPIO_PORT NOT6: NOTP12 Mask */ -#define GPIO_PORT_NOT6_NOTP13_Pos 13 /*!< GPIO_PORT NOT6: NOTP13 Position */ -#define GPIO_PORT_NOT6_NOTP13_Msk (0x01UL << GPIO_PORT_NOT6_NOTP13_Pos) /*!< GPIO_PORT NOT6: NOTP13 Mask */ -#define GPIO_PORT_NOT6_NOTP14_Pos 14 /*!< GPIO_PORT NOT6: NOTP14 Position */ -#define GPIO_PORT_NOT6_NOTP14_Msk (0x01UL << GPIO_PORT_NOT6_NOTP14_Pos) /*!< GPIO_PORT NOT6: NOTP14 Mask */ -#define GPIO_PORT_NOT6_NOTP15_Pos 15 /*!< GPIO_PORT NOT6: NOTP15 Position */ -#define GPIO_PORT_NOT6_NOTP15_Msk (0x01UL << GPIO_PORT_NOT6_NOTP15_Pos) /*!< GPIO_PORT NOT6: NOTP15 Mask */ -#define GPIO_PORT_NOT6_NOTP16_Pos 16 /*!< GPIO_PORT NOT6: NOTP16 Position */ -#define GPIO_PORT_NOT6_NOTP16_Msk (0x01UL << GPIO_PORT_NOT6_NOTP16_Pos) /*!< GPIO_PORT NOT6: NOTP16 Mask */ -#define GPIO_PORT_NOT6_NOTP17_Pos 17 /*!< GPIO_PORT NOT6: NOTP17 Position */ -#define GPIO_PORT_NOT6_NOTP17_Msk (0x01UL << GPIO_PORT_NOT6_NOTP17_Pos) /*!< GPIO_PORT NOT6: NOTP17 Mask */ -#define GPIO_PORT_NOT6_NOTP18_Pos 18 /*!< GPIO_PORT NOT6: NOTP18 Position */ -#define GPIO_PORT_NOT6_NOTP18_Msk (0x01UL << GPIO_PORT_NOT6_NOTP18_Pos) /*!< GPIO_PORT NOT6: NOTP18 Mask */ -#define GPIO_PORT_NOT6_NOTP19_Pos 19 /*!< GPIO_PORT NOT6: NOTP19 Position */ -#define GPIO_PORT_NOT6_NOTP19_Msk (0x01UL << GPIO_PORT_NOT6_NOTP19_Pos) /*!< GPIO_PORT NOT6: NOTP19 Mask */ -#define GPIO_PORT_NOT6_NOTP20_Pos 20 /*!< GPIO_PORT NOT6: NOTP20 Position */ -#define GPIO_PORT_NOT6_NOTP20_Msk (0x01UL << GPIO_PORT_NOT6_NOTP20_Pos) /*!< GPIO_PORT NOT6: NOTP20 Mask */ -#define GPIO_PORT_NOT6_NOTP21_Pos 21 /*!< GPIO_PORT NOT6: NOTP21 Position */ -#define GPIO_PORT_NOT6_NOTP21_Msk (0x01UL << GPIO_PORT_NOT6_NOTP21_Pos) /*!< GPIO_PORT NOT6: NOTP21 Mask */ -#define GPIO_PORT_NOT6_NOTP22_Pos 22 /*!< GPIO_PORT NOT6: NOTP22 Position */ -#define GPIO_PORT_NOT6_NOTP22_Msk (0x01UL << GPIO_PORT_NOT6_NOTP22_Pos) /*!< GPIO_PORT NOT6: NOTP22 Mask */ -#define GPIO_PORT_NOT6_NOTP23_Pos 23 /*!< GPIO_PORT NOT6: NOTP23 Position */ -#define GPIO_PORT_NOT6_NOTP23_Msk (0x01UL << GPIO_PORT_NOT6_NOTP23_Pos) /*!< GPIO_PORT NOT6: NOTP23 Mask */ -#define GPIO_PORT_NOT6_NOTP24_Pos 24 /*!< GPIO_PORT NOT6: NOTP24 Position */ -#define GPIO_PORT_NOT6_NOTP24_Msk (0x01UL << GPIO_PORT_NOT6_NOTP24_Pos) /*!< GPIO_PORT NOT6: NOTP24 Mask */ -#define GPIO_PORT_NOT6_NOTP25_Pos 25 /*!< GPIO_PORT NOT6: NOTP25 Position */ -#define GPIO_PORT_NOT6_NOTP25_Msk (0x01UL << GPIO_PORT_NOT6_NOTP25_Pos) /*!< GPIO_PORT NOT6: NOTP25 Mask */ -#define GPIO_PORT_NOT6_NOTP26_Pos 26 /*!< GPIO_PORT NOT6: NOTP26 Position */ -#define GPIO_PORT_NOT6_NOTP26_Msk (0x01UL << GPIO_PORT_NOT6_NOTP26_Pos) /*!< GPIO_PORT NOT6: NOTP26 Mask */ -#define GPIO_PORT_NOT6_NOTP27_Pos 27 /*!< GPIO_PORT NOT6: NOTP27 Position */ -#define GPIO_PORT_NOT6_NOTP27_Msk (0x01UL << GPIO_PORT_NOT6_NOTP27_Pos) /*!< GPIO_PORT NOT6: NOTP27 Mask */ -#define GPIO_PORT_NOT6_NOTP28_Pos 28 /*!< GPIO_PORT NOT6: NOTP28 Position */ -#define GPIO_PORT_NOT6_NOTP28_Msk (0x01UL << GPIO_PORT_NOT6_NOTP28_Pos) /*!< GPIO_PORT NOT6: NOTP28 Mask */ -#define GPIO_PORT_NOT6_NOTP29_Pos 29 /*!< GPIO_PORT NOT6: NOTP29 Position */ -#define GPIO_PORT_NOT6_NOTP29_Msk (0x01UL << GPIO_PORT_NOT6_NOTP29_Pos) /*!< GPIO_PORT NOT6: NOTP29 Mask */ -#define GPIO_PORT_NOT6_NOTP30_Pos 30 /*!< GPIO_PORT NOT6: NOTP30 Position */ -#define GPIO_PORT_NOT6_NOTP30_Msk (0x01UL << GPIO_PORT_NOT6_NOTP30_Pos) /*!< GPIO_PORT NOT6: NOTP30 Mask */ -#define GPIO_PORT_NOT6_NOTP31_Pos 31 /*!< GPIO_PORT NOT6: NOTP31 Position */ -#define GPIO_PORT_NOT6_NOTP31_Msk (0x01UL << GPIO_PORT_NOT6_NOTP31_Pos) /*!< GPIO_PORT NOT6: NOTP31 Mask */ - -// ------------------------------------- GPIO_PORT_NOT7 ----------------------------------------- -#define GPIO_PORT_NOT7_NOTP0_Pos 0 /*!< GPIO_PORT NOT7: NOTP0 Position */ -#define GPIO_PORT_NOT7_NOTP0_Msk (0x01UL << GPIO_PORT_NOT7_NOTP0_Pos) /*!< GPIO_PORT NOT7: NOTP0 Mask */ -#define GPIO_PORT_NOT7_NOTP1_Pos 1 /*!< GPIO_PORT NOT7: NOTP1 Position */ -#define GPIO_PORT_NOT7_NOTP1_Msk (0x01UL << GPIO_PORT_NOT7_NOTP1_Pos) /*!< GPIO_PORT NOT7: NOTP1 Mask */ -#define GPIO_PORT_NOT7_NOTP2_Pos 2 /*!< GPIO_PORT NOT7: NOTP2 Position */ -#define GPIO_PORT_NOT7_NOTP2_Msk (0x01UL << GPIO_PORT_NOT7_NOTP2_Pos) /*!< GPIO_PORT NOT7: NOTP2 Mask */ -#define GPIO_PORT_NOT7_NOTP3_Pos 3 /*!< GPIO_PORT NOT7: NOTP3 Position */ -#define GPIO_PORT_NOT7_NOTP3_Msk (0x01UL << GPIO_PORT_NOT7_NOTP3_Pos) /*!< GPIO_PORT NOT7: NOTP3 Mask */ -#define GPIO_PORT_NOT7_NOTP4_Pos 4 /*!< GPIO_PORT NOT7: NOTP4 Position */ -#define GPIO_PORT_NOT7_NOTP4_Msk (0x01UL << GPIO_PORT_NOT7_NOTP4_Pos) /*!< GPIO_PORT NOT7: NOTP4 Mask */ -#define GPIO_PORT_NOT7_NOTP5_Pos 5 /*!< GPIO_PORT NOT7: NOTP5 Position */ -#define GPIO_PORT_NOT7_NOTP5_Msk (0x01UL << GPIO_PORT_NOT7_NOTP5_Pos) /*!< GPIO_PORT NOT7: NOTP5 Mask */ -#define GPIO_PORT_NOT7_NOTP6_Pos 6 /*!< GPIO_PORT NOT7: NOTP6 Position */ -#define GPIO_PORT_NOT7_NOTP6_Msk (0x01UL << GPIO_PORT_NOT7_NOTP6_Pos) /*!< GPIO_PORT NOT7: NOTP6 Mask */ -#define GPIO_PORT_NOT7_NOTP7_Pos 7 /*!< GPIO_PORT NOT7: NOTP7 Position */ -#define GPIO_PORT_NOT7_NOTP7_Msk (0x01UL << GPIO_PORT_NOT7_NOTP7_Pos) /*!< GPIO_PORT NOT7: NOTP7 Mask */ -#define GPIO_PORT_NOT7_NOTP8_Pos 8 /*!< GPIO_PORT NOT7: NOTP8 Position */ -#define GPIO_PORT_NOT7_NOTP8_Msk (0x01UL << GPIO_PORT_NOT7_NOTP8_Pos) /*!< GPIO_PORT NOT7: NOTP8 Mask */ -#define GPIO_PORT_NOT7_NOTP9_Pos 9 /*!< GPIO_PORT NOT7: NOTP9 Position */ -#define GPIO_PORT_NOT7_NOTP9_Msk (0x01UL << GPIO_PORT_NOT7_NOTP9_Pos) /*!< GPIO_PORT NOT7: NOTP9 Mask */ -#define GPIO_PORT_NOT7_NOTP10_Pos 10 /*!< GPIO_PORT NOT7: NOTP10 Position */ -#define GPIO_PORT_NOT7_NOTP10_Msk (0x01UL << GPIO_PORT_NOT7_NOTP10_Pos) /*!< GPIO_PORT NOT7: NOTP10 Mask */ -#define GPIO_PORT_NOT7_NOTP11_Pos 11 /*!< GPIO_PORT NOT7: NOTP11 Position */ -#define GPIO_PORT_NOT7_NOTP11_Msk (0x01UL << GPIO_PORT_NOT7_NOTP11_Pos) /*!< GPIO_PORT NOT7: NOTP11 Mask */ -#define GPIO_PORT_NOT7_NOTP12_Pos 12 /*!< GPIO_PORT NOT7: NOTP12 Position */ -#define GPIO_PORT_NOT7_NOTP12_Msk (0x01UL << GPIO_PORT_NOT7_NOTP12_Pos) /*!< GPIO_PORT NOT7: NOTP12 Mask */ -#define GPIO_PORT_NOT7_NOTP13_Pos 13 /*!< GPIO_PORT NOT7: NOTP13 Position */ -#define GPIO_PORT_NOT7_NOTP13_Msk (0x01UL << GPIO_PORT_NOT7_NOTP13_Pos) /*!< GPIO_PORT NOT7: NOTP13 Mask */ -#define GPIO_PORT_NOT7_NOTP14_Pos 14 /*!< GPIO_PORT NOT7: NOTP14 Position */ -#define GPIO_PORT_NOT7_NOTP14_Msk (0x01UL << GPIO_PORT_NOT7_NOTP14_Pos) /*!< GPIO_PORT NOT7: NOTP14 Mask */ -#define GPIO_PORT_NOT7_NOTP15_Pos 15 /*!< GPIO_PORT NOT7: NOTP15 Position */ -#define GPIO_PORT_NOT7_NOTP15_Msk (0x01UL << GPIO_PORT_NOT7_NOTP15_Pos) /*!< GPIO_PORT NOT7: NOTP15 Mask */ -#define GPIO_PORT_NOT7_NOTP16_Pos 16 /*!< GPIO_PORT NOT7: NOTP16 Position */ -#define GPIO_PORT_NOT7_NOTP16_Msk (0x01UL << GPIO_PORT_NOT7_NOTP16_Pos) /*!< GPIO_PORT NOT7: NOTP16 Mask */ -#define GPIO_PORT_NOT7_NOTP17_Pos 17 /*!< GPIO_PORT NOT7: NOTP17 Position */ -#define GPIO_PORT_NOT7_NOTP17_Msk (0x01UL << GPIO_PORT_NOT7_NOTP17_Pos) /*!< GPIO_PORT NOT7: NOTP17 Mask */ -#define GPIO_PORT_NOT7_NOTP18_Pos 18 /*!< GPIO_PORT NOT7: NOTP18 Position */ -#define GPIO_PORT_NOT7_NOTP18_Msk (0x01UL << GPIO_PORT_NOT7_NOTP18_Pos) /*!< GPIO_PORT NOT7: NOTP18 Mask */ -#define GPIO_PORT_NOT7_NOTP19_Pos 19 /*!< GPIO_PORT NOT7: NOTP19 Position */ -#define GPIO_PORT_NOT7_NOTP19_Msk (0x01UL << GPIO_PORT_NOT7_NOTP19_Pos) /*!< GPIO_PORT NOT7: NOTP19 Mask */ -#define GPIO_PORT_NOT7_NOTP20_Pos 20 /*!< GPIO_PORT NOT7: NOTP20 Position */ -#define GPIO_PORT_NOT7_NOTP20_Msk (0x01UL << GPIO_PORT_NOT7_NOTP20_Pos) /*!< GPIO_PORT NOT7: NOTP20 Mask */ -#define GPIO_PORT_NOT7_NOTP21_Pos 21 /*!< GPIO_PORT NOT7: NOTP21 Position */ -#define GPIO_PORT_NOT7_NOTP21_Msk (0x01UL << GPIO_PORT_NOT7_NOTP21_Pos) /*!< GPIO_PORT NOT7: NOTP21 Mask */ -#define GPIO_PORT_NOT7_NOTP22_Pos 22 /*!< GPIO_PORT NOT7: NOTP22 Position */ -#define GPIO_PORT_NOT7_NOTP22_Msk (0x01UL << GPIO_PORT_NOT7_NOTP22_Pos) /*!< GPIO_PORT NOT7: NOTP22 Mask */ -#define GPIO_PORT_NOT7_NOTP23_Pos 23 /*!< GPIO_PORT NOT7: NOTP23 Position */ -#define GPIO_PORT_NOT7_NOTP23_Msk (0x01UL << GPIO_PORT_NOT7_NOTP23_Pos) /*!< GPIO_PORT NOT7: NOTP23 Mask */ -#define GPIO_PORT_NOT7_NOTP24_Pos 24 /*!< GPIO_PORT NOT7: NOTP24 Position */ -#define GPIO_PORT_NOT7_NOTP24_Msk (0x01UL << GPIO_PORT_NOT7_NOTP24_Pos) /*!< GPIO_PORT NOT7: NOTP24 Mask */ -#define GPIO_PORT_NOT7_NOTP25_Pos 25 /*!< GPIO_PORT NOT7: NOTP25 Position */ -#define GPIO_PORT_NOT7_NOTP25_Msk (0x01UL << GPIO_PORT_NOT7_NOTP25_Pos) /*!< GPIO_PORT NOT7: NOTP25 Mask */ -#define GPIO_PORT_NOT7_NOTP26_Pos 26 /*!< GPIO_PORT NOT7: NOTP26 Position */ -#define GPIO_PORT_NOT7_NOTP26_Msk (0x01UL << GPIO_PORT_NOT7_NOTP26_Pos) /*!< GPIO_PORT NOT7: NOTP26 Mask */ -#define GPIO_PORT_NOT7_NOTP27_Pos 27 /*!< GPIO_PORT NOT7: NOTP27 Position */ -#define GPIO_PORT_NOT7_NOTP27_Msk (0x01UL << GPIO_PORT_NOT7_NOTP27_Pos) /*!< GPIO_PORT NOT7: NOTP27 Mask */ -#define GPIO_PORT_NOT7_NOTP28_Pos 28 /*!< GPIO_PORT NOT7: NOTP28 Position */ -#define GPIO_PORT_NOT7_NOTP28_Msk (0x01UL << GPIO_PORT_NOT7_NOTP28_Pos) /*!< GPIO_PORT NOT7: NOTP28 Mask */ -#define GPIO_PORT_NOT7_NOTP29_Pos 29 /*!< GPIO_PORT NOT7: NOTP29 Position */ -#define GPIO_PORT_NOT7_NOTP29_Msk (0x01UL << GPIO_PORT_NOT7_NOTP29_Pos) /*!< GPIO_PORT NOT7: NOTP29 Mask */ -#define GPIO_PORT_NOT7_NOTP30_Pos 30 /*!< GPIO_PORT NOT7: NOTP30 Position */ -#define GPIO_PORT_NOT7_NOTP30_Msk (0x01UL << GPIO_PORT_NOT7_NOTP30_Pos) /*!< GPIO_PORT NOT7: NOTP30 Mask */ -#define GPIO_PORT_NOT7_NOTP31_Pos 31 /*!< GPIO_PORT NOT7: NOTP31 Position */ -#define GPIO_PORT_NOT7_NOTP31_Msk (0x01UL << GPIO_PORT_NOT7_NOTP31_Pos) /*!< GPIO_PORT NOT7: NOTP31 Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- SPI Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ----------------------------------------- SPI_CR --------------------------------------------- -#define SPI_CR_BITENABLE_Pos 2 /*!< SPI CR: BITENABLE Position */ -#define SPI_CR_BITENABLE_Msk (0x01UL << SPI_CR_BITENABLE_Pos) /*!< SPI CR: BITENABLE Mask */ -#define SPI_CR_CPHA_Pos 3 /*!< SPI CR: CPHA Position */ -#define SPI_CR_CPHA_Msk (0x01UL << SPI_CR_CPHA_Pos) /*!< SPI CR: CPHA Mask */ -#define SPI_CR_CPOL_Pos 4 /*!< SPI CR: CPOL Position */ -#define SPI_CR_CPOL_Msk (0x01UL << SPI_CR_CPOL_Pos) /*!< SPI CR: CPOL Mask */ -#define SPI_CR_MSTR_Pos 5 /*!< SPI CR: MSTR Position */ -#define SPI_CR_MSTR_Msk (0x01UL << SPI_CR_MSTR_Pos) /*!< SPI CR: MSTR Mask */ -#define SPI_CR_LSBF_Pos 6 /*!< SPI CR: LSBF Position */ -#define SPI_CR_LSBF_Msk (0x01UL << SPI_CR_LSBF_Pos) /*!< SPI CR: LSBF Mask */ -#define SPI_CR_SPIE_Pos 7 /*!< SPI CR: SPIE Position */ -#define SPI_CR_SPIE_Msk (0x01UL << SPI_CR_SPIE_Pos) /*!< SPI CR: SPIE Mask */ -#define SPI_CR_BITS_Pos 8 /*!< SPI CR: BITS Position */ -#define SPI_CR_BITS_Msk (0x0fUL << SPI_CR_BITS_Pos) /*!< SPI CR: BITS Mask */ - -// ----------------------------------------- SPI_SR --------------------------------------------- -#define SPI_SR_ABRT_Pos 3 /*!< SPI SR: ABRT Position */ -#define SPI_SR_ABRT_Msk (0x01UL << SPI_SR_ABRT_Pos) /*!< SPI SR: ABRT Mask */ -#define SPI_SR_MODF_Pos 4 /*!< SPI SR: MODF Position */ -#define SPI_SR_MODF_Msk (0x01UL << SPI_SR_MODF_Pos) /*!< SPI SR: MODF Mask */ -#define SPI_SR_ROVR_Pos 5 /*!< SPI SR: ROVR Position */ -#define SPI_SR_ROVR_Msk (0x01UL << SPI_SR_ROVR_Pos) /*!< SPI SR: ROVR Mask */ -#define SPI_SR_WCOL_Pos 6 /*!< SPI SR: WCOL Position */ -#define SPI_SR_WCOL_Msk (0x01UL << SPI_SR_WCOL_Pos) /*!< SPI SR: WCOL Mask */ -#define SPI_SR_SPIF_Pos 7 /*!< SPI SR: SPIF Position */ -#define SPI_SR_SPIF_Msk (0x01UL << SPI_SR_SPIF_Pos) /*!< SPI SR: SPIF Mask */ - -// ----------------------------------------- SPI_DR --------------------------------------------- -#define SPI_DR_DATALOW_Pos 0 /*!< SPI DR: DATALOW Position */ -#define SPI_DR_DATALOW_Msk (0x000000ffUL << SPI_DR_DATALOW_Pos) /*!< SPI DR: DATALOW Mask */ -#define SPI_DR_DATAHIGH_Pos 8 /*!< SPI DR: DATAHIGH Position */ -#define SPI_DR_DATAHIGH_Msk (0x000000ffUL << SPI_DR_DATAHIGH_Pos) /*!< SPI DR: DATAHIGH Mask */ - -// ----------------------------------------- SPI_CCR -------------------------------------------- -#define SPI_CCR_COUNTER_Pos 0 /*!< SPI CCR: COUNTER Position */ -#define SPI_CCR_COUNTER_Msk (0x000000ffUL << SPI_CCR_COUNTER_Pos) /*!< SPI CCR: COUNTER Mask */ - -// ----------------------------------------- SPI_TCR -------------------------------------------- -#define SPI_TCR_TEST_Pos 1 /*!< SPI TCR: TEST Position */ -#define SPI_TCR_TEST_Msk (0x7fUL << SPI_TCR_TEST_Pos) /*!< SPI TCR: TEST Mask */ - -// ----------------------------------------- SPI_TSR -------------------------------------------- -#define SPI_TSR_ABRT_Pos 3 /*!< SPI TSR: ABRT Position */ -#define SPI_TSR_ABRT_Msk (0x01UL << SPI_TSR_ABRT_Pos) /*!< SPI TSR: ABRT Mask */ -#define SPI_TSR_MODF_Pos 4 /*!< SPI TSR: MODF Position */ -#define SPI_TSR_MODF_Msk (0x01UL << SPI_TSR_MODF_Pos) /*!< SPI TSR: MODF Mask */ -#define SPI_TSR_ROVR_Pos 5 /*!< SPI TSR: ROVR Position */ -#define SPI_TSR_ROVR_Msk (0x01UL << SPI_TSR_ROVR_Pos) /*!< SPI TSR: ROVR Mask */ -#define SPI_TSR_WCOL_Pos 6 /*!< SPI TSR: WCOL Position */ -#define SPI_TSR_WCOL_Msk (0x01UL << SPI_TSR_WCOL_Pos) /*!< SPI TSR: WCOL Mask */ -#define SPI_TSR_SPIF_Pos 7 /*!< SPI TSR: SPIF Position */ -#define SPI_TSR_SPIF_Msk (0x01UL << SPI_TSR_SPIF_Pos) /*!< SPI TSR: SPIF Mask */ - -// ----------------------------------------- SPI_INT -------------------------------------------- -#define SPI_INT_SPIF_Pos 0 /*!< SPI INT: SPIF Position */ -#define SPI_INT_SPIF_Msk (0x01UL << SPI_INT_SPIF_Pos) /*!< SPI INT: SPIF Mask */ - - -// ------------------------------------------------------------------------------------------------ -// ----- SGPIO Position & Mask ----- -// ------------------------------------------------------------------------------------------------ - - -// ----------------------------------- SGPIO_OUT_MUX_CFG0 --------------------------------------- -#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG0: P_OUT_CFG Position */ -#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG0_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG0: P_OUT_CFG Mask */ -#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG0: P_OE_CFG Position */ -#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG0_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG0: P_OE_CFG Mask */ - -// ----------------------------------- SGPIO_OUT_MUX_CFG1 --------------------------------------- -#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG1: P_OUT_CFG Position */ -#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG1_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG1: P_OUT_CFG Mask */ -#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG1: P_OE_CFG Position */ -#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG1_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG1: P_OE_CFG Mask */ - -// ----------------------------------- SGPIO_OUT_MUX_CFG2 --------------------------------------- -#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG2: P_OUT_CFG Position */ -#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG2_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG2: P_OUT_CFG Mask */ -#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG2: P_OE_CFG Position */ -#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG2_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG2: P_OE_CFG Mask */ - -// ----------------------------------- SGPIO_OUT_MUX_CFG3 --------------------------------------- -#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG3: P_OUT_CFG Position */ -#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG3_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG3: P_OUT_CFG Mask */ -#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG3: P_OE_CFG Position */ -#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG3_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG3: P_OE_CFG Mask */ - -// ----------------------------------- SGPIO_OUT_MUX_CFG4 --------------------------------------- -#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG4: P_OUT_CFG Position */ -#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG4_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG4: P_OUT_CFG Mask */ -#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG4: P_OE_CFG Position */ -#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG4_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG4: P_OE_CFG Mask */ - -// ----------------------------------- SGPIO_OUT_MUX_CFG5 --------------------------------------- -#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG5: P_OUT_CFG Position */ -#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG5_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG5: P_OUT_CFG Mask */ -#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG5: P_OE_CFG Position */ -#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG5_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG5: P_OE_CFG Mask */ - -// ----------------------------------- SGPIO_OUT_MUX_CFG6 --------------------------------------- -#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG6: P_OUT_CFG Position */ -#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG6_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG6: P_OUT_CFG Mask */ -#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG6: P_OE_CFG Position */ -#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG6_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG6: P_OE_CFG Mask */ - -// ----------------------------------- SGPIO_OUT_MUX_CFG7 --------------------------------------- -#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG7: P_OUT_CFG Position */ -#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG7_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG7: P_OUT_CFG Mask */ -#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG7: P_OE_CFG Position */ -#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG7_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG7: P_OE_CFG Mask */ - -// ----------------------------------- SGPIO_OUT_MUX_CFG8 --------------------------------------- -#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG8: P_OUT_CFG Position */ -#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG8_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG8: P_OUT_CFG Mask */ -#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG8: P_OE_CFG Position */ -#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG8_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG8: P_OE_CFG Mask */ - -// ----------------------------------- SGPIO_OUT_MUX_CFG9 --------------------------------------- -#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG9: P_OUT_CFG Position */ -#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG9_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG9: P_OUT_CFG Mask */ -#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG9: P_OE_CFG Position */ -#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG9_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG9: P_OE_CFG Mask */ - -// ----------------------------------- SGPIO_OUT_MUX_CFG10 -------------------------------------- -#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG10: P_OUT_CFG Position */ -#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG10_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG10: P_OUT_CFG Mask */ -#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG10: P_OE_CFG Position */ -#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG10_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG10: P_OE_CFG Mask */ - -// ----------------------------------- SGPIO_OUT_MUX_CFG11 -------------------------------------- -#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG11: P_OUT_CFG Position */ -#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG11_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG11: P_OUT_CFG Mask */ -#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG11: P_OE_CFG Position */ -#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG11_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG11: P_OE_CFG Mask */ - -// ----------------------------------- SGPIO_OUT_MUX_CFG12 -------------------------------------- -#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG12: P_OUT_CFG Position */ -#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG12_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG12: P_OUT_CFG Mask */ -#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG12: P_OE_CFG Position */ -#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG12_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG12: P_OE_CFG Mask */ - -// ----------------------------------- SGPIO_OUT_MUX_CFG13 -------------------------------------- -#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG13: P_OUT_CFG Position */ -#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG13_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG13: P_OUT_CFG Mask */ -#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG13: P_OE_CFG Position */ -#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG13_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG13: P_OE_CFG Mask */ - -// ----------------------------------- SGPIO_OUT_MUX_CFG14 -------------------------------------- -#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG14: P_OUT_CFG Position */ -#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG14_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG14: P_OUT_CFG Mask */ -#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG14: P_OE_CFG Position */ -#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG14_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG14: P_OE_CFG Mask */ - -// ----------------------------------- SGPIO_OUT_MUX_CFG15 -------------------------------------- -#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG15: P_OUT_CFG Position */ -#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG15_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG15: P_OUT_CFG Mask */ -#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG15: P_OE_CFG Position */ -#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG15_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG15: P_OE_CFG Mask */ - -// ---------------------------------- SGPIO_SGPIO_MUX_CFG0 -------------------------------------- -#define SGPIO_SGPIO_MUX_CFG0_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG0: EXT_CLK_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG0_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG0_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG0: EXT_CLK_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG0: CLK_SOURCE_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG0_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG0: QUALIFIER_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG0_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ORDER Position */ -#define SGPIO_SGPIO_MUX_CFG0_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG0_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG0: CONCAT_ORDER Mask */ - -// ---------------------------------- SGPIO_SGPIO_MUX_CFG1 -------------------------------------- -#define SGPIO_SGPIO_MUX_CFG1_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG1: EXT_CLK_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG1_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG1_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG1: EXT_CLK_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG1: CLK_SOURCE_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG1_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG1: QUALIFIER_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG1_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ORDER Position */ -#define SGPIO_SGPIO_MUX_CFG1_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG1_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG1: CONCAT_ORDER Mask */ - -// ---------------------------------- SGPIO_SGPIO_MUX_CFG2 -------------------------------------- -#define SGPIO_SGPIO_MUX_CFG2_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG2: EXT_CLK_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG2_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG2_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG2: EXT_CLK_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG2: CLK_SOURCE_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG2_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG2: QUALIFIER_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG2_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ORDER Position */ -#define SGPIO_SGPIO_MUX_CFG2_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG2_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG2: CONCAT_ORDER Mask */ - -// ---------------------------------- SGPIO_SGPIO_MUX_CFG3 -------------------------------------- -#define SGPIO_SGPIO_MUX_CFG3_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG3: EXT_CLK_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG3_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG3_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG3: EXT_CLK_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG3: CLK_SOURCE_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG3_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG3: QUALIFIER_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG3_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ORDER Position */ -#define SGPIO_SGPIO_MUX_CFG3_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG3_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG3: CONCAT_ORDER Mask */ - -// ---------------------------------- SGPIO_SGPIO_MUX_CFG4 -------------------------------------- -#define SGPIO_SGPIO_MUX_CFG4_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG4: EXT_CLK_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG4_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG4_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG4: EXT_CLK_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG4: CLK_SOURCE_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG4_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG4: QUALIFIER_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG4_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ORDER Position */ -#define SGPIO_SGPIO_MUX_CFG4_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG4_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG4: CONCAT_ORDER Mask */ - -// ---------------------------------- SGPIO_SGPIO_MUX_CFG5 -------------------------------------- -#define SGPIO_SGPIO_MUX_CFG5_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG5: EXT_CLK_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG5_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG5_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG5: EXT_CLK_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG5: CLK_SOURCE_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG5_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG5: QUALIFIER_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG5_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ORDER Position */ -#define SGPIO_SGPIO_MUX_CFG5_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG5_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG5: CONCAT_ORDER Mask */ - -// ---------------------------------- SGPIO_SGPIO_MUX_CFG6 -------------------------------------- -#define SGPIO_SGPIO_MUX_CFG6_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG6: EXT_CLK_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG6_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG6_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG6: EXT_CLK_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG6: CLK_SOURCE_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG6_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG6: QUALIFIER_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG6_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ORDER Position */ -#define SGPIO_SGPIO_MUX_CFG6_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG6_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG6: CONCAT_ORDER Mask */ - -// ---------------------------------- SGPIO_SGPIO_MUX_CFG7 -------------------------------------- -#define SGPIO_SGPIO_MUX_CFG7_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG7: EXT_CLK_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG7_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG7_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG7: EXT_CLK_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG7: CLK_SOURCE_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG7_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG7: QUALIFIER_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG7_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ORDER Position */ -#define SGPIO_SGPIO_MUX_CFG7_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG7_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG7: CONCAT_ORDER Mask */ - -// ---------------------------------- SGPIO_SGPIO_MUX_CFG8 -------------------------------------- -#define SGPIO_SGPIO_MUX_CFG8_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG8: EXT_CLK_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG8_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG8_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG8: EXT_CLK_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG8: CLK_SOURCE_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG8_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG8: QUALIFIER_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG8_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ORDER Position */ -#define SGPIO_SGPIO_MUX_CFG8_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG8_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG8: CONCAT_ORDER Mask */ - -// ---------------------------------- SGPIO_SGPIO_MUX_CFG9 -------------------------------------- -#define SGPIO_SGPIO_MUX_CFG9_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG9: EXT_CLK_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG9_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG9_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG9: EXT_CLK_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG9: CLK_SOURCE_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG9_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG9: QUALIFIER_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG9_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ORDER Position */ -#define SGPIO_SGPIO_MUX_CFG9_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG9_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG9: CONCAT_ORDER Mask */ - -// ---------------------------------- SGPIO_SGPIO_MUX_CFG10 ------------------------------------- -#define SGPIO_SGPIO_MUX_CFG10_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG10: EXT_CLK_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG10_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG10_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG10: EXT_CLK_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG10: CLK_SOURCE_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG10_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG10: QUALIFIER_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG10_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ORDER Position */ -#define SGPIO_SGPIO_MUX_CFG10_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG10_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG10: CONCAT_ORDER Mask */ - -// ---------------------------------- SGPIO_SGPIO_MUX_CFG11 ------------------------------------- -#define SGPIO_SGPIO_MUX_CFG11_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG11: EXT_CLK_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG11_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG11_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG11: EXT_CLK_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG11: CLK_SOURCE_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG11_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG11: QUALIFIER_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG11_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ORDER Position */ -#define SGPIO_SGPIO_MUX_CFG11_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG11_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG11: CONCAT_ORDER Mask */ - -// ---------------------------------- SGPIO_SGPIO_MUX_CFG12 ------------------------------------- -#define SGPIO_SGPIO_MUX_CFG12_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG12: EXT_CLK_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG12_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG12_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG12: EXT_CLK_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG12: CLK_SOURCE_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG12_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG12: QUALIFIER_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG12_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ORDER Position */ -#define SGPIO_SGPIO_MUX_CFG12_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG12_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG12: CONCAT_ORDER Mask */ - -// ---------------------------------- SGPIO_SGPIO_MUX_CFG13 ------------------------------------- -#define SGPIO_SGPIO_MUX_CFG13_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG13: EXT_CLK_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG13_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG13_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG13: EXT_CLK_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG13: CLK_SOURCE_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG13_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG13: QUALIFIER_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG13_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ORDER Position */ -#define SGPIO_SGPIO_MUX_CFG13_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG13_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG13: CONCAT_ORDER Mask */ - -// ---------------------------------- SGPIO_SGPIO_MUX_CFG14 ------------------------------------- -#define SGPIO_SGPIO_MUX_CFG14_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG14: EXT_CLK_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG14_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG14_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG14: EXT_CLK_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG14: CLK_SOURCE_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG14_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG14: QUALIFIER_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG14_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ORDER Position */ -#define SGPIO_SGPIO_MUX_CFG14_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG14_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG14: CONCAT_ORDER Mask */ - -// ---------------------------------- SGPIO_SGPIO_MUX_CFG15 ------------------------------------- -#define SGPIO_SGPIO_MUX_CFG15_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG15: EXT_CLK_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG15_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG15_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG15: EXT_CLK_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG15: CLK_SOURCE_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG15_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_PIN_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_PIN_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_SLICE_MODE Position */ -#define SGPIO_SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG15: QUALIFIER_SLICE_MODE Mask */ -#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ENABLE Position */ -#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG15_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ENABLE Mask */ -#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ORDER Position */ -#define SGPIO_SGPIO_MUX_CFG15_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG15_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG15: CONCAT_ORDER Mask */ - -// ---------------------------------- SGPIO_SLICE_MUX_CFG0 -------------------------------------- -#define SGPIO_SLICE_MUX_CFG0_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG0: MATCH_MODE Position */ -#define SGPIO_SLICE_MUX_CFG0_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG0_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG0: MATCH_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG0: CLK_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG0: CLK_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG0: CLKGEN_MODE Position */ -#define SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG0: CLKGEN_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG0: INV_OUT_CLK Position */ -#define SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG0: INV_OUT_CLK Mask */ -#define SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG0: DATA_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG0: DATA_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG0: PARALLEL_MODE Position */ -#define SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG0: PARALLEL_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG0: INV_QUALIFIER Position */ -#define SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG0: INV_QUALIFIER Mask */ - -// ---------------------------------- SGPIO_SLICE_MUX_CFG1 -------------------------------------- -#define SGPIO_SLICE_MUX_CFG1_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG1: MATCH_MODE Position */ -#define SGPIO_SLICE_MUX_CFG1_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG1_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG1: MATCH_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG1: CLK_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG1: CLK_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG1: CLKGEN_MODE Position */ -#define SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG1: CLKGEN_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG1: INV_OUT_CLK Position */ -#define SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG1: INV_OUT_CLK Mask */ -#define SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG1: DATA_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG1: DATA_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG1: PARALLEL_MODE Position */ -#define SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG1: PARALLEL_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG1: INV_QUALIFIER Position */ -#define SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG1: INV_QUALIFIER Mask */ - -// ---------------------------------- SGPIO_SLICE_MUX_CFG2 -------------------------------------- -#define SGPIO_SLICE_MUX_CFG2_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG2: MATCH_MODE Position */ -#define SGPIO_SLICE_MUX_CFG2_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG2_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG2: MATCH_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG2: CLK_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG2: CLK_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG2: CLKGEN_MODE Position */ -#define SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG2: CLKGEN_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG2: INV_OUT_CLK Position */ -#define SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG2: INV_OUT_CLK Mask */ -#define SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG2: DATA_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG2: DATA_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG2: PARALLEL_MODE Position */ -#define SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG2: PARALLEL_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG2: INV_QUALIFIER Position */ -#define SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG2: INV_QUALIFIER Mask */ - -// ---------------------------------- SGPIO_SLICE_MUX_CFG3 -------------------------------------- -#define SGPIO_SLICE_MUX_CFG3_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG3: MATCH_MODE Position */ -#define SGPIO_SLICE_MUX_CFG3_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG3_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG3: MATCH_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG3: CLK_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG3: CLK_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG3: CLKGEN_MODE Position */ -#define SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG3: CLKGEN_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG3: INV_OUT_CLK Position */ -#define SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG3: INV_OUT_CLK Mask */ -#define SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG3: DATA_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG3: DATA_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG3: PARALLEL_MODE Position */ -#define SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG3: PARALLEL_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG3: INV_QUALIFIER Position */ -#define SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG3: INV_QUALIFIER Mask */ - -// ---------------------------------- SGPIO_SLICE_MUX_CFG4 -------------------------------------- -#define SGPIO_SLICE_MUX_CFG4_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG4: MATCH_MODE Position */ -#define SGPIO_SLICE_MUX_CFG4_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG4_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG4: MATCH_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG4: CLK_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG4: CLK_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG4: CLKGEN_MODE Position */ -#define SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG4: CLKGEN_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG4: INV_OUT_CLK Position */ -#define SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG4: INV_OUT_CLK Mask */ -#define SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG4: DATA_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG4: DATA_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG4: PARALLEL_MODE Position */ -#define SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG4: PARALLEL_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG4: INV_QUALIFIER Position */ -#define SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG4: INV_QUALIFIER Mask */ - -// ---------------------------------- SGPIO_SLICE_MUX_CFG5 -------------------------------------- -#define SGPIO_SLICE_MUX_CFG5_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG5: MATCH_MODE Position */ -#define SGPIO_SLICE_MUX_CFG5_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG5_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG5: MATCH_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG5: CLK_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG5: CLK_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG5: CLKGEN_MODE Position */ -#define SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG5: CLKGEN_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG5: INV_OUT_CLK Position */ -#define SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG5: INV_OUT_CLK Mask */ -#define SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG5: DATA_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG5: DATA_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG5: PARALLEL_MODE Position */ -#define SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG5: PARALLEL_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG5: INV_QUALIFIER Position */ -#define SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG5: INV_QUALIFIER Mask */ - -// ---------------------------------- SGPIO_SLICE_MUX_CFG6 -------------------------------------- -#define SGPIO_SLICE_MUX_CFG6_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG6: MATCH_MODE Position */ -#define SGPIO_SLICE_MUX_CFG6_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG6_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG6: MATCH_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG6: CLK_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG6: CLK_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG6: CLKGEN_MODE Position */ -#define SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG6: CLKGEN_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG6: INV_OUT_CLK Position */ -#define SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG6: INV_OUT_CLK Mask */ -#define SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG6: DATA_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG6: DATA_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG6: PARALLEL_MODE Position */ -#define SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG6: PARALLEL_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG6: INV_QUALIFIER Position */ -#define SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG6: INV_QUALIFIER Mask */ - -// ---------------------------------- SGPIO_SLICE_MUX_CFG7 -------------------------------------- -#define SGPIO_SLICE_MUX_CFG7_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG7: MATCH_MODE Position */ -#define SGPIO_SLICE_MUX_CFG7_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG7_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG7: MATCH_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG7: CLK_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG7: CLK_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG7: CLKGEN_MODE Position */ -#define SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG7: CLKGEN_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG7: INV_OUT_CLK Position */ -#define SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG7: INV_OUT_CLK Mask */ -#define SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG7: DATA_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG7: DATA_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG7: PARALLEL_MODE Position */ -#define SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG7: PARALLEL_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG7: INV_QUALIFIER Position */ -#define SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG7: INV_QUALIFIER Mask */ - -// ---------------------------------- SGPIO_SLICE_MUX_CFG8 -------------------------------------- -#define SGPIO_SLICE_MUX_CFG8_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG8: MATCH_MODE Position */ -#define SGPIO_SLICE_MUX_CFG8_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG8_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG8: MATCH_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG8: CLK_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG8: CLK_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG8: CLKGEN_MODE Position */ -#define SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG8: CLKGEN_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG8: INV_OUT_CLK Position */ -#define SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG8: INV_OUT_CLK Mask */ -#define SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG8: DATA_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG8: DATA_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG8: PARALLEL_MODE Position */ -#define SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG8: PARALLEL_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG8: INV_QUALIFIER Position */ -#define SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG8: INV_QUALIFIER Mask */ - -// ---------------------------------- SGPIO_SLICE_MUX_CFG9 -------------------------------------- -#define SGPIO_SLICE_MUX_CFG9_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG9: MATCH_MODE Position */ -#define SGPIO_SLICE_MUX_CFG9_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG9_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG9: MATCH_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG9: CLK_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG9: CLK_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG9: CLKGEN_MODE Position */ -#define SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG9: CLKGEN_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG9: INV_OUT_CLK Position */ -#define SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG9: INV_OUT_CLK Mask */ -#define SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG9: DATA_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG9: DATA_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG9: PARALLEL_MODE Position */ -#define SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG9: PARALLEL_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG9: INV_QUALIFIER Position */ -#define SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG9: INV_QUALIFIER Mask */ - -// ---------------------------------- SGPIO_SLICE_MUX_CFG10 ------------------------------------- -#define SGPIO_SLICE_MUX_CFG10_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG10: MATCH_MODE Position */ -#define SGPIO_SLICE_MUX_CFG10_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG10_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG10: MATCH_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG10: CLK_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG10: CLK_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG10: CLKGEN_MODE Position */ -#define SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG10: CLKGEN_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG10: INV_OUT_CLK Position */ -#define SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG10: INV_OUT_CLK Mask */ -#define SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG10: DATA_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG10: DATA_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG10: PARALLEL_MODE Position */ -#define SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG10: PARALLEL_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG10: INV_QUALIFIER Position */ -#define SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG10: INV_QUALIFIER Mask */ - -// ---------------------------------- SGPIO_SLICE_MUX_CFG11 ------------------------------------- -#define SGPIO_SLICE_MUX_CFG11_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG11: MATCH_MODE Position */ -#define SGPIO_SLICE_MUX_CFG11_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG11_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG11: MATCH_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG11: CLK_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG11: CLK_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG11: CLKGEN_MODE Position */ -#define SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG11: CLKGEN_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG11: INV_OUT_CLK Position */ -#define SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG11: INV_OUT_CLK Mask */ -#define SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG11: DATA_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG11: DATA_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG11: PARALLEL_MODE Position */ -#define SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG11: PARALLEL_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG11: INV_QUALIFIER Position */ -#define SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG11: INV_QUALIFIER Mask */ - -// ---------------------------------- SGPIO_SLICE_MUX_CFG12 ------------------------------------- -#define SGPIO_SLICE_MUX_CFG12_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG12: MATCH_MODE Position */ -#define SGPIO_SLICE_MUX_CFG12_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG12_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG12: MATCH_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG12: CLK_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG12: CLK_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG12: CLKGEN_MODE Position */ -#define SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG12: CLKGEN_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG12: INV_OUT_CLK Position */ -#define SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG12: INV_OUT_CLK Mask */ -#define SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG12: DATA_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG12: DATA_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG12: PARALLEL_MODE Position */ -#define SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG12: PARALLEL_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG12: INV_QUALIFIER Position */ -#define SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG12: INV_QUALIFIER Mask */ - -// ---------------------------------- SGPIO_SLICE_MUX_CFG13 ------------------------------------- -#define SGPIO_SLICE_MUX_CFG13_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG13: MATCH_MODE Position */ -#define SGPIO_SLICE_MUX_CFG13_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG13_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG13: MATCH_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG13: CLK_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG13: CLK_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG13: CLKGEN_MODE Position */ -#define SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG13: CLKGEN_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG13: INV_OUT_CLK Position */ -#define SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG13: INV_OUT_CLK Mask */ -#define SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG13: DATA_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG13: DATA_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG13: PARALLEL_MODE Position */ -#define SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG13: PARALLEL_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG13: INV_QUALIFIER Position */ -#define SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG13: INV_QUALIFIER Mask */ - -// ---------------------------------- SGPIO_SLICE_MUX_CFG14 ------------------------------------- -#define SGPIO_SLICE_MUX_CFG14_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG14: MATCH_MODE Position */ -#define SGPIO_SLICE_MUX_CFG14_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG14_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG14: MATCH_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG14: CLK_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG14: CLK_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG14: CLKGEN_MODE Position */ -#define SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG14: CLKGEN_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG14: INV_OUT_CLK Position */ -#define SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG14: INV_OUT_CLK Mask */ -#define SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG14: DATA_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG14: DATA_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG14: PARALLEL_MODE Position */ -#define SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG14: PARALLEL_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG14: INV_QUALIFIER Position */ -#define SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG14: INV_QUALIFIER Mask */ - -// ---------------------------------- SGPIO_SLICE_MUX_CFG15 ------------------------------------- -#define SGPIO_SLICE_MUX_CFG15_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG15: MATCH_MODE Position */ -#define SGPIO_SLICE_MUX_CFG15_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG15_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG15: MATCH_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG15: CLK_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG15: CLK_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG15: CLKGEN_MODE Position */ -#define SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG15: CLKGEN_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG15: INV_OUT_CLK Position */ -#define SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG15: INV_OUT_CLK Mask */ -#define SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG15: DATA_CAPTURE_MODE Position */ -#define SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG15: DATA_CAPTURE_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG15: PARALLEL_MODE Position */ -#define SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG15: PARALLEL_MODE Mask */ -#define SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG15: INV_QUALIFIER Position */ -#define SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG15: INV_QUALIFIER Mask */ - -// --------------------------------------- SGPIO_REG0 ------------------------------------------- -#define SGPIO_REG0_REG_Pos 0 /*!< SGPIO REG0: REG Position */ -#define SGPIO_REG0_REG_Msk (0xffffffffUL << SGPIO_REG0_REG_Pos) /*!< SGPIO REG0: REG Mask */ - -// --------------------------------------- SGPIO_REG1 ------------------------------------------- -#define SGPIO_REG1_REG_Pos 0 /*!< SGPIO REG1: REG Position */ -#define SGPIO_REG1_REG_Msk (0xffffffffUL << SGPIO_REG1_REG_Pos) /*!< SGPIO REG1: REG Mask */ - -// --------------------------------------- SGPIO_REG2 ------------------------------------------- -#define SGPIO_REG2_REG_Pos 0 /*!< SGPIO REG2: REG Position */ -#define SGPIO_REG2_REG_Msk (0xffffffffUL << SGPIO_REG2_REG_Pos) /*!< SGPIO REG2: REG Mask */ - -// --------------------------------------- SGPIO_REG3 ------------------------------------------- -#define SGPIO_REG3_REG_Pos 0 /*!< SGPIO REG3: REG Position */ -#define SGPIO_REG3_REG_Msk (0xffffffffUL << SGPIO_REG3_REG_Pos) /*!< SGPIO REG3: REG Mask */ - -// --------------------------------------- SGPIO_REG4 ------------------------------------------- -#define SGPIO_REG4_REG_Pos 0 /*!< SGPIO REG4: REG Position */ -#define SGPIO_REG4_REG_Msk (0xffffffffUL << SGPIO_REG4_REG_Pos) /*!< SGPIO REG4: REG Mask */ - -// --------------------------------------- SGPIO_REG5 ------------------------------------------- -#define SGPIO_REG5_REG_Pos 0 /*!< SGPIO REG5: REG Position */ -#define SGPIO_REG5_REG_Msk (0xffffffffUL << SGPIO_REG5_REG_Pos) /*!< SGPIO REG5: REG Mask */ - -// --------------------------------------- SGPIO_REG6 ------------------------------------------- -#define SGPIO_REG6_REG_Pos 0 /*!< SGPIO REG6: REG Position */ -#define SGPIO_REG6_REG_Msk (0xffffffffUL << SGPIO_REG6_REG_Pos) /*!< SGPIO REG6: REG Mask */ - -// --------------------------------------- SGPIO_REG7 ------------------------------------------- -#define SGPIO_REG7_REG_Pos 0 /*!< SGPIO REG7: REG Position */ -#define SGPIO_REG7_REG_Msk (0xffffffffUL << SGPIO_REG7_REG_Pos) /*!< SGPIO REG7: REG Mask */ - -// --------------------------------------- SGPIO_REG8 ------------------------------------------- -#define SGPIO_REG8_REG_Pos 0 /*!< SGPIO REG8: REG Position */ -#define SGPIO_REG8_REG_Msk (0xffffffffUL << SGPIO_REG8_REG_Pos) /*!< SGPIO REG8: REG Mask */ - -// --------------------------------------- SGPIO_REG9 ------------------------------------------- -#define SGPIO_REG9_REG_Pos 0 /*!< SGPIO REG9: REG Position */ -#define SGPIO_REG9_REG_Msk (0xffffffffUL << SGPIO_REG9_REG_Pos) /*!< SGPIO REG9: REG Mask */ - -// --------------------------------------- SGPIO_REG10 ------------------------------------------ -#define SGPIO_REG10_REG_Pos 0 /*!< SGPIO REG10: REG Position */ -#define SGPIO_REG10_REG_Msk (0xffffffffUL << SGPIO_REG10_REG_Pos) /*!< SGPIO REG10: REG Mask */ - -// --------------------------------------- SGPIO_REG11 ------------------------------------------ -#define SGPIO_REG11_REG_Pos 0 /*!< SGPIO REG11: REG Position */ -#define SGPIO_REG11_REG_Msk (0xffffffffUL << SGPIO_REG11_REG_Pos) /*!< SGPIO REG11: REG Mask */ - -// --------------------------------------- SGPIO_REG12 ------------------------------------------ -#define SGPIO_REG12_REG_Pos 0 /*!< SGPIO REG12: REG Position */ -#define SGPIO_REG12_REG_Msk (0xffffffffUL << SGPIO_REG12_REG_Pos) /*!< SGPIO REG12: REG Mask */ - -// --------------------------------------- SGPIO_REG13 ------------------------------------------ -#define SGPIO_REG13_REG_Pos 0 /*!< SGPIO REG13: REG Position */ -#define SGPIO_REG13_REG_Msk (0xffffffffUL << SGPIO_REG13_REG_Pos) /*!< SGPIO REG13: REG Mask */ - -// --------------------------------------- SGPIO_REG14 ------------------------------------------ -#define SGPIO_REG14_REG_Pos 0 /*!< SGPIO REG14: REG Position */ -#define SGPIO_REG14_REG_Msk (0xffffffffUL << SGPIO_REG14_REG_Pos) /*!< SGPIO REG14: REG Mask */ - -// --------------------------------------- SGPIO_REG15 ------------------------------------------ -#define SGPIO_REG15_REG_Pos 0 /*!< SGPIO REG15: REG Position */ -#define SGPIO_REG15_REG_Msk (0xffffffffUL << SGPIO_REG15_REG_Pos) /*!< SGPIO REG15: REG Mask */ - -// -------------------------------------- SGPIO_REG_SS0 ----------------------------------------- -#define SGPIO_REG_SS0_REG_SS_Pos 0 /*!< SGPIO REG_SS0: REG_SS Position */ -#define SGPIO_REG_SS0_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS0_REG_SS_Pos) /*!< SGPIO REG_SS0: REG_SS Mask */ - -// -------------------------------------- SGPIO_REG_SS1 ----------------------------------------- -#define SGPIO_REG_SS1_REG_SS_Pos 0 /*!< SGPIO REG_SS1: REG_SS Position */ -#define SGPIO_REG_SS1_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS1_REG_SS_Pos) /*!< SGPIO REG_SS1: REG_SS Mask */ - -// -------------------------------------- SGPIO_REG_SS2 ----------------------------------------- -#define SGPIO_REG_SS2_REG_SS_Pos 0 /*!< SGPIO REG_SS2: REG_SS Position */ -#define SGPIO_REG_SS2_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS2_REG_SS_Pos) /*!< SGPIO REG_SS2: REG_SS Mask */ - -// -------------------------------------- SGPIO_REG_SS3 ----------------------------------------- -#define SGPIO_REG_SS3_REG_SS_Pos 0 /*!< SGPIO REG_SS3: REG_SS Position */ -#define SGPIO_REG_SS3_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS3_REG_SS_Pos) /*!< SGPIO REG_SS3: REG_SS Mask */ - -// -------------------------------------- SGPIO_REG_SS4 ----------------------------------------- -#define SGPIO_REG_SS4_REG_SS_Pos 0 /*!< SGPIO REG_SS4: REG_SS Position */ -#define SGPIO_REG_SS4_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS4_REG_SS_Pos) /*!< SGPIO REG_SS4: REG_SS Mask */ - -// -------------------------------------- SGPIO_REG_SS5 ----------------------------------------- -#define SGPIO_REG_SS5_REG_SS_Pos 0 /*!< SGPIO REG_SS5: REG_SS Position */ -#define SGPIO_REG_SS5_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS5_REG_SS_Pos) /*!< SGPIO REG_SS5: REG_SS Mask */ - -// -------------------------------------- SGPIO_REG_SS6 ----------------------------------------- -#define SGPIO_REG_SS6_REG_SS_Pos 0 /*!< SGPIO REG_SS6: REG_SS Position */ -#define SGPIO_REG_SS6_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS6_REG_SS_Pos) /*!< SGPIO REG_SS6: REG_SS Mask */ - -// -------------------------------------- SGPIO_REG_SS7 ----------------------------------------- -#define SGPIO_REG_SS7_REG_SS_Pos 0 /*!< SGPIO REG_SS7: REG_SS Position */ -#define SGPIO_REG_SS7_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS7_REG_SS_Pos) /*!< SGPIO REG_SS7: REG_SS Mask */ - -// -------------------------------------- SGPIO_REG_SS8 ----------------------------------------- -#define SGPIO_REG_SS8_REG_SS_Pos 0 /*!< SGPIO REG_SS8: REG_SS Position */ -#define SGPIO_REG_SS8_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS8_REG_SS_Pos) /*!< SGPIO REG_SS8: REG_SS Mask */ - -// -------------------------------------- SGPIO_REG_SS9 ----------------------------------------- -#define SGPIO_REG_SS9_REG_SS_Pos 0 /*!< SGPIO REG_SS9: REG_SS Position */ -#define SGPIO_REG_SS9_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS9_REG_SS_Pos) /*!< SGPIO REG_SS9: REG_SS Mask */ - -// ------------------------------------- SGPIO_REG_SS10 ----------------------------------------- -#define SGPIO_REG_SS10_REG_SS_Pos 0 /*!< SGPIO REG_SS10: REG_SS Position */ -#define SGPIO_REG_SS10_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS10_REG_SS_Pos) /*!< SGPIO REG_SS10: REG_SS Mask */ - -// ------------------------------------- SGPIO_REG_SS11 ----------------------------------------- -#define SGPIO_REG_SS11_REG_SS_Pos 0 /*!< SGPIO REG_SS11: REG_SS Position */ -#define SGPIO_REG_SS11_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS11_REG_SS_Pos) /*!< SGPIO REG_SS11: REG_SS Mask */ - -// ------------------------------------- SGPIO_REG_SS12 ----------------------------------------- -#define SGPIO_REG_SS12_REG_SS_Pos 0 /*!< SGPIO REG_SS12: REG_SS Position */ -#define SGPIO_REG_SS12_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS12_REG_SS_Pos) /*!< SGPIO REG_SS12: REG_SS Mask */ - -// ------------------------------------- SGPIO_REG_SS13 ----------------------------------------- -#define SGPIO_REG_SS13_REG_SS_Pos 0 /*!< SGPIO REG_SS13: REG_SS Position */ -#define SGPIO_REG_SS13_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS13_REG_SS_Pos) /*!< SGPIO REG_SS13: REG_SS Mask */ - -// ------------------------------------- SGPIO_REG_SS14 ----------------------------------------- -#define SGPIO_REG_SS14_REG_SS_Pos 0 /*!< SGPIO REG_SS14: REG_SS Position */ -#define SGPIO_REG_SS14_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS14_REG_SS_Pos) /*!< SGPIO REG_SS14: REG_SS Mask */ - -// ------------------------------------- SGPIO_REG_SS15 ----------------------------------------- -#define SGPIO_REG_SS15_REG_SS_Pos 0 /*!< SGPIO REG_SS15: REG_SS Position */ -#define SGPIO_REG_SS15_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS15_REG_SS_Pos) /*!< SGPIO REG_SS15: REG_SS Mask */ - -// -------------------------------------- SGPIO_PRESET0 ----------------------------------------- -#define SGPIO_PRESET0_PRESET_Pos 0 /*!< SGPIO PRESET0: PRESET Position */ -#define SGPIO_PRESET0_PRESET_Msk (0x00000fffUL << SGPIO_PRESET0_PRESET_Pos) /*!< SGPIO PRESET0: PRESET Mask */ - -// -------------------------------------- SGPIO_PRESET1 ----------------------------------------- -#define SGPIO_PRESET1_PRESET_Pos 0 /*!< SGPIO PRESET1: PRESET Position */ -#define SGPIO_PRESET1_PRESET_Msk (0x00000fffUL << SGPIO_PRESET1_PRESET_Pos) /*!< SGPIO PRESET1: PRESET Mask */ - -// -------------------------------------- SGPIO_PRESET2 ----------------------------------------- -#define SGPIO_PRESET2_PRESET_Pos 0 /*!< SGPIO PRESET2: PRESET Position */ -#define SGPIO_PRESET2_PRESET_Msk (0x00000fffUL << SGPIO_PRESET2_PRESET_Pos) /*!< SGPIO PRESET2: PRESET Mask */ - -// -------------------------------------- SGPIO_PRESET3 ----------------------------------------- -#define SGPIO_PRESET3_PRESET_Pos 0 /*!< SGPIO PRESET3: PRESET Position */ -#define SGPIO_PRESET3_PRESET_Msk (0x00000fffUL << SGPIO_PRESET3_PRESET_Pos) /*!< SGPIO PRESET3: PRESET Mask */ - -// -------------------------------------- SGPIO_PRESET4 ----------------------------------------- -#define SGPIO_PRESET4_PRESET_Pos 0 /*!< SGPIO PRESET4: PRESET Position */ -#define SGPIO_PRESET4_PRESET_Msk (0x00000fffUL << SGPIO_PRESET4_PRESET_Pos) /*!< SGPIO PRESET4: PRESET Mask */ - -// -------------------------------------- SGPIO_PRESET5 ----------------------------------------- -#define SGPIO_PRESET5_PRESET_Pos 0 /*!< SGPIO PRESET5: PRESET Position */ -#define SGPIO_PRESET5_PRESET_Msk (0x00000fffUL << SGPIO_PRESET5_PRESET_Pos) /*!< SGPIO PRESET5: PRESET Mask */ - -// -------------------------------------- SGPIO_PRESET6 ----------------------------------------- -#define SGPIO_PRESET6_PRESET_Pos 0 /*!< SGPIO PRESET6: PRESET Position */ -#define SGPIO_PRESET6_PRESET_Msk (0x00000fffUL << SGPIO_PRESET6_PRESET_Pos) /*!< SGPIO PRESET6: PRESET Mask */ - -// -------------------------------------- SGPIO_PRESET7 ----------------------------------------- -#define SGPIO_PRESET7_PRESET_Pos 0 /*!< SGPIO PRESET7: PRESET Position */ -#define SGPIO_PRESET7_PRESET_Msk (0x00000fffUL << SGPIO_PRESET7_PRESET_Pos) /*!< SGPIO PRESET7: PRESET Mask */ - -// -------------------------------------- SGPIO_PRESET8 ----------------------------------------- -#define SGPIO_PRESET8_PRESET_Pos 0 /*!< SGPIO PRESET8: PRESET Position */ -#define SGPIO_PRESET8_PRESET_Msk (0x00000fffUL << SGPIO_PRESET8_PRESET_Pos) /*!< SGPIO PRESET8: PRESET Mask */ - -// -------------------------------------- SGPIO_PRESET9 ----------------------------------------- -#define SGPIO_PRESET9_PRESET_Pos 0 /*!< SGPIO PRESET9: PRESET Position */ -#define SGPIO_PRESET9_PRESET_Msk (0x00000fffUL << SGPIO_PRESET9_PRESET_Pos) /*!< SGPIO PRESET9: PRESET Mask */ - -// ------------------------------------- SGPIO_PRESET10 ----------------------------------------- -#define SGPIO_PRESET10_PRESET_Pos 0 /*!< SGPIO PRESET10: PRESET Position */ -#define SGPIO_PRESET10_PRESET_Msk (0x00000fffUL << SGPIO_PRESET10_PRESET_Pos) /*!< SGPIO PRESET10: PRESET Mask */ - -// ------------------------------------- SGPIO_PRESET11 ----------------------------------------- -#define SGPIO_PRESET11_PRESET_Pos 0 /*!< SGPIO PRESET11: PRESET Position */ -#define SGPIO_PRESET11_PRESET_Msk (0x00000fffUL << SGPIO_PRESET11_PRESET_Pos) /*!< SGPIO PRESET11: PRESET Mask */ - -// ------------------------------------- SGPIO_PRESET12 ----------------------------------------- -#define SGPIO_PRESET12_PRESET_Pos 0 /*!< SGPIO PRESET12: PRESET Position */ -#define SGPIO_PRESET12_PRESET_Msk (0x00000fffUL << SGPIO_PRESET12_PRESET_Pos) /*!< SGPIO PRESET12: PRESET Mask */ - -// ------------------------------------- SGPIO_PRESET13 ----------------------------------------- -#define SGPIO_PRESET13_PRESET_Pos 0 /*!< SGPIO PRESET13: PRESET Position */ -#define SGPIO_PRESET13_PRESET_Msk (0x00000fffUL << SGPIO_PRESET13_PRESET_Pos) /*!< SGPIO PRESET13: PRESET Mask */ - -// ------------------------------------- SGPIO_PRESET14 ----------------------------------------- -#define SGPIO_PRESET14_PRESET_Pos 0 /*!< SGPIO PRESET14: PRESET Position */ -#define SGPIO_PRESET14_PRESET_Msk (0x00000fffUL << SGPIO_PRESET14_PRESET_Pos) /*!< SGPIO PRESET14: PRESET Mask */ - -// ------------------------------------- SGPIO_PRESET15 ----------------------------------------- -#define SGPIO_PRESET15_PRESET_Pos 0 /*!< SGPIO PRESET15: PRESET Position */ -#define SGPIO_PRESET15_PRESET_Msk (0x00000fffUL << SGPIO_PRESET15_PRESET_Pos) /*!< SGPIO PRESET15: PRESET Mask */ - -// -------------------------------------- SGPIO_COUNT0 ------------------------------------------ -#define SGPIO_COUNT0_COUNT_Pos 0 /*!< SGPIO COUNT0: COUNT Position */ -#define SGPIO_COUNT0_COUNT_Msk (0x00000fffUL << SGPIO_COUNT0_COUNT_Pos) /*!< SGPIO COUNT0: COUNT Mask */ - -// -------------------------------------- SGPIO_COUNT1 ------------------------------------------ -#define SGPIO_COUNT1_COUNT_Pos 0 /*!< SGPIO COUNT1: COUNT Position */ -#define SGPIO_COUNT1_COUNT_Msk (0x00000fffUL << SGPIO_COUNT1_COUNT_Pos) /*!< SGPIO COUNT1: COUNT Mask */ - -// -------------------------------------- SGPIO_COUNT2 ------------------------------------------ -#define SGPIO_COUNT2_COUNT_Pos 0 /*!< SGPIO COUNT2: COUNT Position */ -#define SGPIO_COUNT2_COUNT_Msk (0x00000fffUL << SGPIO_COUNT2_COUNT_Pos) /*!< SGPIO COUNT2: COUNT Mask */ - -// -------------------------------------- SGPIO_COUNT3 ------------------------------------------ -#define SGPIO_COUNT3_COUNT_Pos 0 /*!< SGPIO COUNT3: COUNT Position */ -#define SGPIO_COUNT3_COUNT_Msk (0x00000fffUL << SGPIO_COUNT3_COUNT_Pos) /*!< SGPIO COUNT3: COUNT Mask */ - -// -------------------------------------- SGPIO_COUNT4 ------------------------------------------ -#define SGPIO_COUNT4_COUNT_Pos 0 /*!< SGPIO COUNT4: COUNT Position */ -#define SGPIO_COUNT4_COUNT_Msk (0x00000fffUL << SGPIO_COUNT4_COUNT_Pos) /*!< SGPIO COUNT4: COUNT Mask */ - -// -------------------------------------- SGPIO_COUNT5 ------------------------------------------ -#define SGPIO_COUNT5_COUNT_Pos 0 /*!< SGPIO COUNT5: COUNT Position */ -#define SGPIO_COUNT5_COUNT_Msk (0x00000fffUL << SGPIO_COUNT5_COUNT_Pos) /*!< SGPIO COUNT5: COUNT Mask */ - -// -------------------------------------- SGPIO_COUNT6 ------------------------------------------ -#define SGPIO_COUNT6_COUNT_Pos 0 /*!< SGPIO COUNT6: COUNT Position */ -#define SGPIO_COUNT6_COUNT_Msk (0x00000fffUL << SGPIO_COUNT6_COUNT_Pos) /*!< SGPIO COUNT6: COUNT Mask */ - -// -------------------------------------- SGPIO_COUNT7 ------------------------------------------ -#define SGPIO_COUNT7_COUNT_Pos 0 /*!< SGPIO COUNT7: COUNT Position */ -#define SGPIO_COUNT7_COUNT_Msk (0x00000fffUL << SGPIO_COUNT7_COUNT_Pos) /*!< SGPIO COUNT7: COUNT Mask */ - -// -------------------------------------- SGPIO_COUNT8 ------------------------------------------ -#define SGPIO_COUNT8_COUNT_Pos 0 /*!< SGPIO COUNT8: COUNT Position */ -#define SGPIO_COUNT8_COUNT_Msk (0x00000fffUL << SGPIO_COUNT8_COUNT_Pos) /*!< SGPIO COUNT8: COUNT Mask */ - -// -------------------------------------- SGPIO_COUNT9 ------------------------------------------ -#define SGPIO_COUNT9_COUNT_Pos 0 /*!< SGPIO COUNT9: COUNT Position */ -#define SGPIO_COUNT9_COUNT_Msk (0x00000fffUL << SGPIO_COUNT9_COUNT_Pos) /*!< SGPIO COUNT9: COUNT Mask */ - -// -------------------------------------- SGPIO_COUNT10 ----------------------------------------- -#define SGPIO_COUNT10_COUNT_Pos 0 /*!< SGPIO COUNT10: COUNT Position */ -#define SGPIO_COUNT10_COUNT_Msk (0x00000fffUL << SGPIO_COUNT10_COUNT_Pos) /*!< SGPIO COUNT10: COUNT Mask */ - -// -------------------------------------- SGPIO_COUNT11 ----------------------------------------- -#define SGPIO_COUNT11_COUNT_Pos 0 /*!< SGPIO COUNT11: COUNT Position */ -#define SGPIO_COUNT11_COUNT_Msk (0x00000fffUL << SGPIO_COUNT11_COUNT_Pos) /*!< SGPIO COUNT11: COUNT Mask */ - -// -------------------------------------- SGPIO_COUNT12 ----------------------------------------- -#define SGPIO_COUNT12_COUNT_Pos 0 /*!< SGPIO COUNT12: COUNT Position */ -#define SGPIO_COUNT12_COUNT_Msk (0x00000fffUL << SGPIO_COUNT12_COUNT_Pos) /*!< SGPIO COUNT12: COUNT Mask */ - -// -------------------------------------- SGPIO_COUNT13 ----------------------------------------- -#define SGPIO_COUNT13_COUNT_Pos 0 /*!< SGPIO COUNT13: COUNT Position */ -#define SGPIO_COUNT13_COUNT_Msk (0x00000fffUL << SGPIO_COUNT13_COUNT_Pos) /*!< SGPIO COUNT13: COUNT Mask */ - -// -------------------------------------- SGPIO_COUNT14 ----------------------------------------- -#define SGPIO_COUNT14_COUNT_Pos 0 /*!< SGPIO COUNT14: COUNT Position */ -#define SGPIO_COUNT14_COUNT_Msk (0x00000fffUL << SGPIO_COUNT14_COUNT_Pos) /*!< SGPIO COUNT14: COUNT Mask */ - -// -------------------------------------- SGPIO_COUNT15 ----------------------------------------- -#define SGPIO_COUNT15_COUNT_Pos 0 /*!< SGPIO COUNT15: COUNT Position */ -#define SGPIO_COUNT15_COUNT_Msk (0x00000fffUL << SGPIO_COUNT15_COUNT_Pos) /*!< SGPIO COUNT15: COUNT Mask */ - -// --------------------------------------- SGPIO_POS0 ------------------------------------------- -#define SGPIO_POS0_POS_Pos 0 /*!< SGPIO POS0: POS Position */ -#define SGPIO_POS0_POS_Msk (0x000000ffUL << SGPIO_POS0_POS_Pos) /*!< SGPIO POS0: POS Mask */ -#define SGPIO_POS0_POS_RESET_Pos 8 /*!< SGPIO POS0: POS_RESET Position */ -#define SGPIO_POS0_POS_RESET_Msk (0x000000ffUL << SGPIO_POS0_POS_RESET_Pos) /*!< SGPIO POS0: POS_RESET Mask */ - -// --------------------------------------- SGPIO_POS1 ------------------------------------------- -#define SGPIO_POS1_POS_Pos 0 /*!< SGPIO POS1: POS Position */ -#define SGPIO_POS1_POS_Msk (0x000000ffUL << SGPIO_POS1_POS_Pos) /*!< SGPIO POS1: POS Mask */ -#define SGPIO_POS1_POS_RESET_Pos 8 /*!< SGPIO POS1: POS_RESET Position */ -#define SGPIO_POS1_POS_RESET_Msk (0x000000ffUL << SGPIO_POS1_POS_RESET_Pos) /*!< SGPIO POS1: POS_RESET Mask */ - -// --------------------------------------- SGPIO_POS2 ------------------------------------------- -#define SGPIO_POS2_POS_Pos 0 /*!< SGPIO POS2: POS Position */ -#define SGPIO_POS2_POS_Msk (0x000000ffUL << SGPIO_POS2_POS_Pos) /*!< SGPIO POS2: POS Mask */ -#define SGPIO_POS2_POS_RESET_Pos 8 /*!< SGPIO POS2: POS_RESET Position */ -#define SGPIO_POS2_POS_RESET_Msk (0x000000ffUL << SGPIO_POS2_POS_RESET_Pos) /*!< SGPIO POS2: POS_RESET Mask */ - -// --------------------------------------- SGPIO_POS3 ------------------------------------------- -#define SGPIO_POS3_POS_Pos 0 /*!< SGPIO POS3: POS Position */ -#define SGPIO_POS3_POS_Msk (0x000000ffUL << SGPIO_POS3_POS_Pos) /*!< SGPIO POS3: POS Mask */ -#define SGPIO_POS3_POS_RESET_Pos 8 /*!< SGPIO POS3: POS_RESET Position */ -#define SGPIO_POS3_POS_RESET_Msk (0x000000ffUL << SGPIO_POS3_POS_RESET_Pos) /*!< SGPIO POS3: POS_RESET Mask */ - -// --------------------------------------- SGPIO_POS4 ------------------------------------------- -#define SGPIO_POS4_POS_Pos 0 /*!< SGPIO POS4: POS Position */ -#define SGPIO_POS4_POS_Msk (0x000000ffUL << SGPIO_POS4_POS_Pos) /*!< SGPIO POS4: POS Mask */ -#define SGPIO_POS4_POS_RESET_Pos 8 /*!< SGPIO POS4: POS_RESET Position */ -#define SGPIO_POS4_POS_RESET_Msk (0x000000ffUL << SGPIO_POS4_POS_RESET_Pos) /*!< SGPIO POS4: POS_RESET Mask */ - -// --------------------------------------- SGPIO_POS5 ------------------------------------------- -#define SGPIO_POS5_POS_Pos 0 /*!< SGPIO POS5: POS Position */ -#define SGPIO_POS5_POS_Msk (0x000000ffUL << SGPIO_POS5_POS_Pos) /*!< SGPIO POS5: POS Mask */ -#define SGPIO_POS5_POS_RESET_Pos 8 /*!< SGPIO POS5: POS_RESET Position */ -#define SGPIO_POS5_POS_RESET_Msk (0x000000ffUL << SGPIO_POS5_POS_RESET_Pos) /*!< SGPIO POS5: POS_RESET Mask */ - -// --------------------------------------- SGPIO_POS6 ------------------------------------------- -#define SGPIO_POS6_POS_Pos 0 /*!< SGPIO POS6: POS Position */ -#define SGPIO_POS6_POS_Msk (0x000000ffUL << SGPIO_POS6_POS_Pos) /*!< SGPIO POS6: POS Mask */ -#define SGPIO_POS6_POS_RESET_Pos 8 /*!< SGPIO POS6: POS_RESET Position */ -#define SGPIO_POS6_POS_RESET_Msk (0x000000ffUL << SGPIO_POS6_POS_RESET_Pos) /*!< SGPIO POS6: POS_RESET Mask */ - -// --------------------------------------- SGPIO_POS7 ------------------------------------------- -#define SGPIO_POS7_POS_Pos 0 /*!< SGPIO POS7: POS Position */ -#define SGPIO_POS7_POS_Msk (0x000000ffUL << SGPIO_POS7_POS_Pos) /*!< SGPIO POS7: POS Mask */ -#define SGPIO_POS7_POS_RESET_Pos 8 /*!< SGPIO POS7: POS_RESET Position */ -#define SGPIO_POS7_POS_RESET_Msk (0x000000ffUL << SGPIO_POS7_POS_RESET_Pos) /*!< SGPIO POS7: POS_RESET Mask */ - -// --------------------------------------- SGPIO_POS8 ------------------------------------------- -#define SGPIO_POS8_POS_Pos 0 /*!< SGPIO POS8: POS Position */ -#define SGPIO_POS8_POS_Msk (0x000000ffUL << SGPIO_POS8_POS_Pos) /*!< SGPIO POS8: POS Mask */ -#define SGPIO_POS8_POS_RESET_Pos 8 /*!< SGPIO POS8: POS_RESET Position */ -#define SGPIO_POS8_POS_RESET_Msk (0x000000ffUL << SGPIO_POS8_POS_RESET_Pos) /*!< SGPIO POS8: POS_RESET Mask */ - -// --------------------------------------- SGPIO_POS9 ------------------------------------------- -#define SGPIO_POS9_POS_Pos 0 /*!< SGPIO POS9: POS Position */ -#define SGPIO_POS9_POS_Msk (0x000000ffUL << SGPIO_POS9_POS_Pos) /*!< SGPIO POS9: POS Mask */ -#define SGPIO_POS9_POS_RESET_Pos 8 /*!< SGPIO POS9: POS_RESET Position */ -#define SGPIO_POS9_POS_RESET_Msk (0x000000ffUL << SGPIO_POS9_POS_RESET_Pos) /*!< SGPIO POS9: POS_RESET Mask */ - -// --------------------------------------- SGPIO_POS10 ------------------------------------------ -#define SGPIO_POS10_POS_Pos 0 /*!< SGPIO POS10: POS Position */ -#define SGPIO_POS10_POS_Msk (0x000000ffUL << SGPIO_POS10_POS_Pos) /*!< SGPIO POS10: POS Mask */ -#define SGPIO_POS10_POS_RESET_Pos 8 /*!< SGPIO POS10: POS_RESET Position */ -#define SGPIO_POS10_POS_RESET_Msk (0x000000ffUL << SGPIO_POS10_POS_RESET_Pos) /*!< SGPIO POS10: POS_RESET Mask */ - -// --------------------------------------- SGPIO_POS11 ------------------------------------------ -#define SGPIO_POS11_POS_Pos 0 /*!< SGPIO POS11: POS Position */ -#define SGPIO_POS11_POS_Msk (0x000000ffUL << SGPIO_POS11_POS_Pos) /*!< SGPIO POS11: POS Mask */ -#define SGPIO_POS11_POS_RESET_Pos 8 /*!< SGPIO POS11: POS_RESET Position */ -#define SGPIO_POS11_POS_RESET_Msk (0x000000ffUL << SGPIO_POS11_POS_RESET_Pos) /*!< SGPIO POS11: POS_RESET Mask */ - -// --------------------------------------- SGPIO_POS12 ------------------------------------------ -#define SGPIO_POS12_POS_Pos 0 /*!< SGPIO POS12: POS Position */ -#define SGPIO_POS12_POS_Msk (0x000000ffUL << SGPIO_POS12_POS_Pos) /*!< SGPIO POS12: POS Mask */ -#define SGPIO_POS12_POS_RESET_Pos 8 /*!< SGPIO POS12: POS_RESET Position */ -#define SGPIO_POS12_POS_RESET_Msk (0x000000ffUL << SGPIO_POS12_POS_RESET_Pos) /*!< SGPIO POS12: POS_RESET Mask */ - -// --------------------------------------- SGPIO_POS13 ------------------------------------------ -#define SGPIO_POS13_POS_Pos 0 /*!< SGPIO POS13: POS Position */ -#define SGPIO_POS13_POS_Msk (0x000000ffUL << SGPIO_POS13_POS_Pos) /*!< SGPIO POS13: POS Mask */ -#define SGPIO_POS13_POS_RESET_Pos 8 /*!< SGPIO POS13: POS_RESET Position */ -#define SGPIO_POS13_POS_RESET_Msk (0x000000ffUL << SGPIO_POS13_POS_RESET_Pos) /*!< SGPIO POS13: POS_RESET Mask */ - -// --------------------------------------- SGPIO_POS14 ------------------------------------------ -#define SGPIO_POS14_POS_Pos 0 /*!< SGPIO POS14: POS Position */ -#define SGPIO_POS14_POS_Msk (0x000000ffUL << SGPIO_POS14_POS_Pos) /*!< SGPIO POS14: POS Mask */ -#define SGPIO_POS14_POS_RESET_Pos 8 /*!< SGPIO POS14: POS_RESET Position */ -#define SGPIO_POS14_POS_RESET_Msk (0x000000ffUL << SGPIO_POS14_POS_RESET_Pos) /*!< SGPIO POS14: POS_RESET Mask */ - -// --------------------------------------- SGPIO_POS15 ------------------------------------------ -#define SGPIO_POS15_POS_Pos 0 /*!< SGPIO POS15: POS Position */ -#define SGPIO_POS15_POS_Msk (0x000000ffUL << SGPIO_POS15_POS_Pos) /*!< SGPIO POS15: POS Mask */ -#define SGPIO_POS15_POS_RESET_Pos 8 /*!< SGPIO POS15: POS_RESET Position */ -#define SGPIO_POS15_POS_RESET_Msk (0x000000ffUL << SGPIO_POS15_POS_RESET_Pos) /*!< SGPIO POS15: POS_RESET Mask */ - -// -------------------------------------- SGPIO_MASK_A ------------------------------------------ -#define SGPIO_MASK_A_MASK_A0_Pos 0 /*!< SGPIO MASK_A: MASK_A0 Position */ -#define SGPIO_MASK_A_MASK_A0_Msk (0x01UL << SGPIO_MASK_A_MASK_A0_Pos) /*!< SGPIO MASK_A: MASK_A0 Mask */ -#define SGPIO_MASK_A_MASK_A1_Pos 1 /*!< SGPIO MASK_A: MASK_A1 Position */ -#define SGPIO_MASK_A_MASK_A1_Msk (0x01UL << SGPIO_MASK_A_MASK_A1_Pos) /*!< SGPIO MASK_A: MASK_A1 Mask */ -#define SGPIO_MASK_A_MASK_A2_Pos 2 /*!< SGPIO MASK_A: MASK_A2 Position */ -#define SGPIO_MASK_A_MASK_A2_Msk (0x01UL << SGPIO_MASK_A_MASK_A2_Pos) /*!< SGPIO MASK_A: MASK_A2 Mask */ -#define SGPIO_MASK_A_MASK_A3_Pos 3 /*!< SGPIO MASK_A: MASK_A3 Position */ -#define SGPIO_MASK_A_MASK_A3_Msk (0x01UL << SGPIO_MASK_A_MASK_A3_Pos) /*!< SGPIO MASK_A: MASK_A3 Mask */ -#define SGPIO_MASK_A_MASK_A4_Pos 4 /*!< SGPIO MASK_A: MASK_A4 Position */ -#define SGPIO_MASK_A_MASK_A4_Msk (0x01UL << SGPIO_MASK_A_MASK_A4_Pos) /*!< SGPIO MASK_A: MASK_A4 Mask */ -#define SGPIO_MASK_A_MASK_A5_Pos 5 /*!< SGPIO MASK_A: MASK_A5 Position */ -#define SGPIO_MASK_A_MASK_A5_Msk (0x01UL << SGPIO_MASK_A_MASK_A5_Pos) /*!< SGPIO MASK_A: MASK_A5 Mask */ -#define SGPIO_MASK_A_MASK_A6_Pos 6 /*!< SGPIO MASK_A: MASK_A6 Position */ -#define SGPIO_MASK_A_MASK_A6_Msk (0x01UL << SGPIO_MASK_A_MASK_A6_Pos) /*!< SGPIO MASK_A: MASK_A6 Mask */ -#define SGPIO_MASK_A_MASK_A7_Pos 7 /*!< SGPIO MASK_A: MASK_A7 Position */ -#define SGPIO_MASK_A_MASK_A7_Msk (0x01UL << SGPIO_MASK_A_MASK_A7_Pos) /*!< SGPIO MASK_A: MASK_A7 Mask */ -#define SGPIO_MASK_A_MASK_A8_Pos 8 /*!< SGPIO MASK_A: MASK_A8 Position */ -#define SGPIO_MASK_A_MASK_A8_Msk (0x01UL << SGPIO_MASK_A_MASK_A8_Pos) /*!< SGPIO MASK_A: MASK_A8 Mask */ -#define SGPIO_MASK_A_MASK_A9_Pos 9 /*!< SGPIO MASK_A: MASK_A9 Position */ -#define SGPIO_MASK_A_MASK_A9_Msk (0x01UL << SGPIO_MASK_A_MASK_A9_Pos) /*!< SGPIO MASK_A: MASK_A9 Mask */ -#define SGPIO_MASK_A_MASK_A10_Pos 10 /*!< SGPIO MASK_A: MASK_A10 Position */ -#define SGPIO_MASK_A_MASK_A10_Msk (0x01UL << SGPIO_MASK_A_MASK_A10_Pos) /*!< SGPIO MASK_A: MASK_A10 Mask */ -#define SGPIO_MASK_A_MASK_A11_Pos 11 /*!< SGPIO MASK_A: MASK_A11 Position */ -#define SGPIO_MASK_A_MASK_A11_Msk (0x01UL << SGPIO_MASK_A_MASK_A11_Pos) /*!< SGPIO MASK_A: MASK_A11 Mask */ -#define SGPIO_MASK_A_MASK_A12_Pos 12 /*!< SGPIO MASK_A: MASK_A12 Position */ -#define SGPIO_MASK_A_MASK_A12_Msk (0x01UL << SGPIO_MASK_A_MASK_A12_Pos) /*!< SGPIO MASK_A: MASK_A12 Mask */ -#define SGPIO_MASK_A_MASK_A13_Pos 13 /*!< SGPIO MASK_A: MASK_A13 Position */ -#define SGPIO_MASK_A_MASK_A13_Msk (0x01UL << SGPIO_MASK_A_MASK_A13_Pos) /*!< SGPIO MASK_A: MASK_A13 Mask */ -#define SGPIO_MASK_A_MASK_A14_Pos 14 /*!< SGPIO MASK_A: MASK_A14 Position */ -#define SGPIO_MASK_A_MASK_A14_Msk (0x01UL << SGPIO_MASK_A_MASK_A14_Pos) /*!< SGPIO MASK_A: MASK_A14 Mask */ -#define SGPIO_MASK_A_MASK_A15_Pos 15 /*!< SGPIO MASK_A: MASK_A15 Position */ -#define SGPIO_MASK_A_MASK_A15_Msk (0x01UL << SGPIO_MASK_A_MASK_A15_Pos) /*!< SGPIO MASK_A: MASK_A15 Mask */ -#define SGPIO_MASK_A_MASK_A16_Pos 16 /*!< SGPIO MASK_A: MASK_A16 Position */ -#define SGPIO_MASK_A_MASK_A16_Msk (0x01UL << SGPIO_MASK_A_MASK_A16_Pos) /*!< SGPIO MASK_A: MASK_A16 Mask */ -#define SGPIO_MASK_A_MASK_A17_Pos 17 /*!< SGPIO MASK_A: MASK_A17 Position */ -#define SGPIO_MASK_A_MASK_A17_Msk (0x01UL << SGPIO_MASK_A_MASK_A17_Pos) /*!< SGPIO MASK_A: MASK_A17 Mask */ -#define SGPIO_MASK_A_MASK_A18_Pos 18 /*!< SGPIO MASK_A: MASK_A18 Position */ -#define SGPIO_MASK_A_MASK_A18_Msk (0x01UL << SGPIO_MASK_A_MASK_A18_Pos) /*!< SGPIO MASK_A: MASK_A18 Mask */ -#define SGPIO_MASK_A_MASK_A19_Pos 19 /*!< SGPIO MASK_A: MASK_A19 Position */ -#define SGPIO_MASK_A_MASK_A19_Msk (0x01UL << SGPIO_MASK_A_MASK_A19_Pos) /*!< SGPIO MASK_A: MASK_A19 Mask */ -#define SGPIO_MASK_A_MASK_A20_Pos 20 /*!< SGPIO MASK_A: MASK_A20 Position */ -#define SGPIO_MASK_A_MASK_A20_Msk (0x01UL << SGPIO_MASK_A_MASK_A20_Pos) /*!< SGPIO MASK_A: MASK_A20 Mask */ -#define SGPIO_MASK_A_MASK_A21_Pos 21 /*!< SGPIO MASK_A: MASK_A21 Position */ -#define SGPIO_MASK_A_MASK_A21_Msk (0x01UL << SGPIO_MASK_A_MASK_A21_Pos) /*!< SGPIO MASK_A: MASK_A21 Mask */ -#define SGPIO_MASK_A_MASK_A22_Pos 22 /*!< SGPIO MASK_A: MASK_A22 Position */ -#define SGPIO_MASK_A_MASK_A22_Msk (0x01UL << SGPIO_MASK_A_MASK_A22_Pos) /*!< SGPIO MASK_A: MASK_A22 Mask */ -#define SGPIO_MASK_A_MASK_A23_Pos 23 /*!< SGPIO MASK_A: MASK_A23 Position */ -#define SGPIO_MASK_A_MASK_A23_Msk (0x01UL << SGPIO_MASK_A_MASK_A23_Pos) /*!< SGPIO MASK_A: MASK_A23 Mask */ -#define SGPIO_MASK_A_MASK_A24_Pos 24 /*!< SGPIO MASK_A: MASK_A24 Position */ -#define SGPIO_MASK_A_MASK_A24_Msk (0x01UL << SGPIO_MASK_A_MASK_A24_Pos) /*!< SGPIO MASK_A: MASK_A24 Mask */ -#define SGPIO_MASK_A_MASK_A25_Pos 25 /*!< SGPIO MASK_A: MASK_A25 Position */ -#define SGPIO_MASK_A_MASK_A25_Msk (0x01UL << SGPIO_MASK_A_MASK_A25_Pos) /*!< SGPIO MASK_A: MASK_A25 Mask */ -#define SGPIO_MASK_A_MASK_A26_Pos 26 /*!< SGPIO MASK_A: MASK_A26 Position */ -#define SGPIO_MASK_A_MASK_A26_Msk (0x01UL << SGPIO_MASK_A_MASK_A26_Pos) /*!< SGPIO MASK_A: MASK_A26 Mask */ -#define SGPIO_MASK_A_MASK_A27_Pos 27 /*!< SGPIO MASK_A: MASK_A27 Position */ -#define SGPIO_MASK_A_MASK_A27_Msk (0x01UL << SGPIO_MASK_A_MASK_A27_Pos) /*!< SGPIO MASK_A: MASK_A27 Mask */ -#define SGPIO_MASK_A_MASK_A28_Pos 28 /*!< SGPIO MASK_A: MASK_A28 Position */ -#define SGPIO_MASK_A_MASK_A28_Msk (0x01UL << SGPIO_MASK_A_MASK_A28_Pos) /*!< SGPIO MASK_A: MASK_A28 Mask */ -#define SGPIO_MASK_A_MASK_A29_Pos 29 /*!< SGPIO MASK_A: MASK_A29 Position */ -#define SGPIO_MASK_A_MASK_A29_Msk (0x01UL << SGPIO_MASK_A_MASK_A29_Pos) /*!< SGPIO MASK_A: MASK_A29 Mask */ -#define SGPIO_MASK_A_MASK_A30_Pos 30 /*!< SGPIO MASK_A: MASK_A30 Position */ -#define SGPIO_MASK_A_MASK_A30_Msk (0x01UL << SGPIO_MASK_A_MASK_A30_Pos) /*!< SGPIO MASK_A: MASK_A30 Mask */ -#define SGPIO_MASK_A_MASK_A31_Pos 31 /*!< SGPIO MASK_A: MASK_A31 Position */ -#define SGPIO_MASK_A_MASK_A31_Msk (0x01UL << SGPIO_MASK_A_MASK_A31_Pos) /*!< SGPIO MASK_A: MASK_A31 Mask */ - -// -------------------------------------- SGPIO_MASK_H ------------------------------------------ -#define SGPIO_MASK_H_MASK_H0_Pos 0 /*!< SGPIO MASK_H: MASK_H0 Position */ -#define SGPIO_MASK_H_MASK_H0_Msk (0x01UL << SGPIO_MASK_H_MASK_H0_Pos) /*!< SGPIO MASK_H: MASK_H0 Mask */ -#define SGPIO_MASK_H_MASK_H1_Pos 1 /*!< SGPIO MASK_H: MASK_H1 Position */ -#define SGPIO_MASK_H_MASK_H1_Msk (0x01UL << SGPIO_MASK_H_MASK_H1_Pos) /*!< SGPIO MASK_H: MASK_H1 Mask */ -#define SGPIO_MASK_H_MASK_H2_Pos 2 /*!< SGPIO MASK_H: MASK_H2 Position */ -#define SGPIO_MASK_H_MASK_H2_Msk (0x01UL << SGPIO_MASK_H_MASK_H2_Pos) /*!< SGPIO MASK_H: MASK_H2 Mask */ -#define SGPIO_MASK_H_MASK_H3_Pos 3 /*!< SGPIO MASK_H: MASK_H3 Position */ -#define SGPIO_MASK_H_MASK_H3_Msk (0x01UL << SGPIO_MASK_H_MASK_H3_Pos) /*!< SGPIO MASK_H: MASK_H3 Mask */ -#define SGPIO_MASK_H_MASK_H4_Pos 4 /*!< SGPIO MASK_H: MASK_H4 Position */ -#define SGPIO_MASK_H_MASK_H4_Msk (0x01UL << SGPIO_MASK_H_MASK_H4_Pos) /*!< SGPIO MASK_H: MASK_H4 Mask */ -#define SGPIO_MASK_H_MASK_H5_Pos 5 /*!< SGPIO MASK_H: MASK_H5 Position */ -#define SGPIO_MASK_H_MASK_H5_Msk (0x01UL << SGPIO_MASK_H_MASK_H5_Pos) /*!< SGPIO MASK_H: MASK_H5 Mask */ -#define SGPIO_MASK_H_MASK_H6_Pos 6 /*!< SGPIO MASK_H: MASK_H6 Position */ -#define SGPIO_MASK_H_MASK_H6_Msk (0x01UL << SGPIO_MASK_H_MASK_H6_Pos) /*!< SGPIO MASK_H: MASK_H6 Mask */ -#define SGPIO_MASK_H_MASK_H7_Pos 7 /*!< SGPIO MASK_H: MASK_H7 Position */ -#define SGPIO_MASK_H_MASK_H7_Msk (0x01UL << SGPIO_MASK_H_MASK_H7_Pos) /*!< SGPIO MASK_H: MASK_H7 Mask */ -#define SGPIO_MASK_H_MASK_H8_Pos 8 /*!< SGPIO MASK_H: MASK_H8 Position */ -#define SGPIO_MASK_H_MASK_H8_Msk (0x01UL << SGPIO_MASK_H_MASK_H8_Pos) /*!< SGPIO MASK_H: MASK_H8 Mask */ -#define SGPIO_MASK_H_MASK_H9_Pos 9 /*!< SGPIO MASK_H: MASK_H9 Position */ -#define SGPIO_MASK_H_MASK_H9_Msk (0x01UL << SGPIO_MASK_H_MASK_H9_Pos) /*!< SGPIO MASK_H: MASK_H9 Mask */ -#define SGPIO_MASK_H_MASK_H10_Pos 10 /*!< SGPIO MASK_H: MASK_H10 Position */ -#define SGPIO_MASK_H_MASK_H10_Msk (0x01UL << SGPIO_MASK_H_MASK_H10_Pos) /*!< SGPIO MASK_H: MASK_H10 Mask */ -#define SGPIO_MASK_H_MASK_H11_Pos 11 /*!< SGPIO MASK_H: MASK_H11 Position */ -#define SGPIO_MASK_H_MASK_H11_Msk (0x01UL << SGPIO_MASK_H_MASK_H11_Pos) /*!< SGPIO MASK_H: MASK_H11 Mask */ -#define SGPIO_MASK_H_MASK_H12_Pos 12 /*!< SGPIO MASK_H: MASK_H12 Position */ -#define SGPIO_MASK_H_MASK_H12_Msk (0x01UL << SGPIO_MASK_H_MASK_H12_Pos) /*!< SGPIO MASK_H: MASK_H12 Mask */ -#define SGPIO_MASK_H_MASK_H13_Pos 13 /*!< SGPIO MASK_H: MASK_H13 Position */ -#define SGPIO_MASK_H_MASK_H13_Msk (0x01UL << SGPIO_MASK_H_MASK_H13_Pos) /*!< SGPIO MASK_H: MASK_H13 Mask */ -#define SGPIO_MASK_H_MASK_H14_Pos 14 /*!< SGPIO MASK_H: MASK_H14 Position */ -#define SGPIO_MASK_H_MASK_H14_Msk (0x01UL << SGPIO_MASK_H_MASK_H14_Pos) /*!< SGPIO MASK_H: MASK_H14 Mask */ -#define SGPIO_MASK_H_MASK_H15_Pos 15 /*!< SGPIO MASK_H: MASK_H15 Position */ -#define SGPIO_MASK_H_MASK_H15_Msk (0x01UL << SGPIO_MASK_H_MASK_H15_Pos) /*!< SGPIO MASK_H: MASK_H15 Mask */ -#define SGPIO_MASK_H_MASK_H16_Pos 16 /*!< SGPIO MASK_H: MASK_H16 Position */ -#define SGPIO_MASK_H_MASK_H16_Msk (0x01UL << SGPIO_MASK_H_MASK_H16_Pos) /*!< SGPIO MASK_H: MASK_H16 Mask */ -#define SGPIO_MASK_H_MASK_H17_Pos 17 /*!< SGPIO MASK_H: MASK_H17 Position */ -#define SGPIO_MASK_H_MASK_H17_Msk (0x01UL << SGPIO_MASK_H_MASK_H17_Pos) /*!< SGPIO MASK_H: MASK_H17 Mask */ -#define SGPIO_MASK_H_MASK_H18_Pos 18 /*!< SGPIO MASK_H: MASK_H18 Position */ -#define SGPIO_MASK_H_MASK_H18_Msk (0x01UL << SGPIO_MASK_H_MASK_H18_Pos) /*!< SGPIO MASK_H: MASK_H18 Mask */ -#define SGPIO_MASK_H_MASK_H19_Pos 19 /*!< SGPIO MASK_H: MASK_H19 Position */ -#define SGPIO_MASK_H_MASK_H19_Msk (0x01UL << SGPIO_MASK_H_MASK_H19_Pos) /*!< SGPIO MASK_H: MASK_H19 Mask */ -#define SGPIO_MASK_H_MASK_H20_Pos 20 /*!< SGPIO MASK_H: MASK_H20 Position */ -#define SGPIO_MASK_H_MASK_H20_Msk (0x01UL << SGPIO_MASK_H_MASK_H20_Pos) /*!< SGPIO MASK_H: MASK_H20 Mask */ -#define SGPIO_MASK_H_MASK_H21_Pos 21 /*!< SGPIO MASK_H: MASK_H21 Position */ -#define SGPIO_MASK_H_MASK_H21_Msk (0x01UL << SGPIO_MASK_H_MASK_H21_Pos) /*!< SGPIO MASK_H: MASK_H21 Mask */ -#define SGPIO_MASK_H_MASK_H22_Pos 22 /*!< SGPIO MASK_H: MASK_H22 Position */ -#define SGPIO_MASK_H_MASK_H22_Msk (0x01UL << SGPIO_MASK_H_MASK_H22_Pos) /*!< SGPIO MASK_H: MASK_H22 Mask */ -#define SGPIO_MASK_H_MASK_H23_Pos 23 /*!< SGPIO MASK_H: MASK_H23 Position */ -#define SGPIO_MASK_H_MASK_H23_Msk (0x01UL << SGPIO_MASK_H_MASK_H23_Pos) /*!< SGPIO MASK_H: MASK_H23 Mask */ -#define SGPIO_MASK_H_MASK_H24_Pos 24 /*!< SGPIO MASK_H: MASK_H24 Position */ -#define SGPIO_MASK_H_MASK_H24_Msk (0x01UL << SGPIO_MASK_H_MASK_H24_Pos) /*!< SGPIO MASK_H: MASK_H24 Mask */ -#define SGPIO_MASK_H_MASK_H25_Pos 25 /*!< SGPIO MASK_H: MASK_H25 Position */ -#define SGPIO_MASK_H_MASK_H25_Msk (0x01UL << SGPIO_MASK_H_MASK_H25_Pos) /*!< SGPIO MASK_H: MASK_H25 Mask */ -#define SGPIO_MASK_H_MASK_H26_Pos 26 /*!< SGPIO MASK_H: MASK_H26 Position */ -#define SGPIO_MASK_H_MASK_H26_Msk (0x01UL << SGPIO_MASK_H_MASK_H26_Pos) /*!< SGPIO MASK_H: MASK_H26 Mask */ -#define SGPIO_MASK_H_MASK_H27_Pos 27 /*!< SGPIO MASK_H: MASK_H27 Position */ -#define SGPIO_MASK_H_MASK_H27_Msk (0x01UL << SGPIO_MASK_H_MASK_H27_Pos) /*!< SGPIO MASK_H: MASK_H27 Mask */ -#define SGPIO_MASK_H_MASK_H28_Pos 28 /*!< SGPIO MASK_H: MASK_H28 Position */ -#define SGPIO_MASK_H_MASK_H28_Msk (0x01UL << SGPIO_MASK_H_MASK_H28_Pos) /*!< SGPIO MASK_H: MASK_H28 Mask */ -#define SGPIO_MASK_H_MASK_H29_Pos 29 /*!< SGPIO MASK_H: MASK_H29 Position */ -#define SGPIO_MASK_H_MASK_H29_Msk (0x01UL << SGPIO_MASK_H_MASK_H29_Pos) /*!< SGPIO MASK_H: MASK_H29 Mask */ -#define SGPIO_MASK_H_MASK_H30_Pos 30 /*!< SGPIO MASK_H: MASK_H30 Position */ -#define SGPIO_MASK_H_MASK_H30_Msk (0x01UL << SGPIO_MASK_H_MASK_H30_Pos) /*!< SGPIO MASK_H: MASK_H30 Mask */ -#define SGPIO_MASK_H_MASK_H31_Pos 31 /*!< SGPIO MASK_H: MASK_H31 Position */ -#define SGPIO_MASK_H_MASK_H31_Msk (0x01UL << SGPIO_MASK_H_MASK_H31_Pos) /*!< SGPIO MASK_H: MASK_H31 Mask */ - -// -------------------------------------- SGPIO_MASK_I ------------------------------------------ -#define SGPIO_MASK_I_MASK_I0_Pos 0 /*!< SGPIO MASK_I: MASK_I0 Position */ -#define SGPIO_MASK_I_MASK_I0_Msk (0x01UL << SGPIO_MASK_I_MASK_I0_Pos) /*!< SGPIO MASK_I: MASK_I0 Mask */ -#define SGPIO_MASK_I_MASK_I1_Pos 1 /*!< SGPIO MASK_I: MASK_I1 Position */ -#define SGPIO_MASK_I_MASK_I1_Msk (0x01UL << SGPIO_MASK_I_MASK_I1_Pos) /*!< SGPIO MASK_I: MASK_I1 Mask */ -#define SGPIO_MASK_I_MASK_I2_Pos 2 /*!< SGPIO MASK_I: MASK_I2 Position */ -#define SGPIO_MASK_I_MASK_I2_Msk (0x01UL << SGPIO_MASK_I_MASK_I2_Pos) /*!< SGPIO MASK_I: MASK_I2 Mask */ -#define SGPIO_MASK_I_MASK_I3_Pos 3 /*!< SGPIO MASK_I: MASK_I3 Position */ -#define SGPIO_MASK_I_MASK_I3_Msk (0x01UL << SGPIO_MASK_I_MASK_I3_Pos) /*!< SGPIO MASK_I: MASK_I3 Mask */ -#define SGPIO_MASK_I_MASK_I4_Pos 4 /*!< SGPIO MASK_I: MASK_I4 Position */ -#define SGPIO_MASK_I_MASK_I4_Msk (0x01UL << SGPIO_MASK_I_MASK_I4_Pos) /*!< SGPIO MASK_I: MASK_I4 Mask */ -#define SGPIO_MASK_I_MASK_I5_Pos 5 /*!< SGPIO MASK_I: MASK_I5 Position */ -#define SGPIO_MASK_I_MASK_I5_Msk (0x01UL << SGPIO_MASK_I_MASK_I5_Pos) /*!< SGPIO MASK_I: MASK_I5 Mask */ -#define SGPIO_MASK_I_MASK_I6_Pos 6 /*!< SGPIO MASK_I: MASK_I6 Position */ -#define SGPIO_MASK_I_MASK_I6_Msk (0x01UL << SGPIO_MASK_I_MASK_I6_Pos) /*!< SGPIO MASK_I: MASK_I6 Mask */ -#define SGPIO_MASK_I_MASK_I7_Pos 7 /*!< SGPIO MASK_I: MASK_I7 Position */ -#define SGPIO_MASK_I_MASK_I7_Msk (0x01UL << SGPIO_MASK_I_MASK_I7_Pos) /*!< SGPIO MASK_I: MASK_I7 Mask */ -#define SGPIO_MASK_I_MASK_I8_Pos 8 /*!< SGPIO MASK_I: MASK_I8 Position */ -#define SGPIO_MASK_I_MASK_I8_Msk (0x01UL << SGPIO_MASK_I_MASK_I8_Pos) /*!< SGPIO MASK_I: MASK_I8 Mask */ -#define SGPIO_MASK_I_MASK_I9_Pos 9 /*!< SGPIO MASK_I: MASK_I9 Position */ -#define SGPIO_MASK_I_MASK_I9_Msk (0x01UL << SGPIO_MASK_I_MASK_I9_Pos) /*!< SGPIO MASK_I: MASK_I9 Mask */ -#define SGPIO_MASK_I_MASK_I10_Pos 10 /*!< SGPIO MASK_I: MASK_I10 Position */ -#define SGPIO_MASK_I_MASK_I10_Msk (0x01UL << SGPIO_MASK_I_MASK_I10_Pos) /*!< SGPIO MASK_I: MASK_I10 Mask */ -#define SGPIO_MASK_I_MASK_I11_Pos 11 /*!< SGPIO MASK_I: MASK_I11 Position */ -#define SGPIO_MASK_I_MASK_I11_Msk (0x01UL << SGPIO_MASK_I_MASK_I11_Pos) /*!< SGPIO MASK_I: MASK_I11 Mask */ -#define SGPIO_MASK_I_MASK_I12_Pos 12 /*!< SGPIO MASK_I: MASK_I12 Position */ -#define SGPIO_MASK_I_MASK_I12_Msk (0x01UL << SGPIO_MASK_I_MASK_I12_Pos) /*!< SGPIO MASK_I: MASK_I12 Mask */ -#define SGPIO_MASK_I_MASK_I13_Pos 13 /*!< SGPIO MASK_I: MASK_I13 Position */ -#define SGPIO_MASK_I_MASK_I13_Msk (0x01UL << SGPIO_MASK_I_MASK_I13_Pos) /*!< SGPIO MASK_I: MASK_I13 Mask */ -#define SGPIO_MASK_I_MASK_I14_Pos 14 /*!< SGPIO MASK_I: MASK_I14 Position */ -#define SGPIO_MASK_I_MASK_I14_Msk (0x01UL << SGPIO_MASK_I_MASK_I14_Pos) /*!< SGPIO MASK_I: MASK_I14 Mask */ -#define SGPIO_MASK_I_MASK_I15_Pos 15 /*!< SGPIO MASK_I: MASK_I15 Position */ -#define SGPIO_MASK_I_MASK_I15_Msk (0x01UL << SGPIO_MASK_I_MASK_I15_Pos) /*!< SGPIO MASK_I: MASK_I15 Mask */ -#define SGPIO_MASK_I_MASK_I16_Pos 16 /*!< SGPIO MASK_I: MASK_I16 Position */ -#define SGPIO_MASK_I_MASK_I16_Msk (0x01UL << SGPIO_MASK_I_MASK_I16_Pos) /*!< SGPIO MASK_I: MASK_I16 Mask */ -#define SGPIO_MASK_I_MASK_I17_Pos 17 /*!< SGPIO MASK_I: MASK_I17 Position */ -#define SGPIO_MASK_I_MASK_I17_Msk (0x01UL << SGPIO_MASK_I_MASK_I17_Pos) /*!< SGPIO MASK_I: MASK_I17 Mask */ -#define SGPIO_MASK_I_MASK_I18_Pos 18 /*!< SGPIO MASK_I: MASK_I18 Position */ -#define SGPIO_MASK_I_MASK_I18_Msk (0x01UL << SGPIO_MASK_I_MASK_I18_Pos) /*!< SGPIO MASK_I: MASK_I18 Mask */ -#define SGPIO_MASK_I_MASK_I19_Pos 19 /*!< SGPIO MASK_I: MASK_I19 Position */ -#define SGPIO_MASK_I_MASK_I19_Msk (0x01UL << SGPIO_MASK_I_MASK_I19_Pos) /*!< SGPIO MASK_I: MASK_I19 Mask */ -#define SGPIO_MASK_I_MASK_I20_Pos 20 /*!< SGPIO MASK_I: MASK_I20 Position */ -#define SGPIO_MASK_I_MASK_I20_Msk (0x01UL << SGPIO_MASK_I_MASK_I20_Pos) /*!< SGPIO MASK_I: MASK_I20 Mask */ -#define SGPIO_MASK_I_MASK_I21_Pos 21 /*!< SGPIO MASK_I: MASK_I21 Position */ -#define SGPIO_MASK_I_MASK_I21_Msk (0x01UL << SGPIO_MASK_I_MASK_I21_Pos) /*!< SGPIO MASK_I: MASK_I21 Mask */ -#define SGPIO_MASK_I_MASK_I22_Pos 22 /*!< SGPIO MASK_I: MASK_I22 Position */ -#define SGPIO_MASK_I_MASK_I22_Msk (0x01UL << SGPIO_MASK_I_MASK_I22_Pos) /*!< SGPIO MASK_I: MASK_I22 Mask */ -#define SGPIO_MASK_I_MASK_I23_Pos 23 /*!< SGPIO MASK_I: MASK_I23 Position */ -#define SGPIO_MASK_I_MASK_I23_Msk (0x01UL << SGPIO_MASK_I_MASK_I23_Pos) /*!< SGPIO MASK_I: MASK_I23 Mask */ -#define SGPIO_MASK_I_MASK_I24_Pos 24 /*!< SGPIO MASK_I: MASK_I24 Position */ -#define SGPIO_MASK_I_MASK_I24_Msk (0x01UL << SGPIO_MASK_I_MASK_I24_Pos) /*!< SGPIO MASK_I: MASK_I24 Mask */ -#define SGPIO_MASK_I_MASK_I25_Pos 25 /*!< SGPIO MASK_I: MASK_I25 Position */ -#define SGPIO_MASK_I_MASK_I25_Msk (0x01UL << SGPIO_MASK_I_MASK_I25_Pos) /*!< SGPIO MASK_I: MASK_I25 Mask */ -#define SGPIO_MASK_I_MASK_I26_Pos 26 /*!< SGPIO MASK_I: MASK_I26 Position */ -#define SGPIO_MASK_I_MASK_I26_Msk (0x01UL << SGPIO_MASK_I_MASK_I26_Pos) /*!< SGPIO MASK_I: MASK_I26 Mask */ -#define SGPIO_MASK_I_MASK_I27_Pos 27 /*!< SGPIO MASK_I: MASK_I27 Position */ -#define SGPIO_MASK_I_MASK_I27_Msk (0x01UL << SGPIO_MASK_I_MASK_I27_Pos) /*!< SGPIO MASK_I: MASK_I27 Mask */ -#define SGPIO_MASK_I_MASK_I28_Pos 28 /*!< SGPIO MASK_I: MASK_I28 Position */ -#define SGPIO_MASK_I_MASK_I28_Msk (0x01UL << SGPIO_MASK_I_MASK_I28_Pos) /*!< SGPIO MASK_I: MASK_I28 Mask */ -#define SGPIO_MASK_I_MASK_I29_Pos 29 /*!< SGPIO MASK_I: MASK_I29 Position */ -#define SGPIO_MASK_I_MASK_I29_Msk (0x01UL << SGPIO_MASK_I_MASK_I29_Pos) /*!< SGPIO MASK_I: MASK_I29 Mask */ -#define SGPIO_MASK_I_MASK_I30_Pos 30 /*!< SGPIO MASK_I: MASK_I30 Position */ -#define SGPIO_MASK_I_MASK_I30_Msk (0x01UL << SGPIO_MASK_I_MASK_I30_Pos) /*!< SGPIO MASK_I: MASK_I30 Mask */ -#define SGPIO_MASK_I_MASK_I31_Pos 31 /*!< SGPIO MASK_I: MASK_I31 Position */ -#define SGPIO_MASK_I_MASK_I31_Msk (0x01UL << SGPIO_MASK_I_MASK_I31_Pos) /*!< SGPIO MASK_I: MASK_I31 Mask */ - -// -------------------------------------- SGPIO_MASK_P ------------------------------------------ -#define SGPIO_MASK_P_MASK_P0_Pos 0 /*!< SGPIO MASK_P: MASK_P0 Position */ -#define SGPIO_MASK_P_MASK_P0_Msk (0x01UL << SGPIO_MASK_P_MASK_P0_Pos) /*!< SGPIO MASK_P: MASK_P0 Mask */ -#define SGPIO_MASK_P_MASK_P1_Pos 1 /*!< SGPIO MASK_P: MASK_P1 Position */ -#define SGPIO_MASK_P_MASK_P1_Msk (0x01UL << SGPIO_MASK_P_MASK_P1_Pos) /*!< SGPIO MASK_P: MASK_P1 Mask */ -#define SGPIO_MASK_P_MASK_P2_Pos 2 /*!< SGPIO MASK_P: MASK_P2 Position */ -#define SGPIO_MASK_P_MASK_P2_Msk (0x01UL << SGPIO_MASK_P_MASK_P2_Pos) /*!< SGPIO MASK_P: MASK_P2 Mask */ -#define SGPIO_MASK_P_MASK_P3_Pos 3 /*!< SGPIO MASK_P: MASK_P3 Position */ -#define SGPIO_MASK_P_MASK_P3_Msk (0x01UL << SGPIO_MASK_P_MASK_P3_Pos) /*!< SGPIO MASK_P: MASK_P3 Mask */ -#define SGPIO_MASK_P_MASK_P4_Pos 4 /*!< SGPIO MASK_P: MASK_P4 Position */ -#define SGPIO_MASK_P_MASK_P4_Msk (0x01UL << SGPIO_MASK_P_MASK_P4_Pos) /*!< SGPIO MASK_P: MASK_P4 Mask */ -#define SGPIO_MASK_P_MASK_P5_Pos 5 /*!< SGPIO MASK_P: MASK_P5 Position */ -#define SGPIO_MASK_P_MASK_P5_Msk (0x01UL << SGPIO_MASK_P_MASK_P5_Pos) /*!< SGPIO MASK_P: MASK_P5 Mask */ -#define SGPIO_MASK_P_MASK_P6_Pos 6 /*!< SGPIO MASK_P: MASK_P6 Position */ -#define SGPIO_MASK_P_MASK_P6_Msk (0x01UL << SGPIO_MASK_P_MASK_P6_Pos) /*!< SGPIO MASK_P: MASK_P6 Mask */ -#define SGPIO_MASK_P_MASK_P7_Pos 7 /*!< SGPIO MASK_P: MASK_P7 Position */ -#define SGPIO_MASK_P_MASK_P7_Msk (0x01UL << SGPIO_MASK_P_MASK_P7_Pos) /*!< SGPIO MASK_P: MASK_P7 Mask */ -#define SGPIO_MASK_P_MASK_P8_Pos 8 /*!< SGPIO MASK_P: MASK_P8 Position */ -#define SGPIO_MASK_P_MASK_P8_Msk (0x01UL << SGPIO_MASK_P_MASK_P8_Pos) /*!< SGPIO MASK_P: MASK_P8 Mask */ -#define SGPIO_MASK_P_MASK_P9_Pos 9 /*!< SGPIO MASK_P: MASK_P9 Position */ -#define SGPIO_MASK_P_MASK_P9_Msk (0x01UL << SGPIO_MASK_P_MASK_P9_Pos) /*!< SGPIO MASK_P: MASK_P9 Mask */ -#define SGPIO_MASK_P_MASK_P10_Pos 10 /*!< SGPIO MASK_P: MASK_P10 Position */ -#define SGPIO_MASK_P_MASK_P10_Msk (0x01UL << SGPIO_MASK_P_MASK_P10_Pos) /*!< SGPIO MASK_P: MASK_P10 Mask */ -#define SGPIO_MASK_P_MASK_P11_Pos 11 /*!< SGPIO MASK_P: MASK_P11 Position */ -#define SGPIO_MASK_P_MASK_P11_Msk (0x01UL << SGPIO_MASK_P_MASK_P11_Pos) /*!< SGPIO MASK_P: MASK_P11 Mask */ -#define SGPIO_MASK_P_MASK_P12_Pos 12 /*!< SGPIO MASK_P: MASK_P12 Position */ -#define SGPIO_MASK_P_MASK_P12_Msk (0x01UL << SGPIO_MASK_P_MASK_P12_Pos) /*!< SGPIO MASK_P: MASK_P12 Mask */ -#define SGPIO_MASK_P_MASK_P13_Pos 13 /*!< SGPIO MASK_P: MASK_P13 Position */ -#define SGPIO_MASK_P_MASK_P13_Msk (0x01UL << SGPIO_MASK_P_MASK_P13_Pos) /*!< SGPIO MASK_P: MASK_P13 Mask */ -#define SGPIO_MASK_P_MASK_P14_Pos 14 /*!< SGPIO MASK_P: MASK_P14 Position */ -#define SGPIO_MASK_P_MASK_P14_Msk (0x01UL << SGPIO_MASK_P_MASK_P14_Pos) /*!< SGPIO MASK_P: MASK_P14 Mask */ -#define SGPIO_MASK_P_MASK_P15_Pos 15 /*!< SGPIO MASK_P: MASK_P15 Position */ -#define SGPIO_MASK_P_MASK_P15_Msk (0x01UL << SGPIO_MASK_P_MASK_P15_Pos) /*!< SGPIO MASK_P: MASK_P15 Mask */ -#define SGPIO_MASK_P_MASK_P16_Pos 16 /*!< SGPIO MASK_P: MASK_P16 Position */ -#define SGPIO_MASK_P_MASK_P16_Msk (0x01UL << SGPIO_MASK_P_MASK_P16_Pos) /*!< SGPIO MASK_P: MASK_P16 Mask */ -#define SGPIO_MASK_P_MASK_P17_Pos 17 /*!< SGPIO MASK_P: MASK_P17 Position */ -#define SGPIO_MASK_P_MASK_P17_Msk (0x01UL << SGPIO_MASK_P_MASK_P17_Pos) /*!< SGPIO MASK_P: MASK_P17 Mask */ -#define SGPIO_MASK_P_MASK_P18_Pos 18 /*!< SGPIO MASK_P: MASK_P18 Position */ -#define SGPIO_MASK_P_MASK_P18_Msk (0x01UL << SGPIO_MASK_P_MASK_P18_Pos) /*!< SGPIO MASK_P: MASK_P18 Mask */ -#define SGPIO_MASK_P_MASK_P19_Pos 19 /*!< SGPIO MASK_P: MASK_P19 Position */ -#define SGPIO_MASK_P_MASK_P19_Msk (0x01UL << SGPIO_MASK_P_MASK_P19_Pos) /*!< SGPIO MASK_P: MASK_P19 Mask */ -#define SGPIO_MASK_P_MASK_P20_Pos 20 /*!< SGPIO MASK_P: MASK_P20 Position */ -#define SGPIO_MASK_P_MASK_P20_Msk (0x01UL << SGPIO_MASK_P_MASK_P20_Pos) /*!< SGPIO MASK_P: MASK_P20 Mask */ -#define SGPIO_MASK_P_MASK_P21_Pos 21 /*!< SGPIO MASK_P: MASK_P21 Position */ -#define SGPIO_MASK_P_MASK_P21_Msk (0x01UL << SGPIO_MASK_P_MASK_P21_Pos) /*!< SGPIO MASK_P: MASK_P21 Mask */ -#define SGPIO_MASK_P_MASK_P22_Pos 22 /*!< SGPIO MASK_P: MASK_P22 Position */ -#define SGPIO_MASK_P_MASK_P22_Msk (0x01UL << SGPIO_MASK_P_MASK_P22_Pos) /*!< SGPIO MASK_P: MASK_P22 Mask */ -#define SGPIO_MASK_P_MASK_P23_Pos 23 /*!< SGPIO MASK_P: MASK_P23 Position */ -#define SGPIO_MASK_P_MASK_P23_Msk (0x01UL << SGPIO_MASK_P_MASK_P23_Pos) /*!< SGPIO MASK_P: MASK_P23 Mask */ -#define SGPIO_MASK_P_MASK_P24_Pos 24 /*!< SGPIO MASK_P: MASK_P24 Position */ -#define SGPIO_MASK_P_MASK_P24_Msk (0x01UL << SGPIO_MASK_P_MASK_P24_Pos) /*!< SGPIO MASK_P: MASK_P24 Mask */ -#define SGPIO_MASK_P_MASK_P25_Pos 25 /*!< SGPIO MASK_P: MASK_P25 Position */ -#define SGPIO_MASK_P_MASK_P25_Msk (0x01UL << SGPIO_MASK_P_MASK_P25_Pos) /*!< SGPIO MASK_P: MASK_P25 Mask */ -#define SGPIO_MASK_P_MASK_P26_Pos 26 /*!< SGPIO MASK_P: MASK_P26 Position */ -#define SGPIO_MASK_P_MASK_P26_Msk (0x01UL << SGPIO_MASK_P_MASK_P26_Pos) /*!< SGPIO MASK_P: MASK_P26 Mask */ -#define SGPIO_MASK_P_MASK_P27_Pos 27 /*!< SGPIO MASK_P: MASK_P27 Position */ -#define SGPIO_MASK_P_MASK_P27_Msk (0x01UL << SGPIO_MASK_P_MASK_P27_Pos) /*!< SGPIO MASK_P: MASK_P27 Mask */ -#define SGPIO_MASK_P_MASK_P28_Pos 28 /*!< SGPIO MASK_P: MASK_P28 Position */ -#define SGPIO_MASK_P_MASK_P28_Msk (0x01UL << SGPIO_MASK_P_MASK_P28_Pos) /*!< SGPIO MASK_P: MASK_P28 Mask */ -#define SGPIO_MASK_P_MASK_P29_Pos 29 /*!< SGPIO MASK_P: MASK_P29 Position */ -#define SGPIO_MASK_P_MASK_P29_Msk (0x01UL << SGPIO_MASK_P_MASK_P29_Pos) /*!< SGPIO MASK_P: MASK_P29 Mask */ -#define SGPIO_MASK_P_MASK_P30_Pos 30 /*!< SGPIO MASK_P: MASK_P30 Position */ -#define SGPIO_MASK_P_MASK_P30_Msk (0x01UL << SGPIO_MASK_P_MASK_P30_Pos) /*!< SGPIO MASK_P: MASK_P30 Mask */ -#define SGPIO_MASK_P_MASK_P31_Pos 31 /*!< SGPIO MASK_P: MASK_P31 Position */ -#define SGPIO_MASK_P_MASK_P31_Msk (0x01UL << SGPIO_MASK_P_MASK_P31_Pos) /*!< SGPIO MASK_P: MASK_P31 Mask */ - -// ------------------------------------ SGPIO_GPIO_INREG ---------------------------------------- -#define SGPIO_GPIO_INREG_GPIO_IN0_Pos 0 /*!< SGPIO GPIO_INREG: GPIO_IN0 Position */ -#define SGPIO_GPIO_INREG_GPIO_IN0_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN0_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN0 Mask */ -#define SGPIO_GPIO_INREG_GPIO_IN1_Pos 1 /*!< SGPIO GPIO_INREG: GPIO_IN1 Position */ -#define SGPIO_GPIO_INREG_GPIO_IN1_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN1_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN1 Mask */ -#define SGPIO_GPIO_INREG_GPIO_IN2_Pos 2 /*!< SGPIO GPIO_INREG: GPIO_IN2 Position */ -#define SGPIO_GPIO_INREG_GPIO_IN2_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN2_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN2 Mask */ -#define SGPIO_GPIO_INREG_GPIO_IN3_Pos 3 /*!< SGPIO GPIO_INREG: GPIO_IN3 Position */ -#define SGPIO_GPIO_INREG_GPIO_IN3_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN3_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN3 Mask */ -#define SGPIO_GPIO_INREG_GPIO_IN4_Pos 4 /*!< SGPIO GPIO_INREG: GPIO_IN4 Position */ -#define SGPIO_GPIO_INREG_GPIO_IN4_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN4_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN4 Mask */ -#define SGPIO_GPIO_INREG_GPIO_IN5_Pos 5 /*!< SGPIO GPIO_INREG: GPIO_IN5 Position */ -#define SGPIO_GPIO_INREG_GPIO_IN5_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN5_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN5 Mask */ -#define SGPIO_GPIO_INREG_GPIO_IN6_Pos 6 /*!< SGPIO GPIO_INREG: GPIO_IN6 Position */ -#define SGPIO_GPIO_INREG_GPIO_IN6_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN6_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN6 Mask */ -#define SGPIO_GPIO_INREG_GPIO_IN7_Pos 7 /*!< SGPIO GPIO_INREG: GPIO_IN7 Position */ -#define SGPIO_GPIO_INREG_GPIO_IN7_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN7_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN7 Mask */ -#define SGPIO_GPIO_INREG_GPIO_IN8_Pos 8 /*!< SGPIO GPIO_INREG: GPIO_IN8 Position */ -#define SGPIO_GPIO_INREG_GPIO_IN8_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN8_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN8 Mask */ -#define SGPIO_GPIO_INREG_GPIO_IN9_Pos 9 /*!< SGPIO GPIO_INREG: GPIO_IN9 Position */ -#define SGPIO_GPIO_INREG_GPIO_IN9_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN9_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN9 Mask */ -#define SGPIO_GPIO_INREG_GPIO_IN10_Pos 10 /*!< SGPIO GPIO_INREG: GPIO_IN10 Position */ -#define SGPIO_GPIO_INREG_GPIO_IN10_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN10_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN10 Mask */ -#define SGPIO_GPIO_INREG_GPIO_IN11_Pos 11 /*!< SGPIO GPIO_INREG: GPIO_IN11 Position */ -#define SGPIO_GPIO_INREG_GPIO_IN11_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN11_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN11 Mask */ -#define SGPIO_GPIO_INREG_GPIO_IN12_Pos 12 /*!< SGPIO GPIO_INREG: GPIO_IN12 Position */ -#define SGPIO_GPIO_INREG_GPIO_IN12_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN12_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN12 Mask */ -#define SGPIO_GPIO_INREG_GPIO_IN13_Pos 13 /*!< SGPIO GPIO_INREG: GPIO_IN13 Position */ -#define SGPIO_GPIO_INREG_GPIO_IN13_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN13_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN13 Mask */ -#define SGPIO_GPIO_INREG_GPIO_IN14_Pos 14 /*!< SGPIO GPIO_INREG: GPIO_IN14 Position */ -#define SGPIO_GPIO_INREG_GPIO_IN14_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN14_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN14 Mask */ -#define SGPIO_GPIO_INREG_GPIO_IN15_Pos 15 /*!< SGPIO GPIO_INREG: GPIO_IN15 Position */ -#define SGPIO_GPIO_INREG_GPIO_IN15_Msk (0x01UL << SGPIO_GPIO_INREG_GPIO_IN15_Pos) /*!< SGPIO GPIO_INREG: GPIO_IN15 Mask */ - -// ------------------------------------ SGPIO_GPIO_OUTREG --------------------------------------- -#define SGPIO_GPIO_OUTREG_GPIO_OUT0_Pos 0 /*!< SGPIO GPIO_OUTREG: GPIO_OUT0 Position */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT0_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT0_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT0 Mask */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT1_Pos 1 /*!< SGPIO GPIO_OUTREG: GPIO_OUT1 Position */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT1_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT1_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT1 Mask */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT2_Pos 2 /*!< SGPIO GPIO_OUTREG: GPIO_OUT2 Position */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT2_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT2_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT2 Mask */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT3_Pos 3 /*!< SGPIO GPIO_OUTREG: GPIO_OUT3 Position */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT3_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT3_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT3 Mask */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT4_Pos 4 /*!< SGPIO GPIO_OUTREG: GPIO_OUT4 Position */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT4_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT4_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT4 Mask */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT5_Pos 5 /*!< SGPIO GPIO_OUTREG: GPIO_OUT5 Position */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT5_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT5_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT5 Mask */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT6_Pos 6 /*!< SGPIO GPIO_OUTREG: GPIO_OUT6 Position */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT6_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT6_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT6 Mask */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT7_Pos 7 /*!< SGPIO GPIO_OUTREG: GPIO_OUT7 Position */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT7_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT7_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT7 Mask */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT8_Pos 8 /*!< SGPIO GPIO_OUTREG: GPIO_OUT8 Position */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT8_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT8_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT8 Mask */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT9_Pos 9 /*!< SGPIO GPIO_OUTREG: GPIO_OUT9 Position */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT9_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT9_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT9 Mask */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT10_Pos 10 /*!< SGPIO GPIO_OUTREG: GPIO_OUT10 Position */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT10_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT10_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT10 Mask */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT11_Pos 11 /*!< SGPIO GPIO_OUTREG: GPIO_OUT11 Position */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT11_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT11_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT11 Mask */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT12_Pos 12 /*!< SGPIO GPIO_OUTREG: GPIO_OUT12 Position */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT12_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT12_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT12 Mask */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT13_Pos 13 /*!< SGPIO GPIO_OUTREG: GPIO_OUT13 Position */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT13_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT13_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT13 Mask */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT14_Pos 14 /*!< SGPIO GPIO_OUTREG: GPIO_OUT14 Position */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT14_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT14_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT14 Mask */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT15_Pos 15 /*!< SGPIO GPIO_OUTREG: GPIO_OUT15 Position */ -#define SGPIO_GPIO_OUTREG_GPIO_OUT15_Msk (0x01UL << SGPIO_GPIO_OUTREG_GPIO_OUT15_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT15 Mask */ - -// ------------------------------------ SGPIO_GPIO_OENREG --------------------------------------- -#define SGPIO_GPIO_OENREG_GPIO_OE0_Pos 0 /*!< SGPIO GPIO_OENREG: GPIO_OE0 Position */ -#define SGPIO_GPIO_OENREG_GPIO_OE0_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE0_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE0 Mask */ -#define SGPIO_GPIO_OENREG_GPIO_OE1_Pos 1 /*!< SGPIO GPIO_OENREG: GPIO_OE1 Position */ -#define SGPIO_GPIO_OENREG_GPIO_OE1_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE1_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE1 Mask */ -#define SGPIO_GPIO_OENREG_GPIO_OE2_Pos 2 /*!< SGPIO GPIO_OENREG: GPIO_OE2 Position */ -#define SGPIO_GPIO_OENREG_GPIO_OE2_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE2_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE2 Mask */ -#define SGPIO_GPIO_OENREG_GPIO_OE3_Pos 3 /*!< SGPIO GPIO_OENREG: GPIO_OE3 Position */ -#define SGPIO_GPIO_OENREG_GPIO_OE3_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE3_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE3 Mask */ -#define SGPIO_GPIO_OENREG_GPIO_OE4_Pos 4 /*!< SGPIO GPIO_OENREG: GPIO_OE4 Position */ -#define SGPIO_GPIO_OENREG_GPIO_OE4_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE4_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE4 Mask */ -#define SGPIO_GPIO_OENREG_GPIO_OE5_Pos 5 /*!< SGPIO GPIO_OENREG: GPIO_OE5 Position */ -#define SGPIO_GPIO_OENREG_GPIO_OE5_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE5_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE5 Mask */ -#define SGPIO_GPIO_OENREG_GPIO_OE6_Pos 6 /*!< SGPIO GPIO_OENREG: GPIO_OE6 Position */ -#define SGPIO_GPIO_OENREG_GPIO_OE6_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE6_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE6 Mask */ -#define SGPIO_GPIO_OENREG_GPIO_OE7_Pos 7 /*!< SGPIO GPIO_OENREG: GPIO_OE7 Position */ -#define SGPIO_GPIO_OENREG_GPIO_OE7_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE7_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE7 Mask */ -#define SGPIO_GPIO_OENREG_GPIO_OE8_Pos 8 /*!< SGPIO GPIO_OENREG: GPIO_OE8 Position */ -#define SGPIO_GPIO_OENREG_GPIO_OE8_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE8_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE8 Mask */ -#define SGPIO_GPIO_OENREG_GPIO_OE9_Pos 9 /*!< SGPIO GPIO_OENREG: GPIO_OE9 Position */ -#define SGPIO_GPIO_OENREG_GPIO_OE9_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE9_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE9 Mask */ -#define SGPIO_GPIO_OENREG_GPIO_OE10_Pos 10 /*!< SGPIO GPIO_OENREG: GPIO_OE10 Position */ -#define SGPIO_GPIO_OENREG_GPIO_OE10_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE10_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE10 Mask */ -#define SGPIO_GPIO_OENREG_GPIO_OE11_Pos 11 /*!< SGPIO GPIO_OENREG: GPIO_OE11 Position */ -#define SGPIO_GPIO_OENREG_GPIO_OE11_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE11_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE11 Mask */ -#define SGPIO_GPIO_OENREG_GPIO_OE12_Pos 12 /*!< SGPIO GPIO_OENREG: GPIO_OE12 Position */ -#define SGPIO_GPIO_OENREG_GPIO_OE12_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE12_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE12 Mask */ -#define SGPIO_GPIO_OENREG_GPIO_OE13_Pos 13 /*!< SGPIO GPIO_OENREG: GPIO_OE13 Position */ -#define SGPIO_GPIO_OENREG_GPIO_OE13_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE13_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE13 Mask */ -#define SGPIO_GPIO_OENREG_GPIO_OE14_Pos 14 /*!< SGPIO GPIO_OENREG: GPIO_OE14 Position */ -#define SGPIO_GPIO_OENREG_GPIO_OE14_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE14_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE14 Mask */ -#define SGPIO_GPIO_OENREG_GPIO_OE15_Pos 15 /*!< SGPIO GPIO_OENREG: GPIO_OE15 Position */ -#define SGPIO_GPIO_OENREG_GPIO_OE15_Msk (0x01UL << SGPIO_GPIO_OENREG_GPIO_OE15_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE15 Mask */ - -// ----------------------------------- SGPIO_CTRL_ENABLED --------------------------------------- -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED0_Pos 0 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED0 Position */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED0_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED0_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED0 Mask */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED1_Pos 1 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED1 Position */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED1_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED1_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED1 Mask */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED2_Pos 2 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED2 Position */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED2_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED2_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED2 Mask */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED3_Pos 3 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED3 Position */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED3_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED3_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED3 Mask */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED4_Pos 4 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED4 Position */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED4_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED4_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED4 Mask */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED5_Pos 5 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED5 Position */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED5_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED5_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED5 Mask */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED6_Pos 6 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED6 Position */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED6_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED6_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED6 Mask */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED7_Pos 7 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED7 Position */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED7_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED7_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED7 Mask */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED8_Pos 8 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED8 Position */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED8_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED8_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED8 Mask */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED9_Pos 9 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED9 Position */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED9_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED9_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED9 Mask */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED10_Pos 10 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED10 Position */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED10_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED10_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED10 Mask */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED11_Pos 11 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED11 Position */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED11_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED11_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED11 Mask */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED12_Pos 12 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED12 Position */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED12_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED12_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED12 Mask */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED13_Pos 13 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED13 Position */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED13_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED13_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED13 Mask */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED14_Pos 14 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED14 Position */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED14_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED14_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED14 Mask */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED15_Pos 15 /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED15 Position */ -#define SGPIO_CTRL_ENABLED_CTRL_ENABLED15_Msk (0x01UL << SGPIO_CTRL_ENABLED_CTRL_ENABLED15_Pos) /*!< SGPIO CTRL_ENABLED: CTRL_ENABLED15 Mask */ - -// ----------------------------------- SGPIO_CTRL_DISABLED -------------------------------------- -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn0_Pos 0 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn0 Position */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn0_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn0_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn0 Mask */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn1_Pos 1 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn1 Position */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn1_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn1_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn1 Mask */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn2_Pos 2 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn2 Position */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn2_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn2_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn2 Mask */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn3_Pos 3 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn3 Position */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn3_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn3_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn3 Mask */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn4_Pos 4 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn4 Position */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn4_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn4_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn4 Mask */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn5_Pos 5 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn5 Position */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn5_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn5_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn5 Mask */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn6_Pos 6 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn6 Position */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn6_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn6_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn6 Mask */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn7_Pos 7 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn7 Position */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn7_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn7_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn7 Mask */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn8_Pos 8 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn8 Position */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn8_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn8_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn8 Mask */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn9_Pos 9 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn9 Position */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn9_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn9_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn9 Mask */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn10_Pos 10 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn10 Position */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn10_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn10_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn10 Mask */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn11_Pos 11 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn11 Position */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn11_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn11_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn11 Mask */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn12_Pos 12 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn12 Position */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn12_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn12_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn12 Mask */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn13_Pos 13 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn13 Position */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn13_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn13_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn13 Mask */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn14_Pos 14 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn14 Position */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn14_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn14_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn14 Mask */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn15_Pos 15 /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn15 Position */ -#define SGPIO_CTRL_DISABLED_CTRL_DISABLEDn15_Msk (0x01UL << SGPIO_CTRL_DISABLED_CTRL_DISABLEDn15_Pos) /*!< SGPIO CTRL_DISABLED: CTRL_DISABLEDn15 Mask */ - -// ------------------------------------- SGPIO_CLR_EN_0 ----------------------------------------- -#define SGPIO_CLR_EN_0_CLR_SCI0_Pos 0 /*!< SGPIO CLR_EN_0: CLR_SCI0 Position */ -#define SGPIO_CLR_EN_0_CLR_SCI0_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI0_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI0 Mask */ -#define SGPIO_CLR_EN_0_CLR_SCI1_Pos 1 /*!< SGPIO CLR_EN_0: CLR_SCI1 Position */ -#define SGPIO_CLR_EN_0_CLR_SCI1_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI1_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI1 Mask */ -#define SGPIO_CLR_EN_0_CLR_SCI2_Pos 2 /*!< SGPIO CLR_EN_0: CLR_SCI2 Position */ -#define SGPIO_CLR_EN_0_CLR_SCI2_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI2_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI2 Mask */ -#define SGPIO_CLR_EN_0_CLR_SCI3_Pos 3 /*!< SGPIO CLR_EN_0: CLR_SCI3 Position */ -#define SGPIO_CLR_EN_0_CLR_SCI3_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI3_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI3 Mask */ -#define SGPIO_CLR_EN_0_CLR_SCI4_Pos 4 /*!< SGPIO CLR_EN_0: CLR_SCI4 Position */ -#define SGPIO_CLR_EN_0_CLR_SCI4_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI4_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI4 Mask */ -#define SGPIO_CLR_EN_0_CLR_SCI5_Pos 5 /*!< SGPIO CLR_EN_0: CLR_SCI5 Position */ -#define SGPIO_CLR_EN_0_CLR_SCI5_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI5_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI5 Mask */ -#define SGPIO_CLR_EN_0_CLR_SCI6_Pos 6 /*!< SGPIO CLR_EN_0: CLR_SCI6 Position */ -#define SGPIO_CLR_EN_0_CLR_SCI6_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI6_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI6 Mask */ -#define SGPIO_CLR_EN_0_CLR_SCI7_Pos 7 /*!< SGPIO CLR_EN_0: CLR_SCI7 Position */ -#define SGPIO_CLR_EN_0_CLR_SCI7_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI7_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI7 Mask */ -#define SGPIO_CLR_EN_0_CLR_SCI8_Pos 8 /*!< SGPIO CLR_EN_0: CLR_SCI8 Position */ -#define SGPIO_CLR_EN_0_CLR_SCI8_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI8_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI8 Mask */ -#define SGPIO_CLR_EN_0_CLR_SCI9_Pos 9 /*!< SGPIO CLR_EN_0: CLR_SCI9 Position */ -#define SGPIO_CLR_EN_0_CLR_SCI9_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI9_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI9 Mask */ -#define SGPIO_CLR_EN_0_CLR_SCI10_Pos 10 /*!< SGPIO CLR_EN_0: CLR_SCI10 Position */ -#define SGPIO_CLR_EN_0_CLR_SCI10_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI10_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI10 Mask */ -#define SGPIO_CLR_EN_0_CLR_SCI11_Pos 11 /*!< SGPIO CLR_EN_0: CLR_SCI11 Position */ -#define SGPIO_CLR_EN_0_CLR_SCI11_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI11_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI11 Mask */ -#define SGPIO_CLR_EN_0_CLR_SCI12_Pos 12 /*!< SGPIO CLR_EN_0: CLR_SCI12 Position */ -#define SGPIO_CLR_EN_0_CLR_SCI12_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI12_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI12 Mask */ -#define SGPIO_CLR_EN_0_CLR_SCI13_Pos 13 /*!< SGPIO CLR_EN_0: CLR_SCI13 Position */ -#define SGPIO_CLR_EN_0_CLR_SCI13_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI13_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI13 Mask */ -#define SGPIO_CLR_EN_0_CLR_SCI14_Pos 14 /*!< SGPIO CLR_EN_0: CLR_SCI14 Position */ -#define SGPIO_CLR_EN_0_CLR_SCI14_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI14_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI14 Mask */ -#define SGPIO_CLR_EN_0_CLR_SCI15_Pos 15 /*!< SGPIO CLR_EN_0: CLR_SCI15 Position */ -#define SGPIO_CLR_EN_0_CLR_SCI15_Msk (0x01UL << SGPIO_CLR_EN_0_CLR_SCI15_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI15 Mask */ - -// ------------------------------------- SGPIO_SET_EN_0 ----------------------------------------- -#define SGPIO_SET_EN_0_SET_SCI0_Pos 0 /*!< SGPIO SET_EN_0: SET_SCI0 Position */ -#define SGPIO_SET_EN_0_SET_SCI0_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI0_Pos) /*!< SGPIO SET_EN_0: SET_SCI0 Mask */ -#define SGPIO_SET_EN_0_SET_SCI1_Pos 1 /*!< SGPIO SET_EN_0: SET_SCI1 Position */ -#define SGPIO_SET_EN_0_SET_SCI1_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI1_Pos) /*!< SGPIO SET_EN_0: SET_SCI1 Mask */ -#define SGPIO_SET_EN_0_SET_SCI2_Pos 2 /*!< SGPIO SET_EN_0: SET_SCI2 Position */ -#define SGPIO_SET_EN_0_SET_SCI2_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI2_Pos) /*!< SGPIO SET_EN_0: SET_SCI2 Mask */ -#define SGPIO_SET_EN_0_SET_SCI3_Pos 3 /*!< SGPIO SET_EN_0: SET_SCI3 Position */ -#define SGPIO_SET_EN_0_SET_SCI3_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI3_Pos) /*!< SGPIO SET_EN_0: SET_SCI3 Mask */ -#define SGPIO_SET_EN_0_SET_SCI4_Pos 4 /*!< SGPIO SET_EN_0: SET_SCI4 Position */ -#define SGPIO_SET_EN_0_SET_SCI4_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI4_Pos) /*!< SGPIO SET_EN_0: SET_SCI4 Mask */ -#define SGPIO_SET_EN_0_SET_SCI5_Pos 5 /*!< SGPIO SET_EN_0: SET_SCI5 Position */ -#define SGPIO_SET_EN_0_SET_SCI5_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI5_Pos) /*!< SGPIO SET_EN_0: SET_SCI5 Mask */ -#define SGPIO_SET_EN_0_SET_SCI6_Pos 6 /*!< SGPIO SET_EN_0: SET_SCI6 Position */ -#define SGPIO_SET_EN_0_SET_SCI6_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI6_Pos) /*!< SGPIO SET_EN_0: SET_SCI6 Mask */ -#define SGPIO_SET_EN_0_SET_SCI7_Pos 7 /*!< SGPIO SET_EN_0: SET_SCI7 Position */ -#define SGPIO_SET_EN_0_SET_SCI7_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI7_Pos) /*!< SGPIO SET_EN_0: SET_SCI7 Mask */ -#define SGPIO_SET_EN_0_SET_SCI8_Pos 8 /*!< SGPIO SET_EN_0: SET_SCI8 Position */ -#define SGPIO_SET_EN_0_SET_SCI8_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI8_Pos) /*!< SGPIO SET_EN_0: SET_SCI8 Mask */ -#define SGPIO_SET_EN_0_SET_SCI9_Pos 9 /*!< SGPIO SET_EN_0: SET_SCI9 Position */ -#define SGPIO_SET_EN_0_SET_SCI9_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI9_Pos) /*!< SGPIO SET_EN_0: SET_SCI9 Mask */ -#define SGPIO_SET_EN_0_SET_SCI10_Pos 10 /*!< SGPIO SET_EN_0: SET_SCI10 Position */ -#define SGPIO_SET_EN_0_SET_SCI10_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI10_Pos) /*!< SGPIO SET_EN_0: SET_SCI10 Mask */ -#define SGPIO_SET_EN_0_SET_SCI11_Pos 11 /*!< SGPIO SET_EN_0: SET_SCI11 Position */ -#define SGPIO_SET_EN_0_SET_SCI11_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI11_Pos) /*!< SGPIO SET_EN_0: SET_SCI11 Mask */ -#define SGPIO_SET_EN_0_SET_SCI12_Pos 12 /*!< SGPIO SET_EN_0: SET_SCI12 Position */ -#define SGPIO_SET_EN_0_SET_SCI12_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI12_Pos) /*!< SGPIO SET_EN_0: SET_SCI12 Mask */ -#define SGPIO_SET_EN_0_SET_SCI13_Pos 13 /*!< SGPIO SET_EN_0: SET_SCI13 Position */ -#define SGPIO_SET_EN_0_SET_SCI13_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI13_Pos) /*!< SGPIO SET_EN_0: SET_SCI13 Mask */ -#define SGPIO_SET_EN_0_SET_SCI14_Pos 14 /*!< SGPIO SET_EN_0: SET_SCI14 Position */ -#define SGPIO_SET_EN_0_SET_SCI14_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI14_Pos) /*!< SGPIO SET_EN_0: SET_SCI14 Mask */ -#define SGPIO_SET_EN_0_SET_SCI15_Pos 15 /*!< SGPIO SET_EN_0: SET_SCI15 Position */ -#define SGPIO_SET_EN_0_SET_SCI15_Msk (0x01UL << SGPIO_SET_EN_0_SET_SCI15_Pos) /*!< SGPIO SET_EN_0: SET_SCI15 Mask */ - -// ------------------------------------- SGPIO_ENABLE_0 ----------------------------------------- -#define SGPIO_ENABLE_0_ENABLE_SCI0_Pos 0 /*!< SGPIO ENABLE_0: ENABLE_SCI0 Position */ -#define SGPIO_ENABLE_0_ENABLE_SCI0_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI0_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI0 Mask */ -#define SGPIO_ENABLE_0_ENABLE_SCI1_Pos 1 /*!< SGPIO ENABLE_0: ENABLE_SCI1 Position */ -#define SGPIO_ENABLE_0_ENABLE_SCI1_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI1_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI1 Mask */ -#define SGPIO_ENABLE_0_ENABLE_SCI2_Pos 2 /*!< SGPIO ENABLE_0: ENABLE_SCI2 Position */ -#define SGPIO_ENABLE_0_ENABLE_SCI2_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI2_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI2 Mask */ -#define SGPIO_ENABLE_0_ENABLE_SCI3_Pos 3 /*!< SGPIO ENABLE_0: ENABLE_SCI3 Position */ -#define SGPIO_ENABLE_0_ENABLE_SCI3_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI3_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI3 Mask */ -#define SGPIO_ENABLE_0_ENABLE_SCI4_Pos 4 /*!< SGPIO ENABLE_0: ENABLE_SCI4 Position */ -#define SGPIO_ENABLE_0_ENABLE_SCI4_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI4_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI4 Mask */ -#define SGPIO_ENABLE_0_ENABLE_SCI5_Pos 5 /*!< SGPIO ENABLE_0: ENABLE_SCI5 Position */ -#define SGPIO_ENABLE_0_ENABLE_SCI5_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI5_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI5 Mask */ -#define SGPIO_ENABLE_0_ENABLE_SCI6_Pos 6 /*!< SGPIO ENABLE_0: ENABLE_SCI6 Position */ -#define SGPIO_ENABLE_0_ENABLE_SCI6_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI6_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI6 Mask */ -#define SGPIO_ENABLE_0_ENABLE_SCI7_Pos 7 /*!< SGPIO ENABLE_0: ENABLE_SCI7 Position */ -#define SGPIO_ENABLE_0_ENABLE_SCI7_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI7_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI7 Mask */ -#define SGPIO_ENABLE_0_ENABLE_SCI8_Pos 8 /*!< SGPIO ENABLE_0: ENABLE_SCI8 Position */ -#define SGPIO_ENABLE_0_ENABLE_SCI8_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI8_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI8 Mask */ -#define SGPIO_ENABLE_0_ENABLE_SCI9_Pos 9 /*!< SGPIO ENABLE_0: ENABLE_SCI9 Position */ -#define SGPIO_ENABLE_0_ENABLE_SCI9_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI9_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI9 Mask */ -#define SGPIO_ENABLE_0_ENABLE_SCI10_Pos 10 /*!< SGPIO ENABLE_0: ENABLE_SCI10 Position */ -#define SGPIO_ENABLE_0_ENABLE_SCI10_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI10_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI10 Mask */ -#define SGPIO_ENABLE_0_ENABLE_SCI11_Pos 11 /*!< SGPIO ENABLE_0: ENABLE_SCI11 Position */ -#define SGPIO_ENABLE_0_ENABLE_SCI11_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI11_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI11 Mask */ -#define SGPIO_ENABLE_0_ENABLE_SCI12_Pos 12 /*!< SGPIO ENABLE_0: ENABLE_SCI12 Position */ -#define SGPIO_ENABLE_0_ENABLE_SCI12_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI12_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI12 Mask */ -#define SGPIO_ENABLE_0_ENABLE_SCI13_Pos 13 /*!< SGPIO ENABLE_0: ENABLE_SCI13 Position */ -#define SGPIO_ENABLE_0_ENABLE_SCI13_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI13_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI13 Mask */ -#define SGPIO_ENABLE_0_ENABLE_SCI14_Pos 14 /*!< SGPIO ENABLE_0: ENABLE_SCI14 Position */ -#define SGPIO_ENABLE_0_ENABLE_SCI14_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI14_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI14 Mask */ -#define SGPIO_ENABLE_0_ENABLE_SCI15_Pos 15 /*!< SGPIO ENABLE_0: ENABLE_SCI15 Position */ -#define SGPIO_ENABLE_0_ENABLE_SCI15_Msk (0x01UL << SGPIO_ENABLE_0_ENABLE_SCI15_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI15 Mask */ - -// ------------------------------------- SGPIO_STATUS_0 ----------------------------------------- -#define SGPIO_STATUS_0_STATUS_SCI0_Pos 0 /*!< SGPIO STATUS_0: STATUS_SCI0 Position */ -#define SGPIO_STATUS_0_STATUS_SCI0_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI0_Pos) /*!< SGPIO STATUS_0: STATUS_SCI0 Mask */ -#define SGPIO_STATUS_0_STATUS_SCI1_Pos 1 /*!< SGPIO STATUS_0: STATUS_SCI1 Position */ -#define SGPIO_STATUS_0_STATUS_SCI1_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI1_Pos) /*!< SGPIO STATUS_0: STATUS_SCI1 Mask */ -#define SGPIO_STATUS_0_STATUS_SCI2_Pos 2 /*!< SGPIO STATUS_0: STATUS_SCI2 Position */ -#define SGPIO_STATUS_0_STATUS_SCI2_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI2_Pos) /*!< SGPIO STATUS_0: STATUS_SCI2 Mask */ -#define SGPIO_STATUS_0_STATUS_SCI3_Pos 3 /*!< SGPIO STATUS_0: STATUS_SCI3 Position */ -#define SGPIO_STATUS_0_STATUS_SCI3_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI3_Pos) /*!< SGPIO STATUS_0: STATUS_SCI3 Mask */ -#define SGPIO_STATUS_0_STATUS_SCI4_Pos 4 /*!< SGPIO STATUS_0: STATUS_SCI4 Position */ -#define SGPIO_STATUS_0_STATUS_SCI4_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI4_Pos) /*!< SGPIO STATUS_0: STATUS_SCI4 Mask */ -#define SGPIO_STATUS_0_STATUS_SCI5_Pos 5 /*!< SGPIO STATUS_0: STATUS_SCI5 Position */ -#define SGPIO_STATUS_0_STATUS_SCI5_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI5_Pos) /*!< SGPIO STATUS_0: STATUS_SCI5 Mask */ -#define SGPIO_STATUS_0_STATUS_SCI6_Pos 6 /*!< SGPIO STATUS_0: STATUS_SCI6 Position */ -#define SGPIO_STATUS_0_STATUS_SCI6_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI6_Pos) /*!< SGPIO STATUS_0: STATUS_SCI6 Mask */ -#define SGPIO_STATUS_0_STATUS_SCI7_Pos 7 /*!< SGPIO STATUS_0: STATUS_SCI7 Position */ -#define SGPIO_STATUS_0_STATUS_SCI7_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI7_Pos) /*!< SGPIO STATUS_0: STATUS_SCI7 Mask */ -#define SGPIO_STATUS_0_STATUS_SCI8_Pos 8 /*!< SGPIO STATUS_0: STATUS_SCI8 Position */ -#define SGPIO_STATUS_0_STATUS_SCI8_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI8_Pos) /*!< SGPIO STATUS_0: STATUS_SCI8 Mask */ -#define SGPIO_STATUS_0_STATUS_SCI9_Pos 9 /*!< SGPIO STATUS_0: STATUS_SCI9 Position */ -#define SGPIO_STATUS_0_STATUS_SCI9_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI9_Pos) /*!< SGPIO STATUS_0: STATUS_SCI9 Mask */ -#define SGPIO_STATUS_0_STATUS_SCI10_Pos 10 /*!< SGPIO STATUS_0: STATUS_SCI10 Position */ -#define SGPIO_STATUS_0_STATUS_SCI10_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI10_Pos) /*!< SGPIO STATUS_0: STATUS_SCI10 Mask */ -#define SGPIO_STATUS_0_STATUS_SCI11_Pos 11 /*!< SGPIO STATUS_0: STATUS_SCI11 Position */ -#define SGPIO_STATUS_0_STATUS_SCI11_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI11_Pos) /*!< SGPIO STATUS_0: STATUS_SCI11 Mask */ -#define SGPIO_STATUS_0_STATUS_SCI12_Pos 12 /*!< SGPIO STATUS_0: STATUS_SCI12 Position */ -#define SGPIO_STATUS_0_STATUS_SCI12_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI12_Pos) /*!< SGPIO STATUS_0: STATUS_SCI12 Mask */ -#define SGPIO_STATUS_0_STATUS_SCI13_Pos 13 /*!< SGPIO STATUS_0: STATUS_SCI13 Position */ -#define SGPIO_STATUS_0_STATUS_SCI13_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI13_Pos) /*!< SGPIO STATUS_0: STATUS_SCI13 Mask */ -#define SGPIO_STATUS_0_STATUS_SCI14_Pos 14 /*!< SGPIO STATUS_0: STATUS_SCI14 Position */ -#define SGPIO_STATUS_0_STATUS_SCI14_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI14_Pos) /*!< SGPIO STATUS_0: STATUS_SCI14 Mask */ -#define SGPIO_STATUS_0_STATUS_SCI15_Pos 15 /*!< SGPIO STATUS_0: STATUS_SCI15 Position */ -#define SGPIO_STATUS_0_STATUS_SCI15_Msk (0x01UL << SGPIO_STATUS_0_STATUS_SCI15_Pos) /*!< SGPIO STATUS_0: STATUS_SCI15 Mask */ - -// ----------------------------------- SGPIO_CTR_STATUS_0 --------------------------------------- -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI0_Pos 0 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI0 Position */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI0_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI0_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI0 Mask */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI1_Pos 1 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI1 Position */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI1_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI1_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI1 Mask */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI2_Pos 2 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI2 Position */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI2_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI2_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI2 Mask */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI3_Pos 3 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI3 Position */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI3_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI3_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI3 Mask */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI4_Pos 4 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI4 Position */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI4_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI4_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI4 Mask */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI5_Pos 5 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI5 Position */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI5_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI5_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI5 Mask */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI6_Pos 6 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI6 Position */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI6_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI6_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI6 Mask */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI7_Pos 7 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI7 Position */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI7_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI7_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI7 Mask */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI8_Pos 8 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI8 Position */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI8_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI8_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI8 Mask */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI9_Pos 9 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI9 Position */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI9_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI9_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI9 Mask */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI10_Pos 10 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI10 Position */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI10_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI10_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI10 Mask */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI11_Pos 11 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI11 Position */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI11_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI11_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI11 Mask */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI12_Pos 12 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI12 Position */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI12_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI12_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI12 Mask */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI13_Pos 13 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI13 Position */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI13_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI13_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI13 Mask */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI14_Pos 14 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI14 Position */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI14_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI14_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI14 Mask */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI15_Pos 15 /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI15 Position */ -#define SGPIO_CTR_STATUS_0_CTR_STATUS_SCI15_Msk (0x01UL << SGPIO_CTR_STATUS_0_CTR_STATUS_SCI15_Pos) /*!< SGPIO CTR_STATUS_0: CTR_STATUS_SCI15 Mask */ - -// ----------------------------------- SGPIO_SET_STATUS_0 --------------------------------------- -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI0_Pos 0 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI0 Position */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI0_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI0_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI0 Mask */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI1_Pos 1 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI1 Position */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI1_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI1_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI1 Mask */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI2_Pos 2 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI2 Position */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI2_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI2_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI2 Mask */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI3_Pos 3 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI3 Position */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI3_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI3_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI3 Mask */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI4_Pos 4 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI4 Position */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI4_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI4_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI4 Mask */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI5_Pos 5 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI5 Position */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI5_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI5_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI5 Mask */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI6_Pos 6 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI6 Position */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI6_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI6_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI6 Mask */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI7_Pos 7 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI7 Position */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI7_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI7_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI7 Mask */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI8_Pos 8 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI8 Position */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI8_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI8_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI8 Mask */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI9_Pos 9 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI9 Position */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI9_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI9_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI9 Mask */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI10_Pos 10 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI10 Position */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI10_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI10_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI10 Mask */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI11_Pos 11 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI11 Position */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI11_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI11_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI11 Mask */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI12_Pos 12 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI12 Position */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI12_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI12_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI12 Mask */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI13_Pos 13 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI13 Position */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI13_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI13_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI13 Mask */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI14_Pos 14 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI14 Position */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI14_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI14_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI14 Mask */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI15_Pos 15 /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI15 Position */ -#define SGPIO_SET_STATUS_0_CTR_STATUS_SCI15_Msk (0x01UL << SGPIO_SET_STATUS_0_CTR_STATUS_SCI15_Pos) /*!< SGPIO SET_STATUS_0: CTR_STATUS_SCI15 Mask */ - -// ------------------------------------- SGPIO_CLR_EN_1 ----------------------------------------- -#define SGPIO_CLR_EN_1_CLR_EN_CCI0_Pos 0 /*!< SGPIO CLR_EN_1: CLR_EN_CCI0 Position */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI0_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI0_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI0 Mask */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI1_Pos 1 /*!< SGPIO CLR_EN_1: CLR_EN_CCI1 Position */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI1_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI1_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI1 Mask */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI2_Pos 2 /*!< SGPIO CLR_EN_1: CLR_EN_CCI2 Position */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI2_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI2_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI2 Mask */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI3_Pos 3 /*!< SGPIO CLR_EN_1: CLR_EN_CCI3 Position */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI3_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI3_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI3 Mask */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI4_Pos 4 /*!< SGPIO CLR_EN_1: CLR_EN_CCI4 Position */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI4_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI4_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI4 Mask */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI5_Pos 5 /*!< SGPIO CLR_EN_1: CLR_EN_CCI5 Position */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI5_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI5_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI5 Mask */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI6_Pos 6 /*!< SGPIO CLR_EN_1: CLR_EN_CCI6 Position */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI6_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI6_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI6 Mask */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI7_Pos 7 /*!< SGPIO CLR_EN_1: CLR_EN_CCI7 Position */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI7_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI7_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI7 Mask */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI8_Pos 8 /*!< SGPIO CLR_EN_1: CLR_EN_CCI8 Position */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI8_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI8_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI8 Mask */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI9_Pos 9 /*!< SGPIO CLR_EN_1: CLR_EN_CCI9 Position */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI9_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI9_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI9 Mask */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI10_Pos 10 /*!< SGPIO CLR_EN_1: CLR_EN_CCI10 Position */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI10_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI10_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI10 Mask */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI11_Pos 11 /*!< SGPIO CLR_EN_1: CLR_EN_CCI11 Position */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI11_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI11_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI11 Mask */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI12_Pos 12 /*!< SGPIO CLR_EN_1: CLR_EN_CCI12 Position */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI12_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI12_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI12 Mask */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI13_Pos 13 /*!< SGPIO CLR_EN_1: CLR_EN_CCI13 Position */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI13_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI13_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI13 Mask */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI14_Pos 14 /*!< SGPIO CLR_EN_1: CLR_EN_CCI14 Position */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI14_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI14_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI14 Mask */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI15_Pos 15 /*!< SGPIO CLR_EN_1: CLR_EN_CCI15 Position */ -#define SGPIO_CLR_EN_1_CLR_EN_CCI15_Msk (0x01UL << SGPIO_CLR_EN_1_CLR_EN_CCI15_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI15 Mask */ - -// ------------------------------------- SGPIO_SET_EN_1 ----------------------------------------- -#define SGPIO_SET_EN_1_SET_EN_CCI0_Pos 0 /*!< SGPIO SET_EN_1: SET_EN_CCI0 Position */ -#define SGPIO_SET_EN_1_SET_EN_CCI0_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI0_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI0 Mask */ -#define SGPIO_SET_EN_1_SET_EN_CCI1_Pos 1 /*!< SGPIO SET_EN_1: SET_EN_CCI1 Position */ -#define SGPIO_SET_EN_1_SET_EN_CCI1_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI1_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI1 Mask */ -#define SGPIO_SET_EN_1_SET_EN_CCI2_Pos 2 /*!< SGPIO SET_EN_1: SET_EN_CCI2 Position */ -#define SGPIO_SET_EN_1_SET_EN_CCI2_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI2_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI2 Mask */ -#define SGPIO_SET_EN_1_SET_EN_CCI3_Pos 3 /*!< SGPIO SET_EN_1: SET_EN_CCI3 Position */ -#define SGPIO_SET_EN_1_SET_EN_CCI3_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI3_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI3 Mask */ -#define SGPIO_SET_EN_1_SET_EN_CCI4_Pos 4 /*!< SGPIO SET_EN_1: SET_EN_CCI4 Position */ -#define SGPIO_SET_EN_1_SET_EN_CCI4_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI4_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI4 Mask */ -#define SGPIO_SET_EN_1_SET_EN_CCI5_Pos 5 /*!< SGPIO SET_EN_1: SET_EN_CCI5 Position */ -#define SGPIO_SET_EN_1_SET_EN_CCI5_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI5_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI5 Mask */ -#define SGPIO_SET_EN_1_SET_EN_CCI6_Pos 6 /*!< SGPIO SET_EN_1: SET_EN_CCI6 Position */ -#define SGPIO_SET_EN_1_SET_EN_CCI6_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI6_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI6 Mask */ -#define SGPIO_SET_EN_1_SET_EN_CCI7_Pos 7 /*!< SGPIO SET_EN_1: SET_EN_CCI7 Position */ -#define SGPIO_SET_EN_1_SET_EN_CCI7_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI7_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI7 Mask */ -#define SGPIO_SET_EN_1_SET_EN_CCI8_Pos 8 /*!< SGPIO SET_EN_1: SET_EN_CCI8 Position */ -#define SGPIO_SET_EN_1_SET_EN_CCI8_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI8_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI8 Mask */ -#define SGPIO_SET_EN_1_SET_EN_CCI9_Pos 9 /*!< SGPIO SET_EN_1: SET_EN_CCI9 Position */ -#define SGPIO_SET_EN_1_SET_EN_CCI9_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI9_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI9 Mask */ -#define SGPIO_SET_EN_1_SET_EN_CCI10_Pos 10 /*!< SGPIO SET_EN_1: SET_EN_CCI10 Position */ -#define SGPIO_SET_EN_1_SET_EN_CCI10_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI10_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI10 Mask */ -#define SGPIO_SET_EN_1_SET_EN_CCI11_Pos 11 /*!< SGPIO SET_EN_1: SET_EN_CCI11 Position */ -#define SGPIO_SET_EN_1_SET_EN_CCI11_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI11_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI11 Mask */ -#define SGPIO_SET_EN_1_SET_EN_CCI12_Pos 12 /*!< SGPIO SET_EN_1: SET_EN_CCI12 Position */ -#define SGPIO_SET_EN_1_SET_EN_CCI12_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI12_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI12 Mask */ -#define SGPIO_SET_EN_1_SET_EN_CCI13_Pos 13 /*!< SGPIO SET_EN_1: SET_EN_CCI13 Position */ -#define SGPIO_SET_EN_1_SET_EN_CCI13_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI13_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI13 Mask */ -#define SGPIO_SET_EN_1_SET_EN_CCI14_Pos 14 /*!< SGPIO SET_EN_1: SET_EN_CCI14 Position */ -#define SGPIO_SET_EN_1_SET_EN_CCI14_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI14_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI14 Mask */ -#define SGPIO_SET_EN_1_SET_EN_CCI15_Pos 15 /*!< SGPIO SET_EN_1: SET_EN_CCI15 Position */ -#define SGPIO_SET_EN_1_SET_EN_CCI15_Msk (0x01UL << SGPIO_SET_EN_1_SET_EN_CCI15_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI15 Mask */ - -// ------------------------------------- SGPIO_ENABLE_1 ----------------------------------------- -#define SGPIO_ENABLE_1_ENABLE_CCI0_Pos 0 /*!< SGPIO ENABLE_1: ENABLE_CCI0 Position */ -#define SGPIO_ENABLE_1_ENABLE_CCI0_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI0_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI0 Mask */ -#define SGPIO_ENABLE_1_ENABLE_CCI1_Pos 1 /*!< SGPIO ENABLE_1: ENABLE_CCI1 Position */ -#define SGPIO_ENABLE_1_ENABLE_CCI1_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI1_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI1 Mask */ -#define SGPIO_ENABLE_1_ENABLE_CCI2_Pos 2 /*!< SGPIO ENABLE_1: ENABLE_CCI2 Position */ -#define SGPIO_ENABLE_1_ENABLE_CCI2_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI2_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI2 Mask */ -#define SGPIO_ENABLE_1_ENABLE_CCI3_Pos 3 /*!< SGPIO ENABLE_1: ENABLE_CCI3 Position */ -#define SGPIO_ENABLE_1_ENABLE_CCI3_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI3_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI3 Mask */ -#define SGPIO_ENABLE_1_ENABLE_CCI4_Pos 4 /*!< SGPIO ENABLE_1: ENABLE_CCI4 Position */ -#define SGPIO_ENABLE_1_ENABLE_CCI4_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI4_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI4 Mask */ -#define SGPIO_ENABLE_1_ENABLE_CCI5_Pos 5 /*!< SGPIO ENABLE_1: ENABLE_CCI5 Position */ -#define SGPIO_ENABLE_1_ENABLE_CCI5_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI5_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI5 Mask */ -#define SGPIO_ENABLE_1_ENABLE_CCI6_Pos 6 /*!< SGPIO ENABLE_1: ENABLE_CCI6 Position */ -#define SGPIO_ENABLE_1_ENABLE_CCI6_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI6_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI6 Mask */ -#define SGPIO_ENABLE_1_ENABLE_CCI7_Pos 7 /*!< SGPIO ENABLE_1: ENABLE_CCI7 Position */ -#define SGPIO_ENABLE_1_ENABLE_CCI7_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI7_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI7 Mask */ -#define SGPIO_ENABLE_1_ENABLE_CCI8_Pos 8 /*!< SGPIO ENABLE_1: ENABLE_CCI8 Position */ -#define SGPIO_ENABLE_1_ENABLE_CCI8_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI8_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI8 Mask */ -#define SGPIO_ENABLE_1_ENABLE_CCI9_Pos 9 /*!< SGPIO ENABLE_1: ENABLE_CCI9 Position */ -#define SGPIO_ENABLE_1_ENABLE_CCI9_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI9_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI9 Mask */ -#define SGPIO_ENABLE_1_ENABLE_CCI10_Pos 10 /*!< SGPIO ENABLE_1: ENABLE_CCI10 Position */ -#define SGPIO_ENABLE_1_ENABLE_CCI10_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI10_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI10 Mask */ -#define SGPIO_ENABLE_1_ENABLE_CCI11_Pos 11 /*!< SGPIO ENABLE_1: ENABLE_CCI11 Position */ -#define SGPIO_ENABLE_1_ENABLE_CCI11_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI11_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI11 Mask */ -#define SGPIO_ENABLE_1_ENABLE_CCI12_Pos 12 /*!< SGPIO ENABLE_1: ENABLE_CCI12 Position */ -#define SGPIO_ENABLE_1_ENABLE_CCI12_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI12_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI12 Mask */ -#define SGPIO_ENABLE_1_ENABLE_CCI13_Pos 13 /*!< SGPIO ENABLE_1: ENABLE_CCI13 Position */ -#define SGPIO_ENABLE_1_ENABLE_CCI13_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI13_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI13 Mask */ -#define SGPIO_ENABLE_1_ENABLE_CCI14_Pos 14 /*!< SGPIO ENABLE_1: ENABLE_CCI14 Position */ -#define SGPIO_ENABLE_1_ENABLE_CCI14_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI14_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI14 Mask */ -#define SGPIO_ENABLE_1_ENABLE_CCI15_Pos 15 /*!< SGPIO ENABLE_1: ENABLE_CCI15 Position */ -#define SGPIO_ENABLE_1_ENABLE_CCI15_Msk (0x01UL << SGPIO_ENABLE_1_ENABLE_CCI15_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI15 Mask */ - -// ------------------------------------- SGPIO_STATUS_1 ----------------------------------------- -#define SGPIO_STATUS_1_STATUS_CCI0_Pos 0 /*!< SGPIO STATUS_1: STATUS_CCI0 Position */ -#define SGPIO_STATUS_1_STATUS_CCI0_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI0_Pos) /*!< SGPIO STATUS_1: STATUS_CCI0 Mask */ -#define SGPIO_STATUS_1_STATUS_CCI1_Pos 1 /*!< SGPIO STATUS_1: STATUS_CCI1 Position */ -#define SGPIO_STATUS_1_STATUS_CCI1_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI1_Pos) /*!< SGPIO STATUS_1: STATUS_CCI1 Mask */ -#define SGPIO_STATUS_1_STATUS_CCI2_Pos 2 /*!< SGPIO STATUS_1: STATUS_CCI2 Position */ -#define SGPIO_STATUS_1_STATUS_CCI2_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI2_Pos) /*!< SGPIO STATUS_1: STATUS_CCI2 Mask */ -#define SGPIO_STATUS_1_STATUS_CCI3_Pos 3 /*!< SGPIO STATUS_1: STATUS_CCI3 Position */ -#define SGPIO_STATUS_1_STATUS_CCI3_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI3_Pos) /*!< SGPIO STATUS_1: STATUS_CCI3 Mask */ -#define SGPIO_STATUS_1_STATUS_CCI4_Pos 4 /*!< SGPIO STATUS_1: STATUS_CCI4 Position */ -#define SGPIO_STATUS_1_STATUS_CCI4_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI4_Pos) /*!< SGPIO STATUS_1: STATUS_CCI4 Mask */ -#define SGPIO_STATUS_1_STATUS_CCI5_Pos 5 /*!< SGPIO STATUS_1: STATUS_CCI5 Position */ -#define SGPIO_STATUS_1_STATUS_CCI5_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI5_Pos) /*!< SGPIO STATUS_1: STATUS_CCI5 Mask */ -#define SGPIO_STATUS_1_STATUS_CCI6_Pos 6 /*!< SGPIO STATUS_1: STATUS_CCI6 Position */ -#define SGPIO_STATUS_1_STATUS_CCI6_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI6_Pos) /*!< SGPIO STATUS_1: STATUS_CCI6 Mask */ -#define SGPIO_STATUS_1_STATUS_CCI7_Pos 7 /*!< SGPIO STATUS_1: STATUS_CCI7 Position */ -#define SGPIO_STATUS_1_STATUS_CCI7_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI7_Pos) /*!< SGPIO STATUS_1: STATUS_CCI7 Mask */ -#define SGPIO_STATUS_1_STATUS_CCI8_Pos 8 /*!< SGPIO STATUS_1: STATUS_CCI8 Position */ -#define SGPIO_STATUS_1_STATUS_CCI8_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI8_Pos) /*!< SGPIO STATUS_1: STATUS_CCI8 Mask */ -#define SGPIO_STATUS_1_STATUS_CCI9_Pos 9 /*!< SGPIO STATUS_1: STATUS_CCI9 Position */ -#define SGPIO_STATUS_1_STATUS_CCI9_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI9_Pos) /*!< SGPIO STATUS_1: STATUS_CCI9 Mask */ -#define SGPIO_STATUS_1_STATUS_CCI10_Pos 10 /*!< SGPIO STATUS_1: STATUS_CCI10 Position */ -#define SGPIO_STATUS_1_STATUS_CCI10_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI10_Pos) /*!< SGPIO STATUS_1: STATUS_CCI10 Mask */ -#define SGPIO_STATUS_1_STATUS_CCI11_Pos 11 /*!< SGPIO STATUS_1: STATUS_CCI11 Position */ -#define SGPIO_STATUS_1_STATUS_CCI11_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI11_Pos) /*!< SGPIO STATUS_1: STATUS_CCI11 Mask */ -#define SGPIO_STATUS_1_STATUS_CCI12_Pos 12 /*!< SGPIO STATUS_1: STATUS_CCI12 Position */ -#define SGPIO_STATUS_1_STATUS_CCI12_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI12_Pos) /*!< SGPIO STATUS_1: STATUS_CCI12 Mask */ -#define SGPIO_STATUS_1_STATUS_CCI13_Pos 13 /*!< SGPIO STATUS_1: STATUS_CCI13 Position */ -#define SGPIO_STATUS_1_STATUS_CCI13_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI13_Pos) /*!< SGPIO STATUS_1: STATUS_CCI13 Mask */ -#define SGPIO_STATUS_1_STATUS_CCI14_Pos 14 /*!< SGPIO STATUS_1: STATUS_CCI14 Position */ -#define SGPIO_STATUS_1_STATUS_CCI14_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI14_Pos) /*!< SGPIO STATUS_1: STATUS_CCI14 Mask */ -#define SGPIO_STATUS_1_STATUS_CCI15_Pos 15 /*!< SGPIO STATUS_1: STATUS_CCI15 Position */ -#define SGPIO_STATUS_1_STATUS_CCI15_Msk (0x01UL << SGPIO_STATUS_1_STATUS_CCI15_Pos) /*!< SGPIO STATUS_1: STATUS_CCI15 Mask */ - -// ----------------------------------- SGPIO_CTR_STATUS_1 --------------------------------------- -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI0_Pos 0 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI0 Position */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI0_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI0_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI0 Mask */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI1_Pos 1 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI1 Position */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI1_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI1_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI1 Mask */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI2_Pos 2 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI2 Position */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI2_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI2_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI2 Mask */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI3_Pos 3 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI3 Position */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI3_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI3_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI3 Mask */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI4_Pos 4 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI4 Position */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI4_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI4_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI4 Mask */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI5_Pos 5 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI5 Position */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI5_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI5_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI5 Mask */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI6_Pos 6 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI6 Position */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI6_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI6_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI6 Mask */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI7_Pos 7 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI7 Position */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI7_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI7_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI7 Mask */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI8_Pos 8 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI8 Position */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI8_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI8_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI8 Mask */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI9_Pos 9 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI9 Position */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI9_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI9_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI9 Mask */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI10_Pos 10 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI10 Position */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI10_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI10_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI10 Mask */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI11_Pos 11 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI11 Position */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI11_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI11_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI11 Mask */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI12_Pos 12 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI12 Position */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI12_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI12_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI12 Mask */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI13_Pos 13 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI13 Position */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI13_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI13_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI13 Mask */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI14_Pos 14 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI14 Position */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI14_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI14_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI14 Mask */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI15_Pos 15 /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI15 Position */ -#define SGPIO_CTR_STATUS_1_CTR_STATUS_CCI15_Msk (0x01UL << SGPIO_CTR_STATUS_1_CTR_STATUS_CCI15_Pos) /*!< SGPIO CTR_STATUS_1: CTR_STATUS_CCI15 Mask */ - -// ----------------------------------- SGPIO_SET_STATUS_1 --------------------------------------- -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI0_Pos 0 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI0 Position */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI0_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI0_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI0 Mask */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI1_Pos 1 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI1 Position */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI1_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI1_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI1 Mask */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI2_Pos 2 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI2 Position */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI2_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI2_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI2 Mask */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI3_Pos 3 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI3 Position */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI3_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI3_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI3 Mask */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI4_Pos 4 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI4 Position */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI4_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI4_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI4 Mask */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI5_Pos 5 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI5 Position */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI5_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI5_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI5 Mask */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI6_Pos 6 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI6 Position */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI6_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI6_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI6 Mask */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI7_Pos 7 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI7 Position */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI7_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI7_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI7 Mask */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI8_Pos 8 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI8 Position */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI8_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI8_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI8 Mask */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI9_Pos 9 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI9 Position */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI9_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI9_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI9 Mask */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI10_Pos 10 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI10 Position */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI10_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI10_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI10 Mask */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI11_Pos 11 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI11 Position */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI11_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI11_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI11 Mask */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI12_Pos 12 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI12 Position */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI12_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI12_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI12 Mask */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI13_Pos 13 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI13 Position */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI13_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI13_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI13 Mask */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI14_Pos 14 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI14 Position */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI14_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI14_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI14 Mask */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI15_Pos 15 /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI15 Position */ -#define SGPIO_SET_STATUS_1_CTR_STATUS_CCI15_Msk (0x01UL << SGPIO_SET_STATUS_1_CTR_STATUS_CCI15_Pos) /*!< SGPIO SET_STATUS_1: CTR_STATUS_CCI15 Mask */ - -// ------------------------------------- SGPIO_CLR_EN_2 ----------------------------------------- -#define SGPIO_CLR_EN_2_CLR_EN2_PMI0_Pos 0 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI0 Position */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI0_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI0_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI0 Mask */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI1_Pos 1 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI1 Position */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI1_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI1_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI1 Mask */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI2_Pos 2 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI2 Position */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI2_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI2_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI2 Mask */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI3_Pos 3 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI3 Position */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI3_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI3_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI3 Mask */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI4_Pos 4 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI4 Position */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI4_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI4_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI4 Mask */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI5_Pos 5 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI5 Position */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI5_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI5_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI5 Mask */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI6_Pos 6 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI6 Position */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI6_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI6_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI6 Mask */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI7_Pos 7 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI7 Position */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI7_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI7_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI7 Mask */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI8_Pos 8 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI8 Position */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI8_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI8_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI8 Mask */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI9_Pos 9 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI9 Position */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI9_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI9_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI9 Mask */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI10_Pos 10 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI10 Position */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI10_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI10_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI10 Mask */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI11_Pos 11 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI11 Position */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI11_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI11_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI11 Mask */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI12_Pos 12 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI12 Position */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI12_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI12_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI12 Mask */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI13_Pos 13 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI13 Position */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI13_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI13_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI13 Mask */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI14_Pos 14 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI14 Position */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI14_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI14_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI14 Mask */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI15_Pos 15 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI15 Position */ -#define SGPIO_CLR_EN_2_CLR_EN2_PMI15_Msk (0x01UL << SGPIO_CLR_EN_2_CLR_EN2_PMI15_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI15 Mask */ - -// ------------------------------------- SGPIO_SET_EN_2 ----------------------------------------- -#define SGPIO_SET_EN_2_SET_EN_PMI0_Pos 0 /*!< SGPIO SET_EN_2: SET_EN_PMI0 Position */ -#define SGPIO_SET_EN_2_SET_EN_PMI0_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI0_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI0 Mask */ -#define SGPIO_SET_EN_2_SET_EN_PMI1_Pos 1 /*!< SGPIO SET_EN_2: SET_EN_PMI1 Position */ -#define SGPIO_SET_EN_2_SET_EN_PMI1_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI1_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI1 Mask */ -#define SGPIO_SET_EN_2_SET_EN_PMI2_Pos 2 /*!< SGPIO SET_EN_2: SET_EN_PMI2 Position */ -#define SGPIO_SET_EN_2_SET_EN_PMI2_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI2_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI2 Mask */ -#define SGPIO_SET_EN_2_SET_EN_PMI3_Pos 3 /*!< SGPIO SET_EN_2: SET_EN_PMI3 Position */ -#define SGPIO_SET_EN_2_SET_EN_PMI3_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI3_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI3 Mask */ -#define SGPIO_SET_EN_2_SET_EN_PMI4_Pos 4 /*!< SGPIO SET_EN_2: SET_EN_PMI4 Position */ -#define SGPIO_SET_EN_2_SET_EN_PMI4_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI4_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI4 Mask */ -#define SGPIO_SET_EN_2_SET_EN_PMI5_Pos 5 /*!< SGPIO SET_EN_2: SET_EN_PMI5 Position */ -#define SGPIO_SET_EN_2_SET_EN_PMI5_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI5_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI5 Mask */ -#define SGPIO_SET_EN_2_SET_EN_PMI6_Pos 6 /*!< SGPIO SET_EN_2: SET_EN_PMI6 Position */ -#define SGPIO_SET_EN_2_SET_EN_PMI6_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI6_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI6 Mask */ -#define SGPIO_SET_EN_2_SET_EN_PMI7_Pos 7 /*!< SGPIO SET_EN_2: SET_EN_PMI7 Position */ -#define SGPIO_SET_EN_2_SET_EN_PMI7_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI7_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI7 Mask */ -#define SGPIO_SET_EN_2_SET_EN_PMI8_Pos 8 /*!< SGPIO SET_EN_2: SET_EN_PMI8 Position */ -#define SGPIO_SET_EN_2_SET_EN_PMI8_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI8_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI8 Mask */ -#define SGPIO_SET_EN_2_SET_EN_PMI9_Pos 9 /*!< SGPIO SET_EN_2: SET_EN_PMI9 Position */ -#define SGPIO_SET_EN_2_SET_EN_PMI9_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI9_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI9 Mask */ -#define SGPIO_SET_EN_2_SET_EN_PMI10_Pos 10 /*!< SGPIO SET_EN_2: SET_EN_PMI10 Position */ -#define SGPIO_SET_EN_2_SET_EN_PMI10_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI10_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI10 Mask */ -#define SGPIO_SET_EN_2_SET_EN_PMI11_Pos 11 /*!< SGPIO SET_EN_2: SET_EN_PMI11 Position */ -#define SGPIO_SET_EN_2_SET_EN_PMI11_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI11_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI11 Mask */ -#define SGPIO_SET_EN_2_SET_EN_PMI12_Pos 12 /*!< SGPIO SET_EN_2: SET_EN_PMI12 Position */ -#define SGPIO_SET_EN_2_SET_EN_PMI12_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI12_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI12 Mask */ -#define SGPIO_SET_EN_2_SET_EN_PMI13_Pos 13 /*!< SGPIO SET_EN_2: SET_EN_PMI13 Position */ -#define SGPIO_SET_EN_2_SET_EN_PMI13_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI13_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI13 Mask */ -#define SGPIO_SET_EN_2_SET_EN_PMI14_Pos 14 /*!< SGPIO SET_EN_2: SET_EN_PMI14 Position */ -#define SGPIO_SET_EN_2_SET_EN_PMI14_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI14_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI14 Mask */ -#define SGPIO_SET_EN_2_SET_EN_PMI15_Pos 15 /*!< SGPIO SET_EN_2: SET_EN_PMI15 Position */ -#define SGPIO_SET_EN_2_SET_EN_PMI15_Msk (0x01UL << SGPIO_SET_EN_2_SET_EN_PMI15_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI15 Mask */ - -// ------------------------------------- SGPIO_ENABLE_2 ----------------------------------------- -#define SGPIO_ENABLE_2_ENABLE_PMI0_Pos 0 /*!< SGPIO ENABLE_2: ENABLE_PMI0 Position */ -#define SGPIO_ENABLE_2_ENABLE_PMI0_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI0_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI0 Mask */ -#define SGPIO_ENABLE_2_ENABLE_PMI1_Pos 1 /*!< SGPIO ENABLE_2: ENABLE_PMI1 Position */ -#define SGPIO_ENABLE_2_ENABLE_PMI1_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI1_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI1 Mask */ -#define SGPIO_ENABLE_2_ENABLE_PMI2_Pos 2 /*!< SGPIO ENABLE_2: ENABLE_PMI2 Position */ -#define SGPIO_ENABLE_2_ENABLE_PMI2_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI2_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI2 Mask */ -#define SGPIO_ENABLE_2_ENABLE_PMI3_Pos 3 /*!< SGPIO ENABLE_2: ENABLE_PMI3 Position */ -#define SGPIO_ENABLE_2_ENABLE_PMI3_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI3_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI3 Mask */ -#define SGPIO_ENABLE_2_ENABLE_PMI4_Pos 4 /*!< SGPIO ENABLE_2: ENABLE_PMI4 Position */ -#define SGPIO_ENABLE_2_ENABLE_PMI4_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI4_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI4 Mask */ -#define SGPIO_ENABLE_2_ENABLE_PMI5_Pos 5 /*!< SGPIO ENABLE_2: ENABLE_PMI5 Position */ -#define SGPIO_ENABLE_2_ENABLE_PMI5_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI5_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI5 Mask */ -#define SGPIO_ENABLE_2_ENABLE_PMI6_Pos 6 /*!< SGPIO ENABLE_2: ENABLE_PMI6 Position */ -#define SGPIO_ENABLE_2_ENABLE_PMI6_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI6_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI6 Mask */ -#define SGPIO_ENABLE_2_ENABLE_PMI7_Pos 7 /*!< SGPIO ENABLE_2: ENABLE_PMI7 Position */ -#define SGPIO_ENABLE_2_ENABLE_PMI7_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI7_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI7 Mask */ -#define SGPIO_ENABLE_2_ENABLE_PMI8_Pos 8 /*!< SGPIO ENABLE_2: ENABLE_PMI8 Position */ -#define SGPIO_ENABLE_2_ENABLE_PMI8_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI8_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI8 Mask */ -#define SGPIO_ENABLE_2_ENABLE_PMI9_Pos 9 /*!< SGPIO ENABLE_2: ENABLE_PMI9 Position */ -#define SGPIO_ENABLE_2_ENABLE_PMI9_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI9_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI9 Mask */ -#define SGPIO_ENABLE_2_ENABLE_PMI10_Pos 10 /*!< SGPIO ENABLE_2: ENABLE_PMI10 Position */ -#define SGPIO_ENABLE_2_ENABLE_PMI10_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI10_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI10 Mask */ -#define SGPIO_ENABLE_2_ENABLE_PMI11_Pos 11 /*!< SGPIO ENABLE_2: ENABLE_PMI11 Position */ -#define SGPIO_ENABLE_2_ENABLE_PMI11_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI11_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI11 Mask */ -#define SGPIO_ENABLE_2_ENABLE_PMI12_Pos 12 /*!< SGPIO ENABLE_2: ENABLE_PMI12 Position */ -#define SGPIO_ENABLE_2_ENABLE_PMI12_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI12_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI12 Mask */ -#define SGPIO_ENABLE_2_ENABLE_PMI13_Pos 13 /*!< SGPIO ENABLE_2: ENABLE_PMI13 Position */ -#define SGPIO_ENABLE_2_ENABLE_PMI13_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI13_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI13 Mask */ -#define SGPIO_ENABLE_2_ENABLE_PMI14_Pos 14 /*!< SGPIO ENABLE_2: ENABLE_PMI14 Position */ -#define SGPIO_ENABLE_2_ENABLE_PMI14_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI14_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI14 Mask */ -#define SGPIO_ENABLE_2_ENABLE_PMI15_Pos 15 /*!< SGPIO ENABLE_2: ENABLE_PMI15 Position */ -#define SGPIO_ENABLE_2_ENABLE_PMI15_Msk (0x01UL << SGPIO_ENABLE_2_ENABLE_PMI15_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI15 Mask */ - -// ------------------------------------- SGPIO_STATUS_2 ----------------------------------------- -#define SGPIO_STATUS_2_STATUS_PMI0_Pos 0 /*!< SGPIO STATUS_2: STATUS_PMI0 Position */ -#define SGPIO_STATUS_2_STATUS_PMI0_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI0_Pos) /*!< SGPIO STATUS_2: STATUS_PMI0 Mask */ -#define SGPIO_STATUS_2_STATUS_PMI1_Pos 1 /*!< SGPIO STATUS_2: STATUS_PMI1 Position */ -#define SGPIO_STATUS_2_STATUS_PMI1_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI1_Pos) /*!< SGPIO STATUS_2: STATUS_PMI1 Mask */ -#define SGPIO_STATUS_2_STATUS_PMI2_Pos 2 /*!< SGPIO STATUS_2: STATUS_PMI2 Position */ -#define SGPIO_STATUS_2_STATUS_PMI2_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI2_Pos) /*!< SGPIO STATUS_2: STATUS_PMI2 Mask */ -#define SGPIO_STATUS_2_STATUS_PMI3_Pos 3 /*!< SGPIO STATUS_2: STATUS_PMI3 Position */ -#define SGPIO_STATUS_2_STATUS_PMI3_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI3_Pos) /*!< SGPIO STATUS_2: STATUS_PMI3 Mask */ -#define SGPIO_STATUS_2_STATUS_PMI4_Pos 4 /*!< SGPIO STATUS_2: STATUS_PMI4 Position */ -#define SGPIO_STATUS_2_STATUS_PMI4_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI4_Pos) /*!< SGPIO STATUS_2: STATUS_PMI4 Mask */ -#define SGPIO_STATUS_2_STATUS_PMI5_Pos 5 /*!< SGPIO STATUS_2: STATUS_PMI5 Position */ -#define SGPIO_STATUS_2_STATUS_PMI5_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI5_Pos) /*!< SGPIO STATUS_2: STATUS_PMI5 Mask */ -#define SGPIO_STATUS_2_STATUS_PMI6_Pos 6 /*!< SGPIO STATUS_2: STATUS_PMI6 Position */ -#define SGPIO_STATUS_2_STATUS_PMI6_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI6_Pos) /*!< SGPIO STATUS_2: STATUS_PMI6 Mask */ -#define SGPIO_STATUS_2_STATUS_PMI7_Pos 7 /*!< SGPIO STATUS_2: STATUS_PMI7 Position */ -#define SGPIO_STATUS_2_STATUS_PMI7_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI7_Pos) /*!< SGPIO STATUS_2: STATUS_PMI7 Mask */ -#define SGPIO_STATUS_2_STATUS_PMI8_Pos 8 /*!< SGPIO STATUS_2: STATUS_PMI8 Position */ -#define SGPIO_STATUS_2_STATUS_PMI8_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI8_Pos) /*!< SGPIO STATUS_2: STATUS_PMI8 Mask */ -#define SGPIO_STATUS_2_STATUS_PMI9_Pos 9 /*!< SGPIO STATUS_2: STATUS_PMI9 Position */ -#define SGPIO_STATUS_2_STATUS_PMI9_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI9_Pos) /*!< SGPIO STATUS_2: STATUS_PMI9 Mask */ -#define SGPIO_STATUS_2_STATUS_PMI10_Pos 10 /*!< SGPIO STATUS_2: STATUS_PMI10 Position */ -#define SGPIO_STATUS_2_STATUS_PMI10_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI10_Pos) /*!< SGPIO STATUS_2: STATUS_PMI10 Mask */ -#define SGPIO_STATUS_2_STATUS_PMI11_Pos 11 /*!< SGPIO STATUS_2: STATUS_PMI11 Position */ -#define SGPIO_STATUS_2_STATUS_PMI11_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI11_Pos) /*!< SGPIO STATUS_2: STATUS_PMI11 Mask */ -#define SGPIO_STATUS_2_STATUS_PMI12_Pos 12 /*!< SGPIO STATUS_2: STATUS_PMI12 Position */ -#define SGPIO_STATUS_2_STATUS_PMI12_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI12_Pos) /*!< SGPIO STATUS_2: STATUS_PMI12 Mask */ -#define SGPIO_STATUS_2_STATUS_PMI13_Pos 13 /*!< SGPIO STATUS_2: STATUS_PMI13 Position */ -#define SGPIO_STATUS_2_STATUS_PMI13_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI13_Pos) /*!< SGPIO STATUS_2: STATUS_PMI13 Mask */ -#define SGPIO_STATUS_2_STATUS_PMI14_Pos 14 /*!< SGPIO STATUS_2: STATUS_PMI14 Position */ -#define SGPIO_STATUS_2_STATUS_PMI14_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI14_Pos) /*!< SGPIO STATUS_2: STATUS_PMI14 Mask */ -#define SGPIO_STATUS_2_STATUS_PMI15_Pos 15 /*!< SGPIO STATUS_2: STATUS_PMI15 Position */ -#define SGPIO_STATUS_2_STATUS_PMI15_Msk (0x01UL << SGPIO_STATUS_2_STATUS_PMI15_Pos) /*!< SGPIO STATUS_2: STATUS_PMI15 Mask */ - -// ----------------------------------- SGPIO_CTR_STATUS_2 --------------------------------------- -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI0_Pos 0 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI0 Position */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI0_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI0_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI0 Mask */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI1_Pos 1 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI1 Position */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI1_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI1_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI1 Mask */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI2_Pos 2 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI2 Position */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI2_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI2_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI2 Mask */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI3_Pos 3 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI3 Position */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI3_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI3_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI3 Mask */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI4_Pos 4 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI4 Position */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI4_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI4_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI4 Mask */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI5_Pos 5 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI5 Position */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI5_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI5_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI5 Mask */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI6_Pos 6 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI6 Position */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI6_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI6_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI6 Mask */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI7_Pos 7 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI7 Position */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI7_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI7_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI7 Mask */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI8_Pos 8 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI8 Position */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI8_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI8_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI8 Mask */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI9_Pos 9 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI9 Position */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI9_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI9_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI9 Mask */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI10_Pos 10 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI10 Position */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI10_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI10_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI10 Mask */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI11_Pos 11 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI11 Position */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI11_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI11_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI11 Mask */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI12_Pos 12 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI12 Position */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI12_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI12_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI12 Mask */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI13_Pos 13 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI13 Position */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI13_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI13_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI13 Mask */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI14_Pos 14 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI14 Position */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI14_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI14_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI14 Mask */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI15_Pos 15 /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI15 Position */ -#define SGPIO_CTR_STATUS_2_CTR_STATUS_PMI15_Msk (0x01UL << SGPIO_CTR_STATUS_2_CTR_STATUS_PMI15_Pos) /*!< SGPIO CTR_STATUS_2: CTR_STATUS_PMI15 Mask */ - -// ----------------------------------- SGPIO_SET_STATUS_2 --------------------------------------- -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI0_Pos 0 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI0 Position */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI0_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI0_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI0 Mask */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI1_Pos 1 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI1 Position */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI1_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI1_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI1 Mask */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI2_Pos 2 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI2 Position */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI2_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI2_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI2 Mask */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI3_Pos 3 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI3 Position */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI3_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI3_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI3 Mask */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI4_Pos 4 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI4 Position */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI4_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI4_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI4 Mask */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI5_Pos 5 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI5 Position */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI5_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI5_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI5 Mask */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI6_Pos 6 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI6 Position */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI6_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI6_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI6 Mask */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI7_Pos 7 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI7 Position */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI7_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI7_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI7 Mask */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI8_Pos 8 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI8 Position */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI8_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI8_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI8 Mask */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI9_Pos 9 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI9 Position */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI9_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI9_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI9 Mask */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI10_Pos 10 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI10 Position */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI10_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI10_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI10 Mask */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI11_Pos 11 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI11 Position */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI11_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI11_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI11 Mask */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI12_Pos 12 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI12 Position */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI12_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI12_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI12 Mask */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI13_Pos 13 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI13 Position */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI13_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI13_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI13 Mask */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI14_Pos 14 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI14 Position */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI14_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI14_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI14 Mask */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI15_Pos 15 /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI15 Position */ -#define SGPIO_SET_STATUS_2_CTR_STATUS_PMI15_Msk (0x01UL << SGPIO_SET_STATUS_2_CTR_STATUS_PMI15_Pos) /*!< SGPIO SET_STATUS_2: CTR_STATUS_PMI15 Mask */ - -// ------------------------------------- SGPIO_CLR_EN_3 ----------------------------------------- -#define SGPIO_CLR_EN_3_CLR_EN_INPI0_Pos 0 /*!< SGPIO CLR_EN_3: CLR_EN_INPI0 Position */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI0_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI0_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI0 Mask */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI1_Pos 1 /*!< SGPIO CLR_EN_3: CLR_EN_INPI1 Position */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI1_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI1_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI1 Mask */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI2_Pos 2 /*!< SGPIO CLR_EN_3: CLR_EN_INPI2 Position */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI2_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI2_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI2 Mask */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI3_Pos 3 /*!< SGPIO CLR_EN_3: CLR_EN_INPI3 Position */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI3_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI3_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI3 Mask */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI4_Pos 4 /*!< SGPIO CLR_EN_3: CLR_EN_INPI4 Position */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI4_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI4_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI4 Mask */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI5_Pos 5 /*!< SGPIO CLR_EN_3: CLR_EN_INPI5 Position */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI5_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI5_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI5 Mask */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI6_Pos 6 /*!< SGPIO CLR_EN_3: CLR_EN_INPI6 Position */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI6_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI6_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI6 Mask */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI7_Pos 7 /*!< SGPIO CLR_EN_3: CLR_EN_INPI7 Position */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI7_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI7_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI7 Mask */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI8_Pos 8 /*!< SGPIO CLR_EN_3: CLR_EN_INPI8 Position */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI8_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI8_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI8 Mask */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI9_Pos 9 /*!< SGPIO CLR_EN_3: CLR_EN_INPI9 Position */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI9_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI9_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI9 Mask */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI10_Pos 10 /*!< SGPIO CLR_EN_3: CLR_EN_INPI10 Position */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI10_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI10_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI10 Mask */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI11_Pos 11 /*!< SGPIO CLR_EN_3: CLR_EN_INPI11 Position */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI11_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI11_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI11 Mask */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI12_Pos 12 /*!< SGPIO CLR_EN_3: CLR_EN_INPI12 Position */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI12_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI12_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI12 Mask */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI13_Pos 13 /*!< SGPIO CLR_EN_3: CLR_EN_INPI13 Position */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI13_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI13_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI13 Mask */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI14_Pos 14 /*!< SGPIO CLR_EN_3: CLR_EN_INPI14 Position */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI14_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI14_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI14 Mask */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI15_Pos 15 /*!< SGPIO CLR_EN_3: CLR_EN_INPI15 Position */ -#define SGPIO_CLR_EN_3_CLR_EN_INPI15_Msk (0x01UL << SGPIO_CLR_EN_3_CLR_EN_INPI15_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI15 Mask */ - -// ------------------------------------- SGPIO_SET_EN_3 ----------------------------------------- -#define SGPIO_SET_EN_3_SET_EN_INPI0_Pos 0 /*!< SGPIO SET_EN_3: SET_EN_INPI0 Position */ -#define SGPIO_SET_EN_3_SET_EN_INPI0_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI0_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI0 Mask */ -#define SGPIO_SET_EN_3_SET_EN_INPI1_Pos 1 /*!< SGPIO SET_EN_3: SET_EN_INPI1 Position */ -#define SGPIO_SET_EN_3_SET_EN_INPI1_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI1_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI1 Mask */ -#define SGPIO_SET_EN_3_SET_EN_INPI2_Pos 2 /*!< SGPIO SET_EN_3: SET_EN_INPI2 Position */ -#define SGPIO_SET_EN_3_SET_EN_INPI2_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI2_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI2 Mask */ -#define SGPIO_SET_EN_3_SET_EN_INPI3_Pos 3 /*!< SGPIO SET_EN_3: SET_EN_INPI3 Position */ -#define SGPIO_SET_EN_3_SET_EN_INPI3_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI3_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI3 Mask */ -#define SGPIO_SET_EN_3_SET_EN_INPI4_Pos 4 /*!< SGPIO SET_EN_3: SET_EN_INPI4 Position */ -#define SGPIO_SET_EN_3_SET_EN_INPI4_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI4_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI4 Mask */ -#define SGPIO_SET_EN_3_SET_EN_INPI5_Pos 5 /*!< SGPIO SET_EN_3: SET_EN_INPI5 Position */ -#define SGPIO_SET_EN_3_SET_EN_INPI5_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI5_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI5 Mask */ -#define SGPIO_SET_EN_3_SET_EN_INPI6_Pos 6 /*!< SGPIO SET_EN_3: SET_EN_INPI6 Position */ -#define SGPIO_SET_EN_3_SET_EN_INPI6_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI6_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI6 Mask */ -#define SGPIO_SET_EN_3_SET_EN_INPI7_Pos 7 /*!< SGPIO SET_EN_3: SET_EN_INPI7 Position */ -#define SGPIO_SET_EN_3_SET_EN_INPI7_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI7_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI7 Mask */ -#define SGPIO_SET_EN_3_SET_EN_INPI8_Pos 8 /*!< SGPIO SET_EN_3: SET_EN_INPI8 Position */ -#define SGPIO_SET_EN_3_SET_EN_INPI8_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI8_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI8 Mask */ -#define SGPIO_SET_EN_3_SET_EN_INPI9_Pos 9 /*!< SGPIO SET_EN_3: SET_EN_INPI9 Position */ -#define SGPIO_SET_EN_3_SET_EN_INPI9_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI9_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI9 Mask */ -#define SGPIO_SET_EN_3_SET_EN_INPI10_Pos 10 /*!< SGPIO SET_EN_3: SET_EN_INPI10 Position */ -#define SGPIO_SET_EN_3_SET_EN_INPI10_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI10_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI10 Mask */ -#define SGPIO_SET_EN_3_SET_EN_INPI11_Pos 11 /*!< SGPIO SET_EN_3: SET_EN_INPI11 Position */ -#define SGPIO_SET_EN_3_SET_EN_INPI11_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI11_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI11 Mask */ -#define SGPIO_SET_EN_3_SET_EN_INPI12_Pos 12 /*!< SGPIO SET_EN_3: SET_EN_INPI12 Position */ -#define SGPIO_SET_EN_3_SET_EN_INPI12_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI12_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI12 Mask */ -#define SGPIO_SET_EN_3_SET_EN_INPI13_Pos 13 /*!< SGPIO SET_EN_3: SET_EN_INPI13 Position */ -#define SGPIO_SET_EN_3_SET_EN_INPI13_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI13_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI13 Mask */ -#define SGPIO_SET_EN_3_SET_EN_INPI14_Pos 14 /*!< SGPIO SET_EN_3: SET_EN_INPI14 Position */ -#define SGPIO_SET_EN_3_SET_EN_INPI14_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI14_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI14 Mask */ -#define SGPIO_SET_EN_3_SET_EN_INPI15_Pos 15 /*!< SGPIO SET_EN_3: SET_EN_INPI15 Position */ -#define SGPIO_SET_EN_3_SET_EN_INPI15_Msk (0x01UL << SGPIO_SET_EN_3_SET_EN_INPI15_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI15 Mask */ - -// ------------------------------------- SGPIO_ENABLE_3 ----------------------------------------- -#define SGPIO_ENABLE_3_ENABLE3_INPI0_Pos 0 /*!< SGPIO ENABLE_3: ENABLE3_INPI0 Position */ -#define SGPIO_ENABLE_3_ENABLE3_INPI0_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI0_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI0 Mask */ -#define SGPIO_ENABLE_3_ENABLE3_INPI1_Pos 1 /*!< SGPIO ENABLE_3: ENABLE3_INPI1 Position */ -#define SGPIO_ENABLE_3_ENABLE3_INPI1_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI1_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI1 Mask */ -#define SGPIO_ENABLE_3_ENABLE3_INPI2_Pos 2 /*!< SGPIO ENABLE_3: ENABLE3_INPI2 Position */ -#define SGPIO_ENABLE_3_ENABLE3_INPI2_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI2_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI2 Mask */ -#define SGPIO_ENABLE_3_ENABLE3_INPI3_Pos 3 /*!< SGPIO ENABLE_3: ENABLE3_INPI3 Position */ -#define SGPIO_ENABLE_3_ENABLE3_INPI3_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI3_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI3 Mask */ -#define SGPIO_ENABLE_3_ENABLE3_INPI4_Pos 4 /*!< SGPIO ENABLE_3: ENABLE3_INPI4 Position */ -#define SGPIO_ENABLE_3_ENABLE3_INPI4_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI4_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI4 Mask */ -#define SGPIO_ENABLE_3_ENABLE3_INPI5_Pos 5 /*!< SGPIO ENABLE_3: ENABLE3_INPI5 Position */ -#define SGPIO_ENABLE_3_ENABLE3_INPI5_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI5_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI5 Mask */ -#define SGPIO_ENABLE_3_ENABLE3_INPI6_Pos 6 /*!< SGPIO ENABLE_3: ENABLE3_INPI6 Position */ -#define SGPIO_ENABLE_3_ENABLE3_INPI6_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI6_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI6 Mask */ -#define SGPIO_ENABLE_3_ENABLE3_INPI7_Pos 7 /*!< SGPIO ENABLE_3: ENABLE3_INPI7 Position */ -#define SGPIO_ENABLE_3_ENABLE3_INPI7_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI7_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI7 Mask */ -#define SGPIO_ENABLE_3_ENABLE3_INPI8_Pos 8 /*!< SGPIO ENABLE_3: ENABLE3_INPI8 Position */ -#define SGPIO_ENABLE_3_ENABLE3_INPI8_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI8_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI8 Mask */ -#define SGPIO_ENABLE_3_ENABLE3_INPI9_Pos 9 /*!< SGPIO ENABLE_3: ENABLE3_INPI9 Position */ -#define SGPIO_ENABLE_3_ENABLE3_INPI9_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI9_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI9 Mask */ -#define SGPIO_ENABLE_3_ENABLE3_INPI10_Pos 10 /*!< SGPIO ENABLE_3: ENABLE3_INPI10 Position */ -#define SGPIO_ENABLE_3_ENABLE3_INPI10_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI10_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI10 Mask */ -#define SGPIO_ENABLE_3_ENABLE3_INPI11_Pos 11 /*!< SGPIO ENABLE_3: ENABLE3_INPI11 Position */ -#define SGPIO_ENABLE_3_ENABLE3_INPI11_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI11_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI11 Mask */ -#define SGPIO_ENABLE_3_ENABLE3_INPI12_Pos 12 /*!< SGPIO ENABLE_3: ENABLE3_INPI12 Position */ -#define SGPIO_ENABLE_3_ENABLE3_INPI12_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI12_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI12 Mask */ -#define SGPIO_ENABLE_3_ENABLE3_INPI13_Pos 13 /*!< SGPIO ENABLE_3: ENABLE3_INPI13 Position */ -#define SGPIO_ENABLE_3_ENABLE3_INPI13_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI13_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI13 Mask */ -#define SGPIO_ENABLE_3_ENABLE3_INPI14_Pos 14 /*!< SGPIO ENABLE_3: ENABLE3_INPI14 Position */ -#define SGPIO_ENABLE_3_ENABLE3_INPI14_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI14_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI14 Mask */ -#define SGPIO_ENABLE_3_ENABLE3_INPI15_Pos 15 /*!< SGPIO ENABLE_3: ENABLE3_INPI15 Position */ -#define SGPIO_ENABLE_3_ENABLE3_INPI15_Msk (0x01UL << SGPIO_ENABLE_3_ENABLE3_INPI15_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI15 Mask */ - -// ------------------------------------- SGPIO_STATUS_3 ----------------------------------------- -#define SGPIO_STATUS_3_STATUS_INPI0_Pos 0 /*!< SGPIO STATUS_3: STATUS_INPI0 Position */ -#define SGPIO_STATUS_3_STATUS_INPI0_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI0_Pos) /*!< SGPIO STATUS_3: STATUS_INPI0 Mask */ -#define SGPIO_STATUS_3_STATUS_INPI1_Pos 1 /*!< SGPIO STATUS_3: STATUS_INPI1 Position */ -#define SGPIO_STATUS_3_STATUS_INPI1_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI1_Pos) /*!< SGPIO STATUS_3: STATUS_INPI1 Mask */ -#define SGPIO_STATUS_3_STATUS_INPI2_Pos 2 /*!< SGPIO STATUS_3: STATUS_INPI2 Position */ -#define SGPIO_STATUS_3_STATUS_INPI2_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI2_Pos) /*!< SGPIO STATUS_3: STATUS_INPI2 Mask */ -#define SGPIO_STATUS_3_STATUS_INPI3_Pos 3 /*!< SGPIO STATUS_3: STATUS_INPI3 Position */ -#define SGPIO_STATUS_3_STATUS_INPI3_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI3_Pos) /*!< SGPIO STATUS_3: STATUS_INPI3 Mask */ -#define SGPIO_STATUS_3_STATUS_INPI4_Pos 4 /*!< SGPIO STATUS_3: STATUS_INPI4 Position */ -#define SGPIO_STATUS_3_STATUS_INPI4_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI4_Pos) /*!< SGPIO STATUS_3: STATUS_INPI4 Mask */ -#define SGPIO_STATUS_3_STATUS_INPI5_Pos 5 /*!< SGPIO STATUS_3: STATUS_INPI5 Position */ -#define SGPIO_STATUS_3_STATUS_INPI5_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI5_Pos) /*!< SGPIO STATUS_3: STATUS_INPI5 Mask */ -#define SGPIO_STATUS_3_STATUS_INPI6_Pos 6 /*!< SGPIO STATUS_3: STATUS_INPI6 Position */ -#define SGPIO_STATUS_3_STATUS_INPI6_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI6_Pos) /*!< SGPIO STATUS_3: STATUS_INPI6 Mask */ -#define SGPIO_STATUS_3_STATUS_INPI7_Pos 7 /*!< SGPIO STATUS_3: STATUS_INPI7 Position */ -#define SGPIO_STATUS_3_STATUS_INPI7_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI7_Pos) /*!< SGPIO STATUS_3: STATUS_INPI7 Mask */ -#define SGPIO_STATUS_3_STATUS_INPI8_Pos 8 /*!< SGPIO STATUS_3: STATUS_INPI8 Position */ -#define SGPIO_STATUS_3_STATUS_INPI8_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI8_Pos) /*!< SGPIO STATUS_3: STATUS_INPI8 Mask */ -#define SGPIO_STATUS_3_STATUS_INPI9_Pos 9 /*!< SGPIO STATUS_3: STATUS_INPI9 Position */ -#define SGPIO_STATUS_3_STATUS_INPI9_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI9_Pos) /*!< SGPIO STATUS_3: STATUS_INPI9 Mask */ -#define SGPIO_STATUS_3_STATUS_INPI10_Pos 10 /*!< SGPIO STATUS_3: STATUS_INPI10 Position */ -#define SGPIO_STATUS_3_STATUS_INPI10_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI10_Pos) /*!< SGPIO STATUS_3: STATUS_INPI10 Mask */ -#define SGPIO_STATUS_3_STATUS_INPI11_Pos 11 /*!< SGPIO STATUS_3: STATUS_INPI11 Position */ -#define SGPIO_STATUS_3_STATUS_INPI11_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI11_Pos) /*!< SGPIO STATUS_3: STATUS_INPI11 Mask */ -#define SGPIO_STATUS_3_STATUS_INPI12_Pos 12 /*!< SGPIO STATUS_3: STATUS_INPI12 Position */ -#define SGPIO_STATUS_3_STATUS_INPI12_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI12_Pos) /*!< SGPIO STATUS_3: STATUS_INPI12 Mask */ -#define SGPIO_STATUS_3_STATUS_INPI13_Pos 13 /*!< SGPIO STATUS_3: STATUS_INPI13 Position */ -#define SGPIO_STATUS_3_STATUS_INPI13_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI13_Pos) /*!< SGPIO STATUS_3: STATUS_INPI13 Mask */ -#define SGPIO_STATUS_3_STATUS_INPI14_Pos 14 /*!< SGPIO STATUS_3: STATUS_INPI14 Position */ -#define SGPIO_STATUS_3_STATUS_INPI14_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI14_Pos) /*!< SGPIO STATUS_3: STATUS_INPI14 Mask */ -#define SGPIO_STATUS_3_STATUS_INPI15_Pos 15 /*!< SGPIO STATUS_3: STATUS_INPI15 Position */ -#define SGPIO_STATUS_3_STATUS_INPI15_Msk (0x01UL << SGPIO_STATUS_3_STATUS_INPI15_Pos) /*!< SGPIO STATUS_3: STATUS_INPI15 Mask */ - -// ----------------------------------- SGPIO_CTR_STATUS_3 --------------------------------------- -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI0_Pos 0 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI0 Position */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI0_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI0_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI0 Mask */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI1_Pos 1 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI1 Position */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI1_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI1_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI1 Mask */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI2_Pos 2 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI2 Position */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI2_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI2_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI2 Mask */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI3_Pos 3 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI3 Position */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI3_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI3_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI3 Mask */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI4_Pos 4 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI4 Position */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI4_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI4_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI4 Mask */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI5_Pos 5 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI5 Position */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI5_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI5_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI5 Mask */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI6_Pos 6 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI6 Position */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI6_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI6_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI6 Mask */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI7_Pos 7 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI7 Position */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI7_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI7_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI7 Mask */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI8_Pos 8 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI8 Position */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI8_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI8_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI8 Mask */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI9_Pos 9 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI9 Position */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI9_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI9_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI9 Mask */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI10_Pos 10 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI10 Position */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI10_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI10_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI10 Mask */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI11_Pos 11 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI11 Position */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI11_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI11_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI11 Mask */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI12_Pos 12 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI12 Position */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI12_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI12_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI12 Mask */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI13_Pos 13 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI13 Position */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI13_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI13_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI13 Mask */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI14_Pos 14 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI14 Position */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI14_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI14_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI14 Mask */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI15_Pos 15 /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI15 Position */ -#define SGPIO_CTR_STATUS_3_CTR_STATUS_INPI15_Msk (0x01UL << SGPIO_CTR_STATUS_3_CTR_STATUS_INPI15_Pos) /*!< SGPIO CTR_STATUS_3: CTR_STATUS_INPI15 Mask */ - -// ----------------------------------- SGPIO_SET_STATUS_3 --------------------------------------- -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI0_Pos 0 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI0 Position */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI0_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI0_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI0 Mask */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI1_Pos 1 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI1 Position */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI1_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI1_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI1 Mask */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI2_Pos 2 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI2 Position */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI2_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI2_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI2 Mask */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI3_Pos 3 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI3 Position */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI3_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI3_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI3 Mask */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI4_Pos 4 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI4 Position */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI4_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI4_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI4 Mask */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI5_Pos 5 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI5 Position */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI5_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI5_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI5 Mask */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI6_Pos 6 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI6 Position */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI6_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI6_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI6 Mask */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI7_Pos 7 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI7 Position */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI7_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI7_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI7 Mask */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI8_Pos 8 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI8 Position */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI8_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI8_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI8 Mask */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI9_Pos 9 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI9 Position */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI9_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI9_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI9 Mask */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI10_Pos 10 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI10 Position */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI10_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI10_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI10 Mask */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI11_Pos 11 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI11 Position */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI11_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI11_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI11 Mask */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI12_Pos 12 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI12 Position */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI12_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI12_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI12 Mask */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI13_Pos 13 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI13 Position */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI13_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI13_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI13 Mask */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI14_Pos 14 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI14 Position */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI14_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI14_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI14 Mask */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI15_Pos 15 /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI15 Position */ -#define SGPIO_SET_STATUS_3_CTR_STATUS_INPI15_Msk (0x01UL << SGPIO_SET_STATUS_3_CTR_STATUS_INPI15_Pos) /*!< SGPIO SET_STATUS_3: CTR_STATUS_INPI15 Mask */ - -#endif - -// ------------------------------------------------------------------------------------------------ -// ----- Peripheral memory map ----- -// ------------------------------------------------------------------------------------------------ - -#define LPC_SCT_BASE 0x40000000 -#define LPC_GPDMA_BASE 0x40002000 -#define LPC_SDMMC_BASE 0x40004000 -#define LPC_EMC_BASE 0x40005000 -#define LPC_USB0_BASE 0x40006000 -#define LPC_USB1_BASE 0x40007000 -#define LPC_LCD_BASE 0x40008000 -#define LPC_ETHERNET_BASE 0x40010000 -#define LPC_ATIMER_BASE 0x40040000 -#define LPC_REGFILE_BASE 0x40041000 -#define LPC_PMC_BASE 0x40042000 -#define LPC_CREG_BASE 0x40043000 -#define LPC_EVENTROUTER_BASE 0x40044000 -#define LPC_RTC_BASE 0x40046000 -#define LPC_CGU_BASE 0x40050000 -#define LPC_CCU1_BASE 0x40051000 -#define LPC_CCU2_BASE 0x40052000 -#define LPC_RGU_BASE 0x40053000 -#define LPC_WWDT_BASE 0x40080000 -#define LPC_USART0_BASE 0x40081000 -#define LPC_USART2_BASE 0x400C1000 -#define LPC_USART3_BASE 0x400C2000 -#define LPC_UART1_BASE 0x40082000 -#define LPC_SSP0_BASE 0x40083000 -#define LPC_SSP1_BASE 0x400C5000 -#define LPC_TIMER0_BASE 0x40084000 -#define LPC_TIMER1_BASE 0x40085000 -#define LPC_TIMER2_BASE 0x400C3000 -#define LPC_TIMER3_BASE 0x400C4000 -#define LPC_SCU_BASE 0x40086000 -#define LPC_GPIO_PIN_INT_BASE 0x40087000 -#define LPC_GPIO_GROUP_INT0_BASE 0x40088000 -#define LPC_GPIO_GROUP_INT1_BASE 0x40089000 -#define LPC_MCPWM_BASE 0x400A0000 -#define LPC_I2C0_BASE 0x400A1000 -#define LPC_I2C1_BASE 0x400E0000 -#define LPC_I2S0_BASE 0x400A2000 -#define LPC_I2S1_BASE 0x400A3000 -#define LPC_C_CAN1_BASE 0x400A4000 -#define LPC_RITIMER_BASE 0x400C0000 -#define LPC_QEI_BASE 0x400C6000 -#define LPC_GIMA_BASE 0x400C7000 -#define LPC_DAC_BASE 0x400E1000 -#define LPC_C_CAN0_BASE 0x400E2000 -#define LPC_ADC0_BASE 0x400E3000 -#define LPC_ADC1_BASE 0x400E4000 -#define LPC_VADC_BASE 0x400F0000 -#define LPC_GPIO_PORT_BASE 0x400F4000 -#define LPC_SPI_BASE 0x40100000 -#define LPC_SGPIO_BASE 0x40101000 - - -// ------------------------------------------------------------------------------------------------ -// ----- Peripheral declaration ----- -// ------------------------------------------------------------------------------------------------ - -#define LPC_SCT ((LPC_SCT_Type *) LPC_SCT_BASE) -#define LPC_GPDMA ((LPC_GPDMA_Type *) LPC_GPDMA_BASE) -#define LPC_SDMMC ((LPC_SDMMC_Type *) LPC_SDMMC_BASE) -#define LPC_EMC ((LPC_EMC_Type *) LPC_EMC_BASE) -#define LPC_USB0 ((LPC_USB0_Type *) LPC_USB0_BASE) -#define LPC_USB1 ((LPC_USB1_Type *) LPC_USB1_BASE) -#define LPC_LCD ((LPC_LCD_Type *) LPC_LCD_BASE) -#define LPC_ETHERNET ((LPC_ETHERNET_Type *) LPC_ETHERNET_BASE) -#define LPC_ATIMER ((LPC_ATIMER_Type *) LPC_ATIMER_BASE) -#define LPC_REGFILE ((LPC_REGFILE_Type *) LPC_REGFILE_BASE) -#define LPC_PMC ((LPC_PMC_Type *) LPC_PMC_BASE) -#define LPC_CREG ((LPC_CREG_Type *) LPC_CREG_BASE) -#define LPC_EVENTROUTER ((LPC_EVENTROUTER_Type *) LPC_EVENTROUTER_BASE) -#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE) -#define LPC_CGU ((LPC_CGU_Type *) LPC_CGU_BASE) -#define LPC_CCU1 ((LPC_CCU1_Type *) LPC_CCU1_BASE) -#define LPC_CCU2 ((LPC_CCU2_Type *) LPC_CCU2_BASE) -#define LPC_RGU ((LPC_RGU_Type *) LPC_RGU_BASE) -#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE) -#define LPC_USART0 ((LPC_USARTn_Type *) LPC_USART0_BASE) -#define LPC_USART2 ((LPC_USARTn_Type *) LPC_USART2_BASE) -#define LPC_USART3 ((LPC_USARTn_Type *) LPC_USART3_BASE) -#define LPC_UART1 ((LPC_UART1_Type *) LPC_UART1_BASE) -#define LPC_SSP0 ((LPC_SSPn_Type *) LPC_SSP0_BASE) -#define LPC_SSP1 ((LPC_SSPn_Type *) LPC_SSP1_BASE) -#define LPC_TIMER0 ((LPC_TIMERn_Type *) LPC_TIMER0_BASE) -#define LPC_TIMER1 ((LPC_TIMERn_Type *) LPC_TIMER1_BASE) -#define LPC_TIMER2 ((LPC_TIMERn_Type *) LPC_TIMER2_BASE) -#define LPC_TIMER3 ((LPC_TIMERn_Type *) LPC_TIMER3_BASE) -#define LPC_SCU ((LPC_SCU_Type *) LPC_SCU_BASE) -#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE) -#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT0_BASE) -#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT1_BASE) -#define LPC_MCPWM ((LPC_MCPWM_Type *) LPC_MCPWM_BASE) -#define LPC_I2C0 ((LPC_I2Cn_Type *) LPC_I2C0_BASE) -#define LPC_I2C1 ((LPC_I2Cn_Type *) LPC_I2C1_BASE) -#define LPC_I2S0 ((LPC_I2Sn_Type *) LPC_I2S0_BASE) -#define LPC_I2S1 ((LPC_I2Sn_Type *) LPC_I2S1_BASE) -#define LPC_C_CAN1 ((LPC_C_CANn_Type *) LPC_C_CAN1_BASE) -#define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE) -#define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE) -#define LPC_GIMA ((LPC_GIMA_Type *) LPC_GIMA_BASE) -#define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE) -#define LPC_C_CAN0 ((LPC_C_CANn_Type *) LPC_C_CAN0_BASE) -#define LPC_ADC0 ((LPC_ADCn_Type *) LPC_ADC0_BASE) -#define LPC_ADC1 ((LPC_ADCn_Type *) LPC_ADC1_BASE) -#define LPC_VADC ((LPC_VADC_Type *) LPC_VADC_BASE) -#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE) -#define LPC_SPI ((LPC_SPI_Type *) LPC_SPI_BASE) -#define LPC_SGPIO ((LPC_SGPIO_Type *) LPC_SGPIO_BASE) - - -/** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group LPC43xx */ -/** @} */ /* End of group (null) */ +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group LPC43xx */ +/** @} */ /* End of group (null) */ #ifdef __cplusplus } -#endif - +#endif -#endif // __LPC43xx_H__ +#endif /* LPC43xx_H */ diff --git a/source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s b/source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s index 14a928ade..715a7c7dd 100644 --- a/source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s +++ b/source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s @@ -1,26 +1,26 @@ -;/*********************************************************************** -; * $Id: startup_LPC18xx.s 6473 2011-02-16 17:40:54Z nxp27266 $ +;/**************************************************************************//** +; * @file LPC43xx.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for +; * NXP LPC43xxDevice Series +; * @version V1.00 +; * @date 03. September 2013 ; * -; * Project: LPC18xx CMSIS Package +; * @note +; * Copyright (C) 2009-2013 ARM Limited. All rights reserved. ; * -; * Description: Cortex-M3 Core Device Startup File for the NXP LPC18xx -; * Device Series. +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. ; * -; * Copyright(C) 2011, NXP Semiconductor -; * All rights reserved. +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. ; * -; *********************************************************************** -; * Software that is described herein is for illustrative purposes only -; * which provides customers with programming information regarding the -; * products. This software is supplied "AS IS" without any warranties. -; * NXP Semiconductors assumes no responsibility or liability for the -; * use of the software, conveys no license or title under any patent, -; * copyright, or mask work right to the product. NXP Semiconductors -; * reserves the right to make changes in the software without -; * notification. NXP Semiconductors also make no representation or -; * warranty that such application will be suitable for the specified -; * use without further testing or modification. -; **********************************************************************/ +; ******************************************************************************/ ; Stack Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> @@ -36,7 +36,7 @@ __initial_sp ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Heap_Size EQU 0x00000100 +Heap_Size EQU 0x00000000 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base @@ -51,86 +51,94 @@ __heap_limit AREA RESET, DATA, READONLY EXPORT __Vectors IMPORT g_board_info -Sign_Value EQU 0x5A5A5A5A - -__Vectors DCD __initial_sp ; 0 Top of Stack - DCD Reset_Handler ; 1 Reset Handler - DCD NMI_Handler ; 2 NMI Handler - DCD HardFault_Handler ; 3 Hard Fault Handler - DCD MemManage_Handler ; 4 MPU Fault Handler - DCD BusFault_Handler ; 5 Bus Fault Handler - DCD UsageFault_Handler ; 6 Usage Fault Handler - DCD Sign_Value ; 7 Reserved - DCD DAPLINK_BUILD_KEY ; 8 DAPLINK: Build type (BL/IF) - DCD DAPLINK_HIC_ID ; 9 DAPLINK: Compatibility - DCD DAPLINK_VERSION ; 10 DAPLINK: Version - DCD SVC_Handler ; 11 SVCall Handler - DCD DebugMon_Handler ; 12 Debug Monitor Handler - DCD g_board_info ; 13 DAPLINK: Pointer to board/family/target info - DCD PendSV_Handler ; 14 PendSV Handler - DCD SysTick_Handler ; 15 SysTick Handler - - ; External Interrupts - DCD DAC_IRQHandler ; 16 D/A Converter - DCD M0CORE_IRQHandler ; 17 M0 Core - DCD DMA_IRQHandler ; 18 General Purpose DMA - DCD EZH_IRQHandler ; 19 EZH/EDM - DCD FLASH_EEPROM_IRQHandler ; 20 Reserved for Typhoon - DCD ETH_IRQHandler ; 21 Ethernet - DCD SDIO_IRQHandler ; 22 SD/MMC - DCD LCD_IRQHandler ; 23 LCD - DCD USB0_IRQHandler ; 24 USB0 - DCD USB1_IRQHandler ; 25 USB1 - DCD SCT_IRQHandler ; 26 State Configurable Timer - DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer - DCD TIMER0_IRQHandler ; 28 Timer0 - DCD TIMER1_IRQHandler ; 29 Timer1 - DCD TIMER2_IRQHandler ; 30 Timer2 - DCD TIMER3_IRQHandler ; 31 Timer3 - DCD MCPWM_IRQHandler ; 32 Motor Control PWM - DCD ADC0_IRQHandler ; 33 A/D Converter 0 - DCD I2C0_IRQHandler ; 34 I2C0 - DCD I2C1_IRQHandler ; 35 I2C1 - DCD SPI_IRQHandler ; 36 SPI - DCD ADC1_IRQHandler ; 37 A/D Converter 1 - DCD SSP0_IRQHandler ; 38 SSP0 - DCD SSP1_IRQHandler ; 39 SSP1 - DCD UART0_IRQHandler ; 40 UART0 - DCD UART1_IRQHandler ; 41 UART1 - DCD UART2_IRQHandler ; 42 UART2 - DCD UART3_IRQHandler ; 43 UART3 - DCD I2S0_IRQHandler ; 44 I2S0 - DCD I2S1_IRQHandler ; 45 I2S1 - DCD SPIFI_IRQHandler ; 46 SPI Flash Interface - DCD SGPIO_IRQHandler ; 47 SGPIO - DCD GPIO0_IRQHandler ; 48 GPIO0 - DCD GPIO1_IRQHandler ; 49 GPIO1 - DCD GPIO2_IRQHandler ; 50 GPIO2 - DCD GPIO3_IRQHandler ; 51 GPIO3 - DCD GPIO4_IRQHandler ; 52 GPIO4 - DCD GPIO5_IRQHandler ; 53 GPIO5 - DCD GPIO6_IRQHandler ; 54 GPIO6 - DCD GPIO7_IRQHandler ; 55 GPIO7 - DCD GINT0_IRQHandler ; 56 GINT0 - DCD GINT1_IRQHandler ; 57 GINT1 - DCD EVRT_IRQHandler ; 58 Event Router - DCD CAN1_IRQHandler ; 59 C_CAN1 - DCD 0 ; 60 Reserved - DCD VADC_IRQHandler ; 61 VADC - DCD ATIMER_IRQHandler ; 62 ATIMER - DCD RTC_IRQHandler ; 63 RTC - DCD 0 ; 64 Reserved - DCD WDT_IRQHandler ; 65 WDT - DCD M0s_IRQHandler ; 66 M0s - DCD CAN0_IRQHandler ; 67 C_CAN0 - DCD QEI_IRQHandler ; 68 QEI - +Sign_Value EQU 0x5A5A5A5A + +__Vectors DCD __initial_sp ; 0 Top of Stack + DCD Reset_Handler ; 1 Reset Handler + DCD NMI_Handler ; 2 NMI Handler + DCD HardFault_Handler ; 3 Hard Fault Handler + DCD MemManage_Handler ; 4 MPU Fault Handler + DCD BusFault_Handler ; 5 Bus Fault Handler + DCD UsageFault_Handler ; 6 Usage Fault Handler + DCD Sign_Value ; 7 Reserved + DCD DAPLINK_BUILD_KEY ; 8 DAPLINK: Build type (BL/IF) + DCD DAPLINK_HIC_ID ; 9 DAPLINK: Compatibility + DCD DAPLINK_VERSION ; 10 DAPLINK: Version + DCD SVC_Handler ; 11 SVCall Handler + DCD DebugMon_Handler ; 12 Debug Monitor Handler + DCD g_board_info ; 13 DAPLINK: Pointer to board/family/target info + DCD PendSV_Handler ; 14 PendSV Handler + DCD SysTick_Handler ; 15 SysTick Handler + + ; External LPC43xx/M4 Interrupts + DCD DAC_IRQHandler ; 0 DAC interrupt + DCD M0APP_IRQHandler ; 1 Cortex-M0APP; Latched TXEV; for M4-M0APP communication + DCD DMA_IRQHandler ; 2 DMA interrupt + DCD 0 ; 3 Reserved + DCD FLASHEEPROM_IRQHandler ; 4 flash bank A, flash bank B, EEPROM ORed interrupt + DCD ETHERNET_IRQHandler ; 5 Ethernet interrupt + DCD SDIO_IRQHandler ; 6 SD/MMC interrupt + DCD LCD_IRQHandler ; 7 LCD interrupt + DCD USB0_IRQHandler ; 8 OTG interrupt + DCD USB1_IRQHandler ; 9 USB1 interrupt + DCD SCT_IRQHandler ; 10 SCT combined interrupt + DCD RITIMER_IRQHandler ; 11 RI Timer interrupt + DCD TIMER0_IRQHandler ; 12 Timer 0 interrupt + DCD TIMER1_IRQHandler ; 13 Timer 1 interrupt + DCD TIMER2_IRQHandler ; 14 Timer 2 interrupt + DCD TIMER3_IRQHandler ; 15 Timer 3 interrupt + DCD MCPWM_IRQHandler ; 16 Motor control PWM interrupt + DCD ADC0_IRQHandler ; 17 ADC0 interrupt + DCD I2C0_IRQHandler ; 18 I2C0 interrupt + DCD I2C1_IRQHandler ; 19 I2C1 interrupt + DCD SPI_IRQHandler ; 20 SPI interrupt + DCD ADC1_IRQHandler ; 21 ADC1 interrupt + DCD SSP0_IRQHandler ; 22 SSP0 interrupt + DCD SSP1_IRQHandler ; 23 SSP1 interrupt + DCD USART0_IRQHandler ; 24 USART0 interrupt + DCD UART1_IRQHandler ; 25 Combined UART1, Modem interrupt + DCD USART2_IRQHandler ; 26 USART2 interrupt + DCD USART3_IRQHandler ; 27 Combined USART3, IrDA interrupt + DCD I2S0_IRQHandler ; 28 I2S0 interrupt + DCD I2S1_IRQHandler ; 29 I2S1 interrupt + DCD SPIFI_IRQHandler ; 30 SPISI interrupt + DCD SGPIO_IRQHandler ; 31 SGPIO interrupt + DCD PIN_INT0_IRQHandler ; 32 GPIO pin interrupt 0 + DCD PIN_INT1_IRQHandler ; 33 GPIO pin interrupt 1 + DCD PIN_INT2_IRQHandler ; 34 GPIO pin interrupt 2 + DCD PIN_INT3_IRQHandler ; 35 GPIO pin interrupt 3 + DCD PIN_INT4_IRQHandler ; 36 GPIO pin interrupt 4 + DCD PIN_INT5_IRQHandler ; 37 GPIO pin interrupt 5 + DCD PIN_INT6_IRQHandler ; 38 GPIO pin interrupt 6 + DCD PIN_INT7_IRQHandler ; 39 GPIO pin interrupt 7 + DCD GINT0_IRQHandler ; 40 GPIO global interrupt 0 + DCD GINT1_IRQHandler ; 41 GPIO global interrupt 1 + DCD EVENTROUTER_IRQHandler ; 42 Event router interrupt + DCD C_CAN1_IRQHandler ; 43 C_CAN1 interrupt + DCD 0 ; 44 Reserved + DCD ADCHS_IRQHandler ; 45 ADCHS combined interrupt + DCD ATIMER_IRQHandler ; 46 Alarm timer interrupt + DCD RTC_IRQHandler ; 47 RTC interrupt + DCD 0 ; 48 Reserved + DCD WWDT_IRQHandler ; 49 WWDT interrupt + DCD M0SUB_IRQHandler ; 50 TXEV instruction from the M0 subsystem core interrupt + DCD C_CAN0_IRQHandler ; 51 C_CAN0 interrupt + DCD QEI_IRQHandler ; 52 QEI interrupt + + +;CRP address at offset 0x2FC relative to the BOOT Bank address IF :LNOT::DEF:NO_CRP #if defined(DAPLINK_BL) - AREA |.ARM.__at_0x1A0002FC|, CODE, READONLY + SPACE (0x2FC - (. - __Vectors)) +; EXPORT CRP_Key CRP_Key DCD 0xFFFFFFFF #endif +; 0xFFFFFFFF => CRP Disabled +; 0x12345678 => CRP Level 1 +; 0x87654321 => CRP Level 2 +; 0x43218765 => CRP Level 3 (ARE YOU SURE?) +; 0x4E697370 => NO ISP (ARE YOU SURE?) ENDIF AREA |.text|, CODE, READONLY @@ -138,11 +146,11 @@ CRP_Key DCD 0xFFFFFFFF ; Reset Handler Reset_Handler PROC - EXPORT Reset_Handler [WEAK] + EXPORT Reset_Handler [WEAK] IMPORT __main IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 + LDR R0, =SystemInit + BLX R0 LDR R0, =__main BX R0 ENDP @@ -150,116 +158,110 @@ Reset_Handler PROC ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC - EXPORT NMI_Handler [WEAK] + EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC - EXPORT HardFault_Handler [WEAK] + EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC - EXPORT MemManage_Handler [WEAK] + EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC - EXPORT BusFault_Handler [WEAK] + EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC - EXPORT UsageFault_Handler [WEAK] + EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC - EXPORT SVC_Handler [WEAK] + EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC - EXPORT DebugMon_Handler [WEAK] + EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] + EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] + EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC - - EXPORT DAC_IRQHandler [WEAK] - EXPORT M0CORE_IRQHandler [WEAK] - EXPORT DMA_IRQHandler [WEAK] - EXPORT EZH_IRQHandler [WEAK] - EXPORT FLASH_EEPROM_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT LCD_IRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT USB1_IRQHandler [WEAK] - EXPORT SCT_IRQHandler [WEAK] - EXPORT RIT_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT MCPWM_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT I2S0_IRQHandler [WEAK] - EXPORT I2S1_IRQHandler [WEAK] - EXPORT SPIFI_IRQHandler [WEAK] - EXPORT SGPIO_IRQHandler [WEAK] - EXPORT GPIO0_IRQHandler [WEAK] - EXPORT GPIO1_IRQHandler [WEAK] - EXPORT GPIO2_IRQHandler [WEAK] - EXPORT GPIO3_IRQHandler [WEAK] - EXPORT GPIO4_IRQHandler [WEAK] - EXPORT GPIO5_IRQHandler [WEAK] - EXPORT GPIO6_IRQHandler [WEAK] - EXPORT GPIO7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT EVRT_IRQHandler [WEAK] - EXPORT CAN1_IRQHandler [WEAK] -; EXPORT RESERVED3 [WEAK] - EXPORT VADC_IRQHandler [WEAK] - EXPORT ATIMER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] -; EXPORT RESERVED4 [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT M0s_IRQHandler [WEAK] - EXPORT CAN0_IRQHandler [WEAK] - EXPORT QEI_IRQHandler [WEAK] - + EXPORT DAC_IRQHandler [WEAK] + EXPORT M0APP_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASHEEPROM_IRQHandler [WEAK] + EXPORT ETHERNET_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT USB1_IRQHandler [WEAK] + EXPORT SCT_IRQHandler [WEAK] + EXPORT RITIMER_IRQHandler [WEAK] + EXPORT TIMER0_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT MCPWM_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT SSP0_IRQHandler [WEAK] + EXPORT SSP1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT I2S0_IRQHandler [WEAK] + EXPORT I2S1_IRQHandler [WEAK] + EXPORT SPIFI_IRQHandler [WEAK] + EXPORT SGPIO_IRQHandler [WEAK] + EXPORT PIN_INT0_IRQHandler [WEAK] + EXPORT PIN_INT1_IRQHandler [WEAK] + EXPORT PIN_INT2_IRQHandler [WEAK] + EXPORT PIN_INT3_IRQHandler [WEAK] + EXPORT PIN_INT4_IRQHandler [WEAK] + EXPORT PIN_INT5_IRQHandler [WEAK] + EXPORT PIN_INT6_IRQHandler [WEAK] + EXPORT PIN_INT7_IRQHandler [WEAK] + EXPORT GINT0_IRQHandler [WEAK] + EXPORT GINT1_IRQHandler [WEAK] + EXPORT EVENTROUTER_IRQHandler [WEAK] + EXPORT C_CAN1_IRQHandler [WEAK] + EXPORT ADCHS_IRQHandler [WEAK] + EXPORT ATIMER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT WWDT_IRQHandler [WEAK] + EXPORT M0SUB_IRQHandler [WEAK] + EXPORT C_CAN0_IRQHandler [WEAK] + EXPORT QEI_IRQHandler [WEAK] DAC_IRQHandler -M0CORE_IRQHandler +M0APP_IRQHandler DMA_IRQHandler -EZH_IRQHandler -FLASH_EEPROM_IRQHandler -ETH_IRQHandler +FLASHEEPROM_IRQHandler +ETHERNET_IRQHandler SDIO_IRQHandler LCD_IRQHandler USB0_IRQHandler USB1_IRQHandler SCT_IRQHandler -RIT_IRQHandler +RITIMER_IRQHandler TIMER0_IRQHandler TIMER1_IRQHandler TIMER2_IRQHandler @@ -272,37 +274,35 @@ SPI_IRQHandler ADC1_IRQHandler SSP0_IRQHandler SSP1_IRQHandler -UART0_IRQHandler +USART0_IRQHandler UART1_IRQHandler -UART2_IRQHandler -UART3_IRQHandler +USART2_IRQHandler +USART3_IRQHandler I2S0_IRQHandler I2S1_IRQHandler SPIFI_IRQHandler SGPIO_IRQHandler -GPIO0_IRQHandler -GPIO1_IRQHandler -GPIO2_IRQHandler -GPIO3_IRQHandler -GPIO4_IRQHandler -GPIO5_IRQHandler -GPIO6_IRQHandler -GPIO7_IRQHandler +PIN_INT0_IRQHandler +PIN_INT1_IRQHandler +PIN_INT2_IRQHandler +PIN_INT3_IRQHandler +PIN_INT4_IRQHandler +PIN_INT5_IRQHandler +PIN_INT6_IRQHandler +PIN_INT7_IRQHandler GINT0_IRQHandler GINT1_IRQHandler -EVRT_IRQHandler -CAN1_IRQHandler -;RESERVED3 -VADC_IRQHandler +EVENTROUTER_IRQHandler +C_CAN1_IRQHandler +ADCHS_IRQHandler ATIMER_IRQHandler RTC_IRQHandler -;RESERVED4 -WDT_IRQHandler -M0s_IRQHandler -CAN0_IRQHandler +WWDT_IRQHandler +M0SUB_IRQHandler +C_CAN0_IRQHandler QEI_IRQHandler - B . + B . ENDP ALIGN @@ -331,4 +331,5 @@ __user_initial_stackheap ENDIF + END diff --git a/source/hic_hal/nxp/lpc4322/fpu_enable.c b/source/hic_hal/nxp/lpc4322/fpu_enable.c deleted file mode 100644 index c6c082acb..000000000 --- a/source/hic_hal/nxp/lpc4322/fpu_enable.c +++ /dev/null @@ -1,65 +0,0 @@ -/*********************************************************************** - * $Id: fpu_enable.c - * - * Project: LPC43xx - * - * Description: fpu initialization routine - * - * Copyright(C) 2011, NXP Semiconductor - * All rights reserved. - * - *********************************************************************** - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * products. This software is supplied "AS IS" without any warranties. - * NXP Semiconductors assumes no responsibility or liability for the - * use of the software, conveys no license or title under any patent, - * copyright, or mask work right to the product. NXP Semiconductors - * reserves the right to make changes in the software without - * notification. NXP Semiconductors also make no representation or - * warranty that such application will be suitable for the specified - * use without further testing or modification. - **********************************************************************/ - -#define LPC_CPACR 0xE000ED88 - -#define SCB_MVFR0 0xE000EF40 -#define SCB_MVFR0_RESET 0x10110021 - -#define SCB_MVFR1 0xE000EF44 -#define SCB_MVFR1_RESET 0x11000011 - -#include "stdint.h" - -void fpuEnable(void) -{ - /* from arm trm manual, howto enable the FPU : - ; CPACR is located at address 0xE000ED88 - LDR.W R0, =0xE000ED88 - ; Read CPACR - LDR R1, [R0] - ; Set bits 20-23 to enable CP10 and CP11 coprocessors - ORR R1, R1, #(0xF << 20) - ; Write back the modified value to the CPACR - STR R1, [R0] - */ - volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR; - volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0; - volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1; - volatile uint32_t Cpacr; - volatile uint32_t Mvfr0; - volatile uint32_t Mvfr1; - char vfpPresent = 0; - Mvfr0 = *regMvfr0; - Mvfr1 = *regMvfr1; - vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1)); - - /* enable the FPU if present on target */ - if (vfpPresent) { - Cpacr = *regCpacr; - Cpacr |= (0xF << 20); - *regCpacr = Cpacr; // enable CP10 and CP11 for full access - } -} - - diff --git a/source/hic_hal/nxp/lpc4322/fpu_enable.h b/source/hic_hal/nxp/lpc4322/fpu_enable.h deleted file mode 100644 index 72ad69c94..000000000 --- a/source/hic_hal/nxp/lpc4322/fpu_enable.h +++ /dev/null @@ -1,33 +0,0 @@ -/*********************************************************************** - * $Id: fpu_enable.h - * - * Project: LPC43xx - * - * Description: fpu initialization routine header - * - * Copyright(C) 2011, NXP Semiconductor - * All rights reserved. - * - *********************************************************************** - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * products. This software is supplied "AS IS" without any warranties. - * NXP Semiconductors assumes no responsibility or liability for the - * use of the software, conveys no license or title under any patent, - * copyright, or mask work right to the product. NXP Semiconductors - * reserves the right to make changes in the software without - * notification. NXP Semiconductors also make no representation or - * warranty that such application will be suitable for the specified - * use without further testing or modification. - **********************************************************************/ - -#ifndef __FPU_ENABLE_H -#define __FPU_ENABLE_H - -#if defined(__ARMCC_VERSION) -void fpuEnable(void) __attribute__((section("BOOTSTRAP_CODE"))); -#else -extern void fpuEnable(void); -#endif - -#endif /* __FPU_ENABLE_H */ diff --git a/source/hic_hal/nxp/lpc4322/system_LPC43xx.c b/source/hic_hal/nxp/lpc4322/system_LPC43xx.c index 405cf5aea..1e22e6979 100644 --- a/source/hic_hal/nxp/lpc4322/system_LPC43xx.c +++ b/source/hic_hal/nxp/lpc4322/system_LPC43xx.c @@ -1,79 +1,713 @@ -/********************************************************************** -* $Id$ system_lpc43xx.c 2012-05-21 -*//** -* @file system_lpc43xx.c -* @brief Cortex-M3 Device System Source File for NXP lpc43xx Series. -* @version 1.0 -* @date 21. May. 2011 -* @author NXP MCU SW Application Team -* -* Copyright(C) 2011, NXP Semiconductor -* All rights reserved. -* -*********************************************************************** -* Software that is described herein is for illustrative purposes only -* which provides customers with programming information regarding the -* products. This software is supplied "AS IS" without any warranties. -* NXP Semiconductors assumes no responsibility or liability for the -* use of the software, conveys no license or title under any patent, -* copyright, or mask work right to the product. NXP Semiconductors -* reserves the right to make changes in the software without -* notification. NXP Semiconductors also make no representation or -* warranty that such application will be suitable for the specified -* use without further testing or modification. -* Permission to use, copy, modify, and distribute this software and its -* documentation is hereby granted, under NXP Semiconductors' -* relevant copyright in the software, without fee, provided that it -* is used in conjunction with NXP Semiconductors microcontrollers. This -* copyright, permission, and disclaimer notice must appear in all copies of -* this code. -**********************************************************************/ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013 - 2020 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * $Date: 20. Januar 2020 + * $Revision: V1.0.4 + * + * Project: NXP LPC43xx System initialization + * -------------------------------------------------------------------------- */ #include "LPC43xx.h" -#include "fpu_enable.h" /*---------------------------------------------------------------------------- - Define clocks + This file configures the clocks as follows: + ----------------------------------------------------------------------------- + Clock Unit | Output clock | Source clock | Note + ----------------------------------------------------------------------------- + PLL0USB | 480 MHz | XTAL | External crystal @ 12 MHz + ----------------------------------------------------------------------------- + PLL1 | 180 MHz | XTAL | External crystal @ 12 MHz + ----------------------------------------------------------------------------- + CPU | 180 MHz | PLL1 | CPU Clock == BASE_M4_CLK + ----------------------------------------------------------------------------- + IDIV A | 60 MHz | PLL1 | To the USB1 peripheral + ----------------------------------------------------------------------------- + IDIV B | 25 MHz | ENET_TX_CLK | ENET_TX_CLK @ 50MHz + ----------------------------------------------------------------------------- + IDIV C | 12 MHz | IRC | Internal oscillator @ 12 MHz + ----------------------------------------------------------------------------- + IDIV D | 12 MHz | IRC | Internal oscillator @ 12 MHz + ----------------------------------------------------------------------------- + IDIV E | 5.3 MHz | PLL1 | To the LCD controller + -----------------------------------------------------------------------------*/ + + +/*---------------------------------------------------------------------------- + Clock source selection definitions (do not change) + *----------------------------------------------------------------------------*/ +#define CLK_SRC_32KHZ 0x00 +#define CLK_SRC_IRC 0x01 +#define CLK_SRC_ENET_RX 0x02 +#define CLK_SRC_ENET_TX 0x03 +#define CLK_SRC_GP_CLKIN 0x04 +#define CLK_SRC_XTAL 0x06 +#define CLK_SRC_PLL0U 0x07 +#define CLK_SRC_PLL0A 0x08 +#define CLK_SRC_PLL1 0x09 +#define CLK_SRC_IDIVA 0x0C +#define CLK_SRC_IDIVB 0x0D +#define CLK_SRC_IDIVC 0x0E +#define CLK_SRC_IDIVD 0x0F +#define CLK_SRC_IDIVE 0x10 + + +/*---------------------------------------------------------------------------- + Define external input frequency values + *----------------------------------------------------------------------------*/ +#define CLK_32KHZ 32768UL /* 32 kHz oscillator frequency */ +#define CLK_IRC 12000000UL /* Internal oscillator frequency */ +#define CLK_ENET_RX 50000000UL /* Ethernet Rx frequency */ +#define CLK_ENET_TX 50000000UL /* Ethernet Tx frequency */ +#define CLK_GP_CLKIN 12000000UL /* General purpose clock input freq. */ +#define CLK_XTAL 12000000UL /* Crystal oscilator frequency */ + + +/*---------------------------------------------------------------------------- + Define clock sources + *----------------------------------------------------------------------------*/ +#define PLL1_CLK_SEL CLK_SRC_XTAL /* PLL1 input clock: XTAL */ +#define PLL0USB_CLK_SEL CLK_SRC_XTAL /* PLL0USB input clock: XTAL */ +#define IDIVA_CLK_SEL CLK_SRC_PLL1 /* IDIVA input clock: PLL1 */ +#define IDIVB_CLK_SEL CLK_SRC_ENET_TX /* IDIVB input clock: ENET TX */ +#define IDIVC_CLK_SEL CLK_SRC_IRC /* IDIVC input clock: IRC */ +#define IDIVD_CLK_SEL CLK_SRC_IRC /* IDIVD input clock: IRC */ +#define IDIVE_CLK_SEL CLK_SRC_PLL1 /* IDIVD input clock: PLL1 */ + + +/*---------------------------------------------------------------------------- + Configure integer divider values + *----------------------------------------------------------------------------*/ +#define IDIVA_IDIV 2 /* Divide input clock by 3 */ +#define IDIVB_IDIV 1 /* Divide input clock by 2 */ +#define IDIVC_IDIV 0 /* Divide input clock by 1 */ +#define IDIVD_IDIV 0 /* Divide input clock by 1 */ +#define IDIVE_IDIV 33 /* Divide input clock by 34 */ + + +/*---------------------------------------------------------------------------- + Define CPU clock input *----------------------------------------------------------------------------*/ -#define __IRC (12000000UL) /* IRC Oscillator frequency */ +#define CPU_CLK_SEL CLK_SRC_PLL1 /* Default CPU clock source is PLL1 */ + /*---------------------------------------------------------------------------- - Clock Variable definitions + Configure external memory controller options *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = 96000000; /* System Clock Frequency (Core Clock)*/ +#define USE_EXT_STAT_MEM_CS0 1 /* Use ext. static memory with CS0 */ +#define USE_EXT_DYN_MEM_CS0 1 /* Use ext. dynamic memory with CS0 */ -extern uint32_t __Vectors; -/** - * Initialize the system +/*---------------------------------------------------------------------------- + * Configure PLL1 + *---------------------------------------------------------------------------- + * Integer mode: + * - PLL1_DIRECT = 0 (Post divider enabled) + * - PLL1_FBSEL = 1 (Feedback divider runs from PLL output) + * - Output frequency: + * FCLKOUT = (FCLKIN / N) * M + * FCCO = FCLKOUT * 2 * P * - * @param none - * @return none + * Non-integer: + * - PLL1_DIRECT = 0 (Post divider enabled) + * - PLL1_FBSEL = 0 (Feedback divider runs from CCO clock) + * - Output frequency: + * FCLKOUT = (FCLKIN / N) * M / (2 * P) + * FCCO = FCLKOUT * 2 * P * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit(void) -{ - fpuEnable(); - - // In case we are running from internal flash, we configure the flash - // accelerator. -#define FLASH_ACCELERATOR_SPEED 6 - { - uint32_t *MAM, t; - // Set up flash controller for both banks - // Bank A - MAM = (uint32_t *)(LPC_CREG_BASE + 0x120); - t = *MAM; - t &= ~(0xF << 12); - *MAM = t | (FLASH_ACCELERATOR_SPEED << 12); - // Bank B - MAM = (uint32_t *)(LPC_CREG_BASE + 0x124); - t = *MAM; - t &= ~(0xF << 12); - *MAM = t | (FLASH_ACCELERATOR_SPEED << 12); + * Direct mode: + * - PLL1_DIRECT = 1 (Post divider disabled) + * - PLL1_FBSEL = dont care (Feedback divider runs from CCO clock) + * - Output frequency: + * FCLKOUT = (FCLKIN / N) * M + * FCCO = FCLKOUT + * + *---------------------------------------------------------------------------- + * PLL1 requirements: + * | Frequency | Minimum | Maximum | Note | + * | FCLKIN | 1MHz | 25MHz | Clock source is external crystal | + * | FCLKIN | 1MHz | 50MHz | | + * | FCCO | 156MHz | 320MHz | | + * | FCLKOUT | 9.75MHz | 320MHz | | + *---------------------------------------------------------------------------- + * Configuration examples: + * | Fclkout | Fcco | N | M | P | DIRECT | FBSEL | BYPASS | + * | 36MHz | 288MHz | 1 | 24 | 4 | 0 | 0 | 0 | + * | 72MHz | 288MHz | 1 | 24 | 2 | 0 | 0 | 0 | + * | 100MHz | 200MHz | 3 | 50 | 1 | 0 | 0 | 0 | + * | 120MHz | 240MHz | 1 | 20 | 1 | 0 | 0 | 0 | + * | 160MHz | 160MHz | 3 | 40 | x | 1 | 0 | 0 | + * | 180MHz | 180MHz | 1 | 15 | x | 1 | 0 | 0 | + * | 204MHz | 204MHz | 1 | 17 | x | 1 | 0 | 0 | + *---------------------------------------------------------------------------- + * Relations beetwen PLL dividers and definitions: + * N = PLL1_NSEL + 1, M = PLL1_MSEL + 1, P = 2 ^ PLL1_PSEL + *----------------------------------------------------------------------------*/ + +/* PLL1 output clock: 180MHz, Fcco: 180MHz, N = 1, M = 15, P = x */ +#define PLL1_NSEL 0 /* Range [0 - 3]: Pre-divider ratio N */ +#define PLL1_MSEL 14 /* Range [0 - 255]: Feedback-divider ratio M */ +#define PLL1_PSEL 0 /* Range [0 - 3]: Post-divider ratio P */ + +#define PLL1_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */ +#define PLL1_DIRECT 1 /* 0: Use PSEL, 1: Don't use PSEL */ +#define PLL1_FBSEL 0 /* 0: FCCO is used as PLL feedback */ + /* 1: FCLKOUT is used as PLL feedback */ + +/*---------------------------------------------------------------------------- + * Configure Flash Accelerator + *---------------------------------------------------------------------------- + * Flash acces time: + * | CPU clock | FLASHTIM | + * | up to 21MHz | 0 | + * | up to 43MHz | 1 | + * | up to 64MHz | 2 | + * | up to 86MHz | 3 | + * | up to 107MHz | 4 | + * | up to 129MHz | 5 | + * | up to 150MHz | 6 | + * | up to 172MHz | 7 | + * | up to 193MHz | 8 | + * | up to 204MHz | 9 | + *----------------------------------------------------------------------------*/ +#define FLASHCFG_FLASHTIM 9 + + +/*---------------------------------------------------------------------------- + * Configure PLL0USB + *---------------------------------------------------------------------------- + * + * Normal operating mode without post-divider and without pre-divider + * - PLL0USB_DIRECTI = 1 + * - PLL0USB_DIRECTO = 1 + * - PLL0USB_BYPASS = 0 + * - Output frequency: + * FOUT = FIN * 2 * M + * FCCO = FOUT + * + * Normal operating mode with post-divider and without pre-divider + * - PLL0USB_DIRECTI = 1 + * - PLL0USB_DIRECTO = 0 + * - PLL0USB_BYPASS = 0 + * - Output frequency: + * FOUT = FIN * (M / P) + * FCCO = FOUT * 2 * P + * + * Normal operating mode without post-divider and with pre-divider + * - PLL0USB_DIRECTI = 0 + * - PLL0USB_DIRECTO = 1 + * - PLL0USB_BYPASS = 0 + * - Output frequency: + * FOUT = FIN * 2 * M / N + * FCCO = FOUT + * + * Normal operating mode with post-divider and with pre-divider + * - PLL0USB_DIRECTI = 0 + * - PLL0USB_DIRECTO = 0 + * - PLL0USB_BYPASS = 0 + * - Output frequency: + * FOUT = FIN * M / (P * N) + * FCCO = FOUT * 2 * P + *---------------------------------------------------------------------------- + * PLL0 requirements: + * | Frequency | Minimum | Maximum | Note | + * | FCLKIN | 14kHz | 25MHz | Clock source is external crystal | + * | FCLKIN | 14kHz | 150MHz | | + * | FCCO | 275MHz | 550MHz | | + * | FCLKOUT | 4.3MHz | 550MHz | | + *---------------------------------------------------------------------------- + * Configuration examples: + * | Fclkout | Fcco | N | M | P | DIRECTI | DIRECTO | BYPASS | + * | 120MHz | 480MHz | x | 20 | 2 | 1 | 0 | 0 | + * | 480MHz | 480MHz | 1 | 20 | 1 | 1 | 1 | 0 | + *----------------------------------------------------------------------------*/ + +/* PLL0USB output clock: 480MHz, Fcco: 480MHz, N = 1, M = 20, P = 1 */ +#define PLL0USB_N 1 /* Range [1 - 256]: Pre-divider */ +#define PLL0USB_M 20 /* Range [1 - 2^15]: Feedback-divider */ +#define PLL0USB_P 1 /* Range [1 - 32]: Post-divider */ + +#define PLL0USB_DIRECTI 1 /* 0: Use N_DIV, 1: Don't use N_DIV */ +#define PLL0USB_DIRECTO 1 /* 0: Use P_DIV, 1: Don't use P_DIV */ +#define PLL0USB_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */ + + +/*---------------------------------------------------------------------------- + End of configuration + *----------------------------------------------------------------------------*/ + +/* PLL0 Setting Check */ +#if (PLL0USB_BYPASS == 0) + #if (PLL0USB_CLK_SEL == CLK_SRC_XTAL) + #define PLL0USB_CLKIN CLK_XTAL + #else + #define PLL0USB_CLKIN CLK_IRC + #endif + + #if ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 1)) /* Mode 1a */ + #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M) + #define PLL0USB_FCCO (PLL0USB_FOUT) + #elif ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 0)) /* Mode 1b */ + #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / PLL0USB_P) + #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P) + #elif ((PLL0USB_DIRECTI == 0) && (PLL0USB_DIRECTO == 1)) /* Mode 1c */ + #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M / PLL0USB_N) + #define PLL0USB_FCCO (PLL0USB_FOUT) + #else /* Mode 1d */ + #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / (PLL0USB_P * PLL0USB_N)) + #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P) + #endif + + #if (PLL0USB_FCCO < 275000000UL || PLL0USB_FCCO > 550000000UL) + #error "PLL0USB Fcco frequency out of range! (275MHz >= Fcco <= 550MHz)" + #endif + #if (PLL0USB_FOUT < 4300000UL || PLL0USB_FOUT > 550000000UL) + #error "PLL0USB output frequency out of range! (4.3MHz >= Fclkout <= 550MHz)" + #endif +#endif + +/* PLL1 Setting Check */ +#if (PLL1_BYPASS == 0) + #if (PLL1_CLK_SEL == CLK_SRC_XTAL) + #define PLL1_CLKIN CLK_XTAL + #else + #define PLL1_CLKIN CLK_IRC + #endif + + #if (PLL1_DIRECT == 1) /* Direct Mode */ + #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1))) + #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1))) + #elif (PLL1_FBSEL == 1) /* Integer Mode */ + #define PLL1_FCCO ((2 * (1 << PLL1_PSEL)) * (PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1))) + #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1))) + #else /* Noninteger Mode */ + #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1))) + #define PLL1_FOUT (PLL1_FCCO / (2 * (1 << PLL1_PSEL))) + #endif + #if (PLL1_FCCO < 156000000UL || PLL1_FCCO > 320000000UL) + #error "PLL1 Fcco frequency out of range! (156MHz >= Fcco <= 320MHz)" + #endif + #if (PLL1_FOUT < 9750000UL || PLL1_FOUT > 204000000UL) + #error "PLL1 output frequency out of range! (9.75MHz >= Fclkout <= 204MHz)" + #endif +#endif + +/*---------------------------------------------------------------------------- + Function prototypes + *----------------------------------------------------------------------------*/ +uint32_t MeasureFreq (uint32_t clk_sel); +uint32_t GetClockFreq (uint32_t clk_src); + +/*---------------------------------------------------------------------------- + System Core Clock variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = 180000000U; /* System Clock Frequency (Core Clock) */ + + +/****************************************************************************** + * SetClock + ******************************************************************************/ +static void SetClock (void) { + uint32_t x, i; + uint32_t selp, seli; + + /* Set flash accelerator configuration for bank A and B to reset value */ + LPC_CREG->FLASHCFGA |= (0xF << 12); + LPC_CREG->FLASHCFGB |= (0xF << 12); + + /* Set flash wait states to maximum */ + LPC_EMC->STATICWAITRD0 = 0x1F; + + /* Switch BASE_M4_CLOCK to IRC */ + LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */ + (CLK_SRC_IRC << 24) ; /* Set clock source */ + + /* Configure input to crystal oscilator */ + LPC_CGU->XTAL_OSC_CTRL = (0 << 0) | /* Enable oscillator-pad */ + (0 << 1) | /* Operation with crystal connected */ + (0 << 2) ; /* Low-frequency mode */ + + /* Wait ~250us @ 12MHz */ + for (i = 1500; i; i--); + +#ifdef USE_SPIFI +/* configure SPIFI clk to IRC via IDIVA (later IDIVA is configured to PLL1/3) */ + LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */ + (0 << 2) | /* IDIV */ + (1 << 11) | /* Autoblock En */ + (CLK_SRC_IRC << 24) ; /* Clock source */ + + LPC_CGU->BASE_SPIFI_CLK = (0 << 0) | /* Disable Power-down */ + (0 << 2) | /* IDIV */ + (1 << 11) | /* Autoblock En */ + (CLK_SRC_IDIVA << 24) ; /* Clock source */ +#endif + +/*---------------------------------------------------------------------------- + PLL1 Setup + *----------------------------------------------------------------------------*/ + /* Power down PLL */ + LPC_CGU->PLL1_CTRL |= 1; + +#if ((PLL1_FOUT > 110000000UL) && (CPU_CLK_SEL == CLK_SRC_PLL1)) + /* To run at full speed, CPU must first run at an intermediate speed */ + LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */ + (PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */ + (PLL1_FBSEL << 6) | /* PLL output used as feedback */ + (0 << 7) | /* Direct on/off */ + (PLL1_PSEL << 8) | /* PSEL */ + (0 << 11)| /* Autoblock Disabled */ + (PLL1_NSEL << 12)| /* NSEL */ + (PLL1_MSEL << 16)| /* MSEL */ + (PLL1_CLK_SEL << 24); /* Clock source */ + /* Wait for lock */ + while (!(LPC_CGU->PLL1_STAT & 1)); + + /* CPU base clock is in the mid frequency range before final clock set */ + LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */ + (0x09 << 24) ; /* Clock source: PLL1 */ + + /* Max. BASE_M4_CLK frequency here is 102MHz, wait at least 20us */ + for (i = 1050; i; i--); /* Wait minimum 2100 cycles */ +#endif + /* Configure PLL1 */ + LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */ + (PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */ + (PLL1_FBSEL << 6) | /* PLL output used as feedback */ + (PLL1_DIRECT << 7) | /* Direct on/off */ + (PLL1_PSEL << 8) | /* PSEL */ + (1 << 11)| /* Autoblock En */ + (PLL1_NSEL << 12)| /* NSEL */ + (PLL1_MSEL << 16)| /* MSEL */ + (PLL1_CLK_SEL << 24); /* Clock source */ + + /* Wait for lock */ + while (!(LPC_CGU->PLL1_STAT & 1)); + + /* Set CPU base clock source */ + LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */ + (CPU_CLK_SEL << 24) ; /* Set clock source */ + + /* Set flash accelerator configuration for internal flash bank A and B */ + LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~0x0000F000U)) | (FLASHCFG_FLASHTIM << 12); + LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~0x0000F000U)) | (FLASHCFG_FLASHTIM << 12); + +/*---------------------------------------------------------------------------- + PLL0USB Setup + *----------------------------------------------------------------------------*/ + + /* Power down PLL0USB */ + LPC_CGU->PLL0USB_CTRL |= 1; + + /* M divider */ + x = 0x00004000; + switch (PLL0USB_M) { + case 0: x = 0xFFFFFFFF; + break; + case 1: x = 0x00018003; + break; + case 2: x = 0x00010003; + break; + default: + for (i = PLL0USB_M; i <= 0x8000; i++) { + x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF); + } + } + + if (PLL0USB_M < 60) selp = (PLL0USB_M >> 1) + 1; + else selp = 31; + + if (PLL0USB_M > 16384) seli = 1; + else if (PLL0USB_M > 8192) seli = 2; + else if (PLL0USB_M > 2048) seli = 4; + else if (PLL0USB_M >= 501) seli = 8; + else if (PLL0USB_M >= 60) seli = 4 * (1024 / (PLL0USB_M + 9)); + else seli = (PLL0USB_M & 0x3C) + 4; + LPC_CGU->PLL0USB_MDIV = (selp << 17) | + (seli << 22) | + (x << 0); + + /* N divider */ + x = 0x80; + switch (PLL0USB_N) { + case 0: x = 0xFFFFFFFF; + break; + case 1: x = 0x00000302; + break; + case 2: x = 0x00000202; + break; + default: + for (i = PLL0USB_N; i <= 0x0100; i++) { + x =(((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F); + } + } + LPC_CGU->PLL0USB_NP_DIV = (x << 12); + + /* P divider */ + x = 0x10; + switch (PLL0USB_P) { + case 0: x = 0xFFFFFFFF; + break; + case 1: x = 0x00000062; + break; + case 2: x = 0x00000042; + break; + default: + for (i = PLL0USB_P; i <= 0x200; i++) { + x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) &0x0F); + } + } + LPC_CGU->PLL0USB_NP_DIV |= x; + + LPC_CGU->PLL0USB_CTRL = (PLL0USB_CLK_SEL << 24) | /* Clock source sel */ + (1 << 11) | /* Autoblock En */ + (1 << 4 ) | /* PLL0USB clock en */ + (PLL0USB_DIRECTO << 3 ) | /* Direct output */ + (PLL0USB_DIRECTI << 2 ) | /* Direct input */ + (PLL0USB_BYPASS << 1 ) | /* PLL bypass */ + (0 << 0 ) ; /* PLL0USB Enabled */ + while (!(LPC_CGU->PLL0USB_STAT & 1)); + + +/*---------------------------------------------------------------------------- + Integer divider Setup + *----------------------------------------------------------------------------*/ + + /* Configure integer dividers */ + LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */ + (IDIVA_IDIV << 2) | /* IDIV */ + (1 << 11) | /* Autoblock En */ + (IDIVA_CLK_SEL << 24) ; /* Clock source */ + + LPC_CGU->IDIVB_CTRL = (0 << 0) | /* Disable Power-down */ + (IDIVB_IDIV << 2) | /* IDIV */ + (1 << 11) | /* Autoblock En */ + (IDIVB_CLK_SEL << 24) ; /* Clock source */ + + LPC_CGU->IDIVC_CTRL = (0 << 0) | /* Disable Power-down */ + (IDIVC_IDIV << 2) | /* IDIV */ + (1 << 11) | /* Autoblock En */ + (IDIVC_CLK_SEL << 24) ; /* Clock source */ + + LPC_CGU->IDIVD_CTRL = (0 << 0) | /* Disable Power-down */ + (IDIVD_IDIV << 2) | /* IDIV */ + (1 << 11) | /* Autoblock En */ + (IDIVD_CLK_SEL << 24) ; /* Clock source */ + + LPC_CGU->IDIVE_CTRL = (0 << 0) | /* Disable Power-down */ + (IDIVE_IDIV << 2) | /* IDIV */ + (1 << 11) | /* Autoblock En */ + (IDIVE_CLK_SEL << 24) ; /* Clock source */ +} + + +/*---------------------------------------------------------------------------- + Approximate delay function (must be used after SystemCoreClockUpdate() call) + *----------------------------------------------------------------------------*/ +#define CPU_NANOSEC(x) (((uint64_t)(x) * SystemCoreClock)/1000000000) + +static void WaitUs (uint32_t us) { + uint32_t cyc = us * CPU_NANOSEC(1000)/4; + while(cyc--); +} + + +/*---------------------------------------------------------------------------- + Measure frequency using frequency monitor + *----------------------------------------------------------------------------*/ +uint32_t MeasureFreq (uint32_t clk_sel) { + uint32_t fcnt, rcnt, fout; + + /* Set register values */ + LPC_CGU->FREQ_MON &= ~(1U << 23); /* Stop frequency counters */ + LPC_CGU->FREQ_MON = (clk_sel << 24) | 511; /* RCNT == 511 */ + LPC_CGU->FREQ_MON |= (1 << 23); /* Start RCNT and FCNT */ + while (LPC_CGU->FREQ_MON & (1 << 23)) { + fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF; + rcnt = (LPC_CGU->FREQ_MON ) & 0x01FF; + if (fcnt == 0 && rcnt == 0) { + return (0); /* No input clock present */ + } + } + fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF; + fout = fcnt * (12000000U/511U); /* FCNT * (IRC_CLK / RCNT) */ + + return (fout); +} + + +/*---------------------------------------------------------------------------- + Get PLL1 (divider and multiplier) parameters + *----------------------------------------------------------------------------*/ +static __inline uint32_t GetPLL1Param (void) { + uint32_t ctrl; + uint32_t p; + uint32_t div, mul; + + ctrl = LPC_CGU->PLL1_CTRL; + div = ((ctrl >> 12) & 0x03) + 1; + mul = ((ctrl >> 16) & 0xFF) + 1; + p = 1 << ((ctrl >> 8) & 0x03); + + if (ctrl & (1 << 1)) { + /* Bypass = 1, PLL1 input clock sent to post-dividers */ + if (ctrl & (1 << 7)) { + div *= (2*p); } + } + else { + /* Direct and integer mode */ + if (((ctrl & (1 << 7)) == 0) && ((ctrl & (1 << 6)) == 0)) { + /* Non-integer mode */ + div *= (2*p); + } + } + return ((div << 8) | (mul)); +} + + +/*---------------------------------------------------------------------------- + Get input clock source for specified clock generation block + *----------------------------------------------------------------------------*/ +static int32_t GetClkSel (uint32_t clk_src) { + uint32_t reg; + int32_t clk_sel = -1; + + switch (clk_src) { + case CLK_SRC_IRC: + case CLK_SRC_ENET_RX: + case CLK_SRC_ENET_TX: + case CLK_SRC_GP_CLKIN: + return ( (int32_t) clk_src); + + case CLK_SRC_32KHZ: + return ((LPC_CREG->CREG0 & 0x0A) != 0x02) ? (-1) : (CLK_SRC_32KHZ); + case CLK_SRC_XTAL: + return (LPC_CGU->XTAL_OSC_CTRL & 1) ? (-1) : (CLK_SRC_XTAL); + + case CLK_SRC_PLL0U: reg = LPC_CGU->PLL0USB_CTRL; break; + case CLK_SRC_PLL0A: reg = LPC_CGU->PLL0AUDIO_CTRL; break; + case CLK_SRC_PLL1: reg = (LPC_CGU->PLL1_STAT & 1) ? (LPC_CGU->PLL1_CTRL) : (0); break; + + case CLK_SRC_IDIVA: reg = LPC_CGU->IDIVA_CTRL; break; + case CLK_SRC_IDIVB: reg = LPC_CGU->IDIVB_CTRL; break; + case CLK_SRC_IDIVC: reg = LPC_CGU->IDIVC_CTRL; break; + case CLK_SRC_IDIVD: reg = LPC_CGU->IDIVD_CTRL; break; + case CLK_SRC_IDIVE: reg = LPC_CGU->IDIVE_CTRL; break; + + default: + return (clk_sel); + } + if (!(reg & 1)) { + clk_sel = (reg >> 24) & 0x1F; + } + return (clk_sel); +} + + +/*---------------------------------------------------------------------------- + Get clock frequency for specified clock source + *----------------------------------------------------------------------------*/ +uint32_t GetClockFreq (uint32_t clk_src) { + uint32_t tmp; + uint32_t mul = 1; + uint32_t div = 1; + uint32_t main_freq = 0; + int32_t clk_sel = (int32_t) clk_src; + + do { + switch (clk_sel) { + case CLK_SRC_32KHZ: main_freq = CLK_32KHZ; break; + case CLK_SRC_IRC: main_freq = CLK_IRC; break; + case CLK_SRC_ENET_RX: main_freq = CLK_ENET_RX; break; + case CLK_SRC_ENET_TX: main_freq = CLK_ENET_TX; break; + case CLK_SRC_GP_CLKIN: main_freq = CLK_GP_CLKIN; break; + case CLK_SRC_XTAL: main_freq = CLK_XTAL; break; + + case CLK_SRC_IDIVA: div *= ((LPC_CGU->IDIVA_CTRL >> 2) & 0x03) + 1; break; + case CLK_SRC_IDIVB: div *= ((LPC_CGU->IDIVB_CTRL >> 2) & 0x0F) + 1; break; + case CLK_SRC_IDIVC: div *= ((LPC_CGU->IDIVC_CTRL >> 2) & 0x0F) + 1; break; + case CLK_SRC_IDIVD: div *= ((LPC_CGU->IDIVD_CTRL >> 2) & 0x0F) + 1; break; + case CLK_SRC_IDIVE: div *= ((LPC_CGU->IDIVE_CTRL >> 2) & 0xFF) + 1; break; + + case CLK_SRC_PLL0U: /* Not implemented */ break; + case CLK_SRC_PLL0A: /* Not implemented */ break; + + case CLK_SRC_PLL1: + tmp = GetPLL1Param (); + mul *= (tmp ) & 0xFF; /* PLL input clock multiplier */ + div *= (tmp >> 8) & 0xFF; /* PLL input clock divider */ + break; + + default: + return (0); /* Clock not running or not supported */ + } + if (main_freq == 0) { + clk_sel = GetClkSel ( (uint32_t) clk_sel); + } + } + while (main_freq == 0); + + return ((main_freq * mul) / div); +} + + +/*---------------------------------------------------------------------------- + System Core Clock update + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) { + /* Check BASE_M4_CLK connection */ + uint32_t base_src = (LPC_CGU->BASE_M4_CLK >> 24) & 0x1F; + + /* Update core clock frequency */ + SystemCoreClock = GetClockFreq (base_src); +} + +#if defined(__ARMCC) +extern uint32_t __Vectors; /* see startup_LPC43xx.s */ +#endif + +/*---------------------------------------------------------------------------- + Initialize the system + *----------------------------------------------------------------------------*/ +void SystemInit (void) { + + #if (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ + #endif + + /* Stop CM0 core */ + LPC_RGU->RESET_CTRL1 = (1 << 24); + + /* Disable SysTick timer */ + SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk); + + /* Set vector table pointer */ +#if defined(__ARMCC) + SCB->VTOR = ((uint32_t)(&__Vectors)) & 0xFFF00000UL; +#endif + + /* Configure PLL0 and PLL1, connect CPU clock to selected clock source */ + SetClock(); + + /* Update SystemCoreClock variable */ + SystemCoreClockUpdate(); } void SystemReset(void) diff --git a/source/hic_hal/nxp/lpc4322/system_LPC43xx.h b/source/hic_hal/nxp/lpc4322/system_LPC43xx.h index 3b0750a9b..3dc53dbea 100644 --- a/source/hic_hal/nxp/lpc4322/system_LPC43xx.h +++ b/source/hic_hal/nxp/lpc4322/system_LPC43xx.h @@ -5,7 +5,7 @@ * @brief Cortex-M3 Device System Header File for NXP lpc43xx Series. * @version 1.0 * @date 02. June. 2011 -* @author NXP MCU SW Application Team +* @author NXP MCU SW Application Team, modified by KEIL * * Copyright(C) 2011, NXP Semiconductor * All rights reserved. @@ -30,18 +30,27 @@ extern "C" { #endif -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/** + \brief System clock frequency (core clock). + The system clock frequency supplied to the SysTick timer and the + processor core clock. + */ +extern uint32_t SystemCoreClock; /** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock + retrieved from cpu registers. */ -extern void SystemInit(void); +extern void SystemCoreClockUpdate (void); #ifdef __cplusplus } From ea6013ded490d276bd1f98ec8214c3a42856c411 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 9 Nov 2021 23:39:46 -0600 Subject: [PATCH 518/617] lpc4322 (core): reduce CPU clock to 120 MHz --- source/hic_hal/nxp/lpc4322/system_LPC43xx.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/source/hic_hal/nxp/lpc4322/system_LPC43xx.c b/source/hic_hal/nxp/lpc4322/system_LPC43xx.c index 1e22e6979..8b0e13fab 100644 --- a/source/hic_hal/nxp/lpc4322/system_LPC43xx.c +++ b/source/hic_hal/nxp/lpc4322/system_LPC43xx.c @@ -32,9 +32,9 @@ ----------------------------------------------------------------------------- PLL0USB | 480 MHz | XTAL | External crystal @ 12 MHz ----------------------------------------------------------------------------- - PLL1 | 180 MHz | XTAL | External crystal @ 12 MHz + PLL1 | 120 MHz | XTAL | External crystal @ 12 MHz ----------------------------------------------------------------------------- - CPU | 180 MHz | PLL1 | CPU Clock == BASE_M4_CLK + CPU | 120 MHz | PLL1 | CPU Clock == BASE_M4_CLK ----------------------------------------------------------------------------- IDIV A | 60 MHz | PLL1 | To the USB1 peripheral ----------------------------------------------------------------------------- @@ -44,7 +44,7 @@ ----------------------------------------------------------------------------- IDIV D | 12 MHz | IRC | Internal oscillator @ 12 MHz ----------------------------------------------------------------------------- - IDIV E | 5.3 MHz | PLL1 | To the LCD controller + IDIV E | 5.2 MHz | PLL1 | To the LCD controller -----------------------------------------------------------------------------*/ @@ -93,11 +93,11 @@ /*---------------------------------------------------------------------------- Configure integer divider values *----------------------------------------------------------------------------*/ -#define IDIVA_IDIV 2 /* Divide input clock by 3 */ +#define IDIVA_IDIV 1 /* Divide input clock by 2 */ #define IDIVB_IDIV 1 /* Divide input clock by 2 */ #define IDIVC_IDIV 0 /* Divide input clock by 1 */ #define IDIVD_IDIV 0 /* Divide input clock by 1 */ -#define IDIVE_IDIV 33 /* Divide input clock by 34 */ +#define IDIVE_IDIV 22 /* Divide input clock by 23 */ /*---------------------------------------------------------------------------- @@ -159,13 +159,13 @@ * N = PLL1_NSEL + 1, M = PLL1_MSEL + 1, P = 2 ^ PLL1_PSEL *----------------------------------------------------------------------------*/ -/* PLL1 output clock: 180MHz, Fcco: 180MHz, N = 1, M = 15, P = x */ +/* PLL1 output clock: 120MHz, Fcco: 240MHz, N = 1, M = 20, P = 1 */ #define PLL1_NSEL 0 /* Range [0 - 3]: Pre-divider ratio N */ -#define PLL1_MSEL 14 /* Range [0 - 255]: Feedback-divider ratio M */ +#define PLL1_MSEL 19 /* Range [0 - 255]: Feedback-divider ratio M */ #define PLL1_PSEL 0 /* Range [0 - 3]: Post-divider ratio P */ #define PLL1_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */ -#define PLL1_DIRECT 1 /* 0: Use PSEL, 1: Don't use PSEL */ +#define PLL1_DIRECT 0 /* 0: Use PSEL, 1: Don't use PSEL */ #define PLL1_FBSEL 0 /* 0: FCCO is used as PLL feedback */ /* 1: FCLKOUT is used as PLL feedback */ @@ -185,7 +185,7 @@ * | up to 193MHz | 8 | * | up to 204MHz | 9 | *----------------------------------------------------------------------------*/ -#define FLASHCFG_FLASHTIM 9 +#define FLASHCFG_FLASHTIM 5 /*---------------------------------------------------------------------------- @@ -316,7 +316,7 @@ uint32_t GetClockFreq (uint32_t clk_src); /*---------------------------------------------------------------------------- System Core Clock variable *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = 180000000U; /* System Clock Frequency (Core Clock) */ +uint32_t SystemCoreClock = 120000000U; /* System Clock Frequency (Core Clock) */ /****************************************************************************** From c6245e5d8c0a59259fc64f0cb1b20b53dc828d5a Mon Sep 17 00:00:00 2001 From: Adrian Negreanu Date: Tue, 18 May 2021 15:45:55 +0300 Subject: [PATCH 519/617] lpc4322 (gcc): add GNU linker script The stack and heap have to reside in m_data. The largest symbols (.bss.TraceBuf, .bss.sector_buf, .bss.DAP_Cmd_queue) are explicitly placed in m_data_2. Signed-off-by: Adrian Negreanu --- records/hic_hal/lpc4322.yaml | 2 + source/hic_hal/nxp/lpc4322/gcc/lpc4322.ld | 233 ++++++++++++++++++++++ 2 files changed, 235 insertions(+) create mode 100644 source/hic_hal/nxp/lpc4322/gcc/lpc4322.ld diff --git a/records/hic_hal/lpc4322.yaml b/records/hic_hal/lpc4322.yaml index 651fb18d2..29c0023ba 100644 --- a/records/hic_hal/lpc4322.yaml +++ b/records/hic_hal/lpc4322.yaml @@ -32,6 +32,8 @@ tool_specific: hic_hal: - source/hic_hal/nxp/lpc4322/armcc gcc_arm: + linker_file: + - source/hic_hal/nxp/lpc4322/gcc/lpc4322.ld sources: hic_hal: - source/hic_hal/nxp/lpc4322/gcc diff --git a/source/hic_hal/nxp/lpc4322/gcc/lpc4322.ld b/source/hic_hal/nxp/lpc4322/gcc/lpc4322.ld new file mode 100644 index 000000000..c6dac5603 --- /dev/null +++ b/source/hic_hal/nxp/lpc4322/gcc/lpc4322.ld @@ -0,0 +1,233 @@ +/** + * @file daplink.ld + * @brief + * + * DAPLink Interface Firmware + * Copyright (c) 2016 Freescale Semiconductor, Inc. + * Copyright (c) 2020-2021 NXP, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "daplink_addr.h" + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = DAPLINK_ROM_APP_START, LENGTH = 0x400 + m_text (RX) : ORIGIN = DAPLINK_ROM_APP_START + 0x400, LENGTH = DAPLINK_ROM_APP_SIZE - 0x400 + m_cfgrom (RW) : ORIGIN = DAPLINK_ROM_CONFIG_USER_START, LENGTH = DAPLINK_ROM_CONFIG_USER_SIZE + m_data (RW) : ORIGIN = DAPLINK_RAM_APP_START, LENGTH = DAPLINK_RAM_APP_SIZE + m_cfgram (RW) : ORIGIN = DAPLINK_RAM_SHARED_START, LENGTH = DAPLINK_RAM_SHARED_SIZE + m_data_2 (RW) : ORIGIN = DAPLINK_RAM_APP2_START, LENGTH = DAPLINK_RAM_APP2_SIZE +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + FILL(0xffffffff) + . = ALIGN(4); + . += LENGTH(m_interrupts) - (. - ORIGIN(m_interrupts)); /* pad out to end of m_interrupts */ + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + + /* fill .text out to the end of the app */ + .fill __DATA_END : + { + FILL(0xffffffff) + . = ALIGN(4); + . += DAPLINK_ROM_APP_START + DAPLINK_ROM_APP_SIZE - __DATA_END - 4; + /* Need some contents in this section or it won't be copied to bin or hex. The CRC will + * be placed here by post_build_script.py. */ + LONG(0x55555555) + } > m_text + + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + .cfgrom (NOLOAD) : + { + *(cfgrom) + } > m_cfgrom + + /* Uninitialized data section */ + + /* build .bss_2 first so we don't have to exclude any sections put in here from .bss */ + .bss_2 : + { + . = ALIGN(4); + *(.bss.TraceBuf) + *(.bss.sector_buf) + *(.bss.DAP_Cmd_queue) + . = ALIGN(4); + } > m_data_2 + + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + .cfgram (NOLOAD) : + { + *(cfgram) + } > m_cfgram + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region overflowed with stack and heap") +} From fb12baf53390410c0352920a503c1fcb904ce772 Mon Sep 17 00:00:00 2001 From: Adrian Negreanu Date: Mon, 28 Dec 2020 19:36:56 +0200 Subject: [PATCH 520/617] lpc4322 (config): increase DAP_PACKET_SIZE and DAP_PACKET_COUNT Signed-off-by: Adrian Negreanu --- source/hic_hal/nxp/lpc4322/DAP_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/hic_hal/nxp/lpc4322/DAP_config.h b/source/hic_hal/nxp/lpc4322/DAP_config.h index a79b5c63d..d010aa5d4 100644 --- a/source/hic_hal/nxp/lpc4322/DAP_config.h +++ b/source/hic_hal/nxp/lpc4322/DAP_config.h @@ -97,7 +97,7 @@ typedef unsigned int BOOL; /// This configuration settings is used to optimize the communication performance with the /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB. -#define DAP_PACKET_COUNT 1 ///< Buffers: 64 = Full-Speed, 4 = High-Speed. +#define DAP_PACKET_COUNT 8 ///< Buffers: 64 = Full-Speed, 4 = High-Speed. /// Indicate that UART Serial Wire Output (SWO) trace is available. /// This information is returned by the command \ref DAP_Info as part of Capabilities. From 8fef660f6d08c112d3b62c9dab37c6e6b27af3e5 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 10 Nov 2021 00:24:11 -0600 Subject: [PATCH 521/617] lpc4322 (SWO): Add CMSIS UART Drivers From Keil LPC4300_DFP version 2.10.0 --- .../nxp/lpc4322/RTE_Driver/GPDMA_LPC43xx.c | 470 +++ .../nxp/lpc4322/RTE_Driver/GPDMA_LPC43xx.h | 212 ++ .../nxp/lpc4322/RTE_Driver/SCU_LPC43xx.c | 160 + .../nxp/lpc4322/RTE_Driver/SCU_LPC43xx.h | 198 ++ .../nxp/lpc4322/RTE_Driver/USART_LPC43xx.c | 2884 +++++++++++++++++ .../nxp/lpc4322/RTE_Driver/USART_LPC43xx.h | 319 ++ 6 files changed, 4243 insertions(+) create mode 100644 source/hic_hal/nxp/lpc4322/RTE_Driver/GPDMA_LPC43xx.c create mode 100644 source/hic_hal/nxp/lpc4322/RTE_Driver/GPDMA_LPC43xx.h create mode 100644 source/hic_hal/nxp/lpc4322/RTE_Driver/SCU_LPC43xx.c create mode 100644 source/hic_hal/nxp/lpc4322/RTE_Driver/SCU_LPC43xx.h create mode 100644 source/hic_hal/nxp/lpc4322/RTE_Driver/USART_LPC43xx.c create mode 100644 source/hic_hal/nxp/lpc4322/RTE_Driver/USART_LPC43xx.h diff --git a/source/hic_hal/nxp/lpc4322/RTE_Driver/GPDMA_LPC43xx.c b/source/hic_hal/nxp/lpc4322/RTE_Driver/GPDMA_LPC43xx.c new file mode 100644 index 000000000..22c3b1640 --- /dev/null +++ b/source/hic_hal/nxp/lpc4322/RTE_Driver/GPDMA_LPC43xx.c @@ -0,0 +1,470 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2019 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 30. April 2019 + * $Revision: V1.6 + * + * Project: GPDMA Driver for NXP LPC43xx + * -------------------------------------------------------------------------- */ + +/* History: + * Version 1.6 + * - Removed Arm Compiler 6 warnings + * - Added timeout to wait loops + * Version 1.5 + * - Corrected transfers bigger than 4k + * Version 1.4 + * - Added GPDMA_ChannelGetCount function. + * Version 1.3 + * - Added support for Cortex-M0APP and Cortex-M0SUB + * Version 1.2 + * - Updated Initialize and Uninitialize functions + * Version 1.1 + * - Corrected peripheral reset + */ + +#include "GPDMA_LPC43xx.h" + +#if (defined(CORE_M0SUB)) +#define MX_DMA_IRQn M0S_DMA_IRQn +#define MX_DMA_IRQHandler M0S_DMA_IRQHandler +#elif (defined(CORE_M0)) +#define MX_DMA_IRQn M0_DMA_IRQn +#define MX_DMA_IRQHandler M0_DMA_IRQHandler +#else +#define MX_DMA_IRQn DMA_IRQn +#define MX_DMA_IRQHandler DMA_IRQHandler +#endif + +// GPDMA Channel register block structure +typedef struct { + __IO uint32_t SRCADDR; // DMA Channel Source Address Register + __IO uint32_t DESTADDR; // DMA Channel Destination Address Register + __IO uint32_t LLI; // DMA Channel Linked List Item Register + __IO uint32_t CONTROL; // DMA Channel Control Register + __IO uint32_t CONFIG; // DMA Channel Configuration Register + __I uint32_t RESERVED1[3]; +} volatile GPDMA_CHANNEL_REG; + +typedef struct { + uint32_t SrcAddr; + uint32_t DestAddr; + uint32_t Size; + uint32_t Cnt; + GPDMA_SignalEvent_t cb_event; +} GPDMA_Channel_Info; + +static uint32_t Channel_active = 0U; +static uint32_t Init_cnt = 0U; + +static GPDMA_Channel_Info Channel_info[GPDMA_NUMBER_OF_CHANNELS] = { 0U }; + +#define GPDMA_CHANNEL(n) ((GPDMA_CHANNEL_REG *) (&(LPC_GPDMA->C0SRCADDR) + (n * 8U))) + +// Safety timeout to exit the loops +#define LOOP_MAX_CNT (SystemCoreClock / 64U) + +// Interrupt Handler Prototype +void MX_DMA_IRQHandler (void); + + +/** + \fn int32_t Set_Channel_active_flag (uint8_t ch) + \brief Protected set of channel active flag + \param[in] ch Channel number (0..7) + \returns + - \b 0: function succeeded + - \b -1: function failed +*/ +__inline static int32_t Set_Channel_active_flag (uint8_t ch) { +#if (defined(CORE_M0SUB) || defined(CORE_M0)) + __disable_irq(); + if (Channel_active & (1U << ch)) { + __enable_irq(); + return -1; + } + Channel_active |= (1U << ch); + __enable_irq(); + + return 0; +#else + uint32_t val; + + do { + val = __LDREXW (&Channel_active); + if (val & (1U << ch)) { + __CLREX (); + return -1; + } + } while (__STREXW (val | (1U << ch), &Channel_active)); + + return 0; +#endif +} + +/** + \fn void Clear_Channel_active_flag (uint8_t ch) + \brief Protected clear of channel active flag + \param[in] ch Channel number (0..7) +*/ +__inline static void Clear_Channel_active_flag (uint8_t ch) { +#if (defined(CORE_M0SUB) || defined(CORE_M0)) + __disable_irq(); + Channel_active &= ~(1U << ch); + __enable_irq(); +#else + while(__STREXW((__LDREXW(&Channel_active) & ~(1U << ch)), &Channel_active)); +#endif +} + +/** + \fn int32_t GPDMA_Initialize (void) + \brief Initialize GPDMA peripheral + \returns + - \b 0: function succeeded + - \b -1: function failed +*/ +int32_t GPDMA_Initialize (void) { + uint32_t ch_num, tout_cnt; + + Init_cnt++; + + // Check if already initialized + if (Init_cnt > 1U) { return 0; } + + // Enable DMA clock + LPC_CCU1->CLK_M4_DMA_CFG |= 1U; + tout_cnt = LOOP_MAX_CNT; + while ((LPC_CCU1->CLK_M4_DMA_STAT & 1U) == 0U) { + if (tout_cnt-- == 0U) { + __NOP(); + return -1; + } + } + + // Reset DMA + LPC_RGU->RESET_CTRL0 = ((1U << 19) | (~(LPC_RGU->RESET_ACTIVE_STATUS0))); + + // Reset all DMA channels + for (ch_num = 0U; ch_num < GPDMA_NUMBER_OF_CHANNELS; ch_num++) { + GPDMA_CHANNEL(ch_num)->CONFIG = 0U; + Channel_info[ch_num].SrcAddr = 0U; + Channel_info[ch_num].DestAddr = 0U; + Channel_info[ch_num].Size = 0U; + Channel_info[ch_num].Cnt = 0U; + } + + // Clear all DMA interrupt flags + LPC_GPDMA->INTTCCLEAR = 0xFFU; + LPC_GPDMA->INTERRCLR = 0xFFU; + + // Clear and Enable DMA IRQ + NVIC_ClearPendingIRQ(MX_DMA_IRQn); + NVIC_EnableIRQ(MX_DMA_IRQn); + + return 0; +} + +/** + \fn int32_t GPDMA_Uninitialize (void) + \brief De-initialize GPDMA peripheral + \returns + - \b 0: function succeeded + - \b -1: function failed +*/ +int32_t GPDMA_Uninitialize (void) { + + // Check if DMA is initialized + if (Init_cnt == 0U) { return -1; } + + Init_cnt--; + if (Init_cnt != 0U) { return 0; } + + // Disable DMA clock + LPC_CCU1->CLK_M4_DMA_CFG &= ~1U; + + // Disable and Clear DMA IRQ + NVIC_DisableIRQ(MX_DMA_IRQn); + NVIC_ClearPendingIRQ(MX_DMA_IRQn); + + return 0; +} + +/** + \fn int32_t GPDMA_PeripheralSelect (uint8_t peri, uint8_t sel) + \brief Selects GPDMA requests + \param[in] peri GPDMA peripheral + \param[in] sel Selects the DMA request for GPDMA input (0..3) + \returns + - \b 0: function succeeded + - \b -1: function failed +*/ +int32_t GPDMA_PeripheralSelect (uint8_t peri, uint8_t sel) { + + if ((peri > 15U) || (sel > 3U)) { return -1; } + + LPC_CREG->DMAMUX = (LPC_CREG->DMAMUX & ~(3U << (2U * peri))) | ((uint32_t)sel << (2U * peri)); + + return 0; +} + +/** + \fn int32_t GPDMA_ChannelConfigure (uint8_t ch, + uint32_t src_addr, + uint32_t dest_addr, + uint32_t size, + uint32_t control, + uint32_t config, + GPDMA_SignalEvent_t cb_event) + \brief Configure GPDMA channel for next transfer + \param[in] ch Channel number (0..7) + \param[in] src_addr Source address + \param[in] dest_addr Destination address + \param[in] size Amount of data to transfer + \param[in] control Channel control + \param[in] config Channel configuration + \param[in] cb_event Channel callback pointer + \returns + - \b 0: function succeeded + - \b -1: function failed +*/ +int32_t GPDMA_ChannelConfigure (uint8_t ch, + uint32_t src_addr, + uint32_t dest_addr, + uint32_t size, + uint32_t control, + uint32_t config, + GPDMA_SignalEvent_t cb_event) { + GPDMA_CHANNEL_REG * dma_ch; + uint32_t tout_cnt; + + // Check if channel is valid + if (ch >= GPDMA_NUMBER_OF_CHANNELS) { return -1; } + + // Set Channel active flag + if (Set_Channel_active_flag (ch) == -1) { return -1; } + + // Save callback pointer + Channel_info[ch].cb_event = cb_event; + + dma_ch = GPDMA_CHANNEL(ch); + + // Reset DMA Channel configuration + dma_ch->CONFIG = 0U; + dma_ch->CONTROL = 0U; + + // Clear DMA interrupts + LPC_GPDMA->INTTCCLEAR = (1U << ch); + LPC_GPDMA->INTERRCLR = (1U << ch); + + // Link list not supported + dma_ch->LLI = 0U; + + // Enable DMA Channels, little endian + LPC_GPDMA->CONFIG = GPDMA_CONFIG_E; + tout_cnt = LOOP_MAX_CNT; + while ((LPC_GPDMA->CONFIG & GPDMA_CONFIG_E) == 0U) { + if (tout_cnt-- == 0U) { + __NOP(); + return -1; + } + } + + Channel_info[ch].Size = size; + if (size > 0x0FFFU) { + // Max DMA transfer size = 4k + size = 0x0FFFU; + } + + control = (control & ~GPDMA_CH_CONTROL_TRANSFERSIZE_MSK) | GPDMA_CH_CONTROL_TRANSFERSIZE(size); + + // Set Source and destination address + dma_ch->SRCADDR = src_addr; + dma_ch->DESTADDR = dest_addr; + + if (control & GPDMA_CH_CONTROL_SI) { + // Source address increment + src_addr += (size << ((control & GPDMA_CH_CONTROL_SWIDTH_MSK) >> GPDMA_CH_CONTROL_SWIDTH_POS)); + } + if (control & GPDMA_CH_CONTROL_DI) { + // Destination address increment + dest_addr += (size << ((control & GPDMA_CH_CONTROL_DWIDTH_MSK) >> GPDMA_CH_CONTROL_DWIDTH_POS)); + } + + // Save channel information + Channel_info[ch].SrcAddr = src_addr; + Channel_info[ch].DestAddr = dest_addr; + Channel_info[ch].Cnt = size; + + dma_ch->CONTROL = control; + dma_ch->CONFIG = config; + + if ((config & GPDMA_CONFIG_E) == 0U) { + // Clear Channel active flag + Clear_Channel_active_flag (ch); + } + + return 0; +} + +/** + \fn int32_t GPDMA_ChannelEnable (uint8_t ch) + \brief Enable GPDMA channel + \param[in] ch Channel number (0..7) + \returns + - \b 0: function succeeded + - \b -1: function failed +*/ +int32_t GPDMA_ChannelEnable (uint8_t ch) { + + // Check if channel is valid + if (ch >= GPDMA_NUMBER_OF_CHANNELS) { return -1; } + + // Set Channel active flag + if (Set_Channel_active_flag (ch) == -1) { return -1; } + + GPDMA_CHANNEL(ch)->CONFIG |= GPDMA_CH_CONFIG_E; + return 0; +} + +/** + \fn int32_t GPDMA_ChannelDisable (uint8_t ch) + \brief Disable GPDMA channel + \param[in] ch Channel number (0..7) + \returns + - \b 0: function succeeded + - \b -1: function failed +*/ +int32_t GPDMA_ChannelDisable (uint8_t ch) { + + // Check if channel is valid + if (ch >= GPDMA_NUMBER_OF_CHANNELS) { return -1; } + + // Clear Channel active flag + Clear_Channel_active_flag (ch); + + GPDMA_CHANNEL(ch)->CONFIG &= ~GPDMA_CH_CONFIG_E; + + return 0; +} + +/** + \fn uint32_t GPDMA_ChannelGetStatus (uint8_t ch) + \brief Check if GPDMA channel is enabled or disabled + \param[in] ch Channel number (0..7) + \returns Channel status + - \b 1: channel enabled + - \b 0: channel disabled +*/ +uint32_t GPDMA_ChannelGetStatus (uint8_t ch) { + + // Check if channel is valid + if (ch >= GPDMA_NUMBER_OF_CHANNELS) { return 0U; } + + if (Channel_active & (1 << ch)) { return 1U; } + else { return 0U; } +} + +/** + \fn uint32_t GPDMA_ChannelGetCount (uint8_t ch) + \brief Get number of transferred data + \param[in] ch Channel number (0..7) + \returns Number of transferred data +*/ +uint32_t GPDMA_ChannelGetCount (uint8_t ch) { + // Check if channel is valid + if (ch >= GPDMA_NUMBER_OF_CHANNELS) return 0; + + return (Channel_info[ch].Cnt - (GPDMA_CHANNEL(ch)->CONTROL & GPDMA_CH_CONTROL_TRANSFERSIZE_MSK)); +} + +/** + \fn void DMA_IRQHandler (void) + \brief DMA interrupt handler +*/ +void MX_DMA_IRQHandler (void) { + uint8_t ch; + uint32_t size; + GPDMA_CHANNEL_REG * dma_ch; + + for (ch = 0; ch < GPDMA_NUMBER_OF_CHANNELS; ch++) { + if (LPC_GPDMA->INTSTAT & (1U << ch)) { + dma_ch = GPDMA_CHANNEL(ch); + + // Terminal count request interrupt + if (LPC_GPDMA->INTTCSTAT & (1U << ch)) { + // Clear interrupt flag + LPC_GPDMA->INTTCCLEAR = (1U << ch); + + if (Channel_info[ch].Cnt != Channel_info[ch].Size) { + // Data waiting to transfer + + size = Channel_info[ch].Size - Channel_info[ch].Cnt; + // Max DMA transfer size = 4k + if (size > 0x0FFFU) { size = 0x0FFFU; } + + Channel_info[ch].Cnt += size; + + if (dma_ch->CONTROL & GPDMA_CH_CONTROL_SI) { + // Source Address Increment + dma_ch->SRCADDR = Channel_info[ch].SrcAddr; + Channel_info[ch].SrcAddr += (size << ((dma_ch->CONTROL & GPDMA_CH_CONTROL_SWIDTH_MSK) >> GPDMA_CH_CONTROL_SWIDTH_POS)); + } + if (dma_ch->CONTROL & GPDMA_CH_CONTROL_DI) { + // Destination address increment + dma_ch->DESTADDR = Channel_info[ch].DestAddr; + Channel_info[ch].DestAddr += (size << ((dma_ch->CONTROL & GPDMA_CH_CONTROL_DWIDTH_MSK) >> GPDMA_CH_CONTROL_DWIDTH_POS)); + } + + // Set transfer size + dma_ch->CONTROL = (dma_ch->CONTROL & ~GPDMA_CH_CONTROL_TRANSFERSIZE_MSK) | GPDMA_CH_CONTROL_TRANSFERSIZE(size); + + // Enable DMA Channel + dma_ch->CONFIG |= GPDMA_CH_CONFIG_E; + } else { + // All Data has been transferred + + // Clear Channel active flag + Clear_Channel_active_flag (ch); + + // Signal Event + if (Channel_info[ch].cb_event) { + Channel_info[ch].cb_event(GPDMA_EVENT_TERMINAL_COUNT_REQUEST); + } + } + } else { + // DMA error interrupt + if (LPC_GPDMA->INTERRSTAT & (1U << ch)) { + dma_ch->CONFIG = 0U; + dma_ch->CONTROL = 0U; + + // Clear Channel active flag + Clear_Channel_active_flag (ch); + + // Clear interrupt flag + LPC_GPDMA->INTERRCLR = (1U << ch); + + // Signal Event + if (Channel_info[ch].cb_event) { + Channel_info[ch].cb_event(GPDMA_EVENT_ERROR); + } + } + } + } + } +} diff --git a/source/hic_hal/nxp/lpc4322/RTE_Driver/GPDMA_LPC43xx.h b/source/hic_hal/nxp/lpc4322/RTE_Driver/GPDMA_LPC43xx.h new file mode 100644 index 000000000..079bee1a9 --- /dev/null +++ b/source/hic_hal/nxp/lpc4322/RTE_Driver/GPDMA_LPC43xx.h @@ -0,0 +1,212 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2019 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 30. April 2019 + * $Revision: V1.3 + * + * Project: GPDMA Driver Definitions for NXP LPC43xx + * -------------------------------------------------------------------------- */ + +#ifndef __GPDMA_LPC43XX_H +#define __GPDMA_LPC43XX_H + +#include "LPC43xx.h" + +// Number of GPDMA channels +#define GPDMA_NUMBER_OF_CHANNELS ((uint8_t) 8) + +// GPDMA Events +#define GPDMA_EVENT_TERMINAL_COUNT_REQUEST (1U) +#define GPDMA_EVENT_ERROR (2U) + +// GPDMA Burst size in Source and Destination definitions +#define GPDMA_BSIZE_1 (0U) // Burst size = 1 +#define GPDMA_BSIZE_4 (1U) // Burst size = 4 +#define GPDMA_BSIZE_8 (2U) // Burst size = 8 +#define GPDMA_BSIZE_16 (3U) // Burst size = 16 +#define GPDMA_BSIZE_32 (4U) // Burst size = 32 +#define GPDMA_BSIZE_64 (5U) // Burst size = 64 +#define GPDMA_BSIZE_128 (6U) // Burst size = 128 +#define GPDMA_BSIZE_256 (7U) // Burst size = 256 + +// Width in Source transfer width and Destination transfer width definitions +#define GPDMA_WIDTH_BYTE (0U) // Width = 1 byte +#define GPDMA_WIDTH_HALFWORD (1U) // Width = 2 bytes +#define GPDMA_WIDTH_WORD (2U) // Width = 4 bytes + +// GPDMA Transfer type and flow control +#define GPDMA_TRANSFER_M2M_CTRL_DMA (0U) // Memory to memory - DMA control +#define GPDMA_TRANSFER_M2P_CTRL_DMA (1U) // Memory to peripheral - DMA control +#define GPDMA_TRANSFER_P2M_CTRL_DMA (2U) // Peripheral to memory - DMA control +#define GPDMA_TRANSFER_P2P_CTRL_DMA (3U) // Source peripheral to destination peripheral - DMA control +#define GPDMA_TRANSFER_P2P_CTRL_DEST_PERI (4U) // Source peripheral to destination peripheral - destination peripheral control +#define GPDMA_TRANSFER_M2P_CTRL_PERI (5U) // Memory to peripheral - peripheral control +#define GPDMA_TRANSFER_P2M_CTRL_PERI (6U) // Peripheral to memory - peripheral control +#define GPDMA_TRANSFER_P2P_CTRL_SRC_PERI (7U) // Source peripheral to destination peripheral - source peripheral control + +// GPDMA Configuration register definitions +#define GPDMA_CONFIG_E (1U << 0) +#define GPDMA_CONFIG_M0 (1U << 1) +#define GPDMA_CONFIG_M1 (1U << 2) + +// GPDMA Channel Configuration registers definitions +#define GPDMA_CH_CONFIG_E (1U << 0) +#define GPDMA_CH_CONFIG_SRC_PERI_POS ( 1U) +#define GPDMA_CH_CONFIG_SRC_PERI_MSK (0x1FU << GPDMA_CH_CONFIG_SRC_PERI_POS) +#define GPDMA_CH_CONFIG_SRC_PERI(n) ((((uint32_t)n) << GPDMA_CH_CONFIG_SRC_PERI_POS) & GPDMA_CH_CONFIG_SRC_PERI_MSK) +#define GPDMA_CH_CONFIG_DEST_PERI_POS ( 6U) +#define GPDMA_CH_CONFIG_DEST_PERI_MSK (0x1FU << GPDMA_CH_CONFIG_DEST_PERI_POS) +#define GPDMA_CH_CONFIG_DEST_PERI(n) ((((uint32_t)n) << GPDMA_CH_CONFIG_DEST_PERI_POS) & GPDMA_CH_CONFIG_DEST_PERI_MSK) +#define GPDMA_CH_CONFIG_FLOWCNTRL_POS ( 11U) +#define GPDMA_CH_CONFIG_FLOWCNTRL_MSK (0x03U << GPDMA_CH_CONFIG_FLOWCNTRL_POS) +#define GPDMA_CH_CONFIG_FLOWCNTRL(n) ((((uint32_t)n) << GPDMA_CH_CONFIG_FLOWCNTRL_POS) & GPDMA_CH_CONFIG_FLOWCNTRL_MSK) +#define GPDMA_CH_CONFIG_IE (1U << 14) +#define GPDMA_CH_CONFIG_ITC (1U << 15) +#define GPDMA_CH_CONFIG_L (1U << 16) +#define GPDMA_CH_CONFIG_A (1U << 17) +#define GPDMA_CH_CONFIG_H (1U << 18) + +// GPDMA Channel Control register definition +#define GPDMA_CH_CONTROL_TRANSFERSIZE_POS ( 0U) +#define GPDMA_CH_CONTROL_TRANSFERSIZE_MSK (0xFFFU << GPDMA_CH_CONTROL_TRANSFERSIZE_POS) +#define GPDMA_CH_CONTROL_TRANSFERSIZE(n) ((((uint32_t)n) << GPDMA_CH_CONTROL_TRANSFERSIZE_POS) & GPDMA_CH_CONTROL_TRANSFERSIZE_MSK) +#define GPDMA_CH_CONTROL_SBSIZE_POS ( 12U) +#define GPDMA_CH_CONTROL_SBSIZE_MSK (0x03U << GPDMA_CH_CONTROL_SBSIZE_POS) +#define GPDMA_CH_CONTROL_SBSIZE(n) ((((uint32_t)n) << GPDMA_CH_CONTROL_SBSIZE_POS) & GPDMA_CH_CONTROL_SBSIZE_MSK) +#define GPDMA_CH_CONTROL_DBSIZE_POS ( 15U) +#define GPDMA_CH_CONTROL_DBSIZE_MSK (0x03U << GPDMA_CH_CONTROL_DBSIZE_POS) +#define GPDMA_CH_CONTROL_DBSIZE(n) ((((uint32_t)n) << GPDMA_CH_CONTROL_DBSIZE_POS) & GPDMA_CH_CONTROL_DBSIZE_MSK) +#define GPDMA_CH_CONTROL_SWIDTH_POS ( 18U) +#define GPDMA_CH_CONTROL_SWIDTH_MSK (0x03U << GPDMA_CH_CONTROL_SWIDTH_POS) +#define GPDMA_CH_CONTROL_SWIDTH(n) ((((uint32_t)n) << GPDMA_CH_CONTROL_SWIDTH_POS) & GPDMA_CH_CONTROL_SWIDTH_MSK) +#define GPDMA_CH_CONTROL_DWIDTH_POS ( 21U) +#define GPDMA_CH_CONTROL_DWIDTH_MSK (0x03U << GPDMA_CH_CONTROL_DWIDTH_POS) +#define GPDMA_CH_CONTROL_DWIDTH(n) ((((uint32_t)n) << GPDMA_CH_CONTROL_DWIDTH_POS) & GPDMA_CH_CONTROL_DWIDTH_MSK) +#define GPDMA_CH_CONTROL_S (1U << 24) +#define GPDMA_CH_CONTROL_D (1U << 25) +#define GPDMA_CH_CONTROL_SI (1U << 26) +#define GPDMA_CH_CONTROL_DI (1U << 27) +#define GPDMA_CH_CONTROL_PROT1 (1U << 28) +#define GPDMA_CH_CONTROL_PROT2 (1U << 29) +#define GPDMA_CH_CONTROL_PROT3 (1U << 30) +#define GPDMA_CH_CONTROL_I (1UL << 31) + +/** + \fn void GPDMA_SignalEvent_t (uint32_t event) + \brief Signal GPDMA Events. + \param[in] event GPDMA Event mask + \return none +*/ +typedef void (*GPDMA_SignalEvent_t) (uint32_t event); + +/** + \fn int32_t GPDMA_Initialize (void) + \brief Initialize GPDMA peripheral + \returns + - \b 0: function succeeded + - \b -1: function failed +*/ +extern int32_t GPDMA_Initialize (void); + +/** + \fn int32_t GPDMA_Uninitialize (void) + \brief De-initialize GPDMA peripheral + \returns + - \b 0: function succeeded + - \b -1: function failed +*/ +extern int32_t GPDMA_Uninitialize (void); + +/** + \fn int32_t GPDMA_PeripheralSelect (uint8_t peri, uint8_t sel) + \brief Selects GPDMA requests + \param[in] peri GPDMA peripheral (0..15) + \param[in] sel Selects the DMA request for GPDMA input (0..3) + \returns + - \b 0: function succeeded + - \b -1: function failed +*/ +extern int32_t GPDMA_PeripheralSelect (uint8_t peri, uint8_t sel); + +/** + \fn int32_t GPDMA_ChannelConfigure (uint8_t ch, + uint32_t src_addr, + uint32_t dest_addr, + uint32_t size, + uint32_t control, + uint32_t config, + GPDMA_SignalEvent_t cb_event) + \brief Configure GPDMA channel for next transfer + \param[in] ch Channel number (0..7) + \param[in] src_addr Source address + \param[in] dest_addr Destination address + \param[in] size Amount of data to transfer + \param[in] control Channel control + \param[in] config Channel configuration + \param[in] cb_event Channel callback pointer + \returns + - \b 0: function succeeded + - \b -1: function failed +*/ +extern int32_t GPDMA_ChannelConfigure (uint8_t ch, + uint32_t src_addr, + uint32_t dest_addr, + uint32_t size, + uint32_t control, + uint32_t config, + GPDMA_SignalEvent_t cb_event); + +/** + \fn int32_t GPDMA_ChannelEnable (uint8_t ch) + \brief Enable GPDMA channel + \param[in] ch Channel number (0..7) + \returns + - \b 0: function succeeded + - \b -1: function failed +*/ +extern int32_t GPDMA_ChannelEnable (uint8_t ch); + +/** + \fn int32_t GPDMA_ChannelDisable (uint8_t ch) + \brief Disable GPDMA channel + \param[in] ch Channel number (0..7) + \returns + - \b 0: function succeeded + - \b -1: function failed +*/ +extern int32_t GPDMA_ChannelDisable (uint8_t ch); + +/** + \fn uint32_t GPDMA_ChannelGetStatus (uint8_t ch) + \brief Check if GPDMA channel is enabled or disabled + \param[in] ch Channel number (0..7) + \returns Channel status + - \b 1: channel enabled + - \b 0: channel disabled +*/ +extern uint32_t GPDMA_ChannelGetStatus (uint8_t ch); + +/** + \fn uint32_t GPDMA_ChannelGetCount (uint8_t ch) + \brief Get number of transferred data + \param[in] ch Channel number (0..7) + \returns Number of transferred data +*/ +extern uint32_t GPDMA_ChannelGetCount (uint8_t ch); + +#endif /* __GPDMA_LPC43XX_H */ diff --git a/source/hic_hal/nxp/lpc4322/RTE_Driver/SCU_LPC43xx.c b/source/hic_hal/nxp/lpc4322/RTE_Driver/SCU_LPC43xx.c new file mode 100644 index 000000000..146b2b7ae --- /dev/null +++ b/source/hic_hal/nxp/lpc4322/RTE_Driver/SCU_LPC43xx.c @@ -0,0 +1,160 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2019 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 30. April 2019 + * $Revision: V1.2 + * + * Project: SCU Driver for NXP LPC43xx + * -------------------------------------------------------------------------- */ + +/* History: + * Version 1.1 + * - Corrected SCU_SFSCLKx(clk_pin) and SCU_ENAIOx(n) macros + * Version 1.0 + * - Initial release + */ + +#include "LPC43xx.h" +#include "SCU_LPC43xx.h" + +#define PORT_OFFSET ( 0x80 ) +#define PIN_OFFSET ( 0x04 ) +#define SCU_SFSPx(port, pin) (*((volatile uint32_t *) ((LPC_SCU_BASE + PORT_OFFSET * port + PIN_OFFSET * pin)))) +#define SCU_SFSCLKx(clk_pin) (*((volatile uint32_t *) (&(LPC_SCU->SFSCLK_0) + clk_pin))) +#define SCU_ENAIOx(n) (*((volatile uint32_t *) (&(LPC_SCU->ENAIO0) + n))) + + +/** + \fn int32_t SCU_PinConfiguare (uint8_t port, uint8_t pin, uint32_t pin_cfg) + \brief Set pin function and electrical characteristics + \param[in] port Port number (0..15) + \param[in] pin Pin number (0..31) + \param[in] pin_cfg pin_cfg configuration bit mask + - \b 0: function succeeded + - \b -1: function failed +*/ +int32_t SCU_PinConfigure (uint8_t port, uint8_t pin, uint32_t pin_cfg) { + + if ((port > 15) || (pin > 31)) return -1; + SCU_SFSPx(port, pin) = pin_cfg; + return 0; +} + +/** + \fn int32_t SCU_CLK_PinConfigure (uint8_t clk_pin, uint32_t pin_cfg) + \brief Set pin function and electrical characteristics for CLK pins + \param[in] clk_pin Clock pin number should be 0..3 + \param[in] pin_cfg pin_cfg + - \b 0: function succeeded + - \b -1: function failed +*/ +int32_t SCU_CLK_PinConfigure (uint8_t pin_clk, uint32_t pin_cfg) { + + if (pin_clk > 3) return -1; + SCU_SFSCLKx(pin_clk) = pin_cfg; + return 0; +} + +/** + \fn int32_t SCU_USB1_PinConfigure (uint32_t USB1_pin_cfg) + \brief Pin configuration for USB1 USB_DP/USBDM pins + \param[in] USB1_pin_cfg USB1_pin_cfg configuration bit mask + - \b 0: function succeeded + - \b -1: function failed +*/ +int32_t SCU_USB1_PinConfigure (uint32_t USB1_pin_cfg) { + LPC_SCU->SFSUSB = USB1_pin_cfg; + return 0; +} + +/** + \fn int32_t SCU_I2C_PinConfigure (uint32_t I2C_mode) + \brief Set I2C pin configuration + \param[in] I2C_mode: SCU_I2C_PIN_MODE_DISABLED + SCU_I2C_PIN_MODE_STANDARD_FAST + SCU_I2C_PIN_MODE_FAST_PLUS + - \b 0: function succeeded + - \b -1: function failed +*/ +int32_t SCU_I2C_PinConfigure (uint32_t I2C_mode) { + + switch (I2C_mode) { + case SCU_I2C_PIN_MODE_DISABLED: break; + case SCU_I2C_PIN_MODE_STANDARD_FAST: break; + case SCU_I2C_PIN_MODE_FAST_PLUS: break; + default: return -1; + } + LPC_SCU->SFSI2C0 = I2C_mode; + return 0; +} + +/** + \fn int32_t SCU_ADC_ChannelPinConfigure (uint8_t ADC_num, uint8_t channel, uint32_t cmd) + \brief ADC Channel configuration + \param[in] ADC_num: 0 = ADC0, 1 = ADC1 + \param[in] channel: channel number 0..7 + \param[in] cmd: 1 - enabled, 0 - disabled + - \b 0: function succeeded + - \b -1: function failed +*/ +int32_t SCU_ADC_ChannelPinConfigure (uint8_t ADC_num, uint8_t channel, uint32_t cmd) { + + if ((ADC_num > 1) || (channel > 7) || (cmd > 1)) return -1; + cmd ? (SCU_ENAIOx(ADC_num) |= (1 << channel)) : (SCU_ENAIOx(ADC_num) &= ~(1 << channel)); + return 0; +} + +/** + \fn int32_t SCU_DAC_PinConfigure (uint32_t cmd) + \brief Analog function on P4_4 + \param[in] cmd: 1 - enabled, 0 - disabled + - \b 0: function succeeded + - \b -1: function failed +*/ +int32_t SCU_DAC_PinConfigure (uint32_t cmd) { + + if (cmd > 1) return -1; + cmd ? (LPC_SCU->ENAIO2 |= SCU_ENAIO2_DAC) : (LPC_SCU->ENAIO2 &= ~SCU_ENAIO2_DAC); + return 0; +} + +/** + \fn int32_t SCU_PinInterruptSourceSelect (uint8_t pin_int, uint8_t port, uint8_t pin) + \brief Select interrupt source pin + \param[in] pin_int: pin interrupt 0..7 + \param[in] port: GPIO port number 0..7 + \param[in] pin: GPIO pin number 0..31 + \returns + - \b 0: function succeeded + - \b -1: function failed +*/ +int32_t SCU_PinInterruptSourceSelect (uint8_t pin_int, uint8_t port, uint8_t pin) { + + if ((port > 7) || (pin > 31) || (pin_int > 7)) return -1; + + if (pin_int < 4) { + LPC_SCU->PINTSEL0 &= ~(0xFFUL << (8 * pin_int)); + LPC_SCU->PINTSEL0 |= ((uint32_t)(pin | (port << 5)) << (8 * pin_int)); + } else { + pin_int -= 4; + LPC_SCU->PINTSEL1 &= ~(0xFFUL << (8 * pin_int)); + LPC_SCU->PINTSEL1 |= ((uint32_t)(pin | (port << 5)) << (8 * pin_int)); + } + + return 0; +} diff --git a/source/hic_hal/nxp/lpc4322/RTE_Driver/SCU_LPC43xx.h b/source/hic_hal/nxp/lpc4322/RTE_Driver/SCU_LPC43xx.h new file mode 100644 index 000000000..af15236e6 --- /dev/null +++ b/source/hic_hal/nxp/lpc4322/RTE_Driver/SCU_LPC43xx.h @@ -0,0 +1,198 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2020 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 20. Januar 2020 + * $Revision: V1.2 + * + * Project: SCU Driver Definitions for NXP LPC43xx + * -------------------------------------------------------------------------- */ + +#ifndef __SCU_LPC43XX_H +#define __SCU_LPC43XX_H + +#include + +// Pin identifier +typedef struct _PIN_ID { + uint8_t port; + uint8_t num; + uint8_t reserved[2]; + uint32_t config_val; +} PIN_ID; + +//------------------------------------------------------------------------------ +// SCU REGISTER BIT DEFINITIONS +//------------------------------------------------------------------------------ +// SCU Pin configuration register for normal-drive pins +#define SCU_SFS_MODE_POS ( 0U ) +#define SCU_SFS_MODE_MSK (7U << SCU_SFS_MODE_POS) +#define SCU_SFS_EPD (1U << 3) +#define SCU_SFS_EPUN (1U << 4) +#define SCU_SFS_EHS (1U << 5) +#define SCU_SFS_EZI (1U << 6) +#define SCU_SFS_ZIF (1U << 7) + +// SCU Pin configuration register for high-drive pins +// P1_17 +// P2_3 to P2_5 +// P8_0 to P8_2 +// PA_1 to PA_3 +#define SCU_SFS_EHD_POS ( 8U ) +#define SCU_SFS_EHD_MSK (3U << SCU_SFS_EHD_POS) + +// SCU Pin configuration register for USB1 pins USB1_DP/USB1_DM +#define SCU_SFSUSB_AIM (1U << 0) +#define SCU_SFSUSB_ESEA (1U << 1) +#define SCU_SFSUSB_EPD (1U << 2) +#define SCU_SFSUSB_EPWR (1U << 4) +#define SCU_SFSUSB_VBUS (1U << 5) + +// SCU Pin configuration for open-drain I2C pins +#define SCU_SFSI2C_SCL_EFP (1U << 0) +#define SCU_SFSI2C_SCL_EHD (1U << 2) +#define SCU_SFSI2C_SCL_EZI (1U << 3) +#define SCU_SFSI2C_SCL_ZIF (1U << 7) +#define SCU_SFSI2C_SDA_EFP (1U << 8) +#define SCU_SFSI2C_SDA_EHD (1U << 10) +#define SCU_SFSI2C_SDA_EZI (1U << 11) +#define SCU_SFSI2C_SDA_ZIF (1U << 15) + +// SCU Analog function select register ENAIO2 +#define SCU_ENAIO2_DAC (1U << 0) +#define SCU_ENAIO2_BG (1U << 4) + + + +//------------------------------------------------------------------------------ +// SCU FUNCTION PARAMETER DEFINITIONS +//------------------------------------------------------------------------------ +// SCU_PIN_CFG_MODE(mode) +#define SCU_CFG_MODE_FUNC0 (0U) +#define SCU_CFG_MODE_FUNC1 (1U) +#define SCU_CFG_MODE_FUNC2 (2U) +#define SCU_CFG_MODE_FUNC3 (3U) +#define SCU_CFG_MODE_FUNC4 (4U) +#define SCU_CFG_MODE_FUNC5 (5U) +#define SCU_CFG_MODE_FUNC6 (6U) +#define SCU_CFG_MODE_FUNC7 (7U) + +// SCU_PIN_CFG_DRIVER_STRENGTH(ehd) (only for high drive pins) +#define SCU_CFG_EHD_4mA (0U) +#define SCU_CFG_EHD_8mA (1U) +#define SCU_CFG_EHD_14mA (2U) +#define SCU_CFG_EHD_20mA (3U) + +// pin_cfg (configuration bit mask) +#define SCU_PIN_CFG_MODE(mode) (((mode) & SCU_SFS_MODE_MSK) << SCU_SFS_MODE_POS) +#define SCU_PIN_CFG_PULLDOWN_EN ( SCU_SFS_EPD ) +#define SCU_PIN_CFG_PULLUP_DIS ( SCU_SFS_EPUN) +#define SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN ( SCU_SFS_EHS ) +#define SCU_PIN_CFG_INPUT_BUFFER_EN ( SCU_SFS_EZI ) +#define SCU_PIN_CFG_INPUT_FILTER_DIS ( SCU_SFS_ZIF ) +// additional pin_cfg for high-drive pins only +#define SCU_PIN_CFG_DRIVER_STRENGTH(ehd) ((val & SCU_SFS_EHD_MSK) << SCU_SFS_EHD_POS) + +// USB1_pin_cfg (configuration bit mask) +#define SCU_USB1_PIN_CFG_AIM (SCU_SFSUSB_AIM ) +#define SCU_USB1_PIN_CFG_ESEA (SCU_SFSUSB_ESEA) +#define SCU_USB1_PIN_CFG_EPD (SCU_SFSUSB_EPD ) +#define SCU_USB1_PIN_CFG_EPWR (SCU_SFSUSB_EPWR) +#define SCU_USB1_PIN_CFG_VBUS (SCU_SFSUSB_VBUS) + +// I2C_mode +#define SCU_I2C_PIN_MODE_DISABLED (0) +#define SCU_I2C_PIN_MODE_STANDARD_FAST (SCU_SFSI2C_SCL_EZI | SCU_SFSI2C_SDA_EZI) +#define SCU_I2C_PIN_MODE_FAST_PLUS (SCU_SFSI2C_SCL_EHD | SCU_SFSI2C_SCL_EZI | \ + SCU_SFSI2C_SCL_EZI | SCU_SFSI2C_SDA_EHD | \ + SCU_SFSI2C_SDA_EZI) + + +/** + \fn int32_t SCU_PinConfiguare (uint8_t port, uint8_t pin, uint32_t pin_cfg) + \brief Set pin function and electrical characteristics + \param[in] port Port number (0..15) + \param[in] pin Pin number (0..31) + \param[in] pin_cfg pin_cfg configuration bit mask + - \b 0: function succeeded + - \b -1: function failed +*/ +extern int32_t SCU_PinConfigure (uint8_t port, uint8_t pin, uint32_t pin_cfg); + +/** + \fn int32_t SCU_CLK_PinConfigure (uint8_t clk_pin, uint32_t pin_cfg) + \brief Set pin function and electrical characteristics for CLK pins + \param[in] clk_pin Clock pin number should be 0..3 + \param[in] pin_cfg pin_cfg + - \b 0: function succeeded + - \b -1: function failed +*/ +extern int32_t SCU_CLK_PinConfigure (uint8_t pin_clk, uint32_t pin_cfg); + +/** + \fn int32_t SCU_USB1_PinConfigure (uint32_t USB1_pin_cfg) + \brief Pin configuration for USB1 USB_DP/USBDM pins + \param[in] USB1_pin_cfg USB1_pin_cfg configuration bit mask + - \b 0: function succeeded + - \b -1: function failed +*/ +extern int32_t SCU_USB1_PinConfigure (uint32_t USB1_pin_cfg); + +/** + \fn int32_t SCU_I2C_PinConfigure (uint32_t I2C_mode) + \brief Set I2C pin configuration + \param[in] I2C_mode: SCU_I2C_PIN_MODE_DISABLED + SCU_I2C_PIN_MODE_STANDARD_FAST + SCU_I2C_PIN_MODE_FAST_PLUS + - \b 0: function succeeded + - \b -1: function failed +*/ +extern int32_t SCU_I2C_PinConfigure (uint32_t I2C_mode); + +/** + \fn int32_t SCU_ADC_ChannelPinConfigure (uint8_t ADC_num, uint8_t channel, uint32_t cmd) + \brief ADC Channel configuration + \param[in] ADC_num: 0 = ADC0, 1 = ADC1 + \param[in] channel: channel number 0..7 + \param[in] cmd: 1 - enabled, 0 - disabled + - \b 0: function succeeded + - \b -1: function failed +*/ +extern int32_t SCU_ADC_ChannelPinConfigure (uint8_t ADC_num, uint8_t channel, uint32_t cmd); + +/** + \fn int32_t SCU_DAC_PinConfigure (uint32_t cmd) + \brief Analog function on P4_4 + \param[in] cmd: 1 - enabled, 0 - disabled + - \b 0: function succeeded + - \b -1: function failed +*/ +extern int32_t SCU_DAC_PinConfigure (uint32_t cmd); + +/** + \fn int32_t SCU_PinInterruptSourceSelect (uint8_t pin_int, uint8_t port, uint8_t pin) + \brief Select interrupt source pin + \param[in] pin_int: pin interrupt 0..7 + \param[in] port: GPIO port number 0..7 + \param[in] pin: GPIO pin number 0..31 + \returns + - \b 0: function succeeded + - \b -1: function failed +*/ +extern int32_t SCU_PinInterruptSourceSelect (uint8_t pin_int, uint8_t port, uint8_t pin); + +#endif /* __SCU_LPC43XX_H */ diff --git a/source/hic_hal/nxp/lpc4322/RTE_Driver/USART_LPC43xx.c b/source/hic_hal/nxp/lpc4322/RTE_Driver/USART_LPC43xx.c new file mode 100644 index 000000000..a8e290d42 --- /dev/null +++ b/source/hic_hal/nxp/lpc4322/RTE_Driver/USART_LPC43xx.c @@ -0,0 +1,2884 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2021 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 6. June 2021 + * $Revision: V2.17 + * + * Driver: Driver_USART0, Driver_USART1, Driver_USART2, Driver_USART3 + * Configured: via RTE_Device.h configuration file + * Project: USART Driver for NXP LPC43xx + * -------------------------------------------------------------------------- + * Use the following configuration settings in the middleware component + * to connect to this driver. + * + * Configuration Setting Value UART Interface + * --------------------- ----- -------------- + * Connect to hardware via Driver_USART# = 0 use USART0 + * Connect to hardware via Driver_USART# = 1 use UART1 + * Connect to hardware via Driver_USART# = 2 use USART2 + * Connect to hardware via Driver_USART# = 3 use USART3 + * -------------------------------------------------------------------------- */ + +/* History: + * Version 2.16 + * - Updated PIN_ID structure alignment + * - Removed minor compiler warnings + * Version 2.15 + * - Added function USART_PIN_Configure() + * Version 2.14 + * - Updated Baudrate divider calculation + * Version 2.13 + * - Removed Arm Compiler warnings + * - Added timeout to wait loops + * - Made Pin configuration const + * Version 2.12 + * - Updated USART_Send function. Corrected send_active flag handling. + * Version 2.11 + * - RX and TX pins can be configured as "not used" + * Version 2.10 + * - Driver update to work with GPDMA_LPC43xx ver.: 1.5 + * Version 2.9 + * - Corrected PowerControl function for conditional Power full (driver must be initialized) + * Version 2.8 + * - PowerControl for Power OFF and Uninitialize functions made unconditional. + * - Corrected status bit-field handling, to prevent race conditions. + * Version 2.7 + * - Corrected disabling of receive DMA channel when aborting + * Receive (ARM_USART_ABORT_RECEIVE) or Transfer (ARM_USART_ABORT_TRANSFER) + * Version 2.6 + * - fract_div_lookup_table moved from USART_LPC43xx.h to USART_LPC43xx.c + * Version 2.5 + * - Improved baudrate calculation + * Version 2.4 + * - Added support for Cortex-M0APP and Cortex-M0SUB + * Version 2.3 + * - Corrected RX Time-Out handling + * - Corrected USART clock configuration + * - Updated USART_Control function + * - Updated USART_Send function + * - GPDMA initialization and uninitialization + * Version 2.2 + * - Corrected peripheral reset + * - Corrected modem lines handling + * Version 2.1 + * - Added DMA support + * - Other Improvements (status checking, USART_Control, ...) + * Version 2.0 + * - Updated to CMSIS Driver API V2.00 + * Version 1.1 + * - Based on API V1.10 (namespace prefix ARM_ added) + * Version 1.0 + * - Initial release + */ +#include "USART_LPC43xx.h" + +#include + +#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,17) + +#if ((!RTE_USART0) && (!RTE_UART1) && (!RTE_USART2) && (!RTE_USART3)) +#error "USART not enabled in RTE_Device.h!" +#endif + +// Driver Version +static const ARM_DRIVER_VERSION usart_driver_version = { ARM_USART_API_VERSION, ARM_USART_DRV_VERSION }; + +// Function Prototypes +static int32_t USART_PowerControl (ARM_POWER_STATE state, USART_RESOURCES *usart); +static int32_t USART_Control (uint32_t control, uint32_t arg, USART_RESOURCES *usart); + +int32_t USART_SetBaudrate (uint32_t baudrate, USART_RESOURCES *usart); +void USART0_IRQHandler (void); +void UART1_IRQHandler (void); +void USART2_IRQHandler (void); +void USART3_IRQHandler (void); + +// Safety timeout to exit the loops +#define LOOP_MAX_CNT (SystemCoreClock / 64U) + +#if (defined(CORE_M0SUB)) +#define MX_USART0_IRQn M0S_USART0_IRQn +#define MX_UART1_IRQn M0S_UART1_IRQn +#define MX_USART2_IRQn M0S_USART2_OR_C_CAN1_IRQn +#define MX_USART3_IRQn M0S_USART3_IRQn +#define MX_USART0_IRQHandler M0S_USART0_IRQHandler +#define MX_UART1_IRQHandler M0S_UART1_IRQHandler +#define MX_USART2_OR_C_CAN1_IRQHandler M0S_USART2_OR_C_CAN1_IRQHandler +#define MX_USART2_IRQHandler M0S_USART2_IRQHandler +#define MX_USART3_IRQHandler M0S_USART3_IRQHandler +#elif (defined(CORE_M0)) +#define MX_USART0_IRQn M0_USART0_IRQn +#define MX_UART1_IRQn M0_UART1_IRQn +#define MX_USART2_IRQn M0_USART2_OR_C_CAN1_IRQn +#define MX_USART3_IRQn M0_USART3_IRQn +#define MX_USART0_IRQHandler M0_USART0_IRQHandler +#define MX_UART1_IRQHandler M0_UART1_IRQHandler +#define MX_USART2_OR_C_CAN1_IRQHandler M0_USART2_OR_C_CAN1_IRQHandler +#define MX_USART2_IRQHandler M0_USART2_IRQHandler +#define MX_USART3_IRQHandler M0_USART3_IRQHandler +#else +#define MX_USART0_IRQn USART0_IRQn +#define MX_UART1_IRQn UART1_IRQn +#define MX_USART2_IRQn USART2_IRQn +#define MX_USART3_IRQn USART3_IRQn +#define MX_USART0_IRQHandler USART0_IRQHandler +#define MX_UART1_IRQHandler UART1_IRQHandler +#define MX_USART2_IRQHandler USART2_IRQHandler +#define MX_USART3_IRQHandler USART3_IRQHandler +#endif + +// Trigger level definitions +// Can be user defined by C preprocessor +#ifndef USART0_TRIG_LVL +#define USART0_TRIG_LVL USART_TRIG_LVL_1 +#endif +#ifndef USART1_TRIG_LVL +#define USART1_TRIG_LVL USART_TRIG_LVL_1 +#endif +#ifndef USART2_TRIG_LVL +#define USART2_TRIG_LVL USART_TRIG_LVL_1 +#endif +#ifndef USART3_TRIG_LVL +#define USART3_TRIG_LVL USART_TRIG_LVL_1 +#endif + +// SmartCard oversampling ratio +#ifndef USART0_SC_OVERSAMPLING_RATIO +#define USART0_SC_OVERSAMPLING_RATIO 372 +#endif +#ifndef USART2_SC_OVERSAMPLING_RATIO +#define USART2_SC_OVERSAMPLING_RATIO 372 +#endif +#ifndef USART3_SC_OVERSAMPLING_RATIO +#define USART3_SC_OVERSAMPLING_RATIO 372 +#endif + +// Fractional divider lookup table +static const FRACT_DIVIDER fract_div_lookup_table[] = { + {(1U << 12), 0U, 0U}, + FRACT_DIV(1, 15), + FRACT_DIV(1, 14), + FRACT_DIV(1, 13), + FRACT_DIV(1, 12), + FRACT_DIV(1, 11), + FRACT_DIV(1, 10), + FRACT_DIV(1, 9), + FRACT_DIV(1, 8), + FRACT_DIV(2, 15), + FRACT_DIV(1, 7), + FRACT_DIV(2, 13), + FRACT_DIV(1, 6), + FRACT_DIV(2, 11), + FRACT_DIV(1, 5), + FRACT_DIV(3, 14), + FRACT_DIV(2, 9), + FRACT_DIV(3, 13), + FRACT_DIV(1, 4), + FRACT_DIV(4, 15), + FRACT_DIV(3, 11), + FRACT_DIV(2, 7), + FRACT_DIV(3, 10), + FRACT_DIV(4, 13), + FRACT_DIV(1, 3), + FRACT_DIV(5, 14), + FRACT_DIV(4, 11), + FRACT_DIV(3, 8), + FRACT_DIV(5, 13), + FRACT_DIV(2, 5), + FRACT_DIV(5, 12), + FRACT_DIV(3, 7), + FRACT_DIV(4, 9), + FRACT_DIV(5, 11), + FRACT_DIV(6, 13), + FRACT_DIV(7, 15), + FRACT_DIV(1, 2), + FRACT_DIV(8, 15), + FRACT_DIV(7, 13), + FRACT_DIV(6, 11), + FRACT_DIV(5, 9), + FRACT_DIV(4, 7), + FRACT_DIV(7, 12), + FRACT_DIV(3, 5), + FRACT_DIV(8, 13), + FRACT_DIV(5, 8), + FRACT_DIV(7, 11), + FRACT_DIV(9, 14), + FRACT_DIV(2, 3), + FRACT_DIV(9, 13), + FRACT_DIV(7, 10), + FRACT_DIV(5, 7), + FRACT_DIV(8, 11), + FRACT_DIV(11, 15), + FRACT_DIV(3, 4), + FRACT_DIV(10, 13), + FRACT_DIV(7, 9), + FRACT_DIV(11, 14), + FRACT_DIV(4, 5), + FRACT_DIV(9, 11), + FRACT_DIV(5, 6), + FRACT_DIV(11, 13), + FRACT_DIV(6, 7), + FRACT_DIV(13, 15), + FRACT_DIV(7, 8), + FRACT_DIV(8, 9), + FRACT_DIV(9, 10), + FRACT_DIV(10, 11), + FRACT_DIV(11, 12), + FRACT_DIV(12, 13), + FRACT_DIV(13, 14), + FRACT_DIV(14, 15) +}; + +// Fractional divider lookup table size +#define FRACT_DIV_LOOKUP_TABLE_SZ (sizeof(fract_div_lookup_table) / sizeof(fract_div_lookup_table[0])) + +// USART0 +#if (RTE_USART0) +static USART_INFO USART0_Info = {0}; +#if (RTE_USART0_TX_PIN_EN == 1) +static const PIN_ID USART0_pin_tx = { RTE_USART0_TX_PORT, RTE_USART0_TX_BIT, {0U, 0U}, RTE_USART0_TX_FUNC }; +#endif +#if (RTE_USART0_RX_PIN_EN == 1) +static const PIN_ID USART0_pin_rx = { RTE_USART0_RX_PORT, RTE_USART0_RX_BIT, {0U, 0U}, RTE_USART0_RX_FUNC }; +#endif +#if (RTE_USART0_UCLK_PIN_EN == 1) +static const PIN_ID USART0_pin_clk = { RTE_USART0_UCLK_PORT, RTE_USART0_UCLK_BIT, {0U, 0U}, RTE_USART0_UCLK_FUNC }; +#endif + +#if (RTE_USART0_DMA_TX_EN == 1) +void USART0_GPDMA_Tx_Event (uint32_t event); +static USART_DMA USART0_DMA_Tx = {RTE_USART0_DMA_TX_CH, + RTE_USART0_DMA_TX_PERI, + RTE_USART0_DMA_TX_PERI_SEL, + 0U, + USART0_GPDMA_Tx_Event}; +#endif +#if (RTE_USART0_DMA_RX_EN == 1) +void USART0_GPDMA_Rx_Event (uint32_t event); +static USART_DMA USART0_DMA_Rx = {RTE_USART0_DMA_RX_CH, + RTE_USART0_DMA_RX_PERI, + RTE_USART0_DMA_RX_PERI_SEL, + 0U, + USART0_GPDMA_Rx_Event}; +#endif + +static USART_RESOURCES USART0_Resources = { + { // Capabilities + 1U, // supports UART (Asynchronous) mode +#if (RTE_USART0_UCLK_PIN_EN == 1) + 1U, // supports Synchronous Master mode + 1U, // supports Synchronous Slave mode +#else + 0U, // supports Synchronous Master mode + 0U, // supports Synchronous Slave mode +#endif + 1U, // supports UART Single-wire mode + 0U, // supports UART IrDA mode + 1U, // supports UART Smart Card mode +#if (RTE_USART0_UCLK_PIN_EN == 1) + 1U, // Smart Card Clock generator +#else + 0U, +#endif + 0U, // RTS Flow Control available + 0U, // CTS Flow Control available + 0U, // Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE + 0U, // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT + 0U, // RTS Line: 0=not available, 1=available + 0U, // CTS Line: 0=not available, 1=available + 0U, // DTR Line: 0=not available, 1=available + 0U, // DSR Line: 0=not available, 1=available + 0U, // DCD Line: 0=not available, 1=available + 0U, // RI Line: 0=not available, 1=available + 0U, // Signal CTS change event: \ref ARM_USART_EVENT_CTS + 0U, // Signal DSR change event: \ref ARM_USART_EVENT_DSR + 0U, // Signal DCD change event: \ref ARM_USART_EVENT_DCD + 0U // Signal RI change event: \ref ARM_USART_EVENT_RI +#if (defined(ARM_USART_API_VERSION) && (ARM_USART_API_VERSION >= 0x203U)) + , 0U // Reserved bits +#endif + }, + LPC_USART0, + NULL, + { // USART Pin Configuration +#if (RTE_USART0_TX_PIN_EN == 1) + &USART0_pin_tx, +#else + NULL, +#endif +#if (RTE_USART0_RX_PIN_EN == 1) + &USART0_pin_rx, +#else + NULL, +#endif +#if (RTE_USART0_UCLK_PIN_EN == 1) + &USART0_pin_clk, +#else + NULL, +#endif + NULL, NULL, NULL, NULL, NULL, NULL, + }, + { // USART Clocks Configuration + &LPC_CCU1->CLK_M4_USART0_CFG, + &LPC_CCU1->CLK_M4_USART0_STAT, + &LPC_CCU2->CLK_APB0_USART0_CFG, + &LPC_CCU2->CLK_APB0_USART0_STAT, + &LPC_CGU->BASE_UART0_CLK, + }, + { // USART Reset Configuration + (1U << 12), + &LPC_RGU->RESET_CTRL1, + &LPC_RGU->RESET_ACTIVE_STATUS1, + }, + MX_USART0_IRQn, + USART0_TRIG_LVL, +#if (RTE_USART0_DMA_TX_EN == 1) + &USART0_DMA_Tx, +#else + NULL, +#endif +#if (RTE_USART0_DMA_RX_EN == 1) + &USART0_DMA_Rx, +#else + NULL, +#endif + &USART0_Info, + USART0_SC_OVERSAMPLING_RATIO, + {0U,0U} +}; +#endif + +// UART1 +#if (RTE_UART1) +static USART_INFO USART1_Info = {0}; +#if (RTE_UART1_TX_PIN_EN == 1) +static const PIN_ID USART1_pin_tx = { RTE_UART1_TX_PORT, RTE_UART1_TX_BIT, {0U, 0U}, RTE_UART1_TX_FUNC }; +#endif +#if (RTE_UART1_RX_PIN_EN == 1) +static const PIN_ID USART1_pin_rx = { RTE_UART1_RX_PORT, RTE_UART1_RX_BIT, {0U, 0U}, RTE_UART1_RX_FUNC }; +#endif +#if (RTE_UART1_CTS_PIN_EN == 1) +static const PIN_ID USART1_pin_cts = { RTE_UART1_CTS_PORT, RTE_UART1_CTS_BIT, {0U, 0U}, RTE_UART1_CTS_FUNC }; +#endif +#if (RTE_UART1_RTS_PIN_EN == 1) +static const PIN_ID USART1_pin_rts = { RTE_UART1_RTS_PORT, RTE_UART1_RTS_BIT, {0U, 0U}, RTE_UART1_RTS_FUNC }; +#endif +#if (RTE_UART1_DCD_PIN_EN == 1) +static const PIN_ID USART1_pin_dcd = { RTE_UART1_DCD_PORT, RTE_UART1_DCD_BIT, {0U, 0U}, RTE_UART1_DCD_FUNC }; +#endif +#if (RTE_UART1_DSR_PIN_EN == 1) +static const PIN_ID USART1_pin_dsr = { RTE_UART1_DSR_PORT, RTE_UART1_DSR_BIT, {0U, 0U}, RTE_UART1_DSR_FUNC }; +#endif +#if (RTE_UART1_DTR_PIN_EN == 1) +static const PIN_ID USART1_pin_dtr = { RTE_UART1_DTR_PORT, RTE_UART1_DTR_BIT, {0U, 0U}, RTE_UART1_DTR_FUNC }; +#endif +#if (RTE_UART1_RI_PIN_EN == 1) +static const PIN_ID USART1_pin_ri = { RTE_UART1_RI_PORT, RTE_UART1_RI_BIT, {0U, 0U}, RTE_UART1_RI_FUNC }; +#endif + +#if (RTE_UART1_DMA_TX_EN == 1) +void USART1_GPDMA_Tx_Event (uint32_t event); +static USART_DMA USART1_DMA_Tx = {RTE_UART1_DMA_TX_CH, + RTE_UART1_DMA_TX_PERI, + RTE_UART1_DMA_TX_PERI_SEL, + 0U, + USART1_GPDMA_Tx_Event}; +#endif +#if (RTE_UART1_DMA_RX_EN == 1) +void USART1_GPDMA_Rx_Event (uint32_t event); +static USART_DMA USART1_DMA_Rx = {RTE_UART1_DMA_RX_CH, + RTE_UART1_DMA_RX_PERI, + RTE_UART1_DMA_RX_PERI_SEL, + 0U, + USART1_GPDMA_Rx_Event}; +#endif + +static USART_RESOURCES USART1_Resources = { + { // Capabilities + 1U, // supports UART (Asynchronous) mode + 0U, // supports Synchronous Master mode + 0U, // supports Synchronous Slave mode + 0U, // supports UART Single-wire mode + 0U, // supports UART IrDA mode + 0U, // supports UART Smart Card mode + 0U, // Smart Card Clock generator +#if (RTE_UART1_RTS_PIN_EN == 1) + 1U, // RTS Flow Control available +#else + 0U, // RTS Flow Control available +#endif +#if (RTE_UART1_CTS_PIN_EN == 1) + 1U, // CTS Flow Control available +#else + 0U, // CTS Flow Control available +#endif + 0U, // Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE + 0U, // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT +#if (RTE_UART1_RTS_PIN_EN == 1) + 1U, // RTS Line: 0=not available, 1=available +#else + 0U, +#endif +#if (RTE_UART1_CTS_PIN_EN == 1) + 1U, // CTS Line: 0=not available, 1=available +#else + 0U, +#endif +#if (RTE_UART1_DTR_PIN_EN == 1) + 1U, // DTR Line: 0=not available, 1=available +#else + 0U, +#endif +#if (RTE_UART1_DSR_PIN_EN == 1) + 1U, // DSR Line: 0=not available, 1=available +#else + 0U, +#endif +#if (RTE_UART1_DCD_PIN_EN == 1) + 1U, // DCD Line: 0=not available, 1=available +#else + 0U, +#endif +#if (RTE_UART1_RI_PIN_EN == 1) + 1U, // RI Line: 0=not available, 1=available +#else + 0U, +#endif +#if (RTE_UART1_CTS_PIN_EN == 1) + 1U, // Signal CTS change event: \ref ARM_USART_EVENT_CTS +#else + 0U, +#endif +#if (RTE_UART1_DSR_PIN_EN == 1) + 1U, // Signal DSR change event: \ref ARM_USART_EVENT_DSR +#else + 0U, +#endif +#if (RTE_UART1_DCD_PIN_EN == 1) + 1U, // Signal DCD change event: \ref ARM_USART_EVENT_DCD +#else + 0U, +#endif +#if (RTE_UART1_RI_PIN_EN == 1) + 1U // Signal RI change event: \ref ARM_USART_EVENT_RI +#else + 0U +#endif +#if (defined(ARM_USART_API_VERSION) && (ARM_USART_API_VERSION >= 0x203U)) + , 0U // Reserved bits +#endif + }, + (LPC_USARTn_Type *)LPC_UART1, + LPC_UART1, + { // USART Pin Configuration +#if (RTE_UART1_TX_PIN_EN == 1) + &USART1_pin_tx, +#else + NULL, +#endif +#if (RTE_UART1_RX_PIN_EN == 1) + &USART1_pin_rx, +#else + NULL, +#endif + NULL, +#if (RTE_UART1_CTS_PIN_EN == 1) + &USART1_pin_cts, +#else + NULL, +#endif +#if (RTE_UART1_RTS_PIN_EN == 1) + &USART1_pin_rts, +#else + NULL, +#endif +#if (RTE_UART1_DCD_PIN_EN == 1) + &USART1_pin_dcd, +#else + NULL, +#endif +#if (RTE_UART1_DSR_PIN_EN == 1) + &USART1_pin_dsr, +#else + NULL, +#endif +#if (RTE_UART1_DTR_PIN_EN == 1) + &USART1_pin_dtr, +#else + NULL, +#endif +#if (RTE_UART1_RI_PIN_EN == 1) + &USART1_pin_ri, +#else + NULL, +#endif + }, + { // USART Clocks Configuration + &LPC_CCU1->CLK_M4_UART1_CFG, + &LPC_CCU1->CLK_M4_UART1_STAT, + &LPC_CCU2->CLK_APB0_UART1_CFG, + &LPC_CCU2->CLK_APB0_UART1_STAT, + &LPC_CGU->BASE_UART1_CLK, + }, + { // USART Reset Configuration + (1U << 13), + &LPC_RGU->RESET_CTRL1, + &LPC_RGU->RESET_ACTIVE_STATUS1, + }, + MX_UART1_IRQn, + USART1_TRIG_LVL, +#if (RTE_UART1_DMA_TX_EN == 1) + &USART1_DMA_Tx, +#else + NULL, +#endif +#if (RTE_UART1_DMA_RX_EN == 1) + &USART1_DMA_Rx, +#else + NULL, +#endif + &USART1_Info, + 0, + {0U,0U} +}; +#endif + +// USART2 +#if (RTE_USART2) +static USART_INFO USART2_Info = {0}; +#if (RTE_USART2_TX_PIN_EN == 1) +static const PIN_ID USART2_pin_tx = { RTE_USART2_TX_PORT, RTE_USART2_TX_BIT, {0U, 0U}, RTE_USART2_TX_FUNC }; +#endif +#if (RTE_USART2_RX_PIN_EN == 1) +static const PIN_ID USART2_pin_rx = { RTE_USART2_RX_PORT, RTE_USART2_RX_BIT, {0U, 0U}, RTE_USART2_RX_FUNC }; +#endif +#if (RTE_USART2_UCLK_PIN_EN == 1) +static const PIN_ID USART2_pin_clk = { RTE_USART2_UCLK_PORT, RTE_USART2_UCLK_BIT, {0U, 0U}, RTE_USART2_UCLK_FUNC }; +#endif + +#if (RTE_USART2_DMA_TX_EN == 1) +void USART2_GPDMA_Tx_Event (uint32_t event); +static USART_DMA USART2_DMA_Tx = {RTE_USART2_DMA_TX_CH, + RTE_USART2_DMA_TX_PERI, + RTE_USART2_DMA_TX_PERI_SEL, + 0U, + USART2_GPDMA_Tx_Event}; +#endif +#if (RTE_USART2_DMA_RX_EN == 1) +void USART2_GPDMA_Rx_Event (uint32_t event); +static USART_DMA USART2_DMA_Rx = {RTE_USART2_DMA_RX_CH, + RTE_USART2_DMA_RX_PERI, + RTE_USART2_DMA_RX_PERI_SEL, + 0U, + USART2_GPDMA_Rx_Event}; +#endif + +static USART_RESOURCES USART2_Resources = { + { // Capabilities + 1U, // supports UART (Asynchronous) mode +#if (RTE_USART2_UCLK_PIN_EN == 1) + 1U, // supports Synchronous Master mode + 1U, // supports Synchronous Slave mode +#else + 0U, // supports Synchronous Master mode + 0U, // supports Synchronous Slave mode +#endif + 1U, // supports UART Single-wire mode + 0U, // supports UART IrDA mode + 1U, // supports UART Smart Card mode +#if (RTE_USART2_UCLK_PIN_EN == 1) + 1U, // Smart Card Clock generator +#else + 0U, +#endif + 0U, // RTS Flow Control available + 0U, // CTS Flow Control available + 0U, // Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE + 0U, // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT + 0U, // RTS Line: 0=not available, 1=available + 0U, // CTS Line: 0=not available, 1=available + 0U, // DTR Line: 0=not available, 1=available + 0U, // DSR Line: 0=not available, 1=available + 0U, // DCD Line: 0=not available, 1=available + 0U, // RI Line: 0=not available, 1=available + 0U, // Signal CTS change event: \ref ARM_USART_EVENT_CTS + 0U, // Signal DSR change event: \ref ARM_USART_EVENT_DSR + 0U, // Signal DCD change event: \ref ARM_USART_EVENT_DCD + 0U // Signal RI change event: \ref ARM_USART_EVENT_RI +#if (defined(ARM_USART_API_VERSION) && (ARM_USART_API_VERSION >= 0x203U)) + , 0U // Reserved bits +#endif + }, + LPC_USART2, + NULL, + { // USART Pin Configuration +#if (RTE_USART2_TX_PIN_EN == 1) + &USART2_pin_tx, +#else + NULL, +#endif +#if (RTE_USART2_RX_PIN_EN == 1) + &USART2_pin_rx, +#else + NULL, +#endif +#if (RTE_USART2_UCLK_PIN_EN == 1) + &USART2_pin_clk, +#else + NULL, +#endif + NULL, NULL, NULL, NULL, NULL, NULL, + }, + { // USART Clocks Configuration + &LPC_CCU1->CLK_M4_USART2_CFG, + &LPC_CCU1->CLK_M4_USART2_STAT, + &LPC_CCU2->CLK_APB2_USART2_CFG, + &LPC_CCU2->CLK_APB2_USART2_STAT, + &LPC_CGU->BASE_UART2_CLK, + }, + { // USART Reset Configuration + (1U << 14), + &LPC_RGU->RESET_CTRL1, + &LPC_RGU->RESET_ACTIVE_STATUS1, + }, + MX_USART2_IRQn, + USART2_TRIG_LVL, +#if (RTE_USART2_DMA_TX_EN == 1) + &USART2_DMA_Tx, +#else + NULL, +#endif +#if (RTE_USART2_DMA_RX_EN == 1) + &USART2_DMA_Rx, +#else + NULL, +#endif + &USART2_Info, + USART2_SC_OVERSAMPLING_RATIO, + {0U,0U} +}; +#endif + +// USART3 +#if (RTE_USART3) +static USART_INFO USART3_Info = {0}; +#if (RTE_USART3_TX_PIN_EN == 1) +static const PIN_ID USART3_pin_tx = { RTE_USART3_TX_PORT, RTE_USART3_TX_BIT, {0U, 0U}, RTE_USART3_TX_FUNC }; +#endif +#if (RTE_USART3_RX_PIN_EN == 1) +static const PIN_ID USART3_pin_rx = { RTE_USART3_RX_PORT, RTE_USART3_RX_BIT, {0U, 0U}, RTE_USART3_RX_FUNC }; +#endif +#if (RTE_USART3_UCLK_PIN_EN == 1) +static const PIN_ID USART3_pin_clk = { RTE_USART3_UCLK_PORT, RTE_USART3_UCLK_BIT, {0U, 0U}, RTE_USART3_UCLK_FUNC }; +#endif + +#if (RTE_USART3_DMA_TX_EN == 1) +void USART3_GPDMA_Tx_Event (uint32_t event); +static USART_DMA USART3_DMA_Tx = {RTE_USART3_DMA_TX_CH, + RTE_USART3_DMA_TX_PERI, + RTE_USART3_DMA_TX_PERI_SEL, + 0U, + USART3_GPDMA_Tx_Event}; +#endif +#if (RTE_USART3_DMA_RX_EN == 1) +void USART3_GPDMA_Rx_Event (uint32_t event); +static USART_DMA USART3_DMA_Rx = {RTE_USART3_DMA_RX_CH, + RTE_USART3_DMA_RX_PERI, + RTE_USART3_DMA_RX_PERI_SEL, + 0U, + USART3_GPDMA_Rx_Event}; +#endif + +static USART_RESOURCES USART3_Resources = { + { // Capabilities + 1U, // supports UART (Asynchronous) mode +#if (RTE_USART3_UCLK_PIN_EN == 1) + 1U, // supports Synchronous Master mode + 1U, // supports Synchronous Slave mode +#else + 0U, // supports Synchronous Master mode + 0U, // supports Synchronous Slave mode +#endif + 1U, // supports UART Single-wire mode + 1U, // supports UART IrDA mode + 1U, // supports UART Smart Card mode +#if (RTE_USART3_UCLK_PIN_EN == 1) + 1U, // Smart Card Clock generator +#else + 0U, +#endif + 0U, // RTS Flow Control available + 0U, // CTS Flow Control available + 0U, // Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE + 0U, // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT + 0U, // RTS Line: 0=not available, 1=available + 0U, // CTS Line: 0=not available, 1=available + 0U, // DTR Line: 0=not available, 1=available + 0U, // DSR Line: 0=not available, 1=available + 0U, // DCD Line: 0=not available, 1=available + 0U, // RI Line: 0=not available, 1=available + 0U, // Signal CTS change event: \ref ARM_USART_EVENT_CTS + 0U, // Signal DSR change event: \ref ARM_USART_EVENT_DSR + 0U, // Signal DCD change event: \ref ARM_USART_EVENT_DCD + 0U // Signal RI change event: \ref ARM_USART_EVENT_RI +#if (defined(ARM_USART_API_VERSION) && (ARM_USART_API_VERSION >= 0x203U)) + , 0U // Reserved bits +#endif + }, + LPC_USART3, + NULL, + { // USART Pin Configuration +#if (RTE_USART3_TX_PIN_EN == 1) + &USART3_pin_tx, +#else + NULL, +#endif +#if (RTE_USART3_RX_PIN_EN == 1) + &USART3_pin_rx, +#else + NULL, +#endif +#if (RTE_USART3_UCLK_PIN_EN == 1) + &USART3_pin_clk, +#else + NULL, +#endif + NULL, NULL, NULL, NULL, NULL, NULL, + }, + { // USART Clocks Configuration + &LPC_CCU1->CLK_M4_USART3_CFG, + &LPC_CCU1->CLK_M4_USART3_STAT, + &LPC_CCU2->CLK_APB2_USART3_CFG, + &LPC_CCU2->CLK_APB2_USART3_STAT, + &LPC_CGU->BASE_UART3_CLK, + }, + { // USART Reset Configuration + (1U << 15), + &LPC_RGU->RESET_CTRL1, + &LPC_RGU->RESET_ACTIVE_STATUS1, + }, + MX_USART3_IRQn, + USART3_TRIG_LVL, +#if (RTE_USART3_DMA_TX_EN == 1) + &USART3_DMA_Tx, +#else + NULL, +#endif +#if (RTE_USART3_DMA_RX_EN == 1) + &USART3_DMA_Rx, +#else + NULL, +#endif + &USART3_Info, + USART3_SC_OVERSAMPLING_RATIO, + {0U,0U} +}; +#endif + + +// Extern Function +extern uint32_t GetClockFreq (uint32_t clk_src); + +// Local Function +/** + \fn int32_t USART_SetBaudrate (uint32_t baudrate, + USART_RESOURCES *usart) + \brief Set baudrate dividers + \param[in] baudrate Usart baudrate + \param[in] usart Pointer to USART resources) + \returns + - \b 0: function succeeded + - \b -1: function failed +*/ +int32_t USART_SetBaudrate (uint32_t baudrate, USART_RESOURCES *usart) { + uint8_t add, mul, add_mul_best, oversampling_fract_best; + uint16_t latch_div_best, oversampling, oversampling_best; + uint32_t i, j, pclk, div, tmp_div, latch_div, delta, delta_best, val; + + pclk = GetClockFreq ((*usart->clk.base_clk >> 24) & 0x1FU); + + // Calculate fixed point divider (12 LSBs are fractional part) + div = (uint32_t)(((uint64_t)pclk << FRACT_BITS) / (uint64_t)baudrate); + + delta_best = 0xFFFFFFFFU; + oversampling_fract_best = 0U; + add_mul_best = 0U; + latch_div_best = 0U; + oversampling = 0U; + oversampling_best = 0U; + + // SmartCard mode + if (usart->info->mode == ARM_USART_MODE_SMART_CARD) { + oversampling_best = usart->sc_oversamp; + for (i = 0; i < FRACT_DIV_LOOKUP_TABLE_SZ; i++) { + // Calculate latch divider (latch_div = div / (fract_div * oversampling(16))) + latch_div = ((div / fract_div_lookup_table[i].val) / oversampling_best); + + if (latch_div > 65535U) { continue; } + + for (j = 0U; j < 2U; j++) { + // Which latch divider value is more appropriate: + // latch_div or latch_div + 1 (rounded up) + + if (latch_div < 3U) { latch_div++; continue; } + + // Calculate actual divider (temp_div = latch_div * fract_div * oversampling(16)) + tmp_div = (latch_div * fract_div_lookup_table[i].val) / oversampling_best; + + // Calculate delta + if (div > tmp_div) { delta = div - tmp_div; } + else { delta = tmp_div - div; } + + // Check if delta is better than best delta + if (delta < delta_best) { + delta_best = delta; + add_mul_best = fract_div_lookup_table[i].add_mul; + latch_div_best = latch_div & 0xFFFFU; + } + latch_div++; + } + } + } else { + + // Oversampling is fixed to 16 + // divider = oversampling * latch divider * fractional divider = 16 * latch_div * fract_div + // check if divider value is integer (no fractional part) + latch_div = div >> (FRACT_BITS + 4U); + if ((div == (latch_div << (FRACT_BITS + 4U))) && ((latch_div >> 4) <= 0xFFFFU)) { + // Fractional part of divider is 0 + delta_best = 0U; + add_mul_best = 0U; + latch_div_best = latch_div & 0xFFFFU; + oversampling_best = 16U; + } else if (div >= FIXED_OVERSAMPLING_DIVIDER_LIMIT) { + // Divider larger than 48, can be accomplished with configurable + // latch and fractional divider, and fixed oversampling to 16 + + for (i = 0U; i < FRACT_DIV_LOOKUP_TABLE_SZ; i++) { + // Calculate latch divider (latch_div = div / (fract_div * oversampling(16))) + latch_div = ((div / fract_div_lookup_table[i].val) >> 4); + + if (latch_div > 65535U) { continue; } + + for (j = 0U; j < 2U; j++) { + // Which latch divider value is more appropriate: + // latch_div or latch_div + 1 (rounded up) + + if (latch_div < 3U) { latch_div++; continue; } + + // Calculate actual divider (temp_div = latch_div * fract_div * oversampling(16)) + tmp_div = (latch_div * fract_div_lookup_table[i].val) << 4; + + // Calculate delta + if (div > tmp_div) { delta = div - tmp_div; } + else { delta = tmp_div - div; } + + // Check if delta is better than best delta + if (delta < delta_best) { + delta_best = delta; + add_mul_best = fract_div_lookup_table[i].add_mul; + latch_div_best = latch_div & 0xFFFFU; + oversampling_best = 16U; + } + latch_div++; + } + } + } else if (usart->uart_reg == NULL) { + // Oversampling register is available + + if (div > INTEGER_OVERSAMPLING_DIVIDER_LIMIT) { + // Oversampling ratio is integer value + + // Set oversampling + if (div > (48U << 12)) { oversampling = 15U; } + else if (div > (45U << 12)) { oversampling = 14U; } + else if (div > (42U << 12)) { oversampling = 13U; } + else if (div > (38U << 12)) { oversampling = 12U; } + else if (div > (35U << 12)) { oversampling = 11U; } + else if (div > (32U << 12)) { oversampling = 10U; } + else if (div > (29U << 12)) { oversampling = 9U; } + else if (div > (26U << 12)) { oversampling = 8U; } + else if (div > (23U << 12)) { oversampling = 7U; } + else if (div > (19U << 12)) { oversampling = 6U; } + else if (div > (16U << 12)) { oversampling = 5U; } + else { oversampling = 4U; } + + // Check if divider is integer value + tmp_div = (div / oversampling); + if ((tmp_div & FRACT_MASK) == 0U) { + // Fractional part of divider is 0 + delta_best = 0U; + add_mul_best = 0U; + latch_div_best = (tmp_div >> FRACT_BITS) & 0xFFFFU; + oversampling_best = oversampling; + } else { + // Fractional part of divider is not 0 + + latch_div = 3U; + + for (i = 0U; i < FRACT_DIV_LOOKUP_TABLE_SZ; i++) { + + // Calculate actual divider (temp_div = latch_div * fract_div * oversampling) + tmp_div = latch_div * fract_div_lookup_table[i].val * oversampling; + + // Calculate delta + if (div > tmp_div) { delta = div - tmp_div; } + else { delta = tmp_div - div; } + + // Check if delta is better than best delta + if (delta < delta_best) { + delta_best = delta; + add_mul_best = fract_div_lookup_table[i].add_mul; + latch_div_best = latch_div & 0xFFFFU; + oversampling_best = oversampling; + } + } + } + + //tmp_div = latch_div_best * fract_best * oversampling_best; + add = add_mul_best & 0x0FU; + mul = add_mul_best >> 4; + tmp_div = (uint32_t)(((latch_div_best * (mul + add) * oversampling_best) << 12) / mul); + if ((tmp_div & FRACT_MASK) == 0U) { + // If best possible divider is integer value, make sure + // fractional divider is 0 and max oversampling is used + + oversampling = 16U; + do { + if (((tmp_div / oversampling) & FRACT_MASK) == 0U) { + // Fractional part of divider is 0 + + tmp_div /= oversampling; + add_mul_best = 0U; + latch_div_best = (tmp_div >> FRACT_BITS) & 0xFFFFU; + oversampling_best = oversampling; + break; + } + oversampling--; + } while (oversampling >= 4U); + } + } else { + // Oversampling ratio can be fractional, + // latch divider is 1 and fractional divider is not used + + // Oversampling step + val = (125U << FRACT_BITS) / 1000U; + oversampling = 13U << FRACT_BITS; + do { + // Calculate delta + if (div > oversampling) { delta = div - oversampling; } + else { delta = oversampling - div; } + + // Check if delta is better than best delta + if (delta < delta_best) { + delta_best = delta; + add_mul_best = 0U; + latch_div_best = 1U; + oversampling_best = oversampling; + } + + oversampling -= val; + } while (oversampling >= (4U << FRACT_BITS)); + + oversampling_fract_best = (((oversampling_best & FRACT_MASK) << 3) >> FRACT_BITS) & 0x07U; + oversampling_best = (oversampling_best >> FRACT_BITS) & 0x0FU; + } + } else { + return -1; + } + } + + if (((delta_best * 100U) / div) > USART_MAX_BAUDRATE_ERROR) { return -1; } + + usart->reg->LCR |= USART_LCR_DLAB; + usart->reg->DLM = ((latch_div_best >> 8) & 0xFFU) << USART_DLM_DLMSB_POS; + usart->reg->DLL = (latch_div_best & USART_DLL_DLLSB_MSK) << USART_DLL_DLLSB_POS; + // Reset DLAB bit + usart->reg->LCR &= (~USART_LCR_DLAB); + usart->reg->FDR = ((add_mul_best & USART_FDR_MULVAL_MSK) | + (add_mul_best & USART_FDR_DIVADDVAL_MSK)); + + // Check if oversampling register is available + if (usart->uart_reg == NULL) { + usart->reg->OSR = (uint32_t)(((oversampling_best - 1) << USART_OSR_OSINT_POS) | + ( oversampling_fract_best << USART_OSR_OSFRAC_POS)); + } + + usart->info->baudrate = baudrate; + + return 0; +} + +/** + \fn uint32_t USART_RxLineIntHandler (USART_RESOURCES *usart) + \brief Receive line interrupt handler + \param[in] usart Pointer to USART resources + \return Rx Line event mask +*/ +static uint32_t USART_RxLineIntHandler (USART_RESOURCES *usart) { + uint32_t lsr, event; + + event = 0U; + lsr = usart->reg->LSR & USART_LSR_LINE_INT; + + // OverRun error + if (lsr & USART_LSR_OE) { + usart->info->rx_status.rx_overflow = 1U; + event |= ARM_USART_EVENT_RX_OVERFLOW; + + // Sync Slave mode: If Transmitter enabled, signal TX underflow + if (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE) { + if (usart->info->xfer.send_active != 0U) { + event |= ARM_USART_EVENT_TX_UNDERFLOW; + } + } + } + + // Parity error + if (lsr & USART_LSR_PE) { + usart->info->rx_status.rx_parity_error = 1U; + event |= ARM_USART_EVENT_RX_PARITY_ERROR; + } + + // Break detected + if (lsr & USART_LSR_BI) { + usart->info->rx_status.rx_break = 1U; + event |= ARM_USART_EVENT_RX_BREAK; + } + + // Framing error + if(lsr & USART_LSR_FE) { + usart->info->rx_status.rx_framing_error = 1U; + event |= ARM_USART_EVENT_RX_FRAMING_ERROR; + } + + return event; +} + +/** + \fn void USART_PIN_Configure (USART_RESOURCES *usart) + \brief Configure USART Rx and TX pin + \param[in] usart Pointer to USART resources +*/ +static void USART_PIN_Configure (USART_RESOURCES *usart) { + + switch (usart->info->mode) { + case ARM_USART_MODE_ASYNCHRONOUS: + case ARM_USART_MODE_SYNCHRONOUS_MASTER: + case ARM_USART_MODE_SYNCHRONOUS_SLAVE: + case ARM_USART_MODE_IRDA: + if (usart->info->flags & USART_FLAG_RX_ENABLED) { + // USART RX pin function selected + SCU_PinConfigure(usart->pins.rx->port, usart->pins.rx->num, + SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_INPUT_FILTER_DIS | + SCU_PIN_CFG_MODE(usart->pins.rx->config_val)); + } + else { + // GPIO pin function selected + SCU_PinConfigure(usart->pins.rx->port, usart->pins.rx->num, SCU_PIN_CFG_INPUT_FILTER_DIS | + SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0)); + } + + if (usart->info->flags & USART_FLAG_TX_ENABLED) { + // USART TX pin function selected + SCU_PinConfigure(usart->pins.tx->port, usart->pins.tx->num, + SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_INPUT_FILTER_DIS | + SCU_PIN_CFG_MODE(usart->pins.tx->config_val)); + } + else { + // GPIO pin function selected + SCU_PinConfigure(usart->pins.tx->port, usart->pins.tx->num, SCU_PIN_CFG_INPUT_FILTER_DIS | + SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0)); + } + break; + case ARM_USART_MODE_SINGLE_WIRE: + case ARM_USART_MODE_SMART_CARD: + if( (usart->info->flags & USART_FLAG_RX_ENABLED) || + (usart->info->flags & USART_FLAG_TX_ENABLED) ) { + // GPIO pin function selected + SCU_PinConfigure(usart->pins.rx->port, usart->pins.rx->num, SCU_PIN_CFG_INPUT_FILTER_DIS | + SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0)); + // USART TX pin function selected + SCU_PinConfigure(usart->pins.tx->port, usart->pins.tx->num, + SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_INPUT_FILTER_DIS | + SCU_PIN_CFG_MODE(usart->pins.tx->config_val)); + } + else { + // GPIO pin function selected + SCU_PinConfigure(usart->pins.rx->port, usart->pins.rx->num, SCU_PIN_CFG_INPUT_FILTER_DIS | + SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0)); + SCU_PinConfigure(usart->pins.tx->port, usart->pins.tx->num, SCU_PIN_CFG_INPUT_FILTER_DIS | + SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0)); + } + break; + } +} + +// Function Prototypes +static int32_t USART_Receive (void *data, + uint32_t num, + USART_RESOURCES *usart); + + +// USART Driver functions + +/** + \fn ARM_DRIVER_VERSION USARTx_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION +*/ +static ARM_DRIVER_VERSION USARTx_GetVersion (void) { + return usart_driver_version; +} + +/** + \fn ARM_USART_CAPABILITIES USART_GetCapabilities (USART_RESOURCES *usart) + \brief Get driver capabilities + \param[in] usart Pointer to USART resources + \return \ref ARM_USART_CAPABILITIES +*/ +static ARM_USART_CAPABILITIES USART_GetCapabilities (USART_RESOURCES *usart) { + return usart->capabilities; +} + +/** + \fn int32_t USART_Initialize (ARM_USART_SignalEvent_t cb_event + USART_RESOURCES *usart) + \brief Initialize USART Interface. + \param[in] cb_event Pointer to \ref ARM_USART_SignalEvent + \param[in] usart Pointer to USART resources + \return \ref execution_status +*/ +static int32_t USART_Initialize (ARM_USART_SignalEvent_t cb_event, + USART_RESOURCES *usart) { + + if (usart->info->flags & USART_FLAG_INITIALIZED) { + // Driver is already initialized + return ARM_DRIVER_OK; + } + + // Initialize USART Run-time Resources + usart->info->cb_event = cb_event; + + usart->info->rx_status.rx_busy = 0U; + usart->info->rx_status.rx_overflow = 0U; + usart->info->rx_status.rx_break = 0U; + usart->info->rx_status.rx_framing_error = 0U; + usart->info->rx_status.rx_parity_error = 0U; + + // Clear transfer information + memset((void *)&usart->info->xfer, 0, sizeof(USART_TRANSFER_INFO)); + + // Configure CTS pin + if (usart->capabilities.cts) { + SCU_PinConfigure(usart->pins.cts->port, usart->pins.cts->num, + SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | + SCU_PIN_CFG_MODE(usart->pins.cts->config_val)); + } + + // Configure RTS pin + if (usart->capabilities.rts) { + SCU_PinConfigure(usart->pins.rts->port, usart->pins.rts->num, + SCU_PIN_CFG_MODE(usart->pins.rts->config_val)); + } + + // Configure DCD pin + if (usart->capabilities.dcd) { + SCU_PinConfigure(usart->pins.dcd->port, usart->pins.dcd->num, + SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | + SCU_PIN_CFG_MODE(usart->pins.dcd->config_val)); + } + + // Configure DSR pin + if (usart->capabilities.dsr) { + SCU_PinConfigure(usart->pins.dsr->port, usart->pins.dsr->num, + SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | + SCU_PIN_CFG_MODE(usart->pins.dsr->config_val)); + } + + // Configure DTR pin + if (usart->capabilities.dtr) { + SCU_PinConfigure(usart->pins.dtr->port, usart->pins.dtr->num, + SCU_PIN_CFG_MODE(usart->pins.dtr->config_val)); + } + + // Configure RI pin + if (usart->capabilities.ri) { + SCU_PinConfigure(usart->pins.ri->port, usart->pins.ri->num, + SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | + SCU_PIN_CFG_MODE(usart->pins.ri->config_val)); + } + + // DMA Initialize + if (usart->dma_tx || usart->dma_rx) { GPDMA_Initialize (); } + + usart->info->flags = USART_FLAG_INITIALIZED; + + return ARM_DRIVER_OK; +} + +/** + \fn int32_t USART_Uninitialize (USART_RESOURCES *usart) + \brief De-initialize USART Interface. + \param[in] usart Pointer to USART resources + \return \ref execution_status +*/ +static int32_t USART_Uninitialize (USART_RESOURCES *usart) { + + if ((usart->info->flags & USART_FLAG_POWERED) != 0U) { + // If peripheral is powered, power off the peripheral + (void)USART_PowerControl(ARM_POWER_OFF, usart); + } + + // Reset TX pin configuration + if (usart->pins.tx) { + SCU_PinConfigure(usart->pins.tx->port, usart->pins.tx->num , 0U); + } + + // Reset RX pin configuration + if (usart->pins.rx) { + SCU_PinConfigure(usart->pins.rx->port, usart->pins.rx->num , 0U); + } + + // Reset CLK pin configuration + if (usart->pins.clk) { + SCU_PinConfigure(usart->pins.clk->port, usart->pins.clk->num, 0U); + } + + // Reset CTS pin configuration + if (usart->capabilities.cts) { + SCU_PinConfigure(usart->pins.cts->port, usart->pins.cts->num, 0U); + } + + // Reset RTS pin configuration + if (usart->capabilities.rts) { + SCU_PinConfigure(usart->pins.rts->port, usart->pins.rts->num, 0U); + } + + // Configure DCD pin configuration + if (usart->capabilities.dcd) { + SCU_PinConfigure(usart->pins.dcd->port, usart->pins.dcd->num, 0U); + } + + // Reset DSR pin configuration + if (usart->capabilities.dsr) { + SCU_PinConfigure(usart->pins.dsr->port, usart->pins.dsr->num, 0U); + } + + // Reset DTR pin configuration + if (usart->capabilities.dtr) { + SCU_PinConfigure(usart->pins.dtr->port, usart->pins.dtr->num, 0U); + } + + // Reset RI pin configuration + if (usart->capabilities.ri) { + SCU_PinConfigure(usart->pins.ri->port, usart->pins.ri->num, 0U); + } + + // DMA Uninitialize + if (usart->dma_tx || usart->dma_rx) { + GPDMA_Uninitialize (); + GPDMA_Initialize (); + GPDMA_Uninitialize (); + } + + // Reset USART status flags + usart->info->flags = 0U; + + return ARM_DRIVER_OK; +} + +/** + \fn int32_t USART_PowerControl (ARM_POWER_STATE state) + \brief Control USART Interface Power. + \param[in] state Power state + \param[in] usart Pointer to USART resources + \return \ref execution_status +*/ +static int32_t USART_PowerControl (ARM_POWER_STATE state, + USART_RESOURCES *usart) { + uint32_t val, tout_cnt; + + if ((usart->info->flags & USART_FLAG_INITIALIZED) == 0U) { + return ARM_DRIVER_ERROR; + } + + if ((state != ARM_POWER_OFF) && + (state != ARM_POWER_FULL) && + (state != ARM_POWER_LOW)) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + switch (state) { + case ARM_POWER_OFF: + USART_Control (ARM_USART_ABORT_SEND, 0U, usart); + USART_Control (ARM_USART_ABORT_RECEIVE, 0U, usart); + USART_Control (ARM_USART_ABORT_TRANSFER, 0U, usart); + + // Disable USART IRQ + NVIC_DisableIRQ( (IRQn_Type) usart->irq_num); + + // If DMA mode - disable TX DMA channel + if ((usart->dma_tx) && (usart->info->xfer.send_active != 0U)) { + GPDMA_ChannelDisable (usart->dma_tx->channel); + } + + // If DMA mode - disable DMA channel + if ((usart->dma_rx) && (usart->info->rx_status.rx_busy)) { + GPDMA_ChannelDisable (usart->dma_rx->channel); + } + + // Reset USART peripheral + *usart->rst.reg_cfg = (usart->rst.reg_cfg_val | (~(*(usart->rst.reg_stat)))); + tout_cnt = LOOP_MAX_CNT; + while ((*(usart->rst.reg_stat) & usart->rst.reg_cfg_val) == 0U) { + if (tout_cnt-- == 0U) { + __NOP(); + break; + } + } + + // Disable USART peripheral clock + *usart->clk.peri_cfg &= ~1U; + tout_cnt = LOOP_MAX_CNT; + while (*usart->clk.peri_cfg & 1U) { + if (tout_cnt-- == 0U) { + __NOP(); + break; + } + } + + // Disable USART register interface clock + *usart->clk.reg_cfg &= ~1U; + tout_cnt = LOOP_MAX_CNT; + while (*usart->clk.reg_cfg & 1U) { + if (tout_cnt-- == 0U) { + __NOP(); + break; + } + } + + // Clear pending USART interrupts in NVIC + NVIC_ClearPendingIRQ( (IRQn_Type) usart->irq_num); + + // Clear driver variables + usart->info->rx_status.rx_busy = 0U; + usart->info->rx_status.rx_overflow = 0U; + usart->info->rx_status.rx_break = 0U; + usart->info->rx_status.rx_framing_error = 0U; + usart->info->rx_status.rx_parity_error = 0U; + + // Clear transfer information + memset((void *)&usart->info->xfer, 0, sizeof(USART_TRANSFER_INFO)); + + usart->info->flags &= ~(USART_FLAG_POWERED | USART_FLAG_CONFIGURED); + break; + + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + + case ARM_POWER_FULL: + if ((usart->info->flags & USART_FLAG_INITIALIZED) == 0U) { return ARM_DRIVER_ERROR; } + if ((usart->info->flags & USART_FLAG_POWERED) != 0U) { return ARM_DRIVER_OK; } + + // Connect USART base clock to PLL1 + *usart->clk.base_clk = (1U << 11) | + (0x09U << 24) ; + + // Enable USART register interface clock + *usart->clk.reg_cfg |= CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN; + tout_cnt = LOOP_MAX_CNT; + while ((*usart->clk.reg_cfg & CCU_CLK_CFG_RUN) == 0U) { + if (tout_cnt-- == 0U) { + __NOP(); + return ARM_DRIVER_ERROR; + } + } + + // Enable USART peripheral clock + *usart->clk.peri_cfg |= CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN; + tout_cnt = LOOP_MAX_CNT; + while (( *usart->clk.peri_cfg & CCU_CLK_CFG_RUN) == 0U) { + if (tout_cnt-- == 0U) { + __NOP(); + return ARM_DRIVER_ERROR; + } + } + + // Reset USART peripheral + *usart->rst.reg_cfg = (usart->rst.reg_cfg_val | (~(*(usart->rst.reg_stat)))); + tout_cnt = LOOP_MAX_CNT; + while ((*(usart->rst.reg_stat) & usart->rst.reg_cfg_val) == 0U) { + if (tout_cnt-- == 0U) { + __NOP(); + return ARM_DRIVER_ERROR; + } + } + + // Disable transmitter + usart->reg->TER &= ~USART_TER_TXEN; + + // Disable receiver + usart->reg->RS485CTRL |= USART_RS485CTRL_RXDIS; + + // Disable interrupts + usart->reg->IER = 0U; + + // Configure FIFO Control register + // Set trigger level + val = (usart->trig_lvl & USART_FCR_RXTRIGLVL_MSK) | USART_FCR_FIFOEN; + + if (usart->dma_rx || usart->dma_tx) { + val |= USART_FCR_DMAMODE; + } + + usart->reg->FCR = val; + +#if (RTE_UART1) + // Enable modem lines status interrupts (only UART1) + if (usart->uart_reg) { + if (usart->capabilities.cts || usart->capabilities.dcd || + usart->capabilities.dsr || usart->capabilities.ri) { + usart->uart_reg->IER |= UART_IER_MSIE; + } + } +#endif + + // Clear driver variables + usart->info->rx_status.rx_busy = 0U; + usart->info->rx_status.rx_overflow = 0U; + usart->info->rx_status.rx_break = 0U; + usart->info->rx_status.rx_framing_error = 0U; + usart->info->rx_status.rx_parity_error = 0U; + + usart->info->mode = 0U; + usart->info->flags = 0U; + usart->info->xfer.send_active = 0U; + + usart->info->flags = USART_FLAG_POWERED | USART_FLAG_INITIALIZED; + + // Clear and Enable USART IRQ + NVIC_ClearPendingIRQ( (IRQn_Type) usart->irq_num); + NVIC_EnableIRQ( (IRQn_Type) usart->irq_num); + } + return ARM_DRIVER_OK; +} + +/** + \fn int32_t USART_Send (const void *data, + uint32_t num, + USART_RESOURCES *usart) + \brief Start sending data to USART transmitter. + \param[in] data Pointer to buffer with data to send to USART transmitter + \param[in] num Number of data items to send + \param[in] usart Pointer to USART resources + \return \ref execution_status +*/ +static int32_t USART_Send (const void *data, + uint32_t num, + USART_RESOURCES *usart) { + int32_t stat; + uint32_t source_inc, event; + + if ((data == NULL) || (num == 0U)) { + // Invalid parameters + return ARM_DRIVER_ERROR_PARAMETER; + } + + if ((usart->info->flags & USART_FLAG_CONFIGURED) == 0U) { + // USART is not configured (mode not selected) + return ARM_DRIVER_ERROR; + } + + if (usart->info->xfer.send_active != 0U) { + // Send is not completed yet + return ARM_DRIVER_ERROR_BUSY; + } + + // Set Send active flag + usart->info->xfer.send_active = 1U; + + // For DMA mode: source increment + source_inc = GPDMA_CH_CONTROL_SI; + + // Synchronous mode + if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) || + (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) { + if (usart->info->xfer.sync_mode == 0U) { + usart->info->xfer.sync_mode = USART_SYNC_MODE_TX; + // Start dummy reads + USART_Control (ARM_USART_CONTROL_RX, 1U, usart); + stat = USART_Receive (&usart->info->xfer.rx_dump_val, num, usart); + if (stat != ARM_DRIVER_OK) { return ARM_DRIVER_ERROR; } + + } else { + if (usart->info->xfer.sync_mode == USART_SYNC_MODE_RX) { + // Dummy DMA writes (do not increment source address) + source_inc = 0U; + } + } + } + + // Save transmit buffer info + usart->info->xfer.tx_buf = (uint8_t *)(uint32_t)data; + usart->info->xfer.tx_num = num; + usart->info->xfer.tx_cnt = 0U; + + // DMA mode + if (usart->dma_tx) { + + // Configure DMA mux + GPDMA_PeripheralSelect (usart->dma_tx->peripheral, usart->dma_tx->peripheral_sel); + + // Configure DMA channel + stat = GPDMA_ChannelConfigure (usart->dma_tx->channel, + (uint32_t)data, + (uint32_t)(&(usart->reg->THR)), + num, + GPDMA_CH_CONTROL_SBSIZE(GPDMA_BSIZE_1) | + GPDMA_CH_CONTROL_DBSIZE(GPDMA_BSIZE_1) | + GPDMA_CH_CONTROL_SWIDTH(GPDMA_WIDTH_BYTE) | + GPDMA_CH_CONTROL_DWIDTH(GPDMA_WIDTH_BYTE) | + GPDMA_CH_CONTROL_S | + GPDMA_CH_CONTROL_D | + GPDMA_CH_CONTROL_I | + source_inc, + GPDMA_CH_CONFIG_DEST_PERI(usart->dma_tx->peripheral) | + GPDMA_CH_CONFIG_FLOWCNTRL(GPDMA_TRANSFER_M2P_CTRL_DMA) | + GPDMA_CH_CONFIG_IE | + GPDMA_CH_CONFIG_ITC | + GPDMA_CH_CONFIG_E, + usart->dma_tx->cb_event); + if (stat == -1) { return ARM_DRIVER_ERROR; } + + // Interrupt mode + } else { + // Fill TX FIFO + if (usart->reg->LSR & USART_LSR_THRE) { + usart->info->xfer.tx_fifo_level = 0U; + } + while ((usart->info->xfer.tx_fifo_level < 16U) && (usart->info->xfer.tx_cnt != usart->info->xfer.tx_num)) { + usart->reg->THR = usart->info->xfer.tx_buf[usart->info->xfer.tx_cnt++]; + usart->info->xfer.tx_fifo_level++; + } + if (usart->info->xfer.tx_cnt == usart->info->xfer.tx_num) { + // Clear TX busy flag + usart->info->xfer.send_active = 0U; + + event = 0U; + + // Set send complete event + if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) || + (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) { + if ((usart->info->xfer.sync_mode == USART_SYNC_MODE_TX) && + ((usart->info->flags & USART_FLAG_RX_ENABLED) == 0U)) { + event = ARM_USART_EVENT_SEND_COMPLETE; + } + } else { + event = ARM_USART_EVENT_SEND_COMPLETE; + } + + if ((usart->info->cb_event != NULL) && (event != 0U)) { + usart->info->cb_event (event); + } + } else { + // Enable transmit holding register empty interrupt + usart->reg->IER |= USART_IER_THREIE; + } + } + + return ARM_DRIVER_OK; +} + +/** + \fn int32_t USART_Receive (void *data, + uint32_t num, + USART_RESOURCES *usart) + \brief Start receiving data from USART receiver. + \param[out] data Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to receive + \param[in] usart Pointer to USART resources + \return \ref execution_status +*/ +static int32_t USART_Receive (void *data, + uint32_t num, + USART_RESOURCES *usart) { + + int32_t stat; + uint32_t dest_inc; + + if ((data == NULL) || (num == 0U)) { + // Invalid parameters + return ARM_DRIVER_ERROR_PARAMETER; + } + + if ((usart->info->flags & USART_FLAG_CONFIGURED) == 0U) { + // USART is not configured (mode not selected) + return ARM_DRIVER_ERROR; + } + + // Check if receiver is busy + if (usart->info->rx_status.rx_busy == 1U) { + return ARM_DRIVER_ERROR_BUSY; + } + + // Set RX busy flag + usart->info->rx_status.rx_busy = 1U; + + dest_inc = GPDMA_CH_CONTROL_DI; + + // Save number of data to be received + usart->info->xfer.rx_num = num; + + // Clear RX statuses + usart->info->rx_status.rx_break = 0U; + usart->info->rx_status.rx_framing_error = 0U; + usart->info->rx_status.rx_overflow = 0U; + usart->info->rx_status.rx_parity_error = 0U; + + // Save receive buffer info + usart->info->xfer.rx_buf = (uint8_t *)data; + usart->info->xfer.rx_cnt = 0U; + + // Synchronous mode + if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) || + (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) { + if (usart->info->xfer.sync_mode == USART_SYNC_MODE_TX) { + // Dummy DMA reads (do not increment destination address) + dest_inc = 0U; + } + } + + // DMA mode + if (usart->dma_rx) { + + GPDMA_PeripheralSelect (usart->dma_rx->peripheral, usart->dma_rx->peripheral_sel); + stat = GPDMA_ChannelConfigure (usart->dma_rx->channel, + (uint32_t)&usart->reg->RBR, + (uint32_t)data, + num, + GPDMA_CH_CONTROL_SBSIZE(GPDMA_BSIZE_1) | + GPDMA_CH_CONTROL_DBSIZE(GPDMA_BSIZE_1) | + GPDMA_CH_CONTROL_SWIDTH(GPDMA_WIDTH_BYTE) | + GPDMA_CH_CONTROL_DWIDTH(GPDMA_WIDTH_BYTE) | + GPDMA_CH_CONTROL_S | + GPDMA_CH_CONTROL_D | + GPDMA_CH_CONTROL_I | + dest_inc, + GPDMA_CH_CONFIG_SRC_PERI(usart->dma_rx->peripheral) | + GPDMA_CH_CONFIG_FLOWCNTRL(GPDMA_TRANSFER_P2M_CTRL_DMA) | + GPDMA_CH_CONFIG_IE | + GPDMA_CH_CONFIG_ITC | + GPDMA_CH_CONFIG_E, + usart->dma_rx->cb_event); + if (stat == -1) { return ARM_DRIVER_ERROR; } + + // Interrupt mode + } else { + // Enable receive data available interrupt + usart->reg->IER |= USART_IER_RBRIE; + } + + // Synchronous mode + if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) || + (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) { + if (usart->info->xfer.sync_mode == 0U) { + usart->info->xfer.sync_mode = USART_SYNC_MODE_RX; + // Send dummy data + USART_Control (ARM_USART_CONTROL_TX, 1U, usart); + stat = USART_Send (&usart->info->xfer.tx_def_val, num, usart); + if (stat != ARM_DRIVER_OK) { return ARM_DRIVER_ERROR; } + } + } + + return ARM_DRIVER_OK; +} + +/** + \fn int32_t USART_Transfer (const void *data_out, + void *data_in, + uint32_t num, + USART_RESOURCES *usart) + \brief Start sending/receiving data to/from USART transmitter/receiver. + \param[in] data_out Pointer to buffer with data to send to USART transmitter + \param[out] data_in Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to transfer + \param[in] usart Pointer to USART resources + \return \ref execution_status +*/ +static int32_t USART_Transfer (const void *data_out, + void *data_in, + uint32_t num, + USART_RESOURCES *usart) { + int32_t status; + + if ((data_out == NULL) || (data_in == NULL) || (num == 0U)) { + // Invalid parameters + return ARM_DRIVER_ERROR_PARAMETER; + } + + if ((usart->info->flags & USART_FLAG_CONFIGURED) == 0U) { + // USART is not configured + return ARM_DRIVER_ERROR; + } + + if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) || + (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) { + + // Set xfer mode + usart->info->xfer.sync_mode = USART_SYNC_MODE_TX_RX; + + // Receive + status = USART_Receive (data_in, num, usart); + if (status != ARM_DRIVER_OK) { return status; } + + // Send + status = USART_Send (data_out, num, usart); + if (status != ARM_DRIVER_OK) { return status; } + + } else { + // Only in synchronous mode + return ARM_DRIVER_ERROR; + } + return ARM_DRIVER_OK; +} + +/** + \fn uint32_t USART_GetTxCount (USART_RESOURCES *usart) + \brief Get transmitted data count. + \param[in] usart Pointer to USART resources + \return number of data items transmitted +*/ +static uint32_t USART_GetTxCount (USART_RESOURCES *usart) { + uint32_t cnt; + + if (usart->dma_tx) { + cnt = GPDMA_ChannelGetCount (usart->dma_tx->channel); + } else { + cnt = usart->info->xfer.tx_cnt; + } + + return cnt; +} + +/** + \fn uint32_t USART_GetRxCount (USART_RESOURCES *usart) + \brief Get received data count. + \param[in] usart Pointer to USART resources + \return number of data items received +*/ +static uint32_t USART_GetRxCount (USART_RESOURCES *usart) { + uint32_t cnt; + + if (usart->dma_rx) { + cnt = GPDMA_ChannelGetCount (usart->dma_rx->channel); + } else { + cnt = usart->info->xfer.rx_cnt; + } + + return cnt; +} + +/** + \fn int32_t USART_Control (uint32_t control, + uint32_t arg, + USART_RESOURCES *usart) + \brief Control USART Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \param[in] usart Pointer to USART resources + \return common \ref execution_status and driver specific \ref usart_execution_status +*/ +static int32_t USART_Control (uint32_t control, + uint32_t arg, + USART_RESOURCES *usart) { + uint8_t mode; + uint32_t val, syncctrl, hden, icr, scictrl, lcr, mcr = 0U; + uint32_t cnt; + + if ((usart->info->flags & USART_FLAG_POWERED) == 0U) { + // USART not powered + return ARM_DRIVER_ERROR; + } + + syncctrl = 0U; + hden = 0U; + icr = 0U; + scictrl = 0U; + lcr = 0U; + + switch (control & ARM_USART_CONTROL_Msk) { + // Control TX + case ARM_USART_CONTROL_TX: + if (arg) { + usart->info->flags |= USART_FLAG_TX_ENABLED; + USART_PIN_Configure (usart); + usart->reg->TER |= USART_TER_TXEN; + } else { + usart->info->flags &= ~USART_FLAG_TX_ENABLED; + usart->reg->TER &= ~USART_TER_TXEN; + USART_PIN_Configure (usart); + } + return ARM_DRIVER_OK; + + // Control RX + case ARM_USART_CONTROL_RX: + // RX Line interrupt enable (overrun, framing, parity error, break) + if (arg) { + usart->info->flags |= USART_FLAG_RX_ENABLED; + usart->reg->RS485CTRL &= ~USART_RS485CTRL_RXDIS; + USART_PIN_Configure (usart); + usart->reg->IER |= USART_IER_RXIE; + } else { + usart->info->flags &= ~USART_FLAG_RX_ENABLED; + usart->reg->RS485CTRL |= USART_RS485CTRL_RXDIS; + usart->reg->IER &= ~USART_IER_RXIE; + USART_PIN_Configure (usart); + } + return ARM_DRIVER_OK; + + // Control break + case ARM_USART_CONTROL_BREAK: + if (arg) { + if (usart->info->xfer.send_active != 0U) { return ARM_DRIVER_ERROR_BUSY; } + + usart->reg->LCR |= USART_LCR_BC; + + // Set Send active flag + usart->info->xfer.send_active = 1U; + } + else { + usart->reg->LCR &= ~USART_LCR_BC; + + // Clear Send active flag + usart->info->xfer.send_active = 0U; + } + return ARM_DRIVER_OK; + + // Abort Send + case ARM_USART_ABORT_SEND: + // Disable transmit holding register empty interrupt + usart->reg->IER &= ~USART_IER_THREIE; + + // Set trigger level + val = (usart->trig_lvl & USART_FCR_RXTRIGLVL_MSK) | USART_FCR_FIFOEN; + if (usart->dma_rx || usart->dma_tx) { + val |= USART_FCR_DMAMODE; + } + + // Transmit FIFO reset + val |= USART_FCR_TXFIFORES; + usart->reg->FCR = val; + + // If DMA mode - disable DMA channel + if ((usart->dma_tx) && (usart->info->xfer.send_active != 0U)) { + GPDMA_ChannelDisable (usart->dma_tx->channel); + } + + if (usart->info->xfer.send_active != 0U) { + if ((usart->reg->LSR & USART_LSR_TEMT) == 0U) { + // If transmit is in progess, wait for it to finish + cnt = 2000000U; + while (((usart->reg->LSR & USART_LSR_TEMT) == 0U) && (cnt-- != 0U)); + } + } + + // Synchronous mode + if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) || + (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) { + if (usart->info->xfer.sync_mode == USART_SYNC_MODE_TX) { + usart->info->xfer.sync_mode = 0U; + // Abort receive also + USART_Control (ARM_USART_ABORT_RECEIVE, 0U, usart); + USART_Control (ARM_USART_CONTROL_RX, 0U, usart); + } + } + + // Clear Send active flag + usart->info->xfer.send_active = 0U; + return ARM_DRIVER_OK; + + // Abort receive + case ARM_USART_ABORT_RECEIVE: + // Disable receive data available interrupt + usart->reg->IER &= ~USART_IER_RBRIE; + + // Set trigger level + val = (usart->trig_lvl & USART_FCR_RXTRIGLVL_MSK) | + USART_FCR_FIFOEN; + if (usart->dma_rx || usart->dma_tx) { + val |= USART_FCR_DMAMODE; + } + + // Receive FIFO reset + val |= USART_FCR_RXFIFORES; + usart->reg->FCR = val; + + // If DMA mode - disable DMA channel + if ((usart->dma_rx) && (usart->info->rx_status.rx_busy)) { + GPDMA_ChannelDisable (usart->dma_rx->channel); + } + + // Synchronous mode + if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) || + (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) { + if (usart->info->xfer.sync_mode == USART_SYNC_MODE_RX) { + usart->info->xfer.sync_mode = 0U; + // Abort send also + USART_Control (ARM_USART_ABORT_SEND, 0U, usart); + USART_Control (ARM_USART_CONTROL_TX, 0U, usart); + } + } + + // Clear RX busy status + usart->info->rx_status.rx_busy = 0U; + return ARM_DRIVER_OK; + + // Abort transfer + case ARM_USART_ABORT_TRANSFER: + // Disable transmit holding register empty and + // receive data available interrupts + usart->reg->IER &= ~(USART_IER_THREIE | USART_IER_RBRIE); + + // If DMA mode - disable DMA channel + if ((usart->dma_tx) && (usart->info->xfer.send_active != 0U)) { + GPDMA_ChannelDisable (usart->dma_tx->channel); + } + if ((usart->dma_rx) && (usart->info->rx_status.rx_busy)) { + GPDMA_ChannelDisable (usart->dma_rx->channel); + } + + // Set trigger level + val = (usart->trig_lvl & USART_FCR_RXTRIGLVL_MSK) | USART_FCR_FIFOEN; + if (usart->dma_rx || usart->dma_tx) { + val |= USART_FCR_DMAMODE; + } + + // Transmit and receive FIFO reset + val |= USART_FCR_TXFIFORES | USART_FCR_RXFIFORES; + usart->reg->FCR = val; + + if (usart->info->xfer.send_active != 0U) { + if ((usart->reg->LSR & USART_LSR_TEMT) == 0U) { + // If transmit is in progess, wait for it to finish + cnt = 2000000U; + while (((usart->reg->LSR & USART_LSR_TEMT) == 0U) && (cnt-- != 0U)); + } + } + + // Clear sync_mode + usart->info->xfer.sync_mode = 0U; + + // Clear busy statuses + usart->info->rx_status.rx_busy = 0U; + usart->info->xfer.send_active = 0U; + return ARM_DRIVER_OK; + + default: break; + } + + switch (control & ARM_USART_CONTROL_Msk) { + case ARM_USART_MODE_ASYNCHRONOUS: + mode = ARM_USART_MODE_ASYNCHRONOUS; + break; + case ARM_USART_MODE_SYNCHRONOUS_MASTER: + if (usart->capabilities.synchronous_master) { + // Enable synchronous master (SCLK out) mode + syncctrl = USART_SYNCCTRL_SYNC | USART_SYNCCTRL_CSRC; + } else { return ARM_USART_ERROR_MODE; } + mode = ARM_USART_MODE_SYNCHRONOUS_MASTER; + break; + case ARM_USART_MODE_SYNCHRONOUS_SLAVE: + if (usart->capabilities.synchronous_slave) { + // Enable synchronous slave (SCLK in) mode + syncctrl = USART_SYNCCTRL_SYNC; + } else { return ARM_USART_ERROR_MODE; } + mode = ARM_USART_MODE_SYNCHRONOUS_SLAVE; + break; + case ARM_USART_MODE_SINGLE_WIRE: + // Enable Half duplex + hden = USART_HDEN_HDEN; + mode = ARM_USART_MODE_SINGLE_WIRE; + break; + case ARM_USART_MODE_IRDA: + if (usart->capabilities.irda) { + // Enable IrDA mode + icr = USART_ICR_IRDAEN; + } else { return ARM_USART_ERROR_MODE; } + mode = ARM_USART_MODE_IRDA; + break; + case ARM_USART_MODE_SMART_CARD: + if (usart->capabilities.smart_card) { + // Enable Smart card mode + scictrl = USART_SCICTRL_SCIEN; + } else { return ARM_USART_ERROR_MODE; } + mode = ARM_USART_MODE_SMART_CARD; + break; + + // Default TX value + case ARM_USART_SET_DEFAULT_TX_VALUE: + usart->info->xfer.tx_def_val = arg & 0xFFU; + return ARM_DRIVER_OK; + + // IrDA pulse + case ARM_USART_SET_IRDA_PULSE: + if (usart->capabilities.irda) { + if (arg == 0U) { + usart->reg->ICR &= ~(USART_ICR_FIXPULSEEN); + } else { + val = 1000000000U / (GetClockFreq (((*usart->clk.base_clk >> 24) & 0x1FU))); + icr = usart->reg->ICR & ~USART_ICR_PULSEDIV_MSK; + if (arg <= (2U * val)) { icr |= (0U << USART_ICR_PULSEDIV_POS); } + else if (arg <= (4U * val)) { icr |= (1U << USART_ICR_PULSEDIV_POS); } + else if (arg <= (8U * val)) { icr |= (2U << USART_ICR_PULSEDIV_POS); } + else if (arg <= (16U * val)) { icr |= (3U << USART_ICR_PULSEDIV_POS); } + else if (arg <= (32U * val)) { icr |= (4U << USART_ICR_PULSEDIV_POS); } + else if (arg <= (64U * val)) { icr |= (5U << USART_ICR_PULSEDIV_POS); } + else if (arg <= (128U * val)) { icr |= (6U << USART_ICR_PULSEDIV_POS); } + else if (arg <= (256U * val)) { icr |= (7U << USART_ICR_PULSEDIV_POS); } + else { return ARM_DRIVER_ERROR; } + usart->reg->ICR = icr | USART_ICR_FIXPULSEEN; + } + } else { return ARM_DRIVER_ERROR; } + return ARM_DRIVER_OK; + + // SmartCard guard time + case ARM_USART_SET_SMART_CARD_GUARD_TIME: + if (usart->capabilities.smart_card) { + if (arg > 0xFFU) { return ARM_DRIVER_ERROR; } + usart->reg->SCICTRL &= ~USART_SCICTRL_GUARDTIME_MSK; + usart->reg->SCICTRL |= (arg << USART_SCICTRL_GUARDTIME_POS); + } else { return ARM_DRIVER_ERROR; } + return ARM_DRIVER_OK; + + // SmartCard clock + case ARM_USART_SET_SMART_CARD_CLOCK: + if (usart->capabilities.smart_card == 0U) { return ARM_DRIVER_ERROR; } + if (arg == 0U) { return ARM_DRIVER_OK; } + if (usart->capabilities.smart_card_clock) { + if ((usart->info->baudrate * (uint32_t) usart->sc_oversamp) != arg) { + return ARM_DRIVER_ERROR; + } + } else { return ARM_DRIVER_ERROR; } + return ARM_DRIVER_OK; + + // SmartCard NACK + case ARM_USART_CONTROL_SMART_CARD_NACK: + if (usart->capabilities.smart_card) { + if (arg) { usart->reg->SCICTRL &= ~USART_SCICTRL_NACKDIS; } + else { usart->reg->SCICTRL |= USART_SCICTRL_NACKDIS; } + } else return ARM_DRIVER_ERROR; + return ARM_DRIVER_OK; + + // Unsupported command + default: return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + // Check if Receiver/Transmitter is busy + if ( usart->info->rx_status.rx_busy || + (usart->info->xfer.send_active != 0U)) { + return ARM_DRIVER_ERROR_BUSY; + } + + // USART Data bits + switch (control & ARM_USART_DATA_BITS_Msk) { + case ARM_USART_DATA_BITS_5: lcr |= (0U << USART_LCR_WLS_POS); break; + case ARM_USART_DATA_BITS_6: lcr |= (1U << USART_LCR_WLS_POS); break; + case ARM_USART_DATA_BITS_7: lcr |= (2U << USART_LCR_WLS_POS); break; + case ARM_USART_DATA_BITS_8: lcr |= (3U << USART_LCR_WLS_POS); break; + default: return ARM_USART_ERROR_DATA_BITS; + } + + // USART Parity + switch (control & ARM_USART_PARITY_Msk) { + case ARM_USART_PARITY_NONE: break; + case ARM_USART_PARITY_EVEN: lcr |= (1U << USART_LCR_PS_POS) | + USART_LCR_PE; break; + case ARM_USART_PARITY_ODD: lcr |= USART_LCR_PE; break; + default: return (ARM_USART_ERROR_PARITY); + } + + // USART Stop bits + switch (control & ARM_USART_STOP_BITS_Msk) { + case ARM_USART_STOP_BITS_1: break; + case ARM_USART_STOP_BITS_2: lcr |= USART_LCR_SBS; break; + default: return ARM_USART_ERROR_STOP_BITS; + } + + // USART Flow control (RTS and CTS lines are only available on USART1) + if (usart->uart_reg != NULL) { + mcr = usart->uart_reg->MCR & ~(UART_MCR_RTSEN | UART_MCR_CTSEN); + switch (control & ARM_USART_FLOW_CONTROL_Msk) { + case ARM_USART_FLOW_CONTROL_NONE: + break; + case ARM_USART_FLOW_CONTROL_RTS: + if (usart->capabilities.flow_control_rts) { + mcr |= UART_MCR_RTSEN; + } + else { return ARM_USART_ERROR_FLOW_CONTROL; } + break; + case ARM_USART_FLOW_CONTROL_CTS: + if (usart->capabilities.flow_control_cts) { + mcr |= UART_MCR_CTSEN; + } else { + return ARM_USART_ERROR_FLOW_CONTROL; + } + break; + case ARM_USART_FLOW_CONTROL_RTS_CTS: + if (usart->capabilities.flow_control_rts && + usart->capabilities.flow_control_cts) { + mcr |= (UART_MCR_RTSEN | UART_MCR_CTSEN); + } else { + return ARM_USART_ERROR_FLOW_CONTROL; + } + break; + default: { return ARM_USART_ERROR_FLOW_CONTROL; } + } + } + + // Clock setting for synchronous mode + if ((mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) || + (mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) { + + // Only CPOL0 - CPHA1 combination available + + // USART clock polarity + if ((control & ARM_USART_CPOL_Msk) != ARM_USART_CPOL0) { + return ARM_USART_ERROR_CPOL; + } + + // USART clock phase + if ((control & ARM_USART_CPHA_Msk) != ARM_USART_CPHA1) { + return ARM_USART_ERROR_CPHA; + } + } + + // USART Baudrate + if (USART_SetBaudrate (arg, usart) == -1) { + return ARM_USART_ERROR_BAUDRATE; + } + + // Configuration is OK - Mode is valid + usart->info->mode = mode; + + // Configure RX pin and TX pin regarding mode and transmitter/receiver state + USART_PIN_Configure (usart); + + // Configure CLK pin regarding mode + if (usart->pins.clk) { + val = SCU_PIN_CFG_INPUT_FILTER_DIS; + switch (usart->info->mode) { + case ARM_USART_MODE_SMART_CARD: + case ARM_USART_MODE_SYNCHRONOUS_MASTER: + // Pin function = USART UCLK (output) + val |= SCU_PIN_CFG_MODE(usart->pins.clk->config_val); + break; + case ARM_USART_MODE_SYNCHRONOUS_SLAVE: + // Pin function = USART UCLK (input) + val |= SCU_PIN_CFG_INPUT_BUFFER_EN | + SCU_PIN_CFG_MODE(usart->pins.clk->config_val); + break; + default: + // Asynchronous, Single-wire and IrDA mode + // Pin function = GPIO + val |= SCU_PIN_CFG_INPUT_BUFFER_EN | + SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0); + } + SCU_PinConfigure(usart->pins.clk->port, usart->pins.clk->num, val); + } + + // Configure SYNCCRTL register (only in synchronous mode) + if (usart->capabilities.synchronous_master || + usart->capabilities.synchronous_slave) { + usart->reg->SYNCCTRL = USART_SYNCCTRL_FES | + USART_SYNCCTRL_SSSDIS | + syncctrl; + } + + // Configure HDEN register (only in single wire mode) + if (usart->capabilities.single_wire) { + usart->reg->HDEN = hden; + } + + // Configure ICR register (only in IrDA mode) + if (usart->capabilities.irda) { + usart->reg->ICR = (usart->reg->ICR & ~USART_ICR_IRDAEN) | icr; + } + + // Configure SCICTRL register (only in Smart Card mode) + if (usart->capabilities.smart_card) { + usart->reg->SCICTRL = (usart->reg->SCICTRL & ~USART_SCICTRL_SCIEN) | + scictrl; + } + + // Configure MCR register (modem line for USART1) + if (usart->uart_reg) { + usart->uart_reg->MCR = ((usart->uart_reg->MCR & ~(UART_MCR_RTSEN | UART_MCR_RTSCTRL | + UART_MCR_CTSEN))) | mcr; + } + + // Configure Line control register + usart->reg->LCR = ((usart->reg->LCR & (USART_LCR_BC | USART_LCR_DLAB)) | lcr); + + // Set configured flag + usart->info->flags |= USART_FLAG_CONFIGURED; + + return ARM_DRIVER_OK; +} + +/** + \fn ARM_USART_STATUS USART_GetStatus (USART_RESOURCES *usart) + \brief Get USART status. + \param[in] usart Pointer to USART resources + \return USART status \ref ARM_USART_STATUS +*/ +static ARM_USART_STATUS USART_GetStatus (USART_RESOURCES *usart) { + ARM_USART_STATUS stat = { 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U }; + + if ((usart->info->flags & USART_FLAG_POWERED) != 0U) { + stat.tx_busy = (usart->reg->LSR & USART_LSR_TEMT ? (0U) : (1U)); + stat.rx_busy = usart->info->rx_status.rx_busy; + stat.tx_underflow = 0U; + stat.rx_overflow = usart->info->rx_status.rx_overflow; + stat.rx_break = usart->info->rx_status.rx_break; + stat.rx_framing_error = usart->info->rx_status.rx_framing_error; + stat.rx_parity_error = usart->info->rx_status.rx_parity_error; + } + + return stat; +} + +/** + \fn int32_t USART_SetModemControl (ARM_USART_MODEM_CONTROL control, + USART_RESOURCES *usart) + \brief Set USART Modem Control line state. + \param[in] control \ref ARM_USART_MODEM_CONTROL + \param[in] usart Pointer to USART resources + \return \ref execution_status +*/ +static int32_t USART_SetModemControl (ARM_USART_MODEM_CONTROL control, + USART_RESOURCES *usart) { + + if ((usart->info->flags & USART_FLAG_CONFIGURED) == 0U) { + // USART is not configured + return ARM_DRIVER_ERROR; + } + + // Only UART1 supports modem lines + if (usart->uart_reg == NULL) { return ARM_DRIVER_ERROR_UNSUPPORTED; } + + if (control == ARM_USART_RTS_CLEAR) { + if (usart->capabilities.rts) { usart->uart_reg->MCR &= ~UART_MCR_RTSCTRL; } + else { return ARM_DRIVER_ERROR_UNSUPPORTED; } + } + if (control == ARM_USART_RTS_SET) { + if (usart->capabilities.rts) { usart->uart_reg->MCR |= UART_MCR_RTSCTRL; } + else {return ARM_DRIVER_ERROR_UNSUPPORTED; } + } + if (control == ARM_USART_DTR_CLEAR) { + if (usart->capabilities.dtr) { usart->uart_reg->MCR &= ~UART_MCR_DTRCTRL; } + else { return ARM_DRIVER_ERROR_UNSUPPORTED; } + } + if (control == ARM_USART_DTR_SET) { + if (usart->capabilities.dtr) { usart->uart_reg->MCR |= UART_MCR_DTRCTRL; } + else { return ARM_DRIVER_ERROR_UNSUPPORTED; } + } + return ARM_DRIVER_OK; +} + +/** + \fn ARM_USART_MODEM_STATUS USART_GetModemStatus (USART_RESOURCES *usart) + \brief Get USART Modem Status lines state. + \param[in] usart Pointer to USART resources + \return modem status \ref ARM_USART_MODEM_STATUS +*/ +static ARM_USART_MODEM_STATUS USART_GetModemStatus (USART_RESOURCES *usart) { + ARM_USART_MODEM_STATUS modem_status = { 0U, 0U, 0U, 0U, 0U }; + uint32_t msr; + + if (usart->uart_reg && + (usart->info->flags & USART_FLAG_CONFIGURED)) { + + msr = usart->uart_reg->MSR; + + if (usart->capabilities.cts) { modem_status.cts = ((msr & UART_MSR_CTS) ? (0U) : (1U)); } + if (usart->capabilities.dsr) { modem_status.dsr = ((msr & UART_MSR_DSR) ? (0U) : (1U)); } + if (usart->capabilities.ri ) { modem_status.ri = ((msr & UART_MSR_RI ) ? (0U) : (1U)); } + if (usart->capabilities.dcd) { modem_status.dcd = ((msr & UART_MSR_DCD) ? (0U) : (1U)); } + } + + return modem_status; +} + +/** + \fn void USART_IRQHandler (UART_RESOURCES *usart) + \brief USART Interrupt handler. + \param[in] usart Pointer to USART resources +*/ +static void USART_IRQHandler (USART_RESOURCES *usart) { + uint32_t iir, event, val, i = 0U; + + event = 0U; + iir = usart->reg->IIR; + + if ((iir & USART_IIR_INTSTATUS) == 0U) { + + // Transmit holding register empty + if ((iir & USART_IIR_INTID_MSK) == USART_IIR_INTID_THRE) { + val = 16U; + while ((val --) && (usart->info->xfer.tx_num != 0U) && (usart->info->xfer.tx_num != usart->info->xfer.tx_cnt)) { + if (((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) || + (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) && + (usart->info->xfer.sync_mode == USART_SYNC_MODE_RX)) { + // Dummy write in synchronous receive only mode + usart->reg->THR = usart->info->xfer.tx_def_val; + } else { + // Write data to Tx FIFO + usart->reg->THR = usart->info->xfer.tx_buf[usart->info->xfer.tx_cnt]; + } + usart->info->xfer.tx_cnt++; + } + + // Check if all data was transmitted + if (usart->info->xfer.tx_num == usart->info->xfer.tx_cnt) { + // Disable THRE interrupt + usart->reg->IER &= ~USART_IER_THREIE; + + // Clear TX busy flag + usart->info->xfer.send_active = 0U; + + // Set send complete event + if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) || + (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) { + if ((usart->info->xfer.sync_mode == USART_SYNC_MODE_TX) && + ((usart->info->flags & USART_FLAG_RX_ENABLED) == 0U)) { + event |= ARM_USART_EVENT_SEND_COMPLETE; + } + } else { + event |= ARM_USART_EVENT_SEND_COMPLETE; + } + } + } + + // Receive line status + if ((iir & USART_IIR_INTID_MSK) == USART_IIR_INTID_RLS) { + event |= USART_RxLineIntHandler(usart); + } + + // Receive data available and Character time-out indicator interrupt + if (((iir & USART_IIR_INTID_MSK) == USART_IIR_INTID_RDA) || + ((iir & USART_IIR_INTID_MSK) == USART_IIR_INTID_CTI)) { + + switch (usart->trig_lvl) { + case USART_TRIG_LVL_1: i = 1U; break; + case USART_TRIG_LVL_4: i = 3U; break; + case USART_TRIG_LVL_8: i = 7U; break; + case USART_TRIG_LVL_14: i = 13U; break; + } + + // Get available data from RX FIFO + while ((usart->reg->LSR & USART_LSR_RDR) && (i--)) { + // Check RX line interrupt for errors + event |= USART_RxLineIntHandler (usart); + + if (((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) || + (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) && + (usart->info->xfer.sync_mode == USART_SYNC_MODE_TX)) { + // Dummy read in synchronous transmit only mode + usart->reg->RBR; + usart->info->xfer.rx_cnt++; + } else { + if (usart->info->xfer.rx_cnt < usart->info->xfer.rx_num) { + // Read data from RX FIFO into receive buffer + usart->info->xfer.rx_buf[usart->info->xfer.rx_cnt] = usart->reg->RBR & 0xFFU; + usart->info->xfer.rx_cnt++; + } else { + usart->reg->RBR; + event |= ARM_USART_EVENT_RX_OVERFLOW; + } + } + + // Check if requested amount of data is received + if (usart->info->xfer.rx_cnt == usart->info->xfer.rx_num) { + // Disable RDA interrupt + usart->reg->IER &= ~USART_IER_RBRIE; + + // Clear RX busy flag and set receive transfer complete event + usart->info->rx_status.rx_busy = 0U; + if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) || + (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) { + val = usart->info->xfer.sync_mode; + usart->info->xfer.sync_mode = 0U; + switch (val) { + case USART_SYNC_MODE_TX: + event |= ARM_USART_EVENT_SEND_COMPLETE; + break; + case USART_SYNC_MODE_RX: + event |= ARM_USART_EVENT_RECEIVE_COMPLETE; + break; + case USART_SYNC_MODE_TX_RX: + event |= ARM_USART_EVENT_TRANSFER_COMPLETE; + break; + default: break; + } + } else { + event |= ARM_USART_EVENT_RECEIVE_COMPLETE; + } + break; + } + } + } + + // Character time-out indicator + if ((iir & USART_IIR_INTID_MSK) == USART_IIR_INTID_CTI) { + if ((usart->info->mode != ARM_USART_MODE_SYNCHRONOUS_MASTER) && + (usart->info->mode != ARM_USART_MODE_SYNCHRONOUS_SLAVE )) { + // Signal RX Time-out event, if not all requested data received + if ((usart->info->xfer.rx_num != 0U) && + (usart->info->xfer.rx_cnt != usart->info->xfer.rx_num)) { + usart->reg->RBR; + event |= ARM_USART_EVENT_RX_TIMEOUT; + } + } + } + + // Modem interrupt (UART1 only) +#if (RTE_UART1) + if (usart->uart_reg) { + if ((iir & USART_IIR_INTID_MSK) == UART_IIR_INTID_MS) { + // Save modem status register + val = usart->uart_reg->MSR; + + // CTS state changed + if ((usart->capabilities.cts) && (val & UART_MSR_DCTS)) { + event |= ARM_USART_EVENT_CTS; + } + // DSR state changed + if ((usart->capabilities.dsr) && (val & UART_MSR_DDSR)) { + event |= ARM_USART_EVENT_DSR; + } + // Ring indicator + if ((usart->capabilities.ri) && (val & UART_MSR_TERI)) { + event |= ARM_USART_EVENT_RI; + } + // DCD state changed + if ((usart->capabilities.dcd) && (val & UART_MSR_DDCD)) { + event |= ARM_USART_EVENT_DCD; + } + } + } +#endif + } + if ((usart->info->cb_event != NULL) && (event != 0U)) { + usart->info->cb_event (event); + } +} + +#if (((RTE_USART0) && (RTE_USART0_DMA_TX_EN == 1)) || \ + ((RTE_UART1) && (RTE_UART1_DMA_TX_EN == 1)) || \ + ((RTE_USART2) && (RTE_USART2_DMA_TX_EN == 1)) || \ + ((RTE_USART3) && (RTE_USART3_DMA_TX_EN == 1))) +/** + \fn void USART_GPDMA_Tx_Event (uint32_t event, USART_RESOURCES *usart) + \brief UART Interrupt handler. + \param[in] usart Pointer to USART resources + \param[in] event GPDMA_EVENT_TERMINAL_COUNT_REQUEST / GPDMA_EVENT_ERROR +*/ +static void USART_GPDMA_Tx_Event (uint32_t event, USART_RESOURCES *usart) { + switch (event) { + case GPDMA_EVENT_TERMINAL_COUNT_REQUEST: + usart->info->xfer.tx_cnt = usart->info->xfer.tx_num; + // Clear TX busy flag + usart->info->xfer.send_active = 0U; + + // Set Send Complete event for asynchronous transfers + if ((usart->info->mode != ARM_USART_MODE_SYNCHRONOUS_MASTER) && + (usart->info->mode != ARM_USART_MODE_SYNCHRONOUS_SLAVE )) { + if (usart->info->cb_event) { + usart->info->cb_event (ARM_USART_EVENT_SEND_COMPLETE); + } + } + break; + case GPDMA_EVENT_ERROR: + default: + break; + } +} +#endif + +#if (((RTE_USART0) && (RTE_USART0_DMA_RX_EN == 1)) || \ + ((RTE_UART1) && (RTE_UART1_DMA_RX_EN == 1)) || \ + ((RTE_USART2) && (RTE_USART2_DMA_RX_EN == 1)) || \ + ((RTE_USART3) && (RTE_USART3_DMA_RX_EN == 1))) +/** + \fn void USART_GPDMA_Rx_Event (uint32_t event, USART_RESOURCES *usart) + \brief UART Interrupt handler. + \param[in] event GPDMA_EVENT_TERMINAL_COUNT_REQUEST / GPDMA_EVENT_ERROR + \param[in] usart Pointer to USART resources +*/ +static void USART_GPDMA_Rx_Event (uint32_t event, USART_RESOURCES *usart) { + uint32_t val, evt; + + evt = 0U; + + switch (event) { + case GPDMA_EVENT_TERMINAL_COUNT_REQUEST: + usart->info->xfer.rx_cnt = usart->info->xfer.rx_num; + usart->info->rx_status.rx_busy = 0U; + + if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) || + (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) { + val = usart->info->xfer.sync_mode; + usart->info->xfer.sync_mode = 0U; + switch (val) { + case USART_SYNC_MODE_TX: + evt |= ARM_USART_EVENT_SEND_COMPLETE; + break; + case USART_SYNC_MODE_RX: + evt |= ARM_USART_EVENT_RECEIVE_COMPLETE; + break; + case USART_SYNC_MODE_TX_RX: + evt |= ARM_USART_EVENT_TRANSFER_COMPLETE; + break; + default: break; + } + } else { + evt |= ARM_USART_EVENT_RECEIVE_COMPLETE; + } + if ((usart->info->cb_event != NULL) && (evt != 0U)) { + usart->info->cb_event (evt); + } + break; + case GPDMA_EVENT_ERROR: + default: + break; + } +} +#endif + + +#if (RTE_USART0) +// USART0 Driver Wrapper functions +static ARM_USART_CAPABILITIES USART0_GetCapabilities (void) { + return USART_GetCapabilities (&USART0_Resources); +} +static int32_t USART0_Initialize (ARM_USART_SignalEvent_t cb_event) { + return USART_Initialize (cb_event, &USART0_Resources); +} +static int32_t USART0_Uninitialize (void) { + return USART_Uninitialize(&USART0_Resources); +} +static int32_t USART0_PowerControl (ARM_POWER_STATE state) { + return USART_PowerControl (state, &USART0_Resources); +} +static int32_t USART0_Send (const void *data, uint32_t num) { + return USART_Send (data, num, &USART0_Resources); +} +static int32_t USART0_Receive (void *data, uint32_t num) { + return USART_Receive (data, num, &USART0_Resources); +} +static int32_t USART0_Transfer (const void *data_out, + void *data_in, + uint32_t num) { + return USART_Transfer (data_out, data_in, num, &USART0_Resources); +} +static uint32_t USART0_GetTxCount (void) { + return USART_GetTxCount (&USART0_Resources); +} +static uint32_t USART0_GetRxCount (void) { + return USART_GetRxCount (&USART0_Resources); +} +static int32_t USART0_Control (uint32_t control, uint32_t arg) { + return USART_Control (control, arg, &USART0_Resources); +} +static ARM_USART_STATUS USART0_GetStatus (void) { + return USART_GetStatus (&USART0_Resources); +} +static int32_t USART0_SetModemControl (ARM_USART_MODEM_CONTROL control) { + return USART_SetModemControl (control, &USART0_Resources); +} +static ARM_USART_MODEM_STATUS USART0_GetModemStatus (void) { + return USART_GetModemStatus (&USART0_Resources); +} +void MX_USART0_IRQHandler (void) { + USART_IRQHandler (&USART0_Resources); +} +#if (RTE_USART0_DMA_TX_EN == 1) +void USART0_GPDMA_Tx_Event (uint32_t event) { + USART_GPDMA_Tx_Event(event, &USART0_Resources); +} +#endif +#if (RTE_USART0_DMA_RX_EN == 1) +void USART0_GPDMA_Rx_Event (uint32_t event) { + USART_GPDMA_Rx_Event(event, &USART0_Resources); +} +#endif + +// USART0 Driver Control Block +ARM_DRIVER_USART Driver_USART0 = { + USARTx_GetVersion, + USART0_GetCapabilities, + USART0_Initialize, + USART0_Uninitialize, + USART0_PowerControl, + USART0_Send, + USART0_Receive, + USART0_Transfer, + USART0_GetTxCount, + USART0_GetRxCount, + USART0_Control, + USART0_GetStatus, + USART0_SetModemControl, + USART0_GetModemStatus +}; +#endif + +#if (RTE_UART1) +// USART1 Driver Wrapper functions +static ARM_USART_CAPABILITIES USART1_GetCapabilities (void) { + return USART_GetCapabilities (&USART1_Resources); +} +static int32_t USART1_Initialize (ARM_USART_SignalEvent_t cb_event) { + return USART_Initialize (cb_event, &USART1_Resources); +} +static int32_t USART1_Uninitialize (void) { + return USART_Uninitialize(&USART1_Resources); +} +static int32_t USART1_PowerControl (ARM_POWER_STATE state) { + return USART_PowerControl (state, &USART1_Resources); +} +static int32_t USART1_Send (const void *data, uint32_t num) { + return USART_Send (data, num, &USART1_Resources); +} +static int32_t USART1_Receive (void *data, uint32_t num) { + return USART_Receive (data, num, &USART1_Resources); +} +static int32_t USART1_Transfer (const void *data_out, + void *data_in, + uint32_t num) { + return USART_Transfer (data_out, data_in, num, &USART1_Resources); +} +static uint32_t USART1_GetTxCount (void) { + return USART_GetTxCount (&USART1_Resources); +} +static uint32_t USART1_GetRxCount (void) { + return USART_GetRxCount (&USART1_Resources); +} +static int32_t USART1_Control (uint32_t control, uint32_t arg) { + return USART_Control (control, arg, &USART1_Resources); +} +static ARM_USART_STATUS USART1_GetStatus (void) { + return USART_GetStatus (&USART1_Resources); +} +static int32_t USART1_SetModemControl (ARM_USART_MODEM_CONTROL control) { + return USART_SetModemControl (control, &USART1_Resources); +} +static ARM_USART_MODEM_STATUS USART1_GetModemStatus (void) { + return USART_GetModemStatus (&USART1_Resources); +} +void MX_UART1_IRQHandler (void) { + USART_IRQHandler (&USART1_Resources); +} +#if (RTE_UART1_DMA_TX_EN == 1) +void USART1_GPDMA_Tx_Event (uint32_t event) { + USART_GPDMA_Tx_Event(event, &USART1_Resources); +} +#endif +#if (RTE_UART1_DMA_RX_EN == 1) +void USART1_GPDMA_Rx_Event (uint32_t event) { + USART_GPDMA_Rx_Event(event, &USART1_Resources); +} +#endif + +// USART1 Driver Control Block +ARM_DRIVER_USART Driver_USART1 = { + USARTx_GetVersion, + USART1_GetCapabilities, + USART1_Initialize, + USART1_Uninitialize, + USART1_PowerControl, + USART1_Send, + USART1_Receive, + USART1_Transfer, + USART1_GetTxCount, + USART1_GetRxCount, + USART1_Control, + USART1_GetStatus, + USART1_SetModemControl, + USART1_GetModemStatus +}; +#endif + +#if (RTE_USART2) +// USART2 Driver Wrapper functions +static ARM_USART_CAPABILITIES USART2_GetCapabilities (void) { + return USART_GetCapabilities (&USART2_Resources); +} +static int32_t USART2_Initialize (ARM_USART_SignalEvent_t cb_event) { + return USART_Initialize (cb_event, &USART2_Resources); +} +static int32_t USART2_Uninitialize (void) { + return USART_Uninitialize(&USART2_Resources); +} +static int32_t USART2_PowerControl (ARM_POWER_STATE state) { + return USART_PowerControl (state, &USART2_Resources); +} +static int32_t USART2_Send (const void *data, uint32_t num) { + return USART_Send (data, num, &USART2_Resources); +} +static int32_t USART2_Receive (void *data, uint32_t num) { + return USART_Receive (data, num, &USART2_Resources); +} +static int32_t USART2_Transfer (const void *data_out, + void *data_in, + uint32_t num) { + return USART_Transfer (data_out, data_in, num, &USART2_Resources); +} +static uint32_t USART2_GetTxCount (void) { + return USART_GetTxCount (&USART2_Resources); +} +static uint32_t USART2_GetRxCount (void) { + return USART_GetRxCount (&USART2_Resources); +} +static int32_t USART2_Control (uint32_t control, uint32_t arg) { + return USART_Control (control, arg, &USART2_Resources); +} +static ARM_USART_STATUS USART2_GetStatus (void) { + return USART_GetStatus (&USART2_Resources); +} +static int32_t USART2_SetModemControl (ARM_USART_MODEM_CONTROL control) { + return USART_SetModemControl (control, &USART2_Resources); +} +static ARM_USART_MODEM_STATUS USART2_GetModemStatus (void) { + return USART_GetModemStatus (&USART2_Resources); +} +void MX_USART2_IRQHandler (void) { + USART_IRQHandler (&USART2_Resources); +} +#if (defined(CORE_M0SUB) || defined(CORE_M0)) +__weak void CAN1_IRQHandler (void) {} +void MX_USART2_OR_C_CAN1_IRQHandler (void) { + MX_USART2_IRQHandler(); + CAN1_IRQHandler(); +} +#endif +#if (RTE_USART2_DMA_TX_EN == 1) +void USART2_GPDMA_Tx_Event (uint32_t event) { + USART_GPDMA_Tx_Event(event, &USART2_Resources); +} +#endif +#if (RTE_USART2_DMA_RX_EN == 1) +void USART2_GPDMA_Rx_Event (uint32_t event) { + USART_GPDMA_Rx_Event(event, &USART2_Resources); +} +#endif + +// USART2 Driver Control Block +ARM_DRIVER_USART Driver_USART2 = { + USARTx_GetVersion, + USART2_GetCapabilities, + USART2_Initialize, + USART2_Uninitialize, + USART2_PowerControl, + USART2_Send, + USART2_Receive, + USART2_Transfer, + USART2_GetTxCount, + USART2_GetRxCount, + USART2_Control, + USART2_GetStatus, + USART2_SetModemControl, + USART2_GetModemStatus +}; +#endif + +#if (RTE_USART3) +// USART3 Driver Wrapper functions +static ARM_USART_CAPABILITIES USART3_GetCapabilities (void) { + return USART_GetCapabilities (&USART3_Resources); +} +static int32_t USART3_Initialize (ARM_USART_SignalEvent_t cb_event) { + return USART_Initialize (cb_event, &USART3_Resources); +} +static int32_t USART3_Uninitialize (void) { + return USART_Uninitialize(&USART3_Resources); +} +static int32_t USART3_PowerControl (ARM_POWER_STATE state) { + return USART_PowerControl (state, &USART3_Resources); +} +static int32_t USART3_Send (const void *data, uint32_t num) { + return USART_Send (data, num, &USART3_Resources); +} +static int32_t USART3_Receive (void *data, uint32_t num) { + return USART_Receive (data, num, &USART3_Resources); +} +static int32_t USART3_Transfer (const void *data_out, + void *data_in, + uint32_t num) { + return USART_Transfer (data_out, data_in, num, &USART3_Resources); +} +static uint32_t USART3_GetTxCount (void) { + return USART_GetTxCount (&USART3_Resources); +} +static uint32_t USART3_GetRxCount (void) { + return USART_GetRxCount (&USART3_Resources); +} +static int32_t USART3_Control (uint32_t control, uint32_t arg) { + return USART_Control (control, arg, &USART3_Resources); +} +static ARM_USART_STATUS USART3_GetStatus (void) { + return USART_GetStatus (&USART3_Resources); +} +static int32_t USART3_SetModemControl (ARM_USART_MODEM_CONTROL control) { + return USART_SetModemControl (control, &USART3_Resources); +} +static ARM_USART_MODEM_STATUS USART3_GetModemStatus (void) { + return USART_GetModemStatus (&USART3_Resources); +} +void MX_USART3_IRQHandler (void) { + USART_IRQHandler (&USART3_Resources); +} +#if (RTE_USART3_DMA_TX_EN == 1) +void USART3_GPDMA_Tx_Event (uint32_t event) { + USART_GPDMA_Tx_Event(event, &USART3_Resources); +} +#endif +#if (RTE_USART3_DMA_RX_EN == 1) +void USART3_GPDMA_Rx_Event (uint32_t event) { + USART_GPDMA_Rx_Event(event, &USART3_Resources); +} +#endif + +// USART3 Driver Control Block +ARM_DRIVER_USART Driver_USART3 = { + USARTx_GetVersion, + USART3_GetCapabilities, + USART3_Initialize, + USART3_Uninitialize, + USART3_PowerControl, + USART3_Send, + USART3_Receive, + USART3_Transfer, + USART3_GetTxCount, + USART3_GetRxCount, + USART3_Control, + USART3_GetStatus, + USART3_SetModemControl, + USART3_GetModemStatus +}; +#endif diff --git a/source/hic_hal/nxp/lpc4322/RTE_Driver/USART_LPC43xx.h b/source/hic_hal/nxp/lpc4322/RTE_Driver/USART_LPC43xx.h new file mode 100644 index 000000000..d5e12535c --- /dev/null +++ b/source/hic_hal/nxp/lpc4322/RTE_Driver/USART_LPC43xx.h @@ -0,0 +1,319 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2020 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 20. Januar 2020 + * $Revision: V2.8 + * + * Project: USART Driver Definitions for NXP LPC43xx + * -------------------------------------------------------------------------- */ + +#ifndef __USART_LPC43XX_H +#define __USART_LPC43XX_H + +#include "Driver_USART.h" + +#include "LPC43xx.h" +#include "SCU_LPC43xx.h" +#include "GPDMA_LPC43xx.h" + +#include "RTE_Device.h" +#include "RTE_Components.h" + +// Clock Control Unit register +#define CCU_CLK_CFG_RUN (1U << 0) +#define CCU_CLK_CFG_AUTO (1U << 1) +#define CCU_CLK_STAT_RUN (1U << 0) + +// USART register interface definitions +// USART Divisor Latch register LSB +#define USART_DLL_DLLSB_POS ( 0U) +#define USART_DLL_DLLSB_MSK (0xFFU << USART_DLL_DLLSB_POS) + +// USART Divisor Latch register MSB +#define USART_DLM_DLMSB_POS ( 0U) +#define USART_DLM_DLMSB_MSK (0xFFU << USART_DLM_DLMSB_POS) + +// USART Interrupt enable register +#define USART_IER_RBRIE (1U << 0) +#define USART_IER_THREIE (1U << 1) +#define USART_IER_RXIE (1U << 2) +#define UART_IER_MSIE (1U << 3) // Only for UART1 - modem status interrupt enable +#define USART_IER_ABEOINTEN (1U << 8) +#define USART_IER_ABTOINTEN (1U << 9) + +// USART Interrupt identification register +#define USART_IIR_INTSTATUS (1U << 0) +#define USART_IIR_INTID_POS ( 1U) +#define USART_IIR_INTID_MSK (7U << USART_IIR_INTID_POS) +#define USART_IIR_FIFOENABLE_POS ( 6U) +#define USART_IIR_FIFOENABLE_MSK (3U << USART_IIR_FIFOENABLE_POS) +#define USART_IIR_ABEOINT (1U << 8) +#define USART_IIR_ABTOINT (1U << 9) + +#define USART_IIR_INTID_RLS (3U << USART_IIR_INTID_POS) +#define USART_IIR_INTID_RDA (2U << USART_IIR_INTID_POS) +#define USART_IIR_INTID_CTI (6U << USART_IIR_INTID_POS) +#define USART_IIR_INTID_THRE (1U << USART_IIR_INTID_POS) +#define UART_IIR_INTID_MS (0U << USART_IIR_INTID_POS) // UART1 only + +// USART FIFO control register +#define USART_FCR_FIFOEN (1U << 0) +#define USART_FCR_RXFIFORES (1U << 1) +#define USART_FCR_TXFIFORES (1U << 2) +#define USART_FCR_DMAMODE (1U << 3) +#define USART_FCR_RXTRIGLVL_POS ( 6U) +#define USART_FCR_RXTRIGLVL_MSK (3U << USART_FCR_RXTRIGLVL_POS) + +// USART Line control register +#define USART_LCR_WLS_POS ( 0U) +#define USART_LCR_WLS_MSK (3U << USART_LCR_WLS_POS) +#define USART_LCR_SBS (1U << 2) +#define USART_LCR_PE (1U << 3) +#define USART_LCR_PS_POS ( 4U) +#define USART_LCR_PS_MSK (3U << USART_LCR_PS_POS) +#define USART_LCR_BC (1U << 6) +#define USART_LCR_DLAB (1U << 7) + +// USART Line status register +#define USART_LSR_RDR (1U << 0) +#define USART_LSR_OE (1U << 1) +#define USART_LSR_PE (1U << 2) +#define USART_LSR_FE (1U << 3) +#define USART_LSR_BI (1U << 4) +#define USART_LSR_THRE (1U << 5) +#define USART_LSR_TEMT (1U << 6) +#define USART_LSR_RXFE (1U << 7) +#define USART_LSR_TXERR (1U << 8) + +#define USART_LSR_LINE_INT (USART_LSR_OE | USART_LSR_PE | USART_LSR_FE | USART_LSR_BI) + +// USART IrDA control register +#define USART_ICR_IRDAEN (1U << 0) +#define USART_ICR_FIXPULSEEN (1U << 1) +#define USART_ICR_IRDAINV (1U << 2) +#define USART_ICR_PULSEDIV_POS ( 3U) +#define USART_ICR_PULSEDIV_MSK (7U << USART_ICR_PULSEDIV_POS) + + +// USART Fractional divider register +#define USART_FDR_DIVADDVAL_POS ( 0U) +#define USART_FDR_DIVADDVAL_MSK (0x0FU << USART_FDR_DIVADDVAL_POS) +#define USART_FDR_MULVAL_POS ( 4U) +#define USART_FDR_MULVAL_MSK (0x0FU << USART_FDR_MULVAL_POS) + +// USART oversampling register +#define USART_OSR_OSFRAC_POS ( 1U) +#define USART_OSR_OSFRAC_MSK (7U << USART_OSR_OSFRAC_POS) +#define USART_OSR_OSINT_POS ( 4U) +#define USART_OSR_OSINT_MSK (0x0FU << USART_OSR_OSINT_POS) +#define USART_OSR_FDINT_POS ( 8U) +#define USART_OSR_FDINT_MSK (0x7FU << USART_OSR_FDINT_MSK) + +// USART Half duplex enable register +#define USART_HDEN_HDEN (1U << 0U) + +// USART SmartCard interface control register +#define USART_SCICTRL_SCIEN (1U << 0) +#define USART_SCICTRL_NACKDIS (1U << 1) +#define USART_SCICTRL_PROTSEL (1U << 2) +#define USART_SCICTRL_TXRETRY_POS ( 5U) +#define USART_SCICTRL_TXRETRY_MSK (7U << USART_SCICTRL_TXRETRY_POS) +#define USART_SCICTRL_GUARDTIME_POS ( 8U) +#define USART_SCICTRL_GUARDTIME_MSK (0xFFU << USART_SCICTRL_GUARDTIME_POS) + +// USART Synchronous mode control register +#define USART_SYNCCTRL_SYNC (1U << 0) +#define USART_SYNCCTRL_CSRC (1U << 1) +#define USART_SYNCCTRL_FES (1U << 2) +#define USART_SYNCCTRL_TSBYPASS (1U << 3) +#define USART_SYNCCTRL_CSCEN (1U << 4) +#define USART_SYNCCTRL_SSSDIS (1U << 5) +#define USART_SYNCCTRL_CCCLR (1U << 6) + +// UART Modem control register +#define UART_MCR_DTRCTRL (1U << 0) +#define UART_MCR_RTSCTRL (1U << 1) +#define UART_MCR_LMS (1U << 4) +#define UART_MCR_RTSEN (1U << 6) +#define UART_MCR_CTSEN (1U << 7) + +// UART Modem status register +#define UART_MSR_DCTS (1U << 0) +#define UART_MSR_DDSR (1U << 1) +#define UART_MSR_TERI (1U << 2) +#define UART_MSR_DDCD (1U << 3) +#define UART_MSR_CTS (1U << 4) +#define UART_MSR_DSR (1U << 5) +#define UART_MSR_RI (1U << 6) +#define UART_MSR_DCD (1U << 7) + +// USART RS485 control register +#define USART_RS485CTRL_NMMEN (1U << 0) +#define USART_RS485CTRL_RXDIS (1U << 1) +#define USART_RS485CTRL_AADEN (1U << 2) +#define USART_RS485CTRL_DCTRL (1U << 4) +#define USART_RS485CTRL_OINV (1U << 5) + +// USART Transmitter enable register +#define USART_TER_TXEN (1U << 0) + + +// USART flags +#define USART_FLAG_INITIALIZED (1U << 0) +#define USART_FLAG_POWERED (1U << 1) +#define USART_FLAG_CONFIGURED (1U << 2) +#define USART_FLAG_TX_ENABLED (1U << 3) +#define USART_FLAG_RX_ENABLED (1U << 4) + +// USART synchronous xfer modes +#define USART_SYNC_MODE_TX ( 1U ) +#define USART_SYNC_MODE_RX ( 2U ) +#define USART_SYNC_MODE_TX_RX (USART_SYNC_MODE_TX | \ + USART_SYNC_MODE_RX) + + +#define FRACT_BITS ( 12U ) +#define FRACT_MASK (0XFFFU) + +#define FIXED_OVERSAMPLING_DIVIDER_LIMIT (51U << FRACT_BITS) +#define INTEGER_OVERSAMPLING_DIVIDER_LIMIT ((12U << FRACT_BITS) + (8 << FRACT_BITS) / 10) + +// Baudrate accepted error +#define USART_MAX_BAUDRATE_ERROR ( 3U ) +#define USART_MAX_DIVIDER_ERROR ( 3U ) + +// USART TX FIFO trigger level +#define USART_TRIG_LVL_1 (0x00U) +#define USART_TRIG_LVL_4 (0x40U) +#define USART_TRIG_LVL_8 (0x80U) +#define USART_TRIG_LVL_14 (0xC0U) + +#define FRACT_DIV(add, mul) { ((uint16_t)((1U << 12) + (((uint32_t)(add << 24) / (mul)) >> 12))), ((uint8_t) (((mul) << 4) | add)), 0U,} + +typedef struct { + uint16_t val; + uint8_t add_mul; + uint8_t reserved; +} FRACT_DIVIDER; + +// USART Transfer Information (Run-Time) +typedef struct { + uint32_t rx_num; // Total number of data to be received + uint32_t tx_num; // Total number of data to be send + uint8_t *rx_buf; // Pointer to in data buffer + uint8_t *tx_buf; // Pointer to out data buffer + uint32_t rx_cnt; // Number of data received + uint32_t tx_cnt; // Number of data sent + uint8_t tx_def_val; // Transmit default value (used in USART_SYNC_MASTER_MODE_RX) + uint8_t rx_dump_val; // Receive dump value (used in USART_SYNC_MASTER_MODE_TX) + uint8_t send_active; // Send active flag + uint8_t sync_mode; // Synchronous mode + uint8_t tx_fifo_level; // Number of items in transmit FIFO + uint8_t reserved[3]; +} USART_TRANSFER_INFO; + +typedef struct { + uint8_t rx_busy; // Receiver busy flag + uint8_t rx_overflow; // Receive data overflow detected (cleared on start of next receive operation) + uint8_t rx_break; // Break detected on receive (cleared on start of next receive operation) + uint8_t rx_framing_error; // Framing error detected on receive (cleared on start of next receive operation) + uint8_t rx_parity_error; // Parity error detected on receive (cleared on start of next receive operation) + uint8_t reserved[3]; +} USART_RX_STATUS; + +// USART Information (Run-Time) +typedef struct { + ARM_USART_SignalEvent_t cb_event; // Event callback + USART_RX_STATUS rx_status; // Receive status flags + USART_TRANSFER_INFO xfer; // Transfer information + uint32_t baudrate; // Baudrate + uint8_t mode; // USART mode + uint8_t flags; // USART driver flags + uint8_t reserved[2]; +} USART_INFO; + +// USART DMA +typedef const struct { + uint8_t channel; // DMA Channel + uint8_t peripheral; // DMA mux + uint8_t peripheral_sel;// DMA mux selection + uint8_t reserved; + GPDMA_SignalEvent_t cb_event; // DMA Event callback +} USART_DMA; + +// USART Pin Configuration +typedef const struct { + const PIN_ID *tx; // TX Pin identifier + const PIN_ID *rx; // RX Pin identifier + const PIN_ID *clk; // CLK Pin identifier + const PIN_ID *cts; // CTS Pin identifier + const PIN_ID *rts; // RTS Pin identifier + const PIN_ID *dcd; // DCD Pin identifier + const PIN_ID *dsr; // DSR Pin identifier + const PIN_ID *dtr; // DTR Pin identifier + const PIN_ID *ri; // RI Pin identifier +} USART_PINS; + +// USART Clocks Configuration +typedef const struct { + __IO uint32_t *reg_cfg; // USART register interface clock configuration register + __I uint32_t *reg_stat; // USART register interface clock status register + __IO uint32_t *peri_cfg; // USART peripheral clock configuration register + __I uint32_t *peri_stat; // USART peripheral clock status register + __IO uint32_t *base_clk; // USART base clock +} USART_CLOCKS; + +// USART Reset Configuration +typedef const struct { + uint32_t reg_cfg_val; // USART reset bit + __IO uint32_t *reg_cfg; // USART reset control register + __I uint32_t *reg_stat; // USART reset active status register +} USART_RESET; + +// USART Resources definitions +typedef const struct { + ARM_USART_CAPABILITIES capabilities; // Capabilities + LPC_USARTn_Type *reg; // Pointer to USART peripheral + LPC_UART1_Type *uart_reg; // Pointer to UART peripheral + USART_PINS pins; // USART pins configuration + USART_CLOCKS clk; // USART clocks configuration + USART_RESET rst; // USART reset configuration + int32_t irq_num; // USART IRQ Number + uint32_t trig_lvl; // FIFO Trigger level + USART_DMA *dma_tx; + USART_DMA *dma_rx; + USART_INFO *info; // Run-Time Information + uint16_t sc_oversamp; // SmartCard oversampling ratio + uint8_t reserved[2]; // Reserved +} USART_RESOURCES; + +// Global functions and variables exported by driver .c module */ +#if (RTE_USART0) +extern ARM_DRIVER_USART Driver_USART0; +#endif +#if (RTE_UART1) +extern ARM_DRIVER_USART Driver_USART1; +#endif +#if (RTE_USART2) +extern ARM_DRIVER_USART Driver_USART2; +#endif +#if (RTE_USART3) +extern ARM_DRIVER_USART Driver_USART3; +#endif + +#endif /* __USART_LPC43XX_H */ From 810aa40375a04ba245d08dd11496a49bbb36696c Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 10 Nov 2021 00:25:06 -0600 Subject: [PATCH 522/617] lpc4322 (SWO): import default RTE_Device.h --- source/hic_hal/nxp/lpc4322/RTE_Device.h | 2483 +++++++++++++++++++++++ 1 file changed, 2483 insertions(+) create mode 100644 source/hic_hal/nxp/lpc4322/RTE_Device.h diff --git a/source/hic_hal/nxp/lpc4322/RTE_Device.h b/source/hic_hal/nxp/lpc4322/RTE_Device.h new file mode 100644 index 000000000..e3593c246 --- /dev/null +++ b/source/hic_hal/nxp/lpc4322/RTE_Device.h @@ -0,0 +1,2483 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 25. April 2016 + * $Revision: V2.2.1 + * + * Project: RTE Device Configuration for NXP LPC43xx + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +// USB0 Controller [Driver_USBD0 and Driver_USBH0] +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host +#define RTE_USB_USB0 0 + +// Pin Configuration +// USB0_PPWR (Host) <0=>Not used <1=>P1_7 <2=>P2_0 <3=>P2_3 <4=>P6_3 +// VBUS drive signal (towards external charge pump or power management unit). +#define RTE_USB0_PPWR_ID 1 +#if (RTE_USB0_PPWR_ID == 0) + #define RTE_USB0_PPWR_PIN_EN 0 +#elif (RTE_USB0_PPWR_ID == 1) + #define RTE_USB0_PPWR_PORT 1 + #define RTE_USB0_PPWR_BIT 7 + #define RTE_USB0_PPWR_FUNC 4 +#elif (RTE_USB0_PPWR_ID == 2) + #define RTE_USB0_PPWR_PORT 2 + #define RTE_USB0_PPWR_BIT 0 + #define RTE_USB0_PPWR_FUNC 3 +#elif (RTE_USB0_PPWR_ID == 3) + #define RTE_USB0_PPWR_PORT 2 + #define RTE_USB0_PPWR_BIT 3 + #define RTE_USB0_PPWR_FUNC 7 +#elif (RTE_USB0_PPWR_ID == 4) + #define RTE_USB0_PPWR_PORT 6 + #define RTE_USB0_PPWR_BIT 3 + #define RTE_USB0_PPWR_FUNC 1 +#else + #error "Invalid RTE_USB0_PPWR Pin Configuration!" +#endif +#ifndef RTE_USB0_PPWR_PIN_EN + #define RTE_USB0_PPWR_PIN_EN 1 +#endif +// USB0_PWR_FAULT (Host) <0=>Not used <1=>P1_5 <2=>P2_1 <3=>P2_4 <4=>P6_6 <5=>P8_0 +// Port power fault signal indicating overcurrent condition. +// This signal monitors over-current on the USB bus +// (external circuitry required to detect over-current condition). +#define RTE_USB0_PWR_FAULT_ID 1 +#if (RTE_USB0_PWR_FAULT_ID == 0) + #define RTE_USB0_PWR_FAULT_PIN_EN 0 +#elif (RTE_USB0_PWR_FAULT_ID == 1) + #define RTE_USB0_PWR_FAULT_PORT 1 + #define RTE_USB0_PWR_FAULT_BIT 5 + #define RTE_USB0_PWR_FAULT_FUNC 4 +#elif (RTE_USB0_PWR_FAULT_ID == 2) + #define RTE_USB0_PWR_FAULT_PORT 2 + #define RTE_USB0_PWR_FAULT_BIT 1 + #define RTE_USB0_PWR_FAULT_FUNC 3 +#elif (RTE_USB0_PWR_FAULT_ID == 3) + #define RTE_USB0_PWR_FAULT_PORT 2 + #define RTE_USB0_PWR_FAULT_BIT 4 + #define RTE_USB0_PWR_FAULT_FUNC 7 +#elif (RTE_USB0_PWR_FAULT_ID == 4) + #define RTE_USB0_PWR_FAULT_PORT 6 + #define RTE_USB0_PWR_FAULT_BIT 6 + #define RTE_USB0_PWR_FAULT_FUNC 3 +#elif (RTE_USB0_PWR_FAULT_ID == 5) + #define RTE_USB0_PWR_FAULT_PORT 8 + #define RTE_USB0_PWR_FAULT_BIT 0 + #define RTE_USB0_PWR_FAULT_FUNC 1 +#else + #error "Invalid RTE_USB0_PWR_FAULT Pin Configuration!" +#endif +#ifndef RTE_USB0_PWR_FAULT_PIN_EN + #define RTE_USB0_PWR_FAULT_PIN_EN 1 +#endif +// USB0_IND0 <0=>Not used <1=>P1_4 <2=>P2_5 <3=>P2_6 <4=>P6_8 <5=>P8_2 +// USB0 port indicator LED control output 0 +#define RTE_USB0_IND0_ID 1 +#if (RTE_USB0_IND0_ID == 0) + #define RTE_USB0_IND0_PIN_EN 0 +#elif (RTE_USB0_IND0_ID == 1) + #define RTE_USB0_IND0_PORT 1 + #define RTE_USB0_IND0_BIT 4 + #define RTE_USB0_IND0_FUNC 4 +#elif (RTE_USB0_IND0_ID == 2) + #define RTE_USB0_IND0_PORT 2 + #define RTE_USB0_IND0_BIT 5 + #define RTE_USB0_IND0_FUNC 7 +#elif (RTE_USB0_IND0_ID == 3) + #define RTE_USB0_IND0_PORT 2 + #define RTE_USB0_IND0_BIT 6 + #define RTE_USB0_IND0_FUNC 3 +#elif (RTE_USB0_IND0_ID == 4) + #define RTE_USB0_IND0_PORT 6 + #define RTE_USB0_IND0_BIT 8 + #define RTE_USB0_IND0_FUNC 3 +#elif (RTE_USB0_IND0_ID == 5) + #define RTE_USB0_IND0_PORT 8 + #define RTE_USB0_IND0_BIT 2 + #define RTE_USB0_IND0_FUNC 1 +#else + #error "Invalid RTE_USB0_IND0 Pin Configuration!" +#endif +#ifndef RTE_USB0_IND0_PIN_EN + #define RTE_USB0_IND0_PIN_EN 1 +#endif +// USB0_IND1 <0=>Not used <1=>P1_3 <2=>P2_2 <3=>P6_7 <4=>P8_1 +// USB0 port indicator LED control output 1 +#define RTE_USB0_IND1_ID 1 +#if (RTE_USB0_IND1_ID == 0) + #define RTE_USB0_IND1_PIN_EN 0 +#elif (RTE_USB0_IND1_ID == 1) + #define RTE_USB0_IND1_PORT 1 + #define RTE_USB0_IND1_BIT 3 + #define RTE_USB0_IND1_FUNC 4 +#elif (RTE_USB0_IND1_ID == 2) + #define RTE_USB0_IND1_PORT 2 + #define RTE_USB0_IND1_BIT 2 + #define RTE_USB0_IND1_FUNC 3 +#elif (RTE_USB0_IND1_ID == 3) + #define RTE_USB0_IND1_PORT 6 + #define RTE_USB0_IND1_BIT 7 + #define RTE_USB0_IND1_FUNC 3 +#elif (RTE_USB0_IND1_ID == 4) + #define RTE_USB0_IND1_PORT 8 + #define RTE_USB0_IND1_BIT 1 + #define RTE_USB0_IND1_FUNC 1 +#else + #error "Invalid RTE_USB0_IND1 Pin Configuration!" +#endif +#ifndef RTE_USB0_IND1_PIN_EN + #define RTE_USB0_IND1_PIN_EN 1 +#endif +// Pin Configuration + +// Device [Driver_USBD0] +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +// High-speed +// Enable high-speed functionality +#define RTE_USB_USB0_HS_EN 0 +// Device [Driver_USBD0] +// USB0 Controller [Driver_USBD0 and Driver_USBH0] + +// USB1 Controller [Driver_USBD1 and Driver_USBH1] +// Configuration settings for Driver_USBD1 in component ::Drivers:USB Device +// Configuration settings for Driver_USBH1 in component ::Drivers:USB Host +#define RTE_USB_USB1 0 + +// Pin Configuration +// USB1_PPWR (Host) <0=>Not used <1=>P9_5 +// VBUS drive signal (towards external charge pump or power management unit). +#define RTE_USB1_PPWR_ID 1 +#if (RTE_USB1_PPWR_ID == 0) + #define RTE_USB1_PPWR_PIN_EN 0 +#elif (RTE_USB1_PPWR_ID == 1) + #define RTE_USB1_PPWR_PORT 9 + #define RTE_USB1_PPWR_BIT 5 + #define RTE_USB1_PPWR_FUNC 2 +#else + #error "Invalid RTE_USB1_PPWR Pin Configuration!" +#endif +#ifndef RTE_USB1_PPWR_PIN_EN + #define RTE_USB1_PPWR_PIN_EN 1 +#endif +// USB1_PWR_FAULT (Host) <0=>Not used <1=>P9_6 +// Port power fault signal indicating overcurrent condition. +// This signal monitors over-current on the USB bus +// (external circuitry required to detect over-current condition). +#define RTE_USB1_PWR_FAULT_ID 1 +#if (RTE_USB1_PWR_FAULT_ID == 0) + #define RTE_USB1_PWR_FAULT_PIN_EN 0 +#elif (RTE_USB1_PWR_FAULT_ID == 1) + #define RTE_USB1_PWR_FAULT_PORT 9 + #define RTE_USB1_PWR_FAULT_BIT 6 + #define RTE_USB1_PWR_FAULT_FUNC 2 +#else + #error "Invalid RTE_USB1_PWR_FAULT Pin Configuration!" +#endif +#ifndef RTE_USB1_PWR_FAULT_PIN_EN + #define RTE_USB1_PWR_FAULT_PIN_EN 1 +#endif +// USB1_IND0 <0=>Not used <1=>P3_2 <2=>P9_4 +// USB1 port indicator LED control output 0 +#define RTE_USB1_IND0_ID 1 +#if (RTE_USB1_IND0_ID == 0) + #define RTE_USB1_IND0_PIN_EN 0 +#elif (RTE_USB1_IND0_ID == 1) + #define RTE_USB1_IND0_PORT 3 + #define RTE_USB1_IND0_BIT 2 + #define RTE_USB1_IND0_FUNC 3 +#elif (RTE_USB1_IND0_ID == 2) + #define RTE_USB1_IND0_PORT 9 + #define RTE_USB1_IND0_BIT 4 + #define RTE_USB1_IND0_FUNC 2 +#else + #error "Invalid RTE_USB1_IND0 Pin Configuration!" +#endif +#ifndef RTE_USB1_IND0_PIN_EN + #define RTE_USB1_IND0_PIN_EN 1 +#endif +// USB1_IND1 <0=>Not used <1=>P3_1 <2=>P9_3 +// USB1 port indicator LED control output 1 +#define RTE_USB1_IND1_ID 1 +#if (RTE_USB1_IND1_ID == 0) + #define RTE_USB1_IND1_PIN_EN 0 +#elif (RTE_USB1_IND1_ID == 1) + #define RTE_USB1_IND1_PORT 3 + #define RTE_USB1_IND1_BIT 1 + #define RTE_USB1_IND1_FUNC 3 +#elif (RTE_USB1_IND1_ID == 2) + #define RTE_USB1_IND1_PORT 9 + #define RTE_USB1_IND1_BIT 3 + #define RTE_USB1_IND1_FUNC 2 +#else + #error "Invalid RTE_USB1_IND1 Pin Configuration!" +#endif +#ifndef RTE_USB1_IND1_PIN_EN + #define RTE_USB1_IND1_PIN_EN 1 +#endif + +// On-chip full-speed PHY +#define RTE_USB_USB1_FS_PHY_EN 1 + +// USB1_VBUS (Device) <0=>Not used <1=>P2_5 +// Monitors the presence of USB1 bus power. +#define RTE_USB1_VBUS_ID 1 +#if (RTE_USB1_VBUS_ID == 0) + #define RTE_USB1_VBUS_PIN_EN 0 +#elif (RTE_USB1_VBUS_ID == 1) + #define RTE_USB1_VBUS_PORT 2 + #define RTE_USB1_VBUS_BIT 5 + #define RTE_USB1_VBUS_FUNC 2 +#else + #error "Invalid RTE_USB1_VBUS Pin Configuration!" +#endif +#ifndef RTE_USB1_VBUS_PIN_EN + #define RTE_USB1_VBUS_PIN_EN 1 +#endif +// On-chip full-speed PHY + +// External high-speed ULPI PHY (UTMI+ Low Pin Interface) +#define RTE_USB_USB1_HS_PHY_EN 0 + +// USB1_ULPI_CLK <0=>P8_8 <1=>PC_0 +// USB1 ULPI link CLK signal. +// 60 MHz clock generated by the PHY. +#define RTE_USB1_ULPI_CLK_ID 0 +#if (RTE_USB1_ULPI_CLK_ID == 0) + #define RTE_USB1_ULPI_CLK_PORT 8 + #define RTE_USB1_ULPI_CLK_BIT 8 + #define RTE_USB1_ULPI_CLK_FUNC 1 +#elif (RTE_USB1_ULPI_CLK_ID == 1) + #define RTE_USB1_ULPI_CLK_PORT 0xC + #define RTE_USB1_ULPI_CLK_BIT 0 + #define RTE_USB1_ULPI_CLK_FUNC 1 +#else + #error "Invalid RTE_USB1_ULPI_CLK Pin Configuration!" +#endif +// USB1_ULPI_DIR <0=>PB_1 <1=>PC_11 +// USB1 ULPI link DIR signal. +// Controls the ULPI data line direction. +#define RTE_USB1_ULPI_DIR_ID 0 +#if (RTE_USB1_ULPI_DIR_ID == 0) + #define RTE_USB1_ULPI_DIR_PORT 0xB + #define RTE_USB1_ULPI_DIR_BIT 1 + #define RTE_USB1_ULPI_DIR_FUNC 1 +#elif (RTE_USB1_ULPI_DIR_ID == 1) + #define RTE_USB1_ULPI_DIR_PORT 0xC + #define RTE_USB1_ULPI_DIR_BIT 11 + #define RTE_USB1_ULPI_DIR_FUNC 1 +#else + #error "Invalid RTE_USB1_ULPI_DIR Pin Configuration!" +#endif +// USB1_ULPI_STP <0=>P8_7 <1=>PC_10 +// USB1 ULPI link STP signal. +// Asserted to end or interrupt transfers to the PHY. +#define RTE_USB1_ULPI_STP_ID 0 +#if (RTE_USB1_ULPI_STP_ID == 0) + #define RTE_USB1_ULPI_STP_PORT 8 + #define RTE_USB1_ULPI_STP_BIT 7 + #define RTE_USB1_ULPI_STP_FUNC 1 +#elif (RTE_USB1_ULPI_STP_ID == 1) + #define RTE_USB1_ULPI_STP_PORT 0xC + #define RTE_USB1_ULPI_STP_BIT 10 + #define RTE_USB1_ULPI_STP_FUNC 1 +#else + #error "Invalid RTE_USB1_ULPI_STP Pin Configuration!" +#endif +// USB1_ULPI_NXT <0=>P8_6 <1=>PC_9 +// USB1 ULPI link NXT signal. +// Data flow control signal from the PHY. +#define RTE_USB1_ULPI_NXT_ID 0 +#if (RTE_USB1_ULPI_NXT_ID == 0) + #define RTE_USB1_ULPI_NXT_PORT 8 + #define RTE_USB1_ULPI_NXT_BIT 6 + #define RTE_USB1_ULPI_NXT_FUNC 1 +#elif (RTE_USB1_ULPI_NXT_ID == 1) + #define RTE_USB1_ULPI_NXT_PORT 0xC + #define RTE_USB1_ULPI_NXT_BIT 9 + #define RTE_USB1_ULPI_NXT_FUNC 1 +#else + #error "Invalid RTE_USB1_ULPI_NXT Pin Configuration!" +#endif +// USB1_ULPI_D0 <0=>P8_5 <1=>PC_8 <2=>PD_11 +// USB1 ULPI link bidirectional data line 0. +#define RTE_USB1_ULPI_D0_ID 0 +#if (RTE_USB1_ULPI_D0_ID == 0) + #define RTE_USB1_ULPI_D0_PORT 8 + #define RTE_USB1_ULPI_D0_BIT 5 + #define RTE_USB1_ULPI_D0_FUNC 1 +#elif (RTE_USB1_ULPI_D0_ID == 1) + #define RTE_USB1_ULPI_D0_PORT 0xC + #define RTE_USB1_ULPI_D0_BIT 8 + #define RTE_USB1_ULPI_D0_FUNC 1 +#elif (RTE_USB1_ULPI_D0_ID == 2) + #define RTE_USB1_ULPI_D0_PORT 0xD + #define RTE_USB1_ULPI_D0_BIT 11 + #define RTE_USB1_ULPI_D0_FUNC 5 +#else + #error "Invalid RTE_USB1_ULPI_D0 Pin Configuration!" +#endif +// USB1_ULPI_D1 <0=>P8_4 <1=>PC_7 +// USB1 ULPI link bidirectional data line 1. +#define RTE_USB1_ULPI_D1_ID 0 +#if (RTE_USB1_ULPI_D1_ID == 0) + #define RTE_USB1_ULPI_D1_PORT 8 + #define RTE_USB1_ULPI_D1_BIT 4 + #define RTE_USB1_ULPI_D1_FUNC 1 +#elif (RTE_USB1_ULPI_D1_ID == 1) + #define RTE_USB1_ULPI_D1_PORT 0xC + #define RTE_USB1_ULPI_D1_BIT 7 + #define RTE_USB1_ULPI_D1_FUNC 1 +#else + #error "Invalid RTE_USB1_ULPI_D1 Pin Configuration!" +#endif +// USB1_ULPI_D2 <0=>P8_3 <1=>PC_6 +// USB1 ULPI link bidirectional data line 2. +#define RTE_USB1_ULPI_D2_ID 0 +#if (RTE_USB1_ULPI_D2_ID == 0) + #define RTE_USB1_ULPI_D2_PORT 8 + #define RTE_USB1_ULPI_D2_BIT 3 + #define RTE_USB1_ULPI_D2_FUNC 1 +#elif (RTE_USB1_ULPI_D2_ID == 1) + #define RTE_USB1_ULPI_D2_PORT 0xC + #define RTE_USB1_ULPI_D2_BIT 6 + #define RTE_USB1_ULPI_D2_FUNC 1 +#else + #error "Invalid RTE_USB1_ULPI_D2 Pin Configuration!" +#endif +// USB1_ULPI_D3 <0=>PB_6 <1=>PC_5 +// USB1 ULPI link bidirectional data line 3. +#define RTE_USB1_ULPI_D3_ID 0 +#if (RTE_USB1_ULPI_D3_ID == 0) + #define RTE_USB1_ULPI_D3_PORT 0xB + #define RTE_USB1_ULPI_D3_BIT 6 + #define RTE_USB1_ULPI_D3_FUNC 1 +#elif (RTE_USB1_ULPI_D3_ID == 1) + #define RTE_USB1_ULPI_D3_PORT 0xC + #define RTE_USB1_ULPI_D3_BIT 5 + #define RTE_USB1_ULPI_D3_FUNC 1 +#else + #error "Invalid RTE_USB1_ULPI_D3 Pin Configuration!" +#endif +// USB1_ULPI_D4 <0=>PB_5 <1=>PC_4 +// USB1 ULPI link bidirectional data line 4. +#define RTE_USB1_ULPI_D4_ID 0 +#if (RTE_USB1_ULPI_D4_ID == 0) + #define RTE_USB1_ULPI_D4_PORT 0xB + #define RTE_USB1_ULPI_D4_BIT 5 + #define RTE_USB1_ULPI_D4_FUNC 1 +#elif (RTE_USB1_ULPI_D4_ID == 1) + #define RTE_USB1_ULPI_D4_PORT 0xC + #define RTE_USB1_ULPI_D4_BIT 4 + #define RTE_USB1_ULPI_D4_FUNC 1 +#else + #error "Invalid RTE_USB1_ULPI_D4 Pin Configuration!" +#endif +// USB1_ULPI_D5 <0=>PB_4 <1=>PC_3 +// USB1 ULPI link bidirectional data line 5. +#define RTE_USB1_ULPI_D5_ID 0 +#if (RTE_USB1_ULPI_D5_ID == 0) + #define RTE_USB1_ULPI_D5_PORT 0xB + #define RTE_USB1_ULPI_D5_BIT 4 + #define RTE_USB1_ULPI_D5_FUNC 1 +#elif (RTE_USB1_ULPI_D5_ID == 1) + #define RTE_USB1_ULPI_D5_PORT 0xC + #define RTE_USB1_ULPI_D5_BIT 3 + #define RTE_USB1_ULPI_D5_FUNC 0 +#else + #error "Invalid RTE_USB1_ULPI_D5 Pin Configuration!" +#endif +// USB1_ULPI_D6 <0=>PB_3 <1=>PC_2 +// USB1 ULPI link bidirectional data line 6. +#define RTE_USB1_ULPI_D6_ID 0 +#if (RTE_USB1_ULPI_D6_ID == 0) + #define RTE_USB1_ULPI_D6_PORT 0xB + #define RTE_USB1_ULPI_D6_BIT 3 + #define RTE_USB1_ULPI_D6_FUNC 1 +#elif (RTE_USB1_ULPI_D6_ID == 1) + #define RTE_USB1_ULPI_D6_PORT 0xC + #define RTE_USB1_ULPI_D6_BIT 2 + #define RTE_USB1_ULPI_D6_FUNC 0 +#else + #error "Invalid RTE_USB1_ULPI_D6 Pin Configuration!" +#endif +// USB1_ULPI_D7 <0=>PB_2 <1=>PC_1 +// USB1 ULPI link bidirectional data line 7. +#define RTE_USB1_ULPI_D7_ID 0 +#if (RTE_USB1_ULPI_D7_ID == 0) + #define RTE_USB1_ULPI_D7_PORT 0xB + #define RTE_USB1_ULPI_D7_BIT 2 + #define RTE_USB1_ULPI_D7_FUNC 1 +#elif (RTE_USB1_ULPI_D7_ID == 1) + #define RTE_USB1_ULPI_D7_PORT 0xC + #define RTE_USB1_ULPI_D7_BIT 1 + #define RTE_USB1_ULPI_D7_FUNC 0 +#else + #error "Invalid RTE_USB1_ULPI_D7 Pin Configuration!" +#endif +// External high-speed ULPI PHY (UTMI+ Low Pin Interface) +// Pin Configuration +// USB1 Controller [Driver_USBD1 and Driver_USBH1] + +// ENET (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC +#define RTE_ENET 0 + +// MII (Media Independent Interface) +#define RTE_ENET_MII 0 + +// ENET_TXD0 Pin <0=>P1_18 +#define RTE_ENET_MII_TXD0_PORT_ID 0 +#if (RTE_ENET_MII_TXD0_PORT_ID == 0) + #define RTE_ENET_MII_TXD0_PORT 1 + #define RTE_ENET_MII_TXD0_PIN 18 + #define RTE_ENET_MII_TXD0_FUNC 3 +#else + #error "Invalid ENET_TXD0 Pin Configuration!" +#endif +// ENET_TXD1 Pin <0=>P1_20 +#define RTE_ENET_MII_TXD1_PORT_ID 0 +#if (RTE_ENET_MII_TXD1_PORT_ID == 0) + #define RTE_ENET_MII_TXD1_PORT 1 + #define RTE_ENET_MII_TXD1_PIN 20 + #define RTE_ENET_MII_TXD1_FUNC 3 +#else + #error "Invalid ENET_TXD1 Pin Configuration!" +#endif +// ENET_TXD2 Pin <0=>P9_4 <1=>PC_2 +#define RTE_ENET_MII_TXD2_PORT_ID 0 +#if (RTE_ENET_MII_TXD2_PORT_ID == 0) + #define RTE_ENET_MII_TXD2_PORT 9 + #define RTE_ENET_MII_TXD2_PIN 4 + #define RTE_ENET_MII_TXD2_FUNC 5 +#elif (RTE_ENET_MII_TXD2_PORT_ID == 1) + #define RTE_ENET_MII_TXD2_PORT 0xC + #define RTE_ENET_MII_TXD2_PIN 2 + #define RTE_ENET_MII_TXD2_FUNC 3 +#else + #error "Invalid ENET_TXD2 Pin Configuration!" +#endif +// ENET_TXD3 Pin <0=>P9_5 <1=>PC_3 +#define RTE_ENET_MII_TXD3_PORT_ID 0 +#if (RTE_ENET_MII_TXD3_PORT_ID == 0) + #define RTE_ENET_MII_TXD3_PORT 9 + #define RTE_ENET_MII_TXD3_PIN 5 + #define RTE_ENET_MII_TXD3_FUNC 5 +#elif (RTE_ENET_MII_TXD3_PORT_ID == 1) + #define RTE_ENET_MII_TXD3_PORT 0xC + #define RTE_ENET_MII_TXD3_PIN 3 + #define RTE_ENET_MII_TXD3_FUNC 3 +#else + #error "Invalid ENET_TXD3 Pin Configuration!" +#endif +// ENET_TX_EN Pin <0=>P0_1 <1=>PC_4 +#define RTE_ENET_MII_TX_EN_PORT_ID 0 +#if (RTE_ENET_MII_TX_EN_PORT_ID == 0) + #define RTE_ENET_MII_TX_EN_PORT 0 + #define RTE_ENET_MII_TX_EN_PIN 1 + #define RTE_ENET_MII_TX_EN_FUNC 6 +#elif (RTE_ENET_MII_TX_EN_PORT_ID == 1) + #define RTE_ENET_MII_TX_EN_PORT 0xC + #define RTE_ENET_MII_TX_EN_PIN 4 + #define RTE_ENET_MII_TX_EN_FUNC 3 +#else + #error "Invalid ENET_TX_EN Pin Configuration!" +#endif +// ENET_TX_CLK Pin <0=>P1_19 <1=>CLK0 +#define RTE_ENET_MII_TX_CLK_PORT_ID 0 +#if (RTE_ENET_MII_TX_CLK_PORT_ID == 0) + #define RTE_ENET_MII_TX_CLK_PORT 1 + #define RTE_ENET_MII_TX_CLK_PIN 19 + #define RTE_ENET_MII_TX_CLK_FUNC 0 +#elif (RTE_ENET_MII_TX_CLK_PORT_ID == 1) + #define RTE_ENET_MII_TX_CLK_PORT 0x10 + #define RTE_ENET_MII_TX_CLK_PIN 0 + #define RTE_ENET_MII_TX_CLK_FUNC 7 +#else + #error "Invalid ENET_TX_CLK Pin Configuration!" +#endif +// ENET_TX_ER Pin <0=>Not used <1=>PC_5 <2=>PC_14 +// Optional signal, rarely used +#define RTE_ENET_MII_TX_ER_PORT_ID 0 +#if (RTE_ENET_MII_TX_ER_PORT_ID == 0) + #define RTE_ENET_MII_TX_ER_PIN_EN 0 +#elif (RTE_ENET_MII_TX_ER_PORT_ID == 1) + #define RTE_ENET_MII_TX_ER_PORT 0xC + #define RTE_ENET_MII_TX_ER_PIN 5 + #define RTE_ENET_MII_TX_ER_FUNC 3 +#elif (RTE_ENET_MII_TX_ER_PORT_ID == 2) + #define RTE_ENET_MII_TX_ER_PORT 0xC + #define RTE_ENET_MII_TX_ER_PIN 14 + #define RTE_ENET_MII_TX_ER_FUNC 6 +#else + #error "Invalid ENET_TX_ER Pin Configuration!" +#endif +#ifndef RTE_ENET_MII_TX_ER_PIN_EN + #define RTE_ENET_MII_TX_ER_PIN_EN 1 +#endif +// ENET_RXD0 Pin <0=>P1_15 +#define RTE_ENET_MII_RXD0_PORT_ID 0 +#if (RTE_ENET_MII_RXD0_PORT_ID == 0) + #define RTE_ENET_MII_RXD0_PORT 1 + #define RTE_ENET_MII_RXD0_PIN 15 + #define RTE_ENET_MII_RXD0_FUNC 3 +#else + #error "Invalid ENET_RXD0 Pin Configuration!" +#endif +// ENET_RXD1 Pin <0=>P0_0 +#define RTE_ENET_MII_RXD1_PORT_ID 0 +#if (RTE_ENET_MII_RXD1_PORT_ID == 0) + #define RTE_ENET_MII_RXD1_PORT 0 + #define RTE_ENET_MII_RXD1_PIN 0 + #define RTE_ENET_MII_RXD1_FUNC 2 +#else + #error "Invalid ENET_RXD1 Pin Configuration!" +#endif +// ENET_RXD2 Pin <0=>P9_3 <1=>PC_6 +#define RTE_ENET_MII_RXD2_PORT_ID 0 +#if (RTE_ENET_MII_RXD2_PORT_ID == 0) + #define RTE_ENET_MII_RXD2_PORT 9 + #define RTE_ENET_MII_RXD2_PIN 3 + #define RTE_ENET_MII_RXD2_FUNC 5 +#elif (RTE_ENET_MII_RXD2_PORT_ID == 1) + #define RTE_ENET_MII_RXD2_PORT 0xC + #define RTE_ENET_MII_RXD2_PIN 6 + #define RTE_ENET_MII_RXD2_FUNC 3 +#else + #error "Invalid ENET_RXD2 Pin Configuration!" +#endif +// ENET_RXD3 Pin <0=>P9_2 <1=>PC_7 +#define RTE_ENET_MII_RXD3_PORT_ID 0 +#if (RTE_ENET_MII_RXD3_PORT_ID == 0) + #define RTE_ENET_MII_RXD3_PORT 9 + #define RTE_ENET_MII_RXD3_PIN 2 + #define RTE_ENET_MII_RXD3_FUNC 5 +#elif (RTE_ENET_MII_RXD3_PORT_ID == 1) + #define RTE_ENET_MII_RXD3_PORT 0xC + #define RTE_ENET_MII_RXD3_PIN 7 + #define RTE_ENET_MII_RXD3_FUNC 3 +#else + #error "Invalid ENET_RXD3 Pin Configuration!" +#endif +// ENET_RX_DV Pin <0=>P1_16 <1=>PC_8 +#define RTE_ENET_MII_RX_DV_PORT_ID 0 +#if (RTE_ENET_MII_RX_DV_PORT_ID == 0) + #define RTE_ENET_MII_RX_DV_PORT 1 + #define RTE_ENET_MII_RX_DV_PIN 16 + #define RTE_ENET_MII_RX_DV_FUNC 7 +#elif (RTE_ENET_MII_RX_DV_PORT_ID == 1) + #define RTE_ENET_MII_RX_DV_PORT 0xC + #define RTE_ENET_MII_RX_DV_PIN 8 + #define RTE_ENET_MII_RX_DV_FUNC 3 +#else + #error "Invalid ENET_RX_DV Pin Configuration!" +#endif +// ENET_RX_CLK Pin <0=>PC_0 +#define RTE_ENET_MII_RX_CLK_PORT_ID 0 +#if (RTE_ENET_MII_RX_CLK_PORT_ID == 0) + #define RTE_ENET_MII_RX_CLK_PORT 0xC + #define RTE_ENET_MII_RX_CLK_PIN 0 + #define RTE_ENET_MII_RX_CLK_FUNC 3 +#else + #error "Invalid ENET_RX_CLK Pin Configuration!" +#endif +// ENET_RX_ER Pin <0=>P9_1 <1=>PC_9 +#define RTE_ENET_MII_RX_ER_PORT_ID 0 +#if (RTE_ENET_MII_RX_ER_PORT_ID == 0) + #define RTE_ENET_MII_RX_ER_PORT 9 + #define RTE_ENET_MII_RX_ER_PIN 1 + #define RTE_ENET_MII_RX_ER_FUNC 5 +#elif (RTE_ENET_MII_RX_ER_PORT_ID == 1) + #define RTE_ENET_MII_RX_ER_PORT 0xC + #define RTE_ENET_MII_RX_ER_PIN 9 + #define RTE_ENET_MII_RX_ER_FUNC 3 +#else + #error "Invalid ENET_RX_ER Pin Configuration!" +#endif +// ENET_COL Pin <0=>P0_1 <1=>P4_1 <2=>P9_6 +#define RTE_ENET_MII_COL_PORT_ID 0 +#if (RTE_ENET_MII_COL_PORT_ID == 0) + #define RTE_ENET_MII_COL_PORT 0 + #define RTE_ENET_MII_COL_PIN 1 + #define RTE_ENET_MII_COL_FUNC 2 +#elif (RTE_ENET_MII_COL_PORT_ID == 1) + #define RTE_ENET_MII_COL_PORT 4 + #define RTE_ENET_MII_COL_PIN 1 + #define RTE_ENET_MII_COL_FUNC 7 +#elif (RTE_ENET_MII_COL_PORT_ID == 2) + #define RTE_ENET_MII_COL_PORT 9 + #define RTE_ENET_MII_COL_PIN 6 + #define RTE_ENET_MII_COL_FUNC 5 +#else + #error "Invalid ENET_COL Pin Configuration!" +#endif +// ENET_CRS Pin <0=>P1_16 <1=>P9_0 +#define RTE_ENET_MII_CRS_PORT_ID 0 +#if (RTE_ENET_MII_CRS_PORT_ID == 0) + #define RTE_ENET_MII_CRS_PORT 1 + #define RTE_ENET_MII_CRS_PIN 16 + #define RTE_ENET_MII_CRS_FUNC 3 +#elif (RTE_ENET_MII_CRS_PORT_ID == 1) + #define RTE_ENET_MII_CRS_PORT 9 + #define RTE_ENET_MII_CRS_PIN 0 + #define RTE_ENET_MII_CRS_FUNC 5 +#else + #error "Invalid ENET_CRS Pin Configuration!" +#endif +// MII (Media Independent Interface) + +// RMII (Reduced Media Independent Interface) +#define RTE_ENET_RMII 0 + +// ENET_TXD0 Pin <0=>P1_18 +#define RTE_ENET_RMII_TXD0_PORT_ID 0 +#if (RTE_ENET_RMII_TXD0_PORT_ID == 0) + #define RTE_ENET_RMII_TXD0_PORT 1 + #define RTE_ENET_RMII_TXD0_PIN 18 + #define RTE_ENET_RMII_TXD0_FUNC 3 +#else + #error "Invalid ENET_TXD0 Pin Configuration!" +#endif +// ENET_TXD1 Pin <0=>P1_20 +#define RTE_ENET_RMII_TXD1_PORT_ID 0 +#if (RTE_ENET_RMII_TXD1_PORT_ID == 0) + #define RTE_ENET_RMII_TXD1_PORT 1 + #define RTE_ENET_RMII_TXD1_PIN 20 + #define RTE_ENET_RMII_TXD1_FUNC 3 +#else + #error "Invalid ENET_TXD1 Pin Configuration!" +#endif +// ENET_TX_EN Pin <0=>P0_1 <1=>PC_4 +#define RTE_ENET_RMII_TX_EN_PORT_ID 0 +#if (RTE_ENET_RMII_TX_EN_PORT_ID == 0) + #define RTE_ENET_RMII_TX_EN_PORT 0 + #define RTE_ENET_RMII_TX_EN_PIN 1 + #define RTE_ENET_RMII_TX_EN_FUNC 6 +#elif (RTE_ENET_RMII_TX_EN_PORT_ID == 1) + #define RTE_ENET_RMII_TX_EN_PORT 0xC + #define RTE_ENET_RMII_TX_EN_PIN 4 + #define RTE_ENET_RMII_TX_EN_FUNC 3 +#else + #error "Invalid ENET_TX_EN Pin Configuration!" +#endif +// ENET_REF_CLK Pin <0=>P1_19 <1=>CLK0 +#define RTE_ENET_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ENET_RMII_REF_CLK_PORT_ID == 0) + #define RTE_ENET_RMII_REF_CLK_PORT 1 + #define RTE_ENET_RMII_REF_CLK_PIN 19 + #define RTE_ENET_RMII_REF_CLK_FUNC 0 +#elif (RTE_ENET_RMII_REF_CLK_PORT_ID == 1) + #define RTE_ENET_RMII_REF_CLK_PORT 0x10 + #define RTE_ENET_RMII_REF_CLK_PIN 0 + #define RTE_ENET_RMII_REF_CLK_FUNC 7 +#else + #error "Invalid ENET_REF_CLK Pin Configuration!" +#endif +// ENET_RXD0 Pin <0=>P1_15 +#define RTE_ENET_RMII_RXD0_PORT_ID 0 +#if (RTE_ENET_RMII_RXD0_PORT_ID == 0) + #define RTE_ENET_RMII_RXD0_PORT 1 + #define RTE_ENET_RMII_RXD0_PIN 15 + #define RTE_ENET_RMII_RXD0_FUNC 3 +#else + #error "Invalid ENET_RXD0 Pin Configuration!" +#endif +// ENET_RXD1 Pin <0=>P0_0 +#define RTE_ENET_RMII_RXD1_PORT_ID 0 +#if (RTE_ENET_RMII_RXD1_PORT_ID == 0) + #define RTE_ENET_RMII_RXD1_PORT 0 + #define RTE_ENET_RMII_RXD1_PIN 0 + #define RTE_ENET_RMII_RXD1_FUNC 2 +#else + #error "Invalid ENET_RXD1 Pin Configuration!" +#endif +// ENET_RX_DV Pin <0=>P1_16 <1=>PC_8 +#define RTE_ENET_RMII_RX_DV_PORT_ID 0 +#if (RTE_ENET_RMII_RX_DV_PORT_ID == 0) + #define RTE_ENET_RMII_RX_DV_PORT 1 + #define RTE_ENET_RMII_RX_DV_PIN 16 + #define RTE_ENET_RMII_RX_DV_FUNC 7 +#elif (RTE_ENET_RMII_RX_DV_PORT_ID == 1) + #define RTE_ENET_RMII_RX_DV_PORT 0xC + #define RTE_ENET_RMII_RX_DV_PIN 8 + #define RTE_ENET_RMII_RX_DV_FUNC 3 +#else + #error "Invalid ENET_RX_DV Pin Configuration!" +#endif +// RMII (Reduced Media Independent Interface) + +// MIIM (Management Data Interface) +// ENET_MDIO Pin <0=>P1_17 +#define RTE_ENET_MDI_MDIO_PORT_ID 0 +#if (RTE_ENET_MDI_MDIO_PORT_ID == 0) + #define RTE_ENET_MDI_MDIO_PORT 1 + #define RTE_ENET_MDI_MDIO_PIN 17 + #define RTE_ENET_MDI_MDIO_FUNC 3 +#else + #error "Invalid ENET_MDIO Pin Configuration!" +#endif +// ENET_MDC Pin <0=>P2_0 <1=>P7_7 <2=>PC_1 +#define RTE_ENET_MDI_MDC_PORT_ID 2 +#if (RTE_ENET_MDI_MDC_PORT_ID == 0) + #define RTE_ENET_MDI_MDC_PORT 2 + #define RTE_ENET_MDI_MDC_PIN 0 + #define RTE_ENET_MDI_MDC_FUNC 7 +#elif (RTE_ENET_MDI_MDC_PORT_ID == 1) + #define RTE_ENET_MDI_MDC_PORT 7 + #define RTE_ENET_MDI_MDC_PIN 7 + #define RTE_ENET_MDI_MDC_FUNC 6 +#elif (RTE_ENET_MDI_MDC_PORT_ID == 2) + #define RTE_ENET_MDI_MDC_PORT 0xC + #define RTE_ENET_MDI_MDC_PIN 1 + #define RTE_ENET_MDI_MDC_FUNC 3 +#else + #error "Invalid ENET_MDC Pin Configuration!" +#endif +// MIIM (Management Data Interface) +// ENET (Ethernet Interface) [Driver_ETH_MAC0] + +// SD/MMC Interface [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::Drivers:MCI +#define RTE_SDMMC 0 + +// SD/MMC Peripheral Bus +// SD_CLK Pin <0=>PC_0 <1=>CLK0 <2=>CLK2 +#define RTE_SD_CLK_PORT_ID 0 +#if (RTE_SD_CLK_PORT_ID == 0) + #define RTE_SD_CLK_PORT 0xC + #define RTE_SD_CLK_PIN 0 + #define RTE_SD_CLK_FUNC 7 +#elif (RTE_SD_CLK_PORT_ID == 1) + #define RTE_SD_CLK_PORT 0x10 + #define RTE_SD_CLK_PIN 0 + #define RTE_SD_CLK_FUNC 4 +#elif (RTE_SD_CLK_PORT_ID == 2) + #define RTE_SD_CLK_PORT 0x10 + #define RTE_SD_CLK_PIN 2 + #define RTE_SD_CLK_FUNC 4 +#else + #error "Invalid SD_CLK Pin Configuration!" +#endif +// SD_CMD Pin <0=>P1_6 <1=>PC_10 +#define RTE_SD_CMD_PORT_ID 0 +#if (RTE_SD_CMD_PORT_ID == 0) + #define RTE_SD_CMD_PORT 1 + #define RTE_SD_CMD_PIN 6 + #define RTE_SD_CMD_FUNC 7 +#elif (RTE_SD_CMD_PORT_ID == 1) + #define RTE_SD_CMD_PORT 0xC + #define RTE_SD_CMD_PIN 10 + #define RTE_SD_CMD_FUNC 7 +#else + #error "Invalid SD_CMD Pin Configuration!" +#endif +// SD_DAT0 Pin <0=>P1_9 <1=>PC_4 +#define RTE_SD_DAT0_PORT_ID 0 +#if (RTE_SD_DAT0_PORT_ID == 0) + #define RTE_SD_DAT0_PORT 1 + #define RTE_SD_DAT0_PIN 9 + #define RTE_SD_DAT0_FUNC 7 +#elif (RTE_SD_DAT0_PORT_ID == 1) + #define RTE_SD_DAT0_PORT 0xC + #define RTE_SD_DAT0_PIN 4 + #define RTE_SD_DAT0_FUNC 7 +#else + #error "Invalid SD_DAT0 Pin Configuration!" +#endif +// SD_DAT[1 .. 3] +#define RTE_SDMMC_BUS_WIDTH_4 0 +// SD_DAT1 Pin <0=>P1_10 <1=>PC_5 +#define RTE_SD_DAT1_PORT_ID 0 +#if (RTE_SD_DAT1_PORT_ID == 0) + #define RTE_SD_DAT1_PORT 1 + #define RTE_SD_DAT1_PIN 10 + #define RTE_SD_DAT1_FUNC 7 +#elif (RTE_SD_DAT1_PORT_ID == 1) + #define RTE_SD_DAT1_PORT 0xC + #define RTE_SD_DAT1_PIN 5 + #define RTE_SD_DAT1_FUNC 7 +#else + #error "Invalid SD_DAT1 Pin Configuration!" +#endif +// SD_DAT2 Pin <0=>P1_11 <1=>PC_6 +#define RTE_SD_DAT2_PORT_ID 0 +#if (RTE_SD_DAT2_PORT_ID == 0) + #define RTE_SD_DAT2_PORT 1 + #define RTE_SD_DAT2_PIN 11 + #define RTE_SD_DAT2_FUNC 7 +#elif (RTE_SD_DAT2_PORT_ID == 1) + #define RTE_SD_DAT2_PORT 0xC + #define RTE_SD_DAT2_PIN 6 + #define RTE_SD_DAT2_FUNC 7 +#else + #error "Invalid SD_DAT2 Pin Configuration!" +#endif +// SD_DAT3 Pin <0=>P1_12 <1=>PC_7 +#define RTE_SD_DAT3_PORT_ID 0 +#if (RTE_SD_DAT3_PORT_ID == 0) + #define RTE_SD_DAT3_PORT 1 + #define RTE_SD_DAT3_PIN 12 + #define RTE_SD_DAT3_FUNC 7 +#elif (RTE_SD_DAT3_PORT_ID == 1) + #define RTE_SD_DAT3_PORT 0xC + #define RTE_SD_DAT3_PIN 7 + #define RTE_SD_DAT3_FUNC 7 +#else + #error "Invalid SD_DAT3 Pin Configuration!" +#endif +// SD_DAT[1 .. 3] +// SD_DAT[4 .. 7] +#define RTE_SDMMC_BUS_WIDTH_8 0 +// SD_DAT4 Pin <0=>PC_11 +#define RTE_SD_DAT4_PORT_ID 0 +#if (RTE_SD_DAT4_PORT_ID == 0) + #define RTE_SD_DAT4_PORT 0xC + #define RTE_SD_DAT4_PIN 11 + #define RTE_SD_DAT4_FUNC 7 +#else + #error "Invalid SD_DAT4 Pin Configuration!" +#endif +// SD_DAT5 Pin <0=>PC_12 +#define RTE_SD_DAT5_PORT_ID 0 +#if (RTE_SD_DAT5_PORT_ID == 0) + #define RTE_SD_DAT5_PORT 0xC + #define RTE_SD_DAT5_PIN 12 + #define RTE_SD_DAT5_FUNC 7 +#else + #error "Invalid SD_DAT5 Pin Configuration!" +#endif +// SD_DAT6 Pin <0=>PC_13 +#define RTE_SD_DAT6_PORT_ID 0 +#if (RTE_SD_DAT6_PORT_ID == 0) + #define RTE_SD_DAT6_PORT 0xC + #define RTE_SD_DAT6_PIN 13 + #define RTE_SD_DAT6_FUNC 7 +#else + #error "Invalid SD_DAT6 Pin Configuration!" +#endif +// SD_DAT7 Pin <0=>PC_14 +#define RTE_SD_DAT7_PORT_ID 0 +#if (RTE_SD_DAT7_PORT_ID == 0) + #define RTE_SD_DAT7_PORT 0xC + #define RTE_SD_DAT7_PIN 14 + #define RTE_SD_DAT7_FUNC 7 +#else + #error "Invalid SD_DAT7 Pin Configuration!" +#endif +// SD_DAT[4 .. 7] +// SD/MMC Peripheral Bus + +// SD_CD (Card Detect) Pin <0=>Not used <1=>P1_13 <2=>PC_8 +// Configure Pin if exists +#define RTE_SD_CD_PORT_ID 0 +#if (RTE_SD_CD_PORT_ID == 0) + #define RTE_SD_CD_PIN_EN 0 +#elif (RTE_SD_CD_PORT_ID == 1) + #define RTE_SD_CD_PORT 1 + #define RTE_SD_CD_PIN 13 + #define RTE_SD_CD_FUNC 7 +#elif (RTE_SD_CD_PORT_ID == 2) + #define RTE_SD_CD_PORT 0xC + #define RTE_SD_CD_PIN 8 + #define RTE_SD_CD_FUNC 7 +#else + #error "Invalid SD_CD Pin Configuration!" +#endif +#ifndef RTE_SD_CD_PIN_EN + #define RTE_SD_CD_PIN_EN 1 +#endif +// SD_WP (Write Protect) Pin <0=>Not used <1=>PD_15 <2=>PF_10 +// Configure Pin if exists +#define RTE_SD_WP_PORT_ID 0 +#if (RTE_SD_WP_PORT_ID == 0) + #define RTE_SD_WP_PIN_EN 0 +#elif (RTE_SD_WP_PORT_ID == 1) + #define RTE_SD_WP_PORT 0xD + #define RTE_SD_WP_PIN 15 + #define RTE_SD_WP_FUNC 5 +#elif (RTE_SD_WP_PORT_ID == 2) + #define RTE_SD_WP_PORT 0xF + #define RTE_SD_WP_PIN 10 + #define RTE_SD_WP_FUNC 6 +#else + #error "Invalid SD_WP Pin Configuration!" +#endif +#ifndef RTE_SD_WP_PIN_EN + #define RTE_SD_WP_PIN_EN 1 +#endif +// SD_POW (Power) Pin <0=>Not used <1=>P1_5 <2=>PC_9 <3=>PD_1 +// Configure Pin if exists +#define RTE_SD_POW_PORT_ID 0 +#if (RTE_SD_POW_PORT_ID == 0) + #define RTE_SD_POW_PIN_EN 0 +#elif (RTE_SD_POW_PORT_ID == 1) + #define RTE_SD_POW_PORT 1 + #define RTE_SD_POW_PIN 5 + #define RTE_SD_POW_FUNC 7 +#elif (RTE_SD_POW_PORT_ID == 2) + #define RTE_SD_POW_PORT 0xC + #define RTE_SD_POW_PIN 9 + #define RTE_SD_POW_FUNC 7 +#elif (RTE_SD_POW_PORT_ID == 3) + #define RTE_SD_POW_PORT 0xD + #define RTE_SD_POW_PIN 1 + #define RTE_SD_POW_FUNC 5 +#else + #error "Invalid SD_POW Pin Configuration!" +#endif +#ifndef RTE_SD_POW_PIN_EN + #define RTE_SD_POW_PIN_EN 1 +#endif +// SD_RST (Card Reset for MMC4.4) Pin <0=>Not used <1=>P1_3 <2=>PC_2 +// Configure Pin if exists +#define RTE_SD_RST_PORT_ID 0 +#if (RTE_SD_RST_PORT_ID == 0) + #define RTE_SD_RST_PIN_EN 0 +#elif (RTE_SD_RST_PORT_ID == 1) + #define RTE_SD_RST_PORT 1 + #define RTE_SD_RST_PIN 3 + #define RTE_SD_RST_FUNC 7 +#elif (RTE_SD_RST_PORT_ID == 2) + #define RTE_SD_RST_PORT 0xC + #define RTE_SD_RST_PIN 2 + #define RTE_SD_RST_FUNC 7 +#else + #error "Invalid SD_RST Pin Configuration!" +#endif +#ifndef RTE_SD_RST_PIN_EN + #define RTE_SD_RST_PIN_EN 1 +#endif +// SD/MMC Interface [Driver_MCI0] + +// I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::Drivers:I2C +// I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0] +#define RTE_I2C0 0 + +// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] +// Configuration settings for Driver_I2C1 in component ::Drivers:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>P2_4 <1=>PE_15 +#define RTE_I2C1_SCL_PORT_ID 0 +#if (RTE_I2C1_SCL_PORT_ID == 0) + #define RTE_I2C1_SCL_PORT 2 + #define RTE_I2C1_SCL_PIN 4 + #define RTE_I2C1_SCL_FUNC 1 +#elif (RTE_I2C1_SCL_PORT_ID == 1) + #define RTE_I2C1_SCL_PORT 0xE + #define RTE_I2C1_SCL_PIN 15 + #define RTE_I2C1_SCL_FUNC 2 +#else + #error "Invalid I2C1_SCL Pin Configuration!" +#endif +// I2C1_SDA Pin <0=>P2_3 <1=>PE_13 +#define RTE_I2C1_SDA_PORT_ID 0 +#if (RTE_I2C1_SDA_PORT_ID == 0) + #define RTE_I2C1_SDA_PORT 2 + #define RTE_I2C1_SDA_PIN 3 + #define RTE_I2C1_SDA_FUNC 1 +#elif (RTE_I2C1_SDA_PORT_ID == 1) + #define RTE_I2C1_SDA_PORT 0xE + #define RTE_I2C1_SDA_PIN 13 + #define RTE_I2C1_SDA_FUNC 2 +#else + #error "Invalid I2C1_SDA Pin Configuration!" +#endif +// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] + +// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] +#define RTE_USART0 0 + +// Pin Configuration +// TX <0=>Not used <1=>P2_0 <2=>P6_4 <3=>P9_5 <4=>PF_10 +// USART0 Serial Output pin +#define RTE_USART0_TX_ID 0 +#if (RTE_USART0_TX_ID == 0) + #define RTE_USART0_TX_PIN_EN 0 +#elif (RTE_USART0_TX_ID == 1) + #define RTE_USART0_TX_PORT 2 + #define RTE_USART0_TX_BIT 0 + #define RTE_USART0_TX_FUNC 1 +#elif (RTE_USART0_TX_ID == 2) + #define RTE_USART0_TX_PORT 6 + #define RTE_USART0_TX_BIT 4 + #define RTE_USART0_TX_FUNC 2 +#elif (RTE_USART0_TX_ID == 3) + #define RTE_USART0_TX_PORT 9 + #define RTE_USART0_TX_BIT 5 + #define RTE_USART0_TX_FUNC 7 +#elif (RTE_USART0_TX_ID == 4) + #define RTE_USART0_TX_PORT 0xF + #define RTE_USART0_TX_BIT 10 + #define RTE_USART0_TX_FUNC 1 +#else + #error "Invalid USART0_TX Pin Configuration!" +#endif +#ifndef RTE_USART0_TX_PIN_EN + #define RTE_USART0_TX_PIN_EN 1 +#endif +// RX <0=>Not used <1=>P2_1 <2=>P6_5 <3=>P9_6 <4=>PF_11 +// USART0 Serial Input pin +#define RTE_USART0_RX_ID 0 +#if (RTE_USART0_RX_ID == 0) + #define RTE_USART0_RX_PIN_EN 0 +#elif (RTE_USART0_RX_ID == 1) + #define RTE_USART0_RX_PORT 2 + #define RTE_USART0_RX_BIT 1 + #define RTE_USART0_RX_FUNC 1 +#elif (RTE_USART0_RX_ID == 2) + #define RTE_USART0_RX_PORT 6 + #define RTE_USART0_RX_BIT 5 + #define RTE_USART0_RX_FUNC 2 +#elif (RTE_USART0_RX_ID == 3) + #define RTE_USART0_RX_PORT 9 + #define RTE_USART0_RX_BIT 6 + #define RTE_USART0_RX_FUNC 7 +#elif (RTE_USART0_RX_ID == 4) + #define RTE_USART0_RX_PORT 0xF + #define RTE_USART0_RX_BIT 11 + #define RTE_USART0_RX_FUNC 1 +#else + #error "Invalid USART0_RX Pin Configuration!" +#endif +#ifndef RTE_USART0_RX_PIN_EN + #define RTE_USART0_RX_PIN_EN 1 +#endif +// UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_2 <2=>P6_1 <3=>PF_8 +// USART0 Serial Clock input/output synchronous mode +#define RTE_USART0_UCLK_ID 0 +#if (RTE_USART0_UCLK_ID == 0) + #define RTE_USART0_UCLK_PIN_EN 0 +#elif (RTE_USART0_UCLK_ID == 1) + #define RTE_USART0_UCLK_PORT 2 + #define RTE_USART0_UCLK_BIT 2 + #define RTE_USART0_UCLK_FUNC 1 +#elif (RTE_USART0_UCLK_ID == 2) + #define RTE_USART0_UCLK_PORT 6 + #define RTE_USART0_UCLK_BIT 1 + #define RTE_USART0_UCLK_FUNC 2 +#elif (RTE_USART0_UCLK_ID == 3) + #define RTE_USART0_UCLK_PORT 0xF + #define RTE_USART0_UCLK_BIT 8 + #define RTE_USART0_UCLK_FUNC 1 +#else + #error "Invalid USART0_UCLK Pin Configuration!" +#endif +#ifndef RTE_USART0_UCLK_PIN_EN + #define RTE_USART0_UCLK_PIN_EN 1 +#endif +// Pin Configuration + +// DMA +// Tx +// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// Peripheral <0=>1 (DMAMUXPER1) <1=>11 (DMAMUXPER11) +// +#define RTE_USART0_DMA_TX_EN 0 +#define RTE_USART0_DMA_TX_CH 0 +#define RTE_USART0_DMA_TX_PERI_ID 0 +#if (RTE_USART0_DMA_TX_PERI_ID == 0) + #define RTE_USART0_DMA_TX_PERI 1 + #define RTE_USART0_DMA_TX_PERI_SEL 1 +#elif (RTE_USART0_DMA_TX_PERI_ID == 1) + #define RTE_USART0_DMA_TX_PERI 11 + #define RTE_USART0_DMA_TX_PERI_SEL 2 +#endif +// Rx +// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// Peripheral <0=>2 (DMAMUXPER2) <1=>12 (DMAMUXPER12) +// +#define RTE_USART0_DMA_RX_EN 0 +#define RTE_USART0_DMA_RX_CH 1 +#define RTE_USART0_DMA_RX_PERI_ID 0 +#if (RTE_USART0_DMA_RX_PERI_ID == 0) + #define RTE_USART0_DMA_RX_PERI 2 + #define RTE_USART0_DMA_RX_PERI_SEL 1 +#elif (RTE_USART0_DMA_RX_PERI_ID == 1) + #define RTE_USART0_DMA_RX_PERI 12 + #define RTE_USART0_DMA_RX_PERI_SEL 2 +#endif +// DMA +// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] + +// UART1 (Universal asynchronous receiver transmitter) [Driver_USART1] +#define RTE_UART1 0 + +// Pin Configuration +// TX <0=>Not used <1=>P1_13 <2=>P3_4 <3=>P5_6 <4=>PC_13 <5=>PE_11 +// UART0 Serial Output pin +#define RTE_UART1_TX_ID 2 +#if (RTE_UART1_TX_ID == 0) + #define RTE_UART1_TX_PIN_EN 0 +#elif (RTE_UART1_TX_ID == 1) + #define RTE_UART1_TX_PORT 1 + #define RTE_UART1_TX_BIT 13 + #define RTE_UART1_TX_FUNC 1 +#elif (RTE_UART1_TX_ID == 2) + #define RTE_UART1_TX_PORT 3 + #define RTE_UART1_TX_BIT 4 + #define RTE_UART1_TX_FUNC 4 +#elif (RTE_UART1_TX_ID == 3) + #define RTE_UART1_TX_PORT 5 + #define RTE_UART1_TX_BIT 6 + #define RTE_UART1_TX_FUNC 4 +#elif (RTE_UART1_TX_ID == 4) + #define RTE_UART1_TX_PORT 0xC + #define RTE_UART1_TX_BIT 13 + #define RTE_UART1_TX_FUNC 2 +#elif (RTE_UART1_TX_ID == 5) + #define RTE_UART1_TX_PORT 0xE + #define RTE_UART1_TX_BIT 11 + #define RTE_UART1_TX_FUNC 2 +#else + #error "Invalid UART1_TX Pin Configuration!" +#endif +#ifndef RTE_UART1_TX_PIN_EN + #define RTE_UART1_TX_PIN_EN 1 +#endif +// RX <0=>Not used <1=>P1_14 <2=>P3_5 <3=>P5_7 <4=>PC_14 <5=>PE_12 +// UART1 Serial Input pin +#define RTE_UART1_RX_ID 0 +#if (RTE_UART1_RX_ID == 0) + #define RTE_UART1_RX_PIN_EN 0 +#elif (RTE_UART1_RX_ID == 1) + #define RTE_UART1_RX_PORT 1 + #define RTE_UART1_RX_BIT 14 + #define RTE_UART1_RX_FUNC 1 +#elif (RTE_UART1_RX_ID == 2) + #define RTE_UART1_RX_PORT 3 + #define RTE_UART1_RX_BIT 5 + #define RTE_UART1_RX_FUNC 4 +#elif (RTE_UART1_RX_ID == 3) + #define RTE_UART1_RX_PORT 5 + #define RTE_UART1_RX_BIT 7 + #define RTE_UART1_RX_FUNC 4 +#elif (RTE_UART1_RX_ID == 4) + #define RTE_UART1_RX_PORT 0xC + #define RTE_UART1_RX_BIT 14 + #define RTE_UART1_RX_FUNC 2 +#elif (RTE_UART1_RX_ID == 5) + #define RTE_UART1_RX_PORT 0xE + #define RTE_UART1_RX_BIT 12 + #define RTE_UART1_RX_FUNC 2 +#else + #error "Invalid UART1_RX Pin Configuration!" +#endif +#ifndef RTE_UART1_RX_PIN_EN + #define RTE_UART1_RX_PIN_EN 1 +#endif + +// Modem Lines +// CTS <0=>Not used <1=>P1_11 <2=>P5_4 <3=>PC_2 <4=>PE_7 +#define RTE_UART1_CTS_ID 1 +#if (RTE_UART1_CTS_ID == 0) + #define RTE_UART1_CTS_PIN_EN 0 +#elif (RTE_UART1_CTS_ID == 1) + #define RTE_UART1_CTS_PORT 1 + #define RTE_UART1_CTS_BIT 11 + #define RTE_UART1_CTS_FUNC 1 +#elif (RTE_UART1_CTS_ID == 2) + #define RTE_UART1_CTS_PORT 5 + #define RTE_UART1_CTS_BIT 4 + #define RTE_UART1_CTS_FUNC 4 +#elif (RTE_UART1_CTS_ID == 3) + #define RTE_UART1_CTS_PORT 0xC + #define RTE_UART1_CTS_BIT 2 + #define RTE_UART1_CTS_FUNC 2 +#elif (RTE_UART1_CTS_ID == 4) + #define RTE_UART1_CTS_PORT 0xE + #define RTE_UART1_CTS_BIT 7 + #define RTE_UART1_CTS_FUNC 2 +#else + #error "Invalid UART1_CTS Pin Configuration!" +#endif +#ifndef RTE_UART1_CTS_PIN_EN + #define RTE_UART1_CTS_PIN_EN 1 +#endif +// RTS <0=>Not used <1=>P1_9 <2=>P5_2 <3=>PC_3 <4=>PE_5 +#define RTE_UART1_RTS_ID 1 +#if (RTE_UART1_RTS_ID == 0) + #define RTE_UART1_RTS_PIN_EN 0 +#elif (RTE_UART1_RTS_ID == 1) + #define RTE_UART1_RTS_PORT 1 + #define RTE_UART1_RTS_BIT 9 + #define RTE_UART1_RTS_FUNC 1 +#elif (RTE_UART1_RTS_ID == 2) + #define RTE_UART1_RTS_PORT 5 + #define RTE_UART1_RTS_BIT 2 + #define RTE_UART1_RTS_FUNC 4 +#elif (RTE_UART1_RTS_ID == 3) + #define RTE_UART1_RTS_PORT 0xC + #define RTE_UART1_RTS_BIT 3 + #define RTE_UART1_RTS_FUNC 2 +#elif (RTE_UART1_RTS_ID == 4) + #define RTE_UART1_RTS_PORT 0xE + #define RTE_UART1_RTS_BIT 5 + #define RTE_UART1_RTS_FUNC 2 +#else + #error "Invalid UART1_RTS Pin Configuration!" +#endif +#ifndef RTE_UART1_RTS_PIN_EN + #define RTE_UART1_RTS_PIN_EN 1 +#endif +// DCD <0=>Not used <1=>P1_12 <2=>P5_5 <3=>PC_11 <4=>PE_9 +#define RTE_UART1_DCD_ID 1 +#if (RTE_UART1_DCD_ID == 0) + #define RTE_UART1_DCD_PIN_EN 0 +#elif (RTE_UART1_DCD_ID == 1) + #define RTE_UART1_DCD_PORT 1 + #define RTE_UART1_DCD_BIT 12 + #define RTE_UART1_DCD_FUNC 1 +#elif (RTE_UART1_DCD_ID == 2) + #define RTE_UART1_DCD_PORT 5 + #define RTE_UART1_DCD_BIT 5 + #define RTE_UART1_DCD_FUNC 4 +#elif (RTE_UART1_DCD_ID == 3) + #define RTE_UART1_DCD_PORT 0xC + #define RTE_UART1_DCD_BIT 11 + #define RTE_UART1_DCD_FUNC 2 +#elif (RTE_UART1_DCD_ID == 4) + #define RTE_UART1_DCD_PORT 0xE + #define RTE_UART1_DCD_BIT 9 + #define RTE_UART1_DCD_FUNC 2 +#else + #error "Invalid UART1_DCD Pin Configuration!" +#endif +#ifndef RTE_UART1_DCD_PIN_EN + #define RTE_UART1_DCD_PIN_EN 1 +#endif +// DSR <0=>Not used <1=>P1_7 <2=>P5_0 <3=>PC_10 <4=>PE_8 +#define RTE_UART1_DSR_ID 1 +#if (RTE_UART1_DSR_ID == 0) + #define RTE_UART1_DSR_PIN_EN 0 +#elif (RTE_UART1_DSR_ID == 1) + #define RTE_UART1_DSR_PORT 1 + #define RTE_UART1_DSR_BIT 7 + #define RTE_UART1_DSR_FUNC 1 +#elif (RTE_UART1_DSR_ID == 2) + #define RTE_UART1_DSR_PORT 5 + #define RTE_UART1_DSR_BIT 0 + #define RTE_UART1_DSR_FUNC 4 +#elif (RTE_UART1_DSR_ID == 3) + #define RTE_UART1_DSR_PORT 0xC + #define RTE_UART1_DSR_BIT 10 + #define RTE_UART1_DSR_FUNC 2 +#elif (RTE_UART1_DSR_ID == 4) + #define RTE_UART1_DSR_PORT 0xE + #define RTE_UART1_DSR_BIT 8 + #define RTE_UART1_DSR_FUNC 2 +#else + #error "Invalid UART1_DSR Pin Configuration!" +#endif +#ifndef RTE_UART1_DSR_PIN_EN + #define RTE_UART1_DSR_PIN_EN 1 +#endif +// DTR <0=>Not used <1=>P1_8 <2=>P5_1 <3=>PC_12 <4=>PE_10 +#define RTE_UART1_DTR_ID 1 +#if (RTE_UART1_DTR_ID == 0) + #define RTE_UART1_DTR_PIN_EN 0 +#elif (RTE_UART1_DTR_ID == 1) + #define RTE_UART1_DTR_PORT 1 + #define RTE_UART1_DTR_BIT 8 + #define RTE_UART1_DTR_FUNC 1 +#elif (RTE_UART1_DTR_ID == 2) + #define RTE_UART1_DTR_PORT 5 + #define RTE_UART1_DTR_BIT 1 + #define RTE_UART1_DTR_FUNC 4 +#elif (RTE_UART1_DTR_ID == 3) + #define RTE_UART1_DTR_PORT 0xC + #define RTE_UART1_DTR_BIT 12 + #define RTE_UART1_DTR_FUNC 2 +#elif (RTE_UART1_DTR_ID == 4) + #define RTE_UART1_DTR_PORT 0xE + #define RTE_UART1_DTR_BIT 10 + #define RTE_UART1_DTR_FUNC 2 +#else + #error "Invalid UART1_DTR Pin Configuration!" +#endif +#ifndef RTE_UART1_DTR_PIN_EN + #define RTE_UART1_DTR_PIN_EN 1 +#endif +// RI <0=>Not used <1=>P1_10 <2=>P5_3 <3=>PC_1 <4=>PE_6 +#define RTE_UART1_RI_ID 1 +#if (RTE_UART1_RI_ID == 0) + #define RTE_UART1_RI_PIN_EN 0 +#elif (RTE_UART1_RI_ID == 1) + #define RTE_UART1_RI_PORT 1 + #define RTE_UART1_RI_BIT 10 + #define RTE_UART1_RI_FUNC 1 +#elif (RTE_UART1_RI_ID == 2) + #define RTE_UART1_RI_PORT 5 + #define RTE_UART1_RI_BIT 3 + #define RTE_UART1_RI_FUNC 4 +#elif (RTE_UART1_RI_ID == 3) + #define RTE_UART1_RI_PORT 0xC + #define RTE_UART1_RI_BIT 1 + #define RTE_UART1_RI_FUNC 2 +#elif (RTE_UART1_RI_ID == 4) + #define RTE_UART1_RI_PORT 0xE + #define RTE_UART1_RI_BIT 6 + #define RTE_UART1_RI_FUNC 2 +#else + #error "Invalid UART1_RI Pin Configuration!" +#endif +#ifndef RTE_UART1_RI_PIN_EN + #define RTE_UART1_RI_PIN_EN 1 +#endif +// Modem Lines +// Pin Configuration + +// DMA +// Tx +// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// Peripheral <0=>3 (DMAMUXPER3) +// +#define RTE_UART1_DMA_TX_EN 0 +#define RTE_UART1_DMA_TX_CH 0 +#define RTE_UART1_DMA_TX_PERI_ID 0 +#if (RTE_UART1_DMA_TX_PERI_ID == 0) + #define RTE_UART1_DMA_TX_PERI 3 + #define RTE_UART1_DMA_TX_PERI_SEL 1 +#endif +// Rx +// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// Peripheral <0=>4 (DMAMUXPER4) +// +#define RTE_UART1_DMA_RX_EN 0 +#define RTE_UART1_DMA_RX_CH 1 +#define RTE_UART1_DMA_RX_PERI_ID 0 +#if (RTE_UART1_DMA_RX_PERI_ID == 0) + #define RTE_UART1_DMA_RX_PERI 4 + #define RTE_UART1_DMA_RX_PERI_SEL 1 +#endif +// DMA +// UART1 (Universal asynchronous receiver transmitter) [Driver_USART1] + +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] +#define RTE_USART2 0 + +// Pin Configuration +// TX <0=>Not used <1=>P1_15 <2=>P2_10 <3=>P7_1 <4=>PA_1 +// USART2 Serial Output pin +#define RTE_USART2_TX_ID 0 +#if (RTE_USART2_TX_ID == 0) + #define RTE_USART2_TX_PIN_EN 0 +#elif (RTE_USART2_TX_ID == 1) + #define RTE_USART2_TX_PORT 1 + #define RTE_USART2_TX_BIT 15 + #define RTE_USART2_TX_FUNC 1 +#elif (RTE_USART2_TX_ID == 2) + #define RTE_USART2_TX_PORT 2 + #define RTE_USART2_TX_BIT 10 + #define RTE_USART2_TX_FUNC 2 +#elif (RTE_USART2_TX_ID == 3) + #define RTE_USART2_TX_PORT 7 + #define RTE_USART2_TX_BIT 1 + #define RTE_USART2_TX_FUNC 6 +#elif (RTE_USART2_TX_ID == 4) + #define RTE_USART2_TX_PORT 0xA + #define RTE_USART2_TX_BIT 1 + #define RTE_USART2_TX_FUNC 3 +#else + #error "Invalid USART2_TX Pin Configuration!" +#endif +#ifndef RTE_USART2_TX_PIN_EN + #define RTE_USART2_TX_PIN_EN 1 +#endif +// RX <0=>Not used <1=>P1_16 <2=>P2_11 <3=>P7_2 <4=>PA_2 +// USART2 Serial Input pin +#define RTE_USART2_RX_ID 0 +#if (RTE_USART2_RX_ID == 0) + #define RTE_USART2_RX_PIN_EN 0 +#elif (RTE_USART2_RX_ID == 1) + #define RTE_USART2_RX_PORT 1 + #define RTE_USART2_RX_BIT 16 + #define RTE_USART2_RX_FUNC 1 +#elif (RTE_USART2_RX_ID == 2) + #define RTE_USART2_RX_PORT 2 + #define RTE_USART2_RX_BIT 11 + #define RTE_USART2_RX_FUNC 2 +#elif (RTE_USART2_RX_ID == 3) + #define RTE_USART2_RX_PORT 7 + #define RTE_USART2_RX_BIT 2 + #define RTE_USART2_RX_FUNC 6 +#elif (RTE_USART2_RX_ID == 4) + #define RTE_USART2_RX_PORT 0xA + #define RTE_USART2_RX_BIT 2 + #define RTE_USART2_RX_FUNC 3 +#else + #error "Invalid USART2_RX Pin Configuration!" +#endif +#ifndef RTE_USART2_RX_PIN_EN + #define RTE_USART2_RX_PIN_EN 1 +#endif +// UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P1_17 <2=>P2_12 +// USART2 Serial Clock input/output synchronous mode +#define RTE_USART2_UCLK_ID 0 +#if (RTE_USART2_UCLK_ID == 0) + #define RTE_USART2_UCLK_PIN_EN 0 +#elif (RTE_USART2_UCLK_ID == 1) + #define RTE_USART2_UCLK_PORT 1 + #define RTE_USART2_UCLK_BIT 17 + #define RTE_USART2_UCLK_FUNC 1 +#elif (RTE_USART2_UCLK_ID == 2) + #define RTE_USART2_UCLK_PORT 2 + #define RTE_USART2_UCLK_BIT 12 + #define RTE_USART2_UCLK_FUNC 7 +#else + #error "Invalid USART2_UCLK Pin Configuration!" +#endif +#ifndef RTE_USART2_UCLK_PIN_EN + #define RTE_USART2_UCLK_PIN_EN 1 +#endif +// Pin Configuration + +// DMA +// Tx +// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// Peripheral <0=>5 (DMAMUXPER5) +// +#define RTE_USART2_DMA_TX_EN 0 +#define RTE_USART2_DMA_TX_CH 0 +#define RTE_USART2_DMA_TX_PERI_ID 0 +#if (RTE_USART2_DMA_TX_PERI_ID == 0) + #define RTE_USART2_DMA_TX_PERI 5 + #define RTE_USART2_DMA_TX_PERI_SEL 1 +#endif +// Rx +// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// Peripheral <0=>6 (DMAMUXPER6) +// +#define RTE_USART2_DMA_RX_EN 0 +#define RTE_USART2_DMA_RX_CH 1 +#define RTE_USART2_DMA_RX_PERI_ID 0 +#if (RTE_USART2_DMA_RX_PERI_ID == 0) + #define RTE_USART2_DMA_RX_PERI 6 + #define RTE_USART2_DMA_RX_PERI_SEL 1 +#endif +// DMA +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] + +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] +#define RTE_USART3 0 + +// Pin Configuration +// TX <0=>Not used <1=>P2_3 <2=>P4_1 <3=>P9_3 <4=>PF_2 +// USART3 Serial Output pin +#define RTE_USART3_TX_ID 0 +#if (RTE_USART3_TX_ID == 0) + #define RTE_USART3_TX_PIN_EN 0 +#elif (RTE_USART3_TX_ID == 1) + #define RTE_USART3_TX_PORT 2 + #define RTE_USART3_TX_BIT 3 + #define RTE_USART3_TX_FUNC 2 +#elif (RTE_USART3_TX_ID == 2) + #define RTE_USART3_TX_PORT 4 + #define RTE_USART3_TX_BIT 1 + #define RTE_USART3_TX_FUNC 6 +#elif (RTE_USART3_TX_ID == 3) + #define RTE_USART3_TX_PORT 9 + #define RTE_USART3_TX_BIT 3 + #define RTE_USART3_TX_FUNC 7 +#elif (RTE_USART3_TX_ID == 4) + #define RTE_USART3_TX_PORT 0xF + #define RTE_USART3_TX_BIT 2 + #define RTE_USART3_TX_FUNC 1 +#else + #error "Invalid USART3_TX Pin Configuration!" +#endif +#ifndef RTE_USART3_TX_PIN_EN + #define RTE_USART3_TX_PIN_EN 1 +#endif +// RX <0=>Not used <1=>P2_4 <2=>P4_2 <3=>P9_4 <4=>PF_3 +// USART3 Serial Input pin +#define RTE_USART3_RX_ID 0 +#if (RTE_USART3_RX_ID == 0) + #define RTE_USART3_RX_PIN_EN 0 +#elif (RTE_USART3_RX_ID == 1) + #define RTE_USART3_RX_PORT 2 + #define RTE_USART3_RX_BIT 4 + #define RTE_USART3_RX_FUNC 2 +#elif (RTE_USART3_RX_ID == 2) + #define RTE_USART3_RX_PORT 4 + #define RTE_USART3_RX_BIT 2 + #define RTE_USART3_RX_FUNC 6 +#elif (RTE_USART3_RX_ID == 3) + #define RTE_USART3_RX_PORT 9 + #define RTE_USART3_RX_BIT 4 + #define RTE_USART3_RX_FUNC 7 +#elif (RTE_USART3_RX_ID == 4) + #define RTE_USART3_RX_PORT 0xF + #define RTE_USART3_RX_BIT 3 + #define RTE_USART3_RX_FUNC 1 +#else + #error "Invalid USART3_RX Pin Configuration!" +#endif +#ifndef RTE_USART3_RX_PIN_EN + #define RTE_USART3_RX_PIN_EN 1 +#endif +// UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_7 <2=>P4_0 <3=>PF_5 +// USART3 Serial Clock input/output synchronous mode +#define RTE_USART3_UCLK_ID 0 +#if (RTE_USART3_UCLK_ID == 0) + #define RTE_USART3_UCLK_PIN_EN 0 +#elif (RTE_USART3_UCLK_ID == 1) + #define RTE_USART3_UCLK_PORT 2 + #define RTE_USART3_UCLK_BIT 7 + #define RTE_USART3_UCLK_FUNC 2 +#elif (RTE_USART3_UCLK_ID == 2) + #define RTE_USART3_UCLK_PORT 4 + #define RTE_USART3_UCLK_BIT 0 + #define RTE_USART3_UCLK_FUNC 6 +#elif (RTE_USART3_UCLK_ID == 3) + #define RTE_USART3_UCLK_PORT 0xF + #define RTE_USART3_UCLK_BIT 5 + #define RTE_USART3_UCLK_FUNC 1 +#else + #error "Invalid USART3_UCLK Pin Configuration!" +#endif +#ifndef RTE_USART3_UCLK_PIN_EN + #define RTE_USART3_UCLK_PIN_EN 1 +#endif +// Pin Configuration + +// DMA +// Tx +// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// Peripheral <0=>7 (DMAMUXPER7) <1=>14 (DMAMUXPER14) +// +#define RTE_USART3_DMA_TX_EN 0 +#define RTE_USART3_DMA_TX_CH 0 +#define RTE_USART3_DMA_TX_PERI_ID 0 +#if (RTE_USART3_DMA_TX_PERI_ID == 0) + #define RTE_USART3_DMA_TX_PERI 7 + #define RTE_USART3_DMA_TX_PERI_SEL 1 +#elif (RTE_USART3_DMA_TX_PERI_ID == 1) + #define RTE_USART3_DMA_TX_PERI 14 + #define RTE_USART3_DMA_TX_PERI_SEL 3 +#endif +// Rx +// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// Peripheral <0=>8 (DMAMUXPER8) <1=>13 (DMAMUXPER13) +// +#define RTE_USART3_DMA_RX_EN 0 +#define RTE_USART3_DMA_RX_CH 1 +#define RTE_USART3_DMA_RX_PERI_ID 0 +#if (RTE_USART3_DMA_RX_PERI_ID == 0) + #define RTE_USART3_DMA_RX_PERI 8 + #define RTE_USART3_DMA_RX_PERI_SEL 1 +#elif (RTE_USART3_DMA_RX_PERI_ID == 1) + #define RTE_USART3_DMA_RX_PERI 13 + #define RTE_USART3_DMA_RX_PERI_SEL 3 +#endif +// DMA +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] + +// SSP0 (Synchronous Serial Port 0) [Driver_SPI0] +// Configuration settings for Driver_SPI0 in component ::Drivers:SPI +#define RTE_SSP0 0 + +// Pin Configuration +// SSP0_SSEL <0=>Not used <1=>P1_0 <2=>P3_6 <3=>P3_8 <4=>P9_0 <5=>PF_1 +// Slave Select for SSP0 +#define RTE_SSP0_SSEL_PIN_SEL 1 +#if (RTE_SSP0_SSEL_PIN_SEL == 0) +#define RTE_SSP0_SSEL_PIN_EN 0 +#elif (RTE_SSP0_SSEL_PIN_SEL == 1) + #define RTE_SSP0_SSEL_PORT 1 + #define RTE_SSP0_SSEL_BIT 0 + #define RTE_SSP0_SSEL_FUNC 5 + #define RTE_SSP0_SSEL_GPIO_FUNC 0 + #define RTE_SSP0_SSEL_GPIO_PORT 0 + #define RTE_SSP0_SSEL_GPIO_BIT 4 +#elif (RTE_SSP0_SSEL_PIN_SEL == 2) + #define RTE_SSP0_SSEL_PORT 3 + #define RTE_SSP0_SSEL_BIT 6 + #define RTE_SSP0_SSEL_FUNC 2 + #define RTE_SSP0_SSEL_GPIO_FUNC 0 + #define RTE_SSP0_SSEL_GPIO_PORT 0 + #define RTE_SSP0_SSEL_GPIO_BIT 6 +#elif (RTE_SSP0_SSEL_PIN_SEL == 3) + #define RTE_SSP0_SSEL_PORT 3 + #define RTE_SSP0_SSEL_BIT 8 + #define RTE_SSP0_SSEL_FUNC 5 + #define RTE_SSP0_SSEL_GPIO_FUNC 4 + #define RTE_SSP0_SSEL_GPIO_PORT 5 + #define RTE_SSP0_SSEL_GPIO_BIT 11 +#elif (RTE_SSP0_SSEL_PIN_SEL == 4) + #define RTE_SSP0_SSEL_PORT 9 + #define RTE_SSP0_SSEL_BIT 0 + #define RTE_SSP0_SSEL_FUNC 7 + #define RTE_SSP0_SSEL_GPIO_FUNC 0 + #define RTE_SSP0_SSEL_GPIO_PORT 4 + #define RTE_SSP0_SSEL_GPIO_BIT 12 +#elif (RTE_SSP0_SSEL_PIN_SEL == 5) + #define RTE_SSP0_SSEL_PORT 0xF + #define RTE_SSP0_SSEL_BIT 1 + #define RTE_SSP0_SSEL_FUNC 2 + #define RTE_SSP0_SSEL_GPIO_FUNC 4 + #define RTE_SSP0_SSEL_GPIO_PORT 7 + #define RTE_SSP0_SSEL_GPIO_BIT 16 +#else + #error "Invalid SSP0 SSP0_SSEL Pin Configuration!" +#endif +#ifndef RTE_SSP0_SSEL_PIN_EN +#define RTE_SSP0_SSEL_PIN_EN 1 +#endif +// SSP0_SCK <0=>P3_0 <1=>P3_3 <2=>PF_0 +// Serial clock for SSP0 +#define RTE_SSP0_SCK_PIN_SEL 0 +#if (RTE_SSP0_SCK_PIN_SEL == 0) + #define RTE_SSP0_SCK_PORT 3 + #define RTE_SSP0_SCK_BIT 0 + #define RTE_SSP0_SCK_FUNC 4 +#elif (RTE_SSP0_SCK_PIN_SEL == 1) + #define RTE_SSP0_SCK_PORT 3 + #define RTE_SSP0_SCK_BIT 3 + #define RTE_SSP0_SCK_FUNC 2 +#elif (RTE_SSP0_SCK_PIN_SEL == 2) + #define RTE_SSP0_SCK_PORT 0xF + #define RTE_SSP0_SCK_BIT 0 + #define RTE_SSP0_SCK_FUNC 0 +#else + #error "Invalid SSP0 SSP0_SCK Pin Configuration!" +#endif +// SSP0_MISO <0=>Not used <1=>P1_1 <2=>P3_6 <3=>P3_7 <4=>P9_1 <5=>PF_2 +// Master In Slave Out for SSP0 +#define RTE_SSP0_MISO_PIN_SEL 0 +#if (RTE_SSP0_MISO_PIN_SEL == 0) + #define RTE_SSP0_MISO_PIN_EN 0 +#elif (RTE_SSP0_MISO_PIN_SEL == 1) + #define RTE_SSP0_MISO_PORT 1 + #define RTE_SSP0_MISO_BIT 1 + #define RTE_SSP0_MISO_FUNC 5 +#elif (RTE_SSP0_MISO_PIN_SEL == 2) + #define RTE_SSP0_MISO_PORT 3 + #define RTE_SSP0_MISO_BIT 6 + #define RTE_SSP0_MISO_FUNC 5 +#elif (RTE_SSP0_MISO_PIN_SEL == 3) + #define RTE_SSP0_MISO_PORT 3 + #define RTE_SSP0_MISO_BIT 7 + #define RTE_SSP0_MISO_FUNC 2 +#elif (RTE_SSP0_MISO_PIN_SEL == 4) + #define RTE_SSP0_MISO_PORT 9 + #define RTE_SSP0_MISO_BIT 1 + #define RTE_SSP0_MISO_FUNC 7 +#elif (RTE_SSP0_MISO_PIN_SEL == 5) + #define RTE_SSP0_MISO_PORT 0xF + #define RTE_SSP0_MISO_BIT 2 + #define RTE_SSP0_MISO_FUNC 2 +#else + #error "Invalid SSP0 SSP0_MISO Pin Configuration!" +#endif +#ifndef RTE_SSP0_MISO_PIN_EN + #define RTE_SSP0_MISO_PIN_EN 1 +#endif +// SSP0_MOSI <0=>Not used <1=>P1_2 <2=>P3_7 <3=>P3_8 <4=>P9_2 <5=>PF_3 +// Master Out Slave In for SSP0 +#define RTE_SSP0_MOSI_PIN_SEL 0 +#if (RTE_SSP0_MOSI_PIN_SEL == 0) + #define RTE_SSP0_MOSI_PIN_EN 0 +#elif (RTE_SSP0_MOSI_PIN_SEL == 1) + #define RTE_SSP0_MOSI_PORT 1 + #define RTE_SSP0_MOSI_BIT 2 + #define RTE_SSP0_MOSI_FUNC 5 +#elif (RTE_SSP0_MOSI_PIN_SEL == 2) + #define RTE_SSP0_MOSI_PORT 3 + #define RTE_SSP0_MOSI_BIT 7 + #define RTE_SSP0_MOSI_FUNC 5 +#elif (RTE_SSP0_MOSI_PIN_SEL == 3) + #define RTE_SSP0_MOSI_PORT 3 + #define RTE_SSP0_MOSI_BIT 8 + #define RTE_SSP0_MOSI_FUNC 2 +#elif (RTE_SSP0_MOSI_PIN_SEL == 4) + #define RTE_SSP0_MOSI_PORT 9 + #define RTE_SSP0_MOSI_BIT 2 + #define RTE_SSP0_MOSI_FUNC 7 +#elif (RTE_SSP0_MOSI_PIN_SEL == 5) + #define RTE_SSP0_MOSI_PORT 0xF + #define RTE_SSP0_MOSI_BIT 3 + #define RTE_SSP0_MOSI_FUNC 2 +#else + #error "Invalid SSP0 SSP0_MOSI Pin Configuration!" +#endif +#ifndef RTE_SSP0_MOSI_PIN_EN + #define RTE_SSP0_MOSI_PIN_EN 1 +#endif +// Pin Configuration + +// DMA +// Tx +// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// Peripheral <0=>10 (DMAMUXPER10) +// +#define RTE_SSP0_DMA_TX_EN 0 +#define RTE_SSP0_DMA_TX_CH 0 +#define RTE_SSP0_DMA_TX_PERI_ID 0 +#if (RTE_SSP0_DMA_TX_PERI_ID == 0) + #define RTE_SSP0_DMA_TX_PERI 10 + #define RTE_SSP0_DMA_TX_PERI_SEL 0 +#endif +// Rx +// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// Peripheral <0=>9 (DMAMUXPER9) +// +#define RTE_SSP0_DMA_RX_EN 0 +#define RTE_SSP0_DMA_RX_CH 1 +#define RTE_SSP0_DMA_RX_PERI_ID 0 +#if (RTE_SSP0_DMA_RX_PERI_ID == 0) + #define RTE_SSP0_DMA_RX_PERI 9 + #define RTE_SSP0_DMA_RX_PERI_SEL 0 +#endif +// DMA +// SSP0 (Synchronous Serial Port 0) [Driver_SPI0] + +// SSP1 (Synchronous Serial Port 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::Drivers:SPI +#define RTE_SSP1 0 + +// Pin Configuration +// SSP1_SSEL <0=>Not used <1=>P1_5 <2=>P1_20 <3=>PF_5 +// Slave Select for SSP1 +#define RTE_SSP1_SSEL_PIN_SEL 1 +#if (RTE_SSP1_SSEL_PIN_SEL == 0) + #define RTE_SSP1_SSEL_PIN_EN 0 +#elif (RTE_SSP1_SSEL_PIN_SEL == 1) + #define RTE_SSP1_SSEL_PORT 1 + #define RTE_SSP1_SSEL_BIT 5 + #define RTE_SSP1_SSEL_FUNC 5 + #define RTE_SSP1_SSEL_GPIO_FUNC 0 + #define RTE_SSP1_SSEL_GPIO_PORT 1 + #define RTE_SSP1_SSEL_GPIO_BIT 8 +#elif (RTE_SSP1_SSEL_PIN_SEL == 2) + #define RTE_SSP1_SSEL_PORT 1 + #define RTE_SSP1_SSEL_BIT 20 + #define RTE_SSP1_SSEL_FUNC 1 + #define RTE_SSP1_SSEL_GPIO_FUNC 0 + #define RTE_SSP1_SSEL_GPIO_PORT 0 + #define RTE_SSP1_SSEL_GPIO_BIT 15 +#elif (RTE_SSP1_SSEL_PIN_SEL == 3) + #define RTE_SSP1_SSEL_PORT 0xF + #define RTE_SSP1_SSEL_BIT 5 + #define RTE_SSP1_SSEL_FUNC 2 + #define RTE_SSP1_SSEL_GPIO_FUNC 4 + #define RTE_SSP1_SSEL_GPIO_PORT 7 + #define RTE_SSP1_SSEL_GPIO_BIT 19 +#else + #error "Invalid SSP1 SSP1_SSEL Pin Configuration!" +#endif +#ifndef RTE_SSP1_SSEL_PIN_EN +#define RTE_SSP1_SSEL_PIN_EN 1 +#endif +// SSP1_SCK <0=>P1_19 <1=>PF_4 <2=>CLK0 +// Serial clock for SSP1 +#define RTE_SSP1_SCK_PIN_SEL 0 +#if (RTE_SSP1_SCK_PIN_SEL == 0) + #define RTE_SSP1_SCK_PORT 1 + #define RTE_SSP1_SCK_BIT 19 + #define RTE_SSP1_SCK_FUNC 1 +#elif (RTE_SSP1_SCK_PIN_SEL == 1) + #define RTE_SSP1_SCK_PORT 0xF + #define RTE_SSP1_SCK_BIT 4 + #define RTE_SSP1_SCK_FUNC 0 +#elif (RTE_SSP1_SCK_PIN_SEL == 2) + #define RTE_SSP1_SCK_PORT 0x10 + #define RTE_SSP1_SCK_BIT 0 + #define RTE_SSP1_SCK_FUNC 6 +#else + #error "Invalid SSP1 SSP1_SCK Pin Configuration!" +#endif +// SSP1_MISO <0=>Not used <1=>P0_0 <2=>P1_3 <3=>PF_6 +// Master In Slave Out for SSP1 +#define RTE_SSP1_MISO_PIN_SEL 0 +#if (RTE_SSP1_MISO_PIN_SEL == 0) + #define RTE_SSP1_MISO_PIN_EN 0 +#elif (RTE_SSP1_MISO_PIN_SEL == 1) + #define RTE_SSP1_MISO_PORT 0 + #define RTE_SSP1_MISO_BIT 0 + #define RTE_SSP1_MISO_FUNC 1 +#elif (RTE_SSP1_MISO_PIN_SEL == 2) + #define RTE_SSP1_MISO_PORT 1 + #define RTE_SSP1_MISO_BIT 3 + #define RTE_SSP1_MISO_FUNC 5 +#elif (RTE_SSP1_MISO_PIN_SEL == 3) + #define RTE_SSP1_MISO_PORT 0xF + #define RTE_SSP1_MISO_BIT 6 + #define RTE_SSP1_MISO_FUNC 2 +#else + #error "Invalid SSP1 SSP1_MISO Pin Configuration!" +#endif +#ifndef RTE_SSP1_MISO_PIN_EN + #define RTE_SSP1_MISO_PIN_EN 1 +#endif +// SSP1_MOSI <0=>Not used <1=>P0_1 <2=>P1_4 <3=>PF_7 +// Master Out Slave In for SSP1 +#define RTE_SSP1_MOSI_PIN_SEL 0 +#if (RTE_SSP1_MOSI_PIN_SEL == 0) + #define RTE_SSP1_MOSI_PIN_EN 0 +#elif (RTE_SSP1_MOSI_PIN_SEL == 1) + #define RTE_SSP1_MOSI_PORT 0 + #define RTE_SSP1_MOSI_BIT 1 + #define RTE_SSP1_MOSI_FUNC 1 +#elif (RTE_SSP1_MOSI_PIN_SEL == 2) + #define RTE_SSP1_MOSI_PORT 1 + #define RTE_SSP1_MOSI_BIT 4 + #define RTE_SSP1_MOSI_FUNC 5 +#elif (RTE_SSP1_MOSI_PIN_SEL == 3) + #define RTE_SSP1_MOSI_PORT 0xF + #define RTE_SSP1_MOSI_BIT 7 + #define RTE_SSP1_MOSI_FUNC 2 +#else + #error "Invalid SSP1 SSP1_MOSI Pin Configuration!" +#endif +#ifndef RTE_SSP1_MOSI_PIN_EN + #define RTE_SSP1_MOSI_PIN_EN 1 +#endif +// Pin Configuration + +// DMA +// Tx +// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// Peripheral <0=>3 (DMAMUXPER3) <1=>5 (DMAMUXPER5) <2=>12 (DMAMUXPER12) <3=>14 (DMAMUXPER14) +// +#define RTE_SSP1_DMA_TX_EN 0 +#define RTE_SSP1_DMA_TX_CH 0 +#define RTE_SSP1_DMA_TX_PERI_ID 0 +#if (RTE_SSP1_DMA_TX_PERI_ID == 0) + #define RTE_SSP1_DMA_TX_PERI 3 + #define RTE_SSP1_DMA_TX_PERI_SEL 3 +#elif (RTE_SSP1_DMA_TX_PERI_ID == 1) + #define RTE_SSP1_DMA_TX_PERI 5 + #define RTE_SSP1_DMA_TX_PERI_SEL 2 +#elif (RTE_SSP1_DMA_TX_PERI_ID == 2) + #define RTE_SSP1_DMA_TX_PERI 12 + #define RTE_SSP1_DMA_TX_PERI_SEL 0 +#elif (RTE_SSP1_DMA_TX_PERI_ID == 3) + #define RTE_SSP1_DMA_TX_PERI 14 + #define RTE_SSP1_DMA_TX_PERI_SEL 2 +#endif +// Rx +// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// Peripheral <0=>4 (DMAMUXPER4) <1=>6 (DMAMUXPER6) <2=>11 (DMAMUXPER11) <3=>13 (DMAMUXPER13) +// +#define RTE_SSP1_DMA_RX_EN 0 +#define RTE_SSP1_DMA_RX_CH 1 +#define RTE_SSP1_DMA_RX_PERI_ID 0 +#if (RTE_SSP1_DMA_RX_PERI_ID == 0) + #define RTE_SSP1_DMA_RX_PERI 4 + #define RTE_SSP1_DMA_RX_PERI_SEL 3 +#elif (RTE_SSP1_DMA_RX_PERI_ID == 1) + #define RTE_SSP1_DMA_RX_PERI 6 + #define RTE_SSP1_DMA_RX_PERI_SEL 2 +#elif (RTE_SSP1_DMA_RX_PERI_ID == 2) + #define RTE_SSP1_DMA_RX_PERI 11 + #define RTE_SSP1_DMA_RX_PERI_SEL 0 +#elif (RTE_SSP1_DMA_RX_PERI_ID == 3) + #define RTE_SSP1_DMA_RX_PERI 13 + #define RTE_SSP1_DMA_RX_PERI_SEL 2 +#endif +// DMA +// SSP1 (Synchronous Serial Port 1) [Driver_SPI1] + +// SPI (Serial Peripheral Interface) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::Drivers:SPI +#define RTE_SPI 0 + +// Pin Configuration +// SPI_SSEL <0=>Not used <1=>P3_8 +// Slave Select for SPI +#define RTE_SPI_SSEL_PIN_SEL 0 +#if (RTE_SPI_SSEL_PIN_SEL == 0) +#define RTE_SPI_SSEL_PIN_EN 0 +#elif (RTE_SPI_SSEL_PIN_SEL == 1) + #define RTE_SPI_SSEL_PORT 3 + #define RTE_SPI_SSEL_BIT 8 + #define RTE_SPI_SSEL_FUNC 1 + #define RTE_SPI_SSEL_GPIO_FUNC 4 + #define RTE_SPI_SSEL_GPIO_PORT 5 + #define RTE_SPI_SSEL_GPIO_BIT 11 +#else + #error "Invalid SPI SPI_SSEL Pin Configuration!" +#endif +#ifndef RTE_SPI_SSEL_PIN_EN +#define RTE_SPI_SSEL_PIN_EN 1 +#endif +// SPI_SCK <0=>P3_3 +// Serial clock for SPI +#define RTE_SPI_SCK_PIN_SEL 0 +#if (RTE_SPI_SCK_PIN_SEL == 0) + #define RTE_SPI_SCK_PORT 3 + #define RTE_SPI_SCK_BIT 3 + #define RTE_SPI_SCK_FUNC 1 +#else + #error "Invalid SPI SPI_SCK Pin Configuration!" +#endif +// SPI_MISO <0=>Not used <1=>P3_6 +// Master In Slave Out for SPI +#define RTE_SPI_MISO_PIN_SEL 0 +#if (RTE_SPI_MISO_PIN_SEL == 0) + #define RTE_SPI_MISO_PIN_EN 0 +#elif (RTE_SPI_MISO_PIN_SEL == 1) + #define RTE_SPI_MISO_PORT 3 + #define RTE_SPI_MISO_BIT 6 + #define RTE_SPI_MISO_FUNC 1 +#else + #error "Invalid SPI SPI_MISO Pin Configuration!" +#endif +#ifndef RTE_SPI_MISO_PIN_EN + #define RTE_SPI_MISO_PIN_EN 1 +#endif +// SPI_MOSI <0=>Not used <1=>P3_7 +// Master Out Slave In for SPI +#define RTE_SPI_MOSI_PIN_SEL 0 +#if (RTE_SPI_MOSI_PIN_SEL == 0) + #define RTE_SPI_MOSI_PIN_EN 0 +#elif (RTE_SPI_MOSI_PIN_SEL == 1) + #define RTE_SPI_MOSI_PORT 3 + #define RTE_SPI_MOSI_BIT 7 + #define RTE_SPI_MOSI_FUNC 1 +#else + #error "Invalid SPI SPI_MOSI Pin Configuration!" +#endif +#ifndef RTE_SPI_MOSI_PIN_EN + #define RTE_SPI_MOSI_PIN_EN 1 +#endif +// Pin Configuration +// SPI (Serial Peripheral Interface) [Driver_SPI2] + +// I2S0 (Integrated Interchip Sound 0) [Driver_SAI0] +// Configuration settings for Driver_SAI0 in component ::Drivers:SAI +#define RTE_I2S0 0 + +// Pin Configuration +// I2S0_RX_SCK <0=>Not used <1=>P3_0 <2=>P6_0 <3=>PF_4 +// Receive clock for I2S0 +#define RTE_I2S0_RX_SCK_PIN_SEL 2 +#if (RTE_I2S0_RX_SCK_PIN_SEL == 0) +#define RTE_I2S0_RX_SCK_PIN_EN 0 +#elif (RTE_I2S0_RX_SCK_PIN_SEL == 1) + #define RTE_I2S0_RX_SCK_PORT 3 + #define RTE_I2S0_RX_SCK_BIT 0 + #define RTE_I2S0_RX_SCK_FUNC 0 +#elif (RTE_I2S0_RX_SCK_PIN_SEL == 2) + #define RTE_I2S0_RX_SCK_PORT 6 + #define RTE_I2S0_RX_SCK_BIT 0 + #define RTE_I2S0_RX_SCK_FUNC 4 +#elif (RTE_I2S0_RX_SCK_PIN_SEL == 3) + #define RTE_I2S0_RX_SCK_PORT 0xF + #define RTE_I2S0_RX_SCK_BIT 4 + #define RTE_I2S0_RX_SCK_FUNC 7 +#else + #error "Invalid I2S0 I2S0_RX_SCK Pin Configuration!" +#endif +#ifndef RTE_I2S0_RX_SCK_PIN_EN +#define RTE_I2S0_RX_SCK_PIN_EN 1 +#endif +// I2S0_RX_WS <0=>Not used <1=>P3_1 <2=>P6_1 +// Receive word select for I2S0 +#define RTE_I2S0_RX_WS_PIN_SEL 2 +#if (RTE_I2S0_RX_WS_PIN_SEL == 0) +#define RTE_I2S0_RX_WS_PIN_EN 0 +#elif (RTE_I2S0_RX_WS_PIN_SEL == 1) + #define RTE_I2S0_RX_WS_PORT 3 + #define RTE_I2S0_RX_WS_BIT 1 + #define RTE_I2S0_RX_WS_FUNC 1 +#elif (RTE_I2S0_RX_WS_PIN_SEL == 2) + #define RTE_I2S0_RX_WS_PORT 6 + #define RTE_I2S0_RX_WS_BIT 1 + #define RTE_I2S0_RX_WS_FUNC 3 +#else + #error "Invalid I2S0 I2S0_RX_WS Pin Configuration!" +#endif +#ifndef RTE_I2S0_RX_WS_PIN_EN +#define RTE_I2S0_RX_WS_PIN_EN 1 +#endif +// I2S0_RX_SDA <0=>Not used <1=>P3_2 <2=>P6_2 +// Receive master clock for I2S0 +#define RTE_I2S0_RX_SDA_PIN_SEL 2 +#if (RTE_I2S0_RX_SDA_PIN_SEL == 0) +#define RTE_I2S0_RX_SDA_PIN_EN 0 +#elif (RTE_I2S0_RX_SDA_PIN_SEL == 1) + #define RTE_I2S0_RX_SDA_PORT 3 + #define RTE_I2S0_RX_SDA_BIT 2 + #define RTE_I2S0_RX_SDA_FUNC 1 +#elif (RTE_I2S0_RX_SDA_PIN_SEL == 2) + #define RTE_I2S0_RX_SDA_PORT 6 + #define RTE_I2S0_RX_SDA_BIT 2 + #define RTE_I2S0_RX_SDA_FUNC 3 +#else + #error "Invalid I2S0 I2S0_RX_SDA Pin Configuration!" +#endif +#ifndef RTE_I2S0_RX_SDA_PIN_EN +#define RTE_I2S0_RX_SDA_PIN_EN 1 +#endif +// I2S0_RX_MCLK <0=>Not used <1=>P1_19 <2=>P3_0 <3=>P6_0 +// Receive master clock for I2S0 +#define RTE_I2S0_RX_MCLK_PIN_SEL 0 +#if (RTE_I2S0_RX_MCLK_PIN_SEL == 0) +#define RTE_I2S0_RX_MCLK_PIN_EN 0 +#elif (RTE_I2S0_RX_MCLK_PIN_SEL == 1) + #define RTE_I2S0_RX_MCLK_PORT 1 + #define RTE_I2S0_RX_MCLK_BIT 19 + #define RTE_I2S0_RX_MCLK_FUNC 6 +#elif (RTE_I2S0_RX_MCLK_PIN_SEL == 2) + #define RTE_I2S0_RX_MCLK_PORT 3 + #define RTE_I2S0_RX_MCLK_BIT 0 + #define RTE_I2S0_RX_MCLK_FUNC 1 +#elif (RTE_I2S0_RX_MCLK_PIN_SEL == 3) + #define RTE_I2S0_RX_MCLK_PORT 6 + #define RTE_I2S0_RX_MCLK_BIT 0 + #define RTE_I2S0_RX_MCLK_FUNC 1 +#else + #error "Invalid I2S0 I2S0_RX_MCLK Pin Configuration!" +#endif +#ifndef RTE_I2S0_RX_MCLK_PIN_EN +#define RTE_I2S0_RX_MCLK_PIN_EN 1 +#endif +// I2S0_TX_SCK <0=>Not used <1=>P3_0 <2=>P4_7 +// Transmit clock for I2S0 +#define RTE_I2S0_TX_SCK_PIN_SEL 1 +#if (RTE_I2S0_TX_SCK_PIN_SEL == 0) +#define RTE_I2S0_TX_SCK_PIN_EN 0 +#elif (RTE_I2S0_TX_SCK_PIN_SEL == 1) + #define RTE_I2S0_TX_SCK_PORT 3 + #define RTE_I2S0_TX_SCK_BIT 0 + #define RTE_I2S0_TX_SCK_FUNC 2 +#elif (RTE_I2S0_TX_SCK_PIN_SEL == 2) + #define RTE_I2S0_TX_SCK_PORT 4 + #define RTE_I2S0_TX_SCK_BIT 7 + #define RTE_I2S0_TX_SCK_FUNC 7 +#else + #error "Invalid I2S0 I2S0_TX_SCK Pin Configuration!" +#endif +#ifndef RTE_I2S0_TX_SCK_PIN_EN +#define RTE_I2S0_TX_SCK_PIN_EN 1 +#endif +// I2S0_TX_WS <0=>Not used <1=>P0_0 <2=>P3_1 <3=>P3_4 <4=>P7_1 <5=>P9_1 <6=>PC_13 +// Transmit word select for I2S0 +#define RTE_I2S0_TX_WS_PIN_SEL 4 +#if (RTE_I2S0_TX_WS_PIN_SEL == 0) +#define RTE_I2S0_TX_WS_PIN_EN 0 +#elif (RTE_I2S0_TX_WS_PIN_SEL == 1) + #define RTE_I2S0_TX_WS_PORT 0 + #define RTE_I2S0_TX_WS_BIT 0 + #define RTE_I2S0_TX_WS_FUNC 6 +#elif (RTE_I2S0_TX_WS_PIN_SEL == 2) + #define RTE_I2S0_TX_WS_PORT 3 + #define RTE_I2S0_TX_WS_BIT 1 + #define RTE_I2S0_TX_WS_FUNC 0 +#elif (RTE_I2S0_TX_WS_PIN_SEL == 3) + #define RTE_I2S0_TX_WS_PORT 3 + #define RTE_I2S0_TX_WS_BIT 4 + #define RTE_I2S0_TX_WS_FUNC 5 +#elif (RTE_I2S0_TX_WS_PIN_SEL == 4) + #define RTE_I2S0_TX_WS_PORT 7 + #define RTE_I2S0_TX_WS_BIT 1 + #define RTE_I2S0_TX_WS_FUNC 2 +#elif (RTE_I2S0_TX_WS_PIN_SEL == 5) + #define RTE_I2S0_TX_WS_PORT 9 + #define RTE_I2S0_TX_WS_BIT 1 + #define RTE_I2S0_TX_WS_FUNC 4 +#elif (RTE_I2S0_TX_WS_PIN_SEL == 6) + #define RTE_I2S0_TX_WS_PORT 0xC + #define RTE_I2S0_TX_WS_BIT 13 + #define RTE_I2S0_TX_WS_FUNC 6 +#else + #error "Invalid I2S0 I2S0_TX_WS Pin Configuration!" +#endif +#ifndef RTE_I2S0_TX_WS_PIN_EN +#define RTE_I2S0_TX_WS_PIN_EN 1 +#endif +// I2S0_TX_SDA <0=>Not used <1=>P3_2 <2=>P3_5 <3=>P7_2 <4=>P9_2 <5=>PC_12 +// Transmit data for I2S0 +#define RTE_I2S0_TX_SDA_PIN_SEL 3 +#if (RTE_I2S0_TX_SDA_PIN_SEL == 0) +#define RTE_I2S0_TX_SDA_PIN_EN 0 +#elif (RTE_I2S0_TX_SDA_PIN_SEL == 1) + #define RTE_I2S0_TX_SDA_PORT 3 + #define RTE_I2S0_TX_SDA_BIT 2 + #define RTE_I2S0_TX_SDA_FUNC 0 +#elif (RTE_I2S0_TX_SDA_PIN_SEL == 2) + #define RTE_I2S0_TX_SDA_PORT 3 + #define RTE_I2S0_TX_SDA_BIT 5 + #define RTE_I2S0_TX_SDA_FUNC 5 +#elif (RTE_I2S0_TX_SDA_PIN_SEL == 3) + #define RTE_I2S0_TX_SDA_PORT 7 + #define RTE_I2S0_TX_SDA_BIT 2 + #define RTE_I2S0_TX_SDA_FUNC 2 +#elif (RTE_I2S0_TX_SDA_PIN_SEL == 4) + #define RTE_I2S0_TX_SDA_PORT 9 + #define RTE_I2S0_TX_SDA_BIT 2 + #define RTE_I2S0_TX_SDA_FUNC 4 +#elif (RTE_I2S0_TX_SDA_PIN_SEL == 5) + #define RTE_I2S0_TX_SDA_PORT 0xC + #define RTE_I2S0_TX_SDA_BIT 12 + #define RTE_I2S0_TX_SDA_FUNC 6 +#else + #error "Invalid I2S0 I2S0_TX_SDA Pin Configuration!" +#endif +#ifndef RTE_I2S0_TX_SDA_PIN_EN +#define RTE_I2S0_TX_SDA_PIN_EN 1 +#endif +// I2S0_TX_MCLK <0=>Not used <1=>P3_0 <2=>P3_3 <3=>PF_4 <4=>CLK2 +// Transmit master clock for I2S0 +#define RTE_I2S0_TX_MCLK_PIN_SEL 2 +#if (RTE_I2S0_TX_MCLK_PIN_SEL == 0) +#define RTE_I2S0_TX_MCLK_PIN_EN 0 +#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 1) + #define RTE_I2S0_TX_MCLK_PORT 3 + #define RTE_I2S0_TX_MCLK_BIT 0 + #define RTE_I2S0_TX_MCLK_FUNC 3 +#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 2) + #define RTE_I2S0_TX_MCLK_PORT 3 + #define RTE_I2S0_TX_MCLK_BIT 3 + #define RTE_I2S0_TX_MCLK_FUNC 6 +#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 3) + #define RTE_I2S0_TX_MCLK_PORT 0xf + #define RTE_I2S0_TX_MCLK_BIT 4 + #define RTE_I2S0_TX_MCLK_FUNC 6 +#elif (RTE_I2S0_TX_MCLK_PIN_SEL == 4) + #define RTE_I2S0_TX_MCLK_PORT 0x10 + #define RTE_I2S0_TX_MCLK_BIT 2 + #define RTE_I2S0_TX_MCLK_FUNC 6 +#else + #error "Invalid I2S0 I2S0_TX_MCLK Pin Configuration!" +#endif +#ifndef RTE_I2S0_TX_MCLK_PIN_EN +#define RTE_I2S0_TX_MCLK_PIN_EN 1 +#endif +// Pin Configuration + +// DMA +// Tx +// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// Peripheral <0=>9 (DMAMUXPER9) +// +#define RTE_I2S0_DMA_TX_EN 0 +#define RTE_I2S0_DMA_TX_CH 0 +#define RTE_I2S0_DMA_TX_PERI_ID 0 +#if (RTE_I2S0_DMA_TX_PERI_ID == 0) + #define RTE_I2S0_DMA_TX_PERI 9 + #define RTE_I2S0_DMA_TX_PERI_SEL 1 +#endif +// Rx +// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// Peripheral <0=>10 (DMAMUXPER10) +// +#define RTE_I2S0_DMA_RX_EN 0 +#define RTE_I2S0_DMA_RX_CH 1 +#define RTE_I2S0_DMA_RX_PERI_ID 0 +#if (RTE_I2S0_DMA_RX_PERI_ID == 0) + #define RTE_I2S0_DMA_RX_PERI 10 + #define RTE_I2S0_DMA_RX_PERI_SEL 1 +#endif +// DMA +// I2S0 (Integrated Interchip Sound 0) [Driver_SAI0] + +// I2S1 (Integrated Interchip Sound 1) [Driver_SAI1] +// Configuration settings for Driver_I2S1 in component ::Drivers:SAI +#define RTE_I2S1 0 + +// Pin Configuration +// I2S1_RX_SCK <0=>Not used <1=>CLK2 <2=>CLK3 +// Receive clock for I2S1 +#define RTE_I2S1_RX_SCK_PIN_SEL 0 +#if (RTE_I2S1_RX_SCK_PIN_SEL == 0) +#define RTE_I2S1_RX_SCK_PIN_EN 0 +#elif (RTE_I2S1_RX_SCK_PIN_SEL == 1) + #define RTE_I2S1_RX_SCK_PORT 0x10 + #define RTE_I2S1_RX_SCK_BIT 2 + #define RTE_I2S1_RX_SCK_FUNC 7 +#elif (RTE_I2S1_RX_SCK_PIN_SEL == 2) + #define RTE_I2S1_RX_SCK_PORT 0x10 + #define RTE_I2S1_RX_SCK_BIT 3 + #define RTE_I2S1_RX_SCK_FUNC 7 +#else + #error "Invalid I2S1 I2S1_RX_SCK Pin Configuration!" +#endif +#ifndef RTE_I2S1_RX_SCK_PIN_EN +#define RTE_I2S1_RX_SCK_PIN_EN 1 +#endif +// I2S1_RX_WS <0=>Not used <1=>P3_5 +// Receive word select for I2S1 +#define RTE_I2S1_RX_WS_PIN_SEL 0 +#if (RTE_I2S1_RX_WS_PIN_SEL == 0) +#define RTE_I2S1_RX_WS_PIN_EN 0 +#elif (RTE_I2S1_RX_WS_PIN_SEL == 1) + #define RTE_I2S1_RX_WS_PORT 3 + #define RTE_I2S1_RX_WS_BIT 5 + #define RTE_I2S1_RX_WS_FUNC 6 +#else + #error "Invalid I2S1 I2S1_RX_WS Pin Configuration!" +#endif +#ifndef RTE_I2S1_RX_WS_PIN_EN +#define RTE_I2S1_RX_WS_PIN_EN 1 +#endif +// I2S1_RX_SDA <0=>Not used <1=>P3_4 +// Receive master clock for I2S1 +#define RTE_I2S1_RX_SDA_PIN_SEL 0 +#if (RTE_I2S1_RX_SDA_PIN_SEL == 0) +#define RTE_I2S1_RX_SDA_PIN_EN 0 +#elif (RTE_I2S1_RX_SDA_PIN_SEL == 1) + #define RTE_I2S1_RX_SDA_PORT 3 + #define RTE_I2S1_RX_SDA_BIT 4 + #define RTE_I2S1_RX_SDA_FUNC 6 +#else + #error "Invalid I2S1 I2S1_RX_SDA Pin Configuration!" +#endif +#ifndef RTE_I2S1_RX_SDA_PIN_EN +#define RTE_I2S1_RX_SDA_PIN_EN 1 +#endif +// I2S1_RX_MCLK <0=>Not used <1=>PA_0 +// Receive master clock for I2S1 +#define RTE_I2S1_RX_MCLK_PIN_SEL 0 +#if (RTE_I2S1_RX_MCLK_PIN_SEL == 0) +#define RTE_I2S1_RX_MCLK_PIN_EN 0 +#elif (RTE_I2S1_RX_MCLK_PIN_SEL == 1) + #define RTE_I2S1_RX_MCLK_PORT 0x0A + #define RTE_I2S1_RX_MCLK_BIT 0 + #define RTE_I2S1_RX_MCLK_FUNC 5 +#else + #error "Invalid I2S1 I2S1_RX_MCLK Pin Configuration!" +#endif +#ifndef RTE_I2S1_RX_MCLK_PIN_EN +#define RTE_I2S1_RX_MCLK_PIN_EN 1 +#endif +// I2S1_TX_SCK <0=>Not used <1=>P1_19 <2=>P3_3 <3=>P4_7 +// Transmit clock for I2S1 +#define RTE_I2S1_TX_SCK_PIN_SEL 0 +#if (RTE_I2S1_TX_SCK_PIN_SEL == 0) +#define RTE_I2S1_TX_SCK_PIN_EN 0 +#elif (RTE_I2S1_TX_SCK_PIN_SEL == 1) + #define RTE_I2S1_TX_SCK_PORT 1 + #define RTE_I2S1_TX_SCK_BIT 19 + #define RTE_I2S1_TX_SCK_FUNC 7 +#elif (RTE_I2S1_TX_SCK_PIN_SEL == 2) + #define RTE_I2S1_TX_SCK_PORT 3 + #define RTE_I2S1_TX_SCK_BIT 3 + #define RTE_I2S1_TX_SCK_FUNC 7 +#elif (RTE_I2S1_TX_SCK_PIN_SEL == 3) + #define RTE_I2S1_TX_SCK_PORT 4 + #define RTE_I2S1_TX_SCK_BIT 7 + #define RTE_I2S1_TX_SCK_FUNC 6 +#else + #error "Invalid I2S1 I2S1_TX_SCK Pin Configuration!" +#endif +#ifndef RTE_I2S1_TX_SCK_PIN_EN +#define RTE_I2S1_TX_SCK_PIN_EN 1 +#endif +// I2S1_TX_WS <0=>Not used <1=>P0_0 <2=>PF_7 +// Transmit word select for I2S1 +#define RTE_I2S1_TX_WS_PIN_SEL 0 +#if (RTE_I2S1_TX_WS_PIN_SEL == 0) +#define RTE_I2S1_TX_WS_PIN_EN 0 +#elif (RTE_I2S1_TX_WS_PIN_SEL == 1) + #define RTE_I2S1_TX_WS_PORT 0 + #define RTE_I2S1_TX_WS_BIT 0 + #define RTE_I2S1_TX_WS_FUNC 7 +#elif (RTE_I2S1_TX_WS_PIN_SEL == 2) + #define RTE_I2S1_TX_WS_PORT 0x0F + #define RTE_I2S1_TX_WS_BIT 7 + #define RTE_I2S1_TX_WS_FUNC 7 +#else + #error "Invalid I2S1 I2S1_TX_WS Pin Configuration!" +#endif +#ifndef RTE_I2S1_TX_WS_PIN_EN +#define RTE_I2S1_TX_WS_PIN_EN 1 +#endif +// I2S1_TX_SDA <0=>Not used <1=>P0_1 <2=>PF_6 +// Transmit data for I2S +#define RTE_I2S1_TX_SDA_PIN_SEL 0 +#if (RTE_I2S1_TX_SDA_PIN_SEL == 0) +#define RTE_I2S1_TX_SDA_PIN_EN 0 +#elif (RTE_I2S1_TX_SDA_PIN_SEL == 1) + #define RTE_I2S1_TX_SDA_PORT 0 + #define RTE_I2S1_TX_SDA_BIT 1 + #define RTE_I2S1_TX_SDA_FUNC 7 +#elif (RTE_I2S1_TX_SDA_PIN_SEL == 2) + #define RTE_I2S1_TX_SDA_PORT 0x0F + #define RTE_I2S1_TX_SDA_BIT 6 + #define RTE_I2S1_TX_SDA_FUNC 7 +#else + #error "Invalid I2S1 I2S1_TX_SDA Pin Configuration!" +#endif +#ifndef RTE_I2S1_TX_SDA_PIN_EN +#define RTE_I2S1_TX_SDA_PIN_EN 1 +#endif +// I2S1_TX_MCLK <0=>Not used <1=>P8_8 <2=>PF_0 <3=>CLK1 +// Transmit master clock for I2S1 +#define RTE_I2S1_TX_MCLK_PIN_SEL 0 +#if (RTE_I2S1_TX_MCLK_PIN_SEL == 0) +#define RTE_I2S1_TX_MCLK_PIN_EN 0 +#elif (RTE_I2S1_TX_MCLK_PIN_SEL == 1) + #define RTE_I2S1_TX_MCLK_PORT 8 + #define RTE_I2S1_TX_MCLK_BIT 8 + #define RTE_I2S1_TX_MCLK_FUNC 7 +#elif (RTE_I2S1_TX_MCLK_PIN_SEL == 2) + #define RTE_I2S1_TX_MCLK_PORT 0x0F + #define RTE_I2S1_TX_MCLK_BIT 0 + #define RTE_I2S1_TX_MCLK_FUNC 7 +#elif (RTE_I2S1_TX_MCLK_PIN_SEL == 3) + #define RTE_I2S1_TX_MCLK_PORT 0x10 + #define RTE_I2S1_TX_MCLK_BIT 1 + #define RTE_I2S1_TX_MCLK_FUNC 7 +#else + #error "Invalid I2S1 I2S1_TX_MCLK Pin Configuration!" +#endif +#ifndef RTE_I2S1_TX_MCLK_PIN_EN +#define RTE_I2S1_TX_MCLK_PIN_EN 1 +#endif +// Pin Configuration + +// DMA +// Tx +// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// Peripheral <0=>3 (DMAMUXPER3) +// +#define RTE_I2S1_DMA_TX_EN 0 +#define RTE_I2S1_DMA_TX_CH 0 +#define RTE_I2S1_DMA_TX_PERI_ID 0 +#if (RTE_I2S1_DMA_TX_PERI_ID == 0) + #define RTE_I2S1_DMA_TX_PERI 3 + #define RTE_I2S1_DMA_TX_PERI_SEL 2 +#endif +// Rx +// Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// Peripheral <0=>4 (DMAMUXPER4) +// +#define RTE_I2S1_DMA_RX_EN 0 +#define RTE_I2S1_DMA_RX_CH 1 +#define RTE_I2S1_DMA_RX_PERI_ID 0 +#if (RTE_I2S1_DMA_RX_PERI_ID == 0) + #define RTE_I2S1_DMA_RX_PERI 4 + #define RTE_I2S1_DMA_RX_PERI_SEL 2 +#endif +// DMA +// I2S1 (Integrated Interchip Sound 1) [Driver_SAI1] + +// CAN0 Controller [Driver_CAN0] +// Configuration settings for Driver_CAN0 in component ::Drivers:CAN +#define RTE_CAN_CAN0 0 + +// Pin Configuration +// CAN0_RD <0=>Not used <1=>P3_1 <2=>PE_2 +// CAN0 receiver input. +#define RTE_CAN0_RD_ID 0 +#if (RTE_CAN0_RD_ID == 0) + #define RTE_CAN0_RD_PIN_EN 0 +#elif (RTE_CAN0_RD_ID == 1) + #define RTE_CAN0_RD_PORT 3 + #define RTE_CAN0_RD_BIT 1 + #define RTE_CAN0_RD_FUNC 2 +#elif (RTE_CAN0_RD_ID == 2) + #define RTE_CAN0_RD_PORT 0xE + #define RTE_CAN0_RD_BIT 2 + #define RTE_CAN0_RD_FUNC 1 +#else + #error "Invalid RTE_CAN0_RD Pin Configuration!" +#endif +#ifndef RTE_CAN0_RD_PIN_EN + #define RTE_CAN0_RD_PIN_EN 1 +#endif +// CAN0_TD <0=>Not used <1=>P3_2 <2=>PE_3 +// CAN0 transmitter output. +#define RTE_CAN0_TD_ID 0 +#if (RTE_CAN0_TD_ID == 0) + #define RTE_CAN0_TD_PIN_EN 0 +#elif (RTE_CAN0_TD_ID == 1) + #define RTE_CAN0_TD_PORT 3 + #define RTE_CAN0_TD_BIT 2 + #define RTE_CAN0_TD_FUNC 2 +#elif (RTE_CAN0_TD_ID == 2) + #define RTE_CAN0_TD_PORT 0xE + #define RTE_CAN0_TD_BIT 3 + #define RTE_CAN0_TD_FUNC 1 +#else + #error "Invalid RTE_CAN0_TD Pin Configuration!" +#endif +#ifndef RTE_CAN0_TD_PIN_EN + #define RTE_CAN0_TD_PIN_EN 1 +#endif +// Pin Configuration +// CAN0 Controller [Driver_CAN0] + +// CAN1 Controller [Driver_CAN1] +// Configuration settings for Driver_CAN1 in component ::Drivers:CAN +#define RTE_CAN_CAN1 0 + +// Pin Configuration +// CAN1_RD <0=>Not used <1=>P1_18 <2=>P4_9 <3=>PE_1 +// CAN1 receiver input. +#define RTE_CAN1_RD_ID 0 +#if (RTE_CAN1_RD_ID == 0) + #define RTE_CAN1_RD_PIN_EN 0 +#elif (RTE_CAN1_RD_ID == 1) + #define RTE_CAN1_RD_PORT 1 + #define RTE_CAN1_RD_BIT 18 + #define RTE_CAN1_RD_FUNC 5 +#elif (RTE_CAN1_RD_ID == 2) + #define RTE_CAN1_RD_PORT 4 + #define RTE_CAN1_RD_BIT 9 + #define RTE_CAN1_RD_FUNC 6 +#elif (RTE_CAN1_RD_ID == 3) + #define RTE_CAN1_RD_PORT 0xE + #define RTE_CAN1_RD_BIT 1 + #define RTE_CAN1_RD_FUNC 5 +#else + #error "Invalid RTE_CAN1_RD Pin Configuration!" +#endif +#ifndef RTE_CAN1_RD_PIN_EN + #define RTE_CAN1_RD_PIN_EN 1 +#endif +// CAN1_TD <0=>Not used <1=>P1_17 <2=>P4_8 <3=>PE_0 +// CAN1 transmitter output. +#define RTE_CAN1_TD_ID 0 +#if (RTE_CAN1_TD_ID == 0) + #define RTE_CAN1_TD_PIN_EN 0 +#elif (RTE_CAN1_TD_ID == 1) + #define RTE_CAN1_TD_PORT 1 + #define RTE_CAN1_TD_BIT 17 + #define RTE_CAN1_TD_FUNC 5 +#elif (RTE_CAN1_TD_ID == 2) + #define RTE_CAN1_TD_PORT 4 + #define RTE_CAN1_TD_BIT 8 + #define RTE_CAN1_TD_FUNC 6 +#elif (RTE_CAN1_TD_ID == 3) + #define RTE_CAN1_TD_PORT 0xE + #define RTE_CAN1_TD_BIT 0 + #define RTE_CAN1_TD_FUNC 5 +#else + #error "Invalid RTE_CAN1_TD Pin Configuration!" +#endif +#ifndef RTE_CAN1_TD_PIN_EN + #define RTE_CAN1_TD_PIN_EN 1 +#endif +// Pin Configuration +// CAN1 Controller [Driver_CAN1] + + +#endif /* __RTE_DEVICE_H */ From 2998341783a8f2fb1fea2601792c4ea541ad6d50 Mon Sep 17 00:00:00 2001 From: Adrian Negreanu Date: Tue, 16 Jun 2020 20:35:29 +0300 Subject: [PATCH 523/617] lpc4322 (SWO): define the SWO gpio ports Signed-off-by: Adrian Negreanu --- source/hic_hal/nxp/lpc4322/IO_Config.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/source/hic_hal/nxp/lpc4322/IO_Config.h b/source/hic_hal/nxp/lpc4322/IO_Config.h index a5ac392b1..98a2c451b 100644 --- a/source/hic_hal/nxp/lpc4322/IO_Config.h +++ b/source/hic_hal/nxp/lpc4322/IO_Config.h @@ -42,6 +42,11 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC4322); #define PIN_SWDIO_IN_BIT 9 #define PIN_SWDIO (1< Date: Sat, 2 May 2020 10:19:09 +0300 Subject: [PATCH 524/617] lpc4322 (SWO): configure the SWO GPIO port as input --- source/hic_hal/nxp/lpc4322/RTE_Device.h | 2 +- source/hic_hal/nxp/lpc4322/gpio.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/source/hic_hal/nxp/lpc4322/RTE_Device.h b/source/hic_hal/nxp/lpc4322/RTE_Device.h index e3593c246..11247f824 100644 --- a/source/hic_hal/nxp/lpc4322/RTE_Device.h +++ b/source/hic_hal/nxp/lpc4322/RTE_Device.h @@ -1161,7 +1161,7 @@ #endif // RX <0=>Not used <1=>P1_14 <2=>P3_5 <3=>P5_7 <4=>PC_14 <5=>PE_12 // UART1 Serial Input pin -#define RTE_UART1_RX_ID 0 +#define RTE_UART1_RX_ID 1 #if (RTE_UART1_RX_ID == 0) #define RTE_UART1_RX_PIN_EN 0 #elif (RTE_UART1_RX_ID == 1) diff --git a/source/hic_hal/nxp/lpc4322/gpio.c b/source/hic_hal/nxp/lpc4322/gpio.c index 953297227..474d3391d 100644 --- a/source/hic_hal/nxp/lpc4322/gpio.c +++ b/source/hic_hal/nxp/lpc4322/gpio.c @@ -75,6 +75,11 @@ void gpio_init(void) LPC_SCU->PINTSEL0 &= ~0xff; LPC_SCU->PINTSEL0 |= (PORT_nRESET << 5) | (PIN_nRESET_IN_BIT); +#if (SWO_UART != 0) + /* Configure: SWO as input */ + LPC_GPIO_PORT->DIR[PORT_SWO] &= ~(1 << PIN_SWO_IN_BIT); +#endif + busy_wait(10000); } From dac348d19af5cdbc45d7317b47cdf2085752cd8d Mon Sep 17 00:00:00 2001 From: Adrian Negreanu Date: Tue, 16 Jun 2020 19:59:38 +0300 Subject: [PATCH 525/617] lpc4322 (SWO): make SWO_UART configurable This way, one can set SWO_UART from the target's yaml. Signed-off-by: Adrian Negreanu --- source/hic_hal/nxp/lpc4322/DAP_config.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/source/hic_hal/nxp/lpc4322/DAP_config.h b/source/hic_hal/nxp/lpc4322/DAP_config.h index d010aa5d4..34c7b90f0 100644 --- a/source/hic_hal/nxp/lpc4322/DAP_config.h +++ b/source/hic_hal/nxp/lpc4322/DAP_config.h @@ -101,7 +101,9 @@ typedef unsigned int BOOL; /// Indicate that UART Serial Wire Output (SWO) trace is available. /// This information is returned by the command \ref DAP_Info as part of Capabilities. +#if !defined(SWO_UART) #define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available +#endif /// USART Driver instance number for the UART SWO. #define SWO_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#). From d2992f473cbb85b665e9b89231080bc058e0815c Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 20 Nov 2021 00:25:25 -0600 Subject: [PATCH 526/617] lpc4322 (SWO): configure UART1 for SWO, enable SWO for LPC55S69-EVK board --- records/board/lpc55S69xpresso.yaml | 2 ++ records/hic_hal/lpc4322.yaml | 2 ++ source/hic_hal/nxp/lpc4322/DAP_config.h | 4 ++-- source/hic_hal/nxp/lpc4322/RTE_Device.h | 20 ++++++++++---------- 4 files changed, 16 insertions(+), 12 deletions(-) diff --git a/records/board/lpc55S69xpresso.yaml b/records/board/lpc55S69xpresso.yaml index 43ef64720..8b0714dd8 100644 --- a/records/board/lpc55S69xpresso.yaml +++ b/records/board/lpc55S69xpresso.yaml @@ -1,4 +1,6 @@ common: + macros: + - SWO_UART=1 sources: board: - source/board/lpc55S69xpresso.c diff --git a/records/hic_hal/lpc4322.yaml b/records/hic_hal/lpc4322.yaml index 29c0023ba..f21e22093 100644 --- a/records/hic_hal/lpc4322.yaml +++ b/records/hic_hal/lpc4322.yaml @@ -11,9 +11,11 @@ common: - OS_CLOCK=96000000 includes: - source/hic_hal/nxp/lpc4322 + - source/hic_hal/nxp/lpc4322/RTE_Driver sources: hic_hal: - source/hic_hal/nxp/lpc4322 + - source/hic_hal/nxp/lpc4322/RTE_Driver tool_specific: uvision: diff --git a/source/hic_hal/nxp/lpc4322/DAP_config.h b/source/hic_hal/nxp/lpc4322/DAP_config.h index 34c7b90f0..62c9043b4 100644 --- a/source/hic_hal/nxp/lpc4322/DAP_config.h +++ b/source/hic_hal/nxp/lpc4322/DAP_config.h @@ -97,7 +97,7 @@ typedef unsigned int BOOL; /// This configuration settings is used to optimize the communication performance with the /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB. -#define DAP_PACKET_COUNT 8 ///< Buffers: 64 = Full-Speed, 4 = High-Speed. +#define DAP_PACKET_COUNT 8 ///< Buffers: 64 = Full-Speed, 4 = High-Speed. /// Indicate that UART Serial Wire Output (SWO) trace is available. /// This information is returned by the command \ref DAP_Info as part of Capabilities. @@ -106,7 +106,7 @@ typedef unsigned int BOOL; #endif /// USART Driver instance number for the UART SWO. -#define SWO_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#). +#define SWO_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#). /// Maximum SWO UART Baudrate #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz diff --git a/source/hic_hal/nxp/lpc4322/RTE_Device.h b/source/hic_hal/nxp/lpc4322/RTE_Device.h index 11247f824..48bdb7fdc 100644 --- a/source/hic_hal/nxp/lpc4322/RTE_Device.h +++ b/source/hic_hal/nxp/lpc4322/RTE_Device.h @@ -1,5 +1,5 @@ -/* -------------------------------------------------------------------------- - * Copyright (c) 2013-2016 Arm Limited (or its affiliates). All +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 Arm Limited (or its affiliates). All * rights reserved. * * SPDX-License-Identifier: Apache-2.0 @@ -1125,12 +1125,12 @@ // USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] // UART1 (Universal asynchronous receiver transmitter) [Driver_USART1] -#define RTE_UART1 0 +#define RTE_UART1 1 // Pin Configuration // TX <0=>Not used <1=>P1_13 <2=>P3_4 <3=>P5_6 <4=>PC_13 <5=>PE_11 // UART0 Serial Output pin -#define RTE_UART1_TX_ID 2 +#define RTE_UART1_TX_ID 0 #if (RTE_UART1_TX_ID == 0) #define RTE_UART1_TX_PIN_EN 0 #elif (RTE_UART1_TX_ID == 1) @@ -1193,7 +1193,7 @@ // Modem Lines // CTS <0=>Not used <1=>P1_11 <2=>P5_4 <3=>PC_2 <4=>PE_7 -#define RTE_UART1_CTS_ID 1 +#define RTE_UART1_CTS_ID 0 #if (RTE_UART1_CTS_ID == 0) #define RTE_UART1_CTS_PIN_EN 0 #elif (RTE_UART1_CTS_ID == 1) @@ -1219,7 +1219,7 @@ #define RTE_UART1_CTS_PIN_EN 1 #endif // RTS <0=>Not used <1=>P1_9 <2=>P5_2 <3=>PC_3 <4=>PE_5 -#define RTE_UART1_RTS_ID 1 +#define RTE_UART1_RTS_ID 0 #if (RTE_UART1_RTS_ID == 0) #define RTE_UART1_RTS_PIN_EN 0 #elif (RTE_UART1_RTS_ID == 1) @@ -1245,7 +1245,7 @@ #define RTE_UART1_RTS_PIN_EN 1 #endif // DCD <0=>Not used <1=>P1_12 <2=>P5_5 <3=>PC_11 <4=>PE_9 -#define RTE_UART1_DCD_ID 1 +#define RTE_UART1_DCD_ID 0 #if (RTE_UART1_DCD_ID == 0) #define RTE_UART1_DCD_PIN_EN 0 #elif (RTE_UART1_DCD_ID == 1) @@ -1271,7 +1271,7 @@ #define RTE_UART1_DCD_PIN_EN 1 #endif // DSR <0=>Not used <1=>P1_7 <2=>P5_0 <3=>PC_10 <4=>PE_8 -#define RTE_UART1_DSR_ID 1 +#define RTE_UART1_DSR_ID 0 #if (RTE_UART1_DSR_ID == 0) #define RTE_UART1_DSR_PIN_EN 0 #elif (RTE_UART1_DSR_ID == 1) @@ -1297,7 +1297,7 @@ #define RTE_UART1_DSR_PIN_EN 1 #endif // DTR <0=>Not used <1=>P1_8 <2=>P5_1 <3=>PC_12 <4=>PE_10 -#define RTE_UART1_DTR_ID 1 +#define RTE_UART1_DTR_ID 0 #if (RTE_UART1_DTR_ID == 0) #define RTE_UART1_DTR_PIN_EN 0 #elif (RTE_UART1_DTR_ID == 1) @@ -1323,7 +1323,7 @@ #define RTE_UART1_DTR_PIN_EN 1 #endif // RI <0=>Not used <1=>P1_10 <2=>P5_3 <3=>PC_1 <4=>PE_6 -#define RTE_UART1_RI_ID 1 +#define RTE_UART1_RI_ID 0 #if (RTE_UART1_RI_ID == 0) #define RTE_UART1_RI_PIN_EN 0 #elif (RTE_UART1_RI_ID == 1) From 041c36075e93d09dab1c3fe08e5f36ef419ce6ff Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 4 Dec 2021 18:27:45 -0600 Subject: [PATCH 527/617] lpc4322 (SWO): downgrade CMSIS UART drivers (thanks to @kc8apf) @kc8apf noticed that the drivers in version 2.9.0 of LPC4300_DFP pack work --- .../nxp/lpc4322/RTE_Driver/SCU_LPC43xx.h | 7 +- .../nxp/lpc4322/RTE_Driver/USART_LPC43xx.c | 388 ++++++++---------- .../nxp/lpc4322/RTE_Driver/USART_LPC43xx.h | 12 +- 3 files changed, 177 insertions(+), 230 deletions(-) diff --git a/source/hic_hal/nxp/lpc4322/RTE_Driver/SCU_LPC43xx.h b/source/hic_hal/nxp/lpc4322/RTE_Driver/SCU_LPC43xx.h index af15236e6..f85867ffd 100644 --- a/source/hic_hal/nxp/lpc4322/RTE_Driver/SCU_LPC43xx.h +++ b/source/hic_hal/nxp/lpc4322/RTE_Driver/SCU_LPC43xx.h @@ -1,5 +1,5 @@ /* -------------------------------------------------------------------------- - * Copyright (c) 2013-2020 Arm Limited (or its affiliates). All + * Copyright (c) 2013-2019 Arm Limited (or its affiliates). All * rights reserved. * * SPDX-License-Identifier: Apache-2.0 @@ -16,8 +16,8 @@ * See the License for the specific language governing permissions and * limitations under the License. * - * $Date: 20. Januar 2020 - * $Revision: V1.2 + * $Date: 30. April 2019 + * $Revision: V1.1 * * Project: SCU Driver Definitions for NXP LPC43xx * -------------------------------------------------------------------------- */ @@ -31,7 +31,6 @@ typedef struct _PIN_ID { uint8_t port; uint8_t num; - uint8_t reserved[2]; uint32_t config_val; } PIN_ID; diff --git a/source/hic_hal/nxp/lpc4322/RTE_Driver/USART_LPC43xx.c b/source/hic_hal/nxp/lpc4322/RTE_Driver/USART_LPC43xx.c index a8e290d42..dc9a5f214 100644 --- a/source/hic_hal/nxp/lpc4322/RTE_Driver/USART_LPC43xx.c +++ b/source/hic_hal/nxp/lpc4322/RTE_Driver/USART_LPC43xx.c @@ -1,5 +1,5 @@ /* -------------------------------------------------------------------------- - * Copyright (c) 2013-2021 Arm Limited (or its affiliates). All + * Copyright (c) 2013-2019 Arm Limited (or its affiliates). All * rights reserved. * * SPDX-License-Identifier: Apache-2.0 @@ -16,8 +16,8 @@ * See the License for the specific language governing permissions and * limitations under the License. * - * $Date: 6. June 2021 - * $Revision: V2.17 + * $Date: 30. May 2019 + * $Revision: V2.14 * * Driver: Driver_USART0, Driver_USART1, Driver_USART2, Driver_USART3 * Configured: via RTE_Device.h configuration file @@ -35,11 +35,6 @@ * -------------------------------------------------------------------------- */ /* History: - * Version 2.16 - * - Updated PIN_ID structure alignment - * - Removed minor compiler warnings - * Version 2.15 - * - Added function USART_PIN_Configure() * Version 2.14 * - Updated Baudrate divider calculation * Version 2.13 @@ -87,9 +82,7 @@ */ #include "USART_LPC43xx.h" -#include - -#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,17) +#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,14) #if ((!RTE_USART0) && (!RTE_UART1) && (!RTE_USART2) && (!RTE_USART3)) #error "USART not enabled in RTE_Device.h!" @@ -99,14 +92,11 @@ static const ARM_DRIVER_VERSION usart_driver_version = { ARM_USART_API_VERSION, ARM_USART_DRV_VERSION }; // Function Prototypes -static int32_t USART_PowerControl (ARM_POWER_STATE state, USART_RESOURCES *usart); -static int32_t USART_Control (uint32_t control, uint32_t arg, USART_RESOURCES *usart); - int32_t USART_SetBaudrate (uint32_t baudrate, USART_RESOURCES *usart); -void USART0_IRQHandler (void); -void UART1_IRQHandler (void); -void USART2_IRQHandler (void); -void USART3_IRQHandler (void); +void MX_UART0_IRQHandler (void); +void MX_UART1_IRQHandler (void); +void MX_UART2_IRQHandler (void); +void MX_UART3_IRQHandler (void); // Safety timeout to exit the loops #define LOOP_MAX_CNT (SystemCoreClock / 64U) @@ -251,13 +241,13 @@ static const FRACT_DIVIDER fract_div_lookup_table[] = { #if (RTE_USART0) static USART_INFO USART0_Info = {0}; #if (RTE_USART0_TX_PIN_EN == 1) -static const PIN_ID USART0_pin_tx = { RTE_USART0_TX_PORT, RTE_USART0_TX_BIT, {0U, 0U}, RTE_USART0_TX_FUNC }; +static const PIN_ID USART0_pin_tx = { RTE_USART0_TX_PORT, RTE_USART0_TX_BIT, RTE_USART0_TX_FUNC }; #endif #if (RTE_USART0_RX_PIN_EN == 1) -static const PIN_ID USART0_pin_rx = { RTE_USART0_RX_PORT, RTE_USART0_RX_BIT, {0U, 0U}, RTE_USART0_RX_FUNC }; +static const PIN_ID USART0_pin_rx = { RTE_USART0_RX_PORT, RTE_USART0_RX_BIT, RTE_USART0_RX_FUNC }; #endif #if (RTE_USART0_UCLK_PIN_EN == 1) -static const PIN_ID USART0_pin_clk = { RTE_USART0_UCLK_PORT, RTE_USART0_UCLK_BIT, {0U, 0U}, RTE_USART0_UCLK_FUNC }; +static const PIN_ID USART0_pin_clk = { RTE_USART0_UCLK_PORT, RTE_USART0_UCLK_BIT, RTE_USART0_UCLK_FUNC }; #endif #if (RTE_USART0_DMA_TX_EN == 1) @@ -298,7 +288,11 @@ static USART_RESOURCES USART0_Resources = { 0U, // RTS Flow Control available 0U, // CTS Flow Control available 0U, // Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE +#if ((RTE_USART0_DMA_RX_EN == 1) || (USART0_TRIG_LVL == USART_TRIG_LVL_1)) 0U, // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT +#else + 1U, // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT +#endif 0U, // RTS Line: 0=not available, 1=available 0U, // CTS Line: 0=not available, 1=available 0U, // DTR Line: 0=not available, 1=available @@ -358,8 +352,7 @@ static USART_RESOURCES USART0_Resources = { NULL, #endif &USART0_Info, - USART0_SC_OVERSAMPLING_RATIO, - {0U,0U} + USART0_SC_OVERSAMPLING_RATIO }; #endif @@ -367,28 +360,28 @@ static USART_RESOURCES USART0_Resources = { #if (RTE_UART1) static USART_INFO USART1_Info = {0}; #if (RTE_UART1_TX_PIN_EN == 1) -static const PIN_ID USART1_pin_tx = { RTE_UART1_TX_PORT, RTE_UART1_TX_BIT, {0U, 0U}, RTE_UART1_TX_FUNC }; +static const PIN_ID USART1_pin_tx = { RTE_UART1_TX_PORT, RTE_UART1_TX_BIT, RTE_UART1_TX_FUNC }; #endif #if (RTE_UART1_RX_PIN_EN == 1) -static const PIN_ID USART1_pin_rx = { RTE_UART1_RX_PORT, RTE_UART1_RX_BIT, {0U, 0U}, RTE_UART1_RX_FUNC }; +static const PIN_ID USART1_pin_rx = { RTE_UART1_RX_PORT, RTE_UART1_RX_BIT, RTE_UART1_RX_FUNC }; #endif #if (RTE_UART1_CTS_PIN_EN == 1) -static const PIN_ID USART1_pin_cts = { RTE_UART1_CTS_PORT, RTE_UART1_CTS_BIT, {0U, 0U}, RTE_UART1_CTS_FUNC }; +static const PIN_ID USART1_pin_cts = { RTE_UART1_CTS_PORT, RTE_UART1_CTS_BIT, RTE_UART1_CTS_FUNC }; #endif #if (RTE_UART1_RTS_PIN_EN == 1) -static const PIN_ID USART1_pin_rts = { RTE_UART1_RTS_PORT, RTE_UART1_RTS_BIT, {0U, 0U}, RTE_UART1_RTS_FUNC }; +static const PIN_ID USART1_pin_rts = { RTE_UART1_RTS_PORT, RTE_UART1_RTS_BIT, RTE_UART1_RTS_FUNC }; #endif #if (RTE_UART1_DCD_PIN_EN == 1) -static const PIN_ID USART1_pin_dcd = { RTE_UART1_DCD_PORT, RTE_UART1_DCD_BIT, {0U, 0U}, RTE_UART1_DCD_FUNC }; +static const PIN_ID USART1_pin_dcd = { RTE_UART1_DCD_PORT, RTE_UART1_DCD_BIT, RTE_UART1_DCD_FUNC }; #endif #if (RTE_UART1_DSR_PIN_EN == 1) -static const PIN_ID USART1_pin_dsr = { RTE_UART1_DSR_PORT, RTE_UART1_DSR_BIT, {0U, 0U}, RTE_UART1_DSR_FUNC }; +static const PIN_ID USART1_pin_dsr = { RTE_UART1_DSR_PORT, RTE_UART1_DSR_BIT, RTE_UART1_DSR_FUNC }; #endif #if (RTE_UART1_DTR_PIN_EN == 1) -static const PIN_ID USART1_pin_dtr = { RTE_UART1_DTR_PORT, RTE_UART1_DTR_BIT, {0U, 0U}, RTE_UART1_DTR_FUNC }; +static const PIN_ID USART1_pin_dtr = { RTE_UART1_DTR_PORT, RTE_UART1_DTR_BIT, RTE_UART1_DTR_FUNC }; #endif #if (RTE_UART1_RI_PIN_EN == 1) -static const PIN_ID USART1_pin_ri = { RTE_UART1_RI_PORT, RTE_UART1_RI_BIT, {0U, 0U}, RTE_UART1_RI_FUNC }; +static const PIN_ID USART1_pin_ri = { RTE_UART1_RI_PORT, RTE_UART1_RI_BIT, RTE_UART1_RI_FUNC }; #endif #if (RTE_UART1_DMA_TX_EN == 1) @@ -428,7 +421,11 @@ static USART_RESOURCES USART1_Resources = { 0U, // CTS Flow Control available #endif 0U, // Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE +#if ((RTE_UART1_DMA_RX_EN == 1) || (USART1_TRIG_LVL == USART_TRIG_LVL_1)) 0U, // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT +#else + 1U, // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT +#endif #if (RTE_UART1_RTS_PIN_EN == 1) 1U, // RTS Line: 0=not available, 1=available #else @@ -553,8 +550,7 @@ static USART_RESOURCES USART1_Resources = { NULL, #endif &USART1_Info, - 0, - {0U,0U} + 0 }; #endif @@ -562,13 +558,13 @@ static USART_RESOURCES USART1_Resources = { #if (RTE_USART2) static USART_INFO USART2_Info = {0}; #if (RTE_USART2_TX_PIN_EN == 1) -static const PIN_ID USART2_pin_tx = { RTE_USART2_TX_PORT, RTE_USART2_TX_BIT, {0U, 0U}, RTE_USART2_TX_FUNC }; +static const PIN_ID USART2_pin_tx = { RTE_USART2_TX_PORT, RTE_USART2_TX_BIT, RTE_USART2_TX_FUNC }; #endif #if (RTE_USART2_RX_PIN_EN == 1) -static const PIN_ID USART2_pin_rx = { RTE_USART2_RX_PORT, RTE_USART2_RX_BIT, {0U, 0U}, RTE_USART2_RX_FUNC }; +static const PIN_ID USART2_pin_rx = { RTE_USART2_RX_PORT, RTE_USART2_RX_BIT, RTE_USART2_RX_FUNC }; #endif #if (RTE_USART2_UCLK_PIN_EN == 1) -static const PIN_ID USART2_pin_clk = { RTE_USART2_UCLK_PORT, RTE_USART2_UCLK_BIT, {0U, 0U}, RTE_USART2_UCLK_FUNC }; +static const PIN_ID USART2_pin_clk = { RTE_USART2_UCLK_PORT, RTE_USART2_UCLK_BIT, RTE_USART2_UCLK_FUNC }; #endif #if (RTE_USART2_DMA_TX_EN == 1) @@ -609,7 +605,11 @@ static USART_RESOURCES USART2_Resources = { 0U, // RTS Flow Control available 0U, // CTS Flow Control available 0U, // Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE +#if ((RTE_USART2_DMA_RX_EN == 1) || (USART2_TRIG_LVL == USART_TRIG_LVL_1)) 0U, // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT +#else + 1U, // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT +#endif 0U, // RTS Line: 0=not available, 1=available 0U, // CTS Line: 0=not available, 1=available 0U, // DTR Line: 0=not available, 1=available @@ -669,8 +669,7 @@ static USART_RESOURCES USART2_Resources = { NULL, #endif &USART2_Info, - USART2_SC_OVERSAMPLING_RATIO, - {0U,0U} + USART2_SC_OVERSAMPLING_RATIO }; #endif @@ -678,13 +677,13 @@ static USART_RESOURCES USART2_Resources = { #if (RTE_USART3) static USART_INFO USART3_Info = {0}; #if (RTE_USART3_TX_PIN_EN == 1) -static const PIN_ID USART3_pin_tx = { RTE_USART3_TX_PORT, RTE_USART3_TX_BIT, {0U, 0U}, RTE_USART3_TX_FUNC }; +static const PIN_ID USART3_pin_tx = { RTE_USART3_TX_PORT, RTE_USART3_TX_BIT, RTE_USART3_TX_FUNC }; #endif #if (RTE_USART3_RX_PIN_EN == 1) -static const PIN_ID USART3_pin_rx = { RTE_USART3_RX_PORT, RTE_USART3_RX_BIT, {0U, 0U}, RTE_USART3_RX_FUNC }; +static const PIN_ID USART3_pin_rx = { RTE_USART3_RX_PORT, RTE_USART3_RX_BIT, RTE_USART3_RX_FUNC }; #endif #if (RTE_USART3_UCLK_PIN_EN == 1) -static const PIN_ID USART3_pin_clk = { RTE_USART3_UCLK_PORT, RTE_USART3_UCLK_BIT, {0U, 0U}, RTE_USART3_UCLK_FUNC }; +static const PIN_ID USART3_pin_clk = { RTE_USART3_UCLK_PORT, RTE_USART3_UCLK_BIT, RTE_USART3_UCLK_FUNC }; #endif #if (RTE_USART3_DMA_TX_EN == 1) @@ -725,7 +724,11 @@ static USART_RESOURCES USART3_Resources = { 0U, // RTS Flow Control available 0U, // CTS Flow Control available 0U, // Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE +#if ((RTE_USART3_DMA_RX_EN == 1) || (USART3_TRIG_LVL == USART_TRIG_LVL_1)) 0U, // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT +#else + 1U, // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT +#endif 0U, // RTS Line: 0=not available, 1=available 0U, // CTS Line: 0=not available, 1=available 0U, // DTR Line: 0=not available, 1=available @@ -785,8 +788,7 @@ static USART_RESOURCES USART3_Resources = { NULL, #endif &USART3_Info, - USART3_SC_OVERSAMPLING_RATIO, - {0U,0U} + USART3_SC_OVERSAMPLING_RATIO }; #endif @@ -824,7 +826,7 @@ int32_t USART_SetBaudrate (uint32_t baudrate, USART_RESOURCES *usart) { // SmartCard mode if (usart->info->mode == ARM_USART_MODE_SMART_CARD) { - oversampling_best = usart->sc_oversamp; + oversampling_best = (uint16_t)usart->sc_oversamp; for (i = 0; i < FRACT_DIV_LOOKUP_TABLE_SZ; i++) { // Calculate latch divider (latch_div = div / (fract_div * oversampling(16))) latch_div = ((div / fract_div_lookup_table[i].val) / oversampling_best); @@ -1062,73 +1064,16 @@ static uint32_t USART_RxLineIntHandler (USART_RESOURCES *usart) { } // Framing error - if(lsr & USART_LSR_FE) { - usart->info->rx_status.rx_framing_error = 1U; - event |= ARM_USART_EVENT_RX_FRAMING_ERROR; + else { + if(lsr & USART_LSR_FE) { + usart->info->rx_status.rx_framing_error = 1U; + event |= ARM_USART_EVENT_RX_FRAMING_ERROR; + } } return event; } -/** - \fn void USART_PIN_Configure (USART_RESOURCES *usart) - \brief Configure USART Rx and TX pin - \param[in] usart Pointer to USART resources -*/ -static void USART_PIN_Configure (USART_RESOURCES *usart) { - - switch (usart->info->mode) { - case ARM_USART_MODE_ASYNCHRONOUS: - case ARM_USART_MODE_SYNCHRONOUS_MASTER: - case ARM_USART_MODE_SYNCHRONOUS_SLAVE: - case ARM_USART_MODE_IRDA: - if (usart->info->flags & USART_FLAG_RX_ENABLED) { - // USART RX pin function selected - SCU_PinConfigure(usart->pins.rx->port, usart->pins.rx->num, - SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_INPUT_FILTER_DIS | - SCU_PIN_CFG_MODE(usart->pins.rx->config_val)); - } - else { - // GPIO pin function selected - SCU_PinConfigure(usart->pins.rx->port, usart->pins.rx->num, SCU_PIN_CFG_INPUT_FILTER_DIS | - SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0)); - } - - if (usart->info->flags & USART_FLAG_TX_ENABLED) { - // USART TX pin function selected - SCU_PinConfigure(usart->pins.tx->port, usart->pins.tx->num, - SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_INPUT_FILTER_DIS | - SCU_PIN_CFG_MODE(usart->pins.tx->config_val)); - } - else { - // GPIO pin function selected - SCU_PinConfigure(usart->pins.tx->port, usart->pins.tx->num, SCU_PIN_CFG_INPUT_FILTER_DIS | - SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0)); - } - break; - case ARM_USART_MODE_SINGLE_WIRE: - case ARM_USART_MODE_SMART_CARD: - if( (usart->info->flags & USART_FLAG_RX_ENABLED) || - (usart->info->flags & USART_FLAG_TX_ENABLED) ) { - // GPIO pin function selected - SCU_PinConfigure(usart->pins.rx->port, usart->pins.rx->num, SCU_PIN_CFG_INPUT_FILTER_DIS | - SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0)); - // USART TX pin function selected - SCU_PinConfigure(usart->pins.tx->port, usart->pins.tx->num, - SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_INPUT_FILTER_DIS | - SCU_PIN_CFG_MODE(usart->pins.tx->config_val)); - } - else { - // GPIO pin function selected - SCU_PinConfigure(usart->pins.rx->port, usart->pins.rx->num, SCU_PIN_CFG_INPUT_FILTER_DIS | - SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0)); - SCU_PinConfigure(usart->pins.tx->port, usart->pins.tx->num, SCU_PIN_CFG_INPUT_FILTER_DIS | - SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0)); - } - break; - } -} - // Function Prototypes static int32_t USART_Receive (void *data, uint32_t num, @@ -1181,8 +1126,8 @@ static int32_t USART_Initialize (ARM_USART_SignalEvent_t cb_event, usart->info->rx_status.rx_framing_error = 0U; usart->info->rx_status.rx_parity_error = 0U; - // Clear transfer information - memset((void *)&usart->info->xfer, 0, sizeof(USART_TRANSFER_INFO)); + usart->info->xfer.send_active = 0U; + usart->info->xfer.tx_def_val = 0U; // Configure CTS pin if (usart->capabilities.cts) { @@ -1240,11 +1185,6 @@ static int32_t USART_Initialize (ARM_USART_SignalEvent_t cb_event, */ static int32_t USART_Uninitialize (USART_RESOURCES *usart) { - if ((usart->info->flags & USART_FLAG_POWERED) != 0U) { - // If peripheral is powered, power off the peripheral - (void)USART_PowerControl(ARM_POWER_OFF, usart); - } - // Reset TX pin configuration if (usart->pins.tx) { SCU_PinConfigure(usart->pins.tx->port, usart->pins.tx->num , 0U); @@ -1291,11 +1231,7 @@ static int32_t USART_Uninitialize (USART_RESOURCES *usart) { } // DMA Uninitialize - if (usart->dma_tx || usart->dma_rx) { - GPDMA_Uninitialize (); - GPDMA_Initialize (); - GPDMA_Uninitialize (); - } + if (usart->dma_tx || usart->dma_rx) { GPDMA_Uninitialize (); } // Reset USART status flags usart->info->flags = 0U; @@ -1314,10 +1250,6 @@ static int32_t USART_PowerControl (ARM_POWER_STATE state, USART_RESOURCES *usart) { uint32_t val, tout_cnt; - if ((usart->info->flags & USART_FLAG_INITIALIZED) == 0U) { - return ARM_DRIVER_ERROR; - } - if ((state != ARM_POWER_OFF) && (state != ARM_POWER_FULL) && (state != ARM_POWER_LOW)) { @@ -1326,12 +1258,8 @@ static int32_t USART_PowerControl (ARM_POWER_STATE state, switch (state) { case ARM_POWER_OFF: - USART_Control (ARM_USART_ABORT_SEND, 0U, usart); - USART_Control (ARM_USART_ABORT_RECEIVE, 0U, usart); - USART_Control (ARM_USART_ABORT_TRANSFER, 0U, usart); - // Disable USART IRQ - NVIC_DisableIRQ( (IRQn_Type) usart->irq_num); + NVIC_DisableIRQ(usart->irq_num); // If DMA mode - disable TX DMA channel if ((usart->dma_tx) && (usart->info->xfer.send_active != 0U)) { @@ -1345,7 +1273,7 @@ static int32_t USART_PowerControl (ARM_POWER_STATE state, // Reset USART peripheral *usart->rst.reg_cfg = (usart->rst.reg_cfg_val | (~(*(usart->rst.reg_stat)))); - tout_cnt = LOOP_MAX_CNT; + tout_cnt = LOOP_MAX_CNT; while ((*(usart->rst.reg_stat) & usart->rst.reg_cfg_val) == 0U) { if (tout_cnt-- == 0U) { __NOP(); @@ -1374,7 +1302,7 @@ static int32_t USART_PowerControl (ARM_POWER_STATE state, } // Clear pending USART interrupts in NVIC - NVIC_ClearPendingIRQ( (IRQn_Type) usart->irq_num); + NVIC_ClearPendingIRQ(usart->irq_num); // Clear driver variables usart->info->rx_status.rx_busy = 0U; @@ -1382,11 +1310,9 @@ static int32_t USART_PowerControl (ARM_POWER_STATE state, usart->info->rx_status.rx_break = 0U; usart->info->rx_status.rx_framing_error = 0U; usart->info->rx_status.rx_parity_error = 0U; + usart->info->xfer.send_active = 0U; - // Clear transfer information - memset((void *)&usart->info->xfer, 0, sizeof(USART_TRANSFER_INFO)); - - usart->info->flags &= ~(USART_FLAG_POWERED | USART_FLAG_CONFIGURED); + usart->info->flags &= ~USART_FLAG_POWERED; break; case ARM_POWER_LOW: @@ -1473,8 +1399,8 @@ static int32_t USART_PowerControl (ARM_POWER_STATE state, usart->info->flags = USART_FLAG_POWERED | USART_FLAG_INITIALIZED; // Clear and Enable USART IRQ - NVIC_ClearPendingIRQ( (IRQn_Type) usart->irq_num); - NVIC_EnableIRQ( (IRQn_Type) usart->irq_num); + NVIC_ClearPendingIRQ(usart->irq_num); + NVIC_EnableIRQ(usart->irq_num); } return ARM_DRIVER_OK; } @@ -1522,7 +1448,6 @@ static int32_t USART_Send (const void *data, if (usart->info->xfer.sync_mode == 0U) { usart->info->xfer.sync_mode = USART_SYNC_MODE_TX; // Start dummy reads - USART_Control (ARM_USART_CONTROL_RX, 1U, usart); stat = USART_Receive (&usart->info->xfer.rx_dump_val, num, usart); if (stat != ARM_DRIVER_OK) { return ARM_DRIVER_ERROR; } @@ -1686,7 +1611,7 @@ static int32_t USART_Receive (void *data, GPDMA_CH_CONFIG_ITC | GPDMA_CH_CONFIG_E, usart->dma_rx->cb_event); - if (stat == -1) { return ARM_DRIVER_ERROR; } + if (stat == -1) { return ARM_DRIVER_ERROR; } // Interrupt mode } else { @@ -1700,7 +1625,6 @@ static int32_t USART_Receive (void *data, if (usart->info->xfer.sync_mode == 0U) { usart->info->xfer.sync_mode = USART_SYNC_MODE_RX; // Send dummy data - USART_Control (ARM_USART_CONTROL_TX, 1U, usart); stat = USART_Send (&usart->info->xfer.tx_def_val, num, usart); if (stat != ARM_DRIVER_OK) { return ARM_DRIVER_ERROR; } } @@ -1809,7 +1733,6 @@ static int32_t USART_Control (uint32_t control, USART_RESOURCES *usart) { uint8_t mode; uint32_t val, syncctrl, hden, icr, scictrl, lcr, mcr = 0U; - uint32_t cnt; if ((usart->info->flags & USART_FLAG_POWERED) == 0U) { // USART not powered @@ -1826,13 +1749,25 @@ static int32_t USART_Control (uint32_t control, // Control TX case ARM_USART_CONTROL_TX: if (arg) { + if (usart->info->mode != ARM_USART_MODE_SMART_CARD) { + // USART TX pin function selected + if (usart->pins.tx) { + SCU_PinConfigure(usart->pins.tx->port, usart->pins.tx->num, SCU_PIN_CFG_INPUT_FILTER_DIS | + SCU_PIN_CFG_MODE(usart->pins.tx->config_val)); + } + } usart->info->flags |= USART_FLAG_TX_ENABLED; - USART_PIN_Configure (usart); usart->reg->TER |= USART_TER_TXEN; } else { usart->info->flags &= ~USART_FLAG_TX_ENABLED; usart->reg->TER &= ~USART_TER_TXEN; - USART_PIN_Configure (usart); + if (usart->info->mode != ARM_USART_MODE_SMART_CARD) { + // GPIO pin function selected + if (usart->pins.tx) { + SCU_PinConfigure(usart->pins.tx->port, usart->pins.tx->num, SCU_PIN_CFG_INPUT_FILTER_DIS | + SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0)); + } + } } return ARM_DRIVER_OK; @@ -1840,15 +1775,30 @@ static int32_t USART_Control (uint32_t control, case ARM_USART_CONTROL_RX: // RX Line interrupt enable (overrun, framing, parity error, break) if (arg) { + if ((usart->info->mode != ARM_USART_MODE_SMART_CARD) && + (usart->info->mode != ARM_USART_MODE_SINGLE_WIRE )) { + // USART RX pin function selected + if (usart->pins.rx) { + SCU_PinConfigure(usart->pins.rx->port, usart->pins.rx->num, + SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_INPUT_FILTER_DIS | + SCU_PIN_CFG_MODE(usart->pins.rx->config_val)); + } + } usart->info->flags |= USART_FLAG_RX_ENABLED; usart->reg->RS485CTRL &= ~USART_RS485CTRL_RXDIS; - USART_PIN_Configure (usart); usart->reg->IER |= USART_IER_RXIE; } else { usart->info->flags &= ~USART_FLAG_RX_ENABLED; usart->reg->RS485CTRL |= USART_RS485CTRL_RXDIS; usart->reg->IER &= ~USART_IER_RXIE; - USART_PIN_Configure (usart); + if ((usart->info->mode != ARM_USART_MODE_SMART_CARD) && + (usart->info->mode != ARM_USART_MODE_SINGLE_WIRE )) { + // GPIO pin function selected + if (usart->pins.rx) { + SCU_PinConfigure(usart->pins.rx->port, usart->pins.rx->num, SCU_PIN_CFG_INPUT_FILTER_DIS | + SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0)); + } + } } return ARM_DRIVER_OK; @@ -1890,25 +1840,6 @@ static int32_t USART_Control (uint32_t control, GPDMA_ChannelDisable (usart->dma_tx->channel); } - if (usart->info->xfer.send_active != 0U) { - if ((usart->reg->LSR & USART_LSR_TEMT) == 0U) { - // If transmit is in progess, wait for it to finish - cnt = 2000000U; - while (((usart->reg->LSR & USART_LSR_TEMT) == 0U) && (cnt-- != 0U)); - } - } - - // Synchronous mode - if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) || - (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) { - if (usart->info->xfer.sync_mode == USART_SYNC_MODE_TX) { - usart->info->xfer.sync_mode = 0U; - // Abort receive also - USART_Control (ARM_USART_ABORT_RECEIVE, 0U, usart); - USART_Control (ARM_USART_CONTROL_RX, 0U, usart); - } - } - // Clear Send active flag usart->info->xfer.send_active = 0U; return ARM_DRIVER_OK; @@ -1934,17 +1865,6 @@ static int32_t USART_Control (uint32_t control, GPDMA_ChannelDisable (usart->dma_rx->channel); } - // Synchronous mode - if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) || - (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) { - if (usart->info->xfer.sync_mode == USART_SYNC_MODE_RX) { - usart->info->xfer.sync_mode = 0U; - // Abort send also - USART_Control (ARM_USART_ABORT_SEND, 0U, usart); - USART_Control (ARM_USART_CONTROL_TX, 0U, usart); - } - } - // Clear RX busy status usart->info->rx_status.rx_busy = 0U; return ARM_DRIVER_OK; @@ -1973,17 +1893,6 @@ static int32_t USART_Control (uint32_t control, val |= USART_FCR_TXFIFORES | USART_FCR_RXFIFORES; usart->reg->FCR = val; - if (usart->info->xfer.send_active != 0U) { - if ((usart->reg->LSR & USART_LSR_TEMT) == 0U) { - // If transmit is in progess, wait for it to finish - cnt = 2000000U; - while (((usart->reg->LSR & USART_LSR_TEMT) == 0U) && (cnt-- != 0U)); - } - } - - // Clear sync_mode - usart->info->xfer.sync_mode = 0U; - // Clear busy statuses usart->info->rx_status.rx_busy = 0U; usart->info->xfer.send_active = 0U; @@ -2071,7 +1980,7 @@ static int32_t USART_Control (uint32_t control, if (usart->capabilities.smart_card == 0U) { return ARM_DRIVER_ERROR; } if (arg == 0U) { return ARM_DRIVER_OK; } if (usart->capabilities.smart_card_clock) { - if ((usart->info->baudrate * (uint32_t) usart->sc_oversamp) != arg) { + if ((uint32_t)(usart->info->baudrate * usart->sc_oversamp) != arg) { return ARM_DRIVER_ERROR; } } else { return ARM_DRIVER_ERROR; } @@ -2176,8 +2085,50 @@ static int32_t USART_Control (uint32_t control, // Configuration is OK - Mode is valid usart->info->mode = mode; - // Configure RX pin and TX pin regarding mode and transmitter/receiver state - USART_PIN_Configure (usart); + // Configure TX pin regarding mode and transmitter state + val = SCU_PIN_CFG_INPUT_FILTER_DIS; + switch (usart->info->mode) { + case ARM_USART_MODE_SMART_CARD: + // Pin function = USART TX + val |= SCU_PIN_CFG_MODE(usart->pins.tx->config_val); + break; + default: + // Synchronous master/slave, asynchronous, single-wire and IrDA mode + if (usart->info->flags & USART_FLAG_TX_ENABLED) { + // Pin function = USART TX + val |= SCU_PIN_CFG_MODE(usart->pins.tx->config_val); + } else { + // Pin function = GPIO + val |= SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0); + } + } + if (usart->pins.tx) { + SCU_PinConfigure(usart->pins.tx->port, usart->pins.tx->num, val); + } + + // Configure RX pin regarding mode and receiver state + val = SCU_PIN_CFG_INPUT_FILTER_DIS; + switch (usart->info->mode) { + case ARM_USART_MODE_SINGLE_WIRE: + case ARM_USART_MODE_SMART_CARD: + // Pin function = GPIO + val |= SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0); + break; + default: + // Synchronous master/slave, asynchronous and IrDA mode + if (usart->info->flags & USART_FLAG_RX_ENABLED) { + // Pin function = USART RX + val |= SCU_PIN_CFG_INPUT_BUFFER_EN | + SCU_PIN_CFG_MODE(usart->pins.rx->config_val); + } else { + // Pin function = GPIO + val |= SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0); + } + break; + } + if (usart->pins.rx) { + SCU_PinConfigure(usart->pins.rx->port, usart->pins.rx->num, val); + } // Configure CLK pin regarding mode if (usart->pins.clk) { @@ -2228,7 +2179,7 @@ static int32_t USART_Control (uint32_t control, // Configure MCR register (modem line for USART1) if (usart->uart_reg) { - usart->uart_reg->MCR = ((usart->uart_reg->MCR & ~(UART_MCR_RTSEN | UART_MCR_RTSCTRL | + usart->uart_reg->MCR = ((usart->uart_reg->MCR & ~(UART_MCR_RTSEN | UART_MCR_CTSEN))) | mcr; } @@ -2248,18 +2199,15 @@ static int32_t USART_Control (uint32_t control, \return USART status \ref ARM_USART_STATUS */ static ARM_USART_STATUS USART_GetStatus (USART_RESOURCES *usart) { - ARM_USART_STATUS stat = { 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U }; - - if ((usart->info->flags & USART_FLAG_POWERED) != 0U) { - stat.tx_busy = (usart->reg->LSR & USART_LSR_TEMT ? (0U) : (1U)); - stat.rx_busy = usart->info->rx_status.rx_busy; - stat.tx_underflow = 0U; - stat.rx_overflow = usart->info->rx_status.rx_overflow; - stat.rx_break = usart->info->rx_status.rx_break; - stat.rx_framing_error = usart->info->rx_status.rx_framing_error; - stat.rx_parity_error = usart->info->rx_status.rx_parity_error; - } - + ARM_USART_STATUS stat; + + stat.tx_busy = (usart->reg->LSR & USART_LSR_TEMT ? (0U) : (1U)); + stat.rx_busy = usart->info->rx_status.rx_busy; + stat.tx_underflow = 0U; + stat.rx_overflow = usart->info->rx_status.rx_overflow; + stat.rx_break = usart->info->rx_status.rx_break; + stat.rx_framing_error = usart->info->rx_status.rx_framing_error; + stat.rx_parity_error = usart->info->rx_status.rx_parity_error; return stat; } @@ -2308,7 +2256,7 @@ static int32_t USART_SetModemControl (ARM_USART_MODEM_CONTROL control, \return modem status \ref ARM_USART_MODEM_STATUS */ static ARM_USART_MODEM_STATUS USART_GetModemStatus (USART_RESOURCES *usart) { - ARM_USART_MODEM_STATUS modem_status = { 0U, 0U, 0U, 0U, 0U }; + ARM_USART_MODEM_STATUS modem_status; uint32_t msr; if (usart->uart_reg && @@ -2316,10 +2264,19 @@ static ARM_USART_MODEM_STATUS USART_GetModemStatus (USART_RESOURCES *usart) { msr = usart->uart_reg->MSR; - if (usart->capabilities.cts) { modem_status.cts = ((msr & UART_MSR_CTS) ? (0U) : (1U)); } - if (usart->capabilities.dsr) { modem_status.dsr = ((msr & UART_MSR_DSR) ? (0U) : (1U)); } - if (usart->capabilities.ri ) { modem_status.ri = ((msr & UART_MSR_RI ) ? (0U) : (1U)); } - if (usart->capabilities.dcd) { modem_status.dcd = ((msr & UART_MSR_DCD) ? (0U) : (1U)); } + if (usart->capabilities.cts) { modem_status.cts = (msr & UART_MSR_CTS ? (1U) : (0U)); } + else { modem_status.cts = 0U; } + if (usart->capabilities.dsr) { modem_status.dsr = (msr & UART_MSR_DSR ? (1U) : (0U)); } + else { modem_status.dsr = 0U; } + if (usart->capabilities.ri ) { modem_status.ri = (msr & UART_MSR_RI ? (1U) : (0U)); } + else { modem_status.ri = 0U; } + if (usart->capabilities.dcd) { modem_status.dcd = (msr & UART_MSR_DCD ? (1U) : (0U)); } + else { modem_status.dcd = 0U; } + } else { + modem_status.cts = 0U; + modem_status.dsr = 0U; + modem_status.ri = 0U; + modem_status.dcd = 0U; } return modem_status; @@ -2341,7 +2298,7 @@ static void USART_IRQHandler (USART_RESOURCES *usart) { // Transmit holding register empty if ((iir & USART_IIR_INTID_MSK) == USART_IIR_INTID_THRE) { val = 16U; - while ((val --) && (usart->info->xfer.tx_num != 0U) && (usart->info->xfer.tx_num != usart->info->xfer.tx_cnt)) { + while ((val --) && (usart->info->xfer.tx_num != usart->info->xfer.tx_cnt)) { if (((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) || (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) && (usart->info->xfer.sync_mode == USART_SYNC_MODE_RX)) { @@ -2354,7 +2311,7 @@ static void USART_IRQHandler (USART_RESOURCES *usart) { usart->info->xfer.tx_cnt++; } - // Check if all data was transmitted + // Check if all data is transmitted if (usart->info->xfer.tx_num == usart->info->xfer.tx_cnt) { // Disable THRE interrupt usart->reg->IER &= ~USART_IER_THREIE; @@ -2401,18 +2358,13 @@ static void USART_IRQHandler (USART_RESOURCES *usart) { (usart->info->xfer.sync_mode == USART_SYNC_MODE_TX)) { // Dummy read in synchronous transmit only mode usart->reg->RBR; - usart->info->xfer.rx_cnt++; } else { - if (usart->info->xfer.rx_cnt < usart->info->xfer.rx_num) { - // Read data from RX FIFO into receive buffer - usart->info->xfer.rx_buf[usart->info->xfer.rx_cnt] = usart->reg->RBR & 0xFFU; - usart->info->xfer.rx_cnt++; - } else { - usart->reg->RBR; - event |= ARM_USART_EVENT_RX_OVERFLOW; - } + // Read data from RX FIFO into receive buffer + usart->info->xfer.rx_buf[usart->info->xfer.rx_cnt] = usart->reg->RBR & 0xFFU; } + usart->info->xfer.rx_cnt++; + // Check if requested amount of data is received if (usart->info->xfer.rx_cnt == usart->info->xfer.rx_num) { // Disable RDA interrupt @@ -2449,9 +2401,7 @@ static void USART_IRQHandler (USART_RESOURCES *usart) { if ((usart->info->mode != ARM_USART_MODE_SYNCHRONOUS_MASTER) && (usart->info->mode != ARM_USART_MODE_SYNCHRONOUS_SLAVE )) { // Signal RX Time-out event, if not all requested data received - if ((usart->info->xfer.rx_num != 0U) && - (usart->info->xfer.rx_cnt != usart->info->xfer.rx_num)) { - usart->reg->RBR; + if (usart->info->xfer.rx_cnt != usart->info->xfer.rx_num) { event |= ARM_USART_EVENT_RX_TIMEOUT; } } diff --git a/source/hic_hal/nxp/lpc4322/RTE_Driver/USART_LPC43xx.h b/source/hic_hal/nxp/lpc4322/RTE_Driver/USART_LPC43xx.h index d5e12535c..d28884bea 100644 --- a/source/hic_hal/nxp/lpc4322/RTE_Driver/USART_LPC43xx.h +++ b/source/hic_hal/nxp/lpc4322/RTE_Driver/USART_LPC43xx.h @@ -1,5 +1,5 @@ /* -------------------------------------------------------------------------- - * Copyright (c) 2013-2020 Arm Limited (or its affiliates). All + * Copyright (c) 2013-2019 Arm Limited (or its affiliates). All * rights reserved. * * SPDX-License-Identifier: Apache-2.0 @@ -16,8 +16,8 @@ * See the License for the specific language governing permissions and * limitations under the License. * - * $Date: 20. Januar 2020 - * $Revision: V2.8 + * $Date: 30. April 2019 + * $Revision: V2.7 * * Project: USART Driver Definitions for NXP LPC43xx * -------------------------------------------------------------------------- */ @@ -32,7 +32,6 @@ #include "GPDMA_LPC43xx.h" #include "RTE_Device.h" -#include "RTE_Components.h" // Clock Control Unit register #define CCU_CLK_CFG_RUN (1U << 0) @@ -293,13 +292,12 @@ typedef const struct { USART_PINS pins; // USART pins configuration USART_CLOCKS clk; // USART clocks configuration USART_RESET rst; // USART reset configuration - int32_t irq_num; // USART IRQ Number + IRQn_Type irq_num; // USART IRQ Number uint32_t trig_lvl; // FIFO Trigger level USART_DMA *dma_tx; USART_DMA *dma_rx; USART_INFO *info; // Run-Time Information - uint16_t sc_oversamp; // SmartCard oversampling ratio - uint8_t reserved[2]; // Reserved + float sc_oversamp; // SmartCard oversampling ratio } USART_RESOURCES; // Global functions and variables exported by driver .c module */ From f4e0774e295ae85944b359f9a8e4d17dfc308d8e Mon Sep 17 00:00:00 2001 From: Adrian Negreanu Date: Mon, 28 Dec 2020 19:47:17 +0200 Subject: [PATCH 528/617] lpc4322 (gpio): add X_WORD gpio helper --- source/hic_hal/nxp/lpc4322/IO_Config.h | 1 + 1 file changed, 1 insertion(+) diff --git a/source/hic_hal/nxp/lpc4322/IO_Config.h b/source/hic_hal/nxp/lpc4322/IO_Config.h index 98a2c451b..d372dddff 100644 --- a/source/hic_hal/nxp/lpc4322/IO_Config.h +++ b/source/hic_hal/nxp/lpc4322/IO_Config.h @@ -71,6 +71,7 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC4322); #define X_DIR_OUT(str) LPC_GPIO_PORT->DIR[PORT_##str] |= (PIN_##str) #define X_DIR_IN(str) LPC_GPIO_PORT->DIR[PORT_##str] &= ~(PIN_##str) #define X_BYTE(str) LPC_GPIO_PORT->B[(PORT_##str << 5) + PIN_##str##_IN_BIT] +#define X_WORD(str) LPC_GPIO_PORT->W[(PORT_##str << 5) + PIN_##str##_IN_BIT] #endif From ab98884f8c3895edf166c22c978b573790405904 Mon Sep 17 00:00:00 2001 From: Adrian Negreanu Date: Mon, 28 Dec 2020 19:53:50 +0200 Subject: [PATCH 529/617] lpc4322 (gpio): use the gpio helpers instead of LPC_GPIO_PORT Signed-off-by: Adrian Negreanu --- source/hic_hal/nxp/lpc4322/IO_Config.h | 7 ++-- source/hic_hal/nxp/lpc4322/gpio.c | 55 +++++++++++++++----------- 2 files changed, 35 insertions(+), 27 deletions(-) diff --git a/source/hic_hal/nxp/lpc4322/IO_Config.h b/source/hic_hal/nxp/lpc4322/IO_Config.h index d372dddff..278f20f87 100644 --- a/source/hic_hal/nxp/lpc4322/IO_Config.h +++ b/source/hic_hal/nxp/lpc4322/IO_Config.h @@ -62,9 +62,10 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC4322); #define PIN_RESET_TXE_IN_BIT 6 #define PIN_RESET_TXE (1<SET[PORT_##str] = PIN_##str #define X_CLR(str) LPC_GPIO_PORT->CLR[PORT_##str] = PIN_##str diff --git a/source/hic_hal/nxp/lpc4322/gpio.c b/source/hic_hal/nxp/lpc4322/gpio.c index 474d3391d..c66c94519 100644 --- a/source/hic_hal/nxp/lpc4322/gpio.c +++ b/source/hic_hal/nxp/lpc4322/gpio.c @@ -57,27 +57,34 @@ void gpio_init(void) /* Configure I/O pins: function number, input buffer enabled, */ /* no pull-up/down */ - scu_pinmux(1, 1, GPIO_NOPULL, FUNC0); /* LED: GPIO0[8] */ - scu_pinmux(2, 11, GPIO_NOPULL, FUNC0); /* ISPCTRL: GPIO1[11] */ - scu_pinmux(2, 5, GPIO_PUP, FUNC4); /* nRESET: GPIO5[5] */ - scu_pinmux(2, 6, GPIO_NOPULL, FUNC4); /* nRESET_OE: GPIO5[6] */ - /* Configure: LED as output (turned off) */ - LPC_GPIO_PORT->CLR[LED_CONNECTED_PORT] = (1 << LED_CONNECTED_BIT); - LPC_GPIO_PORT->DIR[LED_CONNECTED_PORT] |= (1 << LED_CONNECTED_BIT); - /* Configure: ISPCTRL as output and high */ - LPC_GPIO_PORT->SET[ISPCTRL_PORT] = (1 << ISPCTRL_BIT); - LPC_GPIO_PORT->DIR[ISPCTRL_PORT] |= (1 << ISPCTRL_BIT); - /* configure Reset Button as input, Reset Output Enable as output LOW */ - LPC_GPIO_PORT->DIR[PORT_nRESET] &= ~(1 << PIN_nRESET_IN_BIT); - LPC_GPIO_PORT->CLR[PORT_RESET_TXE] = (1 << PIN_RESET_TXE_IN_BIT); - LPC_GPIO_PORT->DIR[PORT_RESET_TXE] |= (1 << PIN_RESET_TXE_IN_BIT); + scu_pinmux(1, 1, GPIO_NOPULL, FUNC0); /* P1_1 LED: GPIO0[8] */ + scu_pinmux(2, 11, GPIO_NOPULL, FUNC0); /* P2_11 ISPCTRL: GPIO1[11] */ + scu_pinmux(2, 5, GPIO_PUP, FUNC4); /* P2_5 nRESET: GPIO5[5] */ + scu_pinmux(2, 6, GPIO_NOPULL, FUNC4); /* P2_6 nRESET_OE: GPIO5[6] */ + + /* Configure: LED as output LOW (turned off)*/ + X_DIR_OUT(LED_CONNECTED); + X_CLR(LED_CONNECTED); + + /* Configure: ISPCTRL as output HIGH */ + X_DIR_OUT(ISPCTRL); + X_SET(ISPCTRL); + + /* Configure: Reset Button */ + X_DIR_IN(nRESET); + X_CLR(nRESET); + + /* Reset Output Enable as output LOW */ + X_DIR_OUT(RESET_TXE); + X_CLR(RESET_TXE); + /* Use Pin Interrupt 0 */ LPC_SCU->PINTSEL0 &= ~0xff; LPC_SCU->PINTSEL0 |= (PORT_nRESET << 5) | (PIN_nRESET_IN_BIT); #if (SWO_UART != 0) /* Configure: SWO as input */ - LPC_GPIO_PORT->DIR[PORT_SWO] &= ~(1 << PIN_SWO_IN_BIT); + X_DIR_IN(SWO); #endif busy_wait(10000); @@ -86,42 +93,42 @@ void gpio_init(void) void gpio_set_hid_led(gpio_led_state_t state) { if (state) { - LPC_GPIO_PORT->SET[LED_CONNECTED_PORT] = (1 << LED_CONNECTED_BIT); + X_SET(LED_CONNECTED); } else { - LPC_GPIO_PORT->CLR[LED_CONNECTED_PORT] = (1 << LED_CONNECTED_BIT); + X_CLR(LED_CONNECTED); } } void gpio_set_cdc_led(gpio_led_state_t state) { if (state) { - LPC_GPIO_PORT->SET[LED_CONNECTED_PORT] = (1 << LED_CONNECTED_BIT); + X_SET(LED_CONNECTED); } else { - LPC_GPIO_PORT->CLR[LED_CONNECTED_PORT] = (1 << LED_CONNECTED_BIT); + X_CLR(LED_CONNECTED); } } void gpio_set_msc_led(gpio_led_state_t state) { if (state) { - LPC_GPIO_PORT->SET[LED_CONNECTED_PORT] = (1 << LED_CONNECTED_BIT); + X_SET(LED_CONNECTED); } else { - LPC_GPIO_PORT->CLR[LED_CONNECTED_PORT] = (1 << LED_CONNECTED_BIT); + X_CLR(LED_CONNECTED); } } void gpio_set_isp_pin(uint8_t state) { if (state) { - LPC_GPIO_PORT->SET[ISPCTRL_PORT] = (1 << ISPCTRL_BIT); + X_SET(ISPCTRL); } else { - LPC_GPIO_PORT->CLR[ISPCTRL_PORT] = (1 << ISPCTRL_BIT); + X_CLR(ISPCTRL); } } uint8_t gpio_get_reset_btn_no_fwrd(void) { - return LPC_GPIO_PORT->W[PORT_nRESET * 32 + PIN_nRESET_IN_BIT] ? 0 : 1; + return X_WORD(nRESET) ? 0 : 1; } uint8_t gpio_get_reset_btn_fwrd(void) From 8714f3fff737c975fe8ef53badf09ecd84b352f1 Mon Sep 17 00:00:00 2001 From: Adrian Negreanu Date: Mon, 28 Dec 2020 20:05:47 +0200 Subject: [PATCH 530/617] lpc4322 (gpio): implement gpio_set_board_power --- source/hic_hal/nxp/lpc4322/DAP_config.h | 2 -- source/hic_hal/nxp/lpc4322/IO_Config.h | 5 +++++ source/hic_hal/nxp/lpc4322/gpio.c | 10 ++++++++++ 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/source/hic_hal/nxp/lpc4322/DAP_config.h b/source/hic_hal/nxp/lpc4322/DAP_config.h index 62c9043b4..2033ba7f6 100644 --- a/source/hic_hal/nxp/lpc4322/DAP_config.h +++ b/source/hic_hal/nxp/lpc4322/DAP_config.h @@ -158,8 +158,6 @@ typedef unsigned int BOOL; // State of Reset Ouput Enable buffer extern bool gpio_reset_pin_is_input; - - //************************************************************************************************** /** \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access diff --git a/source/hic_hal/nxp/lpc4322/IO_Config.h b/source/hic_hal/nxp/lpc4322/IO_Config.h index 278f20f87..1c645222c 100644 --- a/source/hic_hal/nxp/lpc4322/IO_Config.h +++ b/source/hic_hal/nxp/lpc4322/IO_Config.h @@ -67,6 +67,11 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC4322); #define PIN_ISPCTRL_IN_BIT 11 #define PIN_ISPCTRL (1<SET[PORT_##str] = PIN_##str #define X_CLR(str) LPC_GPIO_PORT->CLR[PORT_##str] = PIN_##str #define X_DIR_OUT(str) LPC_GPIO_PORT->DIR[PORT_##str] |= (PIN_##str) diff --git a/source/hic_hal/nxp/lpc4322/gpio.c b/source/hic_hal/nxp/lpc4322/gpio.c index c66c94519..cffdede17 100644 --- a/source/hic_hal/nxp/lpc4322/gpio.c +++ b/source/hic_hal/nxp/lpc4322/gpio.c @@ -61,6 +61,7 @@ void gpio_init(void) scu_pinmux(2, 11, GPIO_NOPULL, FUNC0); /* P2_11 ISPCTRL: GPIO1[11] */ scu_pinmux(2, 5, GPIO_PUP, FUNC4); /* P2_5 nRESET: GPIO5[5] */ scu_pinmux(2, 6, GPIO_NOPULL, FUNC4); /* P2_6 nRESET_OE: GPIO5[6] */ + scu_pinmux(3, 1, GPIO_NOPULL, FUNC4); /* P3_1 POWER_EN: GPIO5[8] */ /* Configure: LED as output LOW (turned off)*/ X_DIR_OUT(LED_CONNECTED); @@ -82,6 +83,10 @@ void gpio_init(void) LPC_SCU->PINTSEL0 &= ~0xff; LPC_SCU->PINTSEL0 |= (PORT_nRESET << 5) | (PIN_nRESET_IN_BIT); + /* Configure: POWER_EN as output LOW */ + X_DIR_OUT(POWER_EN); + X_CLR(POWER_EN); + #if (SWO_UART != 0) /* Configure: SWO as input */ X_DIR_IN(SWO); @@ -138,4 +143,9 @@ uint8_t gpio_get_reset_btn_fwrd(void) void gpio_set_board_power(bool powerEnabled) { + if (powerEnabled) { + X_SET(POWER_EN); + } else { + X_CLR(POWER_EN); + } } From e6bbc89df128273d84ddcd45f6e1150162af6568 Mon Sep 17 00:00:00 2001 From: Adrian Negreanu Date: Mon, 28 Dec 2020 20:08:08 +0200 Subject: [PATCH 531/617] lpc4322 (gpio): implement LED_CONNECTED_OUT Signed-off-by: Adrian Negreanu --- source/hic_hal/nxp/lpc4322/DAP_config.h | 5 +++++ source/hic_hal/nxp/lpc4322/IO_Config.h | 5 +++++ source/hic_hal/nxp/lpc4322/gpio.c | 3 --- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/source/hic_hal/nxp/lpc4322/DAP_config.h b/source/hic_hal/nxp/lpc4322/DAP_config.h index 2033ba7f6..d031bdbda 100644 --- a/source/hic_hal/nxp/lpc4322/DAP_config.h +++ b/source/hic_hal/nxp/lpc4322/DAP_config.h @@ -440,6 +440,11 @@ It is recommended to provide the following LEDs for status indication: */ __STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit) { + if (bit) { + X_SET(LED_CONNECTED); + } else { + X_CLR(LED_CONNECTED); + } } /** Debug Unit: Set status Target Running LED. diff --git a/source/hic_hal/nxp/lpc4322/IO_Config.h b/source/hic_hal/nxp/lpc4322/IO_Config.h index 1c645222c..ec3d0057e 100644 --- a/source/hic_hal/nxp/lpc4322/IO_Config.h +++ b/source/hic_hal/nxp/lpc4322/IO_Config.h @@ -67,6 +67,11 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC4322); #define PIN_ISPCTRL_IN_BIT 11 #define PIN_ISPCTRL (1< Date: Sat, 4 Dec 2021 22:45:28 -0600 Subject: [PATCH 532/617] lpc4322 (core): set CGU to use 120 MHz core clock --- docs/hic/README.md | 2 +- docs/hic/lpc4322.md | 4 ++-- records/hic_hal/lpc4322.yaml | 2 +- source/hic_hal/nxp/lpc4322/board_LPC43xx.c | 4 ++-- source/hic_hal/nxp/lpc4322/lpc43xx_cgu.c | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/docs/hic/README.md b/docs/hic/README.md index 5b097759e..40f819c5e 100644 --- a/docs/hic/README.md +++ b/docs/hic/README.md @@ -7,7 +7,7 @@ | [kl26z](kl26z.md) | M0+ | 48 Mhz | 16 KB | 128 KB | FS | | [kl27z](kl27z.md) | M0+ | 48 Mhz | 32 KB | 128 KB | FS | | [lpc11u35](lpc11u35.md) | M0 | 48 Mhz | 12 KB | 64 KB | FS | -| [lpc4322](lpc4322.md) | M4 | 96 MHz | 256 KB | 256 KB | HS | +| [lpc4322](lpc4322.md) | M4 | 120 MHz | 256 KB | 256 KB | HS | | [lpc55xx](lpc55xx.md) | M33 | 150 MHz | 272 KB | 320 KB | HS | | [max32625](max32625.md) | M4 | 96 MHz | 160 KB | 512 KB | FS | | [nrf52820](nrf52820.md) | M4 | 64 MHz | 32 KB | 256 KB | FS | diff --git a/docs/hic/lpc4322.md b/docs/hic/lpc4322.md index 35d156961..c947d65c6 100644 --- a/docs/hic/lpc4322.md +++ b/docs/hic/lpc4322.md @@ -1,7 +1,7 @@ # lpc4322 HIC Based on LPC4322JET100E chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet/LPC435X_3X_2X_1X.pdf)): -- Cortex-M4 204 Mhz +- Cortex-M4 204 Mhz (currently run at 120 MHz) - 512 KB Flash - 104 KB RAM - High-speed USB 2.0 device controller @@ -16,7 +16,7 @@ Based on LPC4322JET100E chip ([Data Sheet](https://www.nxp.com/docs/en/data-shee Bootloader size is 64 KB -## DAPLink default pin assignment +## DAPLink default pin assignment | Signal | I/O | Symbol | Pin | |-------------|:---:|---------|:---:| diff --git a/records/hic_hal/lpc4322.yaml b/records/hic_hal/lpc4322.yaml index f21e22093..11fa4ee1a 100644 --- a/records/hic_hal/lpc4322.yaml +++ b/records/hic_hal/lpc4322.yaml @@ -8,7 +8,7 @@ common: - CORE_M4 - INTERNAL_FLASH - DAPLINK_HIC_ID=0x97969905 # DAPLINK_HIC_ID_LPC4322 - - OS_CLOCK=96000000 + - OS_CLOCK=120000000 includes: - source/hic_hal/nxp/lpc4322 - source/hic_hal/nxp/lpc4322/RTE_Driver diff --git a/source/hic_hal/nxp/lpc4322/board_LPC43xx.c b/source/hic_hal/nxp/lpc4322/board_LPC43xx.c index 929409871..367366f58 100644 --- a/source/hic_hal/nxp/lpc4322/board_LPC43xx.c +++ b/source/hic_hal/nxp/lpc4322/board_LPC43xx.c @@ -24,8 +24,8 @@ void sdk_init(void) { - /* Set core clock to 96MHz */ - CGU_Init(96000000); + /* Set core clock to 120MHz */ + CGU_Init(120000000); /* Set up USB0 clock */ /* Disable PLL first */ CGU_EnableEntity(CGU_CLKSRC_PLL0, DISABLE); diff --git a/source/hic_hal/nxp/lpc4322/lpc43xx_cgu.c b/source/hic_hal/nxp/lpc4322/lpc43xx_cgu.c index 872ff92c5..867cc2fb4 100644 --- a/source/hic_hal/nxp/lpc4322/lpc43xx_cgu.c +++ b/source/hic_hal/nxp/lpc4322/lpc43xx_cgu.c @@ -244,7 +244,7 @@ uint32_t CGU_Init(uint32_t wantedFreq) // Setup PLL1 to 204MHz // 0. Select IRC as BASE_M4_CLK source CGU_EntityConnect(CGU_CLKSRC_IRC, CGU_BASE_M4); - SystemCoreClock = 96000000; + SystemCoreClock = 120000000; // 1. Enable the crystal oscillator CGU_SetXTALOSC(12000000); CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE); From a7e5c803228186572136576a898d6d1651d01048 Mon Sep 17 00:00:00 2001 From: Alex Yang Date: Fri, 1 May 2020 20:09:13 +0300 Subject: [PATCH 533/617] Add MIMXRT1170-EVK board support Signed-off-by: Alex Yang Signed-off-by: Adrian Negreanu --- projects.yaml | 4 + records/board/mimxrt1170_evk_qspi.yaml | 11 +++ source/board/mimxrt1170_evk.c | 34 +++++++ source/family/freescale/target_reset_mimxrt.c | 9 +- .../nxp/mimxrt1170_spi_flash/flash_blob.c | 98 +++++++++++++++++++ .../family/nxp/mimxrt1170_spi_flash/target.c | 37 +++++++ 6 files changed, 191 insertions(+), 2 deletions(-) create mode 100644 records/board/mimxrt1170_evk_qspi.yaml create mode 100644 source/board/mimxrt1170_evk.c create mode 100644 source/family/nxp/mimxrt1170_spi_flash/flash_blob.c create mode 100644 source/family/nxp/mimxrt1170_spi_flash/target.c diff --git a/projects.yaml b/projects.yaml index a43151106..42c552479 100644 --- a/projects.yaml +++ b/projects.yaml @@ -462,6 +462,10 @@ projects: - *module_if - *module_hic_lpc4322 - records/board/lpc55S69xpresso.yaml + lpc4322_mimxrt1170_evk_qspi_if: + - *module_if + - *module_hic_lpc4322 + - records/board/mimxrt1170_evk_qspi.yaml lpc55s69_mculink_bl: - *module_bl - records/hic_hal/lpc55s69.yaml diff --git a/records/board/mimxrt1170_evk_qspi.yaml b/records/board/mimxrt1170_evk_qspi.yaml new file mode 100644 index 000000000..a3de718a2 --- /dev/null +++ b/records/board/mimxrt1170_evk_qspi.yaml @@ -0,0 +1,11 @@ +common: + macros: + - SOFT_RESET=VECTRESET + includes: + - source/family/nxp/mimxrt1170_spi_flash + sources: + board: + - source/board/mimxrt1170_evk.c + target: + - source/family/nxp/mimxrt1170_spi_flash/target.c + - source/family/freescale/target_reset_mimxrt.c diff --git a/source/board/mimxrt1170_evk.c b/source/board/mimxrt1170_evk.c new file mode 100644 index 000000000..4a1900278 --- /dev/null +++ b/source/board/mimxrt1170_evk.c @@ -0,0 +1,34 @@ +/** + * @file mimxrt1170_evk.c + * @brief board ID for the NXP MIMXRT1170-EVK board. + * + * DAPLink Interface Firmware + * Copyright (c) 2020 - 2021 NXP, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_board.h" +#include "target_family.h" + +const board_info_t g_board_info = { + .info_version = kBoardInfoVersion, + .board_id = "0244", + .family_id = kNXP_Mimxrt_FamilyID, + .flags = kEnablePageErase, + .daplink_url_name = "PRODINFOHTM", + .daplink_drive_name = "RT1170-EVK", + .daplink_target_url = "http://www.nxp.com/imxrt1170evk", + .target_cfg = &target_device, +}; diff --git a/source/family/freescale/target_reset_mimxrt.c b/source/family/freescale/target_reset_mimxrt.c index 9fb589c70..bd91e7bff 100644 --- a/source/family/freescale/target_reset_mimxrt.c +++ b/source/family/freescale/target_reset_mimxrt.c @@ -21,6 +21,7 @@ #include "swd_host.h" #include "info.h" +#include "target_config.h" #include "target_family.h" #include "cmsis_os2.h" @@ -49,12 +50,16 @@ static uint8_t validate_bin_nvic(const uint8_t *buf) { if(buf[0] == 'F' && buf[1] == 'C' && buf[2] == 'F' && buf[3] == 'B') { + target_device.flash_regions[0].start = 0x30000400; return 1; } - else + else if(buf[0] == 0xFF && buf[1] == 0xFF && buf[2] == 0xFF && buf[3] == 0xFF) { - return 0; + target_device.flash_regions[0].start = 0x30000000; + return 1; } + + return 0; } const target_family_descriptor_t g_nxp_mimxrt = { diff --git a/source/family/nxp/mimxrt1170_spi_flash/flash_blob.c b/source/family/nxp/mimxrt1170_spi_flash/flash_blob.c new file mode 100644 index 000000000..92d6373d8 --- /dev/null +++ b/source/family/nxp/mimxrt1170_spi_flash/flash_blob.c @@ -0,0 +1,98 @@ +/* Flash OS Routines (Automagically Generated) + * Copyright (c) 2020 - 2021 NXP, All Rights Reserved + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +static const uint32_t DAPLINK_RT1170_flash_prog_blob[] = { + 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0x4770ba40, 0x4770ba40, 0x4770bac0, 0x4770bac0, 0x49414770, 0x4449b510, 0x460a483e, 0x493f6008, + 0x44492001, 0xf894f000, 0xd1062800, 0x2001493b, 0xf0004449, 0x2800f878, 0x2001d000, 0x2000bd10, + 0xb5704770, 0x460d4613, 0x4604460a, 0x46184601, 0xf8b2f000, 0xd0012800, 0xbd702000, 0xbd701960, + 0x4f2db5f8, 0x4d2e2600, 0x4634444f, 0x444d1f3f, 0x492a6c6b, 0x43604618, 0x44491982, 0xf0002001, + 0x1c64f86d, 0x2c806038, 0xbdf8dbf2, 0x0107b5f8, 0x093f4e23, 0x444e2400, 0x4628e00d, 0x491f4360, + 0x462b19c2, 0x20014449, 0xf858f000, 0x4449491a, 0x1c641f09, 0x6c756008, 0x46292001, 0xf0000300, + 0x42a0f8a8, 0x4814d8e9, 0x1f004448, 0xbdf86800, 0x0106b570, 0x09364812, 0x6c444448, 0x46214615, + 0xf0004630, 0x2900f896, 0x490cd106, 0x46324623, 0x20014449, 0xf832f000, 0x462b4908, 0x44494632, + 0xf0002001, 0x4904f816, 0x1f094449, 0xbd706008, 0x00004770, 0xc0000005, 0x00000008, 0x00000010, + 0x00000190, 0x22214770, 0x69d20412, 0x685268d2, 0xb4304710, 0x04242421, 0x68e469e4, 0x46a468a4, + 0x4760bc30, 0x04122221, 0x68d269d2, 0x471068d2, 0x041b2321, 0x68db69db, 0x47186a5b, 0x2421b430, + 0x69e40424, 0x692468e4, 0xbc3046a4, 0xb5384760, 0x94009c04, 0x04242421, 0x68e469e4, 0x47a06964, + 0xb430bd38, 0x04242421, 0x68e469e4, 0x46a46a24, 0x4760bc30, 0x04122221, 0x68d269d2, 0x471069d2, + 0x04092121, 0x68c969c9, 0x47086989, 0x04122221, 0x68d269d2, 0x47106b92, 0xb5104603, 0x079b430b, + 0x2a04d10f, 0xc808d30d, 0x1f12c910, 0xd0f842a3, 0xba21ba18, 0xd9014288, 0xbd102001, 0x43c02000, + 0x2a00bd10, 0x07d3d003, 0x1c52d003, 0x2000e007, 0x7803bd10, 0x1c40780c, 0x1b1b1c49, 0x7803d107, + 0x1c40780c, 0x1b1b1c49, 0x1e92d101, 0x4618d1f1, 0x2200bd10, 0x428b0903, 0x0a03d32c, 0xd311428b, + 0x469c2300, 0x4603e04e, 0xd43c430b, 0x08432200, 0xd331428b, 0x428b0903, 0x0a03d31c, 0xd301428b, + 0xe03f4694, 0x428b09c3, 0x01cbd301, 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0, 0x428b0943, + 0x014bd301, 0x41521ac0, 0x428b0903, 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301, 0x41521ac0, + 0x428b0883, 0x008bd301, 0x41521ac0, 0x428b0843, 0x004bd301, 0x41521ac0, 0xd2001a41, 0x41524601, + 0x47704610, 0x0fcae05d, 0x4249d000, 0xd3001003, 0x40534240, 0x469c2200, 0x428b0903, 0x0a03d32d, + 0xd312428b, 0x018922fc, 0x0a03ba12, 0xd30c428b, 0x11920189, 0xd308428b, 0x11920189, 0xd304428b, + 0xd03a0189, 0xe0001192, 0x09c30989, 0xd301428b, 0x1ac001cb, 0x09834152, 0xd301428b, 0x1ac0018b, + 0x09434152, 0xd301428b, 0x1ac0014b, 0x09034152, 0xd301428b, 0x1ac0010b, 0x08c34152, 0xd301428b, + 0x1ac000cb, 0x08834152, 0xd301428b, 0x1ac0008b, 0xd2d94152, 0x428b0843, 0x004bd301, 0x41521ac0, + 0xd2001a41, 0x46634601, 0x105b4152, 0xd3014610, 0x2b004240, 0x4249d500, 0x46634770, 0xd300105b, + 0xb5014240, 0x46c02000, 0xbd0246c0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 +}; + +// Start address of flash +static const uint32_t flash_start = 0x30000000; +// Size of flash +static const uint32_t flash_size = 0x00800000; + +/** +* List of start and size for each size of flash sector - even indexes are start, odd are size +* The size will apply to all sectors between the listed address and the next address +* in the list. +* The last pair in the list will have sectors starting at that address and ending +* at address flash_start + flash_size. +*/ +static const sector_info_t sectors_info[] = { + {0x30000000, 0x00001000}, +}; + +static const program_target_t flash = { + 0x20000033, // .init + 0x2000005f, // .uninit + 0x20000081, // .erase_chip + 0x200000ad, // .erase_sector + 0x200000f1, // .program_page + 0x0, // .verify + { // .sys_call_s + 0x20000001, // .breakpoint : start of blob + 1 + 0x2000038C, // .static_base : blob start + header + rw data offset + 0x20002800 // .stack_pointer + }, + 0x20000000 + 0x00003000, // mem buffer location + 0x20000000, // location to write prog_blob in target RAM + sizeof(DAPLINK_RT1170_flash_prog_blob), // prog_blob size + DAPLINK_RT1170_flash_prog_blob, // address of prog_blob + 0x00000100 // .algo_flags: ram_to_flash_bytes_to_be_written +}; diff --git a/source/family/nxp/mimxrt1170_spi_flash/target.c b/source/family/nxp/mimxrt1170_spi_flash/target.c new file mode 100644 index 000000000..0f2a9c9cf --- /dev/null +++ b/source/family/nxp/mimxrt1170_spi_flash/target.c @@ -0,0 +1,37 @@ +/** + * @file target.c + * @brief Target information for the NXP MIMXRT1170-EVK board. + * + * DAPLink Interface Firmware + * Copyright (c) 2020 - 2021 NXP, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_config.h" + +// The file flash_blob.c must only be included in target.c +#include "flash_blob.c" + + // target information +target_cfg_t target_device = { + .sectors_info = sectors_info, + .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), + .flash_regions[0].start = 0x30000000, + .flash_regions[0].end = 0x30000000 + MB(64), + .flash_regions[0].flags = kRegionIsDefault, + .flash_regions[0].flash_algo = (program_target_t *) &flash, + .ram_regions[0].start = 0x30000000, + .ram_regions[0].end = 0x30000000 + MB(64), +}; From ad3dc1c666ada115bfdab1de67faad2525595516 Mon Sep 17 00:00:00 2001 From: Adrian Negreanu Date: Tue, 16 Jun 2020 19:57:31 +0300 Subject: [PATCH 534/617] MIMXRT1170-EVK: enable SWO Signed-off-by: Adrian Negreanu --- records/board/mimxrt1170_evk_qspi.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/records/board/mimxrt1170_evk_qspi.yaml b/records/board/mimxrt1170_evk_qspi.yaml index a3de718a2..4bfe4b763 100644 --- a/records/board/mimxrt1170_evk_qspi.yaml +++ b/records/board/mimxrt1170_evk_qspi.yaml @@ -1,6 +1,8 @@ common: macros: - SOFT_RESET=VECTRESET + - SWO_UART=1 + - SWO_USART_PORT=1 includes: - source/family/nxp/mimxrt1170_spi_flash sources: From 20d7a7a31e5f66434eed740c03e6cea9737a9176 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sun, 5 Dec 2021 00:42:41 -0600 Subject: [PATCH 535/617] MIMXRT1170-EVK: CMSIS-DAP 2.1 updates --- records/board/mimxrt1170_evk_qspi.yaml | 3 --- source/board/mimxrt1170_evk.c | 4 +++- source/family/nxp/mimxrt1170_spi_flash/target.c | 3 +++ 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/records/board/mimxrt1170_evk_qspi.yaml b/records/board/mimxrt1170_evk_qspi.yaml index 4bfe4b763..99c5bb8ee 100644 --- a/records/board/mimxrt1170_evk_qspi.yaml +++ b/records/board/mimxrt1170_evk_qspi.yaml @@ -2,9 +2,6 @@ common: macros: - SOFT_RESET=VECTRESET - SWO_UART=1 - - SWO_USART_PORT=1 - includes: - - source/family/nxp/mimxrt1170_spi_flash sources: board: - source/board/mimxrt1170_evk.c diff --git a/source/board/mimxrt1170_evk.c b/source/board/mimxrt1170_evk.c index 4a1900278..1c5a60757 100644 --- a/source/board/mimxrt1170_evk.c +++ b/source/board/mimxrt1170_evk.c @@ -27,8 +27,10 @@ const board_info_t g_board_info = { .board_id = "0244", .family_id = kNXP_Mimxrt_FamilyID, .flags = kEnablePageErase, - .daplink_url_name = "PRODINFOHTM", + .daplink_url_name = "PRODINFOHTM", .daplink_drive_name = "RT1170-EVK", .daplink_target_url = "http://www.nxp.com/imxrt1170evk", .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "MIMXRT1170-EVK", }; diff --git a/source/family/nxp/mimxrt1170_spi_flash/target.c b/source/family/nxp/mimxrt1170_spi_flash/target.c index 0f2a9c9cf..dd77f2c63 100644 --- a/source/family/nxp/mimxrt1170_spi_flash/target.c +++ b/source/family/nxp/mimxrt1170_spi_flash/target.c @@ -26,6 +26,7 @@ // target information target_cfg_t target_device = { + .version = kTargetConfigVersion, .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x30000000, @@ -34,4 +35,6 @@ target_cfg_t target_device = { .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x30000000, .ram_regions[0].end = 0x30000000 + MB(64), + .target_vendor = "NXP", + .target_part_number = "MIMXRT1176DVMAA", }; From 34f4d2496610ebbf664d4f16ac1049af9404c139 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sun, 5 Dec 2021 01:09:06 -0600 Subject: [PATCH 536/617] Add MIMXRT1060-EVK board support --- projects.yaml | 4 + records/board/mimxrt1060_evk_qspi.yaml | 10 ++ source/board/mimxrt1060_evk.c | 36 +++++ .../nxp/mimxrt1060_spi_flash/flash_blob.c | 150 ++++++++++++++++++ .../family/nxp/mimxrt1060_spi_flash/target.c | 40 +++++ 5 files changed, 240 insertions(+) create mode 100644 records/board/mimxrt1060_evk_qspi.yaml create mode 100644 source/board/mimxrt1060_evk.c create mode 100644 source/family/nxp/mimxrt1060_spi_flash/flash_blob.c create mode 100644 source/family/nxp/mimxrt1060_spi_flash/target.c diff --git a/projects.yaml b/projects.yaml index 42c552479..7a78f864b 100644 --- a/projects.yaml +++ b/projects.yaml @@ -462,6 +462,10 @@ projects: - *module_if - *module_hic_lpc4322 - records/board/lpc55S69xpresso.yaml + lpc4322_mimxrt1060_evk_qspi_if: + - *module_if + - *module_hic_lpc4322 + - records/board/mimxrt1060_evk_qspi.yaml lpc4322_mimxrt1170_evk_qspi_if: - *module_if - *module_hic_lpc4322 diff --git a/records/board/mimxrt1060_evk_qspi.yaml b/records/board/mimxrt1060_evk_qspi.yaml new file mode 100644 index 000000000..b082e612e --- /dev/null +++ b/records/board/mimxrt1060_evk_qspi.yaml @@ -0,0 +1,10 @@ +common: + macros: + - SOFT_RESET=VECTRESET + - SWO_UART=1 + sources: + board: + - source/board/mimxrt1060_evk.c + target: + - source/family/nxp/mimxrt1060_spi_flash/target.c + - source/family/freescale/target_reset_mimxrt.c diff --git a/source/board/mimxrt1060_evk.c b/source/board/mimxrt1060_evk.c new file mode 100644 index 000000000..597ad9d2c --- /dev/null +++ b/source/board/mimxrt1060_evk.c @@ -0,0 +1,36 @@ +/** + * @file mimxrt1060_evk.c + * @brief board ID for the NXP MIMXRT1060-EVK board. + * + * DAPLink Interface Firmware + * Copyright (c) 2020 - 2021 NXP, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_board.h" +#include "target_family.h" + +const board_info_t g_board_info = { + .info_version = kBoardInfoVersion, + .board_id = "0229", + .family_id = kNXP_Mimxrt_FamilyID, + .flags = kEnablePageErase, + .daplink_url_name = "PRODINFOHTM", + .daplink_drive_name = "RT1060-EVK", + .daplink_target_url = "http://www.nxp.com/imxrt1060evk", + .target_cfg = &target_device, + .board_vendor = "NXP", + .board_name = "MIMXRT1060-EVK", +}; diff --git a/source/family/nxp/mimxrt1060_spi_flash/flash_blob.c b/source/family/nxp/mimxrt1060_spi_flash/flash_blob.c new file mode 100644 index 000000000..abf5b4346 --- /dev/null +++ b/source/family/nxp/mimxrt1060_spi_flash/flash_blob.c @@ -0,0 +1,150 @@ +/* Flash OS Routines (Automagically Generated) + * Copyright (c) 2009-2021 Arm Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +static const uint32_t MIMXRT106x_QSPI_4KB_SEC_flash_prog_blob[] = { + 0xE00ABE00, + 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x4855b51c, 0x48559000, + 0x08498901, 0x81010049, 0x890a4953, 0x00520852, 0x8802810a, 0x07522304, 0xda022a00, 0x439a8802, + 0x88088002, 0xd5020740, 0x43988808, 0x484c8008, 0x6041494a, 0x6081494b, 0x22806801, 0x22204391, + 0x60014311, 0xf8a8f000, 0x68014847, 0xd54503c9, 0x60014946, 0x29006801, 0x6b01dafc, 0x03122201, + 0x63014391, 0x29006b01, 0x4a42dafc, 0x60114940, 0x03092103, 0x69016101, 0xdafc2900, 0x22016901, + 0x43910412, 0x4b3b6101, 0x3b40493b, 0x493b6319, 0x610b2301, 0x4c3a694b, 0x00544023, 0x2405191b, + 0x43230264, 0x698b614b, 0x40234c36, 0x04a42403, 0x4c35191b, 0x618b4323, 0x4c3469cb, 0x24034023, + 0x191b0764, 0x43234c32, 0x680161cb, 0x60014391, 0x43916b01, 0x69016301, 0x61014391, 0x466a492d, + 0x20004449, 0xf9d3f000, 0xd1052800, 0x44494929, 0xf9b8f000, 0xd0002800, 0xbd1c2001, 0x47702000, + 0xb5104924, 0x20004449, 0xf9bbf000, 0xd0002800, 0xbd102001, 0x07492105, 0x491e1842, 0x2301b510, + 0x4449041b, 0xf0002000, 0x2800f9b8, 0x2001d000, 0x2105bd10, 0x07494613, 0x49161842, 0x4449b510, + 0xf0002000, 0x2800f995, 0x2001d000, 0x0000bd10, 0xc0000006, 0x400b8000, 0x400d0000, 0xd928c520, + 0x400bc000, 0x0000ffff, 0x400d8000, 0x00012018, 0x18131818, 0x400d8100, 0x0f1a2323, 0x400fc000, + 0xfff8e0ff, 0x1ff3fcff, 0xe0000100, 0x9c7fff80, 0x03800001, 0x0000000c, 0x49d42001, 0x69c00540, + 0x60084449, 0x4ad14770, 0x6812444a, 0x68526992, 0x49ce4710, 0x68094449, 0x68896989, 0x4acb4708, + 0x6812444a, 0x68d26992, 0x49c84710, 0x68094449, 0x69096989, 0x4ac54708, 0x6812444a, 0x69526992, + 0x49c24710, 0x68094449, 0x69896989, 0x49bf4708, 0x68094449, 0x69c96989, 0x49bc4708, 0x68094449, + 0x6a096989, 0x4bb94708, 0x681b444b, 0x6a5b699b, 0x48b64718, 0x68004448, 0x6ac06980, 0x48b34700, + 0x68004448, 0x6bc06980, 0x49b04700, 0x68094449, 0x6c096989, 0x49ad4708, 0x68094449, 0x6c496989, + 0x49aa4708, 0x68094449, 0x6b096989, 0x48a74708, 0x68004448, 0x6b406980, 0x49a44700, 0x68094449, + 0x6b896989, 0x48a14708, 0x68004448, 0x6c806980, 0x489e4700, 0x68004448, 0x6cc06980, 0x499b4700, + 0x68094449, 0x6a896989, 0x4a984708, 0x6812444a, 0x32806992, 0x47106a52, 0x444a4a94, 0x69926812, + 0x6b123280, 0x4a914710, 0x6812444a, 0x32806992, 0x47106a92, 0x4448488d, 0x69806800, 0x6ac03080, + 0x498a4700, 0x68094449, 0x6d096989, 0x48874708, 0x68004448, 0x6d406980, 0x49844700, 0x68094449, + 0x6d896989, 0x48814708, 0x68004448, 0x6dc06980, 0x497e4700, 0x68094449, 0x6e096989, 0x487b4708, + 0x68004448, 0x6e406980, 0x49784700, 0x68094449, 0x6e896989, 0x48754708, 0x68004448, 0x6ec06980, + 0x49724700, 0x68094449, 0x6f096989, 0x486f4708, 0x68004448, 0x6f406980, 0x496c4700, 0x68094449, + 0x6f896989, 0x48694708, 0x68004448, 0x6fc06980, 0x49664700, 0x68094449, 0x31806989, 0x47086809, + 0x44484862, 0x69806800, 0x68403080, 0x495f4700, 0x68094449, 0x31806989, 0x47086889, 0x444a4a5b, + 0x69926812, 0x68d23280, 0x49584710, 0x68094449, 0x31806989, 0x47086909, 0x444a4a54, 0x69926812, + 0x69523280, 0x49514710, 0x68094449, 0x31806989, 0x47086989, 0x4449494d, 0x69896809, 0x69c93180, + 0x494a4708, 0x68094449, 0x31806989, 0x47086a09, 0x444a4a46, 0x69926812, 0x6b523280, 0x48434710, + 0x68004448, 0x30806980, 0x47006b80, 0x444a4a3f, 0x69d26812, 0x47106a12, 0x4449493c, 0x69c96809, + 0x47086809, 0x444a4a39, 0x69d26812, 0x47106852, 0x44494936, 0x69c96809, 0x47086889, 0x44494933, + 0x6a096809, 0x47086809, 0x444a4a30, 0x6a126812, 0x47106852, 0x4449492d, 0x6a096809, 0x47086889, + 0x4449492a, 0x6a096809, 0x47086989, 0x444a4a27, 0x6a126812, 0x471069d2, 0x44494924, 0x6a096809, + 0x47086ac9, 0x444a4a21, 0x69126812, 0x47106852, 0x4c1eb430, 0x6824444c, 0x68a46924, 0xbc3046a4, + 0x4a1a4760, 0x6812444a, 0x68d26912, 0x4b174710, 0x681b444b, 0x6a5b691b, 0xb4304718, 0x444c4c13, + 0x69246824, 0x46a46924, 0x4760bc30, 0x9c04b538, 0x4c0e9400, 0x6824444c, 0x69646924, 0xbd3847a0, + 0x4c0ab430, 0x6824444c, 0x6a246924, 0xbc3046a4, 0x4a064760, 0x6812444a, 0x69d26912, 0x49034710, + 0x68094449, 0x69896909, 0x00004708, 0x00000004, 0xb5104770, 0x89014857, 0x00490849, 0x49568101, + 0x0852890a, 0x810a0052, 0x23048802, 0x2a000752, 0x8802da02, 0x8002439a, 0x07408808, 0x8808d502, + 0x80084398, 0x494d484e, 0x494e6041, 0x68016081, 0x43912280, 0x43112220, 0x484b6001, 0x07c96901, + 0x6901d003, 0x00490849, 0xf7ff6101, 0xbd10ffd1, 0x4d46b5f8, 0x4a466968, 0x01804946, 0x69a8d522, + 0x031b2303, 0xd0074018, 0x031b2301, 0xd00c1ac0, 0xd1084298, 0xe0066b10, 0x03c06910, 0xd5066910, + 0x0f800400, 0x2000d001, 0x4608e008, 0x0780e006, 0x2016d501, 0x2014e000, 0x43484936, 0x00896969, + 0xe03d0f49, 0x03c06810, 0xd5066810, 0x0f800400, 0x2700d001, 0x460fe006, 0x0640e004, 0x0e404b2d, + 0x08474358, 0x03c06b10, 0xd5066b10, 0x0f800400, 0x2400d001, 0x460ce008, 0x07c0e006, 0x2416d001, + 0x2414e000, 0x43444823, 0x30404821, 0x69006a06, 0xf976f000, 0x23004632, 0xf844f000, 0x190069a9, + 0x40114a1d, 0x2201d011, 0x4b1c0492, 0xd0161a89, 0xd0171a89, 0xd1074291, 0x07416928, 0x46380f49, + 0xf0001c49, 0xe000f8b0, 0x69692000, 0x0f4904c9, 0xf0001c49, 0x4912f8a8, 0x60084449, 0x6819bdf8, + 0xe0000c09, 0x06896819, 0xf0000e89, 0x2112f89c, 0xe7ea4348, 0x400b8000, 0x400d0000, 0xd928c520, + 0x400bc000, 0x0000ffff, 0xe000e000, 0x400fc000, 0x400d8000, 0x016e3600, 0x000c0000, 0x400d8100, + 0x00000008, 0x4605b5fe, 0x460c4610, 0xd0734318, 0x468c46ae, 0x1aad2000, 0x419c4601, 0x4666d367, + 0x24012700, 0x1ab6463d, 0xd302419d, 0x463a4613, 0x46652421, 0x042f4676, 0x433e0c36, 0x1ab60c2d, + 0xd304419d, 0x041b0c15, 0x0412432b, 0x46653410, 0x062f4676, 0x433e0a36, 0x1ab60a2d, 0xd304419d, + 0x021b0e15, 0x0212432b, 0x46653408, 0x072f4676, 0x433e0936, 0x1ab6092d, 0xd304419d, 0x011b0f15, + 0x0112432b, 0x46651d24, 0x07af4676, 0x433e08b6, 0x1ab608ad, 0xd304419d, 0x009b0f95, 0x0092432b, + 0x46651ca4, 0x07ef4676, 0x433e0876, 0x1ab6086d, 0xd31a419d, 0x415b1892, 0xe0161c64, 0x46761800, + 0x41494665, 0x419d1ab7, 0x90009101, 0x4660d309, 0x41981ab1, 0x4684468e, 0x99019800, 0x1c402500, + 0x07dd4169, 0x432a0852, 0x1e64085b, 0x4672d5e6, 0xb0034663, 0xe7ffbdf0, 0x46012000, 0x46c046c0, + 0x4623462a, 0x2200e7f5, 0x428b0903, 0x0a03d32c, 0xd311428b, 0x469c2300, 0x4603e04e, 0xd43c430b, + 0x08432200, 0xd331428b, 0x428b0903, 0x0a03d31c, 0xd301428b, 0xe03f4694, 0x428b09c3, 0x01cbd301, + 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0, 0x428b0943, 0x014bd301, 0x41521ac0, 0x428b0903, + 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301, 0x41521ac0, 0x428b0883, 0x008bd301, 0x41521ac0, + 0x428b0843, 0x004bd301, 0x41521ac0, 0xd2001a41, 0x41524601, 0x47704610, 0x0fcae05d, 0x4249d000, + 0xd3001003, 0x40534240, 0x469c2200, 0x428b0903, 0x0a03d32d, 0xd312428b, 0x018922fc, 0x0a03ba12, + 0xd30c428b, 0x11920189, 0xd308428b, 0x11920189, 0xd304428b, 0xd03a0189, 0xe0001192, 0x09c30989, + 0xd301428b, 0x1ac001cb, 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152, 0xd301428b, 0x1ac0014b, + 0x09034152, 0xd301428b, 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb, 0x08834152, 0xd301428b, + 0x1ac0008b, 0xd2d94152, 0x428b0843, 0x004bd301, 0x41521ac0, 0xd2001a41, 0x46634601, 0x105b4152, + 0xd3014610, 0x2b004240, 0x4249d500, 0x46634770, 0xd300105b, 0xb5014240, 0x46c02000, 0xbd0246c0, + 0x0c04b5f8, 0x4626b28b, 0x435eb282, 0x46100c0d, 0x43580c37, 0x19800436, 0x41792100, 0x436e4616, + 0x04360c37, 0x41791980, 0x436e4626, 0xbdf81989, 0x00000000, 0x00000000, 0x1f78a400, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 +}; + +// Start address of flash +static const uint32_t flash_start = 0x60000000; +// Size of flash +static const uint32_t flash_size = 0x00800000; + +/** +* List of start and size for each size of flash sector - even indexes are start, odd are size +* The size will apply to all sectors between the listed address and the next address +* in the list. +* The last pair in the list will have sectors starting at that address and ending +* at address flash_start + flash_size. +*/ +static const sector_info_t sectors_info[] = { + 0x60000000, 0x00010000, +}; + +static const program_target_t flash = { + 0x2000001d, // Init + 0x20000121, // UnInit + 0x20000125, // EraseChip + 0x20000139, // EraseSector + 0x20000157, // ProgramPage + 0x0, // Verify + + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + { + 0x20000001, + 0x20000934, + 0x20000c00 + }, + + 0x20000000 + 0x00000A00, // mem buffer location + 0x20000000, // location to write prog_blob in target RAM + sizeof(MIMXRT106x_QSPI_4KB_SEC_flash_prog_blob), // prog_blob size + MIMXRT106x_QSPI_4KB_SEC_flash_prog_blob, // address of prog_blob + 0x00000100 // ram_to_flash_bytes_to_be_written +}; diff --git a/source/family/nxp/mimxrt1060_spi_flash/target.c b/source/family/nxp/mimxrt1060_spi_flash/target.c new file mode 100644 index 000000000..ee754d80b --- /dev/null +++ b/source/family/nxp/mimxrt1060_spi_flash/target.c @@ -0,0 +1,40 @@ +/** + * @file target.c + * @brief Target information for the i.MXRT1060 (QSPI Flash) + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2021, Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_config.h" + +// The file flash_blob.c must only be included in target.c +#include "flash_blob.c" + +// target information +target_cfg_t target_device = { + .version = kTargetConfigVersion, + .sectors_info = sectors_info, + .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), + .flash_regions[0].start = 0x60000000, + .flash_regions[0].end = 0x60000000 + MB(8), + .flash_regions[0].flags = kRegionIsDefault, + .flash_regions[0].flash_algo = (program_target_t *) &flash, + .ram_regions[0].start = 0x20000000, + .ram_regions[0].end = 0x20000000 + KB(512), + .target_vendor = "NXP", + .target_part_number = "MIMXRT1062DVL6A", +}; From 2a3f33d538d6fad3afbd3221b8eafcea8ee56603 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 6 Dec 2021 13:29:09 -0600 Subject: [PATCH 537/617] Compilation fix for MIMXRT reset Only include `validate_bin_nvic` in projects with i.MX RT target --- records/board/mimxrt1020_evk_qspi.yaml | 1 + records/board/mimxrt1050_evk_hyper.yaml | 1 + records/board/mimxrt1050_evk_qspi.yaml | 1 + records/board/mimxrt1060_evk_qspi.yaml | 1 + records/board/mimxrt1170_evk_qspi.yaml | 1 + source/family/freescale/target_reset_mimxrt.c | 4 ++++ 6 files changed, 9 insertions(+) diff --git a/records/board/mimxrt1020_evk_qspi.yaml b/records/board/mimxrt1020_evk_qspi.yaml index 6cba7d492..50aae68b1 100644 --- a/records/board/mimxrt1020_evk_qspi.yaml +++ b/records/board/mimxrt1020_evk_qspi.yaml @@ -1,5 +1,6 @@ common: macros: + - DAPLINK_MIMXRT_TARGET - SOFT_RESET=VECTRESET sources: board: diff --git a/records/board/mimxrt1050_evk_hyper.yaml b/records/board/mimxrt1050_evk_hyper.yaml index 97272f7cf..f9ef5e951 100644 --- a/records/board/mimxrt1050_evk_hyper.yaml +++ b/records/board/mimxrt1050_evk_hyper.yaml @@ -1,5 +1,6 @@ common: macros: + - DAPLINK_MIMXRT_TARGET - SOFT_RESET=VECTRESET sources: board: diff --git a/records/board/mimxrt1050_evk_qspi.yaml b/records/board/mimxrt1050_evk_qspi.yaml index cfd02ce15..7fb84546c 100644 --- a/records/board/mimxrt1050_evk_qspi.yaml +++ b/records/board/mimxrt1050_evk_qspi.yaml @@ -1,5 +1,6 @@ common: macros: + - DAPLINK_MIMXRT_TARGET - SOFT_RESET=VECTRESET sources: board: diff --git a/records/board/mimxrt1060_evk_qspi.yaml b/records/board/mimxrt1060_evk_qspi.yaml index b082e612e..f1e3a005a 100644 --- a/records/board/mimxrt1060_evk_qspi.yaml +++ b/records/board/mimxrt1060_evk_qspi.yaml @@ -1,5 +1,6 @@ common: macros: + - DAPLINK_MIMXRT_TARGET - SOFT_RESET=VECTRESET - SWO_UART=1 sources: diff --git a/records/board/mimxrt1170_evk_qspi.yaml b/records/board/mimxrt1170_evk_qspi.yaml index 99c5bb8ee..bc5cb24fc 100644 --- a/records/board/mimxrt1170_evk_qspi.yaml +++ b/records/board/mimxrt1170_evk_qspi.yaml @@ -1,5 +1,6 @@ common: macros: + - DAPLINK_MIMXRT_TARGET - SOFT_RESET=VECTRESET - SWO_UART=1 sources: diff --git a/source/family/freescale/target_reset_mimxrt.c b/source/family/freescale/target_reset_mimxrt.c index bd91e7bff..a8b49ce18 100644 --- a/source/family/freescale/target_reset_mimxrt.c +++ b/source/family/freescale/target_reset_mimxrt.c @@ -46,6 +46,7 @@ static void prerun_target_config(void) target_set_state(RESET_RUN); } +#ifdef DAPLINK_MIMXRT_TARGET static uint8_t validate_bin_nvic(const uint8_t *buf) { if(buf[0] == 'F' && buf[1] == 'C' && buf[2] == 'F' && buf[3] == 'B') @@ -61,6 +62,7 @@ static uint8_t validate_bin_nvic(const uint8_t *buf) return 0; } +#endif const target_family_descriptor_t g_nxp_mimxrt = { .family_id = kNXP_Mimxrt_FamilyID, @@ -68,5 +70,7 @@ const target_family_descriptor_t g_nxp_mimxrt = { .soft_reset_type = VECTRESET, .target_before_init_debug = target_before_init_debug, .prerun_target_config = prerun_target_config, +#ifdef DAPLINK_MIMXRT_TARGET .validate_bin_nvic = validate_bin_nvic, +#endif }; From 43e7e42854872d067be4f8e42d763b3209fa4067 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sun, 5 Dec 2021 01:11:38 -0600 Subject: [PATCH 538/617] Fixes for multiple MIMXRT boards --- source/board/mimxrt1020_evk.c | 4 ++-- source/board/mimxrt1050_evk.c | 4 ++-- source/family/freescale/mimxrt1020_spi_flash/target.c | 4 ++-- source/family/freescale/mimxrt1050_hyper_flash/target.c | 2 +- source/family/freescale/mimxrt1050_spi_flash/target.c | 4 ++-- source/family/nxp/mimxrt1170_spi_flash/target.c | 6 +++--- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/source/board/mimxrt1020_evk.c b/source/board/mimxrt1020_evk.c index 137a945da..b50f0c407 100644 --- a/source/board/mimxrt1020_evk.c +++ b/source/board/mimxrt1020_evk.c @@ -27,8 +27,8 @@ const board_info_t g_board_info = { .board_id = "0226", .family_id = kNXP_Mimxrt_FamilyID, .flags = kEnablePageErase, - .daplink_url_name = "PRODINFOHTM", - .daplink_drive_name = "RT1020-EVK", + .daplink_url_name = "PRODINFOHTM", + .daplink_drive_name = "RT1020-EVK", .daplink_target_url = "http://www.nxp.com/imxrt1020evk", .target_cfg = &target_device, .board_vendor = "NXP", diff --git a/source/board/mimxrt1050_evk.c b/source/board/mimxrt1050_evk.c index 1a497123a..02ef61b1a 100644 --- a/source/board/mimxrt1050_evk.c +++ b/source/board/mimxrt1050_evk.c @@ -26,8 +26,8 @@ const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .board_id = "0227", .family_id = kNXP_Mimxrt_FamilyID, - .daplink_url_name = "PRODINFOHTM", - .daplink_drive_name = "RT1050-EVK", + .daplink_url_name = "PRODINFOHTM", + .daplink_drive_name = "RT1050-EVK", .daplink_target_url = "http://www.nxp.com/imxrt1050evk", .target_cfg = &target_device, .board_vendor = "NXP", diff --git a/source/family/freescale/mimxrt1020_spi_flash/target.c b/source/family/freescale/mimxrt1020_spi_flash/target.c index 0e9ae5a7f..fda231de7 100644 --- a/source/family/freescale/mimxrt1020_spi_flash/target.c +++ b/source/family/freescale/mimxrt1020_spi_flash/target.c @@ -31,11 +31,11 @@ target_cfg_t target_device = { .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x60000000, - .flash_regions[0].end = 0x60000000 + MB(64), + .flash_regions[0].end = 0x60000000 + MB(8), .flash_regions[0].flags = kRegionIsDefault, .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, - .ram_regions[0].end = 0x20000000 + MB(64), + .ram_regions[0].end = 0x20000000 + KB(512), .target_vendor = "NXP", .target_part_number = "MIMXRT1021DAG5A", }; diff --git a/source/family/freescale/mimxrt1050_hyper_flash/target.c b/source/family/freescale/mimxrt1050_hyper_flash/target.c index e36390f98..27d93047f 100644 --- a/source/family/freescale/mimxrt1050_hyper_flash/target.c +++ b/source/family/freescale/mimxrt1050_hyper_flash/target.c @@ -34,7 +34,7 @@ target_cfg_t target_device = { .flash_regions[0].flags = kRegionIsDefault, .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, - .ram_regions[0].end = 0x20000000 + MB(64), + .ram_regions[0].end = 0x20000000 + KB(512), .target_vendor = "NXP", .target_part_number = "MIMXRT1052DVL6A", }; diff --git a/source/family/freescale/mimxrt1050_spi_flash/target.c b/source/family/freescale/mimxrt1050_spi_flash/target.c index f63df0435..c0c1aa2c7 100644 --- a/source/family/freescale/mimxrt1050_spi_flash/target.c +++ b/source/family/freescale/mimxrt1050_spi_flash/target.c @@ -30,11 +30,11 @@ target_cfg_t target_device = { .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x60000000, - .flash_regions[0].end = 0x60000000 + MB(64), + .flash_regions[0].end = 0x60000000 + MB(8), .flash_regions[0].flags = kRegionIsDefault, .flash_regions[0].flash_algo = (program_target_t *) &flash, .ram_regions[0].start = 0x20000000, - .ram_regions[0].end = 0x20000000 + MB(64), + .ram_regions[0].end = 0x20000000 + KB(512), .target_vendor = "NXP", .target_part_number = "MIMXRT1052DVL6A", }; diff --git a/source/family/nxp/mimxrt1170_spi_flash/target.c b/source/family/nxp/mimxrt1170_spi_flash/target.c index dd77f2c63..5d855c9c8 100644 --- a/source/family/nxp/mimxrt1170_spi_flash/target.c +++ b/source/family/nxp/mimxrt1170_spi_flash/target.c @@ -30,11 +30,11 @@ target_cfg_t target_device = { .sectors_info = sectors_info, .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), .flash_regions[0].start = 0x30000000, - .flash_regions[0].end = 0x30000000 + MB(64), + .flash_regions[0].end = 0x30000000 + MB(16), .flash_regions[0].flags = kRegionIsDefault, .flash_regions[0].flash_algo = (program_target_t *) &flash, - .ram_regions[0].start = 0x30000000, - .ram_regions[0].end = 0x30000000 + MB(64), + .ram_regions[0].start = 0x20000000, + .ram_regions[0].end = 0x20000000 + KB(512), .target_vendor = "NXP", .target_part_number = "MIMXRT1176DVMAA", }; From 6ff1ee547b47c2da1a8ba291f1b8475aa874d2f5 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 6 Dec 2021 22:38:53 -0600 Subject: [PATCH 539/617] Bump version to 0257 --- records/tools/version.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/records/tools/version.yaml b/records/tools/version.yaml index e76642cb8..f217dddb0 100644 --- a/records/tools/version.yaml +++ b/records/tools/version.yaml @@ -1,3 +1,3 @@ common: macros: - - DAPLINK_VERSION=256 + - DAPLINK_VERSION=257 From 0223662864046c31fea96c7b13cdfcc86bc8acbf Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 7 Dec 2021 18:26:43 -0600 Subject: [PATCH 540/617] lpc4322_hic: update IRQ Handler names --- .../nxp/lpc4322/armcc/startup_LPC43xx.s | 8 +- .../hic_hal/nxp/lpc4322/gcc/startup_LPC43xx.S | 243 +++++++++--------- source/hic_hal/nxp/lpc4322/uart.c | 2 +- 3 files changed, 126 insertions(+), 127 deletions(-) diff --git a/source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s b/source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s index 715a7c7dd..6833af214 100644 --- a/source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s +++ b/source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s @@ -62,12 +62,12 @@ __Vectors DCD __initial_sp ; 0 Top of Sta DCD BusFault_Handler ; 5 Bus Fault Handler DCD UsageFault_Handler ; 6 Usage Fault Handler DCD Sign_Value ; 7 Reserved - DCD DAPLINK_BUILD_KEY ; 8 DAPLINK: Build type (BL/IF) - DCD DAPLINK_HIC_ID ; 9 DAPLINK: Compatibility - DCD DAPLINK_VERSION ; 10 DAPLINK: Version + DCD DAPLINK_BUILD_KEY ; 8 DAPLINK: Build type (BL/IF) + DCD DAPLINK_HIC_ID ; 9 DAPLINK: Compatibility + DCD DAPLINK_VERSION ; 10 DAPLINK: Version DCD SVC_Handler ; 11 SVCall Handler DCD DebugMon_Handler ; 12 Debug Monitor Handler - DCD g_board_info ; 13 DAPLINK: Pointer to board/family/target info + DCD g_board_info ; 13 DAPLINK: Pointer to board/family/target info DCD PendSV_Handler ; 14 PendSV Handler DCD SysTick_Handler ; 15 SysTick Handler diff --git a/source/hic_hal/nxp/lpc4322/gcc/startup_LPC43xx.S b/source/hic_hal/nxp/lpc4322/gcc/startup_LPC43xx.S index 6bd7bffec..b7e9b1f45 100644 --- a/source/hic_hal/nxp/lpc4322/gcc/startup_LPC43xx.S +++ b/source/hic_hal/nxp/lpc4322/gcc/startup_LPC43xx.S @@ -5,7 +5,7 @@ * DAPLink Interface Firmware * Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc. * Copyright 2016 - 2017 NXP - * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2021, Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -30,77 +30,77 @@ .align 2 .globl __isr_vector __isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler*/ - .long HardFault_Handler /* Hard Fault Handler*/ - .long MemManage_Handler /* MPU Fault Handler*/ - .long BusFault_Handler /* Bus Fault Handler*/ - .long UsageFault_Handler /* Usage Fault Handler*/ - .long 0x5A5A5A5A /* Reserved*/ - .long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF)*/ - .long DAPLINK_HIC_ID /* DAPLINK: Compatibility*/ - .long DAPLINK_VERSION /* DAPLINK: Version*/ - .long SVC_Handler /* SVCall Handler*/ - .long DebugMon_Handler /* Debug Monitor Handler*/ - .long g_board_info /* DAPLINK: Pointer to board/family/target info*/ - .long PendSV_Handler /* PendSV Handler*/ - .long SysTick_Handler /* SysTick Handler*/ + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0x5A5A5A5A /* Reserved */ + .long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF) */ + .long DAPLINK_HIC_ID /* DAPLINK: Compatibility */ + .long DAPLINK_VERSION /* DAPLINK: Version */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long g_board_info /* DAPLINK: Pointer to board/family/target info */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ - /* External Interrupts*/ - .long DAC_IRQHandler /* 16 D/A Converter */ - .long M0CORE_IRQHandler /* 17 M0 Core */ - .long DMA_IRQHandler /* 18 General Purpose DMA */ - .long EZH_IRQHandler /* 19 EZH/EDM */ - .long FLASH_EEPROM_IRQHandler /* 20 Reserved for Typhoon */ - .long ETH_IRQHandler /* 21 Ethernet */ - .long SDIO_IRQHandler /* 22 SD/MMC */ - .long LCD_IRQHandler /* 23 LCD */ - .long USB0_IRQHandler /* 24 USB0 */ - .long USB1_IRQHandler /* 25 USB1 */ - .long SCT_IRQHandler /* 26 State Configurable Timer */ - .long RIT_IRQHandler /* 27 Repetitive Interrupt Timer */ - .long TIMER0_IRQHandler /* 28 Timer0 */ - .long TIMER1_IRQHandler /* 29 Timer1 */ - .long TIMER2_IRQHandler /* 30 Timer2 */ - .long TIMER3_IRQHandler /* 31 Timer3 */ - .long MCPWM_IRQHandler /* 32 Motor Control PWM */ - .long ADC0_IRQHandler /* 33 A/D Converter 0 */ - .long I2C0_IRQHandler /* 34 I2C0 */ - .long I2C1_IRQHandler /* 35 I2C1 */ - .long SPI_IRQHandler /* 36 SPI */ - .long ADC1_IRQHandler /* 37 A/D Converter 1 */ - .long SSP0_IRQHandler /* 38 SSP0 */ - .long SSP1_IRQHandler /* 39 SSP1 */ - .long UART0_IRQHandler /* 40 UART0 */ - .long UART1_IRQHandler /* 41 UART1 */ - .long UART2_IRQHandler /* 42 UART2 */ - .long UART3_IRQHandler /* 43 UART3 */ - .long I2S0_IRQHandler /* 44 I2S0 */ - .long I2S1_IRQHandler /* 45 I2S1 */ - .long SPIFI_IRQHandler /* 46 SPI Flash Interface */ - .long SGPIO_IRQHandler /* 47 SGPIO */ - .long GPIO0_IRQHandler /* 48 GPIO0 */ - .long GPIO1_IRQHandler /* 49 GPIO1 */ - .long GPIO2_IRQHandler /* 50 GPIO2 */ - .long GPIO3_IRQHandler /* 51 GPIO3 */ - .long GPIO4_IRQHandler /* 52 GPIO4 */ - .long GPIO5_IRQHandler /* 53 GPIO5 */ - .long GPIO6_IRQHandler /* 54 GPIO6 */ - .long GPIO7_IRQHandler /* 55 GPIO7 */ - .long GINT0_IRQHandler /* 56 GINT0 */ - .long GINT1_IRQHandler /* 57 GINT1 */ - .long EVRT_IRQHandler /* 58 Event Router */ - .long CAN1_IRQHandler /* 59 C_CAN1 */ - .long 0 /* 60 Reserved */ - .long VADC_IRQHandler /* 61 VADC */ - .long ATIMER_IRQHandler /* 62 ATIMER */ - .long RTC_IRQHandler /* 63 RTC */ - .long 0 /* 64 Reserved */ - .long WDT_IRQHandler /* 65 WDT */ - .long M0s_IRQHandler /* 66 M0s */ - .long CAN0_IRQHandler /* 67 C_CAN0 */ - .long QEI_IRQHandler /* 68 QEI */ + /* External LPC43xx/M4 Interrupts */ + .long DAC_IRQHandler /* 0 DAC interrupt */ + .long M0APP_IRQHandler /* 1 Cortex-M0APP; Latched TXEV; for M4-M0APP communication */ + .long DMA_IRQHandler /* 2 DMA interrupt */ + .long 0 /* 3 Reserved */ + .long FLASHEEPROM_IRQHandler /* 4 flash bank A, flash bank B, EEPROM ORed interrupt */ + .long ETHERNET_IRQHandler /* 5 Ethernet interrupt */ + .long SDIO_IRQHandler /* 6 SD/MMC interrupt */ + .long LCD_IRQHandler /* 7 LCD interrupt */ + .long USB0_IRQHandler /* 8 OTG interrupt */ + .long USB1_IRQHandler /* 9 USB1 interrupt */ + .long SCT_IRQHandler /* 10 SCT combined interrupt */ + .long RITIMER_IRQHandler /* 11 RI Timer interrupt */ + .long TIMER0_IRQHandler /* 12 Timer 0 interrupt */ + .long TIMER1_IRQHandler /* 13 Timer 1 interrupt */ + .long TIMER2_IRQHandler /* 14 Timer 2 interrupt */ + .long TIMER3_IRQHandler /* 15 Timer 3 interrupt */ + .long MCPWM_IRQHandler /* 16 Motor control PWM interrupt */ + .long ADC0_IRQHandler /* 17 ADC0 interrupt */ + .long I2C0_IRQHandler /* 18 I2C0 interrupt */ + .long I2C1_IRQHandler /* 19 I2C1 interrupt */ + .long SPI_IRQHandler /* 20 SPI interrupt */ + .long ADC1_IRQHandler /* 21 ADC1 interrupt */ + .long SSP0_IRQHandler /* 22 SSP0 interrupt */ + .long SSP1_IRQHandler /* 23 SSP1 interrupt */ + .long USART0_IRQHandler /* 24 USART0 interrupt */ + .long UART1_IRQHandler /* 25 Combined UART1, Modem interrupt */ + .long USART2_IRQHandler /* 26 USART2 interrupt */ + .long USART3_IRQHandler /* 27 Combined USART3, IrDA interrupt */ + .long I2S0_IRQHandler /* 28 I2S0 interrupt */ + .long I2S1_IRQHandler /* 29 I2S1 interrupt */ + .long SPIFI_IRQHandler /* 30 SPISI interrupt */ + .long SGPIO_IRQHandler /* 31 SGPIO interrupt */ + .long PIN_INT0_IRQHandler /* 32 GPIO pin interrupt 0 */ + .long PIN_INT1_IRQHandler /* 33 GPIO pin interrupt 1 */ + .long PIN_INT2_IRQHandler /* 34 GPIO pin interrupt 2 */ + .long PIN_INT3_IRQHandler /* 35 GPIO pin interrupt 3 */ + .long PIN_INT4_IRQHandler /* 36 GPIO pin interrupt 4 */ + .long PIN_INT5_IRQHandler /* 37 GPIO pin interrupt 5 */ + .long PIN_INT6_IRQHandler /* 38 GPIO pin interrupt 6 */ + .long PIN_INT7_IRQHandler /* 39 GPIO pin interrupt 7 */ + .long GINT0_IRQHandler /* 40 GPIO global interrupt 0 */ + .long GINT1_IRQHandler /* 41 GPIO global interrupt 1 */ + .long EVENTROUTER_IRQHandler /* 42 Event router interrupt */ + .long C_CAN1_IRQHandler /* 43 C_CAN1 interrupt */ + .long 0 /* 44 Reserved */ + .long ADCHS_IRQHandler /* 45 ADCHS combined interrupt */ + .long ATIMER_IRQHandler /* 46 Alarm timer interrupt */ + .long RTC_IRQHandler /* 47 RTC interrupt */ + .long 0 /* 48 Reserved */ + .long WWDT_IRQHandler /* 49 WWDT interrupt */ + .long M0SUB_IRQHandler /* 50 TXEV instruction from the M0 subsystem core interrupt */ + .long C_CAN0_IRQHandler /* 51 C_CAN0 interrupt */ + .long QEI_IRQHandler /* 52 QEI interrupt */ #if defined(MBED_BOOTLOADER) @@ -308,56 +308,55 @@ SysTick_Handler: .endm /* Exception Handlers */ - def_irq_handler DAC_IRQHandler /* 16 D/A Converter */ - def_irq_handler M0CORE_IRQHandler /* 17 M0 Core */ - def_irq_handler DMA_IRQHandler /* 18 General Purpose DMA */ - def_irq_handler EZH_IRQHandler /* 19 EZH/EDM */ - def_irq_handler FLASH_EEPROM_IRQHandler /* 20 Reserved for Typhoon */ - def_irq_handler ETH_IRQHandler /* 21 Ethernet */ - def_irq_handler SDIO_IRQHandler /* 22 SD/MMC */ - def_irq_handler LCD_IRQHandler /* 23 LCD */ - def_irq_handler USB0_IRQHandler /* 24 USB0 */ - def_irq_handler USB1_IRQHandler /* 25 USB1 */ - def_irq_handler SCT_IRQHandler /* 26 State Configurable Timer */ - def_irq_handler RIT_IRQHandler /* 27 Repetitive Interrupt Timer */ - def_irq_handler TIMER0_IRQHandler /* 28 Timer0 */ - def_irq_handler TIMER1_IRQHandler /* 29 Timer1 */ - def_irq_handler TIMER2_IRQHandler /* 30 Timer2 */ - def_irq_handler TIMER3_IRQHandler /* 31 Timer3 */ - def_irq_handler MCPWM_IRQHandler /* 32 Motor Control PWM */ - def_irq_handler ADC0_IRQHandler /* 33 A/D Converter 0 */ - def_irq_handler I2C0_IRQHandler /* 34 I2C0 */ - def_irq_handler I2C1_IRQHandler /* 35 I2C1 */ - def_irq_handler SPI_IRQHandler /* 36 SPI */ - def_irq_handler ADC1_IRQHandler /* 37 A/D Converter 1 */ - def_irq_handler SSP0_IRQHandler /* 38 SSP0 */ - def_irq_handler SSP1_IRQHandler /* 39 SSP1 */ - def_irq_handler UART0_IRQHandler /* 40 UART0 */ - def_irq_handler UART1_IRQHandler /* 41 UART1 */ - def_irq_handler UART2_IRQHandler /* 42 UART2 */ - def_irq_handler UART3_IRQHandler /* 43 UART3 */ - def_irq_handler I2S0_IRQHandler /* 44 I2S0 */ - def_irq_handler I2S1_IRQHandler /* 45 I2S1 */ - def_irq_handler SPIFI_IRQHandler /* 46 SPI Flash Interface */ - def_irq_handler SGPIO_IRQHandler /* 47 SGPIO */ - def_irq_handler GPIO0_IRQHandler /* 48 GPIO0 */ - def_irq_handler GPIO1_IRQHandler /* 49 GPIO1 */ - def_irq_handler GPIO2_IRQHandler /* 50 GPIO2 */ - def_irq_handler GPIO3_IRQHandler /* 51 GPIO3 */ - def_irq_handler GPIO4_IRQHandler /* 52 GPIO4 */ - def_irq_handler GPIO5_IRQHandler /* 53 GPIO5 */ - def_irq_handler GPIO6_IRQHandler /* 54 GPIO6 */ - def_irq_handler GPIO7_IRQHandler /* 55 GPIO7 */ - def_irq_handler GINT0_IRQHandler /* 56 GINT0 */ - def_irq_handler GINT1_IRQHandler /* 57 GINT1 */ - def_irq_handler EVRT_IRQHandler /* 58 Event Router */ - def_irq_handler CAN1_IRQHandler /* 59 C_CAN1 */ - def_irq_handler VADC_IRQHandler /* 61 VADC */ - def_irq_handler ATIMER_IRQHandler /* 62 ATIMER */ - def_irq_handler RTC_IRQHandler /* 63 RTC */ - def_irq_handler WDT_IRQHandler /* 65 WDT */ - def_irq_handler M0s_IRQHandler /* 66 M0s */ - def_irq_handler CAN0_IRQHandler /* 67 C_CAN0 */ - def_irq_handler QEI_IRQHandler /* 68 QEI */ + def_irq_handler DAC_IRQHandler /* D/A Converter */ + def_irq_handler M0APP_IRQHandler /* M0 Core */ + def_irq_handler DMA_IRQHandler /* General Purpose DMA */ + def_irq_handler FLASHEEPROM_IRQHandler /* EZH/EDM */ + def_irq_handler ETHERNET_IRQHandler /* Ethernet */ + def_irq_handler SDIO_IRQHandler /* SD/MMC */ + def_irq_handler LCD_IRQHandler /* LCD */ + def_irq_handler USB0_IRQHandler /* USB0 */ + def_irq_handler USB1_IRQHandler /* USB1 */ + def_irq_handler SCT_IRQHandler /* State Configurable Timer */ + def_irq_handler RITIMER_IRQHandler /* Repetitive Interrupt Timer */ + def_irq_handler TIMER0_IRQHandler /* Timer0 */ + def_irq_handler TIMER1_IRQHandler /* Timer1 */ + def_irq_handler TIMER2_IRQHandler /* Timer2 */ + def_irq_handler TIMER3_IRQHandler /* Timer3 */ + def_irq_handler MCPWM_IRQHandler /* Motor Control PWM */ + def_irq_handler ADC0_IRQHandler /* A/D Converter 0 */ + def_irq_handler I2C0_IRQHandler /* I2C0 */ + def_irq_handler I2C1_IRQHandler /* I2C1 */ + def_irq_handler SPI_IRQHandler /* SPI */ + def_irq_handler ADC1_IRQHandler /* A/D Converter 1 */ + def_irq_handler SSP0_IRQHandler /* SSP0 */ + def_irq_handler SSP1_IRQHandler /* SSP1 */ + def_irq_handler USART0_IRQHandler /* UART0 */ + def_irq_handler UART1_IRQHandler /* UART1 */ + def_irq_handler USART2_IRQHandler /* UART2 */ + def_irq_handler USART3_IRQHandler /* UART3 */ + def_irq_handler I2S0_IRQHandler /* I2S0 */ + def_irq_handler I2S1_IRQHandler /* I2S1 */ + def_irq_handler SPIFI_IRQHandler /* SPI Flash Interface */ + def_irq_handler SGPIO_IRQHandler /* SGPIO */ + def_irq_handler PIN_INT0_IRQHandler /* GPIO0 */ + def_irq_handler PIN_INT1_IRQHandler /* GPIO1 */ + def_irq_handler PIN_INT2_IRQHandler /* GPIO2 */ + def_irq_handler PIN_INT3_IRQHandler /* GPIO3 */ + def_irq_handler PIN_INT4_IRQHandler /* GPIO4 */ + def_irq_handler PIN_INT5_IRQHandler /* GPIO5 */ + def_irq_handler PIN_INT6_IRQHandler /* GPIO6 */ + def_irq_handler PIN_INT7_IRQHandler /* GPIO7 */ + def_irq_handler GINT0_IRQHandler /* GINT0 */ + def_irq_handler GINT1_IRQHandler /* GINT1 */ + def_irq_handler EVENTROUTER_IRQHandler /* Event Router */ + def_irq_handler C_CAN1_IRQHandler /* C_CAN1 */ + def_irq_handler ADCHS_IRQHandler /* VADC */ + def_irq_handler ATIMER_IRQHandler /* ATIMER */ + def_irq_handler RTC_IRQHandler /* RTC */ + def_irq_handler WWDT_IRQHandler /* WDT */ + def_irq_handler M0SUB_IRQHandler /* M0s */ + def_irq_handler C_CAN0_IRQHandler /* C_CAN0 */ + def_irq_handler QEI_IRQHandler /* QEI */ .end diff --git a/source/hic_hal/nxp/lpc4322/uart.c b/source/hic_hal/nxp/lpc4322/uart.c index f4600c6a9..5bf10a9e9 100644 --- a/source/hic_hal/nxp/lpc4322/uart.c +++ b/source/hic_hal/nxp/lpc4322/uart.c @@ -46,7 +46,7 @@ static int32_t reset(void); #define UART_IRQn USART0_IRQn #define LPC_USART LPC_USART0 -#define UART_IRQHandler UART0_IRQHandler +#define UART_IRQHandler USART0_IRQHandler // UART Control Pin P2_2: GPIO5[2] #define PORT_UARTCTRL 5 From 37bc06c69cace1d1bc01baad9d73c19a764050d2 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 8 Dec 2021 10:22:56 -0600 Subject: [PATCH 541/617] nrf52820_hic: add support in tests --- test/info.py | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/test/info.py b/test/info.py index 683b35fe4..ab3bf5d54 100644 --- a/test/info.py +++ b/test/info.py @@ -32,6 +32,7 @@ ("kl26z_artemis_dk_if", False, 0x8000, "hex" ), ("kl26z_microbit_if", False, 0x8000, "hex" ), ("kl27z_microbit_if", False, 0x8000, "hex" ), + ("nrf52820_microbit_if", False, 0x8000, "hex" ), ("lpc11u35_lpc812xpresso_if", False, 0x0000, "bin" ), ("lpc11u35_lpc824xpresso_if", False, 0x0000, "bin" ), ("lpc4322_lpc54114xpresso_if", False, 0x10000, "bin" ), @@ -216,6 +217,8 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x9901, VENDOR_TO_FAMILY('Nordic', 1), 'kl26z_microbit_if', 'kl26z_bl', 'Microbit' ), ( 0x9903, VENDOR_TO_FAMILY('Nordic', 2), 'kl27z_microbit_if', 'kl27z_bl', 'Microbitv2' ), ( 0x9904, VENDOR_TO_FAMILY('Nordic', 2), 'kl27z_microbit_if', 'kl27z_bl', 'Microbitv2' ), + ( 0x9905, VENDOR_TO_FAMILY('Nordic', 2), 'nrf52820_microbit_if', 'nrf52820_bl', 'Microbitv2' ), + ( 0x9906, VENDOR_TO_FAMILY('Nordic', 2), 'nrf52820_microbit_if', 'nrf52820_bl', 'Microbitv2' ), ( 0xA127, VENDOR_TO_FAMILY('Ambiq', 1), 'kl26z_artemis_dk_if', 'kl26z_bl', 'ARTMBED' ), ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'kl26z_if', None, None ), ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'k20dx_if', None, None ), @@ -233,17 +236,18 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y # Add new HICs here HIC_STRING_TO_ID = { 'k20dx': 0x97969900, + 'k26f': 0x97969909, 'kl26z': 0x97969901, + 'kl27z': 0x9796990B, 'lpc11u35': 0x97969902, - 'sam3u2c': 0x97969903, - 'max32620': 0x97969904, 'lpc4322': 0x97969905, + 'lpc55s69': 0x4C504355, + 'm48ssidae': 0x97969921, + 'max32620': 0x97969904, 'max32625': 0x97969906, + 'nrf52820': 0x6E052820, + 'sam3u2c': 0x97969903, 'stm32f103xb': 0x97969908, - 'k26f': 0x97969909, - 'kl27z': 0x9796990B, - 'm48ssidae': 0x97969921, - 'lpc55s69': 0x4C504355, } BOARD_ID_LOCKED_WHEN_ERASED = set([ From 422ded70413e8c6be03f8959e5a4055f291f0c1c Mon Sep 17 00:00:00 2001 From: Carlos Pereira Atencio Date: Wed, 8 Dec 2021 22:56:37 +0000 Subject: [PATCH 542/617] tools: add exit error codes when a project name is invalid or git throws errors (#910) * tools: Add error exit code when project name provided is invalid. Not a simple way to check if a generator is empty without consuming it, so just use a flag. * tools: Check error code from generate_version_file(). --- tools/mbedcli_compile.py | 4 +++- tools/progen_compile.py | 8 +++++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/tools/mbedcli_compile.py b/tools/mbedcli_compile.py index 2291d6cd3..170df51f7 100755 --- a/tools/mbedcli_compile.py +++ b/tools/mbedcli_compile.py @@ -77,7 +77,9 @@ def main(): print("Error - this script must be run from the tools directory") exit(-1) version_git_dir = os.path.join(daplink_dir, "source", "daplink") - generate_version_file(version_git_dir) + error = generate_version_file(version_git_dir) + if error: + exit(-1) if not args.projects == []: for project in args.projects: print("Compiling %s" % project) diff --git a/tools/progen_compile.py b/tools/progen_compile.py index 58299082f..44ad7005e 100755 --- a/tools/progen_compile.py +++ b/tools/progen_compile.py @@ -100,14 +100,18 @@ def get_core_count(): if len(args.projects) > 0: logger.warning("A release can should only be done on all packages") version_git_dir = os.path.join(daplink_dir, "source", "daplink") - generate_version_file(version_git_dir) + error = generate_version_file(version_git_dir) + if error: + exit(-1) # Build the project(s) cores = get_core_count() if args.parallel else 1 projects = args.projects if len(args.projects) > 0 else project_list generator = generate.Generator(PROJECTS_YAML) for p_name in projects: + p_valid = False for project in generator.generate(p_name): + p_valid = True failed = False if hasattr(project, 'workspace_name') and (project.workspace_name is not None): logger.info("Generating %s for %s in workspace %s", toolchain, project.name, project.workspace_name) @@ -126,6 +130,8 @@ def get_core_count(): failed = True if failed and not args.ignore_failures: exit(-1) + if not p_valid: + exit(-1) # Generate images with boardid / familyid for supported configurations if args.release or args.supported: From d4e6ad2131431861ebb5ec8ce95226ffc28e1177 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 9 Dec 2021 15:54:57 -0600 Subject: [PATCH 543/617] python: update pyOCD (and other python dependencies) (#909) Update pyOCD, mbed-cli, mbed-ls and pyyaml modules --- requirements.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/requirements.txt b/requirements.txt index 11f348055..b4c970881 100644 --- a/requirements.txt +++ b/requirements.txt @@ -1,14 +1,15 @@ project_generator==0.11.* -mbed-ls==1.6.2 +mbed-ls==1.8.* pyserial -pyOCD==0.28.* +pyOCD==0.32.* requests intelhex enum34 pyusb -mbed-cli==1.8.2 +mbed-cli==1.10.* bs4 numpy pyelftools fuzzywuzzy jsonschema +pyyaml>=6.0,<7.0 From 9ba34e24163f4ddded0b7406f8f49774d210524e Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Thu, 16 Dec 2021 11:42:27 -0600 Subject: [PATCH 544/617] Microbit v2: Add HW timer for delays instead of busy "for" loops --- source/board/microbitv2/kl27z/pwr_mon.c | 14 ++++++- source/board/microbitv2/microbitv2.c | 50 +++++++++++++++++++++++-- 2 files changed, 58 insertions(+), 6 deletions(-) diff --git a/source/board/microbitv2/kl27z/pwr_mon.c b/source/board/microbitv2/kl27z/pwr_mon.c index 0fe9ca83d..f433293a4 100644 --- a/source/board/microbitv2/kl27z/pwr_mon.c +++ b/source/board/microbitv2/kl27z/pwr_mon.c @@ -25,6 +25,7 @@ #include "fsl_pmc.h" #include "fsl_port.h" #include "fsl_gpio.h" +#include "fsl_tpm.h" #define ADC_VBG_CHANNEL 27U #define ADC_VBG_MUX (kADC16_ChannelMuxA) @@ -38,6 +39,11 @@ static void pwr_mon_bandgap_init(void); static uint32_t pwr_mon_read_vbg(uint32_t channelGroup); static uint32_t pwr_mon_adc_to_mv(uint32_t raw_adc); +void TPM0_IRQHandler(void); + +extern volatile bool tpmIsrFlag; +extern uint32_t tpm_source_clock; + void pwr_mon_init(void) { gpio_pin_config_t pin_config = { @@ -85,11 +91,15 @@ power_source_t pwr_mon_get_power_source(void) { } uint32_t pwr_mon_get_vbat_mv(void) { + /* Set timer period 3ms*/ + TPM_SetTimerPeriod(TPM0, USEC_TO_COUNT(3000U, tpm_source_clock)); // Enable voltage divider to take measurement GPIO_PinWrite(PIN_RUN_VBAT_SENSE_GPIO, PIN_RUN_VBAT_SENSE_BIT, 1); // Add a ~3ms delay to allow the 100nF capacitors to charge to about 3*RC. - // 3 clock cycles per loop at -O2 ARMCC optimization - for (uint32_t count = 48000; count > 0UL; count--); + TPM_StartTimer(TPM0, kTPM_SystemClock); + while (false == tpmIsrFlag); + tpmIsrFlag = false; + uint32_t bat_adc = adc_read_channel(0, PIN_VMON_BAT_ADC_CH, PIN_VMON_BAT_ADC_MUX); // Disable voltage divider GPIO_PinWrite(PIN_RUN_VBAT_SENSE_GPIO, PIN_RUN_VBAT_SENSE_BIT, 0); diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index fb53ac1d8..65dec1adc 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -47,7 +47,19 @@ #include "adc.h" #include "fsl_port.h" #include "fsl_gpio.h" +#include "fsl_tpm.h" +volatile bool tpmIsrFlag = false; +uint32_t tpm_source_clock; + +void TPM0_IRQHandler(void) +{ + /* Clear interrupt flag.*/ + TPM_ClearStatusFlags(TPM0, kTPM_TimeOverflowFlag); + tpmIsrFlag = true; + TPM_StopTimer(TPM0); + __DSB(); +} #endif #ifdef DRAG_N_DROP_SUPPORT @@ -109,6 +121,25 @@ static mb_version_t read_brd_rev_id(void) { mb_version_t board_version = BOARD_VERSION_2_DEF; uint32_t board_rev_id_adc = 0; uint32_t board_rev_id_mv = 0; + + tpm_config_t tpmInfo; + + /* Select the clock source for the TPM counter as kCLOCK_McgIrc48MClk */ + CLOCK_SetTpmClock(1U); + + TPM_GetDefaultConfig(&tpmInfo); + + /* TPM clock divide by TPM_PRESCALER */ + tpmInfo.prescale = kTPM_Prescale_Divide_4; + + /* Initialize TPM module */ + TPM_Init(TPM0, &tpmInfo); + + TPM_EnableInterrupts(TPM0, kTPM_TimeOverflowInterruptEnable); + + EnableIRQ(TPM0_IRQn); + + tpm_source_clock = (CLOCK_GetFreq(kCLOCK_McgIrc48MClk) / 4); // Set Board Rev ID pin as output but pin disabled PORT_SetPinMux(PIN_BOARD_REV_ID_PORT , PIN_BOARD_REV_ID_BIT, kPORT_PinDisabledOrAnalog); @@ -118,19 +149,26 @@ static mb_version_t read_brd_rev_id(void) { adc_init(); // 1. Discharge capacitor + /* Set timer period 3ms*/ + TPM_SetTimerPeriod(TPM0, USEC_TO_COUNT(3000U, tpm_source_clock)); // Drive BRD_REV_ID pin to low GPIO_PortClear(PIN_BOARD_REV_ID_GPIO, PIN_BOARD_REV_ID); PORT_SetPinMux(PIN_BOARD_REV_ID_PORT , PIN_BOARD_REV_ID_BIT, kPORT_MuxAsGpio); // Add a 3ms delay to allow the 100nF Cap to discharge // at least 5*RC with 4700R. - for (uint32_t count = 16 * 3000; count > 0UL; count--); + TPM_StartTimer(TPM0, kTPM_SystemClock); + while (false == tpmIsrFlag); + tpmIsrFlag = false; // 2. Charge capacitor for 100us + /* Set timer period 100us*/ + TPM_SetTimerPeriod(TPM0, USEC_TO_COUNT(100U, tpm_source_clock)); // Drive BRD_REV_ID pin to high GPIO_PortSet(PIN_BOARD_REV_ID_GPIO, PIN_BOARD_REV_ID); // Add a ~100us delay - // 3 clock cycles per loop at -O2 ARMCC optimization - for (uint32_t count = 1600; count > 0UL; count--); + TPM_StartTimer(TPM0, kTPM_SystemClock); + while (false == tpmIsrFlag); + tpmIsrFlag = false; // Change pin to ADC (High-Z). Capacitor will stop charging PORT_SetPinMux(PIN_BOARD_REV_ID_PORT , PIN_BOARD_REV_ID_BIT, kPORT_PinDisabledOrAnalog); @@ -139,12 +177,16 @@ static mb_version_t read_brd_rev_id(void) { board_rev_id_mv = board_rev_id_adc * 3300 / 0xFFF; // Convert ADC 12-bit value to mV with 3.3V reference // 4. Discharge capacitor + /* Set timer period 3ms*/ + TPM_SetTimerPeriod(TPM0, USEC_TO_COUNT(3000U, tpm_source_clock)); // Drive BRD_REV_ID pin to low GPIO_PortClear(PIN_BOARD_REV_ID_GPIO, PIN_BOARD_REV_ID); PORT_SetPinMux(PIN_BOARD_REV_ID_PORT , PIN_BOARD_REV_ID_BIT, kPORT_MuxAsGpio); // Add a 3ms delay to allow the 100nF Cap to discharge // at least 5*RC with 4700R. - for (uint32_t count = 16 * 3000; count > 0UL; count--); + TPM_StartTimer(TPM0, kTPM_SystemClock); + while (false == tpmIsrFlag); + tpmIsrFlag = false; // 5. Identify board ID depending on voltage if ( board_rev_id_mv > BRD_ID_1_LOWER_THR_V && board_rev_id_mv < BRD_ID_1_UPPER_THR_V) { From 695158707f3c9e9b910c7ea4f21ed40a83e21251 Mon Sep 17 00:00:00 2001 From: Ciro Cattuto Date: Sat, 18 Dec 2021 21:52:51 +0100 Subject: [PATCH 545/617] implements external target support and selection for nRF5x-DK GPIO ports/pins for SWD communication can now be modified at runtime. During pre-boot of nrf5X-DK boards, an external target is detected (via EXT_VTG and EXT_GND_DETECT signals) and selected over the OB target by enabling the external SWD lines. Support for detecting/selecting shield-mounted targets is not implemented yet, but it is a minor step. This has been tested on an nRF52-DK board. --- projects.yaml | 4 + records/board/mkit_dk_dongle_nrf5x_ext.yaml | 13 ++ source/board/mkit_dk_dongle_nrf5x_ext.c | 195 ++++++++++++++++++ .../IO_Config_Override.h | 85 ++++++++ source/hic_hal/atmel/sam3u2c/DAP_config.h | 110 +++++----- source/hic_hal/atmel/sam3u2c/gpio.c | 12 ++ 6 files changed, 371 insertions(+), 48 deletions(-) create mode 100644 records/board/mkit_dk_dongle_nrf5x_ext.yaml create mode 100644 source/board/mkit_dk_dongle_nrf5x_ext.c create mode 100644 source/board/override_mkit_dk_dongle_nrf5x_ext/IO_Config_Override.h diff --git a/projects.yaml b/projects.yaml index a43151106..c55b02abe 100644 --- a/projects.yaml +++ b/projects.yaml @@ -523,6 +523,10 @@ projects: - *module_if - *module_hic_sam3u2c - records/board/mkit_dk_dongle_nrf5x.yaml + sam3u2c_mkit_dk_dongle_nrf5x_ext_if: + - *module_if + - *module_hic_sam3u2c + - records/board/mkit_dk_dongle_nrf5x_ext.yaml sam3u2c_ublox_evk_nina_b1_if: - *module_if - *module_hic_sam3u2c diff --git a/records/board/mkit_dk_dongle_nrf5x_ext.yaml b/records/board/mkit_dk_dongle_nrf5x_ext.yaml new file mode 100644 index 000000000..46c1cfdb6 --- /dev/null +++ b/records/board/mkit_dk_dongle_nrf5x_ext.yaml @@ -0,0 +1,13 @@ +common: + macros: + - IO_CONFIG_OVERRIDE + includes: + - source/board/override_mkit_dk_dongle_nrf5x_ext + sources: + board: + - source/board/mkit_dk_dongle_nrf5x_ext.c + family: + - source/family/nordic/nrf51822/target_nrf51.c + - source/family/nordic/nrf52/target.c + - source/family/nordic/target_reset_nrf51.c + - source/family/nordic/target_reset_nrf52.c diff --git a/source/board/mkit_dk_dongle_nrf5x_ext.c b/source/board/mkit_dk_dongle_nrf5x_ext.c new file mode 100644 index 000000000..da46e53b0 --- /dev/null +++ b/source/board/mkit_dk_dongle_nrf5x_ext.c @@ -0,0 +1,195 @@ +/** + * @file mkit_dk_dongle_nrf5x_ext.c + * @brief board ID for the Nordic nRF5x developments boards + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2021, Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "sam3u2c.h" +#include "DAP_config.h" +#include "target_config.h" +#include "util.h" +#include "flash_manager.h" +#include "target_family.h" +#include "target_board.h" + +// BOARD_ID pointer will be set during run time to point to one of these +const char *board_id_nrf51_mkit = "1070"; +const char *board_id_nrf51_dk = "1100"; +const char *board_id_nrf51_dongle = "1120"; +const char *board_id_nrf52_dk = "1101"; +const char *board_id_nrf52840_dk = "1102"; + +const char *board_name_nrf51_mkit = "nRF51822-mKIT"; +const char *board_name_nrf51_dk = "nRF51-DK"; +const char *board_name_nrf51_dongle = "nRF51-Dongle"; +const char *board_name_nrf52_dk = "nRF52-DK"; +const char *board_name_nrf52840_dk = "nRF52840-DK"; +static char board_name[14]; + +extern target_cfg_t target_device_nrf51822_16; +extern target_cfg_t target_device_nrf51822_32; +extern target_cfg_t target_device_nrf52_64; +extern target_cfg_t target_device_nrf52840; +target_cfg_t target_device; +static uint8_t device_type; + +static void set_target_device(uint32_t device) +{ + device_type = device; + if (device == 0) { + target_device = target_device_nrf51822_16; + } else if (device == 1) { + target_device = target_device_nrf51822_32; + } else if (device == 2) { + target_device = target_device_nrf52_64; + } else if (device == 3) { + target_device = target_device_nrf52840; + } +} + +static void nrf_prerun_board_config(void) +{ + // Work around for setting the correct board id based on GPIOs + uint8_t bit1; + uint8_t bit2; + uint8_t bit3; + + PIOB->PIO_PER = (1 << 1); // Enable PIO pin PB1 + PIOB->PIO_PER = (1 << 2); // Enable PIO pin PB2 + PIOB->PIO_PER = (1 << 3); // Enable PIO pin PB3 + PIOB->PIO_ODR = (1 << 1); // Disabe output + PIOB->PIO_ODR = (1 << 2); // Disabe output + PIOB->PIO_ODR = (1 << 3); // Disabe output + PIOB->PIO_PUER = (1 << 1); // Enable pull-up + PIOB->PIO_PUER = (1 << 2); // Enable pull-up + PIOB->PIO_PUER = (1 << 3); // Enable pull-up + + bit1 = (PIOB->PIO_PDSR >> 1) & 1; // Read PB1 + bit2 = (PIOB->PIO_PDSR >> 2) & 1; // Read PB2 + bit3 = (PIOB->PIO_PDSR >> 3) & 1; // Read PB3 + + /* pins translate to board-ids as follow + * + * PB3|PB2|PB1|BOARD ID| BOARD + * ---------------------------------- + * 0 | 0 | 0 | 1120 | nRF51-Dongle + * 0 | 0 | 1 | 1100 | nRF51-DK + * 0 | 1 | 0 | 1101 | nRF52-DK + * 0 | 1 | 1 | 1102 | nRF52840-DK + * 1 | 1 | 1 | 1070 | nRF51822-mKIT + * 1 | 0 | 0 | undefined + * 1 | 0 | 1 | undefined + * 1 | 1 | 0 | undefined + */ + + if (bit3) { + set_target_device(0); + target_device.rt_family_id = kNordic_Nrf51_FamilyID; + target_device.rt_board_id = board_id_nrf51_mkit; // 1070 + memcpy(board_name, board_name_nrf51_mkit, sizeof(board_name_nrf51_mkit)); + // Note only a setting of 111 is defined + util_assert(bit2 && bit1); + } else { + if (!bit2 && bit1) { + set_target_device(1); + target_device.rt_family_id = kNordic_Nrf51_FamilyID; + target_device.rt_board_id = board_id_nrf51_dk; // 1100 + memcpy(board_name, board_name_nrf51_dk, sizeof(board_name_nrf51_dk)); + } else if (!bit2 && !bit1) { + set_target_device(1); + target_device.rt_family_id = kNordic_Nrf51_FamilyID; + target_device.rt_board_id = board_id_nrf51_dongle; // 1120 + memcpy(board_name, board_name_nrf51_dongle, sizeof(board_name_nrf51_dongle)); + } else if (bit2 && !bit1) { + set_target_device(2); + target_device.rt_family_id = kNordic_Nrf52_FamilyID; + target_device.rt_board_id = board_id_nrf52_dk; // 1101 + memcpy(board_name, board_name_nrf52_dk, sizeof(board_name_nrf52_dk)); + } else { //(bit2 && bit1) + set_target_device(3); + target_device.rt_family_id = kNordic_Nrf52_FamilyID; + target_device.rt_board_id = board_id_nrf52840_dk; // 1102 + memcpy(board_name, board_name_nrf52840_dk, sizeof(board_name_nrf52840_dk)); + } + } + + PIOB->PIO_PUDR = (1 << 1); // Disable pull-up + PIOB->PIO_PUDR = (1 << 2); // Disable pull-up + PIOB->PIO_PUDR = (1 << 3); // Disable pull-up + + // EXTERNAL TARGET DETECTION + // - only for nRF51-DK and nRF52-DK, so far + // - need to code shield detection and priority between external and shield-mounted targets + if ( (!bit2 && bit1) || (bit2 && !bit1) ) { + // EXT_VTG (high if external target is powered) + PIOB->PIO_PUDR = (1 << 6); // pull-up disable + PIOB->PIO_ODR = (1 << 6); // input + PIOB->PIO_PER = (1 << 6); // GPIO control + bit1 = (PIOB->PIO_PDSR >> 6) & 1; // Read PB6 + + // EXT_GND_DETECT (high if no external target is connected) + PIOB->PIO_PUER = (1 << 18); // pull-up enable + PIOB->PIO_ODR = (1 << 18); // input + PIOB->PIO_PER = (1 << 18); // GPIO control + bit2 = (PIOB->PIO_PDSR >> 18) & 1; // Read PB18 + PIOB->PIO_PUDR = (1 << 18); // pull-up disable + + // if external target is detected, re-route SWD signals + if (bit1 && !bit2) { + pin_nRESET_port = PIN_EXT_nRESET_PORT; + pin_nRESET_bit = PIN_EXT_nRESET_BIT; + pin_nRESET = PIN_EXT_nRESET; + + pin_SWCLK_port = PIN_EXT_SWCLK_PORT; + pin_SWCLK_bit = PIN_EXT_SWCLK_BIT; + pin_SWCLK = PIN_EXT_SWCLK; + + pin_SWDIO_port = PIN_EXT_SWDIO_PORT; + pin_SWDIO_bit = PIN_EXT_SWDIO_BIT; + pin_SWDIO = PIN_EXT_SWDIO; + } + + // switch on red LED if external target is in use + PIOA->PIO_PUDR = (1 << 28); // pull-up disable + PIOA->PIO_OER = (1 << 28); // output + PIOA->PIO_PER = (1 << 28); // GPIO control + if (bit1 && !bit2) + PIOA->PIO_CODR = (1 << 28); // set low + else + PIOA->PIO_SODR = (1 << 28); // set high + } +} + +static void nrf_swd_set_target_reset(uint8_t asserted){ + if (asserted && device_type == 0) { + PIOA->PIO_OER = PIN_SWDIO; + PIOA->PIO_OER = PIN_SWCLK; + } else if(!asserted) { + PIOA->PIO_MDER = PIN_SWDIO | PIN_SWCLK | PIN_nRESET; + } +} + +const board_info_t g_board_info = { + .info_version = kBoardInfoVersion, + .flags = kEnablePageErase, + .prerun_board_config = nrf_prerun_board_config, + .swd_set_target_reset = nrf_swd_set_target_reset, + .target_cfg = &target_device, + .board_vendor = "Nordic Semiconductor", + .board_name = board_name, +}; diff --git a/source/board/override_mkit_dk_dongle_nrf5x_ext/IO_Config_Override.h b/source/board/override_mkit_dk_dongle_nrf5x_ext/IO_Config_Override.h new file mode 100644 index 000000000..0e88bff1d --- /dev/null +++ b/source/board/override_mkit_dk_dongle_nrf5x_ext/IO_Config_Override.h @@ -0,0 +1,85 @@ +/** + * @file IO_Config_Override.c + * @brief Alternative IO for LPC11U35 based Hardware Interface Circuit + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __IO_CONFIG_OVERRIDE_H__ +#define __IO_CONFIG_OVERRIDE_H__ + +// This GPIO configuration is only valid for the SAM3U2C HIC +COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_SAM3U2C); + +// DAP LED +#define PIN_DAP_LED_PORT PIOA +#define PIN_DAP_LED_BIT 29 +#define PIN_DAP_LED (1UL << PIN_DAP_LED_BIT) + +// MSD LED +#define PIN_MSD_LED_PORT PIOA +#define PIN_MSD_LED_BIT 29 +#define PIN_MSD_LED (1UL << PIN_MSD_LED_BIT) + +// CDC LED +#define PIN_CDC_LED_PORT PIOA +#define PIN_CDC_LED_BIT 29 +#define PIN_CDC_LED (1UL << PIN_CDC_LED_BIT) + +// external nRESET OUT Pin +#ifndef PIN_EXT_nRESET +#define PIN_EXT_nRESET_PORT PIOB +#define PIN_EXT_nRESET_BIT 17 +#define PIN_EXT_nRESET (1UL << PIN_EXT_nRESET_BIT) +#endif + +// external SWCLK/TCK Pin +#ifndef PIN_EXT_SWCLK +#define PIN_EXT_SWCLK_PORT PIOB +#define PIN_EXT_SWCLK_BIT 10 +#define PIN_EXT_SWCLK (1UL << PIN_EXT_SWCLK_BIT) +#endif + +// external SWDIO/TMS In/Out Pin +#ifndef PIN_EXT_SWDIO +#define PIN_EXT_SWDIO_PORT PIOB +#define PIN_EXT_SWDIO_BIT 9 +#define PIN_EXT_SWDIO (1UL << PIN_EXT_SWDIO_BIT) +#endif + +// shield nRESET OUT Pin +#ifndef PIN_SH_nRESET +#define PIN_SH_nRESET_PORT PIOB +#define PIN_SH_nRESET_BIT 22 +#define PIN_SH_nRESET (1UL << PIN_SH_nRESET_BIT) +#endif + +// shield SWCLK/TCK Pin +#ifndef PIN_SH_SWCLK +#define PIN_SH_SWCLK_PORT PIOB +#define PIN_SH_SWCLK_BIT 20 +#define PIN_SH_SWCLK (1UL << PIN_SH_SWCLK_BIT) +#endif + +// shield SWDIO/TMS In/Out Pin +#ifndef PIN_SH_SWDIO +#define PIN_SH_SWDIO_PORT PIOB +#define PIN_SH_SWDIO_BIT 19 +#define PIN_SH_SWDIO (1UL << PIN_SH_SWDIO_BIT) +#endif + +#endif diff --git a/source/hic_hal/atmel/sam3u2c/DAP_config.h b/source/hic_hal/atmel/sam3u2c/DAP_config.h index 22b5c0478..a0ac96b17 100644 --- a/source/hic_hal/atmel/sam3u2c/DAP_config.h +++ b/source/hic_hal/atmel/sam3u2c/DAP_config.h @@ -182,6 +182,17 @@ of the same I/O port. The following SWDIO I/O Pin functions are provided: // Configure DAP I/O pins ------------------------------ +// support for dynamic assignment of SWD signals +extern Pio *pin_nRESET_port; // GPIO port for nRESET signal +extern Pio *pin_SWCLK_port; // GPIO port for SWCLK signal +extern Pio *pin_SWDIO_port; // GPIO port for SWDIO signal +extern unsigned long pin_nRESET_bit; // GPIO pin for nRESET signal +extern unsigned long pin_SWCLK_bit; // GPIO pin for SWCLK signal +extern unsigned long pin_SWDIO_bit; // GPIO pin for SWDIO signal +extern unsigned long pin_nRESET; // GPIO mask for nRESET signal +extern unsigned long pin_SWCLK; // GPIO mask for SWCLK signal +extern unsigned long pin_SWDIO; // GPIO msak for SWDIO signal + /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET. Configures the DAP Hardware I/O pins for JTAG mode: - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level. @@ -198,23 +209,26 @@ __STATIC_INLINE void PORT_SWD_SETUP(void) { PMC->PMC_PCER0 = (1 << 10) | (1 << 11) | (1 << 12); // Enable clock for all PIOs - PIN_nRESET_PORT->PIO_MDDR = PIN_nRESET; // Disable multi drive - PIN_nRESET_PORT->PIO_PUER = PIN_nRESET; // pull-up enable - PIN_nRESET_PORT->PIO_SODR = PIN_nRESET; // HIGH - PIN_nRESET_PORT->PIO_OER = PIN_nRESET; // output - PIN_nRESET_PORT->PIO_PER = PIN_nRESET; // GPIO control - - PIN_SWCLK_PORT->PIO_MDDR = PIN_SWCLK; // Disable multi drive - PIN_SWCLK_PORT->PIO_PUER = PIN_SWCLK; // pull-up enable - PIN_SWCLK_PORT->PIO_SODR = PIN_SWCLK; // HIGH - PIN_SWCLK_PORT->PIO_OER = PIN_SWCLK; // output - PIN_SWCLK_PORT->PIO_PER = PIN_SWCLK; // GPIO control - - PIN_SWDIO_PORT->PIO_MDDR = PIN_SWDIO; // Disable multi drive - PIN_SWDIO_PORT->PIO_PUER = PIN_SWDIO; // pull-up enable - PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO; // HIGH - PIN_SWDIO_PORT->PIO_OER = PIN_SWDIO; // output - PIN_SWDIO_PORT->PIO_PER = PIN_SWDIO; // GPIO control + pin_nRESET_port->PIO_MDDR = pin_nRESET; // Disable multi drive + pin_nRESET_port->PIO_PUER = pin_nRESET; // pull-up enable + pin_nRESET_port->PIO_SODR = pin_nRESET; // HIGH + pin_nRESET_port->PIO_OER = pin_nRESET; // output + pin_nRESET_port->PIO_PER = pin_nRESET; // GPIO control + + pin_SWCLK_port->PIO_MDDR = pin_SWCLK; // Disable multi drive + pin_SWCLK_port->PIO_PUER = pin_SWCLK; // pull-up enable + pin_SWCLK_port->PIO_SODR = pin_SWCLK; // HIGH + pin_SWCLK_port->PIO_OER = pin_SWCLK; // output + pin_SWCLK_port->PIO_PER = pin_SWCLK; // GPIO control + + pin_SWDIO_port->PIO_MDDR = pin_SWDIO; // Disable multi drive + pin_SWDIO_port->PIO_PUER = pin_SWDIO; // pull-up enable + pin_SWDIO_port->PIO_SODR = pin_SWDIO; // HIGH + pin_SWDIO_port->PIO_OER = pin_SWDIO; // output + pin_SWDIO_port->PIO_PER = pin_SWDIO; // GPIO control + + volatile int Cnt = 1000000; + do {} while (--Cnt); // Give pull-up some time to become active } /** Disable JTAG/SWD I/O Pins. @@ -223,17 +237,17 @@ Disables the DAP Hardware I/O pins which configures: */ __STATIC_INLINE void PORT_OFF(void) { - PIN_nRESET_PORT->PIO_PUER = PIN_nRESET; // pull-up enable - PIN_nRESET_PORT->PIO_ODR = PIN_nRESET; // input - PIN_nRESET_PORT->PIO_PER = PIN_nRESET; // GPIO control + pin_nRESET_port->PIO_PUER = pin_nRESET; // pull-up enable + pin_nRESET_port->PIO_ODR = pin_nRESET; // input + pin_nRESET_port->PIO_PER = pin_nRESET; // GPIO control - PIN_SWCLK_PORT->PIO_PUER = PIN_SWCLK; // pull-up enable - PIN_SWCLK_PORT->PIO_ODR = PIN_SWCLK; // input - PIN_SWCLK_PORT->PIO_PER = PIN_SWCLK; // GPIO control + pin_SWCLK_port->PIO_PUER = pin_SWCLK; // pull-up enable + pin_SWCLK_port->PIO_ODR = pin_SWCLK; // input + pin_SWCLK_port->PIO_PER = pin_SWCLK; // GPIO control - PIN_SWDIO_PORT->PIO_PUER = PIN_SWDIO; // pull-up enable - PIN_SWDIO_PORT->PIO_ODR = PIN_SWDIO; // input - PIN_SWDIO_PORT->PIO_PER = PIN_SWDIO; // GPIO control + pin_SWDIO_port->PIO_PUER = pin_SWDIO; // pull-up enable + pin_SWDIO_port->PIO_ODR = pin_SWDIO; // input + pin_SWDIO_port->PIO_PER = pin_SWDIO; // GPIO control } @@ -244,7 +258,7 @@ __STATIC_INLINE void PORT_OFF(void) */ __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void) { - return ((PIN_SWCLK_PORT->PIO_PDSR >> PIN_SWCLK_BIT) & 1); + return ((pin_SWCLK_port->PIO_PDSR >> pin_SWCLK_bit) & 1); } /** SWCLK/TCK I/O pin: Set Output to High. @@ -252,7 +266,7 @@ Set the SWCLK/TCK DAP hardware I/O pin to high level. */ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void) { - PIN_SWCLK_PORT->PIO_SODR = PIN_SWCLK; + pin_SWCLK_port->PIO_SODR = pin_SWCLK; } /** SWCLK/TCK I/O pin: Set Output to Low. @@ -260,7 +274,7 @@ Set the SWCLK/TCK DAP hardware I/O pin to low level. */ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void) { - PIN_SWCLK_PORT->PIO_CODR = PIN_SWCLK; + pin_SWCLK_port->PIO_CODR = pin_SWCLK; } // SWDIO/TMS Pin I/O -------------------------------------- @@ -270,7 +284,7 @@ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void) */ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void) { - return ((PIN_SWDIO_PORT->PIO_PDSR >> PIN_SWDIO_BIT) & 1); + return ((pin_SWDIO_port->PIO_PDSR >> pin_SWDIO_bit) & 1); } /** SWDIO/TMS I/O pin: Set Output to High. @@ -278,7 +292,7 @@ Set the SWDIO/TMS DAP hardware I/O pin to high level. */ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void) { - PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO; + pin_SWDIO_port->PIO_SODR = pin_SWDIO; } /** SWDIO/TMS I/O pin: Set Output to Low. @@ -286,7 +300,7 @@ Set the SWDIO/TMS DAP hardware I/O pin to low level. */ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void) { - PIN_SWDIO_PORT->PIO_CODR = PIN_SWDIO; + pin_SWDIO_port->PIO_CODR = pin_SWDIO; } /** SWDIO I/O pin: Get Input (used in SWD mode only). @@ -294,7 +308,7 @@ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void) */ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void) { - return ((PIN_SWDIO_PORT->PIO_PDSR >> PIN_SWDIO_BIT) & 1); + return ((pin_SWDIO_port->PIO_PDSR >> pin_SWDIO_bit) & 1); } /** SWDIO I/O pin: Set Output (used in SWD mode only). @@ -303,10 +317,10 @@ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void) __STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit) { if (bit & 1) { - PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO; + pin_SWDIO_port->PIO_SODR = pin_SWDIO; } else { - PIN_SWDIO_PORT->PIO_CODR = PIN_SWDIO; + pin_SWDIO_port->PIO_CODR = pin_SWDIO; } } @@ -316,7 +330,7 @@ called prior \ref PIN_SWDIO_OUT function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void) { - PIN_SWDIO_PORT->PIO_OER = PIN_SWDIO; + pin_SWDIO_port->PIO_OER = pin_SWDIO; } /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). @@ -325,7 +339,7 @@ called prior \ref PIN_SWDIO_IN function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void) { - PIN_SWDIO_PORT->PIO_ODR = PIN_SWDIO; + pin_SWDIO_port->PIO_ODR = pin_SWDIO; } @@ -386,7 +400,7 @@ __STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit) */ __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void) { - return ((PIN_nRESET_PORT->PIO_PDSR >> PIN_nRESET_BIT) & 1); + return ((pin_nRESET_port->PIO_PDSR >> pin_nRESET_bit) & 1); } /** nRESET I/O pin: Set Output. @@ -403,11 +417,11 @@ __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit) Hold the SWDCLK and SWDIO/nRESET line low for a minimum of 100 us. */ if (bit & 1) { - PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO; + pin_SWDIO_port->PIO_SODR = pin_SWDIO; - PIN_SWDIO_PORT->PIO_MDER = PIN_SWDIO; - PIN_SWCLK_PORT->PIO_MDER = PIN_SWCLK; - PIN_nRESET_PORT->PIO_MDER = PIN_nRESET; + pin_SWDIO_port->PIO_MDER = pin_SWDIO; + pin_SWCLK_port->PIO_MDER = pin_SWCLK; + pin_nRESET_port->PIO_MDER = pin_nRESET; } else { swd_init_debug(); @@ -422,10 +436,10 @@ __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit) } //Hold RESET and SWCLK low for a minimum of 100us - PIN_SWDIO_PORT->PIO_OER = PIN_SWDIO; - PIN_SWCLK_PORT->PIO_OER = PIN_SWCLK; - PIN_SWDIO_PORT->PIO_CODR = PIN_SWDIO; - PIN_SWCLK_PORT->PIO_CODR = PIN_SWCLK; + pin_SWDIO_port->PIO_OER = pin_SWDIO; + pin_SWCLK_port->PIO_OER = pin_SWCLK; + pin_SWDIO_port->PIO_CODR = pin_SWDIO; + pin_SWCLK_port->PIO_CODR = pin_SWCLK; osDelay(1); } } @@ -433,10 +447,10 @@ __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit) __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit) { if (bit & 1) { - PIN_nRESET_PORT->PIO_SODR = PIN_nRESET; + pin_nRESET_port->PIO_SODR = pin_nRESET; } else { - PIN_nRESET_PORT->PIO_CODR = PIN_nRESET; + pin_nRESET_port->PIO_CODR = pin_nRESET; } } #endif diff --git a/source/hic_hal/atmel/sam3u2c/gpio.c b/source/hic_hal/atmel/sam3u2c/gpio.c index 9479c7416..f9eaba086 100644 --- a/source/hic_hal/atmel/sam3u2c/gpio.c +++ b/source/hic_hal/atmel/sam3u2c/gpio.c @@ -24,10 +24,22 @@ #include "uart.h" #include "compiler.h" #include "daplink.h" +#include "IO_Config.h" // This GPIO configuration is only valid for the SAM3U2C COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_SAM3U2C); +// support for dynamic assignment of SWD signals +Pio *pin_nRESET_port = PIN_nRESET_PORT; // GPIO port for nRESET signal +Pio *pin_SWCLK_port = PIN_SWCLK_PORT; // GPIO port for SWCLK signal +Pio *pin_SWDIO_port = PIN_SWDIO_PORT; // GPIO port for SWDIO signal +unsigned long pin_nRESET_bit = PIN_nRESET_BIT; // GPIO bit for nRESET signal +unsigned long pin_SWCLK_bit = PIN_SWCLK_BIT; // GPIO bit for SWCLK signal +unsigned long pin_SWDIO_bit = PIN_SWDIO_BIT; // GPIO bit for SWDIO signal +unsigned long pin_nRESET = PIN_nRESET; // GPIO mask for nRESET signal +unsigned long pin_SWCLK = PIN_SWCLK; // GPIO mask for SWCLK signal +unsigned long pin_SWDIO = PIN_SWDIO; // GPIO mask for SWDIO signal + void gpio_init(void) { volatile int Cnt; From 07a43d05aa609166456c2611a12b85e9c71f1914 Mon Sep 17 00:00:00 2001 From: Ciro Cattuto Date: Sun, 19 Dec 2021 11:17:00 +0100 Subject: [PATCH 546/617] Added comments on other nRF boards --- source/board/mkit_dk_dongle_nrf5x_ext.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/source/board/mkit_dk_dongle_nrf5x_ext.c b/source/board/mkit_dk_dongle_nrf5x_ext.c index da46e53b0..b9a458c39 100644 --- a/source/board/mkit_dk_dongle_nrf5x_ext.c +++ b/source/board/mkit_dk_dongle_nrf5x_ext.c @@ -134,6 +134,10 @@ static void nrf_prerun_board_config(void) // EXTERNAL TARGET DETECTION // - only for nRF51-DK and nRF52-DK, so far + // - nRF51-Dongle (discontinued) has no external target lines + // - nRF51822-mKIT (discontinued), no external target lines + // - nRF52840-DK has external/shielf SWD lines and is consistent with nRF51-DK / nRF52-DK + // - (nRF52840-Dongle has no interface MCU) // - need to code shield detection and priority between external and shield-mounted targets if ( (!bit2 && bit1) || (bit2 && !bit1) ) { // EXT_VTG (high if external target is powered) From 60488c6f738ffada0d8b068a49dbb64f5a33dc37 Mon Sep 17 00:00:00 2001 From: Ciro Cattuto Date: Sun, 19 Dec 2021 16:21:03 +0100 Subject: [PATCH 547/617] Support for nRF52840 --- source/board/mkit_dk_dongle_nrf5x_ext.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/source/board/mkit_dk_dongle_nrf5x_ext.c b/source/board/mkit_dk_dongle_nrf5x_ext.c index b9a458c39..e8c5d6467 100644 --- a/source/board/mkit_dk_dongle_nrf5x_ext.c +++ b/source/board/mkit_dk_dongle_nrf5x_ext.c @@ -133,13 +133,14 @@ static void nrf_prerun_board_config(void) PIOB->PIO_PUDR = (1 << 3); // Disable pull-up // EXTERNAL TARGET DETECTION - // - only for nRF51-DK and nRF52-DK, so far + // - supports nRF51-DK, nRF52-DK, nRF52840-DK // - nRF51-Dongle (discontinued) has no external target lines // - nRF51822-mKIT (discontinued), no external target lines - // - nRF52840-DK has external/shielf SWD lines and is consistent with nRF51-DK / nRF52-DK - // - (nRF52840-Dongle has no interface MCU) // - need to code shield detection and priority between external and shield-mounted targets - if ( (!bit2 && bit1) || (bit2 && !bit1) ) { + + if ( !bit3 && (bit2 || bit1) ) { + // 001 / 010 / 011 above + // EXT_VTG (high if external target is powered) PIOB->PIO_PUDR = (1 << 6); // pull-up disable PIOB->PIO_ODR = (1 << 6); // input From a4dd72d7290733f159b316ebc78a830d0570b48f Mon Sep 17 00:00:00 2001 From: Ciro Cattuto Date: Sun, 19 Dec 2021 22:36:22 +0100 Subject: [PATCH 548/617] Added support for shield debug port --- source/board/mkit_dk_dongle_nrf5x_ext.c | 43 +++++++++++++++++-- .../IO_Config_Override.h | 6 +-- 2 files changed, 42 insertions(+), 7 deletions(-) diff --git a/source/board/mkit_dk_dongle_nrf5x_ext.c b/source/board/mkit_dk_dongle_nrf5x_ext.c index e8c5d6467..53f4b5873 100644 --- a/source/board/mkit_dk_dongle_nrf5x_ext.c +++ b/source/board/mkit_dk_dongle_nrf5x_ext.c @@ -68,6 +68,8 @@ static void nrf_prerun_board_config(void) uint8_t bit1; uint8_t bit2; uint8_t bit3; + uint8_t target_ext; + uint8_t target_shield; PIOB->PIO_PER = (1 << 1); // Enable PIO pin PB1 PIOB->PIO_PER = (1 << 2); // Enable PIO pin PB2 @@ -147,15 +149,36 @@ static void nrf_prerun_board_config(void) PIOB->PIO_PER = (1 << 6); // GPIO control bit1 = (PIOB->PIO_PDSR >> 6) & 1; // Read PB6 - // EXT_GND_DETECT (high if no external target is connected) + // EXT_GND_DETECT (low if external target is connected) PIOB->PIO_PUER = (1 << 18); // pull-up enable PIOB->PIO_ODR = (1 << 18); // input PIOB->PIO_PER = (1 << 18); // GPIO control + // insert delay? bit2 = (PIOB->PIO_PDSR >> 18) & 1; // Read PB18 PIOB->PIO_PUDR = (1 << 18); // pull-up disable + // nonzero if external target detected + target_ext = bit1 & !bit2; + + // SH_VTG (high if external target is powered) + PIOB->PIO_PUDR = (1 << 5); // pull-up disable + PIOB->PIO_ODR = (1 << 5); // input + PIOB->PIO_PER = (1 << 5); // GPIO control + bit1 = (PIOB->PIO_PDSR >> 5) & 1; // Read PB5 + + // SH_GND_DETECT (low if external target is connected) + PIOB->PIO_PUER = (1 << 23); // pull-up enable + PIOB->PIO_ODR = (1 << 23); // input + PIOB->PIO_PER = (1 << 23); // GPIO control + // insert delay? + bit2 = (PIOB->PIO_PDSR >> 23) & 1; // Read PB23 + PIOB->PIO_PUDR = (1 << 23); // pull-up disable + + // nonzero if external target detected + target_shield = bit1 & !bit2; + // if external target is detected, re-route SWD signals - if (bit1 && !bit2) { + if (target_ext) { pin_nRESET_port = PIN_EXT_nRESET_PORT; pin_nRESET_bit = PIN_EXT_nRESET_BIT; pin_nRESET = PIN_EXT_nRESET; @@ -167,13 +190,25 @@ static void nrf_prerun_board_config(void) pin_SWDIO_port = PIN_EXT_SWDIO_PORT; pin_SWDIO_bit = PIN_EXT_SWDIO_BIT; pin_SWDIO = PIN_EXT_SWDIO; + } else if (target_shield) { + pin_nRESET_port = PIN_SH_nRESET_PORT; + pin_nRESET_bit = PIN_SH_nRESET_BIT; + pin_nRESET = PIN_SH_nRESET; + + pin_SWCLK_port = PIN_SH_SWCLK_PORT; + pin_SWCLK_bit = PIN_SH_SWCLK_BIT; + pin_SWCLK = PIN_SH_SWCLK; + + pin_SWDIO_port = PIN_SH_SWDIO_PORT; + pin_SWDIO_bit = PIN_SH_SWDIO_BIT; + pin_SWDIO = PIN_SH_SWDIO; } - // switch on red LED if external target is in use + // switch on red LED if external or shield target is in use PIOA->PIO_PUDR = (1 << 28); // pull-up disable PIOA->PIO_OER = (1 << 28); // output PIOA->PIO_PER = (1 << 28); // GPIO control - if (bit1 && !bit2) + if (target_ext || target_shield) PIOA->PIO_CODR = (1 << 28); // set low else PIOA->PIO_SODR = (1 << 28); // set high diff --git a/source/board/override_mkit_dk_dongle_nrf5x_ext/IO_Config_Override.h b/source/board/override_mkit_dk_dongle_nrf5x_ext/IO_Config_Override.h index 0e88bff1d..5e25e91e6 100644 --- a/source/board/override_mkit_dk_dongle_nrf5x_ext/IO_Config_Override.h +++ b/source/board/override_mkit_dk_dongle_nrf5x_ext/IO_Config_Override.h @@ -77,9 +77,9 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_SAM3U2C); // shield SWDIO/TMS In/Out Pin #ifndef PIN_SH_SWDIO -#define PIN_SH_SWDIO_PORT PIOB -#define PIN_SH_SWDIO_BIT 19 -#define PIN_SH_SWDIO (1UL << PIN_SH_SWDIO_BIT) +#define PIN_SH_SWDIO_PORT PIOB +#define PIN_SH_SWDIO_BIT 19 +#define PIN_SH_SWDIO (1UL << PIN_SH_SWDIO_BIT) #endif #endif From 2dd6d1bf480c89487a675ee112026124d08ffd4b Mon Sep 17 00:00:00 2001 From: Adrian Negreanu Date: Wed, 8 Dec 2021 11:02:29 +0200 Subject: [PATCH 549/617] DAP: fill the UART capability info only when DAP_UART=1 OpenOCD ends up considering info[1] as capabilities, which in this case is equal zero. Signed-off-by: Adrian Negreanu --- source/daplink/cmsis-dap/DAP.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/source/daplink/cmsis-dap/DAP.c b/source/daplink/cmsis-dap/DAP.c index 0710f5478..317d5330d 100644 --- a/source/daplink/cmsis-dap/DAP.c +++ b/source/daplink/cmsis-dap/DAP.c @@ -110,9 +110,11 @@ static uint8_t DAP_Info(uint8_t id, uint8_t *info) { ((TIMESTAMP_CLOCK != 0U) ? (1U << 5) : 0U) | ((SWO_STREAM != 0U) ? (1U << 6) : 0U) | ((DAP_UART != 0U) ? (1U << 7) : 0U); - + length = 1U; +#if (DAP_UART != 0) info[1] = ((DAP_UART_USB_COM_PORT != 0) ? (1U << 0) : 0U); length = 2U; +#endif break; case DAP_ID_TIMESTAMP_CLOCK: #if (TIMESTAMP_CLOCK != 0U) From 280a20deb84b6c3019485229460735701aca191b Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 20 Dec 2021 20:17:33 -0600 Subject: [PATCH 550/617] DAP: also check DAP_UART_USB_COM_PORT=1 before addomg UART capability info --- source/daplink/cmsis-dap/DAP.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/source/daplink/cmsis-dap/DAP.c b/source/daplink/cmsis-dap/DAP.c index 317d5330d..64451f615 100644 --- a/source/daplink/cmsis-dap/DAP.c +++ b/source/daplink/cmsis-dap/DAP.c @@ -110,10 +110,11 @@ static uint8_t DAP_Info(uint8_t id, uint8_t *info) { ((TIMESTAMP_CLOCK != 0U) ? (1U << 5) : 0U) | ((SWO_STREAM != 0U) ? (1U << 6) : 0U) | ((DAP_UART != 0U) ? (1U << 7) : 0U); - length = 1U; -#if (DAP_UART != 0) +#if ((DAP_UART != 0) && (DAP_UART_USB_COM_PORT != 0)) info[1] = ((DAP_UART_USB_COM_PORT != 0) ? (1U << 0) : 0U); length = 2U; +#else + length = 1U; #endif break; case DAP_ID_TIMESTAMP_CLOCK: From 37ed27bc9806a899d15caf8841635aab50f1dac3 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 20 Dec 2021 23:23:48 -0600 Subject: [PATCH 551/617] sam3u2c_hic: dynamic pin assignment only in override --- source/board/mkit_dk_dongle_nrf5x_ext.c | 51 ++++---- .../IO_Config_Override.h | 31 ++++- .../IO_Config_Override.h | 87 ++++++++++---- source/hic_hal/atmel/sam3u2c/DAP_config.h | 110 ++++++++---------- source/hic_hal/atmel/sam3u2c/IO_Config.h | 30 ++--- source/hic_hal/atmel/sam3u2c/gpio.c | 12 -- 6 files changed, 184 insertions(+), 137 deletions(-) diff --git a/source/board/mkit_dk_dongle_nrf5x_ext.c b/source/board/mkit_dk_dongle_nrf5x_ext.c index 53f4b5873..246fc80af 100644 --- a/source/board/mkit_dk_dongle_nrf5x_ext.c +++ b/source/board/mkit_dk_dongle_nrf5x_ext.c @@ -48,6 +48,17 @@ extern target_cfg_t target_device_nrf52840; target_cfg_t target_device; static uint8_t device_type; +// support for dynamic assignment of SWD signals +Pio *pin_nreset_port = PIN_OB_nRESET_PORT; // GPIO port for nRESET signal +Pio *pin_swclk_port = PIN_OB_SWCLK_PORT; // GPIO port for SWCLK signal +Pio *pin_swdio_port = PIN_OB_SWDIO_PORT; // GPIO port for SWDIO signal +unsigned long pin_nreset_bit = PIN_OB_nRESET_BIT; // GPIO pin for nRESET signal +unsigned long pin_swclk_bit = PIN_OB_SWCLK_BIT; // GPIO pin for SWCLK signal +unsigned long pin_swdio_bit = PIN_OB_SWDIO_BIT; // GPIO pin for SWDIO signal +unsigned long pin_nreset = PIN_OB_nRESET; // GPIO mask for nRESET signal +unsigned long pin_swclk = PIN_OB_SWCLK; // GPIO mask for SWCLK signal +unsigned long pin_swdio = PIN_OB_SWDIO; // GPIO msak for SWDIO signal + static void set_target_device(uint32_t device) { device_type = device; @@ -142,7 +153,7 @@ static void nrf_prerun_board_config(void) if ( !bit3 && (bit2 || bit1) ) { // 001 / 010 / 011 above - + // EXT_VTG (high if external target is powered) PIOB->PIO_PUDR = (1 << 6); // pull-up disable PIOB->PIO_ODR = (1 << 6); // input @@ -179,29 +190,29 @@ static void nrf_prerun_board_config(void) // if external target is detected, re-route SWD signals if (target_ext) { - pin_nRESET_port = PIN_EXT_nRESET_PORT; - pin_nRESET_bit = PIN_EXT_nRESET_BIT; - pin_nRESET = PIN_EXT_nRESET; + pin_nreset_port = PIN_EXT_nRESET_PORT; + pin_nreset_bit = PIN_EXT_nRESET_BIT; + pin_nreset = PIN_EXT_nRESET; - pin_SWCLK_port = PIN_EXT_SWCLK_PORT; - pin_SWCLK_bit = PIN_EXT_SWCLK_BIT; - pin_SWCLK = PIN_EXT_SWCLK; + pin_swclk_port = PIN_EXT_SWCLK_PORT; + pin_swclk_bit = PIN_EXT_SWCLK_BIT; + pin_swclk = PIN_EXT_SWCLK; - pin_SWDIO_port = PIN_EXT_SWDIO_PORT; - pin_SWDIO_bit = PIN_EXT_SWDIO_BIT; - pin_SWDIO = PIN_EXT_SWDIO; + pin_swdio_port = PIN_EXT_SWDIO_PORT; + pin_swdio_bit = PIN_EXT_SWDIO_BIT; + pin_swdio = PIN_EXT_SWDIO; } else if (target_shield) { - pin_nRESET_port = PIN_SH_nRESET_PORT; - pin_nRESET_bit = PIN_SH_nRESET_BIT; - pin_nRESET = PIN_SH_nRESET; + pin_nreset_port = PIN_SH_nRESET_PORT; + pin_nreset_bit = PIN_SH_nRESET_BIT; + pin_nreset = PIN_SH_nRESET; - pin_SWCLK_port = PIN_SH_SWCLK_PORT; - pin_SWCLK_bit = PIN_SH_SWCLK_BIT; - pin_SWCLK = PIN_SH_SWCLK; + pin_swclk_port = PIN_SH_SWCLK_PORT; + pin_swclk_bit = PIN_SH_SWCLK_BIT; + pin_swclk = PIN_SH_SWCLK; - pin_SWDIO_port = PIN_SH_SWDIO_PORT; - pin_SWDIO_bit = PIN_SH_SWDIO_BIT; - pin_SWDIO = PIN_SH_SWDIO; + pin_swdio_port = PIN_SH_SWDIO_PORT; + pin_swdio_bit = PIN_SH_SWDIO_BIT; + pin_swdio = PIN_SH_SWDIO; } // switch on red LED if external or shield target is in use @@ -211,7 +222,7 @@ static void nrf_prerun_board_config(void) if (target_ext || target_shield) PIOA->PIO_CODR = (1 << 28); // set low else - PIOA->PIO_SODR = (1 << 28); // set high + PIOA->PIO_SODR = (1 << 28); // set high } } diff --git a/source/board/override_mkit_dk_dongle_nrf5x/IO_Config_Override.h b/source/board/override_mkit_dk_dongle_nrf5x/IO_Config_Override.h index 314d4da4a..73955deb4 100644 --- a/source/board/override_mkit_dk_dongle_nrf5x/IO_Config_Override.h +++ b/source/board/override_mkit_dk_dongle_nrf5x/IO_Config_Override.h @@ -1,6 +1,6 @@ /** * @file IO_Config_Override.c - * @brief Alternative IO for LPC11U35 based Hardware Interface Circuit + * @brief Alternative IO for Nordic Semiconductor mKit/Dongle/DK * * DAPLink Interface Firmware * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved @@ -22,6 +22,9 @@ #ifndef __IO_CONFIG_OVERRIDE_H__ #define __IO_CONFIG_OVERRIDE_H__ +#include "sam3u2c.h" +#include "daplink.h" + // This GPIO configuration is only valid for the SAM3U2C HIC COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_SAM3U2C); @@ -40,4 +43,30 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_SAM3U2C); #define PIN_CDC_LED_BIT 29 #define PIN_CDC_LED (1UL << PIN_CDC_LED_BIT) +// Non-Forwarded Reset in PIN - Not used + +// Forwarded Reset in PIN +#define PIN_RESET_IN_FWRD_PORT PIOA +#define PIN_RESET_IN_FWRD_BIT 25 +#define PIN_RESET_IN_FWRD (1UL << PIN_RESET_IN_FWRD_BIT) + +// nRESET OUT Pin +#define PIN_nRESET_PORT PIOA +#define PIN_nRESET_BIT 4 +#define PIN_nRESET (1UL << PIN_nRESET_BIT) + +// SWCLK/TCK Pin +#define PIN_SWCLK_PORT PIOA +#define PIN_SWCLK_BIT 17 +#define PIN_SWCLK (1UL << PIN_SWCLK_BIT) + +// SWDIO/TMS In/Out Pin +#define PIN_SWDIO_PORT PIOA +#define PIN_SWDIO_BIT 18 +#define PIN_SWDIO (1UL << PIN_SWDIO_BIT) + +// TDI Pin - Not used + +// SWO/TDO Pin - Not used + #endif diff --git a/source/board/override_mkit_dk_dongle_nrf5x_ext/IO_Config_Override.h b/source/board/override_mkit_dk_dongle_nrf5x_ext/IO_Config_Override.h index 5e25e91e6..59f6e2317 100644 --- a/source/board/override_mkit_dk_dongle_nrf5x_ext/IO_Config_Override.h +++ b/source/board/override_mkit_dk_dongle_nrf5x_ext/IO_Config_Override.h @@ -1,6 +1,6 @@ /** * @file IO_Config_Override.c - * @brief Alternative IO for LPC11U35 based Hardware Interface Circuit + * @brief Alternative IO for nRF5x-DK boards * * DAPLink Interface Firmware * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved @@ -22,64 +22,107 @@ #ifndef __IO_CONFIG_OVERRIDE_H__ #define __IO_CONFIG_OVERRIDE_H__ +#include "sam3u2c.h" +#include "daplink.h" + // This GPIO configuration is only valid for the SAM3U2C HIC COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_SAM3U2C); // DAP LED -#define PIN_DAP_LED_PORT PIOA -#define PIN_DAP_LED_BIT 29 -#define PIN_DAP_LED (1UL << PIN_DAP_LED_BIT) +#define PIN_DAP_LED_PORT PIOA +#define PIN_DAP_LED_BIT 29 +#define PIN_DAP_LED (1UL << PIN_DAP_LED_BIT) // MSD LED -#define PIN_MSD_LED_PORT PIOA -#define PIN_MSD_LED_BIT 29 -#define PIN_MSD_LED (1UL << PIN_MSD_LED_BIT) +#define PIN_MSD_LED_PORT PIOA +#define PIN_MSD_LED_BIT 29 +#define PIN_MSD_LED (1UL << PIN_MSD_LED_BIT) // CDC LED -#define PIN_CDC_LED_PORT PIOA -#define PIN_CDC_LED_BIT 29 -#define PIN_CDC_LED (1UL << PIN_CDC_LED_BIT) +#define PIN_CDC_LED_PORT PIOA +#define PIN_CDC_LED_BIT 29 +#define PIN_CDC_LED (1UL << PIN_CDC_LED_BIT) + +// Non-Forwarded Reset in PIN - Not used + +// Forwarded Reset in PIN +#define PIN_RESET_IN_FWRD_PORT PIOA +#define PIN_RESET_IN_FWRD_BIT 25 +#define PIN_RESET_IN_FWRD (1UL << PIN_RESET_IN_FWRD_BIT) + +// support for dynamic assignment of SWD signals +extern Pio *pin_nreset_port; // GPIO port for nRESET signal +extern Pio *pin_swclk_port; // GPIO port for SWCLK signal +extern Pio *pin_swdio_port; // GPIO port for SWDIO signal +extern unsigned long pin_nreset_bit; // GPIO pin for nRESET signal +extern unsigned long pin_swclk_bit; // GPIO pin for SWCLK signal +extern unsigned long pin_swdio_bit; // GPIO pin for SWDIO signal +extern unsigned long pin_nreset; // GPIO mask for nRESET signal +extern unsigned long pin_swclk; // GPIO mask for SWCLK signal +extern unsigned long pin_swdio; // GPIO msak for SWDIO signal + +// dynamic nRESET OUT Pin +#define PIN_nRESET_PORT pin_nreset_port +#define PIN_nRESET_BIT pin_nreset_bit +#define PIN_nRESET pin_nreset + +// dynamic SWCLK/TCK Pin +#define PIN_SWCLK_PORT pin_swclk_port +#define PIN_SWCLK_BIT pin_swclk_bit +#define PIN_SWCLK pin_swclk + +// dynamic SWDIO/TMS In/Out Pin +#define PIN_SWDIO_PORT pin_swdio_port +#define PIN_SWDIO_BIT pin_swdio_bit +#define PIN_SWDIO pin_swdio + +// internal nRESET OUT Pin +#define PIN_OB_nRESET_PORT PIOA +#define PIN_OB_nRESET_BIT 4 +#define PIN_OB_nRESET (1UL << PIN_OB_nRESET_BIT) + +// internal SWCLK/TCK Pin +#define PIN_OB_SWCLK_PORT PIOA +#define PIN_OB_SWCLK_BIT 17 +#define PIN_OB_SWCLK (1UL << PIN_OB_SWCLK_BIT) + +// internal SWDIO/TMS In/Out Pin +#define PIN_OB_SWDIO_PORT PIOA +#define PIN_OB_SWDIO_BIT 18 +#define PIN_OB_SWDIO (1UL << PIN_OB_SWDIO_BIT) // external nRESET OUT Pin -#ifndef PIN_EXT_nRESET #define PIN_EXT_nRESET_PORT PIOB #define PIN_EXT_nRESET_BIT 17 #define PIN_EXT_nRESET (1UL << PIN_EXT_nRESET_BIT) -#endif // external SWCLK/TCK Pin -#ifndef PIN_EXT_SWCLK #define PIN_EXT_SWCLK_PORT PIOB #define PIN_EXT_SWCLK_BIT 10 #define PIN_EXT_SWCLK (1UL << PIN_EXT_SWCLK_BIT) -#endif // external SWDIO/TMS In/Out Pin -#ifndef PIN_EXT_SWDIO #define PIN_EXT_SWDIO_PORT PIOB #define PIN_EXT_SWDIO_BIT 9 #define PIN_EXT_SWDIO (1UL << PIN_EXT_SWDIO_BIT) -#endif // shield nRESET OUT Pin -#ifndef PIN_SH_nRESET #define PIN_SH_nRESET_PORT PIOB #define PIN_SH_nRESET_BIT 22 #define PIN_SH_nRESET (1UL << PIN_SH_nRESET_BIT) -#endif // shield SWCLK/TCK Pin -#ifndef PIN_SH_SWCLK #define PIN_SH_SWCLK_PORT PIOB #define PIN_SH_SWCLK_BIT 20 #define PIN_SH_SWCLK (1UL << PIN_SH_SWCLK_BIT) -#endif // shield SWDIO/TMS In/Out Pin -#ifndef PIN_SH_SWDIO #define PIN_SH_SWDIO_PORT PIOB #define PIN_SH_SWDIO_BIT 19 #define PIN_SH_SWDIO (1UL << PIN_SH_SWDIO_BIT) -#endif + +// TDI Pin - Not used + +// SWO/TDO Pin - Not used #endif diff --git a/source/hic_hal/atmel/sam3u2c/DAP_config.h b/source/hic_hal/atmel/sam3u2c/DAP_config.h index a0ac96b17..22b5c0478 100644 --- a/source/hic_hal/atmel/sam3u2c/DAP_config.h +++ b/source/hic_hal/atmel/sam3u2c/DAP_config.h @@ -182,17 +182,6 @@ of the same I/O port. The following SWDIO I/O Pin functions are provided: // Configure DAP I/O pins ------------------------------ -// support for dynamic assignment of SWD signals -extern Pio *pin_nRESET_port; // GPIO port for nRESET signal -extern Pio *pin_SWCLK_port; // GPIO port for SWCLK signal -extern Pio *pin_SWDIO_port; // GPIO port for SWDIO signal -extern unsigned long pin_nRESET_bit; // GPIO pin for nRESET signal -extern unsigned long pin_SWCLK_bit; // GPIO pin for SWCLK signal -extern unsigned long pin_SWDIO_bit; // GPIO pin for SWDIO signal -extern unsigned long pin_nRESET; // GPIO mask for nRESET signal -extern unsigned long pin_SWCLK; // GPIO mask for SWCLK signal -extern unsigned long pin_SWDIO; // GPIO msak for SWDIO signal - /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET. Configures the DAP Hardware I/O pins for JTAG mode: - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level. @@ -209,26 +198,23 @@ __STATIC_INLINE void PORT_SWD_SETUP(void) { PMC->PMC_PCER0 = (1 << 10) | (1 << 11) | (1 << 12); // Enable clock for all PIOs - pin_nRESET_port->PIO_MDDR = pin_nRESET; // Disable multi drive - pin_nRESET_port->PIO_PUER = pin_nRESET; // pull-up enable - pin_nRESET_port->PIO_SODR = pin_nRESET; // HIGH - pin_nRESET_port->PIO_OER = pin_nRESET; // output - pin_nRESET_port->PIO_PER = pin_nRESET; // GPIO control - - pin_SWCLK_port->PIO_MDDR = pin_SWCLK; // Disable multi drive - pin_SWCLK_port->PIO_PUER = pin_SWCLK; // pull-up enable - pin_SWCLK_port->PIO_SODR = pin_SWCLK; // HIGH - pin_SWCLK_port->PIO_OER = pin_SWCLK; // output - pin_SWCLK_port->PIO_PER = pin_SWCLK; // GPIO control - - pin_SWDIO_port->PIO_MDDR = pin_SWDIO; // Disable multi drive - pin_SWDIO_port->PIO_PUER = pin_SWDIO; // pull-up enable - pin_SWDIO_port->PIO_SODR = pin_SWDIO; // HIGH - pin_SWDIO_port->PIO_OER = pin_SWDIO; // output - pin_SWDIO_port->PIO_PER = pin_SWDIO; // GPIO control - - volatile int Cnt = 1000000; - do {} while (--Cnt); // Give pull-up some time to become active + PIN_nRESET_PORT->PIO_MDDR = PIN_nRESET; // Disable multi drive + PIN_nRESET_PORT->PIO_PUER = PIN_nRESET; // pull-up enable + PIN_nRESET_PORT->PIO_SODR = PIN_nRESET; // HIGH + PIN_nRESET_PORT->PIO_OER = PIN_nRESET; // output + PIN_nRESET_PORT->PIO_PER = PIN_nRESET; // GPIO control + + PIN_SWCLK_PORT->PIO_MDDR = PIN_SWCLK; // Disable multi drive + PIN_SWCLK_PORT->PIO_PUER = PIN_SWCLK; // pull-up enable + PIN_SWCLK_PORT->PIO_SODR = PIN_SWCLK; // HIGH + PIN_SWCLK_PORT->PIO_OER = PIN_SWCLK; // output + PIN_SWCLK_PORT->PIO_PER = PIN_SWCLK; // GPIO control + + PIN_SWDIO_PORT->PIO_MDDR = PIN_SWDIO; // Disable multi drive + PIN_SWDIO_PORT->PIO_PUER = PIN_SWDIO; // pull-up enable + PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO; // HIGH + PIN_SWDIO_PORT->PIO_OER = PIN_SWDIO; // output + PIN_SWDIO_PORT->PIO_PER = PIN_SWDIO; // GPIO control } /** Disable JTAG/SWD I/O Pins. @@ -237,17 +223,17 @@ Disables the DAP Hardware I/O pins which configures: */ __STATIC_INLINE void PORT_OFF(void) { - pin_nRESET_port->PIO_PUER = pin_nRESET; // pull-up enable - pin_nRESET_port->PIO_ODR = pin_nRESET; // input - pin_nRESET_port->PIO_PER = pin_nRESET; // GPIO control + PIN_nRESET_PORT->PIO_PUER = PIN_nRESET; // pull-up enable + PIN_nRESET_PORT->PIO_ODR = PIN_nRESET; // input + PIN_nRESET_PORT->PIO_PER = PIN_nRESET; // GPIO control - pin_SWCLK_port->PIO_PUER = pin_SWCLK; // pull-up enable - pin_SWCLK_port->PIO_ODR = pin_SWCLK; // input - pin_SWCLK_port->PIO_PER = pin_SWCLK; // GPIO control + PIN_SWCLK_PORT->PIO_PUER = PIN_SWCLK; // pull-up enable + PIN_SWCLK_PORT->PIO_ODR = PIN_SWCLK; // input + PIN_SWCLK_PORT->PIO_PER = PIN_SWCLK; // GPIO control - pin_SWDIO_port->PIO_PUER = pin_SWDIO; // pull-up enable - pin_SWDIO_port->PIO_ODR = pin_SWDIO; // input - pin_SWDIO_port->PIO_PER = pin_SWDIO; // GPIO control + PIN_SWDIO_PORT->PIO_PUER = PIN_SWDIO; // pull-up enable + PIN_SWDIO_PORT->PIO_ODR = PIN_SWDIO; // input + PIN_SWDIO_PORT->PIO_PER = PIN_SWDIO; // GPIO control } @@ -258,7 +244,7 @@ __STATIC_INLINE void PORT_OFF(void) */ __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void) { - return ((pin_SWCLK_port->PIO_PDSR >> pin_SWCLK_bit) & 1); + return ((PIN_SWCLK_PORT->PIO_PDSR >> PIN_SWCLK_BIT) & 1); } /** SWCLK/TCK I/O pin: Set Output to High. @@ -266,7 +252,7 @@ Set the SWCLK/TCK DAP hardware I/O pin to high level. */ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void) { - pin_SWCLK_port->PIO_SODR = pin_SWCLK; + PIN_SWCLK_PORT->PIO_SODR = PIN_SWCLK; } /** SWCLK/TCK I/O pin: Set Output to Low. @@ -274,7 +260,7 @@ Set the SWCLK/TCK DAP hardware I/O pin to low level. */ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void) { - pin_SWCLK_port->PIO_CODR = pin_SWCLK; + PIN_SWCLK_PORT->PIO_CODR = PIN_SWCLK; } // SWDIO/TMS Pin I/O -------------------------------------- @@ -284,7 +270,7 @@ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void) */ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void) { - return ((pin_SWDIO_port->PIO_PDSR >> pin_SWDIO_bit) & 1); + return ((PIN_SWDIO_PORT->PIO_PDSR >> PIN_SWDIO_BIT) & 1); } /** SWDIO/TMS I/O pin: Set Output to High. @@ -292,7 +278,7 @@ Set the SWDIO/TMS DAP hardware I/O pin to high level. */ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void) { - pin_SWDIO_port->PIO_SODR = pin_SWDIO; + PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO; } /** SWDIO/TMS I/O pin: Set Output to Low. @@ -300,7 +286,7 @@ Set the SWDIO/TMS DAP hardware I/O pin to low level. */ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void) { - pin_SWDIO_port->PIO_CODR = pin_SWDIO; + PIN_SWDIO_PORT->PIO_CODR = PIN_SWDIO; } /** SWDIO I/O pin: Get Input (used in SWD mode only). @@ -308,7 +294,7 @@ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void) */ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void) { - return ((pin_SWDIO_port->PIO_PDSR >> pin_SWDIO_bit) & 1); + return ((PIN_SWDIO_PORT->PIO_PDSR >> PIN_SWDIO_BIT) & 1); } /** SWDIO I/O pin: Set Output (used in SWD mode only). @@ -317,10 +303,10 @@ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void) __STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit) { if (bit & 1) { - pin_SWDIO_port->PIO_SODR = pin_SWDIO; + PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO; } else { - pin_SWDIO_port->PIO_CODR = pin_SWDIO; + PIN_SWDIO_PORT->PIO_CODR = PIN_SWDIO; } } @@ -330,7 +316,7 @@ called prior \ref PIN_SWDIO_OUT function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void) { - pin_SWDIO_port->PIO_OER = pin_SWDIO; + PIN_SWDIO_PORT->PIO_OER = PIN_SWDIO; } /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). @@ -339,7 +325,7 @@ called prior \ref PIN_SWDIO_IN function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void) { - pin_SWDIO_port->PIO_ODR = pin_SWDIO; + PIN_SWDIO_PORT->PIO_ODR = PIN_SWDIO; } @@ -400,7 +386,7 @@ __STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit) */ __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void) { - return ((pin_nRESET_port->PIO_PDSR >> pin_nRESET_bit) & 1); + return ((PIN_nRESET_PORT->PIO_PDSR >> PIN_nRESET_BIT) & 1); } /** nRESET I/O pin: Set Output. @@ -417,11 +403,11 @@ __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit) Hold the SWDCLK and SWDIO/nRESET line low for a minimum of 100 us. */ if (bit & 1) { - pin_SWDIO_port->PIO_SODR = pin_SWDIO; + PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO; - pin_SWDIO_port->PIO_MDER = pin_SWDIO; - pin_SWCLK_port->PIO_MDER = pin_SWCLK; - pin_nRESET_port->PIO_MDER = pin_nRESET; + PIN_SWDIO_PORT->PIO_MDER = PIN_SWDIO; + PIN_SWCLK_PORT->PIO_MDER = PIN_SWCLK; + PIN_nRESET_PORT->PIO_MDER = PIN_nRESET; } else { swd_init_debug(); @@ -436,10 +422,10 @@ __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit) } //Hold RESET and SWCLK low for a minimum of 100us - pin_SWDIO_port->PIO_OER = pin_SWDIO; - pin_SWCLK_port->PIO_OER = pin_SWCLK; - pin_SWDIO_port->PIO_CODR = pin_SWDIO; - pin_SWCLK_port->PIO_CODR = pin_SWCLK; + PIN_SWDIO_PORT->PIO_OER = PIN_SWDIO; + PIN_SWCLK_PORT->PIO_OER = PIN_SWCLK; + PIN_SWDIO_PORT->PIO_CODR = PIN_SWDIO; + PIN_SWCLK_PORT->PIO_CODR = PIN_SWCLK; osDelay(1); } } @@ -447,10 +433,10 @@ __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit) __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit) { if (bit & 1) { - pin_nRESET_port->PIO_SODR = pin_nRESET; + PIN_nRESET_PORT->PIO_SODR = PIN_nRESET; } else { - pin_nRESET_port->PIO_CODR = pin_nRESET; + PIN_nRESET_PORT->PIO_CODR = PIN_nRESET; } } #endif diff --git a/source/hic_hal/atmel/sam3u2c/IO_Config.h b/source/hic_hal/atmel/sam3u2c/IO_Config.h index 2ca0b31d6..fdea409dc 100644 --- a/source/hic_hal/atmel/sam3u2c/IO_Config.h +++ b/source/hic_hal/atmel/sam3u2c/IO_Config.h @@ -1,6 +1,6 @@ /** * @file IO_Config.h - * @brief + * @brief * * DAPLink Interface Firmware * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved @@ -19,69 +19,59 @@ * limitations under the License. */ +// Override all defines if IO_CONFIG_OVERRIDE is defined +#ifdef IO_CONFIG_OVERRIDE +#include "IO_Config_Override.h" +#ifndef __IO_CONFIG_H__ +#define __IO_CONFIG_H__ +#endif +#endif + #ifndef __IO_CONFIG_H__ #define __IO_CONFIG_H__ #include "sam3u2c.h" #include "daplink.h" -#ifdef IO_CONFIG_OVERRIDE -#include "IO_Config_Override.h" -#endif - // This GPIO configuration is only valid for the SAM3U2C HIC COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_SAM3U2C); // DAP LED -#ifndef PIN_DAP_LED #define PIN_DAP_LED_PORT PIOA #define PIN_DAP_LED_BIT 29 #define PIN_DAP_LED (1UL << PIN_DAP_LED_BIT) -#endif // MSD LED -#ifndef PIN_MSD_LED #define PIN_MSD_LED_PORT PIOA #define PIN_MSD_LED_BIT 28 #define PIN_MSD_LED (1UL << PIN_MSD_LED_BIT) -#endif // CDC LED -#ifndef PIN_CDC_LED #define PIN_CDC_LED_PORT PIOA #define PIN_CDC_LED_BIT 31 #define PIN_CDC_LED (1UL << PIN_CDC_LED_BIT) -#endif // Non-Forwarded Reset in PIN - Not used -// Forwarded Reset in PIN -#ifndef PIN_RESET_IN_FWRD +// Forwarded Reset in PIN #define PIN_RESET_IN_FWRD_PORT PIOA #define PIN_RESET_IN_FWRD_BIT 25 #define PIN_RESET_IN_FWRD (1UL << PIN_RESET_IN_FWRD_BIT) -#endif // nRESET OUT Pin -#ifndef PIN_nRESET #define PIN_nRESET_PORT PIOA #define PIN_nRESET_BIT 4 #define PIN_nRESET (1UL << PIN_nRESET_BIT) -#endif // SWCLK/TCK Pin -#ifndef PIN_SWCLK #define PIN_SWCLK_PORT PIOA #define PIN_SWCLK_BIT 17 #define PIN_SWCLK (1UL << PIN_SWCLK_BIT) -#endif // SWDIO/TMS In/Out Pin -#ifndef PIN_SWDIO #define PIN_SWDIO_PORT PIOA #define PIN_SWDIO_BIT 18 #define PIN_SWDIO (1UL << PIN_SWDIO_BIT) -#endif // TDI Pin - Not used diff --git a/source/hic_hal/atmel/sam3u2c/gpio.c b/source/hic_hal/atmel/sam3u2c/gpio.c index f9eaba086..9479c7416 100644 --- a/source/hic_hal/atmel/sam3u2c/gpio.c +++ b/source/hic_hal/atmel/sam3u2c/gpio.c @@ -24,22 +24,10 @@ #include "uart.h" #include "compiler.h" #include "daplink.h" -#include "IO_Config.h" // This GPIO configuration is only valid for the SAM3U2C COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_SAM3U2C); -// support for dynamic assignment of SWD signals -Pio *pin_nRESET_port = PIN_nRESET_PORT; // GPIO port for nRESET signal -Pio *pin_SWCLK_port = PIN_SWCLK_PORT; // GPIO port for SWCLK signal -Pio *pin_SWDIO_port = PIN_SWDIO_PORT; // GPIO port for SWDIO signal -unsigned long pin_nRESET_bit = PIN_nRESET_BIT; // GPIO bit for nRESET signal -unsigned long pin_SWCLK_bit = PIN_SWCLK_BIT; // GPIO bit for SWCLK signal -unsigned long pin_SWDIO_bit = PIN_SWDIO_BIT; // GPIO bit for SWDIO signal -unsigned long pin_nRESET = PIN_nRESET; // GPIO mask for nRESET signal -unsigned long pin_SWCLK = PIN_SWCLK; // GPIO mask for SWCLK signal -unsigned long pin_SWDIO = PIN_SWDIO; // GPIO mask for SWDIO signal - void gpio_init(void) { volatile int Cnt; From 9d696f204ea37f3b273cceac260a39be54f43673 Mon Sep 17 00:00:00 2001 From: Ciro Cattuto Date: Tue, 21 Dec 2021 21:44:19 +0100 Subject: [PATCH 552/617] Renamed project/board files --- projects.yaml | 4 ++-- .../{mkit_dk_dongle_nrf5x_ext.yaml => nrf5x_dk_ext.yaml} | 4 ++-- source/board/{mkit_dk_dongle_nrf5x_ext.c => nrf5x_dk_ext.c} | 0 .../IO_Config_Override.h | 0 4 files changed, 4 insertions(+), 4 deletions(-) rename records/board/{mkit_dk_dongle_nrf5x_ext.yaml => nrf5x_dk_ext.yaml} (74%) rename source/board/{mkit_dk_dongle_nrf5x_ext.c => nrf5x_dk_ext.c} (100%) rename source/board/{override_mkit_dk_dongle_nrf5x_ext => override_sam3u2c_nrf5x_dk_ext}/IO_Config_Override.h (100%) diff --git a/projects.yaml b/projects.yaml index c55b02abe..236a07c77 100644 --- a/projects.yaml +++ b/projects.yaml @@ -523,10 +523,10 @@ projects: - *module_if - *module_hic_sam3u2c - records/board/mkit_dk_dongle_nrf5x.yaml - sam3u2c_mkit_dk_dongle_nrf5x_ext_if: + sam3u2c_nrf5x_dk_ext_if: - *module_if - *module_hic_sam3u2c - - records/board/mkit_dk_dongle_nrf5x_ext.yaml + - records/board/nrf5x_dk_ext.yaml sam3u2c_ublox_evk_nina_b1_if: - *module_if - *module_hic_sam3u2c diff --git a/records/board/mkit_dk_dongle_nrf5x_ext.yaml b/records/board/nrf5x_dk_ext.yaml similarity index 74% rename from records/board/mkit_dk_dongle_nrf5x_ext.yaml rename to records/board/nrf5x_dk_ext.yaml index 46c1cfdb6..ccb5e0fd9 100644 --- a/records/board/mkit_dk_dongle_nrf5x_ext.yaml +++ b/records/board/nrf5x_dk_ext.yaml @@ -2,10 +2,10 @@ common: macros: - IO_CONFIG_OVERRIDE includes: - - source/board/override_mkit_dk_dongle_nrf5x_ext + - source/board/override_sam3u2c_nrf5x_dk_ext sources: board: - - source/board/mkit_dk_dongle_nrf5x_ext.c + - source/board/nrf5x_dk_ext.c family: - source/family/nordic/nrf51822/target_nrf51.c - source/family/nordic/nrf52/target.c diff --git a/source/board/mkit_dk_dongle_nrf5x_ext.c b/source/board/nrf5x_dk_ext.c similarity index 100% rename from source/board/mkit_dk_dongle_nrf5x_ext.c rename to source/board/nrf5x_dk_ext.c diff --git a/source/board/override_mkit_dk_dongle_nrf5x_ext/IO_Config_Override.h b/source/board/override_sam3u2c_nrf5x_dk_ext/IO_Config_Override.h similarity index 100% rename from source/board/override_mkit_dk_dongle_nrf5x_ext/IO_Config_Override.h rename to source/board/override_sam3u2c_nrf5x_dk_ext/IO_Config_Override.h From 629b8bf2d8a46c465258d2c38158e36a16115c88 Mon Sep 17 00:00:00 2001 From: Ciro Cattuto Date: Tue, 21 Dec 2021 21:54:20 +0100 Subject: [PATCH 553/617] Rename project / board files --- records/board/nrf5x_dk_ext.yaml | 2 +- .../IO_Config_Override.h | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename source/board/{override_sam3u2c_nrf5x_dk_ext => override_nrf5x_dk_ext}/IO_Config_Override.h (100%) diff --git a/records/board/nrf5x_dk_ext.yaml b/records/board/nrf5x_dk_ext.yaml index ccb5e0fd9..4fb283d1b 100644 --- a/records/board/nrf5x_dk_ext.yaml +++ b/records/board/nrf5x_dk_ext.yaml @@ -2,7 +2,7 @@ common: macros: - IO_CONFIG_OVERRIDE includes: - - source/board/override_sam3u2c_nrf5x_dk_ext + - source/board/override_nrf5x_dk_ext sources: board: - source/board/nrf5x_dk_ext.c diff --git a/source/board/override_sam3u2c_nrf5x_dk_ext/IO_Config_Override.h b/source/board/override_nrf5x_dk_ext/IO_Config_Override.h similarity index 100% rename from source/board/override_sam3u2c_nrf5x_dk_ext/IO_Config_Override.h rename to source/board/override_nrf5x_dk_ext/IO_Config_Override.h From 4146f90f6d30f3595f9bc24a6084d7399ca5b029 Mon Sep 17 00:00:00 2001 From: Ciro Cattuto Date: Wed, 22 Dec 2021 00:17:59 +0100 Subject: [PATCH 554/617] Fix incomplete override --- .../IO_Config_Override.h | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/source/board/override_ublox_evk_nina_b1/IO_Config_Override.h b/source/board/override_ublox_evk_nina_b1/IO_Config_Override.h index 314d4da4a..ebfe81cf1 100644 --- a/source/board/override_ublox_evk_nina_b1/IO_Config_Override.h +++ b/source/board/override_ublox_evk_nina_b1/IO_Config_Override.h @@ -22,6 +22,9 @@ #ifndef __IO_CONFIG_OVERRIDE_H__ #define __IO_CONFIG_OVERRIDE_H__ +#include "sam3u2c.h" +#include "daplink.h" + // This GPIO configuration is only valid for the SAM3U2C HIC COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_SAM3U2C); @@ -40,4 +43,26 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_SAM3U2C); #define PIN_CDC_LED_BIT 29 #define PIN_CDC_LED (1UL << PIN_CDC_LED_BIT) +// Non-Forwarded Reset in PIN - Not used + +// Forwarded Reset in PIN +#define PIN_RESET_IN_FWRD_PORT PIOA +#define PIN_RESET_IN_FWRD_BIT 25 +#define PIN_RESET_IN_FWRD (1UL << PIN_RESET_IN_FWRD_BIT) + +// nRESET OUT Pin +#define PIN_nRESET_PORT PIOA +#define PIN_nRESET_BIT 4 +#define PIN_nRESET (1UL << PIN_nRESET_BIT) + +// SWCLK/TCK Pin +#define PIN_SWCLK_PORT PIOA +#define PIN_SWCLK_BIT 17 +#define PIN_SWCLK (1UL << PIN_SWCLK_BIT) + +// SWDIO/TMS In/Out Pin +#define PIN_SWDIO_PORT PIOA +#define PIN_SWDIO_BIT 18 +#define PIN_SWDIO (1UL << PIN_SWDIO_BIT) + #endif From 1acecc8e9bcd1d7d9a7c7599f996c5e163c08f89 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Wed, 22 Dec 2021 21:06:30 +0000 Subject: [PATCH 555/617] kl27z_microbit: Reduce board ID 100us timer delay to account for overhead. --- source/board/microbitv2/microbitv2.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 65dec1adc..81f258c49 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -161,8 +161,8 @@ static mb_version_t read_brd_rev_id(void) { tpmIsrFlag = false; // 2. Charge capacitor for 100us - /* Set timer period 100us*/ - TPM_SetTimerPeriod(TPM0, USEC_TO_COUNT(100U, tpm_source_clock)); + /* Set timer period slightly below 100us to account for overheads */ + TPM_SetTimerPeriod(TPM0, USEC_TO_COUNT(98U, tpm_source_clock)); // Drive BRD_REV_ID pin to high GPIO_PortSet(PIN_BOARD_REV_ID_GPIO, PIN_BOARD_REV_ID); // Add a ~100us delay @@ -195,8 +195,7 @@ static mb_version_t read_brd_rev_id(void) { board_version = BOARD_VERSION_2_DEF; } - return BOARD_VERSION_2_0; - //return board_version; + return board_version; } #elif defined(INTERFACE_NRF52820) From f74905d1feca584fd81ba878d25d884996abb7e3 Mon Sep 17 00:00:00 2001 From: Ciro Cattuto Date: Thu, 23 Dec 2021 19:10:40 +0100 Subject: [PATCH 556/617] Disable MSD when external/shield target is enabled - override flash_algo_valid() to disable MSD when board is unsupported or when board is supported and external/shield target is enabled - cleaned up nrf5x_dk_ext.c , added comments --- source/board/nrf5x_dk_ext.c | 223 +++++++++++++++-------------------- source/target/target_board.c | 2 +- 2 files changed, 99 insertions(+), 126 deletions(-) diff --git a/source/board/nrf5x_dk_ext.c b/source/board/nrf5x_dk_ext.c index 246fc80af..1b12597e6 100644 --- a/source/board/nrf5x_dk_ext.c +++ b/source/board/nrf5x_dk_ext.c @@ -28,25 +28,23 @@ #include "target_board.h" // BOARD_ID pointer will be set during run time to point to one of these -const char *board_id_nrf51_mkit = "1070"; const char *board_id_nrf51_dk = "1100"; -const char *board_id_nrf51_dongle = "1120"; const char *board_id_nrf52_dk = "1101"; const char *board_id_nrf52840_dk = "1102"; -const char *board_name_nrf51_mkit = "nRF51822-mKIT"; const char *board_name_nrf51_dk = "nRF51-DK"; -const char *board_name_nrf51_dongle = "nRF51-Dongle"; const char *board_name_nrf52_dk = "nRF52-DK"; const char *board_name_nrf52840_dk = "nRF52840-DK"; static char board_name[14]; -extern target_cfg_t target_device_nrf51822_16; extern target_cfg_t target_device_nrf51822_32; extern target_cfg_t target_device_nrf52_64; extern target_cfg_t target_device_nrf52840; target_cfg_t target_device; -static uint8_t device_type; + +static uint8_t board_supported = 0; +static uint8_t target_ext; +static uint8_t target_shield; // support for dynamic assignment of SWD signals Pio *pin_nreset_port = PIN_OB_nRESET_PORT; // GPIO port for nRESET signal @@ -59,28 +57,12 @@ unsigned long pin_nreset = PIN_OB_nRESET; // GPIO mask for nRESET signal unsigned long pin_swclk = PIN_OB_SWCLK; // GPIO mask for SWCLK signal unsigned long pin_swdio = PIN_OB_SWDIO; // GPIO msak for SWDIO signal -static void set_target_device(uint32_t device) -{ - device_type = device; - if (device == 0) { - target_device = target_device_nrf51822_16; - } else if (device == 1) { - target_device = target_device_nrf51822_32; - } else if (device == 2) { - target_device = target_device_nrf52_64; - } else if (device == 3) { - target_device = target_device_nrf52840; - } -} - static void nrf_prerun_board_config(void) { // Work around for setting the correct board id based on GPIOs uint8_t bit1; uint8_t bit2; uint8_t bit3; - uint8_t target_ext; - uint8_t target_shield; PIOB->PIO_PER = (1 << 1); // Enable PIO pin PB1 PIOB->PIO_PER = (1 << 2); // Enable PIO pin PB2 @@ -96,48 +78,40 @@ static void nrf_prerun_board_config(void) bit2 = (PIOB->PIO_PDSR >> 2) & 1; // Read PB2 bit3 = (PIOB->PIO_PDSR >> 3) & 1; // Read PB3 - /* pins translate to board-ids as follow + /* Pins translate to board-ids as follow. + * Starred IDs are those supported here. * * PB3|PB2|PB1|BOARD ID| BOARD * ---------------------------------- * 0 | 0 | 0 | 1120 | nRF51-Dongle - * 0 | 0 | 1 | 1100 | nRF51-DK - * 0 | 1 | 0 | 1101 | nRF52-DK - * 0 | 1 | 1 | 1102 | nRF52840-DK + * 0 | 0 | 1 | 1100 | nRF51-DK* + * 0 | 1 | 0 | 1101 | nRF52-DK* + * 0 | 1 | 1 | 1102 | nRF52840-DK* * 1 | 1 | 1 | 1070 | nRF51822-mKIT * 1 | 0 | 0 | undefined * 1 | 0 | 1 | undefined * 1 | 1 | 0 | undefined */ - if (bit3) { - set_target_device(0); - target_device.rt_family_id = kNordic_Nrf51_FamilyID; - target_device.rt_board_id = board_id_nrf51_mkit; // 1070 - memcpy(board_name, board_name_nrf51_mkit, sizeof(board_name_nrf51_mkit)); - // Note only a setting of 111 is defined - util_assert(bit2 && bit1); - } else { + if (!bit3) { if (!bit2 && bit1) { - set_target_device(1); + target_device = target_device_nrf51822_32; target_device.rt_family_id = kNordic_Nrf51_FamilyID; target_device.rt_board_id = board_id_nrf51_dk; // 1100 memcpy(board_name, board_name_nrf51_dk, sizeof(board_name_nrf51_dk)); - } else if (!bit2 && !bit1) { - set_target_device(1); - target_device.rt_family_id = kNordic_Nrf51_FamilyID; - target_device.rt_board_id = board_id_nrf51_dongle; // 1120 - memcpy(board_name, board_name_nrf51_dongle, sizeof(board_name_nrf51_dongle)); + board_supported = 1; } else if (bit2 && !bit1) { - set_target_device(2); + target_device = target_device_nrf52_64; target_device.rt_family_id = kNordic_Nrf52_FamilyID; target_device.rt_board_id = board_id_nrf52_dk; // 1101 memcpy(board_name, board_name_nrf52_dk, sizeof(board_name_nrf52_dk)); - } else { //(bit2 && bit1) - set_target_device(3); + board_supported = 1; + } else if (bit2 && bit1) { + target_device = target_device_nrf52840; target_device.rt_family_id = kNordic_Nrf52_FamilyID; target_device.rt_board_id = board_id_nrf52840_dk; // 1102 memcpy(board_name, board_name_nrf52840_dk, sizeof(board_name_nrf52840_dk)); + board_supported = 1; } } @@ -145,92 +119,91 @@ static void nrf_prerun_board_config(void) PIOB->PIO_PUDR = (1 << 2); // Disable pull-up PIOB->PIO_PUDR = (1 << 3); // Disable pull-up - // EXTERNAL TARGET DETECTION - // - supports nRF51-DK, nRF52-DK, nRF52840-DK - // - nRF51-Dongle (discontinued) has no external target lines - // - nRF51822-mKIT (discontinued), no external target lines - // - need to code shield detection and priority between external and shield-mounted targets - - if ( !bit3 && (bit2 || bit1) ) { - // 001 / 010 / 011 above - - // EXT_VTG (high if external target is powered) - PIOB->PIO_PUDR = (1 << 6); // pull-up disable - PIOB->PIO_ODR = (1 << 6); // input - PIOB->PIO_PER = (1 << 6); // GPIO control - bit1 = (PIOB->PIO_PDSR >> 6) & 1; // Read PB6 - - // EXT_GND_DETECT (low if external target is connected) - PIOB->PIO_PUER = (1 << 18); // pull-up enable - PIOB->PIO_ODR = (1 << 18); // input - PIOB->PIO_PER = (1 << 18); // GPIO control - // insert delay? - bit2 = (PIOB->PIO_PDSR >> 18) & 1; // Read PB18 - PIOB->PIO_PUDR = (1 << 18); // pull-up disable - - // nonzero if external target detected - target_ext = bit1 & !bit2; - - // SH_VTG (high if external target is powered) - PIOB->PIO_PUDR = (1 << 5); // pull-up disable - PIOB->PIO_ODR = (1 << 5); // input - PIOB->PIO_PER = (1 << 5); // GPIO control - bit1 = (PIOB->PIO_PDSR >> 5) & 1; // Read PB5 - - // SH_GND_DETECT (low if external target is connected) - PIOB->PIO_PUER = (1 << 23); // pull-up enable - PIOB->PIO_ODR = (1 << 23); // input - PIOB->PIO_PER = (1 << 23); // GPIO control - // insert delay? - bit2 = (PIOB->PIO_PDSR >> 23) & 1; // Read PB23 - PIOB->PIO_PUDR = (1 << 23); // pull-up disable - - // nonzero if external target detected - target_shield = bit1 & !bit2; - - // if external target is detected, re-route SWD signals - if (target_ext) { - pin_nreset_port = PIN_EXT_nRESET_PORT; - pin_nreset_bit = PIN_EXT_nRESET_BIT; - pin_nreset = PIN_EXT_nRESET; - - pin_swclk_port = PIN_EXT_SWCLK_PORT; - pin_swclk_bit = PIN_EXT_SWCLK_BIT; - pin_swclk = PIN_EXT_SWCLK; - - pin_swdio_port = PIN_EXT_SWDIO_PORT; - pin_swdio_bit = PIN_EXT_SWDIO_BIT; - pin_swdio = PIN_EXT_SWDIO; - } else if (target_shield) { - pin_nreset_port = PIN_SH_nRESET_PORT; - pin_nreset_bit = PIN_SH_nRESET_BIT; - pin_nreset = PIN_SH_nRESET; - - pin_swclk_port = PIN_SH_SWCLK_PORT; - pin_swclk_bit = PIN_SH_SWCLK_BIT; - pin_swclk = PIN_SH_SWCLK; - - pin_swdio_port = PIN_SH_SWDIO_PORT; - pin_swdio_bit = PIN_SH_SWDIO_BIT; - pin_swdio = PIN_SH_SWDIO; - } - - // switch on red LED if external or shield target is in use - PIOA->PIO_PUDR = (1 << 28); // pull-up disable - PIOA->PIO_OER = (1 << 28); // output - PIOA->PIO_PER = (1 << 28); // GPIO control - if (target_ext || target_shield) - PIOA->PIO_CODR = (1 << 28); // set low - else - PIOA->PIO_SODR = (1 << 28); // set high + if (!board_supported) + return; + + // External target detection: + // supports nRF51-DK, nRF52-DK, nRF52840-DK + + // EXT_VTG (high if external target is powered) + PIOB->PIO_PUDR = (1 << 6); // pull-up disable + PIOB->PIO_ODR = (1 << 6); // input + PIOB->PIO_PER = (1 << 6); // GPIO control + bit1 = (PIOB->PIO_PDSR >> 6) & 1; // Read PB6 + + // EXT_GND_DETECT (low if external target is connected) + PIOB->PIO_PUER = (1 << 18); // pull-up enable + PIOB->PIO_ODR = (1 << 18); // input + PIOB->PIO_PER = (1 << 18); // GPIO control + bit2 = (PIOB->PIO_PDSR >> 18) & 1; // Read PB18 + PIOB->PIO_PUDR = (1 << 18); // pull-up disable + + // nonzero if external target is detected + target_ext = bit1 & !bit2; + + // SH_VTG (high if shield-mounted target is powered) + PIOB->PIO_PUDR = (1 << 5); // pull-up disable + PIOB->PIO_ODR = (1 << 5); // input + PIOB->PIO_PER = (1 << 5); // GPIO control + bit1 = (PIOB->PIO_PDSR >> 5) & 1; // Read PB5 + + // SH_GND_DETECT (low if shield-mounted target is connected) + PIOB->PIO_PUER = (1 << 23); // pull-up enable + PIOB->PIO_ODR = (1 << 23); // input + PIOB->PIO_PER = (1 << 23); // GPIO control + bit2 = (PIOB->PIO_PDSR >> 23) & 1; // Read PB23 + PIOB->PIO_PUDR = (1 << 23); // pull-up disable + + // nonzero if shield-mounted target is detected + target_shield = bit1 & !bit2; + + // if external/shield target is detected, re-route SWD signals + if (target_ext) { + pin_nreset_port = PIN_EXT_nRESET_PORT; + pin_nreset_bit = PIN_EXT_nRESET_BIT; + pin_nreset = PIN_EXT_nRESET; + + pin_swclk_port = PIN_EXT_SWCLK_PORT; + pin_swclk_bit = PIN_EXT_SWCLK_BIT; + pin_swclk = PIN_EXT_SWCLK; + + pin_swdio_port = PIN_EXT_SWDIO_PORT; + pin_swdio_bit = PIN_EXT_SWDIO_BIT; + pin_swdio = PIN_EXT_SWDIO; + + } else if (target_shield) { + pin_nreset_port = PIN_SH_nRESET_PORT; + pin_nreset_bit = PIN_SH_nRESET_BIT; + pin_nreset = PIN_SH_nRESET; + + pin_swclk_port = PIN_SH_SWCLK_PORT; + pin_swclk_bit = PIN_SH_SWCLK_BIT; + pin_swclk = PIN_SH_SWCLK; + + pin_swdio_port = PIN_SH_SWDIO_PORT; + pin_swdio_bit = PIN_SH_SWDIO_BIT; + pin_swdio = PIN_SH_SWDIO; } + + // switch on red LED if external/shield target is in use + PIOA->PIO_PUDR = (1 << 28); // pull-up disable + PIOA->PIO_OER = (1 << 28); // output + PIOA->PIO_PER = (1 << 28); // GPIO control + if (target_ext || target_shield) + PIOA->PIO_CODR = (1 << 28); // set low + else + PIOA->PIO_SODR = (1 << 28); // set high +} + +// Overrides flash_algo_valid() in source/target/target_board.c . +// Only enables MSD when a supported board is detected and the on-board target is enabled. +uint8_t flash_algo_valid(void) +{ + return (board_supported && !target_ext && !target_shield); } static void nrf_swd_set_target_reset(uint8_t asserted){ - if (asserted && device_type == 0) { - PIOA->PIO_OER = PIN_SWDIO; - PIOA->PIO_OER = PIN_SWCLK; - } else if(!asserted) { + if(!asserted) { PIOA->PIO_MDER = PIN_SWDIO | PIN_SWCLK | PIN_nRESET; } } diff --git a/source/target/target_board.c b/source/target/target_board.c index 6399815f2..410a926de 100644 --- a/source/target/target_board.c +++ b/source/target/target_board.c @@ -57,7 +57,7 @@ NO_OPTIMIZE_POST // NULL and will elide the entire expression. However, the board and target info may be modified // using the post processor script, changing what the code sees at runtime. NO_OPTIMIZE_PRE -uint8_t NO_OPTIMIZE_INLINE flash_algo_valid(void) +__WEAK uint8_t NO_OPTIMIZE_INLINE flash_algo_valid(void) { return (g_board_info.target_cfg != 0); } From 3c91672e20129dff182b63cbff1e6ee2e85bc84c Mon Sep 17 00:00:00 2001 From: Ciro Cattuto Date: Thu, 23 Dec 2021 22:30:23 +0100 Subject: [PATCH 557/617] invalidate board and target before detecting board and external targets - append " (ext") and " (shield)" suffixes to board name if an external target is in use - some more cleanup --- source/board/nrf5x_dk_ext.c | 88 +++++++++++++++----- source/family/nordic/nrf51822/target_nrf51.c | 5 ++ source/target/target_board.c | 4 +- 3 files changed, 75 insertions(+), 22 deletions(-) diff --git a/source/board/nrf5x_dk_ext.c b/source/board/nrf5x_dk_ext.c index 1b12597e6..dbe63e22c 100644 --- a/source/board/nrf5x_dk_ext.c +++ b/source/board/nrf5x_dk_ext.c @@ -28,21 +28,27 @@ #include "target_board.h" // BOARD_ID pointer will be set during run time to point to one of these +const char *board_id_invalid = "0000"; const char *board_id_nrf51_dk = "1100"; const char *board_id_nrf52_dk = "1101"; const char *board_id_nrf52840_dk = "1102"; +const char *board_name_invalid = "UNSUPPORTED"; const char *board_name_nrf51_dk = "nRF51-DK"; const char *board_name_nrf52_dk = "nRF52-DK"; const char *board_name_nrf52840_dk = "nRF52840-DK"; -static char board_name[14]; +static char board_name[24]; // needs to be >= longest board name + longest suffix + 1 +const char *suffix_ext_str = " (ext)"; +const char *suffix_shield_str = " (shield)"; + +extern target_cfg_t target_device_invalid; extern target_cfg_t target_device_nrf51822_32; extern target_cfg_t target_device_nrf52_64; extern target_cfg_t target_device_nrf52840; target_cfg_t target_device; -static uint8_t board_supported = 0; +static uint8_t board_supported; static uint8_t target_ext; static uint8_t target_shield; @@ -63,6 +69,16 @@ static void nrf_prerun_board_config(void) uint8_t bit1; uint8_t bit2; uint8_t bit3; + uint8_t gpio_id; + + // invalidate board + memcpy(board_name, board_name_invalid, sizeof(board_name_invalid)); + board_supported = 0; + + // invalidate target_device + target_device = target_device_invalid; + target_device.rt_family_id = kStub_HWReset_FamilyID; + target_device.rt_board_id = board_id_invalid; PIOB->PIO_PER = (1 << 1); // Enable PIO pin PB1 PIOB->PIO_PER = (1 << 2); // Enable PIO pin PB2 @@ -78,6 +94,12 @@ static void nrf_prerun_board_config(void) bit2 = (PIOB->PIO_PDSR >> 2) & 1; // Read PB2 bit3 = (PIOB->PIO_PDSR >> 3) & 1; // Read PB3 + PIOB->PIO_PUDR = (1 << 1); // Disable pull-up + PIOB->PIO_PUDR = (1 << 2); // Disable pull-up + PIOB->PIO_PUDR = (1 << 3); // Disable pull-up + + gpio_id = (bit3 << 2) | (bit2 << 1) | bit1; + /* Pins translate to board-ids as follow. * Starred IDs are those supported here. * @@ -93,32 +115,28 @@ static void nrf_prerun_board_config(void) * 1 | 1 | 0 | undefined */ - if (!bit3) { - if (!bit2 && bit1) { - target_device = target_device_nrf51822_32; - target_device.rt_family_id = kNordic_Nrf51_FamilyID; - target_device.rt_board_id = board_id_nrf51_dk; // 1100 + // if board is supported, set board name + switch (gpio_id) { + case 0x01: // nRF-51 DK memcpy(board_name, board_name_nrf51_dk, sizeof(board_name_nrf51_dk)); board_supported = 1; - } else if (bit2 && !bit1) { - target_device = target_device_nrf52_64; - target_device.rt_family_id = kNordic_Nrf52_FamilyID; - target_device.rt_board_id = board_id_nrf52_dk; // 1101 + break; + + case 0x02: // nRF52-DK memcpy(board_name, board_name_nrf52_dk, sizeof(board_name_nrf52_dk)); board_supported = 1; - } else if (bit2 && bit1) { - target_device = target_device_nrf52840; - target_device.rt_family_id = kNordic_Nrf52_FamilyID; - target_device.rt_board_id = board_id_nrf52840_dk; // 1102 + break; + + case 0x03: // nRF52840-DK memcpy(board_name, board_name_nrf52840_dk, sizeof(board_name_nrf52840_dk)); board_supported = 1; - } - } + break; - PIOB->PIO_PUDR = (1 << 1); // Disable pull-up - PIOB->PIO_PUDR = (1 << 2); // Disable pull-up - PIOB->PIO_PUDR = (1 << 3); // Disable pull-up + default: + board_supported = 0; + } + // if board is unsupported, we are done. if (!board_supported) return; @@ -171,6 +189,9 @@ static void nrf_prerun_board_config(void) pin_swdio_bit = PIN_EXT_SWDIO_BIT; pin_swdio = PIN_EXT_SWDIO; + // append suffix to board name + memcpy(board_name + strlen(board_name), suffix_ext_str, sizeof(suffix_ext_str)); + } else if (target_shield) { pin_nreset_port = PIN_SH_nRESET_PORT; pin_nreset_bit = PIN_SH_nRESET_BIT; @@ -183,6 +204,33 @@ static void nrf_prerun_board_config(void) pin_swdio_port = PIN_SH_SWDIO_PORT; pin_swdio_bit = PIN_SH_SWDIO_BIT; pin_swdio = PIN_SH_SWDIO; + + // append suffix to board name + memcpy(board_name + strlen(board_name), suffix_shield_str, sizeof(suffix_shield_str)); + + } else { // OB target + switch (gpio_id) { + case 0x01: // nRF-51 DK + target_device = target_device_nrf51822_32; + target_device.rt_family_id = kNordic_Nrf51_FamilyID; + target_device.rt_board_id = board_id_nrf51_dk; + break; + + case 0x02: // nRF52-DK + target_device = target_device_nrf52_64; + target_device.rt_family_id = kNordic_Nrf52_FamilyID; + target_device.rt_board_id = board_id_nrf52_dk; + break; + + case 0x03: // nRF52840-DK + target_device = target_device_nrf52840; + target_device.rt_family_id = kNordic_Nrf52_FamilyID; + target_device.rt_board_id = board_id_nrf52840_dk; + break; + + default: // never reached + ; + } } // switch on red LED if external/shield target is in use diff --git a/source/family/nordic/nrf51822/target_nrf51.c b/source/family/nordic/nrf51822/target_nrf51.c index a0844fe18..72fc4fbd0 100644 --- a/source/family/nordic/nrf51822/target_nrf51.c +++ b/source/family/nordic/nrf51822/target_nrf51.c @@ -55,3 +55,8 @@ target_cfg_t target_device_nrf51822_32 = { .target_vendor = "NordicSemiconductor", .target_part_number = "nRF51822_xxAA", }; + +// invalid target configuration +target_cfg_t target_device_invalid = { + .version = kTargetConfigVersion, +}; diff --git a/source/target/target_board.c b/source/target/target_board.c index 410a926de..a1afb59c6 100644 --- a/source/target/target_board.c +++ b/source/target/target_board.c @@ -30,7 +30,7 @@ // modified using the post processor script, changing what the code sees at runtime. NO_OPTIMIZE_PRE -const char * NO_OPTIMIZE_INLINE get_board_id(void) +__WEAK const char * NO_OPTIMIZE_INLINE get_board_id(void) { if (g_board_info.target_cfg && g_board_info.target_cfg->rt_board_id) { return g_board_info.target_cfg->rt_board_id; //flexible board id @@ -41,7 +41,7 @@ const char * NO_OPTIMIZE_INLINE get_board_id(void) NO_OPTIMIZE_POST NO_OPTIMIZE_PRE -uint16_t NO_OPTIMIZE_INLINE get_family_id(void) +__WEAK uint16_t NO_OPTIMIZE_INLINE get_family_id(void) { if (g_board_info.target_cfg && g_board_info.target_cfg->rt_family_id) { return g_board_info.target_cfg->rt_family_id; //flexible family id From 6c558ac53bcc49704a1b4445ad7d46aeaff6c222 Mon Sep 17 00:00:00 2001 From: Ciro Cattuto Date: Thu, 23 Dec 2021 22:39:21 +0100 Subject: [PATCH 558/617] Fixed board ID for external targets --- source/board/nrf5x_dk_ext.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/source/board/nrf5x_dk_ext.c b/source/board/nrf5x_dk_ext.c index dbe63e22c..9c5d35d47 100644 --- a/source/board/nrf5x_dk_ext.c +++ b/source/board/nrf5x_dk_ext.c @@ -118,16 +118,19 @@ static void nrf_prerun_board_config(void) // if board is supported, set board name switch (gpio_id) { case 0x01: // nRF-51 DK + target_device.rt_board_id = board_id_nrf51_dk; memcpy(board_name, board_name_nrf51_dk, sizeof(board_name_nrf51_dk)); board_supported = 1; break; case 0x02: // nRF52-DK + target_device.rt_board_id = board_id_nrf52_dk; memcpy(board_name, board_name_nrf52_dk, sizeof(board_name_nrf52_dk)); board_supported = 1; break; case 0x03: // nRF52840-DK + target_device.rt_board_id = board_id_nrf52840_dk; memcpy(board_name, board_name_nrf52840_dk, sizeof(board_name_nrf52840_dk)); board_supported = 1; break; From 0f39c45741a7324b00e83e62cd26996ec9414038 Mon Sep 17 00:00:00 2001 From: Ciro Cattuto Date: Thu, 23 Dec 2021 22:53:10 +0100 Subject: [PATCH 559/617] Moved invalid target struct to board file. --- source/board/nrf5x_dk_ext.c | 20 +++++++------------- source/family/nordic/nrf51822/target_nrf51.c | 5 ----- 2 files changed, 7 insertions(+), 18 deletions(-) diff --git a/source/board/nrf5x_dk_ext.c b/source/board/nrf5x_dk_ext.c index 9c5d35d47..b3433b00b 100644 --- a/source/board/nrf5x_dk_ext.c +++ b/source/board/nrf5x_dk_ext.c @@ -28,12 +28,10 @@ #include "target_board.h" // BOARD_ID pointer will be set during run time to point to one of these -const char *board_id_invalid = "0000"; const char *board_id_nrf51_dk = "1100"; const char *board_id_nrf52_dk = "1101"; const char *board_id_nrf52840_dk = "1102"; -const char *board_name_invalid = "UNSUPPORTED"; const char *board_name_nrf51_dk = "nRF51-DK"; const char *board_name_nrf52_dk = "nRF52-DK"; const char *board_name_nrf52840_dk = "nRF52840-DK"; @@ -46,9 +44,14 @@ extern target_cfg_t target_device_invalid; extern target_cfg_t target_device_nrf51822_32; extern target_cfg_t target_device_nrf52_64; extern target_cfg_t target_device_nrf52840; -target_cfg_t target_device; -static uint8_t board_supported; +target_cfg_t target_device = { // invalid by default + .version = kTargetConfigVersion, + .rt_family_id = kStub_HWReset_FamilyID, + .rt_board_id = "0000", +}; + +static uint8_t board_supported = 0; static uint8_t target_ext; static uint8_t target_shield; @@ -71,15 +74,6 @@ static void nrf_prerun_board_config(void) uint8_t bit3; uint8_t gpio_id; - // invalidate board - memcpy(board_name, board_name_invalid, sizeof(board_name_invalid)); - board_supported = 0; - - // invalidate target_device - target_device = target_device_invalid; - target_device.rt_family_id = kStub_HWReset_FamilyID; - target_device.rt_board_id = board_id_invalid; - PIOB->PIO_PER = (1 << 1); // Enable PIO pin PB1 PIOB->PIO_PER = (1 << 2); // Enable PIO pin PB2 PIOB->PIO_PER = (1 << 3); // Enable PIO pin PB3 diff --git a/source/family/nordic/nrf51822/target_nrf51.c b/source/family/nordic/nrf51822/target_nrf51.c index 72fc4fbd0..a0844fe18 100644 --- a/source/family/nordic/nrf51822/target_nrf51.c +++ b/source/family/nordic/nrf51822/target_nrf51.c @@ -55,8 +55,3 @@ target_cfg_t target_device_nrf51822_32 = { .target_vendor = "NordicSemiconductor", .target_part_number = "nRF51822_xxAA", }; - -// invalid target configuration -target_cfg_t target_device_invalid = { - .version = kTargetConfigVersion, -}; From e5371e24727f2d065eb72cd1d571abb7ebb54796 Mon Sep 17 00:00:00 2001 From: Ciro Cattuto Date: Mon, 27 Dec 2021 17:47:43 +0100 Subject: [PATCH 560/617] Fix board name assignments --- source/board/nrf5x_dk_ext.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/source/board/nrf5x_dk_ext.c b/source/board/nrf5x_dk_ext.c index b3433b00b..196abb3d5 100644 --- a/source/board/nrf5x_dk_ext.c +++ b/source/board/nrf5x_dk_ext.c @@ -35,7 +35,7 @@ const char *board_id_nrf52840_dk = "1102"; const char *board_name_nrf51_dk = "nRF51-DK"; const char *board_name_nrf52_dk = "nRF52-DK"; const char *board_name_nrf52840_dk = "nRF52840-DK"; -static char board_name[24]; // needs to be >= longest board name + longest suffix + 1 +static char board_name[24] = "UNKNOWN"; // needs to be >= longest board name + longest suffix + 1 const char *suffix_ext_str = " (ext)"; const char *suffix_shield_str = " (shield)"; @@ -113,19 +113,19 @@ static void nrf_prerun_board_config(void) switch (gpio_id) { case 0x01: // nRF-51 DK target_device.rt_board_id = board_id_nrf51_dk; - memcpy(board_name, board_name_nrf51_dk, sizeof(board_name_nrf51_dk)); + strcpy(board_name, board_name_nrf51_dk); board_supported = 1; break; case 0x02: // nRF52-DK target_device.rt_board_id = board_id_nrf52_dk; - memcpy(board_name, board_name_nrf52_dk, sizeof(board_name_nrf52_dk)); + strcpy(board_name, board_name_nrf52_dk); board_supported = 1; break; case 0x03: // nRF52840-DK target_device.rt_board_id = board_id_nrf52840_dk; - memcpy(board_name, board_name_nrf52840_dk, sizeof(board_name_nrf52840_dk)); + strcpy(board_name, board_name_nrf52840_dk); board_supported = 1; break; @@ -187,7 +187,7 @@ static void nrf_prerun_board_config(void) pin_swdio = PIN_EXT_SWDIO; // append suffix to board name - memcpy(board_name + strlen(board_name), suffix_ext_str, sizeof(suffix_ext_str)); + strcpy(board_name + strlen(board_name), suffix_ext_str); } else if (target_shield) { pin_nreset_port = PIN_SH_nRESET_PORT; @@ -203,7 +203,7 @@ static void nrf_prerun_board_config(void) pin_swdio = PIN_SH_SWDIO; // append suffix to board name - memcpy(board_name + strlen(board_name), suffix_shield_str, sizeof(suffix_shield_str)); + strcpy(board_name + strlen(board_name), suffix_shield_str); } else { // OB target switch (gpio_id) { From 208cb6c62af68a0a663023fe86efb4a94a26c4b1 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 27 Dec 2021 23:45:45 -0600 Subject: [PATCH 561/617] Remove superfluous board ID assignement --- source/board/nrf5x_dk_ext.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/source/board/nrf5x_dk_ext.c b/source/board/nrf5x_dk_ext.c index 196abb3d5..4d373f3ec 100644 --- a/source/board/nrf5x_dk_ext.c +++ b/source/board/nrf5x_dk_ext.c @@ -112,19 +112,16 @@ static void nrf_prerun_board_config(void) // if board is supported, set board name switch (gpio_id) { case 0x01: // nRF-51 DK - target_device.rt_board_id = board_id_nrf51_dk; strcpy(board_name, board_name_nrf51_dk); board_supported = 1; break; case 0x02: // nRF52-DK - target_device.rt_board_id = board_id_nrf52_dk; strcpy(board_name, board_name_nrf52_dk); board_supported = 1; break; case 0x03: // nRF52840-DK - target_device.rt_board_id = board_id_nrf52840_dk; strcpy(board_name, board_name_nrf52840_dk); board_supported = 1; break; From 084b83e8907c4f0ca7e4ed5c5045015882758ce9 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 28 Dec 2021 01:00:29 -0600 Subject: [PATCH 562/617] Add dap_info.py script to display DAP_Info command results --- tools/dap_info.py | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 tools/dap_info.py diff --git a/tools/dap_info.py b/tools/dap_info.py new file mode 100644 index 000000000..1dad382ca --- /dev/null +++ b/tools/dap_info.py @@ -0,0 +1,47 @@ +#!/usr/bin/env python +# +# DAPLink Interface Firmware +# Copyright (c) 2009-2021, Arm Limited, All Rights Reserved +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +from pyocd.probe.pydapaccess.dap_access_api import DAPAccessIntf +from pyocd.probe.cmsis_dap_probe import CMSISDAPProbe +from pyocd.probe.debug_probe import DebugProbe +from pyocd.core.session import Session + +for probe in CMSISDAPProbe.get_all_connected_probes(): + probe.session = Session(probe, False) + probe.open() + probe.connect(DebugProbe.Protocol.SWD) + + # 0x01 = Get the Vendor Name (string). + # 0x02 = Get the Product Name (string). + # 0x03 = Get the Serial Number (string). + # 0x04 = Get the CMSIS-DAP Protocol Version (string). + # 0x05 = Get the Target Device Vendor (string). + # 0x06 = Get the Target Device Name (string). + # 0x07 = Get the Target Board Vendor (string). + # 0x08 = Get the Target Board Name (string). + # 0x09 = Get the Product Firmware Version (string, vendor-specific format). + print("Vendor Name: %s" % probe._link._protocol.dap_info(DAPAccessIntf.ID.VENDOR)) + print("Product Name: %s" % probe._link._protocol.dap_info(DAPAccessIntf.ID.PRODUCT)) + print("Serial Number: %s" % probe._link._protocol.dap_info(DAPAccessIntf.ID.SER_NUM)) + print("CMSIS-DAP Protocol Version: %s" % probe._link._protocol.dap_info(DAPAccessIntf.ID.CMSIS_DAP_PROTOCOL_VERSION)) + print("Target Device Vendor: %s" % probe._link._protocol.dap_info(DAPAccessIntf.ID.DEVICE_VENDOR)) + print("Target Device Name: %s" % probe._link._protocol.dap_info(DAPAccessIntf.ID.DEVICE_NAME)) + print("Target Board Vendor: %s" % probe._link._protocol.dap_info(DAPAccessIntf.ID.BOARD_VENDOR)) + print("Target Board Name: %s" % probe._link._protocol.dap_info(DAPAccessIntf.ID.BOARD_NAME)) + print("Product Firmware Version: %s" % probe._link._protocol.dap_info(DAPAccessIntf.ID.PRODUCT_FW_VERSION)) \ No newline at end of file From 95de294c03c0c005cb7fe99e33f66734e3d47555 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 28 Dec 2021 01:03:43 -0600 Subject: [PATCH 563/617] Align external target detection to board detection --- source/board/nrf5x_dk_ext.c | 39 +++++++++++++++++-------------------- 1 file changed, 18 insertions(+), 21 deletions(-) diff --git a/source/board/nrf5x_dk_ext.c b/source/board/nrf5x_dk_ext.c index 4d373f3ec..b53e34083 100644 --- a/source/board/nrf5x_dk_ext.c +++ b/source/board/nrf5x_dk_ext.c @@ -69,10 +69,7 @@ unsigned long pin_swdio = PIN_OB_SWDIO; // GPIO msak for SWDIO signal static void nrf_prerun_board_config(void) { // Work around for setting the correct board id based on GPIOs - uint8_t bit1; - uint8_t bit2; - uint8_t bit3; - uint8_t gpio_id; + uint8_t bit1, bit2, bit3, gpio_id; PIOB->PIO_PER = (1 << 1); // Enable PIO pin PB1 PIOB->PIO_PER = (1 << 2); // Enable PIO pin PB2 @@ -137,37 +134,37 @@ static void nrf_prerun_board_config(void) // External target detection: // supports nRF51-DK, nRF52-DK, nRF52840-DK - // EXT_VTG (high if external target is powered) + // Configure GPIO for detection + // - EXT_VTG (high if external target is powered) PIOB->PIO_PUDR = (1 << 6); // pull-up disable PIOB->PIO_ODR = (1 << 6); // input PIOB->PIO_PER = (1 << 6); // GPIO control - bit1 = (PIOB->PIO_PDSR >> 6) & 1; // Read PB6 - - // EXT_GND_DETECT (low if external target is connected) + // - EXT_GND_DETECT (low if external target is connected) PIOB->PIO_PUER = (1 << 18); // pull-up enable PIOB->PIO_ODR = (1 << 18); // input PIOB->PIO_PER = (1 << 18); // GPIO control - bit2 = (PIOB->PIO_PDSR >> 18) & 1; // Read PB18 - PIOB->PIO_PUDR = (1 << 18); // pull-up disable - - // nonzero if external target is detected - target_ext = bit1 & !bit2; - - // SH_VTG (high if shield-mounted target is powered) + // - SH_VTG (high if shield-mounted target is powered) PIOB->PIO_PUDR = (1 << 5); // pull-up disable PIOB->PIO_ODR = (1 << 5); // input PIOB->PIO_PER = (1 << 5); // GPIO control - bit1 = (PIOB->PIO_PDSR >> 5) & 1; // Read PB5 - - // SH_GND_DETECT (low if shield-mounted target is connected) + // - SH_GND_DETECT (low if shield-mounted target is connected) PIOB->PIO_PUER = (1 << 23); // pull-up enable PIOB->PIO_ODR = (1 << 23); // input PIOB->PIO_PER = (1 << 23); // GPIO control - bit2 = (PIOB->PIO_PDSR >> 23) & 1; // Read PB23 - PIOB->PIO_PUDR = (1 << 23); // pull-up disable + + // nonzero if external target is detected + bit1 = (PIOB->PIO_PDSR >> 6) & 1; // Read PB6 + bit2 = (PIOB->PIO_PDSR >> 18) & 1; // Read PB18 + target_ext = bit1 & !bit2; // nonzero if shield-mounted target is detected - target_shield = bit1 & !bit2; + bit1 = (PIOB->PIO_PDSR >> 5) & 1; // Read PB5 + bit2 = (PIOB->PIO_PDSR >> 23) & 1; // Read PB23 + target_shield = bit1 & !bit2; + + // Disable pull-ups for detection + PIOB->PIO_PUDR = (1 << 18); // pull-up disable + PIOB->PIO_PUDR = (1 << 23); // pull-up disable // if external/shield target is detected, re-route SWD signals if (target_ext) { From 46f388d705481ece85b0e8684f5c4348d878a20e Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 28 Dec 2021 01:09:26 -0600 Subject: [PATCH 564/617] Make external target detection less restrictive Switch to external or shield if VCC or GNDdetect are detected. Requiring both to be detected would reduce the number of targets that can be debugged --- source/board/nrf5x_dk_ext.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/source/board/nrf5x_dk_ext.c b/source/board/nrf5x_dk_ext.c index b53e34083..136796a93 100644 --- a/source/board/nrf5x_dk_ext.c +++ b/source/board/nrf5x_dk_ext.c @@ -155,12 +155,12 @@ static void nrf_prerun_board_config(void) // nonzero if external target is detected bit1 = (PIOB->PIO_PDSR >> 6) & 1; // Read PB6 bit2 = (PIOB->PIO_PDSR >> 18) & 1; // Read PB18 - target_ext = bit1 & !bit2; + target_ext = bit1 | !bit2; // nonzero if shield-mounted target is detected bit1 = (PIOB->PIO_PDSR >> 5) & 1; // Read PB5 bit2 = (PIOB->PIO_PDSR >> 23) & 1; // Read PB23 - target_shield = bit1 & !bit2; + target_shield = bit1 | !bit2; // Disable pull-ups for detection PIOB->PIO_PUDR = (1 << 18); // pull-up disable From 00484a4b69716b3c46a16ac78e8d5d6e77144591 Mon Sep 17 00:00:00 2001 From: Ciro Cattuto Date: Tue, 28 Dec 2021 18:47:34 +0100 Subject: [PATCH 565/617] Fixed board name assignments in mkit_dk_dongle_nrf5x (#914) --- source/board/mkit_dk_dongle_nrf5x.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/source/board/mkit_dk_dongle_nrf5x.c b/source/board/mkit_dk_dongle_nrf5x.c index 012346685..47b3484c4 100644 --- a/source/board/mkit_dk_dongle_nrf5x.c +++ b/source/board/mkit_dk_dongle_nrf5x.c @@ -101,7 +101,7 @@ static void nrf_prerun_board_config(void) set_target_device(0); target_device.rt_family_id = kNordic_Nrf51_FamilyID; target_device.rt_board_id = board_id_nrf51_mkit; // 1070 - memcpy(board_name, board_name_nrf51_mkit, sizeof(board_name_nrf51_mkit)); + strcpy(board_name, board_name_nrf51_mkit); // Note only a setting of 111 is defined util_assert(bit2 && bit1); } else { @@ -109,22 +109,22 @@ static void nrf_prerun_board_config(void) set_target_device(1); target_device.rt_family_id = kNordic_Nrf51_FamilyID; target_device.rt_board_id = board_id_nrf51_dk; // 1100 - memcpy(board_name, board_name_nrf51_dk, sizeof(board_name_nrf51_dk)); + strcpy(board_name, board_name_nrf51_dk); } else if (!bit2 && !bit1) { set_target_device(1); target_device.rt_family_id = kNordic_Nrf51_FamilyID; target_device.rt_board_id = board_id_nrf51_dongle; // 1120 - memcpy(board_name, board_name_nrf51_dongle, sizeof(board_name_nrf51_dongle)); + strcpy(board_name, board_name_nrf51_dongle); } else if (bit2 && !bit1) { set_target_device(2); target_device.rt_family_id = kNordic_Nrf52_FamilyID; target_device.rt_board_id = board_id_nrf52_dk; // 1101 - memcpy(board_name, board_name_nrf52_dk, sizeof(board_name_nrf52_dk)); + strcpy(board_name, board_name_nrf52_dk); } else { //(bit2 && bit1) set_target_device(3); target_device.rt_family_id = kNordic_Nrf52_FamilyID; target_device.rt_board_id = board_id_nrf52840_dk; // 1102 - memcpy(board_name, board_name_nrf52840_dk, sizeof(board_name_nrf52840_dk)); + strcpy(board_name, board_name_nrf52840_dk); } } From d22d50191ae21be8e3ae73d7d2095df2de73651b Mon Sep 17 00:00:00 2001 From: a_p_u_r_o Date: Sun, 2 Jan 2022 10:07:59 +0900 Subject: [PATCH 566/617] Fix HID interface of LPC55xx HIC (#917) --- source/hic_hal/nxp/lpc55xx/usbd_LPC55xx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/source/hic_hal/nxp/lpc55xx/usbd_LPC55xx.c b/source/hic_hal/nxp/lpc55xx/usbd_LPC55xx.c index 01ddbf3f5..564306954 100644 --- a/source/hic_hal/nxp/lpc55xx/usbd_LPC55xx.c +++ b/source/hic_hal/nxp/lpc55xx/usbd_LPC55xx.c @@ -628,7 +628,8 @@ uint32_t USBD_ReadEP(uint32_t EPNum, uint8_t *pData, uint32_t size) memcpy(pData, dataptr, cnt); - *ptr = N_BYTES(EPBufInfo[EP_OUT_IDX(EPNum)].buf_len) | + *ptr = (*ptr & (EP_TYPE | EP_RF_TV)) | + N_BYTES(EPBufInfo[EP_OUT_IDX(EPNum)].buf_len) | BUF_ADDR(EPBufInfo[EP_OUT_IDX(EPNum)].buf_ptr) | EP_BUF_ACTIVE; From 0f57f81a1f2c91f1dc2dbb9ff1142aa93cfb7c41 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 29 Dec 2021 12:16:07 -0600 Subject: [PATCH 567/617] mimxrt: add test configuration --- test/info.py | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/test/info.py b/test/info.py index ab3bf5d54..3c76a6288 100644 --- a/test/info.py +++ b/test/info.py @@ -142,14 +142,16 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0220, VENDOR_TO_FAMILY('NXP', 2), 'k20dx_frdmkl46z_if', 'k20dx_bl', 'FRDM-KL46Z' ), ( 0x0224, VENDOR_TO_FAMILY('NXP', 1), 'k20dx_frdmk28f_if', 'k20dx_bl', None ), # TODO - set target to 'FRDM-K28F' when mbed-os supports this ( 0x0225, VENDOR_TO_FAMILY('NXP', 1), 'k26f_frdmk32w042_if', 'k26f_bl', None ), # TODO - set target to 'FRDM-K32W042' when mbed-os supports this - ( 0x0226, VENDOR_TO_FAMILY('NXP', 3), 'k20dx_mimxrt1020_evk_qspi_if', 'k20dx_bl', None ), # TODO - set target to 'MIMX6RT1050' when mbed-os supports this - ( 0x0227, VENDOR_TO_FAMILY('NXP', 3), 'k20dx_mimxrt1050_evk_hyper_if', 'k20dx_bl', None ), # TODO - set target to 'MIMX6RT1050' when mbed-os supports this - ( 0x0227, VENDOR_TO_FAMILY('NXP', 3), 'k20dx_mimxrt1050_evk_qspi_if', 'k20dx_bl', None ), # TODO - set target to 'MIMX6RT1050' when mbed-os supports this + ( 0x0226, VENDOR_TO_FAMILY('NXP', 3), 'k20dx_mimxrt1020_evk_qspi_if', 'k20dx_bl', 'MIMXRT1020' ), + ( 0x0227, VENDOR_TO_FAMILY('NXP', 3), 'k20dx_mimxrt1050_evk_hyper_if', 'k20dx_bl', 'MIMXRT1050-HYPER' ), + ( 0x0227, VENDOR_TO_FAMILY('NXP', 3), 'k20dx_mimxrt1050_evk_qspi_if', 'k20dx_bl', 'MIMXRT1050-QSPI' ), ( 0x0228, VENDOR_TO_FAMILY('NXP', 4), 'k20dx_rapid_iot_if', 'k20dx_bl', None ), # TODO - set target to 'Rapid-IoT' when mbed-os supports this + ( 0x0229, VENDOR_TO_FAMILY('NXP', 3), 'lpc4322_mimxrt1060_evk_qspi_if', 'lpc4322_bl', 'MIMXRT1060' ), ( 0x0230, VENDOR_TO_FAMILY('NXP', 1), 'k20dx_frdmk20dx_if', 'k20dx_bl', 'FRDM-K20D50M' ), ( 0x0231, VENDOR_TO_FAMILY('NXP', 1), 'k20dx_frdmk22f_if', 'k20dx_bl', 'FRDM-K22F' ), ( 0x0236, VENDOR_TO_FAMILY('NXP', 0), 'lpc4322_lpc55s69xpresso_if', 'lpc4322_bl', 'LPCXpresso55S69' ), ( 0x0240, VENDOR_TO_FAMILY('NXP', 1), 'k20dx_frdmk64f_if', 'k20dx_bl', 'FRDM-K64F' ), + ( 0x0244, VENDOR_TO_FAMILY('NXP', 3), 'lpc4322_mimxrt1170_evk_qspi_if', 'lpc4322_bl', 'MIMXRT1170' ), ( 0x0250, VENDOR_TO_FAMILY('NXP', 1), 'k20dx_frdmkw24d_if', 'k20dx_bl', 'FRDM-KW24D512' ), ( 0x0260, VENDOR_TO_FAMILY('NXP', 2), 'k20dx_frdmkl26z_if', 'k20dx_bl', None ), ( 0x0261, VENDOR_TO_FAMILY('NXP', 2), 'k20dx_frdmkl27z_if', 'k20dx_bl', 'FRDM-KL27Z' ), @@ -176,7 +178,7 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x1018, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_ssci824_if', None, 'Switch-Science-mbed-LPC824' ), ( 0x1019, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_sscity_if', None, 'Switch-Science-mbed-TY51822r3' ), ( 0x1021, VENDOR_TO_FAMILY('Nordic', 1), 'lpc11u35_ssci_chibi_if', None, None ), # TODO - set target to 'SSCI-MBIT' when mbed-os supports this - ( 0x1028, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_pitaya_link_if', None, None ), + ( 0x1028, VENDOR_TO_FAMILY('Nordic', 2), 'lpc11u35_pitaya_link_if', None, None ), ( 0x1050, VENDOR_TO_FAMILY('Stub', 1), 'lpc11u35_lpc812xpresso_if', None, 'NXP-LPC800-MAX' ), ( 0x1054, VENDOR_TO_FAMILY('Stub', 1), 'lpc4322_lpc54114xpresso_if', 'lpc4322_bl', 'LPCXpresso54114' ), ( 0x1056, VENDOR_TO_FAMILY('Stub', 1), 'lpc4322_lpc54608xpresso_if', 'lpc4322_bl', 'LPCXpresso54608' ), From 6ceb627d8e4c13e1d56581f4fa3702da5d861b29 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 29 Dec 2021 12:19:02 -0600 Subject: [PATCH 568/617] mimxrt: revert changes to custom validate_bin_nvic() --- source/family/freescale/target_reset_mimxrt.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/source/family/freescale/target_reset_mimxrt.c b/source/family/freescale/target_reset_mimxrt.c index a8b49ce18..0777b5a4c 100644 --- a/source/family/freescale/target_reset_mimxrt.c +++ b/source/family/freescale/target_reset_mimxrt.c @@ -21,7 +21,6 @@ #include "swd_host.h" #include "info.h" -#include "target_config.h" #include "target_family.h" #include "cmsis_os2.h" @@ -49,14 +48,10 @@ static void prerun_target_config(void) #ifdef DAPLINK_MIMXRT_TARGET static uint8_t validate_bin_nvic(const uint8_t *buf) { - if(buf[0] == 'F' && buf[1] == 'C' && buf[2] == 'F' && buf[3] == 'B') - { - target_device.flash_regions[0].start = 0x30000400; - return 1; - } - else if(buf[0] == 0xFF && buf[1] == 0xFF && buf[2] == 0xFF && buf[3] == 0xFF) - { - target_device.flash_regions[0].start = 0x30000000; + // Flash Configuration Block + // https://www.nxp.com/docs/en/nxp/application-notes/AN12238.pdf + if ((buf[0] == 'F' && buf[1] == 'C' && buf[2] == 'F' && buf[3] == 'B')) { + // FlexSPI Configuration Block return 1; } From 65e2c466f279f76b31de90610730a72f0eae7e22 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 30 Dec 2021 01:25:28 -0600 Subject: [PATCH 569/617] mimxrt: Fix MIMXRT1060 sectors_info --- source/family/nxp/mimxrt1060_spi_flash/flash_blob.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/family/nxp/mimxrt1060_spi_flash/flash_blob.c b/source/family/nxp/mimxrt1060_spi_flash/flash_blob.c index abf5b4346..d50c0919d 100644 --- a/source/family/nxp/mimxrt1060_spi_flash/flash_blob.c +++ b/source/family/nxp/mimxrt1060_spi_flash/flash_blob.c @@ -122,7 +122,7 @@ static const uint32_t flash_size = 0x00800000; * at address flash_start + flash_size. */ static const sector_info_t sectors_info[] = { - 0x60000000, 0x00010000, + {0x60000000, 0x00010000}, }; static const program_target_t flash = { From 716b3836e7427ad6213083684414a14dc294702c Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 30 Dec 2021 03:15:29 -0600 Subject: [PATCH 570/617] mimxrt: Fix MIMXRT1060 stack and buffer pointers --- source/family/nxp/mimxrt1060_spi_flash/flash_blob.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/source/family/nxp/mimxrt1060_spi_flash/flash_blob.c b/source/family/nxp/mimxrt1060_spi_flash/flash_blob.c index d50c0919d..e45e51a01 100644 --- a/source/family/nxp/mimxrt1060_spi_flash/flash_blob.c +++ b/source/family/nxp/mimxrt1060_spi_flash/flash_blob.c @@ -139,10 +139,10 @@ static const program_target_t flash = { { 0x20000001, 0x20000934, - 0x20000c00 + 0x20008000 }, - 0x20000000 + 0x00000A00, // mem buffer location + 0x20000000 + 0x00004000, // mem buffer location 0x20000000, // location to write prog_blob in target RAM sizeof(MIMXRT106x_QSPI_4KB_SEC_flash_prog_blob), // prog_blob size MIMXRT106x_QSPI_4KB_SEC_flash_prog_blob, // address of prog_blob From f86e26ec688b3d4a60e26a6fedc45c0fe312e4d0 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 30 Dec 2021 17:28:13 -0600 Subject: [PATCH 571/617] flash: import modified flash algo conversion script --- tools/generate_flash_algo.py | 267 +++++++++++++++++++++++++++++++++++ 1 file changed, 267 insertions(+) create mode 100644 tools/generate_flash_algo.py diff --git a/tools/generate_flash_algo.py b/tools/generate_flash_algo.py new file mode 100644 index 000000000..6024ea6a7 --- /dev/null +++ b/tools/generate_flash_algo.py @@ -0,0 +1,267 @@ +#!/usr/bin/env python3 +# +# DAPLink Interface Firmware +# Copyright (c) 2011-2021 Arm Limited +# Copyright (c) 2021 Chris Reed +# Copyright (c) 2021 Mathias Brossard +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import argparse +import binascii +import colorama +import hashlib +import jinja2 +import os +import struct +from datetime import datetime +from pyocd.target.pack.flash_algo import PackFlashAlgo + +BLOB_HEADER = '0xe00abe00,' +HEADER_SIZE = 4 +STACK_SIZE = 0x400 + +DAPLINK_TEMPLATE = \ +"""/* Flash OS Routines (Automagically Generated) + * + * DAPLink Interface Firmware + * Copyright (c) {{year}} {{copyright_owner}} + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +// Generated from '{{ filename }}'{%- if algo.flash_info.name %}{{ " (%s)" % algo.flash_info.name.decode('utf-8') }}{% endif %} +{%- if pack_file %} +// Originating from '{{ pack_file }}' +{%- endif %} +// digest = {{ digest }}, file size = {{ file_size}} +// {{ 'algo version = 0x%x, algo size = %d (0x%x)' % (algo.flash_info.version, algo_size + header_size, algo_size + header_size) }} +static const uint32_t {{name}}_flash_prog_blob[] = { + {{prog_header}} + {{algo.format_algo_data(4, 8, "c")}} +}; + +// Start address of flash +static const uint32_t flash_start = {{"0x%08x" % algo.flash_start}}; +// Size of flash +static const uint32_t flash_size = {{"0x%08x" % algo.flash_size}}; + +/** +* List of start and size for each size of flash sector - even indexes are start, odd are size +* The size will apply to all sectors between the listed address and the next address +* in the list. +* The last pair in the list will have sectors starting at that address and ending +* at address flash_start + flash_size. +*/ +static const sector_info_t sectors_info[] = { +{%- for start, size in algo.sector_sizes %} + {{ "{0x%08x, 0x%08x}" % (start + algo.flash_start, size) }}, +{%- endfor %} +}; + +static const program_target_t flash = { + {{'0x%08x' % (algo.symbols['Init'] + header_size + entry)}}, // Init + {{'0x%08x' % (algo.symbols['UnInit'] + header_size + entry)}}, // UnInit + {{'0x%08x' % (algo.symbols['EraseChip'] + header_size + entry)}}, // EraseChip + {{'0x%08x' % (algo.symbols['EraseSector'] + header_size + entry)}}, // EraseSector + {{'0x%08x' % (algo.symbols['ProgramPage'] + header_size + entry)}}, // ProgramPage +{%- if 'Verify' in algo.symbols and algo.symbols['Verify'] < 0xFFFFFFFF %} + {{'0x%08x' % (algo.symbols['Verify'] + header_size + entry)}}, // Verify +{%- else %} + 0x00000000, // Verify +{%- endif %} + + // BKPT : start of blob + 1 + // RSB : blob start + header + rw data offset + // RSP : stack pointer + { + {{'0x%08x' % (entry + 1)}}, + {{'0x%08x' % (entry + header_size + algo.rw_start)}}, + {{'0x%08x' % stack_pointer}} + }, + + // mem buffer location + {{'0x%08x' % stack_pointer}}, + // location to write prog_blob in target RAM + {{'0x%08x' % entry}}, + // prog_blob size + sizeof({{name}}_flash_prog_blob), + // address of prog_blob + {{name}}_flash_prog_blob, + // ram_to_flash_bytes_to_be_written + {{'0x%08x' % algo.page_size}} +}; + +""" + +colorama.init() + +def str_to_num(val): + return int(val, 0) #convert string to number and automatically handle hex conversion + +class PackFlashAlgoGenerator(PackFlashAlgo): + """ + Class to wrap a flash algo + + This class is intended to provide easy access to the information + provided by a flash algorithm, such as symbols and the flash + algorithm itself. + """ + + def format_algo_data(self, spaces, group_size, fmt): + """" + Return a string representing algo_data suitable for use in a template + + The string is intended for use in a template. + + :param spaces: The number of leading spaces for each line + :param group_size: number of elements per line (element type + depends of format) + :param fmt: - format to create - can be either "hex" or "c" + """ + padding = " " * spaces + if fmt == "hex": + blob = binascii.b2a_hex(self.algo_data) + line_list = [] + for i in range(0, len(blob), group_size): + line_list.append('"' + blob[i:i + group_size] + '"') + return ("\n" + padding).join(line_list) + elif fmt == "c": + blob = self.algo_data[:] + pad_size = 0 if len(blob) % 4 == 0 else 4 - len(blob) % 4 + blob = blob + b"\x00" * pad_size + integer_list = struct.unpack("<" + "L" * (len(blob) // 4), blob) + line_list = [] + for pos in range(0, len(integer_list), group_size): + group = ["0x%08x" % value for value in + integer_list[pos:pos + group_size]] + line_list.append(", ".join(group)) + return (",\n" + padding).join(line_list) + else: + raise Exception("Unsupported format %s" % fmt) + + def process_template(self, template_text, data_dict=None): + """ + Generate output from the supplied template + + All the public methods and fields of this class can be accessed from + the template via "algo". + + :param template_path: Relative or absolute file path to the template + :param data_dict: Additional data to use when generating + """ + if data_dict is None: + data_dict = {} + else: + assert isinstance(data_dict, dict) + data_dict = dict(data_dict) + assert "algo" not in data_dict, "algo already set by user data" + data_dict["algo"] = self + data_dict["algo_size"] = len(self.algo_data) + + template = jinja2.Template(template_text) + return template.render(data_dict) + +def main(): + parser = argparse.ArgumentParser(description="Blob generator") + parser.add_argument("elf_path", help="Elf, axf, or flm to extract flash algo from") + parser.add_argument("--blob-start", default=0x20000000, type=str_to_num, help="Starting " + "address of the flash blob in target RAM.") + parser.add_argument("--stack-size", default=STACK_SIZE, type=str_to_num, help="Stack size for the algo " + f"(default {STACK_SIZE}).") + parser.add_argument("--pack-path", default=None, help="Path to pack file from which flash algo is from") + parser.add_argument("-i", "--info-only", action="store_true", help="Only print information about the flash " + "algo, do not generate a blob.") + parser.add_argument("-o", "--output", default="target_blob.c", help="Path of output file " + "(default 'target_blob.c').") + parser.add_argument("-t", "--template", help="Path to Jinja template file (default is an internal " + "template for DAPLink).") + parser.add_argument('-c', '--copyright', help="Set copyright owner.") + args = parser.parse_args() + + if not args.copyright: + print(f"{colorama.Fore.YELLOW}Warning! No copyright owner was specified. Defaulting to \"Arm Limited\". " + f"Please set via --copyright, or edit output.{colorama.Style.RESET_ALL}") + + if args.template: + with open(args.template, "r") as tmpl_file: + tmpl = tmpl_file.read() + else: + tmpl = DAPLINK_TEMPLATE + + with open(args.elf_path, "rb") as file_handle: + algo = PackFlashAlgoGenerator(file_handle) + + print(algo.flash_info) + + if args.info_only: + return + + pack_file = None + if args.pack_path and os.path.exists(args.pack_path) and 'cmsis-pack-manager' in args.pack_path: + (rest, version) = (os.path.split(args.pack_path)) + (rest, pack) = (os.path.split(rest)) + (_, vendor) = (os.path.split(rest)) + pack_file = '%s.%s.%s' % (vendor, pack, version) + elif args.pack_path: + pack_file = os.path.split(args.pack_path)[-1] + else: + print(f"{colorama.Fore.YELLOW}Warning! No CMSIS Pack was set." + f"Please set the path or file name of the CMSIS pack via --pack-path.{colorama.Style.RESET_ALL}") + + file_handle.seek(0) + flm_content = file_handle.read() + hash = hashlib.sha256() + hash.update(flm_content) + + # Allocate stack after algo and its rw data, with top and bottom rounded to 256 bytes. + stack_base = args.blob_start + HEADER_SIZE + algo.rw_start + algo.rw_size + stack_base = (stack_base + 7) // 8 * 8 + sp = stack_base + args.stack_size + sp = (sp + 255) // 256 * 256 + + data_dict = { + 'filename': os.path.split(args.elf_path)[-1], + 'digest': hash.hexdigest(), + 'file_size': len(flm_content), + 'pack_file': pack_file, + 'name': os.path.splitext(os.path.split(args.elf_path)[-1])[0], + 'prog_header': BLOB_HEADER, + 'header_size': HEADER_SIZE, + 'entry': args.blob_start, + 'stack_pointer': sp, + 'year': datetime.now().year, + 'copyright_owner': args.copyright or "Arm Limited", + } + + text = algo.process_template(tmpl, data_dict) + + with open(args.output, "w") as file_handle: + file_handle.write(text) + + print(f"Wrote flash algo dict to {args.output}") + +if __name__ == '__main__': + main() From ff10f64ad652cd03d2fb6161a7ea4cce1f5a8465 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 30 Dec 2021 20:05:22 -0600 Subject: [PATCH 572/617] flash: additional enhancements from pyocd --- tools/generate_flash_algo.py | 48 +++++++++++++++++++++++++++++------- 1 file changed, 39 insertions(+), 9 deletions(-) diff --git a/tools/generate_flash_algo.py b/tools/generate_flash_algo.py index 6024ea6a7..6dd3cac19 100644 --- a/tools/generate_flash_algo.py +++ b/tools/generate_flash_algo.py @@ -28,9 +28,18 @@ from datetime import datetime from pyocd.target.pack.flash_algo import PackFlashAlgo -BLOB_HEADER = '0xe00abe00,' +# This header consists of two instructions: +# +# ``` +# bkpt #0 +# b .-2 # branch to the bkpt +# ``` +# +# Before running a flash algo operation, LR is set to the address of the `bkpt` instruction, +# so when the operation function returns it will halt the CPU. +BLOB_HEADER = '0xe7fdbe00,' HEADER_SIZE = 4 -STACK_SIZE = 0x400 +STACK_SIZE = 0x800 DAPLINK_TEMPLATE = \ """/* Flash OS Routines (Automagically Generated) @@ -179,7 +188,6 @@ def process_template(self, template_text, data_dict=None): data_dict = dict(data_dict) assert "algo" not in data_dict, "algo already set by user data" data_dict["algo"] = self - data_dict["algo_size"] = len(self.algo_data) template = jinja2.Template(template_text) return template.render(data_dict) @@ -216,6 +224,33 @@ def main(): print(algo.flash_info) + # Allocate stack after algo and its rw/zi data, with bottom rounded to 8 bytes. + stack_base = (args.blob_start + HEADER_SIZE + + algo.rw_start + algo.rw_size # rw_start incorporates instruction size + + algo.zi_size) + stack_base = (stack_base + 7) // 8 * 8 + # Stack top rounded to at least 256 bytes + sp = stack_base + args.stack_size + if algo.page_size > 256: + sp = (sp + algo.page_size - 1) // algo.page_size * algo.page_size + else: + sp = (sp + 255) // 256 * 256 + + print(f"load addr: {args.blob_start:#010x}") + print(f"header: {HEADER_SIZE:#x} bytes") + print(f"data: {len(algo.algo_data):#x} bytes") + print(f"ro: {algo.ro_start:#010x} + {algo.ro_size:#x} bytes") + print(f"rw: {algo.rw_start:#010x} + {algo.rw_size:#x} bytes") + print(f"zi: {algo.zi_start:#010x} + {algo.zi_size:#x} bytes") + print(f"stack: {stack_base:#010x} .. {sp:#010x} ({sp - stack_base:#x} bytes)") + print(f"buffer: {sp:#010x} .. {sp + algo.page_size:#010x} ({algo.page_size:#x} bytes)") + + print("\nSymbol offsets:") + for n, v in sorted(algo.symbols.items(), key=lambda x: x[1]): + if v >= 0xffffffff: + continue + print(f"{n}:{' ' * (11 - len(n))} {v:#010x}") + if args.info_only: return @@ -236,17 +271,12 @@ def main(): hash = hashlib.sha256() hash.update(flm_content) - # Allocate stack after algo and its rw data, with top and bottom rounded to 256 bytes. - stack_base = args.blob_start + HEADER_SIZE + algo.rw_start + algo.rw_size - stack_base = (stack_base + 7) // 8 * 8 - sp = stack_base + args.stack_size - sp = (sp + 255) // 256 * 256 - data_dict = { 'filename': os.path.split(args.elf_path)[-1], 'digest': hash.hexdigest(), 'file_size': len(flm_content), 'pack_file': pack_file, + 'algo_size': len(algo.algo_data), 'name': os.path.splitext(os.path.split(args.elf_path)[-1])[0], 'prog_header': BLOB_HEADER, 'header_size': HEADER_SIZE, From 4b50663d267a55ddab5ccfd7d3eb268659d2acf7 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 30 Dec 2021 22:15:35 -0600 Subject: [PATCH 573/617] mimxrt: update MIMXRT1060 flash algo parameters python tools/generate_flash_algo.py \ --pack-path NXP.MIMXRT1062_DFP.13.1.1.pack \ -o source/family/nxp/mimxrt1060_spi_flash/flash_blob.c \ arm/MIMXRT106x_QSPI_4KB_SEC.FLM --- .../nxp/mimxrt1060_spi_flash/flash_blob.c | 31 +++++++++++++------ 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/source/family/nxp/mimxrt1060_spi_flash/flash_blob.c b/source/family/nxp/mimxrt1060_spi_flash/flash_blob.c index e45e51a01..e437bb936 100644 --- a/source/family/nxp/mimxrt1060_spi_flash/flash_blob.c +++ b/source/family/nxp/mimxrt1060_spi_flash/flash_blob.c @@ -1,5 +1,7 @@ -/* Flash OS Routines (Automagically Generated) - * Copyright (c) 2009-2021 Arm Limited +/* Flash algorithm for MIMXRT106x 8mB QuadSPI NOR Flash + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2021 Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,8 +17,12 @@ * limitations under the License. */ +// Generated from 'MIMXRT106x_QSPI_4KB_SEC.FLM' (MIMXRT106x 8mB QuadSPI NOR Flash) +// Originating from 'NXP.MIMXRT1062_DFP.13.1.1.pack' +// digest = 4b2722f4859e5a519ee072466d51eb02e131fbffbe5d8bdffdf025e5f71923ad, file size = 2847664 +// algo version = 0x101, algo size = 2880 (0xb40) static const uint32_t MIMXRT106x_QSPI_4KB_SEC_flash_prog_blob[] = { - 0xE00ABE00, + 0xe7fdbe00, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x4855b51c, 0x48559000, 0x08498901, 0x81010049, 0x890a4953, 0x00520852, 0x8802810a, 0x07522304, 0xda022a00, 0x439a8802, 0x88088002, 0xd5020740, 0x43988808, 0x484c8008, 0x6041494a, 0x6081494b, 0x22806801, 0x22204391, @@ -131,7 +137,7 @@ static const program_target_t flash = { 0x20000125, // EraseChip 0x20000139, // EraseSector 0x20000157, // ProgramPage - 0x0, // Verify + 0x00000000, // Verify // BKPT : start of blob + 1 // RSB : blob start + header + rw data offset @@ -139,12 +145,17 @@ static const program_target_t flash = { { 0x20000001, 0x20000934, - 0x20008000 + 0x20001400 }, - 0x20000000 + 0x00004000, // mem buffer location - 0x20000000, // location to write prog_blob in target RAM - sizeof(MIMXRT106x_QSPI_4KB_SEC_flash_prog_blob), // prog_blob size - MIMXRT106x_QSPI_4KB_SEC_flash_prog_blob, // address of prog_blob - 0x00000100 // ram_to_flash_bytes_to_be_written + // mem buffer location + 0x20001400, + // location to write prog_blob in target RAM + 0x20000000, + // prog_blob size + sizeof(MIMXRT106x_QSPI_4KB_SEC_flash_prog_blob), + // address of prog_blob + MIMXRT106x_QSPI_4KB_SEC_flash_prog_blob, + // ram_to_flash_bytes_to_be_written + 0x00000100 }; From 1ecbbb2d6efb4a48b057f2d4ad8dc06749943da1 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 30 Dec 2021 23:41:29 -0600 Subject: [PATCH 574/617] mimxrt: update flash algorithms for MIMXRT1050 projects python tools/generate_flash_algo.py \ MIMXRT1052_DFP/arm/MIMXRT105x_QuadSPI_4KB_SEC.FLM \ --pack-path NXP.MIMXRT1052_DFP.13.1.1.pack \ -o source/family/freescale/mimxrt1050_spi_flash/flash_blob.c --stack-size 4096 python tools/generate_flash_algo.py \ MIMXRT1052_DFP/arm/MIMXRT105x_HYPER_256KB_SEC.FLM \ --pack-path ~NXP.MIMXRT1052_DFP.13.1.1.pack \ -o source/family/freescale/mimxrt1050_hyper_flash/flash_blob.c --stack-size 4096 --- .../mimxrt1050_hyper_flash/flash_blob.c | 955 +++++++++-------- .../mimxrt1050_spi_flash/flash_blob.c | 993 +++++++++--------- 2 files changed, 1012 insertions(+), 936 deletions(-) diff --git a/source/family/freescale/mimxrt1050_hyper_flash/flash_blob.c b/source/family/freescale/mimxrt1050_hyper_flash/flash_blob.c index 8fd6d3187..2beb8a6dc 100644 --- a/source/family/freescale/mimxrt1050_hyper_flash/flash_blob.c +++ b/source/family/freescale/mimxrt1050_hyper_flash/flash_blob.c @@ -1,449 +1,500 @@ -/** - * @file flash_blob.c - * @brief Flash algorithm for the i.MXRT1050 HyperFlash +/* Flash algorithm for MIMXRT105x 64mB Hyper Flash * * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2021 Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ -static const uint32_t RT1050_IS26KS512S_flash_prog_blob[] = { - 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, +// Generated from 'MIMXRT105x_HYPER_256KB_SEC.FLM' (MIMXRT105x 64mB Hyper Flash) +// Originating from 'NXP.MIMXRT1052_DFP.13.1.1.pack' +// digest = 363749d4cd82a6a7dfd79a347d446c1a71c80e1a384c2b72853989b7a47a12bc, file size = 2889020 +// algo version = 0x101, algo size = 15600 (0x3cf0) +static const uint32_t MIMXRT105x_HYPER_256KB_SEC_flash_prog_blob[] = { + 0xe7fdbe00, 0x4605b570, 0x4616460c, 0xcc0fe002, 0x3e10c50f, 0xd2fa2e10, 0xd3022e08, 0xc503cc03, 0x2e043e08, 0xcc01d307, 0x1f36c501, 0x7821e003, 0x1c647029, 0x1e761c6d, 0xbd70d2f9, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770bac0, 0x4770bac0, 0x4770bac0, - 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x2000b510, 0xf906f000, 0x46c046c0, 0xf0002001, - 0xbd10f8fb, 0xb5104603, 0x079b430b, 0x2a04d10f, 0xc808d30d, 0x1f12c910, 0xd0f842a3, 0xba21ba18, - 0xd9014288, 0xbd102001, 0x43c02000, 0x2a00bd10, 0x07d3d003, 0x1c52d003, 0x2000e007, 0x7803bd10, - 0x1c40780c, 0x1b1b1c49, 0x7803d107, 0x1c40780c, 0x1b1b1c49, 0x1e92d101, 0x4618d1f1, 0xe001bd10, - 0x1f09c004, 0xd2fb2904, 0xd501078b, 0x1c808002, 0xd00007c9, 0x47707002, 0xd00b2900, 0xd00207c3, - 0x1c407002, 0x29021e49, 0x0783d304, 0x8002d502, 0x1e891c80, 0x2200e7e3, 0x2200e7ee, 0x2200e7df, - 0x428b0903, 0x0a03d32c, 0xd311428b, 0x469c2300, 0x4603e04e, 0xd43c430b, 0x08432200, 0xd331428b, - 0x428b0903, 0x0a03d31c, 0xd301428b, 0xe03f4694, 0x428b09c3, 0x01cbd301, 0x41521ac0, 0x428b0983, - 0x018bd301, 0x41521ac0, 0x428b0943, 0x014bd301, 0x41521ac0, 0x428b0903, 0x010bd301, 0x41521ac0, - 0x428b08c3, 0x00cbd301, 0x41521ac0, 0x428b0883, 0x008bd301, 0x41521ac0, 0x428b0843, 0x004bd301, - 0x41521ac0, 0xd2001a41, 0x41524601, 0x47704610, 0x0fcae05d, 0x4249d000, 0xd3001003, 0x40534240, - 0x469c2200, 0x428b0903, 0x0a03d32d, 0xd312428b, 0x018922fc, 0x0a03ba12, 0xd30c428b, 0x11920189, - 0xd308428b, 0x11920189, 0xd304428b, 0xd03a0189, 0xe0001192, 0x09c30989, 0xd301428b, 0x1ac001cb, - 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152, 0xd301428b, 0x1ac0014b, 0x09034152, 0xd301428b, - 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb, 0x08834152, 0xd301428b, 0x1ac0008b, 0xd2d94152, - 0x428b0843, 0x004bd301, 0x41521ac0, 0xd2001a41, 0x46634601, 0x105b4152, 0xd3014610, 0x2b004240, - 0x4249d500, 0x46634770, 0xd300105b, 0xb5014240, 0x46c02000, 0xbd0246c0, 0x20184901, 0xe7febeab, - 0x00020026, 0xf000b510, 0xf000f80b, 0xbd10f802, 0xb5104770, 0xd0012800, 0xffeef7ff, 0x0000bd10, - 0x2100b510, 0xf000a002, 0x2001f813, 0x0000bd10, 0x41474953, 0x3a545242, 0x6e624120, 0x616d726f, - 0x6574206c, 0x6e696d72, 0x6f697461, 0x0000006e, 0x4605b570, 0x200a460c, 0x1c6de000, 0xf812f000, - 0xd0062d00, 0x28007828, 0xe002d1f7, 0xf0001c64, 0x2c00f809, 0x7820d002, 0xd1f72800, 0xf000200a, - 0xbd70f801, 0x4669b508, 0x20037008, 0xbd08beab, 0x06c00a02, 0x0ec0b510, 0xd9012a07, 0xfea8f7ff, - 0x00924b05, 0x681318d2, 0x40842403, 0x408143a3, 0x6013430b, 0x0000bd10, 0x400fc068, 0x4d08b570, - 0x444d2400, 0x04a24907, 0x20004449, 0xfcd3f001, 0x28006068, 0x1c64d102, 0xdbf32c04, 0x0000bd70, - 0x00000004, 0x0000005c, 0x49050102, 0x0912b510, 0x20004449, 0xfcbff001, 0x44494902, 0xbd106048, - 0x0000005c, 0x00000004, 0x2000b57c, 0x43c04914, 0x62c86288, 0x63486308, 0x63c86388, 0x31404910, - 0x49106008, 0x094068c8, 0x300e0140, 0xf00060c8, 0xf002fc9b, 0x480cfc37, 0x490c2500, 0x466a9000, - 0x95014449, 0xf0024628, 0x4c09f9a5, 0x444c4907, 0x44496060, 0xf0012000, 0x6060fce8, 0xbd7c7025, - 0x400fc040, 0x40080000, 0xe0233008, 0x0000005c, 0x00000004, 0xb5104805, 0x68414448, 0xd0032900, - 0xf0004803, 0xbd10f96f, 0xfe32f7ff, 0x0000025c, 0x40184000, 0xf7ffb510, 0xbd10ffed, 0xb5104805, - 0x68814448, 0xd0032900, 0xf0004803, 0xbd10f95b, 0xfe1ef7ff, 0x0000025c, 0x40188000, 0xf7ffb510, - 0xbd10ffed, 0xb5104805, 0x68c14448, 0xd0032900, 0xf0004803, 0xbd10f947, 0xfe0af7ff, 0x0000025c, - 0x4018c000, 0xf7ffb510, 0xbd10ffed, 0xb5104805, 0x69014448, 0xd0032900, 0xf0004803, 0xbd10f933, - 0xfdf6f7ff, 0x0000025c, 0x40190000, 0xf7ffb510, 0xbd10ffed, 0xb5104805, 0x69414448, 0xd0032900, - 0xf0004803, 0xbd10f91f, 0xfde2f7ff, 0x0000025c, 0x40194000, 0xf7ffb510, 0xbd10ffed, 0x460cb510, - 0x29006989, 0x2141d103, 0xf0000549, 0x2000f887, 0x20026120, 0x73603420, 0xb510bd10, 0x2103460c, - 0xf0000589, 0x2000f87b, 0x34206060, 0xbd107320, 0x460bb510, 0x079a6a81, 0x00890889, 0x430a0f92, - 0x69416282, 0x00490fda, 0x07d20849, 0x490b430a, 0x400a4c0a, 0x43e44619, 0x43114021, 0x03a42401, - 0x43a1461a, 0x430a4022, 0x43116941, 0xf0006141, 0x4018f8d1, 0x4802d000, 0x0000bd10, 0xbfe0ffff, - 0x0000051a, 0x461eb5f8, 0x000c4617, 0xd0264605, 0x46202130, 0xfde1f7ff, 0x46202102, 0x73413020, - 0x73012100, 0x62a66267, 0x21106ae8, 0x62e84388, 0xf0004628, 0x4a0bf871, 0x444a0081, 0x490a5054, - 0x44790040, 0x28005e08, 0x06c2db08, 0x21010ed2, 0x09404091, 0x00804a05, 0x60011880, 0xf7ffbdf8, - 0x0000fd67, 0x0000025c, 0x00002eb6, 0xe000e100, 0x6ac1b510, 0x0f490549, 0x6941d1fb, 0xd5fc0249, - 0x61812100, 0xf848f000, 0x00404903, 0x5e084479, 0xf7ff2100, 0xbd10fe9d, 0x00002e7e, 0x23c06902, - 0x021b400b, 0x6102439a, 0x078b6a82, 0x439a0d9b, 0x0a096282, 0x02096982, 0x6182438a, 0x69024770, - 0x400b23c0, 0x431a021b, 0x6a826102, 0x0d9b078b, 0x6282431a, 0x69820a09, 0x430a0209, 0x47706182, - 0x2800b510, 0x21e1d00a, 0x60010249, 0x71012100, 0x71817141, 0x720171c1, 0xbd107241, 0xfd18f7ff, - 0x22c06901, 0x40110a09, 0x69806a82, 0x0f920592, 0x4310430a, 0x00004770, 0xb5104a08, 0x20004601, - 0x0083447a, 0x428b58d3, 0x1c40d003, 0xd3f82808, 0x2808e001, 0xf7ffd301, 0xbd10fcfb, 0x00002db4, - 0x5c40202d, 0xd0072802, 0xd0072a00, 0x69096948, 0x60101a40, 0x47702000, 0x47702006, 0x47702004, - 0x8c0a8c48, 0x8c084290, 0x69cad901, 0x8c491880, 0x47701a40, 0x5c40202c, 0xd0072800, 0xd0072a00, - 0x68496888, 0x60101a40, 0x47702000, 0x47702006, 0x47702004, 0x6a806941, 0x0c0022c3, 0x43084010, - 0x47704770, 0x4605b5f8, 0x460c6940, 0xd50d0300, 0x466969e8, 0x78087008, 0x70081c40, 0x2e006a66, - 0x4a5ed004, 0x46284621, 0x47b06aa3, 0x02816968, 0x30204620, 0x29009000, 0x69a8da71, 0xd56e0280, - 0x01406ae8, 0xe0260f46, 0x42b06920, 0x6920d201, 0x4630e000, 0xb2c168e2, 0xe0022000, 0x541369eb, - 0x460b1c40, 0xd3f94288, 0x184068e0, 0x692060e0, 0x61201a40, 0xb2c61af0, 0x28006920, 0x9800d10b, - 0x73412102, 0x2f006a67, 0x4a44d005, 0x1f924621, 0x6aa34628, 0x2e0047b8, 0x6920d002, 0xd1d32800, - 0x280069a0, 0xe032d12d, 0x46284621, 0xf926f000, 0xd0082800, 0x2f006a67, 0x4a38d005, 0x1e524621, - 0x6aa34628, 0x462147b8, 0xf0004628, 0x2800f917, 0x8c60d009, 0x1c4069e1, 0xd1014288, 0xe0012000, - 0x1c408c60, 0x69e88460, 0x69a18c22, 0x8c205488, 0x1c4069e1, 0xd1014288, 0xe0012000, 0x1c408c20, - 0x46308420, 0xb2f61e76, 0xd1cd2800, 0x6920e007, 0xd1042800, 0x05492141, 0xf7ff4628, 0x6968feef, - 0xd5390200, 0x020069a8, 0x6ae8d536, 0x05402104, 0x1a080f40, 0xe02ab2c6, 0x42b06860, 0x6860d201, - 0x4630e000, 0xb2c16822, 0xe0022000, 0x61eb5c13, 0x460b1c40, 0xd3f94288, 0x18406820, 0x68606020, - 0x60601a40, 0xb2c61af0, 0x28006860, 0x9900d10f, 0x69a87308, 0x05c92101, 0x61a84388, 0x2f006a67, - 0x4a06d005, 0x1fd24621, 0x6aa34628, 0x2e0047b8, 0x6860d002, 0xd1cf2800, 0x0000bdf8, 0x0000051d, - 0xb086b5f7, 0x4604000f, 0x6838d009, 0x28009005, 0x79b8d005, 0xd8022804, 0x280479f8, 0xf7ffd901, - 0x9805fbe7, 0x20009000, 0x25049001, 0x99059002, 0x43699808, 0xfc33f7ff, 0x0c360406, 0x2601d100, - 0x43714629, 0xf7ff9808, 0x9905fc2a, 0x1c701a41, 0x46299103, 0x43419004, 0xf7ff9808, 0x9905fc20, - 0x99031a08, 0xd2024288, 0x98049003, 0x9900b286, 0x42889803, 0x4669d801, 0x1c6dc161, 0xd9d62d20, - 0x98052164, 0xfc0bf7ff, 0x18410041, 0x42819800, 0x4830d202, 0xbdf0b009, 0xf7ff4620, 0x0041fe9d, - 0x4478482d, 0x21035e40, 0xfcf2f7ff, 0x210369a0, 0x43880489, 0x692061a0, 0x1f099901, 0xd2022904, - 0x04492101, 0x211f4308, 0x43880609, 0x1e499901, 0x08c906c9, 0x0b484301, 0x03409902, 0x0cc904c9, - 0x61214301, 0x21016920, 0x43880749, 0x69a06120, 0x43882110, 0x69a061a0, 0x00800880, 0x69a061a0, - 0x43087939, 0x692061a0, 0x03492101, 0x79794388, 0x0c8907c9, 0x61214301, 0x79b979f8, 0x43080400, - 0x6aa062e0, 0x43082188, 0x6aa062a0, 0x03892103, 0x62a04308, 0x7a3969a0, 0xd0022900, 0x04c92101, - 0x7a794308, 0xd0022900, 0x04892101, 0x61a04308, 0xe79f2000, 0x00000521, 0x00002b28, 0x460cb510, - 0xfe5ef7ff, 0x1e4969e1, 0xd1014288, 0xbd102001, 0xbd102000, 0x6ac3e006, 0x0f5b015b, 0x69c3d0fb, - 0x1c49700b, 0xd2f61e52, 0x00004770, 0x460cb5ff, 0x3120b083, 0x7b499100, 0x29034617, 0x69a1d013, - 0x687d2600, 0xd0322900, 0x8110f3ef, 0xb6729101, 0xf7ff4621, 0x2800fe35, 0x4285d01b, 0x4628d200, - 0x21001a2d, 0x481ae013, 0xbdf0b007, 0x69a28c63, 0x683b5cd2, 0x8c62559a, 0x1c5269e3, 0x429a1c76, - 0x2200d101, 0x8c62e001, 0x84621c52, 0x42811c49, 0x2d00d3ec, 0x6838d007, 0x60e01980, 0x61656125, - 0x21039800, 0x98017341, 0x8810f380, 0x6811e00a, 0x612560e1, 0x9a006165, 0x73512103, 0x05492141, - 0xfdadf7ff, 0x28009806, 0x6006d000, 0xe7cb2000, 0x00000515, 0x460bb510, 0x7b1c3320, 0xd00c2c01, - 0x600c6814, 0x604c6854, 0x608a6852, 0x73192101, 0xf7ff05c9, 0x2000fd94, 0x4801bd10, 0x0000bd10, - 0x00000514, 0xb084b5f7, 0xd00d000f, 0x90012000, 0x97002404, 0x46399002, 0x98064361, 0xfb0ff7ff, - 0x0c2d0405, 0xe002d002, 0xfab2f7ff, 0x46212501, 0x98064369, 0xfb03f7ff, 0x1c681bc6, 0x43414621, - 0x98069003, 0xfafbf7ff, 0x42b01a38, 0x4606d202, 0xb2859803, 0x42869800, 0x9600d802, 0x94019502, - 0x2c201c64, 0x2164d9d7, 0xf7ff4638, 0x0041fae8, 0x98001841, 0xd9254281, 0x69819804, 0x22036980, - 0x43900492, 0x61909a04, 0x69009804, 0x1f129a01, 0xd2022a04, 0x04522201, 0x221f4310, 0x43900612, - 0x1e529a01, 0x08d206d2, 0x0b504302, 0x03409a02, 0x0cd204d2, 0x98044302, 0x98046102, 0x20006181, - 0xbdf0b007, 0xe7fb4800, 0x00000521, 0x2900b510, 0x2a00d00b, 0x61cbd008, 0x2200618a, 0x844a840a, - 0x05492141, 0xfd1bf7ff, 0xf7ffbd10, 0xb510fa51, 0xd004000c, 0x5d09212d, 0xd0022902, 0xf7ffe005, - 0x2141fa47, 0xf7ff0549, 0x2000fcf9, 0x61e061a0, 0x84608420, 0xe005bd10, 0x021b6943, 0x780bd5fc, - 0x1c4961c3, 0xd2f71e52, 0x00004770, 0x4d18b570, 0x46160104, 0x444d0924, 0x2001d007, 0x42840340, - 0x7828d11d, 0xd0072800, 0x4912e019, 0x42886830, 0x2001d115, 0xe0127028, 0x22004b0f, 0x4619444b, - 0xf0014610, 0x4b0af8da, 0x444b490b, 0x60682201, 0x03123308, 0x20004449, 0xf8cff001, 0x49066068, - 0x46224633, 0x20004449, 0xf8c7f001, 0xbd706068, 0x00000004, 0x42464346, 0x0000005c, 0x47702000, - 0x4613b570, 0x460a460d, 0x46014604, 0xf7ff4618, 0x2800f9f9, 0x2000d001, 0x1960bd70, 0xb5f8bd70, - 0xb28b0c04, 0xb2824626, 0x0c0d435e, 0x0c374610, 0x04364358, 0x21001980, 0x46164179, 0x0c37436e, - 0x19800436, 0x46264179, 0x1989436e, 0xb430bdf8, 0x1e644674, 0x1c647825, 0xd20042ab, 0x5d63461d, - 0x18e3005b, 0x4718bc30, 0x494db5f8, 0x24016b08, 0x0f800240, 0x6a084084, 0x07404d4a, 0x68280fc2, - 0x03c14f4a, 0xd57d4848, 0xd0012a00, 0xe0002158, 0x23092142, 0x18c9035b, 0x68296029, 0xdafc2900, - 0x23016b29, 0x4399031b, 0x6b296329, 0xdafc2900, 0x6809493f, 0x23034e3f, 0x02db4031, 0x4b3e18c9, - 0x4b3b4319, 0x21036019, 0x61290309, 0x29006929, 0x6929dafc, 0x041b2301, 0x61294399, 0x3b404b34, - 0x40316b19, 0x02362623, 0x4e341989, 0x63194331, 0x21014e33, 0x2a006131, 0x4638d000, 0xf7ff4621, - 0x4930f9ce, 0x44492701, 0x90006008, 0x1c7fe000, 0x98004639, 0xf9c3f7ff, 0x4288492b, 0x6970d8f7, - 0x2207492a, 0x1e794008, 0x0b490749, 0x02a14308, 0x18890292, 0x0cc904c9, 0x02394308, 0x390139ff, - 0x0d890589, 0x61704308, 0x09c06a70, 0x1cc001c0, 0x69b06270, 0x04892103, 0x61b04308, 0x491c69f0, - 0x21034008, 0x18400749, 0x4308491a, 0x682961f0, 0x04002001, 0x60294381, 0x43816b29, 0x69296329, - 0xe0004381, 0x6129e001, 0x2a00bdf8, 0x4638d000, 0xf7ff4621, 0x490bf984, 0x60084449, 0x0000bdf8, - 0x401f4440, 0x400d8000, 0x179a7b00, 0x1f78a400, 0x400d8100, 0xc0c0c0c0, 0x18131818, 0x0f1a2323, - 0x400fc000, 0x0000004c, 0x08954400, 0xfff8e0ff, 0x9c7fff80, 0x03800001, 0x4614b5f8, 0x4607000d, - 0x2c01d024, 0x6c28d822, 0x0fc60640, 0xf0014638, 0x4621fde3, 0x34ff462c, 0x290034c1, 0x7a20d017, - 0xd0092800, 0x5d412046, 0x46384632, 0xf83af000, 0x46384629, 0xfa4ef000, 0x28007ba0, 0x2100d003, - 0xf0004638, 0x4638fca5, 0xf811f000, 0x7a21bdf8, 0xd0072900, 0x46384632, 0xf824f000, 0x46384629, - 0xfa38f000, 0x28007ba0, 0x2101d0ed, 0xb510e7e8, 0xfc66f000, 0xd0012800, 0xfd6ff001, 0xb510bd10, - 0xfc5ef000, 0xd00b2800, 0x23012100, 0x008a07db, 0x32801812, 0x431c6814, 0x1c496014, 0xd3f62904, - 0x0000bd10, 0x460cb5f0, 0xb08b4922, 0x46064615, 0x44792214, 0xf7ff4668, 0x491ef873, 0x44792214, - 0xa8053108, 0xf86cf7ff, 0xd0012d00, 0xd12c2d01, 0x6b184b19, 0x09814f19, 0x018969f8, 0x05d22207, - 0x2d004390, 0xaa05d023, 0xd01e2c00, 0xd9002c09, 0x00642401, 0x18a25d15, 0x785206ac, 0x430c0ea4, - 0x220705d1, 0x188905d2, 0x09ad018d, 0x46304305, 0xf816f000, 0x42a06b18, 0x631cd000, 0x42a869f8, - 0x61fdd000, 0xf0004630, 0xb00bf815, 0x466abdf0, 0x0000e7da, 0x00002416, 0x400d80c0, 0x400fc000, - 0x68014803, 0x02922203, 0x60014391, 0x00004770, 0x400fc080, 0x68014803, 0x02922203, 0x60014311, - 0x00004770, 0x400fc080, 0x4605b5fe, 0x90002004, 0x4628460e, 0xfbe4f000, 0xd07d0004, 0xd0fc2e00, - 0x28037830, 0x7c30d878, 0x27009001, 0xf0014620, 0x4628fd2d, 0xff73f7ff, 0x211e6960, 0x61604308, - 0x35804625, 0x62286870, 0x28027830, 0x2803d002, 0xe003d002, 0xe0008b30, 0xb2878c30, 0x7a307b31, - 0x07001e49, 0x0b000749, 0x43080949, 0x07c99901, 0x43384308, 0x78306268, 0xd1502803, 0x6a3069f1, - 0xd149078b, 0x469e2340, 0x221c6bab, 0x43bb273c, 0x63aa431a, 0x22016bab, 0x63ab4313, 0x07db6bab, - 0x6b2bd1fc, 0x632b4313, 0x1de2e035, 0x32f94673, 0x4570089b, 0x6967d30a, 0xd40206bf, 0xca80e028, - 0x1e5bc180, 0x4672d2fb, 0xe01d1a80, 0x061b6f2b, 0xd1030e1b, 0xca08e01c, 0xc1081f00, 0xd2fa2804, - 0xd0102800, 0x92016812, 0x4694aa01, 0x2300460a, 0x4667e007, 0x7017783f, 0x1c7f4667, 0x46bc1c52, - 0x42831c5b, 0x2000d3f5, 0x23206962, 0x6162431a, 0x07126962, 0xe000d403, 0x2800e05f, 0x7830d1c5, - 0xd0012802, 0xd1412801, 0x69b26971, 0xd1540788, 0x46842040, 0x201c6beb, 0x43bb273c, 0x63e84318, - 0x20016beb, 0x63eb4303, 0x07db6beb, 0x6b2bd1fc, 0x632b4303, 0x4620e028, 0x696330ff, 0x065b3081, - 0x4663d51f, 0x4562089b, 0xe014d202, 0xc080c980, 0xd2fb1e5b, 0x1a124660, 0x2a04e00f, 0xc980d903, - 0x1f12c080, 0x2a00e007, 0xc980d003, 0xc0802200, 0x2700e001, 0x1e5bc080, 0x6960d2ef, 0x43182340, - 0x69606160, 0xd4010700, 0xd1d42a00, 0x28007830, 0x6b28d103, 0x43082101, 0x46206328, 0xfc66f001, - 0x07006960, 0x6e68d50b, 0x0f000100, 0xd001280e, 0xe0014804, 0x1e404803, 0x98009000, 0x2000bdfe, - 0x0000e7fa, 0x00001771, 0xb5104602, 0x2a002004, 0x2900d021, 0x2044d01f, 0x28015c40, 0x68d0d10c, - 0x005b0843, 0x43032040, 0xf0004608, 0x2800fcd3, 0x2001d001, 0x60d34303, 0x212068d0, 0x60d04308, - 0x20004b05, 0x18890081, 0x401c6a0c, 0x1c40620c, 0xd3f72803, 0xbd102000, 0xfcf0ff00, 0xb087b5f3, - 0x2504460c, 0xf0009807, 0x9002facb, 0xd0542800, 0xd0522c00, 0x30404620, 0x90054627, 0x26003750, - 0x304130ff, 0x68389001, 0x0a8100b2, 0x18109802, 0x66019000, 0x1d3f7ba0, 0x7b6006c5, 0x06c00eed, - 0x43050d80, 0x07007be0, 0x43050c40, 0xf0004620, 0x2800fc98, 0x2001d002, 0x43050280, 0x28006f60, - 0xaa03d00d, 0x98072101, 0xfa60f000, 0x6f612301, 0x9a03a804, 0xfa9ef000, 0x04009804, 0x98004305, - 0x98056705, 0x280079c0, 0x9801d00e, 0x07417c00, 0x9901d00a, 0x7c490342, 0x07092007, 0x03400d09, - 0xb2801810, 0xe0014308, 0x02002009, 0x31809900, 0x1c766008, 0xd3b62e04, 0x46282500, 0xbdf0b009, - 0x460db57f, 0xf0004606, 0x0004fa6b, 0x2d00d02c, 0xaa02d02a, 0x46302101, 0xfa28f000, 0x2100aa03, - 0xf0004630, 0x2501fa23, 0x02ad4e10, 0x4631462b, 0x9a024668, 0xfa5ef000, 0x4631462b, 0x9a03a801, - 0xfa58f000, 0x9900480a, 0xd9004281, 0x99019000, 0xd9004281, 0x98009001, 0x04009901, 0x4308b289, - 0x20006060, 0xbd70b004, 0xe7fb2004, 0x1dcd6500, 0x0000ffff, 0xb085b5f3, 0x2404460e, 0xf0009805, - 0x0005fa2f, 0x2e00d07e, 0x7b30d07e, 0xd87b2803, 0xd00a2800, 0xd0082801, 0xd0062802, 0xd1042803, - 0xf0004630, 0x2800fbed, 0x20ffd002, 0xe0093001, 0x2101aa03, 0xf0009805, 0x4935f9d9, 0x42889803, - 0x2079d303, 0x90019000, 0x2400e01e, 0x19800060, 0x8f073040, 0x43472064, 0x214bd01d, 0xf7fe4638, - 0x214bfebe, 0x42b94341, 0x1c40d200, 0x283f213f, 0x4608d900, 0x0c410680, 0x31ff00a2, 0x46683101, - 0x50811c64, 0xd3e12c02, 0x22026828, 0x28000780, 0x2000da1c, 0x4630e01e, 0xfbb9f000, 0x46024607, - 0x9805a902, 0xf9d0f000, 0x9902481a, 0xd0092f00, 0xfe95f7fe, 0x217d0880, 0x434800c9, 0xf7fe214b, - 0xe7d2fe8e, 0xfe8bf7fe, 0xe7f40840, 0x20016829, 0x60294311, 0x29006d31, 0x6d71d102, 0xd0022900, - 0x9b0021c0, 0x6db1514b, 0xd1022900, 0x29006df1, 0x21c4d002, 0x514b9b01, 0xd0022800, 0x43906828, - 0xe0006028, 0x2400e000, 0xb0074620, 0x0000bdf0, 0x05f5e100, 0x3b9aca00, 0xb08ab5f7, 0x2604460d, - 0xf000980a, 0x0007f99d, 0x2d00d053, 0x2001d051, 0x70084669, 0x9001980c, 0x74082000, 0x24002004, - 0x00a09006, 0x46101942, 0x78413020, 0xd03d2900, 0x025b2301, 0x059b59db, 0xd0030f9b, 0x7f5b192b, - 0xd0332b02, 0x78009102, 0x92053230, 0x22009003, 0x9b0c4629, 0xf000980a, 0x2800f90c, 0x9802d12a, - 0x01002101, 0x32801942, 0x980a9b03, 0xfa82f001, 0x90022001, 0x980a4669, 0xfd76f7ff, 0xd1190006, - 0x28008a68, 0x1929d10e, 0x29027f49, 0x2903d00a, 0x2200d008, 0x9b0c4629, 0xf000980a, 0x0006f80d, - 0xe003d108, 0x43482164, 0xfb4cf001, 0x2c031c64, 0x4630d3b7, 0xbdf0b00d, 0x2004b5ff, 0x460cb08f, - 0xd04b2900, 0x900e2000, 0x30404620, 0x21018f82, 0x4095460d, 0x93028fc2, 0x22039200, 0x711a466b, - 0x91039104, 0x9108a90c, 0x29009911, 0x2108d001, 0x2104e000, 0x99119109, 0x79c07519, 0xd0092800, - 0x30ff4620, 0x79013081, 0xd0032900, 0x91037941, 0x90047900, 0x21029803, 0x19020100, 0x9b043280, - 0xf001980f, 0x2002fa27, 0x6f209003, 0xd0022800, 0xfb3ef001, 0x6f20900e, 0xd0112800, 0xfb38f001, - 0x1a40990e, 0xfaf4f001, 0x6f23217d, 0x434b00c9, 0x46112200, 0x41911a18, 0x481ad202, 0xbdf0b013, - 0x980fa901, 0xfd00f7ff, 0xd1f72800, 0x29009911, 0xa90ad019, 0xaa0cab0b, 0x78172608, 0x7857700f, - 0x1c49701f, 0x1c5b1c92, 0xd1f61eb6, 0x9a0b9900, 0x990a2900, 0x4011d005, 0x438a462a, 0x2100d10e, - 0x4311e00d, 0x9900e007, 0xd0032900, 0x46299a0c, 0xe0014391, 0x4029990c, 0xd0002900, 0x29002101, - 0xe7cbd1b9, 0x00001772, 0xb089b5f0, 0x460c4616, 0x25044607, 0xf8b4f000, 0xd0472800, 0xd0452c00, - 0x30ff30ff, 0x68003002, 0x0f800580, 0x7c60d002, 0xd0252802, 0x46692501, 0x9601700d, 0x90027d60, - 0x90037d20, 0x74082000, 0x30184620, 0x20049005, 0x46339006, 0x46212200, 0xf0004638, 0x9802f82a, - 0x01002101, 0x46381902, 0x9b033280, 0xf9a2f001, 0x46384669, 0xf7ff9502, 0x0005fc97, 0xe001d116, - 0xe0132500, 0x29008a61, 0x7c60d10c, 0xd0092802, 0xd0072803, 0x22004633, 0x46384621, 0xff2cf7ff, - 0xe0034605, 0x43482064, 0xfa6cf001, 0xb0094628, 0xb570bdf0, 0x20044604, 0x2900b08a, 0x2000d024, - 0x7030466e, 0x25012003, 0x95039002, 0x20477432, 0x5c409301, 0xd0092800, 0x30ff4608, 0x7a023081, - 0xd0032a00, 0x92027a42, 0x90037a00, 0x9b039802, 0x18420100, 0x46202101, 0xf0013280, 0x4669f95b, - 0x95024620, 0xfc50f7ff, 0xbd70b00a, 0x4616b570, 0x20004a11, 0x6812444a, 0x46044d10, 0xd0052900, - 0xd0082901, 0x60302404, 0xbd704620, 0x05806968, 0x46100f81, 0x69e8e00c, 0x6b004809, 0x0e890681, - 0xf7fe4808, 0x2112fcdc, 0x69e94348, 0x0f490189, 0xf7fe1c49, 0xe7e6fcd4, 0x0000004c, 0x400fc000, - 0x400d80c0, 0x1c9c3800, 0x20044603, 0xd1042b01, 0xd0022900, 0x60084801, 0x47702000, 0x09e4f580, - 0x20004601, 0xd1022900, 0x44784801, 0x47706800, 0x00001ba6, 0x4607b5f8, 0x461d2004, 0x2f00460e, - 0x4611d012, 0xf7fe4809, 0x4601fcaa, 0x43694604, 0xf7fe4630, 0xe000fca4, 0x46011c40, 0x43694361, - 0xd3f942b1, 0x20006038, 0x0000bdf8, 0x3b9aca00, 0x460db570, 0xffd4f7ff, 0xd00a0004, 0xf926f001, - 0x02c02001, 0x2d006821, 0x4301d001, 0x4381e000, 0xbd706021, 0xb087b5f3, 0x2604460d, 0xf7ff9807, - 0x0004ffbf, 0x2d00d07e, 0x7c28d0fc, 0xd1022800, 0x28007f28, 0x6c28d009, 0xd40406c0, 0xf0004628, - 0x2800f986, 0x2001d001, 0x2000e000, 0x49619003, 0x42886828, 0x9807d166, 0xfba2f7ff, 0x98074629, - 0xf8bef000, 0x30404628, 0x90029903, 0xd0022900, 0x21012200, 0x4628e005, 0xf969f000, 0x98024602, - 0x98077981, 0xfb3ef7ff, 0xf7ff9807, 0x6820fb93, 0x43b02602, 0x46206020, 0xf88ff001, 0x43306820, - 0x68206020, 0x4008494c, 0x79499902, 0xd1012908, 0x43080289, 0x43084949, 0x07897b29, 0x43010e89, - 0x46296021, 0xf7ff9807, 0x68a0fcfb, 0x03c92101, 0x60a04388, 0xf0004628, 0x2800f941, 0x68a0d004, - 0x04c92101, 0x60a04308, 0x46204629, 0xfc5cf7ff, 0x98074629, 0xfc82f7ff, 0x98074629, 0xfd1af7ff, - 0x21026820, 0x60204388, 0xf0014620, 0x4628f856, 0x30507c29, 0x29009004, 0x9807d01c, 0x20049005, - 0xe0002100, 0x9e04e052, 0x460f9100, 0x9101ce02, 0xd00a2900, 0x9a004629, 0xf7ff9805, 0x2800fe75, - 0x9a01d106, 0x18899900, 0x1c7f9100, 0xd3ed2f04, 0xd13b0006, 0x28007f28, 0x9807d01c, 0x20049005, - 0xd0152d00, 0x9e042100, 0x460f9100, 0x9101ce02, 0xd00a2900, 0x9a004629, 0xf7ff9805, 0x2800fd6d, - 0x9a01d106, 0x18899900, 0x1c7f9100, 0xd3ed2f04, 0xd11b0006, 0x28009803, 0x6820d017, 0x43302602, - 0x46286020, 0xf8d3f000, 0x98024602, 0x98077981, 0xfaa8f7ff, 0x98074629, 0xfc82f7ff, 0x98074629, - 0xfcb8f7ff, 0x43b06820, 0x26006020, 0xb0094630, 0x0000bdf0, 0x42464346, 0x0000df0f, 0xffff0000, - 0x4d53b5fe, 0x462e4853, 0x460c9001, 0x46084637, 0xf8b9f000, 0xd0042800, 0x6ee06e26, 0x6e679001, - 0x46206ea5, 0x6d213040, 0x6d609000, 0xd0232900, 0xd0042800, 0x20064948, 0x484863c8, 0x6d2062c6, - 0xd0062800, 0x20014944, 0x62c83140, 0x30404843, 0x484161c6, 0x30402311, 0x49406303, 0x620f3140, - 0x63422201, 0x6382624d, 0x9800628d, 0x28047940, 0x2808d005, 0xe01bd003, 0xd1db2800, 0x4936e030, - 0x31402001, 0x493563c8, 0x62cd3140, 0x32804a32, 0x630d6010, 0x79529a00, 0xd1092a08, 0x32404a2e, - 0x610d6210, 0x60cd61d0, 0x608d6190, 0x604d6150, 0x28037b20, 0x2801d001, 0x4827d106, 0x62833040, - 0x98014926, 0x61883140, 0xf0004620, 0x2800f857, 0x4921d006, 0x31402001, 0x48206248, 0x61473040, - 0x28006da0, 0xd0216de0, 0xd0052800, 0x2006491a, 0x60083140, 0x63064819, 0x28006da0, 0x4816d005, - 0x30402104, 0x481560c1, 0x491363c6, 0x31402011, 0x4a126248, 0x61573240, 0x62082001, 0x61c86115, - 0x9b0060d5, 0x2b04795b, 0xe006d003, 0xd1dd2800, 0x6188bdfe, 0x61486095, 0x7b206055, 0xd0012803, - 0xd1f52801, 0x61082014, 0x60109801, 0x0000bdfe, 0x000010f1, 0x000130f1, 0x401f8180, 0x401f8380, - 0x07806c00, 0x2001d501, 0x20004770, 0x6c004770, 0xd5010640, 0x47702001, 0x47702000, 0x07c06c00, - 0x2001d000, 0x6c004770, 0xd5010680, 0x47702001, 0x47702000, 0x07406c00, 0x2001d501, 0x20004770, - 0x6c004770, 0xd5010700, 0x47702001, 0x47702000, 0xb08ab570, 0x20004605, 0x7030466e, 0x2401200f, - 0x94039002, 0x460a7432, 0x930132ff, 0x46233271, 0x46284621, 0xff0ef000, 0x46284669, 0xf7ff9402, - 0xb00afa03, 0xb5ffbd70, 0xb0812004, 0x2900460f, 0x463dd016, 0x358135ff, 0x46146c6e, 0x18b21e71, - 0x438c1e5b, 0x438e18d6, 0x4622e008, 0x98014639, 0xf881f000, 0xd1032800, 0x190c6c69, 0xd3f442b4, - 0xbdf0b005, 0xb08bb5f3, 0x46692000, 0x70089d0c, 0x91032101, 0x9102210b, 0x74084669, 0x5d402047, - 0xd0092800, 0x30ff4628, 0x7d013081, 0xd0032900, 0x91027d41, 0x90037d00, 0x990c2200, 0xf7ff980b, - 0x2600f90b, 0x46373550, 0xcd01950a, 0x28009009, 0x4633d01a, 0x990c2200, 0xf000980b, 0x0004fe86, - 0x9802d13e, 0x01019601, 0x9b03980c, 0x2101180a, 0x980b3280, 0xfeaef000, 0x90022001, 0x980b4669, - 0xf9a2f7ff, 0xd12b0004, 0x1c7f9809, 0x2f041836, 0x2c00d3db, 0x2000d124, 0x46069009, 0x9d0a980c, - 0x30c130ff, 0xcd80900a, 0xd0132f00, 0x9b092200, 0x980b990c, 0xfc30f7ff, 0xd1110004, 0x7bc0980a, - 0xd0072800, 0x9b092200, 0x980b990c, 0xfe2cf000, 0xd1050004, 0x1c769809, 0x900919c0, 0xd3e22e04, - 0xf7ff980b, 0x2201f8f4, 0x980b990c, 0xf8b4f7ff, 0xb00d4620, 0xb5f7bdf0, 0x4617b08a, 0x4608460d, - 0xff38f7ff, 0x22004606, 0x980a4629, 0xf8a4f7ff, 0x4632463b, 0x980a4629, 0xfe27f000, 0xd1390004, - 0x97014669, 0x20057008, 0x90022401, 0x740e9403, 0x5d402047, 0xd0092800, 0x30ff4628, 0x7b013081, - 0xd0032900, 0x91027b41, 0x90037b00, 0x21019802, 0x19420100, 0x9b033280, 0xf000980a, 0x4669fe3b, - 0x980a9402, 0xf930f7ff, 0xd1130004, 0x4632463b, 0x980a4629, 0xfbd0f7ff, 0xd10b0004, 0x30d020ff, - 0x28005d40, 0x463bd006, 0x46294632, 0xf000980a, 0x4604fdcb, 0xf7ff980a, 0x2201f89a, 0x980a4629, - 0xf85af7ff, 0xb00d4620, 0xb5f8bdf0, 0x4607460d, 0xfd30f7ff, 0xd11e0006, 0x3280462a, 0x46142301, - 0x46382100, 0xfe06f000, 0x30cd20ff, 0x28025d40, 0x7c68d003, 0xd00c2801, 0x4620e00d, 0xc80f3020, - 0x35104625, 0x4620c50f, 0xc80f3040, 0xc40f3430, 0x2000e001, 0x46307428, 0xb5ffbdf8, 0x4617b089, - 0x4608460d, 0xfeb6f7ff, 0x22004606, 0x98094629, 0xf822f7ff, 0x4632463b, 0x98094629, 0xfda5f000, - 0xd13f0004, 0x46692002, 0x20097008, 0x90022401, 0x20479403, 0x46285d41, 0x308130ff, 0xd0062900, - 0x29007c01, 0x7c41d003, 0x7c019102, 0x46699103, 0x740e9701, 0x9105990c, 0x90066c00, 0x21019802, - 0x19420100, 0x9b033280, 0xf0009809, 0x4669fdb3, 0x98099402, 0xf8a8f7ff, 0xd1130004, 0x4632463b, - 0x98094629, 0xfb48f7ff, 0xd10b0004, 0x30d020ff, 0x28005d40, 0x463bd006, 0x46294632, 0xf0009809, - 0x4604fd43, 0xf7ff9809, 0x2201f812, 0x98094629, 0xffd2f7fe, 0xb00d4620, 0x0000bdf0, 0xb089b5ff, - 0x9c122004, 0x4616461f, 0xd0222900, 0xd0202e00, 0xd01e2c00, 0xf7ff4608, 0x2103fe4d, 0x7011466a, - 0x91032101, 0x91022100, 0x4d0b7410, 0xd80042ac, 0x46694625, 0x96079701, 0x98099508, 0xf864f7ff, - 0xd1062800, 0x008908a9, 0x197f1b64, 0x2c00198e, 0xb00dd1eb, 0x0000bdf0, 0x0000ffff, 0x460cb5f7, - 0xb0a64958, 0x4f564615, 0x44792240, 0xf7fea815, 0x2000f867, 0x46269000, 0x36402004, 0x68287170, - 0x0f010300, 0x0f00d005, 0xd0062802, 0xd0092803, 0x2010e093, 0x20006420, 0x2050e002, 0x20036420, - 0xe0077320, 0x64202050, 0x73202003, 0x71702008, 0x90002001, 0x98264621, 0xff17f7ff, 0xd17c0007, - 0xa9156828, 0x0f000300, 0x18420100, 0x46192301, 0xf0009826, 0xa901fd1f, 0x98269a00, 0xfc54f000, - 0xd16a0007, 0xa901aa25, 0xf0004620, 0x2050fd77, 0x20036420, 0x46207320, 0x30804933, 0x49336301, - 0x88296101, 0x04092302, 0x1de10f0a, 0x2a0231f9, 0x2a03d002, 0xe050d027, 0x71722204, 0x0312682a, - 0xd10d0f12, 0x04922221, 0x4a2961a2, 0x4a296602, 0x22016642, 0x74637422, 0x75652506, 0x82627522, - 0x60024a25, 0x60424a25, 0x64024a25, 0x32154a22, 0x22336502, 0x630a0152, 0x3a094a1f, 0x4a21610a, - 0x4921614a, 0x2208e025, 0x682a7172, 0x0f120312, 0x2211d10d, 0x61a204d2, 0x66024a15, 0x66424a15, - 0x74222201, 0x25067463, 0x75227565, 0x4a178262, 0x4a176002, 0x4a176042, 0x4a146402, 0x65023215, - 0x0152223b, 0x4a11630a, 0x610a3a09, 0x614a4a12, 0x34ff4912, 0x620134c1, 0x46387323, 0xbdf0b029, - 0x00004e8d, 0x000014aa, 0x00000406, 0x24040405, 0x04000471, 0x00002003, 0x8a20060b, 0x0000a604, - 0x00000606, 0x0000a280, 0xa6040605, 0x8b20070b, 0x0000a704, 0x00000706, 0x0000a380, 0xa7040705, - 0x460fb5f7, 0x2103b088, 0x73f94638, 0x30402308, 0x23587143, 0x2401643b, 0x2a007339, 0x2159d001, - 0x71c46439, 0x8781210f, 0x463e87c4, 0x36ff2001, 0x36810240, 0x02406430, 0x46396470, 0xf7ff9808, - 0x2800fe54, 0x4862d139, 0x90002500, 0x95034861, 0x90012301, 0x466a9502, 0x98084619, 0xfc5af000, - 0x95039502, 0x485c4d5a, 0x90013580, 0x466a2301, 0x95002100, 0xf0009808, 0x2013fc4d, 0x900602c0, - 0xaa062302, 0x98084955, 0xfb50f000, 0xd1142800, 0xaa042308, 0x98082110, 0xfb34f000, 0xd10c2800, - 0x494f9805, 0x9005b280, 0x42889804, 0x2159d104, 0x02099805, 0xd0024288, 0xb00b484a, 0x2308bdf0, - 0x2127aa04, 0xf0009808, 0x2800fb1d, 0x9804d1f5, 0x0e000400, 0x38179004, 0xd8ed2809, 0x20019904, - 0x65384088, 0x0300200f, 0x23029006, 0x2100aa06, 0xf0009808, 0x2800fb1b, 0x463cd1df, 0x49363480, - 0x60616025, 0x4a394938, 0x34104b39, 0x4b39c40e, 0x60236065, 0x60a34b38, 0x60e34b38, 0x34144b34, - 0x4b37c40e, 0x602260a3, 0x4b366061, 0x4b3460e3, 0x61234625, 0x4b2e3554, 0x4b33c50e, 0x4b24602b, - 0x3b203414, 0x4b31606b, 0x4b2960ab, 0x4b30c40e, 0xc4083d1c, 0xc40e4b26, 0x60a34b29, 0x60616022, - 0x60e34b28, 0x61234b26, 0x462c4b19, 0x602b3b20, 0x606b4b28, 0x60ab4b28, 0x34304b1d, 0x4b24c40e, - 0x4b1b63eb, 0xc40e1d24, 0x656b4b1d, 0x652964ea, 0x65ab4b1c, 0x65eb4b1a, 0x6629666a, 0x66a94914, - 0x66e9491e, 0x72312102, 0x72722203, 0x22017131, 0x74317172, 0x74712109, 0x73312104, 0x73732305, - 0x210b7531, 0x757137ff, 0x733a37c1, 0x0000e775, 0x8b188720, 0xa3028f10, 0xa7048f10, 0x00000555, - 0x52005100, 0x00004e8d, 0x87008700, 0x87aa8700, 0x87058700, 0x87708700, 0xb70b8f10, 0x0000a704, - 0x87558700, 0x87028700, 0x87a08700, 0xa3808f10, 0x87808700, 0x87008f10, 0x00008730, 0x87108700, - 0x460cb5f7, 0xb09e4954, 0x22204616, 0xa8144479, 0xfe86f7fd, 0x03006830, 0xd00e0f00, 0x73202003, - 0x46272050, 0x37402108, 0x71796420, 0x981e4621, 0xfd4bf7ff, 0xd10b0005, 0x2000e003, 0x20107320, - 0x6830e7ef, 0x0f010300, 0x0f00d003, 0xd0032803, 0x2301e07e, 0xe001aa14, 0xaa182301, 0x981e2101, - 0xfb48f000, 0x71782008, 0x46692200, 0xf000981e, 0x0005fa7b, 0xaa1cd16c, 0x46204669, 0xfb9ef000, - 0x64202050, 0x73202003, 0x49344620, 0x63013080, 0x61014933, 0x46236832, 0x0f0f0311, 0x1de133ff, - 0x31f933c1, 0xd0062f03, 0x0f170412, 0xd0022f03, 0xd01a0f12, 0x4a2be04c, 0x4a2b6202, 0x4a2b6002, - 0x4a2b6042, 0x4a286402, 0x65023adc, 0x0152223b, 0x4a25630a, 0x610a3aeb, 0x614a4a26, 0x22026831, - 0x0f090309, 0xd0222900, 0x6d22e031, 0x06242401, 0xd30242a2, 0x228e2420, 0x2418e001, 0x9e1c22c2, - 0xb2f60424, 0x4f1c4326, 0x4c1c4322, 0x4322433e, 0x610a6506, 0x01d22247, 0x4a19614a, 0x4a136002, - 0x20236042, 0x63080140, 0x73982001, 0x2101e010, 0x74627421, 0x61a626e7, 0x75662606, 0x82617521, - 0x66014910, 0x3981490f, 0x490f6641, 0x731a6681, 0xb0214628, 0x0000bdf0, 0x000010c8, 0x00000406, - 0x24040405, 0xa7040705, 0x8b2007fd, 0x0000a704, 0x00000706, 0x0000a304, 0x08000400, 0x0b000400, - 0x8b2004fd, 0x04000481, 0x00002001, 0x460cb5f7, 0xb092494b, 0x22204615, 0xa8094479, 0xfdc0f7fd, - 0x26006828, 0x0f010300, 0x29002703, 0x0f00d005, 0xd0072803, 0xb0152004, 0x7326bdf0, 0x64202010, - 0xe0049708, 0x20507327, 0x20066420, 0x21089008, 0x55012045, 0x98124621, 0xfc77f7ff, 0xd1ea2800, - 0x03006828, 0xd0370f00, 0xaa0d2301, 0x98122101, 0xfa80f000, 0x96014668, 0x70077406, 0x48312601, - 0x44489602, 0x90079603, 0x98124669, 0xfd6cf7fe, 0xd1d02800, 0x4449492b, 0x2ac2780a, 0x682ad1cb, - 0x0f130312, 0xd01a4a28, 0x23027949, 0x408a3930, 0x46216522, 0x31ff2201, 0x31810312, 0x1112644a, - 0x7327640a, 0x64212150, 0x03096829, 0x46210f0a, 0x2a003180, 0xe012d005, 0xaa092301, 0x7889e7c6, - 0x7426e7e3, 0x82667463, 0x75622206, 0x4a177526, 0x660a61a3, 0x3a724a15, 0x4a15664a, 0x4a15668a, - 0x4a15600a, 0x4a15604a, 0x4a15630a, 0x4a15640a, 0x4a15610a, 0x4a15620a, 0x628a624a, 0x62ca4a14, - 0x32f91de2, 0x61154d13, 0x61554d13, 0x650d4d13, 0x654d4d13, 0x34ff4913, 0x631134c1, 0xe77a7323, - 0x00000f1c, 0x00000054, 0x00010000, 0x04000472, 0x20010400, 0x871187ee, 0xa7048b20, 0x00000406, - 0x87f98706, 0x24040405, 0x87fa8705, 0x87008700, 0x0000a704, 0x87ed8712, 0xa3048b20, 0x87de8721, - 0x00008b20, 0x879f8760, 0x2000b5f7, 0x460cb0b2, 0x25044616, 0x900c4941, 0x900e900d, 0x44792230, - 0x4668900f, 0xfcfcf7fd, 0x03006830, 0xd1720f00, 0x20044627, 0x71783740, 0x49394620, 0x60013080, - 0x60414938, 0x98324621, 0xfbbff7ff, 0xd1620005, 0x06007830, 0x28010f00, 0x1de0d10e, 0x30f94932, - 0x67416701, 0x67811409, 0x461a2300, 0x98324621, 0xfa9ef7ff, 0xd14e0005, 0x46696830, 0x0f000300, - 0x18420100, 0x46192301, 0xf0009832, 0x2200f9b3, 0x9832a91d, 0xf8e8f000, 0xd13c0005, 0xa9102003, - 0x20017008, 0x20009013, 0x74089012, 0xa8199011, 0x20109017, 0x98329018, 0xfc96f7fe, 0xd12a0005, - 0x9919481a, 0xd11f4281, 0x02402001, 0xa9109018, 0x98329417, 0xfc88f7fe, 0xd11c0005, 0x30ff4620, - 0x6c013081, 0xd0021c49, 0x1c406c40, 0x2101d113, 0x46200249, 0xfd21f7fd, 0x6020480c, 0x6060480c, - 0x71b82001, 0x65200600, 0xaa1d4633, 0x98324621, 0xfacaf000, 0x46284605, 0xbdf0b035, 0x00000d66, - 0x08180403, 0x00012404, 0x06ff06ff, 0x42464346, 0x56010400, 0x2604b5f7, 0x460c4615, 0xd04b2900, - 0xd0492d00, 0x462001f1, 0xfcf7f7fd, 0x46272101, 0x71b93740, 0x65200608, 0x60204820, 0x60604820, - 0x73602003, 0x20ff73a0, 0x550130c9, 0x02006828, 0x00030f00, 0xfabbf7fe, 0x0c060609, 0x1d301711, - 0x00302330, 0x4621462a, 0xf7ff9800, 0xe001ff3d, 0xe0032201, 0xd0180006, 0x2200e01e, 0x98004621, - 0xfc9ef7ff, 0x462ae7f6, 0x98004621, 0xfe6ef7ff, 0x462ae7f0, 0x98004621, 0xfda2f7ff, 0x462ae7ea, - 0x98004621, 0xfbbaf7ff, 0x4620e7e4, 0xf8f3f000, 0x07007828, 0x71b80f00, 0xbdfe4630, 0x42464346, - 0x56010400, 0xb089b530, 0x466d2403, 0x2501702c, 0x24000049, 0x91019503, 0x466d9402, 0x4669742c, - 0x92079308, 0xfbf0f7fe, 0xbd30b009, 0xb089b530, 0x466d2402, 0x2401702c, 0x91010049, 0x94039402, - 0x74292100, 0x93064669, 0xf7fe9205, 0xb009fbdd, 0xb5f0bd30, 0x20044607, 0x461db089, 0x460e4614, - 0xd00f2a00, 0x46682124, 0xfc77f7fd, 0x46692003, 0x20017008, 0x95089002, 0x96019003, 0x46389407, - 0xfbc2f7fe, 0xbdf0b009, 0xb098b5f7, 0x4d33460e, 0x466a2308, 0x98182100, 0xffdbf7ff, 0xd15a0004, - 0x9800492f, 0xd0014288, 0xe054462c, 0x79804668, 0x280a1c40, 0x200ad900, 0x981a9016, 0x28002108, - 0x0209d000, 0xaa029816, 0x981800c3, 0xffc1f7ff, 0xd1400004, 0x46302150, 0xfc3ff7fd, 0xe0372500, - 0xaa0200e8, 0x18835c11, 0x020079d8, 0x20ff180a, 0x42820200, 0x481bd002, 0xd1284282, 0x20022100, - 0x1819020f, 0x43397909, 0xd5f91e40, 0x008778d8, 0x2800981a, 0x0209d000, 0x020020ff, 0xd1084282, - 0x1d32463b, 0xf7ff9818, 0x0004ff94, 0x6037d113, 0x480ce00d, 0xd10a4282, 0x463b4632, 0x98183248, - 0xff87f7ff, 0xd1060004, 0x20442101, 0x1c6d5581, 0x42859816, 0x4620d3c4, 0xbdf0b01b, 0x00004e8b, - 0x50444653, 0x0000ff84, 0xb089b5ff, 0x4616461d, 0x9809460c, 0xfecdf7fe, 0xd1142800, 0x70084669, - 0x200e2701, 0x90029703, 0x4622740e, 0x326132ff, 0x4639463b, 0x98099501, 0xf83cf000, 0x97024669, - 0xf7fe9809, 0xb00dfb31, 0xb5f8bdf0, 0x20ff4607, 0x5c4030ce, 0x4616461d, 0x2800460c, 0x4638d004, - 0xf906f7ff, 0xd1052800, 0x4632462b, 0x46384621, 0xfe9ff7fe, 0x2104bdf8, 0xd00c2800, 0x29037b01, - 0x6c01d108, 0x06493040, 0xda012900, 0xe000210f, 0x8701211e, 0x46082100, 0x68014770, 0x43112201, - 0x68016001, 0xd1fc07c9, 0x8f4ff3bf, 0x8f6ff3bf, 0x00004770, 0x460eb5f8, 0x461f2104, 0x91004615, - 0xfedef7fe, 0xd0230004, 0xd0212d00, 0x19f22100, 0x23104149, 0x1a9a2000, 0xd3194188, 0xf0004620, - 0x4a0cf825, 0x200261a2, 0x19f161e0, 0x008b00b0, 0x19090081, 0x31ff31ff, 0xe0023102, 0xc140cd40, - 0x42981c40, 0x61a2d3fa, 0x61e02001, 0x90002000, 0xbdf89800, 0x5af05af0, 0xf7feb510, 0x2800feb1, - 0x3080d003, 0x07896e01, 0xbd10d5fc, 0x6e013080, 0xd0fc07c9, 0x07896e01, 0x4770d5fc, 0x4805b510, - 0x05806940, 0x48040f81, 0x44481c49, 0xf7fd6800, 0xbd10fb56, 0x400fc000, 0x0000004c, 0x4805b510, - 0x05806940, 0x48040f81, 0x44481c49, 0xf7fd6800, 0xbd10fb46, 0x400fc000, 0x0000004c, 0x460ab5f7, - 0x46963248, 0x1d0d688a, 0x2a002301, 0x461cda03, 0x40941ed2, 0x1c52e001, 0x650408d4, 0x30ff27ff, - 0x3701680a, 0x46a43081, 0xd2012a40, 0xe00a6407, 0x06128d2a, 0x461a0f14, 0x240140a2, 0x42a203e4, - 0x463ad100, 0x4c126402, 0x00532200, 0x7f1f195b, 0xd0052f00, 0x40bb2301, 0xd20142a3, 0x4616461c, - 0x2a041c52, 0x2201d3f1, 0x64440612, 0xd9074594, 0x79083140, 0xd0032800, 0x19804670, 0xe0027901, - 0x19400070, 0x98027f41, 0x20006001, 0x0000bdfe, 0x0000ffff, 0x20ff4a0e, 0x68526851, 0x0f890609, - 0x0f920692, 0xd0072900, 0xd00f2901, 0xd00d2902, 0xd1002903, 0x47702002, 0xd0032a00, 0xd0032a01, - 0x47702020, 0x47702001, 0x47702010, 0x47702008, 0x400f8000, 0x47704800, 0x01312d00, 0x68024803, - 0x438a2103, 0x6002430a, 0x00004770, 0x400fc080, 0xb5104903, 0x00c04449, 0xf7fd6809, 0xbd10fac0, - 0x00000050, 0x4602b570, 0xf832f000, 0x4909460d, 0x44494604, 0x68094610, 0xf871f7fe, 0x08c3074a, - 0x08ca4313, 0x416a191c, 0xf822f000, 0x41911b00, 0xbd70d3fa, 0x00000050, 0x4809b510, 0x69c06941, - 0x0f890589, 0x48070684, 0x44480ea4, 0x1c496800, 0xf7fd1c64, 0x4621fa94, 0xfa91f7fd, 0x0000bd10, - 0x400fc000, 0x0000004c, 0xf7ffb510, 0xbd10ff27, 0x4803b508, 0x6a406a01, 0x43c09000, 0xbd0843c9, - 0x400840c0, 0x4813b510, 0x68012304, 0x03122203, 0x43114391, 0x48106001, 0x60012100, 0x1e4a480f, - 0x61816102, 0x61c42401, 0x43196981, 0x69816181, 0x61814321, 0x60c46002, 0xf7ff6084, 0x00c0ffbd, - 0xf7fd4907, 0x4907fa5c, 0x44492800, 0xd1006008, 0xbd10600c, 0x400fc06c, 0x40084000, 0x40084100, - 0x000f4240, 0x00000050, 0xb089b5ff, 0x90032004, 0x460e980b, 0x90021d00, 0x3048980b, 0x20009007, - 0x980c9001, 0x02006800, 0x28010f00, 0x9802d105, 0x03006800, 0x90010fc0, 0x2000d07e, 0x980c7330, - 0x7800aa08, 0x0f090701, 0x55812046, 0x90042018, 0x90052000, 0x990b4630, 0xfee0f7ff, 0x6d302101, - 0x42880609, 0x980bd906, 0x79003040, 0xd0012800, 0x90042020, 0x8800980c, 0x0f000400, 0x4631d15c, - 0x9a0b9b0c, 0xf0009809, 0x9003f9af, 0xd1f52800, 0x68009802, 0xd5080281, 0x90052002, 0x7a009802, - 0x0f4f0601, 0x0ec006c0, 0x0240e007, 0x9802d506, 0x02016880, 0x02c00f4f, 0x90000ec0, 0x98041df4, - 0x34f94a95, 0xd0012820, 0xe00e4894, 0x49949807, 0x05c36800, 0x4893d501, 0x0600e002, 0x4892d503, - 0x61206161, 0x4890e003, 0x61623011, 0x20016120, 0x46357330, 0x3580488d, 0x488d6328, 0x98086128, - 0x9804b2c1, 0x43010400, 0x488a9006, 0x20234301, 0x65290140, 0x980c6320, 0x01006800, 0xd00f0f00, - 0x6840980c, 0x0e090601, 0x9901d00a, 0xb2c02700, 0x29009000, 0xe000d01f, 0x0040e069, 0xe01a9000, - 0x28009801, 0x9804d017, 0xd1042820, 0x30124876, 0x48796028, 0x46316068, 0xf7fe9809, 0x9003ffe6, - 0xd18b2800, 0x4631466a, 0xf0009809, 0x9003f9b5, 0xd14c2800, 0x98042700, 0xd0062818, 0x90052002, - 0x28009801, 0x20eed01d, 0x9801e003, 0xd0082800, 0x6c3120ed, 0x43112240, 0x99066431, 0x48674301, - 0x9802e025, 0x02816800, 0x9802d503, 0x04008900, 0x0240e003, 0x9802d503, 0x0e006880, 0x2003e011, - 0x9807e00c, 0x06816800, 0x20ecd501, 0x06c0e009, 0x206cd503, 0x91052100, 0x2013e003, 0x460f2100, - 0x99069100, 0x98054301, 0x43010600, 0x46334851, 0x60294301, 0x33ff990c, 0x33c17809, 0x20000609, - 0x93050f0a, 0xd0032a00, 0x29010f09, 0xe06bd004, 0x19c09800, 0xe0499000, 0x6809990b, 0xd3f72940, - 0x6b899902, 0xd5f3058a, 0x0f090309, 0x42112205, 0x20a5d001, 0x0789e00b, 0x4631d509, 0x9a0b9b0c, - 0xf0009809, 0x9003f895, 0xd14d2800, 0x99022001, 0x8f09220a, 0x0e890409, 0xd0074211, 0x67214938, - 0x99046761, 0xd1092920, 0xe0064936, 0x42112211, 0x4935d03a, 0x67616721, 0x67a14934, 0x9a052101, - 0x73512f00, 0x9901d011, 0xd0332900, 0xd02e2f01, 0x02892127, 0x99004308, 0x0a090609, 0x492c4308, - 0x60684308, 0x60a8482b, 0x9800e017, 0xd00f2800, 0x49299a01, 0xd0052a00, 0x1840b2c0, 0x43084927, - 0xe00a6068, 0x1840b2c0, 0x43084925, 0xe00b6068, 0x60684824, 0x28009801, 0x9905d006, 0x73882001, - 0x21406c30, 0x64304308, 0xb00d9803, 0x2126bdf0, 0xe7ce0900, 0xd00c2f01, 0x02892107, 0x99004308, - 0x0a090609, 0x49184308, 0x60684308, 0x60a84817, 0x2106e7ea, 0xe7f00900, 0x00002004, 0x08180402, - 0x00002204, 0x0a20043e, 0x08200401, 0x00000406, 0x24040405, 0x08000400, 0x00012404, 0x8a000400, - 0x06ff06ff, 0x000006ff, 0x06000600, 0x32101e00, 0xb2000200, 0x7c01a604, 0x00040200, 0xa604b000, - 0x26043000, 0x00002404, 0x32000200, 0x7c012604, 0xb08eb570, 0x2100460c, 0x9100910c, 0x910d910b, - 0x9102466a, 0x75114606, 0x71102003, 0x95032501, 0x95094813, 0x900a9208, 0x9504462b, 0x4629aa0a, - 0xf7ff4630, 0xa901fcd7, 0xf7fd4630, 0x2800ffcd, 0x9900d113, 0x401122f7, 0x040a4b0a, 0x910018d3, - 0x742522ff, 0x51133261, 0x220e7525, 0x61a17562, 0x74612104, 0x34c134ff, 0xb00e73e5, 0x0000bd70, - 0x24010485, 0x04000481, 0xb08fb5ff, 0x460c2000, 0x900b900a, 0x900d900c, 0x26016811, 0x2940461d, - 0x7426d318, 0x02496bd1, 0x000b0f49, 0xfe1ff7fd, 0x07041006, 0x1004040c, 0x492c2702, 0x492be002, - 0x39302701, 0xe009910a, 0x27034928, 0xe7f9310a, 0xe0417420, 0x05098829, 0xd03d0f0f, 0x90002000, - 0x90024669, 0x20037508, 0x96037108, 0x23019609, 0xaa0a9108, 0x46199604, 0xf7ff980f, 0xa901fc7b, - 0xf7fd980f, 0x2800ff71, 0x6828d127, 0x0f000100, 0x88a8d005, 0x0e010400, 0x0e00d001, 0x46209000, - 0x74263080, 0xd0052f01, 0xd0082f02, 0xd0162f03, 0xe7cd2000, 0x6401490e, 0x98002140, 0x490de014, - 0x98006401, 0x43082102, 0x90000200, 0x20047526, 0x98007560, 0x746661a0, 0xb0132000, 0x4905bdf0, - 0x6401313d, 0x21809800, 0xe7ee4308, 0x24010435, 0x20010401, 0x20020401, 0x460cb5f7, 0x30c520ff, - 0x59006d09, 0x1a08b098, 0x90012600, 0x74064668, 0x96022501, 0x2c009503, 0x4866d07b, 0xc88d4478, - 0xc18da90d, 0x466a2003, 0xa8097010, 0x20109007, 0x46229008, 0x21013280, 0x98189b03, 0xfc1af7ff, - 0x95024669, 0xf7fd9818, 0x2800ff0f, 0x2001d161, 0x98099011, 0xd1081c40, 0x1c40980a, 0x980bd105, - 0xd1021c40, 0x1c40980c, 0x2210d008, 0xa80da909, 0xff58f7fc, 0xd14c2800, 0xe03a9011, 0x461a2300, - 0x98184621, 0xfbc1f7ff, 0xd1422800, 0x90022009, 0x46692002, 0xa80d7008, 0x27104622, 0x32ff9005, - 0x32119706, 0x9b032101, 0xf7ff9818, 0x4669fbe3, 0x98189502, 0xfed8f7fd, 0xd1742800, 0x461a2300, - 0x98184621, 0xf978f7fe, 0xd16c2800, 0x20039002, 0x70084669, 0x9007a809, 0x98189708, 0xfec4f7fd, - 0xd1602800, 0xa9092210, 0xf7fca80d, 0x2800ff1b, 0x2032d159, 0x20009013, 0x6c209012, 0x43082140, - 0x20466420, 0x25045d01, 0x98182201, 0xfe4af7fd, 0xe048e043, 0x90142000, 0x90169015, 0x21019017, - 0x06096d20, 0xd9014288, 0xe0004823, 0x90144823, 0xb2e84923, 0x49231840, 0x43082301, 0xaa149015, - 0x98182100, 0xfb96f7ff, 0x46692003, 0xa8097008, 0x20109007, 0x98189008, 0xfe86f7fd, 0xd0120007, - 0xd0202e00, 0x6005981a, 0x28009811, 0x4621d008, 0x98189a01, 0xfd0ff7fe, 0x98184607, 0xfdf7f7fd, - 0xd0102e00, 0x2210e010, 0xa80da909, 0xfecaf7fc, 0xd00c2800, 0x2e001c6d, 0x9812d1e4, 0x1c409913, - 0x42889012, 0x4f08d3b6, 0x4638b01b, 0x2601bdf0, 0x0000e7d8, 0x000001d8, 0x8a2004ee, 0x8a1804ed, - 0x00040200, 0xa604b000, 0x00004e8e, 0x08220000, 0x06180816, 0x0612041e, 0x0411060e, 0x0216060c, - 0x06180000, 0x060c0416, 0x0312021e, 0x01210216, 0x0116011a, 0x402a8000, 0x33221100, 0x77665544, + 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x482fb51c, 0x482f9000, 0x08498901, 0x81010049, + 0x890a492d, 0x00520852, 0x8802810a, 0x07522304, 0xda022a00, 0x439a8802, 0x88088002, 0xd5020740, + 0x43988808, 0x48268008, 0x60414924, 0x60814925, 0x22806801, 0x22204391, 0x60014311, 0x466a4922, + 0x20004449, 0xfaacf002, 0xd1052800, 0x4449491e, 0xfdeef000, 0xd0002800, 0xbd1c2001, 0x47702000, + 0xb5104919, 0x20004449, 0xff45f000, 0xd0002800, 0xbd102001, 0x07492105, 0x49131842, 0x2301b510, + 0x4449049b, 0xf0022000, 0x2800fae1, 0x2001d000, 0x2105bd10, 0x07494613, 0x490b1842, 0x4449b510, + 0xf0002000, 0x2800fec9, 0x2001d000, 0x0000bd10, 0xc0233007, 0x400b8000, 0x400d0000, 0xd928c520, + 0x400bc000, 0x0000ffff, 0x00000010, 0x49a4b5f8, 0x444948a2, 0x4ea46008, 0x603048a2, 0x28006830, + 0x6b30dafc, 0x03092101, 0x63304388, 0x28006b30, 0x489edafc, 0x499e6802, 0x400a2303, 0x18d202db, + 0x431a4b9c, 0x20036002, 0x61300300, 0x28006930, 0x6930dafc, 0x043f2701, 0x613043b8, 0x3a404a93, + 0x40086b10, 0x02092123, 0x49931840, 0x63104308, 0x20014c92, 0x49936120, 0x44494891, 0x25016008, + 0xe0009000, 0x46291c6d, 0xf0039800, 0x498efad9, 0xd8f74288, 0x498d6960, 0x1e694008, 0x0b490749, + 0x02294308, 0x390139ff, 0x0d890589, 0x61604308, 0x09c06a60, 0x1cc001c0, 0x69a06260, 0x04892103, + 0x61a04308, 0x498269a0, 0x21054008, 0x18400689, 0x69e061a0, 0x4008497f, 0x07492103, 0x497e1840, + 0x61e04308, 0x210369e0, 0x43080409, 0x6a6061e0, 0x02c921e7, 0x21214388, 0x184002c9, 0x68306260, + 0x603043b8, 0x43b86b30, 0x69306330, 0x613043b8, 0x486abdf8, 0x68013080, 0x02922203, 0x60014311, + 0x48664770, 0x68013080, 0x02922203, 0x60014391, 0xb5f74770, 0x4969460c, 0x4615b08a, 0x44792214, + 0xf7ff4668, 0x4965febd, 0x44792214, 0xa8053108, 0xfeb6f7ff, 0xd0012d00, 0xd1362d01, 0x3e404e53, + 0x09876b30, 0x01bf4855, 0x200769c2, 0x438205c0, 0xd02c2d00, 0x2c00a805, 0x2c09d027, 0x2401d900, + 0x5c430061, 0x78401808, 0x05c02107, 0x069b05c9, 0x0e9b1840, 0x4d520184, 0x09a4433b, 0x43146828, + 0x43382702, 0x980a6028, 0xffbbf7ff, 0x42986b30, 0x6333d000, 0x69c14841, 0xd00042a1, 0x980a61c4, + 0xffa7f7ff, 0x43b86828, 0xb00d6028, 0x4668bdf0, 0xb570e7d1, 0x4a3b4616, 0x444a2000, 0x46046812, + 0xd0082900, 0x29014d35, 0x2902d007, 0x2404d00a, 0x46206030, 0x4610bd70, 0x6968e7fa, 0x0f810580, + 0xe00d4610, 0x482969e8, 0x6b003840, 0x0e890681, 0xf0034834, 0x2112fa15, 0x69e94348, 0x0f490189, + 0xf0031c49, 0xe7e3fa0d, 0x20044603, 0xd1042b00, 0xd0022900, 0x6008482c, 0x47702000, 0x44484821, + 0x47706800, 0x481db510, 0x05806940, 0x481d0f81, 0x44481c49, 0xf0036800, 0xbd10f9f3, 0x4604b5f8, + 0x460d4818, 0x68004448, 0xf0034920, 0x4606f9e9, 0x2103e009, 0xf0034630, 0x9000f9e3, 0xbf00e000, + 0x90001e40, 0x2200d2fb, 0x46281e64, 0x415043d2, 0x43e14605, 0x430143e8, 0xbdf8d1eb, 0x016e3600, + 0x00000004, 0x00012058, 0x400d8000, 0x400d8100, 0xc0c0c0c0, 0x18131818, 0x0f1a2323, 0x400fc000, + 0x1f78a400, 0x0000000c, 0x08954400, 0xfff8e0ff, 0xe3ffffcf, 0x9c7fff80, 0x03800001, 0x0000373e, + 0x402a8000, 0x1c9c3800, 0x09e4f580, 0x000f4240, 0x4d5ab5f8, 0x462e485a, 0x460c9000, 0x46084637, + 0xfa8ff002, 0xd0042800, 0x6ee06e26, 0x6e679000, 0x6d206ea5, 0x6d602800, 0x2800d027, 0x4951d004, + 0x63c82006, 0x62c64850, 0x28006d20, 0x494dd006, 0x31402001, 0x484c62c8, 0x61c63040, 0x23114949, + 0x630b3140, 0x30404848, 0x22016207, 0x6245634a, 0x6285638a, 0x62c563ca, 0x31804942, 0x6305600a, + 0x5d002045, 0xd0032808, 0x2800e00f, 0xe024d1d7, 0x2001493c, 0x62083140, 0x32404a3b, 0x61c86115, + 0x618860d5, 0x61486095, 0x7b206055, 0xd0012803, 0xd1062801, 0x30404833, 0x49336283, 0x31409800, + 0x46206188, 0xfa44f002, 0xd0062800, 0x2101482d, 0x62413040, 0x3040482c, 0x6da06147, 0x6de02800, + 0x2800d02a, 0x4927d005, 0x31402006, 0x48266008, 0x6da06306, 0xd0052800, 0x21044822, 0x62413040, + 0x63c64821, 0x2111481f, 0x62413040, 0x3140491e, 0x2201614f, 0x610d6202, 0x60cd61c2, 0x608d6182, + 0x604d6142, 0x2a037b22, 0x2a01d001, 0x2214d103, 0x98006102, 0xbdf86008, 0xd1d42800, 0x2104bdf8, + 0xd00f2800, 0x29037b01, 0x6c01d10b, 0x06493060, 0xda012900, 0xe003210f, 0x29007e41, 0x211ed101, + 0x21007601, 0x47704608, 0x62884908, 0x47702000, 0x6a894906, 0x20006001, 0x00004770, 0x000010f1, + 0x000130f1, 0x401f8180, 0x401f8380, 0x400f8000, 0x49fcb5f0, 0x4479b085, 0x466dc91e, 0x4efac51e, + 0x4df94ff9, 0x4cf84669, 0x37803640, 0x000335c0, 0xf9e8f003, 0x220d0609, 0x8381582b, 0x00918b89, + 0xfb42f000, 0x06496821, 0x43480e49, 0xf000e048, 0x6a37fb3b, 0x69314605, 0xf9bcf003, 0x2300463a, + 0xffe6f002, 0x07c96b21, 0x2116d001, 0x2114e000, 0x1828434d, 0xbdf0b005, 0xfb26f000, 0xe0676921, + 0xe0002116, 0x43482114, 0xf000e7f4, 0x4604fb1d, 0x06456b30, 0x693f4638, 0x68010e6d, 0xf0034620, + 0x463af999, 0xf0022300, 0x436cffc3, 0x18206b31, 0x04d22203, 0xd0114011, 0x04d22201, 0xd1004291, + 0x49d20840, 0x4ad26b09, 0x22014011, 0x1a8903d2, 0x0212d006, 0xd1cd4291, 0xe7cb0880, 0xe7f00880, + 0xe7c70840, 0xfaf0f000, 0x6a384604, 0x0646682d, 0x6b390e76, 0xf0034620, 0x462af96d, 0xf0022300, + 0x4374ff97, 0x18206a39, 0x04d22203, 0xd0104011, 0x04d22201, 0xd1004291, 0x49bc0840, 0x22016b09, + 0x07890f89, 0x18890792, 0x0052d0d6, 0xd1a142d1, 0x0880e7d6, 0x6a28e7f1, 0x6a28e001, 0x07800880, + 0x58080f00, 0x48b3e796, 0xf000e794, 0x6a21fabd, 0xd0970789, 0x2000e794, 0xb510e78c, 0x20014604, + 0xff56f7ff, 0x394049a9, 0xd0092c00, 0xd0092c01, 0xd00e2c02, 0xd00f2c03, 0x21122000, 0xbd104348, + 0xe0016809, 0x0a096809, 0x0e890689, 0xf828f003, 0x6809e7f3, 0xe7f70c09, 0x0e096809, 0xb510e7f4, + 0x69604c9d, 0x69a00180, 0x2103d512, 0x40080309, 0x2101d005, 0x42880309, 0x2000d005, 0x2002e005, + 0xff26f7ff, 0xf000e001, 0x6961fa7f, 0xe00f0ec9, 0x04892103, 0xd0134008, 0x04892101, 0xd0131a40, + 0xd0121a40, 0xd1094288, 0xf7ff2000, 0x6921ff11, 0x0f490749, 0xf0021c49, 0xbd10fff3, 0xbd102000, + 0xf7ff2001, 0xbd10ff05, 0xf7ff2002, 0xbd10ffa6, 0x2800b510, 0xf002d001, 0x2101ff8c, 0x0789487b, + 0x497e6181, 0x03d26b0a, 0x2201d5fc, 0x61420412, 0x04096901, 0x6182d5fc, 0x2001bd10, 0x07804973, + 0x47706148, 0x49752210, 0xd0012800, 0x4770638a, 0x4770634a, 0x6b014871, 0x43112201, 0x47706301, + 0x6b01486e, 0x00490849, 0x47706301, 0x4604b510, 0xf7ff2002, 0x4965fecd, 0x2c003980, 0x2c01d009, + 0x2c02d009, 0x2c03d00e, 0x2000d00f, 0x43482112, 0x6b09bd10, 0x6b09e001, 0x06890a09, 0xf0020e89, + 0xe7f3ff9f, 0x0c096b09, 0x6b09e7f7, 0xe7f40e09, 0x4c59b510, 0xf0030003, 0x0d17f8a5, 0x362a120d, + 0x403e3c39, 0x4a464442, 0x52504e4c, 0x5c5a5854, 0x0064605e, 0xff63f7ff, 0x0a896961, 0x6960e011, + 0xd50a0640, 0x06006960, 0x2001d503, 0xffbef7ff, 0x2002e005, 0xff31f7ff, 0xf7ffe001, 0x6961ff50, + 0x07490c09, 0x1c490f49, 0xff6af002, 0xf7ffbd10, 0x6961ff46, 0x0f4904c9, 0xf0021c49, 0x6961ff61, + 0x0f890589, 0xf000e7ef, 0xbd10f9cf, 0x03c02001, 0x2000bd10, 0x2002e022, 0x2000e020, 0x2001e004, + 0x2002e002, 0x2003e000, 0xff90f7ff, 0x2008bd10, 0x2001e014, 0x2000e012, 0x2001e004, 0x2002e002, + 0x2003e000, 0xfef9f7ff, 0x2005bd10, 0x2006e006, 0x2007e004, 0x2003e002, 0x2004e000, 0xfe48f7ff, + 0x2000bd10, 0x7800bd10, 0x06402101, 0x03490e40, 0x481d1841, 0x68016001, 0xdafc2900, 0x20014770, + 0x03004919, 0x47706008, 0x21017800, 0x0fc007c0, 0x18410349, 0x63014814, 0x29006b01, 0x4770dafc, + 0x49112001, 0x63080300, 0x78004770, 0x078021c1, 0x01890f80, 0x480c1841, 0x69016101, 0xdafc2900, + 0x49094770, 0x61082000, 0x78004770, 0x078021c1, 0x01890f80, 0x48041841, 0x6a016201, 0xdafc2900, + 0x00004770, 0x0000342e, 0x400d8000, 0x400d8140, 0x00808000, 0x017d7840, 0x400fc000, 0x400d8240, + 0x200049ae, 0xe7eb6208, 0x6841b530, 0x008b2200, 0x089b49aa, 0x600b3180, 0x009b6883, 0x610b089b, + 0x23017801, 0x035b0649, 0x78400e49, 0x019d18c9, 0xd01c2802, 0x006c4ba2, 0xd0162804, 0xd0122808, + 0xd00e2810, 0x4b9f4321, 0x4c9d6b18, 0x402043e4, 0x63184310, 0x30404899, 0x6b016301, 0xdafc2900, + 0x461abd30, 0x4329e7ef, 0x4321e7fb, 0x4329e7f9, 0x2001e7e9, 0x03004991, 0x63083140, 0xb570e7b0, + 0x4b8e6841, 0x22000089, 0x33800889, 0x68816319, 0x00894c8c, 0x3c800889, 0x78016021, 0x06492401, + 0x0e490364, 0x19097840, 0x280201a5, 0x2403d01a, 0x006e07a4, 0xd0132804, 0xd00f2808, 0xd00b2810, + 0x48804331, 0x00a46b04, 0x431408a4, 0x62196304, 0x28006a18, 0xbd70dafc, 0xe7f24622, 0xe7fb4329, + 0xe7f94331, 0xe7ec4329, 0x49742001, 0x31800300, 0xe7756208, 0x78c27901, 0x07920789, 0x0f920f09, + 0x78024311, 0xd0022a00, 0x03522201, 0x78424311, 0xd0022a00, 0x05122201, 0x78804311, 0xd0022800, + 0x05402001, 0x48674301, 0x62013880, 0x29006a01, 0xe755dafc, 0x49632001, 0x39800300, 0xe74f6208, + 0xb5104b60, 0x681a3b40, 0x24bf00c0, 0x43a24084, 0x40842480, 0x601c4314, 0x0e890689, 0x43114081, + 0xbd106019, 0x39404957, 0x00c3680a, 0x40982080, 0x600a4302, 0x4b53e734, 0x3b80b510, 0x00c06b1a, + 0x408424bf, 0x248043a2, 0x43144084, 0x0689631c, 0x40810e89, 0x63194311, 0x494abd10, 0x6b0a3980, + 0x208000c3, 0x43024098, 0xe719630a, 0x4846b508, 0x22036801, 0x60014311, 0x68014844, 0x43112202, + 0x20006001, 0x48429000, 0x9900bf00, 0x91001c49, 0xd3f94281, 0x3940493b, 0x221f6a08, 0x43900212, + 0x43104a3c, 0x20016208, 0xb508bd08, 0x68014836, 0x43112203, 0x48386001, 0x22026801, 0x60014311, + 0x90002000, 0xbf004832, 0x1c499900, 0x42819100, 0x492cd3f9, 0x6a083940, 0x0212221f, 0x4a2d4390, + 0x62084310, 0xbd082001, 0x2200b508, 0x92004668, 0xfebbf7ff, 0x6b014829, 0x08490049, 0x6b016301, + 0x43990483, 0x60026301, 0x22636b01, 0x43110392, 0x20016301, 0xb508bd08, 0x46682200, 0xf7ff9200, + 0x481ffeb4, 0x00496b01, 0x63010849, 0x04436b01, 0x63014399, 0x6b016002, 0x03922263, 0x63014311, + 0xbd082001, 0x2000490d, 0x48146108, 0x04826b01, 0x63014311, 0x4909e6a4, 0x62082000, 0x6b014810, + 0x43110442, 0xe69b6301, 0x6b00480e, 0xd50106c0, 0xe695480d, 0x4448480d, 0xe6916800, 0x400d8000, + 0x00808000, 0x400d8140, 0x400fc080, 0x402e0140, 0x00061a80, 0x00001701, 0x402e0340, 0x400d9000, + 0x400da000, 0x400d8240, 0x016e3600, 0x00000004, 0x460cb570, 0xf0024606, 0x0005fa35, 0x4622d10b, + 0x32802301, 0x46302100, 0xf8e6f002, 0x28017c60, 0x2000d101, 0x46287420, 0xb570bd70, 0x4605b08a, + 0x466e2000, 0x200f7030, 0x90022401, 0x74329403, 0x32ff460a, 0x32719301, 0x46214623, 0xf0024628, + 0x4669f8cb, 0x94024628, 0xffd5f001, 0xbd70b00a, 0x2004b5ff, 0x460db083, 0xd0292900, 0x36ff462e, + 0x7b7036c1, 0xd0062800, 0x9a059b06, 0xf7ff9803, 0x2800ffd4, 0x7b30d11c, 0x3480462c, 0xd10a2802, + 0x30304620, 0x466bc887, 0x4620c307, 0xc80f3040, 0xc40f3430, 0x46293c40, 0x9a059b06, 0xf0029803, + 0x7b31f8cb, 0xd1032902, 0xcd0e466d, 0xc48e3430, 0xbdf0b007, 0xb089b5ff, 0x4616461d, 0x9809460c, + 0xffc6f7ff, 0xd1142800, 0x70084669, 0x200e2701, 0x90029703, 0x4622740e, 0x326132ff, 0x4639463b, + 0x98099501, 0xf878f002, 0x97024669, 0xf0019809, 0xb00dff82, 0xb5ffbdf0, 0xb0832004, 0x4696469c, + 0xd0d52900, 0x35ff460d, 0x7b2835c1, 0x3480460c, 0xd10b2802, 0x30104620, 0x466ac889, 0xc28969e6, + 0x30204620, 0x3410c88d, 0x3c20c48d, 0x46724663, 0xf0029803, 0x7b29f8ae, 0xd1b92902, 0xcd0e466d, + 0xc44e3410, 0xb5f7e7b4, 0x4616b082, 0xd051000d, 0xd84f2e01, 0x34ff462c, 0x7a2034c1, 0xd0002800, + 0x28002001, 0x6c28d046, 0x0fc70640, 0xf0029802, 0x2e00fa62, 0x7a20d02b, 0xd0092800, 0x5d412046, + 0x9802463a, 0xfa15f7ff, 0x98024629, 0xfdaaf001, 0x28007ba0, 0x2100d003, 0xf0029802, 0x466afa5e, + 0x98022102, 0xfa55f7ff, 0xd0022f00, 0x08409800, 0xaa019000, 0x98022100, 0xfa4bf7ff, 0x98019900, + 0xfc7ef002, 0x1c40210a, 0x08804348, 0x7a21e010, 0xd0072900, 0x9802463a, 0xf9ebf7ff, 0x98024629, + 0xfd80f001, 0x28007ba0, 0x2101d0d9, 0xbf00e7d4, 0xd2fc1e40, 0xbdf0b005, 0xb089b5ff, 0x460d4617, + 0xf0014608, 0x4606fd47, 0x46292200, 0xf7ff9809, 0x463bff9a, 0x46294632, 0xf7ff9809, 0x0004ff19, + 0x2002d13f, 0x70084669, 0x24012009, 0x94039002, 0x5d412047, 0x30ff4628, 0x29003081, 0x7c01d006, + 0xd0032900, 0x91027c41, 0x91037c01, 0x97014669, 0x990c740e, 0x6c009105, 0x98029006, 0x01002101, + 0x32801942, 0x98099b03, 0xffb6f001, 0x94024669, 0xf0019809, 0x0004fec0, 0x463bd113, 0x46294632, + 0xf7ff9809, 0x0004ff38, 0x20ffd10b, 0x5d4030d0, 0xd0062800, 0x4632463b, 0x98094629, 0xff0af7ff, + 0x98094604, 0xf9d1f002, 0x46292201, 0xf7ff9809, 0x4620ff4a, 0xb5f3e71d, 0x2600b08b, 0x9d0c4669, + 0x2101700e, 0x210b9103, 0x46699102, 0x2047740e, 0x46375d40, 0x28004634, 0x4628d009, 0x308130ff, + 0x29007d01, 0x7d41d003, 0x7d009102, 0x22009003, 0x980b990c, 0xff27f7ff, 0x950a3550, 0x9009cd01, + 0xd01a2800, 0x22004633, 0x980b990c, 0xfea0f7ff, 0xd13e0004, 0x96019802, 0x980c0101, 0x180a9b03, + 0x32802101, 0xf001980b, 0x2001ff57, 0x46699002, 0xf001980b, 0x0004fe60, 0x9809d12b, 0x18361c7f, + 0xd3db2f04, 0xd1242c00, 0x90092000, 0x980c4606, 0x30ff9d0a, 0x900a30c1, 0x2f00cd80, 0x2200d013, + 0x990c9b09, 0xf7ff980b, 0x0004fec6, 0x980ad111, 0x28007bc0, 0x2200d007, 0x990c9b09, 0xf7ff980b, + 0x0004fe99, 0x9809d105, 0x19c01c76, 0x2e049009, 0x980bd3e2, 0xf959f002, 0x990c2201, 0xf7ff980b, + 0x4620fed2, 0xb5f7e6a5, 0x4617b08a, 0x4608460d, 0xfc70f001, 0x22004606, 0x980a4629, 0xfec3f7ff, + 0x4632463b, 0x980a4629, 0xfe42f7ff, 0xd1390004, 0x97014669, 0x20057008, 0x90022401, 0x740e9403, + 0x5d402047, 0xd0092800, 0x30ff4628, 0x7b013081, 0xd0032900, 0x91027b41, 0x90037b00, 0x21019802, + 0x19420100, 0x9b033280, 0xf001980a, 0x4669fee5, 0x980a9402, 0xfdeff001, 0xd1130004, 0x4632463b, + 0x980a4629, 0xfe67f7ff, 0xd10b0004, 0x30d020ff, 0x28005d40, 0x463bd006, 0x46294632, 0xf7ff980a, + 0x4604fe39, 0xf002980a, 0x2201f900, 0x980a4629, 0xfe79f7ff, 0xe64c4620, 0xb08ab5f7, 0x460d4617, + 0xf0014608, 0x4606fc17, 0x46292200, 0xf7ff980a, 0x463bfe6a, 0x46294632, 0xf7ff980a, 0x0004fde9, + 0x4669d139, 0x70089701, 0x24012008, 0x94039002, 0x2047740e, 0x28005d40, 0x4628d009, 0x308130ff, + 0x29007f01, 0x7f41d003, 0x7f009102, 0x98029003, 0x01002101, 0x32801942, 0x980a9b03, 0xfe8cf001, + 0x94024669, 0xf001980a, 0x0004fd96, 0x463bd113, 0x46294632, 0xf7ff980a, 0x0004fe0e, 0x20ffd10b, + 0x5d4030d0, 0xd0062800, 0x4632463b, 0x980a4629, 0xfde0f7ff, 0x980a4604, 0xf8a7f002, 0x46292201, + 0xf7ff980a, 0x4620fe20, 0xb5f0e5f3, 0x20044607, 0x461db089, 0x460e4614, 0xd00f2a00, 0x46682124, + 0xfaccf002, 0x46692003, 0x20017008, 0x95089002, 0x96019003, 0x46389407, 0xfd5df001, 0xbdf0b009, + 0xb08fb5ff, 0x460c2000, 0x900b900a, 0x900d900c, 0x25016811, 0x2905461e, 0x6851d202, 0xd3152940, + 0x6c117425, 0x0f490249, 0xf002000b, 0x0d07fbbb, 0x050b0905, 0x000d0705, 0xe00b2702, 0xe0092704, + 0xe0072701, 0xe0052703, 0xe03f7420, 0x05098831, 0xd03b0f0f, 0x90002000, 0x90024669, 0x20037508, + 0x95097108, 0x95049503, 0x2f019108, 0x2f02d007, 0x2f03d003, 0x2f04d02d, 0x48fdd104, 0x48fce001, + 0x900a3830, 0xaa0a2301, 0x980f4619, 0xfe04f001, 0x980fa901, 0xfd0ff001, 0xd1182800, 0x01006830, + 0xd0050f00, 0x040088b0, 0xd0010e01, 0x90000e00, 0x46202100, 0x74213080, 0xd00d2f01, 0x2f022202, + 0x2f03d013, 0x2f04d029, 0x7421d01f, 0xb0132000, 0x48e7bdf0, 0xe7d4300a, 0x064a9900, 0x4ae5d4f6, + 0x20c36402, 0x20404001, 0x9900e01e, 0xd4ed078b, 0x43114be1, 0x02086403, 0x74259000, 0x20047525, + 0x98007560, 0x746561a0, 0x9900e7e0, 0xd4dd078b, 0x33304bd8, 0x64034311, 0x9900e007, 0xd4d5060a, + 0x323d4ad5, 0x20806402, 0x91004301, 0xb5f7e7e5, 0x02402001, 0x2700b098, 0x46689001, 0x24017407, + 0x9702460d, 0x29009403, 0x48ccd072, 0xc84d4478, 0xc14da90d, 0x466a2003, 0xa8097010, 0x20109007, + 0x462a9008, 0x21013280, 0x98189b03, 0xfd94f001, 0x94024669, 0xf0019818, 0x2800fc9e, 0x9809d158, + 0xd1081c40, 0x1c40980a, 0x980bd105, 0xd1021c40, 0x1c40980c, 0x2210d007, 0xa80da909, 0xf9a3f002, + 0xd1452800, 0x2300e034, 0x4629461a, 0xf7ff9818, 0x2800fcaf, 0x2009d17b, 0x20029002, 0x70084669, + 0x462aa80d, 0x90052610, 0x960632ff, 0x21013211, 0x98189b03, 0xfd60f001, 0x94024669, 0xf0019818, + 0x2800fc6a, 0x2300d163, 0x4629461a, 0xf0019818, 0x2800fdb0, 0x9002d15b, 0x46692003, 0xa8097008, + 0x96089007, 0xf0019818, 0x2800fc56, 0xe7c2d14f, 0x90162032, 0x90152000, 0x21406c28, 0x64284308, + 0x5d412046, 0x22012602, 0xf7fe9818, 0xe038ff22, 0x2400e03d, 0x94129411, 0x94149413, 0x6d282101, + 0x42880609, 0x488ed901, 0x488ee000, 0x498e9011, 0x1840b2f0, 0x2301498d, 0x90124308, 0x2100aa11, + 0xf0019818, 0x2003fd19, 0x94024669, 0xa8097008, 0x20109007, 0x98189008, 0xfc1df001, 0xd0060004, + 0xd0142f00, 0x2f00981a, 0xd0106006, 0x2210e010, 0xa80da909, 0xf927f002, 0xd00c2800, 0x2f001c76, + 0x9815d1f0, 0x1c409916, 0x42889015, 0x4c78d3c1, 0xb01b4620, 0x2701bdf0, 0xb5ffe7e4, 0xb0824608, + 0x9000305c, 0x68c8460b, 0x27013308, 0xda032800, 0x1ec0463a, 0xe0014082, 0x08c21c40, 0x24ff9802, + 0x9e026502, 0x68489201, 0x340136ff, 0x28403681, 0x6434d201, 0x8d18e00a, 0x0f020600, 0x40904638, + 0x03d22201, 0xd1004290, 0x64304620, 0x24004d61, 0x00424620, 0x7f1718d2, 0xd00d2f00, 0x40ba2201, + 0xd20142aa, 0x46844615, 0xd90542a2, 0x053f2701, 0xd20142ba, 0x46864614, 0x28041c40, 0x6475d3e9, + 0x98026534, 0x30c130ff, 0xd10142a5, 0xe0002201, 0x72422200, 0x98012201, 0x42900612, 0x3140d92d, + 0x28007e08, 0x9800d008, 0x79014460, 0x60019804, 0x44709800, 0xe0187901, 0x00404660, 0x7f4018c0, + 0x22dc2121, 0xd0022820, 0xd10528d8, 0x9804e002, 0xe0016001, 0x60029804, 0x00404670, 0x7f4018c0, + 0xd0022820, 0xd10528d8, 0x9805e002, 0xe0016001, 0x60029805, 0xb0062000, 0x4660bdf0, 0x18c00040, + 0x98047f41, 0x46706001, 0x18c00040, 0xe7ec7f41, 0xb08db5ff, 0x90052004, 0x460f980f, 0x90033008, + 0x305c980f, 0x20009009, 0x98109004, 0x02006800, 0x28010f00, 0x9803d105, 0x03006800, 0x90040fc0, + 0x2000d071, 0x99107338, 0x78094606, 0x070aab0b, 0x21460f12, 0x900055ca, 0x90062018, 0x90072000, + 0x4638aa0a, 0xf7ff990f, 0x2101ff48, 0x06096d38, 0xd9014288, 0x90062020, 0x88009810, 0x0f000400, + 0x4639d151, 0x9a0f9b10, 0xf7ff980d, 0x9005fdd9, 0xd1f52800, 0x68009803, 0xd51d0281, 0x90072002, + 0x7a009803, 0x0f4e0601, 0x0ec006c0, 0x0000e01c, 0x24010435, 0x20010401, 0x20020401, 0x000026a8, + 0x8a2004ee, 0x8a1804ed, 0x00040200, 0xa604b000, 0x00004e2a, 0x00ffffff, 0xd5060240, 0x68809803, + 0x0f4e0201, 0x0ec002c0, 0x980f9000, 0x30409a06, 0x49fc1dfc, 0x900834f9, 0xd0022a20, 0x612048fa, + 0x7e00e012, 0x28004bf9, 0x9809d03b, 0x68004af8, 0xd50105c5, 0xe00348f7, 0xd5320600, 0x302248f3, + 0x61206162, 0xe0a9e001, 0x20016161, 0x463d7338, 0x358048f1, 0x48f16328, 0x980a6128, 0xb2c14af0, + 0x04009806, 0x43114301, 0x65299001, 0xb2c9990b, 0x43114301, 0x01402023, 0x63206021, 0x68009810, + 0x0f010100, 0x9910d00f, 0x060a6849, 0xd00a0e12, 0x9904b2c8, 0x90002600, 0xd0212900, 0x90000040, + 0x6123e01e, 0x9904e7d0, 0xd0192900, 0xd1170f00, 0x28209806, 0x48d5d104, 0x60281c40, 0x606848d9, + 0x980d4639, 0xfaa4f7ff, 0x28009005, 0x466ad166, 0x980d4639, 0xfddbf7ff, 0x28009005, 0x2600d1f6, + 0x28189806, 0x2002d006, 0x98049007, 0xd0202800, 0xe00320ee, 0x28009804, 0x20edd00a, 0x22406c39, + 0x64394311, 0x43019901, 0x430148c7, 0xe0376029, 0x68009803, 0xd5030281, 0x89009803, 0xe0030400, + 0xd5040240, 0x68809803, 0x90020e00, 0x2003e01f, 0x9808e019, 0x28007e00, 0x9809d00a, 0x06816800, + 0x06c0d40a, 0x206cd513, 0x20009002, 0xe00e9007, 0x68009803, 0xd5010281, 0xe7e620ec, 0xd5010240, + 0xe7e2206c, 0x90022013, 0x46062000, 0x99029000, 0x43089801, 0x06099907, 0x49a94308, 0x60284308, + 0x463a9910, 0x32ff7809, 0x32c10609, 0x0f0b2000, 0x2b009201, 0x0f09d003, 0xd0042901, 0x9800e06b, + 0x90001980, 0x990fe049, 0x29406849, 0x9903d3f7, 0x058a6b89, 0x0309d5f3, 0x22050f09, 0xd0014211, + 0xe00b20a5, 0xd5090789, 0x9b104639, 0x980d9a0f, 0xffa1f000, 0x28009005, 0x2001d14d, 0x220a9903, + 0x04098f09, 0x42110e89, 0x4990d007, 0x67616721, 0x29209906, 0x498ed109, 0x2211e006, 0xd03a4211, + 0x6721498c, 0x498c6761, 0x210167a1, 0x2e009a01, 0xd0117351, 0x29009904, 0x2e01d033, 0x2127d02e, + 0x43080289, 0x06099900, 0x43080a09, 0x43084983, 0x48836068, 0xe01760a8, 0x28009800, 0x9a04d00f, + 0x2a004980, 0xb2c0d005, 0x497f1840, 0x60684308, 0xb2c0e00a, 0x497d1840, 0x60684308, 0x487ce00b, + 0x98046068, 0xd0062800, 0x20019901, 0x6c387388, 0x43082140, 0x98056438, 0xbdf0b011, 0x09002126, + 0x2e01e7ce, 0x2107d00c, 0x43080289, 0x06099900, 0x43080a09, 0x4308496f, 0x486f6068, 0xe7ea60a8, + 0x09002106, 0xb5f7e7f0, 0xb0984e6c, 0xd008000d, 0x466a2308, 0x98182100, 0xfc37f7ff, 0xd1640004, + 0x2404e001, 0x4966e061, 0x42889800, 0x4634d001, 0x4668e05b, 0x60287900, 0x79804668, 0x280a1c40, + 0x200ad900, 0x981a9016, 0x28002108, 0x0209d000, 0xaa029816, 0x981800c3, 0xfc17f7ff, 0xd1440004, + 0x46282164, 0xfeeaf001, 0xe03b2600, 0xaa0200f0, 0x18835c11, 0x020079d8, 0x20ff180a, 0x42820200, + 0x4850d002, 0xd12c4282, 0x20022100, 0x1819020f, 0x43397909, 0xd5f91e40, 0x008778d8, 0x2800981a, + 0x0209d000, 0x020020ff, 0xd10c4282, 0xd9002f50, 0x462a2750, 0x3208463b, 0xf7ff9818, 0x0004fbe6, + 0x606fd113, 0x483fe00d, 0xd10a4282, 0x463b462a, 0x9818325c, 0xfbd9f7ff, 0xd1060004, 0x20582101, + 0x1c765541, 0x42869816, 0x4620d3c0, 0xb5f7e541, 0xb088460d, 0x46282103, 0x230873e9, 0x71433040, + 0x642b2358, 0x73292401, 0xd0012a00, 0x64292159, 0x210f71c4, 0x87c48781, 0x2001462e, 0x024036ff, + 0x64303681, 0x64700240, 0x46306530, 0x90073040, 0x46297244, 0xf7ff9808, 0x2800f91b, 0x4822d172, + 0x90002700, 0x97034821, 0x90012301, 0x466a9702, 0x98084619, 0xfa00f001, 0x97039702, 0x481c4f1a, + 0xe0373780, 0x00002004, 0x08180402, 0x08200412, 0x00002204, 0x0a20043e, 0x00000406, 0x24040405, + 0x08000400, 0x00012404, 0x8a000400, 0x06ff06ff, 0x000006ff, 0x06000600, 0x32101e00, 0xb2000200, + 0x7c01a604, 0x00040200, 0xa604b000, 0x26043000, 0x00002404, 0x32000200, 0x7c012604, 0x00004e27, + 0x50444653, 0x0000ff84, 0x8b188720, 0xa3028f10, 0xa7048f10, 0x23019001, 0x2100466a, 0x98089700, + 0xf9baf001, 0x02c02013, 0x23029006, 0x49feaa06, 0xf0009808, 0x2800fefc, 0x2308d114, 0x2110aa04, + 0xf0009808, 0x2800fee0, 0x9805d10c, 0xb28049f7, 0x98049005, 0xd1044288, 0x98052159, 0x42880209, + 0x48f3d002, 0xbdf0b00b, 0xaa042308, 0x98082127, 0xfec9f000, 0xd1f52800, 0x04009804, 0x90040e00, + 0x28093817, 0x9904d8ed, 0x40882001, 0x200f6528, 0x90060300, 0xaa062302, 0x98082100, 0xfec7f000, + 0xd1df2800, 0x49e3462c, 0x60213480, 0x606149e2, 0x60a149e2, 0x4ae349e2, 0x4fe44be3, 0xc48e3410, + 0x60274fdc, 0x60674fe2, 0x60a74fdc, 0xc40e3410, 0x60a74fe0, 0x60616022, 0x60e74fdf, 0x61274fdd, + 0x4fde35ff, 0xc58e3511, 0x34144fd2, 0x602f3fa0, 0x606f4fdb, 0xc48e4fdb, 0x4fd6c40e, 0x602260a7, + 0x4fd56061, 0x4fd360e7, 0x4cca6127, 0x3ca03d20, 0x4cd5602c, 0x4cd5606c, 0x462f60ac, 0x37304cd1, + 0xc70ec71e, 0x656c4ccb, 0x652964ea, 0x65ac4cca, 0x37144cc8, 0xc70e65ec, 0x66e949cd, 0x72312102, + 0x72722203, 0x22017131, 0x74317172, 0x74712109, 0x73312104, 0x73732305, 0x210b7531, 0x99077571, + 0xe77f730a, 0x2504b5f7, 0x4617b092, 0x2a00460c, 0x7878d004, 0x42887839, 0x2500d101, 0x4620e087, + 0x21083040, 0x71419011, 0x25037878, 0x28422601, 0x2841d001, 0x2502d103, 0x21049811, 0x78787141, + 0xd0012882, 0xd1002842, 0x20002621, 0x90014669, 0x70087408, 0x90022001, 0xa8092120, 0xfd5ef001, + 0x200278f9, 0x29060242, 0x2907d00b, 0x2908d012, 0x2001d001, 0x0229e02b, 0x43131d8b, 0x930931ff, + 0x0229e005, 0x3366460b, 0x31994313, 0x43119309, 0xe01c910d, 0x460f0229, 0x376602b2, 0x4317062b, + 0x431f06b5, 0x432f46ac, 0x31992599, 0x4311042d, 0x4319432f, 0x22334665, 0x04524329, 0x97094311, + 0x2e21910d, 0x6c21d103, 0x43112240, 0x90036421, 0x20019911, 0x06017188, 0x498e6521, 0x498e6021, + 0x21036061, 0x73a17361, 0x31c921ff, 0x200a5508, 0x46216760, 0xf7fe9812, 0x0005ffab, 0xaa09d117, + 0x9b032101, 0xf0019812, 0x4669f897, 0xf0009812, 0x4605ffa2, 0x217d4881, 0x00c94448, 0xf0016800, + 0xe001fcff, 0x1e40bf00, 0x28009011, 0x4628d1fa, 0xbdf0b015, 0xb09cb5f7, 0x460c981e, 0x02286805, + 0x28050f00, 0x2700d011, 0x22304975, 0xa80d4479, 0xf926f7fe, 0x0f000428, 0x0328900a, 0x980a0f05, + 0xd0042800, 0xd1132803, 0x2701e001, 0x2d00e7ec, 0x2d03d010, 0x2800d10c, 0x2003d00a, 0x20107320, + 0x981e6420, 0x02006800, 0x28040f00, 0xe019d018, 0xe1952604, 0xf7fe4668, 0x4606fbcb, 0xf7fe2000, + 0x2e00fbc3, 0x466ad106, 0x981c4621, 0xff2af7ff, 0xd1ee0006, 0x73202000, 0x64202010, 0xe0022003, + 0x64202050, 0x90092006, 0x4328980a, 0x2701d100, 0x990a4620, 0x29033040, 0x2101d008, 0x46217141, + 0xf7fe981c, 0x0006ff35, 0xe001d1d3, 0xe7f52108, 0x2d002000, 0x2f00d004, 0x2001d001, 0x2002e000, + 0xa90d0100, 0x23011842, 0x981c4619, 0xf814f001, 0x46692000, 0x75089002, 0x71082003, 0x90032001, + 0xa80b9004, 0xa9019008, 0xf000981c, 0x0006ff14, 0xa808d1af, 0x28c27b00, 0x2101d1ab, 0x2d000409, + 0xd01da808, 0x460a7c40, 0x40823830, 0x46206522, 0x30ff2201, 0x30810312, 0x11126442, 0x65016402, + 0x73202003, 0x64202010, 0x40472001, 0x46294620, 0x30c130ff, 0x35804625, 0x29009019, 0xe078d002, + 0xe7e07b80, 0x2803980a, 0x2101d173, 0x20027421, 0x82617460, 0x75622206, 0x23007521, 0x22074669, + 0x70ca700b, 0xd04a2f00, 0x466a2182, 0x61a07051, 0x6628481c, 0x3872481b, 0x481b6668, 0x981e66a8, + 0x06007800, 0xe0310f00, 0x00000555, 0x52005100, 0x00004e29, 0x8b1887a0, 0xb3068f10, 0x0000a704, + 0x87008700, 0x87aa8700, 0x87058700, 0x87708700, 0xb70b8f10, 0x87558700, 0x87028700, 0x87a08700, + 0xa3808f10, 0x87808700, 0x87008f10, 0x00008730, 0x87108700, 0x42464346, 0x56010400, 0x0000000c, + 0x00001c88, 0x04000472, 0x20010400, 0xd0022803, 0x728b9919, 0x9919e01a, 0x72882001, 0x2181e016, + 0x7059466b, 0x4bfe61a0, 0x662b48fe, 0x48fe6668, 0x210166a8, 0x77214620, 0x70423020, 0x48f87001, + 0x38726321, 0x6768672b, 0x67a848f7, 0xf7fe9800, 0x48f6fadb, 0x48f66328, 0x1de06128, 0x30f9990a, + 0xd0032900, 0xd0162f00, 0xe0152321, 0x73212101, 0x602949f0, 0x606949f0, 0x1d8949ee, 0x49ef6101, + 0x49ec6141, 0x65293115, 0x31d049ea, 0x21236001, 0x63010149, 0x2301e084, 0xd0012f00, 0xe0002122, + 0x468e2102, 0xd0012f00, 0xe000212c, 0x911a210c, 0xd0012f00, 0xe0002129, 0x910a2109, 0xd0012f00, + 0xe0002128, 0x91002108, 0x4ad80299, 0x3a18069b, 0x469c188a, 0x4bda431a, 0x602a431a, 0x23194672, + 0x015b0292, 0x9b1a18d2, 0x069b4696, 0x4bd5431a, 0x606b4313, 0x029a9b0a, 0x009b23c1, 0x920a18d2, + 0x1c9a60aa, 0x4663188a, 0x4bcf431a, 0x4acf4313, 0x188a642b, 0x431a4663, 0x43134bcd, 0x02122203, + 0x188a622b, 0x431a4663, 0x061b2303, 0x626a431a, 0x4ac662aa, 0x320d9b0a, 0x188a62eb, 0x431a4663, + 0x43134bc4, 0x9b006103, 0x069b4672, 0x23c1431a, 0x4313049b, 0x61434abd, 0x188a321c, 0x431a4663, + 0x43134bbd, 0x4672652b, 0x22f7656a, 0x188d0092, 0x431d4663, 0x46724bb9, 0x6005431d, 0x221b6042, + 0x18890152, 0x4ab64663, 0x43114319, 0x2f006301, 0x6c20d003, 0x43082140, 0x99196420, 0x73082002, + 0xb01f4630, 0xb5f7bdf0, 0x49ae460c, 0x4617b0a6, 0x44792220, 0xf7fda81d, 0x6838ff63, 0x0f000200, + 0xd0092807, 0x90002000, 0x03006838, 0xd0050f00, 0x73202003, 0xe0142050, 0xe7f42001, 0xf7fea801, + 0x4605fa17, 0xf7fe2000, 0x2d00fa0f, 0xaa01d106, 0x98264621, 0xfd76f7ff, 0xd1140006, 0x73202000, + 0x46252010, 0x35402108, 0x71696420, 0x98264621, 0xfd8ef7fe, 0xd1f00006, 0x03006838, 0xd0030f01, + 0x28030f00, 0xe09ed003, 0xaa1d2301, 0x2301e001, 0x2101aa21, 0xf0009826, 0x2008fe6f, 0x22007168, + 0x9826a904, 0xfbbff7ff, 0xd1220006, 0xaa02ab03, 0x4620a904, 0xf971f7ff, 0x28009800, 0x2050d103, + 0x20036420, 0x46257320, 0x35804870, 0x48706328, 0x68396128, 0x0f020308, 0x30ff4620, 0x900130c1, + 0x2a0338c0, 0x0409d006, 0x2a030f0a, 0x0f09d002, 0xe068d01b, 0x62294974, 0x60294974, 0x60694974, + 0x64294974, 0x39dc4971, 0x49706529, 0x60013921, 0x0149213b, 0x496d6301, 0x610139eb, 0x6141496e, + 0x03006838, 0xd02f0f00, 0x2201e04a, 0x06126d21, 0xd3024291, 0x218e2220, 0x2218e001, 0x9b0221c2, + 0xb2db0412, 0x43134c65, 0x652b4323, 0x43119b03, 0x4313b2db, 0x43234a62, 0x60034311, 0x21476101, + 0x614101c9, 0x29009900, 0x495ed00a, 0x495e6029, 0x21236069, 0x63010149, 0x20019901, 0xe0227388, + 0x6029495a, 0xe7f34952, 0x46692000, 0x27067008, 0x208270cf, 0x98007048, 0xf966f7fe, 0x74202001, + 0x74612102, 0x61a121e7, 0x75207567, 0x48348260, 0x6628300f, 0x38724832, 0x48386668, 0x66a81ec0, + 0x20029901, 0x46307308, 0xbdf0b029, 0xb0b4b5f7, 0x90004847, 0x46156810, 0x0f000200, 0x2809460c, + 0x2600d01b, 0x22504943, 0xa81e4479, 0xfe78f7fd, 0x90022000, 0x30404620, 0x90012104, 0x68287141, + 0x04000301, 0x20100f05, 0x64200f0f, 0xd0062f00, 0xd01b2f02, 0xd01f2f03, 0x2601e169, 0xa804e7e2, + 0xf926f7fe, 0x20009000, 0xf91ef7fe, 0x28009800, 0xaa04d107, 0x98344621, 0xfc84f7ff, 0x28009000, + 0x9901d1ea, 0x71482001, 0xe0032000, 0x20049901, 0x20037148, 0xe0087320, 0x73202003, 0x99012008, + 0x71482e00, 0x2001d101, 0x2d009002, 0x2d02d003, 0x2d03d001, 0x4638d1d0, 0xd1004328, 0xe03b2601, + 0x04000472, 0x04020400, 0x20010400, 0x00000406, 0x24040405, 0x0820040c, 0x24043308, 0x00002004, + 0x03110000, 0x03060000, 0x03f90000, 0x00000305, 0x03fa0000, 0x03ed0000, 0x03de0000, 0x03230000, + 0x039f0000, 0x00001932, 0xa7040705, 0x8b2007fd, 0xa704b306, 0x00000706, 0x0000a304, 0x08000400, + 0x0b000400, 0x0b2004fc, 0x27043306, 0x8b2004fd, 0x00004e29, 0x0000177c, 0xd0022d02, 0xd0022d03, + 0x2004e004, 0x2008e000, 0x71489901, 0x6c212040, 0xd0012e00, 0xe0004381, 0x64214301, 0x98344621, + 0xfc36f7fe, 0x28009000, 0x2e00d18a, 0x2f02d008, 0x2f03d002, 0xe001d10c, 0xe0092001, 0xe0072002, + 0xd0022f02, 0xd1032f03, 0x2003e001, 0x2004e000, 0xa91e0100, 0x23011842, 0x98344619, 0xfd0cf000, + 0x9a02a905, 0xf7ff9834, 0x9000fa5e, 0xd17d2800, 0xaa32ab33, 0x4620a905, 0xf80ff7ff, 0x73202003, + 0x30804620, 0x630149fd, 0x610149fd, 0xd0012e00, 0xe0002302, 0x2e002322, 0x210cd001, 0x212ce000, + 0x2e00468e, 0x2109d001, 0x2129e000, 0x2e009102, 0x2208d001, 0x2228e000, 0x0d8f07a9, 0x46399204, + 0x07aa9701, 0x370b0992, 0x4317069b, 0x431f469c, 0x431f4bec, 0x46736007, 0x029b1d0f, 0x9b02431f, + 0x069b4317, 0x9302431f, 0x049b2301, 0x6047431f, 0x3720460f, 0x46634317, 0x4be2431f, 0x431f4696, + 0x460f6507, 0x431737d8, 0x431f4663, 0x431f4bdd, 0x33f91de3, 0x1c8f601f, 0x46624317, 0x4ad94317, + 0x611f4317, 0x9a04460f, 0x02923780, 0x22014317, 0x31600292, 0x4311615f, 0x63192702, 0xd0012d02, + 0xd10f2d03, 0x46739901, 0x43191d49, 0x43199b02, 0x43194bcd, 0x99016201, 0x43111d89, 0x32cd22ff, + 0x55176401, 0x61a12100, 0xe0002d02, 0xd002e03f, 0xd0032d03, 0x2201e005, 0xe0010492, 0x04d22201, + 0x2e0061a2, 0x6c22d010, 0x431a2380, 0x22016422, 0x551a2379, 0x66024abd, 0x66424abd, 0x74202001, + 0xd0072d00, 0xe0067467, 0x69a22301, 0x431a05db, 0xe7ef61a2, 0x22067461, 0x75207562, 0x46688260, + 0x2e007301, 0x2d02d008, 0x2d03d002, 0xe007d002, 0xe0122041, 0xe0102081, 0xd00b2d02, 0xd00b2d03, + 0x20087341, 0x73c84669, 0xf7fd9803, 0x9800ffbd, 0xbdf0b037, 0xe0002042, 0x46692082, 0xe7f07348, + 0x2704b5f7, 0x460c4616, 0xd04d2900, 0xd04b2e00, 0x462001f9, 0xf8a2f001, 0x46252101, 0x71a93540, + 0x65200608, 0x6020489b, 0x6060489b, 0x73602003, 0x20ff73a0, 0x550130c9, 0x02006830, 0x00030f00, + 0xf9a0f001, 0x0c06060a, 0x1d171711, 0x3023231d, 0x46214632, 0xf0009800, 0xe001f8d6, 0xe0032201, + 0xd0180007, 0x2200e01e, 0x98004621, 0xf9cff7ff, 0x4632e7f6, 0x98004621, 0xfb7cf7ff, 0x4632e7f0, + 0x98004621, 0xfd3ff7ff, 0x4632e7ea, 0x98004621, 0xfe1cf7ff, 0x4620e7e4, 0xff51f7fd, 0x07007830, + 0x71a80f00, 0x71282001, 0xbdfe4638, 0x2004b5ff, 0x460fb081, 0xd01e2900, 0x35ff463d, 0x6c693581, + 0x460c4249, 0x18d24014, 0x400a4252, 0x31ca21ff, 0x42565dc9, 0xd10c2900, 0x29006d29, 0xe02ad009, + 0x46394622, 0xf7fe9801, 0x2800fcae, 0x6c69d103, 0x42b4190c, 0xb005d3f4, 0x6d29bdf0, 0x43884620, + 0x2000d00e, 0x28001b32, 0x4291d00c, 0x4622d80a, 0x98014639, 0xfcf0f7fe, 0xd1ec2800, 0xe0096d29, + 0xe7ef2001, 0x46394622, 0xf7fe9801, 0x2800fc8c, 0x6c69d1e1, 0x42b4190c, 0xe7dcd3df, 0xb089b5ff, + 0x9c122004, 0x4616461f, 0xd0222900, 0xd0202e00, 0xd01e2c00, 0xf0004608, 0x2103f8ed, 0x7011466a, + 0x91032101, 0x91022100, 0x4d4c7410, 0xd80042ac, 0x46694625, 0x96079701, 0x98099508, 0xfa8bf000, + 0xd1062800, 0x008908a9, 0x197f1b64, 0x2c00198e, 0xb00dd1eb, 0xb570bdf0, 0x460cb08e, 0x910c2100, + 0x910b9100, 0x466a910d, 0x46069102, 0x20037511, 0x25017110, 0x483a9503, 0x92089509, 0x462b900a, + 0xaa0a9504, 0x46304629, 0xfb56f000, 0x4630a901, 0xfa61f000, 0xd1142800, 0x22f79900, 0x4b2b4011, + 0x3310040a, 0x910018d3, 0x742522ff, 0x51133261, 0x220e7525, 0x61a17562, 0x74612104, 0x34c134ff, + 0xb00e73e5, 0xb5f0bd70, 0x20004607, 0x460db0a9, 0x24044616, 0x90254923, 0x90279026, 0x44792230, + 0xa8199028, 0xfbdcf7fd, 0x03006830, 0xd1580f00, 0x20452104, 0x46285541, 0x3080491b, 0x491b6001, + 0x46296041, 0xf7fe4638, 0x0004fa23, 0x7830d149, 0x0f000600, 0xd10e2801, 0x49151de8, 0x670130f9, + 0x14096741, 0x23006781, 0x4629461a, 0xf7fe4638, 0x0004fa24, 0x6830d135, 0xe01b0300, 0x00000406, + 0x24040405, 0x00200400, 0x00040400, 0x04000471, 0x00002003, 0x42464346, 0x56010400, 0x0000ffff, + 0x24010485, 0x000011c6, 0x08180403, 0x00012404, 0x06ff06ff, 0x01000f00, 0x1842a919, 0x46192301, + 0xf0004638, 0x2200fad9, 0x46384669, 0xf82bf7ff, 0xd1060004, 0x466a4633, 0x46384629, 0xfe68f7fe, + 0x46204604, 0xb530e4f0, 0x2403b089, 0x702c466d, 0x00492501, 0x95032400, 0x94029101, 0x742c466d, + 0x93084669, 0xf0009207, 0xb009f9c6, 0xb530bd30, 0x2402b089, 0x702c466d, 0x00492401, 0x94029101, + 0x21009403, 0x46697429, 0x92059306, 0xf9b3f000, 0x0000e7eb, 0x07406c00, 0x2001d501, 0x20004770, + 0x6c004770, 0xd5010680, 0x47702001, 0x47702000, 0x07c06c00, 0x2001d000, 0x6c004770, 0xd5010700, + 0x47702001, 0x47702000, 0x07806c00, 0x2001d501, 0x20004770, 0x6c004770, 0xd5010640, 0x47702001, + 0x47702000, 0xb085b5f3, 0x2404460e, 0xf0009805, 0x0005fcce, 0x2e00d07e, 0x7b30d07c, 0xd8792803, + 0xd00a2800, 0xd0082801, 0xd0062802, 0xd1042803, 0xf7ff4630, 0x2800ffd9, 0x20ffd002, 0xe00c3001, + 0x2102aa03, 0xf7fd9805, 0x49fefc94, 0x42889803, 0x6c30d306, 0xd4030600, 0x90002079, 0xe0219001, + 0x00602400, 0x31601981, 0x7e0f7e48, 0xd10b2800, 0x43472064, 0x214bd01d, 0xf0004638, 0x214bfeb1, + 0x42b94341, 0x1c40d200, 0x283f213f, 0x4608d900, 0x0c400680, 0x30ff00a2, 0x46693001, 0x50881c64, + 0xd3de2c02, 0x22026828, 0x28000780, 0x2000da1c, 0x4630e01e, 0xff9ff7ff, 0x46024607, 0x9805a902, + 0xfc82f7fd, 0x990248e0, 0xd0092f00, 0xfe88f000, 0x217d0880, 0x434800c9, 0xf000214b, 0xe7d2fe81, + 0xfe7ef000, 0xe7f40840, 0x20016829, 0x60294311, 0x29006d31, 0x6d71d102, 0xd0022900, 0x9b0021c0, + 0x6db1514b, 0xd1022900, 0x29006df1, 0x21c4d004, 0xe0009b01, 0x514be006, 0xd0022800, 0x43906828, + 0x24006028, 0xb0074620, 0xb5f8bdf0, 0x20044607, 0x460e461c, 0xd0162f00, 0xd0142a00, 0xd0122c00, + 0x48c14611, 0xfe4cf000, 0x46054601, 0x46304361, 0xfe46f000, 0x1c40e000, 0x43694601, 0x42b14361, + 0x6038d3f9, 0xbdf82000, 0xb085b5f0, 0x460e4db7, 0x95004607, 0xf0009501, 0x0004fc1a, 0x2e00d02b, + 0xaa02d029, 0x46382102, 0xfbf3f7fd, 0x2101aa03, 0xf7fd4638, 0x2601fbee, 0x02b64fad, 0x46394633, + 0x9a024668, 0xffc1f7ff, 0x46394633, 0x9a03a801, 0xffbbf7ff, 0x42a89800, 0x9500d900, 0x42a89801, + 0x9501d900, 0x99019800, 0xb2890400, 0x60604308, 0xb0052000, 0x2004bdf0, 0xb5f3e7fb, 0x2000b087, + 0x460c9000, 0x98072504, 0xfbe1f000, 0x28009003, 0x2c00d054, 0x4620d052, 0x46273040, 0x37509005, + 0x30ff2600, 0x90023041, 0x00b26838, 0x98030a81, 0x90011810, 0x7ba06601, 0x06c51d3f, 0x0eed7b60, + 0x0d8006c0, 0x7be04305, 0x0c400700, 0x46204305, 0xfed3f7ff, 0xd0022800, 0x02802001, 0x6f604305, + 0xd00d2800, 0x2102aa04, 0xf7fd9807, 0x2301fb92, 0x46686f61, 0xf7ff9a04, 0x9800ff68, 0x43050400, + 0x67059801, 0x79c09805, 0xd00e2800, 0x7c009802, 0xd00a0741, 0x22079902, 0x03407c49, 0x0d090709, + 0x18800352, 0x4308b280, 0x2009e001, 0x99010200, 0x60083180, 0x2e041c76, 0x2500d3b6, 0xb0094628, + 0x4602bdf0, 0x2004b510, 0xd0212a00, 0xd01f2900, 0x5c402044, 0xd10c2801, 0x084368d0, 0x2040005b, + 0x46084303, 0xfe76f7ff, 0xd0012800, 0x43032001, 0x68d060d3, 0x43082120, 0x4b5e60d0, 0x00812000, + 0x6a0c1889, 0x620c401c, 0x28031c40, 0x2000d3f7, 0xb510bd10, 0xfb5bf000, 0xd00b2800, 0x23012100, + 0x008a07db, 0x32801812, 0x431c6814, 0x1c496014, 0xd3f62904, 0xb5febd10, 0x20044605, 0x460e9000, + 0xf0004628, 0x0004fb44, 0x2e00d07e, 0x7830d0fc, 0xd8792803, 0x90017c30, 0x46202700, 0xfb3ff000, + 0xf7ff4628, 0x6960ffd6, 0x4308211e, 0x46256160, 0x68703580, 0x78306228, 0xd0022802, 0xd0022803, + 0x8b30e003, 0x8c30e000, 0x7b31b287, 0x1e497a30, 0x07490700, 0x09490b00, 0x99014308, 0x430807c9, + 0x62684338, 0x28037830, 0x69f0d14b, 0x07836a32, 0x2340d14a, 0x469e211c, 0x6bab63a9, 0x430b2101, + 0x6bab63ab, 0xd1fc07db, 0x430b6b2b, 0xe036632b, 0x31f91de1, 0x45724673, 0x6967d30f, 0x06bf089b, + 0xe029d402, 0xc080c980, 0xd2fb1e5b, 0x1a524671, 0x23206961, 0x61614319, 0x6f2be01e, 0x0d5b061b, + 0xd2034293, 0xc908e018, 0xc0081f12, 0xd2fa2a04, 0xd0102a00, 0x91016809, 0x468ca901, 0x23004601, + 0x4667e007, 0x700f783f, 0x1c7f4667, 0x46bc1c49, 0x42931c5b, 0x2200d3f5, 0x07096961, 0x2a00d401, + 0x7830d1c6, 0xe0002802, 0xd001e062, 0xd1482801, 0x69b26971, 0xd15b0788, 0x46842040, 0x63e8201c, + 0xe0096be8, 0x05f5e100, 0x3b9aca00, 0x0000ffff, 0x1dcd6500, 0xfcf0ff00, 0x43182301, 0x6be863e8, + 0xd1fc07c0, 0xe02a4686, 0x30ff4620, 0x30816963, 0xd521065b, 0x089b4663, 0xd2024562, 0xc980e00e, + 0x1e5bc080, 0x4660d2fb, 0xe0091a12, 0xdd032a00, 0xc080c980, 0xe0011f12, 0xc0802700, 0xd2f51e5b, + 0x28004670, 0x6b28d104, 0x43182301, 0x469e6328, 0x23406960, 0x61604318, 0x07006960, 0x2a00d401, + 0x7830dcd2, 0xd1032800, 0x21016b28, 0x63284308, 0xf0004620, 0x6960fa74, 0xd50b0700, 0x01006e68, + 0x280e0f00, 0x48fed001, 0x48fde001, 0x90001e40, 0xbdfe9800, 0xe7fa2000, 0x460eb5f8, 0x461f2104, + 0x91004615, 0xfa53f000, 0xd0230004, 0xd0212d00, 0x19f22100, 0x23104149, 0x1a9a2000, 0xd3194188, + 0xf0004620, 0x4aeffa4c, 0x200261a2, 0x19f161e0, 0x008b00b0, 0x19090081, 0x31ff31ff, 0xe0023102, + 0xc140cd40, 0x42981c40, 0x61a2d3fa, 0x61e02001, 0x90002000, 0xbdf89800, 0x4604b570, 0xb08a2004, + 0xd0242900, 0x466e2000, 0x20037030, 0x90022501, 0x74329503, 0x93012047, 0x28005c40, 0x4608d009, + 0x308130ff, 0x2a007a02, 0x7a42d003, 0x7a009202, 0x98029003, 0x01009b03, 0x21011842, 0x32804620, + 0xffaaf7ff, 0x46204669, 0xf7ff9502, 0xb00afeb4, 0xb5ffbd70, 0xb0912004, 0x900e460d, 0xd0792900, + 0x30404628, 0x21018f82, 0x4094460c, 0x93028fc2, 0x22039200, 0x711a466b, 0x91039104, 0x9108a90c, + 0x29009913, 0x2108d001, 0x2104e000, 0x99139109, 0x79c07519, 0xd0092800, 0x30ff4628, 0x79013081, + 0xd0032900, 0x91037941, 0x90047900, 0x9b049803, 0x19420100, 0x99033280, 0xf7ff9811, 0x6f2dff6d, + 0xd0012d00, 0xe0002001, 0x26002000, 0xa901900f, 0xf7ff9811, 0x900efe70, 0xd13b2800, 0x28009813, + 0xa90ad019, 0xab0ca80b, 0x781f2208, 0x785f700f, 0x1c407007, 0x1e921c49, 0x2a001c9b, 0x9800d1f5, + 0x2800990b, 0xd004980a, 0x46214008, 0xd10a4381, 0x4308e00e, 0x9800e00a, 0xd0062800, 0x4620990c, + 0x28004388, 0x2701d004, 0x980ce003, 0xe7f84020, 0x980f2700, 0xd00b4207, 0x43304628, 0x207dd00d, + 0x210000c0, 0xf9aaf7fd, 0x43c02000, 0x41461e6d, 0xd1bc2f00, 0xb015980e, 0x4889bdf0, 0x900e1c40, + 0xb5f7e7f8, 0x460db08a, 0x980a2604, 0xf96ff000, 0xd0540007, 0xd0522d00, 0x46692001, 0x980c7008, + 0x20009001, 0x20047408, 0x90062400, 0x194200a0, 0x30204610, 0x29007841, 0x2301d03e, 0x59db025b, + 0x0f9b059b, 0x192bd003, 0x2b027f5b, 0x9102d034, 0x32307800, 0x90039205, 0x46292200, 0x980a9b0c, + 0xff1af7ff, 0xd12b2800, 0x21019802, 0x19420100, 0x9b033280, 0xf7ff980a, 0x2001fedf, 0x46699002, + 0xf7ff980a, 0x0006fde8, 0x8a68d11a, 0xd10e2800, 0x7f491929, 0xd00a2902, 0xd0082903, 0x46292200, + 0x980a9b0c, 0xff25f7ff, 0xd1090006, 0x2164e004, 0x21004348, 0xf942f7fd, 0x2c031c64, 0x4630d3b6, + 0xbdf0b00d, 0xb087b5f3, 0x2604460d, 0xf0009807, 0x0004f90e, 0x2d00d07e, 0x7c28d0fc, 0xd1022800, + 0x28007f28, 0x6c28d009, 0xd40406c0, 0xf7ff4628, 0x2800fc22, 0x2001d001, 0x2000e000, 0x494a9003, + 0x42886828, 0x9807d166, 0xf87bf7fd, 0x98074629, 0xf95ef7fd, 0x30404628, 0x90029903, 0xd0022900, + 0x21012200, 0x4628e005, 0xfc05f7ff, 0x98024602, 0x98077981, 0xf86df7fd, 0xf7fd9807, 0x6820f85a, + 0x43b02602, 0x46206020, 0xf8c9f000, 0x43306820, 0x68206020, 0x40084935, 0x79499902, 0xd1012908, + 0x43080289, 0x43084932, 0x07897b29, 0x43010e89, 0x46296021, 0xf7ff9807, 0x68a0fc97, 0x03c92101, + 0x60a04388, 0xf7ff4628, 0x2800fbc3, 0x68a0d004, 0x04c92101, 0x60a04308, 0x46204629, 0xfd21f7ff, + 0x98074629, 0xfcb9f7ff, 0x98074629, 0xfbcaf7ff, 0x21026820, 0x60204388, 0xf0004620, 0x4628f890, + 0x30507c29, 0x29009004, 0x9807d01c, 0x20049005, 0xe0002100, 0x9e04e05d, 0x460f9100, 0x9101ce02, + 0xd00a2900, 0x9a004629, 0xf0009805, 0x2800f890, 0x9a01d106, 0x18899900, 0x1c7f9100, 0xd3ed2f04, + 0xd1460006, 0x28007f28, 0x9807d027, 0x20049005, 0xd0202d00, 0x9e042100, 0x460f9100, 0xe009ce02, + 0x00001b59, 0x5af05af0, 0x42464346, 0x0000df0f, 0xffff0000, 0x29009101, 0x4629d00a, 0x98059a00, + 0xfedff7ff, 0xd1062800, 0x99009a01, 0x91001889, 0x2f041c7f, 0x0006d3e2, 0x9803d11b, 0xd0172800, + 0x26026820, 0x60204330, 0xf7ff4628, 0x4602fb64, 0x79819802, 0xf7fc9807, 0x4629ffcc, 0xf7ff9807, + 0x4629fc13, 0xf7ff9807, 0x6820fb5d, 0x602043b0, 0x46302600, 0xb510e4a3, 0xf829f000, 0xd0032800, + 0x6e013080, 0xd5fc0789, 0xb510bd10, 0xf81ff000, 0xd0012800, 0xf813f000, 0xb570bd10, 0xf000460d, + 0x0004f816, 0xf000d00a, 0x2001f81a, 0x682102c0, 0xd0012d00, 0xe0004301, 0x60214381, 0x6801bd70, + 0x43112201, 0x68016001, 0xd1fc07c9, 0x46014770, 0x29002000, 0x4830d102, 0x68004478, 0x30804770, + 0x07c96e01, 0x6e01d0fc, 0xd5fc0789, 0xb5f04770, 0x4616b089, 0x4607460c, 0xf7ff2504, 0x2800ffe8, + 0x2c00d048, 0x30ffd046, 0x300230ff, 0x05806800, 0xd0020f80, 0x28027c60, 0x2501d025, 0x700d4669, + 0x7d609601, 0x7d209002, 0x20009003, 0x46207408, 0x90053018, 0x90062004, 0x22004633, 0x46384621, + 0xfd9af7ff, 0x21019802, 0x19020100, 0x32804638, 0xf7ff9b03, 0x4669fd61, 0x95024638, 0xfc6bf7ff, + 0xd1170005, 0x2500e001, 0x8a61e014, 0xd10c2900, 0x28027c60, 0x2803d009, 0x4633d007, 0x46212200, + 0xf7ff4638, 0x4605fda6, 0x2064e004, 0x21004348, 0xffc4f7fc, 0xe4124628, 0x0000077c, 0x485eb570, + 0x074a8801, 0x2a002104, 0x8802da02, 0x8002438a, 0x8802485a, 0xd5020752, 0x438a8802, 0x48598002, + 0x60414957, 0x60814958, 0x22806801, 0x22204391, 0x60014311, 0x69014855, 0xd00307c9, 0x08496901, + 0x61010049, 0x8f4ff3bf, 0x8f6ff3bf, 0x21004d50, 0xf3bf6129, 0xf3bf8f4f, 0x4c4e8f6f, 0x22016960, + 0x43100452, 0xf3bf6160, 0xf3bf8f4f, 0x48498f6f, 0x60413080, 0x8f4ff3bf, 0x01016800, 0x04c00c49, + 0x05ca0d83, 0x0c964618, 0x43320782, 0x1e40622a, 0x1e49d2fa, 0xf3bfd2f5, 0x69608f4f, 0x04092101, + 0x61604308, 0x8f4ff3bf, 0x8f6ff3bf, 0xb5f8bd70, 0x69604c39, 0x493a4a39, 0xd5180180, 0x230369a0, + 0x4018031b, 0x2201d005, 0x42900312, 0x2000d00a, 0x6910e009, 0xd0010780, 0xe0002016, 0x49302014, + 0xe0004348, 0x69614608, 0x0f490089, 0x6810e029, 0x06404b2b, 0x43580e40, 0x6b100847, 0xd00107c0, + 0xe0002516, 0x48262514, 0x48244345, 0x6a063040, 0xf0006900, 0x4632fa1f, 0xf0002300, 0x69a1f849, + 0x4a201940, 0xd0114011, 0x04922201, 0x1a894b1e, 0x1a89d016, 0x4291d017, 0x6920d107, 0x0f490741, + 0x1c494638, 0xf90cf000, 0x2000e000, 0x04c96961, 0x1c490f49, 0xf904f000, 0x44494914, 0xbdf86008, + 0x0c096819, 0x6819e000, 0x0e890689, 0xf8f8f000, 0x43482112, 0x0000e7ea, 0x400b8000, 0x400d0000, + 0xd928c520, 0x400bc000, 0x0000ffff, 0xe000e000, 0xe000ef40, 0xe000ed00, 0x400fc000, 0x400d8000, + 0x016e3600, 0x000c0000, 0x400d8100, 0x0000000c, 0x4605b5fe, 0x460c4610, 0xd0734318, 0x468c46ae, + 0x1aad2000, 0x419c4601, 0x4666d367, 0x24012700, 0x1ab6463d, 0xd302419d, 0x463a4613, 0x46652421, + 0x042f4676, 0x433e0c36, 0x1ab60c2d, 0xd304419d, 0x041b0c15, 0x0412432b, 0x46653410, 0x062f4676, + 0x433e0a36, 0x1ab60a2d, 0xd304419d, 0x021b0e15, 0x0212432b, 0x46653408, 0x072f4676, 0x433e0936, + 0x1ab6092d, 0xd304419d, 0x011b0f15, 0x0112432b, 0x46651d24, 0x07af4676, 0x433e08b6, 0x1ab608ad, + 0xd304419d, 0x009b0f95, 0x0092432b, 0x46651ca4, 0x07ef4676, 0x433e0876, 0x1ab6086d, 0xd31a419d, + 0x415b1892, 0xe0161c64, 0x46761800, 0x41494665, 0x419d1ab7, 0x90009101, 0x4660d309, 0x41981ab1, + 0x4684468e, 0x99019800, 0x1c402500, 0x07dd4169, 0x432a0852, 0x1e64085b, 0x4672d5e6, 0xb0034663, + 0xe7ffbdf0, 0x46012000, 0x46c046c0, 0x4623462a, 0xb510e7f5, 0xf0002000, 0x46c0f907, 0x200146c0, + 0xf8fcf000, 0x4603bd10, 0x430bb510, 0xd10f079b, 0xd30d2a04, 0xc910c808, 0x42a31f12, 0xba18d0f8, + 0x4288ba21, 0x2001d901, 0x2000bd10, 0xbd1043c0, 0xd0032a00, 0xd00307d3, 0xe0071c52, 0xbd102000, + 0x780c7803, 0x1c491c40, 0xd1071b1b, 0x780c7803, 0x1c491c40, 0xd1011b1b, 0xd1f11e92, 0xbd104618, + 0xc004e001, 0x29041f09, 0x078bd2fb, 0x8002d501, 0x07c91c80, 0x7002d000, 0x29004770, 0x07c3d00b, + 0x7002d002, 0x1e491c40, 0xd3042902, 0xd5020783, 0x1c808002, 0xe7e31e89, 0xe7ee2200, 0xe7df2200, + 0x09032200, 0xd32c428b, 0x428b0a03, 0x2300d311, 0xe04e469c, 0x430b4603, 0x2200d43c, 0x428b0843, + 0x0903d331, 0xd31c428b, 0x428b0a03, 0x4694d301, 0x09c3e03f, 0xd301428b, 0x1ac001cb, 0x09834152, + 0xd301428b, 0x1ac0018b, 0x09434152, 0xd301428b, 0x1ac0014b, 0x09034152, 0xd301428b, 0x1ac0010b, + 0x08c34152, 0xd301428b, 0x1ac000cb, 0x08834152, 0xd301428b, 0x1ac0008b, 0x08434152, 0xd301428b, + 0x1ac0004b, 0x1a414152, 0x4601d200, 0x46104152, 0xe05d4770, 0xd0000fca, 0x10034249, 0x4240d300, + 0x22004053, 0x0903469c, 0xd32d428b, 0x428b0a03, 0x22fcd312, 0xba120189, 0x428b0a03, 0x0189d30c, + 0x428b1192, 0x0189d308, 0x428b1192, 0x0189d304, 0x1192d03a, 0x0989e000, 0x428b09c3, 0x01cbd301, + 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0, 0x428b0943, 0x014bd301, 0x41521ac0, 0x428b0903, + 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301, 0x41521ac0, 0x428b0883, 0x008bd301, 0x41521ac0, + 0x0843d2d9, 0xd301428b, 0x1ac0004b, 0x1a414152, 0x4601d200, 0x41524663, 0x4610105b, 0x4240d301, + 0xd5002b00, 0x47704249, 0x105b4663, 0x4240d300, 0x2000b501, 0x46c046c0, 0x0000bd02, 0x20184901, + 0xe7febeab, 0x00020026, 0xf000b510, 0xf000f80b, 0xbd10f802, 0xb5104770, 0xd0012800, 0xffeef7ff, + 0x0000bd10, 0x2100b510, 0xf000a002, 0x2001f813, 0x0000bd10, 0x41474953, 0x3a545242, 0x6e624120, + 0x616d726f, 0x6574206c, 0x6e696d72, 0x6f697461, 0x0000006e, 0x4605b570, 0x200a460c, 0x1c6de000, + 0xf812f000, 0xd0062d00, 0x28007828, 0xe002d1f7, 0xf0001c64, 0x2c00f809, 0x7820d002, 0xd1f72800, + 0xf000200a, 0xbd70f801, 0x4669b508, 0x20037008, 0xbd08beab, 0x0c04b5f8, 0x4626b28b, 0x435eb282, + 0x46100c0d, 0x43580c37, 0x19800436, 0x41792100, 0x436e4616, 0x04360c37, 0x41791980, 0x436e4626, + 0xbdf81989, 0x4674b430, 0x78251e64, 0x42ab1c64, 0x461dd200, 0x005b5d63, 0xbc3018e3, 0x00004718, + 0x08220000, 0x06180816, 0x0612041e, 0x0411060e, 0x0216060c, 0x06180000, 0x060c0416, 0x0312021e, + 0x01210216, 0x0116011a, 0x017d7840, 0x02faf080, 0x05f5e100, 0x07735940, 0x33221100, 0x77665544, 0xbbaa9988, 0xffeeddcc, 0x0818045a, 0x24ff3008, 0x00000000, 0x00000000, 0x0918055a, 0x25ff3108, 0x00000000, 0x00000000, 0x0a18065a, 0x26ff3208, 0x00000000, 0x00000000, 0x2403049f, 0x00000000, - 0x00000000, 0x00000000, 0x8760879f, 0xa7048b20, 0x00000000, 0x00000000, 0x0818045a, 0x24ff3008, - 0x00000000, 0x00000000, 0x8b20075a, 0x0000a7ff, 0x00000000, 0x00000000, 0x0818045a, 0x24ff3008, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8a18065a, 0x0000a6ff, - 0x00000000, 0x00000000, 0x8b20075a, 0x0000a7ff, 0x00000000, 0x00000000, 0x00000000, 0x40184000, - 0x40188000, 0x4018c000, 0x40190000, 0x40194000, 0x40198000, 0x4019c000, 0x401a0000, 0x0014ff80, - 0x00160015, 0x00180017, 0x001a0019, 0xffff001b, 0x001c0518, 0x0118000c, 0x03060302, 0x060e051a, - 0x00000000, 0x00000000, 0x00000000, 0x412000d1, 0x60002000, 0x00000000, 0x00000000, 0x60001020, - 0x60001000, 0x00000000, 0x00000000, 0x60000000, 0x00800000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00b71b00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x0760079f, 0x27040b20, 0x00000000, 0x00000000, 0x8760879f, 0xa7048b20, + 0x00000000, 0x00000000, 0x0818045a, 0x24ff3008, 0x00000000, 0x00000000, 0x8b20075a, 0x0000a7ff, + 0x00000000, 0x00000000, 0x0818045a, 0x24ff3008, 0x00000000, 0x00000000, 0x0a18065a, 0x000026ff, + 0x00000000, 0x00000000, 0x0b18075a, 0x000027ff, 0x00000000, 0x00000000, 0x8a18065a, 0x0000a6ff, + 0x00000000, 0x00000000, 0x8b20075a, 0x0000a7ff, 0x00000000, 0x00000000, 0x402a8000, 0x00000000, + 0x00000000, 0x00000000, 0x1f78a400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -459,40 +510,50 @@ static const uint32_t RT1050_IS26KS512S_flash_prog_blob[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + 0x00000000, 0x00000000, 0x00000000 }; +// Start address of flash +static const uint32_t flash_start = 0x60000000; +// Size of flash +static const uint32_t flash_size = 0x04000000; + /** -* List of start and size for each size of flash sector +* List of start and size for each size of flash sector - even indexes are start, odd are size * The size will apply to all sectors between the listed address and the next address * in the list. * The last pair in the list will have sectors starting at that address and ending -* at address start + size. +* at address flash_start + flash_size. */ static const sector_info_t sectors_info[] = { - {0x60000000, 0x00000400}, - }; + {0x60000000, 0x00040000}, +}; static const program_target_t flash = { - 0x200003a9, // Init - 0x20000c9d, // UnInit - 0x2000035d, // EraseChip - 0x20000389, // EraseSector - 0x20000c2d, // ProgramPage - 0x0, // Verify + 0x20000075, // Init + 0x200000e1, // UnInit + 0x200000e5, // EraseChip + 0x200000f9, // EraseSector + 0x20000117, // ProgramPage + 0x00000000, // Verify // BKPT : start of blob + 1 // RSB : blob start + header + rw data offset // RSP : stack pointer { 0x20000001, - 0x20003480, - 0x20000800 + 0x20003ae0, + 0x20004e00 }, - 0x20000000 + 0x00000A00, // mem buffer location - 0x20000000, // location to write prog_blob in target RAM - sizeof(RT1050_IS26KS512S_flash_prog_blob), // prog_blob size - RT1050_IS26KS512S_flash_prog_blob, // address of prog_blob - 0x00000200 // ram_to_flash_bytes_to_be_written + // mem buffer location + 0x20004e00, + // location to write prog_blob in target RAM + 0x20000000, + // prog_blob size + sizeof(MIMXRT105x_HYPER_256KB_SEC_flash_prog_blob), + // address of prog_blob + MIMXRT105x_HYPER_256KB_SEC_flash_prog_blob, + // ram_to_flash_bytes_to_be_written + 0x00000200 }; diff --git a/source/family/freescale/mimxrt1050_spi_flash/flash_blob.c b/source/family/freescale/mimxrt1050_spi_flash/flash_blob.c index 5c3c81479..1a17056c9 100644 --- a/source/family/freescale/mimxrt1050_spi_flash/flash_blob.c +++ b/source/family/freescale/mimxrt1050_spi_flash/flash_blob.c @@ -1,491 +1,496 @@ -/** - * @file flash_blob.c - * @brief Flash algorithm for the i.MXRT1050 QSPI +/* Flash algorithm for MIMXRT105x 8mB QuadSPI NOR Flash * * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * Copyright (c) 2009-2021 Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ +// Generated from 'MIMXRT105x_QuadSPI_4KB_SEC.FLM' (MIMXRT105x 8mB QuadSPI NOR Flash) +// Originating from 'NXP.MIMXRT1052_DFP.13.1.1.pack' +// digest = 32f76ad6e166887076f25302dd9d0bacc352fccaca19205c623231759a7fe084, file size = 1510724 +// algo version = 0x101, algo size = 15484 (0x3c7c) static const uint32_t MIMXRT105x_QuadSPI_4KB_SEC_flash_prog_blob[] = { - 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, + 0xe7fdbe00, 0x4605b570, 0x4616460c, 0xcc0fe002, 0x3e10c50f, 0xd2fa2e10, 0xd3022e08, 0xc503cc03, 0x2e043e08, 0xcc01d307, 0x1f36c501, 0x7821e003, 0x1c647029, 0x1e761c6d, 0xbd70d2f9, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770bac0, 0x4770bac0, 0x4770bac0, - 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x481db51c, 0x9000491d, 0x4449466a, 0xf0022000, - 0x2800fa9e, 0x4919d105, 0xf0004449, 0x2800fde3, 0x2001d000, 0x2000bd1c, 0x49144770, 0x4449b510, - 0xf0002000, 0x2800ff3a, 0x2001d000, 0x2105bd10, 0x18420749, 0xb510490d, 0x049b2301, 0x20004449, - 0xfad3f002, 0xd0002800, 0xbd102001, 0x46132105, 0x18420749, 0xb5104905, 0x20004449, 0xfebef000, - 0xd0002800, 0xbd102001, 0xc0000006, 0x00000010, 0x49a4b5f8, 0x444948a2, 0x4ea46008, 0x603048a2, - 0x28006830, 0x6b30dafc, 0x03092101, 0x63304388, 0x28006b30, 0x489edafc, 0x499e6802, 0x400a2303, - 0x18d202db, 0x431a4b9c, 0x20036002, 0x61300300, 0x28006930, 0x6930dafc, 0x043f2701, 0x613043b8, - 0x3a404a93, 0x40086b10, 0x02092123, 0x49931840, 0x63104308, 0x20014c92, 0x49936120, 0x44494891, - 0x25016008, 0xe0009000, 0x46291c6d, 0xf0039800, 0x498efa9b, 0xd8f74288, 0x498d6960, 0x1e694008, - 0x0b490749, 0x02294308, 0x390139ff, 0x0d890589, 0x61604308, 0x09c06a60, 0x1cc001c0, 0x69a06260, - 0x04892103, 0x61a04308, 0x498269a0, 0x21054008, 0x18400689, 0x69e061a0, 0x4008497f, 0x07492103, - 0x497e1840, 0x61e04308, 0x210369e0, 0x43080409, 0x6a6061e0, 0x02c921e7, 0x21214388, 0x184002c9, - 0x68306260, 0x603043b8, 0x43b86b30, 0x69306330, 0x613043b8, 0x486abdf8, 0x68013080, 0x02922203, - 0x60014311, 0x48664770, 0x68013080, 0x02922203, 0x60014391, 0xb5f74770, 0x4969460c, 0x4615b08a, - 0x44792214, 0xf7ff4668, 0x4965feeb, 0x44792214, 0xa8053108, 0xfee4f7ff, 0xd0012d00, 0xd1362d01, - 0x3e404e53, 0x09876b30, 0x01bf4855, 0x200769c2, 0x438205c0, 0xd02c2d00, 0x2c00a805, 0x2c09d027, - 0x2401d900, 0x5c430061, 0x78401808, 0x05c02107, 0x069b05c9, 0x0e9b1840, 0x4d520184, 0x09a4433b, - 0x43146828, 0x43382702, 0x980a6028, 0xffbbf7ff, 0x42986b30, 0x6333d000, 0x69c14841, 0xd00042a1, - 0x980a61c4, 0xffa7f7ff, 0x43b86828, 0xb00d6028, 0x4668bdf0, 0xb570e7d1, 0x4a3b4616, 0x444a2000, - 0x46046812, 0xd0082900, 0x29014d35, 0x2902d007, 0x2404d00a, 0x46206030, 0x4610bd70, 0x6968e7fa, - 0x0f810580, 0xe00d4610, 0x482969e8, 0x6b003840, 0x0e890681, 0xf0034834, 0x2112f9d7, 0x69e94348, - 0x0f490189, 0xf0031c49, 0xe7e3f9cf, 0x20044603, 0xd1042b00, 0xd0022900, 0x6008482c, 0x47702000, - 0x44484821, 0x47706800, 0x481db510, 0x05806940, 0x481d0f81, 0x44481c49, 0xf0036800, 0xbd10f9b5, - 0x4604b5f8, 0x460d4818, 0x68004448, 0xf0034920, 0x4606f9ab, 0x2103e009, 0xf0034630, 0x9000f9a5, - 0xbf00e000, 0x90001e40, 0x2200d2fb, 0x46281e64, 0x415043d2, 0x43e14605, 0x430143e8, 0xbdf8d1eb, - 0x016e3600, 0x00000004, 0x00012058, 0x400d8000, 0x400d8100, 0xc0c0c0c0, 0x18131818, 0x0f1a2323, - 0x400fc000, 0x1f78a400, 0x0000000c, 0x08954400, 0xfff8e0ff, 0xe3ffffcf, 0x9c7fff80, 0x03800001, - 0x000036c2, 0x402a8000, 0x1c9c3800, 0x09e4f580, 0x000f4240, 0x4d5ab5f8, 0x462e485a, 0x460c9000, - 0x46084637, 0xfa8bf002, 0xd0042800, 0x6ee06e26, 0x6e679000, 0x6d206ea5, 0x6d602800, 0x2800d027, - 0x4951d004, 0x63c82006, 0x62c64850, 0x28006d20, 0x494dd006, 0x31402001, 0x484c62c8, 0x61c63040, - 0x23114949, 0x630b3140, 0x30404848, 0x22016207, 0x6245634a, 0x6285638a, 0x62c563ca, 0x31804942, - 0x6305600a, 0x5d002045, 0xd0032808, 0x2800e00f, 0xe024d1d7, 0x2001493c, 0x62083140, 0x32404a3b, - 0x61c86115, 0x618860d5, 0x61486095, 0x7b206055, 0xd0012803, 0xd1062801, 0x30404833, 0x49336283, - 0x31409800, 0x46206188, 0xfa40f002, 0xd0062800, 0x2101482d, 0x62413040, 0x3040482c, 0x6da06147, - 0x6de02800, 0x2800d02a, 0x4927d005, 0x31402006, 0x48266008, 0x6da06306, 0xd0052800, 0x21044822, - 0x62413040, 0x63c64821, 0x2111481f, 0x62413040, 0x3140491e, 0x2201614f, 0x610d6202, 0x60cd61c2, - 0x608d6182, 0x604d6142, 0x2a037b22, 0x2a01d001, 0x2214d103, 0x98006102, 0xbdf86008, 0xd1d42800, - 0x2104bdf8, 0xd00f2800, 0x29037b01, 0x6c01d10b, 0x06493060, 0xda012900, 0xe003210f, 0x29007e41, - 0x211ed101, 0x21007601, 0x47704608, 0x62884908, 0x47702000, 0x6a894906, 0x20006001, 0x00004770, - 0x000010f1, 0x000130f1, 0x401f8180, 0x401f8380, 0x400f8000, 0x49fcb5f0, 0x4479b085, 0x466dc91e, - 0x4efac51e, 0x4df94ff9, 0x4cf84669, 0x37803640, 0x000335c0, 0xf9aaf003, 0x220d0609, 0x8381582b, - 0x00918b89, 0xfb42f000, 0x06496821, 0x43480e49, 0xf000e048, 0x6a37fb3b, 0x69314605, 0xf97ef003, - 0x2300463a, 0xffa8f002, 0x07c96b21, 0x2116d001, 0x2114e000, 0x1828434d, 0xbdf0b005, 0xfb26f000, - 0xe0676921, 0xe0002116, 0x43482114, 0xf000e7f4, 0x4604fb1d, 0x06456b30, 0x693f4638, 0x68010e6d, - 0xf0034620, 0x463af95b, 0xf0022300, 0x436cff85, 0x18206b31, 0x04d22203, 0xd0114011, 0x04d22201, - 0xd1004291, 0x49d20840, 0x4ad26b09, 0x22014011, 0x1a8903d2, 0x0212d006, 0xd1cd4291, 0xe7cb0880, - 0xe7f00880, 0xe7c70840, 0xfaf0f000, 0x6a384604, 0x0646682d, 0x6b390e76, 0xf0034620, 0x462af92f, - 0xf0022300, 0x4374ff59, 0x18206a39, 0x04d22203, 0xd0104011, 0x04d22201, 0xd1004291, 0x49bc0840, - 0x22016b09, 0x07890f89, 0x18890792, 0x0052d0d6, 0xd1a142d1, 0x0880e7d6, 0x6a28e7f1, 0x6a28e001, - 0x07800880, 0x58080f00, 0x48b3e796, 0xf000e794, 0x6a21fabd, 0xd0970789, 0x2000e794, 0xb510e78c, - 0x20014604, 0xff56f7ff, 0x394049a9, 0xd0092c00, 0xd0092c01, 0xd00e2c02, 0xd00f2c03, 0x21122000, - 0xbd104348, 0xe0016809, 0x0a096809, 0x0e890689, 0xffeaf002, 0x6809e7f3, 0xe7f70c09, 0x0e096809, - 0xb510e7f4, 0x69604c9d, 0x69a00180, 0x2103d512, 0x40080309, 0x2101d005, 0x42880309, 0x2000d005, - 0x2002e005, 0xff26f7ff, 0xf000e001, 0x6961fa7f, 0xe00f0ec9, 0x04892103, 0xd0134008, 0x04892101, - 0xd0131a40, 0xd0121a40, 0xd1094288, 0xf7ff2000, 0x6921ff11, 0x0f490749, 0xf0021c49, 0xbd10ffb5, - 0xbd102000, 0xf7ff2001, 0xbd10ff05, 0xf7ff2002, 0xbd10ffa6, 0x2800b510, 0xf002d001, 0x2101ff4e, - 0x0789487b, 0x497e6181, 0x03d26b0a, 0x2201d5fc, 0x61420412, 0x04096901, 0x6182d5fc, 0x2001bd10, - 0x07804973, 0x47706148, 0x49752210, 0xd0012800, 0x4770638a, 0x4770634a, 0x6b014871, 0x43112201, - 0x47706301, 0x6b01486e, 0x00490849, 0x47706301, 0x4604b510, 0xf7ff2002, 0x4965fecd, 0x2c003980, - 0x2c01d009, 0x2c02d009, 0x2c03d00e, 0x2000d00f, 0x43482112, 0x6b09bd10, 0x6b09e001, 0x06890a09, - 0xf0020e89, 0xe7f3ff61, 0x0c096b09, 0x6b09e7f7, 0xe7f40e09, 0x4c59b510, 0xf0030003, 0x0d17f867, - 0x362a120d, 0x403e3c39, 0x4a464442, 0x52504e4c, 0x5c5a5854, 0x0064605e, 0xff63f7ff, 0x0a896961, - 0x6960e011, 0xd50a0640, 0x06006960, 0x2001d503, 0xffbef7ff, 0x2002e005, 0xff31f7ff, 0xf7ffe001, - 0x6961ff50, 0x07490c09, 0x1c490f49, 0xff2cf002, 0xf7ffbd10, 0x6961ff46, 0x0f4904c9, 0xf0021c49, - 0x6961ff23, 0x0f890589, 0xf000e7ef, 0xbd10f9cf, 0x03c02001, 0x2000bd10, 0x2002e022, 0x2000e020, - 0x2001e004, 0x2002e002, 0x2003e000, 0xff90f7ff, 0x2008bd10, 0x2001e014, 0x2000e012, 0x2001e004, - 0x2002e002, 0x2003e000, 0xfef9f7ff, 0x2005bd10, 0x2006e006, 0x2007e004, 0x2003e002, 0x2004e000, - 0xfe48f7ff, 0x2000bd10, 0x7800bd10, 0x06402101, 0x03490e40, 0x481d1841, 0x68016001, 0xdafc2900, - 0x20014770, 0x03004919, 0x47706008, 0x21017800, 0x0fc007c0, 0x18410349, 0x63014814, 0x29006b01, - 0x4770dafc, 0x49112001, 0x63080300, 0x78004770, 0x078021c1, 0x01890f80, 0x480c1841, 0x69016101, - 0xdafc2900, 0x49094770, 0x61082000, 0x78004770, 0x078021c1, 0x01890f80, 0x48041841, 0x6a016201, - 0xdafc2900, 0x00004770, 0x000033b2, 0x400d8000, 0x400d8140, 0x00808000, 0x017d7840, 0x400fc000, - 0x400d8240, 0x200049ae, 0xe7eb6208, 0x6841b530, 0x008b2200, 0x089b49aa, 0x600b3180, 0x009b6883, - 0x610b089b, 0x23017801, 0x035b0649, 0x78400e49, 0x019d18c9, 0xd01c2802, 0x006c4ba2, 0xd0162804, - 0xd0122808, 0xd00e2810, 0x4b9f4321, 0x4c9d6b18, 0x402043e4, 0x63184310, 0x30404899, 0x6b016301, - 0xdafc2900, 0x461abd30, 0x4329e7ef, 0x4321e7fb, 0x4329e7f9, 0x2001e7e9, 0x03004991, 0x63083140, - 0xb570e7b0, 0x4b8e6841, 0x22000089, 0x33800889, 0x68816319, 0x00894c8c, 0x3c800889, 0x78016021, - 0x06492401, 0x0e490364, 0x19097840, 0x280201a5, 0x2403d01a, 0x006e07a4, 0xd0132804, 0xd00f2808, - 0xd00b2810, 0x48804331, 0x00a46b04, 0x431408a4, 0x62196304, 0x28006a18, 0xbd70dafc, 0xe7f24622, - 0xe7fb4329, 0xe7f94331, 0xe7ec4329, 0x49742001, 0x31800300, 0xe7756208, 0x78c27901, 0x07920789, - 0x0f920f09, 0x78024311, 0xd0022a00, 0x03522201, 0x78424311, 0xd0022a00, 0x05122201, 0x78804311, - 0xd0022800, 0x05402001, 0x48674301, 0x62013880, 0x29006a01, 0xe755dafc, 0x49632001, 0x39800300, - 0xe74f6208, 0xb5104b60, 0x681a3b40, 0x24bf00c0, 0x43a24084, 0x40842480, 0x601c4314, 0x0e890689, - 0x43114081, 0xbd106019, 0x39404957, 0x00c3680a, 0x40982080, 0x600a4302, 0x4b53e734, 0x3b80b510, - 0x00c06b1a, 0x408424bf, 0x248043a2, 0x43144084, 0x0689631c, 0x40810e89, 0x63194311, 0x494abd10, - 0x6b0a3980, 0x208000c3, 0x43024098, 0xe719630a, 0x4846b508, 0x22036801, 0x60014311, 0x68014844, - 0x43112202, 0x20006001, 0x48429000, 0x9900bf00, 0x91001c49, 0xd3f94281, 0x3940493b, 0x221f6a08, - 0x43900212, 0x43104a3c, 0x20016208, 0xb508bd08, 0x68014836, 0x43112203, 0x48386001, 0x22026801, - 0x60014311, 0x90002000, 0xbf004832, 0x1c499900, 0x42819100, 0x492cd3f9, 0x6a083940, 0x0212221f, - 0x4a2d4390, 0x62084310, 0xbd082001, 0x2200b508, 0x92004668, 0xfebbf7ff, 0x6b014829, 0x08490049, - 0x6b016301, 0x43990483, 0x60026301, 0x22636b01, 0x43110392, 0x20016301, 0xb508bd08, 0x46682200, - 0xf7ff9200, 0x481ffeb4, 0x00496b01, 0x63010849, 0x04436b01, 0x63014399, 0x6b016002, 0x03922263, - 0x63014311, 0xbd082001, 0x2000490d, 0x48146108, 0x04826b01, 0x63014311, 0x4909e6a4, 0x62082000, - 0x6b014810, 0x43110442, 0xe69b6301, 0x6b00480e, 0xd50106c0, 0xe695480d, 0x4448480d, 0xe6916800, - 0x400d8000, 0x00808000, 0x400d8140, 0x400fc080, 0x402e0140, 0x00061a80, 0x00001701, 0x402e0340, - 0x400d9000, 0x400da000, 0x400d8240, 0x016e3600, 0x00000004, 0x460cb570, 0xf0024606, 0x0005fa31, - 0x4622d10b, 0x32802301, 0x46302100, 0xf8e2f002, 0x28017c60, 0x2000d101, 0x46287420, 0xb570bd70, - 0x4605b08a, 0x466e2000, 0x200f7030, 0x90022401, 0x74329403, 0x32ff460a, 0x32719301, 0x46214623, - 0xf0024628, 0x4669f8c7, 0x94024628, 0xffd1f001, 0xbd70b00a, 0x2004b5ff, 0x460db083, 0xd0292900, - 0x36ff462e, 0x7b7036c1, 0xd0062800, 0x9a059b06, 0xf7ff9803, 0x2800ffd4, 0x7b30d11c, 0x3480462c, - 0xd10a2802, 0x30304620, 0x466bc887, 0x4620c307, 0xc80f3040, 0xc40f3430, 0x46293c40, 0x9a059b06, - 0xf0029803, 0x7b31f8c7, 0xd1032902, 0xcd0e466d, 0xc48e3430, 0xbdf0b007, 0xb089b5ff, 0x4616461d, - 0x9809460c, 0xffc6f7ff, 0xd1142800, 0x70084669, 0x200e2701, 0x90029703, 0x4622740e, 0x326132ff, - 0x4639463b, 0x98099501, 0xf874f002, 0x97024669, 0xf0019809, 0xb00dff7e, 0xb5ffbdf0, 0xb0832004, - 0x4696469c, 0xd0d52900, 0x35ff460d, 0x7b2835c1, 0x3480460c, 0xd10b2802, 0x30104620, 0x466ac889, - 0xc28969e6, 0x30204620, 0x3410c88d, 0x3c20c48d, 0x46724663, 0xf0029803, 0x7b29f8aa, 0xd1b92902, - 0xcd0e466d, 0xc44e3410, 0xb5f7e7b4, 0x4616b082, 0xd051000d, 0xd84f2e01, 0x34ff462c, 0x7a2034c1, - 0xd0002800, 0x28002001, 0x6c28d046, 0x0fc70640, 0xf0029802, 0x2e00fa5e, 0x7a20d02b, 0xd0092800, - 0x5d412046, 0x9802463a, 0xfa15f7ff, 0x98024629, 0xfda6f001, 0x28007ba0, 0x2100d003, 0xf0029802, - 0x466afa5a, 0x98022102, 0xfa55f7ff, 0xd0022f00, 0x08409800, 0xaa019000, 0x98022100, 0xfa4bf7ff, - 0x98019900, 0xfc40f002, 0x1c40210a, 0x08804348, 0x7a21e010, 0xd0072900, 0x9802463a, 0xf9ebf7ff, - 0x98024629, 0xfd7cf001, 0x28007ba0, 0x2101d0d9, 0xbf00e7d4, 0xd2fc1e40, 0xbdf0b005, 0xb089b5ff, - 0x460d4617, 0xf0014608, 0x4606fd43, 0x46292200, 0xf7ff9809, 0x463bff9a, 0x46294632, 0xf7ff9809, - 0x0004ff19, 0x2002d13f, 0x70084669, 0x24012009, 0x94039002, 0x5d412047, 0x30ff4628, 0x29003081, - 0x7c01d006, 0xd0032900, 0x91027c41, 0x91037c01, 0x97014669, 0x990c740e, 0x6c009105, 0x98029006, - 0x01002101, 0x32801942, 0x98099b03, 0xffb2f001, 0x94024669, 0xf0019809, 0x0004febc, 0x463bd113, - 0x46294632, 0xf7ff9809, 0x0004ff38, 0x20ffd10b, 0x5d4030d0, 0xd0062800, 0x4632463b, 0x98094629, - 0xff0af7ff, 0x98094604, 0xf9cdf002, 0x46292201, 0xf7ff9809, 0x4620ff4a, 0xb5f3e71d, 0x2600b08b, - 0x9d0c4669, 0x2101700e, 0x210b9103, 0x46699102, 0x2047740e, 0x46375d40, 0x28004634, 0x4628d009, - 0x308130ff, 0x29007d01, 0x7d41d003, 0x7d009102, 0x22009003, 0x980b990c, 0xff27f7ff, 0x950a3550, - 0x9009cd01, 0xd01a2800, 0x22004633, 0x980b990c, 0xfea0f7ff, 0xd13e0004, 0x96019802, 0x980c0101, - 0x180a9b03, 0x32802101, 0xf001980b, 0x2001ff53, 0x46699002, 0xf001980b, 0x0004fe5c, 0x9809d12b, - 0x18361c7f, 0xd3db2f04, 0xd1242c00, 0x90092000, 0x980c4606, 0x30ff9d0a, 0x900a30c1, 0x2f00cd80, - 0x2200d013, 0x990c9b09, 0xf7ff980b, 0x0004fec6, 0x980ad111, 0x28007bc0, 0x2200d007, 0x990c9b09, - 0xf7ff980b, 0x0004fe99, 0x9809d105, 0x19c01c76, 0x2e049009, 0x980bd3e2, 0xf955f002, 0x990c2201, - 0xf7ff980b, 0x4620fed2, 0xb5f7e6a5, 0x4617b08a, 0x4608460d, 0xfc6cf001, 0x22004606, 0x980a4629, - 0xfec3f7ff, 0x4632463b, 0x980a4629, 0xfe42f7ff, 0xd1390004, 0x97014669, 0x20057008, 0x90022401, - 0x740e9403, 0x5d402047, 0xd0092800, 0x30ff4628, 0x7b013081, 0xd0032900, 0x91027b41, 0x90037b00, - 0x21019802, 0x19420100, 0x9b033280, 0xf001980a, 0x4669fee1, 0x980a9402, 0xfdebf001, 0xd1130004, - 0x4632463b, 0x980a4629, 0xfe67f7ff, 0xd10b0004, 0x30d020ff, 0x28005d40, 0x463bd006, 0x46294632, - 0xf7ff980a, 0x4604fe39, 0xf002980a, 0x2201f8fc, 0x980a4629, 0xfe79f7ff, 0xe64c4620, 0xb08ab5f7, - 0x460d4617, 0xf0014608, 0x4606fc13, 0x46292200, 0xf7ff980a, 0x463bfe6a, 0x46294632, 0xf7ff980a, - 0x0004fde9, 0x4669d139, 0x70089701, 0x24012008, 0x94039002, 0x2047740e, 0x28005d40, 0x4628d009, - 0x308130ff, 0x29007f01, 0x7f41d003, 0x7f009102, 0x98029003, 0x01002101, 0x32801942, 0x980a9b03, - 0xfe88f001, 0x94024669, 0xf001980a, 0x0004fd92, 0x463bd113, 0x46294632, 0xf7ff980a, 0x0004fe0e, - 0x20ffd10b, 0x5d4030d0, 0xd0062800, 0x4632463b, 0x980a4629, 0xfde0f7ff, 0x980a4604, 0xf8a3f002, - 0x46292201, 0xf7ff980a, 0x4620fe20, 0xb5f0e5f3, 0x20044607, 0x461db089, 0x460e4614, 0xd00f2a00, - 0x46682124, 0xfa8ef002, 0x46692003, 0x20017008, 0x95089002, 0x96019003, 0x46389407, 0xfd59f001, - 0xbdf0b009, 0xb08fb5ff, 0x460c2000, 0x900b900a, 0x900d900c, 0x25016811, 0x2905461e, 0x6851d202, - 0xd3152940, 0x6c117425, 0x0f490249, 0xf002000b, 0x0d07fb7d, 0x050b0905, 0x000d0705, 0xe00b2702, - 0xe0092704, 0xe0072701, 0xe0052703, 0xe06d7420, 0x05098831, 0xd0690f0f, 0x90002000, 0x90024669, - 0x20037508, 0x95097108, 0x95049503, 0x2f019108, 0x2f02d007, 0x2f03d003, 0x2f04d02a, 0x48fdd104, - 0x48fce001, 0x900a3830, 0xaa0a2301, 0x980f4619, 0xfe00f001, 0x980fa901, 0xfd0bf001, 0xd1462800, - 0x01006830, 0xd0050f00, 0x040088b0, 0xd0010e01, 0x90000e00, 0x74202000, 0x30804620, 0xd00a2f01, - 0x2f022202, 0x2f03d010, 0x2f04d026, 0xe01bd12e, 0x300a48e8, 0x9900e7d7, 0xd427064a, 0x64024ae6, - 0x400120c3, 0xe01e2040, 0x078b9900, 0x4be3d41e, 0x64034311, 0x90000208, 0x75257425, 0x75602004, - 0x61a09800, 0xe0117465, 0x078b9900, 0x4bdad40e, 0x43113330, 0xe0076403, 0x060a9900, 0x4ad7d406, - 0x6402323d, 0x43012080, 0xe7e59100, 0xb0132000, 0xb5f7bdf0, 0x02402001, 0x2700b098, 0x46689001, - 0x24017407, 0x9702460d, 0x29009403, 0x48ccd072, 0xc84d4478, 0xc14da90d, 0x466a2003, 0xa8097010, - 0x20109007, 0x462a9008, 0x21013280, 0x98189b03, 0xfd90f001, 0x94024669, 0xf0019818, 0x2800fc9a, - 0x9809d158, 0xd1081c40, 0x1c40980a, 0x980bd105, 0xd1021c40, 0x1c40980c, 0x2210d007, 0xa80da909, - 0xf965f002, 0xd1452800, 0x2300e034, 0x4629461a, 0xf7ff9818, 0x2800fcaf, 0x2009d17b, 0x20029002, - 0x70084669, 0x462aa80d, 0x90052610, 0x960632ff, 0x21013211, 0x98189b03, 0xfd5cf001, 0x94024669, - 0xf0019818, 0x2800fc66, 0x2300d163, 0x4629461a, 0xf0019818, 0x2800fdac, 0x9002d15b, 0x46692003, - 0xa8097008, 0x96089007, 0xf0019818, 0x2800fc52, 0xe7c2d14f, 0x90162032, 0x90152000, 0x21406c28, - 0x64284308, 0x5d412046, 0x22012602, 0xf7fe9818, 0xe038ff22, 0x2400e03d, 0x94129411, 0x94149413, - 0x6d282101, 0x42880609, 0x488ed901, 0x488ee000, 0x498e9011, 0x1840b2f0, 0x2301498d, 0x90124308, - 0x2100aa11, 0xf0019818, 0x2003fd15, 0x94024669, 0xa8097008, 0x20109007, 0x98189008, 0xfc19f001, - 0xd0060004, 0xd0142f00, 0x2f00981a, 0xd0106006, 0x2210e010, 0xa80da909, 0xf8e9f002, 0xd00c2800, - 0x2f001c76, 0x9815d1f0, 0x1c409916, 0x42889015, 0x4c78d3c1, 0xb01b4620, 0x2701bdf0, 0xb5ffe7e4, - 0xb0824608, 0x9000305c, 0x68c8460b, 0x27013308, 0xda032800, 0x1ec0463a, 0xe0014082, 0x08c21c40, - 0x24ff9802, 0x9e026502, 0x68489201, 0x340136ff, 0x28403681, 0x6434d201, 0x8d18e00a, 0x0f020600, - 0x40904638, 0x03d22201, 0xd1004290, 0x64304620, 0x24004d61, 0x00424620, 0x7f1718d2, 0xd00d2f00, - 0x40ba2201, 0xd20142aa, 0x46844615, 0xd90542a2, 0x053f2701, 0xd20142ba, 0x46864614, 0x28041c40, - 0x6475d3e9, 0x98026534, 0x30c130ff, 0xd10142a5, 0xe0002201, 0x72422200, 0x98012201, 0x42900612, - 0x3140d92d, 0x28007e08, 0x9800d008, 0x79014460, 0x60019804, 0x44709800, 0xe0187901, 0x00404660, - 0x7f4018c0, 0x22dc2121, 0xd0022820, 0xd10528d8, 0x9804e002, 0xe0016001, 0x60029804, 0x00404670, - 0x7f4018c0, 0xd0022820, 0xd10528d8, 0x9805e002, 0xe0016001, 0x60029805, 0xb0062000, 0x4660bdf0, - 0x18c00040, 0x98047f41, 0x46706001, 0x18c00040, 0xe7ec7f41, 0xb08db5ff, 0x90052004, 0x460f980f, - 0x90033008, 0x305c980f, 0x20009009, 0x98109004, 0x02006800, 0x28010f00, 0x9803d105, 0x03006800, - 0x90040fc0, 0x2000d071, 0x99107338, 0x78094606, 0x070aab0b, 0x21460f12, 0x900055ca, 0x90062018, - 0x90072000, 0x4638aa0a, 0xf7ff990f, 0x2101ff48, 0x06096d38, 0xd9014288, 0x90062020, 0x88009810, - 0x0f000400, 0x4639d151, 0x9a0f9b10, 0xf7ff980d, 0x9005fdd9, 0xd1f52800, 0x68009803, 0xd51d0281, - 0x90072002, 0x7a009803, 0x0f4e0601, 0x0ec006c0, 0x0000e01c, 0x24010435, 0x20010401, 0x20020401, - 0x0000262c, 0x8a2004ee, 0x8a1804ed, 0x00040200, 0xa604b000, 0x00004e2a, 0x00ffffff, 0xd5060240, - 0x68809803, 0x0f4e0201, 0x0ec002c0, 0x980f9000, 0x30409a06, 0x49fc1dfc, 0x900834f9, 0xd0022a20, - 0x612048fa, 0x7e00e012, 0x28004bf9, 0x9809d03b, 0x68004af8, 0xd50105c5, 0xe00348f7, 0xd5320600, - 0x302248f3, 0x61206162, 0xe0a9e001, 0x20016161, 0x463d7338, 0x358048f1, 0x48f16328, 0x980a6128, - 0xb2c14af0, 0x04009806, 0x43114301, 0x65299001, 0xb2c9990b, 0x43114301, 0x01402023, 0x63206021, - 0x68009810, 0x0f010100, 0x9910d00f, 0x060a6849, 0xd00a0e12, 0x9904b2c8, 0x90002600, 0xd0212900, - 0x90000040, 0x6123e01e, 0x9904e7d0, 0xd0192900, 0xd1170f00, 0x28209806, 0x48d5d104, 0x60281c40, - 0x606848d9, 0x980d4639, 0xfaa4f7ff, 0x28009005, 0x466ad166, 0x980d4639, 0xfddbf7ff, 0x28009005, - 0x2600d1f6, 0x28189806, 0x2002d006, 0x98049007, 0xd0202800, 0xe00320ee, 0x28009804, 0x20edd00a, - 0x22406c39, 0x64394311, 0x43019901, 0x430148c7, 0xe0376029, 0x68009803, 0xd5030281, 0x89009803, - 0xe0030400, 0xd5040240, 0x68809803, 0x90020e00, 0x2003e01f, 0x9808e019, 0x28007e00, 0x9809d00a, - 0x06816800, 0x06c0d40a, 0x206cd513, 0x20009002, 0xe00e9007, 0x68009803, 0xd5010281, 0xe7e620ec, - 0xd5010240, 0xe7e2206c, 0x90022013, 0x46062000, 0x99029000, 0x43089801, 0x06099907, 0x49a94308, - 0x60284308, 0x463a9910, 0x32ff7809, 0x32c10609, 0x0f0b2000, 0x2b009201, 0x0f09d003, 0xd0042901, - 0x9800e06b, 0x90001980, 0x990fe049, 0x29406849, 0x9903d3f7, 0x058a6b89, 0x0309d5f3, 0x22050f09, - 0xd0014211, 0xe00b20a5, 0xd5090789, 0x9b104639, 0x980d9a0f, 0xff9ef000, 0x28009005, 0x2001d14d, - 0x220a9903, 0x04098f09, 0x42110e89, 0x4990d007, 0x67616721, 0x29209906, 0x498ed109, 0x2211e006, - 0xd03a4211, 0x6721498c, 0x498c6761, 0x210167a1, 0x2e009a01, 0xd0117351, 0x29009904, 0x2e01d033, - 0x2127d02e, 0x43080289, 0x06099900, 0x43080a09, 0x43084983, 0x48836068, 0xe01760a8, 0x28009800, - 0x9a04d00f, 0x2a004980, 0xb2c0d005, 0x497f1840, 0x60684308, 0xb2c0e00a, 0x497d1840, 0x60684308, - 0x487ce00b, 0x98046068, 0xd0062800, 0x20019901, 0x6c387388, 0x43082140, 0x98056438, 0xbdf0b011, - 0x09002126, 0x2e01e7ce, 0x2107d00c, 0x43080289, 0x06099900, 0x43080a09, 0x4308496f, 0x486f6068, - 0xe7ea60a8, 0x09002106, 0xb5f7e7f0, 0xb0984e6c, 0xd008000d, 0x466a2308, 0x98182100, 0xfc37f7ff, - 0xd1640004, 0x2404e001, 0x4966e061, 0x42889800, 0x4634d001, 0x4668e05b, 0x60287900, 0x79804668, - 0x280a1c40, 0x200ad900, 0x981a9016, 0x28002108, 0x0209d000, 0xaa029816, 0x981800c3, 0xfc17f7ff, - 0xd1440004, 0x46282164, 0xfeacf001, 0xe03b2600, 0xaa0200f0, 0x18835c11, 0x020079d8, 0x20ff180a, - 0x42820200, 0x4850d002, 0xd12c4282, 0x20022100, 0x1819020f, 0x43397909, 0xd5f91e40, 0x008778d8, - 0x2800981a, 0x0209d000, 0x020020ff, 0xd10c4282, 0xd9002f50, 0x462a2750, 0x3208463b, 0xf7ff9818, - 0x0004fbe6, 0x606fd113, 0x483fe00d, 0xd10a4282, 0x463b462a, 0x9818325c, 0xfbd9f7ff, 0xd1060004, - 0x20582101, 0x1c765541, 0x42869816, 0x4620d3c0, 0xb5f7e541, 0xb088460d, 0x46282103, 0x230873e9, - 0x71433040, 0x642b2358, 0x73292401, 0xd0012a00, 0x64292159, 0x210f71c4, 0x87c48781, 0x2001462e, - 0x024036ff, 0x64303681, 0x64700240, 0x46306530, 0x90073040, 0x46297244, 0xf7ff9808, 0x2800f91b, - 0x4822d172, 0x90002700, 0x97034821, 0x90012301, 0x466a9702, 0x98084619, 0xf9fcf001, 0x97039702, - 0x481c4f1a, 0xe0373780, 0x00002004, 0x08180402, 0x08200412, 0x00002204, 0x0a20043e, 0x00000406, - 0x24040405, 0x08000400, 0x00012404, 0x8a000400, 0x06ff06ff, 0x000006ff, 0x06000600, 0x32101e00, - 0xb2000200, 0x7c01a604, 0x00040200, 0xa604b000, 0x26043000, 0x00002404, 0x32000200, 0x7c012604, - 0x00004e27, 0x50444653, 0x0000ff84, 0x8b188720, 0xa3028f10, 0xa7048f10, 0x23019001, 0x2100466a, - 0x98089700, 0xf9b6f001, 0x02c02013, 0x23029006, 0x49feaa06, 0xf0009808, 0x2800fef9, 0x2308d114, - 0x2110aa04, 0xf0009808, 0x2800fedd, 0x9805d10c, 0xb28049f7, 0x98049005, 0xd1044288, 0x98052159, - 0x42880209, 0x48f3d002, 0xbdf0b00b, 0xaa042308, 0x98082127, 0xfec6f000, 0xd1f52800, 0x04009804, - 0x90040e00, 0x28093817, 0x9904d8ed, 0x40882001, 0x200f6528, 0x90060300, 0xaa062302, 0x98082100, - 0xfec4f000, 0xd1df2800, 0x49e3462c, 0x60213480, 0x606149e2, 0x60a149e2, 0x4ae349e2, 0x4fe44be3, - 0xc48e3410, 0x60274fdc, 0x60674fe2, 0x60a74fdc, 0xc40e3410, 0x60a74fe0, 0x60616022, 0x60e74fdf, - 0x61274fdd, 0x4fde35ff, 0xc58e3511, 0x34144fd2, 0x602f3fa0, 0x606f4fdb, 0xc48e4fdb, 0x4fd6c40e, - 0x602260a7, 0x4fd56061, 0x4fd360e7, 0x4cca6127, 0x3ca03d20, 0x4cd5602c, 0x4cd5606c, 0x462f60ac, - 0x37304cd1, 0xc70ec71e, 0x656c4ccb, 0x652964ea, 0x65ac4cca, 0x37144cc8, 0xc70e65ec, 0x66e949cd, - 0x72312102, 0x72722203, 0x22017131, 0x74317172, 0x74712109, 0x73312104, 0x73732305, 0x210b7531, - 0x99077571, 0xe77f730a, 0x2504b5f7, 0x4617b092, 0x2a00460c, 0x7878d004, 0x42887839, 0x2500d101, - 0x4620e087, 0x21083040, 0x71419011, 0x25037878, 0x28422601, 0x2841d001, 0x2502d103, 0x21049811, - 0x78787141, 0xd0012882, 0xd1002842, 0x20002621, 0x90014669, 0x70087408, 0x90022001, 0xa8092120, - 0xfd20f001, 0x200278f9, 0x29060242, 0x2907d00b, 0x2908d012, 0x2001d001, 0x0229e02b, 0x43131d8b, - 0x930931ff, 0x0229e005, 0x3366460b, 0x31994313, 0x43119309, 0xe01c910d, 0x460f0229, 0x376602b2, - 0x4317062b, 0x431f06b5, 0x432f46ac, 0x31992599, 0x4311042d, 0x4319432f, 0x22334665, 0x04524329, - 0x97094311, 0x2e21910d, 0x6c21d103, 0x43112240, 0x90036421, 0x20019911, 0x06017188, 0x498e6521, - 0x498e6021, 0x21036061, 0x73a17361, 0x31c921ff, 0x200a5508, 0x46216760, 0xf7fe9812, 0x0005ffab, - 0xaa09d117, 0x9b032101, 0xf0019812, 0x4669f893, 0xf0009812, 0x4605ff9e, 0x217d4881, 0x00c94448, - 0xf0016800, 0xe001fcc1, 0x1e40bf00, 0x28009011, 0x4628d1fa, 0xbdf0b015, 0xb09cb5f7, 0x460c981e, - 0x02286805, 0x28050f00, 0x2700d011, 0x22304975, 0xa80d4479, 0xf954f7fe, 0x0f000428, 0x0328900a, - 0x980a0f05, 0xd0042800, 0xd1132803, 0x2701e001, 0x2d00e7ec, 0x2d03d010, 0x2800d10c, 0x2003d00a, - 0x20107320, 0x981e6420, 0x02006800, 0x28040f00, 0xe019d018, 0xe1952604, 0xf7fe4668, 0x4606fbcb, - 0xf7fe2000, 0x2e00fbc3, 0x466ad106, 0x981c4621, 0xff2af7ff, 0xd1ee0006, 0x73202000, 0x64202010, - 0xe0022003, 0x64202050, 0x90092006, 0x4328980a, 0x2701d100, 0x990a4620, 0x29033040, 0x2101d008, - 0x46217141, 0xf7fe981c, 0x0006ff35, 0xe001d1d3, 0xe7f52108, 0x2d002000, 0x2f00d004, 0x2001d001, - 0x2002e000, 0xa90d0100, 0x23011842, 0x981c4619, 0xf810f001, 0x46692000, 0x75089002, 0x71082003, - 0x90032001, 0xa80b9004, 0xa9019008, 0xf000981c, 0x0006ff10, 0xa808d1af, 0x28c27b00, 0x2101d1ab, - 0x2d000409, 0xd01da808, 0x460a7c40, 0x40823830, 0x46206522, 0x30ff2201, 0x30810312, 0x11126442, - 0x65016402, 0x73202003, 0x64202010, 0x40472001, 0x46294620, 0x30c130ff, 0x35804625, 0x29009019, - 0xe078d002, 0xe7e07b80, 0x2803980a, 0x2101d173, 0x20027421, 0x82617460, 0x75622206, 0x23007521, - 0x22074669, 0x70ca700b, 0xd04a2f00, 0x466a2182, 0x61a07051, 0x6628481c, 0x3872481b, 0x481b6668, - 0x981e66a8, 0x06007800, 0xe0310f00, 0x00000555, 0x52005100, 0x00004e29, 0x8b1887a0, 0xb3068f10, - 0x0000a704, 0x87008700, 0x87aa8700, 0x87058700, 0x87708700, 0xb70b8f10, 0x87558700, 0x87028700, - 0x87a08700, 0xa3808f10, 0x87808700, 0x87008f10, 0x00008730, 0x87108700, 0x42464346, 0x56010400, - 0x0000000c, 0x00001c0c, 0x04000472, 0x20010400, 0xd0022803, 0x728b9919, 0x9919e01a, 0x72882001, - 0x2181e016, 0x7059466b, 0x4bfe61a0, 0x662b48fe, 0x48fe6668, 0x210166a8, 0x77214620, 0x70423020, - 0x48f87001, 0x38726321, 0x6768672b, 0x67a848f7, 0xf7fe9800, 0x48f6fadb, 0x48f66328, 0x1de06128, - 0x30f9990a, 0xd0032900, 0xd0162f00, 0xe0152321, 0x73212101, 0x602949f0, 0x606949f0, 0x1d8949ee, - 0x49ef6101, 0x49ec6141, 0x65293115, 0x31d049ea, 0x21236001, 0x63010149, 0x2301e084, 0xd0012f00, - 0xe0002122, 0x468e2102, 0xd0012f00, 0xe000212c, 0x911a210c, 0xd0012f00, 0xe0002129, 0x910a2109, - 0xd0012f00, 0xe0002128, 0x91002108, 0x4ad80299, 0x3a18069b, 0x469c188a, 0x4bda431a, 0x602a431a, - 0x23194672, 0x015b0292, 0x9b1a18d2, 0x069b4696, 0x4bd5431a, 0x606b4313, 0x029a9b0a, 0x009b23c1, - 0x920a18d2, 0x1c9a60aa, 0x4663188a, 0x4bcf431a, 0x4acf4313, 0x188a642b, 0x431a4663, 0x43134bcd, - 0x02122203, 0x188a622b, 0x431a4663, 0x061b2303, 0x626a431a, 0x4ac662aa, 0x320d9b0a, 0x188a62eb, - 0x431a4663, 0x43134bc4, 0x9b006103, 0x069b4672, 0x23c1431a, 0x4313049b, 0x61434abd, 0x188a321c, - 0x431a4663, 0x43134bbd, 0x4672652b, 0x22f7656a, 0x188d0092, 0x431d4663, 0x46724bb9, 0x6005431d, - 0x221b6042, 0x18890152, 0x4ab64663, 0x43114319, 0x2f006301, 0x6c20d003, 0x43082140, 0x99196420, - 0x73082002, 0xb01f4630, 0xb5f7bdf0, 0x49ae460c, 0x4617b0a6, 0x44792220, 0xf7fda81d, 0x6838ff91, - 0x0f000200, 0xd0092807, 0x90002000, 0x03006838, 0xd0050f00, 0x73202003, 0xe0142050, 0xe7f42001, - 0xf7fea801, 0x4605fa17, 0xf7fe2000, 0x2d00fa0f, 0xaa01d106, 0x98264621, 0xfd76f7ff, 0xd1140006, - 0x73202000, 0x46252010, 0x35402108, 0x71696420, 0x98264621, 0xfd8ef7fe, 0xd1f00006, 0x03006838, - 0xd0030f01, 0x28030f00, 0xe09ed003, 0xaa1d2301, 0x2301e001, 0x2101aa21, 0xf0009826, 0x2008fe6b, - 0x22007168, 0x9826a904, 0xfbbff7ff, 0xd1220006, 0xaa02ab03, 0x4620a904, 0xf971f7ff, 0x28009800, - 0x2050d103, 0x20036420, 0x46257320, 0x35804870, 0x48706328, 0x68396128, 0x0f020308, 0x30ff4620, - 0x900130c1, 0x2a0338c0, 0x0409d006, 0x2a030f0a, 0x0f09d002, 0xe068d01b, 0x62294974, 0x60294974, - 0x60694974, 0x64294974, 0x39dc4971, 0x49706529, 0x60013921, 0x0149213b, 0x496d6301, 0x610139eb, - 0x6141496e, 0x03006838, 0xd02f0f00, 0x2201e04a, 0x06126d21, 0xd3024291, 0x218e2220, 0x2218e001, - 0x9b0221c2, 0xb2db0412, 0x43134c65, 0x652b4323, 0x43119b03, 0x4313b2db, 0x43234a62, 0x60034311, - 0x21476101, 0x614101c9, 0x29009900, 0x495ed00a, 0x495e6029, 0x21236069, 0x63010149, 0x20019901, - 0xe0227388, 0x6029495a, 0xe7f34952, 0x46692000, 0x27067008, 0x208270cf, 0x98007048, 0xf966f7fe, - 0x74202001, 0x74612102, 0x61a121e7, 0x75207567, 0x48348260, 0x6628300f, 0x38724832, 0x48386668, - 0x66a81ec0, 0x20029901, 0x46307308, 0xbdf0b029, 0xb0b4b5f7, 0x90004847, 0x46156810, 0x0f000200, - 0x2809460c, 0x2600d01b, 0x22504943, 0xa81e4479, 0xfea6f7fd, 0x90022000, 0x30404620, 0x90012104, - 0x68287141, 0x04000301, 0x20100f05, 0x64200f0f, 0xd0062f00, 0xd01b2f02, 0xd01c2f03, 0x2601e166, - 0xa804e7e2, 0xf926f7fe, 0x20009000, 0xf91ef7fe, 0x28009800, 0xaa04d107, 0x98344621, 0xfc84f7ff, - 0x28009000, 0x9901d1ea, 0x71482001, 0xe0002000, 0x73202003, 0x2003e008, 0x20087320, 0x2e009901, - 0xd1017148, 0x90022001, 0xd0032d00, 0xd0012d02, 0xd1d32d03, 0x43284638, 0x2601d100, 0xd03f2d02, - 0xe03b2d03, 0x04000472, 0x04020400, 0x20010400, 0x00000406, 0x24040405, 0x0820040c, 0x24043308, - 0x00002004, 0x03110000, 0x03060000, 0x03f90000, 0x00000305, 0x03fa0000, 0x03ed0000, 0x03de0000, - 0x03230000, 0x039f0000, 0x000018b6, 0xa7040705, 0x8b2007fd, 0xa704b306, 0x00000706, 0x0000a304, - 0x08000400, 0x0b000400, 0x0b2004fc, 0x27043306, 0x8b2004fd, 0x00004e29, 0x00001700, 0xe004d002, - 0xe0002004, 0x99012008, 0x21407148, 0x2e006c20, 0x4388d001, 0x4308e000, 0x46216420, 0xf7fe9834, - 0x9000fc39, 0xd18d2800, 0xd0082e00, 0xd0022f02, 0xd10c2f03, 0x2001e001, 0x2002e009, 0x2f02e007, - 0x2f03d002, 0xe001d103, 0xe0002003, 0x01002004, 0x1842a91e, 0x46192301, 0xf0009834, 0xa905fd0b, - 0x98349a02, 0xfa61f7ff, 0x28009000, 0xab33d17e, 0xa905aa32, 0xf7ff4620, 0x2003f812, 0x46207320, - 0x49fd3080, 0x49fd6301, 0x2e006101, 0x2302d001, 0x2322e000, 0xd0012e00, 0xe000210c, 0x468e212c, - 0xd0012e00, 0xe0002109, 0x91022129, 0xd0012e00, 0xe0002208, 0x07a92228, 0x92040d8f, 0x97014639, - 0x099207aa, 0x069b370b, 0x469c4317, 0x4bec431f, 0x6007431f, 0x1d0f4673, 0x431f029b, 0x43179b02, - 0x431f069b, 0x23019302, 0x431f049b, 0x460f6047, 0x43173720, 0x431f4663, 0x46964be1, 0x6507431f, - 0x37d8460f, 0x46634317, 0x4bdd431f, 0x1de3431f, 0x601f33f9, 0x43171c8f, 0x43174662, 0x43174ad8, - 0x460f611f, 0x37809a04, 0x43170292, 0x02922201, 0x615f3160, 0x27024311, 0x2d026319, 0x2d03d001, - 0x9901d10f, 0x1d494673, 0x9b024319, 0x4bcd4319, 0x62014319, 0x1d899901, 0x22ff4311, 0x640132cd, - 0x21005517, 0x2d0261a1, 0xe000d004, 0x2d03e03e, 0xe005d003, 0x04922201, 0x2201e001, 0x61a204d2, - 0xd0102e00, 0x23806c22, 0x2301431a, 0x22796422, 0x4abd5513, 0x4abd6602, 0x20016642, 0x2d007420, - 0x7467d007, 0x2301e006, 0x05db69a2, 0x61a2431a, 0x7461e7ef, 0x75622206, 0x82607520, 0x73014668, - 0xd0082e00, 0xd0022d02, 0xd0022d03, 0x2041e007, 0x2081e012, 0x2d02e010, 0x2d03d00b, 0x7341d00b, - 0x46692008, 0x980373c8, 0xffc0f7fd, 0xb0379800, 0x2042bdf0, 0x2082e000, 0x73484669, 0xb5f7e7f0, - 0x46162704, 0x2900460c, 0x2e00d04d, 0x01f9d04b, 0xf0014620, 0x2101f867, 0x35404625, 0x060871a9, - 0x489b6520, 0x489b6020, 0x20036060, 0x73a07360, 0x30c920ff, 0x68305501, 0x0f000200, 0xf0010003, - 0x060af965, 0x17110c06, 0x231d1d17, 0x46323023, 0x98004621, 0xf8d6f000, 0x2201e001, 0x0007e003, - 0xe01ed018, 0x46212200, 0xf7ff9800, 0xe7f6f9d2, 0x46214632, 0xf7ff9800, 0xe7f0fb7f, 0x46214632, - 0xf7ff9800, 0xe7eafd42, 0x46214632, 0xf7ff9800, 0xe7e4fe1f, 0xf7fd4620, 0x7830ff54, 0x0f000700, - 0x200171a8, 0x46387128, 0xb5ffbdfe, 0xb0812004, 0x2900460f, 0x463dd01e, 0x358135ff, 0x42496c69, - 0x4014460c, 0x425218d2, 0x21ff400a, 0x5dc931ca, 0x29004256, 0x6d29d10c, 0xd0092900, 0x4622e02a, - 0x98014639, 0xfcb1f7fe, 0xd1032800, 0x190c6c69, 0xd3f442b4, 0xbdf0b005, 0x46206d29, 0xd00e4388, - 0x1b322000, 0xd00c2800, 0xd80a4291, 0x46394622, 0xf7fe9801, 0x2800fcf3, 0x6d29d1ec, 0x2001e009, - 0x4622e7ef, 0x98014639, 0xfc8ff7fe, 0xd1e12800, 0x190c6c69, 0xd3df42b4, 0xb5ffe7dc, 0x2004b089, - 0x461f9c12, 0x29004616, 0x2e00d022, 0x2c00d020, 0x4608d01e, 0xf8ecf000, 0x466a2103, 0x21017011, - 0x21009103, 0x74109102, 0x42ac4d4b, 0x4625d800, 0x97014669, 0x95089607, 0xf0009809, 0x2800fa8a, - 0x08a9d106, 0x1b640089, 0x198e197f, 0xd1eb2c00, 0xbdf0b00d, 0xb08eb570, 0x2100460c, 0x9100910c, - 0x910d910b, 0x9102466a, 0x75114606, 0x71102003, 0x95032501, 0x95094839, 0x900a9208, 0x9504462b, - 0x4629aa0a, 0xf0004630, 0xa901fb55, 0xf0004630, 0x2800fa60, 0x9900d114, 0x401122f7, 0x040a4b2a, - 0x18d33310, 0x22ff9100, 0x32617425, 0x75255113, 0x7562220e, 0x210461a1, 0x34ff7461, 0x73e534c1, - 0xbd70b00e, 0x4607b5f0, 0xb0a92000, 0x4616460d, 0x49232404, 0x90269025, 0x22309027, 0x90284479, - 0xf7fda819, 0x6830fc0d, 0x0f000300, 0x2104d158, 0x55412045, 0x491b4628, 0x60013080, 0x6041491a, - 0x46384629, 0xfa26f7fe, 0xd1490004, 0x06007830, 0x28010f00, 0x1de8d10e, 0x30f94914, 0x67416701, - 0x67811409, 0x461a2300, 0x46384629, 0xfa27f7fe, 0xd1350004, 0xe01b6830, 0x00000406, 0x24040405, - 0x00200400, 0x00040400, 0x04000471, 0x00002003, 0x42464346, 0x56010400, 0x0000ffff, 0x24010485, - 0x00001150, 0x08180403, 0x00012404, 0x06ff06ff, 0x0f000300, 0xa9190100, 0x23011842, 0x46384619, - 0xfad8f000, 0x46692200, 0xf7ff4638, 0x0004f82e, 0x4633d106, 0x4629466a, 0xf7fe4638, 0x4604fe6b, - 0xe4f34620, 0xb089b530, 0x466d2403, 0x2501702c, 0x24000049, 0x91019503, 0x466d9402, 0x4669742c, - 0x92079308, 0xf9c5f000, 0xbd30b009, 0xb089b530, 0x466d2402, 0x2401702c, 0x91010049, 0x94039402, - 0x74292100, 0x93064669, 0xf0009205, 0xe7ebf9b2, 0x07406c00, 0x2001d501, 0x20004770, 0x6c004770, - 0xd5010680, 0x47702001, 0x47702000, 0x07c06c00, 0x2001d000, 0x6c004770, 0xd5010700, 0x47702001, - 0x47702000, 0x07806c00, 0x2001d501, 0x20004770, 0x6c004770, 0xd5010640, 0x47702001, 0x47702000, - 0xb085b5f3, 0x2404460e, 0xf0009805, 0x0005fcce, 0x2e00d07e, 0x7b30d07c, 0xd8792803, 0xd00a2800, - 0xd0082801, 0xd0062802, 0xd1042803, 0xf7ff4630, 0x2800ffd9, 0x20ffd002, 0xe00c3001, 0x2102aa03, - 0xf7fd9805, 0x49fefc98, 0x42889803, 0x6c30d306, 0xd4030600, 0x90002079, 0xe0219001, 0x00602400, - 0x31601981, 0x7e0f7e48, 0xd10b2800, 0x43472064, 0x214bd01d, 0xf0004638, 0x214bfe77, 0x42b94341, - 0x1c40d200, 0x283f213f, 0x4608d900, 0x0c400680, 0x30ff00a2, 0x46693001, 0x50881c64, 0xd3de2c02, - 0x22026828, 0x28000780, 0x2000da1c, 0x4630e01e, 0xff9ff7ff, 0x46024607, 0x9805a902, 0xfc86f7fd, - 0x990248e0, 0xd0092f00, 0xfe4ef000, 0x217d0880, 0x434800c9, 0xf000214b, 0xe7d2fe47, 0xfe44f000, - 0xe7f40840, 0x20016829, 0x60294311, 0x29006d31, 0x6d71d102, 0xd0022900, 0x9b0021c0, 0x6db1514b, - 0xd1022900, 0x29006df1, 0x21c4d004, 0xe0009b01, 0x514be006, 0xd0022800, 0x43906828, 0x24006028, - 0xb0074620, 0xb5f8bdf0, 0x20044607, 0x460e461c, 0xd0162f00, 0xd0142a00, 0xd0122c00, 0x48c14611, - 0xfe12f000, 0x46054601, 0x46304361, 0xfe0cf000, 0x1c40e000, 0x43694601, 0x42b14361, 0x6038d3f9, - 0xbdf82000, 0xb085b5f0, 0x460e4db7, 0x95004607, 0xf0009501, 0x0004fc1a, 0x2e00d02b, 0xaa02d029, - 0x46382102, 0xfbf7f7fd, 0x2101aa03, 0xf7fd4638, 0x2601fbf2, 0x02b64fad, 0x46394633, 0x9a024668, - 0xffc1f7ff, 0x46394633, 0x9a03a801, 0xffbbf7ff, 0x42a89800, 0x9500d900, 0x42a89801, 0x9501d900, - 0x99019800, 0xb2890400, 0x60604308, 0xb0052000, 0x2004bdf0, 0xb5f3e7fb, 0x2000b087, 0x460c9000, - 0x98072504, 0xfbe1f000, 0x28009003, 0x2c00d054, 0x4620d052, 0x46273040, 0x37509005, 0x30ff2600, - 0x90023041, 0x00b26838, 0x98030a81, 0x90011810, 0x7ba06601, 0x06c51d3f, 0x0eed7b60, 0x0d8006c0, - 0x7be04305, 0x0c400700, 0x46204305, 0xfed3f7ff, 0xd0022800, 0x02802001, 0x6f604305, 0xd00d2800, - 0x2102aa04, 0xf7fd9807, 0x2301fb96, 0x46686f61, 0xf7ff9a04, 0x9800ff68, 0x43050400, 0x67059801, - 0x79c09805, 0xd00e2800, 0x7c009802, 0xd00a0741, 0x22079902, 0x03407c49, 0x0d090709, 0x18800352, - 0x4308b280, 0x2009e001, 0x99010200, 0x60083180, 0x2e041c76, 0x2500d3b6, 0xb0094628, 0x4602bdf0, - 0x2004b510, 0xd0212a00, 0xd01f2900, 0x5c402044, 0xd10c2801, 0x084368d0, 0x2040005b, 0x46084303, - 0xfe76f7ff, 0xd0012800, 0x43032001, 0x68d060d3, 0x43082120, 0x4b5e60d0, 0x00812000, 0x6a0c1889, - 0x620c401c, 0x28031c40, 0x2000d3f7, 0xb510bd10, 0xfb5bf000, 0xd00b2800, 0x23012100, 0x008a07db, - 0x32801812, 0x431c6814, 0x1c496014, 0xd3f62904, 0xb5febd10, 0x20044605, 0x460e9000, 0xf0004628, - 0x0004fb44, 0x2e00d07e, 0x7830d0fc, 0xd8792803, 0x90017c30, 0x46202700, 0xfb3ff000, 0xf7ff4628, - 0x6960ffd6, 0x4308211e, 0x46256160, 0x68703580, 0x78306228, 0xd0022802, 0xd0022803, 0x8b30e003, - 0x8c30e000, 0x7b31b287, 0x1e497a30, 0x07490700, 0x09490b00, 0x99014308, 0x430807c9, 0x62684338, - 0x28037830, 0x69f0d14b, 0x07836a32, 0x2340d14a, 0x469e211c, 0x6bab63a9, 0x430b2101, 0x6bab63ab, - 0xd1fc07db, 0x430b6b2b, 0xe036632b, 0x31f91de1, 0x45724673, 0x6967d30f, 0x06bf089b, 0xe029d402, - 0xc080c980, 0xd2fb1e5b, 0x1a524671, 0x23206961, 0x61614319, 0x6f2be01e, 0x0d5b061b, 0xd2034293, - 0xc908e018, 0xc0081f12, 0xd2fa2a04, 0xd0102a00, 0x91016809, 0x468ca901, 0x23004601, 0x4667e007, - 0x700f783f, 0x1c7f4667, 0x46bc1c49, 0x42931c5b, 0x2200d3f5, 0x07096961, 0x2a00d401, 0x7830d1c6, - 0xe0002802, 0xd001e062, 0xd1482801, 0x69b26971, 0xd15b0788, 0x46842040, 0x63e8201c, 0xe0096be8, - 0x05f5e100, 0x3b9aca00, 0x0000ffff, 0x1dcd6500, 0xfcf0ff00, 0x43182301, 0x6be863e8, 0xd1fc07c0, - 0xe02a4686, 0x30ff4620, 0x30816963, 0xd521065b, 0x089b4663, 0xd2024562, 0xc980e00e, 0x1e5bc080, - 0x4660d2fb, 0xe0091a12, 0xdd032a00, 0xc080c980, 0xe0011f12, 0xc0802700, 0xd2f51e5b, 0x28004670, - 0x6b28d104, 0x43182301, 0x469e6328, 0x23406960, 0x61604318, 0x07006960, 0x2a00d401, 0x7830dcd2, - 0xd1032800, 0x21016b28, 0x63284308, 0xf0004620, 0x6960fa74, 0xd50b0700, 0x01006e68, 0x280e0f00, - 0x48fed001, 0x48fde001, 0x90001e40, 0xbdfe9800, 0xe7fa2000, 0x460eb5f8, 0x461f2104, 0x91004615, - 0xfa53f000, 0xd0230004, 0xd0212d00, 0x19f22100, 0x23104149, 0x1a9a2000, 0xd3194188, 0xf0004620, - 0x4aeffa4c, 0x200261a2, 0x19f161e0, 0x008b00b0, 0x19090081, 0x31ff31ff, 0xe0023102, 0xc140cd40, - 0x42981c40, 0x61a2d3fa, 0x61e02001, 0x90002000, 0xbdf89800, 0x4604b570, 0xb08a2004, 0xd0242900, - 0x466e2000, 0x20037030, 0x90022501, 0x74329503, 0x93012047, 0x28005c40, 0x4608d009, 0x308130ff, - 0x2a007a02, 0x7a42d003, 0x7a009202, 0x98029003, 0x01009b03, 0x21011842, 0x32804620, 0xffaaf7ff, - 0x46204669, 0xf7ff9502, 0xb00afeb4, 0xb5ffbd70, 0xb0912004, 0x900e460d, 0xd0792900, 0x30404628, - 0x21018f82, 0x4094460c, 0x93028fc2, 0x22039200, 0x711a466b, 0x91039104, 0x9108a90c, 0x29009913, - 0x2108d001, 0x2104e000, 0x99139109, 0x79c07519, 0xd0092800, 0x30ff4628, 0x79013081, 0xd0032900, - 0x91037941, 0x90047900, 0x9b049803, 0x19420100, 0x99033280, 0xf7ff9811, 0x6f2dff6d, 0xd0012d00, - 0xe0002001, 0x26002000, 0xa901900f, 0xf7ff9811, 0x900efe70, 0xd13b2800, 0x28009813, 0xa90ad019, - 0xab0ca80b, 0x781f2208, 0x785f700f, 0x1c407007, 0x1e921c49, 0x2a001c9b, 0x9800d1f5, 0x2800990b, - 0xd004980a, 0x46214008, 0xd10a4381, 0x4308e00e, 0x9800e00a, 0xd0062800, 0x4620990c, 0x28004388, - 0x2701d004, 0x980ce003, 0xe7f84020, 0x980f2700, 0xd00b4207, 0x43304628, 0x207dd00d, 0x210000c0, - 0xf9aef7fd, 0x43c02000, 0x41461e6d, 0xd1bc2f00, 0xb015980e, 0x4889bdf0, 0x900e1c40, 0xb5f7e7f8, - 0x460db08a, 0x980a2604, 0xf96ff000, 0xd0540007, 0xd0522d00, 0x46692001, 0x980c7008, 0x20009001, - 0x20047408, 0x90062400, 0x194200a0, 0x30204610, 0x29007841, 0x2301d03e, 0x59db025b, 0x0f9b059b, - 0x192bd003, 0x2b027f5b, 0x9102d034, 0x32307800, 0x90039205, 0x46292200, 0x980a9b0c, 0xff1af7ff, - 0xd12b2800, 0x21019802, 0x19420100, 0x9b033280, 0xf7ff980a, 0x2001fedf, 0x46699002, 0xf7ff980a, - 0x0006fde8, 0x8a68d11a, 0xd10e2800, 0x7f491929, 0xd00a2902, 0xd0082903, 0x46292200, 0x980a9b0c, - 0xff25f7ff, 0xd1090006, 0x2164e004, 0x21004348, 0xf946f7fd, 0x2c031c64, 0x4630d3b6, 0xbdf0b00d, - 0xb087b5f3, 0x2604460d, 0xf0009807, 0x0004f90e, 0x2d00d07e, 0x7c28d0fc, 0xd1022800, 0x28007f28, - 0x6c28d009, 0xd40406c0, 0xf7ff4628, 0x2800fc22, 0x2001d001, 0x2000e000, 0x494a9003, 0x42886828, - 0x9807d166, 0xf87ff7fd, 0x98074629, 0xf962f7fd, 0x30404628, 0x90029903, 0xd0022900, 0x21012200, - 0x4628e005, 0xfc05f7ff, 0x98024602, 0x98077981, 0xf871f7fd, 0xf7fd9807, 0x6820f85e, 0x43b02602, - 0x46206020, 0xf8c9f000, 0x43306820, 0x68206020, 0x40084935, 0x79499902, 0xd1012908, 0x43080289, - 0x43084932, 0x07897b29, 0x43010e89, 0x46296021, 0xf7ff9807, 0x68a0fc97, 0x03c92101, 0x60a04388, - 0xf7ff4628, 0x2800fbc3, 0x68a0d004, 0x04c92101, 0x60a04308, 0x46204629, 0xfd21f7ff, 0x98074629, - 0xfcb9f7ff, 0x98074629, 0xfbcaf7ff, 0x21026820, 0x60204388, 0xf0004620, 0x4628f890, 0x30507c29, - 0x29009004, 0x9807d01c, 0x20049005, 0xe0002100, 0x9e04e05d, 0x460f9100, 0x9101ce02, 0xd00a2900, - 0x9a004629, 0xf0009805, 0x2800f890, 0x9a01d106, 0x18899900, 0x1c7f9100, 0xd3ed2f04, 0xd1460006, - 0x28007f28, 0x9807d027, 0x20049005, 0xd0202d00, 0x9e042100, 0x460f9100, 0xe009ce02, 0x00001b59, - 0x5af05af0, 0x42464346, 0x0000df0f, 0xffff0000, 0x29009101, 0x4629d00a, 0x98059a00, 0xfedff7ff, - 0xd1062800, 0x99009a01, 0x91001889, 0x2f041c7f, 0x0006d3e2, 0x9803d11b, 0xd0172800, 0x26026820, - 0x60204330, 0xf7ff4628, 0x4602fb64, 0x79819802, 0xf7fc9807, 0x4629ffd0, 0xf7ff9807, 0x4629fc13, - 0xf7ff9807, 0x6820fb5d, 0x602043b0, 0x46302600, 0xb510e4a3, 0xf829f000, 0xd0032800, 0x6e013080, - 0xd5fc0789, 0xb510bd10, 0xf81ff000, 0xd0012800, 0xf813f000, 0xb570bd10, 0xf000460d, 0x0004f816, - 0xf000d00a, 0x2001f81a, 0x682102c0, 0xd0012d00, 0xe0004301, 0x60214381, 0x6801bd70, 0x43112201, - 0x68016001, 0xd1fc07c9, 0x46014770, 0x29002000, 0x4830d102, 0x68004478, 0x30804770, 0x07c96e01, - 0x6e01d0fc, 0xd5fc0789, 0xb5f04770, 0x4616b089, 0x4607460c, 0xf7ff2504, 0x2800ffe8, 0x2c00d048, - 0x30ffd046, 0x300230ff, 0x05806800, 0xd0020f80, 0x28027c60, 0x2501d025, 0x700d4669, 0x7d609601, - 0x7d209002, 0x20009003, 0x46207408, 0x90053018, 0x90062004, 0x22004633, 0x46384621, 0xfd9af7ff, - 0x21019802, 0x19020100, 0x32804638, 0xf7ff9b03, 0x4669fd61, 0x95024638, 0xfc6bf7ff, 0xd1170005, - 0x2500e001, 0x8a61e014, 0xd10c2900, 0x28027c60, 0x2803d009, 0x4633d007, 0x46212200, 0xf7ff4638, - 0x4605fda6, 0x2064e004, 0x21004348, 0xffc8f7fc, 0xe4124628, 0x00000708, 0x88014843, 0x07492204, - 0xda022900, 0x43918801, 0x48408001, 0x07498801, 0x8801d502, 0x80014391, 0x493d483e, 0x493e6041, - 0x68016081, 0x43912280, 0x43112220, 0x483b6001, 0x07c96901, 0x6901d003, 0x00490849, 0x47706101, - 0x4c37b5f8, 0x4a376960, 0x01804937, 0x69a0d518, 0x031b2303, 0xd0054018, 0x03122201, 0xd00a4290, - 0xe0092000, 0x07806910, 0x2016d001, 0x2014e000, 0x4348492d, 0x4608e000, 0x00896961, 0xe0290f49, - 0x4b296810, 0x0e400640, 0x08474358, 0x07c06b10, 0x2516d001, 0x2514e000, 0x43454823, 0x30404821, - 0x69006a06, 0xfa1af000, 0x23004632, 0xf844f000, 0x194069a1, 0x40114a1d, 0x2201d011, 0x4b1c0492, - 0xd0161a89, 0xd0171a89, 0xd1074291, 0x07416920, 0x46380f49, 0xf0001c49, 0xe000f907, 0x69612000, - 0x0f4904c9, 0xf0001c49, 0x4912f8ff, 0x60084449, 0x6819bdf8, 0xe0000c09, 0x06896819, 0xf0000e89, - 0x2112f8f3, 0xe7ea4348, 0x400b8000, 0x400d0000, 0xd928c520, 0x400bc000, 0x0000ffff, 0xe000e000, - 0x400fc000, 0x400d8000, 0x016e3600, 0x000c0000, 0x400d8100, 0x0000000c, 0x4605b5fe, 0x460c4610, - 0xd0734318, 0x468c46ae, 0x1aad2000, 0x419c4601, 0x4666d367, 0x24012700, 0x1ab6463d, 0xd302419d, - 0x463a4613, 0x46652421, 0x042f4676, 0x433e0c36, 0x1ab60c2d, 0xd304419d, 0x041b0c15, 0x0412432b, - 0x46653410, 0x062f4676, 0x433e0a36, 0x1ab60a2d, 0xd304419d, 0x021b0e15, 0x0212432b, 0x46653408, - 0x072f4676, 0x433e0936, 0x1ab6092d, 0xd304419d, 0x011b0f15, 0x0112432b, 0x46651d24, 0x07af4676, - 0x433e08b6, 0x1ab608ad, 0xd304419d, 0x009b0f95, 0x0092432b, 0x46651ca4, 0x07ef4676, 0x433e0876, - 0x1ab6086d, 0xd31a419d, 0x415b1892, 0xe0161c64, 0x46761800, 0x41494665, 0x419d1ab7, 0x90009101, - 0x4660d309, 0x41981ab1, 0x4684468e, 0x99019800, 0x1c402500, 0x07dd4169, 0x432a0852, 0x1e64085b, - 0x4672d5e6, 0xb0034663, 0xe7ffbdf0, 0x46012000, 0x46c046c0, 0x4623462a, 0xb510e7f5, 0xf0002000, - 0x46c0f907, 0x200146c0, 0xf8fcf000, 0x4603bd10, 0x430bb510, 0xd10f079b, 0xd30d2a04, 0xc910c808, - 0x42a31f12, 0xba18d0f8, 0x4288ba21, 0x2001d901, 0x2000bd10, 0xbd1043c0, 0xd0032a00, 0xd00307d3, - 0xe0071c52, 0xbd102000, 0x780c7803, 0x1c491c40, 0xd1071b1b, 0x780c7803, 0x1c491c40, 0xd1011b1b, - 0xd1f11e92, 0xbd104618, 0xc004e001, 0x29041f09, 0x078bd2fb, 0x8002d501, 0x07c91c80, 0x7002d000, - 0x29004770, 0x07c3d00b, 0x7002d002, 0x1e491c40, 0xd3042902, 0xd5020783, 0x1c808002, 0xe7e31e89, - 0xe7ee2200, 0xe7df2200, 0x09032200, 0xd32c428b, 0x428b0a03, 0x2300d311, 0xe04e469c, 0x430b4603, - 0x2200d43c, 0x428b0843, 0x0903d331, 0xd31c428b, 0x428b0a03, 0x4694d301, 0x09c3e03f, 0xd301428b, - 0x1ac001cb, 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152, 0xd301428b, 0x1ac0014b, 0x09034152, - 0xd301428b, 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb, 0x08834152, 0xd301428b, 0x1ac0008b, - 0x08434152, 0xd301428b, 0x1ac0004b, 0x1a414152, 0x4601d200, 0x46104152, 0xe05d4770, 0xd0000fca, - 0x10034249, 0x4240d300, 0x22004053, 0x0903469c, 0xd32d428b, 0x428b0a03, 0x22fcd312, 0xba120189, - 0x428b0a03, 0x0189d30c, 0x428b1192, 0x0189d308, 0x428b1192, 0x0189d304, 0x1192d03a, 0x0989e000, - 0x428b09c3, 0x01cbd301, 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0, 0x428b0943, 0x014bd301, - 0x41521ac0, 0x428b0903, 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301, 0x41521ac0, 0x428b0883, - 0x008bd301, 0x41521ac0, 0x0843d2d9, 0xd301428b, 0x1ac0004b, 0x1a414152, 0x4601d200, 0x41524663, - 0x4610105b, 0x4240d301, 0xd5002b00, 0x47704249, 0x105b4663, 0x4240d300, 0x2000b501, 0x46c046c0, - 0x0000bd02, 0x20184901, 0xe7febeab, 0x00020026, 0xf000b510, 0xf000f80b, 0xbd10f802, 0xb5104770, - 0xd0012800, 0xffeef7ff, 0x0000bd10, 0x2100b510, 0xf000a002, 0x2001f813, 0x0000bd10, 0x41474953, - 0x3a545242, 0x6e624120, 0x616d726f, 0x6574206c, 0x6e696d72, 0x6f697461, 0x0000006e, 0x4605b570, - 0x200a460c, 0x1c6de000, 0xf812f000, 0xd0062d00, 0x28007828, 0xe002d1f7, 0xf0001c64, 0x2c00f809, - 0x7820d002, 0xd1f72800, 0xf000200a, 0xbd70f801, 0x4669b508, 0x20037008, 0xbd08beab, 0x0c04b5f8, - 0x4626b28b, 0x435eb282, 0x46100c0d, 0x43580c37, 0x19800436, 0x41792100, 0x436e4616, 0x04360c37, - 0x41791980, 0x436e4626, 0xbdf81989, 0x4674b430, 0x78251e64, 0x42ab1c64, 0x461dd200, 0x005b5d63, - 0xbc3018e3, 0x00004718, 0x08220000, 0x06180816, 0x0612041e, 0x0411060e, 0x0216060c, 0x06180000, - 0x060c0416, 0x0312021e, 0x01210216, 0x0116011a, 0x017d7840, 0x02faf080, 0x05f5e100, 0x07735940, - 0x33221100, 0x77665544, 0xbbaa9988, 0xffeeddcc, 0x0818045a, 0x24ff3008, 0x00000000, 0x00000000, - 0x0918055a, 0x25ff3108, 0x00000000, 0x00000000, 0x0a18065a, 0x26ff3208, 0x00000000, 0x00000000, - 0x2403049f, 0x00000000, 0x00000000, 0x00000000, 0x0760079f, 0x27040b20, 0x00000000, 0x00000000, - 0x8760879f, 0xa7048b20, 0x00000000, 0x00000000, 0x0818045a, 0x24ff3008, 0x00000000, 0x00000000, - 0x8b20075a, 0x0000a7ff, 0x00000000, 0x00000000, 0x0818045a, 0x24ff3008, 0x00000000, 0x00000000, - 0x0a18065a, 0x000026ff, 0x00000000, 0x00000000, 0x0b18075a, 0x000027ff, 0x00000000, 0x00000000, - 0x8a18065a, 0x0000a6ff, 0x00000000, 0x00000000, 0x8b20075a, 0x0000a7ff, 0x00000000, 0x00000000, - 0x402a8000, 0x00000000, 0x00000000, 0x00000000, 0x1f78a400, 0x00000000, 0x00000000, 0x00000000, + 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x482fb51c, 0x482f9000, 0x08498901, 0x81010049, + 0x890a492d, 0x00520852, 0x8802810a, 0x07522304, 0xda022a00, 0x439a8802, 0x88088002, 0xd5020740, + 0x43988808, 0x48268008, 0x60414924, 0x60814925, 0x22806801, 0x22204391, 0x60014311, 0x466a4922, + 0x20004449, 0xfaacf002, 0xd1052800, 0x4449491e, 0xfdeef000, 0xd0002800, 0xbd1c2001, 0x47702000, + 0xb5104919, 0x20004449, 0xff45f000, 0xd0002800, 0xbd102001, 0x07492105, 0x49131842, 0x2301b510, + 0x444902db, 0xf0022000, 0x2800fae1, 0x2001d000, 0x2105bd10, 0x07494613, 0x490b1842, 0x4449b510, + 0xf0002000, 0x2800fec9, 0x2001d000, 0x0000bd10, 0xc0000006, 0x400b8000, 0x400d0000, 0xd928c520, + 0x400bc000, 0x0000ffff, 0x00000010, 0x49a4b5f8, 0x444948a2, 0x4ea46008, 0x603048a2, 0x28006830, + 0x6b30dafc, 0x03092101, 0x63304388, 0x28006b30, 0x489edafc, 0x499e6802, 0x400a2303, 0x18d202db, + 0x431a4b9c, 0x20036002, 0x61300300, 0x28006930, 0x6930dafc, 0x043f2701, 0x613043b8, 0x3a404a93, + 0x40086b10, 0x02092123, 0x49931840, 0x63104308, 0x20014c92, 0x49936120, 0x44494891, 0x25016008, + 0xe0009000, 0x46291c6d, 0xf0039800, 0x498efa9f, 0xd8f74288, 0x498d6960, 0x1e694008, 0x0b490749, + 0x02294308, 0x390139ff, 0x0d890589, 0x61604308, 0x09c06a60, 0x1cc001c0, 0x69a06260, 0x04892103, + 0x61a04308, 0x498269a0, 0x21054008, 0x18400689, 0x69e061a0, 0x4008497f, 0x07492103, 0x497e1840, + 0x61e04308, 0x210369e0, 0x43080409, 0x6a6061e0, 0x02c921e7, 0x21214388, 0x184002c9, 0x68306260, + 0x603043b8, 0x43b86b30, 0x69306330, 0x613043b8, 0x486abdf8, 0x68013080, 0x02922203, 0x60014311, + 0x48664770, 0x68013080, 0x02922203, 0x60014391, 0xb5f74770, 0x4969460c, 0x4615b08a, 0x44792214, + 0xf7ff4668, 0x4965febd, 0x44792214, 0xa8053108, 0xfeb6f7ff, 0xd0012d00, 0xd1362d01, 0x3e404e53, + 0x09876b30, 0x01bf4855, 0x200769c2, 0x438205c0, 0xd02c2d00, 0x2c00a805, 0x2c09d027, 0x2401d900, + 0x5c430061, 0x78401808, 0x05c02107, 0x069b05c9, 0x0e9b1840, 0x4d520184, 0x09a4433b, 0x43146828, + 0x43382702, 0x980a6028, 0xffbbf7ff, 0x42986b30, 0x6333d000, 0x69c14841, 0xd00042a1, 0x980a61c4, + 0xffa7f7ff, 0x43b86828, 0xb00d6028, 0x4668bdf0, 0xb570e7d1, 0x4a3b4616, 0x444a2000, 0x46046812, + 0xd0082900, 0x29014d35, 0x2902d007, 0x2404d00a, 0x46206030, 0x4610bd70, 0x6968e7fa, 0x0f810580, + 0xe00d4610, 0x482969e8, 0x6b003840, 0x0e890681, 0xf0034834, 0x2112f9db, 0x69e94348, 0x0f490189, + 0xf0031c49, 0xe7e3f9d3, 0x20044603, 0xd1042b00, 0xd0022900, 0x6008482c, 0x47702000, 0x44484821, + 0x47706800, 0x481db510, 0x05806940, 0x481d0f81, 0x44481c49, 0xf0036800, 0xbd10f9b9, 0x4604b5f8, + 0x460d4818, 0x68004448, 0xf0034920, 0x4606f9af, 0x2103e009, 0xf0034630, 0x9000f9a9, 0xbf00e000, + 0x90001e40, 0x2200d2fb, 0x46281e64, 0x415043d2, 0x43e14605, 0x430143e8, 0xbdf8d1eb, 0x016e3600, + 0x00000004, 0x00012058, 0x400d8000, 0x400d8100, 0xc0c0c0c0, 0x18131818, 0x0f1a2323, 0x400fc000, + 0x1f78a400, 0x0000000c, 0x08954400, 0xfff8e0ff, 0xe3ffffcf, 0x9c7fff80, 0x03800001, 0x000036ca, + 0x402a8000, 0x1c9c3800, 0x09e4f580, 0x000f4240, 0x4d5ab5f8, 0x462e485a, 0x460c9000, 0x46084637, + 0xfa8ff002, 0xd0042800, 0x6ee06e26, 0x6e679000, 0x6d206ea5, 0x6d602800, 0x2800d027, 0x4951d004, + 0x63c82006, 0x62c64850, 0x28006d20, 0x494dd006, 0x31402001, 0x484c62c8, 0x61c63040, 0x23114949, + 0x630b3140, 0x30404848, 0x22016207, 0x6245634a, 0x6285638a, 0x62c563ca, 0x31804942, 0x6305600a, + 0x5d002045, 0xd0032808, 0x2800e00f, 0xe024d1d7, 0x2001493c, 0x62083140, 0x32404a3b, 0x61c86115, + 0x618860d5, 0x61486095, 0x7b206055, 0xd0012803, 0xd1062801, 0x30404833, 0x49336283, 0x31409800, + 0x46206188, 0xfa44f002, 0xd0062800, 0x2101482d, 0x62413040, 0x3040482c, 0x6da06147, 0x6de02800, + 0x2800d02a, 0x4927d005, 0x31402006, 0x48266008, 0x6da06306, 0xd0052800, 0x21044822, 0x62413040, + 0x63c64821, 0x2111481f, 0x62413040, 0x3140491e, 0x2201614f, 0x610d6202, 0x60cd61c2, 0x608d6182, + 0x604d6142, 0x2a037b22, 0x2a01d001, 0x2214d103, 0x98006102, 0xbdf86008, 0xd1d42800, 0x2104bdf8, + 0xd00f2800, 0x29037b01, 0x6c01d10b, 0x06493060, 0xda012900, 0xe003210f, 0x29007e41, 0x211ed101, + 0x21007601, 0x47704608, 0x62884908, 0x47702000, 0x6a894906, 0x20006001, 0x00004770, 0x000010f1, + 0x000130f1, 0x401f8180, 0x401f8380, 0x400f8000, 0x49fcb5f0, 0x4479b085, 0x466dc91e, 0x4efac51e, + 0x4df94ff9, 0x4cf84669, 0x37803640, 0x000335c0, 0xf9aef003, 0x220d0609, 0x8381582b, 0x00918b89, + 0xfb42f000, 0x06496821, 0x43480e49, 0xf000e048, 0x6a37fb3b, 0x69314605, 0xf982f003, 0x2300463a, + 0xffacf002, 0x07c96b21, 0x2116d001, 0x2114e000, 0x1828434d, 0xbdf0b005, 0xfb26f000, 0xe0676921, + 0xe0002116, 0x43482114, 0xf000e7f4, 0x4604fb1d, 0x06456b30, 0x693f4638, 0x68010e6d, 0xf0034620, + 0x463af95f, 0xf0022300, 0x436cff89, 0x18206b31, 0x04d22203, 0xd0114011, 0x04d22201, 0xd1004291, + 0x49d20840, 0x4ad26b09, 0x22014011, 0x1a8903d2, 0x0212d006, 0xd1cd4291, 0xe7cb0880, 0xe7f00880, + 0xe7c70840, 0xfaf0f000, 0x6a384604, 0x0646682d, 0x6b390e76, 0xf0034620, 0x462af933, 0xf0022300, + 0x4374ff5d, 0x18206a39, 0x04d22203, 0xd0104011, 0x04d22201, 0xd1004291, 0x49bc0840, 0x22016b09, + 0x07890f89, 0x18890792, 0x0052d0d6, 0xd1a142d1, 0x0880e7d6, 0x6a28e7f1, 0x6a28e001, 0x07800880, + 0x58080f00, 0x48b3e796, 0xf000e794, 0x6a21fabd, 0xd0970789, 0x2000e794, 0xb510e78c, 0x20014604, + 0xff56f7ff, 0x394049a9, 0xd0092c00, 0xd0092c01, 0xd00e2c02, 0xd00f2c03, 0x21122000, 0xbd104348, + 0xe0016809, 0x0a096809, 0x0e890689, 0xffeef002, 0x6809e7f3, 0xe7f70c09, 0x0e096809, 0xb510e7f4, + 0x69604c9d, 0x69a00180, 0x2103d512, 0x40080309, 0x2101d005, 0x42880309, 0x2000d005, 0x2002e005, + 0xff26f7ff, 0xf000e001, 0x6961fa7f, 0xe00f0ec9, 0x04892103, 0xd0134008, 0x04892101, 0xd0131a40, + 0xd0121a40, 0xd1094288, 0xf7ff2000, 0x6921ff11, 0x0f490749, 0xf0021c49, 0xbd10ffb9, 0xbd102000, + 0xf7ff2001, 0xbd10ff05, 0xf7ff2002, 0xbd10ffa6, 0x2800b510, 0xf002d001, 0x2101ff52, 0x0789487b, + 0x497e6181, 0x03d26b0a, 0x2201d5fc, 0x61420412, 0x04096901, 0x6182d5fc, 0x2001bd10, 0x07804973, + 0x47706148, 0x49752210, 0xd0012800, 0x4770638a, 0x4770634a, 0x6b014871, 0x43112201, 0x47706301, + 0x6b01486e, 0x00490849, 0x47706301, 0x4604b510, 0xf7ff2002, 0x4965fecd, 0x2c003980, 0x2c01d009, + 0x2c02d009, 0x2c03d00e, 0x2000d00f, 0x43482112, 0x6b09bd10, 0x6b09e001, 0x06890a09, 0xf0020e89, + 0xe7f3ff65, 0x0c096b09, 0x6b09e7f7, 0xe7f40e09, 0x4c59b510, 0xf0030003, 0x0d17f86b, 0x362a120d, + 0x403e3c39, 0x4a464442, 0x52504e4c, 0x5c5a5854, 0x0064605e, 0xff63f7ff, 0x0a896961, 0x6960e011, + 0xd50a0640, 0x06006960, 0x2001d503, 0xffbef7ff, 0x2002e005, 0xff31f7ff, 0xf7ffe001, 0x6961ff50, + 0x07490c09, 0x1c490f49, 0xff30f002, 0xf7ffbd10, 0x6961ff46, 0x0f4904c9, 0xf0021c49, 0x6961ff27, + 0x0f890589, 0xf000e7ef, 0xbd10f9cf, 0x03c02001, 0x2000bd10, 0x2002e022, 0x2000e020, 0x2001e004, + 0x2002e002, 0x2003e000, 0xff90f7ff, 0x2008bd10, 0x2001e014, 0x2000e012, 0x2001e004, 0x2002e002, + 0x2003e000, 0xfef9f7ff, 0x2005bd10, 0x2006e006, 0x2007e004, 0x2003e002, 0x2004e000, 0xfe48f7ff, + 0x2000bd10, 0x7800bd10, 0x06402101, 0x03490e40, 0x481d1841, 0x68016001, 0xdafc2900, 0x20014770, + 0x03004919, 0x47706008, 0x21017800, 0x0fc007c0, 0x18410349, 0x63014814, 0x29006b01, 0x4770dafc, + 0x49112001, 0x63080300, 0x78004770, 0x078021c1, 0x01890f80, 0x480c1841, 0x69016101, 0xdafc2900, + 0x49094770, 0x61082000, 0x78004770, 0x078021c1, 0x01890f80, 0x48041841, 0x6a016201, 0xdafc2900, + 0x00004770, 0x000033ba, 0x400d8000, 0x400d8140, 0x00808000, 0x017d7840, 0x400fc000, 0x400d8240, + 0x200049ae, 0xe7eb6208, 0x6841b530, 0x008b2200, 0x089b49aa, 0x600b3180, 0x009b6883, 0x610b089b, + 0x23017801, 0x035b0649, 0x78400e49, 0x019d18c9, 0xd01c2802, 0x006c4ba2, 0xd0162804, 0xd0122808, + 0xd00e2810, 0x4b9f4321, 0x4c9d6b18, 0x402043e4, 0x63184310, 0x30404899, 0x6b016301, 0xdafc2900, + 0x461abd30, 0x4329e7ef, 0x4321e7fb, 0x4329e7f9, 0x2001e7e9, 0x03004991, 0x63083140, 0xb570e7b0, + 0x4b8e6841, 0x22000089, 0x33800889, 0x68816319, 0x00894c8c, 0x3c800889, 0x78016021, 0x06492401, + 0x0e490364, 0x19097840, 0x280201a5, 0x2403d01a, 0x006e07a4, 0xd0132804, 0xd00f2808, 0xd00b2810, + 0x48804331, 0x00a46b04, 0x431408a4, 0x62196304, 0x28006a18, 0xbd70dafc, 0xe7f24622, 0xe7fb4329, + 0xe7f94331, 0xe7ec4329, 0x49742001, 0x31800300, 0xe7756208, 0x78c27901, 0x07920789, 0x0f920f09, + 0x78024311, 0xd0022a00, 0x03522201, 0x78424311, 0xd0022a00, 0x05122201, 0x78804311, 0xd0022800, + 0x05402001, 0x48674301, 0x62013880, 0x29006a01, 0xe755dafc, 0x49632001, 0x39800300, 0xe74f6208, + 0xb5104b60, 0x681a3b40, 0x24bf00c0, 0x43a24084, 0x40842480, 0x601c4314, 0x0e890689, 0x43114081, + 0xbd106019, 0x39404957, 0x00c3680a, 0x40982080, 0x600a4302, 0x4b53e734, 0x3b80b510, 0x00c06b1a, + 0x408424bf, 0x248043a2, 0x43144084, 0x0689631c, 0x40810e89, 0x63194311, 0x494abd10, 0x6b0a3980, + 0x208000c3, 0x43024098, 0xe719630a, 0x4846b508, 0x22036801, 0x60014311, 0x68014844, 0x43112202, + 0x20006001, 0x48429000, 0x9900bf00, 0x91001c49, 0xd3f94281, 0x3940493b, 0x221f6a08, 0x43900212, + 0x43104a3c, 0x20016208, 0xb508bd08, 0x68014836, 0x43112203, 0x48386001, 0x22026801, 0x60014311, + 0x90002000, 0xbf004832, 0x1c499900, 0x42819100, 0x492cd3f9, 0x6a083940, 0x0212221f, 0x4a2d4390, + 0x62084310, 0xbd082001, 0x2200b508, 0x92004668, 0xfebbf7ff, 0x6b014829, 0x08490049, 0x6b016301, + 0x43990483, 0x60026301, 0x22636b01, 0x43110392, 0x20016301, 0xb508bd08, 0x46682200, 0xf7ff9200, + 0x481ffeb4, 0x00496b01, 0x63010849, 0x04436b01, 0x63014399, 0x6b016002, 0x03922263, 0x63014311, + 0xbd082001, 0x2000490d, 0x48146108, 0x04826b01, 0x63014311, 0x4909e6a4, 0x62082000, 0x6b014810, + 0x43110442, 0xe69b6301, 0x6b00480e, 0xd50106c0, 0xe695480d, 0x4448480d, 0xe6916800, 0x400d8000, + 0x00808000, 0x400d8140, 0x400fc080, 0x402e0140, 0x00061a80, 0x00001701, 0x402e0340, 0x400d9000, + 0x400da000, 0x400d8240, 0x016e3600, 0x00000004, 0x460cb570, 0xf0024606, 0x0005fa35, 0x4622d10b, + 0x32802301, 0x46302100, 0xf8e6f002, 0x28017c60, 0x2000d101, 0x46287420, 0xb570bd70, 0x4605b08a, + 0x466e2000, 0x200f7030, 0x90022401, 0x74329403, 0x32ff460a, 0x32719301, 0x46214623, 0xf0024628, + 0x4669f8cb, 0x94024628, 0xffd5f001, 0xbd70b00a, 0x2004b5ff, 0x460db083, 0xd0292900, 0x36ff462e, + 0x7b7036c1, 0xd0062800, 0x9a059b06, 0xf7ff9803, 0x2800ffd4, 0x7b30d11c, 0x3480462c, 0xd10a2802, + 0x30304620, 0x466bc887, 0x4620c307, 0xc80f3040, 0xc40f3430, 0x46293c40, 0x9a059b06, 0xf0029803, + 0x7b31f8cb, 0xd1032902, 0xcd0e466d, 0xc48e3430, 0xbdf0b007, 0xb089b5ff, 0x4616461d, 0x9809460c, + 0xffc6f7ff, 0xd1142800, 0x70084669, 0x200e2701, 0x90029703, 0x4622740e, 0x326132ff, 0x4639463b, + 0x98099501, 0xf878f002, 0x97024669, 0xf0019809, 0xb00dff82, 0xb5ffbdf0, 0xb0832004, 0x4696469c, + 0xd0d52900, 0x35ff460d, 0x7b2835c1, 0x3480460c, 0xd10b2802, 0x30104620, 0x466ac889, 0xc28969e6, + 0x30204620, 0x3410c88d, 0x3c20c48d, 0x46724663, 0xf0029803, 0x7b29f8ae, 0xd1b92902, 0xcd0e466d, + 0xc44e3410, 0xb5f7e7b4, 0x4616b082, 0xd051000d, 0xd84f2e01, 0x34ff462c, 0x7a2034c1, 0xd0002800, + 0x28002001, 0x6c28d046, 0x0fc70640, 0xf0029802, 0x2e00fa62, 0x7a20d02b, 0xd0092800, 0x5d412046, + 0x9802463a, 0xfa15f7ff, 0x98024629, 0xfdaaf001, 0x28007ba0, 0x2100d003, 0xf0029802, 0x466afa5e, + 0x98022102, 0xfa55f7ff, 0xd0022f00, 0x08409800, 0xaa019000, 0x98022100, 0xfa4bf7ff, 0x98019900, + 0xfc44f002, 0x1c40210a, 0x08804348, 0x7a21e010, 0xd0072900, 0x9802463a, 0xf9ebf7ff, 0x98024629, + 0xfd80f001, 0x28007ba0, 0x2101d0d9, 0xbf00e7d4, 0xd2fc1e40, 0xbdf0b005, 0xb089b5ff, 0x460d4617, + 0xf0014608, 0x4606fd47, 0x46292200, 0xf7ff9809, 0x463bff9a, 0x46294632, 0xf7ff9809, 0x0004ff19, + 0x2002d13f, 0x70084669, 0x24012009, 0x94039002, 0x5d412047, 0x30ff4628, 0x29003081, 0x7c01d006, + 0xd0032900, 0x91027c41, 0x91037c01, 0x97014669, 0x990c740e, 0x6c009105, 0x98029006, 0x01002101, + 0x32801942, 0x98099b03, 0xffb6f001, 0x94024669, 0xf0019809, 0x0004fec0, 0x463bd113, 0x46294632, + 0xf7ff9809, 0x0004ff38, 0x20ffd10b, 0x5d4030d0, 0xd0062800, 0x4632463b, 0x98094629, 0xff0af7ff, + 0x98094604, 0xf9d1f002, 0x46292201, 0xf7ff9809, 0x4620ff4a, 0xb5f3e71d, 0x2600b08b, 0x9d0c4669, + 0x2101700e, 0x210b9103, 0x46699102, 0x2047740e, 0x46375d40, 0x28004634, 0x4628d009, 0x308130ff, + 0x29007d01, 0x7d41d003, 0x7d009102, 0x22009003, 0x980b990c, 0xff27f7ff, 0x950a3550, 0x9009cd01, + 0xd01a2800, 0x22004633, 0x980b990c, 0xfea0f7ff, 0xd13e0004, 0x96019802, 0x980c0101, 0x180a9b03, + 0x32802101, 0xf001980b, 0x2001ff57, 0x46699002, 0xf001980b, 0x0004fe60, 0x9809d12b, 0x18361c7f, + 0xd3db2f04, 0xd1242c00, 0x90092000, 0x980c4606, 0x30ff9d0a, 0x900a30c1, 0x2f00cd80, 0x2200d013, + 0x990c9b09, 0xf7ff980b, 0x0004fec6, 0x980ad111, 0x28007bc0, 0x2200d007, 0x990c9b09, 0xf7ff980b, + 0x0004fe99, 0x9809d105, 0x19c01c76, 0x2e049009, 0x980bd3e2, 0xf959f002, 0x990c2201, 0xf7ff980b, + 0x4620fed2, 0xb5f7e6a5, 0x4617b08a, 0x4608460d, 0xfc70f001, 0x22004606, 0x980a4629, 0xfec3f7ff, + 0x4632463b, 0x980a4629, 0xfe42f7ff, 0xd1390004, 0x97014669, 0x20057008, 0x90022401, 0x740e9403, + 0x5d402047, 0xd0092800, 0x30ff4628, 0x7b013081, 0xd0032900, 0x91027b41, 0x90037b00, 0x21019802, + 0x19420100, 0x9b033280, 0xf001980a, 0x4669fee5, 0x980a9402, 0xfdeff001, 0xd1130004, 0x4632463b, + 0x980a4629, 0xfe67f7ff, 0xd10b0004, 0x30d020ff, 0x28005d40, 0x463bd006, 0x46294632, 0xf7ff980a, + 0x4604fe39, 0xf002980a, 0x2201f900, 0x980a4629, 0xfe79f7ff, 0xe64c4620, 0xb08ab5f7, 0x460d4617, + 0xf0014608, 0x4606fc17, 0x46292200, 0xf7ff980a, 0x463bfe6a, 0x46294632, 0xf7ff980a, 0x0004fde9, + 0x4669d139, 0x70089701, 0x24012008, 0x94039002, 0x2047740e, 0x28005d40, 0x4628d009, 0x308130ff, + 0x29007f01, 0x7f41d003, 0x7f009102, 0x98029003, 0x01002101, 0x32801942, 0x980a9b03, 0xfe8cf001, + 0x94024669, 0xf001980a, 0x0004fd96, 0x463bd113, 0x46294632, 0xf7ff980a, 0x0004fe0e, 0x20ffd10b, + 0x5d4030d0, 0xd0062800, 0x4632463b, 0x980a4629, 0xfde0f7ff, 0x980a4604, 0xf8a7f002, 0x46292201, + 0xf7ff980a, 0x4620fe20, 0xb5f0e5f3, 0x20044607, 0x461db089, 0x460e4614, 0xd00f2a00, 0x46682124, + 0xfa92f002, 0x46692003, 0x20017008, 0x95089002, 0x96019003, 0x46389407, 0xfd5df001, 0xbdf0b009, + 0xb08fb5ff, 0x460c2000, 0x900b900a, 0x900d900c, 0x25016811, 0x2905461e, 0x6851d202, 0xd3152940, + 0x6c117425, 0x0f490249, 0xf002000b, 0x0d07fb81, 0x050b0905, 0x000d0705, 0xe00b2702, 0xe0092704, + 0xe0072701, 0xe0052703, 0xe03f7420, 0x05098831, 0xd03b0f0f, 0x90002000, 0x90024669, 0x20037508, + 0x95097108, 0x95049503, 0x2f019108, 0x2f02d007, 0x2f03d003, 0x2f04d02d, 0x48fdd104, 0x48fce001, + 0x900a3830, 0xaa0a2301, 0x980f4619, 0xfe04f001, 0x980fa901, 0xfd0ff001, 0xd1182800, 0x01006830, + 0xd0050f00, 0x040088b0, 0xd0010e01, 0x90000e00, 0x46202100, 0x74213080, 0xd00d2f01, 0x2f022202, + 0x2f03d013, 0x2f04d029, 0x7421d01f, 0xb0132000, 0x48e7bdf0, 0xe7d4300a, 0x064a9900, 0x4ae5d4f6, + 0x20c36402, 0x20404001, 0x9900e01e, 0xd4ed078b, 0x43114be1, 0x02086403, 0x74259000, 0x20047525, + 0x98007560, 0x746561a0, 0x9900e7e0, 0xd4dd078b, 0x33304bd8, 0x64034311, 0x9900e007, 0xd4d5060a, + 0x323d4ad5, 0x20806402, 0x91004301, 0xb5f7e7e5, 0x02402001, 0x2700b098, 0x46689001, 0x24017407, + 0x9702460d, 0x29009403, 0x48ccd072, 0xc84d4478, 0xc14da90d, 0x466a2003, 0xa8097010, 0x20109007, + 0x462a9008, 0x21013280, 0x98189b03, 0xfd94f001, 0x94024669, 0xf0019818, 0x2800fc9e, 0x9809d158, + 0xd1081c40, 0x1c40980a, 0x980bd105, 0xd1021c40, 0x1c40980c, 0x2210d007, 0xa80da909, 0xf969f002, + 0xd1452800, 0x2300e034, 0x4629461a, 0xf7ff9818, 0x2800fcaf, 0x2009d17b, 0x20029002, 0x70084669, + 0x462aa80d, 0x90052610, 0x960632ff, 0x21013211, 0x98189b03, 0xfd60f001, 0x94024669, 0xf0019818, + 0x2800fc6a, 0x2300d163, 0x4629461a, 0xf0019818, 0x2800fdb0, 0x9002d15b, 0x46692003, 0xa8097008, + 0x96089007, 0xf0019818, 0x2800fc56, 0xe7c2d14f, 0x90162032, 0x90152000, 0x21406c28, 0x64284308, + 0x5d412046, 0x22012602, 0xf7fe9818, 0xe038ff22, 0x2400e03d, 0x94129411, 0x94149413, 0x6d282101, + 0x42880609, 0x488ed901, 0x488ee000, 0x498e9011, 0x1840b2f0, 0x2301498d, 0x90124308, 0x2100aa11, + 0xf0019818, 0x2003fd19, 0x94024669, 0xa8097008, 0x20109007, 0x98189008, 0xfc1df001, 0xd0060004, + 0xd0142f00, 0x2f00981a, 0xd0106006, 0x2210e010, 0xa80da909, 0xf8edf002, 0xd00c2800, 0x2f001c76, + 0x9815d1f0, 0x1c409916, 0x42889015, 0x4c78d3c1, 0xb01b4620, 0x2701bdf0, 0xb5ffe7e4, 0xb0824608, + 0x9000305c, 0x68c8460b, 0x27013308, 0xda032800, 0x1ec0463a, 0xe0014082, 0x08c21c40, 0x24ff9802, + 0x9e026502, 0x68489201, 0x340136ff, 0x28403681, 0x6434d201, 0x8d18e00a, 0x0f020600, 0x40904638, + 0x03d22201, 0xd1004290, 0x64304620, 0x24004d61, 0x00424620, 0x7f1718d2, 0xd00d2f00, 0x40ba2201, + 0xd20142aa, 0x46844615, 0xd90542a2, 0x053f2701, 0xd20142ba, 0x46864614, 0x28041c40, 0x6475d3e9, + 0x98026534, 0x30c130ff, 0xd10142a5, 0xe0002201, 0x72422200, 0x98012201, 0x42900612, 0x3140d92d, + 0x28007e08, 0x9800d008, 0x79014460, 0x60019804, 0x44709800, 0xe0187901, 0x00404660, 0x7f4018c0, + 0x22dc2121, 0xd0022820, 0xd10528d8, 0x9804e002, 0xe0016001, 0x60029804, 0x00404670, 0x7f4018c0, + 0xd0022820, 0xd10528d8, 0x9805e002, 0xe0016001, 0x60029805, 0xb0062000, 0x4660bdf0, 0x18c00040, + 0x98047f41, 0x46706001, 0x18c00040, 0xe7ec7f41, 0xb08db5ff, 0x90052004, 0x460f980f, 0x90033008, + 0x305c980f, 0x20009009, 0x98109004, 0x02006800, 0x28010f00, 0x9803d105, 0x03006800, 0x90040fc0, + 0x2000d071, 0x99107338, 0x78094606, 0x070aab0b, 0x21460f12, 0x900055ca, 0x90062018, 0x90072000, + 0x4638aa0a, 0xf7ff990f, 0x2101ff48, 0x06096d38, 0xd9014288, 0x90062020, 0x88009810, 0x0f000400, + 0x4639d151, 0x9a0f9b10, 0xf7ff980d, 0x9005fdd9, 0xd1f52800, 0x68009803, 0xd51d0281, 0x90072002, + 0x7a009803, 0x0f4e0601, 0x0ec006c0, 0x0000e01c, 0x24010435, 0x20010401, 0x20020401, 0x00002634, + 0x8a2004ee, 0x8a1804ed, 0x00040200, 0xa604b000, 0x00004e2a, 0x00ffffff, 0xd5060240, 0x68809803, + 0x0f4e0201, 0x0ec002c0, 0x980f9000, 0x30409a06, 0x49fc1dfc, 0x900834f9, 0xd0022a20, 0x612048fa, + 0x7e00e012, 0x28004bf9, 0x9809d03b, 0x68004af8, 0xd50105c5, 0xe00348f7, 0xd5320600, 0x302248f3, + 0x61206162, 0xe0a9e001, 0x20016161, 0x463d7338, 0x358048f1, 0x48f16328, 0x980a6128, 0xb2c14af0, + 0x04009806, 0x43114301, 0x65299001, 0xb2c9990b, 0x43114301, 0x01402023, 0x63206021, 0x68009810, + 0x0f010100, 0x9910d00f, 0x060a6849, 0xd00a0e12, 0x9904b2c8, 0x90002600, 0xd0212900, 0x90000040, + 0x6123e01e, 0x9904e7d0, 0xd0192900, 0xd1170f00, 0x28209806, 0x48d5d104, 0x60281c40, 0x606848d9, + 0x980d4639, 0xfaa4f7ff, 0x28009005, 0x466ad166, 0x980d4639, 0xfddbf7ff, 0x28009005, 0x2600d1f6, + 0x28189806, 0x2002d006, 0x98049007, 0xd0202800, 0xe00320ee, 0x28009804, 0x20edd00a, 0x22406c39, + 0x64394311, 0x43019901, 0x430148c7, 0xe0376029, 0x68009803, 0xd5030281, 0x89009803, 0xe0030400, + 0xd5040240, 0x68809803, 0x90020e00, 0x2003e01f, 0x9808e019, 0x28007e00, 0x9809d00a, 0x06816800, + 0x06c0d40a, 0x206cd513, 0x20009002, 0xe00e9007, 0x68009803, 0xd5010281, 0xe7e620ec, 0xd5010240, + 0xe7e2206c, 0x90022013, 0x46062000, 0x99029000, 0x43089801, 0x06099907, 0x49a94308, 0x60284308, + 0x463a9910, 0x32ff7809, 0x32c10609, 0x0f0b2000, 0x2b009201, 0x0f09d003, 0xd0042901, 0x9800e06b, + 0x90001980, 0x990fe049, 0x29406849, 0x9903d3f7, 0x058a6b89, 0x0309d5f3, 0x22050f09, 0xd0014211, + 0xe00b20a5, 0xd5090789, 0x9b104639, 0x980d9a0f, 0xffa1f000, 0x28009005, 0x2001d14d, 0x220a9903, + 0x04098f09, 0x42110e89, 0x4990d007, 0x67616721, 0x29209906, 0x498ed109, 0x2211e006, 0xd03a4211, + 0x6721498c, 0x498c6761, 0x210167a1, 0x2e009a01, 0xd0117351, 0x29009904, 0x2e01d033, 0x2127d02e, + 0x43080289, 0x06099900, 0x43080a09, 0x43084983, 0x48836068, 0xe01760a8, 0x28009800, 0x9a04d00f, + 0x2a004980, 0xb2c0d005, 0x497f1840, 0x60684308, 0xb2c0e00a, 0x497d1840, 0x60684308, 0x487ce00b, + 0x98046068, 0xd0062800, 0x20019901, 0x6c387388, 0x43082140, 0x98056438, 0xbdf0b011, 0x09002126, + 0x2e01e7ce, 0x2107d00c, 0x43080289, 0x06099900, 0x43080a09, 0x4308496f, 0x486f6068, 0xe7ea60a8, + 0x09002106, 0xb5f7e7f0, 0xb0984e6c, 0xd008000d, 0x466a2308, 0x98182100, 0xfc37f7ff, 0xd1640004, + 0x2404e001, 0x4966e061, 0x42889800, 0x4634d001, 0x4668e05b, 0x60287900, 0x79804668, 0x280a1c40, + 0x200ad900, 0x981a9016, 0x28002108, 0x0209d000, 0xaa029816, 0x981800c3, 0xfc17f7ff, 0xd1440004, + 0x46282164, 0xfeb0f001, 0xe03b2600, 0xaa0200f0, 0x18835c11, 0x020079d8, 0x20ff180a, 0x42820200, + 0x4850d002, 0xd12c4282, 0x20022100, 0x1819020f, 0x43397909, 0xd5f91e40, 0x008778d8, 0x2800981a, + 0x0209d000, 0x020020ff, 0xd10c4282, 0xd9002f50, 0x462a2750, 0x3208463b, 0xf7ff9818, 0x0004fbe6, + 0x606fd113, 0x483fe00d, 0xd10a4282, 0x463b462a, 0x9818325c, 0xfbd9f7ff, 0xd1060004, 0x20582101, + 0x1c765541, 0x42869816, 0x4620d3c0, 0xb5f7e541, 0xb088460d, 0x46282103, 0x230873e9, 0x71433040, + 0x642b2358, 0x73292401, 0xd0012a00, 0x64292159, 0x210f71c4, 0x87c48781, 0x2001462e, 0x024036ff, + 0x64303681, 0x64700240, 0x46306530, 0x90073040, 0x46297244, 0xf7ff9808, 0x2800f91b, 0x4822d172, + 0x90002700, 0x97034821, 0x90012301, 0x466a9702, 0x98084619, 0xfa00f001, 0x97039702, 0x481c4f1a, + 0xe0373780, 0x00002004, 0x08180402, 0x08200412, 0x00002204, 0x0a20043e, 0x00000406, 0x24040405, + 0x08000400, 0x00012404, 0x8a000400, 0x06ff06ff, 0x000006ff, 0x06000600, 0x32101e00, 0xb2000200, + 0x7c01a604, 0x00040200, 0xa604b000, 0x26043000, 0x00002404, 0x32000200, 0x7c012604, 0x00004e27, + 0x50444653, 0x0000ff84, 0x8b188720, 0xa3028f10, 0xa7048f10, 0x23019001, 0x2100466a, 0x98089700, + 0xf9baf001, 0x02c02013, 0x23029006, 0x49feaa06, 0xf0009808, 0x2800fefc, 0x2308d114, 0x2110aa04, + 0xf0009808, 0x2800fee0, 0x9805d10c, 0xb28049f7, 0x98049005, 0xd1044288, 0x98052159, 0x42880209, + 0x48f3d002, 0xbdf0b00b, 0xaa042308, 0x98082127, 0xfec9f000, 0xd1f52800, 0x04009804, 0x90040e00, + 0x28093817, 0x9904d8ed, 0x40882001, 0x200f6528, 0x90060300, 0xaa062302, 0x98082100, 0xfec7f000, + 0xd1df2800, 0x49e3462c, 0x60213480, 0x606149e2, 0x60a149e2, 0x4ae349e2, 0x4fe44be3, 0xc48e3410, + 0x60274fdc, 0x60674fe2, 0x60a74fdc, 0xc40e3410, 0x60a74fe0, 0x60616022, 0x60e74fdf, 0x61274fdd, + 0x4fde35ff, 0xc58e3511, 0x34144fd2, 0x602f3fa0, 0x606f4fdb, 0xc48e4fdb, 0x4fd6c40e, 0x602260a7, + 0x4fd56061, 0x4fd360e7, 0x4cca6127, 0x3ca03d20, 0x4cd5602c, 0x4cd5606c, 0x462f60ac, 0x37304cd1, + 0xc70ec71e, 0x656c4ccb, 0x652964ea, 0x65ac4cca, 0x37144cc8, 0xc70e65ec, 0x66e949cd, 0x72312102, + 0x72722203, 0x22017131, 0x74317172, 0x74712109, 0x73312104, 0x73732305, 0x210b7531, 0x99077571, + 0xe77f730a, 0x2504b5f7, 0x4617b092, 0x2a00460c, 0x7878d004, 0x42887839, 0x2500d101, 0x4620e087, + 0x21083040, 0x71419011, 0x25037878, 0x28422601, 0x2841d001, 0x2502d103, 0x21049811, 0x78787141, + 0xd0012882, 0xd1002842, 0x20002621, 0x90014669, 0x70087408, 0x90022001, 0xa8092120, 0xfd24f001, + 0x200278f9, 0x29060242, 0x2907d00b, 0x2908d012, 0x2001d001, 0x0229e02b, 0x43131d8b, 0x930931ff, + 0x0229e005, 0x3366460b, 0x31994313, 0x43119309, 0xe01c910d, 0x460f0229, 0x376602b2, 0x4317062b, + 0x431f06b5, 0x432f46ac, 0x31992599, 0x4311042d, 0x4319432f, 0x22334665, 0x04524329, 0x97094311, + 0x2e21910d, 0x6c21d103, 0x43112240, 0x90036421, 0x20019911, 0x06017188, 0x498e6521, 0x498e6021, + 0x21036061, 0x73a17361, 0x31c921ff, 0x200a5508, 0x46216760, 0xf7fe9812, 0x0005ffab, 0xaa09d117, + 0x9b032101, 0xf0019812, 0x4669f897, 0xf0009812, 0x4605ffa2, 0x217d4881, 0x00c94448, 0xf0016800, + 0xe001fcc5, 0x1e40bf00, 0x28009011, 0x4628d1fa, 0xbdf0b015, 0xb09cb5f7, 0x460c981e, 0x02286805, + 0x28050f00, 0x2700d011, 0x22304975, 0xa80d4479, 0xf926f7fe, 0x0f000428, 0x0328900a, 0x980a0f05, + 0xd0042800, 0xd1132803, 0x2701e001, 0x2d00e7ec, 0x2d03d010, 0x2800d10c, 0x2003d00a, 0x20107320, + 0x981e6420, 0x02006800, 0x28040f00, 0xe019d018, 0xe1952604, 0xf7fe4668, 0x4606fbcb, 0xf7fe2000, + 0x2e00fbc3, 0x466ad106, 0x981c4621, 0xff2af7ff, 0xd1ee0006, 0x73202000, 0x64202010, 0xe0022003, + 0x64202050, 0x90092006, 0x4328980a, 0x2701d100, 0x990a4620, 0x29033040, 0x2101d008, 0x46217141, + 0xf7fe981c, 0x0006ff35, 0xe001d1d3, 0xe7f52108, 0x2d002000, 0x2f00d004, 0x2001d001, 0x2002e000, + 0xa90d0100, 0x23011842, 0x981c4619, 0xf814f001, 0x46692000, 0x75089002, 0x71082003, 0x90032001, + 0xa80b9004, 0xa9019008, 0xf000981c, 0x0006ff14, 0xa808d1af, 0x28c27b00, 0x2101d1ab, 0x2d000409, + 0xd01da808, 0x460a7c40, 0x40823830, 0x46206522, 0x30ff2201, 0x30810312, 0x11126442, 0x65016402, + 0x73202003, 0x64202010, 0x40472001, 0x46294620, 0x30c130ff, 0x35804625, 0x29009019, 0xe078d002, + 0xe7e07b80, 0x2803980a, 0x2101d173, 0x20027421, 0x82617460, 0x75622206, 0x23007521, 0x22074669, + 0x70ca700b, 0xd04a2f00, 0x466a2182, 0x61a07051, 0x6628481c, 0x3872481b, 0x481b6668, 0x981e66a8, + 0x06007800, 0xe0310f00, 0x00000555, 0x52005100, 0x00004e29, 0x8b1887a0, 0xb3068f10, 0x0000a704, + 0x87008700, 0x87aa8700, 0x87058700, 0x87708700, 0xb70b8f10, 0x87558700, 0x87028700, 0x87a08700, + 0xa3808f10, 0x87808700, 0x87008f10, 0x00008730, 0x87108700, 0x42464346, 0x56010400, 0x0000000c, + 0x00001c14, 0x04000472, 0x20010400, 0xd0022803, 0x728b9919, 0x9919e01a, 0x72882001, 0x2181e016, + 0x7059466b, 0x4bfe61a0, 0x662b48fe, 0x48fe6668, 0x210166a8, 0x77214620, 0x70423020, 0x48f87001, + 0x38726321, 0x6768672b, 0x67a848f7, 0xf7fe9800, 0x48f6fadb, 0x48f66328, 0x1de06128, 0x30f9990a, + 0xd0032900, 0xd0162f00, 0xe0152321, 0x73212101, 0x602949f0, 0x606949f0, 0x1d8949ee, 0x49ef6101, + 0x49ec6141, 0x65293115, 0x31d049ea, 0x21236001, 0x63010149, 0x2301e084, 0xd0012f00, 0xe0002122, + 0x468e2102, 0xd0012f00, 0xe000212c, 0x911a210c, 0xd0012f00, 0xe0002129, 0x910a2109, 0xd0012f00, + 0xe0002128, 0x91002108, 0x4ad80299, 0x3a18069b, 0x469c188a, 0x4bda431a, 0x602a431a, 0x23194672, + 0x015b0292, 0x9b1a18d2, 0x069b4696, 0x4bd5431a, 0x606b4313, 0x029a9b0a, 0x009b23c1, 0x920a18d2, + 0x1c9a60aa, 0x4663188a, 0x4bcf431a, 0x4acf4313, 0x188a642b, 0x431a4663, 0x43134bcd, 0x02122203, + 0x188a622b, 0x431a4663, 0x061b2303, 0x626a431a, 0x4ac662aa, 0x320d9b0a, 0x188a62eb, 0x431a4663, + 0x43134bc4, 0x9b006103, 0x069b4672, 0x23c1431a, 0x4313049b, 0x61434abd, 0x188a321c, 0x431a4663, + 0x43134bbd, 0x4672652b, 0x22f7656a, 0x188d0092, 0x431d4663, 0x46724bb9, 0x6005431d, 0x221b6042, + 0x18890152, 0x4ab64663, 0x43114319, 0x2f006301, 0x6c20d003, 0x43082140, 0x99196420, 0x73082002, + 0xb01f4630, 0xb5f7bdf0, 0x49ae460c, 0x4617b0a6, 0x44792220, 0xf7fda81d, 0x6838ff63, 0x0f000200, + 0xd0092807, 0x90002000, 0x03006838, 0xd0050f00, 0x73202003, 0xe0142050, 0xe7f42001, 0xf7fea801, + 0x4605fa17, 0xf7fe2000, 0x2d00fa0f, 0xaa01d106, 0x98264621, 0xfd76f7ff, 0xd1140006, 0x73202000, + 0x46252010, 0x35402108, 0x71696420, 0x98264621, 0xfd8ef7fe, 0xd1f00006, 0x03006838, 0xd0030f01, + 0x28030f00, 0xe09ed003, 0xaa1d2301, 0x2301e001, 0x2101aa21, 0xf0009826, 0x2008fe6f, 0x22007168, + 0x9826a904, 0xfbbff7ff, 0xd1220006, 0xaa02ab03, 0x4620a904, 0xf971f7ff, 0x28009800, 0x2050d103, + 0x20036420, 0x46257320, 0x35804870, 0x48706328, 0x68396128, 0x0f020308, 0x30ff4620, 0x900130c1, + 0x2a0338c0, 0x0409d006, 0x2a030f0a, 0x0f09d002, 0xe068d01b, 0x62294974, 0x60294974, 0x60694974, + 0x64294974, 0x39dc4971, 0x49706529, 0x60013921, 0x0149213b, 0x496d6301, 0x610139eb, 0x6141496e, + 0x03006838, 0xd02f0f00, 0x2201e04a, 0x06126d21, 0xd3024291, 0x218e2220, 0x2218e001, 0x9b0221c2, + 0xb2db0412, 0x43134c65, 0x652b4323, 0x43119b03, 0x4313b2db, 0x43234a62, 0x60034311, 0x21476101, + 0x614101c9, 0x29009900, 0x495ed00a, 0x495e6029, 0x21236069, 0x63010149, 0x20019901, 0xe0227388, + 0x6029495a, 0xe7f34952, 0x46692000, 0x27067008, 0x208270cf, 0x98007048, 0xf966f7fe, 0x74202001, + 0x74612102, 0x61a121e7, 0x75207567, 0x48348260, 0x6628300f, 0x38724832, 0x48386668, 0x66a81ec0, + 0x20029901, 0x46307308, 0xbdf0b029, 0xb0b4b5f7, 0x90004847, 0x46156810, 0x0f000200, 0x2809460c, + 0x2600d01b, 0x22504943, 0xa81e4479, 0xfe78f7fd, 0x90022000, 0x30404620, 0x90012104, 0x68287141, + 0x04000301, 0x20100f05, 0x64200f0f, 0xd0062f00, 0xd01b2f02, 0xd01f2f03, 0x2601e169, 0xa804e7e2, + 0xf926f7fe, 0x20009000, 0xf91ef7fe, 0x28009800, 0xaa04d107, 0x98344621, 0xfc84f7ff, 0x28009000, + 0x9901d1ea, 0x71482001, 0xe0032000, 0x20049901, 0x20037148, 0xe0087320, 0x73202003, 0x99012008, + 0x71482e00, 0x2001d101, 0x2d009002, 0x2d02d003, 0x2d03d001, 0x4638d1d0, 0xd1004328, 0xe03b2601, + 0x04000472, 0x04020400, 0x20010400, 0x00000406, 0x24040405, 0x0820040c, 0x24043308, 0x00002004, + 0x03110000, 0x03060000, 0x03f90000, 0x00000305, 0x03fa0000, 0x03ed0000, 0x03de0000, 0x03230000, + 0x039f0000, 0x000018be, 0xa7040705, 0x8b2007fd, 0xa704b306, 0x00000706, 0x0000a304, 0x08000400, + 0x0b000400, 0x0b2004fc, 0x27043306, 0x8b2004fd, 0x00004e29, 0x00001708, 0xd0022d02, 0xd0022d03, + 0x2004e004, 0x2008e000, 0x71489901, 0x6c212040, 0xd0012e00, 0xe0004381, 0x64214301, 0x98344621, + 0xfc36f7fe, 0x28009000, 0x2e00d18a, 0x2f02d008, 0x2f03d002, 0xe001d10c, 0xe0092001, 0xe0072002, + 0xd0022f02, 0xd1032f03, 0x2003e001, 0x2004e000, 0xa91e0100, 0x23011842, 0x98344619, 0xfd0cf000, + 0x9a02a905, 0xf7ff9834, 0x9000fa5e, 0xd17d2800, 0xaa32ab33, 0x4620a905, 0xf80ff7ff, 0x73202003, + 0x30804620, 0x630149fd, 0x610149fd, 0xd0012e00, 0xe0002302, 0x2e002322, 0x210cd001, 0x212ce000, + 0x2e00468e, 0x2109d001, 0x2129e000, 0x2e009102, 0x2208d001, 0x2228e000, 0x0d8f07a9, 0x46399204, + 0x07aa9701, 0x370b0992, 0x4317069b, 0x431f469c, 0x431f4bec, 0x46736007, 0x029b1d0f, 0x9b02431f, + 0x069b4317, 0x9302431f, 0x049b2301, 0x6047431f, 0x3720460f, 0x46634317, 0x4be2431f, 0x431f4696, + 0x460f6507, 0x431737d8, 0x431f4663, 0x431f4bdd, 0x33f91de3, 0x1c8f601f, 0x46624317, 0x4ad94317, + 0x611f4317, 0x9a04460f, 0x02923780, 0x22014317, 0x31600292, 0x4311615f, 0x63192702, 0xd0012d02, + 0xd10f2d03, 0x46739901, 0x43191d49, 0x43199b02, 0x43194bcd, 0x99016201, 0x43111d89, 0x32cd22ff, + 0x55176401, 0x61a12100, 0xe0002d02, 0xd002e03f, 0xd0032d03, 0x2201e005, 0xe0010492, 0x04d22201, + 0x2e0061a2, 0x6c22d010, 0x431a2380, 0x22016422, 0x551a2379, 0x66024abd, 0x66424abd, 0x74202001, + 0xd0072d00, 0xe0067467, 0x69a22301, 0x431a05db, 0xe7ef61a2, 0x22067461, 0x75207562, 0x46688260, + 0x2e007301, 0x2d02d008, 0x2d03d002, 0xe007d002, 0xe0122041, 0xe0102081, 0xd00b2d02, 0xd00b2d03, + 0x20087341, 0x73c84669, 0xf7fd9803, 0x9800ffbd, 0xbdf0b037, 0xe0002042, 0x46692082, 0xe7f07348, + 0x2704b5f7, 0x460c4616, 0xd04d2900, 0xd04b2e00, 0x462001f9, 0xf868f001, 0x46252101, 0x71a93540, + 0x65200608, 0x6020489b, 0x6060489b, 0x73602003, 0x20ff73a0, 0x550130c9, 0x02006830, 0x00030f00, + 0xf966f001, 0x0c06060a, 0x1d171711, 0x3023231d, 0x46214632, 0xf0009800, 0xe001f8d6, 0xe0032201, + 0xd0180007, 0x2200e01e, 0x98004621, 0xf9cff7ff, 0x4632e7f6, 0x98004621, 0xfb7cf7ff, 0x4632e7f0, + 0x98004621, 0xfd3ff7ff, 0x4632e7ea, 0x98004621, 0xfe1cf7ff, 0x4620e7e4, 0xff51f7fd, 0x07007830, + 0x71a80f00, 0x71282001, 0xbdfe4638, 0x2004b5ff, 0x460fb081, 0xd01e2900, 0x35ff463d, 0x6c693581, + 0x460c4249, 0x18d24014, 0x400a4252, 0x31ca21ff, 0x42565dc9, 0xd10c2900, 0x29006d29, 0xe02ad009, + 0x46394622, 0xf7fe9801, 0x2800fcae, 0x6c69d103, 0x42b4190c, 0xb005d3f4, 0x6d29bdf0, 0x43884620, + 0x2000d00e, 0x28001b32, 0x4291d00c, 0x4622d80a, 0x98014639, 0xfcf0f7fe, 0xd1ec2800, 0xe0096d29, + 0xe7ef2001, 0x46394622, 0xf7fe9801, 0x2800fc8c, 0x6c69d1e1, 0x42b4190c, 0xe7dcd3df, 0xb089b5ff, + 0x9c122004, 0x4616461f, 0xd0222900, 0xd0202e00, 0xd01e2c00, 0xf0004608, 0x2103f8ed, 0x7011466a, + 0x91032101, 0x91022100, 0x4d4c7410, 0xd80042ac, 0x46694625, 0x96079701, 0x98099508, 0xfa8bf000, + 0xd1062800, 0x008908a9, 0x197f1b64, 0x2c00198e, 0xb00dd1eb, 0xb570bdf0, 0x460cb08e, 0x910c2100, + 0x910b9100, 0x466a910d, 0x46069102, 0x20037511, 0x25017110, 0x483a9503, 0x92089509, 0x462b900a, + 0xaa0a9504, 0x46304629, 0xfb56f000, 0x4630a901, 0xfa61f000, 0xd1142800, 0x22f79900, 0x4b2b4011, + 0x3310040a, 0x910018d3, 0x742522ff, 0x51133261, 0x220e7525, 0x61a17562, 0x74612104, 0x34c134ff, + 0xb00e73e5, 0xb5f0bd70, 0x20004607, 0x460db0a9, 0x24044616, 0x90254923, 0x90279026, 0x44792230, + 0xa8199028, 0xfbdcf7fd, 0x03006830, 0xd1580f00, 0x20452104, 0x46285541, 0x3080491b, 0x491b6001, + 0x46296041, 0xf7fe4638, 0x0004fa23, 0x7830d149, 0x0f000600, 0xd10e2801, 0x49151de8, 0x670130f9, + 0x14096741, 0x23006781, 0x4629461a, 0xf7fe4638, 0x0004fa24, 0x6830d135, 0xe01b0300, 0x00000406, + 0x24040405, 0x00200400, 0x00040400, 0x04000471, 0x00002003, 0x42464346, 0x56010400, 0x0000ffff, + 0x24010485, 0x00001152, 0x08180403, 0x00012404, 0x06ff06ff, 0x01000f00, 0x1842a919, 0x46192301, + 0xf0004638, 0x2200fad9, 0x46384669, 0xf82bf7ff, 0xd1060004, 0x466a4633, 0x46384629, 0xfe68f7fe, + 0x46204604, 0xb530e4f0, 0x2403b089, 0x702c466d, 0x00492501, 0x95032400, 0x94029101, 0x742c466d, + 0x93084669, 0xf0009207, 0xb009f9c6, 0xb530bd30, 0x2402b089, 0x702c466d, 0x00492401, 0x94029101, + 0x21009403, 0x46697429, 0x92059306, 0xf9b3f000, 0x0000e7eb, 0x07406c00, 0x2001d501, 0x20004770, + 0x6c004770, 0xd5010680, 0x47702001, 0x47702000, 0x07c06c00, 0x2001d000, 0x6c004770, 0xd5010700, + 0x47702001, 0x47702000, 0x07806c00, 0x2001d501, 0x20004770, 0x6c004770, 0xd5010640, 0x47702001, + 0x47702000, 0xb085b5f3, 0x2404460e, 0xf0009805, 0x0005fcce, 0x2e00d07e, 0x7b30d07c, 0xd8792803, + 0xd00a2800, 0xd0082801, 0xd0062802, 0xd1042803, 0xf7ff4630, 0x2800ffd9, 0x20ffd002, 0xe00c3001, + 0x2102aa03, 0xf7fd9805, 0x49fefc94, 0x42889803, 0x6c30d306, 0xd4030600, 0x90002079, 0xe0219001, + 0x00602400, 0x31601981, 0x7e0f7e48, 0xd10b2800, 0x43472064, 0x214bd01d, 0xf0004638, 0x214bfe77, + 0x42b94341, 0x1c40d200, 0x283f213f, 0x4608d900, 0x0c400680, 0x30ff00a2, 0x46693001, 0x50881c64, + 0xd3de2c02, 0x22026828, 0x28000780, 0x2000da1c, 0x4630e01e, 0xff9ff7ff, 0x46024607, 0x9805a902, + 0xfc82f7fd, 0x990248e0, 0xd0092f00, 0xfe4ef000, 0x217d0880, 0x434800c9, 0xf000214b, 0xe7d2fe47, + 0xfe44f000, 0xe7f40840, 0x20016829, 0x60294311, 0x29006d31, 0x6d71d102, 0xd0022900, 0x9b0021c0, + 0x6db1514b, 0xd1022900, 0x29006df1, 0x21c4d004, 0xe0009b01, 0x514be006, 0xd0022800, 0x43906828, + 0x24006028, 0xb0074620, 0xb5f8bdf0, 0x20044607, 0x460e461c, 0xd0162f00, 0xd0142a00, 0xd0122c00, + 0x48c14611, 0xfe12f000, 0x46054601, 0x46304361, 0xfe0cf000, 0x1c40e000, 0x43694601, 0x42b14361, + 0x6038d3f9, 0xbdf82000, 0xb085b5f0, 0x460e4db7, 0x95004607, 0xf0009501, 0x0004fc1a, 0x2e00d02b, + 0xaa02d029, 0x46382102, 0xfbf3f7fd, 0x2101aa03, 0xf7fd4638, 0x2601fbee, 0x02b64fad, 0x46394633, + 0x9a024668, 0xffc1f7ff, 0x46394633, 0x9a03a801, 0xffbbf7ff, 0x42a89800, 0x9500d900, 0x42a89801, + 0x9501d900, 0x99019800, 0xb2890400, 0x60604308, 0xb0052000, 0x2004bdf0, 0xb5f3e7fb, 0x2000b087, + 0x460c9000, 0x98072504, 0xfbe1f000, 0x28009003, 0x2c00d054, 0x4620d052, 0x46273040, 0x37509005, + 0x30ff2600, 0x90023041, 0x00b26838, 0x98030a81, 0x90011810, 0x7ba06601, 0x06c51d3f, 0x0eed7b60, + 0x0d8006c0, 0x7be04305, 0x0c400700, 0x46204305, 0xfed3f7ff, 0xd0022800, 0x02802001, 0x6f604305, + 0xd00d2800, 0x2102aa04, 0xf7fd9807, 0x2301fb92, 0x46686f61, 0xf7ff9a04, 0x9800ff68, 0x43050400, + 0x67059801, 0x79c09805, 0xd00e2800, 0x7c009802, 0xd00a0741, 0x22079902, 0x03407c49, 0x0d090709, + 0x18800352, 0x4308b280, 0x2009e001, 0x99010200, 0x60083180, 0x2e041c76, 0x2500d3b6, 0xb0094628, + 0x4602bdf0, 0x2004b510, 0xd0212a00, 0xd01f2900, 0x5c402044, 0xd10c2801, 0x084368d0, 0x2040005b, + 0x46084303, 0xfe76f7ff, 0xd0012800, 0x43032001, 0x68d060d3, 0x43082120, 0x4b5e60d0, 0x00812000, + 0x6a0c1889, 0x620c401c, 0x28031c40, 0x2000d3f7, 0xb510bd10, 0xfb5bf000, 0xd00b2800, 0x23012100, + 0x008a07db, 0x32801812, 0x431c6814, 0x1c496014, 0xd3f62904, 0xb5febd10, 0x20044605, 0x460e9000, + 0xf0004628, 0x0004fb44, 0x2e00d07e, 0x7830d0fc, 0xd8792803, 0x90017c30, 0x46202700, 0xfb3ff000, + 0xf7ff4628, 0x6960ffd6, 0x4308211e, 0x46256160, 0x68703580, 0x78306228, 0xd0022802, 0xd0022803, + 0x8b30e003, 0x8c30e000, 0x7b31b287, 0x1e497a30, 0x07490700, 0x09490b00, 0x99014308, 0x430807c9, + 0x62684338, 0x28037830, 0x69f0d14b, 0x07836a32, 0x2340d14a, 0x469e211c, 0x6bab63a9, 0x430b2101, + 0x6bab63ab, 0xd1fc07db, 0x430b6b2b, 0xe036632b, 0x31f91de1, 0x45724673, 0x6967d30f, 0x06bf089b, + 0xe029d402, 0xc080c980, 0xd2fb1e5b, 0x1a524671, 0x23206961, 0x61614319, 0x6f2be01e, 0x0d5b061b, + 0xd2034293, 0xc908e018, 0xc0081f12, 0xd2fa2a04, 0xd0102a00, 0x91016809, 0x468ca901, 0x23004601, + 0x4667e007, 0x700f783f, 0x1c7f4667, 0x46bc1c49, 0x42931c5b, 0x2200d3f5, 0x07096961, 0x2a00d401, + 0x7830d1c6, 0xe0002802, 0xd001e062, 0xd1482801, 0x69b26971, 0xd15b0788, 0x46842040, 0x63e8201c, + 0xe0096be8, 0x05f5e100, 0x3b9aca00, 0x0000ffff, 0x1dcd6500, 0xfcf0ff00, 0x43182301, 0x6be863e8, + 0xd1fc07c0, 0xe02a4686, 0x30ff4620, 0x30816963, 0xd521065b, 0x089b4663, 0xd2024562, 0xc980e00e, + 0x1e5bc080, 0x4660d2fb, 0xe0091a12, 0xdd032a00, 0xc080c980, 0xe0011f12, 0xc0802700, 0xd2f51e5b, + 0x28004670, 0x6b28d104, 0x43182301, 0x469e6328, 0x23406960, 0x61604318, 0x07006960, 0x2a00d401, + 0x7830dcd2, 0xd1032800, 0x21016b28, 0x63284308, 0xf0004620, 0x6960fa74, 0xd50b0700, 0x01006e68, + 0x280e0f00, 0x48fed001, 0x48fde001, 0x90001e40, 0xbdfe9800, 0xe7fa2000, 0x460eb5f8, 0x461f2104, + 0x91004615, 0xfa53f000, 0xd0230004, 0xd0212d00, 0x19f22100, 0x23104149, 0x1a9a2000, 0xd3194188, + 0xf0004620, 0x4aeffa4c, 0x200261a2, 0x19f161e0, 0x008b00b0, 0x19090081, 0x31ff31ff, 0xe0023102, + 0xc140cd40, 0x42981c40, 0x61a2d3fa, 0x61e02001, 0x90002000, 0xbdf89800, 0x4604b570, 0xb08a2004, + 0xd0242900, 0x466e2000, 0x20037030, 0x90022501, 0x74329503, 0x93012047, 0x28005c40, 0x4608d009, + 0x308130ff, 0x2a007a02, 0x7a42d003, 0x7a009202, 0x98029003, 0x01009b03, 0x21011842, 0x32804620, + 0xffaaf7ff, 0x46204669, 0xf7ff9502, 0xb00afeb4, 0xb5ffbd70, 0xb0912004, 0x900e460d, 0xd0792900, + 0x30404628, 0x21018f82, 0x4094460c, 0x93028fc2, 0x22039200, 0x711a466b, 0x91039104, 0x9108a90c, + 0x29009913, 0x2108d001, 0x2104e000, 0x99139109, 0x79c07519, 0xd0092800, 0x30ff4628, 0x79013081, + 0xd0032900, 0x91037941, 0x90047900, 0x9b049803, 0x19420100, 0x99033280, 0xf7ff9811, 0x6f2dff6d, + 0xd0012d00, 0xe0002001, 0x26002000, 0xa901900f, 0xf7ff9811, 0x900efe70, 0xd13b2800, 0x28009813, + 0xa90ad019, 0xab0ca80b, 0x781f2208, 0x785f700f, 0x1c407007, 0x1e921c49, 0x2a001c9b, 0x9800d1f5, + 0x2800990b, 0xd004980a, 0x46214008, 0xd10a4381, 0x4308e00e, 0x9800e00a, 0xd0062800, 0x4620990c, + 0x28004388, 0x2701d004, 0x980ce003, 0xe7f84020, 0x980f2700, 0xd00b4207, 0x43304628, 0x207dd00d, + 0x210000c0, 0xf9aaf7fd, 0x43c02000, 0x41461e6d, 0xd1bc2f00, 0xb015980e, 0x4889bdf0, 0x900e1c40, + 0xb5f7e7f8, 0x460db08a, 0x980a2604, 0xf96ff000, 0xd0540007, 0xd0522d00, 0x46692001, 0x980c7008, + 0x20009001, 0x20047408, 0x90062400, 0x194200a0, 0x30204610, 0x29007841, 0x2301d03e, 0x59db025b, + 0x0f9b059b, 0x192bd003, 0x2b027f5b, 0x9102d034, 0x32307800, 0x90039205, 0x46292200, 0x980a9b0c, + 0xff1af7ff, 0xd12b2800, 0x21019802, 0x19420100, 0x9b033280, 0xf7ff980a, 0x2001fedf, 0x46699002, + 0xf7ff980a, 0x0006fde8, 0x8a68d11a, 0xd10e2800, 0x7f491929, 0xd00a2902, 0xd0082903, 0x46292200, + 0x980a9b0c, 0xff25f7ff, 0xd1090006, 0x2164e004, 0x21004348, 0xf942f7fd, 0x2c031c64, 0x4630d3b6, + 0xbdf0b00d, 0xb087b5f3, 0x2604460d, 0xf0009807, 0x0004f90e, 0x2d00d07e, 0x7c28d0fc, 0xd1022800, + 0x28007f28, 0x6c28d009, 0xd40406c0, 0xf7ff4628, 0x2800fc22, 0x2001d001, 0x2000e000, 0x494a9003, + 0x42886828, 0x9807d166, 0xf87bf7fd, 0x98074629, 0xf95ef7fd, 0x30404628, 0x90029903, 0xd0022900, + 0x21012200, 0x4628e005, 0xfc05f7ff, 0x98024602, 0x98077981, 0xf86df7fd, 0xf7fd9807, 0x6820f85a, + 0x43b02602, 0x46206020, 0xf8c9f000, 0x43306820, 0x68206020, 0x40084935, 0x79499902, 0xd1012908, + 0x43080289, 0x43084932, 0x07897b29, 0x43010e89, 0x46296021, 0xf7ff9807, 0x68a0fc97, 0x03c92101, + 0x60a04388, 0xf7ff4628, 0x2800fbc3, 0x68a0d004, 0x04c92101, 0x60a04308, 0x46204629, 0xfd21f7ff, + 0x98074629, 0xfcb9f7ff, 0x98074629, 0xfbcaf7ff, 0x21026820, 0x60204388, 0xf0004620, 0x4628f890, + 0x30507c29, 0x29009004, 0x9807d01c, 0x20049005, 0xe0002100, 0x9e04e05d, 0x460f9100, 0x9101ce02, + 0xd00a2900, 0x9a004629, 0xf0009805, 0x2800f890, 0x9a01d106, 0x18899900, 0x1c7f9100, 0xd3ed2f04, + 0xd1460006, 0x28007f28, 0x9807d027, 0x20049005, 0xd0202d00, 0x9e042100, 0x460f9100, 0xe009ce02, + 0x00001b59, 0x5af05af0, 0x42464346, 0x0000df0f, 0xffff0000, 0x29009101, 0x4629d00a, 0x98059a00, + 0xfedff7ff, 0xd1062800, 0x99009a01, 0x91001889, 0x2f041c7f, 0x0006d3e2, 0x9803d11b, 0xd0172800, + 0x26026820, 0x60204330, 0xf7ff4628, 0x4602fb64, 0x79819802, 0xf7fc9807, 0x4629ffcc, 0xf7ff9807, + 0x4629fc13, 0xf7ff9807, 0x6820fb5d, 0x602043b0, 0x46302600, 0xb510e4a3, 0xf829f000, 0xd0032800, + 0x6e013080, 0xd5fc0789, 0xb510bd10, 0xf81ff000, 0xd0012800, 0xf813f000, 0xb570bd10, 0xf000460d, + 0x0004f816, 0xf000d00a, 0x2001f81a, 0x682102c0, 0xd0012d00, 0xe0004301, 0x60214381, 0x6801bd70, + 0x43112201, 0x68016001, 0xd1fc07c9, 0x46014770, 0x29002000, 0x4830d102, 0x68004478, 0x30804770, + 0x07c96e01, 0x6e01d0fc, 0xd5fc0789, 0xb5f04770, 0x4616b089, 0x4607460c, 0xf7ff2504, 0x2800ffe8, + 0x2c00d048, 0x30ffd046, 0x300230ff, 0x05806800, 0xd0020f80, 0x28027c60, 0x2501d025, 0x700d4669, + 0x7d609601, 0x7d209002, 0x20009003, 0x46207408, 0x90053018, 0x90062004, 0x22004633, 0x46384621, + 0xfd9af7ff, 0x21019802, 0x19020100, 0x32804638, 0xf7ff9b03, 0x4669fd61, 0x95024638, 0xfc6bf7ff, + 0xd1170005, 0x2500e001, 0x8a61e014, 0xd10c2900, 0x28027c60, 0x2803d009, 0x4633d007, 0x46212200, + 0xf7ff4638, 0x4605fda6, 0x2064e004, 0x21004348, 0xffc4f7fc, 0xe4124628, 0x00000708, 0x88014843, + 0x07492204, 0xda022900, 0x43918801, 0x48408001, 0x07498801, 0x8801d502, 0x80014391, 0x493d483e, + 0x493e6041, 0x68016081, 0x43912280, 0x43112220, 0x483b6001, 0x07c96901, 0x6901d003, 0x00490849, + 0x47706101, 0x4c37b5f8, 0x4a376960, 0x01804937, 0x69a0d518, 0x031b2303, 0xd0054018, 0x03122201, + 0xd00a4290, 0xe0092000, 0x07806910, 0x2016d001, 0x2014e000, 0x4348492d, 0x4608e000, 0x00896961, + 0xe0290f49, 0x4b296810, 0x0e400640, 0x08474358, 0x07c06b10, 0x2516d001, 0x2514e000, 0x43454823, + 0x30404821, 0x69006a06, 0xfa1af000, 0x23004632, 0xf844f000, 0x194069a1, 0x40114a1d, 0x2201d011, + 0x4b1c0492, 0xd0161a89, 0xd0171a89, 0xd1074291, 0x07416920, 0x46380f49, 0xf0001c49, 0xe000f907, + 0x69612000, 0x0f4904c9, 0xf0001c49, 0x4912f8ff, 0x60084449, 0x6819bdf8, 0xe0000c09, 0x06896819, + 0xf0000e89, 0x2112f8f3, 0xe7ea4348, 0x400b8000, 0x400d0000, 0xd928c520, 0x400bc000, 0x0000ffff, + 0xe000e000, 0x400fc000, 0x400d8000, 0x016e3600, 0x000c0000, 0x400d8100, 0x0000000c, 0x4605b5fe, + 0x460c4610, 0xd0734318, 0x468c46ae, 0x1aad2000, 0x419c4601, 0x4666d367, 0x24012700, 0x1ab6463d, + 0xd302419d, 0x463a4613, 0x46652421, 0x042f4676, 0x433e0c36, 0x1ab60c2d, 0xd304419d, 0x041b0c15, + 0x0412432b, 0x46653410, 0x062f4676, 0x433e0a36, 0x1ab60a2d, 0xd304419d, 0x021b0e15, 0x0212432b, + 0x46653408, 0x072f4676, 0x433e0936, 0x1ab6092d, 0xd304419d, 0x011b0f15, 0x0112432b, 0x46651d24, + 0x07af4676, 0x433e08b6, 0x1ab608ad, 0xd304419d, 0x009b0f95, 0x0092432b, 0x46651ca4, 0x07ef4676, + 0x433e0876, 0x1ab6086d, 0xd31a419d, 0x415b1892, 0xe0161c64, 0x46761800, 0x41494665, 0x419d1ab7, + 0x90009101, 0x4660d309, 0x41981ab1, 0x4684468e, 0x99019800, 0x1c402500, 0x07dd4169, 0x432a0852, + 0x1e64085b, 0x4672d5e6, 0xb0034663, 0xe7ffbdf0, 0x46012000, 0x46c046c0, 0x4623462a, 0xb510e7f5, + 0xf0002000, 0x46c0f907, 0x200146c0, 0xf8fcf000, 0x4603bd10, 0x430bb510, 0xd10f079b, 0xd30d2a04, + 0xc910c808, 0x42a31f12, 0xba18d0f8, 0x4288ba21, 0x2001d901, 0x2000bd10, 0xbd1043c0, 0xd0032a00, + 0xd00307d3, 0xe0071c52, 0xbd102000, 0x780c7803, 0x1c491c40, 0xd1071b1b, 0x780c7803, 0x1c491c40, + 0xd1011b1b, 0xd1f11e92, 0xbd104618, 0xc004e001, 0x29041f09, 0x078bd2fb, 0x8002d501, 0x07c91c80, + 0x7002d000, 0x29004770, 0x07c3d00b, 0x7002d002, 0x1e491c40, 0xd3042902, 0xd5020783, 0x1c808002, + 0xe7e31e89, 0xe7ee2200, 0xe7df2200, 0x09032200, 0xd32c428b, 0x428b0a03, 0x2300d311, 0xe04e469c, + 0x430b4603, 0x2200d43c, 0x428b0843, 0x0903d331, 0xd31c428b, 0x428b0a03, 0x4694d301, 0x09c3e03f, + 0xd301428b, 0x1ac001cb, 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152, 0xd301428b, 0x1ac0014b, + 0x09034152, 0xd301428b, 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb, 0x08834152, 0xd301428b, + 0x1ac0008b, 0x08434152, 0xd301428b, 0x1ac0004b, 0x1a414152, 0x4601d200, 0x46104152, 0xe05d4770, + 0xd0000fca, 0x10034249, 0x4240d300, 0x22004053, 0x0903469c, 0xd32d428b, 0x428b0a03, 0x22fcd312, + 0xba120189, 0x428b0a03, 0x0189d30c, 0x428b1192, 0x0189d308, 0x428b1192, 0x0189d304, 0x1192d03a, + 0x0989e000, 0x428b09c3, 0x01cbd301, 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0, 0x428b0943, + 0x014bd301, 0x41521ac0, 0x428b0903, 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301, 0x41521ac0, + 0x428b0883, 0x008bd301, 0x41521ac0, 0x0843d2d9, 0xd301428b, 0x1ac0004b, 0x1a414152, 0x4601d200, + 0x41524663, 0x4610105b, 0x4240d301, 0xd5002b00, 0x47704249, 0x105b4663, 0x4240d300, 0x2000b501, + 0x46c046c0, 0x0000bd02, 0x20184901, 0xe7febeab, 0x00020026, 0xf000b510, 0xf000f80b, 0xbd10f802, + 0xb5104770, 0xd0012800, 0xffeef7ff, 0x0000bd10, 0x2100b510, 0xf000a002, 0x2001f813, 0x0000bd10, + 0x41474953, 0x3a545242, 0x6e624120, 0x616d726f, 0x6574206c, 0x6e696d72, 0x6f697461, 0x0000006e, + 0x4605b570, 0x200a460c, 0x1c6de000, 0xf812f000, 0xd0062d00, 0x28007828, 0xe002d1f7, 0xf0001c64, + 0x2c00f809, 0x7820d002, 0xd1f72800, 0xf000200a, 0xbd70f801, 0x4669b508, 0x20037008, 0xbd08beab, + 0x0c04b5f8, 0x4626b28b, 0x435eb282, 0x46100c0d, 0x43580c37, 0x19800436, 0x41792100, 0x436e4616, + 0x04360c37, 0x41791980, 0x436e4626, 0xbdf81989, 0x4674b430, 0x78251e64, 0x42ab1c64, 0x461dd200, + 0x005b5d63, 0xbc3018e3, 0x00004718, 0x08220000, 0x06180816, 0x0612041e, 0x0411060e, 0x0216060c, + 0x06180000, 0x060c0416, 0x0312021e, 0x01210216, 0x0116011a, 0x017d7840, 0x02faf080, 0x05f5e100, + 0x07735940, 0x33221100, 0x77665544, 0xbbaa9988, 0xffeeddcc, 0x0818045a, 0x24ff3008, 0x00000000, + 0x00000000, 0x0918055a, 0x25ff3108, 0x00000000, 0x00000000, 0x0a18065a, 0x26ff3208, 0x00000000, + 0x00000000, 0x2403049f, 0x00000000, 0x00000000, 0x00000000, 0x0760079f, 0x27040b20, 0x00000000, + 0x00000000, 0x8760879f, 0xa7048b20, 0x00000000, 0x00000000, 0x0818045a, 0x24ff3008, 0x00000000, + 0x00000000, 0x8b20075a, 0x0000a7ff, 0x00000000, 0x00000000, 0x0818045a, 0x24ff3008, 0x00000000, + 0x00000000, 0x0a18065a, 0x000026ff, 0x00000000, 0x00000000, 0x0b18075a, 0x000027ff, 0x00000000, + 0x00000000, 0x8a18065a, 0x0000a6ff, 0x00000000, 0x00000000, 0x8b20075a, 0x0000a7ff, 0x00000000, + 0x00000000, 0x402a8000, 0x00000000, 0x00000000, 0x00000000, 0x1f78a400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -501,40 +506,50 @@ static const uint32_t MIMXRT105x_QuadSPI_4KB_SEC_flash_prog_blob[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; +// Start address of flash +static const uint32_t flash_start = 0x60000000; +// Size of flash +static const uint32_t flash_size = 0x00800000; + /** -* List of start and size for each size of flash sector +* List of start and size for each size of flash sector - even indexes are start, odd are size * The size will apply to all sectors between the listed address and the next address * in the list. * The last pair in the list will have sectors starting at that address and ending -* at address start + size. +* at address flash_start + flash_size. */ static const sector_info_t sectors_info[] = { {0x60000000, 0x00001000}, }; static const program_target_t flash = { - 0x20000091, // Init - 0x200000b7, // UnInit - 0x200000bb, // EraseChip - 0x200000cf, // EraseSector - 0x200000ed, // ProgramPage - 0x0, // Verify - + 0x20000075, // Init + 0x200000e1, // UnInit + 0x200000e5, // EraseChip + 0x200000f9, // EraseSector + 0x20000117, // ProgramPage + 0x00000000, // Verify + // BKPT : start of blob + 1 // RSB : blob start + header + rw data offset // RSP : stack pointer { 0x20000001, - 0x20003a24, - 0x20000800 + 0x20003a6c, + 0x20007d00 }, - 0x20000000 + 0x00000A00, // mem buffer location - 0x20000000, // location to write prog_blob in target RAM - sizeof(MIMXRT105x_QuadSPI_4KB_SEC_flash_prog_blob), // prog_blob size - MIMXRT105x_QuadSPI_4KB_SEC_flash_prog_blob, // address of prog_blob - 0x00000100 // ram_to_flash_bytes_to_be_written + // mem buffer location + 0x20007d00, + // location to write prog_blob in target RAM + 0x20000000, + // prog_blob size + sizeof(MIMXRT105x_QuadSPI_4KB_SEC_flash_prog_blob), + // address of prog_blob + MIMXRT105x_QuadSPI_4KB_SEC_flash_prog_blob, + // ram_to_flash_bytes_to_be_written + 0x00000100 }; From 6bef62b53406bba33371ff26c7aa2df7a193ca72 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 30 Dec 2021 23:42:43 -0600 Subject: [PATCH 575/617] mimxrt: update flash algorithms for MIMXRT1020 python tools/generate_flash_algo.py \ MIMXRT1021_DFP/arm/MIMXRT1021_QuadSPI_4KB_SEC.FLM --pack-path NXP.MIMXRT1021_DFP.13.1.1.pack \ -o source/family/freescale/mimxrt1020_spi_flash/flash_blob.c --stack-size 4096 --- .../mimxrt1020_spi_flash/flash_blob.c | 1078 ++++++++--------- 1 file changed, 490 insertions(+), 588 deletions(-) diff --git a/source/family/freescale/mimxrt1020_spi_flash/flash_blob.c b/source/family/freescale/mimxrt1020_spi_flash/flash_blob.c index 17b6a1b85..b25a42764 100644 --- a/source/family/freescale/mimxrt1020_spi_flash/flash_blob.c +++ b/source/family/freescale/mimxrt1020_spi_flash/flash_blob.c @@ -1,5 +1,8 @@ -/* Flash OS Routines (Automagically Generated) - * Copyright (c) 2009-2019 ARM Limited +/* Flash algorithm for MIMXRT1020 8mB QuadSPI NOR Flash + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2021 Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -14,578 +17,473 @@ * limitations under the License. */ -#include "flash_blob.h" - -static const uint32_t RT1020_S25LP064A_flash_prog_blob[] = { - 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, +// Generated from 'MIMXRT1021_QuadSPI_4KB_SEC.FLM' (MIMXRT1020 8mB QuadSPI NOR Flash) +// Originating from 'NXP.MIMXRT1021_DFP.13.1.1.pack' +// digest = 19f93d076c7c4a284ea0129485399d12b09ccb6b68e4e47b53b43b535eb0cac9, file size = 2477896 +// algo version = 0x101, algo size = 15268 (0x3ba4) +static const uint32_t MIMXRT1021_QuadSPI_4KB_SEC_flash_prog_blob[] = { + 0xe7fdbe00, 0x4605b570, 0x4616460c, 0xcc0fe002, 0x3e10c50f, 0xd2fa2e10, 0xd3022e08, 0xc503cc03, 0x2e043e08, 0xcc01d307, 0x1f36c501, 0x7821e003, 0x1c647029, 0x1e761c6d, 0xbd70d2f9, 0x4770ba40, 0x4770ba40, - 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770bac0, - 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x4770bac0, - 0x4605b5fe, 0x460c4610, 0xd0734318, 0x468c46ae, 0x1aad2000, 0x419c4601, 0x4666d367, 0x24012700, - 0x1ab6463d, 0xd302419d, 0x463a4613, 0x46652421, 0x042f4676, 0x433e0c36, 0x1ab60c2d, 0xd304419d, - 0x041b0c15, 0x0412432b, 0x46653410, 0x062f4676, 0x433e0a36, 0x1ab60a2d, 0xd304419d, 0x021b0e15, - 0x0212432b, 0x46653408, 0x072f4676, 0x433e0936, 0x1ab6092d, 0xd304419d, 0x011b0f15, 0x0112432b, - 0x46651d24, 0x07af4676, 0x433e08b6, 0x1ab608ad, 0xd304419d, 0x009b0f95, 0x0092432b, 0x46651ca4, - 0x07ef4676, 0x433e0876, 0x1ab6086d, 0xd31a419d, 0x415b1892, 0xe0161c64, 0x46761800, 0x41494665, - 0x419d1ab7, 0x90009101, 0x4660d309, 0x41981ab1, 0x4684468e, 0x99019800, 0x1c402500, 0x07dd4169, - 0x432a0852, 0x1e64085b, 0x4672d5e6, 0xb0034663, 0xe7ffbdf0, 0x46012000, 0x46c046c0, 0x4623462a, - 0xb510e7f5, 0xf0002000, 0x46c0f907, 0x200146c0, 0xf8fcf000, 0x4603bd10, 0x430bb510, 0xd10f079b, - 0xd30d2a04, 0xc910c808, 0x42a31f12, 0xba18d0f8, 0x4288ba21, 0x2001d901, 0x2000bd10, 0xbd1043c0, - 0xd0032a00, 0xd00307d3, 0xe0071c52, 0xbd102000, 0x780c7803, 0x1c491c40, 0xd1071b1b, 0x780c7803, - 0x1c491c40, 0xd1011b1b, 0xd1f11e92, 0xbd104618, 0xc004e001, 0x29041f09, 0x078bd2fb, 0x8002d501, - 0x07c91c80, 0x7002d000, 0x29004770, 0x07c3d00b, 0x7002d002, 0x1e491c40, 0xd3042902, 0xd5020783, - 0x1c808002, 0xe7e31e89, 0xe7ee2200, 0xe7df2200, 0x09032200, 0xd32c428b, 0x428b0a03, 0x2300d311, - 0xe04e469c, 0x430b4603, 0x2200d43c, 0x428b0843, 0x0903d331, 0xd31c428b, 0x428b0a03, 0x4694d301, - 0x09c3e03f, 0xd301428b, 0x1ac001cb, 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152, 0xd301428b, - 0x1ac0014b, 0x09034152, 0xd301428b, 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb, 0x08834152, - 0xd301428b, 0x1ac0008b, 0x08434152, 0xd301428b, 0x1ac0004b, 0x1a414152, 0x4601d200, 0x46104152, - 0xe05d4770, 0xd0000fca, 0x10034249, 0x4240d300, 0x22004053, 0x0903469c, 0xd32d428b, 0x428b0a03, - 0x22fcd312, 0xba120189, 0x428b0a03, 0x0189d30c, 0x428b1192, 0x0189d308, 0x428b1192, 0x0189d304, - 0x1192d03a, 0x0989e000, 0x428b09c3, 0x01cbd301, 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0, - 0x428b0943, 0x014bd301, 0x41521ac0, 0x428b0903, 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301, - 0x41521ac0, 0x428b0883, 0x008bd301, 0x41521ac0, 0x0843d2d9, 0xd301428b, 0x1ac0004b, 0x1a414152, - 0x4601d200, 0x41524663, 0x4610105b, 0x4240d301, 0xd5002b00, 0x47704249, 0x105b4663, 0x4240d300, - 0x2000b501, 0x46c046c0, 0x0000bd02, 0x20184901, 0xe7febeab, 0x00020026, 0xf000b510, 0xf000f80b, - 0xbd10f802, 0xb5104770, 0xd0012800, 0xffeef7ff, 0x0000bd10, 0x2100b510, 0xf000a002, 0x2001f813, - 0x0000bd10, 0x41474953, 0x3a545242, 0x6e624120, 0x616d726f, 0x6574206c, 0x6e696d72, 0x6f697461, - 0x0000006e, 0x4605b570, 0x200a460c, 0x1c6de000, 0xf812f000, 0xd0062d00, 0x28007828, 0xe002d1f7, - 0xf0001c64, 0x2c00f809, 0x7820d002, 0xd1f72800, 0xf000200a, 0xbd70f801, 0x4669b508, 0x20037008, - 0xbd08beab, 0x06c00a02, 0x0ec0b510, 0xd9012a06, 0xfea7f7ff, 0x00924b05, 0x681318d2, 0x40842403, - 0x408143a3, 0x6013430b, 0x0000bd10, 0x400fc068, 0x06c00a02, 0x0ec0b510, 0xd9012a06, 0xfe91f7ff, - 0x00924b05, 0x681318d2, 0x40842403, 0x408143a3, 0x6013430b, 0x0000bd10, 0x400fc068, 0x49022001, - 0x63080300, 0x00004770, 0x400d8040, 0x49022001, 0x62080300, 0x00004770, 0x400d80c0, 0x49022001, - 0x61480780, 0x00004770, 0x400d8140, 0x6b014802, 0x00490849, 0x47706301, 0x400d8240, 0x680a4903, - 0x208000c3, 0x43024098, 0x4770600a, 0x400d8100, 0x49022001, 0x63080300, 0x00004770, 0x400d8000, - 0x6b0a4903, 0x208000c3, 0x43024098, 0x4770630a, 0x400d80c0, 0x20004901, 0x47706108, 0x400d8000, - 0x20004904, 0x48046108, 0x04826b01, 0x63014311, 0x00004770, 0x400d8000, 0x400d9000, 0x480eb508, - 0x22036801, 0x60014311, 0x6801480c, 0x43112202, 0x20006001, 0x480a9000, 0x9900bf00, 0x91001c49, - 0xd3f94281, 0x6a084907, 0x0212221f, 0x4a064390, 0x62084310, 0xbd082001, 0x400fc080, 0x402e0140, - 0x00061a80, 0x400d8100, 0x00001701, 0x2200b508, 0x92004668, 0xfa7af000, 0x6b014808, 0x08490049, - 0x6b016301, 0x43990483, 0x60026301, 0x22636b01, 0x43110392, 0x20016301, 0x0000bd08, 0x400d9000, - 0x4c34b510, 0xf0010003, 0x0d17f843, 0x362a120d, 0x3e3c6339, 0x63444240, 0x4e4c4a48, 0x59565450, - 0x00635f5c, 0xf870f000, 0x0a896961, 0x6960e011, 0xd50a0640, 0x06006960, 0x2001d503, 0xf966f000, - 0x2002e005, 0xf93cf000, 0xf000e001, 0x6961f85d, 0x07490c09, 0x1c490f49, 0xfe1af7ff, 0xf000bd10, - 0x6961f853, 0x0f4904c9, 0xf7ff1c49, 0x6961fe11, 0x0f890589, 0xf000e7ef, 0xbd10f837, 0x03c02001, - 0x4815bd10, 0x2000e021, 0x2001e004, 0x2002e002, 0x2003e000, 0xf93af000, 0x4810bd10, 0x2000e015, - 0x2001e004, 0x2002e002, 0x2003e000, 0xf908f000, 0x480bbd10, 0x480ae009, 0xe0061dc0, 0x30084808, - 0x4807e003, 0xe0003009, 0xf0004806, 0xbd10f85f, 0xbd102000, 0x400fc000, 0x0010000d, 0x0030000d, - 0x00e0000d, 0x0070000d, 0x6b004804, 0xd50106c0, 0x47704803, 0x44484803, 0x47706800, 0x400d8240, - 0x016e3600, 0x00000050, 0x4c1cb510, 0x01816960, 0x69a1481b, 0x1202d517, 0xd00d4011, 0x03122201, - 0xd00d1a89, 0xd0084291, 0x69612000, 0x0f490089, 0xf7ff1c49, 0xbd10fdad, 0xf0004812, 0xe7f4f827, - 0xffd2f7ff, 0x2203e7f1, 0x40110492, 0x2201d00b, 0x1a880492, 0x1a80d00a, 0x4290d00c, 0x480ad101, - 0x2000bd10, 0xf000bd10, 0xbd10f811, 0xf0002003, 0xbd10f8a7, 0xf0002003, 0xbd10f8c9, 0x400fc000, - 0x0030000d, 0x0010000d, 0x1dcd6500, 0x4605b5f0, 0xb0854843, 0xc80f4478, 0xc40f466c, 0x01284e41, + 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770bac0, 0x4770bac0, 0x4770bac0, + 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x482fb51c, 0x482f9000, 0x08498901, 0x81010049, + 0x890a492d, 0x00520852, 0x8802810a, 0x07522304, 0xda022a00, 0x439a8802, 0x88088002, 0xd5020740, + 0x43988808, 0x48268008, 0x60414924, 0x60814925, 0x22806801, 0x22204391, 0x60014311, 0x466a4922, + 0x20004449, 0xf9f8f002, 0xd1052800, 0x4449491e, 0xfd3af000, 0xd0002800, 0xbd1c2001, 0x47702000, + 0xb5104919, 0x20004449, 0xfe91f000, 0xd0002800, 0xbd102001, 0x07492105, 0x49131842, 0x2301b510, + 0x4449031b, 0xf0022000, 0x2800fa2d, 0x2001d000, 0x2105bd10, 0x07494613, 0x490b1842, 0x4449b510, + 0xf0002000, 0x2800fe15, 0x2001d000, 0x0000bd10, 0xc0000006, 0x400b8000, 0x400d0000, 0xd928c520, + 0x400bc000, 0x0000ffff, 0x00000010, 0x4605b5f0, 0xb08548f7, 0xc80f4478, 0xc40f466c, 0x01284ef5, 0x59f00d07, 0x0ed206ea, 0x40912101, 0xd00a4008, 0x040059f0, 0xd0080f80, 0x46042000, 0x03c059f0, - 0xd0050fc0, 0xb0054620, 0xf7ffbdf0, 0xe7f4ff8d, 0x4b344935, 0x33c01a68, 0x428d466a, 0xdc31d056, - 0x18284832, 0x2101d046, 0x4f310549, 0xd02f1a40, 0x42880049, 0x6b38d12a, 0x0646492d, 0x31400e76, - 0x4620690d, 0xf0006809, 0x462aff2b, 0xf7ff2300, 0x4374fc67, 0x18206b39, 0x04d22203, 0xd0314011, - 0x04d22201, 0xd1004291, 0x49220840, 0x4a226b09, 0x22014011, 0x1a8903d2, 0x0212d026, 0xd1c24291, - 0xe7c00880, 0xd0232807, 0xd0272808, 0xe7ba2000, 0x46206a3d, 0xf0006939, 0x462aff03, 0xf7ff2300, - 0x6b31fc3f, 0xd00107c9, 0xe0002116, 0x434c2114, 0xe7a81820, 0x07806930, 0x2016d001, 0x2014e000, - 0xe7a04360, 0xe7d00880, 0xe79c0840, 0xe0016a18, 0x08806a18, 0x0f000780, 0xe7945810, 0xe7924807, - 0x00003f40, 0x400d8000, 0x00e0000d, 0xffeffff3, 0x400d8040, 0x400d8140, 0x00808000, 0x017d7840, - 0x4604b510, 0xf7ff480f, 0x490fff61, 0xd0092c00, 0xd0092c01, 0xd00e2c02, 0xd00f2c03, 0x21122000, - 0xbd104348, 0xe0016809, 0x0a096809, 0x0e890689, 0xfccef7ff, 0x6809e7f3, 0xe7f70c09, 0x0e096809, - 0x0000e7f4, 0x0030000d, 0x400d8100, 0x4604b510, 0xf7ff480f, 0x490fff3b, 0xd0092c00, 0xd0092c01, - 0xd00e2c02, 0xd00f2c03, 0x21122000, 0xbd104348, 0xe0016b09, 0x0a096b09, 0x0e890689, 0xfca8f7ff, - 0x6b09e7f3, 0xe7f70c09, 0x0e096b09, 0x0000e7f4, 0x0010000d, 0x400d80c0, 0x6841b530, 0x008b2200, - 0x089b4918, 0x6883600b, 0x089b009b, 0x7801610b, 0x06492301, 0x0e49035b, 0x18c97840, 0x2802019d, - 0x4b11d01d, 0x2804006c, 0x2808d017, 0x2810d013, 0x4321d00f, 0x33c04b0b, 0x4c0b6b18, 0x402043e4, - 0x63184310, 0x38404807, 0x6b016301, 0xdafc2900, 0x461abd30, 0x4329e7ee, 0x4321e7fb, 0x4329e7f9, - 0x0000e7e8, 0x400d8080, 0x00808000, 0x79027941, 0x07920789, 0x0f920f09, 0x78024311, 0xd0022a00, - 0x03522201, 0x78424311, 0xd0022a00, 0x05122201, 0x78824311, 0xd0022a00, 0x05522201, 0x78c04311, - 0xd0022800, 0x05802001, 0x48034301, 0x6a016201, 0xdafc2900, 0x00004770, 0x400d80c0, 0x2800b510, - 0xf7ffd001, 0x2101fbde, 0x07894807, 0x49076181, 0x03d26b0a, 0x2201d5fc, 0x61420412, 0x04096901, - 0x6182d5fc, 0x0000bd10, 0x400d8140, 0x400d8240, 0x6b014802, 0x43112201, 0x47706301, 0x400d8240, - 0x4b08b510, 0x00c0681a, 0x408424bf, 0x248043a2, 0x43144084, 0x0689601c, 0x40810e89, 0x60194311, - 0x0000bd10, 0x400d8100, 0x21017800, 0x0fc007c0, 0x18410349, 0x63014802, 0x29006b01, 0x4770dafc, - 0x400d8000, 0x4b08b510, 0x00c06b1a, 0x408424bf, 0x248043a2, 0x43144084, 0x0689631c, 0x40810e89, - 0x63194311, 0x0000bd10, 0x400d80c0, 0x21c17800, 0x0f800780, 0x18410189, 0x61014802, 0x29006901, - 0x4770dafc, 0x400d8000, 0x49032210, 0xd0012800, 0x4770638a, 0x4770634a, 0x400d8240, 0xb5104906, - 0x22002301, 0x444904db, 0xf0014610, 0x4803fd98, 0x68404448, 0x0000bd10, 0x0000005c, 0x00000004, - 0x49050102, 0x0912b510, 0x20004449, 0xfea2f001, 0x44494902, 0xbd106048, 0x0000005c, 0x00000004, - 0xf3bfb57c, 0xf3bf8f4f, 0x48188f6f, 0x22016a41, 0x43910412, 0x48156241, 0x69413080, 0x00490849, - 0x49136141, 0x62881740, 0x630862c8, 0x63886348, 0x490f63c8, 0x60083140, 0xfd98f000, 0xf926f003, - 0x2500480c, 0x9000490c, 0x4449466a, 0x46289501, 0xfd20f002, 0x49084c09, 0x6060444c, 0x20004449, - 0xfec2f001, 0x70256060, 0x0000bd7c, 0xe000ed00, 0x400fc040, 0xc0000005, 0x0000005c, 0x00000004, - 0xb5104805, 0x68414448, 0xd0032900, 0xf0004803, 0xbd10f96f, 0xfb05f7ff, 0x0000025c, 0x40184000, - 0xf7ffb510, 0xbd10ffed, 0xb5104805, 0x68814448, 0xd0032900, 0xf0004803, 0xbd10f95b, 0xfaf1f7ff, - 0x0000025c, 0x40188000, 0xf7ffb510, 0xbd10ffed, 0xb5104805, 0x68c14448, 0xd0032900, 0xf0004803, - 0xbd10f947, 0xfaddf7ff, 0x0000025c, 0x4018c000, 0xf7ffb510, 0xbd10ffed, 0xb5104805, 0x69014448, - 0xd0032900, 0xf0004803, 0xbd10f933, 0xfac9f7ff, 0x0000025c, 0x40190000, 0xf7ffb510, 0xbd10ffed, - 0xb5104805, 0x69414448, 0xd0032900, 0xf0004803, 0xbd10f91f, 0xfab5f7ff, 0x0000025c, 0x40194000, - 0xf7ffb510, 0xbd10ffed, 0x460cb510, 0x29006989, 0x2141d103, 0xf0000549, 0x2000f887, 0x20026120, - 0x73603420, 0xb510bd10, 0x2103460c, 0xf0000589, 0x2000f87b, 0x34206060, 0xbd107320, 0x460bb510, - 0x079a6a81, 0x00890889, 0x430a0f92, 0x69416282, 0x00490fda, 0x07d20849, 0x490b430a, 0x400a4c0a, - 0x43e44619, 0x43114021, 0x03a42401, 0x43a1461a, 0x430a4022, 0x43116941, 0xf0006141, 0x4018f8d1, - 0x4802d000, 0x0000bd10, 0xbfe0ffff, 0x0000051a, 0x461eb5f8, 0x000c4617, 0xd0264605, 0x46202130, - 0xfab4f7ff, 0x46202102, 0x73413020, 0x73012100, 0x62a66267, 0x21106ae8, 0x62e84388, 0xf0004628, - 0x4a0bf871, 0x444a0081, 0x490a5054, 0x44790040, 0x28005e08, 0x06c2db08, 0x21010ed2, 0x09404091, - 0x00804a05, 0x60011880, 0xf7ffbdf8, 0x0000fa3a, 0x0000025c, 0x00003962, 0xe000e100, 0x6ac1b510, - 0x0f490549, 0x6941d1fb, 0xd5fc0249, 0x61812100, 0xf848f000, 0x00404903, 0x5e084479, 0xf7ff2100, - 0xbd10fb87, 0x0000392a, 0x23c06902, 0x021b400b, 0x6102439a, 0x078b6a82, 0x439a0d9b, 0x0a096282, - 0x02096982, 0x6182438a, 0x69024770, 0x400b23c0, 0x431a021b, 0x6a826102, 0x0d9b078b, 0x6282431a, - 0x69820a09, 0x430a0209, 0x47706182, 0x2800b510, 0x21e1d00a, 0x60010249, 0x71012100, 0x71817141, - 0x720171c1, 0xbd107241, 0xf9ebf7ff, 0x22c06901, 0x40110a09, 0x69806a82, 0x0f920592, 0x4310430a, - 0x00004770, 0xb5104a08, 0x20004601, 0x0083447a, 0x428b58d3, 0x1c40d003, 0xd3f82808, 0x2808e001, - 0xf7ffd301, 0xbd10f9ce, 0x00003860, 0x5c40202d, 0xd0072802, 0xd0072a00, 0x69096948, 0x60101a40, - 0x47702000, 0x47702006, 0x47702004, 0x8c0a8c48, 0x8c084290, 0x69cad901, 0x8c491880, 0x47701a40, - 0x5c40202c, 0xd0072800, 0xd0072a00, 0x68496888, 0x60101a40, 0x47702000, 0x47702006, 0x47702004, - 0x6a806941, 0x0c0022c3, 0x43084010, 0x47704770, 0x4605b5f8, 0x460c6940, 0xd50d0300, 0x466969e8, - 0x78087008, 0x70081c40, 0x2e006a66, 0x4a5ed004, 0x46284621, 0x47b06aa3, 0x02816968, 0x30204620, - 0x29009000, 0x69a8da71, 0xd56e0280, 0x01406ae8, 0xe0260f46, 0x42b06920, 0x6920d201, 0x4630e000, - 0xb2c168e2, 0xe0022000, 0x541369eb, 0x460b1c40, 0xd3f94288, 0x184068e0, 0x692060e0, 0x61201a40, - 0xb2c61af0, 0x28006920, 0x9800d10b, 0x73412102, 0x2f006a67, 0x4a44d005, 0x1f924621, 0x6aa34628, - 0x2e0047b8, 0x6920d002, 0xd1d32800, 0x280069a0, 0xe032d12d, 0x46284621, 0xf926f000, 0xd0082800, - 0x2f006a67, 0x4a38d005, 0x1e524621, 0x6aa34628, 0x462147b8, 0xf0004628, 0x2800f917, 0x8c60d009, - 0x1c4069e1, 0xd1014288, 0xe0012000, 0x1c408c60, 0x69e88460, 0x69a18c22, 0x8c205488, 0x1c4069e1, - 0xd1014288, 0xe0012000, 0x1c408c20, 0x46308420, 0xb2f61e76, 0xd1cd2800, 0x6920e007, 0xd1042800, - 0x05492141, 0xf7ff4628, 0x6968feef, 0xd5390200, 0x020069a8, 0x6ae8d536, 0x05402104, 0x1a080f40, - 0xe02ab2c6, 0x42b06860, 0x6860d201, 0x4630e000, 0xb2c16822, 0xe0022000, 0x61eb5c13, 0x460b1c40, - 0xd3f94288, 0x18406820, 0x68606020, 0x60601a40, 0xb2c61af0, 0x28006860, 0x9900d10f, 0x69a87308, - 0x05c92101, 0x61a84388, 0x2f006a67, 0x4a06d005, 0x1fd24621, 0x6aa34628, 0x2e0047b8, 0x6860d002, - 0xd1cf2800, 0x0000bdf8, 0x0000051d, 0xb086b5f7, 0x4604000f, 0x6838d009, 0x28009005, 0x79b8d005, - 0xd8022804, 0x280479f8, 0xf7ffd901, 0x9805f8ba, 0x20009000, 0x25049001, 0x99059002, 0x43699808, - 0xf906f7ff, 0x0c360406, 0x2601d100, 0x43714629, 0xf7ff9808, 0x9905f8fd, 0x1c701a41, 0x46299103, - 0x43419004, 0xf7ff9808, 0x9905f8f3, 0x99031a08, 0xd2024288, 0x98049003, 0x9900b286, 0x42889803, - 0x4669d801, 0x1c6dc161, 0xd9d62d20, 0x98052164, 0xf8def7ff, 0x18410041, 0x42819800, 0x4830d202, - 0xbdf0b009, 0xf7ff4620, 0x0041fe9d, 0x4478482d, 0x21035e40, 0xf9dcf7ff, 0x210369a0, 0x43880489, - 0x692061a0, 0x1f099901, 0xd2022904, 0x04492101, 0x211f4308, 0x43880609, 0x1e499901, 0x08c906c9, - 0x0b484301, 0x03409902, 0x0cc904c9, 0x61214301, 0x21016920, 0x43880749, 0x69a06120, 0x43882110, - 0x69a061a0, 0x00800880, 0x69a061a0, 0x43087939, 0x692061a0, 0x03492101, 0x79794388, 0x0c8907c9, - 0x61214301, 0x79b979f8, 0x43080400, 0x6aa062e0, 0x43082188, 0x6aa062a0, 0x03892103, 0x62a04308, - 0x7a3969a0, 0xd0022900, 0x04c92101, 0x7a794308, 0xd0022900, 0x04892101, 0x61a04308, 0xe79f2000, - 0x00000521, 0x000035d4, 0x460cb510, 0xfe5ef7ff, 0x1e4969e1, 0xd1014288, 0xbd102001, 0xbd102000, - 0x6ac3e006, 0x0f5b015b, 0x69c3d0fb, 0x1c49700b, 0xd2f61e52, 0x00004770, 0x460cb5ff, 0x3120b083, - 0x7b499100, 0x29034617, 0x69a1d013, 0x687d2600, 0xd0322900, 0x8110f3ef, 0xb6729101, 0xf7ff4621, - 0x2800fe35, 0x4285d01b, 0x4628d200, 0x21001a2d, 0x481ae013, 0xbdf0b007, 0x69a28c63, 0x683b5cd2, - 0x8c62559a, 0x1c5269e3, 0x429a1c76, 0x2200d101, 0x8c62e001, 0x84621c52, 0x42811c49, 0x2d00d3ec, - 0x6838d007, 0x60e01980, 0x61656125, 0x21039800, 0x98017341, 0x8810f380, 0x6811e00a, 0x612560e1, - 0x9a006165, 0x73512103, 0x05492141, 0xfdadf7ff, 0x28009806, 0x6006d000, 0xe7cb2000, 0x00000515, - 0x460bb510, 0x7b1c3320, 0xd00c2c01, 0x600c6814, 0x604c6854, 0x608a6852, 0x73192101, 0xf7ff05c9, - 0x2000fd94, 0x4801bd10, 0x0000bd10, 0x00000514, 0xb084b5f7, 0xd00d000f, 0x90012000, 0x97002404, - 0x46399002, 0x98064361, 0xffe2f7fe, 0x0c2d0405, 0xe002d002, 0xff85f7fe, 0x46212501, 0x98064369, - 0xffd6f7fe, 0x1c681bc6, 0x43414621, 0x98069003, 0xffcef7fe, 0x42b01a38, 0x4606d202, 0xb2859803, - 0x42869800, 0x9600d802, 0x94019502, 0x2c201c64, 0x2164d9d7, 0xf7fe4638, 0x0041ffbb, 0x98001841, - 0xd9254281, 0x69819804, 0x22036980, 0x43900492, 0x61909a04, 0x69009804, 0x1f129a01, 0xd2022a04, - 0x04522201, 0x221f4310, 0x43900612, 0x1e529a01, 0x08d206d2, 0x0b504302, 0x03409a02, 0x0cd204d2, - 0x98044302, 0x98046102, 0x20006181, 0xbdf0b007, 0xe7fb4800, 0x00000521, 0x2900b510, 0x2a00d00b, - 0x61cbd008, 0x2200618a, 0x844a840a, 0x05492141, 0xfd1bf7ff, 0xf7febd10, 0xb510ff24, 0xd004000c, - 0x5d09212d, 0xd0022902, 0xf7fee005, 0x2141ff1a, 0xf7ff0549, 0x2000fcf9, 0x61e061a0, 0x84608420, - 0xe005bd10, 0x021b6943, 0x780bd5fc, 0x1c4961c3, 0xd2f71e52, 0x00004770, 0x0105b5f7, 0x98024c22, - 0x444c092d, 0x2001d007, 0x42850340, 0x7820d132, 0xd0072800, 0x6800e02e, 0x4288491c, 0x2001d12a, - 0xe0277020, 0x22004e1a, 0x4631444e, 0xf0014610, 0x2701fa31, 0x6060033f, 0x4631463a, 0xf0012000, - 0x2200fa29, 0x46336060, 0x46104631, 0xfa91f001, 0x60601df3, 0x113a33f9, 0x20004631, 0xfa89f001, - 0x60604b09, 0x3308444b, 0x4631463a, 0xf0012000, 0x6060fa80, 0x462a4906, 0x20004449, 0xf0019b02, - 0x6060fa78, 0x0000bdfe, 0x00000004, 0x42464346, 0x0000005c, 0x4c35b5f8, 0x49356960, 0x01804f35, - 0x69a0d51b, 0x03122203, 0xd0054010, 0x03122201, 0xd00d4290, 0xe00c2000, 0x07c068e0, 0x6938d008, - 0xd0010780, 0xe0002016, 0x49292014, 0xe0004348, 0x69614608, 0x0f490089, 0x6b38e029, 0xd00107c0, - 0xe0002516, 0x48222514, 0x48224345, 0x6a063040, 0xf0006900, 0x4632f8c5, 0xf7fe2300, 0x6939fe01, - 0x07891940, 0x0f894a1a, 0x084a4351, 0x230369a1, 0x4019049b, 0x2301d010, 0x1ac9049b, 0x1ac8d016, - 0x4298d019, 0x6920d107, 0x48130741, 0x1c490f49, 0xfebef7fe, 0x2000e000, 0x04c96961, 0x1c490f49, - 0xfeb6f7fe, 0x4449490d, 0xbdf86008, 0x6809490c, 0x0e890089, 0x480ae005, 0x6b003840, 0x0e810080, - 0xf7fe4610, 0x2112fea5, 0xe7e54348, 0x400fc000, 0x016e3600, 0x400d8000, 0x1dcd6500, 0x00000058, - 0x400d8100, 0x482db570, 0x074a8801, 0x2a002104, 0x8802da02, 0x8002438a, 0x88024829, 0xd5020752, - 0x438a8802, 0x48288002, 0x60414926, 0x60814927, 0x22806801, 0x22204391, 0x60014311, 0x69014824, - 0xd00307c9, 0x08496901, 0x61010049, 0x8f4ff3bf, 0x8f6ff3bf, 0x21004d1f, 0xf3bf6129, 0xf3bf8f4f, - 0x4c1d8f6f, 0x22016960, 0x43100452, 0xf3bf6160, 0xf3bf8f4f, 0x48188f6f, 0x60413080, 0x8f4ff3bf, - 0x01016800, 0x04c00c49, 0x05ca0d83, 0x0c964618, 0x43320782, 0x1e40622a, 0x1e49d2fa, 0xf3bfd2f5, - 0x69608f4f, 0x04092101, 0x61604308, 0x8f4ff3bf, 0x8f6ff3bf, 0xf812f000, 0x0000bd70, 0x400b8000, - 0x400d0000, 0xd928c520, 0x400bc000, 0x0000ffff, 0xe000e000, 0xe000ef40, 0xe000ed00, 0x20004770, - 0xb5704770, 0x460d4613, 0x4604460a, 0x46184601, 0xfdd1f7fe, 0xd0012800, 0xbd702000, 0xbd701960, - 0x0c04b5f8, 0x4626b28b, 0x435eb282, 0x46100c0d, 0x43580c37, 0x19800436, 0x41792100, 0x436e4616, - 0x04360c37, 0x41791980, 0x436e4626, 0xbdf81989, 0x4674b430, 0x78251e64, 0x42ab1c64, 0x461dd200, - 0x005b5d63, 0xbc3018e3, 0x00004718, 0x4959b5f8, 0x44494857, 0x49586008, 0x24016b08, 0x0f800240, - 0x6a084084, 0x07404e55, 0x6b300fc5, 0xd57d03c0, 0x21016b30, 0x43880309, 0x6b306330, 0xdafc2800, - 0x21016b30, 0x43080409, 0x4a4d6330, 0x4f4d6810, 0x40382303, 0x18c002db, 0x43184b4b, 0x20036010, - 0x61300300, 0x28006930, 0x6930dafc, 0x04092101, 0x61304388, 0x38404842, 0x22236b01, 0x02124039, - 0x4a421889, 0x63014311, 0xd0032d00, 0x2c080064, 0x2408d900, 0xd0062d00, 0x4621483d, 0xfda8f7fe, - 0x90002701, 0x483be002, 0x1c7fe7f7, 0x98004639, 0xfd9ef7fe, 0x42884938, 0x4838d8f7, 0x4a386941, - 0x40112307, 0x07521e7a, 0x43110b52, 0x029b02a2, 0x04d218d2, 0x43110cd2, 0x3aff023a, 0x05923a01, - 0x43110d92, 0x6a416141, 0x01c909c9, 0x62411cc9, 0x04892103, 0x2d006982, 0x438ad002, 0xe0046182, - 0x2101438a, 0x185104c9, 0x69816181, 0x40114a25, 0x06922203, 0x61811889, 0x4a2369c1, 0x22034011, - 0x18890752, 0x43114a21, 0xe00061c1, 0x69c1e014, 0x04122203, 0x61c14311, 0x22e76a41, 0x439102d2, - 0x02d22221, 0x62411889, 0x20016b31, 0x43810400, 0x69316331, 0x61314381, 0xd0072d00, 0x4621480c, - 0xfd46f7fe, 0x44494912, 0xbdf86008, 0xe7f64809, 0x016e3600, 0x00000050, 0x401f4440, 0x400d8000, - 0x400d8100, 0xc0c0c0c0, 0x18131818, 0x0f1a2323, 0x1f78a400, 0x179a7b00, 0x08954400, 0x400fc000, - 0xfff8e0ff, 0xe3ffffcf, 0x9c7fff80, 0x03800001, 0x00000058, 0x2800b510, 0xf7ffd101, 0xbd10ff27, - 0xb5104770, 0x02402003, 0xf7fe2100, 0xbd10fe0b, 0xb5f74770, 0x4616b082, 0xd051000d, 0xd84f2e01, - 0x34ff462c, 0x7a2034c1, 0xd0002800, 0x28002001, 0x6c28d046, 0x0fc70640, 0xf0029802, 0x2e00f94f, - 0x7a20d02b, 0xd0092800, 0x5d412046, 0x9802463a, 0xf852f000, 0x98024629, 0xfa74f000, 0x28007ba0, - 0x2100d003, 0xf0009802, 0x466afcdf, 0x98022102, 0xfc70f000, 0xd0022f00, 0x08409800, 0xaa019000, - 0x98022100, 0xfc66f000, 0x98019900, 0xfcd0f7fe, 0x1c40210a, 0x08804348, 0x7a21e010, 0xd0072900, - 0x9802463a, 0xf828f000, 0x98024629, 0xfa4af000, 0x28007ba0, 0x2101d0d9, 0xbf00e7d4, 0xd2fc1e40, - 0xbdf0b005, 0xf000b510, 0x2800fc83, 0xf002d001, 0xbd10f8ca, 0xf000b510, 0x2800fc7b, 0x2100d00b, - 0x07db2301, 0x1812008a, 0x68143280, 0x6014431c, 0x29041c49, 0xbd10d3f6, 0x460cb5f7, 0xb08a4927, - 0x22144615, 0x46684479, 0xfb7af7fe, 0x22144923, 0x31084479, 0xf7fea805, 0x2d00fb73, 0x2d01d001, - 0x4e1fd137, 0x09876b30, 0x01bf481e, 0x200769c2, 0x438205c0, 0xd02e2d00, 0x2c00a805, 0x2c09d029, - 0x2401d900, 0x5c430061, 0x78401808, 0x05c02107, 0x069b05c9, 0x0e9b1840, 0x4d130184, 0x09a4433b, - 0x43146828, 0x43382702, 0x980a6028, 0xf81ef000, 0x42986b30, 0x6333d000, 0x69c1480a, 0xd00042a1, - 0x980a61c4, 0xf81ef000, 0x43b86828, 0xf3bf6028, 0xb00d8f6f, 0x4668bdf0, 0x0000e7cf, 0x00002c1c, - 0x400d80c0, 0x400fc000, 0x402a8000, 0x68014804, 0x02922203, 0x60014391, 0x8f6ff3bf, 0x00004770, - 0x400fc080, 0x68014804, 0x02922203, 0x60014311, 0x8f6ff3bf, 0x00004770, 0x400fc080, 0x4605b5fe, - 0x90002004, 0x4628460e, 0xfbf2f000, 0xd07d0004, 0xd0fc2e00, 0x28037830, 0x7c30d878, 0x27009001, - 0xf0024620, 0x4628f875, 0xff64f7ff, 0x211e6960, 0x61604308, 0x35804625, 0x62286870, 0x28027830, - 0x2803d002, 0xe003d002, 0xe0008b30, 0xb2878c30, 0x7a307b31, 0x07001e49, 0x0b000749, 0x43080949, - 0x07c99901, 0x43384308, 0x78306268, 0xd14b2803, 0x6a3269f0, 0xd1490783, 0x211c2340, 0x63a9469e, - 0x21016bab, 0x63ab430b, 0x07db6bab, 0x6b2bd1fc, 0x632b430b, 0x1de1e036, 0x467331f9, 0xd30f4572, - 0x089b6967, 0xd40206bf, 0xc980e029, 0x1e5bc080, 0x4671d2fb, 0x69611a52, 0x43192320, 0xe01e6161, - 0x061b6f2b, 0x42930d5b, 0xe018d203, 0x1f12c908, 0x2a04c008, 0x2a00d2fa, 0x6809d010, 0xa9019101, - 0x4601468c, 0xe0072300, 0x783f4667, 0x4667700f, 0x1c491c7f, 0x1c5b46bc, 0xd3f54293, 0x69612200, - 0xd4010709, 0xd1c62a00, 0xe0007830, 0x2802e058, 0x2801d001, 0x6971d13d, 0x078869b2, 0x2040d150, - 0x201c4684, 0x6be863e8, 0x43182301, 0x6be863e8, 0xd1fc07c0, 0xe02a4686, 0x30ff4620, 0x30816963, - 0xd521065b, 0x089b4663, 0xd2024562, 0xc980e00e, 0x1e5bc080, 0x4660d2fb, 0xe0091a12, 0xdd032a00, - 0xc080c980, 0xe0011f12, 0xc0802700, 0xd2f51e5b, 0x28004670, 0x6b28d104, 0x43182301, 0x469e6328, - 0x23406960, 0x61604318, 0x07006960, 0x2a00d401, 0x7830dcd2, 0xd1032800, 0x21016b28, 0x63284308, - 0xf0014620, 0x6960ffb5, 0xd50b0700, 0x01006e68, 0x280e0f00, 0x4804d001, 0x4803e001, 0x90001e40, - 0xbdfe9800, 0xe7fa2000, 0x00001771, 0xb5104602, 0x2a002004, 0x2900d021, 0x2044d01f, 0x28015c40, - 0x68d0d10c, 0x005b0843, 0x43032040, 0xf0004608, 0x2800fcdd, 0x2001d001, 0x60d34303, 0x212068d0, - 0x60d04308, 0x20004b05, 0x18890081, 0x401c6a0c, 0x1c40620c, 0xd3f72803, 0xbd102000, 0xfcf0ff00, - 0xb087b5f3, 0x90002000, 0x2504460c, 0xf0009807, 0x9003fadf, 0xd0542800, 0xd0522c00, 0x30404620, - 0x90054627, 0x26003750, 0x304130ff, 0x68389002, 0x0a8100b2, 0x18109803, 0x66019001, 0x1d3f7ba0, - 0x7b6006c5, 0x06c00eed, 0x43050d80, 0x07007be0, 0x43050c40, 0xf0004620, 0x2800fca0, 0x2001d002, - 0x43050280, 0x28006f60, 0xaa04d00d, 0x98072102, 0xfa70f000, 0x6f612301, 0x9a044668, 0xfab2f000, - 0x04009800, 0x98014305, 0x98056705, 0x280079c0, 0x9802d00e, 0x07417c00, 0x9902d00a, 0x7c492207, - 0x07090340, 0x03520d09, 0xb2801880, 0xe0014308, 0x02002009, 0x31809901, 0x1c766008, 0xd3b62e04, - 0x46282500, 0xbdf0b009, 0xb085b5f0, 0x460e4d1b, 0x95004607, 0xf0009501, 0x0004fa7b, 0x2e00d02b, - 0xaa02d029, 0x46382102, 0xfa34f000, 0x2101aa03, 0xf0004638, 0x2601fa2f, 0x02b64f11, 0x46394633, - 0x9a024668, 0xfa6ef000, 0x46394633, 0x9a03a801, 0xfa68f000, 0x42a89800, 0x9500d900, 0x42a89801, - 0x9501d900, 0x99019800, 0xb2890400, 0x60604308, 0xb0052000, 0x2004bdf0, 0x0000e7fb, 0x0000ffff, - 0x1dcd6500, 0xb085b5f3, 0x2404460e, 0xf0009805, 0x0005fa3f, 0x2e00d07e, 0x7b30d07c, 0xd8792803, - 0xd00a2800, 0xd0082801, 0xd0062802, 0xd1042803, 0xf0004630, 0x2800fbf1, 0x20ffd002, 0xe00c3001, - 0x2102aa03, 0xf0009805, 0x4938f9e5, 0x42889803, 0x6c30d306, 0xd4030600, 0x90002079, 0xe0219001, - 0x00602400, 0x31601981, 0x7e0f7e48, 0xd10b2800, 0x43472064, 0x214bd01d, 0xf7fe4638, 0x214bfa39, - 0x42b94341, 0x1c40d200, 0x283f213f, 0x4608d900, 0x0c400680, 0x30ff00a2, 0x46693001, 0x50881c64, - 0xd3de2c02, 0x22026828, 0x28000780, 0x2000da1c, 0x4630e01e, 0xfbb7f000, 0x46024607, 0x9805a902, - 0xf9daf000, 0x9902481a, 0xd0092f00, 0xfa10f7fe, 0x217d0880, 0x434800c9, 0xf7fe214b, 0xe7d2fa09, - 0xfa06f7fe, 0xe7f40840, 0x20016829, 0x60294311, 0x29006d31, 0x6d71d102, 0xd0022900, 0x9b0021c0, - 0x6db1514b, 0xd1022900, 0x29006df1, 0x21c4d004, 0xe0009b01, 0x514be006, 0xd0022800, 0x43906828, - 0x24006028, 0xb0074620, 0x0000bdf0, 0x05f5e100, 0x3b9aca00, 0xb08ab5f7, 0x2604460d, 0xf000980a, - 0x0007f9a7, 0x2d00d054, 0x2001d052, 0x70084669, 0x9001980c, 0x74082000, 0x24002004, 0x00a09006, - 0x46101942, 0x78413020, 0xd03e2900, 0x025b2301, 0x059b59db, 0xd0030f9b, 0x7f5b192b, 0xd0342b02, - 0x78009102, 0x92053230, 0x22009003, 0x9b0c4629, 0xf000980a, 0x2800f911, 0x9802d12b, 0x01002101, - 0x32801942, 0x980a9b03, 0xfdc6f001, 0x90022001, 0x980a4669, 0xfd72f7ff, 0xd11a0006, 0x28008a68, - 0x1929d10e, 0x29027f49, 0x2903d00a, 0x2200d008, 0x9b0c4629, 0xf000980a, 0x0006f80f, 0xe004d109, - 0x43482164, 0xf0012100, 0x1c64fd8c, 0xd3b62c03, 0xb00d4630, 0x0000bdf0, 0x2004b5ff, 0x460db091, - 0x2900900e, 0x4628d079, 0x8f823040, 0x460c2101, 0x8fc24094, 0x92009302, 0x466b2203, 0x9104711a, - 0xa90c9103, 0x99139108, 0xd0012900, 0xe0002108, 0x91092104, 0x75199913, 0x280079c0, 0x4628d009, - 0x308130ff, 0x29007901, 0x7941d003, 0x79009103, 0x98039004, 0x01009b04, 0x32801942, 0x98119903, - 0xfd6af001, 0x2d006f2d, 0x2001d001, 0x2000e000, 0x900f2600, 0x9811a901, 0xfd10f7ff, 0x2800900e, - 0x9813d13b, 0xd0192800, 0xa80ba90a, 0x2208ab0c, 0x700f781f, 0x7007785f, 0x1c491c40, 0x1c9b1e92, - 0xd1f52a00, 0x990b9800, 0x980a2800, 0x4008d004, 0x43814621, 0xe00ed10a, 0xe00a4308, 0x28009800, - 0x990cd006, 0x43884620, 0xd0042800, 0xe0032701, 0x4020980c, 0x2700e7f8, 0x4207980f, 0x4628d00b, - 0xd00d4330, 0x00c0207d, 0xf0012100, 0x2000fd0a, 0x1e6d43c0, 0x2f004146, 0x980ed1bc, 0xbdf0b015, - 0x900e4801, 0x0000e7f9, 0x00001772, 0xb089b5f0, 0x460c4616, 0x25044607, 0xf8baf000, 0xd0482800, - 0xd0462c00, 0x30ff30ff, 0x68003002, 0x0f800580, 0x7c60d002, 0xd0252802, 0x46692501, 0x9601700d, - 0x90027d60, 0x90037d20, 0x74082000, 0x30184620, 0x20049005, 0x46339006, 0x46212200, 0xf0004638, - 0x9802f82b, 0x01002101, 0x46381902, 0x9b033280, 0xfce2f001, 0x46384669, 0xf7ff9502, 0x0005fc8f, - 0xe001d117, 0xe0142500, 0x29008a61, 0x7c60d10c, 0xd0092802, 0xd0072803, 0x22004633, 0x46384621, - 0xff2af7ff, 0xe0044605, 0x43482064, 0xf0012100, 0x4628fca8, 0xbdf0b009, 0x4604b570, 0xb08a2004, - 0xd0242900, 0x466e2000, 0x20037030, 0x90022501, 0x74329503, 0x93012047, 0x28005c40, 0x4608d009, - 0x308130ff, 0x2a007a02, 0x7a42d003, 0x7a009202, 0x98029003, 0x01009b03, 0x21011842, 0x32804620, - 0xfc9af001, 0x46204669, 0xf7ff9502, 0xb00afc47, 0x0000bd70, 0x4616b570, 0x20004a13, 0x6812444a, - 0x29004604, 0x4d11d008, 0xd0072901, 0xd00a2902, 0x60302404, 0xbd704620, 0xe7fa4610, 0x05806968, - 0x46100f81, 0x69e8e00c, 0x6b004809, 0x0e890681, 0xf7fe4808, 0x2112f84d, 0x69e94348, 0x0f490189, - 0xf7fe1c49, 0xe7e4f845, 0x00000058, 0x400fc000, 0x400d80c0, 0x1c9c3800, 0x20044602, 0xd1042a00, - 0xd0022900, 0x60084801, 0x47702000, 0x07ed6b40, 0x20004601, 0xd1022900, 0x44784801, 0x47706800, - 0x0000236e, 0x4607b5f8, 0x461c2004, 0x2f00460e, 0x2a00d016, 0x2c00d014, 0x4611d012, 0xf7fe4809, - 0x4601f817, 0x43614605, 0xf7fe4630, 0xe000f811, 0x46011c40, 0x43614369, 0xd3f942b1, 0x20006038, - 0x0000bdf8, 0x3b9aca00, 0x460db570, 0xffd0f7ff, 0xd00a0004, 0xfc5cf001, 0x02c02001, 0x2d006821, - 0x4301d001, 0x4381e000, 0xbd706021, 0xb087b5f3, 0x2604460d, 0xf7ff9807, 0x0004ffbb, 0x2d00d07e, - 0x7c28d0fc, 0xd1022800, 0x28007f28, 0x6c28d009, 0xd40406c0, 0xf0004628, 0x2800f976, 0x2001d001, - 0x2000e000, 0x49619003, 0x42886828, 0x9807d166, 0xfb8cf7ff, 0x98074629, 0xf8bef000, 0x30404628, - 0x90029903, 0xd0022900, 0x21012200, 0x4628e005, 0xf959f000, 0x98024602, 0x98077981, 0xfb1cf7ff, - 0xf7ff9807, 0x6820fb7f, 0x43b02602, 0x46206020, 0xfbc9f001, 0x43306820, 0x68206020, 0x4008494c, - 0x79499902, 0xd1012908, 0x43080289, 0x43084949, 0x07897b29, 0x43010e89, 0x46296021, 0xf7ff9807, - 0x68a0fce3, 0x03c92101, 0x60a04388, 0xf0004628, 0x2800f931, 0x68a0d004, 0x04c92101, 0x60a04308, - 0x46204629, 0xfc42f7ff, 0x98074629, 0xfc68f7ff, 0x98074629, 0xfd06f7ff, 0x21026820, 0x60204388, - 0xf0014620, 0x4628fb90, 0x30507c29, 0x29009004, 0x9807d01c, 0x20049005, 0xe0002100, 0x9e04e052, - 0x460f9100, 0x9101ce02, 0xd00a2900, 0x9a004629, 0xf7ff9805, 0x2800fe6b, 0x9a01d106, 0x18899900, - 0x1c7f9100, 0xd3ed2f04, 0xd13b0006, 0x28007f28, 0x9807d01c, 0x20049005, 0xd0152d00, 0x9e042100, - 0x460f9100, 0x9101ce02, 0xd00a2900, 0x9a004629, 0xf7ff9805, 0x2800fd5f, 0x9a01d106, 0x18899900, - 0x1c7f9100, 0xd3ed2f04, 0xd11b0006, 0x28009803, 0x6820d017, 0x43302602, 0x46286020, 0xf8c3f000, - 0x98024602, 0x98077981, 0xfa86f7ff, 0x98074629, 0xfc6af7ff, 0x98074629, 0xfca4f7ff, 0x43b06820, - 0x26006020, 0xb0094630, 0x0000bdf0, 0x42464346, 0x0000df0f, 0xffff0000, 0x4d4bb5f8, 0x462e484b, - 0x460c9000, 0x46084637, 0xf8a9f000, 0xd0042800, 0x6ee06e26, 0x6e679000, 0x6d206ea5, 0x6d602800, - 0x2800d025, 0x4942d004, 0x63c82006, 0x63064841, 0x6d204b3f, 0x28003380, 0x2001d004, 0x483d6058, - 0x63863040, 0x20114a3a, 0x63503240, 0x30404839, 0x21016287, 0x62c56391, 0x63456019, 0x630563d1, - 0x62456311, 0x5d002045, 0xd0032808, 0x2800e00f, 0xe025d1d9, 0x2001492e, 0x62083140, 0x32404a2d, - 0x62886155, 0x624861d5, 0x61886195, 0x7b2060d5, 0xd0012803, 0xd1072801, 0x21114825, 0x62c13040, - 0x98004924, 0x62083140, 0xf0004620, 0x2800f853, 0x481fd006, 0x30402101, 0x481e61c1, 0x61073040, - 0x28006da0, 0xd02b6de0, 0xd0052800, 0x20064918, 0x60083140, 0x63464817, 0x28006da0, 0x4814d006, - 0x30402104, 0x481360c1, 0x60063040, 0x21114810, 0x61c13040, 0x3140490f, 0x2201610f, 0x614d6202, - 0x61cd6282, 0x618d6242, 0x60cd6182, 0x2a037b22, 0x2a01d001, 0x2214d103, 0x98006102, 0xbdf86048, - 0xd1d32800, 0x0000bdf8, 0x000010f1, 0x000130f1, 0x401f8100, 0x401f8280, 0x07806c00, 0x2001d501, - 0x20004770, 0x6c004770, 0xd5010640, 0x47702001, 0x47702000, 0x07c06c00, 0x2001d000, 0x6c004770, - 0xd5010680, 0x47702001, 0x47702000, 0x07406c00, 0x2001d501, 0x20004770, 0x6c004770, 0xd5010700, - 0x47702001, 0x47702000, 0xb08ab570, 0x20004605, 0x7030466e, 0x2401200f, 0x94039002, 0x460a7432, - 0x930132ff, 0x46233271, 0x46284621, 0xfa54f001, 0x46284669, 0xf7ff9402, 0xb00afa01, 0xb5ffbd70, - 0xb0812004, 0x2900460f, 0x463dd01e, 0x358135ff, 0x42496c69, 0x4014460c, 0x425218d2, 0x21ff400a, - 0x5dc931ca, 0x29004256, 0x6d29d10c, 0xd0092900, 0x4622e02a, 0x98014639, 0xf8fcf000, 0xd1032800, - 0x190c6c69, 0xd3f442b4, 0xbdf0b005, 0x46206d29, 0xd00e4388, 0x1b322000, 0xd00c2800, 0xd80a4291, - 0x46394622, 0xf0009801, 0x2800f88b, 0x6d29d1ec, 0x2001e009, 0x4622e7ef, 0x98014639, 0xf8daf000, - 0xd1e12800, 0x190c6c69, 0xd3df42b4, 0xb5f3e7dc, 0x2600b08b, 0x9d0c4669, 0x2101700e, 0x210b9103, + 0xd0050fc0, 0xb0054620, 0xf000bdf0, 0xe7f4fa98, 0x4be849e9, 0x33c01a68, 0x428d466a, 0xdc31d056, + 0x182848e6, 0x2101d046, 0x4fe50549, 0xd02f1a40, 0x42880049, 0x6b38d12a, 0x064649e1, 0x31400e76, + 0x4620690d, 0xf0036809, 0x462afb2f, 0xf0032300, 0x4374f959, 0x18206b39, 0x04d22203, 0xd0314011, + 0x04d22201, 0xd1004291, 0x49d60840, 0x4ad66b09, 0x22014011, 0x1a8903d2, 0x0212d026, 0xd1c24291, + 0xe7c00880, 0xd0232807, 0xd0272808, 0xe7ba2000, 0x46206a3d, 0xf0036939, 0x462afb07, 0xf0032300, + 0x6b31f931, 0xd00107c9, 0xe0002116, 0x434c2114, 0xe7a81820, 0x07806930, 0x2016d001, 0x2014e000, + 0xe7a04360, 0xe7d00880, 0xe79c0840, 0xe0016a18, 0x08806a18, 0x0f000780, 0xe7945810, 0xe79248bb, + 0x4604b510, 0xf7ff48ba, 0x49b6ff71, 0x2c003940, 0x2c01d009, 0x2c02d009, 0x2c03d00e, 0x2000d00f, + 0x43482112, 0x6809bd10, 0x6809e001, 0x06890a09, 0xf0030e89, 0xe7f3f9cf, 0x0c096809, 0x6809e7f7, + 0xe7f40e09, 0x4604b510, 0x424048a4, 0xff4ef7ff, 0x318049a3, 0xd0092c00, 0xd0092c01, 0xd00e2c02, + 0xd00f2c03, 0x21122000, 0xbd104348, 0xe0016b09, 0x0a096b09, 0x0e890689, 0xf9acf003, 0x6b09e7f3, + 0xe7f70c09, 0x0e096b09, 0xb510e7f4, 0x69604c99, 0x48970181, 0xd51869a1, 0x40111202, 0x2201d00d, + 0x1a890312, 0x4291d00e, 0x2000d009, 0x00896961, 0x1c490f49, 0xf98ef003, 0x4888bd10, 0xf7ff4240, + 0xe7f3ff15, 0xf9cbf000, 0x2203e7f0, 0x40110492, 0x2201d00b, 0x1a880492, 0x1a80d00a, 0x4290d00c, + 0x4885d101, 0x2000bd10, 0xf7ffbd10, 0xbd10feff, 0xf7ff2003, 0xbd10ffa7, 0xf7ff2003, 0xbd10ff81, + 0x2800b510, 0xf003d001, 0x2101f90e, 0x07894875, 0x497a6181, 0x03d26b0a, 0x2201d5fc, 0x61420412, + 0x04096901, 0x6182d5fc, 0x2001bd10, 0x0780496d, 0x47706148, 0x49712210, 0xd0012800, 0x4770638a, + 0x4770634a, 0x6b01486d, 0x43112201, 0x47706301, 0x6b01486a, 0x00490849, 0x47706301, 0x4c65b510, + 0xf0030003, 0x0d17fa49, 0x362a120d, 0x3f3c6439, 0x64454341, 0x4f4d4b49, 0x5a575551, 0x0064605d, + 0xff83f7ff, 0x0a896961, 0x6960e011, 0xd50a0640, 0x06006960, 0x2001d503, 0xff54f7ff, 0x2002e005, + 0xff2ef7ff, 0xf7ffe001, 0x6961ff70, 0x07490c09, 0x1c490f49, 0xf90ef003, 0xf7ffbd10, 0x6961ff66, + 0x0f4904c9, 0xf0031c49, 0x6961f905, 0x0f890589, 0xf000e7ef, 0xbd10f944, 0x03c02001, 0x483fbd10, + 0xe0214240, 0xe0042000, 0xe0022001, 0xe0002002, 0xf7ff2003, 0xbd10ff27, 0xe015483d, 0xe0042000, + 0xe0022001, 0xe0002002, 0xf7ff2003, 0xbd10fef9, 0xe0094831, 0x1dc04830, 0x482fe006, 0xe0033008, + 0x3009482d, 0x4836e000, 0xfe60f7ff, 0x2000bd10, 0x7800bd10, 0x07c02101, 0x03490fc0, 0x48251841, + 0x6b016301, 0xdafc2900, 0x20014770, 0x03004921, 0x47706308, 0x21c17800, 0x0f800780, 0x18410189, + 0x6101481c, 0x29006901, 0x4770dafc, 0x20004919, 0x47706108, 0x6841b530, 0x008b2200, 0x089b4918, + 0x600b3140, 0x009b6883, 0x610b089b, 0x23017801, 0x035b0649, 0x78400e49, 0x019d18c9, 0xd0352802, + 0x006c4b11, 0xd02f2804, 0xd02b2808, 0xd00d2810, 0x4b0c4321, 0x4c0c6b18, 0x402043e4, 0x63184310, + 0x63014807, 0x29006b01, 0xbd30dafc, 0xe7f0461a, 0x0000371c, 0x400d8000, 0x00e0000d, 0xffeffff3, + 0x400d8040, 0x400d8140, 0x00808000, 0x017d7840, 0x0030000d, 0x400fc000, 0x1dcd6500, 0x400d8240, + 0x0070000d, 0xe7e14329, 0xe7df4321, 0xe7d04329, 0x49582001, 0x63080300, 0x79414770, 0x07897902, + 0x0f090792, 0x43110f92, 0x2a007802, 0x2201d002, 0x43110352, 0x2a007842, 0x2201d002, 0x43110512, + 0x2a007882, 0x2201d002, 0x43110552, 0x280078c0, 0x2001d002, 0x43010580, 0x30804846, 0x6a016201, + 0xdafc2900, 0x20014770, 0x03004942, 0x62083180, 0x4b404770, 0x33c0b510, 0x00c0681a, 0x408424bf, + 0x248043a2, 0x43144084, 0x0689601c, 0x40810e89, 0x60194311, 0x4937bd10, 0x680a31c0, 0x208000c3, + 0x43024098, 0x4770600a, 0xb5104b32, 0x6b1a3380, 0x24bf00c0, 0x43a24084, 0x40842480, 0x631c4314, + 0x0e890689, 0x43114081, 0xbd106319, 0x31804929, 0x00c36b0a, 0x40982080, 0x630a4302, 0xb5084770, + 0x68014825, 0x43112203, 0x48246001, 0x22026801, 0x60014311, 0x90002000, 0xbf004821, 0x1c499900, + 0x42819100, 0x491bd3f9, 0x6a0831c0, 0x0212221f, 0x4a1c4390, 0x62084310, 0xbd082001, 0x2200b508, + 0x92004668, 0xff16f7ff, 0x6b014817, 0x08490049, 0x6b016301, 0x43990483, 0x60026301, 0x22636b01, + 0x43110392, 0x20016301, 0x490abd08, 0x39402000, 0x480d6108, 0x04826b01, 0x63014311, 0x480b4770, + 0x06c06b00, 0x480ad501, 0x480a4770, 0x68004448, 0x00004770, 0x400d8040, 0x400fc080, 0x402e0140, + 0x00061a80, 0x00001701, 0x400d9000, 0x400d8240, 0x016e3600, 0x00000004, 0x49a0b5f8, 0x4449489e, + 0x60084e9f, 0x21016b30, 0x43880309, 0x6b306330, 0xdafc2800, 0x6802489b, 0x2303499b, 0x02db400a, + 0x4b9a18d2, 0x6002431a, 0x03002003, 0x69306130, 0xdafc2800, 0x27016930, 0x43b8043f, 0x4a916130, + 0x6b103a40, 0x21234008, 0x18400209, 0x43084990, 0x4c906310, 0x61202001, 0x488f4990, 0x60084449, + 0x90002501, 0x1c6de000, 0x98004629, 0xff62f002, 0x4288498b, 0x6960d8f7, 0x4008498a, 0x07491e69, + 0x43080b49, 0x39ff0229, 0x05893901, 0x43080d89, 0x6a606160, 0x01c009c0, 0x62601cc0, 0x210369a0, + 0x43080489, 0x69a061a0, 0x4008497f, 0x06892105, 0x61a01840, 0x497d69e0, 0x21034008, 0x18400749, + 0x4308497b, 0x69e061e0, 0x04092103, 0x61e04308, 0x21e76a60, 0x438802c9, 0x02c92121, 0x62601840, + 0x43b86b30, 0x69306330, 0x613043b8, 0x4869bdf8, 0x68013080, 0x02922203, 0x60014311, 0x48654770, + 0x68013080, 0x02922203, 0x60014391, 0xb5f74770, 0x4968460c, 0x4615b08a, 0x44792214, 0xf7ff4668, + 0x4964fbef, 0x44792214, 0xa8053108, 0xfbe8f7ff, 0xd0012d00, 0xd1362d01, 0x3e404e52, 0x09876b30, + 0x01bf4854, 0x200769c2, 0x438205c0, 0xd02c2d00, 0x2c00a805, 0x2c09d027, 0x2401d900, 0x5c430061, + 0x78401808, 0x05c02107, 0x069b05c9, 0x0e9b1840, 0x4d510184, 0x09a4433b, 0x43146828, 0x43382702, + 0x980a6028, 0xffbbf7ff, 0x42986b30, 0x6333d000, 0x69c14840, 0xd00042a1, 0x980a61c4, 0xffa7f7ff, + 0x43b86828, 0xb00d6028, 0x4668bdf0, 0xb570e7d1, 0x4a3a4616, 0x444a2000, 0x46046812, 0xd0082900, + 0x29014d34, 0x2902d007, 0x2404d00a, 0x46206030, 0x4610bd70, 0x6968e7fa, 0x0f810580, 0xe00d4610, + 0x482869e8, 0x6b003840, 0x0e890681, 0xf0024833, 0x2112fea1, 0x69e94348, 0x0f490189, 0xf0021c49, + 0xe7e3fe99, 0x20044603, 0xd1042b00, 0xd0022900, 0x6008482b, 0x47702000, 0x44484820, 0x47706800, + 0x481cb510, 0x05806940, 0x481c0f81, 0x44481c49, 0xf0026800, 0xbd10fe7f, 0x4604b5f8, 0x460d4817, + 0x68004448, 0xf002491f, 0x4606fe75, 0x2103e009, 0xf0024630, 0x9000fe6f, 0xbf00e000, 0x90001e40, + 0x2200d2fb, 0x46281e64, 0x415043d2, 0x43e14605, 0x430143e8, 0xbdf8d1eb, 0x016e3600, 0x00000004, + 0x400d8000, 0x400d8100, 0xc0c0c0c0, 0x18131818, 0x0f1a2323, 0x400fc000, 0x1f78a400, 0x0000000c, + 0x08954400, 0xfff8e0ff, 0xe3ffffcf, 0x9c7fff80, 0x03800001, 0x00003066, 0x402a8000, 0x1c9c3800, + 0x09e4f580, 0x000f4240, 0x4d5ab5f8, 0x462e485a, 0x460c9000, 0x46084637, 0xff0ff001, 0xd0042800, + 0x6ee06e26, 0x6e679000, 0x6d206ea5, 0x6d602800, 0x2800d027, 0x4951d004, 0x63c82006, 0x63064850, + 0x28006d20, 0x494dd006, 0x31402001, 0x484c6308, 0x62463040, 0x23114a49, 0x63533240, 0x30404848, + 0x21016287, 0x62c56391, 0x630563d1, 0x32804a43, 0x63456011, 0x63856051, 0x5d002045, 0xd0032808, + 0x2800e00f, 0xe024d1d7, 0x2001493c, 0x62483140, 0x32404a3b, 0x62086195, 0x61c86155, 0x61886115, + 0x7b2060d5, 0xd0012803, 0xd1062801, 0x31404933, 0x493362cb, 0x31409800, 0x46206208, 0xfec4f001, + 0xd0062800, 0x2001492d, 0x62883140, 0x3040482c, 0x6da061c7, 0x6de02800, 0x2800d02b, 0x4927d005, + 0x31402006, 0x48266008, 0x6da06346, 0xd0062800, 0x21044822, 0x62813040, 0x30404821, 0x481f6006, + 0x30402111, 0x491e6281, 0x61cf3140, 0x62422201, 0x6202618d, 0x61c2614d, 0x6182610d, 0x7b2260cd, + 0xd0012a03, 0xd1032a01, 0x61022214, 0x60489800, 0x2800bdf8, 0xbdf8d1d3, 0x28002104, 0x7b01d00f, + 0xd10b2903, 0x30606c01, 0x29000649, 0x210fda01, 0x7e41e003, 0xd1012900, 0x7601211e, 0x46082100, + 0x49084770, 0x20006288, 0x49064770, 0x60016a89, 0x47702000, 0x000010f1, 0x000130f1, 0x401f8100, + 0x401f8280, 0x400f8000, 0x460cb570, 0xf0024606, 0x0005fa35, 0x4622d10b, 0x32802301, 0x46302100, + 0xf8e6f002, 0x28017c60, 0x2000d101, 0x46287420, 0xb570bd70, 0x4605b08a, 0x466e2000, 0x200f7030, + 0x90022401, 0x74329403, 0x32ff460a, 0x32719301, 0x46214623, 0xf0024628, 0x4669f8cb, 0x94024628, + 0xffd5f001, 0xbd70b00a, 0x2004b5ff, 0x460db083, 0xd0292900, 0x36ff462e, 0x7b7036c1, 0xd0062800, + 0x9a059b06, 0xf7ff9803, 0x2800ffd4, 0x7b30d11c, 0x3480462c, 0xd10a2802, 0x30304620, 0x466bc887, + 0x4620c307, 0xc80f3040, 0xc40f3430, 0x46293c40, 0x9a059b06, 0xf0029803, 0x7b31f8cb, 0xd1032902, + 0xcd0e466d, 0xc48e3430, 0xbdf0b007, 0xb089b5ff, 0x4616461d, 0x9809460c, 0xffc6f7ff, 0xd1142800, + 0x70084669, 0x200e2701, 0x90029703, 0x4622740e, 0x326132ff, 0x4639463b, 0x98099501, 0xf878f002, + 0x97024669, 0xf0019809, 0xb00dff82, 0xb5ffbdf0, 0xb0832004, 0x4696469c, 0xd0d52900, 0x35ff460d, + 0x7b2835c1, 0x3480460c, 0xd10b2802, 0x30104620, 0x466ac889, 0xc28969e6, 0x30204620, 0x3410c88d, + 0x3c20c48d, 0x46724663, 0xf0029803, 0x7b29f8ae, 0xd1b92902, 0xcd0e466d, 0xc44e3410, 0xb5f7e7b4, + 0x4616b082, 0xd051000d, 0xd84f2e01, 0x34ff462c, 0x7a2034c1, 0xd0002800, 0x28002001, 0x6c28d046, + 0x0fc70640, 0xf0029802, 0x2e00fa62, 0x7a20d02b, 0xd0092800, 0x5d412046, 0x9802463a, 0xfd97f7ff, + 0x98024629, 0xfdaaf001, 0x28007ba0, 0x2100d003, 0xf0029802, 0x466afa5e, 0x98022102, 0xfdd7f7ff, + 0xd0022f00, 0x08409800, 0xaa019000, 0x98022100, 0xfdcdf7ff, 0x98019900, 0xfc8cf002, 0x1c40210a, + 0x08804348, 0x7a21e010, 0xd0072900, 0x9802463a, 0xfd6df7ff, 0x98024629, 0xfd80f001, 0x28007ba0, + 0x2101d0d9, 0xbf00e7d4, 0xd2fc1e40, 0xbdf0b005, 0xb089b5ff, 0x460d4617, 0xf0014608, 0x4606fd47, + 0x46292200, 0xf7ff9809, 0x463bff9a, 0x46294632, 0xf7ff9809, 0x0004ff19, 0x2002d13f, 0x70084669, + 0x24012009, 0x94039002, 0x5d412047, 0x30ff4628, 0x29003081, 0x7c01d006, 0xd0032900, 0x91027c41, + 0x91037c01, 0x97014669, 0x990c740e, 0x6c009105, 0x98029006, 0x01002101, 0x32801942, 0x98099b03, + 0xffb6f001, 0x94024669, 0xf0019809, 0x0004fec0, 0x463bd113, 0x46294632, 0xf7ff9809, 0x0004ff38, + 0x20ffd10b, 0x5d4030d0, 0xd0062800, 0x4632463b, 0x98094629, 0xff0af7ff, 0x98094604, 0xf9d1f002, + 0x46292201, 0xf7ff9809, 0x4620ff4a, 0xb5f3e71d, 0x2600b08b, 0x9d0c4669, 0x2101700e, 0x210b9103, 0x46699102, 0x2047740e, 0x46375d40, 0x28004634, 0x4628d009, 0x308130ff, 0x29007d01, 0x7d41d003, - 0x7d009102, 0x22009003, 0x980b990c, 0xf8b1f7ff, 0x950a3550, 0x9009cd01, 0xd01a2800, 0x22004633, - 0x980b990c, 0xf96ff001, 0xd13e0004, 0x96019802, 0x980c0101, 0x180a9b03, 0x32802101, 0xf001980b, - 0x2001f9cb, 0x46699002, 0xf7ff980b, 0x0004f977, 0x9809d12b, 0x18361c7f, 0xd3db2f04, 0xd1242c00, - 0x90092000, 0x980c4606, 0x30ff9d0a, 0x900a30c1, 0x2f00cd80, 0x2200d013, 0x990c9b09, 0xf001980b, - 0x0004f919, 0x980ad111, 0x28007bc0, 0x2200d007, 0x990c9b09, 0xf001980b, 0x0004f84d, 0x9809d105, - 0x19c01c76, 0x2e049009, 0x980bd3e2, 0xf8baf7ff, 0x990c2201, 0xf7ff980b, 0x4620f85c, 0xbdf0b00d, - 0xb08ab5f7, 0x460d4617, 0xf7ff4608, 0x4606ff0f, 0x46292200, 0xf7ff980a, 0x463bf84c, 0x46294632, - 0xf001980a, 0x0004f910, 0x4669d139, 0x70089701, 0x24012008, 0x94039002, 0x2047740e, 0x28005d40, - 0x4628d009, 0x308130ff, 0x29007f01, 0x7f41d003, 0x7f009102, 0x98029003, 0x01002101, 0x32801942, - 0x980a9b03, 0xf958f001, 0x94024669, 0xf7ff980a, 0x0004f905, 0x463bd113, 0x46294632, 0xf001980a, - 0x0004f8b9, 0x20ffd10b, 0x5d4030d0, 0xd0062800, 0x4632463b, 0x980a4629, 0xffecf000, 0x980a4604, - 0xf860f7ff, 0x46292201, 0xf7ff980a, 0x4620f802, 0xbdf0b00d, 0xb08ab5f7, 0x460d4617, 0xf7ff4608, - 0x4606feb5, 0x46292200, 0xf7fe980a, 0x463bfff2, 0x46294632, 0xf001980a, 0x0004f8b6, 0x4669d139, - 0x70089701, 0x24012005, 0x94039002, 0x2047740e, 0x28005d40, 0x4628d009, 0x308130ff, 0x29007b01, - 0x7b41d003, 0x7b009102, 0x98029003, 0x01002101, 0x32801942, 0x980a9b03, 0xf8fef001, 0x94024669, - 0xf7ff980a, 0x0004f8ab, 0x463bd113, 0x46294632, 0xf001980a, 0x0004f85f, 0x20ffd10b, 0x5d4030d0, - 0xd0062800, 0x4632463b, 0x980a4629, 0xff92f000, 0x980a4604, 0xf806f7ff, 0x46292201, 0xf7fe980a, - 0x4620ffa8, 0xbdf0b00d, 0x460cb570, 0xf7ff4606, 0x0005fcbd, 0x4622d10b, 0x32802301, 0x46302100, - 0xf8caf001, 0x28017c60, 0x2000d101, 0x46287420, 0xb5ffbd70, 0x4617b089, 0x4608460d, 0xfe46f7ff, - 0x22004606, 0x98094629, 0xff83f7fe, 0x4632463b, 0x98094629, 0xf847f001, 0xd13f0004, 0x46692002, - 0x20097008, 0x90022401, 0x20479403, 0x46285d41, 0x308130ff, 0xd0062900, 0x29007c01, 0x7c41d003, - 0x7c019102, 0x46699103, 0x740e9701, 0x9105990c, 0x90066c00, 0x21019802, 0x19420100, 0x9b033280, - 0xf0019809, 0x4669f889, 0x98099402, 0xf836f7ff, 0xd1130004, 0x4632463b, 0x98094629, 0xffeaf000, - 0xd10b0004, 0x30d020ff, 0x28005d40, 0x463bd006, 0x46294632, 0xf0009809, 0x4604ff1d, 0xf7fe9809, - 0x2201ff91, 0x98094629, 0xff33f7fe, 0xb00d4620, 0x0000bdf0, 0xb089b5ff, 0x9c122004, 0x4616461f, - 0xd0222900, 0xd0202e00, 0xd01e2c00, 0xf7ff4608, 0x2103fddd, 0x7011466a, 0x91032101, 0x91022100, - 0x4d0b7410, 0xd80042ac, 0x46694625, 0x96079701, 0x98099508, 0xfff2f7fe, 0xd1062800, 0x008908a9, - 0x197f1b64, 0x2c00198e, 0xb00dd1eb, 0x0000bdf0, 0x0000ffff, 0xb0b4b5f7, 0x900048ab, 0x46156810, - 0x0f000200, 0x2809460c, 0x2600d01b, 0x225049a7, 0xa81e4479, 0xfae4f7fd, 0x90022000, 0x30404620, - 0x90012104, 0x68287141, 0x04000301, 0x20100f05, 0x64200f0f, 0xd0062f00, 0xd01b2f02, 0xd01c2f03, - 0x2601e129, 0xa804e7e2, 0xfe14f000, 0x20009000, 0xffccf000, 0x28009800, 0xaa04d107, 0x98344621, - 0xfecaf000, 0x28009000, 0x9901d1ea, 0x71482001, 0xe0002000, 0x73202003, 0x2003e008, 0x20087320, - 0x2e009901, 0xd1017148, 0x90022001, 0xd0032d00, 0xd0012d02, 0xd1d32d03, 0x43284638, 0x2601d100, - 0xd0022d02, 0xd0022d03, 0x2004e004, 0x2008e000, 0x71489901, 0x6c202140, 0xd0012e00, 0xe0004388, - 0x64204308, 0x98344621, 0xfeeef7ff, 0x28009000, 0x2e00d1b6, 0x2f02d008, 0x2f03d002, 0xe001d10c, - 0xe0092001, 0xe0072002, 0xd0022f02, 0xd1032f03, 0x2003e001, 0x2004e000, 0xa91e0100, 0x23011842, - 0x98344619, 0xffa8f000, 0x9a02a905, 0xf0009834, 0x9000fdd5, 0xd17d2800, 0xaa32ab33, 0x4620a905, - 0xfffef000, 0x73202003, 0x30804620, 0x63014960, 0x61014960, 0xd0012e00, 0xe0002302, 0x2e002322, - 0x210cd001, 0x212ce000, 0x2e00468e, 0x2109d001, 0x2129e000, 0x2e009102, 0x2208d001, 0x2228e000, - 0x0d8f07a9, 0x46399204, 0x07aa9701, 0x370b0992, 0x4317069b, 0x431f469c, 0x431f4b4f, 0x46736007, - 0x029b1d0f, 0x9b02431f, 0x069b4317, 0x9302431f, 0x049b2301, 0x6047431f, 0x3720460f, 0x46634317, - 0x4b45431f, 0x431f4696, 0x460f6507, 0x431737d8, 0x431f4663, 0x431f4b40, 0x33f91de3, 0x1c8f601f, - 0x46624317, 0x4a3c4317, 0x611f4317, 0x9a04460f, 0x02923780, 0x22014317, 0x31600292, 0x4311615f, - 0x63192702, 0xd0012d02, 0xd10f2d03, 0x46739901, 0x43191d49, 0x43199b02, 0x43194b30, 0x99016201, - 0x43111d89, 0x32cd22ff, 0x55176401, 0x61a12100, 0xe0002d02, 0xd002e03f, 0xd0032d03, 0x2201e005, - 0xe0010492, 0x04d22201, 0x2e0061a2, 0x6c22d010, 0x431a2380, 0x64222301, 0x55132279, 0x66024a20, - 0x66424a20, 0x74202001, 0xd0072d00, 0xe0067467, 0x69a22301, 0x431a05db, 0xe7ef61a2, 0x22067461, - 0x75207562, 0x46688260, 0x2e007301, 0x2d02d008, 0x2d03d002, 0xe007d002, 0xe0122041, 0xe0102081, - 0xd00b2d02, 0xd00b2d03, 0x20087341, 0x73c84669, 0xf0009803, 0x9800feab, 0xbdf0b037, 0xe0002042, - 0x46692082, 0xe7f07348, 0x00004e8d, 0x00001bac, 0x00000406, 0x24040405, 0x00200400, 0x00040400, - 0x04000471, 0x00002003, 0x460db5f7, 0x2103b088, 0x73e94628, 0x30402308, 0x23587143, 0x2401642b, - 0x2a007329, 0x2159d001, 0x71c46429, 0x8781210f, 0x462e87c4, 0x36ff2001, 0x36810240, 0x02406430, - 0x65306470, 0x30404630, 0x72449007, 0x98084629, 0xfdcaf7ff, 0xd1392800, 0x2700485d, 0x485d9000, - 0x23019703, 0x97029001, 0x4619466a, 0xf0009808, 0x9702fe93, 0x4f569703, 0x37804857, 0x23019001, - 0x2100466a, 0x98089700, 0xfe86f000, 0x02c02013, 0x23029006, 0x4951aa06, 0xf0009808, 0x2800fc77, - 0x2308d114, 0x2110aa04, 0xf0009808, 0x2800fc5b, 0x9805d10c, 0xb280494a, 0x98049005, 0xd1044288, - 0x98052159, 0x42880209, 0x4846d002, 0xbdf0b00b, 0xaa042308, 0x98082127, 0xfc44f000, 0xd1f52800, - 0x04009804, 0x90040e00, 0x28093817, 0x9904d8ed, 0x40882001, 0x200f6528, 0x90060300, 0xaa062302, - 0x98082100, 0xfc42f000, 0xd1df2800, 0x4930462c, 0x31803480, 0x49346021, 0x49346061, 0x493460a1, - 0x4b354a34, 0x34104f35, 0x4f29c48e, 0x378035ff, 0x4f336027, 0x4f2d6067, 0x341060a7, 0x4f31c40e, - 0x602260a7, 0x4f306061, 0x4f2e60e7, 0x4f2f6127, 0xc58e3511, 0x34144f1e, 0x602f3f20, 0x606f4f2c, - 0xc48e4f2c, 0x4f27c40e, 0x602260a7, 0x4f266061, 0x4f2460e7, 0x4c166127, 0x3c203d20, 0x4c26602c, - 0x4c26606c, 0x462f60ac, 0x37304c22, 0xc70ec71e, 0x656c4c1c, 0x652964ea, 0x65ac4c1b, 0x37144c19, - 0xc70e65ec, 0x66e9491e, 0x72312102, 0x72722203, 0x22017131, 0x74317172, 0x74712109, 0x73312104, - 0x73732305, 0x210b7531, 0x99077571, 0xe77d730a, 0x8b188720, 0xa3028f10, 0xa7048f10, 0x00000555, - 0x52005100, 0x00004e8d, 0xb3068f10, 0x0000a704, 0x87008700, 0x87aa8700, 0x87058700, 0x87708700, - 0xb70b8f10, 0x87558700, 0x87028700, 0x87a08700, 0xa3808f10, 0x87808700, 0x87008f10, 0x00008730, - 0x87108700, 0x460cb5f7, 0xb0a64979, 0x22204617, 0xa81d4479, 0xf874f7fd, 0x02016838, 0x29070f09, - 0x2100d008, 0x91000300, 0xd0050f00, 0x73202003, 0xe0142050, 0xe7f52101, 0xf000a801, 0x4605fbab, - 0xf0002000, 0x2d00fd63, 0xaa01d106, 0x98264621, 0xfc62f000, 0xd1140006, 0x73202000, 0x46252010, - 0x35402108, 0x71696420, 0x98264621, 0xfcacf7ff, 0xd1f00006, 0x03006838, 0xd0030f01, 0x28030f00, - 0xe0b1d003, 0xaa1d2301, 0x2301e001, 0x2101aa21, 0xf0009826, 0x2008fd71, 0x22007168, 0x9826a904, - 0xfb9cf000, 0xd12b0006, 0xaa02ab03, 0x4620a904, 0xfdc6f000, 0x98004625, 0x35802206, 0xd0202800, - 0x6628484c, 0x6668484c, 0x66a8484c, 0x61a0200c, 0x74202001, 0x75207562, 0x63284849, 0x61284849, - 0x03086839, 0x46200f03, 0x30c130ff, 0x38c09001, 0xd00b2b03, 0x0f0b0409, 0xd0072b03, 0xd0200f09, - 0x2050e072, 0x20036420, 0xe7e57320, 0x6229493e, 0x6029493e, 0x6069493e, 0x6429493e, 0x39dc493b, - 0x493a6529, 0x60013921, 0x0149213b, 0x49376301, 0x610139eb, 0x61414938, 0x03006838, 0xd0360f00, - 0x2101e04f, 0x06096d27, 0xd302428f, 0x218e2220, 0x2218e001, 0x9b0221c2, 0xb2db0412, 0x43134c2f, - 0x652b4323, 0x43119b03, 0x4313b2db, 0x60034323, 0x43194b2b, 0x21476101, 0x614101c9, 0x29009900, - 0x21cbd00d, 0x42a7039c, 0x21ccd300, 0x43194311, 0x49246029, 0x21236069, 0x63010149, 0x4922e024, - 0x491b6029, 0x9a016069, 0x73912101, 0x2000e7f3, 0x70084669, 0x208270ca, 0x46177048, 0xf0009800, - 0x2001fca5, 0x21027420, 0x21e77461, 0x756761a1, 0x82607520, 0x66284807, 0x38814806, 0x48076668, - 0x990166a8, 0x73082002, 0xb0294630, 0x0000bdf0, 0x000016ac, 0x04000481, 0x04010400, 0x00002001, - 0x00000406, 0x24040405, 0xa7040705, 0x8b2007fd, 0xa704b306, 0x00000706, 0x0000a304, 0x08000400, - 0x0b000400, 0x2704330c, 0x8b2004fd, 0xb09cb5f7, 0x460c981e, 0x02286805, 0x28050f00, 0x2600d011, - 0x223049cb, 0xa80d4479, 0xff5af7fc, 0x0f000428, 0x0328900a, 0x980a0f05, 0xd0042800, 0xd1132803, - 0x2601e001, 0x2d00e7ec, 0x2d03d010, 0x2800d10c, 0x2003d00a, 0x20107320, 0x981e6420, 0x02006800, - 0x28040f00, 0xe019d018, 0xe16e2704, 0xf0004668, 0x4607fa81, 0xf0002000, 0x2f00fc39, 0x466ad106, - 0x981c4621, 0xfb38f000, 0xd1ee0007, 0x73202000, 0x64202010, 0xe0022003, 0x64202050, 0x90092006, - 0x4328980a, 0x2601d100, 0x990a4620, 0x29033040, 0x2101d008, 0x46217141, 0xf7ff981c, 0x0007fb75, - 0xe001d1d3, 0xe7f52108, 0x2d002000, 0x2e00d004, 0x2001d001, 0x2002e000, 0xa90d0100, 0x23011842, - 0x981c4619, 0xfc38f000, 0x46692000, 0x75089002, 0x71082003, 0x90032001, 0xa80b9004, 0xa9019008, - 0xf7fe981c, 0x0007fbdb, 0xa808d1af, 0x28c27b00, 0x2101d1ab, 0x2d000409, 0xd01da808, 0x460a7c40, + 0x7d009102, 0x22009003, 0x980b990c, 0xff27f7ff, 0x950a3550, 0x9009cd01, 0xd01a2800, 0x22004633, + 0x980b990c, 0xfea0f7ff, 0xd13e0004, 0x96019802, 0x980c0101, 0x180a9b03, 0x32802101, 0xf001980b, + 0x2001ff57, 0x46699002, 0xf001980b, 0x0004fe60, 0x9809d12b, 0x18361c7f, 0xd3db2f04, 0xd1242c00, + 0x90092000, 0x980c4606, 0x30ff9d0a, 0x900a30c1, 0x2f00cd80, 0x2200d013, 0x990c9b09, 0xf7ff980b, + 0x0004fec6, 0x980ad111, 0x28007bc0, 0x2200d007, 0x990c9b09, 0xf7ff980b, 0x0004fe99, 0x9809d105, + 0x19c01c76, 0x2e049009, 0x980bd3e2, 0xf959f002, 0x990c2201, 0xf7ff980b, 0x4620fed2, 0xb5f7e6a5, + 0x4617b08a, 0x4608460d, 0xfc70f001, 0x22004606, 0x980a4629, 0xfec3f7ff, 0x4632463b, 0x980a4629, + 0xfe42f7ff, 0xd1390004, 0x97014669, 0x20057008, 0x90022401, 0x740e9403, 0x5d402047, 0xd0092800, + 0x30ff4628, 0x7b013081, 0xd0032900, 0x91027b41, 0x90037b00, 0x21019802, 0x19420100, 0x9b033280, + 0xf001980a, 0x4669fee5, 0x980a9402, 0xfdeff001, 0xd1130004, 0x4632463b, 0x980a4629, 0xfe67f7ff, + 0xd10b0004, 0x30d020ff, 0x28005d40, 0x463bd006, 0x46294632, 0xf7ff980a, 0x4604fe39, 0xf002980a, + 0x2201f900, 0x980a4629, 0xfe79f7ff, 0xe64c4620, 0xb08ab5f7, 0x460d4617, 0xf0014608, 0x4606fc17, + 0x46292200, 0xf7ff980a, 0x463bfe6a, 0x46294632, 0xf7ff980a, 0x0004fde9, 0x4669d139, 0x70089701, + 0x24012008, 0x94039002, 0x2047740e, 0x28005d40, 0x4628d009, 0x308130ff, 0x29007f01, 0x7f41d003, + 0x7f009102, 0x98029003, 0x01002101, 0x32801942, 0x980a9b03, 0xfe8cf001, 0x94024669, 0xf001980a, + 0x0004fd96, 0x463bd113, 0x46294632, 0xf7ff980a, 0x0004fe0e, 0x20ffd10b, 0x5d4030d0, 0xd0062800, + 0x4632463b, 0x980a4629, 0xfde0f7ff, 0x980a4604, 0xf8a7f002, 0x46292201, 0xf7ff980a, 0x4620fe20, + 0xb5f0e5f3, 0x20044607, 0x461db089, 0x460e4614, 0xd00f2a00, 0x46682124, 0xfadaf002, 0x46692003, + 0x20017008, 0x95089002, 0x96019003, 0x46389407, 0xfd5df001, 0xbdf0b009, 0xb08fb5ff, 0x460c2000, + 0x900b900a, 0x900d900c, 0x25016811, 0x2905461e, 0x6851d202, 0xd3152940, 0x6c117425, 0x0f490249, + 0xf002000b, 0x0d07fbc9, 0x050b0905, 0x000d0705, 0xe00b2702, 0xe0092704, 0xe0072701, 0xe0052703, + 0xe03f7420, 0x05098831, 0xd03b0f0f, 0x90002000, 0x90024669, 0x20037508, 0x95097108, 0x95049503, + 0x2f019108, 0x2f02d007, 0x2f03d003, 0x2f04d02d, 0x48fdd104, 0x48fce001, 0x900a3830, 0xaa0a2301, + 0x980f4619, 0xfe04f001, 0x980fa901, 0xfd0ff001, 0xd1182800, 0x01006830, 0xd0050f00, 0x040088b0, + 0xd0010e01, 0x90000e00, 0x46202100, 0x74213080, 0xd00d2f01, 0x2f022202, 0x2f03d013, 0x2f04d029, + 0x7421d01f, 0xb0132000, 0x48e7bdf0, 0xe7d4300a, 0x064a9900, 0x4ae5d4f6, 0x20c36402, 0x20404001, + 0x9900e01e, 0xd4ed078b, 0x43114be1, 0x02086403, 0x74259000, 0x20047525, 0x98007560, 0x746561a0, + 0x9900e7e0, 0xd4dd078b, 0x33304bd8, 0x64034311, 0x9900e007, 0xd4d5060a, 0x323d4ad5, 0x20806402, + 0x91004301, 0xb5f7e7e5, 0x02402001, 0x2700b098, 0x46689001, 0x24017407, 0x9702460d, 0x29009403, + 0x48ccd072, 0xc84d4478, 0xc14da90d, 0x466a2003, 0xa8097010, 0x20109007, 0x462a9008, 0x21013280, + 0x98189b03, 0xfd94f001, 0x94024669, 0xf0019818, 0x2800fc9e, 0x9809d158, 0xd1081c40, 0x1c40980a, + 0x980bd105, 0xd1021c40, 0x1c40980c, 0x2210d007, 0xa80da909, 0xf9b1f002, 0xd1452800, 0x2300e034, + 0x4629461a, 0xf7ff9818, 0x2800fcaf, 0x2009d17b, 0x20029002, 0x70084669, 0x462aa80d, 0x90052610, + 0x960632ff, 0x21013211, 0x98189b03, 0xfd60f001, 0x94024669, 0xf0019818, 0x2800fc6a, 0x2300d163, + 0x4629461a, 0xf0019818, 0x2800fdb0, 0x9002d15b, 0x46692003, 0xa8097008, 0x96089007, 0xf0019818, + 0x2800fc56, 0xe7c2d14f, 0x90162032, 0x90152000, 0x21406c28, 0x64284308, 0x5d412046, 0x22012602, + 0xf7ff9818, 0xe038faa4, 0x2400e03d, 0x94129411, 0x94149413, 0x6d282101, 0x42880609, 0x488ed901, + 0x488ee000, 0x498e9011, 0x1840b2f0, 0x2301498d, 0x90124308, 0x2100aa11, 0xf0019818, 0x2003fd19, + 0x94024669, 0xa8097008, 0x20109007, 0x98189008, 0xfc1df001, 0xd0060004, 0xd0142f00, 0x2f00981a, + 0xd0106006, 0x2210e010, 0xa80da909, 0xf935f002, 0xd00c2800, 0x2f001c76, 0x9815d1f0, 0x1c409916, + 0x42889015, 0x4c78d3c1, 0xb01b4620, 0x2701bdf0, 0xb5ffe7e4, 0xb0824608, 0x9000305c, 0x68c8460b, + 0x27013308, 0xda032800, 0x1ec0463a, 0xe0014082, 0x08c21c40, 0x24ff9802, 0x9e026502, 0x68489201, + 0x340136ff, 0x28403681, 0x6434d201, 0x8d18e00a, 0x0f020600, 0x40904638, 0x03d22201, 0xd1004290, + 0x64304620, 0x24004d61, 0x00424620, 0x7f1718d2, 0xd00d2f00, 0x40ba2201, 0xd20142aa, 0x46844615, + 0xd90542a2, 0x053f2701, 0xd20142ba, 0x46864614, 0x28041c40, 0x6475d3e9, 0x98026534, 0x30c130ff, + 0xd10142a5, 0xe0002201, 0x72422200, 0x98012201, 0x42900612, 0x3140d92d, 0x28007e08, 0x9800d008, + 0x79014460, 0x60019804, 0x44709800, 0xe0187901, 0x00404660, 0x7f4018c0, 0x22dc2121, 0xd0022820, + 0xd10528d8, 0x9804e002, 0xe0016001, 0x60029804, 0x00404670, 0x7f4018c0, 0xd0022820, 0xd10528d8, + 0x9805e002, 0xe0016001, 0x60029805, 0xb0062000, 0x4660bdf0, 0x18c00040, 0x98047f41, 0x46706001, + 0x18c00040, 0xe7ec7f41, 0xb08db5ff, 0x90052004, 0x460f980f, 0x90033008, 0x305c980f, 0x20009009, + 0x98109004, 0x02006800, 0x28010f00, 0x9803d105, 0x03006800, 0x90040fc0, 0x2000d071, 0x99107338, + 0x78094606, 0x070aab0b, 0x21460f12, 0x900055ca, 0x90062018, 0x90072000, 0x4638aa0a, 0xf7ff990f, + 0x2101ff48, 0x06096d38, 0xd9014288, 0x90062020, 0x88009810, 0x0f000400, 0x4639d151, 0x9a0f9b10, + 0xf7ff980d, 0x9005fdd9, 0xd1f52800, 0x68009803, 0xd51d0281, 0x90072002, 0x7a009803, 0x0f4e0601, + 0x0ec006c0, 0x0000e01c, 0x24010435, 0x20010401, 0x20020401, 0x000026c4, 0x8a2004ee, 0x8a1804ed, + 0x00040200, 0xa604b000, 0x00004e2a, 0x00ffffff, 0xd5060240, 0x68809803, 0x0f4e0201, 0x0ec002c0, + 0x980f9000, 0x30409a06, 0x49fc1dfc, 0x900834f9, 0xd0022a20, 0x612048fa, 0x7e00e012, 0x28004bf9, + 0x9809d03b, 0x68004af8, 0xd50105c5, 0xe00348f7, 0xd5320600, 0x302248f3, 0x61206162, 0xe0a9e001, + 0x20016161, 0x463d7338, 0x358048f1, 0x48f16328, 0x980a6128, 0xb2c14af0, 0x04009806, 0x43114301, + 0x65299001, 0xb2c9990b, 0x43114301, 0x01402023, 0x63206021, 0x68009810, 0x0f010100, 0x9910d00f, + 0x060a6849, 0xd00a0e12, 0x9904b2c8, 0x90002600, 0xd0212900, 0x90000040, 0x6123e01e, 0x9904e7d0, + 0xd0192900, 0xd1170f00, 0x28209806, 0x48d5d104, 0x60281c40, 0x606848d9, 0x980d4639, 0xfaa4f7ff, + 0x28009005, 0x466ad166, 0x980d4639, 0xfddbf7ff, 0x28009005, 0x2600d1f6, 0x28189806, 0x2002d006, + 0x98049007, 0xd0202800, 0xe00320ee, 0x28009804, 0x20edd00a, 0x22406c39, 0x64394311, 0x43019901, + 0x430148c7, 0xe0376029, 0x68009803, 0xd5030281, 0x89009803, 0xe0030400, 0xd5040240, 0x68809803, + 0x90020e00, 0x2003e01f, 0x9808e019, 0x28007e00, 0x9809d00a, 0x06816800, 0x06c0d40a, 0x206cd513, + 0x20009002, 0xe00e9007, 0x68009803, 0xd5010281, 0xe7e620ec, 0xd5010240, 0xe7e2206c, 0x90022013, + 0x46062000, 0x99029000, 0x43089801, 0x06099907, 0x49a94308, 0x60284308, 0x463a9910, 0x32ff7809, + 0x32c10609, 0x0f0b2000, 0x2b009201, 0x0f09d003, 0xd0042901, 0x9800e06b, 0x90001980, 0x990fe049, + 0x29406849, 0x9903d3f7, 0x058a6b89, 0x0309d5f3, 0x22050f09, 0xd0014211, 0xe00b20a5, 0xd5090789, + 0x9b104639, 0x980d9a0f, 0xffa1f000, 0x28009005, 0x2001d14d, 0x220a9903, 0x04098f09, 0x42110e89, + 0x4990d007, 0x67616721, 0x29209906, 0x498ed109, 0x2211e006, 0xd03a4211, 0x6721498c, 0x498c6761, + 0x210167a1, 0x2e009a01, 0xd0117351, 0x29009904, 0x2e01d033, 0x2127d02e, 0x43080289, 0x06099900, + 0x43080a09, 0x43084983, 0x48836068, 0xe01760a8, 0x28009800, 0x9a04d00f, 0x2a004980, 0xb2c0d005, + 0x497f1840, 0x60684308, 0xb2c0e00a, 0x497d1840, 0x60684308, 0x487ce00b, 0x98046068, 0xd0062800, + 0x20019901, 0x6c387388, 0x43082140, 0x98056438, 0xbdf0b011, 0x09002126, 0x2e01e7ce, 0x2107d00c, + 0x43080289, 0x06099900, 0x43080a09, 0x4308496f, 0x486f6068, 0xe7ea60a8, 0x09002106, 0xb5f7e7f0, + 0xb0984e6c, 0xd008000d, 0x466a2308, 0x98182100, 0xfc37f7ff, 0xd1640004, 0x2404e001, 0x4966e061, + 0x42889800, 0x4634d001, 0x4668e05b, 0x60287900, 0x79804668, 0x280a1c40, 0x200ad900, 0x981a9016, + 0x28002108, 0x0209d000, 0xaa029816, 0x981800c3, 0xfc17f7ff, 0xd1440004, 0x46282164, 0xfef8f001, + 0xe03b2600, 0xaa0200f0, 0x18835c11, 0x020079d8, 0x20ff180a, 0x42820200, 0x4850d002, 0xd12c4282, + 0x20022100, 0x1819020f, 0x43397909, 0xd5f91e40, 0x008778d8, 0x2800981a, 0x0209d000, 0x020020ff, + 0xd10c4282, 0xd9002f50, 0x462a2750, 0x3208463b, 0xf7ff9818, 0x0004fbe6, 0x606fd113, 0x483fe00d, + 0xd10a4282, 0x463b462a, 0x9818325c, 0xfbd9f7ff, 0xd1060004, 0x20582101, 0x1c765541, 0x42869816, + 0x4620d3c0, 0xb5f7e541, 0xb088460d, 0x46282103, 0x230873e9, 0x71433040, 0x642b2358, 0x73292401, + 0xd0012a00, 0x64292159, 0x210f71c4, 0x87c48781, 0x2001462e, 0x024036ff, 0x64303681, 0x64700240, + 0x46306530, 0x90073040, 0x46297244, 0xf7ff9808, 0x2800f91b, 0x4822d172, 0x90002700, 0x97034821, + 0x90012301, 0x466a9702, 0x98084619, 0xfa00f001, 0x97039702, 0x481c4f1a, 0xe0373780, 0x00002004, + 0x08180402, 0x08200412, 0x00002204, 0x0a20043e, 0x00000406, 0x24040405, 0x08000400, 0x00012404, + 0x8a000400, 0x06ff06ff, 0x000006ff, 0x06000600, 0x32101e00, 0xb2000200, 0x7c01a604, 0x00040200, + 0xa604b000, 0x26043000, 0x00002404, 0x32000200, 0x7c012604, 0x00004e27, 0x50444653, 0x0000ff84, + 0x8b188720, 0xa3028f10, 0xa7048f10, 0x23019001, 0x2100466a, 0x98089700, 0xf9baf001, 0x02c02013, + 0x23029006, 0x49feaa06, 0xf0009808, 0x2800fefc, 0x2308d114, 0x2110aa04, 0xf0009808, 0x2800fee0, + 0x9805d10c, 0xb28049f7, 0x98049005, 0xd1044288, 0x98052159, 0x42880209, 0x48f3d002, 0xbdf0b00b, + 0xaa042308, 0x98082127, 0xfec9f000, 0xd1f52800, 0x04009804, 0x90040e00, 0x28093817, 0x9904d8ed, + 0x40882001, 0x200f6528, 0x90060300, 0xaa062302, 0x98082100, 0xfec7f000, 0xd1df2800, 0x49e3462c, + 0x60213480, 0x606149e2, 0x60a149e2, 0x4ae349e2, 0x4fe44be3, 0xc48e3410, 0x60274fdc, 0x60674fe2, + 0x60a74fdc, 0xc40e3410, 0x60a74fe0, 0x60616022, 0x60e74fdf, 0x61274fdd, 0x4fde35ff, 0xc58e3511, + 0x34144fd2, 0x602f3fa0, 0x606f4fdb, 0xc48e4fdb, 0x4fd6c40e, 0x602260a7, 0x4fd56061, 0x4fd360e7, + 0x4cca6127, 0x3ca03d20, 0x4cd5602c, 0x4cd5606c, 0x462f60ac, 0x37304cd1, 0xc70ec71e, 0x656c4ccb, + 0x652964ea, 0x65ac4cca, 0x37144cc8, 0xc70e65ec, 0x66e949cd, 0x72312102, 0x72722203, 0x22017131, + 0x74317172, 0x74712109, 0x73312104, 0x73732305, 0x210b7531, 0x99077571, 0xe77f730a, 0x2504b5f7, + 0x4617b092, 0x2a00460c, 0x7878d004, 0x42887839, 0x2500d101, 0x4620e087, 0x21083040, 0x71419011, + 0x25037878, 0x28422601, 0x2841d001, 0x2502d103, 0x21049811, 0x78787141, 0xd0012882, 0xd1002842, + 0x20002621, 0x90014669, 0x70087408, 0x90022001, 0xa8092120, 0xfd6cf001, 0x200278f9, 0x29060242, + 0x2907d00b, 0x2908d012, 0x2001d001, 0x0229e02b, 0x43131d8b, 0x930931ff, 0x0229e005, 0x3366460b, + 0x31994313, 0x43119309, 0xe01c910d, 0x460f0229, 0x376602b2, 0x4317062b, 0x431f06b5, 0x432f46ac, + 0x31992599, 0x4311042d, 0x4319432f, 0x22334665, 0x04524329, 0x97094311, 0x2e21910d, 0x6c21d103, + 0x43112240, 0x90036421, 0x20019911, 0x06017188, 0x498e6521, 0x498e6021, 0x21036061, 0x73a17361, + 0x31c921ff, 0x200a5508, 0x46216760, 0xf7fe9812, 0x0005ffab, 0xaa09d117, 0x9b032101, 0xf0019812, + 0x4669f897, 0xf0009812, 0x4605ffa2, 0x217d4881, 0x00c94448, 0xf0016800, 0xe001fd0d, 0x1e40bf00, + 0x28009011, 0x4628d1fa, 0xbdf0b015, 0xb09cb5f7, 0x460c981e, 0x02286805, 0x28050f00, 0x2700d011, + 0x22304975, 0xa80d4479, 0xf9daf7fe, 0x0f000428, 0x0328900a, 0x980a0f05, 0xd0042800, 0xd1132803, + 0x2701e001, 0x2d00e7ec, 0x2d03d010, 0x2800d10c, 0x2003d00a, 0x20107320, 0x981e6420, 0x02006800, + 0x28040f00, 0xe019d018, 0xe1952604, 0xf7fe4668, 0x4606ff4c, 0xf7fe2000, 0x2e00ff44, 0x466ad106, + 0x981c4621, 0xff2af7ff, 0xd1ee0006, 0x73202000, 0x64202010, 0xe0022003, 0x64202050, 0x90092006, + 0x4328980a, 0x2701d100, 0x990a4620, 0x29033040, 0x2101d008, 0x46217141, 0xf7fe981c, 0x0006ff35, + 0xe001d1d3, 0xe7f52108, 0x2d002000, 0x2f00d004, 0x2001d001, 0x2002e000, 0xa90d0100, 0x23011842, + 0x981c4619, 0xf814f001, 0x46692000, 0x75089002, 0x71082003, 0x90032001, 0xa80b9004, 0xa9019008, + 0xf000981c, 0x0006ff14, 0xa808d1af, 0x28c27b00, 0x2101d1ab, 0x2d000409, 0xd01da808, 0x460a7c40, 0x40823830, 0x46206522, 0x30ff2201, 0x30810312, 0x11126442, 0x65016402, 0x73202003, 0x64202010, - 0x40462001, 0x46294620, 0x30c130ff, 0x35804625, 0x29009019, 0xe045d002, 0xe7e07b80, 0x2803980a, - 0x2101d140, 0x20027421, 0x82617460, 0x75622206, 0x23007521, 0x22074669, 0x70ca700b, 0xd0172e00, - 0x466a2182, 0x61a07051, 0x66284872, 0x38724871, 0x48716668, 0x981e66a8, 0x06007800, 0x28030f00, - 0x9919d002, 0xe01a728b, 0x20019919, 0xe0167288, 0x466b2181, 0x61a07059, 0x48684b66, 0x6668662b, - 0x66a84865, 0x46202101, 0x30207721, 0x70017042, 0x63214860, 0x672b3872, 0x485f6768, 0x980067a8, - 0xfb84f000, 0x6328485e, 0x6128485e, 0x990a1de0, 0x290030f9, 0x2e00d003, 0x2321d016, 0x2101e015, - 0x49597321, 0x49596029, 0x49576069, 0x61011d89, 0x61414957, 0x31154954, 0x49536529, 0x600131d0, - 0x01492123, 0xe0906301, 0x2e002301, 0x2122d001, 0x2102e000, 0x2e00468c, 0x212cd001, 0x210ce000, - 0x2e00911a, 0x2129d001, 0x2109e000, 0x2e00910a, 0x2128d001, 0x2108e000, 0x2e009100, 0x4a40d007, - 0x3a180299, 0x069a1889, 0x4a424311, 0x22fbe006, 0x00920299, 0x069a1889, 0x4a3f4311, 0x60294311, - 0x22194661, 0x01520289, 0x991a188a, 0x06894696, 0x4a3a4311, 0x60694311, 0x22c1990a, 0x00920289, - 0x920a188a, 0x60aa0299, 0x069b4a35, 0x469c188a, 0x4b34431a, 0x642b4313, 0x1e5b4b31, 0x466318ca, - 0x4b31431a, 0x622b4313, 0x021b2303, 0x466318ca, 0x2303431a, 0x4313061b, 0x62ab626b, 0x9a0a4b28, - 0x62ea330c, 0x466318ca, 0x4b28431a, 0x61034313, 0x46729b00, 0x431a069b, 0x049b23c1, 0x61434313, - 0x331b4b1f, 0x466318ca, 0x4b21431a, 0x46724313, 0x656a652b, 0x009222f7, 0x4663188d, 0x4b1d431d, - 0x431d4672, 0x60426005, 0x0152221b, 0x46631889, 0x43194a19, 0x63014311, 0xd0032e00, 0x21406c20, - 0x64204308, 0x20029919, 0x46387308, 0xbdf0b01f, 0x00001448, 0x04000472, 0x20010400, 0x04020400, - 0x00000406, 0x24040405, 0x0820040c, 0x24043008, 0x00002004, 0x03110000, 0x03130000, 0x03060000, - 0x00000306, 0x03f90000, 0x03fa0000, 0x03ed0000, 0x03de0000, 0x03230000, 0x039f0000, 0x4607b5f0, - 0xb0a92000, 0x4616460d, 0x49262404, 0x90269025, 0x22309027, 0x90284479, 0xf7fca819, 0x6830fd91, - 0x0f000300, 0x2104d13b, 0x55412045, 0x491e4628, 0x60013080, 0x6041491d, 0x46384629, 0xf9e4f7ff, - 0xd12c0004, 0x06007830, 0x28010f00, 0x1de8d10e, 0x30f94917, 0x67416701, 0x67811409, 0x461a2300, - 0x46384629, 0xf840f7ff, 0xd1180004, 0xa9196830, 0x0f000300, 0x18420100, 0x46192301, 0xf0004638, - 0x2200fa9b, 0x46384669, 0xf8c8f000, 0xd1060004, 0x466a4633, 0x46384629, 0xfc42f000, 0x46204604, - 0xbdf0b029, 0x00001088, 0x08180403, 0x00012404, 0x06ff06ff, 0x2704b5f7, 0x460c4615, 0xd05a2900, - 0xd0582d00, 0x462001f9, 0xfe50f7fc, 0x46262101, 0x71b13640, 0x65200608, 0x60204828, 0x60604828, - 0x73602003, 0x20ff73a0, 0x550130c9, 0x01006828, 0xd0080f00, 0x03006868, 0x28010f00, 0x6c20d103, - 0x43080209, 0x68286420, 0x0f000200, 0xf7fe0003, 0x060af82f, 0x17110c06, 0x231d1d17, 0x462a3023, - 0x98004621, 0xff6af7ff, 0x2201e001, 0x0007e003, 0xe01ed018, 0x46212200, 0xf7ff9800, 0xe7f6fb75, - 0x4621462a, 0xf7ff9800, 0xe7f0fd91, 0x4621462a, 0xf7ff9800, 0xe7eafc77, 0x4621462a, 0xf7ff9800, - 0xe7e4f9f9, 0xf0004620, 0x7828f9f7, 0x0f000700, 0x200171b0, 0x46387130, 0x0000bdfe, 0x42464346, - 0x56010400, 0xb089b530, 0x466d2403, 0x2501702c, 0x24000049, 0x91019503, 0x466d9402, 0x4669742c, - 0x92079308, 0xf9baf7fe, 0xbd30b009, 0xb089b530, 0x466d2402, 0x2401702c, 0x91010049, 0x94039402, - 0x74292100, 0x93064669, 0xf7fe9205, 0xb009f9a7, 0x0000bd30, 0x6a894902, 0x20006001, 0x00004770, - 0x400f8000, 0x4607b5f0, 0xb0892004, 0x4614461d, 0x2a00460e, 0x2124d00f, 0xf7fc4668, 0x2003fdb7, - 0x70084669, 0x90022001, 0x90039508, 0x94079601, 0xf7fe4638, 0xb009f983, 0x0000bdf0, 0x4e3ab5f7, - 0x000db098, 0x2308d008, 0x2100466a, 0xf7ff9818, 0x0004ffd9, 0xe001d164, 0xe0612404, 0x98004933, - 0xd0014288, 0xe05b4634, 0x79004668, 0x46686028, 0x1c407980, 0xd900280a, 0x9016200a, 0x2108981a, - 0xd0002800, 0x98160209, 0x00c3aa02, 0xf7ff9818, 0x0004ffb9, 0x2164d144, 0xf7fc4628, 0x2600fd77, - 0x00f0e03b, 0x5c11aa02, 0x79d81883, 0x180a0200, 0x020020ff, 0xd0024282, 0x4282481d, 0x2100d12c, - 0x020f2002, 0x79091819, 0x1e404339, 0x78d8d5f9, 0x981a0087, 0xd0002800, 0x20ff0209, 0x42820200, - 0x2f50d10c, 0x2750d900, 0x463b462a, 0x98183208, 0xff88f7ff, 0xd1130004, 0xe00d606f, 0x4282480c, - 0x462ad10a, 0x325c463b, 0xf7ff9818, 0x0004ff7b, 0x2101d106, 0x55412058, 0x98161c76, 0xd3c04286, - 0xb01b4620, 0x0000bdf0, 0x00004e8b, 0x50444653, 0x0000ff84, 0xb089b5ff, 0x4616461d, 0x9809460c, - 0xf8e1f000, 0xd1142800, 0x70084669, 0x200e2701, 0x90029703, 0x4622740e, 0x326132ff, 0x4639463b, - 0x98099501, 0xf938f000, 0x97024669, 0xf7fe9809, 0xb00df8e5, 0x0000bdf0, 0x2504b5f7, 0x4617b092, - 0x2a00460c, 0x7878d004, 0x42887839, 0x2500d101, 0x4620e087, 0x21083040, 0x71419011, 0x25037878, - 0x28422601, 0x2841d001, 0x2502d103, 0x21049811, 0x78787141, 0xd0012882, 0xd1002842, 0x20002621, - 0x90014669, 0x70087408, 0x90022001, 0xa8092120, 0xfcdcf7fc, 0x200278f9, 0x29060242, 0x2907d00b, - 0x2908d012, 0x2001d001, 0x0229e02b, 0x43131d8b, 0x930931ff, 0x0229e005, 0x3366460b, 0x31994313, - 0x43119309, 0xe01c910d, 0x460f0229, 0x376602b2, 0x4317062b, 0x431f06b5, 0x432f46ac, 0x31992599, - 0x4311042d, 0x4319432f, 0x22334665, 0x04524329, 0x97094311, 0x2e21910d, 0x6c21d103, 0x43112240, - 0x90036421, 0x20019911, 0x06017188, 0x49166521, 0x49166021, 0x21036061, 0x73a17361, 0x31c921ff, - 0x200a5508, 0x46216760, 0xf7fe9812, 0x0005ffdd, 0xaa09d117, 0x9b032101, 0xf0009812, 0x4669f8ad, - 0xf7fe9812, 0x4605f85b, 0x217d4809, 0x00c94448, 0xf7fc6800, 0xe001fc7d, 0x1e40bf00, 0x28009011, - 0x4628d1fa, 0xbdf0b015, 0x42464346, 0x56010400, 0x00000058, 0x2004b5ff, 0x469cb083, 0x29004696, - 0x460dd01f, 0x35c135ff, 0x460c7b28, 0x28023480, 0x4620d10b, 0xc8893010, 0x69e6466a, 0x4620c289, - 0xc88d3020, 0xc48d3410, 0x46633c20, 0x98034672, 0xfad2f7fe, 0x29027b29, 0x466dd103, 0x3410cd0e, - 0xb007c44e, 0xb5ffbdf0, 0xb0832004, 0x2900460d, 0x462ed029, 0x36c136ff, 0x28007b70, 0x9b06d006, - 0x98039a05, 0xfdf0f7fe, 0xd11c2800, 0x462c7b30, 0x28023480, 0x4620d10a, 0xc8873030, 0xc307466b, - 0x30404620, 0x3430c80f, 0x3c40c40f, 0x9b064629, 0x98039a05, 0xfb80f7fe, 0x29027b31, 0x466dd103, - 0x3430cd0e, 0xb007c48e, 0x0000bdf0, 0x62884901, 0x47702000, 0x400f8000, 0x28002104, 0x7b01d00f, - 0xd10b2903, 0x30606c01, 0x29000649, 0x2113da01, 0x7e41e003, 0xd1012900, 0x76012126, 0x46082100, - 0xb5f84770, 0x460f4606, 0x2001e002, 0xf94ef000, 0x463c2000, 0x1e7643c0, 0x46274144, 0x43f943f0, - 0xd1f24308, 0x6801bdf8, 0x43112201, 0x68016001, 0xd1fc07c9, 0x00004770, 0x460eb5f8, 0x461f2104, - 0x91004615, 0xfba4f7fe, 0xd0230004, 0xd0212d00, 0x19f22100, 0x23104149, 0x1a9a2000, 0xd3194188, - 0xf0004620, 0x4a0cf825, 0x200261a2, 0x19f161e0, 0x008b00b0, 0x19090081, 0x31ff31ff, 0xe0023102, - 0xc140cd40, 0x42981c40, 0x61a2d3fa, 0x61e02001, 0x90002000, 0xbdf89800, 0x5af05af0, 0xf7feb510, - 0x2800fb77, 0x3080d003, 0x07896e01, 0xbd10d5fc, 0x6e013080, 0xd0fc07c9, 0x07896e01, 0x4770d5fc, - 0x4805b510, 0x05806940, 0x48040f81, 0x44481c49, 0xf7fc6800, 0xbd10fb8d, 0x400fc000, 0x00000058, - 0x4805b510, 0x05806940, 0x48040f81, 0x44481c49, 0xf7fc6800, 0xbd10fb7d, 0x400fc000, 0x00000058, - 0x4608b5ff, 0x305cb082, 0x460b9000, 0x330868c8, 0x28002701, 0x463ada03, 0x40821ec0, 0x1c40e001, - 0x980208c2, 0x650224ff, 0x92019e02, 0x36ff6848, 0x36813401, 0xd2012840, 0xe00a6434, 0x06008d18, - 0x46380f02, 0x22014090, 0x429003d2, 0x4620d100, 0x4d316430, 0x46202400, 0x18d20042, 0x2f007f17, - 0x2201d00d, 0x42aa40ba, 0x4615d201, 0x42a24684, 0x2701d905, 0x42ba053f, 0x4614d201, 0x1c404686, - 0xd3e92804, 0x65346475, 0x30ff9802, 0x42a530c1, 0x2201d101, 0x2200e000, 0x22017242, 0x06129801, - 0xd92d4290, 0x7e083140, 0xd0082800, 0x44609800, 0x98047901, 0x98006001, 0x79014470, 0x4660e018, - 0x18c00040, 0x21217f40, 0x282022dc, 0x28d8d002, 0xe002d105, 0x60019804, 0x9804e001, 0x46706002, - 0x18c00040, 0x28207f40, 0x28d8d002, 0xe002d105, 0x60019805, 0x9805e001, 0x20006002, 0xbdf0b006, - 0x00404660, 0x7f4118c0, 0x60019804, 0x00404670, 0x7f4118c0, 0x0000e7ec, 0x00ffffff, 0x20ff4a0e, - 0x68526851, 0x0f890609, 0x0f920692, 0xd0072900, 0xd00f2901, 0xd0072902, 0xd1002903, 0x47702002, - 0xd0032a00, 0xd0032a01, 0x47702008, 0x47702001, 0x47702010, 0x47702020, 0x400f8000, 0x47704800, - 0x01312d00, 0x2003b510, 0x21030240, 0xfbbaf7fc, 0x2000bd10, 0x20004770, 0x00004770, 0xb5104903, - 0x00c04449, 0xf7fc6809, 0xbd10fab3, 0x0000004c, 0xb5104905, 0x68094449, 0xfc92f7fd, 0x08c0074a, - 0x08c94310, 0x0000bd10, 0x0000004c, 0x4602b570, 0xf832f000, 0x4909460d, 0x44494604, 0x68094610, - 0xfc7ef7fd, 0x08c3074a, 0x08ca4313, 0x416a191c, 0xf822f000, 0x41911b00, 0xbd70d3fa, 0x0000004c, - 0x4809b510, 0x69c06941, 0x0f890589, 0x48070684, 0x44480ea4, 0x1c496800, 0xf7fc1c64, 0x4621fa79, - 0xfa76f7fc, 0x0000bd10, 0x400fc000, 0x00000058, 0xf7ffb510, 0xbd10fed5, 0x4803b508, 0x6a406a01, - 0x43c09000, 0xbd0843c9, 0x400840c0, 0x4813b510, 0x68012304, 0x03122203, 0x43114391, 0x48106001, - 0x60012100, 0x1e4a480f, 0x61816102, 0x61c42401, 0x43196981, 0x69816181, 0x61814321, 0x60c46002, - 0xf7ff6084, 0x00c0ffbd, 0xf7fc4907, 0x4907fa41, 0x44492800, 0xd1006008, 0xbd10600c, 0x400fc06c, - 0x40084000, 0x40084100, 0x000f4240, 0x0000004c, 0x68014802, 0x43112202, 0x47706001, 0x40084000, - 0xb08bb5ff, 0x90032004, 0x460f980d, 0x90013008, 0x305c980d, 0x20009008, 0x980e9002, 0x02006800, - 0x28010f00, 0x9801d105, 0x03006800, 0x90020fc0, 0x2000d07e, 0x990e7338, 0x78094606, 0x070aab0a, - 0x21460f12, 0x900055ca, 0x90042018, 0x90052000, 0x4638aa09, 0xf7ff990d, 0x2101fe83, 0x06096d38, - 0xd9014288, 0x90042020, 0x8800980e, 0x0f000400, 0x4639d15e, 0x9a0d9b0e, 0xf000980b, 0x9003f9cb, - 0xd1f52800, 0x68009801, 0xd5080281, 0x90052002, 0x7a009801, 0x0f4e0601, 0x0ec006c0, 0x0240e007, - 0x9801d506, 0x02016880, 0x02c00f4e, 0x90000ec0, 0x9a04980d, 0x1dfc3040, 0x34f949a2, 0x2a209007, - 0x48a1d002, 0xe0116120, 0x4ba07e00, 0xd03c2800, 0x4a9f9808, 0x05c56800, 0x489ed501, 0x0600e003, - 0x489ad533, 0x61623022, 0xe0006120, 0x20016161, 0x463d7338, 0x35804898, 0x48986328, 0x98096128, - 0xb2c14a97, 0x04009804, 0x43114301, 0x65299006, 0xb2c9990a, 0x43114301, 0x01402023, 0x63206021, - 0x6800980e, 0x0f010100, 0x990ed011, 0xe0006849, 0x060ae0e3, 0xd00a0e12, 0x9902b2c8, 0x90002600, - 0xd0212900, 0x90000040, 0x6123e01e, 0x9902e7ce, 0xd0192900, 0xd1170f00, 0x28209804, 0x487bd104, - 0x60281c40, 0x6068487f, 0x980b4639, 0xfcbcf7fe, 0x28009003, 0x466ad185, 0x980b4639, 0xf9e8f000, - 0x28009003, 0x2600d1f6, 0x28189804, 0xd0039802, 0xd01c2800, 0xe00220ee, 0xd0082800, 0x6c3920ed, - 0x43112240, 0x99066439, 0x486f4301, 0x9801e033, 0x02816800, 0x9801d503, 0x04008900, 0x0240e003, - 0x9801d503, 0x0e006880, 0x2003e01f, 0x9807e010, 0x28007e00, 0x9808d010, 0x06816800, 0x20ecd502, - 0xe0032102, 0xd52706c0, 0x2100206c, 0xe00c9105, 0x460e2100, 0xe0089100, 0x68009801, 0xd5010281, - 0xe00220ec, 0xd5170240, 0x9906206c, 0x98054301, 0x43010600, 0x463a4852, 0x60294301, 0x32ff990e, - 0x32c17809, 0x20000609, 0x92050f0b, 0xd0052b00, 0x29010f09, 0xe06dd006, 0xe7d92013, 0x19809800, - 0xe0499000, 0x6849990d, 0xd3f72940, 0x6b899901, 0xd5f3058a, 0x0f090309, 0x42112205, 0x20a5d001, - 0x0789e00b, 0x4639d509, 0x9a0d9b0e, 0xf000980b, 0x9003f895, 0xd14d2800, 0x99012001, 0x8f09220a, - 0x0e890409, 0xd0074211, 0x67214938, 0x99046761, 0xd1092920, 0xe0064936, 0x42112211, 0x4935d03a, - 0x67616721, 0x67a14934, 0x9a052101, 0x73512e00, 0x9902d011, 0xd0332900, 0xd02e2e01, 0x02892127, - 0x99004308, 0x0a090609, 0x492c4308, 0x60684308, 0x60a8482b, 0x9800e017, 0xd00f2800, 0x49299a02, - 0xd0052a00, 0x1840b2c0, 0x43084927, 0xe00a6068, 0x1840b2c0, 0x43084925, 0xe00b6068, 0x60684824, - 0x28009802, 0x9905d006, 0x73882001, 0x21406c38, 0x64384308, 0xb00f9803, 0x2126bdf0, 0xe7ce0900, - 0xd00c2e01, 0x02892107, 0x99004308, 0x0a090609, 0x49184308, 0x60684308, 0x60a84817, 0x2106e7ea, - 0xe7f00900, 0x00002004, 0x08180402, 0x08200412, 0x00002204, 0x0a20043e, 0x00000406, 0x24040405, - 0x08000400, 0x00012404, 0x8a000400, 0x06ff06ff, 0x000006ff, 0x06000600, 0x32101e00, 0xb2000200, - 0x7c01a604, 0x00040200, 0xa604b000, 0x26043000, 0x00002404, 0x32000200, 0x7c012604, 0xb08eb570, - 0x2100460c, 0x9100910c, 0x910d910b, 0x9102466a, 0x75114606, 0x71102003, 0x95032501, 0x95094813, - 0x900a9208, 0x9504462b, 0x4629aa0a, 0xf7ff4630, 0xa901fc63, 0xf7fd4630, 0x2800fc11, 0x9900d113, - 0x401122f7, 0x040a4b0a, 0x910018d3, 0x742522ff, 0x51133261, 0x220e7525, 0x61a17562, 0x74612104, - 0x34c134ff, 0xb00e73e5, 0x0000bd70, 0x24010485, 0x04000481, 0xb08fb5ff, 0x460c2000, 0x900b900a, - 0x900d900c, 0x25016811, 0x2905461e, 0x6851d202, 0xd3152940, 0x6c117425, 0x0f490249, 0xf7fd000b, - 0x0d07fa07, 0x050b0905, 0x000d0705, 0xe00b2702, 0xe0092704, 0xe0072701, 0xe0052703, 0xe06d7420, - 0x05098831, 0xd0690f0f, 0x90002000, 0x90024669, 0x20037508, 0x95097108, 0x95049503, 0x2f019108, - 0x2f02d007, 0x2f03d003, 0x2f04d02a, 0x482dd104, 0x482ce001, 0x900a3830, 0xaa0a2301, 0x980f4619, - 0xfbfaf7ff, 0x980fa901, 0xfba8f7fd, 0xd1462800, 0x01006830, 0xd0050f00, 0x040088b0, 0xd0010e01, - 0x90000e00, 0x74202000, 0x30804620, 0xd00a2f01, 0x2f022202, 0x2f03d010, 0x2f04d026, 0xe01bd12e, - 0x300a4818, 0x9900e7d7, 0xd427064a, 0x66024a16, 0x400120c3, 0xe01e2040, 0x078b9900, 0x4b13d41e, - 0x66034311, 0x90000208, 0x75257425, 0x75602006, 0x61a09800, 0xe0117465, 0x078b9900, 0x4b0ad40e, - 0x43113330, 0xe0076603, 0x060a9900, 0x4a07d406, 0x6602323d, 0x43012080, 0xe7e59100, 0xb0132000, - 0x0000bdf0, 0x24010435, 0x20010401, 0x20020401, 0x2001b5f7, 0xb0980240, 0x90012700, 0x74074668, - 0x460d2401, 0x94039702, 0xd0722900, 0x4478485b, 0xa90dc84d, 0x2003c14d, 0x7010466a, 0x9007a809, - 0x90082010, 0x3280462a, 0x9b032101, 0xf7ff9818, 0x4669fb83, 0x98189402, 0xfb30f7fd, 0xd1582800, - 0x1c409809, 0x980ad108, 0xd1051c40, 0x1c40980b, 0x980cd102, 0xd0071c40, 0xa9092210, 0xf7fba80d, - 0x2800fefa, 0xe034d145, 0x461a2300, 0x98184629, 0xfaf9f7ff, 0xd17b2800, 0x90022009, 0x46692002, - 0xa80d7008, 0x2610462a, 0x32ff9005, 0x32119606, 0x9b032101, 0xf7ff9818, 0x4669fb4f, 0x98189402, - 0xfafcf7fd, 0xd1632800, 0x461a2300, 0x98184629, 0xfda2f7fd, 0xd15b2800, 0x20039002, 0x70084669, - 0x9007a809, 0x98189608, 0xfae8f7fd, 0xd14f2800, 0x2032e7c2, 0x20009016, 0x6c289015, 0x43082140, - 0x20466428, 0x26025d41, 0x98182201, 0xfa64f7fd, 0xe03de038, 0x94112400, 0x94139412, 0x21019414, - 0x06096d28, 0xd9014288, 0xe000481d, 0x9011481d, 0xb2f0491d, 0x491d1840, 0x43082301, 0xaa119012, - 0x98182100, 0xfb08f7ff, 0x46692003, 0x70089402, 0x9007a809, 0x90082010, 0xf7fd9818, 0x0004faaf, - 0x2f00d006, 0x981ad014, 0x60062f00, 0xe010d010, 0xa9092210, 0xf7fba80d, 0x2800fe7e, 0x1c76d00c, - 0xd1f02f00, 0x99169815, 0x90151c40, 0xd3c14288, 0xb01b4c07, 0xbdf04620, 0xe7e42701, 0x000001fe, - 0x8a2004ee, 0x8a1804ed, 0x00040200, 0xa604b000, 0x00004e8e, 0x00004770, 0x6801480d, 0x43112203, - 0x480c6001, 0x61412140, 0x480b0401, 0x04816381, 0x21006381, 0x48096001, 0x04d26b01, 0x63014311, - 0x68014807, 0x00490849, 0x20016001, 0x00004770, 0x400fc080, 0x400d8000, 0x400d9000, 0x400d8180, - 0x402e0140, 0x08220000, 0x06180816, 0x0612041e, 0x050d060e, 0x0216040d, 0x06180000, 0x060c0416, - 0x0312021e, 0x01210216, 0x0116020d, 0x402a8000, 0x33221100, 0x77665544, 0xbbaa9988, 0xffeeddcc, - 0x0818045a, 0x24ff3008, 0x00000000, 0x00000000, 0x0918055a, 0x25ff3108, 0x00000000, 0x00000000, - 0x0a18065a, 0x26ff3208, 0x00000000, 0x00000000, 0x2403049f, 0x00000000, 0x00000000, 0x00000000, - 0x0760079f, 0x27040b20, 0x00000000, 0x00000000, 0x8760879f, 0xa7048b20, 0x00000000, 0x00000000, - 0x0818045a, 0x24ff3008, 0x00000000, 0x00000000, 0x8b20075a, 0x0000a7ff, 0x00000000, 0x00000000, - 0x0818045a, 0x24ff3008, 0x00000000, 0x00000000, 0x0a18065a, 0x000026ff, 0x00000000, 0x00000000, - 0x0b18075a, 0x000027ff, 0x00000000, 0x00000000, 0x8a18065a, 0x0000a6ff, 0x00000000, 0x00000000, - 0x8b20075a, 0x0000a7ff, 0x00000000, 0x00000000, 0x00000000, 0x40184000, 0x40188000, 0x4018c000, - 0x40190000, 0x40194000, 0x40198000, 0x4019c000, 0x401a0000, 0x0014ff80, 0x00160015, 0x00180017, - 0x001a0019, 0xffff001b, 0x001c0518, 0x0118000c, 0x03060302, 0x060e051a, 0x017d7840, 0x02faf080, - 0x05f5e100, 0x07735940, 0x00000000, 0x00000000, 0x00000000, 0x412000d1, 0x60002000, 0x00000000, - 0x00000000, 0x60001020, 0x60001000, 0x00000000, 0x00000000, 0x60000000, 0x00800000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x11b3dc40, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x40472001, 0x46294620, 0x30c130ff, 0x35804625, 0x29009019, 0xe078d002, 0xe7e07b80, 0x2803980a, + 0x2101d173, 0x20027421, 0x82617460, 0x75622206, 0x23007521, 0x22074669, 0x70ca700b, 0xd04a2f00, + 0x466a2182, 0x61a07051, 0x6628481c, 0x3872481b, 0x481b6668, 0x981e66a8, 0x06007800, 0xe0310f00, + 0x00000555, 0x52005100, 0x00004e29, 0x8b1887a0, 0xb3068f10, 0x0000a704, 0x87008700, 0x87aa8700, + 0x87058700, 0x87708700, 0xb70b8f10, 0x87558700, 0x87028700, 0x87a08700, 0xa3808f10, 0x87808700, + 0x87008f10, 0x00008730, 0x87108700, 0x42464346, 0x56010400, 0x0000000c, 0x00001ca4, 0x04000472, + 0x20010400, 0xd0022803, 0x728b9919, 0x9919e01a, 0x72882001, 0x2181e016, 0x7059466b, 0x4bfe61a0, + 0x662b48fe, 0x48fe6668, 0x210166a8, 0x77214620, 0x70423020, 0x48f87001, 0x38726321, 0x6768672b, + 0x67a848f7, 0xf7fe9800, 0x48f6fe5c, 0x48f66328, 0x1de06128, 0x30f9990a, 0xd0032900, 0xd0162f00, + 0xe0152321, 0x73212101, 0x602949f0, 0x606949f0, 0x1d8949ee, 0x49ef6101, 0x49ec6141, 0x65293115, + 0x31d049ea, 0x21236001, 0x63010149, 0x2301e084, 0xd0012f00, 0xe0002122, 0x468e2102, 0xd0012f00, + 0xe000212c, 0x911a210c, 0xd0012f00, 0xe0002129, 0x910a2109, 0xd0012f00, 0xe0002128, 0x91002108, + 0x4ad80299, 0x3a18069b, 0x469c188a, 0x4bda431a, 0x602a431a, 0x23194672, 0x015b0292, 0x9b1a18d2, + 0x069b4696, 0x4bd5431a, 0x606b4313, 0x029a9b0a, 0x009b23c1, 0x920a18d2, 0x1c9a60aa, 0x4663188a, + 0x4bcf431a, 0x4acf4313, 0x188a642b, 0x431a4663, 0x43134bcd, 0x02122203, 0x188a622b, 0x431a4663, + 0x061b2303, 0x626a431a, 0x4ac662aa, 0x320d9b0a, 0x188a62eb, 0x431a4663, 0x43134bc4, 0x9b006103, + 0x069b4672, 0x23c1431a, 0x4313049b, 0x61434abd, 0x188a321c, 0x431a4663, 0x43134bbd, 0x4672652b, + 0x22f7656a, 0x188d0092, 0x431d4663, 0x46724bb9, 0x6005431d, 0x221b6042, 0x18890152, 0x4ab64663, + 0x43114319, 0x2f006301, 0x6c20d003, 0x43082140, 0x99196420, 0x73082002, 0xb01f4630, 0xb5f7bdf0, + 0x49ae460c, 0x4617b0a6, 0x44792220, 0xf7fea81d, 0x6838f817, 0x0f000200, 0xd0092807, 0x90002000, + 0x03006838, 0xd0050f00, 0x73202003, 0xe0142050, 0xe7f42001, 0xf7fea801, 0x4605fd98, 0xf7fe2000, + 0x2d00fd90, 0xaa01d106, 0x98264621, 0xfd76f7ff, 0xd1140006, 0x73202000, 0x46252010, 0x35402108, + 0x71696420, 0x98264621, 0xfd8ef7fe, 0xd1f00006, 0x03006838, 0xd0030f01, 0x28030f00, 0xe09ed003, + 0xaa1d2301, 0x2301e001, 0x2101aa21, 0xf0009826, 0x2008fe6f, 0x22007168, 0x9826a904, 0xfbbff7ff, + 0xd1220006, 0xaa02ab03, 0x4620a904, 0xf971f7ff, 0x28009800, 0x2050d103, 0x20036420, 0x46257320, + 0x35804870, 0x48706328, 0x68396128, 0x0f020308, 0x30ff4620, 0x900130c1, 0x2a0338c0, 0x0409d006, + 0x2a030f0a, 0x0f09d002, 0xe068d01b, 0x62294974, 0x60294974, 0x60694974, 0x64294974, 0x39dc4971, + 0x49706529, 0x60013921, 0x0149213b, 0x496d6301, 0x610139eb, 0x6141496e, 0x03006838, 0xd02f0f00, + 0x2201e04a, 0x06126d21, 0xd3024291, 0x218e2220, 0x2218e001, 0x9b0221c2, 0xb2db0412, 0x43134c65, + 0x652b4323, 0x43119b03, 0x4313b2db, 0x43234a62, 0x60034311, 0x21476101, 0x614101c9, 0x29009900, + 0x495ed00a, 0x495e6029, 0x21236069, 0x63010149, 0x20019901, 0xe0227388, 0x6029495a, 0xe7f34952, + 0x46692000, 0x27067008, 0x208270cf, 0x98007048, 0xfce7f7fe, 0x74202001, 0x74612102, 0x61a121e7, + 0x75207567, 0x48348260, 0x6628300f, 0x38724832, 0x48386668, 0x66a81ec0, 0x20029901, 0x46307308, + 0xbdf0b029, 0xb0b4b5f7, 0x90004847, 0x46156810, 0x0f000200, 0x2809460c, 0x2600d01b, 0x22504943, + 0xa81e4479, 0xff2cf7fd, 0x90022000, 0x30404620, 0x90012104, 0x68287141, 0x04000301, 0x20100f05, + 0x64200f0f, 0xd0062f00, 0xd01b2f02, 0xd01f2f03, 0x2601e169, 0xa804e7e2, 0xfca7f7fe, 0x20009000, + 0xfc9ff7fe, 0x28009800, 0xaa04d107, 0x98344621, 0xfc84f7ff, 0x28009000, 0x9901d1ea, 0x71482001, + 0xe0032000, 0x20049901, 0x20037148, 0xe0087320, 0x73202003, 0x99012008, 0x71482e00, 0x2001d101, + 0x2d009002, 0x2d02d003, 0x2d03d001, 0x4638d1d0, 0xd1004328, 0xe03b2601, 0x04000472, 0x04020400, + 0x20010400, 0x00000406, 0x24040405, 0x0820040c, 0x24043308, 0x00002004, 0x03110000, 0x03060000, + 0x03f90000, 0x00000305, 0x03fa0000, 0x03ed0000, 0x03de0000, 0x03230000, 0x039f0000, 0x0000194e, + 0xa7040705, 0x8b2007fd, 0xa704b306, 0x00000706, 0x0000a304, 0x08000400, 0x0b000400, 0x0b2004fc, + 0x27043306, 0x8b2004fd, 0x00004e29, 0x00001798, 0xd0022d02, 0xd0022d03, 0x2004e004, 0x2008e000, + 0x71489901, 0x6c212040, 0xd0012e00, 0xe0004381, 0x64214301, 0x98344621, 0xfc36f7fe, 0x28009000, + 0x2e00d18a, 0x2f02d008, 0x2f03d002, 0xe001d10c, 0xe0092001, 0xe0072002, 0xd0022f02, 0xd1032f03, + 0x2003e001, 0x2004e000, 0xa91e0100, 0x23011842, 0x98344619, 0xfd0cf000, 0x9a02a905, 0xf7ff9834, + 0x9000fa5e, 0xd17d2800, 0xaa32ab33, 0x4620a905, 0xf80ff7ff, 0x73202003, 0x30804620, 0x630149fd, + 0x610149fd, 0xd0012e00, 0xe0002302, 0x2e002322, 0x210cd001, 0x212ce000, 0x2e00468e, 0x2109d001, + 0x2129e000, 0x2e009102, 0x2208d001, 0x2228e000, 0x0d8f07a9, 0x46399204, 0x07aa9701, 0x370b0992, + 0x4317069b, 0x431f469c, 0x431f4bec, 0x46736007, 0x029b1d0f, 0x9b02431f, 0x069b4317, 0x9302431f, + 0x049b2301, 0x6047431f, 0x3720460f, 0x46634317, 0x4be2431f, 0x431f4696, 0x460f6507, 0x431737d8, + 0x431f4663, 0x431f4bdd, 0x33f91de3, 0x1c8f601f, 0x46624317, 0x4ad94317, 0x611f4317, 0x9a04460f, + 0x02923780, 0x22014317, 0x31600292, 0x4311615f, 0x63192702, 0xd0012d02, 0xd10f2d03, 0x46739901, + 0x43191d49, 0x43199b02, 0x43194bcd, 0x99016201, 0x43111d89, 0x32cd22ff, 0x55176401, 0x61a12100, + 0xe0002d02, 0xd002e03f, 0xd0032d03, 0x2201e005, 0xe0010492, 0x04d22201, 0x2e0061a2, 0x6c22d010, + 0x431a2380, 0x22016422, 0x551a2379, 0x66024abd, 0x66424abd, 0x74202001, 0xd0072d00, 0xe0067467, + 0x69a22301, 0x431a05db, 0xe7ef61a2, 0x22067461, 0x75207562, 0x46688260, 0x2e007301, 0x2d02d008, + 0x2d03d002, 0xe007d002, 0xe0122041, 0xe0102081, 0xd00b2d02, 0xd00b2d03, 0x20087341, 0x73c84669, + 0xf7fe9803, 0x9800fb3e, 0xbdf0b037, 0xe0002042, 0x46692082, 0xe7f07348, 0x2704b5f7, 0x460c4616, + 0xd04d2900, 0xd04b2e00, 0x462001f9, 0xf8b0f001, 0x46252101, 0x71a93540, 0x65200608, 0x6020489b, + 0x6060489b, 0x73602003, 0x20ff73a0, 0x550130c9, 0x02006830, 0x00030f00, 0xf9aef001, 0x0c06060a, + 0x1d171711, 0x3023231d, 0x46214632, 0xf0009800, 0xe001f8d6, 0xe0032201, 0xd0180007, 0x2200e01e, + 0x98004621, 0xf9cff7ff, 0x4632e7f6, 0x98004621, 0xfb7cf7ff, 0x4632e7f0, 0x98004621, 0xfd3ff7ff, + 0x4632e7ea, 0x98004621, 0xfe1cf7ff, 0x4620e7e4, 0xfad2f7fe, 0x07007830, 0x71a80f00, 0x71282001, + 0xbdfe4638, 0x2004b5ff, 0x460fb081, 0xd01e2900, 0x35ff463d, 0x6c693581, 0x460c4249, 0x18d24014, + 0x400a4252, 0x31ca21ff, 0x42565dc9, 0xd10c2900, 0x29006d29, 0xe02ad009, 0x46394622, 0xf7fe9801, + 0x2800fcae, 0x6c69d103, 0x42b4190c, 0xb005d3f4, 0x6d29bdf0, 0x43884620, 0x2000d00e, 0x28001b32, + 0x4291d00c, 0x4622d80a, 0x98014639, 0xfcf0f7fe, 0xd1ec2800, 0xe0096d29, 0xe7ef2001, 0x46394622, + 0xf7fe9801, 0x2800fc8c, 0x6c69d1e1, 0x42b4190c, 0xe7dcd3df, 0xb089b5ff, 0x9c122004, 0x4616461f, + 0xd0222900, 0xd0202e00, 0xd01e2c00, 0xf0004608, 0x2103f8ed, 0x7011466a, 0x91032101, 0x91022100, + 0x4d4c7410, 0xd80042ac, 0x46694625, 0x96079701, 0x98099508, 0xfa8bf000, 0xd1062800, 0x008908a9, + 0x197f1b64, 0x2c00198e, 0xb00dd1eb, 0xb570bdf0, 0x460cb08e, 0x910c2100, 0x910b9100, 0x466a910d, + 0x46069102, 0x20037511, 0x25017110, 0x483a9503, 0x92089509, 0x462b900a, 0xaa0a9504, 0x46304629, + 0xfb56f000, 0x4630a901, 0xfa61f000, 0xd1142800, 0x22f79900, 0x4b2b4011, 0x3310040a, 0x910018d3, + 0x742522ff, 0x51133261, 0x220e7525, 0x61a17562, 0x74612104, 0x34c134ff, 0xb00e73e5, 0xb5f0bd70, + 0x20004607, 0x460db0a9, 0x24044616, 0x90254923, 0x90279026, 0x44792230, 0xa8199028, 0xfc90f7fd, + 0x03006830, 0xd1580f00, 0x20452104, 0x46285541, 0x3080491b, 0x491b6001, 0x46296041, 0xf7fe4638, + 0x0004fa23, 0x7830d149, 0x0f000600, 0xd10e2801, 0x49151de8, 0x670130f9, 0x14096741, 0x23006781, + 0x4629461a, 0xf7fe4638, 0x0004fa24, 0x6830d135, 0xe01b0300, 0x00000406, 0x24040405, 0x00200400, + 0x00040400, 0x04000471, 0x00002003, 0x42464346, 0x56010400, 0x0000ffff, 0x24010485, 0x000011e2, + 0x08180403, 0x00012404, 0x06ff06ff, 0x01000f00, 0x1842a919, 0x46192301, 0xf0004638, 0x2200fad9, + 0x46384669, 0xf82bf7ff, 0xd1060004, 0x466a4633, 0x46384629, 0xfe68f7fe, 0x46204604, 0xb530e4f0, + 0x2403b089, 0x702c466d, 0x00492501, 0x95032400, 0x94029101, 0x742c466d, 0x93084669, 0xf0009207, + 0xb009f9c6, 0xb530bd30, 0x2402b089, 0x702c466d, 0x00492401, 0x94029101, 0x21009403, 0x46697429, + 0x92059306, 0xf9b3f000, 0x0000e7eb, 0x07406c00, 0x2001d501, 0x20004770, 0x6c004770, 0xd5010680, + 0x47702001, 0x47702000, 0x07c06c00, 0x2001d000, 0x6c004770, 0xd5010700, 0x47702001, 0x47702000, + 0x07806c00, 0x2001d501, 0x20004770, 0x6c004770, 0xd5010640, 0x47702001, 0x47702000, 0xb085b5f3, + 0x2404460e, 0xf0009805, 0x0005fcce, 0x2e00d07e, 0x7b30d07c, 0xd8792803, 0xd00a2800, 0xd0082801, + 0xd0062802, 0xd1042803, 0xf7ff4630, 0x2800ffd9, 0x20ffd002, 0xe00c3001, 0x2102aa03, 0xf7fe9805, + 0x49fef816, 0x42889803, 0x6c30d306, 0xd4030600, 0x90002079, 0xe0219001, 0x00602400, 0x31601981, + 0x7e0f7e48, 0xd10b2800, 0x43472064, 0x214bd01d, 0xf0004638, 0x214bfebf, 0x42b94341, 0x1c40d200, + 0x283f213f, 0x4608d900, 0x0c400680, 0x30ff00a2, 0x46693001, 0x50881c64, 0xd3de2c02, 0x22026828, + 0x28000780, 0x2000da1c, 0x4630e01e, 0xff9ff7ff, 0x46024607, 0x9805a902, 0xf804f7fe, 0x990248e0, + 0xd0092f00, 0xfe96f000, 0x217d0880, 0x434800c9, 0xf000214b, 0xe7d2fe8f, 0xfe8cf000, 0xe7f40840, + 0x20016829, 0x60294311, 0x29006d31, 0x6d71d102, 0xd0022900, 0x9b0021c0, 0x6db1514b, 0xd1022900, + 0x29006df1, 0x21c4d004, 0xe0009b01, 0x514be006, 0xd0022800, 0x43906828, 0x24006028, 0xb0074620, + 0xb5f8bdf0, 0x20044607, 0x460e461c, 0xd0162f00, 0xd0142a00, 0xd0122c00, 0x48c14611, 0xfe5af000, + 0x46054601, 0x46304361, 0xfe54f000, 0x1c40e000, 0x43694601, 0x42b14361, 0x6038d3f9, 0xbdf82000, + 0xb085b5f0, 0x460e4db7, 0x95004607, 0xf0009501, 0x0004fc1a, 0x2e00d02b, 0xaa02d029, 0x46382102, + 0xff75f7fd, 0x2101aa03, 0xf7fd4638, 0x2601ff70, 0x02b64fad, 0x46394633, 0x9a024668, 0xffc1f7ff, + 0x46394633, 0x9a03a801, 0xffbbf7ff, 0x42a89800, 0x9500d900, 0x42a89801, 0x9501d900, 0x99019800, + 0xb2890400, 0x60604308, 0xb0052000, 0x2004bdf0, 0xb5f3e7fb, 0x2000b087, 0x460c9000, 0x98072504, + 0xfbe1f000, 0x28009003, 0x2c00d054, 0x4620d052, 0x46273040, 0x37509005, 0x30ff2600, 0x90023041, + 0x00b26838, 0x98030a81, 0x90011810, 0x7ba06601, 0x06c51d3f, 0x0eed7b60, 0x0d8006c0, 0x7be04305, + 0x0c400700, 0x46204305, 0xfed3f7ff, 0xd0022800, 0x02802001, 0x6f604305, 0xd00d2800, 0x2102aa04, + 0xf7fd9807, 0x2301ff14, 0x46686f61, 0xf7ff9a04, 0x9800ff68, 0x43050400, 0x67059801, 0x79c09805, + 0xd00e2800, 0x7c009802, 0xd00a0741, 0x22079902, 0x03407c49, 0x0d090709, 0x18800352, 0x4308b280, + 0x2009e001, 0x99010200, 0x60083180, 0x2e041c76, 0x2500d3b6, 0xb0094628, 0x4602bdf0, 0x2004b510, + 0xd0212a00, 0xd01f2900, 0x5c402044, 0xd10c2801, 0x084368d0, 0x2040005b, 0x46084303, 0xfe76f7ff, + 0xd0012800, 0x43032001, 0x68d060d3, 0x43082120, 0x4b5e60d0, 0x00812000, 0x6a0c1889, 0x620c401c, + 0x28031c40, 0x2000d3f7, 0xb510bd10, 0xfb5bf000, 0xd00b2800, 0x23012100, 0x008a07db, 0x32801812, + 0x431c6814, 0x1c496014, 0xd3f62904, 0xb5febd10, 0x20044605, 0x460e9000, 0xf0004628, 0x0004fb44, + 0x2e00d07e, 0x7830d0fc, 0xd8792803, 0x90017c30, 0x46202700, 0xfb3ff000, 0xf7ff4628, 0x6960ffd6, + 0x4308211e, 0x46256160, 0x68703580, 0x78306228, 0xd0022802, 0xd0022803, 0x8b30e003, 0x8c30e000, + 0x7b31b287, 0x1e497a30, 0x07490700, 0x09490b00, 0x99014308, 0x430807c9, 0x62684338, 0x28037830, + 0x69f0d14b, 0x07836a32, 0x2340d14a, 0x469e211c, 0x6bab63a9, 0x430b2101, 0x6bab63ab, 0xd1fc07db, + 0x430b6b2b, 0xe036632b, 0x31f91de1, 0x45724673, 0x6967d30f, 0x06bf089b, 0xe029d402, 0xc080c980, + 0xd2fb1e5b, 0x1a524671, 0x23206961, 0x61614319, 0x6f2be01e, 0x0d5b061b, 0xd2034293, 0xc908e018, + 0xc0081f12, 0xd2fa2a04, 0xd0102a00, 0x91016809, 0x468ca901, 0x23004601, 0x4667e007, 0x700f783f, + 0x1c7f4667, 0x46bc1c49, 0x42931c5b, 0x2200d3f5, 0x07096961, 0x2a00d401, 0x7830d1c6, 0xe0002802, + 0xd001e062, 0xd1482801, 0x69b26971, 0xd15b0788, 0x46842040, 0x63e8201c, 0xe0096be8, 0x05f5e100, + 0x3b9aca00, 0x0000ffff, 0x1dcd6500, 0xfcf0ff00, 0x43182301, 0x6be863e8, 0xd1fc07c0, 0xe02a4686, + 0x30ff4620, 0x30816963, 0xd521065b, 0x089b4663, 0xd2024562, 0xc980e00e, 0x1e5bc080, 0x4660d2fb, + 0xe0091a12, 0xdd032a00, 0xc080c980, 0xe0011f12, 0xc0802700, 0xd2f51e5b, 0x28004670, 0x6b28d104, + 0x43182301, 0x469e6328, 0x23406960, 0x61604318, 0x07006960, 0x2a00d401, 0x7830dcd2, 0xd1032800, + 0x21016b28, 0x63284308, 0xf0004620, 0x6960fa74, 0xd50b0700, 0x01006e68, 0x280e0f00, 0x48fed001, + 0x48fde001, 0x90001e40, 0xbdfe9800, 0xe7fa2000, 0x460eb5f8, 0x461f2104, 0x91004615, 0xfa53f000, + 0xd0230004, 0xd0212d00, 0x19f22100, 0x23104149, 0x1a9a2000, 0xd3194188, 0xf0004620, 0x4aeffa4c, + 0x200261a2, 0x19f161e0, 0x008b00b0, 0x19090081, 0x31ff31ff, 0xe0023102, 0xc140cd40, 0x42981c40, + 0x61a2d3fa, 0x61e02001, 0x90002000, 0xbdf89800, 0x4604b570, 0xb08a2004, 0xd0242900, 0x466e2000, + 0x20037030, 0x90022501, 0x74329503, 0x93012047, 0x28005c40, 0x4608d009, 0x308130ff, 0x2a007a02, + 0x7a42d003, 0x7a009202, 0x98029003, 0x01009b03, 0x21011842, 0x32804620, 0xffaaf7ff, 0x46204669, + 0xf7ff9502, 0xb00afeb4, 0xb5ffbd70, 0xb0912004, 0x900e460d, 0xd0792900, 0x30404628, 0x21018f82, + 0x4094460c, 0x93028fc2, 0x22039200, 0x711a466b, 0x91039104, 0x9108a90c, 0x29009913, 0x2108d001, + 0x2104e000, 0x99139109, 0x79c07519, 0xd0092800, 0x30ff4628, 0x79013081, 0xd0032900, 0x91037941, + 0x90047900, 0x9b049803, 0x19420100, 0x99033280, 0xf7ff9811, 0x6f2dff6d, 0xd0012d00, 0xe0002001, + 0x26002000, 0xa901900f, 0xf7ff9811, 0x900efe70, 0xd13b2800, 0x28009813, 0xa90ad019, 0xab0ca80b, + 0x781f2208, 0x785f700f, 0x1c407007, 0x1e921c49, 0x2a001c9b, 0x9800d1f5, 0x2800990b, 0xd004980a, + 0x46214008, 0xd10a4381, 0x4308e00e, 0x9800e00a, 0xd0062800, 0x4620990c, 0x28004388, 0x2701d004, + 0x980ce003, 0xe7f84020, 0x980f2700, 0xd00b4207, 0x43304628, 0x207dd00d, 0x210000c0, 0xfd2cf7fd, + 0x43c02000, 0x41461e6d, 0xd1bc2f00, 0xb015980e, 0x4889bdf0, 0x900e1c40, 0xb5f7e7f8, 0x460db08a, + 0x980a2604, 0xf96ff000, 0xd0540007, 0xd0522d00, 0x46692001, 0x980c7008, 0x20009001, 0x20047408, + 0x90062400, 0x194200a0, 0x30204610, 0x29007841, 0x2301d03e, 0x59db025b, 0x0f9b059b, 0x192bd003, + 0x2b027f5b, 0x9102d034, 0x32307800, 0x90039205, 0x46292200, 0x980a9b0c, 0xff1af7ff, 0xd12b2800, + 0x21019802, 0x19420100, 0x9b033280, 0xf7ff980a, 0x2001fedf, 0x46699002, 0xf7ff980a, 0x0006fde8, + 0x8a68d11a, 0xd10e2800, 0x7f491929, 0xd00a2902, 0xd0082903, 0x46292200, 0x980a9b0c, 0xff25f7ff, + 0xd1090006, 0x2164e004, 0x21004348, 0xfcc4f7fd, 0x2c031c64, 0x4630d3b6, 0xbdf0b00d, 0xb087b5f3, + 0x2604460d, 0xf0009807, 0x0004f90e, 0x2d00d07e, 0x7c28d0fc, 0xd1022800, 0x28007f28, 0x6c28d009, + 0xd40406c0, 0xf7ff4628, 0x2800fc22, 0x2001d001, 0x2000e000, 0x494a9003, 0x42886828, 0x9807d166, + 0xfbfdf7fd, 0x98074629, 0xfcdef7fd, 0x30404628, 0x90029903, 0xd0022900, 0x21012200, 0x4628e005, + 0xfc05f7ff, 0x98024602, 0x98077981, 0xfbeff7fd, 0xf7fd9807, 0x6820fbdc, 0x43b02602, 0x46206020, + 0xf8c9f000, 0x43306820, 0x68206020, 0x40084935, 0x79499902, 0xd1012908, 0x43080289, 0x43084932, + 0x07897b29, 0x43010e89, 0x46296021, 0xf7ff9807, 0x68a0fc97, 0x03c92101, 0x60a04388, 0xf7ff4628, + 0x2800fbc3, 0x68a0d004, 0x04c92101, 0x60a04308, 0x46204629, 0xfd21f7ff, 0x98074629, 0xfcb9f7ff, + 0x98074629, 0xfbcaf7ff, 0x21026820, 0x60204388, 0xf0004620, 0x4628f890, 0x30507c29, 0x29009004, + 0x9807d01c, 0x20049005, 0xe0002100, 0x9e04e05d, 0x460f9100, 0x9101ce02, 0xd00a2900, 0x9a004629, + 0xf0009805, 0x2800f890, 0x9a01d106, 0x18899900, 0x1c7f9100, 0xd3ed2f04, 0xd1460006, 0x28007f28, + 0x9807d027, 0x20049005, 0xd0202d00, 0x9e042100, 0x460f9100, 0xe009ce02, 0x00001b59, 0x5af05af0, + 0x42464346, 0x0000df0f, 0xffff0000, 0x29009101, 0x4629d00a, 0x98059a00, 0xfedff7ff, 0xd1062800, + 0x99009a01, 0x91001889, 0x2f041c7f, 0x0006d3e2, 0x9803d11b, 0xd0172800, 0x26026820, 0x60204330, + 0xf7ff4628, 0x4602fb64, 0x79819802, 0xf7fd9807, 0x4629fb4e, 0xf7ff9807, 0x4629fc13, 0xf7ff9807, + 0x6820fb5d, 0x602043b0, 0x46302600, 0xb510e4a3, 0xf829f000, 0xd0032800, 0x6e013080, 0xd5fc0789, + 0xb510bd10, 0xf81ff000, 0xd0012800, 0xf813f000, 0xb570bd10, 0xf000460d, 0x0004f816, 0xf000d00a, + 0x2001f81a, 0x682102c0, 0xd0012d00, 0xe0004301, 0x60214381, 0x6801bd70, 0x43112201, 0x68016001, + 0xd1fc07c9, 0x46014770, 0x29002000, 0x4830d102, 0x68004478, 0x30804770, 0x07c96e01, 0x6e01d0fc, + 0xd5fc0789, 0xb5f04770, 0x4616b089, 0x4607460c, 0xf7ff2504, 0x2800ffe8, 0x2c00d048, 0x30ffd046, + 0x300230ff, 0x05806800, 0xd0020f80, 0x28027c60, 0x2501d025, 0x700d4669, 0x7d609601, 0x7d209002, + 0x20009003, 0x46207408, 0x90053018, 0x90062004, 0x22004633, 0x46384621, 0xfd9af7ff, 0x21019802, + 0x19020100, 0x32804638, 0xf7ff9b03, 0x4669fd61, 0x95024638, 0xfc6bf7ff, 0xd1170005, 0x2500e001, + 0x8a61e014, 0xd10c2900, 0x28027c60, 0x2803d009, 0x4633d007, 0x46212200, 0xf7ff4638, 0x4605fda6, + 0x2064e004, 0x21004348, 0xfb46f7fd, 0xe4124628, 0x00000798, 0xb5704770, 0x88014864, 0x2104074a, + 0xda022a00, 0x438a8802, 0x48618002, 0x07528802, 0x8802d502, 0x8002438a, 0x495e485f, 0x495f6041, + 0x68016081, 0x43912280, 0x43112220, 0x485c6001, 0x07c96901, 0x6901d003, 0x00490849, 0xf3bf6101, + 0xf3bf8f4f, 0x4d578f6f, 0x61292100, 0x8f4ff3bf, 0x8f6ff3bf, 0x69604c54, 0x04522201, 0x61604310, + 0x8f4ff3bf, 0x8f6ff3bf, 0x3080484f, 0xf3bf6041, 0x68008f4f, 0x0c490101, 0x0d8304c0, 0x461805ca, + 0x07820c96, 0x622a4332, 0xd2fa1e40, 0xd2f51e49, 0x8f4ff3bf, 0x21016960, 0x43080409, 0xf3bf6160, + 0xf3bf8f4f, 0xf7ff8f6f, 0xbd70ffa5, 0x4e3fb5f8, 0x4d3f6b30, 0xd50103c0, 0xe007462c, 0x07c06b30, + 0x2416d001, 0x2414e000, 0x43444839, 0x30404837, 0x69006a07, 0xf0004629, 0x463afa47, 0xf0002300, + 0x6931f871, 0x03c91900, 0x462ad501, 0x6931e007, 0xd0010789, 0xe0002216, 0x492d2214, 0x4c2d434a, + 0x01896961, 0x69a0d511, 0x03092103, 0xd0054008, 0x03092101, 0xd0034288, 0xe0022000, 0xe0004610, + 0x69614628, 0x0f490089, 0x69a1e010, 0x049b2303, 0xd0104019, 0x049b2301, 0xd0161ac9, 0xd01b1ac9, + 0xd1074299, 0x07416920, 0x0f49481b, 0xf0001c49, 0xe000f911, 0x69612000, 0x0f4904c9, 0xf0001c49, + 0x4916f909, 0x60084449, 0x4810bdf8, 0x6b0030c0, 0x0e810080, 0xe0034610, 0x68094911, 0x0e890289, + 0xf8f8f000, 0x43482112, 0x0000e7e5, 0x400b8000, 0x400d0000, 0xd928c520, 0x400bc000, 0x0000ffff, + 0xe000e000, 0xe000ef40, 0xe000ed00, 0x400d8000, 0x016e3600, 0x400fc000, 0x1dcd6500, 0x0000000c, + 0x400d8100, 0x4605b5fe, 0x460c4610, 0xd0734318, 0x468c46ae, 0x1aad2000, 0x419c4601, 0x4666d367, + 0x24012700, 0x1ab6463d, 0xd302419d, 0x463a4613, 0x46652421, 0x042f4676, 0x433e0c36, 0x1ab60c2d, + 0xd304419d, 0x041b0c15, 0x0412432b, 0x46653410, 0x062f4676, 0x433e0a36, 0x1ab60a2d, 0xd304419d, + 0x021b0e15, 0x0212432b, 0x46653408, 0x072f4676, 0x433e0936, 0x1ab6092d, 0xd304419d, 0x011b0f15, + 0x0112432b, 0x46651d24, 0x07af4676, 0x433e08b6, 0x1ab608ad, 0xd304419d, 0x009b0f95, 0x0092432b, + 0x46651ca4, 0x07ef4676, 0x433e0876, 0x1ab6086d, 0xd31a419d, 0x415b1892, 0xe0161c64, 0x46761800, + 0x41494665, 0x419d1ab7, 0x90009101, 0x4660d309, 0x41981ab1, 0x4684468e, 0x99019800, 0x1c402500, + 0x07dd4169, 0x432a0852, 0x1e64085b, 0x4672d5e6, 0xb0034663, 0xe7ffbdf0, 0x46012000, 0x46c046c0, + 0x4623462a, 0xb510e7f5, 0xf0002000, 0x46c0f907, 0x200146c0, 0xf8fcf000, 0x4603bd10, 0x430bb510, + 0xd10f079b, 0xd30d2a04, 0xc910c808, 0x42a31f12, 0xba18d0f8, 0x4288ba21, 0x2001d901, 0x2000bd10, + 0xbd1043c0, 0xd0032a00, 0xd00307d3, 0xe0071c52, 0xbd102000, 0x780c7803, 0x1c491c40, 0xd1071b1b, + 0x780c7803, 0x1c491c40, 0xd1011b1b, 0xd1f11e92, 0xbd104618, 0xc004e001, 0x29041f09, 0x078bd2fb, + 0x8002d501, 0x07c91c80, 0x7002d000, 0x29004770, 0x07c3d00b, 0x7002d002, 0x1e491c40, 0xd3042902, + 0xd5020783, 0x1c808002, 0xe7e31e89, 0xe7ee2200, 0xe7df2200, 0x09032200, 0xd32c428b, 0x428b0a03, + 0x2300d311, 0xe04e469c, 0x430b4603, 0x2200d43c, 0x428b0843, 0x0903d331, 0xd31c428b, 0x428b0a03, + 0x4694d301, 0x09c3e03f, 0xd301428b, 0x1ac001cb, 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152, + 0xd301428b, 0x1ac0014b, 0x09034152, 0xd301428b, 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb, + 0x08834152, 0xd301428b, 0x1ac0008b, 0x08434152, 0xd301428b, 0x1ac0004b, 0x1a414152, 0x4601d200, + 0x46104152, 0xe05d4770, 0xd0000fca, 0x10034249, 0x4240d300, 0x22004053, 0x0903469c, 0xd32d428b, + 0x428b0a03, 0x22fcd312, 0xba120189, 0x428b0a03, 0x0189d30c, 0x428b1192, 0x0189d308, 0x428b1192, + 0x0189d304, 0x1192d03a, 0x0989e000, 0x428b09c3, 0x01cbd301, 0x41521ac0, 0x428b0983, 0x018bd301, + 0x41521ac0, 0x428b0943, 0x014bd301, 0x41521ac0, 0x428b0903, 0x010bd301, 0x41521ac0, 0x428b08c3, + 0x00cbd301, 0x41521ac0, 0x428b0883, 0x008bd301, 0x41521ac0, 0x0843d2d9, 0xd301428b, 0x1ac0004b, + 0x1a414152, 0x4601d200, 0x41524663, 0x4610105b, 0x4240d301, 0xd5002b00, 0x47704249, 0x105b4663, + 0x4240d300, 0x2000b501, 0x46c046c0, 0x0000bd02, 0x20184901, 0xe7febeab, 0x00020026, 0xf000b510, + 0xf000f80b, 0xbd10f802, 0xb5104770, 0xd0012800, 0xffeef7ff, 0x0000bd10, 0x2100b510, 0xf000a002, + 0x2001f813, 0x0000bd10, 0x41474953, 0x3a545242, 0x6e624120, 0x616d726f, 0x6574206c, 0x6e696d72, + 0x6f697461, 0x0000006e, 0x4605b570, 0x200a460c, 0x1c6de000, 0xf812f000, 0xd0062d00, 0x28007828, + 0xe002d1f7, 0xf0001c64, 0x2c00f809, 0x7820d002, 0xd1f72800, 0xf000200a, 0xbd70f801, 0x4669b508, + 0x20037008, 0xbd08beab, 0x0c04b5f8, 0x4626b28b, 0x435eb282, 0x46100c0d, 0x43580c37, 0x19800436, + 0x41792100, 0x436e4616, 0x04360c37, 0x41791980, 0x436e4626, 0xbdf81989, 0x4674b430, 0x78251e64, + 0x42ab1c64, 0x461dd200, 0x005b5d63, 0xbc3018e3, 0x00004718, 0x017d7840, 0x02faf080, 0x05f5e100, + 0x07735940, 0x08220000, 0x06180816, 0x0612041e, 0x0411060e, 0x0216060c, 0x06180000, 0x060c0416, + 0x0312021e, 0x01210216, 0x0116011a, 0x33221100, 0x77665544, 0xbbaa9988, 0xffeeddcc, 0x0818045a, + 0x24ff3008, 0x00000000, 0x00000000, 0x0918055a, 0x25ff3108, 0x00000000, 0x00000000, 0x0a18065a, + 0x26ff3208, 0x00000000, 0x00000000, 0x2403049f, 0x00000000, 0x00000000, 0x00000000, 0x0760079f, + 0x27040b20, 0x00000000, 0x00000000, 0x8760879f, 0xa7048b20, 0x00000000, 0x00000000, 0x0818045a, + 0x24ff3008, 0x00000000, 0x00000000, 0x8b20075a, 0x0000a7ff, 0x00000000, 0x00000000, 0x0818045a, + 0x24ff3008, 0x00000000, 0x00000000, 0x0a18065a, 0x000026ff, 0x00000000, 0x00000000, 0x0b18075a, + 0x000027ff, 0x00000000, 0x00000000, 0x8a18065a, 0x0000a6ff, 0x00000000, 0x00000000, 0x8b20075a, + 0x0000a7ff, 0x00000000, 0x00000000, 0x402a8000, 0x00000000, 0x00000000, 0x00000000, 0x11b3dc40, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -601,8 +499,7 @@ static const uint32_t RT1020_S25LP064A_flash_prog_blob[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; // Start address of flash @@ -611,36 +508,41 @@ static const uint32_t flash_start = 0x60000000; static const uint32_t flash_size = 0x00800000; /** -* List of start and size for each size of flash sector +* List of start and size for each size of flash sector - even indexes are start, odd are size * The size will apply to all sectors between the listed address and the next address * in the list. * The last pair in the list will have sectors starting at that address and ending -* at address start + size. +* at address flash_start + flash_size. */ static const sector_info_t sectors_info[] = { {0x60000000, 0x00001000}, - }; +}; static const program_target_t flash = { - 0x20000b01, // Init - 0x200015ff, // UnInit - 0x20000abd, // EraseChip - 0x20000ae1, // EraseSector - 0x20001399, // ProgramPage - 0x0, // Verify - + 0x20000075, // Init + 0x200000e1, // UnInit + 0x200000e5, // EraseChip + 0x200000f9, // EraseSector + 0x20000117, // ProgramPage + 0x00000000, // Verify + // BKPT : start of blob + 1 // RSB : blob start + header + rw data offset // RSP : stack pointer { 0x20000001, - 0x200046a8, - 0x20000800 + 0x20003994, + 0x20004c00 }, - 0x20000000 + 0x00000A00, // mem buffer location - 0x20000000, // location to write prog_blob in target RAM - sizeof(RT1020_S25LP064A_flash_prog_blob), // prog_blob size - RT1020_S25LP064A_flash_prog_blob, // address of prog_blob - 0x00000100 // ram_to_flash_bytes_to_be_written + // mem buffer location + 0x20004c00, + // location to write prog_blob in target RAM + 0x20000000, + // prog_blob size + sizeof(MIMXRT1021_QuadSPI_4KB_SEC_flash_prog_blob), + // address of prog_blob + MIMXRT1021_QuadSPI_4KB_SEC_flash_prog_blob, + // ram_to_flash_bytes_to_be_written + 0x00000100 }; From a0ac2f1cbd55a859eb33f23e4669dbab8c4f60f9 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 30 Dec 2021 23:44:08 -0600 Subject: [PATCH 576/617] flash: minor aesthetic tweak to flash algo script --- tools/generate_flash_algo.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/generate_flash_algo.py b/tools/generate_flash_algo.py index 6dd3cac19..c84fcb37c 100644 --- a/tools/generate_flash_algo.py +++ b/tools/generate_flash_algo.py @@ -42,8 +42,8 @@ STACK_SIZE = 0x800 DAPLINK_TEMPLATE = \ -"""/* Flash OS Routines (Automagically Generated) - * +"""/*{%- if algo.flash_info.name %} Flash algorithm for {{ algo.flash_info.name.decode('utf-8') }} + *{% endif %} * DAPLink Interface Firmware * Copyright (c) {{year}} {{copyright_owner}} * SPDX-License-Identifier: Apache-2.0 @@ -282,8 +282,8 @@ def main(): 'header_size': HEADER_SIZE, 'entry': args.blob_start, 'stack_pointer': sp, - 'year': datetime.now().year, - 'copyright_owner': args.copyright or "Arm Limited", + 'year': datetime.now().year if args.copyright else ("2009-%d" % datetime.now().year), + 'copyright_owner': args.copyright or "Arm Limited, All Rights Reserved", } text = algo.process_template(tmpl, data_dict) From d64420d864e785a03684d4033afd638abf9fdf3e Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 23 Oct 2021 00:41:56 -0500 Subject: [PATCH 577/617] doc: update README.md in anticipation of merge to main branch --- README.md | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/README.md b/README.md index 52c756c66..19eb16209 100644 --- a/README.md +++ b/README.md @@ -3,14 +3,6 @@ [![Linux Build (develop)](https://github.com/ARMmbed/DAPLink/actions/workflows/linux.yml/badge.svg?branch=develop)](https://github.com/ARMmbed/DAPLink/actions/workflows/linux.yml) -# Warning: Development branch - -This is is a development branch of DAPLink: -- It adds support for the GCC (`gcc_arm`) and ARMC6 (`armclang`) compilers. ARMC5 (`armcc`) will be deprecated. -- It focuses on `progen` support using `make` and `cmake`. - -**Note:** The main branch of DAPLink requires an Arm Compiler 5 or Keil MDK license to build. - ---- Arm Mbed DAPLink is an open-source software project that enables programming and debugging application software running on Arm Cortex CPUs. Commonly referred to as interface firmware, DAPLink runs on a secondary MCU that is attached to the SWD or JTAG port of the application MCU. This configuration is found on nearly all development boards. Enumerating as a USB composite device, it creates a bridge between your development computer and the CPU debug access port. DAPLink enables developers with: @@ -42,9 +34,10 @@ There are many board builds (board = HIC + target combination) created from this ## Contribute -We welcome contributions to DAPLink in any area. Look for an interesting feature or defect [under -issues](https://github.com/ARMmbed/DAPLink/issues), or start a new thread to engage with the -developers and maintainers. +We welcome contributions to DAPLink in any area. Look for an interesting feature or defect +[under issues](https://github.com/ARMmbed/DAPLink/issues). Start a new thread [in the +discussions](https://github.com/ARMmbed/DAPLink/discussions) to engage with the developers +and maintainers. Please see the [contribution guidelines](CONTRIBUTING.md) for detailed requirements for contributions. From 172195e78f7eff4aaf811c88315de29ee3d2e33e Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sun, 2 Jan 2022 00:06:44 -0600 Subject: [PATCH 578/617] Add a few projects to the release --- test/info.py | 4 ++++ tools/progen_compile.py | 7 +++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/test/info.py b/test/info.py index 3c76a6288..d650ccaa2 100644 --- a/test/info.py +++ b/test/info.py @@ -40,6 +40,7 @@ ("lpc4322_lpc55s69xpresso_if", False, 0x10000, "bin" ), ("lpc11u35_ssci1114_if", False, 0x0000, "bin" ), ("sam3u2c_mkit_dk_dongle_nrf5x_if", True, 0x5000, "bin" ), + ("sam3u2c_nrf5x_dk_ext_if", True, 0x5000, "bin" ), ("k20dx_frdmk20dx_if", True, 0x8000, "bin" ), ("k20dx_frdmkw24d_if", True, 0x8000, "bin" ), ("k20dx_frdmkw41z_if", True, 0x8000, "bin" ), @@ -60,6 +61,8 @@ ("k20dx_mimxrt1020_evk_qspi_if", True, 0x8000, "bin" ), ("k20dx_mimxrt1050_evk_hyper_if", True, 0x8000, "bin" ), ("k20dx_mimxrt1050_evk_qspi_if", True, 0x8000, "bin" ), + ("lpc4322_mimxrt1060_evk_qspi_if", False, 0x10000, "bin" ), + ("lpc4322_mimxrt1170_evk_qspi_if", False, 0x10000, "bin" ), ('k20dx_ep_agora_if', True, 0x0000, "bin" ), ('k20dx_ep_kairos_if', True, 0x0000, "bin" ), ("k26f_frdmk32w042_if", False, 0x8000, "bin" ), @@ -100,6 +103,7 @@ ('lpc11u35_if', False, 0x0000, "bin" ), ('lpc4322_if', False, 0x0000, "bin" ), ('lpc55s69_if', False, 0x10000, "bin" ), + ('lpc55s69_mculink_if', False, 0x10000, "bin" ), ('max32620_if', False, 0x0000, "bin" ), ('max32625_if', False, 0x0000, "bin" ), ('nrf52820_if', False, 0x0000, "bin" ), diff --git a/tools/progen_compile.py b/tools/progen_compile.py index 44ad7005e..ce625eb33 100755 --- a/tools/progen_compile.py +++ b/tools/progen_compile.py @@ -90,7 +90,10 @@ def get_core_count(): # armcc does not support Cortex-M33 and lpc55s69 is not ported to armclang if 'armc' in toolchain: - project_list = filter(lambda p: not p.startswith("lpc55"), project_list) + project_list = list(filter(lambda p: not p.startswith("lpc55"), project_list)) +# musca projects are too large to fit when compiled with gcc. LTO should fix that but it does not work (yet) +if 'gcc' in toolchain and args.release: + project_list = list(filter(lambda p: "musca" not in p, project_list)) logging_level = logging.DEBUG if args.verbosity >= 2 else (logging.INFO if args.verbosity >= 1 else logging.WARNING) logging.basicConfig(format="%(asctime)s %(name)020s %(levelname)s\t%(message)s", level=logging_level) @@ -173,7 +176,7 @@ def get_core_count(): except yaml.YAMLError as ex: print("Found yaml parse error", ex) - release_dir = args.release_folder + "_%04i" % release_version + release_dir = args.release_folder + "_%04i" % release_version if os.path.exists(release_dir): logger.info("Deleting: %s" % release_dir) shutil.rmtree(release_dir, ignore_errors=True) From d2bb981bf76f94708848ad460e0a12d466ce9e2d Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 3 Jan 2022 00:38:21 -0600 Subject: [PATCH 579/617] build: git description should always include commit Remove '0' for commits with tags --- tools/pre_build_script.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tools/pre_build_script.py b/tools/pre_build_script.py index 5e19c3977..e953b39db 100755 --- a/tools/pre_build_script.py +++ b/tools/pre_build_script.py @@ -21,6 +21,7 @@ import sys import os +import re import argparse from subprocess import check_output, CalledProcessError @@ -63,8 +64,9 @@ def generate_version_file(version_git_dir): # Get the git description. print("#> Getting git description") try: - git_description = check_output("git describe HEAD --always --tags", shell=True) + git_description = check_output("git describe HEAD --always --tags --long", shell=True) git_description = git_description.decode().strip() + git_description = re.sub(r'-0-g([0-9a-f]+)$', r'-g\1', git_description) except: print("#> ERROR: Failed to get git description, do you have git.exe in your PATH environment variable?") return 1 From fd74e5248cf00efdad622e9d2c1f6a5ef26a90a8 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 3 Jan 2022 15:05:53 -0600 Subject: [PATCH 580/617] max32630fthr: fix typo in .htm file name --- source/board/max32630fthr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/board/max32630fthr.c b/source/board/max32630fthr.c index 3407f43a3..0f0bcee64 100644 --- a/source/board/max32630fthr.c +++ b/source/board/max32630fthr.c @@ -28,7 +28,7 @@ const board_info_t g_board_info = { .family_id = kMaxim_MAX3262X_FamilyID, .flags = kEnablePageErase, .target_cfg = &target_device, - .daplink_url_name = "MAX32620HTM", + .daplink_url_name = "MAX32630HTM", .daplink_target_url = "http://www.maximintegrated.com/max32630fthr", .board_vendor = "Maxim Integrated", .board_name = "MAX32630FTHR", From 8dff8e01027fdb23c49734099a61ee1077af0797 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 3 Jan 2022 15:28:50 -0600 Subject: [PATCH 581/617] usb-hid: move usb-hid to HIC modules --- projects.yaml | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/projects.yaml b/projects.yaml index 257806378..78fd532fd 100644 --- a/projects.yaml +++ b/projects.yaml @@ -25,7 +25,6 @@ module: if: &module_if - *module_tools - records/usb/usb-core.yaml - - records/usb/usb-hid.yaml - records/usb/usb-msc.yaml - records/usb/usb-cdc.yaml - records/usb/usb-webusb.yaml @@ -43,48 +42,61 @@ module: - records/rtos/rtos-cm3.yaml - records/hic_hal/k20dx.yaml - records/usb/usb-bulk.yaml + - records/usb/usb-hid.yaml hic_k26f: &module_hic_k26f - records/rtos/rtos-cm4.yaml - records/hic_hal/k26f.yaml - records/usb/usb-bulk.yaml + - records/usb/usb-hid.yaml hic_kl26z: &module_hic_kl26z - records/rtos/rtos-cm0.yaml - records/hic_hal/kl26z.yaml - records/usb/usb-bulk.yaml + - records/usb/usb-hid.yaml hic_kl27z: &module_hic_kl27z - records/rtos/rtos-cm0.yaml - records/hic_hal/kl27z.yaml - records/usb/usb-bulk.yaml + - records/usb/usb-hid.yaml hic_lpc11u35: &module_hic_lpc11u35 - records/rtos/rtos-cm0.yaml - records/hic_hal/lpc11u35.yaml + - records/usb/usb-hid.yaml hic_lpc4322: &module_hic_lpc4322 - records/rtos/rtos-cm3.yaml - records/hic_hal/lpc4322.yaml - records/usb/usb-bulk.yaml + - records/usb/usb-hid.yaml hic_lpc55s69: &module_hic_lpc55s69 - records/rtos/rtos-cm33.yaml - records/hic_hal/lpc55s69.yaml - records/usb/usb-bulk.yaml + - records/usb/usb-hid.yaml hic_m48ssidae: &module_hic_m48ssidae - records/rtos/rtos-cm4.yaml - records/hic_hal/m48ssidae.yaml + - records/usb/usb-hid.yaml hic_max32620: &module_hic_max32620 - records/rtos/rtos-cm4.yaml - records/hic_hal/max32620.yaml + - records/usb/usb-hid.yaml hic_max32625: &module_hic_max32625 - records/rtos/rtos-cm4.yaml - records/hic_hal/max32625.yaml + - records/usb/usb-hid.yaml hic_nrf52820: &module_hic_nrf52820 - records/rtos/rtos-cm4.yaml - records/hic_hal/nrf52820.yaml - records/usb/usb-bulk.yaml + - records/usb/usb-hid.yaml hic_sam3u2c: &module_hic_sam3u2c - records/rtos/rtos-cm3.yaml - records/hic_hal/sam3u2c.yaml + - records/usb/usb-hid.yaml hic_stm32f103xb: &module_hic_stm32f103xb - records/rtos/rtos-cm3.yaml - records/hic_hal/stm32f103xb.yaml + - records/usb/usb-hid.yaml projects: # HIC bootloaders and all target interfaces From a7ea9360a725b2d2c7878749621ceee6c67dcc53 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Fri, 10 Dec 2021 18:17:49 +0000 Subject: [PATCH 582/617] Remove BOARD_EXTRA_BUFFER vestiges. --- records/board/microbitv2.yaml | 1 - records/board/microbitv2_nrf52820.yaml | 1 - source/daplink/drag-n-drop/vfs_user.c | 5 ----- 3 files changed, 7 deletions(-) diff --git a/records/board/microbitv2.yaml b/records/board/microbitv2.yaml index 03faed711..7473e6b0c 100644 --- a/records/board/microbitv2.yaml +++ b/records/board/microbitv2.yaml @@ -8,7 +8,6 @@ common: - DELAY_FAST_CYCLES=2U # Fast delay needed to reach 8MHz SWD clock speed - DAP_DEFAULT_SWJ_CLOCK=8000000 - BOARD_USB_BMAXPOWER=0x96 - - BOARD_EXTRA_BUFFER=100 includes: - source/board/microbitv2/ - source/board/microbitv2/kl27z/ diff --git a/records/board/microbitv2_nrf52820.yaml b/records/board/microbitv2_nrf52820.yaml index 5aede83c5..7e1b688ce 100644 --- a/records/board/microbitv2_nrf52820.yaml +++ b/records/board/microbitv2_nrf52820.yaml @@ -6,7 +6,6 @@ common: - USB_PROD_STR="BBC micro:bit CMSIS-DAP" # - DELAY_FAST_CYCLES=2U # Fast delay needed to reach 8MHz SWD clock speed # - DAP_DEFAULT_SWJ_CLOCK=8000000 - - BOARD_EXTRA_BUFFER=100 - CDC_ACM_DEFAULT_BAUDRATE=115200 includes: - source/board/microbitv2/ diff --git a/source/daplink/drag-n-drop/vfs_user.c b/source/daplink/drag-n-drop/vfs_user.c index 881ec6d34..701ba8297 100644 --- a/source/daplink/drag-n-drop/vfs_user.c +++ b/source/daplink/drag-n-drop/vfs_user.c @@ -45,11 +45,6 @@ //! device. This is to accomodate for hex file programming. #define VFS_DISK_SIZE (MB(64)) -// Additional buffer space to display more than 512 bytes in DETAILS.TXT -#if !defined(BOARD_EXTRA_BUFFER) -#define BOARD_EXTRA_BUFFER 0 -#endif - //! @brief Constants for magic action or config files. //! //! The "magic files" are files with a special name that if created on the USB MSC volume, will From 1776d33335921e7752b9a92f4269e56d16de831a Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Fri, 10 Dec 2021 18:25:03 +0000 Subject: [PATCH 583/617] microbit: Set CDC ACM default baud rate for micro:bit v1.x and v2.0. --- records/board/microbit.yaml | 1 + records/board/microbitv2.yaml | 1 + 2 files changed, 2 insertions(+) diff --git a/records/board/microbit.yaml b/records/board/microbit.yaml index d63af54d5..8a0eb29af 100644 --- a/records/board/microbit.yaml +++ b/records/board/microbit.yaml @@ -4,6 +4,7 @@ common: - CDC_LED_DEF=GPIO_LED_ON - MSC_LED_DEF=GPIO_LED_ON - USB_PROD_STR="BBC micro:bit CMSIS-DAP" + - CDC_ACM_DEFAULT_BAUDRATE=115200 sources: board: - source/board/microbit.c diff --git a/records/board/microbitv2.yaml b/records/board/microbitv2.yaml index 7473e6b0c..bd22e9fe4 100644 --- a/records/board/microbitv2.yaml +++ b/records/board/microbitv2.yaml @@ -8,6 +8,7 @@ common: - DELAY_FAST_CYCLES=2U # Fast delay needed to reach 8MHz SWD clock speed - DAP_DEFAULT_SWJ_CLOCK=8000000 - BOARD_USB_BMAXPOWER=0x96 + - CDC_ACM_DEFAULT_BAUDRATE=115200 includes: - source/board/microbitv2/ - source/board/microbitv2/kl27z/ From 8f31e4fbc56583a30b403ed2bdb102cbaa040333 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 3 Jan 2022 15:32:32 -0600 Subject: [PATCH 584/617] lpc11u35_if: remove hid from lpc11u35_if (fixes #915) --- projects.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/projects.yaml b/projects.yaml index 78fd532fd..9f9d71258 100644 --- a/projects.yaml +++ b/projects.yaml @@ -62,6 +62,10 @@ module: - records/rtos/rtos-cm0.yaml - records/hic_hal/lpc11u35.yaml - records/usb/usb-hid.yaml + hic_lpc11u35_bulk: &module_hic_lpc11u35_bulk + - records/rtos/rtos-cm0.yaml + - records/hic_hal/lpc11u35.yaml + - records/usb/usb-bulk.yaml hic_lpc4322: &module_hic_lpc4322 - records/rtos/rtos-cm3.yaml - records/hic_hal/lpc4322.yaml @@ -134,9 +138,8 @@ projects: - records/family/all_family.yaml lpc11u35_if: - *module_if - - *module_hic_lpc11u35 + - *module_hic_lpc11u35_bulk - records/family/all_family.yaml - - records/usb/usb-bulk.yaml lpc4322_bl: - *module_bl - records/hic_hal/lpc4322.yaml From 8aaa1412ebb840f2cb7ed8adf8f555583aba15d0 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Tue, 4 Jan 2022 07:09:54 -0600 Subject: [PATCH 585/617] lpc11u35_if: keep DAP_PACKET_SIZE at 64 bytes even when HID is disabled Suggested by @elfmimi --- source/hic_hal/nxp/lpc11u35/DAP_config.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/source/hic_hal/nxp/lpc11u35/DAP_config.h b/source/hic_hal/nxp/lpc11u35/DAP_config.h index 3b9d6ef49..d28472557 100644 --- a/source/hic_hal/nxp/lpc11u35/DAP_config.h +++ b/source/hic_hal/nxp/lpc11u35/DAP_config.h @@ -94,11 +94,7 @@ This information includes: /// This configuration settings is used to optimize the communication performance with the /// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB, /// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB. -#ifndef HID_ENDPOINT //HID end points currently set limits to 64 -#define DAP_PACKET_SIZE 512 ///< Specifies Packet Size in bytes. -#else #define DAP_PACKET_SIZE 64 ///< Specifies Packet Size in bytes. -#endif /// Maximum Package Buffers for Command and Response data. /// This configuration settings is used to optimize the communication performance with the From 130efe7bc8a358a54a670922a30f482c1d06198c Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Thu, 6 Jan 2022 12:21:51 -0600 Subject: [PATCH 586/617] Remove k20dx_mimxrt1050_evk_hyper_if project (#923) --- projects.yaml | 4 - records/board/mimxrt1050_evk_qspi.yaml | 10 - .../mimxrt1050_spi_flash/flash_blob.c | 555 ------------------ .../freescale/mimxrt1050_spi_flash/target.c | 40 -- test/info.py | 4 +- 5 files changed, 1 insertion(+), 612 deletions(-) delete mode 100644 records/board/mimxrt1050_evk_qspi.yaml delete mode 100644 source/family/freescale/mimxrt1050_spi_flash/flash_blob.c delete mode 100644 source/family/freescale/mimxrt1050_spi_flash/target.c diff --git a/projects.yaml b/projects.yaml index 9f9d71258..768ef5bee 100644 --- a/projects.yaml +++ b/projects.yaml @@ -306,10 +306,6 @@ projects: - *module_if - *module_hic_k20dx - records/board/mimxrt1050_evk_hyper.yaml - k20dx_mimxrt1050_evk_qspi_if: - - *module_if - - *module_hic_k20dx - - records/board/mimxrt1050_evk_qspi.yaml k20dx_rapid_iot_if: - *module_if - *module_hic_k20dx diff --git a/records/board/mimxrt1050_evk_qspi.yaml b/records/board/mimxrt1050_evk_qspi.yaml deleted file mode 100644 index 7fb84546c..000000000 --- a/records/board/mimxrt1050_evk_qspi.yaml +++ /dev/null @@ -1,10 +0,0 @@ -common: - macros: - - DAPLINK_MIMXRT_TARGET - - SOFT_RESET=VECTRESET - sources: - board: - - source/board/mimxrt1050_evk.c - family: - - source/family/freescale/mimxrt1050_spi_flash/target.c - - source/family/freescale/target_reset_mimxrt.c diff --git a/source/family/freescale/mimxrt1050_spi_flash/flash_blob.c b/source/family/freescale/mimxrt1050_spi_flash/flash_blob.c deleted file mode 100644 index 1a17056c9..000000000 --- a/source/family/freescale/mimxrt1050_spi_flash/flash_blob.c +++ /dev/null @@ -1,555 +0,0 @@ -/* Flash algorithm for MIMXRT105x 8mB QuadSPI NOR Flash - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2021 Arm Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -// Generated from 'MIMXRT105x_QuadSPI_4KB_SEC.FLM' (MIMXRT105x 8mB QuadSPI NOR Flash) -// Originating from 'NXP.MIMXRT1052_DFP.13.1.1.pack' -// digest = 32f76ad6e166887076f25302dd9d0bacc352fccaca19205c623231759a7fe084, file size = 1510724 -// algo version = 0x101, algo size = 15484 (0x3c7c) -static const uint32_t MIMXRT105x_QuadSPI_4KB_SEC_flash_prog_blob[] = { - 0xe7fdbe00, - 0x4605b570, 0x4616460c, 0xcc0fe002, 0x3e10c50f, 0xd2fa2e10, 0xd3022e08, 0xc503cc03, 0x2e043e08, - 0xcc01d307, 0x1f36c501, 0x7821e003, 0x1c647029, 0x1e761c6d, 0xbd70d2f9, 0x4770ba40, 0x4770ba40, - 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770ba40, 0x4770bac0, 0x4770bac0, 0x4770bac0, - 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x4770bac0, 0x482fb51c, 0x482f9000, 0x08498901, 0x81010049, - 0x890a492d, 0x00520852, 0x8802810a, 0x07522304, 0xda022a00, 0x439a8802, 0x88088002, 0xd5020740, - 0x43988808, 0x48268008, 0x60414924, 0x60814925, 0x22806801, 0x22204391, 0x60014311, 0x466a4922, - 0x20004449, 0xfaacf002, 0xd1052800, 0x4449491e, 0xfdeef000, 0xd0002800, 0xbd1c2001, 0x47702000, - 0xb5104919, 0x20004449, 0xff45f000, 0xd0002800, 0xbd102001, 0x07492105, 0x49131842, 0x2301b510, - 0x444902db, 0xf0022000, 0x2800fae1, 0x2001d000, 0x2105bd10, 0x07494613, 0x490b1842, 0x4449b510, - 0xf0002000, 0x2800fec9, 0x2001d000, 0x0000bd10, 0xc0000006, 0x400b8000, 0x400d0000, 0xd928c520, - 0x400bc000, 0x0000ffff, 0x00000010, 0x49a4b5f8, 0x444948a2, 0x4ea46008, 0x603048a2, 0x28006830, - 0x6b30dafc, 0x03092101, 0x63304388, 0x28006b30, 0x489edafc, 0x499e6802, 0x400a2303, 0x18d202db, - 0x431a4b9c, 0x20036002, 0x61300300, 0x28006930, 0x6930dafc, 0x043f2701, 0x613043b8, 0x3a404a93, - 0x40086b10, 0x02092123, 0x49931840, 0x63104308, 0x20014c92, 0x49936120, 0x44494891, 0x25016008, - 0xe0009000, 0x46291c6d, 0xf0039800, 0x498efa9f, 0xd8f74288, 0x498d6960, 0x1e694008, 0x0b490749, - 0x02294308, 0x390139ff, 0x0d890589, 0x61604308, 0x09c06a60, 0x1cc001c0, 0x69a06260, 0x04892103, - 0x61a04308, 0x498269a0, 0x21054008, 0x18400689, 0x69e061a0, 0x4008497f, 0x07492103, 0x497e1840, - 0x61e04308, 0x210369e0, 0x43080409, 0x6a6061e0, 0x02c921e7, 0x21214388, 0x184002c9, 0x68306260, - 0x603043b8, 0x43b86b30, 0x69306330, 0x613043b8, 0x486abdf8, 0x68013080, 0x02922203, 0x60014311, - 0x48664770, 0x68013080, 0x02922203, 0x60014391, 0xb5f74770, 0x4969460c, 0x4615b08a, 0x44792214, - 0xf7ff4668, 0x4965febd, 0x44792214, 0xa8053108, 0xfeb6f7ff, 0xd0012d00, 0xd1362d01, 0x3e404e53, - 0x09876b30, 0x01bf4855, 0x200769c2, 0x438205c0, 0xd02c2d00, 0x2c00a805, 0x2c09d027, 0x2401d900, - 0x5c430061, 0x78401808, 0x05c02107, 0x069b05c9, 0x0e9b1840, 0x4d520184, 0x09a4433b, 0x43146828, - 0x43382702, 0x980a6028, 0xffbbf7ff, 0x42986b30, 0x6333d000, 0x69c14841, 0xd00042a1, 0x980a61c4, - 0xffa7f7ff, 0x43b86828, 0xb00d6028, 0x4668bdf0, 0xb570e7d1, 0x4a3b4616, 0x444a2000, 0x46046812, - 0xd0082900, 0x29014d35, 0x2902d007, 0x2404d00a, 0x46206030, 0x4610bd70, 0x6968e7fa, 0x0f810580, - 0xe00d4610, 0x482969e8, 0x6b003840, 0x0e890681, 0xf0034834, 0x2112f9db, 0x69e94348, 0x0f490189, - 0xf0031c49, 0xe7e3f9d3, 0x20044603, 0xd1042b00, 0xd0022900, 0x6008482c, 0x47702000, 0x44484821, - 0x47706800, 0x481db510, 0x05806940, 0x481d0f81, 0x44481c49, 0xf0036800, 0xbd10f9b9, 0x4604b5f8, - 0x460d4818, 0x68004448, 0xf0034920, 0x4606f9af, 0x2103e009, 0xf0034630, 0x9000f9a9, 0xbf00e000, - 0x90001e40, 0x2200d2fb, 0x46281e64, 0x415043d2, 0x43e14605, 0x430143e8, 0xbdf8d1eb, 0x016e3600, - 0x00000004, 0x00012058, 0x400d8000, 0x400d8100, 0xc0c0c0c0, 0x18131818, 0x0f1a2323, 0x400fc000, - 0x1f78a400, 0x0000000c, 0x08954400, 0xfff8e0ff, 0xe3ffffcf, 0x9c7fff80, 0x03800001, 0x000036ca, - 0x402a8000, 0x1c9c3800, 0x09e4f580, 0x000f4240, 0x4d5ab5f8, 0x462e485a, 0x460c9000, 0x46084637, - 0xfa8ff002, 0xd0042800, 0x6ee06e26, 0x6e679000, 0x6d206ea5, 0x6d602800, 0x2800d027, 0x4951d004, - 0x63c82006, 0x62c64850, 0x28006d20, 0x494dd006, 0x31402001, 0x484c62c8, 0x61c63040, 0x23114949, - 0x630b3140, 0x30404848, 0x22016207, 0x6245634a, 0x6285638a, 0x62c563ca, 0x31804942, 0x6305600a, - 0x5d002045, 0xd0032808, 0x2800e00f, 0xe024d1d7, 0x2001493c, 0x62083140, 0x32404a3b, 0x61c86115, - 0x618860d5, 0x61486095, 0x7b206055, 0xd0012803, 0xd1062801, 0x30404833, 0x49336283, 0x31409800, - 0x46206188, 0xfa44f002, 0xd0062800, 0x2101482d, 0x62413040, 0x3040482c, 0x6da06147, 0x6de02800, - 0x2800d02a, 0x4927d005, 0x31402006, 0x48266008, 0x6da06306, 0xd0052800, 0x21044822, 0x62413040, - 0x63c64821, 0x2111481f, 0x62413040, 0x3140491e, 0x2201614f, 0x610d6202, 0x60cd61c2, 0x608d6182, - 0x604d6142, 0x2a037b22, 0x2a01d001, 0x2214d103, 0x98006102, 0xbdf86008, 0xd1d42800, 0x2104bdf8, - 0xd00f2800, 0x29037b01, 0x6c01d10b, 0x06493060, 0xda012900, 0xe003210f, 0x29007e41, 0x211ed101, - 0x21007601, 0x47704608, 0x62884908, 0x47702000, 0x6a894906, 0x20006001, 0x00004770, 0x000010f1, - 0x000130f1, 0x401f8180, 0x401f8380, 0x400f8000, 0x49fcb5f0, 0x4479b085, 0x466dc91e, 0x4efac51e, - 0x4df94ff9, 0x4cf84669, 0x37803640, 0x000335c0, 0xf9aef003, 0x220d0609, 0x8381582b, 0x00918b89, - 0xfb42f000, 0x06496821, 0x43480e49, 0xf000e048, 0x6a37fb3b, 0x69314605, 0xf982f003, 0x2300463a, - 0xffacf002, 0x07c96b21, 0x2116d001, 0x2114e000, 0x1828434d, 0xbdf0b005, 0xfb26f000, 0xe0676921, - 0xe0002116, 0x43482114, 0xf000e7f4, 0x4604fb1d, 0x06456b30, 0x693f4638, 0x68010e6d, 0xf0034620, - 0x463af95f, 0xf0022300, 0x436cff89, 0x18206b31, 0x04d22203, 0xd0114011, 0x04d22201, 0xd1004291, - 0x49d20840, 0x4ad26b09, 0x22014011, 0x1a8903d2, 0x0212d006, 0xd1cd4291, 0xe7cb0880, 0xe7f00880, - 0xe7c70840, 0xfaf0f000, 0x6a384604, 0x0646682d, 0x6b390e76, 0xf0034620, 0x462af933, 0xf0022300, - 0x4374ff5d, 0x18206a39, 0x04d22203, 0xd0104011, 0x04d22201, 0xd1004291, 0x49bc0840, 0x22016b09, - 0x07890f89, 0x18890792, 0x0052d0d6, 0xd1a142d1, 0x0880e7d6, 0x6a28e7f1, 0x6a28e001, 0x07800880, - 0x58080f00, 0x48b3e796, 0xf000e794, 0x6a21fabd, 0xd0970789, 0x2000e794, 0xb510e78c, 0x20014604, - 0xff56f7ff, 0x394049a9, 0xd0092c00, 0xd0092c01, 0xd00e2c02, 0xd00f2c03, 0x21122000, 0xbd104348, - 0xe0016809, 0x0a096809, 0x0e890689, 0xffeef002, 0x6809e7f3, 0xe7f70c09, 0x0e096809, 0xb510e7f4, - 0x69604c9d, 0x69a00180, 0x2103d512, 0x40080309, 0x2101d005, 0x42880309, 0x2000d005, 0x2002e005, - 0xff26f7ff, 0xf000e001, 0x6961fa7f, 0xe00f0ec9, 0x04892103, 0xd0134008, 0x04892101, 0xd0131a40, - 0xd0121a40, 0xd1094288, 0xf7ff2000, 0x6921ff11, 0x0f490749, 0xf0021c49, 0xbd10ffb9, 0xbd102000, - 0xf7ff2001, 0xbd10ff05, 0xf7ff2002, 0xbd10ffa6, 0x2800b510, 0xf002d001, 0x2101ff52, 0x0789487b, - 0x497e6181, 0x03d26b0a, 0x2201d5fc, 0x61420412, 0x04096901, 0x6182d5fc, 0x2001bd10, 0x07804973, - 0x47706148, 0x49752210, 0xd0012800, 0x4770638a, 0x4770634a, 0x6b014871, 0x43112201, 0x47706301, - 0x6b01486e, 0x00490849, 0x47706301, 0x4604b510, 0xf7ff2002, 0x4965fecd, 0x2c003980, 0x2c01d009, - 0x2c02d009, 0x2c03d00e, 0x2000d00f, 0x43482112, 0x6b09bd10, 0x6b09e001, 0x06890a09, 0xf0020e89, - 0xe7f3ff65, 0x0c096b09, 0x6b09e7f7, 0xe7f40e09, 0x4c59b510, 0xf0030003, 0x0d17f86b, 0x362a120d, - 0x403e3c39, 0x4a464442, 0x52504e4c, 0x5c5a5854, 0x0064605e, 0xff63f7ff, 0x0a896961, 0x6960e011, - 0xd50a0640, 0x06006960, 0x2001d503, 0xffbef7ff, 0x2002e005, 0xff31f7ff, 0xf7ffe001, 0x6961ff50, - 0x07490c09, 0x1c490f49, 0xff30f002, 0xf7ffbd10, 0x6961ff46, 0x0f4904c9, 0xf0021c49, 0x6961ff27, - 0x0f890589, 0xf000e7ef, 0xbd10f9cf, 0x03c02001, 0x2000bd10, 0x2002e022, 0x2000e020, 0x2001e004, - 0x2002e002, 0x2003e000, 0xff90f7ff, 0x2008bd10, 0x2001e014, 0x2000e012, 0x2001e004, 0x2002e002, - 0x2003e000, 0xfef9f7ff, 0x2005bd10, 0x2006e006, 0x2007e004, 0x2003e002, 0x2004e000, 0xfe48f7ff, - 0x2000bd10, 0x7800bd10, 0x06402101, 0x03490e40, 0x481d1841, 0x68016001, 0xdafc2900, 0x20014770, - 0x03004919, 0x47706008, 0x21017800, 0x0fc007c0, 0x18410349, 0x63014814, 0x29006b01, 0x4770dafc, - 0x49112001, 0x63080300, 0x78004770, 0x078021c1, 0x01890f80, 0x480c1841, 0x69016101, 0xdafc2900, - 0x49094770, 0x61082000, 0x78004770, 0x078021c1, 0x01890f80, 0x48041841, 0x6a016201, 0xdafc2900, - 0x00004770, 0x000033ba, 0x400d8000, 0x400d8140, 0x00808000, 0x017d7840, 0x400fc000, 0x400d8240, - 0x200049ae, 0xe7eb6208, 0x6841b530, 0x008b2200, 0x089b49aa, 0x600b3180, 0x009b6883, 0x610b089b, - 0x23017801, 0x035b0649, 0x78400e49, 0x019d18c9, 0xd01c2802, 0x006c4ba2, 0xd0162804, 0xd0122808, - 0xd00e2810, 0x4b9f4321, 0x4c9d6b18, 0x402043e4, 0x63184310, 0x30404899, 0x6b016301, 0xdafc2900, - 0x461abd30, 0x4329e7ef, 0x4321e7fb, 0x4329e7f9, 0x2001e7e9, 0x03004991, 0x63083140, 0xb570e7b0, - 0x4b8e6841, 0x22000089, 0x33800889, 0x68816319, 0x00894c8c, 0x3c800889, 0x78016021, 0x06492401, - 0x0e490364, 0x19097840, 0x280201a5, 0x2403d01a, 0x006e07a4, 0xd0132804, 0xd00f2808, 0xd00b2810, - 0x48804331, 0x00a46b04, 0x431408a4, 0x62196304, 0x28006a18, 0xbd70dafc, 0xe7f24622, 0xe7fb4329, - 0xe7f94331, 0xe7ec4329, 0x49742001, 0x31800300, 0xe7756208, 0x78c27901, 0x07920789, 0x0f920f09, - 0x78024311, 0xd0022a00, 0x03522201, 0x78424311, 0xd0022a00, 0x05122201, 0x78804311, 0xd0022800, - 0x05402001, 0x48674301, 0x62013880, 0x29006a01, 0xe755dafc, 0x49632001, 0x39800300, 0xe74f6208, - 0xb5104b60, 0x681a3b40, 0x24bf00c0, 0x43a24084, 0x40842480, 0x601c4314, 0x0e890689, 0x43114081, - 0xbd106019, 0x39404957, 0x00c3680a, 0x40982080, 0x600a4302, 0x4b53e734, 0x3b80b510, 0x00c06b1a, - 0x408424bf, 0x248043a2, 0x43144084, 0x0689631c, 0x40810e89, 0x63194311, 0x494abd10, 0x6b0a3980, - 0x208000c3, 0x43024098, 0xe719630a, 0x4846b508, 0x22036801, 0x60014311, 0x68014844, 0x43112202, - 0x20006001, 0x48429000, 0x9900bf00, 0x91001c49, 0xd3f94281, 0x3940493b, 0x221f6a08, 0x43900212, - 0x43104a3c, 0x20016208, 0xb508bd08, 0x68014836, 0x43112203, 0x48386001, 0x22026801, 0x60014311, - 0x90002000, 0xbf004832, 0x1c499900, 0x42819100, 0x492cd3f9, 0x6a083940, 0x0212221f, 0x4a2d4390, - 0x62084310, 0xbd082001, 0x2200b508, 0x92004668, 0xfebbf7ff, 0x6b014829, 0x08490049, 0x6b016301, - 0x43990483, 0x60026301, 0x22636b01, 0x43110392, 0x20016301, 0xb508bd08, 0x46682200, 0xf7ff9200, - 0x481ffeb4, 0x00496b01, 0x63010849, 0x04436b01, 0x63014399, 0x6b016002, 0x03922263, 0x63014311, - 0xbd082001, 0x2000490d, 0x48146108, 0x04826b01, 0x63014311, 0x4909e6a4, 0x62082000, 0x6b014810, - 0x43110442, 0xe69b6301, 0x6b00480e, 0xd50106c0, 0xe695480d, 0x4448480d, 0xe6916800, 0x400d8000, - 0x00808000, 0x400d8140, 0x400fc080, 0x402e0140, 0x00061a80, 0x00001701, 0x402e0340, 0x400d9000, - 0x400da000, 0x400d8240, 0x016e3600, 0x00000004, 0x460cb570, 0xf0024606, 0x0005fa35, 0x4622d10b, - 0x32802301, 0x46302100, 0xf8e6f002, 0x28017c60, 0x2000d101, 0x46287420, 0xb570bd70, 0x4605b08a, - 0x466e2000, 0x200f7030, 0x90022401, 0x74329403, 0x32ff460a, 0x32719301, 0x46214623, 0xf0024628, - 0x4669f8cb, 0x94024628, 0xffd5f001, 0xbd70b00a, 0x2004b5ff, 0x460db083, 0xd0292900, 0x36ff462e, - 0x7b7036c1, 0xd0062800, 0x9a059b06, 0xf7ff9803, 0x2800ffd4, 0x7b30d11c, 0x3480462c, 0xd10a2802, - 0x30304620, 0x466bc887, 0x4620c307, 0xc80f3040, 0xc40f3430, 0x46293c40, 0x9a059b06, 0xf0029803, - 0x7b31f8cb, 0xd1032902, 0xcd0e466d, 0xc48e3430, 0xbdf0b007, 0xb089b5ff, 0x4616461d, 0x9809460c, - 0xffc6f7ff, 0xd1142800, 0x70084669, 0x200e2701, 0x90029703, 0x4622740e, 0x326132ff, 0x4639463b, - 0x98099501, 0xf878f002, 0x97024669, 0xf0019809, 0xb00dff82, 0xb5ffbdf0, 0xb0832004, 0x4696469c, - 0xd0d52900, 0x35ff460d, 0x7b2835c1, 0x3480460c, 0xd10b2802, 0x30104620, 0x466ac889, 0xc28969e6, - 0x30204620, 0x3410c88d, 0x3c20c48d, 0x46724663, 0xf0029803, 0x7b29f8ae, 0xd1b92902, 0xcd0e466d, - 0xc44e3410, 0xb5f7e7b4, 0x4616b082, 0xd051000d, 0xd84f2e01, 0x34ff462c, 0x7a2034c1, 0xd0002800, - 0x28002001, 0x6c28d046, 0x0fc70640, 0xf0029802, 0x2e00fa62, 0x7a20d02b, 0xd0092800, 0x5d412046, - 0x9802463a, 0xfa15f7ff, 0x98024629, 0xfdaaf001, 0x28007ba0, 0x2100d003, 0xf0029802, 0x466afa5e, - 0x98022102, 0xfa55f7ff, 0xd0022f00, 0x08409800, 0xaa019000, 0x98022100, 0xfa4bf7ff, 0x98019900, - 0xfc44f002, 0x1c40210a, 0x08804348, 0x7a21e010, 0xd0072900, 0x9802463a, 0xf9ebf7ff, 0x98024629, - 0xfd80f001, 0x28007ba0, 0x2101d0d9, 0xbf00e7d4, 0xd2fc1e40, 0xbdf0b005, 0xb089b5ff, 0x460d4617, - 0xf0014608, 0x4606fd47, 0x46292200, 0xf7ff9809, 0x463bff9a, 0x46294632, 0xf7ff9809, 0x0004ff19, - 0x2002d13f, 0x70084669, 0x24012009, 0x94039002, 0x5d412047, 0x30ff4628, 0x29003081, 0x7c01d006, - 0xd0032900, 0x91027c41, 0x91037c01, 0x97014669, 0x990c740e, 0x6c009105, 0x98029006, 0x01002101, - 0x32801942, 0x98099b03, 0xffb6f001, 0x94024669, 0xf0019809, 0x0004fec0, 0x463bd113, 0x46294632, - 0xf7ff9809, 0x0004ff38, 0x20ffd10b, 0x5d4030d0, 0xd0062800, 0x4632463b, 0x98094629, 0xff0af7ff, - 0x98094604, 0xf9d1f002, 0x46292201, 0xf7ff9809, 0x4620ff4a, 0xb5f3e71d, 0x2600b08b, 0x9d0c4669, - 0x2101700e, 0x210b9103, 0x46699102, 0x2047740e, 0x46375d40, 0x28004634, 0x4628d009, 0x308130ff, - 0x29007d01, 0x7d41d003, 0x7d009102, 0x22009003, 0x980b990c, 0xff27f7ff, 0x950a3550, 0x9009cd01, - 0xd01a2800, 0x22004633, 0x980b990c, 0xfea0f7ff, 0xd13e0004, 0x96019802, 0x980c0101, 0x180a9b03, - 0x32802101, 0xf001980b, 0x2001ff57, 0x46699002, 0xf001980b, 0x0004fe60, 0x9809d12b, 0x18361c7f, - 0xd3db2f04, 0xd1242c00, 0x90092000, 0x980c4606, 0x30ff9d0a, 0x900a30c1, 0x2f00cd80, 0x2200d013, - 0x990c9b09, 0xf7ff980b, 0x0004fec6, 0x980ad111, 0x28007bc0, 0x2200d007, 0x990c9b09, 0xf7ff980b, - 0x0004fe99, 0x9809d105, 0x19c01c76, 0x2e049009, 0x980bd3e2, 0xf959f002, 0x990c2201, 0xf7ff980b, - 0x4620fed2, 0xb5f7e6a5, 0x4617b08a, 0x4608460d, 0xfc70f001, 0x22004606, 0x980a4629, 0xfec3f7ff, - 0x4632463b, 0x980a4629, 0xfe42f7ff, 0xd1390004, 0x97014669, 0x20057008, 0x90022401, 0x740e9403, - 0x5d402047, 0xd0092800, 0x30ff4628, 0x7b013081, 0xd0032900, 0x91027b41, 0x90037b00, 0x21019802, - 0x19420100, 0x9b033280, 0xf001980a, 0x4669fee5, 0x980a9402, 0xfdeff001, 0xd1130004, 0x4632463b, - 0x980a4629, 0xfe67f7ff, 0xd10b0004, 0x30d020ff, 0x28005d40, 0x463bd006, 0x46294632, 0xf7ff980a, - 0x4604fe39, 0xf002980a, 0x2201f900, 0x980a4629, 0xfe79f7ff, 0xe64c4620, 0xb08ab5f7, 0x460d4617, - 0xf0014608, 0x4606fc17, 0x46292200, 0xf7ff980a, 0x463bfe6a, 0x46294632, 0xf7ff980a, 0x0004fde9, - 0x4669d139, 0x70089701, 0x24012008, 0x94039002, 0x2047740e, 0x28005d40, 0x4628d009, 0x308130ff, - 0x29007f01, 0x7f41d003, 0x7f009102, 0x98029003, 0x01002101, 0x32801942, 0x980a9b03, 0xfe8cf001, - 0x94024669, 0xf001980a, 0x0004fd96, 0x463bd113, 0x46294632, 0xf7ff980a, 0x0004fe0e, 0x20ffd10b, - 0x5d4030d0, 0xd0062800, 0x4632463b, 0x980a4629, 0xfde0f7ff, 0x980a4604, 0xf8a7f002, 0x46292201, - 0xf7ff980a, 0x4620fe20, 0xb5f0e5f3, 0x20044607, 0x461db089, 0x460e4614, 0xd00f2a00, 0x46682124, - 0xfa92f002, 0x46692003, 0x20017008, 0x95089002, 0x96019003, 0x46389407, 0xfd5df001, 0xbdf0b009, - 0xb08fb5ff, 0x460c2000, 0x900b900a, 0x900d900c, 0x25016811, 0x2905461e, 0x6851d202, 0xd3152940, - 0x6c117425, 0x0f490249, 0xf002000b, 0x0d07fb81, 0x050b0905, 0x000d0705, 0xe00b2702, 0xe0092704, - 0xe0072701, 0xe0052703, 0xe03f7420, 0x05098831, 0xd03b0f0f, 0x90002000, 0x90024669, 0x20037508, - 0x95097108, 0x95049503, 0x2f019108, 0x2f02d007, 0x2f03d003, 0x2f04d02d, 0x48fdd104, 0x48fce001, - 0x900a3830, 0xaa0a2301, 0x980f4619, 0xfe04f001, 0x980fa901, 0xfd0ff001, 0xd1182800, 0x01006830, - 0xd0050f00, 0x040088b0, 0xd0010e01, 0x90000e00, 0x46202100, 0x74213080, 0xd00d2f01, 0x2f022202, - 0x2f03d013, 0x2f04d029, 0x7421d01f, 0xb0132000, 0x48e7bdf0, 0xe7d4300a, 0x064a9900, 0x4ae5d4f6, - 0x20c36402, 0x20404001, 0x9900e01e, 0xd4ed078b, 0x43114be1, 0x02086403, 0x74259000, 0x20047525, - 0x98007560, 0x746561a0, 0x9900e7e0, 0xd4dd078b, 0x33304bd8, 0x64034311, 0x9900e007, 0xd4d5060a, - 0x323d4ad5, 0x20806402, 0x91004301, 0xb5f7e7e5, 0x02402001, 0x2700b098, 0x46689001, 0x24017407, - 0x9702460d, 0x29009403, 0x48ccd072, 0xc84d4478, 0xc14da90d, 0x466a2003, 0xa8097010, 0x20109007, - 0x462a9008, 0x21013280, 0x98189b03, 0xfd94f001, 0x94024669, 0xf0019818, 0x2800fc9e, 0x9809d158, - 0xd1081c40, 0x1c40980a, 0x980bd105, 0xd1021c40, 0x1c40980c, 0x2210d007, 0xa80da909, 0xf969f002, - 0xd1452800, 0x2300e034, 0x4629461a, 0xf7ff9818, 0x2800fcaf, 0x2009d17b, 0x20029002, 0x70084669, - 0x462aa80d, 0x90052610, 0x960632ff, 0x21013211, 0x98189b03, 0xfd60f001, 0x94024669, 0xf0019818, - 0x2800fc6a, 0x2300d163, 0x4629461a, 0xf0019818, 0x2800fdb0, 0x9002d15b, 0x46692003, 0xa8097008, - 0x96089007, 0xf0019818, 0x2800fc56, 0xe7c2d14f, 0x90162032, 0x90152000, 0x21406c28, 0x64284308, - 0x5d412046, 0x22012602, 0xf7fe9818, 0xe038ff22, 0x2400e03d, 0x94129411, 0x94149413, 0x6d282101, - 0x42880609, 0x488ed901, 0x488ee000, 0x498e9011, 0x1840b2f0, 0x2301498d, 0x90124308, 0x2100aa11, - 0xf0019818, 0x2003fd19, 0x94024669, 0xa8097008, 0x20109007, 0x98189008, 0xfc1df001, 0xd0060004, - 0xd0142f00, 0x2f00981a, 0xd0106006, 0x2210e010, 0xa80da909, 0xf8edf002, 0xd00c2800, 0x2f001c76, - 0x9815d1f0, 0x1c409916, 0x42889015, 0x4c78d3c1, 0xb01b4620, 0x2701bdf0, 0xb5ffe7e4, 0xb0824608, - 0x9000305c, 0x68c8460b, 0x27013308, 0xda032800, 0x1ec0463a, 0xe0014082, 0x08c21c40, 0x24ff9802, - 0x9e026502, 0x68489201, 0x340136ff, 0x28403681, 0x6434d201, 0x8d18e00a, 0x0f020600, 0x40904638, - 0x03d22201, 0xd1004290, 0x64304620, 0x24004d61, 0x00424620, 0x7f1718d2, 0xd00d2f00, 0x40ba2201, - 0xd20142aa, 0x46844615, 0xd90542a2, 0x053f2701, 0xd20142ba, 0x46864614, 0x28041c40, 0x6475d3e9, - 0x98026534, 0x30c130ff, 0xd10142a5, 0xe0002201, 0x72422200, 0x98012201, 0x42900612, 0x3140d92d, - 0x28007e08, 0x9800d008, 0x79014460, 0x60019804, 0x44709800, 0xe0187901, 0x00404660, 0x7f4018c0, - 0x22dc2121, 0xd0022820, 0xd10528d8, 0x9804e002, 0xe0016001, 0x60029804, 0x00404670, 0x7f4018c0, - 0xd0022820, 0xd10528d8, 0x9805e002, 0xe0016001, 0x60029805, 0xb0062000, 0x4660bdf0, 0x18c00040, - 0x98047f41, 0x46706001, 0x18c00040, 0xe7ec7f41, 0xb08db5ff, 0x90052004, 0x460f980f, 0x90033008, - 0x305c980f, 0x20009009, 0x98109004, 0x02006800, 0x28010f00, 0x9803d105, 0x03006800, 0x90040fc0, - 0x2000d071, 0x99107338, 0x78094606, 0x070aab0b, 0x21460f12, 0x900055ca, 0x90062018, 0x90072000, - 0x4638aa0a, 0xf7ff990f, 0x2101ff48, 0x06096d38, 0xd9014288, 0x90062020, 0x88009810, 0x0f000400, - 0x4639d151, 0x9a0f9b10, 0xf7ff980d, 0x9005fdd9, 0xd1f52800, 0x68009803, 0xd51d0281, 0x90072002, - 0x7a009803, 0x0f4e0601, 0x0ec006c0, 0x0000e01c, 0x24010435, 0x20010401, 0x20020401, 0x00002634, - 0x8a2004ee, 0x8a1804ed, 0x00040200, 0xa604b000, 0x00004e2a, 0x00ffffff, 0xd5060240, 0x68809803, - 0x0f4e0201, 0x0ec002c0, 0x980f9000, 0x30409a06, 0x49fc1dfc, 0x900834f9, 0xd0022a20, 0x612048fa, - 0x7e00e012, 0x28004bf9, 0x9809d03b, 0x68004af8, 0xd50105c5, 0xe00348f7, 0xd5320600, 0x302248f3, - 0x61206162, 0xe0a9e001, 0x20016161, 0x463d7338, 0x358048f1, 0x48f16328, 0x980a6128, 0xb2c14af0, - 0x04009806, 0x43114301, 0x65299001, 0xb2c9990b, 0x43114301, 0x01402023, 0x63206021, 0x68009810, - 0x0f010100, 0x9910d00f, 0x060a6849, 0xd00a0e12, 0x9904b2c8, 0x90002600, 0xd0212900, 0x90000040, - 0x6123e01e, 0x9904e7d0, 0xd0192900, 0xd1170f00, 0x28209806, 0x48d5d104, 0x60281c40, 0x606848d9, - 0x980d4639, 0xfaa4f7ff, 0x28009005, 0x466ad166, 0x980d4639, 0xfddbf7ff, 0x28009005, 0x2600d1f6, - 0x28189806, 0x2002d006, 0x98049007, 0xd0202800, 0xe00320ee, 0x28009804, 0x20edd00a, 0x22406c39, - 0x64394311, 0x43019901, 0x430148c7, 0xe0376029, 0x68009803, 0xd5030281, 0x89009803, 0xe0030400, - 0xd5040240, 0x68809803, 0x90020e00, 0x2003e01f, 0x9808e019, 0x28007e00, 0x9809d00a, 0x06816800, - 0x06c0d40a, 0x206cd513, 0x20009002, 0xe00e9007, 0x68009803, 0xd5010281, 0xe7e620ec, 0xd5010240, - 0xe7e2206c, 0x90022013, 0x46062000, 0x99029000, 0x43089801, 0x06099907, 0x49a94308, 0x60284308, - 0x463a9910, 0x32ff7809, 0x32c10609, 0x0f0b2000, 0x2b009201, 0x0f09d003, 0xd0042901, 0x9800e06b, - 0x90001980, 0x990fe049, 0x29406849, 0x9903d3f7, 0x058a6b89, 0x0309d5f3, 0x22050f09, 0xd0014211, - 0xe00b20a5, 0xd5090789, 0x9b104639, 0x980d9a0f, 0xffa1f000, 0x28009005, 0x2001d14d, 0x220a9903, - 0x04098f09, 0x42110e89, 0x4990d007, 0x67616721, 0x29209906, 0x498ed109, 0x2211e006, 0xd03a4211, - 0x6721498c, 0x498c6761, 0x210167a1, 0x2e009a01, 0xd0117351, 0x29009904, 0x2e01d033, 0x2127d02e, - 0x43080289, 0x06099900, 0x43080a09, 0x43084983, 0x48836068, 0xe01760a8, 0x28009800, 0x9a04d00f, - 0x2a004980, 0xb2c0d005, 0x497f1840, 0x60684308, 0xb2c0e00a, 0x497d1840, 0x60684308, 0x487ce00b, - 0x98046068, 0xd0062800, 0x20019901, 0x6c387388, 0x43082140, 0x98056438, 0xbdf0b011, 0x09002126, - 0x2e01e7ce, 0x2107d00c, 0x43080289, 0x06099900, 0x43080a09, 0x4308496f, 0x486f6068, 0xe7ea60a8, - 0x09002106, 0xb5f7e7f0, 0xb0984e6c, 0xd008000d, 0x466a2308, 0x98182100, 0xfc37f7ff, 0xd1640004, - 0x2404e001, 0x4966e061, 0x42889800, 0x4634d001, 0x4668e05b, 0x60287900, 0x79804668, 0x280a1c40, - 0x200ad900, 0x981a9016, 0x28002108, 0x0209d000, 0xaa029816, 0x981800c3, 0xfc17f7ff, 0xd1440004, - 0x46282164, 0xfeb0f001, 0xe03b2600, 0xaa0200f0, 0x18835c11, 0x020079d8, 0x20ff180a, 0x42820200, - 0x4850d002, 0xd12c4282, 0x20022100, 0x1819020f, 0x43397909, 0xd5f91e40, 0x008778d8, 0x2800981a, - 0x0209d000, 0x020020ff, 0xd10c4282, 0xd9002f50, 0x462a2750, 0x3208463b, 0xf7ff9818, 0x0004fbe6, - 0x606fd113, 0x483fe00d, 0xd10a4282, 0x463b462a, 0x9818325c, 0xfbd9f7ff, 0xd1060004, 0x20582101, - 0x1c765541, 0x42869816, 0x4620d3c0, 0xb5f7e541, 0xb088460d, 0x46282103, 0x230873e9, 0x71433040, - 0x642b2358, 0x73292401, 0xd0012a00, 0x64292159, 0x210f71c4, 0x87c48781, 0x2001462e, 0x024036ff, - 0x64303681, 0x64700240, 0x46306530, 0x90073040, 0x46297244, 0xf7ff9808, 0x2800f91b, 0x4822d172, - 0x90002700, 0x97034821, 0x90012301, 0x466a9702, 0x98084619, 0xfa00f001, 0x97039702, 0x481c4f1a, - 0xe0373780, 0x00002004, 0x08180402, 0x08200412, 0x00002204, 0x0a20043e, 0x00000406, 0x24040405, - 0x08000400, 0x00012404, 0x8a000400, 0x06ff06ff, 0x000006ff, 0x06000600, 0x32101e00, 0xb2000200, - 0x7c01a604, 0x00040200, 0xa604b000, 0x26043000, 0x00002404, 0x32000200, 0x7c012604, 0x00004e27, - 0x50444653, 0x0000ff84, 0x8b188720, 0xa3028f10, 0xa7048f10, 0x23019001, 0x2100466a, 0x98089700, - 0xf9baf001, 0x02c02013, 0x23029006, 0x49feaa06, 0xf0009808, 0x2800fefc, 0x2308d114, 0x2110aa04, - 0xf0009808, 0x2800fee0, 0x9805d10c, 0xb28049f7, 0x98049005, 0xd1044288, 0x98052159, 0x42880209, - 0x48f3d002, 0xbdf0b00b, 0xaa042308, 0x98082127, 0xfec9f000, 0xd1f52800, 0x04009804, 0x90040e00, - 0x28093817, 0x9904d8ed, 0x40882001, 0x200f6528, 0x90060300, 0xaa062302, 0x98082100, 0xfec7f000, - 0xd1df2800, 0x49e3462c, 0x60213480, 0x606149e2, 0x60a149e2, 0x4ae349e2, 0x4fe44be3, 0xc48e3410, - 0x60274fdc, 0x60674fe2, 0x60a74fdc, 0xc40e3410, 0x60a74fe0, 0x60616022, 0x60e74fdf, 0x61274fdd, - 0x4fde35ff, 0xc58e3511, 0x34144fd2, 0x602f3fa0, 0x606f4fdb, 0xc48e4fdb, 0x4fd6c40e, 0x602260a7, - 0x4fd56061, 0x4fd360e7, 0x4cca6127, 0x3ca03d20, 0x4cd5602c, 0x4cd5606c, 0x462f60ac, 0x37304cd1, - 0xc70ec71e, 0x656c4ccb, 0x652964ea, 0x65ac4cca, 0x37144cc8, 0xc70e65ec, 0x66e949cd, 0x72312102, - 0x72722203, 0x22017131, 0x74317172, 0x74712109, 0x73312104, 0x73732305, 0x210b7531, 0x99077571, - 0xe77f730a, 0x2504b5f7, 0x4617b092, 0x2a00460c, 0x7878d004, 0x42887839, 0x2500d101, 0x4620e087, - 0x21083040, 0x71419011, 0x25037878, 0x28422601, 0x2841d001, 0x2502d103, 0x21049811, 0x78787141, - 0xd0012882, 0xd1002842, 0x20002621, 0x90014669, 0x70087408, 0x90022001, 0xa8092120, 0xfd24f001, - 0x200278f9, 0x29060242, 0x2907d00b, 0x2908d012, 0x2001d001, 0x0229e02b, 0x43131d8b, 0x930931ff, - 0x0229e005, 0x3366460b, 0x31994313, 0x43119309, 0xe01c910d, 0x460f0229, 0x376602b2, 0x4317062b, - 0x431f06b5, 0x432f46ac, 0x31992599, 0x4311042d, 0x4319432f, 0x22334665, 0x04524329, 0x97094311, - 0x2e21910d, 0x6c21d103, 0x43112240, 0x90036421, 0x20019911, 0x06017188, 0x498e6521, 0x498e6021, - 0x21036061, 0x73a17361, 0x31c921ff, 0x200a5508, 0x46216760, 0xf7fe9812, 0x0005ffab, 0xaa09d117, - 0x9b032101, 0xf0019812, 0x4669f897, 0xf0009812, 0x4605ffa2, 0x217d4881, 0x00c94448, 0xf0016800, - 0xe001fcc5, 0x1e40bf00, 0x28009011, 0x4628d1fa, 0xbdf0b015, 0xb09cb5f7, 0x460c981e, 0x02286805, - 0x28050f00, 0x2700d011, 0x22304975, 0xa80d4479, 0xf926f7fe, 0x0f000428, 0x0328900a, 0x980a0f05, - 0xd0042800, 0xd1132803, 0x2701e001, 0x2d00e7ec, 0x2d03d010, 0x2800d10c, 0x2003d00a, 0x20107320, - 0x981e6420, 0x02006800, 0x28040f00, 0xe019d018, 0xe1952604, 0xf7fe4668, 0x4606fbcb, 0xf7fe2000, - 0x2e00fbc3, 0x466ad106, 0x981c4621, 0xff2af7ff, 0xd1ee0006, 0x73202000, 0x64202010, 0xe0022003, - 0x64202050, 0x90092006, 0x4328980a, 0x2701d100, 0x990a4620, 0x29033040, 0x2101d008, 0x46217141, - 0xf7fe981c, 0x0006ff35, 0xe001d1d3, 0xe7f52108, 0x2d002000, 0x2f00d004, 0x2001d001, 0x2002e000, - 0xa90d0100, 0x23011842, 0x981c4619, 0xf814f001, 0x46692000, 0x75089002, 0x71082003, 0x90032001, - 0xa80b9004, 0xa9019008, 0xf000981c, 0x0006ff14, 0xa808d1af, 0x28c27b00, 0x2101d1ab, 0x2d000409, - 0xd01da808, 0x460a7c40, 0x40823830, 0x46206522, 0x30ff2201, 0x30810312, 0x11126442, 0x65016402, - 0x73202003, 0x64202010, 0x40472001, 0x46294620, 0x30c130ff, 0x35804625, 0x29009019, 0xe078d002, - 0xe7e07b80, 0x2803980a, 0x2101d173, 0x20027421, 0x82617460, 0x75622206, 0x23007521, 0x22074669, - 0x70ca700b, 0xd04a2f00, 0x466a2182, 0x61a07051, 0x6628481c, 0x3872481b, 0x481b6668, 0x981e66a8, - 0x06007800, 0xe0310f00, 0x00000555, 0x52005100, 0x00004e29, 0x8b1887a0, 0xb3068f10, 0x0000a704, - 0x87008700, 0x87aa8700, 0x87058700, 0x87708700, 0xb70b8f10, 0x87558700, 0x87028700, 0x87a08700, - 0xa3808f10, 0x87808700, 0x87008f10, 0x00008730, 0x87108700, 0x42464346, 0x56010400, 0x0000000c, - 0x00001c14, 0x04000472, 0x20010400, 0xd0022803, 0x728b9919, 0x9919e01a, 0x72882001, 0x2181e016, - 0x7059466b, 0x4bfe61a0, 0x662b48fe, 0x48fe6668, 0x210166a8, 0x77214620, 0x70423020, 0x48f87001, - 0x38726321, 0x6768672b, 0x67a848f7, 0xf7fe9800, 0x48f6fadb, 0x48f66328, 0x1de06128, 0x30f9990a, - 0xd0032900, 0xd0162f00, 0xe0152321, 0x73212101, 0x602949f0, 0x606949f0, 0x1d8949ee, 0x49ef6101, - 0x49ec6141, 0x65293115, 0x31d049ea, 0x21236001, 0x63010149, 0x2301e084, 0xd0012f00, 0xe0002122, - 0x468e2102, 0xd0012f00, 0xe000212c, 0x911a210c, 0xd0012f00, 0xe0002129, 0x910a2109, 0xd0012f00, - 0xe0002128, 0x91002108, 0x4ad80299, 0x3a18069b, 0x469c188a, 0x4bda431a, 0x602a431a, 0x23194672, - 0x015b0292, 0x9b1a18d2, 0x069b4696, 0x4bd5431a, 0x606b4313, 0x029a9b0a, 0x009b23c1, 0x920a18d2, - 0x1c9a60aa, 0x4663188a, 0x4bcf431a, 0x4acf4313, 0x188a642b, 0x431a4663, 0x43134bcd, 0x02122203, - 0x188a622b, 0x431a4663, 0x061b2303, 0x626a431a, 0x4ac662aa, 0x320d9b0a, 0x188a62eb, 0x431a4663, - 0x43134bc4, 0x9b006103, 0x069b4672, 0x23c1431a, 0x4313049b, 0x61434abd, 0x188a321c, 0x431a4663, - 0x43134bbd, 0x4672652b, 0x22f7656a, 0x188d0092, 0x431d4663, 0x46724bb9, 0x6005431d, 0x221b6042, - 0x18890152, 0x4ab64663, 0x43114319, 0x2f006301, 0x6c20d003, 0x43082140, 0x99196420, 0x73082002, - 0xb01f4630, 0xb5f7bdf0, 0x49ae460c, 0x4617b0a6, 0x44792220, 0xf7fda81d, 0x6838ff63, 0x0f000200, - 0xd0092807, 0x90002000, 0x03006838, 0xd0050f00, 0x73202003, 0xe0142050, 0xe7f42001, 0xf7fea801, - 0x4605fa17, 0xf7fe2000, 0x2d00fa0f, 0xaa01d106, 0x98264621, 0xfd76f7ff, 0xd1140006, 0x73202000, - 0x46252010, 0x35402108, 0x71696420, 0x98264621, 0xfd8ef7fe, 0xd1f00006, 0x03006838, 0xd0030f01, - 0x28030f00, 0xe09ed003, 0xaa1d2301, 0x2301e001, 0x2101aa21, 0xf0009826, 0x2008fe6f, 0x22007168, - 0x9826a904, 0xfbbff7ff, 0xd1220006, 0xaa02ab03, 0x4620a904, 0xf971f7ff, 0x28009800, 0x2050d103, - 0x20036420, 0x46257320, 0x35804870, 0x48706328, 0x68396128, 0x0f020308, 0x30ff4620, 0x900130c1, - 0x2a0338c0, 0x0409d006, 0x2a030f0a, 0x0f09d002, 0xe068d01b, 0x62294974, 0x60294974, 0x60694974, - 0x64294974, 0x39dc4971, 0x49706529, 0x60013921, 0x0149213b, 0x496d6301, 0x610139eb, 0x6141496e, - 0x03006838, 0xd02f0f00, 0x2201e04a, 0x06126d21, 0xd3024291, 0x218e2220, 0x2218e001, 0x9b0221c2, - 0xb2db0412, 0x43134c65, 0x652b4323, 0x43119b03, 0x4313b2db, 0x43234a62, 0x60034311, 0x21476101, - 0x614101c9, 0x29009900, 0x495ed00a, 0x495e6029, 0x21236069, 0x63010149, 0x20019901, 0xe0227388, - 0x6029495a, 0xe7f34952, 0x46692000, 0x27067008, 0x208270cf, 0x98007048, 0xf966f7fe, 0x74202001, - 0x74612102, 0x61a121e7, 0x75207567, 0x48348260, 0x6628300f, 0x38724832, 0x48386668, 0x66a81ec0, - 0x20029901, 0x46307308, 0xbdf0b029, 0xb0b4b5f7, 0x90004847, 0x46156810, 0x0f000200, 0x2809460c, - 0x2600d01b, 0x22504943, 0xa81e4479, 0xfe78f7fd, 0x90022000, 0x30404620, 0x90012104, 0x68287141, - 0x04000301, 0x20100f05, 0x64200f0f, 0xd0062f00, 0xd01b2f02, 0xd01f2f03, 0x2601e169, 0xa804e7e2, - 0xf926f7fe, 0x20009000, 0xf91ef7fe, 0x28009800, 0xaa04d107, 0x98344621, 0xfc84f7ff, 0x28009000, - 0x9901d1ea, 0x71482001, 0xe0032000, 0x20049901, 0x20037148, 0xe0087320, 0x73202003, 0x99012008, - 0x71482e00, 0x2001d101, 0x2d009002, 0x2d02d003, 0x2d03d001, 0x4638d1d0, 0xd1004328, 0xe03b2601, - 0x04000472, 0x04020400, 0x20010400, 0x00000406, 0x24040405, 0x0820040c, 0x24043308, 0x00002004, - 0x03110000, 0x03060000, 0x03f90000, 0x00000305, 0x03fa0000, 0x03ed0000, 0x03de0000, 0x03230000, - 0x039f0000, 0x000018be, 0xa7040705, 0x8b2007fd, 0xa704b306, 0x00000706, 0x0000a304, 0x08000400, - 0x0b000400, 0x0b2004fc, 0x27043306, 0x8b2004fd, 0x00004e29, 0x00001708, 0xd0022d02, 0xd0022d03, - 0x2004e004, 0x2008e000, 0x71489901, 0x6c212040, 0xd0012e00, 0xe0004381, 0x64214301, 0x98344621, - 0xfc36f7fe, 0x28009000, 0x2e00d18a, 0x2f02d008, 0x2f03d002, 0xe001d10c, 0xe0092001, 0xe0072002, - 0xd0022f02, 0xd1032f03, 0x2003e001, 0x2004e000, 0xa91e0100, 0x23011842, 0x98344619, 0xfd0cf000, - 0x9a02a905, 0xf7ff9834, 0x9000fa5e, 0xd17d2800, 0xaa32ab33, 0x4620a905, 0xf80ff7ff, 0x73202003, - 0x30804620, 0x630149fd, 0x610149fd, 0xd0012e00, 0xe0002302, 0x2e002322, 0x210cd001, 0x212ce000, - 0x2e00468e, 0x2109d001, 0x2129e000, 0x2e009102, 0x2208d001, 0x2228e000, 0x0d8f07a9, 0x46399204, - 0x07aa9701, 0x370b0992, 0x4317069b, 0x431f469c, 0x431f4bec, 0x46736007, 0x029b1d0f, 0x9b02431f, - 0x069b4317, 0x9302431f, 0x049b2301, 0x6047431f, 0x3720460f, 0x46634317, 0x4be2431f, 0x431f4696, - 0x460f6507, 0x431737d8, 0x431f4663, 0x431f4bdd, 0x33f91de3, 0x1c8f601f, 0x46624317, 0x4ad94317, - 0x611f4317, 0x9a04460f, 0x02923780, 0x22014317, 0x31600292, 0x4311615f, 0x63192702, 0xd0012d02, - 0xd10f2d03, 0x46739901, 0x43191d49, 0x43199b02, 0x43194bcd, 0x99016201, 0x43111d89, 0x32cd22ff, - 0x55176401, 0x61a12100, 0xe0002d02, 0xd002e03f, 0xd0032d03, 0x2201e005, 0xe0010492, 0x04d22201, - 0x2e0061a2, 0x6c22d010, 0x431a2380, 0x22016422, 0x551a2379, 0x66024abd, 0x66424abd, 0x74202001, - 0xd0072d00, 0xe0067467, 0x69a22301, 0x431a05db, 0xe7ef61a2, 0x22067461, 0x75207562, 0x46688260, - 0x2e007301, 0x2d02d008, 0x2d03d002, 0xe007d002, 0xe0122041, 0xe0102081, 0xd00b2d02, 0xd00b2d03, - 0x20087341, 0x73c84669, 0xf7fd9803, 0x9800ffbd, 0xbdf0b037, 0xe0002042, 0x46692082, 0xe7f07348, - 0x2704b5f7, 0x460c4616, 0xd04d2900, 0xd04b2e00, 0x462001f9, 0xf868f001, 0x46252101, 0x71a93540, - 0x65200608, 0x6020489b, 0x6060489b, 0x73602003, 0x20ff73a0, 0x550130c9, 0x02006830, 0x00030f00, - 0xf966f001, 0x0c06060a, 0x1d171711, 0x3023231d, 0x46214632, 0xf0009800, 0xe001f8d6, 0xe0032201, - 0xd0180007, 0x2200e01e, 0x98004621, 0xf9cff7ff, 0x4632e7f6, 0x98004621, 0xfb7cf7ff, 0x4632e7f0, - 0x98004621, 0xfd3ff7ff, 0x4632e7ea, 0x98004621, 0xfe1cf7ff, 0x4620e7e4, 0xff51f7fd, 0x07007830, - 0x71a80f00, 0x71282001, 0xbdfe4638, 0x2004b5ff, 0x460fb081, 0xd01e2900, 0x35ff463d, 0x6c693581, - 0x460c4249, 0x18d24014, 0x400a4252, 0x31ca21ff, 0x42565dc9, 0xd10c2900, 0x29006d29, 0xe02ad009, - 0x46394622, 0xf7fe9801, 0x2800fcae, 0x6c69d103, 0x42b4190c, 0xb005d3f4, 0x6d29bdf0, 0x43884620, - 0x2000d00e, 0x28001b32, 0x4291d00c, 0x4622d80a, 0x98014639, 0xfcf0f7fe, 0xd1ec2800, 0xe0096d29, - 0xe7ef2001, 0x46394622, 0xf7fe9801, 0x2800fc8c, 0x6c69d1e1, 0x42b4190c, 0xe7dcd3df, 0xb089b5ff, - 0x9c122004, 0x4616461f, 0xd0222900, 0xd0202e00, 0xd01e2c00, 0xf0004608, 0x2103f8ed, 0x7011466a, - 0x91032101, 0x91022100, 0x4d4c7410, 0xd80042ac, 0x46694625, 0x96079701, 0x98099508, 0xfa8bf000, - 0xd1062800, 0x008908a9, 0x197f1b64, 0x2c00198e, 0xb00dd1eb, 0xb570bdf0, 0x460cb08e, 0x910c2100, - 0x910b9100, 0x466a910d, 0x46069102, 0x20037511, 0x25017110, 0x483a9503, 0x92089509, 0x462b900a, - 0xaa0a9504, 0x46304629, 0xfb56f000, 0x4630a901, 0xfa61f000, 0xd1142800, 0x22f79900, 0x4b2b4011, - 0x3310040a, 0x910018d3, 0x742522ff, 0x51133261, 0x220e7525, 0x61a17562, 0x74612104, 0x34c134ff, - 0xb00e73e5, 0xb5f0bd70, 0x20004607, 0x460db0a9, 0x24044616, 0x90254923, 0x90279026, 0x44792230, - 0xa8199028, 0xfbdcf7fd, 0x03006830, 0xd1580f00, 0x20452104, 0x46285541, 0x3080491b, 0x491b6001, - 0x46296041, 0xf7fe4638, 0x0004fa23, 0x7830d149, 0x0f000600, 0xd10e2801, 0x49151de8, 0x670130f9, - 0x14096741, 0x23006781, 0x4629461a, 0xf7fe4638, 0x0004fa24, 0x6830d135, 0xe01b0300, 0x00000406, - 0x24040405, 0x00200400, 0x00040400, 0x04000471, 0x00002003, 0x42464346, 0x56010400, 0x0000ffff, - 0x24010485, 0x00001152, 0x08180403, 0x00012404, 0x06ff06ff, 0x01000f00, 0x1842a919, 0x46192301, - 0xf0004638, 0x2200fad9, 0x46384669, 0xf82bf7ff, 0xd1060004, 0x466a4633, 0x46384629, 0xfe68f7fe, - 0x46204604, 0xb530e4f0, 0x2403b089, 0x702c466d, 0x00492501, 0x95032400, 0x94029101, 0x742c466d, - 0x93084669, 0xf0009207, 0xb009f9c6, 0xb530bd30, 0x2402b089, 0x702c466d, 0x00492401, 0x94029101, - 0x21009403, 0x46697429, 0x92059306, 0xf9b3f000, 0x0000e7eb, 0x07406c00, 0x2001d501, 0x20004770, - 0x6c004770, 0xd5010680, 0x47702001, 0x47702000, 0x07c06c00, 0x2001d000, 0x6c004770, 0xd5010700, - 0x47702001, 0x47702000, 0x07806c00, 0x2001d501, 0x20004770, 0x6c004770, 0xd5010640, 0x47702001, - 0x47702000, 0xb085b5f3, 0x2404460e, 0xf0009805, 0x0005fcce, 0x2e00d07e, 0x7b30d07c, 0xd8792803, - 0xd00a2800, 0xd0082801, 0xd0062802, 0xd1042803, 0xf7ff4630, 0x2800ffd9, 0x20ffd002, 0xe00c3001, - 0x2102aa03, 0xf7fd9805, 0x49fefc94, 0x42889803, 0x6c30d306, 0xd4030600, 0x90002079, 0xe0219001, - 0x00602400, 0x31601981, 0x7e0f7e48, 0xd10b2800, 0x43472064, 0x214bd01d, 0xf0004638, 0x214bfe77, - 0x42b94341, 0x1c40d200, 0x283f213f, 0x4608d900, 0x0c400680, 0x30ff00a2, 0x46693001, 0x50881c64, - 0xd3de2c02, 0x22026828, 0x28000780, 0x2000da1c, 0x4630e01e, 0xff9ff7ff, 0x46024607, 0x9805a902, - 0xfc82f7fd, 0x990248e0, 0xd0092f00, 0xfe4ef000, 0x217d0880, 0x434800c9, 0xf000214b, 0xe7d2fe47, - 0xfe44f000, 0xe7f40840, 0x20016829, 0x60294311, 0x29006d31, 0x6d71d102, 0xd0022900, 0x9b0021c0, - 0x6db1514b, 0xd1022900, 0x29006df1, 0x21c4d004, 0xe0009b01, 0x514be006, 0xd0022800, 0x43906828, - 0x24006028, 0xb0074620, 0xb5f8bdf0, 0x20044607, 0x460e461c, 0xd0162f00, 0xd0142a00, 0xd0122c00, - 0x48c14611, 0xfe12f000, 0x46054601, 0x46304361, 0xfe0cf000, 0x1c40e000, 0x43694601, 0x42b14361, - 0x6038d3f9, 0xbdf82000, 0xb085b5f0, 0x460e4db7, 0x95004607, 0xf0009501, 0x0004fc1a, 0x2e00d02b, - 0xaa02d029, 0x46382102, 0xfbf3f7fd, 0x2101aa03, 0xf7fd4638, 0x2601fbee, 0x02b64fad, 0x46394633, - 0x9a024668, 0xffc1f7ff, 0x46394633, 0x9a03a801, 0xffbbf7ff, 0x42a89800, 0x9500d900, 0x42a89801, - 0x9501d900, 0x99019800, 0xb2890400, 0x60604308, 0xb0052000, 0x2004bdf0, 0xb5f3e7fb, 0x2000b087, - 0x460c9000, 0x98072504, 0xfbe1f000, 0x28009003, 0x2c00d054, 0x4620d052, 0x46273040, 0x37509005, - 0x30ff2600, 0x90023041, 0x00b26838, 0x98030a81, 0x90011810, 0x7ba06601, 0x06c51d3f, 0x0eed7b60, - 0x0d8006c0, 0x7be04305, 0x0c400700, 0x46204305, 0xfed3f7ff, 0xd0022800, 0x02802001, 0x6f604305, - 0xd00d2800, 0x2102aa04, 0xf7fd9807, 0x2301fb92, 0x46686f61, 0xf7ff9a04, 0x9800ff68, 0x43050400, - 0x67059801, 0x79c09805, 0xd00e2800, 0x7c009802, 0xd00a0741, 0x22079902, 0x03407c49, 0x0d090709, - 0x18800352, 0x4308b280, 0x2009e001, 0x99010200, 0x60083180, 0x2e041c76, 0x2500d3b6, 0xb0094628, - 0x4602bdf0, 0x2004b510, 0xd0212a00, 0xd01f2900, 0x5c402044, 0xd10c2801, 0x084368d0, 0x2040005b, - 0x46084303, 0xfe76f7ff, 0xd0012800, 0x43032001, 0x68d060d3, 0x43082120, 0x4b5e60d0, 0x00812000, - 0x6a0c1889, 0x620c401c, 0x28031c40, 0x2000d3f7, 0xb510bd10, 0xfb5bf000, 0xd00b2800, 0x23012100, - 0x008a07db, 0x32801812, 0x431c6814, 0x1c496014, 0xd3f62904, 0xb5febd10, 0x20044605, 0x460e9000, - 0xf0004628, 0x0004fb44, 0x2e00d07e, 0x7830d0fc, 0xd8792803, 0x90017c30, 0x46202700, 0xfb3ff000, - 0xf7ff4628, 0x6960ffd6, 0x4308211e, 0x46256160, 0x68703580, 0x78306228, 0xd0022802, 0xd0022803, - 0x8b30e003, 0x8c30e000, 0x7b31b287, 0x1e497a30, 0x07490700, 0x09490b00, 0x99014308, 0x430807c9, - 0x62684338, 0x28037830, 0x69f0d14b, 0x07836a32, 0x2340d14a, 0x469e211c, 0x6bab63a9, 0x430b2101, - 0x6bab63ab, 0xd1fc07db, 0x430b6b2b, 0xe036632b, 0x31f91de1, 0x45724673, 0x6967d30f, 0x06bf089b, - 0xe029d402, 0xc080c980, 0xd2fb1e5b, 0x1a524671, 0x23206961, 0x61614319, 0x6f2be01e, 0x0d5b061b, - 0xd2034293, 0xc908e018, 0xc0081f12, 0xd2fa2a04, 0xd0102a00, 0x91016809, 0x468ca901, 0x23004601, - 0x4667e007, 0x700f783f, 0x1c7f4667, 0x46bc1c49, 0x42931c5b, 0x2200d3f5, 0x07096961, 0x2a00d401, - 0x7830d1c6, 0xe0002802, 0xd001e062, 0xd1482801, 0x69b26971, 0xd15b0788, 0x46842040, 0x63e8201c, - 0xe0096be8, 0x05f5e100, 0x3b9aca00, 0x0000ffff, 0x1dcd6500, 0xfcf0ff00, 0x43182301, 0x6be863e8, - 0xd1fc07c0, 0xe02a4686, 0x30ff4620, 0x30816963, 0xd521065b, 0x089b4663, 0xd2024562, 0xc980e00e, - 0x1e5bc080, 0x4660d2fb, 0xe0091a12, 0xdd032a00, 0xc080c980, 0xe0011f12, 0xc0802700, 0xd2f51e5b, - 0x28004670, 0x6b28d104, 0x43182301, 0x469e6328, 0x23406960, 0x61604318, 0x07006960, 0x2a00d401, - 0x7830dcd2, 0xd1032800, 0x21016b28, 0x63284308, 0xf0004620, 0x6960fa74, 0xd50b0700, 0x01006e68, - 0x280e0f00, 0x48fed001, 0x48fde001, 0x90001e40, 0xbdfe9800, 0xe7fa2000, 0x460eb5f8, 0x461f2104, - 0x91004615, 0xfa53f000, 0xd0230004, 0xd0212d00, 0x19f22100, 0x23104149, 0x1a9a2000, 0xd3194188, - 0xf0004620, 0x4aeffa4c, 0x200261a2, 0x19f161e0, 0x008b00b0, 0x19090081, 0x31ff31ff, 0xe0023102, - 0xc140cd40, 0x42981c40, 0x61a2d3fa, 0x61e02001, 0x90002000, 0xbdf89800, 0x4604b570, 0xb08a2004, - 0xd0242900, 0x466e2000, 0x20037030, 0x90022501, 0x74329503, 0x93012047, 0x28005c40, 0x4608d009, - 0x308130ff, 0x2a007a02, 0x7a42d003, 0x7a009202, 0x98029003, 0x01009b03, 0x21011842, 0x32804620, - 0xffaaf7ff, 0x46204669, 0xf7ff9502, 0xb00afeb4, 0xb5ffbd70, 0xb0912004, 0x900e460d, 0xd0792900, - 0x30404628, 0x21018f82, 0x4094460c, 0x93028fc2, 0x22039200, 0x711a466b, 0x91039104, 0x9108a90c, - 0x29009913, 0x2108d001, 0x2104e000, 0x99139109, 0x79c07519, 0xd0092800, 0x30ff4628, 0x79013081, - 0xd0032900, 0x91037941, 0x90047900, 0x9b049803, 0x19420100, 0x99033280, 0xf7ff9811, 0x6f2dff6d, - 0xd0012d00, 0xe0002001, 0x26002000, 0xa901900f, 0xf7ff9811, 0x900efe70, 0xd13b2800, 0x28009813, - 0xa90ad019, 0xab0ca80b, 0x781f2208, 0x785f700f, 0x1c407007, 0x1e921c49, 0x2a001c9b, 0x9800d1f5, - 0x2800990b, 0xd004980a, 0x46214008, 0xd10a4381, 0x4308e00e, 0x9800e00a, 0xd0062800, 0x4620990c, - 0x28004388, 0x2701d004, 0x980ce003, 0xe7f84020, 0x980f2700, 0xd00b4207, 0x43304628, 0x207dd00d, - 0x210000c0, 0xf9aaf7fd, 0x43c02000, 0x41461e6d, 0xd1bc2f00, 0xb015980e, 0x4889bdf0, 0x900e1c40, - 0xb5f7e7f8, 0x460db08a, 0x980a2604, 0xf96ff000, 0xd0540007, 0xd0522d00, 0x46692001, 0x980c7008, - 0x20009001, 0x20047408, 0x90062400, 0x194200a0, 0x30204610, 0x29007841, 0x2301d03e, 0x59db025b, - 0x0f9b059b, 0x192bd003, 0x2b027f5b, 0x9102d034, 0x32307800, 0x90039205, 0x46292200, 0x980a9b0c, - 0xff1af7ff, 0xd12b2800, 0x21019802, 0x19420100, 0x9b033280, 0xf7ff980a, 0x2001fedf, 0x46699002, - 0xf7ff980a, 0x0006fde8, 0x8a68d11a, 0xd10e2800, 0x7f491929, 0xd00a2902, 0xd0082903, 0x46292200, - 0x980a9b0c, 0xff25f7ff, 0xd1090006, 0x2164e004, 0x21004348, 0xf942f7fd, 0x2c031c64, 0x4630d3b6, - 0xbdf0b00d, 0xb087b5f3, 0x2604460d, 0xf0009807, 0x0004f90e, 0x2d00d07e, 0x7c28d0fc, 0xd1022800, - 0x28007f28, 0x6c28d009, 0xd40406c0, 0xf7ff4628, 0x2800fc22, 0x2001d001, 0x2000e000, 0x494a9003, - 0x42886828, 0x9807d166, 0xf87bf7fd, 0x98074629, 0xf95ef7fd, 0x30404628, 0x90029903, 0xd0022900, - 0x21012200, 0x4628e005, 0xfc05f7ff, 0x98024602, 0x98077981, 0xf86df7fd, 0xf7fd9807, 0x6820f85a, - 0x43b02602, 0x46206020, 0xf8c9f000, 0x43306820, 0x68206020, 0x40084935, 0x79499902, 0xd1012908, - 0x43080289, 0x43084932, 0x07897b29, 0x43010e89, 0x46296021, 0xf7ff9807, 0x68a0fc97, 0x03c92101, - 0x60a04388, 0xf7ff4628, 0x2800fbc3, 0x68a0d004, 0x04c92101, 0x60a04308, 0x46204629, 0xfd21f7ff, - 0x98074629, 0xfcb9f7ff, 0x98074629, 0xfbcaf7ff, 0x21026820, 0x60204388, 0xf0004620, 0x4628f890, - 0x30507c29, 0x29009004, 0x9807d01c, 0x20049005, 0xe0002100, 0x9e04e05d, 0x460f9100, 0x9101ce02, - 0xd00a2900, 0x9a004629, 0xf0009805, 0x2800f890, 0x9a01d106, 0x18899900, 0x1c7f9100, 0xd3ed2f04, - 0xd1460006, 0x28007f28, 0x9807d027, 0x20049005, 0xd0202d00, 0x9e042100, 0x460f9100, 0xe009ce02, - 0x00001b59, 0x5af05af0, 0x42464346, 0x0000df0f, 0xffff0000, 0x29009101, 0x4629d00a, 0x98059a00, - 0xfedff7ff, 0xd1062800, 0x99009a01, 0x91001889, 0x2f041c7f, 0x0006d3e2, 0x9803d11b, 0xd0172800, - 0x26026820, 0x60204330, 0xf7ff4628, 0x4602fb64, 0x79819802, 0xf7fc9807, 0x4629ffcc, 0xf7ff9807, - 0x4629fc13, 0xf7ff9807, 0x6820fb5d, 0x602043b0, 0x46302600, 0xb510e4a3, 0xf829f000, 0xd0032800, - 0x6e013080, 0xd5fc0789, 0xb510bd10, 0xf81ff000, 0xd0012800, 0xf813f000, 0xb570bd10, 0xf000460d, - 0x0004f816, 0xf000d00a, 0x2001f81a, 0x682102c0, 0xd0012d00, 0xe0004301, 0x60214381, 0x6801bd70, - 0x43112201, 0x68016001, 0xd1fc07c9, 0x46014770, 0x29002000, 0x4830d102, 0x68004478, 0x30804770, - 0x07c96e01, 0x6e01d0fc, 0xd5fc0789, 0xb5f04770, 0x4616b089, 0x4607460c, 0xf7ff2504, 0x2800ffe8, - 0x2c00d048, 0x30ffd046, 0x300230ff, 0x05806800, 0xd0020f80, 0x28027c60, 0x2501d025, 0x700d4669, - 0x7d609601, 0x7d209002, 0x20009003, 0x46207408, 0x90053018, 0x90062004, 0x22004633, 0x46384621, - 0xfd9af7ff, 0x21019802, 0x19020100, 0x32804638, 0xf7ff9b03, 0x4669fd61, 0x95024638, 0xfc6bf7ff, - 0xd1170005, 0x2500e001, 0x8a61e014, 0xd10c2900, 0x28027c60, 0x2803d009, 0x4633d007, 0x46212200, - 0xf7ff4638, 0x4605fda6, 0x2064e004, 0x21004348, 0xffc4f7fc, 0xe4124628, 0x00000708, 0x88014843, - 0x07492204, 0xda022900, 0x43918801, 0x48408001, 0x07498801, 0x8801d502, 0x80014391, 0x493d483e, - 0x493e6041, 0x68016081, 0x43912280, 0x43112220, 0x483b6001, 0x07c96901, 0x6901d003, 0x00490849, - 0x47706101, 0x4c37b5f8, 0x4a376960, 0x01804937, 0x69a0d518, 0x031b2303, 0xd0054018, 0x03122201, - 0xd00a4290, 0xe0092000, 0x07806910, 0x2016d001, 0x2014e000, 0x4348492d, 0x4608e000, 0x00896961, - 0xe0290f49, 0x4b296810, 0x0e400640, 0x08474358, 0x07c06b10, 0x2516d001, 0x2514e000, 0x43454823, - 0x30404821, 0x69006a06, 0xfa1af000, 0x23004632, 0xf844f000, 0x194069a1, 0x40114a1d, 0x2201d011, - 0x4b1c0492, 0xd0161a89, 0xd0171a89, 0xd1074291, 0x07416920, 0x46380f49, 0xf0001c49, 0xe000f907, - 0x69612000, 0x0f4904c9, 0xf0001c49, 0x4912f8ff, 0x60084449, 0x6819bdf8, 0xe0000c09, 0x06896819, - 0xf0000e89, 0x2112f8f3, 0xe7ea4348, 0x400b8000, 0x400d0000, 0xd928c520, 0x400bc000, 0x0000ffff, - 0xe000e000, 0x400fc000, 0x400d8000, 0x016e3600, 0x000c0000, 0x400d8100, 0x0000000c, 0x4605b5fe, - 0x460c4610, 0xd0734318, 0x468c46ae, 0x1aad2000, 0x419c4601, 0x4666d367, 0x24012700, 0x1ab6463d, - 0xd302419d, 0x463a4613, 0x46652421, 0x042f4676, 0x433e0c36, 0x1ab60c2d, 0xd304419d, 0x041b0c15, - 0x0412432b, 0x46653410, 0x062f4676, 0x433e0a36, 0x1ab60a2d, 0xd304419d, 0x021b0e15, 0x0212432b, - 0x46653408, 0x072f4676, 0x433e0936, 0x1ab6092d, 0xd304419d, 0x011b0f15, 0x0112432b, 0x46651d24, - 0x07af4676, 0x433e08b6, 0x1ab608ad, 0xd304419d, 0x009b0f95, 0x0092432b, 0x46651ca4, 0x07ef4676, - 0x433e0876, 0x1ab6086d, 0xd31a419d, 0x415b1892, 0xe0161c64, 0x46761800, 0x41494665, 0x419d1ab7, - 0x90009101, 0x4660d309, 0x41981ab1, 0x4684468e, 0x99019800, 0x1c402500, 0x07dd4169, 0x432a0852, - 0x1e64085b, 0x4672d5e6, 0xb0034663, 0xe7ffbdf0, 0x46012000, 0x46c046c0, 0x4623462a, 0xb510e7f5, - 0xf0002000, 0x46c0f907, 0x200146c0, 0xf8fcf000, 0x4603bd10, 0x430bb510, 0xd10f079b, 0xd30d2a04, - 0xc910c808, 0x42a31f12, 0xba18d0f8, 0x4288ba21, 0x2001d901, 0x2000bd10, 0xbd1043c0, 0xd0032a00, - 0xd00307d3, 0xe0071c52, 0xbd102000, 0x780c7803, 0x1c491c40, 0xd1071b1b, 0x780c7803, 0x1c491c40, - 0xd1011b1b, 0xd1f11e92, 0xbd104618, 0xc004e001, 0x29041f09, 0x078bd2fb, 0x8002d501, 0x07c91c80, - 0x7002d000, 0x29004770, 0x07c3d00b, 0x7002d002, 0x1e491c40, 0xd3042902, 0xd5020783, 0x1c808002, - 0xe7e31e89, 0xe7ee2200, 0xe7df2200, 0x09032200, 0xd32c428b, 0x428b0a03, 0x2300d311, 0xe04e469c, - 0x430b4603, 0x2200d43c, 0x428b0843, 0x0903d331, 0xd31c428b, 0x428b0a03, 0x4694d301, 0x09c3e03f, - 0xd301428b, 0x1ac001cb, 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152, 0xd301428b, 0x1ac0014b, - 0x09034152, 0xd301428b, 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb, 0x08834152, 0xd301428b, - 0x1ac0008b, 0x08434152, 0xd301428b, 0x1ac0004b, 0x1a414152, 0x4601d200, 0x46104152, 0xe05d4770, - 0xd0000fca, 0x10034249, 0x4240d300, 0x22004053, 0x0903469c, 0xd32d428b, 0x428b0a03, 0x22fcd312, - 0xba120189, 0x428b0a03, 0x0189d30c, 0x428b1192, 0x0189d308, 0x428b1192, 0x0189d304, 0x1192d03a, - 0x0989e000, 0x428b09c3, 0x01cbd301, 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0, 0x428b0943, - 0x014bd301, 0x41521ac0, 0x428b0903, 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301, 0x41521ac0, - 0x428b0883, 0x008bd301, 0x41521ac0, 0x0843d2d9, 0xd301428b, 0x1ac0004b, 0x1a414152, 0x4601d200, - 0x41524663, 0x4610105b, 0x4240d301, 0xd5002b00, 0x47704249, 0x105b4663, 0x4240d300, 0x2000b501, - 0x46c046c0, 0x0000bd02, 0x20184901, 0xe7febeab, 0x00020026, 0xf000b510, 0xf000f80b, 0xbd10f802, - 0xb5104770, 0xd0012800, 0xffeef7ff, 0x0000bd10, 0x2100b510, 0xf000a002, 0x2001f813, 0x0000bd10, - 0x41474953, 0x3a545242, 0x6e624120, 0x616d726f, 0x6574206c, 0x6e696d72, 0x6f697461, 0x0000006e, - 0x4605b570, 0x200a460c, 0x1c6de000, 0xf812f000, 0xd0062d00, 0x28007828, 0xe002d1f7, 0xf0001c64, - 0x2c00f809, 0x7820d002, 0xd1f72800, 0xf000200a, 0xbd70f801, 0x4669b508, 0x20037008, 0xbd08beab, - 0x0c04b5f8, 0x4626b28b, 0x435eb282, 0x46100c0d, 0x43580c37, 0x19800436, 0x41792100, 0x436e4616, - 0x04360c37, 0x41791980, 0x436e4626, 0xbdf81989, 0x4674b430, 0x78251e64, 0x42ab1c64, 0x461dd200, - 0x005b5d63, 0xbc3018e3, 0x00004718, 0x08220000, 0x06180816, 0x0612041e, 0x0411060e, 0x0216060c, - 0x06180000, 0x060c0416, 0x0312021e, 0x01210216, 0x0116011a, 0x017d7840, 0x02faf080, 0x05f5e100, - 0x07735940, 0x33221100, 0x77665544, 0xbbaa9988, 0xffeeddcc, 0x0818045a, 0x24ff3008, 0x00000000, - 0x00000000, 0x0918055a, 0x25ff3108, 0x00000000, 0x00000000, 0x0a18065a, 0x26ff3208, 0x00000000, - 0x00000000, 0x2403049f, 0x00000000, 0x00000000, 0x00000000, 0x0760079f, 0x27040b20, 0x00000000, - 0x00000000, 0x8760879f, 0xa7048b20, 0x00000000, 0x00000000, 0x0818045a, 0x24ff3008, 0x00000000, - 0x00000000, 0x8b20075a, 0x0000a7ff, 0x00000000, 0x00000000, 0x0818045a, 0x24ff3008, 0x00000000, - 0x00000000, 0x0a18065a, 0x000026ff, 0x00000000, 0x00000000, 0x0b18075a, 0x000027ff, 0x00000000, - 0x00000000, 0x8a18065a, 0x0000a6ff, 0x00000000, 0x00000000, 0x8b20075a, 0x0000a7ff, 0x00000000, - 0x00000000, 0x402a8000, 0x00000000, 0x00000000, 0x00000000, 0x1f78a400, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 -}; - -// Start address of flash -static const uint32_t flash_start = 0x60000000; -// Size of flash -static const uint32_t flash_size = 0x00800000; - -/** -* List of start and size for each size of flash sector - even indexes are start, odd are size -* The size will apply to all sectors between the listed address and the next address -* in the list. -* The last pair in the list will have sectors starting at that address and ending -* at address flash_start + flash_size. -*/ -static const sector_info_t sectors_info[] = { - {0x60000000, 0x00001000}, -}; - -static const program_target_t flash = { - 0x20000075, // Init - 0x200000e1, // UnInit - 0x200000e5, // EraseChip - 0x200000f9, // EraseSector - 0x20000117, // ProgramPage - 0x00000000, // Verify - - // BKPT : start of blob + 1 - // RSB : blob start + header + rw data offset - // RSP : stack pointer - { - 0x20000001, - 0x20003a6c, - 0x20007d00 - }, - - // mem buffer location - 0x20007d00, - // location to write prog_blob in target RAM - 0x20000000, - // prog_blob size - sizeof(MIMXRT105x_QuadSPI_4KB_SEC_flash_prog_blob), - // address of prog_blob - MIMXRT105x_QuadSPI_4KB_SEC_flash_prog_blob, - // ram_to_flash_bytes_to_be_written - 0x00000100 -}; diff --git a/source/family/freescale/mimxrt1050_spi_flash/target.c b/source/family/freescale/mimxrt1050_spi_flash/target.c deleted file mode 100644 index c0c1aa2c7..000000000 --- a/source/family/freescale/mimxrt1050_spi_flash/target.c +++ /dev/null @@ -1,40 +0,0 @@ -/** - * @file target.c - * @brief Target information for the i.MXRT1050 (QSPI Flash) - * - * DAPLink Interface Firmware - * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "target_config.h" - -// The file flash_blob.c must only be included in target.c -#include "flash_blob.c" - -// target information -target_cfg_t target_device = { - .version = kTargetConfigVersion, - .sectors_info = sectors_info, - .sector_info_length = (sizeof(sectors_info))/(sizeof(sector_info_t)), - .flash_regions[0].start = 0x60000000, - .flash_regions[0].end = 0x60000000 + MB(8), - .flash_regions[0].flags = kRegionIsDefault, - .flash_regions[0].flash_algo = (program_target_t *) &flash, - .ram_regions[0].start = 0x20000000, - .ram_regions[0].end = 0x20000000 + KB(512), - .target_vendor = "NXP", - .target_part_number = "MIMXRT1052DVL6A", -}; diff --git a/test/info.py b/test/info.py index d650ccaa2..c32f9fb15 100644 --- a/test/info.py +++ b/test/info.py @@ -60,7 +60,6 @@ ("k20dx_hvpke18f_if", True, 0x8000, "bin" ), ("k20dx_mimxrt1020_evk_qspi_if", True, 0x8000, "bin" ), ("k20dx_mimxrt1050_evk_hyper_if", True, 0x8000, "bin" ), - ("k20dx_mimxrt1050_evk_qspi_if", True, 0x8000, "bin" ), ("lpc4322_mimxrt1060_evk_qspi_if", False, 0x10000, "bin" ), ("lpc4322_mimxrt1170_evk_qspi_if", False, 0x10000, "bin" ), ('k20dx_ep_agora_if', True, 0x0000, "bin" ), @@ -147,8 +146,7 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0224, VENDOR_TO_FAMILY('NXP', 1), 'k20dx_frdmk28f_if', 'k20dx_bl', None ), # TODO - set target to 'FRDM-K28F' when mbed-os supports this ( 0x0225, VENDOR_TO_FAMILY('NXP', 1), 'k26f_frdmk32w042_if', 'k26f_bl', None ), # TODO - set target to 'FRDM-K32W042' when mbed-os supports this ( 0x0226, VENDOR_TO_FAMILY('NXP', 3), 'k20dx_mimxrt1020_evk_qspi_if', 'k20dx_bl', 'MIMXRT1020' ), - ( 0x0227, VENDOR_TO_FAMILY('NXP', 3), 'k20dx_mimxrt1050_evk_hyper_if', 'k20dx_bl', 'MIMXRT1050-HYPER' ), - ( 0x0227, VENDOR_TO_FAMILY('NXP', 3), 'k20dx_mimxrt1050_evk_qspi_if', 'k20dx_bl', 'MIMXRT1050-QSPI' ), + ( 0x0227, VENDOR_TO_FAMILY('NXP', 3), 'k20dx_mimxrt1050_evk_hyper_if', 'k20dx_bl', 'MIMXRT1050' ), ( 0x0228, VENDOR_TO_FAMILY('NXP', 4), 'k20dx_rapid_iot_if', 'k20dx_bl', None ), # TODO - set target to 'Rapid-IoT' when mbed-os supports this ( 0x0229, VENDOR_TO_FAMILY('NXP', 3), 'lpc4322_mimxrt1060_evk_qspi_if', 'lpc4322_bl', 'MIMXRT1060' ), ( 0x0230, VENDOR_TO_FAMILY('NXP', 1), 'k20dx_frdmk20dx_if', 'k20dx_bl', 'FRDM-K20D50M' ), From d60b3e9e10326ca9700beafed730fb61dfb78718 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 9 Jun 2021 10:48:01 -0500 Subject: [PATCH 587/617] hic_docs: minor edits --- docs/hic/README.md | 2 +- docs/hic/lpc11u35.md | 2 +- docs/hic/lpc4322.md | 2 +- docs/hic/lpc55xx.md | 2 +- docs/hic/sam3u2c.md | 6 +++--- docs/hic/stm32f103xb.md | 4 ++-- 6 files changed, 9 insertions(+), 9 deletions(-) diff --git a/docs/hic/README.md b/docs/hic/README.md index 40f819c5e..3aefcfa1e 100644 --- a/docs/hic/README.md +++ b/docs/hic/README.md @@ -1,7 +1,7 @@ # HICs | HIC | Core | Freq. | RAM | ROM | USB | -|-------------------------------|:----:|---------|--------|--------|:---:| +|-------------------------------|:----:|--------:|-------:|-------:|:---:| | [k20dx](k20dx.md) | M4 | 48 MHz | 16 KB | 128 KB | FS | | [k26f](k26f.md) | M4 | 120 MHz | 256 KB | 256 KB | HS | | [kl26z](kl26z.md) | M0+ | 48 Mhz | 16 KB | 128 KB | FS | diff --git a/docs/hic/lpc11u35.md b/docs/hic/lpc11u35.md index d75598b85..706dbf3b1 100644 --- a/docs/hic/lpc11u35.md +++ b/docs/hic/lpc11u35.md @@ -22,7 +22,7 @@ Because of the flash size limitation, the presence of a ROM USB loader (also Cor | Signal | I/O | Symbol | Pin | |-------------|:---:|---------|:---:| -| SWD/JTAG | +| SWD / JTAG | | SWCLK / TCK | O | PIO0_7 | 16 | | SWDIO / TMS | I/O | PIO0_8 | 17 | | SWO / TDO | I | PIO0_9 | 18 | diff --git a/docs/hic/lpc4322.md b/docs/hic/lpc4322.md index c947d65c6..01e59ba54 100644 --- a/docs/hic/lpc4322.md +++ b/docs/hic/lpc4322.md @@ -20,7 +20,7 @@ Bootloader size is 64 KB | Signal | I/O | Symbol | Pin | |-------------|:---:|---------|:---:| -| SWD/JTAG | +| SWD / JTAG | | SWCLK / TCK | O | P1_17 | H10 | | SWDIO / TMS | I/O | P1_6 | K4 | | SWO / TDO | I | P1_14 | J8 | diff --git a/docs/hic/lpc55xx.md b/docs/hic/lpc55xx.md index b9b59a78b..c0fbd1488 100644 --- a/docs/hic/lpc55xx.md +++ b/docs/hic/lpc55xx.md @@ -26,7 +26,7 @@ Reference design is based on [MCU-Link](https://www.nxp.com/design/development-b | Signal | I/O | Symbol | Pin | |-------------|:---:|---------|:---:| -| SWD/JTAG | +| SWD / JTAG | | SWCLK / TCK | O | PIO0_0 | 36 | | SWDIO / TMS | I/O | PIO0_2 | 52 | | SWO / TDO | I | PIO0_3 | 53 | diff --git a/docs/hic/sam3u2c.md b/docs/hic/sam3u2c.md index 21e369572..57966da30 100644 --- a/docs/hic/sam3u2c.md +++ b/docs/hic/sam3u2c.md @@ -20,9 +20,9 @@ Bootloader size is 32 KB | Signal | I/O | Symbol | Pin | |-------------|:---:|---------|:---:| -| SWD/JTAG | -| SWCLK / TCK | O | PA17 | 14 | -| SWDIO / TMS | I/O | PA18 | 17 | +| SWD | +| SWCLK | O | PA17 | 14 | +| SWDIO | I/O | PA18 | 17 | | nRESET | O | PA30 | 30 | | UART | | UART TX | O | PA12 | 41 | diff --git a/docs/hic/stm32f103xb.md b/docs/hic/stm32f103xb.md index b2178b95c..13313e5b6 100644 --- a/docs/hic/stm32f103xb.md +++ b/docs/hic/stm32f103xb.md @@ -20,13 +20,13 @@ Bootloader size is 48 KB | Signal | I/O | Symbol | Pin | |-------------|:---:|---------|:---:| -| SWD/JTAG | +| SWD / JTAG | | SWCLK / TCK | O | PB13 | 26 | | SWDIO / TMS | O | PB14 | 27 | | SWDIO / TMS | I | PB12 | 25 | | SWO / TDO | I | PA10 | 31 | | nRESET | O | PB0 | 18 | -| UART (CDC) | +| UART | | UART RX | I | PA2 | 12 | | UART TX | O | PA3 | 13 | | Button | From b01bc5d304e9e91d1006fd932a71b203426bfef1 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sun, 13 Jun 2021 21:26:43 -0500 Subject: [PATCH 588/617] hic_docs: add section about J-Link OB for sam3u2c HIC --- docs/hic/sam3u2c.md | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/docs/hic/sam3u2c.md b/docs/hic/sam3u2c.md index 57966da30..56a3e343d 100644 --- a/docs/hic/sam3u2c.md +++ b/docs/hic/sam3u2c.md @@ -33,3 +33,36 @@ Bootloader size is 32 KB | HID LED | O | PA29 | 85 | | MSD LED | O | PA28 | 84 | | CDC LED | O | PA31 | 86 | + +# J-Link OB SAM3U128 + +## Warning + +The SEGGER design suggests a change to the pin assignment of the TC2050-IDC +used to debug the HIC MCU. They suggest replacing GNDDetect by power-supply +(VBus, V5), which could create a short with standard Tag-Connect cables and +SWD probes. + +## J-Link OB SAM3U128 pin assignment + +| Signal | I/O | Symbol | Pin | +|-------------|:---:|---------|:---:| +| SWD / JTAG | +| SWCLK / TCK | O | PA17 | 14 | +| SWCLK / TCK | I | PA22 | 5 | +| SWDIO / TMS | O | PA18 | 17 | +| SWDIO / TMS | I | PA15 | 12 | +| TDI | O | PA20 | 19 | +| TDI | I | PA13 | 10 | +| SWO / TDO | I | PA21 | 20 | +| nRESET | O | PA4 | 30 | +| nRESET | I | PA3 | 29 | +| UART | +| UART TX | O | PA12 | 41 | +| UART RX | I | PA11 | 40 | +| Button | +| NF-RST But. | O | PA1 | 27 | +| NF-RST But. | I | PA0 | 26 | +| LEDs | +| LED1 | O | PA29 | 85 | +| LED2 | O | PA28 | 84 | From 25b17086f213ccdd8d62c7c95b608b7cfcb20b39 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sun, 13 Jun 2021 22:48:07 -0500 Subject: [PATCH 589/617] hic_docs: add installation instructions for lpc4322 HIC --- docs/hic/lpc4322.md | 50 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/docs/hic/lpc4322.md b/docs/hic/lpc4322.md index 01e59ba54..5d64f8a34 100644 --- a/docs/hic/lpc4322.md +++ b/docs/hic/lpc4322.md @@ -34,3 +34,53 @@ Bootloader size is 64 KB | NF-RST But. | I | P2_11 | A9 | | LEDs | | LED | O | P1_1 | K2 | + +## Installation using ROM USB DFU support + +The LPC4322 has USB DFU support in ROM which can be leveraged with +[LPCScrypt](https://www.nxp.com/design/microcontrollers-developer-resources/lpcscrypt-v2-1-2:LPCSCRYPT) +to load DAPLink bootloader. + +| Board | Label | Jumper | +|------------------|----------|:------:| +| LPCXpresso55S69 | DFU | J4 | +| LPCXpresso55S28 | DFU | J4 | +| LPCXpresso55S16 | Link2 | JP6 | +| LPCXpresso55S06 | DFU | JP6 | +| LPCXpresso54628 | DFU Link | JP5 | +| LPCXpresso54618 | DFU Link | JP5 | +| LPCXpresso54608 | DFU Link | JP5 | +| LPCXpresso54114 | DFU Link | JP5 | +| LPCXpresso54102 | DFU Link | JP5 | +| LPCXpresso54S018 | DFU Link | JP5 | +| LPCXpresso54018 | DFU Link | JP5 | +| LPCXpresso43S67 | DFU Link | JP6 | +| LPCXpresso43S37 | DFU Link | JP6 | +| LPCXpresso18S37 | DFU Link | JP6 | +| LPCXpresso4367 | DFU Link | JP6 | +| LPCXpresso4337 | DFU Link | JP6 | +| LPCXpresso1125 | DFU Link | JP5 | + +Install jumper according to table above and power cycle to force into +DFU boot mode. Adapt the following command to program +`lpc4322_bl_crc.bin`. + +``` +$ ./scripts/boot_lpcscrypt +Looking for DFU devices with VID 1fc9 PID 000c ... +dfu-util -d 1fc9:000c -c 1 -i 0 -t 2048 -R -D ./scripts/../bin/LPCScrypt_240.bin.hdr +Booted LPCScrypt target (1fc9:000c) with ./scripts/../bin/LPCScrypt_240.bin.hdr +$ ./bin/lpcscrypt querypart +partID = 0xa00bcb3c 80 +decode = LPC4322: BankA 512KB +Core Clock = 180000000 +$ ./bin/lpcscrypt program ${PATH_TO_BINARY}/lpc4322_bl_crc.bin BANKA +.. +Programmed 57344 bytes to 0x1a000000 in 0.532s (105.297KB/sec) +``` + +Remove the jumper and power cycle. The `MAINTENANCE` drive should +appear and you can copy the interface firmware into it. If there is no +specific interface firmware support for the board you can use the +generic `lpc4322_if_crc.bin` interface firmware which does not offer +drag and drop flash functionality. From df8e414ffa444cb5e3ff6a1c62f1a61327585c7c Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Sat, 8 Jan 2022 01:59:33 -0600 Subject: [PATCH 590/617] hic_docs: document the number of endpoints for each HIC --- docs/hic/k20dx.md | 6 ++++-- docs/hic/k26f.md | 6 ++++-- docs/hic/kl26z.md | 6 ++++-- docs/hic/kl27z.md | 6 ++++-- docs/hic/lpc11u35.md | 6 ++++-- docs/hic/lpc4322.md | 5 ++++- docs/hic/lpc55xx.md | 6 ++++-- docs/hic/max32625.md | 7 +++++-- docs/hic/nrf52820.md | 4 +++- docs/hic/sam3u2c.md | 6 ++++-- docs/hic/stm32f103xb.md | 6 ++++-- 11 files changed, 44 insertions(+), 20 deletions(-) diff --git a/docs/hic/k20dx.md b/docs/hic/k20dx.md index 470d095e9..7bbac6f32 100644 --- a/docs/hic/k20dx.md +++ b/docs/hic/k20dx.md @@ -4,9 +4,11 @@ Based on MK20DX128VFM5 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet - Cortex-M4 50 Mhz - 160 KB Flash - 16 KB RAM -- Full-speed USB 2.0 OTG controller +- Full-speed USB 2.0 OTG controller: up to 16 bi-directional endpoints including EP0 (*) - HVQFN32 packaging +(*) "16 bidirectional endpoints can be supported" (source: [K20P32M50SF0RM :lock:](https://www.nxp.com/webapp/Download?colCode=K20P32M50SF0RM)) + ## Memory Map | Region | Size | Start | End | @@ -16,7 +18,7 @@ Based on MK20DX128VFM5 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet Bootloader size is 32 KB -## DAPLink default pin assignment +## DAPLink default pin assignment | Signal | I/O | Symbol | Pin | |-------------|:---:|---------|:---:| diff --git a/docs/hic/k26f.md b/docs/hic/k26f.md index 94cf16be5..1359cb86a 100644 --- a/docs/hic/k26f.md +++ b/docs/hic/k26f.md @@ -4,9 +4,11 @@ Based on MK26FN2M0VMI18 chip ([Data Sheet](https://www.nxp.com/docs/en/data-shee - Cortex-M4 180 Mhz - 2 MB Flash - 256 KB RAM -- High-speed USB 2.0 OTG controller +- High-speed USB 2.0 OTG controller (USBHS): up to 8 bi-directional endpoints including EP0 (**) - LFBGA169 packaging +(*) "Supports eight programmable, bidirectional USB endpoints, including endpoint 0" (source [K26P169M180SF5RM :lock:](https://www.nxp.com/webapp/Download?colCode=K26P169M180SF5RM)) + ## Memory Map | Region | Size | Start | End | @@ -16,7 +18,7 @@ Based on MK26FN2M0VMI18 chip ([Data Sheet](https://www.nxp.com/docs/en/data-shee Bootloader size is 64 KB -## DAPLink default pin assignment +## DAPLink default pin assignment | Signal | I/O | Symbol | Pin | |-------------|:---:|---------|:---:| diff --git a/docs/hic/kl26z.md b/docs/hic/kl26z.md index 777958837..c7316f045 100644 --- a/docs/hic/kl26z.md +++ b/docs/hic/kl26z.md @@ -4,9 +4,11 @@ Based on MKL26Z128VFM4 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet - Cortex-M0+ 48 Mhz - 128 KB Flash - 16 KB RAM -- Full-speed USB 2.0 OTG controller +- Full-speed USB 2.0 OTG controller: up to 16 bi-directional endpoints including EP0 (*) - HVQFN32 packaging +(*) "16 bidirectional endpoints can be supported" (source: [KL26P121M48SF4RM :lock:](https://www.nxp.com/webapp/Download?colCode=KL26P121M48SF4RM)) + ## Memory Map | Region | Size | Start | End | @@ -16,7 +18,7 @@ Based on MKL26Z128VFM4 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet Bootloader size is 32 KB -## DAPLink default pin assignment +## DAPLink default pin assignment | Signal | I/O | Symbol | Pin | |-------------|:---:|---------|:---:| diff --git a/docs/hic/kl27z.md b/docs/hic/kl27z.md index 552682d43..af82267d5 100644 --- a/docs/hic/kl27z.md +++ b/docs/hic/kl27z.md @@ -4,9 +4,11 @@ Based on MKL27Z256VFM4 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet - Cortex-M0+ 48 Mhz - 256 KB Flash - 32 KB RAM -- Full-speed USB 2.0 device controller +- Full-speed USB 2.0 device controller: up to 16 bi-directional endpoints including EP0 (*) - HVQFN32 packaging +(*) "16 bidirectional endpoints can be supported" (source: [KL27P64M48SF6RM :lock:](https://www.nxp.com/webapp/Download?colCode=KL27P64M48SF6RM)) + ## Memory Map | Region | Size | Start | End | @@ -16,7 +18,7 @@ Based on MKL27Z256VFM4 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet Bootloader size is 32 KB -## DAPLink default pin assignment +## DAPLink default pin assignment | Signal | I/O | Symbol | Pin | |-------------|:---:|---------|:---:| diff --git a/docs/hic/lpc11u35.md b/docs/hic/lpc11u35.md index 706dbf3b1..f4a1b6d82 100644 --- a/docs/hic/lpc11u35.md +++ b/docs/hic/lpc11u35.md @@ -4,9 +4,11 @@ Based on LPC11U35FHI33/501 chip ([Data Sheet](https://www.nxp.com/docs/en/data-s - Cortex-M0 48 Mhz - 64 KB Flash - 12 KB RAM -- Full-speed USB 2.0 device controller +- Full-speed USB 2.0 device controller: 5 bi-directional endpoints including EP0(*) - HVQFN32 packaging +(*) "Supports 10 physical (5 logical) endpoints including one control endpoint" (source: [Data Sheet](https://www.nxp.com/docs/en/data-sheet/LPC11U3X.pdf)) + ## Memory Map | Region | Size | Start | End | @@ -18,7 +20,7 @@ Based on LPC11U35FHI33/501 chip ([Data Sheet](https://www.nxp.com/docs/en/data-s Because of the flash size limitation, the presence of a ROM USB loader (also Cortex-M0 does not support vector table relocation). -## DAPLink default pin assignment +## DAPLink default pin assignment | Signal | I/O | Symbol | Pin | |-------------|:---:|---------|:---:| diff --git a/docs/hic/lpc4322.md b/docs/hic/lpc4322.md index 5d64f8a34..3ee988e38 100644 --- a/docs/hic/lpc4322.md +++ b/docs/hic/lpc4322.md @@ -4,9 +4,12 @@ Based on LPC4322JET100E chip ([Data Sheet](https://www.nxp.com/docs/en/data-shee - Cortex-M4 204 Mhz (currently run at 120 MHz) - 512 KB Flash - 104 KB RAM -- High-speed USB 2.0 device controller +- High-speed USB 2.0 device controller: 6 bi-directional endpoints including EP0 (*) - TFBGA100 packaging +(*) : "Supports six logical endpoints including one control endpoint for a total of 12 physical +endpoints." (source: [UM10503 :lock:](https://www.nxp.com/webapp/Download?colCode=UM10503)) + ## Memory Map | Region | Size | Start | End | diff --git a/docs/hic/lpc55xx.md b/docs/hic/lpc55xx.md index c0fbd1488..b279062fe 100644 --- a/docs/hic/lpc55xx.md +++ b/docs/hic/lpc55xx.md @@ -1,15 +1,17 @@ # lpc55xx HIC -Based on LPC55S69JBD64 chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet/LPC55S6x.pdf)): +Based on LPC55S69JBD64 chip ([Data Sheet](https://www.nxp.com/docs/en/nxp/data-sheets/LPC55S6x_DS.pdf)): - Cortex-M33 150 Mhz (cores) - 640 KB Flash - 320 KB RAM -- High-speed USB 2.0 host/device controller +- High-speed USB 2.0 host/device controller: 8 bi-directional endpoints including EP0 (*) - HTQFP64 packaging In order to support other MCUs from the LPC5500 family, the HIC limits usage to one core, 256 KB Flash and 96 KB RAM. +(*) "Supports 8 physical (16 logical) endpoints" (source: [Data Sheet](https://www.nxp.com/docs/en/nxp/data-sheets/LPC55S6x_DS.pdf)) + ## Memory Map | Region | Size | Start | End | diff --git a/docs/hic/max32625.md b/docs/hic/max32625.md index 9334baa5e..13572e16f 100644 --- a/docs/hic/max32625.md +++ b/docs/hic/max32625.md @@ -4,9 +4,12 @@ Based on MAX32625IWY+ chip ([Data Sheet](https://datasheets.maximintegrated.com/ - Cortex-M4 96 Mhz - 512 KB Flash - 160 KB RAM -- Full-speed USB 2.0 device controller +- Full-speed USB 2.0 device controller: up to 7 uni-directional endpoints excluding EP0 (*) - 63 WLP packaging +(*) "A total of 7 endpoint buffers are supported with configurable selection of IN or OUT in addition to endpoint 0." +(source: [AN6350](https://pdfserv.maximintegrated.com/en/an/AN6350.pdf)) + ## Memory Map | Region | Size | Start | End | @@ -16,7 +19,7 @@ Based on MAX32625IWY+ chip ([Data Sheet](https://datasheets.maximintegrated.com/ Bootloader size is 64 KB -## DAPLink default pin assignment +## DAPLink default pin assignment Reference design is based on [MAX32625PICO](https://www.maximintegrated.com/en/products/microcontrollers/MAX32625PICO.html). diff --git a/docs/hic/nrf52820.md b/docs/hic/nrf52820.md index 81477a81f..7e0e4e206 100644 --- a/docs/hic/nrf52820.md +++ b/docs/hic/nrf52820.md @@ -5,9 +5,11 @@ and [nRF52833](https://www.nordicsemi.com/Products/nRF52833): - Cortex-M4 64 MHz - 256 KB Flash - 32 KB RAM -- Full-speed USB 2.0 device controller +- Full-speed USB 2.0 device controller: up to 9 bi-directional endpoints including EP0 (*) - QFN40 packaging +(*) "Endpoints: 2 control (1 IN, 1 OUT) [...] 14 bulk/interrupt (7 IN, 7 OUT) [...] 2 isochronous (1 IN, 1 OUT)" (source: [Datasheet](https://infocenter.nordicsemi.com/pdf/nRF52820_OPS_v0.7.pdf)) + ## Memory Map | Region | Size | Start | End | diff --git a/docs/hic/sam3u2c.md b/docs/hic/sam3u2c.md index 56a3e343d..3ae591ca4 100644 --- a/docs/hic/sam3u2c.md +++ b/docs/hic/sam3u2c.md @@ -4,9 +4,11 @@ Based on ATSAM3U2C chip ([Datasheet](https://ww1.microchip.com/downloads/en/Devi - Cortex-M3 96 Mhz - 128 KB Flash - 36 KB RAM -- High-speed USB 2.0 device controller +- High-speed USB 2.0 device controller: up to 7 bi-directional endpoints including EP0 (*) - LQFP100 packaging +(*) "up to 7 bidirectional Endpoints" (source: Datasheet](https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6430-32-bit-Cortex-M3-Microcontroller-SAM3U4-SAM3U2-SAM3U1_Datasheet.pdf)) + ## Memory Map | Region | Size | Start | End | @@ -16,7 +18,7 @@ Based on ATSAM3U2C chip ([Datasheet](https://ww1.microchip.com/downloads/en/Devi Bootloader size is 32 KB -## DAPLink default pin assignment +## DAPLink default pin assignment | Signal | I/O | Symbol | Pin | |-------------|:---:|---------|:---:| diff --git a/docs/hic/stm32f103xb.md b/docs/hic/stm32f103xb.md index 13313e5b6..949bd8ee5 100644 --- a/docs/hic/stm32f103xb.md +++ b/docs/hic/stm32f103xb.md @@ -4,9 +4,11 @@ Based on STM32F103CBT6 chip ([Datasheet](https://www.st.com/resource/en/datashee - Cortex-M3 72 Mhz - 128 KB Flash - 20 KB RAM -- Full-speed USB 2.0 device controller +- Full-speed USB 2.0 device controller: up to 8 bi-directional endpoints including EP0 (*) - UFQFPN48 packaging +(*) "Configurable number of endpoints from 1 to 8", "up to 16 mono-directional or 8 bidirectional endpoints can be used". (source: [RM0008](https://www.st.com/resource/en/reference_manual/rm0008-stm32f101xx-stm32f102xx-stm32f103xx-stm32f105xx-and-stm32f107xx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf)) + ## Memory Map | Region | Size | Start | End | @@ -16,7 +18,7 @@ Based on STM32F103CBT6 chip ([Datasheet](https://www.st.com/resource/en/datashee Bootloader size is 48 KB -## DAPLink default pin assignment +## DAPLink default pin assignment | Signal | I/O | Symbol | Pin | |-------------|:---:|---------|:---:| From 647daee55b40ee8756e7a4a9e03ce5ffd18700ed Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 10 Jan 2022 17:55:42 -0600 Subject: [PATCH 591/617] Update flash algo for LPC55S69 (#926) --- source/family/nxp/lpc55S6X/flash_blob.c | 146 ++++++++++++++---------- 1 file changed, 83 insertions(+), 63 deletions(-) diff --git a/source/family/nxp/lpc55S6X/flash_blob.c b/source/family/nxp/lpc55S6X/flash_blob.c index 86899b3e3..030c918a5 100644 --- a/source/family/nxp/lpc55S6X/flash_blob.c +++ b/source/family/nxp/lpc55S6X/flash_blob.c @@ -1,5 +1,8 @@ -/* Flash OS Routines (Automagically Generated) - * Copyright (c) 2009-2019 ARM Limited +/* Flash algorithm for LPC55xx IAP 608kB Flash + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2022 Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -14,53 +17,65 @@ * limitations under the License. */ -static const uint32_t lpc55S69_flash_prog_blob[] = { - 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, - 0x20c8b580, 0x0002f2c4, 0x60012120, 0x6080f64f, 0x4100f240, 0x70fff6cf, 0x0100f2c4, 0x500a2200, - 0x6084f64f, 0x70fff6cf, 0x6808500a, 0x6300f04f, 0x30f8f440, 0xf64f6008, 0xf6cf5048, 0x500b70ff, - 0x6028f64f, 0x70fff6cf, 0xf243500b, 0xf2c40010, 0x68030001, 0x4380f443, 0xf8416003, 0xf04f2c80, - 0x21024080, 0xf2406001, 0xf2c0000c, 0x44480000, 0xf862f000, 0xbf182800, 0xbd802001, 0x47702000, - 0xf240b510, 0xf2c0040c, 0xf2460400, 0xeb09636c, 0xf6c60004, 0x21003365, 0x2218f44f, 0xf86cf000, - 0xbf182800, 0xeb09bd10, 0x21000004, 0x2218f44f, 0x4010e8bd, 0xb8b0f000, 0xf240b5b0, 0xf2c0050c, - 0xeb090500, 0x690a0105, 0xf2464604, 0xf6c6636c, 0x46083365, 0xf0004621, 0x2800f84f, 0xbdb0bf18, - 0x0005eb09, 0x46216902, 0x40b0e8bd, 0xb894f000, 0xb085b5f0, 0x070cf240, 0x4606460d, 0x0700f2c0, - 0x0007eb09, 0x462b4631, 0xf0004614, 0xb108f85d, 0xbdf0b005, 0xf10da804, 0x90000c0c, 0x0007eb09, - 0x462a4631, 0xf8cd4623, 0xf000c004, 0xb005f88b, 0x0000bdf0, 0xe7fdbe00, 0x1100f241, 0x3100f2c1, - 0x29006809, 0x680ad00a, 0x0308f240, 0x2207f3c2, 0x0300f2c0, 0x2003f849, 0x47086849, 0x309ef240, - 0x0000f2c0, 0x31abf240, 0x0100f2c0, 0x44794478, 0xf7ff2276, 0xbf00ffdf, 0x0c08f240, 0x0c00f2c0, - 0xc00cf859, 0x0f00f1bc, 0xf241d00b, 0xf2c11c00, 0xf8dc3c00, 0xf1bcc000, 0xd0070f00, 0xc008f8dc, - 0xf2444760, 0xf2c11c3b, 0x47603c00, 0x304ef240, 0x0000f2c0, 0x315bf240, 0x0100f2c0, 0x44794478, - 0xf7ff2286, 0xbf00ffb7, 0x0c08f240, 0x0c00f2c0, 0xc00cf859, 0x0f00f1bc, 0xf241d00b, 0xf2c11c00, - 0xf8dc3c00, 0xf1bcc000, 0xd0070f00, 0xc00cf8dc, 0xf2444760, 0xf2c11c9d, 0x47603c00, 0x20fef240, - 0x0000f2c0, 0x310bf240, 0x0100f2c0, 0x44794478, 0xf7ff2296, 0xbf00ff8f, 0x1300f241, 0x3300f2c1, - 0x2b00681b, 0x691bd001, 0xf2404718, 0xf2c020d0, 0xf2400000, 0xf2c021dd, 0x44780100, 0x229e4479, - 0xff78f7ff, 0x0c08f240, 0x0c00f2c0, 0xc00cf859, 0x0f00f1bc, 0xf241d00b, 0xf2c11c00, 0xf8dc3c00, - 0xf1bcc000, 0xd0070f00, 0xc014f8dc, 0xf2444760, 0xf2c12c7d, 0x47603c00, 0x2082f240, 0x0000f2c0, - 0x218ff240, 0x0100f2c0, 0x44794478, 0xf7ff22b2, 0xbf00ff51, 0x1300f241, 0x3300f2c1, 0x2b00681b, - 0x699bd001, 0xf2404718, 0xf2c02054, 0xf2400000, 0xf2c02161, 0x44780100, 0x22bb4479, 0xff3af7ff, - 0x1100f241, 0x3100f2c1, 0x29006809, 0x69c9d001, 0xf2404708, 0xf2c02028, 0xf2400000, 0xf2c02135, - 0x44780100, 0x22c54479, 0xff24f7ff, 0x1100f241, 0x3100f2c1, 0x29006809, 0x6a09d001, 0xf2404708, - 0xf2c010fc, 0xf2400000, 0xf2c02109, 0x44780100, 0x22cc4479, 0xff0ef7ff, 0x1100f241, 0x3100f2c1, - 0x29006809, 0xf644d004, 0xf2c11151, 0x47083100, 0x10caf240, 0x0000f2c0, 0x11d7f240, 0x0100f2c0, - 0x44794478, 0xf7ff22d2, 0xbf00fef5, 0x230bf644, 0x3300f2c1, 0xbf004718, 0x1c00f241, 0x3c00f2c1, - 0xc000f8dc, 0x0f00f1bc, 0xf8dcd002, 0x4760c040, 0x108af240, 0x0000f2c0, 0x1197f240, 0x0100f2c0, - 0x44794478, 0xf7ff22e0, 0xbf00fed5, 0x21fff644, 0x3100f2c1, 0xbf004708, 0x313df644, 0x3100f2c1, - 0xbf004708, 0x1200f241, 0x3200f2c1, 0x2a006812, 0xf644d004, 0xf2c1328b, 0x47103200, 0x103ef240, - 0x0000f2c0, 0x114bf240, 0x0100f2c0, 0x44794478, 0xf7ff22f5, 0xbf00feaf, 0x1300f241, 0x3300f2c1, - 0x2b00681b, 0x6a5bd001, 0xf2404718, 0xf2c01010, 0xf2400000, 0xf2c0111d, 0x44780100, 0x22fc4479, - 0xfe98f7ff, 0x62a7f644, 0x3200f2c1, 0xbf004710, 0x1c00f241, 0x3c00f2c1, 0xc000f8dc, 0x0f00f1bc, - 0xf8dcd002, 0x4760c02c, 0x00d2f240, 0x0000f2c0, 0x01dff240, 0x0100f2c0, 0x44794478, 0x7284f44f, - 0xfe78f7ff, 0x1200f241, 0x3200f2c1, 0x2a006812, 0x6b12d001, 0xf2404710, 0xf2c000a4, 0xf2400000, - 0xf2c001b1, 0x44780100, 0xf2404479, 0xf7ff120f, 0xbf00fe61, 0x1200f241, 0x3200f2c1, 0x2a006812, - 0x6b52d001, 0xf2404710, 0xf2c00074, 0xf2400000, 0xf2c00181, 0x44780100, 0xf44f4479, 0xf7ff728b, - 0xbf00fe49, 0x1300f241, 0x3300f2c1, 0x2b00681b, 0x6b9bd001, 0xf2404718, 0xf2c00044, 0xf2400000, - 0xf2c00151, 0x44780100, 0xf2404479, 0xf7ff121d, 0xbf00fe31, 0x6c15f644, 0x3c00f2c1, 0xbf004760, - 0x1200f241, 0x3200f2c1, 0x2a006812, 0x6a92d001, 0xf2404710, 0xf2c00008, 0xf2400000, 0xf2c00115, - 0x44780100, 0xf44f4479, 0xf7ff7295, 0x4c46fe13, 0x5f485341, 0x5f495041, 0x45455254, 0x2f2e2e00, - 0x2e2f2e2e, 0x6f732f2e, 0x65637275, 0x70786e2f, 0x63706c2f, 0x36533535, 0x73662f39, 0x61695f6c, - 0x00632e70, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +// Generated from 'LPC55XX_640.FLM' (LPC55xx IAP 608kB Flash) +// Originating from 'NXP.LPC55S69_DFP.13.1.0.pack' +// digest = c672c27550f789743829bb8832245f8c6f0c8ea81b9291b53827849eeabbe52c, file size = 22316 +// algo version = 0x101, algo size = 1696 (0x6a0) +static const uint32_t LPC55XX_640_flash_prog_blob[] = { + 0xe7fdbe00, + 0xf240b580, 0xf2c00004, 0xf6420000, 0xf84961e0, 0xf2401000, 0xf2c52000, 0x21000000, 0x1080f8c0, + 0x1084f8c0, 0x1180f8c0, 0x71fbf647, 0xf6406001, 0x21ff6004, 0x0000f2c5, 0x01def2cc, 0xf04f6001, + 0x210240a0, 0xf2407001, 0xf2c00010, 0x44480000, 0xf874f000, 0xbf182800, 0xbd802001, 0x47702000, + 0xf240b580, 0xf2c00010, 0xf2460000, 0x4448636c, 0xf6c62100, 0xf44f3365, 0xf0002218, 0x2800f87f, + 0x2001bf18, 0xbf00bd80, 0xf020b580, 0xf2404170, 0xf2c00010, 0xf2460000, 0x4448636c, 0x3365f6c6, + 0x4200f44f, 0xf86af000, 0xbf182800, 0xbd802001, 0x4614b570, 0x0441460d, 0x4670f020, 0xf240d10d, + 0xf2c00010, 0xf2460000, 0x4448636c, 0xf6c64631, 0xf44f3365, 0xf0004200, 0xf240f851, 0xf2c00010, + 0xf5b50000, 0xbf987f00, 0x7500f44f, 0x46314448, 0x462b4622, 0xf86af000, 0xbf182800, 0xbd702001, + 0x460cb5b0, 0xf0204605, 0x46114070, 0xf0004622, 0x2800fa01, 0x4425bf08, 0xbdb04628, 0x460ab580, + 0x4170f020, 0x0010f240, 0x0000f2c0, 0xf0004448, 0x2800f875, 0x2001bf18, 0x0000bd80, 0x02f4f241, + 0x3200f2c1, 0x290068d1, 0x2360d00a, 0x78926283, 0xf2406849, 0xf2c0030c, 0xf8490300, 0x47082003, + 0x40baf240, 0x0000f2c0, 0x41c7f240, 0x0100f2c0, 0x44794478, 0xf0002284, 0xbf00f98d, 0x0c0cf240, + 0x0c00f2c0, 0xc00cf859, 0x0f02f1bc, 0xf244d104, 0xf2c11c3b, 0x47603c00, 0x1c00f241, 0x3c00f2c1, + 0xc000f8dc, 0x0f00f1bc, 0xf8dcd002, 0x4760c008, 0x406af240, 0x0000f2c0, 0x4177f240, 0x0100f2c0, + 0x44794478, 0xf0002295, 0xbf00f965, 0x0c0cf240, 0x0c00f2c0, 0xc00cf859, 0x0f02f1bc, 0xf244d104, + 0xf2c11c9d, 0x47603c00, 0x1c00f241, 0x3c00f2c1, 0xc000f8dc, 0x0f00f1bc, 0xf8dcd002, 0x4760c00c, + 0x401af240, 0x0000f2c0, 0x4127f240, 0x0100f2c0, 0x44794478, 0xf00022a5, 0xbf00f93d, 0x1300f241, + 0x3300f2c1, 0x2b00681b, 0x691bd001, 0xf2404718, 0xf2c030ec, 0xf2400000, 0xf2c031f9, 0x44780100, + 0x22ad4479, 0xf926f000, 0x0c0cf240, 0x0c00f2c0, 0xc00cf859, 0x0f02f1bc, 0xf244d104, 0xf2c12c7d, + 0x47603c00, 0x1c00f241, 0x3c00f2c1, 0xc000f8dc, 0x0f00f1bc, 0xf8dcd002, 0x4760c014, 0x309ef240, + 0x0000f2c0, 0x31abf240, 0x0100f2c0, 0x44794478, 0xf00022c2, 0xbf00f8ff, 0x1300f241, 0x3300f2c1, + 0x2b00681b, 0x699bd001, 0xf2404718, 0xf2c03070, 0xf2400000, 0xf2c0317d, 0x44780100, 0x22cb4479, + 0xf8e8f000, 0x1100f241, 0x3100f2c1, 0x29006809, 0x6a89d001, 0xf2404708, 0xf2c03044, 0xf2400000, + 0xf2c03151, 0x44780100, 0x22d54479, 0xf8d2f000, 0x1100f241, 0x3100f2c1, 0x29006809, 0x6ac9d001, + 0xf2404708, 0xf2c03018, 0xf2400000, 0xf2c03125, 0x44780100, 0x22dc4479, 0xf8bcf000, 0x1300f241, + 0x3300f2c1, 0x2b00681b, 0x6b1bd001, 0xf2404718, 0xf2c020ec, 0xf2400000, 0xf2c021f9, 0x44780100, + 0x22e34479, 0xf8a6f000, 0x1200f241, 0x3200f2c1, 0x2a006812, 0x6b52d001, 0xf2404710, 0xf2c020c0, + 0xf2400000, 0xf2c021cd, 0x44780100, 0x22ea4479, 0xf890f000, 0x1c00f241, 0x3c00f2c1, 0xc000f8dc, + 0x0f00f1bc, 0xf8dcd002, 0x4760c038, 0x208ef240, 0x0000f2c0, 0x219bf240, 0x0100f2c0, 0x44794478, + 0xf00022f1, 0xbf00f877, 0x1200f241, 0x3200f2c1, 0x2a006812, 0x6bd2d001, 0xf2404710, 0xf2c02060, + 0xf2400000, 0xf2c0216d, 0x44780100, 0x22f84479, 0xf860f000, 0x1200f241, 0x3200f2c1, 0x2a006812, + 0x6c12d001, 0xf2404710, 0xf2c02034, 0xf2400000, 0xf2c02141, 0x44780100, 0x22ff4479, 0xf84af000, + 0x1300f241, 0x3300f2c1, 0x2b00681b, 0x6c5bd001, 0xf2404718, 0xf2c02008, 0xf2400000, 0xf2c02115, + 0x44780100, 0xf44f4479, 0xf0007283, 0xbf00f833, 0x1300f241, 0x3300f2c1, 0x2b00681b, 0x6c9bd001, + 0xf2404718, 0xf2c010d8, 0xf2400000, 0xf2c011e5, 0x44780100, 0xf2404479, 0xf000120d, 0xbf00f81b, + 0x1c00f241, 0x3c00f2c1, 0xc000f8dc, 0x0f00f1bc, 0xf8dcd002, 0x4760c04c, 0x10a2f240, 0x0000f2c0, + 0x11aff240, 0x0100f2c0, 0x44794478, 0x728af44f, 0xf800f000, 0x4605b50e, 0x460e4614, 0xf000a013, + 0x4628f870, 0xf86df000, 0xf000a016, 0x4630f86a, 0xf867f000, 0xf000a015, 0x2100f864, 0x100bf88d, + 0xf10d210a, 0xf88d000a, 0xe008100a, 0xf2f1fb94, 0x4212fb01, 0xf4f1fb94, 0xf8003230, 0x2c002d01, + 0xf000dcf4, 0xf000f84e, 0x0000f841, 0x202a2a2a, 0x65737361, 0x6f697472, 0x6166206e, 0x64656c69, + 0x0000203a, 0x6966202c, 0x0020656c, 0x696c202c, 0x0020656e, 0x0301ea40, 0x079bb510, 0x2a04d10f, + 0xc810d30d, 0x1f12c908, 0xd0f8429c, 0xba19ba20, 0xd9014288, 0xbd102001, 0x30fff04f, 0xb11abd10, + 0xd00307d3, 0xe0071c52, 0xbd102000, 0x3b01f810, 0x4b01f811, 0xd1071b1b, 0x3b01f810, 0x4b01f811, + 0xd1011b1b, 0xd1f11e92, 0xbd104618, 0x2000b510, 0xf81ef000, 0x8000f3af, 0x4010e8bd, 0xf0002001, + 0xb510b811, 0xe0024604, 0xf0001c64, 0x7820f804, 0xd1f92800, 0xb508bd10, 0xf88d4669, 0x20030000, + 0xbd08beab, 0x20184901, 0xe7febeab, 0x00020026, 0xf000b510, 0xe8bdf80b, 0xf0004010, 0x4770b801, + 0xd0012800, 0xbfeef7ff, 0x00004770, 0x2100b510, 0xf000a002, 0x2001f813, 0x0000bd10, 0x41474953, + 0x3a545242, 0x6e624120, 0x616d726f, 0x6574206c, 0x6e696d72, 0x6f697461, 0x0000006e, 0x4605b570, + 0x200a460c, 0x1c6de000, 0xffc5f7ff, 0x7828b135, 0xd1f82800, 0x1c64e002, 0xffbdf7ff, 0x7820b114, + 0xd1f82800, 0x4070e8bd, 0xf7ff200a, 0x4c46bfb4, 0x5f485341, 0x5f495041, 0x45455254, 0x70616900, + 0x73662f31, 0x61695f6c, 0x632e3170, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000 + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; // Start address of flash @@ -69,36 +84,41 @@ static const uint32_t flash_start = 0x00000000; static const uint32_t flash_size = 0x00098000; /** -* List of start and size for each size of flash sector +* List of start and size for each size of flash sector - even indexes are start, odd are size * The size will apply to all sectors between the listed address and the next address * in the list. * The last pair in the list will have sectors starting at that address and ending -* at address start + size. +* at address flash_start + flash_size. */ static const sector_info_t sectors_info[] = { {0x00000000, 0x00008000}, }; static const program_target_t flash = { - 0x20000021, // Init - 0x2000009d, // UnInit - 0x200000a1, // EraseChip - 0x200000d9, // EraseSector - 0x20000111, // ProgramPage - 0x0, // Verify + 0x20000005, // Init + 0x20000061, // UnInit + 0x20000065, // EraseChip + 0x2000008d, // EraseSector + 0x200000b5, // ProgramPage + 0x00000000, // Verify // BKPT : start of blob + 1 // RSB : blob start + header + rw data offset // RSP : stack pointer { 0x20000001, - 0x20000564, - 0x20000800 + 0x20000654, + 0x20001000 }, - 0x20000000 + 0x00000A00, // mem buffer location - 0x20000000, // location to write prog_blob in target RAM - sizeof(lpc55S69_flash_prog_blob), // prog_blob size - lpc55S69_flash_prog_blob, // address of prog_blob - 0x00000200 // ram_to_flash_bytes_to_be_written + // mem buffer location + 0x20001000, + // location to write prog_blob in target RAM + 0x20000000, + // prog_blob size + sizeof(LPC55XX_640_flash_prog_blob), + // address of prog_blob + LPC55XX_640_flash_prog_blob, + // ram_to_flash_bytes_to_be_written + 0x00000200 }; From be2b4f7563388dc0e22edb0e80acc36ce3fc1ba8 Mon Sep 17 00:00:00 2001 From: Carlos Pereira Atencio Date: Wed, 12 Jan 2022 05:56:50 +0000 Subject: [PATCH 592/617] microbitv2_bl: Add non-zero board ID to micro:bit DAPLink bootloader (#928) --- source/board/kl27z_microbit_bl.c | 2 +- source/board/nrf52820_microbit_bl.c | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/source/board/kl27z_microbit_bl.c b/source/board/kl27z_microbit_bl.c index bbd9fe52c..d1235660b 100644 --- a/source/board/kl27z_microbit_bl.c +++ b/source/board/kl27z_microbit_bl.c @@ -59,7 +59,7 @@ const target_family_descriptor_t *g_target_family = NULL; const board_info_t g_board_info = { .info_version = kBoardInfoVersion, - .board_id = "0000", + .board_id = "9903", .daplink_url_name = "HELP_FAQHTM", .daplink_drive_name = "MAINTENANCE", .daplink_target_url = "https://microbit.org/device/?id=@B&v=@V&bl=1", diff --git a/source/board/nrf52820_microbit_bl.c b/source/board/nrf52820_microbit_bl.c index 31f95db94..9b49a08cd 100644 --- a/source/board/nrf52820_microbit_bl.c +++ b/source/board/nrf52820_microbit_bl.c @@ -68,9 +68,11 @@ target_cfg_t target_device = { // bootloader has no family const target_family_descriptor_t *g_target_family = NULL; +// Use the 9905 board ID in the bootloader for both nRF52833 and nRF52820 +// Mainly used to identify which interface hex file to download from the micro:bit help page const board_info_t g_board_info = { .info_version = kBoardInfoVersion, - .board_id = "0000", + .board_id = "9905", .daplink_url_name = "HELP_FAQHTM", .daplink_drive_name = "MAINTENANCE", .daplink_target_url = "https://microbit.org/device/?id=@B&v=@V&bl=1", From a35b1e387e7cf642b5a11696a314aed7fc70b4e2 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 10 Jan 2022 18:20:56 -0600 Subject: [PATCH 593/617] lpc55xx_hic: Add test project MCU-LINK + nRF52840-DK --- projects.yaml | 8 ++++++ records/board/lpc55s69_nrf52840dk.yaml | 9 +++++++ source/board/lpc55s69_nrf52840dk.c | 35 ++++++++++++++++++++++++++ test/info.py | 3 +++ tools/progen_compile.py | 2 ++ 5 files changed, 57 insertions(+) create mode 100644 records/board/lpc55s69_nrf52840dk.yaml create mode 100644 source/board/lpc55s69_nrf52840dk.c diff --git a/projects.yaml b/projects.yaml index 768ef5bee..019b317a7 100644 --- a/projects.yaml +++ b/projects.yaml @@ -590,3 +590,11 @@ projects: - *module_if - *module_hic_stm32f103xb - records/board/ublox_evk_odin_w2.yaml + + + # Test projects + lpc55s69_nrf52840dk_test_if: + - *module_if + - *module_hic_lpc55s69 + - records/board/lpc55s69_nrf52840dk.yaml + - records/board/mcu_link.yaml diff --git a/records/board/lpc55s69_nrf52840dk.yaml b/records/board/lpc55s69_nrf52840dk.yaml new file mode 100644 index 000000000..da48f0674 --- /dev/null +++ b/records/board/lpc55s69_nrf52840dk.yaml @@ -0,0 +1,9 @@ +common: + macros: + - SWO_UART=1 + sources: + board: + - source/board/lpc55s69_nrf52840dk.c + family: + - source/family/nordic/nrf52/target.c + - source/family/nordic/target_reset_nrf52.c diff --git a/source/board/lpc55s69_nrf52840dk.c b/source/board/lpc55s69_nrf52840dk.c new file mode 100644 index 000000000..ae37d7d66 --- /dev/null +++ b/source/board/lpc55s69_nrf52840dk.c @@ -0,0 +1,35 @@ +/** + * @file lpc55S69_nrf52840dk.c + * @brief board file for test project MCU-LINK + nRF52840-DK + * + * DAPLink Interface Firmware + * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "target_family.h" +#include "target_board.h" + +extern target_cfg_t target_device_nrf52840; + +const board_info_t g_board_info = { + .info_version = kBoardInfoVersion, + .board_id = "1102", + .family_id = kNordic_Nrf52_FamilyID, + .flags = kEnablePageErase, + .target_cfg = &target_device_nrf52840, + .board_vendor = "Nordic Semiconductor", + .board_name = "nRF52840-DK", +}; diff --git a/test/info.py b/test/info.py index c32f9fb15..4f8487a7c 100644 --- a/test/info.py +++ b/test/info.py @@ -235,6 +235,9 @@ def VENDOR_TO_FAMILY(x, y) : return (VENDOR_ID[x] <<8) | y ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'nrf52820_if', None, None ), ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'sam3u2c_if', None, None ), ( 0x0000, VENDOR_TO_FAMILY('Stub', 1), 'stm32f103xb_if', None, None ), + + # Test projects + ( 0x1102, VENDOR_TO_FAMILY('Nordic', 2), 'lpc55s69_nrf52840dk_test_if', 'lpc55s69_bl', 'Nordic-nRF52840-DK' ), ] # Add new HICs here diff --git a/tools/progen_compile.py b/tools/progen_compile.py index ce625eb33..64a32d0e7 100755 --- a/tools/progen_compile.py +++ b/tools/progen_compile.py @@ -94,6 +94,8 @@ def get_core_count(): # musca projects are too large to fit when compiled with gcc. LTO should fix that but it does not work (yet) if 'gcc' in toolchain and args.release: project_list = list(filter(lambda p: "musca" not in p, project_list)) +# remove all test projects from list +project_list = list(filter(lambda p: not p.endswith("test_if"), project_list)) logging_level = logging.DEBUG if args.verbosity >= 2 else (logging.INFO if args.verbosity >= 1 else logging.WARNING) logging.basicConfig(format="%(asctime)s %(name)020s %(levelname)s\t%(message)s", level=logging_level) From 08d6cb507af5e3bcdc1bf90fe338449dd039f85d Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 10 Jan 2022 18:23:22 -0600 Subject: [PATCH 594/617] lpc55xx_hic: Partial revert of "LPC55xx: Improve UART TX performance." This reverts commit 50ed535e44180e90cc5e5b64e8118f143b37e28f for source/hic_hal/nxp/lpc55xx/uart.c --- source/hic_hal/nxp/lpc55xx/uart.c | 47 ++++++++++++------------------- 1 file changed, 18 insertions(+), 29 deletions(-) diff --git a/source/hic_hal/nxp/lpc55xx/uart.c b/source/hic_hal/nxp/lpc55xx/uart.c index f24bf48cf..e0e272420 100644 --- a/source/hic_hal/nxp/lpc55xx/uart.c +++ b/source/hic_hal/nxp/lpc55xx/uart.c @@ -50,6 +50,7 @@ struct { volatile uint32_t tx_size; uint8_t rx; + uint8_t tx; } cb_buf; void uart_handler(uint32_t event); @@ -192,41 +193,23 @@ int32_t uart_write_free(void) return circ_buf_count_free(&write_buffer); } -// Start a new TX transfer if there are bytes pending to be transferred on the -// write_buffer buffer. The transferred bytes are not removed from the circular -// by this function, only the event handler will remove them once the transfer -// is done. -static void uart_start_tx_transfer() { - uint32_t tx_size = 0; - const uint8_t* buf = circ_buf_peek(&write_buffer, &tx_size); - if (tx_size > BUFFER_SIZE / 4) { - // The bytes being transferred remain on the circular buffer memory - // until the transfer is done. Limiting the UART transfer size - // allows the uart_handler to clear those bytes earlier. - tx_size = BUFFER_SIZE / 4; - } - cb_buf.tx_size = tx_size; - if (tx_size) { - USART_INSTANCE.Send(buf, tx_size); - } -} - int32_t uart_write_data(uint8_t *data, uint16_t size) { if (size == 0) { return 0; } + // Disable interrupts to prevent the uart_handler from modifying the + // circular buffer at the same time. + NVIC_DisableIRQ(USART_IRQ); uint32_t cnt = circ_buf_write(&write_buffer, data, size); - if (cb_buf.tx_size == 0) { - // There's no pending transfer and the value of cb_buf.tx_size will not - // change to non-zero by the event handler once it is zero. Note that it - // is entirely possible that we transferred all the bytes we added to - // the circular buffer in this function by the time we are in this - // branch, in that case uart_start_tx_transfer() would not schedule any - // transfer. - uart_start_tx_transfer(); + if (cb_buf.tx_size == 0 && circ_buf_count_used(&write_buffer) > 0) { + // There's no pending transfer, so we need to start the process. + cb_buf.tx = circ_buf_pop(&write_buffer); + USART_INSTANCE.Send(&(cb_buf.tx), 1); + cb_buf.tx_size = 1; } + NVIC_EnableIRQ(USART_IRQ); return cnt; } @@ -250,7 +233,13 @@ void uart_handler(uint32_t event) { } if (event & ARM_USART_EVENT_SEND_COMPLETE) { - circ_buf_pop_n(&write_buffer, cb_buf.tx_size); - uart_start_tx_transfer(); + if (circ_buf_count_used(&write_buffer) > 0) { + cb_buf.tx = circ_buf_pop(&write_buffer); + USART_INSTANCE.Send(&(cb_buf.tx), 1); + } else { + // Signals that next call to uart_write_data() should start a + // transfer. + cb_buf.tx_size = 0; + } } } From bc3e5a028db236376f2796af7e9c1bfa1b765f20 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Mon, 10 Jan 2022 18:31:56 -0600 Subject: [PATCH 595/617] lpc55xx_hic: Reduce CPU clock to 96 MHz due to flash writing constraints --- docs/hic/README.md | 2 +- docs/hic/lpc55xx.md | 2 +- records/hic_hal/lpc55s69.yaml | 2 +- source/hic_hal/nxp/lpc55xx/hic_init.c | 13 ++++++++----- 4 files changed, 11 insertions(+), 8 deletions(-) diff --git a/docs/hic/README.md b/docs/hic/README.md index 3aefcfa1e..6447e1ab7 100644 --- a/docs/hic/README.md +++ b/docs/hic/README.md @@ -8,7 +8,7 @@ | [kl27z](kl27z.md) | M0+ | 48 Mhz | 32 KB | 128 KB | FS | | [lpc11u35](lpc11u35.md) | M0 | 48 Mhz | 12 KB | 64 KB | FS | | [lpc4322](lpc4322.md) | M4 | 120 MHz | 256 KB | 256 KB | HS | -| [lpc55xx](lpc55xx.md) | M33 | 150 MHz | 272 KB | 320 KB | HS | +| [lpc55xx](lpc55xx.md) | M33 | 96 MHz | 272 KB | 320 KB | HS | | [max32625](max32625.md) | M4 | 96 MHz | 160 KB | 512 KB | FS | | [nrf52820](nrf52820.md) | M4 | 64 MHz | 32 KB | 256 KB | FS | | [sam3u2c](sam3u2c.md) | M3 | 96 MHz | 32 KB | 128 KB | HS | diff --git a/docs/hic/lpc55xx.md b/docs/hic/lpc55xx.md index b279062fe..1c6804ff7 100644 --- a/docs/hic/lpc55xx.md +++ b/docs/hic/lpc55xx.md @@ -1,7 +1,7 @@ # lpc55xx HIC Based on LPC55S69JBD64 chip ([Data Sheet](https://www.nxp.com/docs/en/nxp/data-sheets/LPC55S6x_DS.pdf)): -- Cortex-M33 150 Mhz (cores) +- Cortex-M33 96 MHz (2 cores up to 150 Mhz) - 640 KB Flash - 320 KB RAM - High-speed USB 2.0 host/device controller: 8 bi-directional endpoints including EP0 (*) diff --git a/records/hic_hal/lpc55s69.yaml b/records/hic_hal/lpc55s69.yaml index 3400804cf..14b2aafb5 100644 --- a/records/hic_hal/lpc55s69.yaml +++ b/records/hic_hal/lpc55s69.yaml @@ -7,7 +7,7 @@ common: - INTERFACE_LPC55XX - CPU_LPC55S69JBD64_cm33_core0 - DAPLINK_HIC_ID=0x4C504355 # DAPLINK_HIC_ID_LPC55XX - - OS_CLOCK=150000000 + - OS_CLOCK=96000000 includes: - source/hic_hal/nxp/lpc55xx - source/hic_hal/nxp/lpc55xx/LPC55S69 diff --git a/source/hic_hal/nxp/lpc55xx/hic_init.c b/source/hic_hal/nxp/lpc55xx/hic_init.c index a3afbfa3e..6a717a756 100644 --- a/source/hic_hal/nxp/lpc55xx/hic_init.c +++ b/source/hic_hal/nxp/lpc55xx/hic_init.c @@ -172,11 +172,14 @@ void sdk_init(void) //! - Configure the USB PHY and USB1 clocks. void hic_enable_usb_clocks(void) { - // For the interface, switch to 150 MHz before enabling USB. The bootloader will stay at 96 MHz - // so it can always write internal flash. -#if defined(DAPLINK_IF) - BOARD_BootClockPLL150M(); -#endif + // Switching to 150 MHz for interface is disabled because it prevents + // interface from writing configuration and updating bootloader. + // #if defined(DAPLINK_IF) + // // For the interface, switch to 150 MHz before enabling USB. + // // The bootloader will stay at 96 MHz so it can always write + // // internal flash. + // BOARD_BootClockPLL150M(); + // #endif NVIC_ClearPendingIRQ(USB1_IRQn); NVIC_ClearPendingIRQ(USB1_NEEDCLK_IRQn); From 335320f65691bd6b147ff3d5cd0b6cadda439330 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 12 Jan 2022 19:00:51 -0600 Subject: [PATCH 596/617] nrf52820_hic: Revert "Improve UART TX performance" for nrf52820 (#930) --- source/hic_hal/nordic/nrf52820/uart.c | 47 ++++++++++----------------- 1 file changed, 18 insertions(+), 29 deletions(-) diff --git a/source/hic_hal/nordic/nrf52820/uart.c b/source/hic_hal/nordic/nrf52820/uart.c index 467b1330a..e3b5fe83c 100644 --- a/source/hic_hal/nordic/nrf52820/uart.c +++ b/source/hic_hal/nordic/nrf52820/uart.c @@ -52,6 +52,7 @@ struct { volatile uint32_t tx_size; uint8_t rx; + uint8_t tx; } cb_buf; void uart_handler(uint32_t event); @@ -207,41 +208,23 @@ int32_t uart_write_free(void) return circ_buf_count_free(&write_buffer); } -// Start a new TX transfer if there are bytes pending to be transferred on the -// write_buffer buffer. The transferred bytes are not removed from the circular -// by this function, only the event handler will remove them once the transfer -// is done. -static void uart_start_tx_transfer() { - uint32_t tx_size = 0; - const uint8_t* buf = circ_buf_peek(&write_buffer, &tx_size); - if (tx_size > BUFFER_SIZE / 4) { - // The bytes being transferred remain on the circular buffer memory - // until the transfer is done. Limiting the UART transfer size - // allows the uart_handler to clear those bytes earlier. - tx_size = BUFFER_SIZE / 4; - } - cb_buf.tx_size = tx_size; - if (tx_size) { - USART_INSTANCE.Send(buf, tx_size); - } -} - int32_t uart_write_data(uint8_t *data, uint16_t size) { if (size == 0) { return 0; } + // Disable interrupts to prevent the uart_handler from modifying the + // circular buffer at the same time. + NVIC_DisableIRQ(USART_IRQ); uint32_t cnt = circ_buf_write(&write_buffer, data, size); - if (cb_buf.tx_size == 0) { - // There's no pending transfer and the value of cb_buf.tx_size will not - // change to non-zero by the event handler once it is zero. Note that it - // is entirely possible that we transferred all the bytes we added to - // the circular buffer in this function by the time we are in this - // branch, in that case uart_start_tx_transfer() would not schedule any - // transfer. - uart_start_tx_transfer(); + if (cb_buf.tx_size == 0 && circ_buf_count_used(&write_buffer) > 0) { + // There's no pending transfer, so we need to start the process. + cb_buf.tx = circ_buf_pop(&write_buffer); + USART_INSTANCE.Send(&(cb_buf.tx), 1); + cb_buf.tx_size = 1; } + NVIC_EnableIRQ(USART_IRQ); return cnt; } @@ -265,7 +248,13 @@ void uart_handler(uint32_t event) { } if (event & ARM_USART_EVENT_SEND_COMPLETE) { - circ_buf_pop_n(&write_buffer, cb_buf.tx_size); - uart_start_tx_transfer(); + if (circ_buf_count_used(&write_buffer) > 0) { + cb_buf.tx = circ_buf_pop(&write_buffer); + USART_INSTANCE.Send(&(cb_buf.tx), 1); + } else { + // Signals that next call to uart_write_data() should start a + // transfer. + cb_buf.tx_size = 0; + } } } From 9b90cbf47a8edfc56a4b3ed4cc9959ff59476e25 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 12 Jan 2022 22:18:15 -0600 Subject: [PATCH 597/617] nrf52820_hic: add uart_reset() call to clear spurious interrupts --- source/hic_hal/nordic/nrf52820/uart.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/source/hic_hal/nordic/nrf52820/uart.c b/source/hic_hal/nordic/nrf52820/uart.c index e3b5fe83c..5bac440cd 100644 --- a/source/hic_hal/nordic/nrf52820/uart.c +++ b/source/hic_hal/nordic/nrf52820/uart.c @@ -187,6 +187,8 @@ int32_t uart_set_configuration(UART_Configuration *config) NVIC_ClearPendingIRQ(USART_IRQ); NVIC_EnableIRQ(USART_IRQ); + uart_reset(); + return 1; } From ebfa1cbea81f5d7e64d2d59efa9e6227a2317667 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Wed, 12 Jan 2022 22:39:27 -0600 Subject: [PATCH 598/617] Add option to allow test program in release builds --- test/info.py | 10 ++++++++-- tools/package_release_files.py | 6 +++--- tools/progen_compile.py | 10 +++++++--- 3 files changed, 18 insertions(+), 8 deletions(-) diff --git a/test/info.py b/test/info.py index 4f8487a7c..d209e685c 100644 --- a/test/info.py +++ b/test/info.py @@ -20,7 +20,7 @@ # Name of all projects ready for public release # and info on the file to be distributed -PROJECT_RELEASE_INFO = { +PROJECT_RELEASE_INFO = [ # Project Name Legacy Offset Extension ("k20dx_frdmk22f_if", True, 0x8000, "bin" ), ("k20dx_frdmk64f_if", True, 0x5000, "bin" ), @@ -109,7 +109,13 @@ ('sam3u2c_if', False, 0x0000, "bin" ), ('stm32f103xb_if', False, 0x0000, "bin" ), ('lpc11u35_pitaya_link_if', False, 0x0000, "bin" ), -} +] + +TEST_RELEASE_INFO = [ + ('lpc55s69_nrf52840dk_test_if', False, 0x10000, "bin" ), + ('stm32f103xb_stm32f207zg_if', False, 0x0000, "bin" ), +] + # Add new HICs here VENDOR_ID = { diff --git a/tools/package_release_files.py b/tools/package_release_files.py index 14ce0f3b4..7d9cef330 100644 --- a/tools/package_release_files.py +++ b/tools/package_release_files.py @@ -204,9 +204,9 @@ def package_release_files(source, dest, version, toolchain, release_info, suppor parser.add_argument('dest', help='Directory to create and place files in') parser.add_argument('version', type=int, help='Version number of this release') parser.add_argument('--toolchain', type=str, default='', help='Toolchain directory if present') + parser.add_argument('--test', dest='test', action='store_true', help='Add test binaries to release') args = parser.parse_args() - print("args", args.source, args.dest, args.version, args.toolchain) - + release_info = info.PROJECT_RELEASE_INFO + (info.TEST_RELEASE_INFO if args.test else []) package_release_files(args.source, args.dest, args.version, args.toolchain, - info.PROJECT_RELEASE_INFO, info.SUPPORTED_CONFIGURATIONS) + release_info, info.SUPPORTED_CONFIGURATIONS) \ No newline at end of file diff --git a/tools/progen_compile.py b/tools/progen_compile.py index 64a32d0e7..06e60b121 100755 --- a/tools/progen_compile.py +++ b/tools/progen_compile.py @@ -65,6 +65,7 @@ def get_core_count(): parser.add_argument('--release', dest='release', action='store_true', help='Create a release with the yaml version file') parser.add_argument('--release-folder', type=str, default='firmware', help='Directory to create and place files in') parser.add_argument('--supported', dest='supported', action='store_true', help='Generate the images with official identifiers') +parser.add_argument('--test', dest='test', action='store_true', help='Add test binaries to release') parser.add_argument('--toolchain', '-t', type=str, help='Toolchain (default: make_gcc_arm)') parser.add_argument('--generator', '-g', type=str, help='CMake Toolchain Generator (default: make)') parser.add_argument('--clean', dest='clean', action='store_true', help='Rebuild or delete build folder before compile') @@ -95,7 +96,8 @@ def get_core_count(): if 'gcc' in toolchain and args.release: project_list = list(filter(lambda p: "musca" not in p, project_list)) # remove all test projects from list -project_list = list(filter(lambda p: not p.endswith("test_if"), project_list)) +if not args.test: + project_list = list(filter(lambda p: not p.endswith("test_if"), project_list)) logging_level = logging.DEBUG if args.verbosity >= 2 else (logging.INFO if args.verbosity >= 1 else logging.WARNING) logging.basicConfig(format="%(asctime)s %(name)020s %(levelname)s\t%(message)s", level=logging_level) @@ -141,7 +143,7 @@ def get_core_count(): # Generate images with boardid / familyid for supported configurations if args.release or args.supported: sys.path.append(os.path.join(daplink_dir, "test")) - from info import SUPPORTED_CONFIGURATIONS, PROJECT_RELEASE_INFO + from info import SUPPORTED_CONFIGURATIONS, PROJECT_RELEASE_INFO, TEST_RELEASE_INFO id_map = {} for board_id, family_id, firmware, bootloader, target in SUPPORTED_CONFIGURATIONS: if firmware in id_map: @@ -183,5 +185,7 @@ def get_core_count(): logger.info("Deleting: %s" % release_dir) shutil.rmtree(release_dir, ignore_errors=True) logger.info("Releasing directory: %s" % release_dir) + + release_info = PROJECT_RELEASE_INFO + (TEST_RELEASE_INFO if args.test else []) package_release_files("build", release_dir, release_version, "projectfiles/" + toolchain, - PROJECT_RELEASE_INFO, SUPPORTED_CONFIGURATIONS) + release_info, SUPPORTED_CONFIGURATIONS) From a2e6e46a24047696502dbea9bb6e746be463abf0 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Fri, 24 Dec 2021 00:04:13 +0000 Subject: [PATCH 599/617] microbitv2: Refactory board id and Kl27 timer code into their own files. This should result in no change in behaviour. --- records/board/kl27z_microbit_bl.yaml | 2 + records/board/nrf52820_microbit_bl.yaml | 2 + source/board/kl27z_microbit_bl.c | 3 +- source/board/microbitv2/board_id.h | 53 +++++++ source/board/microbitv2/kl27z/board_id.c | 95 +++++++++++++ source/board/microbitv2/kl27z/pwr_mon.c | 24 ++-- source/board/microbitv2/kl27z/timer_wait.c | 70 ++++++++++ source/board/microbitv2/kl27z/timer_wait.h | 33 +++++ source/board/microbitv2/microbitv2.c | 146 ++------------------ source/board/microbitv2/microbitv2.h | 3 - source/board/microbitv2/nrf52820/board_id.c | 34 +++++ source/board/nrf52820_microbit_bl.c | 5 +- 12 files changed, 314 insertions(+), 156 deletions(-) create mode 100644 source/board/microbitv2/board_id.h create mode 100644 source/board/microbitv2/kl27z/board_id.c create mode 100644 source/board/microbitv2/kl27z/timer_wait.c create mode 100644 source/board/microbitv2/kl27z/timer_wait.h create mode 100644 source/board/microbitv2/nrf52820/board_id.c diff --git a/records/board/kl27z_microbit_bl.yaml b/records/board/kl27z_microbit_bl.yaml index da46b813a..0d16d4118 100644 --- a/records/board/kl27z_microbit_bl.yaml +++ b/records/board/kl27z_microbit_bl.yaml @@ -1,6 +1,8 @@ common: macros: - MICROBIT_LOCK_BOOTLOADER + includes: + - source/board/microbitv2/board_id.h sources: board: - source/board/kl27z_microbit_bl.c diff --git a/records/board/nrf52820_microbit_bl.yaml b/records/board/nrf52820_microbit_bl.yaml index 4bd996c64..902d0544c 100644 --- a/records/board/nrf52820_microbit_bl.yaml +++ b/records/board/nrf52820_microbit_bl.yaml @@ -1,4 +1,6 @@ common: + includes: + - source/board/microbitv2/board_id.h sources: board: - source/board/nrf52820_microbit_bl.c diff --git a/source/board/kl27z_microbit_bl.c b/source/board/kl27z_microbit_bl.c index d1235660b..75bf4c003 100644 --- a/source/board/kl27z_microbit_bl.c +++ b/source/board/kl27z_microbit_bl.c @@ -26,6 +26,7 @@ #include "target_family.h" #include "fsl_device_registers.h" #include "gpio.h" +#include "board_id.h" // Warning - changing the interface start will break backwards compatibility COMPILER_ASSERT(DAPLINK_ROM_IF_START == KB(32)); @@ -59,7 +60,7 @@ const target_family_descriptor_t *g_target_family = NULL; const board_info_t g_board_info = { .info_version = kBoardInfoVersion, - .board_id = "9903", + .board_id = BOARD_ID_MB_2_DEFAULT, .daplink_url_name = "HELP_FAQHTM", .daplink_drive_name = "MAINTENANCE", .daplink_target_url = "https://microbit.org/device/?id=@B&v=@V&bl=1", diff --git a/source/board/microbitv2/board_id.h b/source/board/microbitv2/board_id.h new file mode 100644 index 000000000..cf992caf6 --- /dev/null +++ b/source/board/microbitv2/board_id.h @@ -0,0 +1,53 @@ +/** + * @file board_id.h + * @brief + * + * DAPLink Interface Firmware + * Copyright 2021 Micro:bit Educational Foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef BOARD_ID_H_ +#define BOARD_ID_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define BOARD_ID_MB_2_DEFAULT "9903" +#define BOARD_ID_MB_2_0 "9904" +#define BOARD_ID_MB_2_2_833 "9905" +#define BOARD_ID_MB_2_2_820 "9906" + +typedef enum { + BOARD_VERSION_2_DEF = 0x9903, + BOARD_VERSION_2_0 = 0x9904, + BOARD_VERSION_2_2_833 = 0x9905, + BOARD_VERSION_2_2_820 = 0x9906, +} mb_version_t; + + +/** + * Determines the micro:bit board ID based on on-board components configured + * differently between versions. + */ +mb_version_t board_id_detect(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_ID_H_ */ diff --git a/source/board/microbitv2/kl27z/board_id.c b/source/board/microbitv2/kl27z/board_id.c new file mode 100644 index 000000000..2a75c5cf5 --- /dev/null +++ b/source/board/microbitv2/kl27z/board_id.c @@ -0,0 +1,95 @@ +/** + * @file board_id.c + * @brief + * + * DAPLink Interface Firmware + * Copyright 2020 NXP + * Copyright 2021 Micro:bit Educational Foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "IO_Config.h" + +#include "board_id.h" +#include "timer_wait.h" + +#include "adc.h" +#include "fsl_port.h" +#include "fsl_gpio.h" + +#define BRD_ID_1_UPPER_THR_V 935 // Upper threshold in mV for 100nF and 4700R +#define BRD_ID_1_LOWER_THR_V 268 // Lower threshold in mV for 100nF and 4700R + +// Board Rev ID detection. Reads BRD_REV_ID voltage +// Depends on gpio_init() to have been executed already +mb_version_t board_id_detect() +{ + gpio_pin_config_t pin_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 0U + }; + uint32_t board_rev_id_adc = 0; + uint32_t board_rev_id_mv = 0; + + // Set Board Rev ID pin as output but pin disabled + PORT_SetPinMux(PIN_BOARD_REV_ID_PORT , PIN_BOARD_REV_ID_BIT, kPORT_PinDisabledOrAnalog); + PORT_SetPinDriveStrength(PIN_BOARD_REV_ID_PORT, PIN_BOARD_REV_ID_BIT, kPORT_HighDriveStrength); + GPIO_PinInit(PIN_BOARD_REV_ID_GPIO, PIN_BOARD_REV_ID_BIT, &pin_config); + + adc_init(); + timer_wait_init(); + + // 1. Discharge capacitor + /* Set timer period 3ms*/ + timer_wait_set_period(3000); + /* Drive BRD_REV_ID pin to low */ + GPIO_PortClear(PIN_BOARD_REV_ID_GPIO, PIN_BOARD_REV_ID); + PORT_SetPinMux(PIN_BOARD_REV_ID_PORT , PIN_BOARD_REV_ID_BIT, kPORT_MuxAsGpio); + /* Wait 3ms to allow the 100nF Cap to discharge at least 5*RC with 4700R */ + timer_wait(); + + // 2. Charge capacitor for 100us + /* Set timer period slightly below 100us to account for overheads */ + timer_wait_set_period(98); + /* Drive BRD_REV_ID pin to high */ + GPIO_PortSet(PIN_BOARD_REV_ID_GPIO, PIN_BOARD_REV_ID); + /* Wait for ~100us */ + timer_wait(); + /* Change pin to ADC (High-Z). Capacitor will stop charging */ + PORT_SetPinMux(PIN_BOARD_REV_ID_PORT , PIN_BOARD_REV_ID_BIT, kPORT_PinDisabledOrAnalog); + + // 3. Take ADC measurement + board_rev_id_adc = adc_read_channel(0, PIN_BOARD_REV_ID_ADC_CH, PIN_BOARD_REV_ID_ADC_MUX); + board_rev_id_mv = board_rev_id_adc * 3300 / 0xFFF; // Convert ADC 12-bit value to mV with 3.3V reference + + // 4. Discharge capacitor + /* Set timer period 3ms */ + timer_wait_set_period(3000); + /* Drive BRD_REV_ID pin to low */ + GPIO_PortClear(PIN_BOARD_REV_ID_GPIO, PIN_BOARD_REV_ID); + PORT_SetPinMux(PIN_BOARD_REV_ID_PORT , PIN_BOARD_REV_ID_BIT, kPORT_MuxAsGpio); + /* Wait 3ms to allow the 100nF Cap to discharge at least 5*RC with 4700R */ + timer_wait(); + + // 5. Identify board ID depending on voltage + mb_version_t board_version; + if (board_rev_id_mv > BRD_ID_1_LOWER_THR_V && board_rev_id_mv < BRD_ID_1_UPPER_THR_V) { + board_version = BOARD_VERSION_2_0; + } else { + board_version = BOARD_VERSION_2_DEF; + } + + return board_version; +} diff --git a/source/board/microbitv2/kl27z/pwr_mon.c b/source/board/microbitv2/kl27z/pwr_mon.c index f433293a4..e644c2ee9 100644 --- a/source/board/microbitv2/kl27z/pwr_mon.c +++ b/source/board/microbitv2/kl27z/pwr_mon.c @@ -20,6 +20,8 @@ */ #include "pwr_mon.h" +#include "timer_wait.h" + #include "adc.h" #include "fsl_adc16.h" #include "fsl_pmc.h" @@ -39,10 +41,6 @@ static void pwr_mon_bandgap_init(void); static uint32_t pwr_mon_read_vbg(uint32_t channelGroup); static uint32_t pwr_mon_adc_to_mv(uint32_t raw_adc); -void TPM0_IRQHandler(void); - -extern volatile bool tpmIsrFlag; -extern uint32_t tpm_source_clock; void pwr_mon_init(void) { @@ -50,9 +48,10 @@ void pwr_mon_init(void) .pinDirection = kGPIO_DigitalOutput, .outputLogic = 0U }; - + adc_init(); - + timer_wait_init(); + // Configure VMON_BAT and RUN_VBAT_SENSE GPIO_PinInit(PIN_RUN_VBAT_SENSE_GPIO, PIN_RUN_VBAT_SENSE_BIT, &pin_config); PORT_SetPinMux(PIN_RUN_VBAT_SENSE_PORT, PIN_RUN_VBAT_SENSE_BIT, kPORT_MuxAsGpio); @@ -90,23 +89,22 @@ power_source_t pwr_mon_get_power_source(void) { return power_source; } -uint32_t pwr_mon_get_vbat_mv(void) { +uint32_t pwr_mon_get_vbat_mv(void) +{ /* Set timer period 3ms*/ - TPM_SetTimerPeriod(TPM0, USEC_TO_COUNT(3000U, tpm_source_clock)); + timer_wait_set_period(3000); // Enable voltage divider to take measurement GPIO_PinWrite(PIN_RUN_VBAT_SENSE_GPIO, PIN_RUN_VBAT_SENSE_BIT, 1); // Add a ~3ms delay to allow the 100nF capacitors to charge to about 3*RC. - TPM_StartTimer(TPM0, kTPM_SystemClock); - while (false == tpmIsrFlag); - tpmIsrFlag = false; + timer_wait(); uint32_t bat_adc = adc_read_channel(0, PIN_VMON_BAT_ADC_CH, PIN_VMON_BAT_ADC_MUX); // Disable voltage divider GPIO_PinWrite(PIN_RUN_VBAT_SENSE_GPIO, PIN_RUN_VBAT_SENSE_BIT, 0); - + // Compensate for voltage divider with ratio of 11 bat_adc = bat_adc * 11; - + return pwr_mon_adc_to_mv(bat_adc); } diff --git a/source/board/microbitv2/kl27z/timer_wait.c b/source/board/microbitv2/kl27z/timer_wait.c new file mode 100644 index 000000000..eeed47484 --- /dev/null +++ b/source/board/microbitv2/kl27z/timer_wait.c @@ -0,0 +1,70 @@ +/** + * @file timer_wait.c + * @brief + * + * DAPLink Interface Firmware + * Copyright 2021 Micro:bit Educational Foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "timer_wait.h" + +#include "fsl_device_registers.h" +#include "fsl_tpm.h" + + +static volatile bool tpmIsrFlag = false; +static uint32_t tpm_source_clock; + + +void TPM0_IRQHandler(void) +{ + /* Clear interrupt flag.*/ + TPM_ClearStatusFlags(TPM0, kTPM_TimeOverflowFlag); + tpmIsrFlag = true; + TPM_StopTimer(TPM0); + __DSB(); +} + +void timer_wait_init(void) +{ + /* Select the clock source for the TPM counter as kCLOCK_McgIrc48MClk */ + CLOCK_SetTpmClock(1U); + + tpm_config_t tpmInfo; + TPM_GetDefaultConfig(&tpmInfo); + /* TPM clock divide by TPM_PRESCALER */ + tpmInfo.prescale = kTPM_Prescale_Divide_4; + /* Initialize TPM module */ + TPM_Init(TPM0, &tpmInfo); + + TPM_EnableInterrupts(TPM0, kTPM_TimeOverflowInterruptEnable); + EnableIRQ(TPM0_IRQn); + + tpm_source_clock = (CLOCK_GetFreq(kCLOCK_McgIrc48MClk) / 4); + tpmIsrFlag = false; +} + +void timer_wait_set_period(uint32_t microsec) +{ + TPM_SetTimerPeriod(TPM0, USEC_TO_COUNT(microsec, tpm_source_clock)); +} + +void timer_wait(void) +{ + TPM_StartTimer(TPM0, kTPM_SystemClock); + while (false == tpmIsrFlag); + tpmIsrFlag = false; +} diff --git a/source/board/microbitv2/kl27z/timer_wait.h b/source/board/microbitv2/kl27z/timer_wait.h new file mode 100644 index 000000000..725484931 --- /dev/null +++ b/source/board/microbitv2/kl27z/timer_wait.h @@ -0,0 +1,33 @@ +/** + * @file timer_wait.h + * @brief + * + * DAPLink Interface Firmware + * Copyright 2021 Micro:bit Educational Foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef TIMER_WAIT_H_ +#define TIMER_WAIT_H_ + +#include + + +void timer_wait_init(void); +void timer_wait_set_period(uint32_t microsec); +void timer_wait(void); + + +#endif /* TIMER_WAIT_H_ */ diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 81f258c49..c6160f84f 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -5,6 +5,7 @@ * DAPLink Interface Firmware * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved * Copyright 2020 NXP + * Copyright 2021 Micro:bit Educational Foundation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -41,43 +42,13 @@ #include "led_error_app.h" #include "storage.h" #include "gpio_extra.h" - -#if defined(INTERFACE_KL27Z) - -#include "adc.h" -#include "fsl_port.h" -#include "fsl_gpio.h" -#include "fsl_tpm.h" - -volatile bool tpmIsrFlag = false; -uint32_t tpm_source_clock; - -void TPM0_IRQHandler(void) -{ - /* Clear interrupt flag.*/ - TPM_ClearStatusFlags(TPM0, kTPM_TimeOverflowFlag); - tpmIsrFlag = true; - TPM_StopTimer(TPM0); - __DSB(); -} -#endif +#include "board_id.h" #ifdef DRAG_N_DROP_SUPPORT #include "flash_intf.h" #endif -const char * const board_id_mb_2_default = "9903"; -const char * const board_id_mb_2_0 = "9904"; -const char * const board_id_mb_2_2_833 = "9905"; -const char * const board_id_mb_2_2_820 = "9906"; - -typedef enum { - BOARD_VERSION_2_DEF = 0x9903, - BOARD_VERSION_2_0 = 0x9904, - BOARD_VERSION_2_2_833 = 0x9905, - BOARD_VERSION_2_2_820 = 0x9906, -} mb_version_t; - +// Declared in intelhex.c uint16_t board_id_hex_default = BOARD_VERSION_2_DEF; uint16_t board_id_hex = BOARD_VERSION_2_DEF; @@ -110,124 +81,25 @@ static uint16_t gpio_reset_count = 0; // button state static uint8_t reset_pressed = 0; -#if defined(INTERFACE_KL27Z) -// Board Rev ID detection. Reads BRD_REV_ID voltage -// Depends on gpio_init() to have been executed already -static mb_version_t read_brd_rev_id(void) { - gpio_pin_config_t pin_config = { - .pinDirection = kGPIO_DigitalOutput, - .outputLogic = 0U - }; - mb_version_t board_version = BOARD_VERSION_2_DEF; - uint32_t board_rev_id_adc = 0; - uint32_t board_rev_id_mv = 0; - - tpm_config_t tpmInfo; - - /* Select the clock source for the TPM counter as kCLOCK_McgIrc48MClk */ - CLOCK_SetTpmClock(1U); - - TPM_GetDefaultConfig(&tpmInfo); - - /* TPM clock divide by TPM_PRESCALER */ - tpmInfo.prescale = kTPM_Prescale_Divide_4; - - /* Initialize TPM module */ - TPM_Init(TPM0, &tpmInfo); - - TPM_EnableInterrupts(TPM0, kTPM_TimeOverflowInterruptEnable); - - EnableIRQ(TPM0_IRQn); - - tpm_source_clock = (CLOCK_GetFreq(kCLOCK_McgIrc48MClk) / 4); - - // Set Board Rev ID pin as output but pin disabled - PORT_SetPinMux(PIN_BOARD_REV_ID_PORT , PIN_BOARD_REV_ID_BIT, kPORT_PinDisabledOrAnalog); - PORT_SetPinDriveStrength(PIN_BOARD_REV_ID_PORT, PIN_BOARD_REV_ID_BIT, kPORT_HighDriveStrength); - GPIO_PinInit(PIN_BOARD_REV_ID_GPIO, PIN_BOARD_REV_ID_BIT, &pin_config); - - adc_init(); - - // 1. Discharge capacitor - /* Set timer period 3ms*/ - TPM_SetTimerPeriod(TPM0, USEC_TO_COUNT(3000U, tpm_source_clock)); - // Drive BRD_REV_ID pin to low - GPIO_PortClear(PIN_BOARD_REV_ID_GPIO, PIN_BOARD_REV_ID); - PORT_SetPinMux(PIN_BOARD_REV_ID_PORT , PIN_BOARD_REV_ID_BIT, kPORT_MuxAsGpio); - // Add a 3ms delay to allow the 100nF Cap to discharge - // at least 5*RC with 4700R. - TPM_StartTimer(TPM0, kTPM_SystemClock); - while (false == tpmIsrFlag); - tpmIsrFlag = false; - - // 2. Charge capacitor for 100us - /* Set timer period slightly below 100us to account for overheads */ - TPM_SetTimerPeriod(TPM0, USEC_TO_COUNT(98U, tpm_source_clock)); - // Drive BRD_REV_ID pin to high - GPIO_PortSet(PIN_BOARD_REV_ID_GPIO, PIN_BOARD_REV_ID); - // Add a ~100us delay - TPM_StartTimer(TPM0, kTPM_SystemClock); - while (false == tpmIsrFlag); - tpmIsrFlag = false; - // Change pin to ADC (High-Z). Capacitor will stop charging - PORT_SetPinMux(PIN_BOARD_REV_ID_PORT , PIN_BOARD_REV_ID_BIT, kPORT_PinDisabledOrAnalog); - - // 3. Take ADC measurement - board_rev_id_adc = adc_read_channel(0, PIN_BOARD_REV_ID_ADC_CH, PIN_BOARD_REV_ID_ADC_MUX); - board_rev_id_mv = board_rev_id_adc * 3300 / 0xFFF; // Convert ADC 12-bit value to mV with 3.3V reference - - // 4. Discharge capacitor - /* Set timer period 3ms*/ - TPM_SetTimerPeriod(TPM0, USEC_TO_COUNT(3000U, tpm_source_clock)); - // Drive BRD_REV_ID pin to low - GPIO_PortClear(PIN_BOARD_REV_ID_GPIO, PIN_BOARD_REV_ID); - PORT_SetPinMux(PIN_BOARD_REV_ID_PORT , PIN_BOARD_REV_ID_BIT, kPORT_MuxAsGpio); - // Add a 3ms delay to allow the 100nF Cap to discharge - // at least 5*RC with 4700R. - TPM_StartTimer(TPM0, kTPM_SystemClock); - while (false == tpmIsrFlag); - tpmIsrFlag = false; - - // 5. Identify board ID depending on voltage - if ( board_rev_id_mv > BRD_ID_1_LOWER_THR_V && board_rev_id_mv < BRD_ID_1_UPPER_THR_V) { - board_version = BOARD_VERSION_2_0; - } else { - board_version = BOARD_VERSION_2_DEF; - } - - return board_version; -} - -#elif defined(INTERFACE_NRF52820) - -static mb_version_t read_brd_rev_id(void) -{ - switch (NRF_FICR->INFO.PART) { - case 0x52833: return BOARD_VERSION_2_2_833; - case 0x52820: return BOARD_VERSION_2_2_820; - default: return BOARD_VERSION_2_DEF; - } -} -#endif static void set_board_id(mb_version_t board_version) { switch (board_version) { case BOARD_VERSION_2_0: - g_board_info.target_cfg->rt_board_id = board_id_mb_2_0; + g_board_info.target_cfg->rt_board_id = BOARD_ID_MB_2_0; board_id_hex = BOARD_VERSION_2_0; break; case BOARD_VERSION_2_2_833: - g_board_info.target_cfg->rt_board_id = board_id_mb_2_2_833; + g_board_info.target_cfg->rt_board_id = BOARD_ID_MB_2_2_833; board_id_hex = BOARD_VERSION_2_2_833; break; case BOARD_VERSION_2_2_820: - g_board_info.target_cfg->rt_board_id = board_id_mb_2_2_820; + g_board_info.target_cfg->rt_board_id = BOARD_ID_MB_2_2_820; board_id_hex = BOARD_VERSION_2_2_820; break; case BOARD_VERSION_2_DEF: /* Intentional fall-through */ default: - g_board_info.target_cfg->rt_board_id = board_id_mb_2_default; + g_board_info.target_cfg->rt_board_id = BOARD_ID_MB_2_DEFAULT; board_id_hex = BOARD_VERSION_2_DEF; break; } @@ -245,10 +117,10 @@ static void prerun_board_config(void) { // HID_LED_DEF is on so the resting state of the orange LED after flashing is on // but turn it off here so it's initially off, then stays off when on battery, - // and comes on only when USB enumerates + // and comes on only when USB enumerates gpio_set_hid_led(GPIO_LED_OFF); - mb_version_t board_version = read_brd_rev_id(); + mb_version_t board_version = board_id_detect(); set_board_id(board_version); // init power monitoring diff --git a/source/board/microbitv2/microbitv2.h b/source/board/microbitv2/microbitv2.h index e744eef86..3785e62bd 100644 --- a/source/board/microbitv2/microbitv2.h +++ b/source/board/microbitv2/microbitv2.h @@ -25,9 +25,6 @@ #define M0_RESERVED_VECT_OFFSET (4 * 4) #define M0_RESERVED_VECT_SIZE (3 * 4) // Size for mem fault, bus fault and usage fault vectors -#define BRD_ID_1_UPPER_THR_V 935 // Upper threshold in mV for 100nF and 4700R -#define BRD_ID_1_LOWER_THR_V 268 // Lower threshold in mV for 100nF and 4700R - #define PWR_LED_ON_MAX_BRIGHTNESS 255 // Max LED Brightness (PC Connected) #define PWR_LED_INIT_FADE_BRIGHTNESS 200 // Initial fade LED Brightness #define PWR_LED_ON_BATT_BRIGHTNESS 100 // LED Brightness while being powered by battery diff --git a/source/board/microbitv2/nrf52820/board_id.c b/source/board/microbitv2/nrf52820/board_id.c new file mode 100644 index 000000000..bc2194429 --- /dev/null +++ b/source/board/microbitv2/nrf52820/board_id.c @@ -0,0 +1,34 @@ +/** + * @file board_id.c + * @brief + * + * DAPLink Interface Firmware + * Copyright 2021 Micro:bit Educational Foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "board_id.h" + +#include "nrf.h" + + +mb_version_t board_id_detect(void) +{ + switch (NRF_FICR->INFO.PART) { + case 0x52833: return BOARD_VERSION_2_2_833; + case 0x52820: return BOARD_VERSION_2_2_820; + default: return BOARD_VERSION_2_DEF; + } +} diff --git a/source/board/nrf52820_microbit_bl.c b/source/board/nrf52820_microbit_bl.c index 9b49a08cd..8c67f074e 100644 --- a/source/board/nrf52820_microbit_bl.c +++ b/source/board/nrf52820_microbit_bl.c @@ -1,7 +1,7 @@ /** * @file nrf52820_bl.c * @brief board ID, meta-data, and additional configuration for micro:bit - * nRF52820 HIC + * nRF52820 HIC * * DAPLink Interface Firmware * Copyright (c) 2009-2021, ARM Limited, All Rights Reserved @@ -30,6 +30,7 @@ #include "gpio.h" #include "nrf.h" #include "nrf_nvmc.h" +#include "board_id.h" /* NFC configuration in the User UICR area, needed to configure NFC pins as GPIO */ #define NRF52833_UICR_NFCPINS_OFFSET (0x20CUL) @@ -72,7 +73,7 @@ const target_family_descriptor_t *g_target_family = NULL; // Mainly used to identify which interface hex file to download from the micro:bit help page const board_info_t g_board_info = { .info_version = kBoardInfoVersion, - .board_id = "9905", + .board_id = BOARD_ID_MB_2_2_833, .daplink_url_name = "HELP_FAQHTM", .daplink_drive_name = "MAINTENANCE", .daplink_target_url = "https://microbit.org/device/?id=@B&v=@V&bl=1", From f04e4e8fbe731bcde8c1a923179f5529b4b0bf01 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Fri, 24 Dec 2021 00:17:19 +0000 Subject: [PATCH 600/617] microbitv2: Move adc.h/c into microbitv2/kl27z dir. As this library is only used by micro:bit and not generic enough. --- source/{hic_hal/freescale => board/microbitv2}/kl27z/adc.c | 0 source/{hic_hal => board/microbitv2/kl27z}/adc.h | 0 source/board/microbitv2/kl27z/board_id.c | 2 +- source/board/microbitv2/kl27z/pwr_mon.c | 2 +- 4 files changed, 2 insertions(+), 2 deletions(-) rename source/{hic_hal/freescale => board/microbitv2}/kl27z/adc.c (100%) rename source/{hic_hal => board/microbitv2/kl27z}/adc.h (100%) diff --git a/source/hic_hal/freescale/kl27z/adc.c b/source/board/microbitv2/kl27z/adc.c similarity index 100% rename from source/hic_hal/freescale/kl27z/adc.c rename to source/board/microbitv2/kl27z/adc.c diff --git a/source/hic_hal/adc.h b/source/board/microbitv2/kl27z/adc.h similarity index 100% rename from source/hic_hal/adc.h rename to source/board/microbitv2/kl27z/adc.h diff --git a/source/board/microbitv2/kl27z/board_id.c b/source/board/microbitv2/kl27z/board_id.c index 2a75c5cf5..a1ba35e30 100644 --- a/source/board/microbitv2/kl27z/board_id.c +++ b/source/board/microbitv2/kl27z/board_id.c @@ -24,8 +24,8 @@ #include "board_id.h" #include "timer_wait.h" - #include "adc.h" + #include "fsl_port.h" #include "fsl_gpio.h" diff --git a/source/board/microbitv2/kl27z/pwr_mon.c b/source/board/microbitv2/kl27z/pwr_mon.c index e644c2ee9..479b50222 100644 --- a/source/board/microbitv2/kl27z/pwr_mon.c +++ b/source/board/microbitv2/kl27z/pwr_mon.c @@ -21,8 +21,8 @@ #include "pwr_mon.h" #include "timer_wait.h" - #include "adc.h" + #include "fsl_adc16.h" #include "fsl_pmc.h" #include "fsl_port.h" From f17e1540ff100fd55816ba509ac755b53e309881 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Tue, 4 Jan 2022 15:51:43 +0000 Subject: [PATCH 601/617] microbitv2: Refactor global i2c var, and combine i2c isBusy() into canSleep(). --- source/board/microbitv2/i2c.h | 4 +++- source/board/microbitv2/kl27z/i2c.c | 14 ++++++++------ source/board/microbitv2/microbitv2.c | 7 ++----- source/board/microbitv2/nrf52820/i2c.c | 14 ++++++++------ 4 files changed, 21 insertions(+), 18 deletions(-) diff --git a/source/board/microbitv2/i2c.h b/source/board/microbitv2/i2c.h index 1f9df9392..1e700d8c0 100644 --- a/source/board/microbitv2/i2c.h +++ b/source/board/microbitv2/i2c.h @@ -47,7 +47,9 @@ i2c_status_t i2c_registerWriteCallback(i2cCallback_t writeCallback, uint8_t slav i2c_status_t i2c_registerReadCallback(i2cCallback_t readCallback, uint8_t slaveAddress); void i2c_clearBuffers(void); void i2c_fillBuffer(uint8_t* data, uint32_t position, uint32_t size); -bool i2c_isBusy(void); +/* Returns true if I2C activity is idle and device can go too sleep. */ bool i2c_canSleep(void); +/* This functions needs to be called at a 30ms interval. */ +void i2c_30ms_tick(void); #endif /* I2C_H_ */ diff --git a/source/board/microbitv2/kl27z/i2c.c b/source/board/microbitv2/kl27z/i2c.c index 845211ff9..c9aa6e041 100644 --- a/source/board/microbitv2/kl27z/i2c.c +++ b/source/board/microbitv2/kl27z/i2c.c @@ -51,8 +51,8 @@ static i2cCallback_t pfReadCommsCallback = NULL; static i2cCallback_t pfWriteFlashCallback = NULL; static i2cCallback_t pfReadFlashCallback = NULL; -extern uint8_t i2c_wake_timeout; -static bool i2c_allow_sleep; +static uint8_t i2c_wake_timeout = 0; +static bool i2c_allow_sleep = true; static void i2c_clearTxBuffer(void); @@ -274,12 +274,14 @@ void i2c_fillBuffer (uint8_t* data, uint32_t position, uint32_t size) { g_slave_TX_buff_ready = 1; } -bool i2c_isBusy() +bool i2c_canSleep() { - return g_s_handle.isBusy; + return i2c_allow_sleep && !g_s_handle.isBusy && i2c_wake_timeout == 0; } -bool i2c_canSleep() +void i2c_30ms_tick() { - return i2c_allow_sleep; + if (i2c_wake_timeout > 0) { + i2c_wake_timeout--; + } } diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index c6160f84f..95128bac0 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -57,7 +57,6 @@ extern target_cfg_t target_device_nrf52833; volatile uint8_t wake_from_reset = 0; volatile uint8_t wake_from_usb = 0; volatile bool usb_pc_connected = false; -uint8_t i2c_wake_timeout = 0; power_source_t power_source; microbit_if_power_mode_t interface_power_mode = MB_POWER_DOWN; bool power_led_sleep_state_on = PWR_LED_SLEEP_STATE_DEFAULT; @@ -231,13 +230,11 @@ void board_30ms_hook() } } - if (i2c_wake_timeout > 0) { - i2c_wake_timeout--; - } + i2c_30ms_tick(); // Enter light sleep if USB is not enumerated and main_shutdown_state is idle if (usb_state == USB_DISCONNECTED && !usb_pc_connected && main_shutdown_state == MAIN_SHUTDOWN_WAITING - && automatic_sleep_on == true && i2c_isBusy() == false && i2c_wake_timeout == 0 && i2c_canSleep()) { + && automatic_sleep_on == true && i2c_canSleep()) { interface_power_mode = MB_POWER_SLEEP; main_shutdown_state = MAIN_SHUTDOWN_REQUESTED; } diff --git a/source/board/microbitv2/nrf52820/i2c.c b/source/board/microbitv2/nrf52820/i2c.c index e6c58a70b..dd1701f4f 100644 --- a/source/board/microbitv2/nrf52820/i2c.c +++ b/source/board/microbitv2/nrf52820/i2c.c @@ -61,8 +61,7 @@ static callbackToExecute_t callbackToExecute = { .size = 0, }; -// TODO: This can probably be combined with the busy state for simpler sleep config -extern uint8_t i2c_wake_timeout; +static uint8_t i2c_wake_timeout = 0; static bool i2c_allow_sleep = true; @@ -246,13 +245,16 @@ void i2c_fillBuffer(uint8_t* data, uint32_t position, uint32_t size) i2c_allow_sleep = false; } -bool i2c_isBusy() +bool i2c_canSleep() { + ARM_I2C_STATUS status = I2Cdrv->GetStatus(); - return status.busy; + return i2c_allow_sleep && !status.busy && i2c_wake_timeout == 0; } -bool i2c_canSleep() +void i2c_30ms_tick() { - return i2c_allow_sleep; + if (i2c_wake_timeout > 0) { + i2c_wake_timeout--; + } } From b352f3d31c19e1e4e92d44c97272225ef81b7603 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Thu, 6 Jan 2022 23:35:26 +0000 Subject: [PATCH 602/617] microbitv2: Refactor storage functionality from i2c_commands to storage modules. --- source/board/microbitv2/i2c.h | 2 + source/board/microbitv2/i2c_commands.c | 260 ++++++--------------- source/board/microbitv2/i2c_commands.h | 12 - source/board/microbitv2/kl27z/i2c.c | 6 + source/board/microbitv2/kl27z/storage.c | 23 +- source/board/microbitv2/microbitv2.c | 7 +- source/board/microbitv2/nrf52820/i2c.c | 7 +- source/board/microbitv2/nrf52820/storage.c | 22 +- source/board/microbitv2/storage.h | 43 +++- source/board/microbitv2/storage_common.c | 253 ++++++++++++++++++++ 10 files changed, 388 insertions(+), 247 deletions(-) create mode 100644 source/board/microbitv2/storage_common.c diff --git a/source/board/microbitv2/i2c.h b/source/board/microbitv2/i2c.h index 1e700d8c0..2da0620ab 100644 --- a/source/board/microbitv2/i2c.h +++ b/source/board/microbitv2/i2c.h @@ -47,6 +47,8 @@ i2c_status_t i2c_registerWriteCallback(i2cCallback_t writeCallback, uint8_t slav i2c_status_t i2c_registerReadCallback(i2cCallback_t readCallback, uint8_t slaveAddress); void i2c_clearBuffers(void); void i2c_fillBuffer(uint8_t* data, uint32_t position, uint32_t size); +/* A more efficient way to fill the first byte for simple transactions. */ +void i2c_fillBufferHead(uint8_t data); /* Returns true if I2C activity is idle and device can go too sleep. */ bool i2c_canSleep(void); /* This functions needs to be called at a 30ms interval. */ diff --git a/source/board/microbitv2/i2c_commands.c b/source/board/microbitv2/i2c_commands.c index 1413035f3..532ce7e84 100644 --- a/source/board/microbitv2/i2c_commands.c +++ b/source/board/microbitv2/i2c_commands.c @@ -40,24 +40,13 @@ extern bool automatic_sleep_on; extern main_shutdown_state_t main_shutdown_state; extern bool do_remount; -// 'kvld' in hex - key valid -#define CFG_KEY 0x6b766c64 - -flashConfig_t gflashConfig = { - .key = CFG_KEY, - .fileName = STORAGE_CFG_FILENAME, - .fileSize = STORAGE_CFG_FILESIZE, - .fileVisible = STORAGE_CFG_FILEVISIBLE, - .fileEncWindowStart = 0, - .fileEncWindowEnd = 0, -}; - static void i2c_write_comms_callback(uint8_t* pData, uint8_t size); static void i2c_read_comms_callback(uint8_t* pData, uint8_t size); static void i2c_write_flash_callback(uint8_t* pData, uint8_t size); static void i2c_read_flash_callback(uint8_t* pData, uint8_t size); + static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { i2cCommand_t* pI2cCommand = (i2cCommand_t*) pData; i2cCommand_t i2cResponse = {0}; @@ -218,173 +207,105 @@ static void i2c_read_comms_callback(uint8_t* pData, uint8_t size) { gpio_disable_combined_int(); } -static bool file_extension_allowed(const vfs_filename_t filename) -{ - const char *valid_extensions[] = { - "BIN", - "TXT", - "CSV", - "HTM", - "WAV", - }; - uint32_t i; - - // Check for invalid starting characters - for (i = 0; i < (sizeof((valid_extensions))/sizeof((valid_extensions)[0])); i++) { - if (0 == memcmp(&filename[8], valid_extensions[i], 3)) { - return true; - } - } - - // Some checks failed so file extension is invalid - return false; -} - static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { i2cFlashCmd_t* pI2cCommand = (i2cFlashCmd_t*) pData; - - uint32_t status = 0; - uint32_t storage_address = pI2cCommand->cmdData.write.addr2 << 16 | pI2cCommand->cmdData.write.addr1 << 8 | pI2cCommand->cmdData.write.addr0 << 0; - uint32_t address = storage_address + STORAGE_ADDRESS_START; uint32_t length = __REV(pI2cCommand->cmdData.write.length); - uint32_t data = (uint32_t) pI2cCommand->cmdData.write.data; switch (pI2cCommand->cmdId) { case gFlashDataWrite_c: /* Validate length field matches with I2C Write data */ if (size == length + 8) { - /* Address range and alignment validation done inside storage_program_page() */ - status = storage_program_page(address, length, (uint8_t *) data); - - if (0 != status) { - pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - } - else { - /* Fill TX Buffer with received command args */ - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, sizeof(i2cFlashCmd_t) - 1024); - /* Fill TX Buffer with Flash Data Written */ - i2c_fillBuffer((uint8_t*) address, sizeof(i2cFlashCmd_t) - 1024, length); + storage_status_t status = storage_write(storage_address, length, &pI2cCommand->cmdData.write.data[0]); + if (STORAGE_SUCCESS == status) { + /* Echo back all the received data */ + i2c_fillBuffer((uint8_t *)pI2cCommand, 0, size); + } else { + i2c_fillBufferHead(gFlashError_c); } } else { - pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBufferHead(gFlashError_c); } break; case gFlashDataRead_c: { /* Do address range validation */ - if (address + length > STORAGE_ADDRESS_END) { - pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - } else { + uint8_t* storage_data = storage_get_data_pointer(storage_address); + if (storage_data != NULL) { /* Fill TX Buffer with received command args */ - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, sizeof(i2cFlashCmd_t) - 1024); + i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 8); /* Fill TX Buffer with Flash Data Read */ - i2c_fillBuffer((uint8_t*) address, sizeof(i2cFlashCmd_t) - 1024, length); + i2c_fillBuffer(storage_data, 8, length); + } else { + i2c_fillBufferHead(gFlashError_c); } } break; case gFlashDataErase_c: { - uint32_t address = pI2cCommand->cmdData.erase.sAddr2 << 16 | + uint32_t start_addr = pI2cCommand->cmdData.erase.sAddr2 << 16 | pI2cCommand->cmdData.erase.sAddr1 << 8 | pI2cCommand->cmdData.erase.sAddr0 << 0; - uint32_t start_addr = address + STORAGE_ADDRESS_START; - - address = pI2cCommand->cmdData.erase.eAddr2 << 16 | + uint32_t end_addr = pI2cCommand->cmdData.erase.eAddr2 << 16 | pI2cCommand->cmdData.erase.eAddr1 << 8 | pI2cCommand->cmdData.erase.eAddr0 << 0; - uint32_t end_addr = address + STORAGE_ADDRESS_START; - - /* Do address range validation */ - if (start_addr % DAPLINK_SECTOR_SIZE == 0 && - end_addr % DAPLINK_SECTOR_SIZE == 0 && - start_addr <= end_addr && - start_addr < STORAGE_ADDRESS_END && - end_addr < STORAGE_ADDRESS_END) { - for (uint32_t addr = start_addr; addr <= end_addr && status == 0; addr += DAPLINK_SECTOR_SIZE) { - status = storage_erase_sector(addr); - } - - if (status != 0) { - pI2cCommand->cmdId = gFlashError_c; - } + if (storage_erase_range(start_addr, end_addr) == STORAGE_SUCCESS) { + i2c_fillBufferHead(pI2cCommand->cmdId); } else { - pI2cCommand->cmdId = gFlashError_c; + i2c_fillBufferHead(gFlashError_c); } - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - } break; case gFlashCfgFileName_c: if (size == 1) { /* If size is 1 (only cmd id), this means it's a read */ - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - i2c_fillBuffer((uint8_t*) &gflashConfig.fileName, 1, sizeof(gflashConfig.fileName)); - } else if (size == 12) { + i2c_fillBufferHead(pI2cCommand->cmdId); + i2c_fillBuffer((uint8_t *)storage_cfg_get_filename(), 1, STORAGE_CFG_FILENAME_SIZE); + } else if (size == (1 + STORAGE_CFG_FILENAME_SIZE)) { /* If size is 12 (cmd id + 11B data), this means it's a write */ - /* Validate 8.3 filename */ - if (filename_valid((char *) pI2cCommand->cmdData.data)) { - // Check allowed extensions (.bin, .txt, .csv, .htm, .wav) - if (file_extension_allowed((char *) pI2cCommand->cmdData.data)) { - memcpy(gflashConfig.fileName, pI2cCommand->cmdData.data, 11); - } - // If disallowed extension is requested, .bin will be used - else { - memcpy(gflashConfig.fileName, pI2cCommand->cmdData.data, 8); - memcpy(&gflashConfig.fileName[8], "BIN", 3); - } - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - i2c_fillBuffer((uint8_t*) &gflashConfig.fileName, 1, sizeof(gflashConfig.fileName)); - } - else { - // Send error if invalid filename - pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + storage_status_t status = storage_cfg_set_filename((char *)pI2cCommand->cmdData.data); + if (STORAGE_SUCCESS == status) { + i2c_fillBufferHead(pI2cCommand->cmdId); + i2c_fillBuffer(pI2cCommand->cmdData.data, 1, STORAGE_CFG_FILENAME_SIZE); + } else { + i2c_fillBufferHead(gFlashError_c); } } else { - pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBufferHead(gFlashError_c); } break; case gFlashCfgFileSize_c: if (size == 1) { /* If size is 1 (only cmd id), this means it's a read */ - uint32_t tempFileSize = __REV(gflashConfig.fileSize); - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - i2c_fillBuffer((uint8_t*) &tempFileSize, 1, sizeof(gflashConfig.fileSize)); + uint32_t tempFileSize = __REV(storage_cfg_get_file_size()); + i2c_fillBufferHead(pI2cCommand->cmdId); + i2c_fillBuffer((uint8_t*) &tempFileSize, 1, sizeof(tempFileSize)); } else if (size == 5) { /* If size is 5 (cmd id + 4B data), this means it's a write */ + //uint32_t tempFileSize = __REV((uint32_t)pI2cCommand->cmdData.data); uint32_t tempFileSize = pI2cCommand->cmdData.data[0] << 24 | pI2cCommand->cmdData.data[1] << 16 | pI2cCommand->cmdData.data[2] << 8 | pI2cCommand->cmdData.data[3] << 0; - - /* Validate file size */ - if (tempFileSize <= STORAGE_SIZE) { - gflashConfig.fileSize = tempFileSize; - tempFileSize = __REV(gflashConfig.fileSize); - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - i2c_fillBuffer((uint8_t*) &tempFileSize, 1, sizeof(gflashConfig.fileSize)); + storage_status_t status = storage_cfg_set_file_size(tempFileSize); + if (status == STORAGE_SUCCESS) { + i2c_fillBufferHead(pI2cCommand->cmdId); + i2c_fillBuffer(pI2cCommand->cmdData.data, 1, sizeof(tempFileSize)); } else { - pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBufferHead(gFlashError_c); } } else { - pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBufferHead(gFlashError_c); } break; case gFlashCfgEncWindow_c: if (size == 1) { /* If size is 1 (only cmd id), this means it's a read */ - uint32_t tempFileEncWindowStart = __REV(gflashConfig.fileEncWindowStart); - uint32_t tempFileEncWindowEnd = __REV(gflashConfig.fileEncWindowEnd); - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - i2c_fillBuffer((uint8_t*) &tempFileEncWindowStart, 1, sizeof(gflashConfig.fileEncWindowStart)); - i2c_fillBuffer((uint8_t*) &tempFileEncWindowEnd, 5, sizeof(gflashConfig.fileEncWindowEnd)); + uint32_t tempFileEncWindowStart = __REV(storage_cfg_get_encoding_start()); + uint32_t tempFileEncWindowEnd = __REV(storage_cfg_get_encoding_end()); + i2c_fillBufferHead(pI2cCommand->cmdId); + i2c_fillBuffer((uint8_t*) &tempFileEncWindowStart, 1, sizeof(tempFileEncWindowStart)); + i2c_fillBuffer((uint8_t*) &tempFileEncWindowEnd, 5, sizeof(tempFileEncWindowEnd)); } else if (size == 9) { /* If size is 9 (cmd id + 8B data), this means it's a write */ uint32_t tempFileEncWindowStart = pI2cCommand->cmdData.data[0] << 24 | @@ -398,70 +319,44 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { /* Validate encoding window */ if (tempFileEncWindowStart <= tempFileEncWindowEnd) { - gflashConfig.fileEncWindowStart = tempFileEncWindowStart; - tempFileEncWindowStart = __REV(gflashConfig.fileEncWindowStart); - gflashConfig.fileEncWindowEnd = tempFileEncWindowEnd; - tempFileEncWindowEnd = __REV(gflashConfig.fileEncWindowEnd); - - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - i2c_fillBuffer((uint8_t*) &tempFileEncWindowStart, 1, sizeof(gflashConfig.fileEncWindowStart)); - i2c_fillBuffer((uint8_t*) &tempFileEncWindowEnd, 5, sizeof(gflashConfig.fileEncWindowEnd)); + storage_cfg_set_encoding_window(tempFileEncWindowStart, tempFileEncWindowEnd); + /* Echo back all the received data */ + i2c_fillBuffer((uint8_t *)pI2cCommand, 0, size); } else { - pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBufferHead(gFlashError_c); } } else { - pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBufferHead(gFlashError_c); } break; case gFlashCfgFileVisible_c: if (size == 1) { /* If size is 1 (only cmd id), this means it's a read */ - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - i2c_fillBuffer((uint8_t*) &gflashConfig.fileVisible, 1, sizeof(gflashConfig.fileVisible)); + i2c_fillBufferHead(pI2cCommand->cmdId); + uint8_t file_visible = storage_cfg_get_file_visible(); + i2c_fillBuffer((uint8_t*) &file_visible, 1, sizeof(file_visible)); } else if (size == 2) { /* If size is 2 (cmd id + 1B data), this means it's a write */ - gflashConfig.fileVisible = pI2cCommand->cmdData.data[0]; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); - i2c_fillBuffer((uint8_t*) &gflashConfig.fileVisible, 1, sizeof(gflashConfig.fileVisible)); + storage_cfg_set_file_visible(pI2cCommand->cmdData.data[0]); + i2c_fillBufferHead(pI2cCommand->cmdId); + i2c_fillBuffer(pI2cCommand->cmdData.data, 1, sizeof(pI2cCommand->cmdData.data[0])); } else { - pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBufferHead(gFlashError_c); } break; case gFlashCfgWrite_c: - // Check first is config is already present in flash - // If differences are found, erase and write new config - if (0 != memcmp(&gflashConfig, (void *)STORAGE_CONFIG_ADDRESS, sizeof(flashConfig_t))) { - status = storage_erase_sector(STORAGE_CONFIG_ADDRESS); - - if (status != 0) { - pI2cCommand->cmdId = gFlashError_c; - } - else { - status = storage_program_page(STORAGE_CONFIG_ADDRESS, sizeof(flashConfig_t), (uint8_t *) &gflashConfig); - } + if (storage_cfg_write() == STORAGE_SUCCESS) { + i2c_fillBufferHead(pI2cCommand->cmdId); + } else { + i2c_fillBufferHead(gFlashError_c); } - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); break; case gFlashCfgErase_c: - // Erase flash sector containing flash config - status = storage_erase_sector(STORAGE_CONFIG_ADDRESS); - - if (status != 0) { - pI2cCommand->cmdId = gFlashError_c; - } - else { - // Return flash config (RAM) to default values - gflashConfig.key = CFG_KEY; - memcpy(gflashConfig.fileName, STORAGE_CFG_FILENAME, 11); - gflashConfig.fileSize = STORAGE_CFG_FILESIZE; - gflashConfig.fileVisible = STORAGE_CFG_FILEVISIBLE; - gflashConfig.fileEncWindowStart = 0; - gflashConfig.fileEncWindowEnd = 0; + if (storage_cfg_erase() == STORAGE_SUCCESS) { + i2c_fillBufferHead(pI2cCommand->cmdId); + } else { + i2c_fillBufferHead(gFlashError_c); } - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); break; case gFlashStorageSize_c: pI2cCommand->cmdData.data[0] = STORAGE_SECTOR_COUNT; @@ -474,11 +369,10 @@ static void i2c_write_flash_callback(uint8_t* pData, uint8_t size) { break; case gFlashRemountMSD_c: do_remount = true; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBufferHead(pI2cCommand->cmdId); break; default: - pI2cCommand->cmdId = gFlashError_c; - i2c_fillBuffer((uint8_t*) pI2cCommand, 0, 1); + i2c_fillBufferHead(gFlashError_c); break; } @@ -492,30 +386,10 @@ static void i2c_read_flash_callback(uint8_t* pData, uint8_t size) { } void i2c_cmds_init() { - // Load Config from Flash if present - flashConfig_t *pflashConfigROM = (flashConfig_t *) STORAGE_CONFIG_ADDRESS; - if (CFG_KEY == pflashConfigROM->key) { - memcpy(&gflashConfig, pflashConfigROM, sizeof(flashConfig_t)); - } - + // Needs storage_init() to have been run, currently called in microbitv2.c prerun_board_config() i2c_initialize(); i2c_registerWriteCallback(i2c_write_comms_callback, I2C_SLAVE_NRF_KL_COMMS); i2c_registerReadCallback(i2c_read_comms_callback, I2C_SLAVE_NRF_KL_COMMS); i2c_registerWriteCallback(i2c_write_flash_callback, I2C_SLAVE_FLASH); i2c_registerReadCallback(i2c_read_flash_callback, I2C_SLAVE_FLASH); } - -flashConfig_t* i2c_cmds_get_storage_config() { - return &gflashConfig; -} - -void i2c_cmds_reset_storate_config() { - gflashConfig = (flashConfig_t) { - .key = CFG_KEY, - .fileName = STORAGE_CFG_FILENAME, - .fileSize = STORAGE_CFG_FILESIZE, - .fileVisible = STORAGE_CFG_FILEVISIBLE, - .fileEncWindowStart = 0, - .fileEncWindowEnd = 0, - }; -} diff --git a/source/board/microbitv2/i2c_commands.h b/source/board/microbitv2/i2c_commands.h index 5383274f5..31b307494 100644 --- a/source/board/microbitv2/i2c_commands.h +++ b/source/board/microbitv2/i2c_commands.h @@ -26,7 +26,6 @@ #include #include "cmsis_compiler.h" -#include "virtual_fs.h" #ifdef __cplusplus extern "C" { @@ -127,15 +126,6 @@ typedef __PACKED_STRUCT i2cCommand_tag { } cmdData; } i2cCommand_t; -typedef __PACKED_STRUCT flashConfig_tag { - uint32_t key; // Magic key to indicate a valid record - vfs_filename_t fileName; - uint32_t fileSize; - bool fileVisible; - uint32_t fileEncWindowStart; - uint32_t fileEncWindowEnd; -} flashConfig_t; - /*! Flash interface command type */ typedef enum flashCmdId_tag { gFlashCfgFileName_c = 0x01, @@ -183,8 +173,6 @@ typedef __PACKED_STRUCT i2cFlashCmd_tag { } i2cFlashCmd_t; void i2c_cmds_init(void); -flashConfig_t* i2c_cmds_get_storage_config(void); -void i2c_cmds_reset_storate_config(void); #ifdef __cplusplus } diff --git a/source/board/microbitv2/kl27z/i2c.c b/source/board/microbitv2/kl27z/i2c.c index c9aa6e041..e26eb2dac 100644 --- a/source/board/microbitv2/kl27z/i2c.c +++ b/source/board/microbitv2/kl27z/i2c.c @@ -274,6 +274,12 @@ void i2c_fillBuffer (uint8_t* data, uint32_t position, uint32_t size) { g_slave_TX_buff_ready = 1; } +void i2c_fillBufferHead(uint8_t data) +{ + g_slave_TX_buff[0] = data; + g_slave_TX_buff_ready = 1; +} + bool i2c_canSleep() { return i2c_allow_sleep && !g_s_handle.isBusy && i2c_wake_timeout == 0; diff --git a/source/board/microbitv2/kl27z/storage.c b/source/board/microbitv2/kl27z/storage.c index 8d7a6d01a..5055a5adb 100644 --- a/source/board/microbitv2/kl27z/storage.c +++ b/source/board/microbitv2/kl27z/storage.c @@ -25,35 +25,28 @@ extern flash_config_t g_flash; -uint32_t storage_program_page(uint32_t adr, uint32_t sz, uint8_t *buf) +storage_status_t storage_program_flash(uint32_t adr, uint32_t sz, uint8_t *buf) { /* Verify data is word aligned */ util_assert(!((uint32_t)buf & 0x3)); - + int status = FLASH_Program(&g_flash, adr, (uint32_t *) buf, sz); - if (status == kStatus_Success) - { + if (status == kStatus_Success) { // Must use kFlashMargin_User, or kFlashMargin_Factory for verify program status = FLASH_VerifyProgram(&g_flash, adr, sz, (uint32_t *) buf, kFLASH_marginValueUser, NULL, NULL); } - return status; + + return (status == kStatus_Success) ? STORAGE_SUCCESS : STORAGE_ERROR; } -uint32_t storage_erase_sector(uint32_t adr) +storage_status_t storage_erase_flash_page(uint32_t adr) { int status = FLASH_Erase(&g_flash, adr, g_flash.PFlashSectorSize, kFLASH_apiEraseKey); - if (status == kStatus_Success) - { + if (status == kStatus_Success) { status = FLASH_VerifyErase(&g_flash, adr, g_flash.PFlashSectorSize, kFLASH_marginValueNormal); } - return status; -} -uint32_t storage_erase_all() -{ - int status = FLASH_Erase(&g_flash, STORAGE_CONFIG_ADDRESS, g_flash.PFlashTotalSize / g_flash.PFlashBlockCount, kFLASH_apiEraseKey); - // TODO: Should we verify erase? Might be slow - return status; + return (status == kStatus_Success) ? STORAGE_SUCCESS : STORAGE_ERROR; } diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 95128bac0..4ddf8c235 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -142,6 +142,7 @@ static void prerun_board_config(void) uint8_t gamma_led_dc = get_led_gamma(power_led_max_duty_cycle); pwm_set_dutycycle(gamma_led_dc); + storage_init(); i2c_cmds_init(); gpio_init_combined_int(); @@ -410,9 +411,7 @@ void board_vfs_stream_closed_hook() bool vfs_user_magic_file_hook(const vfs_filename_t filename, bool *do_remount) { if (!memcmp(filename, "ERASE ACT", sizeof(vfs_filename_t))) { - // Erase last 128KB flash block storage_erase_all(); - i2c_cmds_reset_storate_config(); } return false; @@ -448,7 +447,7 @@ void vfs_user_build_filesystem_hook() { } } - flashConfig_t* storage_cgf = i2c_cmds_get_storage_config(); + flashConfig_t* storage_cgf = storage_get_cfg(); file_size = storage_cgf->fileSize + (storage_cgf->fileEncWindowEnd - storage_cgf->fileEncWindowStart); if (storage_cgf->fileVisible) { @@ -460,7 +459,7 @@ void vfs_user_build_filesystem_hook() { static uint32_t read_file_data_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors) { uint32_t read_address = STORAGE_ADDRESS_START + (VFS_SECTOR_SIZE * sector_offset); - flashConfig_t* storage_cgf = i2c_cmds_get_storage_config(); + flashConfig_t* storage_cgf = storage_get_cfg(); uint32_t encoded_data_offset = (storage_cgf->fileEncWindowEnd - storage_cgf->fileEncWindowStart); // Ignore out of bound reads diff --git a/source/board/microbitv2/nrf52820/i2c.c b/source/board/microbitv2/nrf52820/i2c.c index dd1701f4f..ca57f27ff 100644 --- a/source/board/microbitv2/nrf52820/i2c.c +++ b/source/board/microbitv2/nrf52820/i2c.c @@ -245,9 +245,14 @@ void i2c_fillBuffer(uint8_t* data, uint32_t position, uint32_t size) i2c_allow_sleep = false; } -bool i2c_canSleep() +void i2c_fillBufferHead(uint8_t data) { + g_slave_TX_buff[0] = data; + i2c_allow_sleep = false; +} +bool i2c_canSleep() +{ ARM_I2C_STATUS status = I2Cdrv->GetStatus(); return i2c_allow_sleep && !status.busy && i2c_wake_timeout == 0; } diff --git a/source/board/microbitv2/nrf52820/storage.c b/source/board/microbitv2/nrf52820/storage.c index 76cbd1d4d..ebdcf1298 100644 --- a/source/board/microbitv2/nrf52820/storage.c +++ b/source/board/microbitv2/nrf52820/storage.c @@ -23,7 +23,7 @@ #include "nrf_nvmc.h" -uint32_t storage_program_page(uint32_t adr, uint32_t sz, uint8_t *buf) +storage_status_t storage_program_flash(uint32_t adr, uint32_t sz, uint8_t *buf) { uint32_t *buf_32 = (uint32_t *)buf; nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_WRITE); @@ -35,10 +35,10 @@ uint32_t storage_program_page(uint32_t adr, uint32_t sz, uint8_t *buf) } nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_READONLY); - return 0; + return STORAGE_SUCCESS; } -uint32_t storage_erase_sector(uint32_t adr) +storage_status_t storage_erase_flash_page(uint32_t adr) { // This operation can take up to 87.5ms nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_ERASE); @@ -48,19 +48,5 @@ uint32_t storage_erase_sector(uint32_t adr) } nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_READONLY); - return 0; -} - -uint32_t storage_erase_all() -{ - nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_ERASE); - for (uint32_t adr = STORAGE_FLASH_ADDRESS_START; adr < STORAGE_FLASH_ADDRESS_END; adr += STORAGE_SECTOR_SIZE) { - nrf_nvmc_page_erase_start(NRF_NVMC, adr); - while (!nrf_nvmc_ready_check(NRF_NVMC)) { - // Wait for controller to be ready - } - } - nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_READONLY); - - return 0; + return STORAGE_SUCCESS; } diff --git a/source/board/microbitv2/storage.h b/source/board/microbitv2/storage.h index 908280bb6..8a0c6afb8 100644 --- a/source/board/microbitv2/storage.h +++ b/source/board/microbitv2/storage.h @@ -19,13 +19,16 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + #ifndef STORAGE_H_ #define STORAGE_H_ #include #include "storage_config.h" +#include "virtual_fs.h" +#include "cmsis_compiler.h" + #ifdef __cplusplus extern "C" { #endif @@ -48,12 +51,44 @@ extern "C" { #define STORAGE_SIZE (STORAGE_ADDRESS_END - STORAGE_ADDRESS_START) #define STORAGE_SECTOR_COUNT (STORAGE_SIZE / STORAGE_SECTOR_SIZE) #define STORAGE_CFG_FILENAME "DATA BIN" +#define STORAGE_CFG_FILENAME_SIZE 11 #define STORAGE_CFG_FILEVISIBLE false #define STORAGE_CFG_FILESIZE (STORAGE_SIZE - STORAGE_SECTOR_SIZE) -uint32_t storage_program_page(uint32_t adr, uint32_t sz, uint8_t *buf); -uint32_t storage_erase_sector(uint32_t adr); -uint32_t storage_erase_all(void); +typedef __PACKED_STRUCT flashConfig_tag { + uint32_t key; // Magic key to indicate a valid record + vfs_filename_t fileName; + uint32_t fileSize; + bool fileVisible; + uint32_t fileEncWindowStart; + uint32_t fileEncWindowEnd; +} flashConfig_t; + +typedef enum { + STORAGE_SUCCESS = 0, + STORAGE_ERROR +} storage_status_t; + +void storage_init(void); +uint8_t* storage_get_data_pointer(uint32_t adr); +storage_status_t storage_write(uint32_t adr, uint32_t sz, uint8_t *buf); +storage_status_t storage_erase_sector(uint32_t adr); +storage_status_t storage_erase_range(uint32_t star_adr, uint32_t end_adr); +storage_status_t storage_erase_all(void); +storage_status_t storage_program_flash(uint32_t adr, uint32_t sz, uint8_t *buf); +storage_status_t storage_erase_flash_page(uint32_t adr); +flashConfig_t* storage_get_cfg(void); +storage_status_t storage_cfg_write(void); +storage_status_t storage_cfg_erase(void); +storage_status_t storage_cfg_set_filename(const char * const filename); +storage_status_t storage_cfg_set_file_size(const uint32_t file_size); +storage_status_t storage_cfg_set_file_visible(const bool file_visible); +storage_status_t storage_cfg_set_encoding_window(const uint32_t start, const uint32_t end); +char* storage_cfg_get_filename(void); +uint32_t storage_cfg_get_file_size(void); +uint8_t storage_cfg_get_file_visible(void); +uint32_t storage_cfg_get_encoding_start(void); +uint32_t storage_cfg_get_encoding_end(void); #ifdef __cplusplus } diff --git a/source/board/microbitv2/storage_common.c b/source/board/microbitv2/storage_common.c new file mode 100644 index 000000000..e4e995a85 --- /dev/null +++ b/source/board/microbitv2/storage_common.c @@ -0,0 +1,253 @@ +/** + * @file storage_common.c + * @brief + * + * DAPLink Interface Firmware + * Copyright 2020 NXP + * Copyright 2022 Micro:bit Educational Foundation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "storage.h" + +#include "virtual_fs.h" +#include "cmsis_compiler.h" + + +// 'kvld' in hex - key valid +#define CFG_KEY 0x6b766c64 + +flashConfig_t gflashConfig = { + .key = CFG_KEY, + .fileName = STORAGE_CFG_FILENAME, + .fileSize = STORAGE_CFG_FILESIZE, + .fileVisible = STORAGE_CFG_FILEVISIBLE, + .fileEncWindowStart = 0, + .fileEncWindowEnd = 0, +}; + + +void storate_reset_config() +{ + // Return flash config (RAM) to default values + gflashConfig.key = CFG_KEY; + memcpy(gflashConfig.fileName, STORAGE_CFG_FILENAME, 11); + gflashConfig.fileSize = STORAGE_CFG_FILESIZE; + gflashConfig.fileVisible = STORAGE_CFG_FILEVISIBLE; + gflashConfig.fileEncWindowStart = 0; + gflashConfig.fileEncWindowEnd = 0; +} + +void storage_init() { + // Load Config from Flash if present + flashConfig_t *pflashConfigROM = (flashConfig_t *)STORAGE_CONFIG_ADDRESS; + if (CFG_KEY == pflashConfigROM->key) { + memcpy(&gflashConfig, pflashConfigROM, sizeof(flashConfig_t)); + } else { + storate_reset_config(); + } +} + +storage_status_t storage_cfg_write() +{ + uint32_t status = STORAGE_SUCCESS; + + // Check first is config is already present in flash + // If differences are found, erase and write new config + if (0 != memcmp(&gflashConfig, (void *)STORAGE_CONFIG_ADDRESS, sizeof(flashConfig_t))) { + status = storage_erase_flash_page(STORAGE_CONFIG_ADDRESS); + if (status == STORAGE_SUCCESS) { + status = storage_program_flash(STORAGE_CONFIG_ADDRESS, sizeof(flashConfig_t), (uint8_t *) &gflashConfig); + } + } + return status; +} + +storage_status_t storage_cfg_erase() +{ + uint32_t status = STORAGE_SUCCESS; + + // Erase flash sector containing flash config + status = storage_erase_flash_page(STORAGE_CONFIG_ADDRESS); + if (status == STORAGE_SUCCESS) { + storate_reset_config(); + } + return status; +} + +flashConfig_t* storage_get_cfg(void) +{ + return &gflashConfig; +} + +bool storage_file_extension_allowed(const vfs_filename_t filename) +{ + const char *valid_extensions[] = { + "BIN", + "TXT", + "CSV", + "HTM", + "WAV", + }; + const uint32_t valid_extensions_len = sizeof(valid_extensions) / sizeof(valid_extensions[0]); + + // Check for invalid starting characters + for (uint32_t i = 0; i < valid_extensions_len; i++) { + if (0 == memcmp(&filename[8], valid_extensions[i], 3)) { + return true; + } + } + + // Some checks failed so file extension is invalid + return false; +} + +storage_status_t storage_cfg_set_filename(const char * const filename) +{ + uint32_t status = STORAGE_SUCCESS; + + // Validate 8.3 filename + if (filename_valid(filename)) { + // Check allowed extensions (.bin, .txt, .csv, .htm, .wav) + if (storage_file_extension_allowed(filename)) { + memcpy(gflashConfig.fileName, filename, 11); + } else { + // If disallowed extension is requested, .bin will be used + memcpy(gflashConfig.fileName, filename, 8); + memcpy(&gflashConfig.fileName[8], "BIN", 3); + } + } else { + status = STORAGE_ERROR; + } + return status; +} + +storage_status_t storage_cfg_set_file_size(const uint32_t file_size) +{ + uint32_t status = STORAGE_SUCCESS; + if (file_size <= STORAGE_SIZE) { + gflashConfig.fileSize = file_size; + } else { + status = STORAGE_ERROR; + } + return status; +} + +storage_status_t storage_cfg_set_file_visible(const bool file_visible) +{ + gflashConfig.fileVisible = file_visible; + return STORAGE_SUCCESS; +} + +storage_status_t storage_cfg_set_encoding_window(const uint32_t start, const uint32_t end) +{ + s_storage_cfg.fileEncWindowStart = start; + s_storage_cfg.fileEncWindowEnd = end; + return STORAGE_SUCCESS; +} + +char* storage_cfg_get_filename(void) +{ + return &gflashConfig.fileName[0]; +} + +uint32_t storage_cfg_get_file_size(void) +{ + return gflashConfig.fileSize; +} + +uint8_t storage_cfg_get_file_visible(void) +{ + return gflashConfig.fileVisible; +} + +uint32_t storage_cfg_get_encoding_start() +{ + return s_storage_cfg.fileEncWindowStart; +} + +uint32_t storage_cfg_get_encoding_end() +{ + return s_storage_cfg.fileEncWindowEnd; +} + +uint8_t* storage_get_data_pointer(uint32_t adr) +{ + adr += STORAGE_ADDRESS_START; + if (adr >= STORAGE_ADDRESS_END) { + return NULL; + } + return (uint8_t *)adr; +} + +storage_status_t storage_write(uint32_t adr, uint32_t sz, uint8_t *buf) +{ + adr += STORAGE_ADDRESS_START; + if ( + adr < STORAGE_ADDRESS_START || + adr + sz > STORAGE_ADDRESS_END + ) { + return STORAGE_ERROR; + } + return storage_program_flash(adr, sz, buf); +} + +storage_status_t storage_erase_sector(uint32_t adr) +{ + adr += STORAGE_ADDRESS_START; + if ( + adr < STORAGE_ADDRESS_START || + adr > (STORAGE_ADDRESS_END - STORAGE_SECTOR_SIZE) + ) { + return STORAGE_ERROR; + } + return storage_erase_flash_page(adr); +} + +storage_status_t storage_erase_range(uint32_t star_adr, uint32_t end_adr) +{ + storage_status_t status = STORAGE_SUCCESS; + + star_adr += STORAGE_ADDRESS_START; + end_adr += STORAGE_ADDRESS_START; + + if (star_adr % STORAGE_SECTOR_SIZE == 0 && + end_adr % STORAGE_SECTOR_SIZE == 0 && + star_adr <= end_adr && + star_adr >= STORAGE_ADDRESS_START && + end_adr < STORAGE_ADDRESS_END + ) { + for (uint32_t addr = star_adr; + addr <= end_adr && status == STORAGE_SUCCESS; + addr += STORAGE_SECTOR_SIZE + ) { + status = storage_erase_flash_page(addr); + } + } else { + status = STORAGE_ERROR; + } + + return status; +} + +storage_status_t storage_erase_all() +{ + storage_status_t status = storage_cfg_erase(); + if (STORAGE_SUCCESS == status) { + status = storage_erase_range(0, STORAGE_SIZE - STORAGE_SECTOR_SIZE); + } + return status; +} From 06ee206d393492853ec0cf60a3eeea9badbc8abf Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Fri, 7 Jan 2022 19:28:07 +0000 Subject: [PATCH 603/617] microbitv2: Update the storage cfg struct to be better aligned & rename it. Also change the magic key used to identify valid data in flash as the structure has changed. --- source/board/microbitv2/microbitv2.c | 4 +- source/board/microbitv2/storage.h | 10 ++--- source/board/microbitv2/storage_common.c | 52 ++++++++++++------------ 3 files changed, 33 insertions(+), 33 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 4ddf8c235..acde1c552 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -447,7 +447,7 @@ void vfs_user_build_filesystem_hook() { } } - flashConfig_t* storage_cgf = storage_get_cfg(); + storage_cfg_t* storage_cgf = storage_get_cfg(); file_size = storage_cgf->fileSize + (storage_cgf->fileEncWindowEnd - storage_cgf->fileEncWindowStart); if (storage_cgf->fileVisible) { @@ -459,7 +459,7 @@ void vfs_user_build_filesystem_hook() { static uint32_t read_file_data_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors) { uint32_t read_address = STORAGE_ADDRESS_START + (VFS_SECTOR_SIZE * sector_offset); - flashConfig_t* storage_cgf = storage_get_cfg(); + storage_cfg_t* storage_cgf = storage_get_cfg(); uint32_t encoded_data_offset = (storage_cgf->fileEncWindowEnd - storage_cgf->fileEncWindowStart); // Ignore out of bound reads diff --git a/source/board/microbitv2/storage.h b/source/board/microbitv2/storage.h index 8a0c6afb8..5c126e7df 100644 --- a/source/board/microbitv2/storage.h +++ b/source/board/microbitv2/storage.h @@ -55,14 +55,14 @@ extern "C" { #define STORAGE_CFG_FILEVISIBLE false #define STORAGE_CFG_FILESIZE (STORAGE_SIZE - STORAGE_SECTOR_SIZE) -typedef __PACKED_STRUCT flashConfig_tag { +typedef __PACKED_STRUCT storage_cfg_tag { uint32_t key; // Magic key to indicate a valid record - vfs_filename_t fileName; + char fileName[STORAGE_CFG_FILENAME_SIZE]; + uint8_t fileVisible; uint32_t fileSize; - bool fileVisible; uint32_t fileEncWindowStart; uint32_t fileEncWindowEnd; -} flashConfig_t; +} storage_cfg_t; typedef enum { STORAGE_SUCCESS = 0, @@ -77,7 +77,7 @@ storage_status_t storage_erase_range(uint32_t star_adr, uint32_t end_adr); storage_status_t storage_erase_all(void); storage_status_t storage_program_flash(uint32_t adr, uint32_t sz, uint8_t *buf); storage_status_t storage_erase_flash_page(uint32_t adr); -flashConfig_t* storage_get_cfg(void); +storage_cfg_t* storage_get_cfg(void); storage_status_t storage_cfg_write(void); storage_status_t storage_cfg_erase(void); storage_status_t storage_cfg_set_filename(const char * const filename); diff --git a/source/board/microbitv2/storage_common.c b/source/board/microbitv2/storage_common.c index e4e995a85..415266446 100644 --- a/source/board/microbitv2/storage_common.c +++ b/source/board/microbitv2/storage_common.c @@ -27,14 +27,14 @@ #include "cmsis_compiler.h" -// 'kvld' in hex - key valid -#define CFG_KEY 0x6b766c64 +// 'scfg' in hex - key valid +#define STORAGE_CFG_KEY 0x73636667 -flashConfig_t gflashConfig = { - .key = CFG_KEY, +static storage_cfg_t s_storage_cfg = { + .key = STORAGE_CFG_KEY, .fileName = STORAGE_CFG_FILENAME, - .fileSize = STORAGE_CFG_FILESIZE, .fileVisible = STORAGE_CFG_FILEVISIBLE, + .fileSize = STORAGE_CFG_FILESIZE, .fileEncWindowStart = 0, .fileEncWindowEnd = 0, }; @@ -43,19 +43,19 @@ flashConfig_t gflashConfig = { void storate_reset_config() { // Return flash config (RAM) to default values - gflashConfig.key = CFG_KEY; - memcpy(gflashConfig.fileName, STORAGE_CFG_FILENAME, 11); - gflashConfig.fileSize = STORAGE_CFG_FILESIZE; - gflashConfig.fileVisible = STORAGE_CFG_FILEVISIBLE; - gflashConfig.fileEncWindowStart = 0; - gflashConfig.fileEncWindowEnd = 0; + s_storage_cfg.key = STORAGE_CFG_KEY; + memcpy(s_storage_cfg.fileName, STORAGE_CFG_FILENAME, 11); + s_storage_cfg.fileVisible = STORAGE_CFG_FILEVISIBLE; + s_storage_cfg.fileSize = STORAGE_CFG_FILESIZE; + s_storage_cfg.fileEncWindowStart = 0; + s_storage_cfg.fileEncWindowEnd = 0; } void storage_init() { // Load Config from Flash if present - flashConfig_t *pflashConfigROM = (flashConfig_t *)STORAGE_CONFIG_ADDRESS; - if (CFG_KEY == pflashConfigROM->key) { - memcpy(&gflashConfig, pflashConfigROM, sizeof(flashConfig_t)); + storage_cfg_t *pflashConfigROM = (storage_cfg_t *)STORAGE_CONFIG_ADDRESS; + if (STORAGE_CFG_KEY == pflashConfigROM->key) { + memcpy(&s_storage_cfg, pflashConfigROM, sizeof(storage_cfg_t)); } else { storate_reset_config(); } @@ -67,10 +67,10 @@ storage_status_t storage_cfg_write() // Check first is config is already present in flash // If differences are found, erase and write new config - if (0 != memcmp(&gflashConfig, (void *)STORAGE_CONFIG_ADDRESS, sizeof(flashConfig_t))) { + if (0 != memcmp(&s_storage_cfg, (void *)STORAGE_CONFIG_ADDRESS, sizeof(storage_cfg_t))) { status = storage_erase_flash_page(STORAGE_CONFIG_ADDRESS); if (status == STORAGE_SUCCESS) { - status = storage_program_flash(STORAGE_CONFIG_ADDRESS, sizeof(flashConfig_t), (uint8_t *) &gflashConfig); + status = storage_program_flash(STORAGE_CONFIG_ADDRESS, sizeof(storage_cfg_t), (uint8_t *) &s_storage_cfg); } } return status; @@ -88,9 +88,9 @@ storage_status_t storage_cfg_erase() return status; } -flashConfig_t* storage_get_cfg(void) +storage_cfg_t* storage_get_cfg(void) { - return &gflashConfig; + return &s_storage_cfg; } bool storage_file_extension_allowed(const vfs_filename_t filename) @@ -123,11 +123,11 @@ storage_status_t storage_cfg_set_filename(const char * const filename) if (filename_valid(filename)) { // Check allowed extensions (.bin, .txt, .csv, .htm, .wav) if (storage_file_extension_allowed(filename)) { - memcpy(gflashConfig.fileName, filename, 11); + memcpy(s_storage_cfg.fileName, filename, 11); } else { // If disallowed extension is requested, .bin will be used - memcpy(gflashConfig.fileName, filename, 8); - memcpy(&gflashConfig.fileName[8], "BIN", 3); + memcpy(s_storage_cfg.fileName, filename, 8); + memcpy(&s_storage_cfg.fileName[8], "BIN", 3); } } else { status = STORAGE_ERROR; @@ -139,7 +139,7 @@ storage_status_t storage_cfg_set_file_size(const uint32_t file_size) { uint32_t status = STORAGE_SUCCESS; if (file_size <= STORAGE_SIZE) { - gflashConfig.fileSize = file_size; + s_storage_cfg.fileSize = file_size; } else { status = STORAGE_ERROR; } @@ -148,7 +148,7 @@ storage_status_t storage_cfg_set_file_size(const uint32_t file_size) storage_status_t storage_cfg_set_file_visible(const bool file_visible) { - gflashConfig.fileVisible = file_visible; + s_storage_cfg.fileVisible = file_visible; return STORAGE_SUCCESS; } @@ -161,17 +161,17 @@ storage_status_t storage_cfg_set_encoding_window(const uint32_t start, const uin char* storage_cfg_get_filename(void) { - return &gflashConfig.fileName[0]; + return &s_storage_cfg.fileName[0]; } uint32_t storage_cfg_get_file_size(void) { - return gflashConfig.fileSize; + return s_storage_cfg.fileSize; } uint8_t storage_cfg_get_file_visible(void) { - return gflashConfig.fileVisible; + return s_storage_cfg.fileVisible; } uint32_t storage_cfg_get_encoding_start() From d41da9faa4bd57c2f8e618ccde833844d5946ca2 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Fri, 7 Jan 2022 22:19:42 +0000 Subject: [PATCH 604/617] microbitv2: Fully encapsulate storage_cfg inside the storage module. --- source/board/microbitv2/microbitv2.c | 23 +++++++++++++---------- source/board/microbitv2/storage.h | 10 ---------- source/board/microbitv2/storage_common.c | 15 ++++++++++----- 3 files changed, 23 insertions(+), 25 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index acde1c552..d07243cda 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -418,7 +418,6 @@ bool vfs_user_magic_file_hook(const vfs_filename_t filename, bool *do_remount) } void vfs_user_build_filesystem_hook() { - uint32_t file_size; error_t status; error_t error = vfs_mngr_get_transfer_status(); @@ -447,11 +446,14 @@ void vfs_user_build_filesystem_hook() { } } - storage_cfg_t* storage_cgf = storage_get_cfg(); - file_size = storage_cgf->fileSize + (storage_cgf->fileEncWindowEnd - storage_cgf->fileEncWindowStart); + uint32_t storage_enc_start = storage_cfg_get_encoding_start(); + uint32_t storage_enc_end = storage_cfg_get_encoding_end(); + uint32_t file_size = storage_cfg_get_file_size(); + // Each byte within the encoding window is converted into an ASCII 2 byte character + file_size += storage_enc_end - storage_enc_start; - if (storage_cgf->fileVisible) { - vfs_create_file(storage_cgf->fileName, read_file_data_txt, 0, file_size); + if (storage_cfg_get_file_visible()) { + vfs_create_file(storage_cfg_get_filename(), read_file_data_txt, 0, file_size); } } @@ -459,18 +461,19 @@ void vfs_user_build_filesystem_hook() { static uint32_t read_file_data_txt(uint32_t sector_offset, uint8_t *data, uint32_t num_sectors) { uint32_t read_address = STORAGE_ADDRESS_START + (VFS_SECTOR_SIZE * sector_offset); - storage_cfg_t* storage_cgf = storage_get_cfg(); - uint32_t encoded_data_offset = (storage_cgf->fileEncWindowEnd - storage_cgf->fileEncWindowStart); + uint32_t storage_enc_start = storage_cfg_get_encoding_start(); + uint32_t storage_enc_end = storage_cfg_get_encoding_end(); + uint32_t encoded_data_offset = (storage_enc_end - storage_enc_start); // Ignore out of bound reads if ( read_address < (STORAGE_ADDRESS_END + encoded_data_offset) ) { for (uint32_t i = 0; i < VFS_SECTOR_SIZE; i++) { - if (i + (VFS_SECTOR_SIZE * sector_offset) < storage_cgf->fileEncWindowStart) { + if (i + (VFS_SECTOR_SIZE * sector_offset) < storage_enc_start) { // If data is before encoding window, no offset is needed data[i] = *(uint8_t *) (read_address + i); - } else if(i + (VFS_SECTOR_SIZE * sector_offset) < (storage_cgf->fileEncWindowStart + encoded_data_offset * 2)) { + } else if(i + (VFS_SECTOR_SIZE * sector_offset) < (storage_enc_start + encoded_data_offset * 2)) { // Data inside encoding window needs to consider encoding window start and size - uint8_t enc_byte = *(uint8_t *) (STORAGE_ADDRESS_START + ((VFS_SECTOR_SIZE * sector_offset) + storage_cgf->fileEncWindowStart + i ) / 2); + uint8_t enc_byte = *(uint8_t *) (STORAGE_ADDRESS_START + ((VFS_SECTOR_SIZE * sector_offset) + storage_enc_start + i ) / 2); if (i % 2 == 0) { // High nibble enc_byte = 0x0F & (enc_byte >> 4); diff --git a/source/board/microbitv2/storage.h b/source/board/microbitv2/storage.h index 5c126e7df..1327d55a0 100644 --- a/source/board/microbitv2/storage.h +++ b/source/board/microbitv2/storage.h @@ -55,15 +55,6 @@ extern "C" { #define STORAGE_CFG_FILEVISIBLE false #define STORAGE_CFG_FILESIZE (STORAGE_SIZE - STORAGE_SECTOR_SIZE) -typedef __PACKED_STRUCT storage_cfg_tag { - uint32_t key; // Magic key to indicate a valid record - char fileName[STORAGE_CFG_FILENAME_SIZE]; - uint8_t fileVisible; - uint32_t fileSize; - uint32_t fileEncWindowStart; - uint32_t fileEncWindowEnd; -} storage_cfg_t; - typedef enum { STORAGE_SUCCESS = 0, STORAGE_ERROR @@ -77,7 +68,6 @@ storage_status_t storage_erase_range(uint32_t star_adr, uint32_t end_adr); storage_status_t storage_erase_all(void); storage_status_t storage_program_flash(uint32_t adr, uint32_t sz, uint8_t *buf); storage_status_t storage_erase_flash_page(uint32_t adr); -storage_cfg_t* storage_get_cfg(void); storage_status_t storage_cfg_write(void); storage_status_t storage_cfg_erase(void); storage_status_t storage_cfg_set_filename(const char * const filename); diff --git a/source/board/microbitv2/storage_common.c b/source/board/microbitv2/storage_common.c index 415266446..ea37fa385 100644 --- a/source/board/microbitv2/storage_common.c +++ b/source/board/microbitv2/storage_common.c @@ -30,6 +30,16 @@ // 'scfg' in hex - key valid #define STORAGE_CFG_KEY 0x73636667 +typedef __PACKED_STRUCT storage_cfg_tag { + uint32_t key; // Magic key to indicate a valid record + char fileName[STORAGE_CFG_FILENAME_SIZE]; + uint8_t fileVisible; + uint32_t fileSize; + uint32_t fileEncWindowStart; + uint32_t fileEncWindowEnd; +} storage_cfg_t; + + static storage_cfg_t s_storage_cfg = { .key = STORAGE_CFG_KEY, .fileName = STORAGE_CFG_FILENAME, @@ -88,11 +98,6 @@ storage_status_t storage_cfg_erase() return status; } -storage_cfg_t* storage_get_cfg(void) -{ - return &s_storage_cfg; -} - bool storage_file_extension_allowed(const vfs_filename_t filename) { const char *valid_extensions[] = { From b96433e44f001fd38b0ad24eedea0cfe25ecb859 Mon Sep 17 00:00:00 2001 From: Martin Williams Date: Wed, 12 Jan 2022 18:12:23 +0000 Subject: [PATCH 605/617] microbitv2: Replace commented out code with explanatory comments. --- source/board/microbitv2/nrf52820/power.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/source/board/microbitv2/nrf52820/power.c b/source/board/microbitv2/nrf52820/power.c index 2e08fde1e..07a313111 100644 --- a/source/board/microbitv2/nrf52820/power.c +++ b/source/board/microbitv2/nrf52820/power.c @@ -115,11 +115,8 @@ void power_sleep() static void power_before(bool systemoff) { - // TODO - wait for USB transmit to computer to finish? - /* Wait for debug console output finished. */ - // while (!(LPUART_STAT_TC_MASK & UART->STAT)) - // { - // } + // KL27 waits "for debug console output finished" by checking (LPUART_STAT_TC_MASK & UART->STAT), + // but we never get here with USB connected, so there is no need to wait uart_uninitialize(); // disables RX and TX pins @@ -190,8 +187,8 @@ static void power_after() PORT_SWD_SETUP(); uart_initialize(); - // i2c_deinitialize(); - // i2c_initialize(); + // The KL27 code calls i2c_deinitialize() and i2c_initialize() + // but tests have indicated this is not necessary here } From 8e7ddac4edaf04c3ae8390a85eb8e42e24e7dc7c Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Thu, 13 Jan 2022 18:58:48 +0000 Subject: [PATCH 606/617] microbitv2: Reset power LED & i2c state when the target is reset and run. --- source/board/microbitv2/microbitv2.c | 30 +++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index d07243cda..0169dd381 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -148,6 +148,14 @@ static void prerun_board_config(void) gpio_init_combined_int(); } +// Return reset button and LED to default state +static void reset_power_led_state() +{ + reset_pressed = 0; + power_led_sleep_state_on = PWR_LED_SLEEP_STATE_DEFAULT; + main_shutdown_state = MAIN_SHUTDOWN_WAITING; +} + // Handle the reset button behavior, this function is called in the main task every 30ms void handle_reset_button() { @@ -159,7 +167,6 @@ void handle_reset_button() if (!reset_pressed && (gpio_get_reset_btn_fwrd() || wake_from_reset)) { // Reset button pressed target_set_state(RESET_PROGRAM); - i2c_clearBuffers(); reset_pressed = 1; gpio_reset_count = 0; wake_from_reset = 0; @@ -396,10 +403,7 @@ void board_usb_sof_event(void) void board_vfs_stream_closed_hook() { - // Return reset button and LED to default state - reset_pressed = 0; - power_led_sleep_state_on = PWR_LED_SLEEP_STATE_DEFAULT; - main_shutdown_state = MAIN_SHUTDOWN_WAITING; + reset_power_led_state(); // Clear any pending I2C response i2c_clearBuffers(); @@ -513,14 +517,26 @@ uint8_t usbd_hid_no_activity(uint8_t *buf) return 0; } +// This function is called before the rest of target_set_state code, so it will +// reset the micro:bit specific features state before the target state is executed +static uint8_t target_set_state_microbit(target_state_t state) +{ + if (state == RESET_RUN) { + i2c_clearBuffers(); + reset_power_led_state(); + } + return 0; +} + const board_info_t g_board_info = { .info_version = kBoardInfoVersion, .family_id = kNordic_Nrf52_FamilyID, - .daplink_url_name = "MICROBITHTM", - .daplink_drive_name = "MICROBIT", + .daplink_url_name = "MICROBITHTM", + .daplink_drive_name = "MICROBIT", .daplink_target_url = "https://microbit.org/device/?id=@B&v=@V", .prerun_board_config = prerun_board_config, .target_cfg = &target_device_nrf52833, + .target_set_state = target_set_state_microbit, .board_vendor = "Micro:bit Educational Foundation", .board_name = "BBC micro:bit V2", }; From 0a044529a441f7086802db7478872d07cc9ee835 Mon Sep 17 00:00:00 2001 From: Martin Williams Date: Fri, 21 Jan 2022 19:48:17 +0000 Subject: [PATCH 607/617] microbitv2: Add comments to KL27/nRF52 power.c differences --- source/board/microbitv2/kl27z/power.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/source/board/microbitv2/kl27z/power.c b/source/board/microbitv2/kl27z/power.c index 5e33f88af..6bb82cf36 100644 --- a/source/board/microbitv2/kl27z/power.c +++ b/source/board/microbitv2/kl27z/power.c @@ -210,6 +210,11 @@ static void power_mode_switch(smc_power_state_t curPowerState, app_power_mode_t static void power_pre_switch_hook(smc_power_state_t originPowerState, app_power_mode_t targetMode) { + // TODO: Check if this is necessary, when we have time to test. This has always been in the V2 code. + // The comment here is misleading. The code waits for completion of the current byte tranmission, + // which is from interface to target. We could possibly move this into uart_uninitialize(), + // and consider waiting for the write buffer to empty too, but as this is our only call to uart_uninitialize() + // and we never get here with USB connected it may be unnecessary. /* Wait for debug console output finished. */ while (!(LPUART_STAT_TC_MASK & UART->STAT)) { @@ -255,6 +260,9 @@ static void power_post_switch_hook(smc_power_state_t originPowerState, app_power PORT_SetPinMux(UART_PORT, PIN_UART_TX_BIT, (port_mux_t)PIN_UART_TX_MUX_ALT); uart_initialize(); + // TODO: Check if this is necessary, when we have time to test. This has always been in the V2 code. + // It used to be at the end of board_handle_powerdown. We are not aware that this is causing a problem, + // but it seems odd if we have been woken by an I2C transaction from the target. i2c_deinitialize(); i2c_initialize(); } From d0bee856f277b9394e1850d06f05960caa88f3f5 Mon Sep 17 00:00:00 2001 From: iosabi Date: Tue, 25 Jan 2022 05:23:15 +0100 Subject: [PATCH 608/617] lpc55xx_hic: Fix circular buffer and re-apply TX performance improvements (#932) * Re-apply "LPC55xx: Improve UART TX performance." This reverts commit 08d6cb507af5e3bcdc1bf90fe338449dd039f85d. * lpc55xx_hic: Fix circ_buf asserts The assert should be checking that there are more or the same number of bytes in the circular buffer than those that are being removed, not the other way around. This was causing an erroneous assert condition in the UART interrupt handler. * lpc55xx_hic: Abort ongoing TX when changing the UART config Changing the UART config (baudrate, parity, etc) was clearing the RX and TX buffers, but if there was an ongoing TX transfer it would try to remove the bytes from the TX buffer after the transfer completes. This patch cancels any ongoing TX transfer when clearing the buffers on config changes and UART reset. --- source/daplink/circ_buf.c | 4 +-- source/hic_hal/nxp/lpc55xx/uart.c | 55 +++++++++++++++++++++---------- 2 files changed, 39 insertions(+), 20 deletions(-) diff --git a/source/daplink/circ_buf.c b/source/daplink/circ_buf.c index 437b79275..811975d7f 100644 --- a/source/daplink/circ_buf.c +++ b/source/daplink/circ_buf.c @@ -166,10 +166,10 @@ void circ_buf_pop_n(circ_buf_t *circ_buf, uint32_t n) state = cortex_int_get_and_disable(); if (circ_buf->tail >= circ_buf->head) { - util_assert(circ_buf->tail - circ_buf->head <= n); + util_assert(circ_buf->tail - circ_buf->head >= n); circ_buf->head += n; } else { - util_assert(circ_buf->tail + circ_buf->size - circ_buf->head <= n); + util_assert(circ_buf->tail + circ_buf->size - circ_buf->head >= n); circ_buf->head += n; if (circ_buf->head >= circ_buf->size) { circ_buf->head -= circ_buf->size; diff --git a/source/hic_hal/nxp/lpc55xx/uart.c b/source/hic_hal/nxp/lpc55xx/uart.c index e0e272420..77a1914e2 100644 --- a/source/hic_hal/nxp/lpc55xx/uart.c +++ b/source/hic_hal/nxp/lpc55xx/uart.c @@ -50,7 +50,6 @@ struct { volatile uint32_t tx_size; uint8_t rx; - uint8_t tx; } cb_buf; void uart_handler(uint32_t event); @@ -88,6 +87,10 @@ int32_t uart_reset(void) // disable interrupt NVIC_DisableIRQ(USART_IRQ); clear_buffers(); + if (cb_buf.tx_size != 0) { + USART_INSTANCE.Control(ARM_USART_ABORT_SEND, 0U); + cb_buf.tx_size = 0; + } // enable interrupt NVIC_EnableIRQ(USART_IRQ); @@ -160,6 +163,10 @@ int32_t uart_set_configuration(UART_Configuration *config) NVIC_DisableIRQ(USART_IRQ); clear_buffers(); + if (cb_buf.tx_size != 0) { + USART_INSTANCE.Control(ARM_USART_ABORT_SEND, 0U); + cb_buf.tx_size = 0; + } // If there was no Receive() call in progress aborting it is harmless. USART_INSTANCE.Control(ARM_USART_CONTROL_RX, 0U); @@ -193,23 +200,41 @@ int32_t uart_write_free(void) return circ_buf_count_free(&write_buffer); } +// Start a new TX transfer if there are bytes pending to be transferred on the +// write_buffer buffer. The transferred bytes are not removed from the circular +// by this function, only the event handler will remove them once the transfer +// is done. +static void uart_start_tx_transfer() { + uint32_t tx_size = 0; + const uint8_t* buf = circ_buf_peek(&write_buffer, &tx_size); + if (tx_size > BUFFER_SIZE / 4) { + // The bytes being transferred remain on the circular buffer memory + // until the transfer is done. Limiting the UART transfer size + // allows the uart_handler to clear those bytes earlier. + tx_size = BUFFER_SIZE / 4; + } + cb_buf.tx_size = tx_size; + if (tx_size) { + USART_INSTANCE.Send(buf, tx_size); + } +} + int32_t uart_write_data(uint8_t *data, uint16_t size) { if (size == 0) { return 0; } - // Disable interrupts to prevent the uart_handler from modifying the - // circular buffer at the same time. - NVIC_DisableIRQ(USART_IRQ); uint32_t cnt = circ_buf_write(&write_buffer, data, size); - if (cb_buf.tx_size == 0 && circ_buf_count_used(&write_buffer) > 0) { - // There's no pending transfer, so we need to start the process. - cb_buf.tx = circ_buf_pop(&write_buffer); - USART_INSTANCE.Send(&(cb_buf.tx), 1); - cb_buf.tx_size = 1; + if (cb_buf.tx_size == 0) { + // There's no pending transfer and the value of cb_buf.tx_size will not + // change to non-zero by the event handler once it is zero. Note that it + // is entirely possible that we transferred all the bytes we added to + // the circular buffer in this function by the time we are in this + // branch, in that case uart_start_tx_transfer() would not schedule any + // transfer. + uart_start_tx_transfer(); } - NVIC_EnableIRQ(USART_IRQ); return cnt; } @@ -233,13 +258,7 @@ void uart_handler(uint32_t event) { } if (event & ARM_USART_EVENT_SEND_COMPLETE) { - if (circ_buf_count_used(&write_buffer) > 0) { - cb_buf.tx = circ_buf_pop(&write_buffer); - USART_INSTANCE.Send(&(cb_buf.tx), 1); - } else { - // Signals that next call to uart_write_data() should start a - // transfer. - cb_buf.tx_size = 0; - } + circ_buf_pop_n(&write_buffer, cb_buf.tx_size); + uart_start_tx_transfer(); } } From 9d8b9d1b57dc6c07a6d0c2f612550089dc843d14 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Wed, 22 Dec 2021 14:09:23 +0000 Subject: [PATCH 609/617] microbitv2: Change the busy flag to be the default I2C empty TX buffer. --- source/board/microbitv2/i2c_commands.h | 5 ---- source/board/microbitv2/kl27z/i2c.c | 37 +++++++------------------- source/board/microbitv2/nrf52820/i2c.c | 19 ++++++++++--- 3 files changed, 24 insertions(+), 37 deletions(-) diff --git a/source/board/microbitv2/i2c_commands.h b/source/board/microbitv2/i2c_commands.h index 31b307494..1288cb9a3 100644 --- a/source/board/microbitv2/i2c_commands.h +++ b/source/board/microbitv2/i2c_commands.h @@ -36,12 +36,7 @@ extern "C" { #define I2C_SLAVE_HID (0x71U) #define I2C_SLAVE_FLASH (0x72U) -// Busy flag not yet implemented in nRF52 -#if defined(INTERFACE_NRF52820) -#define I2C_PROTOCOL_VERSION (0x01) -#else #define I2C_PROTOCOL_VERSION (0x02) -#endif /*! i2c command Id type enumeration */ typedef enum cmdId_tag { diff --git a/source/board/microbitv2/kl27z/i2c.c b/source/board/microbitv2/kl27z/i2c.c index e26eb2dac..573c58f12 100644 --- a/source/board/microbitv2/kl27z/i2c.c +++ b/source/board/microbitv2/kl27z/i2c.c @@ -42,9 +42,6 @@ static volatile bool g_SlaveCompletionFlag = false; static volatile bool g_SlaveRxFlag = false; static uint8_t address_match = 0; static uint32_t transferredCount = 0; -static const uint8_t g_slave_busy_error_buff[] = {gErrorResponse_c, gErrorBusy_c}; -static uint8_t g_slave_TX_buff_ready = 0; -static uint8_t g_slave_busy = 0; static i2cCallback_t pfWriteCommsCallback = NULL; static i2cCallback_t pfReadCommsCallback = NULL; @@ -58,8 +55,6 @@ static void i2c_clearTxBuffer(void); static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData) { - i2cCommand_t i2cResponse = {0}; - switch (xfer->event) { /* Address match event */ @@ -73,15 +68,8 @@ static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void /* Transmit request */ case kI2C_SlaveTransmitEvent: /* Update information for transmit process */ - // Send response if the buffer is ready, otherwise send busy error - if (g_slave_TX_buff_ready) { - xfer->data = g_slave_TX_buff; - xfer->dataSize = I2C_DATA_LENGTH; - } else { - xfer->data = (uint8_t*)g_slave_busy_error_buff; - xfer->dataSize = sizeof(g_slave_busy_error_buff); - g_slave_busy = 1; - } + xfer->data = g_slave_TX_buff; + xfer->dataSize = I2C_DATA_LENGTH; g_SlaveRxFlag = false; break; @@ -113,17 +101,7 @@ static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void // Ignore NOP cmd in I2C Write if (!(g_SlaveRxFlag && g_slave_RX_buff[0] == gNopCmd_c)) { // Only process events if the busy error was not read - if (!g_slave_busy) { - main_board_event(); - } else { - g_slave_busy = 0; - } - } - - // Buffer with response is not ready after an I2C Write inside the IRQ - // It will be ready when the task attends the I2C event - if(g_SlaveRxFlag) { - g_slave_TX_buff_ready = 0; + main_board_event(); } i2c_allow_sleep = false; @@ -137,7 +115,6 @@ static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void // Hook function executed in the main task void board_custom_event() { if (g_SlaveRxFlag) { - i2c_clearTxBuffer(); if (pfWriteCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { pfWriteCommsCallback(&g_slave_RX_buff[0], transferredCount); } @@ -151,6 +128,7 @@ void board_custom_event() { if (pfReadFlashCallback && address_match == I2C_SLAVE_FLASH) { pfReadFlashCallback(&g_slave_TX_buff[0], transferredCount); } + i2c_clearTxBuffer(); } i2c_allow_sleep = true; } @@ -261,6 +239,11 @@ void i2c_clearBuffers(void) void i2c_clearTxBuffer(void) { memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); + // Set the buffer with the "busy flag" + // TODO: This can be later removed and updated in CODAL to interpret 0x00 + // as the busy flag + g_slave_TX_buff[0] = gErrorResponse_c; + g_slave_TX_buff[1] = gErrorBusy_c; } void i2c_fillBuffer (uint8_t* data, uint32_t position, uint32_t size) { @@ -271,13 +254,11 @@ void i2c_fillBuffer (uint8_t* data, uint32_t position, uint32_t size) { for (uint32_t i = 0; i < size; i++) { g_slave_TX_buff[position + i] = data[i]; } - g_slave_TX_buff_ready = 1; } void i2c_fillBufferHead(uint8_t data) { g_slave_TX_buff[0] = data; - g_slave_TX_buff_ready = 1; } bool i2c_canSleep() diff --git a/source/board/microbitv2/nrf52820/i2c.c b/source/board/microbitv2/nrf52820/i2c.c index ca57f27ff..7470bd32a 100644 --- a/source/board/microbitv2/nrf52820/i2c.c +++ b/source/board/microbitv2/nrf52820/i2c.c @@ -64,6 +64,8 @@ static callbackToExecute_t callbackToExecute = { static uint8_t i2c_wake_timeout = 0; static bool i2c_allow_sleep = true; +static void i2c_clearTxBuffer(void); + static void i2c_scheduleCallback(i2cCallback_t callback, uint8_t* pData, uint8_t size) { @@ -97,7 +99,7 @@ void board_custom_event() if ((pfReadCommsCallback != NULL && evtCallback == pfReadCommsCallback) || (pfReadFlashCallback != NULL && evtCallback == pfReadFlashCallback)) { debug_i2c_data((uint8_t *)"[clrTx]\n", 8); - memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); + i2c_clearTxBuffer(); } } @@ -225,7 +227,7 @@ i2c_status_t i2c_registerReadCallback(i2cCallback_t readCallback, uint8_t slaveA void i2c_clearBuffers() { - memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); + i2c_clearTxBuffer(); memset(&g_slave_RX_buff, 0, sizeof(g_slave_RX_buff)); callbackToExecute.pfCallback = NULL; callbackToExecute.pData = NULL; @@ -233,13 +235,22 @@ void i2c_clearBuffers() i2c_allow_sleep = true; } +void i2c_clearTxBuffer() +{ + memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); + // Set the buffer with the "busy flag" + // TODO: This can be later removed and updated in CODAL to interpret 0x00 + // as the busy flag + g_slave_TX_buff[0] = gErrorResponse_c; + g_slave_TX_buff[1] = gErrorBusy_c; +} + void i2c_fillBuffer(uint8_t* data, uint32_t position, uint32_t size) { if ((position + size) > I2C_DATA_LENGTH) { return; } - // TODO: Taken from KL27 code, replace with memcpy? - for (uint32_t i = 0; i < size; i++) { + for (uint32_t i = 0; i < size; i++) { g_slave_TX_buff[position + i] = data[i]; } i2c_allow_sleep = false; From cf164f6a71a2ddaa78e6f1cc4fae5845bee4b05e Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Tue, 4 Jan 2022 17:41:05 +0000 Subject: [PATCH 610/617] microbitv2: Convert i2c_clearBuffers() into i2c_clearState(). Also use memcpy in i2c_clearTxBuffer(). --- source/board/microbitv2/i2c.h | 2 +- source/board/microbitv2/kl27z/i2c.c | 19 ++++++++++++------- source/board/microbitv2/microbitv2.c | 4 ++-- source/board/microbitv2/nrf52820/i2c.c | 9 ++++----- 4 files changed, 19 insertions(+), 15 deletions(-) diff --git a/source/board/microbitv2/i2c.h b/source/board/microbitv2/i2c.h index 2da0620ab..46af207c8 100644 --- a/source/board/microbitv2/i2c.h +++ b/source/board/microbitv2/i2c.h @@ -45,7 +45,7 @@ void i2c_initialize(void); void i2c_deinitialize(void); i2c_status_t i2c_registerWriteCallback(i2cCallback_t writeCallback, uint8_t slaveAddress); i2c_status_t i2c_registerReadCallback(i2cCallback_t readCallback, uint8_t slaveAddress); -void i2c_clearBuffers(void); +void i2c_clearState(void); void i2c_fillBuffer(uint8_t* data, uint32_t position, uint32_t size); /* A more efficient way to fill the first byte for simple transactions. */ void i2c_fillBufferHead(uint8_t data); diff --git a/source/board/microbitv2/kl27z/i2c.c b/source/board/microbitv2/kl27z/i2c.c index 573c58f12..a0d00c556 100644 --- a/source/board/microbitv2/kl27z/i2c.c +++ b/source/board/microbitv2/kl27z/i2c.c @@ -165,7 +165,7 @@ void i2c_initialize() { i2c_init_pins(); - i2c_clearBuffers(); + i2c_clearState(); I2C_SlaveGetDefaultConfig(&slaveConfig); @@ -230,10 +230,16 @@ i2c_status_t i2c_registerReadCallback(i2cCallback_t readCallback, uint8_t slaveA return status; } -void i2c_clearBuffers(void) +void i2c_clearState(void) { - memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); + i2c_clearTxBuffer(); memset(&g_slave_RX_buff, 0, sizeof(g_slave_RX_buff)); + g_SlaveCompletionFlag = false; + g_SlaveRxFlag = false; + address_match = 0; + transferredCount = 0; + i2c_wake_timeout = 0; + i2c_allow_sleep = true; } void i2c_clearTxBuffer(void) @@ -250,15 +256,14 @@ void i2c_fillBuffer (uint8_t* data, uint32_t position, uint32_t size) { if ((position + size) > I2C_DATA_LENGTH) { return; } - - for (uint32_t i = 0; i < size; i++) { - g_slave_TX_buff[position + i] = data[i]; - } + memcpy(g_slave_TX_buff + position, data, size); + i2c_allow_sleep = false; } void i2c_fillBufferHead(uint8_t data) { g_slave_TX_buff[0] = data; + i2c_allow_sleep = false; } bool i2c_canSleep() diff --git a/source/board/microbitv2/microbitv2.c b/source/board/microbitv2/microbitv2.c index 0169dd381..15bd660c7 100644 --- a/source/board/microbitv2/microbitv2.c +++ b/source/board/microbitv2/microbitv2.c @@ -406,7 +406,7 @@ void board_vfs_stream_closed_hook() reset_power_led_state(); // Clear any pending I2C response - i2c_clearBuffers(); + i2c_clearState(); // Release COMBINED_SENSOR_INT gpio_disable_combined_int(); @@ -522,7 +522,7 @@ uint8_t usbd_hid_no_activity(uint8_t *buf) static uint8_t target_set_state_microbit(target_state_t state) { if (state == RESET_RUN) { - i2c_clearBuffers(); + i2c_clearState(); reset_power_led_state(); } return 0; diff --git a/source/board/microbitv2/nrf52820/i2c.c b/source/board/microbitv2/nrf52820/i2c.c index 7470bd32a..76d5ad4a2 100644 --- a/source/board/microbitv2/nrf52820/i2c.c +++ b/source/board/microbitv2/nrf52820/i2c.c @@ -171,7 +171,7 @@ static void i2c_signalEvent(uint32_t event) { void i2c_initialize() { - i2c_clearBuffers(); + i2c_clearState(); // I2C addresses configured via default values from RTE_Device.h I2Cdrv->Initialize(i2c_signalEvent); @@ -225,13 +225,14 @@ i2c_status_t i2c_registerReadCallback(i2cCallback_t readCallback, uint8_t slaveA return status; } -void i2c_clearBuffers() +void i2c_clearState() { i2c_clearTxBuffer(); memset(&g_slave_RX_buff, 0, sizeof(g_slave_RX_buff)); callbackToExecute.pfCallback = NULL; callbackToExecute.pData = NULL; callbackToExecute.size = 0; + i2c_wake_timeout = 0; i2c_allow_sleep = true; } @@ -250,9 +251,7 @@ void i2c_fillBuffer(uint8_t* data, uint32_t position, uint32_t size) if ((position + size) > I2C_DATA_LENGTH) { return; } - for (uint32_t i = 0; i < size; i++) { - g_slave_TX_buff[position + i] = data[i]; - } + memcpy(g_slave_TX_buff + position, data, size); i2c_allow_sleep = false; } From 000bc1d7d047ec03a355905967cb10fc3fe3610d Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Thu, 27 Jan 2022 00:03:06 +0000 Subject: [PATCH 611/617] microbitv2: Move the I2C TX callback back to inside interrupt. As soon as target was done I2C reading from DAPLink it was getting ready the next messsage. Sometime it would send the next I2C write before the TX callback had time to run in the RTOS main thread. --- source/board/microbitv2/kl27z/i2c.c | 44 ++++++++++++------ source/board/microbitv2/nrf52820/i2c.c | 63 ++++++++++++++------------ 2 files changed, 63 insertions(+), 44 deletions(-) diff --git a/source/board/microbitv2/kl27z/i2c.c b/source/board/microbitv2/kl27z/i2c.c index a0d00c556..da7fb667a 100644 --- a/source/board/microbitv2/kl27z/i2c.c +++ b/source/board/microbitv2/kl27z/i2c.c @@ -34,6 +34,7 @@ #define I2C_SLAVE_CLK_SRC I2C1_CLK_SRC #define I2C_SLAVE_CLK_FREQ CLOCK_GetFreq(I2C1_CLK_SRC) +static uint16_t g_slave_TX_i = 0; static uint8_t g_slave_TX_buff[I2C_DATA_LENGTH]; static uint8_t g_slave_RX_buff[I2C_DATA_LENGTH]; @@ -52,6 +53,7 @@ static uint8_t i2c_wake_timeout = 0; static bool i2c_allow_sleep = true; static void i2c_clearTxBuffer(void); +static void i2c_scheduleCallback(void); static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData) { @@ -95,16 +97,15 @@ static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void xfer->dataSize = 0; transferredCount = xfer->transferredCount; + i2c_allow_sleep = false; + // Default driver couldn't differentiate between RX or TX completion // Check flag set in kI2C_SlaveReceiveEvent - // Ignore NOP cmd in I2C Write if (!(g_SlaveRxFlag && g_slave_RX_buff[0] == gNopCmd_c)) { // Only process events if the busy error was not read - main_board_event(); + i2c_scheduleCallback(); } - - i2c_allow_sleep = false; break; default: @@ -112,16 +113,13 @@ static void i2c_slave_callback(I2C_Type *base, i2c_slave_transfer_t *xfer, void break; } } -// Hook function executed in the main task -void board_custom_event() { + +static void i2c_scheduleCallback() { if (g_SlaveRxFlag) { - if (pfWriteCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { - pfWriteCommsCallback(&g_slave_RX_buff[0], transferredCount); - } - if (pfWriteFlashCallback && address_match == I2C_SLAVE_FLASH) { - pfWriteFlashCallback(&g_slave_RX_buff[0], transferredCount); - } + // Raise an RTOS event to run the heavier I2C RX callback in main task + main_board_event(); } else { + // Run the I2C TX callback in the interrupt context if (pfReadCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { pfReadCommsCallback(&g_slave_TX_buff[0], transferredCount); } @@ -129,6 +127,17 @@ void board_custom_event() { pfReadFlashCallback(&g_slave_TX_buff[0], transferredCount); } i2c_clearTxBuffer(); + i2c_allow_sleep = true; + } +} + +// Hook function executed in the main task +void board_custom_event() { + if (pfWriteCommsCallback && address_match == I2C_SLAVE_NRF_KL_COMMS) { + pfWriteCommsCallback(&g_slave_RX_buff[0], transferredCount); + } + if (pfWriteFlashCallback && address_match == I2C_SLAVE_FLASH) { + pfWriteFlashCallback(&g_slave_RX_buff[0], transferredCount); } i2c_allow_sleep = true; } @@ -244,10 +253,9 @@ void i2c_clearState(void) void i2c_clearTxBuffer(void) { - memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); + memset(&g_slave_TX_buff, 0, g_slave_TX_i); + g_slave_TX_i = 0; // Set the buffer with the "busy flag" - // TODO: This can be later removed and updated in CODAL to interpret 0x00 - // as the busy flag g_slave_TX_buff[0] = gErrorResponse_c; g_slave_TX_buff[1] = gErrorBusy_c; } @@ -257,12 +265,18 @@ void i2c_fillBuffer (uint8_t* data, uint32_t position, uint32_t size) { return; } memcpy(g_slave_TX_buff + position, data, size); + if (position + size > g_slave_TX_i) { + g_slave_TX_i = position + size; + } i2c_allow_sleep = false; } void i2c_fillBufferHead(uint8_t data) { g_slave_TX_buff[0] = data; + if (0 == g_slave_TX_i) { + g_slave_TX_i = 1; + } i2c_allow_sleep = false; } diff --git a/source/board/microbitv2/nrf52820/i2c.c b/source/board/microbitv2/nrf52820/i2c.c index 76d5ad4a2..afb863982 100644 --- a/source/board/microbitv2/nrf52820/i2c.c +++ b/source/board/microbitv2/nrf52820/i2c.c @@ -33,17 +33,23 @@ #if DEBUG_I2C #include "daplink_debug.h" -#define debug_i2c_printf debug_msg -#define debug_i2c_data debug_data +#define debug_i2c_printf debug_msg +#define debug_i2c_data debug_data +#define debug_i2c_array(a, i) do { \ + for (int x = 0; x < i; x++) debug_msg("%02x ", a[x]); \ + debug_data((uint8_t *)"\n", 1); \ + } while(0) #else #define debug_i2c_printf(...) #define debug_i2c_data(...) +#define debug_i2c_array(...) #endif extern ARM_DRIVER_I2C Driver_I2C0; static ARM_DRIVER_I2C *I2Cdrv = &Driver_I2C0; static uint8_t g_slave_TX_buff[I2C_DATA_LENGTH] = { 0 }; +static uint16_t g_slave_TX_i = 0; static uint8_t g_slave_RX_buff[I2C_DATA_LENGTH] = { 0 }; static i2cCallback_t pfWriteCommsCallback = NULL; @@ -69,38 +75,35 @@ static void i2c_clearTxBuffer(void); static void i2c_scheduleCallback(i2cCallback_t callback, uint8_t* pData, uint8_t size) { - callbackToExecute.pfCallback = callback; - callbackToExecute.pData = pData; - callbackToExecute.size = size; - - // Raise event so that `board_custom_event()` gets called in the main task - main_board_event(); + if ((callback == pfReadCommsCallback) || (callback == pfReadFlashCallback)) { + // Run the I2C TX callback in the interrupt context + debug_i2c_data((uint8_t *)"[cbTx]\n", 7); + callback(pData, size); + i2c_clearTxBuffer(); + } else { + // Raise an RTOS event to run the heavier I2C RX callback in main task + callbackToExecute.pfCallback = callback; + callbackToExecute.pData = pData; + callbackToExecute.size = size; + i2c_allow_sleep = false; + main_board_event(); + } } // Hook function executed in the main task void board_custom_event() { - i2cCallback_t evtCallback = NULL; - if (callbackToExecute.pfCallback != NULL) { - debug_i2c_data((uint8_t *)"[clbk]\n", 7); + debug_i2c_data((uint8_t *)"[cbRx]\n", 7); callbackToExecute.pfCallback(callbackToExecute.pData, callbackToExecute.size); // Clear the callback data - evtCallback = callbackToExecute.pfCallback; // Save for later callbackToExecute.pfCallback = NULL; callbackToExecute.pData = NULL; callbackToExecute.size = 0; i2c_allow_sleep = true; } - - // Clear TX buffer after a TX callback - if ((pfReadCommsCallback != NULL && evtCallback == pfReadCommsCallback) || - (pfReadFlashCallback != NULL && evtCallback == pfReadFlashCallback)) { - debug_i2c_data((uint8_t *)"[clrTx]\n", 8); - i2c_clearTxBuffer(); - } } static void i2c_signalEvent(uint32_t event) { @@ -118,13 +121,11 @@ static void i2c_signalEvent(uint32_t event) { if (event & ARM_I2C_EVENT_TRANSFER_DONE) { // debug_i2c_data((uint8_t *)"[d", 2); - i2c_allow_sleep = false; if (prev_event & ARM_I2C_EVENT_SLAVE_RECEIVE) { int32_t data_count = I2Cdrv->GetDataCount(); - debug_i2c_printf("[rx][%d] ", data_count); - // for (int i = 0; i < data_count; i++) debug_i2c_printf("%02x ", g_slave_RX_buff[i]); - debug_i2c_data((uint8_t *)"\n", 1); + debug_i2c_printf("[R0%x]\n", g_slave_RX_buff[0]); + // debug_i2c_array(g_slave_RX_buff, data_count); // Ignore NOP commands and 0 length transmissions if ((data_count != 0) && (g_slave_RX_buff[0] != gNopCmd_c)) { @@ -136,9 +137,8 @@ static void i2c_signalEvent(uint32_t event) { } } else if (prev_event & ARM_I2C_EVENT_SLAVE_TRANSMIT) { int32_t data_count = I2Cdrv->GetDataCount(); - debug_i2c_printf("[tx][%d] ", data_count); - // for (int i = 0; i < 5; i++) debug_i2c_printf("%02x ", g_slave_TX_buff[i]); - debug_i2c_data((uint8_t *)"\n", 1); + debug_i2c_printf("[T0%x]\n", g_slave_TX_buff[0]); + // debug_i2c_array(g_slave_TX_buff, 5); if (event & EXTENSION_I2C_EVENT_SLAVE_ADDR_0) { i2c_scheduleCallback(pfReadCommsCallback, &g_slave_TX_buff[0], data_count); @@ -238,10 +238,9 @@ void i2c_clearState() void i2c_clearTxBuffer() { - memset(&g_slave_TX_buff, 0, sizeof(g_slave_TX_buff)); + memset(&g_slave_TX_buff, 0, g_slave_TX_i); + g_slave_TX_i = 0; // Set the buffer with the "busy flag" - // TODO: This can be later removed and updated in CODAL to interpret 0x00 - // as the busy flag g_slave_TX_buff[0] = gErrorResponse_c; g_slave_TX_buff[1] = gErrorBusy_c; } @@ -252,12 +251,18 @@ void i2c_fillBuffer(uint8_t* data, uint32_t position, uint32_t size) return; } memcpy(g_slave_TX_buff + position, data, size); + if (position + size > g_slave_TX_i) { + g_slave_TX_i = position + size; + } i2c_allow_sleep = false; } void i2c_fillBufferHead(uint8_t data) { g_slave_TX_buff[0] = data; + if (0 == g_slave_TX_i) { + g_slave_TX_i = 1; + } i2c_allow_sleep = false; } From c9db11f6e7a5c03bbb922e1bdf53e702876a00d5 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Thu, 27 Jan 2022 00:20:34 +0000 Subject: [PATCH 612/617] microbitv2: Move when to change internal state for shutdown requested. The state should be changed when the target request DAPLink to go into MB_POWER_DOWN mode, not when the reset button has been long pressed. --- source/board/microbitv2/i2c_commands.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/source/board/microbitv2/i2c_commands.c b/source/board/microbitv2/i2c_commands.c index 532ce7e84..0e227e188 100644 --- a/source/board/microbitv2/i2c_commands.c +++ b/source/board/microbitv2/i2c_commands.c @@ -123,6 +123,7 @@ static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { if (pI2cCommand->cmdData.writeReqCmd.dataSize == 1) { if (pI2cCommand->cmdData.writeReqCmd.data[0] == MB_POWER_DOWN) { interface_power_mode = MB_POWER_DOWN; + main_shutdown_state = MAIN_SHUTDOWN_REQUESTED; i2cResponse.cmdId = gWriteResponse_c; i2cResponse.cmdData.writeRspCmd.propertyId = pI2cCommand->cmdData.writeReqCmd.propertyId; } else { @@ -191,18 +192,6 @@ static void i2c_write_comms_callback(uint8_t* pData, uint8_t size) { } static void i2c_read_comms_callback(uint8_t* pData, uint8_t size) { - i2cCommand_t* pI2cCommand = (i2cCommand_t*) pData; - - switch (pI2cCommand->cmdId) { - case gWriteResponse_c: - switch (pI2cCommand->cmdData.writeRspCmd.propertyId) { - case gPowerMode_c: - main_shutdown_state = MAIN_SHUTDOWN_REQUESTED; - break; - } - break; - } - // Release COMBINED_SENSOR_INT gpio_disable_combined_int(); } From d917f915b2743bdfdb340b2afa665ffb028c9e9e Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Thu, 27 Jan 2022 23:19:28 +0000 Subject: [PATCH 613/617] microbitv2: Ensure DMA memory and data written to flash is aligned. Nordic EasyDMA needs the data to be 32-bit aligned. The KL27 code to write to flash asserts also for alignment, so ensure the buffers sent to storage_program_flash() are aligned too. --- source/board/microbitv2/kl27z/i2c.c | 4 ++-- source/board/microbitv2/nrf52820/i2c.c | 4 ++-- source/board/microbitv2/storage_common.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/source/board/microbitv2/kl27z/i2c.c b/source/board/microbitv2/kl27z/i2c.c index da7fb667a..7ca3daeba 100644 --- a/source/board/microbitv2/kl27z/i2c.c +++ b/source/board/microbitv2/kl27z/i2c.c @@ -35,8 +35,8 @@ #define I2C_SLAVE_CLK_FREQ CLOCK_GetFreq(I2C1_CLK_SRC) static uint16_t g_slave_TX_i = 0; -static uint8_t g_slave_TX_buff[I2C_DATA_LENGTH]; -static uint8_t g_slave_RX_buff[I2C_DATA_LENGTH]; +static uint8_t __ALIGNED(4) g_slave_TX_buff[I2C_DATA_LENGTH]; +static uint8_t __ALIGNED(4) g_slave_RX_buff[I2C_DATA_LENGTH]; i2c_slave_handle_t g_s_handle; static volatile bool g_SlaveCompletionFlag = false; diff --git a/source/board/microbitv2/nrf52820/i2c.c b/source/board/microbitv2/nrf52820/i2c.c index afb863982..0ee8ff925 100644 --- a/source/board/microbitv2/nrf52820/i2c.c +++ b/source/board/microbitv2/nrf52820/i2c.c @@ -48,9 +48,9 @@ extern ARM_DRIVER_I2C Driver_I2C0; static ARM_DRIVER_I2C *I2Cdrv = &Driver_I2C0; -static uint8_t g_slave_TX_buff[I2C_DATA_LENGTH] = { 0 }; static uint16_t g_slave_TX_i = 0; -static uint8_t g_slave_RX_buff[I2C_DATA_LENGTH] = { 0 }; +static uint8_t __ALIGNED(4) g_slave_TX_buff[I2C_DATA_LENGTH] = { 0 }; +static uint8_t __ALIGNED(4) g_slave_RX_buff[I2C_DATA_LENGTH] = { 0 }; static i2cCallback_t pfWriteCommsCallback = NULL; static i2cCallback_t pfReadCommsCallback = NULL; diff --git a/source/board/microbitv2/storage_common.c b/source/board/microbitv2/storage_common.c index ea37fa385..bd7dd6d06 100644 --- a/source/board/microbitv2/storage_common.c +++ b/source/board/microbitv2/storage_common.c @@ -40,7 +40,7 @@ typedef __PACKED_STRUCT storage_cfg_tag { } storage_cfg_t; -static storage_cfg_t s_storage_cfg = { +static storage_cfg_t __ALIGNED(4) s_storage_cfg = { .key = STORAGE_CFG_KEY, .fileName = STORAGE_CFG_FILENAME, .fileVisible = STORAGE_CFG_FILEVISIBLE, From 2f4b219fe14e447b176064c179caf4a6cc1d4950 Mon Sep 17 00:00:00 2001 From: microbit-carlos Date: Fri, 28 Jan 2022 16:14:12 +0000 Subject: [PATCH 614/617] nrf52820_hic: Retur error for unimplemented I2C_Control operations. --- source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.c b/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.c index 4954684b5..f3925fe38 100644 --- a/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.c +++ b/source/hic_hal/nordic/nrf52820/I2C_Slave_nRF52820.c @@ -417,9 +417,10 @@ static int32_t I2C_Control (uint32_t control, uint32_t arg, I2C_RESOURCES *i2c) case ARM_I2C_ABORT_TRANSFER: break; - default: return ARM_DRIVER_ERROR; + default: + break; } - return ARM_DRIVER_OK; + return ret; } From beb2784f212dbb2491456f97df21ec2ca161481f Mon Sep 17 00:00:00 2001 From: Carlos Pereira Atencio Date: Sat, 5 Feb 2022 05:36:51 +0100 Subject: [PATCH 615/617] Fix issue flashing hex files with 32 bytes data records. (#936) When a 32 bytes data (or custom data) record is processed and the `HEX_PARSE_UNALIGNED` status is triggered, the `line.buffer` index variable `idx` is set to a value one-too-large and causes a write out-of-bounds, which can corrupt other data placed right after it in RAM. Increasing the hex_blob pointer before exiting the function ensures the start of new record is processed before the `line.buf[idx] |= ctoh((uint8_t)(*hex_blob)) & 0xf;`, which resets `idx` back to zero. More info in PR https://github.com/ARMmbed/DAPLink/pull/936 --- source/daplink/drag-n-drop/intelhex.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/source/daplink/drag-n-drop/intelhex.c b/source/daplink/drag-n-drop/intelhex.c index 5a20ef2d4..3d506e4f4 100644 --- a/source/daplink/drag-n-drop/intelhex.c +++ b/source/daplink/drag-n-drop/intelhex.c @@ -37,9 +37,9 @@ enum hex_record_t { }; typedef union hex_line_t hex_line_t; -union __attribute__((packed)) hex_line_t { +__PACKED_UNION hex_line_t { uint8_t buf[0x25]; - struct __attribute__((packed)) { + __PACKED_STRUCT { uint8_t byte_count; uint16_t address; uint8_t record_type; @@ -176,6 +176,9 @@ hexfile_parse_status_t parse_hex_blob(const uint8_t *hex_blob, const uint32_t he if (((next_address_to_write & 0xffff0000) | line.address) != next_address_to_write) { load_unaligned_record = 1; status = HEX_PARSE_UNALIGNED; + // Function will be executed again and will start by finishing to process this record by + // adding the this line into bin_buf, so the 1st loop iteration should be the next blob byte + hex_blob++; goto hex_parser_exit; } else { // This should be superfluous but it is necessary for GCC From 7cb31d4b9539373b028fbf0cbdeed77253c19ecc Mon Sep 17 00:00:00 2001 From: Gerardo Rodriguez Date: Fri, 4 Feb 2022 22:37:08 -0600 Subject: [PATCH 616/617] microbitv2: Reduce target SWD clock to 6 MHz (#937) --- records/board/microbitv2.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/records/board/microbitv2.yaml b/records/board/microbitv2.yaml index bd22e9fe4..28cba23dd 100644 --- a/records/board/microbitv2.yaml +++ b/records/board/microbitv2.yaml @@ -5,8 +5,7 @@ common: - MSC_LED_DEF=GPIO_LED_ON - USB_PROD_STR="BBC micro:bit CMSIS-DAP" - IO_CONFIG_OVERRIDE - - DELAY_FAST_CYCLES=2U # Fast delay needed to reach 8MHz SWD clock speed - - DAP_DEFAULT_SWJ_CLOCK=8000000 + - DAP_DEFAULT_SWJ_CLOCK=6000000 # Results in one slow delay of 3 cycles - BOARD_USB_BMAXPOWER=0x96 - CDC_ACM_DEFAULT_BAUDRATE=115200 includes: From eb7677b383475e41d894996a8872bc18717337f4 Mon Sep 17 00:00:00 2001 From: Mathias Brossard Date: Fri, 4 Feb 2022 22:48:00 -0600 Subject: [PATCH 617/617] test: additional resilience in the MSD tests + remove 2 tests from quick suite --- test/tests/test_msd.py | 43 ++++++++++++++++++++++++++++-------------- 1 file changed, 29 insertions(+), 14 deletions(-) diff --git a/test/tests/test_msd.py b/test/tests/test_msd.py index 677f9dcf9..62b2702b9 100644 --- a/test/tests/test_msd.py +++ b/test/tests/test_msd.py @@ -151,7 +151,18 @@ def add_mock_dirs_after_load(self, dir_list): def _check_data_correct(self, expected_data, _): """Return True if the actual data written matches the expected""" data_len = len(expected_data) - data_loaded = self.board.read_target_memory(self._start, data_len) + for retry_count in range(self.RETRY_COUNT): + if retry_count > 0: + test_info.info('Previous attempts %s' % retry_count) + try: + data_loaded = self.board.read_target_memory(self._start, data_len) + except: + time.sleep(self.DELAY_BEFORE_RETRY_S) + continue + break + else: + raise Exception("read_target_memory() failed after %i retries" % self.RETRY_COUNT) + return _same(expected_data, data_loaded) def run(self): @@ -296,6 +307,8 @@ def _run(self, test_info): assert not failure_expected assert not failure_occured + time.sleep(1) + # If there is expected data then compare if self._expected_data: if self._check_data_correct(self._expected_data, test_info): @@ -378,11 +391,12 @@ def test_mass_storage(workspace, parent_test, quick=False): # Test loading a blank binary - this image should cause a timeout # since it doesn't have a valid vector table - test = MassStorageTester(board, test_info, "Load blank binary") - test.set_programming_data(blank_bin_contents, 'image.bin') - test.set_expected_failure_msg("The transfer timed out.", "transient, user") - test.set_expected_data(None, start) - test.run() + if not quick: + test = MassStorageTester(board, test_info, "Load blank binary") + test.set_programming_data(blank_bin_contents, 'image.bin') + test.set_expected_failure_msg("The transfer timed out.", "transient, user") + test.set_expected_data(None, start) + test.run() # Test loading a blank binary with a vector table but padded with 0xFF. # A blank image can lock some devices. @@ -397,14 +411,15 @@ def test_mass_storage(workspace, parent_test, quick=False): test.run() # Test a normal load with dummy files created beforehand - test = MassStorageTester(board, test_info, "Extra Files") - test.set_programming_data(hex_file_contents, 'image.hex') - test.add_mock_dirs(MOCK_DIR_LIST) - test.add_mock_files(MOCK_FILE_LIST) - test.add_mock_dirs_after_load(MOCK_DIR_LIST_AFTER) - test.add_mock_files_after_load(MOCK_FILE_LIST_AFTER) - test.set_expected_data(bin_file_contents, start) - test.run() + if not quick: + test = MassStorageTester(board, test_info, "Extra Files") + test.set_programming_data(hex_file_contents, 'image.hex') + test.add_mock_dirs(MOCK_DIR_LIST) + test.add_mock_files(MOCK_FILE_LIST) + test.add_mock_dirs_after_load(MOCK_DIR_LIST_AFTER) + test.add_mock_files_after_load(MOCK_FILE_LIST_AFTER) + test.set_expected_data(bin_file_contents, start) + test.run() # Note - it is not unexpected for an "Extra Files" test to fail # when a binary file is loaded, since there is no way to # tell where the end of the file is.